From skannan at codeaurora.org  Wed May  1 00:42:08 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 30 Apr 2013 21:42:08 -0700
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
Message-ID: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>

Without this patch, the following race conditions are possible.

Race condition 1:
* clk-A has two parents - clk-X and clk-Y.
* All three are disabled and clk-X is current parent.
* Thread A: clk_set_parent(clk-A, clk-Y).
* Thread A: <snip execution flow>
* Thread A: Grabs enable lock.
* Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
* Thread A: Updates clk-A SW parent to clk-Y
* Thread A: Releases enable lock.
* Thread B: clk_enable(clk-A).
* Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.

clk-A is now enabled in software, but not clocking in hardware since the
hardware parent is still clk-X.

The only way to avoid race conditions between clk_set_parent() and
clk_enable/disable() is to ensure that clk_enable/disable() calls don't
require changes to hardware enable state between changes to software clock
topology and hardware clock topology.

There are options to achieve the above:
1. Grab the enable lock before changing software/hardware topology and
   release it afterwards.
2. Keep the clock enabled for the duration of software/hardware topology
   change so that any additional enable/disable calls don't try to change
   the hardware state. Once the topology change is complete, the clock can
   be put back in its original enable state.

Option (1) is not an acceptable solution since the set_parent() ops might
need to sleep.

Therefore, this patch implements option (2).

This patch doesn't violate any API semantics. clk_disable() doesn't
guarantee that the clock is actually disabled. So, no clients of a clock
can assume that a clock is disabled after their last call to clk_disable().
So, enabling the clock during a parent change is not a violation of any API
semantics.

This also has the nice side effect of simplifying the error handling code.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
It's been a while since I submitted a patch. So, apologies if I'm cc'ing
people who no longer care about the state of the common clock framework.

 drivers/clk/clk.c |   72 +++++++++++++++++++++++-----------------------------
 1 files changed, 32 insertions(+), 40 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 934cfd1..fe4055f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1377,67 +1377,59 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
 	unsigned long flags;
 	int ret = 0;
 	struct clk *old_parent = clk->parent;
-	bool migrated_enable = false;
 
-	/* migrate prepare */
-	if (clk->prepare_count)
+	/*
+	 * Migrate prepare state between parents and prevent race with
+	 * clk_enable().
+	 *
+	 * If the clock is not prepared, then a race with
+	 * clk_enable/disable() is impossible since we already have the
+	 * prepare lock (future calls to clk_enable() need to be preceded by
+	 * a clk_prepare()).
+	 *
+	 * If the clock is prepared, migrate the prepared state to the new
+	 * parent and also protect against a race with clk_enable() by
+	 * forcing the clock and the new parent on.  This ensures that all
+	 * future calls to clk_enable() are practically NOPs with respect to
+	 * hardware and software states.
+	 */
+	if (clk->prepare_count) {
 		__clk_prepare(parent);
-
-	flags = clk_enable_lock();
-
-	/* migrate enable */
-	if (clk->enable_count) {
-		__clk_enable(parent);
-		migrated_enable = true;
+		clk_enable(parent);
+		clk_enable(clk);
 	}
 
 	/* update the clk tree topology */
+	flags = clk_enable_lock();
 	clk_reparent(clk, parent);
-
 	clk_enable_unlock(flags);
 
 	/* change clock input source */
 	if (parent && clk->ops->set_parent)
 		ret = clk->ops->set_parent(clk->hw, p_index);
-
 	if (ret) {
-		/*
-		 * The error handling is tricky due to that we need to release
-		 * the spinlock while issuing the .set_parent callback. This
-		 * means the new parent might have been enabled/disabled in
-		 * between, which must be considered when doing rollback.
-		 */
-		flags = clk_enable_lock();
 
+		flags = clk_enable_lock();
 		clk_reparent(clk, old_parent);
-
-		if (migrated_enable && clk->enable_count) {
-			__clk_disable(parent);
-		} else if (migrated_enable && (clk->enable_count == 0)) {
-			__clk_disable(old_parent);
-		} else if (!migrated_enable && clk->enable_count) {
-			__clk_disable(parent);
-			__clk_enable(old_parent);
-		}
-
 		clk_enable_unlock(flags);
 
-		if (clk->prepare_count)
+		if (clk->prepare_count) {
+			clk_disable(clk);
+			clk_disable(parent);
 			__clk_unprepare(parent);
-
+		}
 		return ret;
 	}
 
-	/* clean up enable for old parent if migration was done */
-	if (migrated_enable) {
-		flags = clk_enable_lock();
-		__clk_disable(old_parent);
-		clk_enable_unlock(flags);
-	}
-
-	/* clean up prepare for old parent if migration was done */
-	if (clk->prepare_count)
+	/*
+	 * Finish the migration of prepare state and undo the changes done
+	 * for preventing a race with clk_enable().
+	 */
+	if (clk->prepare_count) {
+		clk_disable(clk);
+		clk_disable(old_parent);
 		__clk_unprepare(old_parent);
+	}
 
 	/* update debugfs with new clk tree topology */
 	clk_debug_reparent(clk, parent);
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From anup at brainfault.org  Wed May  1 01:01:32 2013
From: anup at brainfault.org (Anup Patel)
Date: Wed, 1 May 2013 10:31:32 +0530
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <2A4B3F6B-55DA-44F3-87DB-064DB4A8D8F8@suse.de>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <87r4hsameo.fsf@rustcorp.com.au>
 <2A4B3F6B-55DA-44F3-87DB-064DB4A8D8F8@suse.de>
Message-ID: <CAAhSdy3A_aYKXhGVkWdK4amC14PduccyrGsPNEYKvue=T74_sA@mail.gmail.com>

On Wed, May 1, 2013 at 5:56 AM, Alexander Graf <agraf at suse.de> wrote:
>
> On 30.04.2013, at 02:32, Rusty Russell wrote:
>
>> Alexander Graf <agraf at suse.de> writes:
>>> Am 29.04.2013 um 05:09 schrieb Rusty Russell <rusty at rustcorp.com.au>:
>>>
>>>> Alexander Graf <agraf at suse.de> writes:
>>>>> On 26.04.2013, at 13:04, Pranavkumar Sawargaonkar wrote:
>>>>>
>>>>>> This patch-set implements early printk support for virtio console devices without using any hypercalls.
>>>>>>
>>>>>> The current virtio early printk code in kernel expects that hypervisor will provide some mechanism generally a hypercall to support early printk. This patch-set does not break existing hypercall based early print support.
>>>>>>
>>>>>> This implementation adds:
>>>>>> 1. Early writeonly register named early_wr in virtio console's config space.
>>>>>> 2. Host feature flags namely VIRTIO_CONSOLE_F_EARLY_WRITE for telling guest about early-write capability in console device.
>>>>>>
>>>>>> Early write mechanism:
>>>>>> 1. When a guest wants to out some character, it has to simply write the character to early_wr register in config space of virtio console device.
>>>>>
>>>>> I won't nack this patch set, but I'll definitely express that I'm not happy with it.
>>>>>
>>>>> MMIO registers are handled by a different layer than the virtio console itself. After the virtio refactoring in QEMU, they will be completely separate drivers. So we'll be in a similar mess with early printk as we are on the s390-virtio machine, where early printk is done through hypercalls and thus we can't directly link it to the console output.
>>>>>
>>>>> I still don't see what the issue is with just implementing a small irq-less virtio driver for early printk.
>>>>
>>>> Well, this shouldn't be mmio-specific, but I kind of get what you mean.
>>>>
>>>> I consider this misnamed: it's an emergency write facility.  Linux may
>>>> use it for an early console,
>>>
>>> If Linux uses it for early console, you won't see any messages from before the virtio-console driver is initialized, because Linux thinks that it's all been printed out.
>>
>> If you can't support it, don't offer the feature.
>
> Fair enough.
>
>>
>>>> but it's also useful for bringup and to
>>>> give a method of emitting errors like "the console ring is corrupt".
>>>>
>>>> A valid implementation may well be to only offer it with some magic
>>>> qemu developer-only commandline and dump it to stdout.
>>>
>>> Why implement it differently from other machines? There are facilities to call into firmware, so you could use that. There's the special Foundation model call that you could implement and reuse for this.
>>
>> Sure, for ARM.  We *have* a console device.  It's the logical place to
>> provide a simple write mechanism.  eg. consider bhyve on FreeBSD.
>
> I don't quite see the point. The reason early printk works so well for x86 is that you have a UART at a predefined place.
>
>>
>>> I don't see why anything like this has to live in virtio-mmio. Oh, and it should default to off.
>>
>> virtio-console, not virtio-mmio.
>
> How will it live in virtio-console? Virtio-console speaks virtio, not register values. If you put this into the config space you break the s390 virtio model.

This is a small limitation of QEMU VirtIO implementation and it can be
easily fixed in QEMU VirtIO.

The VirtIO spec does not tell that VirtIO device specific config
registers are to be emulated by VirtIO transport device (MMIO or PCI).

As per VirtIO spec, the only register that should be emulated by
transport device are the generic VirtIO registers and the VirtIO
device specific config registers should be emulated by VirtIO device
backend.

>
>
> Alex
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

--Anup


From sfr at canb.auug.org.au  Wed May  1 02:44:23 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Wed, 1 May 2013 16:44:23 +1000
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20130501164423.1233db0b618d0e6b7184c05b@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-tegra/hotplug.c between commit da2265b130f6 ("ARM: tegra:
remove tegra specific cpu_disable()") from the arm tree and commit
7469688e832e ("ARM: tegra: Unify tegra{20,30,114}_init_early()") from the
arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-tegra/hotplug.c
index e8323bc,8da9f78..0000000
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@@ -12,8 -11,10 +11,9 @@@
  #include <linux/smp.h>
  #include <linux/clk/tegra.h>
  
 -#include <asm/cacheflush.h>
  #include <asm/smp_plat.h>
  
+ #include "fuse.h"
  #include "sleep.h"
  
  static void (*tegra_hotplug_shutdown)(void);
@@@ -46,18 -47,22 +46,13 @@@ void __ref tegra_cpu_die(unsigned int c
  	BUG();
  }
  
- #ifdef CONFIG_ARCH_TEGRA_2x_SOC
- extern void tegra20_hotplug_shutdown(void);
- void __init tegra20_hotplug_init(void)
 -int tegra_cpu_disable(unsigned int cpu)
 -{
 -	/*
 -	 * we don't allow CPU 0 to be shutdown (it is still too special
 -	 * e.g. clock tick interrupts)
 -	 */
 -	return cpu == 0 ? -EPERM : 0;
 -}
 -
+ void __init tegra_hotplug_init(void)
  {
- 	tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
- }
- #endif
+ 	if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
+ 		return;
  
- #ifdef CONFIG_ARCH_TEGRA_3x_SOC
- extern void tegra30_hotplug_shutdown(void);
- void __init tegra30_hotplug_init(void)
- {
- 	tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+ 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+ 		tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+ 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+ 		tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
  }
- #endif
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From monstr at monstr.eu  Wed May  1 02:50:09 2013
From: monstr at monstr.eu (Michal Simek)
Date: Wed, 01 May 2013 08:50:09 +0200
Subject: [PATCH 1/7] tty: xuartps: Sort #includes alphabetically
In-Reply-To: <20130501002321.GB7435@kroah.com>
References: <1367366284-28304-1-git-send-email-soren.brinkmann@xilinx.com>
 <1367366284-28304-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130501000048.GA1840@kroah.com>
 <cbd8c55c-066b-4396-9a4b-97d58a93b573@DB8EHSMHS005.ehs.local>
 <20130501002321.GB7435@kroah.com>
Message-ID: <5180BB21.2080306@monstr.eu>

On 05/01/2013 02:23 AM, Greg Kroah-Hartman wrote:
> On Tue, Apr 30, 2013 at 05:05:40PM -0700, S?ren Brinkmann wrote:
>> On Tue, Apr 30, 2013 at 05:00:48PM -0700, Greg Kroah-Hartman wrote:
>>> On Tue, Apr 30, 2013 at 04:57:58PM -0700, Soren Brinkmann wrote:
>>>> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
>>>> CC: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
>>>> CC: Jiri Slaby <jslaby at suse.cz>
>>>> CC: linux-serial at vger.kernel.org
>>>
>>> Why would you need/want to do this?
>> I often come across duplicated includes. Having some kind of order helps
>> avoiding that, imho.
> 
> We have a tool to handle duplicated includes, no need to put them in
> sorted order for them to be detected.

What's the name of tool which does that?
I have seen results from it but have never tried to find it out name and
how to use it.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From anup at brainfault.org  Wed May  1 02:53:49 2013
From: anup at brainfault.org (Anup Patel)
Date: Wed, 1 May 2013 12:23:49 +0530
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <87sj27xxjr.fsf@rustcorp.com.au>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
Message-ID: <CAAhSdy14ofVEdrfc2r3PqLFrTA9kvM+oBVWmXNSWBq2xTxMLiQ@mail.gmail.com>

On Wed, May 1, 2013 at 7:37 AM, Rusty Russell <rusty at rustcorp.com.au> wrote:
> Alexander Graf <agraf at suse.de> writes:
>> There are not device specific registers in
>> virtio-console. Virtio-console lives behind a virtio bus which doesn't
>> know what these registers are.
>
> You're not going to make coherent arguments without reading that actual
> patch we're discussing.  And you're going to just waste everyone else's
> time.
>
>> Even if you shove it into config space,
>
> Which is what the patch does...
>
>> it'd be broken because config access happens without intercepts on
>> some platforms.
>
> But people keep assuming it, which is one reason virtio_ccw switched
> from passive lguest-style config to active.  Only lguest and the old kvm
> virtio use it, and lguest can change.
>
> An emergency output is a reasonable idea, and this is a reasonable
> implementation.  The question is practical: will it be used?  Because we
> don't implement reasonable ideas which aren't going to be used.

We are already using it for Guest bring-up on APM ARM64 board using
KVMTOOL and so far it has been really helpful in debugging KVM ARM64
guest issues.

Also, this is a very useful debugging method for Guest bring-up on
other architectures supported by KVM and other Hypervisors that
support VirtIO.

>
> Cheers,
> Rusty.
> _______________________________________________
> kvmarm mailing list
> kvmarm at lists.cs.columbia.edu
> https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm

Regards,
Anup


From tom.leiming at gmail.com  Wed May  1 04:11:47 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Wed, 1 May 2013 16:11:47 +0800
Subject: [Question] flush_dcache_page() need to flush icache?
In-Reply-To: <20130430152635.GH29766@arm.com>
References: <CACVXFVMz3jLEPDYFM-_S_t5TiqikVSRiKf9cBNocH3QhVexwZg@mail.gmail.com>
 <20130430090502.GC29766@arm.com>
 <CACVXFVPz-rMiPyW2EE==v58LF6uTD1M1fKTNcF5a5+Z6-5u+Gg@mail.gmail.com>
 <20130430152635.GH29766@arm.com>
Message-ID: <CACVXFVNUu9HKY+Vo7VLWGC3rQoj7TUwC3kfpEsf5kCEibMcThg@mail.gmail.com>

On Tue, Apr 30, 2013 at 11:26 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
>
> It's not self-modifying code, this would be code running in user space
> which modifies some other code and it would invoke the ARM-specific
> syscall for flushing.
>
> Here it is about kernel modifying a page which is already mapped in user
> space, hence the check for mapping && mapping_mapped.

I understand that flushing icache is only needed when the page is mapped
as executable in virtual address, right?  If yes, the flush_dcache_page might
be inside read/write on one mapped page(executable in virtual space), then
still looks like self-modifying code case?

Thanks,
-- 
Ming Lei


From catalin.marinas at arm.com  Wed May  1 04:22:38 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 1 May 2013 09:22:38 +0100
Subject: [Question] flush_dcache_page() need to flush icache?
In-Reply-To: <CACVXFVNUu9HKY+Vo7VLWGC3rQoj7TUwC3kfpEsf5kCEibMcThg@mail.gmail.com>
References: <CACVXFVMz3jLEPDYFM-_S_t5TiqikVSRiKf9cBNocH3QhVexwZg@mail.gmail.com>
 <20130430090502.GC29766@arm.com>
 <CACVXFVPz-rMiPyW2EE==v58LF6uTD1M1fKTNcF5a5+Z6-5u+Gg@mail.gmail.com>
 <20130430152635.GH29766@arm.com>
 <CACVXFVNUu9HKY+Vo7VLWGC3rQoj7TUwC3kfpEsf5kCEibMcThg@mail.gmail.com>
Message-ID: <20130501082238.GA10984@arm.com>

On Wed, May 01, 2013 at 09:11:47AM +0100, Ming Lei wrote:
> On Tue, Apr 30, 2013 at 11:26 PM, Catalin Marinas
> <catalin.marinas at arm.com> wrote:
> >
> > It's not self-modifying code, this would be code running in user space
> > which modifies some other code and it would invoke the ARM-specific
> > syscall for flushing.
> >
> > Here it is about kernel modifying a page which is already mapped in user
> > space, hence the check for mapping && mapping_mapped.
> 
> I understand that flushing icache is only needed when the page is mapped
> as executable in virtual address, right?  If yes, the flush_dcache_page might
> be inside read/write on one mapped page(executable in virtual space), then
> still looks like self-modifying code case?

It depends on the definition of 'self'. If by that you mean the user
application, it hasn't modified itself and it can't trigger
flush_dcache_page().

-- 
Catalin


From tom.leiming at gmail.com  Wed May  1 04:53:47 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Wed, 1 May 2013 16:53:47 +0800
Subject: [Question] flush_dcache_page() need to flush icache?
In-Reply-To: <20130501082238.GA10984@arm.com>
References: <CACVXFVMz3jLEPDYFM-_S_t5TiqikVSRiKf9cBNocH3QhVexwZg@mail.gmail.com>
 <20130430090502.GC29766@arm.com>
 <CACVXFVPz-rMiPyW2EE==v58LF6uTD1M1fKTNcF5a5+Z6-5u+Gg@mail.gmail.com>
 <20130430152635.GH29766@arm.com>
 <CACVXFVNUu9HKY+Vo7VLWGC3rQoj7TUwC3kfpEsf5kCEibMcThg@mail.gmail.com>
 <20130501082238.GA10984@arm.com>
Message-ID: <CACVXFVMCmzESFW_E+1tE9h_yHAnKVwMyot6RSHicAD91HQeQOA@mail.gmail.com>

On Wed, May 1, 2013 at 4:22 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
>
> It depends on the definition of 'self'. If by that you mean the user
> application, it hasn't modified itself and it can't trigger
> flush_dcache_page().

Yes, you are right, and it is the case in which one user application
modifies code of another application. I mean if it is possible to flush
icache only under this situation, which should be very rare.


Thanks,
-- 
Ming Lei


From horms at verge.net.au  Wed May  1 05:09:09 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 1 May 2013 18:09:09 +0900
Subject: [PATCH v3 4/5] ARM: shmobile: BOCK-W: add VIN and ML86V7667
 support
In-Reply-To: <517B06FA.3000303@cogentembedded.com>
References: <201304232118.43686.sergei.shtylyov@cogentembedded.com>
 <201304232132.52741.sergei.shtylyov@cogentembedded.com>
 <517B06FA.3000303@cogentembedded.com>
Message-ID: <20130501090909.GA2562@verge.net.au>

On Sat, Apr 27, 2013 at 03:00:10AM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 04/23/2013 09:32 PM, Sergei Shtylyov wrote:
> 
> >From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
> >
> >Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and
> >register VIN0/1 devices with the ML86V7667 specific platform data.
> >
> >Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
> >[Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate
> >#include, annotated all platform data as '__initdata'.]
> >Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >
> >---
> >Changes since version 2:
> >- removed duplicate #include <linux/pinctrl/machine.h>;
> >- annotated all platform data as '__initdata' since they're kmemdup()'ed while
> >   registering the platform devices anyway;
> >- resolved rejects, refreshed the patch.
> >
> >  arch/arm/mach-shmobile/board-bockw.c |   39 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 39 insertions(+)
> >
> >Index: renesas/arch/arm/mach-shmobile/board-bockw.c
> >===================================================================
> >--- renesas.orig/arch/arm/mach-shmobile/board-bockw.c
> >+++ renesas/arch/arm/mach-shmobile/board-bockw.c
> 
> [...]
> 
> >@@ -80,6 +101,16 @@ static const struct pinctrl_map bockw_pi
> >  				  "sdhi0_data4", "sdhi0"),
> >  	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
> >  				  "sdhi0_wp", "sdhi0"),
> >+	/* VIN0 */
> >+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.0", "pfc-r8a7778",
> >+				  "vin0_clk", "vin0"),
> >+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.0", "pfc-r8a7778",
> >+				  "vin0_data8", "vin0"),
> >+	/* VIN1 */
> >+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.1", "pfc-r8a7778",
> >+				  "vin1_clk", "vin1"),
> >+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.1", "pfc-r8a7778",
> >+				  "vin1_data8", "vin1"),
> >  };
> 
>     It turned out that VIN1 signal VI1_CLK conflicts with Ether
> signal ETH_REF_CLK.
> So I'm a bit at a loss here: whether I should totally remove VIN1
> device if I'm going
> to add Ether device, or add a BOCK-W specific submenu to Kconfig, or
> add driver
> specific #ifdef's in the code to disable VIN1 if sh_eth driver is
> enabled?...

My preference, in order is:

* Remove VIN1 (is it used?)
* Kconfig-foo
* #ifdef nastiness


From catalin.marinas at arm.com  Wed May  1 05:11:08 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 1 May 2013 10:11:08 +0100
Subject: [PATCH 6/4] arm64: Move to generic sched_clock infrastructure
In-Reply-To: <1367369675-13535-2-git-send-email-sboyd@codeaurora.org>
References: <1366417746-24990-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-2-git-send-email-sboyd@codeaurora.org>
Message-ID: <20130501091108.GB10984@arm.com>

On Wed, May 01, 2013 at 01:54:35AM +0100, Stephen Boyd wrote:
> Use the generic sched_clock infrastructure instead of rolling our
> own. This has the added benefit of fixing suspend/resume as
> outlined in 6a4dae5 (ARM: 7565/1: sched: stop sched_clock()
> during suspend, 2012-10-23) and correcting the timestamps when
> the hardware returns a value instead of 0 upon the first read.
> 
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>

Looks ok.

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From lee.jones at linaro.org  Wed May  1 05:51:11 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 1 May 2013 10:51:11 +0100
Subject: [PATCH 1/5] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <201304302242.24002.arnd@arndb.de>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <201304302242.24002.arnd@arndb.de>
Message-ID: <20130501095111.GC25256@gmail.com>

At this moment in time the memcpy channels which can be used by the D40
are fixed, as each supported platform in Mainline uses the same ones.
However, platforms do exist which don't follow this convention, so
these will need to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 2679a87..aa272d8 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -6,6 +6,7 @@ Required properties:
 - reg-names: Names of the above areas to use during resource look-up
 - interrupt: Should contain the DMAC interrupt number
 - #dma-cells: must be <3>
+- memcpy-channels: Channels to be used for memcpy
 
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
@@ -21,6 +22,7 @@ Example:
 		interrupts = <0 25 0x4>;
 
 		#dma-cells = <2>;
+		memcpy-channels  = <56 57 58 59 60>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index d5c39e4..0077184 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,8 +58,10 @@
 #define D40_ALLOC_PHY		BIT(30)
 #define D40_ALLOC_LOG_FREE	0
 
+#define D40_MEMCPY_MAX_CHANS	8
+
 /* Reserved event lines for memcpy only. */
-static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
+static int dma40_memcpy_channels[D40_MEMCPY_MAX_CHANS] = { 56, 57, 58, 59, 60 };
 
 /* Default configuration for physcial memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
@@ -508,6 +510,8 @@ struct d40_gen_dmac {
  * @phy_start: Physical memory start of the DMA registers.
  * @phy_size: Size of the DMA register map.
  * @irq: The IRQ number.
+ * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
+ * transfers).
  * @num_phy_chans: The number of physical channels. Read from HW. This
  * is the number of available channels for this driver, not counting "Secure
  * mode" allocated physical channels.
@@ -551,6 +555,7 @@ struct d40_base {
 	phys_addr_t			  phy_start;
 	resource_size_t			  phy_size;
 	int				  irq;
+	int				  num_memcpy_chans;
 	int				  num_phy_chans;
 	int				  num_log_chans;
 	struct device_dma_parameters	  dma_parms;
@@ -2920,7 +2925,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 	}
 
 	d40_chan_init(base, &base->dma_memcpy, base->log_chans,
-		      base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
+		      base->num_log_chans, base->num_memcpy_chans);
 
 	dma_cap_zero(base->dma_memcpy.cap_mask);
 	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3121,6 +3126,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	struct d40_base *base = NULL;
 	int num_log_chans = 0;
 	int num_phy_chans;
+	int num_memcpy_chans;
 	int clk_ret = -EINVAL;
 	int i;
 	u32 pid;
@@ -3191,6 +3197,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	else
 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
 
+	/* The number of channels used for memcpy */
+	if (plat_data->num_of_memcpy_chans)
+		num_memcpy_chans = plat_data->num_of_memcpy_chans;
+	else
+		num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
+
 	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
 
 	dev_info(&pdev->dev,
@@ -3198,7 +3210,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		 rev, res->start, num_phy_chans, num_log_chans);
 
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
-		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
+		       (num_phy_chans + num_log_chans + num_memcpy_chans) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
 
 	if (base == NULL) {
@@ -3208,6 +3220,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 
 	base->rev = rev;
 	base->clk = clk;
+	base->num_memcpy_chans = num_memcpy_chans;
 	base->num_phy_chans = num_phy_chans;
 	base->num_log_chans = num_log_chans;
 	base->phy_start = res->start;
@@ -3451,12 +3464,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
- 
-	/*
-	 * FIXME: Fill in this routine as more support is added.
-	 * First platform enabled (u8500) doens't need any extra
-	 * properties to run, so this is fairly sparce currently.
-	 */
+	int num_memcpy = 0;
+	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
 			     sizeof(struct stedma40_platform_data),
@@ -3464,6 +3473,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 	if (!pdata)
 		return -ENOMEM;
 
+	list = of_get_property(np, "memcpy-channels", &num_memcpy);
+	num_memcpy /= sizeof(*list);
+
+	if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of memcpy channels specified (%d)\n",
+			num_memcpy);
+		return -EINVAL;
+	}
+	pdata->num_of_memcpy_chans = num_memcpy;
+
+	of_property_read_u32_array(np, "memcpy-channels",
+				   dma40_memcpy_channels,
+				   num_memcpy);
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index ceba6dc..1bb9b18 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
  * @num_of_soft_lli_chans: The number of channels that needs to be configured
  * to use SoftLLI.
  * @use_esram_lcla: flag for mapping the lcla into esram region
+ * @num_of_memcpy_chans: The number of channels reserved for memcpy.
  * @num_of_phy_chans: The number of physical channels implemented in HW.
  * 0 means reading the number of channels from DMA HW but this is only valid
  * for 'multiple of 4' channels, like 8.
@@ -141,6 +142,7 @@ struct stedma40_platform_data {
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
 	bool				 use_esram_lcla;
+	int				 num_of_memcpy_chans;
 	int				 num_of_phy_chans;
 };


From lee.jones at linaro.org  Wed May  1 05:52:43 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 1 May 2013 10:52:43 +0100
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20130501095243.GD25256@gmail.com>

At this moment in time the memcpy channels which can be used by the D40
are fixed, as each supported platform in Mainline uses the same ones.
However, platforms do exist which don't follow this convention, so
these will need to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 2679a87..aa272d8 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -6,6 +6,7 @@ Required properties:
 - reg-names: Names of the above areas to use during resource look-up
 - interrupt: Should contain the DMAC interrupt number
 - #dma-cells: must be <3>
+- memcpy-channels: Channels to be used for memcpy
 
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
@@ -21,6 +22,7 @@ Example:
 		interrupts = <0 25 0x4>;
 
 		#dma-cells = <2>;
+		memcpy-channels  = <56 57 58 59 60>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index d5c39e4..0077184 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,8 +58,10 @@
 #define D40_ALLOC_PHY		BIT(30)
 #define D40_ALLOC_LOG_FREE	0
 
+#define D40_MEMCPY_MAX_CHANS	8
+
 /* Reserved event lines for memcpy only. */
-static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
+static int dma40_memcpy_channels[D40_MEMCPY_MAX_CHANS] = { 56, 57, 58, 59, 60 };
 
 /* Default configuration for physcial memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
@@ -508,6 +510,8 @@ struct d40_gen_dmac {
  * @phy_start: Physical memory start of the DMA registers.
  * @phy_size: Size of the DMA register map.
  * @irq: The IRQ number.
+ * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
+ * transfers).
  * @num_phy_chans: The number of physical channels. Read from HW. This
  * is the number of available channels for this driver, not counting "Secure
  * mode" allocated physical channels.
@@ -551,6 +555,7 @@ struct d40_base {
 	phys_addr_t			  phy_start;
 	resource_size_t			  phy_size;
 	int				  irq;
+	int				  num_memcpy_chans;
 	int				  num_phy_chans;
 	int				  num_log_chans;
 	struct device_dma_parameters	  dma_parms;
@@ -2920,7 +2925,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 	}
 
 	d40_chan_init(base, &base->dma_memcpy, base->log_chans,
-		      base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
+		      base->num_log_chans, base->num_memcpy_chans);
 
 	dma_cap_zero(base->dma_memcpy.cap_mask);
 	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3121,6 +3126,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	struct d40_base *base = NULL;
 	int num_log_chans = 0;
 	int num_phy_chans;
+	int num_memcpy_chans;
 	int clk_ret = -EINVAL;
 	int i;
 	u32 pid;
@@ -3191,6 +3197,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	else
 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
 
+	/* The number of channels used for memcpy */
+	if (plat_data->num_of_memcpy_chans)
+		num_memcpy_chans = plat_data->num_of_memcpy_chans;
+	else
+		num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
+
 	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
 
 	dev_info(&pdev->dev,
@@ -3198,7 +3210,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		 rev, res->start, num_phy_chans, num_log_chans);
 
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
-		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
+		       (num_phy_chans + num_log_chans + num_memcpy_chans) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
 
 	if (base == NULL) {
@@ -3208,6 +3220,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 
 	base->rev = rev;
 	base->clk = clk;
+	base->num_memcpy_chans = num_memcpy_chans;
 	base->num_phy_chans = num_phy_chans;
 	base->num_log_chans = num_log_chans;
 	base->phy_start = res->start;
@@ -3451,12 +3464,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
- 
-	/*
-	 * FIXME: Fill in this routine as more support is added.
-	 * First platform enabled (u8500) doens't need any extra
-	 * properties to run, so this is fairly sparce currently.
-	 */
+	int num_memcpy = 0;
+	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
 			     sizeof(struct stedma40_platform_data),
@@ -3464,6 +3473,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 	if (!pdata)
 		return -ENOMEM;
 
+	list = of_get_property(np, "memcpy-channels", &num_memcpy);
+	num_memcpy /= sizeof(*list);
+
+	if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of memcpy channels specified (%d)\n",
+			num_memcpy);
+		return -EINVAL;
+	}
+	pdata->num_of_memcpy_chans = num_memcpy;
+
+	of_property_read_u32_array(np, "memcpy-channels",
+				   dma40_memcpy_channels,
+				   num_memcpy);
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index ceba6dc..1bb9b18 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
  * @num_of_soft_lli_chans: The number of channels that needs to be configured
  * to use SoftLLI.
  * @use_esram_lcla: flag for mapping the lcla into esram region
+ * @num_of_memcpy_chans: The number of channels reserved for memcpy.
  * @num_of_phy_chans: The number of physical channels implemented in HW.
  * 0 means reading the number of channels from DMA HW but this is only valid
  * for 'multiple of 4' channels, like 8.
@@ -141,6 +142,7 @@ struct stedma40_platform_data {
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
 	bool				 use_esram_lcla;
+	int				 num_of_memcpy_chans;
 	int				 num_of_phy_chans;
 };


From lee.jones at linaro.org  Wed May  1 05:54:06 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 1 May 2013 10:54:06 +0100
Subject: [PATCH 5/5 v2] dmaengine: ste_dma40: Fetch disabled channels from DT
In-Reply-To: <1367336497-10650-5-git-send-email-lee.jones@linaro.org>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <1367336497-10650-5-git-send-email-lee.jones@linaro.org>
Message-ID: <20130501095406.GE25256@gmail.com>

    Some platforms have channels which are not available for normal use.
    This information is currently passed though platform data in internal
    BSP kernels. Once those platforms land, they'll need to configure them
    appropriately, so we may as well add the infrastructure.
    
    Cc: Vinod Koul <vinod.koul at intel.com>
    Cc: Dan Williams <djbw at fb.com>
    Cc: Per Forlin <per.forlin at stericsson.com>
    Cc: Rabin Vincent <rabin at rab.in>
    Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index aa272d8..bea5b73 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -11,6 +11,7 @@ Required properties:
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
 		the driver will attempt to obtain the information from H/W
+- disabled-channels: Channels which can not be used
 
 Example:
 
@@ -23,6 +24,7 @@ Example:
 
 		#dma-cells = <2>;
 		memcpy-channels  = <56 57 58 59 60>;
+		disabled-channels  = <12>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b14de16..658b53b 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3464,7 +3464,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
-	int num_phy = 0, num_memcpy = 0;
+	int num_phy = 0, num_memcpy = 0, num_disabled = 0;
 	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
@@ -3493,6 +3493,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 				   dma40_memcpy_channels,
 				   num_memcpy);
 
+	list = of_get_property(np, "disabled-channels", &num_disabled);
+	num_disabled /= sizeof(*list);
+
+	if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of disabled channels specified (%d)\n",
+			num_disabled);
+		return -EINVAL;
+	}
+
+	of_property_read_u32_array(np, "disabled-channels",
+				   pdata->disabled_channels,
+				   num_disabled);
+	pdata->disabled_channels[num_disabled] = -1;
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;


From daniel.vetter at ffwll.ch  Wed May  1 06:26:01 2013
From: daniel.vetter at ffwll.ch (Daniel Vetter)
Date: Wed, 1 May 2013 12:26:01 +0200
Subject: [Linaro-mm-sig] RFC: Unified DMA allocation algorithms
In-Reply-To: <51785024.40305@codeaurora.org>
References: <51785024.40305@codeaurora.org>
Message-ID: <CAKMK7uE5HQs7JoyVp8HbOzQ4PM=mOW3=WpRtFUzvy3NJ49nYgQ@mail.gmail.com>

On Wed, Apr 24, 2013 at 11:35 PM, Laura Abbott <lauraa at codeaurora.org> wrote:
> Hi all,
>
> I've been looking at a better way to do custom dma allocation algorithms in
> a similar style to Ion heaps. Most drivers/clients have come up with a
> series of semi-standard ways to get memory (CMA, memblock_reserve,
> discontiguous pages etc.) . As these allocation schemes get more and more
> complex, there needs to be a since place where all clients (Ion based driver
> vs. DRM driver vs. ???)  can independently take advantage of any
> optimizations and call a single API for the backing allocations.
>
> The dma_map_ops take care of almost everything needed for abstraction
> but the question is where should new allocation algorithms be located?
> Most of the work has been added to either arm/mm/dma-mapping.c or
> dma-contiguous.c . My current thought:
>
> 1) split out the dma_map_ops currently in dma-mapping.c into separate files
> (dma-mapping-common.c, dma-mapping-iommu.c)
> 2) Extend dma-contiguous.c to support memblock_reserve memory
> 3) Place additional algorithms in either arch/arm/mm or
> drivers/base/dma-alloc/ as appropriate to the code. This is the part where
> I'm most unsure about the direction.
>
> I don't have anything written yet but I plan to draft some patches assuming
> the proposed approach sounds reasonable and no one else has started on
> something similar already.
>
> Thoughts? Opinions?

>From my (oblivious to all the arm madness) pov the big thing is
getting dma allocations working for more than one struct device. This
way we could get rid of to "where do I need to allocate buffers"
duplication between the kernel and userspace (which needs to know that
to pick the right ion heap), which is my main gripe with ion ;-)

Rob Clark sent out a quick rfc for that a while back:

http://lists.linaro.org/pipermail/linaro-mm-sig/2012-July/002250.html

But that's by far not good enough for arm, especially now that cma
gets tightly bound to individual devices with the dt bindings. Also,
no one really followed up on Rob's patches, and personally I don't
really care that much since x86 is a bit saner ... But it should be
good enough for contiguous allocations, which leaves only really crazy
stuff unsolved.

So I think when you want to rework the various algorithms for
allocating dma mem and consolidate them it should also solve this
little multi-dev issue.

Adding tons more people/lists who might be interested.

Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From arnd at arndb.de  Wed May  1 06:27:06 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 1 May 2013 12:27:06 +0200
Subject: [PATCH 5/5 v2] dmaengine: ste_dma40: Fetch disabled channels from
 DT
In-Reply-To: <20130501095406.GE25256@gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <1367336497-10650-5-git-send-email-lee.jones@linaro.org>
 <20130501095406.GE25256@gmail.com>
Message-ID: <201305011227.07086.arnd@arndb.de>

On Wednesday 01 May 2013, Lee Jones wrote:
>     Some platforms have channels which are not available for normal use.
>     This information is currently passed though platform data in internal
>     BSP kernels. Once those platforms land, they'll need to configure them
>     appropriately, so we may as well add the infrastructure.
>     
>     Cc: Vinod Koul <vinod.koul at intel.com>
>     Cc: Dan Williams <djbw at fb.com>
>     Cc: Per Forlin <per.forlin at stericsson.com>
>     Cc: Rabin Vincent <rabin at rab.in>
>     Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed May  1 06:27:32 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 1 May 2013 12:27:32 +0200
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <20130501095243.GD25256@gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <20130501095243.GD25256@gmail.com>
Message-ID: <201305011227.33117.arnd@arndb.de>

On Wednesday 01 May 2013, Lee Jones wrote:
> At this moment in time the memcpy channels which can be used by the D40
> are fixed, as each supported platform in Mainline uses the same ones.
> However, platforms do exist which don't follow this convention, so
> these will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From sylvester.nawrocki at gmail.com  Wed May  1 06:28:17 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Wed, 01 May 2013 12:28:17 +0200
Subject: [alsa-devel] [PATCH] MAINTAINERS: Add linux-samsung-soc list
 to all related entries
In-Reply-To: <20130430132755.GB1023@sirena.org.uk>
References: <1366572050-626-1-git-send-email-tomasz.figa@gmail.com>
 <CAH9JG2U7Qdq_xQbuqHu6PXzURS2fWwBC=HJmyrXT5n3n_pAa0w@mail.gmail.com>
 <20130430132755.GB1023@sirena.org.uk>
Message-ID: <5180EE41.50302@gmail.com>

On 04/30/2013 03:27 PM, Mark Brown wrote:
> On Mon, Apr 22, 2013 at 03:23:29PM +0900, Kyungmin Park wrote:
>
>> I don't think it's not required, each tree has each own mailing list. don't
>> need to post all patches to samsung-soc list.
>
> It can be useful to get system level input on some stuff, I guess it
> mostly depends if the people on the generic list mind the extra traffic
> or if they find it useful.

I think this could also improve testing coverage, if more people are aware
of stuff going in through various mailing lists.

Also on a specific subsystem mailing lists yet another SoC specific patches
may not get enough attention, as people care most about the core subsystem
changes.

So I would in general encourage others to Cc linux-samsung-soc, even if the
$subject patch gets ignored.

I seriously doubt anyone would have ever been disturbed with additional
traffic on the list, with its current average of about 20..50 emails per 
day.


From will.deacon at arm.com  Wed May  1 06:37:18 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 11:37:18 +0100
Subject: [PATCH] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <1367347089-23788-1-git-send-email-csd@broadcom.com>
References: <1367347089-23788-1-git-send-email-csd@broadcom.com>
Message-ID: <20130501103718.GC22796@mudshark.cambridge.arm.com>

Hi Christian,

Thanks for CC'ing me.

On Tue, Apr 30, 2013 at 07:38:09PM +0100, Christian Daudt wrote:
> Rev A2 SoCs have an unorthodox memory re-mapping and this needs
> to be reflected in the cache operations.
> This patch adds new outer cache functions for the l2x0 driver
> to support this SoC revision. It also adds a new compatible
> value for the cache to enable this functionality.

This is a pretty weird thing you've managed to build here...

> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index c465fac..6edba13 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -523,6 +523,162 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
>  	}
>  }
>  
> +/*
> + * For certain Broadcom SoCs, depending on the address range, different offsets
> + * need to be added to the address before passing it to L2 for
> + * invalidation/clean/flush
> + *
> + * Section Address Range              Offset        EMI
> + *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
> + *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
> + *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC

Hmm, so am I right in thinking that the `Broadcom addresses' for section 1
and 2 overlap? It would also be worth describing which physical addresses
Linux actually wants to use; where is the memory in the physical memory map
for devices with this L2 controller?

> + * When the start and end addresses have crossed two different sections, we
> + * need to break the L2 operation into two, each within its own section.
> + * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
> + * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
> + * 0xC0000000 - 0xC0001000
> + *
> + * Note 1:
> + * By breaking a single L2 operation into two, we may potentially suffer some
> + * performance hit, but keep in mind the cross section case is very rare
> + *
> + * Note 2:
> + * We do not need to handle the case when the start address is in
> + * Section 1 and the end address is in Section 3, since it is not a valid use
> + * case
> + */
> +
> +#define BCM_VC_EMI_SEC1_START_ADDR    0x00000000UL
> +#define BCM_VC_EMI_SEC1_END_ADDR      0x3FFFFFFFUL
> +#define BCM_SYS_EMI_START_ADDR        0x40000000UL
> +#define BCM_SYS_EMI_END_ADDR          0xBFFFFFFFUL
> +#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
> +#define BCM_VC_EMI_SEC3_END_ADDR      0xFFFFFFFFUL

Seems a bit odd defining the END_ADDRs here, I'd just use strict '<' against
the start of the next section in your code.

> +#define BCM_SYS_EMI_OFFSET            0x40000000UL
> +#define BCM_VC_EMI_OFFSET             0x80000000UL
> +
> +static inline int bcm_addr_is_sys_emi(unsigned long addr)
> +{
> +	return (addr >= BCM_SYS_EMI_START_ADDR) &&
> +		(addr <= BCM_SYS_EMI_END_ADDR);
> +}
> +
> +static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
> +{
> +	if (bcm_addr_is_sys_emi(addr))
> +		return addr + BCM_SYS_EMI_OFFSET;
> +	else
> +		return addr + BCM_VC_EMI_OFFSET;
> +}
> +
> +static void bcm_inv_range(unsigned long start, unsigned long end)
> +{
> +	unsigned long new_start, new_end;
> +
> +	if (unlikely(end <= start))
> +		return;
> +
> +	new_start = bcm_l2_phys_addr(start);
> +	new_end = bcm_l2_phys_addr(end);
> +
> +	/* normal case, no cross section between start and end */
> +	if (likely((bcm_addr_is_sys_emi(start) && bcm_addr_is_sys_emi(end)) ||
> +		(!bcm_addr_is_sys_emi(start) && !bcm_addr_is_sys_emi(end)))) {

You could avoid evaluating bcm_addr_is_sys_emi twice for each address. In
fact, you know start < end, so you just need to check start >= EMI_START and
end < EMI_END.

Will


From shc_work at mail.ru  Wed May  1 06:46:58 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Wed,  1 May 2013 14:46:58 +0400
Subject: [PATCH 2/3] ARM: dts: Add SPI support for i.MX27 Phytec PCM038 module
In-Reply-To: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
Message-ID: <1367405219-19078-2-git-send-email-shc_work@mail.ru>

Added SPI node to imx27-phytec-phycore DT file.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/boot/dts/imx27-phytec-phycore.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index fe64e3a..b0e9372 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -72,6 +72,12 @@
 	};
 };
 
+&cspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 28 0>;
+	status = "okay";
+};
+
 &nfc {
 	nand-bus-width = <8>;
 	nand-ecc-mode = "hw";
-- 
1.8.1.5



From shc_work at mail.ru  Wed May  1 06:46:57 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Wed,  1 May 2013 14:46:57 +0400
Subject: [PATCH 1/3] ARM: dts: Add aliases for i.MX27 SPI controller
Message-ID: <1367405219-19078-1-git-send-email-shc_work@mail.ru>

Add aliases to determine the proper SPI bus number.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/boot/dts/imx27.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index ff4bd48..cd85828 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -25,6 +25,9 @@
 		gpio3 = &gpio4;
 		gpio4 = &gpio5;
 		gpio5 = &gpio6;
+		spi0 = &cspi1;
+		spi1 = &cspi2;
+		spi2 = &cspi3;
 	};
 
 	avic: avic-interrupt-controller at e0000000 {
-- 
1.8.1.5



From shc_work at mail.ru  Wed May  1 06:46:59 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Wed,  1 May 2013 14:46:59 +0400
Subject: [PATCH 3/3] ARM: dts: Add MC13783 support for i.MX27 Phytec PCM038
 module
In-Reply-To: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
Message-ID: <1367405219-19078-3-git-send-email-shc_work@mail.ru>

Added MC13783 node to imx27-phytec-phycore DT file.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/boot/dts/imx27-phytec-phycore.dts | 92 ++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index b0e9372..5c4fea9 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -76,6 +76,98 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio4 28 0>;
 	status = "okay";
+
+	pmic: mc13783 at 0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,mc13783";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <23 0x4>;
+		fsl,mc13xxx-uses-adc;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			sw1b_reg: sw1b {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			sw2a_reg: sw2a {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			sw2b_reg: sw2b {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			sw3_reg: sw3 {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			vaudio_reg: vaudio {
+				regulator-min-microvolt = <2775000>;
+				regulator-max-microvolt = <2775000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			violo_reg: violo {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			viohi_reg: viohi {
+				regulator-min-microvolt = <2775000>;
+				regulator-max-microvolt = <2775000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			vgen_reg: vgen {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			vcam_reg: vcam {
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			vrf1_reg: vrf1 {
+				regulator-min-microvolt = <2775000>;
+				regulator-max-microvolt = <2775000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			vrf2_reg: vrf2 {
+				regulator-min-microvolt = <2775000>;
+				regulator-max-microvolt = <2775000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			vmmc1_reg: vmmc1 {
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3000000>;
+			};
+			gpo1_reg: gpo1 {
+			};
+			pwgt1spi_reg: pwgt1spi {
+			};
+		};
+	};
 };
 
 &nfc {
-- 
1.8.1.5



From will.deacon at arm.com  Wed May  1 07:05:34 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 12:05:34 +0100
Subject: [RFC PATCH 5/9] ARM64: mm: Add support for flushing huge pages.
In-Reply-To: <1367339448-21727-6-git-send-email-steve.capper@linaro.org>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-6-git-send-email-steve.capper@linaro.org>
Message-ID: <20130501110534.GD22796@mudshark.cambridge.arm.com>

Hi Steve,

On Tue, Apr 30, 2013 at 05:30:44PM +0100, Steve Capper wrote:
> The code to flush the dcache of a dirty page, __flush_dcache_page,
> will only flush the head of a HugeTLB/THP page.
> 
> This patch adjusts __flush_dcache_page such that the order of the
> compound page is used to determine the size of area to flush.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> ---
>  arch/arm64/mm/flush.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
> index 88611c3..71c182d 100644
> --- a/arch/arm64/mm/flush.c
> +++ b/arch/arm64/mm/flush.c
> @@ -72,7 +72,8 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
>  
>  void __flush_dcache_page(struct page *page)
>  {
> -	__flush_dcache_area(page_address(page), PAGE_SIZE);
> +	size_t page_size = PAGE_SIZE << compound_order(page);
> +	__flush_dcache_area(page_address(page), page_size);
>  }

This penalises flush_dcache_page, while it might only be required for
__sync_icache_dcache (called when installing executable ptes).

Now, the job of flush_dcache_page is to deal with D-side aliases between
concurrent user and kernel mappings. On arm64, D-side aliasing is not a
problem so in theory flush_dcache_page could be a nop (well, a clear_bit,
but close enough).

The reason that flush_dcache_page *isn't* currently a nop, is because we
have harvard caches, so if we end up in a situation where the kernel is
writing executable text to a page which is also mapped into userspace (i.e.
there won't be a subsequent call to set_pte), then the user will execute
junk if we don't flush/invalidate things here.

This might be overkill. I can't think of a scenario where the above is true,
but I'm no mm expert, so it would be great if somebody else could chime in
to confirm/rubbish out suspicions...

Cheers,

Will


From catalin.marinas at arm.com  Wed May  1 07:31:46 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 1 May 2013 12:31:46 +0100
Subject: [RFC PATCH 5/9] ARM64: mm: Add support for flushing huge pages.
In-Reply-To: <20130501110534.GD22796@mudshark.cambridge.arm.com>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-6-git-send-email-steve.capper@linaro.org>
 <20130501110534.GD22796@mudshark.cambridge.arm.com>
Message-ID: <20130501113146.GA4269@arm.com>

On Wed, May 01, 2013 at 12:05:34PM +0100, Will Deacon wrote:
> Hi Steve,
> 
> On Tue, Apr 30, 2013 at 05:30:44PM +0100, Steve Capper wrote:
> > The code to flush the dcache of a dirty page, __flush_dcache_page,
> > will only flush the head of a HugeTLB/THP page.
> > 
> > This patch adjusts __flush_dcache_page such that the order of the
> > compound page is used to determine the size of area to flush.
> > 
> > Signed-off-by: Steve Capper <steve.capper at linaro.org>
> > ---
> >  arch/arm64/mm/flush.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
> > index 88611c3..71c182d 100644
> > --- a/arch/arm64/mm/flush.c
> > +++ b/arch/arm64/mm/flush.c
> > @@ -72,7 +72,8 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
> >  
> >  void __flush_dcache_page(struct page *page)
> >  {
> > -	__flush_dcache_area(page_address(page), PAGE_SIZE);
> > +	size_t page_size = PAGE_SIZE << compound_order(page);
> > +	__flush_dcache_area(page_address(page), page_size);
> >  }
> 
> This penalises flush_dcache_page, while it might only be required for
> __sync_icache_dcache (called when installing executable ptes).
> 
> Now, the job of flush_dcache_page is to deal with D-side aliases between
> concurrent user and kernel mappings. On arm64, D-side aliasing is not a
> problem so in theory flush_dcache_page could be a nop (well, a clear_bit,
> but close enough).
> 
> The reason that flush_dcache_page *isn't* currently a nop, is because we
> have harvard caches, so if we end up in a situation where the kernel is
> writing executable text to a page which is also mapped into userspace (i.e.
> there won't be a subsequent call to set_pte), then the user will execute
> junk if we don't flush/invalidate things here.
> 
> This might be overkill. I can't think of a scenario where the above is true,
> but I'm no mm expert, so it would be great if somebody else could chime in
> to confirm/rubbish out suspicions...

And looking at the powerpc implementation, flush_dcache_page just does
clear_bit(PG_arch_1) and they haven't seen any problems. I'm pretty sure
we can to the same on arm64 (and 32-bit ARMv7 where we don't have
D-cache aliasing). But let's see the mm guys have a better insight here.

-- 
Catalin


From will.deacon at arm.com  Wed May  1 07:42:38 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 12:42:38 +0100
Subject: [RFC PATCH 7/9] ARM64: mm: HugeTLB support.
In-Reply-To: <1367339448-21727-8-git-send-email-steve.capper@linaro.org>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-8-git-send-email-steve.capper@linaro.org>
Message-ID: <20130501114238.GG22796@mudshark.cambridge.arm.com>

Hi Steve,

On Tue, Apr 30, 2013 at 05:30:46PM +0100, Steve Capper wrote:
> Add huge page support to ARM64, different huge page sizes are
> supported depending on the size of normal pages:
> 
> PAGE_SIZE is 4K:
>    2MB - (pmds) these can be allocated at any time.
> 1024MB - (puds) usually allocated on bootup with the command line
>          with something like: hugepagesz=1G hugepages=6
> 
> PAGE_SIZE is 64K:
>  512MB - (pmds), usually allocated on bootup via command line.

[...]

> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index 75fd13d..c3cac68 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -53,6 +53,7 @@
>  #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
>  #define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
>  #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
> +#define PTE_TYPE_HUGEPAGE	(_AT(pmdval_t, 1) << 0)

This breaks PROT_NONE mappings, where you get:

	pte = pte_mkhuge(pte_modify(pte, newprot));

The pte_modify will clear the valid bit and set the prot_none bit (in order
to create a present, faulting entry) but then your pte_mkhuge will come in
and clobber that with a valid block entry.

Will


From steve.capper at linaro.org  Wed May  1 09:04:03 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed, 1 May 2013 14:04:03 +0100
Subject: [RFC PATCH 7/9] ARM64: mm: HugeTLB support.
In-Reply-To: <20130501114238.GG22796@mudshark.cambridge.arm.com>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-8-git-send-email-steve.capper@linaro.org>
 <20130501114238.GG22796@mudshark.cambridge.arm.com>
Message-ID: <20130501130401.GA21923@linaro.org>

On Wed, May 01, 2013 at 12:42:38PM +0100, Will Deacon wrote:
> Hi Steve,
> 
> On Tue, Apr 30, 2013 at 05:30:46PM +0100, Steve Capper wrote:
> > Add huge page support to ARM64, different huge page sizes are
> > supported depending on the size of normal pages:
> > 
> > PAGE_SIZE is 4K:
> >    2MB - (pmds) these can be allocated at any time.
> > 1024MB - (puds) usually allocated on bootup with the command line
> >          with something like: hugepagesz=1G hugepages=6
> > 
> > PAGE_SIZE is 64K:
> >  512MB - (pmds), usually allocated on bootup via command line.
> 
> [...]
> 
> > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> > index 75fd13d..c3cac68 100644
> > --- a/arch/arm64/include/asm/pgtable-hwdef.h
> > +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> > @@ -53,6 +53,7 @@
> >  #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
> >  #define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
> >  #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
> > +#define PTE_TYPE_HUGEPAGE	(_AT(pmdval_t, 1) << 0)
> 
> This breaks PROT_NONE mappings, where you get:
> 
> 	pte = pte_mkhuge(pte_modify(pte, newprot));
> 
> The pte_modify will clear the valid bit and set the prot_none bit (in order
> to create a present, faulting entry) but then your pte_mkhuge will come in
> and clobber that with a valid block entry.

Thanks Will, I'll re-work the pte_mkhuge/pte_huge logic and get a PROT_NONE
test case coded up.

Cheers,
-- 
Steve

> 
> Will


From robherring2 at gmail.com  Wed May  1 09:06:56 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 1 May 2013 08:06:56 -0500
Subject: [PATCH] ARM: smp: call platform's cpu_die in ipi_cpu_stop
In-Reply-To: <20130418190923.GE14496@n2100.arm.linux.org.uk>
References: <1365251824-4852-1-git-send-email-kevin@bracey.fi>
 <1365251824-4852-2-git-send-email-kevin@bracey.fi>
 <20130418171801.GC14496@n2100.arm.linux.org.uk>
 <20130418182534.GD14496@n2100.arm.linux.org.uk>
 <20130418190923.GE14496@n2100.arm.linux.org.uk>
Message-ID: <CAL_JsqLFEF9o7SSCcU5isxRdKA+fQNkqOmAncOmtzeMW7KbMrA@mail.gmail.com>

On Thu, Apr 18, 2013 at 2:09 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, Apr 18, 2013 at 07:25:34PM +0100, Russell King - ARM Linux wrote:
>> On Thu, Apr 18, 2013 at 06:18:01PM +0100, Russell King - ARM Linux wrote:
>> > On Sat, Apr 06, 2013 at 03:37:04PM +0300, Kevin Bracey wrote:

[...]

>> Now, with this patch applied, we guarantee that we push out any data
>> that matters from the dying CPU before platform_cpu_kill() is called.
>> That should mean that shmobile can remove that whole cpu_dead thing.
>>
>> I've tested this on OMAP, and it appears to work from a simple test of
>> CPU hotplug.  This patch(set) also kills the cpu_disable() that tegra
>> has which is just a copy of the generic version.
>
> Okay, last version for tonight, with additional comments too, and a
> hole plugged if the powering down is done by the platform via
> cpu_die().
>
>  arch/arm/kernel/smp.c               |   42 +++++++++++++++++++++++++++++++---
>  arch/arm/mach-exynos/hotplug.c      |    1 -
>  arch/arm/mach-highbank/hotplug.c    |    4 ---

Looks like this just landed in -next and it breaks highbank build.
Run-time will also be broken. See the last commit to this file in
final 3.9 which will also conflict with this one. The problem is that
highbank_set_cpu_jump calls outer cache functions which take a
spinlock and pollute the L1 cache. This all goes away once PCSI
support goes in, but for now we need another spot to clear the jump
address or just drop the highbank change.

Rob


From gregkh at linuxfoundation.org  Wed May  1 09:30:16 2013
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Wed, 1 May 2013 06:30:16 -0700
Subject: [PATCH 1/7] tty: xuartps: Sort #includes alphabetically
In-Reply-To: <5180BB21.2080306@monstr.eu>
References: <1367366284-28304-1-git-send-email-soren.brinkmann@xilinx.com>
 <1367366284-28304-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130501000048.GA1840@kroah.com>
 <cbd8c55c-066b-4396-9a4b-97d58a93b573@DB8EHSMHS005.ehs.local>
 <20130501002321.GB7435@kroah.com> <5180BB21.2080306@monstr.eu>
Message-ID: <20130501133016.GA2977@kroah.com>

On Wed, May 01, 2013 at 08:50:09AM +0200, Michal Simek wrote:
> On 05/01/2013 02:23 AM, Greg Kroah-Hartman wrote:
> > On Tue, Apr 30, 2013 at 05:05:40PM -0700, S?ren Brinkmann wrote:
> >> On Tue, Apr 30, 2013 at 05:00:48PM -0700, Greg Kroah-Hartman wrote:
> >>> On Tue, Apr 30, 2013 at 04:57:58PM -0700, Soren Brinkmann wrote:
> >>>> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> >>>> CC: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> >>>> CC: Jiri Slaby <jslaby at suse.cz>
> >>>> CC: linux-serial at vger.kernel.org
> >>>
> >>> Why would you need/want to do this?
> >> I often come across duplicated includes. Having some kind of order helps
> >> avoiding that, imho.
> > 
> > We have a tool to handle duplicated includes, no need to put them in
> > sorted order for them to be detected.
> 
> What's the name of tool which does that?
> I have seen results from it but have never tried to find it out name and
> how to use it.

scripts/checkincludes.pl



From James.Bottomley at HansenPartnership.com  Wed May  1 09:55:54 2013
From: James.Bottomley at HansenPartnership.com (James Bottomley)
Date: Wed, 01 May 2013 06:55:54 -0700
Subject: [PATCH 10/21] [SCSI] nsp32: use mdelay instead of large udelay
 constants
In-Reply-To: <201304291521.14195.arnd@arndb.de>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <1366910944-3033663-11-git-send-email-arnd@arndb.de>
 <CALZLnaFeLcaGM7_McTZ=pKBRnpXk0AvqOTF=1YCqJv-53yk4XQ@mail.gmail.com>
 <201304291521.14195.arnd@arndb.de>
Message-ID: <1367416554.4791.8.camel@dabdike.int.hansenpartnership.com>


On Mon, 2013-04-29 at 15:21 +0200, Arnd Bergmann wrote:
> On Friday 26 April 2013, Masanori Goto wrote:
> > 2013/4/25 Arnd Bergmann <arnd at arndb.de>
> > >
> > > ARM cannot handle udelay for more than 2 miliseconds, so we
> > > should use mdelay instead for those.
> > >
> > 
> > Singed-off-by: GOTO Masanori <gotom at debian.or.jp>
> 
> Thanks. I assume you mean "Acked-by", not "Singed-off" as in "burnt"
> or "Signed-off" as a notification that you have applied it to your
> own git tree.
> 
> I'll keep the patch with an your "Acked-by" line in my tree unless
> James wants to apply to the scsi tree.

I can, certainly.  I'll be sending the first scsi set today, but I'll be
doing another one for just before the close of the merge window.

Goto-san, while I have your attention, is the nsp_cs driver orphaned? I
know it's not your driver, but you did once work with its author (YOKOTA
Hiroshi <yokota at netlab.is.tsukuba.ac.jp>) and I'm trying to get some
cleanup on the static functions in the header files.

Thanks,

James













From James.Bottomley at HansenPartnership.com  Wed May  1 09:55:54 2013
From: James.Bottomley at HansenPartnership.com (James Bottomley)
Date: Wed, 01 May 2013 06:55:54 -0700
Subject: [PATCH 10/21] [SCSI] nsp32: use mdelay instead of large udelay
 constants
In-Reply-To: <201304291521.14195.arnd@arndb.de>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <1366910944-3033663-11-git-send-email-arnd@arndb.de>
 <CALZLnaFeLcaGM7_McTZ=pKBRnpXk0AvqOTF=1YCqJv-53yk4XQ@mail.gmail.com>
 <201304291521.14195.arnd@arndb.de>
Message-ID: <1367416554.4791.8.camel@dabdike.int.hansenpartnership.com>


On Mon, 2013-04-29 at 15:21 +0200, Arnd Bergmann wrote:
> On Friday 26 April 2013, Masanori Goto wrote:
> > 2013/4/25 Arnd Bergmann <arnd at arndb.de>
> > >
> > > ARM cannot handle udelay for more than 2 miliseconds, so we
> > > should use mdelay instead for those.
> > >
> > 
> > Singed-off-by: GOTO Masanori <gotom at debian.or.jp>
> 
> Thanks. I assume you mean "Acked-by", not "Singed-off" as in "burnt"
> or "Signed-off" as a notification that you have applied it to your
> own git tree.
> 
> I'll keep the patch with an your "Acked-by" line in my tree unless
> James wants to apply to the scsi tree.

I can, certainly.  I'll be sending the first scsi set today, but I'll be
doing another one for just before the close of the merge window.

Goto-san, while I have your attention, is the nsp_cs driver orphaned? I
know it's not your driver, but you did once work with its author (YOKOTA
Hiroshi <yokota at netlab.is.tsukuba.ac.jp>) and I'm trying to get some
cleanup on the static functions in the header files.

Thanks,

James











--
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From steve.capper at linaro.org  Wed May  1 10:16:14 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed, 1 May 2013 15:16:14 +0100
Subject: [RFC PATCH 9/9] ARM64: mm: THP support.
In-Reply-To: <1367339448-21727-10-git-send-email-steve.capper@linaro.org>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-10-git-send-email-steve.capper@linaro.org>
Message-ID: <20130501141613.GA23462@linaro.org>

On Tue, Apr 30, 2013 at 05:30:48PM +0100, Steve Capper wrote:
> Bring Transparent HugePage support to ARM. The size of a
> transparent huge page depends on the normal page size. A
> transparent huge page is always represented as a pmd.
> 
> If PAGE_SIZE is 4K, THPs are 2MB.
> If PAGE_SIZE is 64K, THPs are 512MB.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> ---
>  arch/arm64/Kconfig                     |  3 +++
>  arch/arm64/include/asm/pgtable-hwdef.h |  1 +
>  arch/arm64/include/asm/pgtable.h       | 47 ++++++++++++++++++++++++++++++++++
>  arch/arm64/include/asm/tlb.h           |  6 +++++
>  arch/arm64/include/asm/tlbflush.h      |  2 ++
>  5 files changed, 59 insertions(+)
> 

[ ... ]

> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 4b7a058..06bfbd6 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h

[ ... ]

> +#define pmd_modify(pmd,newprot)	(__pmd(pmd_val(pmd) | pgprot_val(newprot)))
> +#define set_pmd_at(mm, addr, pmdp, pmd)	set_pmd(pmdp, pmd)

Apologies, I have over-simplified (and broke) pmd_modify whilst tidying up this
patch. It should mask off certain bits. I will send out a correction once
PROT_NONE support has been sorted as this will affect this code path too.

--
Steve


From catalin.marinas at arm.com  Wed May  1 10:22:06 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 1 May 2013 15:22:06 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130430210403.GA18076@schnuecks.de>
References: <20121008202040.GC4625@n2100.arm.linux.org.uk>
 <20121008230733.GA17819@schnuecks.de>
 <20121118211005.GW22106@titan.lakedaemon.net>
 <20130418111608.GF27197@titan.lakedaemon.net>
 <20130418112201.GQ14496@n2100.arm.linux.org.uk>
 <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
Message-ID: <20130501142206.GB17387@arm.com>

On Tue, Apr 30, 2013 at 10:04:03PM +0100, Simon Baatz wrote:
> On Tue, Apr 30, 2013 at 12:22:25PM +0100, Catalin Marinas wrote:
> > On Sun, Apr 21, 2013 at 11:06:30PM +0100, Simon Baatz wrote:
> > > On Thu, Apr 18, 2013 at 02:51:04PM +0100, Catalin Marinas wrote:
> > > > On Thu, Apr 18, 2013 at 12:40:16PM +0100, Jason Cooper wrote:
> ...
> > > 
> > > It is not the driver itself which is using the API, it is the
> > > generic scatterlist memory iterator. And I don't think that this is
> > > wrong, as I have tried to explain in [1].
> > 
> > Trying to remember what we've discussed over the past months on this
> > topic. It looks like sg_miter_stop() does the right thing in calling
> > flush_kernel_dcache_page(). Commit f8b63c1 (ARM: 6382/1: Remove
> > superfluous flush_kernel_dcache_page()) removed this function entirely.
> > The code previously had this comment - /* highmem pages are always
> > flushed upon kunmap already */ which I think it wasn't fully correct
> > either. The kunmap_atomic() flushes the caches but kunmap() doesn't, so
> > I suspect we only get the flushing if SG_MITER_ATOMIC.
> > 
> > So it looks to me like flush_kernel_dcache_page() should be implemented
> > even for highmem pages (with VIVT or aliasing VIPT, at least for non
> > kmap_atomic addresses by checking for FIXADDR_START). If highmem is
> > disabled, I suspect we still need this function since the calling code
> > doesn't care whether kmap/kunmap was a no-op. But can we keep it as a
> > simple call to __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE)?
> 
> My first version ([1]) had:
> 
> 	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
> 		__flush_kernel_dcache_page(page);
> 
> If I understand this correctly, you are proposing to remove the
> highmem exclusion.

The highmem exclusion may have been there originally because of a
comment suggesting that kunmap() does the flushing. This is the case
only for kunmap_atomic() AFAICT (and maybe we could remove that as well
and rely on flush_kernel_dcache_page() being called).

> And then in __flush_kernel_dcache_page():
> 
> 	mapping = page_mapping(page);
> 
> 	if (!mapping || mapping_mapped(mapping))
> 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> 
> I still prefer to have this condition here to avoid the flush when
> there is no user mapping at all.  This is handled by lazy flushing
> and is probably the most common case anyway (given how many people
> seem to be affected by this problem).

Looking at the old thread, you said there is a case when this condition
is not true (O_DIRECT case). If that's for a page cache page, then we
can handle it lazily (for anonymous pages I don't think we can rely on
lazy flushing since the kernel does not guarantee the clearing of the
PG_arch_1 bit).

> Additionally, although we can assume that the page is kmapped,
> page_address(page) can still be NULL for a highmem page, right?

It looks like kmap() always sets page_address(page) but I'm not sure
about kmap_atomic(), it doesn't seem to.

-- 
Catalin


From lee.jones at linaro.org  Wed May  1 10:26:38 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  1 May 2013 15:26:38 +0100
Subject: [PATCH] dmaengine: ste_dma40: Rectify incorrect configuration
 validation checking
Message-ID: <1367418399-30591-1-git-send-email-lee.jones@linaro.org>

If we compare an event's group (dev_type / 16) with STEDMA40_DEV_DST_MEMORY
(-1), the only way we'd obtain a positive result is if we passed -16 as a
device type, which is unfeasible. Instead, it would be much more sane to
compare STEDMA40_DEV_DST_MEMORY against the raw dev_type in order to expect
the expected result.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 3b83dee..c79853f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1771,19 +1771,19 @@ static int d40_validate_conf(struct d40_chan *d40c,
 	}
 
 	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
-	    dst_event_group == STEDMA40_DEV_DST_MEMORY) {
+	    conf->dst_dev_type == STEDMA40_DEV_DST_MEMORY) {
 		chan_err(d40c, "Invalid dst\n");
 		res = -EINVAL;
 	}
 
 	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
-	    src_event_group == STEDMA40_DEV_SRC_MEMORY) {
+	    conf->src_dev_type == STEDMA40_DEV_SRC_MEMORY) {
 		chan_err(d40c, "Invalid src\n");
 		res = -EINVAL;
 	}
 
-	if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
-	    dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
+	if (conf->src_dev_type == STEDMA40_DEV_SRC_MEMORY &&
+	    conf->dst_dev_type == STEDMA40_DEV_DST_MEMORY && is_log) {
 		chan_err(d40c, "No event line\n");
 		res = -EINVAL;
 	}
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  1 10:28:41 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 1 May 2013 15:28:41 +0100
Subject: [PATCH 08/32 v2] dmaengine: ste_dma40: Remove home-brew MAX()
 macro
In-Reply-To: <CACRpkdaaa+gmsimkJVmhwv+zE+4ZmgZQ=AtHPry9=_EMScMC=w@mail.gmail.com>
References: <1366279934-30761-1-git-send-email-lee.jones@linaro.org>
 <1366279934-30761-9-git-send-email-lee.jones@linaro.org>
 <20130424084912.GH17416@gmail.com>
 <CACRpkdaaa+gmsimkJVmhwv+zE+4ZmgZQ=AtHPry9=_EMScMC=w@mail.gmail.com>
Message-ID: <20130501142841.GF25256@gmail.com>

> > The current implementation of the DMA40's local MAX() macro evaluates
> > its arguments more times than is necessary and it not type checked.
> > This patch strips replaces it with a new, more efficient constant.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Reported-by: Harvey Harrison <harvey.harrison at gmail.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Ah this v2 version is OK, atleast it makes the kernel look nicer.
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Vinod, poke.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed May  1 10:42:13 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 1 May 2013 15:42:13 +0100
Subject: [PATCH 12/32] ARM: ux500: Remove superfluous 'psize' attribute
 from Audio platform data
In-Reply-To: <1366279934-30761-13-git-send-email-lee.jones@linaro.org>
References: <1366279934-30761-1-git-send-email-lee.jones@linaro.org>
 <1366279934-30761-13-git-send-email-lee.jones@linaro.org>
Message-ID: <20130501144213.GG25256@gmail.com>

On Thu, 18 Apr 2013, Lee Jones wrote:

> 'psize' is used to calculate the maximum DMA burst size. However it
> is only taken into consideration when editing the DMA channel's
> configuration. The Audio DMA platform data is only used to allocate
> a channel, not configure it. That will be done at a later date within
> the MSP driver.
> 
> We're also removing comments which are no longer required, as
> 'data_width' is no longer set in any device's platform data period.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/board-mop500-audio.c |   38 ------------------------------
>  1 file changed, 38 deletions(-)
> 
> diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
> index f012cfa..972bec0 100644
> --- a/arch/arm/mach-ux500/board-mop500-audio.c
> +++ b/arch/arm/mach-ux500/board-mop500-audio.c
> @@ -23,25 +23,13 @@
>  static struct stedma40_chan_cfg msp0_dma_rx = {
>  	.high_priority = true,
>  	.dir = STEDMA40_PERIPH_TO_MEM,
> -
>  	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
>  };
>  
>  static struct stedma40_chan_cfg msp0_dma_tx = {
>  	.high_priority = true,
>  	.dir = STEDMA40_MEM_TO_PERIPH,
> -
>  	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
>  };
>  
>  struct msp_i2s_platform_data msp0_platform_data = {
> @@ -53,25 +41,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
>  static struct stedma40_chan_cfg msp1_dma_rx = {
>  	.high_priority = true,
>  	.dir = STEDMA40_PERIPH_TO_MEM,
> -
>  	.dev_type = DB8500_DMA_DEV30_MSP3,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
>  };
>  
>  static struct stedma40_chan_cfg msp1_dma_tx = {
>  	.high_priority = true,
>  	.dir = STEDMA40_MEM_TO_PERIPH,
> -
>  	.dev_type = DB8500_DMA_DEV30_MSP1,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
>  };
>  
>  struct msp_i2s_platform_data msp1_platform_data = {
> @@ -83,29 +59,15 @@ struct msp_i2s_platform_data msp1_platform_data = {
>  static struct stedma40_chan_cfg msp2_dma_rx = {
>  	.high_priority = true,
>  	.dir = STEDMA40_PERIPH_TO_MEM,
> -
>  	.dev_type = DB8500_DMA_DEV14_MSP2,
> -
> -	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
> -	.src_info.psize = STEDMA40_PSIZE_LOG_1,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
> -
> -	/* data_width is set during configuration */
>  };
>  
>  static struct stedma40_chan_cfg msp2_dma_tx = {
>  	.high_priority = true,
>  	.dir = STEDMA40_MEM_TO_PERIPH,
> -
>  	.dev_type = DB8500_DMA_DEV14_MSP2,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
>  	.use_fixed_channel = true,
>  	.phy_channel = 1,
> -
> -	/* data_width is set during configuration */
>  };
>  
>  static struct platform_device *db8500_add_msp_i2s(struct device *parent,

Linus, poke.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From cov at codeaurora.org  Wed May  1 10:44:31 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Wed, 01 May 2013 10:44:31 -0400
Subject: [PATCH 6/4] arm64: Move to generic sched_clock infrastructure
In-Reply-To: <20130501091108.GB10984@arm.com>
References: <1366417746-24990-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-2-git-send-email-sboyd@codeaurora.org>
 <20130501091108.GB10984@arm.com>
Message-ID: <51812A4F.7060400@codeaurora.org>

On 05/01/2013 05:11 AM, Catalin Marinas wrote:
> On Wed, May 01, 2013 at 01:54:35AM +0100, Stephen Boyd wrote:
>> Use the generic sched_clock infrastructure instead of rolling our
>> own. This has the added benefit of fixing suspend/resume as
>> outlined in 6a4dae5 (ARM: 7565/1: sched: stop sched_clock()
>> during suspend, 2012-10-23) and correcting the timestamps when
>> the hardware returns a value instead of 0 upon the first read.
>>
>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> 
> Looks ok.
> 
> Acked-by: Catalin Marinas <catalin.marinas at arm.com>

I built and ran this change and dependencies on top of Catalin's
soc-armv8-model branch [1] and was able to verify that it fixed the printk
timestamp jump.

1.
http://git.kernel.org/cgit/linux/kernel/git/cmarinas/linux-aarch64.git/log/?h=soc-armv8-model

Tested-by: Christopher Covington <cov at codeaurora.org>

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From will.deacon at arm.com  Wed May  1 10:46:22 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 15:46:22 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <CAAhSdy14ofVEdrfc2r3PqLFrTA9kvM+oBVWmXNSWBq2xTxMLiQ@mail.gmail.com>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAAhSdy14ofVEdrfc2r3PqLFrTA9kvM+oBVWmXNSWBq2xTxMLiQ@mail.gmail.com>
Message-ID: <20130501144622.GA24055@mudshark.cambridge.arm.com>

On Wed, May 01, 2013 at 07:53:49AM +0100, Anup Patel wrote:
> On Wed, May 1, 2013 at 7:37 AM, Rusty Russell <rusty at rustcorp.com.au> wrote:
> > Alexander Graf <agraf at suse.de> writes:
> >> There are not device specific registers in
> >> virtio-console. Virtio-console lives behind a virtio bus which doesn't
> >> know what these registers are.
> >
> > You're not going to make coherent arguments without reading that actual
> > patch we're discussing.  And you're going to just waste everyone else's
> > time.
> >
> >> Even if you shove it into config space,
> >
> > Which is what the patch does...
> >
> >> it'd be broken because config access happens without intercepts on
> >> some platforms.
> >
> > But people keep assuming it, which is one reason virtio_ccw switched
> > from passive lguest-style config to active.  Only lguest and the old kvm
> > virtio use it, and lguest can change.
> >
> > An emergency output is a reasonable idea, and this is a reasonable
> > implementation.  The question is practical: will it be used?  Because we
> > don't implement reasonable ideas which aren't going to be used.
> 
> We are already using it for Guest bring-up on APM ARM64 board using
> KVMTOOL and so far it has been really helpful in debugging KVM ARM64
> guest issues.
> 
> Also, this is a very useful debugging method for Guest bring-up on
> other architectures supported by KVM and other Hypervisors that
> support VirtIO.

FWIW: I've hacked together a small set of patches allowing us to use the
x86 ioport peripherals on arm/arm64 in kvmtool. This means you can use the
8250 for earlyprintk on the latter, and even as the main console if you
like since it has a device-tree binding.

I'll post the patches as an RFC to the kvm list.

Will


From will.deacon at arm.com  Wed May  1 11:24:21 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 16:24:21 +0100
Subject: RFC: Unified DMA allocation algorithms
In-Reply-To: <51785024.40305@codeaurora.org>
References: <51785024.40305@codeaurora.org>
Message-ID: <20130501152421.GB24055@mudshark.cambridge.arm.com>

On Wed, Apr 24, 2013 at 10:35:32PM +0100, Laura Abbott wrote:
> Hi all,

Hi Laura,

> I've been looking at a better way to do custom dma allocation algorithms 
> in a similar style to Ion heaps. Most drivers/clients have come up with 
> a series of semi-standard ways to get memory (CMA, memblock_reserve, 
> discontiguous pages etc.) . As these allocation schemes get more and 
> more complex, there needs to be a since place where all clients (Ion 
> based driver vs. DRM driver vs. ???)  can independently take advantage 
> of any optimizations and call a single API for the backing allocations.

Makes sense.

> The dma_map_ops take care of almost everything needed for abstraction
> but the question is where should new allocation algorithms be located?
> Most of the work has been added to either arm/mm/dma-mapping.c or
> dma-contiguous.c . My current thought:
> 
> 1) split out the dma_map_ops currently in dma-mapping.c into separate 
> files (dma-mapping-common.c, dma-mapping-iommu.c)
> 2) Extend dma-contiguous.c to support memblock_reserve memory
> 3) Place additional algorithms in either arch/arm/mm or 
> drivers/base/dma-alloc/ as appropriate to the code. This is the part 
> where I'm most unsure about the direction.
> 
> I don't have anything written yet but I plan to draft some patches 
> assuming the proposed approach sounds reasonable and no one else has 
> started on something similar already.
> 
> Thoughts? Opinions?

The only thing I'd add (which unfortunately doesn't help to answer your
questions!) is that it would be good to see the various allocation
strategies parameterised by IOMMU constraints. For example:

	- Input address sizes / windows
	- Mapping granules (i.e. not just PAGE_SIZE)
	- Streaming hints for physically contiguous allocation

dma-mapping does some of this, but it's still not ideal or generalised (for
example, it allocates a bitmap for the entire virtual space for each
domain). I'd welcome any generalisation in this area.

Will


From axel.lin at ingics.com  Wed May  1 11:31:01 2013
From: axel.lin at ingics.com (Axel Lin)
Date: Wed, 01 May 2013 23:31:01 +0800
Subject: [RFT][PATCH 1/2] clk: wm831x: Fix update wrong register for
 enable/disable FLL
Message-ID: <1367422261.8160.1.camel@phoenix>

According to the datasheet, FLL Enable is controlled by
R16530 (4092h) FLL Control1
        BIT 0: FLL Enable
                0 = Disable
                1 = Enable

Thus the code should update WM831X_FLL_CONTROL_1 register rather than
WM831X_FLL_CONTROL_2 register.

Also fixes a trivial typo in dev_crit message.

Signed-off-by: Axel Lin <axel.lin at ingics.com>
---
 drivers/clk/clk-wm831x.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 16ed068..4bdf0b0 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -97,7 +97,7 @@ static int wm831x_fll_prepare(struct clk_hw *hw)
 	struct wm831x *wm831x = clkdata->wm831x;
 	int ret;
 
-	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
 			      WM831X_FLL_ENA, WM831X_FLL_ENA);
 	if (ret != 0)
 		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
@@ -114,9 +114,9 @@ static void wm831x_fll_unprepare(struct clk_hw *hw)
 	struct wm831x *wm831x = clkdata->wm831x;
 	int ret;
 
-	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
 	if (ret != 0)
-		dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
+		dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
 }
 
 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
-- 
1.8.1.2





From axel.lin at ingics.com  Wed May  1 11:32:05 2013
From: axel.lin at ingics.com (Axel Lin)
Date: Wed, 01 May 2013 23:32:05 +0800
Subject: [RFT][PATCH 2/2] clk: wm831x: Fix wm831x_clkout_get_parent
In-Reply-To: <1367422261.8160.1.camel@phoenix>
References: <1367422261.8160.1.camel@phoenix>
Message-ID: <1367422325.8160.2.camel@phoenix>

Current code looks strange because calling wm831x_clkout_set_parent() with 0 as
parent parameter, wm831x_clkout_get_parent() will return 1.

According to the datasheet:
R16528 (4090h) Clock Control1
        BIT 0: CLKOUT output source select
                0 = FLL output
                1 = 32.768kHz oscillator

Thus fix the entry order in wm831x_clkout_parents[] to make it has
the same meaning as the datasheet and make the return value
of wm831x_clkout_get_parent() consistent with the parent pass to
wm831x_clkout_set_parent().

Signed-off-by: Axel Lin <axel.lin at ingics.com>
---
 drivers/clk/clk-wm831x.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 4bdf0b0..58d08a6 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -299,8 +299,8 @@ static void wm831x_clkout_unprepare(struct clk_hw *hw)
 }
 
 static const char *wm831x_clkout_parents[] = {
-	"xtal",
 	"fll",
+	"xtal",
 };
 
 static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
@@ -318,9 +318,9 @@ static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
 	}
 
 	if (ret & WM831X_CLKOUT_SRC)
-		return 0;
-	else
 		return 1;
+	else
+		return 0;
 }
 
 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
-- 
1.8.1.2





From dirk.behme at gmail.com  Wed May  1 11:32:14 2013
From: dirk.behme at gmail.com (Dirk Behme)
Date: Wed, 01 May 2013 17:32:14 +0200
Subject: [PATCH v3] ARM: imx: replicate the diagnostic register of boot
 cpu into secondary cores
In-Reply-To: <20130426134722.GA1943@S2101-09.ap.freescale.net>
References: <1366948645-12060-1-git-send-email-shawn.guo@linaro.org>
 <20130426132130.GE30858@mudshark.cambridge.arm.com>
 <20130426134722.GA1943@S2101-09.ap.freescale.net>
Message-ID: <5181357E.3090805@gmail.com>

Am 26.04.2013 15:47, schrieb Shawn Guo:
> On Fri, Apr 26, 2013 at 02:21:30PM +0100, Will Deacon wrote:
>>> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
>>> index a58c8b0..cd87970 100644
>>> --- a/arch/arm/mach-imx/headsmp.S
>>> +++ b/arch/arm/mach-imx/headsmp.S
>>> @@ -18,8 +18,20 @@
>>>   	.section ".text.head", "ax"
>>>
>>>   #ifdef CONFIG_SMP
>>> +diag_reg_offset:
>>> +	.word	g_diag_reg - .
>>> +
>>> +	.macro	set_diag_reg
>>> +	adr	r0, diag_reg_offset
>>> +	ldr	r1, [r0]
>>> +	add	r1, r1, r0		@ r1 = physical &g_diag_reg
>>> +	ldr	r0, [r1]
>>> +	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
>>> +	.endm
>>
>> Why not re-read the register directly, rather than mrc on the current core?
>
> I do not understand the comment.  What do you mean by "re-read"?  Read
> the register on secondary cores will only return us 0, as bootloader
> only sets up the register on cpu0.  The macro set_diag_reg only runs on
> secondary cores to copy cpu0's diagnostic bits.  I think it's safe on
> SMP.

Any news on this?

Thanks

Dirk



From sergei.shtylyov at cogentembedded.com  Wed May  1 11:34:17 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 01 May 2013 19:34:17 +0400
Subject: [PATCH v3 4/5] ARM: shmobile: BOCK-W: add VIN and ML86V7667
 support
In-Reply-To: <20130501090909.GA2562@verge.net.au>
References: <201304232118.43686.sergei.shtylyov@cogentembedded.com>
 <201304232132.52741.sergei.shtylyov@cogentembedded.com>
 <517B06FA.3000303@cogentembedded.com> <20130501090909.GA2562@verge.net.au>
Message-ID: <518135F9.9010509@cogentembedded.com>

Hello.

On 01-05-2013 13:09, Simon Horman wrote:

>> On 04/23/2013 09:32 PM, Sergei Shtylyov wrote:

>>> From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

>>> Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and
>>> register VIN0/1 devices with the ML86V7667 specific platform data.

>>> Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
>>> [Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate
>>> #include, annotated all platform data as '__initdata'.]
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

>>> ---
>>> Changes since version 2:
>>> - removed duplicate #include <linux/pinctrl/machine.h>;
>>> - annotated all platform data as '__initdata' since they're kmemdup()'ed while
>>>    registering the platform devices anyway;
>>> - resolved rejects, refreshed the patch.

>>>   arch/arm/mach-shmobile/board-bockw.c |   39 +++++++++++++++++++++++++++++++++++
>>>   1 file changed, 39 insertions(+)

>>> Index: renesas/arch/arm/mach-shmobile/board-bockw.c
>>> ===================================================================
>>> --- renesas.orig/arch/arm/mach-shmobile/board-bockw.c
>>> +++ renesas/arch/arm/mach-shmobile/board-bockw.c

>> [...]

>>> @@ -80,6 +101,16 @@ static const struct pinctrl_map bockw_pi
>>>   				  "sdhi0_data4", "sdhi0"),
>>>   	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
>>>   				  "sdhi0_wp", "sdhi0"),
>>> +	/* VIN0 */
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.0", "pfc-r8a7778",
>>> +				  "vin0_clk", "vin0"),
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.0", "pfc-r8a7778",
>>> +				  "vin0_data8", "vin0"),
>>> +	/* VIN1 */
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.1", "pfc-r8a7778",
>>> +				  "vin1_clk", "vin1"),
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.1", "pfc-r8a7778",
>>> +				  "vin1_data8", "vin1"),
>>>   };

>>      It turned out that VIN1 signal VI1_CLK conflicts with Ether
>> signal ETH_REF_CLK.
>> So I'm a bit at a loss here: whether I should totally remove VIN1
>> device if I'm going
>> to add Ether device, or add a BOCK-W specific submenu to Kconfig, or
>> add driver
>> specific #ifdef's in the code to disable VIN1 if sh_eth driver is
>> enabled?...

> My preference, in order is:

> * Remove VIN1 (is it used?)

    At least video decoders are connected to both VIN0 and VIN1.

> * Kconfig-foo
> * #ifdef nastiness

    I took the 3rd approach but luckily it was possible without #ifdef, using 
*if* (!IS_ENABLED(CONFIG_SH_ETH)) statement. Working patch posted on Monday.

WBR, Sergei



From s.hauer at pengutronix.de  Wed May  1 11:36:09 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 1 May 2013 17:36:09 +0200
Subject: [PATCH 3/3] ARM: dts: Add MC13783 support for i.MX27 Phytec
 PCM038 module
In-Reply-To: <1367405219-19078-3-git-send-email-shc_work@mail.ru>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
 <1367405219-19078-3-git-send-email-shc_work@mail.ru>
Message-ID: <20130501153609.GA31135@pengutronix.de>

On Wed, May 01, 2013 at 02:46:59PM +0400, Alexander Shiyan wrote:
> Added MC13783 node to imx27-phytec-phycore DT file.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  arch/arm/boot/dts/imx27-phytec-phycore.dts | 92 ++++++++++++++++++++++++++++++
>  1 file changed, 92 insertions(+)

You can merge this with the previous patch.

> 
> diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
> index b0e9372..5c4fea9 100644
> --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
> +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
> @@ -76,6 +76,98 @@
>  	fsl,spi-num-chipselects = <1>;
>  	cs-gpios = <&gpio4 28 0>;
>  	status = "okay";
> +
> +	pmic: mc13783 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "fsl,mc13783";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <23 0x4>;
> +		fsl,mc13xxx-uses-adc;
> +
> +		regulators {
> +			sw1a_reg: sw1a {
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <1200000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +			sw1b_reg: sw1b {

Please add a blank line after each node.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From will.deacon at arm.com  Wed May  1 11:38:28 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 16:38:28 +0100
Subject: [PATCH v3] ARM: imx: replicate the diagnostic register of boot
 cpu into secondary cores
In-Reply-To: <5181357E.3090805@gmail.com>
References: <1366948645-12060-1-git-send-email-shawn.guo@linaro.org>
 <20130426132130.GE30858@mudshark.cambridge.arm.com>
 <20130426134722.GA1943@S2101-09.ap.freescale.net>
 <5181357E.3090805@gmail.com>
Message-ID: <20130501153828.GC24055@mudshark.cambridge.arm.com>

On Wed, May 01, 2013 at 04:32:14PM +0100, Dirk Behme wrote:
> Am 26.04.2013 15:47, schrieb Shawn Guo:
> > On Fri, Apr 26, 2013 at 02:21:30PM +0100, Will Deacon wrote:
> >>> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
> >>> index a58c8b0..cd87970 100644
> >>> --- a/arch/arm/mach-imx/headsmp.S
> >>> +++ b/arch/arm/mach-imx/headsmp.S
> >>> @@ -18,8 +18,20 @@
> >>>   	.section ".text.head", "ax"
> >>>
> >>>   #ifdef CONFIG_SMP
> >>> +diag_reg_offset:
> >>> +	.word	g_diag_reg - .
> >>> +
> >>> +	.macro	set_diag_reg
> >>> +	adr	r0, diag_reg_offset
> >>> +	ldr	r1, [r0]
> >>> +	add	r1, r1, r0		@ r1 = physical &g_diag_reg
> >>> +	ldr	r0, [r1]
> >>> +	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
> >>> +	.endm
> >>
> >> Why not re-read the register directly, rather than mrc on the current core?
> >
> > I do not understand the comment.  What do you mean by "re-read"?  Read
> > the register on secondary cores will only return us 0, as bootloader
> > only sets up the register on cpu0.  The macro set_diag_reg only runs on
> > secondary cores to copy cpu0's diagnostic bits.  I think it's safe on
> > SMP.
> 
> Any news on this?

Well, I don't like copying the register value over from CPU0. I'd rather we
orr'd in the bits we actually need, like we would in __v7_setup. Perhaps the
code there should be factored out into arm_errata_xxxx asm macros, so
platforms can invoke them if they need to without breaking non-secure boot
for multi-platform kernels.

Will


From soren.brinkmann at xilinx.com  Wed May  1 11:39:35 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Wed, 1 May 2013 08:39:35 -0700
Subject: [PATCH 1/7] tty: xuartps: Sort #includes alphabetically
In-Reply-To: <20130501002321.GB7435@kroah.com>
References: <1367366284-28304-1-git-send-email-soren.brinkmann@xilinx.com>
 <1367366284-28304-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130501000048.GA1840@kroah.com>
 <cbd8c55c-066b-4396-9a4b-97d58a93b573@DB8EHSMHS005.ehs.local>
 <20130501002321.GB7435@kroah.com>
Message-ID: <79ff34b1-0494-4118-a60d-cd5b536d3daa@VA3EHSMHS006.ehs.local>

On Tue, Apr 30, 2013 at 05:23:21PM -0700, Greg Kroah-Hartman wrote:
> On Tue, Apr 30, 2013 at 05:05:40PM -0700, S?ren Brinkmann wrote:
> > On Tue, Apr 30, 2013 at 05:00:48PM -0700, Greg Kroah-Hartman wrote:
> > > On Tue, Apr 30, 2013 at 04:57:58PM -0700, Soren Brinkmann wrote:
> > > > Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> > > > CC: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > > > CC: Jiri Slaby <jslaby at suse.cz>
> > > > CC: linux-serial at vger.kernel.org
> > > 
> > > Why would you need/want to do this?
> > I often come across duplicated includes. Having some kind of order helps
> > avoiding that, imho.
> 
> We have a tool to handle duplicated includes, no need to put them in
> sorted order for them to be detected.
During conflict resolution, I find it easier when there is some order.
Anyway, consider it dropped.

	S?ren




From shc_work at mail.ru  Wed May  1 11:40:37 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Wed, 01 May 2013 19:40:37 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSCAzLzNdIEFSTTogZHRzOiBBZGQgTUMxMzc4MyBzdXBw?=
 =?UTF-8?B?b3J0IGZvciBpLk1YMjcgUGh5dGVjIFBDTTAzOCBtb2R1bGU=?=
In-Reply-To: <20130501153609.GA31135@pengutronix.de>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
 <1367405219-19078-3-git-send-email-shc_work@mail.ru>
 <20130501153609.GA31135@pengutronix.de>
Message-ID: <1367422837.138582176@f94.mail.ru>

> On Wed, May 01, 2013 at 02:46:59PM +0400, Alexander Shiyan wrote:
> > Added MC13783 node to imx27-phytec-phycore DT file.
> > 
> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > ---
> >  arch/arm/boot/dts/imx27-phytec-phycore.dts | 92 ++++++++++++++++++++++++++++++
> >  1 file changed, 92 insertions(+)
> 
> You can merge this with the previous patch.

Part 2 just adds a SPI host for the target. Is this merge is really necessary?

---

From robherring2 at gmail.com  Wed May  1 11:54:30 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 1 May 2013 10:54:30 -0500
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <1366910944-3033663-4-git-send-email-arnd@arndb.de>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <1366910944-3033663-4-git-send-email-arnd@arndb.de>
Message-ID: <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>

On Thu, Apr 25, 2013 at 12:28 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> The irqchip_init function is only available when building
> with CONFIG_OF enabled, which causes this build failure for
> bonito_defconfig:
>
> arch/arm/mach-shmobile/built-in.o: In function `r8a7740_init_irq_of':
> :(.init.text+0x580): undefined reference to `irqchip_init'
>
> This makes both the OF and the ATAGS portion of the driver
> conditional, which avoids the build error and also results
> in smaller object code if not both are enabled, without the
> need for an #ifdef.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Bastian Hecht <hechtb+renesas at gmail.com>
> Cc: Simon Horman <horms+renesas at verge.net.au>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> ---
>  arch/arm/mach-shmobile/intc-r8a7740.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
> index 8871f77..5dc57f1 100644
> --- a/arch/arm/mach-shmobile/intc-r8a7740.c
> +++ b/arch/arm/mach-shmobile/intc-r8a7740.c
> @@ -53,14 +53,23 @@ static void __init r8a7740_init_irq_common(void)
>
>  void __init r8a7740_init_irq_of(void)
>  {
> +       if (!IS_ENABLED(CONFIG_OF))
> +               return;
> +
>         irqchip_init();

Why not have an empty irqchip_init? I'd guess we'll need this on other
platforms and your default mach.

Rob


From lee.jones at linaro.org  Wed May  1 11:59:40 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  1 May 2013 16:59:40 +0100
Subject: [PATCH] dmaengine: ste_dma40: Only use addresses passed as
 configuration information
Message-ID: <1367423980-32716-1-git-send-email-lee.jones@linaro.org>

Addresses are passed in from the client's driver via the invocation of
dmaengine_slave_config(), so there's no need to fetch them from platform
data too, hardwired or otherwise. This is a great step forward, as it
elevates a large burden from platform data in the way of a look-up
table.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   51 ++++++++++-------------------------------------
 1 file changed, 11 insertions(+), 40 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index a4ce204..f00a428 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1760,22 +1760,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
 		res = -EINVAL;
 	}
 
-	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
-	    d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid TX channel address (%d)\n",
-			 conf->dev_type);
-		res = -EINVAL;
-	}
-
-	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
-	    d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid RX channel address (%d)\n",
-			 conf->dev_type);
-		res = -EINVAL;
-	}
-
 	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
 		/*
 		 * DMAC HW supports it. Will be added to this driver,
@@ -2310,14 +2294,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
 	if (sg_next(&sg_src[sg_len - 1]) == sg_src)
 		desc->cyclic = true;
 
-	if (direction != DMA_TRANS_NONE) {
-		dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
-
-		if (direction == DMA_DEV_TO_MEM)
-			src_dev_addr = dev_addr;
-		else if (direction == DMA_MEM_TO_DEV)
-			dst_dev_addr = dev_addr;
-	}
+	if (direction == DMA_DEV_TO_MEM)
+		src_dev_addr = chan->runtime_addr;
+	else if (direction == DMA_MEM_TO_DEV)
+		dst_dev_addr = chan->runtime_addr;
 
 	if (chan_is_logical(chan))
 		ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
@@ -2764,15 +2744,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	dst_maxburst = config->dst_maxburst;
 
 	if (config->direction == DMA_DEV_TO_MEM) {
-		dma_addr_t dev_addr_rx =
-			d40c->base->plat_data->dev_rx[cfg->dev_type];
-
 		config_addr = config->src_addr;
-		if (dev_addr_rx)
-			dev_dbg(d40c->base->dev,
-				"channel has a pre-wired RX address %08x "
-				"overriding with %08x\n",
-				dev_addr_rx, config_addr);
+
 		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for peripheral "
@@ -2787,15 +2760,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 			dst_maxburst = src_maxburst;
 
 	} else if (config->direction == DMA_MEM_TO_DEV) {
-		dma_addr_t dev_addr_tx =
-			d40c->base->plat_data->dev_tx[cfg->dev_type];
-
 		config_addr = config->dst_addr;
-		if (dev_addr_tx)
-			dev_dbg(d40c->base->dev,
-				"channel has a pre-wired TX address %08x "
-				"overriding with %08x\n",
-				dev_addr_tx, config_addr);
+
 		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for memory "
@@ -2815,6 +2781,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 		return -EINVAL;
 	}
 
+	if (config_addr <= 0) {
+		dev_err(d40c->base->dev, "no address supplied\n");
+		return -EINVAL;
+	}
+
 	if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
 		dev_err(d40c->base->dev,
 			"src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  1 12:01:10 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  1 May 2013 17:01:10 +0100
Subject: [PATCH] dmaengine: ste_dma40: Remove redundant address fetching
 function
Message-ID: <1367424070-326-1-git-send-email-lee.jones@linaro.org>

Addresses are now stored in local data structures and are easy to
obtain, thus a specialist function used to fetch them is now surplus
to requirement.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index f00a428..18d9e12 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2250,24 +2250,6 @@ err:
 	return NULL;
 }
 
-static dma_addr_t
-d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
-{
-	struct stedma40_platform_data *plat = chan->base->plat_data;
-	struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
-	dma_addr_t addr = 0;
-
-	if (chan->runtime_addr)
-		return chan->runtime_addr;
-
-	if (direction == DMA_DEV_TO_MEM)
-		addr = plat->dev_rx[cfg->dev_type];
-	else if (direction == DMA_MEM_TO_DEV)
-		addr = plat->dev_tx[cfg->dev_type];
-
-	return addr;
-}
-
 static struct dma_async_tx_descriptor *
 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
 	    struct scatterlist *sg_dst, unsigned int sg_len,
-- 
1.7.10.4



From lorenzo.pieralisi at arm.com  Wed May  1 12:18:27 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Wed,  1 May 2013 17:18:27 +0100
Subject: [RFC PATCH v2] ARM CCI support
Message-ID: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>

This patch is an updated of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/162539.html

Patch depends on commit:

id: 0c91e7e07ebf08092bf8e28d8cd8d420732fc716

"ARM: cacheflush: add synchronization helpers for mixed cache state accesses"

in RMK tree:

http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-arm.git

branch: devel-stable

main changes in v2:
 - Changed way masters are connected to CCI slave ports in DT
   # now every master has to declare a phandle to a CCI control IF
 - Fixed warning split on different lines
 - Added comments to disable function
 - Moved driver to non-hotpluggable API (registration and probing bundled
   together)
 - Upgraded cache flushing API
 - Reworked the driver to use devm primitives
 - Added disable/enable by index API
 - Fixed port enable and added macro for snoops/DVM control

ARM multi-cluster systems rely on the cache coherent interconnect (CCI) to
support inter-cluster cache coherency and distributed virtual memory (DVM)
messaging.

CCI kernel driver requires tweaks to the kernel and device tree
bindings in order to link specific resources to groups of logical CPUs
so that resources can be associated to specific cpu sets (slave ports can
be associated with a set of CPUs which are part of a cluster).

CCI slave ports must be associated with specific bus masters in the system so
that whenever a CCI operation is requested for a specific master (ie disable
its CCI slave port, read its PMU counters) the association can be carried out
dynamically in the OS through dynamically built data structures.
Bus masters in the system connected to CCI ports must define device tree
properties, as described in the documentation contained in the patch, in order
to explicitly connect ports and allow the OS to build up the required data
structures.

The current CCI DT bindings define the CCI address space as the same one
as the root device tree node, which means that the CCI bus can address the
entire address space visible to CPUs.

Lorenzo Pieralisi (1):
  drivers: bus: add ARM CCI support

 Documentation/devicetree/bindings/arm/cci.txt | 161 +++++++++++
 drivers/bus/Kconfig                           |   7 +
 drivers/bus/Makefile                          |   2 +
 drivers/bus/arm-cci.c                         | 372 ++++++++++++++++++++++++++
 include/linux/arm-cci.h                       |  59 ++++
 5 files changed, 601 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cci.txt
 create mode 100644 drivers/bus/arm-cci.c
 create mode 100644 include/linux/arm-cci.h

-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Wed May  1 12:18:28 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Wed,  1 May 2013 17:18:28 +0100
Subject: [RFC PATCH v2] drivers: bus: add ARM CCI support
In-Reply-To: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>

On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.

This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.

Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.

CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.

Documentation describing the CCI DT bindings is provided with the patch.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 Documentation/devicetree/bindings/arm/cci.txt | 161 +++++++++++
 drivers/bus/Kconfig                           |   7 +
 drivers/bus/Makefile                          |   2 +
 drivers/bus/arm-cci.c                         | 372 ++++++++++++++++++++++++++
 include/linux/arm-cci.h                       |  59 ++++
 5 files changed, 601 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cci.txt
 create mode 100644 drivers/bus/arm-cci.c
 create mode 100644 include/linux/arm-cci.h

diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
new file mode 100644
index 0000000..384b460
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -0,0 +1,161 @@
+=======================================================
+ARM CCI cache coherent interconnect binding description
+=======================================================
+
+ARM multi-cluster systems maintain intra-cluster coherency through a
+cache coherent interconnect (CCI) that is capable of monitoring bus
+transactions and manage coherency, TLB invalidations and memory barriers.
+
+It allows snooping and distributed virtual memory message broadcast across
+clusters, through memory mapped interface, with a global control register
+space and multiple sets of interface control registers, one per slave
+interface.
+
+Bindings for the CCI node follow the ePAPR standard, available from:
+
+www.power.org/documentation/epapr-version-1-1/
+
+with the addition of the bindings described in this document which are
+specific to ARM.
+
+* CCI interconnect node
+
+	Description: Describes a CCI cache coherent Interconnect component
+
+	Node name must be "cci".
+	Node's parent must be the root node /, and the address space visible
+	through the CCI interconnect is the same as the one seen from the
+	root node (ie from CPUs perspective as per DT standard).
+	Every CCI node has to define the following properties:
+
+	- compatible
+		Usage: required
+		Value type: <string>
+		Definition: must be set to
+			"arm,cci-400"
+
+	- reg
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property. Specifies base physical
+			    address of CCI control registers common to all
+			    interfaces.
+
+	- ranges:
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property. Follow rules in the ePAPR for
+			    hierarchical bus addressing. CCI interfaces
+			    addresses refer to the parent node addressing
+			    scheme to declare their register bases.
+
+	CCI interconnect node can define the following child nodes:
+
+	- CCI control interface nodes
+
+		Node name must be "slave-if".
+		Parent node must be CCI interconnect node.
+
+		A CCI interface node must contain the following properties:
+		- interface-type:
+			Usage: required
+			Value type: <string>
+			Definition: must be set to one of {"ace", "ace-lite"}
+				    depending on the interface type the node
+				    represents.
+
+		- reg:
+			Usage: required
+			Value type: <prop-encoded-array>
+			Definition: the base address and size of the
+				    corresponding interface programming
+				    registers.
+
+* CCI interconnect bus masters
+
+	Description: masters in the device tree connected to a CCI port
+		     (inclusive of CPUs and their cpu nodes).
+
+	A CCI interconnect bus master node must contain the following
+	properties:
+
+	- cci-control-port:
+		Usage: required
+		Value type: <phandle>
+		Definition: a phandle containing the CCI control interface node
+			    the master is connected to.
+
+Example:
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		CPU0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			cci-control-port = <&cci_control1>;
+			reg = <0x0>;
+		};
+
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			cci-control-port = <&cci_control1>;
+			reg = <0x1>;
+		};
+
+		CPU2: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			cci-control-port = <&cci_control2>;
+			reg = <0x100>;
+		};
+
+		CPU3: cpu at 101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			cci-control-port = <&cci_control2>;
+			reg = <0x101>;
+		};
+
+	};
+
+	dma0: dma at 3000000 {
+		compatible = "arm,pl330", "arm,primecell";
+		cci-control-port = <&cci_control0>;
+		reg = <0x0 0x3000000 0x0 0x1000>;
+		interrupts = <10>;
+		#dma-cells = <1>;
+		#dma-channels = <8>;
+		#dma-requests = <32>;
+	};
+
+	cci at 2c090000 {
+		compatible = "arm,cci";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x2c090000 0 0x1000>;
+		ranges = <0x0 0x0 0x2c090000 0x6000>;
+
+		cci_control0 : slave-if at 1000 {
+			interface-type = "ace-lite";
+			reg = <0x1000 0x1000>;
+		};
+
+		cci_control1 : slave-if at 4000 {
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+
+		cci_control2 : slave-if at 5000 {
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
+		};
+	};
+
+This CCI node corresponds to a CCI component whose control registers sits
+at address 0x000000002c090000.
+CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
+CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
+CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 0f51ed6..38ea85c 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -19,4 +19,11 @@ config OMAP_INTERCONNECT
 
 	help
 	  Driver to enable OMAP interconnect error handling driver.
+
+config ARM_CCI
+	bool "ARM CCI driver support"
+	depends on ARM
+	help
+	  Driver supporting the CCI cache coherent interconnect for ARM
+	  platforms.
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 45d997c..2bd9947 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
 # Interconnect bus driver for OMAP SoCs.
 obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
+# CCI cache coherent interconnect for ARM platforms
+obj-$(CONFIG_ARM_CCI)		+= arm-cci.o
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
new file mode 100644
index 0000000..fb9e8e0
--- /dev/null
+++ b/drivers/bus/arm-cci.c
@@ -0,0 +1,372 @@
+/*
+ * CCI cache coherent interconnect driver
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+#include <asm/dt_affinity.h>
+#include <asm/outercache.h>
+#include <asm/smp_plat.h>
+
+#define DRIVER_NAME		"CCI"
+
+#define CCI_PORT_CTRL		0x0
+#define CCI_CTRL_STATUS		0xc
+
+#define CCI_ENABLE_SNOOP_REQ	0x1
+#define CCI_ENABLE_DVM_REQ	0x2
+#define CCI_ENABLE_REQ		(CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
+
+struct cci_nb_ports {
+	unsigned int nb_ace;
+	unsigned int nb_ace_lite;
+};
+
+enum cci_ace_port_type {
+	ACE_INVALID_PORT = 0x0,
+	ACE_PORT,
+	ACE_LITE_PORT,
+};
+
+struct cci_ace_port {
+	void __iomem *base;
+	int type;
+	struct device_node *dn;
+};
+
+static struct cci_ace_port *ports;
+static unsigned int nb_cci_ports;
+
+static void __iomem *cci_ctrl_base;
+#define INVALID_PORT_IDX	-1
+static int cpu_port[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_PORT_IDX };
+
+/*
+ * __cci_ace_get_port - Function to retrieve the port index connected to
+ *			a cpu or device.
+ *
+ * @dn = device node of the device to look-up
+ * @type = port type
+ *
+ * Return value:
+ *	- CCI port index if success
+ *	- -ENODEV if failure
+ */
+static int __cci_ace_get_port(struct device_node *dn, int type)
+{
+	int i;
+	bool ace_match;
+	struct device_node *cci_portn;
+
+	cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
+	for (i = 0; i < nb_cci_ports; i++) {
+		ace_match = ports[i].type == type;
+		if (ace_match && cci_portn == ports[i].dn)
+			return i;
+	}
+	return -ENODEV;
+}
+
+int cci_ace_get_port(struct device_node *dn)
+{
+	return __cci_ace_get_port(dn, ACE_LITE_PORT);
+}
+EXPORT_SYMBOL_GPL(cci_ace_get_port);
+
+static void __init cci_ace_init_ports(void)
+{
+	int port, ac, cpu;
+	u64 hwid;
+	const u32 *cell;
+	struct device_node *cpun, *cpus;
+
+	cpus = of_find_node_by_path("/cpus");
+	if (WARN(!cpus, "Missing cpus node, bailing out\n"))
+		return;
+
+	if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
+		ac = of_n_addr_cells(cpus);
+	/*
+	 * Port index look-up speeds up the function disabling ports by CPU,
+	 * since the logical to port index mapping is done once and does
+	 * not change after system boot.
+	 * The stashed index array is initialized for all possible CPUs
+	 * at probe time.
+	 */
+	for_each_child_of_node(cpus, cpun) {
+		if (of_node_cmp(cpun->type, "cpu"))
+			continue;
+		cell = of_get_property(cpun, "reg", NULL);
+		if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
+			continue;
+		hwid = of_read_number(cell, ac);
+		cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
+		if (cpu < 0)
+			continue;
+		port = __cci_ace_get_port(cpun, ACE_PORT);
+		if (port < 0)
+			continue;
+		cpu_port[cpu] = port;
+	}
+
+	for_each_possible_cpu(cpu) {
+		WARN(cpu_port[cpu] == INVALID_PORT_IDX, "CPU %d has an invalid CCI port index\n",
+							cpu);
+	}
+}
+
+/*
+ * Functions to enable/disable a CCI interconnect slave port
+ *
+ * They are called by low-level power management code to disable slave
+ * interfaces snoops and DVM broadcast.
+ * Since they may execute with cache data allocation disabled and
+ * after the caches have been cleaned and invalidated the functions provide
+ * no explicit locking since they may run with D-cache disabled, so normal
+ * cacheable kernel locks based on ldrex/strex may not work.
+ * Locking has to be provided by BSP implementations to ensure proper
+ * operations.
+ */
+
+/*
+ * cci_port_control()
+ *	@port = index of the port to setup
+ *	@enable = if true enables the port, if false disables it
+ */
+static void notrace cci_port_control(unsigned int port, bool enable)
+{
+	void __iomem *base = ports[port].base;
+
+	writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
+	/*
+	 * This function is called from power down procedures
+	 * and must not execute any instruction that might
+	 * cause the processor to be put in a quiescent state
+	 * (eg wfi). Hence, cpu_relax() can not be added to this
+	 * read loop to optimize power, since it might hide possibly
+	 * disruptive operations.
+	 */
+	while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
+			;
+}
+
+/*
+ * cci_disable_port_by_cpu()
+ *	@mpidr = mpidr of the CPU whose CCI port should be disabled
+ *	Returns:
+ *		0 on success
+ *		-ENODEV on port look-up failure
+ *
+ * Disabling a CCI port for a CPU implies disabling the CCI port
+ * controlling that CPU cluster. Code disabling CPU CCI ports
+ * must make sure that the CPU running the code is the last active CPU
+ * in the cluster ie all other CPUs are quiescent in a low power state.
+ */
+int notrace cci_disable_port_by_cpu(u64 mpidr)
+{
+	int cpu = get_logical_index(mpidr & MPIDR_HWID_BITMASK);
+
+	if (cpu < 0 || cpu_port[cpu] == INVALID_PORT_IDX)
+		return -ENODEV;
+	cci_port_control(cpu_port[cpu], false);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
+
+/*
+ * __cci_control_port_by_device()
+ *	@dn = device node pointer of the device whose CCI port should be
+ *	      controlled
+ *	@enable = if true enables the port, if false disables it
+ *	Returns:
+ *		0 on success
+ *		-ENODEV on port look-up failure
+ */
+int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
+{
+	int port;
+
+	if (!dn)
+		return -ENODEV;
+
+	port = __cci_ace_get_port(dn, ACE_LITE_PORT);
+	if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
+				dn->full_name))
+		return -ENODEV;
+	cci_port_control(port, enable);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
+
+/*
+ * __cci_control_port_by_index()
+ *	@port = port index previously retrieved with cci_ace_get_port()
+ *	@enable = if true enables the port, if false disables it
+ *	Returns:
+ *		0 on success
+ *		-ENODEV on port index out of range
+ *		-EPERM if operation carried out on an ACE PORT
+ */
+int notrace __cci_control_port_by_index(u32 port, bool enable)
+{
+	if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
+		return -ENODEV;
+	/*
+	 * CCI control for ports connected to CPUS is extremely fragile
+	 * and must be made to go through a specific and controlled
+	 * interface (ie cci_disable_port_by_cpu(); control by general purpose
+	 * indexing is therefore disabled for ACE ports.
+	 */
+	if (ports[port].type == ACE_PORT)
+		return -EPERM;
+
+	cci_port_control(port, enable);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
+
+static const struct cci_nb_ports cci400_ports = {
+	.nb_ace = 2,
+	.nb_ace_lite = 3
+};
+
+static const struct of_device_id arm_cci_matches[] = {
+	{.compatible = "arm,cci-400", .data = &cci400_ports },
+	{},
+};
+
+static int __init cci_driver_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct cci_nb_ports const *cci_config;
+	int ret, i, nb_ace = 0, nb_ace_lite = 0;
+	struct device_node *np, *cp;
+	const char *match_str;
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	match = of_match_device(arm_cci_matches, &pdev->dev);
+
+	if (!match)
+		return -ENODEV;
+
+	cci_config = (struct cci_nb_ports const *)match->data;
+	nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
+	ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
+	if (!ports)
+		return -ENOMEM;
+
+	np = pdev->dev.of_node;
+
+	cci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
+
+	if (!cci_ctrl_base) {
+		dev_err(&pdev->dev, "unable to ioremap CCI ctrl\n");
+		ret = -ENXIO;
+		goto memalloc_err;
+	}
+
+	for_each_child_of_node(np, cp) {
+		i = nb_ace + nb_ace_lite;
+
+		if (i >= nb_cci_ports)
+			break;
+
+		if (of_property_read_string(cp, "interface-type",
+					    &match_str)) {
+			dev_err(&pdev->dev, "node %s missing interface-type property\n",
+				  cp->full_name);
+			continue;
+		}
+
+		if (strcmp(match_str, "ace")
+				&& strcmp(match_str, "ace-lite")) {
+			dev_err(&pdev->dev, "node %s containing invalid interface-type property, skipping it\n",
+					cp->full_name);
+			continue;
+		}
+
+		if (of_address_to_resource(cp, 0, res)) {
+			dev_err(&pdev->dev, "node %s failure in retrieving resources\n",
+				cp->full_name);
+			continue;
+		}
+
+		ports[i].base = devm_request_and_ioremap(&pdev->dev, res);
+
+		if (!ports[i].base) {
+			dev_err(&pdev->dev, "unable to ioremap CCI port %d\n",
+					    i);
+			continue;
+		}
+
+		if (!strcmp(match_str, "ace")) {
+			if (WARN_ON(nb_ace >= cci_config->nb_ace))
+				continue;
+			ports[i].type = ACE_PORT;
+			++nb_ace;
+		} else if (!strcmp(match_str, "ace-lite")) {
+			if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
+				continue;
+			ports[i].type = ACE_LITE_PORT;
+			++nb_ace_lite;
+		}
+		ports[i].dn = cp;
+	}
+	 /* initialize a stashed array of ACE ports to speed-up look-up */
+	cci_ace_init_ports();
+
+	/*
+	 * Multi-cluster systems may need this data when non-coherent, during
+	 * cluster power-up/power-down. Make sure it reaches main memory.
+	 */
+	sync_cache_w(&cci_ctrl_base);
+	__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
+	__sync_cache_range_w(cpu_port, sizeof cpu_port);
+	dev_info(&pdev->dev, "ARM CCI driver probed\n");
+	return 0;
+
+memalloc_err:
+
+	kfree(ports);
+	return ret;
+}
+
+static struct platform_driver cci_platform_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = DRIVER_NAME,
+		   .of_match_table = arm_cci_matches,
+	},
+};
+/*
+ * CCI is inherently a non-hotpluggable device, since it represents
+ * the CPUs access point to the interconnect system.
+ */
+static int __init cci_init(void)
+{
+	return platform_driver_probe(&cci_platform_driver, cci_driver_probe);
+}
+
+module_init(cci_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ARM CCI support");
diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
new file mode 100644
index 0000000..0e70942
--- /dev/null
+++ b/include/linux/arm-cci.h
@@ -0,0 +1,59 @@
+/*
+ * CCI cache coherent interconnect support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_ARM_CCI_H
+#define __LINUX_ARM_CCI_H
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct device_node;
+
+#ifdef CONFIG_ARM_CCI
+extern int cci_ace_get_port(struct device_node *dn);
+extern int cci_disable_port_by_cpu(u64 mpidr);
+extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
+extern int __cci_control_port_by_index(u32 port, bool enable);
+#else
+static inline int cci_ace_get_port(struct device_node *dn, bool cpu)
+{
+	return -ENODEV;
+}
+static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
+static inline int __cci_control_port_by_device(struct device_node *dn,
+					       bool enable)
+{
+	return -ENODEV;
+}
+static inline int __cci_control_port_by_index(u32 port, bool enable)
+{
+	return -ENODEV;
+}
+#endif
+#define cci_disable_port_by_device(dev) \
+	__cci_control_port_by_device(dev, false)
+#define cci_enable_port_by_device(dev) \
+	__cci_control_port_by_device(dev, true)
+#define cci_disable_port_by_index(dev) \
+	__cci_control_port_by_index(dev, false)
+#define cci_enable_port_by_index(dev) \
+	__cci_control_port_by_index(dev, true)
+
+#endif
-- 
1.8.2.2




From dirk.behme at gmail.com  Wed May  1 12:19:24 2013
From: dirk.behme at gmail.com (Dirk Behme)
Date: Wed, 01 May 2013 18:19:24 +0200
Subject: [PATCH v3] ARM: imx: replicate the diagnostic register of boot
 cpu into secondary cores
In-Reply-To: <20130501153828.GC24055@mudshark.cambridge.arm.com>
References: <1366948645-12060-1-git-send-email-shawn.guo@linaro.org>
 <20130426132130.GE30858@mudshark.cambridge.arm.com>
 <20130426134722.GA1943@S2101-09.ap.freescale.net>
 <5181357E.3090805@gmail.com>
 <20130501153828.GC24055@mudshark.cambridge.arm.com>
Message-ID: <5181408C.8090606@gmail.com>

Am 01.05.2013 17:38, schrieb Will Deacon:
> On Wed, May 01, 2013 at 04:32:14PM +0100, Dirk Behme wrote:
>> Am 26.04.2013 15:47, schrieb Shawn Guo:
>>> On Fri, Apr 26, 2013 at 02:21:30PM +0100, Will Deacon wrote:
>>>>> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
>>>>> index a58c8b0..cd87970 100644
>>>>> --- a/arch/arm/mach-imx/headsmp.S
>>>>> +++ b/arch/arm/mach-imx/headsmp.S
>>>>> @@ -18,8 +18,20 @@
>>>>>    	.section ".text.head", "ax"
>>>>>
>>>>>    #ifdef CONFIG_SMP
>>>>> +diag_reg_offset:
>>>>> +	.word	g_diag_reg - .
>>>>> +
>>>>> +	.macro	set_diag_reg
>>>>> +	adr	r0, diag_reg_offset
>>>>> +	ldr	r1, [r0]
>>>>> +	add	r1, r1, r0		@ r1 = physical &g_diag_reg
>>>>> +	ldr	r0, [r1]
>>>>> +	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
>>>>> +	.endm
>>>>
>>>> Why not re-read the register directly, rather than mrc on the current core?
>>>
>>> I do not understand the comment.  What do you mean by "re-read"?  Read
>>> the register on secondary cores will only return us 0, as bootloader
>>> only sets up the register on cpu0.  The macro set_diag_reg only runs on
>>> secondary cores to copy cpu0's diagnostic bits.  I think it's safe on
>>> SMP.
>>
>> Any news on this?
>
> Well, I don't like copying the register value over from CPU0.

Just for a better understanding: What's wrong with using the same 
register values on all CPUx? I.e. with copying them from CPU0? 
Shouldn't all CPUx use the same setting? Or at least the same errata 
bits enabled?

> I'd rather we
> orr'd in the bits we actually need, like we would in __v7_setup. Perhaps the
> code there should be factored out into arm_errata_xxxx asm macros,

I'm not as much in the details as Shawn and you, but it's my 
understanding that we moved the errata handling recently from the 
kernel to the boot loader? After this, we now find that the boot 
loader does the errata handling only for CPU0, and now we start to 
discuss to move it back to the kernel?

Sorry if my rough understanding is wrong ;)

Thanks for your help and best regards

Dirk



From catalin.marinas at arm.com  Wed May  1 12:21:11 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 1 May 2013 17:21:11 +0100
Subject: [RFC PATCH 7/9] ARM64: mm: HugeTLB support.
In-Reply-To: <1367339448-21727-8-git-send-email-steve.capper@linaro.org>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-8-git-send-email-steve.capper@linaro.org>
Message-ID: <20130501162111.GD17387@arm.com>

On Tue, Apr 30, 2013 at 05:30:46PM +0100, Steve Capper wrote:
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 43b0e9f..16aa780 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -185,6 +185,15 @@ config HW_PERF_EVENTS
>  	  Enable hardware performance counter support for perf events. If
>  	  disabled, perf events will use software events only.
>  
> +config SYS_SUPPORTS_HUGETLBFS
> +	def_bool y if MMU
> +
> +config ARCH_WANT_GENERAL_HUGETLB
> +	def_bool y if MMU

We could drop MMU here, I don't plan a uClinux port ;)

> diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
> new file mode 100644
> index 0000000..d00d72a
> --- /dev/null
> +++ b/arch/arm64/include/asm/hugetlb.h
...
> +static inline pte_t huge_ptep_get(pte_t *ptep)
> +{
> +	return *ptep;
> +}
> +
> +static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
> +				   pte_t *ptep, pte_t pte)
> +{
> +	set_pte_at(mm, addr, ptep, pte);
> +}
> +
> +static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
> +					 unsigned long addr, pte_t *ptep)
> +{
> +	ptep_clear_flush(vma, addr, ptep);
> +}
> +
> +static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
> +					   unsigned long addr, pte_t *ptep)
> +{
> +	ptep_set_wrprotect(mm, addr, ptep);
> +}
> +
> +static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
> +					    unsigned long addr, pte_t *ptep)
> +{
> +	return ptep_get_and_clear(mm, addr, ptep);
> +}
> +
> +static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
> +					     unsigned long addr, pte_t *ptep,
> +					     pte_t pte, int dirty)
> +{
> +	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
> +}
> +
> +static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
> +					  unsigned long addr, unsigned long end,
> +					  unsigned long floor,
> +					  unsigned long ceiling)
> +{
> +	free_pgd_range(tlb, addr, end, floor, ceiling);
> +}
...
> +static inline int huge_pte_none(pte_t pte)
> +{
> +	return pte_none(pte);
> +}
> +
> +static inline pte_t huge_pte_wrprotect(pte_t pte)
> +{
> +	return pte_wrprotect(pte);
> +}

Could we make these generic too?

> diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> new file mode 100644
> index 0000000..06c74e8
> --- /dev/null
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -0,0 +1,70 @@
> +/*
> + * arch/arm64/mm/hugetlbpage.c
> + *
> + * Copyright (C) 2013 Linaro Ltd.
> + *
> + * Based on arch/x86/mm/hugetlbpage.c.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#include <linux/init.h>
> +#include <linux/fs.h>
> +#include <linux/mm.h>
> +#include <linux/hugetlb.h>
> +#include <linux/pagemap.h>
> +#include <linux/err.h>
> +#include <linux/sysctl.h>
> +#include <asm/mman.h>
> +#include <asm/tlb.h>
> +#include <asm/tlbflush.h>
> +#include <asm/pgalloc.h>
> +
> +#ifndef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
> +int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
> +{
> +	return 0;
> +}
> +#endif
> +
> +struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
> +			      int write)
> +{
> +	return ERR_PTR(-EINVAL);
> +}
> +
> +int pmd_huge(pmd_t pmd)
> +{
> +	return (pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_SECT;
> +}
> +
> +int pud_huge(pud_t pud)
> +{
> +	return (pud_val(pud) & PMD_TYPE_MASK) == PMD_TYPE_SECT;
> +}

The types are mismatched here since pud_val() returns a pgd when
pgtable-nopud.h is used. I think we should defined PGD_TYPE_* in terms
of pgdval_t and PUD_TYPE_* just an alias for them.

-- 
Catalin


From will.deacon at arm.com  Wed May  1 12:38:17 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 May 2013 17:38:17 +0100
Subject: [PATCH v3] ARM: imx: replicate the diagnostic register of boot
 cpu into secondary cores
In-Reply-To: <5181408C.8090606@gmail.com>
References: <1366948645-12060-1-git-send-email-shawn.guo@linaro.org>
 <20130426132130.GE30858@mudshark.cambridge.arm.com>
 <20130426134722.GA1943@S2101-09.ap.freescale.net>
 <5181357E.3090805@gmail.com>
 <20130501153828.GC24055@mudshark.cambridge.arm.com>
 <5181408C.8090606@gmail.com>
Message-ID: <20130501163817.GD24055@mudshark.cambridge.arm.com>

On Wed, May 01, 2013 at 05:19:24PM +0100, Dirk Behme wrote:
> Am 01.05.2013 17:38, schrieb Will Deacon:
> > On Wed, May 01, 2013 at 04:32:14PM +0100, Dirk Behme wrote:
> Just for a better understanding: What's wrong with using the same 
> register values on all CPUx? I.e. with copying them from CPU0? 
> Shouldn't all CPUx use the same setting? Or at least the same errata 
> bits enabled?

There's this thing called big.LITTLE... In this case, we're all A9s, but it
still feels horrible.

> > I'd rather we
> > orr'd in the bits we actually need, like we would in __v7_setup. Perhaps the
> > code there should be factored out into arm_errata_xxxx asm macros,
> 
> I'm not as much in the details as Shawn and you, but it's my 
> understanding that we moved the errata handling recently from the 
> kernel to the boot loader? After this, we now find that the boot 
> loader does the errata handling only for CPU0, and now we start to 
> discuss to move it back to the kernel?

In Shawn's case, I don't think the secondary CPUs execute any code prior to
kernel text, but he can correct me if I'm wrong.

Will


From Dave.Martin at arm.com  Wed May  1 12:49:28 2013
From: Dave.Martin at arm.com (Dave P Martin)
Date: Wed,  1 May 2013 17:49:28 +0100
Subject: [PATCH] ARM: KVM: Don't handle PSCI calls via SMC
Message-ID: <1367426968-5577-1-git-send-email-Dave.Martin@arm.com>

Currently, kvmtool unconditionally declares that HVC should be used
to call PSCI, so the function numbers in the DT tell the guest
nothing about the function ID namespace or calling convention for
SMC.

We already assume that the guest will examine and honour the DT,
since there is no way it could possibly guess the KVM-specific PSCI
function IDs otherwise.  So let's not encourage guests to violate
what's specified in the DT by using SMC to make the call.

Signed-off-by: Dave P Martin <Dave.Martin at arm.com>
Acked-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kvm/arm.c  |    3 ---
 arch/arm/kvm/psci.c |    2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 5a93698..32a3495 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -503,9 +503,6 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-	if (kvm_psci_call(vcpu))
-		return 1;
-
 	kvm_inject_undefined(vcpu);
 	return 1;
 }
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
index 7ee5bb7..86a693a 100644
--- a/arch/arm/kvm/psci.c
+++ b/arch/arm/kvm/psci.c
@@ -75,7 +75,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
  * kvm_psci_call - handle PSCI call if r0 value is in range
  * @vcpu: Pointer to the VCPU struct
  *
- * Handle PSCI calls from guests through traps from HVC or SMC instructions.
+ * Handle PSCI calls from guests through traps from HVC instructions.
  * The calling convention is similar to SMC calls to the secure world where
  * the function number is placed in r0 and this function returns true if the
  * function number specified in r0 is withing the PSCI range, and false
-- 
1.7.9.5



From lauraa at codeaurora.org  Wed May  1 12:58:46 2013
From: lauraa at codeaurora.org (Laura Abbott)
Date: Wed,  1 May 2013 09:58:46 -0700
Subject: [PATCH] ARM: nommu: Fix types for ioremap functions
Message-ID: <1367427526-5475-1-git-send-email-lauraa@codeaurora.org>

Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
(ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
changed the type of the ioremap functions to actually use phys_addr_t.
Change the nommu functions accordingly as well to avoid errors:

arch/arm/mm/nommu.c:84:15: error: conflicting types for '__arm_ioremap'
arch/arm/include/asm/io.h:137:22: note: previous declaration of '__arm_ioremap' was here
arch/arm/mm/nommu.c:91:18: error: conflicting types for 'arch_ioremap_caller'
arch/arm/include/asm/io.h:142:25: note: previous declaration of 'arch_ioremap_caller' was here
arch/arm/mm/nommu.c:93:15: error: conflicting types for '__arm_ioremap_caller'
arch/arm/include/asm/io.h:133:22: note: previous declaration of '__arm_ioremap_caller' was here

Signed-off-by: Laura Abbott <lauraa at codeaurora.org>
---
 arch/arm/mm/nommu.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f..31bd77b 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -81,16 +81,16 @@ void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
 	return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
 
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
 			    unsigned int mtype)
 {
 	return (void __iomem *)phys_addr;
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 				   unsigned int mtype, void *caller)
 {
 	return __arm_ioremap(phys_addr, size, mtype);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From aaro.koskinen at iki.fi  Wed May  1 12:59:57 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Wed,  1 May 2013 19:59:57 +0300
Subject: [PATCH] ARM: OMAP: RX-51: change probe order of touchscreen and panel
 SPI devices
Message-ID: <1367427597-30060-1-git-send-email-aaro.koskinen@iki.fi>

Commit 9fdca9df (spi: omap2-mcspi: convert to module_platform_driver)
broke the SPI display/panel driver probe on RX-51/N900. The exact cause is
not fully understood, but it seems to be related to the probe order. SPI
communication to the panel driver (spi1.2) fails unless the touchscreen
(spi1.0) has been probed/initialized before. When the omap2-mcspi driver
was converted to a platform driver, it resulted in that the devices are
probed immediately after the board registers them in the order they are
listed in the board file.

Fix the issue by moving the touchscreen before the panel in the SPI
device list.

The patch fixes the following failure:

[    1.260955] acx565akm spi1.2: invalid display ID
[    1.265899] panel-acx565akm display0: acx_panel_probe panel detect error
[    1.273071] omapdss CORE error: driver probe failed: -19

Tested-by: Sebastian Reichel <sre at debian.org>
Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>
Cc: Pali Roh?r <pali.rohar at gmail.com>
Cc: Joni Lapilainen <joni.lapilainen at gmail.com>
Cc: Tomi Valkeinen <tomi.valkeinen at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: stable at vger.kernel.org
---
 arch/arm/mach-omap2/board-rx51-peripherals.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 1a88467..18ca61e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -73,11 +73,11 @@
 #define LIS302_IRQ1_GPIO 181
 #define LIS302_IRQ2_GPIO 180  /* Not yet in use */
 
-/* list all spi devices here */
+/* List all SPI devices here. Note that the list/probe order seems to matter! */
 enum {
 	RX51_SPI_WL1251,
-	RX51_SPI_MIPID,		/* LCD panel */
 	RX51_SPI_TSC2005,	/* Touch Controller */
+	RX51_SPI_MIPID,		/* LCD panel */
 };
 
 static struct wl12xx_platform_data wl1251_pdata;
-- 
1.7.10.4



From lauraa at codeaurora.org  Wed May  1 13:00:53 2013
From: lauraa at codeaurora.org (Laura Abbott)
Date: Wed,  1 May 2013 10:00:53 -0700
Subject: [PATCH] ARM: imx: Change type of ioremap function
Message-ID: <1367427653-6068-1-git-send-email-lauraa@codeaurora.org>

Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
(ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
changed the type of the ioremap functions to actually use phys_addr_t.

Switch the imx ioremap functions to use phys_addr_t to avoid warnings:

arch/arm/mach-imx/mm-imx3.c: In function 'imx31_init_early':
arch/arm/mach-imx/mm-imx3.c:142:22: warning: assignment from incompatible pointer type [enabled by default]
arch/arm/mach-imx/mm-imx3.c: In function 'imx35_init_early':
arch/arm/mach-imx/mm-imx3.c:221:22: warning: assignment from incompatible pointer type [enabled by default]

Signed-off-by: Laura Abbott <lauraa at codeaurora.org>
---
 arch/arm/mach-imx/mm-imx3.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index cefa047..f019f14 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -65,7 +65,7 @@ static void imx3_idle(void)
 		: "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
 					 unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From holt at sgi.com  Wed May  1 13:06:47 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:47 -0500
Subject: [PATCH -v7 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-8-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/unicore32/kernel/process.c | 10 +++++-----
 arch/unicore32/kernel/setup.h   |  2 +-
 arch/unicore32/mm/mmu.c         |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index c944769..9dc6e48 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,14 +51,14 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static char reboot_mode = 'h';
+static enum reboot_mode reboot_mode;
 
 int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_WARM;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
@@ -88,7 +88,7 @@ void machine_restart(char *cmd)
 	 * we may need it to insert some 1:1 mappings so that
 	 * soft boot works.
 	 */
-	setup_mm_for_reboot(reboot_mode);
+	setup_mm_for_reboot();
 
 	/* Clean and invalidate caches */
 	flush_cache_all();
@@ -102,7 +102,7 @@ void machine_restart(char *cmd)
 	/*
 	 * Now handle reboot code.
 	 */
-	if (reboot_mode == 's') {
+	if (reboot_mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index 30f749d..f5c51b8 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
 extern void pci_puv3_preinit(void);
 extern void __init puv3_init_gpio(void);
 
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 
 extern char __stubs_start[], __stubs_end[];
 extern char __vectors_start[], __vectors_end[];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index 43c20b4..4f5a532 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -445,7 +445,7 @@ void __init paging_init(void)
  * the user-mode pages.  This will then ensure that we have predictable
  * results when turning the mmu off
  */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 	unsigned long base_pmdval;
 	pgd_t *pgd;
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:43 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:43 -0500
Subject: [PATCH -v7 03/11] Remove -stable friendly PF_THREAD_BOUND define
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-4-git-send-email-holt@sgi.com>

Remove the prior patch's #define for easier backporting to the stable
releases.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 kernel/sys.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index dad3c63..79b5f61 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,11 +362,6 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
-/* Add backwards compatibility for stable trees. */
-#ifndef PF_NO_SETAFFINITY
-#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
-#endif
-
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:46 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:46 -0500
Subject: [PATCH -v7 06/11] x86,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-7-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Miguel Boton <mboton.lkml at gmail.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/x86/kernel/reboot.c | 12 +++++++-----
 include/linux/reboot.h   |  5 +++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 76fa1e9..d42e3b2 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,7 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static int reboot_mode;
+static enum reboot_mode reboot_mode = REBOOT_COLD;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -88,11 +88,11 @@ static int __init reboot_setup(char *str)
 
 		switch (*str) {
 		case 'w':
-			reboot_mode = 0x1234;
+			reboot_mode = REBOOT_WARM;
 			break;
 
 		case 'c':
-			reboot_mode = 0;
+			reboot_mode = REBOOT_COLD;
 			break;
 
 #ifdef CONFIG_SMP
@@ -536,6 +536,7 @@ static void native_machine_emergency_restart(void)
 	int i;
 	int attempt = 0;
 	int orig_reboot_type = reboot_type;
+	unsigned short mode;
 
 	if (reboot_emergency)
 		emergency_vmx_disable_all();
@@ -543,7 +544,8 @@ static void native_machine_emergency_restart(void)
 	tboot_shutdown(TB_SHUTDOWN_REBOOT);
 
 	/* Tell the BIOS if we want cold or warm reboot */
-	*((unsigned short *)__va(0x472)) = reboot_mode;
+	mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
+	*((unsigned short *)__va(0x472)) = mode;
 
 	for (;;) {
 		/* Could also try the reset bit in the Hammer NB */
@@ -585,7 +587,7 @@ static void native_machine_emergency_restart(void)
 
 		case BOOT_EFI:
 			if (efi_enabled(EFI_RUNTIME_SERVICES))
-				efi.reset_system(reboot_mode ?
+				efi.reset_system(reboot_mode == REBOOT_WARM ?
 						 EFI_RESET_WARM :
 						 EFI_RESET_COLD,
 						 EFI_SUCCESS, 0, NULL);
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 23b3630..2ca9ed7 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -10,6 +10,11 @@
 #define SYS_HALT	0x0002	/* Notify of system halt */
 #define SYS_POWER_OFF	0x0003	/* Notify of system power off */
 
+enum reboot_mode {
+	REBOOT_COLD = 0,
+	REBOOT_WARM,
+};
+
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
 
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:41 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:41 -0500
Subject: [PATCH -v7 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-2-git-send-email-holt@sgi.com>

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v6:
 - Added a #define for non-hotplug case.
---
 include/linux/cpu.h |  3 +++
 kernel/cpu.c        | 27 +++++++++------------------
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..3e450c0 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -141,6 +141,8 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
 }
 #endif
 
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 int cpu_up(unsigned int cpu);
 void notify_cpu_starting(unsigned int cpu);
 extern void cpu_maps_update_begin(void);
@@ -148,6 +150,7 @@ extern void cpu_maps_update_done(void);
 
 #else	/* CONFIG_SMP */
 
+#define cpu_hotplug_disable()	do { } while (0)
 #define cpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 
 static inline int register_cpu_notifier(struct notifier_block *nb)
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..28769f5 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -541,29 +541,20 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
  */
-void cpu_hotplug_disable_before_freeze(void)
+void cpu_hotplug_disable(void)
 {
 	cpu_maps_update_begin();
 	cpu_hotplug_disabled = 1;
 	cpu_maps_update_done();
 }
 
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
+void cpu_hotplug_enable(void)
 {
 	cpu_maps_update_begin();
 	cpu_hotplug_disabled = 0;
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:48 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:48 -0500
Subject: [PATCH -v7 08/11] arm,
 Remove unused restart_mode fields from some arm subarchs
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-9-git-send-email-holt@sgi.com>

These restart_mode fields are not used at all.  Remove them to make
moving the reboot= cmdline options to the general kernel easier.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/mach-ebsa110/core.c | 1 -
 arch/arm/mach-pxa/mioa701.c  | 1 -
 arch/arm/mach-pxa/spitz.c    | 3 ---
 arch/arm/mach-pxa/tosa.c     | 1 -
 4 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..69a9d5d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
 	.atag_offset	= 0x400,
 	.reserve_lp0	= 1,
 	.reserve_lp2	= 1,
-	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
 	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b9..dbea67a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -756,7 +756,6 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
 	.map_io		= &pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
 	.init_irq	= &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..c3c0042 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,7 +979,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -993,7 +992,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -1007,7 +1005,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e..a41992f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -969,7 +969,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-	.restart_mode	= 'g',
 	.fixup          = fixup_tosa,
 	.map_io         = pxa25x_map_io,
 	.nr_irqs	= TOSA_NR_IRQS,
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:45 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:45 -0500
Subject: [PATCH -v7 05/11] checkpatch.pl the new kernel/reboot.c file.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-6-git-send-email-holt@sgi.com>

Get the new file to pass scripts/checkpatch.pl

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since v6:
 - Removed last remaining line length warning.
---
 kernel/reboot.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/kernel/reboot.c b/kernel/reboot.c
index 169f0b6..8e35e99 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -4,6 +4,8 @@
  *  Copyright (C) 2013  Linus Torvalds
  */
 
+#define pr_fmt(fmt)	"reboot: " fmt
+
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -114,9 +116,9 @@ void kernel_restart(char *cmd)
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
+		pr_emerg("Restarting system\n");
 	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+		pr_emerg("Restarting system with command '%s'\n", cmd);
 	kmsg_dump(KMSG_DUMP_RESTART);
 	machine_restart(cmd);
 }
@@ -125,7 +127,7 @@ EXPORT_SYMBOL_GPL(kernel_restart);
 static void kernel_shutdown_prepare(enum system_states state)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
 	usermodehelper_disable();
 	device_shutdown();
@@ -140,11 +142,10 @@ void kernel_halt(void)
 	kernel_shutdown_prepare(SYSTEM_HALT);
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
+	pr_emerg("System halted\n");
 	kmsg_dump(KMSG_DUMP_HALT);
 	machine_halt();
 }
-
 EXPORT_SYMBOL_GPL(kernel_halt);
 
 /**
@@ -159,7 +160,7 @@ void kernel_power_off(void)
 		pm_power_off_prepare();
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
+	pr_emerg("Power down\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
 	machine_power_off();
 }
@@ -188,10 +189,10 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 
 	/* For safety, we require "magic" arguments. */
 	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			(magic2 != LINUX_REBOOT_MAGIC2 &&
+			magic2 != LINUX_REBOOT_MAGIC2A &&
 			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
+			magic2 != LINUX_REBOOT_MAGIC2C))
 		return -EINVAL;
 
 	/*
@@ -234,7 +235,8 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 		break;
 
 	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+		ret = strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1);
+		if (ret < 0) {
 			ret = -EFAULT;
 			break;
 		}
@@ -301,14 +303,11 @@ static int __orderly_poweroff(bool force)
 		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
 		argv_free(argv);
 	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
 		ret = -ENOMEM;
 	}
 
 	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
+		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 		/*
 		 * I guess this should try to kick off some daemon to sync and
 		 * poweroff asap.  Or not even bother syncing if we're doing an
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:49 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:49 -0500
Subject: [PATCH -v7 09/11] arm,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-10-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/include/asm/mach/arch.h   | 3 ++-
 arch/arm/kernel/process.c          | 8 ++++----
 arch/arm/kernel/setup.c            | 6 +++---
 arch/arm/mach-footbridge/cats-hw.c | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..e2b551e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -9,6 +9,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 
 struct tag;
 struct meminfo;
@@ -39,7 +40,7 @@ struct machine_desc {
 	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-	char			restart_mode;	/* default restart mode	*/
+	enum reboot_mode	reboot_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index ae58d3b..8b4609e 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -174,14 +174,14 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-static char reboot_mode = 'h';
+enum reboot_mode reboot_mode;
 
-int __init reboot_setup(char *str)
+static int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_WARM;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 234e339..624c226 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -72,7 +72,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -758,8 +758,8 @@ void __init setup_arch(char **cmdline_p)
 
 	setup_dma_zone(mdesc);
 
-	if (mdesc->restart_mode)
-		reboot_setup(&mdesc->restart_mode);
+	if (mdesc->reboot_mode != REBOOT_COLD)
+		reboot_mode = mdesc->reboot_mode;
 
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09..14c9cb9 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
 	/* Maintainer: Philip Blundell */
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
+	.reboot_mode	= REBOOT_WARM,
 	.fixup		= fixup_cats,
 	.map_io		= footbridge_map_io,
 	.init_irq	= footbridge_init_irq,
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:40 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:40 -0500
Subject: [PATCH -v7 0/11] Shutdown from reboot_cpuid without stopping other
 cpus.
Message-ID: <1367428011-17123-1-git-send-email-holt@sgi.com>

Andrew, Please do _NOT_ take this patch series yet.  I am sending this
to you because you had comments on my -v6 submission.  If you do take
any of the patches, I believe patches 1-5 would be considered ready for
moving on as you had comments and I don't recall any others.  The first
two would really be nice to get into the stable release.

Peter,  I don't think I went too far off the rails on this.  The three
archs which handle reboot= should have been unified, correct?  I think
that ends up with essentially this.  I think the unicore and arm functions
passing around the now-global reboot_mode is probably the wrong way to
do things, so I would at least want to rework unicore and arm patches
to remove that parameter.  Otherwise, this patch set was building for
all the arm defconfigs as well as my x86_64 configs.

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.


Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From holt at sgi.com  Wed May  1 13:06:42 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:42 -0500
Subject: [PATCH -v7 02/11] Migrate shutdown/reboot to boot cpu.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-3-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
boot cpu and then continuing with shutdown/reboot.

This also has the effect of not breaking x86's command line parameter for
specifying the reboot cpu.  Note, this code was shamelessly copied from
arch/x86/kernel/reboot.c with bits removed pertaining to the reboot_cpu
command line parameter.

Signed-off-by: Robin Holt <holt at sgi.com>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v6:
 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
 - Fixup s/reboot_cpu_id/reboot_cpu/
---
 kernel/sys.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index afd0f7e..dad3c63 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int reboot_cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(reboot_cpu))
+		reboot_cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu));
+}
+
 /**
  *	kernel_restart - reboot the system
  *	@cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
 	kernel_restart_prepare(cmd);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
 		printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
 	kernel_shutdown_prepare(SYSTEM_HALT);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
 	if (pm_power_off_prepare)
 		pm_power_off_prepare();
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:51 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:51 -0500
Subject: [PATCH -v7 11/11] Move arch/x86 reboot= handling to generic kernel.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-12-git-send-email-holt@sgi.com>

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
To: Russell King <linux at arm.linux.org.uk>
To: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 Documentation/kernel-parameters.txt      |  18 ++++-
 arch/arm/kernel/process.c                |  10 ---
 arch/unicore32/kernel/process.c          |  10 ---
 arch/x86/include/asm/emergency-restart.h |  12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |   2 +-
 arch/x86/kernel/reboot.c                 | 111 +------------------------------
 include/linux/reboot.h                   |  17 +++++
 kernel/reboot.c                          |  88 +++++++++++++++++++++++-
 8 files changed, 123 insertions(+), 145 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 8c01a02..4a35d15 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2654,9 +2654,21 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old]] \
+				[,] s[mp]#### \
+				[,b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[,f[orce]
+			Format (all other archs):
+				[s[oft] | h[ard]] \
+				[,b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[,f[orce]]
+			Where reboot_mode is one of warm (soft) or cold,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					(in decimal) to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f7a54c2..095e318 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_WARM;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 9dc6e48..fdb8e79 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_WARM;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index d42e3b2..563ed91 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,22 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode = REBOOT_COLD;
-enum reboot_type reboot_type = BOOT_ACPI;
-int reboot_force;
-
-/*
- * This variable is used privately to keep track of whether or not
- * reboot_type is still set to its default value (i.e., reboot= hasn't
- * been set on the command line).  This is needed so that we can
- * suppress DMI scanning for reboot quirks.  Without it, it's
- * impossible to override a faulty reboot quirk without recompiling.
- */
-static int reboot_default = 1;
-
-#ifdef CONFIG_SMP
-static int reboot_cpu = -1;
-#endif
 
 /*
  * This is set if we need to go through the 'emergency' path.
@@ -64,79 +48,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +527,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 871b18e..9212ef3 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,23 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 8e35e99..057371e 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -87,7 +88,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu = 0;
+	int reboot_cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -344,3 +345,88 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+int reboot_default;
+enum reboot_mode reboot_mode = REBOOT_COLD;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
+/*
+ * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
+ * warm   Don't set the cold reboot flag
+ * cold   Set the cold reboot flag
+ * bios   Reboot by jumping through the BIOS
+ * smp    Reboot by executing reset on BSP or other CPU
+ * triple Force a triple fault (init)
+ * kbd    Use the keyboard controller. cold reset (default)
+ * acpi   Use the RESET_REG in the FADT
+ * efi    Use efi reset_system runtime service
+ * pci    Use the so-called "PCI reset register", CF9
+ * force  Avoid anything that could hang.
+ */
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+#ifdef CONFIG_SMP
+		case 's':
+			if (isdigit(*(str+1))) {
+				reboot_cpu = (int) (*(str+1) - '0');
+				if (isdigit(*(str+2)))
+					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
+			}
+			/*
+			 * We will leave sorting out the final value
+			 * when we are ready to reboot, since we might not
+			 * have detected BSP APIC ID or smp_num_cpu
+			 */
+			break;
+#endif /* CONFIG_SMP */
+
+#else
+		case 's':
+			reboot_mode = REBOOT_WARM;
+		case 'h':
+			reboot_mode = REBOOT_COLD;
+#endif
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:44 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:44 -0500
Subject: [PATCH -v7 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-5-git-send-email-holt@sgi.com>

This patch is preparatory.  It moves reboot related syscall, etc
functions from kernel/sys.c to kernel/reboot.c.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v6:
 - Add include of linux/uaccess.h to allow building on arm.
---
 kernel/Makefile |   2 +-
 kernel/reboot.c | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/sys.c    | 331 -----------------------------------------------------
 3 files changed, 348 insertions(+), 332 deletions(-)
 create mode 100644 kernel/reboot.c

diff --git a/kernel/Makefile b/kernel/Makefile
index d1574d4..e7e9f54 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y     = fork.o exec_domain.o panic.o printk.o \
 	    rcupdate.o extable.o params.o posix-timers.o \
 	    kthread.o wait.o sys_ni.o posix-cpu-timers.o mutex.o \
 	    hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-	    notifier.o ksysfs.o cred.o \
+	    notifier.o ksysfs.o cred.o reboot.o \
 	    async.o range.o groups.o lglock.o smpboot.o
 
 ifdef CONFIG_FUNCTION_TRACER
diff --git a/kernel/reboot.c b/kernel/reboot.c
new file mode 100644
index 0000000..169f0b6
--- /dev/null
+++ b/kernel/reboot.c
@@ -0,0 +1,347 @@
+/*
+ *  linux/kernel/reboot.c
+ *
+ *  Copyright (C) 2013  Linus Torvalds
+ */
+
+#include <linux/export.h>
+#include <linux/kexec.h>
+#include <linux/kmod.h>
+#include <linux/kmsg_dump.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h>
+#include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
+
+/*
+ * this indicates whether you can reboot with ctrl-alt-del: the default is yes
+ */
+
+int C_A_D = 1;
+struct pid *cad_pid;
+EXPORT_SYMBOL(cad_pid);
+
+/*
+ * If set, this is used for preparing the system to power off.
+ */
+
+void (*pm_power_off_prepare)(void);
+
+/**
+ *	emergency_restart - reboot the system
+ *
+ *	Without shutting down any hardware or taking any locks
+ *	reboot the system.  This is called when we know we are in
+ *	trouble so this is our best effort to reboot.  This is
+ *	safe to call in interrupt context.
+ */
+void emergency_restart(void)
+{
+	kmsg_dump(KMSG_DUMP_EMERG);
+	machine_emergency_restart();
+}
+EXPORT_SYMBOL_GPL(emergency_restart);
+
+void kernel_restart_prepare(char *cmd)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
+	system_state = SYSTEM_RESTART;
+	usermodehelper_disable();
+	device_shutdown();
+}
+
+/**
+ *	register_reboot_notifier - Register function to be called at reboot time
+ *	@nb: Info about notifier function to be called
+ *
+ *	Registers a function with the list of functions
+ *	to be called at reboot time.
+ *
+ *	Currently always returns zero, as blocking_notifier_chain_register()
+ *	always returns zero.
+ */
+int register_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(register_reboot_notifier);
+
+/**
+ *	unregister_reboot_notifier - Unregister previously registered reboot notifier
+ *	@nb: Hook to be unregistered
+ *
+ *	Unregisters a previously registered reboot
+ *	notifier function.
+ *
+ *	Returns zero on success, or %-ENOENT on failure.
+ */
+int unregister_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(unregister_reboot_notifier);
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int reboot_cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(reboot_cpu))
+		reboot_cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu));
+}
+
+/**
+ *	kernel_restart - reboot the system
+ *	@cmd: pointer to buffer containing command to execute for restart
+ *		or %NULL
+ *
+ *	Shutdown everything and perform a clean reboot.
+ *	This is not safe to call in interrupt context.
+ */
+void kernel_restart(char *cmd)
+{
+	kernel_restart_prepare(cmd);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	if (!cmd)
+		printk(KERN_EMERG "Restarting system.\n");
+	else
+		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+	kmsg_dump(KMSG_DUMP_RESTART);
+	machine_restart(cmd);
+}
+EXPORT_SYMBOL_GPL(kernel_restart);
+
+static void kernel_shutdown_prepare(enum system_states state)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list,
+		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+	system_state = state;
+	usermodehelper_disable();
+	device_shutdown();
+}
+/**
+ *	kernel_halt - halt the system
+ *
+ *	Shutdown everything and perform a clean system halt.
+ */
+void kernel_halt(void)
+{
+	kernel_shutdown_prepare(SYSTEM_HALT);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "System halted.\n");
+	kmsg_dump(KMSG_DUMP_HALT);
+	machine_halt();
+}
+
+EXPORT_SYMBOL_GPL(kernel_halt);
+
+/**
+ *	kernel_power_off - power_off the system
+ *
+ *	Shutdown everything and perform a clean system power_off.
+ */
+void kernel_power_off(void)
+{
+	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
+	if (pm_power_off_prepare)
+		pm_power_off_prepare();
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "Power down.\n");
+	kmsg_dump(KMSG_DUMP_POWEROFF);
+	machine_power_off();
+}
+EXPORT_SYMBOL_GPL(kernel_power_off);
+
+static DEFINE_MUTEX(reboot_mutex);
+
+/*
+ * Reboot system call: for obvious reasons only root may call it,
+ * and even root needs to set up some magic numbers in the registers
+ * so that some mistake won't make this reboot the whole machine.
+ * You can also set the meaning of the ctrl-alt-del-key here.
+ *
+ * reboot doesn't sync: do that yourself before calling this.
+ */
+SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
+		void __user *, arg)
+{
+	struct pid_namespace *pid_ns = task_active_pid_ns(current);
+	char buffer[256];
+	int ret = 0;
+
+	/* We only trust the superuser with rebooting the system. */
+	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
+		return -EPERM;
+
+	/* For safety, we require "magic" arguments. */
+	if (magic1 != LINUX_REBOOT_MAGIC1 ||
+	    (magic2 != LINUX_REBOOT_MAGIC2 &&
+	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			magic2 != LINUX_REBOOT_MAGIC2B &&
+	                magic2 != LINUX_REBOOT_MAGIC2C))
+		return -EINVAL;
+
+	/*
+	 * If pid namespaces are enabled and the current task is in a child
+	 * pid_namespace, the command is handled by reboot_pid_ns() which will
+	 * call do_exit().
+	 */
+	ret = reboot_pid_ns(pid_ns, cmd);
+	if (ret)
+		return ret;
+
+	/* Instead of trying to make the power_off code look like
+	 * halt when pm_power_off is not set do it the easy way.
+	 */
+	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
+		cmd = LINUX_REBOOT_CMD_HALT;
+
+	mutex_lock(&reboot_mutex);
+	switch (cmd) {
+	case LINUX_REBOOT_CMD_RESTART:
+		kernel_restart(NULL);
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_ON:
+		C_A_D = 1;
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_OFF:
+		C_A_D = 0;
+		break;
+
+	case LINUX_REBOOT_CMD_HALT:
+		kernel_halt();
+		do_exit(0);
+		panic("cannot halt");
+
+	case LINUX_REBOOT_CMD_POWER_OFF:
+		kernel_power_off();
+		do_exit(0);
+		break;
+
+	case LINUX_REBOOT_CMD_RESTART2:
+		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+			ret = -EFAULT;
+			break;
+		}
+		buffer[sizeof(buffer) - 1] = '\0';
+
+		kernel_restart(buffer);
+		break;
+
+#ifdef CONFIG_KEXEC
+	case LINUX_REBOOT_CMD_KEXEC:
+		ret = kernel_kexec();
+		break;
+#endif
+
+#ifdef CONFIG_HIBERNATION
+	case LINUX_REBOOT_CMD_SW_SUSPEND:
+		ret = hibernate();
+		break;
+#endif
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&reboot_mutex);
+	return ret;
+}
+
+static void deferred_cad(struct work_struct *dummy)
+{
+	kernel_restart(NULL);
+}
+
+/*
+ * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
+ * As it's called within an interrupt, it may NOT sync: the only choice
+ * is whether to reboot at once, or just ignore the ctrl-alt-del.
+ */
+void ctrl_alt_del(void)
+{
+	static DECLARE_WORK(cad_work, deferred_cad);
+
+	if (C_A_D)
+		schedule_work(&cad_work);
+	else
+		kill_cad_pid(SIGINT, 1);
+}
+	
+
+char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
+
+static int __orderly_poweroff(bool force)
+{
+	char **argv;
+	static char *envp[] = {
+		"HOME=/",
+		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
+		NULL
+	};
+	int ret;
+
+	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
+	if (argv) {
+		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
+		argv_free(argv);
+	} else {
+		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
+					 __func__, poweroff_cmd);
+		ret = -ENOMEM;
+	}
+
+	if (ret && force) {
+		printk(KERN_WARNING "Failed to start orderly shutdown: "
+					"forcing the issue\n");
+		/*
+		 * I guess this should try to kick off some daemon to sync and
+		 * poweroff asap.  Or not even bother syncing if we're doing an
+		 * emergency shutdown?
+		 */
+		emergency_sync();
+		kernel_power_off();
+	}
+
+	return ret;
+}
+
+static bool poweroff_force;
+
+static void poweroff_work_func(struct work_struct *work)
+{
+	__orderly_poweroff(poweroff_force);
+}
+
+static DECLARE_WORK(poweroff_work, poweroff_work_func);
+
+/**
+ * orderly_poweroff - Trigger an orderly system poweroff
+ * @force: force poweroff if command execution fails
+ *
+ * This may be called from any context to trigger a system shutdown.
+ * If the orderly shutdown fails, it will force an immediate shutdown.
+ */
+int orderly_poweroff(bool force)
+{
+	if (force) /* do not override the pending "true" */
+		poweroff_force = true;
+	schedule_work(&poweroff_work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(orderly_poweroff);
diff --git a/kernel/sys.c b/kernel/sys.c
index 79b5f61..202ec9d 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -116,20 +116,6 @@ EXPORT_SYMBOL(fs_overflowuid);
 EXPORT_SYMBOL(fs_overflowgid);
 
 /*
- * this indicates whether you can reboot with ctrl-alt-del: the default is yes
- */
-
-int C_A_D = 1;
-struct pid *cad_pid;
-EXPORT_SYMBOL(cad_pid);
-
-/*
- * If set, this is used for preparing the system to power off.
- */
-
-void (*pm_power_off_prepare)(void);
-
-/*
  * Returns true if current's euid is same as p's uid or euid,
  * or has CAP_SYS_NICE to p's user_ns.
  *
@@ -308,261 +294,6 @@ out_unlock:
 	return retval;
 }
 
-/**
- *	emergency_restart - reboot the system
- *
- *	Without shutting down any hardware or taking any locks
- *	reboot the system.  This is called when we know we are in
- *	trouble so this is our best effort to reboot.  This is
- *	safe to call in interrupt context.
- */
-void emergency_restart(void)
-{
-	kmsg_dump(KMSG_DUMP_EMERG);
-	machine_emergency_restart();
-}
-EXPORT_SYMBOL_GPL(emergency_restart);
-
-void kernel_restart_prepare(char *cmd)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
-	system_state = SYSTEM_RESTART;
-	usermodehelper_disable();
-	device_shutdown();
-}
-
-/**
- *	register_reboot_notifier - Register function to be called at reboot time
- *	@nb: Info about notifier function to be called
- *
- *	Registers a function with the list of functions
- *	to be called at reboot time.
- *
- *	Currently always returns zero, as blocking_notifier_chain_register()
- *	always returns zero.
- */
-int register_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(register_reboot_notifier);
-
-/**
- *	unregister_reboot_notifier - Unregister previously registered reboot notifier
- *	@nb: Hook to be unregistered
- *
- *	Unregisters a previously registered reboot
- *	notifier function.
- *
- *	Returns zero on success, or %-ENOENT on failure.
- */
-int unregister_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(unregister_reboot_notifier);
-
-static void migrate_to_reboot_cpu(void)
-{
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu = 0;
-
-	cpu_hotplug_disable();
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu))
-		reboot_cpu = cpumask_first(cpu_online_mask);
-
-	/* Prevent races with other tasks migrating this task */
-	current->flags |= PF_NO_SETAFFINITY;
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu));
-}
-
-/**
- *	kernel_restart - reboot the system
- *	@cmd: pointer to buffer containing command to execute for restart
- *		or %NULL
- *
- *	Shutdown everything and perform a clean reboot.
- *	This is not safe to call in interrupt context.
- */
-void kernel_restart(char *cmd)
-{
-	kernel_restart_prepare(cmd);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
-	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
-	kmsg_dump(KMSG_DUMP_RESTART);
-	machine_restart(cmd);
-}
-EXPORT_SYMBOL_GPL(kernel_restart);
-
-static void kernel_shutdown_prepare(enum system_states state)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
-	system_state = state;
-	usermodehelper_disable();
-	device_shutdown();
-}
-/**
- *	kernel_halt - halt the system
- *
- *	Shutdown everything and perform a clean system halt.
- */
-void kernel_halt(void)
-{
-	kernel_shutdown_prepare(SYSTEM_HALT);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
-	kmsg_dump(KMSG_DUMP_HALT);
-	machine_halt();
-}
-
-EXPORT_SYMBOL_GPL(kernel_halt);
-
-/**
- *	kernel_power_off - power_off the system
- *
- *	Shutdown everything and perform a clean system power_off.
- */
-void kernel_power_off(void)
-{
-	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
-	if (pm_power_off_prepare)
-		pm_power_off_prepare();
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
-	kmsg_dump(KMSG_DUMP_POWEROFF);
-	machine_power_off();
-}
-EXPORT_SYMBOL_GPL(kernel_power_off);
-
-static DEFINE_MUTEX(reboot_mutex);
-
-/*
- * Reboot system call: for obvious reasons only root may call it,
- * and even root needs to set up some magic numbers in the registers
- * so that some mistake won't make this reboot the whole machine.
- * You can also set the meaning of the ctrl-alt-del-key here.
- *
- * reboot doesn't sync: do that yourself before calling this.
- */
-SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
-		void __user *, arg)
-{
-	struct pid_namespace *pid_ns = task_active_pid_ns(current);
-	char buffer[256];
-	int ret = 0;
-
-	/* We only trust the superuser with rebooting the system. */
-	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
-		return -EPERM;
-
-	/* For safety, we require "magic" arguments. */
-	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
-			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
-		return -EINVAL;
-
-	/*
-	 * If pid namespaces are enabled and the current task is in a child
-	 * pid_namespace, the command is handled by reboot_pid_ns() which will
-	 * call do_exit().
-	 */
-	ret = reboot_pid_ns(pid_ns, cmd);
-	if (ret)
-		return ret;
-
-	/* Instead of trying to make the power_off code look like
-	 * halt when pm_power_off is not set do it the easy way.
-	 */
-	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
-		cmd = LINUX_REBOOT_CMD_HALT;
-
-	mutex_lock(&reboot_mutex);
-	switch (cmd) {
-	case LINUX_REBOOT_CMD_RESTART:
-		kernel_restart(NULL);
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_ON:
-		C_A_D = 1;
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_OFF:
-		C_A_D = 0;
-		break;
-
-	case LINUX_REBOOT_CMD_HALT:
-		kernel_halt();
-		do_exit(0);
-		panic("cannot halt");
-
-	case LINUX_REBOOT_CMD_POWER_OFF:
-		kernel_power_off();
-		do_exit(0);
-		break;
-
-	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
-			ret = -EFAULT;
-			break;
-		}
-		buffer[sizeof(buffer) - 1] = '\0';
-
-		kernel_restart(buffer);
-		break;
-
-#ifdef CONFIG_KEXEC
-	case LINUX_REBOOT_CMD_KEXEC:
-		ret = kernel_kexec();
-		break;
-#endif
-
-#ifdef CONFIG_HIBERNATION
-	case LINUX_REBOOT_CMD_SW_SUSPEND:
-		ret = hibernate();
-		break;
-#endif
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	mutex_unlock(&reboot_mutex);
-	return ret;
-}
-
-static void deferred_cad(struct work_struct *dummy)
-{
-	kernel_restart(NULL);
-}
-
-/*
- * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
- * As it's called within an interrupt, it may NOT sync: the only choice
- * is whether to reboot at once, or just ignore the ctrl-alt-del.
- */
-void ctrl_alt_del(void)
-{
-	static DECLARE_WORK(cad_work, deferred_cad);
-
-	if (C_A_D)
-		schedule_work(&cad_work);
-	else
-		kill_cad_pid(SIGINT, 1);
-}
-	
 /*
  * Unprivileged users may change the real gid to the effective gid
  * or vice versa.  (BSD-style)
@@ -2262,68 +1993,6 @@ SYSCALL_DEFINE3(getcpu, unsigned __user *, cpup, unsigned __user *, nodep,
 	return err ? -EFAULT : 0;
 }
 
-char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
-
-static int __orderly_poweroff(bool force)
-{
-	char **argv;
-	static char *envp[] = {
-		"HOME=/",
-		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
-		NULL
-	};
-	int ret;
-
-	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
-	if (argv) {
-		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
-		argv_free(argv);
-	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
-		ret = -ENOMEM;
-	}
-
-	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
-		/*
-		 * I guess this should try to kick off some daemon to sync and
-		 * poweroff asap.  Or not even bother syncing if we're doing an
-		 * emergency shutdown?
-		 */
-		emergency_sync();
-		kernel_power_off();
-	}
-
-	return ret;
-}
-
-static bool poweroff_force;
-
-static void poweroff_work_func(struct work_struct *work)
-{
-	__orderly_poweroff(poweroff_force);
-}
-
-static DECLARE_WORK(poweroff_work, poweroff_work_func);
-
-/**
- * orderly_poweroff - Trigger an orderly system poweroff
- * @force: force poweroff if command execution fails
- *
- * This may be called from any context to trigger a system shutdown.
- * If the orderly shutdown fails, it will force an immediate shutdown.
- */
-int orderly_poweroff(bool force)
-{
-	if (force) /* do not override the pending "true" */
-		poweroff_force = true;
-	schedule_work(&poweroff_work);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(orderly_poweroff);
-
 /**
  * do_sysinfo - fill in sysinfo struct
  * @info: pointer to buffer to fill
-- 
1.8.2.1



From holt at sgi.com  Wed May  1 13:06:50 2013
From: holt at sgi.com (Robin Holt)
Date: Wed,  1 May 2013 12:06:50 -0500
Subject: [PATCH -v7 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <1367428011-17123-11-git-send-email-holt@sgi.com>

Preparing to move the parsing of reboot= to generic kernel code
forces the change in reboot_mode handling to use the enum.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/include/asm/hardware/iop3xx.h         |  3 ++-
 arch/arm/include/asm/mach/arch.h               |  2 +-
 arch/arm/include/asm/system_misc.h             |  3 ++-
 arch/arm/kernel/process.c                      |  5 +++--
 arch/arm/mach-at91/at91rm9200.c                |  3 ++-
 arch/arm/mach-at91/generic.h                   |  5 +++--
 arch/arm/mach-bcm2835/bcm2835.c                |  4 ++--
 arch/arm/mach-clps711x/common.c                |  2 +-
 arch/arm/mach-clps711x/common.h                |  4 +++-
 arch/arm/mach-cns3xxx/core.h                   |  4 +++-
 arch/arm/mach-cns3xxx/pm.c                     |  2 +-
 arch/arm/mach-davinci/devices-da8xx.c          |  3 ++-
 arch/arm/mach-davinci/devices.c                |  3 ++-
 arch/arm/mach-davinci/include/mach/common.h    |  3 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h     |  3 ++-
 arch/arm/mach-davinci/include/mach/tnetv107x.h |  3 ++-
 arch/arm/mach-davinci/tnetv107x.c              |  3 ++-
 arch/arm/mach-dove/common.c                    |  2 +-
 arch/arm/mach-dove/common.h                    |  4 +++-
 arch/arm/mach-ebsa110/core.c                   |  2 +-
 arch/arm/mach-ep93xx/core.c                    |  3 ++-
 arch/arm/mach-ep93xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-exynos/common.c                  |  4 ++--
 arch/arm/mach-exynos/common.h                  |  6 ++++--
 arch/arm/mach-footbridge/common.c              |  4 ++--
 arch/arm/mach-footbridge/common.h              |  3 ++-
 arch/arm/mach-footbridge/netwinder-hw.c        |  4 ++--
 arch/arm/mach-h720x/common.c                   |  2 +-
 arch/arm/mach-h720x/common.h                   |  4 +++-
 arch/arm/mach-highbank/core.h                  |  4 +++-
 arch/arm/mach-highbank/system.c                |  5 +++--
 arch/arm/mach-imx/common.h                     |  4 +++-
 arch/arm/mach-imx/mach-imx6q.c                 |  3 ++-
 arch/arm/mach-imx/system.c                     |  2 +-
 arch/arm/mach-integrator/common.h              |  3 ++-
 arch/arm/mach-integrator/core.c                |  2 +-
 arch/arm/mach-iop13xx/include/mach/iop13xx.h   |  5 ++++-
 arch/arm/mach-iop13xx/setup.c                  |  2 +-
 arch/arm/mach-iop32x/n2100.c                   |  2 +-
 arch/arm/mach-ixp4xx/common.c                  |  4 ++--
 arch/arm/mach-ixp4xx/dsmg600-setup.c           |  1 +
 arch/arm/mach-ixp4xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-ixp4xx/include/mach/timex.h      |  2 +-
 arch/arm/mach-kirkwood/board-lsxl.c            |  2 +-
 arch/arm/mach-kirkwood/common.c                |  3 ++-
 arch/arm/mach-kirkwood/common.h                |  4 +++-
 arch/arm/mach-ks8695/generic.h                 |  2 +-
 arch/arm/mach-ks8695/time.c                    |  4 ++--
 arch/arm/mach-lpc32xx/common.c                 |  6 +++---
 arch/arm/mach-lpc32xx/common.h                 |  3 ++-
 arch/arm/mach-mmp/common.c                     |  2 +-
 arch/arm/mach-mmp/common.h                     |  3 ++-
 arch/arm/mach-mmp/include/mach/pxa168.h        |  4 +++-
 arch/arm/mach-mmp/pxa168.c                     |  2 +-
 arch/arm/mach-mv78xx0/common.c                 |  2 +-
 arch/arm/mach-mv78xx0/common.h                 |  4 +++-
 arch/arm/mach-mvebu/common.h                   |  4 +++-
 arch/arm/mach-mvebu/system-controller.c        |  3 ++-
 arch/arm/mach-mxs/include/mach/common.h        |  4 +++-
 arch/arm/mach-mxs/system.c                     |  2 +-
 arch/arm/mach-netx/generic.c                   |  3 ++-
 arch/arm/mach-netx/generic.h                   |  4 +++-
 arch/arm/mach-nomadik/cpu-8815.c               |  2 +-
 arch/arm/mach-omap1/board-voiceblue.c          |  3 ++-
 arch/arm/mach-omap1/common.h                   |  3 ++-
 arch/arm/mach-omap1/reset.c                    |  3 ++-
 arch/arm/mach-omap2/am33xx-restart.c           |  3 ++-
 arch/arm/mach-omap2/common.h                   | 17 +++++++++--------
 arch/arm/mach-omap2/omap2-restart.c            |  2 +-
 arch/arm/mach-omap2/omap3-restart.c            |  3 ++-
 arch/arm/mach-omap2/omap4-common.c             |  3 ++-
 arch/arm/mach-orion5x/common.c                 |  2 +-
 arch/arm/mach-orion5x/common.h                 |  4 +++-
 arch/arm/mach-orion5x/ls-chl-setup.c           |  2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c           |  2 +-
 arch/arm/mach-orion5x/lsmini-setup.c           |  2 +-
 arch/arm/mach-picoxcell/common.c               |  3 ++-
 arch/arm/mach-prima2/common.h                  |  4 +++-
 arch/arm/mach-prima2/rstc.c                    |  3 ++-
 arch/arm/mach-pxa/corgi.c                      |  6 +++---
 arch/arm/mach-pxa/generic.h                    |  4 +++-
 arch/arm/mach-pxa/mioa701.c                    |  7 ++++---
 arch/arm/mach-pxa/poodle.c                     |  2 +-
 arch/arm/mach-pxa/reset.c                      |  8 ++++----
 arch/arm/mach-pxa/spitz.c                      |  5 +++--
 arch/arm/mach-pxa/tosa.c                       |  5 +++--
 arch/arm/mach-realview/realview_eb.c           |  3 ++-
 arch/arm/mach-realview/realview_pb1176.c       |  3 ++-
 arch/arm/mach-realview/realview_pb11mp.c       |  3 ++-
 arch/arm/mach-realview/realview_pba8.c         |  3 ++-
 arch/arm/mach-realview/realview_pbx.c          |  3 ++-
 arch/arm/mach-rpc/riscpc.c                     |  3 ++-
 arch/arm/mach-s3c24xx/common.h                 |  6 ++++--
 arch/arm/mach-s3c24xx/s3c2410.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2412.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2416.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2443.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c244x.c                |  5 +++--
 arch/arm/mach-s3c64xx/common.c                 |  5 +++--
 arch/arm/mach-s3c64xx/common.h                 |  4 +++-
 arch/arm/mach-s5p64x0/common.c                 |  5 +++--
 arch/arm/mach-s5p64x0/common.h                 |  4 +++-
 arch/arm/mach-s5pc100/common.c                 |  5 +++--
 arch/arm/mach-s5pc100/common.h                 |  4 +++-
 arch/arm/mach-s5pv210/common.c                 |  2 +-
 arch/arm/mach-s5pv210/common.h                 |  4 +++-
 arch/arm/mach-sa1100/generic.c                 |  5 +++--
 arch/arm/mach-sa1100/generic.h                 |  3 ++-
 arch/arm/mach-shark/core.c                     |  3 ++-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  3 ++-
 arch/arm/mach-shmobile/board-kzm9g.c           |  3 ++-
 arch/arm/mach-socfpga/socfpga.c                |  3 ++-
 arch/arm/mach-spear13xx/include/mach/generic.h |  4 +++-
 arch/arm/mach-spear3xx/include/mach/generic.h  |  4 +++-
 arch/arm/mach-spear6xx/include/mach/generic.h  |  3 ++-
 arch/arm/mach-sunxi/sunxi.c                    |  3 ++-
 arch/arm/mach-tegra/board.h                    |  3 ++-
 arch/arm/mach-tegra/common.c                   |  3 ++-
 arch/arm/mach-u300/core.c                      |  6 +++---
 arch/arm/mach-versatile/core.c                 |  3 ++-
 arch/arm/mach-versatile/core.h                 |  3 ++-
 arch/arm/mach-vt8500/vt8500.c                  |  3 ++-
 arch/arm/mach-w90x900/cpu.c                    |  4 ++--
 arch/arm/mach-w90x900/nuc9xx.h                 |  5 ++++-
 arch/arm/plat-iop/gpio.c                       |  1 +
 arch/arm/plat-iop/restart.c                    |  2 +-
 arch/arm/plat-samsung/include/plat/s3c2412.h   |  4 +++-
 arch/arm/plat-samsung/include/plat/s3c2416.h   |  4 +++-
 arch/arm/plat-samsung/include/plat/s3c2443.h   |  4 +++-
 arch/arm/plat-spear/restart.c                  |  5 +++--
 drivers/power/reset/restart-poweroff.c         |  3 ++-
 drivers/power/reset/vexpress-poweroff.c        |  2 +-
 include/linux/reboot.h                         |  1 +
 include/linux/vexpress.h                       |  1 +
 134 files changed, 300 insertions(+), 172 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a..423744b 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e2b551e..2353bc3 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -54,7 +54,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	void			(*handle_irq)(struct pt_regs *);
 #endif
-	void			(*restart)(char, const char *);
+	void			(*restart)(enum reboot_mode, const char *);
 };
 
 /*
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e3..a3d61ad 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED	(1 << 0)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 8b4609e..f7a54c2 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -112,7 +113,7 @@ void soft_restart(unsigned long addr)
 	BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +123,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 9706c00..e15ff8b 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -303,7 +304,7 @@ static void at91rm9200_idle(void)
 	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	/*
 	 * Perform a hardware reset with the use of the Watchdog timer.
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..0723ed6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 6f57859..342793e 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -51,7 +51,7 @@ static void bcm2835_setup_restart(void)
 	WARN(!wdt_regs, "failed to remap watchdog regs");
 }
 
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 val;
 
@@ -89,7 +89,7 @@ static void bcm2835_power_off(void)
 	writel_relaxed(val, wdt_regs + PM_RSTS);
 
 	/* Continue with normal reset mechanism */
-	bcm2835_restart(0, "");
+	bcm2835_restart(REBOOT_COLD, "");
 }
 
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..54f6a8d 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -345,7 +345,7 @@ void __init clps711x_timer_init(void)
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2da0ff5 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
  * Common bits.
  */
 
+#include <linux/reboot.h>
+
 #define CLPS711X_NR_IRQS	(33)
 #define CLPS711X_NR_GPIO	(4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit)	((prt) * 8 + (bit))
@@ -12,4 +14,4 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b..5218b61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
+#include <linux/reboot.h>
+
 extern void cns3xxx_timer_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 3645808..5aa02ec 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fc50243..04e95b5 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
 	.resource	= da8xx_watchdog_resources,
 };
 
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device *dev;
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 4c48a36..5bdda3d 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
@@ -301,7 +302,7 @@ struct platform_device davinci_wdt_device = {
 	.resource	= wdt_resources,
 };
 
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
 	davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..cce316b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 extern void davinci_timer_init(void);
 
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index de439b7..89592aa 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,6 +17,7 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
@@ -103,7 +104,7 @@ int __init da850_register_vpif_display
 			(struct vpif_display_config *display_config);
 int __init da850_register_vpif_capture
 			(struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..bc9479d 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -54,7 +55,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index dc1a209..00a4076 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/map.h>
 
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
 	__raw_writel(1, &regs->kick);
 }
 
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
 	tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c6b3b2b..c37dd81 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -345,7 +345,7 @@ void __init dove_init(void)
 	dove_xor1_init();
 }
 
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index ee59fba..0a704ee 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 
 #endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 69a9d5d..62b928b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 
 arch_initcall(ebsa110_init);
 
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0x80000000);
 }
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3d..df8612f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
 	gpio_led_register_device(-1, &ep93xx_led_data);
 }
 
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b3..e256e0b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399..9342252 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -293,12 +293,12 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
-void exynos4_restart(char mode, const char *cmd)
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	u32 val;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8..92118c9 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,14 +12,16 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/reboot.h>
+
 extern void exynos4_timer_init(void);
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
 #ifdef CONFIG_PM_GENERIC_DOMAINS
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369..b0a7dd3 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
 	}
 }
 
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50..56607b3 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23f..807f49a 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
 
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 17ef91f..f335868 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -244,7 +244,7 @@ void __init h720x_map_io(void)
 	iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
 }
 
-void h720x_restart(char mode, const char *cmd)
+void h720x_restart(enum reboot_mode mode, const char *cmd)
 {
 	CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
 }
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h
index 7e73841..95c5728 100644
--- a/arch/arm/mach-h720x/common.h
+++ b/arch/arm/mach-h720x/common.h
@@ -13,10 +13,12 @@
  *
  */
 
+#include <linux/reboot.h>
+
 extern u32 h720x_gettimeoffset(void);
 extern void __init h720x_init_irq(void);
 extern void __init h720x_map_io(void);
-extern void h720x_restart(char, const char *);
+extern void h720x_restart(enum reboot_mode, const char *);
 
 #ifdef CONFIG_ARCH_H7202
 extern void h7202_timer_init(void);
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206..aea1ec5 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
 
+#include <linux/reboot.h>
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384..9e56003 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
  */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 
 #include "core.h"
 #include "sysregs.h"
 
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 'h')
+	if (mode == REBOOT_COLD)
 		highbank_set_pwr_hard_reset();
 	else
 		highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5bf4a97..85ce305 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct platform_device;
 struct clk;
 enum mxc_cpu_pwr_mode;
@@ -71,7 +73,7 @@ extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103..2089c45 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -25,6 +25,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -73,7 +74,7 @@ static int imx6q_revision(void)
 	}
 }
 
-void imx6q_restart(char mode, const char *cmd)
+void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..d7ec547 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -34,7 +34,7 @@ static void __iomem *wdog_base;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658b..ad0ac55 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d2..4cdfd73 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
  * To reset, we hit the on-board reset register in the system FPGA
  */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
 	cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58..17b4027 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 
 #ifndef __ASSEMBLY__
+
+#include <linux/reboot.h>
+
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61..97a4906 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -597,7 +597,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a..0691443 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
 		;
 }
 
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
 	gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
 	gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..b7ebbce 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
 					0xf, 0xfffffffe);
 }
 
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if ( 1 && mode == 's') {
+	if ( 1 && mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8..686ef34 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb6..4c4c6a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 #include <asm/types.h>
 
 #ifndef	__ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index c9e930f..729b2db 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -3,7 +3,7 @@
  * 
  */
 
-#include <mach/hardware.h>
+// #include <mach/hardware.h>
 
 /*
  * We use IXP425 General purpose timer for our timer needs, it runs at 
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..b54d0c7 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -35,7 +35,7 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
  */
 static void lsxl_power_off(void)
 {
-	kirkwood_restart('h', NULL);
+	kirkwood_restart(REBOOT_COLD, NULL);
 }
 
 void __init lsxl_init(void)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 49792a0..c3a8d30 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -695,7 +696,7 @@ void __init kirkwood_init(void)
 #endif
 }
 
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ed7056..bdb8a60 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,7 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 			    int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce4..43253f8 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a386..1a728ff 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
 	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
 
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	unsigned int reg;
 
-	if (mode == 's')
+	if (reboot_mode == REBOOT_WARM)
 		soft_restart(0);
 
 	/* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c..a610434 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
 	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
 
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_WARM:
+	case REBOOT_COLD:
 		lpc32xx_watchdog_reset();
 		break;
 
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b2606..1cd8853 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 /*
  * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 
 
 /*
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..c03b4ab 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..991d7e9 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..459c2d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
 
+#include <linux/reboot.h>
+
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 9bc7b86..9fbc2a1 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 	return platform_device_register(&pxa168_device_usb_host);
 }
 
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0efa144..862ba67 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -407,7 +407,7 @@ void __init mv78xx0_init(void)
 	clk_init();
 }
 
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6889af2 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 
 extern void mv78xx0_timer_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..f7ad45e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,9 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-void mvebu_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df..f875124 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 static void __iomem *system_controller_base;
 
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
 	{ /* end of list */ },
 };
 
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!system_controller_base) {
 		pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index be5a9c9..ab4d384 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -11,10 +11,12 @@
 #ifndef __MACH_MXS_COMMON_H__
 #define __MACH_MXS_COMMON_H__
 
+#include <linux/reboot.h>
+
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
 extern void mxs_timer_init(void);
-extern void mxs_restart(char, const char *);
+extern void mxs_restart(enum reboot_mode, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
 extern int mx23_clocks_init(void);
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 30042e2..48abe02 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -42,7 +42,7 @@ static void __iomem *mxs_clkctrl_reset_addr;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxs_restart(char mode, const char *cmd)
+void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* reset the chip */
 	__mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68..db25b0c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 
 subsys_initcall(netx_init);
 
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
 	       NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26b..bb2ce47 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/reboot.h>
+
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 21c1aa5..b98a042 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -149,7 +149,7 @@ static void __init cpu8815_map_io(void)
 	iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
 
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1..4677a9c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
 	gpio_set_value(0, wdt_gpio_state);
 }
 
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e99..abec019 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <plat/i2c.h>
 
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e..72bf4bf 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
 
 
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8..1eae962 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 14522d0..12e6418 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <asm/proc-fns.h>
 
@@ -111,33 +112,33 @@ void ti81xx_init_late(void);
 int omap2_common_pm_late_init(void);
 
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716..68423e2 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
  * Set the DPLL to bypass so that reboot completes successfully.  No
  * return value.
  */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 rate;
 
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582..5de2a0c 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 	omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 708bb11..2a1c80f 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -326,7 +327,7 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap44xx_restart(char mode, const char *cmd)
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* XXX Should save 'cmd' into scratchpad for use after reboot */
 	omap4_prminst_global_warm_sw_reset(); /* never returns */
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index ad71c8a..b3fa5f8 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -310,7 +310,7 @@ void __init orion5x_init(void)
 	orion5x_wdt_init();
 }
 
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index e603457..8304d6e 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -40,7 +42,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 044da5b..6dfdae5 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 
 static void lschl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_COLD, NULL);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index d49f934..417de0f 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 
 static void ls_hgl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_COLD, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 8e3965c..417bbd3 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_COLD, NULL);
 }
 
 
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..d298ed0 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,6 +15,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
@@ -70,7 +71,7 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Configure the watchdog to reset with the shortest possible timeout
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index b7c26b6..6a363c0 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..bdf57d4 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -82,7 +83,7 @@ int sirfsoc_reset_device(struct device *dev)
 
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fea..e1f527b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
 		/* Green LED off tells the bootloader to halt */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_COLD, NULL);
 }
 
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!machine_is_corgi())
 		/* Green LED on tells the bootloader to reboot */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-	pxa_restart('h', cmd);
+	pxa_restart(REBOOT_COLD, cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39..8963984 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/reboot.h>
+
 struct irq_data;
 
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
 
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dbea67a..01ebf50 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -691,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', NULL);
+	pxa_restart(REBOOT_WARM, NULL);
 }
 
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', cmd);
+	pxa_restart(REBOOT_WARM, cmd);
 }
 
 static struct gpio global_gpios[] = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..5d59bd4 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -422,7 +422,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 
 static void poodle_poweroff(void)
 {
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_COLD, NULL);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583..4a31c12 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
 	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
 	local_irq_disable();
 	local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
 	clear_reset_status(RESET_STATUS_ALL);
 
 	switch (mode) {
-	case 's':
+	case REBOOT_WARM:
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 		break;
-	case 'g':
+	case REBOOT_GPIO:
 		do_gpio_reset();
 		break;
-	case 'h':
+	case REBOOT_COLD:
 	default:
 		do_hw_reset();
 		break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c3c0042..2125df0 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -924,10 +925,10 @@ static inline void spitz_i2c_init(void) {}
  ******************************************************************************/
 static void spitz_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 	/* Bootloader magic for a reboot */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a41992f..0206b91 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bf..c85ddb2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
 	realview_eb_twd_init();
 }
 
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1..c5eade7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe21..f4b0962 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
 	realview_pb11mp_twd_init();
 }
 
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a..10a3e1d 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185..9d75493 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
 
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5..09d602b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 
 arch_initcall(rpc_init);
 
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
 	iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ed6276f..eac1b69 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,8 +12,10 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
-void s3c2410_restart(char mode, const char *cmd);
-void s3c244x_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void s3c2410_restart(enum reboot_mode mode, const char *cmd);
+void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 
 extern struct syscore_ops s3c24xx_irq_syscore_ops;
 
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 9ebef95..7955f7e 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
@@ -196,9 +197,9 @@ int __init s3c2410a_init(void)
 	return s3c2410_init();
 }
 
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		soft_restart(0);
 	}
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0d59215..51fec68 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -130,9 +131,9 @@ static void s3c2412_idle(void)
 	cpu_do_idle();
 }
 
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	/* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index e30476d..6f74edc 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -80,9 +81,9 @@ static struct device s3c2416_dev = {
 	.bus		= &s3c2416_subsys,
 };
 
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 165b6a6..8dcbd53 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -60,9 +61,9 @@ static struct device s3c2443_dev = {
 	.bus		= &s3c2443_subsys,
 };
 
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index ad2671b..b893a67 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -199,9 +200,9 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
 	.resume		= s3c244x_resume,
 };
 
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	arch_wdt_reset();
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..a060fad 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,9 +376,9 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
 
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_WARM)
 		arch_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..e8f990b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
 
+#include <linux/reboot.h>
+
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
 
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..1af3e02 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -437,9 +438,9 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
 
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_WARM)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fd..f3a9b43 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5P6440
 
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..2855bed 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -216,9 +217,9 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_WARM)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index 9fbd3ae..87c50a1 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
 
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5PC100
 
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e..023f1a7 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 	}
 };
 
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 6ed2af5..6f29fc5 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
 
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5PV210
 
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98..040ce1c 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <video/sa1100fb.h>
 
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
 	PMCR = PMCR_SF;
 }
 
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1..9a33695 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
  *
  * Author: Nicolas Pitre
  */
+#include <linux/reboot.h>
 
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 1535557..1d32c5e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
         short temp;
         /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index ff8b7ba..73c5946 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -38,6 +38,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -1196,7 +1197,7 @@ static void __init eva_add_early_devices(void)
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* Do soft power on reset */
 	writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index a385f57..8ad4146 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -31,6 +31,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -774,7 +775,7 @@ static void __init kzm_init(void)
 	sh73a0_pm_init();
 }
 
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
 	/* Do soft power on reset */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 1042c02..78a92a6 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -19,6 +19,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -85,7 +86,7 @@ static void __init socfpga_init_irq(void)
 	socfpga_sysmgr_init();
 }
 
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: */
 }
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 633e678..110f579 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -15,6 +15,8 @@
 #define __MACH_GENERIC_H
 
 #include <linux/dmaengine.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 
 /* Add spear13xx structure declarations here */
@@ -30,7 +32,7 @@ void __init spear_setup_of_timer(void);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
 bool dw_dma_filter(struct dma_chan *chan, void *slave);
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
 
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index df31079..be8461e 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -18,6 +18,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
@@ -31,6 +33,6 @@ void __init spear_setup_of_timer(void);
 void __init spear3xx_clk_init(void);
 void __init spear3xx_map_io(void);
 
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 65514b1..782bd99 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,9 +15,10 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 void __init spear_setup_of_timer(void);
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 void __init spear6xx_clk_init(void);
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 23afb73..5c05687 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -18,6 +18,7 @@
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/sunxi_timer.h>
+#include <linux/reboot.h>
 
 #include <linux/irqchip/sunxi.h>
 
@@ -45,7 +46,7 @@ static void sunxi_setup_restart(void)
 	WARN(!wdt_base, "failed to map watchdog base address");
 }
 
-static void sunxi_restart(char mode, const char *cmd)
+static void sunxi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!wdt_base)
 		return;
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 86851c8..d99edf9 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 
 void __init tegra20_init_early(void);
 void __init tegra30_init_early(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 5449a3f..d9caa7b 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip.h>
 #include <linux/clk/tegra.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -66,7 +67,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
 
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
 	u32 reg;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..c5177c23e 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -671,11 +671,11 @@ static void __init u300_init_machine(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-static void u300_restart(char mode, const char *cmd)
+static void u300_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_WARM:
+	case REBOOT_COLD:
 #ifdef CONFIG_COH901327_WATCHDOG
 		coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 25160ae..9d16f58 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif	/* CONFIG_LEDS */
 
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 	u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d..f06d576 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 49e8005..ea617e7 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -21,6 +21,7 @@
 #include <linux/clocksource.h>
 #include <linux/io.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -46,7 +47,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (pmc_base)
 		writel(1, pmc_base + VT8500_PMSR_REG);
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b..c1f9eed 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define	WTE	(1 << 7)
 #define	WTRE	(1 << 1)
 
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b2..e3ab1e1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
  * published by the Free Software Foundation.
  *
  */
+
+#include <linux/reboot.h>
+
 struct map_desc;
 
 /* core initialisation functions */
 
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be..697de6d 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699..3a4d5e5 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
 
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	*IOP3XX_PCSR = 0x30;
 
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
index cbae50d..228b604 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2412.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2412.h
@@ -12,6 +12,8 @@
 
 #ifdef CONFIG_CPU_S3C2412
 
+#include <linux/reboot.h>
+
 extern  int s3c2412_init(void);
 
 extern void s3c2412_map_io(void);
@@ -22,7 +24,7 @@ extern void s3c2412_init_clocks(int xtal);
 
 extern  int s3c2412_baseclk_add(void);
 
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c2412_init_clocks NULL
 #define s3c2412_init_uarts NULL
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
index f27399a..dd3d950 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -11,6 +11,8 @@
 
 #ifdef CONFIG_CPU_S3C2416
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 extern  int s3c2416_init(void);
@@ -23,7 +25,7 @@ extern void s3c2416_init_clocks(int xtal);
 
 extern  int s3c2416_baseclk_add(void);
 
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 
 extern void s3c2416_init_irq(void);
 extern struct syscore_ops s3c2416_irq_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
index 71b88ec..048b878 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -12,6 +12,8 @@
 
 #ifdef CONFIG_CPU_S3C2443
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 extern  int s3c2443_init(void);
@@ -24,7 +26,7 @@ extern void s3c2443_init_clocks(int xtal);
 
 extern  int s3c2443_baseclk_add(void);
 
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 
 extern void s3c2443_init_irq(void);
 #else
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 7d4616d..358fe45 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -12,14 +12,15 @@
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include <mach/generic.h>
 
 #define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* software reset, Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/drivers/power/reset/restart-poweroff.c b/drivers/power/reset/restart-poweroff.c
index 059cd15..6ebcc11 100644
--- a/drivers/power/reset/restart-poweroff.c
+++ b/drivers/power/reset/restart-poweroff.c
@@ -15,11 +15,12 @@
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 
 static void restart_poweroff_do_poweroff(void)
 {
-	arm_pm_restart('h', NULL);
+	arm_pm_restart(REBOOT_COLD, NULL);
 }
 
 static int restart_poweroff_probe(struct platform_device *pdev)
diff --git a/drivers/power/reset/vexpress-poweroff.c b/drivers/power/reset/vexpress-poweroff.c
index 469e696..476aa49 100644
--- a/drivers/power/reset/vexpress-poweroff.c
+++ b/drivers/power/reset/vexpress-poweroff.c
@@ -48,7 +48,7 @@ static void vexpress_power_off(void)
 
 static struct device *vexpress_restart_device;
 
-static void vexpress_restart(char str, const char *cmd)
+static void vexpress_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	vexpress_reset_do(vexpress_restart_device, "restart");
 }
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 2ca9ed7..871b18e 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -13,6 +13,7 @@
 enum reboot_mode {
 	REBOOT_COLD = 0,
 	REBOOT_WARM,
+	REBOOT_GPIO,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index ea7168a..617c01b 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/reboot.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
-- 
1.8.2.1



From cdall at cs.columbia.edu  Wed May  1 13:59:13 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Wed, 1 May 2013 10:59:13 -0700
Subject: [PATCH] ARM: KVM: Don't handle PSCI calls via SMC
In-Reply-To: <1367426968-5577-1-git-send-email-Dave.Martin@arm.com>
References: <1367426968-5577-1-git-send-email-Dave.Martin@arm.com>
Message-ID: <CAEDV+gK27-vw-RhcSrQsrJUfJx_zKQXtc6R6JGVg=YDsQmWZHA@mail.gmail.com>

On Wed, May 1, 2013 at 9:49 AM, Dave P Martin <Dave.Martin at arm.com> wrote:
> Currently, kvmtool unconditionally declares that HVC should be used
> to call PSCI, so the function numbers in the DT tell the guest
> nothing about the function ID namespace or calling convention for
> SMC.
>
> We already assume that the guest will examine and honour the DT,
> since there is no way it could possibly guess the KVM-specific PSCI
> function IDs otherwise.  So let's not encourage guests to violate
> what's specified in the DT by using SMC to make the call.
>
> Signed-off-by: Dave P Martin <Dave.Martin at arm.com>
> Acked-by: Marc Zyngier <marc.zyngier at arm.com>

Thanks, applied.

-Christoffer


From csd at broadcom.com  Wed May  1 14:09:55 2013
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 1 May 2013 11:09:55 -0700
Subject: [PATCH] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <20130501103718.GC22796@mudshark.cambridge.arm.com>
References: <1367347089-23788-1-git-send-email-csd@broadcom.com>
 <20130501103718.GC22796@mudshark.cambridge.arm.com>
Message-ID: <51815A73.9000705@broadcom.com>

Hi Will,
  Thanks for your feedback. See below for answers.

On 13-05-01 03:37 AM, Will Deacon wrote:
> Hi Christian,
>
> Thanks for CC'ing me.
>
> On Tue, Apr 30, 2013 at 07:38:09PM +0100, Christian Daudt wrote:
>> Rev A2 SoCs have an unorthodox memory re-mapping and this needs
>> to be reflected in the cache operations.
>> This patch adds new outer cache functions for the l2x0 driver
>> to support this SoC revision. It also adds a new compatible
>> value for the cache to enable this functionality.
> This is a pretty weird thing you've managed to build here...
No argument here.
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index c465fac..6edba13 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -523,6 +523,162 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
>>   	}
>>   }
>>   
>> +/*
>> + * For certain Broadcom SoCs, depending on the address range, different offsets
>> + * need to be added to the address before passing it to L2 for
>> + * invalidation/clean/flush
>> + *
>> + * Section Address Range              Offset        EMI
>> + *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
>> + *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
>> + *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
> Hmm, so am I right in thinking that the `Broadcom addresses' for section 1
> and 2 overlap? It would also be worth describing which physical addresses
> Linux actually wants to use; where is the memory in the physical memory map
> for devices with this L2 controller?
I've clarified this internally. Yes, there is an overlap, and because of 
that section 1 can't actually be used. I'm going to clear up the patch 
to remove the section one calculations to simplify it.
>> + * When the start and end addresses have crossed two different sections, we
>> + * need to break the L2 operation into two, each within its own section.
>> + * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
>> + * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
>> + * 0xC0000000 - 0xC0001000
>> + *
>> + * Note 1:
>> + * By breaking a single L2 operation into two, we may potentially suffer some
>> + * performance hit, but keep in mind the cross section case is very rare
>> + *
>> + * Note 2:
>> + * We do not need to handle the case when the start address is in
>> + * Section 1 and the end address is in Section 3, since it is not a valid use
>> + * case
>> + */
>> +
>> +#define BCM_VC_EMI_SEC1_START_ADDR    0x00000000UL
>> +#define BCM_VC_EMI_SEC1_END_ADDR      0x3FFFFFFFUL
>> +#define BCM_SYS_EMI_START_ADDR        0x40000000UL
>> +#define BCM_SYS_EMI_END_ADDR          0xBFFFFFFFUL
>> +#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
>> +#define BCM_VC_EMI_SEC3_END_ADDR      0xFFFFFFFFUL
> Seems a bit odd defining the END_ADDRs here, I'd just use strict '<' against
> the start of the next section in your code.
Makes sense. Removed.
>> +#define BCM_SYS_EMI_OFFSET            0x40000000UL
>> +#define BCM_VC_EMI_OFFSET             0x80000000UL
>> +
>> +static inline int bcm_addr_is_sys_emi(unsigned long addr)
>> +{
>> +	return (addr >= BCM_SYS_EMI_START_ADDR) &&
>> +		(addr <= BCM_SYS_EMI_END_ADDR);
>> +}
>> +
>> +static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
>> +{
>> +	if (bcm_addr_is_sys_emi(addr))
>> +		return addr + BCM_SYS_EMI_OFFSET;
>> +	else
>> +		return addr + BCM_VC_EMI_OFFSET;
>> +}
>> +
>> +static void bcm_inv_range(unsigned long start, unsigned long end)
>> +{
>> +	unsigned long new_start, new_end;
>> +
>> +	if (unlikely(end <= start))
>> +		return;
>> +
>> +	new_start = bcm_l2_phys_addr(start);
>> +	new_end = bcm_l2_phys_addr(end);
>> +
>> +	/* normal case, no cross section between start and end */
>> +	if (likely((bcm_addr_is_sys_emi(start) && bcm_addr_is_sys_emi(end)) ||
>> +		(!bcm_addr_is_sys_emi(start) && !bcm_addr_is_sys_emi(end)))) {
> You could avoid evaluating bcm_addr_is_sys_emi twice for each address. In
> fact, you know start < end, so you just need to check start >= EMI_START and
> end < EMI_END.
This test is to confirm that the range is completely within 1 section, 
so a single test won't do that - with the test as-is, the code after 
this 'if' already knows that there is section overlap. But I'll be 
removing section 1 handling and that will simplify things.

  thanks,
    csd




From davem at davemloft.net  Wed May  1 14:52:09 2013
From: davem at davemloft.net (David Miller)
Date: Wed, 01 May 2013 14:52:09 -0400 (EDT)
Subject: [PATCHv4 0/3] Add support for velocity network driver on
 platform devices
In-Reply-To: <1367302620-4620-1-git-send-email-linux@prisktech.co.nz>
References: <1367302620-4620-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <20130501.145209.2011460600232631301.davem@davemloft.net>

From: Tony Prisk <linux at prisktech.co.nz>
Date: Tue, 30 Apr 2013 18:16:57 +1200

> I think it would be pertinent to get some tested-by's for PCI users.

Tony, this came in a bit late, and there hasn't been any PCI test
reports so I have to defer this to the next merge window, sorry.


From Russ.Dill at ti.com  Wed May  1 15:02:25 2013
From: Russ.Dill at ti.com (Russ Dill)
Date: Wed,  1 May 2013 12:02:25 -0700
Subject: [RFC 0/2] am33xx 0.950V core sleep mode
Message-ID: <1367434947-6442-1-git-send-email-Russ.Dill@ti.com>

This patchset adds support for setting vdd core to 0.95V during
suspend. I wanted to get some comments on the DT usage and also
the location of the code, in sleep33xx.S. Since the am33xx PM code
is not yet merged, the patchset is based on ti-linux-3.8.y kernel
located at https://git.ti.com/ti-linux-kernel/ti-linux-kernel.

am33xx processors have a special VDD core operating point that can
lower power consumption, but the operating point has many
restrictions. One of the restrictions is that it does not support
any DDR3 clock rates, meaning that the memory controller must be
disabled to enter this operating point. For DDR2 systems, the
clock rate must be changed, which can only be done from internal
memory.

For these reasons, the mode is most useful during suspend. The
change must be done after the memory controller has been disabled.
The memory controller is disabled as the last step in the suspend
sequence, within sleep33xx.S.

The patchset basically adds a small I2C controller to sleep33xx.S,
allowing simple I2C messages to be sent to anything on the I2C1 bus.
It can support any am33xx platform so long as VDD core can be
controlled via simple writes on the I2C1 bus.

Since am33xx is a device tree platform, I needed to find a way to
integrate this into DT. I put the sleep and wake sequences as arrays
of binary bytes in the I2C1 node. I'm not sure where else it would
fit better, but I'm open to suggestions.

An example sequence is included for Beaglebone, where this patchset
has been tested.

Russ Dill (2):
  ARM: OMAP2+: AM33XX: I2C Sleep/wake sequence support
  ARM: dts: add AM33XX vdd core opp50 suspend for Beaglebone.

 arch/arm/boot/dts/am335x-bone.dts |  25 +++++-
 arch/arm/mach-omap2/pm33xx.c      | 108 ++++++++++++++++++++++
 arch/arm/mach-omap2/pm33xx.h      |  23 +++++
 arch/arm/mach-omap2/sleep33xx.S   | 184 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 339 insertions(+), 1 deletion(-)

-- 
1.8.1.2



From gmbnomis at gmail.com  Wed May  1 15:04:41 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Wed, 1 May 2013 21:04:41 +0200
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130501142206.GB17387@arm.com>
References: <20121008230733.GA17819@schnuecks.de>
 <20121118211005.GW22106@titan.lakedaemon.net>
 <20130418111608.GF27197@titan.lakedaemon.net>
 <20130418112201.GQ14496@n2100.arm.linux.org.uk>
 <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
Message-ID: <20130501190441.GA22227@schnuecks.de>

On Wed, May 01, 2013 at 03:22:06PM +0100, Catalin Marinas wrote:
> On Tue, Apr 30, 2013 at 10:04:03PM +0100, Simon Baatz wrote:
> > On Tue, Apr 30, 2013 at 12:22:25PM +0100, Catalin Marinas wrote:
> > > On Sun, Apr 21, 2013 at 11:06:30PM +0100, Simon Baatz wrote:
> > > > On Thu, Apr 18, 2013 at 02:51:04PM +0100, Catalin Marinas wrote:
> > > > > On Thu, Apr 18, 2013 at 12:40:16PM +0100, Jason Cooper wrote:
> > ...
> > > > 
> > > > It is not the driver itself which is using the API, it is the
> > > > generic scatterlist memory iterator. And I don't think that this is
> > > > wrong, as I have tried to explain in [1].
> > > 
> > > Trying to remember what we've discussed over the past months on this
> > > topic. It looks like sg_miter_stop() does the right thing in calling
> > > flush_kernel_dcache_page(). Commit f8b63c1 (ARM: 6382/1: Remove
> > > superfluous flush_kernel_dcache_page()) removed this function entirely.
> > > The code previously had this comment - /* highmem pages are always
> > > flushed upon kunmap already */ which I think it wasn't fully correct
> > > either. The kunmap_atomic() flushes the caches but kunmap() doesn't, so
> > > I suspect we only get the flushing if SG_MITER_ATOMIC.
> > > 
> > > So it looks to me like flush_kernel_dcache_page() should be implemented
> > > even for highmem pages (with VIVT or aliasing VIPT, at least for non
> > > kmap_atomic addresses by checking for FIXADDR_START). If highmem is
> > > disabled, I suspect we still need this function since the calling code
> > > doesn't care whether kmap/kunmap was a no-op. But can we keep it as a
> > > simple call to __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE)?
> > 
> > My first version ([1]) had:
> > 
> > 	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
> > 		__flush_kernel_dcache_page(page);
> > 
> > If I understand this correctly, you are proposing to remove the
> > highmem exclusion.
> 
> The highmem exclusion may have been there originally because of a
> comment suggesting that kunmap() does the flushing. This is the case
> only for kunmap_atomic() AFAICT (and maybe we could remove that as well
> and rely on flush_kernel_dcache_page() being called).
> 
> > And then in __flush_kernel_dcache_page():
> > 
> > 	mapping = page_mapping(page);
> > 
> > 	if (!mapping || mapping_mapped(mapping))
> > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > 
> > I still prefer to have this condition here to avoid the flush when
> > there is no user mapping at all.  This is handled by lazy flushing
> > and is probably the most common case anyway (given how many people
> > seem to be affected by this problem).
> 
> Looking at the old thread, you said there is a case when this condition
> is not true (O_DIRECT case). If that's for a page cache page, then we
> can handle it lazily (for anonymous pages I don't think we can rely on
> lazy flushing since the kernel does not guarantee the clearing of the
> PG_arch_1 bit).

As Russel pointed out in a comment to a later version of the patch,
PG_arch_1 makes only sense for page cache pages. The condition above
is ok from my point of view (it is based on what flush_dcache_page()
uses):

- Page cache page without user space mapping:
mapping != NULL and mapping_mapped() == 0

-> no flush here; lazy flush based on PG_arch_1 later if needed (we
   rely on the proper initialization of the page to "dirty" here.)


- Page cache page with user space mapping:
mapping != NULL and mapping_mapped() != 0

-> kernel mapping flushed here (user mapping can be assumed to be clean)


- Anonymous page:
mapping == NULL

-> kernel mapping flushed here (user mapping can be assumed to be clean)

 
> > Additionally, although we can assume that the page is kmapped,
> > page_address(page) can still be NULL for a highmem page, right?
> 
> It looks like kmap() always sets page_address(page) but I'm not sure
> about kmap_atomic(), it doesn't seem to.

Hmm, in __flush_dcache_page() we have the following code to flush the
kernel mapping:

void __flush_dcache_page(struct address_space *mapping, struct page *page)
{
	/*
	 * Writeback any data associated with the kernel mapping of this
	 * page.  This ensures that data in the physical page is mutually
	 * coherent with the kernels mapping.
	 */
	if (!PageHighMem(page)) {
		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
	} else {
		void *addr = kmap_high_get(page);
		if (addr) {
			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
			kunmap_high(page);
		} else if (cache_is_vipt()) {
			/* unmapped pages might still be cached */
			addr = kmap_atomic(page);
			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
			kunmap_atomic(addr);
		}
	}
...


We probably should reuse it in flush_kernel_dcache_page() to flush
the kernel mapping. (The last else clause looks strange though)


- Simon


From linux at prisktech.co.nz  Wed May  1 15:04:55 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 02 May 2013 07:04:55 +1200
Subject: [PATCHv4 0/3] Add support for velocity network driver on platform
 devices
In-Reply-To: <20130501.145209.2011460600232631301.davem@davemloft.net>
References: <1367302620-4620-1-git-send-email-linux@prisktech.co.nz>
 <20130501.145209.2011460600232631301.davem@davemloft.net>
Message-ID: <51816757.4090801@prisktech.co.nz>

On 02/05/13 06:52, David Miller wrote:
> From: Tony Prisk <linux at prisktech.co.nz>
> Date: Tue, 30 Apr 2013 18:16:57 +1200
>
>> I think it would be pertinent to get some tested-by's for PCI users.
> Tony, this came in a bit late, and there hasn't been any PCI test
> reports so I have to defer this to the next merge window, sorry.
No problems - I didn't honestly expect it to go in for 3.10 any way.
I was trying to get in nice and earlier for 3.11 to give people plenty 
of time to test.

Regards
Tony P


From s.hauer at pengutronix.de  Wed May  1 15:15:28 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 1 May 2013 21:15:28 +0200
Subject: [PATCH 3/3] ARM: dts: Add MC13783 support for i.MX27 Phytec
 PCM038 module
In-Reply-To: <1367422837.138582176@f94.mail.ru>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
 <1367405219-19078-3-git-send-email-shc_work@mail.ru>
 <20130501153609.GA31135@pengutronix.de>
 <1367422837.138582176@f94.mail.ru>
Message-ID: <20130501191528.GB31135@pengutronix.de>

On Wed, May 01, 2013 at 07:40:37PM +0400, Alexander Shiyan wrote:
> > On Wed, May 01, 2013 at 02:46:59PM +0400, Alexander Shiyan wrote:
> > > Added MC13783 node to imx27-phytec-phycore DT file.
> > > 
> > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > ---
> > >  arch/arm/boot/dts/imx27-phytec-phycore.dts | 92 ++++++++++++++++++++++++++++++
> > >  1 file changed, 92 insertions(+)
> > 
> > You can merge this with the previous patch.
> 
> Part 2 just adds a SPI host for the target. Is this merge is really necessary?

The SPI host does nothing without devices registered on it, so why not
make 2/3 and 3/3 a single patch?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From stefano.stabellini at eu.citrix.com  Wed May  1 15:27:07 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 May 2013 20:27:07 +0100
Subject: [PATCH 0/3] xen/arm: account for stolen ticks
Message-ID: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>

Hi all,
this small patch series introduces stolen ticks accounting for Xen on
ARM. Stolen ticks are clocksource ticks that have been "stolen" from the
cpu, typically because Linux is running in a virtual machine and the
vcpu has been descheduled.


Stefano Stabellini (3):
      arm_arch_timer: introduce arch_timer_stolen_ticks
      xen: move do_stolen_accounting to drivers/xen/time.c
      xen/arm: account for stolen ticks

 arch/arm/include/asm/arch_timer.h    |    5 +
 arch/arm/xen/enlighten.c             |    4 +
 arch/x86/xen/time.c                  |  127 +------------------------------
 drivers/clocksource/arm_arch_timer.c |    6 ++
 drivers/xen/Makefile                 |    2 +-
 drivers/xen/time.c                   |  142 ++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h                |    4 +
 7 files changed, 163 insertions(+), 127 deletions(-)
 create mode 100644 drivers/xen/time.c


 git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_1


Cheers,

Stefano


From stefano.stabellini at eu.citrix.com  Wed May  1 15:27:38 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 May 2013 20:27:38 +0100
Subject: [PATCH 1/3] arm_arch_timer: introduce arch_timer_stolen_ticks
In-Reply-To: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
Message-ID: <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>

Introduce a function, called arch_timer_stolen_ticks, called from the
arch_timer interrupt handler to account for stolen ticks.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: linux at arm.linux.org.uk
CC: john.stultz at linaro.org
CC: catalin.marinas at arm.com
CC: marc.zyngier at arm.com
---
 arch/arm/include/asm/arch_timer.h    |    5 +++++
 drivers/clocksource/arm_arch_timer.c |    6 ++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7ade91d..30db413 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -13,6 +13,11 @@
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
 
+/* per-platform function to calculate stolen ticks (clock cycles stolen
+ * to the vcpu by the hypervisor).
+ */
+extern void (*arch_timer_stolen_ticks)(void);
+
 /*
  * These register accessors are marked inline so the compiler can
  * nicely work out which register we want, and chuck away the rest of
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index d7ad425..d1ddf0b 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -37,6 +37,8 @@ static int arch_timer_ppi[MAX_TIMER_PPI];
 
 static struct clock_event_device __percpu *arch_timer_evt;
 
+void (*arch_timer_stolen_ticks)(void);
+
 static bool arch_timer_use_virtual = true;
 
 /*
@@ -52,6 +54,10 @@ static inline irqreturn_t timer_handler(const int access,
 		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
 		evt->event_handler(evt);
+
+		if ( arch_timer_stolen_ticks != NULL )
+			arch_timer_stolen_ticks();
+
 		return IRQ_HANDLED;
 	}
 
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  1 15:27:40 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 May 2013 20:27:40 +0100
Subject: [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
Message-ID: <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>

Register the runstate_memory_area with the hypervisor.
Use arch_timer_stolen_ticks and xen_stolen_accounting to account for
stolen ticks.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index d30042e..8f040a0 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -14,6 +14,7 @@
 #include <xen/xen-ops.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <asm/arch_timer.h>
 #include <asm/system_misc.h>
 #include <linux/interrupt.h>
 #include <linux/irqreturn.h>
@@ -172,6 +173,8 @@ static int __init xen_secondary_init(unsigned int cpu)
 		   later ones fail to. */
 		per_cpu(xen_vcpu, cpu) = vcpup;
 	}
+
+	xen_setup_runstate_info(cpu);
 	return 0;
 }
 
@@ -272,6 +275,7 @@ static int __init xen_guest_init(void)
 	if (!xen_initial_domain())
 		xenbus_probe(NULL);
 
+	arch_timer_stolen_ticks = xen_stolen_accounting;
 	pm_power_off = xen_power_off;
 	arm_pm_restart = xen_restart;
 
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  1 15:27:39 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 May 2013 20:27:39 +0100
Subject: [PATCH 2/3] xen: move do_stolen_accounting to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
Message-ID: <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>

Move do_stolen_accounting, xen_vcpu_stolen and related functions and
static variables to common code (drivers/xen/time.c).

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/x86/xen/time.c   |  127 +-------------------------------------------
 drivers/xen/Makefile  |    2 +-
 drivers/xen/time.c    |  142 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h |    4 ++
 4 files changed, 148 insertions(+), 127 deletions(-)
 create mode 100644 drivers/xen/time.c

diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 0296a95..278b7c2 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -28,131 +28,6 @@
 
 /* Xen may fire a timer up to this many ns early */
 #define TIMER_SLOP	100000
-#define NS_PER_TICK	(1000000000LL / HZ)
-
-/* runstate info updated by Xen */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
-
-/* snapshots of runstate info */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
-
-/* unused ns of stolen and blocked time */
-static DEFINE_PER_CPU(u64, xen_residual_stolen);
-static DEFINE_PER_CPU(u64, xen_residual_blocked);
-
-/* return an consistent snapshot of 64-bit time/counter value */
-static u64 get64(const u64 *p)
-{
-	u64 ret;
-
-	if (BITS_PER_LONG < 64) {
-		u32 *p32 = (u32 *)p;
-		u32 h, l;
-
-		/*
-		 * Read high then low, and then make sure high is
-		 * still the same; this will only loop if low wraps
-		 * and carries into high.
-		 * XXX some clean way to make this endian-proof?
-		 */
-		do {
-			h = p32[1];
-			barrier();
-			l = p32[0];
-			barrier();
-		} while (p32[1] != h);
-
-		ret = (((u64)h) << 32) | l;
-	} else
-		ret = *p;
-
-	return ret;
-}
-
-/*
- * Runstate accounting
- */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = get64(&state->state_entry_time);
-		barrier();
-		*res = *state;
-		barrier();
-	} while (get64(&state->state_entry_time) != state_time);
-}
-
-/* return true when a vcpu could run but has no real cpu to run on */
-bool xen_vcpu_stolen(int vcpu)
-{
-	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
-}
-
-void xen_setup_runstate_info(int cpu)
-{
-	struct vcpu_register_runstate_memory_area area;
-
-	area.addr.v = &per_cpu(xen_runstate, cpu);
-
-	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
-			       cpu, &area))
-		BUG();
-}
-
-static void do_stolen_accounting(void)
-{
-	struct vcpu_runstate_info state;
-	struct vcpu_runstate_info *snap;
-	s64 blocked, runnable, offline, stolen;
-	cputime_t ticks;
-
-	get_runstate_snapshot(&state);
-
-	WARN_ON(state.state != RUNSTATE_running);
-
-	snap = &__get_cpu_var(xen_runstate_snapshot);
-
-	/* work out how much time the VCPU has not been runn*ing*  */
-	blocked = state.time[RUNSTATE_blocked] - snap->time[RUNSTATE_blocked];
-	runnable = state.time[RUNSTATE_runnable] - snap->time[RUNSTATE_runnable];
-	offline = state.time[RUNSTATE_offline] - snap->time[RUNSTATE_offline];
-
-	*snap = state;
-
-	/* Add the appropriate number of ticks of stolen time,
-	   including any left-overs from last time. */
-	stolen = runnable + offline + __this_cpu_read(xen_residual_stolen);
-
-	if (stolen < 0)
-		stolen = 0;
-
-	ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen);
-	__this_cpu_write(xen_residual_stolen, stolen);
-	account_steal_ticks(ticks);
-
-	/* Add the appropriate number of ticks of blocked time,
-	   including any left-overs from last time. */
-	blocked += __this_cpu_read(xen_residual_blocked);
-
-	if (blocked < 0)
-		blocked = 0;
-
-	ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked);
-	__this_cpu_write(xen_residual_blocked, blocked);
-	account_idle_ticks(ticks);
-}
 
 /* Get the TSC speed from Xen */
 static unsigned long xen_tsc_khz(void)
@@ -390,7 +265,7 @@ static irqreturn_t xen_timer_interrupt(int irq, void *dev_id)
 		ret = IRQ_HANDLED;
 	}
 
-	do_stolen_accounting();
+	xen_stolen_accounting();
 
 	return ret;
 }
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index eabd0ee..2bf461a 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -3,7 +3,7 @@ obj-y	+= manage.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 endif
 obj-$(CONFIG_X86)			+= fallback.o
-obj-y	+= grant-table.o features.o events.o balloon.o
+obj-y	+= grant-table.o features.o events.o balloon.o time.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
diff --git a/drivers/xen/time.c b/drivers/xen/time.c
new file mode 100644
index 0000000..d00ed24
--- /dev/null
+++ b/drivers/xen/time.c
@@ -0,0 +1,142 @@
+/*
+ * Xen stolen ticks accounting.
+ */
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/math64.h>
+#include <linux/gfp.h>
+
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+
+#include <xen/events.h>
+#include <xen/features.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/vcpu.h>
+#include <xen/xen-ops.h>
+
+#define NS_PER_TICK	(1000000000LL / HZ)
+
+/* runstate info updated by Xen */
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
+
+/* snapshots of runstate info */
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
+
+/* unused ns of stolen and blocked time */
+static DEFINE_PER_CPU(u64, xen_residual_stolen);
+static DEFINE_PER_CPU(u64, xen_residual_blocked);
+
+/* return an consistent snapshot of 64-bit time/counter value */
+static u64 get64(const u64 *p)
+{
+	u64 ret;
+
+	if (BITS_PER_LONG < 64) {
+		u32 *p32 = (u32 *)p;
+		u32 h, l;
+
+		/*
+		 * Read high then low, and then make sure high is
+		 * still the same; this will only loop if low wraps
+		 * and carries into high.
+		 * XXX some clean way to make this endian-proof?
+		 */
+		do {
+			h = p32[1];
+			barrier();
+			l = p32[0];
+			barrier();
+		} while (p32[1] != h);
+
+		ret = (((u64)h) << 32) | l;
+	} else
+		ret = *p;
+
+	return ret;
+}
+
+/*
+ * Runstate accounting
+ */
+static void get_runstate_snapshot(struct vcpu_runstate_info *res)
+{
+	u64 state_time;
+	struct vcpu_runstate_info *state;
+
+	BUG_ON(preemptible());
+
+	state = &__get_cpu_var(xen_runstate);
+
+	/*
+	 * The runstate info is always updated by the hypervisor on
+	 * the current CPU, so there's no need to use anything
+	 * stronger than a compiler barrier when fetching it.
+	 */
+	do {
+		state_time = get64(&state->state_entry_time);
+		barrier();
+		*res = *state;
+		barrier();
+	} while (get64(&state->state_entry_time) != state_time);
+}
+
+/* return true when a vcpu could run but has no real cpu to run on */
+bool xen_vcpu_stolen(int vcpu)
+{
+	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
+}
+
+void xen_setup_runstate_info(int cpu)
+{
+	struct vcpu_register_runstate_memory_area area;
+
+	area.addr.v = &per_cpu(xen_runstate, cpu);
+
+	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
+			       cpu, &area))
+		BUG();
+}
+
+void xen_stolen_accounting(void)
+{
+	struct vcpu_runstate_info state;
+	struct vcpu_runstate_info *snap;
+	s64 blocked, runnable, offline, stolen;
+	cputime_t ticks;
+
+	get_runstate_snapshot(&state);
+
+	WARN_ON(state.state != RUNSTATE_running);
+
+	snap = &__get_cpu_var(xen_runstate_snapshot);
+
+	/* work out how much time the VCPU has not been runn*ing*  */
+	blocked = state.time[RUNSTATE_blocked] - snap->time[RUNSTATE_blocked];
+	runnable = state.time[RUNSTATE_runnable] - snap->time[RUNSTATE_runnable];
+	offline = state.time[RUNSTATE_offline] - snap->time[RUNSTATE_offline];
+
+	*snap = state;
+
+	/* Add the appropriate number of ticks of stolen time,
+	   including any left-overs from last time. */
+	stolen = runnable + offline + __this_cpu_read(xen_residual_stolen);
+
+	if (stolen < 0)
+		stolen = 0;
+
+	ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen);
+	__this_cpu_write(xen_residual_stolen, stolen);
+	account_steal_ticks(ticks);
+
+	/* Add the appropriate number of ticks of blocked time,
+	   including any left-overs from last time. */
+	blocked += __this_cpu_read(xen_residual_blocked);
+
+	if (blocked < 0)
+		blocked = 0;
+
+	ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked);
+	__this_cpu_write(xen_residual_blocked, blocked);
+	account_idle_ticks(ticks);
+}
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index d6fe062..85bb673 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -16,6 +16,10 @@ void xen_mm_unpin_all(void);
 void xen_timer_resume(void);
 void xen_arch_resume(void);
 
+bool xen_vcpu_stolen(int vcpu);
+void xen_setup_runstate_info(int cpu);
+void xen_stolen_accounting(void);
+
 int xen_setup_shutdown_event(void);
 
 extern unsigned long *xen_contiguous_bitmap;
-- 
1.7.2.5



From cov at codeaurora.org  Wed May  1 16:36:14 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Wed, 01 May 2013 16:36:14 -0400
Subject: [PATCH 1/3] arm_arch_timer: introduce arch_timer_stolen_ticks
In-Reply-To: <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <51817CBE.4050003@codeaurora.org>

Hi Stefano,

On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> Introduce a function, called arch_timer_stolen_ticks, called from the
> arch_timer interrupt handler to account for stolen ticks.

[...]

> diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
> index 7ade91d..30db413 100644
> --- a/arch/arm/include/asm/arch_timer.h
> +++ b/arch/arm/include/asm/arch_timer.h
> @@ -13,6 +13,11 @@
>  int arch_timer_of_register(void);
>  int arch_timer_sched_clock_init(void);
>  
> +/* per-platform function to calculate stolen ticks (clock cycles stolen
> + * to the vcpu by the hypervisor).

Stolen from the vcpu by the hypervisor?

Is the hypervisor adjusting the Virtual Offset Register?

[...]

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From athorlton at sgi.com  Wed May  1 18:05:10 2013
From: athorlton at sgi.com (Alex Thorlton)
Date: Wed, 1 May 2013 17:05:10 -0500
Subject: Kernel panic on boot in tick_do_broadcast
Message-ID: <51819196.50804@sgi.com>

Hi guys,

Robin Holt and I have been hitting a kernel panic on boot and have 
narrowed the problem down to commit ID 
26517f3e99248668315aee9460dcea21628cdd7f.  The stack trace trace is 
attached.  We were hoping you might be able to point us towards some 
possible causes of the issue.

Thanks for your time!

Alex
-------------- next part --------------
[    2.451373] smpboot: Booting Node   0, Processors  #1 #2 #3 #4 #5 #6 #7 OK
[    2.555983] smpboot: Booting Node   1, Processors  #8 #9 #10 #11 #12 #13
[    2.724264] BUG: unable to handle kernel NULL pointer dereference at 0000000000000048
[    2.733234] IP: [<ffffffff810ac0c3>] tick_do_broadcast+0x63/0xa0
[    2.739957] PGD 0
[    2.742209] Oops: 0000 [#1] SMP
[    2.745833] Modules linked in:
[    2.749248] CPU 0
[    2.751300] Pid: 1, comm: swapper/0 Not tainted 3.9.0-rc2.el7-medusa-00005-gf7dce82 #19 SGI UV2000/ROMLEY
[    2.762188] RIP: 0010:[<ffffffff810ac0c3>]  [<ffffffff810ac0c3>] tick_do_broadcast+0x63/0xa0
[    2.771623] RSP: 0000:ffff880fc1c03d10  EFLAGS: 00010002
[    2.777552] RAX: 0000000000000000 RBX: 000000000000d940 RCX: ffff880fc1826000
[    2.785518] RDX: 000000000000000d RSI: 0000000000000100 RDI: ffff880fc1826000
[    2.793485] RBP: ffff880fc1c03d20 R08: 0000000000000004 R09: 0000000000002000
[    2.801452] R10: 0000000000000001 R11: 00000000000003fd R12: ffff880fc1826000
[    2.809418] R13: 0000000000000000 R14: ffff880fbb51dd28 R15: 0000000000000000
[    2.817386] FS:  0000000000000000(0000) GS:ffff880fc1c00000(0000) knlGS:0000000000000000
[    2.826420] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    2.832833] CR2: 0000000000000048 CR3: 0000000001b01000 CR4: 00000000000407f0
[    2.840800] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[    2.848767] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
[    2.856734] Process swapper/0 (pid: 1, threadinfo ffff880fbb51c000, task ffff880fbb520000)
[    2.865960] Stack:
[    2.868202]  ffff880fc1818000 ffffffff81b12300 ffff880fc1c03d30 ffffffff810ac271
[    2.876502]  ffff880fc1c03d50 ffffffff810ac294 ffff880fc1818000 ffffffff81b08a40
[    2.884804]  ffff880fc1c03d60 ffffffff81004d65 ffff880fc1c03db0 ffffffff810e58a4
[    2.893105] Call Trace:
[    2.895833]  <IRQ>
[    2.897979]  [<ffffffff810ac271>] tick_do_periodic_broadcast+0x41/0x50
[    2.905486]  [<ffffffff810ac294>] tick_handle_periodic_broadcast+0x14/0x50
[    2.913164]  [<ffffffff81004d65>] timer_interrupt+0x15/0x20
[    2.919387]  [<ffffffff810e58a4>] handle_irq_event_percpu+0x84/0x1e0
[    2.926481]  [<ffffffff810e5a42>] handle_irq_event+0x42/0x70
[    2.932798]  [<ffffffff810e9225>] handle_edge_irq+0x65/0x130
[    2.939115]  [<ffffffff8100455e>] handle_irq+0x5e/0x150
[    2.944950]  [<ffffffff81059c23>] ? irq_enter+0x53/0x90
[    2.950785]  [<ffffffff8179f6c0>] do_IRQ+0x60/0xe0
[    2.956137]  [<ffffffff817959aa>] common_interrupt+0x6a/0x6a
[    2.962454]  [<ffffffff81059d00>] ? __do_softirq+0xa0/0x240
[    2.968675]  [<ffffffff81059cb1>] ? __do_softirq+0x51/0x240
[    2.974895]  [<ffffffff81059fb5>] irq_exit+0xc5/0xd0
[    2.980438]  [<ffffffff8179f7ae>] smp_apic_timer_interrupt+0x6e/0x99
[    2.987532]  [<ffffffff8179ea3a>] apic_timer_interrupt+0x6a/0x70
[    2.994238]  <EOI>
[    2.996383]  [<ffffffff8178d38d>] ? native_cpu_up+0x115/0x1ae
[    3.003009]  [<ffffffff8178f29d>] _cpu_up+0x120/0x161
[    3.008650]  [<ffffffff8178f345>] cpu_up+0x67/0x6b
[    3.014000]  [<ffffffff81c4f4d0>] smp_init+0x68/0x97
[    3.019545]  [<ffffffff81c31a55>] kernel_init_freeable+0x203/0x291
[    3.026438]  [<ffffffff81784280>] ? rest_init+0x80/0x80
[    3.032271]  [<ffffffff8178428e>] kernel_init+0xe/0x180
[    3.038104]  [<ffffffff8179dd5c>] ret_from_fork+0x7c/0xb0
[    3.044131]  [<ffffffff81784280>] ? rest_init+0x80/0x80
[    3.049963] Code: 85 c0 75 2a 48 63 35 05 5a b6 00 4c 89 e7 48 c7 c3 40 d9 00 00 e8 4e 14 35 00 89 c0 4c 89 e7 48 8b 04 c5 20 5d c0 81 48 8b 04 18 <ff> 50 48 48 8b 1c 24 4c 8b 64 24 08 c9 c3 0f 1f 80 00 00 00 00
[    3.071674] RIP  [<ffffffff810ac0c3>] tick_do_broadcast+0x63/0xa0
[    3.078489]  RSP <ffff880fc1c03d10>
[    3.082381] CR2: 0000000000000048
[    3.086085] ---[ end trace 30d634de49f3b984 ]---
[    3.091238] Kernel panic - not syncing: Fatal exception in interrupt
[    4.135664] Shutting down cpus with NMI

From tim at krieglstein.org  Wed May  1 18:24:46 2013
From: tim at krieglstein.org (Tim Sander)
Date: Thu, 2 May 2013 00:24:46 +0200
Subject: Pinmuxing with devicetree (beaglebone)
In-Reply-To: <CAN1soZzz=GRMrmj3rtBkxE74e0JZ4xewR=yVMUeMvp=6Yp34nQ@mail.gmail.com>
References: <201304211143.50961.tim@krieglstein.org>
 <CAN1soZzz=GRMrmj3rtBkxE74e0JZ4xewR=yVMUeMvp=6Yp34nQ@mail.gmail.com>
Message-ID: <201305020024.46922.tim@krieglstein.org>

Hi Haojian and Linux-Folks

Thanks for your reply. This is just a short followup how i got it working. But
as the 3.8.4 kernel on the beaglebone is having no ethernet connectivity i 
went back to the 3.2 kernel without device tree support for the time beeing.
So i didn't spent to much time on the device tree stuff.
> > I am currently trying to get pinmuxing working on a beaglebone board with
> > an offtree driver. This is for a custom handbuild hardware so i guess
> > there is no point in bringing this mainline.
> > 
> > While this is havyly patched 3.8.4 version running over here i think the
> > pinmux infrastructure is the new standard way. At least there is a
> > pinctrl/44e10800.pinmux directory in debugfs?
> > 
> > My last aproach was using the devicetree but beeing new to this
> > devicetree stuff i just got stuck:
> > http://comments.gmane.org/gmane.linux.ports.arm.kernel/231204
> > 
> > Now i tried use the way it is described in Documentation/pinctrl.txt but
> > still there are the includes missing: #include
> > <linux/pinctrl/consumer.h>.
> > 
> > Also while there is a /sys/kernel/debug/pinctrl/44e10800.pinmux in
> > debugfs i found that not so intuitive as the omap_mux which disappeared.
> > Also i didn't find any documentation for this debugfs stuff.
> > 
> > So what is the recommended way to get this stupid pinmuxing going. In pre
> > devicetree days one would just pick the mux.h include of the platform and
> > initialized the muxers which was pretty straight forward. Now with device
> > tree its much more complicated. No proper syntax checking as with the c
> > definitions and no documentation how to get this magic stuff working
> > :-(.
> > 
> > The whole stuff is build by a ptxdist (a embedded buildsystem) and can be
> > found over here:
> > https://gitorious.org/ptxdist-beaglebone/ptxdist-beaglebone
> 
> "pins" node could dump the register configuration if it's pinctrl-single
> driver.
> 
> You can dump this to check whether the right pinmux is set.
> 
> I checked your patch in the link.  It seems that you only write the pinmux
> configuration without using them.
> 
> Don't forget to append this in your DTS file.
>      pinctrl-names = "default";
>        pinctrl-0 = <&wind_pins>;
Thanks for the pointers, but somehow these fragments didn't work. What worked 
was writing it directly into the included dtb at the proper place eg.:

   am33xx_pinmux: pinmux at 44e10800 {
      pinctrl-names = "default";
      pinctrl-0 = <&userleds_pins>;

      userled_pins: pinmux_userled_pins {
         pinctrl-single,pins = <
            /* Tims wind pins */
            0x000  0x27      /* gpmc_ad0 = ad0 = P8-25 = gpio1_0|input, no pullup, gpio mux  */
            0x004  0x27      /* gpmc_ad1 = ad1 = P8-24 = gpio1_1|input, no pullup, gpio mux  */
            0x008  0x27      /* gpmc_ad2 = ad2 = P8-5 = gpio1_2|input, no pullup, gpio mux  */
            0x00c  0x27      /* gpmc_ad3 = ad3 = P8-6 = gpio1_3|input, no pullup, gpio mux  */
            0x038  0x26      /* gpmc_ad14  = pru_gpio_in14 = P8_16 = gpio1.14|input, no pullup, pru0 gpio 14 */

            0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
            0x58 0x17   /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
            0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
            0x60 0x17   /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
         >;
      };
      i2c0_pins: pinmux_i2c0_pins {
         pinctrl-single,pins = <
            0x188 0x70  /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
            0x18c 0x70  /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
         >;
      };
      i2c2_pins: pinmux_i2c2_pins {
         pinctrl-single,pins = <
            0x178 0x73  /* uart1_ctsn.i2c2_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
            0x17c 0x73  /* uart1_rtsn.i2c2_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
         >;
      };
   };

Also one thing i didn't know is that the dtb can also reverse compile so that the result can be seen.
This is especially handy with these fragment and include stuff.

Best regards
Tim


From horms at verge.net.au  Wed May  1 18:35:05 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 2 May 2013 07:35:05 +0900
Subject: [PATCH v3 4/5] ARM: shmobile: BOCK-W: add VIN and ML86V7667
 support
In-Reply-To: <518135F9.9010509@cogentembedded.com>
References: <201304232118.43686.sergei.shtylyov@cogentembedded.com>
 <201304232132.52741.sergei.shtylyov@cogentembedded.com>
 <517B06FA.3000303@cogentembedded.com>
 <20130501090909.GA2562@verge.net.au>
 <518135F9.9010509@cogentembedded.com>
Message-ID: <20130501223501.GA6517@verge.net.au>

On Wed, May 01, 2013 at 07:34:17PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 01-05-2013 13:09, Simon Horman wrote:
> 
> >>On 04/23/2013 09:32 PM, Sergei Shtylyov wrote:
> 
> >>>From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
> 
> >>>Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and
> >>>register VIN0/1 devices with the ML86V7667 specific platform data.
> 
> >>>Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
> >>>[Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate
> >>>#include, annotated all platform data as '__initdata'.]
> >>>Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> 
> >>>---
> >>>Changes since version 2:
> >>>- removed duplicate #include <linux/pinctrl/machine.h>;
> >>>- annotated all platform data as '__initdata' since they're kmemdup()'ed while
> >>>   registering the platform devices anyway;
> >>>- resolved rejects, refreshed the patch.
> 
> >>>  arch/arm/mach-shmobile/board-bockw.c |   39 +++++++++++++++++++++++++++++++++++
> >>>  1 file changed, 39 insertions(+)
> 
> >>>Index: renesas/arch/arm/mach-shmobile/board-bockw.c
> >>>===================================================================
> >>>--- renesas.orig/arch/arm/mach-shmobile/board-bockw.c
> >>>+++ renesas/arch/arm/mach-shmobile/board-bockw.c
> 
> >>[...]
> 
> >>>@@ -80,6 +101,16 @@ static const struct pinctrl_map bockw_pi
> >>>  				  "sdhi0_data4", "sdhi0"),
> >>>  	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
> >>>  				  "sdhi0_wp", "sdhi0"),
> >>>+	/* VIN0 */
> >>>+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.0", "pfc-r8a7778",
> >>>+				  "vin0_clk", "vin0"),
> >>>+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.0", "pfc-r8a7778",
> >>>+				  "vin0_data8", "vin0"),
> >>>+	/* VIN1 */
> >>>+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.1", "pfc-r8a7778",
> >>>+				  "vin1_clk", "vin1"),
> >>>+	PIN_MAP_MUX_GROUP_DEFAULT("rcar_vin.1", "pfc-r8a7778",
> >>>+				  "vin1_data8", "vin1"),
> >>>  };
> 
> >>     It turned out that VIN1 signal VI1_CLK conflicts with Ether
> >>signal ETH_REF_CLK.
> >>So I'm a bit at a loss here: whether I should totally remove VIN1
> >>device if I'm going
> >>to add Ether device, or add a BOCK-W specific submenu to Kconfig, or
> >>add driver
> >>specific #ifdef's in the code to disable VIN1 if sh_eth driver is
> >>enabled?...
> 
> >My preference, in order is:
> 
> >* Remove VIN1 (is it used?)
> 
>    At least video decoders are connected to both VIN0 and VIN1.
> 
> >* Kconfig-foo
> >* #ifdef nastiness
> 
>    I took the 3rd approach but luckily it was possible without
> #ifdef, using *if* (!IS_ENABLED(CONFIG_SH_ETH)) statement. Working
> patch posted on Monday.

Thanks.


From horms at verge.net.au  Wed May  1 18:57:48 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 2 May 2013 07:57:48 +0900
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <1366910944-3033663-4-git-send-email-arnd@arndb.de>
 <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>
Message-ID: <20130501225748.GD6517@verge.net.au>

On Wed, May 01, 2013 at 10:54:30AM -0500, Rob Herring wrote:
> On Thu, Apr 25, 2013 at 12:28 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > The irqchip_init function is only available when building
> > with CONFIG_OF enabled, which causes this build failure for
> > bonito_defconfig:
> >
> > arch/arm/mach-shmobile/built-in.o: In function `r8a7740_init_irq_of':
> > :(.init.text+0x580): undefined reference to `irqchip_init'
> >
> > This makes both the OF and the ATAGS portion of the driver
> > conditional, which avoids the build error and also results
> > in smaller object code if not both are enabled, without the
> > need for an #ifdef.
> >
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > Cc: Bastian Hecht <hechtb+renesas at gmail.com>
> > Cc: Simon Horman <horms+renesas at verge.net.au>
> > Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> > ---
> >  arch/arm/mach-shmobile/intc-r8a7740.c | 13 +++++++++++--
> >  1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
> > index 8871f77..5dc57f1 100644
> > --- a/arch/arm/mach-shmobile/intc-r8a7740.c
> > +++ b/arch/arm/mach-shmobile/intc-r8a7740.c
> > @@ -53,14 +53,23 @@ static void __init r8a7740_init_irq_common(void)
> >
> >  void __init r8a7740_init_irq_of(void)
> >  {
> > +       if (!IS_ENABLED(CONFIG_OF))
> > +               return;
> > +
> >         irqchip_init();
> 
> Why not have an empty irqchip_init? I'd guess we'll need this on other
> platforms and your default mach.

Thanks, I think that could work.

I will see about making it so.


From linux at arm.linux.org.uk  Wed May  1 19:09:57 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 00:09:57 +0100
Subject: [PATCH -v7 08/11] arm, Remove unused restart_mode fields from
 some arm subarchs
In-Reply-To: <1367428011-17123-9-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <1367428011-17123-9-git-send-email-holt@sgi.com>
Message-ID: <20130501230957.GS14496@n2100.arm.linux.org.uk>

On Wed, May 01, 2013 at 12:06:48PM -0500, Robin Holt wrote:
> These restart_mode fields are not used at all.  Remove them to make
> moving the reboot= cmdline options to the general kernel easier.

Your grepping is faulty.  They are most definitely used.


From linux at arm.linux.org.uk  Wed May  1 19:13:47 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 00:13:47 +0100
Subject: [PATCH -v7 0/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <1367428011-17123-1-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
Message-ID: <20130501231347.GT14496@n2100.arm.linux.org.uk>

On Wed, May 01, 2013 at 12:06:40PM -0500, Robin Holt wrote:
> Andrew, Please do _NOT_ take this patch series yet.  I am sending this
> to you because you had comments on my -v6 submission.

Another reason for not applying this is that I believe it wilfully breaks
a bunch of ARM platforms - such as removing the 'g' reboot mode (for gpio
based reboot on PXA), and removing the 's' reboot mode off a bunch of ARM
platforms which have no way to do a hard reboot.

What scares me is that this is revision 7 of this patch set and this is
the first it's been noticed on ARM... Maybe this patch set didn't touch
ARM previously?


From tony at atomide.com  Wed May  1 19:26:49 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 1 May 2013 16:26:49 -0700
Subject: [RFC 1/2] ARM: OMAP2+: AM33XX: I2C Sleep/wake sequence support
In-Reply-To: <1367434947-6442-2-git-send-email-Russ.Dill@ti.com>
References: <1367434947-6442-1-git-send-email-Russ.Dill@ti.com>
 <1367434947-6442-2-git-send-email-Russ.Dill@ti.com>
Message-ID: <20130501232649.GN28721@atomide.com>

* Russ Dill <Russ.Dill at ti.com> [130501 12:07]:
> This patch adds the ability to write an I2C sleep sequence from
> SRAM just before WFI, and a wake sequence just after control is passed
> from the M3. This is useful for adjusting voltages during sleep that cannot
> be lowered while SDRAM is active.
> 
> Each sequence is a series of I2C transfers in the form:
> 
> u8 length | u8 chip address | u8 byte0/reg address | u8 byte 1 | u8 byte n ...
> 
> The length indicates the number of bytes to transfer, including the register
> address. The length of the sequence is limited by the amount of space
> reserved in SRAM, 127 bytes.
> 
> The sequences are taken from the i2c1 node in the device tree. The property
> name for the sleep sequence is "sleep_sequence" and the property name for
> the wake sequence is "wake_sequence". Each property should be an array of
> bytes.
> 
> No actions are performed if the properties are not present in the device
> tree.

Looks like you should make that into just a regular device driver that lives
under drivers/ somewhere?

Regards,

Tony


From Russ.Dill at ti.com  Wed May  1 19:37:56 2013
From: Russ.Dill at ti.com (Russ Dill)
Date: Wed, 1 May 2013 16:37:56 -0700
Subject: [RFC 1/2] ARM: OMAP2+: AM33XX: I2C Sleep/wake sequence support
In-Reply-To: <20130501232649.GN28721@atomide.com>
References: <1367434947-6442-1-git-send-email-Russ.Dill@ti.com>
 <1367434947-6442-2-git-send-email-Russ.Dill@ti.com>
 <20130501232649.GN28721@atomide.com>
Message-ID: <CA+Bv8XYGa0c9+6DawMerDUnZnD_0fEESJZeQLDG6MuJrLPYV0Q@mail.gmail.com>

On Wed, May 1, 2013 at 4:26 PM, Tony Lindgren <tony at atomide.com> wrote:
>
> * Russ Dill <Russ.Dill at ti.com> [130501 12:07]:
> > This patch adds the ability to write an I2C sleep sequence from
> > SRAM just before WFI, and a wake sequence just after control is passed
> > from the M3. This is useful for adjusting voltages during sleep that cannot
> > be lowered while SDRAM is active.
> >
> > Each sequence is a series of I2C transfers in the form:
> >
> > u8 length | u8 chip address | u8 byte0/reg address | u8 byte 1 | u8 byte n ...
> >
> > The length indicates the number of bytes to transfer, including the register
> > address. The length of the sequence is limited by the amount of space
> > reserved in SRAM, 127 bytes.
> >
> > The sequences are taken from the i2c1 node in the device tree. The property
> > name for the sleep sequence is "sleep_sequence" and the property name for
> > the wake sequence is "wake_sequence". Each property should be an array of
> > bytes.
> >
> > No actions are performed if the properties are not present in the device
> > tree.
>
> Looks like you should make that into just a regular device driver that lives
> under drivers/ somewhere?
>
> Regards,
>
> Tony

This code has to be copied to, and run from SRAM. What would that even
look like? Additionally, there is also code under drivers/ that
manages this piece of hardware, i2c-omap.c. The code in this patch
differs in that it accesses no system memory, no stack, only knows how
to write, and it runs without interrupts.


From tony at atomide.com  Wed May  1 19:54:08 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 1 May 2013 16:54:08 -0700
Subject: [RFC 1/2] ARM: OMAP2+: AM33XX: I2C Sleep/wake sequence support
In-Reply-To: <CA+Bv8XYGa0c9+6DawMerDUnZnD_0fEESJZeQLDG6MuJrLPYV0Q@mail.gmail.com>
References: <1367434947-6442-1-git-send-email-Russ.Dill@ti.com>
 <1367434947-6442-2-git-send-email-Russ.Dill@ti.com>
 <20130501232649.GN28721@atomide.com>
 <CA+Bv8XYGa0c9+6DawMerDUnZnD_0fEESJZeQLDG6MuJrLPYV0Q@mail.gmail.com>
Message-ID: <20130501235407.GO28721@atomide.com>

* Russ Dill <Russ.Dill at ti.com> [130501 16:43]:
> On Wed, May 1, 2013 at 4:26 PM, Tony Lindgren <tony at atomide.com> wrote:
> >
> > Looks like you should make that into just a regular device driver that lives
> > under drivers/ somewhere?
> 
> This code has to be copied to, and run from SRAM. What would that even
> look like? Additionally, there is also code under drivers/ that
> manages this piece of hardware, i2c-omap.c. The code in this patch
> differs in that it accesses no system memory, no stack, only knows how
> to write, and it runs without interrupts.

Well we should move to using the generic drivers/misc/sram.c, so
you should be able to load the code to SRAM using that. Then you
can probably register some callback function based on the compatible
flag with i2c-omap.c?

Regards,

Tony


From syin at broadcom.com  Wed May  1 20:07:05 2013
From: syin at broadcom.com (Sherman Yin)
Date: Thu, 2 May 2013 00:07:05 +0000
Subject: [PATCH] ARM: Adds pin config API to set all configs in one
 function
In-Reply-To: <CACRpkdZ6zQdivtq5wmizovWEGb-Q9xzA6EE8CafnuV13hzX_UA@mail.gmail.com>
References: <1366841010-2823-1-git-send-email-syin@broadcom.com>
 <CACRpkdbT7f8ujCHZxKg26iMKcrAb+_yHW_2YsZwkoo892rkgTA@mail.gmail.com>
 <051069C10411E24D9749790C498526FA1BCF5427@SJEXCHMB12.corp.ad.broadcom.com>
 <CACRpkdZ6zQdivtq5wmizovWEGb-Q9xzA6EE8CafnuV13hzX_UA@mail.gmail.com>
Message-ID: <051069C10411E24D9749790C498526FA1BCF706F@SJEXCHMB12.corp.ad.broadcom.com>

>OK I thought a bit about this too and I see the problem.
>
>However I think it's cluttery to have both
>pin_config_set() and pin_config_set_all().
>
>If you want it to be done this way, I think you should modify
>pin_config_set() like so instead:
>
>-        int (*pin_config_set) (struct pinctrl_dev *pctldev,
>-                               unsigned pin,
>-                               unsigned long config);
>+       int (*pin_config_set) (struct pinctrl_dev *pctldev,
>+                                  const struct
>pinctrl_setting_configs *configs, unsigned num_configs);
>
>And then change all the drivers.
>
>(And vice versa mutatis mutandis for the group function.)

So that's basically back to the initial suggestion of moving the 
loop inside the driver's function instead of creating a separate
API?  Stephen said he is concerned about the duplicated loop
but did say it's not a big deal.

>Notice especially the added num_configs parameter that was
>missing from pin_config_set_all() in your patch, please tell
>me how else you deduct the size of the configs array.

We are passing a pointer to struct pinctrl_setting_configs, 
which should have the num_configs already:

105struct pinctrl_setting_configs {
106	unsigned group_or_pin;
107	unsigned long *configs;
108	unsigned num_configs;
109};

I want to be sure you are ok with exposing this struct to 
consumers (ie. drivers).  If not, we could pass the 3
components in the API instead.

>To the drivers to iterate over the array of configs,
>please introduce a static helper function:
>
>for_each_config() in something like <linux/pinctrl/pinconf.h>
>so it's easy for driver writers to get this right. (You'll be much
>helped by this function when refactoring the existing drivers as well
>I think.)

Yup ok.

>Doing the same thing with two different functions isn't
>helpful, refactoring like this is much better, it's just more
>work :-D

Yes it's more work, and a bit more risk of breaking stuff.  Out of the
2 methods, I do like this better since there are less APIs.  I will probably
have to get this patch in after my pinctrl driver since it is almost ready.

Thanks!
Sherman



From holt at sgi.com  Wed May  1 22:19:23 2013
From: holt at sgi.com (Robin Holt)
Date: Wed, 1 May 2013 21:19:23 -0500
Subject: [PATCH -v7 0/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <20130501231347.GT14496@n2100.arm.linux.org.uk>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <20130501231347.GT14496@n2100.arm.linux.org.uk>
Message-ID: <20130502021923.GS3672@sgi.com>

On Thu, May 02, 2013 at 12:13:47AM +0100, Russell King - ARM Linux wrote:
> On Wed, May 01, 2013 at 12:06:40PM -0500, Robin Holt wrote:
> > Andrew, Please do _NOT_ take this patch series yet.  I am sending this
> > to you because you had comments on my -v6 submission.
> 
> Another reason for not applying this is that I believe it wilfully breaks
> a bunch of ARM platforms - such as removing the 'g' reboot mode (for gpio
> based reboot on PXA), and removing the 's' reboot mode off a bunch of ARM
> platforms which have no way to do a hard reboot.
> 
> What scares me is that this is revision 7 of this patch set and this is
> the first it's been noticed on ARM... Maybe this patch set didn't touch
> ARM previously?

It started with a simple add a CONFIG_ value which eliminated the
calls to offline all cpus.  That expanded to the migrate to cpu 0.
Then the suggestion was to make a kernel parameter for selecting which
cpu to migrate to.  That led to discovering x86's reboot=s## parameter.
That led to move that to generic code, which led to resolving the conflict
between arm, unicore32, and x86 and therefore, this patch series.

If I had my preference, I would go back to -v2, polish it a bit,
and resubmit.  It just put the migrate_to_boot_cpu in kernel/sys.c,
put the calls in place, and continued with shutdown.

Second choice would be -v4 which added a reboot_cpu (actually, then it
was reboot_cpuid, but I would make it reboot_cpu) core_param, fixed the
x86 reboot=s## handling to handle more than the first 100 cpus and also
the documented smp## syntax.  I would not twiddle with unicore32 or arm.

Bottom line, the first 5 patches in this series are what I really care
about.  They get me the ability to shut my machine down in under 15
minutes.  The rest is just stuff I am doing to gain acceptance for those.

Robin


From shawn.guo at linaro.org  Wed May  1 22:21:49 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 10:21:49 +0800
Subject: [PATCH v3] ARM: imx: replicate the diagnostic register of boot
 cpu into secondary cores
In-Reply-To: <20130501163817.GD24055@mudshark.cambridge.arm.com>
References: <1366948645-12060-1-git-send-email-shawn.guo@linaro.org>
 <20130426132130.GE30858@mudshark.cambridge.arm.com>
 <20130426134722.GA1943@S2101-09.ap.freescale.net>
 <5181357E.3090805@gmail.com>
 <20130501153828.GC24055@mudshark.cambridge.arm.com>
 <5181408C.8090606@gmail.com>
 <20130501163817.GD24055@mudshark.cambridge.arm.com>
Message-ID: <20130502022147.GC3442@S2101-09.ap.freescale.net>

On Wed, May 01, 2013 at 05:38:17PM +0100, Will Deacon wrote:
> On Wed, May 01, 2013 at 05:19:24PM +0100, Dirk Behme wrote:
> > Am 01.05.2013 17:38, schrieb Will Deacon:
> > > On Wed, May 01, 2013 at 04:32:14PM +0100, Dirk Behme wrote:
> > Just for a better understanding: What's wrong with using the same 
> > register values on all CPUx? I.e. with copying them from CPU0? 
> > Shouldn't all CPUx use the same setting? Or at least the same errata 
> > bits enabled?
> 
> There's this thing called big.LITTLE... In this case, we're all A9s, but it
> still feels horrible.

It sounds more like a feeling instead of any issue in real.  Unless I
hear some convincing technical explanation, I will send the patch for
-rc to fix the broken reboot on imx6q.

Shawn



From Wenyou.Yang at atmel.com  Wed May  1 22:35:16 2013
From: Wenyou.Yang at atmel.com (Yang, Wenyou)
Date: Thu, 2 May 2013 02:35:16 +0000
Subject: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
 xfer->speed_hz set
In-Reply-To: <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
References: <1362626715-6549-1-git-send-email-wenyou.yang@atmel.com>
 <1362626815-6628-1-git-send-email-wenyou.yang@atmel.com>
 <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
Message-ID: <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>

Hi, Joachim,

> -----Original Message-----
> From: Joachim Eastwood [mailto:manabian at gmail.com]
> Sent: 2013?3?7? 20:31
> To: Yang, Wenyou
> Cc: linux-arm-kernel at lists.infradead.org; grant.likely at secretlab.ca; Ferre,
> Nicolas; plagnioj at jcrosoft.com; richard.genoud at gmail.com; Lin, JM;
> spi-devel-general at lists.sourceforge.net; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
> xfer->speed_hz set
> 
> On 7 March 2013 04:26, Wenyou Yang <wenyou.yang at atmel.com> wrote:
> > commit: 059b8ffeee5b427949872bb6ed5db5ae0788054e
> > cause the atmel spi probing failure.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
> > Cc: spi-devel-general at lists.sourceforge.net
> > Cc: linux-kernel at vger.kernel.org
> > ---
> >  drivers/spi/spi-atmel.c |    6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> > index 656d137..1eca815 100644
> > --- a/drivers/spi/spi-atmel.c
> > +++ b/drivers/spi/spi-atmel.c
> > @@ -846,9 +846,9 @@ static int atmel_spi_transfer(struct spi_device *spi,
> struct spi_message *msg)
> >                         }
> >                 }
> >
> > -               /* FIXME implement these protocol options!! */
> > -               if (xfer->speed_hz) {
> > -                       dev_dbg(&spi->dev, "no protocol options
> yet\n");
> > +               if (xfer->speed_hz < spi->max_speed_hz) {
> > +                       dev_dbg(&spi->dev,
> > +                               "speed in transfer less than bus
> speed\n");
> >                         return -ENOPROTOOPT;
> >                 }
> 
> I sent a similar patch to spi-devl a while ago, which Grant said he applied.
> https://patchwork.kernel.org/patch/2165301/
> 
> Can't find the patch in any upstream git tree so I guess Grant hasn't
> pushed it yet.
This patch hasn't still applied in any upstream git tree, so Atmel spi master doesn't work.
Could you help do some ping it? 

Thanks.

> 
> regards
> Joachim Eastwood

Best Regards,
Wenyou Yang

From shawn.guo at linaro.org  Wed May  1 22:39:00 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 10:39:00 +0800
Subject: [PATCH] mxs: icoll: Add function to register an interrupt as FIQ
 source
In-Reply-To: <1367243917-5177-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367243917-5177-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130502023858.GD3442@S2101-09.ap.freescale.net>

On Mon, Apr 29, 2013 at 03:58:37PM +0200, Maxime Ripard wrote:
> MXS, unlike other ARM platforms,

How are other ARM platforms handling that?

> has no way to make a FIQ from an
> interrupt from a driver, without poking directly into the icoll.
> 
> Add an exported function to do this.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-mxs/icoll.c | 11 +++++++++++

This will become drivers/irqchip/irq-mxs.c after the merge window.

Shawn

>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
> index 8fb23af..1bb16da 100644
> --- a/arch/arm/mach-mxs/icoll.c
> +++ b/arch/arm/mach-mxs/icoll.c
> @@ -16,6 +16,7 @@
>   * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>   */
>  
> +#include <linux/export.h>
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/irq.h>
> @@ -34,6 +35,7 @@
>  #define HW_ICOLL_INTERRUPTn_SET(n)		(0x0124 + (n) * 0x10)
>  #define HW_ICOLL_INTERRUPTn_CLR(n)		(0x0128 + (n) * 0x10)
>  #define BM_ICOLL_INTERRUPTn_ENABLE		0x00000004
> +#define BM_ICOLL_INTERRUPTn_FIQ_ENABLE		0x00000010
>  #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0	0x1
>  
>  #define ICOLL_NUM_IRQS		128
> @@ -41,6 +43,15 @@
>  static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
>  static struct irq_domain *icoll_domain;
>  
> +void mxs_icoll_set_irq_fiq(unsigned int irq)
> +{
> +	struct irq_data *d = irq_get_irq_data(irq);
> +
> +	__raw_writel(BM_ICOLL_INTERRUPTn_FIQ_ENABLE,
> +		     icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
> +}
> +EXPORT_SYMBOL(mxs_icoll_set_irq_fiq);
> +
>  static void icoll_ack_irq(struct irq_data *d)
>  {
>  	/*
> -- 
> 1.8.1.2
> 



From shawn.guo at linaro.org  Wed May  1 22:44:44 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 10:44:44 +0800
Subject: [PATCH] gpio: mxs: Use set and clear capabilities of the gpio
 controller
In-Reply-To: <1367244438-5322-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367244438-5322-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130502024443.GE3442@S2101-09.ap.freescale.net>

On Mon, Apr 29, 2013 at 04:07:18PM +0200, Maxime Ripard wrote:
> The current driver doesn't use the set and clear registers found on the
> mxs gpio controller.
> 
> This leads the generic gpio controller to be using some internal value
> to avoid looking up the value stored in the registers, making it behave
> pretty much like a cache.
> 
> This raises some coherency problem when a gpio is not modified by the
> gpio controller, while it can easily be fixed by using the set and clear
> registers.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> ---
>  drivers/gpio/gpio-mxs.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
> index 25000b0..f8e6af2 100644
> --- a/drivers/gpio/gpio-mxs.c
> +++ b/drivers/gpio/gpio-mxs.c
> @@ -326,7 +326,8 @@ static int mxs_gpio_probe(struct platform_device *pdev)
>  
>  	err = bgpio_init(&port->bgc, &pdev->dev, 4,
>  			 port->base + PINCTRL_DIN(port),
> -			 port->base + PINCTRL_DOUT(port), NULL,
> +			 port->base + PINCTRL_DOUT(port) + MXS_SET,
> +			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
>  			 port->base + PINCTRL_DOE(port), NULL, 0);
>  	if (err)
>  		goto out_irqdesc_free;
> -- 
> 1.8.1.2
> 



From shawn.guo at linaro.org  Wed May  1 23:12:09 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 11:12:09 +0800
Subject: [PATCH 1/3] ARM: dts: Add aliases for i.MX27 SPI controller
In-Reply-To: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130502031207.GG3442@S2101-09.ap.freescale.net>

On Wed, May 01, 2013 at 02:46:57PM +0400, Alexander Shiyan wrote:
> Add aliases to determine the proper SPI bus number.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Applied, thanks.

> ---
>  arch/arm/boot/dts/imx27.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> index ff4bd48..cd85828 100644
> --- a/arch/arm/boot/dts/imx27.dtsi
> +++ b/arch/arm/boot/dts/imx27.dtsi
> @@ -25,6 +25,9 @@
>  		gpio3 = &gpio4;
>  		gpio4 = &gpio5;
>  		gpio5 = &gpio6;
> +		spi0 = &cspi1;
> +		spi1 = &cspi2;
> +		spi2 = &cspi3;
>  	};
>  
>  	avic: avic-interrupt-controller at e0000000 {
> -- 
> 1.8.1.5
> 



From holt at sgi.com  Wed May  1 23:39:52 2013
From: holt at sgi.com (Robin Holt)
Date: Wed, 1 May 2013 22:39:52 -0500
Subject: [PATCH -v7 0/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <20130501231347.GT14496@n2100.arm.linux.org.uk>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <20130501231347.GT14496@n2100.arm.linux.org.uk>
Message-ID: <20130502033952.GU3658@sgi.com>

On Thu, May 02, 2013 at 12:13:47AM +0100, Russell King - ARM Linux wrote:
> On Wed, May 01, 2013 at 12:06:40PM -0500, Robin Holt wrote:
> > Andrew, Please do _NOT_ take this patch series yet.  I am sending this
> > to you because you had comments on my -v6 submission.
> 
> Another reason for not applying this is that I believe it wilfully breaks
> a bunch of ARM platforms - such as removing the 'g' reboot mode (for gpio
> based reboot on PXA), and removing the 's' reboot mode off a bunch of ARM
> platforms which have no way to do a hard reboot.

I am not sure what your basis for this statement is.

First, let me look at the GPIO question.
 - The pxa_restart() function was changed to use REBOOT_GPIO instead of
   'g'.

 - The tosa_poweroff() and spitz_poweroff() functions were changed to
   pass REBOOT_GPIO instead of 'g' to pxa_restart().

 - The "SHARP Tosa" machine description was setting restart_mode to 'g',
   and setting the restart function to tosa_restart() which ignored the
   'g' so I eliminated setting restart_mode to 'g' in the first place.

 - The equivalent held true for the "SHARP Spitz", "SHARP Borzoi", and
   "SHARP Akita" machines.

 - I see no other uses of 'g' for a mode being passed to a restart
   function.

Second, the restart_mode = 's' cases:
 - The "EBSA110" machine was setting it, but ebsa110_restart does not use
   the reboot mode parameter so I eliminated it.

 - The "Chalice-CATS" machine was converted from setting restart_mode = 's'
   to setting reboot_mode = REBOOT_WARM and footbridge_restart was converted
   to checking for REBOOT_WARM.

 - The "MIO A701" machine was setting it, but the mioa701_restart() function
   does not use the parameter so I eliminated it.

Of the 418 machines with ".restart =" being set, there are 73 uniq
functions being utilized.  Here is the summary of those functions:
bcm2835_restart                 mode param not used.
clps711x_restart                mode param not used.
cns3xxx_restart                 mode param not used.
corgi_restart                   mode param not used.
cpu8815_restart                 mode param not used.
da8xx_restart                   mode param not used.
davinci_restart                 mode param not used.
dove_restart                    mode param not used.
ebsa110_restart                 mode param not used.
ep93xx_restart                  mode param not used.
eva_restart                     mode param not used.
exynos4_restart                 mode param not used.
exynos5_restart                 mode param not used.
footbridge_restart              Adapted to use REBOOT_WARM instead of 's'
h720x_restart                   mode param not used.
highbank_restart                Adapted to use REBOOT_COLD instead of 'h'
imx6q_restart                   mode param not used.
integrator_restar               mode param not used.
iop13xx_restart                 mode param not used.
iop3xx_restart                  mode param not used.
ixp4xx_restart                  Adapted to use REBOOT_WARM instead of 's'
kirkwood_restart                mode param not used.
ks8695_restart                  Adapted to use REBOOT_WARM instead of 's'
kzm9g_restart                   mode param not used.
lpc23xx_restart                 Adapted to use REBOOT_WARM and REBOOT_COLD
mioa701_restart                 mode param not used.
mmp_restart                     mode param not used.
mv78xx0_restart                 mode param not used.
mvebu_restart                   mode param not used.
mxc_restart                     mode param not used.
mxs_restart                     mode param not used.
n2100_restart                   mode param not used.
netwinder_restart               Adapted to use REBOOT_WARM instead of 's'
netx_restart                    mode param not used.
nuc9xx_restart                  Adapted to use REBOOT_WARM instead of 's'
omap1_restart                   mode param not used.
omap2xxx_restart                mode param not used.
omap3xxx_restart                mode param not used.
omap44xx_restart                mode param not used.
orion5x_restart                 mode param not used.
picoxcell_wdt_restart           mode param not used.
pxa168_restart                  mode param not used.
pxa_restart                     Adapted to use REBOOT_WARM, REBOOT_COLD, and REBOOT_GPIO.
realview_eb_restart             mode param not used.
realview_pb1176_restart         mode param not used.
realview_pb11mp_restart         mode param not used.
realview_pba8_restart           mode param not used.
realview_pbx_restart            mode param not used.
rpc_restart                     mode param not used.
s3c2410_restart                 Adapted to use REBOOT_WARM instead of 's'
s3c2412_restart                 Adapted to use REBOOT_WARM instead of 's'
s3c2416_restart                 Adapted to use REBOOT_WARM instead of 's'
s3c2443_restart                 Adapted to use REBOOT_WARM instead of 's'
s3c244x_restart                 Adapted to use REBOOT_WARM instead of 's'
s3c64xx_restart                 Adapted to use REBOOT_WARM instead of 's'
s5p64x0_restart                 Adapted to use REBOOT_WARM instead of 's'
s5pc100_restart                 Adapted to use REBOOT_WARM instead of 's'
s5pv210_restart                 mode param not used.
sa11x0_restart                  Adapted to use REBOOT_WARM instead of 's'
shark_restart                   mode param not used.
sirfsoc_restart                 mode param not used.
socfpga_cyclone5_restart        mode param not used.
spear_restart                   Adapted to use REBOOT_WARM instead of 's'
spitz_restart                   mode param not used.
sunxi_restart                   mode param not used.
tegra_assert_system_reset       mode param not used.
tnetv107x_restart               mode param not used.
tosa_restart                    mode param not used.
u300_restart                    Adapted to use REBOOT_WARM and REBOOT_COLD
versatile_restart               mode param not used.
voiceblue_restart               mode param not used.
vt8500_restart                  mode param not used.

Callers to pxa_restart were converted as follows:
 - corgi_poweroff(), corgi_restart(), and poodle_poweroff() were converted
   from passing 'h' to passing REBOOT_COLD.

 - mioa701_poweroff() and mioa701_restart() were converted from passing
   's' to passing REBOOT_WARM.

 - As discussed above, tosa_poweroff() and spitz_poweroff() were converted
  from using 'g' to passing REBOOT_GPIO.

>From the above list, no other functions which utilized the mode
parameter were found being called from anything other than their machine
desription's .restart callout.

I _THOUGHT_ I had checked each and every one fairly thoroughly to
ensure all callers were converted as appropriate to pass in REBOOT_COLD,
REBOOT_WARM, or REBOOT_GPIO instead of 'h', 's', or 'g'.  It was a lot of
code to look over with no strong familiarity so I likely missed something,
but I did put an honest effort into doing this right.  If you could point
to a specific problem, I will address it.

Thanks,
Robin


From shc_work at mail.ru  Thu May  2 00:09:58 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 02 May 2013 08:09:58 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSCAzLzNdIEFSTTogZHRzOiBBZGQgTUMxMzc4MyBzdXBw?=
 =?UTF-8?B?b3J0IGZvciBpLk1YMjcgUGh5dGVjIFBDTTAzOCBtb2R1bGU=?=
In-Reply-To: <20130501191528.GB31135@pengutronix.de>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
 <1367422837.138582176@f94.mail.ru>
 <20130501191528.GB31135@pengutronix.de>
Message-ID: <1367467798.105341722@f164.mail.ru>

> On Wed, May 01, 2013 at 07:40:37PM +0400, Alexander Shiyan wrote:
> > > On Wed, May 01, 2013 at 02:46:59PM +0400, Alexander Shiyan wrote:
> > > > Added MC13783 node to imx27-phytec-phycore DT file.
> > > > 
> > > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > > ---
> > > >  arch/arm/boot/dts/imx27-phytec-phycore.dts | 92 ++++++++++++++++++++++++++++++
> > > >  1 file changed, 92 insertions(+)
> > > 
> > > You can merge this with the previous patch.
> > 
> > Part 2 just adds a SPI host for the target. Is this merge is really necessary?
> 
> The SPI host does nothing without devices registered on it, so why not
> make 2/3 and 3/3 a single patch?

At point of 2/3 user can use SPI0.0 as spidev. And in th

---

From shc_work at mail.ru  Thu May  2 00:13:44 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 02 May 2013 08:13:44 +0400
Subject: =?UTF-8?B?UmVbM106IFtQQVRDSCAzLzNdIEFSTTogZHRzOiBBZGQgTUMxMzc4MyBzdXBw?=
 =?UTF-8?B?b3J0IGZvciBpLk1YMjcgUGh5dGVjIFBDTTAzOCBtb2R1bGU=?=
In-Reply-To: <1367467798.105341722@f164.mail.ru>
References: <1367405219-19078-1-git-send-email-shc_work@mail.ru>
 <20130501191528.GB31135@pengutronix.de>
 <1367467798.105341722@f164.mail.ru>
Message-ID: <1367468024.851006021@f164.mail.ru>

> > On Wed, May 01, 2013 at 07:40:37PM +0400, Alexander Shiyan wrote:
> > > > On Wed, May 01, 2013 at 02:46:59PM +0400, Alexander Shiyan wrote:
> > > > > Added MC13783 node to imx27-phytec-phycore DT file.
> > > > > 
> > > > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > > > ---
> > > > >  arch/arm/boot/dts/imx27-phytec-phycore.dts | 92 ++++++++++++++++++++++++++++++
> > > > >  1 file changed, 92 insertions(+)
> > > > 
> > > > You can merge this with the previous patch.
> > > 
> > > Part 2 just adds a SPI host for the target. Is this merge is really necessary?
> > 
> > The SPI host does nothing without devices registered on it, so why not
> > make 2/3 and 3/3 a single patch?
> 
> At point of 2/3 user can use SPI0.0 as spidev. And in th

Please ignore this message.
Thanks.

---

From jg1.han at samsung.com  Thu May  2 01:31:43 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 02 May 2013 14:31:43 +0900
Subject: [PATCH 8/9] s3c2410fb: Remove redundant platform_set_drvdata()
In-Reply-To: <1367006543-5458-9-git-send-email-sylvester.nawrocki@gmail.com>
References: <1367006543-5458-1-git-send-email-sylvester.nawrocki@gmail.com>
 <1367006543-5458-9-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <000001ce46f6$54f27cc0$fed77640$@samsung.com>

On Saturday, April 27, 2013 5:02 AM, Sylwester Nawrocki wrote:
> driver_data field is being cleared by the driver core since
> commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
> device-core: Ensure drvdata = NULL when no driver is bound
> hence there is no need to do it in the driver's remove() callback.
> 
> Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki at gmail.com>
> ---
>  drivers/video/s3c2410fb.c |    1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
> index 11f98ca..0439ed0 100644
> --- a/drivers/video/s3c2410fb.c
> +++ b/drivers/video/s3c2410fb.c
> @@ -1013,7 +1013,6 @@ static int s3c2410fb_remove(struct platform_device *pdev)
>  	irq = platform_get_irq(pdev, 0);
>  	free_irq(irq, info);
> 
> -	platform_set_drvdata(pdev, NULL);
>  	framebuffer_release(fbinfo);

Hi Sylwester,

How about eliminating platform_set_drvdata(pdev, NULL)
in s3c24xxfb_probe() as well as s3c2410fb_remove()?

@@ -1005,7 +1005,6 @@ release_regs:
 release_mem:
        release_mem_region(res->start, size);
 dealloc_fb:
-       platform_set_drvdata(pdev, NULL);
        framebuffer_release(fbinfo);
        return ret;
 }

Best regards,
Jingoo Han

> 
>  	return 0;
> --
> 1.7.4.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From shawn.guo at linaro.org  Thu May  2 01:44:53 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 13:44:53 +0800
Subject: [PATCH] ARM: imx: Change type of ioremap function
In-Reply-To: <1367427653-6068-1-git-send-email-lauraa@codeaurora.org>
References: <1367427653-6068-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <20130502054451.GH3442@S2101-09.ap.freescale.net>

On Wed, May 01, 2013 at 10:00:53AM -0700, Laura Abbott wrote:
> Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
> (ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
> changed the type of the ioremap functions to actually use phys_addr_t.
> 
> Switch the imx ioremap functions to use phys_addr_t to avoid warnings:
> 
> arch/arm/mach-imx/mm-imx3.c: In function 'imx31_init_early':
> arch/arm/mach-imx/mm-imx3.c:142:22: warning: assignment from incompatible pointer type [enabled by default]
> arch/arm/mach-imx/mm-imx3.c: In function 'imx35_init_early':
> arch/arm/mach-imx/mm-imx3.c:221:22: warning: assignment from incompatible pointer type [enabled by default]
> 
> Signed-off-by: Laura Abbott <lauraa at codeaurora.org>

Applied, thanks.

> ---
>  arch/arm/mach-imx/mm-imx3.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
> index cefa047..f019f14 100644
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@ -65,7 +65,7 @@ static void imx3_idle(void)
>  		: "=r" (reg));
>  }
>  
> -static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
> +static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
>  					 unsigned int mtype, void *caller)
>  {
>  	if (mtype == MT_DEVICE) {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 



From shawn.guo at linaro.org  Thu May  2 01:58:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 13:58:51 +0800
Subject: [PATCH] ARM: imx: compile fix for hotplug.c
Message-ID: <1367474331-3479-1-git-send-email-shawn.guo@linaro.org>

Commit bca7a5a (ARM: cpu hotplug: remove majority of cache flushing
from platforms) removes include of <asm/cacheflush.h> and hence
discovers a few indirect inclusion and declaration problems as below.

  CC      arch/arm/mach-imx/hotplug.o
In file included from arch/arm/mach-imx/hotplug.c:16:0:
arch/arm/mach-imx/common.h:100:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
arch/arm/mach-imx/common.h:101:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_die?:
arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ?cpu_do_idle? [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_kill?:
arch/arm/mach-imx/hotplug.c:58:26: error: ?jiffies? undeclared (first use in this function)
arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ?msecs_to_jiffies? [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ?time_after? [-Werror=implicit-function-declaration]

Fix them by adding the needed inclusion and declaration.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/common.h  |    1 +
 arch/arm/mach-imx/hotplug.c |    2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4cba7db..c08ae3f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -12,6 +12,7 @@
 #define __ASM_ARCH_MXC_COMMON_H__
 
 struct platform_device;
+struct pt_regs;
 struct clk;
 enum mxc_cpu_pwr_mode;
 
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 5e91112..3daf1ed 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -11,7 +11,9 @@
  */
 
 #include <linux/errno.h>
+#include <linux/jiffies.h>
 #include <asm/cp15.h>
+#include <asm/proc-fns.h>
 
 #include "common.h"
 
-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 02:02:45 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 May 2013 14:02:45 +0800
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <201304301304.20650.arnd@arndb.de>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <201304301304.20650.arnd@arndb.de>
Message-ID: <20130502060242.GA3616@S2101-09.ap.freescale.net>

On Tue, Apr 30, 2013 at 01:04:20PM +0200, Arnd Bergmann wrote:
> >arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_die':
> >arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function 'cpu_do_idle'
> >arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_kill':
> >arch/arm/mach-imx/hotplug.c:58:26: error: 'jiffies' undeclared (first use in this function)
> >arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function 'msecs_to_jiffies'
> >arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function 'time_after'

...

> >In file included from arch/arm/mach-imx/hotplug.c:16:0:
> >arch/arm/mach-imx/common.h:100:29: warning: 'struct pt_regs' declared inside parameter list
> >arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want
> >arch/arm/mach-imx/common.h:101:29: warning: 'struct pt_regs' declared inside parameter list

I just send a patch [1] to fix these.

Shawn

[1] http://www.spinics.net/lists/arm-kernel/msg241316.html



From dirk.behme at de.bosch.com  Thu May  2 02:14:59 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Thu, 2 May 2013 08:14:59 +0200
Subject: [PATCH v3] ARM: imx: replicate the diagnostic register of boot
 cpu into secondary cores
In-Reply-To: <20130502022147.GC3442@S2101-09.ap.freescale.net>
References: <1366948645-12060-1-git-send-email-shawn.guo@linaro.org>
 <20130426132130.GE30858@mudshark.cambridge.arm.com>
 <20130426134722.GA1943@S2101-09.ap.freescale.net>
 <5181357E.3090805@gmail.com>
 <20130501153828.GC24055@mudshark.cambridge.arm.com>
 <5181408C.8090606@gmail.com>
 <20130501163817.GD24055@mudshark.cambridge.arm.com>
 <20130502022147.GC3442@S2101-09.ap.freescale.net>
Message-ID: <51820463.8050000@de.bosch.com>

On 02.05.2013 04:21, Shawn Guo wrote:
> On Wed, May 01, 2013 at 05:38:17PM +0100, Will Deacon wrote:
>> On Wed, May 01, 2013 at 05:19:24PM +0100, Dirk Behme wrote:
>>> Am 01.05.2013 17:38, schrieb Will Deacon:
>>>> On Wed, May 01, 2013 at 04:32:14PM +0100, Dirk Behme wrote:
>>> Just for a better understanding: What's wrong with using the same
>>> register values on all CPUx? I.e. with copying them from CPU0?
>>> Shouldn't all CPUx use the same setting? Or at least the same errata
>>> bits enabled?
>>
>> There's this thing called big.LITTLE... In this case, we're all A9s, but it
>> still feels horrible.
>
> It sounds more like a feeling instead of any issue in real.  Unless I
> hear some convincing technical explanation, I will send the patch for
> -rc to fix the broken reboot on imx6q.

As v3 of this patch touches only i.MX specific code, we know that i.MX6 
isn't big.LITTLE and all CPUx are the same, I agree with Shawn that it's 
ok to do it this way to fix a real bug.

Acked-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks and best regards

Dirk










From ambresh at ti.com  Thu May  2 02:25:26 2013
From: ambresh at ti.com (Ambresh K)
Date: Thu, 2 May 2013 11:55:26 +0530
Subject: [Patch 0/3] Fix to clk framework while handling orphan clks 
Message-ID: <1367475929-32166-1-git-send-email-ambresh@ti.com>

From: Ambresh K <ambresh at ti.com>

On a possible HW bug or in-correct configuration of clk_sel bits in bootloaders, there 
are high probablity of returning a value greater than available parent clocks for a 
MUX clk.     
Sensing invalid parent index, clk_mux_get_parent returns -EINVALID. 
Due to function's "u8" return type it will get converted into signed value,
thus causing following pointer dereference on test platform.

Patch series fixes the bug and also minor optimzation while re-parenting orphan clk.
 
M[    0.000000] dra7xx_clk_init: clk init (gpu_core_gclk_mux)^M
^M[    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000^M
^M[    0.000000] pgd = c0004000^M
^M[    0.000000] [00000000] *pgd=00000000^M
^M[    0.000000] Internal error: Oops: 5 [#1] SMP ARM^M
^M[    0.000000] Modules linked in:^M
^M[    0.000000] CPU: 0    Not tainted  (3.8.4-gb746a7c-dirty #59)^M
^M[    0.000000] PC is at strcmp+0x8/0x34^M
^M[    0.000000] LR is at __clk_init+0x16c/0x3cc^M
^M[    0.000000] pc : [<c033af7c>]    lr : [<c04ca314>]    psr: 600001d3^M
^M[    0.000000] sp : c09d1f70  ip : c0a12b3c  fp : 00000000^M
^M[    0.000000] r10: 00000000  r9 : c0a0f8b4  r8 : 8000406a^M
^M[    0.000000] r7 : c09d1fe4  r6 : c0a0ff40  r5 : c102888c  r4 : c0a0ff40^M
^M[    0.000000] r3 : 00000000  r2 : 00000067  r1 : 00000000  r0 : c0731c14^M
^M[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel^M
^M[    0.000000] Control: 10c53c7d  Table: 8000406a  DAC: 00000017^M
^M[    0.000000] Process swapper (pid: 0, stack limit = 0xc09d0240)^M
^M[    0.000000] Stack: (0xc09d1f70 to 0xc09d2000)^M
^M[    0.000000] 1f60:                                     00000000 c05c0518 c0731dd4 c0a0c9f8^M
^M[    0.000000] 1f80: c0a0d340 c0838f58 c09d1fe4 8000406a 412fc0f2 00000000 00000000 c0814370^M
^M[    0.000000] 1fa0: 00000005 c0837140 c0a92b78 c0806124 00000000 c09d1fc4 c100d780 c09d0000^M
^M[    0.000000] 1fc0: 00000001 00000000 c09dd6c4 c0802728 00000000 00000000 00000000 00000000^M
^M[    0.000000] 1fe0: 00000000 c0838f58 10c53c7d c09d894c c0838f54 80008078 00000000 00000000^M
^M[    0.000000] [<c033af7c>] (strcmp+0x8/0x34) from [<c04ca314>] (__clk_init+0x16c/0x3cc)^M
^M[    0.000000] [<c04ca314>] (__clk_init+0x16c/0x3cc) from [<c0814370>] (dra7xx_clk_init+0x5c/0xa8)^M
^M[    0.000000] [<c0814370>] (dra7xx_clk_init+0x5c/0xa8) from [<c0806124>] (setup_arch+0x148/0x194)^M
^M[    0.000000] [<c0806124>] (setup_arch+0x148/0x194) from [<c0802728>] (start_kernel+0x80/0x2b8)^M
^M[    0.000000] [<c0802728>] (start_kernel+0x80/0x2b8) from [<80008078>] (0x80008078)^M
^M[    0.000000] Code: e8bd0070 e12fff1e e3a03000 e7d02003 (e7d1c003) ^M
^M[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---^M
^M[    0.000000] Kernel panic - not syncing: Fatal exception^M 

Note:
1) With omap2plus_defconfig following warning are generated with the patches applied, will fix it on
reviewing the patches series. 
2) Other platforms too might have similar warnings.    

arch/arm/mach-omap2/cclock2420_data.c:116: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2420_data.c:369: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2420_data.c:417: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2420_data.c:745: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2430_data.c:116: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2430_data.c:349: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2430_data.c:397: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock2430_data.c:724: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:118: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:257: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:367: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:585: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:619: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:1176: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:2600: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock3xxx_data.c:3091: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:159: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:257: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:327: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:334: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:398: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:614: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock44xx_data.c:1329: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock33xx_data.c:105: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock33xx_data.c:182: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock33xx_data.c:225: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock33xx_data.c:481: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock33xx_data.c:601: warning: initialization from incompatible pointer type
arch/arm/mach-omap2/cclock33xx_data.c:644: warning: initialization from incompatible pointer type


Ambresh K (3):
  clk: fix clk_mux_get_parent return's signed value
  clk: skip re-parenting orphan clk
  clk: Avoid re-parenting orphan clk's having invalid parent index.

 drivers/clk/clk-mux.c        |    2 +-
 drivers/clk/clk.c            |   37 ++++++++++++++++++++++++++++++++++---
 include/linux/clk-provider.h |    4 ++--
 3 files changed, 37 insertions(+), 6 deletions(-)

-- 
1.7.4.1



From ambresh at ti.com  Thu May  2 02:25:27 2013
From: ambresh at ti.com (Ambresh K)
Date: Thu, 2 May 2013 11:55:27 +0530
Subject: [Patch 1/3] clk: fix clk_mux_get_parent return's signed value
In-Reply-To: <1367475929-32166-1-git-send-email-ambresh@ti.com>
References: <1367475929-32166-1-git-send-email-ambresh@ti.com>
Message-ID: <1367475929-32166-2-git-send-email-ambresh@ti.com>

From: Ambresh K <ambresh at ti.com>

If for some reason, the value read from clksel field return
erroneous due to HW bug or improper configuration, then
clk_mux_get_parent should return appropriate error's.

Currently if the value read is greater than the number of
available parents clk_mux_get_parent return's signed error
which will result in NULL pointer dereferencing in the
calling functions.

Signed-off-by: Ambresh K <ambresh at ti.com>
---
 drivers/clk/clk-mux.c        |    2 +-
 drivers/clk/clk.c            |   12 +++++++++++-
 include/linux/clk-provider.h |    4 ++--
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 25b1734..be0857e 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -29,7 +29,7 @@
 
 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
 
-static u8 clk_mux_get_parent(struct clk_hw *hw)
+static int clk_mux_get_parent(struct clk_hw *hw)
 {
 	struct clk_mux *mux = to_clk_mux(hw);
 	int num_parents = __clk_get_num_parents(hw->clk);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 934cfd1..c187321 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1281,7 +1281,7 @@ EXPORT_SYMBOL_GPL(clk_get_parent);
 static struct clk *__clk_init_parent(struct clk *clk)
 {
 	struct clk *ret = NULL;
-	u8 index;
+	int index;
 
 	/* handle the trivial cases */
 
@@ -1309,6 +1309,11 @@ static struct clk *__clk_init_parent(struct clk *clk)
 	 */
 
 	index = clk->ops->get_parent(clk->hw);
+	if (index < 0) {
+		pr_err("%s: clk(%s) invalid parent clk_sel index(%d)\n",
+				__func__, clk->name, index);
+		goto out;
+	}
 
 	if (!clk->parents)
 		clk->parents =
@@ -1632,6 +1637,11 @@ int __clk_init(struct device *dev, struct clk *clk)
 	hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
 		if (orphan->ops->get_parent) {
 			i = orphan->ops->get_parent(orphan->hw);
+			if (i < 0) {
+				pr_err("%s: orphan clk(%s) invalid parent\n",
+						__func__, orphan->name);
+				continue;
+			}
 			if (!strcmp(clk->name, orphan->parent_names[i]))
 				__clk_reparent(orphan, clk);
 			continue;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1186098..96337a1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -80,7 +80,7 @@ struct clk_hw;
  * 		supported by the clock.
  *
  * @get_parent:	Queries the hardware to determine the parent of a clock.  The
- * 		return value is a u8 which specifies the index corresponding to
+ * 		return value which specifies the index corresponding to
  * 		the parent clock.  This index can be applied to either the
  * 		.parent_names or .parents arrays.  In short, this function
  * 		translates the parent value read from hardware into an array
@@ -127,7 +127,7 @@ struct clk_ops {
 	long		(*round_rate)(struct clk_hw *hw, unsigned long,
 					unsigned long *);
 	int		(*set_parent)(struct clk_hw *hw, u8 index);
-	u8		(*get_parent)(struct clk_hw *hw);
+	int		(*get_parent)(struct clk_hw *hw);
 	int		(*set_rate)(struct clk_hw *hw, unsigned long,
 				    unsigned long);
 	void		(*init)(struct clk_hw *hw);
-- 
1.7.4.1



From ambresh at ti.com  Thu May  2 02:25:29 2013
From: ambresh at ti.com (Ambresh K)
Date: Thu, 2 May 2013 11:55:29 +0530
Subject: [Patch 3/3] clk: Avoid re-parenting orphan clk's having invalid
 parent index.
In-Reply-To: <1367475929-32166-1-git-send-email-ambresh@ti.com>
References: <1367475929-32166-1-git-send-email-ambresh@ti.com>
Message-ID: <1367475929-32166-4-git-send-email-ambresh@ti.com>

From: Ambresh K <ambresh at ti.com>

Add orhan clk nodes having invalid parent index to list and use
the list to skip re-parenting orphan clk having invalid parents.

Signed-off-by: Ambresh K <ambresh at ti.com>
---
 drivers/clk/clk.c |   21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f4d2c73..54d2aa3 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -32,6 +32,7 @@ static int enable_refcnt;
 
 static HLIST_HEAD(clk_root_list);
 static HLIST_HEAD(clk_orphan_list);
+static HLIST_HEAD(clk_orphan_invalid_parent);
 static LIST_HEAD(clk_notifier_list);
 
 /***           locking             ***/
@@ -1532,8 +1533,8 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
  */
 int __clk_init(struct device *dev, struct clk *clk)
 {
-	int i, ret = 0;
-	struct clk *orphan;
+	int i, ret = 0, skip = 0;
+	struct clk *orphan, *has_invalid_parent;
 	struct hlist_node *tmp2;
 
 	if (!clk)
@@ -1639,11 +1640,27 @@ int __clk_init(struct device *dev, struct clk *clk)
 		if (!strcmp(clk->name, orphan->name))
 			continue;
 
+		/* Skip iteration if orphan has invalid parent */
+		hlist_for_each_entry(has_invalid_parent,
+				&clk_orphan_invalid_parent, child_node) {
+			if (!strcmp(orphan->name, has_invalid_parent->name)) {
+				skip = 1;
+				break;
+			}
+		}
+
+		if (skip) {
+			skip = 0;
+			continue;
+		}
+
 		if (orphan->ops->get_parent) {
 			i = orphan->ops->get_parent(orphan->hw);
 			if (i < 0) {
 				pr_err("%s: orphan clk(%s) invalid parent\n",
 						__func__, orphan->name);
+				hlist_add_head(&orphan->child_node,
+						&clk_orphan_invalid_parent);
 				continue;
 			}
 			if (!strcmp(clk->name, orphan->parent_names[i]))
-- 
1.7.4.1



From ambresh at ti.com  Thu May  2 02:25:28 2013
From: ambresh at ti.com (Ambresh K)
Date: Thu, 2 May 2013 11:55:28 +0530
Subject: [Patch 2/3] clk: skip re-parenting orphan clk
In-Reply-To: <1367475929-32166-1-git-send-email-ambresh@ti.com>
References: <1367475929-32166-1-git-send-email-ambresh@ti.com>
Message-ID: <1367475929-32166-3-git-send-email-ambresh@ti.com>

From: Ambresh K <ambresh at ti.com>

If clk is same as orphan clk than skip the iteration, there
by avoiding unnecessary look-up.

Signed-off-by: Ambresh K <ambresh at ti.com>
---
 drivers/clk/clk.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c187321..f4d2c73 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1635,6 +1635,10 @@ int __clk_init(struct device *dev, struct clk *clk)
 	 * this clock
 	 */
 	hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
+		/* Skip if clk is same as orphan clk */
+		if (!strcmp(clk->name, orphan->name))
+			continue;
+
 		if (orphan->ops->get_parent) {
 			i = orphan->ops->get_parent(orphan->hw);
 			if (i < 0) {
-- 
1.7.4.1



From olof at lixom.net  Thu May  2 02:58:31 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed,  1 May 2013 23:58:31 -0700
Subject: [GIT PULL 0/5] ARM: First batch of arm-soc branches for 3.10
Message-ID: <1367477916-28399-1-git-send-email-olof@lixom.net>

Hi Linus,

We have a relatively large merge window in front of us for arm-soc,
and we're likely going to split the pull requests into 3 batches. Here's
the first of them.

There are a few merge conflicts on most branches, but none of them should
be complex to resolve. I've pushed a branch named "first-batch-resolved"
if you want to diff your resolutions with ours.


-Olof



From olof at lixom.net  Thu May  2 02:58:32 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed,  1 May 2013 23:58:32 -0700
Subject: [GIT PULL 1/5] ARM: arm-soc non-critical fixes for 3.10
In-Reply-To: <1367477916-28399-1-git-send-email-olof@lixom.net>
References: <1367477916-28399-1-git-send-email-olof@lixom.net>
Message-ID: <1367477916-28399-2-git-send-email-olof@lixom.net>

Here is a collection of fixes (and some intermixed cleanups) that were
considered less important and thus not included in the later parts of
the 3.9-rc cycle.

It's a bit all over the map, contents wise. A series of ux500 fixes
and cleanups, a bunch of various fixes for OMAP and tegra, and some for
Freescale i.MX and even Qualcomm MSM.

Note that there's also a patch on this branch to globally turn off
-Wmaybe-uninitialized when building with -Os. It's been posted several
times by Arnd and no dissent was raised, but nobody seemed interested
to pick it up. So here it is, as the topmost patch.


Conflicts:

arch/arm/boot/dts/dbx5x0.dtsi: Change/add conflict with a fix from
3.9. The first reg entry should have size 0x2000, and the two new regs
(and names) should stay.

----------------------------------------------------------------

The following changes since commit 20b4fb485227404329e41ad15588afad3df23050:

  Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-nc-for-linus

for you to fetch changes up to e74fc973b6e531fef1fce8b101ffff05ecfb774c:

  Turn off -Wmaybe-uninitialized when building with -Os

----------------------------------------------------------------

Arnd Bergmann (8):
      Merge tag 'ux500-dt-fixes' of git://git.kernel.org/.../linusw/linux-stericsson into next/fixes-non-critical
      Merge tag 'v3.9-rc1_cns3xxx_fixes' of git://git.infradead.org/users/cbou/linux-cns3xxx into next/fixes-non-critical
      Merge tag 'omap-for-v3.10/fixes-non-critical-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/.../swarren/linux-tegra into next/fixes-non-critical
      ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
      ARM: tegra: call cpu_do_idle from C code
      ARM: orion5x: include linux/cpu.h
      Turn off -Wmaybe-uninitialized when building with -Os

Fabio Estevam (15):
      ARM: mach-imx: cpu: Include "common.h"
      ARM: mach-imx: mm-imx3: Staticize imx3_init_l2x0()
      ARM: mach-imx: iomux-imx31: Staticize mxc_pin_alloc_map
      ARM: mach-imx: cpu-imx5: Include "common.h"
      ARM: mach-imx: clk-pllv1: Staticize clk_pllv1_ops
      ARM: mach-imx: clk-pllv2: Staticize clk_pllv2_ops
      ARM: mach-imx: clk-gate2: Include "clk.h"
      ARM: mach-imx: irq-common: Remove imx_irq_set_priority()
      ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
      ARM: mach-imx: clk: Include "clk.h"
      ARM: mach-imx: tzic: Staticize *tzic_base
      ARM: mach-imx: avic: Staticize *avic_base
      ARM: mach-imx: gpc: Include "common.h"
      ARM: mach-imx: src: Include "common.h
      ARM: mach-imx: mach-imx6q: Fix sparse warnings

Hiroshi Doyu (2):
      ARM: tegra: Fix unchecked return value
      memory: tegra30: Fix build error w/o PM

Joseph Lo (5):
      ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host
      ARM: tegra: don't unlock MMIO access to DBGLAR
      ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs
      ARM: tegra: fix build error when THUMB2_KERNEL enabled
      ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled

Lee Jones (16):
      ARM: ux500: Change IRQ from low-to-high edge triggered to high-to-low
      ARM: ux500: Include the PRCMU's Secure Registers in DB8500's DT
      ARM: ux500: Provide a means to obtain the SMSC9115 clock when DT is enabled
      clk: ux500: Ensure the FMSC clock is obtainable
      clk: ux500: Provide an alias for the SMSC911x Ethernet chip
      net/smsc911x: Provide common clock functionality
      mmc: mmci: Move ios_handler functionality into the driver
      ARM: ux500: Set correct MMCI regulator voltages in the ux5x0 Device Tree
      ARM: ux500: Specify the ux5x0 MMCI regulator's on/off GPIO as high-enable
      ARM: ux500: Specify which IOS regulator to use for MMCI
      ARM: ux500: Use the correct name when supplying a GPIO enable pin
      ARM: ux500: Setup correct settling time for the MMCI regulator
      ARM: ux500: Use the GPIO regulator framework for SDI0's 'en' and 'vsel'
      ARM: ux500: Remove traces of the ios_handler from platform code
      ARM: ux500: enable AB8500 GPIO for HREF
      ARM: ux500: allow Snowball access to the AB8500 GPIO pins

Linus Walleij (1):
      ARM: u300: fix ages old copy/paste bug

Mac Lin (1):
      ARM: cns3xxx: remove unused virtual address and iotable defines

Olof Johansson (2):
      Merge tag 'imx-noncritical-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/fixes-non-critical
      Merge tag 'msm-fix-3.10' of git://git.kernel.org/.../davidb/linux-msm into next/fixes-non-critical

Paul Bolle (4):
      ARM: OMAP: fix typo "CONFIG_SMC91x_MODULE"
      ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
      ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
      ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro

Paul Walmsley (1):
      ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0

Pawel Moll (1):
      ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms

Peter De Schrijver (1):
      clk: tegra: No 7.1 super clk dividers on Tegra20

Rajendra Nayak (3):
      ARM: OMAP5: clock: No Freqsel on OMAP5 devices too
      ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
      ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass

Santosh Shilimkar (6):
      ARM: OMAP5: Update SOC id detection code for ES2
      ARM: OMAP5: timer: Update the clocksource name as per clock data
      ARM: OMAP5: prm: Allow prm init to succeed
      ARM: OMAP5: Update SAR RAM base address
      ARM: OMAP5: Update SAR memory layout for WakeupGen
      ARM: OMAP5: Make errata i688 workaround available

Stephen Boyd (1):
      ARM: msm: Fix uncompess.h tx underrun check

Stephen Warren (4):
      ARM: tegra: add CPU errata WARs to Tegra reset handler
      ARM: tegra: remove save/restore of CPU diag register
      ARM: tegra: fix ignored return value of regulator_enable
      ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled

Tero Kristo (1):
      ARM: OMAP5: Reuse prm read_inst/write_inst

Thierry Reding (2):
      ARM: tegra: Export tegra_powergate_sequence_power_up()
      ARM: tegra: powergate: Don't error out if new state == old state

Tony Lindgren (2):
      Merge tag 'omap-devel-b-for-3.10' of git://git.kernel.org/.../pjw/omap-pending into omap-for-v3.10/fixes-non-critical
      Merge branch 'for_3.10/omap5_generic_updates' of git://git.kernel.org/.../ssantosh/linux into omap-for-v3.10/fixes-non-critical

Vaibhav Hiremath (2):
      ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
      ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk


 Makefile                                      |  2 +-
 arch/arm/boot/dts/dbx5x0.dtsi                 |  7 ++-
 arch/arm/boot/dts/href.dtsi                   |  1 +
 arch/arm/boot/dts/hrefprev60.dts              | 10 ++++-
 arch/arm/boot/dts/snowball.dts                |  4 ++
 arch/arm/boot/dts/stuib.dtsi                  |  2 +-
 arch/arm/boot/dts/tegra20-colibri-512.dtsi    |  2 +-
 arch/arm/boot/dts/tegra20-harmony.dts         |  4 +-
 arch/arm/boot/dts/tegra20-paz00.dts           |  2 +-
 arch/arm/boot/dts/tegra20-seaboard.dts        |  2 +-
 arch/arm/boot/dts/tegra20-tamonten.dtsi       |  2 +-
 arch/arm/boot/dts/tegra20-trimslice.dts       |  2 +-
 arch/arm/boot/dts/tegra20-ventana.dts         |  2 +-
 arch/arm/boot/dts/tegra20-whistler.dts        |  1 +
 arch/arm/boot/dts/tegra30-beaver.dts          |  2 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi         |  2 +-
 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts   |  2 +-
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts    |  2 +-
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts       |  2 +-
 arch/arm/mach-cns3xxx/core.c                  | 10 -----
 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h  | 27 ------------
 arch/arm/mach-imx/avic.c                      |  2 +-
 arch/arm/mach-imx/clk-busy.c                  |  2 +-
 arch/arm/mach-imx/clk-gate2.c                 |  1 +
 arch/arm/mach-imx/clk-pllv1.c                 |  2 +-
 arch/arm/mach-imx/clk-pllv2.c                 |  2 +-
 arch/arm/mach-imx/clk.c                       |  1 +
 arch/arm/mach-imx/cpu-imx5.c                  |  1 +
 arch/arm/mach-imx/cpu.c                       |  1 +
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c  |  4 +-
 arch/arm/mach-imx/gpc.c                       |  1 +
 arch/arm/mach-imx/iomux-imx31.c               |  2 +-
 arch/arm/mach-imx/irq-common.c                | 19 --------
 arch/arm/mach-imx/mach-cpuimx27.c             |  4 +-
 arch/arm/mach-imx/mach-imx6q.c                |  4 +-
 arch/arm/mach-imx/mm-imx3.c                   |  2 +-
 arch/arm/mach-imx/src.c                       |  1 +
 arch/arm/mach-imx/tzic.c                      |  2 +-
 arch/arm/mach-msm/include/mach/uncompress.h   |  2 +-
 arch/arm/mach-omap1/Kconfig                   |  6 ---
 arch/arm/mach-omap2/Kconfig                   |  7 ++-
 arch/arm/mach-omap2/board-2430sdp.c           |  2 +-
 arch/arm/mach-omap2/board-h4.c                |  2 +-
 arch/arm/mach-omap2/cclock33xx_data.c         |  8 ++++
 arch/arm/mach-omap2/dpll3xxx.c                | 30 ++++++-------
 arch/arm/mach-omap2/dsp.c                     |  4 +-
 arch/arm/mach-omap2/id.c                      | 12 +++--
 arch/arm/mach-omap2/io.c                      |  9 ++++
 arch/arm/mach-omap2/omap4-common.c            | 10 ++++-
 arch/arm/mach-omap2/omap4-sar-layout.h        | 14 +++---
 arch/arm/mach-omap2/omap54xx.h                |  1 +
 arch/arm/mach-omap2/omap_hwmod.c              |  4 --
 arch/arm/mach-omap2/omap_hwmod.h              |  6 +--
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c    | 15 +++++++
 arch/arm/mach-omap2/powerdomain.c             | 18 ++++----
 arch/arm/mach-omap2/prm44xx.c                 |  6 +--
 arch/arm/mach-omap2/soc.h                     |  2 +
 arch/arm/mach-omap2/timer.c                   |  5 ++-
 arch/arm/mach-orion5x/common.c                |  1 +
 arch/arm/mach-tegra/board-harmony-pcie.c      |  7 ++-
 arch/arm/mach-tegra/cpuidle-tegra30.c         |  4 --
 arch/arm/mach-tegra/headsmp.S                 |  3 --
 arch/arm/mach-tegra/platsmp.c                 |  5 ++-
 arch/arm/mach-tegra/pm.c                      | 24 +++-------
 arch/arm/mach-tegra/powergate.c               |  4 +-
 arch/arm/mach-tegra/reset-handler.S           | 49 +++++++++++++++++----
 arch/arm/mach-tegra/sleep-tegra20.S           |  2 +-
 arch/arm/mach-tegra/sleep-tegra30.S           |  4 +-
 arch/arm/mach-tegra/sleep.h                   |  2 +-
 arch/arm/mach-u300/include/mach/u300-regs.h   |  2 +-
 arch/arm/mach-ux500/board-mop500-regulators.c | 14 ++++++
 arch/arm/mach-ux500/board-mop500-regulators.h |  1 +
 arch/arm/mach-ux500/board-mop500-sdi.c        | 51 ----------------------
 arch/arm/mach-ux500/board-mop500.c            | 45 +++++++++++++++++++
 arch/arm/mach-ux500/cpu-db8500.c              |  1 +
 drivers/clk/tegra/clk-tegra20.c               | 36 +--------------
 drivers/clk/ux500/u8500_clk.c                 |  3 +-
 drivers/mmc/host/mmci.c                       |  9 ++++
 drivers/net/ethernet/smsc/smsc911x.c          | 29 +++++++++++-
 79 files changed, 321 insertions(+), 279 deletions(-)


From olof at lixom.net  Thu May  2 02:58:34 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed,  1 May 2013 23:58:34 -0700
Subject: [GIT PULL 3/5] ARM: arm-soc device-tree updates for 3.10, part 1
In-Reply-To: <1367477916-28399-1-git-send-email-olof@lixom.net>
References: <1367477916-28399-1-git-send-email-olof@lixom.net>
Message-ID: <1367477916-28399-4-git-send-email-olof@lixom.net>

Device-tree updates for 3.10. The bulk of the churn in this branch is due
to i.MX moving from C-defined pin control over to device tree, which is
a one-time conversion that will allow greater flexibility down the road.

Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
handful of cleanups to tegra due to the new include file functionality
of the device tree compiler.


Conflicts:

arch/arm/boot/dts/at91sam9x5.dtsi: Two add/add conflicts. Keep both
sides on both, make sure that the upper entries have balanced close
braces. Also, on the last conflict, make sure spi1 has a 'status =
"disabled"' property.

drivers/pinctrl/Makefile: Add/remove. Keep imx6dl, remove pxa3xx.

----------------------------------------------------------------

The following changes since commit 22d9b30cebe1bc2a78f5a2db583f94f3300b97d6:

  Merge branch 'next/cleanup' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/dt-for-linus

for you to fetch changes up to 88cf9c5e494795a53ec360d0b38f483a6d4e508f:

  Merge tag 'sunxi-dt-for-3.10-4' of git://github.com/mripard/linux into next/dt

----------------------------------------------------------------

Alexander Clouter (2):
      arm: orion5x: add ehci bindings to dtsi
      arm: orion5x: enable xor for orion5x platform

Alexander Shiyan (2):
      ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module
      ARM: dts: Add missing imx27-phytec-phycore dtb target

Andrew Lunn (1):
      Dove: Thermal: Add DT node and enable in defconfig

Arnd Bergmann (8):
      Merge tag 'mvebu_dt_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/dt
      Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
      Merge tag 'sunxi-dt-for-3.10' of git://github.com/mripard/linux into next/dt
      Merge branch 'zynq/core' of git://git.xilinx.com/linux-xlnx into next/dt
      Merge tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/.../swarren/linux-rpi into next/dt
      Merge tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux into next/dt
      Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
      Merge tag 'tegra-for-3.10-fixes-for-mmc' of git://git.kernel.org/.../swarren/linux-tegra into next/dt

Dirk Behme (1):
      ARM: dts: imx6q: add PMU

Douglas Gilbert (2):
      ARM: at91: add Acme Systems Aria G25 board
      ARM: at91/at91sam9260.dtsi: fix u(s)art pinctrl encoding

Emilio L?pez (8):
      sunxi: a10-cubieboard: Add user LEDs to the device tree
      arm: sunxi: Add clock definitions for the new clock driver
      arm: sunxi: rename clock compatible strings
      ARM: sunxi: cubieboard: Add UART muxing
      arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
      arm: sunxi: use the right clock phandles for UARTs
      arm: sunxi: Add clock to pinctrl node
      ARM: sunxi: unify osc24M_fixed and osc24M

Ezequiel Garcia (8):
      ARM: mvebu: Add button on Armada 370 Reference Design board
      ARM: mvebu: Add thermal support to Armada XP device tree
      ARM: mvebu: Add thermal support to Armada 370 device tree
      ARM: configs: Update mvebu defconfig for thermal
      ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
      ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
      ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
      ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig

Fabio Estevam (3):
      ARM: mx27: Replace clk_register_clkdev with clock DT lookup
      ARM: dts: Add initial support for Wandboard Dual-Lite
      ARM: dts: imx6dl-wandboard: Add USB Host support

Gregory CLEMENT (1):
      arm: mvebu: enable gpio expander over i2c on Mirabox platform

Gwenhael Goavec-Merou (5):
      ARM: imx: Add support for the Armadeus Systems APF51Dev docking board
      ARM: imx51: Add pinctrl for ecspi2
      ARM: imx51: Add a second pinctrl group for i2c2
      ARM: imx: apf51dev: add ecspi1, ecspi2 and i2c2 support
      ARM: imx: Add support for the Armadeus Systems APF27Dev docking board

Joachim Eastwood (3):
      ARM: at91: add TWI bindings to RM9200 DT
      ARM: at91: add pinctrl nodes to i2c-gpio on RM92000 DT
      ARM: at91: add MPA 1600 DT board

Lior Amsalem (1):
      ARM: dts: Add a 64 bits version of the skeleton device tree

Lubomir Rintel (1):
      ARM: bcm2835: add Broadcom BCM2835 RNG to the device tree

Ludovic Desroches (1):
      ARM: at91: dts: add adc resolution stuff

Marek Vasut (1):
      ARM: dts: imx53: fix SD2_DATA1 pad AUDMUX_AUD4 configuration

Markus Pargmann (3):
      ARM: imx27 DT init cpufreq-cpu0 device
      ARM: imx5 DT init cpufreq-cpu0 device
      ARM: dts: imx51 cpu node

Maxime Ripard (13):
      sunxi: dts: Report the pinctrl nodes as gpio-controllers
      sunxi: a13-olinuxino: Add user LED to the device tree
      ARM: sunxi: dt: Add support for the PineRiver Mini X-plus
      ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
      ARM: sunxi: Rename uart nodes to serial
      ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
      ARM: sunxi: dt: Add uart3 dt node
      ARM: sunxi: dt: Add A10 UARTs to the dtsi.
      ARM: sunxi: hackberry: Add UART muxing
      ARM: sunxi: dt: Reorganize the dtsi
      ARM: sunxi: dt: Update timer compatible string
      ARM: sunxi: dt: Update interrupt controller compatible string
      ARM: sunxi: dt: Update watchdog compatible string

Michal Simek (1):
      arm: zynq: Add support for pmu

Nicolas Ferre (6):
      ARM: at91/dt: gpio-keys: remove address-cells and size-cells properties
      ARM: at91/at91sam9x5: add RTC node
      ARM: at91/trivial: typos in compatible property
      ARM: at91/trivial: fix model name for SAM9G15-EK
      ARM: at91: remove partial parameter in bootargs for at91sam9x5ek.dtsi
      ARM: at91/dt: fix macb node declaration

Nobuhiro Iwamatsu (1):
      ARM: Kirkwood: Add support thermal sensor for 88F6282 and 88F6283

Olof Johansson (4):
      Merge tag 'sunxi-dt-for-3.10-3' of git://github.com/mripard/linux into next/dt
      Merge tag 'dt-3.10-3' of git://git.infradead.org/users/jcooper/linux into next/dt
      Merge tag 'imx-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
      Merge tag 'sunxi-dt-for-3.10-4' of git://github.com/mripard/linux into next/dt

Pavel Machek (1):
      ARM: dts: MicroSys sbc6x support (i.MX6)

Peter Chen (1):
      ARM: dts: imx6q-sabresd: Add USB support

Philipp Zabel (6):
      ARM i.MX5: Move IPU clock lookups into device tree
      ARM i.MX53: Add IOMUXC GPR to device tree
      ARM i.MX53: Add LDB device to device tree
      ARM i.MX6q: Link system reset controller (SRC) to IPU in DT
      ARM i.MX5: Add system reset controller (SRC) to i.MX51 and i.MX53 device tree
      ARM i.MX5: Add System Reset Controller (SRC) support for i.MX51 and i.MX53

Richard Genoud (4):
      ARM: at91: dt: at91sam9x5: add i2c pinctrl
      ARM: at91: dt: at91sam9x5: add i2c-gpio pinctrl
      ARM: at91/at91sam9x5ek: i2c1 and i2c2 conflict with macb and lcd
      ARM: at91/at91sam9x5cm: add 1-wire chip on CM board

Ryan Press (1):
      arm: mvebu: Add GPIO LEDs to Mirabox board

Sascha Hauer (8):
      ARM: i.MX: Add GPT devicetree Documentation
      ARM: i.MX27: Add GPT devicetree nodes
      ARM: i.MX31: Add GPT devicetree node
      ARM: i.MX51: Add GPT devicetree node
      ARM: i.MX53: Add GPT devicetree node
      ARM: i.MX6: Add clocks to GPT devicetree node
      ARM: i.MX27: Add clocks to GPT devicetree nodes
      ARM: i.MX51: Add PATA support

Sean Cross (3):
      ARM: dts: imx6q: Add pinctrl for ecspi3
      ARM: dts: imx6q: Add pinctrl for i2c2 and i2c3
      ARM: dts: imx6q: Add pinctrl for audmix on AUD3

Sebastian Hesselbarth (1):
      ARM: kirkwood: make use of DT mvsdio on guruplug board

Shawn Guo (9):
      Merge tag 'imx-cleanup-3.10' into imx/dt
      Merge remote-tracking branch 'swarren/for-3.10/dtc-cpp-chroot-std-headers' into imx/dt
      ARM: imx: use #include for all device trees
      pinctrl: imx: move hard-coding data into device tree
      pinctrl: add pinctrl driver for imx6dl
      pinctrl: add pinctrl driver for imx6sl
      ARM: dts: imx: make sabreauto and sabresd common
      ARM: dts: imx: add initial imx6dl-sabresd support
      ARM: dts: imx: add initial imx6dl-sabreauto support

Steffen Trumtrar (1):
      ARM i.MX6q: Add LDB device to device tree

Stephen Warren (8):
      ARM: bcm2835: add SPI device to DT
      kbuild: create an "include chroot" for DT bindings
      kbuild: fixdep: support concatenated dep files
      kbuild: cmd_dtc_cpp: extract deps from both gcc -E and dtc
      kbuild: always run gcc -E on *.dts, remove cmd_dtc_cpp
      ARM: dt: add header to define GPIO flags
      ARM: dt: add header to define IRQ flags
      ARM: dt: create a DT header for the GIC

Thomas Petazzoni (7):
      arm: mvebu: add PCIe Device Tree informations for Armada 370
      arm: mvebu: add PCIe Device Tree informations for Armada XP
      arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
      arm: mvebu: PCIe Device Tree informations for Armada XP DB
      arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
      arm: mvebu: PCIe Device Tree informations for Armada 370 DB
      arm: mvebu: PCIe Device Tree informations for Armada XP GP

Tony Prisk (1):
      arm: vt8500: Add SDHC support to WM8505 DT


 .../devicetree/bindings/clock/imx27-clock.txt   |  117 +
 .../bindings/pinctrl/fsl,imx-pinctrl.txt        |    6 +-
 .../bindings/pinctrl/fsl,imx35-pinctrl.txt      |  955 +-------
 .../bindings/pinctrl/fsl,imx51-pinctrl.txt      |  759 +-----
 .../bindings/pinctrl/fsl,imx53-pinctrl.txt      | 1174 +--------
 .../bindings/pinctrl/fsl,imx6dl-pinctrl.txt     |   38 +
 .../bindings/pinctrl/fsl,imx6q-pinctrl.txt      | 1596 +-----------
 .../bindings/pinctrl/fsl,imx6sl-pinctrl.txt     |   39 +
 .../devicetree/bindings/timer/fsl,imxgpt.txt    |   18 +
 arch/arm/boot/dts/Makefile                      |   11 +-
 arch/arm/boot/dts/armada-370-db.dts             |   17 +
 arch/arm/boot/dts/armada-370-mirabox.dts        |   64 +
 arch/arm/boot/dts/armada-370-rd.dts             |   11 +
 arch/arm/boot/dts/armada-370-xp.dtsi            |   45 +
 arch/arm/boot/dts/armada-370.dtsi               |   58 +
 arch/arm/boot/dts/armada-xp-db.dts              |   33 +
 arch/arm/boot/dts/armada-xp-gp.dts              |   50 +
 arch/arm/boot/dts/armada-xp-mv78230.dtsi        |  104 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi        |  122 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi        |  188 ++
 .../arm/boot/dts/armada-xp-openblocks-ax3-4.dts |   38 +
 arch/arm/boot/dts/armada-xp.dtsi                |    6 +
 arch/arm/boot/dts/at91-ariag25.dts              |  171 ++
 arch/arm/boot/dts/at91rm9200.dtsi               |   28 +
 arch/arm/boot/dts/at91sam9260.dtsi              |   19 +-
 arch/arm/boot/dts/at91sam9263ek.dts             |    2 -
 arch/arm/boot/dts/at91sam9g15.dtsi              |    2 +-
 arch/arm/boot/dts/at91sam9g15ek.dts             |    2 +-
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi     |    2 -
 arch/arm/boot/dts/at91sam9g25.dtsi              |    2 +-
 arch/arm/boot/dts/at91sam9g25ek.dts             |    9 +
 arch/arm/boot/dts/at91sam9g35.dtsi              |    2 +-
 arch/arm/boot/dts/at91sam9g35ek.dts             |    9 +
 arch/arm/boot/dts/at91sam9g45.dtsi              |    3 +
 arch/arm/boot/dts/at91sam9m10g45ek.dts          |    2 -
 arch/arm/boot/dts/at91sam9n12ek.dts             |    2 -
 arch/arm/boot/dts/at91sam9x25.dtsi              |    2 +-
 arch/arm/boot/dts/at91sam9x25ek.dts             |   14 +
 arch/arm/boot/dts/at91sam9x35.dtsi              |    2 +-
 arch/arm/boot/dts/at91sam9x35ek.dts             |    9 +
 arch/arm/boot/dts/at91sam9x5.dtsi               |   70 +
 arch/arm/boot/dts/at91sam9x5cm.dtsi             |   20 +
 arch/arm/boot/dts/at91sam9x5ek.dtsi             |   15 +-
 arch/arm/boot/dts/bcm2835.dtsi                  |   22 +
 arch/arm/boot/dts/dove.dtsi                     |    5 +
 arch/arm/boot/dts/imx25-karo-tx25.dts           |    2 +-
 arch/arm/boot/dts/imx25-pdk.dts                 |    2 +-
 arch/arm/boot/dts/imx25.dtsi                    |    2 +-
 arch/arm/boot/dts/imx27-apf27.dts               |    2 +-
 arch/arm/boot/dts/imx27-apf27dev.dts            |   60 +
 arch/arm/boot/dts/imx27-pdk.dts                 |    2 +-
 arch/arm/boot/dts/imx27-phytec-phycore.dts      |    8 +-
 arch/arm/boot/dts/imx27.dtsi                    |   82 +-
 arch/arm/boot/dts/imx31-bug.dts                 |    2 +-
 arch/arm/boot/dts/imx31.dtsi                    |   18 +-
 arch/arm/boot/dts/imx35-pinfunc.h               |  970 ++++++++
 arch/arm/boot/dts/imx51-apf51.dts               |    2 +-
 arch/arm/boot/dts/imx51-apf51dev.dts            |   97 +
 arch/arm/boot/dts/imx51-babbage.dts             |   16 +-
 arch/arm/boot/dts/imx51-pinfunc.h               |  773 ++++++
 arch/arm/boot/dts/imx51.dtsi                    |  343 ++-
 arch/arm/boot/dts/imx53-ard.dts                 |   70 +-
 arch/arm/boot/dts/imx53-evk.dts                 |   18 +-
 arch/arm/boot/dts/imx53-mba53.dts               |   82 +-
 arch/arm/boot/dts/imx53-pinfunc.h               | 1189 +++++++++
 arch/arm/boot/dts/imx53-qsb.dts                 |   22 +-
 arch/arm/boot/dts/imx53-smd.dts                 |   16 +-
 arch/arm/boot/dts/imx53-tqma53.dtsi             |   32 +-
 arch/arm/boot/dts/imx53.dtsi                    |  256 +-
 arch/arm/boot/dts/imx6dl-pinfunc.h              | 1085 +++++++++
 arch/arm/boot/dts/imx6dl-sabreauto.dts          |   31 +
 arch/arm/boot/dts/imx6dl-sabresd.dts            |   35 +
 arch/arm/boot/dts/imx6dl-wandboard.dts          |   44 +
 arch/arm/boot/dts/imx6dl.dtsi                   |  125 +-
 arch/arm/boot/dts/imx6q-arm2.dts                |    8 +-
 arch/arm/boot/dts/imx6q-pinfunc.h               | 1041 ++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts           |   33 +-
 arch/arm/boot/dts/imx6q-sabrelite.dts           |   18 +-
 arch/arm/boot/dts/imx6q-sabresd.dts             |   67 +-
 arch/arm/boot/dts/imx6q-sbc6x.dts               |   44 +
 arch/arm/boot/dts/imx6q.dtsi                    |  280 ++-
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi        |   38 +
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi          |   87 +
 arch/arm/boot/dts/imx6qdl.dtsi                  |   33 +-
 arch/arm/boot/dts/imx6sl-pinfunc.h              | 1077 ++++++++
 arch/arm/boot/dts/include/dt-bindings           |    1 +
 arch/arm/boot/dts/kirkwood-6282.dtsi            |    6 +
 .../boot/dts/kirkwood-guruplug-server-plus.dts  |    4 +
 arch/arm/boot/dts/mpa1600.dts                   |   69 +
 arch/arm/boot/dts/orion5x.dtsi                  |   33 +
 arch/arm/boot/dts/skeleton64.dtsi               |   13 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts      |   32 +-
 arch/arm/boot/dts/sun4i-a10-hackberry.dts       |    6 +-
 arch/arm/boot/dts/sun4i-a10-mini-xplus.dts      |   32 +
 arch/arm/boot/dts/sun4i-a10.dtsi                |  253 +-
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts       |   24 +-
 arch/arm/boot/dts/sun5i-a13.dtsi                |  193 +-
 arch/arm/boot/dts/sunxi.dtsi                    |   82 -
 arch/arm/boot/dts/wm8505.dtsi                   |   31 +
 arch/arm/boot/dts/zynq-7000.dtsi                |    7 +
 arch/arm/configs/dove_defconfig                 |    2 +
 arch/arm/configs/kirkwood_defconfig             |    2 +
 arch/arm/configs/mvebu_defconfig                |    9 +
 arch/arm/mach-at91/at91rm9200.c                 |    1 +
 arch/arm/mach-imx/Kconfig                       |    2 +
 arch/arm/mach-imx/clk-imx27.c                   |   11 +-
 arch/arm/mach-imx/clk-imx51-imx53.c             |    9 +-
 arch/arm/mach-imx/imx27-dt.c                    |   22 +-
 arch/arm/mach-imx/imx51-dt.c                    |    3 +
 arch/arm/mach-imx/mm-imx5.c                     |    2 +
 arch/arm/mach-imx/src.c                         |    4 +-
 arch/arm/mach-kirkwood/board-guruplug.c         |    6 -
 drivers/pinctrl/Kconfig                         |   12 +-
 drivers/pinctrl/Makefile                        |    1 +
 drivers/pinctrl/pinctrl-imx.c                   |  126 +-
 drivers/pinctrl/pinctrl-imx.h                   |   29 +-
 drivers/pinctrl/pinctrl-imx35.c                 | 2088 ++++++----------
 drivers/pinctrl/pinctrl-imx51.c                 | 1532 ++++--------
 drivers/pinctrl/pinctrl-imx53.c                 | 1597 ++----------
 drivers/pinctrl/pinctrl-imx6dl.c                |  497 ++++
 drivers/pinctrl/pinctrl-imx6q.c                 | 2301 ++----------------
 drivers/pinctrl/pinctrl-imx6sl.c                |  403 +++
 include/dt-bindings/gpio/gpio.h                 |   15 +
 .../dt-bindings/interrupt-controller/arm-gic.h  |   22 +
 include/dt-bindings/interrupt-controller/irq.h  |   19 +
 scripts/Makefile.lib                            |   17 +-
 scripts/basic/fixdep.c                          |   93 +-
 127 files changed, 12434 insertions(+), 11152 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx27-clock.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
 create mode 100644 arch/arm/boot/dts/at91-ariag25.dts
 create mode 100644 arch/arm/boot/dts/imx27-apf27dev.dts
 create mode 100644 arch/arm/boot/dts/imx35-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx51-apf51dev.dts
 create mode 100644 arch/arm/boot/dts/imx51-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx53-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6dl-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6dl-sabreauto.dts
 create mode 100644 arch/arm/boot/dts/imx6dl-sabresd.dts
 create mode 100644 arch/arm/boot/dts/imx6dl-wandboard.dts
 create mode 100644 arch/arm/boot/dts/imx6q-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6q-sbc6x.dts
 create mode 100644 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
 create mode 100644 arch/arm/boot/dts/imx6qdl-sabresd.dtsi
 create mode 100644 arch/arm/boot/dts/imx6sl-pinfunc.h
 create mode 120000 arch/arm/boot/dts/include/dt-bindings
 create mode 100644 arch/arm/boot/dts/mpa1600.dts
 create mode 100644 arch/arm/boot/dts/skeleton64.dtsi
 create mode 100644 arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
 delete mode 100644 arch/arm/boot/dts/sunxi.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-imx6dl.c
 create mode 100644 drivers/pinctrl/pinctrl-imx6sl.c
 create mode 100644 include/dt-bindings/gpio/gpio.h
 create mode 100644 include/dt-bindings/interrupt-controller/arm-gic.h
 create mode 100644 include/dt-bindings/interrupt-controller/irq.h


From olof at lixom.net  Thu May  2 02:58:35 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed,  1 May 2013 23:58:35 -0700
Subject: [GIT PULL 4/5] ARM: arm-soc platform updates for 3.10, part 1
In-Reply-To: <1367477916-28399-1-git-send-email-olof@lixom.net>
References: <1367477916-28399-1-git-send-email-olof@lixom.net>
Message-ID: <1367477916-28399-5-git-send-email-olof@lixom.net>

This branch contains platform updates for 3.10. Among the highlights:

- Support for the new Atmel Cortex-A5 based platforms (SAMA5D3)
- New support for CSR SiRFatlas6 SoCs
- A handful of updates for NVidia T114 (a.k.a. Tegra 4)
- A bunch of updates for the shmobile platforms
- A handful of updates for davinci
- A few updates for Qualcomm MSM
- Plus a handful of other patches, defconfig updates, etc.


Conflicts:

Documentation/kernel-parameters.txt: Trivial add/add conflict

arch/arm/mach-exynos/cpuidle.c: Add/remove conflict. Take away the
"en_core_tk_irqen" line but keep the rest of the branch contents.

----------------------------------------------------------------

The following changes since commit 429b8d7cfc7394dd040525e963e3f08df478477c:

  Merge branch 'next/dt' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/soc-for-linus

for you to fetch changes up to e0d20b69d3fa74a21ec363989612bddd58b930b8:

  Merge branch 'gic/cleanup' into next/soc

----------------------------------------------------------------

Arnd Bergmann (15):
      Merge branch 'prima2/soc' into next/soc
      Merge tag 'ux500-defconfig-v3.10' of git://git.kernel.org/.../linusw/linux-stericsson into next/soc
      Merge tag 'ux500-core-v3.10' of git://git.kernel.org/.../linusw/linux-stericsson into next/soc
      Merge tag 'renesas-defconfig-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc
      Merge tag 'renesas-soc-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc
      Merge tag 'omap-for-v3.10/crypto-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/soc
      Merge tag 'bcm2835-for-3.10-defconfig' of git://git.kernel.org/.../swarren/linux-rpi into next/soc
      Merge tag 'davinci-for-v3.10/soc' of git://git.kernel.org/.../nsekhar/linux-davinci into next/soc
      Merge tag 'davinci-for-v3.10/dt' of git://git.kernel.org/.../nsekhar/linux-davinci into next/soc
      Merge branch 'tegra/cleanup' into next/soc
      Merge tag 'tegra-for-3.10-soc' of git://git.kernel.org/.../swarren/linux-tegra into next/soc
      Merge tag 'mxs-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge tag 'omap-for-v3.10/soc-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/soc
      Merge tag 'tegra-for-3.10-defconfig' of git://git.kernel.org/.../swarren/linux-tegra into next/soc
      Merge tag 'devel-samsung-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/soc

Artem Bityutskiy (1):
      ARM: LPC32xx: defconfig update: Remove the museum NAND option

Barry Song (2):
      arm: prima2: add new SiRFatlas6 machine in common board
      ARM/dts: prima2: add .dtsi for atlas6 and .dts for atla6-evb board

Bastian Hecht (1):
      ARM: mach-shmobile: r8a7740: Add DT names to clock list

Charles Keepax (2):
      ARM: S3C64XX: Clear DMA flags on channel request
      ARM: S3C64XX: Slow down mic detection rate for wm5102

Christian Daudt (1):
      ARM: bcm281xx: Add timer driver (DT portion)

Daniel Lezcano (3):
      ARM: EXYNOS: factor out the idle states
      ARM: EXYNOS: handle properly the return values
      ARM: EXYNOS: replace cpumask by the corresponding macro

Danny Huang (2):
      ARM: tegra: expose chip ID and revision
      ARM: tegra: add speedo-based process id for Tegra114

Dinh Nguyen (3):
      ARM: socfpga: Enable soft reset
      ARM: socfpga: Add clock entries into device tree
      ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries

Fabio Estevam (4):
      ARM: mxs: Select ARM_CPU_SUSPEND
      ARM: mxs_defconfig: Build CONFIG_INPUT_EVDEV as built-in
      ARM: mxs_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
      ARM: mxs_defconfig: Select watchdog driver

Guennadi Liakhovetski (2):
      ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and r8a7740
      ARM: shmobile: sh73a0: fix Z and ZG clock hierarchy

Hongbo Zhang (1):
      ARM: ux500: enable ux500 EXT4_FS and LBDAF support by default

Inderpal Singh (2):
      ARM: EXYNOS: Add support for rtc wakeup
      ARM: SAMSUNG: check processor type before cache restoration in resume

Jonathan Kliegman (2):
      ARM: EXYNOS: Remove hardcode wakeup unmask for EINT_0
      ARM: EXYNOS: Clear ENABLE_WAKEUP_SW bit when entering suspend

Joseph Lo (9):
      ARM: tegra: bring up secondary CPU for Tegra114
      ARM: tegra: add clock source of PMC to device trees
      ARM: tegra: moving the CPU power timer function to PMC driver
      gpio: tegra: add gpio wakeup source handling
      ARM: tegra: irq: add wake up handling
      ARM: dt: tegra: add bindings of power management configurations for PMC
      ARM: tegra: pm: add platform suspend support
      ARM: tegra: cpuidle: remove redundant parameters for powered-down mode
      ARM: tegra: pm: fix build error w/o PM_SLEEP

Kuninori Morimoto (9):
      ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID
      ARM: shmobile: r8a7779: fixup dtsi typo
      ARM: shmobile: r8a7779: fixup DT machine name
      ARM: shmobile: r8a7779: use gic_iid macro
      ARM: shmobile: tidyup chip series definition order for r8a7740/r8a7779
      ARM: shmobile: r8a7779: add Thermal support on DT
      ARM: shmobile: armadillo800eva: enable branch prediction on defconfig
      ARM: shmobile: armadillo800eva: enable NEON on defconfig
      ARM: shmobile: armadillo800eva: enable all errata for cache on defconfig

Lee Jones (1):
      ARM: ux500: Turn on the 'heartbeat' LED trigger

Linus Walleij (1):
      ARM: ux500: bump arch nr of GPIOs

Ludovic Desroches (6):
      ARM: at91: change name template in AT91_SOC_START macro
      ARM: at91: add AT91_SAM9_TIME entry to select at91sam926x_time.c compilation
      ARM: at91: introduce the core type choice to split ARMv4/5 and ARMv7 arch
      ARM: at91: introduce SAMA5 support
      ARM: at91: dt: add device tree files for SAMA5D3 family
      ARM: at91: add defconfig for SAMA5

Magnus Damm (21):
      ARM: shmobile: Remove unused headers from hotplug.c
      ARM: shmobile: Remove partial CPU Hotplug from EMEV2
      ARM: shmobile: Move EMEV2 CPU boot vector setup code
      ARM: shmobile: Remove sh73a0_get_core_count()
      ARM: shmobile: Remove r8a7779_get_core_count()
      ARM: shmobile: Remove emev2_get_core_count()
      ARM: shmobile: Kill off sh73a0 scu_base_addr() function
      ARM: shmobile: Kill off r8a7779 scu_base_addr() function
      ARM: shmobile: Rework EMEV2 scu_base variable
      ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.S
      ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S
      ARM: shmobile: Update EMEV2 to use scu_power_mode()
      ARM: shmobile: Make EMEV2 setup functions static
      ARM: shmobile: Fix base address readout in headsmp-scu.S
      ARM: shmobile: Rework SH73A0_SCU_BASE IOMEM() usage
      ARM: shmobile: Use R8A7779_SCU_BASE with TWD
      ARM: shmobile: Update r8a7779 to check SCU for hotplug
      ARM: shmobile: Update r8a7779 to use scu_power_mode()
      ARM: shmobile: Use sh73a0-specific cpu disable code
      ARM: shmobile: Rearrange r8a7779 cpu hotplug code
      ARM: shmobile: Remove unused hotplug.c

Manjunathappa, Prakash (4):
      ARM: davinci: mmc: derive version information from device name
      mmc: davinci_mmc: add DT support
      ARM: davinci: da850: add mmc DT entries
      ARM: davinci: da850: override mmc DT node device name

Mark A. Greer (13):
      ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod
      ARM: OMAP2xxx: hwmod: Add DMA support for SHAM module
      ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod
      ARM: OMAP2+: Remove unnecessary message when no SHA IP is present
      ARM: OMAP2+: Only manually add hwmod data when DT not used.
      ARM: AM33XX: Add sha0 crypto clock data
      ARM: AM33XX: hwmod: Update and uncomment SHA0 module data
      ARM: OMAP2xxx: hwmod: Convert AES crypto devcie data to hwmod
      ARM: OMAP3xxx: hwmod: Convert AES crypto device data to hwmod
      ARM: OMAP2+: Remove unnecessary message when no AES IP is present
      ARM: OMAP2+: Only manually add hwmod data when DT not used.
      ARM: AM33XX: Add aes0 crypto clock data
      ARM: AM33XX: hwmod: Update and uncomment AES0 module data

Maxime Coquelin (1):
      ARM: mach-ux500: enable 128KB way L2 cache on DB8540

Olof Johansson (6):
      Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into next/soc
      Merge tag 'renesas-defconfig2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc
      Merge branch 'lpc32xx/defconfig' of git://git.antcom.de/linux-2.6 into next/soc
      Merge tag 'msm-core-3.10' of git://git.kernel.org/.../davidb/linux-msm into next/soc
      Merge tag 'davinci-for-v3.10/soc-2-v2' of git://git.kernel.org/.../nsekhar/linux-davinci into next/soc
      Merge branch 'gic/cleanup' into next/soc

Paul Bolle (1):
      ARM: davinci: remove test for undefined Kconfig macro

Phil Edworthy (1):
      r8a7779: Add Display Unit clock support

Philip Avinash (2):
      ARM: davinci: clk framework support for enable/disable functionality
      ARM: davinci: da850: add ECAP & EHRPWM clock nodes

Robert Tivy (1):
      ARM: davinci: da8xx: add remoteproc support

Roland Stigge (3):
      ARM: LPC32xx: defconfig update: gpio and keys
      ARM: LPC32xx: defconfig update: Default drivers and cleanup
      ARM: LPC32xx: defconfig update: Cleanup (EXPERIMENTAL)

Ruslan Bilovol (3):
      ARM: OMAP2+: Move common part of late init into common function
      ARM: OMAP2+: SoC name and revision unification
      ARM: OMAP2+: Export SoC information to userspace

Sekhar Nori (3):
      ARM: davinci: da8xx dt: make file local symbols static
      ARM: davinci: sram.c: fix incorrect type in assignment
      ARM: davinci: ensure global variables are declared

Sergei Shtylyov (1):
      ARM: shmobile: R8A7779: use gic_iid() in SATA IRQ resource

Simon Horman (17):
      ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by DT
      ARM: mach-shmobile: r8a7779: Minimal setup using DT
      ARM: shmobile: sh73a0: Remove sh73a0_init_irq_dt()
      ARM: shmobile: sh73a0: Add smp ops to DT_MACHINE_START
      ARM: shmobile: sh73a0: Remove warning about SMP
      ARM: shmobile: sh73a0: Do not use early devices with DT reference
      ARM: shmobile: r8a7779: Do not use early devices with DT reference
      ARM: shmobile: r8a7779: Do not initialise i2c as an early device
      ARM: shmobile: r8a7779: Remove lan from dtsi
      ARM: mach-shmobile: mackerel: enable MMCIF and SDHI in defconfig
      ARM: mach-shmobile: mackerel: enable REGULATOR in defconfig
      ARM: mach-shmobile: armadillo800eva: enable REGULATOR in defconfig
      ARM: shmobile: kzm9g: defconfig: do not enable PREEMPT
      ARM: mach-shmobile: kzm9g: do not enable REGULATOR_DUMMY in defconfig
      ARM: shmobile: marzen: defconfig: add GPIO RCAR driver support
      ARM: shmobile: marzen: defconfig: enable GPIO LEDs driver
      ARM: shmobile: ape6evm: add defconfig

Sricharan R (1):
      ARM: OMAP4: Enable fix for Cortex-A9 erratas

Stephen Boyd (2):
      ARM: msm: Rework timer binding to be more general
      ARM: msm: Wait for timer clear to complete

Stephen Warren (2):
      ARM: bcm2835: defconfig updates
      ARM: tegra: defconfig updates

Sylwester Nawrocki (1):
      ARM: SAMSUNG: Export MIPI CSIS/DSIM PHY control functions

Tony Lindgren (1):
      Merge tag 'omap-devel-a-for-3.10' of git://git.kernel.org/.../pjw/omap-pending into omap-for-v3.10/crypto

Vishwanathrao Badarkhe, Manish (2):
      ARM: regulator: add tps6507x device tree data
      ARM: davinci: da850: add tps6507x regulator DT data

Vladimir Barinov (3):
      ARM: mach-shmobile: r8a7779: SATA DT configuration
      ARM: mach-shmobile: r8a7779: add SATA support
      ARM: mach-shmobile: marzen: add SATA support

Wei Yongjun (1):
      ARM: tegra: pm: remove duplicated include from pm.c


 .../bindings/arm/altera/socfpga-clk-manager.txt |   11 +
 .../bindings/arm/bcm/bcm,kona-timer.txt         |   19 +
 .../devicetree/bindings/arm/msm/timer.txt       |   41 +-
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt   |   67 +-
 .../devicetree/bindings/clock/altr_socfpga.txt  |   18 +
 .../devicetree/bindings/mmc/davinci_mmc.txt     |   33 +
 Documentation/kernel-parameters.txt             |    6 +
 arch/arm/Kconfig                                |    3 +-
 arch/arm/boot/dts/Makefile                      |    5 +
 arch/arm/boot/dts/atlas6-evb.dts                |   78 ++
 arch/arm/boot/dts/atlas6.dtsi                   |  668 ++++++++++++
 arch/arm/boot/dts/bcm11351.dtsi                 |    8 +
 arch/arm/boot/dts/da850-evm.dts                 |   70 ++
 arch/arm/boot/dts/da850.dtsi                    |   15 +
 arch/arm/boot/dts/msm8660-surf.dts              |   20 +-
 arch/arm/boot/dts/msm8960-cdp.dts               |   22 +-
 arch/arm/boot/dts/r8a7779.dtsi                  |   98 ++
 arch/arm/boot/dts/sama5d3.dtsi                  | 1031 ++++++++++++++++++
 arch/arm/boot/dts/sama5d31ek.dts                |   51 +
 arch/arm/boot/dts/sama5d33ek.dts                |   44 +
 arch/arm/boot/dts/sama5d34ek.dts                |   61 ++
 arch/arm/boot/dts/sama5d35ek.dts                |   56 +
 arch/arm/boot/dts/sama5d3xcm.dtsi               |   91 ++
 arch/arm/boot/dts/sama5d3xdm.dtsi               |   42 +
 arch/arm/boot/dts/sama5d3xmb.dtsi               |  166 +++
 arch/arm/boot/dts/socfpga.dtsi                  |  157 +++
 arch/arm/boot/dts/socfpga_cyclone5.dts          |    8 +
 arch/arm/boot/dts/socfpga_vt.dts                |    8 +
 arch/arm/boot/dts/tegra114-dalmore.dts          |   13 +
 arch/arm/boot/dts/tegra114-pluto.dts            |   13 +
 arch/arm/boot/dts/tegra114.dtsi                 |    2 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi      |   13 +
 arch/arm/boot/dts/tegra20-harmony.dts           |   13 +
 arch/arm/boot/dts/tegra20-paz00.dts             |   13 +
 arch/arm/boot/dts/tegra20-seaboard.dts          |   13 +
 arch/arm/boot/dts/tegra20-tamonten.dtsi         |   13 +
 arch/arm/boot/dts/tegra20-trimslice.dts         |   13 +
 arch/arm/boot/dts/tegra20-ventana.dts           |   13 +
 arch/arm/boot/dts/tegra20-whistler.dts          |   13 +
 arch/arm/boot/dts/tegra20.dtsi                  |    2 +
 arch/arm/boot/dts/tegra30-beaver.dts            |   13 +
 arch/arm/boot/dts/tegra30-cardhu.dtsi           |   13 +
 arch/arm/boot/dts/tegra30.dtsi                  |    2 +
 arch/arm/boot/dts/tps6507x.dtsi                 |   47 +
 arch/arm/configs/ape6evm_defconfig              |   95 ++
 arch/arm/configs/armadillo800eva_defconfig      |    8 +-
 arch/arm/configs/bcm2835_defconfig              |    9 +-
 arch/arm/configs/kzm9g_defconfig                |    2 -
 arch/arm/configs/lpc32xx_defconfig              |   21 +-
 arch/arm/configs/mackerel_defconfig             |    4 +
 arch/arm/configs/marzen_defconfig               |    8 +
 arch/arm/configs/mxs_defconfig                  |    5 +-
 arch/arm/configs/sama5_defconfig                |  181 +++
 arch/arm/configs/tegra_defconfig                |   18 +-
 arch/arm/configs/u8500_defconfig                |    4 +-
 arch/arm/mach-at91/Kconfig                      |   59 +-
 arch/arm/mach-at91/Makefile                     |    7 +-
 arch/arm/mach-at91/at91rm9200.c                 |    2 +-
 arch/arm/mach-at91/at91sam9260.c                |    2 +-
 arch/arm/mach-at91/at91sam9261.c                |    2 +-
 arch/arm/mach-at91/at91sam9263.c                |    2 +-
 arch/arm/mach-at91/at91sam9g45.c                |    2 +-
 arch/arm/mach-at91/at91sam9n12.c                |    2 +-
 arch/arm/mach-at91/at91sam9rl.c                 |    2 +-
 arch/arm/mach-at91/at91sam9x5.c                 |    2 +-
 arch/arm/mach-at91/board-dt-sama5.c             |   86 ++
 arch/arm/mach-at91/clock.c                      |  109 +-
 arch/arm/mach-at91/clock.h                      |    2 +
 arch/arm/mach-at91/include/mach/at91_pmc.h      |   18 +-
 arch/arm/mach-at91/include/mach/cpu.h           |   20 +
 arch/arm/mach-at91/include/mach/sama5d3.h       |   73 ++
 arch/arm/mach-at91/sama5d3.c                    |  377 +++++++
 arch/arm/mach-at91/setup.c                      |   27 +
 arch/arm/mach-at91/soc.h                        |    7 +-
 arch/arm/mach-davinci/board-da830-evm.c         |    1 -
 arch/arm/mach-davinci/board-da850-evm.c         |    2 -
 arch/arm/mach-davinci/board-dm355-evm.c         |    1 -
 arch/arm/mach-davinci/board-dm365-evm.c         |    1 -
 arch/arm/mach-davinci/board-dm644x-evm.c        |    1 -
 arch/arm/mach-davinci/board-neuros-osd2.c       |    1 -
 arch/arm/mach-davinci/board-omapl138-hawk.c     |    1 -
 arch/arm/mach-davinci/board-tnetv107x-evm.c     |    1 -
 arch/arm/mach-davinci/clock.c                   |   21 +-
 arch/arm/mach-davinci/clock.h                   |    2 +
 arch/arm/mach-davinci/da830.c                   |    2 +-
 arch/arm/mach-davinci/da850.c                   |   50 +-
 arch/arm/mach-davinci/da8xx-dt.c                |    5 +-
 arch/arm/mach-davinci/devices-da8xx.c           |   92 +-
 arch/arm/mach-davinci/devices-tnetv107x.c       |    4 +-
 arch/arm/mach-davinci/devices.c                 |    6 +-
 arch/arm/mach-davinci/dm355.c                   |    4 +-
 arch/arm/mach-davinci/dm365.c                   |    4 +-
 arch/arm/mach-davinci/dm644x.c                  |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h      |    5 +
 .../arm/mach-davinci/include/mach/debug-macro.S |    2 -
 arch/arm/mach-davinci/pm.c                      |    1 +
 arch/arm/mach-davinci/sram.c                    |    4 +-
 arch/arm/mach-davinci/tnetv107x.c               |    4 +-
 arch/arm/mach-davinci/usb.c                     |    1 +
 arch/arm/mach-exynos/common.c                   |    2 +
 arch/arm/mach-exynos/cpuidle.c                  |   58 +-
 arch/arm/mach-exynos/include/mach/pm-core.h     |    9 +-
 arch/arm/mach-msm/timer.c                       |  110 +-
 arch/arm/mach-mxs/Kconfig                       |    2 +
 arch/arm/mach-omap2/Kconfig                     |    3 +
 arch/arm/mach-omap2/cclock2430_data.c           |    4 +-
 arch/arm/mach-omap2/cclock33xx_data.c           |   10 +
 arch/arm/mach-omap2/cclock3xxx_data.c           |    2 +
 arch/arm/mach-omap2/common.h                    |    8 +
 arch/arm/mach-omap2/devices.c                   |  149 +--
 arch/arm/mach-omap2/id.c                        |   95 +-
 arch/arm/mach-omap2/io.c                        |   34 +-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c      |    2 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c      |    2 +
 .../omap_hwmod_2xxx_interconnect_data.c         |   36 +
 .../mach-omap2/omap_hwmod_2xxx_ipblock_data.c   |   81 ++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c      |   92 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c      |  172 ++-
 arch/arm/mach-omap2/omap_hwmod_common_data.h    |    4 +
 arch/arm/mach-prima2/Kconfig                    |   10 +-
 arch/arm/mach-prima2/common.c                   |   21 +
 arch/arm/mach-s3c64xx/dma.c                     |    1 +
 arch/arm/mach-s3c64xx/mach-crag6410-module.c    |    1 +
 arch/arm/mach-shmobile/Makefile                 |    7 +-
 arch/arm/mach-shmobile/clock-r8a7740.c          |   13 +
 arch/arm/mach-shmobile/clock-r8a7779.c          |    8 +-
 arch/arm/mach-shmobile/clock-sh73a0.c           |    7 +-
 .../{headsmp-sh73a0.S => headsmp-scu.S}         |   15 +-
 arch/arm/mach-shmobile/hotplug.c                |   68 --
 arch/arm/mach-shmobile/include/mach/common.h    |   21 +-
 arch/arm/mach-shmobile/include/mach/irqs.h      |    1 +
 arch/arm/mach-shmobile/intc-r8a7779.c           |   27 +-
 arch/arm/mach-shmobile/intc-sh73a0.c            |    8 -
 arch/arm/mach-shmobile/setup-emev2.c            |    4 +-
 arch/arm/mach-shmobile/setup-r8a7779.c          |  104 +-
 arch/arm/mach-shmobile/setup-sh73a0.c           |   36 +-
 arch/arm/mach-shmobile/smp-emev2.c              |   86 +-
 arch/arm/mach-shmobile/smp-r8a7779.c            |  129 ++-
 arch/arm/mach-shmobile/smp-sh73a0.c             |   36 +-
 arch/arm/mach-socfpga/core.h                    |   11 +
 arch/arm/mach-socfpga/platsmp.c                 |    3 -
 arch/arm/mach-socfpga/socfpga.c                 |   16 +-
 arch/arm/mach-tegra/Makefile                    |    1 +
 arch/arm/mach-tegra/common.c                    |    5 +-
 arch/arm/mach-tegra/cpuidle-tegra20.c           |    6 +-
 arch/arm/mach-tegra/cpuidle-tegra30.c           |    6 +-
 arch/arm/mach-tegra/fuse.c                      |    4 +
 arch/arm/mach-tegra/fuse.h                      |    7 +
 arch/arm/mach-tegra/irq.c                       |   96 +-
 arch/arm/mach-tegra/irq.h                       |    6 +
 arch/arm/mach-tegra/platsmp.c                   |    8 +
 arch/arm/mach-tegra/pm.c                        |  131 ++-
 arch/arm/mach-tegra/pm.h                        |   17 +-
 arch/arm/mach-tegra/pmc.c                       |  162 +++
 arch/arm/mach-tegra/pmc.h                       |   14 +
 arch/arm/mach-tegra/tegra.c                     |   29 +-
 arch/arm/mach-tegra/tegra114_speedo.c           |  104 ++
 arch/arm/mach-ux500/cache-l2x0.c                |    4 +-
 arch/arm/plat-samsung/s5p-sleep.S               |    9 +
 arch/arm/plat-samsung/setup-mipiphy.c           |    3 +
 drivers/clk/socfpga/clk.c                       |  163 ++-
 drivers/gpio/gpio-tegra.c                       |   21 +-
 drivers/mmc/host/davinci_mmc.c                  |   88 +-
 include/linux/platform_data/mmc-davinci.h       |    3 -
 164 files changed, 6029 insertions(+), 846 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt
 create mode 100644 Documentation/devicetree/bindings/clock/altr_socfpga.txt
 create mode 100644 Documentation/devicetree/bindings/mmc/davinci_mmc.txt
 create mode 100644 arch/arm/boot/dts/atlas6-evb.dts
 create mode 100644 arch/arm/boot/dts/atlas6.dtsi
 create mode 100644 arch/arm/boot/dts/r8a7779.dtsi
 create mode 100644 arch/arm/boot/dts/sama5d3.dtsi
 create mode 100644 arch/arm/boot/dts/sama5d31ek.dts
 create mode 100644 arch/arm/boot/dts/sama5d33ek.dts
 create mode 100644 arch/arm/boot/dts/sama5d34ek.dts
 create mode 100644 arch/arm/boot/dts/sama5d35ek.dts
 create mode 100644 arch/arm/boot/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/boot/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/boot/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/boot/dts/tps6507x.dtsi
 create mode 100644 arch/arm/configs/ape6evm_defconfig
 create mode 100644 arch/arm/configs/sama5_defconfig
 create mode 100644 arch/arm/mach-at91/board-dt-sama5.c
 create mode 100644 arch/arm/mach-at91/include/mach/sama5d3.h
 create mode 100644 arch/arm/mach-at91/sama5d3.c
 rename arch/arm/mach-shmobile/{headsmp-sh73a0.S => headsmp-scu.S} (85%)
 delete mode 100644 arch/arm/mach-shmobile/hotplug.c
 create mode 100644 arch/arm/mach-tegra/tegra114_speedo.c


From olof at lixom.net  Thu May  2 02:58:33 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed,  1 May 2013 23:58:33 -0700
Subject: [GIT PULL 2/5] ARM: arm-soc cleanup for 3.10
In-Reply-To: <1367477916-28399-1-git-send-email-olof@lixom.net>
References: <1367477916-28399-1-git-send-email-olof@lixom.net>
Message-ID: <1367477916-28399-3-git-send-email-olof@lixom.net>

Here is a collection of cleanup patches. Among the pieces that stand out are:

- The deletion of h720x platforms
- Split of at91 non-dt platforms to their own Kconfig file to keep them separate
- General cleanups and refactoring of i.MX and MXS platforms
- Some restructuring of clock tables for OMAP
- Convertion of PMC driver for Tegra to dt-only
- Some renames of sunxi -> sun4i (Allwinner A10)
- ... plus a bunch of other stuff that I haven't mentioned


Conflicts:

arch/arm/Kconfig: remove/remove conflict. Both sides should be
removed. There seems to be some dangling use of the SA11x0 options in
cpufreq that should be removed though (separate issue).

drivers/gpio/gpio-pl061.c: Add/add conflict, keep both

drivers/usb/host/ohci-exynos.c: Change/remove. Take out the newline
and the plat/* include.

arch/arm/mach-imx/cpufreq.c: Remove/remove conflict. Drop the file.

----------------------------------------------------------------

The following changes since commit 300aff2eea4843557709f479a2efa753aa53caf5:

  Merge branch 'next/fixes-non-critical' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/cleanup-for-linus

for you to fetch changes up to afcf7924ecab726dab0227188783c4a40d9f0eec:

  Merge branch 'fixes' into next/cleanup

----------------------------------------------------------------

Alexander Shiyan (3):
      ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards
      ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410
      ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412

Arnd Bergmann (18):
      ARM: gemini: get platform to build again
      Merge branch 'next/cleanup-s3c' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge branch 'next/cleanup-s5p' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge tag 'clksrc-cleanup-for-3.10' of git://sources.calxeda.com/kernel/linux into next/cleanup
      Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into next/cleanup
      Merge tag 'cleanup_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/cleanup
      ARM: l7200: remove zombie file
      ARM: kill Hynix h720x platform
      clocksource: make CLOCKSOURCE_OF_DECLARE type safe
      Merge tag 'omap-for-v3.10/cleanup-v2-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge tag 'omap-for-v3.10/fixes-pm-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'tegra/fixes' into next/cleanup
      Merge tag 'tegra-for-3.10-cleanup' of git://git.kernel.org/.../swarren/linux-tegra into next/cleanup
      Merge tag 'v3.9-rc5' into next/cleanup
      Merge tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup
      Merge tag 'cleanup-samsung-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
      Merge branch 'next/spring-cleaning' into next/cleanup

Catalin Marinas (4):
      arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
      arm: Move chained_irq_(enter|exit) to a generic file
      irqchip: gic: Call handle_bad_irq() directly
      irqchip: gic: Perform the gic_secondary_init() call via CPU notifier

Fabio Estevam (3):
      ARM: imx: avic: Move avic_saved_mask_reg under CONFIG_PM
      ARM: imx: clk-imx27: Do not register peripheral clock for SSI
      clocksource: mxs_timer: Add semicolon at end of line

Heiko Stuebner (3):
      ARM: S3C24XX: remove plat/irq.h in plat-samsung
      ARM: S3C24XX: move plat-samsung/s3c24XX headers to local common.h
      ARM: S3C24XX: cleanup the included soc init functions in common.h

Hiroshi Doyu (4):
      ARM: tegra: Unify tegra{20,30,114}_init_early()
      ARM: tegra: Rename board-dt-tegra20.c to tegra.c
      ARM: tegra: Unify Device tree board files
      ARM: tegra: refactor tegra{20,30}_boot_secondary

J Keerthy (1):
      ARM: OMAP2+: clock data: Remove CK_* flags

Jarkko Nikula (2):
      ARM: OMAP1: Remove unused DMA channel definitions
      ARM: OMAP2+: Remove unused DMA channel definitions

Jean-Christophe PLAGNIOL-VILLARD (3):
      ARM: at91: move non DT Kconfig to Kconfig.non_dt
      ARM: at91: rename board-dt to more specific name board-dt-sam9
      ARM: at91: renamme rm9200 dt file

Jingoo Han (1):
      ARM: EXYNOS: change the name of USB ohci header

Johan Hovold (2):
      ARM: at91/setup: fix trivial typos
      ARM: at91: remove trailing semicolon from macros

Joseph Lo (5):
      ARM: tegra: pmc: add specific compatible DT string for Tegra30 and Tegra114
      ARM: tegra: fix the PMC compatible string in DT
      ARM: tegra: pmc: convert PMC driver to support DT only
      ARM: tegra: pmc: add power on function for secondary CPUs
      ARM: tegra: replace the CPU power on function with PMC call

Kukjin Kim (4):
      mmc: s3cmci: moved mach/regs-sdi.h into s3cmci device driver
      ARM: S3C24XX: plat/common-smdk.h local
      ARM: S5PC100: remove useless ifdef in common.h
      ARM: S5PV210: remove useless ifdef in common.h

Markus Pargmann (1):
      ARM: imx: Remove cpufreq driver

Maxime Ripard (10):
      ARM: at91: Fix typo in restart code panic message
      ARM: irq: Call irqchip_init if no init_irq function is specified
      Merge remote-tracking branch 'arm-soc/clksrc/cleanup' into sunxi/core-for-3.10
      Merge remote-tracking branch 'clk/clk-for-3.10' into sunxi/core-for-3.10
      clocksource: sunxi: Cleanup the timer code
      clocksource: sunxi: make use of CLKSRC_OF
      clocksource: sunxi: Rename sunxi to sun4i
      irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
      irqchip: sunxi: Rename sunxi to sun4i
      ARM: sunxi: Rework the restart code

Nicolas Ferre (1):
      ARM: at91: remove unused dbgu_readl() macro

Olof Johansson (9):
      Merge branch 'gic' of git://git.kernel.org/.../cmarinas/linux-aarch64 into next/cleanup
      Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
      irqchip: vic: add include of linux/irq.h
      Merge branch 'gic/cleanup' into next/cleanup
      Merge tag 'imx-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup
      Merge branch 'depends/clk-for-3.10' into next/cleanup
      Merge tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux into next/cleanup
      Merge tag 'msm-cleanup-3.10' of git://git.kernel.org/.../davidb/linux-msm into next/cleanup
      Merge branch 'fixes' into next/cleanup

Padmavathi Venna (1):
      ARM: SAMSUNG: Remove unnecessary code for dma

Paul Bolle (12):
      ARM: S3C24XX: drop "select MACH_N35"
      ARM: S3C24XX: drop "select MACH_NEO1973"
      ARM: EXYNOS: drop "select HAVE_SCHED_CLOCK"
      ARM: EXYNOS: change HAVE_SAMSUNG_KEYPAD to KEYBOARD_SAMSUNG
      ARM: SAMSUNG: remove "config S3C_BOOT_WATCHDOG"
      ARM: SAMSUNG: Remove useless Samsung GPIO related CONFIG
      ARM: S3C24XX: remove unneeded "config SMDK2440_CPU2442"
      ARM: S3C64XX: remove obsolete Makefile line
      ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI"
      ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC"
      ARM: EXYNOS: remove "config EXYNOS_DEV_DRM"
      ARM: i.MX: remove unused ARCH_* configs

Peter De Schrijver (1):
      clocksource: tegra: move to of_clk_get

Rob Herring (4):
      clocksource: add empty version of clocksource_of_init
      clocksource: pass DT node pointer to init functions
      clocksource: tegra20: use the device_node pointer passed to init
      ARM: smp_twd: convert to use CLKSRC_OF init

Sachin Kamat (1):
      irqchip: irq-gic: Fix checkpatch errors

Santosh Shilimkar (9):
      ARM: OMAP2+: PM: Remove bogus fiq_[enable/disable] tuple
      ARM: OMAP4+: Remove the un-necessary cache flush from hotplug code
      ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot path
      ARM: OMAP4+: Remove out of placed smp_wmb() in secondary wakeup code
      ARM: OMAP4+: Move the CPU wakeup prepare code under smp_prepare_cpus()
      ARM: OMAP4: PM: Remove L4 wakeup depedency with MPU since errata fix exist now
      ARM: OMAP4: PM: Now remove L4 per clockdomain static depedency with MPU
      ARM: OMAP4: Fix the init code to have OMAP4460 errata available in DT build
      ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method

Sascha Hauer (1):
      ARM i.MX53: remove platform ahci support

Shawn Guo (30):
      ARM: imx: remove duplicated function declaration
      ARM: imx: remove pl310_get_save_ptr() declaration
      Merge remote-tracking branch 'arm-soc/clksrc/cleanup' into mxs/cleanup
      ARM: mxs: use CLKSRC_OF helper to initialize timer
      ARM: mxs: look up timrot clock from device tree
      ARM: mxs: get timrot base address from device tree
      ARM: mxs: remove cpu_is_mx23() call from timer code
      ARM: mxs: select STMP_DEVICE and use it for timer code
      ARM: mxs: move timer driver into drivers/clocksource
      ARM: mxs: get icoll base address from device tree
      ARM: mxs: call stmp_reset_block() in icoll
      ARM: mxs: move icoll driver into drivers/irqchip
      ARM: mxs: remove unneeded mach-types.h inclusion
      clk: mxs: get base address from device tree
      clk: mxs: remove the use of mach level IO accessor
      rtc: stmp3xxx: use stmp_reset_block() instead
      iio: mxs-lradc: remove unneeded mach header inclusion
      ASoC: mxs-saif: remove mach header inclusion
      ARM: mxs: remove empty hardware.h
      ARM: mxs: get reset address from device tree
      ARM: mxs: remove system.c
      ARM: mxs: get ocotp base address from device tree
      ARM: mxs: use debug_ll_io_init for low-level debug
      ARM: mxs: remove mm.c
      ARM: mxs: move mxs_get_ocotp() into mach-mxs.c
      ARM: mxs: remove common.h
      ARM: mxs: merge imx23 and imx28 into one machine_desc
      ARM: mxs: remove unused headers
      ARM: imx: remove Makefile.boot
      ARM: imx: remove mx6q.h

Stephen Boyd (4):
      ARM: msm: Move dma.h #defines that are private to dma.c
      mmc: msm_sdcc: Remove unnecessary include
      gpio: Make gpio-msm-v1 into a platform driver
      ARM: msm: Remove unused cpu.h header file

Sylwester Nawrocki (1):
      ARM: S3C24XX: Remove unused GPIO drive strength register definitions

Tero Kristo (1):
      ARM: OMAP4+: Use common scratchpad SAR RAM offsets for all architectures

Thomas Petazzoni (3):
      arm: plat-orion: only build addr-map.c when needed
      arm: plat-orion: use mv_mbus_dram_info() in PCIe code
      arm: mach-orion5x: use mv_mbus_dram_info() in PCI code

Tony Lindgren (3):
      Merge tag 'omap-cleanup-a-for-3.10' of git://git.kernel.org/.../pjw/omap-pending into omap-for-v3.10/cleanup
      Merge branch 'for_3.10/omap_generic_cleanup_v2' of git://git.kernel.org/.../ssantosh/linux into omap-for-v3.10/cleanup-v2
      Merge tag 'omap-pm-v3.10/fixes/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into omap-for-v3.10/fixes-pm

Wei Yongjun (1):
      ARM: EXYNOS: remove duplicated include from common.c

Will Deacon (1):
      ARM: tegra: use setup_mm_for_reboot rather than explicit pgd switch


 ...nner,sunxi-ic.txt => allwinner,sun4i-ic.txt} |   4 +-
 ...unxi-timer.txt => allwinner,sun4i-timer.txt} |   4 +-
 .../watchdog/{sunxi-wdt.txt => sun4i-wdt.txt}   |   6 +-
 arch/arm/Kconfig                                |  22 +-
 arch/arm/Makefile                               |   1 -
 arch/arm/boot/dts/imx23.dtsi                    |   5 +-
 arch/arm/boot/dts/imx28.dtsi                    |   5 +-
 arch/arm/boot/dts/tegra114.dtsi                 |   2 +-
 arch/arm/boot/dts/tegra20.dtsi                  |   2 +
 arch/arm/boot/dts/tegra30.dtsi                  |   4 +-
 arch/arm/configs/at91_dt_defconfig              |   2 +-
 arch/arm/configs/at91sam9260_defconfig          |   2 +-
 arch/arm/configs/at91sam9g20_defconfig          |   2 +-
 arch/arm/configs/at91sam9g45_defconfig          |   2 +-
 arch/arm/configs/h7201_defconfig                |  27 -
 arch/arm/configs/h7202_defconfig                |  47 --
 arch/arm/include/asm/irq.h                      |   5 +
 arch/arm/include/asm/mach/irq.h                 |  36 -
 arch/arm/include/asm/smp_twd.h                  |   8 -
 arch/arm/kernel/irq.c                           |   6 +-
 arch/arm/kernel/smp_twd.c                       |  17 +-
 arch/arm/mach-at91/Kconfig                      | 398 +----------
 arch/arm/mach-at91/Kconfig.non_dt               | 399 +++++++++++
 arch/arm/mach-at91/Makefile                     |   4 +-
 arch/arm/mach-at91/at91_rstc.h                  |   2 +-
 arch/arm/mach-at91/at91_shdwc.h                 |   2 +-
 arch/arm/mach-at91/at91x40_time.c               |   2 +-
 .../{board-rm9200-dt.c => board-dt-rm9200.c}    |   0
 .../mach-at91/{board-dt.c => board-dt-sam9.c}   |   0
 arch/arm/mach-at91/gpio.c                       |   3 +-
 arch/arm/mach-at91/include/mach/at91_dbgu.h     |   3 -
 arch/arm/mach-at91/include/mach/at91_matrix.h   |   2 +-
 arch/arm/mach-at91/include/mach/at91_st.h       |   2 +-
 arch/arm/mach-at91/setup.c                      |   8 +-
 arch/arm/mach-exynos/Kconfig                    |  13 +-
 arch/arm/mach-exynos/common.c                   |   2 +-
 arch/arm/mach-exynos/dev-ohci.c                 |   2 +-
 arch/arm/mach-exynos/mach-origen.c              |   2 +-
 arch/arm/mach-exynos/mach-smdkv310.c            |   2 +-
 arch/arm/mach-exynos/platsmp.c                  |   8 -
 arch/arm/mach-gemini/Makefile                   |   2 +-
 arch/arm/mach-gemini/board-nas4220b.c           |   1 +
 arch/arm/mach-gemini/board-rut1xx.c             |   2 +
 arch/arm/mach-gemini/board-wbd111.c             |   1 +
 arch/arm/mach-gemini/board-wbd222.c             |   1 +
 arch/arm/mach-gemini/common.h                   |   2 +
 arch/arm/mach-gemini/gpio.c                     |  19 +-
 arch/arm/mach-gemini/include/mach/hardware.h    |   2 +-
 arch/arm/mach-gemini/irq.c                      |   4 +-
 arch/arm/mach-gemini/mm.c                       |  22 +-
 .../{include/mach/system.h => reset.c}          |   2 +-
 arch/arm/mach-h720x/Kconfig                     |  40 --
 arch/arm/mach-h720x/Makefile                    |  16 -
 arch/arm/mach-h720x/Makefile.boot               |   2 -
 arch/arm/mach-h720x/common.c                    | 268 --------
 arch/arm/mach-h720x/common.h                    |  30 -
 arch/arm/mach-h720x/cpu-h7201.c                 |  57 --
 arch/arm/mach-h720x/cpu-h7202.c                 | 225 ------
 arch/arm/mach-h720x/h7201-eval.c                |  38 -
 arch/arm/mach-h720x/h7202-eval.c                |  81 ---
 arch/arm/mach-h720x/include/mach/boards.h       |  53 --
 arch/arm/mach-h720x/include/mach/debug-macro.S  |  40 --
 arch/arm/mach-h720x/include/mach/entry-macro.S  |  57 --
 arch/arm/mach-h720x/include/mach/h7201-regs.h   |  67 --
 arch/arm/mach-h720x/include/mach/h7202-regs.h   | 155 -----
 arch/arm/mach-h720x/include/mach/hardware.h     | 190 -----
 arch/arm/mach-h720x/include/mach/irqs.h         | 116 ----
 arch/arm/mach-h720x/include/mach/isa-dma.h      |  19 -
 arch/arm/mach-h720x/include/mach/uncompress.h   |  36 -
 arch/arm/mach-highbank/highbank.c               |   5 +-
 arch/arm/mach-highbank/platsmp.c                |   7 -
 arch/arm/mach-imx/Kconfig                       |  18 -
 arch/arm/mach-imx/Makefile                      |   3 +-
 arch/arm/mach-imx/Makefile.boot                 |  35 -
 arch/arm/mach-imx/avic.c                        |   4 +-
 arch/arm/mach-imx/clk-imx27.c                   |   2 -
 arch/arm/mach-imx/common.h                      |   3 -
 arch/arm/mach-imx/cpu_op-mx51.c                 |  31 -
 arch/arm/mach-imx/cpu_op-mx51.h                 |  14 -
 arch/arm/mach-imx/cpufreq.c                     | 202 ------
 arch/arm/mach-imx/devices/Kconfig               |   4 -
 arch/arm/mach-imx/devices/Makefile              |   1 -
 arch/arm/mach-imx/devices/devices-common.h      |  10 -
 arch/arm/mach-imx/devices/platform-ahci-imx.c   | 157 -----
 arch/arm/mach-imx/hardware.h                    |   1 -
 arch/arm/mach-imx/mach-cpuimx51sd.c             |   5 -
 arch/arm/mach-imx/mach-imx6q.c                  |   5 +-
 arch/arm/mach-imx/mach-mx51_babbage.c           |   4 -
 arch/arm/mach-imx/mx6q.h                        |  31 -
 arch/arm/mach-imx/platsmp.c                     |  12 -
 arch/arm/mach-l7200/include/mach/debug-macro.S  |  38 -
 arch/arm/mach-msm/board-halibut.c               |   1 +
 arch/arm/mach-msm/board-msm7x30.c               |   1 +
 arch/arm/mach-msm/board-qsd8x50.c               |   1 +
 arch/arm/mach-msm/board-trout.c                 |   1 +
 arch/arm/mach-msm/devices-msm7x00.c             |  31 +
 arch/arm/mach-msm/devices-msm7x30.c             |  31 +
 arch/arm/mach-msm/devices-qsd8x50.c             |  31 +
 arch/arm/mach-msm/devices.h                     |   4 +
 arch/arm/mach-msm/dma.c                         |  26 +
 arch/arm/mach-msm/include/mach/cpu.h            |  54 --
 arch/arm/mach-msm/include/mach/dma.h            |  26 -
 arch/arm/mach-msm/platsmp.c                     |   8 -
 arch/arm/mach-mxs/Makefile                      |   4 -
 arch/arm/mach-mxs/include/mach/common.h         |  29 -
 arch/arm/mach-mxs/include/mach/debug-macro.S    |   9 +-
 arch/arm/mach-mxs/include/mach/digctl.h         |  22 -
 arch/arm/mach-mxs/include/mach/hardware.h       |  23 -
 arch/arm/mach-mxs/include/mach/mx23.h           | 169 -----
 arch/arm/mach-mxs/include/mach/mx28.h           | 225 ------
 arch/arm/mach-mxs/include/mach/mxs.h            | 117 ----
 arch/arm/mach-mxs/mach-mxs.c                    | 185 ++++-
 arch/arm/mach-mxs/mm.c                          |  52 --
 arch/arm/mach-mxs/ocotp.c                       |  93 ---
 arch/arm/mach-mxs/system.c                      | 139 ----
 arch/arm/mach-omap1/dma.h                       |  41 --
 arch/arm/mach-omap2/cclock2420_data.c           | 283 ++++----
 arch/arm/mach-omap2/cclock2430_data.c           | 311 ++++-----
 arch/arm/mach-omap2/cclock33xx_data.c           | 165 +++--
 arch/arm/mach-omap2/cclock3xxx_data.c           | 685 ++++++++++---------
 arch/arm/mach-omap2/cclock44xx_data.c           | 517 +++++++-------
 arch/arm/mach-omap2/clock.c                     |  17 +-
 arch/arm/mach-omap2/clock.h                     |  20 +-
 arch/arm/mach-omap2/cpuidle34xx.c               |   3 -
 arch/arm/mach-omap2/cpuidle44xx.c               |   8 +-
 arch/arm/mach-omap2/dma.h                       |  70 --
 arch/arm/mach-omap2/omap-hotplug.c              |   6 -
 arch/arm/mach-omap2/omap-smp.c                  |  76 +-
 arch/arm/mach-omap2/omap4-common.c              |  16 +
 arch/arm/mach-omap2/omap4-sar-layout.h          |  14 +-
 arch/arm/mach-omap2/pm24xx.c                    |  11 +-
 arch/arm/mach-omap2/pm34xx.c                    |   9 +-
 arch/arm/mach-omap2/pm44xx.c                    |  20 +-
 arch/arm/mach-omap2/timer.c                     |   2 +-
 arch/arm/mach-orion5x/pci.c                     |   7 +-
 arch/arm/mach-prima2/platsmp.c                  |   8 -
 arch/arm/mach-s3c24xx/Kconfig                   |  22 +-
 arch/arm/mach-s3c24xx/bast-irq.c                |   2 -
 arch/arm/mach-s3c24xx/clock-s3c2410.c           |   1 -
 arch/arm/mach-s3c24xx/clock-s3c2412.c           |   1 -
 arch/arm/mach-s3c24xx/clock-s3c2416.c           |   1 -
 arch/arm/mach-s3c24xx/clock-s3c2443.c           |   1 -
 arch/arm/mach-s3c24xx/common-smdk.c             |   3 +-
 .../include/plat => mach-s3c24xx}/common-smdk.h |   3 +-
 arch/arm/mach-s3c24xx/common.c                  |   7 +-
 arch/arm/mach-s3c24xx/common.h                  |  90 ++-
 arch/arm/mach-s3c24xx/dma-s3c2410.c             |   1 -
 arch/arm/mach-s3c24xx/dma-s3c2412.c             |   1 -
 arch/arm/mach-s3c24xx/dma-s3c2440.c             |   1 -
 arch/arm/mach-s3c24xx/dma-s3c2443.c             |   1 -
 arch/arm/mach-s3c24xx/include/mach/dma.h        |   1 -
 arch/arm/mach-s3c24xx/include/mach/regs-sdi.h   | 127 ----
 arch/arm/mach-s3c24xx/irq-pm.c                  |   7 +-
 arch/arm/mach-s3c24xx/irq.c                     |   9 +-
 arch/arm/mach-s3c24xx/mach-jive.c               |   2 +-
 arch/arm/mach-s3c24xx/mach-n30.c                |   1 -
 arch/arm/mach-s3c24xx/mach-nexcoder.c           |   2 -
 arch/arm/mach-s3c24xx/mach-otom.c               |   1 -
 arch/arm/mach-s3c24xx/mach-qt2410.c             |   2 +-
 arch/arm/mach-s3c24xx/mach-smdk2410.c           |   3 +-
 arch/arm/mach-s3c24xx/mach-smdk2413.c           |   5 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c           |   4 +-
 arch/arm/mach-s3c24xx/mach-smdk2440.c           |   5 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c           |   5 +-
 arch/arm/mach-s3c24xx/mach-vstms.c              |   3 +-
 arch/arm/mach-s3c24xx/pm-s3c2412.c              |   1 -
 arch/arm/mach-s3c24xx/regs-dsc.h                | 203 +-----
 arch/arm/mach-s3c24xx/s3c2410.c                 |   1 -
 arch/arm/mach-s3c24xx/s3c2412.c                 |   1 -
 arch/arm/mach-s3c24xx/s3c2416.c                 |   1 -
 arch/arm/mach-s3c24xx/s3c2440.c                 |   1 -
 arch/arm/mach-s3c24xx/s3c2442.c                 |   1 -
 arch/arm/mach-s3c24xx/s3c2443.c                 |   1 -
 arch/arm/mach-s3c24xx/s3c244x.c                 |   2 -
 arch/arm/mach-s3c64xx/Makefile                  |   1 -
 arch/arm/mach-s3c64xx/include/mach/dma.h        |   1 -
 arch/arm/mach-s5pc100/common.h                  |   9 -
 arch/arm/mach-s5pv210/common.h                  |   9 -
 arch/arm/mach-shmobile/smp-emev2.c              |   7 -
 arch/arm/mach-shmobile/smp-r8a7779.c            |   7 -
 arch/arm/mach-shmobile/smp-sh73a0.c             |   7 -
 arch/arm/mach-socfpga/platsmp.c                 |  12 -
 arch/arm/mach-spear13xx/platsmp.c               |   8 -
 arch/arm/mach-spear13xx/spear13xx.c             |   4 +-
 arch/arm/mach-sunxi/Kconfig                     |   5 +-
 arch/arm/mach-sunxi/sunxi.c                     |  74 +-
 arch/arm/mach-tegra/Makefile                    |   4 +-
 arch/arm/mach-tegra/board-dt-tegra114.c         |  46 --
 arch/arm/mach-tegra/board-dt-tegra30.c          |  60 --
 arch/arm/mach-tegra/board.h                     |   4 +-
 arch/arm/mach-tegra/common.c                    |  26 +-
 arch/arm/mach-tegra/hotplug.c                   |  23 +-
 arch/arm/mach-tegra/platsmp.c                   | 118 ++--
 arch/arm/mach-tegra/pm.c                        |   7 +-
 arch/arm/mach-tegra/pmc.c                       | 152 +++-
 arch/arm/mach-tegra/pmc.h                       |   4 +
 arch/arm/mach-tegra/sleep.h                     |  10 +-
 .../mach-tegra/{board-dt-tegra20.c => tegra.c}  |  16 +-
 arch/arm/mach-ux500/platsmp.c                   |   8 -
 arch/arm/mach-ux500/timer.c                     |   3 +-
 arch/arm/mach-vexpress/v2m.c                    |   6 +-
 arch/arm/mach-virt/platsmp.c                    |   8 -
 arch/arm/plat-orion/Makefile                    |   6 +-
 arch/arm/plat-orion/pcie.c                      |  10 +-
 arch/arm/plat-samsung/Kconfig                   |  14 -
 arch/arm/plat-samsung/dma-ops.c                 |  10 +-
 arch/arm/plat-samsung/include/plat/dma-ops.h    |   1 -
 arch/arm/plat-samsung/include/plat/dma-pl330.h  |   1 -
 arch/arm/plat-samsung/include/plat/irq.h        | 116 ----
 arch/arm/plat-samsung/include/plat/rtc-core.h   |   2 +-
 arch/arm/plat-samsung/include/plat/s3c2410.h    |  31 -
 arch/arm/plat-samsung/include/plat/s3c2412.h    |  32 -
 arch/arm/plat-samsung/include/plat/s3c2416.h    |  37 -
 arch/arm/plat-samsung/include/plat/s3c2443.h    |  36 -
 arch/arm/plat-samsung/include/plat/s3c244x.h    |  42 --
 arch/arm/plat-samsung/include/plat/sdhci.h      |   4 +-
 arch/arm/plat-samsung/irq-vic-timer.c           |   3 +-
 arch/arm/plat-samsung/s5p-irq-gpioint.c         |   3 +-
 arch/arm/plat-versatile/platsmp.c               |   8 -
 drivers/clk/mxs/clk-imx23.c                     |  42 +-
 drivers/clk/mxs/clk-imx28.c                     |  42 +-
 drivers/clocksource/Kconfig                     |   2 +-
 drivers/clocksource/Makefile                    |   3 +-
 drivers/clocksource/bcm2835_timer.c             |  12 +-
 drivers/clocksource/clksrc-of.c                 |   5 +-
 .../timer.c => drivers/clocksource/mxs_timer.c  |  36 +-
 .../{sunxi_timer.c => sun4i_timer.c}            |  94 ++-
 drivers/clocksource/tegra20_timer.c             |  75 +-
 drivers/clocksource/vt8500_timer.c              |  16 +-
 drivers/gpio/gpio-msm-v1.c                      | 220 ++++--
 drivers/gpio/gpio-msm-v2.c                      |   3 +-
 drivers/gpio/gpio-mxc.c                         |   2 +-
 drivers/gpio/gpio-omap.c                        |   3 +-
 drivers/gpio/gpio-pl061.c                       |   2 +-
 drivers/gpio/gpio-pxa.c                         |   3 +-
 drivers/gpio/gpio-tegra.c                       |   3 +-
 drivers/irqchip/Makefile                        |   3 +-
 drivers/irqchip/exynos-combiner.c               |   1 +
 drivers/irqchip/irq-gic.c                       |  36 +-
 .../icoll.c => drivers/irqchip/irq-mxs.c        |  24 +-
 drivers/irqchip/irq-sun4i.c                     | 149 ++++
 drivers/irqchip/irq-sunxi.c                     | 151 ----
 drivers/irqchip/irq-vic.c                       |   3 +-
 drivers/mmc/host/msm_sdcc.c                     |   1 -
 drivers/mmc/host/s3cmci.c                       |  83 ++-
 drivers/pinctrl/pinctrl-at91.c                  |   3 +-
 drivers/pinctrl/pinctrl-exynos.c                |   3 +-
 drivers/pinctrl/pinctrl-nomadik.c               |   2 +-
 drivers/pinctrl/pinctrl-sirf.c                  |   2 +-
 drivers/pinctrl/spear/pinctrl-plgpio.c          |   2 +-
 drivers/rtc/rtc-stmp3xxx.c                      |   6 +-
 drivers/staging/iio/adc/mxs-lradc.c             |   3 -
 drivers/staging/imx-drm/ipu-v3/ipu-common.c     |   2 +-
 drivers/usb/host/ohci-exynos.c                  |   2 +-
 include/linux/clk/mxs.h                         |  16 +
 include/linux/clocksource.h                     |  12 +-
 include/linux/irqchip/arm-gic.h                 |   1 -
 include/linux/irqchip/chained_irq.h             |  52 ++
 .../mach/timex.h => include/linux/irqchip/mxs.h |   9 +-
 include/linux/irqchip/sunxi.h                   |  27 -
 .../{usb-exynos.h => usb-ohci-exynos.h}         |   0
 include/linux/sunxi_timer.h                     |  24 -
 sound/soc/mxs/mxs-saif.c                        |   5 +-
 263 files changed, 2919 insertions(+), 6559 deletions(-)
 rename Documentation/devicetree/bindings/interrupt-controller/{allwinner,sunxi-ic.txt => allwinner,sun4i-ic.txt} (94%)
 rename Documentation/devicetree/bindings/timer/{allwinner,sunxi-timer.txt => allwinner,sun4i-timer.txt} (78%)
 rename Documentation/devicetree/bindings/watchdog/{sunxi-wdt.txt => sun4i-wdt.txt} (57%)
 delete mode 100644 arch/arm/configs/h7201_defconfig
 delete mode 100644 arch/arm/configs/h7202_defconfig
 create mode 100644 arch/arm/mach-at91/Kconfig.non_dt
 rename arch/arm/mach-at91/{board-rm9200-dt.c => board-dt-rm9200.c} (100%)
 rename arch/arm/mach-at91/{board-dt.c => board-dt-sam9.c} (100%)
 rename arch/arm/mach-gemini/{include/mach/system.h => reset.c} (91%)
 delete mode 100644 arch/arm/mach-h720x/Kconfig
 delete mode 100644 arch/arm/mach-h720x/Makefile
 delete mode 100644 arch/arm/mach-h720x/Makefile.boot
 delete mode 100644 arch/arm/mach-h720x/common.c
 delete mode 100644 arch/arm/mach-h720x/common.h
 delete mode 100644 arch/arm/mach-h720x/cpu-h7201.c
 delete mode 100644 arch/arm/mach-h720x/cpu-h7202.c
 delete mode 100644 arch/arm/mach-h720x/h7201-eval.c
 delete mode 100644 arch/arm/mach-h720x/h7202-eval.c
 delete mode 100644 arch/arm/mach-h720x/include/mach/boards.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-h720x/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-h720x/include/mach/h7201-regs.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/h7202-regs.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/isa-dma.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-imx/Makefile.boot
 delete mode 100644 arch/arm/mach-imx/cpu_op-mx51.c
 delete mode 100644 arch/arm/mach-imx/cpu_op-mx51.h
 delete mode 100644 arch/arm/mach-imx/cpufreq.c
 delete mode 100644 arch/arm/mach-imx/devices/platform-ahci-imx.c
 delete mode 100644 arch/arm/mach-imx/mx6q.h
 delete mode 100644 arch/arm/mach-l7200/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-msm/include/mach/cpu.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/common.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/digctl.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mx23.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mx28.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mxs.h
 delete mode 100644 arch/arm/mach-mxs/mm.c
 delete mode 100644 arch/arm/mach-mxs/ocotp.c
 delete mode 100644 arch/arm/mach-mxs/system.c
 rename arch/arm/{plat-samsung/include/plat => mach-s3c24xx}/common-smdk.h (86%)
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
 delete mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c
 delete mode 100644 arch/arm/mach-tegra/board-dt-tegra30.c
 rename arch/arm/mach-tegra/{board-dt-tegra20.c => tegra.c} (89%)
 delete mode 100644 arch/arm/plat-samsung/include/plat/irq.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/s3c2410.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/s3c2412.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/s3c2416.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/s3c2443.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/s3c244x.h
 rename arch/arm/mach-mxs/timer.c => drivers/clocksource/mxs_timer.c (91%)
 rename drivers/clocksource/{sunxi_timer.c => sun4i_timer.c} (50%)
 rename arch/arm/mach-mxs/icoll.c => drivers/irqchip/irq-mxs.c (89%)
 create mode 100644 drivers/irqchip/irq-sun4i.c
 delete mode 100644 drivers/irqchip/irq-sunxi.c
 create mode 100644 include/linux/clk/mxs.h
 create mode 100644 include/linux/irqchip/chained_irq.h
 rename arch/arm/mach-h720x/include/mach/timex.h => include/linux/irqchip/mxs.h (52%)
 delete mode 100644 include/linux/irqchip/sunxi.h
 rename include/linux/platform_data/{usb-exynos.h => usb-ohci-exynos.h} (100%)
 delete mode 100644 include/linux/sunxi_timer.h


From olof at lixom.net  Thu May  2 02:58:36 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed,  1 May 2013 23:58:36 -0700
Subject: [GIT PULL 5/5] ARM: arm-soc multiplatform updates for 3.10
In-Reply-To: <1367477916-28399-1-git-send-email-olof@lixom.net>
References: <1367477916-28399-1-git-send-email-olof@lixom.net>
Message-ID: <1367477916-28399-6-git-send-email-olof@lixom.net>

More multiplatform enablement for ARM platforms. The ones converted in
this branch are:
- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500

We're getting close to having most of them converted!

One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was a
patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then.


Conflicts:

arch/arm/mach-ux500/cpuidle.c: Remove variables, keep comment indented
with tabs.

drivers/clocksource/Makefile: Add/change conflict. Keep SUN4I and
PRIMA2, ditch SUNXI.

----------------------------------------------------------------

The following changes since commit 00b4fd6087edf3b73cba84a6218ff9e68cf61359:

  Merge branch 'next/soc' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/multiplatform-for-linus

for you to fetch changes up to 2fdfe1c26fb9f24cfdf124384abb35396ca2cd3f:

  mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms

----------------------------------------------------------------

Arnd Bergmann (59):
      ARM: spear13xx: make mach/dma.h local
      ARM: spear: unify mach/generic.h and mach/irqs.h
      ARM: spear: move identical headers to plat-spear/include/mach
      ARM: spear: make spear3xx/6xx mach/spear.h files identical
      ARM: spear: merge Kconfig files
      ARM: spear: move spear.h and misc_regs.h into plat-spear
      ARM: spear: move all files to mach-spear
      ARM: spear: move generic.h and pl080.h into private dir
      ARM: spear: make clock driver independent of headers
      ARM: spear: rename duplicate pl080_plat_data
      ARM: spear: use multiplatform configuration options.
      ARM: spear: fix build error in restart.c
      ARM: spear: enable spear13xx in multi_v7_defconfig
      ARM: cns3xxx: make mach header files local
      ARM: cns3xxx: enable sparse IRQ support
      ARM: cns3xxx: move debug_ll code to include/debug/
      ARM: cns3xxx: enable multiplatform support
      ARM: cns3xxx: initial DT support
      Merge tag 'nomadik-multiplatform' of git://git.kernel.org/.../linusw/linux-nomadik into next/multiplatform
      Merge branch 'cns3xxx/multiplatform' into next/multiplatform
      Merge branch 'spear/multiplatform' into next/multiplatform
      ARM: nomadik: hide MACH_NOMADIK_8815NHK in Kconfig
      ARM: spear: build hotplug.o for armv7-a
      clocksource: make CLOCKSOURCE_OF_DECLARE type safe
      Merge branches 'prima2/soc' and 'clksrc/cleanup' into prima2/multiplatform
      pinctrl: sirf: convert to linear irq domain
      ARM: sirf: fix prima2 interrupt lookup
      ARM: sirf: move irq driver to drivers/irqchip
      ARM: sirf: enable sparse IRQ
      ARM: sirf: move debug-macro.S to include/debug/sirf.S
      ARM: sirf: use clocksource_of infrastructure
      ARM: sirf: enable multiplatform support
      ARM: sirf: enable support in multi_v7_defconfig
      Merge branch 'prima2/multiplatform' into next/multiplatform
      ARM: ux500: split out prcmu initialization
      ARM: ux500: move mach/msp.h to <linux/platform_data/*>
      staging: ste_rmi4: kill platform_data hack
      ARM: ux500: make irqs.h local to platform
      ARM: ux500: make remaining headers local
      ARM: ux500: move to multiplatform
      ARM: ux500: build hotplug.o for ARMv7-a
      Merge tag 'bcm2835-for-3.10-multiplatform' of git://git.kernel.org/.../swarren/linux-rpi into next/multiplatform
      Merge tag 'v3.9-rc3' into next/multiplatform
      Merge tag 'ux500-multiplatform-asoc' of git://git.kernel.org/.../linusw/linux-stericsson into next/multiplatform
      Merge branch 'mxs/cleanup' into next/multiplatform
      Merge tag 'mxs-multiplatform-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/multiplatform
      Merge branch 'tegra/soc' into next/multiplatform
      Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/.../swarren/linux-tegra into next/multiplatform
      ARM: tegra: build assembly files with -march=armv7-a
      ARM: exynos: introduce EXYNOS_ATAGS symbol
      ARM: exynos: prepare for sparse IRQ
      ARM: exynos: move debug-macro.S to include/debug/
      ARM: samsung: move mfc device definition to s5p-dev-mfc.c
      mmc: sdhci-s3c: remove platform dependencies
      thermal/exynos: remove unnecessary header inclusions
      mtd: onenand/samsung: make regs-onenand.h file local
      rtc: s3c: make header file local
      ARM: exynos: enable multiplatform support
      Merge branch 'samsung/exynos-multiplatform' into next/multiplatform

Linus Walleij (13):
      ARM: nomadik: delete IRQ header
      ARM: nomadik: move debugmacro to debug includes
      ARM: nomadik: convert to multiplatform
      ARM: nomadik: delete remnant include files
      mfd: prcmu: pass a base and size with the early initcall
      mfd: db8500-prcmu: get base address from resource
      ARM: ux500: move PM-related PRCMU functions to machine
      mfd: db8500-prcmu: drop unused includes
      ARM: ux500: move debugmacro to debug includes
      ARM: ux500: make debug macro stand-alone
      clk: ux500: pass clock base adresses in init call
      ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
      clocksource: nomadik-mtu: fix up clocksource/timer

Mark Brown (1):
      mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms

Olof Johansson (3):
      Revert "ARM: exynos: enable multiplatform support"
      Merge branch 'samsung/exynos-multiplatform' into next/multiplatform
      Merge branch 'clksrc/cleanup' into next/multiplatform

Paul Bolle (1):
      ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"

Shawn Guo (3):
      ARM: mxs: call mxs_pm_init() as a machine_desc hook
      ARM: mxs: rename debug-macro.S for multiplatform build
      ARM: mxs: enable multiplatform build

Stephen Boyd (1):
      ARM: Push selects for TWD/SCU into machine entries

Stephen Warren (3):
      ARM: bcm2835: convert to multi-platform
      ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>
      ARM: tegra: convert to multi-platform

Tony Prisk (1):
      arm: vt8500: Add wm8850 config options to multi_v7_defconfig


 arch/arm/Kconfig                                | 135 +-------
 arch/arm/Kconfig.debug                          |  39 +++
 arch/arm/Makefile                               |   5 +-
 arch/arm/configs/bcm2835_defconfig              |   2 +
 arch/arm/configs/cns3420vb_defconfig            |   3 +
 arch/arm/configs/multi_v7_defconfig             |  23 ++
 arch/arm/configs/mxs_defconfig                  |   2 +-
 arch/arm/configs/nhk8815_defconfig              |  42 ++-
 arch/arm/configs/spear3xx_defconfig             |   2 +
 arch/arm/configs/spear6xx_defconfig             |   1 +
 .../debug-macro.S => include/debug/bcm2835.S}   |   3 +-
 .../debug-macro.S => include/debug/cns3xxx.S}   |   0
 .../debug-macro.S => include/debug/exynos.S}    |  12 +-
 .../mach/debug-macro.S => include/debug/mxs.S}  |   0
 .../debug-macro.S => include/debug/nomadik.S}   |   0
 .../debug-macro.S => include/debug/samsung.S}   |   0
 .../mach/uart.h => include/debug/sirf.S}        |  29 +-
 arch/arm/include/debug/ux500.S                  |  48 +++
 arch/arm/mach-bcm2835/Kconfig                   |  15 +
 arch/arm/mach-bcm2835/Makefile.boot             |   1 -
 arch/arm/mach-bcm2835/bcm2835.c                 |   6 +-
 .../arm/mach-bcm2835/include/mach/bcm2835_soc.h |  29 --
 arch/arm/mach-bcm2835/include/mach/gpio.h       |   1 -
 arch/arm/mach-bcm2835/include/mach/timex.h      |  26 --
 arch/arm/mach-bcm2835/include/mach/uncompress.h |  44 ---
 arch/arm/mach-cns3xxx/Kconfig                   |  12 +
 arch/arm/mach-cns3xxx/Makefile                  |   8 +-
 arch/arm/mach-cns3xxx/cns3420vb.c               |   6 +-
 .../mach-cns3xxx/{include/mach => }/cns3xxx.h   |   7 +-
 arch/arm/mach-cns3xxx/core.c                    | 121 ++++++-
 arch/arm/mach-cns3xxx/devices.c                 |   5 +-
 arch/arm/mach-cns3xxx/include/mach/irqs.h       |  24 --
 arch/arm/mach-cns3xxx/include/mach/timex.h      |  12 -
 arch/arm/mach-cns3xxx/include/mach/uncompress.h |  53 ----
 arch/arm/mach-cns3xxx/pcie.c                    |   2 +-
 arch/arm/mach-cns3xxx/pm.c                      |   4 +-
 arch/arm/mach-cns3xxx/{include/mach => }/pm.h   |   0
 arch/arm/mach-exynos/Kconfig                    |  17 +
 arch/arm/mach-exynos/dev-uart.c                 |   1 +
 arch/arm/mach-exynos/include/mach/irqs.h        |   5 +-
 arch/arm/mach-exynos/mach-armlex4210.c          |   1 +
 arch/arm/mach-exynos/mach-nuri.c                |   1 +
 arch/arm/mach-exynos/mach-origen.c              |   1 +
 arch/arm/mach-exynos/mach-smdk4x12.c            |   1 +
 arch/arm/mach-exynos/mach-smdkv310.c            |   1 +
 arch/arm/mach-exynos/setup-sdhci-gpio.c         |   2 +-
 arch/arm/mach-highbank/Kconfig                  |   1 +
 arch/arm/mach-imx/Kconfig                       |   3 +-
 arch/arm/mach-msm/Kconfig                       |   7 +-
 arch/arm/mach-mxs/Kconfig                       |  22 +-
 arch/arm/mach-mxs/Makefile                      |   2 +-
 arch/arm/mach-mxs/Makefile.boot                 |   1 -
 arch/arm/mach-mxs/include/mach/timex.h          |  21 --
 arch/arm/mach-mxs/include/mach/uncompress.h     |  76 -----
 arch/arm/mach-mxs/mach-mxs.c                    |   3 +
 arch/arm/mach-mxs/pm.c                          |   4 +-
 arch/arm/mach-mxs/pm.h                          |  14 +
 arch/arm/mach-nomadik/Kconfig                   |  25 +-
 arch/arm/mach-nomadik/Makefile.boot             |   4 -
 arch/arm/mach-nomadik/cpu-8815.c                |   1 -
 arch/arm/mach-nomadik/include/mach/irqs.h       |  79 -----
 arch/arm/mach-nomadik/include/mach/timex.h      |   6 -
 arch/arm/mach-nomadik/include/mach/uncompress.h |  60 ----
 arch/arm/mach-omap2/Kconfig                     |   2 +
 arch/arm/mach-prima2/Kconfig                    |  13 +
 arch/arm/mach-prima2/Makefile                   |   5 +-
 arch/arm/mach-prima2/common.c                   |  26 +-
 arch/arm/mach-prima2/common.h                   |   4 +-
 arch/arm/mach-prima2/include/mach/clkdev.h      |  15 -
 arch/arm/mach-prima2/include/mach/debug-macro.S |  29 --
 arch/arm/mach-prima2/include/mach/entry-macro.S |  22 --
 arch/arm/mach-prima2/include/mach/hardware.h    |  15 -
 arch/arm/mach-prima2/include/mach/irqs.h        |  17 -
 arch/arm/mach-prima2/include/mach/map.h         |  18 --
 arch/arm/mach-prima2/include/mach/timex.h       |  14 -
 arch/arm/mach-prima2/include/mach/uncompress.h  |  41 ---
 arch/arm/mach-prima2/irq.c                      | 129 --------
 arch/arm/mach-prima2/lluart.c                   |  14 +-
 arch/arm/mach-prima2/platsmp.c                  |   1 -
 arch/arm/mach-realview/Kconfig                  |   8 +
 .../arm/mach-s3c24xx/include/mach/debug-macro.S |   2 +-
 .../arm/mach-s3c64xx/include/mach/debug-macro.S |   2 +-
 .../arm/mach-s5p64x0/include/mach/debug-macro.S |   2 +-
 .../arm/mach-s5pc100/include/mach/debug-macro.S |   2 +-
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c        |   1 -
 .../arm/mach-s5pv210/include/mach/debug-macro.S |   2 +-
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c        |   1 -
 arch/arm/mach-spear/Kconfig                     | 105 ++++++
 arch/arm/mach-spear/Makefile                    |  26 ++
 .../Makefile.boot                               |   0
 .../include/mach => mach-spear}/generic.h       |  30 +-
 .../{mach-spear13xx => mach-spear}/headsmp.S    |   0
 .../{mach-spear13xx => mach-spear}/hotplug.c    |   0
 .../include/mach}/debug-macro.S                 |   0
 .../include/mach/irqs.h                         |  22 +-
 .../include/mach/misc_regs.h                    |   2 +-
 arch/arm/mach-spear/include/mach/spear.h        |  95 ++++++
 .../plat => mach-spear/include/mach}/timex.h    |   0
 .../include/mach}/uncompress.h                  |   0
 arch/arm/{plat-spear => mach-spear}/pl080.c     |   0
 .../include/plat => mach-spear}/pl080.h         |   0
 .../{mach-spear13xx => mach-spear}/platsmp.c    |   2 +-
 arch/arm/{plat-spear => mach-spear}/restart.c   |   5 +-
 .../{mach-spear13xx => mach-spear}/spear1310.c  |   4 +-
 .../{mach-spear13xx => mach-spear}/spear1340.c  |   5 +-
 .../mach/dma.h => mach-spear/spear13xx-dma.h}   |   0
 .../{mach-spear13xx => mach-spear}/spear13xx.c  |   9 +-
 .../{mach-spear3xx => mach-spear}/spear300.c    |   4 +-
 .../{mach-spear3xx => mach-spear}/spear310.c    |   4 +-
 .../{mach-spear3xx => mach-spear}/spear320.c    |   7 +-
 .../{mach-spear3xx => mach-spear}/spear3xx.c    |  17 +-
 .../{mach-spear6xx => mach-spear}/spear6xx.c    |  25 +-
 arch/arm/{plat-spear => mach-spear}/time.c      |   2 +-
 arch/arm/mach-spear13xx/Kconfig                 |  20 --
 arch/arm/mach-spear13xx/Makefile                |  10 -
 .../mach-spear13xx/include/mach/debug-macro.S   |  14 -
 arch/arm/mach-spear13xx/include/mach/hardware.h |   1 -
 arch/arm/mach-spear13xx/include/mach/irqs.h     |  20 --
 arch/arm/mach-spear13xx/include/mach/spear.h    |  54 ----
 arch/arm/mach-spear13xx/include/mach/timex.h    |  19 --
 .../mach-spear13xx/include/mach/uncompress.h    |  19 --
 arch/arm/mach-spear3xx/Kconfig                  |  26 --
 arch/arm/mach-spear3xx/Makefile                 |  15 -
 arch/arm/mach-spear3xx/Makefile.boot            |   3 -
 .../mach-spear3xx/include/mach/debug-macro.S    |  14 -
 arch/arm/mach-spear3xx/include/mach/generic.h   |  36 ---
 arch/arm/mach-spear3xx/include/mach/hardware.h  |   1 -
 arch/arm/mach-spear3xx/include/mach/irqs.h      |  19 --
 arch/arm/mach-spear3xx/include/mach/spear.h     |  60 ----
 arch/arm/mach-spear3xx/include/mach/timex.h     |  19 --
 .../arm/mach-spear3xx/include/mach/uncompress.h |  19 --
 arch/arm/mach-spear6xx/Kconfig                  |  10 -
 arch/arm/mach-spear6xx/Makefile                 |   6 -
 arch/arm/mach-spear6xx/Makefile.boot            |   3 -
 .../mach-spear6xx/include/mach/debug-macro.S    |  14 -
 arch/arm/mach-spear6xx/include/mach/generic.h   |  23 --
 arch/arm/mach-spear6xx/include/mach/hardware.h  |   1 -
 arch/arm/mach-spear6xx/include/mach/misc_regs.h |  22 --
 arch/arm/mach-spear6xx/include/mach/spear.h     |  46 ---
 arch/arm/mach-spear6xx/include/mach/timex.h     |  19 --
 .../arm/mach-spear6xx/include/mach/uncompress.h |  19 --
 arch/arm/mach-tegra/Kconfig                     |  29 +-
 arch/arm/mach-tegra/Makefile                    |   2 +
 arch/arm/mach-tegra/Makefile.boot               |   3 -
 arch/arm/mach-tegra/board.h                     |   1 +
 arch/arm/mach-tegra/common.c                    |   2 -
 arch/arm/mach-tegra/include/mach/timex.h        |  26 --
 arch/arm/mach-tegra/include/mach/uncompress.h   | 175 ----------
 arch/arm/mach-tegra/pcie.c                      |   3 +-
 arch/arm/mach-tegra/powergate.c                 |   3 +-
 arch/arm/mach-ux500/Kconfig                     |  16 +
 arch/arm/mach-ux500/Makefile                    |   4 +-
 arch/arm/mach-ux500/board-mop500-audio.c        |   7 +-
 arch/arm/mach-ux500/board-mop500-pins.c         |   2 -
 arch/arm/mach-ux500/board-mop500-sdi.c          |   4 +-
 arch/arm/mach-ux500/board-mop500-u8500uib.c     |   9 +-
 arch/arm/mach-ux500/board-mop500-uib.c          |   1 -
 arch/arm/mach-ux500/board-mop500.c              |  66 +---
 arch/arm/mach-ux500/board-mop500.h              |   4 +-
 arch/arm/mach-ux500/cache-l2x0.c                |   2 +-
 arch/arm/mach-ux500/cpu-db8500.c                |  12 +-
 arch/arm/mach-ux500/cpu.c                       |  33 +-
 arch/arm/mach-ux500/cpuidle.c                   |   5 +-
 .../mach-ux500/{include/mach => }/db8500-regs.h |  28 ++
 arch/arm/mach-ux500/devices-common.c            |   3 +-
 arch/arm/mach-ux500/devices-db8500.c            |   8 +-
 arch/arm/mach-ux500/devices-db8500.h            |   3 +-
 arch/arm/mach-ux500/devices.c                   |   5 +-
 .../arm/mach-ux500/{include/mach => }/devices.h |   0
 arch/arm/mach-ux500/hotplug.c                   |   2 +-
 arch/arm/mach-ux500/id.c                        |   4 +-
 arch/arm/mach-ux500/include/mach/debug-macro.S  |  39 ---
 arch/arm/mach-ux500/include/mach/hardware.h     |  47 ---
 arch/arm/mach-ux500/include/mach/timex.h        |   6 -
 arch/arm/mach-ux500/include/mach/uncompress.h   |  57 ----
 .../{include/mach => }/irqs-board-mop500.h      |   0
 .../mach-ux500/{include/mach => }/irqs-db8500.h |  25 --
 arch/arm/mach-ux500/{include/mach => }/irqs.h   |   6 +-
 arch/arm/mach-ux500/platsmp.c                   |   4 +-
 arch/arm/mach-ux500/pm.c                        | 167 ++++++++++
 arch/arm/mach-ux500/{include/mach => }/setup.h  |   0
 arch/arm/mach-ux500/timer.c                     |   6 +-
 arch/arm/mach-ux500/usb.c                       |   2 +-
 arch/arm/mach-vexpress/Kconfig                  |   2 +
 arch/arm/mach-zynq/Kconfig                      |   2 +
 arch/arm/plat-samsung/devs.c                    |  45 ---
 arch/arm/plat-samsung/include/plat/sdhci.h      |  56 +---
 arch/arm/plat-samsung/irq-vic-timer.c           |   1 +
 arch/arm/plat-samsung/pm.c                      |   1 +
 arch/arm/plat-samsung/s5p-dev-mfc.c             |  42 ++-
 arch/arm/plat-samsung/s5p-irq.c                 |   1 +
 arch/arm/plat-spear/Kconfig                     |  47 ---
 arch/arm/plat-spear/Makefile                    |   9 -
 drivers/clk/spear/spear1310_clock.c             |  64 ++--
 drivers/clk/spear/spear1340_clock.c             |  63 ++--
 drivers/clk/spear/spear3xx_clock.c              |  60 ++--
 drivers/clk/spear/spear6xx_clock.c              |  31 +-
 drivers/clk/tegra/clk-tegra30.c                 |   3 +-
 drivers/clk/ux500/clk-prcc.c                    |   1 -
 drivers/clk/ux500/u8500_clk.c                   | 142 ++++-----
 drivers/clocksource/Makefile                    |   2 +
 drivers/clocksource/clksrc-dbx500-prcmu.c       |   3 -
 drivers/clocksource/nomadik-mtu.c               |   4 +-
 .../clocksource}/timer-marco.c                  |  25 +-
 .../clocksource}/timer-prima2.c                 |  42 +--
 drivers/crypto/ux500/cryp/cryp.c                |   2 -
 drivers/crypto/ux500/cryp/cryp_core.c           |   1 -
 drivers/crypto/ux500/hash/hash_core.c           |   1 -
 drivers/irqchip/Makefile                        |   1 +
 drivers/irqchip/irq-sirfsoc.c                   | 126 ++++++++
 drivers/mfd/db8500-prcmu.c                      | 316 +++++++++----------
 drivers/mfd/dbx500-prcmu-regs.h                 | 204 ++++++------
 drivers/mmc/host/sdhci-cns3xxx.c                |   1 -
 .../mmc/host/sdhci-s3c-regs.h                   |   0
 drivers/mmc/host/sdhci-s3c.c                    |   5 +-
 drivers/mtd/onenand/samsung.c                   |   4 +-
 .../mtd/onenand/samsung.h                       |   2 -
 drivers/pinctrl/pinctrl-sirf.c                  |  12 +-
 drivers/rtc/rtc-s3c.c                           |   3 +-
 .../plat/regs-rtc.h => drivers/rtc/rtc-s3c.h    |   3 +-
 drivers/staging/ste_rmi4/Makefile               |   1 -
 .../ste_rmi4/board-mop500-u8500uib-rmi4.c       |  31 --
 drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c   |  31 +-
 drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h   |   1 -
 drivers/thermal/exynos_thermal.c                |   2 -
 include/linux/mfd/db8500-prcmu.h                |  10 +-
 include/linux/mfd/dbx500-prcmu.h                |  38 +--
 include/linux/platform_data/arm-ux500-pm.h      |  21 ++
 .../linux/platform_data/asoc-ux500-msp.h        |   0
 include/linux/platform_data/clk-ux500.h         |   3 +-
 include/linux/platform_data/mmc-sdhci-s3c.h     |  56 ++++
 .../linux/tegra-powergate.h                     |   5 -
 sound/soc/ux500/mop500_ab8500.c                 |   2 -
 sound/soc/ux500/ux500_msp_dai.c                 |   4 +-
 sound/soc/ux500/ux500_msp_i2s.c                 |   4 +-
 sound/soc/ux500/ux500_msp_i2s.h                 |   2 -
 236 files changed, 1834 insertions(+), 2887 deletions(-)
 rename arch/arm/{mach-bcm2835/include/mach/debug-macro.S => include/debug/bcm2835.S} (86%)
 rename arch/arm/{mach-cns3xxx/include/mach/debug-macro.S => include/debug/cns3xxx.S} (100%)
 rename arch/arm/{mach-exynos/include/mach/debug-macro.S => include/debug/exynos.S} (84%)
 rename arch/arm/{mach-mxs/include/mach/debug-macro.S => include/debug/mxs.S} (100%)
 rename arch/arm/{mach-nomadik/include/mach/debug-macro.S => include/debug/nomadik.S} (100%)
 rename arch/arm/{plat-samsung/include/plat/debug-macro.S => include/debug/samsung.S} (100%)
 rename arch/arm/{mach-prima2/include/mach/uart.h => include/debug/sirf.S} (55%)
 create mode 100644 arch/arm/include/debug/ux500.S
 create mode 100644 arch/arm/mach-bcm2835/Kconfig
 delete mode 100644 arch/arm/mach-bcm2835/Makefile.boot
 delete mode 100644 arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
 delete mode 100644 arch/arm/mach-bcm2835/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-bcm2835/include/mach/timex.h
 delete mode 100644 arch/arm/mach-bcm2835/include/mach/uncompress.h
 rename arch/arm/mach-cns3xxx/{include/mach => }/cns3xxx.h (99%)
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/uncompress.h
 rename arch/arm/mach-cns3xxx/{include/mach => }/pm.h (100%)
 delete mode 100644 arch/arm/mach-mxs/Makefile.boot
 delete mode 100644 arch/arm/mach-mxs/include/mach/timex.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-mxs/pm.h
 delete mode 100644 arch/arm/mach-nomadik/Makefile.boot
 delete mode 100644 arch/arm/mach-nomadik/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/timex.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/map.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/timex.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-prima2/irq.c
 create mode 100644 arch/arm/mach-spear/Kconfig
 create mode 100644 arch/arm/mach-spear/Makefile
 rename arch/arm/{mach-spear13xx => mach-spear}/Makefile.boot (100%)
 rename arch/arm/{mach-spear13xx/include/mach => mach-spear}/generic.h (57%)
 rename arch/arm/{mach-spear13xx => mach-spear}/headsmp.S (100%)
 rename arch/arm/{mach-spear13xx => mach-spear}/hotplug.c (100%)
 rename arch/arm/{plat-spear/include/plat => mach-spear/include/mach}/debug-macro.S (100%)
 rename arch/arm/{mach-spear6xx => mach-spear}/include/mach/irqs.h (51%)
 rename arch/arm/{mach-spear3xx => mach-spear}/include/mach/misc_regs.h (90%)
 create mode 100644 arch/arm/mach-spear/include/mach/spear.h
 rename arch/arm/{plat-spear/include/plat => mach-spear/include/mach}/timex.h (100%)
 rename arch/arm/{plat-spear/include/plat => mach-spear/include/mach}/uncompress.h (100%)
 rename arch/arm/{plat-spear => mach-spear}/pl080.c (100%)
 rename arch/arm/{plat-spear/include/plat => mach-spear}/pl080.h (100%)
 rename arch/arm/{mach-spear13xx => mach-spear}/platsmp.c (99%)
 rename arch/arm/{plat-spear => mach-spear}/restart.c (90%)
 rename arch/arm/{mach-spear13xx => mach-spear}/spear1310.c (95%)
 rename arch/arm/{mach-spear13xx => mach-spear}/spear1340.c (99%)
 rename arch/arm/{mach-spear13xx/include/mach/dma.h => mach-spear/spear13xx-dma.h} (100%)
 rename arch/arm/{mach-spear13xx => mach-spear}/spear13xx.c (96%)
 rename arch/arm/{mach-spear3xx => mach-spear}/spear300.c (98%)
 rename arch/arm/{mach-spear3xx => mach-spear}/spear310.c (98%)
 rename arch/arm/{mach-spear3xx => mach-spear}/spear320.c (97%)
 rename arch/arm/{mach-spear3xx => mach-spear}/spear3xx.c (88%)
 rename arch/arm/{mach-spear6xx => mach-spear}/spear6xx.c (93%)
 rename arch/arm/{plat-spear => mach-spear}/time.c (99%)
 delete mode 100644 arch/arm/mach-spear13xx/Kconfig
 delete mode 100644 arch/arm/mach-spear13xx/Makefile
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig
 delete mode 100644 arch/arm/mach-spear3xx/Makefile
 delete mode 100644 arch/arm/mach-spear3xx/Makefile.boot
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/generic.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/spear.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-spear6xx/Kconfig
 delete mode 100644 arch/arm/mach-spear6xx/Makefile
 delete mode 100644 arch/arm/mach-spear6xx/Makefile.boot
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/generic.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/misc_regs.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/spear.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-tegra/Makefile.boot
 delete mode 100644 arch/arm/mach-tegra/include/mach/timex.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/uncompress.h
 rename arch/arm/mach-ux500/{include/mach => }/db8500-regs.h (88%)
 rename arch/arm/mach-ux500/{include/mach => }/devices.h (100%)
 delete mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/timex.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h
 rename arch/arm/mach-ux500/{include/mach => }/irqs-board-mop500.h (100%)
 rename arch/arm/mach-ux500/{include/mach => }/irqs-db8500.h (83%)
 rename arch/arm/mach-ux500/{include/mach => }/irqs.h (93%)
 create mode 100644 arch/arm/mach-ux500/pm.c
 rename arch/arm/mach-ux500/{include/mach => }/setup.h (100%)
 delete mode 100644 arch/arm/plat-spear/Kconfig
 delete mode 100644 arch/arm/plat-spear/Makefile
 rename {arch/arm/mach-prima2 => drivers/clocksource}/timer-marco.c (94%)
 rename {arch/arm/mach-prima2 => drivers/clocksource}/timer-prima2.c (90%)
 create mode 100644 drivers/irqchip/irq-sirfsoc.c
 rename arch/arm/plat-samsung/include/plat/regs-sdhci.h => drivers/mmc/host/sdhci-s3c-regs.h (100%)
 rename arch/arm/plat-samsung/include/plat/regs-onenand.h => drivers/mtd/onenand/samsung.h (98%)
 rename arch/arm/plat-samsung/include/plat/regs-rtc.h => drivers/rtc/rtc-s3c.h (97%)
 delete mode 100644 drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
 create mode 100644 include/linux/platform_data/arm-ux500-pm.h
 rename arch/arm/mach-ux500/include/mach/msp.h => include/linux/platform_data/asoc-ux500-msp.h (100%)
 create mode 100644 include/linux/platform_data/mmc-sdhci-s3c.h
 rename arch/arm/mach-tegra/include/mach/powergate.h => include/linux/tegra-powergate.h (92%)


From mingo at kernel.org  Thu May  2 03:30:20 2013
From: mingo at kernel.org (Ingo Molnar)
Date: Thu, 2 May 2013 09:30:20 +0200
Subject: [PATCH -v7 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1367428011-17123-11-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <1367428011-17123-11-git-send-email-holt@sgi.com>
Message-ID: <20130502073020.GC26361@gmail.com>


* Robin Holt <holt at sgi.com> wrote:

>  #ifndef __ASSEMBLY__
>  
>  #include <linux/types.h>
> +#include <linux/reboot.h>
>  
>  void iop3xx_map_io(void);
>  void iop_init_cp6_handler(void);
>  void iop_init_time(unsigned long tickrate);
> -void iop3xx_restart(char, const char *);
> +void iop3xx_restart(enum reboot_mode, const char *);

IMO the introduction of the enum is making things cleaner here all around.

As long as it's an equivalent transformation for ARM with no reduction in 
functionality (i.e. please fix any bugs Russell found), this all looks 
like a nice series.

Is there no parameter namespace clash between reboot modifier strings on 
various architectures? I.e. 's' meaning something on x86 and meaning a 
different thing on ARM or some other architecture.

Thanks,

	Ingo


From mingo at kernel.org  Thu May  2 03:34:00 2013
From: mingo at kernel.org (Ingo Molnar)
Date: Thu, 2 May 2013 09:34:00 +0200
Subject: [PATCH -v7 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <1367428011-17123-12-git-send-email-holt@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <1367428011-17123-12-git-send-email-holt@sgi.com>
Message-ID: <20130502073400.GD26361@gmail.com>


* Robin Holt <holt at sgi.com> wrote:

> Merge together the unicore32, arm, and x86 reboot= command line
> parameter handling.

Nice!

> +		switch (*str) {
> +#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
> +		case 'w':
> +			reboot_mode = REBOOT_WARM;
> +			break;
> +
> +		case 'c':
> +			reboot_mode = REBOOT_COLD;
> +			break;
> +
> +#ifdef CONFIG_SMP
> +		case 's':
> +			if (isdigit(*(str+1))) {
> +				reboot_cpu = (int) (*(str+1) - '0');
> +				if (isdigit(*(str+2)))
> +					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
> +			}
> +			/*
> +			 * We will leave sorting out the final value
> +			 * when we are ready to reboot, since we might not
> +			 * have detected BSP APIC ID or smp_num_cpu
> +			 */
> +			break;
> +#endif /* CONFIG_SMP */
> +
> +#else
> +		case 's':
> +			reboot_mode = REBOOT_WARM;
> +		case 'h':
> +			reboot_mode = REBOOT_COLD;
> +#endif

This architecture dependent bit is not so nice.

I doubt the 's' parameter is used widely at all on x86 [it's more like a 
debug/hack parameter], so might as well just pick up a new character (for 
example capital 'S'?) and have the same parameters on every architecture.

Thanks,

	Ingo


From richard.genoud at gmail.com  Thu May  2 04:12:03 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Thu, 2 May 2013 10:12:03 +0200
Subject: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
 xfer->speed_hz set
In-Reply-To: <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>
References: <1362626715-6549-1-git-send-email-wenyou.yang@atmel.com>
 <1362626815-6628-1-git-send-email-wenyou.yang@atmel.com>
 <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
 <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>
Message-ID: <CACQ1gAhZO3stjrwf5SiZf7jOO8T5bAJZiz97M7+7vwFmk2e65g@mail.gmail.com>

2013/5/2 Yang, Wenyou <Wenyou.Yang at atmel.com>:
> Hi, Joachim,
>
>> -----Original Message-----
>> From: Joachim Eastwood [mailto:manabian at gmail.com]
>> Sent: 2013?3?7? 20:31
>> To: Yang, Wenyou
>> Cc: linux-arm-kernel at lists.infradead.org; grant.likely at secretlab.ca; Ferre,
>> Nicolas; plagnioj at jcrosoft.com; richard.genoud at gmail.com; Lin, JM;
>> spi-devel-general at lists.sourceforge.net; linux-kernel at vger.kernel.org
>> Subject: Re: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
>> xfer->speed_hz set
>>
>> On 7 March 2013 04:26, Wenyou Yang <wenyou.yang at atmel.com> wrote:
>> > commit: 059b8ffeee5b427949872bb6ed5db5ae0788054e
>> > cause the atmel spi probing failure.
>> >
>> > Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
>> > Cc: spi-devel-general at lists.sourceforge.net
>> > Cc: linux-kernel at vger.kernel.org
>> > ---
>> >  drivers/spi/spi-atmel.c |    6 +++---
>> >  1 file changed, 3 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
>> > index 656d137..1eca815 100644
>> > --- a/drivers/spi/spi-atmel.c
>> > +++ b/drivers/spi/spi-atmel.c
>> > @@ -846,9 +846,9 @@ static int atmel_spi_transfer(struct spi_device *spi,
>> struct spi_message *msg)
>> >                         }
>> >                 }
>> >
>> > -               /* FIXME implement these protocol options!! */
>> > -               if (xfer->speed_hz) {
>> > -                       dev_dbg(&spi->dev, "no protocol options
>> yet\n");
>> > +               if (xfer->speed_hz < spi->max_speed_hz) {
>> > +                       dev_dbg(&spi->dev,
>> > +                               "speed in transfer less than bus
>> speed\n");
>> >                         return -ENOPROTOOPT;
>> >                 }
>>
>> I sent a similar patch to spi-devl a while ago, which Grant said he applied.
>> https://patchwork.kernel.org/patch/2165301/
>>
>> Can't find the patch in any upstream git tree so I guess Grant hasn't
>> pushed it yet.
> This patch hasn't still applied in any upstream git tree, so Atmel spi master doesn't work.
> Could you help do some ping it?

it's in linux-next:
3d3522604a5557e80fdcab61c54bd04eaf15b525
merged from spi-current/spi/merge


Richard.


From Ian.Campbell at citrix.com  Thu May  2 04:19:14 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 2 May 2013 09:19:14 +0100
Subject: [Xen-devel] [PATCH 2/3] xen: move do_stolen_accounting to
 drivers/xen/time.c
In-Reply-To: <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <1367482754.21869.25.camel@zakaz.uk.xensource.com>

On Wed, 2013-05-01 at 20:27 +0100, Stefano Stabellini wrote:
> Move do_stolen_accounting, xen_vcpu_stolen and related functions and
> static variables to common code (drivers/xen/time.c).
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

Acked-by: Ian Campbell <ian.campbell at citrix.com>

> +	/* work out how much time the VCPU has not been runn*ing*  */

I wonder what this emphasis on runn*ing* means?

Ian.



From Ian.Campbell at citrix.com  Thu May  2 04:19:32 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 2 May 2013 09:19:32 +0100
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <51817CBE.4050003@codeaurora.org>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
Message-ID: <1367482772.21869.26.camel@zakaz.uk.xensource.com>

On Wed, 2013-05-01 at 21:36 +0100, Christopher Covington wrote:
> Hi Stefano,
> 
> On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> > Introduce a function, called arch_timer_stolen_ticks, called from the
> > arch_timer interrupt handler to account for stolen ticks.
> 
> [...]
> 
> > diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
> > index 7ade91d..30db413 100644
> > --- a/arch/arm/include/asm/arch_timer.h
> > +++ b/arch/arm/include/asm/arch_timer.h
> > @@ -13,6 +13,11 @@
> >  int arch_timer_of_register(void);
> >  int arch_timer_sched_clock_init(void);
> >  
> > +/* per-platform function to calculate stolen ticks (clock cycles stolen
> > + * to the vcpu by the hypervisor).
> 
> Stolen from the vcpu by the hypervisor?

Stolen is time where the VCPU wants to be running bit isn't because the
hypervisor has descheduled it, e.g. because another VCPU is being run.
So yes, Stefano meant "from".

> Is the hypervisor adjusting the Virtual Offset Register?

The virtual offset register is useful when a VCPU is migrated to another
system to account for the differences in physical time on the two hosts
but isn't useful for accounting for stolen time while running on a
single host.

e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
where the timer goes off. Nor does it make sense to require that the
guest actually be running for 5 before injecting the timer because that
would mean real time elapsed time for the timer would be 5+3 in the case
where 3 are stolen.

So the virtual timer should appear to have been running even while time
is being stolen and therefore stolen time needs to be accounted via some
other means.

Ian.



From b35083 at freescale.com  Thu May  2 03:38:03 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 2 May 2013 15:38:03 +0800
Subject: [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and
 development board support This Vybird MVF600 family is a heterogeneous
 dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This
 SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower
 development board.
Message-ID: <1367480285-26159-1-git-send-email-b35083@freescale.com>

Documentation/devicetree/bindings/clock/mvf600-clock.txt | 180 ++++++++
arch/arm/boot/dts/Makefile                               |   3 +-
arch/arm/boot/dts/mvf600-pinfunc.h                       | 816 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mvf600-twr.dts                         |  80 ++++
arch/arm/boot/dts/mvf600.dtsi                            | 426 ++++++++++++++++++
arch/arm/mach-imx/Kconfig                                |  15 +
arch/arm/mach-imx/Makefile                               |   3 +
arch/arm/mach-imx/clk-mvf.c                              | 406 +++++++++++++++++
arch/arm/mach-imx/common.h                               |   1 +
arch/arm/mach-imx/mach-mvf600.c                          | 118 +++++
arch/arm/mach-imx/pit.c                                  | 244 +++++++++++
11 files changed, 2291 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
create mode 100644 arch/arm/boot/dts/mvf600.dtsi
create mode 100644 arch/arm/mach-imx/clk-mvf.c
create mode 100644 arch/arm/mach-imx/mach-mvf600.c
create mode 100644 arch/arm/mach-imx/pit.c



From b35083 at freescale.com  Thu May  2 03:38:04 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 2 May 2013 15:38:04 +0800
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <1367480285-26159-1-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
Message-ID: <1367480285-26159-2-git-send-email-b35083@freescale.com>

This patch adds Freescale Vybrid Family platform core definitions,
core drivers, including clock, period interrupt timer(PIT),
and DTS based machine support with MVF600 Tower development board.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
V2:
  Use CLOCKSOURCE_OF_DECLARE init timer
  Add ONESHOT mode support
  Add more clks definitions on MVF600 soc

 .../devicetree/bindings/clock/mvf600-clock.txt     | 180 +++++++++
 arch/arm/mach-imx/Kconfig                          |  15 +
 arch/arm/mach-imx/Makefile                         |   3 +
 arch/arm/mach-imx/clk-mvf.c                        | 406 +++++++++++++++++++++
 arch/arm/mach-imx/common.h                         |   1 +
 arch/arm/mach-imx/mach-mvf600.c                    | 118 ++++++
 arch/arm/mach-imx/pit.c                            | 244 +++++++++++++
 7 files changed, 967 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
 create mode 100644 arch/arm/mach-imx/clk-mvf.c
 create mode 100644 arch/arm/mach-imx/mach-mvf600.c
 create mode 100644 arch/arm/mach-imx/pit.c

diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
new file mode 100644
index 0000000..9f8b20e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
@@ -0,0 +1,180 @@
+* Clock bindings for Freescale Vybrid Family
+
+Required properties:
+- compatible: Should be "fsl,mvf-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of MVF600
+clocks and IDs.
+
+	Clock			ID
+	---------------------------
+	dummy			0
+	sirc_128k		1
+	sirc_32k		2
+	firc			3
+	sxosc			4
+	fxosc			5
+	fxosc_half		6
+	slow_clk		7
+	fast_clk		8
+	audio_ext		9
+	enet_ext		10
+	pll1_main_528m		11
+	pll1_pfd1_500m		12
+	pll1_pfd2_452m		13
+	pll1_pfd3_396m		14
+	pll1_pfd4_528m		15
+	pll2_main_528m		16
+	pll2_pfd1_500m		17
+	pll2_pfd2_396m		18
+	pll2_pfd3_339m		19
+	pll2_pfd4_413m		20
+	pll3_main_480m		21
+	pll3_pfd1_308m		22
+	pll3_pfd2_332m		23
+	pll3_pfd3_298m		24
+	pll3_pfd4_320m		25
+	pll4_main		26
+	pll5_main		27
+	pll6_main		28
+	pll3_main_div		29
+	pll4_main_div		30
+	pll6_main_div		31
+	pll1_sw			32
+	pll2_sw			33
+	sys_sw			34
+	ddr_sw			35
+	sys_bus_clk		36
+	platform_bus_clk	37
+	ipg_bus_clk		38
+	uart0_clk		39
+	uart1_clk		40
+	uart2_clk		41
+	uart3_clk		42
+	uart4_clk		43
+	uart5_clk		44
+	pit_clk			45
+	i2c0_clk		46
+	i2c1_clk		47
+	i2c2_clk		48
+	i2c3_clk		49
+	ftm0_ext_sw		50
+	ftm0_fix_sw		51
+	ftm0_ext_fix_gate	52
+	ftm1_ext_sw		53
+	ftm1_fix_sw		54
+	ftm1_ext_fix_gate	55
+	ftm2_ext_sw		56
+	ftm2_fix_sw		57
+	ftm2_ext_fix_gate	58
+	ftm3_ext_sw		59
+	ftm3_fix_sw		60
+	ftm3_ext_fix_gate	61
+	ftm0_clk		62
+	ftm1_clk		63
+	ftm2_clk		64
+	ftm3_clk		65
+	enet_50m		66
+	enet_25m		67
+	enet_clk_sw		68
+	enet_clk		69
+	enet_ts_sw		70
+	enet_ts			71
+	dspi0_clk		72
+	dspi1_clk		73
+	dspi2_clk		74
+	dspi3_clk		75
+	wdt_clk			76
+	esdhc0_sw		77
+	esdhc0_gate		78
+	esdhc0_div		79
+	esdhc0_clk		80
+	esdhc1_sw		81
+	esdhc1_gate		82
+	esdhc1_div		83
+	esdhc1_clk		84
+	dcu0_sw			85
+	dcu0_gate		86
+	dcu0_div		87
+	dcu0_clk		88
+	dcu1_sw			89
+	dcu1_gate		90
+	dcu1_div		91
+	dcu1_clk		92
+	esai_sw			93
+	esai_gate		94
+	esai_div		95
+	esai_clk		96
+	sai0_sw			97
+	sai0_gate		98
+	sai0_div		99
+	sai0_clk		100
+	sai1_sw			101
+	sai1_gate		102
+	sai1_div		103
+	sai1_clk		104
+	sai2_sw			105
+	sai2_gate		106
+	sai2_div		107
+	sai2_clk		108
+	sai3_sw			109
+	sai3_gate		110
+	sai3_div		111
+	sai3_clk		112
+	usbc0_clk		113
+	usbc1_clk		114
+	qspi0_sw		115
+	qspi0_gate		116
+	qspi0_x4_div		117
+	qspi0_x2_div		118
+	qspi0_x1_div		119
+	qspi1_sw		120
+	qspi1_gate		121
+	qspi1_x4_div		122
+	qspi1_x2_div		123
+	qspi1_x1_div		124
+	qspi0_clk		125
+	qspi1_clk		126
+	nfc_sw			127
+	nfc_gate		128
+	nfc_pre_div		129
+	nfc_frac_div		130
+	nfc_inv			131
+	nfc_clk			132
+	vadc_sw			133
+	vadc_gate		134
+	vadc_div		135
+	vadc_div_half		136
+	vadc_clk		137
+	adc0_clk		138
+	adc1_clk		139
+	dac0_clk		140
+	dac1_clk		141
+	flexcan0_clk		142
+	flexcan1_clk		143
+	asrc_clk		144
+	gpu_sw			145
+	gpu_gate		146
+	gpu2d_clk		147
+
+
+
+Examples:
+
+clks: ccm at 4006b000 {
+	compatible = "fsl,mvf-ccm";
+	reg = <0x4006b000 0x1000>;
+	#clock-cells = <1>;
+};
+
+uart1: serial at 40028000 { /* UART1 */
+	compatible = "fsl,mvf-uart";
+	reg = <0x40028000 0x1000>;
+	interrupts = <0 62 0x04>;
+	clocks = <&clks 35>;
+	clock-names = "ipg";
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 78f795d..2fb9562 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -819,6 +819,21 @@ config SOC_IMX6Q
 	help
 	  This enables support for Freescale i.MX6 Quad processor.
 
+config SOC_MVF600
+	bool "Vybrid Family MVF600 support"
+	select CPU_V7
+	select ARM_GIC
+	select COMMON_CLK
+	select CLKSRC_OF
+	select PINCTRL
+	select PINCTRL_MVF
+	select PL310_ERRATA_588369 if CACHE_PL310
+	select PL310_ERRATA_727915 if CACHE_PL310
+	select PL310_ERRATA_769419 if CACHE_PL310
+
+	help
+	  This enable support for Freescale Vybrid Family VF6xx MPU.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b16eb39..76a2ead 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -112,4 +112,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
+# Vybrid based machines
+obj-$(CONFIG_SOC_MVF600) += clk-mvf.o mach-mvf600.o pit.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/clk-mvf.c b/arch/arm/mach-imx/clk-mvf.c
new file mode 100644
index 0000000..1467a304
--- /dev/null
+++ b/arch/arm/mach-imx/clk-mvf.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/hrtimer.h>
+#include <linux/mm.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/clkdev.h>
+#include <linux/regulator/consumer.h>
+#include <asm/div64.h>
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "hardware.h"
+#include "common.h"
+#include "clk.h"
+
+
+#define CCM_CCR		(ccm_base + 0x00)
+#define CCM_CSR		(ccm_base + 0x04)
+#define CCM_CCSR		(ccm_base + 0x08)
+#define CCM_CACRR		(ccm_base + 0x0c)
+#define CCM_CSCMR1		(ccm_base + 0x10)
+#define CCM_CSCDR1		(ccm_base + 0x14)
+#define CCM_CSCDR2		(ccm_base + 0x18)
+#define CCM_CSCDR3		(ccm_base + 0x1c)
+#define CCM_CSCMR2		(ccm_base + 0x20)
+#define CCM_CSCDR4		(ccm_base + 0x24)
+#define CCM_CLPCR		(ccm_base + 0x2c)
+#define CCM_CISR		(ccm_base + 0x30)
+#define CCM_CIMR		(ccm_base + 0x34)
+#define CCM_CGPR		(ccm_base + 0x3c)
+#define CCM_CCGR0		(ccm_base + 0x40)
+#define CCM_CCGR1		(ccm_base + 0x44)
+#define CCM_CCGR2		(ccm_base + 0x48)
+#define CCM_CCGR3		(ccm_base + 0x4c)
+#define CCM_CCGR4		(ccm_base + 0x50)
+#define CCM_CCGR5		(ccm_base + 0x54)
+#define CCM_CCGR6		(ccm_base + 0x58)
+#define CCM_CCGR7		(ccm_base + 0x5c)
+#define CCM_CCGR8		(ccm_base + 0x60)
+#define CCM_CCGR9		(ccm_base + 0x64)
+#define CCM_CCGR10		(ccm_base + 0x68)
+#define CCM_CCGR11		(ccm_base + 0x6C)
+#define CCM_CMEOR0		(ccm_base + 0x70)
+#define CCM_CMEOR1		(ccm_base + 0x74)
+#define CCM_CMEOR2		(ccm_base + 0x78)
+#define CCM_CMEOR3		(ccm_base + 0x7C)
+#define CCM_CMEOR4		(ccm_base + 0x80)
+#define CCM_CMEOR5		(ccm_base + 0x84)
+#define CCM_CPPDSR		(ccm_base + 0x88)
+#define CCM_CCOWR		(ccm_base + 0x8C)
+#define CCM_CCPGR0		(ccm_base + 0x90)
+#define CCM_CCPGR1		(ccm_base + 0x94)
+#define CCM_CCPGR2		(ccm_base + 0x98)
+#define CCM_CCPGR3		(ccm_base + 0x9C)
+
+#define CCM_CCGRx_CGn(n)		(n * 2)
+
+#define PFD_528SYS_BASE		(anatop_base + 0x2B0)
+#define PFD_528_BASE		(anatop_base + 0x100)
+#define PFD_USB_BASE		(anatop_base + 0xF0) /* pll3 pfd definition */
+
+
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+
+/* This is used multiple times */
+static const char const *fast_clk_sel[] = { "firc", "fxosc", };
+static const char const *slow_clk_sel[] = { "sirc_32k", "sxosc", };
+static const char const *pll1_pfd_sel[] = {
+	"pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4",
+};
+static const char const *pll2_pfd_sel[] = {
+	"pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4",
+};
+static const char const *sys_clk_sel[] = {
+	"fast_clk", "slow_clk", "pll2_sw", "pll2_main", "pll1_sw", "pll3_main",
+};
+static const char const *ddr_clk_sel[] = { "pll2_pfd2", "sys_clk", };
+static const char const *rmii_clk_sel[] = {
+	"enet_ext", "audio_ext", "enet_50m", "enet_25m",
+};
+static const char const *enet_ts_clk_sel[] = {
+	"enet_ext", "fxosc", "audio_ext", "usb_clk", "enet_ts_clk", "enet_25m", "enet_50m",
+};
+static const char const *esai_clk_sel[] = {
+	"audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div",
+};
+static const char const *sai_clk_sel[] = {
+	"audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div",
+};
+static const char const *nfc_clk_sel[] = {
+	"platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3",
+};
+static const char const *qspi_clk_sel[] = {
+	"pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4",
+};
+static const char const *esdhc_clk_sel[] = {
+	"pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus",
+};
+static const char const *dcu_clk_sel[] = { "pll1_pfd2", "pll3_main", };
+static const char const *gpu_clk_sel[] = { "pll2_pfd2", "pll3_pfd2", };
+static const char const *vadc_clk_sel[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+/* FTM counter clock source, not module clock */
+static const char const *ftm_ext_clk_sel[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char const *ftm_fix_clk_sel[] = { "sxosc", "ipg_bus", };
+
+enum mvf_clks {
+	dummy,
+	sirc_128k, sirc_32k, firc, sxosc, fxosc, fxosc_half,
+	slow_clk, fast_clk, audio_ext, enet_ext,
+	pll1_main_528m, pll1_pfd1_500m, pll1_pfd2_452m,
+	pll1_pfd3_396m, pll1_pfd4_528m, pll2_main_528m, pll2_pfd1_500m,
+	pll2_pfd2_396m, pll2_pfd3_339m, pll2_pfd4_413m, pll3_main_480m,
+	pll3_pfd1_308m, pll3_pfd2_332m, pll3_pfd3_298m, pll3_pfd4_320m,
+	pll4_main, pll5_main, pll6_main,
+	pll3_main_div, pll4_main_div, pll6_main_div,
+	pll1_sw, pll2_sw, sys_sw, ddr_sw,
+	sys_bus_clk, platform_bus_clk, ipg_bus_clk,
+	uart0_clk, uart1_clk, uart2_clk, uart3_clk, uart4_clk, uart5_clk,
+	pit_clk,
+	i2c0_clk, i2c1_clk, i2c2_clk, i2c3_clk,
+	ftm0_ext_sw, ftm0_fix_sw, ftm0_ext_fix_gate,
+	ftm1_ext_sw, ftm1_fix_sw, ftm1_ext_fix_gate,
+	ftm2_ext_sw, ftm2_fix_sw, ftm2_ext_fix_gate,
+	ftm3_ext_sw, ftm3_fix_sw, ftm3_ext_fix_gate,
+	ftm0_clk, ftm1_clk, ftm2_clk, ftm3_clk,
+	enet_50m, enet_25m, enet_clk_sw, enet_clk, enet_ts_sw, enet_ts,
+	dspi0_clk, dspi1_clk, dspi2_clk, dspi3_clk,
+	wdt_clk,
+	esdhc0_sw, esdhc0_gate, esdhc0_div, esdhc0_clk,
+	esdhc1_sw, esdhc1_gate, esdhc1_div, esdhc1_clk,
+	dcu0_sw, dcu0_gate, dcu0_div, dcu0_clk,
+	dcu1_sw, dcu1_gate, dcu1_div, dcu1_clk,
+	esai_sw, esai_gate, esai_div, esai_clk,
+	sai0_sw, sai0_gate, sai0_div, sai0_clk,
+	sai1_sw, sai1_gate, sai1_div, sai1_clk,
+	sai2_sw, sai2_gate, sai2_div, sai2_clk,
+	sai3_sw, sai3_gate, sai3_div, sai3_clk,
+	usbc0_clk, usbc1_clk,
+	qspi0_sw, qspi0_gate, qspi0_x4_div, qspi0_x2_div, qspi0_x1_div,
+	qspi1_sw, qspi1_gate, qspi1_x4_div, qspi1_x2_div, qspi1_x1_div,
+	qspi0_clk, qspi1_clk,
+	nfc_sw, nfc_gate, nfc_pre_div, nfc_frac_div, nfc_inv, nfc_clk,
+	vadc_sw, vadc_gate, vadc_div, vadc_div_half, vadc_clk,
+	adc0_clk, adc1_clk, dac0_clk, dac1_clk,
+	flexcan0_clk, flexcan1_clk,
+	asrc_clk,
+	gpu_sw, gpu_gate, gpu2d_clk,
+	clk_max
+};
+
+static struct clk_div_table pll4_main_div_table[] = {
+	[0] = {.val = 0, .div = 1},
+	[1] = {.val = 1, .div = 2},
+	[2] = {.val = 2, .div = 6},
+	[3] = {.val = 3, .div = 8},
+	[4] = {.val = 4, .div = 10},
+	[5] = {.val = 5, .div = 12},
+	[6] = {.val = 6, .div = 14},
+	[7] = {.val = 7, .div = 16},
+};
+static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
+
+int __init mvf_clocks_init(void)
+{
+	struct device_node *np;
+
+	clk[dummy] = imx_clk_fixed("dummy", 0);
+	clk[sirc_128k] = imx_clk_fixed("sirc_128k", 128000); /* slow internal IRC */
+	clk[sirc_32k] = imx_clk_fixed("sirc_32k", 32000); /* slow internal IRC */
+	clk[firc] = imx_clk_fixed("firc", 24000000); /* fast internal IRC */
+	clk[sxosc] = imx_clk_fixed("sxosc", 32000); /* fixed 32k external osc */
+
+	for_each_compatible_node(np, NULL, "fixed-clock") {
+		u32 rate;
+
+		if (of_property_read_u32(np, "clock-frequency", &rate))
+			continue;
+		else if (of_device_is_compatible(np, "fsl,mvf-osc"))
+			clk[fxosc] = imx_clk_fixed("fxosc", rate);
+		else if (of_device_is_compatible(np, "fsl,mvf-audio-ext-clk"))
+			clk[audio_ext] = imx_clk_fixed("audio_ext", rate);
+		else if (of_device_is_compatible(np, "fsl,mvf-enet-ext-clk"))
+			clk[enet_ext] = imx_clk_fixed("enet_ext", rate);
+	}
+
+	/* default to 24Mhz OSC */
+	if (!clk[fxosc])
+		clk[fxosc] = imx_clk_fixed("fxosc", 24000000);
+
+	clk[fxosc_half] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-anatop");
+	anatop_base = of_iomap(np, 0);
+	WARN_ON(!anatop_base);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-ccm");
+	ccm_base = of_iomap(np, 0);
+	WARN_ON(!ccm_base);
+
+	clk[slow_clk] = imx_clk_mux("slow_clk", CCM_CCSR, 4, 1,
+				slow_clk_sel, ARRAY_SIZE(slow_clk_sel));
+	clk[fast_clk] = imx_clk_mux("fast_clk", CCM_CCSR, 5, 1,
+				fast_clk_sel, ARRAY_SIZE(fast_clk_sel));
+
+	clk[pll1_main_528m] = imx_clk_fixed_factor("pll1_main",	"fast_clk", 22, 1);
+	clk[pll1_pfd1_500m] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_528SYS_BASE, 0);
+	clk[pll1_pfd2_452m] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_528SYS_BASE, 1);
+	clk[pll1_pfd3_396m] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_528SYS_BASE, 2);
+	clk[pll1_pfd4_528m] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_528SYS_BASE, 3);
+
+	clk[pll2_main_528m] = imx_clk_fixed_factor("pll2_main", "fast_clk", 22, 1);
+	clk[pll2_pfd1_500m] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_528_BASE, 0);
+	clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_528_BASE, 1);
+	clk[pll2_pfd3_339m] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_528_BASE, 2);
+	clk[pll2_pfd4_413m] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_528_BASE, 3);
+
+	clk[pll3_main_480m] = imx_clk_fixed_factor("pll3_main", "fast_clk", 20, 1);
+	clk[pll4_main] = imx_clk_fixed_factor("pll4_main", "fast_clk", 25, 1);
+	/* Enet pll: fixed 50Mhz */
+	clk[pll5_main] = imx_clk_fixed_factor("pll5_main", "fast_clk", 125, 6);
+	clk[enet_50m] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
+	clk[enet_25m] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+	/* Video pll: default 960Mhz */
+	clk[pll6_main] = imx_clk_fixed_factor("pll6_main", "fast_clk", 40, 1);
+	clk[pll1_sw] = imx_clk_mux("pll1_sw", CCM_CCSR, 16, 3, pll1_pfd_sel, 5);
+	clk[pll2_sw] = imx_clk_mux("pll2_sw", CCM_CCSR, 19, 3, pll2_pfd_sel, 5);
+	clk[sys_sw] = imx_clk_mux("sys_sw", CCM_CCSR, 0, 3, sys_clk_sel, ARRAY_SIZE(sys_clk_sel));
+	clk[ddr_sw] = imx_clk_mux("ddr_sw", CCM_CCSR, 6, 1, ddr_clk_sel, ARRAY_SIZE(ddr_clk_sel));
+	clk[sys_bus_clk] = imx_clk_divider("sys_bus", "sys_sw", CCM_CACRR, 0, 3);
+	clk[platform_bus_clk] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
+	clk[ipg_bus_clk] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
+
+	clk[pll3_main_div] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
+	clk[pll4_main_div] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0,
+			CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
+	clk[pll6_main_div] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+
+	clk[usbc0_clk] = imx_clk_gate2("usbc0_clk", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
+	clk[usbc1_clk] = imx_clk_gate2("usbc1_clk", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+
+	clk[qspi0_sw] = imx_clk_mux("qspi0_sw", CCM_CSCMR1, 22, 2, qspi_clk_sel, 4);
+	clk[qspi0_x4_div] = imx_clk_divider("qspi0_x4", "qspi0_sw", CCM_CSCDR3, 0, 2);
+	clk[qspi0_x2_div] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
+	clk[qspi0_x1_div] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
+	clk[qspi0_gate] = imx_clk_gate("qspi0_gate", "qspi0_x1", CCM_CSCDR3, 4);
+	clk[qspi0_clk] = imx_clk_gate2("qspi0_clk", "qspi0_en", CCM_CCGR2, CCM_CCGRx_CGn(4));
+
+	clk[qspi1_sw] = imx_clk_mux("qspi1_sw", CCM_CSCMR1, 24, 2, qspi_clk_sel, 4);
+	clk[qspi1_x4_div] = imx_clk_divider("qspi1_x4", "qspi1_sw", CCM_CSCDR3, 8, 2);
+	clk[qspi1_x2_div] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
+	clk[qspi1_x1_div] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
+	clk[qspi1_gate] = imx_clk_gate("qspi1_gate", "qspi1_x1", CCM_CSCDR3, 12);
+	clk[qspi1_clk] = imx_clk_gate2("qspi1_clk", "qspi1_en", CCM_CCGR8, CCM_CCGRx_CGn(4));
+
+	clk[enet_clk_sw] = imx_clk_mux("enet_sw", CCM_CSCMR2, 4, 2, rmii_clk_sel, 4);
+	clk[enet_ts_sw] = imx_clk_mux("enet_ts_sw", CCM_CSCMR2, 0, 3, enet_ts_clk_sel, 7);
+	clk[enet_clk] = imx_clk_gate("enet_clk", "enet_sw", CCM_CSCDR1, 24);
+	clk[enet_ts] = imx_clk_gate("enet_ts_clk", "enet_ts_sw", CCM_CSCDR1, 23);
+
+	clk[pit_clk] = imx_clk_gate2("pit_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
+
+	clk[uart0_clk] = imx_clk_gate2("uart0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
+	clk[uart1_clk] = imx_clk_gate2("uart1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
+	clk[uart2_clk] = imx_clk_gate2("uart2_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
+	clk[uart3_clk] = imx_clk_gate2("uart3_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
+
+	clk[i2c0_clk] = imx_clk_gate2("i2c0_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
+	clk[i2c1_clk] = imx_clk_gate2("i2c1_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
+
+	clk[dspi0_clk] = imx_clk_gate2("dspi0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
+	clk[dspi1_clk] = imx_clk_gate2("dspi1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
+	clk[dspi2_clk] = imx_clk_gate2("dspi2_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
+	clk[dspi3_clk] = imx_clk_gate2("dspi3_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
+
+	clk[wdt_clk] = imx_clk_gate2("wdt_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
+
+	clk[esdhc0_sw] = imx_clk_mux("esdhc0_sw", CCM_CSCMR1, 16, 2, esdhc_clk_sel, 4);
+	clk[esdhc0_gate] = imx_clk_gate("esdhc0_gate", "esdhc0_sw", CCM_CSCDR2, 28);
+	clk[esdhc0_div] = imx_clk_divider("esdhc0_div", "esdhc0_gate", CCM_CSCDR2, 16, 4);
+	clk[esdhc0_clk] = imx_clk_gate2("eshc0_clk", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
+
+	clk[esdhc1_sw] = imx_clk_mux("esdhc1_sw", CCM_CSCMR1, 18, 2, esdhc_clk_sel, 4);
+	clk[esdhc1_gate] = imx_clk_gate("esdhc1_gate", "esdhc1_sw", CCM_CSCDR2, 29);
+	clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc1_gate", CCM_CSCDR2, 20, 4);
+	clk[esdhc1_clk] = imx_clk_gate2("eshc1_clk", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
+
+	/*
+	 * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
+	 * selectable clock source, both use a common gate bit
+	 * in CCM_CSCDR1, select "dummy" as "ftm0_ext_fix_gate"
+	 * parent make the gate doesn't provids any clock freq
+	 * except for gate/ungate.
+	 */
+	clk[ftm0_ext_sw] = imx_clk_mux("ftm0_ext_sw", CCM_CSCMR2, 6, 2, ftm_ext_clk_sel, 4);
+	clk[ftm0_fix_sw] = imx_clk_mux("ftm0_fix_sw", CCM_CSCMR2, 14, 1, ftm_fix_clk_sel, 2);
+	clk[ftm0_ext_fix_gate] = imx_clk_gate("ftm0_ext_fix_gate", "dummy", CCM_CSCDR1, 25);
+	/* ftm(n)_clk are FTM module operation clock */
+	clk[ftm0_clk] = imx_clk_gate2("ftm0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
+	clk[ftm1_clk] = imx_clk_gate2("ftm1_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
+	clk[ftm2_clk] = imx_clk_gate2("ftm2_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
+	clk[ftm3_clk] = imx_clk_gate2("ftm3_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
+
+	clk[dcu0_sw] = imx_clk_mux("dcu0_sw", CCM_CSCMR1, 28, 1, dcu_clk_sel, 2);
+	clk[dcu0_gate] = imx_clk_gate("dcu0_gate", "dcu0_sw", CCM_CSCDR3, 19);
+	clk[dcu0_div] = imx_clk_divider("dcu0_div", "dcu0_gate", CCM_CSCDR3, 16, 3);
+	clk[dcu0_clk] = imx_clk_gate2("dcu0_clk", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+	clk[dcu1_sw] = imx_clk_mux("dcu1_sw", CCM_CSCMR1, 29, 1, dcu_clk_sel, 2);
+	clk[dcu1_gate] = imx_clk_gate("dcu1_gate", "dcu1_sw", CCM_CSCDR3, 23);
+	clk[dcu1_div] = imx_clk_divider("dcu1_div", "dcu1_gate", CCM_CSCDR3, 20, 3);
+	clk[dcu1_clk] = imx_clk_gate2("dcu1_clk", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+
+	clk[esai_sw] = imx_clk_mux("esai_sw", CCM_CSCMR1, 20, 2, esai_clk_sel, 4);
+	clk[esai_gate] = imx_clk_gate("esai_gate", "esai_sw", CCM_CSCDR2, 30);
+	clk[esai_div] = imx_clk_divider("esai_div", "esai_gate", CCM_CSCDR2, 24, 4);
+	clk[esai_clk] = imx_clk_gate2("esai_clk", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
+
+	clk[sai0_sw] = imx_clk_mux("sai0_sw", CCM_CSCMR1, 0, 2, sai_clk_sel, 4);
+	clk[sai0_gate] = imx_clk_gate("sai0_gate", "sai0_sw", CCM_CSCDR1, 16);
+	clk[sai0_div] = imx_clk_divider("sai0_div", "sai0_gate", CCM_CSCDR1, 0, 4);
+	clk[sai0_clk] = imx_clk_gate2("sai0_clk", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
+
+	clk[sai1_sw] = imx_clk_mux("sai1_sw", CCM_CSCMR1, 2, 2, sai_clk_sel, 4);
+	clk[sai1_gate] = imx_clk_gate("sai1_gate", "sai1_sw", CCM_CSCDR1, 17);
+	clk[sai1_div] = imx_clk_divider("sai1_div", "sai1_gate", CCM_CSCDR1, 4, 4);
+	clk[sai1_clk] = imx_clk_gate2("sai1_clk", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
+
+	clk[sai2_sw] = imx_clk_mux("sai2_sw", CCM_CSCMR1, 4, 2, sai_clk_sel, 4);
+	clk[sai2_gate] = imx_clk_gate("sai2_gate", "sai2_sw", CCM_CSCDR1, 18);
+	clk[sai2_div] = imx_clk_divider("sai2_div", "sai2_gate", CCM_CSCDR1, 8, 4);
+	clk[sai2_clk] = imx_clk_gate2("sai2_clk", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
+
+	clk[sai3_sw] = imx_clk_mux("sai3_sw", CCM_CSCMR1, 6, 2, sai_clk_sel, 4);
+	clk[sai3_gate] = imx_clk_gate("sai3_gate", "sai3_sw", CCM_CSCDR1, 19);
+	clk[sai3_div] = imx_clk_divider("sai3_div", "sai3_gate", CCM_CSCDR1, 12, 4);
+	clk[sai3_clk] = imx_clk_gate2("sai3_clk", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
+
+	clk[nfc_sw] = imx_clk_mux("nfc_sw", CCM_CSCMR1, 12, 2, nfc_clk_sel, 4);
+	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_sw", CCM_CSCDR2, 9);
+	clk[nfc_pre_div] = imx_clk_divider("nfc_pre_div", "nfc_gate", CCM_CSCDR3, 13, 3);
+	clk[nfc_frac_div] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
+	clk[nfc_clk] = imx_clk_gate2("nfc_clk", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
+
+	clk[gpu_sw] = imx_clk_mux("gpu_sw", CCM_CSCMR1, 14, 1, gpu_clk_sel, 2);
+	clk[gpu_gate] = imx_clk_gate("gpu_gate", "gpu_sw", CCM_CSCDR2, 10);
+	clk[gpu2d_clk] = imx_clk_gate2("gpu_clk", "gpu_gate", CCM_CCGR8, CCM_CCGRx_CGn(15));
+
+	clk[vadc_sw] = imx_clk_mux("vadc_sw", CCM_CSCMR1, 8, 2, vadc_clk_sel, 3);
+	clk[vadc_gate] = imx_clk_gate("vadc_gate", "vadc_sw", CCM_CSCDR1, 22);
+	clk[vadc_div] = imx_clk_divider("vadc_div", "vadc_gate", CCM_CSCDR1, 20, 2);
+	clk[vadc_div_half] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
+	clk[vadc_clk] = imx_clk_gate2("vadc_clk", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
+
+	clk[adc0_clk] = imx_clk_gate2("adc0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
+	clk[adc1_clk] = imx_clk_gate2("adc1_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
+	clk[dac0_clk] = imx_clk_gate2("dac0_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
+	clk[dac1_clk] = imx_clk_gate2("dac1_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
+
+	clk[asrc_clk] = imx_clk_gate2("asrc_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
+
+	clk[flexcan0_clk] = imx_clk_gate2("flexcan0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
+	clk[flexcan1_clk] = imx_clk_gate2("flexcan1_clk", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+
+	clk_set_parent(clk[qspi0_sw], clk[pll1_pfd4_528m]);
+	clk_set_rate(clk[qspi0_x4_div],	clk_get_rate(clk[qspi0_x4_div]->parent) / 2);
+	clk_set_rate(clk[qspi0_x2_div],	clk_get_rate(clk[qspi0_x2_div]->parent) / 2);
+	clk_set_rate(clk[qspi0_x1_div],	clk_get_rate(clk[qspi0_x1_div]->parent) / 2);
+
+	clk_set_parent(clk[qspi1_sw], clk[pll1_pfd4_528m]);
+	clk_set_rate(clk[qspi1_x4_div], clk_get_rate(clk[qspi1_x4_div]->parent) / 2);
+	clk_set_rate(clk[qspi1_x2_div], clk_get_rate(clk[qspi1_x2_div]->parent) / 2);
+	clk_set_rate(clk[qspi1_x1_div], clk_get_rate(clk[qspi1_x1_div]->parent) / 2);
+
+	clk_set_parent(clk[sai0_gate], clk[audio_ext]);
+	clk_set_parent(clk[sai1_gate], clk[audio_ext]);
+	clk_set_parent(clk[sai2_gate], clk[audio_ext]);
+	clk_set_parent(clk[sai3_gate], clk[audio_ext]);
+
+	/* Add the clocks to provider list */
+	clk_data.clks = clk;
+	clk_data.clk_num = ARRAY_SIZE(clk);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4cba7db..683c4f4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,6 +68,7 @@ extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
+extern int mvf_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
diff --git a/arch/arm/mach-imx/mach-mvf600.c b/arch/arm/mach-imx/mach-mvf600.c
new file mode 100644
index 0000000..56d3fb0
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mvf600.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clocksource.h>
+#include <linux/platform_device.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/memory.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/system_misc.h>
+
+#include "common.h"
+
+
+void mvf_restart(char mode, const char *cmd)
+{
+	struct device_node *np;
+	void __iomem *wdog_base;
+	struct clk *wdog_clk;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt");
+	wdog_base = of_iomap(np, 0);
+	if (!wdog_base)
+		goto soft;
+
+	wdog_clk = of_clk_get_by_name(np, "wdog");
+	if (!IS_ERR(wdog_clk))
+		clk_prepare_enable(wdog_clk);
+
+	/* enable wdog */
+	writew_relaxed(1 << 2, wdog_base);
+
+	/* wait for reset to assert ... */
+	mdelay(500);
+
+	pr_err("Watchdog reset failed to assert reset\n");
+
+	/* delay to allow the serial port to show the message */
+	mdelay(50);
+
+soft:
+	/* we'll take a jump through zero as a poor second */
+	soft_restart(0);
+}
+
+static void __init mvf_init_machine(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init mvf_of_init_irq(void)
+{
+	struct device_node *np;
+	void __iomem *mscm_base;
+	int i;
+
+	l2x0_of_init(0, ~0UL);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-mscm");
+	mscm_base = of_iomap(np, 0);
+	if (!mscm_base)
+		return;
+
+	/* route each shared peripheral interrupt to CP0 */
+	for (i = 0; i < 111; i++)
+		__raw_writew(1, mscm_base + 0x880 + 2 * i);
+
+	iounmap(mscm_base);
+
+	irqchip_init();
+}
+
+static void __init mvf_timer_init(void)
+{
+	mvf_clocks_init();
+	clocksource_of_init();
+}
+
+/*
+ * initialize __mach_desc_ data structure.
+ */
+static const char *mvf_dt_compat[] __initdata = {
+	"fsl,mvf600",
+	NULL,
+};
+
+DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid Family (Device Tree)")
+	.init_irq	= mvf_of_init_irq,
+	.init_machine	= mvf_init_machine,
+	.init_time	= mvf_timer_init,
+	.dt_compat	= mvf_dt_compat,
+	.restart	= mvf_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/pit.c b/arch/arm/mach-imx/pit.c
new file mode 100644
index 0000000..e2df0e5
--- /dev/null
+++ b/arch/arm/mach-imx/pit.c
@@ -0,0 +1,244 @@
+/*
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+
+
+#define PITMCR		0x00
+#define PITLTMR64H	0xE0
+#define PITLTMR64L	0xE4
+
+#define PITLDVAL	0x00
+#define PITCVAL		0x04
+#define PITTCTRL	0x08
+#define PITTFLG		0x0C
+
+/*
+ * Vybrid has 8 pit timers: pit0 - pit7,
+ * Each memory mapped register occupy 0x10 Bytes
+ */
+#define PITOFFSET0	0x100
+#define PITOFFSETx(n)	(PITOFFSET0 + 0x10 * n)
+
+/* bit definitation */
+#define PITMCR_MDIS		(1 << 1)
+#define PITMCR_FRZ		(1 << 0)
+
+#define PITTCTRL_TEN		(1 << 0)
+#define PITTCTRL_TIE		(1 << 1)
+#define	PITCTRL_CHN		(1 << 2)
+
+#define PITTFLG_TIF		0x1
+
+static struct clock_event_device clockevent_pit;
+static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+static void __iomem *clksrc_base;
+static void __iomem *clkevt_base;
+static void __iomem *sched_clock_reg;
+static unsigned long pit_cycle_per_jiffy;
+
+static inline void pit_timer_enable(void)
+{
+	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_timer_disable(void)
+{
+	__raw_writel(0, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_disable(void)
+{
+	unsigned long val;
+
+	val = __raw_readl(clkevt_base + PITTCTRL);
+	val &= ~PITTCTRL_TIE;
+	__raw_writel(val, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_enable(void)
+{
+	unsigned long val;
+
+	val = __raw_readl(clkevt_base + PITTCTRL);
+	val |= PITTCTRL_TIE;
+	__raw_writel(val, clkevt_base + PITTCTRL);
+}
+
+static void pit_irq_acknowledge(void)
+{
+	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+}
+
+static unsigned int mvf_read_sched_clock(void)
+{
+	return __raw_readl(sched_clock_reg);
+}
+
+
+static int __init pit_clocksource_init(struct clk *pit_clk)
+{
+	unsigned int c = clk_get_rate(pit_clk);
+
+	sched_clock_reg = clksrc_base + PITCVAL;
+
+	setup_sched_clock(mvf_read_sched_clock, 32, c);
+	return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, 32,
+			clocksource_mmio_readl_down);
+}
+
+/* set clock event */
+static int pit_set_next_event(unsigned long delta,
+				struct clock_event_device *unused)
+{
+	pit_timer_disable();
+	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
+	pit_irq_acknowledge();
+	pit_timer_enable();
+
+	return 0;
+}
+
+static void pit_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	pit_timer_disable();
+	pit_irq_acknowledge();
+
+	/* Remember timer mode */
+	clockevent_mode = mode;
+	local_irq_restore(flags);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+
+		__raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
+		pit_timer_enable();
+
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+
+		break;
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_RESUME:
+
+		break;
+	default:
+		WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
+		break;
+	}
+}
+
+/*
+ * interrupt handler for the timer
+ */
+static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = &clockevent_pit;
+
+	pit_irq_acknowledge();
+
+	if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT)
+		pit_timer_disable();
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction pit_timer_irq = {
+	.name		= "MVF PIT Timer Tick",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= pit_timer_interrupt,
+};
+
+static struct clock_event_device clockevent_pit = {
+	.name		= "pit",
+	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode	= pit_set_mode,
+	.set_next_event	= pit_set_next_event,
+	.rating		= 300,
+};
+
+static int __init pit_clockevent_init(struct clk *pit_clk)
+{
+	unsigned int c = clk_get_rate(pit_clk);
+
+	clockevent_pit.cpumask = cpumask_of(0);
+	clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00);
+
+	return 0;
+}
+
+static void __init pit_timer_init(struct device_node *np)
+{
+	struct clk *pit_clk;
+	void __iomem *timer_base;
+	int irq;
+
+	if (!np) {
+		pr_err("Failed to find pit DT node\n");
+		BUG();
+	}
+
+	timer_base = of_iomap(np, 0);
+	WARN_ON(!timer_base);
+
+	/* chose PIT2 as clocksource, PIT3 as clockevent dev */
+	clksrc_base = timer_base + PITOFFSETx(2);
+	clkevt_base = timer_base + PITOFFSETx(3);
+
+	irq = irq_of_parse_and_map(np, 0);
+
+	pit_clk = of_clk_get_by_name(np, "pit");
+	if (IS_ERR(pit_clk)) {
+		pr_err("Vybrid PIT timer: unable to get clk\n");
+		return;
+	}
+
+	clk_prepare_enable(pit_clk);
+
+	pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
+
+	/*
+	 * Initialise to a known state (all timers off, and timing reset)
+	 */
+	__raw_writel(0x0, timer_base + PITMCR);
+
+	__raw_writel(0, clkevt_base + PITTCTRL);
+	__raw_writel(0xffffffff, clkevt_base + PITLDVAL);
+
+	__raw_writel(0, clksrc_base + PITTCTRL);
+	__raw_writel(0xffffffff, clksrc_base + PITLDVAL);
+	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
+
+	pit_clocksource_init(pit_clk);
+
+	setup_irq(irq, &pit_timer_irq);
+
+	pit_clockevent_init(pit_clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf-pit", pit_timer_init);
-- 
1.8.0




From Ian.Campbell at citrix.com  Thu May  2 04:21:02 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 2 May 2013 09:21:02 +0100
Subject: [Xen-devel] [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <1367482862.21869.28.camel@zakaz.uk.xensource.com>

On Wed, 2013-05-01 at 20:27 +0100, Stefano Stabellini wrote:
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index d30042e..8f040a0 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -14,6 +14,7 @@
>  #include <xen/xen-ops.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
> +#include <asm/arch_timer.h>
>  #include <asm/system_misc.h>
>  #include <linux/interrupt.h>
>  #include <linux/irqreturn.h>
> @@ -172,6 +173,8 @@ static int __init xen_secondary_init(unsigned int cpu)
>  		   later ones fail to. */
>  		per_cpu(xen_vcpu, cpu) = vcpup;
>  	}
> +
> +	xen_setup_runstate_info(cpu);

Is this called for the boot processor too?

(do you have a linux-next branch where I can easily find the baseline
for this series?)

Ian.



From b35083 at freescale.com  Thu May  2 03:38:05 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 2 May 2013 15:38:05 +0800
Subject: [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid
In-Reply-To: <1367480285-26159-1-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
Message-ID: <1367480285-26159-3-git-send-email-b35083@freescale.com>

This patch adds basic device tree source for Freescale
Vybrid Family MVF600 platform and Tower development board.

Signed-off-by: Xiaochun Li <b41219 at freescale.com>
Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
V2:
  Add pinctrl support based on IMX new pinctrl framework

 arch/arm/boot/dts/Makefile         |   3 +-
 arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mvf600-twr.dts   |  80 ++++
 arch/arm/boot/dts/mvf600.dtsi      | 426 +++++++++++++++++++
 4 files changed, 1324 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
 create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
 create mode 100644 arch/arm/boot/dts/mvf600.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8fd41b3..6402f21 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6q-sabreauto.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
-	imx6q-sbc6x.dtb
+	imx6q-sbc6x.dtb \
+	mvf600-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx23-olinuxino.dtb \
 	imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h
new file mode 100644
index 0000000..9fbc7a9
--- /dev/null
+++ b/arch/arm/boot/dts/mvf600-pinfunc.h
@@ -0,0 +1,816 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_MVF600_PINFUNC_H
+#define __DTS_MVF600_PINFUNC_H
+
+/*
+ * Macro definations for MVF600 pin functions
+ *
+ * On Vybrid,pin's mux mode and pad control are in one 32-bit register.
+ * mux mode bits occupy bit[20:22] and pad config bits occupy bit[[0:15].
+ * So the config word is a combination of mux mode and control config value.
+ * imx common pinctrl driver requires a tuple of six elements to
+ * describe a pin. The tuple for MVF600 is as below:
+ * <mux_reg conf_reg input_reg mux_mode|conf_val input_val mux_mode|conf_val>
+ */
+
+#define ALT0	0x000000
+#define ALT1	0x100000
+#define ALT2	0x200000
+#define ALT3	0x300000
+#define ALT4	0x400000
+#define ALT5	0x500000
+#define ALT6	0x600000
+#define ALT7	0x700000
+
+
+#define MVF600_PAD_PTA6__GPIO_0(c)		0x000 0x000 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA6__RMII_CLKOUT(c)		0x000 0x000 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA6__RMII_CLKIN(c)		0x000 0x000 0x2F0 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA6__DCU1_TCON11(c)		0x000 0x000 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA6__DCU1_R2(c)		0x000 0x000 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA8__GPIO_1(c)		0x004 0x004 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA8__TCLK(c)		0x004 0x004 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA8__DCU0_R0(c)		0x004 0x004 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA8__MLB_CLK(c)		0x004 0x004 0x354 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA9__GPIO_2(c)		0x008 0x008 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA9__TDI(c)			0x008 0x008 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA9__RMII_CLKOUT(c)		0x008 0x008 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA9__RMII_CLKIN(c)		0x008 0x008 0x2F0 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA9__DCU0_R1(c)		0x008 0x008 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA9__WDOG_B(c)		0x008 0x008 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA10__GPIO_3(c)		0x00C 0x00C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA10__TDO(c)		0x00C 0x00C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA10__EXT_AUDIO_MCLK(c)	0x00C 0x00C 0x2EC (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA10__DCU0_G0(c)		0x00C 0x00C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA10__ENET_TS_CLKIN(c)	0x00C 0x00C 0x2F4 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA10__MLB_SIGNAL(c)		0x00C 0x00C 0x35C (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA11__GPIO_4(c)		0x010 0x010 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA11__TMS(c)		0x010 0x010 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA11__DCU0_G1(c)		0x010 0x010 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA11__MLB_DATA(c)		0x010 0x010 0x358 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA12__GPIO_5(c)		0x014 0x014 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA12__TRACECK(c)		0x014 0x014 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA12__EXT_AUDIO_MCLK(c)	0x014 0x014 0x2EC (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA12__VIU_DATA13(c)		0x014 0x014 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA12__I2C0_SCL(c)		0x014 0x014 0x33C (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA16__GPIO_6(c)		0x018 0x018 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA16__TRACED0(c)		0x018 0x018 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA16__USB0_VBUS_EN(c)	0x018 0x018 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA16__ADC1_SE0(c)		0x018 0x018 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA16__LCD29(c)		0x018 0x018 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA16__SAI2_TX_BCLK(c)	0x018 0x018 0x370 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA16__VIU_DATA14(c)		0x018 0x018 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA16__I2C0_SDA(c)		0x018 0x018 0x340 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA17__GPIO_7(c)		0x01C 0x01C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA17__TRACED1(c)		0x01C 0x01C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA17__USB0_VBUS_OC(c)	0x01C 0x01C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA17__ADC1_SE1(c)		0x01C 0x01C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA17__LCD30(c)		0x01C 0x01C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA17__USB0_SOF_PULSE(c)	0x01C 0x01C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA17__VIU_DATA15(c)		0x01C 0x01C 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA17__I2C1_SCL(c)		0x01C 0x01C 0x344 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA18__GPIO_8(c)		0x020 0x020 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA18__TRACED2(c)		0x020 0x020 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA18__ADC0_SE0(c)		0x020 0x020 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA18__FTM1_QD_PHA(c)	0x020 0x020 0x334 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA18__LCD31(c)		0x020 0x020 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA18__SAI2_TX_DATA(c)	0x020 0x020 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA18__VIU_DATA16(c)		0x020 0x020 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA18__I2C1_SDA(c)		0x020 0x020 0x348 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA19__GPIO_9(c)		0x024 0x024 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA19__TRACED3(c)		0x024 0x024 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA19__ADC0_SE1(c)		0x024 0x024 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA19__FTM1_QD_PHB(c)	0x024 0x024 0x338 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA19__LCD32(c)		0x024 0x024 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA19__SAI2_TX_SYNC(c)	0x024 0x024 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA19__VIU_DATA17(c)		0x024 0x024 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA19__QSPI1_A_QSCK(c)	0x024 0x024 0x374 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA20__GPIO_10(c)		0x028 0x028 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA20__TRACED4(c)		0x028 0x028 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA20__LCD33(c)		0x028 0x028 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA20__UART3_TX(c)		0x028 0x028 0x394 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA20__DCU1_HSYNC(c)		0x028 0x028 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA21__GPIO_11(c)		0x02C 0x02C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA21__TRACED5(c)		0x02C 0x02C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA21__SAI2_RX_BCLK(c)	0x02C 0x02C 0x364 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA21__UART3_RX(c)		0x02C 0x02C 0x390 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA21__DCU1_VSYNC(c)		0x02C 0x02C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA22__GPIO_12(c)		0x030 0x030 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA22__TRACED6(c)		0x030 0x030 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA22__SAI2_RX_DATA(c)	0x030 0x030 0x368 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA22__I2C2_SCL(c)		0x030 0x030 0x34C (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA22__DCU1_TAG(c)		0x030 0x030 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA23__GPIO_13(c)		0x034 0x034 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA23__TRACED7(c)		0x034 0x034 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA23__SAI2_RX_SYNC(c)	0x034 0x034 0x36C (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA23__I2C2_SDA(c)		0x034 0x034 0x350 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA23__DCU1_DE(c)		0x034 0x034 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA24__GPIO_14(c)		0x038 0x038 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA24__TRACED8(c)		0x038 0x038 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA24__USB1_VBUS_EN(c)	0x038 0x038 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA24__ESDHC1_CLK(c)		0x038 0x038 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA24__DCU1_TCON4(c)		0x038 0x038 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA24__DDR_TEST_PAD_CTRL(c)	0x038 0x038 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA25__GPIO_15(c)		0x03C 0x03C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA25__TRACED9(c)		0x03C 0x03C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA25__USB1_VBUS_OC(c)	0x03C 0x03C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA25__ESDHC1_CMD(c)		0x03C 0x03C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA25__DCU1_TCON5(c)		0x03C 0x03C 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA26__GPIO_16(c)		0x040 0x040 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA26__TRACED10(c)		0x040 0x040 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA26__SAI3_TX_BCLK(c)	0x040 0x040 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA26__ESDHC1_DAT0(c)	0x040 0x040 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA26__DCU1_TCON6(c)		0x040 0x040 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA27__GPIO_17(c)		0x044 0x044 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA27__TRACED11(c)		0x044 0x044 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA27__SAI3_RX_BCLK(c)	0x044 0x044 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA27__ESDHC1_DAT1(c)	0x044 0x044 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA27__DCU1_TCON7(c)		0x044 0x044 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA28__GPIO_18(c)		0x048 0x048 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA28__TRACED12(c)		0x048 0x048 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA28__SAI3_RX_DATA(c)	0x048 0x048 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA28__ENET1_1588_TMR0(c)	0x048 0x048 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA28__UART4_TX(c)		0x048 0x048 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA28__ESDHC1_DATA2(c)	0x048 0x048 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA28__DCU1_TCON8(c)		0x048 0x048 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA29__GPIO_19(c)		0x04C 0x04C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA29__TRACED13(c)		0x04C 0x04C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA29__SAI3_TX_DATA(c)	0x04C 0x04C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA29__ENET1_1588_TMR1(c)	0x04C 0x04C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA29__UART4_RX(c)		0x04C 0x04C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA29__ESDHC1_DAT3(c)	0x04C 0x04C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA29__DCU1_TCON9(c)		0x04C 0x04C 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTA30__GPIO_20(c)		0x050 0x050 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA30__TRACED14(c)		0x050 0x050 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA30__SAI3_RX_SYNC(c)	0x050 0x050 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA30__ENET1_1588_TMR2(c)	0x050 0x050 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA30__UART4_RTS(c)		0x050 0x050 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA30__I2C3_SCL(c)		0x050 0x050 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA30__UART3_TX(c)		0x050 0x050 0x394 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA31__GPIO_21(c)		0x054 0x054 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA31__TRACED15(c)		0x054 0x054 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTA31__SAI3_TX_SYNC(c)	0x054 0x054 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTA31__ENET1_1588_TMR3(c)	0x054 0x054 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTA31__UART4_CTS(c)		0x054 0x054 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTA31__I2C3_SDA(c)		0x054 0x054 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTA31__UART3_RX(c)		0x054 0x054 0x390 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB0__GPIO_22(c)		0x058 0x058 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB0__FTM0_CH0(c)		0x058 0x058 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB0__ADC0_SE2(c)		0x058 0x058 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB0__TRACE_CTL(c)		0x058 0x058 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB0__LCD34(c)		0x058 0x058 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB0__SAI2_RX_BCLK(c)	0x058 0x058 0x364 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB0__VIU_DATA18(c)		0x058 0x058 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB0__QSPI1_A_QPCS0(c)	0x058 0x058 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB1__GPIO_23(c)		0x05C 0x05C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB1__FTM0_CH1(c)		0x05C 0x05C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB1__ADC0_SE3(c)		0x05C 0x05C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB1__SRC_RCON30(c)		0x05C 0x05C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB1__LCD35(c)		0x05C 0x05C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB1__SAI2_RX_DATA(c)	0x05C 0x05C 0x368 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB1__VIU_DATA19(c)		0x05C 0x05C 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB1__QSPI1_A_DATA3(c)	0x05C 0x05C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB2__GPIO_24(c)		0x060 0x060 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB2__FTM0_CH2(c)		0x060 0x060 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB2__ADC1_SE2(c)		0x060 0x060 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB2__SRC_RCON31(c)		0x060 0x060 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB2__LCD36(c)		0x060 0x060 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB2__SAI2_RX_SYNC(c)	0x060 0x060 0x36C (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB2__VIDEO_IN0_DATA20(c)	0x060 0x060 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB2__QSPI1_A_DATA2(c)	0x060 0x060 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB3__GPIO_25(c)		0x064 0x064 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB3__FTM0_CH3(c)		0x064 0x064 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB3__ADC1_SE3(c)		0x064 0x064 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB3__PDB_EXTRIG(c)		0x064 0x064 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB3__LCD37(c)		0x064 0x064 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB3__VIU_DATA21(c)		0x064 0x064 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB3__QSPI1_A_DATA1(c)	0x064 0x064 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB4__GPIO_26(c)		0x068 0x068 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB4__FTM0_CH4(c)		0x068 0x068 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB4__UART1_TX(c)		0x068 0x068 0x380 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB4__ADC0_SE4(c)		0x068 0x068 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB4__LCD38(c)		0x068 0x068 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB4__VIU_FID(c)		0x068 0x068 0x3A8 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB4__VIU_DATA22(c)		0x068 0x068 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB4__QSPI1_A_DATA0(c)	0x068 0x068 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB5__GPIO_27(c)		0x06C 0x06C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB5__FTM0_CH5(c)		0x06C 0x06C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB5__UART1_RX(c)		0x06C 0x06C 0x37C (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB5__ADC1_SE4(c)		0x06C 0x06C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB5__LCD39(c)		0x06C 0x06C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB5__VIU_DE(c)		0x06C 0x06C 0x3A4 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB5__QSPI1_A_DQS(c)		0x06C 0x06C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB6__GPIO_28(c)		0x070 0x070 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB6__FTM0_CH6(c)		0x070 0x070 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB6__UART1_RTS(c)		0x070 0x070 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB6__QSPI0_QPCS1_A(c)	0x070 0x070 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB6__LCD_LCD40(c)		0x070 0x070 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB6__FB_CLKOUT(c)		0x070 0x070 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB6__VIU_HSYNC(c)		0x070 0x070 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB6__UART2_TX(c)		0x070 0x070 0x38C (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB7__GPIO_29(c)		0x074 0x074 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB7__FTM0_CH7(c)		0x074 0x074 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB7__UART1_CTS(c)		0x074 0x074 0x378 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB7__QSPI0_B_QPCS1(c)	0x074 0x074 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB7__LCD41(c)		0x074 0x074 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB7__VIU_VSYNC(c)		0x074 0x074 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB7__UART2_RX(c)		0x074 0x074 0x388 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB8__GPIO_30(c)		0x078 0x078 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB8__FTM1_CH0(c)		0x078 0x078 0x32C (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB8__FTM1_QD_PHA(c)		0x078 0x078 0x334 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB8__VIU_DE(c)		0x078 0x078 0x3A4 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB8__DCU1_R6(c)		0x078 0x078 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB9__GPIO_31(c)		0x07C 0x07C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB9__FTM1_CH1(c)		0x07C 0x07C 0x330 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB9__FTM1_QD_PHB(c)		0x07C 0x07C 0x338 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB9__DCU1_R7(c)		0x07C 0x07C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB10__GPIO_32(c)		0x080 0x080 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB10__UART0_TX(c)		0x080 0x080 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB10__DCU0_TCON4(c)		0x080 0x080 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB10__VIU_DE(c)		0x080 0x080 0x3A4 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB10__CKO1(c)		0x080 0x080 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB10__ENET_TS_CLKIN(c)	0x080 0x080 0x2F4 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB11__GPIO_33(c)		0x084 0x084 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB11__UART0_RX(c)		0x084 0x084 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB11__DCU0_TCON5(c)		0x084 0x084 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB11__SNVS_ALARM_OUT_B(c)	0x084 0x084 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB11__CKO2(c)		0x084 0x084 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB11_ENET0_1588_TMR0(c)	0x084 0x084 0x304 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB12__GPIO_34(c)		0x088 0x088 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB12__UART0_RTS(c)		0x088 0x088 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB12__DSPI0_CS5(c)		0x088 0x088 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB12__DCU0_TCON6(c)		0x088 0x088 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB12__FB_AD1(c)		0x088 0x088 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB12__NMI(c)		0x088 0x088 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB12__ENET0_1588_TMR1(c)	0x088 0x088 0x308 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB13__GPIO_35(c)		0x08C 0x08C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB13__UART0_CTS(c)		0x08C 0x08C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB13__DSPI0_CS4(c)		0x08C 0x08C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB13__DCU0_TCON7(c)		0x08C 0x08C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB13__FB_AD0(c)		0x08C 0x08C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB13__TRACE_CTL(c)		0x08C 0x08C 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB14__GPIO_36(c)		0x090 0x090 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB14__CAN0_RX(c)		0x090 0x090 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB14__I2C0_SCL(c)		0x090 0x090 0x33C (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB14__DCU0_TCON8(c)		0x090 0x090 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB14__DCU1_PCLK(c)		0x090 0x090 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB15__GPIO_37(c)		0x094 0x094 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB15__CAN0_TX(c)		0x094 0x094 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB15__I2C0_SDA(c)		0x094 0x094 0x340 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB15__DCU0_TCON9(c)		0x094 0x094 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB15__VIU_PIX_CLK(c)	0x094 0x094 0x3AC (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB16__GPIO_38(c)		0x098 0x098 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB16__CAN1_RX(c)		0x098 0x098 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB16__I2C1_SCL(c)		0x098 0x098 0x344 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB16__DCU0_TCON10(c)	0x098 0x098 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB17__GPIO_39(c)		0x09C 0x09C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB17__CAN1_TX(c)		0x09C 0x09C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB17__I2C1_SDA(c)		0x09C 0x09C 0x348 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB17__DCU0_TCON11(c)	0x09C 0x09C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB18__GPIO_40(c)		0x0A0 0x0A0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB18__DSPI0_CS1(c)		0x0A0 0x0A0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB18__EXT_AUDIO_MCLK(c)	0x0A0 0x0A0 0x2EC (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB18__VIU_DATA9(c)		0x0A0 0x0A0 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB19__GPIO_41(c)		0x0A4 0x0A4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB19__DSPI0_CS0(c)		0x0A4 0x0A4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB19__VIU_DATA10(c)		0x0A4 0x0A4 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB20__GPIO_42(c)		0x0A8 0x0A8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB20__DSPI0_SIN(c)		0x0A8 0x0A8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB20__LCD42(c)		0x0A8 0x0A8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB20__VIU_DATA11(c)		0x0A8 0x0A8 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB21__GPIO_43(c)		0x0AC 0x0AC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB21__DSPI0_SOUT(c)		0x0AC 0x0AC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB21__LCD43(c)		0x0AC 0x0AC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB21__VIU_DATA12(c)		0x0AC 0x0AC 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB21__DCU1_PCLK(c)		0x0AC 0x0AC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB22__GPIO_44(c)		0x0B0 0x0B0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB22__DSPI0_SCK(c)		0x0B0 0x0B0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB22__VLCD(c)		0x0B0 0x0B0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB22__VIU_FID(c)		0x0B0 0x0B0 0x3A8 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC0__GPIO_45(c)		0x0B4 0x0B4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC0__ENET_RMII0_MDC(c)	0x0B4 0x0B4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC0__FTM1_CH0(c)		0x0B4 0x0B4 0x32C (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC0__DSPI0_CS3(c)		0x0B4 0x0B4 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC0__ESAI_SCKT(c)		0x0B4 0x0B4 0x310 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC0__ESDHC0_CLK(c)		0x0B4 0x0B4 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC0__VIU_DATA0(c)		0x0B4 0x0B4 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC0__SRC_RCON18(c)		0x0B4 0x0B4 0x398 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC1__GPIO_46(c)		0x0B8 0x0B8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC1__ENET_RMII0_MDIO(c)	0x0B8 0x0B8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC1__FTM1_CH1(c)		0x0B8 0x0B8 0x330 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC1__DSPI0_CS2(c)		0x0B8 0x0B8 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC1__ESAI_FST(c)		0x0B8 0x0B8 0x30C (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC1__ESDHC0_CMD(c)		0x0B8 0x0B8 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC1__VIU_DATA1(c)		0x0B8 0x0B8 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC1__SRC_RCON19(c)		0x0B8 0x0B8 0x39C (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC2__GPIO_47(c)		0x0BC 0x0BC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC2__ENET_RMII0_CRS(c)	0x0BC 0x0BC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC2__UART1_TX(c)		0x0BC 0x0BC 0x380 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC2__ESAI_SDO0(c)		0x0BC 0x0BC 0x314 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC2__ESDHC0_DAT0(c)		0x0BC 0x0BC 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC2__VIU_DATA2(c)		0x0BC 0x0BC 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC2__SRC_RCON20(c)		0x0BC 0x0BC 0x3A0 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC3__GPIO_48(c)		0x0C0 0x0C0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC3__ENET_RMII0_RXD1(c)	0x0C0 0x0C0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC3__UART1_RX(c)		0x0C0 0x0C0 0x37C (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC3__ESAI_SDO1(c)		0x0C0 0x0C0 0x318 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC3__ESDHC0_DAT1(c)		0x0C0 0x0C0 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC3__VIU_DATA3(c)		0x0C0 0x0C0 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC3__DCU0_R0(c)		0x0C0 0x0C0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC4__GPIO_49(c)		0x0C4 0x0C4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC4__ENET_RMII0_RXD0(c)	0x0C4 0x0C4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC4__UART1_RTS(c)		0x0C4 0x0C4 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC4__DSPI1_CS1(c)		0x0C4 0x0C4 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC4__ESAI_SDO2(c)		0x0C4 0x0C4 0x31C (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC4__ESDHC0_DAT2(c)		0x0C4 0x0C4 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC4__VIU_DATA4(c)		0x0C4 0x0C4 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC4__DCU0_R1(c)		0x0C4 0x0C4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC5__GPIO_50(c)		0x0C8 0x0C8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC5__ENET_RMII0_RXER(c)	0x0C8 0x0C8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC5__UART1_CTS(c)		0x0C8 0x0C8 0x378 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC5__DSPI1_CS0(c)		0x0C8 0x0C8 0x300 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC5__ESAI_SDO3(c)		0x0C8 0x0C8 0x320 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC5__ESDHC0_DAT3(c)		0x0C8 0x0C8 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC5__VIU_DATA5(c)		0x0C8 0x0C8 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC5__DCU0_G0(c)		0x0C8 0x0C8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC6__GPIO_51(c)		0x0CC 0x0CC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC6__ENET_RMII0_TXD1(c)	0x0CC 0x0CC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC6__DSPI1_SIN(c)		0x0CC 0x0CC 0x2FC (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC6__ESAI_SDI0(c)		0x0CC 0x0CC 0x328 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC6__ESDHC0_WP(c)		0x0CC 0x0CC 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC6__VIU_DATA6(c)		0x0CC 0x0CC 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC6__DCU0_G1(c)		0x0CC 0x0CC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC7__GPIO_52(c)		0x0D0 0x0D0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC7__ENET_RMII0_TXD0(c)	0x0D0 0x0D0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC7__DSPI1_SOUT(c)		0x0D0 0x0D0 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC7__ESAI_SDI1(c)		0x0D0 0x0D0 0x324 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC7__VIU_DATA7(c)		0x0D0 0x0D0 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC7__DCU0_B0(c)		0x0D0 0x0D0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC8__GPIO_53(c)		0x0D4 0x0D4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC8__ENET_RMII0_TXEN(c)	0x0D4 0x0D4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC8__DSPI1_SCK(c)		0x0D4 0x0D4 0x2F8 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC8__VIU_DATA8(c)		0x0D4 0x0D4 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC8__DCU0_B1(c)		0x0D4 0x0D4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC9__GPIO_54(c)		0x0D8 0x0D8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC9__ENET_RMII1_MDC(c)	0x0D8 0x0D8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC9__ESAI_SCKT(c)		0x0D8 0x0D8 0x310 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC9__MLB_CLK(c)		0x0D8 0x0D8 0x354 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC9__DEBUG_OUT0(c)		0x0D8 0x0D8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC10__GPIO_55(c)		0x0DC 0x0DC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC10__ENET_RMII1_MDIO(c)	0x0DC 0x0DC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC10__ESAI_FST(c)		0x0DC 0x0DC 0x30C (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC10__MLB_SIGNAL(c)		0x0DC 0x0DC 0x35C (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC10__DEBUG_OUT1(c)		0x0DC 0x0DC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC11__GPIO_56(c)		0x0E0 0x0E0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC11__ENET_RMII1_CRS(c)	0x0E0 0x0E0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC11__ESAI_SDO0(c)		0x0E0 0x0E0 0x314 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC11__MLB_DATA(c)		0x0E0 0x0E0 0x358 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC11__DEBUG_OUT(c)		0x0E0 0x0E0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC12__GPIO_57(c)		0x0E4 0x0E4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC12__ENET_RMII_RXD1(c)	0x0E4 0x0E4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC12__ESAI_SDO1(c)		0x0E4 0x0E4 0x318 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC12__SAI2_TX_BCLK(c)	0x0E4 0x0E4 0x370 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC12__DEBUG_OUT3(c)		0x0E4 0x0E4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC13__GPIO_58(c)		0x0E8 0x0E8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC13__ENET_RMII1_RXD0(c)	0x0E8 0x0E8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC13__ESAI_SDO2(c)		0x0E8 0x0E8 0x31C (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC13__SAI2_RX_BCLK(c)	0x0E8 0x0E8 0x364 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC13__DEBUG_OUT4(c)		0x0E8 0x0E8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC14__GPIO_59(c)		0x0EC 0x0EC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC14__ENET_RMII1_RXER(c)	0x0EC 0x0EC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC14__ESAI_SDO3(c)		0x0EC 0x0EC 0x320 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC14__UART5_TX(c)		0x0EC 0x0EC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC14__SAI2_RX_DATA(c)	0x0EC 0x0EC 0x368 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC14__ADC0_SE6(c)		0x0EC 0x0EC 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC14__DEBUG_OUT5(c)		0x0EC 0x0EC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC15__GPIO_60(c)		0x0F0 0x0F0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC15__ENET_RMII1_TXD1(c)	0x0F0 0x0F0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC15__ESAI_SDI0(c)		0x0F0 0x0F0 0x328 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC15__UART5_RX(c)		0x0F0 0x0F0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC15__SAI2_TX_DATA(c)	0x0F0 0x0F0 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC15__ADC0_SE7(c)		0x0F0 0x0F0 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC15__DEBUG_OUT6(c)		0x0F0 0x0F0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC16__GPIO_61(c)		0x0F4 0x0F4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC16__ENET_RMII1_TXD0(c)	0x0F4 0x0F4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC16__ESAI_SDI1(c)		0x0F4 0x0F4 0x324 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC16__UART5_RTS(c)		0x0F4 0x0F4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC16__SAI2_RX_SYNC(c)	0x0F4 0x0F4 0x36C (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC16__ADC1_SE6(c)		0x0F4 0x0F4 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC16__DEBUG_OUT7(c)		0x0F4 0x0F4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC17__GPIO_62(c)		0x0F8 0x0F8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC17__ENET_RMII1_TXEN(c)	0x0F8 0x0F8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC17__ADC1_SE7(c)		0x0F8 0x0F8 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC17__UART5_CTS(c)		0x0F8 0x0F8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC17__SAI2_TX_SYNC(c)	0x0F8 0x0F8 0x374 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC17__USB1_SOF_PULSE(c)	0x0F8 0x0F8 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC17__DEBUG_OUT8(c)		0x0F8 0x0F8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD31__GPIO_63(c)		0x0FC 0x0FC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD31__FB_AD31(c)		0x0FC 0x0FC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD31__NF_IO15(c)		0x0FC 0x0FC 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD31__FTM3_CH0(c)		0x0FC 0x0FC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD31__DSPI2_CS1(c)		0x0FC 0x0FC 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD31__DEBUG_OUT9(c)		0x0FC 0x0FC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD30__GPIO_64(c)		0x100 0x100 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD30__FB_AD30(c)		0x100 0x100 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD30__NF_IO14(c)		0x100 0x100 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD30__FTM3_CH1(c)		0x100 0x100 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD30__DSPI2_CS0(c)		0x100 0x100 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD30__DEBUG_OUT10(c)	0x100 0x100 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD29__GPIO_65(c)		0x104 0x104 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD29__FB_AD29(c)		0x104 0x104 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD29__NF_IO13(c)		0x104 0x104 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD29__FTM3_CH2(c)		0x104 0x104 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD29__DSPI2_SIN(c)		0x104 0x104 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD29__DEBUG_OUT11(c)	0x104 0x104 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD28__GPIO_66(c)	 	0x108 0x108 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD28__FB_AD28(c)		0x108 0x108 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD28__NF_IO12(c)		0x108 0x108 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD28__I2C2_SCL(c)		0x108 0x108 0x34C (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD28__FTM3_CH3(c)		0x108 0x108 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD28__DSPI2_SOUT(c)		0x108 0x108 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD28__DEBUG_OUT12(c)	0x108 0x108 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD27__GPIO_67(c)		0x10C 0x10C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD27__FB_AD27(c)		0x10C 0x10C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD27__NF_IO11(c)		0x10C 0x10C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD27__I2C2_SDA(c)		0x10C 0x10C 0x350 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD27__FTM3_CH4(c)		0x10C 0x10C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD27__DSPI2_SCK(c)		0x10C 0x10C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD27__DEBUG_OUT13(c)	0x10C 0x10C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD26__GPIO_68(c)		0x110 0x110 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD26__FB_AD26(c)		0x110 0x110 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD26__NF_IO10(c)		0x110 0x110 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD26__FTM3_CH5(c)		0x110 0x110 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD26__ESDHC1_WP(c)		0x110 0x110 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD26__DEBUG_OUT14(c)	0x110 0x110 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD25__GPIO_69(c)		0x114 0x114 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD25__FB_AD25(c)		0x114 0x114 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD25__NF_IO9(c)		0x114 0x114 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD25__FTM3_CH6(c)		0x114 0x114 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD25__DEBUG_OUT15(c)	0x114 0x114 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD24__GPIO_70(c)		0x118 0x118 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD24__FB_AD24(c)		0x118 0x118 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD24__NF_IO8(c)		0x118 0x118 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD24__FTM3_CH7(c)		0x118 0x118 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD24__DEBUG_OUT16(c)	0x118 0x118 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD23__GPIO_71(c)		0x11C 0x11C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD23__FB_AD23(c)		0x11C 0x11C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD23__NF_IO7(c)		0x11C 0x11C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD23__FTM2_CH0(c)		0x11C 0x11C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD23__ENET0_1588_TMR0(c)	0x11C 0x11C 0x304 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD23__ESDHC0_DAT4(c)	0x11C 0x11C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD23__UART2_TX(c)		0x11C 0x11C 0x38C (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTD23__DCU1_R3(c)		0x11C 0x11C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD22__GPIO_72(c)		0x120 0x120 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD22__FB_AD22(c)		0x120 0x120 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD22__NF_IO6(c)		0x120 0x120 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD22__FTM2_CH1(c)		0x120 0x120 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD22__ENET0_1588_TMR1(c)	0x120 0x120 0x308 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD22__ESDHC0_DAT5(c)	0x120 0x120 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD22__UART2_RX(c)		0x120 0x120 0x388 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTD22__DCU1_R4(c)		0x120 0x120 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD21__GPIO_73(c)		0x124 0x124 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD21__FB_AD21(c)		0x124 0x124 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD21__NF_IO5(c)		0x124 0x124 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD21__ENET0_1588_TMR2(c)	0x124 0x124 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD21__ESDHC0_DAT6(c)	0x124 0x124 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD21__UART2_RTS(c)		0x124 0x124 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTD21__DCU1_R5(c)		0x124 0x124 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD20__GPIO_74(c)		0x128 0x128 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD20__FB_AD20(c)		0x128 0x128 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD20__NF_IO4(c)		0x128 0x128 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD20__ENET0_1588_TMR3(c)	0x128 0x128 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD20__ESDHC0_DAT7(c)	0x128 0x128 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD20__UART2_CTS(c)		0x128 0x128 0x384 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTD20__DCU1_R0(c)		0x128 0x128 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD19__GPIO_75(c)		0x12C 0x12C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD19__FB_AD19(c)		0x12C 0x12C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD19__NF_IO3(c)		0x12C 0x12C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD19__ESAI_SCKR(c)		0x12C 0x12C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD19__I2C0_SCL(c)		0x12C 0x12C 0x33C (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD19__FTM2_QD_PHA(c)	0x12C 0x12C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD19__DCU1_R1(c)		0x12C 0x12C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD18__GPIO_76(c)		0x130 0x130 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD18__FB_AD18(c)		0x130 0x130 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD18__NF_IO2(c)		0x130 0x130 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD18__ESAI_FSR(c)		0x130 0x130 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD18__I2C0_SDA(c)		0x130 0x130 0x340 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD18__FTM2_QD_PHB(c)	0x130 0x130 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD18__DCU1_G0(c)		0x130 0x130 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD17__GPIO_77(c)		0x134 0x134 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD17__FB_AD17(c)		0x134 0x134 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD17__NF_IO1(c)		0x134 0x134 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD17__ESAI_HCKR(c)		0x134 0x134 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD17__I2C1_SCL(c)		0x134 0x134 0x344 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD17__DCU1_G1(c)		0x134 0x134 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD16__GPIO_78(c)		0x138 0x138 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD16__FB_AD16(c)		0x138 0x138 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD16__NF_IO0(c)		0x138 0x138 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD16__ESAI_HCKT(c)		0x138 0x138 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD16__I2C1_SDA(c)		0x138 0x138 0x348 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD16__DCU1_G2(c)		0x138 0x138 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD0__GPIO_79(c)		0x13C 0x13C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD0__QSPI0_A_QSCK(c)	0x13C 0x13C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD0__UART2_TX(c)		0x13C 0x13C 0x38C (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD0__FB_AD15(c)		0x13C 0x13C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD0__SPDIF_EXTCLK(c)	0x13C 0x13C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD0__DEBUG_OUT17(c)		0x13C 0x13C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD1__GPIO_80(c)		0x140 0x140 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD1__QSPI0_A_CS0(c)		0x140 0x140 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD1__UART2_RX(c)		0x140 0x140 0x388 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD1__FB_AD14(c)		0x140 0x140 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD1__SPDIF_IN1(c)		0x140 0x140 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD1__DEBUG_OUT18(c)		0x140 0x140 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD2__GPIO_81(c)		0x144 0x144 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD2__QSPI0_A_DATA3(c)	0x144 0x144 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD2__UART2_RTS(c)		0x144 0x144 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD2__DSPI1_CS3(c)		0x144 0x144 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD2__FB_AD13(c)		0x144 0x144 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD2__SPDIF_OUT1(c)		0x144 0x144 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD2__DEBUG_OUT19(c)		0x144 0x144 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD3__GPIO_82(c)		0x148 0x148 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD3__QSPI0_A_DATA2(c)	0x148 0x148 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD3__UART2_CTS(c)		0x148 0x148 0x384 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD3__DSPI1_CS2(c)		0x148 0x148 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD3__FB_AD12(c)		0x148 0x148 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD3__SPDIF_PLOCK(c)		0x148 0x148 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD3__DEBUG_OUT20(c)		0x148 0x148 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD4__GPIO_83(c)		0x14C 0x14C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD4__QSPI0_A_DATA1(c)	0x14C 0x14C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD4__DSPI1_CS1(c)		0x14C 0x14C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD4__FB_AD11(c)		0x14C 0x14C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD4__SPDIF_SRCLK(c)		0x14C 0x14C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTD4__DEBUG_OUT21(c)		0x14C 0x14C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD5__GPIO_84(c)		0x150 0x150 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD5__QSPI0_A_DATA0(c)	0x150 0x150 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD5__DSPI1_CS0(c)		0x150 0x150 0x300 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD5__FB_AD10(c)		0x150 0x150 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD5__DEBUG_OUT22(c)		0x150 0x150 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD6__GPIO_85(c)		0x154 0x154 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD6__QSPI1_A_DQS(c)		0x154 0x154 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD6__DSPI1_SIN(c)		0x154 0x154 0x2FC (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD6__FB_AD9(c)		0x154 0x154 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD6__DEBUG_OUT23(c)		0x154 0x154 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD7__GPIO_86(c)		0x158 0x158 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD7__QSPI0_B_QSCK(c)	0x158 0x158 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD7__DSPI1_SOUT(c)		0x158 0x158 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD7__FB_AD8(c)		0x158 0x158 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD7__DEBUG_OUT24(c)		0x158 0x158 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD8__GPIO_87(c)		0x15C 0x15C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD8__QSPI0_B_CS0(c)		0x15C 0x15C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD8__FB_CLKOUT(c)		0x15C 0x15C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD8__DSPI1_SCK(c)		0x15C 0x15C 0x2F8 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTD8__FB_AD7(c)		0x15C 0x15C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD8__DEBUG_OUT25(c)		0x15C 0x15C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD9__GPIO_88(c)		0x160 0x160 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD9__QSPI0_B_DATA3(c)	0x160 0x160 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD9__DSPI3_CS1(c)		0x160 0x160 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD9__FB_AD6(c)		0x160 0x160 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD9__SAI1_TX_SYNC(c)	0x160 0x160 0x360 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTD9__DCU1_B0(c)		0x160 0x160 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD10__GPIO_89(c)		0x164 0x164 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD10__QSPI0_B_DATA2(c)	0x164 0x164 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD10__DSPI3_CS0(c)		0x164 0x164 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD10__FB_AD5(c)		0x164 0x164 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD10__DCU1_B1(c)		0x164 0x164 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD11__GPIO_90(c)		0x168 0x168 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD11__QSPI0_B_DATA1(c)	0x168 0x168 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD11__DSPI3_SIN(c)		0x168 0x168 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD11__FB_AD4(c)		0x168 0x168 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD11__DEBUG_OUT26(c)	0x168 0x168 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD12__GPIO_91(c)		0x16C 0x16C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD12__QSPI0_B_DATA0(c)	0x16C 0x16C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD12__DSPI3_SOUT(c)		0x16C 0x16C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD12__FB_AD3(c)		0x16C 0x16C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD12__DEBUG_OUT27(c)	0x16C 0x16C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTD13__GPIO_92(c)		0x170 0x170 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTD13__QSPI0_B_DQS(c)	0x170 0x170 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTD13__DSPI3_SCK(c)		0x170 0x170 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTD13__FB_AD2(c)		0x170 0x170 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTD13__DEBUG_OUT28(c)	0x170 0x170 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB23__GPIO_93(c)		0x174 0x174 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB23__SAI0_TX_BCLK(c)	0x174 0x174 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB23__UART1_TX(c)		0x174 0x174 0x380 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB23__SRC_RCON18(c)		0x174 0x174 0x398 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB23__FB_MUXED_ALE(c)	0x174 0x174 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB23__FB_TS_B(c)		0x174 0x174 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB23__UART3_RTS(c)		0x174 0x174 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB23__DCU1_G3(c)		0x174 0x174 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB24__GPIO_94(c)		0x178 0x178 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB24__SAI0_RX_BCLK(c)	0x178 0x178 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB24__UART1_RX(c)		0x178 0x178 0x37C (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB24__SRC_RCON19(c)		0x178 0x178 0x39C (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB24__FB_MUXED_TSIZ0(c)	0x178 0x178 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB24__NF_WE_B(c)		0x178 0x178 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB24__UART3_CTS(c)		0x178 0x178 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB24__DCU1_G4(c)		0x178 0x178 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB25__GPIO_95(c)		0x17C 0x17C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB25__SAI0_RX_DATA(c)	0x17C 0x17C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB25__UART1_RTS(c)		0x17C 0x17C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB25__SRC_RCON20(c)		0x17C 0x17C 0x3A0 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB25__FB_CS1_B(c)		0x17C 0x17C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB25__NF_CE0_B(c)		0x17C 0x17C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB25__DCU1_G5(c)		0x17C 0x17C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB26__GPIO_96(c)		0x180 0x180 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB26__SAI0_TX_DATA(c)	0x180 0x180 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB26__UART1_CTS(c)		0x180 0x180 0x378 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTB26__SRC_RCON21(c)		0x180 0x180 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB26__FB_CS0_B(c)		0x180 0x180 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB26__NF_CE1_B(c)		0x180 0x180 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB26__DCU1_G6(c)		0x180 0x180 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB27__GPIO_97(c)		0x184 0x184 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB27__SAI0_RX_SYNC(c)	0x184 0x184 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB27__SRC_RCON22(c)		0x184 0x184 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB27__FB_OE_B(c)		0x184 0x184 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB27__FB_MUXED_TBST_B(c)	0x184 0x184 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTB27__NF_RE_B(c)		0x184 0x184 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTB27__DCU1_G7(c)		0x184 0x184 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTB28__GPIO_98(c)		0x188 0x188 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTB28__SAI0_TX_SYNC(c)	0x188 0x188 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTB28__SRC_RCON23(c)		0x188 0x188 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTB28__FB_RW_B(c)		0x188 0x188 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTB28__DCU1_B6(c)		0x188 0x188 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC26__GPIO_99(c)		0x18C 0x18C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC26__SAI1_TX_BCLK(c)	0x18C 0x18C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC26__DSPI0_CS5(c)		0x18C 0x18C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC26__SRC_RCON24(c)		0x18C 0x18C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC26__FB_TA_B(c)		0x18C 0x18C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC26__NF_RB_B(c)		0x18C 0x18C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC26__DCU1_B7(c)		0x18C 0x18C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC27__GPIO_100(c)		0x190 0x190 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC27__SAI1_RX_BCLK(c)	0x190 0x190 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC27__DSPI0_CS4(c)		0x190 0x190 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC27__SRC_RCON25(c)		0x190 0x190 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC27__FB_BE3_B(c)		0x190 0x190 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC27__FB_CS3_B(c)		0x190 0x190 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC27__NF_ALE(c)		0x190 0x190 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC27__DCU1_B2(c)		0x190 0x190 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC28__GPIO_101(c)		0x194 0x194 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC28__SAI1_RX_DATA(c)	0x194 0x194 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC28__DSPI0_CS3(c)		0x194 0x194 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC28__SRC_RCON26(c)		0x194 0x194 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC28__FB_BE2_B(c)		0x194 0x194 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC28__FB_CS2_B(c)		0x194 0x194 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC28__NF_CLE(c)		0x194 0x194 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC28__DCU1_B3(c)		0x194 0x194 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC29__GPIO_102(c)		0x198 0x198 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC29__SAI1_TX_DATA(c)	0x198 0x198 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC29__DSPI0_CS2(c)		0x198 0x198 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC29__SRC_RCON27(c)		0x198 0x198 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC29__FB_BE1_B(c)		0x198 0x198 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC29__FB_MUXED_TSIZE1(c)	0x198 0x198 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC29__DCU1_B4(c)		0x198 0x198 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC30__GPIO_103(c)		0x19C 0x19C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC30__SAI1_RX_SYNC(c)	0x19C 0x19C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC30__DSPI1_CS2(c)		0x19C 0x19C 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTC30__SRC_RCON28(c)		0x19C 0x19C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC30__FB_MUXED_BE0_B(c)	0x19C 0x19C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTC30__FB_TSIZ0(c)		0x19C 0x19C 0x000 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTC30__ADC0_SE5(c)		0x19C 0x19C 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC30__DCU1_B5(c)		0x19C 0x19C 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTC31__GPIO_104(c)		0x1A0 0x1A0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTC31__SAI1_TX_SYNC(c)	0x1A0 0x1A0 0x360 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTC31__SRC_RCON29(c)		0x1A0 0x1A0 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTC31__ADC1_SE5(c)		0x1A0 0x1A0 0x000 (ALT6|c) 0 (ALT6|c)
+#define MVF600_PAD_PTC31__DCU1_B6(c)		0x1A0 0x1A0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE0__GPIO_105(c)		0x1A4 0x1A4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE0__DCU0_HSYNC(c)		0x1A4 0x1A4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE0__SRC_BMODE1(c)		0x1A4 0x1A4 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTE0__LCD0(c)		0x1A4 0x1A4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE0__DEBUG_OUT29(c)		0x1A4 0x1A4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE1__GPIO_106(c)		0x1A8 0x1A8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE1__DCU0_VSYNC(c)		0x1A8 0x1A8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE1__SRC_BMODE0(c)		0x1A8 0x1A8 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTE1__LCD1(c)		0x1A8 0x1A8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE1__DEBUG_OUT30(c)		0x1A8 0x1A8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE2__GPIO_107(c)		0x1AC 0x1AC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE2__DCU0_PCLK(c)		0x1AC 0x1AC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE2__LCD2(c)		0x1AC 0x1AC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE2__DEBUG_OUT31(c)		0x1AC 0x1AC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE3__GPIO_108(c)		0x1B0 0x1B0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE3__DCU0_TAG(c)		0x1B0 0x1B0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE3__LCD3(c)		0x1B0 0x1B0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE3__DEBUG_OUT32(c)		0x1B0 0x1B0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE4__GPIO_109(c)		0x1B4 0x1B4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE4__DCU0_DE(c)		0x1B4 0x1B4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE4__LCD4(c)		0x1B4 0x1B4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE4__DEBUG_OUT33(c)		0x1B4 0x1B4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE5__GPIO_110(c)		0x1B8 0x1B8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE5__DCU0_R0(c)		0x1B8 0x1B8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE5__LCD5(c)		0x1B8 0x1B8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE5__DEBUG_OUT34(c)		0x1B8 0x1B8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE6__GPIO_111(c)		0x1BC 0x1BC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE6__DCU0_R1(c)		0x1BC 0x1BC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE6__LCD6(c)		0x1BC 0x1BC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE6__DEBUG_OUT35(c)		0x1BC 0x1BC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE7__GPIO_112(c)		0x1C0 0x1C0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE7__DCU0_R2(c)		0x1C0 0x1C0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE7__SRC_RCON0(c)		0x1C0 0x1C0 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE7__LCD7(c)		0x1C0 0x1C0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE7__DEBUG_OUT36(c)		0x1C0 0x1C0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE8__GPIO_113(c)		0x1C4 0x1C4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE8__DCU0_R3(c)		0x1C4 0x1C4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE8__SRC_RCON1(c)		0x1C4 0x1C4 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE8__LCD8(c)		0x1C4 0x1C4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE8__DEBUG_OUT37(c)		0x1C4 0x1C4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE9__GPIO_114(c)		0x1C8 0x1C8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE9__DCU0_R4(c)		0x1C8 0x1C8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE9__SRC_RCON2(c)		0x1C8 0x1C8 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE9__LCD9(c)		0x1C8 0x1C8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE9__DEBUG_OUT38(c)		0x1C8 0x1C8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE10__GPIO_115(c)		0x1CC 0x1CC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE10__DCU0_R5(c)		0x1CC 0x1CC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE10__SRC_RCON3(c)		0x1CC 0x1CC 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE10__LCD10(c)		0x1CC 0x1CC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE10__DEBUG_OUT39(c)	0x1CC 0x1CC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE11__GPIO_116(c)		0x1D0 0x1D0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE11__DCU0_R6(c)		0x1D0 0x1D0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE11__SRC_RCON4(c)		0x1D0 0x1D0 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE11__LCD11(c)		0x1D0 0x1D0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE11__DEBUG_OUT40(c)	0x1D0 0x1D0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE12__GPIO_117(c)		0x1D4 0x1D4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE12__DCU0_R7(c)		0x1D4 0x1D4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE12__DSPI1_CS3(c)		0x1D4 0x1D4 0x000 (ALT2|c) 0 (ALT2|c)
+#define MVF600_PAD_PTE12__SRC_RCON5(c)		0x1D4 0x1D4 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE12__LCD12(c)		0x1D4 0x1D4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE12__LPT_ALT0(c)		0x1D4 0x1D4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE13__GPIO_118(c)		0x1D8 0x1D8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE13__DCU0_G0(c)		0x1D8 0x1D8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE13__LCD13(c)		0x1D8 0x1D8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE13__DEBUG_OUT41(c)	0x1D8 0x1D8 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE14__GPIO_119(c)		0x1DC 0x1DC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE14__DCU0_G1(c)		0x1DC 0x1DC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE14__LCD14(c)		0x1DC 0x1DC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE14__DEBUG_OUT42(c)	0x1DC 0x1DC 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE15__GPIO_120(c)		0x1E0 0x1E0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE15__DCU0_G2(c)		0x1E0 0x1E0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE15__SRC_RCON6(c)		0x1E0 0x1E0 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE15__LCD15(c)		0x1E0 0x1E0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE15__DEBUG_OUT43(c)	0x1E0 0x1E0 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE16__GPIO_121(c)		0x1E4 0x1E4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE16__DCU0_G3(c)		0x1E4 0x1E4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE16__SRC_RCON7(c)		0x1E4 0x1E4 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE16__LCD16(c)		0x1E4 0x1E4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE17__GPIO_122(c)		0x1E8 0x1E8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE17__DCU0_G4(c)		0x1E8 0x1E8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE17__SRC_RCON8(c)		0x1E8 0x1E8 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE17__LCD17(c)		0x1E8 0x1E8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE18__GPIO_123(c)		0x1EC 0x1EC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE18__DCU0_G5(c)		0x1EC 0x1EC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE18__SRC_RCON9(c)		0x1EC 0x1EC 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE18__LCD18(c)		0x1EC 0x1EC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE19__GPIO_124(c)		0x1F0 0x1F0 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE19__DCU0_G6(c)		0x1F0 0x1F0 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE19__SRC_RCON10(c)		0x1F0 0x1F0 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE19__LCD19(c)		0x1F0 0x1F0 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE19__I2C0_SCL(c)		0x1F0 0x1F0 0x33C (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTE20__GPIO_125(c)		0x1F4 0x1F4 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE20__DCU0_G7(c)		0x1F4 0x1F4 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE20__SRC_RCON11(c)		0x1F4 0x1F4 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE20__LCD20(c)		0x1F4 0x1F4 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE20__I2C0_SDA(c)		0x1F4 0x1F4 0x340 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTE20__EWM_IN(c)		0x1F4 0x1F4 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTE21__GPIO_126(c)		0x1F8 0x1F8 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE21__DCU0_B0(c)		0x1F8 0x1F8 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE21__LCD21(c)		0x1F8 0x1F8 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE22__GPIO_127(c)		0x1FC 0x1FC 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE22__DCU0_B1(c)		0x1FC 0x1FC 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE22__LCD22(c)		0x1FC 0x1FC 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE23__GPIO_128(c)		0x200 0x200 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE23__DCU0_B2(c)		0x200 0x200 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE23__SRC_RCON12(c)		0x200 0x200 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE23__LCD23(c)		0x200 0x200 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE24__GPIO_129(c)		0x204 0x204 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE24__DCU0_B3(c)		0x204 0x204 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE24__SRC_RCON13(c)		0x204 0x204 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE24__LCD24(c)		0x204 0x204 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE25__GPIO_130(c)		0x208 0x208 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE25__DCU0_B4(c)		0x208 0x208 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE25__SRC_RCON14(c)		0x208 0x208 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE25__LCD25(c)		0x208 0x208 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE26__GPIO_131(c)		0x20C 0x20C 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE26__DCU0_B5(c)		0x20C 0x20C 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE26__SRC_RCON15(c)		0x20C 0x20C 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE26__LCD26(c)		0x20C 0x20C 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE27__GPIO_132(c)		0x210 0x210 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE27__DCU0_B6(c)		0x210 0x210 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE27__SRC_RCON16(c)		0x210 0x210 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE27__LCD27(c)		0x210 0x210 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE27__I2C1_SCL(c)		0x210 0x210 0x344 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTE28__GPIO_133(c)		0x214 0x214 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTE28__DCU0_B7(c)		0x214 0x214 0x000 (ALT1|c) 0 (ALT1|c)
+#define MVF600_PAD_PTE28__SRC_RCON17(c)		0x214 0x214 0x000 (ALT3|c) 0 (ALT3|c)
+#define MVF600_PAD_PTE28__LCD28(c)		0x214 0x214 0x000 (ALT4|c) 0 (ALT4|c)
+#define MVF600_PAD_PTE28__I2C1_SDA(c)		0x214 0x214 0x348 (ALT5|c) 0 (ALT5|c)
+#define MVF600_PAD_PTE28__EWM_OUT(c)		0x214 0x214 0x000 (ALT7|c) 0 (ALT7|c)
+#define MVF600_PAD_PTA7__GPIO_134(c)		0x218 0x218 0x000 (ALT0|c) 0 (ALT0|c)
+#define MVF600_PAD_PTA7__VIU_PIX_CLK(c)		0x218 0x218 0x3AC (ALT1|c) 0 (ALT1|c)
+
+#endif
diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts
new file mode 100644
index 0000000..e2dafa2
--- /dev/null
+++ b/arch/arm/boot/dts/mvf600-twr.dts
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "mvf600.dtsi"
+
+/ {
+	model = "MVF600 Tower Board";
+	compatible = "fsl,mvf600-twr", "fsl,mvf600";
+
+	chosen {
+		bootargs = "console=ttymxc1,115200";
+	};
+
+	memory {
+		reg = <0x80000000 0x8000000>;
+	};
+
+	clocks {
+		osc {
+			compatible = "fsl,mvf-osc", "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+
+		audio_clk {
+			compatible = "fsl,mvf-audio-ext-clk", "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
+		enet_clk {
+			compatible = "fsl,mvf-enet-ext-clk", "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&fec0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec0_1>;
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1_1>;
+};
+
+
+&qspi0 { /* QuadSPI0 */
+	fsl,spi-num-chipselects = <1>;
+	fsl,spi-flash-chipselects = <0>;
+	status = "okay";
+
+	flash: s25fl128s at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl128s";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		linux,modalias = "m25p80";
+		modal = "s25fl128s";
+		partition at 0 {
+			label = "s25fl128s";
+			reg = <0x0 0x1000000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi
new file mode 100644
index 0000000..ca25f80
--- /dev/null
+++ b/arch/arm/boot/dts/mvf600.dtsi
@@ -0,0 +1,426 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton.dtsi"
+#include "mvf600-pinfunc.h"
+/ {
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+	};
+
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		aips0: aips-bus at 40000000 { /* AIPS0 */
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-parent = <&intc>;
+			reg = <0x40000000 0x70000>;
+			ranges;
+
+			mscm: mscm at 40001000 {
+				compatible = "fsl,mvf-mscm";
+				reg = <0x40001000 0x1000>;
+			};
+
+			intc: interrupt-controller at 40002000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				reg = <0x40003000 0x1000>,
+				      <0x40002100 0x100>;
+			};
+
+			L2: l2-cache at 40006000 {
+				compatible = "arm,pl310-cache";
+				reg = <0x40006000 0x1000>;
+				interrupts = <0 6 0x04>;
+				cache-unified;
+				cache-level = <2>;
+			};
+
+			uart0: serial at 40027000 { /* UART0 */
+				compatible = "fsl,mvf-uart";
+				reg = <0x40027000 0x1000>;
+				interrupts = <0 61 0x00>;
+				clocks = <&clks 39>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart1: serial at 40028000 { /* UART1 */
+				compatible = "fsl,mvf-uart";
+				reg = <0x40028000 0x1000>;
+				interrupts = <0 62 0x04>;
+				clocks = <&clks 40>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart2: serial at 40029000 { /* UART2 */
+				compatible = "fsl,mvf-uart";
+				reg = <0x40029000 0x1000>;
+				interrupts = <0 63 0x04>;
+				clocks = <&clks 41>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart3: serial at 4002a000 { /* UART3 */
+				compatible = "fsl,mvf-uart";
+				reg = <0x4002a000 0x1000>;
+				interrupts = <0 64 0x04>;
+				clocks = <&clks 42>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			pit:pit at 40037000 {
+				compatible = "fsl,mvf-pit";
+				reg = <0x40037000 0x1000>;
+				interrupts = <0 39 0x04>;
+				clock-names = "pit";
+				clocks = <&clks 45>;
+			};
+
+			wdog at 4003e000 {
+				compatible = "fsl,mvf-wdt";
+				reg = <0x4003e000 0x1000>;
+				clock-names = "wdog";
+				clocks = <&clks 76>;
+			};
+
+			qspi0: quadspi at 40044000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,mvf-qspi";
+				reg = <0x40044000 0x1000>;
+				interrupts = <0 24 0x04>;
+				status = "disabled";
+			};
+
+			iomuxc: iomuxc at 40048000 {
+				compatible = "fsl,mvf-iomuxc";
+				reg = <0x40048000 0x1000>;
+				#gpio-range-cells = <2>;
+
+				/* functions and groups pins */
+				esdhc1 {
+					pinctrl_esdhc1_1: esdhc1grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA24__ESDHC1_CLK(0x31ef)
+						MVF600_PAD_PTA25__ESDHC1_CMD(0x31ef)
+						MVF600_PAD_PTA26__ESDHC1_DAT0(0x31ef)
+						MVF600_PAD_PTA27__ESDHC1_DAT1(0x31ef)
+						MVF600_PAD_PTA28__ESDHC1_DATA2(0x31ef)
+						MVF600_PAD_PTA29__ESDHC1_DAT3(0x31ef)
+						MVF600_PAD_PTA7__GPIO_134(0x219d)
+						>;
+					};
+				};
+
+				i2c0 {
+					pinctrl_i2c0_1: i2c0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB14__I2C0_SCL(0x30d3)
+						MVF600_PAD_PTB15__I2C0_SDA(0x30d3)
+						>;
+					};
+				};
+
+				dspi0 {
+					pinctrl_dspi0_1: dspi0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB19__DSPI0_CS0(0x1182)
+						MVF600_PAD_PTB20__DSPI0_SIN(0x1181)
+						MVF600_PAD_PTB21__DSPI0_SOUT(0x1182)
+						MVF600_PAD_PTB22__DSPI0_SCK(0x1182)
+						>;
+					};
+				};
+
+				fec0 {
+					pinctrl_fec0_1: fec0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA6__RMII_CLKIN(0x30d1)
+						MVF600_PAD_PTC0__ENET_RMII0_MDC(0x30d3)
+						MVF600_PAD_PTC1__ENET_RMII0_MDIO(0x30d1)
+						MVF600_PAD_PTC2__ENET_RMII0_CRS(0x30d1)
+						MVF600_PAD_PTC3__ENET_RMII0_RXD1(0x30d1)
+						MVF600_PAD_PTC4__ENET_RMII0_RXD0(0x30d1)
+						MVF600_PAD_PTC5__ENET_RMII0_RXER(0x30d1)
+						MVF600_PAD_PTC6__ENET_RMII0_TXD1(0x30d2)
+						MVF600_PAD_PTC7__ENET_RMII0_TXD0(0x30d2)
+						MVF600_PAD_PTC8__ENET_RMII0_TXEN(0x30d2)
+						>;
+					};
+				};
+
+				fec1 {
+					pinctrl_fec1_1: fec1grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTC9__ENET_RMII1_MDC(0x30d2)
+						MVF600_PAD_PTC10__ENET_RMII1_MDIO(0x30d3)
+						MVF600_PAD_PTC11__ENET_RMII1_CRS(0x30d1)
+						MVF600_PAD_PTC12__ENET_RMII_RXD1(0x30d1)
+						MVF600_PAD_PTC13__ENET_RMII1_RXD0(0x30d1)
+						MVF600_PAD_PTC14__ENET_RMII1_RXER(0x30d1)
+						MVF600_PAD_PTC15__ENET_RMII1_TXD1(0x30d2)
+						MVF600_PAD_PTC16__ENET_RMII1_TXD0(0x30d2)
+						MVF600_PAD_PTC17__ENET_RMII1_TXEN(0x30d2)
+						>;
+					};
+				};
+
+				sai2 {
+					pinctrl_sai2_1: sai2grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA16__SAI2_TX_BCLK(0x02ed)
+						MVF600_PAD_PTA18__SAI2_TX_DATA(0x02ee)
+						MVF600_PAD_PTA19__SAI2_TX_SYNC(0x02ed)
+						MVF600_PAD_PTA21__SAI2_RX_BCLK(0x02ed)
+						MVF600_PAD_PTA22__SAI2_RX_DATA(0x02ed)
+						MVF600_PAD_PTA23__SAI2_RX_SYNC(0x02ed)
+						MVF600_PAD_PTB18__EXT_AUDIO_MCLK(0x02ed)
+						>;
+					};
+				};
+
+				dcu0 {
+					pinctrl_dcu0_1: dcu0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB8__GPIO_30(0x42)
+						MVF600_PAD_PTE0__DCU0_HSYNC(0x42)
+						MVF600_PAD_PTE1__DCU0_VSYNC(0x42)
+						MVF600_PAD_PTE2__DCU0_PCLK(0x42)
+						MVF600_PAD_PTE4__DCU0_DE(0x42)
+						MVF600_PAD_PTE5__DCU0_R0(0x42)
+						MVF600_PAD_PTE6__DCU0_R1(0x42)
+						MVF600_PAD_PTE7__DCU0_R2(0x42)
+						MVF600_PAD_PTE8__DCU0_R3(0x42)
+						MVF600_PAD_PTE9__DCU0_R4(0x42)
+						MVF600_PAD_PTE10__DCU0_R5(0x42)
+						MVF600_PAD_PTE11__DCU0_R6(0x42)
+						MVF600_PAD_PTE12__DCU0_R7(0x42)
+						MVF600_PAD_PTE13__DCU0_G0(0x42)
+						MVF600_PAD_PTE14__DCU0_G1(0x42)
+						MVF600_PAD_PTE15__DCU0_G2(0x42)
+						MVF600_PAD_PTE16__DCU0_G3(0x42)
+						MVF600_PAD_PTE17__DCU0_G4(0x42)
+						MVF600_PAD_PTE18__DCU0_G5(0x42)
+						MVF600_PAD_PTE19__DCU0_G6(0x42)
+						MVF600_PAD_PTE20__DCU0_G7(0x42)
+						MVF600_PAD_PTE21__DCU0_B0(0x42)
+						MVF600_PAD_PTE22__DCU0_B1(0x42)
+						MVF600_PAD_PTE23__DCU0_B2(0x42)
+						MVF600_PAD_PTE24__DCU0_B3(0x42)
+						MVF600_PAD_PTE25__DCU0_B4(0x42)
+						MVF600_PAD_PTE26__DCU0_B5(0x42)
+						MVF600_PAD_PTE27__DCU0_B6(0x42)
+						MVF600_PAD_PTE28__DCU0_B7(0x42)
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB4__UART1_TX(0x21a2)
+						MVF600_PAD_PTB5__UART1_RX(0x21a1)
+						>;
+					};
+				};
+
+				usbvbus {
+					pinctrl_usbvbus_1: usbvbusgrp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c)
+						MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c)
+						>;
+					};
+				};
+
+				pwm0 {
+					pinctrl_pwm0_1: pwm0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB0__FTM0_CH0(0x1582)
+						MVF600_PAD_PTB1__FTM0_CH1(0x1582)
+						MVF600_PAD_PTB2__FTM0_CH2(0x1582)
+						MVF600_PAD_PTB3__FTM0_CH3(0x1582)
+						MVF600_PAD_PTB6__FTM0_CH6(0x1582)
+						MVF600_PAD_PTB7__FTM0_CH7(0x1582)
+						>;
+					};
+				};
+
+				qspi0 {
+					pinctrl_qspi0_1: qspi0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTD0__QSPI0_A_QSCK(0x307b)
+						MVF600_PAD_PTD1__QSPI0_A_CS0(0x307f)
+						MVF600_PAD_PTD2__QSPI0_A_DATA3(0x3073)
+						MVF600_PAD_PTD3__QSPI0_A_DATA2(0x3073)
+						MVF600_PAD_PTD4__QSPI0_A_DATA1(0x3073)
+						MVF600_PAD_PTD5__QSPI0_A_DATA0(0x307b)
+						MVF600_PAD_PTD7__QSPI0_B_QSCK(0x307b)
+						MVF600_PAD_PTD8__QSPI0_B_CS0(0x307f)
+						MVF600_PAD_PTD9__QSPI0_B_DATA3(0x3073)
+						MVF600_PAD_PTD10__QSPI0_B_DATA2(0x3073)
+						MVF600_PAD_PTD11__QSPI0_B_DATA1(0x3073)
+						MVF600_PAD_PTD12__QSPI0_B_DATA0(0x307b)
+						>;
+					};
+				};
+
+				touchscreen0 {
+					pinctrl_ts0_1: ts0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA31__GPIO_21(0x219d)
+						>;
+					};
+				};
+
+			};
+
+			gpio1: gpio at 40049000 {
+				compatible = "fsl,mvf-gpio";
+				reg = <0x40049000 0x1000 0x400ff000 0x40>;
+				interrupts = <0 107 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 32>;
+			};
+
+			gpio2: gpio at 4004a000 {
+				compatible = "fsl,mvf-gpio";
+				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+				interrupts = <0 108 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 32 32>;
+			};
+
+			gpio3: gpio at 4004b000 {
+				compatible = "fsl,mvf-gpio";
+				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+				interrupts = <0 109 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 64 32>;
+			};
+
+			gpio4: gpio at 4004c000 {
+				compatible = "fsl,mvf-gpio";
+				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+				interrupts = <0 110 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 96 32>;
+			};
+
+			gpio5: gpio at 4004d000 {
+				compatible = "fsl,mvf-gpio";
+				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+				interrupts = <0 111 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 128 7>;
+			};
+
+			anatop at 40050000 {
+				compatible = "fsl,mvf-anatop";
+				reg = <0x40050000 0x1000>;
+			};
+
+			clks: ccm at 4006b000 {
+				compatible = "fsl,mvf-ccm";
+				reg = <0x4006b000 0x1000>;
+				#clock-cells = <1>;
+			};
+
+		};
+
+		aips1: aips-bus at 40080000 { /* AIPS1 */
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40080000 0x80000>;
+			ranges;
+
+			uart4: serial at 400a9000 { /* UART4 */
+				compatible = "fsl,mvf-uart";
+				reg = <0x400a9000 0x1000>;
+				interrupts = <0 65 0x04>;
+				clocks = <&clks 43>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart5: serial at 400aa000 { /* UART5 */
+				compatible = "fsl,mvf-uart";
+				reg = <0x400aa000 0x1000>;
+				interrupts = <0 66 0x04>;
+				clocks = <&clks 44>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			fec0: ethernet at 400d0000 {
+				compatible = "fsl,mvf-fec";
+				reg = <0x400d0000 0x1000>;
+				interrupts = <0 78 0x04>;
+				clocks = <&clks 69>, <&clks 69>, <&clks 69>;
+				clock-names = "ipg", "ahb", "ptp";
+			};
+
+			fec1: ethernet at 400d1000 {
+				compatible = "fsl,mvf-fec";
+				reg = <0x400d1000 0x1000>;
+				interrupts = <0 79 0x04>;
+				clocks = <&clks 69>, <&clks 69>, <&clks 69>;
+				clock-names = "ipg", "ahb", "ptp";
+			};
+
+		};
+	};
+};
-- 
1.8.0




From linux at arm.linux.org.uk  Thu May  2 04:22:18 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 09:22:18 +0100
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130430081739.GP14496@n2100.arm.linux.org.uk>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
Message-ID: <20130502082218.GA21614@n2100.arm.linux.org.uk>

On Tue, Apr 30, 2013 at 09:17:39AM +0100, Russell King - ARM Linux wrote:
> Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> source of errors.
> 
> OMAP stuff needs a serious look at too - much Kconfig madness there
> caused by over-use of select, which then goes on to cause build errors
> because it assumes some stuff is always enabled.
> 
> There's also warnings about of_device_id from include/linux/of_platform.h
> via from arch/arm/kernel/setup.c which feature in all the non-OF builds
> too which need addressing.
> 
> See todays http://www.arm.linux.org.uk/developer/build/ results for all
> the details and configs.  Not pushing my tree until some of this stuff
> gets fixed.

And now we have a new bunch of warnings from OMAP stuff which weren't
previously there...

arch/arm/mach-omap2/omap_device.c: In function 'omap_device_get_by_hwmod_name':
arch/arm/mach-omap2/omap_device.c:821:3: warning: return makes pointer from integer without a cast
arch/arm/mach-omap2/omap_device.c:826:3: warning: return makes pointer from integer without a cast
drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result

include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event' defined but not used


From b35083 at freescale.com  Thu May  2 03:41:46 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 2 May 2013 15:41:46 +0800
Subject: [PATCH V2] tty/serial/mvf: add MVF uart driver support
Message-ID: <1367480506-13220-1-git-send-email-b35083@freescale.com>

It adds Freescale Vybrid Family uart driver support

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
V2:
  Remove unused variables and clean up the code
  based on the comments for last version.

 drivers/tty/serial/Kconfig       |   17 +
 drivers/tty/serial/Makefile      |    1 +
 drivers/tty/serial/mvf.c         | 1053 ++++++++++++++++++++++++++++++++++++++
 include/uapi/linux/serial_core.h |    3 +
 4 files changed, 1074 insertions(+)
 create mode 100644 drivers/tty/serial/mvf.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..032df6f 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -574,6 +574,23 @@ config SERIAL_IMX_CONSOLE
 	  your boot loader (lilo or loadlin) about how to pass options to the
 	  kernel at boot time.)
 
+config SERIAL_MVF
+	bool "Freescale Vybrid serial port support"
+	depends on SOC_MVF600
+	select SERIAL_CORE
+	select RATIONAL
+	help
+	  If you have a machine based on a Freescale Vybrid CPU you
+	  can enable its onboard serial port by enabling this option.
+
+config SERIAL_MVF_CONSOLE
+	bool "Console on Vybrid serial port"
+	depends on SERIAL_MVF
+	select SERIAL_CORE_CONSOLE
+	help
+	  If you have enabled the serial port on the Freescale Vybrid family
+	  CPU you can make it the console by answering Y to this option.
+
 config SERIAL_UARTLITE
 	tristate "Xilinx uartlite serial port support"
 	depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index eedfec4..be2ed68 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
 obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
 obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
 obj-$(CONFIG_SERIAL_IMX) += imx.o
+obj-$(CONFIG_SERIAL_MVF) += mvf.o
 obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
 obj-$(CONFIG_SERIAL_ICOM) += icom.o
 obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
diff --git a/drivers/tty/serial/mvf.c b/drivers/tty/serial/mvf.c
new file mode 100644
index 0000000..e265e14
--- /dev/null
+++ b/drivers/tty/serial/mvf.c
@@ -0,0 +1,1053 @@
+/*
+ *  Driver for Freescale Vybrid Family serial ports
+ *
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if defined(CONFIG_SERIAL_MVF_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/rational.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/io.h>
+#include <asm/irq.h>
+#include <linux/platform_data/serial-imx.h>
+
+/* All uart module registers for MVF is 8-bit width */
+#define MXC_UARTBDH		0x00 /* Baud rate reg: high */
+#define MXC_UARTBDL		0x01 /* Baud rate reg: low */
+#define MXC_UARTCR1		0x02 /* Control reg 1 */
+#define MXC_UARTCR2		0x03 /* Control reg 2 */
+#define MXC_UARTSR1		0x04 /* Status reg 1 */
+#define MXC_UARTSR2		0x05 /* Status reg 2 */
+#define MXC_UARTCR3		0x06 /* Control reg 3 */
+#define MXC_UARTDR		0x07 /* Data reg */
+#define MXC_UARTMAR1		0x08 /* Match address reg 1 */
+#define MXC_UARTMAR2		0x09 /* Match address reg 2 */
+#define MXC_UARTCR4		0x0A /* Control reg 4 */
+#define MXC_UARTCR5		0x0B /* Control reg 5 */
+#define MXC_UARTEDR		0x0C /* Extended data reg */
+#define MXC_UARTMODEM		0x0D /* Modem reg */
+#define MXC_UARTIR		0x0E /* Infrared reg */
+#define MXC_UARTPFIFO		0x10 /* FIFO parameter reg */
+#define MXC_UARTCFIFO		0x11 /* FIFO control reg */
+#define MXC_UARTSFIFO		0x12 /* FIFO status reg */
+#define MXC_UARTTWFIFO		0x13 /* FIFO transmit watermark reg */
+#define MXC_UARTTCFIFO		0x14 /* FIFO transmit count reg */
+#define MXC_UARTRWFIFO		0x15 /* FIFO receive watermark reg */
+#define MXC_UARTRCFIFO		0x16 /* FIFO receive count reg */
+#define MXC_UARTC7816		0x18 /* 7816 control reg */
+#define MXC_UARTIE7816		0x19 /* 7816 interrupt enable reg */
+#define MXC_UARTIS7816		0x1A /* 7816 interrupt status reg */
+#define MXC_UARTWP7816T0	0x1B /* 7816 wait parameter reg */
+#define MXC_UARTWP7816T1	0x1B /* 7816 wait parameter reg */
+#define MXC_UARTWN7816		0x1C /* 7816 wait N reg */
+#define MXC_UARTWF7816		0x1D /* 7816 wait FD reg */
+#define MXC_UARTET7816		0x1E /* 7816 error threshold reg */
+#define MXC_UARTTL7816		0x1F /* 7816 transmit length reg */
+#define MXC_UARTCR6		0x21 /* CEA709.1-B contrl reg */
+#define MXC_UARTPCTH		0x22 /* CEA709.1-B packet cycle counter high */
+#define MXC_UARTPCTL		0x23 /* CEA709.1-B packet cycle counter low */
+#define MXC_UARTB1T		0x24 /* CEA709.1-B beta 1 time */
+#define MXC_UARTSDTH		0x25 /* CEA709.1-B secondary delay timer high */
+#define MXC_UARTSDTL		0x26 /* CEA709.1-B secondary delay timer low */
+#define MXC_UARTPRE		0x27 /* CEA709.1-B preamble */
+#define MXC_UARTTPL		0x28 /* CEA709.1-B transmit packet length */
+#define MXC_UARTIE		0x29 /* CEA709.1-B transmit interrupt enable */
+#define MXC_UARTSR3		0x2B /* CEA709.1-B status reg */
+#define MXC_UARTSR4		0x2C /* CEA709.1-B status reg */
+#define MXC_UARTRPL		0x2D /* CEA709.1-B received packet length */
+#define MXC_UARTRPREL		0x2E /* CEA709.1-B received preamble length */
+#define MXC_UARTCPW		0x2F /* CEA709.1-B collision pulse width */
+#define MXC_UARTRIDT		0x30 /* CEA709.1-B receive indeterminate time */
+#define MXC_UARTTIDT		0x31 /* CEA709.1-B transmit indeterminate time*/
+
+/* Bit definations of BDH */
+#define MXC_UARTBDH_LBKDIE	0x80 /* LIN break detect interrupt enable */
+#define MXC_UARTBDH_RXEDGIE	0x40 /* RxD input Active edge interrupt enable*/
+#define MXC_UARTBDH_SBR_MASK	0x1f /* Uart baud rate high 5-bits */
+/* Bit definations of CR1 */
+#define MXC_UARTCR1_LOOPS	0x80 /* Loop mode select */
+#define MXC_UARTCR1_RSRC	0x20 /* Receiver source select */
+#define MXC_UARTCR1_M		0x10 /* 9-bit 8-bit mode select */
+#define MXC_UARTCR1_WAKE	0x08 /* Receiver wakeup method */
+#define MXC_UARTCR1_ILT		0x04 /* Idle line type */
+#define MXC_UARTCR1_PE		0x02 /* Parity enable */
+#define MXC_UARTCR1_PT		0x01 /* Parity type */
+/* Bit definations of CR2 */
+#define MXC_UARTCR2_TIE		0x80 /* Tx interrupt or DMA request enable */
+#define MXC_UARTCR2_TCIE	0x40 /* Transmission complete int enable */
+#define MXC_UARTCR2_RIE		0x20 /* Rx full int or DMA request enable */
+#define MXC_UARTCR2_ILIE	0x10 /* Idle line interrupt enable */
+#define MXC_UARTCR2_TE		0x08 /* Transmitter enable */
+#define MXC_UARTCR2_RE		0x04 /* Receiver enable */
+#define MXC_UARTCR2_RWU		0x02 /* Receiver wakeup control */
+#define MXC_UARTCR2_SBK		0x01 /* Send break */
+/* Bit definations of SR1 */
+#define MXC_UARTSR1_TDRE	0x80 /* Tx data reg empty */
+#define MXC_UARTSR1_TC		0x40 /* Transmit complete */
+#define MXC_UARTSR1_RDRF	0x20 /* Rx data reg full */
+#define MXC_UARTSR1_IDLE	0x10 /* Idle line flag */
+#define MXC_UARTSR1_OR		0x08 /* Receiver overrun */
+#define MXC_UARTSR1_NF		0x04 /* Noise flag */
+#define MXC_UARTSR1_FE		0x02 /* Frame error */
+#define MXC_UARTSR1_PE		0x01 /* Parity error */
+/* Bit definations of SR2 */
+#define MXC_UARTSR2_LBKDIF	0x80 /* LIN brk detect interrupt flag */
+#define MXC_UARTSR2_RXEDGIF	0x40 /* RxD pin active edge interrupt flag */
+#define MXC_UARTSR2_MSBF	0x20 /* MSB first */
+#define MXC_UARTSR2_RXINV	0x10 /* Receive data inverted */
+#define MXC_UARTSR2_RWUID	0x08 /* Receive wakeup idle detect */
+#define MXC_UARTSR2_BRK13	0x04 /* Break transmit character length */
+#define MXC_UARTSR2_LBKDE	0x02 /* LIN break detection enable */
+#define MXC_UARTSR2_RAF		0x01 /* Receiver active flag */
+/* Bit definations of CR3 */
+#define MXC_UARTCR3_R8		0x80 /* Received bit8, for 9-bit data format */
+#define MXC_UARTCR3_T8		0x40 /* transmit bit8, for 9-bit data format */
+#define MXC_UARTCR3_TXDIR	0x20 /* Tx pin direction in single-wire mode */
+#define MXC_UARTCR3_TXINV	0x10 /* Transmit data inversion */
+#define MXC_UARTCR3_ORIE	0x08 /* Overrun error interrupt enable */
+#define MXC_UARTCR3_NEIE	0x04 /* Noise error interrupt enable */
+#define MXC_UARTCR3_FEIE	0x02 /* Framing error interrupt enable */
+#define MXC_UARTCR3_PEIE	0x01 /* Parity errror interrupt enable */
+/* Bit definations of CR4 */
+#define MXC_UARTCR4_MAEN1	0x80 /* Match address mode enable 1 */
+#define MXC_UARTCR4_MAEN2	0x40 /* Match address mode enable 2 */
+#define MXC_UARTCR4_M10		0x20 /* 10-bit mode select */
+#define MXC_UARTCR4_BRFA_MASK	0x1F /* Baud rate fine adjust */
+#define MXC_UARTCR4_BRFA_OFF	0
+/* Bit definations of CR5 */
+#define MXC_UARTCR5_TDMAS	0x80 /* Transmitter DMA select */
+#define MXC_UARTCR5_RDMAS	0x20 /* Receiver DMA select */
+/* Bit definations of Modem */
+#define MXC_UARTMODEM_RXRTSE	0x08 /* Enable receiver request-to-send */
+#define MXC_UARTMODEM_TXRTSPOL	0x04 /* Select transmitter RTS polarity */
+#define MXC_UARTMODEM_TXRTSE	0x02 /* Enable transmitter request-to-send */
+#define MXC_UARTMODEM_TXCTSE	0x01 /* Enable transmitter CTS clear-to-send */
+/* Bit definations of EDR */
+#define MXC_UARTEDR_NOISY	0x80 /* Current dataword received with noise */
+#define MXC_UARTEDR_PARITYE	0x40 /* Dataword received with parity error */
+/* Bit definations of Infrared reg(IR) */
+#define MXC_UARTIR_IREN		0x04 /* Infrared enable */
+#define MXC_UARTIR_TNP_MASK	0x03 /* Transmitter narrow pluse */
+#define MXC_UARTIR_TNP_OFF	0
+/* Bit definations of FIFO parameter reg */
+#define MXC_UARTPFIFO_TXFE	0x80 /* Transmit fifo enable */
+#define MXC_UARTPFIFO_FIFOSIZE_MASK	0x7
+#define MXC_UARTPFIFO_TXFIFOSIZE_OFF	4
+#define MXC_UARTPFIFO_RXFE	0x08 /* Receiver fifo enable */
+#define MXC_UARTPFIFO_RXFIFOSIZE_OFF	0
+/* Bit definations of FIFO control reg */
+#define MXC_UARTCFIFO_TXFLUSH	0x80 /* Transmit FIFO/buffer flush */
+#define MXC_UARTCFIFO_RXFLUSH	0x40 /* Receive FIFO/buffer flush */
+#define MXC_UARTCFIFO_RXOFE	0x04 /* Receive fifo overflow INT enable */
+#define MXC_UARTCFIFO_TXOFE	0x02 /* Transmit fifo overflow INT enable */
+#define MXC_UARTCFIFO_RXUFE	0x01 /* Receive fifo underflow INT enable */
+/* Bit definations of FIFO status reg */
+#define MXC_UARTSFIFO_TXEMPT	0x80 /* Transmit fifo/buffer empty */
+#define MXC_UARTSFIFO_RXEMPT	0x40 /* Receive fifo/buffer empty */
+#define MXC_UARTSFIFO_RXOF	0x04 /* Rx buffer overflow flag */
+#define MXC_UARTSFIFO_TXOF	0x02 /* Tx buffer overflow flag */
+#define MXC_UARTSFIFO_RXUF	0x01 /* Rx buffer underflow flag */
+
+
+/* follow IMX dev node number */
+#define SERIAL_IMX_MAJOR	207
+#define MINOR_START		24
+#define DEV_NAME		"ttymxc"
+#define DRIVER_NAME		"MVF-uart"
+#define UART_NR			6
+
+struct mvf_port {
+	struct uart_port	port;
+	struct clk		*clk;
+	unsigned int		tx_fifo_size, rx_fifo_size;
+};
+
+enum mvf_uart_type {
+	MVF600_UART,
+};
+
+struct mvf_uart_data {
+	enum mvf_uart_type devtype;
+};
+
+static struct mvf_uart_data mvf_uart_devdata[] = {
+	[MVF600_UART] = {
+		.devtype = MVF600_UART,
+	},
+};
+
+static struct platform_device_id mvf_uart_devtype[] = {
+	{
+		.name = "mvf600-uart",
+		.driver_data = (kernel_ulong_t) &mvf_uart_devdata[MVF600_UART],
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(platform, mvf_uart_devtype);
+
+static struct of_device_id mvf_uart_dt_ids[] = {
+	{
+		.compatible = "fsl,mvf-uart",
+		.data = &mvf_uart_devdata[MVF600_UART],
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mvf_uart_dt_ids);
+
+/*
+ * interrupts disabled on entry
+ */
+static void mvf_stop_tx(struct uart_port *port)
+{
+	struct mvf_port *sport = (struct mvf_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + MXC_UARTCR2);
+	temp &= ~(MXC_UARTCR2_TIE | MXC_UARTCR2_TCIE);
+	writeb(temp, sport->port.membase + MXC_UARTCR2);
+}
+
+/*
+ * interrupts disabled on entry
+ */
+static void mvf_stop_rx(struct uart_port *port)
+{
+	struct mvf_port *sport = (struct mvf_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + MXC_UARTCR2);
+	writeb(temp & ~MXC_UARTCR2_RE, sport->port.membase + MXC_UARTCR2);
+}
+
+ /* modem status update function */
+static void mvf_enable_ms(struct uart_port *port)
+{
+}
+
+static inline void mvf_transmit_buffer(struct mvf_port *sport)
+{
+	struct circ_buf *xmit = &sport->port.state->xmit;
+
+	while (!uart_circ_empty(xmit) &&
+	(readb(sport->port.membase + MXC_UARTTCFIFO) < sport->tx_fifo_size)) {
+		/* send out xmit->buf[xmit->tail] */
+		writeb(xmit->buf[xmit->tail], sport->port.membase + MXC_UARTDR);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		sport->port.icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+	if (uart_circ_empty(xmit))
+		mvf_stop_tx(&sport->port);
+}
+
+static void mvf_start_tx(struct uart_port *port)
+{
+	struct mvf_port *sport = (struct mvf_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + MXC_UARTCR2);
+	writeb(temp | MXC_UARTCR2_TIE,
+			sport->port.membase + MXC_UARTCR2);
+
+	if (readb(sport->port.membase + MXC_UARTSR1) & MXC_UARTSR1_TDRE)
+		mvf_transmit_buffer(sport);
+}
+
+
+static irqreturn_t mvf_txint(int irq, void *dev_id)
+{
+	struct mvf_port *sport = dev_id;
+	struct circ_buf *xmit = &sport->port.state->xmit;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+	if (sport->port.x_char) {
+		/* Send next char */
+		writeb(sport->port.x_char, sport->port.membase + MXC_UARTDR);
+		goto out;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
+		mvf_stop_tx(&sport->port);
+		goto out;
+	}
+
+	mvf_transmit_buffer(sport);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mvf_rxint(int irq, void *dev_id)
+{
+	struct mvf_port *sport = dev_id;
+	unsigned int flg, ignored = 0;
+	struct tty_port *port = &sport->port.state->port;
+	unsigned long flags;
+	unsigned char r8, rx, sr;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	while (!(readb(sport->port.membase + MXC_UARTSFIFO) &
+				MXC_UARTSFIFO_RXEMPT)) {
+		flg = TTY_NORMAL;
+		sport->port.icount.rx++;
+
+		/*  To clear the FE, OR, NF, FE, PE flags when set,
+		 *  read SR1 then read DR
+		 */
+		sr = readb(sport->port.membase + MXC_UARTSR1);
+
+		r8 = readb(sport->port.membase + MXC_UARTCR3) & MXC_UARTCR3_R8;
+		rx = readb(sport->port.membase + MXC_UARTDR);
+
+		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
+			continue;
+		if (sr & (MXC_UARTSR1_PE | MXC_UARTSR1_OR | MXC_UARTSR1_FE)) {
+			if (sr & MXC_UARTSR1_PE)
+				sport->port.icount.parity++;
+			else if (sr & MXC_UARTSR1_FE)
+				sport->port.icount.frame++;
+			if (sr & MXC_UARTSR1_OR)
+				sport->port.icount.overrun++;
+
+			if (sr & sport->port.ignore_status_mask) {
+				if (++ignored > 100)
+					goto out;
+				continue;
+			}
+
+			sr &= sport->port.read_status_mask;
+
+			if (sr & MXC_UARTSR1_PE)
+				flg = TTY_PARITY;
+			else if (sr & MXC_UARTSR1_FE)
+				flg = TTY_FRAME;
+			if (sr & MXC_UARTSR1_OR)
+				flg = TTY_OVERRUN;
+
+#ifdef SUPPORT_SYSRQ
+			sport->port.sysrq = 0;
+#endif
+		}
+
+		tty_insert_flip_char(port, rx, flg);
+	}
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+
+	tty_flip_buffer_push(port);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mvf_int(int irq, void *dev_id)
+{
+	struct mvf_port *sport = dev_id;
+	unsigned int sts;
+
+	sts = readb(sport->port.membase + MXC_UARTSR1);
+
+	if (sts & MXC_UARTSR1_RDRF)
+		mvf_rxint(irq, dev_id);
+
+	if (sts & MXC_UARTSR1_TDRE &&
+		!(readb(sport->port.membase + MXC_UARTCR5) & MXC_UARTCR5_TDMAS))
+		mvf_txint(irq, dev_id);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Return TIOCSER_TEMT when transmitter is not busy.
+ */
+static unsigned int mvf_tx_empty(struct uart_port *port)
+{
+
+	return (readb(port->membase + MXC_UARTSR1) & MXC_UARTSR1_TC) ?
+		TIOCSER_TEMT : 0;
+}
+
+static unsigned int mvf_get_mctrl(struct uart_port *port)
+{
+	unsigned int tmp = 0;
+	unsigned char reg;
+
+	reg = readb(port->membase + MXC_UARTMODEM);
+	if (reg & MXC_UARTMODEM_TXCTSE)
+		tmp |= TIOCM_CTS;
+
+	if (reg & MXC_UARTMODEM_RXRTSE)
+		tmp |= TIOCM_RTS;
+
+	return tmp;
+}
+
+static void mvf_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	unsigned long temp;
+
+	temp = readb(port->membase + MXC_UARTMODEM) &
+			~(MXC_UARTMODEM_RXRTSE | MXC_UARTMODEM_TXCTSE);
+
+	if (mctrl & TIOCM_RTS)
+		temp |= MXC_UARTMODEM_RXRTSE;
+	if (mctrl & TIOCM_CTS)
+		temp |= MXC_UARTMODEM_TXCTSE;
+
+	writeb(temp, port->membase + MXC_UARTMODEM);
+}
+
+/*
+ * Interrupts always disabled.
+ */
+static void mvf_break_ctl(struct uart_port *port, int break_state)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + MXC_UARTCR2) & ~MXC_UARTCR2_SBK;
+
+	if (break_state != 0)
+		temp |= MXC_UARTCR2_SBK;
+
+	writeb(temp, port->membase + MXC_UARTCR2);
+
+}
+
+/* Tx and Rx FIFO watermark */
+#define TXTL 2
+#define RXTL 1
+
+static void mvf_setup_watermark(struct mvf_port *sport)
+{
+	unsigned char val, old_cr2, cr2;
+
+	/* set receiver/transmitter trigger level. */
+	old_cr2 = cr2 = readb(sport->port.membase + MXC_UARTCR2);
+	cr2 &= ~(MXC_UARTCR2_TIE | MXC_UARTCR2_TCIE | MXC_UARTCR2_TE |
+			MXC_UARTCR2_RIE | MXC_UARTCR2_RE);
+	writeb(cr2, sport->port.membase + MXC_UARTCR2);
+
+	writeb(TXTL, sport->port.membase + MXC_UARTTWFIFO);
+	writeb(RXTL, sport->port.membase + MXC_UARTRWFIFO);
+
+	/* determine FIFO size and enable */
+	val = readb(sport->port.membase + MXC_UARTPFIFO);
+
+	sport->tx_fifo_size = 0x1 << (((val >> MXC_UARTPFIFO_TXFIFOSIZE_OFF) &
+		MXC_UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	sport->rx_fifo_size = 0x1 << (((val >> MXC_UARTPFIFO_RXFIFOSIZE_OFF) &
+		MXC_UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	writeb(val | MXC_UARTPFIFO_TXFE | MXC_UARTPFIFO_RXFE,
+			sport->port.membase + MXC_UARTPFIFO);
+
+	/* Flush the Tx and Rx FIFO to a known state */
+	writeb(MXC_UARTCFIFO_TXFLUSH | MXC_UARTCFIFO_RXFLUSH,
+			sport->port.membase + MXC_UARTCFIFO);
+
+	/* restore CR2 */
+	writeb(old_cr2, sport->port.membase + MXC_UARTCR2);
+
+}
+
+
+static int mvf_startup(struct uart_port *port)
+{
+	struct mvf_port *sport = (struct mvf_port *)port;
+	int retval;
+	unsigned long flags, temp;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	mvf_setup_watermark(sport);
+
+	temp = readb(sport->port.membase + MXC_UARTCR2);
+	writeb(temp & ~MXC_UARTCR2_RIE, sport->port.membase + MXC_UARTCR2);
+
+	/* clear and enable interrupts */
+	temp = readb(sport->port.membase + MXC_UARTCR2);
+	temp |= MXC_UARTCR2_RIE | MXC_UARTCR2_TIE;
+	writeb(temp, sport->port.membase + MXC_UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	/*
+	 * request the IRQ: Vybrid chips only have one interrupt.
+	 */
+	retval = devm_request_irq(port->dev, port->irq, mvf_int, 0,
+				DRIVER_NAME, sport);
+	if (retval)
+		return retval;
+
+	return 0;
+}
+
+static void mvf_shutdown(struct uart_port *port)
+{
+	struct mvf_port *sport = container_of(port, struct mvf_port, port);
+	unsigned char temp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	temp = readb(port->membase + MXC_UARTCR2);
+	temp &= ~(MXC_UARTCR2_TE | MXC_UARTCR2_RE);
+	writeb(temp, port->membase + MXC_UARTCR2);
+	/*
+	 * Disable all interrupts, port and break condition.
+	 */
+	temp = readb(port->membase + MXC_UARTCR2);
+	temp &= ~(MXC_UARTCR2_TIE | MXC_UARTCR2_TCIE | MXC_UARTCR2_RIE);
+	writeb(temp, port->membase + MXC_UARTCR2);
+	spin_unlock_irqrestore(&port->lock, flags);
+	/*
+	 * Free the irq
+	 */
+	devm_free_irq(port->dev, port->irq, sport);
+}
+
+static void
+mvf_set_termios(struct uart_port *port, struct ktermios *termios,
+		   struct ktermios *old)
+{
+	struct mvf_port *sport = container_of(port, struct mvf_port, port);
+	unsigned long flags;
+	unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+	unsigned int  baud;
+	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+	unsigned int sbr, brfa;
+
+	cr1 = old_cr1 = readb(sport->port.membase + MXC_UARTCR1);
+	old_cr2 = readb(sport->port.membase + MXC_UARTCR2);
+	cr4 = readb(sport->port.membase + MXC_UARTCR4);
+	bdh = readb(sport->port.membase + MXC_UARTBDH);
+	modem = readb(sport->port.membase + MXC_UARTMODEM);
+
+	/*
+	 * We only support CS8 and CS7,but CS7 must enable PE.
+	 * supported mode:
+	 *  - (7,e/o,1)
+	 *  - (8,n,1)
+	 *  - (8,m/s,1)
+	 *  - (8,e/o,1)
+	 */
+	while ((termios->c_cflag & CSIZE) != CS8 &&
+		(termios->c_cflag & CSIZE) != CS7) {
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= old_csize;
+		old_csize = CS8;
+	}
+
+	if ((termios->c_cflag & CSIZE) == CS8 ||
+		(termios->c_cflag & CSIZE) == CS7)
+		cr1 = old_cr1 & ~MXC_UARTCR1_M;
+
+	if (termios->c_cflag & CMSPAR) {
+		if ((termios->c_cflag & CSIZE) != CS8) {
+			termios->c_cflag &= ~CSIZE;
+			termios->c_cflag |= CS8;
+		}
+		cr1 |= MXC_UARTCR1_M;
+	}
+
+	if (termios->c_cflag & CRTSCTS) {
+		modem |= (MXC_UARTMODEM_RXRTSE | MXC_UARTMODEM_TXCTSE);
+
+	} else {
+		termios->c_cflag &= ~CRTSCTS;
+		modem &= ~(MXC_UARTMODEM_RXRTSE | MXC_UARTMODEM_TXCTSE);
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		termios->c_cflag &= ~CSTOPB;
+
+	/* parity must enable when CS7 to match 8-bits format */
+	if ((termios->c_cflag & CSIZE) == CS7)
+		termios->c_cflag |= PARENB;
+
+	if ((termios->c_cflag & PARENB)) {
+		if (termios->c_cflag & CMSPAR) {
+			cr1 &= ~MXC_UARTCR1_PE;
+			cr1 |= MXC_UARTCR1_M;
+		} else {
+			cr1 |= MXC_UARTCR1_PE;
+			if ((termios->c_cflag & CSIZE) == CS8)
+				cr1 |= MXC_UARTCR1_M;
+			if (termios->c_cflag & PARODD)
+				cr1 |= MXC_UARTCR1_PT;
+			else
+				cr1 &= ~MXC_UARTCR1_PT;
+		}
+	}
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	sport->port.read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		sport->port.read_status_mask |=
+					(MXC_UARTSR1_FE | MXC_UARTSR1_PE);
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		sport->port.read_status_mask |= MXC_UARTSR1_FE;
+
+	/*
+	 * Characters to ignore
+	 */
+	sport->port.ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		sport->port.ignore_status_mask |= MXC_UARTSR1_PE;
+	if (termios->c_iflag & IGNBRK) {
+		sport->port.ignore_status_mask |= MXC_UARTSR1_FE;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			sport->port.ignore_status_mask |= MXC_UARTSR1_OR;
+	}
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/* wait transmit engin complete */
+	while (!(readb(sport->port.membase + MXC_UARTSR1) & MXC_UARTSR1_TC))
+		barrier();
+
+	writeb(old_cr2 & ~(MXC_UARTCR2_TE | MXC_UARTCR2_RE),
+			sport->port.membase + MXC_UARTCR2);
+
+	/* disable transmit and receive */
+	sbr = sport->port.uartclk / (16 * baud);
+	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
+
+	bdh &= ~MXC_UARTBDH_SBR_MASK;
+	bdh |= (sbr >> 8) & 0x1F;
+
+	cr4 &= ~MXC_UARTCR4_BRFA_MASK;
+	brfa &= MXC_UARTCR4_BRFA_MASK;
+	writeb(cr4 | brfa, sport->port.membase + MXC_UARTCR4);
+	writeb(bdh, sport->port.membase + MXC_UARTBDH);
+	writeb(sbr & 0xFF, sport->port.membase + MXC_UARTBDL);
+	writeb(cr1, sport->port.membase + MXC_UARTCR1);
+	writeb(modem, sport->port.membase + MXC_UARTMODEM);
+
+	/* restore control register */
+	writeb(old_cr2, sport->port.membase + MXC_UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
+static const char *mvf_type(struct uart_port *port)
+{
+	return port->type == PORT_MVF ? "MVF" : NULL;
+}
+
+static void mvf_release_port(struct uart_port *port)
+{
+	/* Nothing to do */
+}
+
+static int mvf_request_port(struct uart_port *port)
+{
+	return  0;
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void mvf_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE)
+		port->type = PORT_MVF;
+}
+
+/*
+ * Verify the new serial_struct (for TIOCSSERIAL).
+ * The only change we allow are to the flags and type, and
+ * even then only between PORT_MVF and PORT_UNKNOWN
+ */
+static int
+mvf_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_MVF)
+		ret = -EINVAL;
+	if (port->irq != ser->irq)
+		ret = -EINVAL;
+	if (ser->io_type != UPIO_MEM)
+		ret = -EINVAL;
+	if (port->uartclk / 16 != ser->baud_base)
+		ret = -EINVAL;
+	if (port->iobase != ser->port)
+		ret = -EINVAL;
+	if (ser->hub6 != 0)
+		ret = -EINVAL;
+	return ret;
+}
+
+
+static struct uart_ops mvf_pops = {
+	.tx_empty	= mvf_tx_empty,
+	.set_mctrl	= mvf_set_mctrl,
+	.get_mctrl	= mvf_get_mctrl,
+	.stop_tx	= mvf_stop_tx,
+	.start_tx	= mvf_start_tx,
+	.stop_rx	= mvf_stop_rx,
+	.enable_ms	= mvf_enable_ms,
+	.break_ctl	= mvf_break_ctl,
+	.startup	= mvf_startup,
+	.shutdown	= mvf_shutdown,
+	.set_termios	= mvf_set_termios,
+	.type		= mvf_type,
+	.release_port	= mvf_release_port,
+	.request_port	= mvf_request_port,
+	.config_port	= mvf_config_port,
+	.verify_port	= mvf_verify_port,
+};
+
+static struct mvf_port *mvf_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_MVF_CONSOLE
+static void mvf_console_putchar(struct uart_port *port, int ch)
+{
+	while (!(readb(port->membase + MXC_UARTSR1) & MXC_UARTSR1_TDRE))
+		barrier();
+
+	writeb(ch, port->membase + MXC_UARTDR);
+}
+
+static void
+mvf_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct mvf_port *sport = mvf_ports[co->index];
+	unsigned int  old_cr2, cr2;
+
+	/*
+	 * First, save CR2 and then disable interrupts
+	 */
+	cr2 = old_cr2 = readb(sport->port.membase + MXC_UARTCR2);
+
+	cr2 |= (MXC_UARTCR2_TE |  MXC_UARTCR2_RE);
+	cr2 &= ~(MXC_UARTCR2_TIE | MXC_UARTCR2_TCIE | MXC_UARTCR2_RIE);
+
+	writeb(cr2, sport->port.membase + MXC_UARTCR2);
+
+	uart_console_write(&sport->port, s, count, mvf_console_putchar);
+
+	/*
+	 * wait for transmitter finish complete and restore CR2
+	 */
+	while (!(readb(sport->port.membase + MXC_UARTSR1) & MXC_UARTSR1_TC))
+		;
+
+	writeb(old_cr2, sport->port.membase + MXC_UARTCR2);
+}
+
+/*
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+mvf_console_get_options(struct mvf_port *sport, int *baud,
+			   int *parity, int *bits)
+{
+	unsigned char cr, bdh, bdl, brfa;
+	unsigned int sbr, uartclk;
+	unsigned int baud_raw;
+
+	cr = readb(sport->port.membase + MXC_UARTCR2);
+	cr &= MXC_UARTCR2_TE | MXC_UARTCR2_RE;
+	if (!cr)
+		return;
+
+	/* ok, the port was enabled */
+
+	cr = readb(sport->port.membase + MXC_UARTCR1);
+
+	*parity = 'n';
+	if (cr & MXC_UARTCR1_PE) {
+		if (cr & MXC_UARTCR1_PT)
+			*parity = 'o';
+		else
+			*parity = 'e';
+	}
+
+	if (cr & MXC_UARTCR1_M)
+		*bits = 9;
+	else
+		*bits = 8;
+
+	bdh = readb(sport->port.membase + MXC_UARTBDH);
+	bdh &= MXC_UARTBDH_SBR_MASK;
+	bdl = readb(sport->port.membase + MXC_UARTBDL);
+	sbr = bdh;
+	sbr <<= 8;
+	sbr |= bdl;
+	brfa = readb(sport->port.membase + MXC_UARTCR4);
+	brfa &= MXC_UARTCR4_BRFA_MASK;
+
+	uartclk = clk_get_rate(sport->clk);
+	/*
+	 * Baud = mod_clk/(16*(sbr[13]+(brfa)/32)
+	 */
+	baud_raw = uartclk / (16 * (sbr + brfa / 32));
+
+	if (*baud != baud_raw)
+		printk(KERN_INFO "Serial: Console MVF rounded baud rate"
+				"from %d to %d\n", baud_raw, *baud);
+}
+
+static int __init
+mvf_console_setup(struct console *co, char *options)
+{
+	struct mvf_port *sport;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index == -1 || co->index >= ARRAY_SIZE(mvf_ports))
+		co->index = 0;
+	sport = mvf_ports[co->index];
+
+	if (sport == NULL)
+		return -ENODEV;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		mvf_console_get_options(sport, &baud, &parity, &bits);
+
+	mvf_setup_watermark(sport);
+
+	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver mvf_reg;
+static struct console mvf_console = {
+	.name		= DEV_NAME,
+	.write		= mvf_console_write,
+	.device		= uart_console_device,
+	.setup		= mvf_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &mvf_reg,
+};
+
+#define MVF_CONSOLE	(&mvf_console)
+#else
+#define MVF_CONSOLE	NULL
+#endif
+
+static struct uart_driver mvf_reg = {
+	.owner          = THIS_MODULE,
+	.driver_name    = DRIVER_NAME,
+	.dev_name       = DEV_NAME,
+	.major          = SERIAL_IMX_MAJOR,
+	.minor          = MINOR_START,
+	.nr             = ARRAY_SIZE(mvf_ports),
+	.cons           = MVF_CONSOLE,
+};
+
+static int serial_mvf_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct mvf_port *sport = platform_get_drvdata(dev);
+
+	uart_suspend_port(&mvf_reg, &sport->port);
+
+	return 0;
+}
+
+static int serial_mvf_resume(struct platform_device *dev)
+{
+	struct mvf_port *sport = platform_get_drvdata(dev);
+
+	uart_resume_port(&mvf_reg, &sport->port);
+
+	return 0;
+}
+
+static int serial_mvf_probe_dt(struct mvf_port *sport,
+		struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+
+	if (!np)
+		return 1; /* no device tree device */
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+
+	return 0;
+}
+
+static int serial_mvf_probe(struct platform_device *pdev)
+{
+	struct mvf_port *sport;
+	void __iomem *base;
+	struct resource *res;
+	struct pinctrl *pinctrl;
+	int ret = 0;
+
+	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+	if (!sport)
+		return -ENOMEM;
+
+	pdev->dev.coherent_dma_mask = 0;
+
+	ret = serial_mvf_probe_dt(sport, pdev);
+	if (ret < 0)
+		return ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!base)
+		return -ENOMEM;
+
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl))
+		dev_warn(&pdev->dev,
+			"did not get pinctrl for uart%i error: %li\n",
+			sport->port.line, PTR_ERR(pinctrl));
+
+	sport->port.dev = &pdev->dev;
+	sport->port.mapbase = res->start;
+	sport->port.membase = base;
+	sport->port.type = PORT_MVF,
+	sport->port.iotype = UPIO_MEM;
+	sport->port.irq = platform_get_irq(pdev, 0);
+	sport->port.ops = &mvf_pops;
+	sport->port.flags = UPF_BOOT_AUTOCONF;
+
+	sport->clk = devm_clk_get(&pdev->dev, "ipg");
+	if (IS_ERR(sport->clk)) {
+		ret = PTR_ERR(sport->clk);
+		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+		return ret;
+	}
+
+	clk_prepare_enable(sport->clk);
+
+	sport->port.uartclk = clk_get_rate(sport->clk);
+
+	mvf_ports[sport->port.line] = sport;
+
+	platform_set_drvdata(pdev, &sport->port);
+
+	ret = uart_add_one_port(&mvf_reg, &sport->port);
+
+	if (ret)
+		goto clkput;
+
+	return 0;
+clkput:
+	clk_disable_unprepare(sport->clk);
+
+	return ret;
+}
+
+static int serial_mvf_remove(struct platform_device *pdev)
+{
+	struct mvf_port *sport = platform_get_drvdata(pdev);
+
+	uart_remove_one_port(&mvf_reg, &sport->port);
+
+	clk_disable_unprepare(sport->clk);
+
+	return 0;
+}
+
+static struct platform_driver serial_mvf_driver = {
+	.probe		= serial_mvf_probe,
+	.remove		= serial_mvf_remove,
+
+	.suspend	= serial_mvf_suspend,
+	.resume		= serial_mvf_resume,
+	.id_table       = mvf_uart_devtype,
+	.driver		= {
+		.name	= "mvf-uart",
+		.owner	= THIS_MODULE,
+		.of_match_table = mvf_uart_dt_ids,
+	},
+};
+
+static int __init mvf_serial_init(void)
+{
+	int ret;
+
+	pr_info("Serial: Freescale Vybrid Family driver\n");
+
+	ret = uart_register_driver(&mvf_reg);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&serial_mvf_driver);
+	if (ret != 0)
+		uart_unregister_driver(&mvf_reg);
+
+	return 0;
+}
+
+static void __exit mvf_serial_exit(void)
+{
+	platform_driver_unregister(&serial_mvf_driver);
+	uart_unregister_driver(&mvf_reg);
+}
+
+module_init(mvf_serial_init);
+module_exit(mvf_serial_exit);
+
+MODULE_DESCRIPTION("Freescale Vybrid Family serial port driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 74c2bf7..ffb7192 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -226,4 +226,7 @@
 /* Rocketport EXPRESS/INFINITY */
 #define PORT_RP2	102
 
+/* Freescale Vybrid uart */
+#define PORT_MVF	103
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
1.8.0




From b35083 at freescale.com  Thu May  2 03:48:51 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 2 May 2013 15:48:51 +0800
Subject: [PATCH V2 1/2] pinctrl/mvf: add MVF pinctrl driver
Message-ID: <1367480932-22318-1-git-send-email-b35083@freescale.com>

It adds Freescale Vybrid Family pin controller
driver to IMX iomuxc common driver framework.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
V2:
  Update the driver according to the IMX new pinctrl framework

 .../bindings/pinctrl/fsl,mvf-pinctrl.txt           |  48 +++
 drivers/pinctrl/Kconfig                            |   8 +
 drivers/pinctrl/Makefile                           |   1 +
 drivers/pinctrl/pinctrl-mvf.c                      | 337 +++++++++++++++++++++
 4 files changed, 394 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvf.c

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt
new file mode 100644
index 0000000..60f06cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt
@@ -0,0 +1,48 @@
+Freescale Vybrid IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Note:
+- On Vybrid, pin's mux mode and pad control are in one 32-bit register.
+  mux mode bits occupy bit[20:22] and config bits occupy bit[[0:15].
+  So the config word is a combination of mux_mode and pad control value.
+
+Required properties:
+- compatible: "fsl,mvf-iomuxc"
+- fsl,pins: A pin function macro with one argument, represents a group of
+  pin's mux and pad control setting.
+  The format is fsl,pins = < PIN_FUNC_ID(CONFIG) >, PIN_FUNC_ID is a pin
+  working on a specific function, CONFIG is the pad setting value such as
+  pull-up, spedd, ode and so on for this pin.
+  Please refer to Vybrid datasheet for the valid pad mux and control settings.
+
+CONFIG bits definition:
+PAD_MUX_MODE(x)			(x << 20)
+PAD_CTL_SPEED_LOW		(1 << 12)
+PAD_CTL_SPEED_MED		(2 << 12)
+PAD_CTL_SPEED_HIGH		(3 << 12)
+PAD_CTL_SRE_FAST		(1 << 11)
+PAD_CTL_SRE_SLOW		(0 << 11)
+PAD_CTL_ODE			(1 << 10)
+PAD_CTL_HYS			(1 << 9)
+PAD_CTL_DSE_DISABLE		(0 << 6)
+PAD_CTL_DSE_150ohm		(1 << 6)
+PAD_CTL_DSE_75ohm		(2 << 6)
+PAD_CTL_DSE_50ohm		(3 << 6)
+PAD_CTL_DSE_37ohm		(4 << 6)
+PAD_CTL_DSE_30ohm		(5 << 6)
+PAD_CTL_DSE_25ohm		(6 << 6)
+PAD_CTL_DSE_20ohm		(7 << 6)
+PAD_CTL_PUS_100K_DOWN		(0 << 4)
+PAD_CTL_PUS_47K_UP		(1 << 4)
+PAD_CTL_PUS_100K_UP		(2 << 4)
+PAD_CTL_PUS_22K_UP		(3 << 4)
+PAD_CTL_PKE			(1 << 3)
+PAD_CTL_PUE			(1 << 2)
+PAD_CTL_OBE_ENABLE		(1 << 1)
+PAD_CTL_IBE_ENABLE		(1 << 0)
+PAD_CTL_OBE_IBE_ENABLE		(3 << 0)
+
+Please refer to mvf600-pinfunc.h in device tree source folder
+for all available PIN_FUNC_ID for Vybrid.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f66924..885859c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -108,6 +108,14 @@ config PINCTRL_IMX6SL
 	help
 	  Say Y here to enable the imx6sl pinctrl driver
 
+config PINCTRL_MVF
+	bool "Vybrid pinctrl driver"
+	depends on OF
+	depends on SOC_MVF600
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the Freescale Vybrid pinctrl driver
+
 config PINCTRL_LANTIQ
 	bool
 	depends on LANTIQ
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 9bdaeb8..ec6d7b9 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
 obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
+obj-$(CONFIG_PINCTRL_MVF)	+= pinctrl-mvf.o
 
 obj-$(CONFIG_PLAT_ORION)        += mvebu/
 obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
diff --git a/drivers/pinctrl/pinctrl-mvf.c b/drivers/pinctrl/pinctrl-mvf.c
new file mode 100644
index 0000000..65041f9
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvf.c
@@ -0,0 +1,337 @@
+/*
+ * Vybrid pinctrl driver based on imx pinmux and pinconf core
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum mvf600_pads {
+	MVF600_PAD_PTA6 = 0,
+	MVF600_PAD_PTA8 = 1,
+	MVF600_PAD_PTA9 = 2,
+	MVF600_PAD_PTA10 = 3,
+	MVF600_PAD_PTA11 = 4,
+	MVF600_PAD_PTA12 = 5,
+	MVF600_PAD_PTA16 = 6,
+	MVF600_PAD_PTA17 = 7,
+	MVF600_PAD_PTA18 = 8,
+	MVF600_PAD_PTA19 = 9,
+	MVF600_PAD_PTA20 = 10,
+	MVF600_PAD_PTA21 = 11,
+	MVF600_PAD_PTA22 = 12,
+	MVF600_PAD_PTA23 = 13,
+	MVF600_PAD_PTA24 = 14,
+	MVF600_PAD_PTA25 = 15,
+	MVF600_PAD_PTA26 = 16,
+	MVF600_PAD_PTA27 = 17,
+	MVF600_PAD_PTA28 = 18,
+	MVF600_PAD_PTA29 = 19,
+	MVF600_PAD_PTA30 = 20,
+	MVF600_PAD_PTA31 = 21,
+	MVF600_PAD_PTB0 = 22,
+	MVF600_PAD_PTB1 = 23,
+	MVF600_PAD_PTB2 = 24,
+	MVF600_PAD_PTB3 = 25,
+	MVF600_PAD_PTB4 = 26,
+	MVF600_PAD_PTB5 = 27,
+	MVF600_PAD_PTB6 = 28,
+	MVF600_PAD_PTB7 = 29,
+	MVF600_PAD_PTB8 = 30,
+	MVF600_PAD_PTB9 = 31,
+	MVF600_PAD_PTB10 = 32,
+	MVF600_PAD_PTB11 = 33,
+	MVF600_PAD_PTB12 = 34,
+	MVF600_PAD_PTB13 = 35,
+	MVF600_PAD_PTB14 = 36,
+	MVF600_PAD_PTB15 = 37,
+	MVF600_PAD_PTB16 = 38,
+	MVF600_PAD_PTB17 = 39,
+	MVF600_PAD_PTB18 = 40,
+	MVF600_PAD_PTB19 = 41,
+	MVF600_PAD_PTB20 = 42,
+	MVF600_PAD_PTB21 = 43,
+	MVF600_PAD_PTB22 = 44,
+	MVF600_PAD_PTC0 = 45,
+	MVF600_PAD_PTC1 = 46,
+	MVF600_PAD_PTC2 = 47,
+	MVF600_PAD_PTC3 = 48,
+	MVF600_PAD_PTC4 = 49,
+	MVF600_PAD_PTC5 = 50,
+	MVF600_PAD_PTC6 = 51,
+	MVF600_PAD_PTC7 = 52,
+	MVF600_PAD_PTC8 = 53,
+	MVF600_PAD_PTC9 = 54,
+	MVF600_PAD_PTC10 = 55,
+	MVF600_PAD_PTC11 = 56,
+	MVF600_PAD_PTC12 = 57,
+	MVF600_PAD_PTC13 = 58,
+	MVF600_PAD_PTC14 = 59,
+	MVF600_PAD_PTC15 = 60,
+	MVF600_PAD_PTC16 = 61,
+	MVF600_PAD_PTC17 = 62,
+	MVF600_PAD_PTD31 = 63,
+	MVF600_PAD_PTD30 = 64,
+	MVF600_PAD_PTD29 = 65,
+	MVF600_PAD_PTD28 = 66,
+	MVF600_PAD_PTD27 = 67,
+	MVF600_PAD_PTD26 = 68,
+	MVF600_PAD_PTD25 = 69,
+	MVF600_PAD_PTD24 = 70,
+	MVF600_PAD_PTD23 = 71,
+	MVF600_PAD_PTD22 = 72,
+	MVF600_PAD_PTD21 = 73,
+	MVF600_PAD_PTD20 = 74,
+	MVF600_PAD_PTD19 = 75,
+	MVF600_PAD_PTD18 = 76,
+	MVF600_PAD_PTD17 = 77,
+	MVF600_PAD_PTD16 = 78,
+	MVF600_PAD_PTD0 = 79,
+	MVF600_PAD_PTD1 = 80,
+	MVF600_PAD_PTD2 = 81,
+	MVF600_PAD_PTD3 = 82,
+	MVF600_PAD_PTD4 = 83,
+	MVF600_PAD_PTD5 = 84,
+	MVF600_PAD_PTD6 = 85,
+	MVF600_PAD_PTD7 = 86,
+	MVF600_PAD_PTD8 = 87,
+	MVF600_PAD_PTD9 = 88,
+	MVF600_PAD_PTD10 = 89,
+	MVF600_PAD_PTD11 = 90,
+	MVF600_PAD_PTD12 = 91,
+	MVF600_PAD_PTD13 = 92,
+	MVF600_PAD_PTB23 = 93,
+	MVF600_PAD_PTB24 = 94,
+	MVF600_PAD_PTB25 = 95,
+	MVF600_PAD_PTB26 = 96,
+	MVF600_PAD_PTB27 = 97,
+	MVF600_PAD_PTB28 = 98,
+	MVF600_PAD_PTC26 = 99,
+	MVF600_PAD_PTC27 = 100,
+	MVF600_PAD_PTC28 = 101,
+	MVF600_PAD_PTC29 = 102,
+	MVF600_PAD_PTC30 = 103,
+	MVF600_PAD_PTC31 = 104,
+	MVF600_PAD_PTE0 = 105,
+	MVF600_PAD_PTE1 = 106,
+	MVF600_PAD_PTE2 = 107,
+	MVF600_PAD_PTE3 = 108,
+	MVF600_PAD_PTE4 = 109,
+	MVF600_PAD_PTE5 = 110,
+	MVF600_PAD_PTE6 = 111,
+	MVF600_PAD_PTE7 = 112,
+	MVF600_PAD_PTE8 = 113,
+	MVF600_PAD_PTE9 = 114,
+	MVF600_PAD_PTE10 = 115,
+	MVF600_PAD_PTE11 = 116,
+	MVF600_PAD_PTE12 = 117,
+	MVF600_PAD_PTE13 = 118,
+	MVF600_PAD_PTE14 = 119,
+	MVF600_PAD_PTE15 = 120,
+	MVF600_PAD_PTE16 = 121,
+	MVF600_PAD_PTE17 = 122,
+	MVF600_PAD_PTE18 = 123,
+	MVF600_PAD_PTE19 = 124,
+	MVF600_PAD_PTE20 = 125,
+	MVF600_PAD_PTE21 = 126,
+	MVF600_PAD_PTE22 = 127,
+	MVF600_PAD_PTE23 = 128,
+	MVF600_PAD_PTE24 = 129,
+	MVF600_PAD_PTE25 = 130,
+	MVF600_PAD_PTE26 = 131,
+	MVF600_PAD_PTE27 = 132,
+	MVF600_PAD_PTE28 = 133,
+	MVF600_PAD_PTA7 = 134,
+	};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc mvf600_pinctrl_pads[] = {
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA29),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA30),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA31),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB14),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB15),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC14),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC15),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD31),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD30),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD29),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC29),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC30),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC31),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE14),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE15),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA7),
+};
+
+static struct imx_pinctrl_soc_info mvf600_pinctrl_info = {
+	.pins = mvf600_pinctrl_pads,
+	.npins = ARRAY_SIZE(mvf600_pinctrl_pads),
+};
+
+static struct of_device_id mvf600_pinctrl_of_match[] = {
+	{ .compatible = "fsl,mvf-iomuxc", },
+	{ /* sentinel */ }
+};
+
+static int mvf600_pinctrl_probe(struct platform_device *pdev)
+{
+	return imx_pinctrl_probe(pdev, &mvf600_pinctrl_info);
+}
+
+static struct platform_driver mvf600_pinctrl_driver = {
+	.driver = {
+		.name = "mvf600-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(mvf600_pinctrl_of_match),
+	},
+	.probe = mvf600_pinctrl_probe,
+	.remove = imx_pinctrl_remove,
+};
+
+static int __init mvf600_pinctrl_init(void)
+{
+	return platform_driver_register(&mvf600_pinctrl_driver);
+}
+arch_initcall(mvf600_pinctrl_init);
+
+static void __exit mvf600_pinctrl_exit(void)
+{
+	platform_driver_unregister(&mvf600_pinctrl_driver);
+}
+module_exit(mvf600_pinctrl_exit);
+MODULE_DESCRIPTION("Freescale MVF600 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.0




From b35083 at freescale.com  Thu May  2 03:48:52 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 2 May 2013 15:48:52 +0800
Subject: [PATCH 2/2] pinctrl/imx: add zero register offset valid for Vybrid
 platform
In-Reply-To: <1367480932-22318-1-git-send-email-b35083@freescale.com>
References: <1367480932-22318-1-git-send-email-b35083@freescale.com>
Message-ID: <1367480932-22318-2-git-send-email-b35083@freescale.com>

On some platform such as Vybrid, offset of mux and pad ctrl register
may be zero. This patch add a platform condition to imx core pinctrl
framework, making zero register offset valid on setting mux_mode and
pad config value.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
 drivers/pinctrl/pinctrl-imx.c | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4fcfff92..b4d7c91 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -221,10 +221,14 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 		pin_id = pins[i];
 		pin_reg = &info->pin_regs[pin_id];
 
-		if (!pin_reg->mux_reg) {
-			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
-				info->pins[pin_id].name);
-			return -EINVAL;
+		/* mux_reg offset maybe zero on some platform such as Vybrid */
+		if (!of_machine_is_compatible("fsl,mvf600")) {
+			if (!pin_reg->mux_reg) {
+				dev_err(ipctl->dev,
+					"Pin(%s) does not support mux function\n",
+					info->pins[pin_id].name);
+				return -EINVAL;
+			}
 		}
 
 		writel(mux[i], ipctl->base + pin_reg->mux_reg);
@@ -287,10 +291,13 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 
-	if (!pin_reg->conf_reg) {
-		dev_err(info->dev, "Pin(%s) does not support config function\n",
-			info->pins[pin_id].name);
-		return -EINVAL;
+	if (!of_machine_is_compatible("fsl,mvf600")) {
+		if (!pin_reg->conf_reg) {
+			dev_err(info->dev,
+				"Pin(%s) does not support config function\n",
+				info->pins[pin_id].name);
+			return -EINVAL;
+		}
 	}
 
 	*config = readl(ipctl->base + pin_reg->conf_reg);
@@ -305,10 +312,13 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 
-	if (!pin_reg->conf_reg) {
-		dev_err(info->dev, "Pin(%s) does not support config function\n",
-			info->pins[pin_id].name);
-		return -EINVAL;
+	if (!of_machine_is_compatible("fsl,mvf600")) {
+		if (!pin_reg->conf_reg) {
+			dev_err(info->dev,
+				"Pin(%s) does not support config function\n",
+				info->pins[pin_id].name);
+			return -EINVAL;
+		}
 	}
 
 	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
-- 
1.8.0




From linux at arm.linux.org.uk  Thu May  2 04:34:30 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 09:34:30 +0100
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <alpine.LFD.2.03.1304301418100.17372@syhkavp.arg>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <201304301304.20650.arnd@arndb.de> <20130430114229.GA2439@linaro.org>
 <alpine.LFD.2.03.1304301110030.17372@syhkavp.arg>
 <20130430172816.GA31101@linaro.org>
 <alpine.LFD.2.03.1304301418100.17372@syhkavp.arg>
Message-ID: <20130502083430.GB21614@n2100.arm.linux.org.uk>

On Tue, Apr 30, 2013 at 02:18:42PM -0400, Nicolas Pitre wrote:
> On Tue, 30 Apr 2013, Dave Martin wrote:
> 
> > On Tue, Apr 30, 2013 at 11:12:12AM -0400, Nicolas Pitre wrote:
> > > On Tue, 30 Apr 2013, Dave Martin wrote:
> > > 
> > > > On Tue, Apr 30, 2013 at 01:04:20PM +0200, Arnd Bergmann wrote:
> > > > > On Tuesday 30 April 2013, Russell King - ARM Linux wrote:
> > > > > > Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> > > > > > great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> > > > > > arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> > > > > > source of errors.
> > > > 
> > > > [...]
> > > >  
> > > > > >arch/arm/common/mcpm_head.S:39: Error: selected processor does not support ARM mode `ubfx r9,r0,#0,#8'
> > > > > >arch/arm/common/mcpm_head.S:40: Error: selected processor does not support ARM mode `ubfx r10,r0,#8,#8'
> > > > > >arch/arm/common/mcpm_head.S:100: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/mcpm_head.S:115: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/mcpm_head.S:127: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/mcpm_head.S:131: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/mcpm_head.S:138: Error: selected processor does not support ARM mode `dsb'
> > > > > >arch/arm/common/mcpm_head.S:152: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/mcpm_head.S:161: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/mcpm_head.S:175: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/vlock.S:62: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/vlock.S:72: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/vlock.S:72: Error: selected processor does not support ARM mode `dsb'
> > > > > >arch/arm/common/vlock.S:89: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/vlock.S:95: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/vlock.S:95: Error: selected processor does not support ARM mode `dsb'
> > > > > >arch/arm/common/vlock.S:102: Error: selected processor does not support ARM mode `dmb'
> > > > > >arch/arm/common/vlock.S:105: Error: selected processor does not support ARM mode `dsb'
> > > > > 
> > > > > Right, the problem here is that the code was never tested with an ARMv6+ARMv7 config.
> > > > > We can either fix it up by adding
> > > > > 
> > > > > 	.arch	armv7-a
> > > > > 
> > > > > in the assembly files, or by doing the same in the Makefile:
> > > > > 
> > > > > AFLAGS_vlock.S += -march=armv7-a
> > > > > AFLAGS_mcpm_head.S += -march=armv7-a
> > > > 
> > > > 
> > > > Hmmm, this code was tested with ARCH_MULTIPLATFORM, but it looks like
> > > > no v6 boards were configured in when testing that...
> > > > 
> > > > 
> > > > Assuming people are OK with the Makefile route, here's a patch for that,
> > > > build-tested with a v6+v7 ARCH_MULTIPLATFORM config.
> > > 
> > > Isn't the .arch armv7-a route a bit cleaner?  That would have been my 
> > > choice, although I don't feel strongly about it.
> > 
> > I don't feel strongly either.  We already have the CFLAGS_DISABLE stuff,
> > so it didn't feel that unnatural to add this in the Makefile; but .arch
> > would work equally well.
> > 
> > If somebody wants to change it, it's not a problem for me, but I didn't
> > want to create extra disruption by proposing a different patch...
> 
> Fair enough.
> 
> Acked-by: Nicolas Pitre <nico at linaro.org>

I see Dave Martin has sent a patch for this without your ack.  Was that
a mistake?


From maxime.ripard at free-electrons.com  Thu May  2 04:35:19 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 02 May 2013 10:35:19 +0200
Subject: [PATCH] mxs: icoll: Add function to register an interrupt as
 FIQ source
In-Reply-To: <20130502023858.GD3442@S2101-09.ap.freescale.net>
References: <1367243917-5177-1-git-send-email-maxime.ripard@free-electrons.com>
 <20130502023858.GD3442@S2101-09.ap.freescale.net>
Message-ID: <51822547.20605@free-electrons.com>

Hi Shawn,

Le 02/05/2013 04:39, Shawn Guo a ?crit :
> On Mon, Apr 29, 2013 at 03:58:37PM +0200, Maxime Ripard wrote:
>> MXS, unlike other ARM platforms,
> 
> How are other ARM platforms handling that?

Just like that. You can look at mxc_set_irq_fiq in
arch/arm/mach-imx/irq-common.c or s3c24xx_set_fiq in
arch/arm/mach-s3c24xx/irq.c

I've also thought about declaring a IRQ type and using the .irq_set_type
to register an interrupt as a FIQ source, but since FIQ are
ARM-specific, it's probably a bad idea.

>> has no way to make a FIQ from an
>> interrupt from a driver, without poking directly into the icoll.
>>
>> Add an exported function to do this.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>> ---
>>  arch/arm/mach-mxs/icoll.c | 11 +++++++++++
> 
> This will become drivers/irqchip/irq-mxs.c after the merge window.

Ok, I'll rebase and repost then.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From lee.jones at linaro.org  Thu May  2 04:38:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 May 2013 09:38:49 +0100
Subject: [PATCH 12/32] ARM: ux500: Remove superfluous 'psize' attribute
 from Audio platform data
In-Reply-To: <20130501144213.GG25256@gmail.com>
References: <1366279934-30761-1-git-send-email-lee.jones@linaro.org>
 <1366279934-30761-13-git-send-email-lee.jones@linaro.org>
 <20130501144213.GG25256@gmail.com>
Message-ID: <20130502083849.GH25256@gmail.com>

On Wed, 01 May 2013, Lee Jones wrote:

> On Thu, 18 Apr 2013, Lee Jones wrote:
> 
> > 'psize' is used to calculate the maximum DMA burst size. However it
> > is only taken into consideration when editing the DMA channel's
> > configuration. The Audio DMA platform data is only used to allocate
> > a channel, not configure it. That will be done at a later date within
> > the MSP driver.
> > 
> > We're also removing comments which are no longer required, as
> > 'data_width' is no longer set in any device's platform data period.
> > 
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  arch/arm/mach-ux500/board-mop500-audio.c |   38 ------------------------------
> >  1 file changed, 38 deletions(-)
> > 
> > diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
> > index f012cfa..972bec0 100644
> > --- a/arch/arm/mach-ux500/board-mop500-audio.c
> > +++ b/arch/arm/mach-ux500/board-mop500-audio.c
> > @@ -23,25 +23,13 @@
> >  static struct stedma40_chan_cfg msp0_dma_rx = {
> >  	.high_priority = true,
> >  	.dir = STEDMA40_PERIPH_TO_MEM,
> > -
> >  	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
> > -
> > -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> > -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> > -
> > -	/* data_width is set during configuration */
> >  };
> >  
> >  static struct stedma40_chan_cfg msp0_dma_tx = {
> >  	.high_priority = true,
> >  	.dir = STEDMA40_MEM_TO_PERIPH,
> > -
> >  	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
> > -
> > -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> > -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> > -
> > -	/* data_width is set during configuration */
> >  };
> >  
> >  struct msp_i2s_platform_data msp0_platform_data = {
> > @@ -53,25 +41,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
> >  static struct stedma40_chan_cfg msp1_dma_rx = {
> >  	.high_priority = true,
> >  	.dir = STEDMA40_PERIPH_TO_MEM,
> > -
> >  	.dev_type = DB8500_DMA_DEV30_MSP3,
> > -
> > -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> > -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> > -
> > -	/* data_width is set during configuration */
> >  };
> >  
> >  static struct stedma40_chan_cfg msp1_dma_tx = {
> >  	.high_priority = true,
> >  	.dir = STEDMA40_MEM_TO_PERIPH,
> > -
> >  	.dev_type = DB8500_DMA_DEV30_MSP1,
> > -
> > -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> > -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> > -
> > -	/* data_width is set during configuration */
> >  };
> >  
> >  struct msp_i2s_platform_data msp1_platform_data = {
> > @@ -83,29 +59,15 @@ struct msp_i2s_platform_data msp1_platform_data = {
> >  static struct stedma40_chan_cfg msp2_dma_rx = {
> >  	.high_priority = true,
> >  	.dir = STEDMA40_PERIPH_TO_MEM,
> > -
> >  	.dev_type = DB8500_DMA_DEV14_MSP2,
> > -
> > -	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
> > -	.src_info.psize = STEDMA40_PSIZE_LOG_1,
> > -	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
> > -
> > -	/* data_width is set during configuration */
> >  };
> >  
> >  static struct stedma40_chan_cfg msp2_dma_tx = {
> >  	.high_priority = true,
> >  	.dir = STEDMA40_MEM_TO_PERIPH,
> > -
> >  	.dev_type = DB8500_DMA_DEV14_MSP2,
> > -
> > -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> > -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> > -
> >  	.use_fixed_channel = true,
> >  	.phy_channel = 1,
> > -
> > -	/* data_width is set during configuration */
> >  };
> >  
> >  static struct platform_device *db8500_add_msp_i2s(struct device *parent,
> 
> Linus, poke.

I've just seen this response from you (it didn't make it to my offline
mail store for some reason):

> Linus Walleij wrote:
> So if I understand correctly this is now handled by dmaengine_pcm.c,
> os that right?

Unfortunately not. At the moment ux500 sound is very broken in
Mainline. I looked at it recently and the driver is almost completely
different to the one maintained internally.

There were DMA changes relating to this driver pending for v3.10,
which I believe have just been taking into -next. I will straighten
out the DMA issues shortly, but there are other ones remaining still -
mostly surrounding widgets. Ideally this is something Ola should fix,
as he has the expertise to do so, but he doesn't appear to have been
very active upstream of late.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From pekon at ti.com  Thu May  2 04:48:21 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 2 May 2013 14:18:21 +0530
Subject: [v3,
 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evm
Message-ID: <1367484501-3623-1-git-send-email-pekon@ti.com>

From: avinash philip <avinashphilip at ti.com>

NAND flash connected in am335x-evm on GPMC controller. This patch adds
device tree node in am3355-evm with GPMC contoller timing for NAND flash
interface, NAND partition table, ECC scheme, elm handle id.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
Signed-off-by: Gupta, Pekon <pekon at ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts | 95 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..07761fd 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,26 @@
 				0x154 0x27	/* spi0_d0.gpio0_3, INPUT | MODE7 */
 			>;
 		};
+
+		nandflash_pins_s0: nandflash_pins_s0 {
+			pinctrl-single,pins = <
+				0x0 0x30	/* gpmc_ad0.gpmc_ad0, INPUT | PULLUP | MODE0 */
+				0x4 0x30	/* gpmc_ad1.gpmc_ad1, INPUT | PULLUP | MODE0 */
+				0x8 0x30	/* gpmc_ad2.gpmc_ad2, INPUT | PULLUP | MODE0 */
+				0xc 0x30	/* gpmc_ad3.gpmc_ad3, INPUT | PULLUP | MODE0 */
+				0x10 0x30	/* gpmc_ad4.gpmc_ad4, INPUT | PULLUP | MODE0 */
+				0x14 0x30	/* gpmc_ad5.gpmc_ad5, INPUT | PULLUP | MODE0 */
+				0x18 0x30	/* gpmc_ad6.gpmc_ad6, INPUT | PULLUP | MODE0 */
+				0x1c 0x30	/* gpmc_ad7.gpmc_ad7, INPUT | PULLUP | MODE0 */
+				0x70 0x30	/* gpmc_wait0.gpmc_wait0, INPUT | PULLUP | MODE0 */
+				0x74 0x37	/* gpmc_wpn.gpio0_30, INPUT | PULLUP | MODE7 */
+				0x7c 0x8	/* gpmc_csn0.gpmc_csn0,  PULL DISA */
+				0x90 0x8	/* gpmc_advn_ale.gpmc_advn_ale, PULL DISA */
+				0x94 0x8	/* gpmc_oen_ren.gpmc_oen_ren, PULL DISA */
+				0x98 0x8	/* gpmc_wen.gpmc_wen, PULL DISA */
+				0x9c 0x8	/* gpmc_be0n_cle.gpmc_be0n_cle, PULL DISA */
+			>;
+		};
 	};
 
 	ocp {
@@ -102,6 +122,81 @@
 				reg = <0x48>;
 			};
 		};
+
+		elm: elm at 48080000 {
+			status = "okay";
+		};
+
+		gpmc: gpmc at 50000000 {
+			status = "okay";
+			pinctrl-0 = <&nandflash_pins_s0>;
+			ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+			nand at 0,0 {
+				reg = <0 0 0>; /* CS0, offset 0 */
+				nand-bus-width = <8>;
+				ti,nand-ecc-opt = "bch8";
+
+				gpmc,sync-clk = <0>;
+				gpmc,cs-on = <0>;
+				gpmc,cs-rd-off = <44>;
+				gpmc,cs-wr-off = <44>;
+				gpmc,adv-on = <6>;
+				gpmc,adv-rd-off = <34>;
+				gpmc,adv-wr-off = <44>;
+				gpmc,we-off = <40>;
+				gpmc,oe-off = <54>;
+				gpmc,access = <64>;
+				gpmc,rd-cycle = <82>;
+				gpmc,wr-cycle = <82>;
+				gpmc,wr-access = <40>;
+				gpmc,wr-data-mux-bus = <0>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+				elm_id = <&elm>;
+
+				/* MTD partition table */
+				partition at 0 {
+					label = "SPL1";
+					reg = <0x00000000 0x000020000>;
+				};
+
+				partition at 1 {
+					label = "SPL2";
+					reg = <0x00020000 0x00020000>;
+				};
+
+				partition at 2 {
+					label = "SPL3";
+					reg = <0x00040000 0x00020000>;
+				};
+
+				partition at 3 {
+					label = "SPL4";
+					reg = <0x00060000 0x00020000>;
+				};
+
+				partition at 4 {
+					label = "U-boot";
+					reg = <0x00080000 0x001e0000>;
+				};
+
+				partition at 5 {
+					label = "environment";
+					reg = <0x00260000 0x00020000>;
+				};
+
+				partition at 6 {
+					label = "Kernel";
+					reg = <0x00280000 0x00500000>;
+				};
+
+				partition at 7 {
+					label = "File-System";
+					reg = <0x00780000 0x0F880000>;
+				};
+			};
+		};
 	};
 
 	vbat: fixedregulator at 0 {
-- 
1.8.1



From lee.jones at linaro.org  Thu May  2 04:51:23 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 09:51:23 +0100
Subject: [PATCH] ARM: ux500: Remove DMA address look-up table
Message-ID: <1367484683-3479-1-git-send-email-lee.jones@linaro.org>

DMA addresses are now passed as part of the dmaengine API by invoking
dmaengine_slave_config(). So there's no requirement for the DMA40
driver to look them up in a table provided by platform data. This
method does not fit in well using Device Tree either.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/devices-db8500.c        |   80 ---------------------------
 include/linux/platform_data/dma-ste-dma40.h |    2 -
 2 files changed, 82 deletions(-)

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 2bc4b5e..d35a492 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,87 +42,7 @@ static struct resource dma40_resources[] = {
 	}
 };
 
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
-	/* PrimeCells - run-time configured */
-	[DB8500_DMA_DEV0_SPI0] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2] = -1,
-	[DB8500_DMA_DEV8_SSP0] = -1,
-	[DB8500_DMA_DEV9_SSP1] = -1,
-	[DB8500_DMA_DEV11_UART2] = -1,
-	[DB8500_DMA_DEV12_UART1] = -1,
-	[DB8500_DMA_DEV13_UART0] = -1,
-	[DB8500_DMA_DEV28_SD_MM2] = -1,
-	[DB8500_DMA_DEV29_SD_MM0] = -1,
-	[DB8500_DMA_DEV32_SD_MM1] = -1,
-	[DB8500_DMA_DEV33_SPI2] = -1,
-	[DB8500_DMA_DEV35_SPI1] = -1,
-	[DB8500_DMA_DEV40_SPI3] = -1,
-	[DB8500_DMA_DEV41_SD_MM3] = -1,
-	[DB8500_DMA_DEV42_SD_MM4] = -1,
-	[DB8500_DMA_DEV43_SD_MM5] = -1,
-	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-	[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
-	/* PrimeCells */
-	[DB8500_DMA_DEV0_SPI0] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2] = -1,
-	[DB8500_DMA_DEV8_SSP0] = -1,
-	[DB8500_DMA_DEV9_SSP1] = -1,
-	[DB8500_DMA_DEV11_UART2] = -1,
-	[DB8500_DMA_DEV12_UART1] = -1,
-	[DB8500_DMA_DEV13_UART0] = -1,
-	[DB8500_DMA_DEV28_SD_MM2] = -1,
-	[DB8500_DMA_DEV29_SD_MM0] = -1,
-	[DB8500_DMA_DEV32_SD_MM1] = -1,
-	[DB8500_DMA_DEV33_SPI2] = -1,
-	[DB8500_DMA_DEV35_SPI1] = -1,
-	[DB8500_DMA_DEV40_SPI3] = -1,
-	[DB8500_DMA_DEV41_SD_MM3] = -1,
-	[DB8500_DMA_DEV42_SD_MM4] = -1,
-	[DB8500_DMA_DEV43_SD_MM5] = -1,
-	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
 struct stedma40_platform_data dma40_plat_data = {
-	.dev_rx = dma40_rx_map,
-	.dev_tx = dma40_tx_map,
 	.disabled_channels = {-1},
 };
 
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index c54af61..af0064e 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -152,8 +152,6 @@ struct stedma40_chan_cfg {
  * for 'multiple of 4' channels, like 8.
  */
 struct stedma40_platform_data {
-	const dma_addr_t		*dev_tx;
-	const dma_addr_t		*dev_rx;
 	int				 disabled_channels[STEDMA40_MAX_PHYS];
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
-- 
1.7.10.4



From s.hauer at pengutronix.de  Thu May  2 04:52:33 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 2 May 2013 10:52:33 +0200
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <1367480285-26159-2-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
Message-ID: <20130502085233.GO32299@pengutronix.de>

On Thu, May 02, 2013 at 03:38:04PM +0800, Jingchang Lu wrote:
> This patch adds Freescale Vybrid Family platform core definitions,
> core drivers, including clock, period interrupt timer(PIT),
> and DTS based machine support with MVF600 Tower development board.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
>   Use CLOCKSOURCE_OF_DECLARE init timer
>   Add ONESHOT mode support
>   Add more clks definitions on MVF600 soc
> 
>  .../devicetree/bindings/clock/mvf600-clock.txt     | 180 +++++++++
>  arch/arm/mach-imx/Kconfig                          |  15 +
>  arch/arm/mach-imx/Makefile                         |   3 +
>  arch/arm/mach-imx/clk-mvf.c                        | 406 +++++++++++++++++++++
>  arch/arm/mach-imx/common.h                         |   1 +
>  arch/arm/mach-imx/mach-mvf600.c                    | 118 ++++++
>  arch/arm/mach-imx/pit.c                            | 244 +++++++++++++
>  7 files changed, 967 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
>  create mode 100644 arch/arm/mach-imx/clk-mvf.c
>  create mode 100644 arch/arm/mach-imx/mach-mvf600.c
>  create mode 100644 arch/arm/mach-imx/pit.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
> new file mode 100644
> index 0000000..9f8b20e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt

[...]

> +	sys_bus_clk		36
> +	platform_bus_clk	37
> +	ipg_bus_clk		38
> +	uart0_clk		39
> +	uart1_clk		40
> +	uart2_clk		41
> +	uart3_clk		42
> +	uart4_clk		43
> +	uart5_clk		44

remove the _clk. The context makes it clear that it's a clock.

> +
> +#define CCM_CCGRx_CGn(n)		(n * 2)

Does CCM_CCGRx_CGn(1 + 1) give correct results? Always add braces to
the usage of macro arguments.

> +int __init mvf_clocks_init(void)
> +{
> +	struct device_node *np;
> +
> +	clk[dummy] = imx_clk_fixed("dummy", 0);
> +	clk[sirc_128k] = imx_clk_fixed("sirc_128k", 128000); /* slow internal IRC */
> +	clk[sirc_32k] = imx_clk_fixed("sirc_32k", 32000); /* slow internal IRC */
> +	clk[firc] = imx_clk_fixed("firc", 24000000); /* fast internal IRC */
> +	clk[sxosc] = imx_clk_fixed("sxosc", 32000); /* fixed 32k external osc */
> +
> +	for_each_compatible_node(np, NULL, "fixed-clock") {
> +		u32 rate;
> +
> +		if (of_property_read_u32(np, "clock-frequency", &rate))
> +			continue;
> +		else if (of_device_is_compatible(np, "fsl,mvf-osc"))
> +			clk[fxosc] = imx_clk_fixed("fxosc", rate);
> +		else if (of_device_is_compatible(np, "fsl,mvf-audio-ext-clk"))
> +			clk[audio_ext] = imx_clk_fixed("audio_ext", rate);
> +		else if (of_device_is_compatible(np, "fsl,mvf-enet-ext-clk"))
> +			clk[enet_ext] = imx_clk_fixed("enet_ext", rate);
> +	}

Please do the same as https://patchwork.kernel.org/patch/2476681/ does
for i.MX5.

> +
> +
> +void mvf_restart(char mode, const char *cmd)
> +{
> +	struct device_node *np;
> +	void __iomem *wdog_base;
> +	struct clk *wdog_clk;
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt");
> +	wdog_base = of_iomap(np, 0);
> +	if (!wdog_base)
> +		goto soft;
> +
> +	wdog_clk = of_clk_get_by_name(np, "wdog");

use of_clk_get.

> +
> +
> +static int __init pit_clocksource_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	sched_clock_reg = clksrc_base + PITCVAL;
> +
> +	setup_sched_clock(mvf_read_sched_clock, 32, c);
> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, 32,
> +			clocksource_mmio_readl_down);
> +}
> +
> +/* set clock event */
> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_irq_acknowledge();
> +	pit_timer_enable();

You disable/enable the timer each time here, is this necessary? You will
get a drift in the timer, that's really not nice.

> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	int irq;
> +
> +	if (!np) {
> +		pr_err("Failed to find pit DT node\n");
> +		BUG();
> +	}
> +
> +	timer_base = of_iomap(np, 0);
> +	WARN_ON(!timer_base);
> +
> +	/* chose PIT2 as clocksource, PIT3 as clockevent dev */
> +	clksrc_base = timer_base + PITOFFSETx(2);
> +	clkevt_base = timer_base + PITOFFSETx(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +
> +	pit_clk = of_clk_get_by_name(np, "pit");

Use of_clk_get

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From lee.jones at linaro.org  Thu May  2 04:56:18 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 09:56:18 +0100
Subject: [PATCH] dmaengine: ste_dma40: Correct copy/paste error
Message-ID: <1367484978-3599-1-git-send-email-lee.jones@linaro.org>

'struct stedma40_half_channel_info's header comment says that it's
called 'struct stedma40_chan_cfg'. Let's straighten that out.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/platform_data/dma-ste-dma40.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index af0064e..288dc24 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
 
 
 /**
- * struct stedma40_chan_cfg - dst/src channel configuration
+ * struct stedma40_half_channel_info - dst/src channel configuration
  *
  * @big_endian: true if the src/dst should be read as big endian
  * @data_width: Data width of the src/dst hardware
-- 
1.7.10.4



From s.hauer at pengutronix.de  Thu May  2 04:56:32 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 2 May 2013 10:56:32 +0200
Subject: [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for
 Vybrid
In-Reply-To: <1367480285-26159-3-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-3-git-send-email-b35083@freescale.com>
Message-ID: <20130502085632.GP32299@pengutronix.de>

On Thu, May 02, 2013 at 03:38:05PM +0800, Jingchang Lu wrote:
> This patch adds basic device tree source for Freescale
> Vybrid Family MVF600 platform and Tower development board.
> 
> Signed-off-by: Xiaochun Li <b41219 at freescale.com>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
>   Add pinctrl support based on IMX new pinctrl framework
> 
>  arch/arm/boot/dts/Makefile         |   3 +-
>  arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mvf600-twr.dts   |  80 ++++
>  arch/arm/boot/dts/mvf600.dtsi      | 426 +++++++++++++++++++
>  4 files changed, 1324 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
>  create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
>  create mode 100644 arch/arm/boot/dts/mvf600.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8fd41b3..6402f21 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
>  	imx6q-sabreauto.dtb \
>  	imx6q-sabrelite.dtb \
>  	imx6q-sabresd.dtb \
> -	imx6q-sbc6x.dtb
> +	imx6q-sbc6x.dtb \
> +	mvf600-twr.dtb
>  dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
>  	imx23-olinuxino.dtb \
>  	imx23-stmp378x_devb.dtb \
> diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h
> new file mode 100644
> index 0000000..9fbc7a9
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600-pinfunc.h
> @@ -0,0 +1,816 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DTS_MVF600_PINFUNC_H
> +#define __DTS_MVF600_PINFUNC_H
> +
> +/*
> + * Macro definations for MVF600 pin functions

s/definations/definitions/

> diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts

Make this a separate patch please. It's board specific whereas the rest
is SoC specific.

> +		aips1: aips-bus at 40080000 { /* AIPS1 */
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x40080000 0x80000>;
> +			ranges;
> +
> +			uart4: serial at 400a9000 { /* UART4 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x400a9000 0x1000>;
> +				interrupts = <0 65 0x04>;
> +				clocks = <&clks 43>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart5: serial at 400aa000 { /* UART5 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x400aa000 0x1000>;
> +				interrupts = <0 66 0x04>;
> +				clocks = <&clks 44>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			fec0: ethernet at 400d0000 {
> +				compatible = "fsl,mvf-fec";
> +				reg = <0x400d0000 0x1000>;
> +				interrupts = <0 78 0x04>;
> +				clocks = <&clks 69>, <&clks 69>, <&clks 69>;
> +				clock-names = "ipg", "ahb", "ptp";

				status = "disabled";

> +			};
> +
> +			fec1: ethernet at 400d1000 {
> +				compatible = "fsl,mvf-fec";
> +				reg = <0x400d1000 0x1000>;
> +				interrupts = <0 79 0x04>;
> +				clocks = <&clks 69>, <&clks 69>, <&clks 69>;
> +				clock-names = "ipg", "ahb", "ptp";

				status = "disabled";

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From lee.jones at linaro.org  Thu May  2 04:58:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 09:58:33 +0100
Subject: [PATCH] ARM: ux500: Remove unnecessary attributes from DMA channel
 request pdata
Message-ID: <1367485113-3647-1-git-send-email-lee.jones@linaro.org>

DMA data width and packet size information is only required at channel
configuration time. Any information passed from platform data is passed
directly to the DMA40 driver to use during channel allocation, but these
pieces of information are subsequently ignored by the driver, so we may
as well remove them.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index e0ea490..821703d 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,19 +15,11 @@
 #define MUSB_DMA40_RX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_PERIPH_TO_MEM, \
-		.src_info.data_width = STEDMA40_WORD_WIDTH, \
-		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
-		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
 	}
 
 #define MUSB_DMA40_TX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_MEM_TO_PERIPH, \
-		.src_info.data_width = STEDMA40_WORD_WIDTH, \
-		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
-		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
 	}
 
 static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
-- 
1.7.10.4



From linus.walleij at stericsson.com  Thu May  2 05:06:08 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 11:06:08 +0200
Subject: [PATCH 18/23 v2] dma: coh901318: add devicetree support
Message-ID: <1367485568-6116-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds support for probing the COH 901 318 DMA controller
and channels from the device tree.

Contains portions of a sketch patch from Arnd Bergmann.

Cc: Arnd Bergmann <arnd at arndb.de>
Acked-by: Vinod Koul <vinod.koul at intel.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Folded in channel translation, request and filtering from
  the device tree based on a patch by Arnd Bergmann.
- Added device tree binding documentation.
---
 .../devicetree/bindings/dma/ste-coh901318.txt      | 32 ++++++++++++++++
 drivers/dma/coh901318.c                            | 43 ++++++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/ste-coh901318.txt

diff --git a/Documentation/devicetree/bindings/dma/ste-coh901318.txt b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
new file mode 100644
index 0000000..091ad05
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
@@ -0,0 +1,32 @@
+ST-Ericsson COH 901 318 DMA Controller
+
+This is a DMA controller which has begun as a fork of the
+ARM PL08x PrimeCell VHDL code.
+
+Required properties:
+- compatible: should be "stericsson,coh901318"
+- reg: register locations and length
+- interrupts: the single DMA IRQ
+- #dma-cells: must be set to <1>, as the channels on the
+  COH 901 318 are simple and identified by a single number
+- dma-channels: the number of DMA channels handled
+
+Example:
+
+dmac: dma-controller at c00020000 {
+	compatible = "stericsson,coh901318";
+	reg = <0xc0020000 0x1000>;
+	interrupt-parent = <&vica>;
+	interrupts = <2>;
+	#dma-cells = <1>;
+	dma-channels = <40>;
+};
+
+Consumers example:
+
+uart0: serial at c0013000 {
+	compatible = "...";
+	(...)
+	dmas = <&dmac 17 &dmac 18>;
+	dma-names = "tx", "rx";
+};
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 797940e..8b22f56 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -22,6 +22,7 @@
 #include <linux/uaccess.h>
 #include <linux/debugfs.h>
 #include <linux/platform_data/dma-coh901318.h>
+#include <linux/of_dma.h>
 
 #include "coh901318.h"
 #include "dmaengine.h"
@@ -1788,6 +1789,35 @@ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 }
 EXPORT_SYMBOL(coh901318_filter_id);
 
+struct coh901318_filter_args {
+	struct coh901318_base *base;
+	unsigned int ch_nr;
+};
+
+static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
+{
+	struct coh901318_filter_args *args = data;
+
+	if (&args->base->dma_slave == chan->device &&
+	    args->ch_nr == to_coh901318_chan(chan)->id)
+		return true;
+
+	return false;
+}
+
+static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
+					struct of_dma *ofdma)
+{
+	struct coh901318_filter_args args = {
+		.base = ofdma->of_dma_data,
+		.ch_nr = dma_spec->args[0],
+	};
+	dma_cap_mask_t cap;
+	dma_cap_zero(cap);
+	dma_cap_set(DMA_SLAVE, cap);
+
+	return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
+}
 /*
  * DMA channel allocation
  */
@@ -2735,12 +2765,19 @@ static int __init coh901318_probe(struct platform_device *pdev)
 	if (err)
 		goto err_register_memcpy;
 
+	err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
+					 base);
+	if (err)
+		goto err_register_of_dma;
+
 	platform_set_drvdata(pdev, base);
 	dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
 		(u32) base->virtbase);
 
 	return err;
 
+ err_register_of_dma:
+	dma_async_device_unregister(&base->dma_memcpy);
  err_register_memcpy:
 	dma_async_device_unregister(&base->dma_slave);
  err_register_slave:
@@ -2752,17 +2789,23 @@ static int __exit coh901318_remove(struct platform_device *pdev)
 {
 	struct coh901318_base *base = platform_get_drvdata(pdev);
 
+	of_dma_controller_free(pdev->dev.of_node);
 	dma_async_device_unregister(&base->dma_memcpy);
 	dma_async_device_unregister(&base->dma_slave);
 	coh901318_pool_destroy(&base->pool);
 	return 0;
 }
 
+static const struct of_device_id coh901318_dt_match[] = {
+	{ .compatible = "stericsson,coh901318" },
+	{},
+};
 
 static struct platform_driver coh901318_driver = {
 	.remove = __exit_p(coh901318_remove),
 	.driver = {
 		.name	= "coh901318",
+		.of_match_table = coh901318_dt_match,
 	},
 };
 
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 05:06:49 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 11:06:49 +0200
Subject: [PATCH] ARM: u300: augment device tree with DMA channels
Message-ID: <1367485609-6154-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds DMA channel assignments to the MMC/SD-controller
and the two UARTs already in the U300 device tree, as we
have now defined a way to obtain DMA channels from the
device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index ae51dd1..6be932b 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -185,6 +185,8 @@
 			reg = <0xc0013000 0x1000>;
 			interrupt-parent = <&vica>;
 			interrupts = <22>;
+			dmas = <&dmac 17 &dmac 18>;
+			dma-names = "tx", "rx";
 		};
 
 		uart1: serial at c0007000 {
@@ -192,6 +194,8 @@
 			reg = <0xc0007000 0x1000>;
 			interrupt-parent = <&vicb>;
 			interrupts = <20>;
+			dmas = <&dmac 38 &dmac 39>;
+			dma-names = "tx", "rx";
 		};
 
 		mmcsd: mmcsd at c0001000 {
@@ -206,6 +210,8 @@
 			cd-gpios = <&gpio 12 0x4>;
 			cd-inverted;
 			vmmc-supply = <&ab3100_ldo_g_reg>;
+			dmas = <&dmac 14>;
+			dma-names = "rx";
 		};
 	};
 };
-- 
1.7.11.3



From vincent.guittot at linaro.org  Thu May  2 05:12:32 2013
From: vincent.guittot at linaro.org (Vincent Guittot)
Date: Thu, 2 May 2013 11:12:32 +0200
Subject: [RFC PATCH v4 00/14] sched: packing small tasks
In-Reply-To: <517AA14D.7060202@linux.intel.com>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <517A969B.5040606@linux.intel.com>
 <CAKfTPtCwdw1mYpWRFbPo9zT=9vFANpJyubh1eX-0vJLqrqizgA@mail.gmail.com>
 <517AA14D.7060202@linux.intel.com>
Message-ID: <CAKfTPtA052Lv6oyOqc-t1meVt9wfG1RtVaxMT5PeYPYG_XmdVA@mail.gmail.com>

On 26 April 2013 17:46, Arjan van de Ven <arjan at linux.intel.com> wrote:
>>>
>>>
>>> so I got to ask the hard question; what percentage of system level (not
>>> just
>>> cpu level)
>>> power consumption gain can you measure (pick your favorite workload)...
>>>
>>
>> I haven't system level figures for my patches but only for the cpu
>> subsystem. If we use the MP3 results in the back of my mail, they show
>> an improvement of 37 % (113/178) for the CPU subsystem of the
>> platform. If we assume that the CPU subsystem contributes 25% of an
>> embedded system power consumption (this can vary across platform
>> depending of the use of HW accelerator but it should be a almost fair
>> percentage), the patch can impact the power consumption on up to 9%.
>>
>
> sadly the math tends to not work quite that easy;
> memory takes significantly more power when the system is not idle than when
> it is idle for example. [*]
> so while reducing cpu power by making it run a bit longer (at lower
> frequency or
> slower core or whatever) is a pure win if you only look at the cpu, but it
> may
> (or may not) be a loss when looking at a whole system level.
>
> I've learned the hard way that you cannot just look at the cpu numbers; you
> must look
> at the whole-system power when playing with such tradeoffs.
>
> That does not mean that your patch is not useful; it very well can be, but
> without having looked at whole-system power that's a very dangerous
> conclusion to make.
> So.. if you get a chance, I'd love to see data on a whole-system level...
> even for just one workload
> and one system
> (playing mp3 sounds like a quite reasonable workload for such things indeed)

Hi Arjan,

I don't have full system power consumption but i have gathered some
additional figures for mp3 use case

The power consumption percentage stay similar
             | CA15  | CA7   | total  |
-------------------------------------
default       |  81%  |   95% | 178%   |
pack          |  10%  |  100% | 110%   |
agressive     |  3%   |  100% | 103%   |
-------------------------------------

I have also gathered the time when all CPUs are in low power state so
the entire system can be put in low power mode (DDR in self refresh)
                 |  Time | nb / sec | average |
--------------------------------------------
default       | 85.5% | 296      | 2.9ms   |
pack          | 82.5% | 253      | 3.2ms   |
agressive     | 81.8% | 236      | 3.4ms   |
--------------------------------------------

We can see a decrease of the time spent in low power mode but on the
other side, the number of switch to low power mode also decreases
which results in the increase the average duration of low power state.

Regards,
Vincent

>
>
> [*] I assume that on your ARM systems, memory goes into self refresh during
> system idle just as it does on x86
>


From linus.walleij at stericsson.com  Thu May  2 05:12:32 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 11:12:32 +0200
Subject: [PATCH 20/23 v2] ARM: u300: add SPI PL022 to the device tree
Message-ID: <1367485952-6212-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This registers the PL022 PrimeCell from the U300 device
tree. We make a new copy of the platform data for the
device tree boot path, as the old platform data is in an
older file which will be going away.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Add DMA channels.
---
 arch/arm/boot/dts/ste-u300.dts | 11 +++++++++++
 arch/arm/mach-u300/core.c      | 19 +++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 4dc9f26..46c0785 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -222,5 +222,16 @@
 			dmas = <&dmac 14>;
 			dma-names = "rx";
 		};
+
+		spi: ssp at c0006000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xc0006000 0x1000>;
+			interrupt-parent = <&vica>;
+			interrupts = <23>;
+			dmas = <&dmac 27 &dmac 28>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 98d4dbe..9467ffe 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -19,6 +19,7 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
@@ -703,6 +704,22 @@ MACHINE_END
 
 #ifdef CONFIG_OF
 
+static struct pl022_ssp_controller spi_plat_data = {
+	/* If you have several SPI buses this varies, we have only bus 0 */
+	.bus_id = 0,
+	/*
+	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
+	 * chip selects for SPI. (Same on U330, U335 and U365.)
+	 * TODO: make sure the GPIO driver can select these properly
+	 * and do padmuxing accordingly too.
+	 */
+	.num_chipselect = 3,
+	.enable_dma = 1,
+	.dma_filter = coh901318_filter_id,
+	.dma_rx_param = (void *) U300_DMA_SPI_RX,
+	.dma_tx_param = (void *) U300_DMA_SPI_TX,
+};
+
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
@@ -719,6 +736,8 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
 		"uart1", &uart1_plat_data),
+	OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
+		"pl022", &spi_plat_data),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
 		"stu300.0", NULL),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
-- 
1.7.11.3



From hvaibhav at ti.com  Thu May  2 05:15:15 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 2 May 2013 09:15:15 +0000
Subject: [v3, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <1367484501-3623-1-git-send-email-pekon@ti.com>
References: <1367484501-3623-1-git-send-email-pekon@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC747E9@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Gupta, Pekon
> Sent: Thursday, May 02, 2013 2:18 PM
> To: Gupta, Pekon; Cousson, Benoit; tony at atomide.com;
> linux at arm.linux.org.uk
> Cc: Philip, Avinash; linux-omap at vger.kernel.org; devicetree-
> discuss at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; Nori, Sekhar; Hebbar, Gururaja; Hiremath,
> Vaibhav; zonque at gmail.com; jacmet at sunsite.dk
> Subject: [v3, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
> am335x-evm
> 
> From: avinash philip <avinashphilip at ti.com>
> 
> NAND flash connected in am335x-evm on GPMC controller. This patch adds
> device tree node in am3355-evm with GPMC contoller timing for NAND
> flash
> interface, NAND partition table, ECC scheme, elm handle id.
> 
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>
> Signed-off-by: Gupta, Pekon <pekon at ti.com>
> ---
>  arch/arm/boot/dts/am335x-evm.dts | 95
> ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 95 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am335x-evm.dts
> b/arch/arm/boot/dts/am335x-evm.dts
> index d649644..07761fd 100644
> --- a/arch/arm/boot/dts/am335x-evm.dts
> +++ b/arch/arm/boot/dts/am335x-evm.dts
> @@ -44,6 +44,26 @@
>  				0x154 0x27	/* spi0_d0.gpio0_3, INPUT | MODE7
> */
>  			>;
>  		};
> +
> +		nandflash_pins_s0: nandflash_pins_s0 {
> +			pinctrl-single,pins = <
> +				0x0 0x30	/* gpmc_ad0.gpmc_ad0, INPUT |
> PULLUP | MODE0 */
> +				0x4 0x30	/* gpmc_ad1.gpmc_ad1, INPUT |
> PULLUP | MODE0 */
> +				0x8 0x30	/* gpmc_ad2.gpmc_ad2, INPUT |
> PULLUP | MODE0 */
> +				0xc 0x30	/* gpmc_ad3.gpmc_ad3, INPUT |
> PULLUP | MODE0 */
> +				0x10 0x30	/* gpmc_ad4.gpmc_ad4, INPUT |
> PULLUP | MODE0 */
> +				0x14 0x30	/* gpmc_ad5.gpmc_ad5, INPUT |
> PULLUP | MODE0 */
> +				0x18 0x30	/* gpmc_ad6.gpmc_ad6, INPUT |
> PULLUP | MODE0 */
> +				0x1c 0x30	/* gpmc_ad7.gpmc_ad7, INPUT |
> PULLUP | MODE0 */
> +				0x70 0x30	/* gpmc_wait0.gpmc_wait0, INPUT |
> PULLUP | MODE0 */
> +				0x74 0x37	/* gpmc_wpn.gpio0_30, INPUT |
> PULLUP | MODE7 */
> +				0x7c 0x8	/* gpmc_csn0.gpmc_csn0,  PULL DISA
> */
> +				0x90 0x8	/* gpmc_advn_ale.gpmc_advn_ale,
> PULL DISA */
> +				0x94 0x8	/* gpmc_oen_ren.gpmc_oen_ren, PULL
> DISA */
> +				0x98 0x8	/* gpmc_wen.gpmc_wen, PULL DISA */
> +				0x9c 0x8	/* gpmc_be0n_cle.gpmc_be0n_cle,
> PULL DISA */
> +			>;
> +		};
>  	};
> 
>  	ocp {
> @@ -102,6 +122,81 @@
>  				reg = <0x48>;
>  			};
>  		};
> +
> +		elm: elm at 48080000 {
> +			status = "okay";
> +		};
> +
> +		gpmc: gpmc at 50000000 {
> +			status = "okay";
> +			pinctrl-0 = <&nandflash_pins_s0>;

It would be good, if you label this pin configuration with 'default' name,
as below -


pinctrl-names = "default";

Thanks,
Vaibhav

> +			ranges = <0 0 0x08000000 0x10000000>;	/* CS0:
> NAND */
> +			nand at 0,0 {
> +				reg = <0 0 0>; /* CS0, offset 0 */
> +				nand-bus-width = <8>;
> +				ti,nand-ecc-opt = "bch8";
> +
> +				gpmc,sync-clk = <0>;
> +				gpmc,cs-on = <0>;
> +				gpmc,cs-rd-off = <44>;
> +				gpmc,cs-wr-off = <44>;
> +				gpmc,adv-on = <6>;
> +				gpmc,adv-rd-off = <34>;
> +				gpmc,adv-wr-off = <44>;
> +				gpmc,we-off = <40>;
> +				gpmc,oe-off = <54>;
> +				gpmc,access = <64>;
> +				gpmc,rd-cycle = <82>;
> +				gpmc,wr-cycle = <82>;
> +				gpmc,wr-access = <40>;
> +				gpmc,wr-data-mux-bus = <0>;
> +
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				elm_id = <&elm>;
> +
> +				/* MTD partition table */
> +				partition at 0 {
> +					label = "SPL1";
> +					reg = <0x00000000 0x000020000>;
> +				};
> +
> +				partition at 1 {
> +					label = "SPL2";
> +					reg = <0x00020000 0x00020000>;
> +				};
> +
> +				partition at 2 {
> +					label = "SPL3";
> +					reg = <0x00040000 0x00020000>;
> +				};
> +
> +				partition at 3 {
> +					label = "SPL4";
> +					reg = <0x00060000 0x00020000>;
> +				};
> +
> +				partition at 4 {
> +					label = "U-boot";
> +					reg = <0x00080000 0x001e0000>;
> +				};
> +
> +				partition at 5 {
> +					label = "environment";
> +					reg = <0x00260000 0x00020000>;
> +				};
> +
> +				partition at 6 {
> +					label = "Kernel";
> +					reg = <0x00280000 0x00500000>;
> +				};
> +
> +				partition at 7 {
> +					label = "File-System";
> +					reg = <0x00780000 0x0F880000>;
> +				};
> +			};
> +		};
>  	};
> 
>  	vbat: fixedregulator at 0 {
> --
> 1.8.1



From B35083 at freescale.com  Thu May  2 05:20:18 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Thu, 2 May 2013 09:20:18 +0000
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <20130502085233.GO32299@pengutronix.de>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
 <20130502085233.GO32299@pengutronix.de>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851B3C47@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
>Sent: Thursday, May 02, 2013 4:53 PM
>To: Lu Jingchang-B35083
>Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org
>Subject: Re: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
>
>> +static int __init pit_clocksource_init(struct clk *pit_clk) {
>> +	unsigned int c = clk_get_rate(pit_clk);
>> +
>> +	sched_clock_reg = clksrc_base + PITCVAL;
>> +
>> +	setup_sched_clock(mvf_read_sched_clock, 32, c);
>> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300,
>32,
>> +			clocksource_mmio_readl_down);
>> +}
>> +
>> +/* set clock event */
>> +static int pit_set_next_event(unsigned long delta,
>> +				struct clock_event_device *unused) {
>> +	pit_timer_disable();
>> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
>> +	pit_irq_acknowledge();
>> +	pit_timer_enable();
>
>You disable/enable the timer each time here, is this necessary? You will
>get a drift in the timer, that's really not nice.
>
[Lu Jingchang-B35083] 
  Disable/enable the timer each time is due to the pit hardware mechanism: Writing a new value to PIT_LDVAL register will not restart the timer; instead the value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again.
  It won't affect the clocksoure timer which runs continuously and separately.
  Thanks!


Best Regards,
Jingchang Lu




From pekon at ti.com  Thu May  2 05:43:21 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 2 May 2013 15:13:21 +0530
Subject: [PATCH v3,1/3] ARM: dts: AM33XX: Add ELM node
Message-ID: <7fa7438c9a7c5da575d762423815625d523c4689.1359007746.git.avinashphilip@ti.com>

From: "Philip, Avinash" <avinashphilip at ti.com>

Add ELM data node to AM33XX device tree file.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
Acked-by: Peter Korsgaard <jacmet at sunsite.dk>
Signed-off-by: Pekon Gupta <pekon at ti.com>

---
Changes in v2:
	- Replace <xx> literals to 52
	- remove tab

 arch/arm/boot/dts/am33xx.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..24fc835 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -399,5 +399,13 @@
 			       0x44d80000 0x2000>;	/* M3 DMEM */
 			ti,hwmods = "wkup_m3";
 		};
+
+		elm: elm at 48080000 {
+			compatible = "ti,am3352-elm";
+			reg = <0x48080000 0x2000>;
+			interrupts = <4>;
+			ti,hwmods = "elm";
+			status = "disabled";
+		};
 	};
 };


From pekon at ti.com  Thu May  2 05:44:03 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 2 May 2013 15:14:03 +0530
Subject: [PATCH v3,2/3] ARM: dts: AM33XX: Add GPMC node
Message-ID: <2645efefa3d36388ff1d4b64255d880b6587770f.1359007746.git.avinashphilip@ti.com>

From: "Philip, Avinash" <avinashphilip at ti.com>

Add GPMC data node to AM33XX device tree file.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
Acked-by: Peter Korsgaard <jacmet at sunsite.dk>
Signed-off-by: Pekon Gupta <pekon at ti.com>

---
Changes in v2:
	- Change number of chip select to 7

 arch/arm/boot/dts/am33xx.dtsi |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 24fc835..1048795 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -407,5 +407,17 @@
 			ti,hwmods = "elm";
 			status = "disabled";
 		};
+
+		gpmc: gpmc at 50000000 {
+			compatible = "ti,am3352-gpmc";
+			ti,hwmods = "gpmc";
+			reg = <0x50000000 0x2000>;
+			interrupts = <100>;
+			num-cs = <7>;
+			num-waitpins = <2>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
 	};
 };


From pekon at ti.com  Thu May  2 05:44:28 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 2 May 2013 15:14:28 +0530
Subject: [PATCH v3,
 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evm
Message-ID: <1367487868-14767-1-git-send-email-pekon@ti.com>

From: Philip Avinash <avinashphilip at ti.com>

NAND flash connected in am335x-evm on GPMC controller. This patch adds
device tree node in am3355-evm with GPMC contoller timing for NAND flash
interface, NAND partition table, ECC scheme, elm handle id.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
Signed-off-by: Gupta, Pekon <pekon at ti.com>

---
Changes in v3:
	- moved GPMC pin-mux config to nand node

 arch/arm/boot/dts/am335x-evm.dts | 95 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..0b8f161 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,26 @@
 				0x154 0x27	/* spi0_d0.gpio0_3, INPUT | MODE7 */
 			>;
 		};
+
+		nandflash_pins_s0: nandflash_pins_s0 {
+			pinctrl-single,pins = <
+				0x0 0x30	/* gpmc_ad0.gpmc_ad0, INPUT | PULLUP | MODE0 */
+				0x4 0x30	/* gpmc_ad1.gpmc_ad1, INPUT | PULLUP | MODE0 */
+				0x8 0x30	/* gpmc_ad2.gpmc_ad2, INPUT | PULLUP | MODE0 */
+				0xc 0x30	/* gpmc_ad3.gpmc_ad3, INPUT | PULLUP | MODE0 */
+				0x10 0x30	/* gpmc_ad4.gpmc_ad4, INPUT | PULLUP | MODE0 */
+				0x14 0x30	/* gpmc_ad5.gpmc_ad5, INPUT | PULLUP | MODE0 */
+				0x18 0x30	/* gpmc_ad6.gpmc_ad6, INPUT | PULLUP | MODE0 */
+				0x1c 0x30	/* gpmc_ad7.gpmc_ad7, INPUT | PULLUP | MODE0 */
+				0x70 0x30	/* gpmc_wait0.gpmc_wait0, INPUT | PULLUP | MODE0 */
+				0x74 0x37	/* gpmc_wpn.gpio0_30, INPUT | PULLUP | MODE7 */
+				0x7c 0x8	/* gpmc_csn0.gpmc_csn0,  PULL DISA */
+				0x90 0x8	/* gpmc_advn_ale.gpmc_advn_ale, PULL DISA */
+				0x94 0x8	/* gpmc_oen_ren.gpmc_oen_ren, PULL DISA */
+				0x98 0x8	/* gpmc_wen.gpmc_wen, PULL DISA */
+				0x9c 0x8	/* gpmc_be0n_cle.gpmc_be0n_cle, PULL DISA */
+			>;
+		};
 	};
 
 	ocp {
@@ -102,6 +122,82 @@
 				reg = <0x48>;
 			};
 		};
+
+		elm: elm at 48080000 {
+			status = "okay";
+		};
+
+		gpmc: gpmc at 50000000 {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&nandflash_pins_s0>;
+			ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+			nand at 0,0 {
+				reg = <0 0 0>; /* CS0, offset 0 */
+				nand-bus-width = <8>;
+				ti,nand-ecc-opt = "bch8";
+
+				gpmc,sync-clk = <0>;
+				gpmc,cs-on = <0>;
+				gpmc,cs-rd-off = <44>;
+				gpmc,cs-wr-off = <44>;
+				gpmc,adv-on = <6>;
+				gpmc,adv-rd-off = <34>;
+				gpmc,adv-wr-off = <44>;
+				gpmc,we-off = <40>;
+				gpmc,oe-off = <54>;
+				gpmc,access = <64>;
+				gpmc,rd-cycle = <82>;
+				gpmc,wr-cycle = <82>;
+				gpmc,wr-access = <40>;
+				gpmc,wr-data-mux-bus = <0>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+				elm_id = <&elm>;
+
+				/* MTD partition table */
+				partition at 0 {
+					label = "SPL1";
+					reg = <0x00000000 0x000020000>;
+				};
+
+				partition at 1 {
+					label = "SPL2";
+					reg = <0x00020000 0x00020000>;
+				};
+
+				partition at 2 {
+					label = "SPL3";
+					reg = <0x00040000 0x00020000>;
+				};
+
+				partition at 3 {
+					label = "SPL4";
+					reg = <0x00060000 0x00020000>;
+				};
+
+				partition at 4 {
+					label = "U-boot";
+					reg = <0x00080000 0x001e0000>;
+				};
+
+				partition at 5 {
+					label = "environment";
+					reg = <0x00260000 0x00020000>;
+				};
+
+				partition at 6 {
+					label = "Kernel";
+					reg = <0x00280000 0x00500000>;
+				};
+
+				partition at 7 {
+					label = "File-System";
+					reg = <0x00780000 0x0F880000>;
+				};
+			};
+		};
 	};
 
 	vbat: fixedregulator at 0 {


From linux at arm.linux.org.uk  Thu May  2 05:46:21 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 10:46:21 +0100
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502083430.GB21614@n2100.arm.linux.org.uk>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <201304301304.20650.arnd@arndb.de> <20130430114229.GA2439@linaro.org>
 <alpine.LFD.2.03.1304301110030.17372@syhkavp.arg>
 <20130430172816.GA31101@linaro.org>
 <alpine.LFD.2.03.1304301418100.17372@syhkavp.arg>
 <20130502083430.GB21614@n2100.arm.linux.org.uk>
Message-ID: <20130502094620.GC21614@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 09:34:30AM +0100, Russell King - ARM Linux wrote:
> On Tue, Apr 30, 2013 at 02:18:42PM -0400, Nicolas Pitre wrote:
> > On Tue, 30 Apr 2013, Dave Martin wrote:
> > 
> > > On Tue, Apr 30, 2013 at 11:12:12AM -0400, Nicolas Pitre wrote:
> > > > On Tue, 30 Apr 2013, Dave Martin wrote:
> > > > 
> > > > > On Tue, Apr 30, 2013 at 01:04:20PM +0200, Arnd Bergmann wrote:
> > > > > > On Tuesday 30 April 2013, Russell King - ARM Linux wrote:
> > > > > > > Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> > > > > > > great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> > > > > > > arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> > > > > > > source of errors.
> > > > > 
> > > > > [...]
> > > > >  
> > > > > > >arch/arm/common/mcpm_head.S:39: Error: selected processor does not support ARM mode `ubfx r9,r0,#0,#8'
> > > > > > >arch/arm/common/mcpm_head.S:40: Error: selected processor does not support ARM mode `ubfx r10,r0,#8,#8'
> > > > > > >arch/arm/common/mcpm_head.S:100: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/mcpm_head.S:115: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/mcpm_head.S:127: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/mcpm_head.S:131: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/mcpm_head.S:138: Error: selected processor does not support ARM mode `dsb'
> > > > > > >arch/arm/common/mcpm_head.S:152: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/mcpm_head.S:161: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/mcpm_head.S:175: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/vlock.S:62: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/vlock.S:72: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/vlock.S:72: Error: selected processor does not support ARM mode `dsb'
> > > > > > >arch/arm/common/vlock.S:89: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/vlock.S:95: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/vlock.S:95: Error: selected processor does not support ARM mode `dsb'
> > > > > > >arch/arm/common/vlock.S:102: Error: selected processor does not support ARM mode `dmb'
> > > > > > >arch/arm/common/vlock.S:105: Error: selected processor does not support ARM mode `dsb'
> > > > > > 
> > > > > > Right, the problem here is that the code was never tested with an ARMv6+ARMv7 config.
> > > > > > We can either fix it up by adding
> > > > > > 
> > > > > > 	.arch	armv7-a
> > > > > > 
> > > > > > in the assembly files, or by doing the same in the Makefile:
> > > > > > 
> > > > > > AFLAGS_vlock.S += -march=armv7-a
> > > > > > AFLAGS_mcpm_head.S += -march=armv7-a
> > > > > 
> > > > > 
> > > > > Hmmm, this code was tested with ARCH_MULTIPLATFORM, but it looks like
> > > > > no v6 boards were configured in when testing that...
> > > > > 
> > > > > 
> > > > > Assuming people are OK with the Makefile route, here's a patch for that,
> > > > > build-tested with a v6+v7 ARCH_MULTIPLATFORM config.
> > > > 
> > > > Isn't the .arch armv7-a route a bit cleaner?  That would have been my 
> > > > choice, although I don't feel strongly about it.
> > > 
> > > I don't feel strongly either.  We already have the CFLAGS_DISABLE stuff,
> > > so it didn't feel that unnatural to add this in the Makefile; but .arch
> > > would work equally well.
> > > 
> > > If somebody wants to change it, it's not a problem for me, but I didn't
> > > want to create extra disruption by proposing a different patch...
> > 
> > Fair enough.
> > 
> > Acked-by: Nicolas Pitre <nico at linaro.org>
> 
> I see Dave Martin has sent a patch for this without your ack.  Was that
> a mistake?

... and the patch in the patch system doesn't apply anyway because its
against some other tree.  I've no idea what it's against, it's not as
the version on the patch advertises (v3.9-rc7) and not even the build
tree has the three additional FIQ lines at the end (so it's not in
arm-soc):

 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_ARM_TIMER_SP804)  += timer-sp.o
 obj-$(CONFIG_MCPM)             += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock...
+AFLAGS_mcpm_head.o             := -march=armv7-a
+AFLAGS_vlock.o                 := -march=armv7-a
 CFLAGS_REMOVE_mcpm_entry.o     = -pg
 obj-$(CONFIG_FIQ_GLUE)         += fiq_glue.o fiq_glue_setup.o
 obj-$(CONFIG_FIQ_DEBUGGER)     += fiq_debugger.o

So, this is unapplyable.


From catalin.marinas at arm.com  Thu May  2 05:54:31 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 10:54:31 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130501190441.GA22227@schnuecks.de>
References: <20121118211005.GW22106@titan.lakedaemon.net>
 <20130418111608.GF27197@titan.lakedaemon.net>
 <20130418112201.GQ14496@n2100.arm.linux.org.uk>
 <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
Message-ID: <20130502095431.GA20730@arm.com>

On Wed, May 01, 2013 at 08:04:41PM +0100, Simon Baatz wrote:
> On Wed, May 01, 2013 at 03:22:06PM +0100, Catalin Marinas wrote:
> > On Tue, Apr 30, 2013 at 10:04:03PM +0100, Simon Baatz wrote:
> > > On Tue, Apr 30, 2013 at 12:22:25PM +0100, Catalin Marinas wrote:
> > > > On Sun, Apr 21, 2013 at 11:06:30PM +0100, Simon Baatz wrote:
> > > > > On Thu, Apr 18, 2013 at 02:51:04PM +0100, Catalin Marinas wrote:
> > > > > > On Thu, Apr 18, 2013 at 12:40:16PM +0100, Jason Cooper wrote:
> > > ...
> > > > > 
> > > > > It is not the driver itself which is using the API, it is the
> > > > > generic scatterlist memory iterator. And I don't think that this is
> > > > > wrong, as I have tried to explain in [1].
> > > > 
> > > > Trying to remember what we've discussed over the past months on this
> > > > topic. It looks like sg_miter_stop() does the right thing in calling
> > > > flush_kernel_dcache_page(). Commit f8b63c1 (ARM: 6382/1: Remove
> > > > superfluous flush_kernel_dcache_page()) removed this function entirely.
> > > > The code previously had this comment - /* highmem pages are always
> > > > flushed upon kunmap already */ which I think it wasn't fully correct
> > > > either. The kunmap_atomic() flushes the caches but kunmap() doesn't, so
> > > > I suspect we only get the flushing if SG_MITER_ATOMIC.
> > > > 
> > > > So it looks to me like flush_kernel_dcache_page() should be implemented
> > > > even for highmem pages (with VIVT or aliasing VIPT, at least for non
> > > > kmap_atomic addresses by checking for FIXADDR_START). If highmem is
> > > > disabled, I suspect we still need this function since the calling code
> > > > doesn't care whether kmap/kunmap was a no-op. But can we keep it as a
> > > > simple call to __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE)?
> > > 
> > > My first version ([1]) had:
> > > 
> > > 	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
> > > 		__flush_kernel_dcache_page(page);
> > > 
> > > If I understand this correctly, you are proposing to remove the
> > > highmem exclusion.
> > 
> > The highmem exclusion may have been there originally because of a
> > comment suggesting that kunmap() does the flushing. This is the case
> > only for kunmap_atomic() AFAICT (and maybe we could remove that as well
> > and rely on flush_kernel_dcache_page() being called).
> > 
> > > And then in __flush_kernel_dcache_page():
> > > 
> > > 	mapping = page_mapping(page);
> > > 
> > > 	if (!mapping || mapping_mapped(mapping))
> > > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > > 
> > > I still prefer to have this condition here to avoid the flush when
> > > there is no user mapping at all.  This is handled by lazy flushing
> > > and is probably the most common case anyway (given how many people
> > > seem to be affected by this problem).
> > 
> > Looking at the old thread, you said there is a case when this condition
> > is not true (O_DIRECT case). If that's for a page cache page, then we
> > can handle it lazily (for anonymous pages I don't think we can rely on
> > lazy flushing since the kernel does not guarantee the clearing of the
> > PG_arch_1 bit).
> 
> As Russel pointed out in a comment to a later version of the patch,
> PG_arch_1 makes only sense for page cache pages. The condition above
> is ok from my point of view (it is based on what flush_dcache_page()
> uses):
> 
> - Page cache page without user space mapping:
> mapping != NULL and mapping_mapped() == 0
> 
> -> no flush here; lazy flush based on PG_arch_1 later if needed (we
>    rely on the proper initialization of the page to "dirty" here.)

Indeed.

> - Page cache page with user space mapping:
> mapping != NULL and mapping_mapped() != 0
> 
> -> kernel mapping flushed here (user mapping can be assumed to be clean)

We had similar thoughts for AArch64 here and decided it's not needed, it
can just clear the PG_arch_1 bit and do it lazily (patches not pushed
yet, need more testing). This assumes that even if mapping_mapped(), the
page is not actually mapped in user space and we eventually get a
set_pte_at() call. That's what powerpc is doing.

> - Anonymous page:
> mapping == NULL
> 
> -> kernel mapping flushed here (user mapping can be assumed to be clean)

I don't think it should care about anonymous pages at all. I put a
WARN_ON(!mapping) in flush_dcache_page() and it hasn't triggered yet,
though not intensive testing.

> > > Additionally, although we can assume that the page is kmapped,
> > > page_address(page) can still be NULL for a highmem page, right?
> > 
> > It looks like kmap() always sets page_address(page) but I'm not sure
> > about kmap_atomic(), it doesn't seem to.
> 
> Hmm, in __flush_dcache_page() we have the following code to flush the
> kernel mapping:
> 
> void __flush_dcache_page(struct address_space *mapping, struct page *page)
> {
> 	/*
> 	 * Writeback any data associated with the kernel mapping of this
> 	 * page.  This ensures that data in the physical page is mutually
> 	 * coherent with the kernels mapping.
> 	 */
> 	if (!PageHighMem(page)) {
> 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> 	} else {
> 		void *addr = kmap_high_get(page);
> 		if (addr) {
> 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> 			kunmap_high(page);
> 		} else if (cache_is_vipt()) {
> 			/* unmapped pages might still be cached */
> 			addr = kmap_atomic(page);
> 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> 			kunmap_atomic(addr);
> 		}
> 	}
> ...
> 
> 
> We probably should reuse it in flush_kernel_dcache_page() to flush
> the kernel mapping. (The last else clause looks strange though)

I think it makes sense to reuse this logic in
flush_kernel_dcache_page(). If the page is already mapped with kmap,
then kmap_high_get() should return the actual address. If it was mapped
with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
clause and the additional kmap_atomic(). The cache_is_vipt() check is
useful because kunmap_atomic() would flush VIVT caches anyway.

As for __flush_dcache_page() called from other places like
flush_dcache_page(), because of this 'else if' clause it looks like it
misses flushing unmapped highmem pages on VIVT cache.

-- 
Catalin


From catalin.marinas at arm.com  Thu May  2 06:00:00 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 11:00:00 +0100
Subject: [RFC PATCH 8/9] ARM64: mm: Introduce MAX_ZONE_ORDER for 64K
 and THP.
In-Reply-To: <1367339448-21727-9-git-send-email-steve.capper@linaro.org>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-9-git-send-email-steve.capper@linaro.org>
Message-ID: <20130502100000.GB20730@arm.com>

On Tue, Apr 30, 2013 at 05:30:47PM +0100, Steve Capper wrote:
> The buddy allocator has a default order of 11, which is too low to
> allocate enough memory for 512MB Transparent HugePages if our base
> page size is 64K. For any order less than 13, the combination of
> THP with 64K pages will cause a compile error.
> 
> This patch introduces the MAX_ZONE_ORDER config option that allows
> one to explicitly override the order of the buddy allocator. If
> 64K pages and THP are enabled the minimum value is set to 13.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> ---
>  arch/arm64/Kconfig | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 16aa780..908fd95 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -196,6 +196,23 @@ config ARCH_WANT_HUGE_PMD_SHARE
>  
>  source "mm/Kconfig"
>  
> +config FORCE_MAX_ZONEORDER
> +	int "Maximum zone order"
> +	range 11 64 if !(ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
> +	range 13 64 if ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE
> +	default "11" if !(ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
> +	default "13" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)

Can we just keep some sane defaults here without giving too much choice
to the user? Something like:

config FORCE_MAX_ZONEORDER
	int
	default "13" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
	default "11"

We can extend it later if people need this but I'm aiming for a single
config on a multitude of boards.

-- 
Catalin


From steve.capper at linaro.org  Thu May  2 06:05:08 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 2 May 2013 11:05:08 +0100
Subject: [RFC PATCH 8/9] ARM64: mm: Introduce MAX_ZONE_ORDER for 64K
 and THP.
In-Reply-To: <20130502100000.GB20730@arm.com>
References: <1367339448-21727-1-git-send-email-steve.capper@linaro.org>
 <1367339448-21727-9-git-send-email-steve.capper@linaro.org>
 <20130502100000.GB20730@arm.com>
Message-ID: <20130502100507.GA19880@linaro.org>

On Thu, May 02, 2013 at 11:00:00AM +0100, Catalin Marinas wrote:
> On Tue, Apr 30, 2013 at 05:30:47PM +0100, Steve Capper wrote:
 
> Can we just keep some sane defaults here without giving too much choice
> to the user? Something like:
> 
> config FORCE_MAX_ZONEORDER
> 	int
> 	default "13" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
> 	default "11"
> 
> We can extend it later if people need this but I'm aiming for a single
> config on a multitude of boards.
> 
> -- 
> Catalin

Thanks, that does look a lot neater :-).

-- 
Steve


From peter.maydell at linaro.org  Thu May  2 06:06:09 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Thu, 2 May 2013 11:06:09 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <87sj27xxjr.fsf@rustcorp.com.au>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
Message-ID: <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>

On 1 May 2013 03:07, Rusty Russell <rusty at rustcorp.com.au> wrote:
> An emergency output is a reasonable idea, and this is a reasonable
> implementation.  The question is practical: will it be used?  Because we
> don't implement reasonable ideas which aren't going to be used.

If you think it fits reasonably into the virtio spec (ie doesn't
implement things at the wrong level of the transport/backend
abstraction) then we can implement it in QEMU, and I think it
makes more sense to do this than to throw in a random extra
serial port.

To be actually useful we need to also specify something in
the device tree to say "here is where you will find your
emergency output and what it is".

thanks
-- PMM


From skannan at codeaurora.org  Thu May  2 06:09:24 2013
From: skannan at codeaurora.org (skannan at codeaurora.org)
Date: Thu, 2 May 2013 03:09:24 -0700
Subject: [Patch 2/3] clk: skip re-parenting orphan clk
In-Reply-To: <1367475929-32166-3-git-send-email-ambresh@ti.com>
References: <1367475929-32166-1-git-send-email-ambresh@ti.com>
 <1367475929-32166-3-git-send-email-ambresh@ti.com>
Message-ID: <f023185a0414961d3c30b3cfaf8b9a51.squirrel@www.codeaurora.org>


Ambresh K wrote:
> From: Ambresh K <ambresh at ti.com>
>
> If clk is same as orphan clk than skip the iteration, there

Typo: than => then

> by avoiding unnecessary look-up.
>
> Signed-off-by: Ambresh K <ambresh at ti.com>
> ---
>  drivers/clk/clk.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index c187321..f4d2c73 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1635,6 +1635,10 @@ int __clk_init(struct device *dev, struct clk *clk)
>  	 * this clock
>  	 */
>  	hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
> +		/* Skip if clk is same as orphan clk */
> +		if (!strcmp(clk->name, orphan->name))
> +			continue;
> +
>  		if (orphan->ops->get_parent) {
>  			i = orphan->ops->get_parent(orphan->hw);
>  			if (i < 0) {
> --
> 1.7.4.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From acourbot at nvidia.com  Thu May  2 06:20:10 2013
From: acourbot at nvidia.com (Alex Courbot)
Date: Thu, 2 May 2013 19:20:10 +0900
Subject: [GIT PULL] Removal of GENERIC_GPIO
Message-ID: <51823DDA.7010103@nvidia.com>

Hi Grant,

Here is the pull request for the GENERIC_GPIO removal. It is almost 
certain that a few fixups will be necessary - while I don't have precise 
patches, the following steps should ensure the state of the code is clean:

* "git grep CONFIG_GENERIC_GPIO" should return 0 hits. Matches should be 
replaced with CONFIG_GPIOLIB
* "git grep '\bGENERIC_GPIO\b'" should return 1 hit in the Chinese 
documentation. Selectors of GENERIC_GPIO should be turned into selectors 
of GPIOLIB, while definitions of the option in architecture code should 
be deleted.

Please let me know if there is something more I can do to ease your task.

Thanks,
Alex.

The following changes since commit 10b38669d64c757cfd927e3820292c580ed70aae:

   Merge tag 'for-linus-v3.9-rc4' of git://oss.sgi.com/xfs/xfs 
(2013-03-19 15:17:40 -0700)

are available in the git repository at:

   git://github.com/Gnurou/linux.git for_grant

for you to fetch changes up to f4c54050640e7afa4749875cf9b900d42db361c0:

   gpio: update gpio Chinese documentation (2013-04-16 18:47:22 +0900)

----------------------------------------------------------------
Alexandre Courbot (18):
       mips: remove redundant GENERIC_GPIO select
       mips: loongson: use GPIO driver on CONFIG_GPIOLIB
       mips: txx9: change GENERIC_GPIO to GPIOLIB
       mips: alchemy: require gpiolib
       arm: remove redundant GENERIC_GPIO selection
       arm: plat-orion: use GPIO driver on CONFIG_GPIOLIB
       unicore32: remove unneeded select GENERIC_GPIO
       unicore32: default GENERIC_GPIO to false
       powerpc: remove redundant GENERIC_GPIO selection
       sh: replace CONFIG_GENERIC_GPIO by CONFIG_GPIOLIB
       xtensa: remove explicit selection of GENERIC_GPIO
       avr32: default GENERIC_GPIO to false
       openrisc: default GENERIC_GPIO to false
       mips: pnx833x: remove requirement for GENERIC_GPIO
       m68k: coldfire: use gpiolib
       blackfin: force use of gpiolib
       Convert selectors of GENERIC_GPIO to GPIOLIB
       Remove GENERIC_GPIO config option

Chen Baozi (1):
       gpio: update gpio Chinese documentation

  Documentation/gpio.txt               | 10 +++++-----
  Documentation/zh_CN/gpio.txt         |  8 ++++----
  arch/alpha/Kconfig                   |  3 ---
  arch/arm/Kconfig                     |  3 ---
  arch/arm/plat-orion/Makefile         |  2 +-
  arch/arm/plat-orion/gpio.c           |  2 +-
  arch/arm64/Kconfig                   |  3 ---
  arch/avr32/Kconfig                   |  3 ---
  arch/blackfin/Kconfig                |  5 +----
  arch/hexagon/Kconfig                 |  3 ---
  arch/ia64/Kconfig                    |  3 ---
  arch/m68k/Kconfig                    |  3 ---
  arch/m68k/Kconfig.cpu                |  3 +--
  arch/metag/Kconfig                   |  3 ---
  arch/microblaze/Kconfig              |  3 ---
  arch/mips/Kconfig                    | 10 +---------
  arch/mips/loongson/common/Makefile   |  2 +-
  arch/mips/txx9/generic/setup.c       |  2 +-
  arch/openrisc/Kconfig                |  3 ---
  arch/powerpc/Kconfig                 |  5 -----
  arch/powerpc/platforms/40x/Kconfig   |  1 -
  arch/powerpc/platforms/44x/Kconfig   |  1 -
  arch/powerpc/platforms/85xx/Kconfig  |  1 -
  arch/powerpc/platforms/86xx/Kconfig  |  3 ---
  arch/powerpc/platforms/8xx/Kconfig   |  1 -
  arch/powerpc/platforms/Kconfig       |  4 ----
  arch/sh/Kconfig                      |  3 ---
  arch/sh/boards/mach-sdk7786/Makefile |  2 +-
  arch/sh/boards/mach-x3proto/Makefile |  2 +-
  arch/sh/kernel/cpu/sh2a/Makefile     |  2 +-
  arch/sh/kernel/cpu/sh3/Makefile      |  2 +-
  arch/sh/kernel/cpu/sh4a/Makefile     |  2 +-
  arch/sparc/Kconfig                   |  5 -----
  arch/unicore32/Kconfig               |  6 +-----
  arch/x86/Kconfig                     |  3 ---
  arch/xtensa/Kconfig                  |  3 ---
  arch/xtensa/configs/iss_defconfig    |  1 -
  arch/xtensa/configs/s6105_defconfig  |  1 -
  drivers/extcon/Kconfig               |  2 +-
  drivers/gpio/Kconfig                 |  1 -
  drivers/gpio/gpio-lpc32xx.c          |  2 +-
  drivers/i2c/busses/Kconfig           |  4 ++--
  drivers/i2c/muxes/Kconfig            |  2 +-
  drivers/input/keyboard/Kconfig       |  6 +++---
  drivers/input/misc/Kconfig           |  8 ++++----
  drivers/input/mouse/Kconfig          |  2 +-
  drivers/leds/Kconfig                 |  6 +++---
  drivers/mtd/maps/Kconfig             |  2 +-
  drivers/mtd/nand/Kconfig             |  2 +-
  drivers/net/phy/Kconfig              |  2 +-
  drivers/pinctrl/sh-pfc/Kconfig       | 26 +++++++++++++-------------
  drivers/regulator/Kconfig            |  2 +-
  drivers/spi/Kconfig                  |  8 ++++----
  drivers/staging/android/Kconfig      |  2 +-
  drivers/staging/iio/accel/Kconfig    |  2 +-
  drivers/staging/iio/adc/Kconfig      |  2 +-
  drivers/staging/iio/addac/Kconfig    |  2 +-
  drivers/staging/iio/resolver/Kconfig |  4 ++--
  drivers/staging/iio/trigger/Kconfig  |  2 +-
  drivers/usb/otg/Kconfig              |  2 +-
  drivers/video/Kconfig                |  2 +-
  drivers/video/backlight/Kconfig      |  4 ++--
  drivers/w1/masters/Kconfig           |  2 +-
  include/linux/gpio.h                 |  6 +++---
  64 files changed, 74 insertions(+), 153 deletions(-)


From nicolas.ferre at atmel.com  Thu May  2 06:34:55 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 2 May 2013 12:34:55 +0200
Subject: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
 xfer->speed_hz set
In-Reply-To: <CACQ1gAhZO3stjrwf5SiZf7jOO8T5bAJZiz97M7+7vwFmk2e65g@mail.gmail.com>
References: <1362626715-6549-1-git-send-email-wenyou.yang@atmel.com>
 <1362626815-6628-1-git-send-email-wenyou.yang@atmel.com>
 <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
 <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>
 <CACQ1gAhZO3stjrwf5SiZf7jOO8T5bAJZiz97M7+7vwFmk2e65g@mail.gmail.com>
Message-ID: <5182414F.1000201@atmel.com>

On 02/05/2013 10:12, Richard Genoud :
> 2013/5/2 Yang, Wenyou <Wenyou.Yang at atmel.com>:
>> Hi, Joachim,
>>
>>> -----Original Message-----
>>> From: Joachim Eastwood [mailto:manabian at gmail.com]
>>> Sent: 2013?3?7? 20:31
>>> To: Yang, Wenyou
>>> Cc: linux-arm-kernel at lists.infradead.org; grant.likely at secretlab.ca; Ferre,
>>> Nicolas; plagnioj at jcrosoft.com; richard.genoud at gmail.com; Lin, JM;
>>> spi-devel-general at lists.sourceforge.net; linux-kernel at vger.kernel.org
>>> Subject: Re: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
>>> xfer->speed_hz set
>>>
>>> On 7 March 2013 04:26, Wenyou Yang <wenyou.yang at atmel.com> wrote:
>>>> commit: 059b8ffeee5b427949872bb6ed5db5ae0788054e
>>>> cause the atmel spi probing failure.
>>>>
>>>> Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
>>>> Cc: spi-devel-general at lists.sourceforge.net
>>>> Cc: linux-kernel at vger.kernel.org
>>>> ---
>>>>   drivers/spi/spi-atmel.c |    6 +++---
>>>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
>>>> index 656d137..1eca815 100644
>>>> --- a/drivers/spi/spi-atmel.c
>>>> +++ b/drivers/spi/spi-atmel.c
>>>> @@ -846,9 +846,9 @@ static int atmel_spi_transfer(struct spi_device *spi,
>>> struct spi_message *msg)
>>>>                          }
>>>>                  }
>>>>
>>>> -               /* FIXME implement these protocol options!! */
>>>> -               if (xfer->speed_hz) {
>>>> -                       dev_dbg(&spi->dev, "no protocol options
>>> yet\n");
>>>> +               if (xfer->speed_hz < spi->max_speed_hz) {
>>>> +                       dev_dbg(&spi->dev,
>>>> +                               "speed in transfer less than bus
>>> speed\n");
>>>>                          return -ENOPROTOOPT;
>>>>                  }
>>>
>>> I sent a similar patch to spi-devl a while ago, which Grant said he applied.
>>> https://patchwork.kernel.org/patch/2165301/
>>>
>>> Can't find the patch in any upstream git tree so I guess Grant hasn't
>>> pushed it yet.
>> This patch hasn't still applied in any upstream git tree, so Atmel spi master doesn't work.
>> Could you help do some ping it?
>
> it's in linux-next:
> 3d3522604a5557e80fdcab61c54bd04eaf15b525
> merged from spi-current/spi/merge

Thanks Richard, yes I can find it here:
http://git.secretlab.ca/?p=linux.git;a=commit;h=3d3522604a5557e80fdcab61c54bd04eaf15b525

Grant, Mark,

Can you tell us if this SPI patch will be merged upstream using one of 
your paths?

Best regards,
-- 
Nicolas Ferre


From stefano.stabellini at eu.citrix.com  Thu May  2 06:38:12 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 11:38:12 +0100
Subject: [Xen-devel] [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <1367482862.21869.28.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367482862.21869.28.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305021134160.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Ian Campbell wrote:
> On Wed, 2013-05-01 at 20:27 +0100, Stefano Stabellini wrote:
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index d30042e..8f040a0 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -14,6 +14,7 @@
> >  #include <xen/xen-ops.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> > +#include <asm/arch_timer.h>
> >  #include <asm/system_misc.h>
> >  #include <linux/interrupt.h>
> >  #include <linux/irqreturn.h>
> > @@ -172,6 +173,8 @@ static int __init xen_secondary_init(unsigned int cpu)
> >  		   later ones fail to. */
> >  		per_cpu(xen_vcpu, cpu) = vcpup;
> >  	}
> > +
> > +	xen_setup_runstate_info(cpu);
> 
> Is this called for the boot processor too?

Yep.

> (do you have a linux-next branch where I can easily find the baseline
> for this series?)

git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_1

It's based on my 3.9-rc3-smp-6 branch currently in linux-next (that is
based on 3.9-rc3).
However lost_ticks_1 is not in linux-next yet.


From dave.martin at linaro.org  Thu May  2 06:40:18 2013
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 2 May 2013 11:40:18 +0100
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502094620.GC21614@n2100.arm.linux.org.uk>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <201304301304.20650.arnd@arndb.de>
 <20130430114229.GA2439@linaro.org>
 <alpine.LFD.2.03.1304301110030.17372@syhkavp.arg>
 <20130430172816.GA31101@linaro.org>
 <alpine.LFD.2.03.1304301418100.17372@syhkavp.arg>
 <20130502083430.GB21614@n2100.arm.linux.org.uk>
 <20130502094620.GC21614@n2100.arm.linux.org.uk>
Message-ID: <20130502104018.GA9879@linaro.org>

On Thu, May 02, 2013 at 10:46:21AM +0100, Russell King - ARM Linux wrote:
> On Thu, May 02, 2013 at 09:34:30AM +0100, Russell King - ARM Linux wrote:
> > On Tue, Apr 30, 2013 at 02:18:42PM -0400, Nicolas Pitre wrote:
> > > On Tue, 30 Apr 2013, Dave Martin wrote:
> > > 
> > > > On Tue, Apr 30, 2013 at 11:12:12AM -0400, Nicolas Pitre wrote:
> > > > > On Tue, 30 Apr 2013, Dave Martin wrote:
> > > > > 
> > > > > > On Tue, Apr 30, 2013 at 01:04:20PM +0200, Arnd Bergmann wrote:
> > > > > > > On Tuesday 30 April 2013, Russell King - ARM Linux wrote:
> > > > > > > > Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> > > > > > > > great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> > > > > > > > arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> > > > > > > > source of errors.
> > > > > > 
> > > > > > [...]
> > > > > >  
> > > > > > > >arch/arm/common/mcpm_head.S:39: Error: selected processor does not support ARM mode `ubfx r9,r0,#0,#8'
> > > > > > > >arch/arm/common/mcpm_head.S:40: Error: selected processor does not support ARM mode `ubfx r10,r0,#8,#8'
> > > > > > > >arch/arm/common/mcpm_head.S:100: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/mcpm_head.S:115: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/mcpm_head.S:127: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/mcpm_head.S:131: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/mcpm_head.S:138: Error: selected processor does not support ARM mode `dsb'
> > > > > > > >arch/arm/common/mcpm_head.S:152: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/mcpm_head.S:161: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/mcpm_head.S:175: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/vlock.S:62: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/vlock.S:72: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/vlock.S:72: Error: selected processor does not support ARM mode `dsb'
> > > > > > > >arch/arm/common/vlock.S:89: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/vlock.S:95: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/vlock.S:95: Error: selected processor does not support ARM mode `dsb'
> > > > > > > >arch/arm/common/vlock.S:102: Error: selected processor does not support ARM mode `dmb'
> > > > > > > >arch/arm/common/vlock.S:105: Error: selected processor does not support ARM mode `dsb'
> > > > > > > 
> > > > > > > Right, the problem here is that the code was never tested with an ARMv6+ARMv7 config.
> > > > > > > We can either fix it up by adding
> > > > > > > 
> > > > > > > 	.arch	armv7-a
> > > > > > > 
> > > > > > > in the assembly files, or by doing the same in the Makefile:
> > > > > > > 
> > > > > > > AFLAGS_vlock.S += -march=armv7-a
> > > > > > > AFLAGS_mcpm_head.S += -march=armv7-a
> > > > > > 
> > > > > > 
> > > > > > Hmmm, this code was tested with ARCH_MULTIPLATFORM, but it looks like
> > > > > > no v6 boards were configured in when testing that...
> > > > > > 
> > > > > > 
> > > > > > Assuming people are OK with the Makefile route, here's a patch for that,
> > > > > > build-tested with a v6+v7 ARCH_MULTIPLATFORM config.
> > > > > 
> > > > > Isn't the .arch armv7-a route a bit cleaner?  That would have been my 
> > > > > choice, although I don't feel strongly about it.
> > > > 
> > > > I don't feel strongly either.  We already have the CFLAGS_DISABLE stuff,
> > > > so it didn't feel that unnatural to add this in the Makefile; but .arch
> > > > would work equally well.
> > > > 
> > > > If somebody wants to change it, it's not a problem for me, but I didn't
> > > > want to create extra disruption by proposing a different patch...
> > > 
> > > Fair enough.
> > > 
> > > Acked-by: Nicolas Pitre <nico at linaro.org>
> > 
> > I see Dave Martin has sent a patch for this without your ack.  Was that
> > a mistake?

My bad -- Nico asked me to send you the patch, but I neglected to add
his ack.
 
> ... and the patch in the patch system doesn't apply anyway because its
> against some other tree.  I've no idea what it's against, it's not as
> the version on the patch advertises (v3.9-rc7) and not even the build
> tree has the three additional FIQ lines at the end (so it's not in
> arm-soc):
> 
>  obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
>  obj-$(CONFIG_ARM_TIMER_SP804)  += timer-sp.o
>  obj-$(CONFIG_MCPM)             += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock...
> +AFLAGS_mcpm_head.o             := -march=armv7-a
> +AFLAGS_vlock.o                 := -march=armv7-a
>  CFLAGS_REMOVE_mcpm_entry.o     = -pg
>  obj-$(CONFIG_FIQ_GLUE)         += fiq_glue.o fiq_glue_setup.o
>  obj-$(CONFIG_FIQ_DEBUGGER)     += fiq_debugger.o
> 
> So, this is unapplyable.

...and this was a plain screwup up my part.  v3.9* could not possibly
contain the relevant patches, but somehow I convinced myself I had test-
applied the patch on 3.9-rc7, instead of a local tree based on that.

I've sent you a patch based on devel-stable which should apply.

Apologies for the churn.

Cheers
---Dave


From maxime.ripard at free-electrons.com  Thu May  2 06:45:56 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu,  2 May 2013 12:45:56 +0200
Subject: [PATCH 4/5] ARM: sun5i: dt: Add i2c muxing options
In-Reply-To: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367491557-6027-5-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A13 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 16df784..450b410 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -182,6 +182,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB15", "PB16";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB17", "PB18";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Thu May  2 06:45:52 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu,  2 May 2013 12:45:52 +0200
Subject: [PATCH 0/5] Add I2C support for Allwinner SoCs
Message-ID: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

This patchset adds support for the I2C controller found on most of the
Allwinner SoCs, especially the already supported A10 and A13, and the
yet to come A31.

It has been tested on a A13-Olinuxino.

Thanks,
Maxime

Maxime Ripard (5):
  i2c: sunxi: Add Allwinner A1X i2c driver
  ARM: sunxi: dt: Add i2c controller nodes to the DTSI
  ARM: sun4i: dt: Add i2c muxing options
  ARM: sun5i: dt: Add i2c muxing options
  ARM: sun5i: olinuxino: Enable the i2c controllers

 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 441 +++++++++++++++++++++
 7 files changed, 585 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Thu May  2 06:45:55 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu,  2 May 2013 12:45:55 +0200
Subject: [PATCH 3/5] ARM: sun4i: dt: Add i2c muxing options
In-Reply-To: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367491557-6027-4-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A10 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 311dcd4..63f6716 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Thu May  2 06:45:54 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu,  2 May 2013 12:45:54 +0200
Subject: [PATCH 2/5] ARM: sunxi: dt: Add i2c controller nodes to the DTSI
In-Reply-To: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367491557-6027-3-git-send-email-maxime.ripard@free-electrons.com>

The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..311dcd4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -292,5 +292,32 @@
 			clocks = <&apb1_gates 23>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..16df784 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -215,5 +215,32 @@
 			clocks = <&apb1_gates 19>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Thu May  2 06:45:53 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu,  2 May 2013 12:45:53 +0200
Subject: [PATCH 1/5] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367491557-6027-2-git-send-email-maxime.ripard@free-electrons.com>

This patch implements a basic driver for the I2C host driver found on
the Allwinner A10, A13 and A31 SoCs.

Notable missing feature is 10-bit addressing.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 441 +++++++++++++++++++++
 4 files changed, 471 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
new file mode 100644
index 0000000..40c16d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-i2c".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c at 01c2ac00 {
+	compatible = "allwinner,sun4i-i2c";
+	reg = <0x01c2ac00 0x400>;
+	interrupts = <7>;
+	clocks = <&apb1_gates 0>;
+	clock-frequency = <100000>;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index adfee98..327a49b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -706,6 +706,16 @@ config I2C_STU300
 	  This driver can also be built as a module. If so, the module
 	  will be called i2c-stu300.
 
+config I2C_SUNXI
+	tristate "Allwinner A1X I2C controller"
+	depends on ARCH_SUNXI
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controller embedded in Allwinner A1X SoCs.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called i2c-sunxi.
+
 config I2C_TEGRA
 	tristate "NVIDIA Tegra internal I2C controller"
 	depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..7225818 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
 obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
diff --git a/drivers/i2c/busses/i2c-sunxi.c b/drivers/i2c/busses/i2c-sunxi.c
new file mode 100644
index 0000000..f9f8bd4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi.c
@@ -0,0 +1,441 @@
+/*
+ * Allwinner A1X SoCs i2c controller driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)
+
+struct sunxi_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct clk		*clk;
+	struct device		*dev;
+	struct completion	completion;
+	unsigned int		irq;
+	void __iomem		*membase;
+
+	struct i2c_msg		*msg_cur;
+	u8			*msg_buf;
+	size_t			msg_buf_remaining;
+	unsigned int		msg_err;
+};
+
+static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8 value)
+{
+	writel(value, i2c_dev->membase + reg);
+}
+
+static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
+{
+	return readl(i2c_dev->membase + reg);
+}
+
+/*
+ * This is where all the magic happens. The I2C controller works as a
+ * state machine, each state being a step in the i2c protocol, with
+ * the controller sending an interrupt at each state transition.
+ *
+ * The state we're in is stored in a register, which leads to a pretty
+ * huge switch statement, all of this in the interrupt handler...
+ */
+static irqreturn_t sunxi_i2c_handler(int irq, void *data)
+{
+	struct sunxi_i2c_dev *i2c_dev = (struct sunxi_i2c_dev *)data;
+	u32 status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	u32 addr, val;
+
+	if (!(status & SUNXI_I2C_CNTR_INT_FLAG))
+		return IRQ_NONE;
+
+	/* Read the current state we're in */
+	status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_STA_REG);
+
+	switch (status & 0xff) {
+	/* Start condition has been transmitted */
+	case SUNXI_I2C_STA_START:
+	/* A repeated start condition has been transmitted */
+	case SUNXI_I2C_STA_START_REPEAT:
+		addr = SUNXI_I2C_ADDR_ADDR(i2c_dev->msg_cur->addr);
+
+		if (i2c_dev->msg_cur->flags & I2C_M_RD)
+			addr |= 1;
+
+		sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG, addr);
+		break;
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has not been
+	 * received.
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_NAK:
+	/*
+	 * Data byte has been transmitted, ACK has not been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_ACK:
+	/* Data byte has been transmitted, ACK has been received */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_ACK:
+		if (i2c_dev->msg_buf_remaining) {
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG,
+					*i2c_dev->msg_buf);
+			i2c_dev->msg_buf++;
+			i2c_dev->msg_buf_remaining--;
+			break;
+		}
+
+		if (i2c_dev->msg_buf_remaining == 0) {
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		break;
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has not been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_ACK:
+		/*
+		 * We only need to send the ACK for the all the bytes
+		 * but the last one
+		 */
+		if (i2c_dev->msg_buf_remaining > 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val | SUNXI_I2C_CNTR_ASSERT_ACK);
+		}
+
+		break;
+
+	/*
+	 * Data byte has been received, ACK has not been
+	 * transmitted
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_NAK:
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG);
+			*i2c_dev->msg_buf = val & 0xff;
+			i2c_dev->msg_buf_remaining--;
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/* Data byte has been received, ACK has been transmitted */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_ACK:
+		val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG) & 0xff;
+		*i2c_dev->msg_buf = val;
+		i2c_dev->msg_buf++;
+		i2c_dev->msg_buf_remaining--;
+
+		/* If there's only one byte left, disable the ACK */
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val & ~SUNXI_I2C_CNTR_ASSERT_ACK);
+
+		};
+
+		break;
+
+	case SUNXI_I2C_STA_BUS_ERROR:
+		i2c_dev->msg_err = SUNXI_I2C_BUS_ERROR;
+		goto out;
+
+	default:
+		i2c_dev->msg_err = SUNXI_I2C_ERROR;
+		goto out;
+	}
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	return IRQ_HANDLED;
+
+out:
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val | SUNXI_I2C_CNTR_MASTER_STOP);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	complete(&i2c_dev->completion);
+	return IRQ_HANDLED;
+}
+
+static int sunxi_i2c_xfer_msg(struct sunxi_i2c_dev *i2c_dev,
+			      struct i2c_msg *msg)
+{
+	int time_left;
+	u32 val;
+
+	i2c_dev->msg_cur = msg;
+	i2c_dev->msg_buf = msg->buf;
+	i2c_dev->msg_buf_remaining = msg->len;
+	i2c_dev->msg_err = 0;
+	INIT_COMPLETION(i2c_dev->completion);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	val |= SUNXI_I2C_CNTR_MASTER_START;
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG, val);
+
+	time_left = wait_for_completion_timeout(&i2c_dev->completion,
+						i2c_dev->adapter.timeout);
+	if (!time_left) {
+		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	if (likely(i2c_dev->msg_err == SUNXI_I2C_DONE))
+		return 0;
+
+	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
+
+	return -EIO;
+}
+
+static int sunxi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			  int num)
+{
+	struct sunxi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	int i, ret;
+
+	for (i = 0; i < num; i++) {
+		ret = sunxi_i2c_xfer_msg(i2c_dev, &msgs[i]);
+		if (ret)
+			return ret;
+	}
+
+	return i;
+}
+
+static u32 sunxi_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm sunxi_i2c_algo = {
+	.master_xfer	= sunxi_i2c_xfer,
+	.functionality	= sunxi_i2c_func,
+};
+
+static int sunxi_i2c_probe(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev;
+	struct device_node *np;
+	u32 freq, div_m, div_n;
+	int ret;
+
+	np = pdev->dev.of_node;
+	if (!np)
+		return -EINVAL;
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, i2c_dev);
+	i2c_dev->dev = &pdev->dev;
+
+	init_completion(&i2c_dev->completion);
+
+	i2c_dev->membase = of_iomap(np, 0);
+	if (!i2c_dev->membase)
+		return -EADDRNOTAVAIL;
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_SRST_REG, SUNXI_I2C_SRST_RESET);
+
+	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(i2c_dev->clk)) {
+		ret = PTR_ERR(i2c_dev->clk);
+		goto out_iounmap;
+	}
+	clk_prepare_enable(i2c_dev->clk);
+
+	ret = of_property_read_u32(np, "clock-frequency", &freq);
+	if (ret < 0) {
+		dev_warn(&pdev->dev, "Could not read clock-frequency property\n");
+		freq = 100000;
+	}
+
+	/*
+	 * Set the clock dividers. we don't need to be super smart
+	 * here, the datasheet defines the value of the factors for
+	 * the two supported frequencies, and only the M factor
+	 * changes between 100kHz and 400kHz.
+	 *
+	 * The bus clock is generated from the parent clock with two
+	 * different dividers. It is generated as such:
+	 *     f0 = fclk / (2 ^ DIV_N)
+	 *     fbus = f0 / (10 * (DIV_M + 1))
+	 *
+	 * With DIV_N being on 3 bits, and DIV_M on 4 bits.
+	 * So DIV_N < 8, and DIV_M < 16.
+	 *
+	 * However, we can generate both the supported frequencies
+	 * with f0 = 12MHz, and only change M to get back on our
+	 * feet.
+	 */
+	div_n = ilog2(clk_get_rate(i2c_dev->clk) / 12000000);
+	if (freq == 100000)
+		div_m = 11;
+	else if (freq == 400000)
+		div_m = 2;
+	else {
+		dev_err(&pdev->dev, "Unsupported bus frequency\n");
+		ret = -EINVAL;
+		goto out_clk_dis;
+	}
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CCR_REG,
+			SUNXI_I2C_CCR_DIV_N(div_n) | SUNXI_I2C_CCR_DIV_M(div_m));
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "No IRQ resource\n");
+		ret = -ENODEV;
+		goto out_clk_dis;
+	}
+
+	ret = devm_request_irq(&pdev->dev, i2c_dev->irq, sunxi_i2c_handler,
+			       IRQF_SHARED, dev_name(&pdev->dev), i2c_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not request IRQ\n");
+		goto out_clk_dis;
+	}
+
+	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
+
+	i2c_dev->adapter.owner = THIS_MODULE;
+	strlcpy(i2c_dev->adapter.name, "sunxi I2C adapter",
+		sizeof(i2c_dev->adapter.name));
+	i2c_dev->adapter.algo = &sunxi_i2c_algo;
+	i2c_dev->adapter.dev.parent = &pdev->dev;
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			SUNXI_I2C_CNTR_BUS_ENABLE | SUNXI_I2C_CNTR_INT_ENABLE);
+
+	ret = i2c_add_adapter(&i2c_dev->adapter);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register i2c adapter\n");
+		goto out_clk_dis;
+	}
+
+	return 0;
+
+out_clk_dis:
+	clk_disable_unprepare(i2c_dev->clk);
+out_iounmap:
+	iounmap(i2c_dev->membase);
+	return ret;
+}
+
+
+static int sunxi_i2c_remove(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+	clk_disable_unprepare(i2c_dev->clk);
+	iounmap(i2c_dev->membase);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_i2c_of_match[] = {
+	{ .compatible = "allwinner,sun4i-i2c" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sunxi_i2c_of_match);
+
+static struct platform_driver sunxi_i2c_driver = {
+	.probe		= sunxi_i2c_probe,
+	.remove		= sunxi_i2c_remove,
+	.driver		= {
+		.name	= "i2c-sunxi",
+		.owner	= THIS_MODULE,
+		.of_match_table = sunxi_i2c_of_match,
+	},
+};
+module_platform_driver(sunxi_i2c_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com");
+MODULE_DESCRIPTION("Allwinner A1X I2C bus adapter");
+MODULE_LICENSE("GPL");
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Thu May  2 06:45:57 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu,  2 May 2013 12:45:57 +0200
Subject: [PATCH 5/5] ARM: sun5i: olinuxino: Enable the i2c controllers
In-Reply-To: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367491557-6027-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367491557-6027-6-git-send-email-maxime.ripard@free-electrons.com>

The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner
A13. Enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca5506..80497e3 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
 			pinctrl-0 = <&uart1_pins_b>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.1.2



From Ian.Campbell at citrix.com  Thu May  2 06:48:28 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 2 May 2013 11:48:28 +0100
Subject: [Xen-devel] [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305021134160.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367482862.21869.28.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305021134160.5398@kaball.uk.xensource.com>
Message-ID: <1367491708.21869.77.camel@zakaz.uk.xensource.com>

On Thu, 2013-05-02 at 11:38 +0100, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Ian Campbell wrote:
> > On Wed, 2013-05-01 at 20:27 +0100, Stefano Stabellini wrote:
> > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > > index d30042e..8f040a0 100644
> > > --- a/arch/arm/xen/enlighten.c
> > > +++ b/arch/arm/xen/enlighten.c
> > > @@ -14,6 +14,7 @@
> > >  #include <xen/xen-ops.h>
> > >  #include <asm/xen/hypervisor.h>
> > >  #include <asm/xen/hypercall.h>
> > > +#include <asm/arch_timer.h>
> > >  #include <asm/system_misc.h>
> > >  #include <linux/interrupt.h>
> > >  #include <linux/irqreturn.h>
> > > @@ -172,6 +173,8 @@ static int __init xen_secondary_init(unsigned int cpu)
> > >  		   later ones fail to. */
> > >  		per_cpu(xen_vcpu, cpu) = vcpup;
> > >  	}
> > > +
> > > +	xen_setup_runstate_info(cpu);
> > 
> > Is this called for the boot processor too?
> 
> Yep.
> 
> > (do you have a linux-next branch where I can easily find the baseline
> > for this series?)
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_1

Is that your Xen tree, I was after the Linux one...

> It's based on my 3.9-rc3-smp-6 branch currently in linux-next (that is
> based on 3.9-rc3).
> However lost_ticks_1 is not in linux-next yet.

Which branch is in Linux next? It doesn't seem to be your linux-next
(last commit 2011).

Ian.



From lee.jones at linaro.org  Thu May  2 06:49:42 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:42 +0100
Subject: [PATCH 0/8] crypto: Fix clocks and DMA configuration
Message-ID: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>

This patch-set ensures any clocks that are obtained by the ux500
crypto drivers are prepared for use. We also request DMA channels and
configure them in the correct way using the new dmaengine API.

 arch/arm/mach-ux500/board-mop500.c    |   14 ++------------
 drivers/crypto/ux500/cryp/cryp.h      |    7 ++++++-
 drivers/crypto/ux500/cryp/cryp_core.c |   31 ++++++++++++++++++++++++++++++-
 drivers/crypto/ux500/hash/hash_alg.h  |    5 ++++-
 drivers/crypto/ux500/hash/hash_core.c |   24 ++++++++++++++++++++++--
 5 files changed, 64 insertions(+), 17 deletions(-)



From lee.jones at linaro.org  Thu May  2 06:49:43 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:43 +0100
Subject: [PATCH 1/8] crypto: ux500/hash - Prepare clock before enabling it
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-2-git-send-email-lee.jones@linaro.org>

If we fail to prepare the ux500-hash clock before enabling it the
platform will fail to boot. Here we insure this happens.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: Ulf Hansson <ulf.hansson at linaro.org>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_core.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 632c333..1e8b2f3 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1727,11 +1727,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_regulator;
 	}
 
+	ret = clk_prepare(device_data->clk);
+	if (ret) {
+		dev_err(dev, "[%s] clk_prepare() failed!", __func__);
+		goto out_clk;
+	}
+
 	/* Enable device power (and clock) */
 	ret = hash_enable_power(device_data, false);
 	if (ret) {
 		dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
-		goto out_clk;
+		goto out_clk_unprepare;
 	}
 
 	ret = hash_check_hw(device_data);
@@ -1763,6 +1769,9 @@ static int ux500_hash_probe(struct platform_device *pdev)
 out_power:
 	hash_disable_power(device_data, false);
 
+out_clk_unprepare:
+	clk_unprepare(device_data->clk);
+
 out_clk:
 	clk_put(device_data->clk);
 
@@ -1827,6 +1836,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
 		dev_err(dev, "[%s]: hash_disable_power() failed",
 			__func__);
 
+	clk_unprepare(device_data->clk);
 	clk_put(device_data->clk);
 	regulator_put(device_data->regulator);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:44 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:44 +0100
Subject: [PATCH 2/8] crypto: ux500/hash - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-3-git-send-email-lee.jones@linaro.org>

The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_alg.h  |    5 ++++-
 drivers/crypto/ux500/hash/hash_core.c |   10 ++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index cd9351c..be6eb54 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -11,6 +11,7 @@
 #include <linux/bitops.h>
 
 #define HASH_BLOCK_SIZE			64
+#define HASH_DMA_FIFO			4
 #define HASH_DMA_ALIGN_SIZE		4
 #define HASH_DMA_PERFORMANCE_MIN_SIZE	1024
 #define HASH_BYTES_PER_WORD		4
@@ -347,7 +348,8 @@ struct hash_req_ctx {
 
 /**
  * struct hash_device_data - structure for a hash device.
- * @base:		Pointer to the hardware base address.
+ * @base:		Pointer to virtual base address of the hash device.
+ * @phybase:		Pointer to physical memory location of the hash device.
  * @list_node:		For inclusion in klist.
  * @dev:		Pointer to the device dev structure.
  * @ctx_lock:		Spinlock for current_ctx.
@@ -361,6 +363,7 @@ struct hash_req_ctx {
  */
 struct hash_device_data {
 	struct hash_register __iomem	*base;
+	phys_addr_t             phybase;
 	struct klist_node	list_node;
 	struct device		*dev;
 	struct spinlock		ctx_lock;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 1e8b2f3..5d8a7f3 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -123,6 +123,13 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				struct device *dev)
 {
 	struct hash_platform_data *platform_data = dev->platform_data;
+	struct dma_slave_config conf = {
+		.direction = DMA_MEM_TO_DEV,
+		.dst_addr = device_data->phybase + HASH_DMA_FIFO,
+		.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.dst_maxburst = 16,
+        };
+
 	dma_cap_zero(device_data->dma.mask);
 	dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 
@@ -132,6 +139,8 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				platform_data->dma_filter,
 				device_data->dma.cfg_mem2hash);
 
+	dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
+
 	init_completion(&device_data->dma.complete);
 }
 
@@ -1700,6 +1709,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_kfree;
 	}
 
+	device_data->phybase = res->start;
 	device_data->base = ioremap(res->start, resource_size(res));
 	if (!device_data->base) {
 		dev_err(dev, "[%s] ioremap() failed!",
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:45 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:45 +0100
Subject: [PATCH 3/8] ARM: ux500: Stop passing Hash DMA channel config
 information though pdata
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-4-git-send-email-lee.jones@linaro.org>

DMA channel configuration information should be setup in the driver.
The Ux500 Hash driver now does this, so there's no need to send it
though here too.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 883dc66..cb7ae23 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -473,11 +473,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
 		.dir = STEDMA40_MEM_TO_PERIPH,
 		.dev_type = DB8500_DMA_DEV50_HAC1_TX,
-		.src_info.data_width = STEDMA40_WORD_WIDTH,
-		.dst_info.data_width = STEDMA40_WORD_WIDTH,
 		.mode = STEDMA40_MODE_LOGICAL,
-		.src_info.psize = STEDMA40_PSIZE_LOG_16,
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16,
 };
 
 static struct hash_platform_data u8500_hash1_platform_data = {
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:46 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:46 +0100
Subject: [PATCH 4/8] crypto: ux500/cryp - Prepare clock before enabling it
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-5-git-send-email-lee.jones@linaro.org>

If we fail to prepare the ux500-cryp clock before enabling it the
platform will fail to boot. Here we insure this happens.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: Ulf Hansson <ulf.hansson at linaro.org>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 22c9063..bf78d60 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1459,11 +1459,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_regulator;
 	}
 
+	ret = clk_prepare(device_data->clk);
+	if (ret) {
+		dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
+		goto out_clk;
+	}
+
 	/* Enable device power (and clock) */
 	ret = cryp_enable_power(device_data->dev, device_data, false);
 	if (ret) {
 		dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
-		goto out_clk;
+		goto out_clk_unprepare;
 	}
 
 	cryp_error = cryp_check(device_data);
@@ -1524,6 +1530,9 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 out_power:
 	cryp_disable_power(device_data->dev, device_data, false);
 
+out_clk_unprepare:
+	clk_unprepare(device_data->clk);
+
 out_clk:
 	clk_put(device_data->clk);
 
@@ -1594,6 +1603,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
 		dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
 			__func__);
 
+	clk_unprepare(device_data->clk);
 	clk_put(device_data->clk);
 	regulator_put(device_data->pwr_regulator);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:49 +0100
Subject: [PATCH 7/8] crypto: ux500/[cryp|hash] - Show successful start-up in
 the bootlog
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-8-git-send-email-lee.jones@linaro.org>

The Cryp driver is currently silent and the Hash driver prints the
name of its probe function unnecessarily. Let's just put a nice
descriptive one-liner there instead.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |    2 ++
 drivers/crypto/ux500/hash/hash_core.c |    2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 4b90493..78d7463 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1542,6 +1542,8 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_power;
 	}
 
+	dev_info(dev, "successfully registered\n");
+
 	return 0;
 
 out_power:
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 5d8a7f3..ac606b6 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1773,7 +1773,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_power;
 	}
 
-	dev_info(dev, "[%s] successfully probed\n", __func__);
+	dev_info(dev, "successfully registered\n");
 	return 0;
 
 out_power:
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:48 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:48 +0100
Subject: [PATCH 6/8] ARM: ux500: Stop passing Cryp DMA channel config
 information though pdata
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-7-git-send-email-lee.jones@linaro.org>

DMA channel configuration information should be setup in the driver.
The Ux500 Cryp driver now does this, so there's no need to send it
though here too.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index cb7ae23..7f756cc 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -453,20 +453,12 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 		.mem_to_engine = {
 				.dir = STEDMA40_MEM_TO_PERIPH,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
-				.src_info.data_width = STEDMA40_WORD_WIDTH,
-				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
-				.src_info.psize = STEDMA40_PSIZE_LOG_4,
-				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
 		},
 		.engine_to_mem = {
 				.dir = STEDMA40_PERIPH_TO_MEM,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
-				.src_info.data_width = STEDMA40_WORD_WIDTH,
-				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
-				.src_info.psize = STEDMA40_PSIZE_LOG_4,
-				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
 		}
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:47 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:47 +0100
Subject: [PATCH 5/8] crypto: ux500/cryp - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-6-git-send-email-lee.jones@linaro.org>

The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp.h      |    7 ++++++-
 drivers/crypto/ux500/cryp/cryp_core.c |   17 +++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp.h b/drivers/crypto/ux500/cryp/cryp.h
index 14cfd05..d1d6606 100644
--- a/drivers/crypto/ux500/cryp/cryp.h
+++ b/drivers/crypto/ux500/cryp/cryp.h
@@ -114,6 +114,9 @@ enum cryp_status_id {
 };
 
 /* Cryp DMA interface */
+#define CRYP_DMA_TX_FIFO	0x08
+#define CRYP_DMA_RX_FIFO	0x10
+
 enum cryp_dma_req_type {
 	CRYP_DMA_DISABLE_BOTH,
 	CRYP_DMA_ENABLE_IN_DATA,
@@ -217,7 +220,8 @@ struct cryp_dma {
 
 /**
  * struct cryp_device_data - structure for a cryp device.
- * @base: Pointer to the hardware base address.
+ * @base: Pointer to virtual base address of the cryp device.
+ * @phybase: Pointer to physical memory location of the cryp device.
  * @dev: Pointer to the devices dev structure.
  * @clk: Pointer to the device's clock control.
  * @pwr_regulator: Pointer to the device's power control.
@@ -232,6 +236,7 @@ struct cryp_dma {
  */
 struct cryp_device_data {
 	struct cryp_register __iomem *base;
+	phys_addr_t phybase;
 	struct device *dev;
 	struct clk *clk;
 	struct regulator *pwr_regulator;
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index bf78d60..4b90493 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -476,6 +476,19 @@ static int cryp_get_device_data(struct cryp_ctx *ctx,
 static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
 				   struct device *dev)
 {
+	struct dma_slave_config mem2cryp = {
+		.direction = DMA_MEM_TO_DEV,
+		.dst_addr = device_data->phybase + CRYP_DMA_TX_FIFO,
+		.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.dst_maxburst = 4,
+        };
+	struct dma_slave_config cryp2mem = {
+		.direction = DMA_DEV_TO_MEM,
+		.src_addr = device_data->phybase + CRYP_DMA_RX_FIFO,
+		.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.src_maxburst = 4,
+        };
+
 	dma_cap_zero(device_data->dma.mask);
 	dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 
@@ -491,6 +504,9 @@ static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
 				    stedma40_filter,
 				    device_data->dma.cfg_cryp2mem);
 
+	dmaengine_slave_config(device_data->dma.chan_mem2cryp, &mem2cryp);
+	dmaengine_slave_config(device_data->dma.chan_cryp2mem, &cryp2mem);
+
 	init_completion(&device_data->dma.cryp_dma_complete);
 }
 
@@ -1432,6 +1448,7 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_kfree;
 	}
 
+	device_data->phybase = res->start;
 	device_data->base = ioremap(res->start, resource_size(res));
 	if (!device_data->base) {
 		dev_err(dev, "[%s]: ioremap failed!", __func__);
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:49:50 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 11:49:50 +0100
Subject: [PATCH 8/8] ARM: ux500: Register Cyrp and Hash platform drivers on
 Snowball
In-Reply-To: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367491790-9727-9-git-send-email-lee.jones@linaro.org>

These drivers are now operational and even use the latest common clk
and DMA APIs. There's no reason why we shouldn't start them up now.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 7f756cc..3866fa8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -656,6 +656,8 @@ static void __init snowball_init_machine(void)
 
 	mop500_snowball_ethernet_clock_enable();
 
+	u8500_cryp1_hash1_init(parent);
+
 	/* This board has full regulator constraints */
 	regulator_has_full_constraints();
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 06:52:02 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 May 2013 11:52:02 +0100
Subject: [PATCH 09/10] ARM: ux500: Remove ux500-musb platform registation
 when booting with DT
In-Reply-To: <1366729394-11406-10-git-send-email-lee.jones@linaro.org>
References: <1366729394-11406-1-git-send-email-lee.jones@linaro.org>
 <1366729394-11406-10-git-send-email-lee.jones@linaro.org>
Message-ID: <20130502105202.GJ25256@gmail.com>

On Tue, 23 Apr 2013, Lee Jones wrote:

> Now the ux500-musb driver has been enabled for Device Tree, there is no
> requirement to register it from platform code.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/cpu-db8500.c |    2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
> index 5a6b9ae..36ef6ed 100644
> --- a/arch/arm/mach-ux500/cpu-db8500.c
> +++ b/arch/arm/mach-ux500/cpu-db8500.c
> @@ -227,8 +227,6 @@ static struct device * __init u8500_of_init_devices(void)
>  {
>  	struct device *parent = db8500_soc_device_init();
>  
> -	db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
> -
>  	return parent;
>  }

Linus, poke.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Thu May  2 06:52:46 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 May 2013 11:52:46 +0100
Subject: [PATCH 10/10] ARM: ux500: Remove empty function
 u8500_of_init_devices()
In-Reply-To: <1366729394-11406-11-git-send-email-lee.jones@linaro.org>
References: <1366729394-11406-1-git-send-email-lee.jones@linaro.org>
 <1366729394-11406-11-git-send-email-lee.jones@linaro.org>
Message-ID: <20130502105246.GK25256@gmail.com>

On Tue, 23 Apr 2013, Lee Jones wrote:

> As promised, now all devices which resided in u8500_of_init_devices()
> have been enabled for Device Tree, we can completely remove it.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/cpu-db8500.c |   14 +-------------
>  1 file changed, 1 insertion(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
> index 36ef6ed..a2c83c2 100644
> --- a/arch/arm/mach-ux500/cpu-db8500.c
> +++ b/arch/arm/mach-ux500/cpu-db8500.c
> @@ -221,15 +221,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
>  }
>  
>  #ifdef CONFIG_MACH_UX500_DT
> -
> -/* TODO: Once all pieces are DT:ed, remove completely. */
> -static struct device * __init u8500_of_init_devices(void)
> -{
> -	struct device *parent = db8500_soc_device_init();
> -
> -	return parent;
> -}
> -
>  static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
>  	/* Requires call-back bindings. */
>  	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
> @@ -288,7 +279,7 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
>  
>  static void __init u8500_init_machine(void)
>  {
> -	struct device *parent = NULL;
> +	struct device *parent = db8500_soc_device_init();
>  
>  	/* Pinmaps must be in place before devices register */
>  	if (of_machine_is_compatible("st-ericsson,mop500"))
> @@ -301,9 +292,6 @@ static void __init u8500_init_machine(void)
>  	else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
>  		/* TODO: Add pinmaps for ccu9540 board. */
>  
> -	/* TODO: Export SoC, USB, cpu-freq and DMA40 */
> -	parent = u8500_of_init_devices();
> -
>  	/* automatically probe child nodes of db8500 device */
>  	of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
>  }

Linus, poke.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From stefano.stabellini at eu.citrix.com  Thu May  2 06:54:16 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 11:54:16 +0100
Subject: [Xen-devel] [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <1367491708.21869.77.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367482862.21869.28.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305021134160.5398@kaball.uk.xensource.com>
 <1367491708.21869.77.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305021153220.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Ian Campbell wrote:
> On Thu, 2013-05-02 at 11:38 +0100, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Ian Campbell wrote:
> > > On Wed, 2013-05-01 at 20:27 +0100, Stefano Stabellini wrote:
> > > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > > > index d30042e..8f040a0 100644
> > > > --- a/arch/arm/xen/enlighten.c
> > > > +++ b/arch/arm/xen/enlighten.c
> > > > @@ -14,6 +14,7 @@
> > > >  #include <xen/xen-ops.h>
> > > >  #include <asm/xen/hypervisor.h>
> > > >  #include <asm/xen/hypercall.h>
> > > > +#include <asm/arch_timer.h>
> > > >  #include <asm/system_misc.h>
> > > >  #include <linux/interrupt.h>
> > > >  #include <linux/irqreturn.h>
> > > > @@ -172,6 +173,8 @@ static int __init xen_secondary_init(unsigned int cpu)
> > > >  		   later ones fail to. */
> > > >  		per_cpu(xen_vcpu, cpu) = vcpup;
> > > >  	}
> > > > +
> > > > +	xen_setup_runstate_info(cpu);
> > > 
> > > Is this called for the boot processor too?
> > 
> > Yep.
> > 
> > > (do you have a linux-next branch where I can easily find the baseline
> > > for this series?)
> > 
> > git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_1
> 
> Is that your Xen tree, I was after the Linux one...

nope, that's my Linux tree disguised as a Xen tree to confuse the
maintainers ;-)

> > It's based on my 3.9-rc3-smp-6 branch currently in linux-next (that is
> > based on 3.9-rc3).
> > However lost_ticks_1 is not in linux-next yet.
> 
> Which branch is in Linux next? It doesn't seem to be your linux-next
> (last commit 2011).

that would be linux-next from
git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git


From lee.jones at linaro.org  Thu May  2 06:54:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 May 2013 11:54:53 +0100
Subject: [PATCH 0/6] dmaengine: Refactor the DMA40 driver - continued
In-Reply-To: <1366976295-11728-1-git-send-email-lee.jones@linaro.org>
References: <1366976295-11728-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20130502105453.GL25256@gmail.com>

On Fri, 26 Apr 2013, Lee Jones wrote:

> This is a continuation of the first "dmaengine: Refactor the DMA40 driver"
> patch-set. It encompasses some recommendations given during the review of
> it's predecessor.
> 
>  arch/arm/mach-ux500/board-mop500-audio.c    |   12 +++++-----
>  arch/arm/mach-ux500/board-mop500-sdi.c      |   16 ++++++-------
>  arch/arm/mach-ux500/board-mop500.c          |   22 ++++++++---------
>  arch/arm/mach-ux500/usb.c                   |    4 ++--
>  drivers/dma/ste_dma40.c                     |   99 +++++++++++++++++++++++++++++++++-------------------------------------------
>  drivers/dma/ste_dma40_ll.c                  |  122 ++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------
>  include/linux/platform_data/dma-ste-dma40.h |   19 ++-------------
>  sound/soc/ux500/ux500_pcm.c                 |   10 ++++----
>  8 files changed, 147 insertions(+), 157 deletions(-)
> 

Linus, poke for this series.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From Ian.Campbell at citrix.com  Thu May  2 07:02:13 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 2 May 2013 12:02:13 +0100
Subject: [Xen-devel] [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305021153220.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367482862.21869.28.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305021134160.5398@kaball.uk.xensource.com>
 <1367491708.21869.77.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305021153220.5398@kaball.uk.xensource.com>
Message-ID: <1367492533.21869.81.camel@zakaz.uk.xensource.com>

On Thu, 2013-05-02 at 11:54 +0100, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Ian Campbell wrote:
> > On Thu, 2013-05-02 at 11:38 +0100, Stefano Stabellini wrote:
> > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > On Wed, 2013-05-01 at 20:27 +0100, Stefano Stabellini wrote:
> > > > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > > > > index d30042e..8f040a0 100644
> > > > > --- a/arch/arm/xen/enlighten.c
> > > > > +++ b/arch/arm/xen/enlighten.c
> > > > > @@ -14,6 +14,7 @@
> > > > >  #include <xen/xen-ops.h>
> > > > >  #include <asm/xen/hypervisor.h>
> > > > >  #include <asm/xen/hypercall.h>
> > > > > +#include <asm/arch_timer.h>
> > > > >  #include <asm/system_misc.h>
> > > > >  #include <linux/interrupt.h>
> > > > >  #include <linux/irqreturn.h>
> > > > > @@ -172,6 +173,8 @@ static int __init xen_secondary_init(unsigned int cpu)
> > > > >  		   later ones fail to. */
> > > > >  		per_cpu(xen_vcpu, cpu) = vcpup;
> > > > >  	}
> > > > > +
> > > > > +	xen_setup_runstate_info(cpu);
> > > > 
> > > > Is this called for the boot processor too?
> > > 
> > > Yep.
> > > 
> > > > (do you have a linux-next branch where I can easily find the baseline
> > > > for this series?)
> > > 
> > > git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_1
> > 
> > Is that your Xen tree, I was after the Linux one...
> 
> nope, that's my Linux tree disguised as a Xen tree to confuse the
> maintainers ;-)

;-)

> > > It's based on my 3.9-rc3-smp-6 branch currently in linux-next (that is
> > > based on 3.9-rc3).
> > > However lost_ticks_1 is not in linux-next yet.
> > 
> > Which branch is in Linux next? It doesn't seem to be your linux-next
> > (last commit 2011).
> 
> that would be linux-next from
> git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git

Ah, I was looking in your xenbits tree -- is that deprecated?

Ian.




From catalin.marinas at arm.com  Thu May  2 07:03:57 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 12:03:57 +0100
Subject: [PATCH v3 16/32] arm64: KVM: hypervisor initialization code
In-Reply-To: <1365437854-30214-17-git-send-email-marc.zyngier@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-17-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130502110356.GA10418@localhost.cambridge.arm.com>

On Mon, Apr 08, 2013 at 05:17:18PM +0100, Marc Zyngier wrote:
> Provide EL2 with page tables and stack, and set the vectors
> to point to the full blown world-switch code.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm64/include/asm/kvm_host.h |  13 +++++
>  arch/arm64/kvm/hyp-init.S         | 112 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 125 insertions(+)
>  create mode 100644 arch/arm64/kvm/hyp-init.S
> 
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index a0279ff..8655de4 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -183,4 +183,17 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
>  int kvm_perf_init(void);
>  int kvm_perf_teardown(void);
>  
> +static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
> +				       unsigned long long pgd_ptr,
> +				       unsigned long hyp_stack_ptr,
> +				       unsigned long vector_ptr)

Why some types are long long other others just long? Is it called from
arch/arm/ code? I would rather use phys_addr_t where relevant and
unsigned long where it means a virtual address.

-- 
Catalin


From stefano.stabellini at eu.citrix.com  Thu May  2 07:04:46 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 12:04:46 +0100
Subject: [Xen-devel] [PATCH 3/3] xen/arm: account for stolen ticks
In-Reply-To: <1367492533.21869.81.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367482862.21869.28.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305021134160.5398@kaball.uk.xensource.com>
 <1367491708.21869.77.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305021153220.5398@kaball.uk.xensource.com>
 <1367492533.21869.81.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305021204050.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Ian Campbell wrote:
> > > > It's based on my 3.9-rc3-smp-6 branch currently in linux-next (that is
> > > > based on 3.9-rc3).
> > > > However lost_ticks_1 is not in linux-next yet.
> > > 
> > > Which branch is in Linux next? It doesn't seem to be your linux-next
> > > (last commit 2011).
> > 
> > that would be linux-next from
> > git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git
> 
> Ah, I was looking in your xenbits tree -- is that deprecated?

I guess it is, now that I have a kernel.org account.
I might as well get rid of it.


From wenyou.yang at atmel.com  Thu May  2 07:23:21 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Thu, 2 May 2013 19:23:21 +0800
Subject: [PATCH] BUG: fix atmel spi doesn' support 16 bits transfers using PIO
Message-ID: <1367493801-3037-1-git-send-email-wenyou.yang@atmel.com>

Hi Mark,

This patch is one of atmel spi add dmaengine support patch series which has some issue when applying:
	spi/spi-atmel: BUG: fix doesn' support 16 bits transfers using PIO

I regenerate it based on your next git tree.

Thanks a lot.

Best Regards
Wenyou Yang

Richard Genoud (1):
  spi/spi-atmel: BUG: fix doesn' support 16 bits transfers using PIO

 drivers/spi/spi-atmel.c |   47 ++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 9 deletions(-)

-- 
1.7.9.5



From wenyou.yang at atmel.com  Thu May  2 07:25:11 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Thu, 2 May 2013 19:25:11 +0800
Subject: [PATCH] spi/spi-atmel: BUG: fix doesn' support 16 bits transfers
 using PIO
In-Reply-To: <1367493801-3037-1-git-send-email-wenyou.yang@atmel.com>
References: <1367493801-3037-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <1367493911-3182-1-git-send-email-wenyou.yang@atmel.com>

From: Richard Genoud <richard.genoud at gmail.com>

Fix using PIO transfer mode only support 8 bits transfer, doesn't support 16 bits.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
Cc: spi-devel-general at lists.sourceforge.net
Cc: linux-kernel at vger.kernel.org
[wenyou.yang at atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
---
 drivers/spi/spi-atmel.c |   47 ++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 787bd2c..d8cb7da 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -526,13 +526,17 @@ static void atmel_spi_next_xfer_pio(struct spi_master *master,
 	}
 
 	if (xfer->tx_buf)
-		spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
+		if (xfer->bits_per_word > 8)
+			spi_writel(as, TDR, *(u16 *)(xfer->tx_buf));
+		else
+			spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
 	else
 		spi_writel(as, TDR, 0);
 
 	dev_dbg(master->dev.parent,
-		"  start pio xfer %p: len %u tx %p rx %p\n",
-		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
+		"  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
+		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
+		xfer->bits_per_word);
 
 	/* Enable relevant interrupts */
 	spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
@@ -950,21 +954,39 @@ atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 {
 	u8		*txp;
 	u8		*rxp;
+	u16		*txp16;
+	u16		*rxp16;
 	unsigned long	xfer_pos = xfer->len - as->current_remaining_bytes;
 
 	if (xfer->rx_buf) {
-		rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
-		*rxp = spi_readl(as, RDR);
+		if (xfer->bits_per_word > 8) {
+			rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
+			*rxp16 = spi_readl(as, RDR);
+		} else {
+			rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
+			*rxp = spi_readl(as, RDR);
+		}
 	} else {
 		spi_readl(as, RDR);
 	}
-
-	as->current_remaining_bytes--;
+	if (xfer->bits_per_word > 8) {
+		as->current_remaining_bytes -= 2;
+		if (as->current_remaining_bytes < 0)
+			as->current_remaining_bytes = 0;
+	} else {
+		as->current_remaining_bytes--;
+	}
 
 	if (as->current_remaining_bytes) {
 		if (xfer->tx_buf) {
-			txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
-			spi_writel(as, TDR, *txp);
+			if (xfer->bits_per_word > 8) {
+				txp16 = (u16 *)(((u8 *)xfer->tx_buf)
+							+ xfer_pos + 2);
+				spi_writel(as, TDR, *txp16);
+			} else {
+				txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
+				spi_writel(as, TDR, *txp);
+			}
 		} else {
 			spi_writel(as, TDR, 0);
 		}
@@ -1378,6 +1400,13 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 			}
 		}
 
+		if (xfer->bits_per_word > 8) {
+			if (xfer->len % 2) {
+				dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n");
+				return -EINVAL;
+			}
+		}
+
 		/* FIXME implement these protocol options!! */
 		if (xfer->speed_hz) {
 			dev_dbg(&spi->dev, "no protocol options yet\n");
-- 
1.7.9.5



From srinidhi.kasagar at stericsson.com  Thu May  2 07:29:24 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Thu, 2 May 2013 16:59:24 +0530
Subject: [PATCH 3/5] ARM: ux500: Stop passing DMA platform data though
 AUXDATA
In-Reply-To: <1367336497-10650-3-git-send-email-lee.jones@linaro.org>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <1367336497-10650-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20130502112923.GA22739@bnru10>

On Tue, Apr 30, 2013 at 17:41:35 +0200, Lee Jones wrote:
> The DMA platform data is now empty due to some recent refactoring,
> so there is no longer a requirement to pass it though.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/cpu-db8500.c |    3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
> index a2c83c2..2b6cbde 100644
> --- a/arch/arm/mach-ux500/cpu-db8500.c
> +++ b/arch/arm/mach-ux500/cpu-db8500.c
> @@ -264,8 +264,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
>  	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
>  		"ux500-msp-i2s.3", &msp3_platform_data),
>  	/* Requires clock name bindings and channel address lookup table. */
> -	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
> -		       "dma40.0", &dma40_plat_data),
> +	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
>  	{},
>  };

Acked-by:srinidhi kasagar <srinidhi.kasagar at stericsson.com>

srinidhi 


From alonid at stratoscale.com  Thu May  2 07:52:29 2013
From: alonid at stratoscale.com (Dan Aloni)
Date: Thu,  2 May 2013 14:52:29 +0300
Subject: [PATCH] Move the EM_AARCH64 definition to uapi/linux/elf-em.txt
Message-ID: <1367495549-6293-1-git-send-email-alonid@stratoscale.com>

Signed-off-by: Dan Aloni <alonid at stratoscale.com>
CC: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/elf.h |    2 --
 include/uapi/linux/elf-em.h  |    1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index fe32c0e..b3da1c1 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -33,8 +33,6 @@ typedef unsigned long elf_greg_t;
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef struct user_fpsimd_state elf_fpregset_t;
 
-#define EM_AARCH64		183
-
 /*
  * AArch64 static relocation types.
  */
diff --git a/include/uapi/linux/elf-em.h b/include/uapi/linux/elf-em.h
index 8e2b7ba..bc946e9 100644
--- a/include/uapi/linux/elf-em.h
+++ b/include/uapi/linux/elf-em.h
@@ -34,6 +34,7 @@
 #define EM_MN10300	89	/* Panasonic/MEI MN10300, AM33 */
 #define EM_BLACKFIN     106     /* ADI Blackfin Processor */
 #define EM_TI_C6000	140	/* TI C6X DSPs */
+#define EM_AARCH64	183	/* ARM 64 bit */
 #define EM_FRV		0x5441	/* Fujitsu FR-V */
 #define EM_AVR32	0x18ad	/* Atmel AVR32 */
 
-- 
1.7.10.4



From alonid at stratoscale.com  Thu May  2 07:56:18 2013
From: alonid at stratoscale.com (Dan Aloni)
Date: Thu,  2 May 2013 14:56:18 +0300
Subject: [PATCH] Move the EM_AARCH64 definition to uapi/linux/elf-em.h
Message-ID: <1367495778-6406-1-git-send-email-alonid@stratoscale.com>

Signed-off-by: Dan Aloni <alonid at stratoscale.com>
CC: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/elf.h |    2 --
 include/uapi/linux/elf-em.h  |    1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

(fixed the commit message)

diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index fe32c0e..b3da1c1 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -33,8 +33,6 @@ typedef unsigned long elf_greg_t;
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef struct user_fpsimd_state elf_fpregset_t;
 
-#define EM_AARCH64		183
-
 /*
  * AArch64 static relocation types.
  */
diff --git a/include/uapi/linux/elf-em.h b/include/uapi/linux/elf-em.h
index 8e2b7ba..bc946e9 100644
--- a/include/uapi/linux/elf-em.h
+++ b/include/uapi/linux/elf-em.h
@@ -34,6 +34,7 @@
 #define EM_MN10300	89	/* Panasonic/MEI MN10300, AM33 */
 #define EM_BLACKFIN     106     /* ADI Blackfin Processor */
 #define EM_TI_C6000	140	/* TI C6X DSPs */
+#define EM_AARCH64	183	/* ARM 64 bit */
 #define EM_FRV		0x5441	/* Fujitsu FR-V */
 #define EM_AVR32	0x18ad	/* Atmel AVR32 */
 
-- 
1.7.10.4



From linus.walleij at linaro.org  Thu May  2 08:34:05 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 2 May 2013 14:34:05 +0200
Subject: [PATCH 0/5] various ab8500 fixes
In-Reply-To: <1366978638-967-1-git-send-email-fabio.baltieri@linaro.org>
References: <1366978638-967-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <CACRpkdYSf8T8anTgU=rxhhJWdELxN22koQ=Y27uuS4WyxZn4DA@mail.gmail.com>

On Fri, Apr 26, 2013 at 2:17 PM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:

> Hi Samuel,
>
> this series contains various fixes I found on the current -next ab8500
> driver(s).

The series:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From emilio at elopez.com.ar  Thu May  2 08:37:46 2013
From: emilio at elopez.com.ar (=?UTF-8?q?Emilio=20L=C3=B3pez?=)
Date: Thu,  2 May 2013 09:37:46 -0300
Subject: [PATCH] ARM: sun4i: cubieboard: Enable the i2c controllers
Message-ID: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>

The Cubieboard makes use of the first two i2c controllers found on the
Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1
is exposed on the board headers. This patch enables them in the device
tree.

Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..0e22a28 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -41,6 +41,18 @@
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.2.2



From holt at sgi.com  Thu May  2 08:49:06 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 2 May 2013 07:49:06 -0500
Subject: [PATCH -v7 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <20130502073020.GC26361@gmail.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <1367428011-17123-11-git-send-email-holt@sgi.com>
 <20130502073020.GC26361@gmail.com>
Message-ID: <20130502124906.GW3658@sgi.com>

On Thu, May 02, 2013 at 09:30:20AM +0200, Ingo Molnar wrote:
> 
> * Robin Holt <holt at sgi.com> wrote:
> 
> >  #ifndef __ASSEMBLY__
> >  
> >  #include <linux/types.h>
> > +#include <linux/reboot.h>
> >  
> >  void iop3xx_map_io(void);
> >  void iop_init_cp6_handler(void);
> >  void iop_init_time(unsigned long tickrate);
> > -void iop3xx_restart(char, const char *);
> > +void iop3xx_restart(enum reboot_mode, const char *);
> 
> IMO the introduction of the enum is making things cleaner here all around.
> 
> As long as it's an equivalent transformation for ARM with no reduction in 
> functionality (i.e. please fix any bugs Russell found), this all looks 
> like a nice series.
> 
> Is there no parameter namespace clash between reboot modifier strings on 
> various architectures? I.e. 's' meaning something on x86 and meaning a 
> different thing on ARM or some other architecture.

There is.  I used an #ifdef in kernel/reboot.c.  Also w[arm] | c[old]
on x86 becomes s[oft] | h[ard] | g[pio] on arm/unicore32. (Well, I just
added gpio that to the patch set after noticing I missed it earlier).

Robin


From catalin.marinas at arm.com  Thu May  2 09:27:56 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 14:27:56 +0100
Subject: [PATCH] Move the EM_AARCH64 definition to uapi/linux/elf-em.h
In-Reply-To: <1367495778-6406-1-git-send-email-alonid@stratoscale.com>
References: <1367495778-6406-1-git-send-email-alonid@stratoscale.com>
Message-ID: <20130502132756.GD20730@arm.com>

On Thu, May 02, 2013 at 12:56:18PM +0100, Dan Aloni wrote:
> Signed-off-by: Dan Aloni <alonid at stratoscale.com>
> CC: Catalin Marinas <catalin.marinas at arm.com>
> ---
>  arch/arm64/include/asm/elf.h |    2 --
>  include/uapi/linux/elf-em.h  |    1 +
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> (fixed the commit message)
> 
> diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
> index fe32c0e..b3da1c1 100644
> --- a/arch/arm64/include/asm/elf.h
> +++ b/arch/arm64/include/asm/elf.h
> @@ -33,8 +33,6 @@ typedef unsigned long elf_greg_t;
>  typedef elf_greg_t elf_gregset_t[ELF_NGREG];
>  typedef struct user_fpsimd_state elf_fpregset_t;
>  
> -#define EM_AARCH64		183
> -
>  /*
>   * AArch64 static relocation types.
>   */
> diff --git a/include/uapi/linux/elf-em.h b/include/uapi/linux/elf-em.h
> index 8e2b7ba..bc946e9 100644
> --- a/include/uapi/linux/elf-em.h
> +++ b/include/uapi/linux/elf-em.h
> @@ -34,6 +34,7 @@
>  #define EM_MN10300	89	/* Panasonic/MEI MN10300, AM33 */
>  #define EM_BLACKFIN     106     /* ADI Blackfin Processor */
>  #define EM_TI_C6000	140	/* TI C6X DSPs */
> +#define EM_AARCH64	183	/* ARM 64 bit */
>  #define EM_FRV		0x5441	/* Fujitsu FR-V */
>  #define EM_AVR32	0x18ad	/* Atmel AVR32 */

Will you do the same for arch/arm? There is EM_ARM defined under
arch/arm and arch/arm64 (elf.h).

-- 
Catalin


From marc.zyngier at arm.com  Thu May  2 09:28:42 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu, 02 May 2013 14:28:42 +0100
Subject: [PATCH v3 16/32] arm64: KVM: hypervisor initialization code
In-Reply-To: <20130502110356.GA10418@localhost.cambridge.arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-17-git-send-email-marc.zyngier@arm.com>
 <20130502110356.GA10418@localhost.cambridge.arm.com>
Message-ID: <51826A0A.5040403@arm.com>

On 02/05/13 12:03, Catalin Marinas wrote:
> On Mon, Apr 08, 2013 at 05:17:18PM +0100, Marc Zyngier wrote:
>> Provide EL2 with page tables and stack, and set the vectors
>> to point to the full blown world-switch code.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
>> ---
>>  arch/arm64/include/asm/kvm_host.h |  13 +++++
>>  arch/arm64/kvm/hyp-init.S         | 112 ++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 125 insertions(+)
>>  create mode 100644 arch/arm64/kvm/hyp-init.S
>>
>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
>> index a0279ff..8655de4 100644
>> --- a/arch/arm64/include/asm/kvm_host.h
>> +++ b/arch/arm64/include/asm/kvm_host.h
>> @@ -183,4 +183,17 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
>>  int kvm_perf_init(void);
>>  int kvm_perf_teardown(void);
>>  
>> +static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
>> +				       unsigned long long pgd_ptr,
>> +				       unsigned long hyp_stack_ptr,
>> +				       unsigned long vector_ptr)
> 
> Why some types are long long other others just long? Is it called from
> arch/arm/ code? I would rather use phys_addr_t where relevant and
> unsigned long where it means a virtual address.

Indeed. This is my fault for not pushing the idmap rework far enough.

kvm_mmu_get_[boot_]httbr() already return a phys_addr_t, and that should
be propagated to __cpu_init_hyp_mode().

I'll cook a patch for 32bit, and update the 64bit code.

Thanks for noticing this.

	M.
-- 
Jazz is not dead. It just smells funny...



From linus.walleij at stericsson.com  Thu May  2 09:32:23 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 15:32:23 +0200
Subject: [PATCH 03/23 v2] ARM: u300: device tree support for the timer
Message-ID: <1367501543-30669-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds device tree support for the U300 timer, by making
the memory base offset and IRQ dynamically assigned, then
optionally looking them up from the device tree.

Since the timer needs to be registered before any platform
devices are created, we will go into the device tree and look
up the "/timer at c0014000" node and read our base address and
IRQ from there.

Cc: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Use CLOCKSOURCE_OF_DECLARE as suggested by Rob Herring, select
  this for the machine so we do not get compile warnings.
---
 .../bindings/timer/stericsson-u300-apptimer.txt    |  18 ++++
 arch/arm/Kconfig                                   |   1 +
 arch/arm/mach-u300/timer.c                         | 109 ++++++++++++++-------
 arch/arm/mach-u300/timer.h                         |   1 +
 4 files changed, 91 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt

diff --git a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
new file mode 100644
index 0000000..9499bc8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
@@ -0,0 +1,18 @@
+ST-Ericsson U300 apptimer
+
+Required properties:
+
+- compatible : should be "stericsson,u300-apptimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupts; one for each subtimer. These
+  are, in order: OS (operating system), DD (device driver) both
+  adopted for EPOC/Symbian with two specific IRQs for these tasks,
+  then GP1 and GP2, which are general-purpose timers.
+
+Example:
+
+timer {
+	compatible = "stericsson,u300-apptimer";
+	reg = <0xc0014000 0x1000>;
+	interrupts = <24 25 26 27>;
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bbddefe..848f919 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -895,6 +895,7 @@ config ARCH_U300
 	select ARM_VIC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
+	select CLKSRC_OF
 	select COMMON_CLK
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index c3d3802..df1e3b5 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -19,6 +19,8 @@
 #include <linux/err.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -190,6 +192,8 @@
 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 
+static void __iomem *u300_timer_base;
+
 /*
  * The u300_set_mode() function is always called first, if we
  * have oneshot timer active, the oneshot scheduling function
@@ -202,28 +206,28 @@ static void u300_set_mode(enum clock_event_mode mode,
 	case CLOCK_EVT_MODE_PERIODIC:
 		/* Disable interrupts on GPT1 */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Disable GP1 while we're reprogramming it. */
 		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+		       u300_timer_base + U300_TIMER_APP_DGPT1);
 		/*
 		 * Set the periodic mode to a certain number of ticks per
 		 * jiffy.
 		 */
 		writel(TICKS_PER_JIFFY,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+		       u300_timer_base + U300_TIMER_APP_GPT1TC);
 		/*
 		 * Set continuous mode, so the timer keeps triggering
 		 * interrupts.
 		 */
 		writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+		       u300_timer_base + U300_TIMER_APP_SGPT1M);
 		/* Enable timer interrupts */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Then enable the OS timer again */
 		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+		       u300_timer_base + U300_TIMER_APP_EGPT1);
 		break;
 	case CLOCK_EVT_MODE_ONESHOT:
 		/* Just break; here? */
@@ -234,33 +238,33 @@ static void u300_set_mode(enum clock_event_mode mode,
 		 */
 		/* Disable interrupts on GPT1 */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Disable GP1 while we're reprogramming it. */
 		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+		       u300_timer_base + U300_TIMER_APP_DGPT1);
 		/*
 		 * Expire far in the future, u300_set_next_event() will be
 		 * called soon...
 		 */
-		writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+		writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
 		/* We run one shot per tick here! */
 		writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+		       u300_timer_base + U300_TIMER_APP_SGPT1M);
 		/* Enable interrupts for this timer */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Enable timer */
 		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+		       u300_timer_base + U300_TIMER_APP_EGPT1);
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 		/* Disable interrupts on GP1 */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Disable GP1 */
 		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+		       u300_timer_base + U300_TIMER_APP_DGPT1);
 		break;
 	case CLOCK_EVT_MODE_RESUME:
 		/* Ignore this call */
@@ -282,27 +286,27 @@ static int u300_set_next_event(unsigned long cycles,
 {
 	/* Disable interrupts on GPT1 */
 	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+	       u300_timer_base + U300_TIMER_APP_GPT1IE);
 	/* Disable GP1 while we're reprogramming it. */
 	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+	       u300_timer_base + U300_TIMER_APP_DGPT1);
 	/* Reset the General Purpose timer 1. */
 	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+	       u300_timer_base + U300_TIMER_APP_RGPT1);
 	/* IRQ in n * cycles */
-	writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
 	/*
 	 * We run one shot per tick here! (This is necessary to reconfigure,
 	 * the timer will tilt if you don't!)
 	 */
 	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+	       u300_timer_base + U300_TIMER_APP_SGPT1M);
 	/* Enable timer interrupts */
 	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+	       u300_timer_base + U300_TIMER_APP_GPT1IE);
 	/* Then enable the OS timer again */
 	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+	       u300_timer_base + U300_TIMER_APP_EGPT1);
 	return 0;
 }
 
@@ -321,8 +325,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = &clockevent_u300_1mhz;
 	/* ACK/Clear timer IRQ for the APP GPT1 Timer */
+
 	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+		u300_timer_base + U300_TIMER_APP_GPT1IA);
 	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
@@ -343,12 +348,12 @@ static struct irqaction u300_timer_irq = {
 
 static u32 notrace u300_read_sched_clock(void)
 {
-	return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
 
 static unsigned long u300_read_current_timer(void)
 {
-	return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
 
 static struct delay_timer u300_delay_timer;
@@ -356,11 +361,14 @@ static struct delay_timer u300_delay_timer;
 /*
  * This sets up the system timers, clock source and clock event.
  */
-void __init u300_timer_init(void)
+static void __init u300_timer_setup(void __iomem *base, int irq)
 {
 	struct clk *clk;
 	unsigned long rate;
 
+	u300_timer_base = base;
+	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
+
 	/* Clock the interrupt controller */
 	clk = clk_get_sys("apptimer", NULL);
 	BUG_ON(IS_ERR(clk));
@@ -378,40 +386,40 @@ void __init u300_timer_init(void)
 	 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 	 */
 	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+		u300_timer_base + U300_TIMER_APP_CRC);
 	writel(U300_TIMER_APP_ROST_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+		u300_timer_base + U300_TIMER_APP_ROST);
 	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+		u300_timer_base + U300_TIMER_APP_DOST);
 	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+		u300_timer_base + U300_TIMER_APP_RDDT);
 	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+		u300_timer_base + U300_TIMER_APP_DDDT);
 
 	/* Reset the General Purpose timer 1. */
 	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+		u300_timer_base + U300_TIMER_APP_RGPT1);
 
 	/* Set up the IRQ handler */
-	setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+	setup_irq(irq, &u300_timer_irq);
 
 	/* Reset the General Purpose timer 2 */
 	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+		u300_timer_base + U300_TIMER_APP_RGPT2);
 	/* Set this timer to run around forever */
-	writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
 	/* Set continuous mode so it wraps around */
 	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+	       u300_timer_base + U300_TIMER_APP_SGPT2M);
 	/* Disable timer interrupts */
 	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+		u300_timer_base + U300_TIMER_APP_GPT2IE);
 	/* Then enable the GP2 timer to use as a free running us counter */
 	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+		u300_timer_base + U300_TIMER_APP_EGPT2);
 
 	/* Use general purpose timer 2 as clock source */
-	if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+	if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
 			"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 		pr_err("timer: failed to initialize U300 clock source\n");
 
@@ -424,3 +432,28 @@ void __init u300_timer_init(void)
 	 * used by hrtimers!
 	 */
 }
+
+
+void __init u300_timer_init()
+{
+	u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
+}
+
+#ifdef CONFIG_OF
+
+static void __init u300_timer_init_of(struct device_node *np)
+{
+	void __iomem *base;
+	struct resource irq_res;
+	int irq;
+
+	base = of_iomap(np, 0);
+	/* Get the IRQ for the GP1 timer */
+	irq = of_irq_to_resource(np, 2, &irq_res);
+	u300_timer_setup(base, irq);
+}
+
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+		       u300_timer_init_of);
+
+#endif
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
index d34287b..7766dfa 100644
--- a/arch/arm/mach-u300/timer.h
+++ b/arch/arm/mach-u300/timer.h
@@ -1 +1,2 @@
 extern void u300_timer_init(void);
+
-- 
1.7.11.3



From broonie at kernel.org  Thu May  2 09:41:23 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 2 May 2013 14:41:23 +0100
Subject: [PATCH] spi/spi-atmel: BUG: fix doesn' support 16 bits transfers
 using PIO
In-Reply-To: <1367493911-3182-1-git-send-email-wenyou.yang@atmel.com>
References: <1367493801-3037-1-git-send-email-wenyou.yang@atmel.com>
 <1367493911-3182-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <20130502134123.GA4945@sirena.org.uk>

On Thu, May 02, 2013 at 07:25:11PM +0800, Wenyou Yang wrote:
> From: Richard Genoud <richard.genoud at gmail.com>
> 
> Fix using PIO transfer mode only support 8 bits transfer, doesn't support 16 bits.

Applied, thanks.
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From arnd at arndb.de  Thu May  2 09:43:27 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 02 May 2013 15:43:27 +0200
Subject: [PATCH] ARM: sun4i: cubieboard: Enable the i2c controllers
In-Reply-To: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>
References: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>
Message-ID: <2206623.mnYPZ5KTnx@wuerfel>

On Thursday 02 May 2013 09:37:46 Emilio L?pez wrote:
> The Cubieboard makes use of the first two i2c controllers found on the
> Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1
> is exposed on the board headers. This patch enables them in the device
> tree.
> 
> Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>

Shouldn't you list the attached devices in the same patch?

What is the point of enabling the I2C bus if there are no devices
to be found?

	Arnd


From emilio at elopez.com.ar  Thu May  2 10:03:01 2013
From: emilio at elopez.com.ar (=?ISO-8859-1?Q?Emilio_L=F3pez?=)
Date: Thu, 02 May 2013 11:03:01 -0300
Subject: [PATCH] ARM: sun4i: cubieboard: Enable the i2c controllers
In-Reply-To: <2206623.mnYPZ5KTnx@wuerfel>
References: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>
 <2206623.mnYPZ5KTnx@wuerfel>
Message-ID: <51827215.100@elopez.com.ar>

Hi Arnd,

El 02/05/13 10:43, Arnd Bergmann escribi?:
> On Thursday 02 May 2013 09:37:46 Emilio L?pez wrote:
>> The Cubieboard makes use of the first two i2c controllers found on the
>> Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1
>> is exposed on the board headers. This patch enables them in the device
>> tree.
>>
>> Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
> 
> Shouldn't you list the attached devices in the same patch?
> 
> What is the point of enabling the I2C bus if there are no devices
> to be found?

This is complementary to the series titled "Add I2C support for
Allwinner SoCs" sent by Maxime today. We have no driver for the AXP20
PMIC yet, and the external header is left for the user to connect, so I
haven't added any device. This is still useful though, as it lets you
use I2C from userspace (i2cdetect, i2cdump, etc).

Regards,

Emilio


From marc.zyngier at arm.com  Thu May  2 10:39:00 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu,  2 May 2013 15:39:00 +0100
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page
 tables
In-Reply-To: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>

Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
introduced code that flushes page tables to the point of coherency.
This is overkill (point of unification is enough and already done),
and actually not required if running on a SMP capable platform
(the HW PTW can snoop other cpus' L1).

Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
a no-op for SMP ARMv7.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kvm/mmu.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 4a838db..d79b594 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -234,7 +234,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
 		pte = pte_offset_kernel(pmd, addr);
 		kvm_set_pte(pte, pfn_pte(pfn, prot));
 		get_page(virt_to_page(pte));
-		kvm_flush_dcache_to_poc(pte, sizeof(*pte));
 		pfn++;
 	} while (addr += PAGE_SIZE, addr != end);
 }
@@ -261,7 +260,6 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
 			}
 			pmd_populate_kernel(NULL, pmd, pte);
 			get_page(virt_to_page(pmd));
-			kvm_flush_dcache_to_poc(pmd, sizeof(*pmd));
 		}
 
 		next = pmd_addr_end(addr, end);
@@ -299,7 +297,6 @@ static int __create_hyp_mappings(pgd_t *pgdp,
 			}
 			pud_populate(NULL, pud, pmd);
 			get_page(virt_to_page(pud));
-			kvm_flush_dcache_to_poc(pud, sizeof(*pud));
 		}
 
 		next = pgd_addr_end(addr, end);
-- 
1.8.2.1




From marc.zyngier at arm.com  Thu May  2 10:39:02 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu,  2 May 2013 15:39:02 +0100
Subject: [PATCH v2 5/5] ARM: KVM: use phys_addr_t instead of unsigned long
 long for HYP PGDs
In-Reply-To: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367505542-2231-6-git-send-email-marc.zyngier@arm.com>

HYP PGDs are passed around as phys_addr_t, except just before calling
into the hypervisor init code, where they are cast to a rather weird
unsigned long long.

Just keep them around as phys_addr_t, which is what makes the most
sense.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_host.h | 4 ++--
 arch/arm/kvm/arm.c              | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786..ff49193 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -190,8 +190,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
 		int exception_index);
 
-static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
-				       unsigned long long pgd_ptr,
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+				       phys_addr_t pgd_ptr,
 				       unsigned long hyp_stack_ptr,
 				       unsigned long vector_ptr)
 {
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index fa177df..801ffce 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -797,8 +797,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 static void cpu_init_hyp_mode(void *dummy)
 {
-	unsigned long long boot_pgd_ptr;
-	unsigned long long pgd_ptr;
+	phys_addr_t boot_pgd_ptr;
+	phys_addr_t pgd_ptr;
 	unsigned long hyp_stack_ptr;
 	unsigned long stack_page;
 	unsigned long vector_ptr;
@@ -806,8 +806,8 @@ static void cpu_init_hyp_mode(void *dummy)
 	/* Switch from the HYP stub to our own HYP init vector */
 	__hyp_set_vectors(kvm_get_idmap_vector());
 
-	boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
-	pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+	boot_pgd_ptr = kvm_mmu_get_boot_httbr();
+	pgd_ptr = kvm_mmu_get_httbr();
 	stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
 	hyp_stack_ptr = stack_page + PAGE_SIZE;
 	vector_ptr = (unsigned long)__kvm_hyp_vector;
-- 
1.8.2.1




From marc.zyngier at arm.com  Thu May  2 10:38:59 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu,  2 May 2013 15:38:59 +0100
Subject: [PATCH v2 2/5] ARM: KVM: remove dead prototype for
 __kvm_tlb_flush_vmid
In-Reply-To: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367505542-2231-3-git-send-email-marc.zyngier@arm.com>

__kvm_tlb_flush_vmid has been renamed to __kvm_tlb_flush_vmid_ipa,
and the old prototype should have been removed when the code was
modified.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_asm.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d5032..6ae3d2a 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -72,8 +72,6 @@ extern char __kvm_hyp_vector[];
 extern char __kvm_hyp_code_start[];
 extern char __kvm_hyp_code_end[];
 
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
-
 extern void __kvm_flush_vm_context(void);
 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
 
-- 
1.8.2.1




From marc.zyngier at arm.com  Thu May  2 10:38:57 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu,  2 May 2013 15:38:57 +0100
Subject: [PATCH v2 0/5] ARM: KVM: various mmu related fixes for 3.10
Message-ID: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>

This patch series fixes a number of of KVM/ARM issues that have either
been spotted during the review of the arm64 code, or while reworking
related code.

Only the first patch fixes a potential (if unlikely) problem, the
others are either cosmetic or performance related.

Tested on TC-2.

Marc Zyngier (5):
  ARM: KVM: be more thorough when invalidating TLBs
  ARM: KVM: remove dead prototype for __kvm_tlb_flush_vmid
  ARM: KVM: relax cache maintainance when building page tables
  ARM: KVM: get rid of S2_PGD_SIZE
  ARM: KVM: use phys_addr_t instead of unsigned long long for HYP PGDs

 arch/arm/include/asm/kvm_arm.h  |  1 -
 arch/arm/include/asm/kvm_asm.h  |  2 --
 arch/arm/include/asm/kvm_host.h |  4 ++--
 arch/arm/kvm/arm.c              |  8 +++----
 arch/arm/kvm/interrupts.S       |  2 ++
 arch/arm/kvm/mmu.c              | 48 +++++++++++++++++++++++------------------
 6 files changed, 35 insertions(+), 30 deletions(-)

-- 
1.8.2.1




From marc.zyngier at arm.com  Thu May  2 10:39:01 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu,  2 May 2013 15:39:01 +0100
Subject: [PATCH v2 4/5] ARM: KVM: get rid of S2_PGD_SIZE
In-Reply-To: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367505542-2231-5-git-send-email-marc.zyngier@arm.com>

S2_PGD_SIZE defines the number of pages used by a stage-2 PGD
and is unused, except for a VM_BUG_ON check that missuses the
define.

As the check is very unlikely to ever triggered except in
circumstances where KVM is the least of our worries, just kill
both the define and the VM_BUG_ON check.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_arm.h | 1 -
 arch/arm/kvm/mmu.c             | 3 ---
 2 files changed, 4 deletions(-)

diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 124623e..64e9696 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -135,7 +135,6 @@
 #define KVM_PHYS_MASK	(KVM_PHYS_SIZE - 1ULL)
 #define PTRS_PER_S2_PGD	(1ULL << (KVM_PHYS_SHIFT - 30))
 #define S2_PGD_ORDER	get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
-#define S2_PGD_SIZE	(1 << S2_PGD_ORDER)
 
 /* Virtualization Translation Control Register (VTCR) bits */
 #define VTCR_SH0	(3 << 12)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index d79b594..3c506c7 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -379,9 +379,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
 	if (!pgd)
 		return -ENOMEM;
 
-	/* stage-2 pgd must be aligned to its size */
-	VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
-
 	memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
 	kvm_clean_pgd(pgd);
 	kvm->arch.pgd = pgd;
-- 
1.8.2.1




From catalin.marinas at arm.com  Thu May  2 10:38:29 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 15:38:29 +0100
Subject: [PATCH v3 19/32] arm64: KVM: Plug the VGIC
In-Reply-To: <5177C559.9070806@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-20-git-send-email-marc.zyngier@arm.com>
 <20130423230012.GG20569@gmail.com> <5177C559.9070806@arm.com>
Message-ID: <20130502143828.GE20730@arm.com>

On Wed, Apr 24, 2013 at 12:43:21PM +0100, Marc Zyngier wrote:
> On 24/04/13 00:00, Christoffer Dall wrote:
> > On Mon, Apr 08, 2013 at 05:17:21PM +0100, Marc Zyngier wrote:
> >> Add support for the in-kernel GIC emulation. The include file
> >> is a complete duplicate of the 32bit one - something to fix
> >> at one point.
> > 
> > seems like something that should be fixed sooner as opposed to later...
> > Is it hard?
> 
> Hard? No. Disgusting? Yes.
> 
> You need to find a common location for the files. Something like
> virt/kvm/arm/vgic.h? The x86/ia64 guys already have virt/kvm/ioapic.h as
> a (bad) precedent.

Probably not that bad, we already have include/linux/irqchip/arm-gic.h,
so you could add virt/kvm/arm-vgic.[ch] (or create an arm subdirectory
so there will be a tendency to move a lot more in there).

-- 
Catalin


From marc.zyngier at arm.com  Thu May  2 10:38:58 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu,  2 May 2013 15:38:58 +0100
Subject: [PATCH v2 1/5] ARM: KVM: be more thorough when invalidating TLBs
In-Reply-To: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367505542-2231-2-git-send-email-marc.zyngier@arm.com>

The KVM/ARM MMU code doesn't take care of invalidating TLBs before
freeing a {pte,pmd} table. This could cause problems if the page
is reallocated and then speculated into by another CPU.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kvm/interrupts.S |  2 ++
 arch/arm/kvm/mmu.c        | 42 +++++++++++++++++++++++++++---------------
 2 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index f7793df..9e2d906c 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -37,6 +37,8 @@ __kvm_hyp_code_start:
  *
  * void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
  *
+ * Invalidate TLB for the given IPA, or invalidate all if ipa is zero.
+ *
  * We rely on the hardware to broadcast the TLB invalidation to all CPUs
  * inside the inner-shareable domain (which is the case for all v7
  * implementations).  If we come across a non-IS SMP implementation, we'll
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 9657065..4a838db 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -43,7 +43,14 @@ static phys_addr_t hyp_idmap_vector;
 
 static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
 {
-	kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
+	/*
+	 * This function also gets called when dealing with HYP page
+	 * tables. As HYP doesn't have an associated struct kvm (and
+	 * the HYP page tables are fairly static), we don't do
+	 * anything there.
+	 */
+	if (kvm)
+		kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
 }
 
 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
@@ -78,18 +85,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
 	return p;
 }
 
-static void clear_pud_entry(pud_t *pud)
+static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
 {
 	pmd_t *pmd_table = pmd_offset(pud, 0);
 	pud_clear(pud);
+	kvm_tlb_flush_vmid_ipa(kvm, addr);
 	pmd_free(NULL, pmd_table);
 	put_page(virt_to_page(pud));
 }
 
-static void clear_pmd_entry(pmd_t *pmd)
+static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
 {
 	pte_t *pte_table = pte_offset_kernel(pmd, 0);
 	pmd_clear(pmd);
+	kvm_tlb_flush_vmid_ipa(kvm, addr);
 	pte_free_kernel(NULL, pte_table);
 	put_page(virt_to_page(pmd));
 }
@@ -100,11 +109,12 @@ static bool pmd_empty(pmd_t *pmd)
 	return page_count(pmd_page) == 1;
 }
 
-static void clear_pte_entry(pte_t *pte)
+static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
 {
 	if (pte_present(*pte)) {
 		kvm_set_pte(pte, __pte(0));
 		put_page(virt_to_page(pte));
+		kvm_tlb_flush_vmid_ipa(kvm, addr);
 	}
 }
 
@@ -114,7 +124,8 @@ static bool pte_empty(pte_t *pte)
 	return page_count(pte_page) == 1;
 }
 
-static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
+static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
+			unsigned long long start, u64 size)
 {
 	pgd_t *pgd;
 	pud_t *pud;
@@ -138,15 +149,15 @@ static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
 		}
 
 		pte = pte_offset_kernel(pmd, addr);
-		clear_pte_entry(pte);
+		clear_pte_entry(kvm, pte, addr);
 		range = PAGE_SIZE;
 
 		/* If we emptied the pte, walk back up the ladder */
 		if (pte_empty(pte)) {
-			clear_pmd_entry(pmd);
+			clear_pmd_entry(kvm, pmd, addr);
 			range = PMD_SIZE;
 			if (pmd_empty(pmd)) {
-				clear_pud_entry(pud);
+				clear_pud_entry(kvm, pud, addr);
 				range = PUD_SIZE;
 			}
 		}
@@ -165,14 +176,14 @@ void free_boot_hyp_pgd(void)
 	mutex_lock(&kvm_hyp_pgd_mutex);
 
 	if (boot_hyp_pgd) {
-		unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
-		unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+		unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
+		unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
 		kfree(boot_hyp_pgd);
 		boot_hyp_pgd = NULL;
 	}
 
 	if (hyp_pgd)
-		unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+		unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
 
 	kfree(init_bounce_page);
 	init_bounce_page = NULL;
@@ -200,9 +211,10 @@ void free_hyp_pgds(void)
 
 	if (hyp_pgd) {
 		for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
-			unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+			unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
 		for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
-			unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+			unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+
 		kfree(hyp_pgd);
 		hyp_pgd = NULL;
 	}
@@ -393,7 +405,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
  */
 static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
 {
-	unmap_range(kvm->arch.pgd, start, size);
+	unmap_range(kvm, kvm->arch.pgd, start, size);
 }
 
 /**
@@ -413,6 +425,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm)
 		return;
 
 	unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);
+	kvm_tlb_flush_vmid_ipa(kvm, 0);	/* Invalidate TLB ALL */
 	free_pages((unsigned long)kvm->arch.pgd, S2_PGD_ORDER);
 	kvm->arch.pgd = NULL;
 }
@@ -675,7 +688,6 @@ static void handle_hva_to_gpa(struct kvm *kvm,
 static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
 {
 	unmap_stage2_range(kvm, gpa, PAGE_SIZE);
-	kvm_tlb_flush_vmid_ipa(kvm, gpa);
 }
 
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
-- 
1.8.2.1




From catalin.marinas at arm.com  Thu May  2 11:00:29 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 16:00:29 +0100
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when
 building page tables
In-Reply-To: <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130502150028.GF20730@arm.com>

On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required if running on a SMP capable platform
> (the HW PTW can snoop other cpus' L1).
> 
> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> a no-op for SMP ARMv7.

I think the comment is a bit misleading. You actually don't need
kvm_flush_dcache_to_poc() since you already do this in kvm_set_pte()
etc.

-- 
Catalin


From will.deacon at arm.com  Thu May  2 11:03:56 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 2 May 2013 16:03:56 +0100
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130502150355.GA25022@mudshark.cambridge.arm.com>

On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required if running on a SMP capable platform
> (the HW PTW can snoop other cpus' L1).
> 
> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> a no-op for SMP ARMv7.
> 
> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/kvm/mmu.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 4a838db..d79b594 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -234,7 +234,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
>  		pte = pte_offset_kernel(pmd, addr);
>  		kvm_set_pte(pte, pfn_pte(pfn, prot));
>  		get_page(virt_to_page(pte));
> -		kvm_flush_dcache_to_poc(pte, sizeof(*pte));
>  		pfn++;
>  	} while (addr += PAGE_SIZE, addr != end);

Could you remove the flushing code out of kvm_set_pte, then flush the range
after the loop? Then you get one flush and one barrier for the whole range.

Will


From arnd at arndb.de  Thu May  2 11:06:33 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 17:06:33 +0200
Subject: [PATCH] ARM: sun4i: cubieboard: Enable the i2c controllers
In-Reply-To: <51827215.100@elopez.com.ar>
References: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>
 <2206623.mnYPZ5KTnx@wuerfel> <51827215.100@elopez.com.ar>
Message-ID: <201305021706.33456.arnd@arndb.de>

On Thursday 02 May 2013, Emilio L?pez wrote:
> This is complementary to the series titled "Add I2C support for
> Allwinner SoCs" sent by Maxime today. We have no driver for the AXP20
> PMIC yet, and the external header is left for the user to connect, so I
> haven't added any device. This is still useful though, as it lets you
> use I2C from userspace (i2cdetect, i2cdump, etc).

Right, that makes sense. Thanks,

	Arnd


From catalin.marinas at arm.com  Thu May  2 11:13:02 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 16:13:02 +0100
Subject: [PATCH v2 1/5] ARM: KVM: be more thorough when invalidating TLBs
In-Reply-To: <1367505542-2231-2-git-send-email-marc.zyngier@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130502151302.GG20730@arm.com>

On Thu, May 02, 2013 at 03:38:58PM +0100, Marc Zyngier wrote:
> diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
> index f7793df..9e2d906c 100644
> --- a/arch/arm/kvm/interrupts.S
> +++ b/arch/arm/kvm/interrupts.S
...
> -static void clear_pte_entry(pte_t *pte)
> +static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
>  {
>  	if (pte_present(*pte)) {
>  		kvm_set_pte(pte, __pte(0));
>  		put_page(virt_to_page(pte));
> +		kvm_tlb_flush_vmid_ipa(kvm, addr);
>  	}
>  }
...
>  static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
>  {
> -	unmap_range(kvm->arch.pgd, start, size);
> +	unmap_range(kvm, kvm->arch.pgd, start, size);
>  }
>  
>  /**
> @@ -413,6 +425,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm)
>  		return;
>  
>  	unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);
> +	kvm_tlb_flush_vmid_ipa(kvm, 0);	/* Invalidate TLB ALL */

Do you still need this here if you invalidated each individual pte in
clear_pte_entry()? I think you can remove it from clear_pte_entry() and
just leave it here (more efficient probably) since you wouldn't free the
actual pages pointed at by the pte before unmapping.

>  	free_pages((unsigned long)kvm->arch.pgd, S2_PGD_ORDER);
>  	kvm->arch.pgd = NULL;
>  }
> @@ -675,7 +688,6 @@ static void handle_hva_to_gpa(struct kvm *kvm,
>  static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
>  {
>  	unmap_stage2_range(kvm, gpa, PAGE_SIZE);
> -	kvm_tlb_flush_vmid_ipa(kvm, gpa);

Here you removed it relying on clear_pte_entry(), I think you could keep
it (see above).

-- 
Catalin


From cdall at cs.columbia.edu  Thu May  2 11:15:05 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Thu, 2 May 2013 08:15:05 -0700
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <20130502150355.GA25022@mudshark.cambridge.arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
 <20130502150355.GA25022@mudshark.cambridge.arm.com>
Message-ID: <CAEDV+gJwYpHzehWZci2bmgYedJoBxMOGZFhjGeGRQ_cT8TKkyw@mail.gmail.com>

On Thu, May 2, 2013 at 8:03 AM, Will Deacon <will.deacon at arm.com> wrote:
> On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
>> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
>> introduced code that flushes page tables to the point of coherency.
>> This is overkill (point of unification is enough and already done),
>> and actually not required if running on a SMP capable platform
>> (the HW PTW can snoop other cpus' L1).
>>
>> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
>> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
>> a no-op for SMP ARMv7.
>>
>> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
>> Cc: Will Deacon <will.deacon at arm.com>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
>> ---
>>  arch/arm/kvm/mmu.c | 3 ---
>>  1 file changed, 3 deletions(-)
>>
>> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
>> index 4a838db..d79b594 100644
>> --- a/arch/arm/kvm/mmu.c
>> +++ b/arch/arm/kvm/mmu.c
>> @@ -234,7 +234,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
>>               pte = pte_offset_kernel(pmd, addr);
>>               kvm_set_pte(pte, pfn_pte(pfn, prot));
>>               get_page(virt_to_page(pte));
>> -             kvm_flush_dcache_to_poc(pte, sizeof(*pte));
>>               pfn++;
>>       } while (addr += PAGE_SIZE, addr != end);
>
> Could you remove the flushing code out of kvm_set_pte, then flush the range
> after the loop? Then you get one flush and one barrier for the whole range.
>
that would be different from how it's done in the rest of the kernel
where you're expecting set_pte to do the necessary flushing for you,
no?

instead, if this optimization is worth it, the code could just use
pte_val(pte) = XX;

-Christoffer


From arnd at arndb.de  Thu May  2 11:16:05 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:05 +0200
Subject: [PATCH, RFC 01/22] can: move CONFIG_HAVE_CAN_FLEXCAN out of CAN_DEV
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-2-git-send-email-arnd@arndb.de>

CONFIG_HAVE_CAN_FLEXCAN is a silect symbol that is meant to be selected
by platforms that support this driver, but that is not possible without
also selecting CAN_DEV, unless we move it out of the "if CAN_DEV"
section of the Kconfig file.

warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 &&
 IMX_HAVE_PLATFORM_FLEXCAN && SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
 which has unmet direct dependencies (NET && CAN && CAN_DEV)

Cc: Oliver Hartkopp <socketcan at hartkopp.net>
Cc: linux-can at vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/net/can/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index e456b70..3941a7d 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -29,6 +29,9 @@ config CAN_SLCAN
 	  can be changed by the 'maxdev=xx' module option. This driver can
 	  also be built as a module. If so, the module will be called slcan.
 
+config HAVE_CAN_FLEXCAN
+	bool
+
 config CAN_DEV
 	tristate "Platform CAN drivers with Netlink support"
 	default y
@@ -102,9 +105,6 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config HAVE_CAN_FLEXCAN
-	bool
-
 config CAN_FLEXCAN
 	tristate "Support for Freescale FLEXCAN based chips"
 	depends on HAVE_CAN_FLEXCAN
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:07 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:07 +0200
Subject: [PATCH, RFC 03/22] cpuidle: calxeda: select ARM_CPU_SUSPEND
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-4-git-send-email-arnd@arndb.de>

Like other ARM specific drivers, this one requires ARM_CPU_SUSPEND,
as shown by this linker error:

drivers/built-in.o: In function `calxeda_pwrdown_idle':
drivers/cpuidle/cpuidle-calxeda.c:84: undefined reference to `cpu_suspend'
drivers/cpuidle/cpuidle-calxeda.c:86: undefined reference to `cpu_resume'

Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: linux-pm at vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/cpuidle/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index c4cc27e..e21cdfa 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -36,6 +36,7 @@ if CPU_IDLE
 config CPU_IDLE_CALXEDA
 	bool "CPU Idle Driver for Calxeda processors"
 	depends on ARCH_HIGHBANK
+	select ARM_CPU_SUSPEND
 	help
 	  Select this to enable cpuidle on Calxeda processors.
 
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:11 +0200
Subject: [PATCH, RFC 07/22] drm/tilcd: select BACKLIGHT_LCD_SUPPORT
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-8-git-send-email-arnd@arndb.de>

The dependecies for BACKLIGHT_CLASS_DEVICE are defined a bit
strange, but it seems one has to always select both BACKLIGHT_CLASS_DEVICE
and BACKLIGHT_LCD_SUPPORT to avoid this error:

drivers/gpu/drm/tilcdc/tilcdc_panel.c:396:
 undefined reference to `of_find_backlight_by_node'

Cc: Rob Clark <robdclark at gmail.com>
Cc: dri-devel at lists.freedesktop.org
Cc: Dave Airlie <airlied at redhat.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/gpu/drm/tilcdc/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index e461e99..7a4d101 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -6,6 +6,7 @@ config DRM_TILCDC
 	select DRM_GEM_CMA_HELPER
 	select VIDEOMODE_HELPERS
 	select BACKLIGHT_CLASS_DEVICE
+	select BACKLIGHT_LCD_SUPPORT
 	help
 	  Choose this option if you have an TI SoC with LCDC display
 	  controller, for example AM33xx in beagle-bone, DA8xx, or
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:06 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:06 +0200
Subject: [PATCH, RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-3-git-send-email-arnd@arndb.de>

The big.LITTLE cpufreq driver uses the CPU topology API, which
needs to be reflected in Kconfig to prevent broken configurations.

warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM && ARM_CPU_TOPOLOGY)

Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Viresh Kumar <viresh.kumar at linaro.org>
Cc: cpufreq at vger.kernel.org
Cc: linux-pm at vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/cpufreq/Kconfig.arm | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index f3af18b..3fd6bdf 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -10,6 +10,7 @@ config ARM_DT_BL_CPUFREQ
 	tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
 	select ARM_BIG_LITTLE_CPUFREQ
 	depends on OF && HAVE_CLK
+	depends on ARM_CPU_TOPOLOGY
 	help
 	  This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
 	  This gets frequency tables from DT.
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:12 +0200
Subject: [PATCH, RFC 08/22] OMAPDSS: DPI needs DSI
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-9-git-send-email-arnd@arndb.de>

The dpi.c file cannot be build correctly when the dsi.c file is
disabled in Kconfig. This clarifies the dependency in Kconfig
to avoid build errors:

drivers/video/omap2/dss/dpi.c: In function 'dpi_calc_pll_cb':
drivers/video/omap2/dss/dpi.c:181:2: error: implicit declaration of function 'dsi_hsdiv_calc' [-Werror=implicit-function-declaration]
drivers/video/omap2/dss/dpi.c: In function 'dpi_dsi_clk_calc':
drivers/video/omap2/dss/dpi.c:201:2: error: implicit declaration of function 'dsi_get_pll_clkin' [-Werror=implicit-function-declaration]

Cc: Tomi Valkeinen <tomi.valkeinen at ti.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/video/omap2/dss/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
index cb0f145..4b30084 100644
--- a/drivers/video/omap2/dss/Kconfig
+++ b/drivers/video/omap2/dss/Kconfig
@@ -35,6 +35,7 @@ config OMAP2_DSS_COLLECT_IRQ_STATS
 
 config OMAP2_DSS_DPI
 	bool "DPI support"
+	depends on OMAP2_DSS_DSI
 	default y
 	help
 	  DPI Interface. This is the Parallel Display Interface.
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:14 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:14 +0200
Subject: [PATCH, RFC 10/22] mfd: ab8500: debugfs code depends on gpadc
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-11-git-send-email-arnd@arndb.de>

The AB8500_DEBUG code specifically requires access to the gpadc code,
not just the common ab8500 driver.

drivers/built-in.o: In function `ab8500_gpadc_bat_ctrl_print':
 mfd/ab8500-debugfs.c:1733: undefined reference to `ab8500_gpadc_get'
 mfd/ab8500-debugfs.c:1734: undefined reference to `ab8500_gpadc_read_raw'
 mfd/ab8500-debugfs.c:1736: undefined reference to `ab8500_gpadc_ad_to_voltage'

Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Lee Jones <lee.jones at linaro.org>
Cc: Philippe LANGLAIS <philippe.langlais at stericsson.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/mfd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9b4703e..bf785db 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -580,7 +580,7 @@ config AB8500_CORE
 
 config AB8500_DEBUG
        bool "Enable debug info via debugfs"
-       depends on AB8500_CORE && DEBUG_FS
+       depends on AB8500_GPADC && DEBUG_FS
        default y if DEBUG_FS
        help
          Select this option if you want debug information using the debug
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:19 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:19 +0200
Subject: [PATCH, RFC 15/22] USB: EHCI: remove bogus #error
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-16-git-send-email-arnd@arndb.de>

The EHCI host controller driver can be built standalone now,
without enabling any of the available bus glue drivers, so
there is not really a reason to error out here:

drivers/usb/host/ehci-hcd.c:1303:2: error:
 #error "missing bus glue for ehci-hcd"  #error "missing bus glue for ehci-hcd"

The alternative would be to change the Kconfig code to build
the ehci-hcd module only if any of the symbols below are
in fact enabled.

Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/usb/host/ehci-hcd.c | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 312fc10..246e124 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1286,23 +1286,6 @@ MODULE_LICENSE ("GPL");
 #define	PLATFORM_DRIVER		ehci_hcd_sead3_driver
 #endif
 
-#if !IS_ENABLED(CONFIG_USB_EHCI_PCI) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) && \
-	!IS_ENABLED(CONFIG_USB_CHIPIDEA_HOST) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_MXC) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_HCD_OMAP) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_HCD_ORION) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_HCD_SPEAR) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_S5P) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_HCD_AT91) && \
-	!IS_ENABLED(CONFIG_USB_EHCI_MSM) && \
-	!defined(PLATFORM_DRIVER) && \
-	!defined(PS3_SYSTEM_BUS_DRIVER) && \
-	!defined(OF_PLATFORM_DRIVER) && \
-	!defined(XILINX_OF_PLATFORM_DRIVER)
-#error "missing bus glue for ehci-hcd"
-#endif
-
 static int __init ehci_hcd_init(void)
 {
 	int retval = 0;
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:10 +0200
Subject: [PATCH, RFC 06/22] gpu/drm: host1x: add dependency on Tegra
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-7-git-send-email-arnd@arndb.de>

While we try to make drivers platform independent, this driver currently
calls into an exported interface that is only provided on its own
platform, so we have to add the dependency.

drivers/built-in.o: In function `tegra_crtc_prepare':
 drivers/gpu/host1x/drm/dc.c:650: undefined reference to `tegra_periph_reset_deassert'
drivers/built-in.o: In function `tegra_output_hdmi_disable':
 drivers/gpu/host1x/drm/hdmi.c:840: undefined reference to `tegra_periph_reset_assert'
drivers/built-in.o: In function `tegra_output_hdmi_enable':
 drivers/gpu/host1x/drm/hdmi.c:651: undefined reference to `tegra_periph_reset_assert'
 drivers/gpu/host1x/drm/hdmi.c:653: undefined reference to `tegra_periph_reset_deassert'

Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Arto Merilainen <amerilainen at nvidia.com>
Cc: Terje Bergstrom <tbergstrom at nvidia.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/gpu/host1x/drm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/host1x/drm/Kconfig b/drivers/gpu/host1x/drm/Kconfig
index 69853a4..5a6a5cd 100644
--- a/drivers/gpu/host1x/drm/Kconfig
+++ b/drivers/gpu/host1x/drm/Kconfig
@@ -1,6 +1,7 @@
 config DRM_TEGRA
 	bool "NVIDIA Tegra DRM"
 	depends on DRM
+	depends on ARCH_TEGRA
 	select DRM_KMS_HELPER
 	select FB_SYS_FILLRECT
 	select FB_SYS_COPYAREA
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:26 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:26 +0200
Subject: [PATCH, RFC 22/22] radio-si4713: depend on SND_SOC
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-23-git-send-email-arnd@arndb.de>

It is not possible to select SND_SOC_SI476X if we have not also
enabled SND_SOC.

warning: (RADIO_SI476X) selects SND_SOC_SI476X which has unmet
	 direct dependencies (SOUND && !M68K && !UML && SND && SND_SOC)

Cc: Hans Verkuil <hverkuil at xs4all.nl>
Cc: linux-media at vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/media/radio/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig
index c0beee2..d529ba7 100644
--- a/drivers/media/radio/Kconfig
+++ b/drivers/media/radio/Kconfig
@@ -22,6 +22,7 @@ config RADIO_SI476X
 	tristate "Silicon Laboratories Si476x I2C FM Radio"
 	depends on I2C && VIDEO_V4L2
 	depends on MFD_SI476X_CORE
+	depends on SND_SOC
 	select SND_SOC_SI476X
 	---help---
 	  Choose Y here if you have this FM radio chip.
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:24 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:24 +0200
Subject: [PATCH, RFC 20/22] media: coda: select GENERIC_ALLOCATOR
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-21-git-send-email-arnd@arndb.de>

The coda driver uses the generic allocator to get at the
"iram" memory, so add the necessary dependency to avoid:

drivers/built-in.o: In function `coda_remove':
 :(.text+0x2ab680): undefined reference to `gen_pool_free'
drivers/built-in.o: In function `coda_probe':
:(.text+0x2ad168): undefined reference to `of_get_named_gen_pool'
:(.text+0x2ad188): undefined reference to `dev_get_gen_pool'
:(.text+0x2ad220): undefined reference to `gen_pool_alloc'
:(.text+0x2ad2ec): undefined reference to `gen_pool_virt_to_phys'

Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/media/platform/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 0494d27..4608d03 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -145,6 +145,7 @@ config VIDEO_CODA
 	depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXC
 	select VIDEOBUF2_DMA_CONTIG
 	select V4L2_MEM2MEM_DEV
+	select GENERIC_ALLOCATOR
 	---help---
 	   Coda is a range of video codec IPs that supports
 	   H.264, MPEG-4, and other video formats.
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:16 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:16 +0200
Subject: [PATCH, RFC 12/22] thermal: cpu_cooling: fix stub function
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-13-git-send-email-arnd@arndb.de>

The function stub for cpufreq_cooling_get_level introduced
in 57df81069 "Thermal: exynos: fix cooling state translation"
is not syntactically correct C and needs to be fixed to avoid
this error:

In file included from drivers/thermal/db8500_thermal.c:20:0:
 include/linux/cpu_cooling.h: In function 'cpufreq_cooling_get_level':
include/linux/cpu_cooling.h:57:1:
 error: parameter name omitted  unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)  ^
 include/linux/cpu_cooling.h:57:1: error: parameter name omitted

Cc: Eduardo Valentin <eduardo.valentin at ti.com>
Cc: Zhang Rui <rui.zhang at intel.com>
Cc: Amit Daniel kachhap <amit.daniel at samsung.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 include/linux/cpu_cooling.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h
index 282e270..cf03111 100644
--- a/include/linux/cpu_cooling.h
+++ b/include/linux/cpu_cooling.h
@@ -54,7 +54,7 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
 	return;
 }
 static inline
-unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)
+unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq)
 {
 	return THERMAL_CSTATE_INVALID;
 }
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:09 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:09 +0200
Subject: [PATCH, RFC 05/22] drm: always provide debugfs function prototypes
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-6-git-send-email-arnd@arndb.de>

It is generally considered bad style to enclose function prototypes
in header files in #ifdef. This case illustrates why that is:
The tegra host1x driver calls into the debugfs functions if
CONFIG_DEBUG_FS is enabled, but that code is otherwise already
discarded by the compiler, so leaving the prototype in place
actually makes everything work.

drivers/gpu/host1x/drm/dc.c: In function 'tegra_dc_debugfs_init':
drivers/gpu/host1x/drm/dc.c:1004:2: error: implicit declaration of function 'drm_debugfs_create_files' [-Werror=implicit-function-declaration]
drivers/gpu/host1x/drm/dc.c: In function 'tegra_dc_debugfs_exit': drivers/gpu/host1x/drm/dc.c:1026:2: error: implicit declaration of function 'drm_debugfs_remove_files' [-Werror=implicit-function-declaration]

Cc: Ben Gamari <bgamari at gmail.com>
Cc: Dave Airlie <airlied at redhat.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 include/drm/drmP.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 6119659..f780d62 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1550,7 +1550,7 @@ extern int drm_proc_init(struct drm_minor *minor, struct proc_dir_entry *root);
 extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root);
 
 				/* Debugfs support */
-#if defined(CONFIG_DEBUG_FS)
+
 extern int drm_debugfs_init(struct drm_minor *minor, int minor_id,
 			    struct dentry *root);
 extern int drm_debugfs_create_files(struct drm_info_list *files, int count,
@@ -1558,7 +1558,6 @@ extern int drm_debugfs_create_files(struct drm_info_list *files, int count,
 extern int drm_debugfs_remove_files(struct drm_info_list *files, int count,
                                     struct drm_minor *minor);
 extern int drm_debugfs_cleanup(struct drm_minor *minor);
-#endif
 
 				/* Info file support */
 extern int drm_name_info(struct seq_file *m, void *data);
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:17 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:17 +0200
Subject: [PATCH, RFC 13/22] staging/logger: use kuid_t internally
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-14-git-send-email-arnd@arndb.de>

This is probably wrong but lets us build the driver with
CONFIG_UIDGID_STRICT_TYPE_CHECKS enabled. Without it, we get
these errors:

drivers/staging/android/logger.c: In function 'logger_read':
drivers/staging/android/logger.c:316:4: error: incompatible type for argument 3 of 'get_next_entry_by_uid'
drivers/staging/android/logger.c:244:15: note: expected 'uid_t' but argument is of type 'kuid_t'
drivers/staging/android/logger.c: In function 'logger_aio_write':
drivers/staging/android/logger.c:483:14: error: incompatible types when assigning to type 'uid_t' from type 'kuid_t'

which tells us that the driver is not compatible with user namespaces.
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/staging/android/logger.c | 4 ++--
 drivers/staging/android/logger.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/android/logger.c b/drivers/staging/android/logger.c
index b040200..9bd8747 100644
--- a/drivers/staging/android/logger.c
+++ b/drivers/staging/android/logger.c
@@ -242,7 +242,7 @@ static ssize_t do_read_log_to_user(struct logger_log *log,
  * 'log->buffer' which contains the first entry readable by 'euid'
  */
 static size_t get_next_entry_by_uid(struct logger_log *log,
-		size_t off, uid_t euid)
+		size_t off, kuid_t euid)
 {
 	while (off != log->w_off) {
 		struct logger_entry *entry;
@@ -251,7 +251,7 @@ static size_t get_next_entry_by_uid(struct logger_log *log,
 
 		entry = get_entry_header(log, off, &scratch);
 
-		if (entry->euid == euid)
+		if (uid_eq(entry->euid, euid))
 			return off;
 
 		next_len = sizeof(struct logger_entry) + entry->len;
diff --git a/drivers/staging/android/logger.h b/drivers/staging/android/logger.h
index cc6bbd9..70af7d8 100644
--- a/drivers/staging/android/logger.h
+++ b/drivers/staging/android/logger.h
@@ -66,7 +66,7 @@ struct logger_entry {
 	__s32		tid;
 	__s32		sec;
 	__s32		nsec;
-	uid_t		euid;
+	kuid_t		euid;
 	char		msg[0];
 };
 
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:22 +0200
Subject: [PATCH, RFC 18/22] Xen: SWIOTLB is only used on x86
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-19-git-send-email-arnd@arndb.de>

Enabling SWIOTLB_XEN on ARM results in build errors because the
underlying SWIOTLB is only available on X86:

drivers/xen/swiotlb-xen.c: In function 'is_xen_swiotlb_buffer':
drivers/xen/swiotlb-xen.c:105:2: error: implicit declaration of function 'mfn_to_local_pfn

Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
Cc: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/xen/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index dd4d9cb..f03bf50 100644
--- a/drivers/xen/Kconfig
+++ b/drivers/xen/Kconfig
@@ -141,7 +141,7 @@ config XEN_GRANT_DEV_ALLOC
 
 config SWIOTLB_XEN
 	def_bool y
-	depends on PCI
+	depends on PCI && X86
 	select SWIOTLB
 
 config XEN_TMEM
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:25 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:25 +0200
Subject: [PATCH, RFC 21/22] davinci: vpfe_capture needs i2c
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-22-git-send-email-arnd@arndb.de>

The vpfe_capture driver is implicitly built for three of the davinci
capture drivers but depends on i2c, so we need to add the dependency
in Kconfig for each driver using this.

 drivers/media/platform/davinci/vpfe_capture.c: In function 'vpfe_probe':
 drivers/media/platform/davinci/vpfe_capture.c:1934:2: error: implicit declaration of function 'i2c_get_adapter' [-Werror=implicit-function-declaration]
 drivers/media/platform/davinci/vpfe_capture.c:1934:11: warning: assignment makes pointer from integer without a cast [enabled by default]

Cc: Lad, Prabhakar <prabhakar.csengg at gmail.com>
Cc: Hans Verkuil <hans.verkuil at cisco.com>
Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/media/platform/davinci/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/media/platform/davinci/Kconfig b/drivers/media/platform/davinci/Kconfig
index afb3aec..02da88b 100644
--- a/drivers/media/platform/davinci/Kconfig
+++ b/drivers/media/platform/davinci/Kconfig
@@ -27,6 +27,7 @@ config VIDEO_DAVINCI_VPIF_CAPTURE
 config VIDEO_DM6446_CCDC
 	tristate "TI DM6446 CCDC video capture driver"
 	depends on VIDEO_V4L2 && (ARCH_DAVINCI || ARCH_OMAP3)
+	depends on I2C
 	select VIDEOBUF_DMA_CONTIG
 	help
 	   Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces
@@ -41,6 +42,7 @@ config VIDEO_DM6446_CCDC
 config VIDEO_DM355_CCDC
 	tristate "TI DM355 CCDC video capture driver"
 	depends on VIDEO_V4L2 && ARCH_DAVINCI
+	depends on I2C
 	select VIDEOBUF_DMA_CONTIG
 	help
 	   Enables DM355 CCD hw module. DM355 CCDC hw interfaces
@@ -55,6 +57,7 @@ config VIDEO_DM355_CCDC
 config VIDEO_DM365_ISIF
 	tristate "TI DM365 ISIF video capture driver"
 	depends on VIDEO_V4L2 && ARCH_DAVINCI
+	depends on I2C
 	select VIDEOBUF_DMA_CONTIG
 	help
 	   Enables ISIF hw module. This is the hardware module for
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:13 +0200
Subject: [PATCH, RFC 09/22] crypto: lz4: don't build on ARM
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-10-git-send-email-arnd@arndb.de>

It is not currently possible to build the LZ4 code on ARM, so let's
remove that option in Kconfig for now.

lib/built-in.o: In function `lz4_compress64kctx':
 lib/lz4/lz4_compress.c:339: undefined reference to `__ctzsi2'
lib/built-in.o: In function `lz4_compressctx':
 lib/lz4/lz4_compress.c:157: undefined reference to `__ctzsi2'
lib/built-in.o: In function `lz4hc_commonlength':
 lib/lz4/lz4hc_compress.c:102: undefined reference to `__ctzsi2'
 lib/lz4/lz4hc_compress.c:102: undefined reference to `__ctzsi2'
lib/built-in.o: In function `lz4hc_insertandgetwidermatch':
 lib/lz4/lz4hc_compress.c:230: undefined reference to `__ctzsi2'

Cc: Chanho Min <chanho.min at lge.com>
Cc: Herbert Xu <herbert at gondor.hengli.com.au>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 crypto/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/crypto/Kconfig b/crypto/Kconfig
index aa3a349..1cd134b 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -1361,6 +1361,7 @@ config CRYPTO_842
 
 config CRYPTO_LZ4
 	tristate "LZ4 compression algorithm"
+	depends on !ARM
 	select CRYPTO_ALGAPI
 	select LZ4_COMPRESS
 	select LZ4_DECOMPRESS
@@ -1369,6 +1370,7 @@ config CRYPTO_LZ4
 
 config CRYPTO_LZ4HC
 	tristate "LZ4HC compression algorithm"
+	depends on !ARM
 	select CRYPTO_ALGAPI
 	select LZ4HC_COMPRESS
 	select LZ4_DECOMPRESS
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:20 +0200
Subject: [PATCH, RFC 16/22] USB: UHCI: clarify Kconfig dependencies
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-17-git-send-email-arnd@arndb.de>

The UHCI driver currently gives a build error if the base driver is
enabled but none of the three bus glues are turned on:

drivers/usb/host/uhci-hcd.c:857:2: error: #error "missing bus glue for uhci-hcd"

A better solution for this is to change the Kconfig statements to
prevent getting into this situation. This adds a new USB_UHCI_CORE
symbol in Kconfig, which is selected by each of the three bus glues.
This way, the driver never gets built if all three of them are disabled.

Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/usb/host/Kconfig    | 36 +++++++++++++++++++++++++++---------
 drivers/usb/host/Makefile   |  2 +-
 drivers/usb/host/uhci-hcd.c |  4 ++--
 3 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 7b176bc..656af4d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -525,28 +525,46 @@ config USB_UHCI_HCD
 	  To compile this driver as a module, choose M here: the
 	  module will be called uhci-hcd.
 
-config USB_UHCI_SUPPORT_NON_PCI_HC
-	bool
-	depends on USB_UHCI_HCD
-	default y if (SPARC_LEON || ARCH_VT8500)
+if USB_UHCI_HCD
+
+config USB_UHCI_PCI
+	tristate
+	default USB_UHCI_HCD
+	depends on PCI
+	select USB_UHCI_CORE
+
+config USB_UHCI_GRLIB
+	tristate
+	default USB_UHCI_HCD
+	depends on SPARC_LEON
+	select USB_UHCI_CORE
+	select USB_UHCI_SUPPORT_NON_PCI_HC
+	select USB_UHCI_BIG_ENDIAN_MMIO
+	select USB_UHCI_BIG_ENDIAN_DESC
 
 config USB_UHCI_PLATFORM
 	bool "Generic UHCI Platform Driver support"
-	depends on USB_UHCI_SUPPORT_NON_PCI_HC
 	default y if ARCH_VT8500
+	select USB_UHCI_SUPPORT_NON_PCI_HC
+	select USB_UHCI_CORE
 	---help---
 	  Enable support for generic UHCI platform devices that require no
 	  additional configuration.
 
+config USB_UHCI_CORE
+	tristate
+	depends on USB_UHCI_HCD
+
+config USB_UHCI_SUPPORT_NON_PCI_HC
+	bool
+
 config USB_UHCI_BIG_ENDIAN_MMIO
 	bool
-	depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON
-	default y
 
 config USB_UHCI_BIG_ENDIAN_DESC
 	bool
-	depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON
-	default y
+
+endif
 
 config USB_FHCI_HCD
 	tristate "Freescale QE USB Host Controller support"
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4fb73c1..1441d42 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -38,7 +38,7 @@ obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
-obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
+obj-$(CONFIG_USB_UHCI_CORE)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
 obj-$(CONFIG_USB_SL811_HCD)	+= sl811-hcd.o
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index 4a86b63..612b792 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -838,12 +838,12 @@ static int uhci_count_ports(struct usb_hcd *hcd)
 
 static const char hcd_name[] = "uhci_hcd";
 
-#ifdef CONFIG_PCI
+#ifdef CONFIG_USB_UHCI_PCI
 #include "uhci-pci.c"
 #define	PCI_DRIVER		uhci_pci_driver
 #endif
 
-#ifdef CONFIG_SPARC_LEON
+#ifdef CONFIG_USB_UHCI_GRLIB
 #include "uhci-grlib.c"
 #define PLATFORM_DRIVER		uhci_grlib_driver
 #endif
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:08 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:08 +0200
Subject: [PATCH, RFC 04/22] staging/drm: imx: add missing dependencies
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-5-git-send-email-arnd@arndb.de>

The imx DRM driver needs a couple of extra Kconfig dependencies
to avoid random build failures:

drivers/staging/imx-drm/ipuv3-crtc.c:448:
 undefined reference to `ipu_idmac_put'
 drivers/staging/imx-drm/ipuv3-crtc.c:450: undefined reference to
 `ipu_dmfc_put' drivers/staging/imx-drm/ipuv3-crtc.c:452:
 undefined reference to `ipu_dp_put'
 drivers/staging/imx-drm/ipuv3-crtc.c:454: undefined reference to
 `ipu_di_put'
drivers/built-in.o: In function `ipu_probe':
 :(.text+0x4b4174): undefined reference to `device_reset'
drivers/built-in.o: In function `imx_tve_probe':
 drivers/staging/imx-drm/imx-tve.c:648: undefined reference to
 `devm_regmap_init_mmio_clk'
drivers/built-in.o: In function
 `imx_pd_connector_get_modes':
 drivers/staging/imx-drm/parallel-display.c:78: undefined
 reference to `of_get_drm_display_mode'

Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/staging/imx-drm/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/staging/imx-drm/Kconfig b/drivers/staging/imx-drm/Kconfig
index 8c9e403..35ccda5 100644
--- a/drivers/staging/imx-drm/Kconfig
+++ b/drivers/staging/imx-drm/Kconfig
@@ -1,6 +1,7 @@
 config DRM_IMX
 	tristate "DRM Support for Freescale i.MX"
 	select DRM_KMS_HELPER
+	select VIDEOMODE_HELPERS
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_CMA_HELPER
 	depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM)
@@ -23,6 +24,7 @@ config DRM_IMX_PARALLEL_DISPLAY
 config DRM_IMX_TVE
 	tristate "Support for TV and VGA displays"
 	depends on DRM_IMX
+	select REGMAP_MMIO
 	help
 	  Choose this to enable the internal Television Encoder (TVe)
 	  found on i.MX53 processors.
@@ -30,6 +32,7 @@ config DRM_IMX_TVE
 config DRM_IMX_IPUV3_CORE
 	tristate "IPUv3 core support"
 	depends on DRM_IMX
+	depends on RESET_CONTROLLER
 	help
 	  Choose this if you have a i.MX5/6 system and want
 	  to use the IPU. This option only enables IPU base
@@ -38,5 +41,6 @@ config DRM_IMX_IPUV3_CORE
 config DRM_IMX_IPUV3
 	tristate "DRM Support for i.MX IPUv3"
 	depends on DRM_IMX
+	depends on DRM_IMX_IPUV3_CORE
 	help
 	  Choose this if you have a i.MX5 or i.MX6 processor.
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:04 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:04 +0200
Subject: [PATCH, RFC 00/22] ARM randconfig bugs
Message-ID: <1367507786-505303-1-git-send-email-arnd@arndb.de>

Hi subsystem maintainers,

This is a set of patches to to fix build errors I hit while trying to
build lots of randconfig kernels on linux-next.

Most of them are simple missing dependencies in Kconfig, but some are
more substantial. I would like to see at least the obvious patches
get merged for 3.10. If you are happy with the patches, feel free
to apply them directly, otherwise please provide feedback.

No single patch out of these is very important though, most of them
only concern corner cases and don't matter in practice.

	Arnd

Arnd Bergmann (22):
  can: move CONFIG_HAVE_CAN_FLEXCAN out of CAN_DEV
  cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
  cpuidle: calxeda: select ARM_CPU_SUSPEND
  staging/drm: imx: add missing dependencies
  drm: always provide debugfs function prototypes
  gpu/drm: host1x: add dependency on Tegra
  drm/tilcd: select BACKLIGHT_LCD_SUPPORT
  OMAPDSS: DPI needs DSI
  crypto: lz4: don't build on ARM
  mfd: ab8500: debugfs code depends on gpadc
  iwlegacy: il_pm_ops is only provided for PM_SLEEP
  thermal: cpu_cooling: fix stub function
  staging/logger: use kuid_t internally
  oprofile: always enable IRQ_WORK
  USB: EHCI: remove bogus #error
  USB: UHCI: clarify Kconfig dependencies
  USB: OHCI: clarify Kconfig dependencies
  Xen: SWIOTLB is only used on x86
  staging/solo6x10: depend on CONFIG_FONTS
  media: coda: select GENERIC_ALLOCATOR
  davinci: vpfe_capture needs i2c
  radio-si4713: depend on SND_SOC

 arch/Kconfig                           |  1 +
 crypto/Kconfig                         |  2 ++
 drivers/cpufreq/Kconfig.arm            |  1 +
 drivers/cpuidle/Kconfig                |  1 +
 drivers/gpu/drm/tilcdc/Kconfig         |  1 +
 drivers/gpu/host1x/drm/Kconfig         |  1 +
 drivers/media/platform/Kconfig         |  1 +
 drivers/media/platform/davinci/Kconfig |  3 ++
 drivers/media/radio/Kconfig            |  1 +
 drivers/mfd/Kconfig                    |  2 +-
 drivers/net/can/Kconfig                |  6 ++--
 drivers/net/wireless/iwlegacy/common.h |  2 +-
 drivers/staging/android/logger.c       |  4 +--
 drivers/staging/android/logger.h       |  2 +-
 drivers/staging/imx-drm/Kconfig        |  4 +++
 drivers/staging/media/solo6x10/Kconfig |  1 +
 drivers/usb/host/Kconfig               | 65 +++++++++++++++++++++++++++++-----
 drivers/usb/host/Makefile              |  4 +--
 drivers/usb/host/ehci-hcd.c            | 17 ---------
 drivers/usb/host/ohci-hcd.c            | 19 ----------
 drivers/usb/host/uhci-hcd.c            |  4 +--
 drivers/video/console/Makefile         |  2 ++
 drivers/video/omap2/dss/Kconfig        |  1 +
 drivers/xen/Kconfig                    |  2 +-
 include/drm/drmP.h                     |  3 +-
 include/linux/cpu_cooling.h            |  2 +-
 26 files changed, 91 insertions(+), 61 deletions(-)

-- 
1.8.1.2

Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Dave Airlie <airlied at redhat.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Hans Verkuil <hverkuil at xs4all.nl>
Cc: Herbert Xu <herbert at gondor.hengli.com.au>
Cc: John W. Linville <linville at tuxdriver.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
Cc: Mauro Carvalho Chehab <mchehab at infradead.org>
Cc: Oliver Hartkopp <socketcan at hartkopp.net>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Robert Richter <rric at kernel.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Tomi Valkeinen <tomi.valkeinen at ti.com>
Cc: Viresh Kumar <viresh.kumar at linaro.org>
Cc: Zhang Rui <rui.zhang at intel.com>
Cc: cpufreq at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: linux-can at vger.kernel.org
Cc: linux-media at vger.kernel.org
Cc: linux-pm at vger.kernel.org
Cc: oprofile-list at lists.sf.net



From arnd at arndb.de  Thu May  2 11:16:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:23 +0200
Subject: [PATCH, RFC 19/22] staging/solo6x10: depend on CONFIG_FONTS
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-20-git-send-email-arnd@arndb.de>

The new SOLO6X10 driver needs the built-in console fonts, specifically
the VGA8x16 font and building it without console support results in
a link error error.

drivers/built-in.o: In function `solo_osd_print':
 :(.text+0x7d3424): undefined reference to `find_font'

This adds a dependency on the CONFIG_FONTS symbol and changes the
console code to always build the base driver even if there are
no specific fonts built-in.

Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Hans Verkuil <hans.verkuil at cisco.com>
Cc: Mauro Carvalho Chehab <mchehab at infradead.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/staging/media/solo6x10/Kconfig | 1 +
 drivers/video/console/Makefile         | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/staging/media/solo6x10/Kconfig b/drivers/staging/media/solo6x10/Kconfig
index ec32776..df6569b 100644
--- a/drivers/staging/media/solo6x10/Kconfig
+++ b/drivers/staging/media/solo6x10/Kconfig
@@ -1,6 +1,7 @@
 config SOLO6X10
 	tristate "Softlogic 6x10 MPEG codec cards"
 	depends on PCI && VIDEO_DEV && SND && I2C
+	depends on FONTS
 	select VIDEOBUF2_DMA_SG
 	select VIDEOBUF2_DMA_CONTIG
 	select SND_PCM
diff --git a/drivers/video/console/Makefile b/drivers/video/console/Makefile
index a862e91..48da25c 100644
--- a/drivers/video/console/Makefile
+++ b/drivers/video/console/Makefile
@@ -18,6 +18,8 @@ font-objs-$(CONFIG_FONT_MINI_4x6)  += font_mini_4x6.o
 
 font-objs += $(font-objs-y)
 
+obj-$(CONFIG_FONTS) += font.o
+
 # Each configuration option enables a list of files.
 
 obj-$(CONFIG_DUMMY_CONSOLE)       += dummycon.o
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:18 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:18 +0200
Subject: [PATCH, RFC 14/22] oprofile: always enable IRQ_WORK
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-15-git-send-email-arnd@arndb.de>

oprofile fails to build if CONFIG_IRQ_WORK is not already enabled,
because of the dependency on the RING_BUFFER code that now uses
the irq work library.

kernel/built-in.o: In function `ring_buffer_unlock_commit':
:(.text+0x5b8f0): undefined reference to `irq_work_queue'
kernel/built-in.o: In function `ring_buffer_write':
:(.text+0x5bd10): undefined reference to `irq_work_queue'

Cc: Robert Richter <rric at kernel.org>
Cc: oprofile-list at lists.sf.net
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index a6b1056..434a8dc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -8,6 +8,7 @@ config OPROFILE
 	depends on HAVE_OPROFILE
 	select RING_BUFFER
 	select RING_BUFFER_ALLOW_SWAP
+	select IRQ_WORK
 	help
 	  OProfile is a profiling system capable of profiling the
 	  whole system, include the kernel, kernel modules, libraries,
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:21 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:21 +0200
Subject: [PATCH, RFC 17/22] USB: OHCI: clarify Kconfig dependencies
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-18-git-send-email-arnd@arndb.de>

The OHCI driver currently gives a build error if the base driver is
enabled but none of its bus glues are turned on:

drivers/usb/host/ohci-hcd.c:1209:2: error:
 #error "missing bus glue for ohci-hcd"  #error "missing bus glue for ohci-hcd"

A better solution for this is to change the Kconfig statements to
prevent getting into this situation. This adds a new USB_UHCI_CORE
symbol in Kconfig, which is selected by each of the bus glues.
This way, the driver never gets built if all of them are disabled.

Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/usb/host/Kconfig    | 29 +++++++++++++++++++++++++++++
 drivers/usb/host/Makefile   |  2 +-
 drivers/usb/host/ohci-hcd.c | 19 -------------------
 3 files changed, 30 insertions(+), 20 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 656af4d..46d1b9e 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -368,9 +368,30 @@ config USB_OHCI_HCD
 
 if USB_OHCI_HCD
 
+config USB_OHCI_CORE
+	tristate
+	depends on USB_OHCI_HCD
+	default y if PCI
+	default y if ARCH_SA1100 && SA1111
+	default y if ARCH_S3C24XX
+	default y if ARCH_S3C64XX
+	default y if PXA27x
+	default y if PXA3xx
+	default y if ARCH_EP93XX
+	default y if ARCH_AT91
+	default y if ARCH_LPC32XX
+	default y if ARCH_DAVINCI_DA8XX
+	default y if PLAT_SPEAR
+	default y if PPC_PS3
+	default y if MFD_SM501
+	default y if MFD_TC6393XB
+	default y if MACH_JZ4740
+	default y if TILE_USB
+
 config USB_OHCI_HCD_OMAP1
 	bool "OHCI support for OMAP1/2 chips"
 	depends on ARCH_OMAP1
+	select USB_OHCI_CORE
 	default y
 	---help---
 	  Enables support for the OHCI controller on OMAP1/2 chips.
@@ -378,6 +399,7 @@ config USB_OHCI_HCD_OMAP1
 config USB_OHCI_HCD_OMAP3
 	bool "OHCI support for OMAP3 and later chips"
 	depends on (ARCH_OMAP3 || ARCH_OMAP4)
+	select USB_OHCI_CORE
 	default y
 	---help---
 	  Enables support for the on-chip OHCI controller on
@@ -398,6 +420,7 @@ config USB_OHCI_ATH79
 config USB_OHCI_HCD_PPC_OF_BE
 	bool "OHCI support for OF platform bus (big endian)"
 	depends on PPC_OF
+	select USB_OHCI_CORE
 	select USB_OHCI_BIG_ENDIAN_DESC
 	select USB_OHCI_BIG_ENDIAN_MMIO
 	---help---
@@ -407,6 +430,7 @@ config USB_OHCI_HCD_PPC_OF_BE
 config USB_OHCI_HCD_PPC_OF_LE
 	bool "OHCI support for OF platform bus (little endian)"
 	depends on PPC_OF
+	select USB_OHCI_CORE
 	select USB_OHCI_LITTLE_ENDIAN
 	---help---
 	  Enables support for little-endian USB controllers present on the
@@ -421,6 +445,7 @@ config USB_OHCI_HCD_PCI
 	bool "OHCI support for PCI-bus USB controllers"
 	depends on PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
 	default y
+	select USB_OHCI_CORE
 	select USB_OHCI_LITTLE_ENDIAN
 	---help---
 	  Enables support for PCI-bus plug-in USB controller cards.
@@ -458,6 +483,7 @@ config USB_OHCI_SH
 config USB_OHCI_EXYNOS
 	boolean "OHCI support for Samsung EXYNOS SoC Series"
 	depends on ARCH_EXYNOS
+	select USB_OHCI_CORE
 	help
 	 Enable support for the Samsung Exynos SOC's on-chip OHCI controller.
 
@@ -465,6 +491,7 @@ config USB_CNS3XXX_OHCI
 	bool "Cavium CNS3XXX OHCI Module (DEPRECATED)"
 	depends on ARCH_CNS3XXX
 	select USB_OHCI_HCD_PLATFORM
+	select USB_OHCI_CORE
 	---help---
 	  This option is deprecated now and the driver was removed, use
 	  USB_OHCI_HCD_PLATFORM instead.
@@ -475,6 +502,7 @@ config USB_CNS3XXX_OHCI
 config USB_OHCI_HCD_PLATFORM
 	bool "Generic OHCI driver for a platform device"
 	default n
+	select USB_OHCI_CORE
 	---help---
 	  Adds an OHCI host driver for a generic platform device, which
 	  provides a memory space and an irq.
@@ -487,6 +515,7 @@ config USB_OCTEON_OHCI
 	default USB_OCTEON_EHCI
 	select USB_OHCI_BIG_ENDIAN_MMIO
 	select USB_OHCI_LITTLE_ENDIAN
+	select USB_OHCI_CORE
 	help
 	  Enable support for the Octeon II SOC's on-chip OHCI
 	  controller.  It is needed for low-speed USB 1.0 device
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 1441d42..2697bd9 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -37,7 +37,7 @@ obj-$(CONFIG_USB_EHCI_MSM)	+= ehci-msm.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
-obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+obj-$(CONFIG_USB_OHCI_CORE)	+= ohci-hcd.o
 obj-$(CONFIG_USB_UHCI_CORE)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9e6de95..2bb1b06 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1190,25 +1190,6 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_platform_driver
 #endif
 
-#if	!defined(PCI_DRIVER) &&		\
-	!defined(PLATFORM_DRIVER) &&	\
-	!defined(OMAP1_PLATFORM_DRIVER) &&	\
-	!defined(OMAP3_PLATFORM_DRIVER) &&	\
-	!defined(OF_PLATFORM_DRIVER) &&	\
-	!defined(SA1111_DRIVER) &&	\
-	!defined(PS3_SYSTEM_BUS_DRIVER) && \
-	!defined(SM501_OHCI_DRIVER) && \
-	!defined(TMIO_OHCI_DRIVER) && \
-	!defined(S3C2410_PLATFORM_DRIVER) && \
-	!defined(EXYNOS_PLATFORM_DRIVER) && \
-	!defined(EP93XX_PLATFORM_DRIVER) && \
-	!defined(AT91_PLATFORM_DRIVER) && \
-	!defined(NXP_PLATFORM_DRIVER) && \
-	!defined(DAVINCI_PLATFORM_DRIVER) && \
-	!defined(SPEAR_PLATFORM_DRIVER)
-#error "missing bus glue for ohci-hcd"
-#endif
-
 static int __init ohci_hcd_mod_init(void)
 {
 	int retval = 0;
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 11:16:15 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 17:16:15 +0200
Subject: [PATCH, RFC 11/22] iwlegacy: il_pm_ops is only provided for PM_SLEEP
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <1367507786-505303-12-git-send-email-arnd@arndb.de>

This makes sure the conditionals for the declaration match the
definition, so we provide the alternative

 #else
 #define IL_LEGACY_PM_OPS NULL
 #endif

in the correct cases.

drivers/built-in.o:(.data+0x57974): undefined reference to `il_pm_ops'

Cc: Johannes Berg <johannes.berg at intel.com>
Cc: John W. Linville <linville at tuxdriver.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/net/wireless/iwlegacy/common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2..734f1b4 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,7 +1832,7 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
 			  u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS	(&il_pm_ops)
-- 
1.8.1.2



From will.deacon at arm.com  Thu May  2 11:17:53 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 2 May 2013 16:17:53 +0100
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <CAEDV+gJwYpHzehWZci2bmgYedJoBxMOGZFhjGeGRQ_cT8TKkyw@mail.gmail.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
 <20130502150355.GA25022@mudshark.cambridge.arm.com>
 <CAEDV+gJwYpHzehWZci2bmgYedJoBxMOGZFhjGeGRQ_cT8TKkyw@mail.gmail.com>
Message-ID: <20130502151753.GB25022@mudshark.cambridge.arm.com>

On Thu, May 02, 2013 at 04:15:05PM +0100, Christoffer Dall wrote:
> On Thu, May 2, 2013 at 8:03 AM, Will Deacon <will.deacon at arm.com> wrote:
> > On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> >> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> >> introduced code that flushes page tables to the point of coherency.
> >> This is overkill (point of unification is enough and already done),
> >> and actually not required if running on a SMP capable platform
> >> (the HW PTW can snoop other cpus' L1).
> >>
> >> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> >> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> >> a no-op for SMP ARMv7.
> >>
> >> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> >> Cc: Will Deacon <will.deacon at arm.com>
> >> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> >> ---
> >>  arch/arm/kvm/mmu.c | 3 ---
> >>  1 file changed, 3 deletions(-)
> >>
> >> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> >> index 4a838db..d79b594 100644
> >> --- a/arch/arm/kvm/mmu.c
> >> +++ b/arch/arm/kvm/mmu.c
> >> @@ -234,7 +234,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
> >>               pte = pte_offset_kernel(pmd, addr);
> >>               kvm_set_pte(pte, pfn_pte(pfn, prot));
> >>               get_page(virt_to_page(pte));
> >> -             kvm_flush_dcache_to_poc(pte, sizeof(*pte));
> >>               pfn++;
> >>       } while (addr += PAGE_SIZE, addr != end);
> >
> > Could you remove the flushing code out of kvm_set_pte, then flush the range
> > after the loop? Then you get one flush and one barrier for the whole range.
> >
> that would be different from how it's done in the rest of the kernel
> where you're expecting set_pte to do the necessary flushing for you,
> no?

Correct, but since kvm_set_pte seems only to be called from this file, I'm
not sure you need to match thes rest of the kernel.

> instead, if this optimization is worth it, the code could just use
> pte_val(pte) = XX;

or just *pte = XX;

Will


From edubezval at gmail.com  Thu May  2 11:24:18 2013
From: edubezval at gmail.com (edubezval at gmail.com)
Date: Thu, 2 May 2013 11:24:18 -0400
Subject: [PATCH, RFC 22/22] radio-si4713: depend on SND_SOC
In-Reply-To: <1367507786-505303-23-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-23-git-send-email-arnd@arndb.de>
Message-ID: <CAC-25o9Xp+pu_AUwxyh+YsiOCOebzMRF37v1VWZJD6nrbx5e6Q@mail.gmail.com>

Arnd,

On Thu, May 2, 2013 at 11:16 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> It is not possible to select SND_SOC_SI476X if we have not also
> enabled SND_SOC.
>
> warning: (RADIO_SI476X) selects SND_SOC_SI476X which has unmet
>          direct dependencies (SOUND && !M68K && !UML && SND && SND_SOC)
>
> Cc: Hans Verkuil <hverkuil at xs4all.nl>
> Cc: linux-media at vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---

Note on your patch title, this change is against si476X, not on *si4713*.



>  drivers/media/radio/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig
> index c0beee2..d529ba7 100644
> --- a/drivers/media/radio/Kconfig
> +++ b/drivers/media/radio/Kconfig
> @@ -22,6 +22,7 @@ config RADIO_SI476X
>         tristate "Silicon Laboratories Si476x I2C FM Radio"
>         depends on I2C && VIDEO_V4L2
>         depends on MFD_SI476X_CORE
> +       depends on SND_SOC
>         select SND_SOC_SI476X
>         ---help---
>           Choose Y here if you have this FM radio chip.
> --
> 1.8.1.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-media" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Eduardo Bezerra Valentin


From arnd at arndb.de  Thu May  2 11:26:49 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 17:26:49 +0200
Subject: [PATCH 20/23 v2] ARM: u300: add SPI PL022 to the device tree
In-Reply-To: <1367485952-6212-1-git-send-email-linus.walleij@stericsson.com>
References: <1367485952-6212-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <201305021726.49729.arnd@arndb.de>

On Thursday 02 May 2013, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This registers the PL022 PrimeCell from the U300 device
> tree. We make a new copy of the platform data for the
> device tree boot path, as the old platform data is in an
> older file which will be going away.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Why do you need both the platform data and the DT description?

	Arnd


From arnd at arndb.de  Thu May  2 11:27:57 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 17:27:57 +0200
Subject: [PATCH] ARM: imx: compile fix for hotplug.c
In-Reply-To: <1367474331-3479-1-git-send-email-shawn.guo@linaro.org>
References: <1367474331-3479-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <201305021727.57769.arnd@arndb.de>

On Thursday 02 May 2013, Shawn Guo wrote:
> Commit bca7a5a (ARM: cpu hotplug: remove majority of cache flushing
> from platforms) removes include of <asm/cacheflush.h> and hence
> discovers a few indirect inclusion and declaration problems as below.
> 
>   CC      arch/arm/mach-imx/hotplug.o
> In file included from arch/arm/mach-imx/hotplug.c:16:0:
> arch/arm/mach-imx/common.h:100:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
> arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
> arch/arm/mach-imx/common.h:101:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
> arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_die?:
> arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ?cpu_do_idle? [-Werror=implicit-function-declaration]
> arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_kill?:
> arch/arm/mach-imx/hotplug.c:58:26: error: ?jiffies? undeclared (first use in this function)
> arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
> arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ?msecs_to_jiffies? [-Werror=implicit-function-declaration]
> arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ?time_after? [-Werror=implicit-function-declaration]
> 
> Fix them by adding the needed inclusion and declaration.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Acked-by: Arnd Bergmann <arnd at arndb.de>

I found the same thing today, and there seems to be a similar problem for highbank.

	Arnd


From catalin.marinas at arm.com  Thu May  2 11:31:34 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 16:31:34 +0100
Subject: [PATCH v3 20/32] arm64: KVM: Plug the arch timer
In-Reply-To: <5177C577.2050209@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-21-git-send-email-marc.zyngier@arm.com>
 <20130423230024.GH20569@gmail.com> <5177C577.2050209@arm.com>
Message-ID: <20130502153134.GH20730@arm.com>

On Wed, Apr 24, 2013 at 12:43:51PM +0100, Marc Zyngier wrote:
> On 24/04/13 00:00, Christoffer Dall wrote:
> > On Mon, Apr 08, 2013 at 05:17:22PM +0100, Marc Zyngier wrote:
> >> Add support for the in-kernel timer emulation. The include file
> >> is a complete duplicate of the 32bit one - something to fix
> >> at one point.
> > 
> > again, I'd really like to see this fixed before we merge the code...
> 
> Feel free to suggest a solution. None of the one I tried are nice.

Both arch timers and GIC are now drivers outside the arch/ directories.
To me it makes sense for emulated device drivers to also live outside
the arch/ directories, something like virt/kvm/drivers? As you said,
ioapic is already in virt/kvm.

-- 
Catalin


From lee.jones at linaro.org  Thu May  2 11:36:24 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 May 2013 16:36:24 +0100
Subject: [PATCH, RFC 10/22] mfd: ab8500: debugfs code depends on gpadc
In-Reply-To: <1367507786-505303-11-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-11-git-send-email-arnd@arndb.de>
Message-ID: <20130502153624.GN25256@gmail.com>

On Thu, 02 May 2013, Arnd Bergmann wrote:

> The AB8500_DEBUG code specifically requires access to the gpadc code,
> not just the common ab8500 driver.
> 
> drivers/built-in.o: In function `ab8500_gpadc_bat_ctrl_print':
>  mfd/ab8500-debugfs.c:1733: undefined reference to `ab8500_gpadc_get'
>  mfd/ab8500-debugfs.c:1734: undefined reference to `ab8500_gpadc_read_raw'
>  mfd/ab8500-debugfs.c:1736: undefined reference to `ab8500_gpadc_ad_to_voltage'
> 
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Lee Jones <lee.jones at linaro.org>
> Cc: Philippe LANGLAIS <philippe.langlais at stericsson.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/mfd/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 9b4703e..bf785db 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -580,7 +580,7 @@ config AB8500_CORE
>  
>  config AB8500_DEBUG
>         bool "Enable debug info via debugfs"
> -       depends on AB8500_CORE && DEBUG_FS
> +       depends on AB8500_GPADC && DEBUG_FS
>         default y if DEBUG_FS
>         help
>           Select this option if you want debug information using the debug

Did you find this with ALLCONFIG out of interest.

Applied by the way.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From tony at atomide.com  Thu May  2 11:38:34 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 2 May 2013 08:38:34 -0700
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502082218.GA21614@n2100.arm.linux.org.uk>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
Message-ID: <20130502153834.GR28721@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [130502 01:27]:
> On Tue, Apr 30, 2013 at 09:17:39AM +0100, Russell King - ARM Linux wrote:
> > Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> > great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> > arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> > source of errors.
> > 
> > OMAP stuff needs a serious look at too - much Kconfig madness there
> > caused by over-use of select, which then goes on to cause build errors
> > because it assumes some stuff is always enabled.
> > 
> > There's also warnings about of_device_id from include/linux/of_platform.h
> > via from arch/arm/kernel/setup.c which feature in all the non-OF builds
> > too which need addressing.
> > 
> > See todays http://www.arm.linux.org.uk/developer/build/ results for all
> > the details and configs.  Not pushing my tree until some of this stuff
> > gets fixed.
> 
> And now we have a new bunch of warnings from OMAP stuff which weren't
> previously there...
> 
> arch/arm/mach-omap2/omap_device.c: In function 'omap_device_get_by_hwmod_name':
> arch/arm/mach-omap2/omap_device.c:821:3: warning: return makes pointer from integer without a cast
> arch/arm/mach-omap2/omap_device.c:826:3: warning: return makes pointer from integer without a cast

Hmm these I already fixed earlier along with a merge resolution, and
I'm not seeing them in next/master or arm-soc/for-next. What do you
have merged into your current tree?

> drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
> drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result

Neil, care to provide a fix for this? It's from your commit ab37813
(twl4030_charger: Allow charger to control the regulator that feeds it).

> include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event' defined but not used

Eduardo, can you fix that one? It seems to be from your commit 8ab3e6a
(thermal: Use thermal zone device id in netlink messages).

Regards,

Tony


From stefano.stabellini at eu.citrix.com  Thu May  2 11:38:50 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 16:38:50 +0100
Subject: [PATCH, RFC 18/22] Xen: SWIOTLB is only used on x86
In-Reply-To: <1367507786-505303-19-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-19-git-send-email-arnd@arndb.de>
Message-ID: <alpine.DEB.2.02.1305021638100.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Arnd Bergmann wrote:
> Enabling SWIOTLB_XEN on ARM results in build errors because the
> underlying SWIOTLB is only available on X86:
> 
> drivers/xen/swiotlb-xen.c: In function 'is_xen_swiotlb_buffer':
> drivers/xen/swiotlb-xen.c:105:2: error: implicit declaration of function 'mfn_to_local_pfn
> 
> Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> Cc: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>


>  drivers/xen/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
> index dd4d9cb..f03bf50 100644
> --- a/drivers/xen/Kconfig
> +++ b/drivers/xen/Kconfig
> @@ -141,7 +141,7 @@ config XEN_GRANT_DEV_ALLOC
>  
>  config SWIOTLB_XEN
>  	def_bool y
> -	depends on PCI
> +	depends on PCI && X86
>  	select SWIOTLB
>  
>  config XEN_TMEM
> -- 
> 1.8.1.2
> 


From tomi.valkeinen at ti.com  Thu May  2 11:42:39 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Thu, 2 May 2013 18:42:39 +0300
Subject: [PATCH, RFC 08/22] OMAPDSS: DPI needs DSI
In-Reply-To: <1367507786-505303-9-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-9-git-send-email-arnd@arndb.de>
Message-ID: <5182896F.90807@ti.com>

Hi Arnd,

On 05/02/2013 06:16 PM, Arnd Bergmann wrote:
> The dpi.c file cannot be build correctly when the dsi.c file is
> disabled in Kconfig. This clarifies the dependency in Kconfig
> to avoid build errors:
> 
> drivers/video/omap2/dss/dpi.c: In function 'dpi_calc_pll_cb':
> drivers/video/omap2/dss/dpi.c:181:2: error: implicit declaration of function 'dsi_hsdiv_calc' [-Werror=implicit-function-declaration]
> drivers/video/omap2/dss/dpi.c: In function 'dpi_dsi_clk_calc':
> drivers/video/omap2/dss/dpi.c:201:2: error: implicit declaration of function 'dsi_get_pll_clkin' [-Werror=implicit-function-declaration]

I've sent a patch for this to DRM maintainer, hopefully merged soon.

 Tomi


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From eduardo.valentin at ti.com  Thu May  2 11:46:13 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 2 May 2013 11:46:13 -0400
Subject: [PATCH, RFC 12/22] thermal: cpu_cooling: fix stub function
In-Reply-To: <1367507786-505303-13-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-13-git-send-email-arnd@arndb.de>
Message-ID: <51828A45.60909@ti.com>

On 02-05-2013 11:16, Arnd Bergmann wrote:
> The function stub for cpufreq_cooling_get_level introduced
> in 57df81069 "Thermal: exynos: fix cooling state translation"
> is not syntactically correct C and needs to be fixed to avoid
> this error:
> 
> In file included from drivers/thermal/db8500_thermal.c:20:0:
>  include/linux/cpu_cooling.h: In function 'cpufreq_cooling_get_level':
> include/linux/cpu_cooling.h:57:1:
>  error: parameter name omitted  unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)  ^
>  include/linux/cpu_cooling.h:57:1: error: parameter name omitted
> 
> Cc: Eduardo Valentin <eduardo.valentin at ti.com>
> Cc: Zhang Rui <rui.zhang at intel.com>
> Cc: Amit Daniel kachhap <amit.daniel at samsung.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  include/linux/cpu_cooling.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h
> index 282e270..cf03111 100644
> --- a/include/linux/cpu_cooling.h
> +++ b/include/linux/cpu_cooling.h
> @@ -54,7 +54,7 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
>  	return;
>  }
>  static inline
> -unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)
> +unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq)

While there, could you please also include the following (same, but on
the function declaration on line 44), just to keep the header in same style?
diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h
index 282e270..c023afa 100644
--- a/include/linux/cpu_cooling.h
+++ b/include/linux/cpu_cooling.h
@@ -41,7 +41,7 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus);
  */
 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev);

-unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int);
+unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int
freq);
 #else /* !CONFIG_CPU_THERMAL */
 static inline struct thermal_cooling_device *
 cpufreq_cooling_register(const struct cpumask *clip_cpus)


>  {
>  	return THERMAL_CSTATE_INVALID;
>  }
> 


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From lee.jones at linaro.org  Thu May  2 11:48:06 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 16:48:06 +0100
Subject: [PATCH 0/4] Fixing boot warnings in -next 
Message-ID: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>

When booting -next on the u8500 based Snowball development board these
new warnings appeared. If applicable these should probably be filtered
though your -fixes branches.



From lee.jones at linaro.org  Thu May  2 11:48:07 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 16:48:07 +0100
Subject: [PATCH 1/4] ARM: ux500: Rid ignored return value of
 regulator_enable() compiler warning
In-Reply-To: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367509690-24022-2-git-send-email-lee.jones@linaro.org>

arch/arm/mach-ux500/board-mop500.c: In function ?mop500_prox_activate?:
arch/arm/mach-ux500/board-mop500.c:406:18: warning: ignoring return value of
        ?regulator_enable?, declared with attribute warn_unused_result
        [-Wunused-result]

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a15dd6b..9bc762a 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -403,8 +403,8 @@ static int mop500_prox_activate(struct device *dev)
 			"no regulator\n");
 		return PTR_ERR(prox_regulator);
 	}
-	regulator_enable(prox_regulator);
-	return 0;
+	
+	return regulator_enable(prox_regulator);
 }
 
 static void mop500_prox_deactivate(struct device *dev)
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 11:48:09 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 16:48:09 +0100
Subject: [PATCH 3/4] mmc: mmci: Ensure return value of regulator_enable() is
 checked
In-Reply-To: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367509690-24022-4-git-send-email-lee.jones@linaro.org>

This patch suppresses the warning below:

drivers/mmc/host/mmci.c: In function ?mmci_set_ios?:
drivers/mmc/host/mmci.c:1165:20: warning: ignoring return value of
        ?regulator_enable?, declared with attribute warn_unused_result
        [-Wunused-result]

Cc: Russell King <linux at arm.linux.org.uk>
Cc: Chris Ball <cjb at laptop.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mmc/host/mmci.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 375c109..f4f3038 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1130,6 +1130,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	struct variant_data *variant = host->variant;
 	u32 pwr = 0;
 	unsigned long flags;
+	int ret;
 
 	pm_runtime_get_sync(mmc_dev(mmc));
 
@@ -1161,8 +1162,12 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		break;
 	case MMC_POWER_ON:
 		if (!IS_ERR(mmc->supply.vqmmc) &&
-		    !regulator_is_enabled(mmc->supply.vqmmc))
-			regulator_enable(mmc->supply.vqmmc);
+		    !regulator_is_enabled(mmc->supply.vqmmc)) {
+			ret = regulator_enable(mmc->supply.vqmmc);
+			if (ret < 0)
+				dev_err(mmc_dev(mmc),
+					"failed to enable vqmmc regulator\n");
+		}
 
 		pwr |= MCI_PWR_ON;
 		break;
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 11:48:08 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 16:48:08 +0100
Subject: [PATCH 2/4] mfd: ab8500-gpadc: Suppress 'ignoring regulator_enable()
 return value' warning
In-Reply-To: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367509690-24022-3-git-send-email-lee.jones@linaro.org>

drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
        ?regulator_enable?, declared with attribute warn_unused_result
        [-Wunused-result]

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/ab8500-gpadc.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/ab8500-gpadc.c b/drivers/mfd/ab8500-gpadc.c
index 5e65b28..7278e53 100644
--- a/drivers/mfd/ab8500-gpadc.c
+++ b/drivers/mfd/ab8500-gpadc.c
@@ -907,8 +907,11 @@ static int ab8500_gpadc_suspend(struct device *dev)
 static int ab8500_gpadc_resume(struct device *dev)
 {
 	struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
+	int ret;
 
-	regulator_enable(gpadc->regu);
+	ret = regulator_enable(gpadc->regu);
+	if (ret < 0)
+		return ret;
 
 	pm_runtime_mark_last_busy(gpadc->dev);
 	pm_runtime_put_autosuspend(gpadc->dev);
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May  2 11:48:10 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  2 May 2013 16:48:10 +0100
Subject: [PATCH 4/4] =?UTF-8?q?staging:=20ste=5Frmi4:=20Suppress=20'ignoring?=
 =?UTF-8?q?=20return=20value=20of=20=E2=80=98regulator=5Fenable()'=20warning?=
In-Reply-To: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367509690-24022-5-git-send-email-lee.jones@linaro.org>

drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
        In function ?synaptics_rmi4_resume?:
drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
        warning: ignoring return value of ?regulator_enable?, declared
        with attribute warn_unused_result [-Wunused-result

Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: devel at driverdev.osuosl.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
index fe667dd..c4d013d 100644
--- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
+++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
@@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
 	unsigned char intr_status;
 	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
 
-	regulator_enable(rmi4_data->regulator);
+	retval = regulator_enable(rmi4_data->regulator);
+	if (retval < 0)
+		return retval;
 
 	enable_irq(rmi4_data->i2c_client->irq);
 	rmi4_data->touch_stopped = false;
-- 
1.7.10.4



From vinod.koul at intel.com  Thu May  2 11:19:38 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 2 May 2013 20:49:38 +0530
Subject: [PATCH] dmaengine: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <1365660568-2588-1-git-send-email-Barry.Song@csr.com>
References: <1365660568-2588-1-git-send-email-Barry.Song@csr.com>
Message-ID: <20130502151938.GK1960@intel.com>

On Thu, Apr 11, 2013 at 02:09:28PM +0800, Barry Song wrote:
> From: Barry Song <Baohua.Song at csr.com>
> 
> if we initilize dma driver by module_init, there are still many devices
> which will be initilized earlier than dma. these devices will fail to
> get dma channel.
> this moves dmaengine earlier than device_initcall and make dma available
> for all devices.
> 
> Reported-by: Renwei Wu <Renwei.Wu at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
Applied thanks, this is what many drivers in susystem do...

--
~Vinod
> ---
>  drivers/dma/sirf-dma.c |   13 ++++++++++++-
>  1 files changed, 12 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
> index 1d627e2..c35fa34 100644
> --- a/drivers/dma/sirf-dma.c
> +++ b/drivers/dma/sirf-dma.c
> @@ -742,7 +742,18 @@ static struct platform_driver sirfsoc_dma_driver = {
>  	},
>  };
>  
> -module_platform_driver(sirfsoc_dma_driver);
> +static __init int sirfsoc_dma_init(void)
> +{
> +	return platform_driver_register(&sirfsoc_dma_driver);
> +}
> +
> +static void __exit sirfsoc_dma_exit(void)
> +{
> +	platform_driver_unregister(&sirfsoc_dma_driver);
> +}
> +
> +subsys_initcall(sirfsoc_dma_init);
> +module_exit(sirfsoc_dma_exit);
>  
>  MODULE_AUTHOR("Rongjun Ying <rongjun.ying at csr.com>, "
>  	"Barry Song <baohua.song at csr.com>");
> -- 
> 1.7.5.4
> 
> 
> 
> Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
> More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From shc_work at mail.ru  Thu May  2 12:03:16 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Thu,  2 May 2013 20:03:16 +0400
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
Message-ID: <1367510596-27780-1-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f..8d17a0d 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 	supplies->dev_name = dev_id;
 
 	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
-	if (!reg_data)
+	if (!reg_data) {
+		kfree(supplies);
 		return -ENOMEM;
+	}
 
 	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
 	reg_data->consumer_supplies = supplies;
@@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 
 	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
 			GFP_KERNEL);
-	if (!config)
+	if (!config) {
+		kfree(supplies);
+		kfree(reg_data);
 		return -ENOMEM;
+	}
 
 	config->supply_name = name;
 	config->gpio = gpio;
@@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 
 	/* create a regulator device */
 	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-	if (!pdev)
+	if (!pdev) {
+		kfree(supplies);
+		kfree(reg_data);
+		kfree(config);
 		return -ENOMEM;
+	}
 
 	pdev->id = PLATFORM_DEVID_AUTO;
 	pdev->name = reg_name;
 	pdev->dev.platform_data = config;
 
 	ret = platform_device_register(pdev);
-	if (ret)
+	if (ret) {
 		pr_err("%s: Failed registering regulator %s for %s\n",
 				__func__, name, dev_id);
+		kfree(supplies);
+		kfree(reg_data);
+		kfree(config);
+	}
 
 	return ret;
 }
-- 
1.8.1.5



From catalin.marinas at arm.com  Thu May  2 12:09:07 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 2 May 2013 17:09:07 +0100
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130502160906.GI20730@arm.com>

On Mon, Apr 08, 2013 at 05:17:26PM +0100, Marc Zyngier wrote:
>  static inline bool kvm_vcpu_reg_is_pc(const struct kvm_vcpu *vcpu, int reg)
>  {
> -	return false;
> +	return (vcpu_mode_is_32bit(vcpu)) && reg == 15;
>  }

On AArch64, would ESR_EL2 have SRT == 15 when the source/destination
register is PC? The mapping between AArch32 and AArch64 registers
suggests R13_hyp. Maybe 15 is correct but it's not clear to me from the
spec.

BTW, on arch/arm it looks like this is used when you get a data abort
with PC as the destination register and you inject a prefetch abort in
this case. Why isn't this a normal data abort? Once you get the
information, you load it into PC but first you need to sort out the data
abort (unless I don't understand how the kvm_inject_pabt works).

-- 
Catalin


From linus.walleij at stericsson.com  Thu May  2 12:16:48 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:48 +0200
Subject: [PATCH 0/7] ARM: u300 multiplatform support
Message-ID: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This series builds on top of the recently iterated U300
device tree support to convert the platform to multiplatform
(a.k.a. single zImage).

This is intended to be pulled on top of the DT support.

Linus Walleij (7):
  ARM: u300: push down syscon registers
  ARM: u300: remove deps from debug macro
  ARM: u300: delete <mach/hardware.h>
  ARM: u300: delete <mach/irqs.h>
  ARM: u300: localize <mach/u300-regs.h>
  ARM: u300: convert to multiplatform
  ARM: u300: delete remnant machine headers

 arch/arm/Kconfig                                  |  21 +-
 arch/arm/configs/u300_defconfig                   |  11 +-
 arch/arm/include/debug/u300.S                     |   9 +-
 arch/arm/mach-u300/Kconfig                        |  31 +-
 arch/arm/mach-u300/core.c                         |  29 +-
 arch/arm/mach-u300/include/mach/hardware.h        |   5 -
 arch/arm/mach-u300/include/mach/irqs.h            |  80 ---
 arch/arm/mach-u300/include/mach/syscon.h          | 592 ----------------------
 arch/arm/mach-u300/include/mach/timex.h           |  17 -
 arch/arm/mach-u300/include/mach/uncompress.h      |  45 --
 arch/arm/mach-u300/regulator.c                    |   9 +-
 arch/arm/mach-u300/timer.c                        |   3 -
 arch/arm/mach-u300/{include/mach => }/u300-regs.h |   0
 drivers/clk/clk-u300.c                            | 343 ++++++++++++-
 14 files changed, 407 insertions(+), 788 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-u300/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-u300/include/mach/syscon.h
 delete mode 100644 arch/arm/mach-u300/include/mach/timex.h
 delete mode 100644 arch/arm/mach-u300/include/mach/uncompress.h
 rename arch/arm/mach-u300/{include/mach => }/u300-regs.h (100%)

-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:51 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:51 +0200
Subject: [PATCH 3/7] ARM: u300: delete <mach/hardware.h>
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-4-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This file is now unused and can be deleted.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/hardware.h | 5 -----
 arch/arm/mach-u300/timer.c                 | 1 -
 2 files changed, 6 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/hardware.h

diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce..0000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/hardware.h
- */
-#include <asm/sizes.h>
-#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 564e32d..2e622f9 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -22,7 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/hardware.h>
 #include <mach/irqs.h>
 
 /* Generic stuff */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:50 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:50 +0200
Subject: [PATCH 2/7] ARM: u300: remove deps from debug macro
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-3-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This rids the dependency to <mach/hardware.h> (which is an
implicit dependency to <mach/u300-regs.h>) from the U300
debug macro. Take this opportunity to update the file
header.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/include/debug/u300.S | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S
index 8ae8e4a..6f04f08 100644
--- a/arch/arm/include/debug/u300.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
 /*
- *
- * arch-arm/mach-u300/include/mach/debug-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2013 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Debugging macro include header.
  * Author: Linus Walleij <linus.walleij at stericsson.com>
  */
-#include <mach/hardware.h>
+#define U300_SLOW_PER_PHYS_BASE		0xc0010000
+#define U300_SLOW_PER_VIRT_BASE		0xff000000
 
 	.macro	addruart, rp, rv, tmp
 	/* If we move the address using MMU, use this. */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:49 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:49 +0200
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-2-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Get rid of the <mach/syscon.h> header as a prerequisite for
multiplatform support. Do this by pushing the registers down
to their respective drivers and deleting the unused remainder.

Cc: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Mike: I'm seeking an ACK for this to take it through the
ARM SoC tree alongside the big bowl of DT enablement patches.
---
 arch/arm/mach-u300/core.c                |  26 +-
 arch/arm/mach-u300/include/mach/syscon.h | 592 -------------------------------
 arch/arm/mach-u300/regulator.c           |   9 +-
 drivers/clk/clk-u300.c                   | 343 +++++++++++++++++-
 4 files changed, 373 insertions(+), 597 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/syscon.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index ff99e26..9a46426 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -26,11 +26,35 @@
 #include <asm/mach/arch.h>
 
 #include <mach/u300-regs.h>
-#include <mach/syscon.h>
 
 #include "timer.h"
 
 /*
+ * SYSCON addresses applicable to the core machine.
+ */
+
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR					(0x400)
+/* SMCR */
+#define U300_SYSCON_SMCR					(0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK				(0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND			(0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE			(0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE		(0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR					(0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE			(0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR						(0x4f8)
+#define U300_SYSCON_PCR_SERV_IND				(0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR						(0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND		(0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND		(0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
+
+/*
  * Static I/O mappings that are needed for booting the U300 platforms. The
  * only things we need are the areas where we find the timer, syscon and
  * intcon, since the remaining device drivers will map their own memory
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0b..0000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/syscon.h
- *
- *
- * Copyright (C) 2008-2012 ST-Ericsson AB
- *
- * Author: Rickard Andersson <rickard.andersson at stericsson.com>
- */
-
-#ifndef __MACH_SYSCON_H
-#define __MACH_SYSCON_H
-
-/*
- * All register defines for SYSCON registers that concerns individual
- * block clocks and reset lines are registered here. This is because
- * we don't want any other file to try to fool around with this stuff.
- */
-
-/* APP side SYSCON registers */
-/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
-/* CLK Control Register 16bit (R/W) */
-#define U300_SYSCON_CCR						(0x0000)
-#define U300_SYSCON_CCR_I2S1_USE_VCXO				(0x0040)
-#define U300_SYSCON_CCR_I2S0_USE_VCXO				(0x0020)
-#define U300_SYSCON_CCR_TURN_VCXO_ON				(0x0008)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK			(0x0007)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER		(0x04)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW			(0x03)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE		(0x02)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH			(0x01)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST			(0x00)
-/* CLK Status Register 16bit (R/W) */
-#define U300_SYSCON_CSR						(0x0004)
-#define U300_SYSCON_CSR_PLL208_LOCK_IND				(0x0002)
-#define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
-/* Reset lines for SLOW devices 16bit (R/W) */
-#define U300_SYSCON_RSR						(0x0014)
-#define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
-#define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
-#define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
-#define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
-#define U300_SYSCON_RSR_KEYPAD_RESET_EN				(0x0020)
-#define U300_SYSCON_RSR_GPIO_RESET_EN				(0x0010)
-#define U300_SYSCON_RSR_EH_RESET_EN				(0x0008)
-#define U300_SYSCON_RSR_BTR_RESET_EN				(0x0004)
-#define U300_SYSCON_RSR_UART_RESET_EN				(0x0002)
-#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
-/* Reset lines for FAST devices 16bit (R/W) */
-#define U300_SYSCON_RFR						(0x0018)
-#define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
-#define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
-#define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
-#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
-#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE			(0x0008)
-#define U300_SYSCON_RFR_I2C1_RESET_ENABLE			(0x0004)
-#define U300_SYSCON_RFR_I2C0_RESET_ENABLE			(0x0002)
-#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
-/* Reset lines for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_RRR						(0x001c)
-#define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
-#define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
-#define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
-#define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
-#define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
-#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN			(0x0080)
-#define U300_SYSCON_RRR_NANDIF_RESET_EN				(0x0040)
-#define U300_SYSCON_RRR_EMIF_RESET_EN				(0x0020)
-#define U300_SYSCON_RRR_DMAC_RESET_EN				(0x0010)
-#define U300_SYSCON_RRR_CPU_RESET_EN				(0x0008)
-#define U300_SYSCON_RRR_APEX_RESET_EN				(0x0004)
-#define U300_SYSCON_RRR_AHB_RESET_EN				(0x0002)
-#define U300_SYSCON_RRR_AAIF_RESET_EN				(0x0001)
-/* Clock enable for SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CESR					(0x0020)
-#define U300_SYSCON_CESR_PPM_CLK_EN				(0x0200)
-#define U300_SYSCON_CESR_ACC_TMR_CLK_EN				(0x0100)
-#define U300_SYSCON_CESR_APP_TMR_CLK_EN				(0x0080)
-#define U300_SYSCON_CESR_KEYPAD_CLK_EN				(0x0040)
-#define U300_SYSCON_CESR_GPIO_CLK_EN				(0x0010)
-#define U300_SYSCON_CESR_EH_CLK_EN				(0x0008)
-#define U300_SYSCON_CESR_BTR_CLK_EN				(0x0004)
-#define U300_SYSCON_CESR_UART_CLK_EN				(0x0002)
-#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN			(0x0001)
-/* Clock enable for FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CEFR					(0x0024)
-#define U300_SYSCON_CEFR_UART1_CLK_EN				(0x0200)
-#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN			(0x0100)
-#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN			(0x0080)
-#define U300_SYSCON_CEFR_SPI_CLK_EN				(0x0040)
-#define U300_SYSCON_CEFR_MMC_CLK_EN				(0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN				(0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN				(0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN				(0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN				(0x0002)
-#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN			(0x0001)
-/* Clock enable for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CERR					(0x0028)
-#define U300_SYSCON_CERR_CDS_CLK_EN				(0x2000)
-#define U300_SYSCON_CERR_ISP_CLK_EN				(0x1000)
-#define U300_SYSCON_CERR_MSPRO_CLK_EN				(0x0800)
-#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN		(0x0400)
-#define U300_SYSCON_CERR_SEMI_CLK_EN				(0x0200)
-#define U300_SYSCON_CERR_XGAM_CLK_EN				(0x0100)
-#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN			(0x0080)
-#define U300_SYSCON_CERR_NANDIF_CLK_EN				(0x0040)
-#define U300_SYSCON_CERR_EMIF_CLK_EN				(0x0020)
-#define U300_SYSCON_CERR_DMAC_CLK_EN				(0x0010)
-#define U300_SYSCON_CERR_CPU_CLK_EN				(0x0008)
-#define U300_SYSCON_CERR_APEX_CLK_EN				(0x0004)
-#define U300_SYSCON_CERR_AHB_CLK_EN				(0x0002)
-#define U300_SYSCON_CERR_AAIF_CLK_EN				(0x0001)
-/* Single block clock enable 16bit (-/W) */
-#define U300_SYSCON_SBCER					(0x002c)
-#define U300_SYSCON_SBCER_PPM_CLK_EN				(0x0009)
-#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN			(0x0008)
-#define U300_SYSCON_SBCER_APP_TMR_CLK_EN			(0x0007)
-#define U300_SYSCON_SBCER_KEYPAD_CLK_EN				(0x0006)
-#define U300_SYSCON_SBCER_GPIO_CLK_EN				(0x0004)
-#define U300_SYSCON_SBCER_EH_CLK_EN				(0x0003)
-#define U300_SYSCON_SBCER_BTR_CLK_EN				(0x0002)
-#define U300_SYSCON_SBCER_UART_CLK_EN				(0x0001)
-#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN			(0x0000)
-#define U300_SYSCON_SBCER_UART1_CLK_EN				(0x0019)
-#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN			(0x0018)
-#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN			(0x0017)
-#define U300_SYSCON_SBCER_SPI_CLK_EN				(0x0016)
-#define U300_SYSCON_SBCER_MMC_CLK_EN				(0x0015)
-#define U300_SYSCON_SBCER_I2S1_CLK_EN				(0x0014)
-#define U300_SYSCON_SBCER_I2S0_CLK_EN				(0x0013)
-#define U300_SYSCON_SBCER_I2C1_CLK_EN				(0x0012)
-#define U300_SYSCON_SBCER_I2C0_CLK_EN				(0x0011)
-#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN			(0x0010)
-#define U300_SYSCON_SBCER_CDS_CLK_EN				(0x002D)
-#define U300_SYSCON_SBCER_ISP_CLK_EN				(0x002C)
-#define U300_SYSCON_SBCER_MSPRO_CLK_EN				(0x002B)
-#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN		(0x002A)
-#define U300_SYSCON_SBCER_SEMI_CLK_EN				(0x0029)
-#define U300_SYSCON_SBCER_XGAM_CLK_EN				(0x0028)
-#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN			(0x0027)
-#define U300_SYSCON_SBCER_NANDIF_CLK_EN				(0x0026)
-#define U300_SYSCON_SBCER_EMIF_CLK_EN				(0x0025)
-#define U300_SYSCON_SBCER_DMAC_CLK_EN				(0x0024)
-#define U300_SYSCON_SBCER_CPU_CLK_EN				(0x0023)
-#define U300_SYSCON_SBCER_APEX_CLK_EN				(0x0022)
-#define U300_SYSCON_SBCER_AHB_CLK_EN				(0x0021)
-#define U300_SYSCON_SBCER_AAIF_CLK_EN				(0x0020)
-/* Single block clock disable 16bit (-/W) */
-#define U300_SYSCON_SBCDR					(0x0030)
-/* Same values as above for SBCER */
-/* Clock force SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CFSR					(0x003c)
-#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN			(0x0200)
-#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN			(0x0100)
-#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN			(0x0080)
-#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN			(0x0020)
-#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN			(0x0010)
-#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN			(0x0008)
-#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN			(0x0004)
-#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN			(0x0002)
-#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN		(0x0001)
-/* Clock force FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CFFR					(0x40)
-/* Values not defined. Define if you want to use them. */
-/* Clock force the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CFRR					(0x44)
-#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN			(0x2000)
-#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN			(0x1000)
-#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN			(0x0800)
-#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN		(0x0400)
-#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN			(0x0200)
-#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN			(0x0100)
-#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN			(0x0080)
-#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN			(0x0040)
-#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN			(0x0020)
-#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN			(0x0010)
-#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN			(0x0008)
-#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN			(0x0004)
-#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN			(0x0002)
-#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN			(0x0001)
-/* PLL208 Frequency Control 16bit (R/W) */
-#define U300_SYSCON_PFCR					(0x48)
-#define U300_SYSCON_PFCR_DPLL_MULT_NUM				(0x000F)
-/* Power Management Control 16bit (R/W) */
-#define U300_SYSCON_PMCR					(0x50)
-#define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
-#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
-/*
- * All other clocking registers moved to clock.c!
- */
-/* Reset Out 16bit (R/W) */
-#define U300_SYSCON_RCR						(0x6c)
-#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE			(0x0001)
-/* EMIF Slew Rate Control 16bit (R/W) */
-#define U300_SYSCON_SRCLR					(0x70)
-#define U300_SYSCON_SRCLR_MASK					(0x03FF)
-#define U300_SYSCON_SRCLR_VALUE					(0x03FF)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B			(0x0200)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A			(0x0100)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B			(0x0080)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A			(0x0040)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B			(0x0020)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A			(0x0010)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B			(0x0008)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A			(0x0004)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B			(0x0002)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A			(0x0001)
-/* EMIF Clock Control Register 16bit (R/W) */
-#define U300_SYSCON_ECCR					(0x0078)
-#define U300_SYSCON_ECCR_MASK					(0x000F)
-#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE		(0x0008)
-#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE	(0x0004)
-#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE		(0x0002)
-#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE		(0x0001)
-/* Step one for killing the applications system 16bit (-/W) */
-#define U300_SYSCON_KA1R					(0x0080)
-#define U300_SYSCON_KA1R_MASK					(0xFFFF)
-#define U300_SYSCON_KA1R_VALUE					(0xFFFF)
-/* Step two for killing the application system 16bit (-/W) */
-#define U300_SYSCON_KA2R					(0x0084)
-#define U300_SYSCON_KA2R_MASK					(0xFFFF)
-#define U300_SYSCON_KA2R_VALUE					(0xFFFF)
-/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
-#define U300_SYSCON_MMF0R					(0x90)
-#define U300_SYSCON_MMF0R_MASK					(0x00FF)
-#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK			(0x00F0)
-#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK			(0x000F)
-/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
-#define U300_SYSCON_MMF1R					(0x94)
-#define U300_SYSCON_MMF1R_MASK					(0x00FF)
-#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK			(0x00F0)
-#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK			(0x000F)
-/* AAIF control register 16 bit (R/W) */
-#define U300_SYSCON_AAIFCR					(0x98)
-#define U300_SYSCON_AAIFCR_MASK					(0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK			(0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL			(0x0000)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING			(0x0001)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT			(0x0002)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT			(0x0003)
-/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
-#define U300_SYSCON_MMCR					(0x9C)
-#define U300_SYSCON_MMCR_MASK					(0x0003)
-#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE			(0x0002)
-#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE			(0x0001)
-/* Pull up/down control (R/W) */
-#define U300_SYSCON_PUCR					(0x104)
-#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE		(0x0200)
-#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE		(0x0100)
-#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE			(0x0080)
-#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE			(0x0040)
-#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK			(0x003F)
-/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
-#define U300_SYSCON_S0CCR					(0x120)
-#define U300_SYSCON_S0CCR_FIELD_MASK				(0x43FF)
-#define U300_SYSCON_S0CCR_CLOCK_REQ				(0x4000)
-#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR			(0x2000)
-#define U300_SYSCON_S0CCR_CLOCK_INV				(0x0200)
-#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK			(0x01E0)
-#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK			(0x001E)
-#define U300_SYSCON_S0CCR_CLOCK_ENABLE				(0x0001)
-#define U300_SYSCON_S0CCR_SEL_MCLK				(0x8<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK			(0xA<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK			(0xC<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK			(0xD<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK			(0x0<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK			(0x2<<1)
-#define U300_SYSCON_S0CCR_SEL_RTC_CLK				(0x4<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK			(0x6<<1)
-/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
-#define U300_SYSCON_S1CCR					(0x124)
-#define U300_SYSCON_S1CCR_FIELD_MASK				(0x43FF)
-#define U300_SYSCON_S1CCR_CLOCK_REQ				(0x4000)
-#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR			(0x2000)
-#define U300_SYSCON_S1CCR_CLOCK_INV				(0x0200)
-#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK			(0x01E0)
-#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK			(0x001E)
-#define U300_SYSCON_S1CCR_CLOCK_ENABLE				(0x0001)
-#define U300_SYSCON_S1CCR_SEL_MCLK				(0x8<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK			(0xA<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK			(0xC<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK			(0xD<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK			(0x2<<1)
-#define U300_SYSCON_S1CCR_SEL_RTC_CLK				(0x4<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK			(0x6<<1)
-/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
-#define U300_SYSCON_S2CCR					(0x128)
-#define U300_SYSCON_S2CCR_FIELD_MASK				(0xC3FF)
-#define U300_SYSCON_S2CCR_CLK_STEAL				(0x8000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ				(0x4000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR			(0x2000)
-#define U300_SYSCON_S2CCR_CLOCK_INV				(0x0200)
-#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK			(0x01E0)
-#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK			(0x001E)
-#define U300_SYSCON_S2CCR_CLOCK_ENABLE				(0x0001)
-#define U300_SYSCON_S2CCR_SEL_MCLK				(0x8<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK			(0xA<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK			(0xC<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK			(0xD<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK			(0x2<<1)
-#define U300_SYSCON_S2CCR_SEL_RTC_CLK				(0x4<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK			(0x6<<1)
-/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
-#define U300_SYSCON_MCR						(0x12c)
-#define U300_SYSCON_MCR_FIELD_MASK				(0x00FF)
-#define U300_SYSCON_MCR_PMGEN_CR_4_MASK				(0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO				(0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_4_SPI				(0x0040)
-#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF				(0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_2_MASK				(0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO				(0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC		(0x0010)
-#define U300_SYSCON_MCR_PMGEN_CR_2_DSP				(0x0020)
-#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF				(0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_0_MASK				(0x000C)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1		(0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2		(0x0004)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3		(0x0008)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM			(0x000C)
-#define U300_SYSCON_MCR_PM1G_MODE_ENABLE			(0x0002)
-#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE			(0x0001)
-/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
-#define U300_SYSCON_PICR					(0x0130)
-#define U300_SYSCON_PICR_MASK					(0x00FF)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE		(0x0080)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE		(0x0040)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE		(0x0020)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE		(0x0010)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE		(0x0008)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE		(0x0004)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE		(0x0002)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE		(0x0001)
-/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
-#define U300_SYSCON_PISR					(0x0134)
-#define U300_SYSCON_PISR_MASK					(0x000F)
-#define U300_SYSCON_PISR_PLL13_UNLOCK_IND			(0x0008)
-#define U300_SYSCON_PISR_PLL13_LOCK_IND				(0x0004)
-#define U300_SYSCON_PISR_PLL208_UNLOCK_IND			(0x0002)
-#define U300_SYSCON_PISR_PLL208_LOCK_IND			(0x0001)
-/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
-#define U300_SYSCON_PICLR					(0x0138)
-#define U300_SYSCON_PICLR_MASK					(0x000F)
-#define U300_SYSCON_PICLR_RWMASK				(0x0000)
-#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC			(0x0008)
-#define U300_SYSCON_PICLR_PLL13_LOCK_SC				(0x0004)
-#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC			(0x0002)
-#define U300_SYSCON_PICLR_PLL208_LOCK_SC			(0x0001)
-/* CAMIF_CONTROL 16 bit (-/W) */
-#define U300_SYSCON_CICR					(0x013C)
-#define U300_SYSCON_CICR_MASK					(0x0FFF)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK		(0x0F00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1		(0x0C00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0		(0x0300)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK		(0x00F0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1		(0x00C0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0		(0x0030)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK		(0x000F)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1		(0x000C)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0		(0x0003)
-/* Clock activity observability register 0 */
-#define U300_SYSCON_C0OAR					(0x140)
-#define U300_SYSCON_C0OAR_MASK					(0xFFFF)
-#define U300_SYSCON_C0OAR_VALUE					(0xFFFF)
-#define U300_SYSCON_C0OAR_BT_H_CLK				(0x8000)
-#define U300_SYSCON_C0OAR_ASPB_P_CLK				(0x4000)
-#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK			(0x2000)
-#define U300_SYSCON_C0OAR_APP_SEMI_CLK				(0x1000)
-#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK			(0x0800)
-#define U300_SYSCON_C0OAR_APP_I2S1_CLK				(0x0400)
-#define U300_SYSCON_C0OAR_APP_I2S0_CLK				(0x0200)
-#define U300_SYSCON_C0OAR_APP_CPU_CLK				(0x0100)
-#define U300_SYSCON_C0OAR_APP_52_CLK				(0x0080)
-#define U300_SYSCON_C0OAR_APP_208_CLK				(0x0040)
-#define U300_SYSCON_C0OAR_APP_104_CLK				(0x0020)
-#define U300_SYSCON_C0OAR_APEX_CLK				(0x0010)
-#define U300_SYSCON_C0OAR_AHPB_M_H_CLK				(0x0008)
-#define U300_SYSCON_C0OAR_AHB_CLK				(0x0004)
-#define U300_SYSCON_C0OAR_AFPB_P_CLK				(0x0002)
-#define U300_SYSCON_C0OAR_AAIF_CLK				(0x0001)
-/* Clock activity observability register 1 */
-#define U300_SYSCON_C1OAR					(0x144)
-#define U300_SYSCON_C1OAR_MASK					(0x3FFE)
-#define U300_SYSCON_C1OAR_VALUE					(0x3FFE)
-#define U300_SYSCON_C1OAR_NFIF_F_CLK				(0x2000)
-#define U300_SYSCON_C1OAR_MSPRO_CLK				(0x1000)
-#define U300_SYSCON_C1OAR_MMC_P_CLK				(0x0800)
-#define U300_SYSCON_C1OAR_MMC_CLK				(0x0400)
-#define U300_SYSCON_C1OAR_KP_P_CLK				(0x0200)
-#define U300_SYSCON_C1OAR_I2C1_P_CLK				(0x0100)
-#define U300_SYSCON_C1OAR_I2C0_P_CLK				(0x0080)
-#define U300_SYSCON_C1OAR_GPIO_CLK				(0x0040)
-#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK				(0x0020)
-#define U300_SYSCON_C1OAR_EMIF_H_CLK				(0x0010)
-#define U300_SYSCON_C1OAR_EVHIST_CLK				(0x0008)
-#define U300_SYSCON_C1OAR_PPM_CLK				(0x0004)
-#define U300_SYSCON_C1OAR_DMA_CLK				(0x0002)
-/* Clock activity observability register 2 */
-#define U300_SYSCON_C2OAR					(0x148)
-#define U300_SYSCON_C2OAR_MASK					(0x0FFF)
-#define U300_SYSCON_C2OAR_VALUE					(0x0FFF)
-#define U300_SYSCON_C2OAR_XGAM_CDI_CLK				(0x0800)
-#define U300_SYSCON_C2OAR_XGAM_CLK				(0x0400)
-#define U300_SYSCON_C2OAR_VC_H_CLK				(0x0200)
-#define U300_SYSCON_C2OAR_VC_CLK				(0x0100)
-#define U300_SYSCON_C2OAR_UA_P_CLK				(0x0080)
-#define U300_SYSCON_C2OAR_TMR1_CLK				(0x0040)
-#define U300_SYSCON_C2OAR_TMR0_CLK				(0x0020)
-#define U300_SYSCON_C2OAR_SPI_P_CLK				(0x0010)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK			(0x0008)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CLK				(0x0004)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK			(0x0002)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CLK				(0x0001)
-
-/* Chip ID register 16bit (R/-) */
-#define U300_SYSCON_CIDR					(0x400)
-/* Video IRQ clear 16bit (R/W) */
-#define U300_SYSCON_VICR					(0x404)
-#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE		(0x0002)
-#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE		(0x0001)
-/* SMCR */
-#define U300_SYSCON_SMCR					(0x4d0)
-#define U300_SYSCON_SMCR_FIELD_MASK				(0x000e)
-#define U300_SYSCON_SMCR_SEMI_SREFACK_IND			(0x0008)
-#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE			(0x0004)
-#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE		(0x0002)
-/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
-#define U300_SYSCON_CSDR					(0x4f0)
-#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE			(0x0001)
-/* PRINT_CONTROL Print Control 16bit (R/-) */
-#define U300_SYSCON_PCR						(0x4f8)
-#define U300_SYSCON_PCR_SERV_IND				(0x0001)
-/* BOOT_CONTROL 16bit (R/-) */
-#define U300_SYSCON_BCR						(0x4fc)
-#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND		(0x0400)
-#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND		(0x0200)
-#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
-#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
-
-
-/* CPU clock defines */
-/**
- * CPU high frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_HIGH    208
-/**
- * CPU medium frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_MEDIUM   52
-/**
- * CPU low frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_LOW      13
-
-/* EMIF clock defines */
-/**
- * EMIF high frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_HIGH   104
-/**
- * EMIF medium frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_MEDIUM  52
-/**
- * EMIF low frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_LOW     13
-
-/* AHB clock defines */
-/**
- * AHB high frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_HIGH     52
-/**
- * AHB medium frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_MEDIUM   26
-/**
- * AHB low frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_LOW       7  /* i.e 13/2=6.5MHz */
-
-enum syscon_busmaster {
-  SYSCON_BM_DMAC,
-  SYSCON_BM_XGAM,
-  SYSCON_BM_VIDEO_ENC
-};
-
-/* Selectr a resistor or a set of resistors */
-enum syscon_pull_up_down {
-  SYSCON_PU_KEY_IN_EN,
-  SYSCON_PU_EMIF_1_8_BIT_EN,
-  SYSCON_PU_EMIF_1_16_BIT_EN,
-  SYSCON_PU_EMIF_1_NFIF_READY_EN,
-  SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
-};
-
-/*
- * Note that this array must match the order of the array "clk_reg"
- * in syscon.c
- */
-enum syscon_clk {
-  SYSCON_CLKCONTROL_SLOW_BRIDGE,
-  SYSCON_CLKCONTROL_UART,
-  SYSCON_CLKCONTROL_BTR,
-  SYSCON_CLKCONTROL_EH,
-  SYSCON_CLKCONTROL_GPIO,
-  SYSCON_CLKCONTROL_KEYPAD,
-  SYSCON_CLKCONTROL_APP_TIMER,
-  SYSCON_CLKCONTROL_ACC_TIMER,
-  SYSCON_CLKCONTROL_FAST_BRIDGE,
-  SYSCON_CLKCONTROL_I2C0,
-  SYSCON_CLKCONTROL_I2C1,
-  SYSCON_CLKCONTROL_I2S0,
-  SYSCON_CLKCONTROL_I2S1,
-  SYSCON_CLKCONTROL_MMC,
-  SYSCON_CLKCONTROL_SPI,
-  SYSCON_CLKCONTROL_I2S0_CORE,
-  SYSCON_CLKCONTROL_I2S1_CORE,
-  SYSCON_CLKCONTROL_UART1,
-  SYSCON_CLKCONTROL_AAIF,
-  SYSCON_CLKCONTROL_AHB,
-  SYSCON_CLKCONTROL_APEX,
-  SYSCON_CLKCONTROL_CPU,
-  SYSCON_CLKCONTROL_DMA,
-  SYSCON_CLKCONTROL_EMIF,
-  SYSCON_CLKCONTROL_NAND_IF,
-  SYSCON_CLKCONTROL_VIDEO_ENC,
-  SYSCON_CLKCONTROL_XGAM,
-  SYSCON_CLKCONTROL_SEMI,
-  SYSCON_CLKCONTROL_AHB_SUBSYS,
-  SYSCON_CLKCONTROL_MSPRO
-};
-
-enum syscon_sysclk_mode {
-  SYSCON_SYSCLK_DISABLED,
-  SYSCON_SYSCLK_M_CLK,
-  SYSCON_SYSCLK_ACC_FSM,
-  SYSCON_SYSCLK_PLL60_48,
-  SYSCON_SYSCLK_PLL60_60,
-  SYSCON_SYSCLK_ACC_PLL208,
-  SYSCON_SYSCLK_APP_PLL13,
-  SYSCON_SYSCLK_APP_FSM,
-  SYSCON_SYSCLK_RTC,
-  SYSCON_SYSCLK_APP_PLL208
-};
-
-enum syscon_sysclk_req {
-  SYSCON_SYSCLKREQ_DISABLED,
-  SYSCON_SYSCLKREQ_ACTIVE_LOW,
-  SYSCON_SYSCLKREQ_MONITOR
-};
-
-enum syscon_clk_mode {
-  SYSCON_CLKMODE_OFF,
-  SYSCON_CLKMODE_DEFAULT,
-  SYSCON_CLKMODE_LOW,
-  SYSCON_CLKMODE_MEDIUM,
-  SYSCON_CLKMODE_HIGH,
-  SYSCON_CLKMODE_PERMANENT,
-  SYSCON_CLKMODE_ON,
-};
-
-enum syscon_call_mode {
-  SYSCON_CLKCALL_NOWAIT,
-  SYSCON_CLKCALL_WAIT,
-};
-
-int syscon_dc_on(bool keep_power_on);
-int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
-				      bool active);
-bool syscon_get_busmaster_active_state(void);
-int syscon_set_sleep_mask(enum syscon_clk,
-			  bool sleep_ctrl);
-int syscon_config_sysclk(u32 sysclk,
-			 enum syscon_sysclk_mode sysclkmode,
-			 bool inverse,
-			 u32 divisor,
-			 enum syscon_sysclk_req sysclkreq);
-bool syscon_can_turn_off_semi_clock(void);
-
-/* This function is restricted to core.c */
-int syscon_request_normal_power(bool req);
-
-/* This function is restricted to be used by platform_speed.c */
-int syscon_speed_request(enum syscon_call_mode wait_mode,
-			 enum syscon_clk_mode req_clk_mode);
-#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index bbda954..ab7d7a5 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,9 +17,12 @@
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
 #include <linux/io.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/syscon.h>
+#include <mach/u300-regs.h>
+
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR					(0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
 
 /*
  * Regulators that power the board and chip and which are
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f792..a41e42e 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,348 @@
 #include <linux/io.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
-#include <mach/syscon.h>
+
+/* APP side SYSCON registers */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR						(0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO				(0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO				(0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON				(0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK			(0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER		(0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW			(0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE		(0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH			(0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST			(0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR						(0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND				(0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR						(0x0014)
+#define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN				(0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN				(0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN				(0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN				(0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN				(0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR						(0x0018)
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE			(0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE			(0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE			(0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR						(0x001c)
+#define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
+#define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN			(0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN				(0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN				(0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN				(0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN				(0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN				(0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN				(0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN				(0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR					(0x0020)
+#define U300_SYSCON_CESR_PPM_CLK_EN				(0x0200)
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN				(0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN				(0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN				(0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN				(0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN				(0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN				(0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN				(0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN			(0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR					(0x0024)
+#define U300_SYSCON_CEFR_UART1_CLK_EN				(0x0200)
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN			(0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN			(0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN				(0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN				(0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN				(0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN				(0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN				(0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN				(0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN			(0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR					(0x0028)
+#define U300_SYSCON_CERR_CDS_CLK_EN				(0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN				(0x1000)
+#define U300_SYSCON_CERR_MSPRO_CLK_EN				(0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN		(0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN				(0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN				(0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN			(0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN				(0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN				(0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN				(0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN				(0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN				(0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN				(0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN				(0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER					(0x002c)
+#define U300_SYSCON_SBCER_PPM_CLK_EN				(0x0009)
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN			(0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN			(0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN				(0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN				(0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN				(0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN				(0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN				(0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN			(0x0000)
+#define U300_SYSCON_SBCER_UART1_CLK_EN				(0x0019)
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN			(0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN			(0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN				(0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN				(0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN				(0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN				(0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN				(0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN				(0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN			(0x0010)
+#define U300_SYSCON_SBCER_CDS_CLK_EN				(0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN				(0x002C)
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN				(0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN		(0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN				(0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN				(0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN			(0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN				(0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN				(0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN				(0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN				(0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN				(0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN				(0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN				(0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR					(0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR					(0x003c)
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN			(0x0200)
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN			(0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN			(0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN			(0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN			(0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN			(0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN			(0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN			(0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN		(0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR					(0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR					(0x44)
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN			(0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN			(0x1000)
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN			(0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN		(0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN			(0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN			(0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN			(0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN			(0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN			(0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN			(0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN			(0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN			(0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN			(0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN			(0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR					(0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM				(0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR					(0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR						(0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE			(0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR					(0x70)
+#define U300_SYSCON_SRCLR_MASK					(0x03FF)
+#define U300_SYSCON_SRCLR_VALUE					(0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B			(0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A			(0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B			(0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A			(0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B			(0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A			(0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B			(0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A			(0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B			(0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A			(0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR					(0x0078)
+#define U300_SYSCON_ECCR_MASK					(0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE		(0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE	(0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE		(0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE		(0x0001)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R					(0x90)
+#define U300_SYSCON_MMF0R_MASK					(0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK			(0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK			(0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R					(0x94)
+#define U300_SYSCON_MMF1R_MASK					(0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK			(0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK			(0x000F)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR					(0x9C)
+#define U300_SYSCON_MMCR_MASK					(0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE			(0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE			(0x0001)
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR					(0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK				(0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ				(0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR			(0x2000)
+#define U300_SYSCON_S0CCR_CLOCK_INV				(0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK			(0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK			(0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE				(0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK				(0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK			(0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK			(0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK			(0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK			(0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK			(0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK				(0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK			(0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR					(0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK				(0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ				(0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR			(0x2000)
+#define U300_SYSCON_S1CCR_CLOCK_INV				(0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK			(0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK			(0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE				(0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK				(0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK			(0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK			(0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK			(0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK			(0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK				(0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK			(0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR					(0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK				(0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL				(0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ				(0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR			(0x2000)
+#define U300_SYSCON_S2CCR_CLOCK_INV				(0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK			(0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK			(0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE				(0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK				(0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK			(0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK			(0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK			(0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK			(0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK				(0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK			(0x6<<1)
+/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
+#define U300_SYSCON_PICR					(0x0130)
+#define U300_SYSCON_PICR_MASK					(0x00FF)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE		(0x0080)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE		(0x0040)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE		(0x0020)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE		(0x0010)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE		(0x0008)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE		(0x0004)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE		(0x0002)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE		(0x0001)
+/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
+#define U300_SYSCON_PISR					(0x0134)
+#define U300_SYSCON_PISR_MASK					(0x000F)
+#define U300_SYSCON_PISR_PLL13_UNLOCK_IND			(0x0008)
+#define U300_SYSCON_PISR_PLL13_LOCK_IND				(0x0004)
+#define U300_SYSCON_PISR_PLL208_UNLOCK_IND			(0x0002)
+#define U300_SYSCON_PISR_PLL208_LOCK_IND			(0x0001)
+/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
+#define U300_SYSCON_PICLR					(0x0138)
+#define U300_SYSCON_PICLR_MASK					(0x000F)
+#define U300_SYSCON_PICLR_RWMASK				(0x0000)
+#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC			(0x0008)
+#define U300_SYSCON_PICLR_PLL13_LOCK_SC				(0x0004)
+#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC			(0x0002)
+#define U300_SYSCON_PICLR_PLL208_LOCK_SC			(0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR					(0x140)
+#define U300_SYSCON_C0OAR_MASK					(0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE					(0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK				(0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK				(0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK			(0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK				(0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK			(0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK				(0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK				(0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK				(0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK				(0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK				(0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK				(0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK				(0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK				(0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK				(0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK				(0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK				(0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR					(0x144)
+#define U300_SYSCON_C1OAR_MASK					(0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE					(0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK				(0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK				(0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK				(0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK				(0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK				(0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK				(0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK				(0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK				(0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK				(0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK				(0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK				(0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK				(0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK				(0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR					(0x148)
+#define U300_SYSCON_C2OAR_MASK					(0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE					(0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK				(0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK				(0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK				(0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK				(0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK				(0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK				(0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK				(0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK				(0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK			(0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK				(0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK			(0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK				(0x0001)
+
 
 /*
  * The clocking hierarchy currently looks like this.
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:54 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:54 +0200
Subject: [PATCH 6/7] ARM: u300: convert to multiplatform
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-7-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Now that we removed our dependency on <mach/*> the U300
can be converted to mutliplatform. Remove the invalid restriction
that U300 would not support AUTO_ZRELADDR (it does) and update
the defconfig in the process.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig                | 21 +--------------------
 arch/arm/configs/u300_defconfig | 11 ++++-------
 arch/arm/mach-u300/Kconfig      | 31 +++++++++++++++++++++++++------
 3 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd0be78..7e6355c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -886,25 +886,6 @@ config ARCH_SHARK
 	  Support for the StrongARM based Digital DNARD machine, also known
 	  as "Shark" (<http://www.shark-linux.de/shark.html>).
 
-config ARCH_U300
-	bool "ST-Ericsson U300 Series"
-	depends on MMU
-	select ARCH_REQUIRE_GPIOLIB
-	select ARM_AMBA
-	select ARM_PATCH_PHYS_VIRT
-	select ARM_VIC
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select CLKSRC_OF
-	select COMMON_CLK
-	select CPU_ARM926T
-	select GENERIC_CLOCKEVENTS
-	select HAVE_TCM
-	select SPARSE_IRQ
-	select USE_OF
-	help
-	  Support for ST-Ericsson U300 series mobile platforms.
-
 config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
 	depends on MMU
@@ -2151,7 +2132,7 @@ config CRASH_DUMP
 
 config AUTO_ZRELADDR
 	bool "Auto calculation of the decompressed kernel image address"
-	depends on !ZBOOT_ROM && !ARCH_U300
+	depends on !ZBOOT_ROM
 	help
 	  ZRELADDR is the physical address where the decompressed kernel
 	  image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000e..a5fa0d9 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 # CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_U300=y
-CONFIG_MACH_U300=y
-CONFIG_MACH_U300_BS335=y
 CONFIG_MACH_U300_SPIDUMMY=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,11 +42,11 @@ CONFIG_I2C=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_CLKGATE=y
@@ -70,4 +68,3 @@ CONFIG_DEBUG_FS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f59764..e2f350f 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,45 @@
-if ARCH_U300
-
 menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
-config MACH_U300
-	bool "U300"
+config ARCH_U300
+	bool "ST-Ericsson U300 Series"
+	depends on MMU
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_VIC
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select CLKSRC_OF
+	select COMMON_CLK
+	select CPU_ARM926T
+	select GENERIC_CLOCKEVENTS
+	select HAVE_TCM
 	select PINCTRL
 	select PINCTRL_COH901
 	select PINCTRL_U300
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  Support for ST-Ericsson U300 series mobile platforms.
 
 comment "ST-Ericsson U300/U335 Feature Selections"
 
+config MACH_U300
+	depends on ARCH_U300
+	bool "U300"
+	default y
+
 config U300_DEBUG
+	depends on ARCH_U300
 	bool "Debug support for U300"
 	depends on PM
 	help
 		Debug support for U300 in sysfs, procfs etc.
 
 config MACH_U300_SPIDUMMY
+	depends on ARCH_U300
 	bool "SSP/SPI dummy chip"
 	select SPI
 	select SPI_MASTER
@@ -31,5 +52,3 @@ config MACH_U300_SPIDUMMY
 		SPI framework and ARM PL022 support.
 
 endmenu
-
-endif
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:52 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:52 +0200
Subject: [PATCH 4/7] ARM: u300: delete <mach/irqs.h>
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-5-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

All IRQs are now obtained from the device tree, and this file
is unused, so delete it.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/irqs.h | 80 ----------------------------------
 arch/arm/mach-u300/timer.c             |  2 -
 2 files changed, 82 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/irqs.h

diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76..0000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/irqs.h
- *
- *
- * Copyright (C) 2006-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * IRQ channel definitions for the U300 platforms.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_U300_INTCON0_START		32
-#define IRQ_U300_INTCON1_START		64
-/* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT		32
-#define IRQ_U300_IRQ1_EXT		33
-#define IRQ_U300_DMA			34
-#define IRQ_U300_VIDEO_ENC_0		35
-#define IRQ_U300_VIDEO_ENC_1		36
-#define IRQ_U300_AAIF_RX		37
-#define IRQ_U300_AAIF_TX		38
-#define IRQ_U300_AAIF_VGPIO		39
-#define IRQ_U300_AAIF_WAKEUP		40
-#define IRQ_U300_PCM_I2S0_FRAME		41
-#define IRQ_U300_PCM_I2S0_FIFO		42
-#define IRQ_U300_PCM_I2S1_FRAME		43
-#define IRQ_U300_PCM_I2S1_FIFO		44
-#define IRQ_U300_XGAM_GAMCON		45
-#define IRQ_U300_XGAM_CDI		46
-#define IRQ_U300_XGAM_CDICON		47
-#define IRQ_U300_XGAM_PDI		49
-#define IRQ_U300_XGAM_PDICON		50
-#define IRQ_U300_XGAM_GAMEACC		51
-#define IRQ_U300_XGAM_MCIDCT		52
-#define IRQ_U300_APEX			53
-#define IRQ_U300_UART0			54
-#define IRQ_U300_SPI			55
-#define IRQ_U300_TIMER_APP_OS		56
-#define IRQ_U300_TIMER_APP_DD		57
-#define IRQ_U300_TIMER_APP_GP1		58
-#define IRQ_U300_TIMER_APP_GP2		59
-#define IRQ_U300_TIMER_OS		60
-#define IRQ_U300_TIMER_MS		61
-#define IRQ_U300_KEYPAD_KEYBF		62
-#define IRQ_U300_KEYPAD_KEYBR		63
-/* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0		64
-#define IRQ_U300_GPIO_PORT1		65
-#define IRQ_U300_GPIO_PORT2		66
-
-/* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG			67
-#define IRQ_U300_EVHIST			68
-#define IRQ_U300_MSPRO			69
-#define IRQ_U300_MMCSD_MCIINTR0		70
-#define IRQ_U300_MMCSD_MCIINTR1		71
-#define IRQ_U300_I2C0			72
-#define IRQ_U300_I2C1			73
-#define IRQ_U300_RTC			74
-#define IRQ_U300_NFIF			75
-#define IRQ_U300_NFIF2			76
-
-/* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0			77
-#define IRQ_U300_ISP_F1			78
-#define IRQ_U300_ISP_F2			79
-#define IRQ_U300_ISP_F3			80
-#define IRQ_U300_ISP_F4			81
-#define IRQ_U300_GPIO_PORT3		82
-#define IRQ_U300_SYSCON_PLL_LOCK	83
-#define IRQ_U300_UART1			84
-#define IRQ_U300_GPIO_PORT4		85
-#define IRQ_U300_GPIO_PORT5		86
-#define IRQ_U300_GPIO_PORT6		87
-#define U300_VIC_IRQS_END		88
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e622f9..188de9b 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -22,8 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/irqs.h>
-
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:55 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:55 +0200
Subject: [PATCH 7/7] ARM: u300: delete remnant machine headers
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-8-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Two files remain in <mach/*> for U300: timex.h and
uncompress.h. The former is done away with by using
defaults, the latter is unused in multiplatform.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/timex.h      | 17 -----------
 arch/arm/mach-u300/include/mach/uncompress.h | 45 ----------------------------
 2 files changed, 62 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/timex.h
 delete mode 100644 arch/arm/mach-u300/include/mach/uncompress.h

diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72..0000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/timex.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform tick rate definition.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-/* This is for the APP OS GP1 (General Purpose 1) timer */
-#define CLOCK_TICK_RATE		1000000
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e6..0000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/uncompress.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR	(*(volatile unsigned char *)0xc0013000)
-#define AMBA_UART_LCRH	(*(volatile unsigned char *)0xc001302C)
-#define AMBA_UART_CR	(*(volatile unsigned char *)0xc0013030)
-#define AMBA_UART_FR	(*(volatile unsigned char *)0xc0013018)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-	while (AMBA_UART_FR & (1 << 5))
-		barrier();
-
-	AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
-	while (AMBA_UART_FR & (1 << 3))
-		barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May  2 12:16:53 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:16:53 +0200
Subject: [PATCH 5/7] ARM: u300: localize <mach/u300-regs.h>
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1367511416-4312-6-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This register base file is now only used in the machine
itself so move it down into mach-u300.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                         | 3 +--
 arch/arm/mach-u300/regulator.c                    | 2 +-
 arch/arm/mach-u300/{include/mach => }/u300-regs.h | 0
 3 files changed, 2 insertions(+), 3 deletions(-)
 rename arch/arm/mach-u300/{include/mach => }/u300-regs.h (100%)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 9a46426..87fdadb 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -25,9 +25,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
-#include <mach/u300-regs.h>
-
 #include "timer.h"
+#include "u300-regs.h"
 
 /*
  * SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index ab7d7a5..1cbe88c 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,7 +17,7 @@
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
 #include <linux/io.h>
-#include <mach/u300-regs.h>
+#include "u300-regs.h"
 
 /* Power Management Control 16bit (R/W) */
 #define U300_SYSCON_PMCR					(0x50)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
similarity index 100%
rename from arch/arm/mach-u300/include/mach/u300-regs.h
rename to arch/arm/mach-u300/u300-regs.h
-- 
1.7.11.3



From arnd at arndb.de  Thu May  2 12:21:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 18:21:11 +0200
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <1367511416-4312-2-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
 <1367511416-4312-2-git-send-email-linus.walleij@stericsson.com>
Message-ID: <201305021821.12008.arnd@arndb.de>

On Thursday 02 May 2013, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> Get rid of the <mach/syscon.h> header as a prerequisite for
> multiplatform support. Do this by pushing the registers down
> to their respective drivers and deleting the unused remainder.
> 
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> Mike: I'm seeking an ACK for this to take it through the
> ARM SoC tree alongside the big bowl of DT enablement patches.
> ---

How do those drivers get to the SYSCON base address? Should they
be using drivers/mfd/syscon.c as the multiplexor instead?

	Arnd


From linus.walleij at linaro.org  Thu May  2 12:21:30 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 2 May 2013 18:21:30 +0200
Subject: [PATCH 20/23 v2] ARM: u300: add SPI PL022 to the device tree
In-Reply-To: <201305021726.49729.arnd@arndb.de>
References: <1367485952-6212-1-git-send-email-linus.walleij@stericsson.com>
 <201305021726.49729.arnd@arndb.de>
Message-ID: <CACRpkdbO1H4tpRG5rABVZDDOP0uHFs2Fc4+66TD9kyZauUrkLg@mail.gmail.com>

On Thu, May 2, 2013 at 5:26 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 02 May 2013, Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij at linaro.org>
>>
>> This registers the PL022 PrimeCell from the U300 device
>> tree. We make a new copy of the platform data for the
>> device tree boot path, as the old platform data is in an
>> older file which will be going away.
>>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>
> Why do you need both the platform data and the DT description?

This is because the device-tree DMA support for PL022 has
not yet been merged upstream, so it still has to come from
platform data instead.

If/when there is a branch in ARM SoC that has that patch in place
(and I remember reviewing and ACKing it) I can rebase on that
and drop the platform data.

The same goes for PL011 and MMCI platform data actually...

Yours,
Linus Walleij


From arnd at arndb.de  Thu May  2 12:23:02 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 18:23:02 +0200
Subject: [PATCH 0/7] ARM: u300 multiplatform support
In-Reply-To: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <201305021823.02703.arnd@arndb.de>

On Thursday 02 May 2013, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This series builds on top of the recently iterated U300
> device tree support to convert the platform to multiplatform
> (a.k.a. single zImage).
> 
> This is intended to be pulled on top of the DT support.
> 

Very nice! For the patches 2-7:

Acked-by: Arnd Bergmann <arnd at arndb.de>

For patch 1, I'll wait for your reply. It's probably ok too.

	Arnd


From arnd at arndb.de  Thu May  2 12:24:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 18:24:20 +0200
Subject: [PATCH, RFC 10/22] mfd: ab8500: debugfs code depends on gpadc
In-Reply-To: <20130502153624.GN25256@gmail.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-11-git-send-email-arnd@arndb.de>
 <20130502153624.GN25256@gmail.com>
Message-ID: <201305021824.20548.arnd@arndb.de>

On Thursday 02 May 2013, Lee Jones wrote:
> > @@ -580,7 +580,7 @@ config AB8500_CORE
> >  
> >  config AB8500_DEBUG
> >         bool "Enable debug info via debugfs"
> > -       depends on AB8500_CORE && DEBUG_FS
> > +       depends on AB8500_GPADC && DEBUG_FS
> >         default y if DEBUG_FS
> >         help
> >           Select this option if you want debug information using the debug
> 
> Did you find this with ALLCONFIG out of interest.

I used "make randconfig" with this KCONFIG_ALLCONFIG file:

CONFIG_MMU=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_PROC_FS=y
 
> Applied by the way.

Thanks!

	Arnd


From nm at ti.com  Thu May  2 12:24:33 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 11:24:33 -0500
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130502162433.GA10016@kahuna>

On 20:03-20130502, Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> index aa27d7f..8d17a0d 100644
> --- a/arch/arm/mach-omap2/usb-host.c
> +++ b/arch/arm/mach-omap2/usb-host.c
> @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>  	supplies->dev_name = dev_id;
>  
>  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> -	if (!reg_data)
> +	if (!reg_data) {
> +		kfree(supplies);
>  		return -ENOMEM;
> +	}
>  
>  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
>  	reg_data->consumer_supplies = supplies;
> @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>  
>  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
>  			GFP_KERNEL);
> -	if (!config)
> +	if (!config) {
> +		kfree(supplies);
> +		kfree(reg_data);
>  		return -ENOMEM;
> +	}
>  
>  	config->supply_name = name;
>  	config->gpio = gpio;
> @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>  
>  	/* create a regulator device */
>  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> -	if (!pdev)
> +	if (!pdev) {
> +		kfree(supplies);
> +		kfree(reg_data);
> +		kfree(config);
>  		return -ENOMEM;
> +	}
>  
>  	pdev->id = PLATFORM_DEVID_AUTO;
>  	pdev->name = reg_name;
>  	pdev->dev.platform_data = config;
>  
>  	ret = platform_device_register(pdev);
> -	if (ret)
> +	if (ret) {
>  		pr_err("%s: Failed registering regulator %s for %s\n",
>  				__func__, name, dev_id);
> +		kfree(supplies);
> +		kfree(reg_data);
> +		kfree(config);
> +	}

Might be better to switch to devm_XXX managed functions?
>  
>  	return ret;
>  }
> -- 
> 1.8.1.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Regards,
Nishanth Menon


From arnd at arndb.de  Thu May  2 12:25:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 18:25:11 +0200
Subject: [PATCH, RFC 22/22] radio-si4713: depend on SND_SOC
In-Reply-To: <CAC-25o9Xp+pu_AUwxyh+YsiOCOebzMRF37v1VWZJD6nrbx5e6Q@mail.gmail.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-23-git-send-email-arnd@arndb.de>
 <CAC-25o9Xp+pu_AUwxyh+YsiOCOebzMRF37v1VWZJD6nrbx5e6Q@mail.gmail.com>
Message-ID: <201305021825.12094.arnd@arndb.de>

On Thursday 02 May 2013, edubezval at gmail.com wrote:
> On Thu, May 2, 2013 at 11:16 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > It is not possible to select SND_SOC_SI476X if we have not also
> > enabled SND_SOC.
> >
> > warning: (RADIO_SI476X) selects SND_SOC_SI476X which has unmet
> >          direct dependencies (SOUND && !M68K && !UML && SND && SND_SOC)
> >
> > Cc: Hans Verkuil <hverkuil at xs4all.nl>
> > Cc: linux-media at vger.kernel.org
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > ---
> 
> Note on your patch title, this change is against si476X, not on *si4713*.
> 

Sorry about that, I must have copied the wrong prefix from an older patch
then. I'll fix it up locally in case I need to resend.

	Arnd


From arnd at arndb.de  Thu May  2 12:26:41 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 18:26:41 +0200
Subject: [PATCH, RFC 08/22] OMAPDSS: DPI needs DSI
In-Reply-To: <5182896F.90807@ti.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-9-git-send-email-arnd@arndb.de> <5182896F.90807@ti.com>
Message-ID: <201305021826.41263.arnd@arndb.de>

On Thursday 02 May 2013, Tomi Valkeinen wrote:
> On 05/02/2013 06:16 PM, Arnd Bergmann wrote:
> > The dpi.c file cannot be build correctly when the dsi.c file is
> > disabled in Kconfig. This clarifies the dependency in Kconfig
> > to avoid build errors:
> > 
> > drivers/video/omap2/dss/dpi.c: In function 'dpi_calc_pll_cb':
> > drivers/video/omap2/dss/dpi.c:181:2: error: implicit declaration of function 'dsi_hsdiv_calc' [-Werror=implicit-function-declaration]
> > drivers/video/omap2/dss/dpi.c: In function 'dpi_dsi_clk_calc':
> > drivers/video/omap2/dss/dpi.c:201:2: error: implicit declaration of function 'dsi_get_pll_clkin' [-Werror=implicit-function-declaration]
> 
> I've sent a patch for this to DRM maintainer, hopefully merged soon.
> 

Ok, thanks!

	Arnd


From shc_work at mail.ru  Thu May  2 12:28:44 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 02 May 2013 20:28:44 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSF0gQVJNOiBPTUFQLVVTQjogRml4IHBvc3NpYmxlIG1l?=
 =?UTF-8?B?bW9yeSBsZWFr?=
In-Reply-To: <20130502162433.GA10016@kahuna>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna>
Message-ID: <1367512124.978518915@f372.mail.ru>

> On 20:03-20130502, Alexander Shiyan wrote:
> > 
> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > ---
> >  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
> >  1 file changed, 17 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> > index aa27d7f..8d17a0d 100644
> > --- a/arch/arm/mach-omap2/usb-host.c
> > +++ b/arch/arm/mach-omap2/usb-host.c
> > @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> >  	supplies->dev_name = dev_id;
> >  
> >  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> > -	if (!reg_data)
> > +	if (!reg_data) {
> > +		kfree(supplies);
> >  		return -ENOMEM;
> > +	}
> >  
> >  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> >  	reg_data->consumer_supplies = supplies;
> > @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> >  
> >  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
> >  			GFP_KERNEL);
> > -	if (!config)
> > +	if (!config) {
> > +		kfree(supplies);
> > +		kfree(reg_data);
> >  		return -ENOMEM;
> > +	}
> >  
> >  	config->supply_name = name;
> >  	config->gpio = gpio;
> > @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> >  
> >  	/* create a regulator device */
> >  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> > -	if (!pdev)
> > +	if (!pdev) {
> > +		kfree(supplies);
> > +		kfree(reg_data);
> > +		kfree(config);
> >  		return -ENOMEM;
> > +	}
> >  
> >  	pdev->id = PLATFORM_DEVID_AUTO;
> >  	pdev->name = reg_name;
> >  	pdev->dev.platform_data = config;
> >  
> >  	ret = platform_device_register(pdev);
> > -	if (ret)
> > +	if (ret) {
> >  		pr_err("%s: Failed registering regulator %s for %s\n",
> >  				__func__, name, dev_id);
> > +		kfree(supplies);
> > +		kfree(reg_data);
> > +		kfree(config);
> > +	}
> 
> Might be better to switch to devm_XXX managed functions?

If anyone can rewrite driver to use devm_xx, it would have been better.
I'm not going to redo the patch yet, let it be so, I just showed a point
for OMAP-developers.
Thanks.

---

From arnd at arndb.de  Thu May  2 12:29:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 18:29:37 +0200
Subject: [PATCH v2] thermal: cpu_cooling: fix stub function
In-Reply-To: <51828A45.60909@ti.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-13-git-send-email-arnd@arndb.de> <51828A45.60909@ti.com>
Message-ID: <201305021829.37343.arnd@arndb.de>

The function stub for cpufreq_cooling_get_level introduced
in 57df81069 "Thermal: exynos: fix cooling state translation"
is not syntactically correct C and needs to be fixed to avoid
this error:

In file included from drivers/thermal/db8500_thermal.c:20:0:
 include/linux/cpu_cooling.h: In function 'cpufreq_cooling_get_level':
include/linux/cpu_cooling.h:57:1:
 error: parameter name omitted  unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)  ^
 include/linux/cpu_cooling.h:57:1: error: parameter name omitted

Cc: Eduardo Valentin <eduardo.valentin at ti.com>
Cc: Zhang Rui <rui.zhang at intel.com>
Cc: Amit Daniel kachhap <amit.daniel at samsung.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h
index 282e270..a5d52ee 100644
--- a/include/linux/cpu_cooling.h
+++ b/include/linux/cpu_cooling.h
@@ -41,7 +41,7 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus);
  */
 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev);
 
-unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int);
+unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq);
 #else /* !CONFIG_CPU_THERMAL */
 static inline struct thermal_cooling_device *
 cpufreq_cooling_register(const struct cpumask *clip_cpus)
@@ -54,7 +54,7 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
 	return;
 }
 static inline
-unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)
+unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq)
 {
 	return THERMAL_CSTATE_INVALID;
 }




From linus.walleij at linaro.org  Thu May  2 12:38:36 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 2 May 2013 18:38:36 +0200
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <201305021821.12008.arnd@arndb.de>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
 <1367511416-4312-2-git-send-email-linus.walleij@stericsson.com>
 <201305021821.12008.arnd@arndb.de>
Message-ID: <CACRpkdayJCm-PcY_=+NDraEPn0m6BrjNRH+tYp3Abar43RamaA@mail.gmail.com>

On Thu, May 2, 2013 at 6:21 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 02 May 2013, Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij at linaro.org>
>>
>> Get rid of the <mach/syscon.h> header as a prerequisite for
>> multiplatform support. Do this by pushing the registers down
>> to their respective drivers and deleting the unused remainder.
>>
>> Cc: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>> ---
>> Mike: I'm seeking an ACK for this to take it through the
>> ARM SoC tree alongside the big bowl of DT enablement patches.
>> ---
>
> How do those drivers get to the SYSCON base address? Should they
> be using drivers/mfd/syscon.c as the multiplexor instead?

No, there is no mutex to be taken. The consecutive range of memory
addresses are used by different things (mainly the clocks) but there
is no register that needs to be protected against access from two
subsystems simultaneously.

As a follow-up to this series I plan to move also the U300 clocks
to the device tree (similar three-step ladder as used for the Nomadik)
and then they will (hopefully) get the syscon base address from the
device tree.

Yours,
Linus Walleij


From balbi at ti.com  Thu May  2 12:40:58 2013
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 2 May 2013 19:40:58 +0300
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <1367512124.978518915@f372.mail.ru>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
Message-ID: <20130502164058.GC8577@arwen.pp.htv.fi>

Hi,

On Thu, May 02, 2013 at 08:28:44PM +0400, Alexander Shiyan wrote:
> > On 20:03-20130502, Alexander Shiyan wrote:
> > > 
> > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > ---
> > >  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
> > >  1 file changed, 17 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> > > index aa27d7f..8d17a0d 100644
> > > --- a/arch/arm/mach-omap2/usb-host.c
> > > +++ b/arch/arm/mach-omap2/usb-host.c
> > > @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > >  	supplies->dev_name = dev_id;
> > >  
> > >  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> > > -	if (!reg_data)
> > > +	if (!reg_data) {
> > > +		kfree(supplies);
> > >  		return -ENOMEM;
> > > +	}
> > >  
> > >  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> > >  	reg_data->consumer_supplies = supplies;
> > > @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > >  
> > >  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
> > >  			GFP_KERNEL);
> > > -	if (!config)
> > > +	if (!config) {
> > > +		kfree(supplies);
> > > +		kfree(reg_data);
> > >  		return -ENOMEM;
> > > +	}
> > >  
> > >  	config->supply_name = name;
> > >  	config->gpio = gpio;
> > > @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > >  
> > >  	/* create a regulator device */
> > >  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> > > -	if (!pdev)
> > > +	if (!pdev) {
> > > +		kfree(supplies);
> > > +		kfree(reg_data);
> > > +		kfree(config);
> > >  		return -ENOMEM;
> > > +	}
> > >  
> > >  	pdev->id = PLATFORM_DEVID_AUTO;
> > >  	pdev->name = reg_name;
> > >  	pdev->dev.platform_data = config;
> > >  
> > >  	ret = platform_device_register(pdev);
> > > -	if (ret)
> > > +	if (ret) {
> > >  		pr_err("%s: Failed registering regulator %s for %s\n",
> > >  				__func__, name, dev_id);
> > > +		kfree(supplies);
> > > +		kfree(reg_data);
> > > +		kfree(config);
> > > +	}
> > 
> > Might be better to switch to devm_XXX managed functions?

I don't think it makes sense since the platform_device hasn't been
registered yet.

Still, patch can be improved with proper goto labels instead of
sprinkling different kfree() calls in every single error branch.

> If anyone can rewrite driver to use devm_xx, it would have been better.
> I'm not going to redo the patch yet, let it be so, I just showed a point
> for OMAP-developers.

fair enough.

-- 
balbi
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From linus.walleij at stericsson.com  Thu May  2 12:47:32 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 2 May 2013 18:47:32 +0200
Subject: [PATCH] ARM: u300: move debugmacro to debug includes
Message-ID: <1367513252-23384-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This moves the U300 debug macro to the debug headers to
make way for multiplatform support.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig.debug                                            | 8 ++++++++
 .../include/mach/debug-macro.S => include/debug/u300.S}           | 0
 2 files changed, 8 insertions(+)
 rename arch/arm/{mach-u300/include/mach/debug-macro.S => include/debug/u300.S} (100%)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b31f43..ea74618 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -414,6 +414,13 @@ choice
 		  Say Y here if you want the debug print routines to direct
 		  their output to the uart1 port on SiRFmarco devices.
 
+	config DEBUG_U300_UART
+		bool "Kernel low-level debugging messages via U300 UART0"
+		depends on ARCH_U300
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the uart port on U300 devices.
+
 	config DEBUG_VEXPRESS_UART0_DETECT
 		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
 		depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -595,6 +602,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
 	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
 	default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
+	default "debug/u300.S" if DEBUG_U300_UART
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
 		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
 	default "debug/vt8500.S" if DEBUG_VT8500_UART0
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S
similarity index 100%
rename from arch/arm/mach-u300/include/mach/debug-macro.S
rename to arch/arm/include/debug/u300.S
-- 
1.7.11.3



From mturquette at linaro.org  Thu May  2 12:53:17 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 02 May 2013 09:53:17 -0700
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <1367480285-26159-2-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
Message-ID: <20130502165317.7790.1722@quantum>

Quoting Jingchang Lu (2013-05-02 00:38:04)
> diff --git a/arch/arm/mach-imx/clk-mvf.c b/arch/arm/mach-imx/clk-mvf.c
> new file mode 100644
> index 0000000..1467a304
> --- /dev/null
> +++ b/arch/arm/mach-imx/clk-mvf.c
> @@ -0,0 +1,406 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/types.h>
> +#include <linux/time.h>
> +#include <linux/hrtimer.h>
> +#include <linux/mm.h>
> +#include <linux/errno.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/clkdev.h>
> +#include <linux/regulator/consumer.h>
> +#include <asm/div64.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk-private.h>

Please do not use clk-private.h.  I plan to remove it soon.

Regards,
Mike


From eduardo.valentin at ti.com  Thu May  2 12:54:29 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 2 May 2013 12:54:29 -0400
Subject: [PATCH v2] thermal: cpu_cooling: fix stub function
In-Reply-To: <201305021829.37343.arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-13-git-send-email-arnd@arndb.de> <51828A45.60909@ti.com>
 <201305021829.37343.arnd@arndb.de>
Message-ID: <51829A45.7040307@ti.com>

Rui, Arnd,

On 02-05-2013 12:29, Arnd Bergmann wrote:
> The function stub for cpufreq_cooling_get_level introduced
> in 57df81069 "Thermal: exynos: fix cooling state translation"
> is not syntactically correct C and needs to be fixed to avoid
> this error:
> 
> In file included from drivers/thermal/db8500_thermal.c:20:0:
>  include/linux/cpu_cooling.h: In function 'cpufreq_cooling_get_level':
> include/linux/cpu_cooling.h:57:1:
>  error: parameter name omitted  unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)  ^
>  include/linux/cpu_cooling.h:57:1: error: parameter name omitted
> 
> Cc: Eduardo Valentin <eduardo.valentin at ti.com>
> Cc: Zhang Rui <rui.zhang at intel.com>
> Cc: Amit Daniel kachhap <amit.daniel at samsung.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Eduardo Valentin <eduardo.valentin at ti.com>

> 
> diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h
> index 282e270..a5d52ee 100644
> --- a/include/linux/cpu_cooling.h
> +++ b/include/linux/cpu_cooling.h
> @@ -41,7 +41,7 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus);
>   */
>  void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev);
>  
> -unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int);
> +unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq);
>  #else /* !CONFIG_CPU_THERMAL */
>  static inline struct thermal_cooling_device *
>  cpufreq_cooling_register(const struct cpumask *clip_cpus)
> @@ -54,7 +54,7 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
>  	return;
>  }
>  static inline
> -unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)
> +unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq)
>  {
>  	return THERMAL_CSTATE_INVALID;
>  }
> 
> 
> 

> 


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From eduardo.valentin at ti.com  Thu May  2 13:07:49 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 2 May 2013 13:07:49 -0400
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502153834.GR28721@atomide.com>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com>
Message-ID: <51829D65.7040109@ti.com>

Arnd, Tony,

On 02-05-2013 11:38, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux at arm.linux.org.uk> [130502 01:27]:
>> On Tue, Apr 30, 2013 at 09:17:39AM +0100, Russell King - ARM Linux wrote:
>>> Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
>>> great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
>>> arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
>>> source of errors.
>>>
>>> OMAP stuff needs a serious look at too - much Kconfig madness there
>>> caused by over-use of select, which then goes on to cause build errors
>>> because it assumes some stuff is always enabled.
>>>
>>> There's also warnings about of_device_id from include/linux/of_platform.h
>>> via from arch/arm/kernel/setup.c which feature in all the non-OF builds
>>> too which need addressing.
>>>
>>> See todays http://www.arm.linux.org.uk/developer/build/ results for all
>>> the details and configs.  Not pushing my tree until some of this stuff
>>> gets fixed.
>>
>> And now we have a new bunch of warnings from OMAP stuff which weren't
>> previously there...
>>
>> arch/arm/mach-omap2/omap_device.c: In function 'omap_device_get_by_hwmod_name':
>> arch/arm/mach-omap2/omap_device.c:821:3: warning: return makes pointer from integer without a cast
>> arch/arm/mach-omap2/omap_device.c:826:3: warning: return makes pointer from integer without a cast
> 
> Hmm these I already fixed earlier along with a merge resolution, and
> I'm not seeing them in next/master or arm-soc/for-next. What do you
> have merged into your current tree?
> 
>> drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
>> drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result
> 
> Neil, care to provide a fix for this? It's from your commit ab37813
> (twl4030_charger: Allow charger to control the regulator that feeds it).
> 
>> include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event' defined but not used
> 
> Eduardo, can you fix that one? It seems to be from your commit 8ab3e6a
> (thermal: Use thermal zone device id in netlink messages).

Yeah sure I can fix it. As simple as the following:
From c04244c87312f5bfc61d9e12ba3fbaa0fdd81adb Mon Sep 17 00:00:00 2001
From: Eduardo Valentin <eduardo.valentin at ti.com>
Date: Thu, 2 May 2013 12:58:20 -0400
Subject: [PATCH 1/1] thermal: remove stub for thermal_generate_netlink_event

This patch removes the stub for thermal_generate_netlink_event
because this function is not used anywhere inside the kernel.

In case CONFIG_NET is not set we get:
include/linux/thermal.h:254:12: warning:
'thermal_generate_netlink_event' defined but not used

Thus removing it.

Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 include/linux/thermal.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index e3c0ae9..e3f3cba 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -250,12 +250,6 @@ void thermal_unregister_governor(struct
thermal_governor *);
 #ifdef CONFIG_NET
 extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
 						enum events event);
-#else
-static int thermal_generate_netlink_event(struct thermal_zone_device *tz,
-						enum events event)
-{
-	return 0;
-}
 #endif

 #endif /* __THERMAL_H__ */
-- 
1.8.2.1.342.gfa7285d

However,...

Rui, Durga,

 That function was used in the previous thermal  layer design. Now the
notification is done via sysfs, not netlink. The netlink interface needs
to be flagged as DEPRECATED and then we would remove it.

In any case, the above function is used by no one within the kernel:
$ git grep thermal_generate_netlink_event
Documentation/thermal/sysfs-api.txt:just need to call
thermal_generate_netlink_event() with two arguments viz
drivers/thermal/thermal_core.c:int thermal_generate_netlink_event(struct
thermal_zone_device *tz,
drivers/thermal/thermal_core.c:EXPORT_SYMBOL_GPL(thermal_generate_netlink_event);
include/linux/thermal.h:extern int thermal_generate_netlink_event(struct
thermal_zone_device *tz,
include/linux/thermal.h:static inline int
thermal_generate_netlink_event(struct thermal_zone_device *tz,


For that reason, I d propose to simply remove it, as I do not have any
user space application that uses that net link interface. But that needs
a confirmation from the Intel folks.

Rui, Durga? Last merge window we discussed to remove this API, do you
guys have dependency on this one still?


Cheers,

> 
> Regards,
> 
> Tony
> 
> 


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From lauraa at codeaurora.org  Thu May  2 13:09:26 2013
From: lauraa at codeaurora.org (Laura Abbott)
Date: Thu,  2 May 2013 10:09:26 -0700
Subject: [PATCH] ARM: ixp4xx: change type of ioremap function
Message-ID: <1367514566-30831-1-git-send-email-lauraa@codeaurora.org>

Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
(ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
changed the type of the ioremap functions to actually use phys_addr_t
instead of unsigned long. Change the type of the arch_ioremap function
to use phys_addr_t as well.

Signed-off-by: Laura Abbott <lauraa at codeaurora.org>

diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 1dbeb7c..659768b 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -558,7 +558,7 @@ void ixp4xx_restart(char mode, const char *cmd)
  * fallback to the default.
  */
 
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
 					   unsigned int mtype, void *caller)
 {
 	if (!is_pci_memory(addr))
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From stefano.stabellini at eu.citrix.com  Thu May  2 13:12:12 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 18:12:12 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce
 psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>

ping

On Tue, 30 Apr 2013, Stefano Stabellini wrote:
> Hi all,
> this is the tenth version of the patch series to move virt_smp_ops out
> of mach-virt and make it a generic set of reusable PSCI based smp_ops.
> psci_smp_ops are preferred over the platform smp_ops.  The last patch
> introduces smp_init.
> 
> Changes in v10:
> - add include <linux/types.h> to mach/arch.h.
> 
> 
> 
> Jon Medhurst (1):
>       ARM: Enable selection of SMP operations at boot time
> 
> Stefano Stabellini (1):
>       arm: introduce psci_smp_ops
> 
>  arch/arm/include/asm/mach/arch.h |    5 ++
>  arch/arm/include/asm/psci.h      |    9 ++++
>  arch/arm/kernel/Makefile         |    5 ++-
>  arch/arm/kernel/psci.c           |    7 +--
>  arch/arm/kernel/psci_smp.c       |   90 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/kernel/setup.c          |    9 +++-
>  arch/arm/mach-virt/Makefile      |    1 -
>  arch/arm/mach-virt/platsmp.c     |   58 ------------------------
>  arch/arm/mach-virt/virt.c        |    3 -
>  9 files changed, 119 insertions(+), 68 deletions(-)
>  create mode 100644 arch/arm/kernel/psci_smp.c
>  delete mode 100644 arch/arm/mach-virt/platsmp.c
> 
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git 3.9-rc3-psci-ops-10-tag
> 
> Cheers,
> 
> Stefano
> 


From will.deacon at arm.com  Thu May  2 13:15:16 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 2 May 2013 18:15:16 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
Message-ID: <20130502171516.GA3040@mudshark.cambridge.arm.com>

Hi Stefano,

On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> ping

Is this a ping to have this pulled into Russell's tree? If so, might be
worth sending a pull request to linux+pull at arm.linux.org.uk.

Has this been in -next?

Will


From lauraa at codeaurora.org  Thu May  2 13:17:58 2013
From: lauraa at codeaurora.org (Laura Abbott)
Date: Thu,  2 May 2013 10:17:58 -0700
Subject: [PATCH] ARM: ebsa110: Change the type of ioremap function
Message-ID: <1367515078-32202-1-git-send-email-lauraa@codeaurora.org>

Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
(ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
changed the type of the ioremap functions to actually use phys_addr_t
instead of unsigned long. Change the type of the arch_ioremap function
to use phys_addr_t as well.

Signed-off-by: Laura Abbott <lauraa at codeaurora.org>

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..8a53f34 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void)
 	iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
 					    unsigned int flags, void *caller)
 {
 	return (void __iomem *)cookie;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From dave.martin at linaro.org  Thu May  2 13:19:25 2013
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 2 May 2013 18:19:25 +0100
Subject: [PATCH] ARM: KVM: Don't handle PSCI calls via SMC
In-Reply-To: <CAEDV+gK27-vw-RhcSrQsrJUfJx_zKQXtc6R6JGVg=YDsQmWZHA@mail.gmail.com>
References: <1367426968-5577-1-git-send-email-Dave.Martin@arm.com>
 <CAEDV+gK27-vw-RhcSrQsrJUfJx_zKQXtc6R6JGVg=YDsQmWZHA@mail.gmail.com>
Message-ID: <20130502171925.GB9879@linaro.org>

On Wed, May 01, 2013 at 10:59:13AM -0700, Christoffer Dall wrote:
> On Wed, May 1, 2013 at 9:49 AM, Dave P Martin <Dave.Martin at arm.com> wrote:
> > Currently, kvmtool unconditionally declares that HVC should be used
> > to call PSCI, so the function numbers in the DT tell the guest
> > nothing about the function ID namespace or calling convention for
> > SMC.
> >
> > We already assume that the guest will examine and honour the DT,
> > since there is no way it could possibly guess the KVM-specific PSCI
> > function IDs otherwise.  So let's not encourage guests to violate
> > what's specified in the DT by using SMC to make the call.
> >
> > Signed-off-by: Dave P Martin <Dave.Martin at arm.com>
> > Acked-by: Marc Zyngier <marc.zyngier at arm.com>
> 
> Thanks, applied.
> 
> -Christoffer

Thanks
---Dave


From linux at arm.linux.org.uk  Thu May  2 13:19:51 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 18:19:51 +0100
Subject: [PATCHv3 3/3] net: velocity: Add platform device support to
 VIA velocity driver
In-Reply-To: <20130429230450.GA2620@electric-eye.fr.zoreil.com>
References: <1367264772-4557-1-git-send-email-linux@prisktech.co.nz>
 <1367264772-4557-4-git-send-email-linux@prisktech.co.nz>
 <20130429230450.GA2620@electric-eye.fr.zoreil.com>
Message-ID: <20130502171951.GV14496@n2100.arm.linux.org.uk>

On Tue, Apr 30, 2013 at 01:04:50AM +0200, Francois Romieu wrote:
> Tony Prisk <linux at prisktech.co.nz> :
> [...]
> > +static int velocity_remove(void *pdev, enum velocity_bus_type bustype)
> > +{
> > +	struct net_device *netdev;
> > +	struct velocity_info *vptr;
> > +	int pci = (bustype == BUS_PCI) ? 1 : 0;
> > +
> > +	if (pci)
> > +		netdev = pci_get_drvdata(pdev);
> > +	else
> > +		netdev = platform_get_drvdata(pdev);
> 
> The caller knows how to retrieve the net_device pointer, whence
> the struct velocity_info pointer, whence any bustype dependent
> function pointer to alleviate the "if (pci)" and CONFIG stuff.
> 
> If you are not convinced, please consider turning the void *
> into an union *.

The other thing here is that you can just pass a struct device into
these and retrieve the same driver data via:

	netdev = dev_get_drvdata(dev);

as:

static inline void *platform_get_drvdata(const struct platform_device *pdev)
{
        return dev_get_drvdata(&pdev->dev);
}

static inline void *pci_get_drvdata(struct pci_dev *pdev)
{
        return dev_get_drvdata(&pdev->dev);
}

So there's no need for void * or union nonsense.


From nm at ti.com  Thu May  2 13:20:13 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 12:20:13 -0500
Subject: [PATCH v3 4/5] ARM: dts: OMAP4460: Add device nodes for ABB
In-Reply-To: <1367515215-30753-1-git-send-email-nm@ti.com>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
Message-ID: <1367515215-30753-5-git-send-email-nm@ti.com>

From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>

Add ABB device nodes for OMAP4460 device Data is based on OMAP4460
Technical Reference Manual revision Z (April 2013)

[nm at ti.com: co-developer]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi at ti.com>
---
 arch/arm/boot/dts/omap4460.dtsi |   38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..e854c41 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -29,4 +29,42 @@
 			     <0 55 0x4>;
 		ti,hwmods = "debugss";
 	};
+
+	ocp {
+		abb_mpu: regulator-abb-mpu {
+			status = "okay";
+
+			reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
+			      <0x4A002268 0x4>;
+			reg-names = "base-address", "int-address",
+				    "efuse-address";
+
+			ti,abb_info = <
+			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
+			1025000		0	0	0	0	0
+			1200000		0	0	0	0	0
+			1313000		0	0	0x100000 0x40000 0
+			1375000		1	0	0	0	0
+			1389000		1	0	0	0	0
+			>;
+		};
+
+		abb_iva: regulator-abb-iva {
+			status = "okay";
+
+			reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
+			      <0x4A002268 0x4>;
+			reg-names = "base-address", "int-address",
+				    "efuse-address";
+
+			ti,abb_info = <
+			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
+			950000		0	0	0	0	0
+			1140000		0	0	0	0	0
+			1291000		0	0	0x200000 0	0
+			1375000		1	0	0	0	0
+			1376000		1	0	0	0	0
+			>;
+		};
+	};
 };
-- 
1.7.9.5



From nm at ti.com  Thu May  2 13:20:12 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 12:20:12 -0500
Subject: [PATCH v3 3/5] ARM: dts: OMAP443x: Add device nodes for ABB
In-Reply-To: <1367515215-30753-1-git-send-email-nm@ti.com>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
Message-ID: <1367515215-30753-4-git-send-email-nm@ti.com>

From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>

Add ABB device nodes for OMAP443x family of devices. abb_iva is
populated, but disabled as it is not used on current OMAP443x family,
but the node is used on OMAP446x family. Data is based on OMAP443x
Technical Reference Manual revision AN (April 2013).

[nm at ti.com: co-developer]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi    |   32 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap443x.dtsi |   26 ++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 1c6d969..8f6a1fb 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -108,6 +108,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		sysclk_in: sys_clkin {
+			#clock-cells = <0>;
+			compatible = "ti,omap-clock";
+		};
+
 		dpll_mpu: dpll_mpu {
 			#clock-cells = <0>;
 			compatible = "ti,omap-clock";
@@ -667,5 +672,32 @@
 			ram-bits = <12>;
 			ti,has-mailbox;
 		};
+
+		abb_mpu: regulator-abb-mpu {
+			compatible = "ti,abb-v2";
+			regulator-name = "abb_mpu";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			ti,tranxdone-status-mask = <0x80>;
+			clocks = <&sysclk_in>;
+			ti,settling-time = <50>;
+			ti,clock-cycles = <16>;
+
+			status = "disabled";
+		};
+
+		abb_iva: regulator-abb-iva {
+			compatible = "ti,abb-v2";
+			regulator-name = "abb_iva";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			ti,tranxdone-status-mask = <0x80000000>;
+			clocks = <&sysclk_in>;
+			ti,settling-time = <50>;
+			ti,clock-cycles = <16>;
+
+			status = "disabled";
+		};
+
 	};
 };
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..377e519 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -24,4 +24,30 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+
+	ocp {
+		abb_mpu: regulator-abb-mpu {
+			status = "okay";
+
+			reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
+			reg-names = "base-address", "int-address";
+
+			ti,abb_info = <
+			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
+			1025000		0	0	0	0	0
+			1200000		0	0	0	0	0
+			1313000		0	0	0	0	0
+			1375000		1	0	0	0	0
+			1389000		1	0	0	0	0
+			>;
+		};
+
+		/* Default unused, just provide register info for record */
+		abb_iva: regulator-abb-iva {
+			reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
+			reg-names = "base-address", "int-address";
+		};
+
+	};
+
 };
-- 
1.7.9.5



From nm at ti.com  Thu May  2 13:20:11 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 12:20:11 -0500
Subject: [PATCH v3 2/5] ARM: dts: OMAP36xx: Add device node for ABB
In-Reply-To: <1367515215-30753-1-git-send-email-nm@ti.com>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
Message-ID: <1367515215-30753-3-git-send-email-nm@ti.com>

From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>

Add ABB device node for OMAP36xx family of devices. Data is based on
OMAP36XX Technical Reference Manual revision AB (Dec 2012).

[nm at ti.com: co-developer]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi at ti.com>
---
 arch/arm/boot/dts/omap3.dtsi    |    5 +++++
 arch/arm/boot/dts/omap36xx.dtsi |   20 ++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 58c6ed6..5d97201 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -75,6 +75,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		sysclk: sys {
+			#clock-cells = <0>;
+			compatible = "ti,omap-clock";
+		};
+
 		dpll1: dpll1 {
 			#clock-cells = <0>;
 			compatible = "ti,omap-clock";
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc..38cdcb0 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -34,5 +34,25 @@
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
+
+		abb_mpu_iva: regulator-abb-mpu {
+			compatible = "ti,abb-v1";
+			regulator-name = "abb_mpu_iva";
+			#address-cell = <0>;
+			#size-cells = <0>;
+			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+			reg-names = "base-address", "int-address";
+			ti,tranxdone-status-mask = <0x4000000>;
+			clocks = <&sysclk>;
+			ti,settling-time = <30>;
+			ti,clock-cycles = <8>;
+			ti,abb_info = <
+			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
+			1012500		0	0	0	0	0
+			1200000		0	0	0	0	0
+			1325000		0	0	0	0	0
+			1375000		1	0	0	0	0
+			>;
+		};
 	};
 };
-- 
1.7.9.5



From nm at ti.com  Thu May  2 13:20:09 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 12:20:09 -0500
Subject: [PATCH v3 0/5] regulator/OMAP: Support TI Adaptive Body Bias(ABB)
 on-chip LDO driver
Message-ID: <1367515215-30753-1-git-send-email-nm@ti.com>

Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.

Texas Instruments' SoC processors have an on chip LDO subsystem which
is part of the SmartReflex 2 technology and provides support for this
power management technique with Forward Body Biasing (FBB) and Reverse
Body Biasing (RBB). These modulate the body voltage of transistor
cells or blocks dynamically to gain performance and reduce leakage.

This series introduces ABB regulator and associated data for
controlling ABB module on OMAP3630+ TI SoCs. Usage of ABB LDO is part
of SoC's OPP voltage transition sequence. We just introduce the
regulator in this series for LDO control, however, the actual sequence
of control of this regulator is left to the implementation of SoC OPP
voltage transition of the appropriate domain.

Note: We only support device tree supported boot in this series.

Testing and Caveats:
	- Sanity tested on OMAP3,4,5 platforms - verified with omapconf.
	- Testing performed with regulator virtual consumer:
		http://pastebin.com/Knp1fSxA
	- OMAP5 clock nodes are introduced, but clock data is missing in
		upstream - tested with private tree with requisite clock nodes
		introduced. Clock node has been commented out in this series.

V3 of this series also available (with testing patch):
http link: https://github.com/nmenon/linux-2.6-playground/commits/devel/abb-regulator-v3
git link: git://github.com/nmenon/linux-2.6-playground.git
branch: devel/abb-regulator-v3

Changes in V3:
	- Regulator is purely meant to control ABB LDO.
	- The "regulator chaining" for doing voltage scale for entire
	  SoC voltage domain has been dropped.
	- Debugfs entries meant to expose ABB registers has been dropped as
	  the same functionality can be achieved with readmem like omapconf
	  application.
	- Re-factored regulator logic to make it simpler using the existing
	  voltage indexing support of regulator framework.
	- Implemented efuse based detection strategy and provided requisite
	  data to cover all existing OMAPs using ABB.
	- Depends on OMAP clock driver introduced in:
		http://marc.info/?t=136580758500001&r=1&w=2

V2: http://marc.info/?t=136603261400007&r=1&w=2&n=3
V1/RFC: http://marc.info/?l=linux-omap&m=136449099409794&w=2

Andrii.Tseglytskyi (5):
  regulator: Introduce TI Adaptive Body Bias(ABB) on-chip LDO driver
  ARM: dts: OMAP36xx: Add device node for ABB
  ARM: dts: OMAP443x: Add device nodes for ABB
  ARM: dts: OMAP4460: Add device nodes for ABB
  ARM: dts: OMAP5: Add device nodes for ABB

 .../bindings/regulator/ti-abb-regulator.txt        |  128 +++
 arch/arm/boot/dts/omap3.dtsi                       |    5 +
 arch/arm/boot/dts/omap36xx.dtsi                    |   20 +
 arch/arm/boot/dts/omap4.dtsi                       |   32 +
 arch/arm/boot/dts/omap443x.dtsi                    |   26 +
 arch/arm/boot/dts/omap4460.dtsi                    |   38 +
 arch/arm/boot/dts/omap5.dtsi                       |   67 ++
 drivers/regulator/Kconfig                          |   10 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/ti-abb-regulator.c               |  912 ++++++++++++++++++++
 10 files changed, 1239 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
 create mode 100644 drivers/regulator/ti-abb-regulator.c

-- 
1.7.9.5



From nm at ti.com  Thu May  2 13:20:14 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 12:20:14 -0500
Subject: [PATCH v3 5/5] ARM: dts: OMAP5: Add device nodes for ABB
In-Reply-To: <1367515215-30753-1-git-send-email-nm@ti.com>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
Message-ID: <1367515215-30753-6-git-send-email-nm@ti.com>

From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>

Add ABB device nodes for OMAP5 family of devices. Data is based on
OMAP543x Technical Reference Manual revision U (April 2013).
NOTE: clock node has been disabled in this patch due to the lack of
OMAP5 clock data.

[nm at ti.com: co-developer]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   67 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..a9d86d2 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -667,5 +667,72 @@
 				ctrl-module = <&omap_control_usb>;
 			};
 		};
+
+		abb_mpu: regulator-abb-mpu {
+			compatible = "ti,abb-v2";
+			regulator-name = "abb_mpu";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			/* clocks = <&sysclk_in>; - once we have clock data */
+			ti,settling-time = <50>;
+			ti,clock-cycles = <16>;
+
+			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
+			      <0x4a0021ac 0x18>, <0x4ae0C318 0x4>;
+			reg-names = "base-address", "int-address",
+				    "efuse-address", "ldo-address";
+			ti,tranxdone-status-mask = <0x80>;
+			/* LDOVBBMPU_MUX_CTRL */
+			ti,ldovbb-override-mask = <0x400>;
+			/* LDOVBBMPU_VSET_OUT */
+			ti,ldovbb-vset-mask = <0x1F>;
+
+			/*
+			 * NOTE: only FBB mode used but actual vset will
+			 * determine final biasing
+			 */
+			ti,abb_info = <
+			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
+			880000		0	0x4	0 0x20000000 0x1F000000
+			1060000		0	0x8	0 0x20000000 0x1F000000
+			1250000		0	0x10	0 0x20000000 0x1F000000
+			1260000		1	0x14	0 0x20000000 0x1F000000
+			>;
+
+			status = "disabled";
+		};
+
+		abb_mm: regulator-abb-mm {
+			compatible = "ti,abb-v2";
+			regulator-name = "abb_iva";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			/* clocks = <&sysclk_in>; - once we have clock data */
+			ti,settling-time = <50>;
+			ti,clock-cycles = <16>;
+
+			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+			      <0x4a002194 0x14>, <0x4ae0C314 0x4>;
+			reg-names = "base-address", "int-address",
+				    "efuse-address", "ldo-address";
+			ti,tranxdone-status-mask = <0x80000000>;
+			/* LDOVBBMM_MUX_CTRL */
+			ti,ldovbb-override-mask = <0x400>;
+			/* LDOVBBMM_VSET_OUT */
+			ti,ldovbb-vset-mask = <0x1F>;
+
+			/*
+			 * NOTE: only FBB mode used but actual vset will
+			 * determine final biasing
+			 */
+			ti,abb_info = <
+			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
+			880000		0	0x4	0 0x20000000 0x1F000000
+			1025000		0	0x8	0 0x20000000 0x1F000000
+			1120000		1	0x10	0 0x20000000 0x1F000000
+			>;
+
+			status = "disabled";
+		};
 	};
 };
-- 
1.7.9.5



From nm at ti.com  Thu May  2 13:20:10 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 2 May 2013 12:20:10 -0500
Subject: [PATCH v3 1/5] regulator: Introduce TI Adaptive Body Bias(ABB)
 on-chip LDO driver
In-Reply-To: <1367515215-30753-1-git-send-email-nm@ti.com>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
Message-ID: <1367515215-30753-2-git-send-email-nm@ti.com>

From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>

Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.

Texas Instruments' SmartReflex 2 technology provides support for this
power management technique with Forward Body Biasing (FBB) and Reverse
Body Biasing (RBB). These modulate the body voltage of transistor
cells or blocks dynamically to gain performance and reduce leakage.
TI's SmartReflex white paper[1] has further information for usage in
conjunction with other power management techniques.

The application of FBB/RBB technique is determined for each unique
device in some process nodes, whereas, they are mandated on other
process nodes.

In a nutshell, ABB technique is implemented on TI SoC as an on-chip
LDO which has ABB module controlling the bias voltage. However, the
voltage is unique per device. These vary per SoC family and the manner
in which these techniques are used may vary depending on the Operating
Performance Point (OPP) voltage targeted. For example:
OMAP3630/OMAP4430: certain OPPs mandate usage of FBB independent of
	devices.
OMAP4460/OMAP4470: certain OPPs mandate usage of FBB, while others may
	optionally use FBB or optimization with RBB.
OMAP5: ALL OPPs may optionally use ABB, and ABB biasing voltage is
	influenced by vset fused in s/w and requiring s/w override of
	default values.

Further, two generations of ABB module are used in various TI SoCs.
They have remained mostly register field compatible, however the
register offset had switched between versions.

We introduce ABB LDO support in the form of a regulator which is
controlled by voltages denoting the desired Operating Performance
Point which is targeted. However, since ABB transition is part of OPP
change sequence, the sequencing required to ensure sane operation
w.r.t OPP change is left to the controlling driver (example: cpufreq
SoC driver) using standard regulator operations.

The driver supports all ABB modes and ability to override ABB LDO vset
control efuse based ABB mode detection etc.

Current implementation is heavily influenced by the original patch
series [2][3] from Mike Turquette. However, the current implementation
supports only device tree based information.

[1] http://www.ti.com/pdfs/wtbu/smartreflex_whitepaper.pdf
[2] http://marc.info/?l=linux-omap&m=134931341818379&w=2
[3] http://marc.info/?l=linux-arm-kernel&m=134931402406853&w=2

[nm at ti.com: co-developer]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi at ti.com>
---

V2: http://marc.info/?l=linux-omap&m=136611169104414&w=2
V1: http://marc.info/?l=linux-omap&m=136481444405843&w=2
 .../bindings/regulator/ti-abb-regulator.txt        |  128 +++
 drivers/regulator/Kconfig                          |   10 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/ti-abb-regulator.c               |  912 ++++++++++++++++++++
 4 files changed, 1051 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
 create mode 100644 drivers/regulator/ti-abb-regulator.c

diff --git a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
new file mode 100644
index 0000000..2e57a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
@@ -0,0 +1,128 @@
+Adaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs
+
+Required Properties:
+- compatible: Should be one of:
+  - "ti,abb-v1" for older SoCs like OMAP3
+  - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  - "base-address"	- contains base address of ABB module
+  - "int-address"	- contains address of interrupt register for ABB module
+  (also see Optional properties)
+- #address-cell: should be 0
+- #size-cell: should be 0
+- clocks: should point to the clock node used by ABB module
+- ti,settling-time: Settling time in uSecs from SoC documentation for ABB module
+	to settle down(target time for SR2_WTCNT_VALUE).
+- ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
+	computing settling time from SoC Documentation for ABB module(clock
+	cycles for SR2_WTCNT_VALUE).
+- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
+	indicating LDO tranxdone (operation complete).
+- ti,abb_info: An array of 6-tuples u32 items providing information about ABB
+	configuration needed per operational voltage of the device.
+	Each item consists of the following in the same order:
+	volt: voltage in uV - Only used to index ABB information.
+	ABB mode: one of the following:
+		0-bypass
+		1-Forward Body Bias(FBB)
+		3-Reverse Body Bias(RBB)
+	efuse:	(see Optional properties)
+	RBB enable efuse Mask:	(See Optional properties)
+	FBB enable efuse Mask:	(See Optional properties)
+	Vset value efuse Mask:	(See Optional properties)
+
+	NOTE: If more than 1 entry is present, then regulator is setup to change
+	      voltage, allowing for various modes to be selected indexed off
+	      the regulator. Further, ABB LDOs are considered always-on by
+	      default.
+
+Optional Properties:
+- reg-names: In addition to the required properties, the following are optional
+  - "efuse-address"	- Contains efuse base address used to pick up ABB info.
+  - "ldo-address"	- Contains address of ABB LDO overide register address.
+	"efuse-address" is required for this.
+- ti,ldovbb-vset-mask	- Required if ldo-address is set, mask for LDO override
+	register to provide override vset value.
+- ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO
+	override register to enable override vset value.
+- ti,abb_opp_sel: Addendum to the description in required properties
+	efuse: Mandatory if 'efuse-address' register is defined. Provides offset
+	       from efuse-address to pick up ABB characteristics. Set to 0 if
+	       'efuse-address' is not defined.
+	RBB enable efuse Mask:	Optional if 'efuse-address' register is defined.
+		'ABB mode' is force set to RBB mode if value at "efuse-address"
+		+ efuse maps to RBB mask. Set to 0 to ignore this.
+	FBB enable efuse Mask:	Optional if 'efuse-address' register is defined.
+		'ABB mode' is force set to FBB mode if value at "efuse-address"
+		+ efuse maps to FBB mask (valid only if RBB mask does not match)
+		Set to 0 to ignore this.
+	Vset value efuse Mask:	Mandatory if ldo-address is set. Picks up from
+		efuse the value to set in 'ti,ldovbb-vset-mask' at ldo-address.
+
+Example #1: Simplest configuration (no efuse data, hard coded ABB table):
+abb_x: regulator-abb-x {
+	compatible = "ti,abb-v1";
+	regulator-name = "abb_x";
+	#address-cell = <0>;
+	#size-cells = <0>;
+	reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+	reg-names = "base-address", "int-address";
+	ti,tranxdone-status-mask = <0x4000000>;
+	clocks = <&sysclk>;
+	ti,settling-time = <30>;
+	ti,clock-cycles = <8>;
+	ti,abb_info = <
+	/* uV		ABB	efuse	rbb_m	fbb_m	vset_m */
+	1012500		0	0	0	0	0 /* Bypass */
+	1200000		3	0	0	0	0 /* RBB mandatory */
+	1320000		1	0	0	0	0 /* FBB mandatory */
+	>;
+};
+
+Example #2: Efuse bits contain ABB mode setting (no LDO override capability)
+abb_y: regulator-abb-y {
+	compatible = "ti,abb-v2";
+	regulator-name = "abb_y";
+	#address-cell = <0>;
+	#size-cells = <0>;
+	reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>;
+	reg-names = "base-address", "int-address", "efuse-address";
+	ti,tranxdone-status-mask = <0x4000000>;
+	clocks = <&sysclk>;
+	ti,settling-time = <50>;
+	ti,clock-cycles = <16>;
+	ti,abb_info = <
+	/* uV		ABB	efuse	rbb_m	fbb_m	vset_m */
+	975000		0	0	0	0	0 /* Bypass */
+	1012500		0	0	0x40000	0	0 /* RBB optional */
+	1200000		0	0x4	0	0x40000	0 /* FBB optional */
+	1320000		1	0	0	0	0 /* FBB mandatory */
+	>;
+};
+
+Example #3: Efuse bits contain ABB mode setting and LDO override capability
+abb_z: regulator-abb-z {
+	compatible = "ti,abb-v2";
+	regulator-name = "abb_z";
+	#address-cell = <0>;
+	#size-cells = <0>;
+	reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+	      <0x4a002194 0x8>, <0x4ae0C314 0x4>;
+	reg-names = "base-address", "int-address",
+		    "efuse-address", "ldo-address";
+	ti,tranxdone-status-mask = <0x8000000>;
+	/* LDOVBBMM_MUX_CTRL */
+	ti,ldovbb-override-mask = <0x400>;
+	/* LDOVBBMM_VSET_OUT */
+	ti,ldovbb-vset-mask = <0x1F>;
+	clocks = <&sysclk>;
+	ti,settling-time = <50>;
+	ti,clock-cycles = <16>;
+	ti,abb_info = <
+	/* uV	ABB	efuse	rbb_m	fbb_m	vset_m */
+	975000	0	0	0	0	0	/* Bypass */
+	1200000	0	0x4	0	0x40000	0x1f00	/* FBB optional, vset */
+	>;
+};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index a5d97ea..a6f7633 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -472,6 +472,16 @@ config REGULATOR_TWL4030
 	  This driver supports the voltage regulators provided by
 	  this family of companion chips.
 
+config REGULATOR_TI_ABB
+	bool "TI Adaptive Body Bias on-chip LDO"
+	depends on ARCH_OMAP
+	help
+	  Select this option to support Texas Instruments' on-chip Adaptive Body
+	  Bias (ABB) LDO regulators. It is recommended that this option be
+	  enabled on required TI SoC. Certain Operating Performance Points
+	  on TI SoCs may be unstable without enabling this as it provides
+	  device specific optimized bias to allow/optimize functionality.
+
 config REGULATOR_VEXPRESS
 	tristate "Versatile Express regulators"
 	depends on VEXPRESS_CONFIG
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 6e82503..f1116ca 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_TPS65912) += tps65912-regulator.o
 obj-$(CONFIG_REGULATOR_TPS80031) += tps80031-regulator.o
 obj-$(CONFIG_REGULATOR_TWL4030) += twl-regulator.o
+obj-$(CONFIG_REGULATOR_TI_ABB) += ti-abb-regulator.o
 obj-$(CONFIG_REGULATOR_VEXPRESS) += vexpress.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o
diff --git a/drivers/regulator/ti-abb-regulator.c b/drivers/regulator/ti-abb-regulator.c
new file mode 100644
index 0000000..c1870ea
--- /dev/null
+++ b/drivers/regulator/ti-abb-regulator.c
@@ -0,0 +1,912 @@
+/*
+ * Texas Instruments SoC Adaptive Body Bias(ABB) Regulator
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Mike Turquette <mturquette at ti.com>
+ *
+ * Copyright (C) 2012-2013 Texas Instruments, Inc.
+ * Andrii Tseglytskyi <andrii.tseglytskyi at ti.com>
+ * Nishanth Menon <nm at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+
+/*
+ * ABB LDO operating states:
+ * NOMINAL_OPP:	bypasses the ABB LDO
+ * FAST_OPP:	sets ABB LDO to Forward Body-Bias
+ * SLOW_OPP:	sets ABB LDO to Reverse Body-Bias
+ */
+#define TI_ABB_NOMINAL_OPP	0
+#define TI_ABB_FAST_OPP		1
+#define TI_ABB_SLOW_OPP		3
+
+/**
+ * struct ti_abb_info - ABB information per voltage setting
+ * @opp_sel:	one of TI_ABB macro
+ * @vset:	(optional) vset value that LDOVBB needs to be overriden with.
+ *
+ * Array of per voltage entries organized in the same order as regulator_desc's
+ * volt_table list. (selector is used to index from this array)
+ */
+struct ti_abb_info {
+	u32 opp_sel;
+	u32 vset;
+};
+
+/**
+ * struct ti_abb_reg - Register description for ABB block
+ * @setup_reg:			setup register offset from base
+ * @control_reg:		control register offset from base
+ * @sr2_wtcnt_value_mask:	setup register- sr2_wtcnt_value mask
+ * @fbb_sel_mask:		setup register- FBB sel mask
+ * @rbb_sel_mask:		setup register- RBB sel mask
+ * @sr2_en_mask:		setup register- enable mask
+ * @opp_change_mask:		control register - mask to trigger LDOVBB change
+ * @opp_sel_mask:		control register - mask for mode to operate
+ */
+struct ti_abb_reg {
+	u32 setup_reg;
+	u32 control_reg;
+
+	/* Setup register fields */
+	u32 sr2_wtcnt_value_mask;
+	u32 fbb_sel_mask;
+	u32 rbb_sel_mask;
+	u32 sr2_en_mask;
+
+	/* Control register fields */
+	u32 opp_change_mask;
+	u32 opp_sel_mask;
+};
+
+/**
+ * struct ti_abb - ABB instance data
+ * @rdesc:			regulator descriptor
+ * @clk:			clock(usually sysclk) supplying ABB block
+ * @base:			base address of ABB block
+ * @int_base:			interrupt register base address
+ * @efuse_base:			(optional) efuse base address for ABB modes
+ * @ldo_base:			(optional) LDOVBB vset override base address
+ * @regs:			pointer to struct ti_abb_reg for ABB block
+ * @txdone_mask:		mask on int_base for tranxdone interrupt
+ * @ldovbb_override_mask:	mask to ldo_base for overriding default LDO VBB
+ *				vset with value from efuse
+ * @ldovbb_vset_mask:		mask to ldo_base for providing the VSET override
+ * @info:			array to per voltage ABB configuration
+ * @current_info_idx:		current index to info
+ * @settling_time:		SoC specific settling time for LDO VBB
+ */
+struct ti_abb {
+	struct regulator_desc rdesc;
+	struct clk *clk;
+	void __iomem *base;
+	void __iomem *int_base;
+	void __iomem *efuse_base;
+	void __iomem *ldo_base;
+
+	const struct ti_abb_reg *regs;
+	u32 txdone_mask;
+	u32 ldovbb_override_mask;
+	u32 ldovbb_vset_mask;
+
+	struct ti_abb_info *info;
+	int current_info_idx;
+
+	u32 settling_time;
+};
+
+/**
+ * ti_abb_rmw() - handy wrapper to set specific register bits
+ * @mask:	mask for register field
+ * @value:	value shifted to mask location and written
+ * @offset:	offset of register
+ * @base:	base address
+ *
+ * Return: final register value (may be unused)
+ */
+static inline u32 ti_abb_rmw(u32 mask, u32 value, u32 offset,
+			     void __iomem *base)
+{
+	u32 val;
+
+	val = readl(base + offset);
+	val &= ~mask;
+	val |= (value << __ffs(mask)) & mask;
+	writel(val, base + offset);
+
+	return val;
+}
+
+/**
+ * ti_abb_check_txdone() - handy wrapper to check ABB tranxdone status
+ * @abb:	pointer to the abb instance
+ *
+ * Return: true or false
+ */
+static inline bool ti_abb_check_txdone(const struct ti_abb *abb)
+{
+	return !!(readl(abb->int_base) & abb->txdone_mask);
+}
+
+/**
+ * ti_abb_clear_txdone() - handy wrapper to clear ABB tranxdone status
+ * @abb:	pointer to the abb instance
+ */
+static inline void ti_abb_clear_txdone(const struct ti_abb *abb)
+{
+	writel(abb->txdone_mask, abb->int_base);
+};
+
+/**
+ * ti_abb_wait_tranx() - waits for ABB tranxdone event
+ * @dev:	device
+ * @abb:	pointer to the abb instance
+ *
+ * Return: 0 on success or -ETIMEDOUT if the event is not cleared on time.
+ */
+static int ti_abb_wait_txdone(struct device *dev, struct ti_abb *abb)
+{
+	int timeout = 0;
+	bool status;
+
+	while (timeout++ <= abb->settling_time) {
+		status = ti_abb_check_txdone(abb);
+		if (status)
+			break;
+
+		udelay(1);
+	}
+
+	if (timeout > abb->settling_time) {
+		dev_warn_ratelimited(dev,
+				     "%s:TRANXDONE timeout(%duS) int=0x%08x\n",
+				     __func__, timeout, readl(abb->int_base));
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+/**
+ * ti_abb_clear_all_txdone() - clears ABB tranxdone event
+ * @dev:	device
+ * @abb:	pointer to the abb instance
+ *
+ * Return: 0 on success or -ETIMEDOUT if the event is not cleared on time.
+ */
+static int ti_abb_clear_all_txdone(struct device *dev, const struct ti_abb *abb)
+{
+	int timeout = 0;
+	bool status;
+
+	while (timeout++ <= abb->settling_time) {
+		ti_abb_clear_txdone(abb);
+
+		status = ti_abb_check_txdone(abb);
+		if (!status)
+			break;
+
+		udelay(1);
+	}
+
+	if (timeout > abb->settling_time) {
+		dev_warn_ratelimited(dev,
+				     "%s:TRANXDONE timeout(%duS) int=0x%08x\n",
+				     __func__, timeout, readl(abb->int_base));
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+/**
+ * ti_abb_program_ldovbb() - program LDOVBB register for override value
+ * @dev:	device
+ * @abb:	pointer to the abb instance
+ * @info:	ABB info to program
+ */
+static void ti_abb_program_ldovbb(struct device *dev, const struct ti_abb *abb,
+				  struct ti_abb_info *info)
+{
+	u32 val;
+
+	val = readl(abb->ldo_base);
+	/* clear up previous values */
+	val &= ~(abb->ldovbb_override_mask | abb->ldovbb_vset_mask);
+
+	switch (info->opp_sel) {
+	case TI_ABB_SLOW_OPP:
+	case TI_ABB_FAST_OPP:
+		val |= abb->ldovbb_override_mask;
+		val |= info->vset << __ffs(abb->ldovbb_vset_mask);
+		break;
+	}
+
+	writel(val, abb->ldo_base);
+}
+
+/**
+ * ti_abb_set_opp() - Setup ABB and LDO VBB for required bias
+ * @rdev:	regulator device
+ * @abb:	pointer to the abb instance
+ * @info:	ABB info to program
+ *
+ * Return: 0 on success or appropriate error value when fails
+ */
+static int ti_abb_set_opp(struct regulator_dev *rdev, struct ti_abb *abb,
+			  struct ti_abb_info *info)
+{
+	const struct ti_abb_reg *regs = abb->regs;
+	struct device *dev = &rdev->dev;
+	int ret;
+
+	ret = ti_abb_clear_all_txdone(dev, abb);
+	if (ret)
+		goto out;
+
+	ti_abb_rmw(regs->fbb_sel_mask | regs->rbb_sel_mask, 0, regs->setup_reg,
+		   abb->base);
+
+	switch (info->opp_sel) {
+	case TI_ABB_SLOW_OPP:
+		ti_abb_rmw(regs->rbb_sel_mask, 1, regs->setup_reg, abb->base);
+		break;
+	case TI_ABB_FAST_OPP:
+		ti_abb_rmw(regs->fbb_sel_mask, 1, regs->setup_reg, abb->base);
+		break;
+	}
+
+	/* program next state of ABB ldo */
+	ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, regs->control_reg,
+		   abb->base);
+
+	/* program LDO VBB vset override if needed */
+	if (abb->ldo_base)
+		ti_abb_program_ldovbb(dev, abb, info);
+
+	/* Initiate ABB ldo change */
+	ti_abb_rmw(regs->opp_change_mask, 1, regs->control_reg, abb->base);
+
+	/* Wait for ABB LDO to complete transition to new Bias setting */
+	ret = ti_abb_wait_txdone(dev, abb);
+	if (ret)
+		goto out;
+
+	ret = ti_abb_clear_all_txdone(dev, abb);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+/**
+ * ti_abb_set_voltage_sel() - regulator accessor function to set ABB LDO
+ * @rdev:	regulator device
+ * @sel:	selector to index into required ABB LDO settings (maps to
+ *		regulator descriptor's volt_table)
+ *
+ * Return: 0 on success or appropriate error value when fails
+ */
+static int ti_abb_set_voltage_sel(struct regulator_dev *rdev, unsigned sel)
+{
+	const struct regulator_desc *desc = rdev->desc;
+	struct ti_abb *abb = rdev_get_drvdata(rdev);
+	struct device *dev = &rdev->dev;
+	struct ti_abb_info *info, *oinfo;
+	int ret = 0;
+
+	if (!abb) {
+		dev_err_ratelimited(dev, "%s: No regulator drvdata\n",
+				    __func__);
+		return -ENODEV;
+	}
+
+	if (!desc->n_voltages || !abb->info) {
+		dev_err_ratelimited(dev,
+				    "%s: No valid voltage table entries?\n",
+				    __func__);
+		return -EINVAL;
+	}
+
+	if (sel >= desc->n_voltages) {
+		dev_err(dev, "%s: sel idx(%d) >= n_voltages(%d)\n", __func__,
+			sel, desc->n_voltages);
+		return -EINVAL;
+	}
+
+	/* If we are in the same index as we were, nothing to do here! */
+	if (sel == abb->current_info_idx) {
+		dev_dbg(dev, "%s: Already at sel=%d\n", __func__, sel);
+		return ret;
+	}
+
+	/* If data is exactly the same, then just update index, no change */
+	info = &abb->info[sel];
+	oinfo = &abb->info[abb->current_info_idx];
+	if (!memcmp(info, oinfo, sizeof(*info))) {
+		dev_dbg(dev, "%s: Same data new idx=%d, old idx=%d\n", __func__,
+			sel, abb->current_info_idx);
+		goto out;
+	}
+
+	ret = ti_abb_set_opp(rdev, abb, info);
+
+out:
+	if (!ret)
+		abb->current_info_idx = sel;
+	else
+		dev_err_ratelimited(dev,
+				    "%s: Volt[%d] idx[%d] mode[%d] Fail(%d)\n",
+				    __func__, desc->volt_table[sel], sel,
+				    info->opp_sel, ret);
+	return ret;
+}
+
+/**
+ * ti_abb_get_voltage_sel() - Regulator accessor to get current ABB LDO setting
+ * @rdev:	regulator device
+ *
+ * Return: 0 on success or appropriate error value when fails
+ */
+static int ti_abb_get_voltage_sel(struct regulator_dev *rdev)
+{
+	const struct regulator_desc *desc = rdev->desc;
+	struct ti_abb *abb = rdev_get_drvdata(rdev);
+	struct device *dev = &rdev->dev;
+
+	if (!abb) {
+		dev_err_ratelimited(dev, "%s: No regulator drvdata\n",
+				    __func__);
+		return -ENODEV;
+	}
+
+	if (!desc->n_voltages || !abb->info) {
+		dev_err_ratelimited(dev,
+				    "%s: No valid voltage table entries?\n",
+				    __func__);
+		return -EINVAL;
+	}
+
+	if (abb->current_info_idx > (int)desc->n_voltages) {
+		dev_err(dev, "%s: Corrupted data? idx(%d) > n_voltages(%d)\n",
+			__func__, abb->current_info_idx, desc->n_voltages);
+		return -EINVAL;
+	}
+
+	return abb->current_info_idx;
+}
+
+/**
+ * ti_abb_init_timings() - setup ABB clock timing for the current platform
+ * @dev:	device
+ * @abb:	pointer to the abb instance
+ *
+ * Return: 0 if timing is updated, else returns error result.
+ */
+static int ti_abb_init_timings(struct device *dev, struct ti_abb *abb)
+{
+	u32 clock_cycles;
+	u32 clk_rate, sr2_wt_cnt_val, cycle_rate;
+	const struct ti_abb_reg *regs = abb->regs;
+	int ret;
+	char *pname = "ti,settling-time";
+
+	/* read device tree properties */
+	ret = of_property_read_u32(dev->of_node, pname, &abb->settling_time);
+	if (ret) {
+		dev_err(dev, "Unable to get property '%s'(%d)\n", pname, ret);
+		return ret;
+	}
+
+	/* ABB LDO cannot be settle in 0 time */
+	if (!abb->settling_time) {
+		dev_err(dev, "Invalid property:'%s' set as 0!\n", pname);
+		return -EINVAL;
+	}
+
+	pname = "ti,clock-cycles";
+	ret = of_property_read_u32(dev->of_node, pname, &clock_cycles);
+	if (ret) {
+		dev_err(dev, "Unable to get property '%s'(%d)\n", pname, ret);
+		return ret;
+	}
+	/* ABB LDO cannot be settle in 0 clock cycles */
+	if (!clock_cycles) {
+		dev_err(dev, "Invalid property:'%s' set as 0!\n", pname);
+		return -EINVAL;
+	}
+
+	abb->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(abb->clk)) {
+		ret = PTR_ERR(abb->clk);
+		dev_err(dev, "%s: Unable to get clk(%d)\n", __func__, ret);
+		return ret;
+	}
+
+	/*
+	 * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
+	 * transition and must be programmed with the correct time at boot.
+	 * The value programmed into the register is the number of SYS_CLK
+	 * clock cycles that match a given wall time profiled for the ldo.
+	 * This value depends on:
+	 * settling time of ldo in micro-seconds (varies per OMAP family)
+	 * # of clock cycles per SYS_CLK period (varies per OMAP family)
+	 * the SYS_CLK frequency in MHz (varies per board)
+	 * The formula is:
+	 *
+	 *                      ldo settling time (in micro-seconds)
+	 * SR2_WTCNT_VALUE = ------------------------------------------
+	 *                   (# system clock cycles) * (sys_clk period)
+	 *
+	 * Put another way:
+	 *
+	 * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
+	 *
+	 * To avoid dividing by zero multiply both "# clock cycles" and
+	 * "settling time" by 10 such that the final result is the one we want.
+	 */
+
+	/* Convert SYS_CLK rate to MHz & prevent divide by zero */
+	clk_rate = DIV_ROUND_CLOSEST(clk_get_rate(abb->clk), 1000000);
+
+	/* Calculate cycle rate */
+	cycle_rate = DIV_ROUND_CLOSEST(clock_cycles * 10, clk_rate);
+
+	/* Calulate SR2_WTCNT_VALUE */
+	sr2_wt_cnt_val = DIV_ROUND_CLOSEST(abb->settling_time * 10, cycle_rate);
+
+	dev_dbg(dev, "%s: Clk_rate=%ld, sr2_cnt=0x%08x\n", __func__,
+		clk_get_rate(abb->clk), sr2_wt_cnt_val);
+
+	ti_abb_rmw(regs->sr2_wtcnt_value_mask, sr2_wt_cnt_val, regs->setup_reg,
+		   abb->base);
+
+	return 0;
+}
+
+/**
+ * ti_abb_init_table() - Initialize ABB table from device tree
+ * @dev:	device
+ * @abb:	pointer to the abb instance
+ * @rinit_data:	regulator initdata
+ *
+ * Return: 0 on success or appropriate error value when fails
+ */
+static int ti_abb_init_table(struct device *dev, struct ti_abb *abb,
+			     struct regulator_init_data *rinit_data)
+{
+	struct ti_abb_info *info;
+	const struct property *prop;
+	const __be32 *abb_info;
+	const u32 num_values = 6;
+	char *pname = "ti,abb_info";
+	u32 num_entries, i;
+	unsigned int *volt_table;
+	int min_uV = INT_MAX, max_uV = 0;
+	struct regulation_constraints *c = &rinit_data->constraints;
+
+	prop = of_find_property(dev->of_node, pname, NULL);
+	if (!prop) {
+		dev_err(dev, "No '%s' property?\n", pname);
+		return -ENODEV;
+	}
+
+	if (!prop->value) {
+		dev_err(dev, "Empty '%s' property?\n", pname);
+		return -ENODATA;
+	}
+
+	/*
+	 * Each abb_info is a set of n-tuple, where n is num_values, consisting
+	 * of voltage and a set of detection logic for ABB information for that
+	 * voltage to apply.
+	 */
+	num_entries = prop->length / sizeof(u32);
+	if (!num_entries || (num_entries % num_values)) {
+		dev_err(dev, "All '%s' list entries need %d vals\n", pname,
+			num_values);
+		return -EINVAL;
+	}
+	num_entries /= num_values;
+
+	info = devm_kzalloc(dev, sizeof(*info) * num_entries, GFP_KERNEL);
+	if (!info) {
+		dev_err(dev, "Can't allocate info table for '%s' property\n",
+			pname);
+		return -ENOMEM;
+	}
+	abb->info = info;
+
+	volt_table = devm_kzalloc(dev, sizeof(unsigned int) * num_entries,
+				  GFP_KERNEL);
+	if (!volt_table) {
+		dev_err(dev, "Can't allocate voltage table for '%s' property\n",
+			pname);
+		return -ENOMEM;
+	}
+
+	abb->rdesc.n_voltages = num_entries;
+	abb->rdesc.volt_table = volt_table;
+	/* We do not know where the OPP voltage is at the moment */
+	abb->current_info_idx = -EINVAL;
+
+	abb_info = prop->value;
+	for (i = 0; i < num_entries; i++, info++, volt_table++) {
+		u32 efuse_offset, rbb_mask, fbb_mask, vset_mask;
+		u32 efuse_val;
+
+		/* NOTE: num_values should equal to entries picked up here */
+		*volt_table = be32_to_cpup(abb_info++);
+		info->opp_sel = be32_to_cpup(abb_info++);
+		efuse_offset = be32_to_cpup(abb_info++);
+		rbb_mask = be32_to_cpup(abb_info++);
+		fbb_mask = be32_to_cpup(abb_info++);
+		vset_mask = be32_to_cpup(abb_info++);
+
+		dev_dbg(dev,
+			"[%d]v=%d ABB=%d ef=0x%x rbb=0x%x fbb=0x%x vset=0x%x\n",
+			i, *volt_table, info->opp_sel, efuse_offset, rbb_mask,
+			fbb_mask, vset_mask);
+
+		/* Find min/max for voltage set */
+		if (min_uV > *volt_table)
+			min_uV = *volt_table;
+		if (max_uV < *volt_table)
+			max_uV = *volt_table;
+
+		if (!abb->efuse_base) {
+			/* Ignore invalid data, but warn to help cleanup */
+			if (efuse_offset || rbb_mask || fbb_mask || vset_mask)
+				dev_err(dev, "prop '%s': v=%d,bad efuse/mask\n",
+					pname, *volt_table);
+			goto check_abb;
+		}
+
+		efuse_val = readl(abb->efuse_base + efuse_offset);
+
+		/* Use ABB recommendation from Efuse */
+		if (efuse_val & rbb_mask)
+			info->opp_sel = TI_ABB_SLOW_OPP;
+		else if (efuse_val & fbb_mask)
+			info->opp_sel = TI_ABB_FAST_OPP;
+		else if (rbb_mask || fbb_mask)
+			info->opp_sel = TI_ABB_NOMINAL_OPP;
+
+		dev_dbg(dev,
+			"[%d]v=%d efusev=0x%x final ABB=%d\n",
+			i, *volt_table, efuse_val, info->opp_sel);
+
+		/* Use recommended Vset bits from Efuse */
+		if (!abb->ldo_base) {
+			if (vset_mask)
+				dev_err(dev, "prop'%s':v=%d vst=%x LDO base?\n",
+					pname, *volt_table, vset_mask);
+			continue;
+		}
+		info->vset = efuse_val & vset_mask >> __ffs(vset_mask);
+		dev_dbg(dev, "[%d]v=%d vset=%x\n", i, *volt_table, info->vset);
+check_abb:
+		switch (info->opp_sel) {
+		case TI_ABB_NOMINAL_OPP:
+		case TI_ABB_FAST_OPP:
+		case TI_ABB_SLOW_OPP:
+			/* Valid values */
+			break;
+		default:
+			dev_err(dev, "%s:[%d]v=%d, ABB=%d is invalid! Abort!\n",
+				__func__, i, *volt_table, info->opp_sel);
+			return -EINVAL;
+		}
+	}
+
+	/* Setup the min/max voltage constraints from the supported list */
+	c->min_uV = min_uV;
+	c->max_uV = max_uV;
+
+	return 0;
+}
+
+static struct regulator_ops ti_abb_reg_ops = {
+	.list_voltage = regulator_list_voltage_table,
+
+	.set_voltage_sel = ti_abb_set_voltage_sel,
+	.get_voltage_sel = ti_abb_get_voltage_sel,
+};
+
+/* Default ABB block offsets, IF this changes in future, create new one */
+static const struct ti_abb_reg abb_regs_v1 = {
+	/* WARNING: registers are wrongly documented in TRM */
+	.setup_reg		= 0x04,
+	.control_reg		= 0x00,
+
+	.sr2_wtcnt_value_mask	= (0xff << 8),
+	.fbb_sel_mask		= (0x01 << 2),
+	.rbb_sel_mask		= (0x01 << 1),
+	.sr2_en_mask		= (0x01 << 0),
+
+	.opp_change_mask	= (0x01 << 2),
+	.opp_sel_mask		= (0x03 << 0),
+};
+
+static const struct ti_abb_reg abb_regs_v2 = {
+	.setup_reg		= 0x00,
+	.control_reg		= 0x04,
+
+	.sr2_wtcnt_value_mask	= (0xff << 8),
+	.fbb_sel_mask		= (0x01 << 2),
+	.rbb_sel_mask		= (0x01 << 1),
+	.sr2_en_mask		= (0x01 << 0),
+
+	.opp_change_mask	= (0x01 << 2),
+	.opp_sel_mask		= (0x03 << 0),
+};
+
+static const struct of_device_id ti_abb_of_match[] = {
+	{.compatible = "ti,abb-v1", .data = &abb_regs_v1},
+	{.compatible = "ti,abb-v2", .data = &abb_regs_v2},
+	{ },
+};
+
+MODULE_DEVICE_TABLE(of, ti_abb_of_match);
+
+/**
+ * ti_abb_probe() - Initialize an ABB ldo instance
+ * @pdev: ABB platform device
+ *
+ * Initializes an individual ABB LDO for required Body-Bias. ABB is used to
+ * addional bias supply to SoC modules for power savings or mandatory stability
+ * configuration at certain Operating Performance Points(OPPs).
+ *
+ * Return: 0 on success or appropriate error value when fails
+ */
+static int ti_abb_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct of_device_id *match;
+	struct resource *res;
+	struct ti_abb *abb;
+	struct regulator_init_data *initdata = NULL;
+	struct regulator_dev *rdev = NULL;
+	struct regulator_desc *desc;
+	struct regulation_constraints *c;
+	struct regulator_config config = { };
+	char *pname;
+	int ret = 0;
+
+	match = of_match_device(ti_abb_of_match, dev);
+	if (!match) {
+		/* We do not expect this to happen */
+		ret = -ENODEV;
+		dev_err(dev, "%s: Unable to match device\n", __func__);
+		goto err;
+	}
+	if (!match->data) {
+		ret = -EINVAL;
+		dev_err(dev, "%s: Bad data in match\n", __func__);
+		goto err;
+	}
+
+	abb = devm_kzalloc(dev, sizeof(struct ti_abb), GFP_KERNEL);
+	if (!abb) {
+		dev_err(dev, "%s: Unable to allocate ABB struct\n", __func__);
+		ret = -ENOMEM;
+		goto err;
+	}
+	abb->regs = match->data;
+
+	/* Map ABB resources */
+	pname = "base-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	if (!res) {
+		dev_err(dev, "Missing '%s' IO resource\n", pname);
+		ret = -ENODEV;
+		goto err;
+	}
+	abb->base = devm_request_and_ioremap(dev, res);
+	if (!abb->base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	pname = "int-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	if (!res) {
+		dev_err(dev, "Missing '%s' IO resource\n", pname);
+		ret = -ENODEV;
+		goto err;
+	}
+	/*
+	 * We may have shared interrupt register offsets which are
+	 * write-1-to-clear between domains ensuring exclusivity.
+	 */
+	abb->int_base = devm_ioremap_nocache(dev, res->start,
+					     resource_size(res));
+	if (!abb->int_base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	/* Map Optional resources */
+	pname = "efuse-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	if (!res) {
+		dev_dbg(dev, "Missing '%s' IO resource\n", pname);
+		ret = -ENODEV;
+		goto skip_opt;
+	}
+
+	/*
+	 * We may have shared efuse register offsets which are read-only
+	 * between domains
+	 */
+	abb->efuse_base = devm_ioremap_nocache(dev, res->start,
+					       resource_size(res));
+	if (!abb->efuse_base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	pname = "ldo-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	if (!res) {
+		dev_dbg(dev, "Missing '%s' IO resource\n", pname);
+		ret = -ENODEV;
+		goto skip_opt;
+	}
+	abb->ldo_base = devm_request_and_ioremap(dev, res);
+	if (!abb->ldo_base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	/* IF ldo_base is set, the following are mandatory */
+	pname = "ti,ldovbb-override-mask";
+	ret =
+	    of_property_read_u32(pdev->dev.of_node, pname,
+				 &abb->ldovbb_override_mask);
+	if (ret) {
+		dev_err(dev, "Missing '%s' (%d)\n", pname, ret);
+		goto err;
+	}
+	if (!abb->ldovbb_override_mask) {
+		dev_err(dev, "Invalid property:'%s' set as 0!\n", pname);
+		ret = -EINVAL;
+		goto err;
+	}
+
+	pname = "ti,ldovbb-vset-mask";
+	ret =
+	    of_property_read_u32(pdev->dev.of_node, pname,
+				 &abb->ldovbb_vset_mask);
+	if (ret) {
+		dev_err(dev, "Missing '%s' (%d)\n", pname, ret);
+		goto err;
+	}
+	if (!abb->ldovbb_vset_mask) {
+		dev_err(dev, "Invalid property:'%s' set as 0!\n", pname);
+		ret = -EINVAL;
+		goto err;
+	}
+
+skip_opt:
+	pname = "ti,tranxdone-status-mask";
+	ret =
+	    of_property_read_u32(pdev->dev.of_node, pname,
+				 &abb->txdone_mask);
+	if (ret) {
+		dev_err(dev, "Missing '%s' (%d)\n", pname, ret);
+		goto err;
+	}
+	if (!abb->txdone_mask) {
+		dev_err(dev, "Invalid property:'%s' set as 0!\n", pname);
+		ret = -EINVAL;
+		goto err;
+	}
+
+	initdata = of_get_regulator_init_data(dev, pdev->dev.of_node);
+	if (!initdata) {
+		ret = -ENOMEM;
+		dev_err(dev, "%s: Unable to alloc regulator init data\n",
+			__func__);
+		goto err;
+	}
+
+	/* init ABB opp_sel table */
+	ret = ti_abb_init_table(dev, abb, initdata);
+	if (ret)
+		goto err;
+
+	/* init ABB timing */
+	ret = ti_abb_init_timings(dev, abb);
+	if (ret)
+		goto err;
+
+	desc = &abb->rdesc;
+	desc->name = dev_name(dev);
+	desc->owner = THIS_MODULE;
+	desc->type = REGULATOR_VOLTAGE;
+	desc->ops = &ti_abb_reg_ops;
+
+	c = &initdata->constraints;
+	if (desc->n_voltages > 1)
+		c->valid_ops_mask |= REGULATOR_CHANGE_VOLTAGE;
+	c->always_on = true;
+
+	config.dev = dev;
+	config.init_data = initdata;
+	config.driver_data = abb;
+	config.of_node = pdev->dev.of_node;
+
+	rdev = regulator_register(desc, &config);
+	if (IS_ERR(rdev)) {
+		ret = PTR_ERR(rdev);
+		dev_err(dev, "%s: failed to register regulator(%d)\n",
+			__func__, ret);
+		goto err;
+	}
+	platform_set_drvdata(pdev, rdev);
+
+	/* Enable the ldo if not already done by bootloader */
+	ti_abb_rmw(abb->regs->sr2_en_mask, 1, abb->regs->setup_reg, abb->base);
+
+	return 0;
+
+err:
+	dev_err(dev, "%s: Failed to initialize(%d)\n", __func__, ret);
+	return ret;
+}
+
+/**
+ * ti_abb_remove() - cleanups
+ * @pdev: ABB platform device
+ *
+ * Return: 0
+ */
+static int ti_abb_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+	return 0;
+}
+
+MODULE_ALIAS("platform:ti_abb");
+
+static struct platform_driver ti_abb_driver = {
+	.probe = ti_abb_probe,
+	.remove = ti_abb_remove,
+	.driver = {
+		   .name = "ti_abb",
+		   .owner = THIS_MODULE,
+		   .of_match_table = of_match_ptr(ti_abb_of_match),
+		   },
+};
+module_platform_driver(ti_abb_driver);
+
+MODULE_DESCRIPTION("Texas Instruments ABB LDO regulator driver");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From stefano.stabellini at eu.citrix.com  Thu May  2 13:20:32 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 18:20:32 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce
 psci_smp_ops
In-Reply-To: <20130502171516.GA3040@mudshark.cambridge.arm.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
 <20130502171516.GA3040@mudshark.cambridge.arm.com>
Message-ID: <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Will Deacon wrote:
> Hi Stefano,
> 
> On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> > ping
> 
> Is this a ping to have this pulled into Russell's tree?

I thought that we agreed that the patches should go via the arm-soc
tree, after Russell acks them.

The ping is for Russell to ack them and Arnd to merge them.


> If so, might be
> worth sending a pull request to linux+pull at arm.linux.org.uk.
> 
> Has this been in -next?

Yes they have, because I temporarily added them to my branch in
linux-next.
In fact Stephen found and solved a merge conflict here:

http://marc.info/?l=linux-arm-kernel&m=136722292031420&w=2


From shc_work at mail.ru  Thu May  2 13:20:55 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 02 May 2013 21:20:55 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSCwgUkZDIDIwLzIyXSBtZWRpYTogY29kYTogc2VsZWN0IEdF?=
 =?UTF-8?B?TkVSSUNfQUxMT0NBVE9S?=
In-Reply-To: <1367507786-505303-21-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-21-git-send-email-arnd@arndb.de>
Message-ID: <1367515255.447627800@f375.mail.ru>

> The coda driver uses the generic allocator to get at the
> "iram" memory, so add the necessary dependency to avoid:
> 
> drivers/built-in.o: In function `coda_remove':
>  :(.text+0x2ab680): undefined reference to `gen_pool_free'
> drivers/built-in.o: In function `coda_probe':
> :(.text+0x2ad168): undefined reference to `of_get_named_gen_pool'
> :(.text+0x2ad188): undefined reference to `dev_get_gen_pool'
> :(.text+0x2ad220): undefined reference to `gen_pool_alloc'
> :(.text+0x2ad2ec): undefined reference to `gen_pool_virt_to_phys'
> 
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/media/platform/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 0494d27..4608d03 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -145,6 +145,7 @@ config VIDEO_CODA
>  	depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXC
>  	select VIDEOBUF2_DMA_CONTIG
>  	select V4L2_MEM2MEM_DEV
> +	select GENERIC_ALLOCATOR
>  	---help---
>  	   Coda is a range of video codec IPs that supports
>  	   H.264, MPEG-4, and other video formats.

Again?

---

From lauraa at codeaurora.org  Thu May  2 13:21:00 2013
From: lauraa at codeaurora.org (Laura Abbott)
Date: Thu,  2 May 2013 10:21:00 -0700
Subject: [PATCH] ARM: iop13xx: change type of ioremap function
Message-ID: <1367515260-32364-1-git-send-email-lauraa@codeaurora.org>

Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
(ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
changed the type of the ioremap functions to actually use phys_addr_t
instead of unsigned long. Change the type of the arch_ioremap function
to use phys_addr_t as well.

Signed-off-by: Laura Abbott <lauraa at codeaurora.org>

diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 183dc8b..faaf7d4 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,7 +23,7 @@
 
 #include "pci.h"
 
-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
 	size_t size, unsigned int mtype, void *caller)
 {
 	void __iomem * retval;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From arnd at arndb.de  Thu May  2 13:23:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 19:23:20 +0200
Subject: [PATCH 0/4] ARM architecture fixes
Message-ID: <1367515404-512212-1-git-send-email-arnd@arndb.de>

Hi Russell,

These are four bug fixes that came out of my build testing.
The first one replaces a patch I put into the patch tracker
earlier but had to retract because it broke THUMB2_KERNEL.

The other three are for recent regressions coming from your
tree.

	Arnd

Arnd Bergmann (4):
  ARM: compressed/head.S: work around new binutils warning
  ARM: fix prototypes for arch_ioremap_caller functions
  ARM: fix NOMMU __arm_ioremap prototype
  ARM: highbank: fix build after cache flush change

 arch/arm/boot/compressed/Makefile      | 2 +-
 arch/arm/boot/compressed/head-sa1100.S | 1 +
 arch/arm/boot/compressed/head-shark.S  | 1 +
 arch/arm/boot/compressed/head.S        | 1 +
 arch/arm/mach-ebsa110/core.c           | 2 +-
 arch/arm/mach-highbank/hotplug.c       | 1 +
 arch/arm/mach-imx/mm-imx3.c            | 2 +-
 arch/arm/mach-iop13xx/io.c             | 2 +-
 arch/arm/mach-ixp4xx/common.c          | 2 +-
 arch/arm/mach-msm/common.h             | 2 +-
 arch/arm/mach-msm/io.c                 | 2 +-
 arch/arm/mm/nommu.c                    | 4 ++--
 12 files changed, 13 insertions(+), 9 deletions(-)

-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 13:23:21 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 19:23:21 +0200
Subject: [PATCH 1/4] ARM: compressed/head.S: work around new binutils warning
In-Reply-To: <1367515404-512212-1-git-send-email-arnd@arndb.de>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
Message-ID: <1367515404-512212-2-git-send-email-arnd@arndb.de>

In August 2012, Matthew Gretton-Dann checked a change into binutils
labelled "Error on obsolete & warn on deprecated registers", apparently as
part of ARMv8 support. Apparently, this was supposed to emit the message
"Warning: This coprocessor register access is deprecated in ARMv8" when
using certain mcr/mrc instructions and building for ARMv8. Unfortunately,
the message that is actually emitted appears to be '(null)', which is
less helpful in comparison.

Even more unfortunately, this is biting us on every single kernel
build with a new gas, because arch/arm/boot/compressed/head.S and some
other files in that directory are built with -march=all since kernel
commit 80cec14a8 "[ARM] Add -march=all to assembly file build in
arch/arm/boot/compressed" back in v2.6.28.

This patch reverts Russell's nice solution and instead marks the head.S
file to be built for armv7-a, which fortunately lets us build all
instructions in that file without warnings even on the broken binutils.

Without this patch, building anything results in:

arch/arm/boot/compressed/head.S: Assembler messages:
arch/arm/boot/compressed/head.S:565: Warning: (null)
arch/arm/boot/compressed/head.S:676: Warning: (null)
arch/arm/boot/compressed/head.S:698: Warning: (null)
arch/arm/boot/compressed/head.S:722: Warning: (null)
arch/arm/boot/compressed/head.S:726: Warning: (null)
arch/arm/boot/compressed/head.S:957: Warning: (null)
arch/arm/boot/compressed/head.S:996: Warning: (null)
arch/arm/boot/compressed/head.S:997: Warning: (null)
arch/arm/boot/compressed/head.S:1027: Warning: (null)
arch/arm/boot/compressed/head.S:1035: Warning: (null)
arch/arm/boot/compressed/head.S:1046: Warning: (null)
arch/arm/boot/compressed/head.S:1060: Warning: (null)
arch/arm/boot/compressed/head.S:1092: Warning: (null)
arch/arm/boot/compressed/head.S:1094: Warning: (null)
arch/arm/boot/compressed/head.S:1095: Warning: (null)
arch/arm/boot/compressed/head.S:1102: Warning: (null)
arch/arm/boot/compressed/head.S:1134: Warning: (null)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Matthew Gretton-Dann <matthew.gretton-dann at arm.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/boot/compressed/Makefile      | 2 +-
 arch/arm/boot/compressed/head-sa1100.S | 1 +
 arch/arm/boot/compressed/head-shark.S  | 1 +
 arch/arm/boot/compressed/head.S        | 1 +
 4 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 001a13a..592ede5 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -128,7 +128,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 6179d94..3115e31 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -11,6 +11,7 @@
 #include <asm/mach-types.h>
 
 		.section        ".start", "ax"
+		.arch	armv4
 
 __SA1100_start:
 
diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S
index 089c560..92b5689 100644
--- a/arch/arm/boot/compressed/head-shark.S
+++ b/arch/arm/boot/compressed/head-shark.S
@@ -18,6 +18,7 @@
 	
 		.section	".start", "ax"
 
+		.arch armv4
 		b	__beginning
 	
 __ofw_data:	.long	0				@ the number of memory blocks
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3..6938559 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -11,6 +11,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+	.arch	armv7-a
 /*
  * Debugging stuff
  *
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 13:23:24 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 19:23:24 +0200
Subject: [PATCH 4/4] ARM: highbank: fix build after cache flush change
In-Reply-To: <1367515404-512212-1-git-send-email-arnd@arndb.de>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
Message-ID: <1367515404-512212-5-git-send-email-arnd@arndb.de>

Commit "ARM: cpu hotplug: remove majority of cache flushing from
platforms" has removed the inclusion of asm/cacheflush.h from
a number of files. Highbank still needs it because it calls
flush_cache_louis().

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-highbank/hotplug.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
index 80957f4..a019e4e 100644
--- a/arch/arm/mach-highbank/hotplug.c
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -14,6 +14,7 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/kernel.h>
+#include <asm/cacheflush.h>
 
 #include "core.h"
 #include "sysregs.h"
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 13:23:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 19:23:23 +0200
Subject: [PATCH 3/4] ARM: fix NOMMU __arm_ioremap prototype
In-Reply-To: <1367515404-512212-1-git-send-email-arnd@arndb.de>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
Message-ID: <1367515404-512212-4-git-send-email-arnd@arndb.de>

The declaration of __arm_ioremap has changed to take a phys_addr_t
as the first argument, while the definition for nommu has not
changed. This adds the obvious change.

Cc: Laura Abbott <lauraa at codeaurora.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mm/nommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index e9f2e44..98303d9 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -88,7 +88,7 @@ void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
 	return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
 
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
 			    unsigned int mtype)
 {
 	return (void __iomem *)phys_addr;
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 13:23:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 19:23:22 +0200
Subject: [PATCH 2/4] ARM: fix prototypes for arch_ioremap_caller functions
In-Reply-To: <1367515404-512212-1-git-send-email-arnd@arndb.de>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
Message-ID: <1367515404-512212-3-git-send-email-arnd@arndb.de>

Patch "ARM: 7704/1: mm: Use phys_addr_t properly for ioremap
functions" changes the prototype for the arch_ioremap_caller()
function, a change which was evidently never tested, because
all functions that get assigned to this pointer still have
an unchanged prototype:

arch/arm/mach-ebsa110/core.c: In function 'ebsa110_init_early':
arch/arm/mach-ebsa110/core.c:130:22: warning: assignment from incompatible pointer type [enabled by default]
  arch_ioremap_caller = ebsa110_ioremap_caller;
                      ^
arch/arm/mach-iop13xx/io.c: In function 'iop13xx_init_early':
arch/arm/mach-iop13xx/io.c:88:22: warning: assignment from incompatible pointer type [enabled by default]
  arch_ioremap_caller = __iop13xx_ioremap_caller;
                      ^

This does the trivial change to all the respective functions
to avoid the build warnings.

Cc: Laura Abbott <lauraa at codeaurora.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-ebsa110/core.c  | 2 +-
 arch/arm/mach-imx/mm-imx3.c   | 2 +-
 arch/arm/mach-iop13xx/io.c    | 2 +-
 arch/arm/mach-ixp4xx/common.c | 2 +-
 arch/arm/mach-msm/common.h    | 2 +-
 arch/arm/mach-msm/io.c        | 2 +-
 arch/arm/mm/nommu.c           | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..8a53f34 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void)
 	iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
 					    unsigned int flags, void *caller)
 {
 	return (void __iomem *)cookie;
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a6..eed32ca 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -65,7 +65,7 @@ static void imx3_idle(void)
 		: "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
 					 unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 183dc8b..faaf7d4 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,7 +23,7 @@
 
 #include "pci.h"
 
-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
 	size_t size, unsigned int mtype, void *caller)
 {
 	void __iomem * retval;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..d7223b3 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -559,7 +559,7 @@ void ixp4xx_restart(char mode, const char *cmd)
  * fallback to the default.
  */
 
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
 					   unsigned int mtype, void *caller)
 {
 	if (!is_pci_memory(addr))
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index ce8215a..421cf77 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,7 +23,7 @@ extern void msm_map_msm8x60_io(void);
 extern void msm_map_msm8960_io(void);
 extern void msm_map_qsd8x50_io(void);
 
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 					  unsigned int mtype, void *caller);
 
 extern struct smp_operations msm_smp_ops;
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 123ef9c..fd65b6d 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -172,7 +172,7 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
-void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 				   unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index dd3a6c6..e9f2e44 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -95,7 +95,7 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 
 void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
 				   unsigned int mtype, void *caller)
-- 
1.8.1.2



From stern at rowland.harvard.edu  Thu May  2 13:30:17 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 2 May 2013 13:30:17 -0400 (EDT)
Subject: [PATCH, RFC 16/22] USB: UHCI: clarify Kconfig dependencies
In-Reply-To: <1367507786-505303-17-git-send-email-arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305021304500.1436-100000@iolanthe.rowland.org>

On Thu, 2 May 2013, Arnd Bergmann wrote:

> The UHCI driver currently gives a build error if the base driver is
> enabled but none of the three bus glues are turned on:
> 
> drivers/usb/host/uhci-hcd.c:857:2: error: #error "missing bus glue for uhci-hcd"
> 
> A better solution for this is to change the Kconfig statements to
> prevent getting into this situation. This adds a new USB_UHCI_CORE
> symbol in Kconfig, which is selected by each of the three bus glues.
> This way, the driver never gets built if all three of them are disabled.

I had already worked out a patch on my own for this (below).  It is
different from yours in several ways:

	It relies more on "depends" than "select".  I don't know how 
	important this is in the end.

	It doesn't add a new USB_UHCI_GRLIB symbol; instead it uses
	SPARC_LEON in several places.  I tend to think the new symbol
	is nicer.

	It doesn't add a new USB_UHCI_PCI symbol.

	It improves the dependency list for USB_UHCI_HCD.

	It removes the help text for USB_UHCI_PLATFORM, thereby making
	that symbol not user-configurable.  I don't see any reason why
	the user should need to worry about this -- the choice should
	be a very simple one: build UHCI support or don't build it.  If
	the user chooses to build it then it should include support for
	all the compatible bus glues.  (This last decision may need to 
	be changed if more bus glues get added.)

	It prevents situations where USB_UHCI_HCD is enabled but the
	driver doesn't get built.

	It creates a bunch of USB_UHCI_* symbols even when USB_UHCI_HCD
	is disabled.  This is a disadvantage, but I don't see any way
	around it.  Basically, we have to consider two separate but
	related questions:

		Does the supported hardware configuration allow for 
		UHCI?

		Which types of UHCI bus glue support should be included 
		in the kernel?

	If the answer to the first is Yes then creating these symbols
	seems unavoidable, even when the answer to the second is None.

Maybe the ideal solution is some sort of combination of the two
patches.

What do you think of my patch as compared to yours?  And what do you
think of the "depends" vs. "select" issue?

Alan Stern



Index: usb-3.9/drivers/usb/host/Kconfig
===================================================================
--- usb-3.9.orig/drivers/usb/host/Kconfig
+++ usb-3.9/drivers/usb/host/Kconfig
@@ -507,7 +507,7 @@ endif # USB_OHCI_HCD
 
 config USB_UHCI_HCD
 	tristate "UHCI HCD (most Intel and VIA) support"
-	depends on PCI || SPARC_LEON || ARCH_VT8500
+	depends on PCI || USB_UHCI_SUPPORT_NON_PCI_HC
 	---help---
 	  The Universal Host Controller Interface is a standard by Intel for
 	  accessing the USB hardware in the PC (which is also called the USB
@@ -524,26 +524,19 @@ config USB_UHCI_HCD
 
 config USB_UHCI_SUPPORT_NON_PCI_HC
 	bool
-	depends on USB_UHCI_HCD
-	default y if (SPARC_LEON || ARCH_VT8500)
+	default y if (SPARC_LEON || USB_UHCI_PLATFORM)
 
 config USB_UHCI_PLATFORM
-	bool "Generic UHCI Platform Driver support"
-	depends on USB_UHCI_SUPPORT_NON_PCI_HC
+	bool
 	default y if ARCH_VT8500
-	---help---
-	  Enable support for generic UHCI platform devices that require no
-	  additional configuration.
 
 config USB_UHCI_BIG_ENDIAN_MMIO
 	bool
-	depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON
-	default y
+	default y if SPARC_LEON
 
 config USB_UHCI_BIG_ENDIAN_DESC
 	bool
-	depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON
-	default y
+	default y if SPARC_LEON
 
 config USB_FHCI_HCD
 	tristate "Freescale QE USB Host Controller support"




From stern at rowland.harvard.edu  Thu May  2 13:34:54 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 2 May 2013 13:34:54 -0400 (EDT)
Subject: [PATCH, RFC 15/22] USB: EHCI: remove bogus #error
In-Reply-To: <1367507786-505303-16-git-send-email-arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305021333020.1436-100000@iolanthe.rowland.org>

On Thu, 2 May 2013, Arnd Bergmann wrote:

> The EHCI host controller driver can be built standalone now,
> without enabling any of the available bus glue drivers, so
> there is not really a reason to error out here:

On the other hand, there's no reason to build the driver without any 
bus glue.  It wouldn't do anything.

> drivers/usb/host/ehci-hcd.c:1303:2: error:
>  #error "missing bus glue for ehci-hcd"  #error "missing bus glue for ehci-hcd"
> 
> The alternative would be to change the Kconfig code to build
> the ehci-hcd module only if any of the symbols below are
> in fact enabled.
> 
> Cc: Alan Stern <stern at rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Alan Stern <stern at rowland.harvard.edu>



From mchehab at redhat.com  Thu May  2 13:37:18 2013
From: mchehab at redhat.com (Mauro Carvalho Chehab)
Date: Thu, 02 May 2013 14:37:18 -0300
Subject: [PATCH, RFC 22/22] radio-si4713: depend on SND_SOC
In-Reply-To: <1367507786-505303-23-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-23-git-send-email-arnd@arndb.de>
Message-ID: <5182A44E.7080701@redhat.com>

Em 02-05-2013 12:16, Arnd Bergmann escreveu:
> It is not possible to select SND_SOC_SI476X if we have not also
> enabled SND_SOC.
>
> warning: (RADIO_SI476X) selects SND_SOC_SI476X which has unmet
> 	 direct dependencies (SOUND && !M68K && !UML && SND && SND_SOC)
>
> Cc: Hans Verkuil <hverkuil at xs4all.nl>
> Cc: linux-media at vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>   drivers/media/radio/Kconfig | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig
> index c0beee2..d529ba7 100644
> --- a/drivers/media/radio/Kconfig
> +++ b/drivers/media/radio/Kconfig
> @@ -22,6 +22,7 @@ config RADIO_SI476X
>   	tristate "Silicon Laboratories Si476x I2C FM Radio"
>   	depends on I2C && VIDEO_V4L2
>   	depends on MFD_SI476X_CORE
> +	depends on SND_SOC
>   	select SND_SOC_SI476X
>   	---help---
>   	  Choose Y here if you have this FM radio chip.
>

Do you prefer to send it via your tree or via mine? Either way works for me.

If you're willing to send it via your tree:

Acked-by: Mauro Carvalho Chehab <mchehab at redhat.com>


From arnd at arndb.de  Thu May  2 13:37:56 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 19:37:56 +0200
Subject: [PATCH] ARM: iop13xx: change type of ioremap function
In-Reply-To: <1367515260-32364-1-git-send-email-lauraa@codeaurora.org>
References: <1367515260-32364-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <201305021937.56853.arnd@arndb.de>

On Thursday 02 May 2013, Laura Abbott wrote:
> Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
> (ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
> changed the type of the ioremap functions to actually use phys_addr_t
> instead of unsigned long. Change the type of the arch_ioremap function
> to use phys_addr_t as well.
> 
> Signed-off-by: Laura Abbott <lauraa at codeaurora.org>

Hi Laura,

I've just sent a patch fixing up the same bug and all others
that go along with it.

	Arnd


From arnd at arndb.de  Thu May  2 13:39:48 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 19:39:48 +0200
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <CACRpkdayJCm-PcY_=+NDraEPn0m6BrjNRH+tYp3Abar43RamaA@mail.gmail.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
 <201305021821.12008.arnd@arndb.de>
 <CACRpkdayJCm-PcY_=+NDraEPn0m6BrjNRH+tYp3Abar43RamaA@mail.gmail.com>
Message-ID: <201305021939.48381.arnd@arndb.de>

On Thursday 02 May 2013, Linus Walleij wrote:
> > How do those drivers get to the SYSCON base address? Should they
> > be using drivers/mfd/syscon.c as the multiplexor instead?
> 
> No, there is no mutex to be taken. The consecutive range of memory
> addresses are used by different things (mainly the clocks) but there
> is no register that needs to be protected against access from two
> subsystems simultaneously.
> 
> As a follow-up to this series I plan to move also the U300 clocks
> to the device tree (similar three-step ladder as used for the Nomadik)
> and then they will (hopefully) get the syscon base address from the
> device tree.

I was less worried about mutexes than a correct representation
in the device tree. With the syscon driver, you can have the
register ranges described exactly once and just use the offsets
on the regmap in the other drivers.

	Arnd


From arnd at arndb.de  Thu May  2 13:52:34 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 19:52:34 +0200
Subject: [PATCH, RFC 16/22] USB: UHCI: clarify Kconfig dependencies
In-Reply-To: <Pine.LNX.4.44L0.1305021304500.1436-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305021304500.1436-100000@iolanthe.rowland.org>
Message-ID: <201305021952.35040.arnd@arndb.de>

On Thursday 02 May 2013, Alan Stern wrote:
> On Thu, 2 May 2013, Arnd Bergmann wrote:
> 
> 	It relies more on "depends" than "select".  I don't know how 
> 	important this is in the end.

'select' is sometimes problematic, but the only use that I try to
avoid is having one Kconfig symbol that is both user-selectable
standalone and selected by something else.

> 	It doesn't add a new USB_UHCI_GRLIB symbol; instead it uses
> 	SPARC_LEON in several places.  I tend to think the new symbol
> 	is nicer.
> 
> 	It doesn't add a new USB_UHCI_PCI symbol.
> 
> 	It improves the dependency list for USB_UHCI_HCD.
> 
> 	It removes the help text for USB_UHCI_PLATFORM, thereby making
> 	that symbol not user-configurable.  I don't see any reason why
> 	the user should need to worry about this -- the choice should
> 	be a very simple one: build UHCI support or don't build it.  If
> 	the user chooses to build it then it should include support for
> 	all the compatible bus glues.  (This last decision may need to 
> 	be changed if more bus glues get added.)
>
> What do you think of my patch as compared to yours? 

I think in the end it comes down to the question where you want to
head with your driver. The way I did my version was going towards
making it similar to EHCI, with stand-alone bus glue drivers
and a core that is just a library module but does not register
a device_driver by itself.

Given that there are just three bus glues from UHCI, and at most
two of them enabled at the same time, I don't see a direct need
for UHCI to go down the same route as EHCI. If you want to just
leave this driver alone, your patch is simpler and has the same
effect in the end. Otherwise I think my patch avoids changing it
all again once the driver gets reworked.

Things might also get a little messy if we are seeing a lot
of other platforms beside VIA VT8500 use UHCI, but I think that
is rather unlikely.

	Arnd


From arnd at arndb.de  Thu May  2 13:55:08 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 19:55:08 +0200
Subject: [PATCH, RFC 15/22] USB: EHCI: remove bogus #error
In-Reply-To: <Pine.LNX.4.44L0.1305021333020.1436-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305021333020.1436-100000@iolanthe.rowland.org>
Message-ID: <201305021955.08470.arnd@arndb.de>

On Thursday 02 May 2013, Alan Stern wrote:
> On Thu, 2 May 2013, Arnd Bergmann wrote:
> 
> > The EHCI host controller driver can be built standalone now,
> > without enabling any of the available bus glue drivers, so
> > there is not really a reason to error out here:
> 
> On the other hand, there's no reason to build the driver without any 
> bus glue.  It wouldn't do anything.

Yes, as I mention below, we could also use Kconfig logic to prevent
that case, as the OHCI and UHCI patches from this series do, but I felt
that would be a lot of unnecessary churn, and having just ehci-hci.ko
enabled without a bus glue is not an error, it's just as pointless
as most of the other drivers we get with "make randconfig".

> > drivers/usb/host/ehci-hcd.c:1303:2: error:
> >  #error "missing bus glue for ehci-hcd"  #error "missing bus glue for ehci-hcd"
> > 
> > The alternative would be to change the Kconfig code to build
> > the ehci-hcd module only if any of the symbols below are
> > in fact enabled.

	Arnd


From linux at arm.linux.org.uk  Thu May  2 13:55:24 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 18:55:24 +0100
Subject: [PATCH] ARM: smp: call platform's cpu_die in ipi_cpu_stop
In-Reply-To: <CAL_JsqLFEF9o7SSCcU5isxRdKA+fQNkqOmAncOmtzeMW7KbMrA@mail.gmail.com>
References: <1365251824-4852-1-git-send-email-kevin@bracey.fi>
 <1365251824-4852-2-git-send-email-kevin@bracey.fi>
 <20130418171801.GC14496@n2100.arm.linux.org.uk>
 <20130418182534.GD14496@n2100.arm.linux.org.uk>
 <20130418190923.GE14496@n2100.arm.linux.org.uk>
 <CAL_JsqLFEF9o7SSCcU5isxRdKA+fQNkqOmAncOmtzeMW7KbMrA@mail.gmail.com>
Message-ID: <20130502175524.GX14496@n2100.arm.linux.org.uk>

On Wed, May 01, 2013 at 08:06:56AM -0500, Rob Herring wrote:
> On Thu, Apr 18, 2013 at 2:09 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Thu, Apr 18, 2013 at 07:25:34PM +0100, Russell King - ARM Linux wrote:
> >> On Thu, Apr 18, 2013 at 06:18:01PM +0100, Russell King - ARM Linux wrote:
> >> > On Sat, Apr 06, 2013 at 03:37:04PM +0300, Kevin Bracey wrote:
> 
> [...]
> 
> >> Now, with this patch applied, we guarantee that we push out any data
> >> that matters from the dying CPU before platform_cpu_kill() is called.
> >> That should mean that shmobile can remove that whole cpu_dead thing.
> >>
> >> I've tested this on OMAP, and it appears to work from a simple test of
> >> CPU hotplug.  This patch(set) also kills the cpu_disable() that tegra
> >> has which is just a copy of the generic version.
> >
> > Okay, last version for tonight, with additional comments too, and a
> > hole plugged if the powering down is done by the platform via
> > cpu_die().
> >
> >  arch/arm/kernel/smp.c               |   42 +++++++++++++++++++++++++++++++---
> >  arch/arm/mach-exynos/hotplug.c      |    1 -
> >  arch/arm/mach-highbank/hotplug.c    |    4 ---
> 
> Looks like this just landed in -next and it breaks highbank build.
> Run-time will also be broken. See the last commit to this file in
> final 3.9 which will also conflict with this one. The problem is that
> highbank_set_cpu_jump calls outer cache functions which take a
> spinlock and pollute the L1 cache. This all goes away once PCSI
> support goes in, but for now we need another spot to clear the jump
> address or just drop the highbank change.

If that's the case then what you currently have is dangerous.  There
is no guarantee that the results of touching those locks will get
flushed out of the L1 cache of the going-down CPU - you _could_ end
up with the result of the lock being flushed out but not the unlock,
which would lead to a system deadlock.

The only thing which has changed as far as highbank is concerned is
that it will now use flush_cache_louis() rather than flush_cache_all()
before calling highbank_set_cpu_jump().

So, I think this has merely uncovered a latent bug in your code. :)


From arnd at arndb.de  Thu May  2 13:57:33 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 19:57:33 +0200
Subject: [PATCH, RFC 22/22] radio-si4713: depend on SND_SOC
In-Reply-To: <5182A44E.7080701@redhat.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-23-git-send-email-arnd@arndb.de>
 <5182A44E.7080701@redhat.com>
Message-ID: <201305021957.33657.arnd@arndb.de>

On Thursday 02 May 2013, Mauro Carvalho Chehab wrote:
> Do you prefer to send it via your tree or via mine? Either way works for me.
> 
> If you're willing to send it via your tree:
> 
> Acked-by: Mauro Carvalho Chehab <mchehab at redhat.com>

I'd prefer your tree, because the patch does not apply on 3.9.

	Arnd


From linux at arm.linux.org.uk  Thu May  2 14:02:37 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:02:37 +0100
Subject: [PATCH] arm: mm: Use phys_addr_t properly for ioremap functions
In-Reply-To: <1366761098-4485-1-git-send-email-lauraa@codeaurora.org>
References: <1366761098-4485-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <20130502180237.GY14496@n2100.arm.linux.org.uk>

On Tue, Apr 23, 2013 at 04:51:38PM -0700, Laura Abbott wrote:
> -	unsigned long last_addr;
> - 	unsigned long offset = phys_addr & ~PAGE_MASK;
> +	phys_addr_t last_addr;
> +	phys_addr_t offset = phys_addr & ~PAGE_MASK;

BTW, this doesn't need to be phys_addr_t.  An offset of a page is always
less than 32-bits.


From arnd at arndb.de  Thu May  2 14:03:26 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 20:03:26 +0200
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <51829D65.7040109@ti.com>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com> <51829D65.7040109@ti.com>
Message-ID: <201305022003.27037.arnd@arndb.de>

On Thursday 02 May 2013, Eduardo Valentin wrote:
> index e3c0ae9..e3f3cba 100644
> --- a/include/linux/thermal.h
> +++ b/include/linux/thermal.h
> @@ -250,12 +250,6 @@ void thermal_unregister_governor(struct
> thermal_governor *);
>  #ifdef CONFIG_NET
>  extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>                                                 enum events event);
> -#else
> -static int thermal_generate_netlink_event(struct thermal_zone_device *tz,
> -                                               enum events event)
> -{
> -       return 0;
> -}
>  #endif

Actually it seems this bug is already fixed in linux-next:

commit f8b587055a793c7719f0d4f41b7b4aeeef43aa2d
Author: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Date:   Wed Mar 20 21:38:07 2013 +0000

    thermal: Fix compiler warning
    
    The following warning is obtained when CONFIG_NET is not defined:
    
    In file included from drivers/thermal/mvebu_thermal.c:27:0:
    include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event'
    defined but not used [-Wunused-function]
    
    This patch fixes the warning by properly inlining
    thermal_generate_netlink_event().
    
    Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
    Signed-off-by: Zhang Rui <rui.zhang at intel.com>

diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index f0bd7f9..fd7b8f3 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -251,7 +251,7 @@ void thermal_unregister_governor(struct thermal_governor *);
 extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
                                                enum events event);
 #else
-static int thermal_generate_netlink_event(struct thermal_zone_device *tz,
+static inline int thermal_generate_netlink_event(struct thermal_zone_device *tz,
                                                enum events event)
 {
        return 0;


Your patch also seems correct, but it would conflict with Ezequiel's.
The problem was apparently that you removed the 'inline' keyword
in 8ab3e6a08a "thermal: Use thermal zone device id in netlink messages",
I assume by accident, since defining a non-inline function in a header
file is obviously wrong.

	Arnd


From linux at arm.linux.org.uk  Thu May  2 14:05:35 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:05:35 +0100
Subject: [PATCH -v7 0/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <20130502033952.GU3658@sgi.com>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <20130501231347.GT14496@n2100.arm.linux.org.uk>
 <20130502033952.GU3658@sgi.com>
Message-ID: <20130502180535.GZ14496@n2100.arm.linux.org.uk>

On Wed, May 01, 2013 at 10:39:52PM -0500, Robin Holt wrote:
> On Thu, May 02, 2013 at 12:13:47AM +0100, Russell King - ARM Linux wrote:
> > On Wed, May 01, 2013 at 12:06:40PM -0500, Robin Holt wrote:
> > > Andrew, Please do _NOT_ take this patch series yet.  I am sending this
> > > to you because you had comments on my -v6 submission.
> > 
> > Another reason for not applying this is that I believe it wilfully breaks
> > a bunch of ARM platforms - such as removing the 'g' reboot mode (for gpio
> > based reboot on PXA), and removing the 's' reboot mode off a bunch of ARM
> > platforms which have no way to do a hard reboot.
> 
> I am not sure what your basis for this statement is.

Probably old understanding of the code, and me getting old and getting
forgetful. :(


From balbi at ti.com  Thu May  2 14:06:27 2013
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 2 May 2013 21:06:27 +0300
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <51829D65.7040109@ti.com>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com> <51829D65.7040109@ti.com>
Message-ID: <20130502180627.GA10672@arwen.pp.htv.fi>

Hi,

On Thu, May 02, 2013 at 01:07:49PM -0400, Eduardo Valentin wrote:
> Arnd, Tony,
> 
> On 02-05-2013 11:38, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux at arm.linux.org.uk> [130502 01:27]:
> >> On Tue, Apr 30, 2013 at 09:17:39AM +0100, Russell King - ARM Linux wrote:
> >>> Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> >>> great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> >>> arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> >>> source of errors.
> >>>
> >>> OMAP stuff needs a serious look at too - much Kconfig madness there
> >>> caused by over-use of select, which then goes on to cause build errors
> >>> because it assumes some stuff is always enabled.
> >>>
> >>> There's also warnings about of_device_id from include/linux/of_platform.h
> >>> via from arch/arm/kernel/setup.c which feature in all the non-OF builds
> >>> too which need addressing.
> >>>
> >>> See todays http://www.arm.linux.org.uk/developer/build/ results for all
> >>> the details and configs.  Not pushing my tree until some of this stuff
> >>> gets fixed.
> >>
> >> And now we have a new bunch of warnings from OMAP stuff which weren't
> >> previously there...
> >>
> >> arch/arm/mach-omap2/omap_device.c: In function 'omap_device_get_by_hwmod_name':
> >> arch/arm/mach-omap2/omap_device.c:821:3: warning: return makes pointer from integer without a cast
> >> arch/arm/mach-omap2/omap_device.c:826:3: warning: return makes pointer from integer without a cast
> > 
> > Hmm these I already fixed earlier along with a merge resolution, and
> > I'm not seeing them in next/master or arm-soc/for-next. What do you
> > have merged into your current tree?
> > 
> >> drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
> >> drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result
> > 
> > Neil, care to provide a fix for this? It's from your commit ab37813
> > (twl4030_charger: Allow charger to control the regulator that feeds it).
> > 
> >> include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event' defined but not used
> > 
> > Eduardo, can you fix that one? It seems to be from your commit 8ab3e6a
> > (thermal: Use thermal zone device id in netlink messages).
> 
> Yeah sure I can fix it. As simple as the following:
> From c04244c87312f5bfc61d9e12ba3fbaa0fdd81adb Mon Sep 17 00:00:00 2001
> From: Eduardo Valentin <eduardo.valentin at ti.com>
> Date: Thu, 2 May 2013 12:58:20 -0400
> Subject: [PATCH 1/1] thermal: remove stub for thermal_generate_netlink_event
> 
> This patch removes the stub for thermal_generate_netlink_event
> because this function is not used anywhere inside the kernel.
> 
> In case CONFIG_NET is not set we get:
> include/linux/thermal.h:254:12: warning:
> 'thermal_generate_netlink_event' defined but not used
> 
> Thus removing it.
> 
> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
> ---
>  include/linux/thermal.h | 6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/include/linux/thermal.h b/include/linux/thermal.h
> index e3c0ae9..e3f3cba 100644
> --- a/include/linux/thermal.h
> +++ b/include/linux/thermal.h
> @@ -250,12 +250,6 @@ void thermal_unregister_governor(struct
> thermal_governor *);
>  #ifdef CONFIG_NET
>  extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>  						enum events event);
> -#else
> -static int thermal_generate_netlink_event(struct thermal_zone_device *tz,

just adding 'inline' would be an easier patch and lets you compile fine
on !CONFIG_NET when you starting using thermal_generate_netlink_event().

-- 
balbi
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From jjo.braun at gmail.com  Thu May  2 14:00:24 2013
From: jjo.braun at gmail.com (Johannes Braun)
Date: Thu, 2 May 2013 20:00:24 +0200
Subject: Freescale imx35: sgtl5000 codec not working over i2c
Message-ID: <20130502200024.72c112cc@jobraun>

Hello @all,

I hope this is the right place for my problem. Currently I am trying to
get a sigmatel sgtl5000 codec to work on a Freescale imx35 based board.
I am using a vanilla kernel 3.7.10. The codec is connected via i2c. I
configured the i2c device in /arch/arm/mach-imx/mach-proxmobil2.c.
Proxmobil2 is the name of our device. Here is the part which configures
the i2c device and the bus.

static const struct imxi2c_platform_data mx35_prox2_i2c0_data
	__initconst = {
        .bitrate = 100000,
};

imx35_add_imx_i2c0(&mx35_prox2_i2c0_data);

static struct i2c_board_info __initdata i2c_devices_prox2[] = {
        {
                I2C_BOARD_INFO("imx-audio-sgtl5000", 0x0a),
        },
};

i2c_register_board_info(0, i2c_devices_prox2,
	ARRAY_SIZE(i2c_devices_prox2));


The i2c bus is working correctly. I can scan the bus in uboot and in
linux with i2cdetect. In both cases a device with the address 0x0a is
found. This is the address of the sgtl5000 codec. The device is also
present in /sys/bus/i2c/devices.The audio codec is the only device on
the bus.

I tested the data and clock line with a oszilloscope while booting
linux. There was no activity. But when I scan the bus via uboot or via
i2cdetect I can seen that there is action on the bus. Also the power
supply for the codec looks good. I measured 3.3 V. So I think it is not
a problem with the wiring. 

The problem I is that the driver imx-audio-sgtl5000 does not start. I
tested it with some printk outputs in its probe method. But the probe
method is never called.

Then I thought, maybe it is a it is a problem with my board
configuration file. So I tested the codec on the Freescale imx35 3stack
eval board. But without success. This try ends with the same result. No
driver was loaded, alsa did not detect a soundcard and so on.

The result is a non working audio codec on the board. Shure I can use
the Freescale kernel. But this kernel I to old. I think it is a
2.6.28 kernel. I want to use an actual kernel with the board. So maybe
someone has a running sgtl5000 code in combination with a imx35 board.
I am grateful for tips. Thanks for reading.

---
Johannes



From konrad.wilk at oracle.com  Thu May  2 14:13:09 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Thu, 2 May 2013 14:13:09 -0400
Subject: [PATCH, RFC 18/22] Xen: SWIOTLB is only used on x86
In-Reply-To: <alpine.DEB.2.02.1305021638100.5398@kaball.uk.xensource.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-19-git-send-email-arnd@arndb.de>
 <alpine.DEB.2.02.1305021638100.5398@kaball.uk.xensource.com>
Message-ID: <20130502181309.GA23642@phenom.dumpdata.com>

On Thu, May 02, 2013 at 04:38:50PM +0100, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Arnd Bergmann wrote:
> > Enabling SWIOTLB_XEN on ARM results in build errors because the
> > underlying SWIOTLB is only available on X86:
> > 
> > drivers/xen/swiotlb-xen.c: In function 'is_xen_swiotlb_buffer':
> > drivers/xen/swiotlb-xen.c:105:2: error: implicit declaration of function 'mfn_to_local_pfn
> > 
> > Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> > Cc: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> 
> Acked-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

Acked as well. Should I pull this in or Arnd are you OK with taking
with my our Acks?

Thanks.
> 
> 
> >  drivers/xen/Kconfig | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
> > index dd4d9cb..f03bf50 100644
> > --- a/drivers/xen/Kconfig
> > +++ b/drivers/xen/Kconfig
> > @@ -141,7 +141,7 @@ config XEN_GRANT_DEV_ALLOC
> >  
> >  config SWIOTLB_XEN
> >  	def_bool y
> > -	depends on PCI
> > +	depends on PCI && X86
> >  	select SWIOTLB
> >  
> >  config XEN_TMEM
> > -- 
> > 1.8.1.2
> > 


From arnd at arndb.de  Thu May  2 14:16:03 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 20:16:03 +0200
Subject: [PATCH, RFC 18/22] Xen: SWIOTLB is only used on x86
In-Reply-To: <20130502181309.GA23642@phenom.dumpdata.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <alpine.DEB.2.02.1305021638100.5398@kaball.uk.xensource.com>
 <20130502181309.GA23642@phenom.dumpdata.com>
Message-ID: <201305022016.03332.arnd@arndb.de>

On Thursday 02 May 2013, Konrad Rzeszutek Wilk wrote:
> On Thu, May 02, 2013 at 04:38:50PM +0100, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Arnd Bergmann wrote:
> > > Enabling SWIOTLB_XEN on ARM results in build errors because the
> > > underlying SWIOTLB is only available on X86:
> > > 
> > > drivers/xen/swiotlb-xen.c: In function 'is_xen_swiotlb_buffer':
> > > drivers/xen/swiotlb-xen.c:105:2: error: implicit declaration of function 'mfn_to_local_pfn
> > > 
> > > Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> > > Cc: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > 
> > Acked-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> 
> Acked as well. Should I pull this in or Arnd are you OK with taking
> with my our Acks?

I'd prefer you to take it through your tree.

Thanks,

	Arnd


From s.hauer at pengutronix.de  Thu May  2 14:18:21 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 2 May 2013 20:18:21 +0200
Subject: Freescale imx35: sgtl5000 codec not working over i2c
In-Reply-To: <20130502200024.72c112cc@jobraun>
References: <20130502200024.72c112cc@jobraun>
Message-ID: <20130502181821.GC31135@pengutronix.de>

On Thu, May 02, 2013 at 08:00:24PM +0200, Johannes Braun wrote:
> Hello @all,
> 
> I hope this is the right place for my problem. Currently I am trying to
> get a sigmatel sgtl5000 codec to work on a Freescale imx35 based board.
> I am using a vanilla kernel 3.7.10. The codec is connected via i2c. I
> configured the i2c device in /arch/arm/mach-imx/mach-proxmobil2.c.
> Proxmobil2 is the name of our device. Here is the part which configures
> the i2c device and the bus.
> 
> static const struct imxi2c_platform_data mx35_prox2_i2c0_data
> 	__initconst = {
>         .bitrate = 100000,
> };
> 
> imx35_add_imx_i2c0(&mx35_prox2_i2c0_data);
> 
> static struct i2c_board_info __initdata i2c_devices_prox2[] = {
>         {
>                 I2C_BOARD_INFO("imx-audio-sgtl5000", 0x0a),
>         },

The driver matches "sgtl5000", not "imx-audio-sgtl5000".

You should use devicetree support for new boards. The platform support
will vanish sooner or later.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at arm.linux.org.uk  Thu May  2 14:18:51 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:18:51 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
 <20130502171516.GA3040@mudshark.cambridge.arm.com>
 <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
Message-ID: <20130502181851.GB14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 06:20:32PM +0100, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Will Deacon wrote:
> > Hi Stefano,
> > 
> > On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> > > ping
> > 
> > Is this a ping to have this pulled into Russell's tree?
> 
> I thought that we agreed that the patches should go via the arm-soc
> tree, after Russell acks them.
> 
> The ping is for Russell to ack them and Arnd to merge them.

Sorry but I tend not to be around on Tuesdays and Wednesdays, which leads
to a hell of an email problem on Thursdays.  I haven't looked at them in
any great detail (I just paged through them so far and on to the next
email.)

I don't really have sufficient time to properly deal with all the email
traffic that is now on this list - even from just flicking through the
messages.  It's far too much.


From linux at arm.linux.org.uk  Thu May  2 14:20:20 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:20:20 +0100
Subject: [PATCH 3/4] ARM: fix NOMMU __arm_ioremap prototype
In-Reply-To: <1367515404-512212-4-git-send-email-arnd@arndb.de>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
 <1367515404-512212-4-git-send-email-arnd@arndb.de>
Message-ID: <20130502182020.GC14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 07:23:23PM +0200, Arnd Bergmann wrote:
> The declaration of __arm_ioremap has changed to take a phys_addr_t
> as the first argument, while the definition for nommu has not
> changed. This adds the obvious change.

I've now dropped the offending patch from Laura which created this problem
(and from what it looks like other problems elsewhere).

It would be much better to have one patch which addresses this properly
rather than one patch causing a problem and then lots of smaller patches
fixing the problems caused by the first patch.


From stefano.stabellini at eu.citrix.com  Thu May  2 14:23:11 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 19:23:11 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce
 psci_smp_ops
In-Reply-To: <20130502181851.GB14496@n2100.arm.linux.org.uk>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
 <20130502171516.GA3040@mudshark.cambridge.arm.com>
 <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
 <20130502181851.GB14496@n2100.arm.linux.org.uk>
Message-ID: <alpine.DEB.2.02.1305021920070.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Russell King - ARM Linux wrote:
> On Thu, May 02, 2013 at 06:20:32PM +0100, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Will Deacon wrote:
> > > Hi Stefano,
> > > 
> > > On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> > > > ping
> > > 
> > > Is this a ping to have this pulled into Russell's tree?
> > 
> > I thought that we agreed that the patches should go via the arm-soc
> > tree, after Russell acks them.
> > 
> > The ping is for Russell to ack them and Arnd to merge them.
> 
> Sorry but I tend not to be around on Tuesdays and Wednesdays, which leads
> to a hell of an email problem on Thursdays.  I haven't looked at them in
> any great detail (I just paged through them so far and on to the next
> email.)

No problems, if there is one person that can understand being flooded by
emails, that's me.


> I don't really have sufficient time to properly deal with all the email
> traffic that is now on this list - even from just flicking through the
> messages.  It's far too much.

This patches have been discussed in great details, would you be content
with Will Deacon and Nicolas Pitre's Acks?
Nobody objected again them so far.


From swarren at wwwdotorg.org  Thu May  2 14:25:07 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 02 May 2013 12:25:07 -0600
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <201304300004.20320.arnd@arndb.de>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <1556968.7tR6KuEIWb@flatron> <6607610.omg016OAvj@avalon>
 <201304300004.20320.arnd@arndb.de>
Message-ID: <5182AF83.4080705@wwwdotorg.org>

On 04/29/2013 04:04 PM, Arnd Bergmann wrote:
> On Monday 29 April 2013, Laurent Pinchart wrote:
>> On Monday 29 April 2013 23:31:30 Tomasz Figa wrote:
>>
>>> Good point. Stephen, would it be a problem to make this a KMS driver
>>> instead? Old fbdev API could be emulated on top of it, until it goes out
>>> of use, couldn't it?
>>
>> There's already an fbdev emulation layer in KMS, for such a simple use case it 
>> will work fine.
> 
> I suggested the same to Stephen when he first brought up this driver.
> Unfortunately his attempt to create a simple KMS driver resulted in a
> significantly larger driver than the one he did for the framebuffer
> interface. This means that either Stephen did something really wrong
> in his attempt, or the KMS interface isn't as good as it should be
> if we want to move people away from frame buffer drivers.

Well, I didn't actually attempt to write the KMS driver; I simply took a
look at existing KMS drivers (and perhaps some stub KMS driver; I forget
right now) to see what it'd take, and it looked quite scary.

The other issue is that the KMS semantics appear to desire that the
driver allocate FB memory from some pool, and then point the display
scanout at the allocated memory. However, this driver's semantics are
that some other entity has allocated and reserved some memory region for
scanout, and the simple FB driver exists solely to scribble to that
memory region. Rob Clark said the thought this could be handled by
writing a custom memory allocator to support this, but it seemed a
little pointless to write a whole memory allocator when the existing FB
interface allows the driver to just set a struct member to the address
and be done with it.


From sebastian.hesselbarth at gmail.com  Thu May  2 14:25:04 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu,  2 May 2013 20:25:04 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
Message-ID: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
Corresponding device tree documentation is also added.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: This patch triggers a checkpatch warning for
  WARNING: Avoid CamelCase: <handle_IRQ>

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 .../interrupt-controller/marvell,orion-mpic.txt    |   22 ++++
 drivers/irqchip/Kconfig                            |    5 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-orion.c                        |  129 ++++++++++++++++++++
 include/linux/irqchip/orion.h                      |   18 +++
 5 files changed, 175 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt
 create mode 100644 drivers/irqchip/irq-orion.c
 create mode 100644 include/linux/irqchip/orion.h

diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt
new file mode 100644
index 0000000..3b303ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt
@@ -0,0 +1,22 @@
+Marvell Orion SoC main interrupt controller
+
+Required properties:
+- compatible: shall be "marvell,orion-mpic"
+- reg: base address(es) of interrupt registers starting with CAUSE register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1.
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of first base address,
+- 1 maps to bit 1 of first base address,
+- 32 maps to bit 0 of second base address, and so on.
+
+Example:
+	intc: interrupt-controller {
+		compatible = "marvell,orion-mpic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+                /* Dove has 64 primary interrupts */
+		reg = <0x20200 0x10>, <0x20210 0x10>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a350969..8da3559 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -2,6 +2,11 @@ config IRQCHIP
 	def_bool y
 	depends on OF_IRQ
 
+config IRQCHIP_ORION
+	bool
+	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
+
 config ARM_GIC
 	bool
 	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 98e3b87..8adbd43 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
+obj-$(CONFIG_IRQCHIP_ORION)		+= irq-orion.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi.o
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
new file mode 100644
index 0000000..ea02e11
--- /dev/null
+++ b/drivers/irqchip/irq-orion.c
@@ -0,0 +1,129 @@
+/*
+ * Marvell Orion SoCs IRQ chip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/orion.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/mach/irq.h>
+
+/* max number of handled irq register blocks */
+#define ORION_MAX_IRQREG		2
+
+#define ORION_IRQ_CAUSE			0x00
+#define ORION_IRQ_MASK			0x04
+#define ORION_IRQ_FIQ_MASK		0x08
+#define ORION_IRQ_ENDP_MASK		0x0c
+
+static void __iomem *orion_irq_base[ORION_MAX_IRQREG];
+static unsigned int orion_irq_regs;
+static struct irq_domain *orion_irq_domain;
+
+asmlinkage void __exception_irq_entry orion_handle_irq(struct pt_regs *regs)
+{
+	int n;
+	for (n = 0; n < orion_irq_regs; n++) {
+		u32 hwirq_base = n * 32;
+		u32 stat = readl_relaxed(orion_irq_base[n] + ORION_IRQ_CAUSE) &
+			   readl_relaxed(orion_irq_base[n] + ORION_IRQ_MASK);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			u32 irq = irq_find_mapping(orion_irq_domain,
+						hwirq_base + hwirq);
+			handle_IRQ(irq, regs);
+			stat &= ~(1 << hwirq);
+		}
+	}
+}
+
+static void orion_irq_mask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
+	writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
+}
+
+static void orion_irq_unmask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
+	writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
+}
+
+static struct irq_chip orion_irq_chip = {
+	.name		= "orion_irq",
+	.irq_mask	= orion_irq_mask,
+	.irq_unmask	= orion_irq_unmask,
+};
+
+static int orion_irq_map(struct irq_domain *d, unsigned int virq,
+			 irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &orion_irq_chip,
+				 handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops orion_irq_ops = {
+	.map = orion_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init orion_of_init(struct device_node *np,
+				struct device_node *parent)
+{
+	int n;
+
+	for (n = 0; n < ORION_MAX_IRQREG; n++) {
+		orion_irq_base[n] = of_iomap(np, n);
+
+		if (!orion_irq_base[n])
+			continue;
+
+		/* mask all interrupts */
+		writel(0, orion_irq_base[n] + ORION_IRQ_MASK);
+		orion_irq_regs++;
+	}
+
+	/* at least one irq reg must be set */
+	if (!orion_irq_regs)
+		panic("%s: unable to map IRQC registers\n", np->full_name);
+
+	orion_irq_domain = irq_domain_add_linear(np, orion_irq_regs * 32,
+						 &orion_irq_ops, NULL);
+	if (!orion_irq_domain)
+		panic("%s: unable to create IRQ domain\n", np->full_name);
+
+	set_handle_irq(orion_handle_irq);
+
+	return 0;
+}
+
+static struct of_device_id orion_irq_dt_ids[] __initconst = {
+	{ .compatible = "marvell,orion-mpic", .data = orion_of_init },
+	{ }
+};
+
+void __init orion_init_irq(void)
+{
+	of_irq_init(orion_irq_dt_ids);
+}
diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
new file mode 100644
index 0000000..04f7bab
--- /dev/null
+++ b/include/linux/irqchip/orion.h
@@ -0,0 +1,18 @@
+/*
+ * Marvell Orion SoCs IRQ chip driver header.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_IRQCHIP_ORION_H
+#define __LINUX_IRQCHIP_ORION_H
+
+#include <asm/exception.h>
+
+extern void orion_init_irq(void);
+
+#endif
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Thu May  2 14:25:37 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu,  2 May 2013 20:25:37 +0200
Subject: [PATCH 0/3] ARM: dove: prepare and move to orion irqchip driver
Message-ID: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set moves Dove to the recently introduced irqchip driver
for Marvell Orion SoCs. First, init code for timer and mv643xx_eth
is added to prepare legacy non-DT drivers for virtual irqs provided by
irqchip drivers. Then DT enabled boards for Dove are moved to the
orion irqchip driver.

Note: This patch set depends on irqchip driver for Orion SoCs patch.

Sebastian Hesselbarth (3):
  ARM: dove: add DT parsing for legacy mv643xx_eth
  ARM: dove: add DT parsing for legacy timer
  ARM: dove: move DT boards to orion irqchip driver

 arch/arm/boot/dts/dove.dtsi   |   18 ++++++++-
 arch/arm/mach-dove/Kconfig    |    1 +
 arch/arm/mach-dove/Makefile   |    4 +-
 arch/arm/mach-dove/board-dt.c |   77 ++++++++++++++++++++++++++++++++++++-----
 4 files changed, 87 insertions(+), 13 deletions(-)
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Thu May  2 14:25:38 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu,  2 May 2013 20:25:38 +0200
Subject: [PATCH 1/3] ARM: dove: add DT parsing for legacy mv643xx_eth
In-Reply-To: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367519140-19716-2-git-send-email-sebastian.hesselbarth@gmail.com>

To allow to move to orion irqchip driver, existing legacy devices
have to map their irqs. This patch adds a node for mv643xx_eth and
some init code to map the corresponding irqs. While the device tree
node can stay, the init code will vanish as soon as there is true
device tree support for mv643xx_eth.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove.dtsi   |    7 +++++++
 arch/arm/mach-dove/board-dt.c |   31 ++++++++++++++++++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index f7509ca..ea7c5da 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -197,6 +197,13 @@
 			status = "disabled";
 		};
 
+		gbe: ethernet-controller {
+			compatible = "marvell,mv643xx-eth-block";
+			reg = <0x72000 0x4000>;
+			interrupts = <29>, <30>;
+			status = "disabled";
+		};
+
 		rtc at d8500 {
 			compatible = "marvell,orion-rtc";
 			reg = <0xd8500 0x20>;
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd..9df6dd7 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -12,6 +12,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <asm/hardware/cache-tauros2.h>
@@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
 	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
 };
 
+#define DOVE_GE00_PHYS_BASE	0xf1070000
+
+static void __init dove_legacy_ge00_init(void)
+{
+	struct device_node *np = of_find_compatible_node(NULL, NULL,
+					 "marvell,mv643xx-eth-block");
+	int irq_sum, irq_err;
+
+	if (!np)
+		return;
+
+	irq_sum = irq_of_parse_and_map(np, 0);
+	if (!irq_sum) {
+		pr_err("%s: missing sum irq\n", np->full_name);
+		return;
+	}
+
+	irq_err = irq_of_parse_and_map(np, 1);
+	if (!irq_err) {
+		pr_err("%s: missing err irq\n", np->full_name);
+		return;
+	}
+
+	/* legacy ge00_init wants phys base */
+	orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
+			irq_sum, irq_err, 1600);
+}
+
 static void __init dove_dt_init(void)
 {
 	pr_info("Dove 88AP510 SoC\n");
@@ -70,7 +99,7 @@ static void __init dove_dt_init(void)
 	dove_of_clk_init();
 
 	/* Internal devices not ported to DT yet */
-	dove_ge00_init(&dove_dt_ge00_data);
+	dove_legacy_ge00_init();
 	dove_pcie_init(1, 1);
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Thu May  2 14:25:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu,  2 May 2013 20:25:40 +0200
Subject: [PATCH 3/3] ARM: dove: move DT boards to orion irqchip driver
In-Reply-To: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367519140-19716-4-git-send-email-sebastian.hesselbarth@gmail.com>

With legacy devices mapping their irqs, we can now switch DT enabled
boards to orion irqchip driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove.dtsi   |    4 ++--
 arch/arm/mach-dove/Kconfig    |    1 +
 arch/arm/mach-dove/Makefile   |    4 ++--
 arch/arm/mach-dove/board-dt.c |    4 ++--
 4 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 433cca1..8ba528a 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -38,10 +38,10 @@
 		};
 
 		intc: interrupt-controller {
-			compatible = "marvell,orion-intc";
+			compatible = "marvell,orion-mpic";
 			interrupt-controller;
 			#interrupt-cells = <1>;
-			reg = <0x20204 0x04>, <0x20214 0x04>;
+			reg = <0x20200 0x04>, <0x20210 0x04>;
 		};
 
 		core_clk: core-clocks at d0214 {
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d8..60d72b4 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,6 +22,7 @@ config MACH_CM_A510
 
 config MACH_DOVE_DT
 	bool "Marvell Dove Flattened Device Tree"
+	select IRQCHIP_ORION
 	select MVEBU_CLK_CORE
 	select MVEBU_CLK_GATING
 	select REGULATOR
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 3f0a858..4780f78 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,5 +1,5 @@
-obj-y				+= common.o addr-map.o irq.o
-obj-$(CONFIG_DOVE_LEGACY)	+= mpp.o
+obj-y				+= common.o addr-map.o
+obj-$(CONFIG_DOVE_LEGACY)	+= irq.o mpp.o
 obj-$(CONFIG_PCI)		+= pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)	+= dove-db-setup.o
 obj-$(CONFIG_MACH_DOVE_DT)	+= board-dt.o
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index cea65b7..b6734b9 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
+#include <linux/irqchip/orion.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -20,7 +21,6 @@
 #include <asm/mach/arch.h>
 #include <mach/pm.h>
 #include <plat/common.h>
-#include <plat/irq.h>
 #include <plat/time.h>
 #include "common.h"
 
@@ -143,7 +143,7 @@ static const char * const dove_dt_board_compat[] = {
 
 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
 	.map_io		= dove_map_io,
-	.init_irq	= orion_dt_init_irq,
+	.init_irq	= orion_init_irq,
 	.init_time	= dove_legacy_timer_init,
 	.init_machine	= dove_dt_init,
 	.restart	= dove_restart,
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Thu May  2 14:25:39 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu,  2 May 2013 20:25:39 +0200
Subject: [PATCH 2/3] ARM: dove: add DT parsing for legacy timer
In-Reply-To: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367519140-19716-3-git-send-email-sebastian.hesselbarth@gmail.com>

To allow to move to orion irqchip driver, existing legacy devices
have to map their irqs. This patch adds a node for orion timer and
some init code to map the corresponding irqs. While the device tree
node can stay, the init code will vanish as soon as there is true
device tree support for orion timer.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove.dtsi   |    7 ++++++
 arch/arm/mach-dove/board-dt.c |   42 +++++++++++++++++++++++++++++++++++-----
 2 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index ea7c5da..433cca1 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -30,6 +30,13 @@
 			marvell,tauros2-cache-features = <0>;
 		};
 
+		timer: timer {
+			compatible = "marvell,orion-timer";
+			reg = <0x20300 0x20>;
+			interrupts = <0>;
+			clocks = <&core_clk 0>;
+		};
+
 		intc: interrupt-controller {
 			compatible = "marvell,orion-intc";
 			interrupt-controller;
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 9df6dd7..cea65b7 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -12,6 +12,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -20,6 +21,7 @@
 #include <mach/pm.h>
 #include <plat/common.h>
 #include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 
 /*
@@ -48,10 +50,42 @@ static void __init dove_legacy_clk_init(void)
 			 of_clk_get_from_provider(&clkspec));
 }
 
-static void __init dove_of_clk_init(void)
+#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
+
+static void __init dove_legacy_timer_init(void)
 {
+	struct device_node *np = of_find_compatible_node(NULL, NULL,
+					 "marvell,orion-timer");
+	struct clk *clk;
+	void __iomem *base;
+	unsigned int tclk, irq;
+
+	/* Setup root of clk tree */
 	mvebu_clocks_init();
 	dove_legacy_clk_init();
+
+	if (!np)
+		panic("missing timer node\n");
+
+	base = of_iomap(np, 0);
+	if (!base)
+		panic("%s: missing reg base for timer\n", np->full_name);
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq)
+		panic("%s: missing irq for timer\n", np->full_name);
+
+	clk = of_clk_get(np, 0);
+	if (IS_ERR(clk))
+		panic("%s: missing clock for timer\n", np->full_name);
+
+	clk_prepare_enable(clk);
+	tclk = clk_get_rate(clk);
+	clk_put(clk);
+
+	orion_time_set_base(base);
+	/* legacy timer init gets bridge reg base */
+	orion_time_init(base - 0x300, BRIDGE_INT_TIMER1_CLR, irq, tclk);
 }
 
 static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
@@ -95,9 +129,6 @@ static void __init dove_dt_init(void)
 #endif
 	dove_setup_cpu_mbus();
 
-	/* Setup root of clk tree */
-	dove_of_clk_init();
-
 	/* Internal devices not ported to DT yet */
 	dove_legacy_ge00_init();
 	dove_pcie_init(1, 1);
@@ -112,9 +143,8 @@ static const char * const dove_dt_board_compat[] = {
 
 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
 	.map_io		= dove_map_io,
-	.init_early	= dove_init_early,
 	.init_irq	= orion_dt_init_irq,
-	.init_time	= dove_timer_init,
+	.init_time	= dove_legacy_timer_init,
 	.init_machine	= dove_dt_init,
 	.restart	= dove_restart,
 	.dt_compat	= dove_dt_board_compat,
-- 
1.7.2.5



From stern at rowland.harvard.edu  Thu May  2 14:27:55 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 2 May 2013 14:27:55 -0400 (EDT)
Subject: [PATCH, RFC 16/22] USB: UHCI: clarify Kconfig dependencies
In-Reply-To: <201305021952.35040.arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305021423450.1436-100000@iolanthe.rowland.org>

On Thu, 2 May 2013, Arnd Bergmann wrote:

> > What do you think of my patch as compared to yours? 
> 
> I think in the end it comes down to the question where you want to
> head with your driver. The way I did my version was going towards
> making it similar to EHCI, with stand-alone bus glue drivers
> and a core that is just a library module but does not register
> a device_driver by itself.
> 
> Given that there are just three bus glues from UHCI, and at most
> two of them enabled at the same time, I don't see a direct need
> for UHCI to go down the same route as EHCI. If you want to just
> leave this driver alone, your patch is simpler and has the same
> effect in the end. Otherwise I think my patch avoids changing it
> all again once the driver gets reworked.

Okay then, I'll submit my patch to Greg after the merge window closes.

> Things might also get a little messy if we are seeing a lot
> of other platforms beside VIA VT8500 use UHCI, but I think that
> is rather unlikely.

Indeed.  UHCI is the oldest of the host controller standards; people
aren't about to start creating a whole bunch of new implementations of 
it.  Even Intel no longer uses UHCI on their more recent motherboards.

Alan Stern



From s.hauer at pengutronix.de  Thu May  2 14:27:59 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 2 May 2013 20:27:59 +0200
Subject: [PATCH 2/2] pinctrl/imx: add zero register offset valid for
 Vybrid platform
In-Reply-To: <1367480932-22318-2-git-send-email-b35083@freescale.com>
References: <1367480932-22318-1-git-send-email-b35083@freescale.com>
 <1367480932-22318-2-git-send-email-b35083@freescale.com>
Message-ID: <20130502182759.GQ32299@pengutronix.de>

On Thu, May 02, 2013 at 03:48:52PM +0800, Jingchang Lu wrote:
> On some platform such as Vybrid, offset of mux and pad ctrl register
> may be zero. This patch add a platform condition to imx core pinctrl
> framework, making zero register offset valid on setting mux_mode and
> pad config value.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
>  drivers/pinctrl/pinctrl-imx.c | 34 ++++++++++++++++++++++------------
>  1 file changed, 22 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
> index 4fcfff92..b4d7c91 100644
> --- a/drivers/pinctrl/pinctrl-imx.c
> +++ b/drivers/pinctrl/pinctrl-imx.c
> @@ -221,10 +221,14 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
>  		pin_id = pins[i];
>  		pin_reg = &info->pin_regs[pin_id];
>  
> -		if (!pin_reg->mux_reg) {
> -			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
> -				info->pins[pin_id].name);
> -			return -EINVAL;
> +		/* mux_reg offset maybe zero on some platform such as Vybrid */
> +		if (!of_machine_is_compatible("fsl,mvf600")) {
> +			if (!pin_reg->mux_reg) {

Please add a zero_offset_valid flag to the drivers private structure
instead of using a rather expensive function in a frequently used path.
Also the && operator can be used to test for two conditions being true.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at arm.linux.org.uk  Thu May  2 14:28:12 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:28:12 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
 <20130502171516.GA3040@mudshark.cambridge.arm.com>
 <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
Message-ID: <20130502182812.GD14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 06:20:32PM +0100, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Will Deacon wrote:
> > Hi Stefano,
> > 
> > On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> > > ping
> > 
> > Is this a ping to have this pulled into Russell's tree?
> 
> I thought that we agreed that the patches should go via the arm-soc
> tree, after Russell acks them.

Okay, well, is there a reason for them to go through arm-soc?  They
look more like core code to me than SoC specific - they only minimally
touch mach-virt.


From swarren at wwwdotorg.org  Thu May  2 14:31:05 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 02 May 2013 12:31:05 -0600
Subject: [RFC PATCH v2 13/13] ARM: DT: kernel: DT cpu node bindings update
In-Reply-To: <1366644455-16550-14-git-send-email-lorenzo.pieralisi@arm.com>
References: <1366644455-16550-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1366644455-16550-14-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <5182B0E9.3090006@wwwdotorg.org>

On 04/22/2013 09:27 AM, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.

Since I'm late reviewing this due to vacation, I imagine this has been
applied by now. But for the record, the structure of the DT binding
documentation in this version does look much better to me, and addresses
any concerns I had with v1.


From sebastian.hesselbarth at gmail.com  Thu May  2 14:33:48 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 20:33:48 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <5182B18C.4080404@gmail.com>

On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
> This patch adds an irqchip driver for the main interrupt controller found
> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
> Corresponding device tree documentation is also added.
>
> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> ---
> Note: This patch triggers a checkpatch warning for
>    WARNING: Avoid CamelCase:<handle_IRQ>
>
[...]
> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
> new file mode 100644
> index 0000000..04f7bab
> --- /dev/null
> +++ b/include/linux/irqchip/orion.h
> @@ -0,0 +1,18 @@
> +/*
> + * Marvell Orion SoCs IRQ chip driver header.
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __LINUX_IRQCHIP_ORION_H
> +#define __LINUX_IRQCHIP_ORION_H
> +
> +#include<asm/exception.h>

First review by myself. The above include is a left-over and
will be removed in a v2.

> +
> +extern void orion_init_irq(void);
> +
> +#endif



From geert at linux-m68k.org  Thu May  2 14:35:45 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 2 May 2013 20:35:45 +0200
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <5182AF83.4080705@wwwdotorg.org>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <1556968.7tR6KuEIWb@flatron> <6607610.omg016OAvj@avalon>
 <201304300004.20320.arnd@arndb.de> <5182AF83.4080705@wwwdotorg.org>
Message-ID: <CAMuHMdV9nv3FA8J4MPPyUjb1T_nDttV_X-KCSKP==K4g9sXj5w@mail.gmail.com>

On Thu, May 2, 2013 at 8:25 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 04/29/2013 04:04 PM, Arnd Bergmann wrote:
>> On Monday 29 April 2013, Laurent Pinchart wrote:
>>> On Monday 29 April 2013 23:31:30 Tomasz Figa wrote:
>>>
>>>> Good point. Stephen, would it be a problem to make this a KMS driver
>>>> instead? Old fbdev API could be emulated on top of it, until it goes out
>>>> of use, couldn't it?
>>>
>>> There's already an fbdev emulation layer in KMS, for such a simple use case it
>>> will work fine.
>>
>> I suggested the same to Stephen when he first brought up this driver.
>> Unfortunately his attempt to create a simple KMS driver resulted in a
>> significantly larger driver than the one he did for the framebuffer
>> interface. This means that either Stephen did something really wrong
>> in his attempt, or the KMS interface isn't as good as it should be
>> if we want to move people away from frame buffer drivers.
>
> Well, I didn't actually attempt to write the KMS driver; I simply took a
> look at existing KMS drivers (and perhaps some stub KMS driver; I forget
> right now) to see what it'd take, and it looked quite scary.
>
> The other issue is that the KMS semantics appear to desire that the
> driver allocate FB memory from some pool, and then point the display
> scanout at the allocated memory. However, this driver's semantics are
> that some other entity has allocated and reserved some memory region for
> scanout, and the simple FB driver exists solely to scribble to that
> memory region. Rob Clark said the thought this could be handled by
> writing a custom memory allocator to support this, but it seemed a
> little pointless to write a whole memory allocator when the existing FB
> interface allows the driver to just set a struct member to the address
> and be done with it.

I'm also curious to see the code for the first real simplekms/vesakms/ofkms/...
driver...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From jjo.braun at gmail.com  Thu May  2 14:40:20 2013
From: jjo.braun at gmail.com (Johannes Braun)
Date: Thu, 2 May 2013 20:40:20 +0200
Subject: Freescale imx35: sgtl5000 codec not working over i2c
In-Reply-To: <20130502181821.GC31135@pengutronix.de>
References: <20130502200024.72c112cc@jobraun>
 <20130502181821.GC31135@pengutronix.de>
Message-ID: <20130502204020.0462f080@jobraun>

Hello Sascha,

> On Thu, May 02, 2013 at 08:00:24PM +0200, Johannes Braun wrote:
> > Hello @all,
> > 
> > I hope this is the right place for my problem. Currently I am
> > trying to get a sigmatel sgtl5000 codec to work on a Freescale
> > imx35 based board. I am using a vanilla kernel 3.7.10. The codec is
> > connected via i2c. I configured the i2c device
> > in /arch/arm/mach-imx/mach-proxmobil2.c. Proxmobil2 is the name of
> > our device. Here is the part which configures the i2c device and
> > the bus.
> > 
> > static const struct imxi2c_platform_data mx35_prox2_i2c0_data
> > 	__initconst = {
> >         .bitrate = 100000,
> > };
> > 
> > imx35_add_imx_i2c0(&mx35_prox2_i2c0_data);
> > 
> > static struct i2c_board_info __initdata i2c_devices_prox2[] = {
> >         {
> >                 I2C_BOARD_INFO("imx-audio-sgtl5000", 0x0a),
> >         },
> 
> The driver matches "sgtl5000", not "imx-audio-sgtl5000".

I tried "sgtl5000" and "fsl", both without success.

> 
> You should use devicetree support for new boards. The platform support
> will vanish sooner or later.
> 

As I wrote before, my board is based on the very old imx35 processor
platform and I think this processor type does not support device tree
out of the box? Or is it possible to use a device tree with an imx35?
Haven`t seen this before. Is the problem realy the missing device tree
support? 

There are much reasons why I don`t want to spend that much time with
this old product. We had so much problems with this board and probably
in summer there is a new board coming. Maybe an im6q.

---
Johannes


From stefano.stabellini at eu.citrix.com  Thu May  2 14:42:58 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 2 May 2013 19:42:58 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce
 psci_smp_ops
In-Reply-To: <20130502182812.GD14496@n2100.arm.linux.org.uk>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
 <20130502171516.GA3040@mudshark.cambridge.arm.com>
 <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
 <20130502182812.GD14496@n2100.arm.linux.org.uk>
Message-ID: <alpine.DEB.2.02.1305021938170.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Russell King - ARM Linux wrote:
> On Thu, May 02, 2013 at 06:20:32PM +0100, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Will Deacon wrote:
> > > Hi Stefano,
> > > 
> > > On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> > > > ping
> > > 
> > > Is this a ping to have this pulled into Russell's tree?
> > 
> > I thought that we agreed that the patches should go via the arm-soc
> > tree, after Russell acks them.
> 
> Okay, well, is there a reason for them to go through arm-soc?  They
> look more like core code to me than SoC specific - they only minimally
> touch mach-virt.

The original reason is that some SoC specific code depends on this
series (Calxeda I believe).

But you are probably right, if you prefer that I issue a pull request
for your tree, I have no problems with that.


From rjw at sisk.pl  Thu May  2 14:53:44 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 02 May 2013 20:53:44 +0200
Subject: [PATCH, RFC 00/22] ARM randconfig bugs
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <2710056.LHQ0Ee0x8t@vostro.rjw.lan>

On Thursday, May 02, 2013 05:16:04 PM Arnd Bergmann wrote:
> Hi subsystem maintainers,
> 
> This is a set of patches to to fix build errors I hit while trying to
> build lots of randconfig kernels on linux-next.
> 
> Most of them are simple missing dependencies in Kconfig, but some are
> more substantial. I would like to see at least the obvious patches
> get merged for 3.10. If you are happy with the patches, feel free
> to apply them directly, otherwise please provide feedback.
> 
> No single patch out of these is very important though, most of them
> only concern corner cases and don't matter in practice.

For cpufreq and cpuidle:

Acked-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com>

> Arnd Bergmann (22):
>   can: move CONFIG_HAVE_CAN_FLEXCAN out of CAN_DEV
>   cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
>   cpuidle: calxeda: select ARM_CPU_SUSPEND
>   staging/drm: imx: add missing dependencies
>   drm: always provide debugfs function prototypes
>   gpu/drm: host1x: add dependency on Tegra
>   drm/tilcd: select BACKLIGHT_LCD_SUPPORT
>   OMAPDSS: DPI needs DSI
>   crypto: lz4: don't build on ARM
>   mfd: ab8500: debugfs code depends on gpadc
>   iwlegacy: il_pm_ops is only provided for PM_SLEEP
>   thermal: cpu_cooling: fix stub function
>   staging/logger: use kuid_t internally
>   oprofile: always enable IRQ_WORK
>   USB: EHCI: remove bogus #error
>   USB: UHCI: clarify Kconfig dependencies
>   USB: OHCI: clarify Kconfig dependencies
>   Xen: SWIOTLB is only used on x86
>   staging/solo6x10: depend on CONFIG_FONTS
>   media: coda: select GENERIC_ALLOCATOR
>   davinci: vpfe_capture needs i2c
>   radio-si4713: depend on SND_SOC
> 
>  arch/Kconfig                           |  1 +
>  crypto/Kconfig                         |  2 ++
>  drivers/cpufreq/Kconfig.arm            |  1 +
>  drivers/cpuidle/Kconfig                |  1 +
>  drivers/gpu/drm/tilcdc/Kconfig         |  1 +
>  drivers/gpu/host1x/drm/Kconfig         |  1 +
>  drivers/media/platform/Kconfig         |  1 +
>  drivers/media/platform/davinci/Kconfig |  3 ++
>  drivers/media/radio/Kconfig            |  1 +
>  drivers/mfd/Kconfig                    |  2 +-
>  drivers/net/can/Kconfig                |  6 ++--
>  drivers/net/wireless/iwlegacy/common.h |  2 +-
>  drivers/staging/android/logger.c       |  4 +--
>  drivers/staging/android/logger.h       |  2 +-
>  drivers/staging/imx-drm/Kconfig        |  4 +++
>  drivers/staging/media/solo6x10/Kconfig |  1 +
>  drivers/usb/host/Kconfig               | 65 +++++++++++++++++++++++++++++-----
>  drivers/usb/host/Makefile              |  4 +--
>  drivers/usb/host/ehci-hcd.c            | 17 ---------
>  drivers/usb/host/ohci-hcd.c            | 19 ----------
>  drivers/usb/host/uhci-hcd.c            |  4 +--
>  drivers/video/console/Makefile         |  2 ++
>  drivers/video/omap2/dss/Kconfig        |  1 +
>  drivers/xen/Kconfig                    |  2 +-
>  include/drm/drmP.h                     |  3 +-
>  include/linux/cpu_cooling.h            |  2 +-
>  26 files changed, 91 insertions(+), 61 deletions(-)
> 
> 
-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From eduardo.valentin at ti.com  Thu May  2 14:45:43 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 2 May 2013 14:45:43 -0400
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <201305022003.27037.arnd@arndb.de>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com> <51829D65.7040109@ti.com>
 <201305022003.27037.arnd@arndb.de>
Message-ID: <5182B457.5030009@ti.com>

On 02-05-2013 14:03, Arnd Bergmann wrote:
> On Thursday 02 May 2013, Eduardo Valentin wrote:
>> index e3c0ae9..e3f3cba 100644
>> --- a/include/linux/thermal.h
>> +++ b/include/linux/thermal.h
>> @@ -250,12 +250,6 @@ void thermal_unregister_governor(struct
>> thermal_governor *);
>>  #ifdef CONFIG_NET
>>  extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>>                                                 enum events event);
>> -#else
>> -static int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>> -                                               enum events event)
>> -{
>> -       return 0;
>> -}
>>  #endif
> 
> Actually it seems this bug is already fixed in linux-next:
> 
> commit f8b587055a793c7719f0d4f41b7b4aeeef43aa2d
> Author: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Date:   Wed Mar 20 21:38:07 2013 +0000
> 
>     thermal: Fix compiler warning
>     
>     The following warning is obtained when CONFIG_NET is not defined:
>     
>     In file included from drivers/thermal/mvebu_thermal.c:27:0:
>     include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event'
>     defined but not used [-Wunused-function]
>     
>     This patch fixes the warning by properly inlining
>     thermal_generate_netlink_event().
>     
>     Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
>     Signed-off-by: Zhang Rui <rui.zhang at intel.com>
> 
> diff --git a/include/linux/thermal.h b/include/linux/thermal.h
> index f0bd7f9..fd7b8f3 100644
> --- a/include/linux/thermal.h
> +++ b/include/linux/thermal.h
> @@ -251,7 +251,7 @@ void thermal_unregister_governor(struct thermal_governor *);
>  extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>                                                 enum events event);
>  #else
> -static int thermal_generate_netlink_event(struct thermal_zone_device *tz,
> +static inline int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>                                                 enum events event)
>  {
>         return 0;
> 
> 
> Your patch also seems correct, but it would conflict with Ezequiel's.
> The problem was apparently that you removed the 'inline' keyword
> in 8ab3e6a08a "thermal: Use thermal zone device id in netlink messages",
> I assume by accident, since defining a non-inline function in a header
> file is obviously wrong.

Yeah, that was my bad. I am fine with Ezequiel s patch.

Thanks.

> 
> 	Arnd
> 
> 


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From linux at prisktech.co.nz  Thu May  2 14:46:02 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri,  3 May 2013 06:46:02 +1200
Subject: [PATCHv5 0/3] Add support for velocity network driver on platform
 devices
Message-ID: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>

v5 changes:
Remove velocity_info union. Change velocity_info->pdev back to struct pci_dev.
Remove more 'if (pci)' sections.
Remove 'void *pdev' function parameters.
Pass correct variable to velocity_choose_state()

v4 changes:
Code tidyup as requested by Francois Romieu
Removed '#ifdef PCI' around PCI code. Compile tested on (!)PCI and (!)PM.

v3 changes:
Rebased against net-next.
Fix errors in pm code.

v2 changes:
Drop patch #1 as requested by David Miller.
Correct the PHYID_ICPLUS_IP101A MII bits - should be ON, rather than OFF.
Read the platform rev_id from the correct register [regs->rev_id]. It's possible
this would work for the PCI version as well and would remove the need for the
'if (pci)' test to set vptr->rev_id.

v1:
The first three patches are general tidyup.

[DROPPED] Patch ## just alphabetizes the #includes to make it easier to read.

Patch #1 replaces vptr->dev with vptr->netdev, in preparation of adding a
struct device *dev in Patch #3

Patch #2 replaces the pci dma functions with the generic versions.

I have build tested these patches but don't have a PCI velocity to run-test it.
I can't see that they should introduce any problems as it is all renames and
function swapping.

Patch #3 adds support for the velocity driver on devicetree platform devices.
Binding document included. This patch is compile-tested for PCI, and boot
tested on a VIA APC8750.

I think it would be pertinent to get some tested-by's for PCI users.

Regards
Tony Prisk

Tony Prisk (3):
  net: velocity: Rename vptr->dev to vptr->netdev
  net: velocity: Convert to generic dma functions
  net: velocity: Add platform device support to VIA velocity driver

 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  543 +++++++++++++-------
 drivers/net/ethernet/via/via-velocity.h            |   35 +-
 4 files changed, 419 insertions(+), 182 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

-- 
1.7.9.5



From linux at arm.linux.org.uk  Thu May  2 14:45:14 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:45:14 +0100
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182B18C.4080404@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <5182B18C.4080404@gmail.com>
Message-ID: <20130502184514.GE14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 08:33:48PM +0200, Sebastian Hesselbarth wrote:
> On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
>> This patch adds an irqchip driver for the main interrupt controller found
>> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
>> Corresponding device tree documentation is also added.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>> ---
>> Note: This patch triggers a checkpatch warning for
>>    WARNING: Avoid CamelCase:<handle_IRQ>
>>
> [...]
>> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
>> new file mode 100644
>> index 0000000..04f7bab
>> --- /dev/null
>> +++ b/include/linux/irqchip/orion.h
>> @@ -0,0 +1,18 @@
>> +/*
>> + * Marvell Orion SoCs IRQ chip driver header.
>> + *
>> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#ifndef __LINUX_IRQCHIP_ORION_H
>> +#define __LINUX_IRQCHIP_ORION_H
>> +
>> +#include<asm/exception.h>
>
> First review by myself. The above include is a left-over and
> will be removed in a v2.

You still need your first level IRQ handlers marked with __exception_irq_entry
which is defined in the above file.


From linux at prisktech.co.nz  Thu May  2 14:46:04 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri,  3 May 2013 06:46:04 +1200
Subject: [PATCHv5 2/3] net: velocity: Convert to generic dma functions
In-Reply-To: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
References: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1367520365-18842-3-git-send-email-linux@prisktech.co.nz>

Remove the pci_* dma functions and replace with the more generic
versions.

In preparation of adding platform support, a new struct device *dev
is added to struct velocity_info which can be used by both the pci
and platform code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   51 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    1 +
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 187eef3..5996cee 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -46,6 +46,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 #include <linux/init.h>
+#include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
@@ -1459,7 +1460,6 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	struct velocity_opt *opt = &vptr->options;
 	const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
 	const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
-	struct pci_dev *pdev = vptr->pdev;
 	dma_addr_t pool_dma;
 	void *pool;
 	unsigned int i;
@@ -1467,13 +1467,13 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	/*
 	 * Allocate all RD/TD rings a single pool.
 	 *
-	 * pci_alloc_consistent() fulfills the requirement for 64 bytes
+	 * dma_alloc_coherent() fulfills the requirement for 64 bytes
 	 * alignment
 	 */
-	pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
-				    rx_ring_size, &pool_dma);
+	pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
+				    rx_ring_size, &pool_dma, GFP_ATOMIC);
 	if (!pool) {
-		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
+		dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
 			vptr->netdev->name);
 		return -ENOMEM;
 	}
@@ -1524,8 +1524,8 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	 */
 	skb_reserve(rd_info->skb,
 			64 - ((unsigned long) rd_info->skb->data & 63));
-	rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
-					vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
+					vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Fill in the descriptor to match
@@ -1588,8 +1588,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr)
 
 		if (!rd_info->skb)
 			continue;
-		pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-				 PCI_DMA_FROMDEVICE);
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
 		rd_info->skb_dma = 0;
 
 		dev_kfree_skb(rd_info->skb);
@@ -1670,7 +1670,7 @@ static void velocity_free_dma_rings(struct velocity_info *vptr)
 	const int size = vptr->options.numrx * sizeof(struct rx_desc) +
 		vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
 
-	pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
+	dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
 }
 
 static int velocity_init_rings(struct velocity_info *vptr, int mtu)
@@ -1727,8 +1727,8 @@ static void velocity_free_tx_buf(struct velocity_info *vptr,
 				pktlen = max_t(size_t, pktlen,
 						td->td_buf[i].size & ~TD_QUEUE);
 
-			pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
-					le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
+			dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
+					le16_to_cpu(pktlen), DMA_TO_DEVICE);
 		}
 	}
 	dev_kfree_skb_irq(skb);
@@ -1750,8 +1750,8 @@ static void velocity_free_td_ring_entry(struct velocity_info *vptr,
 	if (td_info->skb) {
 		for (i = 0; i < td_info->nskb_dma; i++) {
 			if (td_info->skb_dma[i]) {
-				pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
-					td_info->skb->len, PCI_DMA_TODEVICE);
+				dma_unmap_single(vptr->dev, td_info->skb_dma[i],
+					td_info->skb->len, DMA_TO_DEVICE);
 				td_info->skb_dma[i] = 0;
 			}
 		}
@@ -2029,7 +2029,6 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
  */
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
-	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
 	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
@@ -2047,8 +2046,8 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 
 	skb = rd_info->skb;
 
-	pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
-				    vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
+				    vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Drop frame not meeting IEEE 802.3
@@ -2061,19 +2060,18 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		}
 	}
 
-	pci_action = pci_dma_sync_single_for_device;
-
 	velocity_rx_csum(rd, skb);
 
 	if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
 		velocity_iph_realign(vptr, skb, pkt_len);
-		pci_action = pci_unmap_single;
 		rd_info->skb = NULL;
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
+	} else {
+		dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
+					   vptr->rx.buf_sz, DMA_FROM_DEVICE);
 	}
 
-	pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-		   PCI_DMA_FROMDEVICE);
-
 	skb_put(skb, pkt_len - 4);
 	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
@@ -2550,7 +2548,8 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	 *	add it to the transmit ring.
 	 */
 	tdinfo->skb = skb;
-	tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+	tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
+								DMA_TO_DEVICE);
 	td_ptr->tdesc0.len = cpu_to_le16(pktlen);
 	td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
 	td_ptr->td_buf[0].pa_high = 0;
@@ -2560,7 +2559,7 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
-		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(&vptr->pdev->dev,
+		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
 							  frag, 0,
 							  skb_frag_size(frag),
 							  DMA_TO_DEVICE);
@@ -2637,6 +2636,7 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
 {
 	memset(vptr, 0, sizeof(struct velocity_info));
 
+	vptr->dev = &pdev->dev;
 	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
@@ -2744,7 +2744,6 @@ static int velocity_found1(struct pci_dev *pdev,
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	vptr = netdev_priv(dev);
 
-
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
 			VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index ff8d7828..c38bbae 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1434,6 +1434,7 @@ struct velocity_opt {
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
 struct velocity_info {
+	struct device *dev;
 	struct pci_dev *pdev;
 	struct net_device *netdev;
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu May  2 14:46:03 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri,  3 May 2013 06:46:03 +1200
Subject: [PATCHv5 1/3] net: velocity: Rename vptr->dev to vptr->netdev
In-Reply-To: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
References: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1367520365-18842-2-git-send-email-linux@prisktech.co.nz>

Improve the clarity of the code in preparation for converting the
dma functions to generic versions, which require a struct device *.

This makes it possible to store a 'struct device *dev' in the
velocity_info structure.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   66 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    4 +-
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index fb62489..187eef3 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -998,9 +998,9 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 {
 
 	if (vptr->mii_status & VELOCITY_LINK_FAIL) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
 	} else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
 
 		if (vptr->mii_status & VELOCITY_SPEED_1000)
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
@@ -1014,7 +1014,7 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 		else
 			VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
 	} else {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
 		switch (vptr->options.spd_dpx) {
 		case SPD_DPX_1000_FULL:
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
@@ -1319,7 +1319,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 	case VELOCITY_INIT_RESET:
 	case VELOCITY_INIT_WOL:
 
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/*
 		 *	Reset RX to prevent RX pointer not on the 4X location
@@ -1332,7 +1332,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1354,7 +1354,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 
 		mac_eeprom_reload(regs);
 		for (i = 0; i < 6; i++)
-			writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -1377,7 +1377,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		/*
 		 *	Set packet filter: Receive directed and broadcast address
 		 */
-		velocity_set_multi(vptr->dev);
+		velocity_set_multi(vptr->netdev);
 
 		/*
 		 *	Enable MII auto-polling
@@ -1404,14 +1404,14 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
 
 		mii_status = velocity_get_opt_media_mode(vptr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		mii_init(vptr, mii_status);
 
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1474,7 +1474,7 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 				    rx_ring_size, &pool_dma);
 	if (!pool) {
 		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
-			vptr->dev->name);
+			vptr->netdev->name);
 		return -ENOMEM;
 	}
 
@@ -1514,7 +1514,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 
-	rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx.buf_sz + 64);
+	rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
 	if (rd_info->skb == NULL)
 		return -ENOMEM;
 
@@ -1620,7 +1620,7 @@ static int velocity_init_rd_ring(struct velocity_info *vptr)
 
 	if (velocity_rx_refill(vptr) != vptr->options.numrx) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
-			"%s: failed to allocate RX buffer.\n", vptr->dev->name);
+			"%s: failed to allocate RX buffer.\n", vptr->netdev->name);
 		velocity_free_rd_ring(vptr);
 		goto out;
 	}
@@ -1809,7 +1809,7 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
 		BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
 		writew(TRDCSR_RUN, &regs->TDCSRClr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/* FIXME: port over the pci_device_failed code and use it
 		   here */
@@ -1850,10 +1850,10 @@ static void velocity_error(struct velocity_info *vptr, int status)
 
 		if (linked) {
 			vptr->mii_status &= ~VELOCITY_LINK_FAIL;
-			netif_carrier_on(vptr->dev);
+			netif_carrier_on(vptr->netdev);
 		} else {
 			vptr->mii_status |= VELOCITY_LINK_FAIL;
-			netif_carrier_off(vptr->dev);
+			netif_carrier_off(vptr->netdev);
 		}
 
 		velocity_print_link_status(vptr);
@@ -1867,9 +1867,9 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		enable_mii_autopoll(regs);
 
 		if (vptr->mii_status & VELOCITY_LINK_FAIL)
-			netif_stop_queue(vptr->dev);
+			netif_stop_queue(vptr->netdev);
 		else
-			netif_wake_queue(vptr->dev);
+			netif_wake_queue(vptr->netdev);
 
 	}
 	if (status & ISR_MIBFI)
@@ -1894,7 +1894,7 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	int idx;
 	int works = 0;
 	struct velocity_td_info *tdinfo;
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 
 	for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
 		for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
@@ -1939,9 +1939,9 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	 *	Look to see if we should kick the transmit network
 	 *	layer for more work.
 	 */
-	if (netif_queue_stopped(vptr->dev) && (full == 0) &&
+	if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
 	    (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
-		netif_wake_queue(vptr->dev);
+		netif_wake_queue(vptr->netdev);
 	}
 	return works;
 }
@@ -1989,7 +1989,7 @@ static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
 	if (pkt_size < rx_copybreak) {
 		struct sk_buff *new_skb;
 
-		new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
+		new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
 		if (new_skb) {
 			new_skb->ip_summed = rx_skb[0]->ip_summed;
 			skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
@@ -2030,14 +2030,14 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
 	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
 	struct sk_buff *skb;
 
 	if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
-		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->netdev->name);
 		stats->rx_length_errors++;
 		return -EINVAL;
 	}
@@ -2075,7 +2075,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		   PCI_DMA_FROMDEVICE);
 
 	skb_put(skb, pkt_len - 4);
-	skb->protocol = eth_type_trans(skb, vptr->dev);
+	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
 	if (rd->rdesc0.RSR & RSR_DETAG) {
 		u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
@@ -2100,7 +2100,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
  */
 static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
 {
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	int rd_curr = vptr->rx.curr;
 	int works = 0;
 
@@ -2292,7 +2292,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 	if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
-				vptr->dev->name);
+				vptr->netdev->name);
 		ret = -EINVAL;
 		goto out_0;
 	}
@@ -2314,7 +2314,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 			goto out_0;
 		}
 
-		tmp_vptr->dev = dev;
+		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
@@ -2692,7 +2692,7 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
  */
 static void velocity_print_info(struct velocity_info *vptr)
 {
-	struct net_device *dev = vptr->dev;
+	struct net_device *dev = vptr->netdev;
 
 	printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
 	printk(KERN_INFO "%s: Ethernet Address: %pM\n",
@@ -2755,7 +2755,7 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	velocity_init_info(pdev, vptr, info);
 
-	vptr->dev = dev;
+	vptr->netdev = dev;
 
 	ret = pci_enable_device(pdev);
 	if (ret < 0)
@@ -3010,10 +3010,10 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	struct velocity_info *vptr = netdev_priv(dev);
 	unsigned long flags;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
-	netif_device_detach(vptr->dev);
+	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
 	pci_save_state(pdev);
@@ -3078,7 +3078,7 @@ static int velocity_resume(struct pci_dev *pdev)
 	unsigned long flags;
 	int i;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
 	pci_set_power_state(pdev, PCI_D0);
@@ -3101,7 +3101,7 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	mac_enable_int(vptr->mac_regs);
 	spin_unlock_irqrestore(&vptr->lock, flags);
-	netif_device_attach(vptr->dev);
+	netif_device_attach(vptr->netdev);
 
 	return 0;
 }
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index 4cb9f13..ff8d7828 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1435,7 +1435,7 @@ struct velocity_opt {
 
 struct velocity_info {
 	struct pci_dev *pdev;
-	struct net_device *dev;
+	struct net_device *netdev;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
@@ -1514,7 +1514,7 @@ static inline int velocity_get_ip(struct velocity_info *vptr)
 	int res = -ENOENT;
 
 	rcu_read_lock();
-	in_dev = __in_dev_get_rcu(vptr->dev);
+	in_dev = __in_dev_get_rcu(vptr->netdev);
 	if (in_dev != NULL) {
 		ifa = (struct in_ifaddr *) in_dev->ifa_list;
 		if (ifa != NULL) {
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu May  2 14:46:05 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri,  3 May 2013 06:46:05 +1200
Subject: [PATCHv5 3/3] net: velocity: Add platform device support to VIA
 velocity driver
In-Reply-To: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
References: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1367520365-18842-4-git-send-email-linux@prisktech.co.nz>

Add support for the VIA Velocity network driver to be bound to a
OF created platform device.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  432 ++++++++++++++------
 drivers/net/ethernet/via/via-velocity.h            |   32 +-
 4 files changed, 362 insertions(+), 125 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

diff --git a/Documentation/devicetree/bindings/net/via-velocity.txt b/Documentation/devicetree/bindings/net/via-velocity.txt
new file mode 100644
index 0000000..b3db469
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/via-velocity.txt
@@ -0,0 +1,20 @@
+* VIA Velocity 10/100/1000 Network Controller
+
+Required properties:
+- compatible : Should be "via,velocity-vt6110"
+- reg : Address and length of the io space
+- interrupts : Should contain the controller interrupt line
+
+Optional properties:
+- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
+	devices quite often set this data in uboot and do not provide an eeprom.
+	Specify this option if you have no external eeprom.
+
+Examples:
+
+eth0 at d8004000 {
+	compatible = "via,velocity-vt6110";
+	reg = <0xd8004000 0x400>;
+	interrupts = <10>;
+	no-eeprom;
+};
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
index 68a9ba6..6a87097 100644
--- a/drivers/net/ethernet/via/Kconfig
+++ b/drivers/net/ethernet/via/Kconfig
@@ -5,7 +5,6 @@
 config NET_VENDOR_VIA
 	bool "VIA devices"
 	default y
-	depends on PCI
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y
 	  and read the Ethernet-HOWTO, available from
@@ -45,7 +44,7 @@ config VIA_RHINE_MMIO
 
 config VIA_VELOCITY
 	tristate "VIA Velocity support"
-	depends on PCI
+	depends on (PCI || USE_OF)
 	select CRC32
 	select CRC_CCITT
 	select NET_CORE
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 5996cee..cd4bf87 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -65,7 +65,11 @@
 #include <linux/if.h>
 #include <linux/uaccess.h>
 #include <linux/proc_fs.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
 #include <linux/inetdevice.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/ethtool.h>
 #include <linux/mii.h>
@@ -84,6 +88,16 @@
 static int velocity_nics;
 static int msglevel = MSG_LEVEL_INFO;
 
+static void velocity_set_power_state(struct velocity_info *vptr, char state)
+{
+	void *addr = vptr->mac_regs;
+
+	if (vptr->bustype == BUS_PCI)
+		pci_set_power_state(vptr->pdev, state);
+	else
+		writeb(state, addr + 0x154);
+}
+
 /**
  *	mac_get_cam_mask	-	Read a CAM mask
  *	@regs: register block for this velocity
@@ -362,12 +376,23 @@ static struct velocity_info_tbl chip_info_table[] = {
  *	Describe the PCI device identifiers that we support in this
  *	device driver. Used for hotplug autoloading.
  */
-static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
+
+static DEFINE_PCI_DEVICE_TABLE(velocity_pci_id_table) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
 	{ }
 };
 
-MODULE_DEVICE_TABLE(pci, velocity_id_table);
+MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
+
+/**
+ *	Describe the OF device identifiers that we support in this
+ *	device driver. Used for devicetree nodes.
+ */
+static struct of_device_id velocity_of_ids[] = {
+	{ .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, velocity_of_ids);
 
 /**
  *	get_chip_name	- 	identifier to name
@@ -386,29 +411,6 @@ static const char *get_chip_name(enum chip_type chip_id)
 }
 
 /**
- *	velocity_remove1	-	device unplug
- *	@pdev: PCI device being removed
- *
- *	Device unload callback. Called on an unplug or on module
- *	unload for each active device that is present. Disconnects
- *	the device from the network layer and frees all the resources
- */
-static void velocity_remove1(struct pci_dev *pdev)
-{
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
-
-	unregister_netdev(dev);
-	iounmap(vptr->mac_regs);
-	pci_release_regions(pdev);
-	pci_disable_device(pdev);
-	pci_set_drvdata(pdev, NULL);
-	free_netdev(dev);
-
-	velocity_nics--;
-}
-
-/**
  *	velocity_set_int_opt	-	parser for integer options
  *	@opt: pointer to option value
  *	@val: value the user requested (or -1 for default)
@@ -1181,6 +1183,17 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
 	u16 BMCR;
 
 	switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
+	case PHYID_ICPLUS_IP101A:
+		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
+						MII_ADVERTISE, vptr->mac_regs);
+		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		else
+			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
+		break;
 	case PHYID_CICADA_CS8201:
 		/*
 		 *	Reset to hardware default
@@ -1353,9 +1366,12 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		velocity_soft_reset(vptr);
 		mdelay(5);
 
-		mac_eeprom_reload(regs);
-		for (i = 0; i < 6; i++)
-			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
+		if (!vptr->no_eeprom) {
+			mac_eeprom_reload(regs);
+			for (i = 0; i < 6; i++)
+				writeb(vptr->netdev->dev_addr[i],
+							&(regs->PAR[i]));
+		}
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -2233,15 +2249,15 @@ static int velocity_open(struct net_device *dev)
 		goto out;
 
 	/* Ensure chip is running */
-	pci_set_power_state(vptr->pdev, PCI_D0);
+	velocity_set_power_state(vptr, PCI_D0);
 
 	velocity_init_registers(vptr, VELOCITY_INIT_COLD);
 
-	ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
+	ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
 			  dev->name, dev);
 	if (ret < 0) {
 		/* Power down the chip */
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 		velocity_free_rings(vptr);
 		goto out;
 	}
@@ -2413,7 +2429,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	   saving then we need to bring the device back up to talk to it */
 
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 
 	switch (cmd) {
 	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
@@ -2426,7 +2442,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 		ret = -EOPNOTSUPP;
 	}
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 
 
 	return ret;
@@ -2492,7 +2508,7 @@ static int velocity_close(struct net_device *dev)
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
 		velocity_get_ip(vptr);
 
-	free_irq(vptr->pdev->irq, dev);
+	free_irq(dev->irq, dev);
 
 	velocity_free_rings(vptr);
 
@@ -2631,13 +2647,9 @@ static const struct net_device_ops velocity_netdev_ops = {
  *	Set up the initial velocity_info struct for the device that has been
  *	discovered.
  */
-static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
-			       const struct velocity_info_tbl *info)
+static void velocity_init_info(struct velocity_info *vptr,
+				const struct velocity_info_tbl *info)
 {
-	memset(vptr, 0, sizeof(struct velocity_info));
-
-	vptr->dev = &pdev->dev;
-	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
 	vptr->multicast_limit = MCAM_SIZE;
@@ -2652,33 +2664,61 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
  *	Retrieve the PCI configuration space data that interests us from
  *	the kernel PCI layer
  */
-static int velocity_get_pci_info(struct velocity_info *vptr,
-				 struct pci_dev *pdev)
+static int velocity_get_pci_info(struct velocity_info *vptr)
 {
-	vptr->rev_id = pdev->revision;
+	pci_set_master(vptr->pdev);
 
-	pci_set_master(pdev);
+	vptr->ioaddr = pci_resource_start(vptr->pdev, 0);
+	vptr->memaddr = pci_resource_start(vptr->pdev, 1);
 
-	vptr->ioaddr = pci_resource_start(pdev, 0);
-	vptr->memaddr = pci_resource_start(pdev, 1);
-
-	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
-		dev_err(&pdev->dev,
+	if (!(pci_resource_flags(vptr->pdev, 0) & IORESOURCE_IO)) {
+		dev_err(vptr->dev,
 			   "region #0 is not an I/O resource, aborting.\n");
 		return -EINVAL;
 	}
 
-	if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
-		dev_err(&pdev->dev,
+	if ((pci_resource_flags(vptr->pdev, 1) & IORESOURCE_IO)) {
+		dev_err(vptr->dev,
 			   "region #1 is an I/O resource, aborting.\n");
 		return -EINVAL;
 	}
 
-	if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
-		dev_err(&pdev->dev, "region #1 is too small.\n");
+	if (pci_resource_len(vptr->pdev, 1) < VELOCITY_IO_SIZE) {
+		dev_err(vptr->dev, "region #1 is too small.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ *	velocity_get_platform_info - retrieve platform info for device
+ *	@vptr: velocity device
+ *	@pdev: platform device it matches
+ *
+ *	Retrieve the Platform configuration data that interests us
+ */
+static int velocity_get_platform_info(struct platform_device *pdev,
+					struct velocity_info *vptr)
+{
+	struct resource res;
+	int ret;
+
+	if (of_get_property(pdev->dev.of_node, "no-eeprom", NULL))
+		vptr->no_eeprom = 1;
+
+	ret = of_address_to_resource(pdev->dev.of_node, 0, &res);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to find memory address\n");
+		return ret;
+	}
+
+	vptr->memaddr = res.start;
+
+	if (resource_size(&res) < VELOCITY_IO_SIZE) {
+		dev_err(&pdev->dev, "memory region is too small.\n");
 		return -EINVAL;
 	}
-	vptr->pdev = pdev;
 
 	return 0;
 }
@@ -2707,42 +2747,59 @@ static u32 velocity_get_link(struct net_device *dev)
 }
 
 /**
- *	velocity_found1		-	set up discovered velocity card
+ *	velocity_probe - set up discovered velocity device
  *	@pdev: PCI device
  *	@ent: PCI device table entry that matched
+ *	@bustype: bus that device is connected to
  *
  *	Configure a discovered adapter from scratch. Return a negative
  *	errno error code on failure paths.
  */
-static int velocity_found1(struct pci_dev *pdev,
-			   const struct pci_device_id *ent)
+static int velocity_probe(void *pdev,
+			   const struct pci_device_id *ent,
+			   enum velocity_bus_type bustype)
 {
 	static int first = 1;
-	struct net_device *dev;
+	struct pci_dev *pci_dev = NULL;
+	struct platform_device *platform_dev = NULL;
+	struct net_device *netdev;
+	struct device *dev;
+	const struct of_device_id *of_id;
 	int i;
 	const char *drv_string;
-	const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
+	const struct velocity_info_tbl *info;
 	struct velocity_info *vptr;
 	struct mac_regs __iomem *regs;
 	int ret = -ENOMEM;
 
+	if (bustype == BUS_PCI) {
+		pci_dev = pdev;
+		dev = &pci_dev->dev;
+		info = &chip_info_table[ent->driver_data];
+	} else {
+		platform_dev = pdev;
+		dev = &platform_dev->dev;
+		of_id = of_match_device(velocity_of_ids, dev);
+		info = of_id->data;
+	}
+
 	/* FIXME: this driver, like almost all other ethernet drivers,
 	 * can support more than MAX_UNITS.
 	 */
 	if (velocity_nics >= MAX_UNITS) {
-		dev_notice(&pdev->dev, "already found %d NICs.\n",
-			   velocity_nics);
+		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
 		return -ENODEV;
 	}
 
-	dev = alloc_etherdev(sizeof(struct velocity_info));
-	if (!dev)
+	netdev = alloc_etherdev(sizeof(struct velocity_info));
+	if (!netdev)
 		goto out;
 
 	/* Chain it all together */
 
-	SET_NETDEV_DEV(dev, &pdev->dev);
-	vptr = netdev_priv(dev);
+	SET_NETDEV_DEV(netdev, dev);
+	vptr = netdev_priv(netdev);
+	memset(vptr, 0, sizeof(struct velocity_info));
 
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
@@ -2752,24 +2809,40 @@ static int velocity_found1(struct pci_dev *pdev,
 		first = 0;
 	}
 
-	velocity_init_info(pdev, vptr, info);
+	vptr->bustype = bustype;
+	vptr->netdev = netdev;
+	vptr->dev = dev;
 
-	vptr->netdev = dev;
+	velocity_init_info(vptr, info);
 
-	ret = pci_enable_device(pdev);
-	if (ret < 0)
-		goto err_free_dev;
+	if (vptr->bustype == BUS_PCI) {
+		vptr->pdev = pci_dev;
+		ret = pci_enable_device(pci_dev);
+		if (ret < 0)
+			goto err_free_dev;
 
-	ret = velocity_get_pci_info(vptr, pdev);
-	if (ret < 0) {
-		/* error message already printed */
-		goto err_disable;
-	}
+		netdev->irq = pci_dev->irq;
 
-	ret = pci_request_regions(pdev, VELOCITY_NAME);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "No PCI resources.\n");
-		goto err_disable;
+		ret = velocity_get_pci_info(vptr);
+		if (ret < 0)
+			goto err_disable;
+
+		ret = pci_request_regions(pci_dev, VELOCITY_NAME);
+		if (ret < 0) {
+			dev_err(dev, "No PCI resources.\n");
+			goto err_disable;
+		}
+	} else {
+		netdev->irq =
+			irq_of_parse_and_map(platform_dev->dev.of_node, 0);
+		if (!netdev->irq) {
+			ret = -EINVAL;
+			goto err_free_dev;
+		}
+
+		ret = velocity_get_platform_info(platform_dev, vptr);
+		if (ret < 0)
+			goto err_disable;
 	}
 
 	regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
@@ -2780,13 +2853,18 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	vptr->mac_regs = regs;
 
+	if (vptr->bustype == BUS_PCI)
+		vptr->rev_id = pci_dev->revision;
+	else
+		vptr->rev_id = readb(&regs->rev_id);
+
 	mac_wol_reset(regs);
 
 	for (i = 0; i < 6; i++)
-		dev->dev_addr[i] = readb(&regs->PAR[i]);
+		netdev->dev_addr[i] = readb(&regs->PAR[i]);
 
 
-	drv_string = dev_driver_string(&pdev->dev);
+	drv_string = dev_driver_string(dev);
 
 	velocity_get_options(&vptr->options, velocity_nics, drv_string);
 
@@ -2807,30 +2885,32 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
 
-	dev->netdev_ops = &velocity_netdev_ops;
-	dev->ethtool_ops = &velocity_ethtool_ops;
-	netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
+	netdev->netdev_ops = &velocity_netdev_ops;
+	netdev->ethtool_ops = &velocity_ethtool_ops;
+	netif_napi_add(netdev, &vptr->napi, velocity_poll,
+							VELOCITY_NAPI_WEIGHT);
 
-	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
+	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
 			   NETIF_F_HW_VLAN_CTAG_TX;
-	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_FILTER |
-			 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_IP_CSUM;
+	netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
+			NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
+			NETIF_F_IP_CSUM;
 
-	ret = register_netdev(dev);
+	ret = register_netdev(netdev);
 	if (ret < 0)
 		goto err_iounmap;
 
-	if (!velocity_get_link(dev)) {
-		netif_carrier_off(dev);
+	if (!velocity_get_link(netdev)) {
+		netif_carrier_off(netdev);
 		vptr->mii_status |= VELOCITY_LINK_FAIL;
 	}
 
 	velocity_print_info(vptr);
-	pci_set_drvdata(pdev, dev);
+	dev_set_drvdata(vptr->dev, netdev);
 
 	/* and leave the chip powered down */
 
-	pci_set_power_state(pdev, PCI_D3hot);
+	velocity_set_power_state(vptr, PCI_D3hot);
 	velocity_nics++;
 out:
 	return ret;
@@ -2838,14 +2918,68 @@ out:
 err_iounmap:
 	iounmap(regs);
 err_release_res:
-	pci_release_regions(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_release_regions(vptr->pdev);
 err_disable:
-	pci_disable_device(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_disable_device(vptr->pdev);
 err_free_dev:
-	free_netdev(dev);
+	free_netdev(netdev);
 	goto out;
 }
 
+/**
+ *	velocity_remove	- device unplug
+ *	@pdev: PCI device being removed
+ *
+ *	Device unload callback. Called on an unplug or on module
+ *	unload for each active device that is present. Disconnects
+ *	the device from the network layer and frees all the resources
+ */
+static int velocity_remove(struct net_device *netdev)
+{
+	struct velocity_info *vptr = netdev_priv(netdev);
+
+	unregister_netdev(netdev);
+	iounmap(vptr->mac_regs);
+	free_netdev(netdev);
+	velocity_nics--;
+
+	return 0;
+}
+
+static int velocity_pci_probe(struct pci_dev *pdev,
+			   const struct pci_device_id *ent)
+{
+	return velocity_probe(pdev, ent, BUS_PCI);
+}
+
+static void velocity_pci_remove(struct pci_dev *pdev)
+{
+	struct net_device *netdev = pci_get_drvdata(pdev);
+
+	velocity_remove(netdev);
+
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+	pci_set_drvdata(pdev, NULL);
+}
+
+static int velocity_platform_probe(struct platform_device *pdev)
+{
+	return velocity_probe(pdev, NULL, BUS_PLATFORM);
+}
+
+static int velocity_platform_remove(struct platform_device *pdev)
+{
+	struct net_device *netdev = platform_get_drvdata(pdev);
+
+	velocity_remove(netdev);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
 #ifdef CONFIG_PM
 /**
  *	wol_calc_crc		-	WOL CRC
@@ -3003,10 +3137,9 @@ static void velocity_save_context(struct velocity_info *vptr, struct velocity_co
 
 }
 
-static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
+static int velocity_suspend(struct net_device *netdev, pm_message_t state)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 
 	if (!netif_running(vptr->netdev))
@@ -3015,20 +3148,24 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
-	pci_save_state(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_save_state(vptr->pdev);
 
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
 		velocity_get_ip(vptr);
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
 		velocity_set_wol(vptr);
-		pci_enable_wake(pdev, PCI_D3hot, 1);
-		pci_set_power_state(pdev, PCI_D3hot);
+		if (vptr->bustype == BUS_PCI)
+			pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	} else {
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
-		pci_disable_device(pdev);
-		pci_set_power_state(pdev, pci_choose_state(pdev, state));
+		if (vptr->bustype == BUS_PCI)
+			pci_disable_device(vptr->pdev);
+		velocity_set_power_state(vptr,
+				velocity_choose_state(vptr->dev, state));
 	}
 
 	spin_unlock_irqrestore(&vptr->lock, flags);
@@ -3070,19 +3207,21 @@ static void velocity_restore_context(struct velocity_info *vptr, struct velocity
 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
 }
 
-static int velocity_resume(struct pci_dev *pdev)
+static int velocity_resume(struct net_device *netdev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 	int i;
 
 	if (!netif_running(vptr->netdev))
 		return 0;
 
-	pci_set_power_state(pdev, PCI_D0);
-	pci_enable_wake(pdev, 0, 0);
-	pci_restore_state(pdev);
+	velocity_set_power_state(vptr, PCI_D0);
+
+	if (vptr->bustype == BUS_PCI) {
+		pci_enable_wake(vptr->pdev, 0, 0);
+		pci_restore_state(vptr->pdev);
+	}
 
 	mac_wol_reset(vptr->mac_regs);
 
@@ -3104,23 +3243,62 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	return 0;
 }
-#endif
+
+static int velocity_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	struct net_device *netdev = pci_get_drvdata(pdev);
+	return velocity_suspend(netdev, state);
+}
+
+static int velocity_pci_resume(struct pci_dev *pdev)
+{
+	struct net_device *netdev = pci_get_drvdata(pdev);
+	return velocity_resume(netdev);
+}
+
+static int velocity_platform_suspend(struct platform_device *pdev,
+				      pm_message_t state)
+{
+	struct net_device *netdev = platform_get_drvdata(pdev);
+	return velocity_suspend(netdev, state);
+}
+
+static int velocity_platform_resume(struct platform_device *pdev)
+{
+	struct net_device *netdev = platform_get_drvdata(pdev);
+	return velocity_resume(netdev);
+}
+
+#endif	/* !CONFIG_PM */
 
 /*
  *	Definition for our device driver. The PCI layer interface
  *	uses this to handle all our card discover and plugging
  */
-static struct pci_driver velocity_driver = {
+static struct pci_driver velocity_pci_driver = {
 	.name		= VELOCITY_NAME,
-	.id_table	= velocity_id_table,
-	.probe		= velocity_found1,
-	.remove		= velocity_remove1,
+	.id_table	= velocity_pci_id_table,
+	.probe		= velocity_pci_probe,
+	.remove		= velocity_pci_remove,
 #ifdef CONFIG_PM
-	.suspend	= velocity_suspend,
-	.resume		= velocity_resume,
+	.suspend	= velocity_pci_suspend,
+	.resume		= velocity_pci_resume,
 #endif
 };
 
+static struct platform_driver velocity_platform_driver = {
+	.probe		= velocity_platform_probe,
+	.remove		= velocity_platform_remove,
+#ifdef CONFIG_PM
+	.suspend	= velocity_platform_suspend,
+	.resume		= velocity_platform_resume,
+#endif
+	.driver = {
+		.name = "via-velocity",
+		.owner = THIS_MODULE,
+		.of_match_table = velocity_of_ids,
+	},
+};
 
 /**
  *	velocity_ethtool_up	-	pre hook for ethtool
@@ -3133,7 +3311,7 @@ static int velocity_ethtool_up(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 	return 0;
 }
 
@@ -3148,7 +3326,7 @@ static void velocity_ethtool_down(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 }
 
 static int velocity_get_settings(struct net_device *dev,
@@ -3270,7 +3448,11 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
 	struct velocity_info *vptr = netdev_priv(dev);
 	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
 	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
-	strlcpy(info->bus_info, pci_name(vptr->pdev), sizeof(info->bus_info));
+	if (vptr->bustype == BUS_PCI)
+		strlcpy(info->bus_info, pci_name(vptr->pdev),
+						sizeof(info->bus_info));
+	else
+		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
 }
 
 static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -3563,9 +3745,15 @@ static int __init velocity_init_module(void)
 	int ret;
 
 	velocity_register_notifier();
-	ret = pci_register_driver(&velocity_driver);
+
+	ret = pci_register_driver(&velocity_pci_driver);
+	if (ret < 0)
+		velocity_unregister_notifier();
+
+	ret = platform_driver_register(&velocity_platform_driver);
 	if (ret < 0)
 		velocity_unregister_notifier();
+
 	return ret;
 }
 
@@ -3580,7 +3768,9 @@ static int __init velocity_init_module(void)
 static void __exit velocity_cleanup_module(void)
 {
 	velocity_unregister_notifier();
-	pci_unregister_driver(&velocity_driver);
+
+	pci_unregister_driver(&velocity_pci_driver);
+	platform_driver_unregister(&velocity_platform_driver);
 }
 
 module_init(velocity_init_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index c38bbae..6be7e46 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1265,7 +1265,7 @@ struct velocity_context {
 #define PHYID_VT3216_64BIT  0x000FC600UL
 #define PHYID_MARVELL_1000  0x01410C50UL
 #define PHYID_MARVELL_1000S 0x01410C40UL
-
+#define PHYID_ICPLUS_IP101A 0x02430C54UL
 #define PHYID_REV_ID_MASK   0x0000000FUL
 
 #define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
@@ -1433,10 +1433,38 @@ struct velocity_opt {
 
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
+static inline char velocity_choose_state(struct device *dev,
+					   pm_message_t state)
+
+{
+	switch (state.event) {
+	case PM_EVENT_ON:
+		return PCI_D0;
+	case PM_EVENT_FREEZE:
+	case PM_EVENT_PRETHAW:
+		/* REVISIT both freeze and pre-thaw "should" use D0 */
+	case PM_EVENT_SUSPEND:
+	case PM_EVENT_HIBERNATE:
+		return PCI_D3hot;
+	default:
+		dev_info(dev, "unrecognized suspend event %d\n", state.event);
+		BUG();
+	}
+
+	return PCI_D0;
+}
+
+enum velocity_bus_type {
+	BUS_PCI,
+	BUS_PLATFORM,
+};
+
 struct velocity_info {
-	struct device *dev;
 	struct pci_dev *pdev;
+	struct device *dev;
 	struct net_device *netdev;
+	enum velocity_bus_type bustype;
+	int no_eeprom;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
-- 
1.7.9.5



From eduardo.valentin at ti.com  Thu May  2 14:46:31 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 2 May 2013 14:46:31 -0400
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502180627.GA10672@arwen.pp.htv.fi>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com> <51829D65.7040109@ti.com>
 <20130502180627.GA10672@arwen.pp.htv.fi>
Message-ID: <5182B487.7090801@ti.com>

On 02-05-2013 14:06, Felipe Balbi wrote:
> Hi,
> 
> On Thu, May 02, 2013 at 01:07:49PM -0400, Eduardo Valentin wrote:
>> Arnd, Tony,
>>
>> On 02-05-2013 11:38, Tony Lindgren wrote:
>>> * Russell King - ARM Linux <linux at arm.linux.org.uk> [130502 01:27]:
>>>> On Tue, Apr 30, 2013 at 09:17:39AM +0100, Russell King - ARM Linux wrote:
>>>>> Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
>>>>> great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
>>>>> arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
>>>>> source of errors.
>>>>>
>>>>> OMAP stuff needs a serious look at too - much Kconfig madness there
>>>>> caused by over-use of select, which then goes on to cause build errors
>>>>> because it assumes some stuff is always enabled.
>>>>>
>>>>> There's also warnings about of_device_id from include/linux/of_platform.h
>>>>> via from arch/arm/kernel/setup.c which feature in all the non-OF builds
>>>>> too which need addressing.
>>>>>
>>>>> See todays http://www.arm.linux.org.uk/developer/build/ results for all
>>>>> the details and configs.  Not pushing my tree until some of this stuff
>>>>> gets fixed.
>>>>
>>>> And now we have a new bunch of warnings from OMAP stuff which weren't
>>>> previously there...
>>>>
>>>> arch/arm/mach-omap2/omap_device.c: In function 'omap_device_get_by_hwmod_name':
>>>> arch/arm/mach-omap2/omap_device.c:821:3: warning: return makes pointer from integer without a cast
>>>> arch/arm/mach-omap2/omap_device.c:826:3: warning: return makes pointer from integer without a cast
>>>
>>> Hmm these I already fixed earlier along with a merge resolution, and
>>> I'm not seeing them in next/master or arm-soc/for-next. What do you
>>> have merged into your current tree?
>>>
>>>> drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
>>>> drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result
>>>
>>> Neil, care to provide a fix for this? It's from your commit ab37813
>>> (twl4030_charger: Allow charger to control the regulator that feeds it).
>>>
>>>> include/linux/thermal.h:254:12: warning: 'thermal_generate_netlink_event' defined but not used
>>>
>>> Eduardo, can you fix that one? It seems to be from your commit 8ab3e6a
>>> (thermal: Use thermal zone device id in netlink messages).
>>
>> Yeah sure I can fix it. As simple as the following:
>> From c04244c87312f5bfc61d9e12ba3fbaa0fdd81adb Mon Sep 17 00:00:00 2001
>> From: Eduardo Valentin <eduardo.valentin at ti.com>
>> Date: Thu, 2 May 2013 12:58:20 -0400
>> Subject: [PATCH 1/1] thermal: remove stub for thermal_generate_netlink_event
>>
>> This patch removes the stub for thermal_generate_netlink_event
>> because this function is not used anywhere inside the kernel.
>>
>> In case CONFIG_NET is not set we get:
>> include/linux/thermal.h:254:12: warning:
>> 'thermal_generate_netlink_event' defined but not used
>>
>> Thus removing it.
>>
>> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
>> ---
>>  include/linux/thermal.h | 6 ------
>>  1 file changed, 6 deletions(-)
>>
>> diff --git a/include/linux/thermal.h b/include/linux/thermal.h
>> index e3c0ae9..e3f3cba 100644
>> --- a/include/linux/thermal.h
>> +++ b/include/linux/thermal.h
>> @@ -250,12 +250,6 @@ void thermal_unregister_governor(struct
>> thermal_governor *);
>>  #ifdef CONFIG_NET
>>  extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
>>  						enum events event);
>> -#else
>> -static int thermal_generate_netlink_event(struct thermal_zone_device *tz,
> 
> just adding 'inline' would be an easier patch and lets you compile fine
> on !CONFIG_NET when you starting using thermal_generate_netlink_event().
> 

Yeah, that is one thing. But as I pointed, the fix is actually to remove
the whole netlink thing.

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From linux at arm.linux.org.uk  Thu May  2 14:48:01 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:48:01 +0100
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305021938170.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021811560.5398@kaball.uk.xensource.com>
 <20130502171516.GA3040@mudshark.cambridge.arm.com>
 <alpine.DEB.2.02.1305021816490.5398@kaball.uk.xensource.com>
 <20130502182812.GD14496@n2100.arm.linux.org.uk>
 <alpine.DEB.2.02.1305021938170.5398@kaball.uk.xensource.com>
Message-ID: <20130502184801.GF14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 07:42:58PM +0100, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Russell King - ARM Linux wrote:
> > On Thu, May 02, 2013 at 06:20:32PM +0100, Stefano Stabellini wrote:
> > > On Thu, 2 May 2013, Will Deacon wrote:
> > > > Hi Stefano,
> > > > 
> > > > On Thu, May 02, 2013 at 06:12:12PM +0100, Stefano Stabellini wrote:
> > > > > ping
> > > > 
> > > > Is this a ping to have this pulled into Russell's tree?
> > > 
> > > I thought that we agreed that the patches should go via the arm-soc
> > > tree, after Russell acks them.
> > 
> > Okay, well, is there a reason for them to go through arm-soc?  They
> > look more like core code to me than SoC specific - they only minimally
> > touch mach-virt.
> 
> The original reason is that some SoC specific code depends on this
> series (Calxeda I believe).
> 
> But you are probably right, if you prefer that I issue a pull request
> for your tree, I have no problems with that.

The only issue that there is is where we are in the development cycle
(almost mid merge window), and I've yet to push anything to Linus thanks
to late discovery of various messups in other chunks of code submitted
via my tree - I'm starting to drop stuff from my tree in the hope that
I'll get back to something that's going to be suitable for mainline.

I really don't want to go pulling anything else at the moment in the
hope of getting what I currently have out the door.

And in any case, we shouldn't be adding any new code to our trees at
this point in time.


From cov at codeaurora.org  Thu May  2 14:49:22 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Thu, 02 May 2013 14:49:22 -0400
Subject: [PATCH 2/3] xen: move do_stolen_accounting to drivers/xen/time.c
In-Reply-To: <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <5182B532.10607@codeaurora.org>

Hi Stefano,

On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> Move do_stolen_accounting, xen_vcpu_stolen and related functions and
> static variables to common code (drivers/xen/time.c).
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/x86/xen/time.c   |  127 +-------------------------------------------

In going through some of the code, it looked like there might be a few little
bits that you might be interested in pulling out of arch/ia64/xen/time.c as well.

[...]

Regards,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From jgunthorpe at obsidianresearch.com  Thu May  2 14:53:22 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 2 May 2013 12:53:22 -0600
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130502185322.GA29333@obsidianresearch.com>

On Thu, May 02, 2013 at 08:25:04PM +0200, Sebastian Hesselbarth wrote:
> +
> +static void __iomem *orion_irq_base[ORION_MAX_IRQREG];
> +static unsigned int orion_irq_regs;
> +static struct irq_domain *orion_irq_domain;
> +
> +asmlinkage void __exception_irq_entry orion_handle_irq(struct
> pt_regs *regs)

This can be static?

> +static int __init orion_of_init(struct device_node *np,
> +				struct device_node *parent)
> +{
> +	int n;
> +
> +	for (n = 0; n < ORION_MAX_IRQREG; n++) {
> +		orion_irq_base[n] = of_iomap(np, n);

Is it possible to also reserve the resources for these registers at
this point in the boot sequence?

> +static struct of_device_id orion_irq_dt_ids[] __initconst = {
> +	{ .compatible = "marvell,orion-mpic", .data = orion_of_init },
> +	{ }

Is there a strong reason to change the compatible string? Looks to me
like either the new driver or the old driver will bind depending on
what is in the machine description. No need for a new string?

> +};
> +
> +void __init orion_init_irq(void)
> +{
> +	of_irq_init(orion_irq_dt_ids);
> +}

Shouldn't this use the new IRQCHIP_DECLARE mechanism?

> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h

> +extern void orion_init_irq(void);

.. which lets this go away, use the generic irqchip_init instead of
orion_init_irq.

Regards,
Jason


From sebastian.hesselbarth at gmail.com  Thu May  2 14:54:20 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 20:54:20 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130502184514.GE14496@n2100.arm.linux.org.uk>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <5182B18C.4080404@gmail.com> <20130502184514.GE14496@n2100.arm.linux.org.uk>
Message-ID: <5182B65C.8030000@gmail.com>

On 05/02/13 20:45, Russell King - ARM Linux wrote:
> On Thu, May 02, 2013 at 08:33:48PM +0200, Sebastian Hesselbarth wrote:
>> On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
>>> This patch adds an irqchip driver for the main interrupt controller found
>>> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
>>> Corresponding device tree documentation is also added.
>>>
>>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>> ---
>>> Note: This patch triggers a checkpatch warning for
>>>     WARNING: Avoid CamelCase:<handle_IRQ>
>>>
>> [...]
>>> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
>>> new file mode 100644
>>> index 0000000..04f7bab
>>> --- /dev/null
>>> +++ b/include/linux/irqchip/orion.h
>>> @@ -0,0 +1,18 @@
>>> +/*
>>> + * Marvell Orion SoCs IRQ chip driver header.
>>> + *
>>> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public
>>> + * License version 2.  This program is licensed "as is" without any
>>> + * warranty of any kind, whether express or implied.
>>> + */
>>> +
>>> +#ifndef __LINUX_IRQCHIP_ORION_H
>>> +#define __LINUX_IRQCHIP_ORION_H
>>> +
>>> +#include<asm/exception.h>
>>
>> First review by myself. The above include is a left-over and
>> will be removed in a v2.
>
> You still need your first level IRQ handlers marked with __exception_irq_entry
> which is defined in the above file.
>

Russell,

I know and it is marked with __exception_irq_entry. The above is in
include/linux/irqchip/orion.h and only used for .init_irq in machine
descriptor later.

The irq handler is never exposed to the board file itself, but set
within orion_init_irq. This approach has been taked by
irqchip/irq-gic.c and irqchip/irq-vic.c rather than adding
.handle_irq to the machine descriptor.

Sebastian


From linux at arm.linux.org.uk  Thu May  2 14:54:49 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:54:49 +0100
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502153834.GR28721@atomide.com>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com>
Message-ID: <20130502185449.GD21614@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 08:38:34AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux at arm.linux.org.uk> [130502 01:27]:
> > On Tue, Apr 30, 2013 at 09:17:39AM +0100, Russell King - ARM Linux wrote:
> > > Latest nightly build of 3.9+my for-next+arm-soc's for-next results in a
> > > great load of new warnings and errors.  arch/arm/common/mcpm_head.S,
> > > arch/arm/common/mcpm_platsmp.c, arch/arm/common/vlock.S are the biggest
> > > source of errors.
> > > 
> > > OMAP stuff needs a serious look at too - much Kconfig madness there
> > > caused by over-use of select, which then goes on to cause build errors
> > > because it assumes some stuff is always enabled.
> > > 
> > > There's also warnings about of_device_id from include/linux/of_platform.h
> > > via from arch/arm/kernel/setup.c which feature in all the non-OF builds
> > > too which need addressing.
> > > 
> > > See todays http://www.arm.linux.org.uk/developer/build/ results for all
> > > the details and configs.  Not pushing my tree until some of this stuff
> > > gets fixed.
> > 
> > And now we have a new bunch of warnings from OMAP stuff which weren't
> > previously there...
> > 
> > arch/arm/mach-omap2/omap_device.c: In function 'omap_device_get_by_hwmod_name':
> > arch/arm/mach-omap2/omap_device.c:821:3: warning: return makes pointer from integer without a cast
> > arch/arm/mach-omap2/omap_device.c:826:3: warning: return makes pointer from integer without a cast
> 
> Hmm these I already fixed earlier along with a merge resolution, and
> I'm not seeing them in next/master or arm-soc/for-next. What do you
> have merged into your current tree?

I just found the cause, and it's my cleanup branch.  Odd that it only
started appearing a couple of days ago.  Should now be fixed.


From linux at arm.linux.org.uk  Thu May  2 14:56:23 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 19:56:23 +0100
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182B65C.8030000@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <5182B18C.4080404@gmail.com> <20130502184514.GE14496@n2100.arm.linux.org.uk>
 <5182B65C.8030000@gmail.com>
Message-ID: <20130502185623.GG14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 08:54:20PM +0200, Sebastian Hesselbarth wrote:
> On 05/02/13 20:45, Russell King - ARM Linux wrote:
>> On Thu, May 02, 2013 at 08:33:48PM +0200, Sebastian Hesselbarth wrote:
>>> On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
>>>> This patch adds an irqchip driver for the main interrupt controller found
>>>> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
>>>> Corresponding device tree documentation is also added.
>>>>
>>>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>>> ---
>>>> Note: This patch triggers a checkpatch warning for
>>>>     WARNING: Avoid CamelCase:<handle_IRQ>
>>>>
>>> [...]
>>>> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
>>>> new file mode 100644
>>>> index 0000000..04f7bab
>>>> --- /dev/null
>>>> +++ b/include/linux/irqchip/orion.h
>>>> @@ -0,0 +1,18 @@
>>>> +/*
>>>> + * Marvell Orion SoCs IRQ chip driver header.
>>>> + *
>>>> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>>> + *
>>>> + * This file is licensed under the terms of the GNU General Public
>>>> + * License version 2.  This program is licensed "as is" without any
>>>> + * warranty of any kind, whether express or implied.
>>>> + */
>>>> +
>>>> +#ifndef __LINUX_IRQCHIP_ORION_H
>>>> +#define __LINUX_IRQCHIP_ORION_H
>>>> +
>>>> +#include<asm/exception.h>
>>>
>>> First review by myself. The above include is a left-over and
>>> will be removed in a v2.
>>
>> You still need your first level IRQ handlers marked with __exception_irq_entry
>> which is defined in the above file.
>>
>
> Russell,
>
> I know and it is marked with __exception_irq_entry. The above is in
> include/linux/irqchip/orion.h and only used for .init_irq in machine
> descriptor later.
>
> The irq handler is never exposed to the board file itself, but set
> within orion_init_irq. This approach has been taked by
> irqchip/irq-gic.c and irqchip/irq-vic.c rather than adding
> .handle_irq to the machine descriptor.

But I don't find an asm/exception.h include in drivers/irqchip/whateveryour.cfileiscalled


From arnd at arndb.de  Thu May  2 15:03:58 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 21:03:58 +0200
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <20130502184801.GF14496@n2100.arm.linux.org.uk>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021938170.5398@kaball.uk.xensource.com>
 <20130502184801.GF14496@n2100.arm.linux.org.uk>
Message-ID: <201305022103.58445.arnd@arndb.de>

On Thursday 02 May 2013, Russell King - ARM Linux wrote:
> The only issue that there is is where we are in the development cycle
> (almost mid merge window), and I've yet to push anything to Linus thanks
> to late discovery of various messups in other chunks of code submitted
> via my tree - I'm starting to drop stuff from my tree in the hope that
> I'll get back to something that's going to be suitable for mainline.
> 
> I really don't want to go pulling anything else at the moment in the
> hope of getting what I currently have out the door.
> 
> And in any case, we shouldn't be adding any new code to our trees at
> this point in time.

Agreed. I would have like to see the patches in 3.10, but the timing
didn't work out.

Stefano, I'm sure we can queue it up early for 3.11 if you send them
again after the merge window. Sorry you had to go through 10 versions
and not getting it merged in time in the end.

	Arnd


From sebastian.hesselbarth at gmail.com  Thu May  2 15:04:31 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 21:04:31 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130502185623.GG14496@n2100.arm.linux.org.uk>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <5182B18C.4080404@gmail.com> <20130502184514.GE14496@n2100.arm.linux.org.uk>
 <5182B65C.8030000@gmail.com> <20130502185623.GG14496@n2100.arm.linux.org.uk>
Message-ID: <5182B8BF.804@gmail.com>

On 05/02/13 20:56, Russell King - ARM Linux wrote:
> On Thu, May 02, 2013 at 08:54:20PM +0200, Sebastian Hesselbarth wrote:
>> On 05/02/13 20:45, Russell King - ARM Linux wrote:
>>> On Thu, May 02, 2013 at 08:33:48PM +0200, Sebastian Hesselbarth wrote:
>>>> On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
>>>>> This patch adds an irqchip driver for the main interrupt controller found
>>>>> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
>>>>> Corresponding device tree documentation is also added.
>>>>>
>>>>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>>>> ---
>>>>> Note: This patch triggers a checkpatch warning for
>>>>>      WARNING: Avoid CamelCase:<handle_IRQ>
>>>>>
>>>> [...]
>>>>> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
>>>>> new file mode 100644
>>>>> index 0000000..04f7bab
>>>>> --- /dev/null
>>>>> +++ b/include/linux/irqchip/orion.h
>>>>> @@ -0,0 +1,18 @@
>>>>> +/*
>>>>> + * Marvell Orion SoCs IRQ chip driver header.
>>>>> + *
>>>>> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>>>> + *
>>>>> + * This file is licensed under the terms of the GNU General Public
>>>>> + * License version 2.  This program is licensed "as is" without any
>>>>> + * warranty of any kind, whether express or implied.
>>>>> + */
>>>>> +
>>>>> +#ifndef __LINUX_IRQCHIP_ORION_H
>>>>> +#define __LINUX_IRQCHIP_ORION_H
>>>>> +
>>>>> +#include<asm/exception.h>
>>>>
>>>> First review by myself. The above include is a left-over and
>>>> will be removed in a v2.
>>>
>>> You still need your first level IRQ handlers marked with __exception_irq_entry
>>> which is defined in the above file.
>>>
>>
>> Russell,
>>
>> I know and it is marked with __exception_irq_entry. The above is in
>> include/linux/irqchip/orion.h and only used for .init_irq in machine
>> descriptor later.
>>
>> The irq handler is never exposed to the board file itself, but set
>> within orion_init_irq. This approach has been taked by
>> irqchip/irq-gic.c and irqchip/irq-vic.c rather than adding
>> .handle_irq to the machine descriptor.
>
> But I don't find an asm/exception.h include in drivers/irqchip/whateveryour.cfileiscalled
>

Well, that might be because you can magically _see_ compiler warnings
while I have to actually run the compiler ;)

With the review from Jason Gunthorpe things will move anyway and I
expect include/irqchip/orion.h to vanish in v2.

Sebastian



From sebastian.hesselbarth at gmail.com  Thu May  2 15:05:38 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 21:05:38 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130502185322.GA29333@obsidianresearch.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
Message-ID: <5182B902.7040908@gmail.com>

On 05/02/13 20:53, Jason Gunthorpe wrote:
> On Thu, May 02, 2013 at 08:25:04PM +0200, Sebastian Hesselbarth wrote:
>> +
>> +static void __iomem *orion_irq_base[ORION_MAX_IRQREG];
>> +static unsigned int orion_irq_regs;
>> +static struct irq_domain *orion_irq_domain;
>> +
>> +asmlinkage void __exception_irq_entry orion_handle_irq(struct
>> pt_regs *regs)
>
> This can be static?

True, corresponds with the left-over #include in linux/irqchip/orion.h.

>> +static int __init orion_of_init(struct device_node *np,
>> +				struct device_node *parent)
>> +{
>> +	int n;
>> +
>> +	for (n = 0; n < ORION_MAX_IRQREG; n++) {
>> +		orion_irq_base[n] = of_iomap(np, n);
>
> Is it possible to also reserve the resources for these registers at
> this point in the boot sequence?

I see what I can do.

>> +static struct of_device_id orion_irq_dt_ids[] __initconst = {
>> +	{ .compatible = "marvell,orion-mpic", .data = orion_of_init },
>> +	{ }
>
> Is there a strong reason to change the compatible string? Looks to me
> like either the new driver or the old driver will bind depending on
> what is in the machine description. No need for a new string?

The reason for a new compatible string is, that we will also need an
secondary irq controller for bridge irqs. That could be called
marvell,orion-spic. Dove is again a little bit different than the
others and this will require timer and especially rtc not to share
bridge irqs here. RTC irq is located in PMU regs on Dove instead of
bridge regs.

But I don't have a strong opinion here and we can also reuse
marvell,orion-intc for the irqchip driver.

>> +};
>> +
>> +void __init orion_init_irq(void)
>> +{
>> +	of_irq_init(orion_irq_dt_ids);
>> +}
>
> Shouldn't this use the new IRQCHIP_DECLARE mechanism?

I didn't follow irqchip discussion lately, but will catch up.

>
>> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
>
>> +extern void orion_init_irq(void);
>
> .. which lets this go away, use the generic irqchip_init instead of
> orion_init_irq.

Same as above.

Thanks for the review,
   Sebastian



From arnd at arndb.de  Thu May  2 15:11:40 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 21:11:40 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130502185322.GA29333@obsidianresearch.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
Message-ID: <201305022111.41043.arnd@arndb.de>

On Thursday 02 May 2013, Jason Gunthorpe wrote:
> > +static struct of_device_id orion_irq_dt_ids[] __initconst = {
> > +     { .compatible = "marvell,orion-mpic", .data = orion_of_init },
> > +     { }
> 
> Is there a strong reason to change the compatible string? Looks to me
> like either the new driver or the old driver will bind depending on
> what is in the machine description. No need for a new string?
> 

The compatible string should change if the binding changes in an
incomptible way, and we should try not to change it unless it's
fundamentally flawed.

	Arnd


From arnd at arndb.de  Thu May  2 15:12:42 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 21:12:42 +0200
Subject: [PATCH, RFC 16/22] USB: UHCI: clarify Kconfig dependencies
In-Reply-To: <Pine.LNX.4.44L0.1305021423450.1436-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305021423450.1436-100000@iolanthe.rowland.org>
Message-ID: <201305022112.42583.arnd@arndb.de>

On Thursday 02 May 2013, Alan Stern wrote:
> On Thu, 2 May 2013, Arnd Bergmann wrote:
> 
> > > What do you think of my patch as compared to yours? 
> > 
> > I think in the end it comes down to the question where you want to
> > head with your driver. The way I did my version was going towards
> > making it similar to EHCI, with stand-alone bus glue drivers
> > and a core that is just a library module but does not register
> > a device_driver by itself.
> > 
> > Given that there are just three bus glues from UHCI, and at most
> > two of them enabled at the same time, I don't see a direct need
> > for UHCI to go down the same route as EHCI. If you want to just
> > leave this driver alone, your patch is simpler and has the same
> > effect in the end. Otherwise I think my patch avoids changing it
> > all again once the driver gets reworked.
> 
> Okay then, I'll submit my patch to Greg after the merge window closes.

Ok, thanks!

	Arnd


From jason at lakedaemon.net  Thu May  2 15:19:34 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 2 May 2013 15:19:34 -0400
Subject: [PATCH 0/3] ARM: dove: prepare and move to orion irqchip driver
In-Reply-To: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130502191934.GH31290@titan.lakedaemon.net>

On Thu, May 02, 2013 at 08:25:37PM +0200, Sebastian Hesselbarth wrote:
> This patch set moves Dove to the recently introduced irqchip driver
> for Marvell Orion SoCs. First, init code for timer and mv643xx_eth
> is added to prepare legacy non-DT drivers for virtual irqs provided by
> irqchip drivers. Then DT enabled boards for Dove are moved to the
> orion irqchip driver.
> 
> Note: This patch set depends on irqchip driver for Orion SoCs patch.
> 
> Sebastian Hesselbarth (3):
>   ARM: dove: add DT parsing for legacy mv643xx_eth
>   ARM: dove: add DT parsing for legacy timer
>   ARM: dove: move DT boards to orion irqchip driver
> 
>  arch/arm/boot/dts/dove.dtsi   |   18 ++++++++-

In the next version, please send the dtsi changes as separate patches.
This will reduce merge conflicts on our end.

Also, and I'll note this on the other thread as well, please put the
drivers/irqchip patch in the same series as this so the dependency is
clear.

In it's current state, your driver patch can only conflict with other
work in drivers/irqchip/{Makefile,Kconfig}.  This easy for us.  So we
should try to get an Ack from the irqchip folks to keep that patch with
this series and prevent a cross-tree dependency.

thx,

Jason.

>  arch/arm/mach-dove/Kconfig    |    1 +
>  arch/arm/mach-dove/Makefile   |    4 +-
>  arch/arm/mach-dove/board-dt.c |   77 ++++++++++++++++++++++++++++++++++++-----
>  4 files changed, 87 insertions(+), 13 deletions(-)
> ---
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> -- 
> 1.7.2.5
> 


From jason at lakedaemon.net  Thu May  2 15:22:28 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 2 May 2013 15:22:28 -0400
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130502192228.GI31290@titan.lakedaemon.net>

On Thu, May 02, 2013 at 08:25:04PM +0200, Sebastian Hesselbarth wrote:
> This patch adds an irqchip driver for the main interrupt controller found
> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
> Corresponding device tree documentation is also added.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Note: This patch triggers a checkpatch warning for
>   WARNING: Avoid CamelCase: <handle_IRQ>
> 
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  .../interrupt-controller/marvell,orion-mpic.txt    |   22 ++++
>  drivers/irqchip/Kconfig                            |    5 +
>  drivers/irqchip/Makefile                           |    1 +
>  drivers/irqchip/irq-orion.c                        |  129 ++++++++++++++++++++
>  include/linux/irqchip/orion.h                      |   18 +++
>  5 files changed, 175 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt
>  create mode 100644 drivers/irqchip/irq-orion.c
>  create mode 100644 include/linux/irqchip/orion.h

Sebastian,

Could you please include this patch in the next version of the series
depending on it.  I'd like to get an Ack from the irqchip folks for us
to take this patch through mvebu/arm-soc.

This will prevent an external tree dependency, and any resulting merge
conflict will be a trivial add in Kconfig or Makefile.

thx,

Jason.

> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt
> new file mode 100644
> index 0000000..3b303ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-mpic.txt
> @@ -0,0 +1,22 @@
> +Marvell Orion SoC main interrupt controller
> +
> +Required properties:
> +- compatible: shall be "marvell,orion-mpic"
> +- reg: base address(es) of interrupt registers starting with CAUSE register
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt source, shall be 1.
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of first base address,
> +- 1 maps to bit 1 of first base address,
> +- 32 maps to bit 0 of second base address, and so on.
> +
> +Example:
> +	intc: interrupt-controller {
> +		compatible = "marvell,orion-mpic";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +                /* Dove has 64 primary interrupts */
> +		reg = <0x20200 0x10>, <0x20210 0x10>;
> +	};
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index a350969..8da3559 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -2,6 +2,11 @@ config IRQCHIP
>  	def_bool y
>  	depends on OF_IRQ
>  
> +config IRQCHIP_ORION
> +	bool
> +	select IRQ_DOMAIN
> +	select MULTI_IRQ_HANDLER
> +
>  config ARM_GIC
>  	bool
>  	select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 98e3b87..8adbd43 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
>  
>  obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
>  obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
> +obj-$(CONFIG_IRQCHIP_ORION)		+= irq-orion.o
>  obj-$(CONFIG_METAG)			+= irq-metag-ext.o
>  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
>  obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi.o
> diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
> new file mode 100644
> index 0000000..ea02e11
> --- /dev/null
> +++ b/drivers/irqchip/irq-orion.c
> @@ -0,0 +1,129 @@
> +/*
> + * Marvell Orion SoCs IRQ chip driver.
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/orion.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <asm/mach/irq.h>
> +
> +/* max number of handled irq register blocks */
> +#define ORION_MAX_IRQREG		2
> +
> +#define ORION_IRQ_CAUSE			0x00
> +#define ORION_IRQ_MASK			0x04
> +#define ORION_IRQ_FIQ_MASK		0x08
> +#define ORION_IRQ_ENDP_MASK		0x0c
> +
> +static void __iomem *orion_irq_base[ORION_MAX_IRQREG];
> +static unsigned int orion_irq_regs;
> +static struct irq_domain *orion_irq_domain;
> +
> +asmlinkage void __exception_irq_entry orion_handle_irq(struct pt_regs *regs)
> +{
> +	int n;
> +	for (n = 0; n < orion_irq_regs; n++) {
> +		u32 hwirq_base = n * 32;
> +		u32 stat = readl_relaxed(orion_irq_base[n] + ORION_IRQ_CAUSE) &
> +			   readl_relaxed(orion_irq_base[n] + ORION_IRQ_MASK);
> +		while (stat) {
> +			u32 hwirq = ffs(stat) - 1;
> +			u32 irq = irq_find_mapping(orion_irq_domain,
> +						hwirq_base + hwirq);
> +			handle_IRQ(irq, regs);
> +			stat &= ~(1 << hwirq);
> +		}
> +	}
> +}
> +
> +static void orion_irq_mask(struct irq_data *irqd)
> +{
> +	unsigned int irq = irqd_to_hwirq(irqd);
> +	unsigned int irq_off = irq % 32;
> +	int reg = irq / 32;
> +	u32 val;
> +
> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> +	writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}
> +
> +static void orion_irq_unmask(struct irq_data *irqd)
> +{
> +	unsigned int irq = irqd_to_hwirq(irqd);
> +	unsigned int irq_off = irq % 32;
> +	int reg = irq / 32;
> +	u32 val;
> +
> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> +	writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}
> +
> +static struct irq_chip orion_irq_chip = {
> +	.name		= "orion_irq",
> +	.irq_mask	= orion_irq_mask,
> +	.irq_unmask	= orion_irq_unmask,
> +};
> +
> +static int orion_irq_map(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw)
> +{
> +	irq_set_chip_and_handler(virq, &orion_irq_chip,
> +				 handle_level_irq);
> +	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
> +
> +	return 0;
> +}
> +
> +static struct irq_domain_ops orion_irq_ops = {
> +	.map = orion_irq_map,
> +	.xlate = irq_domain_xlate_onecell,
> +};
> +
> +static int __init orion_of_init(struct device_node *np,
> +				struct device_node *parent)
> +{
> +	int n;
> +
> +	for (n = 0; n < ORION_MAX_IRQREG; n++) {
> +		orion_irq_base[n] = of_iomap(np, n);
> +
> +		if (!orion_irq_base[n])
> +			continue;
> +
> +		/* mask all interrupts */
> +		writel(0, orion_irq_base[n] + ORION_IRQ_MASK);
> +		orion_irq_regs++;
> +	}
> +
> +	/* at least one irq reg must be set */
> +	if (!orion_irq_regs)
> +		panic("%s: unable to map IRQC registers\n", np->full_name);
> +
> +	orion_irq_domain = irq_domain_add_linear(np, orion_irq_regs * 32,
> +						 &orion_irq_ops, NULL);
> +	if (!orion_irq_domain)
> +		panic("%s: unable to create IRQ domain\n", np->full_name);
> +
> +	set_handle_irq(orion_handle_irq);
> +
> +	return 0;
> +}
> +
> +static struct of_device_id orion_irq_dt_ids[] __initconst = {
> +	{ .compatible = "marvell,orion-mpic", .data = orion_of_init },
> +	{ }
> +};
> +
> +void __init orion_init_irq(void)
> +{
> +	of_irq_init(orion_irq_dt_ids);
> +}
> diff --git a/include/linux/irqchip/orion.h b/include/linux/irqchip/orion.h
> new file mode 100644
> index 0000000..04f7bab
> --- /dev/null
> +++ b/include/linux/irqchip/orion.h
> @@ -0,0 +1,18 @@
> +/*
> + * Marvell Orion SoCs IRQ chip driver header.
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __LINUX_IRQCHIP_ORION_H
> +#define __LINUX_IRQCHIP_ORION_H
> +
> +#include <asm/exception.h>
> +
> +extern void orion_init_irq(void);
> +
> +#endif
> -- 
> 1.7.2.5
> 


From sebastian.hesselbarth at gmail.com  Thu May  2 15:34:30 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 21:34:30 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <201305022111.41043.arnd@arndb.de>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
 <201305022111.41043.arnd@arndb.de>
Message-ID: <5182BFC6.3070709@gmail.com>

On 05/02/2013 09:11 PM, Arnd Bergmann wrote:
> On Thursday 02 May 2013, Jason Gunthorpe wrote:
>>> +static struct of_device_id orion_irq_dt_ids[] __initconst = {
>>> +     { .compatible = "marvell,orion-mpic", .data = orion_of_init },
>>> +     { }
>>
>> Is there a strong reason to change the compatible string? Looks to me
>> like either the new driver or the old driver will bind depending on
>> what is in the machine description. No need for a new string?
>>
>
> The compatible string should change if the binding changes in an
> incomptible way, and we should try not to change it unless it's
> fundamentally flawed.

Well, there is no _fundamental_ change in the binding syntax as it
is only reg, interrupts, and clocks. But there is a semantic change
in reg properties, as current orion irq controller wants the mask
registers (0x04,0x08) only while this also needs cause register
(0x00).

Nothing that couldn't be handled while moving Orion arch to irqchip
but if there are no further objections, I'd like to stick with the new
compatible string - also having orion-spic in mind.

Sebastian


From jgunthorpe at obsidianresearch.com  Thu May  2 15:35:10 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 2 May 2013 13:35:10 -0600
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182B902.7040908@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
 <5182B902.7040908@gmail.com>
Message-ID: <20130502193510.GA29522@obsidianresearch.com>

On Thu, May 02, 2013 at 09:05:38PM +0200, Sebastian Hesselbarth wrote:

> >>+static struct of_device_id orion_irq_dt_ids[] __initconst = {
> >>+	{ .compatible = "marvell,orion-mpic", .data = orion_of_init },
> >>+	{ }
> >
> >Is there a strong reason to change the compatible string? Looks to me
> >like either the new driver or the old driver will bind depending on
> >what is in the machine description. No need for a new string?
> 
> The reason for a new compatible string is, that we will also need an
> secondary irq controller for bridge irqs. That could be called
> marvell,orion-spic. Dove is again a little bit different than the
> others and this will require timer and especially rtc not to share
> bridge irqs here. RTC irq is located in PMU regs on Dove instead of
> bridge regs.

As Arnd mentioned, I would keep the old name then..

The bridge controller can be called marvell,orion-intc-bridge, and if
Dove needs a pmu controller, marvell,dove-intc-pmu ?

> >.. which lets this go away, use the generic irqchip_init instead of
> >orion_init_irq.
> 
> Same as above.

I have kirkwood HW but I haven't had time to make newer kernels run on
it, otherwise I'd test it too :(

Jason


From jgunthorpe at obsidianresearch.com  Thu May  2 15:37:26 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 2 May 2013 13:37:26 -0600
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182BFC6.3070709@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
 <201305022111.41043.arnd@arndb.de> <5182BFC6.3070709@gmail.com>
Message-ID: <20130502193726.GA29622@obsidianresearch.com>

On Thu, May 02, 2013 at 09:34:30PM +0200, Sebastian Hesselbarth wrote:

> >The compatible string should change if the binding changes in an
> >incomptible way, and we should try not to change it unless it's
> >fundamentally flawed.
> 
> Well, there is no _fundamental_ change in the binding syntax as it
> is only reg, interrupts, and clocks. But there is a semantic change
> in reg properties, as current orion irq controller wants the mask
> registers (0x04,0x08) only while this also needs cause register
> (0x00).

Oh, I didn't notice that, good point - the original binding was flawed
in that regard :|

Jason


From gmbnomis at gmail.com  Thu May  2 15:38:36 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Thu, 2 May 2013 21:38:36 +0200
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130502095431.GA20730@arm.com>
References: <20130418111608.GF27197@titan.lakedaemon.net>
 <20130418112201.GQ14496@n2100.arm.linux.org.uk>
 <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
Message-ID: <20130502193835.GA29144@schnuecks.de>

Hi Catalin,

On Thu, May 02, 2013 at 10:54:31AM +0100, Catalin Marinas wrote:
> On Wed, May 01, 2013 at 08:04:41PM +0100, Simon Baatz wrote:
> > On Wed, May 01, 2013 at 03:22:06PM +0100, Catalin Marinas wrote:
> > > On Tue, Apr 30, 2013 at 10:04:03PM +0100, Simon Baatz wrote:
> > > > On Tue, Apr 30, 2013 at 12:22:25PM +0100, Catalin Marinas wrote:
> > > > > On Sun, Apr 21, 2013 at 11:06:30PM +0100, Simon Baatz wrote:
> > > > > > On Thu, Apr 18, 2013 at 02:51:04PM +0100, Catalin Marinas wrote:
> > > > > > > On Thu, Apr 18, 2013 at 12:40:16PM +0100, Jason Cooper wrote:
> > > > ...
> > > > > > 
> > > > > > It is not the driver itself which is using the API, it is the
> > > > > > generic scatterlist memory iterator. And I don't think that this is
> > > > > > wrong, as I have tried to explain in [1].
> > > > > 
> > > > > Trying to remember what we've discussed over the past months on this
> > > > > topic. It looks like sg_miter_stop() does the right thing in calling
> > > > > flush_kernel_dcache_page(). Commit f8b63c1 (ARM: 6382/1: Remove
> > > > > superfluous flush_kernel_dcache_page()) removed this function entirely.
> > > > > The code previously had this comment - /* highmem pages are always
> > > > > flushed upon kunmap already */ which I think it wasn't fully correct
> > > > > either. The kunmap_atomic() flushes the caches but kunmap() doesn't, so
> > > > > I suspect we only get the flushing if SG_MITER_ATOMIC.
> > > > > 
> > > > > So it looks to me like flush_kernel_dcache_page() should be implemented
> > > > > even for highmem pages (with VIVT or aliasing VIPT, at least for non
> > > > > kmap_atomic addresses by checking for FIXADDR_START). If highmem is
> > > > > disabled, I suspect we still need this function since the calling code
> > > > > doesn't care whether kmap/kunmap was a no-op. But can we keep it as a
> > > > > simple call to __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE)?
> > > > 
> > > > My first version ([1]) had:
> > > > 
> > > > 	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
> > > > 		__flush_kernel_dcache_page(page);
> > > > 
> > > > If I understand this correctly, you are proposing to remove the
> > > > highmem exclusion.
> > > 
> > > The highmem exclusion may have been there originally because of a
> > > comment suggesting that kunmap() does the flushing. This is the case
> > > only for kunmap_atomic() AFAICT (and maybe we could remove that as well
> > > and rely on flush_kernel_dcache_page() being called).
> > > 
> > > > And then in __flush_kernel_dcache_page():
> > > > 
> > > > 	mapping = page_mapping(page);
> > > > 
> > > > 	if (!mapping || mapping_mapped(mapping))
> > > > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > > > 
> > > > I still prefer to have this condition here to avoid the flush when
> > > > there is no user mapping at all.  This is handled by lazy flushing
> > > > and is probably the most common case anyway (given how many people
> > > > seem to be affected by this problem).
> > > 
> > > Looking at the old thread, you said there is a case when this condition
> > > is not true (O_DIRECT case). If that's for a page cache page, then we
> > > can handle it lazily (for anonymous pages I don't think we can rely on
> > > lazy flushing since the kernel does not guarantee the clearing of the
> > > PG_arch_1 bit).
> > 
> > As Russel pointed out in a comment to a later version of the patch,
> > PG_arch_1 makes only sense for page cache pages. The condition above
> > is ok from my point of view (it is based on what flush_dcache_page()
> > uses):
> > 
> > - Page cache page without user space mapping:
> > mapping != NULL and mapping_mapped() == 0
> > 
> > -> no flush here; lazy flush based on PG_arch_1 later if needed (we
> >    rely on the proper initialization of the page to "dirty" here.)
> 
> Indeed.
> 
> > - Page cache page with user space mapping:
> > mapping != NULL and mapping_mapped() != 0
> > 
> > -> kernel mapping flushed here (user mapping can be assumed to be clean)
> 
> We had similar thoughts for AArch64 here and decided it's not needed, it
> can just clear the PG_arch_1 bit and do it lazily (patches not pushed
> yet, need more testing). This assumes that even if mapping_mapped(), the
> page is not actually mapped in user space and we eventually get a
> set_pte_at() call. That's what powerpc is doing.

For arm64 only I-/D-cache coherency is relevant, right? In this case,
that may be right (but you may want to have a look at what
xol_get_insn_slot() in kernel/events/uprobes.c does.  I don't know
what kind of pages it handles, but this looks suspicious. And I think
uprobes are also available for powerpc).

However, if you can have aliases in D-cache this is needed.  See
below to trigger this on pages that are already mapped
to user space (direct I/O into a memory mapped file).
 
> > - Anonymous page:
> > mapping == NULL
> > 
> > -> kernel mapping flushed here (user mapping can be assumed to be clean)
> 
> I don't think it should care about anonymous pages at all. I put a
> WARN_ON(!mapping) in flush_dcache_page() and it hasn't triggered yet,
> though not intensive testing.

I assume that you inhibited the call to flush_dcache_page() in
__get_user_pages() for anon pages.  Otherwise, you will be flooded
with warnings.

DIY steps to produce both cases:
(We will need software encryption, thus I need to remove the hardware
encryption module mv_cesa on my hardware first)

# rmmod mv_cesa     
# wget -O mapping_tests.c http://ubuntuone.com/0jF9fNsguN8BvI1Z8fsBVI
# gcc -o mapping_tests mapping_tests.c
# dd if=/dev/urandom of=map.out bs=4k count=10
# dd if=/dev/urandom of=cdevice.img bs=4k count=10
# losetup /dev/loop0 cdevice.img 
# cryptsetup -c aes create c_sda2 /dev/loop0
<enter any passphrase>
# ./mapping_tests

cryptsetup will already trigger the warning and mapping_tests should
flood your console.
 
Since flush_kernel_dcache_page() is supposed to handle user space
pages, it must flush the kernel mapping in these cases.  Running the
above on a device driver using an unpatched
flush_kernel_dcache_page() yields:

# ./mapping_tests 
Anonymous page: differs!
User space mapped page: differs!

It is even needed in flush_dcache_page() as long as everybody
continues to use flush_dcache_page() instead of
flush_kernel_dcache_page() when appropriate...
(This is probably the main reason why the problem I reported is so
uncommon: Everybody seems to use flush_dcache_page() and since it
flushes the kernel mapping in these cases, everything is fine.)

> > > > Additionally, although we can assume that the page is kmapped,
> > > > page_address(page) can still be NULL for a highmem page, right?
> > > 
> > > It looks like kmap() always sets page_address(page) but I'm not sure
> > > about kmap_atomic(), it doesn't seem to.
> > 
> > Hmm, in __flush_dcache_page() we have the following code to flush the
> > kernel mapping:
> > 
> > void __flush_dcache_page(struct address_space *mapping, struct page *page)
> > {
> > 	/*
> > 	 * Writeback any data associated with the kernel mapping of this
> > 	 * page.  This ensures that data in the physical page is mutually
> > 	 * coherent with the kernels mapping.
> > 	 */
> > 	if (!PageHighMem(page)) {
> > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > 	} else {
> > 		void *addr = kmap_high_get(page);
> > 		if (addr) {
> > 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> > 			kunmap_high(page);
> > 		} else if (cache_is_vipt()) {
> > 			/* unmapped pages might still be cached */
> > 			addr = kmap_atomic(page);
> > 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> > 			kunmap_atomic(addr);
> > 		}
> > 	}
> > ...
> > 
> > 
> > We probably should reuse it in flush_kernel_dcache_page() to flush
> > the kernel mapping. (The last else clause looks strange though)
> 
> I think it makes sense to reuse this logic in
> flush_kernel_dcache_page(). If the page is already mapped with kmap,
> then kmap_high_get() should return the actual address. If it was mapped
> with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
> clause and the additional kmap_atomic(). The cache_is_vipt() check is
> useful because kunmap_atomic() would flush VIVT caches anyway.

Yes, but why don't we flush for VIPT _aliasing_ already in
kunmap_atomic? Why do we need to do anything for non-aliasing VIPT
here?
 
> As for __flush_dcache_page() called from other places like
> flush_dcache_page(), because of this 'else if' clause it looks like it
> misses flushing unmapped highmem pages on VIVT cache.

How many users do we have with VIVT D-caches using highmem? (This is
not a rhetorical questions, I have no idea.  However, I would assume
that this use case is almost non-existent.)

- Simon



From robherring2 at gmail.com  Thu May  2 15:39:11 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 02 May 2013 14:39:11 -0500
Subject: [PATCH 4/4] ARM: highbank: fix build after cache flush change
In-Reply-To: <1367515404-512212-5-git-send-email-arnd@arndb.de>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
 <1367515404-512212-5-git-send-email-arnd@arndb.de>
Message-ID: <5182C0DF.9000500@gmail.com>

On 05/02/2013 12:23 PM, Arnd Bergmann wrote:
> Commit "ARM: cpu hotplug: remove majority of cache flushing from
> platforms" has removed the inclusion of asm/cacheflush.h from
> a number of files. Highbank still needs it because it calls
> flush_cache_louis().

AFAICT, the commit in question only showed up buried in a reply to
another thread and was never cc'ed to the relevant platform maintainers...

> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Rob Herring <rob.herring at calxeda.com>
> ---

I'd rather see the highbank changes dropped as this will all go away
with PSCI in 3.11, but:

Acked-by: Rob Herring <rob.herring at calxeda.com>

Rob

>  arch/arm/mach-highbank/hotplug.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
> index 80957f4..a019e4e 100644
> --- a/arch/arm/mach-highbank/hotplug.c
> +++ b/arch/arm/mach-highbank/hotplug.c
> @@ -14,6 +14,7 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>  #include <linux/kernel.h>
> +#include <asm/cacheflush.h>
>  
>  #include "core.h"
>  #include "sysregs.h"
> 



From sebastian.hesselbarth at gmail.com  Thu May  2 15:39:24 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 21:39:24 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182BFC6.3070709@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
 <201305022111.41043.arnd@arndb.de> <5182BFC6.3070709@gmail.com>
Message-ID: <5182C0EC.7040008@gmail.com>

On 05/02/2013 09:34 PM, Sebastian Hesselbarth wrote:
> On 05/02/2013 09:11 PM, Arnd Bergmann wrote:
>> On Thursday 02 May 2013, Jason Gunthorpe wrote:
>>>> +static struct of_device_id orion_irq_dt_ids[] __initconst = {
>>>> + { .compatible = "marvell,orion-mpic", .data = orion_of_init },
>>>> + { }
>>>
>>> Is there a strong reason to change the compatible string? Looks to me
>>> like either the new driver or the old driver will bind depending on
>>> what is in the machine description. No need for a new string?
>>>
>>
>> The compatible string should change if the binding changes in an
>> incomptible way, and we should try not to change it unless it's
>> fundamentally flawed.
>
> Well, there is no _fundamental_ change in the binding syntax as it
> is only reg, interrupts, and clocks. But there is a semantic change
> in reg properties, as current orion irq controller wants the mask
> registers (0x04,0x08) only while this also needs cause register
> (0x00).
>
> Nothing that couldn't be handled while moving Orion arch to irqchip
> but if there are no further objections, I'd like to stick with the new
> compatible string - also having orion-spic in mind.

Taking Jason Gunthorpe's last reply, I will stick to the _old_
compatible string and name the bridge irq handler as Jason suggested.

I will send a v2 soon.

Sebastian


From linux at arm.linux.org.uk  Thu May  2 15:41:26 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 20:41:26 +0100
Subject: [PATCH 4/4] ARM: highbank: fix build after cache flush change
In-Reply-To: <5182C0DF.9000500@gmail.com>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
 <1367515404-512212-5-git-send-email-arnd@arndb.de>
 <5182C0DF.9000500@gmail.com>
Message-ID: <20130502194125.GH14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 02:39:11PM -0500, Rob Herring wrote:
> On 05/02/2013 12:23 PM, Arnd Bergmann wrote:
> > Commit "ARM: cpu hotplug: remove majority of cache flushing from
> > platforms" has removed the inclusion of asm/cacheflush.h from
> > a number of files. Highbank still needs it because it calls
> > flush_cache_louis().
> 
> AFAICT, the commit in question only showed up buried in a reply to
> another thread and was never cc'ed to the relevant platform maintainers...
> 
> > 
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> > Cc: Rob Herring <rob.herring at calxeda.com>
> > ---
> 
> I'd rather see the highbank changes dropped as this will all go away
> with PSCI in 3.11, but:
> 
> Acked-by: Rob Herring <rob.herring at calxeda.com>

I'll drop the removal of asm/cacheflush.h but not the rest of it; I
believe your existing code to be in error with or without my changes.


From gregory.clement at free-electrons.com  Thu May  2 15:43:22 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu,  2 May 2013 21:43:22 +0200
Subject: [PATCH] ARM: kirkwood: add button for OpenBlock A6
Message-ID: <1367523802-16372-1-git-send-email-gregory.clement@free-electrons.com>

The OpenBlocks A6 board has one software-controlled button on the
front side, labeled "INIT", so we add minimal support for this button
in the kernel.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f724..627d8d0 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -209,4 +209,17 @@
 			gpios = <&gpio1 11 1>;
 		};
         };
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+			button at 1 {
+			label = "Init Button";
+			linux,code = <116>;
+			gpios = <&gpio1 6 0>;
+		};
+	};
+
 };
-- 
1.7.9.5



From linux at arm.linux.org.uk  Thu May  2 15:44:33 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 20:44:33 +0100
Subject: [PATCH 4/4] ARM: highbank: fix build after cache flush change
In-Reply-To: <20130502194125.GH14496@n2100.arm.linux.org.uk>
References: <1367515404-512212-1-git-send-email-arnd@arndb.de>
 <1367515404-512212-5-git-send-email-arnd@arndb.de>
 <5182C0DF.9000500@gmail.com> <20130502194125.GH14496@n2100.arm.linux.org.uk>
Message-ID: <20130502194433.GI14496@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 08:41:26PM +0100, Russell King - ARM Linux wrote:
> On Thu, May 02, 2013 at 02:39:11PM -0500, Rob Herring wrote:
> > On 05/02/2013 12:23 PM, Arnd Bergmann wrote:
> > > Commit "ARM: cpu hotplug: remove majority of cache flushing from
> > > platforms" has removed the inclusion of asm/cacheflush.h from
> > > a number of files. Highbank still needs it because it calls
> > > flush_cache_louis().
> > 
> > AFAICT, the commit in question only showed up buried in a reply to
> > another thread and was never cc'ed to the relevant platform maintainers...
> > 
> > > 
> > > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > > Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> > > Cc: Rob Herring <rob.herring at calxeda.com>
> > > ---
> > 
> > I'd rather see the highbank changes dropped as this will all go away
> > with PSCI in 3.11, but:
> > 
> > Acked-by: Rob Herring <rob.herring at calxeda.com>
> 
> I'll drop the removal of asm/cacheflush.h but not the rest of it; I
> believe your existing code to be in error with or without my changes.

Actually, no I'm not even going to do that, because that is _wrong_.  This
is what my mach-highbank/hotplug.c looks like after my change:

#include <linux/kernel.h>
        
#include "core.h"
#include "sysregs.h"
 
extern void secondary_startup(void);

/*
 * platform-specific code to shutdown a CPU
 *
 */
void __ref highbank_cpu_die(unsigned int cpu)
{
        highbank_set_cpu_jump(cpu, phys_to_virt(0));
        highbank_set_core_pwr();

        cpu_do_idle();

        /* We should never return from idle */
        panic("highbank: cpu %d unexpectedly exit from shutdown\n", cpu);
}

hence my change is completely correct in removing asm/cacheflush.h.


From sebastian.hesselbarth at gmail.com  Thu May  2 15:48:50 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 21:48:50 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130502193510.GA29522@obsidianresearch.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com> <5182B902.7040908@gmail.com>
 <20130502193510.GA29522@obsidianresearch.com>
Message-ID: <5182C322.3030304@gmail.com>

On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
> I have kirkwood HW but I haven't had time to make newer kernels run on
> it, otherwise I'd test it too :(

I also have kirkwood HW but that will cut me from email as I use it as
relay server ;) Maybe I can turn it into a test bed for a while.

There is also Orion5x and Discovery Innovation (mv78xx0) to be tested.

@Jason Cooper: I will merge both irqchip and dove patches into one
patch set. I wasn't earlier because I didn't want the above SoCs to
slow down patch integration. And I will split dtsi changes into
separate patches as requested.

Sebastian



From ezequiel.garcia at free-electrons.com  Thu May  2 15:53:16 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Thu, 2 May 2013 16:53:16 -0300
Subject: [PATCH] ARM: kirkwood: add button for OpenBlock A6
In-Reply-To: <1367523802-16372-1-git-send-email-gregory.clement@free-electrons.com>
References: <1367523802-16372-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130502195315.GA4107@localhost>

Hi Gregory,

On Thu, May 02, 2013 at 09:43:22PM +0200, Gregory CLEMENT wrote:
> The OpenBlocks A6 board has one software-controlled button on the
> front side, labeled "INIT", so we add minimal support for this button
> in the kernel.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/boot/dts/kirkwood-openblocks_a6.dts |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> index d27f724..627d8d0 100644
> --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> @@ -209,4 +209,17 @@
>  			gpios = <&gpio1 11 1>;
>  		};
>          };
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +			button at 1 {
> +			label = "Init Button";
> +			linux,code = <116>;
> +			gpios = <&gpio1 6 0>;
> +		};
> +	};
> +
>  };

Shouldn't you add a proper pinctrl entry for this as well?

-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com


From linux at arm.linux.org.uk  Thu May  2 15:52:43 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 May 2013 20:52:43 +0100
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130502162433.GA10016@kahuna>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna>
Message-ID: <20130502195243.GE21614@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 11:24:33AM -0500, Nishanth Menon wrote:
> On 20:03-20130502, Alexander Shiyan wrote:
> > 
> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > ---
> >  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
> >  1 file changed, 17 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> > index aa27d7f..8d17a0d 100644
> > --- a/arch/arm/mach-omap2/usb-host.c
> > +++ b/arch/arm/mach-omap2/usb-host.c
> > @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> >  	supplies->dev_name = dev_id;
> >  
> >  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> > -	if (!reg_data)
> > +	if (!reg_data) {
> > +		kfree(supplies);
> >  		return -ENOMEM;
> > +	}
> >  
> >  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> >  	reg_data->consumer_supplies = supplies;
> > @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> >  
> >  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
> >  			GFP_KERNEL);
> > -	if (!config)
> > +	if (!config) {
> > +		kfree(supplies);
> > +		kfree(reg_data);
> >  		return -ENOMEM;
> > +	}
> >  
> >  	config->supply_name = name;
> >  	config->gpio = gpio;
> > @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> >  
> >  	/* create a regulator device */
> >  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> > -	if (!pdev)
> > +	if (!pdev) {
> > +		kfree(supplies);
> > +		kfree(reg_data);
> > +		kfree(config);
> >  		return -ENOMEM;
> > +	}
> >  
> >  	pdev->id = PLATFORM_DEVID_AUTO;
> >  	pdev->name = reg_name;
> >  	pdev->dev.platform_data = config;
> >  
> >  	ret = platform_device_register(pdev);
> > -	if (ret)
> > +	if (ret) {
> >  		pr_err("%s: Failed registering regulator %s for %s\n",
> >  				__func__, name, dev_id);
> > +		kfree(supplies);
> > +		kfree(reg_data);
> > +		kfree(config);
> > +	}
> 
> Might be better to switch to devm_XXX managed functions?

Oh god no.  Stop this madness right now.  Never kmalloc memory for
platform devices.  EVER.

There's an API provided to dynamically create platform devices.  Use it!


From arnd at arndb.de  Thu May  2 15:53:19 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 21:53:19 +0200
Subject: [PATCH, RFC 20/22] media: coda: select GENERIC_ALLOCATOR
In-Reply-To: <1367515255.447627800@f375.mail.ru>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-21-git-send-email-arnd@arndb.de>
 <1367515255.447627800@f375.mail.ru>
Message-ID: <201305022153.19518.arnd@arndb.de>

On Thursday 02 May 2013, Alexander Shiyan wrote:
> > The coda driver uses the generic allocator to get at the
> > "iram" memory, so add the necessary dependency to avoid:
> > 

> > diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> > index 0494d27..4608d03 100644
> > --- a/drivers/media/platform/Kconfig
> > +++ b/drivers/media/platform/Kconfig
> > @@ -145,6 +145,7 @@ config VIDEO_CODA
> >       depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXC
> >       select VIDEOBUF2_DMA_CONTIG
> >       select V4L2_MEM2MEM_DEV
> > +     select GENERIC_ALLOCATOR
> >       ---help---
> >          Coda is a range of video codec IPs that supports
> >          H.264, MPEG-4, and other video formats.
> 
> Again?
> 

Ah, now I remember where I saw this before -- you sent the same patch, and
Fabio commented that Shawn had already queued up a different solution.

Unfortunately, linux-next as of today is still broken. Shawn, did I
miss a pull request from you?

	Arnd


From nerv at dawncrow.de  Thu May  2 15:54:40 2013
From: nerv at dawncrow.de (=?ISO-8859-1?Q?Andr=E9_Hentschel?=)
Date: Thu, 02 May 2013 21:54:40 +0200
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <20130424094251.GA21850@mudshark.cambridge.arm.com>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
Message-ID: <5182C480.3080001@dawncrow.de>

Am 24.04.2013 11:42, schrieb Will Deacon:
> Hi Andrew,
> 
> On Tue, Apr 23, 2013 at 11:42:22PM +0100, Andr? Hentschel wrote:
>> Am 23.04.2013 11:15, schrieb Will Deacon:
>>> You could introduce `get' tls functions, which don't do anything for CPUs
>>> without the relevant registers.
>>
>> Before i have another round of testing and patch formatting/sending,
>> what about the untested patch below?
> 
> Ok. Comments inline.

I answered to that seperatly.
Here is another try based on your comments:



diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f..bb5b48d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..02f8674 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,48 +2,87 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
+	.macro check_hwcap_tls, tmp1
+	ldr	\tmp1, =elf_hwcap
+	ldr	\tmp1, [\tmp1, #0]
+	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
+	.endm
+
+
+	.macro get_tls_none, tp, tmp1
+	.endm
+
+	.macro get_tls_v6k, tp, tmp1
+	mrc	p15, 0, \tmp1, c13, c0, 2		@ get user r/w TLS register
+	str	\tmp1, [\tp, #4]
+	.endm
+
+	.macro get_tls_v6, tp, tmp1
+	check_hwcap_tls \tmp1
+	mrcne	p15, 0, \tmp1, c13, c0, 2		@ get user r/w TLS register
+	strne	\tmp1, [\tp, #4]
+	.endm
+
+
 	.macro set_tls_none, tp, tmp1, tmp2
 	.endm
 
 	.macro set_tls_v6k, tp, tmp1, tmp2
-	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	ldrd	\tmp1, \tmp2, [\tp]
+	mcr	p15, 0, \tmp1, c13, c0, 3	@ set user r/o TLS register
+	mcr	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
 	.endm
 
 	.macro set_tls_v6, tp, tmp1, tmp2
-	ldr	\tmp1, =elf_hwcap
-	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
-	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
-	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	check_hwcap_tls \tmp1
+	ldrdne	\tmp1, \tmp2, [\tp]
+	ldreq	\tmp1, [\tp]
+	mcrne	p15, 0, \tmp1, c13, c0, 3	@ yes, set user r/o TLS register
+	mcrne	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
+	streq	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
 
 	.macro set_tls_software, tp, tmp1, tmp2
-	mov	\tmp1, #0xffff0fff
-	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
+	ldr	\tmp1, [\tp]
+	mov	\tmp2, #0xffff0fff
+	str	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
 #endif
 
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
+#define get_tls		get_tls_none
 #define set_tls		set_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
+#define get_tls		get_tls_v6
 #define set_tls		set_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
+#define get_tls		get_tls_v6k
 #define set_tls		set_tls_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
+#define get_tls		get_tls_none
 #define set_tls		set_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline void get_tpidrurw(unsigned long *tpidrurw)
+{
+	unsigned long t;
+#ifdef CONFIG_TLS_REG_EMUL
+	return;
+#endif
+	if (!has_tls_reg) return;
+	__asm__("mcr p15, 0, %0, c13, c0, 2" : : "r" (t));
+	*tpidrurw = t;
+}
+#endif
+
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..2c892b2 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,7 +728,7 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
+	add	r3, r1, #TI_TP_VALUE
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
@@ -736,6 +736,8 @@ ENTRY(__switch_to)
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
+	get_tls	r3, r4
+	add	r3, r2, #TI_TP_VALUE
 	set_tls	r3, r4, r5
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e4..a13bbc8 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -36,6 +36,7 @@
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
 #include <asm/processor.h>
+#include <asm/tls.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
@@ -395,7 +396,10 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+	{
+		thread->tp_value[0] = childregs->ARM_r3;
+		get_tpidrurw(&thread->tp_value[1]);
+	}
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c08911..f9d6259 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }



From gregory.clement at free-electrons.com  Thu May  2 15:57:06 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu, 02 May 2013 21:57:06 +0200
Subject: [PATCH] ARM: kirkwood: add button for OpenBlock A6
In-Reply-To: <1367523802-16372-1-git-send-email-gregory.clement@free-electrons.com>
References: <1367523802-16372-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <5182C512.4050102@free-electrons.com>

On 05/02/2013 09:43 PM, Gregory CLEMENT wrote:
> The OpenBlocks A6 board has one software-controlled button on the
> front side, labeled "INIT", so we add minimal support for this button
> in the kernel.
> 

Oh, I found that Thomas have already submitted the same patch but I was
misleaded because I didn't find anything related to this in v3.9,
nor in next-20130502.

You can drop this patch of course, but waht happens to Thomas' patch?

> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/boot/dts/kirkwood-openblocks_a6.dts |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> index d27f724..627d8d0 100644
> --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> @@ -209,4 +209,17 @@
>  			gpios = <&gpio1 11 1>;
>  		};
>          };
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +			button at 1 {
> +			label = "Init Button";
> +			linux,code = <116>;
> +			gpios = <&gpio1 6 0>;
> +		};
> +	};
> +
>  };
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From andrew at lunn.ch  Thu May  2 16:02:04 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 2 May 2013 22:02:04 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182C322.3030304@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
 <5182B902.7040908@gmail.com>
 <20130502193510.GA29522@obsidianresearch.com>
 <5182C322.3030304@gmail.com>
Message-ID: <20130502200204.GA24965@lunn.ch>

On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
> On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
> >I have kirkwood HW but I haven't had time to make newer kernels run on
> >it, otherwise I'd test it too :(
> 
> I also have kirkwood HW but that will cut me from email as I use it as
> relay server ;) Maybe I can turn it into a test bed for a while.
> 
> There is also Orion5x and Discovery Innovation (mv78xx0) to be tested.

I can test kirkwood and Orion5x.

  Andrew


From gregory.clement at free-electrons.com  Thu May  2 16:08:51 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu, 02 May 2013 22:08:51 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130502200204.GA24965@lunn.ch>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com> <5182B902.7040908@gmail.com>
 <20130502193510.GA29522@obsidianresearch.com> <5182C322.3030304@gmail.com>
 <20130502200204.GA24965@lunn.ch>
Message-ID: <5182C7D3.3040308@free-electrons.com>

On 05/02/2013 10:02 PM, Andrew Lunn wrote:
> On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
>> On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
>>> I have kirkwood HW but I haven't had time to make newer kernels run on
>>> it, otherwise I'd test it too :(
>>
>> I also have kirkwood HW but that will cut me from email as I use it as
>> relay server ;) Maybe I can turn it into a test bed for a while.
>>
>> There is also Orion5x and Discovery Innovation (mv78xx0) to be tested.
> 
> I can test kirkwood and Orion5x.

And I can test mv78xx0

Gregory


From sylvester.nawrocki at gmail.com  Thu May  2 16:11:07 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Thu, 02 May 2013 22:11:07 +0200
Subject: [PATCH 8/9] s3c2410fb: Remove redundant platform_set_drvdata()
In-Reply-To: <000001ce46f6$54f27cc0$fed77640$@samsung.com>
References: <1367006543-5458-1-git-send-email-sylvester.nawrocki@gmail.com>
 <1367006543-5458-9-git-send-email-sylvester.nawrocki@gmail.com>
 <000001ce46f6$54f27cc0$fed77640$@samsung.com>
Message-ID: <5182C85B.7090305@gmail.com>

Hi Jingoo,

On 05/02/2013 07:31 AM, Jingoo Han wrote:
> On Saturday, April 27, 2013 5:02 AM, Sylwester Nawrocki wrote:
>> >  driver_data field is being cleared by the driver core since
>> >  commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
>> >  device-core: Ensure drvdata = NULL when no driver is bound
>> >  hence there is no need to do it in the driver's remove() callback.

> How about eliminating platform_set_drvdata(pdev, NULL)
> in s3c24xxfb_probe() as well as s3c2410fb_remove()?

Ah, thanks for pointing out. Indeed, that could be dropped too, I've
overlooked it somehow. Will update and resend this patch shortly.

Regards,
Sylwester


From olof at lixom.net  Thu May  2 16:34:03 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 May 2013 13:34:03 -0700
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <201305022103.58445.arnd@arndb.de>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021938170.5398@kaball.uk.xensource.com>
 <20130502184801.GF14496@n2100.arm.linux.org.uk>
 <201305022103.58445.arnd@arndb.de>
Message-ID: <CAOesGMgtwb5z-LcJNf7Jtnz92T7u3Z9_uzBxYCaD1ahwYa514A@mail.gmail.com>

Hi,

On Thu, May 2, 2013 at 12:03 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 02 May 2013, Russell King - ARM Linux wrote:
>> The only issue that there is is where we are in the development cycle
>> (almost mid merge window), and I've yet to push anything to Linus thanks
>> to late discovery of various messups in other chunks of code submitted
>> via my tree - I'm starting to drop stuff from my tree in the hope that
>> I'll get back to something that's going to be suitable for mainline.
>>
>> I really don't want to go pulling anything else at the moment in the
>> hope of getting what I currently have out the door.
>>
>> And in any case, we shouldn't be adding any new code to our trees at
>> this point in time.
>
> Agreed. I would have like to see the patches in 3.10, but the timing
> didn't work out.
>
> Stefano, I'm sure we can queue it up early for 3.11 if you send them
> again after the merge window. Sorry you had to go through 10 versions
> and not getting it merged in time in the end.

Yeah, sorry for being quiet on this; I've seen the patches go by but
also haven't looked closely at them since timing was pointing more
towards 3.11 material. 3.10 is already a very busy release for us on
arm-soc.

If there's SoC code that needs this as a base, we can do a shared
branch with Russell. That has worked well in the past -- he merges it
but we bring in a copy of the topic in our tree.


-Olof


From davem at davemloft.net  Thu May  2 16:51:19 2013
From: davem at davemloft.net (David Miller)
Date: Thu, 02 May 2013 16:51:19 -0400 (EDT)
Subject: [PATCHv5 0/3] Add support for velocity network driver on
 platform devices
In-Reply-To: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
References: <1367520365-18842-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <20130502.165119.1376209468571090341.davem@davemloft.net>


Please resubmit this when the net-next tree opens again, thanks!


From arnd at arndb.de  Thu May  2 17:02:53 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:53 +0200
Subject: [PATCH 4/9] ARM: SPEAr: conditionalize l2x0 support
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-5-git-send-email-arnd@arndb.de>

If the cache controller implementation is disabled at build time,
we must not call any functions related to it.

arch/arm/mach-spear/built-in.o: In function `spear13xx_l2x0_init':
arch/arm/mach-spear/spear13xx.c:47: undefined reference to `l2x0_init'

Cc: Viresh Kumar <viresh.linux at gmail.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-spear/spear13xx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 8e7cb45..5403c01 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -35,6 +35,8 @@ void __init spear13xx_l2x0_init(void)
 	 * write alloc and 'Full line of zero' options
 	 *
 	 */
+	if (!IS_ENABLED(CONFIG_CACHE_L2X0))
+		return;
 
 	writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
 
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:56 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:56 +0200
Subject: [PATCH 7/9] ARM: OMAP: don't select SERIAL_OMAP unconditionally
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-8-git-send-email-arnd@arndb.de>

It is possible to build a kernel without TTY support, so we must not
attempt to select SERIAL_OMAP in that case.

warning: (ARCH_OMAP2PLUS_TYPICAL) selects SERIAL_OMAP which has unmet direct dependencies (TTY && HAS_IOMEM && GENERIC_HARDIRQS && ARCH_OMAP2PLUS)

Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-omap2/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 857b1f0..a95c7af 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -37,8 +37,8 @@ config ARCH_OMAP2PLUS_TYPICAL
 	select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
 	select PM_RUNTIME
 	select REGULATOR
-	select SERIAL_OMAP
-	select SERIAL_OMAP_CONSOLE
+	select SERIAL_OMAP if TTY
+	select SERIAL_OMAP_CONSOLE if TTY
 	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
 	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
 	select VFP
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:52 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:52 +0200
Subject: [PATCH 3/9] ARM: imx: build CPU suspend code only when needed
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-4-git-send-email-arnd@arndb.de>

The ARM CPU suspend function has its own configuration symbol,
which we need to use for conditionalizing any code calling into
it as well.

arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
/git/arm-soc/arch/arm/mach-imx/headsmp.S:57: undefined
 reference to `cpu_resume'

Cc: Sascha Hauer <kernel at pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-imx/headsmp.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index a58c8b0..67b9c48 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -24,7 +24,7 @@ ENTRY(v7_secondary_startup)
 ENDPROC(v7_secondary_startup)
 #endif
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_ARM_CPU_SUSPEND
 /*
  * The following code must assume it is running from physical address
  * where absolute virtual addresses to the data section have to be
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:58 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:58 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-10-git-send-email-arnd@arndb.de>

The use of 'select' in the ux500 platform is a huge mess, we should
not be selecting most of the drivers that are currently selected
there, but rather enable them from the defconfig.

As a fixup for 3.10, let's at least select the dependencies for
the other drivers we already select, to make it consistent.

warning: (UX500_SOC_COMMON) selects AB8500_CORE which has unmet direct dependencies (HAS_IOMEM && GENERIC_HARDIRQS && ABX500_CORE && MFD_DB8500_PRCMU)

Cc: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-ux500/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index f66d7de..6a4387e 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -19,6 +19,8 @@ if ARCH_U8500
 config UX500_SOC_COMMON
 	bool
 	default y
+	select ABX500_CORE
+	select AB8500_CORE
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_764369 if SMP
 	select ARM_GIC
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:57 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:57 +0200
Subject: [PATCH 8/9] ARM: SIRF: select SMP_ON_UP only on SMP builds
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-9-git-send-email-arnd@arndb.de>

Like all other platforms, we can only select SMP_ON_UP if SMP
is also enabled.

warning: (SOC_IMX31 && SOC_IMX35 && ARCH_MARCO) selects
 SMP_ON_UP which has unmet direct dependencies (SMP && !XIP_KERNEL)

Cc: Barry Song <baohua.song at csr.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-prima2/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 80ca974..6988b11 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -38,7 +38,7 @@ config ARCH_MARCO
 	select CPU_V7
 	select HAVE_ARM_SCU if SMP
 	select HAVE_SMP
-	select SMP_ON_UP
+	select SMP_ON_UP if SMP
 	help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:55 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:55 +0200
Subject: [PATCH 6/9] ARM: SPEAr: conditionalize SMP code
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-7-git-send-email-arnd@arndb.de>

Some constant definitions are only defined for spear13xx, so
we must not attempt to build SPEAr SMP support when that
SoC is not enabled.

arch/arm/mach-spear/platsmp.c:25:35:
 error: 'VA_SCU_BASE' undeclared here (not in a function)
 arch/arm/mach-spear/platsmp.c: In function 'spear13xx_smp_prepare_cpus':
 arch/arm/mach-spear/platsmp.c:111:58: error: 'SYS_LOCATION' undeclared (first use in this function)

Cc: Viresh Kumar <viresh.linux at gmail.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-spear/Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile
index af9bffb..a946c19 100644
--- a/arch/arm/mach-spear/Makefile
+++ b/arch/arm/mach-spear/Makefile
@@ -7,10 +7,10 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 # Common support
 obj-y	:= restart.o time.o
 
-obj-$(CONFIG_SMP)		+= headsmp.o platsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
+smp-$(CONFIG_SMP)		+= headsmp.o platsmp.o
+smp-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
-obj-$(CONFIG_ARCH_SPEAR13XX)	+= spear13xx.o
+obj-$(CONFIG_ARCH_SPEAR13XX)	+= spear13xx.o $(smp-y)
 obj-$(CONFIG_MACH_SPEAR1310)	+= spear1310.o
 obj-$(CONFIG_MACH_SPEAR1340)	+= spear1340.o
 
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:49 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:49 +0200
Subject: [PATCH 0/9] arm-soc: randconfig fixes
Message-ID: <1367528578-518090-1-git-send-email-arnd@arndb.de>

Hi platform maintainers,

These patches are all fallout from randconfig testing, and I've
applied them directly to the arm-soc tree since I don't expect
them to be controversial. They will be part of the next set
of patch submissions to Linus.

Please have a look anyway.

Arnd Bergmann (9):
  ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
  ARM: OMAP: build SMP code only for OMAP4/5
  ARM: imx: build CPU suspend code only when needed
  ARM: SPEAr: conditionalize l2x0 support
  ARM: imx: reset_controller may be disabled
  ARM: SPEAr: conditionalize SMP code
  ARM: OMAP: don't select SERIAL_OMAP unconditionally
  ARM: SIRF: select SMP_ON_UP only on SMP builds
  ARM: ux500: always select ABX500_CORE

 arch/arm/mach-imx/headsmp.S     | 2 +-
 arch/arm/mach-imx/src.c         | 3 ++-
 arch/arm/mach-omap2/Kconfig     | 4 ++--
 arch/arm/mach-omap2/Makefile    | 8 ++++----
 arch/arm/mach-prima2/Kconfig    | 2 +-
 arch/arm/mach-spear/Makefile    | 6 +++---
 arch/arm/mach-spear/spear13xx.c | 2 ++
 arch/arm/mach-tegra/Kconfig     | 1 +
 arch/arm/mach-ux500/Kconfig     | 2 ++
 9 files changed, 18 insertions(+), 12 deletions(-)

-- 
1.8.1.2

Cc: Barry Song <baohua.song at csr.com>
Cc: Hiroshi Doyu <hdoyu at nvidia.com>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Stephen Warren <swarren at nvidia.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Viresh Kumar <viresh.linux at gmail.com>


From arnd at arndb.de  Thu May  2 17:02:50 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:50 +0200
Subject: [PATCH 1/9] ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-2-git-send-email-arnd@arndb.de>

Like the other Tegra SoCs using the same cpufreq driver, we
have to enable CPU_FREQ_TABLE for this one.

drivers/built-in.o: In function `tegra_cpu_exit':
 drivers/cpufreq/tegra-cpufreq.c:237: undefined reference to
 `cpufreq_frequency_table_cpuinfo'

Cc: Stephen Warren <swarren at nvidia.com>
Cc: Hiroshi Doyu <hdoyu at nvidia.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-tegra/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 597e76b..9878503 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -63,6 +63,7 @@ config ARCH_TEGRA_114_SOC
 	select ARM_ARCH_TIMER
 	select ARM_GIC
 	select ARM_L1_CACHE_SHIFT_6
+	select CPU_FREQ_TABLE if CPU_FREQ
 	select CPU_V7
 	select PINCTRL
 	select PINCTRL_TEGRA114
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:54 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:54 +0200
Subject: [PATCH 5/9] ARM: imx: reset_controller may be disabled
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-6-git-send-email-arnd@arndb.de>

The new reset controller API is optional, so if that is disabled,
we must not call it from platform code.

arch/arm/mach-imx/built-in.o: In function
 `imx_src_init': /git/arm-soc/arch/arm/mach-imx/src.c:144:
	undefined reference to `reset_controller_register'

Cc: Sascha Hauer <kernel at pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-imx/src.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index dc101898..10a6b1a 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -141,7 +141,8 @@ void __init imx_src_init(void)
 	WARN_ON(!src_base);
 
 	imx_reset_controller.of_node = np;
-	reset_controller_register(&imx_reset_controller);
+	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+		reset_controller_register(&imx_reset_controller);
 
 	/*
 	 * force warm reset sources to generate cold reset
-- 
1.8.1.2



From arnd at arndb.de  Thu May  2 17:02:51 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu,  2 May 2013 23:02:51 +0200
Subject: [PATCH 2/9] ARM: OMAP: build SMP code only for OMAP4/5
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <1367528578-518090-3-git-send-email-arnd@arndb.de>

The OMAP platform code assumes that SMP is only ever enabled when
CONFIG_ARCH_OMAP4 or CONFIG_SOC_OMAP5 is enabled, which is not
necessarirly true in a multiplatform configuration.

arch/arm/mach-omap2/built-in.o: In function `omap4_smp_prepare_cpus':
 :(.init.text+0x413c): undefined reference to `omap_get_wakeupgen_base'
 :(.init.text+0x415c): undefined reference to `omap_secure_apis_support'
arch/arm/mach-omap2/built-in.o: In function `omap4_boot_secondary':
 :(.cpuinit.text+0x28): undefined reference to `omap_get_wakeupgen_base'
 :(.cpuinit.text+0x3c): undefined reference to `omap_secure_apis_support'
arch/arm/mach-omap2/built-in.o: In function `omap4_cpu_die':
 :(.ref.text+0x8): undefined reference to `omap_get_wakeupgen_base'
 :(.ref.text+0x10): undefined reference to `omap_secure_apis_support'
 :(.ref.text+0x4c): undefined reference to `omap4_hotplug_cpu'
 :(.ref.text+0x50): undefined reference to `omap_secure_apis_support'

Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-omap2/Makefile | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e50b6da..f2d19af 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -32,12 +32,12 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)	+= sdrc.o
 
 # SMP support ONLY available for OMAP4
 
-obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
+smp-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
+smp-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
 omap-4-5-common				=  omap4-common.o omap-wakeupgen.o \
 					   sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common)
-obj-$(CONFIG_SOC_OMAP5)			+= $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common) $(smp-y)
+obj-$(CONFIG_SOC_OMAP5)			+= $(omap-4-5-common) $(smp-y)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
-- 
1.8.1.2



From rjw at sisk.pl  Thu May  2 17:19:53 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 02 May 2013 23:19:53 +0200
Subject: [PATCH 0/5] CPUFreq: ARM big LITTLE Fixes
In-Reply-To: <cover.1367241503.git.viresh.kumar@linaro.org>
References: <cover.1367241503.git.viresh.kumar@linaro.org>
Message-ID: <5220775.R7TYxWOgo3@vostro.rjw.lan>

On Monday, April 29, 2013 06:54:43 PM Viresh Kumar wrote:
> Hi Rafael,
> 
> I know I am late for this merge window and you have already closed the gates :)
> If you can still take them, its good, otherwise we will push this for v3.10-rc2.
> 
> These are minor fixes for ARM big LITTLE cpufreq driver. It doesn't impact any
> other driver or cpufreq core and are fairly independent.
> 
> Viresh Kumar (5):
>   cpufreq: ARM big LITTLE: Select PM_OPP
>   cpufreq: ARM big LITTLE DT: Return correct transition latency
>   cpufreq: ARM big LITTLE DT: Return CPUFREQ_ETERNAL if clock-latency
>     isn't found
>   cpufreq: ARM big LITTLE: Move cpu_to_cluster() to arm_big_little.h
>   cpufreq: ARM big LITTLE: Improve print message
> 
>  drivers/cpufreq/Kconfig.arm         | 1 +
>  drivers/cpufreq/arm_big_little.c    | 7 +------
>  drivers/cpufreq/arm_big_little.h    | 5 +++++
>  drivers/cpufreq/arm_big_little_dt.c | 9 +++++----
>  4 files changed, 12 insertions(+), 10 deletions(-)

All 5 queued up for the v3.10-rc2 push.

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From arnd at arndb.de  Thu May  2 17:20:00 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 May 2013 23:20:00 +0200
Subject: [PATCH 0/2] clk: add of_clk_provider stubs to enable clk-si5351
 on non OF
In-Reply-To: <1367369910-20402-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367369910-20402-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <201305022320.00769.arnd@arndb.de>

On Wednesday 01 May 2013, Sebastian Hesselbarth wrote:
> 
> Yesterday 02:58:27
> Enabling drivers that provide clocks on DT on platforms that don't have
> CONFIG_OF set fails due to compilation errors. This patch set first adds
> some stubs for of_clk_provider functions if CONFIG_OF is not set. Second
> it allows those platforms to build and use clk-si5351 i2c clock driver
> by removing the dependency on CONFIG_OF.
> 
> The above approach has been suggested by Arnd Bergmann and replaces the
> corresponding Kconfig patch for clk-si5351 posted earlier. It has been
> compile tested with allmodconfig on x86_64 for post v3.9.
> 
> Sebastian Hesselbarth (2):
>   clk: add non CONFIG_OF routines for clk-provider
>   clk: si5351: Allow to build without CONFIG_OF
> 

Acked-by: Arnd Bergmann <arnd at arndb.de>


From daniel.lezcano at linaro.org  Thu May  2 17:31:01 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Thu, 02 May 2013 23:31:01 +0200
Subject: [PATCH, RFC 03/22] cpuidle: calxeda: select ARM_CPU_SUSPEND
In-Reply-To: <1367507786-505303-4-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-4-git-send-email-arnd@arndb.de>
Message-ID: <5182DB15.2060006@linaro.org>

On 05/02/2013 05:16 PM, Arnd Bergmann wrote:
> Like other ARM specific drivers, this one requires ARM_CPU_SUSPEND,
> as shown by this linker error:
> 
> drivers/built-in.o: In function `calxeda_pwrdown_idle':
> drivers/cpuidle/cpuidle-calxeda.c:84: undefined reference to `cpu_suspend'
> drivers/cpuidle/cpuidle-calxeda.c:86: undefined reference to `cpu_resume'
> 
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
> Cc: linux-pm at vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>

> ---
>  drivers/cpuidle/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> index c4cc27e..e21cdfa 100644
> --- a/drivers/cpuidle/Kconfig
> +++ b/drivers/cpuidle/Kconfig
> @@ -36,6 +36,7 @@ if CPU_IDLE
>  config CPU_IDLE_CALXEDA
>  	bool "CPU Idle Driver for Calxeda processors"
>  	depends on ARCH_HIGHBANK
> +	select ARM_CPU_SUSPEND
>  	help
>  	  Select this to enable cpuidle on Calxeda processors.
>  
> 


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From cov at codeaurora.org  Thu May  2 17:33:29 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Thu, 02 May 2013 17:33:29 -0400
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <1367482772.21869.26.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
Message-ID: <5182DBA9.9080609@codeaurora.org>

Hi Ian,

On 05/02/2013 04:19 AM, Ian Campbell wrote:
> On Wed, 2013-05-01 at 21:36 +0100, Christopher Covington wrote:
>> Hi Stefano,
>>
>> On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
>>> Introduce a function, called arch_timer_stolen_ticks, called from the
>>> arch_timer interrupt handler to account for stolen ticks.
>>
>> [...]
>>
>>> diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
>>> index 7ade91d..30db413 100644
>>> --- a/arch/arm/include/asm/arch_timer.h
>>> +++ b/arch/arm/include/asm/arch_timer.h
>>> @@ -13,6 +13,11 @@
>>>  int arch_timer_of_register(void);
>>>  int arch_timer_sched_clock_init(void);
>>>  
>>> +/* per-platform function to calculate stolen ticks (clock cycles stolen
>>> + * to the vcpu by the hypervisor).

[...]

>> Is the hypervisor adjusting the Virtual Offset Register?
> 
> The virtual offset register is useful when a VCPU is migrated to another
> system to account for the differences in physical time on the two hosts
> but isn't useful for accounting for stolen time while running on a
> single host.
> 
> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
> would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
> where the timer goes off. Nor does it make sense to require that the
> guest actually be running for 5 before injecting the timer because that
> would mean real time elapsed time for the timer would be 5+3 in the case
> where 3 are stolen.

This is a bit of an aside, but I think that hiding time spent at higher
privilege levels can be a quite sensible approach to timekeeping in a
virtualized environment, but I understand that it's not the approach taken
with Xen, and as you pointed out above, adjusting the Virtual Offset Register
by itself isn't enough to implement that approach.

> So the virtual timer should appear to have been running even while time
> is being stolen and therefore stolen time needs to be accounted via some
> other means.

Something that's not currently obvious to me is that given that the stolen
cycle accounting should be done, what makes the architected timer interrupt
handler the ideal place to do it?

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From tglx at linutronix.de  Thu May  2 17:34:49 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Thu, 2 May 2013 23:34:49 +0200 (CEST)
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <alpine.LFD.2.02.1305022324371.2891@ionos>

Sebastian,

please do not take the rant below personally. You just happen to
trigger it.

On Thu, 2 May 2013, Sebastian Hesselbarth wrote:

> +static void orion_irq_mask(struct irq_data *irqd)
> +{
> +	unsigned int irq = irqd_to_hwirq(irqd);
> +	unsigned int irq_off = irq % 32;
> +	int reg = irq / 32;
> +	u32 val;
> +
> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> +	writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}
> +
> +static void orion_irq_unmask(struct irq_data *irqd)
> +{
> +	unsigned int irq = irqd_to_hwirq(irqd);
> +	unsigned int irq_off = irq % 32;
> +	int reg = irq / 32;
> +	u32 val;
> +
> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> +	writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}

I'm really tired of looking at the next incarnation of an OF/DT irq
chip driver, which reimplements stuff which I have consolidated in the
generic irq chip implementation with a lot of effort.

Just look at the various implementations in drivers/irqchip/ and find
out how similar they are. Moving code to drivers/irqchip/ does not
make an excuse for reestablishing the mess which was addressed by the
generic irq chip implementation.

Can you - and that means all of you ARM folks - please get your gear
together and add the missing features to the generic irq chip
implementation? I'm not going to accept more of that OF/DT frenzy.

Thanks,

	tglx


From thomas.petazzoni at free-electrons.com  Thu May  2 17:45:49 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 2 May 2013 23:45:49 +0200
Subject: [PATCH] ARM: kirkwood: add button for OpenBlock A6
In-Reply-To: <5182C512.4050102@free-electrons.com>
References: <1367523802-16372-1-git-send-email-gregory.clement@free-electrons.com>
 <5182C512.4050102@free-electrons.com>
Message-ID: <20130502234549.79caecc3@skate>

Dear Gregory CLEMENT,

On Thu, 02 May 2013 21:57:06 +0200, Gregory CLEMENT wrote:

> Oh, I found that Thomas have already submitted the same patch but I
> was misleaded because I didn't find anything related to this in v3.9,
> nor in next-20130502.
> 
> You can drop this patch of course, but waht happens to Thomas' patch?

I have to rework it as part as a refactoring of the pinctrl definitions
on kirkwood. I'll try to work on that soon.

Thanks,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sebastian.hesselbarth at gmail.com  Thu May  2 17:56:46 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 02 May 2013 23:56:46 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <alpine.LFD.2.02.1305022324371.2891@ionos>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <alpine.LFD.2.02.1305022324371.2891@ionos>
Message-ID: <5182E11E.5010103@gmail.com>

On 05/02/2013 11:34 PM, Thomas Gleixner wrote:
> please do not take the rant below personally. You just happen to
> trigger it.

Thomas,

it is okay for me - but thanks for the notice! I will comment below.

> On Thu, 2 May 2013, Sebastian Hesselbarth wrote:
>> +static void orion_irq_mask(struct irq_data *irqd)
>> +{
>> +	unsigned int irq = irqd_to_hwirq(irqd);
>> +	unsigned int irq_off = irq % 32;
>> +	int reg = irq / 32;
>> +	u32 val;
>> +
>> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
>> +	writel(val&  ~(1<<  irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
>> +}
>> +
>> +static void orion_irq_unmask(struct irq_data *irqd)
>> +{
>> +	unsigned int irq = irqd_to_hwirq(irqd);
>> +	unsigned int irq_off = irq % 32;
>> +	int reg = irq / 32;
>> +	u32 val;
>> +
>> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
>> +	writel(val | (1<<  irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
>> +}
>
> I'm really tired of looking at the next incarnation of an OF/DT irq
> chip driver, which reimplements stuff which I have consolidated in the
> generic irq chip implementation with a lot of effort.

Actually, non-irqchip implementation of orion intc was based on generic
irq chip already. I took a look at drivers/irqchip and realized that
at least sunxi (ARM again) was reimplementing mask/unmask the way
above. So I took the short path and copied that.

> Just look at the various implementations in drivers/irqchip/ and find
> out how similar they are. Moving code to drivers/irqchip/ does not
> make an excuse for reestablishing the mess which was addressed by the
> generic irq chip implementation.
>
> Can you - and that means all of you ARM folks - please get your gear
> together and add the missing features to the generic irq chip
> implementation? I'm not going to accept more of that OF/DT frenzy.

So you are suggesting to have a "linux,generic-intc" or you want me
to have "marvell,orion-intc" make use of generic irq chip again?

The second is easy, the first will take me a while to think about
proper DT properties how to encode mask/unmask/ack/.. availability
and offsets.

Regards,
   Sebastian


From arnd at arndb.de  Thu May  2 18:09:56 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 00:09:56 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182E11E.5010103@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <alpine.LFD.2.02.1305022324371.2891@ionos> <5182E11E.5010103@gmail.com>
Message-ID: <201305030009.57041.arnd@arndb.de>

On Thursday 02 May 2013, Sebastian Hesselbarth wrote:
> > Just look at the various implementations in drivers/irqchip/ and find
> > out how similar they are. Moving code to drivers/irqchip/ does not
> > make an excuse for reestablishing the mess which was addressed by the
> > generic irq chip implementation.
> >
> > Can you - and that means all of you ARM folks - please get your gear
> > together and add the missing features to the generic irq chip
> > implementation? I'm not going to accept more of that OF/DT frenzy.
> 
> So you are suggesting to have a "linux,generic-intc" or you want me
> to have "marvell,orion-intc" make use of generic irq chip again?
> 
> The second is easy, the first will take me a while to think about
> proper DT properties how to encode mask/unmask/ack/.. availability
> and offsets.

I think it should not be "linux,..." since the description can
well be OS independent. I don't have a good idea for a generic
name, but it's not very important.

The main missing piece in the generic irqchip code at the moment
is support for the linear irqdomain. Once we have that, a lot of
code can be simplified significantly.

	Arnd


From s-anna at ti.com  Thu May  2 18:09:07 2013
From: s-anna at ti.com (Suman Anna)
Date: Thu, 2 May 2013 17:09:07 -0500
Subject: [GIT PULL] mailbox driver framework for v3.10 merge window
In-Reply-To: <CAJe_Zhf5QwQQU5aVtNhbDT3EK9Dof-ZK_boP9WaNghqO8xY7iA@mail.gmail.com>
References: <37C860A02101E749A747FA2D3C1E3C504A1971@DLEE11.ent.ti.com>
 <201304091255.03020.arnd@arndb.de>
 <CAJe_Zhf5QwQQU5aVtNhbDT3EK9Dof-ZK_boP9WaNghqO8xY7iA@mail.gmail.com>
Message-ID: <5182E403.1030808@ti.com>

Hi Arnd,

On 04/28/2013 11:07 PM, Jassi Brar wrote:
> Hello Arnd,
> 
> On 9 April 2013 16:25, Arnd Bergmann <arnd at arndb.de> wrote:
>> On Thursday 04 April 2013, Anna, Suman wrote:
>>> OMAP and ST-Ericsson platforms are both using mailbox to communicate with some coprocessors. This series creates a consolidated framework, living under drivers/mailbox.
>>> The changes mainly contain:
>>> - create a mailbox framework independent from OMAP h/w
>>> - creates dbx500 mailbox driver for ST-Ericsson platforms
>>> - move the omap mailbox out of plat-omap/mach-omapX  adapting to the new framework.
>>> - minor bug fixes in mailbox code
>>
>> Pulled into a new next/mailbox branch, to keep it separate from the
>> existing subsystems.
>>
> I am going to be a heavy user of the Mailbox API. And I have reviewed
> this API quite in detail. I pointed out many aspects that might have
> worked for TI's usage but are not going to be work on many platforms
> (including one of mine).  Suman and Loic also acknowledged most (if
> not all) from 'generic' POV.  Here is the thread ...
>    http://www.spinics.net/lists/arm-kernel/msg239433.html
> 
> Not to mean only talk and no do, I prepared another proposal that
> addressed all the concerns shared so far in the RFC
> http://www.spinics.net/lists/kernel/msg1523873.html (its not ready for
> primetime yet)  And also converted the PL320 driver to the new API,
> unlike the pulled patchset which leaves that out in the cold.
> http://www.spinics.net/lists/kernel/msg1523874.html

Yes, the current code is mainly interrupt-driven and supports only
non-atomic context. We have a need to support atomic contexts and ipc
controllers that do not have interrupt-based triggering. As Jassi
pointed out, the RFC is not ready yet and there are still some
contention points that needs to be sorted out (especially to maintain
OMAP mailbox functionality).

> 
> Now, we could either call it (effectively the TI's framework with
> quirks for STE) as the "Common API" and then dismantle and convert it
> patch by patch (authors and I seem to agree many things need to be
> changed and implemented).
>   OR we do it reasonably right the first time even if that means yet
> another release. IMHO we should go for slow but steady thing.

I think it is your call here, either of the above approaches would
definitely involve some rework on the framework as well as both the OMAP
& ST mailboxes. Atleast for OMAP, the code exists in kernel but disabled
currently due to the multi-platform support. It is pending on the move
to drivers/mailbox folder, and can be enabled just with the first 3
patches (and another one for renaming generic mailbox.c/.h back to
omap_mailbox.c/.h files if we go the RFC approach) in the series
(irrespective of the framework). TI DSP/Bridge would remain broken
because of the omap dmtimer api dependencies on multi-platform.

I do not know how much of an impact it is for the ST driver as the
series adds the driver, and would have to wait until the RFC is sorted
out otherwise.

regards
Suman


From sebastian.hesselbarth at gmail.com  Thu May  2 18:37:20 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 03 May 2013 00:37:20 +0200
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <201305030009.57041.arnd@arndb.de>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <alpine.LFD.2.02.1305022324371.2891@ionos> <5182E11E.5010103@gmail.com>
 <201305030009.57041.arnd@arndb.de>
Message-ID: <5182EAA0.9070208@gmail.com>

On 05/03/2013 12:09 AM, Arnd Bergmann wrote:
> On Thursday 02 May 2013, Sebastian Hesselbarth wrote:
>>> Just look at the various implementations in drivers/irqchip/ and find
>>> out how similar they are. Moving code to drivers/irqchip/ does not
>>> make an excuse for reestablishing the mess which was addressed by the
>>> generic irq chip implementation.
>>>
>>> Can you - and that means all of you ARM folks - please get your gear
>>> together and add the missing features to the generic irq chip
>>> implementation? I'm not going to accept more of that OF/DT frenzy.
>>
>> So you are suggesting to have a "linux,generic-intc" or you want me
>> to have "marvell,orion-intc" make use of generic irq chip again?
>>
>> The second is easy, the first will take me a while to think about
>> proper DT properties how to encode mask/unmask/ack/.. availability
>> and offsets.
>
> I think it should not be "linux,..." since the description can
> well be OS independent. I don't have a good idea for a generic
> name, but it's not very important.
>
> The main missing piece in the generic irqchip code at the moment
> is support for the linear irqdomain. Once we have that, a lot of
> code can be simplified significantly.

Arnd, Thomas,

I still don't get it completely. Are you requesting a full blown
DT-enabled generic irq chip driver that can be setup by DT properties?

Or is it just to have current generic irq chip play with linear
irqdomain?

If it is just linear irqdomain, then I can have a look at it
now. I would first send v2 to allow the others to integrate
Kirkwood, Orion5x, and Discovery Innovation. Then v3 will
touch generic irq and merge that with orion irqchip.

(@Jason C: Are you sure that I should merge dove and orion
irqchip patches? I doubt that anything touching generic irq
will not go through irq tree.)

Sebastian


From linux at arm.linux.org.uk  Thu May  2 19:13:53 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 00:13:53 +0100
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130502164058.GC8577@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
Message-ID: <20130502231353.GF21614@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 07:40:58PM +0300, Felipe Balbi wrote:
> Hi,
> 
> On Thu, May 02, 2013 at 08:28:44PM +0400, Alexander Shiyan wrote:
> > > On 20:03-20130502, Alexander Shiyan wrote:
> > > > 
> > > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > > ---
> > > >  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
> > > >  1 file changed, 17 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> > > > index aa27d7f..8d17a0d 100644
> > > > --- a/arch/arm/mach-omap2/usb-host.c
> > > > +++ b/arch/arm/mach-omap2/usb-host.c
> > > > @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > >  	supplies->dev_name = dev_id;
> > > >  
> > > >  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> > > > -	if (!reg_data)
> > > > +	if (!reg_data) {
> > > > +		kfree(supplies);
> > > >  		return -ENOMEM;
> > > > +	}
> > > >  
> > > >  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> > > >  	reg_data->consumer_supplies = supplies;
> > > > @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > >  
> > > >  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
> > > >  			GFP_KERNEL);
> > > > -	if (!config)
> > > > +	if (!config) {
> > > > +		kfree(supplies);
> > > > +		kfree(reg_data);
> > > >  		return -ENOMEM;
> > > > +	}
> > > >  
> > > >  	config->supply_name = name;
> > > >  	config->gpio = gpio;
> > > > @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > >  
> > > >  	/* create a regulator device */
> > > >  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> > > > -	if (!pdev)
> > > > +	if (!pdev) {
> > > > +		kfree(supplies);
> > > > +		kfree(reg_data);
> > > > +		kfree(config);
> > > >  		return -ENOMEM;
> > > > +	}
> > > >  
> > > >  	pdev->id = PLATFORM_DEVID_AUTO;
> > > >  	pdev->name = reg_name;
> > > >  	pdev->dev.platform_data = config;
> > > >  
> > > >  	ret = platform_device_register(pdev);
> > > > -	if (ret)
> > > > +	if (ret) {
> > > >  		pr_err("%s: Failed registering regulator %s for %s\n",
> > > >  				__func__, name, dev_id);
> > > > +		kfree(supplies);
> > > > +		kfree(reg_data);
> > > > +		kfree(config);
> > > > +	}
> > > 
> > > Might be better to switch to devm_XXX managed functions?
> 
> I don't think it makes sense since the platform_device hasn't been
> registered yet.
> 
> Still, patch can be improved with proper goto labels instead of
> sprinkling different kfree() calls in every single error branch.
> 
> > If anyone can rewrite driver to use devm_xx, it would have been better.
> > I'm not going to redo the patch yet, let it be so, I just showed a point
> > for OMAP-developers.
> 
> fair enough.

Well, as long as this crap violates the driver model by using kfree() on
a device...  Devices are refcounted and must only be freed when the
refcount drops to zero.

This is exactly why we have platform_device_alloc(),
platform_device_register_full() and friends - so that people don't have to
fsck around with kzalloc themselves and get it wrong like the above does.

Would you like me to pass your details to gregkh for another one of his
public humilation exercises over basic kernel programming stuff? :)


From tony at atomide.com  Thu May  2 19:30:11 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 2 May 2013 16:30:11 -0700
Subject: [PATCH 2/9] ARM: OMAP: build SMP code only for OMAP4/5
In-Reply-To: <1367528578-518090-3-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-3-git-send-email-arnd@arndb.de>
Message-ID: <20130502233011.GT28721@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [130502 14:08]:
> The OMAP platform code assumes that SMP is only ever enabled when
> CONFIG_ARCH_OMAP4 or CONFIG_SOC_OMAP5 is enabled, which is not
> necessarirly true in a multiplatform configuration.
> 
> arch/arm/mach-omap2/built-in.o: In function `omap4_smp_prepare_cpus':
>  :(.init.text+0x413c): undefined reference to `omap_get_wakeupgen_base'
>  :(.init.text+0x415c): undefined reference to `omap_secure_apis_support'
> arch/arm/mach-omap2/built-in.o: In function `omap4_boot_secondary':
>  :(.cpuinit.text+0x28): undefined reference to `omap_get_wakeupgen_base'
>  :(.cpuinit.text+0x3c): undefined reference to `omap_secure_apis_support'
> arch/arm/mach-omap2/built-in.o: In function `omap4_cpu_die':
>  :(.ref.text+0x8): undefined reference to `omap_get_wakeupgen_base'
>  :(.ref.text+0x10): undefined reference to `omap_secure_apis_support'
>  :(.ref.text+0x4c): undefined reference to `omap4_hotplug_cpu'
>  :(.ref.text+0x50): undefined reference to `omap_secure_apis_support'
> 

Acked-by: Tony Lindgren <tony at atomide.com>

> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/arm/mach-omap2/Makefile | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index e50b6da..f2d19af 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -32,12 +32,12 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)	+= sdrc.o
>  
>  # SMP support ONLY available for OMAP4
>  
> -obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
> -obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
> +smp-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
> +smp-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
>  omap-4-5-common				=  omap4-common.o omap-wakeupgen.o \
>  					   sleep44xx.o
> -obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common)
> -obj-$(CONFIG_SOC_OMAP5)			+= $(omap-4-5-common)
> +obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common) $(smp-y)
> +obj-$(CONFIG_SOC_OMAP5)			+= $(omap-4-5-common) $(smp-y)
>  
>  plus_sec := $(call as-instr,.arch_extension sec,+sec)
>  AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
> -- 
> 1.8.1.2
> 


From tony at atomide.com  Thu May  2 19:32:49 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 2 May 2013 16:32:49 -0700
Subject: [PATCH 7/9] ARM: OMAP: don't select SERIAL_OMAP unconditionally
In-Reply-To: <1367528578-518090-8-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-8-git-send-email-arnd@arndb.de>
Message-ID: <20130502233249.GU28721@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [130502 14:08]:
> It is possible to build a kernel without TTY support, so we must not
> attempt to select SERIAL_OMAP in that case.
> 
> warning: (ARCH_OMAP2PLUS_TYPICAL) selects SERIAL_OMAP which has unmet direct dependencies (TTY && HAS_IOMEM && GENERIC_HARDIRQS && ARCH_OMAP2PLUS)
> 
> Cc: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/arm/mach-omap2/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 857b1f0..a95c7af 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -37,8 +37,8 @@ config ARCH_OMAP2PLUS_TYPICAL
>  	select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
>  	select PM_RUNTIME
>  	select REGULATOR
> -	select SERIAL_OMAP
> -	select SERIAL_OMAP_CONSOLE
> +	select SERIAL_OMAP if TTY
> +	select SERIAL_OMAP_CONSOLE if TTY
>  	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
>  	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
>  	select VFP

Please just drop this and pick my earlier fix instead:

[PATCH 1/3] ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP

Or let me know if you prefer me to queue it.

Regards,

Tony


From sebastian.hesselbarth at gmail.com  Thu May  2 19:48:34 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri,  3 May 2013 01:48:34 +0200
Subject: [PATCH v2 0/5] ARM: orion: add orion irqchip driver
In-Reply-To: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set adds an irqchip driver for the main interrupt controller
found on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation)
and the corresponding device tree documentation.

It also moves Dove as the first Orion SoC to this irqchip driver. 
As legacy non-DT drivers don't know about virtual irqs provided by irqchip
drivers, init code for timer and mv643xx_eth is added until true DT enabled
drivers are available. Finally, DT enabled boards for Dove are moved to the
orion irqchip driver.

*Note:*
This patch set is _not_ feature complete. There has been a request for
irqdomain support for generic irq and perhaps even a DT enabled generic
irq chip driver.

The patch set still can be used to port other Orion SoCs as I did with Dove.
It also merges irqchip driver patches with Dove patches to use this driver.

Sebastian Hesselbarth (5):
  irqchip: add support for Marvell Orion SoCs
  ARM: dove: add DT parsing for legacy mv643xx_eth
  ARM: dove: add DT parsing for legacy timer
  ARM: dove: move DT boards to orion irqchip driver
  ARM: dove: add DT nodes for irqchip conversion

 .../interrupt-controller/marvell,orion-intc.txt    |   22 ++++
 arch/arm/boot/dts/dove.dtsi                        |   16 ++-
 arch/arm/mach-dove/Kconfig                         |    1 +
 arch/arm/mach-dove/Makefile                        |    4 +-
 arch/arm/mach-dove/board-dt.c                      |   77 ++++++++++--
 drivers/irqchip/Kconfig                            |    5 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-orion.c                        |  133 ++++++++++++++++++++
 8 files changed, 247 insertions(+), 12 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
 create mode 100644 drivers/irqchip/irq-orion.c
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Thu May  2 19:48:35 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri,  3 May 2013 01:48:35 +0200
Subject: [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367538519-23940-2-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
Corresponding device tree documentation is also added.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: This patch triggers a checkpatch warning for
  WARNING: Avoid CamelCase: <handle_IRQ>

Changelog:
v1->v2:
- rename compatible string to "marvell,orion-intc" (Suggested by Jason Gunthorpe)
- request mem regions for irq base registers (Suggested by Jason Gunthorpe)
- make orion_handle_irq static (Suggested by Jason Gunthorpe)
- make use of IRQCHIP_DECLARE (Suggested by Jason Gunthorpe)

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 .../interrupt-controller/marvell,orion-intc.txt    |   22 ++++
 drivers/irqchip/Kconfig                            |    5 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-orion.c                        |  133 ++++++++++++++++++++
 4 files changed, 161 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
 create mode 100644 drivers/irqchip/irq-orion.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
new file mode 100644
index 0000000..9b7aee9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
@@ -0,0 +1,22 @@
+Marvell Orion SoC main interrupt controller
+
+Required properties:
+- compatible: shall be "marvell,orion-intc"
+- reg: base address(es) of interrupt registers starting with CAUSE register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1.
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of first base address,
+- 1 maps to bit 1 of first base address,
+- 32 maps to bit 0 of second base address, and so on.
+
+Example:
+	intc: interrupt-controller {
+		compatible = "marvell,orion-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+                /* Dove has 64 first level interrupts */
+		reg = <0x20200 0x10>, <0x20210 0x10>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a350969..8da3559 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -2,6 +2,11 @@ config IRQCHIP
 	def_bool y
 	depends on OF_IRQ
 
+config IRQCHIP_ORION
+	bool
+	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
+
 config ARM_GIC
 	bool
 	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 10ef57f..2cad23d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
+obj-$(CONFIG_IRQCHIP_ORION)		+= irq-orion.o
 obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
 obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
new file mode 100644
index 0000000..21ebe6c
--- /dev/null
+++ b/drivers/irqchip/irq-orion.c
@@ -0,0 +1,133 @@
+/*
+ * Marvell Orion SoCs IRQ chip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
+
+/* max number of handled irq register blocks */
+#define ORION_MAX_IRQREG		2
+
+#define ORION_IRQ_CAUSE			0x00
+#define ORION_IRQ_MASK			0x04
+#define ORION_IRQ_FIQ_MASK		0x08
+#define ORION_IRQ_ENDP_MASK		0x0c
+
+static void __iomem *orion_irq_base[ORION_MAX_IRQREG];
+static unsigned int orion_irq_regs;
+static struct irq_domain *orion_irq_domain;
+
+static asmlinkage void __exception_irq_entry orion_handle_irq(
+	struct pt_regs *regs)
+{
+	int n;
+	for (n = 0; n < orion_irq_regs; n++) {
+		u32 hwirq_base = n * 32;
+		u32 stat = readl_relaxed(orion_irq_base[n] + ORION_IRQ_CAUSE) &
+			readl_relaxed(orion_irq_base[n] + ORION_IRQ_MASK);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			u32 irq = irq_find_mapping(orion_irq_domain,
+						   hwirq_base + hwirq);
+			handle_IRQ(irq, regs);
+			stat &= ~(1 << hwirq);
+		}
+	}
+}
+
+static void orion_irq_mask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
+	writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
+}
+
+static void orion_irq_unmask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
+	writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
+}
+
+static struct irq_chip orion_irq_chip = {
+	.name		= "orion_irq",
+	.irq_mask	= orion_irq_mask,
+	.irq_unmask	= orion_irq_unmask,
+};
+
+static int orion_irq_map(struct irq_domain *d, unsigned int virq,
+			 irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &orion_irq_chip,
+				 handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops orion_irq_ops = {
+	.map = orion_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init orion_of_init(struct device_node *np,
+				struct device_node *parent)
+{
+	int n;
+
+	for (n = 0; n < ORION_MAX_IRQREG; n++) {
+		struct resource r;
+
+		/* parsing reg property may fail silently here */
+		if (of_address_to_resource(np, n, &r))
+			continue;
+
+		if (!request_mem_region(r.start, resource_size(&r), np->name))
+			panic("%s: unable to request mem region %d",
+			      np->full_name, n);
+
+		orion_irq_base[n] = ioremap(r.start, resource_size(&r));
+		if (!orion_irq_base[n])
+			panic("%s: unable to map resource %d",
+			      np->full_name, n);
+
+		/* mask all interrupts */
+		writel(0, orion_irq_base[n] + ORION_IRQ_MASK);
+		orion_irq_regs++;
+	}
+
+	/* at least one irq reg must be set */
+	if (!orion_irq_regs)
+		panic("%s: unable to map IRQC registers\n", np->full_name);
+
+	orion_irq_domain = irq_domain_add_linear(np, orion_irq_regs * 32,
+						 &orion_irq_ops, NULL);
+	if (!orion_irq_domain)
+		panic("%s: unable to create IRQ domain\n", np->full_name);
+
+	set_handle_irq(orion_handle_irq);
+
+	return 0;
+}
+IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_of_init);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Thu May  2 19:48:36 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri,  3 May 2013 01:48:36 +0200
Subject: [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
In-Reply-To: <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367538519-23940-3-git-send-email-sebastian.hesselbarth@gmail.com>

To allow to move to orion irqchip driver, existing legacy devices
have to map their irqs. This patch adds init code to map the
corresponding irqs. It will vanish as soon as there is true device tree
support for mv643xx_eth.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v1->v2:
- split off DT changes (Suggested by Jason Cooper)

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/board-dt.c |   31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd..9df6dd7 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -12,6 +12,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <asm/hardware/cache-tauros2.h>
@@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
 	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
 };
 
+#define DOVE_GE00_PHYS_BASE	0xf1070000
+
+static void __init dove_legacy_ge00_init(void)
+{
+	struct device_node *np = of_find_compatible_node(NULL, NULL,
+					 "marvell,mv643xx-eth-block");
+	int irq_sum, irq_err;
+
+	if (!np)
+		return;
+
+	irq_sum = irq_of_parse_and_map(np, 0);
+	if (!irq_sum) {
+		pr_err("%s: missing sum irq\n", np->full_name);
+		return;
+	}
+
+	irq_err = irq_of_parse_and_map(np, 1);
+	if (!irq_err) {
+		pr_err("%s: missing err irq\n", np->full_name);
+		return;
+	}
+
+	/* legacy ge00_init wants phys base */
+	orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
+			irq_sum, irq_err, 1600);
+}
+
 static void __init dove_dt_init(void)
 {
 	pr_info("Dove 88AP510 SoC\n");
@@ -70,7 +99,7 @@ static void __init dove_dt_init(void)
 	dove_of_clk_init();
 
 	/* Internal devices not ported to DT yet */
-	dove_ge00_init(&dove_dt_ge00_data);
+	dove_legacy_ge00_init();
 	dove_pcie_init(1, 1);
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Thu May  2 19:48:37 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri,  3 May 2013 01:48:37 +0200
Subject: [PATCH v2 3/5] ARM: dove: add DT parsing for legacy timer
In-Reply-To: <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367538519-23940-4-git-send-email-sebastian.hesselbarth@gmail.com>

To allow to move to orion irqchip driver, existing legacy devices
have to map their irqs. This patch adds init code to map the
corresponding irqs. It will vanish as soon as there is true device tree
support for orion timer.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v1->v2:
- split off DT changes (Suggested by Jason Cooper)

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/board-dt.c |   42 +++++++++++++++++++++++++++++++++++------
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 9df6dd7..cea65b7 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -12,6 +12,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -20,6 +21,7 @@
 #include <mach/pm.h>
 #include <plat/common.h>
 #include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 
 /*
@@ -48,10 +50,42 @@ static void __init dove_legacy_clk_init(void)
 			 of_clk_get_from_provider(&clkspec));
 }
 
-static void __init dove_of_clk_init(void)
+#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
+
+static void __init dove_legacy_timer_init(void)
 {
+	struct device_node *np = of_find_compatible_node(NULL, NULL,
+					 "marvell,orion-timer");
+	struct clk *clk;
+	void __iomem *base;
+	unsigned int tclk, irq;
+
+	/* Setup root of clk tree */
 	mvebu_clocks_init();
 	dove_legacy_clk_init();
+
+	if (!np)
+		panic("missing timer node\n");
+
+	base = of_iomap(np, 0);
+	if (!base)
+		panic("%s: missing reg base for timer\n", np->full_name);
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq)
+		panic("%s: missing irq for timer\n", np->full_name);
+
+	clk = of_clk_get(np, 0);
+	if (IS_ERR(clk))
+		panic("%s: missing clock for timer\n", np->full_name);
+
+	clk_prepare_enable(clk);
+	tclk = clk_get_rate(clk);
+	clk_put(clk);
+
+	orion_time_set_base(base);
+	/* legacy timer init gets bridge reg base */
+	orion_time_init(base - 0x300, BRIDGE_INT_TIMER1_CLR, irq, tclk);
 }
 
 static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
@@ -95,9 +129,6 @@ static void __init dove_dt_init(void)
 #endif
 	dove_setup_cpu_mbus();
 
-	/* Setup root of clk tree */
-	dove_of_clk_init();
-
 	/* Internal devices not ported to DT yet */
 	dove_legacy_ge00_init();
 	dove_pcie_init(1, 1);
@@ -112,9 +143,8 @@ static const char * const dove_dt_board_compat[] = {
 
 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
 	.map_io		= dove_map_io,
-	.init_early	= dove_init_early,
 	.init_irq	= orion_dt_init_irq,
-	.init_time	= dove_timer_init,
+	.init_time	= dove_legacy_timer_init,
 	.init_machine	= dove_dt_init,
 	.restart	= dove_restart,
 	.dt_compat	= dove_dt_board_compat,
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Thu May  2 19:48:38 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri,  3 May 2013 01:48:38 +0200
Subject: [PATCH v2 4/5] ARM: dove: move DT boards to orion irqchip driver
In-Reply-To: <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367538519-23940-5-git-send-email-sebastian.hesselbarth@gmail.com>

With legacy devices mapping their irqs, we can now switch DT enabled
boards to orion irqchip driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v1->v2:
- split off DT changes (Suggested by Jason Cooper)
- use irqchip_init (Suggested by Jason Gunthorpe)

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/Kconfig    |    1 +
 arch/arm/mach-dove/Makefile   |    4 ++--
 arch/arm/mach-dove/board-dt.c |    4 ++--
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d8..60d72b4 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,6 +22,7 @@ config MACH_CM_A510
 
 config MACH_DOVE_DT
 	bool "Marvell Dove Flattened Device Tree"
+	select IRQCHIP_ORION
 	select MVEBU_CLK_CORE
 	select MVEBU_CLK_GATING
 	select REGULATOR
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 3f0a858..4780f78 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,5 +1,5 @@
-obj-y				+= common.o addr-map.o irq.o
-obj-$(CONFIG_DOVE_LEGACY)	+= mpp.o
+obj-y				+= common.o addr-map.o
+obj-$(CONFIG_DOVE_LEGACY)	+= irq.o mpp.o
 obj-$(CONFIG_PCI)		+= pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)	+= dove-db-setup.o
 obj-$(CONFIG_MACH_DOVE_DT)	+= board-dt.o
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index cea65b7..404c993 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
+#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -20,7 +21,6 @@
 #include <asm/mach/arch.h>
 #include <mach/pm.h>
 #include <plat/common.h>
-#include <plat/irq.h>
 #include <plat/time.h>
 #include "common.h"
 
@@ -143,7 +143,7 @@ static const char * const dove_dt_board_compat[] = {
 
 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
 	.map_io		= dove_map_io,
-	.init_irq	= orion_dt_init_irq,
+	.init_irq	= irqchip_init,
 	.init_time	= dove_legacy_timer_init,
 	.init_machine	= dove_dt_init,
 	.restart	= dove_restart,
-- 
1.7.10.4



From chanho.min at lge.com  Thu May  2 19:52:10 2013
From: chanho.min at lge.com (Chanho Min)
Date: Fri, 3 May 2013 08:52:10 +0900
Subject: [PATCH, RFC 09/22] crypto: lz4: don't build on ARM
In-Reply-To: <1367507786-505303-1-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
Message-ID: <OF54831661.2286D403-ON49257B5F.00831E7A-49257B5F.00831E7D@lge.com>


>It is not currently possible to build the LZ4 code on ARM, so let's
>remove that option in Kconfig for now.
>
>lib/built-in.o: In function `lz4_compress64kctx':
> lib/lz4/lz4_compress.c:339: undefined reference to `__ctzsi2'
>lib/built-in.o: In function `lz4_compressctx':
> lib/lz4/lz4_compress.c:157: undefined reference to `__ctzsi2'
>lib/built-in.o: In function `lz4hc_commonlength':
> lib/lz4/lz4hc_compress.c:102: undefined reference to `__ctzsi2'
> lib/lz4/lz4hc_compress.c:102: undefined reference to `__ctzsi2'
>lib/built-in.o: In function `lz4hc_insertandgetwidermatch':
> lib/lz4/lz4hc_compress.c:230: undefined reference to `__ctzsi2'

Please, let me know the gcc version and tested defconfig.
I didn't have any problem to build with gcc 4.6.4 on armv7.
Some architecture need libgcc functions for __builtin_clz/ctz.
Porting them to lib is in progress:
http://marc.info/?l=linux-kernel&m=136748861811956&w=2
But, It doesn't happen on ARM, PowerPC and x86.

Thanks
Chanho Min
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From sebastian.hesselbarth at gmail.com  Thu May  2 19:48:39 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri,  3 May 2013 01:48:39 +0200
Subject: [PATCH v2 5/5] ARM: dove: add DT nodes for irqchip conversion
In-Reply-To: <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367538519-23940-6-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds required device tree nodes for irqchip conversion
on Dove. The nodes are named and layed out to allow seamless migration
to true DT enabled drivers as soon as they are available.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v1->v2:
- merge DT changes into this patch (Suggested by Jason Cooper)

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove.dtsi |   16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 6cab468..afb719a 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -30,11 +30,18 @@
 			marvell,tauros2-cache-features = <0>;
 		};
 
+		timer: timer {
+			compatible = "marvell,orion-timer";
+			reg = <0x20300 0x20>;
+			interrupts = <0>;
+			clocks = <&core_clk 0>;
+		};
+
 		intc: interrupt-controller {
 			compatible = "marvell,orion-intc";
 			interrupt-controller;
 			#interrupt-cells = <1>;
-			reg = <0x20204 0x04>, <0x20214 0x04>;
+			reg = <0x20200 0x10>, <0x20210 0x10>;
 		};
 
 		core_clk: core-clocks at d0214 {
@@ -202,6 +209,13 @@
 			status = "disabled";
 		};
 
+		gbe: ethernet-controller {
+			compatible = "marvell,mv643xx-eth-block";
+			reg = <0x72000 0x4000>;
+			interrupts = <29>, <30>;
+			status = "disabled";
+		};
+
 		rtc at d8500 {
 			compatible = "marvell,orion-rtc";
 			reg = <0xd8500 0x20>;
-- 
1.7.10.4



From sfr at canb.auug.org.au  Thu May  2 20:52:34 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 3 May 2013 10:52:34 +1000
Subject: [GIT PULL] Removal of GENERIC_GPIO
In-Reply-To: <51823DDA.7010103@nvidia.com>
References: <51823DDA.7010103@nvidia.com>
Message-ID: <20130503105234.6e9c8aa5ed2784bbe084caa8@canb.auug.org.au>

Hi Grant,

On Thu, 2 May 2013 19:20:10 +0900 Alex Courbot <acourbot at nvidia.com> wrote:
>
> Here is the pull request for the GENERIC_GPIO removal. It is almost 
> certain that a few fixups will be necessary - while I don't have precise 
> patches, the following steps should ensure the state of the code is clean:
> 
> * "git grep CONFIG_GENERIC_GPIO" should return 0 hits. Matches should be 
> replaced with CONFIG_GPIOLIB
> * "git grep '\bGENERIC_GPIO\b'" should return 1 hit in the Chinese 
> documentation. Selectors of GENERIC_GPIO should be turned into selectors 
> of GPIOLIB, while definitions of the option in architecture code should 
> be deleted.
> 
> Please let me know if there is something more I can do to ease your task.
> 
> Thanks,
> Alex.
> 
> The following changes since commit 10b38669d64c757cfd927e3820292c580ed70aae:
> 
>    Merge tag 'for-linus-v3.9-rc4' of git://oss.sgi.com/xfs/xfs 
> (2013-03-19 15:17:40 -0700)
> 
> are available in the git repository at:
> 
>    git://github.com/Gnurou/linux.git for_grant
> 
> for you to fetch changes up to f4c54050640e7afa4749875cf9b900d42db361c0:
> 
>    gpio: update gpio Chinese documentation (2013-04-16 18:47:22 +0900)

I currently have 3 merge fix patches for the gen-cpio tree:

gen-gpio: GPIOLIB merge fix up
merge fix for Convert selectors of GENERIC_GPIO to GPIOLIB
merge fix 2 for Convert selectors of GENERIC_GPIO to GPIOLIB

I have attached them.  All three are now applicable to Linus' tree.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From csd at broadcom.com  Thu May  2 20:57:33 2013
From: csd at broadcom.com (Christian Daudt)
Date: Thu, 2 May 2013 17:57:33 -0700
Subject: [PATCH V2] ARM: bcm281xx: Add L2 support for Rev A2 chips
Message-ID: <1367542653-955-1-git-send-email-csd@broadcom.com>

Rev A2 SoCs have an unorthodox memory re-mapping and this needs
to be reflected in the cache operations.
This patch adds new outer cache functions for the l2x0 driver
to support this SoC revision. It also adds a new compatible
value for the cache to enable this functionality.

Updates from V1:
- remove section 1 altogether and note that in comments
- simplify section selection caused by section 1 removal
- BUG_ON just in case section 1 shows up

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index cbef09b..69ddf9f 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -16,6 +16,9 @@ Required properties:
      performs the same operation).
 	"marvell,"aurora-outer-cache: Marvell Controller designed to be
 	 compatible with the ARM one with outer cache mode.
+	"bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+	offset needs to be added to the address before passing down to the L2
+	cache controller
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c..5e48c85 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,10 +47,10 @@
 	};
 
 	L2: l2-cache {
-		    compatible = "arm,pl310-cache";
-		    reg = <0x3ff20000 0x1000>;
-		    cache-unified;
-		    cache-level = <2>;
+		compatible = "bcm,bcm11351-a2-pl310-cache";
+		reg = <0x3ff20000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
 	};
 
 	timer at 35006000 {
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c465fac..d70e0ab 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
 	}
 }
 
+/*
+ * For certain Broadcom SoCs, depending on the address range, different offsets
+ * need to be added to the address before passing it to L2 for
+ * invalidation/clean/flush
+ *
+ * Section Address Range              Offset        EMI
+ *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
+ *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
+ *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
+ *
+ * When the start and end addresses have crossed two different sections, we
+ * need to break the L2 operation into two, each within its own section.
+ * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
+ * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
+ * 0xC0000000 - 0xC0001000
+ *
+ * Note 1:
+ * By breaking a single L2 operation into two, we may potentially suffer some
+ * performance hit, but keep in mind the cross section case is very rare
+ *
+ * Note 2:
+ * We do not need to handle the case when the start address is in
+ * Section 1 and the end address is in Section 3, since it is not a valid use
+ * case
+ *
+ * Note 3:
+ * Section 1 in practical terms can no longer be used on rev A2. Because of
+ * that the code does not need to handle section 1 at all.
+ *
+ */
+#define BCM_SYS_EMI_START_ADDR        0x40000000UL
+#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
+
+#define BCM_SYS_EMI_OFFSET            0x40000000UL
+#define BCM_VC_EMI_OFFSET             0x80000000UL
+
+static inline int bcm_addr_is_sys_emi(unsigned long addr)
+{
+	return (addr >= BCM_SYS_EMI_START_ADDR) &&
+		(addr < BCM_VC_EMI_SEC3_START_ADDR);
+}
+
+static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
+{
+	if (bcm_addr_is_sys_emi(addr))
+		return addr + BCM_SYS_EMI_OFFSET;
+	else
+		return addr + BCM_VC_EMI_OFFSET;
+}
+
+static void bcm_inv_range(unsigned long start, unsigned long end)
+{
+	unsigned long new_start, new_end;
+
+	BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+	if (unlikely(end <= start))
+		return;
+
+	new_start = bcm_l2_phys_addr(start);
+	new_end = bcm_l2_phys_addr(end);
+
+	/* normal case, no cross section between start and end */
+	if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+		l2x0_inv_range(new_start, new_end);
+		return;
+	}
+
+	/* They cross sections, so it can only be a cross from section
+	 * 2 to section 3
+	 */
+	l2x0_inv_range(new_start,
+		bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+	l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+		new_end);
+}
+
+static void bcm_clean_range(unsigned long start, unsigned long end)
+{
+	unsigned long new_start, new_end;
+
+	BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+	if (unlikely(end <= start))
+		return;
+
+	if ((end - start) >= l2x0_size) {
+		l2x0_clean_all();
+		return;
+	}
+
+	new_start = bcm_l2_phys_addr(start);
+	new_end = bcm_l2_phys_addr(end);
+
+	/* normal case, no cross section between start and end */
+	if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+		l2x0_clean_range(new_start, new_end);
+		return;
+	}
+
+	/* They cross sections, so it can only be a cross from section
+	 * 2 to section 3
+	 */
+	l2x0_clean_range(new_start,
+		bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+	l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+		new_end);
+}
+
+static void bcm_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long new_start, new_end;
+
+	BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+	if (unlikely(end <= start))
+		return;
+
+	if ((end - start) >= l2x0_size) {
+		l2x0_flush_all();
+		return;
+	}
+
+	new_start = bcm_l2_phys_addr(start);
+	new_end = bcm_l2_phys_addr(end);
+
+	/* normal case, no cross section between start and end */
+	if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+		l2x0_flush_range(new_start, new_end);
+		return;
+	}
+
+	/* They cross sections, so it can only be a cross from section
+	 * 2 to section 3
+	 */
+	l2x0_flush_range(new_start,
+		bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+	l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+		new_end);
+}
+
 static void __init l2x0_of_setup(const struct device_node *np,
 				 u32 *aux_val, u32 *aux_mask)
 {
@@ -765,6 +906,21 @@ static const struct l2x0_of_data aurora_no_outer_data = {
 	},
 };
 
+static const struct l2x0_of_data bcm_l2x0_data = {
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = bcm_inv_range,
+		.clean_range = bcm_clean_range,
+		.flush_range = bcm_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
@@ -773,6 +929,8 @@ static const struct of_device_id l2x0_ids[] __initconst = {
 	  .data = (void *)&aurora_no_outer_data},
 	{ .compatible = "marvell,aurora-outer-cache",
 	  .data = (void *)&aurora_with_outer_data},
+	{ .compatible = "bcm,bcm11351-a2-pl310-cache",
+	  .data = (void *)&bcm_l2x0_data},
 	{}
 };
 
-- 
1.7.10.4




From sfr at canb.auug.org.au  Thu May  2 21:03:18 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 3 May 2013 11:03:18 +1000
Subject: [GIT PULL] Removal of GENERIC_GPIO
In-Reply-To: <20130503105234.6e9c8aa5ed2784bbe084caa8@canb.auug.org.au>
References: <51823DDA.7010103@nvidia.com>
 <20130503105234.6e9c8aa5ed2784bbe084caa8@canb.auug.org.au>
Message-ID: <20130503110318.0d30b773852640ee94ba07b5@canb.auug.org.au>

Hi Guys,

On Fri, 3 May 2013 10:52:34 +1000 Stephen Rothwell <sfr at canb.auug.org.au> wrote:
>
> I currently have 3 merge fix patches for the gen-cpio tree:
> 
> gen-gpio: GPIOLIB merge fix up
> merge fix for Convert selectors of GENERIC_GPIO to GPIOLIB
> merge fix 2 for Convert selectors of GENERIC_GPIO to GPIOLIB
> 
> I have attached them.  All three are now applicable to Linus' tree.

Just to absolutely clear, I *do not* expect either of you to rebase your
trees or backmerge Linus' tree to fix these, I *do* expect whoever send
this stuff to Linus to mention the necessary fixes to him.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From robherring2 at gmail.com  Thu May  2 21:51:43 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 02 May 2013 20:51:43 -0500
Subject: [PATCH v10 0/2] (arm-soc for v3.10) arm: introduce psci_smp_ops
In-Reply-To: <CAOesGMgtwb5z-LcJNf7Jtnz92T7u3Z9_uzBxYCaD1ahwYa514A@mail.gmail.com>
References: <alpine.DEB.2.02.1304301707290.5398@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305021938170.5398@kaball.uk.xensource.com>
 <20130502184801.GF14496@n2100.arm.linux.org.uk>
 <201305022103.58445.arnd@arndb.de>
 <CAOesGMgtwb5z-LcJNf7Jtnz92T7u3Z9_uzBxYCaD1ahwYa514A@mail.gmail.com>
Message-ID: <5183182F.1050408@gmail.com>

On 05/02/2013 03:34 PM, Olof Johansson wrote:
> Hi,
> 
> On Thu, May 2, 2013 at 12:03 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>> On Thursday 02 May 2013, Russell King - ARM Linux wrote:
>>> The only issue that there is is where we are in the development cycle
>>> (almost mid merge window), and I've yet to push anything to Linus thanks
>>> to late discovery of various messups in other chunks of code submitted
>>> via my tree - I'm starting to drop stuff from my tree in the hope that
>>> I'll get back to something that's going to be suitable for mainline.
>>>
>>> I really don't want to go pulling anything else at the moment in the
>>> hope of getting what I currently have out the door.
>>>
>>> And in any case, we shouldn't be adding any new code to our trees at
>>> this point in time.
>>
>> Agreed. I would have like to see the patches in 3.10, but the timing
>> didn't work out.
>>
>> Stefano, I'm sure we can queue it up early for 3.11 if you send them
>> again after the merge window. Sorry you had to go through 10 versions
>> and not getting it merged in time in the end.
> 
> Yeah, sorry for being quiet on this; I've seen the patches go by but
> also haven't looked closely at them since timing was pointing more
> towards 3.11 material. 3.10 is already a very busy release for us on
> arm-soc.
> 
> If there's SoC code that needs this as a base, we can do a shared
> branch with Russell. That has worked well in the past -- he merges it
> but we bring in a copy of the topic in our tree.

Yes, there will be. I've got highbank about ready to go.

Rob



From shawn.guo at linaro.org  Thu May  2 22:16:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 10:16:51 +0800
Subject: [PATCH, RFC 04/22] staging/drm: imx: add missing dependencies
In-Reply-To: <1367507786-505303-5-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-5-git-send-email-arnd@arndb.de>
Message-ID: <20130503021650.GL3442@S2101-09.ap.freescale.net>

On Thu, May 02, 2013 at 05:16:08PM +0200, Arnd Bergmann wrote:
> The imx DRM driver needs a couple of extra Kconfig dependencies
> to avoid random build failures:
> 
> drivers/staging/imx-drm/ipuv3-crtc.c:448:
>  undefined reference to `ipu_idmac_put'
>  drivers/staging/imx-drm/ipuv3-crtc.c:450: undefined reference to
>  `ipu_dmfc_put' drivers/staging/imx-drm/ipuv3-crtc.c:452:
>  undefined reference to `ipu_dp_put'
>  drivers/staging/imx-drm/ipuv3-crtc.c:454: undefined reference to
>  `ipu_di_put'
> drivers/built-in.o: In function `ipu_probe':
>  :(.text+0x4b4174): undefined reference to `device_reset'
> drivers/built-in.o: In function `imx_tve_probe':
>  drivers/staging/imx-drm/imx-tve.c:648: undefined reference to
>  `devm_regmap_init_mmio_clk'
> drivers/built-in.o: In function
>  `imx_pd_connector_get_modes':

>  drivers/staging/imx-drm/parallel-display.c:78: undefined
>  reference to `of_get_drm_display_mode'

There is a patch [1] from Marek fixing this one.

Shawn

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/233449

> 
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Philipp Zabel <p.zabel at pengutronix.de>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/staging/imx-drm/Kconfig | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/staging/imx-drm/Kconfig b/drivers/staging/imx-drm/Kconfig
> index 8c9e403..35ccda5 100644
> --- a/drivers/staging/imx-drm/Kconfig
> +++ b/drivers/staging/imx-drm/Kconfig
> @@ -1,6 +1,7 @@
>  config DRM_IMX
>  	tristate "DRM Support for Freescale i.MX"
>  	select DRM_KMS_HELPER
> +	select VIDEOMODE_HELPERS
>  	select DRM_GEM_CMA_HELPER
>  	select DRM_KMS_CMA_HELPER
>  	depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM)
> @@ -23,6 +24,7 @@ config DRM_IMX_PARALLEL_DISPLAY
>  config DRM_IMX_TVE
>  	tristate "Support for TV and VGA displays"
>  	depends on DRM_IMX
> +	select REGMAP_MMIO
>  	help
>  	  Choose this to enable the internal Television Encoder (TVe)
>  	  found on i.MX53 processors.
> @@ -30,6 +32,7 @@ config DRM_IMX_TVE
>  config DRM_IMX_IPUV3_CORE
>  	tristate "IPUv3 core support"
>  	depends on DRM_IMX
> +	depends on RESET_CONTROLLER
>  	help
>  	  Choose this if you have a i.MX5/6 system and want
>  	  to use the IPU. This option only enables IPU base
> @@ -38,5 +41,6 @@ config DRM_IMX_IPUV3_CORE
>  config DRM_IMX_IPUV3
>  	tristate "DRM Support for i.MX IPUv3"
>  	depends on DRM_IMX
> +	depends on DRM_IMX_IPUV3_CORE
>  	help
>  	  Choose this if you have a i.MX5 or i.MX6 processor.
> -- 
> 1.8.1.2
> 



From shawn.guo at linaro.org  Thu May  2 22:33:55 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 10:33:55 +0800
Subject: [PATCH, RFC 20/22] media: coda: select GENERIC_ALLOCATOR
In-Reply-To: <201305022153.19518.arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-21-git-send-email-arnd@arndb.de>
 <1367515255.447627800@f375.mail.ru>
 <201305022153.19518.arnd@arndb.de>
Message-ID: <20130503023353.GM3442@S2101-09.ap.freescale.net>

On Thu, May 02, 2013 at 09:53:19PM +0200, Arnd Bergmann wrote:
> Unfortunately, linux-next as of today is still broken. Shawn, did I
> miss a pull request from you?

No, I haven't sent you a pull request for that.  I have queued it for
3.10-rc but am still waiting for a stable base (3.10-rc1 where
coda and genalloc changes should be merged together) to send it out.

Shawn



From jaswinder.singh at linaro.org  Thu May  2 22:37:54 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Fri, 3 May 2013 08:07:54 +0530
Subject: [GIT PULL] mailbox driver framework for v3.10 merge window
In-Reply-To: <5182E403.1030808@ti.com>
References: <37C860A02101E749A747FA2D3C1E3C504A1971@DLEE11.ent.ti.com>
 <201304091255.03020.arnd@arndb.de>
 <CAJe_Zhf5QwQQU5aVtNhbDT3EK9Dof-ZK_boP9WaNghqO8xY7iA@mail.gmail.com>
 <5182E403.1030808@ti.com>
Message-ID: <CAJe_ZhfA=eqihefgtYGmLt03sNV6arme9t1YgzTFoC8nB6SNkQ@mail.gmail.com>

On 3 May 2013 03:39, Suman Anna <s-anna at ti.com> wrote:
> Hi Arnd,
>
> On 04/28/2013 11:07 PM, Jassi Brar wrote:
>>
>> Not to mean only talk and no do, I prepared another proposal that
>> addressed all the concerns shared so far in the RFC
>> http://www.spinics.net/lists/kernel/msg1523873.html (its not ready for
>> primetime yet)  And also converted the PL320 driver to the new API,
>> unlike the pulled patchset which leaves that out in the cold.
>> http://www.spinics.net/lists/kernel/msg1523874.html
>
> Yes, the current code is mainly interrupt-driven and supports only
> non-atomic context. We have a need to support atomic contexts and ipc
> controllers that do not have interrupt-based triggering.
>
Supporting poll and client driven TX and atomic context is going to
need big chunks of changes which we can avoid by doing them already.
Plus a bottleneck with PL320, as Mark pointed out they can't afford
any bigger latency, which will come from RX via notifier path.

> As Jassi
> pointed out, the RFC is not ready yet and there are still some
> contention points that needs to be sorted out (especially to maintain
> OMAP mailbox functionality).
>
Apart from a few checkpatch fixes, a missing timer delete call and
some testing with dummy client and controller drivers for various
usecases, it's ready from my side. It worked at least as good as your
API in our internal testing.

Please do let me know which OMAP functionality are you worried about,
I believe it could all still be done above this api.

>>
>> Now, we could either call it (effectively the TI's framework with
>> quirks for STE) as the "Common API" and then dismantle and convert it
>> patch by patch (authors and I seem to agree many things need to be
>> changed and implemented).
>>   OR we do it reasonably right the first time even if that means yet
>> another release. IMHO we should go for slow but steady thing.
>
> I think it is your call here, either of the above approaches would
> definitely involve some rework on the framework as well as both the OMAP
> & ST mailboxes.

I am interested to know what changes do you anticipate in my proposed
API. Not to mean it's perfect, but I thought I provided for all
practical use-cases.

Yes, TI and STE would need re-work, but then as of now they are their
own APIs upstream. And even with your proposal they would still need
to be changed if we are to implement the desired features. What about
PL320?

Thanks.


From shawn.guo at linaro.org  Thu May  2 22:40:47 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 10:40:47 +0800
Subject: [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform
 and development board support This Vybird MVF600 family is a heterogeneous
 dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This
 SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower
 development board.
In-Reply-To: <1367480285-26159-1-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
Message-ID: <20130503024046.GN3442@S2101-09.ap.freescale.net>

I don't know how it gets wrong, but the Subject line apparently contains
some message that should be put in the email body. 

Shawn

On Thu, May 02, 2013 at 03:38:03PM +0800, Jingchang Lu wrote:
> Documentation/devicetree/bindings/clock/mvf600-clock.txt | 180 ++++++++
> arch/arm/boot/dts/Makefile                               |   3 +-
> arch/arm/boot/dts/mvf600-pinfunc.h                       | 816 +++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/mvf600-twr.dts                         |  80 ++++
> arch/arm/boot/dts/mvf600.dtsi                            | 426 ++++++++++++++++++
> arch/arm/mach-imx/Kconfig                                |  15 +
> arch/arm/mach-imx/Makefile                               |   3 +
> arch/arm/mach-imx/clk-mvf.c                              | 406 +++++++++++++++++
> arch/arm/mach-imx/common.h                               |   1 +
> arch/arm/mach-imx/mach-mvf600.c                          | 118 +++++
> arch/arm/mach-imx/pit.c                                  | 244 +++++++++++
> 11 files changed, 2291 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
> create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
> create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
> create mode 100644 arch/arm/boot/dts/mvf600.dtsi
> create mode 100644 arch/arm/mach-imx/clk-mvf.c
> create mode 100644 arch/arm/mach-imx/mach-mvf600.c
> create mode 100644 arch/arm/mach-imx/pit.c
> 



From shawn.guo at linaro.org  Thu May  2 22:59:39 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 10:59:39 +0800
Subject: [PATCH] ARM: imx: fix typo in gpu3d_shader_sels
Message-ID: <1367549979-31291-1-git-send-email-shawn.guo@linaro.org>

There is no clock pll2_pfd9_720m.  Instead it should be pll3_pfd0_720m.
Fix the typo in gpu3d_shader_sels.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/clk-imx6q.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f2e1c62..dda9a2b 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -186,7 +186,7 @@ static const char *audio_sels[]	= { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd
 static const char *gpu_axi_sels[]	= { "axi", "ahb", };
 static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
 static const char *gpu3d_core_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
-static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
+static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
 static const char *ipu_sels[]		= { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
 static const char *ldb_di_sels[]	= { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
 static const char *ipu_di_pre_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 23:49:52 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 11:49:52 +0800
Subject: [PATCH 2/5] ARM: imx: enable low-level debug support for imx6sl
In-Reply-To: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1367552995-31777-3-git-send-email-shawn.guo@linaro.org>

Enable low-level debug support for i.MX6 SoloLite by adding the debug
port definitions for the SoC.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/Kconfig.debug            |   13 +++++++++++--
 arch/arm/include/debug/imx-uart.h |   10 ++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 24aeef7..b025103 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -240,6 +240,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on i.MX6Q/DL.
 
+	config DEBUG_IMX6SL_UART
+		bool "i.MX6SL Debug UART"
+		depends on SOC_IMX6SL
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on i.MX6SL.
+
 	config DEBUG_MMP_UART2
 		bool "Kernel low-level debugging message via MMP UART2"
 		depends on ARCH_MMP
@@ -493,7 +500,8 @@ config DEBUG_IMX_UART_PORT
 						DEBUG_IMX35_UART || \
 						DEBUG_IMX51_UART || \
 						DEBUG_IMX53_UART || \
-						DEBUG_IMX6Q_UART
+						DEBUG_IMX6Q_UART || \
+						DEBUG_IMX6SL_UART
 	default 1
 	depends on ARCH_MXC
 	help
@@ -588,7 +596,8 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_IMX35_UART || \
 				 DEBUG_IMX51_UART || \
 				 DEBUG_IMX53_UART ||\
-				 DEBUG_IMX6Q_UART
+				 DEBUG_IMX6Q_UART || \
+				 DEBUG_IMX6SL_UART
 	default "debug/highbank.S" if DEBUG_HIGHBANK_UART
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
 	default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e3..29da84e 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
 #define IMX6Q_UART_BASE_ADDR(n)	IMX6Q_UART##n##_BASE_ADDR
 #define IMX6Q_UART_BASE(n)	IMX6Q_UART_BASE_ADDR(n)
 
+#define IMX6SL_UART1_BASE_ADDR	0x02020000
+#define IMX6SL_UART2_BASE_ADDR	0x02024000
+#define IMX6SL_UART3_BASE_ADDR	0x02034000
+#define IMX6SL_UART4_BASE_ADDR	0x02038000
+#define IMX6SL_UART5_BASE_ADDR	0x02018000
+#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
+#define IMX6SL_UART_BASE(n)	IMX6SL_UART_BASE_ADDR(n)
+
 #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
 
 #ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
 #define UART_PADDR	IMX_DEBUG_UART_BASE(IMX53)
 #elif defined(CONFIG_DEBUG_IMX6Q_UART)
 #define UART_PADDR	IMX_DEBUG_UART_BASE(IMX6Q)
+#elif defined(CONFIG_DEBUG_IMX6SL_UART)
+#define UART_PADDR	IMX_DEBUG_UART_BASE(IMX6SL)
 #endif
 
 #endif /* __DEBUG_IMX_UART_H */
-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 23:49:53 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 11:49:53 +0800
Subject: [PATCH 3/5] ARM: imx: add initial support for imx6sl
In-Reply-To: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1367552995-31777-4-git-send-email-shawn.guo@linaro.org>

Add initial support for i.MX6 SoloLite.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig       |   19 ++++++++++++++++
 arch/arm/mach-imx/Makefile      |    1 +
 arch/arm/mach-imx/common.h      |    1 +
 arch/arm/mach-imx/mach-imx6sl.c |   48 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx6sl.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c132f6f..8454221 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -820,6 +820,25 @@ config SOC_IMX6Q
 	help
 	  This enables support for Freescale i.MX6 Quad processor.
 
+config SOC_IMX6SL
+	bool "i.MX6 SoloLite support"
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_775420
+	select ARM_GIC
+	select CPU_V7
+	select HAVE_IMX_ANATOP
+	select HAVE_IMX_GPC
+	select HAVE_IMX_MMDC
+	select HAVE_IMX_SRC
+	select PINCTRL
+	select PINCTRL_IMX6SL
+	select PL310_ERRATA_588369 if CACHE_PL310
+	select PL310_ERRATA_727915 if CACHE_PL310
+	select PL310_ERRATA_769419 if CACHE_PL310
+
+	help
+	  This enables support for Freescale i.MX6 SoloLite processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b16eb39..d6f99e1 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -99,6 +99,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4cba7db..efae60c 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,6 +68,7 @@ extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
+extern int imx6sl_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
new file mode 100644
index 0000000..b044134
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+
+static void __init imx6sl_init_machine(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init imx6sl_init_irq(void)
+{
+	l2x0_of_init(0, ~0UL);
+	imx_src_init();
+	imx_gpc_init();
+	irqchip_init();
+}
+
+static void __init imx6sl_timer_init(void)
+{
+	imx6sl_clocks_init();
+}
+
+static const char *imx6sl_dt_compat[] __initdata = {
+	"fsl,imx6sl",
+	NULL,
+};
+
+DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
+	.map_io		= debug_ll_io_init,
+	.init_irq	= imx6sl_init_irq,
+	.init_time	= imx6sl_timer_init,
+	.init_machine	= imx6sl_init_machine,
+	.dt_compat	= imx6sl_dt_compat,
+MACHINE_END
-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 23:49:55 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 11:49:55 +0800
Subject: [PATCH 5/5] ARM: dts: imx6sl: add initial imx6sl-evk support
In-Reply-To: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1367552995-31777-6-git-send-email-shawn.guo@linaro.org>

Add initial imx6sl-evk board support with uart, usdhc and fec enabled.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/Makefile       |    3 +-
 arch/arm/boot/dts/imx6sl-evk.dts |   74 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/imx6sl-evk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2498cba..73794c3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -106,7 +106,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6q-sabreauto.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
-	imx6q-sbc6x.dtb
+	imx6q-sbc6x.dtb \
+	imx6sl-evk.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx23-olinuxino.dtb \
 	imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
new file mode 100644
index 0000000..2886a59
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sl.dtsi"
+
+/ {
+	model = "Freescale i.MX6 SoloLite EVK Board";
+	compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec_1>;
+	phy-mode = "rmii";
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	hog {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
+				MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
+				MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
+				MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
+				MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+			>;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1_1>;
+	bus-width = <8>;
+	cd-gpios = <&gpio4 7 0>;
+	wp-gpios = <&gpio4 6 0>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_1>;
+	cd-gpios = <&gpio5 0 0>;
+	wp-gpios = <&gpio4 29 0>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	cd-gpios = <&gpio3 22 0>;
+	status = "okay";
+};
-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 23:49:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 11:49:51 +0800
Subject: [PATCH 1/5] ARM: imx: add clock support for imx6sl
In-Reply-To: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1367552995-31777-2-git-send-email-shawn.guo@linaro.org>

Add clock support for i.MX6 SoloLite.  It uses the dtc marco support to
define all clock IDs in imx6sl-clock.h, which will be included by both
clock driver and device tree sources, so that the data will stay sync
all the time between kernel and DT.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx6sl-clock.txt     |   10 +
 arch/arm/mach-imx/clk-imx6sl.c                     |  270 ++++++++++++++++++++
 include/dt-bindings/clock/imx6sl-clock.h           |  148 +++++++++++
 3 files changed, 428 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/imx6sl-clock.txt
 create mode 100644 arch/arm/mach-imx/clk-imx6sl.c
 create mode 100644 include/dt-bindings/clock/imx6sl-clock.h

diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
new file mode 100644
index 0000000..15e40bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
@@ -0,0 +1,10 @@
+* Clock bindings for Freescale i.MX6 SoloLite
+
+Required properties:
+- compatible: Should be "fsl,imx6sl-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6sl-clock.h
+for the full list of i.MX6 SoloLite clock IDs.
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
new file mode 100644
index 0000000..94e5d12
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <dt-bindings/clock/imx6sl-clock.h>
+
+#include "clk.h"
+#include "common.h"
+
+static const char * const step_sels[]		= { "osc", "pll2_pfd2", };
+static const char * const pll1_sw_sels[]	= { "pll1_sys", "step", };
+static const char * const ocram_alt_sels[]	= { "pll2_pfd2", "pll3_pfd1", };
+static const char * const ocram_sels[]		= { "periph", "ocram_alt_sels", };
+static const char * const pre_periph_sels[]	= { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char * const periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char * const periph2_clk2_sels[]	= { "pll3_usb_otg", "pll2_bus", };
+static const char * const periph_sels[]		= { "pre_periph_sel", "periph_clk2_podf", };
+static const char * const periph2_sels[]	= { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char * const csi_lcdif_sels[]	= { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char * const usdhc_sels[]		= { "pll2_pfd2", "pll2_pfd0", };
+static const char * const ssi_sels[]		= { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
+static const char * const perclk_sels[]		= { "ipg", "osc", };
+static const char * const epdc_pxp_sels[]	= { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char * const gpu2d_ovg_sels[]	= { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char * const gpu2d_sels[]		= { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char * const lcdif_pix_sels[]	= { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char * const epdc_pix_sels[]	= { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char * const audio_sels[]		= { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char * const ecspi_sels[]		= { "pll3_60m", "osc", };
+static const char * const uart_sels[]		= { "pll3_80m", "osc", };
+
+static struct clk_div_table clk_enet_ref_table[] = {
+	{ .val = 0, .div = 20, },
+	{ .val = 1, .div = 10, },
+	{ .val = 2, .div = 5, },
+	{ .val = 3, .div = 4, },
+	{ }
+};
+
+static struct clk_div_table post_div_table[] = {
+	{ .val = 2, .div = 1, },
+	{ .val = 1, .div = 2, },
+	{ .val = 0, .div = 4, },
+	{ }
+};
+
+static struct clk_div_table video_div_table[] = {
+	{ .val = 0, .div = 1, },
+	{ .val = 1, .div = 2, },
+	{ .val = 2, .div = 1, },
+	{ .val = 3, .div = 4, },
+	{ }
+};
+
+static struct clk *clks[IMX6SL_CLK_CLK_END];
+static struct clk_onecell_data clk_data;
+
+int __init imx6sl_clocks_init(void)
+{
+	struct device_node *np;
+	void __iomem *base;
+	int irq;
+	int i;
+
+	of_clk_init(NULL);
+
+	clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+	clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+	clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+
+	/*                                             type               name            parent  base         div_mask */
+	clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,	  "pll1_sys",	   "osc", base,        0x7f);
+	clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",	   "osc", base + 0x30, 0x1);
+	clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,	  "pll3_usb_otg",  "osc", base + 0x10, 0x3);
+	clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,	  "pll4_audio",	   "osc", base + 0x70, 0x7f);
+	clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,	  "pll5_video",	   "osc", base + 0xa0, 0x7f);
+	clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,	  "pll6_enet",	   "osc", base + 0xe0, 0x3);
+	clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
+
+	/*
+	 * usbphy1 and usbphy2 are implemented as dummy gates using reserve
+	 * bit 20.  They are used by phy driver to keep the refcount of
+	 * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
+	 * turned on during boot, and software will not need to control it
+	 * anymore after that.
+	 */
+	clks[IMX6SL_CLK_USBPHY1]      = imx_clk_gate("usbphy1",      "pll3_usb_otg",  base + 0x10, 20);
+	clks[IMX6SL_CLK_USBPHY2]      = imx_clk_gate("usbphy2",      "pll7_usb_host", base + 0x20, 20);
+	clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy",         base + 0x10, 6);
+	clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy",         base + 0x20, 6);
+
+	/*                                                           dev   name              parent_name      flags                reg        shift width div: flags, div_table lock */
+	clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
+	clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
+	clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
+	clks[IMX6SL_CLK_ENET_REF]       = clk_register_divider_table(NULL, "enet_ref",       "pll6_enet",     0,                   base + 0xe0,  0,  2,   0, clk_enet_ref_table, &imx_ccm_lock);
+
+	/*                                       name         parent_name     reg           idx */
+	clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus",     base + 0x100, 0);
+	clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus",     base + 0x100, 1);
+	clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus",     base + 0x100, 2);
+	clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0,  0);
+	clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0,  1);
+	clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0,  2);
+	clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0,  3);
+
+	/*                                                name         parent_name     mult div */
+	clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2",      1, 2);
+	clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+	clks[IMX6SL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+	clks[IMX6SL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ccm");
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+
+	/*                                              name                reg       shift width parent_names     num_parents */
+	clks[IMX6SL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+	clks[IMX6SL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+	clks[IMX6SL_CLK_OCRAM_ALT_SEL]    = imx_clk_mux("ocram_alt_sel",    base + 0x14, 7,  1, ocram_alt_sels,    ARRAY_SIZE(ocram_alt_sels));
+	clks[IMX6SL_CLK_OCRAM_SEL]        = imx_clk_mux("ocram_sel",        base + 0x14, 6,  1, ocram_sels,        ARRAY_SIZE(ocram_sels));
+	clks[IMX6SL_CLK_PRE_PERIPH2_SEL]  = imx_clk_mux("pre_periph2_sel",  base + 0x18, 21, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+	clks[IMX6SL_CLK_PRE_PERIPH_SEL]   = imx_clk_mux("pre_periph_sel",   base + 0x18, 18, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+	clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+	clks[IMX6SL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+	clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+	clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+	clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+	clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+	clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+	clks[IMX6SL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+	clks[IMX6SL_CLK_SSI1_SEL]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+	clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+	clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+	clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",       base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels));
+	clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+	clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+	clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
+	clks[IMX6SL_CLK_GPU2D_SEL]        = imx_clk_mux("gpu2d_sel",        base + 0x18, 8,  2, gpu2d_sels,        ARRAY_SIZE(gpu2d_sels));
+	clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels));
+	clks[IMX6SL_CLK_EPDC_PIX_SEL]     = imx_clk_mux("epdc_pix_sel",     base + 0x38, 15, 3, epdc_pix_sels,     ARRAY_SIZE(epdc_pix_sels));
+	clks[IMX6SL_CLK_SPDIF0_SEL]       = imx_clk_mux("spdif0_sel",       base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+	clks[IMX6SL_CLK_SPDIF1_SEL]       = imx_clk_mux("spdif1_sel",       base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+	clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+	clks[IMX6SL_CLK_ECSPI_SEL]        = imx_clk_mux("ecspi_sel",        base + 0x38, 18, 1, ecspi_sels,        ARRAY_SIZE(ecspi_sels));
+	clks[IMX6SL_CLK_UART_SEL]         = imx_clk_mux("uart_sel",         base + 0x24, 6,  1, uart_sels,         ARRAY_SIZE(uart_sels));
+
+	/*                                          name       reg        shift width busy: reg, shift parent_names  num_parents */
+	clks[IMX6SL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+	clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+	/*                                                   name                 parent_name          reg       shift width */
+	clks[IMX6SL_CLK_OCRAM_PODF]        = imx_clk_divider("ocram_podf",        "ocram_sel",         base + 0x14, 16, 3);
+	clks[IMX6SL_CLK_PERIPH_CLK2_PODF]  = imx_clk_divider("periph_clk2_podf",  "periph_clk2_sel",   base + 0x14, 27, 3);
+	clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel",  base + 0x14, 0,  3);
+	clks[IMX6SL_CLK_IPG]               = imx_clk_divider("ipg",               "ahb",               base + 0x14, 8,  2);
+	clks[IMX6SL_CLK_CSI_PODF]          = imx_clk_divider("csi_podf",          "csi_sel",           base + 0x3c, 11, 3);
+	clks[IMX6SL_CLK_LCDIF_AXI_PODF]    = imx_clk_divider("lcdif_axi_podf",    "lcdif_axi_sel",     base + 0x3c, 16, 3);
+	clks[IMX6SL_CLK_USDHC1_PODF]       = imx_clk_divider("usdhc1_podf",       "usdhc1_sel",        base + 0x24, 11, 3);
+	clks[IMX6SL_CLK_USDHC2_PODF]       = imx_clk_divider("usdhc2_podf",       "usdhc2_sel",        base + 0x24, 16, 3);
+	clks[IMX6SL_CLK_USDHC3_PODF]       = imx_clk_divider("usdhc3_podf",       "usdhc3_sel",        base + 0x24, 19, 3);
+	clks[IMX6SL_CLK_USDHC4_PODF]       = imx_clk_divider("usdhc4_podf",       "usdhc4_sel",        base + 0x24, 22, 3);
+	clks[IMX6SL_CLK_SSI1_PRED]         = imx_clk_divider("ssi1_pred",         "ssi1_sel",          base + 0x28, 6,  3);
+	clks[IMX6SL_CLK_SSI1_PODF]         = imx_clk_divider("ssi1_podf",         "ssi1_pred",         base + 0x28, 0,  6);
+	clks[IMX6SL_CLK_SSI2_PRED]         = imx_clk_divider("ssi2_pred",         "ssi2_sel",          base + 0x2c, 6,  3);
+	clks[IMX6SL_CLK_SSI2_PODF]         = imx_clk_divider("ssi2_podf",         "ssi2_pred",         base + 0x2c, 0,  6);
+	clks[IMX6SL_CLK_SSI3_PRED]         = imx_clk_divider("ssi3_pred",         "ssi3_sel",          base + 0x28, 22, 3);
+	clks[IMX6SL_CLK_SSI3_PODF]         = imx_clk_divider("ssi3_podf",         "ssi3_pred",         base + 0x28, 16, 6);
+	clks[IMX6SL_CLK_PERCLK]            = imx_clk_divider("perclk",            "perclk_sel",        base + 0x1c, 0,  6);
+	clks[IMX6SL_CLK_PXP_AXI_PODF]      = imx_clk_divider("pxp_axi_podf",      "pxp_axi_sel",       base + 0x34, 3,  3);
+	clks[IMX6SL_CLK_EPDC_AXI_PODF]     = imx_clk_divider("epdc_axi_podf",     "epdc_axi_sel",      base + 0x34, 12, 3);
+	clks[IMX6SL_CLK_GPU2D_OVG_PODF]    = imx_clk_divider("gpu2d_ovg_podf",    "gpu2d_ovg_sel",     base + 0x18, 26, 3);
+	clks[IMX6SL_CLK_GPU2D_PODF]        = imx_clk_divider("gpu2d_podf",        "gpu2d_sel",         base + 0x18, 29, 3);
+	clks[IMX6SL_CLK_LCDIF_PIX_PRED]    = imx_clk_divider("lcdif_pix_pred",    "lcdif_pix_sel",     base + 0x38, 3,  3);
+	clks[IMX6SL_CLK_EPDC_PIX_PRED]     = imx_clk_divider("epdc_pix_pred",     "epdc_pix_sel",      base + 0x38, 12, 3);
+	clks[IMX6SL_CLK_LCDIF_PIX_PODF]    = imx_clk_divider("lcdif_pix_podf",    "lcdif_pix_pred",    base + 0x1c, 20, 3);
+	clks[IMX6SL_CLK_EPDC_PIX_PODF]     = imx_clk_divider("epdc_pix_podf",     "epdc_pix_pred",     base + 0x18, 23, 3);
+	clks[IMX6SL_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred",       "spdif0_sel",        base + 0x30, 25, 3);
+	clks[IMX6SL_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf",       "spdif0_pred",       base + 0x30, 22, 3);
+	clks[IMX6SL_CLK_SPDIF1_PRED]       = imx_clk_divider("spdif1_pred",       "spdif1_sel",        base + 0x30, 12, 3);
+	clks[IMX6SL_CLK_SPDIF1_PODF]       = imx_clk_divider("spdif1_podf",       "spdif1_pred",       base + 0x30, 9,  3);
+	clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel",  base + 0x28, 9,  3);
+	clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
+	clks[IMX6SL_CLK_ECSPI_ROOT]        = imx_clk_divider("ecspi_root",        "ecspi_sel",         base + 0x38, 19, 6);
+	clks[IMX6SL_CLK_UART_ROOT]         = imx_clk_divider("uart_root",         "uart_sel",          base + 0x24, 0,  6);
+
+	/*                                                name         parent_name reg       shift width busy: reg, shift */
+	clks[IMX6SL_CLK_AHB]       = imx_clk_busy_divider("ahb",       "periph",  base + 0x14, 10, 3,    base + 0x48, 1);
+	clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc",      "periph2", base + 0x14, 3,  3,    base + 0x48, 2);
+	clks[IMX6SL_CLK_ARM]       = imx_clk_busy_divider("arm",       "pll1_sw", base + 0x10, 0,  3,    base + 0x48, 16);
+
+	/*                                            name            parent_name          reg         shift */
+	clks[IMX6SL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",       "ecspi_root",        base + 0x6c, 0);
+	clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
+	clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
+	clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
+	clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
+	clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
+	clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
+	clks[IMX6SL_CLK_GPT]          = imx_clk_gate2("gpt",          "perclk",            base + 0x6c, 20);
+	clks[IMX6SL_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",   "perclk",            base + 0x6c, 22);
+	clks[IMX6SL_CLK_GPU2D_OVG]    = imx_clk_gate2("gpu2d_ovg",    "gpu2d_ovg_podf",    base + 0x6c, 26);
+	clks[IMX6SL_CLK_I2C1]         = imx_clk_gate2("i2c1",         "perclk",            base + 0x70, 6);
+	clks[IMX6SL_CLK_I2C2]         = imx_clk_gate2("i2c2",         "perclk",            base + 0x70, 8);
+	clks[IMX6SL_CLK_I2C3]         = imx_clk_gate2("i2c3",         "perclk",            base + 0x70, 10);
+	clks[IMX6SL_CLK_OCOTP]        = imx_clk_gate2("ocotp",        "ipg",               base + 0x70, 12);
+	clks[IMX6SL_CLK_CSI]          = imx_clk_gate2("csi",          "csi_podf",          base + 0x74, 0);
+	clks[IMX6SL_CLK_PXP_AXI]      = imx_clk_gate2("pxp_axi",      "pxp_axi_podf",      base + 0x74, 2);
+	clks[IMX6SL_CLK_EPDC_AXI]     = imx_clk_gate2("epdc_axi",     "epdc_axi_podf",     base + 0x74, 4);
+	clks[IMX6SL_CLK_LCDIF_AXI]    = imx_clk_gate2("lcdif_axi",    "lcdif_axi_podf",    base + 0x74, 6);
+	clks[IMX6SL_CLK_LCDIF_PIX]    = imx_clk_gate2("lcdif_pix",    "lcdif_pix_podf",    base + 0x74, 8);
+	clks[IMX6SL_CLK_EPDC_PIX]     = imx_clk_gate2("epdc_pix",     "epdc_pix_podf",     base + 0x74, 10);
+	clks[IMX6SL_CLK_OCRAM]        = imx_clk_gate2("ocram",        "ocram_podf",        base + 0x74, 28);
+	clks[IMX6SL_CLK_PWM1]         = imx_clk_gate2("pwm1",         "perclk",            base + 0x78, 16);
+	clks[IMX6SL_CLK_PWM2]         = imx_clk_gate2("pwm2",         "perclk",            base + 0x78, 18);
+	clks[IMX6SL_CLK_PWM3]         = imx_clk_gate2("pwm3",         "perclk",            base + 0x78, 20);
+	clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
+	clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
+	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+	clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2("ssi1",         "ssi1_podf",         base + 0x7c, 18);
+	clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2("ssi2",         "ssi2_podf",         base + 0x7c, 20);
+	clks[IMX6SL_CLK_SSI3]         = imx_clk_gate2("ssi3",         "ssi3_podf",         base + 0x7c, 22);
+	clks[IMX6SL_CLK_UART]         = imx_clk_gate2("uart",         "ipg",               base + 0x7c, 24);
+	clks[IMX6SL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",  "uart_root",         base + 0x7c, 26);
+	clks[IMX6SL_CLK_USBOH3]       = imx_clk_gate2("usboh3",       "ipg",               base + 0x80, 0);
+	clks[IMX6SL_CLK_USDHC1]       = imx_clk_gate2("usdhc1",       "usdhc1_podf",       base + 0x80, 2);
+	clks[IMX6SL_CLK_USDHC2]       = imx_clk_gate2("usdhc2",       "usdhc2_podf",       base + 0x80, 4);
+	clks[IMX6SL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",       "usdhc3_podf",       base + 0x80, 6);
+	clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++)
+		if (IS_ERR(clks[i]))
+			pr_err("i.MX6SL clk %d: register failed with %ld\n",
+				i, PTR_ERR(clks[i]));
+
+	clk_data.clks = clks;
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
+	clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+
+	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+	}
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+	irq = irq_of_parse_and_map(np, 0);
+	mxc_timer_init(base, irq);
+
+	return 0;
+}
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 0000000..7fcdf90
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY		0
+#define IMX6SL_CLK_CKIL			1
+#define IMX6SL_CLK_OSC			2
+#define IMX6SL_CLK_PLL1_SYS		3
+#define IMX6SL_CLK_PLL2_BUS		4
+#define IMX6SL_CLK_PLL3_USB_OTG		5
+#define IMX6SL_CLK_PLL4_AUDIO		6
+#define IMX6SL_CLK_PLL5_VIDEO		7
+#define IMX6SL_CLK_PLL6_ENET		8
+#define IMX6SL_CLK_PLL7_USB_HOST	9
+#define IMX6SL_CLK_USBPHY1		10
+#define IMX6SL_CLK_USBPHY2		11
+#define IMX6SL_CLK_USBPHY1_GATE		12
+#define IMX6SL_CLK_USBPHY2_GATE		13
+#define IMX6SL_CLK_PLL4_POST_DIV	14
+#define IMX6SL_CLK_PLL5_POST_DIV	15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV	16
+#define IMX6SL_CLK_ENET_REF		17
+#define IMX6SL_CLK_PLL2_PFD0		18
+#define IMX6SL_CLK_PLL2_PFD1		19
+#define IMX6SL_CLK_PLL2_PFD2		20
+#define IMX6SL_CLK_PLL3_PFD0		21
+#define IMX6SL_CLK_PLL3_PFD1		22
+#define IMX6SL_CLK_PLL3_PFD2		23
+#define IMX6SL_CLK_PLL3_PFD3		24
+#define IMX6SL_CLK_PLL2_198M		25
+#define IMX6SL_CLK_PLL3_120M		26
+#define IMX6SL_CLK_PLL3_80M		27
+#define IMX6SL_CLK_PLL3_60M		28
+#define IMX6SL_CLK_STEP			29
+#define IMX6SL_CLK_PLL1_SW		30
+#define IMX6SL_CLK_OCRAM_ALT_SEL	31
+#define IMX6SL_CLK_OCRAM_SEL		32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL	33
+#define IMX6SL_CLK_PRE_PERIPH_SEL	34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL	35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL	36
+#define IMX6SL_CLK_CSI_SEL		37
+#define IMX6SL_CLK_LCDIF_AXI_SEL	38
+#define IMX6SL_CLK_USDHC1_SEL		39
+#define IMX6SL_CLK_USDHC2_SEL		40
+#define IMX6SL_CLK_USDHC3_SEL		41
+#define IMX6SL_CLK_USDHC4_SEL		42
+#define IMX6SL_CLK_SSI1_SEL		43
+#define IMX6SL_CLK_SSI2_SEL		44
+#define IMX6SL_CLK_SSI3_SEL		45
+#define IMX6SL_CLK_PERCLK_SEL		46
+#define IMX6SL_CLK_PXP_AXI_SEL		47
+#define IMX6SL_CLK_EPDC_AXI_SEL		48
+#define IMX6SL_CLK_GPU2D_OVG_SEL	49
+#define IMX6SL_CLK_GPU2D_SEL		50
+#define IMX6SL_CLK_LCDIF_PIX_SEL	51
+#define IMX6SL_CLK_EPDC_PIX_SEL		52
+#define IMX6SL_CLK_SPDIF0_SEL		53
+#define IMX6SL_CLK_SPDIF1_SEL		54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL	55
+#define IMX6SL_CLK_ECSPI_SEL		56
+#define IMX6SL_CLK_UART_SEL		57
+#define IMX6SL_CLK_PERIPH		58
+#define IMX6SL_CLK_PERIPH2		59
+#define IMX6SL_CLK_OCRAM_PODF		60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF	61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF	62
+#define IMX6SL_CLK_IPG			63
+#define IMX6SL_CLK_CSI_PODF		64
+#define IMX6SL_CLK_LCDIF_AXI_PODF	65
+#define IMX6SL_CLK_USDHC1_PODF		66
+#define IMX6SL_CLK_USDHC2_PODF		67
+#define IMX6SL_CLK_USDHC3_PODF		68
+#define IMX6SL_CLK_USDHC4_PODF		69
+#define IMX6SL_CLK_SSI1_PRED		70
+#define IMX6SL_CLK_SSI1_PODF		71
+#define IMX6SL_CLK_SSI2_PRED		72
+#define IMX6SL_CLK_SSI2_PODF		73
+#define IMX6SL_CLK_SSI3_PRED		74
+#define IMX6SL_CLK_SSI3_PODF		75
+#define IMX6SL_CLK_PERCLK		76
+#define IMX6SL_CLK_PXP_AXI_PODF		77
+#define IMX6SL_CLK_EPDC_AXI_PODF	78
+#define IMX6SL_CLK_GPU2D_OVG_PODF	79
+#define IMX6SL_CLK_GPU2D_PODF		80
+#define IMX6SL_CLK_LCDIF_PIX_PRED	81
+#define IMX6SL_CLK_EPDC_PIX_PRED	82
+#define IMX6SL_CLK_LCDIF_PIX_PODF	83
+#define IMX6SL_CLK_EPDC_PIX_PODF	84
+#define IMX6SL_CLK_SPDIF0_PRED		85
+#define IMX6SL_CLK_SPDIF0_PODF		86
+#define IMX6SL_CLK_SPDIF1_PRED		87
+#define IMX6SL_CLK_SPDIF1_PODF		88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED	89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF	90
+#define IMX6SL_CLK_ECSPI_ROOT		91
+#define IMX6SL_CLK_UART_ROOT		92
+#define IMX6SL_CLK_AHB			93
+#define IMX6SL_CLK_MMDC_ROOT		94
+#define IMX6SL_CLK_ARM			95
+#define IMX6SL_CLK_ECSPI1		96
+#define IMX6SL_CLK_ECSPI2		97
+#define IMX6SL_CLK_ECSPI3		98
+#define IMX6SL_CLK_ECSPI4		99
+#define IMX6SL_CLK_EPIT1		100
+#define IMX6SL_CLK_EPIT2		101
+#define IMX6SL_CLK_EXTERN_AUDIO		102
+#define IMX6SL_CLK_GPT			103
+#define IMX6SL_CLK_GPT_SERIAL		104
+#define IMX6SL_CLK_GPU2D_OVG		105
+#define IMX6SL_CLK_I2C1			106
+#define IMX6SL_CLK_I2C2			107
+#define IMX6SL_CLK_I2C3			108
+#define IMX6SL_CLK_OCOTP		109
+#define IMX6SL_CLK_CSI			110
+#define IMX6SL_CLK_PXP_AXI		111
+#define IMX6SL_CLK_EPDC_AXI		112
+#define IMX6SL_CLK_LCDIF_AXI		113
+#define IMX6SL_CLK_LCDIF_PIX		114
+#define IMX6SL_CLK_EPDC_PIX		115
+#define IMX6SL_CLK_OCRAM		116
+#define IMX6SL_CLK_PWM1			117
+#define IMX6SL_CLK_PWM2			118
+#define IMX6SL_CLK_PWM3			119
+#define IMX6SL_CLK_PWM4			120
+#define IMX6SL_CLK_SDMA			121
+#define IMX6SL_CLK_SPDIF		122
+#define IMX6SL_CLK_SSI1			123
+#define IMX6SL_CLK_SSI2			124
+#define IMX6SL_CLK_SSI3			125
+#define IMX6SL_CLK_UART			126
+#define IMX6SL_CLK_UART_SERIAL		127
+#define IMX6SL_CLK_USBOH3		128
+#define IMX6SL_CLK_USDHC1		129
+#define IMX6SL_CLK_USDHC2		130
+#define IMX6SL_CLK_USDHC3		131
+#define IMX6SL_CLK_USDHC4		132
+#define IMX6SL_CLK_CLK_END		133
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 23:49:50 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 11:49:50 +0800
Subject: [PATCH 0/5] Add initial i.MX6 SoloLite support
Message-ID: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>

The i.MX6 SoloLite (imx6sl) is another member of Freescale i.MX6 family
besides i.MX6 Quad/Dual (imx6q) and i.MX6 DualLite/Solo (imx6dl).
Unlike that there are much similarity and compatibility between imx6q
and imx6dl, imx6sl has significant differences on the integrated
multimedia IP blocks.  That's why we choose to add imx6dl support on top
of imx6q code base, but imx6sl support is added as a new SoC here.

Shawn Guo (5):
  ARM: imx: add clock support for imx6sl
  ARM: imx: enable low-level debug support for imx6sl
  ARM: imx: add initial support for imx6sl
  ARM: dts: add device tree source for imx6sl SoC
  ARM: dts: imx6sl: add initial imx6sl-evk support

 .../devicetree/bindings/clock/imx6sl-clock.txt     |   10 +
 arch/arm/Kconfig.debug                             |   13 +-
 arch/arm/boot/dts/Makefile                         |    3 +-
 arch/arm/boot/dts/imx6sl-evk.dts                   |   74 ++
 arch/arm/boot/dts/imx6sl.dtsi                      |  777 ++++++++++++++++++++
 arch/arm/include/debug/imx-uart.h                  |   10 +
 arch/arm/mach-imx/Kconfig                          |   19 +
 arch/arm/mach-imx/Makefile                         |    1 +
 arch/arm/mach-imx/clk-imx6sl.c                     |  270 +++++++
 arch/arm/mach-imx/common.h                         |    1 +
 arch/arm/mach-imx/mach-imx6sl.c                    |   48 ++
 include/dt-bindings/clock/imx6sl-clock.h           |  148 ++++
 12 files changed, 1371 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx6sl-clock.txt
 create mode 100644 arch/arm/boot/dts/imx6sl-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6sl.dtsi
 create mode 100644 arch/arm/mach-imx/clk-imx6sl.c
 create mode 100644 arch/arm/mach-imx/mach-imx6sl.c
 create mode 100644 include/dt-bindings/clock/imx6sl-clock.h

-- 
1.7.9.5




From shawn.guo at linaro.org  Thu May  2 23:49:54 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 11:49:54 +0800
Subject: [PATCH 4/5] ARM: dts: add device tree source for imx6sl SoC
In-Reply-To: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1367552995-31777-5-git-send-email-shawn.guo@linaro.org>

Add SoC level device tree source for imx6sl.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6sl.dtsi |  777 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 777 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6sl.dtsi

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
new file mode 100644
index 0000000..ab506e6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -0,0 +1,777 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include "imx6sl-pinfunc.h"
+#include <dt-bindings/clock/imx6sl-clock.h>
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	intc: interrupt-controller at 00a01000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-controller;
+		reg = <0x00a01000 0x1000>,
+		      <0x00a00100 0x100>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ckil {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		osc {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		L2: l2-cache at 00a02000 {
+			compatible = "arm,pl310-cache";
+			reg = <0x00a02000 0x1000>;
+			interrupts = <0 92 0x04>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		pmu {
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <0 94 0x04>;
+		};
+
+		aips1: aips-bus at 02000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x02000000 0x100000>;
+			ranges;
+
+			spba: spba-bus at 02000000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x02000000 0x40000>;
+				ranges;
+
+				spdif: spdif at 02004000 {
+					reg = <0x02004000 0x4000>;
+					interrupts = <0 52 0x04>;
+				};
+
+				ecspi1: ecspi at 02008000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02008000 0x4000>;
+					interrupts = <0 31 0x04>;
+					clocks = <&clks IMX6SL_CLK_ECSPI1>,
+						 <&clks IMX6SL_CLK_ECSPI1>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi2: ecspi at 0200c000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+					reg = <0x0200c000 0x4000>;
+					interrupts = <0 32 0x04>;
+					clocks = <&clks IMX6SL_CLK_ECSPI2>,
+						 <&clks IMX6SL_CLK_ECSPI2>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi3: ecspi at 02010000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02010000 0x4000>;
+					interrupts = <0 33 0x04>;
+					clocks = <&clks IMX6SL_CLK_ECSPI3>,
+						 <&clks IMX6SL_CLK_ECSPI3>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi4: ecspi at 02014000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02014000 0x4000>;
+					interrupts = <0 34 0x04>;
+					clocks = <&clks IMX6SL_CLK_ECSPI4>,
+						 <&clks IMX6SL_CLK_ECSPI4>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart5: serial at 02018000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+					reg = <0x02018000 0x4000>;
+					interrupts = <0 30 0x04>;
+					clocks = <&clks IMX6SL_CLK_UART>,
+						 <&clks IMX6SL_CLK_UART_SERIAL>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart1: serial at 02020000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+					reg = <0x02020000 0x4000>;
+					interrupts = <0 26 0x04>;
+					clocks = <&clks IMX6SL_CLK_UART>,
+						 <&clks IMX6SL_CLK_UART_SERIAL>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart2: serial at 02024000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+					reg = <0x02024000 0x4000>;
+					interrupts = <0 27 0x04>;
+					clocks = <&clks IMX6SL_CLK_UART>,
+						 <&clks IMX6SL_CLK_UART_SERIAL>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ssi1: ssi at 02028000 {
+					compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+					reg = <0x02028000 0x4000>;
+					interrupts = <0 46 0x04>;
+					clocks = <&clks IMX6SL_CLK_SSI1>;
+					fsl,fifo-depth = <15>;
+					status = "disabled";
+				};
+
+				ssi2: ssi at 0202c000 {
+					compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+					reg = <0x0202c000 0x4000>;
+					interrupts = <0 47 0x04>;
+					clocks = <&clks IMX6SL_CLK_SSI2>;
+					fsl,fifo-depth = <15>;
+					status = "disabled";
+				};
+
+				ssi3: ssi at 02030000 {
+					compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+					reg = <0x02030000 0x4000>;
+					interrupts = <0 48 0x04>;
+					clocks = <&clks IMX6SL_CLK_SSI3>;
+					fsl,fifo-depth = <15>;
+					status = "disabled";
+				};
+
+				uart3: serial at 02034000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+					reg = <0x02034000 0x4000>;
+					interrupts = <0 28 0x04>;
+					clocks = <&clks IMX6SL_CLK_UART>,
+						 <&clks IMX6SL_CLK_UART_SERIAL>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart4: serial at 02038000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+					reg = <0x02038000 0x4000>;
+					interrupts = <0 29 0x04>;
+					clocks = <&clks IMX6SL_CLK_UART>,
+						 <&clks IMX6SL_CLK_UART_SERIAL>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+			};
+
+			pwm1: pwm at 02080000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+				reg = <0x02080000 0x4000>;
+				interrupts = <0 83 0x04>;
+				clocks = <&clks IMX6SL_CLK_PWM1>,
+					 <&clks IMX6SL_CLK_PWM1>;
+				clock-names = "ipg", "per";
+			};
+
+			pwm2: pwm at 02084000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+				reg = <0x02084000 0x4000>;
+				interrupts = <0 84 0x04>;
+				clocks = <&clks IMX6SL_CLK_PWM2>,
+					 <&clks IMX6SL_CLK_PWM2>;
+				clock-names = "ipg", "per";
+			};
+
+			pwm3: pwm at 02088000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+				reg = <0x02088000 0x4000>;
+				interrupts = <0 85 0x04>;
+				clocks = <&clks IMX6SL_CLK_PWM3>,
+					 <&clks IMX6SL_CLK_PWM3>;
+				clock-names = "ipg", "per";
+			};
+
+			pwm4: pwm at 0208c000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+				reg = <0x0208c000 0x4000>;
+				interrupts = <0 86 0x04>;
+				clocks = <&clks IMX6SL_CLK_PWM4>,
+					 <&clks IMX6SL_CLK_PWM4>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt: gpt at 02098000 {
+				compatible = "fsl,imx6sl-gpt";
+				reg = <0x02098000 0x4000>;
+				interrupts = <0 55 0x04>;
+				clocks = <&clks IMX6SL_CLK_GPT>,
+					 <&clks IMX6SL_CLK_GPT_SERIAL>;
+				clock-names = "ipg", "per";
+			};
+
+			gpio1: gpio at 0209c000 {
+				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+				reg = <0x0209c000 0x4000>;
+				interrupts = <0 66 0x04 0 67 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio at 020a0000 {
+				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+				reg = <0x020a0000 0x4000>;
+				interrupts = <0 68 0x04 0 69 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio at 020a4000 {
+				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+				reg = <0x020a4000 0x4000>;
+				interrupts = <0 70 0x04 0 71 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio at 020a8000 {
+				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+				reg = <0x020a8000 0x4000>;
+				interrupts = <0 72 0x04 0 73 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio at 020ac000 {
+				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+				reg = <0x020ac000 0x4000>;
+				interrupts = <0 74 0x04 0 75 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			kpp: kpp at 020b8000 {
+				reg = <0x020b8000 0x4000>;
+				interrupts = <0 82 0x04>;
+			};
+
+			wdog1: wdog at 020bc000 {
+				compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+				reg = <0x020bc000 0x4000>;
+				interrupts = <0 80 0x04>;
+				clocks = <&clks IMX6SL_CLK_DUMMY>;
+			};
+
+			wdog2: wdog at 020c0000 {
+				compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+				reg = <0x020c0000 0x4000>;
+				interrupts = <0 81 0x04>;
+				clocks = <&clks IMX6SL_CLK_DUMMY>;
+				status = "disabled";
+			};
+
+			clks: ccm at 020c4000 {
+				compatible = "fsl,imx6sl-ccm";
+				reg = <0x020c4000 0x4000>;
+				interrupts = <0 87 0x04 0 88 0x04>;
+				#clock-cells = <1>;
+			};
+
+			anatop: anatop at 020c8000 {
+				compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+				reg = <0x020c8000 0x1000>;
+				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+
+				regulator-1p1 at 110 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p1";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1375000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x110>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <4>;
+					anatop-min-voltage = <800000>;
+					anatop-max-voltage = <1375000>;
+				};
+
+				regulator-3p0 at 120 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd3p0";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <3150000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x120>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0>;
+					anatop-min-voltage = <2625000>;
+					anatop-max-voltage = <3400000>;
+				};
+
+				regulator-2p5 at 130 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd2p5";
+					regulator-min-microvolt = <2100000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x130>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0>;
+					anatop-min-voltage = <2100000>;
+					anatop-max-voltage = <2850000>;
+				};
+
+				reg_arm: regulator-vddcore at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "cpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1450000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x140>;
+					anatop-vol-bit-shift = <0>;
+					anatop-vol-bit-width = <5>;
+					anatop-delay-reg-offset = <0x170>;
+					anatop-delay-bit-shift = <24>;
+					anatop-delay-bit-width = <2>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1450000>;
+				};
+
+				reg_pu: regulator-vddpu at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vddpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1450000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x140>;
+					anatop-vol-bit-shift = <9>;
+					anatop-vol-bit-width = <5>;
+					anatop-delay-reg-offset = <0x170>;
+					anatop-delay-bit-shift = <26>;
+					anatop-delay-bit-width = <2>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1450000>;
+				};
+
+				reg_soc: regulator-vddsoc at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vddsoc";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1450000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x140>;
+					anatop-vol-bit-shift = <18>;
+					anatop-vol-bit-width = <5>;
+					anatop-delay-reg-offset = <0x170>;
+					anatop-delay-bit-shift = <28>;
+					anatop-delay-bit-width = <2>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1450000>;
+				};
+			};
+
+			usbphy1: usbphy at 020c9000 {
+				compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+				reg = <0x020c9000 0x1000>;
+				interrupts = <0 44 0x04>;
+				clocks = <&clks IMX6SL_CLK_USBPHY1>;
+			};
+
+			usbphy2: usbphy at 020ca000 {
+				compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+				reg = <0x020ca000 0x1000>;
+				interrupts = <0 45 0x04>;
+				clocks = <&clks IMX6SL_CLK_USBPHY2>;
+			};
+
+			snvs at 020cc000 {
+				compatible = "fsl,sec-v4.0-mon", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x020cc000 0x4000>;
+
+				snvs-rtc-lp at 34 {
+					compatible = "fsl,sec-v4.0-mon-rtc-lp";
+					reg = <0x34 0x58>;
+					interrupts = <0 19 0x04 0 20 0x04>;
+				};
+			};
+
+			epit1: epit at 020d0000 {
+				reg = <0x020d0000 0x4000>;
+				interrupts = <0 56 0x04>;
+			};
+
+			epit2: epit at 020d4000 {
+				reg = <0x020d4000 0x4000>;
+				interrupts = <0 57 0x04>;
+			};
+
+			src: src at 020d8000 {
+				compatible = "fsl,imx6sl-src", "fsl,imx51-src";
+				reg = <0x020d8000 0x4000>;
+				interrupts = <0 91 0x04 0 96 0x04>;
+				#reset-cells = <1>;
+			};
+
+			gpc: gpc at 020dc000 {
+				compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
+				reg = <0x020dc000 0x4000>;
+				interrupts = <0 89 0x04>;
+			};
+
+			iomuxc: iomuxc at 020e0000 {
+				compatible = "fsl,imx6sl-iomuxc";
+				reg = <0x020e0000 0x4000>;
+
+				fec {
+					pinctrl_fec_1: fecgrp-1 {
+						fsl,pins = <
+							MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
+							MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
+							MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
+							MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
+							MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
+							MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
+							MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
+							MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
+							MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp-1 {
+						fsl,pins = <
+							MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+							MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+						>;
+					};
+				};
+
+				usdhc1 {
+					pinctrl_usdhc1_1: usdhc1grp-1 {
+						fsl,pins = <
+							MX6SL_PAD_SD1_CMD__SD1_CMD    0x17059
+							MX6SL_PAD_SD1_CLK__SD1_CLK    0x10059
+							MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+							MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+							MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+							MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+							MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+							MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+							MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+							MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+						>;
+					};
+				};
+
+				usdhc2 {
+					pinctrl_usdhc2_1: usdhc2grp-1 {
+						fsl,pins = <
+							MX6SL_PAD_SD2_CMD__SD2_CMD    0x17059
+							MX6SL_PAD_SD2_CLK__SD2_CLK    0x10059
+							MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+							MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+							MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+							MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+						>;
+					};
+				};
+
+				usdhc3 {
+					pinctrl_usdhc3_1: usdhc3grp-1 {
+						fsl,pins = <
+							MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
+							MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
+							MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+							MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+							MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+							MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+						>;
+					};
+				};
+			};
+
+			csi: csi at 020e4000 {
+				reg = <0x020e4000 0x4000>;
+				interrupts = <0 7 0x04>;
+			};
+
+			spdc: spdc at 020e8000 {
+				reg = <0x020e8000 0x4000>;
+				interrupts = <0 6 0x04>;
+			};
+
+			sdma: sdma at 020ec000 {
+				compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
+				reg = <0x020ec000 0x4000>;
+				interrupts = <0 2 0x04>;
+				clocks = <&clks IMX6SL_CLK_SDMA>,
+					 <&clks IMX6SL_CLK_SDMA>;
+				clock-names = "ipg", "ahb";
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
+			};
+
+			pxp: pxp at 020f0000 {
+				reg = <0x020f0000 0x4000>;
+				interrupts = <0 98 0x04>;
+			};
+
+			epdc: epdc at 020f4000 {
+				reg = <0x020f4000 0x4000>;
+				interrupts = <0 97 0x04>;
+			};
+
+			lcdif: lcdif at 020f8000 {
+				reg = <0x020f8000 0x4000>;
+				interrupts = <0 39 0x04>;
+			};
+
+			dcp: dcp at 020fc000 {
+				reg = <0x020fc000 0x4000>;
+				interrupts = <0 99 0x04>;
+			};
+		};
+
+		aips2: aips-bus at 02100000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x02100000 0x100000>;
+			ranges;
+
+			usbotg1: usb at 02184000 {
+				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+				reg = <0x02184000 0x200>;
+				interrupts = <0 43 0x04>;
+				clocks = <&clks IMX6SL_CLK_USBOH3>;
+				fsl,usbphy = <&usbphy1>;
+				fsl,usbmisc = <&usbmisc 0>;
+				status = "disabled";
+			};
+
+			usbotg2: usb at 02184200 {
+				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+				reg = <0x02184200 0x200>;
+				interrupts = <0 40 0x04>;
+				clocks = <&clks IMX6SL_CLK_USBOH3>;
+				fsl,usbphy = <&usbphy2>;
+				fsl,usbmisc = <&usbmisc 1>;
+				status = "disabled";
+			};
+
+			usbh: usb at 02184400 {
+				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+				reg = <0x02184400 0x200>;
+				interrupts = <0 42 0x04>;
+				clocks = <&clks IMX6SL_CLK_USBOH3>;
+				fsl,usbmisc = <&usbmisc 2>;
+				status = "disabled";
+			};
+
+			usbmisc: usbmisc at 02184800 {
+				#index-cells = <1>;
+				compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
+				reg = <0x02184800 0x200>;
+				clocks = <&clks IMX6SL_CLK_USBOH3>;
+			};
+
+			fec: ethernet at 02188000 {
+				compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
+				reg = <0x02188000 0x4000>;
+				interrupts = <0 114 0x04>;
+				clocks = <&clks IMX6SL_CLK_ENET_REF>,
+					 <&clks IMX6SL_CLK_ENET_REF>;
+				clock-names = "ipg", "ahb";
+				status = "disabled";
+			};
+
+			usdhc1: usdhc at 02190000 {
+				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+				reg = <0x02190000 0x4000>;
+				interrupts = <0 22 0x04>;
+				clocks = <&clks IMX6SL_CLK_USDHC1>,
+					 <&clks IMX6SL_CLK_USDHC1>,
+					 <&clks IMX6SL_CLK_USDHC1>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc2: usdhc at 02194000 {
+				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+				reg = <0x02194000 0x4000>;
+				interrupts = <0 23 0x04>;
+				clocks = <&clks IMX6SL_CLK_USDHC2>,
+					 <&clks IMX6SL_CLK_USDHC2>,
+					 <&clks IMX6SL_CLK_USDHC2>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc3: usdhc at 02198000 {
+				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+				reg = <0x02198000 0x4000>;
+				interrupts = <0 24 0x04>;
+				clocks = <&clks IMX6SL_CLK_USDHC3>,
+					 <&clks IMX6SL_CLK_USDHC3>,
+					 <&clks IMX6SL_CLK_USDHC3>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc4: usdhc at 0219c000 {
+				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+				reg = <0x0219c000 0x4000>;
+				interrupts = <0 25 0x04>;
+				clocks = <&clks IMX6SL_CLK_USDHC4>,
+					 <&clks IMX6SL_CLK_USDHC4>,
+					 <&clks IMX6SL_CLK_USDHC4>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 021a0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+				reg = <0x021a0000 0x4000>;
+				interrupts = <0 36 0x04>;
+				clocks = <&clks IMX6SL_CLK_I2C1>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 021a4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+				reg = <0x021a4000 0x4000>;
+				interrupts = <0 37 0x04>;
+				clocks = <&clks IMX6SL_CLK_I2C2>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 021a8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+				reg = <0x021a8000 0x4000>;
+				interrupts = <0 38 0x04>;
+				clocks = <&clks IMX6SL_CLK_I2C3>;
+				status = "disabled";
+			};
+
+			mmdc: mmdc at 021b0000 {
+				compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+				reg = <0x021b0000 0x4000>;
+			};
+
+			rngb: rngb at 021b4000 {
+				reg = <0x021b4000 0x4000>;
+				interrupts = <0 5 0x04>;
+			};
+
+			weim: weim at 021b8000 {
+				reg = <0x021b8000 0x4000>;
+				interrupts = <0 14 0x04>;
+			};
+
+			ocotp: ocotp at 021bc000 {
+				compatible = "fsl,imx6sl-ocotp";
+				reg = <0x021bc000 0x4000>;
+			};
+
+			audmux: audmux at 021d8000 {
+				compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
+				reg = <0x021d8000 0x4000>;
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.7.9.5




From mturquette at linaro.org  Fri May  3 00:04:16 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 02 May 2013 21:04:16 -0700
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <1367511416-4312-2-git-send-email-linus.walleij@stericsson.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
 <1367511416-4312-2-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130503040416.7790.51673@quantum>

Quoting Linus Walleij (2013-05-02 09:16:49)
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> Get rid of the <mach/syscon.h> header as a prerequisite for
> multiplatform support. Do this by pushing the registers down
> to their respective drivers and deleting the unused remainder.
> 
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> Mike: I'm seeking an ACK for this to take it through the
> ARM SoC tree alongside the big bowl of DT enablement patches.

For the clk-u300.c part:
Acked-by: Mike Turquette <mturquette at linaro.org>


From viresh.kumar at linaro.org  Fri May  3 00:51:45 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Fri, 3 May 2013 10:21:45 +0530
Subject: [PATCH,
 RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <1367507786-505303-3-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-3-git-send-email-arnd@arndb.de>
Message-ID: <CAKohpomBKuaxk+sSF63cu6JKut1uV7J7Sj2o85c3wQ=fodx+Ow@mail.gmail.com>

On 2 May 2013 20:46, Arnd Bergmann <arnd at arndb.de> wrote:
> The big.LITTLE cpufreq driver uses the CPU topology API, which
> needs to be reflected in Kconfig to prevent broken configurations.
>
> warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
> has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM && ARM_CPU_TOPOLOGY)
>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Viresh Kumar <viresh.kumar at linaro.org>
> Cc: cpufreq at vger.kernel.org
> Cc: linux-pm at vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/cpufreq/Kconfig.arm | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index f3af18b..3fd6bdf 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -10,6 +10,7 @@ config ARM_DT_BL_CPUFREQ
>         tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
>         select ARM_BIG_LITTLE_CPUFREQ
>         depends on OF && HAVE_CLK
> +       depends on ARM_CPU_TOPOLOGY
>         help
>           This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
>           This gets frequency tables from DT.

This Kconfig thing has always been confusing to me. This is how the code looks
currently.

config ARM_BIG_LITTLE_CPUFREQ
        tristate
        depends on ARM_CPU_TOPOLOGY

config ARM_DT_BL_CPUFREQ
        tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
        select ARM_BIG_LITTLE_CPUFREQ
        depends on OF && HAVE_CLK
        help
          This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
          This gets frequency tables from DT.

Because all ARM big LITTLE cpufreq stuff have dependency on
ARM_CPU_TOPOLOGY, i have added dependency at a common place. So that
we don't end up adding this in every glue layer driver. How should this be done?


From viresh.kumar at linaro.org  Fri May  3 00:55:57 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Fri, 3 May 2013 10:25:57 +0530
Subject: [PATCH 0/9] arm-soc: randconfig fixes
In-Reply-To: <1367528578-518090-1-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
Message-ID: <CAOh2x==vXWEoA_D1H5iXFsrVv3pWFnUNx0vpc-KjuU+vVZ86Pw@mail.gmail.com>

On Fri, May 3, 2013 at 2:32 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> Arnd Bergmann (9):
>   ARM: SPEAr: conditionalize l2x0 support
>   ARM: SPEAr: conditionalize SMP code

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From viresh.kumar at linaro.org  Fri May  3 00:57:17 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Fri, 3 May 2013 10:27:17 +0530
Subject: [PATCH 1/9] ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
In-Reply-To: <1367528578-518090-2-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-2-git-send-email-arnd@arndb.de>
Message-ID: <CAOh2x==i-_+30mmMp=WkcCQn4qm1-nGfWpPuQnScvRQVd=h+LA@mail.gmail.com>

On Fri, May 3, 2013 at 2:32 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> Like the other Tegra SoCs using the same cpufreq driver, we
> have to enable CPU_FREQ_TABLE for this one.
>
> drivers/built-in.o: In function `tegra_cpu_exit':
>  drivers/cpufreq/tegra-cpufreq.c:237: undefined reference to
>  `cpufreq_frequency_table_cpuinfo'
>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Hiroshi Doyu <hdoyu at nvidia.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/arm/mach-tegra/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 597e76b..9878503 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -63,6 +63,7 @@ config ARCH_TEGRA_114_SOC
>         select ARM_ARCH_TIMER
>         select ARM_GIC
>         select ARM_L1_CACHE_SHIFT_6
> +       select CPU_FREQ_TABLE if CPU_FREQ
>         select CPU_V7
>         select PINCTRL
>         select PINCTRL_TEGRA114

I doubt which is the best place for doing this? This one or
cpufreq/Kconfig.arm with select CPU_FREQ_TABLE for
tegra?


From andrew at lunn.ch  Fri May  3 01:06:32 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 3 May 2013 07:06:32 +0200
Subject: [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
In-Reply-To: <1367538519-23940-3-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-3-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130503050632.GC24965@lunn.ch>

On Fri, May 03, 2013 at 01:48:36AM +0200, Sebastian Hesselbarth wrote:
> To allow to move to orion irqchip driver, existing legacy devices
> have to map their irqs. This patch adds init code to map the
> corresponding irqs. It will vanish as soon as there is true device tree
> support for mv643xx_eth.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Changelog:
> v1->v2:
> - split off DT changes (Suggested by Jason Cooper)
> 
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/mach-dove/board-dt.c |   31 ++++++++++++++++++++++++++++++-
>  1 file changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
> index fbde1dd..9df6dd7 100644
> --- a/arch/arm/mach-dove/board-dt.c
> +++ b/arch/arm/mach-dove/board-dt.c
> @@ -12,6 +12,7 @@
>  #include <linux/clk-provider.h>
>  #include <linux/clk/mvebu.h>
>  #include <linux/of.h>
> +#include <linux/of_irq.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_data/usb-ehci-orion.h>
>  #include <asm/hardware/cache-tauros2.h>
> @@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
>  	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
>  };
>  
> +#define DOVE_GE00_PHYS_BASE	0xf1070000
> +
> +static void __init dove_legacy_ge00_init(void)
> +{
> +	struct device_node *np = of_find_compatible_node(NULL, NULL,
> +					 "marvell,mv643xx-eth-block");
> +	int irq_sum, irq_err;
> +
> +	if (!np)
> +		return;
> +
> +	irq_sum = irq_of_parse_and_map(np, 0);
> +	if (!irq_sum) {
> +		pr_err("%s: missing sum irq\n", np->full_name);
> +		return;
> +	}
> +
> +	irq_err = irq_of_parse_and_map(np, 1);
> +	if (!irq_err) {
> +		pr_err("%s: missing err irq\n", np->full_name);
> +		return;
> +	}
> +
> +	/* legacy ge00_init wants phys base */
> +	orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
> +			irq_sum, irq_err, 1600);
> +}

Hi Sebastian

I know the above code is throw away, but it might help with getting
Kirkwood, Orion5x, mv78xx00 supported if we refactor this code and
move most of it into plat-orion/common.c. I could imaging a function

orion_ge00_irq_init(struct mv643xx_eth_platform_data *eth_data,
                    unsigned long mapbase, unsigned int tx_csum_limit)

which does the irq lookup and then calls orion_ge00_init().


Jason: what is the status of the ethernet driver conversion to DT?
Will it get merged this week, or is it material for the next merge
window?

      Andrew


From marek.belisko at gmail.com  Fri May  3 01:33:27 2013
From: marek.belisko at gmail.com (Marek Belisko)
Date: Fri,  3 May 2013 07:33:27 +0200
Subject: [PATCH v2] clk: si5351: Allow user to define disabled state for every
 clock output
Message-ID: <1367559207-20086-1-git-send-email-marek.belisko@streamunlimited.com>

From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>

This patch adds platform data and DT bindings to allow to overwrite
the stored disabled state for each clock output.

Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changes from v1->v2:
Sebastian Hesselbarth send me updated version of patch which was based
on v1. Resending with updates.

 .../devicetree/bindings/clock/silabs,si5351.txt    |    5 ++
 drivers/clk/clk-si5351.c                           |   74 +++++++++++++++++++-
 drivers/clk/clk-si5351.h                           |    1 +
 include/linux/platform_data/si5351.h               |   18 +++++
 4 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
index cc37465..66c75b2 100644
--- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt
+++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
@@ -44,6 +44,11 @@ Optional child node properties:
 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
   divider.
 - silabs,pll-master: boolean, multisynth can change pll frequency.
+- silabs,disable-state : clock output disable state, shall be
+  0 = clock output is driven LOW when disabled
+  1 = clock output is driven HIGH when disabled
+  2 = clock output is FLOATING (HIGH-Z) when disabled
+  3 = clock output is NEVER disabled
 
 ==Example==
 
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 8323c31..098f28b 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -851,6 +851,41 @@ static int _si5351_clkout_set_drive_strength(
 	return 0;
 }
 
+static int _si5351_clkout_set_disable_state(
+	struct si5351_driver_data *drvdata, int num,
+	enum si5351_disable_state state)
+{
+	u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
+		SI5351_CLK7_4_DISABLE_STATE;
+	u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
+	u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
+	u8 val;
+
+	if (num > 8)
+		return -EINVAL;
+
+	switch (state) {
+	case SI5351_DISABLE_LOW:
+		val = SI5351_CLK_DISABLE_STATE_LOW;
+		break;
+	case SI5351_DISABLE_HIGH:
+		val = SI5351_CLK_DISABLE_STATE_HIGH;
+		break;
+	case SI5351_DISABLE_FLOATING:
+		val = SI5351_CLK_DISABLE_STATE_FLOAT;
+		break;
+	case SI5351_DISABLE_NEVER:
+		val = SI5351_CLK_DISABLE_STATE_NEVER;
+		break;
+	default:
+		return 0;
+	}
+
+	si5351_set_bits(drvdata, reg, mask, val << shift);
+
+	return 0;
+}
+
 static int si5351_clkout_prepare(struct clk_hw *hw)
 {
 	struct si5351_hw_data *hwdata =
@@ -1225,6 +1260,33 @@ static int si5351_dt_parse(struct i2c_client *client)
 			}
 		}
 
+		if (!of_property_read_u32(child, "silabs,disable-state",
+					  &val)) {
+			switch (val) {
+			case 0:
+				pdata->clkout[num].disable_state =
+					SI5351_DISABLE_LOW;
+				break;
+			case 1:
+				pdata->clkout[num].disable_state =
+					SI5351_DISABLE_HIGH;
+				break;
+			case 2:
+				pdata->clkout[num].disable_state =
+					SI5351_DISABLE_FLOATING;
+				break;
+			case 3:
+				pdata->clkout[num].disable_state =
+					SI5351_DISABLE_NEVER;
+				break;
+			default:
+				dev_err(&client->dev,
+					"invalid disable state %d for clkout %d\n",
+					val, num);
+				return -EINVAL;
+			}
+		}
+
 		if (!of_property_read_u32(child, "clock-frequency", &val))
 			pdata->clkout[num].rate = val;
 
@@ -1281,9 +1343,6 @@ static int si5351_i2c_probe(struct i2c_client *client,
 
 	/* Disable interrupts */
 	si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
-	/* Set disabled output drivers to drive low */
-	si5351_reg_write(drvdata, SI5351_CLK3_0_DISABLE_STATE, 0x00);
-	si5351_reg_write(drvdata, SI5351_CLK7_4_DISABLE_STATE, 0x00);
 	/* Ensure pll select is on XTAL for Si5351A/B */
 	if (drvdata->variant != SI5351_VARIANT_C)
 		si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
@@ -1327,6 +1386,15 @@ static int si5351_i2c_probe(struct i2c_client *client,
 				n, pdata->clkout[n].drive);
 			return ret;
 		}
+
+		ret = _si5351_clkout_set_disable_state(drvdata, n,
+						pdata->clkout[n].disable_state);
+		if (ret) {
+			dev_err(&client->dev,
+				"failed set disable state of clkout%d to %d\n",
+				n, pdata->clkout[n].disable_state);
+			return ret;
+		}
 	}
 
 	/* register xtal input clock gate */
diff --git a/drivers/clk/clk-si5351.h b/drivers/clk/clk-si5351.h
index af41b50..c0dbf26 100644
--- a/drivers/clk/clk-si5351.h
+++ b/drivers/clk/clk-si5351.h
@@ -81,6 +81,7 @@
 
 #define SI5351_CLK3_0_DISABLE_STATE		24
 #define SI5351_CLK7_4_DISABLE_STATE		25
+#define  SI5351_CLK_DISABLE_STATE_MASK		3
 #define  SI5351_CLK_DISABLE_STATE_LOW		0
 #define  SI5351_CLK_DISABLE_STATE_HIGH		1
 #define  SI5351_CLK_DISABLE_STATE_FLOAT		2
diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h
index 92dabca..5433439 100644
--- a/include/linux/platform_data/si5351.h
+++ b/include/linux/platform_data/si5351.h
@@ -79,6 +79,23 @@ enum si5351_drive_strength {
 };
 
 /**
+ * enum si5351_disable_state - Si5351 clock output disable state
+ * @SI5351_DISABLE_DEFAULT: default, do not change eeprom config
+ * @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled
+ * @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled
+ * @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when
+ *				disabled
+ * @SI5351_DISABLE_NEVER: CLKx is NEVER disabled
+ */
+enum si5351_disable_state {
+	SI5351_DISABLE_DEFAULT = 0,
+	SI5351_DISABLE_LOW,
+	SI5351_DISABLE_HIGH,
+	SI5351_DISABLE_FLOATING,
+	SI5351_DISABLE_NEVER,
+};
+
+/**
  * struct si5351_clkout_config - Si5351 clock output configuration
  * @clkout: clkout number
  * @multisynth_src: multisynth source clock
@@ -91,6 +108,7 @@ struct si5351_clkout_config {
 	enum si5351_multisynth_src multisynth_src;
 	enum si5351_clkout_src clkout_src;
 	enum si5351_drive_strength drive;
+	enum si5351_disable_state disable_state;
 	bool pll_master;
 	unsigned long rate;
 };
-- 
1.7.9.5



From airlied at gmail.com  Fri May  3 01:40:25 2013
From: airlied at gmail.com (Dave Airlie)
Date: Fri, 3 May 2013 15:40:25 +1000
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <517FAF0C.1060901@ti.com>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <517F7245.2050606@iki.fi> <201304301228.42245.arnd@arndb.de>
 <517FAF0C.1060901@ti.com>
Message-ID: <CAPM=9twuLZT=BaGrmE6fvsSXciitG383ZnghP0hOnSfNGq=A5Q@mail.gmail.com>

>
> I think it would be reasonable to have a restriction of only a single
> bootfb instance, so one could just use static global variables/funcs to
> manage the hand-over.
>
> All this, of course, presumes that nobody else than fbcon is using the
> fb. But I think it's also a reasonable restriction that the fb device is
> not used (mmapped) by anyone.
>

We already have this on x86, though the handover isn't great,

FBINFO_MISC_FIRMWARE flag, and the aperture tracking stuff.

Dave.


From marek.belisko at gmail.com  Fri May  3 01:53:22 2013
From: marek.belisko at gmail.com (Marek Belisko)
Date: Fri,  3 May 2013 07:53:22 +0200
Subject: [PATCH v2 1/2] clk: si5351: Fix clkout rate computation.
Message-ID: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>

Rate was incorrectly computed because we read from wrong divider register.

Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
 drivers/clk/clk-si5351.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 8927284..cf39e53 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
 	unsigned char reg;
 	unsigned char rdiv;
 
-	if (hwdata->num > 5)
+	if (hwdata->num <= 5)
 		reg = si5351_msynth_params_address(hwdata->num) + 2;
 	else
 		reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
-- 
1.7.9.5



From marek.belisko at gmail.com  Fri May  3 01:53:23 2013
From: marek.belisko at gmail.com (Marek Belisko)
Date: Fri,  3 May 2013 07:53:23 +0200
Subject: [PATCH v2 2/2] clk: si5351: Set initial clkout rate when defined in
 platform data.
In-Reply-To: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
References: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <1367560403-21685-2-git-send-email-marek.belisko@streamunlimited.com>

Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
---
Changes v1->v2:
- update commit message and comment to refer to platform data not DT

 drivers/clk/clk-si5351.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index cf39e53..24f5536 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client,
 			return -EINVAL;
 		}
 		drvdata->onecell.clks[n] = clk;
+
+		/* set initial clkout rate */
+		if (pdata->clkout[n].rate != 0) {
+			int ret;
+			ret = clk_set_rate(clk, pdata->clkout[n].rate);
+			if (ret != 0) {
+				dev_err(&client->dev, "Cannot set rate : %d\n",
+					ret);
+			}
+		}
 	}
 
 	ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
-- 
1.7.9.5



From dirk.behme at de.bosch.com  Fri May  3 02:12:07 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 3 May 2013 08:12:07 +0200
Subject: [PATCH] ARM: imx: fix typo in gpu3d_shader_sels
In-Reply-To: <1367549979-31291-1-git-send-email-shawn.guo@linaro.org>
References: <1367549979-31291-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <51835537.7040604@de.bosch.com>

On 03.05.2013 04:59, Shawn Guo wrote:
> There is no clock pll2_pfd9_720m.  Instead it should be pll3_pfd0_720m.
> Fix the typo in gpu3d_shader_sels.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>   arch/arm/mach-imx/clk-imx6q.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index f2e1c62..dda9a2b 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -186,7 +186,7 @@ static const char *audio_sels[]	= { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd
>   static const char *gpu_axi_sels[]	= { "axi", "ahb", };
>   static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
>   static const char *gpu3d_core_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
> -static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
> +static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
>   static const char *ipu_sels[]		= { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
>   static const char *ldb_di_sels[]	= { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
>   static const char *ipu_di_pre_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };

Acked-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk


From balbi at ti.com  Fri May  3 02:21:51 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 May 2013 09:21:51 +0300
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130502231353.GF21614@n2100.arm.linux.org.uk>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
Message-ID: <20130503061931.GB27451@arwen.pp.htv.fi>

Hi,

On Fri, May 03, 2013 at 12:13:53AM +0100, Russell King - ARM Linux wrote:
> > > > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > > > ---
> > > > >  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
> > > > >  1 file changed, 17 insertions(+), 4 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> > > > > index aa27d7f..8d17a0d 100644
> > > > > --- a/arch/arm/mach-omap2/usb-host.c
> > > > > +++ b/arch/arm/mach-omap2/usb-host.c
> > > > > @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > > >  	supplies->dev_name = dev_id;
> > > > >  
> > > > >  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> > > > > -	if (!reg_data)
> > > > > +	if (!reg_data) {
> > > > > +		kfree(supplies);
> > > > >  		return -ENOMEM;
> > > > > +	}
> > > > >  
> > > > >  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> > > > >  	reg_data->consumer_supplies = supplies;
> > > > > @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > > >  
> > > > >  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
> > > > >  			GFP_KERNEL);
> > > > > -	if (!config)
> > > > > +	if (!config) {
> > > > > +		kfree(supplies);
> > > > > +		kfree(reg_data);
> > > > >  		return -ENOMEM;
> > > > > +	}
> > > > >  
> > > > >  	config->supply_name = name;
> > > > >  	config->gpio = gpio;
> > > > > @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > > >  
> > > > >  	/* create a regulator device */
> > > > >  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> > > > > -	if (!pdev)
> > > > > +	if (!pdev) {
> > > > > +		kfree(supplies);
> > > > > +		kfree(reg_data);
> > > > > +		kfree(config);
> > > > >  		return -ENOMEM;
> > > > > +	}
> > > > >  
> > > > >  	pdev->id = PLATFORM_DEVID_AUTO;
> > > > >  	pdev->name = reg_name;
> > > > >  	pdev->dev.platform_data = config;
> > > > >  
> > > > >  	ret = platform_device_register(pdev);
> > > > > -	if (ret)
> > > > > +	if (ret) {
> > > > >  		pr_err("%s: Failed registering regulator %s for %s\n",
> > > > >  				__func__, name, dev_id);
> > > > > +		kfree(supplies);
> > > > > +		kfree(reg_data);
> > > > > +		kfree(config);
> > > > > +	}
> > > > 
> > > > Might be better to switch to devm_XXX managed functions?
> > 
> > I don't think it makes sense since the platform_device hasn't been
> > registered yet.
> > 
> > Still, patch can be improved with proper goto labels instead of
> > sprinkling different kfree() calls in every single error branch.
> > 
> > > If anyone can rewrite driver to use devm_xx, it would have been better.
> > > I'm not going to redo the patch yet, let it be so, I just showed a point
> > > for OMAP-developers.
> > 
> > fair enough.
> 
> Well, as long as this crap violates the driver model by using kfree() on
> a device...  Devices are refcounted and must only be freed when the
> refcount drops to zero.

read the patch again, there's no kfree() on any device. There is a kfree
of supplies, reg_data and config.

On top of that, the code being changed here doesn't even exist, so I
wonder which tree is this code based off. usb-host.c has always being
using omap_device_build() which internally calls
platform_device_alloc().

> This is exactly why we have platform_device_alloc(),
> platform_device_register_full() and friends - so that people don't have to
> fsck around with kzalloc themselves and get it wrong like the above does.
> 
> Would you like me to pass your details to gregkh for another one of his
> public humilation exercises over basic kernel programming stuff? :)

How about we pass yours for not reading the patch before flaming ? Note
that $SUBJECT is *not* touching at all that line which kzallocs a
platform_device. Wrong as it is, it's not part of $SUBJECT.

-- 
balbi
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From balbi at ti.com  Fri May  3 02:25:06 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 May 2013 09:25:06 +0300
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503061931.GB27451@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
Message-ID: <20130503062506.GC27451@arwen.pp.htv.fi>

Hi,

On Fri, May 03, 2013 at 09:21:51AM +0300, Felipe Balbi wrote:
> > This is exactly why we have platform_device_alloc(),
> > platform_device_register_full() and friends - so that people don't have to
> > fsck around with kzalloc themselves and get it wrong like the above does.
> > 
> > Would you like me to pass your details to gregkh for another one of his
> > public humilation exercises over basic kernel programming stuff? :)
> 
> How about we pass yours for not reading the patch before flaming ? Note
> that $SUBJECT is *not* touching at all that line which kzallocs a
> platform_device. Wrong as it is, it's not part of $SUBJECT.

that line was added by Roger on commit
5ecd52e563f1e14f9cfe06130fbf9fdb73f227e8 (ARM: OMAP2+: omap-usb-host: Add
usbhs_init_phys()).

-- 
balbi
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From balbi at ti.com  Fri May  3 02:25:35 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 May 2013 09:25:35 +0300
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503062506.GC27451@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
 <20130503062506.GC27451@arwen.pp.htv.fi>
Message-ID: <20130503062535.GD27451@arwen.pp.htv.fi>

On Fri, May 03, 2013 at 09:25:06AM +0300, Felipe Balbi wrote:
> > > This is exactly why we have platform_device_alloc(),
> > > platform_device_register_full() and friends - so that people don't have to
> > > fsck around with kzalloc themselves and get it wrong like the above does.
> > > 
> > > Would you like me to pass your details to gregkh for another one of his
> > > public humilation exercises over basic kernel programming stuff? :)
> > 
> > How about we pass yours for not reading the patch before flaming ? Note
> > that $SUBJECT is *not* touching at all that line which kzallocs a
> > platform_device. Wrong as it is, it's not part of $SUBJECT.
> 
> that line was added by Roger on commit
> 5ecd52e563f1e14f9cfe06130fbf9fdb73f227e8 (ARM: OMAP2+: omap-usb-host: Add
> usbhs_init_phys()).

forgot to add him to Cc, now done.

-- 
balbi
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From dirk.behme at de.bosch.com  Fri May  3 02:26:34 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 3 May 2013 08:26:34 +0200
Subject: [PATCH 4/5] ARM: dts: add device tree source for imx6sl SoC
In-Reply-To: <1367552995-31777-5-git-send-email-shawn.guo@linaro.org>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
 <1367552995-31777-5-git-send-email-shawn.guo@linaro.org>
Message-ID: <5183589A.5090109@de.bosch.com>

On 03.05.2013 05:49, Shawn Guo wrote:
> Add SoC level device tree source for imx6sl.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>   arch/arm/boot/dts/imx6sl.dtsi |  777 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 777 insertions(+)
>   create mode 100644 arch/arm/boot/dts/imx6sl.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> new file mode 100644

Just as a proposal do discuss: What's about to move the existing 
imx6qdl.dtsi to a imx6.dtsi and include it in

imx6q.dtsi
imx6dl.dtsi
imx6sl.dtsi

then?

> +       soc {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "simple-bus";
> +               interrupt-parent = <&intc>;
> +               ranges;
> +
> +               L2: l2-cache at 00a02000 {
> +                       compatible = "arm,pl310-cache";
> +                       reg = <0x00a02000 0x1000>;
> +                       interrupts = <0 92 0x04>;
> +                       cache-unified;
> +                       cache-level = <2>;
> +               };
The arm,tag-latency and arm,data-latency we recently added for the other 
SoCs are missing here?

Best regards

Dirk

















From grant.likely at secretlab.ca  Fri May  3 02:53:34 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 3 May 2013 07:53:34 +0100
Subject: [GIT PULL] Removal of GENERIC_GPIO
In-Reply-To: <20130503110318.0d30b773852640ee94ba07b5@canb.auug.org.au>
References: <51823DDA.7010103@nvidia.com>
 <20130503105234.6e9c8aa5ed2784bbe084caa8@canb.auug.org.au>
 <20130503110318.0d30b773852640ee94ba07b5@canb.auug.org.au>
Message-ID: <CACxGe6tdJr22bJ0GZL_18FqYWLdNROMKuH3UQbKciEwRy9v1Wg@mail.gmail.com>

On Fri, May 3, 2013 at 2:03 AM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Hi Guys,
>
> On Fri, 3 May 2013 10:52:34 +1000 Stephen Rothwell <sfr at canb.auug.org.au> wrote:
>>
>> I currently have 3 merge fix patches for the gen-cpio tree:
>>
>> gen-gpio: GPIOLIB merge fix up
>> merge fix for Convert selectors of GENERIC_GPIO to GPIOLIB
>> merge fix 2 for Convert selectors of GENERIC_GPIO to GPIOLIB
>>
>> I have attached them.  All three are now applicable to Linus' tree.
>
> Just to absolutely clear, I *do not* expect either of you to rebase your
> trees or backmerge Linus' tree to fix these, I *do* expect whoever send
> this stuff to Linus to mention the necessary fixes to him.

Yes, that is exactly what I'm going to do

g.


From srinidhi.kasagar at stericsson.com  Fri May  3 03:07:14 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Fri, 3 May 2013 12:37:14 +0530
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
Message-ID: <20130503070713.GA27956@bnru09>

On Thu, May 02, 2013 at 17:48:10 +0200, Lee Jones wrote:
> drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
>         In function ?synaptics_rmi4_resume?:
> drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
>         warning: ignoring return value of ?regulator_enable?, declared
>         with attribute warn_unused_result [-Wunused-result
> 
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: devel at driverdev.osuosl.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> index fe667dd..c4d013d 100644
> --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> @@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
>  	unsigned char intr_status;
>  	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
>  
> -	regulator_enable(rmi4_data->regulator);
> +	retval = regulator_enable(rmi4_data->regulator);
> +	if (retval < 0)
> +		return retval;
Does it make sense to add a dev_err?


Otherwise, you can add my
Acked-by:srinidhi kasagar <srinidhi.kasagar at stericsson.com> for this series.

>  
>  	enable_irq(rmi4_data->i2c_client->irq);
>  	rmi4_data->touch_stopped = false;
> -- 
> 1.7.10.4
> 


From lee.jones at linaro.org  Fri May  3 03:11:42 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 08:11:42 +0100
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <20130503070713.GA27956@bnru09>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
 <20130503070713.GA27956@bnru09>
Message-ID: <20130503071142.GB24153@gmail.com>

On Fri, 03 May 2013, Srinidhi Kasagar wrote:

> On Thu, May 02, 2013 at 17:48:10 +0200, Lee Jones wrote:
> > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
> >         In function ?synaptics_rmi4_resume?:
> > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
> >         warning: ignoring return value of ?regulator_enable?, declared
> >         with attribute warn_unused_result [-Wunused-result
> > 
> > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > Cc: devel at driverdev.osuosl.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > index fe667dd..c4d013d 100644
> > --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > @@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
> >  	unsigned char intr_status;
> >  	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
> >  
> > -	regulator_enable(rmi4_data->regulator);
> > +	retval = regulator_enable(rmi4_data->regulator);
> > +	if (retval < 0)
> > +		return retval;
> Does it make sense to add a dev_err?

Yes, I can do that.

> Otherwise, you can add my
> Acked-by:srinidhi kasagar <srinidhi.kasagar at stericsson.com> for this series.

Thanks.

> >  
> >  	enable_irq(rmi4_data->i2c_client->irq);
> >  	rmi4_data->touch_stopped = false;

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From shawn.guo at linaro.org  Fri May  3 03:41:07 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 15:41:07 +0800
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <1367480285-26159-2-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
Message-ID: <20130503074105.GA31873@S2101-09.ap.freescale.net>

On Thu, May 02, 2013 at 03:38:04PM +0800, Jingchang Lu wrote:
> This patch adds Freescale Vybrid Family platform core definitions,
> core drivers, including clock, period interrupt timer(PIT),

IMO, separating the patch into 3 would make the reviewing and
merging a little easier, e.g. one patch for PIT, one patch for clock
driver, and one for the rest.  And this is what I have done for i.MX6
SoloLite series which I have copied you on.

> and DTS based machine support with MVF600 Tower development board.

You do not have these in this patch.

> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
>   Use CLOCKSOURCE_OF_DECLARE init timer
>   Add ONESHOT mode support
>   Add more clks definitions on MVF600 soc
> 
>  .../devicetree/bindings/clock/mvf600-clock.txt     | 180 +++++++++
>  arch/arm/mach-imx/Kconfig                          |  15 +
>  arch/arm/mach-imx/Makefile                         |   3 +
>  arch/arm/mach-imx/clk-mvf.c                        | 406 +++++++++++++++++++++

If the bindings doc is named mvf600-clock, the clock driver should
probably be named clk-mvf600.c?

>  arch/arm/mach-imx/common.h                         |   1 +
>  arch/arm/mach-imx/mach-mvf600.c                    | 118 ++++++
>  arch/arm/mach-imx/pit.c                            | 244 +++++++++++++

We're recently moving ARM timer drivers into drivers/clocksource.  I
think PIT should probably be done that way from the beginning.

>  7 files changed, 967 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
>  create mode 100644 arch/arm/mach-imx/clk-mvf.c
>  create mode 100644 arch/arm/mach-imx/mach-mvf600.c
>  create mode 100644 arch/arm/mach-imx/pit.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
> new file mode 100644
> index 0000000..9f8b20e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
> @@ -0,0 +1,180 @@
> +* Clock bindings for Freescale Vybrid Family

The file name suggest this is a bindings for SoC mvf600, but subject
tells it's for Vybrid Family.  I think these are two slightly different
things, and mvf600 is only a member of Vybrid Family.

> +
> +Required properties:
> +- compatible: Should be "fsl,mvf-ccm"

If this is a compatible of given SoC, it should be "fsl,mvf600-ccm"?

> +- reg: Address and length of the register set
> +- interrupts: Should contain CCM interrupt

I know this is copied from IMX, but if you have no interrupt for CCM,
you shouldn't list it as a required property.  I do not see you define
the property for "ccm" node in the example below.

> +- #clock-cells: Should be <1>
> +
> +The clock consumer should specify the desired clock by having the clock
> +ID in its "clocks" phandle cell.  The following is a full list of MVF600
> +clocks and IDs.
> +
> +	Clock			ID

In the imx6sl clock patch I copied you, we choose to use DTC macro
support to define these clock IDs as macro in a header, and have both
kernel and DTS include the header.  Doing so will help maintain the data
consistency between kernel and DT.

> +	---------------------------
> +	dummy			0
> +	sirc_128k		1
> +	sirc_32k		2
> +	firc			3
> +	sxosc			4
> +	fxosc			5
> +	fxosc_half		6
> +	slow_clk		7
> +	fast_clk		8
> +	audio_ext		9
> +	enet_ext		10
> +	pll1_main_528m		11
> +	pll1_pfd1_500m		12
> +	pll1_pfd2_452m		13
> +	pll1_pfd3_396m		14
> +	pll1_pfd4_528m		15
> +	pll2_main_528m		16
> +	pll2_pfd1_500m		17
> +	pll2_pfd2_396m		18
> +	pll2_pfd3_339m		19
> +	pll2_pfd4_413m		20
> +	pll3_main_480m		21
> +	pll3_pfd1_308m		22
> +	pll3_pfd2_332m		23
> +	pll3_pfd3_298m		24
> +	pll3_pfd4_320m		25
> +	pll4_main		26
> +	pll5_main		27
> +	pll6_main		28
> +	pll3_main_div		29
> +	pll4_main_div		30
> +	pll6_main_div		31
> +	pll1_sw			32
> +	pll2_sw			33
> +	sys_sw			34
> +	ddr_sw			35
> +	sys_bus_clk		36
> +	platform_bus_clk	37
> +	ipg_bus_clk		38
> +	uart0_clk		39
> +	uart1_clk		40
> +	uart2_clk		41
> +	uart3_clk		42
> +	uart4_clk		43
> +	uart5_clk		44
> +	pit_clk			45
> +	i2c0_clk		46
> +	i2c1_clk		47
> +	i2c2_clk		48
> +	i2c3_clk		49
> +	ftm0_ext_sw		50
> +	ftm0_fix_sw		51
> +	ftm0_ext_fix_gate	52
> +	ftm1_ext_sw		53
> +	ftm1_fix_sw		54
> +	ftm1_ext_fix_gate	55
> +	ftm2_ext_sw		56
> +	ftm2_fix_sw		57
> +	ftm2_ext_fix_gate	58
> +	ftm3_ext_sw		59
> +	ftm3_fix_sw		60
> +	ftm3_ext_fix_gate	61
> +	ftm0_clk		62
> +	ftm1_clk		63
> +	ftm2_clk		64
> +	ftm3_clk		65
> +	enet_50m		66
> +	enet_25m		67
> +	enet_clk_sw		68
> +	enet_clk		69
> +	enet_ts_sw		70
> +	enet_ts			71
> +	dspi0_clk		72
> +	dspi1_clk		73
> +	dspi2_clk		74
> +	dspi3_clk		75
> +	wdt_clk			76
> +	esdhc0_sw		77
> +	esdhc0_gate		78
> +	esdhc0_div		79
> +	esdhc0_clk		80
> +	esdhc1_sw		81
> +	esdhc1_gate		82
> +	esdhc1_div		83
> +	esdhc1_clk		84
> +	dcu0_sw			85
> +	dcu0_gate		86
> +	dcu0_div		87
> +	dcu0_clk		88
> +	dcu1_sw			89
> +	dcu1_gate		90
> +	dcu1_div		91
> +	dcu1_clk		92
> +	esai_sw			93
> +	esai_gate		94
> +	esai_div		95
> +	esai_clk		96
> +	sai0_sw			97
> +	sai0_gate		98
> +	sai0_div		99
> +	sai0_clk		100
> +	sai1_sw			101
> +	sai1_gate		102
> +	sai1_div		103
> +	sai1_clk		104
> +	sai2_sw			105
> +	sai2_gate		106
> +	sai2_div		107
> +	sai2_clk		108
> +	sai3_sw			109
> +	sai3_gate		110
> +	sai3_div		111
> +	sai3_clk		112
> +	usbc0_clk		113
> +	usbc1_clk		114
> +	qspi0_sw		115
> +	qspi0_gate		116
> +	qspi0_x4_div		117
> +	qspi0_x2_div		118
> +	qspi0_x1_div		119
> +	qspi1_sw		120
> +	qspi1_gate		121
> +	qspi1_x4_div		122
> +	qspi1_x2_div		123
> +	qspi1_x1_div		124
> +	qspi0_clk		125
> +	qspi1_clk		126
> +	nfc_sw			127
> +	nfc_gate		128
> +	nfc_pre_div		129
> +	nfc_frac_div		130
> +	nfc_inv			131
> +	nfc_clk			132
> +	vadc_sw			133
> +	vadc_gate		134
> +	vadc_div		135
> +	vadc_div_half		136
> +	vadc_clk		137
> +	adc0_clk		138
> +	adc1_clk		139
> +	dac0_clk		140
> +	dac1_clk		141
> +	flexcan0_clk		142
> +	flexcan1_clk		143
> +	asrc_clk		144
> +	gpu_sw			145
> +	gpu_gate		146
> +	gpu2d_clk		147
> +
> +
> +
> +Examples:
> +
> +clks: ccm at 4006b000 {
> +	compatible = "fsl,mvf-ccm";
> +	reg = <0x4006b000 0x1000>;
> +	#clock-cells = <1>;
> +};
> +
> +uart1: serial at 40028000 { /* UART1 */
> +	compatible = "fsl,mvf-uart";
> +	reg = <0x40028000 0x1000>;
> +	interrupts = <0 62 0x04>;
> +	clocks = <&clks 35>;
> +	clock-names = "ipg";
> +};
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 78f795d..2fb9562 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -819,6 +819,21 @@ config SOC_IMX6Q
>  	help
>  	  This enables support for Freescale i.MX6 Quad processor.
>  
> +config SOC_MVF600
> +	bool "Vybrid Family MVF600 support"
> +	select CPU_V7
> +	select ARM_GIC
> +	select COMMON_CLK

This one has been select by ARCH_MULTIPLATFORM.  As IMX/MXC is part of
multiplatform build now, this select of COMMON_CLK is redundant.

> +	select CLKSRC_OF
> +	select PINCTRL
> +	select PINCTRL_MVF
> +	select PL310_ERRATA_588369 if CACHE_PL310
> +	select PL310_ERRATA_727915 if CACHE_PL310
> +	select PL310_ERRATA_769419 if CACHE_PL310
> +
> +	help
> +	  This enable support for Freescale Vybrid Family VF6xx MPU.
> +
>  endif
>  
>  source "arch/arm/mach-imx/devices/Kconfig"
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index b16eb39..76a2ead 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -112,4 +112,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
>  obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
>  obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>  
> +# Vybrid based machines

The comment is a little confusing, as "machines" means the board files
which have been replaced by device tree support.  The comment is not so
helpful anyway, so please just remove it.

> +obj-$(CONFIG_SOC_MVF600) += clk-mvf.o mach-mvf600.o pit.o
> +
>  obj-y += devices/
> diff --git a/arch/arm/mach-imx/clk-mvf.c b/arch/arm/mach-imx/clk-mvf.c
> new file mode 100644
> index 0000000..1467a304
> --- /dev/null
> +++ b/arch/arm/mach-imx/clk-mvf.c
> @@ -0,0 +1,406 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/types.h>
> +#include <linux/time.h>
> +#include <linux/hrtimer.h>
> +#include <linux/mm.h>
> +#include <linux/errno.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/clkdev.h>

Do you need this header?

> +#include <linux/regulator/consumer.h>

Ditto

> +#include <asm/div64.h>

Ditto

> +#include <linux/clk-provider.h>
> +#include <linux/clk-private.h>

Ditto

> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>

Ditto

> +
> +#include "hardware.h"

And this?  You should only include the headers that you really need.

> +#include "common.h"
> +#include "clk.h"
> +
> +
One blank line is enough.

> +#define CCM_CCR		(ccm_base + 0x00)
> +#define CCM_CSR		(ccm_base + 0x04)
> +#define CCM_CCSR		(ccm_base + 0x08)
> +#define CCM_CACRR		(ccm_base + 0x0c)
> +#define CCM_CSCMR1		(ccm_base + 0x10)
> +#define CCM_CSCDR1		(ccm_base + 0x14)
> +#define CCM_CSCDR2		(ccm_base + 0x18)
> +#define CCM_CSCDR3		(ccm_base + 0x1c)
> +#define CCM_CSCMR2		(ccm_base + 0x20)
> +#define CCM_CSCDR4		(ccm_base + 0x24)
> +#define CCM_CLPCR		(ccm_base + 0x2c)
> +#define CCM_CISR		(ccm_base + 0x30)
> +#define CCM_CIMR		(ccm_base + 0x34)
> +#define CCM_CGPR		(ccm_base + 0x3c)
> +#define CCM_CCGR0		(ccm_base + 0x40)
> +#define CCM_CCGR1		(ccm_base + 0x44)
> +#define CCM_CCGR2		(ccm_base + 0x48)
> +#define CCM_CCGR3		(ccm_base + 0x4c)
> +#define CCM_CCGR4		(ccm_base + 0x50)
> +#define CCM_CCGR5		(ccm_base + 0x54)
> +#define CCM_CCGR6		(ccm_base + 0x58)
> +#define CCM_CCGR7		(ccm_base + 0x5c)
> +#define CCM_CCGR8		(ccm_base + 0x60)
> +#define CCM_CCGR9		(ccm_base + 0x64)
> +#define CCM_CCGR10		(ccm_base + 0x68)
> +#define CCM_CCGR11		(ccm_base + 0x6C)

So I have seen both lowercase and uppercase in hex value.  Please be
consistent.  My personal taste is to use lowercase.

> +#define CCM_CMEOR0		(ccm_base + 0x70)
> +#define CCM_CMEOR1		(ccm_base + 0x74)
> +#define CCM_CMEOR2		(ccm_base + 0x78)
> +#define CCM_CMEOR3		(ccm_base + 0x7C)
> +#define CCM_CMEOR4		(ccm_base + 0x80)
> +#define CCM_CMEOR5		(ccm_base + 0x84)
> +#define CCM_CPPDSR		(ccm_base + 0x88)
> +#define CCM_CCOWR		(ccm_base + 0x8C)
> +#define CCM_CCPGR0		(ccm_base + 0x90)
> +#define CCM_CCPGR1		(ccm_base + 0x94)
> +#define CCM_CCPGR2		(ccm_base + 0x98)
> +#define CCM_CCPGR3		(ccm_base + 0x9C)
> +
> +#define CCM_CCGRx_CGn(n)		(n * 2)
> +
> +#define PFD_528SYS_BASE		(anatop_base + 0x2B0)
> +#define PFD_528_BASE		(anatop_base + 0x100)
> +#define PFD_USB_BASE		(anatop_base + 0xF0) /* pll3 pfd definition */
> +
> +
One blank line is enough.

> +static void __iomem *anatop_base;
> +static void __iomem *ccm_base;
> +
> +/* This is used multiple times */
> +static const char const *fast_clk_sel[] = { "firc", "fxosc", };
> +static const char const *slow_clk_sel[] = { "sirc_32k", "sxosc", };
> +static const char const *pll1_pfd_sel[] = {
> +	"pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4",
> +};
> +static const char const *pll2_pfd_sel[] = {
> +	"pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4",
> +};
> +static const char const *sys_clk_sel[] = {
> +	"fast_clk", "slow_clk", "pll2_sw", "pll2_main", "pll1_sw", "pll3_main",
> +};
> +static const char const *ddr_clk_sel[] = { "pll2_pfd2", "sys_clk", };
> +static const char const *rmii_clk_sel[] = {
> +	"enet_ext", "audio_ext", "enet_50m", "enet_25m",
> +};
> +static const char const *enet_ts_clk_sel[] = {
> +	"enet_ext", "fxosc", "audio_ext", "usb_clk", "enet_ts_clk", "enet_25m", "enet_50m",
> +};
> +static const char const *esai_clk_sel[] = {
> +	"audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div",
> +};
> +static const char const *sai_clk_sel[] = {
> +	"audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div",
> +};
> +static const char const *nfc_clk_sel[] = {
> +	"platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3",
> +};
> +static const char const *qspi_clk_sel[] = {
> +	"pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4",
> +};
> +static const char const *esdhc_clk_sel[] = {
> +	"pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus",
> +};
> +static const char const *dcu_clk_sel[] = { "pll1_pfd2", "pll3_main", };
> +static const char const *gpu_clk_sel[] = { "pll2_pfd2", "pll3_pfd2", };
> +static const char const *vadc_clk_sel[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
> +/* FTM counter clock source, not module clock */
> +static const char const *ftm_ext_clk_sel[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
> +static const char const *ftm_fix_clk_sel[] = { "sxosc", "ipg_bus", };
> +
> +enum mvf_clks {
> +	dummy,
> +	sirc_128k, sirc_32k, firc, sxosc, fxosc, fxosc_half,
> +	slow_clk, fast_clk, audio_ext, enet_ext,
> +	pll1_main_528m, pll1_pfd1_500m, pll1_pfd2_452m,
> +	pll1_pfd3_396m, pll1_pfd4_528m, pll2_main_528m, pll2_pfd1_500m,
> +	pll2_pfd2_396m, pll2_pfd3_339m, pll2_pfd4_413m, pll3_main_480m,
> +	pll3_pfd1_308m, pll3_pfd2_332m, pll3_pfd3_298m, pll3_pfd4_320m,
> +	pll4_main, pll5_main, pll6_main,
> +	pll3_main_div, pll4_main_div, pll6_main_div,
> +	pll1_sw, pll2_sw, sys_sw, ddr_sw,
> +	sys_bus_clk, platform_bus_clk, ipg_bus_clk,
> +	uart0_clk, uart1_clk, uart2_clk, uart3_clk, uart4_clk, uart5_clk,
> +	pit_clk,
> +	i2c0_clk, i2c1_clk, i2c2_clk, i2c3_clk,
> +	ftm0_ext_sw, ftm0_fix_sw, ftm0_ext_fix_gate,
> +	ftm1_ext_sw, ftm1_fix_sw, ftm1_ext_fix_gate,
> +	ftm2_ext_sw, ftm2_fix_sw, ftm2_ext_fix_gate,
> +	ftm3_ext_sw, ftm3_fix_sw, ftm3_ext_fix_gate,
> +	ftm0_clk, ftm1_clk, ftm2_clk, ftm3_clk,
> +	enet_50m, enet_25m, enet_clk_sw, enet_clk, enet_ts_sw, enet_ts,
> +	dspi0_clk, dspi1_clk, dspi2_clk, dspi3_clk,
> +	wdt_clk,
> +	esdhc0_sw, esdhc0_gate, esdhc0_div, esdhc0_clk,
> +	esdhc1_sw, esdhc1_gate, esdhc1_div, esdhc1_clk,
> +	dcu0_sw, dcu0_gate, dcu0_div, dcu0_clk,
> +	dcu1_sw, dcu1_gate, dcu1_div, dcu1_clk,
> +	esai_sw, esai_gate, esai_div, esai_clk,
> +	sai0_sw, sai0_gate, sai0_div, sai0_clk,
> +	sai1_sw, sai1_gate, sai1_div, sai1_clk,
> +	sai2_sw, sai2_gate, sai2_div, sai2_clk,
> +	sai3_sw, sai3_gate, sai3_div, sai3_clk,
> +	usbc0_clk, usbc1_clk,
> +	qspi0_sw, qspi0_gate, qspi0_x4_div, qspi0_x2_div, qspi0_x1_div,
> +	qspi1_sw, qspi1_gate, qspi1_x4_div, qspi1_x2_div, qspi1_x1_div,
> +	qspi0_clk, qspi1_clk,
> +	nfc_sw, nfc_gate, nfc_pre_div, nfc_frac_div, nfc_inv, nfc_clk,
> +	vadc_sw, vadc_gate, vadc_div, vadc_div_half, vadc_clk,
> +	adc0_clk, adc1_clk, dac0_clk, dac1_clk,
> +	flexcan0_clk, flexcan1_clk,
> +	asrc_clk,
> +	gpu_sw, gpu_gate, gpu2d_clk,
> +	clk_max
> +};
> +
> +static struct clk_div_table pll4_main_div_table[] = {
> +	[0] = {.val = 0, .div = 1},
> +	[1] = {.val = 1, .div = 2},
> +	[2] = {.val = 2, .div = 6},
> +	[3] = {.val = 3, .div = 8},
> +	[4] = {.val = 4, .div = 10},
> +	[5] = {.val = 5, .div = 12},
> +	[6] = {.val = 6, .div = 14},
> +	[7] = {.val = 7, .div = 16},

Per kernel doc of function clk_register_divider_table(), the
clk_div_table should end with a div set to 0.

> +};
> +static struct clk *clk[clk_max];
> +static struct clk_onecell_data clk_data;
> +
> +int __init mvf_clocks_init(void)
> +{
> +	struct device_node *np;
> +
> +	clk[dummy] = imx_clk_fixed("dummy", 0);
> +	clk[sirc_128k] = imx_clk_fixed("sirc_128k", 128000); /* slow internal IRC */
> +	clk[sirc_32k] = imx_clk_fixed("sirc_32k", 32000); /* slow internal IRC */
> +	clk[firc] = imx_clk_fixed("firc", 24000000); /* fast internal IRC */
> +	clk[sxosc] = imx_clk_fixed("sxosc", 32000); /* fixed 32k external osc */
> +
> +	for_each_compatible_node(np, NULL, "fixed-clock") {
> +		u32 rate;
> +
> +		if (of_property_read_u32(np, "clock-frequency", &rate))
> +			continue;
> +		else if (of_device_is_compatible(np, "fsl,mvf-osc"))
> +			clk[fxosc] = imx_clk_fixed("fxosc", rate);
> +		else if (of_device_is_compatible(np, "fsl,mvf-audio-ext-clk"))
> +			clk[audio_ext] = imx_clk_fixed("audio_ext", rate);
> +		else if (of_device_is_compatible(np, "fsl,mvf-enet-ext-clk"))
> +			clk[enet_ext] = imx_clk_fixed("enet_ext", rate);
> +	}
> +
> +	/* default to 24Mhz OSC */
> +	if (!clk[fxosc])
> +		clk[fxosc] = imx_clk_fixed("fxosc", 24000000);
> +
> +	clk[fxosc_half] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-anatop");
> +	anatop_base = of_iomap(np, 0);
> +	WARN_ON(!anatop_base);
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-ccm");
> +	ccm_base = of_iomap(np, 0);
> +	WARN_ON(!ccm_base);
> +
> +	clk[slow_clk] = imx_clk_mux("slow_clk", CCM_CCSR, 4, 1,
> +				slow_clk_sel, ARRAY_SIZE(slow_clk_sel));

I would suggest we name the clocks as close as how reference manual
names them.  For above example, it would be:

	clk[slow_clk_sel] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1,
				slow_clk_sels, ARRAY_SIZE(slow_clk_sels));

> +	clk[fast_clk] = imx_clk_mux("fast_clk", CCM_CCSR, 5, 1,
> +				fast_clk_sel, ARRAY_SIZE(fast_clk_sel));
> +
> +	clk[pll1_main_528m] = imx_clk_fixed_factor("pll1_main",	"fast_clk", 22, 1);
> +	clk[pll1_pfd1_500m] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_528SYS_BASE, 0);
> +	clk[pll1_pfd2_452m] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_528SYS_BASE, 1);
> +	clk[pll1_pfd3_396m] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_528SYS_BASE, 2);
> +	clk[pll1_pfd4_528m] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_528SYS_BASE, 3);
> +
> +	clk[pll2_main_528m] = imx_clk_fixed_factor("pll2_main", "fast_clk", 22, 1);
> +	clk[pll2_pfd1_500m] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_528_BASE, 0);
> +	clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_528_BASE, 1);
> +	clk[pll2_pfd3_339m] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_528_BASE, 2);
> +	clk[pll2_pfd4_413m] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_528_BASE, 3);
> +
> +	clk[pll3_main_480m] = imx_clk_fixed_factor("pll3_main", "fast_clk", 20, 1);
> +	clk[pll4_main] = imx_clk_fixed_factor("pll4_main", "fast_clk", 25, 1);
> +	/* Enet pll: fixed 50Mhz */
> +	clk[pll5_main] = imx_clk_fixed_factor("pll5_main", "fast_clk", 125, 6);
> +	clk[enet_50m] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
> +	clk[enet_25m] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
> +	/* Video pll: default 960Mhz */
> +	clk[pll6_main] = imx_clk_fixed_factor("pll6_main", "fast_clk", 40, 1);
> +	clk[pll1_sw] = imx_clk_mux("pll1_sw", CCM_CCSR, 16, 3, pll1_pfd_sel, 5);
> +	clk[pll2_sw] = imx_clk_mux("pll2_sw", CCM_CCSR, 19, 3, pll2_pfd_sel, 5);
> +	clk[sys_sw] = imx_clk_mux("sys_sw", CCM_CCSR, 0, 3, sys_clk_sel, ARRAY_SIZE(sys_clk_sel));
> +	clk[ddr_sw] = imx_clk_mux("ddr_sw", CCM_CCSR, 6, 1, ddr_clk_sel, ARRAY_SIZE(ddr_clk_sel));
> +	clk[sys_bus_clk] = imx_clk_divider("sys_bus", "sys_sw", CCM_CACRR, 0, 3);
> +	clk[platform_bus_clk] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
> +	clk[ipg_bus_clk] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
> +
> +	clk[pll3_main_div] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
> +	clk[pll4_main_div] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0,
> +			CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
> +	clk[pll6_main_div] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
> +
> +	clk[usbc0_clk] = imx_clk_gate2("usbc0_clk", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
> +	clk[usbc1_clk] = imx_clk_gate2("usbc1_clk", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
> +
> +	clk[qspi0_sw] = imx_clk_mux("qspi0_sw", CCM_CSCMR1, 22, 2, qspi_clk_sel, 4);
> +	clk[qspi0_x4_div] = imx_clk_divider("qspi0_x4", "qspi0_sw", CCM_CSCDR3, 0, 2);
> +	clk[qspi0_x2_div] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
> +	clk[qspi0_x1_div] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
> +	clk[qspi0_gate] = imx_clk_gate("qspi0_gate", "qspi0_x1", CCM_CSCDR3, 4);
> +	clk[qspi0_clk] = imx_clk_gate2("qspi0_clk", "qspi0_en", CCM_CCGR2, CCM_CCGRx_CGn(4));
> +
> +	clk[qspi1_sw] = imx_clk_mux("qspi1_sw", CCM_CSCMR1, 24, 2, qspi_clk_sel, 4);
> +	clk[qspi1_x4_div] = imx_clk_divider("qspi1_x4", "qspi1_sw", CCM_CSCDR3, 8, 2);
> +	clk[qspi1_x2_div] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
> +	clk[qspi1_x1_div] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
> +	clk[qspi1_gate] = imx_clk_gate("qspi1_gate", "qspi1_x1", CCM_CSCDR3, 12);
> +	clk[qspi1_clk] = imx_clk_gate2("qspi1_clk", "qspi1_en", CCM_CCGR8, CCM_CCGRx_CGn(4));
> +
> +	clk[enet_clk_sw] = imx_clk_mux("enet_sw", CCM_CSCMR2, 4, 2, rmii_clk_sel, 4);
> +	clk[enet_ts_sw] = imx_clk_mux("enet_ts_sw", CCM_CSCMR2, 0, 3, enet_ts_clk_sel, 7);
> +	clk[enet_clk] = imx_clk_gate("enet_clk", "enet_sw", CCM_CSCDR1, 24);
> +	clk[enet_ts] = imx_clk_gate("enet_ts_clk", "enet_ts_sw", CCM_CSCDR1, 23);
> +
> +	clk[pit_clk] = imx_clk_gate2("pit_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
> +
> +	clk[uart0_clk] = imx_clk_gate2("uart0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
> +	clk[uart1_clk] = imx_clk_gate2("uart1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
> +	clk[uart2_clk] = imx_clk_gate2("uart2_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
> +	clk[uart3_clk] = imx_clk_gate2("uart3_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
> +
> +	clk[i2c0_clk] = imx_clk_gate2("i2c0_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
> +	clk[i2c1_clk] = imx_clk_gate2("i2c1_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
> +
> +	clk[dspi0_clk] = imx_clk_gate2("dspi0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
> +	clk[dspi1_clk] = imx_clk_gate2("dspi1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
> +	clk[dspi2_clk] = imx_clk_gate2("dspi2_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
> +	clk[dspi3_clk] = imx_clk_gate2("dspi3_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
> +
> +	clk[wdt_clk] = imx_clk_gate2("wdt_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
> +
> +	clk[esdhc0_sw] = imx_clk_mux("esdhc0_sw", CCM_CSCMR1, 16, 2, esdhc_clk_sel, 4);
> +	clk[esdhc0_gate] = imx_clk_gate("esdhc0_gate", "esdhc0_sw", CCM_CSCDR2, 28);
> +	clk[esdhc0_div] = imx_clk_divider("esdhc0_div", "esdhc0_gate", CCM_CSCDR2, 16, 4);
> +	clk[esdhc0_clk] = imx_clk_gate2("eshc0_clk", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
> +
> +	clk[esdhc1_sw] = imx_clk_mux("esdhc1_sw", CCM_CSCMR1, 18, 2, esdhc_clk_sel, 4);
> +	clk[esdhc1_gate] = imx_clk_gate("esdhc1_gate", "esdhc1_sw", CCM_CSCDR2, 29);
> +	clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc1_gate", CCM_CSCDR2, 20, 4);
> +	clk[esdhc1_clk] = imx_clk_gate2("eshc1_clk", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
> +
> +	/*
> +	 * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
> +	 * selectable clock source, both use a common gate bit
> +	 * in CCM_CSCDR1, select "dummy" as "ftm0_ext_fix_gate"
> +	 * parent make the gate doesn't provids any clock freq
> +	 * except for gate/ungate.
> +	 */
> +	clk[ftm0_ext_sw] = imx_clk_mux("ftm0_ext_sw", CCM_CSCMR2, 6, 2, ftm_ext_clk_sel, 4);
> +	clk[ftm0_fix_sw] = imx_clk_mux("ftm0_fix_sw", CCM_CSCMR2, 14, 1, ftm_fix_clk_sel, 2);
> +	clk[ftm0_ext_fix_gate] = imx_clk_gate("ftm0_ext_fix_gate", "dummy", CCM_CSCDR1, 25);
> +	/* ftm(n)_clk are FTM module operation clock */
> +	clk[ftm0_clk] = imx_clk_gate2("ftm0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
> +	clk[ftm1_clk] = imx_clk_gate2("ftm1_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
> +	clk[ftm2_clk] = imx_clk_gate2("ftm2_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
> +	clk[ftm3_clk] = imx_clk_gate2("ftm3_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
> +
> +	clk[dcu0_sw] = imx_clk_mux("dcu0_sw", CCM_CSCMR1, 28, 1, dcu_clk_sel, 2);
> +	clk[dcu0_gate] = imx_clk_gate("dcu0_gate", "dcu0_sw", CCM_CSCDR3, 19);
> +	clk[dcu0_div] = imx_clk_divider("dcu0_div", "dcu0_gate", CCM_CSCDR3, 16, 3);
> +	clk[dcu0_clk] = imx_clk_gate2("dcu0_clk", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
> +	clk[dcu1_sw] = imx_clk_mux("dcu1_sw", CCM_CSCMR1, 29, 1, dcu_clk_sel, 2);
> +	clk[dcu1_gate] = imx_clk_gate("dcu1_gate", "dcu1_sw", CCM_CSCDR3, 23);
> +	clk[dcu1_div] = imx_clk_divider("dcu1_div", "dcu1_gate", CCM_CSCDR3, 20, 3);
> +	clk[dcu1_clk] = imx_clk_gate2("dcu1_clk", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
> +
> +	clk[esai_sw] = imx_clk_mux("esai_sw", CCM_CSCMR1, 20, 2, esai_clk_sel, 4);
> +	clk[esai_gate] = imx_clk_gate("esai_gate", "esai_sw", CCM_CSCDR2, 30);
> +	clk[esai_div] = imx_clk_divider("esai_div", "esai_gate", CCM_CSCDR2, 24, 4);
> +	clk[esai_clk] = imx_clk_gate2("esai_clk", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
> +
> +	clk[sai0_sw] = imx_clk_mux("sai0_sw", CCM_CSCMR1, 0, 2, sai_clk_sel, 4);
> +	clk[sai0_gate] = imx_clk_gate("sai0_gate", "sai0_sw", CCM_CSCDR1, 16);
> +	clk[sai0_div] = imx_clk_divider("sai0_div", "sai0_gate", CCM_CSCDR1, 0, 4);
> +	clk[sai0_clk] = imx_clk_gate2("sai0_clk", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
> +
> +	clk[sai1_sw] = imx_clk_mux("sai1_sw", CCM_CSCMR1, 2, 2, sai_clk_sel, 4);
> +	clk[sai1_gate] = imx_clk_gate("sai1_gate", "sai1_sw", CCM_CSCDR1, 17);
> +	clk[sai1_div] = imx_clk_divider("sai1_div", "sai1_gate", CCM_CSCDR1, 4, 4);
> +	clk[sai1_clk] = imx_clk_gate2("sai1_clk", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
> +
> +	clk[sai2_sw] = imx_clk_mux("sai2_sw", CCM_CSCMR1, 4, 2, sai_clk_sel, 4);
> +	clk[sai2_gate] = imx_clk_gate("sai2_gate", "sai2_sw", CCM_CSCDR1, 18);
> +	clk[sai2_div] = imx_clk_divider("sai2_div", "sai2_gate", CCM_CSCDR1, 8, 4);
> +	clk[sai2_clk] = imx_clk_gate2("sai2_clk", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
> +
> +	clk[sai3_sw] = imx_clk_mux("sai3_sw", CCM_CSCMR1, 6, 2, sai_clk_sel, 4);
> +	clk[sai3_gate] = imx_clk_gate("sai3_gate", "sai3_sw", CCM_CSCDR1, 19);
> +	clk[sai3_div] = imx_clk_divider("sai3_div", "sai3_gate", CCM_CSCDR1, 12, 4);
> +	clk[sai3_clk] = imx_clk_gate2("sai3_clk", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
> +
> +	clk[nfc_sw] = imx_clk_mux("nfc_sw", CCM_CSCMR1, 12, 2, nfc_clk_sel, 4);
> +	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_sw", CCM_CSCDR2, 9);
> +	clk[nfc_pre_div] = imx_clk_divider("nfc_pre_div", "nfc_gate", CCM_CSCDR3, 13, 3);
> +	clk[nfc_frac_div] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
> +	clk[nfc_clk] = imx_clk_gate2("nfc_clk", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
> +
> +	clk[gpu_sw] = imx_clk_mux("gpu_sw", CCM_CSCMR1, 14, 1, gpu_clk_sel, 2);
> +	clk[gpu_gate] = imx_clk_gate("gpu_gate", "gpu_sw", CCM_CSCDR2, 10);
> +	clk[gpu2d_clk] = imx_clk_gate2("gpu_clk", "gpu_gate", CCM_CCGR8, CCM_CCGRx_CGn(15));
> +
> +	clk[vadc_sw] = imx_clk_mux("vadc_sw", CCM_CSCMR1, 8, 2, vadc_clk_sel, 3);
> +	clk[vadc_gate] = imx_clk_gate("vadc_gate", "vadc_sw", CCM_CSCDR1, 22);
> +	clk[vadc_div] = imx_clk_divider("vadc_div", "vadc_gate", CCM_CSCDR1, 20, 2);
> +	clk[vadc_div_half] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
> +	clk[vadc_clk] = imx_clk_gate2("vadc_clk", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
> +
> +	clk[adc0_clk] = imx_clk_gate2("adc0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
> +	clk[adc1_clk] = imx_clk_gate2("adc1_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
> +	clk[dac0_clk] = imx_clk_gate2("dac0_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
> +	clk[dac1_clk] = imx_clk_gate2("dac1_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
> +
> +	clk[asrc_clk] = imx_clk_gate2("asrc_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
> +
> +	clk[flexcan0_clk] = imx_clk_gate2("flexcan0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
> +	clk[flexcan1_clk] = imx_clk_gate2("flexcan1_clk", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
> +
> +	clk_set_parent(clk[qspi0_sw], clk[pll1_pfd4_528m]);
> +	clk_set_rate(clk[qspi0_x4_div],	clk_get_rate(clk[qspi0_x4_div]->parent) / 2);
> +	clk_set_rate(clk[qspi0_x2_div],	clk_get_rate(clk[qspi0_x2_div]->parent) / 2);
> +	clk_set_rate(clk[qspi0_x1_div],	clk_get_rate(clk[qspi0_x1_div]->parent) / 2);
> +
> +	clk_set_parent(clk[qspi1_sw], clk[pll1_pfd4_528m]);
> +	clk_set_rate(clk[qspi1_x4_div], clk_get_rate(clk[qspi1_x4_div]->parent) / 2);
> +	clk_set_rate(clk[qspi1_x2_div], clk_get_rate(clk[qspi1_x2_div]->parent) / 2);
> +	clk_set_rate(clk[qspi1_x1_div], clk_get_rate(clk[qspi1_x1_div]->parent) / 2);
> +
> +	clk_set_parent(clk[sai0_gate], clk[audio_ext]);
> +	clk_set_parent(clk[sai1_gate], clk[audio_ext]);
> +	clk_set_parent(clk[sai2_gate], clk[audio_ext]);
> +	clk_set_parent(clk[sai3_gate], clk[audio_ext]);
> +
> +	/* Add the clocks to provider list */
> +	clk_data.clks = clk;
> +	clk_data.clk_num = ARRAY_SIZE(clk);
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +
> +	return 0;
> +}
> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index 4cba7db..683c4f4 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -68,6 +68,7 @@ extern int mx31_clocks_init_dt(void);
>  extern int mx51_clocks_init_dt(void);
>  extern int mx53_clocks_init_dt(void);
>  extern int mx6q_clocks_init(void);
> +extern int mvf_clocks_init(void);
>  extern struct platform_device *mxc_register_gpio(char *name, int id,
>  	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
>  extern void mxc_set_cpu_type(unsigned int type);
> diff --git a/arch/arm/mach-imx/mach-mvf600.c b/arch/arm/mach-imx/mach-mvf600.c
> new file mode 100644
> index 0000000..56d3fb0
> --- /dev/null
> +++ b/arch/arm/mach-imx/mach-mvf600.c
> @@ -0,0 +1,118 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/types.h>
> +#include <linux/sched.h>
> +#include <linux/delay.h>
> +#include <linux/pm.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/init.h>
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clocksource.h>
> +#include <linux/platform_device.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqchip/arm-gic.h>
> +#include <asm/memory.h>
> +#include <asm/irq.h>
> +#include <asm/setup.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <asm/hardware/cache-l2x0.h>
> +#include <asm/system_misc.h>

Please check if you really need all these headers.

> +
> +#include "common.h"
> +
> +
> +void mvf_restart(char mode, const char *cmd)
> +{
> +	struct device_node *np;
> +	void __iomem *wdog_base;
> +	struct clk *wdog_clk;
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt");
> +	wdog_base = of_iomap(np, 0);
> +	if (!wdog_base)
> +		goto soft;
> +
> +	wdog_clk = of_clk_get_by_name(np, "wdog");
> +	if (!IS_ERR(wdog_clk))
> +		clk_prepare_enable(wdog_clk);
> +
> +	/* enable wdog */
> +	writew_relaxed(1 << 2, wdog_base);
> +
> +	/* wait for reset to assert ... */
> +	mdelay(500);
> +
> +	pr_err("Watchdog reset failed to assert reset\n");
> +
> +	/* delay to allow the serial port to show the message */
> +	mdelay(50);
> +
> +soft:
> +	/* we'll take a jump through zero as a poor second */
> +	soft_restart(0);
> +}

If mvf600 uses the same wdt IP block as imx, we should make this restart
routine a common function to be used on mvf600, imx6q and imx6sl etc.

> +
> +static void __init mvf_init_machine(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
> +
> +static void __init mvf_of_init_irq(void)

MVF is a DT/OF only platform, so name mvf_init_irq is just good.

> +{
> +	struct device_node *np;
> +	void __iomem *mscm_base;
> +	int i;
> +
> +	l2x0_of_init(0, ~0UL);
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-mscm");
> +	mscm_base = of_iomap(np, 0);
> +	if (!mscm_base)
> +		return;
> +
> +	/* route each shared peripheral interrupt to CP0 */
> +	for (i = 0; i < 111; i++)
> +		__raw_writew(1, mscm_base + 0x880 + 2 * i);
> +
> +	iounmap(mscm_base);
> +
> +	irqchip_init();
> +}
> +
> +static void __init mvf_timer_init(void)
> +{
> +	mvf_clocks_init();
> +	clocksource_of_init();
> +}
> +
> +/*
> + * initialize __mach_desc_ data structure.
> + */

The comment does not help too much.

> +static const char *mvf_dt_compat[] __initdata = {
> +	"fsl,mvf600",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid Family (Device Tree)")

The string should specify a SoC rather than a Family.

> +	.init_irq	= mvf_of_init_irq,
> +	.init_machine	= mvf_init_machine,
> +	.init_time	= mvf_timer_init,

We generally sort these hooks in the sequence of call time.  That said,
the .init_time should be put before .init_machine.

Shawn

> +	.dt_compat	= mvf_dt_compat,
> +	.restart	= mvf_restart,
> +MACHINE_END
> diff --git a/arch/arm/mach-imx/pit.c b/arch/arm/mach-imx/pit.c
> new file mode 100644
> index 0000000..e2df0e5
> --- /dev/null
> +++ b/arch/arm/mach-imx/pit.c
> @@ -0,0 +1,244 @@
> +/*
> + *  Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/clockchips.h>
> +#include <linux/clocksource.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <asm/mach/time.h>
> +#include <asm/sched_clock.h>
> +
> +
> +#define PITMCR		0x00
> +#define PITLTMR64H	0xE0
> +#define PITLTMR64L	0xE4
> +
> +#define PITLDVAL	0x00
> +#define PITCVAL		0x04
> +#define PITTCTRL	0x08
> +#define PITTFLG		0x0C
> +
> +/*
> + * Vybrid has 8 pit timers: pit0 - pit7,
> + * Each memory mapped register occupy 0x10 Bytes
> + */
> +#define PITOFFSET0	0x100
> +#define PITOFFSETx(n)	(PITOFFSET0 + 0x10 * n)
> +
> +/* bit definitation */
> +#define PITMCR_MDIS		(1 << 1)
> +#define PITMCR_FRZ		(1 << 0)
> +
> +#define PITTCTRL_TEN		(1 << 0)
> +#define PITTCTRL_TIE		(1 << 1)
> +#define	PITCTRL_CHN		(1 << 2)
> +
> +#define PITTFLG_TIF		0x1
> +
> +static struct clock_event_device clockevent_pit;
> +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
> +
> +static void __iomem *clksrc_base;
> +static void __iomem *clkevt_base;
> +static void __iomem *sched_clock_reg;
> +static unsigned long pit_cycle_per_jiffy;
> +
> +static inline void pit_timer_enable(void)
> +{
> +	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_timer_disable(void)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_disable(void)
> +{
> +	unsigned long val;
> +
> +	val = __raw_readl(clkevt_base + PITTCTRL);
> +	val &= ~PITTCTRL_TIE;
> +	__raw_writel(val, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_enable(void)
> +{
> +	unsigned long val;
> +
> +	val = __raw_readl(clkevt_base + PITTCTRL);
> +	val |= PITTCTRL_TIE;
> +	__raw_writel(val, clkevt_base + PITTCTRL);
> +}
> +
> +static void pit_irq_acknowledge(void)
> +{
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +}
> +
> +static unsigned int mvf_read_sched_clock(void)
> +{
> +	return __raw_readl(sched_clock_reg);
> +}
> +
> +
> +static int __init pit_clocksource_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	sched_clock_reg = clksrc_base + PITCVAL;
> +
> +	setup_sched_clock(mvf_read_sched_clock, 32, c);
> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, 32,
> +			clocksource_mmio_readl_down);
> +}
> +
> +/* set clock event */
> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_irq_acknowledge();
> +	pit_timer_enable();
> +
> +	return 0;
> +}
> +
> +static void pit_set_mode(enum clock_event_mode mode,
> +				struct clock_event_device *evt)
> +{
> +	unsigned long flags;
> +
> +	local_irq_save(flags);
> +
> +	pit_timer_disable();
> +	pit_irq_acknowledge();
> +
> +	/* Remember timer mode */
> +	clockevent_mode = mode;
> +	local_irq_restore(flags);
> +
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +
> +		__raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
> +		pit_timer_enable();
> +
> +		break;
> +	case CLOCK_EVT_MODE_ONESHOT:
> +
> +		break;
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_RESUME:
> +
> +		break;
> +	default:
> +		WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
> +		break;
> +	}
> +}
> +
> +/*
> + * interrupt handler for the timer
> + */
> +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = &clockevent_pit;
> +
> +	pit_irq_acknowledge();
> +
> +	if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT)
> +		pit_timer_disable();
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction pit_timer_irq = {
> +	.name		= "MVF PIT Timer Tick",
> +	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= pit_timer_interrupt,
> +};
> +
> +static struct clock_event_device clockevent_pit = {
> +	.name		= "pit",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= pit_set_mode,
> +	.set_next_event	= pit_set_next_event,
> +	.rating		= 300,
> +};
> +
> +static int __init pit_clockevent_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	clockevent_pit.cpumask = cpumask_of(0);
> +	clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00);
> +
> +	return 0;
> +}
> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	int irq;
> +
> +	if (!np) {
> +		pr_err("Failed to find pit DT node\n");
> +		BUG();
> +	}
> +
> +	timer_base = of_iomap(np, 0);
> +	WARN_ON(!timer_base);
> +
> +	/* chose PIT2 as clocksource, PIT3 as clockevent dev */
> +	clksrc_base = timer_base + PITOFFSETx(2);
> +	clkevt_base = timer_base + PITOFFSETx(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +
> +	pit_clk = of_clk_get_by_name(np, "pit");
> +	if (IS_ERR(pit_clk)) {
> +		pr_err("Vybrid PIT timer: unable to get clk\n");
> +		return;
> +	}
> +
> +	clk_prepare_enable(pit_clk);
> +
> +	pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
> +
> +	/*
> +	 * Initialise to a known state (all timers off, and timing reset)
> +	 */
> +	__raw_writel(0x0, timer_base + PITMCR);
> +
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +	__raw_writel(0xffffffff, clkevt_base + PITLDVAL);
> +
> +	__raw_writel(0, clksrc_base + PITTCTRL);
> +	__raw_writel(0xffffffff, clksrc_base + PITLDVAL);
> +	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
> +
> +	pit_clocksource_init(pit_clk);
> +
> +	setup_irq(irq, &pit_timer_irq);
> +
> +	pit_clockevent_init(pit_clk);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf-pit", pit_timer_init);
> -- 
> 1.8.0
> 
> 



From shawn.guo at linaro.org  Fri May  3 03:57:49 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 15:57:49 +0800
Subject: [PATCH 4/5] ARM: dts: add device tree source for imx6sl SoC
In-Reply-To: <5183589A.5090109@de.bosch.com>
References: <1367552995-31777-1-git-send-email-shawn.guo@linaro.org>
 <1367552995-31777-5-git-send-email-shawn.guo@linaro.org>
 <5183589A.5090109@de.bosch.com>
Message-ID: <20130503075747.GB31873@S2101-09.ap.freescale.net>

On Fri, May 03, 2013 at 08:26:34AM +0200, Dirk Behme wrote:
> On 03.05.2013 05:49, Shawn Guo wrote:
> >Add SoC level device tree source for imx6sl.
> >
> >Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> >---
> >  arch/arm/boot/dts/imx6sl.dtsi |  777 +++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 777 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx6sl.dtsi
> >
> >diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> >new file mode 100644
> 
> Just as a proposal do discuss: What's about to move the existing
> imx6qdl.dtsi to a imx6.dtsi and include it in
> 
> imx6q.dtsi
> imx6dl.dtsi
> imx6sl.dtsi
> 
No.  Doing that would mean we need to do another around of shuffling of
all imx6 dts files with one more common level added.  And it brings even
more churn than last time when we add imx6dl support, since we have more
stuff to move around for getting 3 common levels.  Comparing
imx6qdl.dtsi and imx6sl.dtsi, you will find that the effort is not
really worthy, because there are already enough differences there.

> then?
> 
> >+       soc {
> >+               #address-cells = <1>;
> >+               #size-cells = <1>;
> >+               compatible = "simple-bus";
> >+               interrupt-parent = <&intc>;
> >+               ranges;
> >+
> >+               L2: l2-cache at 00a02000 {
> >+                       compatible = "arm,pl310-cache";
> >+                       reg = <0x00a02000 0x1000>;
> >+                       interrupts = <0 92 0x04>;
> >+                       cache-unified;
> >+                       cache-level = <2>;
> >+               };
> The arm,tag-latency and arm,data-latency we recently added for the
> other SoCs are missing here?

Right, I will add it.

Shawn



From lee.jones at linaro.org  Fri May  3 04:01:25 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 09:01:25 +0100
Subject: [PATCH 0/5] various ab8500 fixes
In-Reply-To: <1366978638-967-1-git-send-email-fabio.baltieri@linaro.org>
References: <1366978638-967-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <20130503080125.GC24153@gmail.com>

On Fri, 26 Apr 2013, Fabio Baltieri wrote:

> Hi Samuel,
> 
> this series contains various fixes I found on the current -next ab8500
> driver(s).
> 
> Patches 1 and 2 are just sparse warning, patch 3 drops reference to a
> superseeded driver and last two makes ab8500-sysctrl works again without
> an explicit ab8500->sysctrl defined, as it is in current kernel.
> 
> Thanks,
> Fabio
> 
> 
> Fabio Baltieri (5):
>   mfd: abx500-core: fix sparse warning
>   mfd: ab8500-sysctrl: fix sparse warning
>   mfd: ab8500: drop references to ab8500-leds
>   mfd: ab8500-sysctrl: set sysctrl_dev during probe
>   mfd: ab8500-sysctrl: let sysctrl driver work without pdata

I have a really petty point:

Try and keep to the $SUBJECT line conventions which are preferred by
each subsystem maintainer. Linus Walleij tends to prefer the scheme
you've used above, but Sam likes the description to start with an
uppercase character. No biggy, I'll just fix that up for you.

>  drivers/mfd/ab8500-core.c    | 13 -------------
>  drivers/mfd/ab8500-sysctrl.c |  9 +++++----
>  drivers/mfd/abx500-core.c    |  2 +-
>  3 files changed, 6 insertions(+), 18 deletions(-)

All patches applied. Thanks Fabio.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From ulf.hansson at linaro.org  Fri May  3 04:01:53 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Fri, 3 May 2013 10:01:53 +0200
Subject: [PATCH 3/4] mmc: mmci: Ensure return value of regulator_enable()
 is checked
In-Reply-To: <1367509690-24022-4-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CAPDyKFr60-nuh-BFsWtFhNeqUmswKC4hL4mw-gDhiqLmarvEDA@mail.gmail.com>

On 2 May 2013 17:48, Lee Jones <lee.jones at linaro.org> wrote:
> This patch suppresses the warning below:
>
> drivers/mmc/host/mmci.c: In function ?mmci_set_ios?:
> drivers/mmc/host/mmci.c:1165:20: warning: ignoring return value of
>         ?regulator_enable?, declared with attribute warn_unused_result
>         [-Wunused-result]
>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Chris Ball <cjb at laptop.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/mmc/host/mmci.c |    9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 375c109..f4f3038 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -1130,6 +1130,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>         struct variant_data *variant = host->variant;
>         u32 pwr = 0;
>         unsigned long flags;
> +       int ret;
>
>         pm_runtime_get_sync(mmc_dev(mmc));
>
> @@ -1161,8 +1162,12 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>                 break;
>         case MMC_POWER_ON:
>                 if (!IS_ERR(mmc->supply.vqmmc) &&
> -                   !regulator_is_enabled(mmc->supply.vqmmc))

I realize that we actually have a bug here (and in the MMC_POWER_OFF
mode as well).

We shall not use regulator_is_enabled API as a trigger to enable/fetch
a reference to the regulator, since it will only tell us if the
regulator is enabled - hw wise.
Instead we need a local variable in the mmci host struct keeping track
if we have enabled the regulator. Do you mind fix this up in this
patch as well since it is tightly coupled to the regulator handling!?

Otherwise it looks good to me.

Kind regards
Ulf Hansson

> -                       regulator_enable(mmc->supply.vqmmc);
> +                   !regulator_is_enabled(mmc->supply.vqmmc)) {
> +                       ret = regulator_enable(mmc->supply.vqmmc);
> +                       if (ret < 0)
> +                               dev_err(mmc_dev(mmc),
> +                                       "failed to enable vqmmc regulator\n");
> +               }
>
>                 pwr |= MCI_PWR_ON;
>                 break;
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


From linus.walleij at linaro.org  Fri May  3 04:01:59 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 10:01:59 +0200
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <201305021939.48381.arnd@arndb.de>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
 <201305021821.12008.arnd@arndb.de>
 <CACRpkdayJCm-PcY_=+NDraEPn0m6BrjNRH+tYp3Abar43RamaA@mail.gmail.com>
 <201305021939.48381.arnd@arndb.de>
Message-ID: <CACRpkdZHRQqd277Qv8O0dek_jYb=eewhpLYfKtip-YLYx_ukUA@mail.gmail.com>

On Thu, May 2, 2013 at 7:39 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 02 May 2013, Linus Walleij wrote:
>> > How do those drivers get to the SYSCON base address? Should they
>> > be using drivers/mfd/syscon.c as the multiplexor instead?
>>
>> No, there is no mutex to be taken. The consecutive range of memory
>> addresses are used by different things (mainly the clocks) but there
>> is no register that needs to be protected against access from two
>> subsystems simultaneously.
>>
>> As a follow-up to this series I plan to move also the U300 clocks
>> to the device tree (similar three-step ladder as used for the Nomadik)
>> and then they will (hopefully) get the syscon base address from the
>> device tree.
>
> I was less worried about mutexes than a correct representation
> in the device tree. With the syscon driver, you can have the
> register ranges described exactly once and just use the offsets
> on the regmap in the other drivers.

Hm. This sounds a bit like modeling the Linux subsystems after
the needs of the device tree rather than keeping these two as
separate concepts.

It is true however that the same register base will appear twice:
once for the clk driver, and once for the syscon, which is not
yet in the device tree.

The system controllers on several systems typically share this
aspect.

For the DBx500 PRCMU we have solved the case where the pinctrl
is using a few registers inside the PRCMU range like this:

pinctrl {
        compatible = "stericsson,nmk-pinctrl";
        prcm = <&prcmu>;
};

prcmu: prcmu at 80157000 {
        compatible = "stericsson,db8500-prcmu";
        reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
        (...)
};

Then in the code:

if (np) {
        prcm_np = of_parse_phandle(np, "prcm", 0);
        if (prcm_np)
                npct->prcm_base = of_iomap(prcm_np, 0);
}

I could do something similar by creating a U300 syscon node
and referring to it from the clk node, so the clk looks up its
syscon to find the base.

If so, I can build this on top of the current patch series
with multiplatform and all, as I convert the clocks to DT
(which is the next and final step).

Yours,
Linus Walleij


From shc_work at mail.ru  Fri May  3 04:08:21 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Fri,  3 May 2013 12:08:21 +0400
Subject: [PATCH v2] ARM: dts: Add SPI support for i.MX27 Phytec PCM038 module
Message-ID: <1367568501-29467-1-git-send-email-shc_work@mail.ru>

Added SPI node and PMIC MC13783 (spi0.0) to imx27-phytec-phycore DT file.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/boot/dts/imx27-phytec-phycore.dts | 109 +++++++++++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index fe64e3a..eb7d9fa 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -72,6 +72,115 @@
 	};
 };
 
+&cspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 28 0>;
+	status = "okay";
+
+	pmic: mc13783 at 0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,mc13783";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <23 0x4>;
+		fsl,mc13xxx-uses-adc;
+		fsl,mc13xxx-uses-rtc;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			sw1b_reg: sw1b {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			sw2a_reg: sw2a {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			sw2b_reg: sw2b {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			sw3_reg: sw3 {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vaudio_reg: vaudio {
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			violo_reg: violo {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			viohi_reg: viohi {
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vgen_reg: vgen {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcam_reg: vcam {
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+
+			vrf1_reg: vrf1 {
+				regulator-min-microvolt = <2775000>;
+				regulator-max-microvolt = <2775000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vrf2_reg: vrf2 {
+				regulator-min-microvolt = <2775000>;
+				regulator-max-microvolt = <2775000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vmmc1_reg: vmmc1 {
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			gpo1_reg: gpo1 { };
+
+			pwgt1spi_reg: pwgt1spi {
+				regulator-always-on;
+			};
+		};
+	};
+};
+
 &nfc {
 	nand-bus-width = <8>;
 	nand-ecc-mode = "hw";
-- 
1.8.1.5



From linus.walleij at linaro.org  Fri May  3 04:14:28 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 10:14:28 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <1367528578-518090-10-git-send-email-arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-10-git-send-email-arnd@arndb.de>
Message-ID: <CACRpkdY+5gdh1G7N+_Spg=iNZ0QMZ=ZXuhsVPuMEt62NxPhRxA@mail.gmail.com>

On Thu, May 2, 2013 at 11:02 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> The use of 'select' in the ux500 platform is a huge mess, we should
> not be selecting most of the drivers that are currently selected
> there, but rather enable them from the defconfig.
>
> As a fixup for 3.10, let's at least select the dependencies for
> the other drivers we already select, to make it consistent.
>
> warning: (UX500_SOC_COMMON) selects AB8500_CORE which has unmet direct dependencies (HAS_IOMEM && GENERIC_HARDIRQS && ABX500_CORE && MFD_DB8500_PRCMU)
>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

I do not necessarily agree with this commit message.

The only mess I see is that this very patch is missing...

If we look at this:

config UX500_SOC_DB8500
        bool
        select CPU_FREQ_TABLE if CPU_FREQ
        select MFD_DB8500_PRCMU
        select PINCTRL_DB8500
        select PINCTRL_DB8540
        select PINCTRL_AB8500
        select PINCTRL_AB8505
        select PINCTRL_AB9540
        select PINCTRL_AB8540
        select REGULATOR
        select REGULATOR_DB8500_PRCMU

The PRCMU, the PINCTRL drivers, and the PRCMU regulators
are necessary to boot the system correctly, by which I mean
necessary so as not to cause potential damage to the hardware.

The PRCMU is a system controller without which the system
cannot really be brought up, and the ABx500's are the PMICs
which are developed in pair with the SoC and they are in practice
Siamese twins, there is no chance you can build a Ux500 system
without both of them. It just won't even start. There are deep
dependencies between the PRCMU and the ABx500, as the
PRCMU firmware will talk directly to the ABx500 without the
kernel intervening. I.e. the whole set of hardware has to be
there.

While I understand that from a compile-time point of view it does
not seem nice, and all things would be separate units that you
plug in, from a run-time and system architecture point of view it
makes a lot of sense to select these. Worlds collide...

Apart from that:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Fri May  3 04:15:10 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 09:15:10 +0100
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503061931.GB27451@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
Message-ID: <20130503081510.GG21614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 09:21:51AM +0300, Felipe Balbi wrote:
> Hi,
> 
> On Fri, May 03, 2013 at 12:13:53AM +0100, Russell King - ARM Linux wrote:
> > > > > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > > > > ---
> > > > > >  arch/arm/mach-omap2/usb-host.c | 21 +++++++++++++++++----
> > > > > >  1 file changed, 17 insertions(+), 4 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> > > > > > index aa27d7f..8d17a0d 100644
> > > > > > --- a/arch/arm/mach-omap2/usb-host.c
> > > > > > +++ b/arch/arm/mach-omap2/usb-host.c
> > > > > > @@ -570,8 +570,10 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > > > >  	supplies->dev_name = dev_id;
> > > > > >  
> > > > > >  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
> > > > > > -	if (!reg_data)
> > > > > > +	if (!reg_data) {
> > > > > > +		kfree(supplies);
> > > > > >  		return -ENOMEM;
> > > > > > +	}
> > > > > >  
> > > > > >  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
> > > > > >  	reg_data->consumer_supplies = supplies;
> > > > > > @@ -579,8 +581,11 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > > > >  
> > > > > >  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
> > > > > >  			GFP_KERNEL);
> > > > > > -	if (!config)
> > > > > > +	if (!config) {
> > > > > > +		kfree(supplies);
> > > > > > +		kfree(reg_data);
> > > > > >  		return -ENOMEM;
> > > > > > +	}
> > > > > >  
> > > > > >  	config->supply_name = name;
> > > > > >  	config->gpio = gpio;
> > > > > > @@ -589,17 +594,25 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
> > > > > >  
> > > > > >  	/* create a regulator device */
> > > > > >  	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> > > > > > -	if (!pdev)
> > > > > > +	if (!pdev) {
> > > > > > +		kfree(supplies);
> > > > > > +		kfree(reg_data);
> > > > > > +		kfree(config);
> > > > > >  		return -ENOMEM;
> > > > > > +	}
> > > > > >  
> > > > > >  	pdev->id = PLATFORM_DEVID_AUTO;
> > > > > >  	pdev->name = reg_name;
> > > > > >  	pdev->dev.platform_data = config;
> > > > > >  
> > > > > >  	ret = platform_device_register(pdev);
> > > > > > -	if (ret)
> > > > > > +	if (ret) {
> > > > > >  		pr_err("%s: Failed registering regulator %s for %s\n",
> > > > > >  				__func__, name, dev_id);
> > > > > > +		kfree(supplies);
> > > > > > +		kfree(reg_data);
> > > > > > +		kfree(config);
> > > > > > +	}
> > > > > 
> > > > > Might be better to switch to devm_XXX managed functions?
> > > 
> > > I don't think it makes sense since the platform_device hasn't been
> > > registered yet.
> > > 
> > > Still, patch can be improved with proper goto labels instead of
> > > sprinkling different kfree() calls in every single error branch.
> > > 
> > > > If anyone can rewrite driver to use devm_xx, it would have been better.
> > > > I'm not going to redo the patch yet, let it be so, I just showed a point
> > > > for OMAP-developers.
> > > 
> > > fair enough.
> > 
> > Well, as long as this crap violates the driver model by using kfree() on
> > a device...  Devices are refcounted and must only be freed when the
> > refcount drops to zero.
> 
> read the patch again, there's no kfree() on any device. There is a kfree
> of supplies, reg_data and config.
> 
> On top of that, the code being changed here doesn't even exist, so I
> wonder which tree is this code based off. usb-host.c has always being
> using omap_device_build() which internally calls
> platform_device_alloc().
> 
> > This is exactly why we have platform_device_alloc(),
> > platform_device_register_full() and friends - so that people don't have to
> > fsck around with kzalloc themselves and get it wrong like the above does.
> > 
> > Would you like me to pass your details to gregkh for another one of his
> > public humilation exercises over basic kernel programming stuff? :)
> 
> How about we pass yours for not reading the patch before flaming ? Note
> that $SUBJECT is *not* touching at all that line which kzallocs a
> platform_device. Wrong as it is, it's not part of $SUBJECT.

It's really simple.  You do not use k*alloc with platform devices.  And
you reject any patch which contains that, and point it out to the patch
author.

It really doesn't matter if there's a kfree or not.  The fact is you do
not allow it in any situation, because such bad practises get copied
and then you end up with kfree's.

How about you gain an understanding of this stuff and why this stuff is
soo "hot".


From lee.jones at linaro.org  Fri May  3 04:16:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 09:16:33 +0100
Subject: [PATCH 3/4] mmc: mmci: Ensure return value of regulator_enable()
 is checked
In-Reply-To: <CAPDyKFr60-nuh-BFsWtFhNeqUmswKC4hL4mw-gDhiqLmarvEDA@mail.gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-4-git-send-email-lee.jones@linaro.org>
 <CAPDyKFr60-nuh-BFsWtFhNeqUmswKC4hL4mw-gDhiqLmarvEDA@mail.gmail.com>
Message-ID: <20130503081633.GD24153@gmail.com>

On Fri, 03 May 2013, Ulf Hansson wrote:

> On 2 May 2013 17:48, Lee Jones <lee.jones at linaro.org> wrote:
> > This patch suppresses the warning below:
> >
> > drivers/mmc/host/mmci.c: In function ?mmci_set_ios?:
> > drivers/mmc/host/mmci.c:1165:20: warning: ignoring return value of
> >         ?regulator_enable?, declared with attribute warn_unused_result
> >         [-Wunused-result]
> >
> > Cc: Russell King <linux at arm.linux.org.uk>
> > Cc: Chris Ball <cjb at laptop.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/mmc/host/mmci.c |    9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> > index 375c109..f4f3038 100644
> > --- a/drivers/mmc/host/mmci.c
> > +++ b/drivers/mmc/host/mmci.c
> > @@ -1130,6 +1130,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> >         struct variant_data *variant = host->variant;
> >         u32 pwr = 0;
> >         unsigned long flags;
> > +       int ret;
> >
> >         pm_runtime_get_sync(mmc_dev(mmc));
> >
> > @@ -1161,8 +1162,12 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> >                 break;
> >         case MMC_POWER_ON:
> >                 if (!IS_ERR(mmc->supply.vqmmc) &&
> > -                   !regulator_is_enabled(mmc->supply.vqmmc))
> 
> I realize that we actually have a bug here (and in the MMC_POWER_OFF
> mode as well).
> 
> We shall not use regulator_is_enabled API as a trigger to enable/fetch
> a reference to the regulator, since it will only tell us if the
> regulator is enabled - hw wise.
> Instead we need a local variable in the mmci host struct keeping track
> if we have enabled the regulator. Do you mind fix this up in this
> patch as well since it is tightly coupled to the regulator handling!?

IMHO I think that should be taken care of in a separate patch. This
patch only touches the line containing regulator_is_enabled() to
encompass a multi-line comparison result.

Care to write that patch? I have so much on my TODO already. :|

> Otherwise it looks good to me.
> 
> Kind regards
> Ulf Hansson
> 
> > -                       regulator_enable(mmc->supply.vqmmc);
> > +                   !regulator_is_enabled(mmc->supply.vqmmc)) {
> > +                       ret = regulator_enable(mmc->supply.vqmmc);
> > +                       if (ret < 0)
> > +                               dev_err(mmc_dev(mmc),
> > +                                       "failed to enable vqmmc regulator\n");
> > +               }
> >
> >                 pwr |= MCI_PWR_ON;
> >                 break;
> >

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From ulf.hansson at linaro.org  Fri May  3 04:20:10 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Fri, 3 May 2013 10:20:10 +0200
Subject: [PATCH 3/4] mmc: mmci: Ensure return value of regulator_enable()
 is checked
In-Reply-To: <20130503081633.GD24153@gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-4-git-send-email-lee.jones@linaro.org>
 <CAPDyKFr60-nuh-BFsWtFhNeqUmswKC4hL4mw-gDhiqLmarvEDA@mail.gmail.com>
 <20130503081633.GD24153@gmail.com>
Message-ID: <CAPDyKFqKP0sSBwZtcnH4tfPxSik5+GOVE-6tTBYaK5Qhvr3=4A@mail.gmail.com>

On 3 May 2013 10:16, Lee Jones <lee.jones at linaro.org> wrote:
> On Fri, 03 May 2013, Ulf Hansson wrote:
>
>> On 2 May 2013 17:48, Lee Jones <lee.jones at linaro.org> wrote:
>> > This patch suppresses the warning below:
>> >
>> > drivers/mmc/host/mmci.c: In function ?mmci_set_ios?:
>> > drivers/mmc/host/mmci.c:1165:20: warning: ignoring return value of
>> >         ?regulator_enable?, declared with attribute warn_unused_result
>> >         [-Wunused-result]
>> >
>> > Cc: Russell King <linux at arm.linux.org.uk>
>> > Cc: Chris Ball <cjb at laptop.org>
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>> > ---
>> >  drivers/mmc/host/mmci.c |    9 +++++++--
>> >  1 file changed, 7 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> > index 375c109..f4f3038 100644
>> > --- a/drivers/mmc/host/mmci.c
>> > +++ b/drivers/mmc/host/mmci.c
>> > @@ -1130,6 +1130,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> >         struct variant_data *variant = host->variant;
>> >         u32 pwr = 0;
>> >         unsigned long flags;
>> > +       int ret;
>> >
>> >         pm_runtime_get_sync(mmc_dev(mmc));
>> >
>> > @@ -1161,8 +1162,12 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> >                 break;
>> >         case MMC_POWER_ON:
>> >                 if (!IS_ERR(mmc->supply.vqmmc) &&
>> > -                   !regulator_is_enabled(mmc->supply.vqmmc))
>>
>> I realize that we actually have a bug here (and in the MMC_POWER_OFF
>> mode as well).
>>
>> We shall not use regulator_is_enabled API as a trigger to enable/fetch
>> a reference to the regulator, since it will only tell us if the
>> regulator is enabled - hw wise.
>> Instead we need a local variable in the mmci host struct keeping track
>> if we have enabled the regulator. Do you mind fix this up in this
>> patch as well since it is tightly coupled to the regulator handling!?
>
> IMHO I think that should be taken care of in a separate patch. This
> patch only touches the line containing regulator_is_enabled() to
> encompass a multi-line comparison result.
>
> Care to write that patch? I have so much on my TODO already. :|

Sure, I can fix it.

I guess this patch will be going through Russell's patch tracker?

>
>> Otherwise it looks good to me.
>>
>> Kind regards
>> Ulf Hansson
>>
>> > -                       regulator_enable(mmc->supply.vqmmc);
>> > +                   !regulator_is_enabled(mmc->supply.vqmmc)) {
>> > +                       ret = regulator_enable(mmc->supply.vqmmc);
>> > +                       if (ret < 0)
>> > +                               dev_err(mmc_dev(mmc),
>> > +                                       "failed to enable vqmmc regulator\n");
>> > +               }
>> >
>> >                 pwr |= MCI_PWR_ON;
>> >                 break;
>> >
>
> --
> Lee Jones
> Linaro ST-Ericsson Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog


From Ian.Campbell at citrix.com  Fri May  3 04:26:45 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Fri, 3 May 2013 09:26:45 +0100
Subject: [Xen-devel] [PATCH 2/3] xen: move do_stolen_accounting to
 drivers/xen/time.c
In-Reply-To: <5182B532.10607@codeaurora.org>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <5182B532.10607@codeaurora.org>
Message-ID: <1367569605.28742.28.camel@zakaz.uk.xensource.com>

On Thu, 2013-05-02 at 19:49 +0100, Christopher Covington wrote:
> Hi Stefano,
> 
> On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> > Move do_stolen_accounting, xen_vcpu_stolen and related functions and
> > static variables to common code (drivers/xen/time.c).
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/x86/xen/time.c   |  127 +-------------------------------------------
> 
> In going through some of the code, it looked like there might be a few little
> bits that you might be interested in pulling out of arch/ia64/xen/time.c as well.

ia64 in the hypervisor was deprecated and with the 4.3 release has been
removed.

AFAIK ia64/Xen support has been broken in the mainline kernel for year.

Ian



From linus.walleij at linaro.org  Fri May  3 04:27:09 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 10:27:09 +0200
Subject: [PATCH 1/4] ARM: ux500: Rid ignored return value of
 regulator_enable() compiler warning
In-Reply-To: <1367509690-24022-2-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdacXK-uBsQF=VGfOvh_zZ3ad-A_Zk1Bd-oz+OAUTeXqHA@mail.gmail.com>

On Thu, May 2, 2013 at 5:48 PM, Lee Jones <lee.jones at linaro.org> wrote:

> arch/arm/mach-ux500/board-mop500.c: In function ?mop500_prox_activate?:
> arch/arm/mach-ux500/board-mop500.c:406:18: warning: ignoring return value of
>         ?regulator_enable?, declared with attribute warn_unused_result
>         [-Wunused-result]
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied!

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 04:28:28 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 10:28:28 +0200
Subject: [PATCH 2/4] mfd: ab8500-gpadc: Suppress 'ignoring
 regulator_enable() return value' warning
In-Reply-To: <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaf75sQduyfw58PFmC1ZyNDMxpwAf0OSyRLPP6vFc+wBQ@mail.gmail.com>

On Thu, May 2, 2013 at 5:48 PM, Lee Jones <lee.jones at linaro.org> wrote:
> drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
> drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
>         ?regulator_enable?, declared with attribute warn_unused_result
>         [-Wunused-result]
>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/mfd/ab8500-gpadc.c |    5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mfd/ab8500-gpadc.c b/drivers/mfd/ab8500-gpadc.c
> index 5e65b28..7278e53 100644
> --- a/drivers/mfd/ab8500-gpadc.c
> +++ b/drivers/mfd/ab8500-gpadc.c
> @@ -907,8 +907,11 @@ static int ab8500_gpadc_suspend(struct device *dev)
>  static int ab8500_gpadc_resume(struct device *dev)
>  {
>         struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
> +       int ret;
>
> -       regulator_enable(gpadc->regu);
> +       ret = regulator_enable(gpadc->regu);
> +       if (ret < 0)
> +               return ret;
>
>         pm_runtime_mark_last_busy(gpadc->dev);
>         pm_runtime_put_autosuspend(gpadc->dev);
> --
> 1.7.10.4

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From balbi at ti.com  Fri May  3 04:30:09 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 May 2013 11:30:09 +0300
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503081510.GG21614@n2100.arm.linux.org.uk>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
 <20130503081510.GG21614@n2100.arm.linux.org.uk>
Message-ID: <20130503083009.GA19377@arwen.pp.htv.fi>

Hi,

On Fri, May 03, 2013 at 09:15:10AM +0100, Russell King - ARM Linux wrote:
> > > This is exactly why we have platform_device_alloc(),
> > > platform_device_register_full() and friends - so that people don't have to
> > > fsck around with kzalloc themselves and get it wrong like the above does.
> > > 
> > > Would you like me to pass your details to gregkh for another one of his
> > > public humilation exercises over basic kernel programming stuff? :)
> > 
> > How about we pass yours for not reading the patch before flaming ? Note
> > that $SUBJECT is *not* touching at all that line which kzallocs a
> > platform_device. Wrong as it is, it's not part of $SUBJECT.
> 
> It's really simple.  You do not use k*alloc with platform devices.  And

agree, no discussions here

> you reject any patch which contains that, and point it out to the patch
> author.
> 
> It really doesn't matter if there's a kfree or not.  The fact is you do
> not allow it in any situation, because such bad practises get copied
> and then you end up with kfree's.
> 
> How about you gain an understanding of this stuff and why this stuff is
> soo "hot".

how about you look at the git log to figure out I had nothing to do with
that original patch which added k*alloc to the pdev ?

-- 
balbi
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From linux at arm.linux.org.uk  Fri May  3 04:32:06 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 09:32:06 +0100
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503061931.GB27451@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
Message-ID: <20130503083205.GH21614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 09:21:51AM +0300, Felipe Balbi wrote:
> How about we pass yours for not reading the patch before flaming ?

And another thing.  If you want to be flamed, continue with that tone.
The problem here is that *you* have not been flamed in the previous
message.  The previous message was all about pointing out an error in
the code in a way that hopefully you will take notice of, because you
showed no sign of taking any notice of my previous mail.

If you want to be a total dork, continue behaving as you currently are.
There, *now* I *have* flamed you!


From linux at arm.linux.org.uk  Fri May  3 04:33:20 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 09:33:20 +0100
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503083009.GA19377@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
 <20130503081510.GG21614@n2100.arm.linux.org.uk>
 <20130503083009.GA19377@arwen.pp.htv.fi>
Message-ID: <20130503083320.GI21614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 11:30:09AM +0300, Felipe Balbi wrote:
> Hi,
> 
> On Fri, May 03, 2013 at 09:15:10AM +0100, Russell King - ARM Linux wrote:
> > > > This is exactly why we have platform_device_alloc(),
> > > > platform_device_register_full() and friends - so that people don't have to
> > > > fsck around with kzalloc themselves and get it wrong like the above does.
> > > > 
> > > > Would you like me to pass your details to gregkh for another one of his
> > > > public humilation exercises over basic kernel programming stuff? :)
> > > 
> > > How about we pass yours for not reading the patch before flaming ? Note
> > > that $SUBJECT is *not* touching at all that line which kzallocs a
> > > platform_device. Wrong as it is, it's not part of $SUBJECT.
> > 
> > It's really simple.  You do not use k*alloc with platform devices.  And
> 
> agree, no discussions here
> 
> > you reject any patch which contains that, and point it out to the patch
> > author.
> > 
> > It really doesn't matter if there's a kfree or not.  The fact is you do
> > not allow it in any situation, because such bad practises get copied
> > and then you end up with kfree's.
> > 
> > How about you gain an understanding of this stuff and why this stuff is
> > soo "hot".
> 
> how about you look at the git log to figure out I had nothing to do with
> that original patch which added k*alloc to the pdev ?

How about you realise I haven't got time to fuck around like that at the
moment, so in the interests of getting people to fix the glaring error
I commented on it instead in a relevant thread in the hope that some
prat like you would take notice and ask for it to be fixed by someone
working on the driver.


From shawn.guo at linaro.org  Fri May  3 04:35:36 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 May 2013 16:35:36 +0800
Subject: [PATCH 2/2] pinctrl/imx: add zero register offset valid for
 Vybrid platform
In-Reply-To: <20130502182759.GQ32299@pengutronix.de>
References: <1367480932-22318-1-git-send-email-b35083@freescale.com>
 <1367480932-22318-2-git-send-email-b35083@freescale.com>
 <20130502182759.GQ32299@pengutronix.de>
Message-ID: <20130503083534.GC31873@S2101-09.ap.freescale.net>

On Thu, May 02, 2013 at 08:27:59PM +0200, Sascha Hauer wrote:
> > @@ -221,10 +221,14 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
> >  		pin_id = pins[i];
> >  		pin_reg = &info->pin_regs[pin_id];
> >  
> > -		if (!pin_reg->mux_reg) {
> > -			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
> > -				info->pins[pin_id].name);
> > -			return -EINVAL;
> > +		/* mux_reg offset maybe zero on some platform such as Vybrid */
> > +		if (!of_machine_is_compatible("fsl,mvf600")) {
> > +			if (!pin_reg->mux_reg) {
> 
> Please add a zero_offset_valid flag to the drivers private structure
> instead of using a rather expensive function in a frequently used path.
> Also the && operator can be used to test for two conditions being true.

Agreed.  I would suggest that we add a flag member into struct
imx_pinctrl_soc_info telling the mvf case, and handle the following mvf
specialties by checking the flag.

* FSL_PIN_SIZE is 20 on mvf, as PIN_FUNC_ID consists of 4 u32 there.
* Assign mux_reg to conf_reg in imx_pinctrl_parse_groups() for mvf case.
* In imx_pmx_enable(), write mux_reg[22:20] bit field rather than the
  whole register for mvf case.
* In imx_pinconf_set(), write conf_reg[15:0] bit field rather than the
  whole register for mvf case.

Doing above will ease the defining of the pin function ID in
mvf600-pinfunc.h.

Shawn



From linus.walleij at linaro.org  Fri May  3 04:38:39 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 10:38:39 +0200
Subject: [PATCH] ARM: Adds pin config API to set all configs in one
 function
In-Reply-To: <051069C10411E24D9749790C498526FA1BCF706F@SJEXCHMB12.corp.ad.broadcom.com>
References: <1366841010-2823-1-git-send-email-syin@broadcom.com>
 <CACRpkdbT7f8ujCHZxKg26iMKcrAb+_yHW_2YsZwkoo892rkgTA@mail.gmail.com>
 <051069C10411E24D9749790C498526FA1BCF5427@SJEXCHMB12.corp.ad.broadcom.com>
 <CACRpkdZ6zQdivtq5wmizovWEGb-Q9xzA6EE8CafnuV13hzX_UA@mail.gmail.com>
 <051069C10411E24D9749790C498526FA1BCF706F@SJEXCHMB12.corp.ad.broadcom.com>
Message-ID: <CACRpkdYw--zVux+j1KYfW6CejdWWUheo3Ypo_X1Kt1qvNyQKRA@mail.gmail.com>

On Thu, May 2, 2013 at 2:07 AM, Sherman Yin <syin at broadcom.com> wrote:
> [Me]:
>>Notice especially the added num_configs parameter that was
>>missing from pin_config_set_all() in your patch, please tell
>>me how else you deduct the size of the configs array.
>
> We are passing a pointer to struct pinctrl_setting_configs,
> which should have the num_configs already:
>
> 105struct pinctrl_setting_configs {
> 106     unsigned group_or_pin;
> 107     unsigned long *configs;
> 108     unsigned num_configs;
> 109};
>
> I want to be sure you are ok with exposing this struct to
> consumers (ie. drivers).  If not, we could pass the 3
> components in the API instead.

Damned I got it wrong. I was totally confused by
the passing of the struct to the driver and not really
grasping what it contained.

The idea was to pass the array of configs (since this
is dealing with configs, not multuiplexing) and then
a number telling how many configs there are in the
array.

Pass struct pinctrl_setting_configs is not OK because
then all of a sudden we're starting to expose a lot of
pinctrl internals to the drivers and that will invariably
be abused: one day someone will make a pinconfig
function that look at the mux group just because it's
convenient...

So I was after something like this:

int (*pin_config_set) (struct pinctrl_dev *pctldev,
                               unsigned pin,
                               unsigned long *configs,
                               unsigned num_configs);

(And same for groups.)

So we get an array of configs and the driver can
iterate over this. Since these are
unsigned longs we do not need a special helper
as I thought.

And then you should refactor the drivers to account
for this.

Yours,
Linus Walleij


From balbi at ti.com  Fri May  3 04:39:00 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 May 2013 11:39:00 +0300
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503083205.GH21614@n2100.arm.linux.org.uk>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
 <20130503083205.GH21614@n2100.arm.linux.org.uk>
Message-ID: <20130503083859.GB19377@arwen.pp.htv.fi>

Hi,

On Fri, May 03, 2013 at 09:32:06AM +0100, Russell King - ARM Linux wrote:
> On Fri, May 03, 2013 at 09:21:51AM +0300, Felipe Balbi wrote:
> > How about we pass yours for not reading the patch before flaming ?
> 
> And another thing.  If you want to be flamed, continue with that tone.
> The problem here is that *you* have not been flamed in the previous
> message.  The previous message was all about pointing out an error in
> the code in a way that hopefully you will take notice of, because you
> showed no sign of taking any notice of my previous mail.
> 
> If you want to be a total dork, continue behaving as you currently are.
> There, *now* I *have* flamed you!

what a load of crap. Just because it wasn't pointed out in my previous
email doesn't automatically mean I haven't noticed. Anyway, I won't be
doing this all day.

cheers

-- 
balbi
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From linux at arm.linux.org.uk  Fri May  3 04:43:21 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 09:43:21 +0100
Subject: [PATCH] ARM: OMAP-USB: Fix possible memory leak
In-Reply-To: <20130503083859.GB19377@arwen.pp.htv.fi>
References: <1367510596-27780-1-git-send-email-shc_work@mail.ru>
 <20130502162433.GA10016@kahuna> <1367512124.978518915@f372.mail.ru>
 <20130502164058.GC8577@arwen.pp.htv.fi>
 <20130502231353.GF21614@n2100.arm.linux.org.uk>
 <20130503061931.GB27451@arwen.pp.htv.fi>
 <20130503083205.GH21614@n2100.arm.linux.org.uk>
 <20130503083859.GB19377@arwen.pp.htv.fi>
Message-ID: <20130503084321.GJ21614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 11:39:00AM +0300, Felipe Balbi wrote:
> Hi,
> 
> On Fri, May 03, 2013 at 09:32:06AM +0100, Russell King - ARM Linux wrote:
> > On Fri, May 03, 2013 at 09:21:51AM +0300, Felipe Balbi wrote:
> > > How about we pass yours for not reading the patch before flaming ?
> > 
> > And another thing.  If you want to be flamed, continue with that tone.
> > The problem here is that *you* have not been flamed in the previous
> > message.  The previous message was all about pointing out an error in
> > the code in a way that hopefully you will take notice of, because you
> > showed no sign of taking any notice of my previous mail.
> > 
> > If you want to be a total dork, continue behaving as you currently are.
> > There, *now* I *have* flamed you!
> 
> what a load of crap. Just because it wasn't pointed out in my previous
> email doesn't automatically mean I haven't noticed. Anyway, I won't be
> doing this all day.

Yes you are a load of crap *you* spout about people flaming you.  Well, if
you can't be bothered to acknowledge a problem then you can expect to get
resends because it's not clear that the message has been received.  And
you do *not* call resends "flames" back to those who were kind enough put
the effort in to tell you about them more than once.

That's just down right insulting and flame provoking.  Which is exactly
how we ended up here.


From will.deacon at arm.com  Fri May  3 04:51:00 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 3 May 2013 09:51:00 +0100
Subject: [PATCH V2] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <1367542653-955-1-git-send-email-csd@broadcom.com>
References: <1367542653-955-1-git-send-email-csd@broadcom.com>
Message-ID: <20130503085100.GA6188@mudshark.cambridge.arm.com>

Hi Christian,

On Fri, May 03, 2013 at 01:57:33AM +0100, Christian Daudt wrote:
> Rev A2 SoCs have an unorthodox memory re-mapping and this needs
> to be reflected in the cache operations.
> This patch adds new outer cache functions for the l2x0 driver
> to support this SoC revision. It also adds a new compatible
> value for the cache to enable this functionality.
> 
> Updates from V1:
> - remove section 1 altogether and note that in comments
> - simplify section selection caused by section 1 removal
> - BUG_ON just in case section 1 shows up

Looking much better now :)

> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index c465fac..d70e0ab 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
>  	}
>  }
>  
> +/*
> + * For certain Broadcom SoCs, depending on the address range, different offsets
> + * need to be added to the address before passing it to L2 for
> + * invalidation/clean/flush
> + *
> + * Section Address Range              Offset        EMI
> + *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
> + *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
> + *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC

I don't think you answered last time (or I missed it) but where is the RAM
in the physical memory map for boards with this L2 controller? Do you
actually have 3GB at 0x40000000?

Will


From ulf.hansson at linaro.org  Fri May  3 04:51:50 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Fri, 3 May 2013 10:51:50 +0200
Subject: [PATCH] clk: ux500: clk-sysctrl: handle clocks with no parents
In-Reply-To: <1367325906-23045-1-git-send-email-fabio.baltieri@linaro.org>
References: <1367325906-23045-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <CAPDyKFpZ+-6b3kPyNacPQ33=Ssdjs=fvFxkr4iSUT_hm1YzVTg@mail.gmail.com>

On 30 April 2013 14:45, Fabio Baltieri <fabio.baltieri at linaro.org> wrote:
> Fix clk_reg_sysctrl() to set main clock registers of new struct
> clk_sysctrl even if the registered clock has no parents.
>
> This fixes an issue where "ulpclk" was registered with all clk->reg_*
> fields uninitialized, causing a -EINVAL error from clk_prepare().
>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> ---
>  drivers/clk/ux500/clk-sysctrl.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
> index bc7e9bd..e364c9d 100644
> --- a/drivers/clk/ux500/clk-sysctrl.c
> +++ b/drivers/clk/ux500/clk-sysctrl.c
> @@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
>                 return ERR_PTR(-ENOMEM);
>         }
>
> -       for (i = 0; i < num_parents; i++) {
> +       /* set main clock registers */
> +       clk->reg_sel[0] = reg_sel[0];
> +       clk->reg_bits[0] = reg_bits[0];
> +       clk->reg_mask[0] = reg_mask[0];
> +
> +       /* handle clocks with more than one parent */
> +       for (i = 1; i < num_parents; i++) {
>                 clk->reg_sel[i] = reg_sel[i];
>                 clk->reg_bits[i] = reg_bits[i];
>                 clk->reg_mask[i] = reg_mask[i];
> --
> 1.8.2
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>

This is bugfix, should go "stable" as well?

Kind regards
Ulf Hansson


From ulf.hansson at linaro.org  Fri May  3 04:54:09 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Fri, 3 May 2013 10:54:09 +0200
Subject: [PATCH] clk: ux500: clk-sysctrl: handle clocks with no parents
In-Reply-To: <CAPDyKFpZ+-6b3kPyNacPQ33=Ssdjs=fvFxkr4iSUT_hm1YzVTg@mail.gmail.com>
References: <1367325906-23045-1-git-send-email-fabio.baltieri@linaro.org>
 <CAPDyKFpZ+-6b3kPyNacPQ33=Ssdjs=fvFxkr4iSUT_hm1YzVTg@mail.gmail.com>
Message-ID: <CAPDyKFq6iQ21QosEH_WqGCetXfaO1uecvK7+WzjZJDkK8r3SxA@mail.gmail.com>

On 3 May 2013 10:51, Ulf Hansson <ulf.hansson at linaro.org> wrote:
> On 30 April 2013 14:45, Fabio Baltieri <fabio.baltieri at linaro.org> wrote:
>> Fix clk_reg_sysctrl() to set main clock registers of new struct
>> clk_sysctrl even if the registered clock has no parents.
>>
>> This fixes an issue where "ulpclk" was registered with all clk->reg_*
>> fields uninitialized, causing a -EINVAL error from clk_prepare().
>>
>> Cc: Ulf Hansson <ulf.hansson at linaro.org>
>> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
>> ---
>>  drivers/clk/ux500/clk-sysctrl.c | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
>> index bc7e9bd..e364c9d 100644
>> --- a/drivers/clk/ux500/clk-sysctrl.c
>> +++ b/drivers/clk/ux500/clk-sysctrl.c
>> @@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
>>                 return ERR_PTR(-ENOMEM);
>>         }
>>
>> -       for (i = 0; i < num_parents; i++) {
>> +       /* set main clock registers */
>> +       clk->reg_sel[0] = reg_sel[0];
>> +       clk->reg_bits[0] = reg_bits[0];
>> +       clk->reg_mask[0] = reg_mask[0];
>> +
>> +       /* handle clocks with more than one parent */
>> +       for (i = 1; i < num_parents; i++) {
>>                 clk->reg_sel[i] = reg_sel[i];
>>                 clk->reg_bits[i] = reg_bits[i];
>>                 clk->reg_mask[i] = reg_mask[i];
>> --
>> 1.8.2
>>
>
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
>
> This is bugfix, should go "stable" as well?

Stable means 3.10 rcs, since the abx500 clk tree was added for 3.10.

>
> Kind regards
> Ulf Hansson


From kyungsik.lee at lge.com  Fri May  3 05:02:52 2013
From: kyungsik.lee at lge.com (Kyungsik Lee)
Date: Fri, 3 May 2013 18:02:52 +0900
Subject: [PATCH v3 -next 3/5] arm: Add support for LZ4-compressed kernel
In-Reply-To: <20130430135602.2aa0d3b4ec392bf83a9b64d0@linux-foundation.org>
References: <1362484056-9778-1-git-send-email-kyungsik.lee@lge.com>
 <1362484056-9778-4-git-send-email-kyungsik.lee@lge.com>
 <20130430135602.2aa0d3b4ec392bf83a9b64d0@linux-foundation.org>
Message-ID: <20130503090252.GB3170@Corona>

On Tue, Apr 30, 2013 at 01:56:02PM -0700, Andrew Morton wrote:
> On Tue,  5 Mar 2013 20:47:34 +0900 Kyungsik Lee <kyungsik.lee at lge.com> wrote:
> 
> > This patch integrates the LZ4 decompression code to the arm pre-boot code.
> > And it depends on two patchs below
> > 
> > lib: Add support for LZ4-compressed kernel
> > decompressor: Add LZ4 decompressor module
> > 
> > ...
> >
> > - Apply CFLAGS, -Os to decompress.o to improve decompress
> >   performance during boot-up process
> >
> > ...
> >
> > --- a/arch/arm/boot/compressed/Makefile
> > +++ b/arch/arm/boot/compressed/Makefile
> > @@ -24,6 +24,9 @@ endif
> >  AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
> >  HEAD	= head.o
> >  OBJS	+= misc.o decompress.o
> > +ifeq ($(CONFIG_KERNEL_LZ4),y)
> > +CFLAGS_decompress.o := -Os
> > +endif
> 
> Surprised.  You found that -Os produces faster code than -O2?  Details,
> please?
-Os is enforced here, based on the test result of decompression time
below, slightly faster than -O2.
But further tests with UA show that using -O2 will be the right choice
especially in the case of the unaligned access enabled.

Decompression Time(counts)
             UA
-Os  6717    3447
-O2  6720    2728

Note: ARM v7, Kernel 3.4
      counter freq. = 32768 HZ
      UA(Unaligned Access)
      gcc version 4.6.2 (Ubuntu/Linaro 4.6.2-14ubuntu2~ppa1)

Thanks,
Kyungsik


From fabio.baltieri at linaro.org  Fri May  3 05:03:05 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Fri, 3 May 2013 11:03:05 +0200
Subject: [PATCH] clk: ux500: clk-sysctrl: handle clocks with no parents
In-Reply-To: <CAPDyKFq6iQ21QosEH_WqGCetXfaO1uecvK7+WzjZJDkK8r3SxA@mail.gmail.com>
References: <1367325906-23045-1-git-send-email-fabio.baltieri@linaro.org>
 <CAPDyKFpZ+-6b3kPyNacPQ33=Ssdjs=fvFxkr4iSUT_hm1YzVTg@mail.gmail.com>
 <CAPDyKFq6iQ21QosEH_WqGCetXfaO1uecvK7+WzjZJDkK8r3SxA@mail.gmail.com>
Message-ID: <20130503090305.GA17733@balto.lan>

On Fri, May 03, 2013 at 10:54:09AM +0200, Ulf Hansson wrote:
> On 3 May 2013 10:51, Ulf Hansson <ulf.hansson at linaro.org> wrote:
> > On 30 April 2013 14:45, Fabio Baltieri <fabio.baltieri at linaro.org> wrote:
> >> Fix clk_reg_sysctrl() to set main clock registers of new struct
> >> clk_sysctrl even if the registered clock has no parents.
> >>
> >> This fixes an issue where "ulpclk" was registered with all clk->reg_*
> >> fields uninitialized, causing a -EINVAL error from clk_prepare().
> >>
> >> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> >> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> >> ---
> >>  drivers/clk/ux500/clk-sysctrl.c | 8 +++++++-
> >>  1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
> >> index bc7e9bd..e364c9d 100644
> >> --- a/drivers/clk/ux500/clk-sysctrl.c
> >> +++ b/drivers/clk/ux500/clk-sysctrl.c
> >> @@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
> >>                 return ERR_PTR(-ENOMEM);
> >>         }
> >>
> >> -       for (i = 0; i < num_parents; i++) {
> >> +       /* set main clock registers */
> >> +       clk->reg_sel[0] = reg_sel[0];
> >> +       clk->reg_bits[0] = reg_bits[0];
> >> +       clk->reg_mask[0] = reg_mask[0];
> >> +
> >> +       /* handle clocks with more than one parent */
> >> +       for (i = 1; i < num_parents; i++) {
> >>                 clk->reg_sel[i] = reg_sel[i];
> >>                 clk->reg_bits[i] = reg_bits[i];
> >>                 clk->reg_mask[i] = reg_mask[i];
> >> --
> >> 1.8.2
> >>
> >
> > Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> >
> > This is bugfix, should go "stable" as well?
> 
> Stable means 3.10 rcs, since the abx500 clk tree was added for 3.10.

Thanks!  Yes, it would be great if this could be queued up for an -rc.

Fabio

-- 
Fabio Baltieri


From broonie at kernel.org  Fri May  3 05:02:58 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 3 May 2013 10:02:58 +0100
Subject: [PATCH v3 1/5] regulator: Introduce TI Adaptive Body Bias(ABB)
 on-chip LDO driver
In-Reply-To: <1367515215-30753-2-git-send-email-nm@ti.com>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
 <1367515215-30753-2-git-send-email-nm@ti.com>
Message-ID: <20130503090258.GG4945@sirena.org.uk>

On Thu, May 02, 2013 at 12:20:10PM -0500, Nishanth Menon wrote:
> From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>
> 
> Adaptive Body Biasing (ABB) modulates transistor bias voltages
> dynamically in order to optimize switching speed versus leakage.

I've applied this but please note that I still have deep concerns about
some of the discussion about controlling this from other regulators.
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From dirk.behme at de.bosch.com  Fri May  3 05:08:45 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 3 May 2013 11:08:45 +0200
Subject: [PATCH] ARM: i.MX6: clk: add i.MX6 DualLite differences
Message-ID: <1367572125-28420-1-git-send-email-dirk.behme@de.bosch.com>

The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.

Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and
moves the gpu2_core configuration at that place.

Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences
by using cpu_is_mx6dl().

Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>
---

Note: This patch is against
      https://git.linaro.org/gitweb?p=people/shawnguo/linux-2.6.git;a=shortlog;h=refs/heads/imx/soc
      as it needs cpu_is_imx6dl() from the commit "ARM: imx: add initial imx6dl support"

 arch/arm/mach-imx/clk-imx6q.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1512590..32c19c7 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -480,7 +480,14 @@ int __init mx6q_clocks_init(void)
 	clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
 	clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
 	clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
-	clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
+	if (cpu_is_imx6dl())
+		/*
+		 * The multiplexer and divider of imx6q clock gpu3d_shader get
+		 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
+		 */
+		clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+	else
+		clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
 	clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
 	clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
 	clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
-- 
1.8.2



From ming.lei at canonical.com  Fri May  3 05:12:45 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri,  3 May 2013 17:12:45 +0800
Subject: [PATCH] ARM: DMA-mapping: mark all !DMA_TO_DEVICE pages in unmapping
 as clean
Message-ID: <1367572365-18905-1-git-send-email-ming.lei@canonical.com>

It is common for one sg to include many pages, so mark all these
pages as clean to avoid unnecessary flushing on them in
set_pte_at() or update_mmu_cache().

The patch might improve loading performance of applciation code a bit.

On the below test code to read file(~1GByte size) from usb mass storage
disk to buffer created with mmap(PROT_READ | PROT_EXEC) on
Pandaboard, average ~1% improvement can be observed with the patch on
10 times test.


#define _GNU_SOURCE

#include <fcntl.h>
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <string.h>
#include <assert.h>

unsigned int sum = 0;

static unsigned long tv_diff(struct timeval *tv1, struct timeval *tv2)
{
	return (tv2->tv_sec - tv1->tv_sec) * 1000000 +
		(tv2->tv_usec - tv1->tv_usec);
}

int main(int argc, char *argv[])
{
	char *mbuffer;
	int fd;
	int i;
	unsigned long page_size, size;
	struct stat stat;
	struct timeval t1, t2;

	page_size = getpagesize();
	fd = open(argv[1], O_RDONLY);
	assert(fd >= 0);

	fstat(fd, &stat);
	size = stat.st_size;
	printf("%s: file %s, file size %lu, page size %lu\n", argv[0],
		read_filename, size, page_size);

	gettimeofday(&t1, NULL);
	mbuffer = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0);
	for (i = 0 ; i < size ; i += page_size)
		sum += mbuffer[i];
	munmap(mbuffer, page_size);
	gettimeofday(&t2, NULL);
	printf("\tread mmaped time: %luus\n", tv_diff(&t1, &t2));

	close(fd);
}

Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Marek Szyprowski <m.szyprowski at samsung.com>
Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Ming Lei <ming.lei at canonical.com>
---
 arch/arm/mm/dma-mapping.c |   19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e9db6b4..e63124a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -879,10 +879,23 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
 
 	/*
-	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 * Mark the D-cache clean for these pages to avoid extra flushing.
 	 */
-	if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
-		set_bit(PG_dcache_clean, &page->flags);
+	if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
+		unsigned long pfn;
+		size_t left = size;
+
+		pfn = page_to_pfn(page);
+		if (off) {
+			pfn++;
+			left -= PAGE_SIZE - off % PAGE_SIZE;
+		}
+		while (left >= PAGE_SIZE) {
+			page = pfn_to_page(pfn++);
+			set_bit(PG_dcache_clean, &page->flags);
+			left -= PAGE_SIZE;
+		}
+	}
 }
 
 /**
-- 
1.7.9.5



From lorenzo.pieralisi at arm.com  Fri May  3 05:15:11 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 3 May 2013 10:15:11 +0100
Subject: [RFC PATCH v2 13/13] ARM: DT: kernel: DT cpu node bindings update
In-Reply-To: <5182B0E9.3090006@wwwdotorg.org>
References: <1366644455-16550-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1366644455-16550-14-git-send-email-lorenzo.pieralisi@arm.com>
 <5182B0E9.3090006@wwwdotorg.org>
Message-ID: <20130503091510.GB20678@e102568-lin.cambridge.arm.com>

On Thu, May 02, 2013 at 07:31:05PM +0100, Stephen Warren wrote:
> On 04/22/2013 09:27 AM, Lorenzo Pieralisi wrote:
> > In order to extend the current cpu nodes bindings to newer CPUs
> > inclusive of AArch64 and to update support for older ARM CPUs this
> > patch updates device tree documentation for the cpu nodes bindings.
> 
> Since I'm late reviewing this due to vacation, I imagine this has been
> applied by now. But for the record, the structure of the DT binding
> documentation in this version does look much better to me, and addresses
> any concerns I had with v1.

It is not merged yet, but hopefully it can be as soon as the merge
window closes, I just need to update some bits and bobs after rebasing,
to take into account changes that got merged this cycle.

I will repost a, hopefully, final series as soon as the merge window closes.

Thanks,
Lorenzo



From maxime.ripard at free-electrons.com  Fri May  3 05:17:44 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 May 2013 11:17:44 +0200
Subject: [PATCH RESEND 0/5] Add I2C support for Allwinner SoCs
Message-ID: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

This patchset adds support for the I2C controller found on most of the
Allwinner SoCs, especially the already supported A10 and A13, and the
yet to come A31.

It has been tested on a A13-Olinuxino.

Thanks,
Maxime

Resent to fix Wolfram's email address.

Maxime Ripard (5):
  i2c: sunxi: Add Allwinner A1X i2c driver
  ARM: sunxi: dt: Add i2c controller nodes to the DTSI
  ARM: sun4i: dt: Add i2c muxing options
  ARM: sun5i: dt: Add i2c muxing options
  ARM: sun5i: olinuxino: Enable the i2c controllers

 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 441 +++++++++++++++++++++
 7 files changed, 585 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May  3 05:17:45 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 May 2013 11:17:45 +0200
Subject: [PATCH 1/5] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367572669-24354-2-git-send-email-maxime.ripard@free-electrons.com>

This patch implements a basic driver for the I2C host driver found on
the Allwinner A10, A13 and A31 SoCs.

Notable missing feature is 10-bit addressing.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 441 +++++++++++++++++++++
 4 files changed, 471 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
new file mode 100644
index 0000000..40c16d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-i2c".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c at 01c2ac00 {
+	compatible = "allwinner,sun4i-i2c";
+	reg = <0x01c2ac00 0x400>;
+	interrupts = <7>;
+	clocks = <&apb1_gates 0>;
+	clock-frequency = <100000>;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index adfee98..327a49b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -706,6 +706,16 @@ config I2C_STU300
 	  This driver can also be built as a module. If so, the module
 	  will be called i2c-stu300.
 
+config I2C_SUNXI
+	tristate "Allwinner A1X I2C controller"
+	depends on ARCH_SUNXI
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controller embedded in Allwinner A1X SoCs.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called i2c-sunxi.
+
 config I2C_TEGRA
 	tristate "NVIDIA Tegra internal I2C controller"
 	depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..7225818 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
 obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
diff --git a/drivers/i2c/busses/i2c-sunxi.c b/drivers/i2c/busses/i2c-sunxi.c
new file mode 100644
index 0000000..f9f8bd4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi.c
@@ -0,0 +1,441 @@
+/*
+ * Allwinner A1X SoCs i2c controller driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)
+
+struct sunxi_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct clk		*clk;
+	struct device		*dev;
+	struct completion	completion;
+	unsigned int		irq;
+	void __iomem		*membase;
+
+	struct i2c_msg		*msg_cur;
+	u8			*msg_buf;
+	size_t			msg_buf_remaining;
+	unsigned int		msg_err;
+};
+
+static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8 value)
+{
+	writel(value, i2c_dev->membase + reg);
+}
+
+static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
+{
+	return readl(i2c_dev->membase + reg);
+}
+
+/*
+ * This is where all the magic happens. The I2C controller works as a
+ * state machine, each state being a step in the i2c protocol, with
+ * the controller sending an interrupt at each state transition.
+ *
+ * The state we're in is stored in a register, which leads to a pretty
+ * huge switch statement, all of this in the interrupt handler...
+ */
+static irqreturn_t sunxi_i2c_handler(int irq, void *data)
+{
+	struct sunxi_i2c_dev *i2c_dev = (struct sunxi_i2c_dev *)data;
+	u32 status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	u32 addr, val;
+
+	if (!(status & SUNXI_I2C_CNTR_INT_FLAG))
+		return IRQ_NONE;
+
+	/* Read the current state we're in */
+	status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_STA_REG);
+
+	switch (status & 0xff) {
+	/* Start condition has been transmitted */
+	case SUNXI_I2C_STA_START:
+	/* A repeated start condition has been transmitted */
+	case SUNXI_I2C_STA_START_REPEAT:
+		addr = SUNXI_I2C_ADDR_ADDR(i2c_dev->msg_cur->addr);
+
+		if (i2c_dev->msg_cur->flags & I2C_M_RD)
+			addr |= 1;
+
+		sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG, addr);
+		break;
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has not been
+	 * received.
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_NAK:
+	/*
+	 * Data byte has been transmitted, ACK has not been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_ACK:
+	/* Data byte has been transmitted, ACK has been received */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_ACK:
+		if (i2c_dev->msg_buf_remaining) {
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG,
+					*i2c_dev->msg_buf);
+			i2c_dev->msg_buf++;
+			i2c_dev->msg_buf_remaining--;
+			break;
+		}
+
+		if (i2c_dev->msg_buf_remaining == 0) {
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		break;
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has not been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has been
+	 * received
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_ACK:
+		/*
+		 * We only need to send the ACK for the all the bytes
+		 * but the last one
+		 */
+		if (i2c_dev->msg_buf_remaining > 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val | SUNXI_I2C_CNTR_ASSERT_ACK);
+		}
+
+		break;
+
+	/*
+	 * Data byte has been received, ACK has not been
+	 * transmitted
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_NAK:
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG);
+			*i2c_dev->msg_buf = val & 0xff;
+			i2c_dev->msg_buf_remaining--;
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/* Data byte has been received, ACK has been transmitted */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_ACK:
+		val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG) & 0xff;
+		*i2c_dev->msg_buf = val;
+		i2c_dev->msg_buf++;
+		i2c_dev->msg_buf_remaining--;
+
+		/* If there's only one byte left, disable the ACK */
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val & ~SUNXI_I2C_CNTR_ASSERT_ACK);
+
+		};
+
+		break;
+
+	case SUNXI_I2C_STA_BUS_ERROR:
+		i2c_dev->msg_err = SUNXI_I2C_BUS_ERROR;
+		goto out;
+
+	default:
+		i2c_dev->msg_err = SUNXI_I2C_ERROR;
+		goto out;
+	}
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	return IRQ_HANDLED;
+
+out:
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val | SUNXI_I2C_CNTR_MASTER_STOP);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	complete(&i2c_dev->completion);
+	return IRQ_HANDLED;
+}
+
+static int sunxi_i2c_xfer_msg(struct sunxi_i2c_dev *i2c_dev,
+			      struct i2c_msg *msg)
+{
+	int time_left;
+	u32 val;
+
+	i2c_dev->msg_cur = msg;
+	i2c_dev->msg_buf = msg->buf;
+	i2c_dev->msg_buf_remaining = msg->len;
+	i2c_dev->msg_err = 0;
+	INIT_COMPLETION(i2c_dev->completion);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	val |= SUNXI_I2C_CNTR_MASTER_START;
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG, val);
+
+	time_left = wait_for_completion_timeout(&i2c_dev->completion,
+						i2c_dev->adapter.timeout);
+	if (!time_left) {
+		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	if (likely(i2c_dev->msg_err == SUNXI_I2C_DONE))
+		return 0;
+
+	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
+
+	return -EIO;
+}
+
+static int sunxi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			  int num)
+{
+	struct sunxi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	int i, ret;
+
+	for (i = 0; i < num; i++) {
+		ret = sunxi_i2c_xfer_msg(i2c_dev, &msgs[i]);
+		if (ret)
+			return ret;
+	}
+
+	return i;
+}
+
+static u32 sunxi_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm sunxi_i2c_algo = {
+	.master_xfer	= sunxi_i2c_xfer,
+	.functionality	= sunxi_i2c_func,
+};
+
+static int sunxi_i2c_probe(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev;
+	struct device_node *np;
+	u32 freq, div_m, div_n;
+	int ret;
+
+	np = pdev->dev.of_node;
+	if (!np)
+		return -EINVAL;
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, i2c_dev);
+	i2c_dev->dev = &pdev->dev;
+
+	init_completion(&i2c_dev->completion);
+
+	i2c_dev->membase = of_iomap(np, 0);
+	if (!i2c_dev->membase)
+		return -EADDRNOTAVAIL;
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_SRST_REG, SUNXI_I2C_SRST_RESET);
+
+	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(i2c_dev->clk)) {
+		ret = PTR_ERR(i2c_dev->clk);
+		goto out_iounmap;
+	}
+	clk_prepare_enable(i2c_dev->clk);
+
+	ret = of_property_read_u32(np, "clock-frequency", &freq);
+	if (ret < 0) {
+		dev_warn(&pdev->dev, "Could not read clock-frequency property\n");
+		freq = 100000;
+	}
+
+	/*
+	 * Set the clock dividers. we don't need to be super smart
+	 * here, the datasheet defines the value of the factors for
+	 * the two supported frequencies, and only the M factor
+	 * changes between 100kHz and 400kHz.
+	 *
+	 * The bus clock is generated from the parent clock with two
+	 * different dividers. It is generated as such:
+	 *     f0 = fclk / (2 ^ DIV_N)
+	 *     fbus = f0 / (10 * (DIV_M + 1))
+	 *
+	 * With DIV_N being on 3 bits, and DIV_M on 4 bits.
+	 * So DIV_N < 8, and DIV_M < 16.
+	 *
+	 * However, we can generate both the supported frequencies
+	 * with f0 = 12MHz, and only change M to get back on our
+	 * feet.
+	 */
+	div_n = ilog2(clk_get_rate(i2c_dev->clk) / 12000000);
+	if (freq == 100000)
+		div_m = 11;
+	else if (freq == 400000)
+		div_m = 2;
+	else {
+		dev_err(&pdev->dev, "Unsupported bus frequency\n");
+		ret = -EINVAL;
+		goto out_clk_dis;
+	}
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CCR_REG,
+			SUNXI_I2C_CCR_DIV_N(div_n) | SUNXI_I2C_CCR_DIV_M(div_m));
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "No IRQ resource\n");
+		ret = -ENODEV;
+		goto out_clk_dis;
+	}
+
+	ret = devm_request_irq(&pdev->dev, i2c_dev->irq, sunxi_i2c_handler,
+			       IRQF_SHARED, dev_name(&pdev->dev), i2c_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not request IRQ\n");
+		goto out_clk_dis;
+	}
+
+	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
+
+	i2c_dev->adapter.owner = THIS_MODULE;
+	strlcpy(i2c_dev->adapter.name, "sunxi I2C adapter",
+		sizeof(i2c_dev->adapter.name));
+	i2c_dev->adapter.algo = &sunxi_i2c_algo;
+	i2c_dev->adapter.dev.parent = &pdev->dev;
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			SUNXI_I2C_CNTR_BUS_ENABLE | SUNXI_I2C_CNTR_INT_ENABLE);
+
+	ret = i2c_add_adapter(&i2c_dev->adapter);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register i2c adapter\n");
+		goto out_clk_dis;
+	}
+
+	return 0;
+
+out_clk_dis:
+	clk_disable_unprepare(i2c_dev->clk);
+out_iounmap:
+	iounmap(i2c_dev->membase);
+	return ret;
+}
+
+
+static int sunxi_i2c_remove(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+	clk_disable_unprepare(i2c_dev->clk);
+	iounmap(i2c_dev->membase);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_i2c_of_match[] = {
+	{ .compatible = "allwinner,sun4i-i2c" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sunxi_i2c_of_match);
+
+static struct platform_driver sunxi_i2c_driver = {
+	.probe		= sunxi_i2c_probe,
+	.remove		= sunxi_i2c_remove,
+	.driver		= {
+		.name	= "i2c-sunxi",
+		.owner	= THIS_MODULE,
+		.of_match_table = sunxi_i2c_of_match,
+	},
+};
+module_platform_driver(sunxi_i2c_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com");
+MODULE_DESCRIPTION("Allwinner A1X I2C bus adapter");
+MODULE_LICENSE("GPL");
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May  3 05:17:48 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 May 2013 11:17:48 +0200
Subject: [PATCH 4/5] ARM: sun5i: dt: Add i2c muxing options
In-Reply-To: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367572669-24354-5-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A13 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 16df784..450b410 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -182,6 +182,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB15", "PB16";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB17", "PB18";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May  3 05:17:47 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 May 2013 11:17:47 +0200
Subject: [PATCH 3/5] ARM: sun4i: dt: Add i2c muxing options
In-Reply-To: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367572669-24354-4-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A10 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 311dcd4..63f6716 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May  3 05:17:46 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 May 2013 11:17:46 +0200
Subject: [PATCH 2/5] ARM: sunxi: dt: Add i2c controller nodes to the DTSI
In-Reply-To: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367572669-24354-3-git-send-email-maxime.ripard@free-electrons.com>

The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..311dcd4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -292,5 +292,32 @@
 			clocks = <&apb1_gates 23>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..16df784 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -215,5 +215,32 @@
 			clocks = <&apb1_gates 19>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May  3 05:17:49 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 May 2013 11:17:49 +0200
Subject: [PATCH 5/5] ARM: sun5i: olinuxino: Enable the i2c controllers
In-Reply-To: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1367572669-24354-6-git-send-email-maxime.ripard@free-electrons.com>

The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner
A13. Enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca5506..80497e3 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
 			pinctrl-0 = <&uart1_pins_b>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.1.2



From jonathan.austin at arm.com  Fri May  3 05:21:34 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 03 May 2013 10:21:34 +0100
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <5182C480.3080001@dawncrow.de>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
 <5182C480.3080001@dawncrow.de>
Message-ID: <5183819E.50308@arm.com>

Hi Andr?,

Will pointed me at this thread and I had a look at fixing
this up yesterday by extending his original patch...

There are a few things about this that aren't quite right. Most
of the comments are cosmetic but there's an issue in copy_thread
that will result in incorrect behaviour, I think.

I've commented below inline and there's a patch at the bottom- can
you let me know if it works for you?

On 02/05/13 20:54, Andr? Hentschel wrote:
> Am 24.04.2013 11:42, schrieb Will Deacon:
>> Hi Andrew,
>>
>> On Tue, Apr 23, 2013 at 11:42:22PM +0100, Andr? Hentschel wrote:
>>> Am 23.04.2013 11:15, schrieb Will Deacon:
>>>> You could introduce `get' tls functions, which don't do anything for CPUs
>>>> without the relevant registers.
>>>
>>> Before i have another round of testing and patch formatting/sending,
>>> what about the untested patch below?
>>
>> Ok. Comments inline.
> 
> I answered to that seperatly.
> Here is another try based on your comments:
> 
> 
> 
> diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
> index cddda1f..bb5b48d 100644
> --- a/arch/arm/include/asm/thread_info.h
> +++ b/arch/arm/include/asm/thread_info.h
> @@ -58,7 +58,7 @@ struct thread_info {
>   	struct cpu_context_save	cpu_context;	/* cpu context */
>   	__u32			syscall;	/* syscall number */
>   	__u8			used_cp[16];	/* thread used copro */
> -	unsigned long		tp_value;
> +	unsigned long		tp_value[2];
>   #ifdef CONFIG_CRUNCH
>   	struct crunch_state	crunchstate;
>   #endif
> diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
> index 73409e6..02f8674 100644
> --- a/arch/arm/include/asm/tls.h
> +++ b/arch/arm/include/asm/tls.h
> @@ -2,48 +2,87 @@
>   #define __ASMARM_TLS_H
>   
>   #ifdef __ASSEMBLY__
> +	.macro check_hwcap_tls, tmp1
> +	ldr	\tmp1, =elf_hwcap
> +	ldr	\tmp1, [\tmp1, #0]
> +	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> +	.endm
> +
> +
> +	.macro get_tls_none, tp, tmp1
> +	.endm
> +
> +	.macro get_tls_v6k, tp, tmp1
> +	mrc	p15, 0, \tmp1, c13, c0, 2		@ get user r/w TLS register
> +	str	\tmp1, [\tp, #4]
> +	.endm
> +
> +	.macro get_tls_v6, tp, tmp1
> +	check_hwcap_tls \tmp1

I tend to steer clear of asm that requires certain behaviour wrt
the flags, though in this case I think it's probably a sufficiently
self contained case to be okay...

> +	mrcne	p15, 0, \tmp1, c13, c0, 2		@ get user r/w TLS register
> +	strne	\tmp1, [\tp, #4]
> +	.endm
> +
> +
>   	.macro set_tls_none, tp, tmp1, tmp2
>   	.endm
>   
>   	.macro set_tls_v6k, tp, tmp1, tmp2
> -	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
> -	mov	\tmp1, #0
> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> +	ldrd	\tmp1, \tmp2, [\tp]
> +	mcr	p15, 0, \tmp1, c13, c0, 3	@ set user r/o TLS register
> +	mcr	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
>   	.endm
>   
>   	.macro set_tls_v6, tp, tmp1, tmp2
> -	ldr	\tmp1, =elf_hwcap
> -	ldr	\tmp1, [\tmp1, #0]
>   	mov	\tmp2, #0xffff0fff
> -	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> -	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> -	movne	\tmp1, #0
> -	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> -	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> +	check_hwcap_tls \tmp1
> +	ldrdne	\tmp1, \tmp2, [\tp]
> +	ldreq	\tmp1, [\tp]
> +	mcrne	p15, 0, \tmp1, c13, c0, 3	@ yes, set user r/o TLS register
> +	mcrne	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
> +	streq	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
>   	.endm
>   
>   	.macro set_tls_software, tp, tmp1, tmp2
> -	mov	\tmp1, #0xffff0fff
> -	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
> +	ldr	\tmp1, [\tp]
> +	mov	\tmp2, #0xffff0fff
> +	str	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
>   	.endm
>   #endif
>   
>   #ifdef CONFIG_TLS_REG_EMUL
>   #define tls_emu		1
>   #define has_tls_reg		1
> +#define get_tls		get_tls_none

This is different from the set_tls, which deals with both
tpidrurw and tpidruro, so the naming is a little inconsistent here...

>   #define set_tls		set_tls_none
>   #elif defined(CONFIG_CPU_V6)
>   #define tls_emu		0
>   #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
> +#define get_tls		get_tls_v6
>   #define set_tls		set_tls_v6
>   #elif defined(CONFIG_CPU_32v6K)
>   #define tls_emu		0
>   #define has_tls_reg		1
> +#define get_tls		get_tls_v6k
>   #define set_tls		set_tls_v6k
>   #else
>   #define tls_emu		0
>   #define has_tls_reg		0
> +#define get_tls		get_tls_none
>   #define set_tls		set_tls_software
>   #endif
>   
> +#ifndef __ASSEMBLY__
> +static inline void get_tpidrurw(unsigned long *tpidrurw)

A bit weird to have tpidrurw here but tls elsewhere - I
settled on tlsuser... (see below)

> +{
> +	unsigned long t;
> +#ifdef CONFIG_TLS_REG_EMUL
> +	return;
> +#endif
> +	if (!has_tls_reg) return;
> +	__asm__("mcr p15, 0, %0, c13, c0, 2" : : "r" (t));
> +	*tpidrurw = t;
> +}
> +#endif
> +
>   #endif	/* __ASMARM_TLS_H */
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index 0f82098..2c892b2 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -728,7 +728,7 @@ ENTRY(__switch_to)
>    UNWIND(.fnstart	)
>    UNWIND(.cantunwind	)
>   	add	ip, r1, #TI_CPU_SAVE
> -	ldr	r3, [r2, #TI_TP_VALUE]
> +	add	r3, r1, #TI_TP_VALUE
>    ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
>    THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
>    THUMB(	str	sp, [ip], #4		   )
> @@ -736,6 +736,8 @@ ENTRY(__switch_to)
>   #ifdef CONFIG_CPU_USE_DOMAINS
>   	ldr	r6, [r2, #TI_CPU_DOMAIN]
>   #endif
> +	get_tls	r3, r4
> +	add	r3, r2, #TI_TP_VALUE
>   	set_tls	r3, r4, r5
>   #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
>   	ldr	r7, [r2, #TI_TASK]
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 047d3e4..a13bbc8 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -36,6 +36,7 @@
>   #include <asm/cacheflush.h>
>   #include <asm/idmap.h>
>   #include <asm/processor.h>
> +#include <asm/tls.h>
>   #include <asm/thread_notify.h>
>   #include <asm/stacktrace.h>
>   #include <asm/mach/time.h>
> @@ -395,7 +396,10 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
>   	clear_ptrace_hw_breakpoint(p);
>   
>   	if (clone_flags & CLONE_SETTLS)
> -		thread->tp_value = childregs->ARM_r3;
> +	{
> +		thread->tp_value[0] = childregs->ARM_r3;
> +		get_tpidrurw(&thread->tp_value[1]);
> +	}

This isn't quite right - the re-reading of tpidrurw should
be independent of CLONE_SETTLS. We should update tpidrurw
from userspace in all cases.

The following is what I've been looking at/testing...
It works on V7 and I've build tested it for 1136 - I would've
sent it yesterday but was getting things set up for testing on
1136 (v6 not k)

----8<-------
>From bd3fe4055777b404a1635f366483637fd0cfa35a Mon Sep 17 00:00:00 2001
From: Jonathan Austin <jonathan.austin at arm.com>
Date: Fri, 8 Feb 2013 15:55:12 +0000
Subject: [PATCH] ARM: tls: context switch user writeable TLS register
 TPIDRURW

Since commit 6a1c53124aa1 ("ARM: 7403/1: tls: remove covert channel via
TPIDRURW") we have zeroed the user writeable TLS register to prevent it
from being used as a covert channel between two tasks.

However, it turns out that the wine guys would rather we actually
switched the register so that WinRT applications can use it to store a
pointer to their `thread environment block (TEB)'.

This patch implements TPIDRURW context-switching for cpus implementing
the register. Unlike the TPIDRURO, which is already switched, the TPIDRURW
can be updated from userspace so needs careful treatment in the case that we
modify TPIDRURW and call fork(). If no context switch occurs between these
two events then the thread_info struct that we use to construct the child
will have the old, stale, TPIDRURW value. To avoid this we must always read
TPIDRURW in copy_thread.

This patch is extended from an earlier version by Will Deacon in order to:
- Save TPIDRURW at context switch
- Deal with the race condition described above, including adding C-getters

Reported-by: Andre Hentschel <nerv at dawncrow.de>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
---
 arch/arm/include/asm/thread_info.h |    2 +-
 arch/arm/include/asm/tls.h         |   51 +++++++++++++++++++++++++++++-------
 arch/arm/kernel/Makefile           |    2 +-
 arch/arm/kernel/entry-armv.S       |    5 +++-
 arch/arm/kernel/process.c          |    4 ++-
 arch/arm/kernel/ptrace.c           |    2 +-
 arch/arm/kernel/tls.c              |   50 +++++++++++++++++++++++++++++++++++
 arch/arm/kernel/traps.c            |    4 +--
 8 files changed, 104 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/kernel/tls.c

diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f..d90be6d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];	/* TLS registers */
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..e292794 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -5,10 +5,19 @@
 	.macro set_tls_none, tp, tmp1, tmp2
 	.endm
 
+	.macro save_tlsuser_none, tp, tmp1, tmp2
+	.endm
+
 	.macro set_tls_v6k, tp, tmp1, tmp2
-	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	ldrd	\tmp1, \tmp2, [\tp]
+	mcr	p15, 0, \tmp1, c13, c0, 3	@ set user r/o TLS register
+	mcr	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
+	.endm
+
+	.macro save_tlsuser_v6k, tp, tmp1, tmp2
+	@ TPIDRURW can be updated from userspace, so we have to re-read it
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ load user r/w TLS register
+	str	\tmp2, [\tp, #4]
 	.endm
 
 	.macro set_tls_v6, tp, tmp1, tmp2
@@ -16,15 +25,26 @@
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
-	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	ldrned	\tmp1, \tmp2, [\tp]
+	ldreq	\tmp1, [\tp]
+	mcrne	p15, 0, \tmp1, c13, c0, 3	@ yes, set user r/o TLS register
+	mcrne	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
+	streq	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	.endm
+
+	.macro save_tlsuser_v6, tp, tmp1, tmp2
+	@ TPIDRURW can be updated from userspace, so we have to re-read it
+	ldr	\tmp1, =elf_hwcap
+	ldr	\tmp1, [\tmp1, #0]
+	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ read user r/w TLS register
+	strne	\tmp2, [\tp, #4]		@ save in to thread_info
 	.endm
 
 	.macro set_tls_software, tp, tmp1, tmp2
-	mov	\tmp1, #0xffff0fff
-	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
+	ldr	\tmp1, [\tp]
+	mov	\tmp2, #0xffff0fff
+	str	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
 #endif
 
@@ -32,18 +52,31 @@
 #define tls_emu		1
 #define has_tls_reg		1
 #define set_tls		set_tls_none
+#define save_tlsuser	save_tlsuser_none
+#define get_tlsuser	get_tlsuser_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
 #define set_tls		set_tls_v6
+#define save_tlsuser	save_tlsuser_v6
+#define get_tlsuser	get_tlsuser_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
 #define set_tls		set_tls_v6k
+#define save_tlsuser	save_tlsuser_v6k
+#define get_tlsuser	get_tlsuser_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
 #define set_tls		set_tls_software
+#define save_tlsuser	save_tlsuser_none
+#define get_tlsuser	get_tlsuser_none
 #endif
 
+#ifndef __ASSEMBLY__
+extern unsigned long get_tlsuser_none(void);
+extern unsigned long get_tlsuser_v6(void);
+extern unsigned long get_tlsuser_v6k(void);
+#endif
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..4e1114c 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -17,7 +17,7 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 		   process.o ptrace.o return_address.o sched_clock.o \
-		   setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
+		   setup.o signal.o stacktrace.o sys_arm.o time.o tls.o traps.o
 
 obj-$(CONFIG_ATAGS)		+= atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)	+= atags_proc.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..66adb0c 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,7 +728,7 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
+	add	r3, r1, #TI_TP_VALUE
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
@@ -736,6 +736,9 @@ ENTRY(__switch_to)
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
+	/* Save the user-writeable tls register */
+	save_tlsuser	r3, r4, r5
+	add	r3, r2, #TI_TP_VALUE
 	set_tls	r3, r4, r5
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e4..24dbc72 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -395,7 +396,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+		thread->tp_value[0] = childregs->ARM_r3;
+	thread->tp_value[1] = get_tlsuser();
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/tls.c b/arch/arm/kernel/tls.c
new file mode 100644
index 0000000..1627f5b
--- /dev/null
+++ b/arch/arm/kernel/tls.c
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/kernel/tls.c
+ *
+ * Copyright (C) 2013 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <asm/tls.h>
+
+/*
+ * Access to the TPIDRURW register, with full certainty that it exists.
+ */
+unsigned long get_tlsuser_v6k(void)
+{
+	unsigned long v;
+	asm("mrc        p15, 0, %0, c13, c0, 2\n" : "=r" (v));
+	return v;
+}
+
+/*
+ * Access to the TPIDRURW register if it exists.
+ */
+unsigned long get_tlsuser_v6(void)
+{
+	unsigned long v = 0;
+	if (elf_hwcap & HWCAP_TLS)
+		asm("mrc        p15, 0, %0, c13, c0, 2\n" : "=r" (v));
+	return v;
+}
+
+/*
+ * Dummy access for the case that TLS is emulated in software
+ */
+unsigned long get_tlsuser_none(void)
+{
+	return 0;
+}
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c08911..f9d6259 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }
-- 
1.7.9.5




From s.hauer at pengutronix.de  Fri May  3 05:39:48 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 May 2013 11:39:48 +0200
Subject: Freescale imx35: sgtl5000 codec not working over i2c
In-Reply-To: <20130502204020.0462f080@jobraun>
References: <20130502200024.72c112cc@jobraun>
 <20130502181821.GC31135@pengutronix.de>
 <20130502204020.0462f080@jobraun>
Message-ID: <20130503093948.GT32299@pengutronix.de>

On Thu, May 02, 2013 at 08:40:20PM +0200, Johannes Braun wrote:
> Hello Sascha,
> 
> > On Thu, May 02, 2013 at 08:00:24PM +0200, Johannes Braun wrote:
> > > Hello @all,
> > > 
> > > I hope this is the right place for my problem. Currently I am
> > > trying to get a sigmatel sgtl5000 codec to work on a Freescale
> > > imx35 based board. I am using a vanilla kernel 3.7.10. The codec is
> > > connected via i2c. I configured the i2c device
> > > in /arch/arm/mach-imx/mach-proxmobil2.c. Proxmobil2 is the name of
> > > our device. Here is the part which configures the i2c device and
> > > the bus.
> > > 
> > > static const struct imxi2c_platform_data mx35_prox2_i2c0_data
> > > 	__initconst = {
> > >         .bitrate = 100000,
> > > };
> > > 
> > > imx35_add_imx_i2c0(&mx35_prox2_i2c0_data);
> > > 
> > > static struct i2c_board_info __initdata i2c_devices_prox2[] = {
> > >         {
> > >                 I2C_BOARD_INFO("imx-audio-sgtl5000", 0x0a),
> > >         },
> > 
> > The driver matches "sgtl5000", not "imx-audio-sgtl5000".
> 
> I tried "sgtl5000" and "fsl", both without success.

With "sgtl5000" at least sgtl5000_i2c_probe should be called. Is the
i.MX I2C driver registered correctly. What's in /sys/bus/i2c/devices/?

> 
> As I wrote before, my board is based on the very old imx35 processor
> platform and I think this processor type does not support device tree
> out of the box? Or is it possible to use a device tree with an imx35?

you won't need much more than something similar to
arch/arm/mach-imx/imx25-dt.c and an auxdata table for the clock lookups.
There even is pinctrl support.

That said, your actual problem won't be related to that.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From mkl at pengutronix.de  Fri May  3 05:53:47 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Fri, 03 May 2013 11:53:47 +0200
Subject: [PATCH,
 RFC 01/22] can: move CONFIG_HAVE_CAN_FLEXCAN out of CAN_DEV
In-Reply-To: <1367507786-505303-2-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-2-git-send-email-arnd@arndb.de>
Message-ID: <5183892B.8020400@pengutronix.de>

On 05/02/2013 05:16 PM, Arnd Bergmann wrote:
> CONFIG_HAVE_CAN_FLEXCAN is a silect symbol that is meant to be selected
> by platforms that support this driver, but that is not possible without
> also selecting CAN_DEV, unless we move it out of the "if CAN_DEV"
> section of the Kconfig file.
> 
> warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 &&
>  IMX_HAVE_PLATFORM_FLEXCAN && SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
>  which has unmet direct dependencies (NET && CAN && CAN_DEV)

With the advent of multi platform kernels I like to get rid of
HAVE_CAN_FLEXCAN completely.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From nsekhar at ti.com  Fri May  3 05:55:32 2013
From: nsekhar at ti.com (Sekhar Nori)
Date: Fri, 3 May 2013 15:25:32 +0530
Subject: [PATCH 0/6] Davinci fbdev driver and enable it for DMx platform
In-Reply-To: <CA+V-a8sLD2dP1RLb8ibZDOsLCP8hhMNUTr-zzU1zx_2ALDaDrg@mail.gmail.com>
References: <1366804808-22720-1-git-send-email-prabhakar.csengg@gmail.com>
 <1780031.B4OAypccep@avalon>
 <CA+V-a8sLD2dP1RLb8ibZDOsLCP8hhMNUTr-zzU1zx_2ALDaDrg@mail.gmail.com>
Message-ID: <51838994.7070805@ti.com>

On 4/26/2013 11:16 AM, Prabhakar Lad wrote:
> Hi Laurent,
> 
> On Thu, Apr 25, 2013 at 2:32 AM, Laurent Pinchart
> <laurent.pinchart at ideasonboard.com> wrote:
>> Hi Prabhakar,
>>
>> Thank you for the patch.
>>
>> On Wednesday 24 April 2013 17:30:02 Prabhakar Lad wrote:
>>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>>>
>>> This patch series adds an fbdev driver for Texas
>>> Instruments Davinci SoC.The display subsystem consists
>>> of OSD and VENC, with OSD supporting 2 RGb planes and
>>> 2 video planes.
>>> http://focus.ti.com/general/docs/lit/
>>> getliterature.tsp?literatureNumber=sprue37d&fileType=pdf
>>>
>>> A good amount of the OSD and VENC enabling code is
>>> present in the kernel, and this patch series adds the
>>> fbdev interface.
>>>
>>> The fbdev driver exports 4 nodes representing each
>>> plane to the user - from fb0 to fb3.
>>
>> The obvious question is: why not a KMS driver instead ? :-)
>>
> I did go through the KMS model (thanks for pointing to your work and the video)
> and it looks like this would require a fair amount of development, at this point
> of time I would go with the current implementation and revisit on KMS model
> at later point of time.

But I doubt you will be able to sneak a new fbdev driver through. Last
time I heard, Andrew is only taking in fixes not new features.

Thanks,
Sekhar


From linux at arm.linux.org.uk  Fri May  3 05:55:47 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 10:55:47 +0100
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <5183819E.50308@arm.com>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
 <5182C480.3080001@dawncrow.de> <5183819E.50308@arm.com>
Message-ID: <20130503095547.GD18614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 10:21:34AM +0100, Jonathan Austin wrote:
>  	.macro set_tls_v6k, tp, tmp1, tmp2
> -	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
> -	mov	\tmp1, #0
> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> +	ldrd	\tmp1, \tmp2, [\tp]
> +	mcr	p15, 0, \tmp1, c13, c0, 3	@ set user r/o TLS register
> +	mcr	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register

So we're still back at stalling the pipeline with result delays on older
CPUs?

> +	.endm
> +
> +	.macro save_tlsuser_v6k, tp, tmp1, tmp2
> +	@ TPIDRURW can be updated from userspace, so we have to re-read it
> +	mrc	p15, 0, \tmp2, c13, c0, 2	@ load user r/w TLS register
> +	str	\tmp2, [\tp, #4]
>  	.endm
>  
>  	.macro set_tls_v6, tp, tmp1, tmp2
> @@ -16,15 +25,26 @@
>  	ldr	\tmp1, [\tmp1, #0]
>  	mov	\tmp2, #0xffff0fff
>  	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> -	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> -	movne	\tmp1, #0
> -	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> -	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> +	ldrned	\tmp1, \tmp2, [\tp]
> +	ldreq	\tmp1, [\tp]
> +	mcrne	p15, 0, \tmp1, c13, c0, 3	@ yes, set user r/o TLS register
> +	mcrne	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
> +	streq	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0

This at least is better.

> +	.endm
> +
> +	.macro save_tlsuser_v6, tp, tmp1, tmp2
> +	@ TPIDRURW can be updated from userspace, so we have to re-read it
> +	ldr	\tmp1, =elf_hwcap
> +	ldr	\tmp1, [\tmp1, #0]
> +	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?

But this isn't - this involves two delays.

> +	mrcne	p15, 0, \tmp2, c13, c0, 2	@ read user r/w TLS register
> +	strne	\tmp2, [\tp, #4]		@ save in to thread_info
>  	.endm
>  
>  	.macro set_tls_software, tp, tmp1, tmp2
> -	mov	\tmp1, #0xffff0fff
> -	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
> +	ldr	\tmp1, [\tp]
> +	mov	\tmp2, #0xffff0fff
> +	str	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
>  	.endm
>  #endif
>  
> @@ -32,18 +52,31 @@
>  #define tls_emu		1
>  #define has_tls_reg		1
>  #define set_tls		set_tls_none
> +#define save_tlsuser	save_tlsuser_none
> +#define get_tlsuser	get_tlsuser_none
>  #elif defined(CONFIG_CPU_V6)
>  #define tls_emu		0
>  #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
>  #define set_tls		set_tls_v6
> +#define save_tlsuser	save_tlsuser_v6
> +#define get_tlsuser	get_tlsuser_v6
>  #elif defined(CONFIG_CPU_32v6K)
>  #define tls_emu		0
>  #define has_tls_reg		1
>  #define set_tls		set_tls_v6k
> +#define save_tlsuser	save_tlsuser_v6k
> +#define get_tlsuser	get_tlsuser_v6k
>  #else
>  #define tls_emu		0
>  #define has_tls_reg		0
>  #define set_tls		set_tls_software
> +#define save_tlsuser	save_tlsuser_none
> +#define get_tlsuser	get_tlsuser_none
>  #endif

This separation of setting and saving the TLS value is actually quite
silly.  They're called from the same place, so lets just call it
"switch_tls" instead.

Here's just the assembly bits doing that - this is totally untested
of course:

 arch/arm/include/asm/tls.h   |   28 +++++++++++++++-------------
 arch/arm/kernel/entry-armv.S |    4 ++--
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..9c377f1 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,29 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-	.macro set_tls_none, tp, tmp1, tmp2
+	.macro switch_tls_none, base, tp, trw, tmp1, tmp2
 	.endm
 
-	.macro set_tls_v6k, tp, tmp1, tmp2
+	.macro switch_tls_v6k, base, tp, trw, tmp1, tmp2
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
 	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	mcr	p15, 0, \trw, c13, c0, 2	@ and the user r/w register
+	str	\tmp2, [\base, #TI_TP_VALUE + 4]@ save it
 	.endm
 
-	.macro set_tls_v6, tp, tmp1, tmp2
+	.macro switch_tls_v6, base, tp, trw, tmp1, tmp2
 	ldr	\tmp1, =elf_hwcap
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
 	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	mcrne	p15, 0, \trw, c13, c0, 2	@ set user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4]@ save it
 	.endm
 
-	.macro set_tls_software, tp, tmp1, tmp2
+	.macro switch_tls_software, base, tp, trw, tmp1, tmp2
 	mov	\tmp1, #0xffff0fff
 	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
@@ -31,19 +33,19 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
-#define set_tls		set_tls_none
+#define switch_tls	switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
-#define set_tls		set_tls_v6
+#define switch_tls	switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
-#define set_tls		set_tls_v6k
+#define switch_tls	switch_tls_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
-#define set_tls		set_tls_software
+#define switch_tls	switch_tls_software
 #endif
 
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..81a08b1 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,15 +728,15 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
+	ldrd	r4, r5, [r2, #TI_TP_VALUE]
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-	set_tls	r3, r4, r5
+	switch_tls r2, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
 	ldr	r8, =__stack_chk_guard



From sebastian.hesselbarth at gmail.com  Fri May  3 05:58:03 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 03 May 2013 11:58:03 +0200
Subject: [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
In-Reply-To: <20130503050632.GC24965@lunn.ch>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-3-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130503050632.GC24965@lunn.ch>
Message-ID: <51838A2B.50302@gmail.com>

On 05/03/2013 07:06 AM, Andrew Lunn wrote:
> On Fri, May 03, 2013 at 01:48:36AM +0200, Sebastian Hesselbarth wrote:
>> To allow to move to orion irqchip driver, existing legacy devices
>> have to map their irqs. This patch adds init code to map the
>> corresponding irqs. It will vanish as soon as there is true device tree
>> support for mv643xx_eth.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>> ---
>> Changelog:
>> v1->v2:
>> - split off DT changes (Suggested by Jason Cooper)
>>
>> Cc: Grant Likely<grant.likely at linaro.org>
>> Cc: Rob Herring<rob.herring at calxeda.com>
>> Cc: Rob Landley<rob at landley.net>
>> Cc: Thomas Gleixner<tglx at linutronix.de>
>> Cc: Russell King<linux at arm.linux.org.uk>
>> Cc: Arnd Bergmann<arnd at arndb.de>
>> Cc: Jason Cooper<jason at lakedaemon.net>
>> Cc: Andrew Lunn<andrew at lunn.ch>
>> Cc: Jason Gunthorpe<jgunthorpe at obsidianresearch.com>
>> Cc: Thomas Petazzoni<thomas.petazzoni at free-electrons.com>
>> Cc: Gregory Clement<gregory.clement at free-electrons.com>
>> Cc: Ezequiel Garcia<ezequiel.garcia at free-electrons.com>
>> Cc: Jean-Francois Moine<moinejf at free.fr>
>> Cc: devicetree-discuss at lists.ozlabs.org
>> Cc: linux-doc at vger.kernel.org
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: linux-kernel at vger.kernel.org
>> ---
>>   arch/arm/mach-dove/board-dt.c |   31 ++++++++++++++++++++++++++++++-
>>   1 file changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
>> index fbde1dd..9df6dd7 100644
>> --- a/arch/arm/mach-dove/board-dt.c
>> +++ b/arch/arm/mach-dove/board-dt.c
>> @@ -12,6 +12,7 @@
>>   #include<linux/clk-provider.h>
>>   #include<linux/clk/mvebu.h>
>>   #include<linux/of.h>
>> +#include<linux/of_irq.h>
>>   #include<linux/of_platform.h>
>>   #include<linux/platform_data/usb-ehci-orion.h>
>>   #include<asm/hardware/cache-tauros2.h>
>> @@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
>>   	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
>>   };
>>
>> +#define DOVE_GE00_PHYS_BASE	0xf1070000
>> +
>> +static void __init dove_legacy_ge00_init(void)
>> +{
>> +	struct device_node *np = of_find_compatible_node(NULL, NULL,
>> +					 "marvell,mv643xx-eth-block");
>> +	int irq_sum, irq_err;
>> +
>> +	if (!np)
>> +		return;
>> +
>> +	irq_sum = irq_of_parse_and_map(np, 0);
>> +	if (!irq_sum) {
>> +		pr_err("%s: missing sum irq\n", np->full_name);
>> +		return;
>> +	}
>> +
>> +	irq_err = irq_of_parse_and_map(np, 1);
>> +	if (!irq_err) {
>> +		pr_err("%s: missing err irq\n", np->full_name);
>> +		return;
>> +	}
>> +
>> +	/* legacy ge00_init wants phys base */
>> +	orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
>> +			irq_sum, irq_err, 1600);
>> +}
>
> Hi Sebastian
>
> I know the above code is throw away, but it might help with getting
> Kirkwood, Orion5x, mv78xx00 supported if we refactor this code and
> move most of it into plat-orion/common.c. I could imaging a function
>
> orion_ge00_irq_init(struct mv643xx_eth_platform_data *eth_data,
>                      unsigned long mapbase, unsigned int tx_csum_limit)
>
> which does the irq lookup and then calls orion_ge00_init().

Andrew,

sure. Feel free to move legacy code to where all SoCs can use it.

> Jason: what is the status of the ethernet driver conversion to DT?
> Will it get merged this week, or is it material for the next merge
> window?

What I remember from Florian's work it was close to be released. I
never saw Florian sending an update to his patches, maybe he ran out
of time?

I guess DT timer will be a quick patch when we have all SoCs running
on DT irqchip and maybe Florian can update his patches even before we
sort out Thomas request. Then we could also merge DT timer within this
patch set and get rid of legacy helpers before we even introduce them.

Sebastian



From sebastian.hesselbarth at gmail.com  Fri May  3 06:02:02 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 03 May 2013 12:02:02 +0200
Subject: [PATCH v2] clk: si5351: Allow user to define disabled state for
 every clock output
In-Reply-To: <1367559207-20086-1-git-send-email-marek.belisko@streamunlimited.com>
References: <1367559207-20086-1-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <51838B1A.4010803@gmail.com>

On 05/03/2013 07:33 AM, Marek Belisko wrote:
> From: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>
> This patch adds platform data and DT bindings to allow to overwrite
> the stored disabled state for each clock output.
>
> Signed-off-by: Marek Belisko<marek.belisko at streamunlimited.com>
> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> ---
> Changes from v1->v2:
> Sebastian Hesselbarth send me updated version of patch which was based
> on v1. Resending with updates.

Marek,

it is ok to be a little bit more noisy about changes. But as I took
your v1 and did it, here is the Changelog:

- add helper to set disabled state for clkout
- make disabled-state property behave like other properties, i.e.
   only overwrite disabled state when set through platform_data or DT

Sebastian


From catalin.marinas at arm.com  Fri May  3 06:02:42 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 3 May 2013 11:02:42 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130502193835.GA29144@schnuecks.de>
References: <20130418112201.GQ14496@n2100.arm.linux.org.uk>
 <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
Message-ID: <20130503100242.GB29962@arm.com>

On Thu, May 02, 2013 at 08:38:36PM +0100, Simon Baatz wrote:
> On Thu, May 02, 2013 at 10:54:31AM +0100, Catalin Marinas wrote:
> > On Wed, May 01, 2013 at 08:04:41PM +0100, Simon Baatz wrote:
> > > On Wed, May 01, 2013 at 03:22:06PM +0100, Catalin Marinas wrote:
> > > > On Tue, Apr 30, 2013 at 10:04:03PM +0100, Simon Baatz wrote:
> > > > > On Tue, Apr 30, 2013 at 12:22:25PM +0100, Catalin Marinas wrote:
> > > > > > On Sun, Apr 21, 2013 at 11:06:30PM +0100, Simon Baatz wrote:
> > > > > > > On Thu, Apr 18, 2013 at 02:51:04PM +0100, Catalin Marinas wrote:
> > > > > > > > On Thu, Apr 18, 2013 at 12:40:16PM +0100, Jason Cooper wrote:
> > > > > ...
> > > > > > > 
> > > > > > > It is not the driver itself which is using the API, it is the
> > > > > > > generic scatterlist memory iterator. And I don't think that this is
> > > > > > > wrong, as I have tried to explain in [1].
> > > > > > 
> > > > > > Trying to remember what we've discussed over the past months on this
> > > > > > topic. It looks like sg_miter_stop() does the right thing in calling
> > > > > > flush_kernel_dcache_page(). Commit f8b63c1 (ARM: 6382/1: Remove
> > > > > > superfluous flush_kernel_dcache_page()) removed this function entirely.
> > > > > > The code previously had this comment - /* highmem pages are always
> > > > > > flushed upon kunmap already */ which I think it wasn't fully correct
> > > > > > either. The kunmap_atomic() flushes the caches but kunmap() doesn't, so
> > > > > > I suspect we only get the flushing if SG_MITER_ATOMIC.
> > > > > > 
> > > > > > So it looks to me like flush_kernel_dcache_page() should be implemented
> > > > > > even for highmem pages (with VIVT or aliasing VIPT, at least for non
> > > > > > kmap_atomic addresses by checking for FIXADDR_START). If highmem is
> > > > > > disabled, I suspect we still need this function since the calling code
> > > > > > doesn't care whether kmap/kunmap was a no-op. But can we keep it as a
> > > > > > simple call to __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE)?
> > > > > 
> > > > > My first version ([1]) had:
> > > > > 
> > > > > 	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
> > > > > 		__flush_kernel_dcache_page(page);
> > > > > 
> > > > > If I understand this correctly, you are proposing to remove the
> > > > > highmem exclusion.
> > > > 
> > > > The highmem exclusion may have been there originally because of a
> > > > comment suggesting that kunmap() does the flushing. This is the case
> > > > only for kunmap_atomic() AFAICT (and maybe we could remove that as well
> > > > and rely on flush_kernel_dcache_page() being called).
> > > > 
> > > > > And then in __flush_kernel_dcache_page():
> > > > > 
> > > > > 	mapping = page_mapping(page);
> > > > > 
> > > > > 	if (!mapping || mapping_mapped(mapping))
> > > > > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > > > > 
> > > > > I still prefer to have this condition here to avoid the flush when
> > > > > there is no user mapping at all.  This is handled by lazy flushing
> > > > > and is probably the most common case anyway (given how many people
> > > > > seem to be affected by this problem).
> > > > 
> > > > Looking at the old thread, you said there is a case when this condition
> > > > is not true (O_DIRECT case). If that's for a page cache page, then we
> > > > can handle it lazily (for anonymous pages I don't think we can rely on
> > > > lazy flushing since the kernel does not guarantee the clearing of the
> > > > PG_arch_1 bit).
> > > 
> > > As Russel pointed out in a comment to a later version of the patch,
> > > PG_arch_1 makes only sense for page cache pages. The condition above
> > > is ok from my point of view (it is based on what flush_dcache_page()
> > > uses):
> > > 
> > > - Page cache page without user space mapping:
> > > mapping != NULL and mapping_mapped() == 0
> > > 
> > > -> no flush here; lazy flush based on PG_arch_1 later if needed (we
> > >    rely on the proper initialization of the page to "dirty" here.)
> > 
> > Indeed.
> > 
> > > - Page cache page with user space mapping:
> > > mapping != NULL and mapping_mapped() != 0
> > > 
> > > -> kernel mapping flushed here (user mapping can be assumed to be clean)
> > 
> > We had similar thoughts for AArch64 here and decided it's not needed, it
> > can just clear the PG_arch_1 bit and do it lazily (patches not pushed
> > yet, need more testing). This assumes that even if mapping_mapped(), the
> > page is not actually mapped in user space and we eventually get a
> > set_pte_at() call. That's what powerpc is doing.
> 
> For arm64 only I-/D-cache coherency is relevant, right?

Yes. Same for 32-bit ARMv7 or non-aliasing D-cache on ARMv6.

> In this case,
> that may be right (but you may want to have a look at what
> xol_get_insn_slot() in kernel/events/uprobes.c does.  I don't know
> what kind of pages it handles, but this looks suspicious. And I think
> uprobes are also available for powerpc).

It is suspicious indeed and even the author is unsure about using the
right API. Should it rather use copy_to_user_page? I'm not familiar with
uprobes.

> However, if you can have aliases in D-cache this is needed.  See
> below to trigger this on pages that are already mapped
> to user space (direct I/O into a memory mapped file).

You are probably right, for direct I/O and aliases in the D-cache it
needs to flush. The documentation for flush_dcache_page() states that it
can also be called when the kernel is about to read from a page cache
page (potentially mapped into user space).

> > > - Anonymous page:
> > > mapping == NULL
> > > 
> > > -> kernel mapping flushed here (user mapping can be assumed to be clean)
> > 
> > I don't think it should care about anonymous pages at all. I put a
> > WARN_ON(!mapping) in flush_dcache_page() and it hasn't triggered yet,
> > though not intensive testing.
> 
> I assume that you inhibited the call to flush_dcache_page() in
> __get_user_pages() for anon pages.  Otherwise, you will be flooded
> with warnings.

I haven't done any stress testing so I don't think I hit this code path,
so no warning. But yes, it should have triggered. Anyway, in this case
flush_dcache_page() should have just ignored (clearing PG_arch_1 is
harmless anyway if we also ignore this bit in __sync_icache_dcache for
non-aliasing caches).

> DIY steps to produce both cases:
> (We will need software encryption, thus I need to remove the hardware
> encryption module mv_cesa on my hardware first)
> 
> # rmmod mv_cesa     
> # wget -O mapping_tests.c http://ubuntuone.com/0jF9fNsguN8BvI1Z8fsBVI
> # gcc -o mapping_tests mapping_tests.c
> # dd if=/dev/urandom of=map.out bs=4k count=10
> # dd if=/dev/urandom of=cdevice.img bs=4k count=10
> # losetup /dev/loop0 cdevice.img 
> # cryptsetup -c aes create c_sda2 /dev/loop0
> <enter any passphrase>
> # ./mapping_tests
> 
> cryptsetup will already trigger the warning and mapping_tests should
> flood your console.
>  
> Since flush_kernel_dcache_page() is supposed to handle user space
> pages, it must flush the kernel mapping in these cases.  Running the
> above on a device driver using an unpatched
> flush_kernel_dcache_page() yields:
> 
> # ./mapping_tests 
> Anonymous page: differs!
> User space mapped page: differs!

I haven't run the tests but I can see  why it fails without
flush_kernel_dcache_page(). So I think this function needs to be
implemented for aliasing VIPT or VIVT caches.

> It is even needed in flush_dcache_page() as long as everybody
> continues to use flush_dcache_page() instead of
> flush_kernel_dcache_page() when appropriate...
> (This is probably the main reason why the problem I reported is so
> uncommon: Everybody seems to use flush_dcache_page() and since it
> flushes the kernel mapping in these cases, everything is fine.)

That's why for non-aliasing VIPT we could make it just a clear_bit() and
let the callers fix their API usage.

> > > > > Additionally, although we can assume that the page is kmapped,
> > > > > page_address(page) can still be NULL for a highmem page, right?
> > > > 
> > > > It looks like kmap() always sets page_address(page) but I'm not sure
> > > > about kmap_atomic(), it doesn't seem to.
> > > 
> > > Hmm, in __flush_dcache_page() we have the following code to flush the
> > > kernel mapping:
> > > 
> > > void __flush_dcache_page(struct address_space *mapping, struct page *page)
> > > {
> > > 	/*
> > > 	 * Writeback any data associated with the kernel mapping of this
> > > 	 * page.  This ensures that data in the physical page is mutually
> > > 	 * coherent with the kernels mapping.
> > > 	 */
> > > 	if (!PageHighMem(page)) {
> > > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > > 	} else {
> > > 		void *addr = kmap_high_get(page);
> > > 		if (addr) {
> > > 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> > > 			kunmap_high(page);
> > > 		} else if (cache_is_vipt()) {
> > > 			/* unmapped pages might still be cached */
> > > 			addr = kmap_atomic(page);
> > > 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> > > 			kunmap_atomic(addr);
> > > 		}
> > > 	}
> > > ...
> > > 
> > > 
> > > We probably should reuse it in flush_kernel_dcache_page() to flush
> > > the kernel mapping. (The last else clause looks strange though)
> > 
> > I think it makes sense to reuse this logic in
> > flush_kernel_dcache_page(). If the page is already mapped with kmap,
> > then kmap_high_get() should return the actual address. If it was mapped
> > with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
> > clause and the additional kmap_atomic(). The cache_is_vipt() check is
> > useful because kunmap_atomic() would flush VIVT caches anyway.
> 
> Yes, but why don't we flush for VIPT _aliasing_ already in
> kunmap_atomic?

Some comment from Nico on the list, it seems that highmem does not work
with aliasing VIPT caches:

http://article.gmane.org/gmane.linux.ports.arm.kernel/85114

> Why do we need to do anything for non-aliasing VIPT here?

Do you mean __flush_dcache_page()? I don't think we need.

> > As for __flush_dcache_page() called from other places like
> > flush_dcache_page(), because of this 'else if' clause it looks like it
> > misses flushing unmapped highmem pages on VIVT cache.
> 
> How many users do we have with VIVT D-caches using highmem? (This is
> not a rhetorical questions, I have no idea.  However, I would assume
> that this use case is almost non-existent.)

I don't really know. Maybe Nico has more info.

So my proposal:

1. Non-aliasing VIPT - defer any D-cache flushing until
   __sync_icache_dcache() (and fix callers like uprobes)
2. Aliasing VIPT or VIVT - flush the aliases as before in
   flush_dcache_page()
3. Aliasing VIPT or VIVT - implement flush_kernel_dcache_page() for all
   pages (don't check for PageHighmem)
4. VIVT - remove cache flushing from kunmap_atomic and rely on
   flush_kernel_dcache_page()

I'm not entirely sure about 4 but at the moment kunmap() doesn't flush
caches, only kunmap_atomic() so it looks like an inconsistency.

-- 
Catalin


From sebastian.hesselbarth at gmail.com  Fri May  3 06:05:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 03 May 2013 12:05:40 +0200
Subject: [PATCH v2 2/2] clk: si5351: Set initial clkout rate when defined
 in platform data.
In-Reply-To: <1367560403-21685-2-git-send-email-marek.belisko@streamunlimited.com>
References: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
 <1367560403-21685-2-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <51838BF4.9050207@gmail.com>

On 05/03/2013 07:53 AM, Marek Belisko wrote:
> Signed-off-by: Marek Belisko<marek.belisko at streamunlimited.com>
> ---
> Changes v1->v2:
> - update commit message and comment to refer to platform data not DT

Marek,

except that the commit msg itself is very short (there is no!) you can
add my

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>

Next time sending patches for clk-si5351, please ensure you are using
get_maintainers.pl and add me to the list of people to Cc also.

Sebastian

>   drivers/clk/clk-si5351.c |   10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index cf39e53..24f5536 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client,
>   			return -EINVAL;
>   		}
>   		drvdata->onecell.clks[n] = clk;
> +
> +		/* set initial clkout rate */
> +		if (pdata->clkout[n].rate != 0) {
> +			int ret;
> +			ret = clk_set_rate(clk, pdata->clkout[n].rate);
> +			if (ret != 0) {
> +				dev_err(&client->dev, "Cannot set rate : %d\n",
> +					ret);
> +			}
> +		}
>   	}
>
>   	ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,



From laurent.pinchart at ideasonboard.com  Fri May  3 06:06:24 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Fri, 03 May 2013 12:06:24 +0200
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <5182AF83.4080705@wwwdotorg.org>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <201304300004.20320.arnd@arndb.de> <5182AF83.4080705@wwwdotorg.org>
Message-ID: <1956593.M6NmITdEKh@avalon>

Hi Stephen,

On Thursday 02 May 2013 12:25:07 Stephen Warren wrote:
> On 04/29/2013 04:04 PM, Arnd Bergmann wrote:
> > On Monday 29 April 2013, Laurent Pinchart wrote:
> >> On Monday 29 April 2013 23:31:30 Tomasz Figa wrote:
> >>> Good point. Stephen, would it be a problem to make this a KMS driver
> >>> instead? Old fbdev API could be emulated on top of it, until it goes out
> >>> of use, couldn't it?
> >> 
> >> There's already an fbdev emulation layer in KMS, for such a simple use
> >> case it will work fine.
> > 
> > I suggested the same to Stephen when he first brought up this driver.
> > Unfortunately his attempt to create a simple KMS driver resulted in a
> > significantly larger driver than the one he did for the framebuffer
> > interface. This means that either Stephen did something really wrong
> > in his attempt, or the KMS interface isn't as good as it should be
> > if we want to move people away from frame buffer drivers.
> 
> Well, I didn't actually attempt to write the KMS driver; I simply took a
> look at existing KMS drivers (and perhaps some stub KMS driver; I forget
> right now) to see what it'd take, and it looked quite scary.
> 
> The other issue is that the KMS semantics appear to desire that the
> driver allocate FB memory from some pool, and then point the display
> scanout at the allocated memory. However, this driver's semantics are
> that some other entity has allocated and reserved some memory region for
> scanout, and the simple FB driver exists solely to scribble to that
> memory region. Rob Clark said the thought this could be handled by
> writing a custom memory allocator to support this, but it seemed a
> little pointless to write a whole memory allocator when the existing FB
> interface allows the driver to just set a struct member to the address
> and be done with it.

KMS handles frame buffers through two objects, a GEM object that represents a 
piece of memory and a frame buffer object that represents, well, a frame 
buffer :-)

GEM objects management requires an allocator, and frame buffers reference one 
or more GEM objects to model the frame buffer memory. As allocating new GEM 
objects isn't possible in this case, the driver could create a GEM object and 
a frame buffer at initialization time, and implement GEM allocation stubs that 
would simply return an error unconditionally.

-- 
Regards,

Laurent Pinchart



From prabhakar.csengg at gmail.com  Fri May  3 06:15:44 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 3 May 2013 15:45:44 +0530
Subject: [PATCH 0/6] Davinci fbdev driver and enable it for DMx platform
In-Reply-To: <51838994.7070805@ti.com>
References: <1366804808-22720-1-git-send-email-prabhakar.csengg@gmail.com>
 <1780031.B4OAypccep@avalon>
 <CA+V-a8sLD2dP1RLb8ibZDOsLCP8hhMNUTr-zzU1zx_2ALDaDrg@mail.gmail.com>
 <51838994.7070805@ti.com>
Message-ID: <CA+V-a8tM=VxvCt5dvbLSJz-pz7OS88QaHJ9r_Y+ysxP_JUzn2Q@mail.gmail.com>

On Fri, May 3, 2013 at 3:25 PM, Sekhar Nori <nsekhar at ti.com> wrote:
> On 4/26/2013 11:16 AM, Prabhakar Lad wrote:
>> Hi Laurent,
>>
>> On Thu, Apr 25, 2013 at 2:32 AM, Laurent Pinchart
>> <laurent.pinchart at ideasonboard.com> wrote:
>>> Hi Prabhakar,
>>>
>>> Thank you for the patch.
>>>
>>> On Wednesday 24 April 2013 17:30:02 Prabhakar Lad wrote:
>>>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>>>>
>>>> This patch series adds an fbdev driver for Texas
>>>> Instruments Davinci SoC.The display subsystem consists
>>>> of OSD and VENC, with OSD supporting 2 RGb planes and
>>>> 2 video planes.
>>>> http://focus.ti.com/general/docs/lit/
>>>> getliterature.tsp?literatureNumber=sprue37d&fileType=pdf
>>>>
>>>> A good amount of the OSD and VENC enabling code is
>>>> present in the kernel, and this patch series adds the
>>>> fbdev interface.
>>>>
>>>> The fbdev driver exports 4 nodes representing each
>>>> plane to the user - from fb0 to fb3.
>>>
>>> The obvious question is: why not a KMS driver instead ? :-)
>>>
>> I did go through the KMS model (thanks for pointing to your work and the video)
>> and it looks like this would require a fair amount of development, at this point
>> of time I would go with the current implementation and revisit on KMS model
>> at later point of time.
>
> But I doubt you will be able to sneak a new fbdev driver through. Last
> time I heard, Andrew is only taking in fixes not new features.
>
Then we have no choice left and go with KMS driver itself though it would take
some time since KMS is a new inclusion into DRM.

Regards,
--Prabhakar


From stefano.stabellini at eu.citrix.com  Fri May  3 06:29:14 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 3 May 2013 11:29:14 +0100
Subject: [Xen-devel] [PATCH 2/3] xen: move do_stolen_accounting to
 drivers/xen/time.c
In-Reply-To: <1367569605.28742.28.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <5182B532.10607@codeaurora.org>
 <1367569605.28742.28.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305031118080.5398@kaball.uk.xensource.com>

On Fri, 3 May 2013, Ian Campbell wrote:
> On Thu, 2013-05-02 at 19:49 +0100, Christopher Covington wrote:
> > Hi Stefano,
> > 
> > On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> > > Move do_stolen_accounting, xen_vcpu_stolen and related functions and
> > > static variables to common code (drivers/xen/time.c).
> > > 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > ---
> > >  arch/x86/xen/time.c   |  127 +-------------------------------------------
> > 
> > In going through some of the code, it looked like there might be a few little
> > bits that you might be interested in pulling out of arch/ia64/xen/time.c as well.
> 
> ia64 in the hypervisor was deprecated and with the 4.3 release has been
> removed.
> 
> AFAIK ia64/Xen support has been broken in the mainline kernel for year.

Yes, that's why it didn't occur to me to do anything about it.

Also, the ia64 code differs from the x86 code, I can't just replace it
with the newly introduced common code unfortunately.


From lee.jones at linaro.org  Fri May  3 06:38:19 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 11:38:19 +0100
Subject: [PATCH 3/4] mmc: mmci: Ensure return value of regulator_enable()
 is checked
In-Reply-To: <CAPDyKFqKP0sSBwZtcnH4tfPxSik5+GOVE-6tTBYaK5Qhvr3=4A@mail.gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-4-git-send-email-lee.jones@linaro.org>
 <CAPDyKFr60-nuh-BFsWtFhNeqUmswKC4hL4mw-gDhiqLmarvEDA@mail.gmail.com>
 <20130503081633.GD24153@gmail.com>
 <CAPDyKFqKP0sSBwZtcnH4tfPxSik5+GOVE-6tTBYaK5Qhvr3=4A@mail.gmail.com>
Message-ID: <20130503103819.GE24153@gmail.com>

On Fri, 03 May 2013, Ulf Hansson wrote:

> On 3 May 2013 10:16, Lee Jones <lee.jones at linaro.org> wrote:
> > On Fri, 03 May 2013, Ulf Hansson wrote:
> >
> >> On 2 May 2013 17:48, Lee Jones <lee.jones at linaro.org> wrote:
> >> > This patch suppresses the warning below:
> >> >
> >> > drivers/mmc/host/mmci.c: In function ?mmci_set_ios?:
> >> > drivers/mmc/host/mmci.c:1165:20: warning: ignoring return value of
> >> >         ?regulator_enable?, declared with attribute warn_unused_result
> >> >         [-Wunused-result]
> >> >
> >> > Cc: Russell King <linux at arm.linux.org.uk>
> >> > Cc: Chris Ball <cjb at laptop.org>
> >> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >> > ---
> >> >  drivers/mmc/host/mmci.c |    9 +++++++--
> >> >  1 file changed, 7 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> >> > index 375c109..f4f3038 100644
> >> > --- a/drivers/mmc/host/mmci.c
> >> > +++ b/drivers/mmc/host/mmci.c
> >> > @@ -1130,6 +1130,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> >> >         struct variant_data *variant = host->variant;
> >> >         u32 pwr = 0;
> >> >         unsigned long flags;
> >> > +       int ret;
> >> >
> >> >         pm_runtime_get_sync(mmc_dev(mmc));
> >> >
> >> > @@ -1161,8 +1162,12 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> >> >                 break;
> >> >         case MMC_POWER_ON:
> >> >                 if (!IS_ERR(mmc->supply.vqmmc) &&
> >> > -                   !regulator_is_enabled(mmc->supply.vqmmc))
> >>
> >> I realize that we actually have a bug here (and in the MMC_POWER_OFF
> >> mode as well).
> >>
> >> We shall not use regulator_is_enabled API as a trigger to enable/fetch
> >> a reference to the regulator, since it will only tell us if the
> >> regulator is enabled - hw wise.
> >> Instead we need a local variable in the mmci host struct keeping track
> >> if we have enabled the regulator. Do you mind fix this up in this
> >> patch as well since it is tightly coupled to the regulator handling!?
> >
> > IMHO I think that should be taken care of in a separate patch. This
> > patch only touches the line containing regulator_is_enabled() to
> > encompass a multi-line comparison result.
> >
> > Care to write that patch? I have so much on my TODO already. :|
> 
> Sure, I can fix it.
> 
> I guess this patch will be going through Russell's patch tracker?

Yeah, I'll queue this and another one I have in a bit.

> >> Otherwise it looks good to me.
> >>
> >> Kind regards
> >> Ulf Hansson
> >>
> >> > -                       regulator_enable(mmc->supply.vqmmc);
> >> > +                   !regulator_is_enabled(mmc->supply.vqmmc)) {
> >> > +                       ret = regulator_enable(mmc->supply.vqmmc);
> >> > +                       if (ret < 0)
> >> > +                               dev_err(mmc_dev(mmc),
> >> > +                                       "failed to enable vqmmc regulator\n");
> >> > +               }
> >> >
> >> >                 pwr |= MCI_PWR_ON;
> >> >                 break;
> >> >
> >

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From stefano.stabellini at eu.citrix.com  Fri May  3 06:43:23 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 3 May 2013 11:43:23 +0100
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <5182DBA9.9080609@codeaurora.org>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
Message-ID: <alpine.DEB.2.02.1305031130210.5398@kaball.uk.xensource.com>

On Thu, 2 May 2013, Christopher Covington wrote:
> > So the virtual timer should appear to have been running even while time
> > is being stolen and therefore stolen time needs to be accounted via some
> > other means.
> 
> Something that's not currently obvious to me is that given that the stolen
> cycle accounting should be done, what makes the architected timer interrupt
> handler the ideal place to do it?

That is a good question and I would appreciate suggestions to improve
the patch.

Given that Xen x86 and ia64 does stolen time accounting from the timer
interrupt handler:

arch/x86/xen/time.c:xen_timer_interrupt
arch/ia64/kernel/time.c:timer_interrupt

and given that the arch_timer is the only timer used by Xen on ARM and
that it includes a virt_timer that is made on purpose to be used by
virtual machines, I thought that it might be a good place for it.

I also thought that doing it this way, KVM should be able to reuse the
same hook.


From marc.zyngier at arm.com  Fri May  3 06:54:34 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 03 May 2013 11:54:34 +0100
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <alpine.DEB.2.02.1305031130210.5398@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
 <alpine.DEB.2.02.1305031130210.5398@kaball.uk.xensource.com>
Message-ID: <5183976A.6000703@arm.com>

On 03/05/13 11:43, Stefano Stabellini wrote:
> On Thu, 2 May 2013, Christopher Covington wrote:
>>> So the virtual timer should appear to have been running even while time
>>> is being stolen and therefore stolen time needs to be accounted via some
>>> other means.
>>
>> Something that's not currently obvious to me is that given that the stolen
>> cycle accounting should be done, what makes the architected timer interrupt
>> handler the ideal place to do it?
> 
> That is a good question and I would appreciate suggestions to improve
> the patch.
> 
> Given that Xen x86 and ia64 does stolen time accounting from the timer
> interrupt handler:
> 
> arch/x86/xen/time.c:xen_timer_interrupt
> arch/ia64/kernel/time.c:timer_interrupt
> 
> and given that the arch_timer is the only timer used by Xen on ARM and
> that it includes a virt_timer that is made on purpose to be used by
> virtual machines, I thought that it might be a good place for it.
> 
> I also thought that doing it this way, KVM should be able to reuse the
> same hook.

Indeed. I just need to understand how time stealing works there ;-).

Now, KVM is not necessarily limited to arch_timers, and we've run KVM
using a QEMU-provided timer in the past. Can you think of a more generic
location for this hook? Possibly something that would satisfy the
requirements of other architectures while we're at it?

	M.
-- 
Jazz is not dead. It just smells funny...



From prabhakar.csengg at gmail.com  Fri May  3 07:00:30 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 3 May 2013 16:30:30 +0530
Subject: [PATCH, RFC 21/22] davinci: vpfe_capture needs i2c
In-Reply-To: <1367507786-505303-22-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-22-git-send-email-arnd@arndb.de>
Message-ID: <CA+V-a8sUPwNZq6ed=75_Lq0x_-jy5x4cXcg8BYvZP7b0PQBpcg@mail.gmail.com>

Hi Arnd,

Thanks for the patch.

On Thu, May 2, 2013 at 8:46 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> The vpfe_capture driver is implicitly built for three of the davinci
> capture drivers but depends on i2c, so we need to add the dependency
> in Kconfig for each driver using this.
>
>  drivers/media/platform/davinci/vpfe_capture.c: In function 'vpfe_probe':
>  drivers/media/platform/davinci/vpfe_capture.c:1934:2: error: implicit declaration of function 'i2c_get_adapter' [-Werror=implicit-function-declaration]
>  drivers/media/platform/davinci/vpfe_capture.c:1934:11: warning: assignment makes pointer from integer without a cast [enabled by default]
>
> Cc: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> Cc: Hans Verkuil <hans.verkuil at cisco.com>
> Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>

Regards,
--Prabhakar Lad


From lee.jones at linaro.org  Fri May  3 07:04:24 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 12:04:24 +0100
Subject: [PATCH 2/4] mfd: ab8500-gpadc: Suppress 'ignoring
 regulator_enable() return value' warning
In-Reply-To: <CACRpkdaf75sQduyfw58PFmC1ZyNDMxpwAf0OSyRLPP6vFc+wBQ@mail.gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdaf75sQduyfw58PFmC1ZyNDMxpwAf0OSyRLPP6vFc+wBQ@mail.gmail.com>
Message-ID: <20130503110424.GG24153@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Thu, May 2, 2013 at 5:48 PM, Lee Jones <lee.jones at linaro.org> wrote:
> > drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
> > drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
> >         ?regulator_enable?, declared with attribute warn_unused_result
> >         [-Wunused-result]
> >
> > Cc: Samuel Ortiz <sameo at linux.intel.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/mfd/ab8500-gpadc.c |    5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mfd/ab8500-gpadc.c b/drivers/mfd/ab8500-gpadc.c
> > index 5e65b28..7278e53 100644
> > --- a/drivers/mfd/ab8500-gpadc.c
> > +++ b/drivers/mfd/ab8500-gpadc.c
> > @@ -907,8 +907,11 @@ static int ab8500_gpadc_suspend(struct device *dev)
> >  static int ab8500_gpadc_resume(struct device *dev)
> >  {
> >         struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
> > +       int ret;
> >
> > -       regulator_enable(gpadc->regu);
> > +       ret = regulator_enable(gpadc->regu);
> > +       if (ret < 0)
> > +               return ret;
> >
> >         pm_runtime_mark_last_busy(gpadc->dev);
> >         pm_runtime_put_autosuspend(gpadc->dev);
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

As it has your Ack, I'm going to add an error print as per Srinidhi's
suggestion, test it again and apply this to my MFD tree.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Fri May  3 07:15:37 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 12:15:37 +0100
Subject: [PATCH 2/4 v2] mfd: ab8500-gpadc: Suppress 'ignoring
 regulator_enable() return value' warning
In-Reply-To: <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20130503111537.GH24153@gmail.com>

drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
        ?regulator_enable?, declared with attribute warn_unused_result
        [-Wunused-result]

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/drivers/mfd/ab8500-gpadc.c b/drivers/mfd/ab8500-gpadc.c
index 5e65b28..13f7866 100644
--- a/drivers/mfd/ab8500-gpadc.c
+++ b/drivers/mfd/ab8500-gpadc.c
@@ -907,14 +907,17 @@ static int ab8500_gpadc_suspend(struct device *dev)
 static int ab8500_gpadc_resume(struct device *dev)
 {
 	struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
+	int ret;
 
-	regulator_enable(gpadc->regu);
+	ret = regulator_enable(gpadc->regu);
+	if (ret)
+		dev_err(dev, "Failed to enable vtvout LDO: %d\n", ret);
 
 	pm_runtime_mark_last_busy(gpadc->dev);
 	pm_runtime_put_autosuspend(gpadc->dev);
 
 	mutex_unlock(&gpadc->ab8500_gpadc_lock);
-	return 0;
+	return ret;
 }
 
 static int ab8500_gpadc_probe(struct platform_device *pdev)


From linus.walleij at linaro.org  Fri May  3 07:16:25 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 13:16:25 +0200
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <20130501095243.GD25256@gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <20130501095243.GD25256@gmail.com>
Message-ID: <CACRpkdZtOtnUYvLm7BPA98oMOLAMPHpJ9GLoyMXOKW1nsTDYiQ@mail.gmail.com>

On Wed, May 1, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:

> At this moment in time the memcpy channels which can be used by the D40
> are fixed, as each supported platform in Mainline uses the same ones.
> However, platforms do exist which don't follow this convention, so
> these will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Real nice!

But can you split this in two patches: one that changes
drivers/dma/ste_dma40* and one sequel patch that changes
Documentation/* and arch/arm/boot/dts/* so I can merge them
out-of-order?

I am trying this development cycle to split changes to the
device trees and bindings off from the rest of the patches
becaused it caused me a mess last cycle.

Yours,
Linus Walleij


From shc_work at mail.ru  Fri May  3 07:16:09 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Fri,  3 May 2013 15:16:09 +0400
Subject: [PATCH 2/2] ARM: dts: Add DMA support to imx27 device tree
In-Reply-To: <1367579769-22958-1-git-send-email-shc_work@mail.ru>
References: <1367579769-22958-1-git-send-email-shc_work@mail.ru>
Message-ID: <1367579769-22958-2-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/boot/dts/imx27.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index cd85828..943e8f3 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -61,6 +61,14 @@
 			reg = <0x10000000 0x20000>;
 			ranges;
 
+			dma: dma at 10001000 {
+				compatible = "fsl,imx27-dma";
+				reg = <0x10001000 0x1000>;
+				interrupts = <32>;
+				clocks = <&clks 50>, <&clks 70>;
+				clock-names = "ipg", "ahb";
+			};
+
 			wdog: wdog at 10002000 {
 				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
 				reg = <0x10002000 0x1000>;
-- 
1.8.1.5



From shc_work at mail.ru  Fri May  3 07:16:08 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Fri,  3 May 2013 15:16:08 +0400
Subject: [PATCH 1/2] dmaengine: imx-dma: Add device tree probe support
Message-ID: <1367579769-22958-1-git-send-email-shc_work@mail.ru>

This patch adds device tree probe support for imx-dma driver.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 .../devicetree/bindings/dma/fsl-imx-dma.txt         | 18 ++++++++++++++++++
 drivers/dma/imx-dma.c                               | 21 +++++++++++++++++++--
 2 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-imx-dma.txt

diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
new file mode 100644
index 0000000..9409682
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
@@ -0,0 +1,18 @@
+* Freescale Direct Memory Access (DMA) Controller for i.MX
+
+Required properties:
+- compatible: Should be "fsl,<chip>-dma"
+- reg: Should contain DMA registers location and length
+- interrupts: Should contain DMA interrupt
+- clocks: Pointer to the reference clocks
+- clock-names: Names of DMA reference clocks
+
+Examples:
+
+dma: dma at 10001000 {
+	compatible = "fsl,imx27-dma";
+	reg = <0x10001000 0x1000>;
+	interrupts = <32>;
+	clocks = <&clks 50>, <&clks 70>;
+	clock-names = "ipg", "ahb";
+};
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index f285833..ce8c2a0 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -27,6 +27,8 @@
 #include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <asm/irq.h>
 #include <linux/platform_data/dma-imx.h>
@@ -202,6 +204,14 @@ static struct platform_device_id imx_dma_devtype[] = {
 };
 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
 
+static const struct of_device_id imx_dma_dt_ids[] = {
+	{ .compatible = "fsl,imx1-dma",  .data = &imx_dma_devtype[IMX1_DMA], },
+	{ .compatible = "fsl,imx21-dma", .data = &imx_dma_devtype[IMX21_DMA], },
+	{ .compatible = "fsl,imx27-dma", .data = &imx_dma_devtype[IMX27_DMA], },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, imx_dma_dt_ids);
+
 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
 {
 	return imxdma->devtype == IMX1_DMA;
@@ -997,7 +1007,9 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
-	{
+{
+	const struct of_device_id *of_id =
+			of_match_device(imx_dma_dt_ids, &pdev->dev);
 	struct imxdma_engine *imxdma;
 	struct resource *res;
 	int ret, i;
@@ -1007,6 +1019,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	if (!imxdma)
 		return -ENOMEM;
 
+	if (of_id)
+		pdev->id_entry = of_id->data;
 	imxdma->devtype = pdev->id_entry->driver_data;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1136,6 +1150,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		goto err;
 	}
 
+	dev_info(imxdma->dev, "initialized\n");
+
 	return 0;
 
 err:
@@ -1158,7 +1174,8 @@ static int imxdma_remove(struct platform_device *pdev)
 
 static struct platform_driver imxdma_driver = {
 	.driver		= {
-		.name	= "imx-dma",
+		.name		= "imx-dma",
+		.of_match_table	= imx_dma_dt_ids,
 	},
 	.id_table	= imx_dma_devtype,
 	.remove		= imxdma_remove,
-- 
1.8.1.5



From arnd at arndb.de  Fri May  3 07:20:07 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 13:20:07 +0200
Subject: [PATCH 1/9] ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
In-Reply-To: <CAOh2x==i-_+30mmMp=WkcCQn4qm1-nGfWpPuQnScvRQVd=h+LA@mail.gmail.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-2-git-send-email-arnd@arndb.de>
 <CAOh2x==i-_+30mmMp=WkcCQn4qm1-nGfWpPuQnScvRQVd=h+LA@mail.gmail.com>
Message-ID: <2416484.HHc7d0zNGR@wuerfel>

On Friday 03 May 2013 10:27:17 Viresh Kumar wrote:
> > diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> > index 597e76b..9878503 100644
> > --- a/arch/arm/mach-tegra/Kconfig
> > +++ b/arch/arm/mach-tegra/Kconfig
> > @@ -63,6 +63,7 @@ config ARCH_TEGRA_114_SOC
> >         select ARM_ARCH_TIMER
> >         select ARM_GIC
> >         select ARM_L1_CACHE_SHIFT_6
> > +       select CPU_FREQ_TABLE if CPU_FREQ
> >         select CPU_V7
> >         select PINCTRL
> >         select PINCTRL_TEGRA114
> 
> I doubt which is the best place for doing this? This one or
> cpufreq/Kconfig.arm with select CPU_FREQ_TABLE for
> tegra?

It would be much better IMHO to have an entry for TEGRA_CPUFREQ
in drivers/cpufreq/Kcofnig.arm and move the select there. However,
creating that entry has some (small) regression potential and I
didn't want to do that now but instead just made sure that all
three Tegra SoCs do the same thing for now.

	Arnd


From lee.jones at linaro.org  Fri May  3 07:22:29 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 12:22:29 +0100
Subject: [PATCH 2/4] mfd: ab8500-gpadc: Suppress 'ignoring
 regulator_enable() return value' warning
In-Reply-To: <20130503110424.GG24153@gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdaf75sQduyfw58PFmC1ZyNDMxpwAf0OSyRLPP6vFc+wBQ@mail.gmail.com>
 <20130503110424.GG24153@gmail.com>
Message-ID: <20130503112229.GI24153@gmail.com>

On Fri, 03 May 2013, Lee Jones wrote:

> On Fri, 03 May 2013, Linus Walleij wrote:
> 
> > On Thu, May 2, 2013 at 5:48 PM, Lee Jones <lee.jones at linaro.org> wrote:
> > > drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
> > > drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
> > >         ?regulator_enable?, declared with attribute warn_unused_result
> > >         [-Wunused-result]
> > >
> > > Cc: Samuel Ortiz <sameo at linux.intel.com>
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > > ---
> > >  drivers/mfd/ab8500-gpadc.c |    5 ++++-
> > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mfd/ab8500-gpadc.c b/drivers/mfd/ab8500-gpadc.c
> > > index 5e65b28..7278e53 100644
> > > --- a/drivers/mfd/ab8500-gpadc.c
> > > +++ b/drivers/mfd/ab8500-gpadc.c
> > > @@ -907,8 +907,11 @@ static int ab8500_gpadc_suspend(struct device *dev)
> > >  static int ab8500_gpadc_resume(struct device *dev)
> > >  {
> > >         struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
> > > +       int ret;
> > >
> > > -       regulator_enable(gpadc->regu);
> > > +       ret = regulator_enable(gpadc->regu);
> > > +       if (ret < 0)
> > > +               return ret;
> > >
> > >         pm_runtime_mark_last_busy(gpadc->dev);
> > >         pm_runtime_put_autosuspend(gpadc->dev);
> > 
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> As it has your Ack, I'm going to add an error print as per Srinidhi's
> suggestion, test it again and apply this to my MFD tree.

Slight change of plan, as I've changed the semantics.

Would you be kind enough to see v2?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From arnd at arndb.de  Fri May  3 07:28:38 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 13:28:38 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <CACRpkdY+5gdh1G7N+_Spg=iNZ0QMZ=ZXuhsVPuMEt62NxPhRxA@mail.gmail.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-10-git-send-email-arnd@arndb.de>
 <CACRpkdY+5gdh1G7N+_Spg=iNZ0QMZ=ZXuhsVPuMEt62NxPhRxA@mail.gmail.com>
Message-ID: <15723843.9mConxltov@wuerfel>

On Friday 03 May 2013 10:14:28 Linus Walleij wrote:
> 
> I do not necessarily agree with this commit message.
> 
> The only mess I see is that this very patch is missing...
> 
> If we look at this:
> 
> config UX500_SOC_DB8500
>         bool
>         select CPU_FREQ_TABLE if CPU_FREQ
>         select MFD_DB8500_PRCMU
>         select PINCTRL_DB8500
>         select PINCTRL_DB8540
>         select PINCTRL_AB8500
>         select PINCTRL_AB8505
>         select PINCTRL_AB9540
>         select PINCTRL_AB8540
>         select REGULATOR
>         select REGULATOR_DB8500_PRCMU
> 
> The PRCMU, the PINCTRL drivers, and the PRCMU regulators
> are necessary to boot the system correctly, by which I mean
> necessary so as not to cause potential damage to the hardware.
> 
> The PRCMU is a system controller without which the system
> cannot really be brought up, and the ABx500's are the PMICs
> which are developed in pair with the SoC and they are in practice
> Siamese twins, there is no chance you can build a Ux500 system
> without both of them. It just won't even start. There are deep
> dependencies between the PRCMU and the ABx500, as the
> PRCMU firmware will talk directly to the ABx500 without the
> kernel intervening. I.e. the whole set of hardware has to be
> there.
> 
> While I understand that from a compile-time point of view it does
> not seem nice, and all things would be separate units that you
> plug in, from a run-time and system architecture point of view it
> makes a lot of sense to select these. Worlds collide...
> 
> Apart from that:
> Acked-by: Linus Walleij <linus.walleij at linaro.org>


If they are completely essential, we should not have an entry
like 

config AB8500_CORE
        bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
        depends on GENERIC_HARDIRQS && ABX500_CORE && MFD_DB8500_PRCMU
        select POWER_SUPPLY
        select MFD_CORE
        select IRQ_DOMAIN
        help
          Select this option to enable access to AB8500 power management
          chip. This connects to U8500 either on the SSP/SPI bus (deprecated
          since hardware version v1.0) or the I2C bus via PRCMU. It also adds
          the irq_chip parts for handling the Mixed Signal chip events.
          This chip embeds various other multimedia funtionalities as well.

(and more of the same) in drivers/mfd/Kconfig. The rule is that you either
make a Kconfig option user-selectable or make it always selected by another
option.

My preference would be to make it user-selectable and enable it only in
the defconfig, but if that can damage the hardware, we should not actually
provide a named option.

	Arnd




From s.hauer at pengutronix.de  Fri May  3 07:32:14 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 May 2013 13:32:14 +0200
Subject: [PATCH 1/2] dmaengine: imx-dma: Add device tree probe support
In-Reply-To: <1367579769-22958-1-git-send-email-shc_work@mail.ru>
References: <1367579769-22958-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130503113214.GU32299@pengutronix.de>

On Fri, May 03, 2013 at 03:16:08PM +0400, Alexander Shiyan wrote:
> This patch adds device tree probe support for imx-dma driver.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

There's already v6 of a series adding devicetree support for imx-dma
available:

See http://comments.gmane.org/gmane.linux.drivers.devicetree/34800

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shc_work at mail.ru  Fri May  3 07:37:23 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Fri, 03 May 2013 15:37:23 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSCAxLzJdIGRtYWVuZ2luZTogaW14LWRtYTogQWRkIGRl?=
 =?UTF-8?B?dmljZSB0cmVlIHByb2JlIHN1cHBvcnQ=?=
In-Reply-To: <20130503113214.GU32299@pengutronix.de>
References: <1367579769-22958-1-git-send-email-shc_work@mail.ru>
 <20130503113214.GU32299@pengutronix.de>
Message-ID: <1367581043.757588430@f76.mail.ru>

> On Fri, May 03, 2013 at 03:16:08PM +0400, Alexander Shiyan wrote:
> > This patch adds device tree probe support for imx-dma driver.
> > 
> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> 
> There's already v6 of a series adding devicetree support for imx-dma
> available:
> 
> See http://comments.gmane.org/gmane.linux.drivers.devicetree/34800

Ah, OK. Then just throw these patches.

---

From rric at kernel.org  Fri May  3 07:53:32 2013
From: rric at kernel.org (Robert Richter)
Date: Fri, 3 May 2013 13:53:32 +0200
Subject: [PATCH, RFC 14/22] oprofile: always enable IRQ_WORK
In-Reply-To: <1367507786-505303-15-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-15-git-send-email-arnd@arndb.de>
Message-ID: <20130503115332.GT8356@rric.localhost>

On 02.05.13 17:16:18, Arnd Bergmann wrote:
> oprofile fails to build if CONFIG_IRQ_WORK is not already enabled,
> because of the dependency on the RING_BUFFER code that now uses
> the irq work library.
> 
> kernel/built-in.o: In function `ring_buffer_unlock_commit':
> :(.text+0x5b8f0): undefined reference to `irq_work_queue'
> kernel/built-in.o: In function `ring_buffer_write':
> :(.text+0x5bd10): undefined reference to `irq_work_queue'

Shouldn't this be fixed in the ring_buffer implementation?

I also do not see, where this comes from. I was successfully compiling
a kernel with OPROFILE and RING_BUFFER enabled but IRQ_WORK disabled.
Do you have that config still available?

Thanks,

-Robert

> 
> Cc: Robert Richter <rric at kernel.org>
> Cc: oprofile-list at lists.sf.net
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/Kconfig b/arch/Kconfig
> index a6b1056..434a8dc 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -8,6 +8,7 @@ config OPROFILE
>  	depends on HAVE_OPROFILE
>  	select RING_BUFFER
>  	select RING_BUFFER_ALLOW_SWAP
> +	select IRQ_WORK
>  	help
>  	  OProfile is a profiling system capable of profiling the
>  	  whole system, include the kernel, kernel modules, libraries,
> -- 
> 1.8.1.2
> 


From jjo.braun at gmail.com  Fri May  3 07:56:00 2013
From: jjo.braun at gmail.com (Johannes Braun)
Date: Fri, 3 May 2013 13:56:00 +0200
Subject: Freescale imx35: sgtl5000 codec not working over i2c
In-Reply-To: <20130503093948.GT32299@pengutronix.de>
References: <20130502200024.72c112cc@jobraun>
 <20130502181821.GC31135@pengutronix.de>
 <20130502204020.0462f080@jobraun>
 <20130503093948.GT32299@pengutronix.de>
Message-ID: <CADwvPCtK_4gMHggP0mN2yqCLHzFY7EC9EnK8CpEHr87E=pkMPQ@mail.gmail.com>

> With "sgtl5000" at least sgtl5000_i2c_probe should be called.

Ok my fault. I did not see the i2c probe mehtod. I checked whether
sgtl5000_i2c_probe is called or not and I can confirm that the method
was passed successfully. I tested it with several kernel log messages.

> Is the i.MX I2C driver registered correctly. What's in /sys/bus/i2c/devices/?

I think so. The following devices are shown:
ls -la /sys/bus/i2c/devices/
lrwxrwxrwx 1 root root 0 Jan  1  1970 0-000a ->
../../../devices/platform/imx-i2c.0/i2c-0/0-000a/
lrwxrwxrwx 1 root root 0 Jan  1  1970 i2c-0 ->
../../../devices/platform/imx-i2c.0/i2c-0/
lrwxrwxrwx 1 root root 0 Jan  1  1970 i2c-2 ->
../../../devices/platform/imx-i2c.2/i2c-2/

Also I am able to probe the bus via i2cdetect. This is the result:
root at generic-armv6:~$ i2cdetect 0
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0.
I will probe address range 0x03-0x77.
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- UU -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --

UU shows that this device is use by a driver.

> you won't need much more than something similar to
> arch/arm/mach-imx/imx25-dt.c and an auxdata table for the clock lookups.
> There even is pinctrl support.

I will check this out.

---
Johannes


From lee.jones at linaro.org  Fri May  3 07:57:39 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 12:57:39 +0100
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <CACRpkdZtOtnUYvLm7BPA98oMOLAMPHpJ9GLoyMXOKW1nsTDYiQ@mail.gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <20130501095243.GD25256@gmail.com>
 <CACRpkdZtOtnUYvLm7BPA98oMOLAMPHpJ9GLoyMXOKW1nsTDYiQ@mail.gmail.com>
Message-ID: <20130503115739.GJ24153@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Wed, May 1, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > At this moment in time the memcpy channels which can be used by the D40
> > are fixed, as each supported platform in Mainline uses the same ones.
> > However, platforms do exist which don't follow this convention, so
> > these will need to be tailored. Fortunately, these platforms will be DT
> > only, so this change has very little impact on platform data.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Real nice!
> 
> But can you split this in two patches: one that changes
> drivers/dma/ste_dma40* and one sequel patch that changes
> Documentation/* and arch/arm/boot/dts/* so I can merge them
> out-of-order?
> 
> I am trying this development cycle to split changes to the
> device trees and bindings off from the rest of the patches
> becaused it caused me a mess last cycle.

I was under the impression that the documentation went with the
bindings, rather than the Device Tree. Am I wrong?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Fri May  3 08:02:59 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 14:02:59 +0200
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <20130503115739.GJ24153@gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <20130501095243.GD25256@gmail.com>
 <CACRpkdZtOtnUYvLm7BPA98oMOLAMPHpJ9GLoyMXOKW1nsTDYiQ@mail.gmail.com>
 <20130503115739.GJ24153@gmail.com>
Message-ID: <CACRpkdb-_pf=9cm_Hy25nzFWKSTKc6OmmG9rhN2T1wR1=2tddg@mail.gmail.com>

On Fri, May 3, 2013 at 1:57 PM, Lee Jones <lee.jones at linaro.org> wrote:
> On Fri, 03 May 2013, Linus Walleij wrote:
>
>> On Wed, May 1, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > At this moment in time the memcpy channels which can be used by the D40
>> > are fixed, as each supported platform in Mainline uses the same ones.
>> > However, platforms do exist which don't follow this convention, so
>> > these will need to be tailored. Fortunately, these platforms will be DT
>> > only, so this change has very little impact on platform data.
>> >
>> > Cc: Vinod Koul <vinod.koul at intel.com>
>> > Cc: Dan Williams <djbw at fb.com>
>> > Cc: Per Forlin <per.forlin at stericsson.com>
>> > Cc: Rabin Vincent <rabin at rab.in>
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> Real nice!
>>
>> But can you split this in two patches: one that changes
>> drivers/dma/ste_dma40* and one sequel patch that changes
>> Documentation/* and arch/arm/boot/dts/* so I can merge them
>> out-of-order?
>>
>> I am trying this development cycle to split changes to the
>> device trees and bindings off from the rest of the patches
>> becaused it caused me a mess last cycle.
>
> I was under the impression that the documentation went with the
> bindings, rather than the Device Tree. Am I wrong?

No you're right. The documentation with the bindings and the
patch to the driver...

Then just arch/arm/boot/dts/* separately.

The latter is where I have all my trouble and screwup...

(However when we break the devicetree data out of the kernel
and into its own git we will have to follow the pattern above with
a patch of bindings+DT changes and another one in parallell
changing the kernel, but that is for a more advanced age.)

Yours,
Linus Walleij


From nm at ti.com  Fri May  3 08:03:50 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 3 May 2013 07:03:50 -0500
Subject: [PATCH v3 1/5] regulator: Introduce TI Adaptive Body Bias(ABB)
 on-chip LDO driver
In-Reply-To: <20130503090258.GG4945@sirena.org.uk>
References: <1367515215-30753-1-git-send-email-nm@ti.com>
 <1367515215-30753-2-git-send-email-nm@ti.com>
 <20130503090258.GG4945@sirena.org.uk>
Message-ID: <20130503120349.GA2735@snafu>

Hi Mark,
On 10:02-20130503, Mark Brown wrote:
> On Thu, May 02, 2013 at 12:20:10PM -0500, Nishanth Menon wrote:
> > From: "Andrii.Tseglytskyi" <andrii.tseglytskyi at ti.com>
> > 
> > Adaptive Body Biasing (ABB) modulates transistor bias voltages
> > dynamically in order to optimize switching speed versus leakage.
> 
> I've applied this but please note that I still have deep concerns about
> some of the discussion about controlling this from other regulators.
Thanks for the merge.

We don't have any further plans of pursuing the concept of regulator
chaining for upstream. After an off-line chat with Mike T, we are
planning on introducing OMAP specific notifier hooks to clock
framework. This should allow us to do the appropriate sequencing
necessary to control AVS, regulators for ABB and PMIC in the right
sequence.

-- 
Regards,
Nishanth Menon


From viresh.kumar at linaro.org  Fri May  3 08:06:53 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Fri, 3 May 2013 17:36:53 +0530
Subject: [PATCH 1/9] ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
In-Reply-To: <2416484.HHc7d0zNGR@wuerfel>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-2-git-send-email-arnd@arndb.de>
 <CAOh2x==i-_+30mmMp=WkcCQn4qm1-nGfWpPuQnScvRQVd=h+LA@mail.gmail.com>
 <2416484.HHc7d0zNGR@wuerfel>
Message-ID: <CAKohpokKGi_nKYbZqvNW64fbEFdbtbmhvcVY93F3ONtWuffvug@mail.gmail.com>

On 3 May 2013 16:50, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 03 May 2013 10:27:17 Viresh Kumar wrote:
>> > diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
>> > index 597e76b..9878503 100644
>> > --- a/arch/arm/mach-tegra/Kconfig
>> > +++ b/arch/arm/mach-tegra/Kconfig
>> > @@ -63,6 +63,7 @@ config ARCH_TEGRA_114_SOC
>> >         select ARM_ARCH_TIMER
>> >         select ARM_GIC
>> >         select ARM_L1_CACHE_SHIFT_6
>> > +       select CPU_FREQ_TABLE if CPU_FREQ
>> >         select CPU_V7
>> >         select PINCTRL
>> >         select PINCTRL_TEGRA114
>>
>> I doubt which is the best place for doing this? This one or
>> cpufreq/Kconfig.arm with select CPU_FREQ_TABLE for
>> tegra?
>
> It would be much better IMHO to have an entry for TEGRA_CPUFREQ
> in drivers/cpufreq/Kcofnig.arm and move the select there. However,
> creating that entry has some (small) regression potential and I
> didn't want to do that now but instead just made sure that all
> three Tegra SoCs do the same thing for now.

I was under the impression that this entry is already there.

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From rjw at sisk.pl  Fri May  3 08:15:57 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Fri, 03 May 2013 14:15:57 +0200
Subject: [PATCH,
 RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <CAKohpomBKuaxk+sSF63cu6JKut1uV7J7Sj2o85c3wQ=fodx+Ow@mail.gmail.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-3-git-send-email-arnd@arndb.de>
 <CAKohpomBKuaxk+sSF63cu6JKut1uV7J7Sj2o85c3wQ=fodx+Ow@mail.gmail.com>
Message-ID: <5563691.6kxbXZTjH5@vostro.rjw.lan>

On Friday, May 03, 2013 10:21:45 AM Viresh Kumar wrote:
> On 2 May 2013 20:46, Arnd Bergmann <arnd at arndb.de> wrote:
> > The big.LITTLE cpufreq driver uses the CPU topology API, which
> > needs to be reflected in Kconfig to prevent broken configurations.
> >
> > warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
> > has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM && ARM_CPU_TOPOLOGY)
> >
> > Cc: Rafael J. Wysocki <rjw at sisk.pl>
> > Cc: Viresh Kumar <viresh.kumar at linaro.org>
> > Cc: cpufreq at vger.kernel.org
> > Cc: linux-pm at vger.kernel.org
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > ---
> >  drivers/cpufreq/Kconfig.arm | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > index f3af18b..3fd6bdf 100644
> > --- a/drivers/cpufreq/Kconfig.arm
> > +++ b/drivers/cpufreq/Kconfig.arm
> > @@ -10,6 +10,7 @@ config ARM_DT_BL_CPUFREQ
> >         tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
> >         select ARM_BIG_LITTLE_CPUFREQ
> >         depends on OF && HAVE_CLK
> > +       depends on ARM_CPU_TOPOLOGY
> >         help
> >           This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
> >           This gets frequency tables from DT.
> 
> This Kconfig thing has always been confusing to me. This is how the code looks
> currently.
> 
> config ARM_BIG_LITTLE_CPUFREQ
>         tristate
>         depends on ARM_CPU_TOPOLOGY
> 
> config ARM_DT_BL_CPUFREQ
>         tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
>         select ARM_BIG_LITTLE_CPUFREQ
>         depends on OF && HAVE_CLK
>         help
>           This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
>           This gets frequency tables from DT.
> 
> Because all ARM big LITTLE cpufreq stuff have dependency on
> ARM_CPU_TOPOLOGY, i have added dependency at a common place. So that
> we don't end up adding this in every glue layer driver. How should this be done?

First, there's no rule of thumb here as far as I can say.

In this particular case I think it is OK to make both ARM_DT_BL_CPUFREQ and
ARM_BIG_LITTLE_CPUFREQ depend on ARM_CPU_TOPOLOGY, because (in theory?) the
latter may be set without the former (unless you want to make ARM_DT_BL_CPUFREQ
depend on ARM_BIG_LITTLE_CPUFREQ, but then it may be kind of confusing to
users).

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From lee.jones at linaro.org  Fri May  3 08:11:35 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 13:11:35 +0100
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <CACRpkdb-_pf=9cm_Hy25nzFWKSTKc6OmmG9rhN2T1wR1=2tddg@mail.gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <20130501095243.GD25256@gmail.com>
 <CACRpkdZtOtnUYvLm7BPA98oMOLAMPHpJ9GLoyMXOKW1nsTDYiQ@mail.gmail.com>
 <20130503115739.GJ24153@gmail.com>
 <CACRpkdb-_pf=9cm_Hy25nzFWKSTKc6OmmG9rhN2T1wR1=2tddg@mail.gmail.com>
Message-ID: <20130503121135.GK24153@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 1:57 PM, Lee Jones <lee.jones at linaro.org> wrote:
> > On Fri, 03 May 2013, Linus Walleij wrote:
> >
> >> On Wed, May 1, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:
> >>
> >> > At this moment in time the memcpy channels which can be used by the D40
> >> > are fixed, as each supported platform in Mainline uses the same ones.
> >> > However, platforms do exist which don't follow this convention, so
> >> > these will need to be tailored. Fortunately, these platforms will be DT
> >> > only, so this change has very little impact on platform data.
> >> >
> >> > Cc: Vinod Koul <vinod.koul at intel.com>
> >> > Cc: Dan Williams <djbw at fb.com>
> >> > Cc: Per Forlin <per.forlin at stericsson.com>
> >> > Cc: Rabin Vincent <rabin at rab.in>
> >> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >>
> >> Real nice!
> >>
> >> But can you split this in two patches: one that changes
> >> drivers/dma/ste_dma40* and one sequel patch that changes
> >> Documentation/* and arch/arm/boot/dts/* so I can merge them
> >> out-of-order?
> >>
> >> I am trying this development cycle to split changes to the
> >> device trees and bindings off from the rest of the patches
> >> becaused it caused me a mess last cycle.
> >
> > I was under the impression that the documentation went with the
> > bindings, rather than the Device Tree. Am I wrong?
> 
> No you're right. The documentation with the bindings and the
> patch to the driver...
> 
> Then just arch/arm/boot/dts/* separately.

I'm confused, that's how it is already:

  Documentation/devicetree/bindings/dma/ste-dma40.txt |    2 ++
  drivers/dma/ste_dma40.c                             |   42 +++++++++++++++++++++++++++++++++---------
  include/linux/platform_data/dma-ste-dma40.h         |    2 ++
  3 files changed, 37 insertions(+), 9 deletions(-)

Are you getting enough sleep? ;)

> The latter is where I have all my trouble and screwup...
> 
> (However when we break the devicetree data out of the kernel
> and into its own git we will have to follow the pattern above with
> a patch of bindings+DT changes and another one in parallell
> changing the kernel, but that is for a more advanced age.)
> 
> Yours,
> Linus Walleij

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Fri May  3 08:13:20 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 14:13:20 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <15723843.9mConxltov@wuerfel>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-10-git-send-email-arnd@arndb.de>
 <CACRpkdY+5gdh1G7N+_Spg=iNZ0QMZ=ZXuhsVPuMEt62NxPhRxA@mail.gmail.com>
 <15723843.9mConxltov@wuerfel>
Message-ID: <CACRpkdYgGVepjaGY=1HP-GxE0mzTozA0aaT=jPe=aCPb5ppi9A@mail.gmail.com>

On Fri, May 3, 2013 at 1:28 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 03 May 2013 10:14:28 Linus Walleij wrote:

>> While I understand that from a compile-time point of view it does
>> not seem nice, and all things would be separate units that you
>> plug in, from a run-time and system architecture point of view it
>> makes a lot of sense to select these. Worlds collide...
(...)
> My preference would be to make it user-selectable and enable it only in
> the defconfig, but if that can damage the hardware, we should not actually
> provide a named option.

Hm I'd lean towards the latter. However the AB8500 has subdrivers
and *some* of these are optional, such as the RTC. And it'd be
strange to have that depend on some totally unrelated config symbol
like UX500_SOC_COMMON.

I think that in that case we should make AB8500_CORE a hidden
(non-user selectable) bool so it is more logical.

However any if these approaches will lead to unaestetic menuconfig
with AB8500 suboptions appearing right in the MFD menu instead of
being ordered under a AB8500_CORE node which is better for
anyone actually trying to use menuconfig interactively.

The latter aestetic is one of the reasons why it looks as it does
IIRC, but maybe that is HTML thinking :-)

Yours,
Linus Walleij


From arnd at arndb.de  Fri May  3 08:48:38 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 14:48:38 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <CACRpkdYgGVepjaGY=1HP-GxE0mzTozA0aaT=jPe=aCPb5ppi9A@mail.gmail.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <15723843.9mConxltov@wuerfel>
 <CACRpkdYgGVepjaGY=1HP-GxE0mzTozA0aaT=jPe=aCPb5ppi9A@mail.gmail.com>
Message-ID: <1883078.Smcmxe7hlB@wuerfel>

On Friday 03 May 2013 14:13:20 Linus Walleij wrote:
> On Fri, May 3, 2013 at 1:28 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Friday 03 May 2013 10:14:28 Linus Walleij wrote:
> 
> >> While I understand that from a compile-time point of view it does
> >> not seem nice, and all things would be separate units that you
> >> plug in, from a run-time and system architecture point of view it
> >> makes a lot of sense to select these. Worlds collide...
> (...)
> > My preference would be to make it user-selectable and enable it only in
> > the defconfig, but if that can damage the hardware, we should not actually
> > provide a named option.
> 
> Hm I'd lean towards the latter. However the AB8500 has subdrivers
> and *some* of these are optional, such as the RTC. And it'd be
> strange to have that depend on some totally unrelated config symbol
> like UX500_SOC_COMMON.
> 
> I think that in that case we should make AB8500_CORE a hidden
> (non-user selectable) bool so it is more logical.

Yes, makes sense.

> However any if these approaches will lead to unaestetic menuconfig
> with AB8500 suboptions appearing right in the MFD menu instead of
> being ordered under a AB8500_CORE node which is better for
> anyone actually trying to use menuconfig interactively.

Yes, I can see that. Right now we have:

   -*- ST-Ericsson ABX500 Mixed Signal Circuit register functions 
   [*]   ST-Ericsson AB3100 Mixed Signal Circuit core functions   
   [*]     ST-Ericsson AB3100 OTP functions                      
   -*-   ST-Ericsson AB8500 Mixed Signal Power Management chip
   [*]     ST-Ericsson AB8500 GPADC driver
   [*]       Enable debug info via debugfs
   -*- ST-Ericsson DB8500 Power Reset Control Management Unit

I think we can certainly eliminate the ABX500 option, this one can
just get selected by AB3100 and AB8500. The PRCMU can also
be silent because as you say it is always needed.

One possible reason to allow them to be selected is to enable
build-time coverage on other platforms, but at the moment, they
all depend on ARCH_U300|ARCH_U8500, presumably because until
very recently they would not actually build anywhere else.

The GPADC driver is interesting: it does not have its own user
interface (besides the debugging driver) and could just get selected
by the other drivers using its exported interfaces. It would
also be better to convert it to the standard IIO ADC interface,
but I don't know if that's realistic. This leavs the debugging
interface as the only sub-option. Do you know if that is
actually being used by developers, or is this one of those interfaces
that were created during bringup and then never touched again
after everything worked?

Regarding AB3100, I assume the relationship to U300 is similar to
that between DB8500 and AB8500. Are you able to boot a U300 system
without touching AB3100?

	Arnd




From linux at arm.linux.org.uk  Fri May  3 08:55:27 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 13:55:27 +0100
Subject: [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <1367538519-23940-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130503125527.GE18614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 01:48:35AM +0200, Sebastian Hesselbarth wrote:
> This patch adds an irqchip driver for the main interrupt controller found
> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
> Corresponding device tree documentation is also added.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Note: This patch triggers a checkpatch warning for
>   WARNING: Avoid CamelCase: <handle_IRQ>
> 
> Changelog:
> v1->v2:
> - rename compatible string to "marvell,orion-intc" (Suggested by Jason Gunthorpe)
> - request mem regions for irq base registers (Suggested by Jason Gunthorpe)
> - make orion_handle_irq static (Suggested by Jason Gunthorpe)
> - make use of IRQCHIP_DECLARE (Suggested by Jason Gunthorpe)

It would still be a good idea to convert this to use the generic chip
stuff which Thomas created, though exactly how is hard to see at the
moment.

> +static void orion_irq_mask(struct irq_data *irqd)
> +{
> +	unsigned int irq = irqd_to_hwirq(irqd);
> +	unsigned int irq_off = irq % 32;
> +	int reg = irq / 32;
> +	u32 val;
> +
> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> +	writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}

This could be replaced with irq_gc_mask_clr_bit().

> +
> +static void orion_irq_unmask(struct irq_data *irqd)
> +{
> +	unsigned int irq = irqd_to_hwirq(irqd);
> +	unsigned int irq_off = irq % 32;
> +	int reg = irq / 32;
> +	u32 val;
> +
> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> +	writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}

This with irq_gc_mask_set_bit().

> +
> +static struct irq_chip orion_irq_chip = {
> +	.name		= "orion_irq",
> +	.irq_mask	= orion_irq_mask,
> +	.irq_unmask	= orion_irq_unmask,
> +};
> +
> +static int orion_irq_map(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw)
> +{
> +	irq_set_chip_and_handler(virq, &orion_irq_chip,
> +				 handle_level_irq);
> +	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);

This is where it starts to get tricky, because I can't see how you'd
merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with
this.  Maybe you don't need to do anything here and just do all that
in orion_of_init() instead?  But then you seem to need to know the
virq range before hand, and I can't see how that's known.  Maybe Thomas
can provide some enlightenment about how the gc irqchip stuff works
with the irq domain stuff...

However, you wouldn't need the statically defined orion_irq_chip nor
orion_irq_base[] either, because those would be held within the gc
irqchip stuff and stored in the upper layer.


From viresh.kumar at linaro.org  Fri May  3 09:01:52 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Fri, 3 May 2013 18:31:52 +0530
Subject: [PATCH,
 RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <5563691.6kxbXZTjH5@vostro.rjw.lan>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-3-git-send-email-arnd@arndb.de>
 <CAKohpomBKuaxk+sSF63cu6JKut1uV7J7Sj2o85c3wQ=fodx+Ow@mail.gmail.com>
 <5563691.6kxbXZTjH5@vostro.rjw.lan>
Message-ID: <CAKohpon9qmowJ4PmL-nvnoaCzJSC-ZSPv8EUOyoFcTdRqNRwnw@mail.gmail.com>

On 3 May 2013 17:45, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> In this particular case I think it is OK to make both ARM_DT_BL_CPUFREQ and
> ARM_BIG_LITTLE_CPUFREQ depend on ARM_CPU_TOPOLOGY, because (in theory?) the
> latter may be set without the former (unless you want to make ARM_DT_BL_CPUFREQ
> depend on ARM_BIG_LITTLE_CPUFREQ, but then it may be kind of confusing to
> users).

ARM_BIG_LITTLE_CPUFREQ is the core cpufreq code for big LITTLE SoC's and every
other driver will be a glue providing ops to it. So, ARM_DT_BL_CPUFREQ
does depend
on ARM_BIG_LITTLE_CPUFREQ and that's why i added depends on
ARM_CPU_TOPOLOGY in ARM_BIG_LITTLE_CPUFREQ only and depends on
ARM_BIG_LITTLE_CPUFREQ in ARM_DT_BL_CPUFREQ.

But the problem is if ARM_DT_BL_CPUFREQ isn't selected then we still get
ARM_DT_BL_CPUFREQ enabled in menuconfig but a warning just before compilation.
Which Arnd pointed to..


From sebastian.hesselbarth at gmail.com  Fri May  3 09:13:17 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 03 May 2013 15:13:17 +0200
Subject: [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <20130503125527.GE18614@n2100.arm.linux.org.uk>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130503125527.GE18614@n2100.arm.linux.org.uk>
Message-ID: <5183B7ED.7030800@gmail.com>

On 05/03/13 14:55, Russell King - ARM Linux wrote:
> On Fri, May 03, 2013 at 01:48:35AM +0200, Sebastian Hesselbarth wrote:
>> This patch adds an irqchip driver for the main interrupt controller found
>> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
>> Corresponding device tree documentation is also added.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
>> ---
>> Note: This patch triggers a checkpatch warning for
>>    WARNING: Avoid CamelCase: <handle_IRQ>
>>
>> Changelog:
>> v1->v2:
>> - rename compatible string to "marvell,orion-intc" (Suggested by Jason Gunthorpe)
>> - request mem regions for irq base registers (Suggested by Jason Gunthorpe)
>> - make orion_handle_irq static (Suggested by Jason Gunthorpe)
>> - make use of IRQCHIP_DECLARE (Suggested by Jason Gunthorpe)
>
> It would still be a good idea to convert this to use the generic chip
> stuff which Thomas created, though exactly how is hard to see at the
> moment.

Russel,

that is the plan and that's why the whole patch set is preliminary.
Maybe it would have been more precise to call it RFC instead.

>> +static void orion_irq_mask(struct irq_data *irqd)
>> +{
>> +	unsigned int irq = irqd_to_hwirq(irqd);
>> +	unsigned int irq_off = irq % 32;
>> +	int reg = irq / 32;
>> +	u32 val;
>> +
>> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
>> +	writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
>> +}
>
> This could be replaced with irq_gc_mask_clr_bit().
>
>> +
>> +static void orion_irq_unmask(struct irq_data *irqd)
>> +{
>> +	unsigned int irq = irqd_to_hwirq(irqd);
>> +	unsigned int irq_off = irq % 32;
>> +	int reg = irq / 32;
>> +	u32 val;
>> +
>> +	val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
>> +	writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
>> +}
>
> This with irq_gc_mask_set_bit().
>
>> +
>> +static struct irq_chip orion_irq_chip = {
>> +	.name		= "orion_irq",
>> +	.irq_mask	= orion_irq_mask,
>> +	.irq_unmask	= orion_irq_unmask,
>> +};
>> +
>> +static int orion_irq_map(struct irq_domain *d, unsigned int virq,
>> +			 irq_hw_number_t hw)
>> +{
>> +	irq_set_chip_and_handler(virq, &orion_irq_chip,
>> +				 handle_level_irq);
>> +	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
>
> This is where it starts to get tricky, because I can't see how you'd
> merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with
> this.  Maybe you don't need to do anything here and just do all that
> in orion_of_init() instead?  But then you seem to need to know the
> virq range before hand, and I can't see how that's known.  Maybe Thomas
> can provide some enlightenment about how the gc irqchip stuff works
> with the irq domain stuff...

Exactly, and that is what I am looking into right now. But hell, I am
not an expert in linux irq yet. Moreover, I am not even sure if it is
okay to rely on irqdomain or at least irq_data->hw_irq at all.

My current impression is, that generic chip knowns nothing about irq
domains. But my first modification of it was to use irqd_to_hwirq(d)
where ever it uses d->irq instead. This should allow to abstract from
virtual irqs and retain compatibility (_if_ hw_irq is also set on
!CONFIG_IRQ_DOMAIN).

To add more juice: IRQF_VALID and IRQF_PROBE are ARM only flags. I
tried to find out what they are good for, but stopped googl'ing after
a while. (I know you explained that before somewhere)

> However, you wouldn't need the statically defined orion_irq_chip nor
> orion_irq_base[] either, because those would be held within the gc
> irqchip stuff and stored in the upper layer.

Yeah, that would be very nice. But the current limitation to one
register set with max 32 irqs of generic chip would still require to
keep a list of primary generic irq chips to flip through in the
irq_handler.

This also raises the question, how to check if an generic irq chip
flow handler has to be called. Current irq_chip_regs don't know nothing
about a cause/status register. And actually you don't even know if it
is high/low active and how to mask it with the high/low active mask
register or mask_cache.

Sebastian



From catalin.marinas at arm.com  Fri May  3 09:17:54 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 3 May 2013 14:17:54 +0100
Subject: [PATCH v3 00/32] Port of KVM to arm64
In-Reply-To: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130503131754.GC21621@localhost.cambridge.arm.com>

On Mon, Apr 08, 2013 at 05:17:02PM +0100, Marc Zyngier wrote:
> This series contains the third version of KVM for arm64.
> 
> It depends on the following branches/series:
> - git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git soc-armv8-model
>   Catalin's platform support branch for v8 models

After 3.10-rc1 you should be able to base it on the mainline kernel (or
-rc2 if something breaks).

> The code is unsurprisingly extremely similar to the KVM/arm code, and
> a lot of it is actually shared with the 32bit version. Some of the
> include files are duplicated though (I'm definitely willing to fix
> that).

As it was already commented, some of the commonality could be shared via
virt/kvm/ (timers, gic).

Apart from the other comments I (and the others) had, the series looks
fine and in shape for 3.11. Looking forward to see v4...

Thanks.

-- 
Catalin


From arnd at arndb.de  Fri May  3 09:25:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 15:25:23 +0200
Subject: [GIT PULL] mailbox driver framework for v3.10 merge window
In-Reply-To: <5182E403.1030808@ti.com>
References: <37C860A02101E749A747FA2D3C1E3C504A1971@DLEE11.ent.ti.com>
 <CAJe_Zhf5QwQQU5aVtNhbDT3EK9Dof-ZK_boP9WaNghqO8xY7iA@mail.gmail.com>
 <5182E403.1030808@ti.com>
Message-ID: <1407180.uGFidLMFHk@wuerfel>

On Thursday 02 May 2013 17:09:07 Suman Anna wrote:
> On 04/28/2013 11:07 PM, Jassi Brar wrote:
> > Now, we could either call it (effectively the TI's framework with
> > quirks for STE) as the "Common API" and then dismantle and convert it
> > patch by patch (authors and I seem to agree many things need to be
> > changed and implemented).
> >   OR we do it reasonably right the first time even if that means yet
> > another release. IMHO we should go for slow but steady thing.
> 
> I think it is your call here, either of the above approaches would
> definitely involve some rework on the framework as well as both the OMAP
> & ST mailboxes. Atleast for OMAP, the code exists in kernel but disabled
> currently due to the multi-platform support. It is pending on the move
> to drivers/mailbox folder, and can be enabled just with the first 3
> patches (and another one for renaming generic mailbox.c/.h back to
> omap_mailbox.c/.h files if we go the RFC approach) in the series
> (irrespective of the framework). TI DSP/Bridge would remain broken
> because of the omap dmtimer api dependencies on multi-platform.
> 
> I do not know how much of an impact it is for the ST driver as the
> series adds the driver, and would have to wait until the RFC is sorted
> out otherwise.

I think I'd prefer to drop the branch from the 3.10 queue then
and let you all work out a common approach for 3.11. Olof, any
other input?

	Arnd


From rostedt at goodmis.org  Fri May  3 09:30:18 2013
From: rostedt at goodmis.org (Steven Rostedt)
Date: Fri, 03 May 2013 09:30:18 -0400
Subject: [PATCH, RFC 14/22] oprofile: always enable IRQ_WORK
In-Reply-To: <20130503115332.GT8356@rric.localhost>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-15-git-send-email-arnd@arndb.de>
 <20130503115332.GT8356@rric.localhost>
Message-ID: <1367587818.7373.12.camel@gandalf.local.home>

On Fri, 2013-05-03 at 13:53 +0200, Robert Richter wrote:
> On 02.05.13 17:16:18, Arnd Bergmann wrote:
> > oprofile fails to build if CONFIG_IRQ_WORK is not already enabled,
> > because of the dependency on the RING_BUFFER code that now uses
> > the irq work library.
> > 
> > kernel/built-in.o: In function `ring_buffer_unlock_commit':
> > :(.text+0x5b8f0): undefined reference to `irq_work_queue'
> > kernel/built-in.o: In function `ring_buffer_write':
> > :(.text+0x5bd10): undefined reference to `irq_work_queue'
> 
> Shouldn't this be fixed in the ring_buffer implementation?

Hmm, I thought I had ring buffer select irq work. I must have not have
done that.

> 
> I also do not see, where this comes from. I was successfully compiling
> a kernel with OPROFILE and RING_BUFFER enabled but IRQ_WORK disabled.
> Do you have that config still available?
> 

The ring buffer code can now wake up waiters, and to do so it requires
irq_work. I'll send a patch.

Thanks,

-- Steve





From linus.walleij at linaro.org  Fri May  3 09:33:17 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 15:33:17 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <1883078.Smcmxe7hlB@wuerfel>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <15723843.9mConxltov@wuerfel>
 <CACRpkdYgGVepjaGY=1HP-GxE0mzTozA0aaT=jPe=aCPb5ppi9A@mail.gmail.com>
 <1883078.Smcmxe7hlB@wuerfel>
Message-ID: <CACRpkdaNd0Ej-bM0MaXNdyHeWWH0CMi+mKKvtV5-891OFETtEA@mail.gmail.com>

On Fri, May 3, 2013 at 2:48 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> I think we can certainly eliminate the ABX500 option, this one can
> just get selected by AB3100 and AB8500. The PRCMU can also
> be silent because as you say it is always needed.

OK sounds like a plan.

> The GPADC driver is interesting: it does not have its own user
> interface (besides the debugging driver) and could just get selected
> by the other drivers using its exported interfaces. It would
> also be better to convert it to the standard IIO ADC interface,
> but I don't know if that's realistic.

This should be moved over to IIO ADC, that subsystem however
did not exist when this driver was submitted, that is why it ended
up in MFD. As usual someone needs to go hack on it...

> This leavs the debugging
> interface as the only sub-option. Do you know if that is
> actually being used by developers, or is this one of those interfaces
> that were created during bringup and then never touched again
> after everything worked?

Something like that, but as long as new platforms using that
ASIC is coming out it remains quite usable for this.

It is also used for hardware validation, where you hook up the
system with a lot of electric probes and want to set specific
bits here and there to validate functionality. There just a minor
change to the silicon or packaging triggers such re-validation.

The usecase is similar to the debug interface we invented for
pin control recently, however there we managed to make things
centralized.

> Regarding AB3100, I assume the relationship to U300 is similar to
> that between DB8500 and AB8500. Are you able to boot a U300 system
> without touching AB3100?

I would say no. The system will be in some bootstrap state unless
you bring up the AB3100, and especially the regulators.

These are default y but should arguably be selected y
instead.

The U300 SoC will bootstrap power in a strange way until the
regulators are up, and then hand over to software-controlled
regulators for powering the SoC and release that bootstrap.

This is not harmful but a very strange and it's doubtful whether
I would call that "fully booted". It's something like booting
into "safe mode"
http://en.wikipedia.org/wiki/Safe_mode

Not enabling regulators on the U300 will have other strange
effects ... like MMC/SD not working. Yet we can not have
depends on REGULATORS in the Kconfig for the MMCI driver
since this driver is also used on systems without the regulator
framework (hardwired power).

All these run-time "makes sense" is in a bit of flux as compared
to config-and-compile-time "makes sense" unfortunately.

I lean toward selecting AB3100 and REGULATOR_AB3100
for the U300 actually.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 09:39:42 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 15:39:42 +0200
Subject: [GIT PULL] mailbox driver framework for v3.10 merge window
In-Reply-To: <1407180.uGFidLMFHk@wuerfel>
References: <37C860A02101E749A747FA2D3C1E3C504A1971@DLEE11.ent.ti.com>
 <CAJe_Zhf5QwQQU5aVtNhbDT3EK9Dof-ZK_boP9WaNghqO8xY7iA@mail.gmail.com>
 <5182E403.1030808@ti.com> <1407180.uGFidLMFHk@wuerfel>
Message-ID: <CACRpkdYSnNeO8F-1WWN9J+pkMi6B_Qydo85QovbgWOEoDDS9Aw@mail.gmail.com>

On Fri, May 3, 2013 at 3:25 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 02 May 2013 17:09:07 Suman Anna wrote:
>>
>> I do not know how much of an impact it is for the ST driver as the
>> series adds the driver, and would have to wait until the RFC is sorted
>> out otherwise.
>
> I think I'd prefer to drop the branch from the 3.10 queue then
> and let you all work out a common approach for 3.11. Olof, any
> other input?

This will block all refactoring of the PRCMU driver, which Loic
is working on, and also Ulf Hansson's clock driver. It is basically
the key to breaking that driver apart and distributing it out into
the proper subsystems. Loic has a big patch series for that
for next merge window which will then have to be postponed,
or queued on top of the mailbox work when finished.

But maybe it's the right thing to do if the subsystem needs more
work? I have no clear opinion on this, Loic, Ulf?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 09:41:14 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 15:41:14 +0200
Subject: [PATCH 2/4 v2] mfd: ab8500-gpadc: Suppress 'ignoring
 regulator_enable() return value' warning
In-Reply-To: <20130503111537.GH24153@gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
 <20130503111537.GH24153@gmail.com>
Message-ID: <CACRpkdZUDFakgYbUsbm6y9G0TqNr2z8U-f3Y1T6vNR1+CvLpKg@mail.gmail.com>

On Fri, May 3, 2013 at 1:15 PM, Lee Jones <lee.jones at linaro.org> wrote:

> drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
> drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
>         ?regulator_enable?, declared with attribute warn_unused_result
>         [-Wunused-result]
>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 09:42:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 15:42:38 +0200
Subject: [PATCH 1/5 v2] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <20130503121135.GK24153@gmail.com>
References: <1367336497-10650-1-git-send-email-lee.jones@linaro.org>
 <20130501095243.GD25256@gmail.com>
 <CACRpkdZtOtnUYvLm7BPA98oMOLAMPHpJ9GLoyMXOKW1nsTDYiQ@mail.gmail.com>
 <20130503115739.GJ24153@gmail.com>
 <CACRpkdb-_pf=9cm_Hy25nzFWKSTKc6OmmG9rhN2T1wR1=2tddg@mail.gmail.com>
 <20130503121135.GK24153@gmail.com>
Message-ID: <CACRpkdaUO=j2Ugd5MKA2iUKV_VX5KJMw=R6hCpA_MjrCQNB+fA@mail.gmail.com>

On Fri, May 3, 2013 at 2:11 PM, Lee Jones <lee.jones at linaro.org> wrote:

>> Then just arch/arm/boot/dts/* separately.
>
> I'm confused, that's how it is already:

Hm haha yes :-)

> Are you getting enough sleep? ;)

It's more like I'm getting too many patch series...

Yours,
Linus Walleij


From thierry.reding at avionic-design.de  Fri May  3 09:45:39 2013
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 3 May 2013 15:45:39 +0200
Subject: [PATCH, RFC 06/22] gpu/drm: host1x: add dependency on Tegra
In-Reply-To: <1367507786-505303-7-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-7-git-send-email-arnd@arndb.de>
Message-ID: <20130503134539.GA18652@avionic-0098.adnet.avionic-design.de>

On Thu, May 02, 2013 at 05:16:10PM +0200, Arnd Bergmann wrote:
> While we try to make drivers platform independent, this driver currently
> calls into an exported interface that is only provided on its own
> platform, so we have to add the dependency.
> 
> drivers/built-in.o: In function `tegra_crtc_prepare':
>  drivers/gpu/host1x/drm/dc.c:650: undefined reference to `tegra_periph_reset_deassert'
> drivers/built-in.o: In function `tegra_output_hdmi_disable':
>  drivers/gpu/host1x/drm/hdmi.c:840: undefined reference to `tegra_periph_reset_assert'
> drivers/built-in.o: In function `tegra_output_hdmi_enable':
>  drivers/gpu/host1x/drm/hdmi.c:651: undefined reference to `tegra_periph_reset_assert'
>  drivers/gpu/host1x/drm/hdmi.c:653: undefined reference to `tegra_periph_reset_deassert'
> 
> Cc: Thierry Reding <thierry.reding at avionic-design.de>
> Cc: Arto Merilainen <amerilainen at nvidia.com>
> Cc: Terje Bergstrom <tbergstrom at nvidia.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/gpu/host1x/drm/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/host1x/drm/Kconfig b/drivers/gpu/host1x/drm/Kconfig
> index 69853a4..5a6a5cd 100644
> --- a/drivers/gpu/host1x/drm/Kconfig
> +++ b/drivers/gpu/host1x/drm/Kconfig
> @@ -1,6 +1,7 @@
>  config DRM_TEGRA
>  	bool "NVIDIA Tegra DRM"
>  	depends on DRM
> +	depends on ARCH_TEGRA
>  	select DRM_KMS_HELPER
>  	select FB_SYS_FILLRECT
>  	select FB_SYS_COPYAREA

This was solved by a patch that went into Dave's DRM pull request for
3.10 by adding:

	depends on ARCH_TEGRA || ARCH_MULTIPLATFORM

to the Kconfig entry for TEGRA_HOST1X. The plan was to eventually remove
ARCH_TEGRA from that condition after 3.10 since ARCH_MULTIPLATFORM will
include ARCH_TEGRA anyway. I'm not sure why that patch hasn't made it
into linux-next yet, though.

Thierry
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From arnd at arndb.de  Fri May  3 09:49:05 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 15:49:05 +0200
Subject: [GIT PULL] mailbox driver framework for v3.10 merge window
In-Reply-To: <CACRpkdYSnNeO8F-1WWN9J+pkMi6B_Qydo85QovbgWOEoDDS9Aw@mail.gmail.com>
References: <37C860A02101E749A747FA2D3C1E3C504A1971@DLEE11.ent.ti.com>
 <1407180.uGFidLMFHk@wuerfel>
 <CACRpkdYSnNeO8F-1WWN9J+pkMi6B_Qydo85QovbgWOEoDDS9Aw@mail.gmail.com>
Message-ID: <4518021.h47erc1rfT@wuerfel>

On Friday 03 May 2013 15:39:42 Linus Walleij wrote:
> On Fri, May 3, 2013 at 3:25 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Thursday 02 May 2013 17:09:07 Suman Anna wrote:
> >>
> >> I do not know how much of an impact it is for the ST driver as the
> >> series adds the driver, and would have to wait until the RFC is sorted
> >> out otherwise.
> >
> > I think I'd prefer to drop the branch from the 3.10 queue then
> > and let you all work out a common approach for 3.11. Olof, any
> > other input?
> 
> This will block all refactoring of the PRCMU driver, which Loic
> is working on, and also Ulf Hansson's clock driver. It is basically
> the key to breaking that driver apart and distributing it out into
> the proper subsystems. Loic has a big patch series for that
> for next merge window which will then have to be postponed,
> or queued on top of the mailbox work when finished.
> 
> But maybe it's the right thing to do if the subsystem needs more
> work? I have no clear opinion on this, Loic, Ulf?

I think we can queue them together. I'm certainly fine with the
mailbox subsystem getting merged through both the mfd and arm-soc
trees to avoid conflicts.

	Arnd


From heiko at sntech.de  Fri May  3 09:52:45 2013
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Fri, 3 May 2013 15:52:45 +0200
Subject: [PATCH v5] pinctrl: Add pinctrl-s3c24xx driver
Message-ID: <201305031552.45410.heiko@sntech.de>

The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.

The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller instead. We solve this by forwarding the external
interrupt from the main controller into the irq domain of the pin bank.
The masking/acking of these interrupts is handled in the same way.

Furthermore the S3C2412/2413 SoCs contain another oddity in that they
keep the same 4 eints in the main interrupt controller and eintpend
register and requiring ack operations to happen in both. This is solved
by using different compatible properties for the wakeup eint node which
set a property accordingly.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
Reviewed-by: Tomasz Figa <t.figa at samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
changes since v4:
- fix wrong s3c2413 naming
  between s3c2412 and s3c2413, the s3c2412 is the base type. Till v4 the
  naming was mixed up, with parts being labeled as s3c2412* and others
  as s3c2413*. Fix this by renaming the s3c2413* parts to s3c2412.
  No functional changes.

changes since v3:
- address comments from Sylwester Nawrocki:
  (typos, wrong comments, etc)

changes since v2:
- address more comments from Tomasz Figa:
  * remove obsolete ctrl_type references
  * remove redundant check for parent_chip
  * update docs and commit message

changes since v1:
- address comments from Tomasz Figa:
  * split handling functions for eints 0-3 for s3c2412 and all others
  * change the handling for s3c2412 eints 0-3 in that they now use
    chained_irq_* for the outer parent interrupt

 .../bindings/pinctrl/samsung-pinctrl.txt           |    8 +
 drivers/gpio/gpio-samsung.c                        |    4 +
 drivers/pinctrl/Kconfig                            |    5 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-s3c24xx.c                  |  652 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.c                  |   10 +
 drivers/pinctrl/pinctrl-samsung.h                  |    4 +
 7 files changed, 684 insertions(+), 0 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-s3c24xx.c

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index c70fca1..dc50c7e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -7,6 +7,10 @@ on-chip controllers onto these pads.
 
 Required Properties:
 - compatible: should be one of the following.
+  - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
+  - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
+  - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
+  - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
   - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
   - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
   - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
@@ -106,6 +110,10 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
 
    - compatible: identifies the type of the external wakeup interrupt controller
      The possible values are:
+     - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller
+       found on Samsung S3C24xx SoCs except S3C2412 and S3C2413,
+     - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller
+       found on Samsung S3C2412 and S3C2413 SoCs,
      - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
        found on Samsung S3C64xx SoCs,
      - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index dc06a6f..73017b9 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3026,6 +3026,10 @@ static __init int samsung_gpiolib_init(void)
 	*/
 	struct device_node *pctrl_np;
 	static const struct of_device_id exynos_pinctrl_ids[] = {
+		{ .compatible = "samsung,s3c2412-pinctrl", },
+		{ .compatible = "samsung,s3c2416-pinctrl", },
+		{ .compatible = "samsung,s3c2440-pinctrl", },
+		{ .compatible = "samsung,s3c2450-pinctrl", },
 		{ .compatible = "samsung,s3c64xx-pinctrl", },
 		{ .compatible = "samsung,exynos4210-pinctrl", },
 		{ .compatible = "samsung,exynos4x12-pinctrl", },
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7402ac9..58d73ac 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -226,6 +226,11 @@ config PINCTRL_EXYNOS5440
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_S3C24XX
+	bool "Samsung S3C24XX SoC pinctrl driver"
+	depends on ARCH_S3C24XX
+	select PINCTRL_SAMSUNG
+
 config PINCTRL_S3C64XX
 	bool "Samsung S3C64XX SoC pinctrl driver"
 	depends on ARCH_S3C64XX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 21d34c2..1ccdfd8 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
 obj-$(CONFIG_PINCTRL_EXYNOS)	+= pinctrl-exynos.o
 obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
+obj-$(CONFIG_PINCTRL_S3C24XX)	+= pinctrl-s3c24xx.o
 obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/pinctrl-s3c24xx.c
new file mode 100644
index 0000000..efd0908
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-s3c24xx.c
@@ -0,0 +1,652 @@
+/*
+ * S3C24XX specific support for Samsung pinctrl/gpiolib driver.
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko at sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file contains the SamsungS3C24XX specific information required by the
+ * Samsung pinctrl/gpiolib driver. It also includes the implementation of
+ * external gpio and wakeup interrupt support.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <asm/mach/irq.h>
+
+#include "pinctrl-samsung.h"
+
+#define NUM_EINT	24
+#define NUM_EINT_IRQ	6
+#define EINT_MAX_PER_GROUP	8
+
+#define EINTPEND_REG	0xa8
+#define EINTMASK_REG	0xa4
+
+#define EINT_GROUP(i)		((int)((i) / EINT_MAX_PER_GROUP))
+#define EINT_REG(i)		((EINT_GROUP(i) * 4) + 0x88)
+#define EINT_OFFS(i)		((i) % EINT_MAX_PER_GROUP * 4)
+
+#define EINT_LEVEL_LOW		0
+#define EINT_LEVEL_HIGH		1
+#define EINT_EDGE_FALLING	2
+#define EINT_EDGE_RISING	4
+#define EINT_EDGE_BOTH		6
+#define EINT_MASK		0xf
+
+static struct samsung_pin_bank_type bank_type_1bit = {
+	.fld_width = { 1, 1, },
+	.reg_offset = { 0x00, 0x04, },
+};
+
+static struct samsung_pin_bank_type bank_type_2bit = {
+	.fld_width = { 2, 1, 2, },
+	.reg_offset = { 0x00, 0x04, 0x08, },
+};
+
+#define PIN_BANK_A(pins, reg, id)		\
+	{						\
+		.type		= &bank_type_1bit,	\
+		.pctl_offset	= reg,			\
+		.nr_pins	= pins,			\
+		.eint_type	= EINT_TYPE_NONE,	\
+		.name		= id			\
+	}
+
+#define PIN_BANK_2BIT(pins, reg, id)		\
+	{						\
+		.type		= &bank_type_2bit,	\
+		.pctl_offset	= reg,			\
+		.nr_pins	= pins,			\
+		.eint_type	= EINT_TYPE_NONE,	\
+		.name		= id			\
+	}
+
+#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
+	{						\
+		.type		= &bank_type_2bit,	\
+		.pctl_offset	= reg,			\
+		.nr_pins	= pins,			\
+		.eint_type	= EINT_TYPE_WKUP,	\
+		.eint_func	= 2,			\
+		.eint_mask	= emask,		\
+		.eint_offset	= eoffs,		\
+		.name		= id			\
+	}
+
+/**
+ * struct s3c24xx_eint_data: EINT common data
+ * @drvdata: pin controller driver data
+ * @domains: IRQ domains of particular EINT interrupts
+ * @parents: mapped parent irqs in the main interrupt controller
+ */
+struct s3c24xx_eint_data {
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct irq_domain *domains[NUM_EINT];
+	int parents[NUM_EINT_IRQ];
+};
+
+/**
+ * struct s3c24xx_eint_domain_data: per irq-domain data
+ * @bank: pin bank related to the domain
+ * @eint_data: common data
+ * eint0_3_parent_only: live eints 0-3 only in the main intc
+ */
+struct s3c24xx_eint_domain_data {
+	struct samsung_pin_bank *bank;
+	struct s3c24xx_eint_data *eint_data;
+	bool eint0_3_parent_only;
+};
+
+static int s3c24xx_eint_get_trigger(unsigned int type)
+{
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		return EINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		return EINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		return EINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		return EINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		return EINT_LEVEL_LOW;
+		break;
+	default:
+		return -EINVAL;
+	}
+}
+
+static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type)
+{
+	/* Edge- and level-triggered interrupts need different handlers */
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		__irq_set_handler_locked(irq, handle_edge_irq);
+	else
+		__irq_set_handler_locked(irq, handle_level_irq);
+}
+
+static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
+					struct samsung_pin_bank *bank, int pin)
+{
+	struct samsung_pin_bank_type *bank_type = bank->type;
+	unsigned long flags;
+	void __iomem *reg;
+	u8 shift;
+	u32 mask;
+	u32 val;
+
+	/* Make sure that pin is configured as interrupt */
+	reg = d->virt_base + bank->pctl_offset;
+	shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
+	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+
+	spin_lock_irqsave(&bank->slock, flags);
+
+	val = readl(reg);
+	val &= ~(mask << shift);
+	val |= bank->eint_func << shift;
+	writel(val, reg);
+
+	spin_unlock_irqrestore(&bank->slock, flags);
+}
+
+static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+	int index = bank->eint_offset + data->hwirq;
+	void __iomem *reg;
+	int trigger;
+	u8 shift;
+	u32 val;
+
+	trigger = s3c24xx_eint_get_trigger(type);
+	if (trigger < 0) {
+		dev_err(d->dev, "unsupported external interrupt type\n");
+		return -EINVAL;
+	}
+
+	s3c24xx_eint_set_handler(data->irq, type);
+
+	/* Set up interrupt trigger */
+	reg = d->virt_base + EINT_REG(index);
+	shift = EINT_OFFS(index);
+
+	val = readl(reg);
+	val &= ~(EINT_MASK << shift);
+	val |= trigger << shift;
+	writel(val, reg);
+
+	s3c24xx_eint_set_function(d, bank, data->hwirq);
+
+	return 0;
+}
+
+/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
+
+static void s3c2410_eint0_3_ack(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
+	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
+	int parent_irq = eint_data->parents[data->hwirq];
+	struct irq_chip *parent_chip = irq_get_chip(parent_irq);
+
+	parent_chip->irq_ack(irq_get_irq_data(parent_irq));
+}
+
+static void s3c2410_eint0_3_mask(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
+	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
+	int parent_irq = eint_data->parents[data->hwirq];
+	struct irq_chip *parent_chip = irq_get_chip(parent_irq);
+
+	parent_chip->irq_mask(irq_get_irq_data(parent_irq));
+}
+
+static void s3c2410_eint0_3_unmask(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
+	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
+	int parent_irq = eint_data->parents[data->hwirq];
+	struct irq_chip *parent_chip = irq_get_chip(parent_irq);
+
+	parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
+}
+
+static struct irq_chip s3c2410_eint0_3_chip = {
+	.name		= "s3c2410-eint0_3",
+	.irq_ack	= s3c2410_eint0_3_ack,
+	.irq_mask	= s3c2410_eint0_3_mask,
+	.irq_unmask	= s3c2410_eint0_3_unmask,
+	.irq_set_type	= s3c24xx_eint_type,
+};
+
+static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_data *data = irq_desc_get_irq_data(desc);
+	struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
+	unsigned int virq;
+
+	/* the first 4 eints have a simple 1 to 1 mapping */
+	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
+	/* Something must be really wrong if an unmapped EINT is unmasked */
+	BUG_ON(!virq);
+
+	generic_handle_irq(virq);
+}
+
+/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
+
+static void s3c2412_eint0_3_ack(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+
+	unsigned long bitval = 1UL << data->hwirq;
+	writel(bitval, d->virt_base + EINTPEND_REG);
+}
+
+static void s3c2412_eint0_3_mask(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + EINTMASK_REG);
+	mask |= (1UL << data->hwirq);
+	writel(mask, d->virt_base + EINTMASK_REG);
+}
+
+static void s3c2412_eint0_3_unmask(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + EINTMASK_REG);
+	mask &= ~(1UL << data->hwirq);
+	writel(mask, d->virt_base + EINTMASK_REG);
+}
+
+static struct irq_chip s3c2412_eint0_3_chip = {
+	.name		= "s3c2412-eint0_3",
+	.irq_ack	= s3c2412_eint0_3_ack,
+	.irq_mask	= s3c2412_eint0_3_mask,
+	.irq_unmask	= s3c2412_eint0_3_unmask,
+	.irq_set_type	= s3c24xx_eint_type,
+};
+
+static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct irq_data *data = irq_desc_get_irq_data(desc);
+	struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
+	unsigned int virq;
+
+	chained_irq_enter(chip, desc);
+
+	/* the first 4 eints have a simple 1 to 1 mapping */
+	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
+	/* Something must be really wrong if an unmapped EINT is unmasked */
+	BUG_ON(!virq);
+
+	generic_handle_irq(virq);
+
+	chained_irq_exit(chip, desc);
+}
+
+/* Handling of all other eints */
+
+static void s3c24xx_eint_ack(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+	unsigned char index = bank->eint_offset + data->hwirq;
+
+	writel(1UL << index, d->virt_base + EINTPEND_REG);
+}
+
+static void s3c24xx_eint_mask(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+	unsigned char index = bank->eint_offset + data->hwirq;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + EINTMASK_REG);
+	mask |= (1UL << index);
+	writel(mask, d->virt_base + EINTMASK_REG);
+}
+
+static void s3c24xx_eint_unmask(struct irq_data *data)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
+	unsigned char index = bank->eint_offset + data->hwirq;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + EINTMASK_REG);
+	mask &= ~(1UL << index);
+	writel(mask, d->virt_base + EINTMASK_REG);
+}
+
+static struct irq_chip s3c24xx_eint_chip = {
+	.name		= "s3c-eint",
+	.irq_ack	= s3c24xx_eint_ack,
+	.irq_mask	= s3c24xx_eint_mask,
+	.irq_unmask	= s3c24xx_eint_unmask,
+	.irq_set_type	= s3c24xx_eint_type,
+};
+
+static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc,
+				      u32 offset, u32 range)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct s3c24xx_eint_data *data = irq_get_handler_data(irq);
+	struct samsung_pinctrl_drv_data *d = data->drvdata;
+	unsigned int pend, mask;
+
+	chained_irq_enter(chip, desc);
+
+	pend = readl(d->virt_base + EINTPEND_REG);
+	mask = readl(d->virt_base + EINTMASK_REG);
+
+	pend &= ~mask;
+	pend &= range;
+
+	while (pend) {
+		unsigned int virq;
+
+		irq = __ffs(pend);
+		pend &= ~(1 << irq);
+		virq = irq_linear_revmap(data->domains[irq], irq - offset);
+		/* Something is really wrong if an unmapped EINT is unmasked */
+		BUG_ON(!virq);
+
+		generic_handle_irq(virq);
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc)
+{
+	s3c24xx_demux_eint(irq, desc, 0, 0xf0);
+}
+
+static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc)
+{
+	s3c24xx_demux_eint(irq, desc, 8, 0xffff00);
+}
+
+static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
+	s3c2410_demux_eint0_3,
+	s3c2410_demux_eint0_3,
+	s3c2410_demux_eint0_3,
+	s3c2410_demux_eint0_3,
+	s3c24xx_demux_eint4_7,
+	s3c24xx_demux_eint8_23,
+};
+
+static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
+	s3c2412_demux_eint0_3,
+	s3c2412_demux_eint0_3,
+	s3c2412_demux_eint0_3,
+	s3c2412_demux_eint0_3,
+	s3c24xx_demux_eint4_7,
+	s3c24xx_demux_eint8_23,
+};
+
+static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
+					irq_hw_number_t hw)
+{
+	struct s3c24xx_eint_domain_data *ddata = h->host_data;
+	struct samsung_pin_bank *bank = ddata->bank;
+
+	if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
+		return -EINVAL;
+
+	if (hw <= 3) {
+		if (ddata->eint0_3_parent_only)
+			irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
+						 handle_edge_irq);
+		else
+			irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
+						 handle_edge_irq);
+	} else {
+		irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
+					 handle_edge_irq);
+	}
+	irq_set_chip_data(virq, bank);
+	set_irq_flags(virq, IRQF_VALID);
+	return 0;
+}
+
+static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
+	.map	= s3c24xx_gpf_irq_map,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
+					irq_hw_number_t hw)
+{
+	struct s3c24xx_eint_domain_data *ddata = h->host_data;
+	struct samsung_pin_bank *bank = ddata->bank;
+
+	if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
+		return -EINVAL;
+
+	irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
+	irq_set_chip_data(virq, bank);
+	set_irq_flags(virq, IRQF_VALID);
+	return 0;
+}
+
+static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
+	.map	= s3c24xx_gpg_irq_map,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+static const struct of_device_id s3c24xx_eint_irq_ids[] = {
+	{ .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
+	{ .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
+	{ }
+};
+
+static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
+{
+	struct device *dev = d->dev;
+	const struct of_device_id *match;
+	struct device_node *eint_np = NULL;
+	struct device_node *np;
+	struct samsung_pin_bank *bank;
+	struct s3c24xx_eint_data *eint_data;
+	const struct irq_domain_ops *ops;
+	unsigned int i;
+	bool eint0_3_parent_only;
+	irq_flow_handler_t *handlers;
+
+	for_each_child_of_node(dev->of_node, np) {
+		match = of_match_node(s3c24xx_eint_irq_ids, np);
+		if (match) {
+			eint_np = np;
+			eint0_3_parent_only = (bool)match->data;
+			break;
+		}
+	}
+	if (!eint_np)
+		return -ENODEV;
+
+	eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
+	if (!eint_data)
+		return -ENOMEM;
+
+	eint_data->drvdata = d;
+
+	handlers = eint0_3_parent_only ? s3c2410_eint_handlers
+				       : s3c2412_eint_handlers;
+	for (i = 0; i < NUM_EINT_IRQ; ++i) {
+		unsigned int irq;
+
+		irq = irq_of_parse_and_map(eint_np, i);
+		if (!irq) {
+			dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
+			return -ENXIO;
+		}
+
+		eint_data->parents[i] = irq;
+		irq_set_chained_handler(irq, handlers[i]);
+		irq_set_handler_data(irq, eint_data);
+	}
+
+	bank = d->ctrl->pin_banks;
+	for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
+		struct s3c24xx_eint_domain_data *ddata;
+		unsigned int mask;
+		unsigned int irq;
+		unsigned int pin;
+
+		if (bank->eint_type != EINT_TYPE_WKUP)
+			continue;
+
+		ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
+		if (!ddata)
+			return -ENOMEM;
+
+		ddata->bank = bank;
+		ddata->eint_data = eint_data;
+		ddata->eint0_3_parent_only = eint0_3_parent_only;
+
+		ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
+					       : &s3c24xx_gpg_irq_ops;
+
+		bank->irq_domain = irq_domain_add_linear(bank->of_node,
+				bank->nr_pins, ops, ddata);
+		if (!bank->irq_domain) {
+			dev_err(dev, "wkup irq domain add failed\n");
+			return -ENXIO;
+		}
+
+		irq = bank->eint_offset;
+		mask = bank->eint_mask;
+		for (pin = 0; mask; ++pin, mask >>= 1) {
+			if (irq > NUM_EINT)
+				break;
+			if (!(mask & 1))
+				continue;
+			eint_data->domains[irq] = bank->irq_domain;
+			++irq;
+		}
+	}
+
+	return 0;
+}
+
+static struct samsung_pin_bank s3c2412_pin_banks[] = {
+	PIN_BANK_A(23, 0x000, "gpa"),
+	PIN_BANK_2BIT(11, 0x010, "gpb"),
+	PIN_BANK_2BIT(16, 0x020, "gpc"),
+	PIN_BANK_2BIT(16, 0x030, "gpd"),
+	PIN_BANK_2BIT(16, 0x040, "gpe"),
+	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
+	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
+	PIN_BANK_2BIT(11, 0x070, "gph"),
+	PIN_BANK_2BIT(13, 0x080, "gpj"),
+};
+
+struct samsung_pin_ctrl s3c2412_pin_ctrl[] = {
+	{
+		.pin_banks	= s3c2412_pin_banks,
+		.nr_banks	= ARRAY_SIZE(s3c2412_pin_banks),
+		.eint_wkup_init = s3c24xx_eint_init,
+		.label		= "S3C2412-GPIO",
+	},
+};
+
+static struct samsung_pin_bank s3c2416_pin_banks[] = {
+	PIN_BANK_A(27, 0x000, "gpa"),
+	PIN_BANK_2BIT(11, 0x010, "gpb"),
+	PIN_BANK_2BIT(16, 0x020, "gpc"),
+	PIN_BANK_2BIT(16, 0x030, "gpd"),
+	PIN_BANK_2BIT(16, 0x040, "gpe"),
+	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
+	PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
+	PIN_BANK_2BIT(15, 0x070, "gph"),
+	PIN_BANK_2BIT(16, 0x0e0, "gpk"),
+	PIN_BANK_2BIT(14, 0x0f0, "gpl"),
+	PIN_BANK_2BIT(2, 0x100, "gpm"),
+};
+
+struct samsung_pin_ctrl s3c2416_pin_ctrl[] = {
+	{
+		.pin_banks	= s3c2416_pin_banks,
+		.nr_banks	= ARRAY_SIZE(s3c2416_pin_banks),
+		.eint_wkup_init = s3c24xx_eint_init,
+		.label		= "S3C2416-GPIO",
+	},
+};
+
+static struct samsung_pin_bank s3c2440_pin_banks[] = {
+	PIN_BANK_A(25, 0x000, "gpa"),
+	PIN_BANK_2BIT(11, 0x010, "gpb"),
+	PIN_BANK_2BIT(16, 0x020, "gpc"),
+	PIN_BANK_2BIT(16, 0x030, "gpd"),
+	PIN_BANK_2BIT(16, 0x040, "gpe"),
+	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
+	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
+	PIN_BANK_2BIT(11, 0x070, "gph"),
+	PIN_BANK_2BIT(13, 0x0d0, "gpj"),
+};
+
+struct samsung_pin_ctrl s3c2440_pin_ctrl[] = {
+	{
+		.pin_banks	= s3c2440_pin_banks,
+		.nr_banks	= ARRAY_SIZE(s3c2440_pin_banks),
+		.eint_wkup_init = s3c24xx_eint_init,
+		.label		= "S3C2440-GPIO",
+	},
+};
+
+static struct samsung_pin_bank s3c2450_pin_banks[] = {
+	PIN_BANK_A(28, 0x000, "gpa"),
+	PIN_BANK_2BIT(11, 0x010, "gpb"),
+	PIN_BANK_2BIT(16, 0x020, "gpc"),
+	PIN_BANK_2BIT(16, 0x030, "gpd"),
+	PIN_BANK_2BIT(16, 0x040, "gpe"),
+	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
+	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
+	PIN_BANK_2BIT(15, 0x070, "gph"),
+	PIN_BANK_2BIT(16, 0x0d0, "gpj"),
+	PIN_BANK_2BIT(16, 0x0e0, "gpk"),
+	PIN_BANK_2BIT(15, 0x0f0, "gpl"),
+	PIN_BANK_2BIT(2, 0x100, "gpm"),
+};
+
+struct samsung_pin_ctrl s3c2450_pin_ctrl[] = {
+	{
+		.pin_banks	= s3c2450_pin_banks,
+		.nr_banks	= ARRAY_SIZE(s3c2450_pin_banks),
+		.eint_wkup_init = s3c24xx_eint_init,
+		.label		= "S3C2450-GPIO",
+	},
+};
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index e836135..234c32f 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -977,6 +977,16 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 	{ .compatible = "samsung,s3c64xx-pinctrl",
 		.data = s3c64xx_pin_ctrl },
 #endif
+#ifdef CONFIG_PINCTRL_S3C24XX
+	{ .compatible = "samsung,s3c2412-pinctrl",
+		.data = s3c2412_pin_ctrl },
+	{ .compatible = "samsung,s3c2416-pinctrl",
+		.data = s3c2416_pin_ctrl },
+	{ .compatible = "samsung,s3c2440-pinctrl",
+		.data = s3c2440_pin_ctrl },
+	{ .compatible = "samsung,s3c2450-pinctrl",
+		.data = s3c2450_pin_ctrl },
+#endif
 	{},
 };
 MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 7c7f9eb..c79d634 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -246,5 +246,9 @@ extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
 extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
+extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
+extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
+extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
+extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
 
 #endif /* __PINCTRL_SAMSUNG_H */
-- 
1.7.2.3



From lee.jones at linaro.org  Fri May  3 09:55:09 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 14:55:09 +0100
Subject: [PATCH 2/4 v2] mfd: ab8500-gpadc: Suppress 'ignoring
 regulator_enable() return value' warning
In-Reply-To: <CACRpkdZUDFakgYbUsbm6y9G0TqNr2z8U-f3Y1T6vNR1+CvLpKg@mail.gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-3-git-send-email-lee.jones@linaro.org>
 <20130503111537.GH24153@gmail.com>
 <CACRpkdZUDFakgYbUsbm6y9G0TqNr2z8U-f3Y1T6vNR1+CvLpKg@mail.gmail.com>
Message-ID: <20130503135509.GL24153@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 1:15 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > drivers/mfd/ab8500-gpadc.c: In function ?ab8500_gpadc_resume?:
> > drivers/mfd/ab8500-gpadc.c:911:18: warning: ignoring return value of
> >         ?regulator_enable?, declared with attribute warn_unused_result
> >         [-Wunused-result]
> >
> > Cc: Samuel Ortiz <sameo at linux.intel.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Yours,
> Linus Walleij

Nice, thanks. I'm applying this now.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From arnd at arndb.de  Fri May  3 09:56:42 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 15:56:42 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <CACRpkdaNd0Ej-bM0MaXNdyHeWWH0CMi+mKKvtV5-891OFETtEA@mail.gmail.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1883078.Smcmxe7hlB@wuerfel>
 <CACRpkdaNd0Ej-bM0MaXNdyHeWWH0CMi+mKKvtV5-891OFETtEA@mail.gmail.com>
Message-ID: <1500795.gEuGziRZET@wuerfel>

On Friday 03 May 2013 15:33:17 Linus Walleij wrote:
> On Fri, May 3, 2013 at 2:48 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> > This leavs the debugging
> > interface as the only sub-option. Do you know if that is
> > actually being used by developers, or is this one of those interfaces
> > that were created during bringup and then never touched again
> > after everything worked?
> 
> Something like that, but as long as new platforms using that
> ASIC is coming out it remains quite usable for this.
> 
> It is also used for hardware validation, where you hook up the
> system with a lot of electric probes and want to set specific
> bits here and there to validate functionality. There just a minor
> change to the silicon or packaging triggers such re-validation.
> 
> The usecase is similar to the debug interface we invented for
> pin control recently, however there we managed to make things
> centralized.

Ok, makes sense.

> > Regarding AB3100, I assume the relationship to U300 is similar to
> > that between DB8500 and AB8500. Are you able to boot a U300 system
> > without touching AB3100?
> 
> I would say no. The system will be in some bootstrap state unless
> you bring up the AB3100, and especially the regulators.
> 
> These are default y but should arguably be selected y
> instead.
> 
> The U300 SoC will bootstrap power in a strange way until the
> regulators are up, and then hand over to software-controlled
> regulators for powering the SoC and release that bootstrap.
> 
> This is not harmful but a very strange and it's doubtful whether
> I would call that "fully booted". It's something like booting
> into "safe mode"
> http://en.wikipedia.org/wiki/Safe_mode

I see.

> Not enabling regulators on the U300 will have other strange
> effects ... like MMC/SD not working. Yet we can not have
> depends on REGULATORS in the Kconfig for the MMCI driver
> since this driver is also used on systems without the regulator
> framework (hardwired power).
> 
> All these run-time "makes sense" is in a bit of flux as compared
> to config-and-compile-time "makes sense" unfortunately.
> 
> I lean toward selecting AB3100 and REGULATOR_AB3100
> for the U300 actually.

Should we still allow building them on other platforms then?
Right now, these depend on the platforms that actually use
the hardware, but in other places, we just allow everything to
be built that compiles without errors.
Is it theoretically possible to use the AB in combination with
another (non-ST-Ericsson) digital baseband?

	Arnd


From linus.walleij at linaro.org  Fri May  3 09:57:27 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 15:57:27 +0200
Subject: [PATCH 12/32] ARM: ux500: Remove superfluous 'psize' attribute
 from Audio platform data
In-Reply-To: <20130502083849.GH25256@gmail.com>
References: <1366279934-30761-1-git-send-email-lee.jones@linaro.org>
 <1366279934-30761-13-git-send-email-lee.jones@linaro.org>
 <20130501144213.GG25256@gmail.com>
 <20130502083849.GH25256@gmail.com>
Message-ID: <CACRpkdYbqU=bHrzf6Vpv-KFYN_+z6+y1ocNHtkLEO7ihHEd=dA@mail.gmail.com>

On Thu, May 2, 2013 at 10:38 AM, Lee Jones <lee.jones at linaro.org> wrote:

>> > 'psize' is used to calculate the maximum DMA burst size. However it
>> > is only taken into consideration when editing the DMA channel's
>> > configuration. The Audio DMA platform data is only used to allocate
>> > a channel, not configure it. That will be done at a later date within
>> > the MSP driver.
>> >
>> > We're also removing comments which are no longer required, as
>> > 'data_width' is no longer set in any device's platform data period.
>> >
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>

>> Linus Walleij wrote:
>> So if I understand correctly this is now handled by dmaengine_pcm.c,
>> os that right?
>
> Unfortunately not. At the moment ux500 sound is very broken in
> Mainline. I looked at it recently and the driver is almost completely
> different to the one maintained internally.

I was more thinking that the dmaengine_pcm.c which appears
to have its functions called from the ux500 ASoC driver should
do the calls to slave config to set up proper DMA characteristics
for the channel.

Maybe that part is in the MSP driver as you say, is that so?

> There were DMA changes relating to this driver pending for v3.10,
> which I believe have just been taking into -next. I will straighten
> out the DMA issues shortly, but there are other ones remaining still -
> mostly surrounding widgets. Ideally this is something Ola should fix,
> as he has the expertise to do so, but he doesn't appear to have been
> very active upstream of late.

IIRC there are also patches from Fabio to this stuff so I'm
a bit confused, but if the intention is to merge this through
ASoC with some other stuff, by all means:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From arnd at arndb.de  Fri May  3 10:02:04 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 16:02:04 +0200
Subject: [PATCH, RFC 06/22] gpu/drm: host1x: add dependency on Tegra
In-Reply-To: <20130503134539.GA18652@avionic-0098.adnet.avionic-design.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-7-git-send-email-arnd@arndb.de>
 <20130503134539.GA18652@avionic-0098.adnet.avionic-design.de>
Message-ID: <3432070.tv7Jup0G8r@wuerfel>

On Friday 03 May 2013 15:45:39 Thierry Reding wrote:
> > diff --git a/drivers/gpu/host1x/drm/Kconfig b/drivers/gpu/host1x/drm/Kconfig
> > index 69853a4..5a6a5cd 100644
> > --- a/drivers/gpu/host1x/drm/Kconfig
> > +++ b/drivers/gpu/host1x/drm/Kconfig
> > @@ -1,6 +1,7 @@
> >  config DRM_TEGRA
> >       bool "NVIDIA Tegra DRM"
> >       depends on DRM
> > +     depends on ARCH_TEGRA
> >       select DRM_KMS_HELPER
> >       select FB_SYS_FILLRECT
> >       select FB_SYS_COPYAREA
> 
> This was solved by a patch that went into Dave's DRM pull request for
> 3.10 by adding:
> 
>         depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
> 
> to the Kconfig entry for TEGRA_HOST1X. The plan was to eventually remove
> ARCH_TEGRA from that condition after 3.10 since ARCH_MULTIPLATFORM will
> include ARCH_TEGRA anyway. I'm not sure why that patch hasn't made it
> into linux-next yet, though.

I saw the problem with ARCH_MULTIPLATFORM enabled, so I don't understand
how adding the dependency above would help. A possible alternative
would be to define an empty alternative for the interface used here,
as the patch below.

	Arnd

diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 642789b..1397190 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,8 +120,13 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
+#ifdef ARCH_TEGRA
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
+#else
+static inline void tegra_periph_reset_deassert(struct clk *c) {}
+static inline void tegra_periph_reset_assert(struct clk *c) {}
+#endif
 void tegra_clocks_init(void);
 void tegra_clocks_apply_init_table(void);
 



From maxime.ripard at free-electrons.com  Fri May  3 10:01:47 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 03 May 2013 16:01:47 +0200
Subject: [PATCH] ARM: sun4i: cubieboard: Enable the i2c controllers
In-Reply-To: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>
References: <1367498266-1246-1-git-send-email-emilio@elopez.com.ar>
Message-ID: <5183C34B.8050801@free-electrons.com>

Hi Emilio,

Le 02/05/2013 14:37, Emilio L?pez a ?crit :
> The Cubieboard makes use of the first two i2c controllers found on the
> Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1
> is exposed on the board headers. This patch enables them in the device
> tree.
> 
> Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>

Thanks for this patch.

I'll merge it in my i2c patchset, so that every thing stays together.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From linus.walleij at linaro.org  Fri May  3 10:01:56 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 16:01:56 +0200
Subject: [PATCH] ARM: ux500: Remove DMA address look-up table
In-Reply-To: <1367484683-3479-1-git-send-email-lee.jones@linaro.org>
References: <1367484683-3479-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaeEDHNLFt2z=7L=iFbxbSkbe25mYxCG3+MreLsZZ21SA@mail.gmail.com>

On Thu, May 2, 2013 at 10:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA addresses are now passed as part of the dmaengine API by invoking
> dmaengine_slave_config(). So there's no requirement for the DMA40
> driver to look them up in a table provided by platform data. This
> method does not fit in well using Device Tree either.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This goes on top of some other changes right?

Right now the DMA series is confusing me a bit, there is
these 6 patches:
http://marc.info/?l=linux-arm-kernel&m=136698179306642&w=2

Then these 5 patches:
http://marc.info/?l=linux-arm-kernel&m=136740201416293&w=2

And then this single patch.

Where shall I start, i.e. which patches go first?

Can they all be combined into one big series?

Yours,
Linus Walleij


From marc.zyngier at arm.com  Fri May  3 10:02:53 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri,  3 May 2013 15:02:53 +0100
Subject: [RFC PATCH 2/2] ARM: KVM: standalone Makefile for vgic and timers
In-Reply-To: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367589773-5609-3-git-send-email-marc.zyngier@arm.com>

On the road to turn KVM/arm64 into something more sensible, change
the way we compile the VGIC and arch_timer code by using local
Makefiles instead of the very backward method we used before.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 Makefile              | 2 +-
 arch/arm/kvm/Makefile | 2 --
 virt/Makefile         | 1 +
 virt/kvm/Makefile     | 1 +
 virt/kvm/arm/Makefile | 2 ++
 5 files changed, 5 insertions(+), 3 deletions(-)
 create mode 100644 virt/Makefile
 create mode 100644 virt/kvm/Makefile
 create mode 100644 virt/kvm/arm/Makefile

diff --git a/Makefile b/Makefile
index 6db672b..19d51df 100644
--- a/Makefile
+++ b/Makefile
@@ -732,7 +732,7 @@ export mod_sign_cmd
 
 
 ifeq ($(KBUILD_EXTMOD),)
-core-y		+= kernel/ mm/ fs/ ipc/ security/ crypto/ block/
+core-y		+= kernel/ mm/ fs/ ipc/ security/ crypto/ block/ virt/
 
 vmlinux-dirs	:= $(patsubst %/,%,$(filter %/, $(init-y) $(init-m) \
 		     $(core-y) $(core-m) $(drivers-y) $(drivers-m) \
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 110d6da..e0540fd 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -20,5 +20,3 @@ kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += $(addprefix $(KVM)/arm/, vgic.o)
-obj-$(CONFIG_KVM_ARM_TIMER) += $(addprefix $(KVM)/arm/, arch_timer.o)
diff --git a/virt/Makefile b/virt/Makefile
new file mode 100644
index 0000000..c3b9ad0
--- /dev/null
+++ b/virt/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_KVM)	+= kvm/
diff --git a/virt/kvm/Makefile b/virt/kvm/Makefile
new file mode 100644
index 0000000..dc87943
--- /dev/null
+++ b/virt/kvm/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_KVM_ARM_HOST)	+= arm/
diff --git a/virt/kvm/arm/Makefile b/virt/kvm/arm/Makefile
new file mode 100644
index 0000000..4df943b
--- /dev/null
+++ b/virt/kvm/arm/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
-- 
1.8.2.1




From marc.zyngier at arm.com  Fri May  3 10:02:51 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri,  3 May 2013 15:02:51 +0100
Subject: [RFC PATCH 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
Message-ID: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

Once the code has been moved, it becomes easy to build it in a
less hackish way, which makes the code easily reusable by KVM/arm64.

Marc Zyngier (2):
  ARM: KVM: move GIC/timer code to a common location
  ARM: KVM: standalone Makefile for vgic and timers

 Makefile                                               | 2 +-
 arch/arm/include/asm/kvm_host.h                        | 4 ++--
 arch/arm/kvm/Makefile                                  | 5 ++---
 {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
 {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
 virt/Makefile                                          | 1 +
 virt/kvm/Makefile                                      | 1 +
 virt/kvm/arm/Makefile                                  | 2 ++
 {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
 {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
 10 files changed, 11 insertions(+), 8 deletions(-)
 rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
 rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
 create mode 100644 virt/Makefile
 create mode 100644 virt/kvm/Makefile
 create mode 100644 virt/kvm/arm/Makefile
 rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
 rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)

-- 
1.8.2.1




From marc.zyngier at arm.com  Fri May  3 10:02:52 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri,  3 May 2013 15:02:52 +0100
Subject: [RFC PATCH 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

Eventually, we should probably have independant Makefiles at every
levels (just like everywhere else in the kernel), but this is just
the first step.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_host.h                        | 4 ++--
 arch/arm/kvm/Makefile                                  | 7 ++++---
 {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
 {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
 {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
 {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
 6 files changed, 8 insertions(+), 7 deletions(-)
 rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
 rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
 rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
 rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index ff49193..4ad51e6 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,7 +23,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/kvm_arch_timer.h>
 
 #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
 #define KVM_USER_MEM_SLOTS 32
@@ -38,7 +38,7 @@
 #define KVM_NR_PAGE_SIZES	1
 #define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
 
-#include <asm/kvm_vgic.h>
+#include <kvm/kvm_vgic.h>
 
 struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 53c5ed8..110d6da 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
-kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+KVM := ../../../virt/kvm
+kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
-obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
+obj-$(CONFIG_KVM_ARM_VGIC) += $(addprefix $(KVM)/arm/, vgic.o)
+obj-$(CONFIG_KVM_ARM_TIMER) += $(addprefix $(KVM)/arm/, arch_timer.o)
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/include/kvm/kvm_arch_timer.h
similarity index 100%
rename from arch/arm/include/asm/kvm_arch_timer.h
rename to include/kvm/kvm_arch_timer.h
diff --git a/arch/arm/include/asm/kvm_vgic.h b/include/kvm/kvm_vgic.h
similarity index 100%
rename from arch/arm/include/asm/kvm_vgic.h
rename to include/kvm/kvm_vgic.h
diff --git a/arch/arm/kvm/arch_timer.c b/virt/kvm/arm/arch_timer.c
similarity index 99%
rename from arch/arm/kvm/arch_timer.c
rename to virt/kvm/arm/arch_timer.c
index 49a7516..0728904 100644
--- a/arch/arm/kvm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -25,8 +25,8 @@
 #include <clocksource/arm_arch_timer.h>
 #include <asm/arch_timer.h>
 
-#include <asm/kvm_vgic.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/kvm_vgic.h>
+#include <kvm/kvm_arch_timer.h>
 
 static struct timecounter *timecounter;
 static struct workqueue_struct *wqueue;
diff --git a/arch/arm/kvm/vgic.c b/virt/kvm/arm/vgic.c
similarity index 100%
rename from arch/arm/kvm/vgic.c
rename to virt/kvm/arm/vgic.c
-- 
1.8.2.1




From linus.walleij at linaro.org  Fri May  3 10:06:57 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 16:06:57 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <1500795.gEuGziRZET@wuerfel>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1883078.Smcmxe7hlB@wuerfel>
 <CACRpkdaNd0Ej-bM0MaXNdyHeWWH0CMi+mKKvtV5-891OFETtEA@mail.gmail.com>
 <1500795.gEuGziRZET@wuerfel>
Message-ID: <CACRpkdbDNoQSmFAyOMJRHSrnnuqpEfb0U9a7ZeaEztn1dAr_xA@mail.gmail.com>

On Fri, May 3, 2013 at 3:56 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 03 May 2013 15:33:17 Linus Walleij wrote:

>> I lean toward selecting AB3100 and REGULATOR_AB3100
>> for the U300 actually.
>
> Should we still allow building them on other platforms then?
> Right now, these depend on the platforms that actually use
> the hardware, but in other places, we just allow everything to
> be built that compiles without errors.

Not in my opinion but IIRC in 2008 or so some other
subsystem maintainer beat us up for not allowing it
to build on every other platform, and the rationale given
was that allowin this to build on e.g. x86_64 gives some
nice compile coverage.

I don't know which argument wins :-)

> Is it theoretically possible to use the AB in combination with
> another (non-ST-Ericsson) digital baseband?

Theoretically (it's just a bunch of regulators etc when all comes
around), but it won't happen since these components
are not sold separately.

Yours,
Linus Walleij


From lee.jones at linaro.org  Fri May  3 10:09:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 15:09:49 +0100
Subject: [PATCH] ARM: ux500: Remove DMA address look-up table
In-Reply-To: <CACRpkdaeEDHNLFt2z=7L=iFbxbSkbe25mYxCG3+MreLsZZ21SA@mail.gmail.com>
References: <1367484683-3479-1-git-send-email-lee.jones@linaro.org>
 <CACRpkdaeEDHNLFt2z=7L=iFbxbSkbe25mYxCG3+MreLsZZ21SA@mail.gmail.com>
Message-ID: <20130503140949.GN24153@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Thu, May 2, 2013 at 10:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > DMA addresses are now passed as part of the dmaengine API by invoking
> > dmaengine_slave_config(). So there's no requirement for the DMA40
> > driver to look them up in a table provided by platform data. This
> > method does not fit in well using Device Tree either.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This goes on top of some other changes right?
> 
> Right now the DMA series is confusing me a bit, there is
> these 6 patches:
> http://marc.info/?l=linux-arm-kernel&m=136698179306642&w=2
> 
> Then these 5 patches:
> http://marc.info/?l=linux-arm-kernel&m=136740201416293&w=2
> 
> And then this single patch.

Right. I can prepare one big branch if you like.

> Where shall I start, i.e. which patches go first?
> 
> Can they all be combined into one big series?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From tglx at linutronix.de  Fri May  3 10:09:46 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 3 May 2013 16:09:46 +0200 (CEST)
Subject: [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5183B7ED.7030800@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130503125527.GE18614@n2100.arm.linux.org.uk>
 <5183B7ED.7030800@gmail.com>
Message-ID: <alpine.LFD.2.02.1305031514230.2886@ionos>

On Fri, 3 May 2013, Sebastian Hesselbarth wrote:
> On 05/03/13 14:55, Russell King - ARM Linux wrote:
> > This is where it starts to get tricky, because I can't see how you'd
> > merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with
> > this.  Maybe you don't need to do anything here and just do all that
> > in orion_of_init() instead?  But then you seem to need to know the
> > virq range before hand, and I can't see how that's known.  Maybe Thomas
> > can provide some enlightenment about how the gc irqchip stuff works
> > with the irq domain stuff...
> 
> Exactly, and that is what I am looking into right now. But hell, I am
> not an expert in linux irq yet. Moreover, I am not even sure if it is
> okay to rely on irqdomain or at least irq_data->hw_irq at all.

Here is a solution to that problem.

1) It adds a mask field to irq_data so we dont have to compute the
   mask over and over

2) For compability with existing users it populates the mask with 
   1 << (d->irq - gc->irq_base)

3) It gives you the option to disable that mask setup or let it
   generate from d->hwirq

I'm still looking into a way how to proper support the generic chip /
linear domain mapping in the setup path. Will send you a draft patch
to play with later.

Thanks,

	tglx


Index: linux-2.6/include/linux/irq.h
===================================================================
--- linux-2.6.orig/include/linux/irq.h
+++ linux-2.6/include/linux/irq.h
@@ -119,6 +119,7 @@ struct irq_domain;
 
 /**
  * struct irq_data - per irq and irq chip data passed down to chip functions
+ * @mask:		precomputed bitmask for accessing the chip registers
  * @irq:		interrupt number
  * @hwirq:		hardware interrupt number, local to the interrupt domain
  * @node:		node index useful for balancing
@@ -138,6 +139,7 @@ struct irq_domain;
  * irq_data.
  */
 struct irq_data {
+	u32			mask;
 	unsigned int		irq;
 	unsigned long		hwirq;
 	unsigned int		node;
@@ -700,10 +702,14 @@ struct irq_chip_generic {
  * @IRQ_GC_INIT_NESTED_LOCK:	Set the lock class of the irqs to nested for
  *				irq chips which need to call irq_set_wake() on
  *				the parent irq. Usually GPIO implementations
+ * @IRQ_GC_NO_MASK:		Do not calculate irq_data->mask
+ * @IRQ_GC_MASK_FROM_HWIRQ:	Calculate irq_data->mask from the hwirq number
  */
 enum irq_gc_flags {
 	IRQ_GC_INIT_MASK_CACHE		= 1 << 0,
 	IRQ_GC_INIT_NESTED_LOCK		= 1 << 1,
+	IRQ_GC_NO_MASK			= 1 << 2,
+	IRQ_GC_MASK_FROM_HWIRQ		= 1 << 4,
 };
 
 /* Generic chip callback functions */
Index: linux-2.6/kernel/irq/generic-chip.c
===================================================================
--- linux-2.6.orig/kernel/irq/generic-chip.c
+++ linux-2.6/kernel/irq/generic-chip.c
@@ -39,7 +39,7 @@ void irq_gc_noop(struct irq_data *d)
 void irq_gc_mask_disable_reg(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
@@ -57,7 +57,7 @@ void irq_gc_mask_disable_reg(struct irq_
 void irq_gc_mask_set_bit(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	gc->mask_cache |= mask;
@@ -75,7 +75,7 @@ void irq_gc_mask_set_bit(struct irq_data
 void irq_gc_mask_clr_bit(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	gc->mask_cache &= ~mask;
@@ -93,7 +93,7 @@ void irq_gc_mask_clr_bit(struct irq_data
 void irq_gc_unmask_enable_reg(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
@@ -108,7 +108,7 @@ void irq_gc_unmask_enable_reg(struct irq
 void irq_gc_ack_set_bit(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
@@ -122,7 +122,7 @@ void irq_gc_ack_set_bit(struct irq_data 
 void irq_gc_ack_clr_bit(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = ~(1 << (d->irq - gc->irq_base));
+	u32 mask = ~d->mask;
 
 	irq_gc_lock(gc);
 	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
@@ -136,7 +136,7 @@ void irq_gc_ack_clr_bit(struct irq_data 
 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
@@ -151,7 +151,7 @@ void irq_gc_mask_disable_reg_and_ack(str
 void irq_gc_eoi(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
 	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
@@ -169,7 +169,7 @@ void irq_gc_eoi(struct irq_data *d)
 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	u32 mask = 1 << (d->irq - gc->irq_base);
+	u32 mask = d->mask;
 
 	if (!(mask & gc->wake_enabled))
 		return -EINVAL;
@@ -254,6 +254,15 @@ void irq_setup_generic_chip(struct irq_c
 		if (flags & IRQ_GC_INIT_NESTED_LOCK)
 			irq_set_lockdep_class(i, &irq_nested_lock_class);
 
+		if (!(flags & IRQ_GC_NO_MASK)) {
+			struct irq_data *d = irq_get_irq_data(i);
+			u32 mask;
+
+			if (flags & IRQ_GC_MASK_FROM_HWIRQ)
+				d->mask = 1 << (d->hwirq % 32);
+			else
+				d->mask = 1 << (i - gc->irq_base);
+		}
 		irq_set_chip_and_handler(i, &ct->chip, ct->handler);
 		irq_set_chip_data(i, gc);
 		irq_modify_status(i, clr, set);


From arnd at arndb.de  Fri May  3 10:20:29 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 16:20:29 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <CACRpkdbDNoQSmFAyOMJRHSrnnuqpEfb0U9a7ZeaEztn1dAr_xA@mail.gmail.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1500795.gEuGziRZET@wuerfel>
 <CACRpkdbDNoQSmFAyOMJRHSrnnuqpEfb0U9a7ZeaEztn1dAr_xA@mail.gmail.com>
Message-ID: <2812721.61fsxKBgRj@wuerfel>

On Friday 03 May 2013 16:06:57 Linus Walleij wrote:
> On Fri, May 3, 2013 at 3:56 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Friday 03 May 2013 15:33:17 Linus Walleij wrote:
> 
> >> I lean toward selecting AB3100 and REGULATOR_AB3100
> >> for the U300 actually.
> >
> > Should we still allow building them on other platforms then?
> > Right now, these depend on the platforms that actually use
> > the hardware, but in other places, we just allow everything to
> > be built that compiles without errors.
> 
> Not in my opinion but IIRC in 2008 or so some other
> subsystem maintainer beat us up for not allowing it
> to build on every other platform, and the rationale given
> was that allowin this to build on e.g. x86_64 gives some
> nice compile coverage.
> 
> I don't know which argument wins 

I know that a certain other Linus frequently complains when ARM specific
options show up on his x86 machine during "make oldconfig" ;-)

One idea I had is to create a global CONFIG_SOC option that would
hide all on-chip peripherals when building for a PC-like system.
On ARM, we would always select CONFIG_SOC, except for a few special
cases like ARCH_RPC, ARCH_FOOTBRIDGE and ARCH_SHARK.

> > Is it theoretically possible to use the AB in combination with
> > another (non-ST-Ericsson) digital baseband?
> 
> Theoretically (it's just a bunch of regulators etc when all comes
> around), but it won't happen since these components
> are not sold separately.

Right, I was specifically asking about the technical possibilities,
not what people are likely to do. 

	Arnd


From lee.jones at linaro.org  Fri May  3 10:21:46 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 May 2013 15:21:46 +0100
Subject: [PATCH 4/4 v2] staging: =?utf-8?Q?ste=5Frm?=
 =?utf-8?Q?i4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5Fe?=
 =?utf-8?Q?nable=28=29'?= warning
In-Reply-To: <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
Message-ID: <20130503142146.GO24153@gmail.com>

drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
        In function ?synaptics_rmi4_resume?:
drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
        warning: ignoring return value of ?regulator_enable?, declared
        with attribute warn_unused_result [-Wunused-result

Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: devel at driverdev.osuosl.org
Acked-by: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
index fe667dd..386362c 100644
--- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
+++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
@@ -1087,7 +1087,11 @@ static int synaptics_rmi4_resume(struct device *dev)
 	unsigned char intr_status;
 	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
 
-	regulator_enable(rmi4_data->regulator);
+	retval = regulator_enable(rmi4_data->regulator);
+	if (retval) {
+		dev_err(dev, "Regulator enable failed (%d)\n", retval);
+		return retval;
+	}
 
 	enable_irq(rmi4_data->i2c_client->irq);
 	rmi4_data->touch_stopped = false;


From linus.walleij at linaro.org  Fri May  3 10:22:41 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 16:22:41 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <517ED12B.8080502@wwwdotorg.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
Message-ID: <CACRpkdboCQmV_Aam3EDcSG6PRVnpEmGkC78m3h7rXT68V2a9Qg@mail.gmail.com>

On Mon, Apr 29, 2013 at 9:59 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:

> I would suggest simply dropping or reverting this patch; I had pointed out a
> long time ago that it was unlikely to be correct.
>
> My guess/suspicion is a recursive lock attempt during processing hogs during
> pinctrl device registration, or perhaps during dt->map conversion. Bryan,
> are you able to confirm this?

This was not the case at all, it was an mutex_unlock misspelled as
mutex_lock()... totally unrecursive dual locking :-)

I did test the patch quite extensively, albeit not on a system using
DT to populate the pinctrl tables so I missed this, mea culpa.

I really want to get rid of the big pinctrl lock and make this more
fine-granular, and that is why the patch is being pushed, bear
with me.

Yours,
Linus Walleij


From lee.jones at linaro.org  Fri May  3 10:31:46 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:46 +0100
Subject: [PATCH 00/63] dmaengine: Convert to correct API & Device Tree
 handling 
Message-ID: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>

As requested, this is the whole shebang. The first few patches are
the Device Tree adaptions. Then we move into some driver refactoring
basing on the fact that channel configuration should not be carried
out during channel allocation, but during a separate invocation of
dmaengine_slave_config(). Then we convert some of the clients over
to the new API. And finally, we provide all of the Device Tree
bindings to start requesting and configuration channels without the
use of platform data.

 Documentation/devicetree/bindings/dma/ste-dma40.txt |   66 ++++++++++++
 Documentation/devicetree/bindings/usb/ux500-usb.txt |   50 +++++++++
 arch/arm/boot/dts/dbx5x0.dtsi                       |   81 ++++++++++++--
 arch/arm/mach-ux500/board-mop500-audio.c            |   68 +++---------
 arch/arm/mach-ux500/board-mop500-sdi.c              |   56 +++-------
 arch/arm/mach-ux500/board-mop500.c                  |   85 +++++----------
 arch/arm/mach-ux500/board-mop500.h                  |    1 +
 arch/arm/mach-ux500/cpu-db8500.c                    |   74 ++++---------
 arch/arm/mach-ux500/devices-db8500.c                |  123 +--------------------
 arch/arm/mach-ux500/ste-dma40-db8500.h              |  193 ++++++++++++---------------------
 arch/arm/mach-ux500/usb.c                           |   47 +++-----
 drivers/crypto/ux500/cryp/cryp.h                    |    7 +-
 drivers/crypto/ux500/cryp/cryp_core.c               |   31 +++++-
 drivers/crypto/ux500/hash/hash_alg.h                |    5 +-
 drivers/crypto/ux500/hash/hash_core.c               |   24 ++++-
 drivers/dma/ste_dma40.c                             |  509 +++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------
 drivers/dma/ste_dma40_ll.c                          |  189 ++++++++++++++++----------------
 drivers/dma/ste_dma40_ll.h                          |    3 +-
 drivers/usb/musb/ux500.c                            |   61 ++++++++++-
 drivers/usb/musb/ux500_dma.c                        |   59 +++++-----
 include/linux/platform_data/dma-ste-dma40.h         |   41 ++-----
 include/linux/platform_data/usb-musb-ux500.h        |    5 +-
 sound/soc/ux500/ux500_pcm.c                         |   10 +-
 23 files changed, 903 insertions(+), 885 deletions(-)



From lee.jones at linaro.org  Fri May  3 10:31:47 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:47 +0100
Subject: [PATCH 01/63] ARM: ux500: Supply address location names for the DMA40
 DMA controller
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-2-git-send-email-lee.jones@linaro.org>

The DMA40 controller uses two sets of base addresses. In order to have
the resources setup by the of_platform framework so they are searchable
by name instead of index, we have to set names for them. The names have
to be the same as the ones used to fetch them back out of the resource
structure.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index aaa63d0..0f462b7 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -186,6 +186,7 @@
 			compatible = "stericsson,db8500-dma40",
 					"stericsson,dma40";
 			reg = <0x801C0000 0x1000 0x40010000 0x800>;
+			reg-names = "base", "lcpa";
 			interrupts = <0 25 0x4>;
 		};
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:48 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:48 +0100
Subject: [PATCH 02/63] ARM: ux500: Setup the DMA40 driver's DT node using the
 new DMA API
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-3-git-send-email-lee.jones@linaro.org>

The new DMA is now available, so let's use it to setup ST-Ericsson's
DMA40 driver when Device Tree is enabled.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 0f462b7..8a82b18 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -182,12 +182,13 @@
 			interrupts = <0 23 0x4>;
 		};
 
-		dma-controller at 801C0000 {
-			compatible = "stericsson,db8500-dma40",
-					"stericsson,dma40";
+		dma: dma-controller at 801C0000 {
+			compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 			reg = <0x801C0000 0x1000 0x40010000 0x800>;
 			reg-names = "base", "lcpa";
 			interrupts = <0 25 0x4>;
+
+			#dma-cells = <3>;
 		};
 
 		prcmu: prcmu at 80157000 {
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:49 +0100
Subject: [PATCH 03/63] ARM: ux500: Supply UART's DMA configuration via Device
 Tree
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-4-git-send-email-lee.jones@linaro.org>

When requesting a channel, a DMA client needs to pass some pieces of
information such as; request channel, device type, channel type and
direction etc. Normally we do this in the form of platform data, but
when DT is enabled we need to pass it using the driver's bindings
instead.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 8a82b18..d595e2c 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -568,18 +568,35 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80120000 0x1000>;
 			interrupts = <0 11 0x4>;
+
+			dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+			       <&dma 13 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
+
 		uart at 80121000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80121000 0x1000>;
 			interrupts = <0 19 0x4>;
+
+			dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
+			       <&dma 12 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
+
 		uart at 80007000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80007000 0x1000>;
 			interrupts = <0 26 0x4>;
+
+			dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
+			       <&dma 11 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:50 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:50 +0100
Subject: [PATCH 04/63] ARM: ux500: Supply MMC DMA configuration via Device Tree
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-5-git-send-email-lee.jones@linaro.org>

When requesting a channel, a DMA client needs to pass some pieces of
information such as; request channel, device type, channel type and
direction etc. Normally we do this in the form of platform data, but
when DT is enabled we need to pass it using the driver's bindings
instead.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index d595e2c..86b35a1 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -604,6 +604,11 @@
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80126000 0x1000>;
 			interrupts = <0 60 0x4>;
+
+			dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
+			       <&dma 29 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
 
@@ -611,6 +616,11 @@
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80118000 0x1000>;
 			interrupts = <0 50 0x4>;
+
+			dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
+			       <&dma 32 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
 
@@ -618,6 +628,11 @@
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80005000 0x1000>;
 			interrupts = <0 41 0x4>;
+
+			dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
+			       <&dma 28 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
 
@@ -632,6 +647,11 @@
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80114000 0x1000>;
 			interrupts = <0 99 0x4>;
+
+			dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
+			       <&dma 42 0 0x0>; /* Logical - MemToDev */
+			dma-names = "rx", "tx";
+
 			status = "disabled";
 		};
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:51 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:51 +0100
Subject: [PATCH 05/63] ARM: ux500: Populate the ux500-musb Device Tree entry
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-6-git-send-email-lee.jones@linaro.org>

This patch provides all the information to successfully probe() and
correctly configure the ux500-musb device driver for DMA.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 86b35a1..838214c 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -175,11 +175,40 @@
 			prcm = <&prcmu>;
 		};
 
-		usb at a03e0000 {
+		usb_per5 at a03e0000 {
 			compatible = "stericsson,db8500-musb",
 				"mentor,musb";
 			reg = <0xa03e0000 0x10000>;
 			interrupts = <0 23 0x4>;
+			interrupt-names = "mc";
+
+			dr_mode = "otg";
+
+			dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+			       <&dma 38 0 0x0>, /* Logical - MemToDev */
+			       <&dma 37 0 0x2>, /* Logical - DevToMem */
+			       <&dma 37 0 0x0>, /* Logical - MemToDev */
+			       <&dma 36 0 0x2>, /* Logical - DevToMem */
+			       <&dma 36 0 0x0>, /* Logical - MemToDev */
+			       <&dma 19 0 0x2>, /* Logical - DevToMem */
+			       <&dma 19 0 0x0>, /* Logical - MemToDev */
+			       <&dma 18 0 0x2>, /* Logical - DevToMem */
+			       <&dma 18 0 0x0>, /* Logical - MemToDev */
+			       <&dma 17 0 0x2>, /* Logical - DevToMem */
+			       <&dma 17 0 0x0>, /* Logical - MemToDev */
+			       <&dma 16 0 0x2>, /* Logical - DevToMem */
+			       <&dma 16 0 0x0>, /* Logical - MemToDev */
+			       <&dma 39 0 0x2>, /* Logical - DevToMem */
+			       <&dma 39 0 0x0>; /* Logical - MemToDev */
+
+			dma-names = "iep_1_9",  "oep_1_9",
+				    "iep_2_10", "oep_2_10",
+				    "iep_3_11", "oep_3_11",
+				    "iep_4_12", "oep_4_12",
+				    "iep_5_13", "oep_5_13",
+				    "iep_6_14", "oep_6_14",
+				    "iep_7_15", "oep_7_15",
+				    "iep_8",    "oep_8";
 		};
 
 		dma: dma-controller at 801C0000 {
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:52 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:52 +0100
Subject: [PATCH 06/63] ARM: ux500: Pass DMA memcpy channels though Device Tree
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-7-git-send-email-lee.jones@linaro.org>

It's now possible to configure memcpy channels dynamically with DT.
We're providing them despite the fact that they're the same as the
hard-coded channels, as they will be removed once the u8500 platform
goes DT-only.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 838214c..c693428 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -218,6 +218,7 @@
 			interrupts = <0 25 0x4>;
 
 			#dma-cells = <3>;
+			memcpy-channels = <56 57 58 59 60>;
 		};
 
 		prcmu: prcmu at 80157000 {
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:53 +0100
Subject: [PATCH 07/63] dmaengine: ste_dma40: Assign memcpy channels in the
 driver
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-8-git-send-email-lee.jones@linaro.org>

The channels reserved for memcpy are the same for all currently
supported platforms. With this in mind, we can ease the platform
data passing requirement by moving these assignments out from
platform code and place them directly into the driver.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/devices-db8500.c        |   12 ------------
 drivers/dma/ste_dma40.c                     |   12 +++++++-----
 include/linux/platform_data/dma-ste-dma40.h |    4 ----
 3 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index f3d9419..01cfb68 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -146,22 +146,10 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
 	[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
 };
 
-/* Reserved event lines for memcpy only */
-static int dma40_memcpy_event[] = {
-	DB8500_DMA_MEMCPY_TX_0,
-	DB8500_DMA_MEMCPY_TX_1,
-	DB8500_DMA_MEMCPY_TX_2,
-	DB8500_DMA_MEMCPY_TX_3,
-	DB8500_DMA_MEMCPY_TX_4,
-	DB8500_DMA_MEMCPY_TX_5,
-};
-
 static struct stedma40_platform_data dma40_plat_data = {
 	.dev_len = DB8500_DMA_NR_DEV,
 	.dev_rx = dma40_rx_map,
 	.dev_tx = dma40_tx_map,
-	.memcpy = dma40_memcpy_event,
-	.memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
 	.memcpy_conf_phy = &dma40_memcpy_conf_phy,
 	.memcpy_conf_log = &dma40_memcpy_conf_log,
 	.disabled_channels = {-1},
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 1734fee..12de79e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -55,6 +55,9 @@
 
 #define MAX(a, b) (((a) < (b)) ? (b) : (a))
 
+/* Reserved event lines for memcpy only. */
+static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
+
 /**
  * enum 40_command - The different commands and/or statuses.
  *
@@ -2014,8 +2017,7 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 	if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
 		d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
 		d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
-		d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
-			memcpy[d40c->chan.chan_id];
+		d40c->dma_cfg.dst_dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
 
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
@@ -2927,7 +2929,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 	}
 
 	d40_chan_init(base, &base->dma_memcpy, base->log_chans,
-		      base->num_log_chans, base->plat_data->memcpy_len);
+		      base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
 
 	dma_cap_zero(base->dma_memcpy.cap_mask);
 	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3215,7 +3217,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 			num_log_chans++;
 
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
-		       (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
+		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
 
 	if (base == NULL) {
@@ -3276,7 +3278,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	if (!base->lookup_phy_chans)
 		goto failure;
 
-	if (num_log_chans + plat_data->memcpy_len) {
+	if (num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) {
 		/*
 		 * The max number of logical channels are event lines for all
 		 * src devices and dst devices
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 4b78101..a808784 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -141,8 +141,6 @@ struct stedma40_chan_cfg {
  * @dev_len: length of dev_tx and dev_rx
  * @dev_tx: mapping between destination event line and io address
  * @dev_rx: mapping between source event line and io address
- * @memcpy: list of memcpy event lines
- * @memcpy_len: length of memcpy
  * @memcpy_conf_phy: default configuration of physical channel memcpy
  * @memcpy_conf_log: default configuration of logical channel memcpy
  * @disabled_channels: A vector, ending with -1, that marks physical channels
@@ -162,8 +160,6 @@ struct stedma40_platform_data {
 	u32				 dev_len;
 	const dma_addr_t		*dev_tx;
 	const dma_addr_t		*dev_rx;
-	int				*memcpy;
-	u32				 memcpy_len;
 	struct stedma40_chan_cfg	*memcpy_conf_phy;
 	struct stedma40_chan_cfg	*memcpy_conf_log;
 	int				 disabled_channels[STEDMA40_MAX_PHYS];
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:55 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:55 +0100
Subject: [PATCH 09/63] dmaengine: ste_dma40: Rectify incorrect configuration
 validation checking
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-10-git-send-email-lee.jones@linaro.org>

If we compare an event's group (dev_type / 16) with STEDMA40_DEV_DST_MEMORY
(-1), the only way we'd obtain a positive result is if we passed -16 as a
device type, which is unfeasible. Instead, it would be much more sane to
compare STEDMA40_DEV_DST_MEMORY against the raw dev_type in order to expect
the expected result.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 3b83dee..c79853f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1771,19 +1771,19 @@ static int d40_validate_conf(struct d40_chan *d40c,
 	}
 
 	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
-	    dst_event_group == STEDMA40_DEV_DST_MEMORY) {
+	    conf->dst_dev_type == STEDMA40_DEV_DST_MEMORY) {
 		chan_err(d40c, "Invalid dst\n");
 		res = -EINVAL;
 	}
 
 	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
-	    src_event_group == STEDMA40_DEV_SRC_MEMORY) {
+	    conf->src_dev_type == STEDMA40_DEV_SRC_MEMORY) {
 		chan_err(d40c, "Invalid src\n");
 		res = -EINVAL;
 	}
 
-	if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
-	    dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
+	if (conf->src_dev_type == STEDMA40_DEV_SRC_MEMORY &&
+	    conf->dst_dev_type == STEDMA40_DEV_DST_MEMORY && is_log) {
 		chan_err(d40c, "No event line\n");
 		res = -EINVAL;
 	}
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:57 +0100
Subject: [PATCH 11/63] ARM: ux500: Strip out duplicate USB DMA configuration
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-12-git-send-email-lee.jones@linaro.org>

For the moment at least, the TX and RX channels for DB8500 USB are
identical, so this patch generalises them into a single structure
and passes it twice. Once as the TX and again for the RX configuration.
We're keeping the infrastructure the same i.e. passing the TX and RX
separately in case they start to differ on latter incarnations of the
platform.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |   17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 2357191..d769459 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -166,18 +166,7 @@ static void __init db8500_add_gpios(struct device *parent)
 	dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 }
 
-static int usb_db8500_rx_dma_cfg[] = {
-	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
-	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
-	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
-	DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
-	DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
-	DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
-	DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
-	DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
-};
-
-static int usb_db8500_tx_dma_cfg[] = {
+static int usb_db8500_dma_cfg[] = {
 	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
 	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
 	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
@@ -219,7 +208,7 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 
 	db8500_add_rtc(parent);
 	db8500_add_gpios(parent);
-	db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+	db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 
 	for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
 		platform_devs[i]->dev.parent = parent;
@@ -238,7 +227,7 @@ static struct device * __init u8500_of_init_devices(void)
 {
 	struct device *parent = db8500_soc_device_init();
 
-	db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+	db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 
 	u8500_dma40_device.dev.parent = parent;
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:58 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:58 +0100
Subject: [PATCH 12/63] dmaengine: ste_dma40: Remove home-brew MAX() macro
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-13-git-send-email-lee.jones@linaro.org>

The current implementation of the DMA40's local MAX() macro evaluates
its arguments more times than is necessary and it not type checked.
This patch strips replaces it with a new, more efficient constant.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Reported-by: Harvey Harrison <harvey.harrison at gmail.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 2354474..9a04559 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -53,8 +53,6 @@
 #define D40_ALLOC_PHY		(1 << 30)
 #define D40_ALLOC_LOG_FREE	0
 
-#define MAX(a, b) (((a) < (b)) ? (b) : (a))
-
 /* Reserved event lines for memcpy only. */
 static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
 
@@ -202,6 +200,9 @@ static u32 d40_backup_regs_chan[] = {
 	D40_CHAN_REG_SDLNK,
 };
 
+#define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
+			     BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
+
 /**
  * struct d40_interrupt_lookup - lookup table for interrupt handler
  *
@@ -565,7 +566,7 @@ struct d40_base {
 	resource_size_t			  lcpa_size;
 	struct kmem_cache		 *desc_slab;
 	u32				  reg_val_backup[BACKUP_REGS_SZ];
-	u32				  reg_val_backup_v4[MAX(BACKUP_REGS_SZ_V4A, BACKUP_REGS_SZ_V4B)];
+	u32				  reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
 	u32				 *reg_val_backup_chan;
 	u16				  gcc_pwr_off_mask;
 	bool				  initialized;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:59 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:59 +0100
Subject: [PATCH 13/63] ARM: ux500: Remove unused 'data_width' attributes from
 SDI DMA configs
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-14-git-send-email-lee.jones@linaro.org>

DMA configuration data is now allocated in the MMCI driver, so these
are just ignored.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |   16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 5c28216..553ace6 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -65,16 +65,12 @@ struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type = DB8500_DMA_DEV29_SD_MM0,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV29_SD_MM0,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 
@@ -134,16 +130,12 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type = DB8500_DMA_DEV32_SD_MM1,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV32_SD_MM1,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 
@@ -169,16 +161,12 @@ struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type =  DB8500_DMA_DEV28_SD_MM2,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV28_SD_MM2,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 
@@ -205,16 +193,12 @@ struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type =  DB8500_DMA_DEV42_SD_MM4,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV42_SD_MM4,
-	.src_info.data_width = STEDMA40_WORD_WIDTH,
-	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:00 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:00 +0100
Subject: [PATCH 14/63] ARM: ux500: Remove unused 'data_width' attributes from
 SSP DMA configs
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-15-git-send-email-lee.jones@linaro.org>

DMA configuration data is now allocated in the SSP driver, so these
are just ignored.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a8b3ad9..35fd82f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -495,16 +495,12 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type = DB8500_DMA_DEV8_SSP0,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV8_SSP0,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 #endif
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:56 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:56 +0100
Subject: [PATCH 10/63] dmaengine: ste_dma40: Amalgamate DMA source and
 destination channel numbers
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-11-git-send-email-lee.jones@linaro.org>

Devices which utilise DMA use the same device numbers for transmitting
and receiving. In this patch we encode the source and destination
information into one single attribute. We can subsequently exploit the
direction attribute to see which of the transfer directions are being
described. This also lessens the burden on platform data.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-audio.c    |   18 +--
 arch/arm/mach-ux500/board-mop500-sdi.c      |   24 ++--
 arch/arm/mach-ux500/board-mop500.c          |   33 ++---
 arch/arm/mach-ux500/cpu-db8500.c            |   32 ++---
 arch/arm/mach-ux500/devices-db8500.c        |  120 ++++++++---------
 arch/arm/mach-ux500/ste-dma40-db8500.h      |  193 ++++++++++-----------------
 arch/arm/mach-ux500/usb.c                   |   10 +-
 drivers/dma/ste_dma40.c                     |   93 +++++--------
 drivers/dma/ste_dma40_ll.c                  |    4 +-
 include/linux/platform_data/dma-ste-dma40.h |    6 +-
 10 files changed, 207 insertions(+), 326 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 7209db7..f012cfa 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -24,8 +24,7 @@ static struct stedma40_chan_cfg msp0_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 
-	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 
 	.src_info.psize = STEDMA40_PSIZE_LOG_4,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -37,8 +36,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
 	.high_priority = true,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
+	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 
 	.src_info.psize = STEDMA40_PSIZE_LOG_4,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -56,8 +54,7 @@ static struct stedma40_chan_cfg msp1_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 
-	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV30_MSP3,
 
 	.src_info.psize = STEDMA40_PSIZE_LOG_4,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -69,8 +66,7 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
 	.high_priority = true,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
+	.dev_type = DB8500_DMA_DEV30_MSP1,
 
 	.src_info.psize = STEDMA40_PSIZE_LOG_4,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -88,8 +84,7 @@ static struct stedma40_chan_cfg msp2_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 
-	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV14_MSP2,
 
 	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
 	.src_info.psize = STEDMA40_PSIZE_LOG_1,
@@ -102,8 +97,7 @@ static struct stedma40_chan_cfg msp2_dma_tx = {
 	.high_priority = true,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
+	.dev_type = DB8500_DMA_DEV14_MSP2,
 
 	.src_info.psize = STEDMA40_PSIZE_LOG_4,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 7f2cb6c..5c28216 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -64,8 +64,7 @@ static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV29_SD_MM0,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -73,8 +72,7 @@ struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
+	.dev_type = DB8500_DMA_DEV29_SD_MM0,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -135,8 +133,7 @@ void mop500_sdi_tc35892_init(struct device *parent)
 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV32_SD_MM1,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -144,8 +141,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
+	.dev_type = DB8500_DMA_DEV32_SD_MM1,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -172,8 +168,7 @@ struct mmci_platform_data mop500_sdi1_data = {
 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type =  DB8500_DMA_DEV28_SD_MM2,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -181,8 +176,7 @@ struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
+	.dev_type = DB8500_DMA_DEV28_SD_MM2,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -210,8 +204,7 @@ struct mmci_platform_data mop500_sdi2_data = {
 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type =  DB8500_DMA_DEV42_SD_MM4,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
@@ -219,8 +212,7 @@ struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
+	.dev_type = DB8500_DMA_DEV42_SD_MM4,
 	.src_info.data_width = STEDMA40_WORD_WIDTH,
 	.dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 87d2d7b..a8b3ad9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -452,8 +452,7 @@ void mop500_snowball_ethernet_clock_enable(void)
 static struct cryp_platform_data u8500_cryp1_platform_data = {
 		.mem_to_engine = {
 				.dir = STEDMA40_MEM_TO_PERIPH,
-				.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-				.dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
+				.dev_type = DB8500_DMA_DEV48_CAC1,
 				.src_info.data_width = STEDMA40_WORD_WIDTH,
 				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
@@ -462,8 +461,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 		},
 		.engine_to_mem = {
 				.dir = STEDMA40_PERIPH_TO_MEM,
-				.src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
-				.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+				.dev_type = DB8500_DMA_DEV48_CAC1,
 				.src_info.data_width = STEDMA40_WORD_WIDTH,
 				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
@@ -474,8 +472,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
 		.dir = STEDMA40_MEM_TO_PERIPH,
-		.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-		.dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
+		.dev_type = DB8500_DMA_DEV50_HAC1_TX,
 		.src_info.data_width = STEDMA40_WORD_WIDTH,
 		.dst_info.data_width = STEDMA40_WORD_WIDTH,
 		.mode = STEDMA40_MODE_LOGICAL,
@@ -497,8 +494,7 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV8_SSP0,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -506,8 +502,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
+	.dev_type = DB8500_DMA_DEV8_SSP0,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -538,8 +533,7 @@ static void __init mop500_spi_init(struct device *parent)
 static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV13_UART0,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -547,8 +541,7 @@ static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
+	.dev_type = DB8500_DMA_DEV13_UART0,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -556,8 +549,7 @@ static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV12_UART1,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -565,8 +557,7 @@ static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
+	.dev_type = DB8500_DMA_DEV12_UART1,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -574,8 +565,7 @@ static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-	.src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dev_type = DB8500_DMA_DEV11_UART2,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
@@ -583,8 +573,7 @@ static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
+	.dev_type = DB8500_DMA_DEV11_UART2,
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f1a5818..2357191 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -167,25 +167,25 @@ static void __init db8500_add_gpios(struct device *parent)
 }
 
 static int usb_db8500_rx_dma_cfg[] = {
-	DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
-	DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
-	DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
-	DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
-	DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
-	DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
-	DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
-	DB8500_DMA_DEV39_USB_OTG_IEP_8
+	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
+	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
+	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
+	DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
+	DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
+	DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
+	DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
+	DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
 };
 
 static int usb_db8500_tx_dma_cfg[] = {
-	DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
-	DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
-	DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
-	DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
-	DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
-	DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
-	DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
-	DB8500_DMA_DEV39_USB_OTG_OEP_8
+	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
+	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
+	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
+	DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
+	DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
+	DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
+	DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
+	DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
 };
 
 static const char *db8500_read_soc_id(void)
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 8b20c91..28308f9 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -50,74 +50,74 @@ static struct resource dma40_resources[] = {
  */
 static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
 	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
+	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
+	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
+	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
+	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
+	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
+	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
+	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
+	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
 	/* PrimeCells - run-time configured */
-	[DB8500_DMA_DEV0_SPI0_TX] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
-	[DB8500_DMA_DEV8_SSP0_TX] = -1,
-	[DB8500_DMA_DEV9_SSP1_TX] = -1,
-	[DB8500_DMA_DEV11_UART2_TX] = -1,
-	[DB8500_DMA_DEV12_UART1_TX] = -1,
-	[DB8500_DMA_DEV13_UART0_TX] = -1,
-	[DB8500_DMA_DEV28_SD_MM2_TX] = -1,
-	[DB8500_DMA_DEV29_SD_MM0_TX] = -1,
-	[DB8500_DMA_DEV32_SD_MM1_TX] = -1,
-	[DB8500_DMA_DEV33_SPI2_TX] = -1,
-	[DB8500_DMA_DEV35_SPI1_TX] = -1,
-	[DB8500_DMA_DEV40_SPI3_TX] = -1,
-	[DB8500_DMA_DEV41_SD_MM3_TX] = -1,
-	[DB8500_DMA_DEV42_SD_MM4_TX] = -1,
-	[DB8500_DMA_DEV43_SD_MM5_TX] = -1,
-	[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
+	[DB8500_DMA_DEV0_SPI0] = -1,
+	[DB8500_DMA_DEV1_SD_MMC0] = -1,
+	[DB8500_DMA_DEV2_SD_MMC1] = -1,
+	[DB8500_DMA_DEV3_SD_MMC2] = -1,
+	[DB8500_DMA_DEV8_SSP0] = -1,
+	[DB8500_DMA_DEV9_SSP1] = -1,
+	[DB8500_DMA_DEV11_UART2] = -1,
+	[DB8500_DMA_DEV12_UART1] = -1,
+	[DB8500_DMA_DEV13_UART0] = -1,
+	[DB8500_DMA_DEV28_SD_MM2] = -1,
+	[DB8500_DMA_DEV29_SD_MM0] = -1,
+	[DB8500_DMA_DEV32_SD_MM1] = -1,
+	[DB8500_DMA_DEV33_SPI2] = -1,
+	[DB8500_DMA_DEV35_SPI1] = -1,
+	[DB8500_DMA_DEV40_SPI3] = -1,
+	[DB8500_DMA_DEV41_SD_MM3] = -1,
+	[DB8500_DMA_DEV42_SD_MM4] = -1,
+	[DB8500_DMA_DEV43_SD_MM5] = -1,
+	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
 	[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
 };
 
 /* Mapping between source event lines and physical device address */
 static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
 	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
+	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
+	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
+	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
+	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
+	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
+	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
+	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
+	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
 	/* PrimeCells */
-	[DB8500_DMA_DEV0_SPI0_RX] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
-	[DB8500_DMA_DEV8_SSP0_RX] = -1,
-	[DB8500_DMA_DEV9_SSP1_RX] = -1,
-	[DB8500_DMA_DEV11_UART2_RX] = -1,
-	[DB8500_DMA_DEV12_UART1_RX] = -1,
-	[DB8500_DMA_DEV13_UART0_RX] = -1,
-	[DB8500_DMA_DEV28_SD_MM2_RX] = -1,
-	[DB8500_DMA_DEV29_SD_MM0_RX] = -1,
-	[DB8500_DMA_DEV32_SD_MM1_RX] = -1,
-	[DB8500_DMA_DEV33_SPI2_RX] = -1,
-	[DB8500_DMA_DEV35_SPI1_RX] = -1,
-	[DB8500_DMA_DEV40_SPI3_RX] = -1,
-	[DB8500_DMA_DEV41_SD_MM3_RX] = -1,
-	[DB8500_DMA_DEV42_SD_MM4_RX] = -1,
-	[DB8500_DMA_DEV43_SD_MM5_RX] = -1,
-	[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
+	[DB8500_DMA_DEV0_SPI0] = -1,
+	[DB8500_DMA_DEV1_SD_MMC0] = -1,
+	[DB8500_DMA_DEV2_SD_MMC1] = -1,
+	[DB8500_DMA_DEV3_SD_MMC2] = -1,
+	[DB8500_DMA_DEV8_SSP0] = -1,
+	[DB8500_DMA_DEV9_SSP1] = -1,
+	[DB8500_DMA_DEV11_UART2] = -1,
+	[DB8500_DMA_DEV12_UART1] = -1,
+	[DB8500_DMA_DEV13_UART0] = -1,
+	[DB8500_DMA_DEV28_SD_MM2] = -1,
+	[DB8500_DMA_DEV29_SD_MM0] = -1,
+	[DB8500_DMA_DEV32_SD_MM1] = -1,
+	[DB8500_DMA_DEV33_SPI2] = -1,
+	[DB8500_DMA_DEV35_SPI1] = -1,
+	[DB8500_DMA_DEV40_SPI3] = -1,
+	[DB8500_DMA_DEV41_SD_MM3] = -1,
+	[DB8500_DMA_DEV42_SD_MM4] = -1,
+	[DB8500_DMA_DEV43_SD_MM5] = -1,
+	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
 };
 
 static struct stedma40_platform_data dma40_plat_data = {
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index a616419..0296ae5 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -12,133 +12,74 @@
 
 #define DB8500_DMA_NR_DEV 64
 
-enum dma_src_dev_type {
-	DB8500_DMA_DEV0_SPI0_RX = 0,
-	DB8500_DMA_DEV1_SD_MMC0_RX = 1,
-	DB8500_DMA_DEV2_SD_MMC1_RX = 2,
-	DB8500_DMA_DEV3_SD_MMC2_RX = 3,
-	DB8500_DMA_DEV4_I2C1_RX = 4,
-	DB8500_DMA_DEV5_I2C3_RX = 5,
-	DB8500_DMA_DEV6_I2C2_RX = 6,
-	DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
-	DB8500_DMA_DEV8_SSP0_RX = 8,
-	DB8500_DMA_DEV9_SSP1_RX = 9,
-	DB8500_DMA_DEV10_MCDE_RX = 10,
-	DB8500_DMA_DEV11_UART2_RX = 11,
-	DB8500_DMA_DEV12_UART1_RX = 12,
-	DB8500_DMA_DEV13_UART0_RX = 13,
-	DB8500_DMA_DEV14_MSP2_RX = 14,
-	DB8500_DMA_DEV15_I2C0_RX = 15,
-	DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
-	DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
-	DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
-	DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
-	DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
-	DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
-	DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
-	DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
-	DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
-	DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
-	DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
-	DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
-	DB8500_DMA_DEV28_SD_MM2_RX = 28,
-	DB8500_DMA_DEV29_SD_MM0_RX = 29,
-	DB8500_DMA_DEV30_MSP1_RX = 30,
+/*
+ * Unless otherwise specified, all channels numbers are used for
+ * TX & RX, and can be used for either source or destination
+ * channels.
+ */
+enum dma_dev_type {
+	DB8500_DMA_DEV0_SPI0 = 0,
+	DB8500_DMA_DEV1_SD_MMC0 = 1,
+	DB8500_DMA_DEV2_SD_MMC1 = 2,
+	DB8500_DMA_DEV3_SD_MMC2 = 3,
+	DB8500_DMA_DEV4_I2C1 = 4,
+	DB8500_DMA_DEV5_I2C3 = 5,
+	DB8500_DMA_DEV6_I2C2 = 6,
+	DB8500_DMA_DEV7_I2C4 = 7,			/* Only on V1 and later */
+	DB8500_DMA_DEV8_SSP0 = 8,
+	DB8500_DMA_DEV9_SSP1 = 9,
+	DB8500_DMA_DEV10_MCDE_RX = 10,			/* RX only */
+	DB8500_DMA_DEV11_UART2 = 11,
+	DB8500_DMA_DEV12_UART1 = 12,
+	DB8500_DMA_DEV13_UART0 = 13,
+	DB8500_DMA_DEV14_MSP2 = 14,
+	DB8500_DMA_DEV15_I2C0 = 15,
+	DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
+	DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
+	DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
+	DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
+	DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
+	DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
+	DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
+	DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
+	DB8500_DMA_DEV24_SXA0 = 24,
+	DB8500_DMA_DEV25_SXA1 = 25,
+	DB8500_DMA_DEV26_SXA2 = 26,
+	DB8500_DMA_DEV27_SXA3 = 27,
+	DB8500_DMA_DEV28_SD_MM2 = 28,
+	DB8500_DMA_DEV29_SD_MM0 = 29,
+	DB8500_DMA_DEV30_MSP1 = 30,
 	/* On DB8500v2, MSP3 RX replaces MSP1 RX */
-	DB8500_DMA_DEV30_MSP3_RX = 30,
-	DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
-	DB8500_DMA_DEV32_SD_MM1_RX = 32,
-	DB8500_DMA_DEV33_SPI2_RX = 33,
-	DB8500_DMA_DEV34_I2C3_RX2 = 34,
-	DB8500_DMA_DEV35_SPI1_RX = 35,
-	DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
-	DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
-	DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
-	DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
-	DB8500_DMA_DEV40_SPI3_RX = 40,
-	DB8500_DMA_DEV41_SD_MM3_RX = 41,
-	DB8500_DMA_DEV42_SD_MM4_RX = 42,
-	DB8500_DMA_DEV43_SD_MM5_RX = 43,
-	DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
-	DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
-	DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
-	DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
-	DB8500_DMA_DEV48_CAC1_RX = 48,
-	/* 49, 50 and 51 are not used */
-	DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
-	DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
-	DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
-	DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
-	/* 56, 57, 58, 59 and 60 are not used */
-	DB8500_DMA_DEV61_CAC0_RX = 61,
-	/* 62 and 63 are not used */
-};
-
-enum dma_dest_dev_type {
-	DB8500_DMA_DEV0_SPI0_TX = 0,
-	DB8500_DMA_DEV1_SD_MMC0_TX = 1,
-	DB8500_DMA_DEV2_SD_MMC1_TX = 2,
-	DB8500_DMA_DEV3_SD_MMC2_TX = 3,
-	DB8500_DMA_DEV4_I2C1_TX = 4,
-	DB8500_DMA_DEV5_I2C3_TX = 5,
-	DB8500_DMA_DEV6_I2C2_TX = 6,
-	DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
-	DB8500_DMA_DEV8_SSP0_TX = 8,
-	DB8500_DMA_DEV9_SSP1_TX = 9,
-	/* 10 is not used*/
-	DB8500_DMA_DEV11_UART2_TX = 11,
-	DB8500_DMA_DEV12_UART1_TX = 12,
-	DB8500_DMA_DEV13_UART0_TX = 13,
-	DB8500_DMA_DEV14_MSP2_TX = 14,
-	DB8500_DMA_DEV15_I2C0_TX = 15,
-	DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
-	DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
-	DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
-	DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
-	DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
-	DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
-	DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
-	DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
-	DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
-	DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
-	DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
-	DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
-	DB8500_DMA_DEV28_SD_MM2_TX = 28,
-	DB8500_DMA_DEV29_SD_MM0_TX = 29,
-	DB8500_DMA_DEV30_MSP1_TX = 30,
-	DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
-	DB8500_DMA_DEV32_SD_MM1_TX = 32,
-	DB8500_DMA_DEV33_SPI2_TX = 33,
-	DB8500_DMA_DEV34_I2C3_TX2 = 34,
-	DB8500_DMA_DEV35_SPI1_TX = 35,
-	DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
-	DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
-	DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
-	DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
-	DB8500_DMA_DEV40_SPI3_TX = 40,
-	DB8500_DMA_DEV41_SD_MM3_TX = 41,
-	DB8500_DMA_DEV42_SD_MM4_TX = 42,
-	DB8500_DMA_DEV43_SD_MM5_TX = 43,
-	DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
-	DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
-	DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
-	DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
-	DB8500_DMA_DEV48_CAC1_TX  = 48,
-	DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
-	DB8500_DMA_DEV50_HAC1_TX = 50,
-	DB8500_DMA_MEMCPY_TX_0 = 51,
-	DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
-	DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
-	DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
-	DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
-	DB8500_DMA_MEMCPY_TX_1 = 56,
-	DB8500_DMA_MEMCPY_TX_2 = 57,
-	DB8500_DMA_MEMCPY_TX_3 = 58,
-	DB8500_DMA_MEMCPY_TX_4 = 59,
-	DB8500_DMA_MEMCPY_TX_5 = 60,
-	DB8500_DMA_DEV61_CAC0_TX = 61,
-	DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
-	DB8500_DMA_DEV63_HAC0_TX = 63,
+	DB8500_DMA_DEV30_MSP3 = 30,
+	DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
+	DB8500_DMA_DEV32_SD_MM1 = 32,
+	DB8500_DMA_DEV33_SPI2 = 33,
+	DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
+	DB8500_DMA_DEV35_SPI1 = 35,
+	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
+	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
+	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
+	DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
+	DB8500_DMA_DEV40_SPI3 = 40,
+	DB8500_DMA_DEV41_SD_MM3 = 41,
+	DB8500_DMA_DEV42_SD_MM4 = 42,
+	DB8500_DMA_DEV43_SD_MM5 = 43,
+	DB8500_DMA_DEV44_SXA4 = 44,
+	DB8500_DMA_DEV45_SXA5 = 45,
+	DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
+	DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
+	DB8500_DMA_DEV48_CAC1 = 48,
+	DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,		/* TX only */
+	DB8500_DMA_DEV50_HAC1_TX = 50,			/* TX only */
+	DB8500_DMA_MEMCPY_TX_0 = 51,			/* TX only */
+	DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
+	DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
+	DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
+	DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
+	/* 56 -> 60 are channels reserved for memcpy only */
+	DB8500_DMA_DEV61_CAC0 = 61,
+	DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,		/* TX only */
+	DB8500_DMA_DEV63_HAC0_TX = 63,			/* TX only */
 };
 
 #endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 78ac65f..e0ea490 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,7 +15,6 @@
 #define MUSB_DMA40_RX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_PERIPH_TO_MEM, \
-		.dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
 		.src_info.data_width = STEDMA40_WORD_WIDTH, \
 		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
 		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
@@ -25,7 +24,6 @@
 #define MUSB_DMA40_TX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_MEM_TO_PERIPH, \
-		.src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
 		.src_info.data_width = STEDMA40_WORD_WIDTH, \
 		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
 		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
@@ -125,20 +123,20 @@ struct platform_device ux500_musb_device = {
 	.resource = usb_resources,
 };
 
-static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
+static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
 {
 	u32 idx;
 
 	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
-		musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
+		musb_dma_rx_ch[idx].dev_type = dev_type[idx];
 }
 
-static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
+static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
 {
 	u32 idx;
 
 	for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
-		musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
+		musb_dma_tx_ch[idx].dev_type = dev_type[idx];
 }
 
 void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index c79853f..2354474 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1288,21 +1288,17 @@ static void __d40_config_set_event(struct d40_chan *d40c,
 static void d40_config_set_event(struct d40_chan *d40c,
 				 enum d40_events event_type)
 {
+	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
+
 	/* Enable event line connected to device (or memcpy) */
 	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
-		u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
-
+	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
 		__d40_config_set_event(d40c, event_type, event,
 				       D40_CHAN_REG_SSLNK);
-	}
-
-	if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
-		u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 
+	if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM)
 		__d40_config_set_event(d40c, event_type, event,
 				       D40_CHAN_REG_SDLNK);
-	}
 }
 
 static u32 d40_chan_has_events(struct d40_chan *d40c)
@@ -1744,8 +1740,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
 			     struct stedma40_chan_cfg *conf)
 {
 	int res = 0;
-	u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
-	u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
 	bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
 
 	if (!conf->dir) {
@@ -1753,44 +1747,26 @@ static int d40_validate_conf(struct d40_chan *d40c,
 		res = -EINVAL;
 	}
 
-	if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
-	    d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-
-		chan_err(d40c, "Invalid TX channel address (%d)\n",
-			 conf->dst_dev_type);
-		res = -EINVAL;
-	}
-
-	if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
-	    d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid RX channel address (%d)\n",
-			conf->src_dev_type);
+	if ((is_log && conf->dev_type > d40c->base->num_log_chans)  ||
+	    (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
+	    (conf->dev_type < 0)) {
+		chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
 		res = -EINVAL;
 	}
 
 	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
-	    conf->dst_dev_type == STEDMA40_DEV_DST_MEMORY) {
-		chan_err(d40c, "Invalid dst\n");
+	    d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
+	    d40c->runtime_addr == 0) {
+		chan_err(d40c, "Invalid TX channel address (%d)\n",
+			 conf->dev_type);
 		res = -EINVAL;
 	}
 
 	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
-	    conf->src_dev_type == STEDMA40_DEV_SRC_MEMORY) {
-		chan_err(d40c, "Invalid src\n");
-		res = -EINVAL;
-	}
-
-	if (conf->src_dev_type == STEDMA40_DEV_SRC_MEMORY &&
-	    conf->dst_dev_type == STEDMA40_DEV_DST_MEMORY && is_log) {
-		chan_err(d40c, "No event line\n");
-		res = -EINVAL;
-	}
-
-	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
-	    (src_event_group != dst_event_group)) {
-		chan_err(d40c, "Invalid event group\n");
+	    d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
+	    d40c->runtime_addr == 0) {
+		chan_err(d40c, "Invalid RX channel address (%d)\n",
+			 conf->dev_type);
 		res = -EINVAL;
 	}
 
@@ -1911,7 +1887,7 @@ out:
 
 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
 {
-	int dev_type;
+	int dev_type = d40c->dma_cfg.dev_type;
 	int event_group;
 	int event_line;
 	struct d40_phy_res *phys;
@@ -1926,13 +1902,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
 	num_phy_chans = d40c->base->num_phy_chans;
 
 	if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
-		dev_type = d40c->dma_cfg.src_dev_type;
 		log_num = 2 * dev_type;
 		is_src = true;
 	} else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
 		   d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
 		/* dst event lines are used for logical memcpy */
-		dev_type = d40c->dma_cfg.dst_dev_type;
 		log_num = 2 * dev_type + 1;
 		is_src = false;
 	} else
@@ -2044,8 +2018,7 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 
 	if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
 		d40c->dma_cfg = dma40_memcpy_conf_log;
-		d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
-		d40c->dma_cfg.dst_dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
+		d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
 
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
@@ -2062,7 +2035,7 @@ static int d40_free_dma(struct d40_chan *d40c)
 {
 
 	int res = 0;
-	u32 event;
+	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
 	struct d40_phy_res *phy = d40c->phy_chan;
 	bool is_src;
 
@@ -2081,13 +2054,11 @@ static int d40_free_dma(struct d40_chan *d40c)
 	}
 
 	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
-		event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
+	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
 		is_src = false;
-	} else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
-		event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
+	else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
 		is_src = true;
-	} else {
+	else {
 		chan_err(d40c, "Unknown direction\n");
 		return -EINVAL;
 	}
@@ -2128,7 +2099,7 @@ static bool d40_is_paused(struct d40_chan *d40c)
 	unsigned long flags;
 	void __iomem *active_reg;
 	u32 status;
-	u32 event;
+	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
 
 	spin_lock_irqsave(&d40c->lock, flags);
 
@@ -2149,10 +2120,8 @@ static bool d40_is_paused(struct d40_chan *d40c)
 
 	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
 	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
-		event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 		status = readl(chanbase + D40_CHAN_REG_SDLNK);
 	} else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
-		event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 		status = readl(chanbase + D40_CHAN_REG_SSLNK);
 	} else {
 		chan_err(d40c, "Unknown direction\n");
@@ -2294,9 +2263,9 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
 		return chan->runtime_addr;
 
 	if (direction == DMA_DEV_TO_MEM)
-		addr = plat->dev_rx[cfg->src_dev_type];
+		addr = plat->dev_rx[cfg->dev_type];
 	else if (direction == DMA_MEM_TO_DEV)
-		addr = plat->dev_tx[cfg->dst_dev_type];
+		addr = plat->dev_tx[cfg->dev_type];
 
 	return addr;
 }
@@ -2427,11 +2396,11 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
 
 	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
 	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
-		__d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
+		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
 
 	if ((d40c->dma_cfg.dir ==  STEDMA40_MEM_TO_PERIPH) ||
 	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
-		__d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
+		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
 }
 
 /* DMA ENGINE functions */
@@ -2475,10 +2444,10 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 
 		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
 			d40c->lcpa = d40c->base->lcpa_base +
-				d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
+				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
 		else
 			d40c->lcpa = d40c->base->lcpa_base +
-				d40c->dma_cfg.dst_dev_type *
+				d40c->dma_cfg.dev_type *
 				D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
 	}
 
@@ -2741,7 +2710,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 
 	if (config->direction == DMA_DEV_TO_MEM) {
 		dma_addr_t dev_addr_rx =
-			d40c->base->plat_data->dev_rx[cfg->src_dev_type];
+			d40c->base->plat_data->dev_rx[cfg->dev_type];
 
 		config_addr = config->src_addr;
 		if (dev_addr_rx)
@@ -2764,7 +2733,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 
 	} else if (config->direction == DMA_MEM_TO_DEV) {
 		dma_addr_t dev_addr_tx =
-			d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
+			d40c->base->plat_data->dev_tx[cfg->dev_type];
 
 		config_addr = config->dst_addr;
 		if (dev_addr_tx)
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 7180e0d..5eb6c10 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -63,7 +63,7 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
 			/* Set master port to 1 */
 			src |= 1 << D40_SREG_CFG_MST_POS;
-			src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
+			src |= D40_TYPE_TO_EVENT(cfg->dev_type);
 
 			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
 				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
@@ -74,7 +74,7 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
 			/* Set master port to 1 */
 			dst |= 1 << D40_SREG_CFG_MST_POS;
-			dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
+			dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
 
 			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
 				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 869c571..9e42a67 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -109,8 +109,7 @@ struct stedma40_half_channel_info {
  * version 3+, i.e DB8500v2+
  * @mode: channel mode: physical, logical, or operation
  * @mode_opt: options for the chosen channel mode
- * @src_dev_type: Src device type
- * @dst_dev_type: Dst device type
+ * @dev_type: src/dst device type (driver uses dir to figure out which)
  * @src_info: Parameters for dst half channel
  * @dst_info: Parameters for dst half channel
  * @use_fixed_channel: if true, use physical channel specified by phy_channel
@@ -126,8 +125,7 @@ struct stedma40_chan_cfg {
 	bool					 realtime;
 	enum stedma40_mode			 mode;
 	enum stedma40_mode_opt			 mode_opt;
-	int					 src_dev_type;
-	int					 dst_dev_type;
+	int					 dev_type;
 	struct stedma40_half_channel_info	 src_info;
 	struct stedma40_half_channel_info	 dst_info;
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:01 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:01 +0100
Subject: [PATCH 15/63] ARM: ux500: Remove unused 'data_width' attributes from
 UART DMA configs
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-16-git-send-email-lee.jones@linaro.org>

DMA configuration data is now allocated in the UART driver, so these
are just ignored.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |   12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 35fd82f..883dc66 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -530,48 +530,36 @@ static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type = DB8500_DMA_DEV13_UART0,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV13_UART0,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type = DB8500_DMA_DEV12_UART1,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV12_UART1,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_PERIPH_TO_MEM,
 	.dev_type = DB8500_DMA_DEV11_UART2,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = STEDMA40_MEM_TO_PERIPH,
 	.dev_type = DB8500_DMA_DEV11_UART2,
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 #endif
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:02 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:02 +0100
Subject: [PATCH 16/63] ARM: ux500: Remove superfluous 'psize' attribute from
 Audio platform data
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-17-git-send-email-lee.jones@linaro.org>

'psize' is used to calculate the maximum DMA burst size. However it
is only taken into consideration when editing the DMA channel's
configuration. The Audio DMA platform data is only used to allocate
a channel, not configure it. That will be done at a later date within
the MSP driver.

We're also removing comments which are no longer required, as
'data_width' is no longer set in any device's platform data period.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-audio.c |   38 ------------------------------
 1 file changed, 38 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index f012cfa..972bec0 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -23,25 +23,13 @@
 static struct stedma40_chan_cfg msp0_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-
 	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
 };
 
 static struct stedma40_chan_cfg msp0_dma_tx = {
 	.high_priority = true,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-
 	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
 };
 
 struct msp_i2s_platform_data msp0_platform_data = {
@@ -53,25 +41,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
 static struct stedma40_chan_cfg msp1_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-
 	.dev_type = DB8500_DMA_DEV30_MSP3,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
 };
 
 static struct stedma40_chan_cfg msp1_dma_tx = {
 	.high_priority = true,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-
 	.dev_type = DB8500_DMA_DEV30_MSP1,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
 };
 
 struct msp_i2s_platform_data msp1_platform_data = {
@@ -83,29 +59,15 @@ struct msp_i2s_platform_data msp1_platform_data = {
 static struct stedma40_chan_cfg msp2_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
-
 	.dev_type = DB8500_DMA_DEV14_MSP2,
-
-	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
-	.src_info.psize = STEDMA40_PSIZE_LOG_1,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
-
-	/* data_width is set during configuration */
 };
 
 static struct stedma40_chan_cfg msp2_dma_tx = {
 	.high_priority = true,
 	.dir = STEDMA40_MEM_TO_PERIPH,
-
 	.dev_type = DB8500_DMA_DEV14_MSP2,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
 	.use_fixed_channel = true,
 	.phy_channel = 1,
-
-	/* data_width is set during configuration */
 };
 
 static struct platform_device *db8500_add_msp_i2s(struct device *parent,
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:04 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:04 +0100
Subject: [PATCH 18/63] dmaengine: ste_dma40: Remove 'always true' checking
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-19-git-send-email-lee.jones@linaro.org>

Before allocating memory for logical channels, the current driver
checks to see if there are any. Well as the dma40_memcpy_channels[]
array is always populated, the check is always true. Best to
remove the check.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 0a5f3705..091d6a5 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3272,17 +3272,11 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	if (!base->lookup_phy_chans)
 		goto failure;
 
-	if (num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) {
-		/*
-		 * The max number of logical channels are event lines for all
-		 * src devices and dst devices
-		 */
-		base->lookup_log_chans = kzalloc(num_log_chans *
-						 sizeof(struct d40_chan *),
-						 GFP_KERNEL);
-		if (!base->lookup_log_chans)
-			goto failure;
-	}
+	base->lookup_log_chans = kzalloc(num_log_chans *
+					 sizeof(struct d40_chan *),
+					 GFP_KERNEL);
+	if (!base->lookup_log_chans)
+		goto failure;
 
 	base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
 					    sizeof(d40_backup_regs_chan),
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:03 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:03 +0100
Subject: [PATCH 17/63] dmaengine: ste_dma40: Calculate number of logical
 channels from physical ones
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-18-git-send-email-lee.jones@linaro.org>

This change will cost ~25KB of memory, but it's worth the trade-off,
as it removes a great deal of overhead. It means that instead of only
allocating memory for the logical channels in use, it does so for all
available ones, which is 32 per physical channel. However, this now
means we can remove some platform data and we don't have to worry
about adding vendor specific variables to Device Tree.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/devices-db8500.c        |    1 -
 drivers/dma/ste_dma40.c                     |   16 ++++++----------
 include/linux/platform_data/dma-ste-dma40.h |    2 --
 3 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 28308f9..99bc532 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -121,7 +121,6 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
 };
 
 static struct stedma40_platform_data dma40_plat_data = {
-	.dev_len = DB8500_DMA_NR_DEV,
 	.dev_rx = dma40_rx_map,
 	.dev_tx = dma40_tx_map,
 	.disabled_channels = {-1},
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 9a04559..0a5f3705 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -45,6 +45,9 @@
 #define D40_LCLA_LINK_PER_EVENT_GRP 128
 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
 
+/* Max number of logical channels per physical channel */
+#define D40_MAX_LOG_CHAN_PER_PHY 32
+
 /* Attempts before giving up to trying to get pages that are aligned */
 #define MAX_LCLA_ALLOC_ATTEMPTS 256
 
@@ -3196,6 +3199,8 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	else
 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
 
+	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
+
 	dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
 		 rev, res->start, num_phy_chans);
 
@@ -3205,15 +3210,6 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		goto failure;
 	}
 
-	/* Count the number of logical channels in use */
-	for (i = 0; i < plat_data->dev_len; i++)
-		if (plat_data->dev_rx[i] != 0)
-			num_log_chans++;
-
-	for (i = 0; i < plat_data->dev_len; i++)
-		if (plat_data->dev_tx[i] != 0)
-			num_log_chans++;
-
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
 		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
@@ -3281,7 +3277,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		 * The max number of logical channels are event lines for all
 		 * src devices and dst devices
 		 */
-		base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
+		base->lookup_log_chans = kzalloc(num_log_chans *
 						 sizeof(struct d40_chan *),
 						 GFP_KERNEL);
 		if (!base->lookup_log_chans)
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 9e42a67..c54af61 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -136,7 +136,6 @@ struct stedma40_chan_cfg {
 /**
  * struct stedma40_platform_data - Configuration struct for the dma device.
  *
- * @dev_len: length of dev_tx and dev_rx
  * @dev_tx: mapping between destination event line and io address
  * @dev_rx: mapping between source event line and io address
  * @disabled_channels: A vector, ending with -1, that marks physical channels
@@ -153,7 +152,6 @@ struct stedma40_chan_cfg {
  * for 'multiple of 4' channels, like 8.
  */
 struct stedma40_platform_data {
-	u32				 dev_len;
 	const dma_addr_t		*dev_tx;
 	const dma_addr_t		*dev_rx;
 	int				 disabled_channels[STEDMA40_MAX_PHYS];
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:05 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:05 +0100
Subject: [PATCH 19/63] dmaengine: ste_dma40: Separate Logical Global Interrupt
 Mask (GIM) unmasking
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-20-git-send-email-lee.jones@linaro.org>

During the initial setup of a logical channel, it is necessary to unmask
the GIM in order to receive generated terminal count and error interrupts.
We're separating out this required code so it will be possible to move
the remaining code in d40_phy_cfg(), which is mostly runtime configuration
into the runtime_config() routine.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c    |    4 ++++
 drivers/dma/ste_dma40_ll.c |    5 -----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 091d6a5..6df1b01 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2453,6 +2453,10 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 			d40c->lcpa = d40c->base->lcpa_base +
 				d40c->dma_cfg.dev_type *
 				D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
+
+		/* Unmask the Global Interrupt Mask. */
+		d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
+		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
 	}
 
 	dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 5eb6c10..435a223 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -107,11 +107,6 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 			src |= 1 << D40_SREG_CFG_PRI_POS;
 			dst |= 1 << D40_SREG_CFG_PRI_POS;
 		}
-
-	} else {
-		/* Logical channel */
-		dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
-		src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
 	}
 
 	if (cfg->src_info.big_endian)
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:06 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:06 +0100
Subject: [PATCH 20/63] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-21-git-send-email-lee.jones@linaro.org>

All configuration left in d40_phy_cfg() is runtime configurable and
there is already a call into it from d40_runtime_config(), so let's
rely on that.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c    |   14 +++---
 drivers/dma/ste_dma40_ll.c |  101 +++++++++++++++++++++-----------------------
 drivers/dma/ste_dma40_ll.h |    3 +-
 3 files changed, 58 insertions(+), 60 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 6df1b01..8bff463 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2027,6 +2027,14 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
 		d40c->dma_cfg = dma40_memcpy_conf_phy;
+
+		/* Generate interrrupt at end of transfer or relink. */
+		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
+
+		/* Generate interrupt on error. */
+		d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
+		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
+
 	} else {
 		chan_err(d40c, "No memcpy\n");
 		return -EINVAL;
@@ -2436,9 +2444,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	pm_runtime_get_sync(d40c->base->dev);
-	/* Fill in basic CFG register values */
-	d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
-		    &d40c->dst_def_cfg, chan_is_logical(d40c));
 
 	d40_set_prio_realtime(d40c);
 
@@ -2802,8 +2807,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	if (chan_is_logical(d40c))
 		d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
 	else
-		d40_phy_cfg(cfg, &d40c->src_def_cfg,
-			    &d40c->dst_def_cfg, false);
+		d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
 
 	/* These settings will take precedence later */
 	d40c->runtime_addr = config_addr;
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 435a223..ab5a2a7 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -50,63 +50,58 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 
 }
 
-/* Sets up SRC and DST CFG register for both logical and physical channels */
-void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
-		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
+void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 {
 	u32 src = 0;
 	u32 dst = 0;
 
-	if (!is_log) {
-		/* Physical channel */
-		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
-		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
-			/* Set master port to 1 */
-			src |= 1 << D40_SREG_CFG_MST_POS;
-			src |= D40_TYPE_TO_EVENT(cfg->dev_type);
-
-			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
-			else
-				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
-		}
-		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
-		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
-			/* Set master port to 1 */
-			dst |= 1 << D40_SREG_CFG_MST_POS;
-			dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
-
-			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
-			else
-				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
-		}
-		/* Interrupt on end of transfer for destination */
-		dst |= 1 << D40_SREG_CFG_TIM_POS;
-
-		/* Generate interrupt on error */
-		src |= 1 << D40_SREG_CFG_EIM_POS;
-		dst |= 1 << D40_SREG_CFG_EIM_POS;
-
-		/* PSIZE */
-		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
-			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
-			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
-		}
-		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
-			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
-			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
-		}
-
-		/* Element size */
-		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
-		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
-
-		/* Set the priority bit to high for the physical channel */
-		if (cfg->high_priority) {
-			src |= 1 << D40_SREG_CFG_PRI_POS;
-			dst |= 1 << D40_SREG_CFG_PRI_POS;
-		}
+	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
+	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+		/* Set master port to 1 */
+		src |= 1 << D40_SREG_CFG_MST_POS;
+		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
+
+		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
+			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
+		else
+			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
+	}
+	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
+	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+		/* Set master port to 1 */
+		dst |= 1 << D40_SREG_CFG_MST_POS;
+		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
+
+		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
+			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
+		else
+			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
+	}
+	/* Interrupt on end of transfer for destination */
+	dst |= 1 << D40_SREG_CFG_TIM_POS;
+
+	/* Generate interrupt on error */
+	src |= 1 << D40_SREG_CFG_EIM_POS;
+	dst |= 1 << D40_SREG_CFG_EIM_POS;
+
+	/* PSIZE */
+	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
+		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
+	}
+	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
+		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
+	}
+
+	/* Element size */
+	src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
+	dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
+
+	/* Set the priority bit to high for the physical channel */
+	if (cfg->high_priority) {
+		src |= 1 << D40_SREG_CFG_PRI_POS;
+		dst |= 1 << D40_SREG_CFG_PRI_POS;
 	}
 
 	if (cfg->src_info.big_endian)
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index fdde8ef..1b47312 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -432,8 +432,7 @@ enum d40_lli_flags {
 
 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 		 u32 *src_cfg,
-		 u32 *dst_cfg,
-		 bool is_log);
+		 u32 *dst_cfg);
 
 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 		 u32 *lcsp1,
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:07 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:07 +0100
Subject: [PATCH 21/63] dmaengine: ste_dma40: Don't configure runtime
 configurable setup during allocate
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-22-git-send-email-lee.jones@linaro.org>

Using the dmaengine API, allocating and configuring a channel are two
separate actions. Here we're removing logical channel configuration from
the channel allocating routines.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 8bff463..34e0fb0 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2024,6 +2024,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 		d40c->dma_cfg = dma40_memcpy_conf_log;
 		d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
 
+		d40_log_cfg(&d40c->dma_cfg,
+			    &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
+
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
 		d40c->dma_cfg = dma40_memcpy_conf_phy;
@@ -2448,9 +2451,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	d40_set_prio_realtime(d40c);
 
 	if (chan_is_logical(d40c)) {
-		d40_log_cfg(&d40c->dma_cfg,
-			    &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
-
 		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
 			d40c->lcpa = d40c->base->lcpa_base +
 				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:08 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:08 +0100
Subject: [PATCH 22/63] dmaengine: ste_dma40: Move rev error-check up to
 revision acquisition
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-23-git-send-email-lee.jones@linaro.org>

At the moment we fetch the hardware revision, then do some stuff, then
check whether the revision is correct and return in error if it's not.
Well we may as well check it as soon as we know what it is, so let's
move the check right up underneath where we acquire the version.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 34e0fb0..e5f0e3c 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3198,6 +3198,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	 * DB8540v1 has revision 4
 	 */
 	rev = AMBA_REV_BITS(pid);
+	if (rev < 2) {
+		d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
+		goto failure;
+	}
 
 	plat_data = pdev->dev.platform_data;
 
@@ -3212,12 +3216,6 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
 		 rev, res->start, num_phy_chans);
 
-	if (rev < 2) {
-		d40_err(&pdev->dev, "hardware revision: %d is not supported",
-			rev);
-		goto failure;
-	}
-
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
 		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:09 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:09 +0100
Subject: [PATCH 23/63] dmaengine: ste_dma40: Also report the number of logical
 channels
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-24-git-send-email-lee.jones@linaro.org>

Now we know the total of physical and logical channels, we may as
well report them within the information log.

Before:
dma40 dma40.0: hardware revision: 3 @ 0x801c0000 with 8 physical channels

After:
<as above ...> and 256 logical channels

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index e5f0e3c..6d81f44 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3213,8 +3213,9 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 
 	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
 
-	dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
-		 rev, res->start, num_phy_chans);
+	dev_info(&pdev->dev,
+		 "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n",
+		 rev, res->start, num_phy_chans, num_log_chans);
 
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
 		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:11 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:11 +0100
Subject: [PATCH 25/63] dmaengine: ste_dma40: Allow driver to be probe()able
 when DT is enabled
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-26-git-send-email-lee.jones@linaro.org>

When booting using Device Tree, devices aren't registered in the normal
way. Instead, they need to be provided with a compatible string which is
held in an OF Match Table for comparison during start-up. Here we provide
the compatible string and prepare the driver to not receive a platform
data pointer.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   46 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index ba50561..d7c2397 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -17,6 +17,7 @@
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
 #include <linux/err.h>
+#include <linux/of.h>
 #include <linux/amba/bus.h>
 #include <linux/regulator/consumer.h>
 #include <linux/platform_data/dma-ste-dma40.h>
@@ -3465,17 +3466,52 @@ failure:
 	return ret;
 }
 
+static int __init d40_of_probe(struct platform_device *pdev,
+			       struct device_node *np)
+{
+	struct stedma40_platform_data *pdata;
+ 
+	/*
+	 * FIXME: Fill in this routine as more support is added.
+	 * First platform enabled (u8500) doens't need any extra
+	 * properties to run, so this is fairly sparce currently.
+	 */
+
+	pdata = devm_kzalloc(&pdev->dev,
+			     sizeof(struct stedma40_platform_data),
+			     GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdev->dev.platform_data = pdata;
+
+	return 0;
+}
+
 static int __init d40_probe(struct platform_device *pdev)
 {
+	struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
+	struct device_node *np = pdev->dev.of_node;
 	int err;
 	int ret = -ENOENT;
-	struct d40_base *base;
+	struct d40_base *base = NULL;
 	struct resource *res = NULL;
 	int num_reserved_chans;
 	u32 val;
 
-	base = d40_hw_detect_init(pdev);
+	if (!plat_data) {
+		if (np) {
+			if(d40_of_probe(pdev, np)) {
+				ret = -ENOMEM;
+				goto failure;
+			}
+		} else {
+			d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
+			goto failure;
+		}
+	}
 
+	base = d40_hw_detect_init(pdev);
 	if (!base)
 		goto failure;
 
@@ -3649,11 +3685,17 @@ failure:
 	return ret;
 }
 
+static const struct of_device_id d40_match[] = {
+        { .compatible = "stericsson,dma40", },
+        {}
+};
+
 static struct platform_driver d40_driver = {
 	.driver = {
 		.owner = THIS_MODULE,
 		.name  = D40_NAME,
 		.pm = DMA40_PM_OPS,
+		.of_match_table = d40_match,
 	},
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:10 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:10 +0100
Subject: [PATCH 24/63] dmaengine: ste_dma40: Allocate plat_data on declaration
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-25-git-send-email-lee.jones@linaro.org>

It's the way that most other drivers do it.

Very trivial clean-up which reduces line count and simplifies code.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 6d81f44..ba50561 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3132,7 +3132,7 @@ static int __init d40_phy_res_init(struct d40_base *base)
 
 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 {
-	struct stedma40_platform_data *plat_data;
+	struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
 	struct clk *clk = NULL;
 	void __iomem *virtbase = NULL;
 	struct resource *res = NULL;
@@ -3203,8 +3203,6 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		goto failure;
 	}
 
-	plat_data = pdev->dev.platform_data;
-
 	/* The number of physical channels on this HW */
 	if (plat_data->num_of_phy_chans)
 		num_phy_chans = plat_data->num_of_phy_chans;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:13 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:13 +0100
Subject: [PATCH 27/63] ARM: ux500: Pass remnant platform data though to DMA40
 driver
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-28-git-send-email-lee.jones@linaro.org>

Ironically, in order to remove lots of the auxdata assignments, we have
to add just one more. A lot of them require DMA information to be passed
into clients for DMA channel allocation, but we now have this capability
in Device Tree. However, the DMA40 driver still relies on a reverse table
look-up to obtain DMA addresses. Until all of the clients are converted,
over to the new API, we're stuck with this.

Also, now the DMA40 has been DT:ed, there's no requirement to register
it using traditional methods, so let's remove it.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.h   |    1 +
 arch/arm/mach-ux500/cpu-db8500.c     |   13 +++----------
 arch/arm/mach-ux500/devices-db8500.c |    2 +-
 3 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d38951b..2c5139d 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat;
 extern struct amba_pl011_data uart1_plat;
 extern struct amba_pl011_data uart2_plat;
 extern struct pl022_ssp_controller ssp0_plat;
+extern struct stedma40_platform_data dma40_plat_data;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index d769459..b22faa8 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -229,16 +229,6 @@ static struct device * __init u8500_of_init_devices(void)
 
 	db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 
-	u8500_dma40_device.dev.parent = parent;
-
-	/*
-	 * Devices to be DT:ed:
-	 *   u8500_dma40_device  = todo
-	 *   db8500_pmu_device   = done
-	 *   db8500_prcmu_device = done
-	 */
-	platform_device_register(&u8500_dma40_device);
-
 	return parent;
 }
 
@@ -283,6 +273,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 		"ux500-msp-i2s.2", &msp2_platform_data),
 	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
 		"ux500-msp-i2s.3", &msp3_platform_data),
+	/* Requires clock name bindings and channel address lookup table. */
+	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
+		       "dma40.0", &dma40_plat_data),
 	{},
 };
 
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 99bc532..2bc4b5e 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -120,7 +120,7 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
 	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
 };
 
-static struct stedma40_platform_data dma40_plat_data = {
+struct stedma40_platform_data dma40_plat_data = {
 	.dev_rx = dma40_rx_map,
 	.dev_tx = dma40_tx_map,
 	.disabled_channels = {-1},
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:12 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:12 +0100
Subject: [PATCH 26/63] dmaengine: ste_dma40: Supply full Device Tree parsing
 support
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-27-git-send-email-lee.jones@linaro.org>

Using the new DMA DT bindings and API, we can register the DMA40 driver
as Device Tree capable. Now, when a client attempts to allocate a
channel using the DMA DT bindings via its own node, we are able to parse
the request and allocate a channel in the correct manner.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: devicetree-discuss at lists.ozlabs.org
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/dma/ste-dma40.txt          |   62 ++++++++++++++++++++
 drivers/dma/ste_dma40.c                            |   52 ++++++++++++++++
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/ste-dma40.txt

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
new file mode 100644
index 0000000..2679a87
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -0,0 +1,62 @@
+* DMA40 DMA Controller
+
+Required properties:
+- compatible: "stericsson,dma40"
+- reg: Address range of the DMAC registers
+- reg-names: Names of the above areas to use during resource look-up
+- interrupt: Should contain the DMAC interrupt number
+- #dma-cells: must be <3>
+
+Optional properties:
+- dma-channels: Number of channels supported by hardware - if not present
+		the driver will attempt to obtain the information from H/W
+
+Example:
+
+	dma: dma-controller at 801C0000 {
+		compatible = "stericsson,db8500-dma40", "stericsson,dma40";
+		reg = <0x801C0000 0x1000  0x40010000 0x800>;
+		reg-names = "base", "lcpa";
+		interrupt-parent = <&intc>;
+		interrupts = <0 25 0x4>;
+
+		#dma-cells = <2>;
+		dma-channels = <8>;
+	};
+
+Clients
+Required properties:
+- dmas: Comma separated list of dma channel requests
+- dma-names: Names of the aforementioned requested channels
+
+Each dmas request consists of 4 cells:
+  1. A phandle pointing to the DMA controller
+  2. Device Type
+  3. The DMA request line number (only when 'use fixed channel' is set)
+  4. A 32bit mask specifying; mode, direction and endianess [NB: This list will grow]
+        0x00000001: Mode:
+                Logical channel when unset
+                Physical channel when set
+        0x00000002: Direction:
+                Memory to Device when unset
+                Device to Memory when set
+        0x00000004: Endianess:
+                Little endian when unset
+                Big endian when set
+        0x00000008: Use fixed channel:
+                Use automatic channel selection when unset
+                Use DMA request line number when set
+
+Example:
+
+	uart at 80120000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x80120000 0x1000>;
+		interrupts = <0 11 0x4>;
+
+		dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+		       <&dma 13 0 0x0>; /* Logical - MemToDev */
+		dma-names = "rx", "rx";
+
+		status = "disabled";
+	};
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index d7c2397..b77d508 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -18,6 +18,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/err.h>
 #include <linux/of.h>
+#include <linux/of_dma.h>
 #include <linux/amba/bus.h>
 #include <linux/regulator/consumer.h>
 #include <linux/platform_data/dma-ste-dma40.h>
@@ -2419,6 +2420,50 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
 }
 
+#define D40_DT_FLAGS_MODE(flags)       ((flags >> 0) & 0x1)
+#define D40_DT_FLAGS_DIR(flags)        ((flags >> 1) & 0x1)
+#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
+#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
+
+static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
+				  struct of_dma *ofdma)
+{
+	struct stedma40_chan_cfg cfg;
+	dma_cap_mask_t cap;
+	u32 flags;
+
+	memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
+
+	dma_cap_zero(cap);
+	dma_cap_set(DMA_SLAVE, cap);
+
+	cfg.dev_type = dma_spec->args[0];
+	flags = dma_spec->args[2];
+
+	switch (D40_DT_FLAGS_MODE(flags)) {
+	case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
+	case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
+	}
+
+	switch (D40_DT_FLAGS_DIR(flags)) {
+	case 0:
+		cfg.dir = STEDMA40_MEM_TO_PERIPH;
+		cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
+		break;
+	case 1:
+		cfg.dir = STEDMA40_PERIPH_TO_MEM;
+		cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
+		break;
+	}
+
+	if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
+		cfg.phy_channel = dma_spec->args[1];
+		cfg.use_fixed_channel = true;
+	}
+
+	return dma_request_channel(cap, stedma40_filter, &cfg);
+}
+
 /* DMA ENGINE functions */
 static int d40_alloc_chan_resources(struct dma_chan *chan)
 {
@@ -3632,6 +3677,13 @@ static int __init d40_probe(struct platform_device *pdev)
 
 	d40_hw_init(base);
 
+	if (np) {
+		err = of_dma_controller_register(np, d40_xlate, NULL);
+		if (err && err != -ENODEV)
+			dev_err(&pdev->dev,
+				"could not register of_dma_controller\n");
+	}
+
 	dev_info(base->dev, "initialized\n");
 	return 0;
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:14 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:14 +0100
Subject: [PATCH 28/63] ARM: ux500: Stop passing UART's platform data for
 Device Tree boots
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-29-git-send-email-lee.jones@linaro.org>

It was required to pass DMA channel configuration information to the
UART driver before the new DMA API was in place. Now that it is, and
is fully compatible with Device Tree we can stop doing that.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index b22faa8..91fcde8 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -236,9 +236,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 	/* Requires DMA bindings. */
-	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
-	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
-	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:15 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:15 +0100
Subject: [PATCH 29/63] ARM: ux500: Stop passing MMC's platform data for Device
 Tree boots
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-30-git-send-email-lee.jones@linaro.org>

It was required to pass DMA channel configuration information to the
MMC driver before the new DMA API was in place. Now that it is, and
is fully compatible with Device Tree we can stop doing that.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 91fcde8..bb8f58f 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -240,10 +240,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
 	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  NULL),
 	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:16 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:16 +0100
Subject: [PATCH 30/63] ARM: ux500: Move SDI (MMC) and UART devices under more
 descriptive heading
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-31-git-send-email-lee.jones@linaro.org>

Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
should be possible to remove them from the auxdata structure. However,
after doing so the drivers fail. Common clk is still reliant on the
dev_name() call to do device name matching, which will fail due to the
fact that Device Tree naming differs somewhat do the more traditional
conventions.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index bb8f58f..3276472 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -236,15 +236,15 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 	/* Requires DMA bindings. */
+	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
 	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
 	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
-	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  NULL),
-	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:17 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:17 +0100
Subject: [PATCH 31/63] dmaengine: ste_dma40: Only use addresses passed as
 configuration information
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-32-git-send-email-lee.jones@linaro.org>

Addresses are passed in from the client's driver via the invocation of
dmaengine_slave_config(), so there's no need to fetch them from platform
data too, hardwired or otherwise. This is a great step forward, as it
elevates a large burden from platform data in the way of a look-up
table.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   51 ++++++++++-------------------------------------
 1 file changed, 11 insertions(+), 40 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b77d508..3ff6ea4 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1760,22 +1760,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
 		res = -EINVAL;
 	}
 
-	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
-	    d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid TX channel address (%d)\n",
-			 conf->dev_type);
-		res = -EINVAL;
-	}
-
-	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
-	    d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid RX channel address (%d)\n",
-			 conf->dev_type);
-		res = -EINVAL;
-	}
-
 	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
 		/*
 		 * DMAC HW supports it. Will be added to this driver,
@@ -2313,14 +2297,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
 	if (sg_next(&sg_src[sg_len - 1]) == sg_src)
 		desc->cyclic = true;
 
-	if (direction != DMA_TRANS_NONE) {
-		dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
-
-		if (direction == DMA_DEV_TO_MEM)
-			src_dev_addr = dev_addr;
-		else if (direction == DMA_MEM_TO_DEV)
-			dst_dev_addr = dev_addr;
-	}
+	if (direction == DMA_DEV_TO_MEM)
+		src_dev_addr = chan->runtime_addr;
+	else if (direction == DMA_MEM_TO_DEV)
+		dst_dev_addr = chan->runtime_addr;
 
 	if (chan_is_logical(chan))
 		ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
@@ -2768,15 +2748,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	dst_maxburst = config->dst_maxburst;
 
 	if (config->direction == DMA_DEV_TO_MEM) {
-		dma_addr_t dev_addr_rx =
-			d40c->base->plat_data->dev_rx[cfg->dev_type];
-
 		config_addr = config->src_addr;
-		if (dev_addr_rx)
-			dev_dbg(d40c->base->dev,
-				"channel has a pre-wired RX address %08x "
-				"overriding with %08x\n",
-				dev_addr_rx, config_addr);
+
 		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for peripheral "
@@ -2791,15 +2764,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 			dst_maxburst = src_maxburst;
 
 	} else if (config->direction == DMA_MEM_TO_DEV) {
-		dma_addr_t dev_addr_tx =
-			d40c->base->plat_data->dev_tx[cfg->dev_type];
-
 		config_addr = config->dst_addr;
-		if (dev_addr_tx)
-			dev_dbg(d40c->base->dev,
-				"channel has a pre-wired TX address %08x "
-				"overriding with %08x\n",
-				dev_addr_tx, config_addr);
+
 		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for memory "
@@ -2819,6 +2785,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 		return -EINVAL;
 	}
 
+	if (config_addr <= 0) {
+		dev_err(d40c->base->dev, "no address supplied\n");
+		return -EINVAL;
+	}
+
 	if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
 		dev_err(d40c->base->dev,
 			"src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:18 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:18 +0100
Subject: [PATCH 32/63] dmaengine: ste_dma40: Remove redundant address fetching
 function
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-33-git-send-email-lee.jones@linaro.org>

Addresses are now stored in local data structures and are easy to
obtain, thus a specialist function used to fetch them is now surplus
to requirement.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 3ff6ea4..555d851 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2253,24 +2253,6 @@ err:
 	return NULL;
 }
 
-static dma_addr_t
-d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
-{
-	struct stedma40_platform_data *plat = chan->base->plat_data;
-	struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
-	dma_addr_t addr = 0;
-
-	if (chan->runtime_addr)
-		return chan->runtime_addr;
-
-	if (direction == DMA_DEV_TO_MEM)
-		addr = plat->dev_rx[cfg->dev_type];
-	else if (direction == DMA_MEM_TO_DEV)
-		addr = plat->dev_tx[cfg->dev_type];
-
-	return addr;
-}
-
 static struct dma_async_tx_descriptor *
 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
 	    struct scatterlist *sg_dst, unsigned int sg_len,
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:21 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:21 +0100
Subject: [PATCH 35/63] ARM: ux500: Remove unnecessary attributes from DMA
 channel request pdata
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-36-git-send-email-lee.jones@linaro.org>

DMA data width and packet size information is only required at channel
configuration time. Any information passed from platform data is passed
directly to the DMA40 driver to use during channel allocation, but these
pieces of information are subsequently ignored by the driver, so we may
as well remove them.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index e0ea490..821703d 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,19 +15,11 @@
 #define MUSB_DMA40_RX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_PERIPH_TO_MEM, \
-		.src_info.data_width = STEDMA40_WORD_WIDTH, \
-		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
-		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
 	}
 
 #define MUSB_DMA40_TX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_MEM_TO_PERIPH, \
-		.src_info.data_width = STEDMA40_WORD_WIDTH, \
-		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
-		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
 	}
 
 static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:19 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:19 +0100
Subject: [PATCH 33/63] ARM: ux500: Remove DMA address look-up table
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-34-git-send-email-lee.jones@linaro.org>

DMA addresses are now passed as part of the dmaengine API by invoking
dmaengine_slave_config(). So there's no requirement for the DMA40
driver to look them up in a table provided by platform data. This
method does not fit in well using Device Tree either.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/devices-db8500.c        |   80 ---------------------------
 include/linux/platform_data/dma-ste-dma40.h |    2 -
 2 files changed, 82 deletions(-)

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 2bc4b5e..d35a492 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,87 +42,7 @@ static struct resource dma40_resources[] = {
 	}
 };
 
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
-	/* PrimeCells - run-time configured */
-	[DB8500_DMA_DEV0_SPI0] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2] = -1,
-	[DB8500_DMA_DEV8_SSP0] = -1,
-	[DB8500_DMA_DEV9_SSP1] = -1,
-	[DB8500_DMA_DEV11_UART2] = -1,
-	[DB8500_DMA_DEV12_UART1] = -1,
-	[DB8500_DMA_DEV13_UART0] = -1,
-	[DB8500_DMA_DEV28_SD_MM2] = -1,
-	[DB8500_DMA_DEV29_SD_MM0] = -1,
-	[DB8500_DMA_DEV32_SD_MM1] = -1,
-	[DB8500_DMA_DEV33_SPI2] = -1,
-	[DB8500_DMA_DEV35_SPI1] = -1,
-	[DB8500_DMA_DEV40_SPI3] = -1,
-	[DB8500_DMA_DEV41_SD_MM3] = -1,
-	[DB8500_DMA_DEV42_SD_MM4] = -1,
-	[DB8500_DMA_DEV43_SD_MM5] = -1,
-	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-	[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
-	/* PrimeCells */
-	[DB8500_DMA_DEV0_SPI0] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2] = -1,
-	[DB8500_DMA_DEV8_SSP0] = -1,
-	[DB8500_DMA_DEV9_SSP1] = -1,
-	[DB8500_DMA_DEV11_UART2] = -1,
-	[DB8500_DMA_DEV12_UART1] = -1,
-	[DB8500_DMA_DEV13_UART0] = -1,
-	[DB8500_DMA_DEV28_SD_MM2] = -1,
-	[DB8500_DMA_DEV29_SD_MM0] = -1,
-	[DB8500_DMA_DEV32_SD_MM1] = -1,
-	[DB8500_DMA_DEV33_SPI2] = -1,
-	[DB8500_DMA_DEV35_SPI1] = -1,
-	[DB8500_DMA_DEV40_SPI3] = -1,
-	[DB8500_DMA_DEV41_SD_MM3] = -1,
-	[DB8500_DMA_DEV42_SD_MM4] = -1,
-	[DB8500_DMA_DEV43_SD_MM5] = -1,
-	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
 struct stedma40_platform_data dma40_plat_data = {
-	.dev_rx = dma40_rx_map,
-	.dev_tx = dma40_tx_map,
 	.disabled_channels = {-1},
 };
 
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index c54af61..af0064e 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -152,8 +152,6 @@ struct stedma40_chan_cfg {
  * for 'multiple of 4' channels, like 8.
  */
 struct stedma40_platform_data {
-	const dma_addr_t		*dev_tx;
-	const dma_addr_t		*dev_rx;
 	int				 disabled_channels[STEDMA40_MAX_PHYS];
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:20 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:20 +0100
Subject: [PATCH 34/63] dmaengine: ste_dma40: Correct copy/paste error
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-35-git-send-email-lee.jones@linaro.org>

'struct stedma40_half_channel_info's header comment says that it's
called 'struct stedma40_chan_cfg'. Let's straighten that out.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/platform_data/dma-ste-dma40.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index af0064e..288dc24 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
 
 
 /**
- * struct stedma40_chan_cfg - dst/src channel configuration
+ * struct stedma40_half_channel_info - dst/src channel configuration
  *
  * @big_endian: true if the src/dst should be read as big endian
  * @data_width: Data width of the src/dst hardware
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:22 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:22 +0100
Subject: [PATCH 36/63] crypto: ux500/hash - Prepare clock before enabling it
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-37-git-send-email-lee.jones@linaro.org>

If we fail to prepare the ux500-hash clock before enabling it the
platform will fail to boot. Here we insure this happens.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: Ulf Hansson <ulf.hansson at linaro.org>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_core.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 632c333..1e8b2f3 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1727,11 +1727,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_regulator;
 	}
 
+	ret = clk_prepare(device_data->clk);
+	if (ret) {
+		dev_err(dev, "[%s] clk_prepare() failed!", __func__);
+		goto out_clk;
+	}
+
 	/* Enable device power (and clock) */
 	ret = hash_enable_power(device_data, false);
 	if (ret) {
 		dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
-		goto out_clk;
+		goto out_clk_unprepare;
 	}
 
 	ret = hash_check_hw(device_data);
@@ -1763,6 +1769,9 @@ static int ux500_hash_probe(struct platform_device *pdev)
 out_power:
 	hash_disable_power(device_data, false);
 
+out_clk_unprepare:
+	clk_unprepare(device_data->clk);
+
 out_clk:
 	clk_put(device_data->clk);
 
@@ -1827,6 +1836,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
 		dev_err(dev, "[%s]: hash_disable_power() failed",
 			__func__);
 
+	clk_unprepare(device_data->clk);
 	clk_put(device_data->clk);
 	regulator_put(device_data->regulator);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:24 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:24 +0100
Subject: [PATCH 38/63] ARM: ux500: Stop passing Hash DMA channel config
 information though pdata
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-39-git-send-email-lee.jones@linaro.org>

DMA channel configuration information should be setup in the driver.
The Ux500 Hash driver now does this, so there's no need to send it
though here too.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 883dc66..cb7ae23 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -473,11 +473,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
 		.dir = STEDMA40_MEM_TO_PERIPH,
 		.dev_type = DB8500_DMA_DEV50_HAC1_TX,
-		.src_info.data_width = STEDMA40_WORD_WIDTH,
-		.dst_info.data_width = STEDMA40_WORD_WIDTH,
 		.mode = STEDMA40_MODE_LOGICAL,
-		.src_info.psize = STEDMA40_PSIZE_LOG_16,
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16,
 };
 
 static struct hash_platform_data u8500_hash1_platform_data = {
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:25 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:25 +0100
Subject: [PATCH 39/63] crypto: ux500/cryp - Prepare clock before enabling it
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-40-git-send-email-lee.jones@linaro.org>

If we fail to prepare the ux500-cryp clock before enabling it the
platform will fail to boot. Here we insure this happens.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: Ulf Hansson <ulf.hansson at linaro.org>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 22c9063..bf78d60 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1459,11 +1459,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_regulator;
 	}
 
+	ret = clk_prepare(device_data->clk);
+	if (ret) {
+		dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
+		goto out_clk;
+	}
+
 	/* Enable device power (and clock) */
 	ret = cryp_enable_power(device_data->dev, device_data, false);
 	if (ret) {
 		dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
-		goto out_clk;
+		goto out_clk_unprepare;
 	}
 
 	cryp_error = cryp_check(device_data);
@@ -1524,6 +1530,9 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 out_power:
 	cryp_disable_power(device_data->dev, device_data, false);
 
+out_clk_unprepare:
+	clk_unprepare(device_data->clk);
+
 out_clk:
 	clk_put(device_data->clk);
 
@@ -1594,6 +1603,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
 		dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
 			__func__);
 
+	clk_unprepare(device_data->clk);
 	clk_put(device_data->clk);
 	regulator_put(device_data->pwr_regulator);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:23 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:23 +0100
Subject: [PATCH 37/63] crypto: ux500/hash - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-38-git-send-email-lee.jones@linaro.org>

The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_alg.h  |    5 ++++-
 drivers/crypto/ux500/hash/hash_core.c |   10 ++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index cd9351c..be6eb54 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -11,6 +11,7 @@
 #include <linux/bitops.h>
 
 #define HASH_BLOCK_SIZE			64
+#define HASH_DMA_FIFO			4
 #define HASH_DMA_ALIGN_SIZE		4
 #define HASH_DMA_PERFORMANCE_MIN_SIZE	1024
 #define HASH_BYTES_PER_WORD		4
@@ -347,7 +348,8 @@ struct hash_req_ctx {
 
 /**
  * struct hash_device_data - structure for a hash device.
- * @base:		Pointer to the hardware base address.
+ * @base:		Pointer to virtual base address of the hash device.
+ * @phybase:		Pointer to physical memory location of the hash device.
  * @list_node:		For inclusion in klist.
  * @dev:		Pointer to the device dev structure.
  * @ctx_lock:		Spinlock for current_ctx.
@@ -361,6 +363,7 @@ struct hash_req_ctx {
  */
 struct hash_device_data {
 	struct hash_register __iomem	*base;
+	phys_addr_t             phybase;
 	struct klist_node	list_node;
 	struct device		*dev;
 	struct spinlock		ctx_lock;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 1e8b2f3..5d8a7f3 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -123,6 +123,13 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				struct device *dev)
 {
 	struct hash_platform_data *platform_data = dev->platform_data;
+	struct dma_slave_config conf = {
+		.direction = DMA_MEM_TO_DEV,
+		.dst_addr = device_data->phybase + HASH_DMA_FIFO,
+		.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.dst_maxburst = 16,
+        };
+
 	dma_cap_zero(device_data->dma.mask);
 	dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 
@@ -132,6 +139,8 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				platform_data->dma_filter,
 				device_data->dma.cfg_mem2hash);
 
+	dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
+
 	init_completion(&device_data->dma.complete);
 }
 
@@ -1700,6 +1709,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_kfree;
 	}
 
+	device_data->phybase = res->start;
 	device_data->base = ioremap(res->start, resource_size(res));
 	if (!device_data->base) {
 		dev_err(dev, "[%s] ioremap() failed!",
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:26 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:26 +0100
Subject: [PATCH 40/63] crypto: ux500/cryp - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-41-git-send-email-lee.jones@linaro.org>

The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp.h      |    7 ++++++-
 drivers/crypto/ux500/cryp/cryp_core.c |   17 +++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp.h b/drivers/crypto/ux500/cryp/cryp.h
index 14cfd05..d1d6606 100644
--- a/drivers/crypto/ux500/cryp/cryp.h
+++ b/drivers/crypto/ux500/cryp/cryp.h
@@ -114,6 +114,9 @@ enum cryp_status_id {
 };
 
 /* Cryp DMA interface */
+#define CRYP_DMA_TX_FIFO	0x08
+#define CRYP_DMA_RX_FIFO	0x10
+
 enum cryp_dma_req_type {
 	CRYP_DMA_DISABLE_BOTH,
 	CRYP_DMA_ENABLE_IN_DATA,
@@ -217,7 +220,8 @@ struct cryp_dma {
 
 /**
  * struct cryp_device_data - structure for a cryp device.
- * @base: Pointer to the hardware base address.
+ * @base: Pointer to virtual base address of the cryp device.
+ * @phybase: Pointer to physical memory location of the cryp device.
  * @dev: Pointer to the devices dev structure.
  * @clk: Pointer to the device's clock control.
  * @pwr_regulator: Pointer to the device's power control.
@@ -232,6 +236,7 @@ struct cryp_dma {
  */
 struct cryp_device_data {
 	struct cryp_register __iomem *base;
+	phys_addr_t phybase;
 	struct device *dev;
 	struct clk *clk;
 	struct regulator *pwr_regulator;
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index bf78d60..4b90493 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -476,6 +476,19 @@ static int cryp_get_device_data(struct cryp_ctx *ctx,
 static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
 				   struct device *dev)
 {
+	struct dma_slave_config mem2cryp = {
+		.direction = DMA_MEM_TO_DEV,
+		.dst_addr = device_data->phybase + CRYP_DMA_TX_FIFO,
+		.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.dst_maxburst = 4,
+        };
+	struct dma_slave_config cryp2mem = {
+		.direction = DMA_DEV_TO_MEM,
+		.src_addr = device_data->phybase + CRYP_DMA_RX_FIFO,
+		.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.src_maxburst = 4,
+        };
+
 	dma_cap_zero(device_data->dma.mask);
 	dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 
@@ -491,6 +504,9 @@ static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
 				    stedma40_filter,
 				    device_data->dma.cfg_cryp2mem);
 
+	dmaengine_slave_config(device_data->dma.chan_mem2cryp, &mem2cryp);
+	dmaengine_slave_config(device_data->dma.chan_cryp2mem, &cryp2mem);
+
 	init_completion(&device_data->dma.cryp_dma_complete);
 }
 
@@ -1432,6 +1448,7 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_kfree;
 	}
 
+	device_data->phybase = res->start;
 	device_data->base = ioremap(res->start, resource_size(res));
 	if (!device_data->base) {
 		dev_err(dev, "[%s]: ioremap failed!", __func__);
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:29 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:29 +0100
Subject: [PATCH 43/63] ARM: ux500: Register Cyrp and Hash platform drivers on
 Snowball
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-44-git-send-email-lee.jones@linaro.org>

These drivers are now operational and even use the latest common clk
and DMA APIs. There's no reason why we shouldn't start them up now.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 7f756cc..3866fa8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -656,6 +656,8 @@ static void __init snowball_init_machine(void)
 
 	mop500_snowball_ethernet_clock_enable();
 
+	u8500_cryp1_hash1_init(parent);
+
 	/* This board has full regulator constraints */
 	regulator_has_full_constraints();
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:28 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:28 +0100
Subject: [PATCH 42/63] crypto: ux500/[cryp|hash] - Show successful start-up in
 the bootlog
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-43-git-send-email-lee.jones@linaro.org>

The Cryp driver is currently silent and the Hash driver prints the
name of its probe function unnecessarily. Let's just put a nice
descriptive one-liner there instead.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |    2 ++
 drivers/crypto/ux500/hash/hash_core.c |    2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 4b90493..78d7463 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1542,6 +1542,8 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_power;
 	}
 
+	dev_info(dev, "successfully registered\n");
+
 	return 0;
 
 out_power:
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 5d8a7f3..ac606b6 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1773,7 +1773,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_power;
 	}
 
-	dev_info(dev, "[%s] successfully probed\n", __func__);
+	dev_info(dev, "successfully registered\n");
 	return 0;
 
 out_power:
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:27 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:27 +0100
Subject: [PATCH 41/63] ARM: ux500: Stop passing Cryp DMA channel config
 information though pdata
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-42-git-send-email-lee.jones@linaro.org>

DMA channel configuration information should be setup in the driver.
The Ux500 Cryp driver now does this, so there's no need to send it
though here too.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index cb7ae23..7f756cc 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -453,20 +453,12 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 		.mem_to_engine = {
 				.dir = STEDMA40_MEM_TO_PERIPH,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
-				.src_info.data_width = STEDMA40_WORD_WIDTH,
-				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
-				.src_info.psize = STEDMA40_PSIZE_LOG_4,
-				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
 		},
 		.engine_to_mem = {
 				.dir = STEDMA40_PERIPH_TO_MEM,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
-				.src_info.data_width = STEDMA40_WORD_WIDTH,
-				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
-				.src_info.psize = STEDMA40_PSIZE_LOG_4,
-				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
 		}
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:30 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:30 +0100
Subject: [PATCH 44/63] usb: musb: ux500: move channel number knowledge into
 the driver
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-45-git-send-email-lee.jones@linaro.org>

For all ux500 based platforms the maximum number of end-points are used.
Move this knowledge into the driver so we can relinquish the burden from
platform data. This also removes quite a bit of complexity from the driver
and will aid us when we come to enable the driver for Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c                    |   14 ++++++------
 drivers/usb/musb/ux500_dma.c                 |   30 ++++++++------------------
 include/linux/platform_data/usb-musb-ux500.h |    5 +----
 3 files changed, 16 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 821703d..8aff9a4 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -22,7 +22,7 @@
 		.dir = STEDMA40_MEM_TO_PERIPH, \
 	}
 
-static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
 	= {
 	MUSB_DMA40_RX_CH,
 	MUSB_DMA40_RX_CH,
@@ -34,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
 	MUSB_DMA40_RX_CH
 };
 
-static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
 	= {
 	MUSB_DMA40_TX_CH,
 	MUSB_DMA40_TX_CH,
@@ -46,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
 	MUSB_DMA40_TX_CH,
 };
 
-static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
 	&musb_dma_rx_ch[0],
 	&musb_dma_rx_ch[1],
 	&musb_dma_rx_ch[2],
@@ -57,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
 	&musb_dma_rx_ch[7]
 };
 
-static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
 	&musb_dma_tx_ch[0],
 	&musb_dma_tx_ch[1],
 	&musb_dma_tx_ch[2],
@@ -71,8 +71,6 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
 static struct ux500_musb_board_data musb_board_data = {
 	.dma_rx_param_array = ux500_dma_rx_param_array,
 	.dma_tx_param_array = ux500_dma_tx_param_array,
-	.num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
-	.num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
 	.dma_filter = stedma40_filter,
 };
 
@@ -119,7 +117,7 @@ static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
 {
 	u32 idx;
 
-	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
+	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
 		musb_dma_rx_ch[idx].dev_type = dev_type[idx];
 }
 
@@ -127,7 +125,7 @@ static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
 {
 	u32 idx;
 
-	for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
+	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
 		musb_dma_tx_ch[idx].dev_type = dev_type[idx];
 }
 
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 039e567d..c75e07a 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -47,10 +47,8 @@ struct ux500_dma_channel {
 
 struct ux500_dma_controller {
 	struct dma_controller controller;
-	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
-	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
-	u32	num_rx_channels;
-	u32	num_tx_channels;
+	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
+	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
 	void *private_data;
 	dma_addr_t phy_base;
 };
@@ -142,19 +140,15 @@ static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
 	struct ux500_dma_channel *ux500_channel = NULL;
 	struct musb *musb = controller->private_data;
 	u8 ch_num = hw_ep->epnum - 1;
-	u32 max_ch;
 
-	/* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
+	/* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
 	 * to specified hw_ep. For example DMA channel 0 can only be allocated
 	 * to hw_ep 1 and 9.
 	 */
 	if (ch_num > 7)
 		ch_num -= 8;
 
-	max_ch = is_tx ? controller->num_tx_channels :
-			controller->num_rx_channels;
-
-	if (ch_num >= max_ch)
+	if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
 		return NULL;
 
 	ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
@@ -262,7 +256,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c)
 	struct dma_channel *channel;
 	u8 ch_num;
 
-	for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
+	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
 		channel = &controller->rx_channel[ch_num].channel;
 		ux500_channel = channel->private_data;
 
@@ -272,7 +266,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c)
 			dma_release_channel(ux500_channel->dma_chan);
 	}
 
-	for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
+	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
 		channel = &controller->tx_channel[ch_num].channel;
 		ux500_channel = channel->private_data;
 
@@ -301,26 +295,21 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 
 	void **param_array;
 	struct ux500_dma_channel *channel_array;
-	u32 ch_count;
 	dma_cap_mask_t mask;
 
-	if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
-		(data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
-		return -EINVAL;
 
-	controller->num_rx_channels = data->num_rx_channels;
-	controller->num_tx_channels = data->num_tx_channels;
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 
 	/* Prepare the loop for RX channels */
 	channel_array = controller->rx_channel;
-	ch_count = data->num_rx_channels;
 	param_array = data->dma_rx_param_array;
 
 	for (dir = 0; dir < 2; dir++) {
-		for (ch_num = 0; ch_num < ch_count; ch_num++) {
+		for (ch_num = 0;
+		     ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
+		     ch_num++) {
 			ux500_channel = &channel_array[ch_num];
 			ux500_channel->controller = controller;
 			ux500_channel->ch_num = ch_num;
@@ -348,7 +337,6 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 
 		/* Prepare the loop for TX channels */
 		channel_array = controller->tx_channel;
-		ch_count = data->num_tx_channels;
 		param_array = data->dma_tx_param_array;
 		is_tx = 1;
 	}
diff --git a/include/linux/platform_data/usb-musb-ux500.h b/include/linux/platform_data/usb-musb-ux500.h
index 4c1cc50..dd9c83a 100644
--- a/include/linux/platform_data/usb-musb-ux500.h
+++ b/include/linux/platform_data/usb-musb-ux500.h
@@ -9,14 +9,11 @@
 
 #include <linux/dmaengine.h>
 
-#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
-#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
+#define UX500_MUSB_DMA_NUM_RX_TX_CHANNELS 8
 
 struct ux500_musb_board_data {
 	void	**dma_rx_param_array;
 	void	**dma_tx_param_array;
-	u32	num_rx_channels;
-	u32	num_tx_channels;
 	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:31 +0100
Subject: [PATCH 45/63] usb: musb: ux500: move the MUSB HDRC configuration into
 the driver
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-46-git-send-email-lee.jones@linaro.org>

The MUSB HDRC configuration never changes between each of the ux500
supported platforms, so there's little point passing it though platform
data. If we set it in the driver instead, we can make good use of it
when booting with either ATAGs or Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    8 --------
 drivers/usb/musb/ux500.c  |    8 ++++++++
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 8aff9a4..4f68a9c 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -76,16 +76,8 @@ static struct ux500_musb_board_data musb_board_data = {
 
 static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
 
-static struct musb_hdrc_config musb_hdrc_config = {
-	.multipoint	= true,
-	.dyn_fifo	= true,
-	.num_eps	= 16,
-	.ram_bits	= 16,
-};
-
 static struct musb_hdrc_platform_data musb_platform_data = {
 	.mode = MUSB_OTG,
-	.config = &musb_hdrc_config,
 	.board_data = &musb_board_data,
 };
 
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 13a3929..4a8f5c9 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -29,6 +29,13 @@
 
 #include "musb_core.h"
 
+static struct musb_hdrc_config ux500_musb_hdrc_config = {
+	.multipoint	= true,
+	.dyn_fifo	= true,
+	.num_eps	= 16,
+	.ram_bits	= 16,
+};
+
 struct ux500_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
@@ -123,6 +130,7 @@ static int ux500_probe(struct platform_device *pdev)
 	glue->clk			= clk;
 
 	pdata->platform_ops		= &ux500_ops;
+	pdata->config 			= &ux500_musb_hdrc_config;
 
 	platform_set_drvdata(pdev, glue);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:33 +0100
Subject: [PATCH 47/63] usb: musb: ux500: harden checks for platform data
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-48-git-send-email-lee.jones@linaro.org>

In its current state, the ux500-musb driver uses platform data pointers
blindly with no prior checking. If no platform data pointer is passed
this will Oops the kernel. In this patch we ensure platform data and
board data are present prior to using them.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/usb/musb/ux500_dma.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index c75e07a..8d5128d 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -287,7 +287,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	struct musb *musb = controller->private_data;
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
-	struct ux500_musb_board_data *data = plat->board_data;
+	struct ux500_musb_board_data *data;
 	struct dma_channel *dma_channel = NULL;
 	u32 ch_num;
 	u8 dir;
@@ -297,14 +297,19 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	struct ux500_dma_channel *channel_array;
 	dma_cap_mask_t mask;
 
+	if (!plat) {
+		dev_err(musb->controller, "No platform data\n");
+		return -EINVAL;
+	}
 
+	data = plat->board_data;
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 
 	/* Prepare the loop for RX channels */
 	channel_array = controller->rx_channel;
-	param_array = data->dma_rx_param_array;
+	param_array = data ? data->dma_rx_param_array : NULL;
 
 	for (dir = 0; dir < 2; dir++) {
 		for (ch_num = 0;
@@ -337,7 +342,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 
 		/* Prepare the loop for TX channels */
 		channel_array = controller->tx_channel;
-		param_array = data->dma_tx_param_array;
+		param_array = data ? data->dma_tx_param_array : NULL;
 		is_tx = 1;
 	}
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:32 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:32 +0100
Subject: [PATCH 46/63] usb: musb: ux500: take the dma_mask from
 coherent_dma_mask
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-47-git-send-email-lee.jones@linaro.org>

The dma_mask will always be the same as the coherent_dma_mask, so let's
cut down on the platform_data burden and set it as such in the driver.
This also saves us from supporting it separately when we come to enable
this driver for Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    3 ---
 drivers/usb/musb/ux500.c  |    2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 4f68a9c..e6c4a05 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -74,8 +74,6 @@ static struct ux500_musb_board_data musb_board_data = {
 	.dma_filter = stedma40_filter,
 };
 
-static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
-
 static struct musb_hdrc_platform_data musb_platform_data = {
 	.mode = MUSB_OTG,
 	.board_data = &musb_board_data,
@@ -98,7 +96,6 @@ struct platform_device ux500_musb_device = {
 	.id = 0,
 	.dev = {
 		.platform_data = &musb_platform_data,
-		.dma_mask = &ux500_musb_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
 	.num_resources = ARRAY_SIZE(usb_resources),
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 4a8f5c9..7ddb132 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -122,7 +122,7 @@ static int ux500_probe(struct platform_device *pdev)
 	}
 
 	musb->dev.parent		= &pdev->dev;
-	musb->dev.dma_mask		= pdev->dev.dma_mask;
+	musb->dev.dma_mask		= &pdev->dev.coherent_dma_mask;
 	musb->dev.coherent_dma_mask	= pdev->dev.coherent_dma_mask;
 
 	glue->dev			= &pdev->dev;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:37 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:37 +0100
Subject: [PATCH 51/63] ARM: ux500: Remove ux500-musb platform registation when
 booting with DT
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-52-git-send-email-lee.jones@linaro.org>

Now the ux500-musb driver has been enabled for Device Tree, there is no
requirement to register it from platform code.

Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 5a6b9ae..36ef6ed 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -227,8 +227,6 @@ static struct device * __init u8500_of_init_devices(void)
 {
 	struct device *parent = db8500_soc_device_init();
 
-	db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
-
 	return parent;
 }
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:36 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:36 +0100
Subject: [PATCH 50/63] ARM: ux500: Add an auxdata entry for MUSB for
 clock-name look-up
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-51-git-send-email-lee.jones@linaro.org>

The recently DT:ed MUSB driver will require clock-name by device-name
look-up capability, until common clk has is properly supported by the
ux500 platform.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 3276472..5a6b9ae 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -259,6 +259,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+	OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
 	/* Requires device name bindings. */
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:38 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:38 +0100
Subject: [PATCH 52/63] ARM: ux500: Remove empty function
 u8500_of_init_devices()
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-53-git-send-email-lee.jones@linaro.org>

As promised, now all devices which resided in u8500_of_init_devices()
have been enabled for Device Tree, we can completely remove it.

Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |   14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 36ef6ed..a2c83c2 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -221,15 +221,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 }
 
 #ifdef CONFIG_MACH_UX500_DT
-
-/* TODO: Once all pieces are DT:ed, remove completely. */
-static struct device * __init u8500_of_init_devices(void)
-{
-	struct device *parent = db8500_soc_device_init();
-
-	return parent;
-}
-
 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
@@ -288,7 +279,7 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
 
 static void __init u8500_init_machine(void)
 {
-	struct device *parent = NULL;
+	struct device *parent = db8500_soc_device_init();
 
 	/* Pinmaps must be in place before devices register */
 	if (of_machine_is_compatible("st-ericsson,mop500"))
@@ -301,9 +292,6 @@ static void __init u8500_init_machine(void)
 	else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
 		/* TODO: Add pinmaps for ccu9540 board. */
 
-	/* TODO: Export SoC, USB, cpu-freq and DMA40 */
-	parent = u8500_of_init_devices();
-
 	/* automatically probe child nodes of db8500 device */
 	of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:39 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:39 +0100
Subject: [PATCH 53/63] dmaengine: ste_dma40: Use the BIT macro to replace ugly
 '(1 << x)'s
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-54-git-send-email-lee.jones@linaro.org>

The aim is to make the code that little more readable.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 555d851..8e7fa9d 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -54,8 +54,8 @@
 #define MAX_LCLA_ALLOC_ATTEMPTS 256
 
 /* Bit markings for allocation map */
-#define D40_ALLOC_FREE		(1 << 31)
-#define D40_ALLOC_PHY		(1 << 30)
+#define D40_ALLOC_FREE		BIT(31)
+#define D40_ALLOC_PHY		BIT(30)
 #define D40_ALLOC_LOG_FREE	0
 
 /* Reserved event lines for memcpy only. */
@@ -1724,7 +1724,7 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data)
 		}
 
 		/* ACK interrupt */
-		writel(1 << idx, base->virtbase + il[row].clr);
+		writel(BIT(idx), base->virtbase + il[row].clr);
 
 		spin_lock(&d40c->lock);
 
@@ -1814,8 +1814,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy,
 		if (phy->allocated_src == D40_ALLOC_FREE)
 			phy->allocated_src = D40_ALLOC_LOG_FREE;
 
-		if (!(phy->allocated_src & (1 << log_event_line))) {
-			phy->allocated_src |= 1 << log_event_line;
+		if (!(phy->allocated_src & BIT(log_event_line))) {
+			phy->allocated_src |= BIT(log_event_line);
 			goto found;
 		} else
 			goto not_found;
@@ -1826,8 +1826,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy,
 		if (phy->allocated_dst == D40_ALLOC_FREE)
 			phy->allocated_dst = D40_ALLOC_LOG_FREE;
 
-		if (!(phy->allocated_dst & (1 << log_event_line))) {
-			phy->allocated_dst |= 1 << log_event_line;
+		if (!(phy->allocated_dst & BIT(log_event_line))) {
+			phy->allocated_dst |= BIT(log_event_line);
 			goto found;
 		} else
 			goto not_found;
@@ -1857,11 +1857,11 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
 
 	/* Logical channel */
 	if (is_src) {
-		phy->allocated_src &= ~(1 << log_event_line);
+		phy->allocated_src &= ~BIT(log_event_line);
 		if (phy->allocated_src == D40_ALLOC_LOG_FREE)
 			phy->allocated_src = D40_ALLOC_FREE;
 	} else {
-		phy->allocated_dst &= ~(1 << log_event_line);
+		phy->allocated_dst &= ~BIT(log_event_line);
 		if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
 			phy->allocated_dst = D40_ALLOC_FREE;
 	}
@@ -2342,7 +2342,7 @@ static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
 	u32 rtreg;
 	u32 event = D40_TYPE_TO_EVENT(dev_type);
 	u32 group = D40_TYPE_TO_GROUP(dev_type);
-	u32 bit = 1 << event;
+	u32 bit = BIT(event);
 	u32 prioreg;
 	struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:35 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:35 +0100
Subject: [PATCH 49/63] usb: musb: ux500: add device tree probing support
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-50-git-send-email-lee.jones@linaro.org>

This patch will allow ux500-musb to be probed and configured solely from
configuration found in Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: linux-usb at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/usb/ux500-usb.txt          |   50 +++++++++++++++++++
 drivers/usb/musb/ux500.c                           |   51 ++++++++++++++++++++
 2 files changed, 101 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/ux500-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt
new file mode 100644
index 0000000..330d6ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ux500-usb.txt
@@ -0,0 +1,50 @@
+Ux500 MUSB
+
+Required properties:
+ - compatible : Should be "stericsson,db8500-musb"
+ - reg        : Offset and length of registers
+ - interrupts : Interrupt; mode, number and trigger
+ - dr_mode    : Dual-role; either host mode "host", peripheral mode "peripheral"
+                or both "otg"
+
+Optional properties:
+ - dmas       : A list of dma channels;
+                dma-controller, event-line, fixed-channel, flags
+ - dma-names  : An ordered list of channel names affiliated to the above
+
+Example:
+
+usb_per5 at a03e0000 {
+	compatible = "stericsson,db8500-musb", "mentor,musb";
+	reg = <0xa03e0000 0x10000>;
+	interrupts = <0 23 0x4>;
+	interrupt-names = "mc";
+
+	dr_mode = "otg";
+
+	dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+	       <&dma 38 0 0x0>, /* Logical - MemToDev */
+	       <&dma 37 0 0x2>, /* Logical - DevToMem */
+	       <&dma 37 0 0x0>, /* Logical - MemToDev */
+	       <&dma 36 0 0x2>, /* Logical - DevToMem */
+	       <&dma 36 0 0x0>, /* Logical - MemToDev */
+	       <&dma 19 0 0x2>, /* Logical - DevToMem */
+	       <&dma 19 0 0x0>, /* Logical - MemToDev */
+	       <&dma 18 0 0x2>, /* Logical - DevToMem */
+	       <&dma 18 0 0x0>, /* Logical - MemToDev */
+	       <&dma 17 0 0x2>, /* Logical - DevToMem */
+	       <&dma 17 0 0x0>, /* Logical - MemToDev */
+	       <&dma 16 0 0x2>, /* Logical - DevToMem */
+	       <&dma 16 0 0x0>, /* Logical - MemToDev */
+	       <&dma 39 0 0x2>, /* Logical - DevToMem */
+	       <&dma 39 0 0x0>; /* Logical - MemToDev */
+
+	dma-names = "iep_1_9",  "oep_1_9",
+		    "iep_2_10", "oep_2_10",
+		    "iep_3_11", "oep_3_11",
+		    "iep_4_12", "oep_4_12",
+		    "iep_5_13", "oep_5_13",
+		    "iep_6_14", "oep_6_14",
+		    "iep_7_15", "oep_7_15",
+		    "iep_8",    "oep_8";
+};
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 7ddb132..5ff304c 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -25,6 +25,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 
 #include "musb_core.h"
@@ -88,14 +89,57 @@ static const struct musb_platform_ops ux500_ops = {
 	.exit		= ux500_musb_exit,
 };
 
+static struct musb_hdrc_platform_data *
+ux500_of_probe(struct platform_device *pdev, struct device_node *np)
+{
+	struct musb_hdrc_platform_data *pdata;
+	const char *mode;
+	int strlen;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	mode = of_get_property(np, "dr_mode", &strlen);
+	if (!mode) {
+		dev_err(&pdev->dev, "No 'dr_mode' property found\n");
+		return NULL;
+	}
+
+	if (strlen > 0) {
+		if (!strcmp(mode, "host"))
+			pdata->mode = MUSB_HOST;
+		if (!strcmp(mode, "otg"))
+			pdata->mode = MUSB_OTG;
+		if (!strcmp(mode, "peripheral"))
+			pdata->mode = MUSB_PERIPHERAL;
+	}
+
+	return pdata;
+}
+
 static int ux500_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
+	struct device_node		*np = pdev->dev.of_node;
 	struct platform_device		*musb;
 	struct ux500_glue		*glue;
 	struct clk			*clk;
 	int				ret = -ENOMEM;
 
+	if (!pdata) {
+		if (np) {
+			pdata = ux500_of_probe(pdev, np);
+			if (!pdata)
+				goto err0;
+
+			pdev->dev.platform_data = pdata;
+		} else {
+			dev_err(&pdev->dev, "no pdata or device tree found\n");
+			goto err0;
+		}
+	}
+
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
@@ -124,6 +168,7 @@ static int ux500_probe(struct platform_device *pdev)
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &pdev->dev.coherent_dma_mask;
 	musb->dev.coherent_dma_mask	= pdev->dev.coherent_dma_mask;
+	musb->dev.of_node		= pdev->dev.of_node;
 
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
@@ -222,12 +267,18 @@ static const struct dev_pm_ops ux500_pm_ops = {
 #define DEV_PM_OPS	NULL
 #endif
 
+static const struct of_device_id ux500_match[] = {
+        { .compatible = "stericsson,db8500-musb", },
+        {}
+};
+
 static struct platform_driver ux500_driver = {
 	.probe		= ux500_probe,
 	.remove		= ux500_remove,
 	.driver		= {
 		.name	= "musb-ux500",
 		.pm	= DEV_PM_OPS,
+		.of_match_table = ux500_match,
 	},
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:34 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:34 +0100
Subject: [PATCH 48/63] usb: musb: ux500: attempt to find channels by name
 before using pdata
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-49-git-send-email-lee.jones@linaro.org>

If we can ever get to a state where we can solely search for DMA channels
by name, this will almost completely alleviate the requirement to pass
copious amounts of information though platform data. Here we take the
first step towards this. The next step will be to enable Device Tree
complete with name<->event_line mapping.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/usb/musb/ux500_dma.c |   20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 8d5128d..99ad1fe 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -33,6 +33,11 @@
 #include <linux/platform_data/usb-musb-ux500.h>
 #include "musb_core.h"
 
+static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
+					"iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
+static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
+					"oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
+
 struct ux500_dma_channel {
 	struct dma_channel channel;
 	struct ux500_dma_controller *controller;
@@ -289,6 +294,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct ux500_musb_board_data *data;
 	struct dma_channel *dma_channel = NULL;
+	char **chan_names;
 	u32 ch_num;
 	u8 dir;
 	u8 is_tx = 0;
@@ -310,6 +316,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	/* Prepare the loop for RX channels */
 	channel_array = controller->rx_channel;
 	param_array = data ? data->dma_rx_param_array : NULL;
+	chan_names = (char **)iep_chan_names;
 
 	for (dir = 0; dir < 2; dir++) {
 		for (ch_num = 0;
@@ -325,9 +332,15 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 			dma_channel->status = MUSB_DMA_STATUS_FREE;
 			dma_channel->max_len = SZ_16M;
 
-			ux500_channel->dma_chan = dma_request_channel(mask,
-							data->dma_filter,
-							param_array[ch_num]);
+			ux500_channel->dma_chan =
+				dma_request_slave_channel(dev, chan_names[ch_num]);
+
+			if (!ux500_channel->dma_chan)
+				ux500_channel->dma_chan =
+					dma_request_channel(mask,
+							    data->dma_filter,
+							    param_array[ch_num]);
+
 			if (!ux500_channel->dma_chan) {
 				ERR("Dma pipe allocation error dir=%d ch=%d\n",
 					dir, ch_num);
@@ -343,6 +356,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 		/* Prepare the loop for TX channels */
 		channel_array = controller->tx_channel;
 		param_array = data ? data->dma_tx_param_array : NULL;
+		chan_names = (char **)oep_chan_names;
 		is_tx = 1;
 	}
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:40 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:40 +0100
Subject: [PATCH 54/63] ARM: ux500: Replace ST-E's home-brew DMA direction
 definition with the generic one
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-55-git-send-email-lee.jones@linaro.org>

STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-audio.c |   12 ++++++------
 arch/arm/mach-ux500/board-mop500-sdi.c   |   16 ++++++++--------
 arch/arm/mach-ux500/board-mop500.c       |   22 +++++++++++-----------
 arch/arm/mach-ux500/usb.c                |    4 ++--
 4 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 972bec0..4bd4d0f 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -22,13 +22,13 @@
 
 static struct stedma40_chan_cfg msp0_dma_rx = {
 	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
 static struct stedma40_chan_cfg msp0_dma_tx = {
 	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
@@ -40,13 +40,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
 
 static struct stedma40_chan_cfg msp1_dma_rx = {
 	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV30_MSP3,
 };
 
 static struct stedma40_chan_cfg msp1_dma_tx = {
 	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV30_MSP1,
 };
 
@@ -58,13 +58,13 @@ struct msp_i2s_platform_data msp1_platform_data = {
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
 	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV14_MSP2,
 };
 
 static struct stedma40_chan_cfg msp2_dma_tx = {
 	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV14_MSP2,
 	.use_fixed_channel = true,
 	.phy_channel = 1,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 553ace6..381acd0 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -63,13 +63,13 @@ static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 #endif
@@ -128,13 +128,13 @@ void mop500_sdi_tc35892_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 #endif
@@ -159,13 +159,13 @@ struct mmci_platform_data mop500_sdi1_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type =  DB8500_DMA_DEV28_SD_MM2,
 };
 
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV28_SD_MM2,
 };
 #endif
@@ -191,13 +191,13 @@ struct mmci_platform_data mop500_sdi2_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type =  DB8500_DMA_DEV42_SD_MM4,
 };
 
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV42_SD_MM4,
 };
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 3866fa8..65abf8d 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -451,19 +451,19 @@ void mop500_snowball_ethernet_clock_enable(void)
 
 static struct cryp_platform_data u8500_cryp1_platform_data = {
 		.mem_to_engine = {
-				.dir = STEDMA40_MEM_TO_PERIPH,
+				.dir = DMA_MEM_TO_DEV,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
 				.mode = STEDMA40_MODE_LOGICAL,
 		},
 		.engine_to_mem = {
-				.dir = STEDMA40_PERIPH_TO_MEM,
+				.dir = DMA_DEV_TO_MEM,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
 				.mode = STEDMA40_MODE_LOGICAL,
 		}
 };
 
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
-		.dir = STEDMA40_MEM_TO_PERIPH,
+		.dir = DMA_MEM_TO_DEV,
 		.dev_type = DB8500_DMA_DEV50_HAC1_TX,
 		.mode = STEDMA40_MODE_LOGICAL,
 };
@@ -481,13 +481,13 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV8_SSP0,
 };
 
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV8_SSP0,
 };
 #endif
@@ -516,37 +516,37 @@ static void __init mop500_spi_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV11_UART2,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV11_UART2,
 };
 #endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index e6c4a05..88e0a77 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -14,12 +14,12 @@
 
 #define MUSB_DMA40_RX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
-		.dir = STEDMA40_PERIPH_TO_MEM, \
+		.dir = DMA_DEV_TO_MEM, \
 	}
 
 #define MUSB_DMA40_TX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
-		.dir = STEDMA40_MEM_TO_PERIPH, \
+		.dir = DMA_MEM_TO_DEV, \
 	}
 
 static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:42 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:42 +0100
Subject: [PATCH 56/63] ARM: ux500: Remove recently unused stedma40_xfer_dir
 enums
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-57-git-send-email-lee.jones@linaro.org>

We're now using the transfer direction definitions provided by the DMA
sub-system, so the home-brew ones have become obsolete.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/platform_data/dma-ste-dma40.h |   10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 288dc24..54ddca6 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -77,14 +77,6 @@ enum stedma40_periph_data_width {
 	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
 };
 
-enum stedma40_xfer_dir {
-	STEDMA40_MEM_TO_MEM = 1,
-	STEDMA40_MEM_TO_PERIPH,
-	STEDMA40_PERIPH_TO_MEM,
-	STEDMA40_PERIPH_TO_PERIPH
-};
-
-
 /**
  * struct stedma40_half_channel_info - dst/src channel configuration
  *
@@ -120,7 +112,7 @@ struct stedma40_half_channel_info {
  *
  */
 struct stedma40_chan_cfg {
-	enum stedma40_xfer_dir			 dir;
+	enum dma_transfer_direction		 dir;
 	bool					 high_priority;
 	bool					 realtime;
 	enum stedma40_mode			 mode;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:43 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:43 +0100
Subject: [PATCH 57/63] dmaengine: ste_dma40_ll: Use the BIT macro to replace
 ugly '(1 << x)'s
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-58-git-send-email-lee.jones@linaro.org>

The aim is to make the code that little more readable.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40_ll.c |   44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 121c0ce..5ddd724 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -20,28 +20,28 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 	/* src is mem? -> increase address pos */
 	if (cfg->dir ==  DMA_MEM_TO_DEV ||
 	    cfg->dir ==  DMA_MEM_TO_MEM)
-		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
+		l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
 
 	/* dst is mem? -> increase address pos */
 	if (cfg->dir ==  DMA_DEV_TO_MEM ||
 	    cfg->dir ==  DMA_MEM_TO_MEM)
-		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
+		l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
 
 	/* src is hw? -> master port 1 */
 	if (cfg->dir ==  DMA_DEV_TO_MEM ||
 	    cfg->dir ==  DMA_DEV_TO_DEV)
-		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
+		l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
 
 	/* dst is hw? -> master port 1 */
 	if (cfg->dir ==  DMA_MEM_TO_DEV ||
 	    cfg->dir ==  DMA_DEV_TO_DEV)
-		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
+		l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
 
-	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
+	l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
 	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
 	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
 
-	l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
+	l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
 	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
 	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
 
@@ -58,39 +58,39 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 	if ((cfg->dir == DMA_DEV_TO_MEM) ||
 	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
-		src |= 1 << D40_SREG_CFG_MST_POS;
+		src |= BIT(D40_SREG_CFG_MST_POS);
 		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
 
 		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
+			src |= BIT(D40_SREG_CFG_PHY_TM_POS);
 		else
 			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
 	}
 	if ((cfg->dir == DMA_MEM_TO_DEV) ||
 	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
-		dst |= 1 << D40_SREG_CFG_MST_POS;
+		dst |= BIT(D40_SREG_CFG_MST_POS);
 		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
 
 		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
+			dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
 		else
 			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
 	}
 	/* Interrupt on end of transfer for destination */
-	dst |= 1 << D40_SREG_CFG_TIM_POS;
+	dst |= BIT(D40_SREG_CFG_TIM_POS);
 
 	/* Generate interrupt on error */
-	src |= 1 << D40_SREG_CFG_EIM_POS;
-	dst |= 1 << D40_SREG_CFG_EIM_POS;
+	src |= BIT(D40_SREG_CFG_EIM_POS);
+	dst |= BIT(D40_SREG_CFG_EIM_POS);
 
 	/* PSIZE */
 	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
-		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
 		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
 	}
 	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
-		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
 		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
 	}
 
@@ -100,14 +100,14 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 
 	/* Set the priority bit to high for the physical channel */
 	if (cfg->high_priority) {
-		src |= 1 << D40_SREG_CFG_PRI_POS;
-		dst |= 1 << D40_SREG_CFG_PRI_POS;
+		src |= BIT(D40_SREG_CFG_PRI_POS);
+		dst |= BIT(D40_SREG_CFG_PRI_POS);
 	}
 
 	if (cfg->src_info.big_endian)
-		src |= 1 << D40_SREG_CFG_LBE_POS;
+		src |= BIT(D40_SREG_CFG_LBE_POS);
 	if (cfg->dst_info.big_endian)
-		dst |= 1 << D40_SREG_CFG_LBE_POS;
+		dst |= BIT(D40_SREG_CFG_LBE_POS);
 
 	*src_cfg = src;
 	*dst_cfg = dst;
@@ -157,15 +157,15 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 
 	/* If this scatter list entry is the last one, no next link */
 	if (next_lli == 0)
-		lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
+		lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
 	else
 		lli->reg_lnk = next_lli;
 
 	/* Set/clear interrupt generation on this link item.*/
 	if (term_int)
-		lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
+		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
 	else
-		lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
+		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
 
 	/* Post link */
 	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:45 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:45 +0100
Subject: [PATCH 59/63] dmaengine: ste_dma40_ll: Replace meaningless register
 set with comment
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-60-git-send-email-lee.jones@linaro.org>

Unsure of the author's intentions, rather than just removing the nop,
we're replacing it with a comment containing the possible intention
of the statement OR:ing with 0.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40_ll.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index a035dfe..27b818d 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -182,8 +182,10 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 	else
 		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
 
-	/* Post link */
-	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
+	/*
+	 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
+	 * Relink happens after transfer completion.
+	 */
 
 	return 0;
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:41 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:41 +0100
Subject: [PATCH 55/63] dmaengine: ste_dma40: Replace ST-E's home-brew DMA
 direction defs with generic ones
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-56-git-send-email-lee.jones@linaro.org>

STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c    |   56 ++++++++++++++++++++++----------------------
 drivers/dma/ste_dma40_ll.c |   24 +++++++++----------
 2 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 8e7fa9d..78aeaa7 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -64,7 +64,7 @@ static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
 /* Default configuration for physcial memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 	.mode = STEDMA40_MODE_PHYSICAL,
-	.dir = STEDMA40_MEM_TO_MEM,
+	.dir = DMA_MEM_TO_MEM,
 
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.src_info.psize = STEDMA40_PSIZE_PHY_1,
@@ -78,7 +78,7 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 /* Default configuration for logical memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_MEM,
+	.dir = DMA_MEM_TO_MEM,
 
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.src_info.psize = STEDMA40_PSIZE_LOG_1,
@@ -829,7 +829,7 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
 		 * that uses linked lists.
 		 */
 		if (!(chan->phy_chan->use_soft_lli &&
-			chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM))
+			chan->dma_cfg.dir == DMA_DEV_TO_MEM))
 			curr_lcla = d40_lcla_alloc_one(chan, desc);
 
 		first_lcla = curr_lcla;
@@ -1297,12 +1297,12 @@ static void d40_config_set_event(struct d40_chan *d40c,
 	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
 
 	/* Enable event line connected to device (or memcpy) */
-	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+	if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
+	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
 		__d40_config_set_event(d40c, event_type, event,
 				       D40_CHAN_REG_SSLNK);
 
-	if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM)
+	if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
 		__d40_config_set_event(d40c, event_type, event,
 				       D40_CHAN_REG_SDLNK);
 }
@@ -1760,7 +1760,7 @@ static int d40_validate_conf(struct d40_chan *d40c,
 		res = -EINVAL;
 	}
 
-	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
+	if (conf->dir == DMA_DEV_TO_DEV) {
 		/*
 		 * DMAC HW supports it. Will be added to this driver,
 		 * in case any dma client requires it.
@@ -1891,11 +1891,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
 	phys = d40c->base->phy_res;
 	num_phy_chans = d40c->base->num_phy_chans;
 
-	if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
+	if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
 		log_num = 2 * dev_type;
 		is_src = true;
-	} else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-		   d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+	} else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+		   d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
 		/* dst event lines are used for logical memcpy */
 		log_num = 2 * dev_type + 1;
 		is_src = false;
@@ -1906,7 +1906,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
 	event_line = D40_TYPE_TO_EVENT(dev_type);
 
 	if (!is_log) {
-		if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+		if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
 			/* Find physical half channel */
 			if (d40c->dma_cfg.use_fixed_channel) {
 				i = d40c->dma_cfg.phy_channel;
@@ -2054,10 +2054,10 @@ static int d40_free_dma(struct d40_chan *d40c)
 		return -EINVAL;
 	}
 
-	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
+	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
 		is_src = false;
-	else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+	else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
 		is_src = true;
 	else {
 		chan_err(d40c, "Unknown direction\n");
@@ -2119,10 +2119,10 @@ static bool d40_is_paused(struct d40_chan *d40c)
 		goto _exit;
 	}
 
-	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
 		status = readl(chanbase + D40_CHAN_REG_SDLNK);
-	} else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
+	} else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
 		status = readl(chanbase + D40_CHAN_REG_SSLNK);
 	} else {
 		chan_err(d40c, "Unknown direction\n");
@@ -2373,12 +2373,12 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
 	if (d40c->base->rev < 3)
 		return;
 
-	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+	if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
+	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
 
-	if ((d40c->dma_cfg.dir ==  STEDMA40_MEM_TO_PERIPH) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+	if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
+	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
 }
 
@@ -2409,11 +2409,11 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
 
 	switch (D40_DT_FLAGS_DIR(flags)) {
 	case 0:
-		cfg.dir = STEDMA40_MEM_TO_PERIPH;
+		cfg.dir = DMA_MEM_TO_DEV;
 		cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
 		break;
 	case 1:
-		cfg.dir = STEDMA40_PERIPH_TO_MEM;
+		cfg.dir = DMA_DEV_TO_MEM;
 		cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
 		break;
 	}
@@ -2459,7 +2459,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	d40_set_prio_realtime(d40c);
 
 	if (chan_is_logical(d40c)) {
-		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+		if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
 			d40c->lcpa = d40c->base->lcpa_base +
 				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
 		else
@@ -2732,12 +2732,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	if (config->direction == DMA_DEV_TO_MEM) {
 		config_addr = config->src_addr;
 
-		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
+		if (cfg->dir != DMA_DEV_TO_MEM)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for peripheral "
 				"to memory transfer (%d) overriding\n",
 				cfg->dir);
-		cfg->dir = STEDMA40_PERIPH_TO_MEM;
+		cfg->dir = DMA_DEV_TO_MEM;
 
 		/* Configure the memory side */
 		if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
@@ -2748,12 +2748,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	} else if (config->direction == DMA_MEM_TO_DEV) {
 		config_addr = config->dst_addr;
 
-		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
+		if (cfg->dir != DMA_MEM_TO_DEV)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for memory "
 				"to peripheral transfer (%d) overriding\n",
 				cfg->dir);
-		cfg->dir = STEDMA40_MEM_TO_PERIPH;
+		cfg->dir = DMA_MEM_TO_DEV;
 
 		/* Configure the memory side */
 		if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index ab5a2a7..121c0ce 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -18,23 +18,23 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 	u32 l1 = 0; /* src */
 
 	/* src is mem? -> increase address pos */
-	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
-	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
+	if (cfg->dir ==  DMA_MEM_TO_DEV ||
+	    cfg->dir ==  DMA_MEM_TO_MEM)
 		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
 
 	/* dst is mem? -> increase address pos */
-	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
-	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
+	if (cfg->dir ==  DMA_DEV_TO_MEM ||
+	    cfg->dir ==  DMA_MEM_TO_MEM)
 		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
 
 	/* src is hw? -> master port 1 */
-	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
-	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
+	if (cfg->dir ==  DMA_DEV_TO_MEM ||
+	    cfg->dir ==  DMA_DEV_TO_DEV)
 		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
 
 	/* dst is hw? -> master port 1 */
-	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
-	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
+	if (cfg->dir ==  DMA_MEM_TO_DEV ||
+	    cfg->dir ==  DMA_DEV_TO_DEV)
 		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
 
 	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
@@ -55,8 +55,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 	u32 src = 0;
 	u32 dst = 0;
 
-	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+	if ((cfg->dir == DMA_DEV_TO_MEM) ||
+	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
 		src |= 1 << D40_SREG_CFG_MST_POS;
 		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
@@ -66,8 +66,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 		else
 			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
 	}
-	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
-	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+	if ((cfg->dir == DMA_MEM_TO_DEV) ||
+	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
 		dst |= 1 << D40_SREG_CFG_MST_POS;
 		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
-- 
1.7.10.4



From linus.walleij at linaro.org  Fri May  3 10:35:28 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 16:35:28 +0200
Subject: [PATCH 3/5] gpio/omap: Add DT support to GPIO driver
In-Reply-To: <517AF0C1.60009@ti.com>
References: <1329321854-24490-1-git-send-email-b-cousson@ti.com>
 <515319D5.20105@wwwdotorg.org>
 <CACRpkdYXVLgCz1Tyu-Ls2V2OTc4R3cGNJhfQJB6Hiz_K9dkZYQ@mail.gmail.com>
 <5155C902.7080207@wwwdotorg.org>
 <CACRpkdYbs4-uudpRUY8e+7icYYkZrfM0kReP3pLL5DMiURJ4dg@mail.gmail.com>
 <5165CB9D.1090202@wwwdotorg.org>
 <CACRpkdYirFNqmGhA4K9CL4ve4NYhs8Rd3SFt1iwW9vHBkrcz8g@mail.gmail.com>
 <51671D7B.5060303@wwwdotorg.org>
 <CACRpkdbf32Ef77GmXk9id9+RRjcDRTr7S+F4nznoeZU8y=BT_Q@mail.gmail.com>
 <51673D70.3010503@wwwdotorg.org>
 <CAAwP0s0e2x33jZQhFRY+Hoo61SFqYKRgWk=1mL2+DNxSDJHz+A@mail.gmail.com>
 <CACRpkda4h+qXTvsirPAS7E7sjXhMLE62q=VDy53W8UchsYjbNg@mail.gmail.com>
 <516C31C3.9040505@wwwdotorg.org> <516C7C43.3040105@wwwdotorg.org>
 <516C8760.2050500@ti.com> <516D9B05.1000501@wwwdotorg.org>
 <516DA60A.5070000@ti.com> <516DCCA8.3070108@wwwdotorg.org>
 <516DDB4D.9020500@ti.com> <516EC2AF.9090905@wwwdotorg.org>
 <CACRpkdaOOrooK7kff2Y-7gH6L6m-MsiU7PfHnqBkPpc=tk_iWA@mail.gmail.com>
 <517AF0C1.60009@ti.com>
Message-ID: <CACRpkdbSjKaeAreG02Q4c3bZ3-Zzg6d=qUKfm4WTQKWsX8B_Xg@mail.gmail.com>

On Fri, Apr 26, 2013 at 11:25 PM, Jon Hunter <jon-hunter at ti.com> wrote:
> On 04/26/2013 02:27 AM, Linus Walleij wrote:

>> You will just have to give the xlate function information about which
>> GPIOs are used as IRQs only, and only request the GPIO on these.
>
> That should not be necessary. The xlate is only called in the case where
> the gpio controller is declared as the interrupt controller in the
> device tree source ...

Sorry I don't understand this. Irqdomains are not device tree
concepts. Why would it only be called if it was declared such
or such in the device tree?

> eth at 0 {
>         compatible = "ks8851";
>         ...
>         interrupt-parent = <&gpio2>;
>         interrupts = <2 8>; /* gpio line 34, low triggered */
>         ...
> };
>
> So in the case where you have a driver call gpio_request() and then
> request_irq(), in the device tree source, the gpio controller will not
> be declared as an interrupt controller. It will just list the gpios ...

And how do you get from there to the conclusion that
gpio_to_irq() will not ever be called, maybe by
some other driver than the ethernet?

> sdhci at c8000200 {
>         ...
>         cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>         wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>         ...
> };

Like if this driver wants to set up an IRQ?

>> It all comes back to this: keep all applicable knowledge in the
>> system, so it can make proper decisions, don't try to create
>> mechanisms that will half-guess things.
>
> Agreed. However the xlate looks like a good place to request the gpio
> without needing to add these "input-hogs" or any other platform code. So
> if this is not considered abuse of the xlate, then it seems like an
> ideal solution. I have been also implementing a generic xlate so that we
> don't need to have a xlate for each platform as well.

I'm still not following. Maybe I'm just too stupid...

How do you *avoid* requesting the GPIO in the translation
for a certain IRQ if the driver first issues gpio_request() and
then goes on to perform gpio_to_irq() itself?

Yours,
Linus Walleij


From lee.jones at linaro.org  Fri May  3 10:32:47 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:47 +0100
Subject: [PATCH 61/63] ARM: ux500: Stop passing DMA platform data though
 AUXDATA
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-62-git-send-email-lee.jones@linaro.org>

The DMA platform data is now empty due to some recent refactoring,
so there is no longer a requirement to pass it though.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index a2c83c2..2b6cbde 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -264,8 +264,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
 		"ux500-msp-i2s.3", &msp3_platform_data),
 	/* Requires clock name bindings and channel address lookup table. */
-	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
-		       "dma40.0", &dma40_plat_data),
+	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
 	{},
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:48 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:48 +0100
Subject: [PATCH 62/63] dmaengine: ste_dma40: Fetch the number of physical
 channels from DT
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-63-git-send-email-lee.jones@linaro.org>

Some platforms insist on obscure physical channel availability. This
information is currently passed though platform data in internal BSP
kernels. Once those platforms land, they'll need to configure them
appropriately, so we may as well add the infrastructure.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index bd5b156..ee96acb 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3468,7 +3468,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
-	int num_memcpy = 0;
+	int num_phy = 0, num_memcpy = 0;
 	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
@@ -3477,6 +3477,11 @@ static int __init d40_of_probe(struct platform_device *pdev,
 	if (!pdata)
 		return -ENOMEM;
 
+	/* If absent this value will be obtained from h/w. */
+	of_property_read_u32(np, "dma-channels", &num_phy);
+	if (num_phy > 0)
+		pdata->num_of_phy_chans = num_phy;
+
 	list = of_get_property(np, "memcpy-channels", &num_memcpy);
 	num_memcpy /= sizeof(*list);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:44 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:44 +0100
Subject: [PATCH 58/63] dmaengine: ste_dma40: Convert data_width from register
 bit format to value
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-59-git-send-email-lee.jones@linaro.org>

When a DMA client requests and configures a DMA channel, it requests
data_width in Bytes. The DMA40 driver then swiftly converts it over to
the necessary register bit value. Unfortunately, for any subsequent
calculations we have to shift '1' by the bit pattern (1 << data_width)
times to make any sense of it.

This patch flips the semantics on its head and only converts the value
to its respective register bit pattern when writing to registers. This
way we can use the true data_width (in Bytes) value.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c                     |   63 +++++++++++----------------
 drivers/dma/ste_dma40_ll.c                  |   43 ++++++++++++------
 include/linux/platform_data/dma-ste-dma40.h |    9 +---
 sound/soc/ux500/ux500_pcm.c                 |   10 ++---
 4 files changed, 60 insertions(+), 65 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 78aeaa7..552a534 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -66,11 +66,11 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 	.mode = STEDMA40_MODE_PHYSICAL,
 	.dir = DMA_MEM_TO_MEM,
 
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.src_info.psize = STEDMA40_PSIZE_PHY_1,
 	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.dst_info.psize = STEDMA40_PSIZE_PHY_1,
 	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 };
@@ -80,11 +80,11 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = DMA_MEM_TO_MEM,
 
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.src_info.psize = STEDMA40_PSIZE_LOG_1,
 	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
 	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 };
@@ -991,20 +991,21 @@ static int d40_psize_2_burst_size(bool is_log, int psize)
 
 /*
  * The dma only supports transmitting packages up to
- * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
- * dma elements required to send the entire sg list
+ * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
+ *
+ * Calculate the total number of dma elements required to send the entire sg list.
  */
 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
 {
 	int dmalen;
 	u32 max_w = max(data_width1, data_width2);
 	u32 min_w = min(data_width1, data_width2);
-	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
 
 	if (seg_max > STEDMA40_MAX_SEG_SIZE)
-		seg_max -= (1 << max_w);
+		seg_max -= max_w;
 
-	if (!IS_ALIGNED(size, 1 << max_w))
+	if (!IS_ALIGNED(size, max_w))
 		return -EINVAL;
 
 	if (size <= seg_max)
@@ -1450,7 +1451,7 @@ static u32 d40_residue(struct d40_chan *d40c)
 			  >> D40_SREG_ELEM_PHY_ECNT_POS;
 	}
 
-	return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
+	return num_elt * d40c->dma_cfg.dst_info.data_width;
 }
 
 static bool d40_tx_is_linked(struct d40_chan *d40c)
@@ -1770,9 +1771,9 @@ static int d40_validate_conf(struct d40_chan *d40c,
 	}
 
 	if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
-	    (1 << conf->src_info.data_width) !=
+	    conf->src_info.data_width !=
 	    d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
-	    (1 << conf->dst_info.data_width)) {
+	    conf->dst_info.data_width) {
 		/*
 		 * The DMAC hardware only supports
 		 * src (burst x width) == dst (burst x width)
@@ -2659,33 +2660,10 @@ static void d40_terminate_all(struct dma_chan *chan)
 static int
 dma40_config_to_halfchannel(struct d40_chan *d40c,
 			    struct stedma40_half_channel_info *info,
-			    enum dma_slave_buswidth width,
 			    u32 maxburst)
 {
-	enum stedma40_periph_data_width addr_width;
 	int psize;
 
-	switch (width) {
-	case DMA_SLAVE_BUSWIDTH_1_BYTE:
-		addr_width = STEDMA40_BYTE_WIDTH;
-		break;
-	case DMA_SLAVE_BUSWIDTH_2_BYTES:
-		addr_width = STEDMA40_HALFWORD_WIDTH;
-		break;
-	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		addr_width = STEDMA40_WORD_WIDTH;
-		break;
-	case DMA_SLAVE_BUSWIDTH_8_BYTES:
-		addr_width = STEDMA40_DOUBLEWORD_WIDTH;
-		break;
-	default:
-		dev_err(d40c->base->dev,
-			"illegal peripheral address width "
-			"requested (%d)\n",
-			width);
-		return -EINVAL;
-	}
-
 	if (chan_is_logical(d40c)) {
 		if (maxburst >= 16)
 			psize = STEDMA40_PSIZE_LOG_16;
@@ -2706,7 +2684,6 @@ dma40_config_to_halfchannel(struct d40_chan *d40c,
 			psize = STEDMA40_PSIZE_PHY_1;
 	}
 
-	info->data_width = addr_width;
 	info->psize = psize;
 	info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
 
@@ -2790,14 +2767,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 		src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
 	}
 
+	/* Only valid widths are; 1, 2, 4 and 8. */
+	if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
+	    src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
+	    dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
+	    dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
+	    ((src_addr_width > 1) && (src_addr_width & 1)) ||
+	    ((dst_addr_width > 1) && (dst_addr_width & 1)))
+		return -EINVAL;
+
+	cfg->src_info.data_width = src_addr_width;
+	cfg->dst_info.data_width = dst_addr_width;
+
 	ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
-					  src_addr_width,
 					  src_maxburst);
 	if (ret)
 		return ret;
 
 	ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
-					  dst_addr_width,
 					  dst_maxburst);
 	if (ret)
 		return ret;
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 5ddd724..a035dfe 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -10,6 +10,18 @@
 
 #include "ste_dma40_ll.h"
 
+u8 d40_width_to_bits(enum dma_slave_buswidth width)
+{
+	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+		return STEDMA40_ESIZE_8_BIT;
+	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+		return STEDMA40_ESIZE_16_BIT;
+	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
+		return STEDMA40_ESIZE_64_BIT;
+	else
+		return STEDMA40_ESIZE_32_BIT;
+}
+
 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 		 u32 *lcsp1, u32 *lcsp3)
@@ -39,11 +51,13 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 
 	l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
 	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
-	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
+	l3 |= d40_width_to_bits(cfg->dst_info.data_width)
+		<< D40_MEM_LCSP3_DCFG_ESIZE_POS;
 
 	l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
 	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
-	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
+	l1 |= d40_width_to_bits(cfg->src_info.data_width)
+		<< D40_MEM_LCSP1_SCFG_ESIZE_POS;
 
 	*lcsp1 = l1;
 	*lcsp3 = l3;
@@ -95,8 +109,10 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 	}
 
 	/* Element size */
-	src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
-	dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
+	src |= d40_width_to_bits(cfg->src_info.data_width)
+		<< D40_SREG_CFG_ESIZE_POS;
+	dst |= d40_width_to_bits(cfg->dst_info.data_width)
+		<< D40_SREG_CFG_ESIZE_POS;
 
 	/* Set the priority bit to high for the physical channel */
 	if (cfg->high_priority) {
@@ -133,23 +149,22 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 		num_elems = 2 << psize;
 
 	/* Must be aligned */
-	if (!IS_ALIGNED(data, 0x1 << data_width))
+	if (!IS_ALIGNED(data, data_width))
 		return -EINVAL;
 
 	/* Transfer size can't be smaller than (num_elms * elem_size) */
-	if (data_size < num_elems * (0x1 << data_width))
+	if (data_size < num_elems * data_width)
 		return -EINVAL;
 
 	/* The number of elements. IE now many chunks */
-	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
+	lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
 
 	/*
 	 * Distance to next element sized entry.
 	 * Usually the size of the element unless you want gaps.
 	 */
 	if (addr_inc)
-		lli->reg_elt |= (0x1 << data_width) <<
-			D40_SREG_ELEM_PHY_EIDX_POS;
+		lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
 
 	/* Where the data is */
 	lli->reg_ptr = data;
@@ -177,16 +192,16 @@ static int d40_seg_size(int size, int data_width1, int data_width2)
 {
 	u32 max_w = max(data_width1, data_width2);
 	u32 min_w = min(data_width1, data_width2);
-	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
 
 	if (seg_max > STEDMA40_MAX_SEG_SIZE)
-		seg_max -= (1 << max_w);
+		seg_max -= max_w;
 
 	if (size <= seg_max)
 		return size;
 
 	if (size <= 2 * seg_max)
-		return ALIGN(size / 2, 1 << max_w);
+		return ALIGN(size / 2, max_w);
 
 	return seg_max;
 }
@@ -352,10 +367,10 @@ static void d40_log_fill_lli(struct d40_log_lli *lli,
 	lli->lcsp13 = reg_cfg;
 
 	/* The number of elements to transfer */
-	lli->lcsp02 = ((data_size >> data_width) <<
+	lli->lcsp02 = ((data_size / data_width) <<
 		       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
 
-	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
+	BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
 
 	/* 16 LSBs address of the current element */
 	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 54ddca6..ceba6dc 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
 	STEDMA40_FLOW_CTRL,
 };
 
-enum stedma40_periph_data_width {
-	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
-	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
-	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
-	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
-};
-
 /**
  * struct stedma40_half_channel_info - dst/src channel configuration
  *
@@ -87,7 +80,7 @@ enum stedma40_periph_data_width {
  */
 struct stedma40_half_channel_info {
 	bool big_endian;
-	enum stedma40_periph_data_width data_width;
+	enum dma_slave_buswidth data_width;
 	int psize;
 	enum stedma40_flow_ctrl flow_ctrl;
 };
diff --git a/sound/soc/ux500/ux500_pcm.c b/sound/soc/ux500/ux500_pcm.c
index 846fa82..b897733 100644
--- a/sound/soc/ux500/ux500_pcm.c
+++ b/sound/soc/ux500/ux500_pcm.c
@@ -125,21 +125,21 @@ static int ux500_pcm_open(struct snd_pcm_substream *substream)
 	runtime->hw = (stream_id == SNDRV_PCM_STREAM_PLAYBACK) ?
 		ux500_pcm_hw_playback : ux500_pcm_hw_capture;
 
-	mem_data_width = STEDMA40_HALFWORD_WIDTH;
+	mem_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 
 	dma_params = snd_soc_dai_get_dma_data(dai, substream);
 	switch (dma_params->data_size) {
 	case 32:
-		per_data_width = STEDMA40_WORD_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	case 16:
-		per_data_width = STEDMA40_HALFWORD_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 		break;
 	case 8:
-		per_data_width = STEDMA40_BYTE_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 		break;
 	default:
-		per_data_width = STEDMA40_WORD_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		dev_warn(rtd->platform->dev,
 			"%s: Unknown data-size (%d)! Assuming 32 bits.\n",
 			__func__, dma_params->data_size);
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:49 +0100
Subject: [PATCH 63/63] dmaengine: ste_dma40: Fetch disabled channels from DT
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-64-git-send-email-lee.jones@linaro.org>

Some platforms have channels which are not available for normal use.
This information is currently passed though platform data in internal
BSP kernels. Once those platforms land, they'll need to configure them
appropriately, so we may as well add the infrastructure.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/dma/ste-dma40.txt |    2 ++
 drivers/dma/ste_dma40.c                             |   17 ++++++++++++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index aa272d8..bea5b73 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -11,6 +11,7 @@ Required properties:
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
 		the driver will attempt to obtain the information from H/W
+- disabled-channels: Channels which can not be used
 
 Example:
 
@@ -23,6 +24,7 @@ Example:
 
 		#dma-cells = <2>;
 		memcpy-channels  = <56 57 58 59 60>;
+		disabled-channels  = <12>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index ee96acb..dfe182e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3468,7 +3468,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
-	int num_phy = 0, num_memcpy = 0;
+	int num_phy = 0, num_memcpy = 0, num_disabled = 0;
 	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
@@ -3497,6 +3497,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 				   dma40_memcpy_channels,
 				   num_memcpy);
 
+	list = of_get_property(np, "disabled-channels", &num_disabled);
+	num_disabled /= sizeof(*list);
+
+	if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of disabled channels specified (%d)\n",
+			num_disabled);
+		return -EINVAL;
+	}
+
+	of_property_read_u32_array(np, "disabled-channels",
+				   pdata->disabled_channels,
+				   num_disabled);
+	pdata->disabled_channels[num_disabled] = -1;
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:32:46 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:32:46 +0100
Subject: [PATCH 60/63] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-61-git-send-email-lee.jones@linaro.org>

At this moment in time the memcpy channels which can be used by the D40
are fixed, as each supported platform in Mainline uses the same ones.
However, platforms do exist which don't follow this convention, so
these will need to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/dma/ste-dma40.txt          |    2 +
 drivers/dma/ste_dma40.c                            |   42 +++++++++++++++-----
 include/linux/platform_data/dma-ste-dma40.h        |    2 +
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 2679a87..aa272d8 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -6,6 +6,7 @@ Required properties:
 - reg-names: Names of the above areas to use during resource look-up
 - interrupt: Should contain the DMAC interrupt number
 - #dma-cells: must be <3>
+- memcpy-channels: Channels to be used for memcpy
 
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
@@ -21,6 +22,7 @@ Example:
 		interrupts = <0 25 0x4>;
 
 		#dma-cells = <2>;
+		memcpy-channels  = <56 57 58 59 60>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 552a534..bd5b156 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,8 +58,10 @@
 #define D40_ALLOC_PHY		BIT(30)
 #define D40_ALLOC_LOG_FREE	0
 
+#define D40_MEMCPY_MAX_CHANS	8
+
 /* Reserved event lines for memcpy only. */
-static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
+static int dma40_memcpy_channels[D40_MEMCPY_MAX_CHANS] = { 56, 57, 58, 59, 60 };
 
 /* Default configuration for physcial memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
@@ -508,6 +510,8 @@ struct d40_gen_dmac {
  * @phy_start: Physical memory start of the DMA registers.
  * @phy_size: Size of the DMA register map.
  * @irq: The IRQ number.
+ * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
+ * transfers).
  * @num_phy_chans: The number of physical channels. Read from HW. This
  * is the number of available channels for this driver, not counting "Secure
  * mode" allocated physical channels.
@@ -551,6 +555,7 @@ struct d40_base {
 	phys_addr_t			  phy_start;
 	resource_size_t			  phy_size;
 	int				  irq;
+	int				  num_memcpy_chans;
 	int				  num_phy_chans;
 	int				  num_log_chans;
 	struct device_dma_parameters	  dma_parms;
@@ -2924,7 +2929,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 	}
 
 	d40_chan_init(base, &base->dma_memcpy, base->log_chans,
-		      base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
+		      base->num_log_chans, base->num_memcpy_chans);
 
 	dma_cap_zero(base->dma_memcpy.cap_mask);
 	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3125,6 +3130,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	struct d40_base *base = NULL;
 	int num_log_chans = 0;
 	int num_phy_chans;
+	int num_memcpy_chans;
 	int clk_ret = -EINVAL;
 	int i;
 	u32 pid;
@@ -3195,6 +3201,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	else
 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
 
+	/* The number of channels used for memcpy */
+	if (plat_data->num_of_memcpy_chans)
+		num_memcpy_chans = plat_data->num_of_memcpy_chans;
+	else
+		num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
+
 	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
 
 	dev_info(&pdev->dev,
@@ -3202,7 +3214,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		 rev, res->start, num_phy_chans, num_log_chans);
 
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
-		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
+		       (num_phy_chans + num_log_chans + num_memcpy_chans) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
 
 	if (base == NULL) {
@@ -3212,6 +3224,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 
 	base->rev = rev;
 	base->clk = clk;
+	base->num_memcpy_chans = num_memcpy_chans;
 	base->num_phy_chans = num_phy_chans;
 	base->num_log_chans = num_log_chans;
 	base->phy_start = res->start;
@@ -3455,12 +3468,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
- 
-	/*
-	 * FIXME: Fill in this routine as more support is added.
-	 * First platform enabled (u8500) doens't need any extra
-	 * properties to run, so this is fairly sparce currently.
-	 */
+	int num_memcpy = 0;
+	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
 			     sizeof(struct stedma40_platform_data),
@@ -3468,6 +3477,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 	if (!pdata)
 		return -ENOMEM;
 
+	list = of_get_property(np, "memcpy-channels", &num_memcpy);
+	num_memcpy /= sizeof(*list);
+
+	if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of memcpy channels specified (%d)\n",
+			num_memcpy);
+		return -EINVAL;
+	}
+	pdata->num_of_memcpy_chans = num_memcpy;
+
+	of_property_read_u32_array(np, "memcpy-channels",
+				   dma40_memcpy_channels,
+				   num_memcpy);
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index ceba6dc..1bb9b18 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
  * @num_of_soft_lli_chans: The number of channels that needs to be configured
  * to use SoftLLI.
  * @use_esram_lcla: flag for mapping the lcla into esram region
+ * @num_of_memcpy_chans: The number of channels reserved for memcpy.
  * @num_of_phy_chans: The number of physical channels implemented in HW.
  * 0 means reading the number of channels from DMA HW but this is only valid
  * for 'multiple of 4' channels, like 8.
@@ -141,6 +142,7 @@ struct stedma40_platform_data {
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
 	bool				 use_esram_lcla;
+	int				 num_of_memcpy_chans;
 	int				 num_of_phy_chans;
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May  3 10:31:54 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri,  3 May 2013 15:31:54 +0100
Subject: [PATCH 08/63] dmaengine: ste_dma40: Move default memcpy configs into
 the driver
In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1367591569-32197-9-git-send-email-lee.jones@linaro.org>

There are only two default memcpy configurations used for the DMA40
driver; one for physical memcpy and one for logical memcpy. Instead
of invariably passing the same configurations though platform data,
we're moving them into the driver instead.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/devices-db8500.c        |   28 -----------------------
 drivers/dma/ste_dma40.c                     |   32 +++++++++++++++++++++++++--
 include/linux/platform_data/dma-ste-dma40.h |    4 ----
 3 files changed, 30 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 01cfb68..8b20c91 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,32 +42,6 @@ static struct resource dma40_resources[] = {
 	}
 };
 
-/* Default configuration for physcial memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
-	.mode = STEDMA40_MODE_PHYSICAL,
-	.dir = STEDMA40_MEM_TO_MEM,
-
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.src_info.psize = STEDMA40_PSIZE_PHY_1,
-	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.psize = STEDMA40_PSIZE_PHY_1,
-	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/* Default configuration for logical memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-	.dir = STEDMA40_MEM_TO_MEM,
-
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
-	.src_info.psize = STEDMA40_PSIZE_LOG_1,
-	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
-	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-
 /*
  * Mapping between destination event lines and physical device address.
  * The event line is tied to a device and therefore the address is constant.
@@ -150,8 +124,6 @@ static struct stedma40_platform_data dma40_plat_data = {
 	.dev_len = DB8500_DMA_NR_DEV,
 	.dev_rx = dma40_rx_map,
 	.dev_tx = dma40_tx_map,
-	.memcpy_conf_phy = &dma40_memcpy_conf_phy,
-	.memcpy_conf_log = &dma40_memcpy_conf_log,
 	.disabled_channels = {-1},
 };
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 12de79e..3b83dee 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,6 +58,34 @@
 /* Reserved event lines for memcpy only. */
 static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
 
+/* Default configuration for physcial memcpy */
+struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
+	.mode = STEDMA40_MODE_PHYSICAL,
+	.dir = STEDMA40_MEM_TO_MEM,
+
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.src_info.psize = STEDMA40_PSIZE_PHY_1,
+	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.psize = STEDMA40_PSIZE_PHY_1,
+	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+};
+
+/* Default configuration for logical memcpy */
+struct stedma40_chan_cfg dma40_memcpy_conf_log = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_MEM_TO_MEM,
+
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.src_info.psize = STEDMA40_PSIZE_LOG_1,
+	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
+	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+};
+
 /**
  * enum 40_command - The different commands and/or statuses.
  *
@@ -2015,13 +2043,13 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 	dma_cap_mask_t cap = d40c->chan.device->cap_mask;
 
 	if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
-		d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
+		d40c->dma_cfg = dma40_memcpy_conf_log;
 		d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
 		d40c->dma_cfg.dst_dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
 
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
-		d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
+		d40c->dma_cfg = dma40_memcpy_conf_phy;
 	} else {
 		chan_err(d40c, "No memcpy\n");
 		return -EINVAL;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index a808784..869c571 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -141,8 +141,6 @@ struct stedma40_chan_cfg {
  * @dev_len: length of dev_tx and dev_rx
  * @dev_tx: mapping between destination event line and io address
  * @dev_rx: mapping between source event line and io address
- * @memcpy_conf_phy: default configuration of physical channel memcpy
- * @memcpy_conf_log: default configuration of logical channel memcpy
  * @disabled_channels: A vector, ending with -1, that marks physical channels
  * that are for different reasons not available for the driver.
  * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
@@ -160,8 +158,6 @@ struct stedma40_platform_data {
 	u32				 dev_len;
 	const dma_addr_t		*dev_tx;
 	const dma_addr_t		*dev_rx;
-	struct stedma40_chan_cfg	*memcpy_conf_phy;
-	struct stedma40_chan_cfg	*memcpy_conf_log;
 	int				 disabled_channels[STEDMA40_MAX_PHYS];
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
-- 
1.7.10.4



From arnd at arndb.de  Fri May  3 10:43:47 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 16:43:47 +0200
Subject: [PATCH 1/7] ARM: u300: push down syscon registers
In-Reply-To: <CACRpkdZHRQqd277Qv8O0dek_jYb=eewhpLYfKtip-YLYx_ukUA@mail.gmail.com>
References: <1367511416-4312-1-git-send-email-linus.walleij@stericsson.com>
 <201305021939.48381.arnd@arndb.de>
 <CACRpkdZHRQqd277Qv8O0dek_jYb=eewhpLYfKtip-YLYx_ukUA@mail.gmail.com>
Message-ID: <201305031643.47527.arnd@arndb.de>

On Friday 03 May 2013, Linus Walleij wrote:
> I could do something similar by creating a U300 syscon node
> and referring to it from the clk node, so the clk looks up its
> syscon to find the base.
> 
> If so, I can build this on top of the current patch series
> with multiplatform and all, as I convert the clocks to DT
> (which is the next and final step).

Yes, I think this is a good plan. If there are just two drivers,
that is probably the easiest way to do it. Using the syscon
driver is not very different in the end and avoids mapping the
same physical address range multiple times (having a static mapping
avoids this too), and I'd prefer that if you have more drivers
that need to get to the same registers.

	Arnd


From rostedt at goodmis.org  Fri May  3 11:14:55 2013
From: rostedt at goodmis.org (Steven Rostedt)
Date: Fri, 03 May 2013 11:14:55 -0400
Subject: [PATCH, RFC 14/22] oprofile: always enable IRQ_WORK
In-Reply-To: <20130503115332.GT8356@rric.localhost>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-15-git-send-email-arnd@arndb.de>
 <20130503115332.GT8356@rric.localhost>
Message-ID: <1367594095.7373.14.camel@gandalf.local.home>

On Fri, 2013-05-03 at 13:53 +0200, Robert Richter wrote:
> On 02.05.13 17:16:18, Arnd Bergmann wrote:
> > oprofile fails to build if CONFIG_IRQ_WORK is not already enabled,
> > because of the dependency on the RING_BUFFER code that now uses
> > the irq work library.
> > 
> > kernel/built-in.o: In function `ring_buffer_unlock_commit':
> > :(.text+0x5b8f0): undefined reference to `irq_work_queue'
> > kernel/built-in.o: In function `ring_buffer_write':
> > :(.text+0x5bd10): undefined reference to `irq_work_queue'
> 
> Shouldn't this be fixed in the ring_buffer implementation?

Does this patch fix it?

-- Steve

diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig
index 5e9efd4..015f85a 100644
--- a/kernel/trace/Kconfig
+++ b/kernel/trace/Kconfig
@@ -71,6 +71,7 @@ config TRACE_CLOCK
 config RING_BUFFER
 	bool
 	select TRACE_CLOCK
+	select IRQ_WORK
 
 config FTRACE_NMI_ENTER
        bool
@@ -107,7 +108,6 @@ config TRACING
 	select BINARY_PRINTF
 	select EVENT_TRACING
 	select TRACE_CLOCK
-	select IRQ_WORK
 
 config GENERIC_TRACER
 	bool




From javi.merino at arm.com  Fri May  3 11:17:07 2013
From: javi.merino at arm.com (Javi Merino)
Date: Fri, 3 May 2013 16:17:07 +0100
Subject: [RFC PATCH v2] drivers: bus: add ARM CCI support
In-Reply-To: <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
References: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <20130503151706.GB2756@e102654-lin.cambridge.arm.com>

Hi Lorenzo,

On Wed, May 01, 2013 at 05:18:28PM +0100, Lorenzo Pieralisi wrote:
> On ARM multi-cluster systems coherency between cores running on
> different clusters is managed by the cache-coherent interconnect (CCI).
> It allows broadcasting of TLB invalidates and memory barriers and it
> guarantees cache coherency at system level through snooping of slave
> interfaces connected to it.
> 
> This patch enables the basic infrastructure required in Linux to handle and
> programme the CCI component.
> 
> Non-local variables used by the CCI management functions called by power
> down function calls after disabling the cache must be flushed out to main
> memory in advance, otherwise incoherency of those values may occur if they
> are sitting in the cache of some other CPU when power down functions
> execute. Driver code ensures that relevant data structures are flushed
> from inner and outer caches after the driver probe is completed.
> 
> CCI slave port resources are linked to set of CPUs through bus masters
> phandle properties that link the interface resources to masters node in
> the device tree.
> 
> Documentation describing the CCI DT bindings is provided with the patch.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> ---

[...]

> diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
> new file mode 100644
> index 0000000..0e70942
> --- /dev/null
> +++ b/include/linux/arm-cci.h
> @@ -0,0 +1,59 @@
> +/*
> + * CCI cache coherent interconnect support
> + *
> + * Copyright (C) 2013 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#ifndef __LINUX_ARM_CCI_H
> +#define __LINUX_ARM_CCI_H
> +
> +#include <linux/errno.h>
> +#include <linux/types.h>
> +
> +struct device_node;
> +
> +#ifdef CONFIG_ARM_CCI
> +extern int cci_ace_get_port(struct device_node *dn);
> +extern int cci_disable_port_by_cpu(u64 mpidr);
> +extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
> +extern int __cci_control_port_by_index(u32 port, bool enable);
> +#else
> +static inline int cci_ace_get_port(struct device_node *dn, bool cpu)

Builds with !CONFIG_ARM_CCI fail because this definition of
cci_ace_get_port() takes two arguments whereas the one for
CONFIG_ARM_CCI takes only one.

> +{
> +       return -ENODEV;
> +}
> +static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
> +static inline int __cci_control_port_by_device(struct device_node *dn,
> +                                              bool enable)
> +{
> +       return -ENODEV;
> +}
> +static inline int __cci_control_port_by_index(u32 port, bool enable)
> +{
> +       return -ENODEV;
> +}
> +#endif
> +#define cci_disable_port_by_device(dev) \
> +       __cci_control_port_by_device(dev, false)
> +#define cci_enable_port_by_device(dev) \
> +       __cci_control_port_by_device(dev, true)
> +#define cci_disable_port_by_index(dev) \
> +       __cci_control_port_by_index(dev, false)
> +#define cci_enable_port_by_index(dev) \
> +       __cci_control_port_by_index(dev, true)
> +
> +#endif



From arnd at arndb.de  Fri May  3 11:21:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 17:21:37 +0200
Subject: [PATCH, RFC 04/22] staging/drm: imx: add missing dependencies
In-Reply-To: <20130503021650.GL3442@S2101-09.ap.freescale.net>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-5-git-send-email-arnd@arndb.de>
 <20130503021650.GL3442@S2101-09.ap.freescale.net>
Message-ID: <201305031721.37954.arnd@arndb.de>

On Friday 03 May 2013, Shawn Guo wrote:
> On Thu, May 02, 2013 at 05:16:08PM +0200, Arnd Bergmann wrote:
> > The imx DRM driver needs a couple of extra Kconfig dependencies
> > to avoid random build failures:
> > 
> > drivers/staging/imx-drm/ipuv3-crtc.c:448:
> >  undefined reference to `ipu_idmac_put'
> >  drivers/staging/imx-drm/ipuv3-crtc.c:450: undefined reference to
> >  `ipu_dmfc_put' drivers/staging/imx-drm/ipuv3-crtc.c:452:
> >  undefined reference to `ipu_dp_put'
> >  drivers/staging/imx-drm/ipuv3-crtc.c:454: undefined reference to
> >  `ipu_di_put'
> > drivers/built-in.o: In function `ipu_probe':
> >  :(.text+0x4b4174): undefined reference to `device_reset'
> > drivers/built-in.o: In function `imx_tve_probe':
> >  drivers/staging/imx-drm/imx-tve.c:648: undefined reference to
> >  `devm_regmap_init_mmio_clk'
> > drivers/built-in.o: In function
> >  `imx_pd_connector_get_modes':
> 
> >  drivers/staging/imx-drm/parallel-display.c:78: undefined
> >  reference to `of_get_drm_display_mode'
> 
> There is a patch [1] from Marek fixing this one.
> 
> Shawn
> 
> [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/233449
> 

That patch only addresses one of the four missing dependencies.
I originally had four separate patches, but did not want to
bother everyone with those so I combined them into one.

	Arnd


From jonathan.austin at arm.com  Fri May  3 11:24:51 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 03 May 2013 16:24:51 +0100
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <20130503095547.GD18614@n2100.arm.linux.org.uk>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
 <5182C480.3080001@dawncrow.de> <5183819E.50308@arm.com>
 <20130503095547.GD18614@n2100.arm.linux.org.uk>
Message-ID: <5183D6C3.8090402@arm.com>

Hi Russell,

Thanks for the comments - you're right about the 'switch_tls'
being more appropriate - needed to take a step back to see that.

I've got a few questions, added inline.

Andr?, Assuming I've understood things okay, there's a patch that
uses Russell's asm stuff (with minor modifications, see the questions)
and includes the C-world changes too. Perhaps you could see that it
solves your problem?

On 03/05/13 10:55, Russell King - ARM Linux wrote:
> On Fri, May 03, 2013 at 10:21:34AM +0100, Jonathan Austin wrote:
>>   	.macro set_tls_v6k, tp, tmp1, tmp2
>> -	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
>> -	mov	\tmp1, #0
>> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
>> +	ldrd	\tmp1, \tmp2, [\tp]
>> +	mcr	p15, 0, \tmp1, c13, c0, 3	@ set user r/o TLS register
>> +	mcr	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
> 
> So we're still back at stalling the pipeline with result delays on older
> CPUs?

How much older? This particular bit is v6k specific so I wasn't worrying
too much but I guess I'm missing something?

It's an academic question wrt to this patch now, though, as the version
you show below re-orders to reduce the stalls...

> 
>> +	.endm
>> +
>> +	.macro save_tlsuser_v6k, tp, tmp1, tmp2
>> +	@ TPIDRURW can be updated from userspace, so we have to re-read it
>> +	mrc	p15, 0, \tmp2, c13, c0, 2	@ load user r/w TLS register
>> +	str	\tmp2, [\tp, #4]
>>   	.endm
>>   
>>   	.macro set_tls_v6, tp, tmp1, tmp2
>> @@ -16,15 +25,26 @@
>>   	ldr	\tmp1, [\tmp1, #0]
>>   	mov	\tmp2, #0xffff0fff
>>   	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
>> -	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
>> -	movne	\tmp1, #0
>> -	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
>> -	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
>> +	ldrned	\tmp1, \tmp2, [\tp]
>> +	ldreq	\tmp1, [\tp]
>> +	mcrne	p15, 0, \tmp1, c13, c0, 3	@ yes, set user r/o TLS register
>> +	mcrne	p15, 0, \tmp2, c13, c0, 2	@ set user r/w TLS register
>> +	streq	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> 
> This at least is better.
> 
>> +	.endm
>> +
>> +	.macro save_tlsuser_v6, tp, tmp1, tmp2
>> +	@ TPIDRURW can be updated from userspace, so we have to re-read it
>> +	ldr	\tmp1, =elf_hwcap
>> +	ldr	\tmp1, [\tmp1, #0]
>> +	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> 
> But this isn't - this involves two delays.

Indeed. You left this section untouched in your asm below - was that
because you didn't look at optimising it, or because you thought there
wasn't much better that could be done with it?

As far as I can see, we can't start doing any mcr/mrc operations until we
know for sure that the hw implements them, so this is something we're
stuck with?

Is V6 but not V6k just 1136?

> 
>> +	mrcne	p15, 0, \tmp2, c13, c0, 2	@ read user r/w TLS register
>> +	strne	\tmp2, [\tp, #4]		@ save in to thread_info
>>   	.endm
>>   
>>   	.macro set_tls_software, tp, tmp1, tmp2
>> -	mov	\tmp1, #0xffff0fff
>> -	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
>> +	ldr	\tmp1, [\tp]
>> +	mov	\tmp2, #0xffff0fff
>> +	str	\tmp1, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
>>   	.endm
>>   #endif
>>   
>> @@ -32,18 +52,31 @@
>>   #define tls_emu		1
>>   #define has_tls_reg		1
>>   #define set_tls		set_tls_none
>> +#define save_tlsuser	save_tlsuser_none
>> +#define get_tlsuser	get_tlsuser_none
>>   #elif defined(CONFIG_CPU_V6)
>>   #define tls_emu		0
>>   #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
>>   #define set_tls		set_tls_v6
>> +#define save_tlsuser	save_tlsuser_v6
>> +#define get_tlsuser	get_tlsuser_v6
>>   #elif defined(CONFIG_CPU_32v6K)
>>   #define tls_emu		0
>>   #define has_tls_reg		1
>>   #define set_tls		set_tls_v6k
>> +#define save_tlsuser	save_tlsuser_v6k
>> +#define get_tlsuser	get_tlsuser_v6k
>>   #else
>>   #define tls_emu		0
>>   #define has_tls_reg		0
>>   #define set_tls		set_tls_software
>> +#define save_tlsuser	save_tlsuser_none
>> +#define get_tlsuser	get_tlsuser_none
>>   #endif
> 
> This separation of setting and saving the TLS value is actually quite
> silly.  They're called from the same place, so lets just call it
> "switch_tls" instead.

Agreed. Thanks for the suggestion.

> 
> Here's just the assembly bits doing that - this is totally untested
> of course:
> 
>   arch/arm/include/asm/tls.h   |   28 +++++++++++++++-------------
>   arch/arm/kernel/entry-armv.S |    4 ++--
>   2 files changed, 17 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
> index 73409e6..9c377f1 100644
> --- a/arch/arm/include/asm/tls.h
> +++ b/arch/arm/include/asm/tls.h
> @@ -2,27 +2,29 @@
>   #define __ASMARM_TLS_H
>   
>   #ifdef __ASSEMBLY__

+#include <asm/asm-offsets.h>

required for TI_TP_VALUE

> -	.macro set_tls_none, tp, tmp1, tmp2
> +	.macro switch_tls_none, base, tp, trw, tmp1, tmp2
>   	.endm
>   
> -	.macro set_tls_v6k, tp, tmp1, tmp2
> +	.macro switch_tls_v6k, base, tp, trw, tmp1, tmp2

How do you feel about calling tp and trw something different? tpidro
and tpidrw, or tp and tpuser?

The naming threw me off slightly first time I read this new signature
(tp=thread_pointer/tls_pointer/etc).

> +	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
>   	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
> -	mov	\tmp1, #0
> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> +	mcr	p15, 0, \trw, c13, c0, 2	@ and the user r/w register
> +	str	\tmp2, [\base, #TI_TP_VALUE + 4]@ save it
>   	.endm
>   
> -	.macro set_tls_v6, tp, tmp1, tmp2
> +	.macro switch_tls_v6, base, tp, trw, tmp1, tmp2
>   	ldr	\tmp1, =elf_hwcap
>   	ldr	\tmp1, [\tmp1, #0]
>   	mov	\tmp2, #0xffff0fff
>   	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> -	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> -	movne	\tmp1, #0
> -	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
>   	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> +	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
> +	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> +	mcrne	p15, 0, \trw, c13, c0, 2	@ set user r/w register
> +	strne	\tmp2, [\base, #TI_TP_VALUE + 4]@ save it
>   	.endm
>   
> -	.macro set_tls_software, tp, tmp1, tmp2
> +	.macro switch_tls_software, base, tp, trw, tmp1, tmp2
>   	mov	\tmp1, #0xffff0fff
>   	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
>   	.endm
> @@ -31,19 +33,19 @@
>   #ifdef CONFIG_TLS_REG_EMUL
>   #define tls_emu		1
>   #define has_tls_reg		1
> -#define set_tls		set_tls_none
> +#define switch_tls	switch_tls_none
>   #elif defined(CONFIG_CPU_V6)
>   #define tls_emu		0
>   #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
> -#define set_tls		set_tls_v6
> +#define switch_tls	switch_tls_v6
>   #elif defined(CONFIG_CPU_32v6K)
>   #define tls_emu		0
>   #define has_tls_reg		1
> -#define set_tls		set_tls_v6k
> +#define switch_tls	switch_tls_v6k
>   #else
>   #define tls_emu		0
>   #define has_tls_reg		0
> -#define set_tls		set_tls_software
> +#define switch_tls	switch_tls_software
>   #endif
>   
>   #endif	/* __ASMARM_TLS_H */
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index 0f82098..81a08b1 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -728,15 +728,15 @@ ENTRY(__switch_to)
>    UNWIND(.fnstart	)
>    UNWIND(.cantunwind	)
>   	add	ip, r1, #TI_CPU_SAVE
> -	ldr	r3, [r2, #TI_TP_VALUE]
>    ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
>    THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
>    THUMB(	str	sp, [ip], #4		   )
>    THUMB(	str	lr, [ip], #4		   )
> +	ldrd	r4, r5, [r2, #TI_TP_VALUE]
>   #ifdef CONFIG_CPU_USE_DOMAINS
>   	ldr	r6, [r2, #TI_CPU_DOMAIN]
>   #endif
> -	set_tls	r3, r4, r5
> +	switch_tls r2, r4, r5, r3, r7

Looking at the implementation above and the way you use 'base', I think
that should be 
switch_tls r1, r4, r5, r3, r7
not
switch_tls r2, r4, r5, r3, r7

That way we save tpidrurw in to the old thread pointer not the new one.

>   #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
>   	ldr	r7, [r2, #TI_TASK]
>   	ldr	r8, =__stack_chk_guard
> 
> 

Here's a complete patch including Russell's suggested asm. Tested on
TC2, build-tested for 1136

I think we could drop the extra .c file too - though it is kinda nice
for keeping include/asm/tls.h clean...

----8<------
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f..d90be6d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];	/* TLS registers */
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..39bce5b 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-	.macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+	.macro switch_tls_none, base, tp, trw, tmp1, tmp2
 	.endm
 
-	.macro set_tls_v6k, tp, tmp1, tmp2
+	.macro switch_tls_v6k, base, tp, trw, tmp1, tmp2
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
 	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	mcr	p15, 0, \trw, c13, c0, 2	@ and the user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_v6, tp, tmp1, tmp2
+	.macro switch_tls_v6, base, tp, trw, tmp1, tmp2
 	ldr	\tmp1, =elf_hwcap
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
 	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	mcrne	p15, 0, \trw, c13, c0, 2	@ set user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_software, tp, tmp1, tmp2
+	.macro switch_tls_software, base, tp, trw, tmp1, tmp2
 	mov	\tmp1, #0xffff0fff
 	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
@@ -31,19 +34,28 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
-#define set_tls		set_tls_none
+#define switch_tls	switch_tls_none
+#define get_tlsuser	get_tlsuser_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
-#define set_tls		set_tls_v6
+#define switch_tls	switch_tls_v6
+#define get_tlsuser	get_tlsuser_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
-#define set_tls		set_tls_v6k
+#define switch_tls	switch_tls_v6k
+#define get_tlsuser	get_tlsuser_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
-#define set_tls		set_tls_software
+#define switch_tls	switch_tls_software
+#define get_tlsuser	get_tlsuser_none
 #endif
 
+#ifndef __ASSEMBLY__
+extern unsigned long get_tlsuser_none(void);
+extern unsigned long get_tlsuser_v6(void);
+extern unsigned long get_tlsuser_v6k(void);
+#endif
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..4e1114c 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -17,7 +17,7 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 		   process.o ptrace.o return_address.o sched_clock.o \
-		   setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
+		   setup.o signal.o stacktrace.o sys_arm.o time.o tls.o traps.o
 
 obj-$(CONFIG_ATAGS)		+= atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)	+= atags_proc.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..80f09fe 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,15 +728,15 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
+	ldrd	r4, r5, [r2, #TI_TP_VALUE]
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-	set_tls	r3, r4, r5
+	switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
 	ldr	r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e4..24dbc72 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -395,7 +396,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+		thread->tp_value[0] = childregs->ARM_r3;
+	thread->tp_value[1] = get_tlsuser();
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/tls.c b/arch/arm/kernel/tls.c
new file mode 100644
index 0000000..1627f5b
--- /dev/null
+++ b/arch/arm/kernel/tls.c
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/kernel/tls.c
+ *
+ * Copyright (C) 2013 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <asm/tls.h>
+
+/*
+ * Access to the TPIDRURW register, with full certainty that it exists.
+ */
+unsigned long get_tlsuser_v6k(void)
+{
+	unsigned long v;
+	asm("mrc        p15, 0, %0, c13, c0, 2\n" : "=r" (v));
+	return v;
+}
+
+/*
+ * Access to the TPIDRURW register if it exists.
+ */
+unsigned long get_tlsuser_v6(void)
+{
+	unsigned long v = 0;
+	if (elf_hwcap & HWCAP_TLS)
+		asm("mrc        p15, 0, %0, c13, c0, 2\n" : "=r" (v));
+	return v;
+}
+
+/*
+ * Dummy access for the case that TLS is emulated in software
+ */
+unsigned long get_tlsuser_none(void)
+{
+	return 0;
+}
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c08911..f9d6259 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }




From arnd at arndb.de  Fri May  3 11:24:15 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 17:24:15 +0200
Subject: [PATCH,
 RFC 01/22] can: move CONFIG_HAVE_CAN_FLEXCAN out of CAN_DEV
In-Reply-To: <5183892B.8020400@pengutronix.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-2-git-send-email-arnd@arndb.de>
 <5183892B.8020400@pengutronix.de>
Message-ID: <201305031724.15584.arnd@arndb.de>

On Friday 03 May 2013, Marc Kleine-Budde wrote:
> On 05/02/2013 05:16 PM, Arnd Bergmann wrote:
> > CONFIG_HAVE_CAN_FLEXCAN is a silect symbol that is meant to be selected
> > by platforms that support this driver, but that is not possible without
> > also selecting CAN_DEV, unless we move it out of the "if CAN_DEV"
> > section of the Kconfig file.
> > 
> > warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 &&
> >  IMX_HAVE_PLATFORM_FLEXCAN && SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
> >  which has unmet direct dependencies (NET && CAN && CAN_DEV)
> 
> With the advent of multi platform kernels I like to get rid of
> HAVE_CAN_FLEXCAN completely.

Yes, good idea. Are there any other dependencies we need to add then?
I assume FLEXCAN needs to depend on HAS_IOMEM and OF at least, but
there might be more.

	Arnd


From arnd at arndb.de  Fri May  3 11:29:17 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 17:29:17 +0200
Subject: [PATCH, RFC 09/22] crypto: lz4: don't build on ARM
In-Reply-To: <OF54831661.2286D403-ON49257B5F.00831E7A-49257B5F.00831E7D@lge.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <OF54831661.2286D403-ON49257B5F.00831E7A-49257B5F.00831E7D@lge.com>
Message-ID: <201305031729.17360.arnd@arndb.de>

On Friday 03 May 2013, Chanho Min wrote:
> >It is not currently possible to build the LZ4 code on ARM, so let's
> >remove that option in Kconfig for now.
> >
> >lib/built-in.o: In function `lz4_compress64kctx':
> > lib/lz4/lz4_compress.c:339: undefined reference to `__ctzsi2'
> >lib/built-in.o: In function `lz4_compressctx':
> > lib/lz4/lz4_compress.c:157: undefined reference to `__ctzsi2'
> >lib/built-in.o: In function `lz4hc_commonlength':
> > lib/lz4/lz4hc_compress.c:102: undefined reference to `__ctzsi2'
> > lib/lz4/lz4hc_compress.c:102: undefined reference to `__ctzsi2'
> >lib/built-in.o: In function `lz4hc_insertandgetwidermatch':
> > lib/lz4/lz4hc_compress.c:230: undefined reference to `__ctzsi2'
> 
> Please, let me know the gcc version and tested defconfig.
> I didn't have any problem to build with gcc 4.6.4 on armv7.
> Some architecture need libgcc functions for __builtin_clz/ctz.
> Porting them to lib is in progress:
> http://marc.info/?l=linux-kernel&amp;m=136748861811956&amp;w=2
> But, It doesn't happen on ARM, PowerPC and x86.

I tested with gcc-4.8 and random configurations. I've tried it
again now and can't reproduce it at the moment. I'll try building
more random configurations until I have nailed down the problem.

Sorry about this, I should have been more careful about my
original conclusion here.

	Arnd


From anup at brainfault.org  Fri May  3 11:31:56 2013
From: anup at brainfault.org (Anup Patel)
Date: Fri, 3 May 2013 21:01:56 +0530
Subject: [RFC PATCH 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
In-Reply-To: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <CAAhSdy3s+beJRwh_BzsyHTkjeRFaSm4nac1WFRo6oEWYBQNx_g@mail.gmail.com>

On Fri, May 3, 2013 at 7:32 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> As KVM/arm64 is looming on the horizon, it makes sense to move some
> of the common code to a single location in order to reduce duplication.
>
> The code could live anywhere. Actually, most of KVM is already built
> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
> not exactly talking about style here. But maybe it is time to start
> moving into a less ugly direction.
>
> The include files must be in a "public" location, as they are accessed
> from non-KVM files (arch/arm/kernel/asm-offsets.c).
>
> For this purpose, introduce two new locations:
> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>   virt/kvm, so this could be seen as a (very ugly) precedent.
> - include/kvm/  : there is already an include/xen, and while the
>   intent is slightly different, this seems as good a location as
>   any
>
> Once the code has been moved, it becomes easy to build it in a
> less hackish way, which makes the code easily reusable by KVM/arm64.
>
> Marc Zyngier (2):
>   ARM: KVM: move GIC/timer code to a common location
>   ARM: KVM: standalone Makefile for vgic and timers
>
>  Makefile                                               | 2 +-
>  arch/arm/include/asm/kvm_host.h                        | 4 ++--
>  arch/arm/kvm/Makefile                                  | 5 ++---
>  {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
>  {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
>  virt/Makefile                                          | 1 +
>  virt/kvm/Makefile                                      | 1 +
>  virt/kvm/arm/Makefile                                  | 2 ++
>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
>  10 files changed, 11 insertions(+), 8 deletions(-)
>  rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
>  rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
>  create mode 100644 virt/Makefile
>  create mode 100644 virt/kvm/Makefile
>  create mode 100644 virt/kvm/arm/Makefile
>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
>
> --
> 1.8.2.1
>
>
>
> _______________________________________________
> kvmarm mailing list
> kvmarm at lists.cs.columbia.edu
> https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm

The source files arch/arm/kvm/arm.c and arch/arm/kvm/mmu.c are also
shared between KVM ARM and KVM ARM64.

Can we move these files in virt/arm ?

--Anup


From marc.zyngier at arm.com  Fri May  3 11:55:01 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 03 May 2013 16:55:01 +0100
Subject: [RFC PATCH 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
In-Reply-To: <CAAhSdy3s+beJRwh_BzsyHTkjeRFaSm4nac1WFRo6oEWYBQNx_g@mail.gmail.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <CAAhSdy3s+beJRwh_BzsyHTkjeRFaSm4nac1WFRo6oEWYBQNx_g@mail.gmail.com>
Message-ID: <5183DDD5.6000202@arm.com>

On 03/05/13 16:31, Anup Patel wrote:
> On Fri, May 3, 2013 at 7:32 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> As KVM/arm64 is looming on the horizon, it makes sense to move some
>> of the common code to a single location in order to reduce duplication.
>>
>> The code could live anywhere. Actually, most of KVM is already built
>> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
>> not exactly talking about style here. But maybe it is time to start
>> moving into a less ugly direction.
>>
>> The include files must be in a "public" location, as they are accessed
>> from non-KVM files (arch/arm/kernel/asm-offsets.c).
>>
>> For this purpose, introduce two new locations:
>> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>>   virt/kvm, so this could be seen as a (very ugly) precedent.
>> - include/kvm/  : there is already an include/xen, and while the
>>   intent is slightly different, this seems as good a location as
>>   any
>>
>> Once the code has been moved, it becomes easy to build it in a
>> less hackish way, which makes the code easily reusable by KVM/arm64.
>>
>> Marc Zyngier (2):
>>   ARM: KVM: move GIC/timer code to a common location
>>   ARM: KVM: standalone Makefile for vgic and timers
>>
>>  Makefile                                               | 2 +-
>>  arch/arm/include/asm/kvm_host.h                        | 4 ++--
>>  arch/arm/kvm/Makefile                                  | 5 ++---
>>  {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
>>  {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
>>  virt/Makefile                                          | 1 +
>>  virt/kvm/Makefile                                      | 1 +
>>  virt/kvm/arm/Makefile                                  | 2 ++
>>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
>>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
>>  10 files changed, 11 insertions(+), 8 deletions(-)
>>  rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
>>  rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
>>  create mode 100644 virt/Makefile
>>  create mode 100644 virt/kvm/Makefile
>>  create mode 100644 virt/kvm/arm/Makefile
>>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
>>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
>>
>> --
>> 1.8.2.1
>>
>>
>>
>> _______________________________________________
>> kvmarm mailing list
>> kvmarm at lists.cs.columbia.edu
>> https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
> 
> The source files arch/arm/kvm/arm.c and arch/arm/kvm/mmu.c are also
> shared between KVM ARM and KVM ARM64.
> 
> Can we move these files in virt/arm ?

I suggest we start by finding out if there is an agreement on the
location, method and overall usefulness of this particular patch.

Moving core ARM code around is quite different from sharing what is
basically device emulation stuff.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From s-anna at ti.com  Fri May  3 12:29:32 2013
From: s-anna at ti.com (Suman Anna)
Date: Fri, 3 May 2013 11:29:32 -0500
Subject: [GIT PULL] mailbox driver framework for v3.10 merge window
In-Reply-To: <CAJe_ZhfA=eqihefgtYGmLt03sNV6arme9t1YgzTFoC8nB6SNkQ@mail.gmail.com>
References: <37C860A02101E749A747FA2D3C1E3C504A1971@DLEE11.ent.ti.com>
 <201304091255.03020.arnd@arndb.de>
 <CAJe_Zhf5QwQQU5aVtNhbDT3EK9Dof-ZK_boP9WaNghqO8xY7iA@mail.gmail.com>
 <5182E403.1030808@ti.com>
 <CAJe_ZhfA=eqihefgtYGmLt03sNV6arme9t1YgzTFoC8nB6SNkQ@mail.gmail.com>
Message-ID: <5183E5EC.9040702@ti.com>

On 05/02/2013 09:37 PM, Jassi Brar wrote:
> On 3 May 2013 03:39, Suman Anna <s-anna at ti.com> wrote:
>> Hi Arnd,
>>
>> On 04/28/2013 11:07 PM, Jassi Brar wrote:
>>>
>>> Not to mean only talk and no do, I prepared another proposal that
>>> addressed all the concerns shared so far in the RFC
>>> http://www.spinics.net/lists/kernel/msg1523873.html (its not ready for
>>> primetime yet)  And also converted the PL320 driver to the new API,
>>> unlike the pulled patchset which leaves that out in the cold.
>>> http://www.spinics.net/lists/kernel/msg1523874.html
>>
>> Yes, the current code is mainly interrupt-driven and supports only
>> non-atomic context. We have a need to support atomic contexts and ipc
>> controllers that do not have interrupt-based triggering.
>>
> Supporting poll and client driven TX and atomic context is going to
> need big chunks of changes which we can avoid by doing them already.
> Plus a bottleneck with PL320, as Mark pointed out they can't afford
> any bigger latency, which will come from RX via notifier path.
> 
>> As Jassi
>> pointed out, the RFC is not ready yet and there are still some
>> contention points that needs to be sorted out (especially to maintain
>> OMAP mailbox functionality).
>>
> Apart from a few checkpatch fixes, a missing timer delete call and
> some testing with dummy client and controller drivers for various
> usecases, it's ready from my side. It worked at least as good as your
> API in our internal testing.
> 
> Please do let me know which OMAP functionality are you worried about,
> I believe it could all still be done above this api.

Mainly the splitting of bottom-half responsibility of the controller
driver between mailbox and the client (or another in-between layer
between my existing client (remoteproc driver), because of the support
for only atomic context.

> 
>>>
>>> Now, we could either call it (effectively the TI's framework with
>>> quirks for STE) as the "Common API" and then dismantle and convert it
>>> patch by patch (authors and I seem to agree many things need to be
>>> changed and implemented).
>>>   OR we do it reasonably right the first time even if that means yet
>>> another release. IMHO we should go for slow but steady thing.
>>
>> I think it is your call here, either of the above approaches would
>> definitely involve some rework on the framework as well as both the OMAP
>> & ST mailboxes.
> 
> I am interested to know what changes do you anticipate in my proposed
> API. Not to mean it's perfect, but I thought I provided for all
> practical use-cases.

I will provide feedback on the RFC thread, and we can continue the
discussion on that thread. I will also share the link to my current
work-in-progress branch so that you can see the design approach that I
have taken.

> 
> Yes, TI and STE would need re-work, but then as of now they are their
> own APIs upstream. And even with your proposal they would still need
> to be changed if we are to implement the desired features. What about
> PL320?

The pl320_transmit function is identical to the present
mailbox_msg_send_receive_no_irq, but that is a non-factor anyway since
we would have changed the API.

regards
Suman



From s.hauer at pengutronix.de  Fri May  3 13:04:34 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 May 2013 19:04:34 +0200
Subject: [PATCH v2] ARM: dts: Add SPI support for i.MX27 Phytec PCM038
 module
In-Reply-To: <1367568501-29467-1-git-send-email-shc_work@mail.ru>
References: <1367568501-29467-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130503170434.GV32299@pengutronix.de>

On Fri, May 03, 2013 at 12:08:21PM +0400, Alexander Shiyan wrote:
> Added SPI node and PMIC MC13783 (spi0.0) to imx27-phytec-phycore DT file.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

> ---
>  arch/arm/boot/dts/imx27-phytec-phycore.dts | 109 +++++++++++++++++++++++++++++
>  1 file changed, 109 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
> index fe64e3a..eb7d9fa 100644
> --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
> +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
> @@ -72,6 +72,115 @@
>  	};
>  };
>  
> +&cspi1 {
> +	fsl,spi-num-chipselects = <1>;
> +	cs-gpios = <&gpio4 28 0>;
> +	status = "okay";
> +
> +	pmic: mc13783 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "fsl,mc13783";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <23 0x4>;
> +		fsl,mc13xxx-uses-adc;
> +		fsl,mc13xxx-uses-rtc;
> +
> +		regulators {
> +			sw1a_reg: sw1a {
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <1200000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			sw1b_reg: sw1b {
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <1200000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			sw2a_reg: sw2a {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			sw2b_reg: sw2b {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			sw3_reg: sw3 {
> +				regulator-min-microvolt = <5000000>;
> +				regulator-max-microvolt = <5000000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			vaudio_reg: vaudio {
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			violo_reg: violo {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			viohi_reg: viohi {
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			vgen_reg: vgen {
> +				regulator-min-microvolt = <1500000>;
> +				regulator-max-microvolt = <1500000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			vcam_reg: vcam {
> +				regulator-min-microvolt = <2800000>;
> +				regulator-max-microvolt = <2800000>;
> +			};
> +
> +			vrf1_reg: vrf1 {
> +				regulator-min-microvolt = <2775000>;
> +				regulator-max-microvolt = <2775000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			vrf2_reg: vrf2 {
> +				regulator-min-microvolt = <2775000>;
> +				regulator-max-microvolt = <2775000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +
> +			vmmc1_reg: vmmc1 {
> +				regulator-min-microvolt = <1600000>;
> +				regulator-max-microvolt = <3000000>;
> +			};
> +
> +			gpo1_reg: gpo1 { };
> +
> +			pwgt1spi_reg: pwgt1spi {
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
>  &nfc {
>  	nand-bus-width = <8>;
>  	nand-ecc-mode = "hw";
> -- 
> 1.8.1.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From csd at broadcom.com  Fri May  3 13:13:42 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 3 May 2013 10:13:42 -0700
Subject: [PATCH V2] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <20130503085100.GA6188@mudshark.cambridge.arm.com>
References: <1367542653-955-1-git-send-email-csd@broadcom.com>
 <20130503085100.GA6188@mudshark.cambridge.arm.com>
Message-ID: <5183F046.9020802@broadcom.com>

On 13-05-03 01:51 AM, Will Deacon wrote:
> Hi Christian,
>
> On Fri, May 03, 2013 at 01:57:33AM +0100, Christian Daudt wrote:
>> Rev A2 SoCs have an unorthodox memory re-mapping and this needs
>> to be reflected in the cache operations.
>> This patch adds new outer cache functions for the l2x0 driver
>> to support this SoC revision. It also adds a new compatible
>> value for the cache to enable this functionality.
>>
>> Updates from V1:
>> - remove section 1 altogether and note that in comments
>> - simplify section selection caused by section 1 removal
>> - BUG_ON just in case section 1 shows up
> Looking much better now :)
>
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index c465fac..d70e0ab 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
>>   	}
>>   }
>>   
>> +/*
>> + * For certain Broadcom SoCs, depending on the address range, different offsets
>> + * need to be added to the address before passing it to L2 for
>> + * invalidation/clean/flush
>> + *
>> + * Section Address Range              Offset        EMI
>> + *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
>> + *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
>> + *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
> I don't think you answered last time (or I missed it) but where is the RAM
> in the physical memory map for boards with this L2 controller? Do you
> actually have 3GB at 0x40000000?
There can be up to 1G for VC and 1G for SYS. Usually that translates to 
0x80000000-0xFFFFFFFF

  thanks,
    csd




From will.deacon at arm.com  Fri May  3 13:30:55 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 3 May 2013 18:30:55 +0100
Subject: [PATCH V2] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <5183F046.9020802@broadcom.com>
References: <1367542653-955-1-git-send-email-csd@broadcom.com>
 <20130503085100.GA6188@mudshark.cambridge.arm.com>
 <5183F046.9020802@broadcom.com>
Message-ID: <20130503173055.GA19154@mudshark.cambridge.arm.com>

On Fri, May 03, 2013 at 06:13:42PM +0100, Christian Daudt wrote:
> On 13-05-03 01:51 AM, Will Deacon wrote:
> > On Fri, May 03, 2013 at 01:57:33AM +0100, Christian Daudt wrote:
> >> Rev A2 SoCs have an unorthodox memory re-mapping and this needs
> >> to be reflected in the cache operations.
> >> This patch adds new outer cache functions for the l2x0 driver
> >> to support this SoC revision. It also adds a new compatible
> >> value for the cache to enable this functionality.
> >>
> >> Updates from V1:
> >> - remove section 1 altogether and note that in comments
> >> - simplify section selection caused by section 1 removal
> >> - BUG_ON just in case section 1 shows up
> > Looking much better now :)
> >
> >> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> >> index c465fac..d70e0ab 100644
> >> --- a/arch/arm/mm/cache-l2x0.c
> >> +++ b/arch/arm/mm/cache-l2x0.c
> >> @@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
> >>   	}
> >>   }
> >>   
> >> +/*
> >> + * For certain Broadcom SoCs, depending on the address range, different offsets
> >> + * need to be added to the address before passing it to L2 for
> >> + * invalidation/clean/flush
> >> + *
> >> + * Section Address Range              Offset        EMI
> >> + *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
> >> + *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
> >> + *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
> > I don't think you answered last time (or I missed it) but where is the RAM
> > in the physical memory map for boards with this L2 controller? Do you
> > actually have 3GB at 0x40000000?
> There can be up to 1G for VC and 1G for SYS. Usually that translates to 
> 0x80000000-0xFFFFFFFF

Ok, in which case:

  Reviewed-by: Will Deacon <will.deacon at arm.com>

Will


From will.deacon at arm.com  Fri May  3 13:35:46 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri,  3 May 2013 18:35:46 +0100
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
Message-ID: <1367602547-19322-2-git-send-email-will.deacon@arm.com>

Now that we support a timer-backed delay loop, I'm quickly getting sick
and tired of people complaining that their beloved bogomips value has
decreased. You know who you are!

Unfortunately, we can't just remove the entry from /proc/cpuinfo, as it
will likely break fragile userspace code which is parsing that stuff, so
instead replace it with a dummy value that can be chosen in the Kconfig.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig.debug  | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/setup.c | 16 ++++++++--------
 arch/arm/kernel/smp.c   | 13 ++-----------
 3 files changed, 58 insertions(+), 19 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b31f43..5a0fce1 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -633,4 +633,52 @@ config PID_IN_CONTEXTIDR
 	  additional instructions during context switch. Say Y here only if you
 	  are planning to use hardware trace tools with this kernel.
 
+choice
+	prompt "BogoMIPs setting"
+	default BOGOMIPS_MEDIUM
+	help
+	  The BogoMIPs value reported by Linux is exactly what it sounds
+	  like: totally bogus. It is used to calibrate the delay loop,
+	  which may be backed by a timer clocked completely independently
+	  of the CPU.
+
+	  Unfortunately, that doesn't stop marketing types (and even people
+	  who should know better) from using the number to compare machines
+	  and then screaming if it's less than some fictitious, expected
+	  value.
+
+	  So, this option can be used to avoid the inevitable amount of
+	  pain and suffering you will endure when the chaps described above
+	  start parsing /proc/cpuinfo.
+
+	config BOGOMIPS_SLOW
+		bool "Slow (older machines)"
+		help
+		  If you're comparing a faster machine with a slower machine,
+		  then you might want this option selected on one of them.
+
+	config BOGOMIPS_MEDIUM
+		bool "Medium (default)"
+		help
+		  A BogoMIPS value for the masses.
+
+	config BOGOMIPS_FAST
+		bool "Fast (marketing)"
+		help
+		  Some people believe that software runs faster with this
+		  setting so, if you're one of them, say Y here.
+
+	config BOGOMIPS_RANDOM
+		bool "Random (increased Bogosity)"
+		help
+		  Putting the Bogo back into BogoMIPs.
+endchoice
+
+config BOGOMIPS
+	int
+	default	1 if BOGOMIPS_SLOW
+	default	10000 if BOGOMIPS_MEDIUM
+	default 99999 if BOGOMIPS_FAST
+	default	0
+
 endmenu
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ec04c16..7996a12 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -30,6 +30,7 @@
 #include <linux/compiler.h>
 #include <linux/sort.h>
 #include <linux/debugfs.h>
+#include <linux/random.h>
 
 #include <asm/unified.h>
 #include <asm/cp15.h>
@@ -878,7 +879,7 @@ static const char *hwcap_str[] = {
 static int c_show(struct seq_file *m, void *v)
 {
 	int i, j;
-	u32 cpuid;
+	u32 cpuid, bogomips;
 
 	for_each_online_cpu(i) {
 		/*
@@ -891,15 +892,14 @@ static int c_show(struct seq_file *m, void *v)
 		seq_printf(m, "model name\t: %s rev %d (%s)\n",
 			   cpu_name, cpuid & 15, elf_platform);
 
-#if defined(CONFIG_SMP)
-		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
-			   per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
-			   (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
+#ifdef CONFIG_BOGOMIPS_RANDOM
+		get_random_bytes(&bogomips, sizeof(bogomips));
+		bogomips &= USHRT_MAX;
 #else
-		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
-			   loops_per_jiffy / (500000/HZ),
-			   (loops_per_jiffy / (5000/HZ)) % 100);
+		bogomips = CONFIG_BOGOMIPS;
 #endif
+		seq_printf(m, "BogoMIPS\t: %u.00\n", bogomips);
+
 		/* dump out the processor features */
 		seq_puts(m, "Features\t: ");
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 1f2cccc..8acff93 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -341,17 +341,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
 
 void __init smp_cpus_done(unsigned int max_cpus)
 {
-	int cpu;
-	unsigned long bogosum = 0;
-
-	for_each_online_cpu(cpu)
-		bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
-
-	printk(KERN_INFO "SMP: Total of %d processors activated "
-	       "(%lu.%02lu BogoMIPS).\n",
-	       num_online_cpus(),
-	       bogosum / (500000/HZ),
-	       (bogosum / (5000/HZ)) % 100);
+	printk(KERN_INFO "SMP: Total of %d processors activated.\n",
+	       num_online_cpus());
 
 	hyp_mode_check();
 }
-- 
1.8.2.2



From will.deacon at arm.com  Fri May  3 13:35:45 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri,  3 May 2013 18:35:45 +0100
Subject: [RFC PATCH 0/2] ARM: Remove any correlation between IPC and BogoMips
 value
Message-ID: <1367602547-19322-1-git-send-email-will.deacon@arm.com>

Hi all,

This small patch set may look a little over a month late, but there is a
serious reason for posting it.

When I moved the ARM delay loop over to using the architected timers
rather than the CPU spinning loop (which has all the problems associated
with cpu frequency scaling and what-not) I thought I was doing something
useful for the port. However, it turns out that a surprising number of
people have complained, and continue to complain, about the drop in
their `BogoMIPs score'.

After some education, they usually give in, but I figured it could be
solved by removing the reporting of this number to userspace altogether.
Unfortunately, that affects the output of /proc/cpuinfo, which I'm not
comfortable changing, so instead I've written this slightly tongue-in-cheek
series reporting obviously bogus values in those fields in the hope that
people don't interpret them as anything meaningful.

Comments welcome,

Will


Will Deacon (2):
  ARM: delay: print dummy values for bogomips
  init: calibrate: don't print out bogomips value on boot

 arch/arm/Kconfig.debug  | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/setup.c | 16 ++++++++--------
 arch/arm/kernel/smp.c   | 13 ++-----------
 init/calibrate.c        |  8 +++-----
 4 files changed, 61 insertions(+), 24 deletions(-)

-- 
1.8.2.2



From will.deacon at arm.com  Fri May  3 13:35:47 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri,  3 May 2013 18:35:47 +0100
Subject: [RFC PATCH 2/2] init: calibrate: don't print out bogomips value on
 boot
In-Reply-To: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
Message-ID: <1367602547-19322-3-git-send-email-will.deacon@arm.com>

BogoMIPs is a confusing concept, so allow architectures to print it only
if they find it worthwhile. The delay calibration code should stick to
lpj and avoid trying to draw any correlation with BogoMIPs, which may be
a fixed, bogus (geddit?) value.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 init/calibrate.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/init/calibrate.c b/init/calibrate.c
index fda0a7b..cf48068 100644
--- a/init/calibrate.c
+++ b/init/calibrate.c
@@ -135,13 +135,13 @@ static unsigned long __cpuinit calibrate_delay_direct(void)
 		if ((measured_times[max] - estimate) <
 				(estimate - measured_times[min])) {
 			printk(KERN_NOTICE "calibrate_delay_direct() dropping "
-					"min bogoMips estimate %d = %lu\n",
+					"min delay estimate %d = %lu\n",
 				min, measured_times[min]);
 			measured_times[min] = 0;
 			min = max;
 		} else {
 			printk(KERN_NOTICE "calibrate_delay_direct() dropping "
-					"max bogoMips estimate %d = %lu\n",
+					"max delay estimate %d = %lu\n",
 				max, measured_times[max]);
 			measured_times[max] = 0;
 			max = min;
@@ -292,9 +292,7 @@ void __cpuinit calibrate_delay(void)
 	}
 	per_cpu(cpu_loops_per_jiffy, this_cpu) = lpj;
 	if (!printed)
-		pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
-			lpj/(500000/HZ),
-			(lpj/(5000/HZ)) % 100, lpj);
+		pr_cont("lpj=%lu\n", lpj);
 
 	loops_per_jiffy = lpj;
 	printed = true;
-- 
1.8.2.2



From itooo at itooo.com  Fri May  3 13:48:08 2013
From: itooo at itooo.com (Greg)
Date: Fri, 03 May 2013 19:48:08 +0200
Subject: MVEBU PCI Express support
Message-ID: <5183F858.1050804@itooo.com>

Hello guys,

this one is targeted to the Free Electrons guys : should I start 
investigating by myself or are you planning to release a patch for 
supporting PCI express on Marvell Armada* platforms ?

Cheers,



From linus.walleij at linaro.org  Fri May  3 14:43:42 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 20:43:42 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <2812721.61fsxKBgRj@wuerfel>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1500795.gEuGziRZET@wuerfel>
 <CACRpkdbDNoQSmFAyOMJRHSrnnuqpEfb0U9a7ZeaEztn1dAr_xA@mail.gmail.com>
 <2812721.61fsxKBgRj@wuerfel>
Message-ID: <CACRpkdaUKM1VzDhi3dMRh92XAYgg3KynvdmXKvCLfiCachP1EQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:20 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 03 May 2013 16:06:57 Linus Walleij wrote:
>>
>> Not in my opinion but IIRC in 2008 or so some other
>> subsystem maintainer beat us up for not allowing it
>> to build on every other platform, and the rationale given
>> was that allowin this to build on e.g. x86_64 gives some
>> nice compile coverage.
>>
>> I don't know which argument wins
>
> I know that a certain other Linus frequently complains when ARM specific
> options show up on his x86 machine during "make oldconfig" ;-)

OK let's make it SoC-specific.

> One idea I had is to create a global CONFIG_SOC option that would
> hide all on-chip peripherals when building for a PC-like system.
> On ARM, we would always select CONFIG_SOC, except for a few special
> cases like ARCH_RPC, ARCH_FOOTBRIDGE and ARCH_SHARK.

Sounds like a deal. The AB chips aren't on-chip though
they sit on I2C or SPI actually. But they are still
strongly coupled with the SoC.

I just took a stroll around the premises and found this
Aardvark I2C/SPI "embedded systems interface".

This is a USB thing that makes it possible to connect
any I2C or SPI peripheral to the desktop ... I don't know how
such things should be used with Linux really, it seems like
it's something that normally gets used from userspace by
libusb but in theory we could have a kernel driver for this
and plug in whatever SoC I2C/SPI device into a desktop.

Whatever use it would be ... but could be useful for
developing drivers for a chip outside of the target
system I believe.

Yours,
Linus Walleij


From marc.zyngier at arm.com  Fri May  3 14:55:52 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 03 May 2013 20:55:52 +0200
Subject: MVEBU PCI Express support
In-Reply-To: <5183F858.1050804@itooo.com>
References: <5183F858.1050804@itooo.com>
Message-ID: <da554b46c589eace32e89331bb0c2610@localhost>

On Fri, 03 May 2013 19:48:08 +0200, Greg <itooo at itooo.com> wrote:
> Hello guys,
> 
> this one is targeted to the Free Electrons guys : should I start 
> investigating by myself or are you planning to release a patch for 
> supporting PCI express on Marvell Armada* platforms ?

Reading the mailing list archives is always a good start:
http://www.spinics.net/lists/arm-kernel/msg237063.html

Cheers,

        M.
-- 
Fast, cheap, reliable. Pick two.


From linus.walleij at linaro.org  Fri May  3 15:04:28 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:04:28 +0200
Subject: [GIT PULL] Two ux500 fixes for the v3.10 series
Message-ID: <CACRpkdYeWi2cx2weXao9=2f78eM0_J=gK-8o6gKjcG7pjYFAxA@mail.gmail.com>

Hi ARM SoC folks,

here are two ux500 fixes for the v3.10 series, please pull
them in. Since -rc1 is not out this is based on Torvald's
HEAD from yesterday.

Yours,
Linus Walleij

The following changes since commit ce857229e0c3adc211944a13a5579ef84fd7b4af:

  ipc: fix GETALL/IPC_RM race for sysv semaphores (2013-05-02 19:51:31 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-fixes-for-v3.10-1

for you to fetch changes up to 9b7a2104e7e5dd02210ac26f5dc488ceb29778f7:

  ARM: ux500: Rid ignored return value of regulator_enable() compiler
warning (2013-05-03 10:27:12 +0200)

----------------------------------------------------------------
Two ux500 fixes for the v3.10 series:
- SoC ID fix
- Fix errorpath for proximity regulator

----------------------------------------------------------------
Fabio Baltieri (1):
      ARM: ux500: read the correct soc_id number

Lee Jones (1):
      ARM: ux500: Rid ignored return value of regulator_enable()
compiler warning

 arch/arm/mach-ux500/board-mop500.c | 4 ++--
 arch/arm/mach-ux500/cpu-db8500.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)


From holt at sgi.com  Fri May  3 15:05:14 2013
From: holt at sgi.com (Robin Holt)
Date: Fri, 3 May 2013 14:05:14 -0500
Subject: [PATCH -v7 0/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <20130502180535.GZ14496@n2100.arm.linux.org.uk>
References: <1367428011-17123-1-git-send-email-holt@sgi.com>
 <20130501231347.GT14496@n2100.arm.linux.org.uk>
 <20130502033952.GU3658@sgi.com>
 <20130502180535.GZ14496@n2100.arm.linux.org.uk>
Message-ID: <20130503190514.GH3658@sgi.com>

On Thu, May 02, 2013 at 07:05:35PM +0100, Russell King - ARM Linux wrote:
> On Wed, May 01, 2013 at 10:39:52PM -0500, Robin Holt wrote:
> > On Thu, May 02, 2013 at 12:13:47AM +0100, Russell King - ARM Linux wrote:
> > > On Wed, May 01, 2013 at 12:06:40PM -0500, Robin Holt wrote:
> > > > Andrew, Please do _NOT_ take this patch series yet.  I am sending this
> > > > to you because you had comments on my -v6 submission.
> > > 
> > > Another reason for not applying this is that I believe it wilfully breaks
> > > a bunch of ARM platforms - such as removing the 'g' reboot mode (for gpio
> > > based reboot on PXA), and removing the 's' reboot mode off a bunch of ARM
> > > platforms which have no way to do a hard reboot.
> > 
> > I am not sure what your basis for this statement is.
> 
> Probably old understanding of the code, and me getting old and getting
> forgetful. :(

Russell,

Are you alright with these patches?

Thanks,
Robin


From rjw at sisk.pl  Fri May  3 15:27:12 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Fri, 03 May 2013 21:27:12 +0200
Subject: [PATCH,
 RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <CAKohpon9qmowJ4PmL-nvnoaCzJSC-ZSPv8EUOyoFcTdRqNRwnw@mail.gmail.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <5563691.6kxbXZTjH5@vostro.rjw.lan>
 <CAKohpon9qmowJ4PmL-nvnoaCzJSC-ZSPv8EUOyoFcTdRqNRwnw@mail.gmail.com>
Message-ID: <5824559.D65khaWcvS@vostro.rjw.lan>

On Friday, May 03, 2013 06:31:52 PM Viresh Kumar wrote:
> On 3 May 2013 17:45, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> > In this particular case I think it is OK to make both ARM_DT_BL_CPUFREQ and
> > ARM_BIG_LITTLE_CPUFREQ depend on ARM_CPU_TOPOLOGY, because (in theory?) the
> > latter may be set without the former (unless you want to make ARM_DT_BL_CPUFREQ
> > depend on ARM_BIG_LITTLE_CPUFREQ, but then it may be kind of confusing to
> > users).
> 
> ARM_BIG_LITTLE_CPUFREQ is the core cpufreq code for big LITTLE SoC's and every
> other driver will be a glue providing ops to it. So, ARM_DT_BL_CPUFREQ
> does depend
> on ARM_BIG_LITTLE_CPUFREQ and that's why i added depends on
> ARM_CPU_TOPOLOGY in ARM_BIG_LITTLE_CPUFREQ only and depends on
> ARM_BIG_LITTLE_CPUFREQ in ARM_DT_BL_CPUFREQ.

I'm seeing "select" in there, which is kind of different from "depends on".

> But the problem is if ARM_DT_BL_CPUFREQ isn't selected then we still get
> ARM_DT_BL_CPUFREQ enabled in menuconfig but a warning just before compilation.
> Which Arnd pointed to..

What do you mean by "enabled in menuconfig"?  Does it appear as an option to
select or is it actually selected?

In any case, I'm afraid adding ARM_CPU_TOPOLOGY to the "depends on" list in
ARM_DT_BL_CPUFREQ is the only way to avoid that particular warning.

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From w at 1wt.eu  Fri May  3 15:23:51 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Fri, 3 May 2013 21:23:51 +0200
Subject: MVEBU PCI Express support
In-Reply-To: <5183F858.1050804@itooo.com>
References: <5183F858.1050804@itooo.com>
Message-ID: <20130503192351.GN10563@1wt.eu>

Hi Greg,

On Fri, May 03, 2013 at 07:48:08PM +0200, Greg wrote:
> Hello guys,
> 
> this one is targeted to the Free Electrons guys : should I start 
> investigating by myself or are you planning to release a patch for 
> supporting PCI express on Marvell Armada* platforms ?

Look at their github, there is a patchset for the PCI-express. I
managed to get some NICs and the USB3 controller to work in the 
armada370 using it, I have not tried the armadaXP yet.

Willy



From linus.walleij at linaro.org  Fri May  3 15:27:47 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:27:47 +0200
Subject: [PATCH 01/63] ARM: ux500: Supply address location names for the
 DMA40 DMA controller
In-Reply-To: <1367591569-32197-2-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdacfGZ5tWiKM_RxbaQv+8QQaU1Wq_7TgYHtHTNqr9BqVw@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The DMA40 controller uses two sets of base addresses. In order to have
> the resources setup by the of_platform framework so they are searchable
> by name instead of index, we have to set names for them. The names have
> to be the same as the ones used to fetch them back out of the resource
> structure.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied this one to my ux500-devicetree branch.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:29:33 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:29:33 +0200
Subject: [PATCH 02/63] ARM: ux500: Setup the DMA40 driver's DT node using
 the new DMA API
In-Reply-To: <1367591569-32197-3-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdak+tbRM7fbKNEWh4H_YipC7B4-MxmEdnsQG65tqzG5JQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The new DMA is now available, so let's use it to setup ST-Ericsson's
> DMA40 driver when Device Tree is enabled.
>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:33:15 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:33:15 +0200
Subject: [PATCH 04/63] ARM: ux500: Supply MMC DMA configuration via Device
 Tree
In-Reply-To: <1367591569-32197-5-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZEYKPeutHjs7UfSGmjQQvafp1nV-ZR6DBLWZ0-oVfa_g@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> When requesting a channel, a DMA client needs to pass some pieces of
> information such as; request channel, device type, channel type and
> direction etc. Normally we do this in the form of platform data, but
> when DT is enabled we need to pass it using the driver's bindings
> instead.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:33:54 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:33:54 +0200
Subject: [PATCH 03/63] ARM: ux500: Supply UART's DMA configuration via
 Device Tree
In-Reply-To: <1367591569-32197-4-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYrb10bVpcm706NmVs7osM=gy4fT3=qZ3__pfndTWM+bQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> When requesting a channel, a DMA client needs to pass some pieces of
> information such as; request channel, device type, channel type and
> direction etc. Normally we do this in the form of platform data, but
> when DT is enabled we need to pass it using the driver's bindings
> instead.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:35:29 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:35:29 +0200
Subject: [PATCH 05/63] ARM: ux500: Populate the ux500-musb Device Tree
 entry
In-Reply-To: <1367591569-32197-6-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda_8KZeTfxwutyOD6S8nBe4BVUp+x-LhbMSohdOzyvDTg@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch provides all the information to successfully probe() and
> correctly configure the ux500-musb device driver for DMA.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:37:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:37:04 +0200
Subject: [PATCH 06/63] ARM: ux500: Pass DMA memcpy channels though Device
 Tree
In-Reply-To: <1367591569-32197-7-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ+srX-gEimgNYBgvK-qGBGorM4EygWgGdDXBhtBaTFcQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It's now possible to configure memcpy channels dynamically with DT.
> We're providing them despite the fact that they're the same as the
> hard-coded channels, as they will be removed once the u8500 platform
> goes DT-only.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Thanks!
Linus Walleij


From arnd at arndb.de  Fri May  3 15:38:07 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 21:38:07 +0200
Subject: [PATCH 9/9] ARM: ux500: always select ABX500_CORE
In-Reply-To: <CACRpkdaUKM1VzDhi3dMRh92XAYgg3KynvdmXKvCLfiCachP1EQ@mail.gmail.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <2812721.61fsxKBgRj@wuerfel>
 <CACRpkdaUKM1VzDhi3dMRh92XAYgg3KynvdmXKvCLfiCachP1EQ@mail.gmail.com>
Message-ID: <1448676.shCqS631GB@wuerfel>

On Friday 03 May 2013 20:43:42 Linus Walleij wrote:
> 
> Sounds like a deal. The AB chips aren't on-chip though
> they sit on I2C or SPI actually. But they are still
> strongly coupled with the SoC.
> 
> I just took a stroll around the premises and found this
> Aardvark I2C/SPI "embedded systems interface".
> 
> This is a USB thing that makes it possible to connect
> any I2C or SPI peripheral to the desktop ... I don't know how
> such things should be used with Linux really, it seems like
> it's something that normally gets used from userspace by
> libusb but in theory we could have a kernel driver for this
> and plug in whatever SoC I2C/SPI device into a desktop.
> 
> Whatever use it would be ... but could be useful for
> developing drivers for a chip outside of the target
> system I believe.

I would argue that the AB8500 is close enough to a
'system-on-a-chip' to make it depend on CONFIG_SOC, even
though it is technically one half of a 'system-on-two-chips'.

I would also allow x86 and all other architectures to enable
CONFIG_SOC, since there are lots of SoCs these days that combine
an x86 core with the same kind of peripherals we have on ARM
systems. It's just not what you you find in a regualar PC or
Laptop, and anyone building their own kernel can ignore those.

	Arnd


From linus.walleij at linaro.org  Fri May  3 15:40:50 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:40:50 +0200
Subject: [PATCH 07/63] dmaengine: ste_dma40: Assign memcpy channels in the
 driver
In-Reply-To: <1367591569-32197-8-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYUo+uApXMzFpYe74CMP+2r=+OiignXrkL9UgJoL7CLXg@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The channels reserved for memcpy are the same for all currently
> supported platforms. With this in mind, we can ease the platform
> data passing requirement by moving these assignments out from
> platform code and place them directly into the driver.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

(...)
> -/* Reserved event lines for memcpy only */
> -static int dma40_memcpy_event[] = {
> -       DB8500_DMA_MEMCPY_TX_0,
> -       DB8500_DMA_MEMCPY_TX_1,
> -       DB8500_DMA_MEMCPY_TX_2,
> -       DB8500_DMA_MEMCPY_TX_3,
> -       DB8500_DMA_MEMCPY_TX_4,
> -       DB8500_DMA_MEMCPY_TX_5,
> -};
(...)
> +/* Reserved event lines for memcpy only. */
> +static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };

I'm still not OK with named numbers being replaced with hardcoded
numbers.

Apparently this is a hard review comment so I will go in and patch
it myself with a separate patch on top of this.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:51:07 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:51:07 +0200
Subject: [PATCH 07/63] dmaengine: ste_dma40: Assign memcpy channels in the
 driver
In-Reply-To: <1367591569-32197-8-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda1ELOH_aHcmy1LOs3XpWrwdtOhQWpEXx5Uik5yOJVbng@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The channels reserved for memcpy are the same for all currently
> supported platforms. With this in mind, we can ease the platform
> data passing requirement by moving these assignments out from
> platform code and place them directly into the driver.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied this to my ux500-dma40 branch, then applied the just mailed
fixup patch immediately after it.

Let's see how far ahead we get before I run into merge conflicts because
of this :-)

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:53:40 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:53:40 +0200
Subject: [PATCH 08/63] dmaengine: ste_dma40: Move default memcpy configs
 into the driver
In-Reply-To: <1367591569-32197-9-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-9-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbBWdxCHRjJ_Q-PF4bROnW6s7FXbCineuoxUEk_VJopUw@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> There are only two default memcpy configurations used for the DMA40
> driver; one for physical memcpy and one for logical memcpy. Instead
> of invariably passing the same configurations though platform data,
> we're moving them into the driver instead.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied with some fuzzing to my ux500-dma40 branch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 15:58:16 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 21:58:16 +0200
Subject: [PATCH 09/63] dmaengine: ste_dma40: Rectify incorrect
 configuration validation checking
In-Reply-To: <1367591569-32197-10-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-10-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYY7Z2invp-Eq2+n+hqdqxKx05QuKCqAe+PudU9JWGXrg@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> If we compare an event's group (dev_type / 16) with STEDMA40_DEV_DST_MEMORY
> (-1), the only way we'd obtain a positive result is if we passed -16 as a
> device type, which is unfeasible. Instead, it would be much more sane to
> compare STEDMA40_DEV_DST_MEMORY against the raw dev_type in order to expect
> the expected result.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I'd like Vinod's ACK on this before I send it to ARM SoC but tentatively
applied (and just what I wanted!)

Vinod can I have your ACK on this?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:00:36 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:00:36 +0200
Subject: [PATCH 10/63] dmaengine: ste_dma40: Amalgamate DMA source and
 destination channel numbers
In-Reply-To: <1367591569-32197-11-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-11-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYmuyj7tpnykUcdbjw4zjWvuLN3UBsnFc7dG=OpaEVfcA@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Devices which utilise DMA use the same device numbers for transmitting
> and receiving. In this patch we encode the source and destination
> information into one single attribute. We can subsequently exploit the
> direction attribute to see which of the transfer directions are being
> described. This also lessens the burden on platform data.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch!

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:02:19 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:02:19 +0200
Subject: [PATCH 11/63] ARM: ux500: Strip out duplicate USB DMA
 configuration
In-Reply-To: <1367591569-32197-12-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-12-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ4ufprKp4P9p+Np-omi1on8BDTO0q9DONHtk7gGxczMw@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> For the moment at least, the TX and RX channels for DB8500 USB are
> identical, so this patch generalises them into a single structure
> and passes it twice. Once as the TX and again for the RX configuration.
> We're keeping the infrastructure the same i.e. passing the TX and RX
> separately in case they start to differ on latter incarnations of the
> platform.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:04:19 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:04:19 +0200
Subject: [PATCH 12/63] dmaengine: ste_dma40: Remove home-brew MAX() macro
In-Reply-To: <1367591569-32197-13-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-13-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZcEFkuPeCk+ef2QJeWr+4MXBcjyNpASrH9btTb2TR_YQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The current implementation of the DMA40's local MAX() macro evaluates
> its arguments more times than is necessary and it not type checked.
> This patch strips replaces it with a new, more efficient constant.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Reported-by: Harvey Harrison <harvey.harrison at gmail.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch with some fuzzing.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:07:33 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:07:33 +0200
Subject: [PATCH 13/63] ARM: ux500: Remove unused 'data_width' attributes
 from SDI DMA configs
In-Reply-To: <1367591569-32197-14-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-14-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaQ7bj9Wut2Pcuroq167AtP9TavvtA7FuZ+58KA7wj33Q@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA configuration data is now allocated in the MMCI driver, so these
> are just ignored.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:09:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:09:04 +0200
Subject: [PATCH 14/63] ARM: ux500: Remove unused 'data_width' attributes
 from SSP DMA configs
In-Reply-To: <1367591569-32197-15-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-15-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbVhxmei-VgYwD2-wO4i7Otz4NROhZ01HzBWwTk2CK2KQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA configuration data is now allocated in the SSP driver, so these
> are just ignored.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:11:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:11:00 +0200
Subject: [PATCH 15/63] ARM: ux500: Remove unused 'data_width' attributes
 from UART DMA configs
In-Reply-To: <1367591569-32197-16-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-16-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZXTdkTkE2xW=ktuiTHddxJeqNkVwKFT3LnsitCjsTmQw@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA configuration data is now allocated in the UART driver, so these
> are just ignored.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:13:22 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:13:22 +0200
Subject: [PATCH 16/63] ARM: ux500: Remove superfluous 'psize' attribute
 from Audio platform data
In-Reply-To: <1367591569-32197-17-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-17-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYPDnvb+_TEf63NsW8ra0ciWAHmp-VHiXPumFJbL=PNXg@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> 'psize' is used to calculate the maximum DMA burst size. However it
> is only taken into consideration when editing the DMA channel's
> configuration. The Audio DMA platform data is only used to allocate
> a channel, not configure it. That will be done at a later date within
> the MSP driver.
>
> We're also removing comments which are no longer required, as
> 'data_width' is no longer set in any device's platform data period.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied.

Fabio: as I know you have audio working on the ux500
with the mainline driver: could you confirm that this patch
does not disturb the audio playback and provide a
Tested-by?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:15:16 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:15:16 +0200
Subject: [PATCH 17/63] dmaengine: ste_dma40: Calculate number of logical
 channels from physical ones
In-Reply-To: <1367591569-32197-18-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-18-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdatVVLX8S=OGUFs-ab+HZ6mrj6nyqCxg_YzojNJ=FJPoQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This change will cost ~25KB of memory, but it's worth the trade-off,
> as it removes a great deal of overhead. It means that instead of only
> allocating memory for the logical channels in use, it does so for all
> available ones, which is 32 per physical channel. However, this now
> means we can remove some platform data and we don't have to worry
> about adding vendor specific variables to Device Tree.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:17:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:17:26 +0200
Subject: [PATCH 18/63] dmaengine: ste_dma40: Remove 'always true' checking
In-Reply-To: <1367591569-32197-19-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-19-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda2+49CjTOBcnfjp=EXOhOnrLHz4K+yOH-bKp+s7OmpsA@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Before allocating memory for logical channels, the current driver
> checks to see if there are any. Well as the dma40_memcpy_channels[]
> array is always populated, the check is always true. Best to
> remove the check.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied to my ux500-dma40 branch.

Vinod, can I have your ACK on this patch?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:23:57 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:23:57 +0200
Subject: [PATCH 19/63] dmaengine: ste_dma40: Separate Logical Global
 Interrupt Mask (GIM) unmasking
In-Reply-To: <1367591569-32197-20-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-20-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZexk6a7yaWEzzOkihcHNGY_UQN3hYiz45LK1cuy0ob=g@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> During the initial setup of a logical channel, it is necessary to unmask
> the GIM in order to receive generated terminal count and error interrupts.
> We're separating out this required code so it will be possible to move
> the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> into the runtime_config() routine.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

These review comments are only partially accounted for:
http://marc.info/?l=linux-kernel&m=136688761708399&w=2

Please supply a short changelog in the next submission
so I know what was changed and why some things were not
changed and if you split out other changes to other patches
etc etc.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:27:07 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:27:07 +0200
Subject: [PATCH 20/63] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <1367591569-32197-21-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-21-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbx_-wcatRaUpRw5LJY6qsoqDc3iqwk+UVmoBWR1M35KQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> All configuration left in d40_phy_cfg() is runtime configurable and
> there is already a call into it from d40_runtime_config(), so let's
> rely on that.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
(...)

> @@ -2027,6 +2027,14 @@ static int d40_config_memcpy(struct d40_chan *d40c)
>         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
>                    dma_has_cap(DMA_SLAVE, cap)) {
>                 d40c->dma_cfg = dma40_memcpy_conf_phy;
> +
> +               /* Generate interrrupt at end of transfer or relink. */
> +               d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
> +
> +               /* Generate interrupt on error. */
> +               d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> +               d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> +

This hunk looks like it's fixing a bug introduced in patch 19/63.

Do you try to run a memcpy test after patch 19?

Breaking the drive in one patch and fixing it in the next is
a no-no because of bisection.

Maybe things work fine if you just move this hunk of the
patch over to 19/63?

Apart from this the patch looks fine.

Yours,
Linus Walleij


From arnd at arndb.de  Fri May  3 16:34:30 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 22:34:30 +0200
Subject: [PATCH 7/9] ARM: OMAP: don't select SERIAL_OMAP unconditionally
In-Reply-To: <20130502233249.GU28721@atomide.com>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-8-git-send-email-arnd@arndb.de>
 <20130502233249.GU28721@atomide.com>
Message-ID: <201305032234.30974.arnd@arndb.de>

On Friday 03 May 2013, Tony Lindgren wrote:
> Please just drop this and pick my earlier fix instead:
> 
> [PATCH 1/3] ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP
> 
> Or let me know if you prefer me to queue it.

I've applied your patch now. Should I also take the other two of that
series? I was not on Cc for these patches, but all three seem to be
required still.

	Arnd


From arnd at arndb.de  Fri May  3 16:40:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 22:40:46 +0200
Subject: [GIT PULL] Two ux500 fixes for the v3.10 series
In-Reply-To: <CACRpkdYeWi2cx2weXao9=2f78eM0_J=gK-8o6gKjcG7pjYFAxA@mail.gmail.com>
References: <CACRpkdYeWi2cx2weXao9=2f78eM0_J=gK-8o6gKjcG7pjYFAxA@mail.gmail.com>
Message-ID: <201305032240.46483.arnd@arndb.de>

On Friday 03 May 2013, Linus Walleij wrote:
> Hi ARM SoC folks,
> 
> here are two ux500 fixes for the v3.10 series, please pull
> them in. Since -rc1 is not out this is based on Torvald's
> HEAD from yesterday.

We try hard to avoid doing bug fixes on top of random HEADs.
Can you send these on top of the minimum set of branches?

	Arnd


From linus.walleij at linaro.org  Fri May  3 16:41:51 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:41:51 +0200
Subject: [PATCH 21/63] dmaengine: ste_dma40: Don't configure runtime
 configurable setup during allocate
In-Reply-To: <1367591569-32197-22-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-22-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbZmzJhZuST+T+qomK_q3q9wt34CGS6sqk0JkZV-Q6O7A@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Using the dmaengine API, allocating and configuring a channel are two
> separate actions. Here we're removing logical channel configuration from
> the channel allocating routines.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
(...)

> @@ -2024,6 +2024,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
>                 d40c->dma_cfg = dma40_memcpy_conf_log;
>                 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
>
> +               d40_log_cfg(&d40c->dma_cfg,
> +                           &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> +

So it only gets configured for memcpy now?

What happens if you use a logical channel for a device transfer?

Where will that be configured?

Have you tested this combo?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:43:10 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:43:10 +0200
Subject: [GIT PULL] Two ux500 fixes for the v3.10 series
In-Reply-To: <201305032240.46483.arnd@arndb.de>
References: <CACRpkdYeWi2cx2weXao9=2f78eM0_J=gK-8o6gKjcG7pjYFAxA@mail.gmail.com>
 <201305032240.46483.arnd@arndb.de>
Message-ID: <CACRpkdYV26xRiASZ8L3PuPqoqyPKx1Jq-okN6LgD40ffgS6zdg@mail.gmail.com>

On Fri, May 3, 2013 at 10:40 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 03 May 2013, Linus Walleij wrote:
>> Hi ARM SoC folks,
>>
>> here are two ux500 fixes for the v3.10 series, please pull
>> them in. Since -rc1 is not out this is based on Torvald's
>> HEAD from yesterday.
>
> We try hard to avoid doing bug fixes on top of random HEADs.
> Can you send these on top of the minimum set of branches?

I think I'll just wait for -rc1.

It's not *that* urgent, just wanted to clean my desk.

Yours,
Linus Walleij


From arnd at arndb.de  Fri May  3 16:47:58 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 03 May 2013 22:47:58 +0200
Subject: [GIT PULL] Two ux500 fixes for the v3.10 series
In-Reply-To: <CACRpkdYV26xRiASZ8L3PuPqoqyPKx1Jq-okN6LgD40ffgS6zdg@mail.gmail.com>
References: <CACRpkdYeWi2cx2weXao9=2f78eM0_J=gK-8o6gKjcG7pjYFAxA@mail.gmail.com>
 <201305032240.46483.arnd@arndb.de>
 <CACRpkdYV26xRiASZ8L3PuPqoqyPKx1Jq-okN6LgD40ffgS6zdg@mail.gmail.com>
Message-ID: <18485798.NYy1bj12OB@wuerfel>

On Friday 03 May 2013 22:43:10 Linus Walleij wrote:
> On Fri, May 3, 2013 at 10:40 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Friday 03 May 2013, Linus Walleij wrote:
> >> Hi ARM SoC folks,
> >>
> >> here are two ux500 fixes for the v3.10 series, please pull
> >> them in. Since -rc1 is not out this is based on Torvald's
> >> HEAD from yesterday.
> >
> > We try hard to avoid doing bug fixes on top of random HEADs.
> > Can you send these on top of the minimum set of branches?
> 
> I think I'll just wait for -rc1.
> 
> It's not *that* urgent, just wanted to clean my desk.

Ok, sounds good.

	Arnd


From linus.walleij at linaro.org  Fri May  3 16:48:20 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:48:20 +0200
Subject: [PATCH 22/63] dmaengine: ste_dma40: Move rev error-check up to
 revision acquisition
In-Reply-To: <1367591569-32197-23-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-23-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdb7KFfNTZNwzyvh75k1cbjpxfSrxDW9cchM7cfUK3dmEw@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> At the moment we fetch the hardware revision, then do some stuff, then
> check whether the revision is correct and return in error if it's not.
> Well we may as well check it as soon as we know what it is, so let's
> move the check right up underneath where we acquire the version.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-dm40 branch.

(Notice I didn't apply 20 and 21 so now I'm screwing around.)

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:53:27 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:53:27 +0200
Subject: [PATCH 23/63] dmaengine: ste_dma40: Also report the number of
 logical channels
In-Reply-To: <1367591569-32197-24-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-24-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda44=9TrUaMNhyZ43eYyXtvPjB31JxiiH7OB9xnJO_gkw@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Now we know the total of physical and logical channels, we may as
> well report them within the information log.
>
> Before:
> dma40 dma40.0: hardware revision: 3 @ 0x801c0000 with 8 physical channels
>
> After:
> <as above ...> and 256 logical channels
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:55:11 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:55:11 +0200
Subject: [PATCH 24/63] dmaengine: ste_dma40: Allocate plat_data on
 declaration
In-Reply-To: <1367591569-32197-25-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-25-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdayY5BH3t-0m9w9SW4Ru47=Vc6N9nV=vKvHTRMDTReLmA@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It's the way that most other drivers do it.
>
> Very trivial clean-up which reduces line count and simplifies code.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 16:58:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:58:00 +0200
Subject: [PATCH 25/63] dmaengine: ste_dma40: Allow driver to be
 probe()able when DT is enabled
In-Reply-To: <1367591569-32197-26-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-26-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbQLVGfvyJ5tkz7mv+kdAPuzDT1ASR_KzkQRmh0WS_+CQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> When booting using Device Tree, devices aren't registered in the normal
> way. Instead, they need to be provided with a compatible string which is
> held in an OF Match Table for comparison during start-up. Here we provide
> the compatible string and prepare the driver to not receive a platform
> data pointer.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Fixed up some whitespace error that git am was complaining about
and applied to ux500-dma40.

Thanks!
Linus Walleij


From fabio.baltieri at linaro.org  Fri May  3 16:59:34 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Fri, 3 May 2013 22:59:34 +0200
Subject: [PATCH 16/63] ARM: ux500: Remove superfluous 'psize' attribute
 from Audio platform data
In-Reply-To: <CACRpkdYPDnvb+_TEf63NsW8ra0ciWAHmp-VHiXPumFJbL=PNXg@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-17-git-send-email-lee.jones@linaro.org>
 <CACRpkdYPDnvb+_TEf63NsW8ra0ciWAHmp-VHiXPumFJbL=PNXg@mail.gmail.com>
Message-ID: <20130503205934.GA20194@balto.lan>

Hi Linus,

On Fri, May 03, 2013 at 10:13:22PM +0200, Linus Walleij wrote:
> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > 'psize' is used to calculate the maximum DMA burst size. However it
> > is only taken into consideration when editing the DMA channel's
> > configuration. The Audio DMA platform data is only used to allocate
> > a channel, not configure it. That will be done at a later date within
> > the MSP driver.
> >
> > We're also removing comments which are no longer required, as
> > 'data_width' is no longer set in any device's platform data period.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Patch applied.
> 
> Fabio: as I know you have audio working on the ux500
> with the mainline driver: could you confirm that this patch
> does not disturb the audio playback and provide a
> Tested-by?

Sure, I applied just this patch and it still works fine, tested on HREF
with speaker-test.
I have another non-related hack on dmaengine applied though, but Lee is
already aware of it so this is good for me:

Tested-by: Fabio Baltieri <fabio.baltieri at linaro.org>

Thanks,
Fabio

-- 
Fabio Baltieri


From linus.walleij at linaro.org  Fri May  3 16:59:52 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 22:59:52 +0200
Subject: [PATCH 26/63] dmaengine: ste_dma40: Supply full Device Tree
 parsing support
In-Reply-To: <1367591569-32197-27-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-27-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaj0RcZUJ9DX8D1v-MKecFs6ZwGjqD2gqaSFvP9QCbgGA@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Using the new DMA DT bindings and API, we can register the DMA40 driver
> as Device Tree capable. Now, when a client attempts to allocate a
> channel using the DMA DT bindings via its own node, we are able to parse
> the request and allocate a channel in the correct manner.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 17:00:47 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:00:47 +0200
Subject: [PATCH 26/63] dmaengine: ste_dma40: Supply full Device Tree
 parsing support
In-Reply-To: <CACRpkdaj0RcZUJ9DX8D1v-MKecFs6ZwGjqD2gqaSFvP9QCbgGA@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-27-git-send-email-lee.jones@linaro.org>
 <CACRpkdaj0RcZUJ9DX8D1v-MKecFs6ZwGjqD2gqaSFvP9QCbgGA@mail.gmail.com>
Message-ID: <CACRpkdbB6mN6XTyceCZO9j6rAPawdTijM11-ws-23tnamGYz5A@mail.gmail.com>

On Fri, May 3, 2013 at 10:59 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
>
>> Using the new DMA DT bindings and API, we can register the DMA40 driver
>> as Device Tree capable. Now, when a client attempts to allocate a
>> channel using the DMA DT bindings via its own node, we are able to parse
>> the request and allocate a channel in the correct manner.
>>
>> Cc: Vinod Koul <vinod.koul at intel.com>
>> Cc: Dan Williams <djbw at fb.com>
>> Cc: Per Forlin <per.forlin at stericsson.com>
>> Cc: Rabin Vincent <rabin at rab.in>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: devicetree-discuss at lists.ozlabs.org
>> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>
> Applied to my ux500-dma40 branch.

But hmmm would be really nice to have Vinod's ACK on this
patch as well.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 17:04:43 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:04:43 +0200
Subject: [PATCH 16/63] ARM: ux500: Remove superfluous 'psize' attribute
 from Audio platform data
In-Reply-To: <20130503205934.GA20194@balto.lan>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-17-git-send-email-lee.jones@linaro.org>
 <CACRpkdYPDnvb+_TEf63NsW8ra0ciWAHmp-VHiXPumFJbL=PNXg@mail.gmail.com>
 <20130503205934.GA20194@balto.lan>
Message-ID: <CACRpkdaCtG2B-hJpNGHv=dd9=t+9SqUrQa1OWO3A727otVfuKg@mail.gmail.com>

On Fri, May 3, 2013 at 10:59 PM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:
> Hi Linus,
> On Fri, May 03, 2013 at 10:13:22PM +0200, Linus Walleij wrote:
>> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > 'psize' is used to calculate the maximum DMA burst size. However it
>> > is only taken into consideration when editing the DMA channel's
>> > configuration. The Audio DMA platform data is only used to allocate
>> > a channel, not configure it. That will be done at a later date within
>> > the MSP driver.
>> >
>> > We're also removing comments which are no longer required, as
>> > 'data_width' is no longer set in any device's platform data period.
>> >
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> Patch applied.
>>
>> Fabio: as I know you have audio working on the ux500
>> with the mainline driver: could you confirm that this patch
>> does not disturb the audio playback and provide a
>> Tested-by?
>
> Sure, I applied just this patch and it still works fine, tested on HREF
> with speaker-test.
> I have another non-related hack on dmaengine applied though, but Lee is
> already aware of it so this is good for me:
>
> Tested-by: Fabio Baltieri <fabio.baltieri at linaro.org>

Thanks! Much appreciated!

Yours,
Linus Walleij


From tony at atomide.com  Fri May  3 17:04:46 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 3 May 2013 14:04:46 -0700
Subject: [PATCH 7/9] ARM: OMAP: don't select SERIAL_OMAP unconditionally
In-Reply-To: <201305032234.30974.arnd@arndb.de>
References: <1367528578-518090-1-git-send-email-arnd@arndb.de>
 <1367528578-518090-8-git-send-email-arnd@arndb.de>
 <20130502233249.GU28721@atomide.com>
 <201305032234.30974.arnd@arndb.de>
Message-ID: <20130503210446.GX28721@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [130503 13:40]:
> On Friday 03 May 2013, Tony Lindgren wrote:
> > Please just drop this and pick my earlier fix instead:
> > 
> > [PATCH 1/3] ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP
> > 
> > Or let me know if you prefer me to queue it.
> 
> I've applied your patch now. Should I also take the other two of that
> series? I was not on Cc for these patches, but all three seem to be
> required still.

Yes go for it. Note that the two other patches have dependencies to
branches for the current merge window, but you probably already 
have some base they can be applied against.

Regards,

Tony


From linus.walleij at linaro.org  Fri May  3 17:09:16 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:09:16 +0200
Subject: [PATCH 27/63] ARM: ux500: Pass remnant platform data though to
 DMA40 driver
In-Reply-To: <1367591569-32197-28-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-28-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ_cnneFWtinO1dPz0Ky=29aKG=wHW447cHoE8Hnok=xA@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Ironically, in order to remove lots of the auxdata assignments, we have
> to add just one more. A lot of them require DMA information to be passed
> into clients for DMA channel allocation, but we now have this capability
> in Device Tree. However, the DMA40 driver still relies on a reverse table
> look-up to obtain DMA addresses. Until all of the clients are converted,
> over to the new API, we're stuck with this.
>
> Also, now the DMA40 has been DT:ed, there's no requirement to register
> it using traditional methods, so let's remove it.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-dma40 branch.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 17:11:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:11:00 +0200
Subject: [PATCH 28/63] ARM: ux500: Stop passing UART's platform data for
 Device Tree boots
In-Reply-To: <1367591569-32197-29-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-29-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYCABo0AULsiUgwm3g=906iKzp_ZDFKLj=HgDbNK9mNUQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It was required to pass DMA channel configuration information to the
> UART driver before the new DMA API was in place. Now that it is, and
> is fully compatible with Device Tree we can stop doing that.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I can't apply this as it is clearly dependent on a patch to
drivers/tty/serial/amba-pl011.c that is not yet upstream.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 17:12:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:12:04 +0200
Subject: [PATCH 29/63] ARM: ux500: Stop passing MMC's platform data for
 Device Tree boots
In-Reply-To: <1367591569-32197-30-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-30-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY8N1_xH8RAnqA-9W9cUyX5QVs4WYJERc31TK2r6Yz8qA@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It was required to pass DMA channel configuration information to the
> MMC driver before the new DMA API was in place. Now that it is, and
> is fully compatible with Device Tree we can stop doing that.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Can't apply this because of dependencies to be merged
by Russell.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 17:12:52 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:12:52 +0200
Subject: [PATCH 30/63] ARM: ux500: Move SDI (MMC) and UART devices under
 more descriptive heading
In-Reply-To: <1367591569-32197-31-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-31-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbX_L_KAZqWWeGp1eVvUGBHgPX0cfr=zggsak+X3WNFzg@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
> should be possible to remove them from the auxdata structure. However,
> after doing so the drivers fail. Common clk is still reliant on the
> dev_name() call to do device name matching, which will fail due to the
> fact that Device Tree naming differs somewhat do the more traditional
> conventions.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Can't apply this because of dependencies on the two previous
patches which also have dependencies.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May  3 17:16:13 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 3 May 2013 23:16:13 +0200
Subject: [PATCH 31/63] dmaengine: ste_dma40: Only use addresses passed as
 configuration information
In-Reply-To: <1367591569-32197-32-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-32-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZgPs1i=Lna41di97jZ2h-=_XzfZXMN8z9QFa-U-Avxog@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Addresses are passed in from the client's driver via the invocation of
> dmaengine_slave_config(), so there's no need to fetch them from platform
> data too, hardwired or otherwise. This is a great step forward, as it
> elevates a large burden from platform data in the way of a look-up
> table.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I get uncertain at this point and need Vinod's ACK so I stop
applying patches here.

Please base further submissions on my ux500-dma40 branch to
avoid resending already applied patches, if possible. (Atleast
that make things convenient for me.)

Is it possible to move patches with hairy dependencies
toward the end of the series or something?

Yours,
Linus Walleij


From arnd at arndb.de  Fri May  3 17:26:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 May 2013 23:26:23 +0200
Subject: [PATCH, RFC 14/22] oprofile: always enable IRQ_WORK
In-Reply-To: <1367594095.7373.14.camel@gandalf.local.home>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <20130503115332.GT8356@rric.localhost>
 <1367594095.7373.14.camel@gandalf.local.home>
Message-ID: <201305032326.23973.arnd@arndb.de>

On Friday 03 May 2013, Steven Rostedt wrote:
> On Fri, 2013-05-03 at 13:53 +0200, Robert Richter wrote:
> > On 02.05.13 17:16:18, Arnd Bergmann wrote:
> > > oprofile fails to build if CONFIG_IRQ_WORK is not already enabled,
> > > because of the dependency on the RING_BUFFER code that now uses
> > > the irq work library.
> > > 
> > > kernel/built-in.o: In function `ring_buffer_unlock_commit':
> > > :(.text+0x5b8f0): undefined reference to `irq_work_queue'
> > > kernel/built-in.o: In function `ring_buffer_write':
> > > :(.text+0x5bd10): undefined reference to `irq_work_queue'
> > 
> > Shouldn't this be fixed in the ring_buffer implementation?
> 
> Does this patch fix it?
> 


Yes, this works, and looks much nicer than my version. Thanks!

	Arnd


From tglx at linutronix.de  Fri May  3 17:50:48 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:48 -0000
Subject: [RFC patch 3/8] genirq: generic chip: Handle separate mask registers
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.536981253@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:50 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:50 -0000
Subject: [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask 
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.599155322@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:46 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:46 -0000
Subject: [RFC patch 2/8] genirq: generic chip: Add support for per chip type
 mask cache
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.470374625@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:45 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:45 -0000
Subject: [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs()
 function
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.397359626@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:51 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:51 -0000
Subject: [RFC patch 5/8] genirq: Add a mask calculation function
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.669826342@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:43 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:43 -0000
Subject: [RFC patch 0/8] genirq: Support for irq domains in generic irq chip
In-Reply-To: <alpine.LFD.2.02.1305031514230.2886@ionos>
Message-ID: <20130503212258.385818955@linutronix.de>

The ongoing device tree support for ARM is creating new irq chip
drivers in drivers/irqchip/ in a frenzy. Quite some of them are
ripping out the generic irq chip implementation from arch/arm/* and
just creating the same mess of duplicated code again, which was
cleaned up with the generic irq chip implementation with a lot of
effort. Sigh!

I already prodded a few people in reviews to tackle that issue with no
outcome. Even more sigh!

Poor Sebastian triggered me into rant mode, but he ad hoc
volunteered to give it a try. YAY!

Though he asked for a bit of kickstart help. So I squeezed out a few
spare cycles and implemented the basics as far as I think that they
should work.

The following series contains the missing bits and pieces including a
somehow forgotten and now slightly modified series from Gerlando
adding support for irq chips which need separate mask caches for
different chip (control flow) types.

At the moment this supports only linear irq domains, but it could be
extended to other types as well if the need arises. Though the ARM
chips are pretty much all about linear domains AFAICT.

It also lacks support for removing an irq domain at the moment, but
that should be rather trivial to fix.

The last patch in the series is a blind conversion of the irq-sun4i
irq chip driver, completely untested and not even compiled. I just
added it for demonstration purposes. As Russell expected, there is a
lot of consolidation potential. The changelog of that patch is:

 1 file changed, 29 insertions(+), 71 deletions(-)

The preparing series has

 4 files changed, 294 insertions(+), 50 deletions(-)

So for removing 42 lines in a single driver the core grows 244 lines
including header changes and comments. Convert 6 drivers and we are
more than even because we get the benefit of sharing and therefor
exposing the same code to broader testing and utilization.

We have already 11 of those candidates in drivers/irqchips and new
ones are knocking on the door.

There might be even more consolidation potential, but I leave that to the
DT/irq domain experts.


WARNING: It's compile tested only. So if you find bugs you can keep
them and fix them yourself :)


Thanks,

	tglx
---
 drivers/irqchip/irq-sun4i.c |  100 ++++-----------
 include/linux/irq.h         |   45 ++++++-
 include/linux/irqdomain.h   |   12 +
 kernel/irq/generic-chip.c   |  281 +++++++++++++++++++++++++++++++++++++-------
 kernel/irq/irqdomain.c      |    6 
 5 files changed, 323 insertions(+), 121 deletions(-)



From tglx at linutronix.de  Fri May  3 17:50:55 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:55 -0000
Subject: [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.880345092@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:52 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:52 -0000
Subject: [RFC patch 6/8] genirq: Split out code in generic chip
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.741399680@linutronix.de>

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From tglx at linutronix.de  Fri May  3 17:50:53 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 03 May 2013 21:50:53 -0000
Subject: [RFC patch 7/8] genirq: generic chip: Add linear irq domain support
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130503214629.810207749@linutronix.de>

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From linux at arm.linux.org.uk  Fri May  3 18:23:01 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 23:23:01 +0100
Subject: [RFC patch 7/8] genirq: generic chip: Add linear irq domain
 support
In-Reply-To: <20130503214629.810207749@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.810207749@linutronix.de>
Message-ID: <20130503222300.GF18614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 09:50:53PM -0000, Thomas Gleixner wrote:
> +	/* Init mask cache ? */
> +	if (dgc->gc_flags & IRQ_GC_INIT_MASK_CACHE) {
> +		raw_spin_lock_irqsave(&gc->lock, flags);
> +		gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
> +		raw_spin_unlock_irqrestore(&gc->lock, flags);
> +	}

This looks a little weird to me - it seems that it'll re-read this
each time any irq is mapped in the domain, which is probably not
wanted.


From linux at arm.linux.org.uk  Fri May  3 18:24:06 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 May 2013 23:24:06 +0100
Subject: [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask
In-Reply-To: <20130503214629.599155322@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.599155322@linutronix.de>
Message-ID: <20130503222406.GG18614@n2100.arm.linux.org.uk>

On Fri, May 03, 2013 at 09:50:50PM -0000, Thomas Gleixner wrote:
> -	u32 mask = ~(1 << (d->irq - gc->irq_base));
> +	u32 mask = ~(d->mask);

I suspect the above changes are all a result of a search-and-replace
which results in the cosmetic parens remaining.  Would be nice to get
rid of them too as they're completely unnecessary.


From tglx at linutronix.de  Fri May  3 18:38:34 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Sat, 4 May 2013 00:38:34 +0200 (CEST)
Subject: [RFC patch 7/8] genirq: generic chip: Add linear irq domain
 support
In-Reply-To: <20130503222300.GF18614@n2100.arm.linux.org.uk>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.810207749@linutronix.de>
 <20130503222300.GF18614@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1305040033000.2990@ionos>

On Fri, 3 May 2013, Russell King - ARM Linux wrote:

> On Fri, May 03, 2013 at 09:50:53PM -0000, Thomas Gleixner wrote:
> > +	/* Init mask cache ? */
> > +	if (dgc->gc_flags & IRQ_GC_INIT_MASK_CACHE) {
> > +		raw_spin_lock_irqsave(&gc->lock, flags);
> > +		gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
> > +		raw_spin_unlock_irqrestore(&gc->lock, flags);
> > +	}
> 
> This looks a little weird to me - it seems that it'll re-read this
> each time any irq is mapped in the domain, which is probably not
> wanted.

Yes, it's sloppy in two aspects.

1) It does not respect the per irq type mask cache, which got
   introduced in the same series

2) It rereads the mask cache for each mapping, but thats harmless
   because it's proper serialized. We can avoid that by clearing the
   IRQ_GC_INIT_MASK_CACHE bit when the first irq of that chip is
   mapped.

Congrats, you found a bug and as I said:

	  WARNING: It's compile tested only. So if you find bugs you can keep
	  them and fix them yourself :)

Thanks,

	tglx


From tglx at linutronix.de  Fri May  3 18:39:15 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Sat, 4 May 2013 00:39:15 +0200 (CEST)
Subject: [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask
In-Reply-To: <20130503222406.GG18614@n2100.arm.linux.org.uk>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.599155322@linutronix.de>
 <20130503222406.GG18614@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1305040038510.2990@ionos>

On Fri, 3 May 2013, Russell King - ARM Linux wrote:

> On Fri, May 03, 2013 at 09:50:50PM -0000, Thomas Gleixner wrote:
> > -	u32 mask = ~(1 << (d->irq - gc->irq_base));
> > +	u32 mask = ~(d->mask);
> 
> I suspect the above changes are all a result of a search-and-replace
> which results in the cosmetic parens remaining.  Would be nice to get
> rid of them too as they're completely unnecessary.

Fair enough.

Thanks,

	tglx 


From s-anna at ti.com  Fri May  3 22:20:32 2013
From: s-anna at ti.com (Suman Anna)
Date: Fri, 3 May 2013 21:20:32 -0500
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <51847070.8040400@ti.com>

Hi Jassi,

On 04/27/2013 01:14 PM, jassisinghbrar at gmail.com wrote:
> From: Jassi Brar <jaswinder.singh at linaro.org>
> 
> Introduce common framework for client/protocol drivers and
> controller drivers of Inter-Processor-Communication (IPC).
> 
> Client driver developers should have a look at
>  include/linux/mailbox_client.h to understand the part of
> the API exposed to client drivers.
> Similarly controller driver developers should have a look
> at include/linux/mailbox_controller.h

This implementation looks decent based on your design points. These
are the open/contention points that needs to be sorted out.

I think understanding the OMAP mailbox architecture also helps you,
since this series currently addressed PL320, but we will run into
some issues when adopting for OMAP as is. OMAP has a single mailbox IP,
each with multiple h/w FIFOs (fifo of length 4, and message size of a
u32). Each IP can cause one or more irq (usually 1) into the linux host.
It has status registers for number of messages in a FIFO (Rx), FIFO full
(Tx non-readiness/busy state), and interrupts for both Rx and Tx. There
are registers indicating the source of the interrupt, and these are per
FIFO. The Tx interrupt source is really for indicating Tx readiness or
that a fifo has open room for sending messages. This will keep on firing
as long as the FIFO is not-full, so we usually configure this only when
the FIFO is full and disable it the moment it is fired. It is re-enabled
when the h/w FIFO is full again, and we use s/w buffering in between.
The Rx interrupt is fired as long as there is a message in any FIFO
which has been configured to interrupt the host, so we have to empty all
the messages for that interrupt source.

Anyway, here is a summary of the open points that we have:
1. Atomic Callbacks:
The current code provides some sort of buffering on Tx, but imposes the
restriction that the clients do the buffering on Rx. This is main
concern for OMAP. We have multiple links on a single interrupt and
multiple messages per link on a interrupt source. Pushing this logic
into a client (remoteproc for us) is not right, that code does not
belong to the remoteproc driver, and neither is adding another layer in
between. It also kills the shared clients idea. The current
ipc_link_received_data seems open enough for me to use by calling it
from a work-queue, and have the OMAP controller driver take care of Rx
buffering (will test this next week). Restricting ipc_link_received_data
to atomic callbacks might have been enough for single transport
payloads, but we do have a FIFO. I could possibly make it work using
this API, but it brings me to my next point which is shared clients.

2. Support for Shared Clients AND Time-shared Clients:
As I said before, we need the framework to be flexible enough to support
shared clients. The shared clients may not be applicable for all h/w
controllers, where a client has to send a series of operations that
needs to be sent to the remote before anyone else can use it. This is a
functional integration aspect, and is dictated by the nature of the
remote. For the time-shared clients, the remote must have some implicit
message protocol where in the remote is able to identify the macro
usecase through a specific message. The framework should allow the case
of shared clients, with the clients doing their own message demuxing.

You can take a look at my patches on top of the existing mailbox code
that allows both shared clients and atomic callbacks, and multi-instance
support. It is not that hard to incorporate similar concepts into this
code as well. It is based on properties published by the
controller/link. [I haven't added the tx callbacks and poll method, that
would actually mean I will be doing a very similar state machine to what
you have, no point in me spending time on that, unless we are gonna
absorb the current mailbox series.]

https://github.com/sumananna/mailbox/commits/mailbox-multi-atomic-dt-doc

3. Buffering/Size: I think we need to take a re-look at the whole tx
buffering mechanism. You are using an array that stores just the
pointers, which means that there are underlying assumptions that the
clients are keeping their buffer ptrs intact until the duration of the
transfer is done. This means that one cannot use local payload
variables for messages in the calling functions. I feel this is
unnecessary burden on the clients.

Secondly, we may not need the logic around client knows_txdone and
tx_buffering together. I understand the need for buffering when you have
TX_POLL or TX_IRQ, but as far as TX_ACK is concerned, it is a client
protocol-level knowledge, and so the tx buffering logic can remain with
the client itself. This should simplify the code a little bit and get
rid of the ipc_client_txdone API.

Looking at the current use-cases, I think OMAP might be the only one
which needs the buffering. The API that Loic added suggests that he
either sends a message and expects a response, or just sends a message
if the transport is free (I am not sure if he is using the API that uses
buffering currently). PL320 is the same as the first scenario that Loic has.

The other point is regarding the size field, I am not convinced that we
can take this out, and leave it between the client and the controller
implementation. I think the mailbox core should at least perform a check
based on the max size published by a controller driver. Like in the
PL320 patch conversion, the for loop for writing the data - how does it
know that the provided pointer is atleast 7 ints, and not smaller than
that?

Rest of the comments are in the code...

> 
> diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
> new file mode 100644
> index 0000000..c5ec93e
> --- /dev/null
> +++ b/drivers/mailbox/mailbox.c
> +
> +/*
> + * Called by a client to "put data on the h/w channel" so that if
> + * everything else is fine we don't need to do anything more locally
> + * for the remote to receive the data intact.
> + * In reality, the remote may receive it intact, corrupted or not at all.
> + * This could be called from atomic context as it simply
> + * queues the data and returns a token (request_token_t)
> + * against the request.
> + * The client is later notified of successful transmission of
> + * data over the channel via the 'txcb'. The client could in
> + * turn queue more messages from txcb.
> + */
> +request_token_t ipc_send_message(void *channel, void *data)
> +{
> +	struct ipc_chan *chan = (struct ipc_chan *)channel;
> +	request_token_t t;
> +
> +	if (!chan)
> +		return 0;
> +
> +	t = _add_to_rbuf(chan, data);
> +	if (!t)
> +		printk("Try increasing MBOX_TX_QUEUE_LEN\n");
> +
> +	_msg_submit(chan);
> +
> +	if (chan->txdone_method	== TXDONE_BY_POLL)
> +		poll_txdone((unsigned long)chan->timer);
> +
> +	if (chan->tx_block && chan->active_token) {

Assigning the tx_block at channel request time might not be flexible
enough. We should not impose that the client will request and release
channels with different modes if both scenarios are needed.

> +		int ret;
> +		init_completion(&chan->tx_complete);
> +		ret = wait_for_completion_timeout(&chan->tx_complete,
> +			chan->tx_tout);
> +		if (ret == 0) {
> +			t = 0;
> +			tx_tick(chan, XFER_ERR);
> +		}
> +	}
> +
> +	return t;
> +}
> +EXPORT_SYMBOL(ipc_send_message);

Do we need to add an API similar to mailbox_msg_send_receive_no_irq, or
are you leaving it to be client's responsibility?

> +
> +/*
> + * A client driver asks for exclusive use of a channel/mailbox.
> + * If assigned, the channel has to be 'freed' before it could
> + * be assigned to some other client.
> + * After assignment, any packet received on this channel will be
> + * handed over to the client via the 'rxcb' callback.
> + * The 'txcb' callback is used to notify client upon sending the
> + * packet over the channel, which may or may not have been yet
> + * read by the remote processor.
> + */
> +void *ipc_request_channel(struct ipc_client *cl)
> +{
> +	struct ipc_chan *chan;
> +	unsigned long flags;
> +	int ret = 0;
> +
> +	mutex_lock(&chpool_mutex);
> +
> +	list_for_each_entry(chan, &ipc_channels, node)
I had a different design in mind here, maintain the list of controllers
globally instead of the channels, that way your search can be a bit
quicker.

> +		if(!chan->assigned
> +				&& !strcmp(cl->chan_name, chan->chan_name)) {
> +			spin_lock_irqsave(&chan->lock, flags);
> +			chan->msg_free = 0;
> +			chan->msg_count = 0;
> +			chan->active_token = 0;
> +			chan->rxcb = cl->rxcb;
> +			chan->txcb = cl->txcb;
> +			chan->assigned = true;
> +			chan->tx_block = cl->tx_block;
> +			if (!cl->tx_tout)
> +				chan->tx_tout = ~0;
> +			else
> +				chan->tx_tout = msecs_to_jiffies(cl->tx_tout);
> +			if (chan->txdone_method	== TXDONE_BY_POLL
> +					&& cl->knows_txdone)
> +				chan->txdone_method |= TXDONE_BY_ACK;
> +			spin_unlock_irqrestore(&chan->lock, flags);
> +			ret = 1;
> +			break;
> +		}
> +
> +	mutex_unlock(&chpool_mutex);
> +
> +	if (!ret) {
> +		printk("Unable to assign mailbox(%s)\n", cl->chan_name);
> +		return NULL;
> +	}
> +
> +	ret = chan->link_ops->startup(chan->link, cl->cntlr_data);
> +	if (ret) {
> +		printk("Unable to startup the link\n");
> +		ipc_free_channel((void *)chan);
> +		return NULL;
> +	}
> +
> +	return (void *)chan;
> +}
> +EXPORT_SYMBOL(ipc_request_channel);
> +
> +/*
> + * Call for IPC controller drivers to register a controller, adding
> + * its channels/mailboxes to the global pool.
> + */
> +int ipc_links_register(struct ipc_controller *ipc_con)
> +{
> +	struct tx_poll_timer *timer = NULL;
> +	struct ipc_chan *channel;
> +	int i, num_links, txdone;
> +
> +	/* Are you f***ing with us, sir? */
> +	if (!ipc_con || !ipc_con->ops)
> +		return -EINVAL;
> +
> +	for (i = 0; ipc_con->links[i]; i++)
> +		;
> +	if (!i)
> +		return -EINVAL;
> +	num_links = i;
> +
> +	if (ipc_con->txdone_irq)
> +		txdone = TXDONE_BY_IRQ;
> +	else if (ipc_con->txdone_poll)
> +		txdone = TXDONE_BY_POLL;
> +	else /* It has to be at least ACK */
> +		txdone = TXDONE_BY_ACK;
> +
> +	if (txdone == TXDONE_BY_POLL) {
> +		timer = kzalloc(sizeof(struct tx_poll_timer), GFP_KERNEL);
> +		timer->period = ipc_con->txpoll_period;
> +		timer->poll.function = &poll_txdone;
> +		timer->poll.data = (unsigned long)timer;
> +		init_timer(&timer->poll);
> +	}
> +
> +	channel = kzalloc(sizeof(struct ipc_chan) * num_links, GFP_KERNEL);

minor, but you might be aware of this already, failure check needed

> +
> +	for (i = 0; i < num_links; i++) {
> +		channel[i].timer = timer;
> +		channel[i].assigned = false;
> +		channel[i].txdone_method = txdone;
> +		channel[i].link_ops = ipc_con->ops;
> +		channel[i].link = ipc_con->links[i];
> +		channel[i].link->api_priv = &channel[i];
> +		snprintf(channel[i].chan_name, 32, "%s:%s",
> +			ipc_con->controller_name,
> +			ipc_con->links[i]->link_name);
> +		spin_lock_init(&channel[i].lock);
> +		BLOCKING_INIT_NOTIFIER_HEAD(&channel[i].avail);
> +		mutex_lock(&chpool_mutex);
> +		list_add_tail(&channel[i].node, &ipc_channels);
> +		mutex_unlock(&chpool_mutex);
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(ipc_links_register);
> +
> +static int __init ipc_mbox_init(void)
> +{
> +	INIT_LIST_HEAD(&ipc_channels);
> +	return 0;
> +}
> +subsys_initcall(ipc_mbox_init);

The ipc_mbox_init can be replaced by static list init of ipc_channels,
nothing much to be gained by defining this function. We expect the
mailbox.c to be built anyways whenever the mailbox framework is selected.

> diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h
> new file mode 100644
> index 0000000..33545f6
> --- /dev/null
> +++ b/include/linux/mailbox_client.h
> +/**
> + * struct ipc_client - User of a mailbox
> + * @chan_name: the "controller:channel" this client wants
> + * @rxcb: atomic callback to provide client the data received
> + * @txcb: atomic callback to tell client of data transmission
> + * @tx_block: if the ipc_send_message should block until data is transmitted
> + * @tx_tout: Max block period in ms before TX is assumed failure
> + * @knows_txdone: if the client could run the TX state machine. Usually if
> + *    the client receives some ACK packet for transmission. Unused if the
> + *    controller already has TX_Done/RTR IRQ.
> + * @cntlr_data: Optional controller specific parameters during channel request
> + */
> +struct ipc_client {
> +	char *chan_name;
> +	void (*rxcb)(void *data);
> +	void (*txcb)(request_token_t t, enum xfer_result r);
> +	bool tx_block;
> +	unsigned long tx_tout;
> +	bool knows_txdone;
> +	void *cntlr_data;

What is the current use-case for exposing cntrl_data through ipc_client?
I think this should be avoided and leave the controller configuration to
the controller driver implementation. This will be a problem for
multiple link scenarios.

> diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h
> new file mode 100644
> index 0000000..defcfb3
> --- /dev/null
> +++ b/include/linux/mailbox_controller.h
> +
> +/**
> + * struct ipc_link - s/w representation of a communication link
> + * @link_name: Literal name assigned to the link. Physically
> + *    identical channels may have the same name.
> + * @api_priv: hook for the API to map its private data on the link
> + *    Controller driver must not touch it.
> + */
> +struct ipc_link {
> +	char link_name[16];
> +	void *api_priv;
> +};

this definitely needs a link-private void *ptr. PL320 doesn't have
multiple links in the controller, but this is a problem for OMAP & DBX500.

> +struct ipc_link_ops {
> +	int (*send_data)(struct ipc_link *link, void *data);
> +	int (*startup)(struct ipc_link *link, void *params);
> +	void (*shutdown)(struct ipc_link *link);
> +	bool (*last_tx_done)(struct ipc_link *link);
minor comment, maybe rename this to something that indicates link
busyness or readiness

> +};
> +
> +/**
> + * struct ipc_controller - Controller of a class of communication links
> + * @controller_name: Literal name of the controller.
> + * @ops: Operators that work on each communication link
> + * @links: Null terminated array of links.
> + * @txdone_irq: Indicates if the controller can report to API when the
> + *    last transmitted data was read by the remote. Eg, if it has some
> + *    TX ACK irq.
> + * @txdone_poll: If the controller can read but not report the TX done.
> + *    Eg, is some register shows the TX status but no interrupt rises.
> + *    Ignored if 'txdone_irq' is set.
> + * @txpoll_period: If 'txdone_poll' is in effect, the API polls for
> + *    last TX's status after these many millisecs
> + */
> +struct ipc_controller {
> +	char controller_name[16];
i think this can be avoided and use the underlying dev-name directly
based on the controller device. Adding a struct device pointer would
automatically allow you to use the name from the probe.

> +	struct ipc_link_ops *ops;
I think this should be a property of the individual link for
flexibility. Right now, it probably doesn't make a difference (as seen
from the current mailbox code), but the moment we have one link behaving
differently this will make the ops implementation a bit messy.

I think we also need a controller-specific ops, to put common stuff
between multiple links within the controller.

> +	struct ipc_link **links;
> +	bool txdone_irq;
> +	bool txdone_poll;
> +	unsigned txpoll_period;
> +};
> +




From sebastian.hesselbarth at gmail.com  Fri May  3 22:30:28 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 04 May 2013 04:30:28 +0200
Subject: [RFC patch 7/8] genirq: generic chip: Add linear irq domain
 support
In-Reply-To: <20130503214629.810207749@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.810207749@linutronix.de>
Message-ID: <518472C4.5080209@gmail.com>

On 05/03/2013 11:50 PM, Thomas Gleixner wrote:
 > Provide infrastructure for irq chip implementations which work on
 > linear irq domains.

Thomas,

I am happy that I put you into rant mode. It took me little more
than an hour to read through your patches, prepare orion irqchip
driver on top of them and finally got it working.

Anyway, I found some more issues.

 > Index: linux-2.6/kernel/irq/generic-chip.c
 > ===================================================================
 > --- linux-2.6.orig/kernel/irq/generic-chip.c
 > +++ linux-2.6/kernel/irq/generic-chip.c
 > @@ -7,6 +7,7 @@
[...]
 > +int irq_alloc_domain_generic_chips(struct irq_domain *d, int 
irqs_per_chip,
 > +				   int num_ct, const char *name,
 > +				   irq_flow_handler_t handler,
 > +				   unsigned int clr, unsigned int set,
 > +				   enum irq_gc_flags gcflags)
 > +{
 > +	struct irq_domain_chip_generic *dgc;
 > +	struct irq_chip_generic *gc;
 > +	int numchips, sz, i;
 > +	unsigned long flags;
 > +
 > +	if (d->gc)
 > +		return -EBUSY;
 > +
 > +	if (d->revmap_type != IRQ_DOMAIN_MAP_LINEAR)
 > +		return -EINVAL;
 > +
 > +	numchips = d->revmap_data.linear.size / irqs_per_chip;
 > +	if (!numchips)
 > +		return -EINVAL;
 > +
 > +	sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 > +	sz *= numchips;
 > +	sz += sizeof(*dgc);
 > +
 > +	dgc = kzalloc(sz, GFP_KERNEL);
 > +	if (!dgc)
 > +		return -ENOMEM;
 > +	dgc->irqs_per_chip = irqs_per_chip;
 > +	dgc->num_chips = numchips;
 > +	dgc->irq_flags_to_set = set;
 > +	dgc->irq_flags_to_clear = clr;
 > +	dgc->gc_flags = gcflags;
 > +	gc = dgc->gc;
 > +
 > +	for (i = 0; i < numchips; i++, gc++) {

The memory you allocated for gc, num_ct * ct, and dgc doesn't allow
to increment through gc. gc is struct irq_chip_generic * but next
gc is at sizeof(*gc) + num_ct * sizeof(struct irq_chip_type).
This also affects indexing dgc->gc later.

I chose to fix it by having an index helper but that first maps
dgc-gc to unsigned char * and then adds the correct offset. Not
nice but it works. Maybe having real array of ptr to gc is more
intuitive here even if we will have to have split kzallocs.

 > +		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
 > +				      NULL, handler);

irq_init_generic_chip does not take care of initalizing ct
mask_cache ptr. This should be done here.

 > +		gc->domain = d;
 > +		raw_spin_lock_irqsave(&gc_lock, flags);
 > +		list_add_tail(&gc->list, &gc_list);
 > +		raw_spin_unlock_irqrestore(&gc_lock, flags);
 > +	}
 > +	d->gc = dgc;

Moving this assignment above the for loop allows to get
gc by index as indexing helper relies on domain, not domain
generic chip.

You want me to prepare patches for the above? Maybe you can
split your RFC into 1-6 and 7-8. Then you can have 1-6 applied
independently of irq_domain_generic_chip stuff.

Thanks for the RFC again!

Sebastian


From sebastian.hesselbarth at gmail.com  Fri May  3 22:37:24 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 04 May 2013 04:37:24 +0200
Subject: [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip
In-Reply-To: <20130503214629.880345092@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.880345092@linutronix.de>
Message-ID: <51847464.8040802@gmail.com>

On 05/03/2013 11:50 PM, Thomas Gleixner wrote:
 > Proof of concept patch to demonstrate the new irqdomain support for
 > the generic irq chip. Untested !!
 >
 > Signed-off-by: Thomas Gleixner <tglx at linutronix.de>
 > Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
 > ---
...
 > +		gc->reg_base = sun4i_irq_base;
 > +		gc->chip_types[0].regs.mask = SUN4I_IRQ_ENABLE_REG(i);
 > +		gc->chip_types[0].regs.ack = SUN4I_IRQ_PENDING_REG(i);
 > +		gc->chip_types[0].chip.mask = irq_gc_mask_clr_bit;
 > +		gc->chip_types[0].chip.ack = irq_gc_ack_set_bit;
 > +		gc->chip_types[0].chip.unmask = irq_gc_mask_set_bit;

To help Maxime debug, the three callbacks must be prepended by irq_,
i.e. chip.irq_mask, ...

Sebastian


From viresh.kumar at linaro.org  Sat May  4 02:39:40 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sat, 4 May 2013 12:09:40 +0530
Subject: [PATCH,
 RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <1367507786-505303-3-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-3-git-send-email-arnd@arndb.de>
Message-ID: <CAKohponuYRm+D-FU5_7Ny1PPmwUhFLm9DkAR9iHURur+GFq_kA@mail.gmail.com>

On 2 May 2013 20:46, Arnd Bergmann <arnd at arndb.de> wrote:
> The big.LITTLE cpufreq driver uses the CPU topology API, which
> needs to be reflected in Kconfig to prevent broken configurations.
>
> warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
> has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM && ARM_CPU_TOPOLOGY)
>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Viresh Kumar <viresh.kumar at linaro.org>
> Cc: cpufreq at vger.kernel.org
> Cc: linux-pm at vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/cpufreq/Kconfig.arm | 1 +
>  1 file changed, 1 insertion(+)

With all the discussions we had, please see if you can replace your
patch with this one (Attached too for applying, copy/paste in gmail
will break it):

From: Viresh Kumar <viresh.kumar at linaro.org>
Date: Sat, 4 May 2013 12:03:54 +0530
Subject: [PATCH] cpufreq: ARM big LITTLE: Fix Kconfig entries

This fixes usage of "depends on" and "select" options in Kconfig for ARM big
LITTLE cpufreq driver. Otherwise we get these warnings:

warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM &&
ARM_CPU_TOPOLOGY)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>
---
 drivers/cpufreq/Kconfig.arm | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 634e992..a924408 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -3,17 +3,17 @@
 #

 config ARM_BIG_LITTLE_CPUFREQ
-	tristate
-	depends on ARM_CPU_TOPOLOGY
-	select PM_OPP
+	tristate "Generic ARM big LITTLE CPUfreq driver"
+	depends on ARM_CPU_TOPOLOGY && PM_OPP && HAVE_CLK
+	help
+	  This enables the Generic CPUfreq driver for ARM big.LITTLE platforms.

 config ARM_DT_BL_CPUFREQ
-	tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
-	select ARM_BIG_LITTLE_CPUFREQ
-	depends on OF && HAVE_CLK
+	tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver"
+	depends on ARM_BIG_LITTLE_CPUFREQ && OF
 	help
-	  This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
-	  This gets frequency tables from DT.
+	  This enables probing via DT for Generic CPUfreq driver for ARM
+	  big.LITTLE platform. This gets frequency tables from DT.

 config ARM_EXYNOS_CPUFREQ
 	bool "SAMSUNG EXYNOS SoCs"
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From olof at lixom.net  Sat May  4 03:42:44 2013
From: olof at lixom.net (Olof Johansson)
Date: Sat,  4 May 2013 00:42:44 -0700
Subject: [GIT PULL 0/4] ARM: Second batch of arm-soc changes for 3.10
Message-ID: <1367653368-25291-1-git-send-email-olof@lixom.net>

Hi Linus,

Here is the second batch of branches from arm-soc for 3.10, descriptions
in each pull request including conflict resolutions.

As before, a combined resolved branch has been pushed to our repo for
comparison. Branch name this time is 'second-batch-resolved'.


Thanks,

-Olof



From olof at lixom.net  Sat May  4 03:42:46 2013
From: olof at lixom.net (Olof Johansson)
Date: Sat,  4 May 2013 00:42:46 -0700
Subject: [GIT PULL 2/4] ARM: arm-soc pinctrl changes for Renesas for 3.10
In-Reply-To: <1367653368-25291-1-git-send-email-olof@lixom.net>
References: <1367653368-25291-1-git-send-email-olof@lixom.net>
Message-ID: <1367653368-25291-3-git-send-email-olof@lixom.net>

This is yet another driver change, which is split out just because
of its size. As already in 3.9, a lot of changes are going on here,
as the shmobile platform gets converted from its own pin control
API to the generic drivers/pinctrl subsystem.

Based on agreements with Paul Mundt, we are merging the sh-arch-side
changes here as well.


Conflicts:

arch/arm/mach-shmobile/board-armadillo800eva.c:
Change/remove conflict. Remove.

----------------------------------------------------------------

The following changes since commit 01e34577d8840a5f46693b6231eb6f5a334bb1ae:

  Merge branch 'next/drivers' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/renesas-pinctrl-for-linus

for you to fetch changes up to cb3daf580a6bd798580d274a164e63a598d165c5:

  Merge tag 'renesas-pinmux-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/renesas-pinctrl

----------------------------------------------------------------

Arnd Bergmann (1):
      Merge tag 'renesas-pinmux-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/renesas-pinctrl

Guennadi Liakhovetski (5):
      sh-pfc: Fix a typo and simplify a definition on sh73a0
      ARM: shmobile: sh73a0: Support sparse GPIO numbers
      sh-pfc: sh7372: Add SDHCI and MMCIF pin groups and functions
      sh-pfc: sh73a0: Add SDHI and MMCIF pin groups and functions
      sh-pfc: r8a7740: Add SDHI and MMCIF pin groups and functions

Laurent Pinchart (136):
      sh-pfc: Declare operation structures as const
      sh-pfc: Don't define the per-device pinctrl struct instances as global
      sh-pfc: Drop the sh_pfc_pinctrl spinlock
      sh-pfc: Don't take the sh_pfc spinlock in sh_pfc_map_gpios()
      sh-pfc: Use GPIO_FN instead of PINMUX_GPIO where possible
      sh-pfc: Replace first_gpio and last_gpio with nr_gpios
      sh-pfc: Replace SoC info data and mark ranges with a number of pins
      sh-pfc: Remove unused sh_pfc_soc_info reserved_id field
      sh-pfc: Initialize pinmux_gpio flags statically
      sh-pfc: Make struct pinmux_gpio enum_id field const
      sh-pfc: Shrink the pinctrl GPIO range to include real GPIOs only
      sh-pfc: Don't needlessly check GPIO type in sh_gpio_free()
      sh-pfc: Split pins and functions definition tables
      sh-pfc: Split pins and functions into separate gpio_chip instances
      sh-pfc: Rename struct pinmux_pin to struct sh_pfc_pin
      sh-pfc: Look up IRQ table entries by GPIO number
      sh-pfc: Share the PORT_10_REV, PORT_32 and PORT_32_REV definitions
      sh-pfc: Use pinmux identifiers in the pin muxing API
      sh-pfc: Simplify the sh_pfc_gpio_is_pin() logic
      sh-pfc: Add function to retrieve a pin instance from its pin number
      sh-pfc: Replace pinctrl_add_gpio_range() with gpiochip_add_pin_range()
      sh-pfc: Add support for sparse pin numbers
      ARM: shmobile: ap4-evb: Replace GPIO_PORTx enum with GPIO port numbers
      ARM: shmobile: armadillo: Replace GPIO_PORTx enum with GPIO port numbers
      ARM: shmobile: bonito: Replace GPIO_PORTx enum with GPIO port numbers
      ARM: shmobile: mackerel: Replace GPIO_PORTx enum with GPIO port numbers
      sh-pfc: Expose real groups and functions in pinctrl/pinmux operations
      sh: sh7203: Add pin control resources
      sh: sh7264: Add pin control resources
      sh: sh7269: Add pin control resources
      sh: sh7720: Add pin control resources
      sh: sh7722: Add pin control resources
      sh: sh7723: Add pin control resources
      sh: sh7724: Add pin control resources
      sh: sh7757: Add pin control resources
      sh: sh7785: Add pin control resources
      sh: sh7786: Add pin control resources
      sh: shx3: Add pin control resources
      sh-pfc: Move GPIO registers access functions to gpio.c
      sh-pfc: Don't map data registers individually
      sh-pfc: Drop unused support for 1:1 physical to virtual memory mappings
      sh-pfc: Don't modify pinmux_data_reg SoC data
      sh-pfc: Don't modify sh_pfc_pin SoC data
      sh-pfc: Remove configuration dry-run and free
      sh-pfc: Constify all SoC data
      sh-pfc: Use proper error codes
      sh-pfc: Implement generic pinconf support
      sh-pfc: Merge sh_pfc_reconfig_pin() into sh_pfc_gpio_set_direction()
      sh-pfc: Clean up pin configuration type handling
      sh-pfc: Convert message printing from pr_* to dev_*
      sh-pfc: Return an error if a pin doesn't support the requested direction
      sh-pfc: sh73a0: Add bias (pull-up/down) pinconf support
      sh-pfc: sh73a0: Add LCD and LCD2 pin groups and functions
      sh-pfc: sh73a0: Add SCIFA and SCIFB pin groups and functions
      sh-pfc: sh73a0: Add I2C2 and I2C3 pin groups and functions
      sh-pfc: sh73a0: Add FSI pin groups and functions
      sh-pfc: sh73a0: Add KEYSC pin groups and functions
      sh-pfc: sh73a0: Add BSC pin groups and functions
      sh-pfc: sh73a0: Add USB pin groups and functions
      sh-pfc: sh73a0: Add IrDA pin groups and functions
      sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions
      sh-pfc: r8a7779: Add DU pin groups and functions
      sh-pfc: r8a7779: Add SDHI and MMCIF pin groups and functions
      sh-pfc: r8a7779: Add SCIF pin groups and functions
      sh-pfc: r8a7779: Add HSPI pin groups and functions
      sh-pfc: r8a7779: Add USB0 and USB1 PENC pinmux support
      sh-pfc: r8a7779: Add USB pin groups and functions
      sh-pfc: r8a7779: Add LBSC pin groups and functions
      sh-pfc: r8a7779: Add INTC pin groups and functions
      ARM: shmobile: ag5evm: Register pinctrl mappings for SCIF
      ARM: shmobile: ag5evm: Register pinctrl mappings for I2C
      ARM: shmobile: ag5evm: Register pinctrl mappings for FSI
      ARM: shmobile: ag5evm: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: ag5evm: Register pinctrl mappings for KEYSC
      ARM: shmobile: ag5evm: Register pinctrl mappings for IrDA
      ARM: shmobile: ap4evb: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: armadillo800eva: Register pinctrl mappings for LCDC0
      ARM: shmobile: armadillo800eva: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: bonito: Register pinctrl mappings for LCDC0
      ARM: shmobile: kota2: Register pinctrl mappings for SCIF
      ARM: shmobile: kota2: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: kota2: Register pinctrl mappings for KEYSC
      ARM: shmobile: kota2: Register pinctrl mappings for BSC
      ARM: shmobile: kzm9g: Register pinctrl mappings for LCD
      ARM: shmobile: kzm9g: Register pinctrl mappings for SCIF
      ARM: shmobile: kzm9g: Register pinctrl mappings for I2C
      ARM: shmobile: kzm9g: Register pinctrl mappings for FSI
      ARM: shmobile: kzm9g: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: kzm9g: Register pinctrl mappings for BSC
      ARM: shmobile: kzm9g: Register pinctrl mappings for USB
      ARM: shmobile: mackerel: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: marzen: Register pinctrl mappings for SDHI and MMCIF
      ARM: shmobile: marzen: Register pinctrl mappings for SCIF
      ARM: shmobile: marzen: Register pinctrl mappings for HSPI
      ARM: shmobile: marzen: Register pinctrl mappings for USB
      ARM: shmobile: marzen: Register pinctrl mappings for LBSC
      ARM: shmobile: marzen: Register pinctrl mappings for INTC
      sh-pfc: sh7372: Remove SDHI and MMCIF function GPIOS
      sh-pfc: sh73a0: Remove LCD and LCD2 function GPIOS
      sh-pfc: sh73a0: Remove SCIFA and SCIFB function GPIOS
      sh-pfc: sh73a0: Remove I2C function GPIOS
      sh-pfc: sh73a0: Remove FSI function GPIOS
      sh-pfc: sh73a0: Remove pull-up function GPIOS
      sh-pfc: sh73a0: Remove KEYSC function GPIOS
      sh-pfc: sh73a0: Remove BSC function GPIOS
      sh-pfc: sh73a0: Remove USB function GPIOS
      sh-pfc: sh73a0: Remove IrDA function GPIOS
      sh-pfc: r8a7740: Remove LCD0 and LCD1 function GPIOS
      sh-pfc: r8a7740: Remove SDHI and MMCIF function GPIOS
      sh-pfc: r8a7779: Remove DU1_DOTCLKOUT1 GPIO
      sh-pfc: r8a7779: Remove SDHI and MMCIF function GPIOS
      sh-pfc: r8a7779: Remove SCIF function GPIOS
      sh-pfc: r8a7779: Remove HSPI function GPIOS
      sh-pfc: r8a7779: Remove USB function GPIOS
      sh-pfc: r8a7779: Remove LBSC function GPIOS
      sh-pfc: r8a7779: Remove INTC function GPIOS
      ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs
      ARM: shmobile: sh73a0: Remove LCDC and LCDC2 function GPIOs
      ARM: shmobile: sh73a0: Remove SCIFA and SCIFB function GPIOs
      ARM: shmobile: sh73a0: Remove I2C function GPIOs
      ARM: shmobile: sh73a0: Remove FSI function GPIOs
      ARM: shmobile: sh73a0: Remove pull-up function GPIOS
      ARM: shmobile: sh73a0: Remove KEYSC function GPIOs
      ARM: shmobile: sh73a0: Remove BSC function GPIOs
      ARM: shmobile: sh73a0: Remove USB function GPIOs
      ARM: shmobile: sh73a0: Remove IrDA function GPIOs
      ARM: shmobile: r8a7740: Remove LCD0 and LCD1 function GPIOs
      ARM: shmobile: r8a7740: Remove SDHI and MMCIF function GPIOs
      ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO
      ARM: shmobile: r8a7779: Remove DU function GPIOs
      ARM: shmobile: r8a7779: Remove SDHI and MMCIF function GPIOs
      ARM: shmobile: r8a7779: Remove SCIF function GPIOs
      ARM: shmobile: r8a7779: Remove HSPI function GPIOs
      ARM: shmobile: r8a7779: Remove USB function GPIOs
      ARM: shmobile: r8a7779: Remove LBSC function GPIOs
      ARM: shmobile: r8a7779: Remove INTC function GPIOs

Simon Horman (2):
      Merge branch 'devel' of git://git.kernel.org/.../linusw/linux-pinctrl into pinmux
      Merge branch 'fixes' of git://git.kernel.org/.../linusw/linux-pinctrl into pinmux-base

Wei Yongjun (1):
      sh-pfc: Fix return value check in sh_pfc_register_pinctrl()


 arch/arm/mach-shmobile/board-ag5evm.c          |  172 +-
 arch/arm/mach-shmobile/board-ap4evb.c          |   91 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  158 +-
 arch/arm/mach-shmobile/board-bonito.c          |   52 +-
 arch/arm/mach-shmobile/board-kota2.c           |  208 +-
 arch/arm/mach-shmobile/board-kzm9g.c           |  152 +-
 arch/arm/mach-shmobile/board-mackerel.c        |  102 +-
 arch/arm/mach-shmobile/board-marzen.c          |   75 +-
 arch/arm/mach-shmobile/include/mach/r8a7740.h  |   74 -
 arch/arm/mach-shmobile/include/mach/r8a7779.h  |  324 ++-
 arch/arm/mach-shmobile/include/mach/sh7372.h   |   29 -
 arch/arm/mach-shmobile/include/mach/sh73a0.h   |  363 +--
 arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c        |   13 +-
 arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c        |   13 +-
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c        |   11 +-
 arch/sh/kernel/cpu/sh3/pinmux-sh7720.c         |   14 +-
 arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c        |   14 +-
 arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c        |   14 +-
 arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c        |   13 +-
 arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c        |   13 +-
 arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c        |   14 +-
 arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c        |   14 +-
 arch/sh/kernel/cpu/sh4a/pinmux-shx3.c          |   17 +-
 drivers/pinctrl/sh-pfc/Kconfig                 |    1 +
 drivers/pinctrl/sh-pfc/core.c                  |  261 +-
 drivers/pinctrl/sh-pfc/core.h                  |   54 +-
 drivers/pinctrl/sh-pfc/gpio.c                  |  363 ++-
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c           |  694 ++++-
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c           | 1648 ++++++++++--
 drivers/pinctrl/sh-pfc/pfc-sh7203.c            |  488 ++--
 drivers/pinctrl/sh-pfc/pfc-sh7264.c            |  460 ++--
 drivers/pinctrl/sh-pfc/pfc-sh7269.c            |  624 ++---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c            |  323 ++-
 drivers/pinctrl/sh-pfc/pfc-sh73a0.c            | 2656 +++++++++++++------
 drivers/pinctrl/sh-pfc/pfc-sh7720.c            |  333 +--
 drivers/pinctrl/sh-pfc/pfc-sh7722.c            |  480 ++--
 drivers/pinctrl/sh-pfc/pfc-sh7723.c            |  642 ++---
 drivers/pinctrl/sh-pfc/pfc-sh7724.c            |  638 ++---
 drivers/pinctrl/sh-pfc/pfc-sh7734.c            |   55 +-
 drivers/pinctrl/sh-pfc/pfc-sh7757.c            |  620 ++---
 drivers/pinctrl/sh-pfc/pfc-sh7785.c            |  354 +--
 drivers/pinctrl/sh-pfc/pfc-sh7786.c            |  296 ++-
 drivers/pinctrl/sh-pfc/pfc-shx3.c              |  148 +-
 drivers/pinctrl/sh-pfc/pinctrl.c               |  484 ++--
 drivers/pinctrl/sh-pfc/sh_pfc.h                |  135 +-
 45 files changed, 8367 insertions(+), 5340 deletions(-)


From olof at lixom.net  Sat May  4 03:42:47 2013
From: olof at lixom.net (Olof Johansson)
Date: Sat,  4 May 2013 00:42:47 -0700
Subject: [GIT PULL 3/4] ARM: platform specific firmware interfaces for 3.10
In-Reply-To: <1367653368-25291-1-git-send-email-olof@lixom.net>
References: <1367653368-25291-1-git-send-email-olof@lixom.net>
Message-ID: <1367653368-25291-4-git-send-email-olof@lixom.net>

Two platforms, bcm and exynos have their own firmware interfaces using
the "secure monitor call", this adds support for those.

We had originally planned to have a third set of patches in here, which
would extend support for the existing generic "psci" call that is used
on multiple platforms as well as Xen and KVM guests, but that ended up
getting dropped because the patches were not ready in time.


Conflicts:

None

----------------------------------------------------------------

The following changes since commit c47ceb86748d75280ab478ac0bb76150cde90b7a:

  Merge branch 'next/renesas-pinctrl' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/firmware-for-linus

for you to fetch changes up to 721e0205b07589223343737a9c421d8118d87bba:

  ARM: bcm: mark bcm_kona_smc_init as __init

----------------------------------------------------------------

Arnd Bergmann (3):
      Merge branch 'exynos/clk' into next/firmware
      Merge tag 'secure-exynos-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/firmware
      ARM: bcm: mark bcm_kona_smc_init as __init

Christian Daudt (2):
      ARM: bcm281xx: Add L2 cache enable code
      ARM: bcm281xx: Add DT support for SMC handler

Olof Johansson (1):
      Merge tag 'fw-for-3.10' of git://github.com/broadcom/bcm11351 into next/firmware

Tomasz Figa (5):
      ARM: Add interface for registering and calling firmware-specific operations
      ARM: EXYNOS: Add support for secure monitor calls
      ARM: EXYNOS: Add support for Exynos secure firmware
      ARM: EXYNOS: Add IO mapping for non-secure SYSRAM.
      ARM: EXYNOS: Add secure firmware support to secondary CPU bring-up


 Documentation/arm/firmware.txt                  |  88 ++++++++++++++
 .../devicetree/bindings/arm/samsung-boards.txt  |  10 ++
 Documentation/devicetree/bindings/misc/smc.txt  |  14 +++
 arch/arm/boot/dts/bcm11351.dtsi                 |   5 +
 arch/arm/common/Makefile                        |   2 +
 arch/arm/common/firmware.c                      |  18 +++
 arch/arm/include/asm/firmware.h                 |  66 +++++++++++
 arch/arm/mach-bcm/Makefile                      |   4 +-
 arch/arm/mach-bcm/bcm_kona_smc.c                | 118 +++++++++++++++++++
 arch/arm/mach-bcm/bcm_kona_smc.h                |  80 +++++++++++++
 arch/arm/mach-bcm/bcm_kona_smc_asm.S            |  41 +++++++
 arch/arm/mach-bcm/board_bcm.c                   |  23 ++++
 arch/arm/mach-exynos/Makefile                   |   6 +
 arch/arm/mach-exynos/common.c                   |  35 ++++++
 arch/arm/mach-exynos/common.h                   |   2 +
 arch/arm/mach-exynos/exynos-smc.S               |  22 ++++
 arch/arm/mach-exynos/firmware.c                 |  70 +++++++++++
 arch/arm/mach-exynos/include/mach/map.h         |   3 +
 arch/arm/mach-exynos/mach-exynos4-dt.c          |   1 +
 arch/arm/mach-exynos/platsmp.c                  |  32 ++++-
 arch/arm/mach-exynos/smc.h                      |  31 +++++
 arch/arm/plat-samsung/include/plat/map-s5p.h    |   1 +
 22 files changed, 666 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/arm/firmware.txt
 create mode 100644 Documentation/devicetree/bindings/misc/smc.txt
 create mode 100644 arch/arm/common/firmware.c
 create mode 100644 arch/arm/include/asm/firmware.h
 create mode 100644 arch/arm/mach-bcm/bcm_kona_smc.c
 create mode 100644 arch/arm/mach-bcm/bcm_kona_smc.h
 create mode 100644 arch/arm/mach-bcm/bcm_kona_smc_asm.S
 create mode 100644 arch/arm/mach-exynos/exynos-smc.S
 create mode 100644 arch/arm/mach-exynos/firmware.c
 create mode 100644 arch/arm/mach-exynos/smc.h


From olof at lixom.net  Sat May  4 03:42:48 2013
From: olof at lixom.net (Olof Johansson)
Date: Sat,  4 May 2013 00:42:48 -0700
Subject: [GIT PULL 4/4] ARM: arm-soc board specific changes for 3.10, part 1
In-Reply-To: <1367653368-25291-1-git-send-email-olof@lixom.net>
References: <1367653368-25291-1-git-send-email-olof@lixom.net>
Message-ID: <1367653368-25291-5-git-send-email-olof@lixom.net>

These changes are all for board specific files. These used to make up a
large portion of the ARM changes in the past, but as we are generalizing
the support and moving to device tree probing, this has gotten
significantly smaller. The only platform actually adding new code here
at the moment is Renesas shmobile, as they are still busy converting
their code to device tree and have not come far enough to not need it.

Conflicts:

arch/arm/Kconfig.debug:
Add/add conflict, keep both.

----------------------------------------------------------------

The following changes since commit c77984fd31ca2b2a3227eae717587da60072685f:

  Merge branch 'next/firmware' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/boards-for-linus

for you to fetch changes up to 21bdcc1a2ffce8c9bc7caad711401fff47f99c00:

  ARM: msm: USB_MSM_OTG needs USB_PHY

----------------------------------------------------------------

Aaro Koskinen (2):
      ARM: OMAP1: fix omap_udc registration
      ARM: OMAP: RX-51: add missing regulator supply definitions for lis3lv02d

Andrew Chew (1):
      ARM: OMAP: board-4430sdp: Provide regulator to pwm-backlight

Arnaud Ebalard (1):
      ARM: kirkwood: Add support for NETGEAR ReadyNAS Duo v2 using DT

Arnd Bergmann (6):
      ARM: shmobile: mark mackerel sh_mmcif_device __maybe_unused
      Merge tag 'renesas-boards-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards
      Merge tag 'renesas-boards2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards
      Merge tag 'davinci-for-v3.10/board' of git://git.kernel.org/.../nsekhar/linux-davinci into next/boards
      Merge tag 'omap-for-v3.10/board-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      ARM: msm: USB_MSM_OTG needs USB_PHY

David Brown (1):
      ARM: msm: enable SSBI driver in defconfig

Guennadi Liakhovetski (11):
      ARM: shmobile: use GPIO SD-card detection on armadillo800eva
      ARM: shmobile: switch SDHI0 to GPIO regulator on armadillo800eva
      ARM: shmobile: streamline mackerel SD and MMC devices
      ARM: shmobile: parse DT and configure pinmux early on kzm9g-reference
      ARM: shmobile: SDHI and MMCIF interfaces to kzm9g-reference
      ARM: shmobile: simplify kzm9g Kconfig dependencies
      ARM: shmobile: kzm9g: SDHI0 and SDHI1 use a 3.3V power supply
      ARM: shmobile: sh73a0: move SDHI and MMCIF DT nodes to sh73a0.dtsi
      ARM: shmobile: armadillo800eva: add a fixed voltage regulator for SDHI1
      ARM: shmobile: kzm9g: add fixed voltage regulators for SDHI0 and SDHI2
      ARM: shmobile: kzm9g-reference: fix device-tree bindings and device names

Haojian Zhuang (5):
      ARM: pxa: remove cpu_is_xxx in gpio driver
      ARM: pxa: move PXA_GPIO_TO_IRQ macro
      ARM: mmp: add more compatible names in gpio driver
      ARM: pxa: select PXA935 on saar & tavorevb
      ARM: pxa: move debug uart code

Kuninori Morimoto (1):
      ARM: shmobile: marzen: Use gic_iid macro for ICCIAR / interrupt ID

Lad, Prabhakar (1):
      ARM: davinci: use is IS_ENABLED macro

Olof Johansson (4):
      Merge branch 'armsoc/pxa' of git://github.com/hzhuang1/linux into next/boards
      Merge tag 'msm-defconfig-3.10' of git://git.kernel.org/.../davidb/linux-msm into next/boards
      Merge tag 'boards-3.10' of git://git.infradead.org/users/jcooper/linux into next/boards
      Merge tag 'davinci-for-v3.10/board-2-v2' of git://git.kernel.org/.../nsekhar/linux-davinci into next/boards

Paul Bolle (2):
      omap2+: Remove useless Makefile line
      omap2+: Remove useless Makefile line

Peter Ujfalusi (1):
      ARM: OMAP: zoom: Use pwm stack for lcd and keyboard backlight

Robert Tivy (1):
      ARM: davinci: da850 board: add remoteproc support

Ruslan Bilovol (1):
      ARM: OMAP2+: omap2plus_defconfig: Add support for BMP085 pressure sensor

Sebastian Hesselbarth (1):
      ARM: kirkwood: add MACH_GURUPLUG_DT to defconfig

Sekhar Nori (2):
      ARM: davinci: defconfig: enable CGROUPS
      ARM: davinci: da850 evm: fix const qualifier placement

Simon Guinot (3):
      ARM: Kirkwood: sort board entries by ASCII-code order
      ARM: Kirkwood: DT board setup for CloudBox
      ARM: Kirkwood: update Network Space Mini v2 description

Simon Horman (7):
      Merge branches 'soc' and 'pinmux' into boards-base
      ARM: shmobile: marzen: Reference DT implementation
      ARM: shmobile: kzm9g: Reference DT implementation
      ARM: shmobile: kzm9g: Remove warning about SMP
      ARM: shmobile: kzm9g: Trim reference DT_MACHINE_START
      ARM: shmobile: kzm9g: correct smsc regulator registration
      Revert "ARM: shmobile: streamline mackerel SD and MMC devices"

Stephen Boyd (1):
      ARM: msm: Concentrate defconfig on DT supported devices


 .../devicetree/bindings/gpio/mrvl-gpio.txt      |   7 +-
 arch/arm/Kconfig.debug                          |   9 +
 arch/arm/boot/dts/Makefile                      |   6 +-
 arch/arm/boot/dts/kirkwood-cloudbox.dts         |  89 +++++
 .../dts/kirkwood-netgear_readynas_duo_v2.dts    | 180 ++++++++++
 arch/arm/boot/dts/kirkwood-ns2mini.dts          |   1 +
 arch/arm/boot/dts/mmp2.dtsi                     |   2 +-
 arch/arm/boot/dts/pxa168.dtsi                   |   2 +-
 arch/arm/boot/dts/pxa910.dtsi                   |   2 +-
 arch/arm/boot/dts/r8a7779-marzen-reference.dts  |  47 +++
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts    |  66 ++++
 arch/arm/boot/dts/sh73a0-reference.dtsi         |  24 --
 arch/arm/boot/dts/sh73a0.dtsi                   |  44 +++
 arch/arm/configs/da8xx_omapl_defconfig          |   1 +
 arch/arm/configs/davinci_all_defconfig          |   1 +
 arch/arm/configs/kirkwood_defconfig             |  53 +--
 arch/arm/configs/msm_defconfig                  | 155 ++++++---
 arch/arm/configs/omap2plus_defconfig            |   1 +
 arch/arm/include/debug/pxa.S                    |  33 ++
 arch/arm/mach-davinci/board-da830-evm.c         |   6 +-
 arch/arm/mach-davinci/board-da850-evm.c         |  17 +-
 arch/arm/mach-davinci/board-dm644x-evm.c        |  25 +-
 arch/arm/mach-davinci/board-dm646x-evm.c        |   7 +-
 arch/arm/mach-davinci/board-neuros-osd2.c       |  15 +-
 arch/arm/mach-davinci/board-omapl138-hawk.c     |   6 +
 arch/arm/mach-davinci/devices.c                 |   2 +-
 arch/arm/mach-davinci/usb.c                     |   2 +-
 arch/arm/mach-kirkwood/Kconfig                  | 334 ++++++++++---------
 arch/arm/mach-kirkwood/Makefile                 |  42 +--
 arch/arm/mach-kirkwood/board-dt.c               |  18 +-
 arch/arm/mach-kirkwood/board-ns2.c              |   3 +-
 arch/arm/mach-kirkwood/board-readynas.c         |  28 ++
 arch/arm/mach-kirkwood/common.h                 |  12 +
 arch/arm/mach-mmp/aspenite.c                    |   7 +
 arch/arm/mach-mmp/avengers_lite.c               |   7 +
 arch/arm/mach-mmp/brownstone.c                  |   7 +
 arch/arm/mach-mmp/clock-mmp2.c                  |   2 +-
 arch/arm/mach-mmp/clock-pxa168.c                |   2 +-
 arch/arm/mach-mmp/clock-pxa910.c                |   2 +-
 arch/arm/mach-mmp/flint.c                       |   7 +
 arch/arm/mach-mmp/gplugd.c                      |   7 +
 arch/arm/mach-mmp/include/mach/debug-macro.S    |  30 --
 arch/arm/mach-mmp/jasper.c                      |   8 +
 arch/arm/mach-mmp/mmp-dt.c                      |   4 +-
 arch/arm/mach-mmp/mmp2-dt.c                     |   2 +-
 arch/arm/mach-mmp/mmp2.c                        |   2 +-
 arch/arm/mach-mmp/pxa168.c                      |   2 +-
 arch/arm/mach-mmp/pxa910.c                      |   2 +-
 arch/arm/mach-mmp/tavorevb.c                    |   7 +
 arch/arm/mach-mmp/teton_bga.c                   |   7 +
 arch/arm/mach-mmp/ttc_dkb.c                     |   7 +
 arch/arm/mach-omap1/include/mach/usb.h          |   2 +-
 arch/arm/mach-omap1/usb.c                       |   6 +-
 arch/arm/mach-omap2/Makefile                    |   3 -
 arch/arm/mach-omap2/board-4430sdp.c             |   6 +
 arch/arm/mach-omap2/board-rx51-peripherals.c    |   4 +
 arch/arm/mach-omap2/board-zoom-display.c        |  56 ----
 arch/arm/mach-omap2/board-zoom-peripherals.c    |  53 ++-
 arch/arm/mach-pxa/Kconfig                       |   2 +
 arch/arm/mach-pxa/devices.c                     |  29 +-
 arch/arm/mach-pxa/devices.h                     |   6 +-
 arch/arm/mach-pxa/include/mach/debug-macro.S    |  23 --
 arch/arm/mach-pxa/pxa25x.c                      |  11 +-
 arch/arm/mach-pxa/pxa27x.c                      |   7 +-
 arch/arm/mach-pxa/pxa3xx.c                      |  23 +-
 arch/arm/mach-pxa/pxa930.c                      |  17 +-
 arch/arm/mach-shmobile/Kconfig                  |  27 ++
 arch/arm/mach-shmobile/Makefile                 |   2 +
 arch/arm/mach-shmobile/board-armadillo800eva.c  | 148 ++++++--
 arch/arm/mach-shmobile/board-kzm9g-reference.c  | 107 ++++++
 arch/arm/mach-shmobile/board-kzm9g.c            |  82 ++++-
 arch/arm/mach-shmobile/board-mackerel.c         |   2 +-
 arch/arm/mach-shmobile/board-marzen-reference.c |  75 +++++
 arch/arm/mach-shmobile/board-marzen.c           |  12 +-
 drivers/clk/mmp/clk-mmp2.c                      |   2 +-
 drivers/clk/mmp/clk-pxa168.c                    |   2 +-
 drivers/clk/mmp/clk-pxa910.c                    |   2 +-
 drivers/gpio/gpio-pxa.c                         | 151 +++++----
 include/linux/gpio-pxa.h                        |   1 +
 79 files changed, 1627 insertions(+), 586 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-cloudbox.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
 create mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
 create mode 100644 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
 delete mode 100644 arch/arm/boot/dts/sh73a0-reference.dtsi
 create mode 100644 arch/arm/include/debug/pxa.S
 create mode 100644 arch/arm/mach-kirkwood/board-readynas.c
 delete mode 100644 arch/arm/mach-mmp/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-pxa/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-shmobile/board-kzm9g-reference.c
 create mode 100644 arch/arm/mach-shmobile/board-marzen-reference.c


From olof at lixom.net  Sat May  4 03:42:45 2013
From: olof at lixom.net (Olof Johansson)
Date: Sat,  4 May 2013 00:42:45 -0700
Subject: [GIT PULL 1/4] ARM: arm-soc driver changes for 3.10
In-Reply-To: <1367653368-25291-1-git-send-email-olof@lixom.net>
References: <1367653368-25291-1-git-send-email-olof@lixom.net>
Message-ID: <1367653368-25291-2-git-send-email-olof@lixom.net>

This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem
specific interfaces.

In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into
platform specific interface, or to get called from platform specific
code, as long as all information about the hardware is provided
through a device tree.

Most of the drivers we touch this time are for clocksource. Since
now most of them are part of drivers/clocksource, I expect that we
won't have to touch these again from arm-soc and can let the
clocksource maintainers take care of these in the future.

Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the
merge conflicts.

There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface
for taking devices on the SoC out of reset or back into reset.
Patches to use this interface on i.MX follow later in this merge
window, and we are going to have other platforms (at least tegra
and sirf) get converted in 3.11. This will let us get rid of
platform specific callbacks in a number of platform independent
device drivers.


Conflicts:

arch/arm/Kconfig:
- Remove/change conflict. Take out the HAVE_ARM_TWD select.
- Change/change conflict on ARCH_NR_GPIO. Keep 392 for U8500 and the
  split VT8500/SUNXI entries

arch/arm/mach-omap2/*:
Keep all versions from the branch (caused by a duplicate commits from
the ARM tree).

drivers/clocksource/Makefile:
Add/add, keep both.

drivers/irqchip/Makefile:
Add/add, keep both. This file can do with a fresh sorting at some
point.

drivers/irqchip/irq-s3c24xx.c: 
- Include statements: Add/add, keep both.
- reg_pending change: Keep first line from HEAD and second from
branch.

drivers/pinctrl/pinctrl-samsung.c:
Add/add. Move new 5250 entry up into upper ifdef.

drivers/pinctrl/pinctrl-samsung.h:
Add/add, keep both.

----------------------------------------------------------------

The following changes since commit 1db772216f48978d5146b858586f6178433aad38:

  Merge branch 'for-3.10' of git://linux-nfs.org/~bfields/linux

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/drivers-for-linus

for you to fetch changes up to bc8fd900c4d460b4e4bf785bb48bfced0ac9941b:

  irqchip: s3c24xx: add missing __init annotations

----------------------------------------------------------------

Abhilash Kesavan (1):
      ARM: dts: Add max77686 device tree support for CROS5250

Andrzej Hajda (1):
      clk: exynos4: Add missing CMU_TOP and ISP clocks

Arnd Bergmann (25):
      Merge branch 'next/timer-samsung' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/irq-s3c24xx' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/pinctrl-exynos' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge tag 'at91-driversLCD' of git://github.com/at91linux/linux-at91 into next/drivers
      Merge tag 'renesas-intc-external-irq-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/drivers
      Merge tag 'renesas-clocksource-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/drivers
      Merge tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/drivers
      Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into next/drivers
      Merge branch 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx into next/drivers
      Merge tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/drivers
      Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/drivers
      Merge tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/.../tmlind/linux-omap into next/drivers
      Merge branch 'tegra/soc' into next/drivers
      Merge branch 'depends/clk' into next/drivers
      Merge tag 'tegra-for-3.10-clk' of git://git.kernel.org/.../swarren/linux-tegra into next/drivers
      Merge tag 'ux500-pinctrl' of git://git.kernel.org/.../linusw/linux-stericsson into next/drivers
      Merge tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge tag 'mct-exynos-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge tag 'pmu-exynos-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge tag 'timer-samsung-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'samsung/exynos-multiplatform' into next/drivers
      clocksource: exynos_mct: fix build error on non-DT
      ARM: exynos: restore mach/regs-clock.h for exynos5
      irqchip: s3c24xx: add missing __init annotations

Axel Lin (2):
      clocksource: mct: Add terminating entry for exynos_mct_ids table
      pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()

Bastian Hecht (1):
      irqchip: intc-irqpin: Add support for shared interrupt lines

Chanho Park (5):
      irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
      irqchip: exynos-combiner: Correct combined IRQs for exynos4
      ARM: EXYNOS: Enable PMUs for exynos4
      ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
      ARM: EXYNOS: Add arm-pmu DT binding for exynos421x

Dan Carpenter (1):
      reset: NULL deref on allocation failure

Dongjin Kim (3):
      ARM: dts: Add board dts file for ODROID-X
      ARM: dts: Fix the timing property of MSHC controller for exynos4412-odroidx
      ARM: dts: enable RTC device node for exynos4412-odroidx

Doug Anderson (2):
      clocksource: mct: Add missing semicolons in exynos_mct.c
      ARM: dts: Disable the RTC by default on exynos5

Ezequiel Garcia (8):
      ARM: omap2: gpmc: Mark local scoped functions static
      ARM: omap2: gpmc: Remove unused gpmc_round_ns_to_ticks() function
      ARM: omap2: gpmc: Fix gpmc_cs_reserved() return value
      ARM: omap2: gpmc-nand: Print something useful on CS request failure
      ARM: omap2: gpmc-onenand: Print something useful on CS request failure
      ARM: omap2: gpmc-onenand: Replace pr_err() with dev_err()
      ARM: omap2: gpmc-onenand: Replace printk KERN_ERR with dev_warn()
      ARM: omap2: gpmc: Remove redundant chip select out of range check

Fabio Baltieri (1):
      ARM: ux500: remove redundant DB8500_PIN_SLEEP definition

Giridhar Maruthy (3):
      ARM: dts: remove disabled status from watchdog node for exynos5440-ssdk5440
      ARM: dts: remove disabled status from RTC node for exynos5440-ssdk5440
      ARM: dts: change compatible value for exynos5440 i2c

Girish K S (1):
      ARM: dts: Add initial board support file for exynos5250-arndale

Heiko Stueber (1):
      clk: samsung: fix pm init on non-dt platforms

Heiko Stuebner (28):
      ARM: S3C24XX: move s3c244x irq init to common irq code
      ARM: S3C24XX: create dedicated irq init functions for s3c2440 and s3c2442
      ARM: S3C24XX: move s3c2440 irqs to common irq code
      ARM: S3C24XX: integrate s3c2440 irqs into common init
      ARM: S3C24XX: transform s3c2442 irqs into new structure
      ARM: S3C24XX: transform s3c2440 irqs into new structure
      ARM: S3C24XX: use samsung_sync_wakemask in s3c2412 pm
      ARM: S3C24XX: move s3c2412 irq init to common code
      ARM: S3C24XX: modify s3c2412 irq init to initialize all irqs
      ARM: S3C24XX: transform s3c2412 irqs into new structure
      ARM: S3C24XX: include first 4 bits of the eint register in irq mapping
      ARM: S3C24XX: add soc_is_s3c2412 option
      ARM: S3C24XX: handle s3c2412 eints using new infrastructure
      ARM: S3C24XX: fix redundant checks in the irq mapping function
      ARM: S3C24XX: fix irq parent check
      ARM: S3C24XX: move s3c24xx_init_irq to s3c2410_init_irq
      ARM: S3C24XX: make s3c24xx_init_intc static
      ARM: S3C24XX: add handle_irq function
      clk: samsung: register clk_div_tables for divider clocks
      clk: samsung: always allocate the clk_table
      clk: samsung: add infrastructure to add separate aliases
      ARM: S3C24XX: move irq driver to drivers/irqchip
      irqchip: s3c24xx: fix comments on some camera interrupts
      irqchip: s3c24xx: fix irqlist of second s3c2416 controller
      irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
      irqchip: s3c24xx: globally keep track of the created intc instances
      irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
      irqchip: s3c24xx: add devicetree support

Javier Martinez Canillas (3):
      ARM: OMAP2+: return -ENODEV if GPMC child device creation fails
      ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child()
      ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes

Jingoo Han (2):
      ARM: EXYNOS: Add AUXDATA for DP controller
      ARM: dts: Add device tree node for DP controller for exynos5250

Johan Hovold (3):
      ARM: at91/avr32/atmel_lcdfb: add bus-clock entry
      atmel_lcdfb: move lcdcon2 register access to compute_hozval
      ARM: at91/avr32/atmel_lcdfb: add platform device-id table

Jon Hunter (26):
      Merge commit '6bb27d7349db51b50c40534710fe164ca0d58902' into omap-timer-for-v3.10
      ARM: OMAP2+: Display correct system timer name
      ARM: OMAP2+: Remove hard-coded test on timer ID
      ARM: OMAP2+: Simplify system timer clock definitions
      ARM: OMAP2+: Simplify system timers definitions
      ARM: OMAP3: Update clocksource timer selection
      ARM: OMAP2+: Store ID of system timers in timer structure
      ARM: OMAP4+: Fix sparse warning in system timers
      Merge commit '31d9adca82ce65e5c99d045b5fd917c702b6fce3' into tmp
      ARM: OMAP2+: Simplify code configuring ONENAND devices
      ARM: OMAP2+: Add variable to store number of GPMC waitpins
      ARM: OMAP2+: Add structure for storing GPMC settings
      ARM: OMAP2+: Add function for configuring GPMC settings
      ARM: OMAP2+: Convert ONENAND to use gpmc_cs_program_settings()
      ARM: OMAP2+: Convert NAND to use gpmc_cs_program_settings()
      ARM: OMAP2+: Convert SMC91x to use gpmc_cs_program_settings()
      ARM: OMAP2+: Convert TUSB to use gpmc_cs_program_settings()
      ARM: OMAP2+: Don't configure of chip-select options in gpmc_cs_configure()
      ARM: OMAP2+: Add function to read GPMC settings from device-tree
      ARM: OMAP2+: Add additional GPMC timing parameters
      ARM: OMAP2+: Add device-tree support for NOR flash
      ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT
      ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT
      ARM: OMAP2+: Detect incorrectly aligned GPMC base address
      ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable
      ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails

Julien Delacou (1):
      ARM: ux500: u8500: fix pinctrl IDLE state definition for SPI2

Kukjin Kim (7):
      ARM: dts: cleanup exynos5440.dtsi
      gpio: samsung: fixes build warning with s3c2410_defconfig
      ARM: dts: re-organized cpu node for exynos5440
      Merge branch 'next/timer-samsung' into next/clk-exynos
      Merge branch 'next/mct-exynos' into next/clk-exynos
      ARM: SAMSUNG: change GENERIC_GPIO to ARCH_REQUIRE_GPIOLIB
      Merge commit 'v3.9-rc5' into next/clk-exynos

Lee Jones (1):
      ARM: ux500: Add Snowball pin configuration for user LED

Leela Krishna Amudala (1):
      clk: exynos5250: register display block gate clocks to common clock framework

Lukasz Majewski (1):
      clk: exynos4: Export clocks used by exynos cpufreq drivers

Magnus Damm (22):
      clocksource: sh_cmt: Take care of clk_put() when setup_irq() fails
      clocksource: sh_cmt: Initialize 'max_match_value' and 'lock' in sh_cmt_setup()
      clocksource: sh_cmt: Introduce per-register functions
      clocksource: sh_cmt: Consolidate platform_set_drvdata() call
      clocksource: sh_cmt: CMSTR and CMCSR register access update
      clocksource: sh_cmt: CMCNT and CMCOR register access update
      clocksource: sh_cmt: Add control register callbacks
      clocksource: sh_cmt: Add CMT register layout comment
      irqchip: Renesas INTC External IRQ pin driver
      ARM: shmobile: irq_pin() for static IRQ pin assignment
      ARM: shmobile: INTC External IRQ pin driver on sh73a0
      ARM: shmobile: INTC External IRQ pin driver on r8a7779
      irqchip: intc-irqpin: Whitespace fixes
      irqchip: intc-irqpin: Cache mapped IRQ
      irqchip: intc-irqpin: Add force comments
      irqchip: intc-irqpin: Make use of devm functions
      irqchip: intc-irqpin: GPL header for platform data
      irqchip: Renesas IRQC driver
      ARM: shmobile: Make sh73a0 INTC irqpin platform data static
      ARM: shmobile: Make r8a7779 INTC irqpin platform data static
      irqchip: intc-irqpin: Initial DT support
      irqchip: irqc: Add DT support

Mark Jackson (1):
      ARM: OMAP: Clear GPMC bits when applying new setting.

Michal Simek (4):
      arm: zynq: Use standard timer binding
      arm: zynq: Move timer to clocksource interface
      arm: zynq: Do not use xilinx specific function names
      arm: zynq: Move timer to generic location

Olof Johansson (2):
      Merge branch 'reset/for_v3.10' of git://git.pengutronix.de/git/pza/linux into next/drivers
      Merge branch 'samsung/exynos-multiplatform' into next/drivers

Patrice Chotard (1):
      ARM: ux500: 8500: add ab8500-musb pinctrl support

Peter De Schrijver (14):
      clk: tegra: provide dummy cpu car ops
      clk: tegra: Refactor PLL programming code
      clk: tegra: Add TEGRA_PLL_BYPASS flag
      clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
      clk: tegra: Add PLL post divider table
      clk: tegra: move from a lock bit idx to a lock mask
      clk: tegra: Add new fields and PLL types for Tegra114
      clk: tegra: Add flags to tegra_clk_periph()
      clk: tegra: Workaround for Tegra114 MSENC problem
      ARM: tegra: Define Tegra114 CAR binding
      clk: tegra: Implement clocks for Tegra114
      clk: tegra: devicetree match for nvidia,tegra114-car
      ARM: dt: Add references to tegra_car clocks
      clk: tegra: Remove forced clk_enable of uartd

Philipp Zabel (1):
      reset: Add reset controller API

Prasanna Kumar (1):
      ARM: dts: Set up power domain for MFC and G-scaler for exynos5250

Prashant Gaikwad (1):
      clk: tegra: Fix cdev1 and cdev2 IDs

Roger Quadros (20):
      ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
      ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
      ARM: OMAP3: Beagle: Adapt to ehci-omap changes
      ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
      ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
      ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
      ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
      ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
      ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
      ARM: OMAP: devkit8000: Adapt to ehci-omap changes
      ARM: OMAP3: igep0020: Adapt to ehci-omap changes
      ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
      ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
      ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
      ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
      ARM: OMAP3: overo: Adapt to ehci-omap changes
      ARM: OMAP: zoom: Adapt to ehci-omap changes
      ARM: dts: OMAP4: Add HS USB Host IP nodes
      ARM: dts: OMAP3: Add HS USB Host IP nodes
      ARM: dts: omap3-beagle: Add USB Host support

Romain Naour (5):
      ARM: SAMSUNG: Rename s5p-time to samsung-time
      ARM: S3C24XX: Add samsung-time support for s3c24xx
      ARM: S3C64XX: Add samsung-time support for s3c64xx
      ARM: S5PC100: Add samsung-time support for s5pc100
      ARM: SAMSUNG: Remove unused plat-samsung/time.c

Russell King (2):
      ARM: cleanup: OMAP hwmod error checking
      ARM: OMAP: use consistent error checking

Sachin Kamat (12):
      ARM: dts: Add vmmc regulator node in exynos4412-origen.dts
      ARM: dts: Add sdhci node for exynos4412-origen
      ARM: dts: Update MFC DT binding documentation
      ARM: dts: Add MFC codec support for EXYNOS4 DT machines
      ARM: dts: Add MFC codec support to SMDKV310 DT
      ARM: dts: Add MFC codec support to Origen DT
      ARM: dts: Add MFC codec entry to exynos4412-origen DT
      ARM: dts: Add MFC codec entry to exynos4412-smdk4412 DT
      ARM: dts: Add MSHC node for exynos4412-origen DT
      ARM: dts: Add s5m8767 PMIC node to exynos4412-origen DT
      ARM: dts: Add sdhci node for exynos4412-smdk4412
      clk: samsung: Fix compilation error

Simon Horman (4):
      clocksource: sh_cmt: Set initcall level to subsys
      clocksource: sh_tmu: Set initcall level to subsys
      clocksource: em_sti: Set initcall level to subsys
      clocksource: sh_mtu2: Set initcall level to subsys

Stephen Warren (6):
      pinctrl: bcm2835: make use of of_property_read_u32_index()
      Merge branch 'for-3.10/soc' into for-3.10/clk
      Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into for-3.10/clk
      clk: tegra: defer application of init table
      clk: tegra: fix enum tegra114_clk to match binding
      dt: describe base reset signal binding

Sylwester Nawrocki (3):
      clk: exynos4: Correct sclk_mfc clock definition
      clk: exynos4: Add camera related clock definitions
      clk: exynos4: export clocks required for fimc-is

Thierry Reding (2):
      clk: tegra: Export peripheral reset functions
      clk: tegra: Make gr2d and gr3d clocks children of pll_c

Thomas Abraham (28):
      pinctrl: exynos: add exynos5250 SoC specific data
      gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250
      ARM: EXYNOS: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled
      ARM: dts: add board dts file for EXYNOS4412 based Origen board
      ARM: EXYNOS: add a register base address variable in mct controller driver
      ARM: EXYNOS: prepare an array of MCT interrupt numbers and use it
      ARM: EXYNOS: add device tree support for MCT controller driver
      ARM: EXYNOS: allow dt based discovery of mct controller using clocksource_of_init
      ARM: dts: add mct device tree node for all supported Exynos SoC's
      ARM: EXYNOS: remove static io-remapping of mct registers for Exynos5
      ARM: EXYNOS: move mct driver to drivers/clocksource
      clk: samsung: add common clock framework helper functions for Samsung platforms
      clk: samsung: add pll clock registration helper functions
      clk: exynos4: register clocks using common clock framework
      clk: exynos5250: register clocks using common clock framework
      clk: exynos5440: register clocks using common clock framework
      ARM: EXYNOS: Migrate clock support to common clock framework
      ARM: EXYNOS: Initialize the clocks prior to timer initialization
      ARM: EXYNOS: allow legacy board support to specify xxti and xusbxti clock speed
      ARM: EXYNOS: remove auxdata table from exynos4/5 dt machine file
      clocksource: mct: use fin_pll clock as the tick clock source for mct
      clocksource: mct: add support for mct clock setup
      ARM: dts: add Exynos4 and Exynos5 clock controller nodes
      ARM: dts: add clock provider information for all controllers in Exynos4 SoCs
      ARM: dts: add clock provider information for all controllers in Exynos5250 SoC
      ARM: dts: add clock provider information for all controllers in Exynos5440 SoC
      ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms
      ARM: EXYNOS: fix compilation error introduced due to common clock migration

Tomasz Figa (17):
      clk: exynos4: Use mout_mpll_user_* on Exynos4x12
      clk: exynos4: Add missing mout_mipihsi clock
      clk: exynos4: Add missing sclk_audio0 clock
      clk: exynos4: Export sclk_pcm0
      clk: exynos4: Move dac and mixer to Exynos4210-specific clocks
      clk: samsung: Remove unimplemented ops for pll
      clk: exynos4: Export mout_core clock of Exynos4210
      clk: exynos4: Add G3D clocks
      clk: exynos4: Add missing mout_sata on Exynos4210
      clk: exynos4: Define {E,V}PLL registers
      clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
      clk: exynos4: Remove SoC-specific registers from save list
      clk: exynos4: Add E4210 prefix to LCD1 clock registers
      clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
      clk: exynos4: Remove E4X12 prefix from SRC_DMC register
      clk: exynos4: Add missing registers to suspend save list
      clk: exynos4: Add support for SoC-specific register save list

Tony Lindgren (3):
      Merge commit '7185684' into omap-for-v3.10/timer
      Merge branch 'omap-timer-for-v3.10' of git://github.com/jonhunter/linux into omap-for-v3.10/timer
      Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux into omap-for-v3.10/gpmc

Tony Prisk (8):
      of: Add support for reading a u32 from a multi-value property.
      of: Remove duplicated code for validating property and value
      arm: vt8500: Increase available GPIOs on arch-vt8500
      pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
      arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver
      arm: vt8500: Remove gpio devicetree nodes
      gpio: vt8500: Remove arch-vt8500 gpio driver
      irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure

Tushar Behera (2):
      clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
      clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}

Vivek Gautam (2):
      ARM: dts: Enabling ehci-s5p driver for EXYNOS5250
      ARM: dts: Enabling ohci-exynos driver for EXYNOS5250

Yen Lin (1):
      clk: tegra: Fix periph_clk_to_bit macro


 .../devicetree/bindings/bus/ti-gpmc.txt         |  103 +-
 .../devicetree/bindings/clock/exynos4-clock.txt |  288 +++
 .../bindings/clock/exynos5250-clock.txt         |  177 ++
 .../bindings/clock/exynos5440-clock.txt         |   61 +
 .../bindings/clock/nvidia,tegra114-car.txt      |  303 +++
 .../bindings/clock/nvidia,tegra20-car.txt       |    4 +-
 .../devicetree/bindings/gpio/gpio-vt8500.txt    |   24 -
 .../samsung,s3c24xx-irq.txt                     |   53 +
 .../devicetree/bindings/media/s5p-mfc.txt       |   21 +
 .../devicetree/bindings/mtd/gpmc-nor.txt        |   98 +
 .../devicetree/bindings/mtd/gpmc-onenand.txt    |    3 +
 .../devicetree/bindings/net/gpmc-eth.txt        |   97 +
 .../bindings/pinctrl/pinctrl-vt8500.txt         |   57 +
 .../devicetree/bindings/reset/reset.txt         |   75 +
 .../bindings/timer/cadence,ttc-timer.txt        |   17 +
 .../bindings/timer/samsung,exynos4210-mct.txt   |   68 +
 .../devicetree/bindings/usb/exynos-usb.txt      |   40 +
 arch/arm/Kconfig                                |   16 +-
 arch/arm/boot/dts/Makefile                      |    3 +
 arch/arm/boot/dts/cros5250-common.dtsi          |  138 ++
 arch/arm/boot/dts/exynos4.dtsi                  |   58 +
 arch/arm/boot/dts/exynos4210-origen.dts         |   18 +
 arch/arm/boot/dts/exynos4210-smdkv310.dts       |   18 +
 arch/arm/boot/dts/exynos4210-trats.dts          |   12 +
 arch/arm/boot/dts/exynos4210.dtsi               |   36 +
 arch/arm/boot/dts/exynos4212.dtsi               |   22 +
 arch/arm/boot/dts/exynos4412-odroidx.dts        |  111 +
 arch/arm/boot/dts/exynos4412-origen.dts         |  432 ++++
 arch/arm/boot/dts/exynos4412-smdk4412.dts       |   25 +
 arch/arm/boot/dts/exynos4412.dtsi               |   26 +
 arch/arm/boot/dts/exynos4x12.dtsi               |    6 +
 arch/arm/boot/dts/exynos5250-arndale.dts        |  129 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |   20 +
 arch/arm/boot/dts/exynos5250-snow.dts           |   11 +
 arch/arm/boot/dts/exynos5250.dtsi               |  149 ++
 arch/arm/boot/dts/exynos5440-ssdk5440.dts       |   19 +-
 arch/arm/boot/dts/exynos5440.dtsi               |   67 +-
 arch/arm/boot/dts/omap3-beagle.dts              |   71 +
 arch/arm/boot/dts/omap3.dtsi                    |   31 +
 arch/arm/boot/dts/omap4.dtsi                    |   30 +
 arch/arm/boot/dts/tegra114-dalmore.dts          |    1 -
 arch/arm/boot/dts/tegra114-pluto.dts            |    1 -
 arch/arm/boot/dts/tegra114.dtsi                 |    8 +-
 arch/arm/boot/dts/vt8500.dtsi                   |   10 +-
 arch/arm/boot/dts/wm8505.dtsi                   |   10 +-
 arch/arm/boot/dts/wm8650.dtsi                   |   10 +-
 arch/arm/boot/dts/wm8850.dtsi                   |   10 +-
 arch/arm/boot/dts/zynq-7000.dtsi                |   45 +-
 arch/arm/boot/dts/zynq-zc702.dts                |   10 -
 arch/arm/mach-at91/at91sam9261.c                |    2 +
 arch/arm/mach-at91/at91sam9261_devices.c        |    6 +-
 arch/arm/mach-at91/at91sam9263.c                |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c        |    2 +-
 arch/arm/mach-at91/at91sam9g45.c                |    2 +
 arch/arm/mach-at91/at91sam9g45_devices.c        |    6 +-
 arch/arm/mach-at91/at91sam9rl.c                 |    1 +
 arch/arm/mach-at91/at91sam9rl_devices.c         |    2 +-
 arch/arm/mach-exynos/Kconfig                    |   12 +-
 arch/arm/mach-exynos/Makefile                   |    6 -
 arch/arm/mach-exynos/clock-exynos4.c            | 1601 --------------
 arch/arm/mach-exynos/clock-exynos4.h            |   35 -
 arch/arm/mach-exynos/clock-exynos4210.c         |  187 --
 arch/arm/mach-exynos/clock-exynos4212.c         |  201 --
 arch/arm/mach-exynos/clock-exynos5.c            | 1645 --------------
 arch/arm/mach-exynos/common.c                   |   88 +-
 arch/arm/mach-exynos/common.h                   |   10 +-
 arch/arm/mach-exynos/include/mach/irqs.h        |   19 +-
 arch/arm/mach-exynos/include/mach/map.h         |    1 -
 arch/arm/mach-exynos/include/mach/regs-mct.h    |   53 -
 arch/arm/mach-exynos/mach-armlex4210.c          |    3 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c          |  122 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c          |  141 +-
 arch/arm/mach-exynos/mach-nuri.c                |    5 +-
 arch/arm/mach-exynos/mach-origen.c              |    5 +-
 arch/arm/mach-exynos/mach-smdk4x12.c            |    5 +-
 arch/arm/mach-exynos/mach-smdkv310.c            |    7 +-
 arch/arm/mach-exynos/mach-universal_c210.c      |    9 +-
 arch/arm/mach-omap2/board-3430sdp.c             |   21 +-
 arch/arm/mach-omap2/board-3630sdp.c             |   21 +-
 arch/arm/mach-omap2/board-am3517crane.c         |   24 +-
 arch/arm/mach-omap2/board-am3517evm.c           |   17 +-
 arch/arm/mach-omap2/board-cm-t35.c              |   20 +-
 arch/arm/mach-omap2/board-cm-t3517.c            |   22 +-
 arch/arm/mach-omap2/board-devkit8000.c          |    8 -
 arch/arm/mach-omap2/board-generic.c             |    2 +-
 arch/arm/mach-omap2/board-igep0020.c            |   32 +-
 arch/arm/mach-omap2/board-omap3beagle.c         |   32 +-
 arch/arm/mach-omap2/board-omap3evm.c            |   25 +-
 arch/arm/mach-omap2/board-omap3pandora.c        |   21 +-
 arch/arm/mach-omap2/board-omap3stalker.c        |   17 +-
 arch/arm/mach-omap2/board-omap3touchbook.c      |   17 +-
 arch/arm/mach-omap2/board-omap4panda.c          |   55 +-
 arch/arm/mach-omap2/board-overo.c               |   16 +-
 arch/arm/mach-omap2/board-zoom.c                |   16 +-
 arch/arm/mach-omap2/common.h                    |    3 +-
 arch/arm/mach-omap2/gpmc-nand.c                 |   42 +-
 arch/arm/mach-omap2/gpmc-onenand.c              |  118 +-
 arch/arm/mach-omap2/gpmc-smc91x.c               |   30 +-
 arch/arm/mach-omap2/gpmc.c                      |  544 +++--
 arch/arm/mach-omap2/gpmc.h                      |   43 +-
 arch/arm/mach-omap2/timer.c                     |  124 +-
 arch/arm/mach-omap2/usb-host.c                  |  160 +-
 arch/arm/mach-omap2/usb-tusb6010.c              |   62 +-
 arch/arm/mach-omap2/usb.h                       |    9 +
 arch/arm/mach-s3c24xx/Kconfig                   |    7 +
 arch/arm/mach-s3c24xx/Makefile                  |    8 +-
 arch/arm/mach-s3c24xx/common.h                  |    4 +
 .../arm/mach-s3c24xx/include/mach/entry-macro.S |   70 -
 arch/arm/mach-s3c24xx/include/mach/irqs.h       |   58 +-
 arch/arm/mach-s3c24xx/irq-s3c2412.c             |  215 --
 arch/arm/mach-s3c24xx/irq-s3c2440.c             |  128 --
 arch/arm/mach-s3c24xx/irq-s3c244x.c             |  142 --
 arch/arm/mach-s3c24xx/mach-amlm5900.c           |    7 +-
 arch/arm/mach-s3c24xx/mach-anubis.c             |    6 +-
 arch/arm/mach-s3c24xx/mach-at2440evb.c          |    6 +-
 arch/arm/mach-s3c24xx/mach-bast.c               |    6 +-
 arch/arm/mach-s3c24xx/mach-gta02.c              |    6 +-
 arch/arm/mach-s3c24xx/mach-h1940.c              |   12 +-
 arch/arm/mach-s3c24xx/mach-jive.c               |    6 +-
 arch/arm/mach-s3c24xx/mach-mini2440.c           |    6 +-
 arch/arm/mach-s3c24xx/mach-n30.c                |   10 +-
 arch/arm/mach-s3c24xx/mach-nexcoder.c           |    6 +-
 arch/arm/mach-s3c24xx/mach-osiris.c             |    6 +-
 arch/arm/mach-s3c24xx/mach-otom.c               |    6 +-
 arch/arm/mach-s3c24xx/mach-qt2410.c             |    6 +-
 arch/arm/mach-s3c24xx/mach-rx1950.c             |    6 +-
 arch/arm/mach-s3c24xx/mach-rx3715.c             |   11 +-
 arch/arm/mach-s3c24xx/mach-smdk2410.c           |    6 +-
 arch/arm/mach-s3c24xx/mach-smdk2413.c           |   14 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c           |    4 +-
 arch/arm/mach-s3c24xx/mach-smdk2440.c           |    6 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c           |    4 +-
 arch/arm/mach-s3c24xx/mach-tct_hammer.c         |    6 +-
 arch/arm/mach-s3c24xx/mach-vr1000.c             |    6 +-
 arch/arm/mach-s3c24xx/mach-vstms.c              |    6 +-
 arch/arm/mach-s3c24xx/pm-s3c2412.c              |    8 +
 arch/arm/mach-s3c64xx/Kconfig                   |    2 +
 arch/arm/mach-s3c64xx/mach-anw6410.c            |    4 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c           |    4 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                |    4 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c           |    4 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                |    4 +-
 arch/arm/mach-s3c64xx/mach-real6410.c           |    4 +-
 arch/arm/mach-s3c64xx/mach-smartq.c             |    2 +
 arch/arm/mach-s3c64xx/mach-smartq5.c            |    3 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c            |    3 +-
 arch/arm/mach-s3c64xx/mach-smdk6400.c           |    4 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c           |    4 +-
 arch/arm/mach-s5p64x0/Kconfig                   |    4 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c           |    6 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c           |    6 +-
 arch/arm/mach-s5pc100/Kconfig                   |    1 +
 arch/arm/mach-s5pc100/mach-smdkc100.c           |    4 +-
 arch/arm/mach-s5pv210/Kconfig                   |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c             |    6 +-
 arch/arm/mach-s5pv210/mach-goni.c               |    6 +-
 arch/arm/mach-s5pv210/mach-smdkc110.c           |    6 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c           |    6 +-
 arch/arm/mach-s5pv210/mach-torbreck.c           |    6 +-
 arch/arm/mach-shmobile/Kconfig                  |    2 +
 arch/arm/mach-shmobile/board-kzm9g.c            |   14 +-
 arch/arm/mach-shmobile/include/mach/common.h    |    1 +
 arch/arm/mach-shmobile/include/mach/irqs.h      |    4 +
 arch/arm/mach-shmobile/intc-r8a7779.c           |   53 +-
 arch/arm/mach-shmobile/intc-sh73a0.c            |  117 -
 arch/arm/mach-shmobile/setup-sh73a0.c           |  126 ++
 arch/arm/mach-tegra/tegra.c                     |    3 +
 arch/arm/mach-ux500/board-mop500-pins.c         |   34 +-
 arch/arm/mach-vt8500/Kconfig                    |    1 +
 arch/arm/mach-vt8500/Makefile                   |    2 +-
 arch/arm/mach-vt8500/common.h                   |    6 -
 arch/arm/mach-vt8500/vt8500.c                   |   14 +-
 arch/arm/mach-zynq/Kconfig                      |    1 +
 arch/arm/mach-zynq/Makefile                     |    2 +-
 arch/arm/mach-zynq/common.c                     |    3 +-
 arch/arm/mach-zynq/common.h                     |    2 -
 arch/arm/mach-zynq/timer.c                      |  324 ---
 arch/arm/plat-samsung/Kconfig                   |    6 +-
 arch/arm/plat-samsung/Makefile                  |    3 +-
 arch/arm/plat-samsung/devs.c                    |    2 +-
 arch/arm/plat-samsung/include/plat/cpu.h        |   15 +-
 arch/arm/plat-samsung/include/plat/s5p-time.h   |   40 -
 .../plat-samsung/include/plat/samsung-time.h    |   53 +
 .../plat-samsung/{s5p-time.c => samsung-time.c} |  138 +-
 arch/arm/plat-samsung/time.c                    |  287 ---
 arch/avr32/mach-at32ap/at32ap700x.c             |    6 +-
 drivers/Kconfig                                 |    2 +
 drivers/Makefile                                |    3 +
 drivers/clk/Makefile                            |    1 +
 drivers/clk/samsung/Makefile                    |    8 +
 drivers/clk/samsung/clk-exynos4.c               | 1091 +++++++++
 drivers/clk/samsung/clk-exynos5250.c            |  523 +++++
 drivers/clk/samsung/clk-exynos5440.c            |  139 ++
 drivers/clk/samsung/clk-pll.c                   |  419 ++++
 drivers/clk/samsung/clk-pll.h                   |   41 +
 drivers/clk/samsung/clk.c                       |  320 +++
 drivers/clk/samsung/clk.h                       |  289 +++
 drivers/clk/tegra/Makefile                      |    1 +
 drivers/clk/tegra/clk-periph-gate.c             |   11 +-
 drivers/clk/tegra/clk-periph.c                  |   14 +-
 drivers/clk/tegra/clk-pll.c                     | 1194 ++++++++--
 drivers/clk/tegra/clk-tegra114.c                | 2085 ++++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c                 |  184 +-
 drivers/clk/tegra/clk-tegra30.c                 |  276 +--
 drivers/clk/tegra/clk.c                         |   14 +-
 drivers/clk/tegra/clk.h                         |   98 +-
 drivers/clocksource/Kconfig                     |    8 +
 drivers/clocksource/Makefile                    |    2 +
 drivers/clocksource/cadence_ttc_timer.c         |  436 ++++
 drivers/clocksource/em_sti.c                    |   13 +-
 .../mct.c => drivers/clocksource/exynos_mct.c   |  217 +-
 drivers/clocksource/sh_cmt.c                    |  189 +-
 drivers/clocksource/sh_mtu2.c                   |    2 +-
 drivers/clocksource/sh_tmu.c                    |    2 +-
 drivers/gpio/Kconfig                            |    6 -
 drivers/gpio/Makefile                           |    1 -
 drivers/gpio/gpio-samsung.c                     |    9 +-
 drivers/gpio/gpio-vt8500.c                      |  355 ---
 drivers/irqchip/Kconfig                         |    8 +
 drivers/irqchip/Makefile                        |    4 +
 drivers/irqchip/exynos-combiner.c               |   80 +-
 drivers/irqchip/irq-renesas-intc-irqpin.c       |  547 +++++
 drivers/irqchip/irq-renesas-irqc.c              |  307 +++
 .../irq.c => drivers/irqchip/irq-s3c24xx.c      |  691 +++++-
 .../irq.c => drivers/irqchip/irq-vt8500.c       |    6 +
 drivers/of/base.c                               |  111 +-
 drivers/pinctrl/Kconfig                         |    1 +
 drivers/pinctrl/Makefile                        |    1 +
 drivers/pinctrl/pinctrl-bcm2835.c               |   19 +-
 drivers/pinctrl/pinctrl-exynos.c                |  108 +
 drivers/pinctrl/pinctrl-samsung.c               |    2 +
 drivers/pinctrl/pinctrl-samsung.h               |    1 +
 drivers/pinctrl/sh-pfc/pfc-sh73a0.c             |    6 +-
 drivers/pinctrl/vt8500/Kconfig                  |   52 +
 drivers/pinctrl/vt8500/Makefile                 |    8 +
 drivers/pinctrl/vt8500/pinctrl-vt8500.c         |  501 +++++
 drivers/pinctrl/vt8500/pinctrl-wm8505.c         |  532 +++++
 drivers/pinctrl/vt8500/pinctrl-wm8650.c         |  370 ++++
 drivers/pinctrl/vt8500/pinctrl-wm8750.c         |  409 ++++
 drivers/pinctrl/vt8500/pinctrl-wm8850.c         |  388 ++++
 drivers/pinctrl/vt8500/pinctrl-wmt.c            |  632 ++++++
 drivers/pinctrl/vt8500/pinctrl-wmt.h            |   79 +
 drivers/reset/Kconfig                           |   13 +
 drivers/reset/Makefile                          |    1 +
 drivers/reset/core.c                            |  297 +++
 drivers/video/atmel_lcdfb.c                     |  120 +-
 include/linux/clk/tegra.h                       |    1 +
 include/linux/of.h                              |    9 +
 .../platform_data/irq-renesas-intc-irqpin.h     |   29 +
 include/linux/platform_data/irq-renesas-irqc.h  |   27 +
 include/linux/reset-controller.h                |   51 +
 include/linux/reset.h                           |   17 +
 include/video/atmel_lcdc.h                      |    4 +-
 253 files changed, 16930 insertions(+), 7327 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5440-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/gpmc-nor.txt
 create mode 100644 Documentation/devicetree/bindings/net/gpmc-eth.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/reset/reset.txt
 create mode 100644 Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
 create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
 create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
 create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts
 create mode 100644 arch/arm/boot/dts/exynos4412-origen.dts
 create mode 100644 arch/arm/boot/dts/exynos5250-arndale.dts
 delete mode 100644 arch/arm/mach-exynos/clock-exynos4.c
 delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h
 delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c
 delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c
 delete mode 100644 arch/arm/mach-exynos/clock-exynos5.c
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mct.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-s3c24xx/irq-s3c2412.c
 delete mode 100644 arch/arm/mach-s3c24xx/irq-s3c2440.c
 delete mode 100644 arch/arm/mach-s3c24xx/irq-s3c244x.c
 delete mode 100644 arch/arm/mach-zynq/timer.c
 delete mode 100644 arch/arm/plat-samsung/include/plat/s5p-time.h
 create mode 100644 arch/arm/plat-samsung/include/plat/samsung-time.h
 rename arch/arm/plat-samsung/{s5p-time.c => samsung-time.c} (68%)
 delete mode 100644 arch/arm/plat-samsung/time.c
 create mode 100644 drivers/clk/samsung/Makefile
 create mode 100644 drivers/clk/samsung/clk-exynos4.c
 create mode 100644 drivers/clk/samsung/clk-exynos5250.c
 create mode 100644 drivers/clk/samsung/clk-exynos5440.c
 create mode 100644 drivers/clk/samsung/clk-pll.c
 create mode 100644 drivers/clk/samsung/clk-pll.h
 create mode 100644 drivers/clk/samsung/clk.c
 create mode 100644 drivers/clk/samsung/clk.h
 create mode 100644 drivers/clk/tegra/clk-tegra114.c
 create mode 100644 drivers/clocksource/cadence_ttc_timer.c
 rename arch/arm/mach-exynos/mct.c => drivers/clocksource/exynos_mct.c (64%)
 delete mode 100644 drivers/gpio/gpio-vt8500.c
 create mode 100644 drivers/irqchip/irq-renesas-intc-irqpin.c
 create mode 100644 drivers/irqchip/irq-renesas-irqc.c
 rename arch/arm/mach-s3c24xx/irq.c => drivers/irqchip/irq-s3c24xx.c (53%)
 rename arch/arm/mach-vt8500/irq.c => drivers/irqchip/irq-vt8500.c (97%)
 create mode 100644 drivers/pinctrl/vt8500/Kconfig
 create mode 100644 drivers/pinctrl/vt8500/Makefile
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-vt8500.c
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-wm8505.c
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-wm8650.c
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-wm8750.c
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-wm8850.c
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-wmt.c
 create mode 100644 drivers/pinctrl/vt8500/pinctrl-wmt.h
 create mode 100644 drivers/reset/Kconfig
 create mode 100644 drivers/reset/Makefile
 create mode 100644 drivers/reset/core.c
 create mode 100644 include/linux/platform_data/irq-renesas-intc-irqpin.h
 create mode 100644 include/linux/platform_data/irq-renesas-irqc.h
 create mode 100644 include/linux/reset-controller.h
 create mode 100644 include/linux/reset.h


From tglx at linutronix.de  Sat May  4 04:04:32 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Sat, 4 May 2013 10:04:32 +0200 (CEST)
Subject: [RFC patch 7/8] genirq: generic chip: Add linear irq domain
 support
In-Reply-To: <518472C4.5080209@gmail.com>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.810207749@linutronix.de> <518472C4.5080209@gmail.com>
Message-ID: <alpine.LFD.2.02.1305040959060.8869@ionos>

On Sat, 4 May 2013, Sebastian Hesselbarth wrote:

> On 05/03/2013 11:50 PM, Thomas Gleixner wrote:
> > Provide infrastructure for irq chip implementations which work on
> > linear irq domains.
> 
> Thomas,
> 
> I am happy that I put you into rant mode. It took me little more
> than an hour to read through your patches, prepare orion irqchip
> driver on top of them and finally got it working.

Cool.
 
> Anyway, I found some more issues.

That was expected. :)

> > +	for (i = 0; i < numchips; i++, gc++) {
> 
> The memory you allocated for gc, num_ct * ct, and dgc doesn't allow
> to increment through gc. gc is struct irq_chip_generic * but next
> gc is at sizeof(*gc) + num_ct * sizeof(struct irq_chip_type).
> This also affects indexing dgc->gc later.

Indeed.
 
> I chose to fix it by having an index helper but that first maps
> dgc-gc to unsigned char * and then adds the correct offset. Not

void * is the preferred over uchar *

> nice but it works. Maybe having real array of ptr to gc is more
> intuitive here even if we will have to have split kzallocs.

No, you still can have a single kzalloc. It's just a matter of setting
the pointers correctly.

> > +		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
> > +				      NULL, handler);
> 
> irq_init_generic_chip does not take care of initalizing ct
> mask_cache ptr. This should be done here.

Right.
 
> > +		gc->domain = d;
> > +		raw_spin_lock_irqsave(&gc_lock, flags);
> > +		list_add_tail(&gc->list, &gc_list);
> > +		raw_spin_unlock_irqrestore(&gc_lock, flags);
> > +	}
> > +	d->gc = dgc;
> 
> Moving this assignment above the for loop allows to get
> gc by index as indexing helper relies on domain, not domain
> generic chip.
> 
> You want me to prepare patches for the above? Maybe you can

That'd be nice.

> split your RFC into 1-6 and 7-8. Then you can have 1-6 applied
> independently of irq_domain_generic_chip stuff.

> Thanks for the RFC again!

Welcome. Have fun!

	 tglx


From tom.leiming at gmail.com  Sat May  4 04:21:27 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Sat, 4 May 2013 16:21:27 +0800
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130503100242.GB29962@arm.com>
References: <20130418112201.GQ14496@n2100.arm.linux.org.uk>
 <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
Message-ID: <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>

On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
>>
>> I assume that you inhibited the call to flush_dcache_page() in
>> __get_user_pages() for anon pages.  Otherwise, you will be flooded
>> with warnings.
>
> I haven't done any stress testing so I don't think I hit this code path,
> so no warning. But yes, it should have triggered. Anyway, in this case
> flush_dcache_page() should have just ignored (clearing PG_arch_1 is
> harmless anyway if we also ignore this bit in __sync_icache_dcache for
> non-aliasing caches).

Yes, maybe we can do a little optimization for O_DIRECT since no
dcache alias and I/D coherency problem in this case on ARMv7, how
about below change?

diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 1c8f7f5..962a657 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
 	    mapping && !mapping_mapped(mapping))
 		clear_bit(PG_dcache_clean, &page->flags);
 	else {
+		if (!mapping && cache_is_vipt_nonaliasing())
+			return;
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);

Thanks,
-- 
Ming Lei


From shawn.guo at linaro.org  Sat May  4 08:35:56 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 May 2013 20:35:56 +0800
Subject: [PATCH, RFC 04/22] staging/drm: imx: add missing dependencies
In-Reply-To: <201305031721.37954.arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-5-git-send-email-arnd@arndb.de>
 <20130503021650.GL3442@S2101-09.ap.freescale.net>
 <201305031721.37954.arnd@arndb.de>
Message-ID: <20130504123555.GA1749@S2101-09.ap.freescale.net>

On Fri, May 03, 2013 at 05:21:37PM +0200, Arnd Bergmann wrote:
> On Friday 03 May 2013, Shawn Guo wrote:
> > On Thu, May 02, 2013 at 05:16:08PM +0200, Arnd Bergmann wrote:
> > > The imx DRM driver needs a couple of extra Kconfig dependencies
> > > to avoid random build failures:
> > > 
> > > drivers/staging/imx-drm/ipuv3-crtc.c:448:
> > >  undefined reference to `ipu_idmac_put'
> > >  drivers/staging/imx-drm/ipuv3-crtc.c:450: undefined reference to
> > >  `ipu_dmfc_put' drivers/staging/imx-drm/ipuv3-crtc.c:452:
> > >  undefined reference to `ipu_dp_put'
> > >  drivers/staging/imx-drm/ipuv3-crtc.c:454: undefined reference to
> > >  `ipu_di_put'
> > > drivers/built-in.o: In function `ipu_probe':
> > >  :(.text+0x4b4174): undefined reference to `device_reset'
> > > drivers/built-in.o: In function `imx_tve_probe':
> > >  drivers/staging/imx-drm/imx-tve.c:648: undefined reference to
> > >  `devm_regmap_init_mmio_clk'
> > > drivers/built-in.o: In function
> > >  `imx_pd_connector_get_modes':
> > 
> > >  drivers/staging/imx-drm/parallel-display.c:78: undefined
> > >  reference to `of_get_drm_display_mode'
> > 
> > There is a patch [1] from Marek fixing this one.
> > 
> > Shawn
> > 
> > [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/233449
> > 
> 
> That patch only addresses one of the four missing dependencies.
> I originally had four separate patches, but did not want to
> bother everyone with those so I combined them into one.

Yea, I agree we can address all of them in one patch.  But it seems
people agreed that there is a more correct way [1] to fix
of_get_drm_display_mode one, and that's how v2 of Marek's patch comes.

Shawn

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/232861/focus=232898



From shawn.guo at linaro.org  Sat May  4 08:40:52 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 May 2013 20:40:52 +0800
Subject: [PATCH v2] ARM: dts: Add SPI support for i.MX27 Phytec PCM038
 module
In-Reply-To: <1367568501-29467-1-git-send-email-shc_work@mail.ru>
References: <1367568501-29467-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130504124028.GB1749@S2101-09.ap.freescale.net>

On Fri, May 03, 2013 at 12:08:21PM +0400, Alexander Shiyan wrote:
> Added SPI node and PMIC MC13783 (spi0.0) to imx27-phytec-phycore DT file.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Applied, thanks.



From mirq-linux at rere.qmqm.pl  Sat May  4 09:19:35 2013
From: mirq-linux at rere.qmqm.pl (=?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?=)
Date: Sat,  4 May 2013 15:19:35 +0200 (CEST)
Subject: [PATCH 2/2] staging/iio/mxs-lradc: fix preenable for multiple buffers
In-Reply-To: <6bb527db65fb20f60bb95814bff3abc513733a7c.1367671597.git.mirq-linux@rere.qmqm.pl>
References: <6bb527db65fb20f60bb95814bff3abc513733a7c.1367671597.git.mirq-linux@rere.qmqm.pl>
Message-ID: <ba60ca91ef1d3061b454e518f6026a1157fae5d7.1367671597.git.mirq-linux@rere.qmqm.pl>

This fixes 'preenable failed: -EINVAL' error when using this driver.

Signed-off-by: Micha? Miros?aw <mirq-linux at rere.qmqm.pl>
---
 drivers/staging/iio/adc/mxs-lradc.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
index 03299ea..d92c97a 100644
--- a/drivers/staging/iio/adc/mxs-lradc.c
+++ b/drivers/staging/iio/adc/mxs-lradc.c
@@ -690,7 +690,6 @@ static void mxs_lradc_trigger_remove(struct iio_dev *iio)
 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
 {
 	struct mxs_lradc *lradc = iio_priv(iio);
-	struct iio_buffer *buffer = iio->buffer;
 	int ret = 0, chan, ofs = 0;
 	unsigned long enable = 0;
 	uint32_t ctrl4_set = 0;
@@ -698,7 +697,7 @@ static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
 	uint32_t ctrl1_irq = 0;
 	const uint32_t chan_value = LRADC_CH_ACCUMULATE |
 		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
-	const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
+	const int len = bitmap_weight(iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS);
 
 	if (!len)
 		return -EINVAL;
@@ -725,7 +724,7 @@ static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
 		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
 	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
 
-	for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
+	for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
 		ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
 		ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
 		ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
-- 
1.7.10.4



From mirq-linux at rere.qmqm.pl  Sat May  4 09:19:35 2013
From: mirq-linux at rere.qmqm.pl (=?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?=)
Date: Sat,  4 May 2013 15:19:35 +0200 (CEST)
Subject: [PATCH 1/2] staging/iio/mxs-lradc: cleanup masklength
Message-ID: <6bb527db65fb20f60bb95814bff3abc513733a7c.1367671597.git.mirq-linux@rere.qmqm.pl>

We know the exact iio->masklength = LRADC_MAX_TOTAL_CHANS.
Let's use it consistently.

Signed-off-by: Micha? Miros?aw <mirq-linux at rere.qmqm.pl>
---
 drivers/staging/iio/adc/mxs-lradc.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
index 2856b8f..03299ea 100644
--- a/drivers/staging/iio/adc/mxs-lradc.c
+++ b/drivers/staging/iio/adc/mxs-lradc.c
@@ -620,7 +620,7 @@ static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
 		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
 	unsigned int i, j = 0;
 
-	for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
+	for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
 		lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
 		writel(chan_value, lradc->base + LRADC_CH(j));
 		lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
@@ -775,8 +775,7 @@ static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
 					const unsigned long *mask)
 {
 	struct mxs_lradc *lradc = iio_priv(iio);
-	const int len = iio->masklength;
-	const int map_chans = bitmap_weight(mask, len);
+	const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
 	int rsvd_chans = 0;
 	unsigned long rsvd_mask = 0;
 
@@ -793,7 +792,7 @@ static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
 		rsvd_chans++;
 
 	/* Test for attempts to map channels with special mode of operation. */
-	if (bitmap_intersects(mask, &rsvd_mask, len))
+	if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
 		return false;
 
 	/* Test for attempts to map more channels then available slots. */
@@ -969,6 +968,7 @@ static int mxs_lradc_probe(struct platform_device *pdev)
 	iio->modes = INDIO_DIRECT_MODE;
 	iio->channels = mxs_lradc_chan_spec;
 	iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
+	iio->masklength = LRADC_MAX_TOTAL_CHANS;
 
 	ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
 				&mxs_lradc_trigger_handler,
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sat May  4 09:30:04 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 4 May 2013 15:30:04 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <517ED12B.8080502@wwwdotorg.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
Message-ID: <20130504133004.GC24282@game.jcrosoft.org>

On 13:59 Mon 29 Apr     , Stephen Warren wrote:
> On 04/29/13 12:41, Bryan Wu wrote:
> >Forward to ARM and Tegra mail list.
> >
> >---------- Forwarded message ----------
> >From: Bryan Wu <cooloney at gmail.com>
> >Date: Mon, Apr 29, 2013 at 11:15 AM
> >Subject: Tegra 30 System hangs because of commit "pinctrl: move
> >subsystem mutex to pinctrl_dev struct"
> >To: patrice.chotard at st.com, Linus Walleij <linus.walleij at linaro.org>
> >Cc: Stephen Warren <swarren at wwwdotorg.org>,
> >"linux-next at vger.kernel.org" <linux-next at vger.kernel.org>
> >
> >
> >Hi Patrice and Linus,
> >
> >I'm running linux-next on my Tegra 30 system everyday. But since
> >next-20130426 release, the linux-next kernel will hang on my Tegra 30
> >boards like Cardhu and Beaver.
> >
> >After some bisect and comparing to next-20130424, I found the commit
> >"pinctrl: move subsystem mutex to pinctrl_dev struct" introduced this
> >issue. If I simply revert this patch in next-20130429, system boots up
> >as before.
> >
> >Could you please help to check this?
> 
> I would suggest simply dropping or reverting this patch; I had
> pointed out a long time ago that it was unlikely to be correct.
> 
> My guess/suspicion is a recursive lock attempt during processing
> hogs during pinctrl device registration, or perhaps during dt->map
> conversion. Bryan, are you able to confirm this?

same issue on at91sam9g45ek

revert it

Best Regards,
J.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From shawn.guo at linaro.org  Sat May  4 11:20:36 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 May 2013 23:20:36 +0800
Subject: [PATCH] ARM: i.MX6: clk: add i.MX6 DualLite differences
In-Reply-To: <1367572125-28420-1-git-send-email-dirk.behme@de.bosch.com>
References: <1367572125-28420-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <20130504152034.GC1749@S2101-09.ap.freescale.net>

On Fri, May 03, 2013 at 11:08:45AM +0200, Dirk Behme wrote:
> The CCM_CBCMR register (address 0x02C4018) has different meaning
> between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.
> 
> Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
> i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and
> moves the gpu2_core configuration at that place.
> 
> Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences
> by using cpu_is_mx6dl().
> 
> Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>

Applied, thanks.



From nerv at dawncrow.de  Sat May  4 11:54:37 2013
From: nerv at dawncrow.de (=?UTF-8?B?QW5kcsOpIEhlbnRzY2hlbA==?=)
Date: Sat, 04 May 2013 17:54:37 +0200
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <5183D6C3.8090402@arm.com>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
 <5182C480.3080001@dawncrow.de> <5183819E.50308@arm.com>
 <20130503095547.GD18614@n2100.arm.linux.org.uk> <5183D6C3.8090402@arm.com>
Message-ID: <51852F3D.5000802@dawncrow.de>

Am 03.05.2013 17:24, schrieb Jonathan Austin:
> Hi Russell,
> 
> Thanks for the comments - you're right about the 'switch_tls'
> being more appropriate - needed to take a step back to see that.
> 
> I've got a few questions, added inline.
> 
> Andr?, Assuming I've understood things okay, there's a patch that
> uses Russell's asm stuff (with minor modifications, see the questions)
> and includes the C-world changes too. Perhaps you could see that it
> solves your problem?

I'll test it tomorrow with my test tool and Wine.
FWIW i hacked together a test tool and it's available at https://github.com/AndreRH/tpidrurw-test


From khc at pm.waw.pl  Sat May  4 13:44:42 2013
From: khc at pm.waw.pl (Krzysztof Halasa)
Date: Sat, 04 May 2013 19:44:42 +0200
Subject: [PATCH] ARM: ixp4xx: change type of ioremap function
In-Reply-To: <1367514566-30831-1-git-send-email-lauraa@codeaurora.org> (Laura
 Abbott's message of "Thu, 2 May 2013 10:09:26 -0700")
References: <1367514566-30831-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <m3sj22prlh.fsf@intrepid.localdomain>

Laura Abbott <lauraa at codeaurora.org> writes:

> Commit cd024d4245b2bfbd824b911f11a9756d1d6c167d
> (ARM: 7704/1: mm: Use phys_addr_t properly for ioremap functions)
> changed the type of the ioremap functions to actually use phys_addr_t
> instead of unsigned long. Change the type of the arch_ioremap function
> to use phys_addr_t as well.
>
> Signed-off-by: Laura Abbott <lauraa at codeaurora.org>

Acked-by: Krzysztof Halasa <khc at pm.waw.pl>

>
> diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
> index 1dbeb7c..659768b 100644
> --- a/arch/arm/mach-ixp4xx/common.c
> +++ b/arch/arm/mach-ixp4xx/common.c
> @@ -558,7 +558,7 @@ void ixp4xx_restart(char mode, const char *cmd)
>   * fallback to the default.
>   */
>  
> -static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
> +static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
>  					   unsigned int mtype, void *caller)
>  {
>  	if (!is_pci_memory(addr))

-- 
Krzysztof Halasa


From jason at lakedaemon.net  Sat May  4 13:58:39 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 4 May 2013 13:58:39 -0400
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182C322.3030304@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130502185322.GA29333@obsidianresearch.com>
 <5182B902.7040908@gmail.com>
 <20130502193510.GA29522@obsidianresearch.com>
 <5182C322.3030304@gmail.com>
Message-ID: <20130504175839.GM31290@titan.lakedaemon.net>

On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
> On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
> >I have kirkwood HW but I haven't had time to make newer kernels run on
> >it, otherwise I'd test it too :(
> 
> I also have kirkwood HW but that will cut me from email as I use it as
> relay server ;) Maybe I can turn it into a test bed for a while.
> 
> There is also Orion5x and Discovery Innovation (mv78xx0) to be tested.
> 
> @Jason Cooper: I will merge both irqchip and dove patches into one
> patch set. I wasn't earlier because I didn't want the above SoCs to
> slow down patch integration. And I will split dtsi changes into
> separate patches as requested.

Understood.  I'd prefer to keep patches developed together in the same
series, that way, discussions about who is taking what and which patch
depends on what are all in the same thread of the archives.

It's difficult because some series (eg pcie) touch many different areas
and _need_ to be kept together because of the chain of dependencies.
Most other series though, aren't in that situation.

thx,

Jason.


From jason at lakedaemon.net  Sat May  4 14:12:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 4 May 2013 14:12:27 -0400
Subject: [PATCH] irqchip: add support for Marvell Orion SoCs
In-Reply-To: <5182EAA0.9070208@gmail.com>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <alpine.LFD.2.02.1305022324371.2891@ionos>
 <5182E11E.5010103@gmail.com> <201305030009.57041.arnd@arndb.de>
 <5182EAA0.9070208@gmail.com>
Message-ID: <20130504181227.GN31290@titan.lakedaemon.net>

On Fri, May 03, 2013 at 12:37:20AM +0200, Sebastian Hesselbarth wrote:
> (@Jason C: Are you sure that I should merge dove and orion
> irqchip patches? I doubt that anything touching generic irq
> will not go through irq tree.)

Putting them in the same patch series does not imply they have to go
through the same tree.  But it *does* allow us to see relationships,
conflicts, etc.

Based on how the finally dependencies work out, we may ask the irq
maintainers for an Ack to take it through arm-soc.  This would happen if
we can't remove the dependency between the trees.  The resulting
potential merge conflicts weigh into it, and that's where the irqchip
maintainer's Ack get decided.

If the changes to irqchip are just Makefile/Kconfig, then it's easy.
However, if several other files are changed and conflicting, then we let
it go through irqchip and wait one merge window for the board changes
depending on it.

The goal here is to identify and remove branch dependencies within
arm-soc and between arm-soc and other trees.  A secondary goal is to
identify high-risk series (risk of being dropped), and keep them
in separate branches from other changes.

thx,

Jason.


From hvaibhav at ti.com  Sat May  4 14:23:40 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Sat, 4 May 2013 23:53:40 +0530
Subject: [PATCH] ARM: OMAP2: AM33XX: id: Add support for new AM335x PG2.1 Si
Message-ID: <1367691820-11875-1-git-send-email-hvaibhav@ti.com>

Add support for chip id detection of AM335x PG2.1 Silicon.

Currently omap3xxx_check_revision() detects PG1.0 and PG2.0 only,
this patch extends it by adding PG2.1 Si support.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
---
 arch/arm/mach-omap2/id.c  |    8 ++++++--
 arch/arm/mach-omap2/soc.h |    1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0f4c18e..9bc5a18 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -419,11 +419,15 @@ void __init omap3xxx_check_revision(void)
 			cpu_rev = "1.0";
 			break;
 		case 1:
-		/* FALLTHROUGH */
-		default:
 			omap_revision = AM335X_REV_ES2_0;
 			cpu_rev = "2.0";
 			break;
+		case 2:
+		/* FALLTHROUGH */
+		default:
+			omap_revision = AM335X_REV_ES2_1;
+			cpu_rev = "2.1";
+			break;
 		}
 		break;
 	case 0xb8f2:
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 18fdeeb..ccef2dd 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -396,6 +396,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_CLASS		0x33500033
 #define AM335X_REV_ES1_0	AM335X_CLASS
 #define AM335X_REV_ES2_0	(AM335X_CLASS | (0x1 << 8))
+#define AM335X_REV_ES2_1	(AM335X_CLASS | (0x2 << 8))

 #define OMAP443X_CLASS		0x44300044
 #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
--
1.7.0.4



From jason at lakedaemon.net  Sat May  4 14:29:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 4 May 2013 14:29:35 -0400
Subject: [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
In-Reply-To: <20130503050632.GC24965@lunn.ch>
References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367538519-23940-3-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130503050632.GC24965@lunn.ch>
Message-ID: <20130504182935.GO31290@titan.lakedaemon.net>

On Fri, May 03, 2013 at 07:06:32AM +0200, Andrew Lunn wrote:
> Jason: what is the status of the ethernet driver conversion to DT?
> Will it get merged this week, or is it material for the next merge
> window?

You'd have to ask Florian/David Miller.  I'm not sure wether David was
able to pull that in for v3.10 or not.  He was pretty responsive to all
of the other changes Florian posted.

thx,

Jason.


From jason at lakedaemon.net  Sat May  4 14:35:33 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 4 May 2013 14:35:33 -0400
Subject: [PATCH 1/3] ARM: dove: add DT parsing for legacy mv643xx_eth
In-Reply-To: <1367519140-19716-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367519140-19716-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130504183533.GQ31290@titan.lakedaemon.net>

On Thu, May 02, 2013 at 08:25:38PM +0200, Sebastian Hesselbarth wrote:
> To allow to move to orion irqchip driver, existing legacy devices
> have to map their irqs. This patch adds a node for mv643xx_eth and
> some init code to map the corresponding irqs. While the device tree
> node can stay, the init code will vanish as soon as there is true
> device tree support for mv643xx_eth.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/boot/dts/dove.dtsi   |    7 +++++++
>  arch/arm/mach-dove/board-dt.c |   31 ++++++++++++++++++++++++++++++-
>  2 files changed, 37 insertions(+), 1 deletions(-)

Please break this into two patches, dtsi in one, board-dt.c in the
other.

thx,

Jason.


From jason at lakedaemon.net  Sat May  4 14:36:24 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 4 May 2013 14:36:24 -0400
Subject: [PATCH 2/3] ARM: dove: add DT parsing for legacy timer
In-Reply-To: <1367519140-19716-3-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367519140-19716-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367519140-19716-3-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130504183624.GR31290@titan.lakedaemon.net>

On Thu, May 02, 2013 at 08:25:39PM +0200, Sebastian Hesselbarth wrote:
> To allow to move to orion irqchip driver, existing legacy devices
> have to map their irqs. This patch adds a node for orion timer and
> some init code to map the corresponding irqs. While the device tree
> node can stay, the init code will vanish as soon as there is true
> device tree support for orion timer.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/boot/dts/dove.dtsi   |    7 ++++++
>  arch/arm/mach-dove/board-dt.c |   42 +++++++++++++++++++++++++++++++++++-----
>  2 files changed, 43 insertions(+), 6 deletions(-)

Same for the rest of these, please.

thx,

Jason.


From hvaibhav at ti.com  Sat May  4 14:48:04 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Sun, 5 May 2013 00:18:04 +0530
Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to GFX
 hwmod
Message-ID: <1367693284-7870-1-git-send-email-hvaibhav@ti.com>

GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
so update the GFX hwmod data with .rstst_off and .st_shift
information.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index d1cf3ab..38c7b04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 };
 
 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-	{ .name = "gfx", .rst_shift = 0 },
+	{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
 };
 
 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
 			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
+			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
-- 
1.7.0.4



From jaswinder.singh at linaro.org  Sat May  4 15:08:51 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Sun, 5 May 2013 00:38:51 +0530
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <51847070.8040400@ti.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
Message-ID: <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>

Hi Suman,

On 4 May 2013 07:50, Suman Anna <s-anna at ti.com> wrote:
> Hi Jassi,
>
> On 04/27/2013 01:14 PM, jassisinghbrar at gmail.com wrote:
>> From: Jassi Brar <jaswinder.singh at linaro.org>
>>
>> Introduce common framework for client/protocol drivers and
>> controller drivers of Inter-Processor-Communication (IPC).
>>
>> Client driver developers should have a look at
>>  include/linux/mailbox_client.h to understand the part of
>> the API exposed to client drivers.
>> Similarly controller driver developers should have a look
>> at include/linux/mailbox_controller.h
>
> This implementation looks decent based on your design points. These
> are the open/contention points that needs to be sorted out.
>
> I think understanding the OMAP mailbox architecture also helps you,
> since this series currently addressed PL320, but we will run into
> some issues when adopting for OMAP as is. OMAP has a single mailbox IP,
> each with multiple h/w FIFOs (fifo of length 4, and message size of a
> u32). Each IP can cause one or more irq (usually 1) into the linux host.
> It has status registers for number of messages in a FIFO (Rx), FIFO full
> (Tx non-readiness/busy state), and interrupts for both Rx and Tx. There
> are registers indicating the source of the interrupt, and these are per
> FIFO. The Tx interrupt source is really for indicating Tx readiness or
> that a fifo has open room for sending messages. This will keep on firing
> as long as the FIFO is not-full, so we usually configure this only when
> the FIFO is full and disable it the moment it is fired. It is re-enabled
> when the h/w FIFO is full again, and we use s/w buffering in between.
> The Rx interrupt is fired as long as there is a message in any FIFO
> which has been configured to interrupt the host, so we have to empty all
> the messages for that interrupt source.
>
Yeah, thanks for explanation. I've worked on OMAP for almost 2 yrs
now, though not mailbox. I did have a look at the OMAP4430 trm.
 I understand OMAP's MBox doesn't really have TX-Done/RTR interrupt,
it only has "Tx Buffer Not Full" interrupt which serves the purpose
only for the window when there are at least 4 TX messages pending. Now
the driver could switch between Polling and IRQ at runtime depending
upon the buffer filled extent, OR simply work in polling mode all the
time. IMHO the controller driver should opt for the latter.  Though it
might be interesting to profile out of total transfers during a
period, how many are actually queued till depth of 4.


> Anyway, here is a summary of the open points that we have:
> 1. Atomic Callbacks:
> The current code provides some sort of buffering on Tx, but imposes the
> restriction that the clients do the buffering on Rx. This is main
> concern for OMAP.

I am afraid a common API can't do without buffering TX and it can't do
by buffering RX.

 The client(s) can always generate TX requests at a rate greater than
the API could transmit on the physical link. So as much as we dislike
it, we have to buffer TX requests, otherwise N clients would.
 OTOH Buffering received packets in the API doesn't help anybody, it
only incurs unavoidable latencies on clients. Only clients, that need
to take non-atomic actions upon RX, would need to buffer RX. Other
clients should not suffer.

IMHO if clients on OMAP need to buffer RX, let us keep it OMAP
specific. If number of such platforms rise in future we could move
that as an _optional_ helper API on top, that does RX buffering on
behalf of clients ?


> 2. Support for Shared Clients AND Time-shared Clients:
> As I said before, we need the framework to be flexible enough to support
> shared clients. The shared clients may not be applicable for all h/w
> controllers, where a client has to send a series of operations that
> needs to be sent to the remote before anyone else can use it. This is a
> functional integration aspect, and is dictated by the nature of the
> remote. For the time-shared clients, the remote must have some implicit
> message protocol where in the remote is able to identify the macro
> usecase through a specific message. The framework should allow the case
> of shared clients, with the clients doing their own message demuxing.
>
 If the API provides shared ownership of a mailbox, it won't work for
clients that need exclusive ownership (like 'server' side
implementation of a protocol).
 OTOH if the API provides exclusive ownership, it is still possible to
emulate shared ownership by simply publishing the mailbox handle (void
*chan) globally. It works for all.

>
> 3. Buffering/Size: I think we need to take a re-look at the whole tx
> buffering mechanism. You are using an array that stores just the
> pointers, which means that there are underlying assumptions that the
> clients are keeping their buffer ptrs intact until the duration of the
> transfer is done. This means that one cannot use local payload
> variables for messages in the calling functions. I feel this is
> unnecessary burden on the clients.
>
Most of the clients won't queue more than 1 request at a time. And
then, isn't it only natural that clients don't mess with requests
after submitting them ?  I see mailbox clients working quite like I2C
clients.

> Secondly, we may not need the logic around client knows_txdone and
> tx_buffering together. I understand the need for buffering when you have
> TX_POLL or TX_IRQ, but as far as TX_ACK is concerned, it is a client
> protocol-level knowledge, and so the tx buffering logic can remain with
> the client itself. This should simplify the code a little bit and get
> rid of the ipc_client_txdone API.
>
Yeah I had it that way originally. But then I realized we could be
running an 'ACK Packet' protocol over a controller that supports only
POLL. In that case the controller's poll doesn't override client's
knows_txdone because we want the client to cut-short the next poll
delay as soon as it gets an ACK packet.

> Looking at the current use-cases, I think OMAP might be the only one
> which needs the buffering. The API that Loic added suggests that he
> either sends a message and expects a response, or just sends a message
> if the transport is free (I am not sure if he is using the API that uses
> buffering currently). PL320 is the same as the first scenario that Loic has.
>
Yeah I too expect TX buffering to be very rare.

> The other point is regarding the size field, I am not convinced that we
> can take this out, and leave it between the client and the controller
> implementation. I think the mailbox core should at least perform a check
> based on the max size published by a controller driver. Like in the
> PL320 patch conversion, the for loop for writing the data - how does it
> know that the provided pointer is atleast 7 ints, and not smaller than
> that?
>
First of all, PL320 is a highly configurable and programmable IP.
pl320.c is very specific to Highbank's usage, it is not usable as such
on other platforms. There are many things hardcoded and tacitly
assumed in the driver. I just changed the API, didn't add anything
new.

Secondly, I believe we acknowledged the fact that a client can't do
without controller specific knowledge. So in proper implementation the
controller's header would look like

struct foobar_con_mssg {
   int datalen; /* size of received packet in bytes */
   u8 *buf;  /* buffer that holds the packet data */
    .....
};

So instead of telling the API the 'datalen' and the remaining
structure of each message, we simply pass "struct foobar_con_mssg *"
as a void* to the API.


>> +
>> +/*
>> + * Called by a client to "put data on the h/w channel" so that if
>> + * everything else is fine we don't need to do anything more locally
>> + * for the remote to receive the data intact.
>> + * In reality, the remote may receive it intact, corrupted or not at all.
>> + * This could be called from atomic context as it simply
>> + * queues the data and returns a token (request_token_t)
>> + * against the request.
>> + * The client is later notified of successful transmission of
>> + * data over the channel via the 'txcb'. The client could in
>> + * turn queue more messages from txcb.
>> + */
>> +request_token_t ipc_send_message(void *channel, void *data)
>> +{
>> +     struct ipc_chan *chan = (struct ipc_chan *)channel;
>> +     request_token_t t;
>> +
>> +     if (!chan)
>> +             return 0;
>> +
>> +     t = _add_to_rbuf(chan, data);
>> +     if (!t)
>> +             printk("Try increasing MBOX_TX_QUEUE_LEN\n");
>> +
>> +     _msg_submit(chan);
>> +
>> +     if (chan->txdone_method == TXDONE_BY_POLL)
>> +             poll_txdone((unsigned long)chan->timer);
>> +
>> +     if (chan->tx_block && chan->active_token) {
>
> Assigning the tx_block at channel request time might not be flexible
> enough. We should not impose that the client will request and release
> channels with different modes if both scenarios are needed.
>
If there is one blocking request, no more could arrive (blocking or
non-blocking). The increased code complexity doesn't justify the
rarely used feature. I don't see many use-cases when the client can't
release-request the channel. It's made like opening a file - blocking
vs non-blocking is the mode you open the resource.

>> +             int ret;
>> +             init_completion(&chan->tx_complete);
>> +             ret = wait_for_completion_timeout(&chan->tx_complete,
>> +                     chan->tx_tout);
>> +             if (ret == 0) {
>> +                     t = 0;
>> +                     tx_tick(chan, XFER_ERR);
>> +             }
>> +     }
>> +
>> +     return t;
>> +}
>> +EXPORT_SYMBOL(ipc_send_message);
>
> Do we need to add an API similar to mailbox_msg_send_receive_no_irq, or
> are you leaving it to be client's responsibility?
>
Yes the API provides enough ways for a client to do that.

>> +
>> +/*
>> + * A client driver asks for exclusive use of a channel/mailbox.
>> + * If assigned, the channel has to be 'freed' before it could
>> + * be assigned to some other client.
>> + * After assignment, any packet received on this channel will be
>> + * handed over to the client via the 'rxcb' callback.
>> + * The 'txcb' callback is used to notify client upon sending the
>> + * packet over the channel, which may or may not have been yet
>> + * read by the remote processor.
>> + */
>> +void *ipc_request_channel(struct ipc_client *cl)
>> +{
>> +     struct ipc_chan *chan;
>> +     unsigned long flags;
>> +     int ret = 0;
>> +
>> +     mutex_lock(&chpool_mutex);
>> +
>> +     list_for_each_entry(chan, &ipc_channels, node)
> I had a different design in mind here, maintain the list of controllers
> globally instead of the channels, that way your search can be a bit
> quicker.
>
Yeah, I changed that to it last minute :)
The API has no real use of controller nodes, it works solely on a
global pool of mailboxes. I tried to reflect that in code.


>> +
>> +     if (txdone == TXDONE_BY_POLL) {
>> +             timer = kzalloc(sizeof(struct tx_poll_timer), GFP_KERNEL);
>> +             timer->period = ipc_con->txpoll_period;
>> +             timer->poll.function = &poll_txdone;
>> +             timer->poll.data = (unsigned long)timer;
>> +             init_timer(&timer->poll);
>> +     }
>> +
>> +     channel = kzalloc(sizeof(struct ipc_chan) * num_links, GFP_KERNEL);
>
> minor, but you might be aware of this already, failure check needed
>
No, I overlooked. Thanks.


>> +
>> +static int __init ipc_mbox_init(void)
>> +{
>> +     INIT_LIST_HEAD(&ipc_channels);
>> +     return 0;
>> +}
>> +subsys_initcall(ipc_mbox_init);
>
> The ipc_mbox_init can be replaced by static list init of ipc_channels,
> nothing much to be gained by defining this function. We expect the
> mailbox.c to be built anyways whenever the mailbox framework is selected.
>
Yes, you are right. Thanks.

>> + * @cntlr_data: Optional controller specific parameters during channel request
>> + */
>> +struct ipc_client {
>> +     char *chan_name;
>> +     void (*rxcb)(void *data);
>> +     void (*txcb)(request_token_t t, enum xfer_result r);
>> +     bool tx_block;
>> +     unsigned long tx_tout;
>> +     bool knows_txdone;
>> +     void *cntlr_data;
>
> What is the current use-case for exposing cntrl_data through ipc_client?
> I think this should be avoided and leave the controller configuration to
> the controller driver implementation. This will be a problem for
> multiple link scenarios.
>
There are some highly programmable controllers that, if the driver is
proper, could change behavior runtime. For ex, if the controller
supports, a client might want to broadcast messages to multiple
remotes or listen for messages from more than one remote source or
both. The client could, say, specify bitmasks for such source/sink
remotes via cntlr_data while requesting the mailbox.  PL320 could work
in such mode if rest all fits.


>> +struct ipc_link {
>> +     char link_name[16];
>> +     void *api_priv;
>> +};
>
> this definitely needs a link-private void *ptr. PL320 doesn't have
> multiple links in the controller, but this is a problem for OMAP & DBX500.
>
The API keeps the ipc_link provided by the controller driver, which
could have it embedded in its private representation of the h/w links.
 For ex, my controller has 6 links, and its structure contains 6
element array of 'struct myhw_link' which embeds an ipc_link. And I
use container_of().


>> +struct ipc_link_ops {
>> +     int (*send_data)(struct ipc_link *link, void *data);
>> +     int (*startup)(struct ipc_link *link, void *params);
>> +     void (*shutdown)(struct ipc_link *link);
>> +     bool (*last_tx_done)(struct ipc_link *link);
> minor comment, maybe rename this to something that indicates link
> busyness or readiness
>
The API gives the controller only one TX at a time, so I chose the
name. What do you suggest?


>> +};
>> +
>> +/**
>> + * struct ipc_controller - Controller of a class of communication links
>> + * @controller_name: Literal name of the controller.
>> + * @ops: Operators that work on each communication link
>> + * @links: Null terminated array of links.
>> + * @txdone_irq: Indicates if the controller can report to API when the
>> + *    last transmitted data was read by the remote. Eg, if it has some
>> + *    TX ACK irq.
>> + * @txdone_poll: If the controller can read but not report the TX done.
>> + *    Eg, is some register shows the TX status but no interrupt rises.
>> + *    Ignored if 'txdone_irq' is set.
>> + * @txpoll_period: If 'txdone_poll' is in effect, the API polls for
>> + *    last TX's status after these many millisecs
>> + */
>> +struct ipc_controller {
>> +     char controller_name[16];
> i think this can be avoided and use the underlying dev-name directly
> based on the controller device. Adding a struct device pointer would
> automatically allow you to use the name from the probe.
>
Ah ha... yes. Thanks.

>> +     struct ipc_link_ops *ops;
> I think this should be a property of the individual link for
> flexibility. Right now, it probably doesn't make a difference (as seen
> from the current mailbox code), but the moment we have one link behaving
> differently this will make the ops implementation a bit messy.
>
> I think we also need a controller-specific ops, to put common stuff
> between multiple links within the controller.
>
A controller is assumed to be a bunch of identical links/mailboxes.
However the cntlr_data could still help the client specify mode in
which it wants a mailbox behave.

Thanks and Regards.
-Jassi


From tomasz.figa at gmail.com  Sat May  4 15:28:20 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sat, 04 May 2013 21:28:20 +0200
Subject: DMA mapping API abuse in exynos-drm
Message-ID: <2146981.l1bUpBI0CH@flatron>

Hi,

Recently I've been working a bit on a DRM driver for the GPU of Samsung 
S3C6410 SoCs, which required me to familiarize a bit with exynos-drm, as 
it already contains a KMS driver which is compatible with the SoC I'm 
working with, making it a good place to put my driver in.

Reading through exynos_drm_buf.c I stumbled across following (a bit long) 
piece of code:

        dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &buf->dma_attrs);

        nr_pages = buf->size >> PAGE_SHIFT;

        if (!is_drm_iommu_supported(dev)) {
                dma_addr_t start_addr;
                unsigned int i = 0;

                buf->pages = kzalloc(sizeof(struct page) * nr_pages,
                                        GFP_KERNEL);
                if (!buf->pages) {
                        DRM_ERROR("failed to allocate pages.\n");
                        return -ENOMEM;
                }

                buf->kvaddr = dma_alloc_attrs(dev->dev, buf->size,
                                        &buf->dma_addr, GFP_KERNEL,
                                        &buf->dma_attrs);
                if (!buf->kvaddr) {
                        DRM_ERROR("failed to allocate buffer.\n");
                        kfree(buf->pages);
                        return -ENOMEM;
                }

                start_addr = buf->dma_addr;
                while (i < nr_pages) {
                        buf->pages[i] = phys_to_page(start_addr);
                        start_addr += PAGE_SIZE;
                        i++;
                }
        } else {

                buf->pages = dma_alloc_attrs(dev->dev, buf->size,
                                        &buf->dma_addr, GFP_KERNEL,
                                        &buf->dma_attrs);
                if (!buf->pages) {
                        DRM_ERROR("failed to allocate buffer.\n");
                        return -ENOMEM;
                }
        }

        buf->sgt = drm_prime_pages_to_sg(buf->pages, nr_pages);
        if (!buf->sgt) {
                DRM_ERROR("failed to get sg table.\n");
                ret = -ENOMEM;
                goto err_free_attrs;
        }

Notice that the value returned by dma_alloc_attrs() is assumed by this 
code to be either a kernel virtual address (in !is_drm_iommu_supported() 
case) or struct pages ** (in is_drm_iommu_supported() case), which seemed 
a bit worrying to me, making me do a more in depth research on how 
dma_alloc_attrs works.

This, in turn, led me to following excerpt of Documentation/DMA-
attributes.txt :

DMA_ATTR_NO_KERNEL_MAPPING
--------------------------

DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
virtual mapping for the allocated buffer. On some architectures creating
such mapping is non-trivial task and consumes very limited resources
(like kernel virtual address space or dma consistent address space).
Buffers allocated with this attribute can be only passed to user space
by calling dma_mmap_attrs(). By using this API, you are guaranteeing
that you won't dereference the pointer returned by dma_alloc_attr(). You
can threat it as a cookie that must be passed to dma_mmap_attrs() and
dma_free_attrs(). Make sure that both of these also get this attribute
set on each call.

of which the following sentence is the most relevant:

By using this API, you are guaranteeing that you won't dereference the 
pointer returned by dma_alloc_attr().

This statement is obviously ignored by buffer allocation code of exynos-
drm.

A simple git blame revealed that this brokenness has been introduced by 
commit:

4744ad2 drm/exynos: use DMA_ATTR_NO_KERNEL_MAPPING attribute


and later fixed a bit by following depending patches (because the original 
patch apparently broke any allocations without IOMMU):

c704f1b drm/exynos: consider no iommu support to console framebuffer
694be45 drm/exynos: consider buffer allocation without iommu


Now, the real question is whether my reasoning is incorrect (sorry for the 
noise then) or this is really a bug which needs to be fixed?

Best regards,
Tomasz



From linus.walleij at linaro.org  Sat May  4 16:52:50 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 4 May 2013 22:52:50 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130504133004.GC24282@game.jcrosoft.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
Message-ID: <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>

On Sat, May 4, 2013 at 3:30 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> same issue on at91sam9g45ek

Is it working with mainline (Torvalds) HEAD?

Yours,
Linus Walleij


From benh at kernel.crashing.org  Sat May  4 22:41:49 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sun, 05 May 2013 12:41:49 +1000
Subject: [PATCH v8 1/3] of/pci: Unify pci_process_bridge_OF_ranges from
 Microblaze and PowerPC
In-Reply-To: <1366627295-16964-2-git-send-email-Andrew.Murray@arm.com>
References: <1366627295-16964-1-git-send-email-Andrew.Murray@arm.com>
 <1366627295-16964-2-git-send-email-Andrew.Murray@arm.com>
Message-ID: <1367721709.11982.37.camel@pasglop>

On Mon, 2013-04-22 at 11:41 +0100, Andrew Murray wrote:
> The pci_process_bridge_OF_ranges function, used to parse the "ranges"
> property of a PCI host device, is found in both Microblaze and PowerPC
> architectures. These implementations are nearly identical. This patch
> moves this common code to a common place.

What's happening with this ? I'd like to avoid that patch for now
as I'm doing some changes to pci_process_bridge_OF_ranges
which are fairly urgent (I might even stick them in the current
merge window) to deal with memory windows having separate offsets.

There's also a few hacks in there that are really ppc specific...

I think the right long term approach is to change the way powerpc
(and microblaze ?) initializes PCI host bridges. Move it away from
setup_arch() (which is a PITA anyway since it's way too early) to
an early init call of some sort, and encapsulate the new struct
pci_host_bridge.

We can then directly configure the host bridge windows rather
than having this "intermediary" set of resources in our pci_controller
and in fact move most of the fields from pci_controller to
pci_host_bridge to the point where the former can remain as a
simple platform specific wrapper if needed.

So for new stuff (hint: DT based ARM PCI) or stuff that has to deal with
a lot less archaic platforms (hint: Microblaze), I'd recommend going
straight for that approach rather than perpetuating the PowerPC code
which I'll try to deal with in the next few monthes.

Cheers,
Ben.
 



From alonid at stratoscale.com  Sun May  5 04:24:13 2013
From: alonid at stratoscale.com (Dan Aloni)
Date: Sun,  5 May 2013 11:24:13 +0300
Subject: [PATCH] Move the EM_ARM and EM_AARCH64 definitions to
 uapi/linux/elf-em.h
In-Reply-To: <20130502132756.GD20730@arm.com>
References: <20130502132756.GD20730@arm.com>
Message-ID: <1367742253-22294-1-git-send-email-alonid@stratoscale.com>

Signed-off-by: Dan Aloni <alonid at stratoscale.com>
CC: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/elf.h   |    2 --
 arch/arm64/include/asm/elf.h |    3 ---
 include/uapi/linux/elf-em.h  |    2 ++
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 38050b1..e110a67 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -19,8 +19,6 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 
 typedef struct user_fp elf_fpregset_t;
 
-#define EM_ARM	40
-
 #define EF_ARM_EABI_MASK	0xff000000
 #define EF_ARM_EABI_UNKNOWN	0x00000000
 #define EF_ARM_EABI_VER1	0x01000000
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index fe32c0e..e7fa87f 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -33,8 +33,6 @@ typedef unsigned long elf_greg_t;
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef struct user_fpsimd_state elf_fpregset_t;
 
-#define EM_AARCH64		183
-
 /*
  * AArch64 static relocation types.
  */
@@ -151,7 +149,6 @@ extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
 #ifdef CONFIG_COMPAT
-#define EM_ARM				40
 #define COMPAT_ELF_PLATFORM		("v8l")
 
 #define COMPAT_ELF_ET_DYN_BASE		(randomize_et_dyn(2 * TASK_SIZE_32 / 3))
diff --git a/include/uapi/linux/elf-em.h b/include/uapi/linux/elf-em.h
index 8e2b7ba..59c17a2 100644
--- a/include/uapi/linux/elf-em.h
+++ b/include/uapi/linux/elf-em.h
@@ -22,6 +22,7 @@
 #define EM_PPC		20	/* PowerPC */
 #define EM_PPC64	21	 /* PowerPC64 */
 #define EM_SPU		23	/* Cell BE SPU */
+#define EM_ARM		40	/* ARM 32 bit */
 #define EM_SH		42	/* SuperH */
 #define EM_SPARCV9	43	/* SPARC v9 64-bit */
 #define EM_IA_64	50	/* HP/Intel IA-64 */
@@ -34,6 +35,7 @@
 #define EM_MN10300	89	/* Panasonic/MEI MN10300, AM33 */
 #define EM_BLACKFIN     106     /* ADI Blackfin Processor */
 #define EM_TI_C6000	140	/* TI C6X DSPs */
+#define EM_AARCH64	183	/* ARM 64 bit */
 #define EM_FRV		0x5441	/* Fujitsu FR-V */
 #define EM_AVR32	0x18ad	/* Atmel AVR32 */
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May  5 07:28:19 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 5 May 2013 13:28:19 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
Message-ID: <20130505112819.GD24282@game.jcrosoft.org>

On 22:52 Sat 04 May     , Linus Walleij wrote:
> On Sat, May 4, 2013 at 3:30 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> 
> > same issue on at91sam9g45ek
> 
> Is it working with mainline (Torvalds) HEAD?
now yes

Best Regards,
J.
> 
> Yours,
> Linus Walleij


From shc_work at mail.ru  Sun May  5 08:18:08 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Sun,  5 May 2013 16:18:08 +0400
Subject: [PATCH] Cpufreq: Fix incorrect dependecies for ARM SA11xx drivers
Message-ID: <1367756288-13422-1-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/cpufreq/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index a1488f5..534fcb8 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -47,7 +47,7 @@ config CPU_FREQ_STAT_DETAILS
 
 choice
 	prompt "Default CPUFreq governor"
-	default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || CPU_FREQ_SA1110
+	default CPU_FREQ_DEFAULT_GOV_USERSPACE if ARM_SA1100_CPUFREQ || ARM_SA1110_CPUFREQ
 	default CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 	help
 	  This option sets which CPUFreq governor shall be loaded at
-- 
1.8.1.5



From bp at alien8.de  Sun May  5 08:36:33 2013
From: bp at alien8.de (Borislav Petkov)
Date: Sun, 5 May 2013 14:36:33 +0200
Subject: [PATCH v4 0/7] enable support for AMBA drivers under x86
In-Reply-To: <20121213181449.GA15966@mail.gnudd.com>
References: <50C93A83.8040106@zytor.com>
 <1355146956-6009-1-git-send-email-ciminaghi@gnudd.com>
 <50C93718.2090706@zytor.com>
 <20121213181449.GA15966@mail.gnudd.com>
Message-ID: <20130505123633.GA14095@pd.tnic>

On Thu, Dec 13, 2012 at 07:14:49PM +0100, Alessandro Rubini wrote:
> This is a long-standing problem, but with not practical effects. I
> proposed a pair of different fixes quite some months ago. I'll respin
> the problem tomorrow.

Did this got fixed in some tree in the meantime? Because I still see it on
current Linus + tip/master:

arch/x86/pci/sta2x11-fixup.c:186:2: warning: initialization from incompatible pointer type [enabled by default]
arch/x86/pci/sta2x11-fixup.c:186:2: warning: (near initialization for ?sta2x11_dma_ops.free?) [enabled by default]

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--


From dan.carpenter at oracle.com  Sun May  5 10:18:55 2013
From: dan.carpenter at oracle.com (Dan Carpenter)
Date: Sun, 5 May 2013 17:18:55 +0300
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <20130503070713.GA27956@bnru09>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
 <20130503070713.GA27956@bnru09>
Message-ID: <20130505141855.GB4686@mwanda>

On Fri, May 03, 2013 at 12:37:14PM +0530, Srinidhi Kasagar wrote:
> On Thu, May 02, 2013 at 17:48:10 +0200, Lee Jones wrote:
> > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
> >         In function ?synaptics_rmi4_resume?:
> > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
> >         warning: ignoring return value of ?regulator_enable?, declared
> >         with attribute warn_unused_result [-Wunused-result
> > 
> > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > Cc: devel at driverdev.osuosl.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > index fe667dd..c4d013d 100644
> > --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > @@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
> >  	unsigned char intr_status;
> >  	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
> >  
> > -	regulator_enable(rmi4_data->regulator);
> > +	retval = regulator_enable(rmi4_data->regulator);
> > +	if (retval < 0)
> > +		return retval;
> Does it make sense to add a dev_err?
> 

Is that a question?

regulator_enable() already prints some warnings.  Probably it's not
going to fail and adding code that is duplicative or will never be
run is pointless.

regards,
dan carpenter



From menon.nishanth at gmail.com  Sun May  5 11:04:52 2013
From: menon.nishanth at gmail.com (Nishanth Menon)
Date: Sun, 05 May 2013 10:04:52 -0500
Subject: [PATCH 0/2] ARM: dts: OMAP36xx/OMAP4460 Fix CPU OPP voltages
In-Reply-To: <1366997973-19120-1-git-send-email-nm@ti.com>
References: <1366997973-19120-1-git-send-email-nm@ti.com>
Message-ID: <51867514.9030803@gmail.com>

Tony/Benoit,
gentle offline ping for this series?
https://patchwork.kernel.org/patch/2494481/
https://patchwork.kernel.org/patch/2494491/
Regards,
Nishanth Menon
On 04/26/2013 12:39 PM, Nishanth Menon wrote:
> Hi,
> It seems that I have not been paying close attention to
> actual voltage value seen on scope to map it back to verify the validity
> of the voltage value. Even though I did verify[1] that voltage did scale to
> values in DT entries, the values in the case of 3630 and 4460 were lower than
> what the spec voltage was as per opp_data files.
>
> This series is based off Benoit's tree here:
> http://git.kernel.org/cgit/linux/kernel/git/bcousson/linux-omap-dt.git/log/?h=for_3.10/dts
>
> Commit ID's in the patches to indicate regressions are from there as well.
> Would be good to have this fix merged to 3.10 dts entries.
> I have cross verified that OMAP3430,3630,4430 and 4460 entries now match that
> of corresponding opp*_data.c
>
> My sincere apologies on the oversight.
>
> Nishanth Menon (2):
>    ARM: dts: OMAP36xx: Fix CPU OPP voltages
>    ARM: dts: OMAP4460: Fix CPU OPP voltages
>
>   arch/arm/boot/dts/omap36xx.dtsi |    6 +++---
>   arch/arm/boot/dts/omap4460.dtsi |    6 +++---
>   2 files changed, 6 insertions(+), 6 deletions(-)
>
> [1] http://marc.info/?l=linux-arm-kernel&m=136580742724210&w=2
> Regards,
> Nishanth Menon
>



From stefano.stabellini at eu.citrix.com  Sun May  5 12:47:12 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Sun, 5 May 2013 17:47:12 +0100
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <5183976A.6000703@arm.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
 <alpine.DEB.2.02.1305031130210.5398@kaball.uk.xensource.com>
 <5183976A.6000703@arm.com>
Message-ID: <alpine.DEB.2.02.1305051745390.4756@kaball.uk.xensource.com>

On Fri, 3 May 2013, Marc Zyngier wrote:
> On 03/05/13 11:43, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Christopher Covington wrote:
> >>> So the virtual timer should appear to have been running even while time
> >>> is being stolen and therefore stolen time needs to be accounted via some
> >>> other means.
> >>
> >> Something that's not currently obvious to me is that given that the stolen
> >> cycle accounting should be done, what makes the architected timer interrupt
> >> handler the ideal place to do it?
> > 
> > That is a good question and I would appreciate suggestions to improve
> > the patch.
> > 
> > Given that Xen x86 and ia64 does stolen time accounting from the timer
> > interrupt handler:
> > 
> > arch/x86/xen/time.c:xen_timer_interrupt
> > arch/ia64/kernel/time.c:timer_interrupt
> > 
> > and given that the arch_timer is the only timer used by Xen on ARM and
> > that it includes a virt_timer that is made on purpose to be used by
> > virtual machines, I thought that it might be a good place for it.
> > 
> > I also thought that doing it this way, KVM should be able to reuse the
> > same hook.
> 
> Indeed. I just need to understand how time stealing works there ;-).
> 
> Now, KVM is not necessarily limited to arch_timers, and we've run KVM
> using a QEMU-provided timer in the past. Can you think of a more generic
> location for this hook? Possibly something that would satisfy the
> requirements of other architectures while we're at it?

Probably the best option would be to reuse

kernel/sched/cputime.c:steal_account_process_tick

but that also means introducing CONFIG_PARAVIRT on arm.
I am up for that, what do you think?


From linus.walleij at linaro.org  Sun May  5 15:57:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 May 2013 21:57:26 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130505112819.GD24282@game.jcrosoft.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
Message-ID: <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>

On Sun, May 5, 2013 at 1:28 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:
> On 22:52 Sat 04 May     , Linus Walleij wrote:
>> On Sat, May 4, 2013 at 3:30 PM, Jean-Christophe PLAGNIOL-VILLARD

>> > same issue on at91sam9g45ek
>>
>> Is it working with mainline (Torvalds) HEAD?
>
> now yes

Thanks! I had some panic there for a while :-)

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sun May  5 16:04:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 May 2013 22:04:58 +0200
Subject: [PATCH v2 1/3] GPIO: clps711x: Rewrite driver for using generic
 GPIO code
In-Reply-To: <1366991250-17130-1-git-send-email-shc_work@mail.ru>
References: <1366991250-17130-1-git-send-email-shc_work@mail.ru>
Message-ID: <CACRpkdZHYmcD7CS42Gmh=QtSEG4zdpEp+x-Nac3oFcnLdTk-hw@mail.gmail.com>

On Fri, Apr 26, 2013 at 5:47 PM, Alexander Shiyan <shc_work at mail.ru> wrote:

> This patch provides rewritten driver for CLPS711X GPIO which uses
> generic GPIO code.
>
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

The series:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Sun May  5 16:13:25 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun,  5 May 2013 22:13:25 +0200
Subject: [PATCH 1/1] ARM: at91: rm9200 fix time support
Message-ID: <1367784805-12040-1-git-send-email-plagnioj@jcrosoft.com>

since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488
Author: Shawn Guo <shawn.guo at linaro.org>
Date:   Sat Jan 12 11:50:05 2013 +0000

ARM: use clockevents_config_and_register() where possible

The timer is wrongly configured and result in since crash
so revert it on rm9200 timer

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Hi Greg,

	if possible apply it to v3.8 and v3.9 stable

	I'll apply it for mainline

Best Regards,
J.
 arch/arm/mach-at91/at91rm9200_time.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 2acdff4..180b302 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 static struct clock_event_device clkevt = {
 	.name		= "at91_tick",
 	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.shift		= 32,
 	.rating		= 150,
 	.set_next_event	= clkevt32k_next_event,
 	.set_mode	= clkevt32k_mode,
@@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void)
 	at91_st_write(AT91_ST_RTMR, 1);
 
 	/* Setup timer clockevent, with minimum of two ticks (important!!) */
+	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
+	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
+	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
 	clkevt.cpumask = cpumask_of(0);
-	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
-					2, AT91_ST_ALMV);
+	clockevents_register_device(&clkevt);
 
 	/* register clocksource */
 	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May  5 16:20:25 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 5 May 2013 22:20:25 +0200
Subject: [PATCH 1/1] ARM: at91: rm9200 fix time support
Message-ID: <20130505202025.GE24282@game.jcrosoft.org>

since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488
Author: Shawn Guo <shawn.guo at linaro.org>
Date:   Sat Jan 12 11:50:05 2013 +0000

ARM: use clockevents_config_and_register() where possible

The timer is wrongly configured and result in since crash
so revert it on rm9200 timer

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Hi Greg,

	if possible apply it to v3.8 and v3.9 stable

	I'll apply it for mainline

Best Regards,
J.
 arch/arm/mach-at91/at91rm9200_time.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 2acdff4..180b302 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 static struct clock_event_device clkevt = {
 	.name		= "at91_tick",
 	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.shift		= 32,
 	.rating		= 150,
 	.set_next_event	= clkevt32k_next_event,
 	.set_mode	= clkevt32k_mode,
@@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void)
 	at91_st_write(AT91_ST_RTMR, 1);
 
 	/* Setup timer clockevent, with minimum of two ticks (important!!) */
+	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
+	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
+	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
 	clkevt.cpumask = cpumask_of(0);
-	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
-					2, AT91_ST_ALMV);
+	clockevents_register_device(&clkevt);
 
 	/* register clocksource */
 	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
-- 
1.7.10.4



From rubini at gnudd.com  Sun May  5 16:24:22 2013
From: rubini at gnudd.com (Alessandro Rubini)
Date: Sun, 5 May 2013 22:24:22 +0200
Subject: [PATCH v4 0/7] enable support for AMBA drivers under x86
In-Reply-To: <20130505123633.GA14095@pd.tnic>
References: <20130505123633.GA14095@pd.tnic>  <50C93A83.8040106@zytor.com>
 <1355146956-6009-1-git-send-email-ciminaghi@gnudd.com>
 <50C93718.2090706@zytor.com>  <20121213181449.GA15966@mail.gnudd.com>
Message-ID: <20130505202422.GA13758@mail.gnudd.com>

> Did this got fixed in some tree in the meantime? Because I still see it on
> current Linus + tip/master:
> 
> arch/x86/pci/sta2x11-fixup.c:186:2: warning: initialization from incompatible pointer type [enabled by default]
> arch/x86/pci/sta2x11-fixup.c:186:2: warning: (near initialization for ???sta2x11_dma_ops.free???) [enabled by default]

Last time I sent the patch was on Feb 22nd:

   The .free field of struct dma_map_ops features a prototype that is
   different from what lib/swiotlb.c offers. The new "attrs" argument in
   dma_ops.free is missing from the generic implementation.

   This removes the build warning by providing a function that just calls
   swiotlb_free_coherent() without passing "attrs", like others do.

I got no reply.

This is the link:

    http://lkml.org/lkml/2013/2/22/111

It is in patchwork here:

    https://patchwork.kernel.org/patch/2175551/

/alessandro


From bp at alien8.de  Sun May  5 16:29:46 2013
From: bp at alien8.de (Borislav Petkov)
Date: Sun, 5 May 2013 22:29:46 +0200
Subject: [PATCH, RFC 11/22] iwlegacy: il_pm_ops is only provided for
 PM_SLEEP
In-Reply-To: <1367507786-505303-12-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-12-git-send-email-arnd@arndb.de>
Message-ID: <20130505202946.GB12757@pd.tnic>

On Thu, May 02, 2013 at 05:16:15PM +0200, Arnd Bergmann wrote:
> This makes sure the conditionals for the declaration match the
> definition, so we provide the alternative
> 
>  #else
>  #define IL_LEGACY_PM_OPS NULL
>  #endif
> 
> in the correct cases.
> 
> drivers/built-in.o:(.data+0x57974): undefined reference to `il_pm_ops'

Yep, I see this too here.

> 
> Cc: Johannes Berg <johannes.berg at intel.com>
> Cc: John W. Linville <linville at tuxdriver.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/net/wireless/iwlegacy/common.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
> index f8246f2..734f1b4 100644
> --- a/drivers/net/wireless/iwlegacy/common.h
> +++ b/drivers/net/wireless/iwlegacy/common.h
> @@ -1832,7 +1832,7 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
>  __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
>  			  u32 beacon_interval);
>  
> -#ifdef CONFIG_PM
> +#ifdef CONFIG_PM_SLEEP
>  extern const struct dev_pm_ops il_pm_ops;
>  
>  #define IL_LEGACY_PM_OPS	(&il_pm_ops)

Btw, you might want to adjust the macro comments for consistency too,
like so. Alternatively, you could simply remove them since they only
clutter two-liner and one can see what it encloses.

--
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2d88f9..4caaf52986a4 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,16 +1832,16 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
 			  u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS	(&il_pm_ops)
 
-#else /* !CONFIG_PM */
+#else /* !CONFIG_PM_SLEEP */
 
 #define IL_LEGACY_PM_OPS	NULL
 
-#endif /* !CONFIG_PM */
+#endif /* !CONFIG_PM_SLEEP */
 
 /*****************************************************
 *  Error Handling Debugging
--

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--


From plagnioj at jcrosoft.com  Sun May  5 16:22:36 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 5 May 2013 22:22:36 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
Message-ID: <20130505202236.GF24282@game.jcrosoft.org>

On 21:57 Sun 05 May     , Linus Walleij wrote:
> On Sun, May 5, 2013 at 1:28 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> > On 22:52 Sat 04 May     , Linus Walleij wrote:
> >> On Sat, May 4, 2013 at 3:30 PM, Jean-Christophe PLAGNIOL-VILLARD
> 
> >> > same issue on at91sam9g45ek
> >>
> >> Is it working with mainline (Torvalds) HEAD?
> >
> > now yes
> 
> Thanks! I had some panic there for a while :-)

I was thinking to put a jenkins to test Linus HEAD all the time
And with some automatic test one some hw

to detect it more quick

Best Regards,
J.


From bp at alien8.de  Sun May  5 16:39:32 2013
From: bp at alien8.de (Borislav Petkov)
Date: Sun, 5 May 2013 22:39:32 +0200
Subject: [PATCH v4 0/7] enable support for AMBA drivers under x86
In-Reply-To: <20130505202422.GA13758@mail.gnudd.com>
References: <20130505123633.GA14095@pd.tnic> <50C93A83.8040106@zytor.com>
 <1355146956-6009-1-git-send-email-ciminaghi@gnudd.com>
 <50C93718.2090706@zytor.com>
 <20121213181449.GA15966@mail.gnudd.com>
 <20130505202422.GA13758@mail.gnudd.com>
Message-ID: <20130505203932.GA12742@pd.tnic>

On Sun, May 05, 2013 at 10:24:22PM +0200, Alessandro Rubini wrote:
> > Did this got fixed in some tree in the meantime? Because I still see it on
> > current Linus + tip/master:
> > 
> > arch/x86/pci/sta2x11-fixup.c:186:2: warning: initialization from incompatible pointer type [enabled by default]
> > arch/x86/pci/sta2x11-fixup.c:186:2: warning: (near initialization for ???sta2x11_dma_ops.free???) [enabled by default]
> 
> Last time I sent the patch was on Feb 22nd:
> 
>    The .free field of struct dma_map_ops features a prototype that is
>    different from what lib/swiotlb.c offers. The new "attrs" argument in
>    dma_ops.free is missing from the generic implementation.
> 
>    This removes the build warning by providing a function that just calls
>    swiotlb_free_coherent() without passing "attrs", like others do.
> 
> I got no reply.

It probably fell through the cracks...

> This is the link:
> 
>     http://lkml.org/lkml/2013/2/22/111
> 
> It is in patchwork here:
> 
>     https://patchwork.kernel.org/patch/2175551/

Ingo, hpa, can you guys pick it up?

Thanks.

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--


From gregkh at linuxfoundation.org  Sun May  5 17:26:55 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Sun, 5 May 2013 14:26:55 -0700
Subject: [PATCH 1/1] ARM: at91: rm9200 fix time support
In-Reply-To: <20130505202025.GE24282@game.jcrosoft.org>
References: <20130505202025.GE24282@game.jcrosoft.org>
Message-ID: <20130505212655.GD12954@kroah.com>

On Sun, May 05, 2013 at 10:20:25PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488
> Author: Shawn Guo <shawn.guo at linaro.org>
> Date:   Sat Jan 12 11:50:05 2013 +0000
> 
> ARM: use clockevents_config_and_register() where possible
> 
> The timer is wrongly configured and result in since crash
> so revert it on rm9200 timer
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
> Hi Greg,
> 
> 	if possible apply it to v3.8 and v3.9 stable
> 
> 	I'll apply it for mainline

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read Documentation/stable_kernel_rules.txt
for how to do this properly.

</formletter>


From gmbnomis at gmail.com  Sun May  5 18:26:47 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 6 May 2013 00:26:47 +0200
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130503100242.GB29962@arm.com>
References: <20130418114016.GG27197@titan.lakedaemon.net>
 <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
Message-ID: <20130505222645.GA1433@schnuecks.de>

On Fri, May 03, 2013 at 11:02:42AM +0100, Catalin Marinas wrote:
> On Thu, May 02, 2013 at 08:38:36PM +0100, Simon Baatz wrote:
> > On Thu, May 02, 2013 at 10:54:31AM +0100, Catalin Marinas wrote:
> > > On Wed, May 01, 2013 at 08:04:41PM +0100, Simon Baatz wrote:
> > > > On Wed, May 01, 2013 at 03:22:06PM +0100, Catalin Marinas wrote:
> > > > > On Tue, Apr 30, 2013 at 10:04:03PM +0100, Simon Baatz wrote:
> > > > > > On Tue, Apr 30, 2013 at 12:22:25PM +0100, Catalin Marinas wrote:
> > > > > > > On Sun, Apr 21, 2013 at 11:06:30PM +0100, Simon Baatz wrote:
> > > > > > > > On Thu, Apr 18, 2013 at 02:51:04PM +0100, Catalin Marinas wrote:
> > > > > > > > > On Thu, Apr 18, 2013 at 12:40:16PM +0100, Jason Cooper wrote:
...
> 
> I haven't run the tests but I can see  why it fails without
> flush_kernel_dcache_page(). So I think this function needs to be
> implemented for aliasing VIPT or VIVT caches.
> 
> > It is even needed in flush_dcache_page() as long as everybody
> > continues to use flush_dcache_page() instead of
> > flush_kernel_dcache_page() when appropriate...
> > (This is probably the main reason why the problem I reported is so
> > uncommon: Everybody seems to use flush_dcache_page() and since it
> > flushes the kernel mapping in these cases, everything is fine.)
> 
> That's why for non-aliasing VIPT we could make it just a clear_bit() and
> let the callers fix their API usage.

Do you mean the unnecessary flush for anon pages or also the D/I
flush for user space mapped page cache pages?

For anon pages, that was the content of the patch you acked ([1])
once.  However, Russel did not like the idea to use the
PG_dcache_clean bit also for anon pages.

I have a newer version that does the following: Do nothing for
mapping == NULL on non-aliasing VIPT in flush_dcache_page().  In
__sync_icache_dcache() flush if mapping == NULL (always on aliasing
VIPT, only if pte_exec() on non-aliasing VIPT).
 
> > > > > > Additionally, although we can assume that the page is kmapped,
> > > > > > page_address(page) can still be NULL for a highmem page, right?
> > > > > 
> > > > > It looks like kmap() always sets page_address(page) but I'm not sure
> > > > > about kmap_atomic(), it doesn't seem to.
> > > > 
> > > > Hmm, in __flush_dcache_page() we have the following code to flush the
> > > > kernel mapping:
> > > > 
> > > > void __flush_dcache_page(struct address_space *mapping, struct page *page)
> > > > {
> > > > 	/*
> > > > 	 * Writeback any data associated with the kernel mapping of this
> > > > 	 * page.  This ensures that data in the physical page is mutually
> > > > 	 * coherent with the kernels mapping.
> > > > 	 */
> > > > 	if (!PageHighMem(page)) {
> > > > 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
> > > > 	} else {
> > > > 		void *addr = kmap_high_get(page);
> > > > 		if (addr) {
> > > > 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> > > > 			kunmap_high(page);
> > > > 		} else if (cache_is_vipt()) {
> > > > 			/* unmapped pages might still be cached */
> > > > 			addr = kmap_atomic(page);
> > > > 			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
> > > > 			kunmap_atomic(addr);
> > > > 		}
> > > > 	}
> > > > ...
> > > > 
> > > > 
> > > > We probably should reuse it in flush_kernel_dcache_page() to flush
> > > > the kernel mapping. (The last else clause looks strange though)
> > > 
> > > I think it makes sense to reuse this logic in
> > > flush_kernel_dcache_page(). If the page is already mapped with kmap,
> > > then kmap_high_get() should return the actual address. If it was mapped
> > > with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
> > > clause and the additional kmap_atomic(). The cache_is_vipt() check is
> > > useful because kunmap_atomic() would flush VIVT caches anyway.
> > 
> > Yes, but why don't we flush for VIPT _aliasing_ already in
> > kunmap_atomic?
> 
> Some comment from Nico on the list, it seems that highmem does not work
> with aliasing VIPT caches:
> 
> http://article.gmane.org/gmane.linux.ports.arm.kernel/85114
> 
> > Why do we need to do anything for non-aliasing VIPT here?
> 
> Do you mean __flush_dcache_page()? I don't think we need.
> 
> > > As for __flush_dcache_page() called from other places like
> > > flush_dcache_page(), because of this 'else if' clause it looks like it
> > > misses flushing unmapped highmem pages on VIVT cache.
> > 
> > How many users do we have with VIVT D-caches using highmem? (This is
> > not a rhetorical questions, I have no idea.  However, I would assume
> > that this use case is almost non-existent.)
> 
> I don't really know. Maybe Nico has more info.
> 
> So my proposal:
> 
> 1. Non-aliasing VIPT - defer any D-cache flushing until
>    __sync_icache_dcache() (and fix callers like uprobes)

See above, not sure whether we can also get rid of the I-cache flush.

> 2. Aliasing VIPT or VIVT - flush the aliases as before in
>    flush_dcache_page()

Yes.

> 3. Aliasing VIPT or VIVT - implement flush_kernel_dcache_page() for all
>    pages (don't check for PageHighmem)

Ok, I will update the first version of my patch.

> 4. VIVT - remove cache flushing from kunmap_atomic and rely on
>    flush_kernel_dcache_page()
> 
> I'm not entirely sure about 4 but at the moment kunmap() doesn't flush
> caches, only kunmap_atomic() so it looks like an inconsistency.

Not sure either. 

- Simon

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/124291.html


From shawn.guo at linaro.org  Sun May  5 22:38:10 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 May 2013 10:38:10 +0800
Subject: [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for
 Vybrid
In-Reply-To: <1367480285-26159-3-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-3-git-send-email-b35083@freescale.com>
Message-ID: <20130506023808.GE1749@S2101-09.ap.freescale.net>

Generally, we use prefix "ARM: dts: ..." for arch/arm/dts and
"ARM: imx: ..." for arch/arm/mach-imx changes.

On Thu, May 02, 2013 at 03:38:05PM +0800, Jingchang Lu wrote:
> This patch adds basic device tree source for Freescale
> Vybrid Family MVF600 platform and Tower development board.
> 
> Signed-off-by: Xiaochun Li <b41219 at freescale.com>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
>   Add pinctrl support based on IMX new pinctrl framework
> 
>  arch/arm/boot/dts/Makefile         |   3 +-
>  arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mvf600-twr.dts   |  80 ++++
>  arch/arm/boot/dts/mvf600.dtsi      | 426 +++++++++++++++++++
>  4 files changed, 1324 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
>  create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
>  create mode 100644 arch/arm/boot/dts/mvf600.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8fd41b3..6402f21 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
>  	imx6q-sabreauto.dtb \
>  	imx6q-sabrelite.dtb \
>  	imx6q-sabresd.dtb \
> -	imx6q-sbc6x.dtb
> +	imx6q-sbc6x.dtb \
> +	mvf600-twr.dtb
>  dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
>  	imx23-olinuxino.dtb \
>  	imx23-stmp378x_devb.dtb \
> diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h
> new file mode 100644
> index 0000000..9fbc7a9
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600-pinfunc.h
> @@ -0,0 +1,816 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DTS_MVF600_PINFUNC_H
> +#define __DTS_MVF600_PINFUNC_H
> +
> +/*
> + * Macro definations for MVF600 pin functions
> + *
> + * On Vybrid,pin's mux mode and pad control are in one 32-bit register.
> + * mux mode bits occupy bit[20:22] and pad config bits occupy bit[[0:15].
> + * So the config word is a combination of mux mode and control config value.
> + * imx common pinctrl driver requires a tuple of six elements to
> + * describe a pin. The tuple for MVF600 is as below:
> + * <mux_reg conf_reg input_reg mux_mode|conf_val input_val mux_mode|conf_val>

As I commented on the pinctrl driver, I prefer to define mvf600 pinfunc
ID as <mux_reg input_reg mux_mode input_val> and have pinctrl driver
handle the differences between mvf600 and imx.

> + */

...

> diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts
> new file mode 100644
> index 0000000..e2dafa2
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600-twr.dts
> @@ -0,0 +1,80 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +/dts-v1/;
> +#include "mvf600.dtsi"
> +
> +/ {
> +	model = "MVF600 Tower Board";
> +	compatible = "fsl,mvf600-twr", "fsl,mvf600";
> +
> +	chosen {
> +		bootargs = "console=ttymxc1,115200";
> +	};
> +
> +	memory {
> +		reg = <0x80000000 0x8000000>;
> +	};
> +
> +	clocks {
> +		osc {
> +			compatible = "fsl,mvf-osc", "fixed-clock";

Please drop the custom compatible for these fixed rate clocks, as we
will use common of_clk_init() to register them.

> +			clock-frequency = <24000000>;
> +		};
> +
> +		audio_clk {
> +			compatible = "fsl,mvf-audio-ext-clk", "fixed-clock";
> +			clock-frequency = <24576000>;
> +		};
> +
> +		enet_clk {
> +			compatible = "fsl,mvf-enet-ext-clk", "fixed-clock";
> +			clock-frequency = <50000000>;
> +		};
> +	};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1_1>;
> +	status = "okay";
> +};
> +
> +&fec0 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec0_1>;
> +};

Please sort the nodes in alphabet order of the labels, something like
the below.

&fec0 {
	...
};

&fec1 {
	...
};

&qspi00 {
	...
};

&uart1 {
	...
};

> +
> +&fec1 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1_1>;
> +};
> +
> +
> +&qspi0 { /* QuadSPI0 */
> +	fsl,spi-num-chipselects = <1>;
> +	fsl,spi-flash-chipselects = <0>;
> +	status = "okay";
> +
> +	flash: s25fl128s at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "spansion,s25fl128s";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +		linux,modalias = "m25p80";
> +		modal = "s25fl128s";
> +		partition at 0 {
> +			label = "s25fl128s";
> +			reg = <0x0 0x1000000>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi
> new file mode 100644
> index 0000000..ca25f80
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600.dtsi
> @@ -0,0 +1,426 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include "skeleton.dtsi"
> +#include "mvf600-pinfunc.h"

Put a blank line here.

> +/ {
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
> +	};
> +
> +

Remove one blank line here.

> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <0>;

If like imx that "osc" is a clock which is defined by SoC, the clock
should be put here rather than board dts.

> +	};
> +
> +

One blank line is enough.

> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&intc>;
> +		ranges;
> +
> +		aips0: aips-bus at 40000000 { /* AIPS0 */

With the label aips0 in front of, the comment "/* AIPS0 */" can just be
saved.

> +			compatible = "fsl,aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-parent = <&intc>;
> +			reg = <0x40000000 0x70000>;
> +			ranges;
> +
> +			mscm: mscm at 40001000 {
> +				compatible = "fsl,mvf-mscm";

We generally specify a particular hardware version by using given SoC
name in compatible.  So in your case, "fsl,mvf600-mscm" is the one we
want to use.

> +				reg = <0x40001000 0x1000>;
> +			};
> +
> +			intc: interrupt-controller at 40002000 {
> +				compatible = "arm,cortex-a9-gic";
> +				#interrupt-cells = <3>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				interrupt-controller;
> +				reg = <0x40003000 0x1000>,
> +				      <0x40002100 0x100>;
> +			};
> +
> +			L2: l2-cache at 40006000 {
> +				compatible = "arm,pl310-cache";
> +				reg = <0x40006000 0x1000>;
> +				interrupts = <0 6 0x04>;
> +				cache-unified;
> +				cache-level = <2>;

You may want the similar change as the patch below adds for imx6?

https://patchwork.kernel.org/patch/2491311/

> +			};
> +
> +			uart0: serial at 40027000 { /* UART0 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x40027000 0x1000>;
> +				interrupts = <0 61 0x00>;
> +				clocks = <&clks 39>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart1: serial at 40028000 { /* UART1 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x40028000 0x1000>;
> +				interrupts = <0 62 0x04>;
> +				clocks = <&clks 40>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart2: serial at 40029000 { /* UART2 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x40029000 0x1000>;
> +				interrupts = <0 63 0x04>;
> +				clocks = <&clks 41>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart3: serial at 4002a000 { /* UART3 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x4002a000 0x1000>;
> +				interrupts = <0 64 0x04>;
> +				clocks = <&clks 42>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			pit:pit at 40037000 {
> +				compatible = "fsl,mvf-pit";
> +				reg = <0x40037000 0x1000>;
> +				interrupts = <0 39 0x04>;
> +				clock-names = "pit";
> +				clocks = <&clks 45>;
> +			};
> +
> +			wdog at 4003e000 {
> +				compatible = "fsl,mvf-wdt";
> +				reg = <0x4003e000 0x1000>;
> +				clock-names = "wdog";
> +				clocks = <&clks 76>;
> +			};
> +
> +			qspi0: quadspi at 40044000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,mvf-qspi";
> +				reg = <0x40044000 0x1000>;
> +				interrupts = <0 24 0x04>;
> +				status = "disabled";
> +			};
> +
> +			iomuxc: iomuxc at 40048000 {
> +				compatible = "fsl,mvf-iomuxc";
> +				reg = <0x40048000 0x1000>;
> +				#gpio-range-cells = <2>;
> +
> +				/* functions and groups pins */
> +				esdhc1 {
> +					pinctrl_esdhc1_1: esdhc1grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA24__ESDHC1_CLK(0x31ef)
> +						MVF600_PAD_PTA25__ESDHC1_CMD(0x31ef)
> +						MVF600_PAD_PTA26__ESDHC1_DAT0(0x31ef)
> +						MVF600_PAD_PTA27__ESDHC1_DAT1(0x31ef)
> +						MVF600_PAD_PTA28__ESDHC1_DATA2(0x31ef)
> +						MVF600_PAD_PTA29__ESDHC1_DAT3(0x31ef)
> +						MVF600_PAD_PTA7__GPIO_134(0x219d)
> +						>;
> +					};
> +				};

Please sort all these iomuxc sub-nodes in alphabet sort of node name, so
that the new pinctrl entries can easily find their places.

Shawn

> +
> +				i2c0 {
> +					pinctrl_i2c0_1: i2c0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB14__I2C0_SCL(0x30d3)
> +						MVF600_PAD_PTB15__I2C0_SDA(0x30d3)
> +						>;
> +					};
> +				};
> +
> +				dspi0 {
> +					pinctrl_dspi0_1: dspi0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB19__DSPI0_CS0(0x1182)
> +						MVF600_PAD_PTB20__DSPI0_SIN(0x1181)
> +						MVF600_PAD_PTB21__DSPI0_SOUT(0x1182)
> +						MVF600_PAD_PTB22__DSPI0_SCK(0x1182)
> +						>;
> +					};
> +				};
> +
> +				fec0 {
> +					pinctrl_fec0_1: fec0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA6__RMII_CLKIN(0x30d1)
> +						MVF600_PAD_PTC0__ENET_RMII0_MDC(0x30d3)
> +						MVF600_PAD_PTC1__ENET_RMII0_MDIO(0x30d1)
> +						MVF600_PAD_PTC2__ENET_RMII0_CRS(0x30d1)
> +						MVF600_PAD_PTC3__ENET_RMII0_RXD1(0x30d1)
> +						MVF600_PAD_PTC4__ENET_RMII0_RXD0(0x30d1)
> +						MVF600_PAD_PTC5__ENET_RMII0_RXER(0x30d1)
> +						MVF600_PAD_PTC6__ENET_RMII0_TXD1(0x30d2)
> +						MVF600_PAD_PTC7__ENET_RMII0_TXD0(0x30d2)
> +						MVF600_PAD_PTC8__ENET_RMII0_TXEN(0x30d2)
> +						>;
> +					};
> +				};
> +
> +				fec1 {
> +					pinctrl_fec1_1: fec1grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTC9__ENET_RMII1_MDC(0x30d2)
> +						MVF600_PAD_PTC10__ENET_RMII1_MDIO(0x30d3)
> +						MVF600_PAD_PTC11__ENET_RMII1_CRS(0x30d1)
> +						MVF600_PAD_PTC12__ENET_RMII_RXD1(0x30d1)
> +						MVF600_PAD_PTC13__ENET_RMII1_RXD0(0x30d1)
> +						MVF600_PAD_PTC14__ENET_RMII1_RXER(0x30d1)
> +						MVF600_PAD_PTC15__ENET_RMII1_TXD1(0x30d2)
> +						MVF600_PAD_PTC16__ENET_RMII1_TXD0(0x30d2)
> +						MVF600_PAD_PTC17__ENET_RMII1_TXEN(0x30d2)
> +						>;
> +					};
> +				};
> +
> +				sai2 {
> +					pinctrl_sai2_1: sai2grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA16__SAI2_TX_BCLK(0x02ed)
> +						MVF600_PAD_PTA18__SAI2_TX_DATA(0x02ee)
> +						MVF600_PAD_PTA19__SAI2_TX_SYNC(0x02ed)
> +						MVF600_PAD_PTA21__SAI2_RX_BCLK(0x02ed)
> +						MVF600_PAD_PTA22__SAI2_RX_DATA(0x02ed)
> +						MVF600_PAD_PTA23__SAI2_RX_SYNC(0x02ed)
> +						MVF600_PAD_PTB18__EXT_AUDIO_MCLK(0x02ed)
> +						>;
> +					};
> +				};
> +
> +				dcu0 {
> +					pinctrl_dcu0_1: dcu0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB8__GPIO_30(0x42)
> +						MVF600_PAD_PTE0__DCU0_HSYNC(0x42)
> +						MVF600_PAD_PTE1__DCU0_VSYNC(0x42)
> +						MVF600_PAD_PTE2__DCU0_PCLK(0x42)
> +						MVF600_PAD_PTE4__DCU0_DE(0x42)
> +						MVF600_PAD_PTE5__DCU0_R0(0x42)
> +						MVF600_PAD_PTE6__DCU0_R1(0x42)
> +						MVF600_PAD_PTE7__DCU0_R2(0x42)
> +						MVF600_PAD_PTE8__DCU0_R3(0x42)
> +						MVF600_PAD_PTE9__DCU0_R4(0x42)
> +						MVF600_PAD_PTE10__DCU0_R5(0x42)
> +						MVF600_PAD_PTE11__DCU0_R6(0x42)
> +						MVF600_PAD_PTE12__DCU0_R7(0x42)
> +						MVF600_PAD_PTE13__DCU0_G0(0x42)
> +						MVF600_PAD_PTE14__DCU0_G1(0x42)
> +						MVF600_PAD_PTE15__DCU0_G2(0x42)
> +						MVF600_PAD_PTE16__DCU0_G3(0x42)
> +						MVF600_PAD_PTE17__DCU0_G4(0x42)
> +						MVF600_PAD_PTE18__DCU0_G5(0x42)
> +						MVF600_PAD_PTE19__DCU0_G6(0x42)
> +						MVF600_PAD_PTE20__DCU0_G7(0x42)
> +						MVF600_PAD_PTE21__DCU0_B0(0x42)
> +						MVF600_PAD_PTE22__DCU0_B1(0x42)
> +						MVF600_PAD_PTE23__DCU0_B2(0x42)
> +						MVF600_PAD_PTE24__DCU0_B3(0x42)
> +						MVF600_PAD_PTE25__DCU0_B4(0x42)
> +						MVF600_PAD_PTE26__DCU0_B5(0x42)
> +						MVF600_PAD_PTE27__DCU0_B6(0x42)
> +						MVF600_PAD_PTE28__DCU0_B7(0x42)
> +						>;
> +					};
> +				};
> +
> +				uart1 {
> +					pinctrl_uart1_1: uart1grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB4__UART1_TX(0x21a2)
> +						MVF600_PAD_PTB5__UART1_RX(0x21a1)
> +						>;
> +					};
> +				};
> +
> +				usbvbus {
> +					pinctrl_usbvbus_1: usbvbusgrp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c)
> +						MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c)
> +						>;
> +					};
> +				};
> +
> +				pwm0 {
> +					pinctrl_pwm0_1: pwm0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB0__FTM0_CH0(0x1582)
> +						MVF600_PAD_PTB1__FTM0_CH1(0x1582)
> +						MVF600_PAD_PTB2__FTM0_CH2(0x1582)
> +						MVF600_PAD_PTB3__FTM0_CH3(0x1582)
> +						MVF600_PAD_PTB6__FTM0_CH6(0x1582)
> +						MVF600_PAD_PTB7__FTM0_CH7(0x1582)
> +						>;
> +					};
> +				};
> +
> +				qspi0 {
> +					pinctrl_qspi0_1: qspi0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTD0__QSPI0_A_QSCK(0x307b)
> +						MVF600_PAD_PTD1__QSPI0_A_CS0(0x307f)
> +						MVF600_PAD_PTD2__QSPI0_A_DATA3(0x3073)
> +						MVF600_PAD_PTD3__QSPI0_A_DATA2(0x3073)
> +						MVF600_PAD_PTD4__QSPI0_A_DATA1(0x3073)
> +						MVF600_PAD_PTD5__QSPI0_A_DATA0(0x307b)
> +						MVF600_PAD_PTD7__QSPI0_B_QSCK(0x307b)
> +						MVF600_PAD_PTD8__QSPI0_B_CS0(0x307f)
> +						MVF600_PAD_PTD9__QSPI0_B_DATA3(0x3073)
> +						MVF600_PAD_PTD10__QSPI0_B_DATA2(0x3073)
> +						MVF600_PAD_PTD11__QSPI0_B_DATA1(0x3073)
> +						MVF600_PAD_PTD12__QSPI0_B_DATA0(0x307b)
> +						>;
> +					};
> +				};
> +
> +				touchscreen0 {
> +					pinctrl_ts0_1: ts0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA31__GPIO_21(0x219d)
> +						>;
> +					};
> +				};
> +
> +			};
> +
> +			gpio1: gpio at 40049000 {
> +				compatible = "fsl,mvf-gpio";
> +				reg = <0x40049000 0x1000 0x400ff000 0x40>;
> +				interrupts = <0 107 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 0 32>;
> +			};
> +
> +			gpio2: gpio at 4004a000 {
> +				compatible = "fsl,mvf-gpio";
> +				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
> +				interrupts = <0 108 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 32 32>;
> +			};
> +
> +			gpio3: gpio at 4004b000 {
> +				compatible = "fsl,mvf-gpio";
> +				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
> +				interrupts = <0 109 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 64 32>;
> +			};
> +
> +			gpio4: gpio at 4004c000 {
> +				compatible = "fsl,mvf-gpio";
> +				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
> +				interrupts = <0 110 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 96 32>;
> +			};
> +
> +			gpio5: gpio at 4004d000 {
> +				compatible = "fsl,mvf-gpio";
> +				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
> +				interrupts = <0 111 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 128 7>;
> +			};
> +
> +			anatop at 40050000 {
> +				compatible = "fsl,mvf-anatop";
> +				reg = <0x40050000 0x1000>;
> +			};
> +
> +			clks: ccm at 4006b000 {
> +				compatible = "fsl,mvf-ccm";
> +				reg = <0x4006b000 0x1000>;
> +				#clock-cells = <1>;
> +			};
> +
> +		};
> +
> +		aips1: aips-bus at 40080000 { /* AIPS1 */
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x40080000 0x80000>;
> +			ranges;
> +
> +			uart4: serial at 400a9000 { /* UART4 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x400a9000 0x1000>;
> +				interrupts = <0 65 0x04>;
> +				clocks = <&clks 43>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart5: serial at 400aa000 { /* UART5 */
> +				compatible = "fsl,mvf-uart";
> +				reg = <0x400aa000 0x1000>;
> +				interrupts = <0 66 0x04>;
> +				clocks = <&clks 44>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			fec0: ethernet at 400d0000 {
> +				compatible = "fsl,mvf-fec";
> +				reg = <0x400d0000 0x1000>;
> +				interrupts = <0 78 0x04>;
> +				clocks = <&clks 69>, <&clks 69>, <&clks 69>;
> +				clock-names = "ipg", "ahb", "ptp";
> +			};
> +
> +			fec1: ethernet at 400d1000 {
> +				compatible = "fsl,mvf-fec";
> +				reg = <0x400d1000 0x1000>;
> +				interrupts = <0 79 0x04>;
> +				clocks = <&clks 69>, <&clks 69>, <&clks 69>;
> +				clock-names = "ipg", "ahb", "ptp";
> +			};
> +
> +		};
> +	};
> +};
> -- 
> 1.8.0
> 
> 



From neilb at suse.de  Sun May  5 22:40:11 2013
From: neilb at suse.de (NeilBrown)
Date: Mon, 6 May 2013 12:40:11 +1000
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130502153834.GR28721@atomide.com>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com>
Message-ID: <20130506124011.7e4c2806@notabene.brown>

On Thu, 2 May 2013 08:38:34 -0700 Tony Lindgren <tony at atomide.com> wrote:

> > drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
> > drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result
> 
> Neil, care to provide a fix for this? It's from your commit ab37813
> (twl4030_charger: Allow charger to control the regulator that feeds it).
> 
>
This the sort of thing that might be appropriate?

NeilBrown


From: NeilBrown <neilb at suse.de>
Date: Mon, 6 May 2013 12:35:59 +1000
Subject: [PATCH] twl4030_charger: don't ignore regulator_enable()

regulator_enable() doesn't like being ignored.  If it does fail there
is nothing we can do except not set usb_enabled (which is necessary
else a subsequent regulator_disable() will be unbalanced).

We cannot usefully return an error here as errors from
twl4030_charger_enable_usb() are ignored.

Signed-off-by: NeilBrown <neilb at suse.de>

diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c
index bed4581..8b0ec70 100644
--- a/drivers/power/twl4030_charger.c
+++ b/drivers/power/twl4030_charger.c
@@ -189,8 +189,8 @@ static int twl4030_charger_enable_usb(struct twl4030_bci *bci, bool enable)
 
 		/* Need to keep regulator on */
 		if (!bci->usb_enabled) {
-			regulator_enable(bci->usb_reg);
-			bci->usb_enabled = 1;
+			if (regulator_enable(bci->usb_reg) == 0)
+				bci->usb_enabled = 1;
 		}
 
 		/* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */
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From shawn.guo at linaro.org  Sun May  5 22:54:48 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 May 2013 10:54:48 +0800
Subject: [PATCH V2 1/2] pinctrl/mvf: add MVF pinctrl driver
In-Reply-To: <1367480932-22318-1-git-send-email-b35083@freescale.com>
References: <1367480932-22318-1-git-send-email-b35083@freescale.com>
Message-ID: <20130506025447.GF1749@S2101-09.ap.freescale.net>

On Thu, May 02, 2013 at 03:48:51PM +0800, Jingchang Lu wrote:
> It adds Freescale Vybrid Family pin controller
> driver to IMX iomuxc common driver framework.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
>   Update the driver according to the IMX new pinctrl framework
> 
>  .../bindings/pinctrl/fsl,mvf-pinctrl.txt           |  48 +++

fsl,mvf600-pinctrl.txt

>  drivers/pinctrl/Kconfig                            |   8 +
>  drivers/pinctrl/Makefile                           |   1 +
>  drivers/pinctrl/pinctrl-mvf.c                      | 337 +++++++++++++++++++++

pinctrl-mvf600.c

>  4 files changed, 394 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt
>  create mode 100644 drivers/pinctrl/pinctrl-mvf.c
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt
> new file mode 100644
> index 0000000..60f06cc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,mvf-pinctrl.txt
> @@ -0,0 +1,48 @@
> +Freescale Vybrid IOMUX Controller
> +
> +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
> +and usage.
> +
> +Note:
> +- On Vybrid, pin's mux mode and pad control are in one 32-bit register.
> +  mux mode bits occupy bit[20:22] and config bits occupy bit[[0:15].
> +  So the config word is a combination of mux_mode and pad control value.
> +
> +Required properties:
> +- compatible: "fsl,mvf-iomuxc"

fsl,mvf600-iomuxc

> +- fsl,pins: A pin function macro with one argument, represents a group of
> +  pin's mux and pad control setting.
> +  The format is fsl,pins = < PIN_FUNC_ID(CONFIG) >, PIN_FUNC_ID is a pin
> +  working on a specific function, CONFIG is the pad setting value such as
> +  pull-up, spedd, ode and so on for this pin.
> +  Please refer to Vybrid datasheet for the valid pad mux and control settings.
> +
> +CONFIG bits definition:
> +PAD_MUX_MODE(x)			(x << 20)
> +PAD_CTL_SPEED_LOW		(1 << 12)
> +PAD_CTL_SPEED_MED		(2 << 12)
> +PAD_CTL_SPEED_HIGH		(3 << 12)
> +PAD_CTL_SRE_FAST		(1 << 11)
> +PAD_CTL_SRE_SLOW		(0 << 11)
> +PAD_CTL_ODE			(1 << 10)
> +PAD_CTL_HYS			(1 << 9)
> +PAD_CTL_DSE_DISABLE		(0 << 6)
> +PAD_CTL_DSE_150ohm		(1 << 6)
> +PAD_CTL_DSE_75ohm		(2 << 6)
> +PAD_CTL_DSE_50ohm		(3 << 6)
> +PAD_CTL_DSE_37ohm		(4 << 6)
> +PAD_CTL_DSE_30ohm		(5 << 6)
> +PAD_CTL_DSE_25ohm		(6 << 6)
> +PAD_CTL_DSE_20ohm		(7 << 6)
> +PAD_CTL_PUS_100K_DOWN		(0 << 4)
> +PAD_CTL_PUS_47K_UP		(1 << 4)
> +PAD_CTL_PUS_100K_UP		(2 << 4)
> +PAD_CTL_PUS_22K_UP		(3 << 4)
> +PAD_CTL_PKE			(1 << 3)
> +PAD_CTL_PUE			(1 << 2)
> +PAD_CTL_OBE_ENABLE		(1 << 1)
> +PAD_CTL_IBE_ENABLE		(1 << 0)
> +PAD_CTL_OBE_IBE_ENABLE		(3 << 0)
> +
> +Please refer to mvf600-pinfunc.h in device tree source folder
> +for all available PIN_FUNC_ID for Vybrid.
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 8f66924..885859c 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -108,6 +108,14 @@ config PINCTRL_IMX6SL
>  	help
>  	  Say Y here to enable the imx6sl pinctrl driver
>  
> +config PINCTRL_MVF

PINCTRL_MVF600

> +	bool "Vybrid pinctrl driver"
> +	depends on OF
> +	depends on SOC_MVF600
> +	select PINCTRL_IMX
> +	help
> +	  Say Y here to enable the Freescale Vybrid pinctrl driver
> +
>  config PINCTRL_LANTIQ
>  	bool
>  	depends on LANTIQ
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 9bdaeb8..ec6d7b9 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
>  obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o
>  obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
>  obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
> +obj-$(CONFIG_PINCTRL_MVF)	+= pinctrl-mvf.o
>  
>  obj-$(CONFIG_PLAT_ORION)        += mvebu/
>  obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
> diff --git a/drivers/pinctrl/pinctrl-mvf.c b/drivers/pinctrl/pinctrl-mvf.c
> new file mode 100644
> index 0000000..65041f9
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-mvf.c
> @@ -0,0 +1,337 @@
> +/*
> + * Vybrid pinctrl driver based on imx pinmux and pinconf core
> + *
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-imx.h"

...

> +static struct imx_pinctrl_soc_info mvf600_pinctrl_info = {
> +	.pins = mvf600_pinctrl_pads,
> +	.npins = ARRAY_SIZE(mvf600_pinctrl_pads),
> +};
> +
> +static struct of_device_id mvf600_pinctrl_of_match[] = {
> +	{ .compatible = "fsl,mvf-iomuxc", },
> +	{ /* sentinel */ }
> +};
> +
> +static int mvf600_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return imx_pinctrl_probe(pdev, &mvf600_pinctrl_info);
> +}
> +
> +static struct platform_driver mvf600_pinctrl_driver = {
> +	.driver = {
> +		.name = "mvf600-pinctrl",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_match_ptr(mvf600_pinctrl_of_match),
> +	},
> +	.probe = mvf600_pinctrl_probe,
> +	.remove = imx_pinctrl_remove,
> +};
> +
> +static int __init mvf600_pinctrl_init(void)
> +{
> +	return platform_driver_register(&mvf600_pinctrl_driver);
> +}
> +arch_initcall(mvf600_pinctrl_init);
> +
> +static void __exit mvf600_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&mvf600_pinctrl_driver);
> +}
> +module_exit(mvf600_pinctrl_exit);

Put a blank line here.

Shawn

> +MODULE_DESCRIPTION("Freescale MVF600 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.0
> 
> 



From srinidhi.kasagar at stericsson.com  Mon May  6 02:51:39 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Mon, 6 May 2013 12:21:39 +0530
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <20130505141855.GB4686@mwanda>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
 <20130503070713.GA27956@bnru09> <20130505141855.GB4686@mwanda>
Message-ID: <20130506065138.GA31763@bnru10>

On Sun, May 05, 2013 at 16:18:55 +0200, Dan Carpenter wrote:
> On Fri, May 03, 2013 at 12:37:14PM +0530, Srinidhi Kasagar wrote:
> > On Thu, May 02, 2013 at 17:48:10 +0200, Lee Jones wrote:
> > > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
> > >         In function ?synaptics_rmi4_resume?:
> > > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
> > >         warning: ignoring return value of ?regulator_enable?, declared
> > >         with attribute warn_unused_result [-Wunused-result
> > > 
> > > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > > Cc: devel at driverdev.osuosl.org
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > > ---
> > >  drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > > index fe667dd..c4d013d 100644
> > > --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > > +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > > @@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
> > >  	unsigned char intr_status;
> > >  	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
> > >  
> > > -	regulator_enable(rmi4_data->regulator);
> > > +	retval = regulator_enable(rmi4_data->regulator);
> > > +	if (retval < 0)
> > > +		return retval;
> > Does it make sense to add a dev_err?
> > 
> 
> Is that a question?
> 
> regulator_enable() already prints some warnings.  Probably it's not
> going to fail and adding code that is duplicative or will never be
> run is pointless.

It has become a habit checking the return value and spit some errors.
And BTW, there are many drivers which does this way..Anyway if your
intention is to avoid them for the new drivers..I dont mind skipping
this..

regards/srinidhi


> 
> regards,
> dan carpenter
> 


From srinidhi.kasagar at stericsson.com  Mon May  6 02:55:53 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Mon, 6 May 2013 12:25:53 +0530
Subject: [PATCH 61/63] ARM: ux500: Stop passing DMA platform data
 though AUXDATA
In-Reply-To: <1367591569-32197-62-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-62-git-send-email-lee.jones@linaro.org>
Message-ID: <20130506065552.GA14706@bnru10>

On Fri, May 03, 2013 at 16:32:47 +0200, Lee Jones wrote:
> The DMA platform data is now empty due to some recent refactoring,
> so there is no longer a requirement to pass it though.
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/cpu-db8500.c |    3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
> index a2c83c2..2b6cbde 100644
> --- a/arch/arm/mach-ux500/cpu-db8500.c
> +++ b/arch/arm/mach-ux500/cpu-db8500.c
> @@ -264,8 +264,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
>  	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
>  		"ux500-msp-i2s.3", &msp3_platform_data),
>  	/* Requires clock name bindings and channel address lookup table. */
> -	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
> -		       "dma40.0", &dma40_plat_data),
> +	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),

Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>

srinidhi


From hvaibhav at ti.com  Mon May  6 03:06:25 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 6 May 2013 07:06:25 +0000
Subject: mach-omap2/timer.c: Bug introduced while merging patch - ff931c82
Message-ID: <79CD15C6BA57404B839C016229A409A83EC7C45D@DBDE04.ent.ti.com>

Hi,

Not sure whether this got discussed and fixed already, but Google didn't give me anything :)

The below commit got merged wrongly to Mainline (Changes from timer.c got missed), and 
due to this none of omap boards will boot.


>From ff931c821bab6713a52b768b0cd7ee7e90713b36 Mon Sep 17 00:00:00 2001
From: Rajendra Nayak <rnayak at ti.com>
Date: Thu, 21 Mar 2013 11:04:52 +0000
Subject: ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized


It seems Linux-omap tree has the fix patch for this, and it should get pushed ASAP. 
Below are links for Linus's mainline commit [1], the actual patch submitted to the list [2] and
Commit  present in Linux-omap [3].


[1] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/arm/mach-omap2/io.c?id=ff931c821bab6713a52b768b0cd7ee7e90713b36
[2] https://patchwork.kernel.org/patch/2300071/
[3] http://git.kernel.org/cgit/linux/kernel/git/tmlind/linux-omap.git/commit/arch/arm/mach-omap2/timer.c?id=ff931c821bab6713a52b768b0cd7ee7e90713b36


Thanks,
Vaibhav



From srinidhi.kasagar at stericsson.com  Mon May  6 03:13:56 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Mon, 6 May 2013 12:43:56 +0530
Subject: [PATCH 54/63] ARM: ux500: Replace ST-E's home-brew DMA
 direction definition with the generic one
In-Reply-To: <1367591569-32197-55-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-55-git-send-email-lee.jones@linaro.org>
Message-ID: <20130506071355.GA5552@bnru10>

On Fri, May 03, 2013 at 16:32:40 +0200, Lee Jones wrote:
> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/board-mop500-audio.c |   12 ++++++------
>  arch/arm/mach-ux500/board-mop500-sdi.c   |   16 ++++++++--------
>  arch/arm/mach-ux500/board-mop500.c       |   22 +++++++++++-----------
>  arch/arm/mach-ux500/usb.c                |    4 ++--
>  4 files changed, 27 insertions(+), 27 deletions(-)

Hope you have taken care for all other files, because, I see
few more instances in my tree apart from the above files.

Otherwise..

Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>

regards,
srinidhi


From axel.lin at ingics.com  Mon May  6 03:15:03 2013
From: axel.lin at ingics.com (Axel Lin)
Date: Mon, 06 May 2013 15:15:03 +0800
Subject: [PATCH] ARM: U300: Add proper ifdef guard to fix build error when
 CONFIG_I2C_STU300=m
Message-ID: <1367824503.6190.1.camel@phoenix>

I got below build error if CONFIG_I2C_STU300=m.

ERROR: "i2c_register_board_info" [arch/arm/mach-u300/i2c.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2

Fix it by adding proper ifdef guard in i2c.h and Makefile.
So arch/arm/mach-u300/i2c.c will be compiled when CONFIG_I2C_STU300 is
configured as built-in or as a module.

Signed-off-by: Axel Lin <axel.lin at ingics.com>
---
 arch/arm/mach-u300/Makefile | 4 +++-
 arch/arm/mach-u300/i2c.h    | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58..f612d17 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -9,5 +9,7 @@ obj-		:=
 
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
-obj-$(CONFIG_I2C_STU300)          += i2c.o
+ifneq ($(CONFIG_I2C_STU300),)
+obj-y          += i2c.o
+endif
 obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
index 485c02e..9eec276 100644
--- a/arch/arm/mach-u300/i2c.h
+++ b/arch/arm/mach-u300/i2c.h
@@ -11,7 +11,7 @@
 #ifndef MACH_U300_I2C_H
 #define MACH_U300_I2C_H
 
-#ifdef CONFIG_I2C_STU300
+#if IS_ENABLED(ISCONFIG_I2C_STU300)
 void __init u300_i2c_register_board_devices(void);
 #else
 /* Compile out this stuff if no I2C adapter is available */
-- 
1.8.1.2





From srinidhi.kasagar at stericsson.com  Mon May  6 03:17:34 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Mon, 6 May 2013 12:47:34 +0530
Subject: [PATCH 56/63] ARM: ux500: Remove recently unused
 stedma40_xfer_dir enums
In-Reply-To: <1367591569-32197-57-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-57-git-send-email-lee.jones@linaro.org>
Message-ID: <20130506071733.GA30181@bnru10>

On Fri, May 03, 2013 at 16:32:42 +0200, Lee Jones wrote:
> We're now using the transfer direction definitions provided by the DMA
> sub-system, so the home-brew ones have become obsolete.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  include/linux/platform_data/dma-ste-dma40.h |   10 +---------
>  1 file changed, 1 insertion(+), 9 deletions(-)
> 
> diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
> index 288dc24..54ddca6 100644
> --- a/include/linux/platform_data/dma-ste-dma40.h
> +++ b/include/linux/platform_data/dma-ste-dma40.h
> @@ -77,14 +77,6 @@ enum stedma40_periph_data_width {
>  	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
>  };
>  
> -enum stedma40_xfer_dir {
> -	STEDMA40_MEM_TO_MEM = 1,
> -	STEDMA40_MEM_TO_PERIPH,
> -	STEDMA40_PERIPH_TO_MEM,
> -	STEDMA40_PERIPH_TO_PERIPH
> -};
> -
> -
>  /**
>   * struct stedma40_half_channel_info - dst/src channel configuration
>   *
> @@ -120,7 +112,7 @@ struct stedma40_half_channel_info {
>   *
>   */
>  struct stedma40_chan_cfg {
> -	enum stedma40_xfer_dir			 dir;
> +	enum dma_transfer_direction		 dir;


Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>

srinidhi

>  	bool					 high_priority;
>  	bool					 realtime;
>  	enum stedma40_mode			 mode;
> -- 
> 1.7.10.4
> 


From xiechao.mail at gmail.com  Mon May  6 03:22:39 2013
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 6 May 2013 15:22:39 +0800
Subject: [V9 PATCH 01/12] usb: phy: protect phy init and shutdown for
 mutiple deivces
In-Reply-To: <20130429182441.GA1632@arwen.pp.htv.fi>
References: <1366784606-1813-1-git-send-email-chao.xie@marvell.com>
 <1366784606-1813-2-git-send-email-chao.xie@marvell.com>
 <20130429182441.GA1632@arwen.pp.htv.fi>
Message-ID: <CADApbeiKnTSscVrPrCWzZjrJKW9XnyHxNuvy_ReaLEaKgPb+Tg@mail.gmail.com>

On Tue, Apr 30, 2013 at 2:24 AM, Felipe Balbi <balbi at ti.com> wrote:
> On Wed, Apr 24, 2013 at 02:23:15AM -0400, Chao Xie wrote:
>> diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
>> index 6b5978f..98d7e60 100644
>> --- a/include/linux/usb/phy.h
>> +++ b/include/linux/usb/phy.h
>> @@ -87,6 +87,14 @@ struct usb_phy {
>>       /* to support controllers that have multiple transceivers */
>>       struct list_head        head;
>>
>> +     /*
>> +      * PHY may be shared by multiple devices.
>> +      * mutex and refcount are used to make sure PHY only initialize or
>> +      * shutdown once.
>
> bad grammar in this sentence.
>

I will fix it in the next version.

>> +      */
>> +     struct mutex            phy_mutex;
>> +     unsigned int            refcount;
>
> why don't you use an atomic_t ?
>

Mutex will protect both ->init and ->shutdown routines. Thanks for
Russell's explanation.

> --
> balbi

Can you help to review other patches in this series? So I can fix all
the errors in the next version.
Thanks.


From jassisinghbrar at gmail.com  Mon May  6 03:22:26 2013
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon,  6 May 2013 12:52:26 +0530
Subject: [PATCHv2 0/4] mailbox: Common API
Message-ID: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>

Hello,
  I have made the implementation look more proper. Also made some changes
suggested by Suman. Changes since V1:

* Delete timer upon mailbox release
* Filled in the stub ipc_links_unregister()
* Check kzalloc return for errors.
* Add the controller driver for OMAP2 class. I have taken the patch
  for mailbox's hwmod from Suman's. The clients are yet to be converted
  but this should be enough to convey the idea that the API could
  work for OMAP as well. If I had access to STE documentation, I might
  have done some implementation for U8500 as well.

 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   12 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   11 +
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   11 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   13 +
 drivers/cpufreq/highbank-cpufreq.c         |   22 +-
 drivers/mailbox/Kconfig                    |    9 +
 drivers/mailbox/Makefile                   |    7 +-
 drivers/mailbox/mailbox.c                  |  494 ++++++++++++++++++++++++++++
 drivers/mailbox/omap2.c                    |  420 +++++++++++++++++++++++
 drivers/mailbox/pl320-ipc.c                |  198 -----------
 drivers/mailbox/pl320.c                    |  212 ++++++++++++
 include/linux/mailbox.h                    |   28 +-
 include/linux/mailbox_client.h             |   85 +++++
 include/linux/mailbox_controller.h         |  102 ++++++
 include/linux/platform_data/mailbox-omap.h |   64 ++++
 15 files changed, 1473 insertions(+), 215 deletions(-)

Cheers,
-Jassi


From jassisinghbrar at gmail.com  Mon May  6 03:23:44 2013
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon,  6 May 2013 12:53:44 +0530
Subject: [PATCHv2 1/4] mailbox: rename pl320-ipc specific mailbox.h
In-Reply-To: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <1367825024-6195-1-git-send-email-jaswinder.singh@linaro.org>

From: Suman Anna <s-anna at ti.com>

The patch 30058677 "ARM / highbank: add support for pl320 IPC"
added a pl320 IPC specific header file as a generic mailbox.h.
This file has been renamed appropriately to allow the
introduction of the generic mailbox API framework.

Acked-by: Mark Langsdorf <mark.langsdorf at calxeda.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
Signed-off-by: Suman Anna <s-anna at ti.com>
---
 drivers/cpufreq/highbank-cpufreq.c |    2 +-
 drivers/mailbox/pl320-ipc.c        |    2 +-
 include/linux/mailbox.h            |   17 -----------------
 include/linux/pl320-ipc.h          |   17 +++++++++++++++++
 4 files changed, 19 insertions(+), 19 deletions(-)
 delete mode 100644 include/linux/mailbox.h
 create mode 100644 include/linux/pl320-ipc.h

diff --git a/drivers/cpufreq/highbank-cpufreq.c b/drivers/cpufreq/highbank-cpufreq.c
index b61b5a3..3118b87 100644
--- a/drivers/cpufreq/highbank-cpufreq.c
+++ b/drivers/cpufreq/highbank-cpufreq.c
@@ -19,7 +19,7 @@
 #include <linux/cpu.h>
 #include <linux/err.h>
 #include <linux/of.h>
-#include <linux/mailbox.h>
+#include <linux/pl320-ipc.h>
 #include <linux/platform_device.h>
 
 #define HB_CPUFREQ_CHANGE_NOTE	0x80000001
diff --git a/drivers/mailbox/pl320-ipc.c b/drivers/mailbox/pl320-ipc.c
index d873cba..f3755e0 100644
--- a/drivers/mailbox/pl320-ipc.c
+++ b/drivers/mailbox/pl320-ipc.c
@@ -26,7 +26,7 @@
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 
-#include <linux/mailbox.h>
+#include <linux/pl320-ipc.h>
 
 #define IPCMxSOURCE(m)		((m) * 0x40)
 #define IPCMxDSET(m)		(((m) * 0x40) + 0x004)
diff --git a/include/linux/mailbox.h b/include/linux/mailbox.h
deleted file mode 100644
index 5161f63..0000000
--- a/include/linux/mailbox.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-int pl320_ipc_transmit(u32 *data);
-int pl320_ipc_register_notifier(struct notifier_block *nb);
-int pl320_ipc_unregister_notifier(struct notifier_block *nb);
diff --git a/include/linux/pl320-ipc.h b/include/linux/pl320-ipc.h
new file mode 100644
index 0000000..5161f63
--- /dev/null
+++ b/include/linux/pl320-ipc.h
@@ -0,0 +1,17 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+int pl320_ipc_transmit(u32 *data);
+int pl320_ipc_register_notifier(struct notifier_block *nb);
+int pl320_ipc_unregister_notifier(struct notifier_block *nb);
-- 
1.7.10.4



From jassisinghbrar at gmail.com  Mon May  6 03:24:06 2013
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon,  6 May 2013 12:54:06 +0530
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>

Introduce common framework for client/protocol drivers and
controller drivers of Inter-Processor-Communication (IPC).

Client driver developers should have a look at
 include/linux/mailbox_client.h to understand the part of
the API exposed to client drivers.
Similarly controller driver developers should have a look
at include/linux/mailbox_controller.h

Signed-off-by: Jassi Brar <jaswinder.singh at linaro.org>
---
 drivers/mailbox/Makefile           |    4 +
 drivers/mailbox/mailbox.c          |  494 ++++++++++++++++++++++++++++++++++++
 include/linux/mailbox.h            |   17 ++
 include/linux/mailbox_client.h     |   85 +++++++
 include/linux/mailbox_controller.h |  102 ++++++++
 5 files changed, 702 insertions(+)
 create mode 100644 drivers/mailbox/mailbox.c
 create mode 100644 include/linux/mailbox.h
 create mode 100644 include/linux/mailbox_client.h
 create mode 100644 include/linux/mailbox_controller.h

diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 543ad6a..fefef7e 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -1 +1,5 @@
+# Generic MAILBOX API
+
+obj-$(CONFIG_MAILBOX)		+= mailbox.o
+
 obj-$(CONFIG_PL320_MBOX)	+= pl320-ipc.o
diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
new file mode 100644
index 0000000..a93c22f
--- /dev/null
+++ b/drivers/mailbox/mailbox.c
@@ -0,0 +1,494 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/mailbox_client.h>
+#include <linux/mailbox_controller.h>
+
+/*
+ * The length of circular buffer for queuing messages from a client.
+ * 'msg_count' tracks the number of buffered messages while 'msg_free'
+ * is the index where the next message would be buffered.
+ * We shouldn't need it too big because every transferr is interrupt
+ * triggered and if we have lots of data to transfer, the interrupt
+ * latencies are going to be the bottleneck, not the buffer length.
+ * Besides, ipc_send_message could be called from atomic context and
+ * the client could also queue another message from the notifier 'txcb'
+ * of the last transfer done.
+ */
+#define MBOX_TX_QUEUE_LEN	10
+
+#define TXDONE_BY_IRQ	(1 << 0) /* controller has remote RTR irq */
+#define TXDONE_BY_POLL	(1 << 1) /* controller can read status of last TX */
+#define TXDONE_BY_ACK	(1 << 2) /* S/W ACK recevied by Client ticks the TX */
+
+struct ipc_chan {
+	char chan_name[32]; /* controller_name:link_name */
+	unsigned txdone_method;
+
+	/* Cached values from controller */
+	struct ipc_link *link;
+	struct ipc_link_ops *link_ops;
+
+	/* Cached values from client */
+	void (*rxcb)(void *data);
+	void (*txcb)(request_token_t t, enum xfer_result r);
+	bool tx_block;
+	unsigned long tx_tout;
+	struct completion tx_complete;
+
+	request_token_t active_token;
+	unsigned msg_count, msg_free;
+	void *msg_data[MBOX_TX_QUEUE_LEN];
+	/* Timer shared by all links of a controller */
+	struct tx_poll_timer *timer;
+	bool assigned;
+	/* Serialize access to the channel */
+	spinlock_t lock;
+	/* Hook to add to the global list of channels */
+	struct list_head node;
+	/* Notifier to all clients waiting on aquiring this channel */
+	struct blocking_notifier_head avail;
+};
+
+/*
+ * If the controller supports only TXDONE_BY_POLL, this
+ * timer polls all the links for txdone.
+ */
+struct tx_poll_timer {
+	struct timer_list poll;
+	unsigned period;
+};
+
+static LIST_HEAD(ipc_channels);
+static DEFINE_MUTEX(chpool_mutex);
+
+static request_token_t _add_to_rbuf(struct ipc_chan *chan, void *data)
+{
+	request_token_t idx;
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	/* See if there is any space left */
+	if (chan->msg_count == MBOX_TX_QUEUE_LEN) {
+		spin_unlock_irqrestore(&chan->lock, flags);
+		return 0;
+	}
+
+	idx = chan->msg_free;
+	chan->msg_data[idx] = data;
+	chan->msg_count++;
+
+	if (idx == MBOX_TX_QUEUE_LEN - 1)
+		chan->msg_free = 0;
+	else
+		chan->msg_free++;
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	return idx + 1;
+}
+
+static void _msg_submit(struct ipc_chan *chan)
+{
+	struct ipc_link *link = chan->link;
+	unsigned count, idx;
+	unsigned long flags;
+	void *data;
+	int err;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (!chan->msg_count || chan->active_token) {
+		spin_unlock_irqrestore(&chan->lock, flags);
+		return;
+	}
+
+	count = chan->msg_count;
+	idx = chan->msg_free;
+	if (idx >= count)
+		idx -= count;
+	else
+		idx += MBOX_TX_QUEUE_LEN - count;
+
+	data = chan->msg_data[idx];
+
+	/* Try to submit a message to the IPC controller */
+	err = chan->link_ops->send_data(link, data);
+	if (!err) {
+		chan->active_token = idx + 1;
+		chan->msg_count--;
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static void tx_tick(struct ipc_chan *chan, enum xfer_result r)
+{
+	unsigned long flags;
+	request_token_t t;
+
+	spin_lock_irqsave(&chan->lock, flags);
+	t = chan->active_token;
+	chan->active_token = 0;
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	/* Submit next message */
+	_msg_submit(chan);
+
+	/* Notify the client */
+	if (chan->tx_block)
+		complete(&chan->tx_complete);
+	else if (t && chan->txcb)
+		chan->txcb(t, r);
+}
+
+static void poll_txdone(unsigned long data)
+{
+	struct tx_poll_timer *timer = (struct tx_poll_timer *)data;
+	bool txdone, resched = false;
+	struct ipc_chan *chan;
+
+	list_for_each_entry(chan, &ipc_channels, node) {
+		if (chan->timer == timer
+				&& chan->active_token && chan->assigned) {
+			resched = true;
+			txdone = chan->link_ops->last_tx_done(chan->link);
+			if (txdone)
+				tx_tick(chan, XFER_OK);
+		}
+	}
+
+	if (resched)
+		mod_timer(&timer->poll,
+			jiffies + msecs_to_jiffies(timer->period));
+}
+
+/*
+ * After 'startup' and before 'shutdown', the IPC controller driver
+ * notifies the API of data received over the link.
+ * The controller driver should make sure the 'RTR' is de-asserted since
+ * reception of the packet and until after this call returns.
+ * This call could be made from atomic context.
+ */
+void ipc_link_received_data(struct ipc_link *link, void *data)
+{
+	struct ipc_chan *chan = (struct ipc_chan *)link->api_priv;
+
+	/* No buffering the received data */
+	if (chan->rxcb)
+		chan->rxcb(data);
+}
+EXPORT_SYMBOL(ipc_link_received_data);
+
+/*
+ * The IPC controller driver notifies the API that the remote has
+ * asserted RTR and it could now send another message on the link.
+ */
+void ipc_link_txdone(struct ipc_link *link, enum xfer_result r)
+{
+	struct ipc_chan *chan = (struct ipc_chan *)link->api_priv;
+
+	if (unlikely(!(chan->txdone_method & TXDONE_BY_IRQ))) {
+		pr_err("Controller can't run the TX ticker\n");
+		return;
+	}
+
+	tx_tick(chan, r);
+}
+EXPORT_SYMBOL(ipc_link_txdone);
+
+/*
+ * The client/protocol had received some 'ACK' packet and it notifies
+ * the API that the last packet was sent successfully. This only works
+ * if the controller doesn't get IRQ for TX done.
+ */
+void ipc_client_txdone(void *channel, enum xfer_result r)
+{
+	struct ipc_chan *chan = (struct ipc_chan *)channel;
+	bool txdone = true;
+
+	if (unlikely(!(chan->txdone_method & TXDONE_BY_ACK))) {
+		pr_err("Client can't run the TX ticker\n");
+		return;
+	}
+
+	if (chan->txdone_method & TXDONE_BY_POLL)
+		txdone = chan->link_ops->last_tx_done(chan->link);
+
+	if (txdone)
+		tx_tick(chan, r);
+}
+EXPORT_SYMBOL(ipc_client_txdone);
+
+/*
+ * Called by a client to "put data on the h/w channel" so that if
+ * everything else is fine we don't need to do anything more locally
+ * for the remote to receive the data intact.
+ * In reality, the remote may receive it intact, corrupted or not at all.
+ * This could be called from atomic context as it simply
+ * queues the data and returns a token (request_token_t)
+ * against the request.
+ * The client is later notified of successful transmission of
+ * data over the channel via the 'txcb'. The client could in
+ * turn queue more messages from txcb.
+ */
+request_token_t ipc_send_message(void *channel, void *data)
+{
+	struct ipc_chan *chan = (struct ipc_chan *)channel;
+	request_token_t t;
+
+	if (!chan || !chan->assigned)
+		return 0;
+
+	t = _add_to_rbuf(chan, data);
+	if (!t)
+		pr_err("Try increasing MBOX_TX_QUEUE_LEN\n");
+
+	_msg_submit(chan);
+
+	if (chan->txdone_method	== TXDONE_BY_POLL)
+		poll_txdone((unsigned long)chan->timer);
+
+	if (chan->tx_block && chan->active_token) {
+		int ret;
+		init_completion(&chan->tx_complete);
+		ret = wait_for_completion_timeout(&chan->tx_complete,
+			chan->tx_tout);
+		if (ret == 0) {
+			t = 0;
+			tx_tick(chan, XFER_ERR);
+		}
+	}
+
+	return t;
+}
+EXPORT_SYMBOL(ipc_send_message);
+
+/*
+ * A client driver asks for exclusive use of a channel/mailbox.
+ * If assigned, the channel has to be 'freed' before it could
+ * be assigned to some other client.
+ * After assignment, any packet received on this channel will be
+ * handed over to the client via the 'rxcb' callback.
+ * The 'txcb' callback is used to notify client upon sending the
+ * packet over the channel, which may or may not have been yet
+ * read by the remote processor.
+ */
+void *ipc_request_channel(struct ipc_client *cl)
+{
+	struct ipc_chan *chan;
+	unsigned long flags;
+	int ret = 0;
+
+	mutex_lock(&chpool_mutex);
+
+	list_for_each_entry(chan, &ipc_channels, node)
+		if (!chan->assigned
+				&& !strcmp(cl->chan_name, chan->chan_name)) {
+			spin_lock_irqsave(&chan->lock, flags);
+			chan->msg_free = 0;
+			chan->msg_count = 0;
+			chan->active_token = 0;
+			chan->rxcb = cl->rxcb;
+			chan->txcb = cl->txcb;
+			chan->assigned = true;
+			chan->tx_block = cl->tx_block;
+			if (!cl->tx_tout)
+				chan->tx_tout = ~0;
+			else
+				chan->tx_tout = msecs_to_jiffies(cl->tx_tout);
+			if (chan->txdone_method	== TXDONE_BY_POLL
+					&& cl->knows_txdone)
+				chan->txdone_method |= TXDONE_BY_ACK;
+			spin_unlock_irqrestore(&chan->lock, flags);
+			ret = 1;
+			break;
+		}
+
+	mutex_unlock(&chpool_mutex);
+
+	if (!ret) {
+		pr_err("Unable to assign mailbox(%s)\n", cl->chan_name);
+		return NULL;
+	}
+
+	ret = chan->link_ops->startup(chan->link, cl->cntlr_data);
+	if (ret) {
+		pr_err("Unable to startup the link\n");
+		ipc_free_channel((void *)chan);
+		return NULL;
+	}
+
+	return (void *)chan;
+}
+EXPORT_SYMBOL(ipc_request_channel);
+
+/* Drop any messages queued and release the channel */
+void ipc_free_channel(void *ch)
+{
+	struct ipc_chan *chan = (struct ipc_chan *)ch;
+	unsigned long flags;
+
+	if (!chan || !chan->assigned)
+		return;
+
+	chan->link_ops->shutdown(chan->link);
+
+	/* The queued TX requests are simply aborted, no callbacks are made */
+	spin_lock_irqsave(&chan->lock, flags);
+	chan->assigned = false;
+	chan->active_token = 0;
+	if (chan->txdone_method == (TXDONE_BY_POLL | TXDONE_BY_ACK))
+		chan->txdone_method = TXDONE_BY_POLL;
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	del_timer_sync(chan->timer);
+
+	blocking_notifier_call_chain(&chan->avail, 0, NULL);
+}
+EXPORT_SYMBOL(ipc_free_channel);
+
+static struct ipc_chan *name_to_chan(const char *name)
+{
+	struct ipc_chan *chan;
+	int ret = 0;
+
+	mutex_lock(&chpool_mutex);
+	list_for_each_entry(chan, &ipc_channels, node)
+		if (!strcmp(name, chan->chan_name)) {
+			ret = 1;
+			break;
+		}
+	mutex_unlock(&chpool_mutex);
+
+	if (!ret)
+		return NULL;
+
+	return chan;
+}
+
+int ipc_notify_chan_register(const char *name, struct notifier_block *nb)
+{
+	struct ipc_chan *chan = name_to_chan(name);
+
+	if (chan && nb)
+		return blocking_notifier_chain_register(&chan->avail, nb);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL(ipc_notify_chan_register);
+
+void ipc_notify_chan_unregister(const char *name, struct notifier_block *nb)
+{
+	struct ipc_chan *chan = name_to_chan(name);
+
+	if (chan && nb)
+		blocking_notifier_chain_unregister(&chan->avail, nb);
+}
+EXPORT_SYMBOL(ipc_notify_chan_unregister);
+
+/*
+ * Call for IPC controller drivers to register a controller, adding
+ * its channels/mailboxes to the global pool.
+ */
+int ipc_links_register(struct ipc_controller *ipc_con)
+{
+	struct tx_poll_timer *timer = NULL;
+	struct ipc_chan *channel;
+	int i, num_links, txdone;
+
+	/* Are you f***ing with us, sir? */
+	if (!ipc_con || !ipc_con->ops)
+		return -EINVAL;
+
+	for (i = 0; ipc_con->links[i]; i++)
+		;
+	if (!i)
+		return -EINVAL;
+	num_links = i;
+
+	if (ipc_con->txdone_irq)
+		txdone = TXDONE_BY_IRQ;
+	else if (ipc_con->txdone_poll)
+		txdone = TXDONE_BY_POLL;
+	else /* It has to be at least ACK */
+		txdone = TXDONE_BY_ACK;
+
+	if (txdone == TXDONE_BY_POLL) {
+		timer = kzalloc(sizeof(struct tx_poll_timer), GFP_KERNEL);
+		if (!timer)
+			return -ENOMEM;
+		timer->period = ipc_con->txpoll_period;
+		timer->poll.function = &poll_txdone;
+		timer->poll.data = (unsigned long)timer;
+		init_timer(&timer->poll);
+	}
+
+	channel = kzalloc(sizeof(struct ipc_chan) * num_links, GFP_KERNEL);
+	if (!channel) {
+		kfree(timer);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < num_links; i++) {
+		channel[i].timer = timer;
+		channel[i].assigned = false;
+		channel[i].txdone_method = txdone;
+		channel[i].link_ops = ipc_con->ops;
+		channel[i].link = ipc_con->links[i];
+		channel[i].link->api_priv = &channel[i];
+		snprintf(channel[i].chan_name, 32, "%s:%s",
+			ipc_con->controller_name,
+			ipc_con->links[i]->link_name);
+		spin_lock_init(&channel[i].lock);
+		BLOCKING_INIT_NOTIFIER_HEAD(&channel[i].avail);
+		mutex_lock(&chpool_mutex);
+		list_add_tail(&channel[i].node, &ipc_channels);
+		mutex_unlock(&chpool_mutex);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ipc_links_register);
+
+void ipc_links_unregister(struct ipc_controller *ipc_con)
+{
+	struct ipc_chan *chan, *t, *first = NULL;
+	struct tx_poll_timer *timer = NULL;
+	char *name;
+	int i;
+
+	mutex_lock(&chpool_mutex);
+	for (i = 0; ipc_con->links[i]; i++) {
+		snprintf(name, 32, "%s:%s",
+			ipc_con->controller_name,
+			ipc_con->links[i]->link_name);
+		list_for_each_entry_safe(chan, t, &ipc_channels, node) {
+			if (!strcmp(name, chan->chan_name)) {
+				if (!first)
+					first = chan;
+				if (!timer)
+					timer = chan->timer;
+				list_del(&chan->node);
+				ipc_free_channel((void *)chan);
+				break;
+			}
+		}
+	}
+	mutex_unlock(&chpool_mutex);
+
+	kfree(first);
+	kfree(timer);
+}
+EXPORT_SYMBOL(ipc_links_unregister);
diff --git a/include/linux/mailbox.h b/include/linux/mailbox.h
new file mode 100644
index 0000000..232e2c4
--- /dev/null
+++ b/include/linux/mailbox.h
@@ -0,0 +1,17 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MAILBOX_H
+#define __MAILBOX_H
+
+enum xfer_result {
+	XFER_OK = 0,
+	XFER_ERR,
+};
+
+typedef unsigned request_token_t;
+
+#endif /* __MAILBOX_H */
diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h
new file mode 100644
index 0000000..232fdc7
--- /dev/null
+++ b/include/linux/mailbox_client.h
@@ -0,0 +1,85 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MAILBOX_CLIENT_H
+#define __MAILBOX_CLIENT_H
+
+#include <linux/mailbox.h>
+
+/**
+ * struct ipc_client - User of a mailbox
+ * @chan_name: the "controller:channel" this client wants
+ * @rxcb: atomic callback to provide client the data received
+ * @txcb: atomic callback to tell client of data transmission
+ * @tx_block: if the ipc_send_message should block until data is transmitted
+ * @tx_tout: Max block period in ms before TX is assumed failure
+ * @knows_txdone: if the client could run the TX state machine. Usually if
+ *    the client receives some ACK packet for transmission. Unused if the
+ *    controller already has TX_Done/RTR IRQ.
+ * @cntlr_data: Optional controller specific parameters during channel request
+ */
+struct ipc_client {
+	char *chan_name;
+	void (*rxcb)(void *data);
+	void (*txcb)(request_token_t t, enum xfer_result r);
+	bool tx_block;
+	unsigned long tx_tout;
+	bool knows_txdone;
+	void *cntlr_data;
+};
+
+/**
+ * The Client specifies it requirements and capabilities while asking for
+ * a channel/mailbox by name. It can't be called from atomic context.
+ * The channel is exclusively allocated and can't be used by another
+ * client before the owner calls ipc_free_channel.
+ */
+void *ipc_request_channel(struct ipc_client *cl);
+
+/**
+ * For client to submit data to the controller destined for a remote
+ * processor. If the client had set 'tx_block', the call will return
+ * either when the remote receives the data or when 'tx_tout' millisecs
+ * run out.
+ *  In non-blocking mode, the requests are buffered by the API and a
+ * non-zero token is returned for each queued request. If the queue
+ * was full the returned token will be 0. Upon failure or successful
+ * TX, the API calls 'txcb' from atomic context, from which the client
+ * could submit yet another request.
+ *  In blocking mode, 'txcb' is not called, effectively making the
+ * queue length 1. The returned value is 0 if TX timed out, some
+ * non-zero value upon success.
+ */
+request_token_t ipc_send_message(void *channel, void *data);
+
+/**
+ * The way for a client to run the TX state machine. This works
+ * only if the client sets 'knows_txdone' and the IPC controller
+ * don't get an IRQ for TX_Done.
+ */
+void ipc_client_txdone(void *channel, enum xfer_result r);
+
+/**
+ * The client relinquishes control of a mailbox by this call,
+ * make it available to other clients.
+ * The ipc_request/free_channel are light weight calls, so the
+ * client should avoid holding it when it doesn't need to
+ * transfer data.
+ */
+void ipc_free_channel(void *ch);
+
+/**
+ * The client make ask the API to be notified when a particular channel
+ * becomes available to be acquired again.
+ */
+int ipc_notify_chan_register(const char *name, struct notifier_block *nb);
+
+/**
+ * The client is no more interested in acquiring the channel.
+ */
+void ipc_notify_chan_unregister(const char *name, struct notifier_block *nb);
+
+#endif /* __MAILBOX_CLIENT_H */
diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h
new file mode 100644
index 0000000..23b80e3
--- /dev/null
+++ b/include/linux/mailbox_controller.h
@@ -0,0 +1,102 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MAILBOX_CONTROLLER_H
+#define __MAILBOX_CONTROLLER_H
+
+#include <linux/mailbox.h>
+
+/**
+ * struct ipc_link - s/w representation of a communication link
+ * @link_name: Literal name assigned to the link. Physically
+ *    identical channels may have the same name.
+ * @api_priv: hook for the API to map its private data on the link
+ *    Controller driver must not touch it.
+ */
+struct ipc_link {
+	char link_name[16];
+	void *api_priv;
+};
+
+/**
+ * struct ipc_link - s/w representation of a communication link
+ * @send_data: The API asks the IPC controller driver, in atomic
+ *    context try to transmit a message on the bus. Returns 0 if
+ *    data is accepted for transmission, -EBUSY while rejecting
+ *    if the remote hasn't yet read the last data sent. Actual
+ *    transmission of data is reported by the controller via
+ *    ipc_link_txdone (if it has some TX ACK irq). It must not
+ *    block.
+ * @startup: Called when a client requests the link. The controller
+ *    could ask clients for additional parameters of communication
+ *    to be provided via client's cntlr_data. This call may block.
+ *    After this call the Controller must forward any data received
+ *    on the link by calling ipc_link_received_data (which won't block)
+ * @shutdown: Called when a client relinquishes control of a link.
+ *    This call may block too. The controller must not forwared
+ *    any received data anymore.
+ * @last_tx_done: If the controller sets 'txdone_poll', the API calls
+ *    this to poll status of last TX. The controller must give priority
+ *    to IRQ method over polling and never set both txdone_poll and
+ *    txdone_irq. Only in polling mode 'send_data' is expected to
+ *    return -EBUSY. Used only if txdone_poll:=true && txdone_irq:=false
+ */
+struct ipc_link_ops {
+	int (*send_data)(struct ipc_link *link, void *data);
+	int (*startup)(struct ipc_link *link, void *params);
+	void (*shutdown)(struct ipc_link *link);
+	bool (*last_tx_done)(struct ipc_link *link);
+};
+
+/**
+ * struct ipc_controller - Controller of a class of communication links
+ * @controller_name: Literal name of the controller.
+ * @ops: Operators that work on each communication link
+ * @links: Null terminated array of links.
+ * @txdone_irq: Indicates if the controller can report to API when the
+ *    last transmitted data was read by the remote. Eg, if it has some
+ *    TX ACK irq.
+ * @txdone_poll: If the controller can read but not report the TX done.
+ *    Eg, is some register shows the TX status but no interrupt rises.
+ *    Ignored if 'txdone_irq' is set.
+ * @txpoll_period: If 'txdone_poll' is in effect, the API polls for
+ *    last TX's status after these many millisecs
+ */
+struct ipc_controller {
+	char controller_name[16];
+	struct ipc_link_ops *ops;
+	struct ipc_link **links;
+	bool txdone_irq;
+	bool txdone_poll;
+	unsigned txpoll_period;
+};
+
+/**
+ * The controller driver registers its communication links to the
+ * global pool managed by the API.
+ */
+int ipc_links_register(struct ipc_controller *ipc_con);
+
+/**
+ * After startup and before shutdown any data received on the link
+ * is pused to the API via atomic ipc_link_received_data() API.
+ * The controller should ACK the RX only after this call returns.
+ */
+void ipc_link_received_data(struct ipc_link *link, void *data);
+
+/**
+ * The controller the has IRQ for TX ACK calls this atomic API
+ * to tick the TX state machine. It works only if txdone_irq
+ * is set by the controller.
+ */
+void ipc_link_txdone(struct ipc_link *link, enum xfer_result r);
+
+/**
+ * Purge the links from the global pool maintained by the API.
+ */
+void ipc_links_unregister(struct ipc_controller *ipc_con);
+
+#endif /* __MAILBOX_CONTROLLER_H */
-- 
1.7.10.4



From jassisinghbrar at gmail.com  Mon May  6 03:24:23 2013
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon,  6 May 2013 12:54:23 +0530
Subject: [PATCHv2 3/4] mailbox: pl320: Introduce common API driver
In-Reply-To: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <1367825063-6263-1-git-send-email-jaswinder.singh@linaro.org>

Convert the PL320 controller driver to work with the common
mailbox API. Also convert the only user of PL320, highbank-cpufreq.c
to work with thee API. Drop the obsoleted driver pl320-ipc.c

Signed-off-by: Jassi Brar <jaswinder.singh at linaro.org>
---
 drivers/cpufreq/highbank-cpufreq.c |   22 +++-
 drivers/mailbox/Makefile           |    2 +-
 drivers/mailbox/pl320-ipc.c        |  198 ---------------------------------
 drivers/mailbox/pl320.c            |  212 ++++++++++++++++++++++++++++++++++++
 include/linux/pl320-ipc.h          |   17 ---
 5 files changed, 233 insertions(+), 218 deletions(-)
 delete mode 100644 drivers/mailbox/pl320-ipc.c
 create mode 100644 drivers/mailbox/pl320.c
 delete mode 100644 include/linux/pl320-ipc.h

diff --git a/drivers/cpufreq/highbank-cpufreq.c b/drivers/cpufreq/highbank-cpufreq.c
index 3118b87..5c057e0 100644
--- a/drivers/cpufreq/highbank-cpufreq.c
+++ b/drivers/cpufreq/highbank-cpufreq.c
@@ -19,7 +19,7 @@
 #include <linux/cpu.h>
 #include <linux/err.h>
 #include <linux/of.h>
-#include <linux/pl320-ipc.h>
+#include <linux/mailbox_client.h>
 #include <linux/platform_device.h>
 
 #define HB_CPUFREQ_CHANGE_NOTE	0x80000001
@@ -29,8 +29,26 @@
 static int hb_voltage_change(unsigned int freq)
 {
 	u32 msg[HB_CPUFREQ_IPC_LEN] = {HB_CPUFREQ_CHANGE_NOTE, freq / 1000000};
+	struct ipc_client cl;
+	int ret = -ETIMEDOUT;
+	void *chan;
 
-	return pl320_ipc_transmit(msg);
+	cl.rxcb = NULL;
+	cl.txcb = NULL;
+	cl.tx_block = true;
+	cl.tx_tout = 1000; /* 1 sec */
+	cl.cntlr_data = NULL;
+	cl.knows_txdone = false;
+	cl.chan_name = "pl320:A9_to_M3";
+
+	chan = ipc_request_channel(&cl);
+
+	if (ipc_send_message(chan, (void *)msg))
+		ret = msg[1]; /* PL320 updates buffer with FIFO after ACK */
+
+	ipc_free_channel(chan);
+
+	return ret;
 }
 
 static int hb_cpufreq_clk_notify(struct notifier_block *nb,
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index fefef7e..7b897f3 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -2,4 +2,4 @@
 
 obj-$(CONFIG_MAILBOX)		+= mailbox.o
 
-obj-$(CONFIG_PL320_MBOX)	+= pl320-ipc.o
+obj-$(CONFIG_PL320_MBOX)	+= pl320.o
diff --git a/drivers/mailbox/pl320-ipc.c b/drivers/mailbox/pl320-ipc.c
deleted file mode 100644
index f3755e0..0000000
--- a/drivers/mailbox/pl320-ipc.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright 2012 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/types.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/completion.h>
-#include <linux/mutex.h>
-#include <linux/notifier.h>
-#include <linux/spinlock.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-
-#include <linux/pl320-ipc.h>
-
-#define IPCMxSOURCE(m)		((m) * 0x40)
-#define IPCMxDSET(m)		(((m) * 0x40) + 0x004)
-#define IPCMxDCLEAR(m)		(((m) * 0x40) + 0x008)
-#define IPCMxDSTATUS(m)		(((m) * 0x40) + 0x00C)
-#define IPCMxMODE(m)		(((m) * 0x40) + 0x010)
-#define IPCMxMSET(m)		(((m) * 0x40) + 0x014)
-#define IPCMxMCLEAR(m)		(((m) * 0x40) + 0x018)
-#define IPCMxMSTATUS(m)		(((m) * 0x40) + 0x01C)
-#define IPCMxSEND(m)		(((m) * 0x40) + 0x020)
-#define IPCMxDR(m, dr)		(((m) * 0x40) + ((dr) * 4) + 0x024)
-
-#define IPCMMIS(irq)		(((irq) * 8) + 0x800)
-#define IPCMRIS(irq)		(((irq) * 8) + 0x804)
-
-#define MBOX_MASK(n)		(1 << (n))
-#define IPC_TX_MBOX		1
-#define IPC_RX_MBOX		2
-
-#define CHAN_MASK(n)		(1 << (n))
-#define A9_SOURCE		1
-#define M3_SOURCE		0
-
-static void __iomem *ipc_base;
-static int ipc_irq;
-static DEFINE_MUTEX(ipc_m1_lock);
-static DECLARE_COMPLETION(ipc_completion);
-static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
-
-static inline void set_destination(int source, int mbox)
-{
-	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
-	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
-}
-
-static inline void clear_destination(int source, int mbox)
-{
-	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
-	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
-}
-
-static void __ipc_send(int mbox, u32 *data)
-{
-	int i;
-	for (i = 0; i < 7; i++)
-		__raw_writel(data[i], ipc_base + IPCMxDR(mbox, i));
-	__raw_writel(0x1, ipc_base + IPCMxSEND(mbox));
-}
-
-static u32 __ipc_rcv(int mbox, u32 *data)
-{
-	int i;
-	for (i = 0; i < 7; i++)
-		data[i] = __raw_readl(ipc_base + IPCMxDR(mbox, i));
-	return data[1];
-}
-
-/* blocking implmentation from the A9 side, not usuable in interrupts! */
-int pl320_ipc_transmit(u32 *data)
-{
-	int ret;
-
-	mutex_lock(&ipc_m1_lock);
-
-	init_completion(&ipc_completion);
-	__ipc_send(IPC_TX_MBOX, data);
-	ret = wait_for_completion_timeout(&ipc_completion,
-					  msecs_to_jiffies(1000));
-	if (ret == 0) {
-		ret = -ETIMEDOUT;
-		goto out;
-	}
-
-	ret = __ipc_rcv(IPC_TX_MBOX, data);
-out:
-	mutex_unlock(&ipc_m1_lock);
-	return ret;
-}
-EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
-
-static irqreturn_t ipc_handler(int irq, void *dev)
-{
-	u32 irq_stat;
-	u32 data[7];
-
-	irq_stat = __raw_readl(ipc_base + IPCMMIS(1));
-	if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
-		__raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
-		complete(&ipc_completion);
-	}
-	if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
-		__ipc_rcv(IPC_RX_MBOX, data);
-		atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
-		__raw_writel(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
-	}
-
-	return IRQ_HANDLED;
-}
-
-int pl320_ipc_register_notifier(struct notifier_block *nb)
-{
-	return atomic_notifier_chain_register(&ipc_notifier, nb);
-}
-EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
-
-int pl320_ipc_unregister_notifier(struct notifier_block *nb)
-{
-	return atomic_notifier_chain_unregister(&ipc_notifier, nb);
-}
-EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
-
-static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
-{
-	int ret;
-
-	ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
-	if (ipc_base == NULL)
-		return -ENOMEM;
-
-	__raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
-
-	ipc_irq = adev->irq[0];
-	ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
-	if (ret < 0)
-		goto err;
-
-	/* Init slow mailbox */
-	__raw_writel(CHAN_MASK(A9_SOURCE),
-			ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
-	__raw_writel(CHAN_MASK(M3_SOURCE),
-			ipc_base + IPCMxDSET(IPC_TX_MBOX));
-	__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
-		     ipc_base + IPCMxMSET(IPC_TX_MBOX));
-
-	/* Init receive mailbox */
-	__raw_writel(CHAN_MASK(M3_SOURCE),
-			ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
-	__raw_writel(CHAN_MASK(A9_SOURCE),
-			ipc_base + IPCMxDSET(IPC_RX_MBOX));
-	__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
-		     ipc_base + IPCMxMSET(IPC_RX_MBOX));
-
-	return 0;
-err:
-	iounmap(ipc_base);
-	return ret;
-}
-
-static struct amba_id pl320_ids[] = {
-	{
-		.id	= 0x00041320,
-		.mask	= 0x000fffff,
-	},
-	{ 0, 0 },
-};
-
-static struct amba_driver pl320_driver = {
-	.drv = {
-		.name	= "pl320",
-	},
-	.id_table	= pl320_ids,
-	.probe		= pl320_probe,
-};
-
-static int __init ipc_init(void)
-{
-	return amba_driver_register(&pl320_driver);
-}
-module_init(ipc_init);
diff --git a/drivers/mailbox/pl320.c b/drivers/mailbox/pl320.c
new file mode 100644
index 0000000..7ddae5c
--- /dev/null
+++ b/drivers/mailbox/pl320.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/notifier.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/mailbox_controller.h>
+
+#define IPCMSOURCE(m)		((m) * 0x40)
+#define IPCMDSET(m)		(((m) * 0x40) + 0x004)
+#define IPCMDCLEAR(m)		(((m) * 0x40) + 0x008)
+#define IPCMDSTATUS(m)		(((m) * 0x40) + 0x00C)
+#define IPCMMODE(m)		(((m) * 0x40) + 0x010)
+#define IPCMMSET(m)		(((m) * 0x40) + 0x014)
+#define IPCMMCLEAR(m)		(((m) * 0x40) + 0x018)
+#define IPCMMSTATUS(m)		(((m) * 0x40) + 0x01C)
+#define IPCMSEND(m)		(((m) * 0x40) + 0x020)
+#define IPCMDR(m, dr)		(((m) * 0x40) + ((dr) * 4) + 0x024)
+
+#define IPCMMIS(irq)		(((irq) * 8) + 0x800)
+#define IPCMRIS(irq)		(((irq) * 8) + 0x804)
+
+#define MBOX_MASK(n)		(1 << (n))
+#define IPC_TX_MBOX		1
+
+#define CHAN_MASK(n)		(1 << (n))
+#define A9_SOURCE		1
+#define M3_SOURCE		0
+
+struct pl320_con {
+	u32 *data;
+	int ipc_irq;
+	struct device *dev;
+	struct ipc_link link;
+	void __iomem *ipc_base;
+	struct ipc_controller ipc_con;
+};
+
+static inline struct pl320_con *to_pl320(struct ipc_link *l)
+{
+	if (!l)
+		return NULL;
+
+	return container_of(l, struct pl320_con, link);
+}
+
+static irqreturn_t ipc_handler(int irq, void *p)
+{
+	struct ipc_link *link = (struct ipc_link *)p;
+	struct pl320_con *pl320 = to_pl320(link);
+	void __iomem *ipc_base = pl320->ipc_base;
+	u32 irq_stat;
+
+	irq_stat = __raw_readl(ipc_base + IPCMMIS(1));
+	if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
+		u32 *data = pl320->data;
+		int i;
+
+		__raw_writel(0, ipc_base + IPCMSEND(IPC_TX_MBOX));
+
+		/*
+		 * The PL320 driver specifies that the send buffer
+		 * will be overwritten by same fifo upon TX ACK.
+		 */
+		for (i = 0; i < 7; i++)
+			data[i] = __raw_readl(ipc_base
+					 + IPCMDR(IPC_TX_MBOX, i));
+
+		ipc_link_txdone(link, XFER_OK);
+
+		pl320->data = NULL;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int pl320_send_data(struct ipc_link *link, void *msg)
+{
+	struct pl320_con *pl320 = to_pl320(link);
+	void __iomem *ipc_base = pl320->ipc_base;
+	u32 *data = (u32 *)msg;
+	int i;
+
+	pl320->data = data;
+
+	for (i = 0; i < 7; i++)
+		__raw_writel(data[i], ipc_base + IPCMDR(IPC_TX_MBOX, i));
+
+	__raw_writel(0x1, ipc_base + IPCMSEND(IPC_TX_MBOX));
+
+	return 0;
+}
+
+static int pl320_startup(struct ipc_link *link, void *ignored)
+{
+	struct pl320_con *pl320 = to_pl320(link);
+	void __iomem *ipc_base = pl320->ipc_base;
+	int err, ipc_irq = pl320->ipc_irq;
+
+	__raw_writel(0, ipc_base + IPCMSEND(IPC_TX_MBOX));
+
+	err = request_irq(ipc_irq, ipc_handler, 0, dev_name(pl320->dev), link);
+	if (err)
+		return err;
+
+	/* Init slow mailbox */
+	__raw_writel(CHAN_MASK(A9_SOURCE),
+			ipc_base + IPCMSOURCE(IPC_TX_MBOX));
+	__raw_writel(CHAN_MASK(M3_SOURCE),
+			ipc_base + IPCMDSET(IPC_TX_MBOX));
+	__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
+		     ipc_base + IPCMMSET(IPC_TX_MBOX));
+
+	pl320->data = NULL;
+	return 0;
+}
+
+static void pl320_shutdown(struct ipc_link *link)
+{
+	struct pl320_con *pl320 = to_pl320(link);
+
+	pl320->data = NULL;
+	free_irq(pl320->ipc_irq, link);
+}
+
+static struct ipc_link_ops pl320_ops = {
+	.send_data = pl320_send_data,
+	.startup = pl320_startup,
+	.shutdown = pl320_shutdown,
+};
+
+static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
+{
+	struct pl320_con *pl320;
+	struct ipc_link *l[2];
+	int ret;
+
+	pl320 = kzalloc(sizeof(struct pl320_con), GFP_KERNEL);
+	if (!pl320)
+		return -ENOMEM;
+
+	pl320->ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
+	if (pl320->ipc_base == NULL) {
+		kfree(pl320);
+		return -ENOMEM;
+	}
+
+	pl320->dev = &adev->dev;
+	pl320->ipc_irq = adev->irq[0];
+	amba_set_drvdata(adev, pl320);
+
+	l[0] = &pl320->link;
+	l[1] = NULL;
+	pl320->ipc_con.links = l;
+	pl320->ipc_con.txdone_irq = true;
+	pl320->ipc_con.ops = &pl320_ops;
+	snprintf(pl320->link.link_name, 16, "A9_to_M3");
+	snprintf(pl320->ipc_con.controller_name, 16, "pl320");
+
+	ret = ipc_links_register(&pl320->ipc_con);
+	if (ret) {
+		iounmap(pl320->ipc_base);
+		kfree(pl320);
+	}
+
+	return ret;
+}
+
+static struct amba_id pl320_ids[] = {
+	{
+		.id	= 0x00041320,
+		.mask	= 0x000fffff,
+	},
+	{ 0, 0 },
+};
+
+static struct amba_driver pl320_driver = {
+	.drv = {
+		.name	= "pl320",
+	},
+	.id_table	= pl320_ids,
+	.probe		= pl320_probe,
+};
+
+static int __init ipc_init(void)
+{
+	return amba_driver_register(&pl320_driver);
+}
+module_init(ipc_init);
diff --git a/include/linux/pl320-ipc.h b/include/linux/pl320-ipc.h
deleted file mode 100644
index 5161f63..0000000
--- a/include/linux/pl320-ipc.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-int pl320_ipc_transmit(u32 *data);
-int pl320_ipc_register_notifier(struct notifier_block *nb);
-int pl320_ipc_unregister_notifier(struct notifier_block *nb);
-- 
1.7.10.4



From jassisinghbrar at gmail.com  Mon May  6 03:24:40 2013
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon,  6 May 2013 12:54:40 +0530
Subject: [PATCHv2 4/4] mailbox: omap2: Introduce common API driver
In-Reply-To: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <1367825080-6297-1-git-send-email-jaswinder.singh@linaro.org>

A new driver conforming to the common API.

Signed-off-by: Jassi Brar <jaswinder.singh at linaro.org>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   12 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   11 +
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   11 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   13 +
 drivers/mailbox/Kconfig                    |    9 +
 drivers/mailbox/Makefile                   |    1 +
 drivers/mailbox/omap2.c                    |  420 ++++++++++++++++++++++++++++
 include/linux/platform_data/mailbox-omap.h |   64 +++++
 8 files changed, 541 insertions(+)
 create mode 100644 drivers/mailbox/omap2.c
 create mode 100644 include/linux/platform_data/mailbox-omap.h

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 5137cc8..dbcb928 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,6 +16,7 @@
 #include <linux/i2c-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -166,6 +167,16 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 };
 
 /* mailbox */
+static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
+	{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
+	{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
+};
+
+static struct omap_mbox_pdata omap2420_mailbox_attrs = {
+	.info_cnt	= ARRAY_SIZE(omap2420_mailbox_info),
+	.info		= omap2420_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
 	{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
 	{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
@@ -186,6 +197,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 		},
 	},
+	.dev_attr	= &omap2420_mailbox_attrs,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4ce999e..df2f874 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,6 +17,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -170,6 +171,15 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 };
 
 /* mailbox */
+static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
+	{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
+};
+
+static struct omap_mbox_pdata omap2430_mailbox_attrs = {
+	.info_cnt	= ARRAY_SIZE(omap2430_mailbox_info),
+	.info		= omap2430_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
 	{ .irq = 26 + OMAP_INTC_START, },
 	{ .irq = -1 },
@@ -189,6 +199,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 		},
 	},
+	.dev_attr	= &omap2430_mailbox_attrs,
 };
 
 /* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 4083606..3833e96 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,6 +25,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/iommu-omap.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "am35xx.h"
@@ -1501,6 +1502,15 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
 	.sysc = &omap3xxx_mailbox_sysc,
 };
 
+static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
+	{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
+};
+
+static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
+	.info_cnt	= ARRAY_SIZE(omap3xxx_mailbox_info),
+	.info		= omap3xxx_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
 	{ .irq = 26 + OMAP_INTC_START, },
 	{ .irq = -1 },
@@ -1520,6 +1530,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
 			.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
 		},
 	},
+	.dev_attr	= &omap3xxx_mailbox_attrs,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index eaba9dc..44d99b6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -29,6 +29,7 @@
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/iommu-omap.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -1861,6 +1862,17 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 };
 
 /* mailbox */
+static struct omap_mbox_dev_info omap44xx_mailbox_info[] = {
+	{ .name = "mbox-ipu", .tx_id = 0, .rx_id = 1 },
+	{ .name = "mbox-dsp", .tx_id = 3, .rx_id = 2 },
+};
+
+static struct omap_mbox_pdata omap44xx_mailbox_attrs = {
+	.intr_type	= MBOX_INTR_CFG_TYPE2,
+	.info_cnt	= ARRAY_SIZE(omap44xx_mailbox_info),
+	.info		= omap44xx_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
 	{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
 	{ .irq = -1 }
@@ -1877,6 +1889,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
 			.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
 		},
 	},
+	.dev_attr	= &omap44xx_mailbox_attrs,
 };
 
 /*
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 9545c9f..897b1c7 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -16,4 +16,13 @@ config PL320_MBOX
 	  Management Engine, primarily for cpufreq. Say Y here if you want
 	  to use the PL320 IPCM support.
 
+config OMAP2PLUS_MBOX
+	tristate "OMAP2+ Mailbox framework support"
+	depends on ARCH_OMAP2PLUS
+	help
+	  Mailbox implementation for OMAP family chips with hardware for
+	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
+	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4. Say Y here if you want
+	  to use OMAP2+ Mailbox framework support.
+
 endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 7b897f3..b1c9b14 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -3,3 +3,4 @@
 obj-$(CONFIG_MAILBOX)		+= mailbox.o
 
 obj-$(CONFIG_PL320_MBOX)	+= pl320.o
+obj-$(CONFIG_OMAP2PLUS_MBOX)	+= omap2.o
diff --git a/drivers/mailbox/omap2.c b/drivers/mailbox/omap2.c
new file mode 100644
index 0000000..c22a82a
--- /dev/null
+++ b/drivers/mailbox/omap2.c
@@ -0,0 +1,420 @@
+/*
+ * Mailbox driver for OMAP4
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/mailbox-omap.h>
+
+#define MAILBOX_REVISION		0x000
+#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
+#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
+#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
+#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
+#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
+
+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
+
+#define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
+#define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
+
+#define RX_IRQ	0
+#define TX_IRQ	1
+
+/* We assume peak RX activity won't be more than 32 packets together */
+#define RXBUF_LEN	32
+
+/*
+ * Logical link is a pair of independent physical TX+RX mailboxes.
+ * IDEALLY, a client should acquire RX and TX separately as 2 links, so
+ * that (for example) when it can't take in anymore packets it could
+ * release the RX link and re-acquire only when it has appetite once again.
+ */
+struct omap2_mbox_link {
+	int irq;
+	bool active;
+	unsigned usr_id;
+	unsigned mb_rx, mb_tx;
+	u32 rxbuf[RXBUF_LEN];
+	struct ipc_link link;
+	struct omap2_mbox_con *omc;
+};
+
+struct omap2_mbox_con {
+	struct device *dev;
+	unsigned intr_type;
+	void __iomem *mbox_base;
+	struct omap2_mbox_link oml[4];
+	struct ipc_controller ipc_con;
+	struct mutex lock;
+};
+
+static inline struct omap2_mbox_link *to_oml(struct ipc_link *l)
+{
+	if (!l)
+		return NULL;
+
+	return container_of(l, struct omap2_mbox_link, link);
+}
+
+static inline void omap_mb_write(struct omap2_mbox_con *omc, u32 val, u32 off)
+{
+	__raw_writel(val, omc->mbox_base + off);
+}
+
+static inline u32 omap_mb_read(struct omap2_mbox_con *omc, u32 off)
+{
+	return __raw_readl(omc->mbox_base + off);
+}
+
+static void omc_enable_irq(struct omap2_mbox_link *oml, int tx)
+{
+	struct omap2_mbox_con *omc = oml->omc;
+	u32 val, off;
+
+	if (omc->intr_type)
+		off = OMAP4_MAILBOX_IRQENABLE(oml->usr_id);
+	else
+		off = MAILBOX_IRQENABLE(oml->usr_id);
+
+	val = omap_mb_read(omc, off);
+	if (tx)
+		val |= MAILBOX_IRQ_NOTFULL(oml->mb_tx);
+	else
+		val |= MAILBOX_IRQ_NEWMSG(oml->mb_rx);
+
+	omap_mb_write(omc, val, off);
+}
+
+static void omc_disable_irq(struct omap2_mbox_link *oml, int tx)
+{
+	struct omap2_mbox_con *omc = oml->omc;
+	u32 val, off;
+
+	if (tx)
+		val = MAILBOX_IRQ_NOTFULL(oml->mb_tx);
+	else
+		val = MAILBOX_IRQ_NEWMSG(oml->mb_rx);
+
+	if (omc->intr_type) {
+		off = OMAP4_MAILBOX_IRQENABLE_CLR(oml->usr_id);
+	} else {
+		off = MAILBOX_IRQENABLE(oml->usr_id);
+		val = omap_mb_read(omc, off) & ~val;
+	}
+
+	omap_mb_write(omc, val, off);
+}
+
+static void omc_ack_irq(struct omap2_mbox_link *oml, int tx)
+{
+	struct omap2_mbox_con *omc = oml->omc;
+	u32 val, off;
+
+	if (tx)
+		val = MAILBOX_IRQ_NOTFULL(oml->mb_tx);
+	else
+		val = MAILBOX_IRQ_NEWMSG(oml->mb_rx);
+
+	if (omc->intr_type)
+		off = OMAP4_MAILBOX_IRQSTATUS(oml->usr_id);
+	else
+		off = MAILBOX_IRQSTATUS(oml->usr_id);
+
+	omap_mb_write(omc, val, off);
+	/* Flush posted write for irq status to avoid spurious interrupts */
+	omap_mb_read(omc, off);
+}
+
+static int omc_is_irq(struct omap2_mbox_link *oml, int tx)
+{
+	struct omap2_mbox_con *omc = oml->omc;
+	u32 val, off;
+
+	if (tx)
+		val = MAILBOX_IRQ_NOTFULL(oml->mb_tx);
+	else
+		val = MAILBOX_IRQ_NEWMSG(oml->mb_rx);
+
+	if (omc->intr_type)
+		off = OMAP4_MAILBOX_IRQSTATUS(oml->usr_id);
+	else
+		off = MAILBOX_IRQSTATUS(oml->usr_id);
+
+	return omap_mb_read(omc, off) & val;
+}
+
+static void omc_tx_irq(struct omap2_mbox_link *oml)
+{
+	omc_disable_irq(oml, TX_IRQ);
+	ipc_link_txdone(&oml->link, XFER_OK);
+}
+
+static void omc_rx_irq(struct omap2_mbox_link *oml)
+{
+	struct omap2_mbox_con *omc = oml->omc;
+	int i, j, count = omap_mb_read(omc, MAILBOX_MSGSTATUS(oml->mb_rx));
+	struct omap2_mbox_rxdata pkt;
+
+	j = 0;
+	while (count && j < RXBUF_LEN) {
+
+		for (i = 0; i < count; i++)
+			oml->rxbuf[j++] = omap_mb_read(omc,
+						MAILBOX_MESSAGE(oml->mb_rx));
+
+		count = omap_mb_read(omc, MAILBOX_MSGSTATUS(oml->mb_rx));
+	}
+	pkt.len = j;
+	pkt.buf = oml->rxbuf;
+	ipc_link_received_data(&oml->link, (void *)&pkt)
+}
+
+static irqreturn_t ipc_handler(int irq, void *p)
+{
+	struct omap2_mbox_link *oml = p;
+	struct omap2_mbox_con *omc = oml->omc;
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		struct omap2_mbox_link *l = &omc->oml[i];
+
+		if (!l->active)
+			continue;
+
+		if (omc_is_irq(l, TX_IRQ)) {
+			omc_tx_irq(l);
+			omc_ack_irq(l, TX_IRQ);
+		}
+
+		if (omc_is_irq(l, RX_IRQ)) {
+			omc_rx_irq(l);
+			omc_ack_irq(l, RX_IRQ);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int mhu_send_data(struct ipc_link *link, void *data)
+{
+	struct omap2_mbox_link *oml = to_oml(link);
+	struct omap2_mbox_con *omc = oml->omc;
+
+	/* If FIFO is already full */
+	if (omap_mb_read(omc, MAILBOX_FIFOSTATUS(oml->mb_tx)) & 0x1) {
+		/* Enable IRQ and return busy */
+		omc_enable_irq(oml, TX_IRQ);
+		return -EBUSY;
+	}
+
+	omap_mb_write(omc, (u32)data, MAILBOX_MESSAGE(oml->mb_tx));
+	ipc_link_txdone(link, XFER_OK);
+
+	return 0;
+}
+
+static int mhu_startup(struct ipc_link *link, void *ignored)
+{
+	struct omap2_mbox_link *oml = to_oml(link);
+	struct omap2_mbox_con *omc = oml->omc;
+	int i, irq_taken, err = 0;
+
+	pm_runtime_enable(omc->dev);
+	pm_runtime_get_sync(omc->dev);
+
+	mutex_lock(&omc->lock);
+
+	irq_taken = 0;
+	for (i = 0; i < 4; i++) {
+		struct omap2_mbox_link *l = &omc->oml[i];
+		if (l->irq == oml->irq && l->active)
+			irq_taken = 1;
+	}
+	oml->active = true;
+	if (!irq_taken) {
+		err = request_irq(oml->irq, ipc_handler,
+			0, omc->oml[i].link.link_name, oml);
+		if (err)
+			oml->active = false;
+	}
+
+	mutex_unlock(&omc->lock);
+
+	if (err) {
+		pm_runtime_put_sync(omc->dev);
+		pm_runtime_disable(omc->dev);
+	} else {
+		omc_disable_irq(oml, TX_IRQ);
+		/* Start accepting messages */
+		omc_enable_irq(oml, RX_IRQ);
+	}
+
+	return err;
+}
+
+static void mhu_shutdown(struct ipc_link *link)
+{
+	struct omap2_mbox_link *oml = to_oml(link);
+	struct omap2_mbox_con *omc = oml->omc;
+	int irq_taken;
+
+	/* Stop accepting messages */
+	omc_disable_irq(oml, RX_IRQ);
+	/* Flush the TX FIFO */
+	omc_disable_irq(oml, TX_IRQ);
+	omap_mb_read(omc, MAILBOX_MESSAGE(oml->mb_tx));
+	omap_mb_read(omc, MAILBOX_MESSAGE(oml->mb_tx));
+	omap_mb_read(omc, MAILBOX_MESSAGE(oml->mb_tx));
+	omap_mb_read(omc, MAILBOX_MESSAGE(oml->mb_tx));
+
+	mutex_lock(&omc->lock);
+
+	irq_taken = 0;
+	oml->active = false;
+	for (i = 0; i < 4; i++) {
+		struct omap2_mbox_link *l = &omc->oml[i];
+		if (l->irq == oml->irq && l->active)
+			irq_taken = 1;
+	}
+	if (!irq_taken)
+		free_irq(oml->irq, omc);
+
+	mutex_unlock(&omc->lock);
+
+	pm_runtime_put_sync(omc->dev);
+	pm_runtime_disable(omc->dev);
+}
+
+static struct ipc_link_ops omap2_mbox_ops = {
+	.startup = omap2_mbox_startup,
+	.send_data = omap2_mbox_send_data,
+	.shutdown = omap2_mbox_shutdown,
+};
+
+static int omap2_mbox_probe(struct platform_device *pdev)
+{
+	struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
+	struct omap_mbox_dev_info *info;
+	struct omap2_mbox_con *omc;
+	void __iomem *base;
+	struct ipc_link *l[5];
+	struct resource *mem;
+	int i, ret;
+
+	if (!pdata || !pdata->info_cnt || !pdata->info) {
+		pr_err("%s: platform not supported\n", __func__);
+		return -ENODEV;
+	}
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		pr_err("%s: No mem resource\n", __func__);
+		return -ENOMEM;
+	}
+
+	base = ioremap(mem->start, resource_size(mem));
+	if (!base) {
+		pr_err("%s: Ioremap failed\n", __func__);
+		return -ENOMEM;
+	}
+
+	omc = kzalloc(sizeof(*omc), GFP_KERNEL);
+	if (!omc) {
+		pr_err("%s: Unable to alloc omap2_mbox_con\n", __func__);
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	info = pdata->info;
+	for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
+		omc->oml[i].irq = platform_get_irq(pdev, info->irq_id);
+		omc->oml[i].active = false;
+		omc->oml[i].usr_id = info->usr_id;
+		omc->oml[i].mb_rx = info->rx_id;
+		omc->oml[i].mb_tx = info->tx_id;
+		omc->oml[i].omc = omc;
+		snprintf(omc->oml[i].link.link_name, 16, "%s", info->name);
+		l[i] = &omc->oml[i].link;
+		omc->intr_type = pdata->intr_type;
+	}
+	l[i] = NULL;
+	omc->ipc_con.links = l;
+	omc->mbox_base = base;
+	omc->dev = &pdev->dev;
+	/*
+	 * OMAP has "TX-FIFO Not Full" IRQ, not the "TX-Done" IRQ
+	 * So we simply put data in FIFO and assume we are done.
+	 */
+	omc->ipc_con.txdone_irq = true;
+	omc->ipc_con.ops = &omap2_mbox_ops;
+	snprintf(ipcu->ipc_con.controller_name, 16, "omap2");
+	mutex_init(&omc->lock);
+
+	ret = ipc_links_register(&omc->ipc_con);
+	if (ret) {
+		pr_err("%s: IPC register failed\n", __func__);
+		ret = -EINVAL;
+		goto err_reg;
+	}
+
+	platform_set_drvdata(pdev, omc);
+
+	return ret;
+
+err_alloc:
+	iounmap(base);
+err_reg:
+	kfree(omc);
+	return ret;
+}
+
+static int omap2_mbox_remove(struct platform_device *pdev)
+{
+	struct omap2_mbox_con *omc = platform_set_drvdata(pdev);
+
+	ipc_links_unregister(&omc->ipc_con);
+	iounmap(omc->mbox_base);
+	kfree(omc);
+
+	return 0;
+}
+
+static struct platform_driver omap2_mbox_driver = {
+	.probe	= omap2_mbox_probe,
+	.remove	= omap2_mbox_remove,
+	.driver	= {
+		.name = "omap-mailbox",
+	},
+};
+
+static int __init omap2_mbox_init(void)
+{
+	return platform_driver_register(&omap2_mbox_driver);
+}
+module_init(omap2_mbox_init);
+
+static void __exit omap2_mbox_exit(void)
+{
+	platform_driver_unregister(&omap2_mbox_driver);
+}
+module_exit(omap2_mbox_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
+MODULE_AUTHOR("Jaswinder Singh <jaswinder.singh at linaro.org>");
+MODULE_AUTHOR("Suman Anna <s-anna at ti.com>");
+MODULE_ALIAS("platform:omap2-mailbox");
diff --git a/include/linux/platform_data/mailbox-omap.h b/include/linux/platform_data/mailbox-omap.h
new file mode 100644
index 0000000..b35eaee
--- /dev/null
+++ b/include/linux/platform_data/mailbox-omap.h
@@ -0,0 +1,64 @@
+/*
+ * mailbox-omap.h
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PLAT_MAILBOX_H
+#define _PLAT_MAILBOX_H
+
+/* Interrupt register configuration types */
+#define MBOX_INTR_CFG_TYPE1	(0)
+#define MBOX_INTR_CFG_TYPE2	(1)
+
+/**
+ * struct omap_mbox_dev_info - OMAP mailbox device attribute info
+ * @name:	name of the mailbox device
+ * @tx_id:	mailbox queue id used for transmitting messages
+ * @rx_id:	mailbox queue id on which messages are received
+ * @irq_id:	irq identifier number to use from the hwmod data
+ * @usr_id:	mailbox user id for identifying the interrupt into
+ *			the MPU interrupt controller.
+ */
+struct omap_mbox_dev_info {
+	const char *name;
+	u32 tx_id;
+	u32 rx_id;
+	u32 irq_id;
+	u32 usr_id;
+};
+
+/**
+ * struct omap_mbox_pdata - OMAP mailbox platform data
+ * @intr_type:	type of interrupt configuration registers used
+			while programming mailbox queue interrupts
+ * @info_cnt:	number of mailbox devices for the platform
+ * @info:	array of mailbox device attributes
+ */
+struct omap_mbox_pdata {
+	u32 intr_type;
+	u32 info_cnt;
+	struct omap_mbox_dev_info *info;
+};
+
+/**
+ * struct omap2_mbox_rxdata - RX Packet handed over to a client by controller.
+ *  For TX, clients simply provide a (void *)u32 packet at a time.
+ * @len: Number of words received
+ * @buf: Array of received words
+ */
+struct omap2_mbox_rxdata {
+	int len;
+	u32 *buf;
+};
+
+#endif /* _PLAT_MAILBOX_H */
-- 
1.7.10.4



From dan.carpenter at oracle.com  Mon May  6 03:43:23 2013
From: dan.carpenter at oracle.com (Dan Carpenter)
Date: Mon, 6 May 2013 10:43:23 +0300
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <20130506065138.GA31763@bnru10>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
 <20130503070713.GA27956@bnru09> <20130505141855.GB4686@mwanda>
 <20130506065138.GA31763@bnru10>
Message-ID: <20130506074323.GH4635@mwanda>

On Mon, May 06, 2013 at 12:21:39PM +0530, Srinidhi Kasagar wrote:
> > > > -	regulator_enable(rmi4_data->regulator);
> > > > +	retval = regulator_enable(rmi4_data->regulator);
> > > > +	if (retval < 0)
> > > > +		return retval;
> > > Does it make sense to add a dev_err?
> > > 
> > 
> > Is that a question?
> > 
> > regulator_enable() already prints some warnings.  Probably it's not
> > going to fail and adding code that is duplicative or will never be
> > run is pointless.
> 
> It has become a habit checking the return value and spit some errors.
> And BTW, there are many drivers which does this way..Anyway if your
> intention is to avoid them for the new drivers..I dont mind skipping
> this..

It's not like I'm trying to ban error messages.  There isn't any
official policy on error messages.

regards,
dan carpenter



From rusty at rustcorp.com.au  Mon May  6 01:11:46 2013
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Mon, 06 May 2013 14:41:46 +0930
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
Message-ID: <87ip2wr8tp.fsf@rustcorp.com.au>

Peter Maydell <peter.maydell at linaro.org> writes:
> On 1 May 2013 03:07, Rusty Russell <rusty at rustcorp.com.au> wrote:
>> An emergency output is a reasonable idea, and this is a reasonable
>> implementation.  The question is practical: will it be used?  Because we
>> don't implement reasonable ideas which aren't going to be used.
>
> If you think it fits reasonably into the virtio spec (ie doesn't
> implement things at the wrong level of the transport/backend
> abstraction) then we can implement it in QEMU, and I think it
> makes more sense to do this than to throw in a random extra
> serial port.
>
> To be actually useful we need to also specify something in
> the device tree to say "here is where you will find your
> emergency output and what it is".

Hmm, I'm not sure that's true.  It looks like it needs:

1) An enhancment to the vdev->set_config callback to pass through (at
   least) an offset, probably offset and length.

2) An emerg_write() function ptr which can be called at any time, set by
   virtio_console.c's class_init:

static void emerg_write(VirtIOSerialPort *port, char c)
{
    VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);

    if (vcon->chr)
        qemu_chr_fe_write(vcon->chr, &c, 1);
}

3) A routine to find an emerg-write-capable console in
   virtio_serial_bus.c (or just assume port 0?):

static VirtIOSerialPort *find_emerg_write_port(VirtIOSerial *vser)
{
    VirtIOSerialPort *port;

    QTAILQ_FOREACH(port, &vser->ports, next) {
        VirtIOSerialPortClass *vsc;
        vsc = VIRTIO_SERIAL_PORT_GET_CLASS(port);

        if (vsc->emerg_write) {
            return port;
        }
    }
    return NULL;
}

4) set_config in virtio_serial_bus.c to notice emergency writes:

    if (offset == offsetof(struct virtio_console_config, emerg_w) {
        VirtIOSerial *vser;
        vser = DO_UPCAST(VirtIOSerial, vdev, vdev);
        VirtIOSerialPort *port;

        port = find_emerg_write_port(vser);
        if (port) {
            vsc->emerg_write(port, config.emerg_w);
        }
    }

Amit might have more clue... Amit?

Thanks,
Rusty.

From: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Subject: virtio: console: Add early writeonly register to config space

This patch adds a emerg_wr register (writeonly) in config space of virtio console device which can be used for debugging.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 include/uapi/linux/virtio_console.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/uapi/linux/virtio_console.h b/include/uapi/linux/virtio_console.h
index ee13ab6..586678d 100644
--- a/include/uapi/linux/virtio_console.h
+++ b/include/uapi/linux/virtio_console.h
@@ -38,6 +38,7 @@
 /* Feature bits */
 #define VIRTIO_CONSOLE_F_SIZE	0	/* Does host provide console size? */
 #define VIRTIO_CONSOLE_F_MULTIPORT 1	/* Does host provide multiple ports? */
+#define VIRTIO_CONSOLE_F_EMERG_WRITE 2	/* Does host support emergency write? */
 
 #define VIRTIO_CONSOLE_BAD_ID		(~(u32)0)
 
@@ -48,6 +49,8 @@ struct virtio_console_config {
 	__u16 rows;
 	/* max. number of ports this device can hold */
 	__u32 max_nr_ports;
+	/* emergency write register */
+	__u32 emerg_wr;
 } __attribute__((packed));
 
 /*


From kyungsik.lee at lge.com  Mon May  6 04:42:54 2013
From: kyungsik.lee at lge.com (Kyungsik Lee)
Date: Mon,  6 May 2013 17:42:54 +0900
Subject: [PATCH -next 1/2] arm: Remove enforced Os flag for LZ4 decompressor
Message-ID: <1367829775-4434-1-git-send-email-kyungsik.lee@lge.com>

-Os is enforced here, based on the test result of decompression time
below, slightly faster than -O2.

But further tests with UA show that using -O2 will be the right choice
especially in the case of the unaligned access enabled and the gap,
few counts in the normal decompression mode is small enough to remove -Os.

Decompression Time(counts)
     Normal    UA enabled
-Os  6717      3447
-O2  6720      2728

Note: ARM v7, Kernel 3.4
      counter freq. = 32768 HZ
      UA(Unaligned Access)
      gcc version 4.6.2

Signed-off-by: Kyungsik Lee <kyungsik.lee at lge.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <rmk at arm.linux.org.uk>
Cc: Borislav Petkov <bp at alien8.de>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Yann Collet <yann.collet.73 at gmail.com>
---
 arch/arm/boot/compressed/Makefile | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 001a13a..198a4ad 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -27,9 +27,6 @@ OBJS	+= misc.o decompress.o
 ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
 OBJS	+= debug.o
 endif
-ifeq ($(CONFIG_KERNEL_LZ4),y)
-CFLAGS_decompress.o := -Os
-endif
 FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
 
 # string library code (-Os is enforced to keep it much smaller)
-- 
1.8.1.1



From kyungsik.lee at lge.com  Mon May  6 04:42:55 2013
From: kyungsik.lee at lge.com (Kyungsik Lee)
Date: Mon,  6 May 2013 17:42:55 +0900
Subject: [PATCH -next 2/2] kbuild: fix for updated LZ4 tool with the new
 streaming format
In-Reply-To: <1367829775-4434-1-git-send-email-kyungsik.lee@lge.com>
References: <1367829775-4434-1-git-send-email-kyungsik.lee@lge.com>
Message-ID: <1367829775-4434-2-git-send-email-kyungsik.lee@lge.com>

LZ4 has been updated with LZ4 Streaming Format specification(v1.3).
lz4demo is replaced by lz4c. lz4c supports both the new streaming and
legacy format with -l option.

This patch makes use of lz4c to support legacy format which is
used for LZ4 De/compression in the linux kernel.

Link: https://code.google.com/p/lz4/source/checkout
Signed-off-by: Kyungsik Lee <kyungsik.lee at lge.com>
Cc: "H. Peter Anvin" <hpa at zytor.com>
Cc: Ingo Molnar <mingo at elte.hu>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <rmk at arm.linux.org.uk>
Cc: Borislav Petkov <bp at alien8.de>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Yann Collet <yann.collet.73 at gmail.com>
Cc: Chanho Min <chanho.min at lge.com>
---
 scripts/Makefile.lib | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index a0ab6d7..c9bfbb0 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -313,7 +313,7 @@ cmd_lzo = (cat $(filter-out FORCE,$^) | \
 
 quiet_cmd_lz4 = LZ4     $@
 cmd_lz4 = (cat $(filter-out FORCE,$^) | \
-	lz4demo -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+	lz4c -l -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
 	(rm -f $@ ; false)
 
 # U-Boot mkimage
-- 
1.8.1.1



From shawn.guo at linaro.org  Mon May  6 04:46:03 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 May 2013 16:46:03 +0800
Subject: [PATCH V2] tty/serial/mvf: add MVF uart driver support
In-Reply-To: <1367480506-13220-1-git-send-email-b35083@freescale.com>
References: <1367480506-13220-1-git-send-email-b35083@freescale.com>
Message-ID: <20130506084601.GG1749@S2101-09.ap.freescale.net>

On Thu, May 02, 2013 at 03:41:46PM +0800, Jingchang Lu wrote:
> It adds Freescale Vybrid Family uart driver support
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
>   Remove unused variables and clean up the code
>   based on the comments for last version.
> 
>  drivers/tty/serial/Kconfig       |   17 +
>  drivers/tty/serial/Makefile      |    1 +
>  drivers/tty/serial/mvf.c         | 1053 ++++++++++++++++++++++++++++++++++++++
>  include/uapi/linux/serial_core.h |    3 +

You should have a binding doc added in
Documentation/devicetree/bindings/tty/serial/.

>  4 files changed, 1074 insertions(+)
>  create mode 100644 drivers/tty/serial/mvf.c
> 
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 7e7006f..032df6f 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -574,6 +574,23 @@ config SERIAL_IMX_CONSOLE
>  	  your boot loader (lilo or loadlin) about how to pass options to the
>  	  kernel at boot time.)
>  
> +config SERIAL_MVF
> +	bool "Freescale Vybrid serial port support"
> +	depends on SOC_MVF600
> +	select SERIAL_CORE
> +	select RATIONAL
> +	help
> +	  If you have a machine based on a Freescale Vybrid CPU you
> +	  can enable its onboard serial port by enabling this option.
> +
> +config SERIAL_MVF_CONSOLE
> +	bool "Console on Vybrid serial port"
> +	depends on SERIAL_MVF
> +	select SERIAL_CORE_CONSOLE
> +	help
> +	  If you have enabled the serial port on the Freescale Vybrid family
> +	  CPU you can make it the console by answering Y to this option.
> +
>  config SERIAL_UARTLITE
>  	tristate "Xilinx uartlite serial port support"
>  	depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE
> diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
> index eedfec4..be2ed68 100644
> --- a/drivers/tty/serial/Makefile
> +++ b/drivers/tty/serial/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
>  obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
>  obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
>  obj-$(CONFIG_SERIAL_IMX) += imx.o
> +obj-$(CONFIG_SERIAL_MVF) += mvf.o
>  obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
>  obj-$(CONFIG_SERIAL_ICOM) += icom.o
>  obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
> diff --git a/drivers/tty/serial/mvf.c b/drivers/tty/serial/mvf.c
> new file mode 100644
> index 0000000..e265e14
> --- /dev/null
> +++ b/drivers/tty/serial/mvf.c
> @@ -0,0 +1,1053 @@
> +/*
> + *  Driver for Freescale Vybrid Family serial ports
> + *
> + *  Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#if defined(CONFIG_SERIAL_MVF_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
> +#define SUPPORT_SYSRQ
> +#endif
> +
> +#include <linux/module.h>
> +#include <linux/ioport.h>
> +#include <linux/init.h>
> +#include <linux/console.h>
> +#include <linux/sysrq.h>
> +#include <linux/platform_device.h>
> +#include <linux/tty.h>
> +#include <linux/tty_flip.h>
> +#include <linux/serial_core.h>
> +#include <linux/serial.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/rational.h>
> +#include <linux/slab.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/consumer.h>
> +#include <linux/io.h>
> +#include <asm/irq.h>
> +#include <linux/platform_data/serial-imx.h>

You do not need this header at all.

It seems you copied all these headers from imx.c, but you should really
scan them to pick out what you actually need.

> +
> +/* All uart module registers for MVF is 8-bit width */
> +#define MXC_UARTBDH		0x00 /* Baud rate reg: high */

I do not like the prefix "MXC_".  You can use "MVF_" but I prefer to
not use any prefix.

I'm not sure how useful those comments following the definitions are.
I can even know the registers from the macro names.

Scanning the following bunch of marcos in the file, I found that many of
them are not used at all.  And I guess mostly they will never used in
this file.  I'm wondering why we define those unused registers and bits
at all.

> +#define MXC_UARTBDL		0x01 /* Baud rate reg: low */
> +#define MXC_UARTCR1		0x02 /* Control reg 1 */
> +#define MXC_UARTCR2		0x03 /* Control reg 2 */
> +#define MXC_UARTSR1		0x04 /* Status reg 1 */
> +#define MXC_UARTSR2		0x05 /* Status reg 2 */
> +#define MXC_UARTCR3		0x06 /* Control reg 3 */
> +#define MXC_UARTDR		0x07 /* Data reg */
> +#define MXC_UARTMAR1		0x08 /* Match address reg 1 */
> +#define MXC_UARTMAR2		0x09 /* Match address reg 2 */
> +#define MXC_UARTCR4		0x0A /* Control reg 4 */
> +#define MXC_UARTCR5		0x0B /* Control reg 5 */
> +#define MXC_UARTEDR		0x0C /* Extended data reg */
> +#define MXC_UARTMODEM		0x0D /* Modem reg */
> +#define MXC_UARTIR		0x0E /* Infrared reg */
> +#define MXC_UARTPFIFO		0x10 /* FIFO parameter reg */
> +#define MXC_UARTCFIFO		0x11 /* FIFO control reg */
> +#define MXC_UARTSFIFO		0x12 /* FIFO status reg */
> +#define MXC_UARTTWFIFO		0x13 /* FIFO transmit watermark reg */
> +#define MXC_UARTTCFIFO		0x14 /* FIFO transmit count reg */
> +#define MXC_UARTRWFIFO		0x15 /* FIFO receive watermark reg */
> +#define MXC_UARTRCFIFO		0x16 /* FIFO receive count reg */
> +#define MXC_UARTC7816		0x18 /* 7816 control reg */
> +#define MXC_UARTIE7816		0x19 /* 7816 interrupt enable reg */
> +#define MXC_UARTIS7816		0x1A /* 7816 interrupt status reg */
> +#define MXC_UARTWP7816T0	0x1B /* 7816 wait parameter reg */
> +#define MXC_UARTWP7816T1	0x1B /* 7816 wait parameter reg */
> +#define MXC_UARTWN7816		0x1C /* 7816 wait N reg */
> +#define MXC_UARTWF7816		0x1D /* 7816 wait FD reg */
> +#define MXC_UARTET7816		0x1E /* 7816 error threshold reg */
> +#define MXC_UARTTL7816		0x1F /* 7816 transmit length reg */
> +#define MXC_UARTCR6		0x21 /* CEA709.1-B contrl reg */
> +#define MXC_UARTPCTH		0x22 /* CEA709.1-B packet cycle counter high */
> +#define MXC_UARTPCTL		0x23 /* CEA709.1-B packet cycle counter low */
> +#define MXC_UARTB1T		0x24 /* CEA709.1-B beta 1 time */
> +#define MXC_UARTSDTH		0x25 /* CEA709.1-B secondary delay timer high */
> +#define MXC_UARTSDTL		0x26 /* CEA709.1-B secondary delay timer low */
> +#define MXC_UARTPRE		0x27 /* CEA709.1-B preamble */
> +#define MXC_UARTTPL		0x28 /* CEA709.1-B transmit packet length */
> +#define MXC_UARTIE		0x29 /* CEA709.1-B transmit interrupt enable */
> +#define MXC_UARTSR3		0x2B /* CEA709.1-B status reg */
> +#define MXC_UARTSR4		0x2C /* CEA709.1-B status reg */
> +#define MXC_UARTRPL		0x2D /* CEA709.1-B received packet length */
> +#define MXC_UARTRPREL		0x2E /* CEA709.1-B received preamble length */
> +#define MXC_UARTCPW		0x2F /* CEA709.1-B collision pulse width */
> +#define MXC_UARTRIDT		0x30 /* CEA709.1-B receive indeterminate time */
> +#define MXC_UARTTIDT		0x31 /* CEA709.1-B transmit indeterminate time*/
> +
> +/* Bit definations of BDH */
> +#define MXC_UARTBDH_LBKDIE	0x80 /* LIN break detect interrupt enable */
> +#define MXC_UARTBDH_RXEDGIE	0x40 /* RxD input Active edge interrupt enable*/
> +#define MXC_UARTBDH_SBR_MASK	0x1f /* Uart baud rate high 5-bits */
> +/* Bit definations of CR1 */
> +#define MXC_UARTCR1_LOOPS	0x80 /* Loop mode select */
> +#define MXC_UARTCR1_RSRC	0x20 /* Receiver source select */
> +#define MXC_UARTCR1_M		0x10 /* 9-bit 8-bit mode select */
> +#define MXC_UARTCR1_WAKE	0x08 /* Receiver wakeup method */
> +#define MXC_UARTCR1_ILT		0x04 /* Idle line type */
> +#define MXC_UARTCR1_PE		0x02 /* Parity enable */
> +#define MXC_UARTCR1_PT		0x01 /* Parity type */
> +/* Bit definations of CR2 */
> +#define MXC_UARTCR2_TIE		0x80 /* Tx interrupt or DMA request enable */
> +#define MXC_UARTCR2_TCIE	0x40 /* Transmission complete int enable */
> +#define MXC_UARTCR2_RIE		0x20 /* Rx full int or DMA request enable */
> +#define MXC_UARTCR2_ILIE	0x10 /* Idle line interrupt enable */
> +#define MXC_UARTCR2_TE		0x08 /* Transmitter enable */
> +#define MXC_UARTCR2_RE		0x04 /* Receiver enable */
> +#define MXC_UARTCR2_RWU		0x02 /* Receiver wakeup control */
> +#define MXC_UARTCR2_SBK		0x01 /* Send break */
> +/* Bit definations of SR1 */
> +#define MXC_UARTSR1_TDRE	0x80 /* Tx data reg empty */
> +#define MXC_UARTSR1_TC		0x40 /* Transmit complete */
> +#define MXC_UARTSR1_RDRF	0x20 /* Rx data reg full */
> +#define MXC_UARTSR1_IDLE	0x10 /* Idle line flag */
> +#define MXC_UARTSR1_OR		0x08 /* Receiver overrun */
> +#define MXC_UARTSR1_NF		0x04 /* Noise flag */
> +#define MXC_UARTSR1_FE		0x02 /* Frame error */
> +#define MXC_UARTSR1_PE		0x01 /* Parity error */
> +/* Bit definations of SR2 */
> +#define MXC_UARTSR2_LBKDIF	0x80 /* LIN brk detect interrupt flag */
> +#define MXC_UARTSR2_RXEDGIF	0x40 /* RxD pin active edge interrupt flag */
> +#define MXC_UARTSR2_MSBF	0x20 /* MSB first */
> +#define MXC_UARTSR2_RXINV	0x10 /* Receive data inverted */
> +#define MXC_UARTSR2_RWUID	0x08 /* Receive wakeup idle detect */
> +#define MXC_UARTSR2_BRK13	0x04 /* Break transmit character length */
> +#define MXC_UARTSR2_LBKDE	0x02 /* LIN break detection enable */
> +#define MXC_UARTSR2_RAF		0x01 /* Receiver active flag */
> +/* Bit definations of CR3 */
> +#define MXC_UARTCR3_R8		0x80 /* Received bit8, for 9-bit data format */
> +#define MXC_UARTCR3_T8		0x40 /* transmit bit8, for 9-bit data format */
> +#define MXC_UARTCR3_TXDIR	0x20 /* Tx pin direction in single-wire mode */
> +#define MXC_UARTCR3_TXINV	0x10 /* Transmit data inversion */
> +#define MXC_UARTCR3_ORIE	0x08 /* Overrun error interrupt enable */
> +#define MXC_UARTCR3_NEIE	0x04 /* Noise error interrupt enable */
> +#define MXC_UARTCR3_FEIE	0x02 /* Framing error interrupt enable */
> +#define MXC_UARTCR3_PEIE	0x01 /* Parity errror interrupt enable */
> +/* Bit definations of CR4 */
> +#define MXC_UARTCR4_MAEN1	0x80 /* Match address mode enable 1 */
> +#define MXC_UARTCR4_MAEN2	0x40 /* Match address mode enable 2 */
> +#define MXC_UARTCR4_M10		0x20 /* 10-bit mode select */
> +#define MXC_UARTCR4_BRFA_MASK	0x1F /* Baud rate fine adjust */
> +#define MXC_UARTCR4_BRFA_OFF	0
> +/* Bit definations of CR5 */
> +#define MXC_UARTCR5_TDMAS	0x80 /* Transmitter DMA select */
> +#define MXC_UARTCR5_RDMAS	0x20 /* Receiver DMA select */
> +/* Bit definations of Modem */
> +#define MXC_UARTMODEM_RXRTSE	0x08 /* Enable receiver request-to-send */
> +#define MXC_UARTMODEM_TXRTSPOL	0x04 /* Select transmitter RTS polarity */
> +#define MXC_UARTMODEM_TXRTSE	0x02 /* Enable transmitter request-to-send */
> +#define MXC_UARTMODEM_TXCTSE	0x01 /* Enable transmitter CTS clear-to-send */
> +/* Bit definations of EDR */
> +#define MXC_UARTEDR_NOISY	0x80 /* Current dataword received with noise */
> +#define MXC_UARTEDR_PARITYE	0x40 /* Dataword received with parity error */
> +/* Bit definations of Infrared reg(IR) */
> +#define MXC_UARTIR_IREN		0x04 /* Infrared enable */
> +#define MXC_UARTIR_TNP_MASK	0x03 /* Transmitter narrow pluse */
> +#define MXC_UARTIR_TNP_OFF	0
> +/* Bit definations of FIFO parameter reg */
> +#define MXC_UARTPFIFO_TXFE	0x80 /* Transmit fifo enable */
> +#define MXC_UARTPFIFO_FIFOSIZE_MASK	0x7
> +#define MXC_UARTPFIFO_TXFIFOSIZE_OFF	4
> +#define MXC_UARTPFIFO_RXFE	0x08 /* Receiver fifo enable */
> +#define MXC_UARTPFIFO_RXFIFOSIZE_OFF	0
> +/* Bit definations of FIFO control reg */
> +#define MXC_UARTCFIFO_TXFLUSH	0x80 /* Transmit FIFO/buffer flush */
> +#define MXC_UARTCFIFO_RXFLUSH	0x40 /* Receive FIFO/buffer flush */
> +#define MXC_UARTCFIFO_RXOFE	0x04 /* Receive fifo overflow INT enable */
> +#define MXC_UARTCFIFO_TXOFE	0x02 /* Transmit fifo overflow INT enable */
> +#define MXC_UARTCFIFO_RXUFE	0x01 /* Receive fifo underflow INT enable */
> +/* Bit definations of FIFO status reg */
> +#define MXC_UARTSFIFO_TXEMPT	0x80 /* Transmit fifo/buffer empty */
> +#define MXC_UARTSFIFO_RXEMPT	0x40 /* Receive fifo/buffer empty */
> +#define MXC_UARTSFIFO_RXOF	0x04 /* Rx buffer overflow flag */
> +#define MXC_UARTSFIFO_TXOF	0x02 /* Tx buffer overflow flag */
> +#define MXC_UARTSFIFO_RXUF	0x01 /* Rx buffer underflow flag */
> +
> +
> +/* follow IMX dev node number */
> +#define SERIAL_IMX_MAJOR	207
> +#define MINOR_START		24
> +#define DEV_NAME		"ttymxc"

I don't think we will likely run into it.  But will it be a problem if
we have a future SoC integrating both imx-uart and mvf-uart blocks?

> +#define DRIVER_NAME		"MVF-uart"
> +#define UART_NR			6
> +
> +struct mvf_port {
> +	struct uart_port	port;
> +	struct clk		*clk;
> +	unsigned int		tx_fifo_size, rx_fifo_size;
> +};
> +

---8<-------
> +enum mvf_uart_type {
> +	MVF600_UART,
> +};
> +
> +struct mvf_uart_data {
> +	enum mvf_uart_type devtype;
> +};
> +
> +static struct mvf_uart_data mvf_uart_devdata[] = {
> +	[MVF600_UART] = {
> +		.devtype = MVF600_UART,
> +	},
> +};
> +
> +static struct platform_device_id mvf_uart_devtype[] = {
> +	{
> +		.name = "mvf600-uart",
> +		.driver_data = (kernel_ulong_t) &mvf_uart_devdata[MVF600_UART],
> +	}, {
> +		/* sentinel */
> +	}
> +};
> +MODULE_DEVICE_TABLE(platform, mvf_uart_devtype);
------->8---

The above stuff is completely useless.  The imx driver uses it to
handle differences between two revision of the IP block.

> +
> +static struct of_device_id mvf_uart_dt_ids[] = {
> +	{
> +		.compatible = "fsl,mvf-uart",
> +		.data = &mvf_uart_devdata[MVF600_UART],
> +	},
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mvf_uart_dt_ids);

Remove .data field, and move the mvf_uart_dt_ids[] to where it's being
used, right before serial_mvf_driver definition.

<snip>

> +static int serial_mvf_probe_dt(struct mvf_port *sport,
> +		struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	int ret;
> +
> +	if (!np)
> +		return 1; /* no device tree device */
> +
> +	ret = of_alias_get_id(np, "serial");
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
> +		return ret;
> +	}
> +	sport->port.line = ret;
> +
> +	return 0;
> +}
> +
> +static int serial_mvf_probe(struct platform_device *pdev)
> +{
> +	struct mvf_port *sport;
> +	void __iomem *base;
> +	struct resource *res;
> +	struct pinctrl *pinctrl;
> +	int ret = 0;
> +
> +	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
> +	if (!sport)
> +		return -ENOMEM;
> +
> +	pdev->dev.coherent_dma_mask = 0;
> +
> +	ret = serial_mvf_probe_dt(sport, pdev);

We have this function for imx, because imx support both non-dt and dt
boot.  Since mvf supports dt boot only, I do not see the need of a DT
specific setup function.

> +	if (ret < 0)
> +		return ret;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -ENODEV;
> +
> +	base = devm_request_and_ioremap(&pdev->dev, res);
> +	if (!base)
> +		return -ENOMEM;
> +
> +	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
> +	if (IS_ERR(pinctrl))
> +		dev_warn(&pdev->dev,
> +			"did not get pinctrl for uart%i error: %li\n",
> +			sport->port.line, PTR_ERR(pinctrl));

Driver core already handles this type of pinctrl setup, so we do not
need to explicitly do it again here.

> +
> +	sport->port.dev = &pdev->dev;
> +	sport->port.mapbase = res->start;
> +	sport->port.membase = base;
> +	sport->port.type = PORT_MVF,
> +	sport->port.iotype = UPIO_MEM;
> +	sport->port.irq = platform_get_irq(pdev, 0);
> +	sport->port.ops = &mvf_pops;
> +	sport->port.flags = UPF_BOOT_AUTOCONF;
> +
> +	sport->clk = devm_clk_get(&pdev->dev, "ipg");
> +	if (IS_ERR(sport->clk)) {
> +		ret = PTR_ERR(sport->clk);
> +		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	clk_prepare_enable(sport->clk);
> +
> +	sport->port.uartclk = clk_get_rate(sport->clk);
> +
> +	mvf_ports[sport->port.line] = sport;
> +
> +	platform_set_drvdata(pdev, &sport->port);
> +
> +	ret = uart_add_one_port(&mvf_reg, &sport->port);
> +
> +	if (ret)
> +		goto clkput;
> +
> +	return 0;
> +clkput:
> +	clk_disable_unprepare(sport->clk);

The label name mismatches what it does.  The name says it puts clk while
it disables clock acutally.

> +
> +	return ret;
> +}
> +
> +static int serial_mvf_remove(struct platform_device *pdev)
> +{
> +	struct mvf_port *sport = platform_get_drvdata(pdev);
> +
> +	uart_remove_one_port(&mvf_reg, &sport->port);
> +
> +	clk_disable_unprepare(sport->clk);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver serial_mvf_driver = {
> +	.probe		= serial_mvf_probe,
> +	.remove		= serial_mvf_remove,
> +
Remove the blank line.

> +	.suspend	= serial_mvf_suspend,
> +	.resume		= serial_mvf_resume,

Shouldn't they be protected by #ifdef CONFIG_PM check?

> +	.id_table       = mvf_uart_devtype,
> +	.driver		= {
> +		.name	= "mvf-uart",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = mvf_uart_dt_ids,
> +	},
> +};
> +
> +static int __init mvf_serial_init(void)
> +{
> +	int ret;
> +
> +	pr_info("Serial: Freescale Vybrid Family driver\n");
> +
> +	ret = uart_register_driver(&mvf_reg);
> +	if (ret)
> +		return ret;
> +
> +	ret = platform_driver_register(&serial_mvf_driver);
> +	if (ret != 0)

This is inconsistent with if (ret) check right above.

Shawn

> +		uart_unregister_driver(&mvf_reg);
> +
> +	return 0;
> +}
> +
> +static void __exit mvf_serial_exit(void)
> +{
> +	platform_driver_unregister(&serial_mvf_driver);
> +	uart_unregister_driver(&mvf_reg);
> +}
> +
> +module_init(mvf_serial_init);
> +module_exit(mvf_serial_exit);
> +
> +MODULE_DESCRIPTION("Freescale Vybrid Family serial port driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
> index 74c2bf7..ffb7192 100644
> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -226,4 +226,7 @@
>  /* Rocketport EXPRESS/INFINITY */
>  #define PORT_RP2	102
>  
> +/* Freescale Vybrid uart */
> +#define PORT_MVF	103
> +
>  #endif /* _UAPILINUX_SERIAL_CORE_H */
> -- 
> 1.8.0
> 
> 



From peter.maydell at linaro.org  Mon May  6 05:14:23 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Mon, 6 May 2013 10:14:23 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <87ip2wr8tp.fsf@rustcorp.com.au>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
Message-ID: <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>

On 6 May 2013 06:11, Rusty Russell <rusty at rustcorp.com.au> wrote:
> Peter Maydell <peter.maydell at linaro.org> writes:
>> To be actually useful we need to also specify something in
>> the device tree to say "here is where you will find your
>> emergency output and what it is".
>
> Hmm, I'm not sure that's true.  It looks like it needs:
>
> 1) An enhancment to the vdev->set_config callback to pass through (at
>    least) an offset, probably offset and length.
>
> 2) An emerg_write() function ptr which can be called at any time, set by
>    virtio_console.c's class_init:

That all looks like sensible QEMU implementation possibilities
but it seems to be a bit of a non-sequitur from "how do we
tell the kernel to actually use this?"

-- PMM


From u.kleine-koenig at pengutronix.de  Mon May  6 05:30:59 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 6 May 2013 11:30:59 +0200
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130418091019.GA21099@pengutronix.de>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
Message-ID: <20130506093059.GH23285@pengutronix.de>

Hello,

On Thu, Apr 18, 2013 at 11:10:19AM +0200, Uwe Kleine-K?nig wrote:
> On Mon, Mar 18, 2013 at 11:28:56AM -0700, Stephen Boyd wrote:
> > The ISAR0 register indicates support for the SDIV and UDIV
> > instructions in both the Thumb and ARM instruction set. Read the
> > register to detect the supported instructions and update the
> > elf_hwcap mask as appropriate. This is better than adding more
> > and more cpuid checks in proc-v7.S for each new cpu variant that
> > supports these instructions.
> you pointed out yesterday that this could work on v7-m, too. As I based
> my patches on 3.9-rc1 this patch (8164f7af88) wasn't included. When
> updating this results in a warning, because I have
> 
> 	6ebd4d0 (ARM: stub out read_cpuid and read_cpuid_ext for CPU_CP15=n)
> 
> from rmk's devel-stable branch.
>  
> > Acked-by: Will Deacon <will.deacon at arm.com>
> > Cc: Stepan Moskovchenko <stepanm at codeaurora.org>
> > Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> > ---
> >  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
> >  arch/arm/mm/proc-v7.S   |  4 ++--
> >  2 files changed, 22 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> > index e2c8bbf..f3ac13f 100644
> > --- a/arch/arm/kernel/setup.c
> > +++ b/arch/arm/kernel/setup.c
> > @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
> >  	printk("%s", buf);
> >  }
> >  
> > +static void __init cpuid_init_hwcaps(void)
> > +{
> > +	unsigned int divide_instrs;
> > +
> > +	if (cpu_architecture() < CPU_ARCH_ARMv7)
> > +		return;
> > +
> > +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
> The problem is that read_cpuid_ext is called which doesn't map to
> something useful for v7-m. So maybe add a check:
> 
> 	if (!IS_ENABLED(CONFIG_CPU_CP15))
> 		return;
> 
> ?
The patch below fixes the issue for me on V7-M. The only drawback is
that the list of registers isn't shared. Maybe someone has a nice idea?

BTW, there doesn't seem to be an equivalent register set for 
CPUID_{CACHETYPE,TCM,TLBTYPE,MPIDR} on v7-M.

Best regards
Uwe

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 4eb94a3..ec635ff 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -10,6 +10,22 @@
 #define CPUID_TLBTYPE	3
 #define CPUID_MPIDR	5
 
+#ifdef CONFIG_CPU_V7M
+#define CPUID_EXT_PFR0	0x40
+#define CPUID_EXT_PFR1	0x44
+#define CPUID_EXT_DFR0	0x48
+#define CPUID_EXT_AFR0	0x4c
+#define CPUID_EXT_MMFR0	0x50
+#define CPUID_EXT_MMFR1	0x54
+#define CPUID_EXT_MMFR2	0x58
+#define CPUID_EXT_MMFR3	0x5c
+#define CPUID_EXT_ISAR0	0x60
+#define CPUID_EXT_ISAR1	0x64
+#define CPUID_EXT_ISAR2	0x68
+#define CPUID_EXT_ISAR3	0x6c
+#define CPUID_EXT_ISAR4	0x70
+#define CPUID_EXT_ISAR5	0x74
+#else
 #define CPUID_EXT_PFR0	"c1, 0"
 #define CPUID_EXT_PFR1	"c1, 1"
 #define CPUID_EXT_DFR0	"c1, 2"
@@ -24,6 +40,7 @@
 #define CPUID_EXT_ISAR3	"c2, 3"
 #define CPUID_EXT_ISAR4	"c2, 4"
 #define CPUID_EXT_ISAR5	"c2, 5"
+#endif
 
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
@@ -79,7 +96,23 @@ extern unsigned int processor_id;
 		__val;							\
 	})
 
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+
+#include <asm/io.h>
+#include <asm/v7m.h>
+
+#define read_cpuid(reg)							\
+	({								\
+		WARN_ON_ONCE(1);					\
+		0;							\
+	})
+
+static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
+{
+	return readl(BASEADDR_V7M_SCB + offset);
+}
+
+#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 
 /*
  * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -108,9 +141,6 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
 
 #elif defined(CONFIG_CPU_V7M)
 
-#include <asm/io.h>
-#include <asm/v7m.h>
-
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 000499c..0c93588 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -144,7 +144,7 @@ __v7m_proc_info:
 	b	__v7m_setup		@ proc_info_list.__cpu_flush
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_IDIVT
+	.long	HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
 	.long	cpu_v7m_name
 	.long	v7m_processor_functions	@ proc_info_list.proc
 	.long	0			@ proc_info_list.tlb

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From pranavkumar at linaro.org  Mon May  6 05:40:29 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Mon, 6 May 2013 15:10:29 +0530
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <87ip2wr8tp.fsf@rustcorp.com.au>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
Message-ID: <CAAHg+HhAgD=-YVOf_nmXv0MnX-3pp+yhNAwxXAfKr4Xp5XyP4w@mail.gmail.com>

Hi Rusty,

On 6 May 2013 10:41, Rusty Russell <rusty at rustcorp.com.au> wrote:
> Peter Maydell <peter.maydell at linaro.org> writes:
>> On 1 May 2013 03:07, Rusty Russell <rusty at rustcorp.com.au> wrote:
>>> An emergency output is a reasonable idea, and this is a reasonable
>>> implementation.  The question is practical: will it be used?  Because we
>>> don't implement reasonable ideas which aren't going to be used.
>>
>> If you think it fits reasonably into the virtio spec (ie doesn't
>> implement things at the wrong level of the transport/backend
>> abstraction) then we can implement it in QEMU, and I think it
>> makes more sense to do this than to throw in a random extra
>> serial port.
>>
>> To be actually useful we need to also specify something in
>> the device tree to say "here is where you will find your
>> emergency output and what it is".
>
> Hmm, I'm not sure that's true.  It looks like it needs:
>
> 1) An enhancment to the vdev->set_config callback to pass through (at
>    least) an offset, probably offset and length.
>
> 2) An emerg_write() function ptr which can be called at any time, set by
>    virtio_console.c's class_init:
>
> static void emerg_write(VirtIOSerialPort *port, char c)
> {
>     VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
>
>     if (vcon->chr)
>         qemu_chr_fe_write(vcon->chr, &c, 1);
> }
>
> 3) A routine to find an emerg-write-capable console in
>    virtio_serial_bus.c (or just assume port 0?):
>
> static VirtIOSerialPort *find_emerg_write_port(VirtIOSerial *vser)
> {
>     VirtIOSerialPort *port;
>
>     QTAILQ_FOREACH(port, &vser->ports, next) {
>         VirtIOSerialPortClass *vsc;
>         vsc = VIRTIO_SERIAL_PORT_GET_CLASS(port);
>
>         if (vsc->emerg_write) {
>             return port;
>         }
>     }
>     return NULL;
> }
>
> 4) set_config in virtio_serial_bus.c to notice emergency writes:
>
>     if (offset == offsetof(struct virtio_console_config, emerg_w) {
>         VirtIOSerial *vser;
>         vser = DO_UPCAST(VirtIOSerial, vdev, vdev);
>         VirtIOSerialPort *port;
>
>         port = find_emerg_write_port(vser);
>         if (port) {
>             vsc->emerg_write(port, config.emerg_w);
>         }
>     }
>
> Amit might have more clue... Amit?
>
> Thanks,
> Rusty.
>
> From: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Subject: virtio: console: Add early writeonly register to config space
>
> This patch adds a emerg_wr register (writeonly) in config space of virtio console device which can be used for debugging.
>
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
> ---
>  include/uapi/linux/virtio_console.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/uapi/linux/virtio_console.h b/include/uapi/linux/virtio_console.h
> index ee13ab6..586678d 100644
> --- a/include/uapi/linux/virtio_console.h
> +++ b/include/uapi/linux/virtio_console.h
> @@ -38,6 +38,7 @@
>  /* Feature bits */
>  #define VIRTIO_CONSOLE_F_SIZE  0       /* Does host provide console size? */
>  #define VIRTIO_CONSOLE_F_MULTIPORT 1   /* Does host provide multiple ports? */
> +#define VIRTIO_CONSOLE_F_EMERG_WRITE 2 /* Does host support emergency write? */
>
>  #define VIRTIO_CONSOLE_BAD_ID          (~(u32)0)
>
> @@ -48,6 +49,8 @@ struct virtio_console_config {
>         __u16 rows;
>         /* max. number of ports this device can hold */
>         __u32 max_nr_ports;
> +       /* emergency write register */
> +       __u32 emerg_wr;
>  } __attribute__((packed));
>
>  /*

I will send above patch with V2 tagged with the addition of
documentation change and also separate arm64 early printk
implementation for the same.

Thanks,
Pranav


From bp at alien8.de  Mon May  6 05:51:24 2013
From: bp at alien8.de (Borislav Petkov)
Date: Mon, 6 May 2013 11:51:24 +0200
Subject: [PATCH -next 2/2] kbuild: fix for updated LZ4 tool with the new
 streaming format
In-Reply-To: <1367829775-4434-2-git-send-email-kyungsik.lee@lge.com>
References: <1367829775-4434-1-git-send-email-kyungsik.lee@lge.com>
 <1367829775-4434-2-git-send-email-kyungsik.lee@lge.com>
Message-ID: <20130506095124.GA22041@pd.tnic>

On Mon, May 06, 2013 at 05:42:55PM +0900, Kyungsik Lee wrote:
> LZ4 has been updated with LZ4 Streaming Format specification(v1.3).
> lz4demo is replaced by lz4c. lz4c supports both the new streaming and
> legacy format with -l option.
> 
> This patch makes use of lz4c to support legacy format which is
> used for LZ4 De/compression in the linux kernel.
> 
> Link: https://code.google.com/p/lz4/source/checkout
> Signed-off-by: Kyungsik Lee <kyungsik.lee at lge.com>
> Cc: "H. Peter Anvin" <hpa at zytor.com>
> Cc: Ingo Molnar <mingo at elte.hu>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Russell King <rmk at arm.linux.org.uk>
> Cc: Borislav Petkov <bp at alien8.de>
> Cc: Florian Fainelli <florian at openwrt.org>
> Cc: Yann Collet <yann.collet.73 at gmail.com>
> Cc: Chanho Min <chanho.min at lge.com>
> ---
>  scripts/Makefile.lib | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> index a0ab6d7..c9bfbb0 100644
> --- a/scripts/Makefile.lib
> +++ b/scripts/Makefile.lib
> @@ -313,7 +313,7 @@ cmd_lzo = (cat $(filter-out FORCE,$^) | \
>  
>  quiet_cmd_lz4 = LZ4     $@
>  cmd_lz4 = (cat $(filter-out FORCE,$^) | \
> -	lz4demo -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
> +	lz4c -l -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \

You probably want to check for the presence of lz4c on the system and
bail with an informative message if absent.

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--


From u.kleine-koenig at pengutronix.de  Mon May  6 05:48:51 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 6 May 2013 11:48:51 +0200
Subject: [RFC patch 0/8] genirq: Support for irq domains in generic irq
 chip
In-Reply-To: <20130503212258.385818955@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
Message-ID: <20130506094851.GI23285@pengutronix.de>

Hello,

On Fri, May 03, 2013 at 09:50:43PM -0000, Thomas Gleixner wrote:
> The ongoing device tree support for ARM is creating new irq chip
> drivers in drivers/irqchip/ in a frenzy. Quite some of them are
> ripping out the generic irq chip implementation from arch/arm/* and
> just creating the same mess of duplicated code again, which was
> cleaned up with the generic irq chip implementation with a lot of
> effort. Sigh!
> 
> I already prodded a few people in reviews to tackle that issue with no
> outcome. Even more sigh!
> 
> Poor Sebastian triggered me into rant mode, but he ad hoc
> volunteered to give it a try. YAY!
> 
> Though he asked for a bit of kickstart help. So I squeezed out a few
> spare cycles and implemented the basics as far as I think that they
> should work.
> 
> The following series contains the missing bits and pieces including a
> somehow forgotten and now slightly modified series from Gerlando
> adding support for irq chips which need separate mask caches for
> different chip (control flow) types.
> 
> At the moment this supports only linear irq domains, but it could be
> extended to other types as well if the need arises. Though the ARM
> chips are pretty much all about linear domains AFAICT.
Is there a tree/set of patches that have already fixed the issues
pointed out by Russell and Sebastian? I'd like to use it to get forward
with my nvic patch and want to avert double work and merging different
approaches.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From rubini at gnudd.com  Mon May  6 05:54:30 2013
From: rubini at gnudd.com (Alessandro Rubini)
Date: Mon, 6 May 2013 11:54:30 +0200
Subject: [PATCH v4 0/7] enable support for AMBA drivers under x86
In-Reply-To: <20130506094154.GA9464@gmail.com>
References: <20130506094154.GA9464@gmail.com>
 <20130505123633.GA14095@pd.tnic>  <50C93A83.8040106@zytor.com>
 <1355146956-6009-1-git-send-email-ciminaghi@gnudd.com>
 <50C93718.2090706@zytor.com>  <20121213181449.GA15966@mail.gnudd.com>
 <20130505202422.GA13758@mail.gnudd.com>  <20130505203932.GA12742@pd.tnic>
Message-ID: <20130506095430.GA26898@mail.gnudd.com>

All-To: mingo at kernel.org,bp at alien8.de,hpa at zytor.com,ciminaghi at gnudd.com,jaswinder.singh at linaro.org,will.deacon at arm.com,linux at arm.linux.org.uk,tglx at linutronix.de,mingo at redhat.com,djbw at fb.com,vinod.koul at intel.com,grant.likely at secretlab.ca,linus.walleij at linaro.org,wim at iguana.be,cjb at laptop.org,davidb at codeaurora.org,nico at fluxnic.net,ben-linux at fluff.org,viresh.linux at gmail.com,rajeev-dlh.kumar at st.com,linux-kernel at vger.kernel.org,linux-arm-kernel at lists.infradead.org,giancarlo.asnaghi at st.com Re: [PATCH v4 0/7] enable support for AMBA drivers under x86
> From: Ingo Molnar <mingo at kernel.org>
> To: Borislav Petkov <bp at alien8.de>
> Cc: Alessandro Rubini <rubini at gnudd.com>, hpa at zytor.com, ciminaghi at gnudd.com,         jaswinder.singh at linaro.org, will.deacon at arm.com,         linux at arm.linux.org.uk, tglx at linutronix.de, mingo at redhat.com,         djbw at fb.com, vinod.koul at intel.com, grant.likely at secretlab.ca,         linus.walleij at linaro.org, wim at iguana.be, cjb at laptop.org,         davidb at codeaurora.org, nico at fluxnic.net, ben-linux at fluff.org,         viresh.linux at gmail.com, rajeev-dlh.kumar at st.com,         linux-kernel at vger.kernel.org, linux-arm-kernel at lists.infradead.org,         giancarlo.asnaghi at st.com
> Subject: Re: [PATCH v4 0/7] enable support for AMBA drivers under x86
> Date: Mon, 6 May 2013 11:41:54 +0200

> A lot happened meanwhile - patches got acked, applied - so I expected a 
> resend of the patches that are still pending, with all acks in place in 
> the patches (not in the cover letter), and against Linus's latest tree.

Ok, I'll resend this AMBA/PCI set.  But this warning we are discussing
about is unrelated and I sent it by itself in february.  Anyways, I'll
add it to the patch-set I'm going to send most likely tomorrow.

thanks
/alessndro


From mingo at kernel.org  Mon May  6 05:41:54 2013
From: mingo at kernel.org (Ingo Molnar)
Date: Mon, 6 May 2013 11:41:54 +0200
Subject: [PATCH v4 0/7] enable support for AMBA drivers under x86
In-Reply-To: <20130505203932.GA12742@pd.tnic>
References: <20130505123633.GA14095@pd.tnic> <50C93A83.8040106@zytor.com>
 <1355146956-6009-1-git-send-email-ciminaghi@gnudd.com>
 <50C93718.2090706@zytor.com>
 <20121213181449.GA15966@mail.gnudd.com>
 <20130505202422.GA13758@mail.gnudd.com>
 <20130505203932.GA12742@pd.tnic>
Message-ID: <20130506094154.GA9464@gmail.com>


* Borislav Petkov <bp at alien8.de> wrote:

> On Sun, May 05, 2013 at 10:24:22PM +0200, Alessandro Rubini wrote:
> > > Did this got fixed in some tree in the meantime? Because I still see it on
> > > current Linus + tip/master:
> > > 
> > > arch/x86/pci/sta2x11-fixup.c:186:2: warning: initialization from incompatible pointer type [enabled by default]
> > > arch/x86/pci/sta2x11-fixup.c:186:2: warning: (near initialization for ??????sta2x11_dma_ops.free??????) [enabled by default]
> > 
> > Last time I sent the patch was on Feb 22nd:
> > 
> >    The .free field of struct dma_map_ops features a prototype that is
> >    different from what lib/swiotlb.c offers. The new "attrs" argument in
> >    dma_ops.free is missing from the generic implementation.
> > 
> >    This removes the build warning by providing a function that just calls
> >    swiotlb_free_coherent() without passing "attrs", like others do.
> > 
> > I got no reply.
> 
> It probably fell through the cracks...
> 
> > This is the link:
> > 
> >     http://lkml.org/lkml/2013/2/22/111
> > 
> > It is in patchwork here:
> > 
> >     https://patchwork.kernel.org/patch/2175551/
> 
> Ingo, hpa, can you guys pick it up?

A lot happened meanwhile - patches got acked, applied - so I expected a 
resend of the patches that are still pending, with all acks in place in 
the patches (not in the cover letter), and against Linus's latest tree.

Thanks,

	Ingo


From bp at alien8.de  Mon May  6 06:11:12 2013
From: bp at alien8.de (Borislav Petkov)
Date: Mon, 6 May 2013 12:11:12 +0200
Subject: [PATCH v4 0/7] enable support for AMBA drivers under x86
In-Reply-To: <20130506094154.GA9464@gmail.com>
References: <20130505123633.GA14095@pd.tnic> <50C93A83.8040106@zytor.com>
 <1355146956-6009-1-git-send-email-ciminaghi@gnudd.com>
 <50C93718.2090706@zytor.com>
 <20121213181449.GA15966@mail.gnudd.com>
 <20130505202422.GA13758@mail.gnudd.com>
 <20130505203932.GA12742@pd.tnic> <20130506094154.GA9464@gmail.com>
Message-ID: <20130506101112.GA22084@pd.tnic>

On Mon, May 06, 2013 at 11:41:54AM +0200, Ingo Molnar wrote:
> A lot happened meanwhile - patches got acked, applied - so I expected
> a resend of the patches that are still pending, with all acks in place
> in the patches (not in the cover letter), and against Linus's latest
> tree.

That one above was a single submission anyway and it could go in now
since it fixes a build issue. I don't know about the rest of the set
though.

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--


From broonie at kernel.org  Mon May  6 06:29:57 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 6 May 2013 11:29:57 +0100
Subject: [RFT][PATCH 1/2] clk: wm831x: Fix update wrong register for
 enable/disable FLL
In-Reply-To: <1367422261.8160.1.camel@phoenix>
References: <1367422261.8160.1.camel@phoenix>
Message-ID: <20130506102957.GA13472@opensource.wolfsonmicro.com>

On Wed, May 01, 2013 at 11:31:01PM +0800, Axel Lin wrote:
> According to the datasheet, FLL Enable is controlled by
> R16530 (4092h) FLL Control1

Both

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From broonie at kernel.org  Mon May  6 06:31:05 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 6 May 2013 11:31:05 +0100
Subject: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
 xfer->speed_hz set
In-Reply-To: <5182414F.1000201@atmel.com>
References: <1362626715-6549-1-git-send-email-wenyou.yang@atmel.com>
 <1362626815-6628-1-git-send-email-wenyou.yang@atmel.com>
 <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
 <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>
 <CACQ1gAhZO3stjrwf5SiZf7jOO8T5bAJZiz97M7+7vwFmk2e65g@mail.gmail.com>
 <5182414F.1000201@atmel.com>
Message-ID: <20130506103105.GB13472@opensource.wolfsonmicro.com>

On Thu, May 02, 2013 at 12:34:55PM +0200, Nicolas Ferre wrote:

> Can you tell us if this SPI patch will be merged upstream using one
> of your paths?

I have no idea what patch this is but if it's not in my tree -next it's
unlikely to be merged.
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From pranavkumar at linaro.org  Mon May  6 08:19:48 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Mon,  6 May 2013 17:49:48 +0530
Subject: [PATCH V2 0/3] Emergency write support for virtio console devices.
Message-ID: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>

This patch-set implements early printk support for virtio console
devices by adding and using emergency write register to virtio console's 
config space.

The current virtio early printk code in kernel expects that hypervisor 
will provide some mechanism generally a hypercall to support early printk. 
This patch-set does not break existing hypercall based early print support.

This implementation adds:
1. Emergency writeonly register named emerg_wr in 
   virtio console's config space.
2. Host feature flags namely VIRTIO_CONSOLE_F_EMERG_WRITE
   for telling guest about early-write capability in console device.

Emergency write mechanism:
1. When a guest wants to out some character, it has to simply write 
   the character to emerg_wr register in config space of 
   virtio console device.

Pranavkumar Sawargaonkar (3):
  virtio: console: Add emergency writeonly register to config space
  Documentation: virtio: Add emergency write (emerg_wr) config register
        in virtio console.
  arm64: earlyprintk support for virtio-mmio console.

 Documentation/virtual/virtio-spec.txt |    8 +++++++-
 arch/arm64/kernel/early_printk.c      |   35 +++++++++++++++++++++++++++++++++
 include/uapi/linux/virtio_console.h   |    3 +++
 3 files changed, 45 insertions(+), 1 deletion(-)

-- 
1.7.9.5



From pranavkumar at linaro.org  Mon May  6 08:19:49 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Mon,  6 May 2013 17:49:49 +0530
Subject: [PATCH V2 1/3] virtio: console: Add emergency writeonly register to
 config space
In-Reply-To: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
Message-ID: <1367842791-30285-2-git-send-email-pranavkumar@linaro.org>

This patch adds an emerg_wr register (writeonly) in config space
of virtio console device which can be used for debugging.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 include/uapi/linux/virtio_console.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/uapi/linux/virtio_console.h b/include/uapi/linux/virtio_console.h
index ee13ab6..3fd0dce 100644
--- a/include/uapi/linux/virtio_console.h
+++ b/include/uapi/linux/virtio_console.h
@@ -38,6 +38,7 @@
 /* Feature bits */
 #define VIRTIO_CONSOLE_F_SIZE	0	/* Does host provide console size? */
 #define VIRTIO_CONSOLE_F_MULTIPORT 1	/* Does host provide multiple ports? */
+#define VIRTIO_CONSOLE_F_EMERG_WRITE 2 /* Does host support emergency write? */
 
 #define VIRTIO_CONSOLE_BAD_ID		(~(u32)0)
 
@@ -48,6 +49,8 @@ struct virtio_console_config {
 	__u16 rows;
 	/* max. number of ports this device can hold */
 	__u32 max_nr_ports;
+	/* emergency write register */
+	__u32 emerg_wr;
 } __attribute__((packed));
 
 /*
-- 
1.7.9.5



From pranavkumar at linaro.org  Mon May  6 08:19:50 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Mon,  6 May 2013 17:49:50 +0530
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write (emerg_wr)
 config register in virtio console.
In-Reply-To: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
Message-ID: <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
---
 Documentation/virtual/virtio-spec.txt |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/virtual/virtio-spec.txt b/Documentation/virtual/virtio-spec.txt
index 0d6ec85..3ca38f8 100644
--- a/Documentation/virtual/virtio-spec.txt
+++ b/Documentation/virtual/virtio-spec.txt
@@ -1927,11 +1927,16 @@ Ports 2 onwards only if VIRTIO_CONSOLE_F_MULTIPORT is set
     ports; configuration fields nr_ports and max_nr_ports are
     valid and control virtqueues will be used.
 
+  VIRTIO_CONSOLE_F_EMERG_WRITE(2) Device has support for emergency
+  write. Configuration filed emerg_wr is valid.
+
   Device configuration layout The size of the console is supplied
   in the configuration space if the VIRTIO_CONSOLE_F_SIZE feature
   is set. Furthermore, if the VIRTIO_CONSOLE_F_MULTIPORT feature
   is set, the maximum number of ports supported by the device can
-  be fetched.struct virtio_console_config {
+  be fetched. If VIRTIO_CONSOLE_F_EMERG_WRITE is set then one can
+  use emergency write to output single character without initializing
+  virtio queues. struct virtio_console_config {
 
 	u16 cols;
 
@@ -1941,6 +1946,7 @@ Ports 2 onwards only if VIRTIO_CONSOLE_F_MULTIPORT is set
 
 	u32 max_nr_ports;
 
+	u32 emerg_wr;
 };
 
   Device Initialization
-- 
1.7.9.5



From pranavkumar at linaro.org  Mon May  6 08:19:51 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Mon,  6 May 2013 17:49:51 +0530
Subject: [PATCH V2 3/3] arm64: earlyprintk support for virtio-mmio console.
In-Reply-To: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
Message-ID: <1367842791-30285-4-git-send-email-pranavkumar@linaro.org>

This patch implements earlyprintk based on virtio console
using emerg_wr config register.

Kernel args for using this will be:
earlyprintk=virtio-console,<phys_address>

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
---
 arch/arm64/kernel/early_printk.c |   35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/kernel/early_printk.c b/arch/arm64/kernel/early_printk.c
index ac974f4..ea3d2f5 100644
--- a/arch/arm64/kernel/early_printk.c
+++ b/arch/arm64/kernel/early_printk.c
@@ -25,6 +25,9 @@
 
 #include <linux/amba/serial.h>
 #include <linux/serial_reg.h>
+#include <linux/virtio_ids.h>
+#include <linux/virtio_mmio.h>
+#include <linux/virtio_console.h>
 
 static void __iomem *early_base;
 static void (*printch)(char ch);
@@ -53,6 +56,37 @@ static void smh_printch(char ch)
 }
 
 /*
+ * VIRTIO MMIO console single character Tx.
+ */
+static void virtio_console_printch(char ch)
+{
+	u32 tmp;
+	static u32 init_done;
+	static u32 can_write;
+	struct virtio_console_config *p = early_base + VIRTIO_MMIO_CONFIG;
+
+	if (!init_done) {
+		tmp = readl_relaxed(early_base + VIRTIO_MMIO_DEVICE_ID);
+		if (tmp != VIRTIO_ID_CONSOLE) {
+			init_done = 1;
+			return;
+		}
+
+		tmp = readl_relaxed(early_base + VIRTIO_MMIO_HOST_FEATURES);
+		if (!(tmp & (1 << VIRTIO_CONSOLE_F_EMERG_WRITE))) {
+			init_done = 1;
+			return;
+		}
+
+		init_done = 1;
+		can_write = 1;
+	}
+
+	if (can_write)
+		writeb_relaxed(ch, &p->emerg_wr);
+}
+
+/*
  * 8250/16550 (8-bit aligned registers) single character TX.
  */
 static void uart8250_8bit_printch(char ch)
@@ -82,6 +116,7 @@ static const struct earlycon_match earlycon_match[] __initconst = {
 	{ .name = "smh", .printch = smh_printch, },
 	{ .name = "uart8250-8bit", .printch = uart8250_8bit_printch, },
 	{ .name = "uart8250-32bit", .printch = uart8250_32bit_printch, },
+	{ .name = "virtio-console", .printch = virtio_console_printch, },
 	{}
 };
 
-- 
1.7.9.5



From sebastian.hesselbarth at gmail.com  Mon May  6 08:32:13 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 14:32:13 +0200
Subject: [RFC patch 7/8] fixup 2/2: genirq: generic chip: Add linear irq
 domain support
In-Reply-To: <1367843533-7117-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20130503214629.810207749@linutronix.de>
 <1367843533-7117-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367843533-7117-2-git-send-email-sebastian.hesselbarth@gmail.com>

mask_cache pointer also needs to be initialized for domain generic
chips.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Gerlando Falauto <gerlando.falauto at keymile.com>
Cc: Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 kernel/irq/generic-chip.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 3dbfe2e..3e0312f 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -275,12 +275,22 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 
 	p += sizeof(*dgc) + numchips * sizeof(void *);
 	for (i = 0; i < numchips; i++) {
+		int k;
+
 		gc = (struct irq_chip_generic *)p;
 		dgc->gc[i] = gc;
 		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
 				      NULL, handler);
 		gc->domain = d;
 
+		for (k = 0; k < gc->num_ct; k++) {
+			struct irq_chip_type *ct = &gc->chip_types[k];
+			if (gcflags & IRQ_GC_MASK_CACHE_PER_TYPE)
+				ct->mask_cache = &ct->mask_cache_priv;
+			else
+				ct->mask_cache = &gc->mask_cache;
+		}
+
 		raw_spin_lock_irqsave(&gc_lock, flags);
 		list_add_tail(&gc->list, &gc_list);
 		raw_spin_unlock_irqrestore(&gc_lock, flags);
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 08:32:12 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 14:32:12 +0200
Subject: [RFC patch 7/8] fixup 1/2: genirq: generic chip: Add linear irq
 domain support
In-Reply-To: <20130503214629.810207749@linutronix.de>
References: <20130503214629.810207749@linutronix.de>
Message-ID: <1367843533-7117-1-git-send-email-sebastian.hesselbarth@gmail.com>

irq_domain_chip_generic is allocating and indexing irq_chip_generic
itself. However, the size of irq_chip_generic varies with number of
irq_chip_types. This fixup moves irq_chip_generic helt by
irq_domain_chip_generic to array of ptr and fixes the pointer arith
used by irq_alloc_domain_generic_chip.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Gerlando Falauto <gerlando.falauto at keymile.com>
Cc: Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 include/linux/irq.h       |    4 ++--
 kernel/irq/generic-chip.c |   20 +++++++++++++-------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 7315155..fd2d7cb 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -730,7 +730,7 @@ enum irq_gc_flags {
  * @irq_flags_to_set:	IRQ* flags to set on irq setup
  * @irq_flags_to_clear:	IRQ* flags to clear on irq setup
  * @gc_flags:		Generic chip specific setup flags
- * @gc:			Array of generic interrupt chips
+ * @gc:			Array of pointer to generic interrupt chips
  */
 struct irq_domain_chip_generic {
 	unsigned int		irqs_per_chip;
@@ -738,7 +738,7 @@ struct irq_domain_chip_generic {
 	unsigned int		irq_flags_to_clear;
 	unsigned int		irq_flags_to_set;
 	enum irq_gc_flags	gc_flags;
-	struct irq_chip_generic	gc[0];
+	struct irq_chip_generic	*gc[0];
 };
 
 /* Generic chip callback functions */
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index e212b26..3dbfe2e 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -247,6 +247,7 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 	struct irq_chip_generic *gc;
 	int numchips, sz, i;
 	unsigned long flags;
+	void *p;
 
 	if (d->gc)
 		return -EBUSY;
@@ -260,9 +261,9 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 
 	sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 	sz *= numchips;
-	sz += sizeof(*dgc);
+	sz += sizeof(*dgc) + numchips * sizeof(void *);
 
-	dgc = kzalloc(sz, GFP_KERNEL);
+	p = dgc = kzalloc(sz, GFP_KERNEL);
 	if (!dgc)
 		return -ENOMEM;
 	dgc->irqs_per_chip = irqs_per_chip;
@@ -270,17 +271,22 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 	dgc->irq_flags_to_set = set;
 	dgc->irq_flags_to_clear = clr;
 	dgc->gc_flags = gcflags;
-	gc = dgc->gc;
+	d->gc = dgc;
 
-	for (i = 0; i < numchips; i++, gc++) {
+	p += sizeof(*dgc) + numchips * sizeof(void *);
+	for (i = 0; i < numchips; i++) {
+		gc = (struct irq_chip_generic *)p;
+		dgc->gc[i] = gc;
 		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
 				      NULL, handler);
 		gc->domain = d;
+
 		raw_spin_lock_irqsave(&gc_lock, flags);
 		list_add_tail(&gc->list, &gc_list);
 		raw_spin_unlock_irqrestore(&gc_lock, flags);
+
+		p += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 	}
-	d->gc = dgc;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
@@ -301,7 +307,7 @@ irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
 	idx = hw_irq / dgc->irqs_per_chip;
 	if (idx >= dgc->num_chips)
 		return NULL;
-	return &dgc->gc[idx];
+	return dgc->gc[idx];
 }
 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
 
@@ -331,7 +337,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 	idx = hw_irq / dgc->irqs_per_chip;
 	if (idx >= dgc->num_chips)
 		return -EINVAL;
-	gc = &dgc->gc[idx];
+	gc = dgc->gc[idx];
 
 	idx = hw_irq % dgc->irqs_per_chip;
 
-- 
1.7.2.5



From pavel at denx.de  Mon May  6 08:48:14 2013
From: pavel at denx.de (Pavel Machek)
Date: Mon, 6 May 2013 14:48:14 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <20130426214313.GB24891@amd.pavel.ucw.cz>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <20130426124128.GB6946@page>
 <20130426213723.GA24891@amd.pavel.ucw.cz>
 <20130426214313.GB24891@amd.pavel.ucw.cz>
Message-ID: <20130506124814.GA28259@amd.pavel.ucw.cz>

Hi!

Ping? Previous version was tested by Dinh, and this one is based on
Jamie's updates, so I assume it is acceptable for him, too.

It brings two platforms closer together, and makes time actually work
on socfpga. It would be good to get it applied.

Thanks,
								Pavel

On Fri 2013-04-26 23:43:13, Pavel Machek wrote:
> It seems we made a mistake when creating dw_apb_timer_of.c:
> picoxcell sched_clock had parts that were not related to
> dw_apb_timer, yet we moved them to dw_apb_timer_of, and tried to
> use them on socfpga.
> 
> This results in system where user/system time is not measured
> properly, as demonstrated by
>     
>     time dd if=/dev/urandom of=/dev/zero bs=100000 count=100
>     
> So this patch switches sched_clock to hardware that exists on both
> platforms, and adds missing of_node_put() in dw_apb_timer_init().
>     
> Signed-off-by: Pavel Machek <pavel at denx.de>
> 
> diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
> index 481b42a..237fb3b 100644
> --- a/arch/arm/mach-picoxcell/common.h
> +++ b/arch/arm/mach-picoxcell/common.h
> @@ -12,6 +12,4 @@
>  
>  #include <asm/mach/time.h>
>  
> -extern void dw_apb_timer_init(void);
> -
>  #endif /* __PICOXCELL_COMMON_H__ */
> diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
> index 8c2a35f..460ac99 100644
> --- a/drivers/clocksource/dw_apb_timer.c
> +++ b/drivers/clocksource/dw_apb_timer.c
> @@ -21,12 +21,6 @@
>  #define APBT_MIN_PERIOD			4
>  #define APBT_MIN_DELTA_USEC		200
>  
> -#define APBTMR_N_LOAD_COUNT		0x00
> -#define APBTMR_N_CURRENT_VALUE		0x04
> -#define APBTMR_N_CONTROL		0x08
> -#define APBTMR_N_EOI			0x0c
> -#define APBTMR_N_INT_STATUS		0x10
> -
>  #define APBTMRS_INT_STATUS		0xa0
>  #define APBTMRS_EOI			0xa4
>  #define APBTMRS_RAW_INT_STATUS		0xa8
> diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
> index ab09ed3..0fa3104 100644
> --- a/drivers/clocksource/dw_apb_timer_of.c
> +++ b/drivers/clocksource/dw_apb_timer_of.c
> @@ -57,6 +57,15 @@ static void add_clockevent(struct device_node *event_timer)
>  	dw_apb_clockevent_register(ced);
>  }
>  
> +static void __iomem *sched_io_base;
> +
> +/* This is actually same as __apbt_read_clocksource(), but with
> +   different interface */
> +static u32 read_sched_clock_sptimer(void)
> +{
> +	return ~__raw_readl(sched_io_base + APBTMR_N_CURRENT_VALUE);
> +}
> +
>  static void add_clocksource(struct device_node *source_timer)
>  {
>  	void __iomem *iobase;
> @@ -71,41 +80,27 @@ static void add_clocksource(struct device_node *source_timer)
>  
>  	dw_apb_clocksource_start(cs);
>  	dw_apb_clocksource_register(cs);
> -}
>  
> -static void __iomem *sched_io_base;
> -
> -static u32 read_sched_clock(void)
> -{
> -	return __raw_readl(sched_io_base);
> +	sched_io_base = iobase;
> +	setup_sched_clock(read_sched_clock_sptimer, 32, rate);
>  }
>  
> -static const struct of_device_id sptimer_ids[] __initconst = {
> -	{ .compatible = "picochip,pc3x2-rtc" },
> +static const struct of_device_id osctimer_ids[] __initconst = {
> +	{ .compatible = "picochip,pc3x2-timer" },
> +	{ .compatible = "snps,dw-apb-timer-osc" },
>  	{ .compatible = "snps,dw-apb-timer-sp" },
> -	{ /* Sentinel */ },
> +	{  /* Sentinel */ },
>  };
>  
> -static void init_sched_clock(void)
> -{
> -	struct device_node *sched_timer;
> -	u32 rate;
> -
> -	sched_timer = of_find_matching_node(NULL, sptimer_ids);
> -	if (!sched_timer)
> -		panic("No RTC for sched clock to use");
> +/*
> +   You don't have to use dw_apb_timer for scheduler clock,
> +   this should also work fine on arm:
>  
> -	timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
> -	of_node_put(sched_timer);
> +  twd_local_timer_of_register();
> +  arch_timer_of_register();                 
> +  arch_timer_sched_clock_init();
> +*/
>  
> -	setup_sched_clock(read_sched_clock, 32, rate);
> -}
> -
> -static const struct of_device_id osctimer_ids[] __initconst = {
> -	{ .compatible = "picochip,pc3x2-timer" },
> -	{ .compatible = "snps,dw-apb-timer-osc" },
> -	{},
> -};
>  
>  void __init dw_apb_timer_init(void)
>  {
> @@ -121,7 +116,6 @@ void __init dw_apb_timer_init(void)
>  		panic("No timer for clocksource");
>  	add_clocksource(source_timer);
>  
> +	of_node_put(event_timer);
>  	of_node_put(source_timer);
> -
> -	init_sched_clock();
>  }
> diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
> index dd755ce..a64c987 100644
> --- a/include/linux/dw_apb_timer.h
> +++ b/include/linux/dw_apb_timer.h
> @@ -17,6 +17,12 @@
>  #include <linux/clocksource.h>
>  #include <linux/interrupt.h>
>  
> +#define APBTMR_N_LOAD_COUNT		0x00
> +#define APBTMR_N_CURRENT_VALUE		0x04
> +#define APBTMR_N_CONTROL		0x08
> +#define APBTMR_N_EOI			0x0c
> +#define APBTMR_N_INT_STATUS		0x10
> +
>  #define APBTMRS_REG_SIZE       0x14
>  
>  struct dw_apb_timer {
> 
> 

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From thomas.petazzoni at free-electrons.com  Mon May  6 08:52:25 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 6 May 2013 14:52:25 +0200
Subject: MVEBU PCI Express support
In-Reply-To: <5183F858.1050804@itooo.com>
References: <5183F858.1050804@itooo.com>
Message-ID: <20130506145225.67d04859@skate>

Dear Greg,

On Fri, 03 May 2013 19:48:08 +0200, Greg wrote:

> this one is targeted to the Free Electrons guys : should I start 
> investigating by myself or are you planning to release a patch for 
> supporting PCI express on Marvell Armada* platforms ?

We have already posted 8 versions of the PCIe patches on this list. The
last version is
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/161968.html.
However, this patch set has a few dependencies, so if you want
something ready-to-use even if not yet in mainline, I would recommend
you to have a look at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/backport-3.8.
This is a 3.8 vanilla kernel into which we have backported a number of
features/fixes, including the PCIe support.

We're hoping to get PCIe support in mainline for 3.11.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From tglx at linutronix.de  Mon May  6 09:25:18 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 6 May 2013 15:25:18 +0200 (CEST)
Subject: [RFC patch 7/8] fixup 1/2: genirq: generic chip: Add linear irq
 domain support
In-Reply-To: <1367843533-7117-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20130503214629.810207749@linutronix.de>
 <1367843533-7117-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <alpine.LFD.2.02.1305061524520.3095@ionos>

On Mon, 6 May 2013, Sebastian Hesselbarth wrote:

> irq_domain_chip_generic is allocating and indexing irq_chip_generic
> itself. However, the size of irq_chip_generic varies with number of
> irq_chip_types. This fixup moves irq_chip_generic helt by
> irq_domain_chip_generic to array of ptr and fixes the pointer arith
> used by irq_alloc_domain_generic_chip.

Thanks. I folded it in.


From tglx at linutronix.de  Mon May  6 09:31:58 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 6 May 2013 15:31:58 +0200 (CEST)
Subject: [RFC patch 7/8] fixup 2/2: genirq: generic chip: Add linear irq
 domain support
In-Reply-To: <1367843533-7117-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20130503214629.810207749@linutronix.de>
 <1367843533-7117-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367843533-7117-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <alpine.LFD.2.02.1305061525420.3095@ionos>

On Mon, 6 May 2013, Sebastian Hesselbarth wrote:

> mask_cache pointer also needs to be initialized for domain generic
> chips.

It's not only the mask cache pointer. We also need to initialize the
mask cache itself. I solved it by spitting out that code from
irq_setup_generic_chip().

Thanks,

	tglx




From arnd at arndb.de  Mon May  6 09:45:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 May 2013 15:45:22 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <20130506124814.GA28259@amd.pavel.ucw.cz>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <20130426214313.GB24891@amd.pavel.ucw.cz>
 <20130506124814.GA28259@amd.pavel.ucw.cz>
Message-ID: <201305061545.22587.arnd@arndb.de>

On Monday 06 May 2013, Pavel Machek wrote:
> 
> Hi!
> 
> Ping? Previous version was tested by Dinh, and this one is based on
> Jamie's updates, so I assume it is acceptable for him, too.
> 
> It brings two platforms closer together, and makes time actually work
> on socfpga. It would be good to get it applied.

Who should apply it? I guess it needs to go through arm-soc with all the
other clocksource changes already queued up there. Can we have an Ack
from Jamie and from the clocksource maintainers?

	Arnd


From tglx at linutronix.de  Mon May  6 10:30:16 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:16 -0000
Subject: [patch 0/8] genirq: Support for irq domains in generic irq chip - V2
In-Reply-To: <20130503212258.385818955@linutronix.de>
Message-ID: <20130506142348.321859745@linutronix.de>

Changes vs. V1:

	- Fixed the generic chip pointer thinko (Sebastian Hesselbarth)

	- Proper support for mask cache

	- Read mask hardware only for the first map of an generic chip
          instance

	- sun4i prefix irq functions proper  

Thanks,

	tglx




From tglx at linutronix.de  Mon May  6 10:30:21 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:21 -0000
Subject: [patch 3/8] genirq: generic chip: Handle separate mask registers
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.152569748@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:19 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:19 -0000
Subject: [patch 2/8] genirq: generic chip: Add support for per chip type mask
 cache
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.082226607@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:17 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:17 -0000
Subject: [patch 1/8] genirq: generic chip: Remove the local cur_regs() function
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.010164766@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:24 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:24 -0000
Subject: [patch 5/8] genirq: Add a mask calculation function
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.302898834@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:25 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:25 -0000
Subject: [patch 6/8] genirq: Split out code in generic chip
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.377017672@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:22 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:22 -0000
Subject: [patch 4/8] genirq: generic chip: Cache per irq bit mask 
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.227119865@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:28 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:28 -0000
Subject: [patch 8/8] irqchip: sun4i: Convert to generic irq chip
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.523110430@linutronix.de>

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From tglx at linutronix.de  Mon May  6 10:30:27 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 06 May 2013 14:30:27 -0000
Subject: [patch 7/8] genirq: generic chip: Add linear irq domain support
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
Message-ID: <20130506142539.450634298@linutronix.de>

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From konrad.wilk at oracle.com  Mon May  6 10:35:33 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Mon, 6 May 2013 10:35:33 -0400
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <5182DBA9.9080609@codeaurora.org>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
Message-ID: <20130506143533.GF15278@phenom.dumpdata.com>

> > e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
> > would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
> > where the timer goes off. Nor does it make sense to require that the
> > guest actually be running for 5 before injecting the timer because that
> > would mean real time elapsed time for the timer would be 5+3 in the case
> > where 3 are stolen.
> 
> This is a bit of an aside, but I think that hiding time spent at higher
> privilege levels can be a quite sensible approach to timekeeping in a
> virtualized environment, but I understand that it's not the approach taken
> with Xen, and as you pointed out above, adjusting the Virtual Offset Register
> by itself isn't enough to implement that approach.

This is the approach taken by Xen and KVM. Look in CONFIG_PARAVIRT_CLOCK for
implementation. In the user-space, the entry in 'top' of "stolen" (%st)
is for this exact value.


From stefano.stabellini at eu.citrix.com  Mon May  6 10:50:22 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 May 2013 15:50:22 +0100
Subject: [PATCH RFC v2 0/4] xen/arm: CONFIG_PARAVIRT and stolen ticks
 accounting
Message-ID: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>

Hi all,
this patch series introduces stolen ticks accounting for Xen on ARM.
Stolen ticks are clocksource ticks that have been "stolen" from the cpu,
typically because Linux is running in a virtual machine and the vcpu has
been descheduled.
To account for these ticks we introduce CONFIG_PARAVIRT and pv_time_ops
so that we can make use of:

kernel/sched/cputime.c:steal_account_process_tick



Stefano Stabellini (4):
      xen: move xen_setup_runstate_info and get_runstate_snapshot to drivers/xen/time.c
      arm: introduce CONFIG_PARAVIRT and pv_time_ops
      kernel: missing include in cputime.c
      xen/arm: account for stolen ticks

 arch/arm/Kconfig                |    9 ++++
 arch/arm/include/asm/paravirt.h |   19 ++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   32 ++++++++++++++
 arch/arm/xen/enlighten.c        |   23 ++++++++++
 arch/ia64/xen/time.c            |   48 +++------------------
 arch/x86/xen/time.c             |   76 +--------------------------------
 drivers/xen/Makefile            |    2 +-
 drivers/xen/time.c              |   91 +++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h           |    5 ++
 kernel/sched/cputime.c          |    1 +
 11 files changed, 189 insertions(+), 118 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c
 create mode 100644 drivers/xen/time.c



Cheers,

Stefano


From stefano.stabellini at eu.citrix.com  Mon May  6 10:51:17 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 May 2013 15:51:17 +0100
Subject: [PATCH RFC v2 3/4] kernel: missing include in cputime.c
In-Reply-To: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
Message-ID: <1367851878-21629-3-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: mingo at redhat.com
CC: peterz at infradead.org
---
 kernel/sched/cputime.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
index ed12cbb..488a5bf 100644
--- a/kernel/sched/cputime.c
+++ b/kernel/sched/cputime.c
@@ -5,6 +5,7 @@
 #include <linux/static_key.h>
 #include <linux/context_tracking.h>
 #include "sched.h"
+#include <asm/paravirt.h>
 
 
 #ifdef CONFIG_IRQ_TIME_ACCOUNTING
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon May  6 10:51:18 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 May 2013 15:51:18 +0100
Subject: [PATCH RFC v2 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
Message-ID: <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>

Register the runstate_memory_area with the hypervisor.
Use pv_time_ops.steal_clock to account for stolen ticks.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index ee86bfa..2a5cc82 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -14,7 +14,10 @@
 #include <xen/xen-ops.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <asm/arch_timer.h>
 #include <asm/system_misc.h>
+#include <asm/paravirt.h>
+#include <linux/jump_label.h>
 #include <linux/interrupt.h>
 #include <linux/irqreturn.h>
 #include <linux/module.h>
@@ -152,6 +155,20 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
 }
 EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 
+unsigned long long xen_stolen_accounting(int cpu)
+{
+	struct vcpu_runstate_info state;
+
+	if (cpu != get_cpu())
+		BUG();
+
+	xen_get_runstate_snapshot(&state);
+
+	WARN_ON(state.state != RUNSTATE_running);
+
+	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
+}
+
 static void __init xen_percpu_init(void *unused)
 {
 	struct vcpu_register_vcpu_info info;
@@ -170,6 +187,8 @@ static void __init xen_percpu_init(void *unused)
 		BUG();
 	per_cpu(xen_vcpu, cpu) = vcpup;
 
+	xen_setup_runstate_info(cpu);
+
 	enable_percpu_irq(xen_events_irq, 0);
 }
 
@@ -301,6 +320,10 @@ static int __init xen_init_events(void)
 
 	on_each_cpu(xen_percpu_init, NULL, 0);
 
+	pv_time_ops.steal_clock = xen_stolen_accounting;
+	static_key_slow_inc(&paravirt_steal_enabled);
+	static_key_slow_inc(&paravirt_steal_rq_enabled);
+
 	return 0;
 }
 postcore_initcall(xen_init_events);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon May  6 10:51:16 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 May 2013 15:51:16 +0100
Subject: [PATCH RFC v2 2/4] arm: introduce CONFIG_PARAVIRT and pv_time_ops
In-Reply-To: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
Message-ID: <1367851878-21629-2-git-send-email-stefano.stabellini@eu.citrix.com>

Introduce CONFIG_PARAVIRT on ARM.

The only paravirt interface supported is pv_time_ops.steal_clock.
No runtime pvops patching yet.

This allows us to make us of steal_account_process_tick for stolen ticks
accounting.


Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: linux at arm.linux.org.uk
CC: will.deacon at arm.com
CC: nico at linaro.org
CC: marc.zyngier at arm.com
CC: cov at codeaurora.org
CC: arnd at arndb.de
CC: olof at lixom.net
---
 arch/arm/Kconfig                |    9 +++++++++
 arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   32 ++++++++++++++++++++++++++++++++
 4 files changed, 61 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 344e299..35cb10a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1887,12 +1887,21 @@ config XEN_DOM0
 	def_bool y
 	depends on XEN
 
+config PARAVIRT
+	bool "Enable paravirtualization code"
+	---help---
+	  This changes the kernel so it can modify itself when it is run
+	  under a hypervisor, potentially improving performance significantly
+	  over full virtualization.  However, when run without a hypervisor
+	  the kernel is theoretically slower and slightly larger.
+
 config XEN
 	bool "Xen guest support on ARM (EXPERIMENTAL)"
 	depends on ARM && AEABI && OF
 	depends on CPU_V7 && !CPU_V6
 	depends on !GENERIC_ATOMIC64
 	select ARM_PSCI
+	select PARAVIRT
 	help
 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
diff --git a/arch/arm/include/asm/paravirt.h b/arch/arm/include/asm/paravirt.h
new file mode 100644
index 0000000..3b95bc6
--- /dev/null
+++ b/arch/arm/include/asm/paravirt.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_PARAVIRT_H
+#define _ASM_ARM_PARAVIRT_H
+
+struct static_key;
+extern struct static_key paravirt_steal_enabled;
+extern struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops {
+	unsigned long long (*steal_clock)(int cpu);
+};
+extern struct pv_time_ops pv_time_ops;
+
+static inline u64 paravirt_steal_clock(int cpu)
+{
+	return pv_time_ops.steal_clock(cpu);
+}
+
+
+#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index dd9d90a..6764f60 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -86,5 +86,6 @@ ifeq ($(CONFIG_ARM_PSCI),y)
 obj-y				+= psci.o
 obj-$(CONFIG_SMP)		+= psci_smp.o
 endif
+obj-$(CONFIG_PARAVIRT)	+= paravirt.o
 
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/paravirt.c b/arch/arm/kernel/paravirt.c
new file mode 100644
index 0000000..3e73fc8
--- /dev/null
+++ b/arch/arm/kernel/paravirt.c
@@ -0,0 +1,32 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 Citrix Systems
+ *
+ * Author: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
+ */
+
+#include <linux/export.h>
+#include <linux/jump_label.h>
+#include <linux/types.h>
+#include <asm/paravirt.h>
+
+struct static_key paravirt_steal_enabled;
+struct static_key paravirt_steal_rq_enabled;
+
+static u64 native_steal_clock(int cpu)
+{
+	return 0;
+}
+
+struct pv_time_ops pv_time_ops = {
+	.steal_clock = native_steal_clock,
+};
+EXPORT_SYMBOL_GPL(pv_time_ops);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon May  6 10:51:15 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 May 2013 15:51:15 +0100
Subject: [PATCH RFC v2 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
Message-ID: <1367851878-21629-1-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:
- leave do_stolen_accounting in arch/x86/xen/time.c;
- use the new common functions in arch/ia64/xen/time.c.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell at citrix.com>
CC: konrad.wilk at oracle.com
---
 arch/ia64/xen/time.c  |   48 +++----------------------
 arch/x86/xen/time.c   |   76 +----------------------------------------
 drivers/xen/Makefile  |    2 +-
 drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h |    5 +++
 5 files changed, 104 insertions(+), 118 deletions(-)
 create mode 100644 drivers/xen/time.c

diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
index 1f8244a..79a0b8c 100644
--- a/arch/ia64/xen/time.c
+++ b/arch/ia64/xen/time.c
@@ -34,53 +34,17 @@
 
 #include "../kernel/fsyscall_gtod_data.h"
 
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
 static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
 static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
 
 /* taken from i386/kernel/time-xen.c */
 static void xen_init_missing_ticks_accounting(int cpu)
 {
-	struct vcpu_register_runstate_memory_area area;
-	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
-	int rc;
+	xen_setup_runstate_info(&runstate);
 
-	memset(runstate, 0, sizeof(*runstate));
-
-	area.addr.v = runstate;
-	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
-				&area);
-	WARN_ON(rc && rc != -ENOSYS);
-
-	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
-	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
-					    + runstate->time[RUNSTATE_offline];
-}
-
-/*
- * Runstate accounting
- */
-/* stolen from arch/x86/xen/time.c */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = state->state_entry_time;
-		rmb();
-		*res = *state;
-		rmb();
-	} while (state->state_entry_time != state_time);
+	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
+	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
+					    + runstate.time[RUNSTATE_offline];
 }
 
 #define NS_PER_TICK (1000000000LL/HZ)
@@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
 	struct vcpu_runstate_info runstate;
 	struct task_struct *p = current;
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	/*
 	 * Check for vcpu migration effect
@@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
 	 */
 	now = ia64_native_sched_clock();
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	WARN_ON(runstate.state != RUNSTATE_running);
 
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 0296a95..18d0104 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -30,9 +30,6 @@
 #define TIMER_SLOP	100000
 #define NS_PER_TICK	(1000000000LL / HZ)
 
-/* runstate info updated by Xen */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
-
 /* snapshots of runstate info */
 static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 
@@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 static DEFINE_PER_CPU(u64, xen_residual_stolen);
 static DEFINE_PER_CPU(u64, xen_residual_blocked);
 
-/* return an consistent snapshot of 64-bit time/counter value */
-static u64 get64(const u64 *p)
-{
-	u64 ret;
-
-	if (BITS_PER_LONG < 64) {
-		u32 *p32 = (u32 *)p;
-		u32 h, l;
-
-		/*
-		 * Read high then low, and then make sure high is
-		 * still the same; this will only loop if low wraps
-		 * and carries into high.
-		 * XXX some clean way to make this endian-proof?
-		 */
-		do {
-			h = p32[1];
-			barrier();
-			l = p32[0];
-			barrier();
-		} while (p32[1] != h);
-
-		ret = (((u64)h) << 32) | l;
-	} else
-		ret = *p;
-
-	return ret;
-}
-
-/*
- * Runstate accounting
- */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = get64(&state->state_entry_time);
-		barrier();
-		*res = *state;
-		barrier();
-	} while (get64(&state->state_entry_time) != state_time);
-}
-
-/* return true when a vcpu could run but has no real cpu to run on */
-bool xen_vcpu_stolen(int vcpu)
-{
-	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
-}
-
-void xen_setup_runstate_info(int cpu)
-{
-	struct vcpu_register_runstate_memory_area area;
-
-	area.addr.v = &per_cpu(xen_runstate, cpu);
-
-	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
-			       cpu, &area))
-		BUG();
-}
-
 static void do_stolen_accounting(void)
 {
 	struct vcpu_runstate_info state;
@@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
 	s64 blocked, runnable, offline, stolen;
 	cputime_t ticks;
 
-	get_runstate_snapshot(&state);
+	xen_get_runstate_snapshot(&state);
 
 	WARN_ON(state.state != RUNSTATE_running);
 
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index eabd0ee..2bf461a 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -3,7 +3,7 @@ obj-y	+= manage.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 endif
 obj-$(CONFIG_X86)			+= fallback.o
-obj-y	+= grant-table.o features.o events.o balloon.o
+obj-y	+= grant-table.o features.o events.o balloon.o time.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
diff --git a/drivers/xen/time.c b/drivers/xen/time.c
new file mode 100644
index 0000000..c2e39d3
--- /dev/null
+++ b/drivers/xen/time.c
@@ -0,0 +1,91 @@
+/*
+ * Xen stolen ticks accounting.
+ */
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/math64.h>
+#include <linux/gfp.h>
+
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+
+#include <xen/events.h>
+#include <xen/features.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/vcpu.h>
+#include <xen/xen-ops.h>
+
+/* runstate info updated by Xen */
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
+
+/* return an consistent snapshot of 64-bit time/counter value */
+static u64 get64(const u64 *p)
+{
+	u64 ret;
+
+	if (BITS_PER_LONG < 64) {
+		u32 *p32 = (u32 *)p;
+		u32 h, l;
+
+		/*
+		 * Read high then low, and then make sure high is
+		 * still the same; this will only loop if low wraps
+		 * and carries into high.
+		 * XXX some clean way to make this endian-proof?
+		 */
+		do {
+			h = p32[1];
+			barrier();
+			l = p32[0];
+			barrier();
+		} while (p32[1] != h);
+
+		ret = (((u64)h) << 32) | l;
+	} else
+		ret = *p;
+
+	return ret;
+}
+
+/*
+ * Runstate accounting
+ */
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
+{
+	u64 state_time;
+	struct vcpu_runstate_info *state;
+
+	BUG_ON(preemptible());
+
+	state = &__get_cpu_var(xen_runstate);
+
+	/*
+	 * The runstate info is always updated by the hypervisor on
+	 * the current CPU, so there's no need to use anything
+	 * stronger than a compiler barrier when fetching it.
+	 */
+	do {
+		state_time = get64(&state->state_entry_time);
+		barrier();
+		*res = *state;
+		barrier();
+	} while (get64(&state->state_entry_time) != state_time);
+}
+
+/* return true when a vcpu could run but has no real cpu to run on */
+bool xen_vcpu_stolen(int vcpu)
+{
+	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
+}
+
+void xen_setup_runstate_info(int cpu)
+{
+	struct vcpu_register_runstate_memory_area area;
+
+	area.addr.v = &per_cpu(xen_runstate, cpu);
+
+	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
+			       cpu, &area))
+		BUG();
+}
+
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index d6fe062..4fd4e47 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -3,6 +3,7 @@
 
 #include <linux/percpu.h>
 #include <asm/xen/interface.h>
+#include <xen/interface/vcpu.h>
 
 DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
 
@@ -16,6 +17,10 @@ void xen_mm_unpin_all(void);
 void xen_timer_resume(void);
 void xen_arch_resume(void);
 
+bool xen_vcpu_stolen(int vcpu);
+void xen_setup_runstate_info(int cpu);
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res);
+
 int xen_setup_shutdown_event(void);
 
 extern unsigned long *xen_contiguous_bitmap;
-- 
1.7.2.5



From cov at codeaurora.org  Mon May  6 10:55:39 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 06 May 2013 10:55:39 -0400
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <alpine.DEB.2.02.1305051745390.4756@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
 <alpine.DEB.2.02.1305031130210.5398@kaball.uk.xensource.com>
 <5183976A.6000703@arm.com>
 <alpine.DEB.2.02.1305051745390.4756@kaball.uk.xensource.com>
Message-ID: <5187C46B.5070309@codeaurora.org>

On 05/05/2013 12:47 PM, Stefano Stabellini wrote:
> On Fri, 3 May 2013, Marc Zyngier wrote:
>> On 03/05/13 11:43, Stefano Stabellini wrote:
>>> On Thu, 2 May 2013, Christopher Covington wrote:
>>>>> So the virtual timer should appear to have been running even while time
>>>>> is being stolen and therefore stolen time needs to be accounted via some
>>>>> other means.
>>>>
>>>> Something that's not currently obvious to me is that given that the stolen
>>>> cycle accounting should be done, what makes the architected timer interrupt
>>>> handler the ideal place to do it?
>>>
>>> That is a good question and I would appreciate suggestions to improve
>>> the patch.
>>>
>>> Given that Xen x86 and ia64 does stolen time accounting from the timer
>>> interrupt handler:
>>>
>>> arch/x86/xen/time.c:xen_timer_interrupt
>>> arch/ia64/kernel/time.c:timer_interrupt
>>>
>>> and given that the arch_timer is the only timer used by Xen on ARM and
>>> that it includes a virt_timer that is made on purpose to be used by
>>> virtual machines, I thought that it might be a good place for it.
>>>
>>> I also thought that doing it this way, KVM should be able to reuse the
>>> same hook.
>>
>> Indeed. I just need to understand how time stealing works there ;-).
>>
>> Now, KVM is not necessarily limited to arch_timers, and we've run KVM
>> using a QEMU-provided timer in the past. Can you think of a more generic
>> location for this hook? Possibly something that would satisfy the
>> requirements of other architectures while we're at it?
> 
> Probably the best option would be to reuse
> 
> kernel/sched/cputime.c:steal_account_process_tick
> 
> but that also means introducing CONFIG_PARAVIRT on arm.
> I am up for that, what do you think?

That sounds like a good move to me.

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From itooo at itooo.com  Mon May  6 10:58:04 2013
From: itooo at itooo.com (Greg)
Date: Mon, 06 May 2013 16:58:04 +0200
Subject: MVEBU PCI Express support
In-Reply-To: <20130506145225.67d04859@skate>
References: <5183F858.1050804@itooo.com> <20130506145225.67d04859@skate>
Message-ID: <5187C4FC.20504@itooo.com>

Le 06/05/2013 14:52, Thomas Petazzoni a ?crit :
> Dear Greg,
>
> On Fri, 03 May 2013 19:48:08 +0200, Greg wrote:
>
>> this one is targeted to the Free Electrons guys : should I start
>> investigating by myself or are you planning to release a patch for
>> supporting PCI express on Marvell Armada* platforms ?
> We have already posted 8 versions of the PCIe patches on this list. The
> last version is
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/161968.html.
> However, this patch set has a few dependencies, so if you want
> something ready-to-use even if not yet in mainline, I would recommend
> you to have a look at
> https://github.com/MISL-EBU-System-SW/mainline-public/tree/backport-3.8.
> This is a 3.8 vanilla kernel into which we have backported a number of
> features/fixes, including the PCIe support.
>
> We're hoping to get PCIe support in mainline for 3.11.
> Thanks Thomas,

Sorry I'm not yet very familiar with all this (patches, repos, 
backports, branches, ...).
I'll give a try to the backport you suggest and, hopefully, get back to 
you with some feedback.

Cheers,



From nicolas.pitre at linaro.org  Mon May  6 11:05:28 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 6 May 2013 11:05:28 -0400 (EDT)
Subject: [RFC PATCH v2] drivers: bus: add ARM CCI support
In-Reply-To: <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
References: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <alpine.LFD.2.03.1305011239240.11070@syhkavp.arg>

Review comments below.

On Wed, 1 May 2013, Lorenzo Pieralisi wrote:

> index 0000000..fb9e8e0
> --- /dev/null
> +++ b/drivers/bus/arm-cci.c
> @@ -0,0 +1,372 @@
> +/*
> + * CCI cache coherent interconnect driver
> + *
> + * Copyright (C) 2013 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/arm-cci.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <asm/cacheflush.h>
> +#include <asm/dt_affinity.h>
> +#include <asm/outercache.h>

You don't need this include anymore.

> +#include <asm/smp_plat.h>
> +
> +#define DRIVER_NAME		"CCI"
> +
> +#define CCI_PORT_CTRL		0x0
> +#define CCI_CTRL_STATUS		0xc
> +
> +#define CCI_ENABLE_SNOOP_REQ	0x1
> +#define CCI_ENABLE_DVM_REQ	0x2
> +#define CCI_ENABLE_REQ		(CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
> +
> +struct cci_nb_ports {
> +	unsigned int nb_ace;
> +	unsigned int nb_ace_lite;
> +};
> +
> +enum cci_ace_port_type {
> +	ACE_INVALID_PORT = 0x0,
> +	ACE_PORT,
> +	ACE_LITE_PORT,
> +};
> +
> +struct cci_ace_port {
> +	void __iomem *base;
> +	int type;

You could use: enum cci_ace_port_type type;

> +	struct device_node *dn;
> +};
> +
> +static struct cci_ace_port *ports;
> +static unsigned int nb_cci_ports;
> +
> +static void __iomem *cci_ctrl_base;
> +#define INVALID_PORT_IDX	-1
> +static int cpu_port[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_PORT_IDX };
> +
> +/*
> + * __cci_ace_get_port - Function to retrieve the port index connected to
> + *			a cpu or device.
> + *
> + * @dn = device node of the device to look-up
> + * @type = port type
> + *
> + * Return value:
> + *	- CCI port index if success
> + *	- -ENODEV if failure
> + */
> +static int __cci_ace_get_port(struct device_node *dn, int type)
> +{
> +	int i;
> +	bool ace_match;
> +	struct device_node *cci_portn;
> +
> +	cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
> +	for (i = 0; i < nb_cci_ports; i++) {
> +		ace_match = ports[i].type == type;
> +		if (ace_match && cci_portn == ports[i].dn)
> +			return i;
> +	}
> +	return -ENODEV;
> +}
> +
> +int cci_ace_get_port(struct device_node *dn)
> +{
> +	return __cci_ace_get_port(dn, ACE_LITE_PORT);
> +}
> +EXPORT_SYMBOL_GPL(cci_ace_get_port);
> +
> +static void __init cci_ace_init_ports(void)
> +{
> +	int port, ac, cpu;
> +	u64 hwid;
> +	const u32 *cell;
> +	struct device_node *cpun, *cpus;
> +
> +	cpus = of_find_node_by_path("/cpus");
> +	if (WARN(!cpus, "Missing cpus node, bailing out\n"))
> +		return;
> +
> +	if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
> +		ac = of_n_addr_cells(cpus);
> +	/*
> +	 * Port index look-up speeds up the function disabling ports by CPU,
> +	 * since the logical to port index mapping is done once and does
> +	 * not change after system boot.
> +	 * The stashed index array is initialized for all possible CPUs
> +	 * at probe time.
> +	 */
> +	for_each_child_of_node(cpus, cpun) {
> +		if (of_node_cmp(cpun->type, "cpu"))
> +			continue;
> +		cell = of_get_property(cpun, "reg", NULL);
> +		if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
> +			continue;
> +		hwid = of_read_number(cell, ac);
> +		cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
> +		if (cpu < 0)
> +			continue;
> +		port = __cci_ace_get_port(cpun, ACE_PORT);
> +		if (port < 0)
> +			continue;
> +		cpu_port[cpu] = port;
> +	}
> +
> +	for_each_possible_cpu(cpu) {
> +		WARN(cpu_port[cpu] == INVALID_PORT_IDX, "CPU %d has an invalid CCI port index\n",
> +							cpu);
> +	}
> +}
> +
> +/*
> + * Functions to enable/disable a CCI interconnect slave port
> + *
> + * They are called by low-level power management code to disable slave
> + * interfaces snoops and DVM broadcast.
> + * Since they may execute with cache data allocation disabled and
> + * after the caches have been cleaned and invalidated the functions provide
> + * no explicit locking since they may run with D-cache disabled, so normal
> + * cacheable kernel locks based on ldrex/strex may not work.
> + * Locking has to be provided by BSP implementations to ensure proper
> + * operations.
> + */
> +
> +/*
> + * cci_port_control()
> + *	@port = index of the port to setup
> + *	@enable = if true enables the port, if false disables it
> + */
> +static void notrace cci_port_control(unsigned int port, bool enable)
> +{
> +	void __iomem *base = ports[port].base;
> +
> +	writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
> +	/*
> +	 * This function is called from power down procedures
> +	 * and must not execute any instruction that might
> +	 * cause the processor to be put in a quiescent state
> +	 * (eg wfi). Hence, cpu_relax() can not be added to this
> +	 * read loop to optimize power, since it might hide possibly
> +	 * disruptive operations.
> +	 */
> +	while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
> +			;
> +}
> +
> +/*
> + * cci_disable_port_by_cpu()
> + *	@mpidr = mpidr of the CPU whose CCI port should be disabled
> + *	Returns:
> + *		0 on success
> + *		-ENODEV on port look-up failure
> + *
> + * Disabling a CCI port for a CPU implies disabling the CCI port
> + * controlling that CPU cluster. Code disabling CPU CCI ports
> + * must make sure that the CPU running the code is the last active CPU
> + * in the cluster ie all other CPUs are quiescent in a low power state.
> + */
> +int notrace cci_disable_port_by_cpu(u64 mpidr)
> +{
> +	int cpu = get_logical_index(mpidr & MPIDR_HWID_BITMASK);

This is dangerous.  Same reasoning for not using cpu_relax() above 
should apply here too.  Better avoid any external calls and cache things 
locally by marking cpu_port[] entries with MPIDR values directly.

Furthermore, get_logical_index() might not be reliable when the cache or 
local coherency is off.  We'd have to flush all the data it might access 
to RAM just like it is done for our very own data structures in this 
code, but starting doing that outside of this driver would become rather 
ugly.

> +	if (cpu < 0 || cpu_port[cpu] == INVALID_PORT_IDX)
> +		return -ENODEV;
> +	cci_port_control(cpu_port[cpu], false);
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
> +
> +/*
> + * __cci_control_port_by_device()
> + *	@dn = device node pointer of the device whose CCI port should be
> + *	      controlled
> + *	@enable = if true enables the port, if false disables it
> + *	Returns:
> + *		0 on success
> + *		-ENODEV on port look-up failure
> + */
> +int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
> +{
> +	int port;
> +
> +	if (!dn)
> +		return -ENODEV;
> +
> +	port = __cci_ace_get_port(dn, ACE_LITE_PORT);
> +	if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
> +				dn->full_name))
> +		return -ENODEV;
> +	cci_port_control(port, enable);
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
> +
> +/*
> + * __cci_control_port_by_index()
> + *	@port = port index previously retrieved with cci_ace_get_port()
> + *	@enable = if true enables the port, if false disables it
> + *	Returns:
> + *		0 on success
> + *		-ENODEV on port index out of range
> + *		-EPERM if operation carried out on an ACE PORT
> + */
> +int notrace __cci_control_port_by_index(u32 port, bool enable)
> +{
> +	if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
> +		return -ENODEV;
> +	/*
> +	 * CCI control for ports connected to CPUS is extremely fragile
> +	 * and must be made to go through a specific and controlled
> +	 * interface (ie cci_disable_port_by_cpu(); control by general purpose
> +	 * indexing is therefore disabled for ACE ports.
> +	 */
> +	if (ports[port].type == ACE_PORT)
> +		return -EPERM;
> +
> +	cci_port_control(port, enable);
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
> +
> +static const struct cci_nb_ports cci400_ports = {
> +	.nb_ace = 2,
> +	.nb_ace_lite = 3
> +};
> +
> +static const struct of_device_id arm_cci_matches[] = {
> +	{.compatible = "arm,cci-400", .data = &cci400_ports },
> +	{},
> +};
> +
> +static int __init cci_driver_probe(struct platform_device *pdev)
> +{
> +	const struct of_device_id *match;
> +	struct cci_nb_ports const *cci_config;
> +	int ret, i, nb_ace = 0, nb_ace_lite = 0;
> +	struct device_node *np, *cp;
> +	const char *match_str;
> +	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	match = of_match_device(arm_cci_matches, &pdev->dev);
> +
> +	if (!match)
> +		return -ENODEV;
> +
> +	cci_config = (struct cci_nb_ports const *)match->data;
> +	nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
> +	ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
> +	if (!ports)
> +		return -ENOMEM;
> +
> +	np = pdev->dev.of_node;
> +
> +	cci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
> +
> +	if (!cci_ctrl_base) {
> +		dev_err(&pdev->dev, "unable to ioremap CCI ctrl\n");
> +		ret = -ENXIO;
> +		goto memalloc_err;
> +	}
> +
> +	for_each_child_of_node(np, cp) {
> +		i = nb_ace + nb_ace_lite;
> +
> +		if (i >= nb_cci_ports)
> +			break;
> +
> +		if (of_property_read_string(cp, "interface-type",
> +					    &match_str)) {
> +			dev_err(&pdev->dev, "node %s missing interface-type property\n",
> +				  cp->full_name);
> +			continue;
> +		}
> +
> +		if (strcmp(match_str, "ace")
> +				&& strcmp(match_str, "ace-lite")) {
> +			dev_err(&pdev->dev, "node %s containing invalid interface-type property, skipping it\n",
> +					cp->full_name);
> +			continue;
> +		}
> +
> +		if (of_address_to_resource(cp, 0, res)) {
> +			dev_err(&pdev->dev, "node %s failure in retrieving resources\n",
> +				cp->full_name);
> +			continue;
> +		}
> +
> +		ports[i].base = devm_request_and_ioremap(&pdev->dev, res);
> +
> +		if (!ports[i].base) {
> +			dev_err(&pdev->dev, "unable to ioremap CCI port %d\n",
> +					    i);
> +			continue;
> +		}
> +
> +		if (!strcmp(match_str, "ace")) {
> +			if (WARN_ON(nb_ace >= cci_config->nb_ace))
> +				continue;
> +			ports[i].type = ACE_PORT;
> +			++nb_ace;
> +		} else if (!strcmp(match_str, "ace-lite")) {
> +			if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
> +				continue;
> +			ports[i].type = ACE_LITE_PORT;
> +			++nb_ace_lite;
> +		}
> +		ports[i].dn = cp;
> +	}
> +	 /* initialize a stashed array of ACE ports to speed-up look-up */
> +	cci_ace_init_ports();
> +
> +	/*
> +	 * Multi-cluster systems may need this data when non-coherent, during
> +	 * cluster power-up/power-down. Make sure it reaches main memory.
> +	 */
> +	sync_cache_w(&cci_ctrl_base);
> +	__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);

This is not enough to flush the cache for the memory referenced by the 
ports pointer.  The pointer value itself has to be flushed to RAM as 
well.

> +	__sync_cache_range_w(cpu_port, sizeof cpu_port);

You might be able to use sync_cache_w(&cpu_port) here instead given it 
is a fixed size array object.

> +	dev_info(&pdev->dev, "ARM CCI driver probed\n");
> +	return 0;
> +
> +memalloc_err:
> +
> +	kfree(ports);
> +	return ret;
> +}
> +
> +static struct platform_driver cci_platform_driver = {
> +	.driver = {
> +		   .owner = THIS_MODULE,
> +		   .name = DRIVER_NAME,
> +		   .of_match_table = arm_cci_matches,
> +	},
> +};
> +/*
> + * CCI is inherently a non-hotpluggable device, since it represents
> + * the CPUs access point to the interconnect system.
> + */
> +static int __init cci_init(void)
> +{
> +	return platform_driver_probe(&cci_platform_driver, cci_driver_probe);
> +}
> +
> +module_init(cci_init);

When compiled in, module_init() is translated into device_initcall().  
This is way too late for bringing up secondary CPUs during boot via the 
MCPM layer.  That is not an issue as far as the code presented here is 
concerned since there is no integration with MCPM yet, but eventually 
we'd want the MCPM power_up_setup method to integrate with the port 
discovery performed here instead of having them hardcoded in the 
assembly code.  This means it would have to become early_initcall() 
instead.  And at that point the driver infrastructure isn't fully 
operational, meaning that driver_probe() won't be usable either (looking 
at what we did to the TC2 spc init code is a good example of what I mean 
here).


Nicolas


From robherring2 at gmail.com  Mon May  6 11:18:05 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 06 May 2013 10:18:05 -0500
Subject: [patch 8/8] irqchip: sun4i: Convert to generic irq chip
In-Reply-To: <20130506142539.523110430@linutronix.de>
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
 <20130506142539.523110430@linutronix.de>
Message-ID: <5187C9AD.3080409@gmail.com>

On 05/06/2013 09:30 AM, Thomas Gleixner wrote:
> Proof of concept patch to demonstrate the new irqdomain support for
> the generic irq chip. Untested !!
> 
> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>
> Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  drivers/irqchip/irq-sun4i.c |  100 ++++++++++++--------------------------------
>  1 file changed, 29 insertions(+), 71 deletions(-)
> 
> Index: linux-2.6/drivers/irqchip/irq-sun4i.c
> ===================================================================
> --- linux-2.6.orig/drivers/irqchip/irq-sun4i.c
> +++ linux-2.6/drivers/irqchip/irq-sun4i.c
> @@ -32,70 +32,43 @@
>  #define SUN4I_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
>  #define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
>  #define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
> +#define SUN4I_NUM_CHIPS			3
> +#define SUN4I_IRQS_PER_CHIP		32
>  
>  static void __iomem *sun4i_irq_base;
>  static struct irq_domain *sun4i_irq_domain;
>  
>  static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
>  
> -void sun4i_irq_ack(struct irq_data *irqd)
> +static int __init sun4i_init_domain_chips(void)
>  {
> -	unsigned int irq = irqd_to_hwirq(irqd);
> -	unsigned int irq_off = irq % 32;
> -	int reg = irq / 32;
> -	u32 val;
> -
> -	val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
> -	writel(val | (1 << irq_off),
> -	       sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
> -}
> -
> -static void sun4i_irq_mask(struct irq_data *irqd)
> -{
> -	unsigned int irq = irqd_to_hwirq(irqd);
> -	unsigned int irq_off = irq % 32;
> -	int reg = irq / 32;
> -	u32 val;
> -
> -	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> -	writel(val & ~(1 << irq_off),
> -	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> -}
> -
> -static void sun4i_irq_unmask(struct irq_data *irqd)
> -{
> -	unsigned int irq = irqd_to_hwirq(irqd);
> -	unsigned int irq_off = irq % 32;
> -	int reg = irq / 32;
> -	u32 val;
> -
> -	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> -	writel(val | (1 << irq_off),
> -	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> -}
> -
> -static struct irq_chip sun4i_irq_chip = {
> -	.name		= "sun4i_irq",
> -	.irq_ack	= sun4i_irq_ack,
> -	.irq_mask	= sun4i_irq_mask,
> -	.irq_unmask	= sun4i_irq_unmask,
> -};
> -
> -static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
> -			 irq_hw_number_t hw)
> -{
> -	irq_set_chip_and_handler(virq, &sun4i_irq_chip,
> -				 handle_level_irq);
> -	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
> -
> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> +	struct irq_chip_generic *gc;
> +	int i, ret, base = 0;
> +
> +	ret = irq_alloc_domain_generic_chips(d, SUN4I_IRQS_PER_CHIP, 1,

1 should be SUN4I_NUM_CHIPS.

> +					     "sun4i_irq", handle_level_irq,
> +					     clr, 0, IRQ_GC_INIT_MASK_CACHE);
> +	if (ret)
> +		return ret;
> +
> +	for (i = 0; i < SUN4I_NUM_CHIPS; i++, base += SUN4I_IRQS_PER_CHIP) {
> +		gc = irq_get_domain_generic_chip(sun4i_irq_domain, base);

Perhaps this could be an iterator macro.

> +		gc->reg_base = sun4i_irq_base;
> +		gc->chip_types[0].regs.mask = SUN4I_IRQ_ENABLE_REG(i);
> +		gc->chip_types[0].regs.ack = SUN4I_IRQ_PENDING_REG(i);
> +		gc->chip_types[0].chip.mask = irq_gc_mask_clr_bit;
> +		gc->chip_types[0].chip.ack = irq_gc_ack_set_bit;
> +		gc->chip_types[0].chip.unmask = irq_gc_mask_set_bit;
> +
> +		/* Disable, mask and clear all pending interrupts */
> +		writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(i));
> +		writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(i));
> +		writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(i));
> +	}
>  	return 0;
>  }
>  
> -static struct irq_domain_ops sun4i_irq_ops = {
> -	.map = sun4i_irq_map,
> -	.xlate = irq_domain_xlate_onecell,
> -};
> -
>  static int __init sun4i_of_init(struct device_node *node,
>  				struct device_node *parent)
>  {
> @@ -104,21 +77,6 @@ static int __init sun4i_of_init(struct d
>  		panic("%s: unable to map IC registers\n",
>  			node->full_name);
>  
> -	/* Disable all interrupts */
> -	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
> -	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
> -	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
> -
> -	/* Mask all the interrupts */
> -	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
> -	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
> -	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
> -
> -	/* Clear all the pending interrupts */
> -	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
> -	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
> -	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
> -
>  	/* Enable protection mode */
>  	writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
>  
> @@ -126,8 +84,8 @@ static int __init sun4i_of_init(struct d
>  	writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
>  
>  	sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,

s/3 * 32/SUN4I_NUM_CHIPS * SUN4I_IRQS_PER_CHIP/

> -						 &sun4i_irq_ops, NULL);
> -	if (!sun4i_irq_domain)
> +						 &irq_generic_chip_ops, NULL);
> +	if (!sun4i_irq_domain || sun4i_init_domain_chips())
>  		panic("%s: unable to create IRQ domain\n", node->full_name);
>  
>  	set_handle_irq(sun4i_handle_irq);
> 
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss



From tony at atomide.com  Mon May  6 11:27:06 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 6 May 2013 08:27:06 -0700
Subject: mach-omap2/timer.c: Bug introduced while merging patch - ff931c82
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EC7C45D@DBDE04.ent.ti.com>
References: <79CD15C6BA57404B839C016229A409A83EC7C45D@DBDE04.ent.ti.com>
Message-ID: <20130506152706.GD28721@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [130506 00:12]:
> Hi,
> 
> Not sure whether this got discussed and fixed already, but Google didn't give me anything :)
> 
> The below commit got merged wrongly to Mainline (Changes from timer.c got missed), and 
> due to this none of omap boards will boot.
> 
> 
> From ff931c821bab6713a52b768b0cd7ee7e90713b36 Mon Sep 17 00:00:00 2001
> From: Rajendra Nayak <rnayak at ti.com>
> Date: Thu, 21 Mar 2013 11:04:52 +0000
> Subject: ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
> 
> 
> It seems Linux-omap tree has the fix patch for this, and it should get pushed ASAP. 
> Below are links for Linus's mainline commit [1], the actual patch submitted to the list [2] and
> Commit  present in Linux-omap [3].

Can you please provide a proper patch for the regression since sounds
like you already figured out what happened?

Regards,

Tony 
 
> [1] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/arm/mach-omap2/io.c?id=ff931c821bab6713a52b768b0cd7ee7e90713b36
> [2] https://patchwork.kernel.org/patch/2300071/
> [3] http://git.kernel.org/cgit/linux/kernel/git/tmlind/linux-omap.git/commit/arch/arm/mach-omap2/timer.c?id=ff931c821bab6713a52b768b0cd7ee7e90713b36


From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:33 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:33 +0200
Subject: [PATCH 0/7] mv643xx_eth: device tree bindings
In-Reply-To: <1365071235-11611-1-git-send-email-florian@openwrt.org>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
Message-ID: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set picks up work by Florian Fainelli bringing full DT
support to mv643xx_eth and Marvell SoCs using it.

The current patch set drops Florian's device tree conversions for
Kirkwood, Dove, and Orion5x in favour of split patches for board
files and board descriptor files.

Device tree conversion for Dove and Kirkwood is added. Dove has
been fully tested, while Kirkwood is compile-tested only.

Florian Fainelli (2):
  net: mv643xx_eth: add Device Tree bindings
  net: mv643xx_eth: update Device Tree bindings documentation

Sebastian Hesselbarth (5):
  ARM: dove: remove legacy mv643xx_eth setup
  ARM: dove: add gigabit ethernet and mvmdio device tree nodes
  ARM: kirkwood: remove legacy mv643xx_eth board setup
  ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
  ARM: kirkwood: remove legacy clk alias for mv643xx_eth

 Documentation/devicetree/bindings/marvell.txt      |   22 ++++-
 arch/arm/boot/dts/dove-cubox.dts                   |    8 ++
 arch/arm/boot/dts/dove.dtsi                        |   35 +++++++
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   15 +++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   15 +++
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   15 +++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   26 +++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   15 +++
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |   26 +++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   15 +++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   15 +++
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   22 ++++
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   15 +++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   26 +++++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   25 +++++
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   15 +++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   15 +++
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |   15 +++
 arch/arm/boot/dts/kirkwood-topkick.dts             |   15 +++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   15 +++
 arch/arm/boot/dts/kirkwood.dtsi                    |   52 ++++++++++
 arch/arm/mach-dove/board-dt.c                      |    5 -
 arch/arm/mach-kirkwood/board-dnskw.c               |    7 --
 arch/arm/mach-kirkwood/board-dockstar.c            |    9 --
 arch/arm/mach-kirkwood/board-dreamplug.c           |   14 ---
 arch/arm/mach-kirkwood/board-dt.c                  |   16 ---
 arch/arm/mach-kirkwood/board-goflexnet.c           |    9 --
 arch/arm/mach-kirkwood/board-guruplug.c            |   14 ---
 arch/arm/mach-kirkwood/board-ib62x0.c              |    9 --
 arch/arm/mach-kirkwood/board-iconnect.c            |    6 -
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c      |   16 ---
 arch/arm/mach-kirkwood/board-km_kirkwood.c         |    7 --
 arch/arm/mach-kirkwood/board-lsxl.c                |   12 --
 arch/arm/mach-kirkwood/board-mplcec4.c             |   11 --
 arch/arm/mach-kirkwood/board-ns2.c                 |   13 ---
 arch/arm/mach-kirkwood/board-openblocks_a6.c       |    9 --
 arch/arm/mach-kirkwood/board-readynas.c            |    6 -
 arch/arm/mach-kirkwood/board-ts219.c               |   13 ---
 arch/arm/mach-kirkwood/board-usi_topkick.c         |    9 --
 drivers/net/ethernet/marvell/mv643xx_eth.c         |  108 +++++++++++++++++++-
 include/linux/mv643xx_eth.h                        |    3 +
 48 files changed, 544 insertions(+), 192 deletions(-)
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:34 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:34 +0200
Subject: [PATCH v3 1/7] net: mv643xx_eth: add Device Tree bindings
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-2-git-send-email-sebastian.hesselbarth@gmail.com>

From: Florian Fainelli <florian at openwrt.org>

This patch adds Device Tree bindings following the already defined
bindings at Documentation/devicetree/bindings/marvell.txt. The binding
documentation is also enhanced with new optionnal properties required
for supporting certain devices (RX/TX queue and SRAM). Since we now have
proper support for the orion MDIO bus driver, there is no need to fiddle
around with device tree phandles. PHY-less (MAC connected to switch)
configurations are supported by not specifying any phy phandle for an
ethernet node.

Signed-off-by: Florian Fainelli <florian at openwrt.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v2->v3:
- rebase on top of mv643xx_eth clean-ups
- do not reparse existing platform_data
- use managed devm_kzalloc for parsed platform_data
- use of_property_read_u32 where applicable
- add phy_node to platform_data
- use of_connect_phy if DT phy node was found

v1->v2:
- properly ifdef of_platform_bus_probe with CONFIG_OF
- handle of_platform_bus_probe errors and cleanup accordingly
- use of_property_read_u32 where applicable
- parse "duplex" and "speed" property in PHY-less configuration

Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 Documentation/devicetree/bindings/marvell.txt |   22 +++++-
 drivers/net/ethernet/marvell/mv643xx_eth.c    |  108 ++++++++++++++++++++++++-
 include/linux/mv643xx_eth.h                   |    3 +
 3 files changed, 128 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/marvell.txt b/Documentation/devicetree/bindings/marvell.txt
index f7a0da6..73ea12f 100644
--- a/Documentation/devicetree/bindings/marvell.txt
+++ b/Documentation/devicetree/bindings/marvell.txt
@@ -112,11 +112,13 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
    Required properties:
      - #address-cells : <1>
      - #size-cells : <0>
-     - compatible : "marvell,mv64360-eth-block"
+     - compatible : "marvell,mv64360-eth-block", "marvell,mv643xx-eth-block"
      - reg : Offset and length of the register set for this block
 
    Optional properties:
      - clocks : Phandle to the clock control device and gate bit
+     - tx-csum-limit : Hardware limit above which transmit checksumming
+                       is disabled.
 
    Example Discovery Ethernet block node:
      ethernet-block at 2000 {
@@ -133,7 +135,7 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
 
    Required properties:
      - device_type : Should be "network".
-     - compatible : Should be "marvell,mv64360-eth".
+     - compatible : Should be "marvell,mv64360-eth", "marvell,mv643xx-eth"
      - reg : Should be <0>, <1>, or <2>, according to which registers
        within the silicon block the device uses.
      - interrupts : <a> where a is the interrupt number for the port.
@@ -143,6 +145,22 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
        controller.
      - local-mac-address : 6 bytes, MAC address
 
+   Optional properties:
+     - clocks : Phandle to the clock control device and gate bit
+     - clock-names : String describing the clock gate bit
+     - speed : Speed to force the link (10, 100, 1000), used when no
+               phy property is defined
+     - duplex : Duplex to force the link (0: half, 1: full), used when no
+               phy property is defined
+     - rx-queue-count : number of RX queues to use
+     - tx-queue-count : number of TX queues to use
+     - rx-queue-size : size of the RX queue (in bytes)
+     - tx-queue-size : size of the TX queue (in bytes)
+     - rx-sram-addr : address of the SRAM for RX path (non 0 means used)
+     - rx-sram-size : size of the SRAM for RX path (non 0 means used)
+     - tx-sram-addr : address of the SRAM for TX path (non 0 means used)
+     - tx-sram-size : size of the SRAM for TX path (non 0 means used)
+
    Example Discovery Ethernet port node:
      ethernet at 0 {
 	     device_type = "network";
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index d0afeea..efa5a2f 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -60,6 +60,11 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/stringify.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_mdio.h>
+#include <linux/of_net.h>
 
 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
 static char mv643xx_eth_driver_version[] = "1.4";
@@ -2450,13 +2455,22 @@ static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
 	}
 }
 
+static const struct of_device_id mv643xx_eth_match[] = {
+	{ .compatible = "marvell,mv64360-eth" },
+	{ .compatible = "marvell,mv643xx-eth" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mv643xx_eth_match);
+
 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 {
 	static int mv643xx_eth_version_printed;
+	struct device_node *np = pdev->dev.of_node;
 	struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
 	struct mv643xx_eth_shared_private *msp;
 	const struct mbus_dram_target_info *dram;
 	struct resource *res;
+	int tx_csum_limit = 0;
 
 	if (!mv643xx_eth_version_printed++)
 		pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
@@ -2485,13 +2499,21 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	if (dram)
 		mv643xx_eth_conf_mbus_windows(msp, dram);
 
-	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
-					pd->tx_csum_limit : 9 * 1024;
+	if (np)
+		of_property_read_u32(np, "tx-csum-limit", &tx_csum_limit);
+	else
+		tx_csum_limit = pd->tx_csum_limit;
+
+	msp->tx_csum_limit = tx_csum_limit ? tx_csum_limit : 9 * 1024;
 	infer_hw_params(msp);
 
 	platform_set_drvdata(pdev, msp);
 
+#ifdef CONFIG_OF
+	return of_platform_bus_probe(np, mv643xx_eth_match, &pdev->dev);
+#else
 	return 0;
+#endif
 }
 
 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
@@ -2505,12 +2527,20 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id mv643xx_eth_shared_match[] = {
+	{ .compatible = "marvell,mv64360-eth-block" },
+	{ .compatible = "marvell,mv643xx-eth-block" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_match);
+
 static struct platform_driver mv643xx_eth_shared_driver = {
 	.probe		= mv643xx_eth_shared_probe,
 	.remove		= mv643xx_eth_shared_remove,
 	.driver = {
 		.name	= MV643XX_ETH_SHARED_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mv643xx_eth_shared_match),
 	},
 };
 
@@ -2669,6 +2699,68 @@ static const struct net_device_ops mv643xx_eth_netdev_ops = {
 #endif
 };
 
+#ifdef CONFIG_OF
+static int mv643xx_eth_of_probe(struct platform_device *pdev)
+{
+	struct mv643xx_eth_platform_data *pd;
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *shared = of_get_parent(np);
+	const int *prop;
+	const char *mac_addr;
+
+	if (pdev->dev.platform_data || !pdev->dev.of_node)
+		return 0;
+
+	pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return -ENOMEM;
+
+	pdev->dev.platform_data = pd;
+
+	pd->shared = of_find_device_by_node(shared);
+	if (!pd->shared)
+		return -ENODEV;
+
+	if (of_property_read_u32(np, "reg", &pd->port_number))
+		return -EINVAL;
+
+	pd->phy_node = of_parse_phandle(np, "phy", 0);
+	if (!pd->phy_node) {
+		pd->phy_addr = MV643XX_ETH_PHY_NONE;
+
+		of_property_read_u32(np, "speed", &pd->speed);
+		of_property_read_u32(np, "duplex", &pd->duplex);
+	}
+
+	mac_addr = of_get_mac_address(np);
+	if (mac_addr)
+		memcpy(pd->mac_addr, mac_addr, ETH_ALEN);
+
+#define rx_tx_queue_sram_property(_name)				\
+	do {								\
+		prop = of_get_property(np, __stringify(_name), NULL);	\
+		if (prop)						\
+			pd->_name = be32_to_cpup(prop);			\
+	} while (0)
+
+	rx_tx_queue_sram_property(rx_queue_count);
+	rx_tx_queue_sram_property(tx_queue_count);
+	rx_tx_queue_sram_property(rx_queue_size);
+	rx_tx_queue_sram_property(tx_queue_size);
+	rx_tx_queue_sram_property(rx_sram_addr);
+	rx_tx_queue_sram_property(rx_sram_size);
+	rx_tx_queue_sram_property(tx_sram_addr);
+	rx_tx_queue_sram_property(rx_sram_size);
+
+	return 0;
+}
+#else
+static inline int mv643xx_eth_of_probe(struct platform_device *dev)
+{
+	return 0;
+}
+#endif
+
 static int mv643xx_eth_probe(struct platform_device *pdev)
 {
 	struct mv643xx_eth_platform_data *pd;
@@ -2677,6 +2769,10 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	struct resource *res;
 	int err;
 
+	err = mv643xx_eth_of_probe(pdev);
+	if (err)
+		return err;
+
 	pd = pdev->dev.platform_data;
 	if (pd == NULL) {
 		dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
@@ -2717,7 +2813,12 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	netif_set_real_num_rx_queues(dev, mp->rxq_count);
 
 	if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
-		mp->phy = phy_scan(mp, pd->phy_addr);
+		if (pd->phy_node)
+			mp->phy = of_phy_connect(mp->dev, pd->phy_node,
+						mv643xx_eth_adjust_link, 0,
+						PHY_INTERFACE_MODE_GMII);
+		else
+			mp->phy = phy_scan(mp, pd->phy_addr);
 
 		if (IS_ERR(mp->phy)) {
 			err = PTR_ERR(mp->phy);
@@ -2837,6 +2938,7 @@ static struct platform_driver mv643xx_eth_driver = {
 	.driver = {
 		.name	= MV643XX_ETH_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mv643xx_eth_match),
 	},
 };
 
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 141d395..c006d3d 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -30,6 +30,8 @@ struct mv643xx_eth_shared_platform_data {
 #define MV643XX_ETH_PHY_ADDR(x)		(0x80 | (x))
 #define MV643XX_ETH_PHY_NONE		0xff
 
+struct device_node;
+
 struct mv643xx_eth_platform_data {
 	/*
 	 * Pointer back to our parent instance, and our port number.
@@ -41,6 +43,7 @@ struct mv643xx_eth_platform_data {
 	 * Whether a PHY is present, and if yes, at which address.
 	 */
 	int			phy_addr;
+	struct device_node	*phy_node;
 
 	/*
 	 * Use this MAC address if it is valid, overriding the
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:36 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:36 +0200
Subject: [PATCH v3 3/7] ARM: dove: remove legacy mv643xx_eth setup
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-4-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/board-dt.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd..3c0963d 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -34,10 +34,6 @@ static void __init dove_legacy_clk_init(void)
 	clkspec.np = np;
 	clkspec.args_count = 1;
 
-	clkspec.args[0] = CLOCK_GATING_BIT_GBE;
-	orion_clkdev_add(NULL, "mv643xx_eth_port.0",
-			 of_clk_get_from_provider(&clkspec));
-
 	clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
 	orion_clkdev_add("0", "pcie",
 			 of_clk_get_from_provider(&clkspec));
@@ -70,7 +66,6 @@ static void __init dove_dt_init(void)
 	dove_of_clk_init();
 
 	/* Internal devices not ported to DT yet */
-	dove_ge00_init(&dove_dt_ge00_data);
 	dove_pcie_init(1, 1);
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:35 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:35 +0200
Subject: [PATCH v3 2/7] net: mv643xx_eth: update Device Tree bindings
 documentation
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-3-git-send-email-sebastian.hesselbarth@gmail.com>

From: Florian Fainelli <florian at openwrt.org>

This patch updates the Device Tree bindings documentation for the
Marvell MV643xx ethernet controller node and makes the
"local-mac-address" and "phy" properties optional instead of required.
The absence of a "phy" node is legal and describes a MAC to switch
configuration, while not specifying the "local-mac-address" allows for
reuse of the MAC address already programmed into the Ethernet
controller.

Signed-off-by: Florian Fainelli <florian at openwrt.org>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 Documentation/devicetree/bindings/marvell.txt |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/marvell.txt b/Documentation/devicetree/bindings/marvell.txt
index 73ea12f..ed4058c 100644
--- a/Documentation/devicetree/bindings/marvell.txt
+++ b/Documentation/devicetree/bindings/marvell.txt
@@ -141,11 +141,11 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
      - interrupts : <a> where a is the interrupt number for the port.
      - interrupt-parent : the phandle for the interrupt controller
        that services interrupts for this device.
+
+   Optional properties:
      - phy : the phandle for the PHY connected to this ethernet
        controller.
      - local-mac-address : 6 bytes, MAC address
-
-   Optional properties:
      - clocks : Phandle to the clock control device and gate bit
      - clock-names : String describing the clock gate bit
      - speed : Speed to force the link (10, 100, 1000), used when no
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:37 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:37 +0200
Subject: [PATCH v3 4/7] ARM: dove: add gigabit ethernet and mvmdio device tree
 nodes
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-5-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Dove boards. As there is only one ethernet controller on Dove, a default
phy node is also added with a note to overwrite its reg property on a
per-board basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove-cubox.dts |    8 ++++++++
 arch/arm/boot/dts/dove.dtsi      |   35 +++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7e3065a..a52f016 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -49,6 +49,14 @@
 &uart0 { status = "okay"; };
 &sata0 { status = "okay"; };
 &i2c0 { status = "okay"; };
+&mdio { status = "okay"; };
+&eth { status = "okay"; };
+&eth0 { status = "okay"; };
+
+&ethphy {
+	compatible = "marvell,88e1310";
+	reg = <1>;
+};
 
 &sdio0 {
 	status = "okay";
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 6cab468..8bb46c4 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -258,5 +258,40 @@
 				dmacap,xor;
 			};
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			reg = <0x72004 0x84>;
+			interrupts = <30>;
+			clocks = <&gate_clk 2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			ethphy: ethernet-phy {
+				device_type = "ethernet-phy";
+				/* overwrite reg property in board file */
+			};
+		};
+
+		eth: ethernet-controller at 72000 {
+			compatible = "marvell,mv643xx-eth-block";
+			reg = <0x72000 0x4000>;
+			clocks = <&gate_clk 2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-csum-limit = <1600>;
+			status = "disabled";
+
+			eth0: ethernet-port at 0 {
+				compatible = "marvell,mv643xx-eth";
+				device_type = "network";
+				reg = <0>;
+				interrupts = <29>;
+				clocks = <&gate_clk 2>;
+				phy = <&ethphy>;
+				status = "disabled";
+			};
+		};
 	};
 };
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:40 +0200
Subject: [PATCH v3 7/7] ARM: kirkwood: remove legacy clk alias for mv643xx_eth
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-8-git-send-email-sebastian.hesselbarth@gmail.com>

With all boards converted to DT enabled mv643xx_eth we can now
remove the clock alias for gbe clocks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/board-dt.c |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 7904758..f474cb9 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -42,7 +42,6 @@ static void __init kirkwood_legacy_clk_init(void)
 	struct device_node *np = of_find_compatible_node(
 		NULL, NULL, "marvell,kirkwood-gating-clock");
 	struct of_phandle_args clkspec;
-	struct clk *clk;
 
 	clkspec.np = np;
 	clkspec.args_count = 1;
@@ -58,21 +57,6 @@ static void __init kirkwood_legacy_clk_init(void)
 	clkspec.args[0] = CGC_BIT_SDIO;
 	orion_clkdev_add(NULL, "mvsdio",
 			 of_clk_get_from_provider(&clkspec));
-
-	/*
-	 * The ethernet interfaces forget the MAC address assigned by
-	 * u-boot if the clocks are turned off. Until proper DT support
-	 * is available we always enable them for now.
-	 */
-	clkspec.args[0] = CGC_BIT_GE0;
-	clk = of_clk_get_from_provider(&clkspec);
-	orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
-	clk_prepare_enable(clk);
-
-	clkspec.args[0] = CGC_BIT_GE1;
-	clk = of_clk_get_from_provider(&clkspec);
-	orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
-	clk_prepare_enable(clk);
 }
 
 static void __init kirkwood_of_clk_init(void)
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:38 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:38 +0200
Subject: [PATCH v3 5/7] ARM: kirkwood: remove legacy mv643xx_eth board setup
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-6-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards. This patch removes eth setup
for all kirkwood DT board files.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/board-dnskw.c          |    7 -------
 arch/arm/mach-kirkwood/board-dockstar.c       |    9 ---------
 arch/arm/mach-kirkwood/board-dreamplug.c      |   14 --------------
 arch/arm/mach-kirkwood/board-goflexnet.c      |    9 ---------
 arch/arm/mach-kirkwood/board-guruplug.c       |   14 --------------
 arch/arm/mach-kirkwood/board-ib62x0.c         |    9 ---------
 arch/arm/mach-kirkwood/board-iconnect.c       |    6 ------
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   16 ----------------
 arch/arm/mach-kirkwood/board-km_kirkwood.c    |    7 -------
 arch/arm/mach-kirkwood/board-lsxl.c           |   12 ------------
 arch/arm/mach-kirkwood/board-mplcec4.c        |   11 -----------
 arch/arm/mach-kirkwood/board-ns2.c            |   13 -------------
 arch/arm/mach-kirkwood/board-openblocks_a6.c  |    9 ---------
 arch/arm/mach-kirkwood/board-readynas.c       |    6 ------
 arch/arm/mach-kirkwood/board-ts219.c          |   13 -------------
 arch/arm/mach-kirkwood/board-usi_topkick.c    |    9 ---------
 16 files changed, 0 insertions(+), 164 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index a1aa87f..2af7a95 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,14 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data dnskw_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 /* Register any GPIO for output and set the value */
 static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 {
@@ -36,8 +31,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 
 void __init dnskw_init(void)
 {
-	kirkwood_ge00_init(&dnskw_ge00_data);
-
 	/* Set NAS to turn back on after a power failure */
 	dnskw_gpio_register(37, "dnskw:power:recover", 1);
 }
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
index d7196db..b78032e 100644
--- a/arch/arm/mach-kirkwood/board-dockstar.c
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -16,17 +16,8 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data dockstar_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init dockstar_dt_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&dockstar_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 0903242..cb7823d 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -13,23 +13,9 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
 void __init dreamplug_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&dreamplug_ge00_data);
-	kirkwood_ge01_init(&dreamplug_ge01_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 9db979a..4213e20 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -18,17 +18,8 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init goflexnet_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&goflexnet_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
index a857163..d515f64 100644
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ b/arch/arm/mach-kirkwood/board-guruplug.c
@@ -11,23 +11,9 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data guruplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data guruplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
 void __init guruplug_dt_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&guruplug_ge00_data);
-	kirkwood_ge01_init(&guruplug_ge01_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index 9a857ae..6082373 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -13,17 +13,8 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 void __init ib62x0_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&ib62x0_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4..045668c 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -11,16 +11,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data iconnect_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
-};
-
 void __init iconnect_init(void)
 {
-	kirkwood_ge00_init(&iconnect_ge00_data);
 }
 
 static int __init iconnect_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
index e5f7041..dc86cf7 100644
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -10,25 +10,9 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
-	.phy_addr       = MV643XX_ETH_PHY_NONE,
-	.speed          = SPEED_1000,
-	.duplex         = DUPLEX_FULL,
-};
-
-static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
-};
-
 void __init iomega_ix2_200_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
-	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
index 44e4605..6b8464b 100644
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -14,15 +14,10 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/clk.h>
 #include <linux/clk-private.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init km_kirkwood_init(void)
 {
 	struct clk *sata_clk;
@@ -39,6 +34,4 @@ void __init km_kirkwood_init(void)
 	sata_clk = clk_get_sys("sata_mv.0", "1");
 	if (!IS_ERR(sata_clk))
 		sata_clk->flags |= CLK_IGNORE_UNUSED;
-
-	kirkwood_ge00_init(&km_kirkwood_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..1cbcd56 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -14,17 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data lsxl_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data lsxl_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 /*
  * On the LS-XHL/LS-CHLv2, the shutdown process is following:
  * - Userland monitors key events until the power switch goes to off position
@@ -44,9 +35,6 @@ void __init lsxl_init(void)
 	 * Basic setup. Needs to be called early.
 	 */
 
-	kirkwood_ge00_init(&lsxl_ge00_data);
-	kirkwood_ge01_init(&lsxl_ge01_data);
-
 	/* register power-off method */
 	pm_power_off = lsxl_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc66..a337ef5 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -11,24 +11,13 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(2),
-};
-
 void __init mplcec4_init(void)
 {
 	/*
 	 * Basic setup. Needs to be called early.
 	 */
-	kirkwood_ge00_init(&mplcec4_ge00_data);
-	kirkwood_ge01_init(&mplcec4_ge01_data);
 	kirkwood_pcie_init(KW_PCIE0);
 }
 
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
index f8f6605..ba3abd6 100644
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -14,22 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/of.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data ns2_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 void __init ns2_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	if (of_machine_is_compatible("lacie,cloudbox") ||
-	    of_machine_is_compatible("lacie,netspace_lite_v2") ||
-	    of_machine_is_compatible("lacie,netspace_mini_v2"))
-		ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-	kirkwood_ge00_init(&ns2_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
index b11d8fd..120dccf 100644
--- a/arch/arm/mach-kirkwood/board-openblocks_a6.c
+++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c
@@ -10,17 +10,8 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data openblocks_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init openblocks_a6_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&openblocks_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20..3ab3e0e 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -13,16 +13,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init netgear_readynas_init(void)
 {
-	kirkwood_ge00_init(&netgear_readynas_ge00_data);
 	kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index acb0187..854d448 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -18,27 +18,14 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 #include "tsx1x-common.h"
 
-static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 void __init qnap_dt_ts219_init(void)
 {
-	u32 dev, rev;
-
-	kirkwood_pcie_id(&dev, &rev);
-	if (dev == MV88F6282_DEV_ID)
-		qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-
-	kirkwood_ge00_init(&qnap_ts219_ge00_data);
-
 	pm_power_off = qnap_tsx1x_power_off;
 }
 
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
index 1cc04ec..44a8a6b 100644
--- a/arch/arm/mach-kirkwood/board-usi_topkick.c
+++ b/arch/arm/mach-kirkwood/board-usi_topkick.c
@@ -12,18 +12,9 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data topkick_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init usi_topkick_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&topkick_ge00_data);
 }
-- 
1.7.2.5



From sebastian.hesselbarth at gmail.com  Mon May  6 11:33:39 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 May 2013 17:33:39 +0200
Subject: [PATCH v3 6/7] ARM: kirkwood: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1367854420-8006-7-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Kirkwood boards. Phy nodes are also added with reg property set on a
per-board basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: David Miller <davem at davemloft.net>
Cc: Florian Fainelli <florian at openwrt.org>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Simon Guinot <simon.guinot at sequanux.org>
Cc: Jamie Lentin <jm at lentin.co.uk>
Cc: Michael Walle <michael at walle.cc>
Cc: Eric Hutter <hutter.eric at gmail.com>
Cc: Joshua Coombs <josh.coombs at gmail.com>
Cc: Willy Tarreau <w at 1wt.eu>
Cc: Simon Baatz <gmbnomis at gmail.com>
Cc: Alan M Butler <alanbutty12 at gmail.com>
Cc: Nigel Roberts <nigel at nobiscuit.com>
Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Stefan Peter <s.peter at mpl.ch>
Cc: Arnaud Ebalard <arno at natisbad.org>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: netdev at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   15 ++++++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   15 ++++++
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   15 ++++++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   26 ++++++++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   15 ++++++
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |   26 ++++++++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   15 ++++++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   15 ++++++
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   22 ++++++++
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   15 ++++++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   26 ++++++++++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   25 +++++++++
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   15 ++++++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   15 ++++++
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |   15 ++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |   15 ++++++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   15 ++++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   52 ++++++++++++++++++++
 25 files changed, 373 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e..d4f1e89 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -87,3 +87,18 @@
 		gpios = <&gpio0 17 0>;
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac0..b203f07 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -217,3 +217,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6..1b46882 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -91,3 +91,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d..3ce258b 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -99,3 +99,29 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&eth1 { status = "okay"; };
+&egiga1 {
+	status = "okay";
+	phy = <&ethphy1>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be..84fe313 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -170,3 +170,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97d..894e658 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -96,3 +96,29 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&eth1 { status = "okay"; };
+&egiga1 {
+	status = "okay";
+	phy = <&ethphy1>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1a..7e7845d 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -119,3 +119,18 @@
 
 
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74..7991168 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -168,3 +168,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 11 {
+		device_type = "ethernet-phy";
+		reg = <11>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94..40e85aa 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -191,3 +191,25 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	speed = <1000>;
+	duplex = <1>;
+};
+
+&eth1 { status = "okay"; };
+&egiga1 {
+	status = "okay";
+	phy = <&ethphy1>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy1: ethernet-phy at 11 {
+		device_type = "ethernet-phy";
+		reg = <11>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0a..2e5fe72 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd054..fd97497 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -43,3 +43,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4..e9d61db 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -201,3 +201,29 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&eth1 { status = "okay"; };
+&egiga1 {
+	status = "okay";
+	phy = <&ethphy1>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..326cc48 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -182,3 +182,28 @@
 	};
 };
 
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&eth1 { status = "okay"; };
+&egiga1 {
+	status = "okay";
+	phy = <&ethphy1>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+
+	ethphy1: ethernet-phy at 2 {
+		device_type = "ethernet-phy";
+		reg = <2>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab..f3b39f7 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -178,3 +178,18 @@
                 };
         };
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd92..b205832 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -82,3 +82,18 @@
 	};
 
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy {
+		device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf..8ffd552 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4e..16332f8 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6..68d767d 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -47,3 +47,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab..5b1b17b 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -48,3 +48,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f724..d8109f9 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -210,3 +210,18 @@
 		};
         };
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b..dc3bb78 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -201,3 +201,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c83..0bd67bf 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -49,4 +49,6 @@
 			gpios = <&gpio0 16 1>;
 		};
 	};
-};
\ No newline at end of file
+};
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95d..a1bdef6 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -49,4 +49,6 @@
 			gpios = <&gpio1 5 1>;
 		};
 	};
-};
\ No newline at end of file
+};
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..5865dc5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -76,3 +76,18 @@
 		};
 	};
 };
+
+&eth0 { status = "okay"; };
+&egiga0 {
+	status = "okay";
+	phy = <&ethphy0>;
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy {
+		device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..c01a273 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -202,5 +202,57 @@
 			clocks = <&gate_clk 4>;
 			status = "disabled";
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			reg = <0x72004 0x84>;
+			interrupts = <11>;
+			clocks = <&gate_clk 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			/* add phy nodes in board file */
+		};
+
+		eth0: ethernet-controller at 72000 {
+			compatible = "marvell,mv643xx-eth-block";
+			reg = <0x72000 0x4000>;
+			clocks = <&gate_clk 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-csum-limit = <1600>;
+			status = "disabled";
+
+			egiga0: ethernet-port at 0 {
+				compatible = "marvell,mv643xx-eth";
+				device_type = "network";
+				reg = <0>;
+				interrupts = <11>;
+				clocks = <&gate_clk 0>;
+				/* set phy property in board file */
+				status = "disabled";
+			};
+		};
+
+		eth1: ethernet-controller at 76000 {
+			compatible = "marvell,mv643xx-eth-block";
+			reg = <0x76000 0x4000>;
+			clocks = <&gate_clk 19>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-csum-limit = <1600>;
+			status = "disabled";
+
+			egiga1: ethernet-port at 1 {
+				compatible = "marvell,mv643xx-eth";
+				device_type = "network";
+				reg = <1>;
+				interrupts = <15>;
+				clocks = <&gate_clk 19>;
+				/* set phy property in board file */
+				status = "disabled";
+			};
+		};
 	};
 };
-- 
1.7.2.5



From davem at davemloft.net  Mon May  6 11:38:00 2013
From: davem at davemloft.net (David Miller)
Date: Mon, 06 May 2013 11:38:00 -0400 (EDT)
Subject: [PATCH 0/7] mv643xx_eth: device tree bindings
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130506.113800.203598940932244298.davem@davemloft.net>


Two things:

1) None of your postings make the mailing lists because your CC: line is
   too large, and we block large ones because those are %99 of SPAM.

   It really isn't reasonable to CC: so many people, and I do understand
   that you're just sifting email addresses from MAINTAINERS or whatever,
   but just use the appropriate mailing lists and the absolute most direct
   developer(s).  Probably just the person who you believe should apply
   this patch.

2) Networking feature patch submissions are closed, as per:

	http://marc.info/?l=linux-netdev&m=136730964130303&w=2

   Therefore please resubmit this after the merge window is closed
   and I have explicitly announced that the net-next tree is open again
   for submissions.

Thanks.


From thomas.petazzoni at free-electrons.com  Mon May  6 11:39:09 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 6 May 2013 17:39:09 +0200
Subject: [PATCH v3 5/7] ARM: kirkwood: remove legacy mv643xx_eth board
 setup
In-Reply-To: <1367854420-8006-6-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367854420-8006-6-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130506173909.10dc7c59@skate>

Dear Sebastian Hesselbarth,

On Mon,  6 May 2013 17:33:38 +0200, Sebastian Hesselbarth wrote:
> With DT support for mv643xx_eth we do not need legacy platform_data
> based setup for DT enabled boards. This patch removes eth setup
> for all kirkwood DT board files.
> 

>  arch/arm/mach-kirkwood/board-dnskw.c          |    7 -------
>  arch/arm/mach-kirkwood/board-dockstar.c       |    9 ---------
>  arch/arm/mach-kirkwood/board-dreamplug.c      |   14 --------------
>  arch/arm/mach-kirkwood/board-goflexnet.c      |    9 ---------
>  arch/arm/mach-kirkwood/board-guruplug.c       |   14 --------------
>  arch/arm/mach-kirkwood/board-ib62x0.c         |    9 ---------
>  arch/arm/mach-kirkwood/board-iconnect.c       |    6 ------
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   16 ----------------
>  arch/arm/mach-kirkwood/board-km_kirkwood.c    |    7 -------
>  arch/arm/mach-kirkwood/board-lsxl.c           |   12 ------------
>  arch/arm/mach-kirkwood/board-mplcec4.c        |   11 -----------
>  arch/arm/mach-kirkwood/board-ns2.c            |   13 -------------
>  arch/arm/mach-kirkwood/board-openblocks_a6.c  |    9 ---------
>  arch/arm/mach-kirkwood/board-readynas.c       |    6 ------
>  arch/arm/mach-kirkwood/board-ts219.c          |   13 -------------
>  arch/arm/mach-kirkwood/board-usi_topkick.c    |    9 ---------

I believe a good number of those files become empty once you've removed
the registration of the Ethernet devices. Shouldn't such files be
removed in this patch?

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From pavel at denx.de  Mon May  6 11:53:04 2013
From: pavel at denx.de (Pavel Machek)
Date: Mon, 6 May 2013 17:53:04 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <201305061545.22587.arnd@arndb.de>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <20130426214313.GB24891@amd.pavel.ucw.cz>
 <20130506124814.GA28259@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de>
Message-ID: <20130506155304.GA6645@amd.pavel.ucw.cz>

On Mon 2013-05-06 15:45:22, Arnd Bergmann wrote:
> On Monday 06 May 2013, Pavel Machek wrote:
> > 
> > Hi!
> > 
> > Ping? Previous version was tested by Dinh, and this one is based on
> > Jamie's updates, so I assume it is acceptable for him, too.
> > 
> > It brings two platforms closer together, and makes time actually work
> > on socfpga. It would be good to get it applied.
> 
> Who should apply it? I guess it needs to go through arm-soc with all the
> other clocksource changes already queued up there. Can we have an Ack
> from Jamie and from the clocksource maintainers?

Well, changes to arch/arm/mach-picoxcell are single line (and that's a
cleanup of duplicate include). 

So I guess it should go through the timekeeping tree...?

Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From jason at lakedaemon.net  Mon May  6 12:07:43 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 6 May 2013 12:07:43 -0400
Subject: [PATCH 0/7] mv643xx_eth: device tree bindings
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130506160743.GV31290@titan.lakedaemon.net>

Sebastian,

Thanks for picking this up!  A few comments about merging strategy:

On Mon, May 06, 2013 at 05:33:33PM +0200, Sebastian Hesselbarth wrote:
> This patch set picks up work by Florian Fainelli bringing full DT
> support to mv643xx_eth and Marvell SoCs using it.
> 
> The current patch set drops Florian's device tree conversions for
> Kirkwood, Dove, and Orion5x in favour of split patches for board
> files and board descriptor files.
> 
> Device tree conversion for Dove and Kirkwood is added. Dove has
> been fully tested, while Kirkwood is compile-tested only.
> 
> Florian Fainelli (2):
>   net: mv643xx_eth: add Device Tree bindings
>   net: mv643xx_eth: update Device Tree bindings documentation

Obviously, these will go through -net once the submission window opens.

> Sebastian Hesselbarth (5):
(reordered for clarity)

>   ARM: dove: remove legacy mv643xx_eth setup
>   ARM: kirkwood: remove legacy mv643xx_eth board setup
>   ARM: kirkwood: remove legacy clk alias for mv643xx_eth

mvebu/boards or /soc.

>   ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
>   ARM: dove: add gigabit ethernet and mvmdio device tree nodes

mvebu/dt


mvebu/dt and -net are fine.  They have no dependencies.  The problem is
mvebu/boards.  To boot with networking, it needs -net *and* mvebu/dt.
Otherwise, the board needs to do legacy init.

I'd like to attempt to remove this dependency-hell with code.  eg some
quick pseudo-code:

	if (!dt_node_present("marvell,mv643xx_eth") ||
	    !mvebu_dt_bindings_present())
		kirkwood_ge00_init();

The advantages of figuring this out are:
 - *no* branch dependencies
 - whole conversion done in one merge window

The drawbacks:
 - need to remember to do a follow-on patch if all branches are
   successfuly merged, removing the unneeded logic (after -rc1)
 - considered churn?

The easy answer is to merge mvebu/dt, and -net, wait one cycle, and
merge the board stuff as you have it now (with Thomas' comment).

If we can figure this out, I'd like to do the same for the kirkwood-pcie
series.

thoughts?

thx,

Jason.


From sebastian.hesselbarth at gmail.com  Mon May  6 12:21:54 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 06 May 2013 18:21:54 +0200
Subject: [PATCH 0/7] mv643xx_eth: device tree bindings
In-Reply-To: <20130506160743.GV31290@titan.lakedaemon.net>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130506160743.GV31290@titan.lakedaemon.net>
Message-ID: <5187D8A2.5060604@gmail.com>

On 05/06/13 18:07, Jason Cooper wrote:
> Sebastian,
>
> Thanks for picking this up!  A few comments about merging strategy:
>
> On Mon, May 06, 2013 at 05:33:33PM +0200, Sebastian Hesselbarth wrote:
>> This patch set picks up work by Florian Fainelli bringing full DT
>> support to mv643xx_eth and Marvell SoCs using it.
>>
>> The current patch set drops Florian's device tree conversions for
>> Kirkwood, Dove, and Orion5x in favour of split patches for board
>> files and board descriptor files.
>>
>> Device tree conversion for Dove and Kirkwood is added. Dove has
>> been fully tested, while Kirkwood is compile-tested only.
>>
>> Florian Fainelli (2):
>>    net: mv643xx_eth: add Device Tree bindings
>>    net: mv643xx_eth: update Device Tree bindings documentation
>
> Obviously, these will go through -net once the submission window opens.
>
>> Sebastian Hesselbarth (5):
> (reordered for clarity)
>
>>    ARM: dove: remove legacy mv643xx_eth setup
>>    ARM: kirkwood: remove legacy mv643xx_eth board setup
>>    ARM: kirkwood: remove legacy clk alias for mv643xx_eth
>
> mvebu/boards or /soc.
>
>>    ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
>>    ARM: dove: add gigabit ethernet and mvmdio device tree nodes
>
> mvebu/dt
>
>
> mvebu/dt and -net are fine.  They have no dependencies.  The problem is
> mvebu/boards.  To boot with networking, it needs -net *and* mvebu/dt.
> Otherwise, the board needs to do legacy init.
>
> I'd like to attempt to remove this dependency-hell with code.  eg some
> quick pseudo-code:
>
> 	if (!dt_node_present("marvell,mv643xx_eth") ||
> 	    !mvebu_dt_bindings_present())
> 		kirkwood_ge00_init();
>
> The advantages of figuring this out are:
>   - *no* branch dependencies
>   - whole conversion done in one merge window
>
> The drawbacks:
>   - need to remember to do a follow-on patch if all branches are
>     successfuly merged, removing the unneeded logic (after -rc1)
>   - considered churn?
>
> The easy answer is to merge mvebu/dt, and -net, wait one cycle, and
> merge the board stuff as you have it now (with Thomas' comment).
>
> If we can figure this out, I'd like to do the same for the kirkwood-pcie
> series.

Jason,

I suggest to take the "easy answer", i.e. merge mvebu/dt and -net and
take all board merges one cycle later.

Waiting for -net will stall irqchip but will give us enough time to
add DT timer and get rid of any legacy init code introduced for irqchip.
Also orion5x and mv78x00 can be added to mv643xx_eth conversion.

I am preparing empty board files removal as Thomas suggested.

Sebastian

P.S.: I was hoping that adding all people scripts/get_maintainers.pl
throws out, will notice all kirkwood board users ever committed to
mainline kernel. But as David Miller pointed out, it will not go through
SPAM filters that way. So have an eye open for v4 on mailing lists as
soon as -net merge window re-opens.



From jic23 at kernel.org  Mon May  6 12:27:38 2013
From: jic23 at kernel.org (Jonathan Cameron)
Date: Mon, 06 May 2013 17:27:38 +0100
Subject: [PATCH 1/2] staging/iio/mxs-lradc: cleanup masklength
In-Reply-To: <6bb527db65fb20f60bb95814bff3abc513733a7c.1367671597.git.mirq-linux@rere.qmqm.pl>
References: <6bb527db65fb20f60bb95814bff3abc513733a7c.1367671597.git.mirq-linux@rere.qmqm.pl>
Message-ID: <5187D9FA.8000808@kernel.org>

On 05/04/2013 02:19 PM, Micha? Miros?aw wrote:
> We know the exact iio->masklength = LRADC_MAX_TOTAL_CHANS.
> Let's use it consistently.
I guess this gives a small improvement in clarity so
applied to togreg branch of iio.git.

Thanks,
> 
> Signed-off-by: Micha? Miros?aw <mirq-linux at rere.qmqm.pl>
> ---
>  drivers/staging/iio/adc/mxs-lradc.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
> index 2856b8f..03299ea 100644
> --- a/drivers/staging/iio/adc/mxs-lradc.c
> +++ b/drivers/staging/iio/adc/mxs-lradc.c
> @@ -620,7 +620,7 @@ static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
>  		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
>  	unsigned int i, j = 0;
>  
> -	for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
> +	for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
>  		lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
>  		writel(chan_value, lradc->base + LRADC_CH(j));
>  		lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
> @@ -775,8 +775,7 @@ static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
>  					const unsigned long *mask)
>  {
>  	struct mxs_lradc *lradc = iio_priv(iio);
> -	const int len = iio->masklength;
> -	const int map_chans = bitmap_weight(mask, len);
> +	const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
>  	int rsvd_chans = 0;
>  	unsigned long rsvd_mask = 0;
>  
> @@ -793,7 +792,7 @@ static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
>  		rsvd_chans++;
>  
>  	/* Test for attempts to map channels with special mode of operation. */
> -	if (bitmap_intersects(mask, &rsvd_mask, len))
> +	if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
>  		return false;
>  
>  	/* Test for attempts to map more channels then available slots. */
> @@ -969,6 +968,7 @@ static int mxs_lradc_probe(struct platform_device *pdev)
>  	iio->modes = INDIO_DIRECT_MODE;
>  	iio->channels = mxs_lradc_chan_spec;
>  	iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
> +	iio->masklength = LRADC_MAX_TOTAL_CHANS;
>  
>  	ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
>  				&mxs_lradc_trigger_handler,
> 


From jic23 at kernel.org  Mon May  6 12:30:25 2013
From: jic23 at kernel.org (Jonathan Cameron)
Date: Mon, 06 May 2013 17:30:25 +0100
Subject: [PATCH 2/2] staging/iio/mxs-lradc: fix preenable for multiple
 buffers
In-Reply-To: <ba60ca91ef1d3061b454e518f6026a1157fae5d7.1367671597.git.mirq-linux@rere.qmqm.pl>
References: <6bb527db65fb20f60bb95814bff3abc513733a7c.1367671597.git.mirq-linux@rere.qmqm.pl>
 <ba60ca91ef1d3061b454e518f6026a1157fae5d7.1367671597.git.mirq-linux@rere.qmqm.pl>
Message-ID: <5187DAA1.50503@kernel.org>

On 05/04/2013 02:19 PM, Micha? Miros?aw wrote:
> This fixes 'preenable failed: -EINVAL' error when using this driver.
> 
For future patches, please cleanly separate out (in a different series)
the bug fixes from the cleanups.  This one has been applied to the
fixes-togreg branch of iio.git wherease the first patch will go
through the togreg branch and hit one kernel cycle later.

Applied to the fixes-togreg
> Signed-off-by: Micha? Miros?aw <mirq-linux at rere.qmqm.pl>
> ---
>  drivers/staging/iio/adc/mxs-lradc.c |    5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
> index 03299ea..d92c97a 100644
> --- a/drivers/staging/iio/adc/mxs-lradc.c
> +++ b/drivers/staging/iio/adc/mxs-lradc.c
> @@ -690,7 +690,6 @@ static void mxs_lradc_trigger_remove(struct iio_dev *iio)
>  static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
>  {
>  	struct mxs_lradc *lradc = iio_priv(iio);
> -	struct iio_buffer *buffer = iio->buffer;
>  	int ret = 0, chan, ofs = 0;
>  	unsigned long enable = 0;
>  	uint32_t ctrl4_set = 0;
> @@ -698,7 +697,7 @@ static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
>  	uint32_t ctrl1_irq = 0;
>  	const uint32_t chan_value = LRADC_CH_ACCUMULATE |
>  		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
> -	const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
> +	const int len = bitmap_weight(iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS);
>  
>  	if (!len)
>  		return -EINVAL;
> @@ -725,7 +724,7 @@ static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
>  		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
>  	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
>  
> -	for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
> +	for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
>  		ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
>  		ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
>  		ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
> 


From sboyd at codeaurora.org  Mon May  6 13:31:04 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 06 May 2013 10:31:04 -0700
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130506093059.GH23285@pengutronix.de>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
Message-ID: <5187E8D8.3080708@codeaurora.org>

On 05/06/13 02:30, Uwe Kleine-K?nig wrote:
> Hello,
>
> On Thu, Apr 18, 2013 at 11:10:19AM +0200, Uwe Kleine-K?nig wrote:
>> On Mon, Mar 18, 2013 at 11:28:56AM -0700, Stephen Boyd wrote:
>>> The ISAR0 register indicates support for the SDIV and UDIV
>>> instructions in both the Thumb and ARM instruction set. Read the
>>> register to detect the supported instructions and update the
>>> elf_hwcap mask as appropriate. This is better than adding more
>>> and more cpuid checks in proc-v7.S for each new cpu variant that
>>> supports these instructions.
>> you pointed out yesterday that this could work on v7-m, too. As I based
>> my patches on 3.9-rc1 this patch (8164f7af88) wasn't included. When
>> updating this results in a warning, because I have
>>
>> 	6ebd4d0 (ARM: stub out read_cpuid and read_cpuid_ext for CPU_CP15=n)
>>
>> from rmk's devel-stable branch.
>>  
>>> Acked-by: Will Deacon <will.deacon at arm.com>
>>> Cc: Stepan Moskovchenko <stepanm at codeaurora.org>
>>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
>>> ---
>>>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>>>  arch/arm/mm/proc-v7.S   |  4 ++--
>>>  2 files changed, 22 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>>> index e2c8bbf..f3ac13f 100644
>>> --- a/arch/arm/kernel/setup.c
>>> +++ b/arch/arm/kernel/setup.c
>>> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>>>  	printk("%s", buf);
>>>  }
>>>  
>>> +static void __init cpuid_init_hwcaps(void)
>>> +{
>>> +	unsigned int divide_instrs;
>>> +
>>> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
>>> +		return;
>>> +
>>> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
>> The problem is that read_cpuid_ext is called which doesn't map to
>> something useful for v7-m. So maybe add a check:
>>
>> 	if (!IS_ENABLED(CONFIG_CPU_CP15))
>> 		return;
>>
>> ?
> The patch below fixes the issue for me on V7-M. The only drawback is
> that the list of registers isn't shared. Maybe someone has a nice idea?

The patch looks ok to me.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From cov at codeaurora.org  Mon May  6 14:01:23 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 06 May 2013 14:01:23 -0400
Subject: [RFC PATCH 0/2] ARM: Remove any correlation between IPC and
 BogoMips value
In-Reply-To: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
Message-ID: <5187EFF3.6010005@codeaurora.org>

Hi Will,

On 05/03/2013 01:35 PM, Will Deacon wrote:
> Hi all,
> 
> This small patch set may look a little over a month late, but there is a
> serious reason for posting it.
> 
> When I moved the ARM delay loop over to using the architected timers
> rather than the CPU spinning loop (which has all the problems associated
> with cpu frequency scaling and what-not) I thought I was doing something
> useful for the port. However, it turns out that a surprising number of
> people have complained, and continue to complain, about the drop in
> their `BogoMIPs score'.

Have you considered adding the old code back in, but in a form that's not at
all referenced by the delay loop code and just calculates CPU-based bogomips?

Regards,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From hvaibhav at ti.com  Mon May  6 14:30:36 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 6 May 2013 18:30:36 +0000
Subject: mach-omap2/timer.c: Bug introduced while merging patch - ff931c82
In-Reply-To: <20130506152706.GD28721@atomide.com>
References: <79CD15C6BA57404B839C016229A409A83EC7C45D@DBDE04.ent.ti.com>
 <20130506152706.GD28721@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC7C93A@DBDE04.ent.ti.com>

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Monday, May 06, 2013 8:57 PM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; linux-kernel at vger.kernel.org; linux-
> arm-kernel at lists.infradead.org
> Subject: Re: mach-omap2/timer.c: Bug introduced while merging patch -
> ff931c82
> 
> * Hiremath, Vaibhav <hvaibhav at ti.com> [130506 00:12]:
> > Hi,
> >
> > Not sure whether this got discussed and fixed already, but Google
> didn't give me anything :)
> >
> > The below commit got merged wrongly to Mainline (Changes from timer.c
> got missed), and
> > due to this none of omap boards will boot.
> >
> >
> > From ff931c821bab6713a52b768b0cd7ee7e90713b36 Mon Sep 17 00:00:00
> 2001
> > From: Rajendra Nayak <rnayak at ti.com>
> > Date: Thu, 21 Mar 2013 11:04:52 +0000
> > Subject: ARM: OMAP: clocks: Delay clk inits atleast until slab is
> initialized
> >
> >
> > It seems Linux-omap tree has the fix patch for this, and it should
> get pushed ASAP.
> > Below are links for Linus's mainline commit [1], the actual patch
> submitted to the list [2] and
> > Commit  present in Linux-omap [3].
> 
> Can you please provide a proper patch for the regression since sounds
> like you already figured out what happened?
> 

Ohh yeah, I already have a patch for it -



From: Vaibhav Hiremath <hvaibhav at ti.com>
Date: Mon, 6 May 2013 13:23:27 +0530
Subject: [PATCH] ARM: OMAP2+: Regression: Add missing code while merging commit ff931c82 to Mainline

While merging commit ff931c82 [1] to Mainline,, it seems not all the changes from 
the original patch [2] have been merged; changes from mach-omap2/timer.c have been
dropped, which invokes xxx_clk_init() function required to register platform
clock table. And without this none of OMAP family of devices will boot from
Mainline.

[1] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/arm/mach-omap2/io.c?id=ff931c821bab6713a52b768b0cd7ee7e90713b36
[2] https://patchwork.kernel.org/patch/2300071/

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
---
arch/arm/mach-omap2/timer.c |    4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f12aa6c..31ae764 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -549,6 +549,8 @@ static inline void __init realtime_counter_init(void)
                               clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                      \
 {                                                                      \
+       if (omap_clk_init)                                              \
+               omap_clk_init();                                        \
        omap_dmtimer_init();                                            \
        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
@@ -559,6 +561,8 @@ void __init omap##name##_gptimer_timer_init(void)                   \
                                clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)              \
 {                                                                      \
+       if (omap_clk_init)                                              \
+               omap_clk_init();                                        \
        omap_dmtimer_init();                                            \
        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
        /* Enable the use of clocksource="gp_timer" kernel parameter */ \




Thanks,
Vaibhav


From linus.walleij at linaro.org  Mon May  6 15:29:48 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 6 May 2013 21:29:48 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130505202236.GF24282@game.jcrosoft.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
Message-ID: <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>

On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> I was thinking to put a jenkins to test Linus HEAD all the time
> And with some automatic test one some hw
>
> to detect it more quick

Hm yeah, I think I need a broader diversity of testsystems too ... I have this
nice Chromebook so I thought if I could get a mainline kernel running on
it I'd have a bigger coverage as well.

Yours,
Linus Walleij


From cooloney at gmail.com  Mon May  6 15:32:28 2013
From: cooloney at gmail.com (Bryan Wu)
Date: Mon, 6 May 2013 12:32:28 -0700
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org> <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
Message-ID: <CAK5ve-L3tz0QHw8Wf6y2oM0sQEBZ_QyMA6qf5TfYnTv2j_ENqQ@mail.gmail.com>

On Mon, May 6, 2013 at 12:29 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
>
>> I was thinking to put a jenkins to test Linus HEAD all the time
>> And with some automatic test one some hw
>>
>> to detect it more quick
>
> Hm yeah, I think I need a broader diversity of testsystems too ... I have this
> nice Chromebook so I thought if I could get a mainline kernel running on
> it I'd have a bigger coverage as well.
>

I think Stephen are working on bring up linux-next daily build and QA
testing on Tegra hardware. This should be quite helpful.

Thanks,
-Bryan


From plagnioj at jcrosoft.com  Mon May  6 15:41:22 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 6 May 2013 21:41:22 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
Message-ID: <20130506194122.GG24282@game.jcrosoft.org>

On 21:29 Mon 06 May     , Linus Walleij wrote:
> On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> 
> > I was thinking to put a jenkins to test Linus HEAD all the time
> > And with some automatic test one some hw
> >
> > to detect it more quick
> 
> Hm yeah, I think I need a broader diversity of testsystems too ... I have this
> nice Chromebook so I thought if I could get a mainline kernel running on
> it I'd have a bigger coverage as well.

Maybe we could all work together to setup such automatic testing tool

I mean all vendors

Best Regards,
J.
> 
> Yours,
> Linus Walleij


From swarren at wwwdotorg.org  Mon May  6 15:49:58 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 06 May 2013 13:49:58 -0600
Subject: [PATCH 1/3] ARM: tegra: pcie: Add tegra3 support
In-Reply-To: <1365435688-4179-1-git-send-email-jagarwal@nvidia.com>
References: <1365435688-4179-1-git-send-email-jagarwal@nvidia.com>
Message-ID: <51880966.9060503@wwwdotorg.org>

On 04/08/2013 09:41 AM, Jay Agarwal wrote:
> Signed-off-by: Jay Agarwal <jagarwal at nvidia.com>
> 
> - Enable pcie root port 2 for cardhu
> - Make private data structure for each SOC
> - Add required tegra3 clocks and regulators
> - Add tegra3 specific code in enable controller
> - Modify clock tree to get clocks based on device
> - Based on git://gitorious.org/thierryreding/linux.git

Jay, I made quite a few comments on this series, and pointed out that it
didn't actually work for me. Are you planning on fixes these issues and
reposting?


From linux at arm.linux.org.uk  Mon May  6 15:54:03 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 6 May 2013 20:54:03 +0100
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130506194122.GG24282@game.jcrosoft.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org> <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
Message-ID: <20130506195403.GJ18614@n2100.arm.linux.org.uk>

On Mon, May 06, 2013 at 09:41:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 21:29 Mon 06 May     , Linus Walleij wrote:
> > On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
> > <plagnioj at jcrosoft.com> wrote:
> > 
> > > I was thinking to put a jenkins to test Linus HEAD all the time
> > > And with some automatic test one some hw
> > >
> > > to detect it more quick
> > 
> > Hm yeah, I think I need a broader diversity of testsystems too ... I have this
> > nice Chromebook so I thought if I could get a mainline kernel running on
> > it I'd have a bigger coverage as well.
> 
> Maybe we could all work together to setup such automatic testing tool
> 
> I mean all vendors

Don't bother.  We had one, Simtec's Vince Sanders gave us the build side.
No one was interested.  No one took any notice of it.  I have one for a
limited number of platforms - it even boots the resulting kernels on real
hardware.  The only person who looks at it is me.  Again, just one person,
so little value.

And that same thing will appy to anything else setup by anyone else.

It's a good idea, but it only really works if people can be bothered to
derive value from it by checking the results.

My conclusion is that build and boot test systems just don't work in an
open source environment as no one actively checks the results.  Why would
they - maintainers already have enough to do with reading 6500+ emails a
month on mailing lists.  Why bother going to look at a website as well
which might give even more work.


From linus.walleij at linaro.org  Mon May  6 16:12:11 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 6 May 2013 22:12:11 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130506195403.GJ18614@n2100.arm.linux.org.uk>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
Message-ID: <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>

On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:

> My conclusion is that build and boot test systems just don't work in an
> open source environment as no one actively checks the results.  Why would
> they - maintainers already have enough to do with reading 6500+ emails a
> month on mailing lists.  Why bother going to look at a website as well
> which might give even more work.

Point taken. I was in a discussion some time back with Greg and some
other people and we concluded that unless the system mails you when
something breaks it won't make a difference. And it mustn't flood you,
just be very precise.

Actually the autobuilder at kernel.org helped me out but then stopped
building my trees at some point, but that was nice and the same thing
doing boots would be great.

(However I did go in and fix a few build errors in linux-next after
reading on Rothwells autobuilder kisskb some time ... but it was more
a few-off thing.)

Yours,
Linus Walleij


From swarren at wwwdotorg.org  Mon May  6 16:14:39 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 06 May 2013 14:14:39 -0600
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130506195403.GJ18614@n2100.arm.linux.org.uk>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org> <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
Message-ID: <51880F2F.8010102@wwwdotorg.org>

On 05/06/2013 01:54 PM, Russell King - ARM Linux wrote:
> On Mon, May 06, 2013 at 09:41:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 21:29 Mon 06 May     , Linus Walleij wrote:
>>> On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
>>> <plagnioj at jcrosoft.com> wrote:
>>>
>>>> I was thinking to put a jenkins to test Linus HEAD all the time
>>>> And with some automatic test one some hw
>>>>
>>>> to detect it more quick
...
> My conclusion is that build and boot test systems just don't work in an
> open source environment as no one actively checks the results.  Why would
> they - maintainers already have enough to do with reading 6500+ emails a
> month on mailing lists.  Why bother going to look at a website as well
> which might give even more work.

Couldn't such a system email people pro-actively, so nobody had to do
any manual checking? The kisskb(?) build system does that, as does the
"zero day build system" thing from Intel, and I find them quite useful.
Personally, I do the build/test checks manually myself, so if an
automated system were to do it, it'd save me work rather than give me
more work.


From plagnioj at jcrosoft.com  Mon May  6 16:19:22 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 6 May 2013 22:19:22 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <51880F2F.8010102@wwwdotorg.org>
References: <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <51880F2F.8010102@wwwdotorg.org>
Message-ID: <20130506201922.GH24282@game.jcrosoft.org>

On 14:14 Mon 06 May     , Stephen Warren wrote:
> On 05/06/2013 01:54 PM, Russell King - ARM Linux wrote:
> > On Mon, May 06, 2013 at 09:41:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> On 21:29 Mon 06 May     , Linus Walleij wrote:
> >>> On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
> >>> <plagnioj at jcrosoft.com> wrote:
> >>>
> >>>> I was thinking to put a jenkins to test Linus HEAD all the time
> >>>> And with some automatic test one some hw
> >>>>
> >>>> to detect it more quick
> ...
> > My conclusion is that build and boot test systems just don't work in an
> > open source environment as no one actively checks the results.  Why would
> > they - maintainers already have enough to do with reading 6500+ emails a
> > month on mailing lists.  Why bother going to look at a website as well
> > which might give even more work.
> 
> Couldn't such a system email people pro-actively, so nobody had to do
> any manual checking? The kisskb(?) build system does that, as does the
> "zero day build system" thing from Intel, and I find them quite useful.
> Personally, I do the build/test checks manually myself, so if an
> automated system were to do it, it'd save me work rather than give me
> more work.

I've one on at91 but not on all HW but as Russell I need to check manualy

and yes I agreewe should have such automatic tool could be easly be integrated
in Jenkins and send automatic emails

It's really a shamge that no-one is intrested in such tools. I will all save a
huge amount of time of boring basic testing

Best Regards,
J.


From plagnioj at jcrosoft.com  Mon May  6 16:25:01 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 6 May 2013 22:25:01 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <20130506195403.GJ18614@n2100.arm.linux.org.uk>
References: <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
Message-ID: <20130506202501.GI24282@game.jcrosoft.org>

On 20:54 Mon 06 May     , Russell King - ARM Linux wrote:
> On Mon, May 06, 2013 at 09:41:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 21:29 Mon 06 May     , Linus Walleij wrote:
> > > On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
> > > <plagnioj at jcrosoft.com> wrote:
> > > 
> > > > I was thinking to put a jenkins to test Linus HEAD all the time
> > > > And with some automatic test one some hw
> > > >
> > > > to detect it more quick
> > > 
> > > Hm yeah, I think I need a broader diversity of testsystems too ... I have this
> > > nice Chromebook so I thought if I could get a mainline kernel running on
> > > it I'd have a bigger coverage as well.
> > 
> > Maybe we could all work together to setup such automatic testing tool
> > 
> > I mean all vendors
> 
> Don't bother.  We had one, Simtec's Vince Sanders gave us the build side.
> No one was interested.  No one took any notice of it.  I have one for a
> limited number of platforms - it even boots the resulting kernels on real
> hardware.  The only person who looks at it is me.  Again, just one person,
> so little value.

Could you push the build failled on the arm ML or a specific ML

I'm really intresting I hate to brake platform support specialy yours
> 
> And that same thing will appy to anything else setup by anyone else.
> 
> It's a good idea, but it only really works if people can be bothered to
> derive value from it by checking the results.
We can have enforce policy if some brake something again and agian we can do
as Greg did for one of the Linaro dev. Force the patch to be double check by a
senior Maintainter.

And I think it will help Maintainer (Specially subsystem) to detect runtime
bug when applying code they can not test

So I really hope we could change this and make it work

Maybe as you rsaid it will not work but I'm willing to try one more time


From swarren at wwwdotorg.org  Mon May  6 16:39:04 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 May 2013 14:39:04 -0600
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
Message-ID: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
this, simply disable LP2 if the PCI driver and DT node are both enabled.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
Thierry,

This patch is physically based on next-20130506 so that it doesn't
conflict with any of the recent cpuidle cleanup work. I'm sending it with
the expectation that you'll apply it to your PCIe development branch
though. If you do that, you'll see some conflicts unless you rebase your
dev branch onto something more recent than next-20130422; I assume you'll
do that rebase soon enough anyway, but if you weren't planning to, I can
resend the patch based on your current dev branch.

 arch/arm/mach-tegra/cpuidle-tegra20.c |   30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 0cdba8d..d2c9349 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -25,6 +25,7 @@
 #include <linux/cpu_pm.h>
 #include <linux/clockchips.h>
 #include <linux/clk/tegra.h>
+#include <linux/of.h>
 
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
@@ -212,10 +213,39 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 }
 #endif
 
+static const struct of_device_id pcie_matches[] __initconst = {
+	{ .compatible = "nvidia,tegra20-pcie" },
+	{ }
+};
+
+/*
+ * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
+ * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
+ * this, simply disable LP2 if the PCI driver and DT node are both enabled.
+ */
+static void __init tegra20_cpuidle_disable_lp2_with_pcie(void)
+{
+	struct device_node *np;
+
+	if (!IS_ENABLED(CONFIG_PCI_TEGRA))
+		return;
+
+	np = of_find_matching_node(NULL, pcie_matches);
+	if (!np)
+		return;
+
+	if (!of_device_is_available(np))
+		return;
+
+	pr_info("Disabling LP2 cpuidle state, since PCIe is enabled\n");
+	tegra_idle_driver.state_count = 1;
+}
+
 int __init tegra20_cpuidle_init(void)
 {
 #ifdef CONFIG_PM_SLEEP
 	tegra_tear_down_cpu = tegra20_tear_down_cpu;
 #endif
+	tegra20_cpuidle_disable_lp2_with_pcie();
 	return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 }
-- 
1.7.10.4



From cooloney at gmail.com  Mon May  6 16:40:37 2013
From: cooloney at gmail.com (Bryan Wu)
Date: Mon, 6 May 2013 13:40:37 -0700
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <51880F2F.8010102@wwwdotorg.org>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org> <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <51880F2F.8010102@wwwdotorg.org>
Message-ID: <CAK5ve-Lu_mrXDHvxv64GvzrxFYGW+2P2+_tOGGFKC9mf0FOpJw@mail.gmail.com>

On Mon, May 6, 2013 at 1:14 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 05/06/2013 01:54 PM, Russell King - ARM Linux wrote:
>> On Mon, May 06, 2013 at 09:41:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 21:29 Mon 06 May     , Linus Walleij wrote:
>>>> On Sun, May 5, 2013 at 10:22 PM, Jean-Christophe PLAGNIOL-VILLARD
>>>> <plagnioj at jcrosoft.com> wrote:
>>>>
>>>>> I was thinking to put a jenkins to test Linus HEAD all the time
>>>>> And with some automatic test one some hw
>>>>>
>>>>> to detect it more quick
> ...
>> My conclusion is that build and boot test systems just don't work in an
>> open source environment as no one actively checks the results.  Why would
>> they - maintainers already have enough to do with reading 6500+ emails a
>> month on mailing lists.  Why bother going to look at a website as well
>> which might give even more work.
>
> Couldn't such a system email people pro-actively, so nobody had to do
> any manual checking? The kisskb(?) build system does that, as does the
> "zero day build system" thing from Intel, and I find them quite useful.
> Personally, I do the build/test checks manually myself, so if an
> automated system were to do it, it'd save me work rather than give me
> more work.

Yes, this 0day build system rocks. It will pull in specific branches
in maintainer branch and do building/automatic code checking like
smack/boot testing. If they find any issues, they will send out emails
directly to the authors and SoB persons. We just need to add our ARM
into to their system for such building/booting test.

So for this issue, it should be very easy to find and email to the author.

Thanks,
-Bryan


From thierry.reding at avionic-design.de  Mon May  6 16:44:24 2013
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 6 May 2013 22:44:24 +0200
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20130506204424.GA18286@avionic-0098.adnet.avionic-design.de>

On Mon, May 06, 2013 at 02:39:04PM -0600, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
> they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
> this, simply disable LP2 if the PCI driver and DT node are both enabled.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
> Thierry,
> 
> This patch is physically based on next-20130506 so that it doesn't
> conflict with any of the recent cpuidle cleanup work. I'm sending it with
> the expectation that you'll apply it to your PCIe development branch
> though. If you do that, you'll see some conflicts unless you rebase your
> dev branch onto something more recent than next-20130422; I assume you'll
> do that rebase soon enough anyway, but if you weren't planning to, I can
> resend the patch based on your current dev branch.

Yes, I'll be rebasing my development branch soon anyway and I'll pull
this patch into the branch. Thanks for writing it.

Thierry
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From eduardo.valentin at ti.com  Mon May  6 17:00:56 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Mon, 6 May 2013 17:00:56 -0400
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
Message-ID: <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>

Introduce HAS_BANDGAP config entry. This config is a
boolean value so that arch code can flag is they
feature a bandgap device.

Cc: Russell King <linux at arm.linux.org.uk>
Cc: Tony Lindgren <tony at atomide.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-omap at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 arch/arm/Kconfig            | 3 +++
 arch/arm/mach-omap2/Kconfig | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f95674a..39fc561 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -176,6 +176,9 @@ config ARCH_HAS_CPUFREQ
 	  and that the relevant menu configurations are displayed for
 	  it.
 
+config ARCH_HAS_BANDGAP
+	bool
+
 config GENERIC_HWEIGHT
 	bool
 	default y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..8620ab5 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -4,6 +4,7 @@ config ARCH_OMAP
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
 	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_BANDGAP
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select ARCH_OMAP
 	select ARCH_REQUIRE_GPIOLIB
-- 
1.8.2.1.342.gfa7285d



From eduardo.valentin at ti.com  Mon May  6 17:00:57 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Mon, 6 May 2013 17:00:57 -0400
Subject: [RESEND][PATCH 2/3] arm: dts: add bandgap entry for OMAP443x devices
In-Reply-To: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
Message-ID: <1367874058-2378-3-git-send-email-eduardo.valentin@ti.com>

This patch add the bandgap entry for OMAP4430 devices.

Cc: "Beno?t Cousson" <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-omap at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 arch/arm/boot/dts/omap443x.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..8d6c968 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -24,4 +24,8 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+	bandgap {
+		reg = <0x4a002260 0x4 0x4a00232C 0x4>;
+		compatible = "ti,omap4430-bandgap";
+	};
 };
-- 
1.8.2.1.342.gfa7285d



From eduardo.valentin at ti.com  Mon May  6 17:00:58 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Mon, 6 May 2013 17:00:58 -0400
Subject: [RESEND][PATCH 3/3] arm: add bandgap entry for OMAP4460 devices
In-Reply-To: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
Message-ID: <1367874058-2378-4-git-send-email-eduardo.valentin@ti.com>

Include bandgap devices for OMAP4460 devices.

Cc: "Beno?t Cousson" <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-omap at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 7c2c23c..3808b5c 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -29,4 +29,13 @@
 			     <0 55 0x4>;
 		ti,hwmods = "debugss";
 	};
+
+	bandgap {
+		reg = <0x4a002260 0x4
+			0x4a00232C 0x4
+			0x4a002378 0x18>;
+		compatible = "ti,omap4460-bandgap";
+		interrupts = <0 126 4>; /* talert */
+		ti,tshut-gpio = <86>;
+	};
 };
-- 
1.8.2.1.342.gfa7285d



From swarren at wwwdotorg.org  Mon May  6 17:11:09 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 May 2013 15:11:09 -0600
Subject: [PATCH 0/2] ARM: tegra: a couple clock bug-fixes 
Message-ID: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Arnd, Olof,

The following two patches fix a couple issues in the Tegra20 clock driver
that show up on specific platforms. They were sent a little late for 3.9,
and I forgot to include them for 3.10 since they weren't reposted:-(

Patch 1 is clearly a bug-fix. Someone pedantic could argue that patch 2
is a new feature since it's the last piece to enabling AC'97 support, but
I'd argue that it's a bug in the clock driver that it didn't support this
clock when it was first written:-)

These patches logically belong to Tegra's for-3.10/clk branch, but feel
free to apply them where is easiest; it'd be fine to defer them to a post-
3.10-rc1 fixes branch too if you want.

Lucas Stach (2):
  clk: tegra: remove USB from clk init table
  clk: tegra: add ac97 controller clock

 drivers/clk/tegra/clk-tegra20.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May  6 17:11:11 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 May 2013 15:11:11 -0600
Subject: [PATCH 2/2] clk: tegra: add ac97 controller clock
In-Reply-To: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
References: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1367874671-11474-3-git-send-email-swarren@wwwdotorg.org>

From: Lucas Stach <dev at lynxeye.de>

AC97 controller clock is hardwired to pll_a_out0.

Signed-off-by: Lucas Stach <dev at lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver at nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad at nvidia.com>
Acked-by: Mike Turquette <mturquette at linaro.org>
Tested-by: Stephen Warren <swarren at nvidia.com>
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 drivers/clk/tegra/clk-tegra20.c |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index ecfe532..2547bc0 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void)
 	struct clk *clk;
 	int i;
 
+	/* ac97 */
+	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
+				    TEGRA_PERIPH_ON_APB,
+				    clk_base, 0, 3, &periph_l_regs,
+				    periph_clk_enb_refcnt);
+	clk_register_clkdev(clk, NULL, "tegra20-ac97");
+	clks[ac97] = clk;
+
 	/* apbdma */
 	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
 				    0, 34, &periph_h_regs,
-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May  6 17:11:10 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 May 2013 15:11:10 -0600
Subject: [PATCH 1/2] clk: tegra: remove USB from clk init table
In-Reply-To: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
References: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1367874671-11474-2-git-send-email-swarren@wwwdotorg.org>

From: Lucas Stach <dev at lynxeye.de>

The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.

As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.

Signed-off-by: Lucas Stach <dev at lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver at nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad at nvidia.com>
Acked-by: Mike Turquette <mturquette at linaro.org>
Tested-by: Stephen Warren <swarren at nvidia.com>
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 drivers/clk/tegra/clk-tegra20.c |    3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b0405b6..ecfe532 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1234,9 +1234,6 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{uartc, pll_p, 0, 0},
 	{uartd, pll_p, 0, 0},
 	{uarte, pll_p, 0, 0},
-	{usbd, clk_max, 12000000, 0},
-	{usb2, clk_max, 12000000, 0},
-	{usb3, clk_max, 12000000, 0},
 	{pll_a, clk_max, 56448000, 1},
 	{pll_a_out0, clk_max, 11289600, 1},
 	{cdev1, clk_max, 0, 1},
-- 
1.7.10.4



From arnd at arndb.de  Mon May  6 17:24:16 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 May 2013 23:24:16 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <20130506155304.GA6645@amd.pavel.ucw.cz>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de> <20130506155304.GA6645@amd.pavel.ucw.cz>
Message-ID: <201305062324.17080.arnd@arndb.de>

On Monday 06 May 2013, Pavel Machek wrote:
> On Mon 2013-05-06 15:45:22, Arnd Bergmann wrote:
> > On Monday 06 May 2013, Pavel Machek wrote:
> > > 
> > > Hi!
> > > 
> > > Ping? Previous version was tested by Dinh, and this one is based on
> > > Jamie's updates, so I assume it is acceptable for him, too.
> > > 
> > > It brings two platforms closer together, and makes time actually work
> > > on socfpga. It would be good to get it applied.
> > 
> > Who should apply it? I guess it needs to go through arm-soc with all the
> > other clocksource changes already queued up there. Can we have an Ack
> > from Jamie and from the clocksource maintainers?
> 
> Well, changes to arch/arm/mach-picoxcell are single line (and that's a
> cleanup of duplicate include). 

The point is that Jamie had comments on the earlier version, so it would
be good to see his Ack on the current one.

> So I guess it should go through the timekeeping tree...?

I would prefer that, but we can also take it through arm-soc, it doesn't
really matter.

	Arnd


From aaro.koskinen at iki.fi  Mon May  6 17:34:13 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 7 May 2013 00:34:13 +0300
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
Message-ID: <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>

On Mon, May 06, 2013 at 05:00:56PM -0400, Eduardo Valentin wrote:
> Introduce HAS_BANDGAP config entry. This config is a
> boolean value so that arch code can flag is they
> feature a bandgap device.

Maybe it could be mentioned that omap-thermal already depend on this?
At least for a random reviewer it was not immediately clear why this is
added, especially since there were no users for it in subsequent patches.

A.


From swarren at wwwdotorg.org  Mon May  6 17:31:25 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 06 May 2013 15:31:25 -0600
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
Message-ID: <5188212D.3030904@wwwdotorg.org>

On 05/06/2013 03:00 PM, Eduardo Valentin wrote:
> Introduce HAS_BANDGAP config entry. This config is a
> boolean value so that arch code can flag is they
> feature a bandgap device.

What does this patch have to do with device tree (there's "dts" in the
subject)? What's a BANDGAP device?


From nerv at dawncrow.de  Mon May  6 18:27:54 2013
From: nerv at dawncrow.de (=?UTF-8?B?QW5kcsOpIEhlbnRzY2hlbA==?=)
Date: Tue, 07 May 2013 00:27:54 +0200
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <5183D6C3.8090402@arm.com>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
 <5182C480.3080001@dawncrow.de> <5183819E.50308@arm.com>
 <20130503095547.GD18614@n2100.arm.linux.org.uk> <5183D6C3.8090402@arm.com>
Message-ID: <51882E6A.6070302@dawncrow.de>

Am 03.05.2013 17:24, schrieb Jonathan Austin:
>> -	.macro set_tls_none, tp, tmp1, tmp2
>> +	.macro switch_tls_none, base, tp, trw, tmp1, tmp2
>>   	.endm
>>   
>> -	.macro set_tls_v6k, tp, tmp1, tmp2
>> +	.macro switch_tls_v6k, base, tp, trw, tmp1, tmp2
> 
> How do you feel about calling tp and trw something different? tpidro
> and tpidrw, or tp and tpuser?
> 
> The naming threw me off slightly first time I read this new signature
> (tp=thread_pointer/tls_pointer/etc).
> 

FWIW i think tp&tpuser is more consistent.

> Andr?, Assuming I've understood things okay, there's a patch that
> uses Russell's asm stuff (with minor modifications, see the questions)
> and includes the C-world changes too. Perhaps you could see that it
> solves your problem?

It works, but for various reasons i would like to suggest the patch below.
Reasons include: My thoughts about tp&tpuser naming and the helper function for copy_thread, further i'd really like to get a bit credit for spending weeks on getting my second kernel patch in :)
If that patch is fine for you and no one object, i'd be happy to test it, adapt the commit message and include:
	Reported-by: Andr? Hentschel <nerv at dawncrow.de>
	Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
	Signed-off-by: Will Deacon <will.deacon at arm.com>
	Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
	Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>

Not totally sure about the Signed-off-bys. Can i add a Signed-off-by for Russell King? Is it the right mail address for him/you?




diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f..d90be6d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];	/* TLS registers */
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..d7d542b 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-	.macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
 	.endm
 
-	.macro set_tls_v6k, tp, tmp1, tmp2
+	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
 	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_v6, tp, tmp1, tmp2
+	.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
 	ldr	\tmp1, =elf_hwcap
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
 	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	mcrne	p15, 0, \tpuser, c13, c0, 2	@ set user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_software, tp, tmp1, tmp2
+	.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
 	mov	\tmp1, #0xffff0fff
 	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
@@ -31,19 +34,31 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
-#define set_tls		set_tls_none
+#define switch_tls	switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
-#define set_tls		set_tls_v6
+#define switch_tls	switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
-#define set_tls		set_tls_v6k
+#define switch_tls	switch_tls_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
-#define set_tls		set_tls_software
+#define switch_tls	switch_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tlsuser(void)
+{
+	if (has_tls_reg && !tls_emu)
+	{
+		unsigned long t;
+		__asm__("mcr p15, 0, %0, c13, c0, 2" : : "r" (t));
+		return t;
+	}
+	return 0;
+}
+#endif
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..80f09fe 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,15 +728,15 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
+	ldrd	r4, r5, [r2, #TI_TP_VALUE]
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-	set_tls	r3, r4, r5
+	switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
 	ldr	r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e4..24dbc72 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -395,7 +396,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+		thread->tp_value[0] = childregs->ARM_r3;
+	thread->tp_value[1] = get_tlsuser();
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c08911..f9d6259 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }



From jgunthorpe at obsidianresearch.com  Mon May  6 18:36:53 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Mon, 6 May 2013 16:36:53 -0600
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
Message-ID: <20130506223653.GA12089@obsidianresearch.com>

On Tue, May 07, 2013 at 12:34:13AM +0300, Aaro Koskinen wrote:
> On Mon, May 06, 2013 at 05:00:56PM -0400, Eduardo Valentin wrote:
> > Introduce HAS_BANDGAP config entry. This config is a
> > boolean value so that arch code can flag is they
> > feature a bandgap device.
> 
> Maybe it could be mentioned that omap-thermal already depend on this?
> At least for a random reviewer it was not immediately clear why this is
> added, especially since there were no users for it in subsequent patches.

I looked (very briefly), and it seemed like omap-thermal is self
contained and doesn't need arch support?

I get the impression it is desired to minimize driver kconfig
dependencies to the minimum required to compile to increase build
testing coverage, so maybe it would be appropriate to drop this
entirely?

Jason


From eduardo.valentin at ti.com  Mon May  6 18:40:53 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Mon, 6 May 2013 18:40:53 -0400
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
Message-ID: <51883175.8010001@ti.com>

On 06-05-2013 17:34, Aaro Koskinen wrote:
> On Mon, May 06, 2013 at 05:00:56PM -0400, Eduardo Valentin wrote:
>> Introduce HAS_BANDGAP config entry. This config is a
>> boolean value so that arch code can flag is they
>> feature a bandgap device.
> 
> Maybe it could be mentioned that omap-thermal already depend on this?
> At least for a random reviewer it was not immediately clear why this is
> added, especially since there were no users for it in subsequent patches.
> 
> A.
> 
> 
The flag has been proposed here [1]. The adaptation on the driver has
been introduced here [2,3]. It has reached the staging (next) tree. That
is why you do not see any follow up patch. Although it does not have
users at v3.9, the patch on the user has been sent several weeks ago.

[1] -
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101827.html
[2] - http://marc.info/?l=linux-omap&m=136335347305197&w=2
[3] - http://marc.info/?l=linux-driver-devel&m=136335404205514&w=1

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From mturquette at linaro.org  Mon May  6 18:41:26 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Mon, 06 May 2013 15:41:26 -0700
Subject: [PATCH] clk: remove clock notifier at unregister
In-Reply-To: <1366633361-28887-1-git-send-email-david.andrey@netmodule.com>
References: <1366633361-28887-1-git-send-email-david.andrey@netmodule.com>
Message-ID: <20130506224126.4542.19886@quantum>

Quoting David Andrey (2013-04-22 05:22:41)
> Clock notifier node is now removed from the
> notifier list during unregister
> 
> Signed-off-by: David Andrey <david.andrey at netmodule.com>
> Acked-by: Martin Meuli <martin.meuli at netmodule.com>

This looks good.  I'll take it in after -rc1 comes out.

Thanks,
Mike

> ---
>  drivers/clk/clk.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 20ce67f..eb66434 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1941,7 +1941,10 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
>  
>                 /* XXX the notifier code should handle this better */
>                 if (!cn->notifier_head.head) {
> +                       if (clk->notifier_count)
> +                               BUG();
>                         srcu_cleanup_notifier_head(&cn->notifier_head);
> +                       list_del(&cn->node);
>                         kfree(cn);
>                 }
>  
> -- 
> 1.7.4.1


From pavel at ucw.cz  Mon May  6 19:16:14 2013
From: pavel at ucw.cz (Pavel Machek)
Date: Tue, 7 May 2013 01:16:14 +0200
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <1367602547-19322-2-git-send-email-will.deacon@arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
Message-ID: <20130506231554.GB16801@amd.pavel.ucw.cz>

Hi!

> Now that we support a timer-backed delay loop, I'm quickly getting sick
> and tired of people complaining that their beloved bogomips value has
> decreased. You know who you are!

> Unfortunately, we can't just remove the entry from /proc/cpuinfo, as it
> will likely break fragile userspace code which is parsing that stuff, so
> instead replace it with a dummy value that can be chosen in the
> Kconfig.

So, instead of removing it you silently report invalid value? Note
that there's no cpumhz display in procinfo... at least on OLPC I
looked.

And whether it is 30MHz or 3GHz cpu might be relevant information for
userspace, and yes, bogomips used to be good enough for that.

Actually it was mhz, mhz/2 or mhz*2 on pretty much all reasonable systems.

> +choice
> +	prompt "BogoMIPs setting"
> +	default BOGOMIPS_MEDIUM
> +	help
> +	  The BogoMIPs value reported by Linux is exactly what it sounds
> +	  like: totally bogus. It is used to calibrate the delay loop,
> +	  which may be backed by a timer clocked completely independently
> +	  of the CPU.

This is too ugly to live, sorry.

> +	config BOGOMIPS_SLOW
> +		bool "Slow (older machines)"
> +		help
> +		  If you're comparing a faster machine with a slower machine,
> +		  then you might want this option selected on one of them.
> +
> +	config BOGOMIPS_MEDIUM
> +		bool "Medium (default)"
> +		help
> +		  A BogoMIPS value for the masses.
> +
> +	config BOGOMIPS_FAST
> +		bool "Fast (marketing)"
> +		help
> +		  Some people believe that software runs faster with this
> +		  setting so, if you're one of them, say Y here.

April 1st came late this year?

									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From sebastian.hesselbarth at gmail.com  Mon May  6 19:36:08 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue,  7 May 2013 01:36:08 +0200
Subject: [PATCH] pinctrl: dove: add PMU functions to pinctrl
Message-ID: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>

Dove power management unit can mux some special functions to mpp0-15.
This patch adds support to set/get the current PMU function mapped
to the corresponding mpp pins. The device tree documentation is also
updated accordingly.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   49 ++--
 drivers/pinctrl/mvebu/pinctrl-dove.c               |  244 +++++++++++++++++---
 2 files changed, 249 insertions(+), 44 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index a648aaa..50ec351 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -10,29 +10,31 @@ Required properties:
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
 only for more detailed description in this document.
+Note: pmu* also allows for Power Management functions listed below
 
 name          pins     functions
 ================================================================================
-mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
-mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
 mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
-                       uart1(rts)
+                       uart1(rts), pmu*
 mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
-                       uart1(cts), lcd-spi(cs1)
-mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
-mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
-mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
-mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
-mpp8          8        gpio, pmu, watchdog(rstout)
-mpp9          9        gpio, pmu, pex1(clkreq)
-mpp10         10       gpio, pmu, ssp(sclk)
+                       uart1(cts), lcd-spi(cs1), pmu*
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
+mpp8          8        gpio, pmu, watchdog(rstout), pmu*
+mpp9          9        gpio, pmu, pex1(clkreq), pmu*
+mpp10         10       gpio, pmu, ssp(sclk), pmu*
 mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
-                       sdio1(ledctrl), pex0(clkreq)
-mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+                       sdio1(ledctrl), pex0(clkreq), pmu*
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
+                       sata(act), pmu*
 mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
-                       ssp(extclk)
-mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
-mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+                       ssp(extclk), pmu*
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
 mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
 mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
                        ac97-1(sysclko)
@@ -57,6 +59,21 @@ mpp_nand      64-71    gpo, nand
 audio0        -        i2s, ac97
 twsi          -        none, opt1, opt2, opt3
 
+Power Management functions (pmu*):
+pmu-nc               Pin not driven by any PM function
+pmu-low              Pin driven low (0)
+pmu-high             Pin driven high (1)
+pmic(sdi)            Pin is used for PMIC SDI
+cpu-pwr-down         Pin is used for CPU_PWRDWN
+standby-pwr-down     Pin is used for STBY_PWRDWN
+core-pwr-good        Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
+cpu-pwr-good         Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
+bat-fault            Pin is used for BATTERY_FAULT
+ext0-wakeup          Pin is used for EXT0_WU
+ext1-wakeup          Pin is used for EXT0_WU
+ext2-wakeup          Pin is used for EXT0_WU
+pmu-blink            Pin is used for blink function
+
 Notes:
 * group "mpp_audio1" allows the following functions and gpio pins:
   - gpio          : gpio on pins 52-57
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index 428ea96..048ae80 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -26,6 +26,9 @@
 #define DOVE_MPP_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE + 0xd0200)
 #define DOVE_PMU_MPP_GENERAL_CTRL	(DOVE_MPP_VIRT_BASE + 0x10)
 #define  DOVE_AU0_AC97_SEL		BIT(16)
+#define DOVE_PMU_SIGNAL_SELECT_0	(DOVE_SB_REGS_VIRT_BASE + 0xd802C)
+#define DOVE_PMU_SIGNAL_SELECT_1	(DOVE_SB_REGS_VIRT_BASE + 0xd8030)
+#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define  DOVE_TWSI_ENABLE_OPTION1	BIT(7)
 #define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE + 0xe8030)
@@ -58,12 +61,16 @@ static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
 	unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
 	unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
 	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
-	unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
-
-	if (pmu & (1 << ctrl->pid))
-		*config = CONFIG_PMU;
-	else
-		*config = (mpp >> shift) & MPP_MASK;
+	unsigned long func;
+
+	if (pmu & (1 << ctrl->pid)) {
+		func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
+		*config = (func >> shift) & MPP_MASK;
+		*config |= CONFIG_PMU;
+	} else {
+		func = readl(DOVE_MPP_VIRT_BASE + off);
+		*config = (func >> shift) & MPP_MASK;
+	}
 	return 0;
 }
 
@@ -73,15 +80,20 @@ static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
 	unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
 	unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
 	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
-	unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+	unsigned long func;
 
-	if (config == CONFIG_PMU)
+	if (config & CONFIG_PMU) {
 		writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
-	else {
+		func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
+		func &= ~(MPP_MASK << shift);
+		func |= (config & MPP_MASK) << shift;
+		writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off);
+	} else {
 		writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
-		mpp &= ~(MPP_MASK << shift);
-		mpp |= config << shift;
-		writel(mpp, DOVE_MPP_VIRT_BASE + off);
+		func = readl(DOVE_MPP_VIRT_BASE + off);
+		func &= ~(MPP_MASK << shift);
+		func |= (config & MPP_MASK) << shift;
+		writel(func, DOVE_MPP_VIRT_BASE + off);
 	}
 	return 0;
 }
@@ -378,20 +390,53 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = {
 		MPP_FUNCTION(0x02, "uart2", "rts"),
 		MPP_FUNCTION(0x03, "sdio0", "cd"),
 		MPP_FUNCTION(0x0f, "lcd0", "pwm"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(1,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart2", "cts"),
 		MPP_FUNCTION(0x03, "sdio0", "wp"),
 		MPP_FUNCTION(0x0f, "lcd1", "pwm"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(2,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x01, "sata", "prsnt"),
 		MPP_FUNCTION(0x02, "uart2", "txd"),
 		MPP_FUNCTION(0x03, "sdio0", "buspwr"),
 		MPP_FUNCTION(0x04, "uart1", "rts"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(3,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x01, "sata", "act"),
@@ -399,43 +444,131 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = {
 		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
 		MPP_FUNCTION(0x04, "uart1", "cts"),
 		MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(4,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart3", "rts"),
 		MPP_FUNCTION(0x03, "sdio1", "cd"),
 		MPP_FUNCTION(0x04, "spi1", "miso"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(5,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart3", "cts"),
 		MPP_FUNCTION(0x03, "sdio1", "wp"),
 		MPP_FUNCTION(0x04, "spi1", "cs"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(6,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart3", "txd"),
 		MPP_FUNCTION(0x03, "sdio1", "buspwr"),
 		MPP_FUNCTION(0x04, "spi1", "mosi"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(7,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart3", "rxd"),
 		MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
 		MPP_FUNCTION(0x04, "spi1", "sck"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(8,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x01, "watchdog", "rstout"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(9,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x05, "pex1", "clkreq"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(10,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x05, "ssp", "sclk"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(11,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x01, "sata", "prsnt"),
@@ -443,33 +576,88 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = {
 		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
 		MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
 		MPP_FUNCTION(0x05, "pex0", "clkreq"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(12,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x01, "sata", "act"),
 		MPP_FUNCTION(0x02, "uart2", "rts"),
 		MPP_FUNCTION(0x03, "audio0", "extclk"),
 		MPP_FUNCTION(0x04, "sdio1", "cd"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(13,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart2", "cts"),
 		MPP_FUNCTION(0x03, "audio1", "extclk"),
 		MPP_FUNCTION(0x04, "sdio1", "wp"),
 		MPP_FUNCTION(0x05, "ssp", "extclk"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(14,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart2", "txd"),
 		MPP_FUNCTION(0x04, "sdio1", "buspwr"),
 		MPP_FUNCTION(0x05, "ssp", "rxd"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(15,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart2", "rxd"),
 		MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
 		MPP_FUNCTION(0x05, "ssp", "sfrm"),
-		MPP_FUNCTION(0x10, "pmu", NULL)),
+		MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
+		MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
+		MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 	MPP_MODE(16,
 		MPP_FUNCTION(0x00, "gpio", NULL),
 		MPP_FUNCTION(0x02, "uart3", "rts"),
-- 
1.7.10.4



From tony at atomide.com  Mon May  6 19:37:43 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 6 May 2013 16:37:43 -0700
Subject: mach-omap2/timer.c: Bug introduced while merging patch - ff931c82
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EC7C93A@DBDE04.ent.ti.com>
References: <79CD15C6BA57404B839C016229A409A83EC7C45D@DBDE04.ent.ti.com>
 <20130506152706.GD28721@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EC7C93A@DBDE04.ent.ti.com>
Message-ID: <20130506233743.GJ28721@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [130506 11:35]:
> 
> Ohh yeah, I already have a patch for it -

Thanks, I'll add that into omap-for-v3.10/fixes. I modified
the comments a bit trying to figure out where it changed, updated
patch below.

Regards,

Tony


From: Vaibhav Hiremath <hvaibhav at ti.com>
Date: Mon, 6 May 2013 15:19:01 -0700
Subject: [PATCH] ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a

Looks like the timer.c fixes in commit ff931c82 (ARM: OMAP: clocks:
Delay clk inits atleast until slab is initialized) got lost in a
merge with da4a686a (ARM: smp_twd: convert to use CLKSRC_OF init).

Without the omap_clk_init() calls none of OMAP family of devices
boot.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
[tony at atomide.com: updated comments to describe merge error]
Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -549,6 +549,8 @@ static inline void __init realtime_counter_init(void)
 			       clksrc_nr, clksrc_src, clksrc_prop)	\
 void __init omap##name##_gptimer_timer_init(void)			\
 {									\
+	if (omap_clk_init)						\
+		omap_clk_init();					\
 	omap_dmtimer_init();						\
 	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,		\
@@ -559,6 +561,8 @@ void __init omap##name##_gptimer_timer_init(void)			\
 				clksrc_nr, clksrc_src, clksrc_prop)	\
 void __init omap##name##_sync32k_timer_init(void)		\
 {									\
+	if (omap_clk_init)						\
+		omap_clk_init();					\
 	omap_dmtimer_init();						\
 	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	/* Enable the use of clocksource="gp_timer" kernel parameter */	\


From tony at atomide.com  Mon May  6 19:46:11 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 6 May 2013 16:46:11 -0700
Subject: [GIT PULL] Urgent omap timer fix for current merge window
Message-ID: <20130506234610.GK28721@atomide.com>

The following changes since commit dc2d3db8137fba0f62d7517e1bea8a47f69fcbc4:

  Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers (2013-04-08 19:30:48 +0200)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/fixes-for-merge-window

for you to fetch changes up to 08a48be32ff31d38bcfec7d210c954cb62fd5cd7:

  ARM: OMAP4: change the device names in usb_bind_phy (2013-05-06 16:39:16 -0700)

----------------------------------------------------------------
An urgent fix for a timer mismerge for and a regression fix for
musb device naming change.

----------------------------------------------------------------
Kishon Vijay Abraham I (1):
      ARM: OMAP4: change the device names in usb_bind_phy

Vaibhav Hiremath (1):
      ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a

 arch/arm/mach-omap2/board-4430sdp.c    | 2 +-
 arch/arm/mach-omap2/board-omap4panda.c | 2 +-
 arch/arm/mach-omap2/timer.c            | 4 ++++
 3 files changed, 6 insertions(+), 2 deletions(-)


From s-anna at ti.com  Mon May  6 19:45:38 2013
From: s-anna at ti.com (Suman Anna)
Date: Mon, 6 May 2013 18:45:38 -0500
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
Message-ID: <518840A2.5000205@ti.com>

Hi Jassi,

On 05/04/2013 02:08 PM, Jassi Brar wrote:
> Hi Suman,
> 
>> Anyway, here is a summary of the open points that we have:
>> 1. Atomic Callbacks:
>> The current code provides some sort of buffering on Tx, but imposes the
>> restriction that the clients do the buffering on Rx. This is main
>> concern for OMAP.
> 
> I am afraid a common API can't do without buffering TX and it can't do
> by buffering RX.

Maybe both these are properties of the controller then.

> 
>  The client(s) can always generate TX requests at a rate greater than
> the API could transmit on the physical link. So as much as we dislike
> it, we have to buffer TX requests, otherwise N clients would.

The current code doesn't support N clients today anyway, and if they are
blocking mode on top of it, it would never need Tx buffering.

>
> OTOH Buffering received packets in the API doesn't help anybody, it
> only incurs unavoidable latencies on clients. Only clients, that need
> to take non-atomic actions upon RX, would need to buffer RX. Other
> clients should not suffer.

As I have explained for OMAP, it is about performing the bottom-half of
the Rx interrupt in the OMAP mailbox controller driver. The clients just
process the message (independent of inherent knowledge that they all
have to behave in a certain way to perform the bottom-half). A single
transport payload used for both Rx and Tx would make the state machine
very simple.

> 
> IMHO if clients on OMAP need to buffer RX, let us keep it OMAP
> specific. If number of such platforms rise in future we could move
> that as an _optional_ helper API on top, that does RX buffering on
> behalf of clients ?

Yeah, that's my idea as well to put this in the OMAP mailbox controller
driver implementation. The IPC stacks on OMAP are quite established
(both in remoteproc and DSP/Bridge - different generations), so I cannot
afford to break the functionality of either of those. This already means
I have to export some API from my controller driver and there is no
other way or now.

> 
>> 2. Support for Shared Clients AND Time-shared Clients:
>> As I said before, we need the framework to be flexible enough to support
>> shared clients. The shared clients may not be applicable for all h/w
>> controllers, where a client has to send a series of operations that
>> needs to be sent to the remote before anyone else can use it. This is a
>> functional integration aspect, and is dictated by the nature of the
>> remote. For the time-shared clients, the remote must have some implicit
>> message protocol where in the remote is able to identify the macro
>> usecase through a specific message. The framework should allow the case
>> of shared clients, with the clients doing their own message demuxing.
>>
>  If the API provides shared ownership of a mailbox, it won't work for
> clients that need exclusive ownership (like 'server' side
> implementation of a protocol).
>  OTOH if the API provides exclusive ownership, it is still possible to
> emulate shared ownership by simply publishing the mailbox handle (void
> *chan) globally. It works for all.

I am not saying provide this always. Have this dictated by the
controller or mailbox (look at my branch). The global publication works
well functionality-wise for Tx, but not so much for Rx. In anycase,
global publication will have its own set of problems - mostly you are
implying another layer of implementation that provides this sharing
capability (since they have to be outside of any single client).

> 
>>
>> 3. Buffering/Size: I think we need to take a re-look at the whole tx
>> buffering mechanism. You are using an array that stores just the
>> pointers, which means that there are underlying assumptions that the
>> clients are keeping their buffer ptrs intact until the duration of the
>> transfer is done. This means that one cannot use local payload
>> variables for messages in the calling functions. I feel this is
>> unnecessary burden on the clients.
>>
> Most of the clients won't queue more than 1 request at a time. And
> then, isn't it only natural that clients don't mess with requests
> after submitting them ?  I see mailbox clients working quite like I2C
> clients.

The OMAP use-cases do this today, so not a good assumption to make. The
OMAP IPC is built upon simple transmitting and processing received
messages separately, we will not be using blocking mode or tx callbacks.
I really don't need the complexity of having to introduce tx callbacks
just because I need to know if my pointer can be freed, as I said - it
eliminates the simplicity of using local variables unless the send API
is blocking. void * works for OMAP since my payloads are only 4 bytes by
themselves (this is a discussion that came up during the earlier series
as well), but this is not flexible enough on the clients-side generally.

> 
>> Secondly, we may not need the logic around client knows_txdone and
>> tx_buffering together. I understand the need for buffering when you have
>> TX_POLL or TX_IRQ, but as far as TX_ACK is concerned, it is a client
>> protocol-level knowledge, and so the tx buffering logic can remain with
>> the client itself. This should simplify the code a little bit and get
>> rid of the ipc_client_txdone API.
>>
> Yeah I had it that way originally. But then I realized we could be
> running an 'ACK Packet' protocol over a controller that supports only
> POLL. In that case the controller's poll doesn't override client's
> knows_txdone because we want the client to cut-short the next poll
> delay as soon as it gets an ACK packet.

I think the same can be achieved from the Rx path upon an interrupt in
the specific controller, without having to introduce the knows_txdone.
It is knowledge intrinsic to a controller/mailbox. I really hope that
there are no controllers where you have to poll for Rx too :)

> 
>> Looking at the current use-cases, I think OMAP might be the only one
>> which needs the buffering. The API that Loic added suggests that he
>> either sends a message and expects a response, or just sends a message
>> if the transport is free (I am not sure if he is using the API that uses
>> buffering currently). PL320 is the same as the first scenario that Loic has.
>>
> Yeah I too expect TX buffering to be very rare.

If so, can we eliminate this for the first pass, and leave it to the
controllers for now or dictate this based on a tx_buffering property? As
I see it, we do not yet have an agreement on the Tx buffering semantics.

> 
>> The other point is regarding the size field, I am not convinced that we
>> can take this out, and leave it between the client and the controller
>> implementation. I think the mailbox core should at least perform a check
>> based on the max size published by a controller driver. Like in the
>> PL320 patch conversion, the for loop for writing the data - how does it
>> know that the provided pointer is atleast 7 ints, and not smaller than
>> that?
>>
> First of all, PL320 is a highly configurable and programmable IP.
> pl320.c is very specific to Highbank's usage, it is not usable as such
> on other platforms. There are many things hardcoded and tacitly
> assumed in the driver. I just changed the API, didn't add anything
> new.

OK, should we be renaming this file accordingly then until another
common user comes along? Also, an appropriate 'depends on' in the Kconfig.

> 
> Secondly, I believe we acknowledged the fact that a client can't do
> without controller specific knowledge. So in proper implementation the
> controller's header would look like
> 
> struct foobar_con_mssg {
>    int datalen; /* size of received packet in bytes */
>    u8 *buf;  /* buffer that holds the packet data */
>     .....
> };
> 
> So instead of telling the API the 'datalen' and the remaining
> structure of each message, we simply pass "struct foobar_con_mssg *"
> as a void* to the API.

This has to be documented very well. And yes, I did acknowledge the
inter-dependencies portion for understanding the packet structure (there
is no way if you have a packet of 6 ints and you expect specific ints
for specific fields). The size and void * are generic enough that can be
present in the core to perform some error checking. The API would be
akin to memcpy then. The other motivation is based on the buffering
scheme (same comment as above on Tx buffering), which we haven't agreed
upon completely.

> 
> 
>>> +
>>> +/*
>>> + * Called by a client to "put data on the h/w channel" so that if
>>> + * everything else is fine we don't need to do anything more locally
>>> + * for the remote to receive the data intact.
>>> + * In reality, the remote may receive it intact, corrupted or not at all.
>>> + * This could be called from atomic context as it simply
>>> + * queues the data and returns a token (request_token_t)
>>> + * against the request.
>>> + * The client is later notified of successful transmission of
>>> + * data over the channel via the 'txcb'. The client could in
>>> + * turn queue more messages from txcb.
>>> + */
>>> +request_token_t ipc_send_message(void *channel, void *data)
>>> +{
>>> +     struct ipc_chan *chan = (struct ipc_chan *)channel;
>>> +     request_token_t t;
>>> +
>>> +     if (!chan)
>>> +             return 0;
>>> +
>>> +     t = _add_to_rbuf(chan, data);
>>> +     if (!t)
>>> +             printk("Try increasing MBOX_TX_QUEUE_LEN\n");
>>> +
>>> +     _msg_submit(chan);
>>> +
>>> +     if (chan->txdone_method == TXDONE_BY_POLL)
>>> +             poll_txdone((unsigned long)chan->timer);
>>> +
>>> +     if (chan->tx_block && chan->active_token) {
>>
>> Assigning the tx_block at channel request time might not be flexible
>> enough. We should not impose that the client will request and release
>> channels with different modes if both scenarios are needed.
>>
> If there is one blocking request, no more could arrive (blocking or
> non-blocking).

Well, you are assuming that there is only one thread from within the
client driver who is gonna use the send API. There is nothing in the
code that stops from say two threads/contexts queueing in the message
from the same client driver. I am ok from my side for this to be sorted
out later, since I won't be using the blocking mode, but I do have two
threads (in DSPBridge driver) that will do a send.

 The increased code complexity doesn't justify the
> rarely used feature. I don't see many use-cases when the client can't
> release-request the channel. It's made like opening a file - blocking
> vs non-blocking is the mode you open the resource.
> 
>>> +             int ret;
>>> +             init_completion(&chan->tx_complete);
>>> +             ret = wait_for_completion_timeout(&chan->tx_complete,
>>> +                     chan->tx_tout);
>>> +             if (ret == 0) {
>>> +                     t = 0;
>>> +                     tx_tick(chan, XFER_ERR);
>>> +             }
>>> +     }
>>> +
>>> +     return t;
>>> +}
>>> +EXPORT_SYMBOL(ipc_send_message);
>>
>> Do we need to add an API similar to mailbox_msg_send_receive_no_irq, or
>> are you leaving it to be client's responsibility?
>>
> Yes the API provides enough ways for a client to do that.

I will let Loic comment on this, based on his usage/complexity in the
client. I think you got lucky with PL320 implementation since it fills
in the buffer on a Tx done, so you have folded that functionality in
send_data itself.

> 
>>> +void *ipc_request_channel(struct ipc_client *cl)
>>> +{
>>> +     struct ipc_chan *chan;
>>> +     unsigned long flags;
>>> +     int ret = 0;
>>> +
>>> +     mutex_lock(&chpool_mutex);
>>> +
>>> +     list_for_each_entry(chan, &ipc_channels, node)
>> I had a different design in mind here, maintain the list of controllers
>> globally instead of the channels, that way your search can be a bit
>> quicker.
>>
> Yeah, I changed that to it last minute :)
> The API has no real use of controller nodes, it works solely on a
> global pool of mailboxes. I tried to reflect that in code.

Can we go back to using controller nodes? I understand that the API
doesn't use much, but the list of controller nodes is gonna be static
anyway in the file. It just improves the search algorithm when looking
for a mailbox. We have a new device coming up (u-boot patches already
submitted) wherein we have 13 controller instances, each with about 4 to
6 links, a linear search would be really painful.

> 
> 
>>> + * @cntlr_data: Optional controller specific parameters during channel request
>>> + */
>>> +struct ipc_client {
>>> +     char *chan_name;
>>> +     void (*rxcb)(void *data);
>>> +     void (*txcb)(request_token_t t, enum xfer_result r);
>>> +     bool tx_block;
>>> +     unsigned long tx_tout;
>>> +     bool knows_txdone;
>>> +     void *cntlr_data;
>>
>> What is the current use-case for exposing cntrl_data through ipc_client?
>> I think this should be avoided and leave the controller configuration to
>> the controller driver implementation. This will be a problem for
>> multiple link scenarios.
>>
> There are some highly programmable controllers that, if the driver is
> proper, could change behavior runtime. For ex, if the controller
> supports, a client might want to broadcast messages to multiple
> remotes or listen for messages from more than one remote source or
> both. The client could, say, specify bitmasks for such source/sink
> remotes via cntlr_data while requesting the mailbox.  PL320 could work
> in such mode if rest all fits.

Are you configuring the specific mailbox or configuring the controller
on a whole in this particular example?

> 
> 
>>> +struct ipc_link {
>>> +     char link_name[16];
>>> +     void *api_priv;
>>> +};
>>
>> this definitely needs a link-private void *ptr. PL320 doesn't have
>> multiple links in the controller, but this is a problem for OMAP & DBX500.
>>
> The API keeps the ipc_link provided by the controller driver, which
> could have it embedded in its private representation of the h/w links.
>  For ex, my controller has 6 links, and its structure contains 6
> element array of 'struct myhw_link' which embeds an ipc_link. And I
> use container_of().

Ofcourse, that works. But I was trying to avoid it, since it streamlines
the controller implementation better - it can avoid managing another
variable to pass the links just for registration (especially if I have
to dynamically create them), and also manage the creation/static
declaration of the actual links. The mailbox/ipc core is anyway
constructing a ipc_chan above this link, and doesn't use it directly for
anything.

> 
>>> +struct ipc_link_ops {
>>> +     int (*send_data)(struct ipc_link *link, void *data);
>>> +     int (*startup)(struct ipc_link *link, void *params);
>>> +     void (*shutdown)(struct ipc_link *link);
>>> +     bool (*last_tx_done)(struct ipc_link *link);
>> minor comment, maybe rename this to something that indicates link
>> busyness or readiness
>>
> The API gives the controller only one TX at a time, so I chose the
> name. What do you suggest?

how about 'is_ready', i think it is a bit more generic name and
automatically implies there are no pending tx.

>>> +};
>>> +
>>> +/**
>>> + * struct ipc_controller - Controller of a class of communication links
>>> + * @controller_name: Literal name of the controller.
>>> + * @ops: Operators that work on each communication link
>>> + * @links: Null terminated array of links.
>>> + * @txdone_irq: Indicates if the controller can report to API when the
>>> + *    last transmitted data was read by the remote. Eg, if it has some
>>> + *    TX ACK irq.
>>> + * @txdone_poll: If the controller can read but not report the TX done.
>>> + *    Eg, is some register shows the TX status but no interrupt rises.
>>> + *    Ignored if 'txdone_irq' is set.
>>> + * @txpoll_period: If 'txdone_poll' is in effect, the API polls for
>>> + *    last TX's status after these many millisecs
>>> + */
>>> +struct ipc_controller {
>>> +     char controller_name[16];
>> i think this can be avoided and use the underlying dev-name directly
>> based on the controller device. Adding a struct device pointer would
>> automatically allow you to use the name from the probe.
>>
> Ah ha... yes. Thanks.

Is your intention to leave the dev out to the controller driver specific
structure (atleast from the OMAP example code). I was asking for this to
be part of the ipc_controller structure, use a struct device *dev
instead of controller_name, and construct the controller name from the
dev_name.

> 
>>> +     struct ipc_link_ops *ops;
>> I think this should be a property of the individual link for
>> flexibility. Right now, it probably doesn't make a difference (as seen
>> from the current mailbox code), but the moment we have one link behaving
>> differently this will make the ops implementation a bit messy.
>>
>> I think we also need a controller-specific ops, to put common stuff
>> between multiple links within the controller.
>>
> A controller is assumed to be a bunch of identical links/mailboxes.
> However the cntlr_data could still help the client specify mode in
> which it wants a mailbox behave.

Yeah, assumptions hold true until an unfortunate SoC comes up with it
:). The TI AM3352 has one link that doesn't behave quite like the other
(I am hoping to avoid using it), so I am ok with it for now. Guess we
can always change it when a concrete need arises.

I prefer to see the controller_ops for startup/shutdown atleast. This
will allow the controller code state machine to be much better
maintained and make the code look good. As I said, with our new device,
where we have 13 controllers this will be very helpful. Also from what
Andy explained, you seem to have two controllers that are quite
different from each other.

regards
Suman


From s-anna at ti.com  Mon May  6 20:02:44 2013
From: s-anna at ti.com (Suman Anna)
Date: Mon, 6 May 2013 19:02:44 -0500
Subject: [PATCHv2 0/4] mailbox: Common API
In-Reply-To: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <518844A4.8040203@ti.com>

Hi Jassi,

On 05/06/2013 02:22 AM, Jassi Brar wrote:
> Hello,
>   I have made the implementation look more proper. Also made some changes
> suggested by Suman. Changes since V1:
> 
> * Delete timer upon mailbox release
> * Filled in the stub ipc_links_unregister()
> * Check kzalloc return for errors.
> * Add the controller driver for OMAP2 class. I have taken the patch
>   for mailbox's hwmod from Suman's. The clients are yet to be converted
>   but this should be enough to convey the idea that the API could
>   work for OMAP as well. If I had access to STE documentation, I might
>   have done some implementation for U8500 as well.

The bug fixes in this series look good in general. I have provided my
design comments in the previous RFC thread [1] still, since the overall
changes here are not that much different from the RFC.

Thanks for prototyping the OMAP portions, it demonstrates the adaptation
to the new API, but I have to take a step approach in moving the current
OMAP mailbox code and making incremental changes on top of it. The
mailbox driver is the bottom-most layer in our IPC stacks, so changes at
this layer are very critical to the functional behavior.

regards
Suman

[1] http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg429678.html




From eduardo.valentin at ti.com  Mon May  6 20:20:16 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Mon, 6 May 2013 20:20:16 -0400
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <5188212D.3030904@wwwdotorg.org>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <5188212D.3030904@wwwdotorg.org>
Message-ID: <518848C0.2020808@ti.com>

On 06-05-2013 17:31, Stephen Warren wrote:
> On 05/06/2013 03:00 PM, Eduardo Valentin wrote:
>> Introduce HAS_BANDGAP config entry. This config is a
>> boolean value so that arch code can flag is they
>> feature a bandgap device.
> 
> What does this patch have to do with device tree (there's "dts" in the
> subject)? What's a BANDGAP device?
> 
> 
In fact, this one has nothing to do with DT. dts in the title is a typo..



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From eduardo.valentin at ti.com  Mon May  6 20:23:13 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Mon, 6 May 2013 20:23:13 -0400
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <20130506223653.GA12089@obsidianresearch.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
 <20130506223653.GA12089@obsidianresearch.com>
Message-ID: <51884971.9050508@ti.com>

On 06-05-2013 18:36, Jason Gunthorpe wrote:
> On Tue, May 07, 2013 at 12:34:13AM +0300, Aaro Koskinen wrote:
>> On Mon, May 06, 2013 at 05:00:56PM -0400, Eduardo Valentin wrote:
>>> Introduce HAS_BANDGAP config entry. This config is a
>>> boolean value so that arch code can flag is they
>>> feature a bandgap device.
>>
>> Maybe it could be mentioned that omap-thermal already depend on this?
>> At least for a random reviewer it was not immediately clear why this is
>> added, especially since there were no users for it in subsequent patches.
> 
> I looked (very briefly), and it seemed like omap-thermal is self
> contained and doesn't need arch support?
> 

It is. At least I tried to make it, at least to the extenstion I could get.

> I get the impression it is desired to minimize driver kconfig
> dependencies to the minimum required to compile to increase build
> testing coverage, so maybe it would be appropriate to drop this
> entirely?
> 

Well, it is also desired to compile things to the correct target right?
Thats the idea behind this config option. It follows the same design as
CONFIG_ARCH_HAS_CPUFREQ, for instance.

> Jason
> 
> 


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From jgunthorpe at obsidianresearch.com  Mon May  6 20:36:51 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Mon, 6 May 2013 18:36:51 -0600
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <51884971.9050508@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
 <20130506223653.GA12089@obsidianresearch.com>
 <51884971.9050508@ti.com>
Message-ID: <20130507003651.GA26035@obsidianresearch.com>

On Mon, May 06, 2013 at 08:23:13PM -0400, Eduardo Valentin wrote:

> > I get the impression it is desired to minimize driver kconfig
> > dependencies to the minimum required to compile to increase build
> > testing coverage, so maybe it would be appropriate to drop this
> > entirely?

> Well, it is also desired to compile things to the correct target
> right?

There is some of that too..

But broadly the direction seems that drivers should have minimal
dependencies so, eg, the thermal maintainer compiling for x86 should
be able to compile test/static analyze your driver..

> Thats the idea behind this config option. It follows the same design as
> CONFIG_ARCH_HAS_CPUFREQ, for instance.

That is entirely contained inside arch/arm and doesn't involve
drivers.

Jason


From Wenyou.Yang at atmel.com  Mon May  6 21:11:17 2013
From: Wenyou.Yang at atmel.com (Yang, Wenyou)
Date: Tue, 7 May 2013 01:11:17 +0000
Subject: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
 xfer->speed_hz set
In-Reply-To: <20130506103105.GB13472@opensource.wolfsonmicro.com>
References: <1362626715-6549-1-git-send-email-wenyou.yang@atmel.com>
 <1362626815-6628-1-git-send-email-wenyou.yang@atmel.com>
 <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
 <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>
 <CACQ1gAhZO3stjrwf5SiZf7jOO8T5bAJZiz97M7+7vwFmk2e65g@mail.gmail.com>
 <5182414F.1000201@atmel.com>
 <20130506103105.GB13472@opensource.wolfsonmicro.com>
Message-ID: <B256D81BAE5131468A838E5D7A24364154238AF5@penmbx02>

Hi, Mark

> From: Mark Brown [mailto:broonie at kernel.org]
> Sent: 2013?5?6? 18:31
> To: Ferre, Nicolas
> Cc: grant.likely at secretlab.ca; Grant Likely; Richard Genoud; Yang, Wenyou;
> Joachim Eastwood; linux-arm-kernel at lists.infradead.org;
> plagnioj at jcrosoft.com; Lin, JM; spi-devel-general at lists.sourceforge.net;
> linux-kernel at vger.kernel.org
> Subject: Re: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
> xfer->speed_hz set
> 
> On Thu, May 02, 2013 at 12:34:55PM +0200, Nicolas Ferre wrote:
> 
> > Can you tell us if this SPI patch will be merged upstream using one of
> > your paths?
> 
> I have no idea what patch this is but if it's not in my tree -next it's unlikely to be
> merged.
This is dropped patch, no need to be merged.

We tested Atmel spi in your tree-next , but it doesn't work, the reason is the Joachim Eastwood's patch is not included. 
https://patchwork.kernel.org/patch/2165301/
which Joachim said that Grant said he applied.

Thanks

Best Regards,
Wenyou Yang

From haojian.zhuang at gmail.com  Mon May  6 21:48:47 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 7 May 2013 09:48:47 +0800
Subject: [PATCH 2/2] rtc: pxa: add pxa95x rtc support
In-Reply-To: <1367889447-15619-3-git-send-email-chao.xie@marvell.com>
References: <1367889447-15619-1-git-send-email-chao.xie@marvell.com>
 <1367889447-15619-3-git-send-email-chao.xie@marvell.com>
Message-ID: <CAN1soZxQQTQG1CdNGYmCDfddLHWA5HVZ+SWjFhcfidsdGazprw@mail.gmail.com>

On Tue, May 7, 2013 at 9:17 AM, Chao Xie <chao.xie at marvell.com> wrote:
> the pxa95x rtc need access PBSR register before write to RTTR, RCNR, RDCR, and RYCR registers.
>
> Signed-off-by: Chao Xie <chao.xie at marvell.com>
> ---

Do we really need this for other SoC? PXA95x is removed already since
it's a block on supporting
multi-platform & not used widely.

Regards
Haojian


From robherring2 at gmail.com  Mon May  6 21:58:28 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 06 May 2013 20:58:28 -0500
Subject: [PATCHv2 3/4] mailbox: pl320: Introduce common API driver
In-Reply-To: <1367825063-6263-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825063-6263-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <51885FC4.7000401@gmail.com>

On 05/06/2013 02:24 AM, Jassi Brar wrote:
> Convert the PL320 controller driver to work with the common
> mailbox API. Also convert the only user of PL320, highbank-cpufreq.c
> to work with thee API. Drop the obsoleted driver pl320-ipc.c
> 
> Signed-off-by: Jassi Brar <jaswinder.singh at linaro.org>
> ---
>  drivers/cpufreq/highbank-cpufreq.c |   22 +++-
>  drivers/mailbox/Makefile           |    2 +-
>  drivers/mailbox/pl320-ipc.c        |  198 ---------------------------------
>  drivers/mailbox/pl320.c            |  212 ++++++++++++++++++++++++++++++++++++

Can you resend this using git format-patch -M option.

Rob

>  include/linux/pl320-ipc.h          |   17 ---
>  5 files changed, 233 insertions(+), 218 deletions(-)
>  delete mode 100644 drivers/mailbox/pl320-ipc.c
>  create mode 100644 drivers/mailbox/pl320.c
>  delete mode 100644 include/linux/pl320-ipc.h
> 
> diff --git a/drivers/cpufreq/highbank-cpufreq.c b/drivers/cpufreq/highbank-cpufreq.c
> index 3118b87..5c057e0 100644
> --- a/drivers/cpufreq/highbank-cpufreq.c
> +++ b/drivers/cpufreq/highbank-cpufreq.c
> @@ -19,7 +19,7 @@
>  #include <linux/cpu.h>
>  #include <linux/err.h>
>  #include <linux/of.h>
> -#include <linux/pl320-ipc.h>
> +#include <linux/mailbox_client.h>
>  #include <linux/platform_device.h>
>  
>  #define HB_CPUFREQ_CHANGE_NOTE	0x80000001
> @@ -29,8 +29,26 @@
>  static int hb_voltage_change(unsigned int freq)
>  {
>  	u32 msg[HB_CPUFREQ_IPC_LEN] = {HB_CPUFREQ_CHANGE_NOTE, freq / 1000000};
> +	struct ipc_client cl;
> +	int ret = -ETIMEDOUT;
> +	void *chan;
>  
> -	return pl320_ipc_transmit(msg);
> +	cl.rxcb = NULL;
> +	cl.txcb = NULL;
> +	cl.tx_block = true;
> +	cl.tx_tout = 1000; /* 1 sec */
> +	cl.cntlr_data = NULL;
> +	cl.knows_txdone = false;
> +	cl.chan_name = "pl320:A9_to_M3";
> +
> +	chan = ipc_request_channel(&cl);
> +
> +	if (ipc_send_message(chan, (void *)msg))
> +		ret = msg[1]; /* PL320 updates buffer with FIFO after ACK */
> +
> +	ipc_free_channel(chan);
> +
> +	return ret;
>  }
>  
>  static int hb_cpufreq_clk_notify(struct notifier_block *nb,
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index fefef7e..7b897f3 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -2,4 +2,4 @@
>  
>  obj-$(CONFIG_MAILBOX)		+= mailbox.o
>  
> -obj-$(CONFIG_PL320_MBOX)	+= pl320-ipc.o
> +obj-$(CONFIG_PL320_MBOX)	+= pl320.o
> diff --git a/drivers/mailbox/pl320-ipc.c b/drivers/mailbox/pl320-ipc.c
> deleted file mode 100644
> index f3755e0..0000000
> --- a/drivers/mailbox/pl320-ipc.c
> +++ /dev/null
> @@ -1,198 +0,0 @@
> -/*
> - * Copyright 2012 Calxeda, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program.  If not, see <http://www.gnu.org/licenses/>.
> - */
> -#include <linux/types.h>
> -#include <linux/err.h>
> -#include <linux/delay.h>
> -#include <linux/export.h>
> -#include <linux/io.h>
> -#include <linux/interrupt.h>
> -#include <linux/completion.h>
> -#include <linux/mutex.h>
> -#include <linux/notifier.h>
> -#include <linux/spinlock.h>
> -#include <linux/device.h>
> -#include <linux/amba/bus.h>
> -
> -#include <linux/pl320-ipc.h>
> -
> -#define IPCMxSOURCE(m)		((m) * 0x40)
> -#define IPCMxDSET(m)		(((m) * 0x40) + 0x004)
> -#define IPCMxDCLEAR(m)		(((m) * 0x40) + 0x008)
> -#define IPCMxDSTATUS(m)		(((m) * 0x40) + 0x00C)
> -#define IPCMxMODE(m)		(((m) * 0x40) + 0x010)
> -#define IPCMxMSET(m)		(((m) * 0x40) + 0x014)
> -#define IPCMxMCLEAR(m)		(((m) * 0x40) + 0x018)
> -#define IPCMxMSTATUS(m)		(((m) * 0x40) + 0x01C)
> -#define IPCMxSEND(m)		(((m) * 0x40) + 0x020)
> -#define IPCMxDR(m, dr)		(((m) * 0x40) + ((dr) * 4) + 0x024)
> -
> -#define IPCMMIS(irq)		(((irq) * 8) + 0x800)
> -#define IPCMRIS(irq)		(((irq) * 8) + 0x804)
> -
> -#define MBOX_MASK(n)		(1 << (n))
> -#define IPC_TX_MBOX		1
> -#define IPC_RX_MBOX		2
> -
> -#define CHAN_MASK(n)		(1 << (n))
> -#define A9_SOURCE		1
> -#define M3_SOURCE		0
> -
> -static void __iomem *ipc_base;
> -static int ipc_irq;
> -static DEFINE_MUTEX(ipc_m1_lock);
> -static DECLARE_COMPLETION(ipc_completion);
> -static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
> -
> -static inline void set_destination(int source, int mbox)
> -{
> -	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
> -	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
> -}
> -
> -static inline void clear_destination(int source, int mbox)
> -{
> -	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
> -	__raw_writel(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
> -}
> -
> -static void __ipc_send(int mbox, u32 *data)
> -{
> -	int i;
> -	for (i = 0; i < 7; i++)
> -		__raw_writel(data[i], ipc_base + IPCMxDR(mbox, i));
> -	__raw_writel(0x1, ipc_base + IPCMxSEND(mbox));
> -}
> -
> -static u32 __ipc_rcv(int mbox, u32 *data)
> -{
> -	int i;
> -	for (i = 0; i < 7; i++)
> -		data[i] = __raw_readl(ipc_base + IPCMxDR(mbox, i));
> -	return data[1];
> -}
> -
> -/* blocking implmentation from the A9 side, not usuable in interrupts! */
> -int pl320_ipc_transmit(u32 *data)
> -{
> -	int ret;
> -
> -	mutex_lock(&ipc_m1_lock);
> -
> -	init_completion(&ipc_completion);
> -	__ipc_send(IPC_TX_MBOX, data);
> -	ret = wait_for_completion_timeout(&ipc_completion,
> -					  msecs_to_jiffies(1000));
> -	if (ret == 0) {
> -		ret = -ETIMEDOUT;
> -		goto out;
> -	}
> -
> -	ret = __ipc_rcv(IPC_TX_MBOX, data);
> -out:
> -	mutex_unlock(&ipc_m1_lock);
> -	return ret;
> -}
> -EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
> -
> -static irqreturn_t ipc_handler(int irq, void *dev)
> -{
> -	u32 irq_stat;
> -	u32 data[7];
> -
> -	irq_stat = __raw_readl(ipc_base + IPCMMIS(1));
> -	if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
> -		__raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
> -		complete(&ipc_completion);
> -	}
> -	if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
> -		__ipc_rcv(IPC_RX_MBOX, data);
> -		atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
> -		__raw_writel(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
> -	}
> -
> -	return IRQ_HANDLED;
> -}
> -
> -int pl320_ipc_register_notifier(struct notifier_block *nb)
> -{
> -	return atomic_notifier_chain_register(&ipc_notifier, nb);
> -}
> -EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
> -
> -int pl320_ipc_unregister_notifier(struct notifier_block *nb)
> -{
> -	return atomic_notifier_chain_unregister(&ipc_notifier, nb);
> -}
> -EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
> -
> -static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
> -{
> -	int ret;
> -
> -	ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
> -	if (ipc_base == NULL)
> -		return -ENOMEM;
> -
> -	__raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
> -
> -	ipc_irq = adev->irq[0];
> -	ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
> -	if (ret < 0)
> -		goto err;
> -
> -	/* Init slow mailbox */
> -	__raw_writel(CHAN_MASK(A9_SOURCE),
> -			ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
> -	__raw_writel(CHAN_MASK(M3_SOURCE),
> -			ipc_base + IPCMxDSET(IPC_TX_MBOX));
> -	__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
> -		     ipc_base + IPCMxMSET(IPC_TX_MBOX));
> -
> -	/* Init receive mailbox */
> -	__raw_writel(CHAN_MASK(M3_SOURCE),
> -			ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
> -	__raw_writel(CHAN_MASK(A9_SOURCE),
> -			ipc_base + IPCMxDSET(IPC_RX_MBOX));
> -	__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
> -		     ipc_base + IPCMxMSET(IPC_RX_MBOX));
> -
> -	return 0;
> -err:
> -	iounmap(ipc_base);
> -	return ret;
> -}
> -
> -static struct amba_id pl320_ids[] = {
> -	{
> -		.id	= 0x00041320,
> -		.mask	= 0x000fffff,
> -	},
> -	{ 0, 0 },
> -};
> -
> -static struct amba_driver pl320_driver = {
> -	.drv = {
> -		.name	= "pl320",
> -	},
> -	.id_table	= pl320_ids,
> -	.probe		= pl320_probe,
> -};
> -
> -static int __init ipc_init(void)
> -{
> -	return amba_driver_register(&pl320_driver);
> -}
> -module_init(ipc_init);
> diff --git a/drivers/mailbox/pl320.c b/drivers/mailbox/pl320.c
> new file mode 100644
> index 0000000..7ddae5c
> --- /dev/null
> +++ b/drivers/mailbox/pl320.c
> @@ -0,0 +1,212 @@
> +/*
> + * Copyright 2012 Calxeda, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/types.h>
> +#include <linux/err.h>
> +#include <linux/delay.h>
> +#include <linux/export.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/completion.h>
> +#include <linux/mutex.h>
> +#include <linux/notifier.h>
> +#include <linux/spinlock.h>
> +#include <linux/device.h>
> +#include <linux/amba/bus.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/mailbox_controller.h>
> +
> +#define IPCMSOURCE(m)		((m) * 0x40)
> +#define IPCMDSET(m)		(((m) * 0x40) + 0x004)
> +#define IPCMDCLEAR(m)		(((m) * 0x40) + 0x008)
> +#define IPCMDSTATUS(m)		(((m) * 0x40) + 0x00C)
> +#define IPCMMODE(m)		(((m) * 0x40) + 0x010)
> +#define IPCMMSET(m)		(((m) * 0x40) + 0x014)
> +#define IPCMMCLEAR(m)		(((m) * 0x40) + 0x018)
> +#define IPCMMSTATUS(m)		(((m) * 0x40) + 0x01C)
> +#define IPCMSEND(m)		(((m) * 0x40) + 0x020)
> +#define IPCMDR(m, dr)		(((m) * 0x40) + ((dr) * 4) + 0x024)
> +
> +#define IPCMMIS(irq)		(((irq) * 8) + 0x800)
> +#define IPCMRIS(irq)		(((irq) * 8) + 0x804)
> +
> +#define MBOX_MASK(n)		(1 << (n))
> +#define IPC_TX_MBOX		1
> +
> +#define CHAN_MASK(n)		(1 << (n))
> +#define A9_SOURCE		1
> +#define M3_SOURCE		0
> +
> +struct pl320_con {
> +	u32 *data;
> +	int ipc_irq;
> +	struct device *dev;
> +	struct ipc_link link;
> +	void __iomem *ipc_base;
> +	struct ipc_controller ipc_con;
> +};
> +
> +static inline struct pl320_con *to_pl320(struct ipc_link *l)
> +{
> +	if (!l)
> +		return NULL;
> +
> +	return container_of(l, struct pl320_con, link);
> +}
> +
> +static irqreturn_t ipc_handler(int irq, void *p)
> +{
> +	struct ipc_link *link = (struct ipc_link *)p;
> +	struct pl320_con *pl320 = to_pl320(link);
> +	void __iomem *ipc_base = pl320->ipc_base;
> +	u32 irq_stat;
> +
> +	irq_stat = __raw_readl(ipc_base + IPCMMIS(1));
> +	if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
> +		u32 *data = pl320->data;
> +		int i;
> +
> +		__raw_writel(0, ipc_base + IPCMSEND(IPC_TX_MBOX));
> +
> +		/*
> +		 * The PL320 driver specifies that the send buffer
> +		 * will be overwritten by same fifo upon TX ACK.
> +		 */
> +		for (i = 0; i < 7; i++)
> +			data[i] = __raw_readl(ipc_base
> +					 + IPCMDR(IPC_TX_MBOX, i));
> +
> +		ipc_link_txdone(link, XFER_OK);
> +
> +		pl320->data = NULL;
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int pl320_send_data(struct ipc_link *link, void *msg)
> +{
> +	struct pl320_con *pl320 = to_pl320(link);
> +	void __iomem *ipc_base = pl320->ipc_base;
> +	u32 *data = (u32 *)msg;
> +	int i;
> +
> +	pl320->data = data;
> +
> +	for (i = 0; i < 7; i++)
> +		__raw_writel(data[i], ipc_base + IPCMDR(IPC_TX_MBOX, i));
> +
> +	__raw_writel(0x1, ipc_base + IPCMSEND(IPC_TX_MBOX));
> +
> +	return 0;
> +}
> +
> +static int pl320_startup(struct ipc_link *link, void *ignored)
> +{
> +	struct pl320_con *pl320 = to_pl320(link);
> +	void __iomem *ipc_base = pl320->ipc_base;
> +	int err, ipc_irq = pl320->ipc_irq;
> +
> +	__raw_writel(0, ipc_base + IPCMSEND(IPC_TX_MBOX));
> +
> +	err = request_irq(ipc_irq, ipc_handler, 0, dev_name(pl320->dev), link);
> +	if (err)
> +		return err;
> +
> +	/* Init slow mailbox */
> +	__raw_writel(CHAN_MASK(A9_SOURCE),
> +			ipc_base + IPCMSOURCE(IPC_TX_MBOX));
> +	__raw_writel(CHAN_MASK(M3_SOURCE),
> +			ipc_base + IPCMDSET(IPC_TX_MBOX));
> +	__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
> +		     ipc_base + IPCMMSET(IPC_TX_MBOX));
> +
> +	pl320->data = NULL;
> +	return 0;
> +}
> +
> +static void pl320_shutdown(struct ipc_link *link)
> +{
> +	struct pl320_con *pl320 = to_pl320(link);
> +
> +	pl320->data = NULL;
> +	free_irq(pl320->ipc_irq, link);
> +}
> +
> +static struct ipc_link_ops pl320_ops = {
> +	.send_data = pl320_send_data,
> +	.startup = pl320_startup,
> +	.shutdown = pl320_shutdown,
> +};
> +
> +static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> +	struct pl320_con *pl320;
> +	struct ipc_link *l[2];
> +	int ret;
> +
> +	pl320 = kzalloc(sizeof(struct pl320_con), GFP_KERNEL);
> +	if (!pl320)
> +		return -ENOMEM;
> +
> +	pl320->ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
> +	if (pl320->ipc_base == NULL) {
> +		kfree(pl320);
> +		return -ENOMEM;
> +	}
> +
> +	pl320->dev = &adev->dev;
> +	pl320->ipc_irq = adev->irq[0];
> +	amba_set_drvdata(adev, pl320);
> +
> +	l[0] = &pl320->link;
> +	l[1] = NULL;
> +	pl320->ipc_con.links = l;
> +	pl320->ipc_con.txdone_irq = true;
> +	pl320->ipc_con.ops = &pl320_ops;
> +	snprintf(pl320->link.link_name, 16, "A9_to_M3");
> +	snprintf(pl320->ipc_con.controller_name, 16, "pl320");
> +
> +	ret = ipc_links_register(&pl320->ipc_con);
> +	if (ret) {
> +		iounmap(pl320->ipc_base);
> +		kfree(pl320);
> +	}
> +
> +	return ret;
> +}
> +
> +static struct amba_id pl320_ids[] = {
> +	{
> +		.id	= 0x00041320,
> +		.mask	= 0x000fffff,
> +	},
> +	{ 0, 0 },
> +};
> +
> +static struct amba_driver pl320_driver = {
> +	.drv = {
> +		.name	= "pl320",
> +	},
> +	.id_table	= pl320_ids,
> +	.probe		= pl320_probe,
> +};
> +
> +static int __init ipc_init(void)
> +{
> +	return amba_driver_register(&pl320_driver);
> +}
> +module_init(ipc_init);
> diff --git a/include/linux/pl320-ipc.h b/include/linux/pl320-ipc.h
> deleted file mode 100644
> index 5161f63..0000000
> --- a/include/linux/pl320-ipc.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/*
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program.  If not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -int pl320_ipc_transmit(u32 *data);
> -int pl320_ipc_register_notifier(struct notifier_block *nb);
> -int pl320_ipc_unregister_notifier(struct notifier_block *nb);
> 



From shawn.guo at linaro.org  Mon May  6 22:56:12 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 7 May 2013 10:56:12 +0800
Subject: [PATCH v2 2/2] dma: imx-sdma: move to generic device tree bindings
In-Reply-To: <20130430105105.GG1960@intel.com>
References: <1366901008-7593-1-git-send-email-shawn.guo@linaro.org>
 <1366901008-7593-3-git-send-email-shawn.guo@linaro.org>
 <20130430105105.GG1960@intel.com>
Message-ID: <20130507025609.GA10851@S2101-09.ap.freescale.net>

On Tue, Apr 30, 2013 at 04:21:05PM +0530, Vinod Koul wrote:
> On Thu, Apr 25, 2013 at 10:43:28PM +0800, Shawn Guo wrote:
> > Update imx-sdma driver to adopt generic DMA device tree bindings.  It
> > calls of_dma_controller_register() with imx-sdma specific of_dma_xlate
> > to get the generic DMA device tree helper support.  The #dma-cells for
> > imx-sdma must be 3, which includes request ID, peripheral type and
> > priority.
> > 
> > The definitions of peripheral type and priority get moved into
> > include/dt-bindings/dma/imx.h, so that the macros can also be used in
> > dts files.
> > 
> > The existing way of requesting channel, clients directly call
> > dma_request_channel(), still work there, and will be removed after
> > all imx-sdma clients get converted to generic DMA device tree helper.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Looks fine to me, Arnd?

ping.

I was hoping we can get this in with 3.10 merge window, and start
convert client device drivers to it during 3.11 development cycle.
Is it still possible?

Shawn



From padma.v at samsung.com  Mon May  6 23:37:33 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 09:07:33 +0530
Subject: [PATCH] ARM: dts: Correct the base address of pinctrl_3
Message-ID: <1367897853-18403-1-git-send-email-padma.v@samsung.com>

This patch corrects the base address of pinctrl_3 on Exynos5250
platform.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---

This patch is dependent on below patch posted by Thomas Abraham.
https://patchwork.kernel.org/patch/2225151/

 arch/arm/boot/dts/exynos5250-pinctrl.dtsi |    2 +-
 arch/arm/boot/dts/exynos5250.dtsi         |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb..ded558b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -763,7 +763,7 @@
 		};
 	};
 
-	pinctrl at 03680000 {
+	pinctrl at 03860000 {
 		gpz: gpz {
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4bd9e9c..51f0a7e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -155,9 +155,9 @@
 		interrupts = <0 50 0>;
 	};
 
-	pinctrl_3: pinctrl at 03680000 {
+	pinctrl_3: pinctrl at 03860000 {
 		compatible = "samsung,exynos5250-pinctrl";
-		reg = <0x0368000 0x1000>;
+		reg = <0x03860000 0x1000>;
 		interrupts = <0 47 0>;
 	};
 
-- 
1.7.4.4



From padma.v at samsung.com  Mon May  6 23:39:01 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 09:09:01 +0530
Subject: [PATCH] ASoC: Samsung: i2s: Fix crash in i2s driver
Message-ID: <1367897941-18439-1-git-send-email-padma.v@samsung.com>

This patch fixes a null pointer deference in i2s driver in DT
case

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---

This patch is dependent on below patch posted by Thomas Abraham.
https://patchwork.kernel.org/patch/2224801/

 sound/soc/samsung/i2s.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 7ce7c50..eaf6439 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -1182,7 +1182,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
 		pri_dai->sec_dai = sec_dai;
 	}
 
-	if (i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
+	if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
 		dev_err(&pdev->dev, "Unable to configure gpio\n");
 		ret = -EINVAL;
 		goto err;
-- 
1.7.4.4



From hvaibhav at ti.com  Mon May  6 23:53:13 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Tue, 7 May 2013 03:53:13 +0000
Subject: mach-omap2/timer.c: Bug introduced while merging patch - ff931c82
In-Reply-To: <20130506233743.GJ28721@atomide.com>
References: <79CD15C6BA57404B839C016229A409A83EC7C45D@DBDE04.ent.ti.com>
 <20130506152706.GD28721@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EC7C93A@DBDE04.ent.ti.com>
 <20130506233743.GJ28721@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC7CB23@DBDE04.ent.ti.com>

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, May 07, 2013 5:08 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; linux-kernel at vger.kernel.org; linux-
> arm-kernel at lists.infradead.org
> Subject: Re: mach-omap2/timer.c: Bug introduced while merging patch -
> ff931c82
> 
> * Hiremath, Vaibhav <hvaibhav at ti.com> [130506 11:35]:
> >
> > Ohh yeah, I already have a patch for it -
> 
> Thanks, I'll add that into omap-for-v3.10/fixes. I modified
> the comments a bit trying to figure out where it changed, updated
> patch below.
> 

Thanks Tony. 

Thanks,
Vaibhav


From s.hauer at pengutronix.de  Tue May  7 00:58:13 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 7 May 2013 06:58:13 +0200
Subject: [PATCH] ARM: dts: Correct the base address of pinctrl_3
In-Reply-To: <1367897853-18403-1-git-send-email-padma.v@samsung.com>
References: <1367897853-18403-1-git-send-email-padma.v@samsung.com>
Message-ID: <20130507045813.GN32299@pengutronix.de>

Hi,

On Tue, May 07, 2013 at 09:07:33AM +0530, Padmavathi Venna wrote:
> This patch corrects the base address of pinctrl_3 on Exynos5250
> platform.

Exynos5250 should be part of the subject so that other people can know
whether this patch is interesting for them or not.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From padma.kvr at gmail.com  Tue May  7 01:41:15 2013
From: padma.kvr at gmail.com (Padma Venkat)
Date: Tue, 7 May 2013 11:11:15 +0530
Subject: [PATCH] ARM: dts: Correct the base address of pinctrl_3
In-Reply-To: <20130507045813.GN32299@pengutronix.de>
References: <1367897853-18403-1-git-send-email-padma.v@samsung.com>
 <20130507045813.GN32299@pengutronix.de>
Message-ID: <CAAgF-Bc4c7CEuOZQFo9Ar7zo+jHOx0re6_Un5xzWSxw5oojjNQ@mail.gmail.com>

Hi,

On Tue, May 7, 2013 at 10:28 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Hi,
>
> On Tue, May 07, 2013 at 09:07:33AM +0530, Padmavathi Venna wrote:
>> This patch corrects the base address of pinctrl_3 on Exynos5250
>> platform.
>
> Exynos5250 should be part of the subject so that other people can know
> whether this patch is interesting for them or not.

Okey. I will resend the patch.

Thanks
Padma
>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From giridhar.maruthy at linaro.org  Tue May  7 01:51:50 2013
From: giridhar.maruthy at linaro.org (giridhar.maruthy at linaro.org)
Date: Tue,  7 May 2013 11:21:50 +0530
Subject: [RFC PATCH V2] ARM: EXYNOS: Fix hotplug when CPUs boot in HYP mode
Message-ID: <1367905910-30913-1-git-send-email-giridhar.m@samsung.com>

From: Giridhar Maruthy <giridhar.maruthy at linaro.org>

In intial boot-up, u-boot commit "3d28a181aab5e... arndale5250: Boot in Hyp
mode and enable architected timers" puts the CPUs in HYP mode.

Hence, the CPUs need to be put in HYP mode when they are hot plugged out and
plugged in back.

This patch is almost same as above u-boot patch, it additionally takes care
if the kernel is compiled with thumb-2 option.

Signed-off-by: Giridhar Maruthy <giridhar.m at samsung.com>
Signed-off-by: Inderpal Singh <inderpal.singh at linaro.org>
---
 arch/arm/mach-exynos/headsmp.S |  114 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index 5364d4b..a837941 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -12,6 +12,7 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/assembler.h>
 
 	__CPUINIT
 
@@ -20,6 +21,98 @@
  * a "holding pen" into which all secondary cores are held until we're
  * ready for them to initialise.
  */
+
+.arch_extension sec
+.arch_extension virt
+.text
+
+.align 5
+/* We use the same vector table for Hyp and Monitor mode, since
+ * we will only use each once and they don't overlap.
+ */
+mon_vectors:
+	W(b)	.	/* reset */
+	W(b)	.	/* undef */
+	W(b)	2f	/* smc */
+	W(b)	.	/* pabt */
+	W(b)	.	/* dabt */
+	W(b)	1f	/* hyp */
+	W(b)	.	/* irq */
+	W(b)	.	/* fiq */
+
+/* Return directly back to the caller without leaving Hyp mode: */
+1:	mrs	lr, elr_hyp
+	mov	pc, lr
+
+/* In monitor mode, set up HVBAR and SCR then return to caller in NS-SVC. */
+2:
+	mrc	p15, 0, r1, c1, c1, 0		@ SCR
+	/*
+	 * Set SCR.NS=1(needed for setting HVBAR and also returning to NS state)
+	 *        .IRQ,FIQ,EA=0 (don't take aborts/exceptions to Monitor mode)
+	 *        .FW,AW=1 (CPSR.A,F modifiable in NS state)
+	 *        .nET=0 (early termination OK)
+	 *        .SCD=0 (SMC in NS mode OK, so we can call secure firmware)
+	 *        .HCE=1 (HVC does Hyp call)
+	 */
+	bic	r1, r1, #0x07f
+	ldr	r2, =0x131
+	orr	r1, r1, r2
+	mcr	p15, 0, r2, c1, c1, 0		@ SCR
+	isb
+	ldr	r2, =mon_vectors
+
+
+	adr	r4, 1f
+	ldmia	r4, {r5}
+	sub	r4, r4, r5
+	add	r2, r2, r4
+
+	mcr	p15, 4, r2, c12, c0, 0		@ set HVBAR
+
+ THUMB(	mrc	p15, 4, r2, c1, c0, 0 )		@ ctrl register
+ THUMB(	orr	r2, r2, #1 << 30 )		@ HSCTLR.TE (Thumb exceptions)
+ THUMB(	mcr	p15, 4, r2, c1, c0, 0 )
+ THUMB(	isb)
+
+	/* ...and return to calling code in NS state */
+	movs	pc, lr
+
+
+	.globl monitor_init
+monitor_init:
+	ldr	ip, =mon_vectors
+
+	adr	r4, 1f
+	ldmia	r4, {r5}
+	sub	r4, r4, r5
+	add	ip, ip, r4
+	mcr	p15, 0, ip, c12, c0, 1
+
+ THUMB(	mrc     p15, 0, r1, c1, c0, 0 )		@ ctrl register
+ THUMB( orr     r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
+ THUMB( mcr     p15, 0, r1, c1, c0, 0 )
+ THUMB( isb )
+
+	mov	pc, lr
+
+	/* Try to go into NS-SVC: void enter_ns(void); */
+	.globl enter_ns
+enter_ns:
+	smc	#0
+	mov	pc, lr
+
+	/* void enter_hyp(void); */
+	.globl enter_hyp
+enter_hyp:
+	/* Now we're in NS-SVC, make a Hyp call to get into Hyp mode */
+	mov	r0, lr
+	mov	r1, sp
+	hvc	#0
+	/* We will end up here in NS-Hyp. */
+	mov	sp, r1
+	mov	pc, r0
+
 ENTRY(exynos4_secondary_startup)
 	mrc	p15, 0, r0, c0, c0, 5
 	and	r0, r0, #15
@@ -31,6 +124,27 @@ pen:	ldr	r7, [r6]
 	cmp	r7, r0
 	bne	pen
 
+	ldr	r1, =__boot_cpu_mode
+	add	r1, r1, r4
+	ldr	r2, [r1]
+	mrs     r0, cpsr
+	ands	r0, r0, #MODE_MASK
+	subs	r1, r0, r2
+	beq	3f
+	subs	r2, r2, #HYP_MODE
+	bne	3f
+
+	/* Setting NSACR to allow coprocessor access from non-secure mode */
+	mrc	p15, 0, r0, c1, c1, 2
+	movw	r1, #0x3fff
+	orr	r0, r0, r1
+	mcr	p15, 0, r0, c1, c1, 2
+5:
+	bl	monitor_init
+	bl	enter_ns
+	bl	enter_hyp
+
+3:
 	/*
 	 * we've been released from the holding pen: secondary_stack
 	 * should now contain the SVC stack for this core
-- 
1.7.9.5



From giridhar.maruthy at linaro.org  Tue May  7 01:54:43 2013
From: giridhar.maruthy at linaro.org (Giridhar Maruthy)
Date: Tue, 7 May 2013 11:24:43 +0530
Subject: [RFC PATCH V2] ARM: EXYNOS: Fix hotplug when CPUs boot in HYP mode
In-Reply-To: <1367905910-30913-1-git-send-email-giridhar.m@samsung.com>
References: <1367905910-30913-1-git-send-email-giridhar.m@samsung.com>
Message-ID: <CAHuqX+HUWcX_sTXKCjSQ9pR1K8obLc+T7vYK_zTn_gqO8ULPVQ@mail.gmail.com>

This patch is a modification from the Christoffer Dall's u-boot
patch. This is required to put the secondary processors in hyp
mode during cpu hotplug when u-boot is no longer alive.

Marc Zyngier suggested this logic to go into firmware or, u-boot
putting a trampoline code into a page /memreserve/d by DT. But
this seemed to have a problem. Once the cpu is hotplugged in
runtime, the control is in ROM code and waits for event.
Kernel provides a return address in kernel to which the processor
jumps once it gets an event. If the control branches to the
trampoline code here, this trampoline code has no kernel return
address.

Someone with better logic or better placement of this logic
elsewhere is welcome.

Regards,
Giridhar

On 7 May 2013 11:21,  <giridhar.maruthy at linaro.org> wrote:
> From: Giridhar Maruthy <giridhar.maruthy at linaro.org>
>
> In intial boot-up, u-boot commit "3d28a181aab5e... arndale5250: Boot in Hyp
> mode and enable architected timers" puts the CPUs in HYP mode.
>
> Hence, the CPUs need to be put in HYP mode when they are hot plugged out and
> plugged in back.
>
> This patch is almost same as above u-boot patch, it additionally takes care
> if the kernel is compiled with thumb-2 option.
>
> Signed-off-by: Giridhar Maruthy <giridhar.m at samsung.com>
> Signed-off-by: Inderpal Singh <inderpal.singh at linaro.org>
> ---
>  arch/arm/mach-exynos/headsmp.S |  114 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 114 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
> index 5364d4b..a837941 100644
> --- a/arch/arm/mach-exynos/headsmp.S
> +++ b/arch/arm/mach-exynos/headsmp.S
> @@ -12,6 +12,7 @@
>   */
>  #include <linux/linkage.h>
>  #include <linux/init.h>
> +#include <asm/assembler.h>
>
>         __CPUINIT
>
> @@ -20,6 +21,98 @@
>   * a "holding pen" into which all secondary cores are held until we're
>   * ready for them to initialise.
>   */
> +
> +.arch_extension sec
> +.arch_extension virt
> +.text
> +
> +.align 5
> +/* We use the same vector table for Hyp and Monitor mode, since
> + * we will only use each once and they don't overlap.
> + */
> +mon_vectors:
> +       W(b)    .       /* reset */
> +       W(b)    .       /* undef */
> +       W(b)    2f      /* smc */
> +       W(b)    .       /* pabt */
> +       W(b)    .       /* dabt */
> +       W(b)    1f      /* hyp */
> +       W(b)    .       /* irq */
> +       W(b)    .       /* fiq */
> +
> +/* Return directly back to the caller without leaving Hyp mode: */
> +1:     mrs     lr, elr_hyp
> +       mov     pc, lr
> +
> +/* In monitor mode, set up HVBAR and SCR then return to caller in NS-SVC. */
> +2:
> +       mrc     p15, 0, r1, c1, c1, 0           @ SCR
> +       /*
> +        * Set SCR.NS=1(needed for setting HVBAR and also returning to NS state)
> +        *        .IRQ,FIQ,EA=0 (don't take aborts/exceptions to Monitor mode)
> +        *        .FW,AW=1 (CPSR.A,F modifiable in NS state)
> +        *        .nET=0 (early termination OK)
> +        *        .SCD=0 (SMC in NS mode OK, so we can call secure firmware)
> +        *        .HCE=1 (HVC does Hyp call)
> +        */
> +       bic     r1, r1, #0x07f
> +       ldr     r2, =0x131
> +       orr     r1, r1, r2
> +       mcr     p15, 0, r2, c1, c1, 0           @ SCR
> +       isb
> +       ldr     r2, =mon_vectors
> +
> +
> +       adr     r4, 1f
> +       ldmia   r4, {r5}
> +       sub     r4, r4, r5
> +       add     r2, r2, r4
> +
> +       mcr     p15, 4, r2, c12, c0, 0          @ set HVBAR
> +
> + THUMB(        mrc     p15, 4, r2, c1, c0, 0 )         @ ctrl register
> + THUMB(        orr     r2, r2, #1 << 30 )              @ HSCTLR.TE (Thumb exceptions)
> + THUMB(        mcr     p15, 4, r2, c1, c0, 0 )
> + THUMB(        isb)
> +
> +       /* ...and return to calling code in NS state */
> +       movs    pc, lr
> +
> +
> +       .globl monitor_init
> +monitor_init:
> +       ldr     ip, =mon_vectors
> +
> +       adr     r4, 1f
> +       ldmia   r4, {r5}
> +       sub     r4, r4, r5
> +       add     ip, ip, r4
> +       mcr     p15, 0, ip, c12, c0, 1
> +
> + THUMB(        mrc     p15, 0, r1, c1, c0, 0 )         @ ctrl register
> + THUMB( orr     r1, r1, #1 << 30 )             @ SCTLR.TE (Thumb exceptions)
> + THUMB( mcr     p15, 0, r1, c1, c0, 0 )
> + THUMB( isb )
> +
> +       mov     pc, lr
> +
> +       /* Try to go into NS-SVC: void enter_ns(void); */
> +       .globl enter_ns
> +enter_ns:
> +       smc     #0
> +       mov     pc, lr
> +
> +       /* void enter_hyp(void); */
> +       .globl enter_hyp
> +enter_hyp:
> +       /* Now we're in NS-SVC, make a Hyp call to get into Hyp mode */
> +       mov     r0, lr
> +       mov     r1, sp
> +       hvc     #0
> +       /* We will end up here in NS-Hyp. */
> +       mov     sp, r1
> +       mov     pc, r0
> +
>  ENTRY(exynos4_secondary_startup)
>         mrc     p15, 0, r0, c0, c0, 5
>         and     r0, r0, #15
> @@ -31,6 +124,27 @@ pen:        ldr     r7, [r6]
>         cmp     r7, r0
>         bne     pen
>
> +       ldr     r1, =__boot_cpu_mode
> +       add     r1, r1, r4
> +       ldr     r2, [r1]
> +       mrs     r0, cpsr
> +       ands    r0, r0, #MODE_MASK
> +       subs    r1, r0, r2
> +       beq     3f
> +       subs    r2, r2, #HYP_MODE
> +       bne     3f
> +
> +       /* Setting NSACR to allow coprocessor access from non-secure mode */
> +       mrc     p15, 0, r0, c1, c1, 2
> +       movw    r1, #0x3fff
> +       orr     r0, r0, r1
> +       mcr     p15, 0, r0, c1, c1, 2
> +5:
> +       bl      monitor_init
> +       bl      enter_ns
> +       bl      enter_hyp
> +
> +3:
>         /*
>          * we've been released from the holding pen: secondary_stack
>          * should now contain the SVC stack for this core
> --
> 1.7.9.5
>


From padma.v at samsung.com  Tue May  7 02:25:29 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 11:55:29 +0530
Subject: [PATCH] ARM: samsung: use #include for all device trees
Message-ID: <1367907929-5664-1-git-send-email-padma.v@samsung.com>

Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---

This patch is dependent on below patches by Stephen Warren
http://www.spinics.net/lists/linux-kbuild/msg07616.html

 arch/arm/boot/dts/exynos4.dtsi            |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts   |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts    |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi         |    4 ++--
 arch/arm/boot/dts/exynos4212.dtsi         |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts  |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts   |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi         |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi         |    4 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts  |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts     |    4 ++--
 arch/arm/boot/dts/exynos5250.dtsi         |    4 ++--
 arch/arm/boot/dts/exynos5440-sd5v1.dts    |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi         |    2 +-
 18 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index efd441a..e6f4261 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 8b0a781..8d7a9e5 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 5d925ed..e9f878e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 36d4299..c7a9193 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 15dc0a3..9f7f467 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Hardkernel ODROID-X board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 65e9c57..cfc6208 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index c52b01f..1e816fa 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Samsung SMDK evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 7f42827..fae4f81 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7..8896bb5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76..8e27120 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 26d856b..cea2790 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 581ffae..be56289 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "exynos5250.dtsi"
+#include "cros5250-common.dtsi"
 
 / {
 	model = "Google Snow";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4bd9e9c..36c9d8d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "skeleton.dtsi"
+#include "exynos5250-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos5250";
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b5..5e84c5f 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SD5v1 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..2fd6646 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..13b40b3 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,exynos5440";
-- 
1.7.4.4



From padma.v at samsung.com  Tue May  7 02:43:33 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 12:13:33 +0530
Subject: [PATCH V2 0/3] clk: Samsung: audss: Register audio subsytem clocks
 using common clk framework
Message-ID: <1367909016-19657-1-git-send-email-padma.v@samsung.com>

Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem
has a internal clock controller which controls i2s0 and pcm0 clocks. This patch
series adds the Samsung audio subsytem clock to the common clock framework and
provides the I2S controllers clock information in the dtsi file.

This patch series is dependent on 
https://patchwork.kernel.org/patch/2532091/
http://www.spinics.net/lists/linux-kbuild/msg07616.html

This patch series is made based on Kukjin Kim for-next branch

Changes since V1:
	- Reworked on all review comments by Sylwester Nawrocki
	- Added a header file for all clock indexes as requested by Sylwester
	- Added different compatible names for s5pv210, exynos4 and exynos5
	- Registered the pcm clocks with common clock framework
	
Padmavathi Venna (3):
  clk: samsung: register audio subsystem clocks using common clock
    framework
  ARM: dts: add Exynos audio subsystem clock controller node
  ARM: dts: add clock provider information for i2s controllers in
    Exynos5250

 .../bindings/clock/clk-samsung-audss.txt           |   64 +++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |   16 +++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-samsung-audss.c            |  137 ++++++++++++++++++++
 include/dt-bindings/clk/samsung-audss-clk.h        |   25 ++++
 5 files changed, 243 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
 create mode 100644 drivers/clk/samsung/clk-samsung-audss.c
 create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h

-- 
1.7.4.4



From padma.v at samsung.com  Tue May  7 02:43:34 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 12:13:34 +0530
Subject: [PATCH V2 1/3] clk: samsung: register audio subsystem clocks using
 common clock framework
In-Reply-To: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
Message-ID: <1367909016-19657-2-git-send-email-padma.v@samsung.com>

Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 .../bindings/clock/clk-samsung-audss.txt           |   64 +++++++++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-samsung-audss.c            |  137 ++++++++++++++++++++
 include/dt-bindings/clk/samsung-audss-clk.h        |   25 ++++
 4 files changed, 227 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
 create mode 100644 drivers/clk/samsung/clk-samsung-audss.c
 create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h

diff --git a/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
new file mode 100644
index 0000000..ec2cd0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in the S5PV210 and Exynos
+family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+  - "samsung,s5pv210-audss-clock" - controller compatible with all S5PV210 SoCs.
+  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
+  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock           ID      SoC (if specific)
+-----------------------------------------------
+
+mout_audss      0
+mout_i2s        1
+dout_srp        2
+dout_bus        3
+dout_i2s        4
+srp_clk         5
+i2s_bus         6
+sclk_i2s        7
+pcm_bus         8
+sclk_pcm        9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller at 03810000 {
+	compatible = "samsung,exynos5250-audss-clock";
+	reg = <0x03810000 0x0C>;
+	#clock-cells = <1>;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+ i2s0: i2s at 03830000 {
+		compatible = "samsung,i2s-v5";
+		reg = <0x03830000 0x100>;
+		dmas = <&pdma0 10
+			&pdma0 9
+			&pdma0 8>;
+		dma-names = "tx", "rx", "tx-sec";
+		clocks = <&clock_audss SAMSUNG_I2S_BUS>,
+			<&clock_audss SAMSUNG_I2S_BUS>,
+			<&clock_audss SAMSUNG_SCLK_I2S>;
+		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+};
+
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..5425fa8 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
+obj-$(CONFIG_PLAT_SAMSUNG)	+= clk-samsung-audss.o
diff --git a/drivers/clk/samsung/clk-samsung-audss.c b/drivers/clk/samsung/clk-samsung-audss.c
new file mode 100644
index 0000000..97526b7
--- /dev/null
+++ b/drivers/clk/samsung/clk-samsung-audss.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clk/samsung-audss-clk.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+	{ASS_CLK_SRC,  0},
+	{ASS_CLK_DIV,  0},
+	{ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+
+#ifdef CONFIG_PM_SLEEP
+static int samsung_audss_clk_suspend(void)
+{
+	int i;
+
+	for (i = 0; i < 3; i++)
+		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+	return 0;
+}
+
+static void samsung_audss_clk_resume(void)
+{
+	int i;
+
+	for (i = 0; i < 3; i++)
+		writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops samsung_audss_clk_syscore_ops = {
+	.suspend	= samsung_audss_clk_suspend,
+	.resume		= samsung_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* register samsung_audss clocks */
+void __init samsung_audss_clk_init(struct device_node *np)
+{
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: failed to map audss registers\n", __func__);
+		return;
+	}
+
+	clk_table = kzalloc(sizeof(struct clk *) * SAMSUNG_AUDSS_MAX_CLKS,
+				GFP_KERNEL);
+	if (!clk_table) {
+		pr_err("%s: could not allocate clock lookup table\n", __func__);
+		return;
+	}
+
+	clk_data.clks = clk_table;
+	clk_data.clk_num = SAMSUNG_AUDSS_MAX_CLKS;
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	clk_table[SAMSUNG_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+				mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
+				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+	clk_register_clkdev(clk_table[SAMSUNG_MOUT_AUDSS], "mout_audss", NULL);
+
+	clk_table[SAMSUNG_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+				mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
+				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+	clk_register_clkdev(clk_table[SAMSUNG_MOUT_I2S], "mout_i2s", NULL);
+
+	clk_table[SAMSUNG_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+				"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
+				0, &lock);
+
+	clk_table[SAMSUNG_DOUT_BUS] = clk_register_divider(NULL, "dout_bus",
+				"dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0,
+				&lock);
+
+	clk_table[SAMSUNG_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
+				&lock);
+
+	clk_table[SAMSUNG_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+				"dout_srp", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+	clk_table[SAMSUNG_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+				"dout_bus", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 2, 0, &lock);
+
+	clk_table[SAMSUNG_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+				"dout_i2s", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 3, 0, &lock);
+
+	clk_table[SAMSUNG_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+				 "sclk_pcm", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 4, 0, &lock);
+
+	clk_table[SAMSUNG_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+				"div_pcm0", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 5, 0, &lock);
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&samsung_audss_clk_syscore_ops);
+#endif
+
+	pr_info("Exynos: Audss: clock setup completed\n");
+}
+CLK_OF_DECLARE(s5pv210_audss_clk, "samsung,s5pv210-audss-clock",
+		samsung_audss_clk_init);
+CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
+		samsung_audss_clk_init);
+CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
+		samsung_audss_clk_init);
diff --git a/include/dt-bindings/clk/samsung-audss-clk.h b/include/dt-bindings/clk/samsung-audss-clk.h
new file mode 100644
index 0000000..d335555
--- /dev/null
+++ b/include/dt-bindings/clk/samsung-audss-clk.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and samsung audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SAMSUNG_AUDSS_H
+#define _DT_BINDINGS_CLK_SAMSUNG_AUDSS_H
+
+#define SAMSUNG_MOUT_AUDSS	0
+#define SAMSUNG_MOUT_I2S	1
+#define SAMSUNG_DOUT_SRP	2
+#define SAMSUNG_DOUT_BUS	3
+#define SAMSUNG_DOUT_I2S	4
+#define SAMSUNG_SRP_CLK		5
+#define SAMSUNG_I2S_BUS		6
+#define SAMSUNG_SCLK_I2S	7
+#define SAMSUNG_PCM_BUS		8
+#define SAMSUNG_SCLK_PCM	9
+
+#define SAMSUNG_AUDSS_MAX_CLKS	10
+
+#endif
-- 
1.7.4.4



From padma.v at samsung.com  Tue May  7 02:43:35 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 12:13:35 +0530
Subject: [PATCH V2 2/3] ARM: dts: add Exynos audio subsystem clock controller
 node
In-Reply-To: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
Message-ID: <1367909016-19657-3-git-send-email-padma.v@samsung.com>

Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 36c9d8d..7026de0 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
 		#clock-cells = <1>;
 	};
 
+	clock_audss: audss-clock-controller at 0x03810000 {
+		compatible = "samsung,exynos5250-audss-clock";
+		reg = <0x03810000 0x0C>;
+		#clock-cells = <1>;
+	};
+
 	gic:interrupt-controller at 10481000 {
 		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
-- 
1.7.4.4



From padma.v at samsung.com  Tue May  7 02:43:36 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 07 May 2013 12:13:36 +0530
Subject: [PATCH V2 3/3] ARM: dts: add clock provider information for i2s
 controllers in Exynos5250
In-Reply-To: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
Message-ID: <1367909016-19657-4-git-send-email-padma.v@samsung.com>

Add clock lookup information for i2s controllers on exynos5250 SoC.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 7026de0..13305b9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
 #include "skeleton.dtsi"
 #include "exynos5250-pinctrl.dtsi"
 
+#include <dt-bindings/clk/samsung-audss-clk.h>
+
 / {
 	compatible = "samsung,exynos5250";
 	interrupt-parent = <&gic>;
@@ -457,6 +459,10 @@
 			&pdma0 9
 			&pdma0 8>;
 		dma-names = "tx", "rx", "tx-sec";
+		clocks = <&clock_audss SAMSUNG_I2S_BUS>,
+			<&clock_audss SAMSUNG_I2S_BUS>,
+			<&clock_audss SAMSUNG_SCLK_I2S>;
+		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 		samsung,supports-6ch;
 		samsung,supports-rstclr;
 		samsung,supports-secdai;
@@ -471,6 +477,8 @@
 		dmas = <&pdma1 12
 			&pdma1 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 307>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_bus>;
 	};
@@ -481,6 +489,8 @@
 		dmas = <&pdma0 12
 			&pdma0 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 308>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s2_bus>;
 	};
-- 
1.7.4.4



From lee.jones at linaro.org  Tue May  7 03:39:21 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 7 May 2013 08:39:21 +0100
Subject: [PATCH 54/63] ARM: ux500: Replace ST-E's home-brew DMA direction
 definition with the generic one
In-Reply-To: <20130506071355.GA5552@bnru10>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-55-git-send-email-lee.jones@linaro.org>
 <20130506071355.GA5552@bnru10>
Message-ID: <20130507073921.GT24153@gmail.com>

On Mon, 06 May 2013, Srinidhi Kasagar wrote:

> On Fri, May 03, 2013 at 16:32:40 +0200, Lee Jones wrote:
> > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > duplicating such things.
> > 
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  arch/arm/mach-ux500/board-mop500-audio.c |   12 ++++++------
> >  arch/arm/mach-ux500/board-mop500-sdi.c   |   16 ++++++++--------
> >  arch/arm/mach-ux500/board-mop500.c       |   22 +++++++++++-----------
> >  arch/arm/mach-ux500/usb.c                |    4 ++--
> >  4 files changed, 27 insertions(+), 27 deletions(-)
> 
> Hope you have taken care for all other files, because, I see
> few more instances in my tree apart from the above files.

Would you be kind enough to paste those files please?

> Otherwise..
> 
> Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> 
> regards,
> srinidhi

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From jaswinder.singh at linaro.org  Tue May  7 03:40:08 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Tue, 7 May 2013 13:10:08 +0530
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <518840A2.5000205@ti.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
Message-ID: <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>

Hi Suman,

On 7 May 2013 05:15, Suman Anna <s-anna at ti.com> wrote:
>>
>>  The client(s) can always generate TX requests at a rate greater than
>> the API could transmit on the physical link. So as much as we dislike
>> it, we have to buffer TX requests, otherwise N clients would.
>
> The current code doesn't support N clients today anyway, and if they are
> blocking mode on top of it, it would never need Tx buffering.
>
No, I meant if the API doesn't buffer TX requests, then N client
drivers that simply need to send 2 or more messages would have to
buffer them locally.
 Also by buffering TX requests the API reduces TX latency by
submitting the next request atomically as soon as it knows the last TX
is done.


>>
>> IMHO if clients on OMAP need to buffer RX, let us keep it OMAP
>> specific. If number of such platforms rise in future we could move
>> that as an _optional_ helper API on top, that does RX buffering on
>> behalf of clients ?
>
> Yeah, that's my idea as well to put this in the OMAP mailbox controller
> driver implementation. The IPC stacks on OMAP are quite established
> (both in remoteproc and DSP/Bridge - different generations), so I cannot
> afford to break the functionality of either of those. This already means
> I have to export some API from my controller driver and there is no
> other way or now.
>
Yes, I anticipated that.
Though imho OMAP's mailbox client/controller drivers could have be better.
 The controller has 8 instances of identical mailboxes/links which
operate independent of each other. It is the s/w implementation that
has tacit understanding of who sends/receives on which link. So
ideally a client driver should simply, say for omap3430, ask for
separate "mbox1" to read messages and "mbox0" to send messages to DSP.
 The unnecessary logical coupling of 0th and 1st links seems to be the
cause of 'hacks' like mailbox_dis/enable_irq(), whereas it should have
been release/request of the RX mbox.
Also logically coupling the independent physical links makes the
controller driver not very portable - what if some other platform has
usage of 3 send+receive and 2 send-only communications of the 8
physical links? The controller h/w is perfectly capable of providing
that, but its driver is not.
  Similarly something sure seems fishy about the client driver having
to explicitly save and restore registers of controller. Anyways, OMAP'
implementation of mailbox is a separate subject.


>>>
>>  If the API provides shared ownership of a mailbox, it won't work for
>> clients that need exclusive ownership (like 'server' side
>> implementation of a protocol).
>>  OTOH if the API provides exclusive ownership, it is still possible to
>> emulate shared ownership by simply publishing the mailbox handle (void
>> *chan) globally. It works for all.
>
> I am not saying provide this always. Have this dictated by the
> controller or mailbox (look at my branch). The global publication works
> well functionality-wise for Tx, but not so much for Rx.
>
Right now for RX the clients register a blocking notifier call within
the API, you could move that out into the same code that publishes the
TX handlle globally.  I am a bit hesitant because I want to make sure
we don't push anything into the common API that isn't already done
right in OMAP's implementation.

> In anycase,
> global publication will have its own set of problems - mostly you are
> implying another layer of implementation that provides this sharing
> capability (since they have to be outside of any single client).
>
Yes. Though yet another way of doing it is for the controller driver
to populate N logical per physical link that needs to be shared.

BTW, there doesn't exist any code/dt that creates the "omap-rproc"
platform_device so I may have misunderstood, but it seems the OMAP
already acquires a mailbox only once and save it in the data structure
representing the remote, which should simply work as such. No?


>>>
>> Most of the clients won't queue more than 1 request at a time. And
>> then, isn't it only natural that clients don't mess with requests
>> after submitting them ?  I see mailbox clients working quite like I2C
>> clients.
>
> The OMAP use-cases do this today, so not a good assumption to make. The
> OMAP IPC is built upon simple transmitting and processing received
> messages separately, we will not be using blocking mode or tx callbacks.
> I really don't need the complexity of having to introduce tx callbacks
> just because I need to know if my pointer can be freed, as I said - it
> eliminates the simplicity of using local variables unless the send API
> is blocking. void * works for OMAP since my payloads are only 4 bytes by
> themselves (this is a discussion that came up during the earlier series
> as well), but this is not flexible enough on the clients-side generally.
>
The OMAP simply pass by value a u32 as a message.  Why do you think it
won't work ? (Please have a look at my implementation of the omap2
controller driver)


>>
>>> Secondly, we may not need the logic around client knows_txdone and
>>> tx_buffering together. I understand the need for buffering when you have
>>> TX_POLL or TX_IRQ, but as far as TX_ACK is concerned, it is a client
>>> protocol-level knowledge, and so the tx buffering logic can remain with
>>> the client itself. This should simplify the code a little bit and get
>>> rid of the ipc_client_txdone API.
>>>
>> Yeah I had it that way originally. But then I realized we could be
>> running an 'ACK Packet' protocol over a controller that supports only
>> POLL. In that case the controller's poll doesn't override client's
>> knows_txdone because we want the client to cut-short the next poll
>> delay as soon as it gets an ACK packet.
>
> I think the same can be achieved from the Rx path upon an interrupt in
> the specific controller, without having to introduce the knows_txdone.
>
RX may not only be responses, it could very well be a remote command
just before the response to the last local command. OR the RX
responses may be out of order. So it can't be tied to the RX
interrupt.

> It is knowledge intrinsic to a controller/mailbox. I really hope that
> there are no controllers where you have to poll for Rx too :)
>
No, not intrinsic to controller, but to the high level protocol.
Yes, I assume the RX to be always interrupt driven :)

>>
>>> Looking at the current use-cases, I think OMAP might be the only one
>>> which needs the buffering. The API that Loic added suggests that he
>>> either sends a message and expects a response, or just sends a message
>>> if the transport is free (I am not sure if he is using the API that uses
>>> buffering currently). PL320 is the same as the first scenario that Loic has.
>>>
>> Yeah I too expect TX buffering to be very rare.
>
> If so, can we eliminate this for the first pass, and leave it to the
> controllers for now or dictate this based on a tx_buffering property? As
> I see it, we do not yet have an agreement on the Tx buffering semantics.
>
As I said, among other advantages, TX buffering is needed to reduce
latencies. My platform's protocol isn't yet clear as to whether use
shared-memory (secure and non-secure versions) for not very large data
transfers or interrupt payload. So if we get good enough speed we
could save cost on dedicated memories.

I wrote the omap2 controller driver code to convey my proposal better.
If you could please tell me how TX buffering is a problem for OMAP, it
will help me understand your concern better.

>>>
>> First of all, PL320 is a highly configurable and programmable IP.
>> pl320.c is very specific to Highbank's usage, it is not usable as such
>> on other platforms. There are many things hardcoded and tacitly
>> assumed in the driver. I just changed the API, didn't add anything
>> new.
>
> OK, should we be renaming this file accordingly then until another
> common user comes along? Also, an appropriate 'depends on' in the Kconfig.
>
Yes, will do. Thanks.


>>
>> Secondly, I believe we acknowledged the fact that a client can't do
>> without controller specific knowledge. So in proper implementation the
>> controller's header would look like
>>
>> struct foobar_con_mssg {
>>    int datalen; /* size of received packet in bytes */
>>    u8 *buf;  /* buffer that holds the packet data */
>>     .....
>> };
>>
>> So instead of telling the API the 'datalen' and the remaining
>> structure of each message, we simply pass "struct foobar_con_mssg *"
>> as a void* to the API.
>
> This has to be documented very well. And yes, I did acknowledge the
> inter-dependencies portion for understanding the packet structure (there
> is no way if you have a packet of 6 ints and you expect specific ints
> for specific fields). The size and void * are generic enough that can be
> present in the core to perform some error checking. The API would be
> akin to memcpy then. The other motivation is based on the buffering
> scheme (same comment as above on Tx buffering), which we haven't agreed
> upon completely.
>
How could the core perform any meaningful sanity check?  What if we
send/receive proper 'datalen' of garbage data?  What if the client
sends a "Give me info in not more than 32-bytes at a time" command to
the remote and the remote has valid info worth only 16 bytes?
IMHO there is not much for core to verify in a packet in transit. The
introduced checks are not worth it and actually limit some scenarios
like above example.


>>>
>>> Assigning the tx_block at channel request time might not be flexible
>>> enough. We should not impose that the client will request and release
>>> channels with different modes if both scenarios are needed.
>>>
>> If there is one blocking request, no more could arrive (blocking or
>> non-blocking).
>
> Well, you are assuming that there is only one thread from within the
> client driver who is gonna use the send API. There is nothing in the
> code that stops from say two threads/contexts queueing in the message
> from the same client driver. I am ok from my side for this to be sorted
> out later, since I won't be using the blocking mode,
>
Thanks


>>>
>>> Do we need to add an API similar to mailbox_msg_send_receive_no_irq, or
>>> are you leaving it to be client's responsibility?
>>>
>> Yes the API provides enough ways for a client to do that.
>
> I will let Loic comment on this, based on his usage/complexity in the
> client. I think you got lucky with PL320 implementation since it fills
> in the buffer on a Tx done, so you have folded that functionality in
> send_data itself.
>
No, the pl320 models the links properly. The links could be used for
RX or TX independently.
Any RX channel will return data only from a remote. The TX returns
data in tx-buffer which may or may not be changed by the remote after
reading. The Highbank's protocol make use of that feature. Though I am
interested to know if Loic has some unmet requirements still.


>>>
>> Yeah, I changed that to it last minute :)
>> The API has no real use of controller nodes, it works solely on a
>> global pool of mailboxes. I tried to reflect that in code.
>
> Can we go back to using controller nodes? I understand that the API
> doesn't use much, but the list of controller nodes is gonna be static
> anyway in the file. It just improves the search algorithm when looking
> for a mailbox. We have a new device coming up (u-boot patches already
> submitted) wherein we have 13 controller instances, each with about 4 to
> 6 links, a linear search would be really painful.
>
OK I'll keep a local list of controllers.


>>>
>> There are some highly programmable controllers that, if the driver is
>> proper, could change behavior runtime. For ex, if the controller
>> supports, a client might want to broadcast messages to multiple
>> remotes or listen for messages from more than one remote source or
>> both. The client could, say, specify bitmasks for such source/sink
>> remotes via cntlr_data while requesting the mailbox.  PL320 could work
>> in such mode if rest all fits.
>
> Are you configuring the specific mailbox or configuring the controller
> on a whole in this particular example?
>
The cntlr_data is to configure the link/mailbox, not the controller.

>>>
>> The API gives the controller only one TX at a time, so I chose the
>> name. What do you suggest?
>
> how about 'is_ready', i think it is a bit more generic name and
> automatically implies there are no pending tx.
>
OK I can live with that ;)

>
> Is your intention to leave the dev out to the controller driver specific
> structure (atleast from the OMAP example code). I was asking for this to
> be part of the ipc_controller structure, use a struct device *dev
> instead of controller_name, and construct the controller name from the
> dev_name.
>
Yes, the ipc_controller should have it. I didn't implement that yet in
v2 though.

>>>
>> A controller is assumed to be a bunch of identical links/mailboxes.
>> However the cntlr_data could still help the client specify mode in
>> which it wants a mailbox behave.
>
> Yeah, assumptions hold true until an unfortunate SoC comes up with it
> :). The TI AM3352 has one link that doesn't behave quite like the other
> (I am hoping to avoid using it), so I am ok with it for now. Guess we
> can always change it when a concrete need arises.
>
It would work right now :)   If your controller has 2 types of links,
the driver should register each bunch separately, each with its own
ipc_link_ops, with the core. The core can already take care of the
rest.


> I prefer to see the controller_ops for startup/shutdown atleast. This
> will allow the controller code state machine to be much better
> maintained and make the code look good. As I said, with our new device,
> where we have 13 controllers this will be very helpful. Also from what
> Andy explained, you seem to have two controllers that are quite
> different from each other.
>
Yes, I have 2 types of controllers and I already thought about
multiple controllers in a platform.
 What do you expect to do in controller startup/shutdown? Since the
API works on individual links, not the controllers, when would it call
controller_start() and controller_shutdown()?  The ipc_link's
startup/shutdown are already non-atomic, if the controller needs any
setup it could do it in the first link's startup and teardown in the
last link's shutdown. Not to forget the resources lke IRQ are usually
per Link which should be acquired/released upon link's use/idle.
 While writing the OMAP2 controller driver, did I miss any controller
startup/shutdown ?

Regards,
-Jassi


From b32955 at freescale.com  Tue May  7 03:39:20 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 7 May 2013 15:39:20 +0800
Subject: [PATCH 3/3] ARM: dts: enable the gpmi-nand for imx6q{dl}-sabreauto
 boards
In-Reply-To: <1367912360-3283-1-git-send-email-b32955@freescale.com>
References: <1367912360-3283-1-git-send-email-b32955@freescale.com>
Message-ID: <1367912360-3283-3-git-send-email-b32955@freescale.com>

enable the gpmi-nand for imx6q-sabreauto and imx6qdl-sabreauto boards.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 4d237cf..7b561fb 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -23,6 +23,12 @@
 	status = "okay";
 };
 
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+};
+
 &uart4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart4_1>;
-- 
1.7.1




From b32955 at freescale.com  Tue May  7 03:39:19 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 7 May 2013 15:39:19 +0800
Subject: [PATCH 2/3] ARM: dts: imx6dl: add pinctrl for gpmi-nand
In-Reply-To: <1367912360-3283-1-git-send-email-b32955@freescale.com>
References: <1367912360-3283-1-git-send-email-b32955@freescale.com>
Message-ID: <1367912360-3283-2-git-send-email-b32955@freescale.com>

add the pinctrl item for gpmi-nand.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a..24544ed 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -78,6 +78,30 @@
 					};
 				};
 
+				gpmi-nand {
+					pinctrl_gpmi_nand_1: gpmi-nand-1 {
+						fsl,pins = <
+							MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+							MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+							MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+							MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+							MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+							MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+							MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+							MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+							MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+							MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+							MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+							MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+							MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+							MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+							MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+							MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+							MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+						>;
+					};
+				};
+
 				uart1 {
 					pinctrl_uart1_1: uart1grp-1 {
 						fsl,pins = <
-- 
1.7.1




From b32955 at freescale.com  Tue May  7 03:39:18 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 7 May 2013 15:39:18 +0800
Subject: [PATCH 1/3] ARM: dts: imx6q: remove the unused pins for gpmi-nand
Message-ID: <1367912360-3283-1-git-send-email-b32955@freescale.com>

The gpmi does not use the MX6Q_PAD_NANDF_CS2__NAND_CE2_B and
MX6Q_PAD_NANDF_CS3__NAND_CE3_B.

Just remove them.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e6758..ed11bcf 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -168,8 +168,6 @@
 							MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
 							MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 							MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-							MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
-							MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
 							MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 							MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 							MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-- 
1.7.1




From andrew.murray at arm.com  Tue May  7 04:01:42 2013
From: andrew.murray at arm.com (Andrew Murray)
Date: Tue, 7 May 2013 09:01:42 +0100
Subject: [PATCH v8 1/3] of/pci: Unify pci_process_bridge_OF_ranges from
 Microblaze and PowerPC
In-Reply-To: <1367721709.11982.37.camel@pasglop>
References: <1366627295-16964-1-git-send-email-Andrew.Murray@arm.com>
 <1366627295-16964-2-git-send-email-Andrew.Murray@arm.com>
 <1367721709.11982.37.camel@pasglop>
Message-ID: <20130507080142.GA8808@arm.com>

On Sun, May 05, 2013 at 03:41:49AM +0100, Benjamin Herrenschmidt wrote:
> On Mon, 2013-04-22 at 11:41 +0100, Andrew Murray wrote:
> > The pci_process_bridge_OF_ranges function, used to parse the "ranges"
> > property of a PCI host device, is found in both Microblaze and PowerPC
> > architectures. These implementations are nearly identical. This patch
> > moves this common code to a common place.
> 
> What's happening with this ? I'd like to avoid that patch for now
> as I'm doing some changes to pci_process_bridge_OF_ranges
> which are fairly urgent (I might even stick them in the current
> merge window) to deal with memory windows having separate offsets.

There were no objections to this latest revision until now and it is
currently sitting with Jason Cooper (mvebu-next/pcie). [1]

> 
> There's also a few hacks in there that are really ppc specific...
> 
> I think the right long term approach is to change the way powerpc
> (and microblaze ?) initializes PCI host bridges. Move it away from
> setup_arch() (which is a PITA anyway since it's way too early) to
> an early init call of some sort, and encapsulate the new struct
> pci_host_bridge.
> 
> We can then directly configure the host bridge windows rather
> than having this "intermediary" set of resources in our pci_controller
> and in fact move most of the fields from pci_controller to
> pci_host_bridge to the point where the former can remain as a
> simple platform specific wrapper if needed.

This is a view that was also shared by Bjorn [2] when I attempted to
submit a patchset which moves struct pci_controller to asm-generic.

> 
> So for new stuff (hint: DT based ARM PCI) or stuff that has to deal with
> a lot less archaic platforms (hint: Microblaze), I'd recommend going
> straight for that approach rather than perpetuating the PowerPC code
> which I'll try to deal with in the next few monthes.

The motativation for my patchsets were to give a way for ARM PCI host
bridge drivers to parse the DT ranges property, but this snow-balled into
unifying pci_process_bridge_OF_ranges.

My v8 patchset provides a of_pci_range_parser which is used directly by a
few ARM PCI DT host bridge drivers, this has been generally accepted and
tested. I don't see why this can't remain and so I'd really like to keep this
around. 

Grant, Benjamin would you be happy for me to resubmit this series which provides
the of_pci_range_parser which will be used by the separate implementations of
pci_process_bridge_OF_ranges in PowerPC/Microblaze?

Benjamin are you able to still use of_pci_range_parser in your
'Support per-aperture memory offset' patch?

Thanks,

Andrew Murray

[1] https://lkml.org/lkml/2013/4/22/505
[2] https://patchwork.kernel.org/patch/2487671

> 
> Cheers,
> Ben.
>  
> 
> 


From marek.belisko at gmail.com  Tue May  7 04:14:50 2013
From: marek.belisko at gmail.com (Marek Belisko)
Date: Tue,  7 May 2013 10:14:50 +0200
Subject: [PATCH 1/2] clk: si5351: Fix msynth_recalc_rate return value when
 fOUT is 0.
Message-ID: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>

When p3 is eual to 0 then result for fOUT is 0. In that case we should
return 0 not parent_rate;

This issue was causing deadlock in si5351 chip when user set_rate for
ms0->clk0 and then set_rate for ms1->clk1 (both ms sourced from plla).
After that clk1 was 0 and it wasn't possible to enable it again (try also
manually with i2cset commands). Only power cycle helps.

Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
---
 drivers/clk/clk-si5351.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index fc215ce..a8fc0f4 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -607,7 +607,7 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
 		si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
 
 	if (hwdata->params.p3 == 0)
-		return parent_rate;
+		return 0;
 
 	/*
 	 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
-- 
1.7.9.5



From marek.belisko at gmail.com  Tue May  7 04:14:51 2013
From: marek.belisko at gmail.com (Marek Belisko)
Date: Tue,  7 May 2013 10:14:51 +0200
Subject: [PATCH 2/2] clk: si5351: Powerdown output when clock rate is 0.
In-Reply-To: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
References: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <1367914491-17445-2-git-send-email-marek.belisko@streamunlimited.com>

When rate is 0 powerdown clock output.

Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
---
 drivers/clk/clk-si5351.c |   32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index a8fc0f4..e254e76 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1042,20 +1042,22 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct si5351_hw_data *hwdata =
 		container_of(hw, struct si5351_hw_data, hw);
 	unsigned long new_rate, new_err, err;
-	unsigned char rdiv;
+	unsigned char rdiv, pdn = 0;
 
 	/* round to closed rdiv */
 	rdiv = SI5351_OUTPUT_CLK_DIV_1;
-	new_rate = parent_rate;
-	err = abs(new_rate - rate);
-	do {
-		new_rate >>= 1;
-		new_err = abs(new_rate - rate);
-		if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
-			break;
-		rdiv++;
-		err = new_err;
-	} while (1);
+	if (rate) {
+		new_rate = parent_rate;
+		err = abs(new_rate - rate);
+		do {
+			new_rate >>= 1;
+			new_err = abs(new_rate - rate);
+			if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
+				break;
+			rdiv++;
+			err = new_err;
+		} while (1);
+	}
 
 	/* write output divider */
 	switch (hwdata->num) {
@@ -1075,9 +1077,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
 				rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
 	}
 
-	/* powerup clkout */
+	/* when rate is 0 powerdown output */
+	if (rate == 0)
+		pdn = SI5351_CLK_POWERDOWN;
+
+	/* powerup/down clkout */
 	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
-			SI5351_CLK_POWERDOWN, 0);
+			SI5351_CLK_POWERDOWN, pdn);
 
 	dev_dbg(&hwdata->drvdata->client->dev,
 		"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
-- 
1.7.9.5



From marc.zyngier at arm.com  Tue May  7 04:17:54 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 07 May 2013 09:17:54 +0100
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <20130506231554.GB16801@amd.pavel.ucw.cz>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz>
Message-ID: <5188B8B2.5030601@arm.com>

On 07/05/13 00:16, Pavel Machek wrote:

Hi Pawel,

>> Now that we support a timer-backed delay loop, I'm quickly getting sick
>> and tired of people complaining that their beloved bogomips value has
>> decreased. You know who you are!
> 
>> Unfortunately, we can't just remove the entry from /proc/cpuinfo, as it
>> will likely break fragile userspace code which is parsing that stuff, so
>> instead replace it with a dummy value that can be chosen in the
>> Kconfig.
> 
> So, instead of removing it you silently report invalid value? Note

Removing it would be an ABI breakage. Unfortunately.

> that there's no cpumhz display in procinfo... at least on OLPC I
> looked.

And? What does the CPU frequency bring you when any modern CPU has some
kind of cpufreq support that renders this information information pretty
much meaningless?

> And whether it is 30MHz or 3GHz cpu might be relevant information for
> userspace, and yes, bogomips used to be good enough for that.

Name one userspace application that extracts meaningful information out
of the BogoMIPS field. Just one.

> Actually it was mhz, mhz/2 or mhz*2 on pretty much all reasonable systems.

So any number within a ratio from one to four is good enough for you?
Wow. That pretty much proves the usefulness of this patch.

Additionally, having switched arch_timer capable CPUs to a timer based
delay instead of a loop-based delay means your precious pseudo-frequency
is now a thing of the past. And guess what? Nothing broke so far.
Because using BogoMIPS to deduct anything is *bogus*.

Timer-based delay calibration has been around for about ages. I still
remember the day (some 10 or 12 years ago) when DaveM switched the
UltraSPARC port to use the timer, and my BogoMIPS went from ~1000 to 12.
People moaned, DaveM held his position, and nothing happened. *Nothing*.
End of story.

	M.
-- 
Jazz is not dead. It just smells funny...



From shawn.guo at linaro.org  Tue May  7 04:29:00 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 7 May 2013 16:29:00 +0800
Subject: [PATCH 1/3] ARM: dts: imx6q: remove the unused pins for gpmi-nand
In-Reply-To: <1367912360-3283-1-git-send-email-b32955@freescale.com>
References: <1367912360-3283-1-git-send-email-b32955@freescale.com>
Message-ID: <20130507082858.GK1749@S2101-09.ap.freescale.net>

On Tue, May 07, 2013 at 03:39:18PM +0800, Huang Shijie wrote:
> The gpmi does not use the MX6Q_PAD_NANDF_CS2__NAND_CE2_B and
> MX6Q_PAD_NANDF_CS3__NAND_CE3_B.
> 
> Just remove them.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Applied all 3, thanks.

> ---
>  arch/arm/boot/dts/imx6q.dtsi |    2 --
>  1 files changed, 0 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 21e6758..ed11bcf 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -168,8 +168,6 @@
>  							MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
>  							MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
>  							MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
> -							MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
> -							MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
>  							MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
>  							MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
>  							MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
> -- 
> 1.7.1
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From marc.zyngier at arm.com  Tue May  7 04:55:41 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 07 May 2013 09:55:41 +0100
Subject: [RFC PATCH V2] ARM: EXYNOS: Fix hotplug when CPUs boot in HYP mode
In-Reply-To: <CAHuqX+HUWcX_sTXKCjSQ9pR1K8obLc+T7vYK_zTn_gqO8ULPVQ@mail.gmail.com>
References: <1367905910-30913-1-git-send-email-giridhar.m@samsung.com>
 <CAHuqX+HUWcX_sTXKCjSQ9pR1K8obLc+T7vYK_zTn_gqO8ULPVQ@mail.gmail.com>
Message-ID: <5188C18D.10103@arm.com>

On 07/05/13 06:54, Giridhar Maruthy wrote:
> This patch is a modification from the Christoffer Dall's u-boot
> patch. This is required to put the secondary processors in hyp
> mode during cpu hotplug when u-boot is no longer alive.
> 
> Marc Zyngier suggested this logic to go into firmware or, u-boot
> putting a trampoline code into a page /memreserve/d by DT. But
> this seemed to have a problem. Once the cpu is hotplugged in
> runtime, the control is in ROM code and waits for event.
> Kernel provides a return address in kernel to which the processor
> jumps once it gets an event. If the control branches to the
> trampoline code here, this trampoline code has no kernel return
> address.
> 
> Someone with better logic or better placement of this logic
> elsewhere is welcome.

What prevents you from writing the kernel address in the memreserved
page? Some obvious location, like the last word of the page? You only
have to do it once (from the boot CPU, for example).

Or did I miss something else?

	M.
-- 
Jazz is not dead. It just smells funny...



From broonie at kernel.org  Tue May  7 05:03:36 2013
From: broonie at kernel.org (Mark Brown)
Date: Tue, 7 May 2013 10:03:36 +0100
Subject: [PATCH] ASoC: Samsung: i2s: Fix crash in i2s driver
In-Reply-To: <1367897941-18439-1-git-send-email-padma.v@samsung.com>
References: <1367897941-18439-1-git-send-email-padma.v@samsung.com>
Message-ID: <20130507090336.GP7478@sirena.org.uk>

On Tue, May 07, 2013 at 09:09:01AM +0530, Padmavathi Venna wrote:
> This patch fixes a null pointer deference in i2s driver in DT
> case
> 
> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
> ---
> 
> This patch is dependent on below patch posted by Thomas Abraham.
> https://patchwork.kernel.org/patch/2224801/

Please don't submit patches that can't be applied, the two patches need
to be submitted together.  Please also remember to include human
readable descriptions of patches in e-mails for the benefit of human
readers, commit IDs and URLs aren't immediately comprehensible.

Please further note my new e-mail address.
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From will.deacon at arm.com  Tue May  7 05:08:49 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 May 2013 10:08:49 +0100
Subject: [RFC PATCH 0/2] ARM: Remove any correlation between IPC and
 BogoMips value
In-Reply-To: <5187EFF3.6010005@codeaurora.org>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <5187EFF3.6010005@codeaurora.org>
Message-ID: <20130507090849.GC25387@mudshark.cambridge.arm.com>

On Mon, May 06, 2013 at 07:01:23PM +0100, Christopher Covington wrote:
> Hi Will,
> 
> On 05/03/2013 01:35 PM, Will Deacon wrote:
> > Hi all,
> > 
> > This small patch set may look a little over a month late, but there is a
> > serious reason for posting it.
> > 
> > When I moved the ARM delay loop over to using the architected timers
> > rather than the CPU spinning loop (which has all the problems associated
> > with cpu frequency scaling and what-not) I thought I was doing something
> > useful for the port. However, it turns out that a surprising number of
> > people have complained, and continue to complain, about the drop in
> > their `BogoMIPs score'.
> 
> Have you considered adding the old code back in, but in a form that's not at
> all referenced by the delay loop code and just calculates CPU-based bogomips?

That seems like a lot of effort in order to preserve something that isn't
even meaningful. We might be better just zeroing the value, but then we'll
inevitably get bug reports of it being `wrong'.

Plus, the calibration during boot introduces a brief delay when onlining
each core whereas this can be skipped when using a constant timer.

Will


From valentin.longchamp at keymile.com  Tue May  7 05:10:24 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Tue, 07 May 2013 11:10:24 +0200
Subject: [PATCH 0/7] mv643xx_eth: device tree bindings
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <5188C500.8010209@keymile.com>

Sebastian,

On 05/06/2013 05:33 PM, Sebastian Hesselbarth wrote:
> This patch set picks up work by Florian Fainelli bringing full DT
> support to mv643xx_eth and Marvell SoCs using it.
> 
> The current patch set drops Florian's device tree conversions for
> Kirkwood, Dove, and Orion5x in favour of split patches for board
> files and board descriptor files.
> 
> Device tree conversion for Dove and Kirkwood is added. Dove has
> been fully tested, while Kirkwood is compile-tested only.
> 
> Florian Fainelli (2):
>   net: mv643xx_eth: add Device Tree bindings
>   net: mv643xx_eth: update Device Tree bindings documentation
> 
> Sebastian Hesselbarth (5):
>   ARM: dove: remove legacy mv643xx_eth setup
>   ARM: dove: add gigabit ethernet and mvmdio device tree nodes
>   ARM: kirkwood: remove legacy mv643xx_eth board setup
>   ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
>   ARM: kirkwood: remove legacy clk alias for mv643xx_eth
> 

I have successfully tested these patches on km_kirkwood, you can add my tested-by:

Tested-by: Valentin Longchamp<valentin.longchamp at keymile.com>


From holt at sgi.com  Tue May  7 05:17:34 2013
From: holt at sgi.com (Robin Holt)
Date: Tue, 7 May 2013 04:17:34 -0500
Subject: How does commit 47ec340c not introduce a bug?
Message-ID: <20130507091734.GM3658@sgi.com>

I noticed a warning while cross-compiling all arm defconfigs.

The mmp2_defconfig gave this warning:

drivers/video/backlight/max8925_bl.c: In function 'max8925_backlight_probe':
drivers/video/backlight/max8925_bl.c:177:3: warning: statement with no effect [-Wunused-value]

This appears to have been introduced by the above commit when !CONFIG_OF

Looking at this more closely, I am not sure how this was ever intended
to be handled or how the errors returned in the CONFIG_OF case were
intended to be handled as the return from max8925_backlight_dt_init is
always ignored.

I think this needs some more attention, but do not feel like I know
enough about it or have any means to test it to weigh in.

Thanks,
Robin


commit 47ec340cb8e232671e7c4a4689ff32c3bdf329da
Author: Qing Xu <qingx at marvell.com>
Date:   Mon Feb 4 23:40:45 2013 +0800

    mfd: max8925: Support dt for backlight
    
    Add device tree support in max8925 backlight.
    
    Signed-off-by: Qing Xu <qingx at marvell.com>
    Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
    Signed-off-by: Samuel Ortiz <sameo at linux.intel.com>

diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c
index 2c9bce0..5ca11b0 100644
--- a/drivers/video/backlight/max8925_bl.c
+++ b/drivers/video/backlight/max8925_bl.c
@@ -101,6 +101,29 @@ static const struct backlight_ops max8925_backlight_ops = {
 	.get_brightness	= max8925_backlight_get_brightness,
 };
 
+#ifdef CONFIG_OF
+static int max8925_backlight_dt_init(struct platform_device *pdev,
+			      struct max8925_backlight_pdata *pdata)
+{
+	struct device_node *nproot = pdev->dev.parent->of_node, *np;
+	int dual_string;
+
+	if (!nproot)
+		return -ENODEV;
+	np = of_find_node_by_name(nproot, "backlight");
+	if (!np) {
+		dev_err(&pdev->dev, "failed to find backlight node\n");
+		return -ENODEV;
+	}
+
+	of_property_read_u32(np, "maxim,max8925-dual-string", &dual_string);
+	pdata->dual_string = dual_string;
+	return 0;
+}
+#else
+#define max8925_backlight_dt_init(x, y)	(-1)
+#endif
+
 static int max8925_backlight_probe(struct platform_device *pdev)
 {
 	struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent);
@@ -147,6 +170,13 @@ static int max8925_backlight_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, bl);
 
 	value = 0;
+	if (pdev->dev.parent->of_node && !pdata) {
+		pdata = devm_kzalloc(&pdev->dev,
+				     sizeof(struct max8925_backlight_pdata),
+				     GFP_KERNEL);
+		max8925_backlight_dt_init(pdev, pdata);
+	}
+
 	if (pdata) {
 		if (pdata->lxw_scl)
 			value |= (1 << 7);
@@ -158,7 +188,6 @@ static int max8925_backlight_probe(struct platform_device *pdev)
 	ret = max8925_set_bits(chip->i2c, data->reg_mode_cntl, 0xfe, value);
 	if (ret < 0)
 		goto out_brt;
-
 	backlight_update_status(bl);
 	return 0;
 out_brt:


From Ian.Campbell at citrix.com  Tue May  7 05:17:50 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Tue, 7 May 2013 10:17:50 +0100
Subject: [Xen-devel] [PATCH RFC v2 4/4] xen/arm: account for stolen ticks
In-Reply-To: <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <1367918270.26321.39.camel@zakaz.uk.xensource.com>

On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> Register the runstate_memory_area with the hypervisor.
> Use pv_time_ops.steal_clock to account for stolen ticks.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   23 +++++++++++++++++++++++
>  1 files changed, 23 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index ee86bfa..2a5cc82 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -14,7 +14,10 @@
>  #include <xen/xen-ops.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
> +#include <asm/arch_timer.h>
>  #include <asm/system_misc.h>
> +#include <asm/paravirt.h>
> +#include <linux/jump_label.h>
>  #include <linux/interrupt.h>
>  #include <linux/irqreturn.h>
>  #include <linux/module.h>
> @@ -152,6 +155,20 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
>  }
>  EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
>  
> +unsigned long long xen_stolen_accounting(int cpu)
> +{
> +	struct vcpu_runstate_info state;
> +
> +	if (cpu != get_cpu())

get_cpu disables preempt, so you need a matching put_cpu.

But actually I think you just want smp_processor_id and you probably
want the BUG_ON form to get unlikely etc.

That said, you don't use cpu for anything else, so why not drop it
entirely?

> +		BUG();
> +
> +	xen_get_runstate_snapshot(&state);
> +
> +	WARN_ON(state.state != RUNSTATE_running);
> +
> +	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
> +}
> +
>  static void __init xen_percpu_init(void *unused)
>  {
>  	struct vcpu_register_vcpu_info info;
> @@ -170,6 +187,8 @@ static void __init xen_percpu_init(void *unused)
>  		BUG();
>  	per_cpu(xen_vcpu, cpu) = vcpup;
>  
> +	xen_setup_runstate_info(cpu);
> +
>  	enable_percpu_irq(xen_events_irq, 0);
>  }
>  
> @@ -301,6 +320,10 @@ static int __init xen_init_events(void)
>  
>  	on_each_cpu(xen_percpu_init, NULL, 0);
>  
> +	pv_time_ops.steal_clock = xen_stolen_accounting;
> +	static_key_slow_inc(&paravirt_steal_enabled);
> +	static_key_slow_inc(&paravirt_steal_rq_enabled);

We don't seem to do this on x86 -- is that a bug on x86 on Xen?

> +
>  	return 0;
>  }
>  postcore_initcall(xen_init_events);




From mkl at pengutronix.de  Tue May  7 05:18:53 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Tue, 07 May 2013 11:18:53 +0200
Subject: [PATCH,
 RFC 01/22] can: move CONFIG_HAVE_CAN_FLEXCAN out of CAN_DEV
In-Reply-To: <201305031724.15584.arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-2-git-send-email-arnd@arndb.de>
 <5183892B.8020400@pengutronix.de> <201305031724.15584.arnd@arndb.de>
Message-ID: <5188C6FD.9010903@pengutronix.de>

On 05/03/2013 05:24 PM, Arnd Bergmann wrote:
> On Friday 03 May 2013, Marc Kleine-Budde wrote:
>> On 05/02/2013 05:16 PM, Arnd Bergmann wrote:
>>> CONFIG_HAVE_CAN_FLEXCAN is a silect symbol that is meant to be selected
>>> by platforms that support this driver, but that is not possible without
>>> also selecting CAN_DEV, unless we move it out of the "if CAN_DEV"
>>> section of the Kconfig file.
>>>
>>> warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 &&
>>>  IMX_HAVE_PLATFORM_FLEXCAN && SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
>>>  which has unmet direct dependencies (NET && CAN && CAN_DEV)
>>
>> With the advent of multi platform kernels I like to get rid of
>> HAVE_CAN_FLEXCAN completely.
> 
> Yes, good idea. Are there any other dependencies we need to add then?
> I assume FLEXCAN needs to depend on HAS_IOMEM and OF at least, but
> there might be more.

The driver compiles (tested on SH and blacksfin) and works without
CONFIG_OF (on non DT arm platforms).

Marc
-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From geert at linux-m68k.org  Tue May  7 05:20:26 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Tue,  7 May 2013 11:20:26 +0200
Subject: [PATCH] proc: Use PDE attribute setting accessor functions
Message-ID: <1367918426-7076-1-git-send-email-geert@linux-m68k.org>

arch/arm/mach-msm/last_radio_log.c: In function 'msm_init_last_radio_log':
arch/arm/mach-msm/last_radio_log.c:69:7: error: dereferencing pointer to incomplete type

arch/cris/kernel/profile.c: In function 'init_cris_profile':
arch/cris/kernel/profile.c:79:8: error: dereferencing pointer to incomplete type

Use proc_set_size(), cfr. commit 271a15eabe094538d958dc68ccfc9c36b699247a
("proc: Supply PDE attribute setting accessor functions")

Signed-off-by: Geert Uytterhoeven <geert at linux-m68k.org>
---
 arch/arm/mach-msm/last_radio_log.c |    2 +-
 arch/cris/kernel/profile.c         |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c
index 7777767..9c392a2 100644
--- a/arch/arm/mach-msm/last_radio_log.c
+++ b/arch/arm/mach-msm/last_radio_log.c
@@ -66,6 +66,6 @@ void msm_init_last_radio_log(struct module *owner)
 	pr_err("%s: last radio log is %d bytes long\n", __func__,
 		radio_log_size);
 	last_radio_log_fops.owner = owner;
-	entry->size = radio_log_size;
+	proc_set_size(entry, radio_log_size);
 }
 EXPORT_SYMBOL(msm_init_last_radio_log);
diff --git a/arch/cris/kernel/profile.c b/arch/cris/kernel/profile.c
index b82e086..cd9f15b 100644
--- a/arch/cris/kernel/profile.c
+++ b/arch/cris/kernel/profile.c
@@ -76,7 +76,7 @@ static int __init init_cris_profile(void)
 	entry = proc_create("system_profile", S_IWUSR | S_IRUGO, NULL,
 			    &cris_proc_profile_operations);
 	if (entry) {
-		entry->size = SAMPLE_BUFFER_SIZE;
+		proc_set_size(entry, SAMPLE_BUFFER_SIZE);
 	}
 	prof_running = 1;
 
-- 
1.7.0.4



From will.deacon at arm.com  Tue May  7 05:22:09 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 May 2013 10:22:09 +0100
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130506093059.GH23285@pengutronix.de>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
Message-ID: <20130507092209.GD25387@mudshark.cambridge.arm.com>

On Mon, May 06, 2013 at 10:30:59AM +0100, Uwe Kleine-K?nig wrote:
> Hello,

Hi Uwe,

> On Thu, Apr 18, 2013 at 11:10:19AM +0200, Uwe Kleine-K?nig wrote:
> The patch below fixes the issue for me on V7-M. The only drawback is
> that the list of registers isn't shared. Maybe someone has a nice idea?
> 
> BTW, there doesn't seem to be an equivalent register set for 
> CPUID_{CACHETYPE,TCM,TLBTYPE,MPIDR} on v7-M.

That make sense: we don't have caches, MMUs or SMP.

> Best regards
> Uwe
> 
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 4eb94a3..ec635ff 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -10,6 +10,22 @@
>  #define CPUID_TLBTYPE	3
>  #define CPUID_MPIDR	5
>  
> +#ifdef CONFIG_CPU_V7M
> +#define CPUID_EXT_PFR0	0x40
> +#define CPUID_EXT_PFR1	0x44
> +#define CPUID_EXT_DFR0	0x48
> +#define CPUID_EXT_AFR0	0x4c
> +#define CPUID_EXT_MMFR0	0x50
> +#define CPUID_EXT_MMFR1	0x54
> +#define CPUID_EXT_MMFR2	0x58
> +#define CPUID_EXT_MMFR3	0x5c
> +#define CPUID_EXT_ISAR0	0x60
> +#define CPUID_EXT_ISAR1	0x64
> +#define CPUID_EXT_ISAR2	0x68
> +#define CPUID_EXT_ISAR3	0x6c
> +#define CPUID_EXT_ISAR4	0x70
> +#define CPUID_EXT_ISAR5	0x74
> +#else
>  #define CPUID_EXT_PFR0	"c1, 0"
>  #define CPUID_EXT_PFR1	"c1, 1"
>  #define CPUID_EXT_DFR0	"c1, 2"
> @@ -24,6 +40,7 @@
>  #define CPUID_EXT_ISAR3	"c2, 3"
>  #define CPUID_EXT_ISAR4	"c2, 4"
>  #define CPUID_EXT_ISAR5	"c2, 5"
> +#endif
>  
>  #define MPIDR_SMP_BITMASK (0x3 << 30)
>  #define MPIDR_SMP_VALUE (0x2 << 30)
> @@ -79,7 +96,23 @@ extern unsigned int processor_id;
>  		__val;							\
>  	})
>  
> -#else /* ifdef CONFIG_CPU_CP15 */
> +#elif defined(CONFIG_CPU_V7M)
> +
> +#include <asm/io.h>
> +#include <asm/v7m.h>
> +
> +#define read_cpuid(reg)							\
> +	({								\
> +		WARN_ON_ONCE(1);					\
> +		0;							\
> +	})

We do have an MIDR in PMSAv7 (not to be confused with MPIDR), so why not read
that here?

Will


From Ian.Campbell at citrix.com  Tue May  7 05:23:29 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Tue, 7 May 2013 10:23:29 +0100
Subject: [Xen-devel] [PATCH RFC v2 2/4] arm: introduce CONFIG_PARAVIRT
 and pv_time_ops
In-Reply-To: <1367851878-21629-2-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-2-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <1367918609.26321.43.camel@zakaz.uk.xensource.com>

On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> Introduce CONFIG_PARAVIRT on ARM.

What about PARAVIRT_TIME_ACCOUNTING? I'm not sure what it is but it
looks like a more lightweight version of pv stolen time?

> The only paravirt interface supported is pv_time_ops.steal_clock.
> No runtime pvops patching yet.

Or indeed ever, I think. The use cases for patching on x86 are not
things which carry over to ARM with virt extensions.

> This allows us to make us of steal_account_process_tick for stolen ticks
> accounting.
> 
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> CC: linux at arm.linux.org.uk
> CC: will.deacon at arm.com
> CC: nico at linaro.org
> CC: marc.zyngier at arm.com
> CC: cov at codeaurora.org
> CC: arnd at arndb.de
> CC: olof at lixom.net
> ---
>  arch/arm/Kconfig                |    9 +++++++++
>  arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
>  arch/arm/kernel/Makefile        |    1 +
>  arch/arm/kernel/paravirt.c      |   32 ++++++++++++++++++++++++++++++++
>  4 files changed, 61 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/include/asm/paravirt.h
>  create mode 100644 arch/arm/kernel/paravirt.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 344e299..35cb10a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1887,12 +1887,21 @@ config XEN_DOM0
>  	def_bool y
>  	depends on XEN
>  
> +config PARAVIRT
> +	bool "Enable paravirtualization code"
> +	---help---
> +	  This changes the kernel so it can modify itself when it is run
> +	  under a hypervisor, potentially improving performance significantly
> +	  over full virtualization.  However, when run without a hypervisor
> +	  the kernel is theoretically slower and slightly larger.

I'm not sure this description (carried over from x86) are really true
for ARM. e.g. the downsides there when not virtualised are in the PV MMU
(pte operations) and interrupt masking stuff, which should never make
its way onto ARM.

I think it would be a worthwhile change to refactor the stolen time
handling out from under the rather wide reaching umbrella of the x86
PARAVIRT option. (assuming PARAVIRT_TIME_ACCOUNTING isn't already that)

> +
>  config XEN
>  	bool "Xen guest support on ARM (EXPERIMENTAL)"
>  	depends on ARM && AEABI && OF
>  	depends on CPU_V7 && !CPU_V6
>  	depends on !GENERIC_ATOMIC64
>  	select ARM_PSCI
> +	select PARAVIRT
>  	help
>  	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
>  
> diff --git a/arch/arm/include/asm/paravirt.h b/arch/arm/include/asm/paravirt.h
> new file mode 100644
> index 0000000..3b95bc6
> --- /dev/null
> +++ b/arch/arm/include/asm/paravirt.h
> @@ -0,0 +1,19 @@
> +#ifndef _ASM_ARM_PARAVIRT_H
> +#define _ASM_ARM_PARAVIRT_H
> +
> +struct static_key;
> +extern struct static_key paravirt_steal_enabled;
> +extern struct static_key paravirt_steal_rq_enabled;
> +
> +struct pv_time_ops {
> +	unsigned long long (*steal_clock)(int cpu);
> +};
> +extern struct pv_time_ops pv_time_ops;
> +
> +static inline u64 paravirt_steal_clock(int cpu)
> +{
> +	return pv_time_ops.steal_clock(cpu);
> +}
> +
> +
> +#endif
> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> index dd9d90a..6764f60 100644
> --- a/arch/arm/kernel/Makefile
> +++ b/arch/arm/kernel/Makefile
> @@ -86,5 +86,6 @@ ifeq ($(CONFIG_ARM_PSCI),y)
>  obj-y				+= psci.o
>  obj-$(CONFIG_SMP)		+= psci_smp.o
>  endif
> +obj-$(CONFIG_PARAVIRT)	+= paravirt.o
>  
>  extra-y := $(head-y) vmlinux.lds
> diff --git a/arch/arm/kernel/paravirt.c b/arch/arm/kernel/paravirt.c
> new file mode 100644
> index 0000000..3e73fc8
> --- /dev/null
> +++ b/arch/arm/kernel/paravirt.c
> @@ -0,0 +1,32 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Copyright (C) 2013 Citrix Systems
> + *
> + * Author: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> + */
> +
> +#include <linux/export.h>
> +#include <linux/jump_label.h>
> +#include <linux/types.h>
> +#include <asm/paravirt.h>
> +
> +struct static_key paravirt_steal_enabled;
> +struct static_key paravirt_steal_rq_enabled;
> +
> +static u64 native_steal_clock(int cpu)
> +{
> +	return 0;
> +}
> +
> +struct pv_time_ops pv_time_ops = {
> +	.steal_clock = native_steal_clock,
> +};
> +EXPORT_SYMBOL_GPL(pv_time_ops);

This foo_ops.bar and native_bar thing is a bit of a hangover from the
paravirt patching infrastructure on x86 and it doesn't really apply
here.

Given that the call to paravirt_steal_time call is already protected by
this static_key stuff I think it would be safe to leave the hook as NULL
in the case where it is unused.

Given all the different clock sources on ARM is there not an existing
ops struct where this could live?

Ian.



From u.kleine-koenig at pengutronix.de  Tue May  7 05:24:28 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 7 May 2013 11:24:28 +0200
Subject: How does commit 47ec340c not introduce a bug?
In-Reply-To: <20130507091734.GM3658@sgi.com>
References: <20130507091734.GM3658@sgi.com>
Message-ID: <20130507092428.GK23285@pengutronix.de>

Hello,

On Tue, May 07, 2013 at 04:17:34AM -0500, Robin Holt wrote:
> I noticed a warning while cross-compiling all arm defconfigs.
> 
> The mmp2_defconfig gave this warning:
> 
> drivers/video/backlight/max8925_bl.c: In function 'max8925_backlight_probe':
> drivers/video/backlight/max8925_bl.c:177:3: warning: statement with no effect [-Wunused-value]
> 
> This appears to have been introduced by the above commit when !CONFIG_OF
> 
> Looking at this more closely, I am not sure how this was ever intended
> to be handled or how the errors returned in the CONFIG_OF case were
> intended to be handled as the return from max8925_backlight_dt_init is
> always ignored.
> 
> I think this needs some more attention, but do not feel like I know
> enough about it or have any means to test it to weigh in.
> 
> Thanks,
> Robin
> 
> 
> commit 47ec340cb8e232671e7c4a4689ff32c3bdf329da
> Author: Qing Xu <qingx at marvell.com>
> Date:   Mon Feb 4 23:40:45 2013 +0800
> 
>     mfd: max8925: Support dt for backlight
>     
>     Add device tree support in max8925 backlight.
>     
>     Signed-off-by: Qing Xu <qingx at marvell.com>
>     Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
>     Signed-off-by: Samuel Ortiz <sameo at linux.intel.com>
> 
> diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c
> index 2c9bce0..5ca11b0 100644
> --- a/drivers/video/backlight/max8925_bl.c
> +++ b/drivers/video/backlight/max8925_bl.c
> @@ -101,6 +101,29 @@ static const struct backlight_ops max8925_backlight_ops = {
>  	.get_brightness	= max8925_backlight_get_brightness,
>  };
>  
> +#ifdef CONFIG_OF
> +static int max8925_backlight_dt_init(struct platform_device *pdev,
> +			      struct max8925_backlight_pdata *pdata)
> +{
> +	struct device_node *nproot = pdev->dev.parent->of_node, *np;
> +	int dual_string;
> +
> +	if (!nproot)
> +		return -ENODEV;
> +	np = of_find_node_by_name(nproot, "backlight");
> +	if (!np) {
> +		dev_err(&pdev->dev, "failed to find backlight node\n");
> +		return -ENODEV;
> +	}
> +
> +	of_property_read_u32(np, "maxim,max8925-dual-string", &dual_string);
> +	pdata->dual_string = dual_string;
> +	return 0;
> +}
> +#else
> +#define max8925_backlight_dt_init(x, y)	(-1)
It's probably best to make this:

static inline max8925_backlight_dt_init(struct platform_device *pdev,
				struct max8925_backlight_pdata *pdata)
{
	return -ENODEV;
}

> +#endif
> +
>  static int max8925_backlight_probe(struct platform_device *pdev)
>  {
>  	struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent);
> @@ -147,6 +170,13 @@ static int max8925_backlight_probe(struct platform_device *pdev)
>  	platform_set_drvdata(pdev, bl);
>  
>  	value = 0;
> +	if (pdev->dev.parent->of_node && !pdata) {
> +		pdata = devm_kzalloc(&pdev->dev,
> +				     sizeof(struct max8925_backlight_pdata),
> +				     GFP_KERNEL);
> +		max8925_backlight_dt_init(pdev, pdata);
> +	}
> +
>  	if (pdata) {
>  		if (pdata->lxw_scl)
>  			value |= (1 << 7);
> @@ -158,7 +188,6 @@ static int max8925_backlight_probe(struct platform_device *pdev)
>  	ret = max8925_set_bits(chip->i2c, data->reg_mode_cntl, 0xfe, value);
>  	if (ret < 0)
>  		goto out_brt;
> -
>  	backlight_update_status(bl);
>  	return 0;
>  out_brt:
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From nicolas.ferre at atmel.com  Tue May  7 05:31:24 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 May 2013 11:31:24 +0200
Subject: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
 xfer->speed_hz set
In-Reply-To: <B256D81BAE5131468A838E5D7A24364154238AF5@penmbx02>
References: <1362626715-6549-1-git-send-email-wenyou.yang@atmel.com>
 <1362626815-6628-1-git-send-email-wenyou.yang@atmel.com>
 <CAGhQ9VwW18LXY5Jn0FUFCaAzKxP1W3QADG=JBp9JbgaAwo=F2Q@mail.gmail.com>
 <B256D81BAE5131468A838E5D7A24364154236AB5@penmbx02>
 <CACQ1gAhZO3stjrwf5SiZf7jOO8T5bAJZiz97M7+7vwFmk2e65g@mail.gmail.com>
 <5182414F.1000201@atmel.com>
 <20130506103105.GB13472@opensource.wolfsonmicro.com>
 <B256D81BAE5131468A838E5D7A24364154238AF5@penmbx02>
Message-ID: <5188C9EC.7000303@atmel.com>

On 07/05/2013 03:11, Yang, Wenyou :
> Hi, Mark
> 
>> From: Mark Brown [mailto:broonie at kernel.org]
>> Sent: 2013?5?6? 18:31
>> To: Ferre, Nicolas
>> Cc: grant.likely at secretlab.ca; Grant Likely; Richard Genoud; Yang, Wenyou;
>> Joachim Eastwood; linux-arm-kernel at lists.infradead.org;
>> plagnioj at jcrosoft.com; Lin, JM; spi-devel-general at lists.sourceforge.net;
>> linux-kernel at vger.kernel.org
>> Subject: Re: [PATCH v6 01/16] spi/spi-atmel: fix probing failure after
>> xfer->speed_hz set
>>
>> On Thu, May 02, 2013 at 12:34:55PM +0200, Nicolas Ferre wrote:
>>
>>> Can you tell us if this SPI patch will be merged upstream using one of
>>> your paths?
>>
>> I have no idea what patch this is but if it's not in my tree -next it's unlikely to be
>> merged.
> This is dropped patch, no need to be merged.
> 
> We tested Atmel spi in your tree-next , but it doesn't work, the reason is the Joachim Eastwood's patch is not included.
> https://patchwork.kernel.org/patch/2165301/
> which Joachim said that Grant said he applied.

Hi Wenyou,

Sorry for not having communicating with you after Mark told me the story
about this patch: Mark merged Grant's material in his SPI tree (with is
the official one nowadays). You can see that by browsing linux-next:

 Merge remote-tracking branch 'spi/fix/grant' into spi-linus

Joachim's patch is well included in it. We still have to monitor
inclusion of it in Linus' tree...

Mark, sorry for the noise.

Bye,
-- 
Nicolas Ferre


From u.kleine-koenig at pengutronix.de  Tue May  7 05:35:08 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 7 May 2013 11:35:08 +0200
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130507092209.GD25387@mudshark.cambridge.arm.com>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
 <20130507092209.GD25387@mudshark.cambridge.arm.com>
Message-ID: <20130507093508.GL23285@pengutronix.de>

Hello Will,

On Tue, May 07, 2013 at 10:22:09AM +0100, Will Deacon wrote:
> On Mon, May 06, 2013 at 10:30:59AM +0100, Uwe Kleine-K?nig wrote:
> > On Thu, Apr 18, 2013 at 11:10:19AM +0200, Uwe Kleine-K?nig wrote:
> > The patch below fixes the issue for me on V7-M. The only drawback is
> > that the list of registers isn't shared. Maybe someone has a nice idea?
> > 
> > BTW, there doesn't seem to be an equivalent register set for 
> > CPUID_{CACHETYPE,TCM,TLBTYPE,MPIDR} on v7-M.
> 
> That make sense: we don't have caches, MMUs or SMP.
IMHO the sensible thing is to implement the registers then and let them
tell: I don't have these things.

> > diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> > index 4eb94a3..ec635ff 100644
> > --- a/arch/arm/include/asm/cputype.h
> > +++ b/arch/arm/include/asm/cputype.h
> > @@ -10,6 +10,22 @@
> >  #define CPUID_TLBTYPE	3
> >  #define CPUID_MPIDR	5
> >  
> > +#ifdef CONFIG_CPU_V7M
> > +#define CPUID_EXT_PFR0	0x40
> > +#define CPUID_EXT_PFR1	0x44
> > +#define CPUID_EXT_DFR0	0x48
> > +#define CPUID_EXT_AFR0	0x4c
> > +#define CPUID_EXT_MMFR0	0x50
> > +#define CPUID_EXT_MMFR1	0x54
> > +#define CPUID_EXT_MMFR2	0x58
> > +#define CPUID_EXT_MMFR3	0x5c
> > +#define CPUID_EXT_ISAR0	0x60
> > +#define CPUID_EXT_ISAR1	0x64
> > +#define CPUID_EXT_ISAR2	0x68
> > +#define CPUID_EXT_ISAR3	0x6c
> > +#define CPUID_EXT_ISAR4	0x70
> > +#define CPUID_EXT_ISAR5	0x74
> > +#else
> >  #define CPUID_EXT_PFR0	"c1, 0"
> >  #define CPUID_EXT_PFR1	"c1, 1"
> >  #define CPUID_EXT_DFR0	"c1, 2"
> > @@ -24,6 +40,7 @@
> >  #define CPUID_EXT_ISAR3	"c2, 3"
> >  #define CPUID_EXT_ISAR4	"c2, 4"
> >  #define CPUID_EXT_ISAR5	"c2, 5"
> > +#endif
> >  
> >  #define MPIDR_SMP_BITMASK (0x3 << 30)
> >  #define MPIDR_SMP_VALUE (0x2 << 30)
> > @@ -79,7 +96,23 @@ extern unsigned int processor_id;
> >  		__val;							\
> >  	})
> >  
> > -#else /* ifdef CONFIG_CPU_CP15 */
> > +#elif defined(CONFIG_CPU_V7M)
> > +
> > +#include <asm/io.h>
> > +#include <asm/v7m.h>
> > +
> > +#define read_cpuid(reg)							\
> > +	({								\
> > +		WARN_ON_ONCE(1);					\
> > +		0;							\
> > +	})
> 
> We do have an MIDR in PMSAv7 (not to be confused with MPIDR), so why not read
> that here?
I don't know it and it's unrelated to this patch. But I will note it and
check it. In the meantime I'm taking patches of course :-)

Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From haojian.zhuang at gmail.com  Tue May  7 05:35:28 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 7 May 2013 17:35:28 +0800
Subject: How does commit 47ec340c not introduce a bug?
In-Reply-To: <20130507092428.GK23285@pengutronix.de>
References: <20130507091734.GM3658@sgi.com>
 <20130507092428.GK23285@pengutronix.de>
Message-ID: <CAN1soZyHx1XZzukunbKsj+v4h93MRQKjPPjJ3+i3u8BeBbhCGw@mail.gmail.com>

On Tue, May 7, 2013 at 5:24 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> Hello,
>
> On Tue, May 07, 2013 at 04:17:34AM -0500, Robin Holt wrote:
>> I noticed a warning while cross-compiling all arm defconfigs.
>>
>> The mmp2_defconfig gave this warning:
>>
>> drivers/video/backlight/max8925_bl.c: In function 'max8925_backlight_probe':
>> drivers/video/backlight/max8925_bl.c:177:3: warning: statement with no effect [-Wunused-value]
>>
>> This appears to have been introduced by the above commit when !CONFIG_OF
>>
>> Looking at this more closely, I am not sure how this was ever intended
>> to be handled or how the errors returned in the CONFIG_OF case were
>> intended to be handled as the return from max8925_backlight_dt_init is
>> always ignored.
>>
>> I think this needs some more attention, but do not feel like I know
>> enough about it or have any means to test it to weigh in.
>>
>> Thanks,
>> Robin
>>
>>
>> commit 47ec340cb8e232671e7c4a4689ff32c3bdf329da
>> Author: Qing Xu <qingx at marvell.com>
>> Date:   Mon Feb 4 23:40:45 2013 +0800
>>
>>     mfd: max8925: Support dt for backlight
>>
>>     Add device tree support in max8925 backlight.
>>
>>     Signed-off-by: Qing Xu <qingx at marvell.com>
>>     Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
>>     Signed-off-by: Samuel Ortiz <sameo at linux.intel.com>
>>
>> diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c
>> index 2c9bce0..5ca11b0 100644
>> --- a/drivers/video/backlight/max8925_bl.c
>> +++ b/drivers/video/backlight/max8925_bl.c
>> @@ -101,6 +101,29 @@ static const struct backlight_ops max8925_backlight_ops = {
>>       .get_brightness = max8925_backlight_get_brightness,
>>  };
>>
>> +#ifdef CONFIG_OF
>> +static int max8925_backlight_dt_init(struct platform_device *pdev,
>> +                           struct max8925_backlight_pdata *pdata)
>> +{
>> +     struct device_node *nproot = pdev->dev.parent->of_node, *np;
>> +     int dual_string;
>> +
>> +     if (!nproot)
>> +             return -ENODEV;
>> +     np = of_find_node_by_name(nproot, "backlight");
>> +     if (!np) {
>> +             dev_err(&pdev->dev, "failed to find backlight node\n");
>> +             return -ENODEV;
>> +     }
>> +
>> +     of_property_read_u32(np, "maxim,max8925-dual-string", &dual_string);
>> +     pdata->dual_string = dual_string;
>> +     return 0;
>> +}
>> +#else
>> +#define max8925_backlight_dt_init(x, y)      (-1)
> It's probably best to make this:
>
> static inline max8925_backlight_dt_init(struct platform_device *pdev,
>                                 struct max8925_backlight_pdata *pdata)
> {
>         return -ENODEV;
> }
>

I've submitted this patch to fix this issue for a long time.

Samuel,

Should I send it again?

Regards
Haojian


From jamie at jamieiles.com  Tue May  7 05:36:02 2013
From: jamie at jamieiles.com (Jamie Iles)
Date: Tue, 7 May 2013 10:36:02 +0100
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <20130426214313.GB24891@amd.pavel.ucw.cz>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <20130426124128.GB6946@page>
 <20130426213723.GA24891@amd.pavel.ucw.cz>
 <20130426214313.GB24891@amd.pavel.ucw.cz>
Message-ID: <20130507093602.GA30902@page>

Hi Pavel,

Apologies for the delay, but this looks good to me.

On Fri, Apr 26, 2013 at 11:43:14PM +0200, Pavel Machek wrote:
> It seems we made a mistake when creating dw_apb_timer_of.c:
> picoxcell sched_clock had parts that were not related to
> dw_apb_timer, yet we moved them to dw_apb_timer_of, and tried to
> use them on socfpga.
> 
> This results in system where user/system time is not measured
> properly, as demonstrated by
>     
>     time dd if=/dev/urandom of=/dev/zero bs=100000 count=100
>     
> So this patch switches sched_clock to hardware that exists on both
> platforms, and adds missing of_node_put() in dw_apb_timer_init().
>     
> Signed-off-by: Pavel Machek <pavel at denx.de>

Acked-by: Jamie Iles <jamie at jamieiles.com>


From dhowells at redhat.com  Tue May  7 05:37:30 2013
From: dhowells at redhat.com (David Howells)
Date: Tue, 07 May 2013 10:37:30 +0100
Subject: [PATCH] proc: Use PDE attribute setting accessor functions
In-Reply-To: <1367918426-7076-1-git-send-email-geert@linux-m68k.org>
References: <1367918426-7076-1-git-send-email-geert@linux-m68k.org>
Message-ID: <23761.1367919450@warthog.procyon.org.uk>

Geert Uytterhoeven <geert at linux-m68k.org> wrote:

> arch/arm/mach-msm/last_radio_log.c: In function 'msm_init_last_radio_log':
> arch/arm/mach-msm/last_radio_log.c:69:7: error: dereferencing pointer to incomplete type
> 
> arch/cris/kernel/profile.c: In function 'init_cris_profile':
> arch/cris/kernel/profile.c:79:8: error: dereferencing pointer to incomplete type
> 
> Use proc_set_size(), cfr. commit 271a15eabe094538d958dc68ccfc9c36b699247a
> ("proc: Supply PDE attribute setting accessor functions")
> 
> Signed-off-by: Geert Uytterhoeven <geert at linux-m68k.org>

Acked-by: David Howells <dhowells at redhat.com>


From srinidhi.kasagar at stericsson.com  Tue May  7 05:42:06 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Tue, 7 May 2013 15:12:06 +0530
Subject: [PATCH 54/63] ARM: ux500: Replace ST-E's home-brew DMA
 direction definition with the generic one
In-Reply-To: <20130507073921.GT24153@gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-55-git-send-email-lee.jones@linaro.org>
 <20130506071355.GA5552@bnru10> <20130507073921.GT24153@gmail.com>
Message-ID: <20130507094205.GA32548@bnru10>

On Tue, May 07, 2013 at 09:39:21 +0200, Lee Jones wrote:
> On Mon, 06 May 2013, Srinidhi Kasagar wrote:
> 
> > On Fri, May 03, 2013 at 16:32:40 +0200, Lee Jones wrote:
> > > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > > duplicating such things.
> > > 
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > > ---
> > >  arch/arm/mach-ux500/board-mop500-audio.c |   12 ++++++------
> > >  arch/arm/mach-ux500/board-mop500-sdi.c   |   16 ++++++++--------
> > >  arch/arm/mach-ux500/board-mop500.c       |   22 +++++++++++-----------
> > >  arch/arm/mach-ux500/usb.c                |    4 ++--
> > >  4 files changed, 27 insertions(+), 27 deletions(-)
> > 
> > Hope you have taken care for all other files, because, I see
> > few more instances in my tree apart from the above files.
> 
> Would you be kind enough to paste those files please?

arch/arm/mach-ux500/board-mop500-audio.c:       .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500-audio.c:       .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500-audio.c:       .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500.c:                             .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500.c:             .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
arch/arm/mach-ux500/devices-db8500.c:   .dir = STEDMA40_MEM_TO_MEM,
arch/arm/mach-ux500/devices-db8500.c:   .dir = STEDMA40_MEM_TO_MEM,
arch/arm/mach-ux500/usb.c:              .dir = STEDMA40_MEM_TO_PERIPH, \

regards,
srinidhi


From hvaibhav at ti.com  Tue May  7 05:39:32 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 7 May 2013 15:09:32 +0530
Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output on
 SoC pad
Message-ID: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>

'clkout2' comes out on the device pad and is being used by various
external on-board peripherals like, Audio codecs, Wilink and stuff.
So enable the clkout2 by default during init sequence itself
along with right pinmux configuration clkout2 output.

Also, add the missing entry of "clkout2_ck" to the AM33xx clock table.

As far as enabling of clkout2 during init is concerned,
we can argue that it can be handled using DT property and enable
the clock only when specified; but not until OMAP clock-tree
migration to DT.

Vaibhav Hiremath (2):
  ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init
  ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output

 arch/arm/boot/dts/am335x-bone.dts     |    8 +++++++-
 arch/arm/boot/dts/am335x-evm.dts      |    8 +++++++-
 arch/arm/boot/dts/am335x-evmsk.dts    |    8 +++++++-
 arch/arm/mach-omap2/cclock33xx_data.c |    2 ++
 4 files changed, 23 insertions(+), 3 deletions(-)



From hvaibhav at ti.com  Tue May  7 05:39:34 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 7 May 2013 15:09:34 +0530
Subject: [PATCH 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad used for
 clock output
In-Reply-To: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1367919574-21353-3-git-send-email-hvaibhav@ti.com>

xdma_event_intr1.clkout2 pad can be used to source clock
from either 32K OSC or any of the PLL (except MPU) outputs.
On the existing AM335x based boards (EVM, EVM-SK and Bone),
this pad is used to feed the clock to audio codes.

So, this patch configures the pinmux to get clkout2 on the pad.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts  |    8 +++++++-
 arch/arm/boot/dts/am335x-evm.dts   |    8 +++++++-
 arch/arm/boot/dts/am335x-evmsk.dts |    8 +++++++-
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index bfba6fc..f4630a3 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
 
 	am33xx_pinmux: pinmux at 44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <>;
+		pinctrl-0 = <&clkout2_pin>;
 
 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
@@ -50,6 +50,12 @@
 				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
 			>;
 		};
+
+		clkout2_pin: pinumx_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			>;
+		};
 	};
 
 	ocp {
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index f598ed2..0673308 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,7 @@
 
 	am33xx_pinmux: pinmux at 44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
 
 		matrix_keypad_s0: matrix_keypad_s0 {
 			pinctrl-single,pins = <
@@ -65,6 +65,12 @@
 				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
 			>;
 		};
+
+		clkout2_pin: pinumx_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			>;
+		};
 	};
 
 	ocp {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 0eec644..a559389 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
 
 	am33xx_pinmux: pinmux at 44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&gpio_keys_s0>;
+		pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
 
 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
@@ -65,6 +65,12 @@
 				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
 			>;
 		};
+
+		clkout2_pin: pinumx_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			>;
+		};
 	};
 
 	ocp {
-- 
1.7.0.4



From hvaibhav at ti.com  Tue May  7 05:39:33 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 7 May 2013 15:09:33 +0530
Subject: [PATCH 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2 as part of
 init
In-Reply-To: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1367919574-21353-2-git-send-email-hvaibhav@ti.com>

clkout2 comes out on the pad and is being used by various
external on-board peripherals like, Audio codecs and stuff.
So enable the clkout2 by default during init sequence itself.

Also, add the missing entry of "clkout2_ck" to the clock table.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
---
 arch/arm/mach-omap2/cclock33xx_data.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 6fd0ed1..a8140b6 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -979,6 +979,7 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
 	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
 	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
+	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
 };
 
 
@@ -989,6 +990,7 @@ static const char *enable_init_clks[] = {
 	"l4hs_gclk",
 	"l4fw_gclk",
 	"l4ls_gclk",
+	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
 };
 
 int __init am33xx_clk_init(void)
-- 
1.7.0.4



From manjunath.goudar at linaro.org  Tue May  7 05:48:14 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue,  7 May 2013 15:18:14 +0530
Subject: [RFC PATCH 0/2] USB: OHCI: Start splitting up the driver
In-Reply-To: <y>
References: <y>
Message-ID: <1367920096-15137-1-git-send-email-manjunath.goudar@linaro.org>

This series of patches begins the process of splitting ohci-hcd up into
a core library module and independent pci driver modules.

Patch 1/2 prepares the way by exporting a few functions from ohci-hcd
and adding a new mechanism for platform-specific drivers to initialize
their hc_driver structures.  This deserves to be done in the core
because almost all of the entries in these structures are pure
boilerplate -- practically none of the drivers need to override more
than three of the standard core values.

Patch 2/2  separate out ohci-pci into independent driver modules.

Manjunath Goudar (2):
  USB: OHCI: prepare to make ohci-hcd a library module
  USB: OHCI: make ohci-pci a separate driver

 drivers/usb/host/Kconfig         |    9 ++-
 drivers/usb/host/Makefile        |    3 +
 drivers/usb/host/ohci-hcd.c      |  142 +++++++++++++++++++++++++++++---------
 drivers/usb/host/ohci-pci.c      |  129 ++++++++++------------------------
 drivers/usb/host/ohci-platform.c |    2 +-
 drivers/usb/host/ohci-q.c        |   13 ++++
 drivers/usb/host/ohci.h          |   30 +++++++-
 7 files changed, 197 insertions(+), 131 deletions(-)

-- 
1.7.9.5



From manjunath.goudar at linaro.org  Tue May  7 05:48:15 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue,  7 May 2013 15:18:15 +0530
Subject: [RFC PATCH 1/2] USB: OHCI: prepare to make ohci-hcd a library module
In-Reply-To: <1367920096-15137-1-git-send-email-manjunath.goudar@linaro.org>
References: <y> <1367920096-15137-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1367920096-15137-2-git-send-email-manjunath.goudar@linaro.org>

This patch prepares ohci-hcd for being split up into a core
library and separate platform driver modules.  A generic
ohci_hc_driver structure is created, containing all the "standard"
values, and a new mechanism is added whereby a driver module can
specify a set of overrides to those values.  In addition the
ohci_restart(),ohci_suspend() and ohci_resume() routines need
to be EXPORTed for use by the drivers.

In V2:
-ohci_hcd_init(), ohci_run() and ohci_stop revert back to static routine.
-ohci_setup() and ohci_start() functions written to generic OHCI initialization
 for all ohci bus glue.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Makefile        |    2 +
 drivers/usb/host/ohci-hcd.c      |  123 +++++++++++++++++++++++++++++++++-----
 drivers/usb/host/ohci-pci.c      |    2 +-
 drivers/usb/host/ohci-platform.c |    2 +-
 drivers/usb/host/ohci.h          |   30 +++++++++-
 5 files changed, 138 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 58c14c1..a38d76b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -40,7 +40,9 @@ obj-$(CONFIG_USB_EHCI_TEGRA)    +=ehci-tegra.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
+
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9e6de95..7922c61 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -79,13 +79,7 @@ static const char	hcd_name [] = "ohci_hcd";
 #include "pci-quirks.h"
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
-static int ohci_init (struct ohci_hcd *ohci);
-static void ohci_stop (struct usb_hcd *hcd);
-
-#if defined(CONFIG_PM) || defined(CONFIG_PCI)
-static int ohci_restart (struct ohci_hcd *ohci);
-#endif
-
+static void ohci_stop(struct usb_hcd *hcd);
 #ifdef CONFIG_PCI
 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
 #else
@@ -520,7 +514,7 @@ done:
 
 /* init memory, and kick BIOS/SMM off */
 
-static int ohci_init (struct ohci_hcd *ohci)
+int ohci_init(struct ohci_hcd *ohci)
 {
 	int ret;
 	struct usb_hcd *hcd = ohci_to_hcd(ohci);
@@ -590,6 +584,7 @@ static int ohci_init (struct ohci_hcd *ohci)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(ohci_init);
 
 /*-------------------------------------------------------------------------*/
 
@@ -597,11 +592,11 @@ static int ohci_init (struct ohci_hcd *ohci)
  * resets USB and controller
  * enable interrupts
  */
-static int ohci_run (struct ohci_hcd *ohci)
+static int ohci_run(struct usb_hcd *hcd)
 {
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	u32			mask, val;
 	int			first = ohci->fminterval == 0;
-	struct usb_hcd		*hcd = ohci_to_hcd(ohci);
 
 	ohci->rh_state = OHCI_RH_HALTED;
 
@@ -767,7 +762,37 @@ retry:
 
 	return 0;
 }
+/*------------------------------------------------------------------------*/
+
+/* ohci generic function for all OHCI bus glue */
+
+static int ohci_setup(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int retval;
+
+	ohci->sbrn = HCD_USB11;
+
+	/* data structure init */
+	retval = ohci_init(ohci);
+	if (retval)
+		return retval;
+	ohci_usb_reset(ohci);
+	return 0;
+}
 
+static int ohci_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int	ret;
+	ret = ohci_run(hcd);
+	if (ret < 0) {
+		ohci_err(ohci, "can't start\n");
+		ohci_stop(hcd);
+	}
+	return ret;
+}
+/*-------------------------------------------------------------------------*/
 /*-------------------------------------------------------------------------*/
 
 /* an interrupt happens */
@@ -949,11 +974,12 @@ static void ohci_stop (struct usb_hcd *hcd)
 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 
 /* must not be called from interrupt context */
-static int ohci_restart (struct ohci_hcd *ohci)
+int ohci_restart(struct ohci_hcd *ohci)
 {
 	int temp;
 	int i;
 	struct urb_priv *priv;
+	struct usb_hcd	*hcd;
 
 	spin_lock_irq(&ohci->lock);
 	ohci->rh_state = OHCI_RH_HALTED;
@@ -1001,19 +1027,22 @@ static int ohci_restart (struct ohci_hcd *ohci)
 	ohci->ed_controltail = NULL;
 	ohci->ed_bulktail    = NULL;
 
-	if ((temp = ohci_run (ohci)) < 0) {
-		ohci_err (ohci, "can't restart, %d\n", temp);
+	hcd = ohci_to_hcd(ohci);
+	temp = ohci_run(hcd);
+	if (temp < 0) {
+		ohci_err(ohci, "can't restart, %d\n", temp);
 		return temp;
 	}
 	ohci_dbg(ohci, "restart complete\n");
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_restart);
 
 #endif
 
 #ifdef CONFIG_PM
 
-static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
 	unsigned long	flags;
@@ -1031,9 +1060,9 @@ static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_suspend);
 
-
-static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
+int ohci_resume(struct usb_hcd *hcd, bool hibernated)
 {
 	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	int			port;
@@ -1081,11 +1110,73 @@ static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_resume);
 
 #endif
 
 /*-------------------------------------------------------------------------*/
 
+/*
+ * Generic structure: This gets copied for platform drivers so that
+ * individual entries can be overridden as needed.
+ */
+
+static const struct hc_driver ohci_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "OHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	*/
+	.irq =                  ohci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/*
+	* basic lifecycle operations
+	*/
+	.reset =		ohci_setup,
+	.start =                ohci_start,
+	.stop =                 ohci_stop,
+	.shutdown =             ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	*/
+	.urb_enqueue =          ohci_urb_enqueue,
+	.urb_dequeue =          ohci_urb_dequeue,
+	.endpoint_disable =     ohci_endpoint_disable,
+
+	/*
+	* scheduling support
+	*/
+	.get_frame_number =     ohci_get_frame,
+
+	/*
+	* root hub support
+	*/
+	.hub_status_data =      ohci_hub_status_data,
+	.hub_control =          ohci_hub_control,
+	.bus_suspend =          ohci_bus_suspend,
+	.bus_resume =           ohci_bus_resume,
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+void ohci_init_driver(struct hc_driver *drv,
+		const struct ohci_driver_overrides *over)
+{
+	/* Copy the generic table to drv and then apply the overrides */
+	*drv = ohci_hc_driver;
+
+	drv->product_desc = over->product_desc;
+	drv->hcd_priv_size += over->extra_priv_size;
+	if (over->reset)
+		drv->reset = over->reset;
+}
+EXPORT_SYMBOL_GPL(ohci_init_driver);
+
+/*-------------------------------------------------------------------------*/
+
 MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 951514e..0b34b59 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -288,7 +288,7 @@ static int ohci_pci_start (struct usb_hcd *hcd)
 	}
 #endif /* CONFIG_PM */
 
-	ret = ohci_run (ohci);
+	ret = ohci_run(hcd);
 	if (ret < 0) {
 		ohci_err (ohci, "can't start\n");
 		ohci_stop (hcd);
diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
index c3e7287..545c657 100644
--- a/drivers/usb/host/ohci-platform.c
+++ b/drivers/usb/host/ohci-platform.c
@@ -46,7 +46,7 @@ static int ohci_platform_start(struct usb_hcd *hcd)
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 	int err;
 
-	err = ohci_run(ohci);
+	err = ohci_run(hcd);
 	if (err < 0) {
 		ohci_err(ohci, "can't start\n");
 		ohci_stop(hcd);
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index d329914..455e9b1 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -357,7 +357,6 @@ struct ohci_hcd {
 	 * I/O memory used to communicate with the HC (dma-consistent)
 	 */
 	struct ohci_regs __iomem *regs;
-
 	/*
 	 * main memory used to communicate with the HC (dma-consistent).
 	 * hcd adds to schedule for a live hc any time, but removals finish
@@ -373,7 +372,6 @@ struct ohci_hcd {
 	struct ed		*periodic [NUM_INTS];	/* shadow int_table */
 
 	void (*start_hnp)(struct ohci_hcd *ohci);
-
 	/*
 	 * memory management for queue data structures
 	 */
@@ -392,7 +390,7 @@ struct ohci_hcd {
 	unsigned long		next_statechange;	/* suspend/resume */
 	u32			fminterval;		/* saved register */
 	unsigned		autostop:1;	/* rh auto stopping/stopped */
-
+	u8			sbrn;
 	unsigned long		flags;		/* for HC bugs */
 #define	OHCI_QUIRK_AMD756	0x01			/* erratum #4 */
 #define	OHCI_QUIRK_SUPERIO	0x02			/* natsemi */
@@ -718,3 +716,29 @@ static inline u32 roothub_status (struct ohci_hcd *hc)
 	{ return ohci_readl (hc, &hc->regs->roothub.status); }
 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+/* Declarations of things exported for use by ohci platform drivers */
+
+struct ohci_driver_overrides {
+	const char	*product_desc;
+	size_t		extra_priv_size;
+	int		(*reset)(struct usb_hcd *hcd);
+};
+
+extern void	ohci_init_driver(struct hc_driver *drv,
+				const struct ohci_driver_overrides *over);
+extern int	ohci_init(struct ohci_hcd *ohci);
+extern int	ohci_restart(struct ohci_hcd *ohci);
+#ifdef CONFIG_PM
+extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
+extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
+#else
+static inline int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+{
+	return 0;
+}
+static inline int ohci_resume(struct usb_hcd *hcd, bool hibernated)
+{
+	return 0;
+}
+#endif
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Tue May  7 05:48:16 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue,  7 May 2013 15:18:16 +0530
Subject: [RFC PATCH 2/2] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1367920096-15137-1-git-send-email-manjunath.goudar@linaro.org>
References: <y> <1367920096-15137-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1367920096-15137-3-git-send-email-manjunath.goudar@linaro.org>

This patch splits the PCI portion of ohci-hcd out into its
own separate driver module, called ohci-pci.  Consistently with the
current practice, the decision whether to build this module is not
user-configurable.  If OHCI_PCI are enabled then the module will
be built, always.

V2:
  - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
    and rest of the generic code is written in ohci_start of ohci-hcd.c file.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig    |    9 ++-
 drivers/usb/host/Makefile   |    1 +
 drivers/usb/host/ohci-hcd.c |   19 +------
 drivers/usb/host/ohci-pci.c |  129 +++++++++++++------------------------------
 drivers/usb/host/ohci-q.c   |   13 +++++
 5 files changed, 60 insertions(+), 111 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 7a1a248..3620ecce 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -333,8 +333,13 @@ config USB_ISP1362_HCD
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1362-hcd.
 
+config USB_OHCI_PCI
+	tristate
+	depends on USB_OHCI_HCD && PCI
+	default y
+
 config USB_OHCI_HCD
-	tristate "OHCI HCD support"
+	tristate "OHCI HCD (USB 1.1) support"
 	depends on USB && USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	select USB_OTG_UTILS if ARCH_OMAP
@@ -402,7 +407,7 @@ config USB_OHCI_HCD_PPC_OF
 	default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE
 
 config USB_OHCI_HCD_PCI
-	bool "OHCI support for PCI-bus USB controllers"
+	tristate "OHCI support for PCI-bus USB controllers"
 	depends on USB_OHCI_HCD && PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
 	default y
 	select USB_OHCI_LITTLE_ENDIAN
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a38d76b..a20a8d9 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
 
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+obj-$(CONFIG_USB_OHCI_PCI)	+= ohci-pci.o
 
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 7922c61..2e62e7d 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -95,7 +95,6 @@ static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
 #include "ohci-mem.c"
 #include "ohci-q.c"
 
-
 /*
  * On architectures with edge-triggered interrupts we must never return
  * IRQ_NONE.
@@ -585,7 +584,6 @@ int ohci_init(struct ohci_hcd *ohci)
 	return ret;
 }
 EXPORT_SYMBOL_GPL(ohci_init);
-
 /*-------------------------------------------------------------------------*/
 
 /* Start an OHCI controller, set the BUS operational
@@ -1181,11 +1179,6 @@ MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
 
-#ifdef CONFIG_PCI
-#include "ohci-pci.c"
-#define PCI_DRIVER		ohci_pci_driver
-#endif
-
 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
 #include "ohci-sa1111.c"
 #define SA1111_DRIVER		ohci_hcd_sa1111_driver
@@ -1281,7 +1274,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_platform_driver
 #endif
 
-#if	!defined(PCI_DRIVER) &&		\
+#if	!IS_ENABLED(CONFIG_USB_OHCI_PCI) &&	\
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
@@ -1356,12 +1349,6 @@ static int __init ohci_hcd_mod_init(void)
 		goto error_sa1111;
 #endif
 
-#ifdef PCI_DRIVER
-	retval = pci_register_driver(&PCI_DRIVER);
-	if (retval < 0)
-		goto error_pci;
-#endif
-
 #ifdef SM501_OHCI_DRIVER
 	retval = platform_driver_register(&SM501_OHCI_DRIVER);
 	if (retval < 0)
@@ -1455,10 +1442,6 @@ static int __init ohci_hcd_mod_init(void)
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
  error_sm501:
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
- error_pci:
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
  error_sa1111:
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 0b34b59..20f6187 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -14,12 +14,19 @@
  * This file is licenced under the GPL.
  */
 
-#ifndef CONFIG_PCI
-#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
-#endif
-
-#include <linux/pci.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+#include "pci-quirks.h"
+
+#define DRIVER_DESC "OHCI PCI platform driver"
+
+static const char hcd_name[] = "ohci-pci";
 
 
 /*-------------------------------------------------------------------------*/
@@ -175,19 +182,6 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
 	return 0;
 }
 
-static void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	struct pci_dev *pdev;
-	u16 misc;
-
-	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
-	pci_read_config_word(pdev, 0x50, &misc);
-	if (on == 0)
-		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
-	else
-		pci_write_config_word(pdev, 0x50, misc | 0x0300);
-}
-
 /* List of quirks for OHCI */
 static const struct pci_device_id ohci_pci_quirks[] = {
 	{
@@ -261,95 +255,27 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
 			quirk = (void *)quirk_id->driver_data;
 			ret = quirk(hcd);
 		}
-	}
-	if (ret == 0) {
-		ohci_hcd_init (ohci);
-		return ohci_init (ohci);
-	}
-	return ret;
-}
-
-
-static int ohci_pci_start (struct usb_hcd *hcd)
-{
-	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
-	int		ret;
-
 #ifdef CONFIG_PM /* avoid warnings about unused pdev */
-	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
-
 		/* RWC may not be set for add-in PCI cards, since boot
 		 * firmware probably ignored them.  This transfers PCI
 		 * PM wakeup capabilities.
 		 */
 		if (device_can_wakeup(&pdev->dev))
 			ohci->hc_control |= OHCI_CTRL_RWC;
-	}
 #endif /* CONFIG_PM */
-
-	ret = ohci_run(hcd);
-	if (ret < 0) {
-		ohci_err (ohci, "can't start\n");
-		ohci_stop (hcd);
 	}
+	if (ret == 0)
+		return ohci_init(ohci);
 	return ret;
 }
 
+static struct hc_driver __read_mostly ohci_pci_hc_driver;
 
-/*-------------------------------------------------------------------------*/
-
-static const struct hc_driver ohci_pci_hc_driver = {
-	.description =		hcd_name,
-	.product_desc =		"OHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			ohci_irq,
-	.flags =		HCD_MEMORY | HCD_USB11,
-
-	/*
-	 * basic lifecycle operations
-	 */
+static const struct ohci_driver_overrides overrides = {
+	.product_desc =		"OHCI PCI host controller",
 	.reset =		ohci_pci_reset,
-	.start =		ohci_pci_start,
-	.stop =			ohci_stop,
-	.shutdown =		ohci_shutdown,
-
-#ifdef	CONFIG_PM
-	.pci_suspend =		ohci_suspend,
-	.pci_resume =		ohci_resume,
-#endif
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		ohci_urb_enqueue,
-	.urb_dequeue =		ohci_urb_dequeue,
-	.endpoint_disable =	ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data =	ohci_hub_status_data,
-	.hub_control =		ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend =		ohci_bus_suspend,
-	.bus_resume =		ohci_bus_resume,
-#endif
-	.start_port_reset =	ohci_start_port_reset,
 };
 
-/*-------------------------------------------------------------------------*/
-
-
 static const struct pci_device_id pci_ids [] = { {
 	/* handle any USB OHCI controller */
 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
@@ -377,3 +303,24 @@ static struct pci_driver ohci_pci_driver = {
 	},
 #endif
 };
+
+static int __init ohci_pci_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_pci_hc_driver, &overrides);
+	return pci_register_driver(&ohci_pci_driver);
+}
+module_init(ohci_pci_init);
+
+static void __exit ohci_pci_cleanup(void)
+{
+	pci_unregister_driver(&ohci_pci_driver);
+}
+module_exit(ohci_pci_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 88731b7..a7e8139 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -29,6 +29,19 @@ static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
 	kfree (urb_priv);
 }
 
+static void sb800_prefetch(struct ohci_hcd *ohci, int on)
+{
+	struct pci_dev *pdev;
+	u16 misc;
+
+	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
+	pci_read_config_word(pdev, 0x50, &misc);
+	if (on == 0)
+		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
+	else
+		pci_write_config_word(pdev, 0x50, misc | 0x0300);
+}
+
 /*-------------------------------------------------------------------------*/
 
 /*
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Tue May  7 05:50:51 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue,  7 May 2013 15:20:51 +0530
Subject: [RFC PATCH 0/2] USB: OHCI: Start splitting up the driver
In-Reply-To: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1367920253-15207-1-git-send-email-manjunath.goudar@linaro.org>

This series of patches begins the process of splitting ohci-hcd up into
a core library module and independent pci driver modules.

Patch 1/2 prepares the way by exporting a few functions from ohci-hcd
and adding a new mechanism for platform-specific drivers to initialize
their hc_driver structures.  This deserves to be done in the core
because almost all of the entries in these structures are pure
boilerplate -- practically none of the drivers need to override more
than three of the standard core values.

Patch 2/2  separate out ohci-pci into independent driver modules.

Manjunath Goudar (2):
  USB: OHCI: prepare to make ohci-hcd a library module
  USB: OHCI: make ohci-pci a separate driver

 drivers/usb/host/Kconfig         |    9 ++-
 drivers/usb/host/Makefile        |    3 +
 drivers/usb/host/ohci-hcd.c      |  142 +++++++++++++++++++++++++++++---------
 drivers/usb/host/ohci-pci.c      |  129 ++++++++++------------------------
 drivers/usb/host/ohci-platform.c |    2 +-
 drivers/usb/host/ohci-q.c        |   13 ++++
 drivers/usb/host/ohci.h          |   30 +++++++-
 7 files changed, 197 insertions(+), 131 deletions(-)

-- 
1.7.9.5



From t.figa at samsung.com  Tue May  7 05:50:51 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 07 May 2013 11:50:51 +0200
Subject: [PATCH] ASoC: Samsung: i2s: Fix crash in i2s driver
In-Reply-To: <1367897941-18439-1-git-send-email-padma.v@samsung.com>
References: <1367897941-18439-1-git-send-email-padma.v@samsung.com>
Message-ID: <2286960.PxJxnETVLS@amdc1227>

Hi Padmavathi,

On Tuesday 07 of May 2013 09:09:01 Padmavathi Venna wrote:
> This patch fixes a null pointer deference in i2s driver in DT
> case
> 
> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
> ---
> 
> This patch is dependent on below patch posted by Thomas Abraham.
> https://patchwork.kernel.org/patch/2224801/
> 
>  sound/soc/samsung/i2s.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
> index 7ce7c50..eaf6439 100644
> --- a/sound/soc/samsung/i2s.c
> +++ b/sound/soc/samsung/i2s.c
> @@ -1182,7 +1182,7 @@ static int samsung_i2s_probe(struct platform_device
> *pdev) pri_dai->sec_dai = sec_dai;
>  	}
> 
> -	if (i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
> +	if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {

This is a problem that needs to be fixed indeed. However the same problem 
exists in samsung_i2s_remove() as well (at least in latest linux-next).

This makes me wonder what happens with i2s_pdata in DT case. Most of drivers 
allocate a pdata struct anyway and fill it with data parsed from device tree. 
This allows rest of the code to remain unmodified and consider DT and non-DT 
cases equal.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Kernel and System Framework



From manjunath.goudar at linaro.org  Tue May  7 05:50:52 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue,  7 May 2013 15:20:52 +0530
Subject: [RFC PATCH 1/2] USB: OHCI: prepare to make ohci-hcd a library module
In-Reply-To: <1367920253-15207-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1367920253-15207-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1367920253-15207-2-git-send-email-manjunath.goudar@linaro.org>

This patch prepares ohci-hcd for being split up into a core
library and separate platform driver modules.  A generic
ohci_hc_driver structure is created, containing all the "standard"
values, and a new mechanism is added whereby a driver module can
specify a set of overrides to those values.  In addition the
ohci_restart(),ohci_suspend() and ohci_resume() routines need
to be EXPORTed for use by the drivers.

In V2:
-ohci_hcd_init(), ohci_run() and ohci_stop revert back to static routine.
-ohci_setup() and ohci_start() functions written to generic OHCI initialization
 for all ohci bus glue.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Makefile        |    2 +
 drivers/usb/host/ohci-hcd.c      |  123 +++++++++++++++++++++++++++++++++-----
 drivers/usb/host/ohci-pci.c      |    2 +-
 drivers/usb/host/ohci-platform.c |    2 +-
 drivers/usb/host/ohci.h          |   30 +++++++++-
 5 files changed, 138 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 58c14c1..a38d76b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -40,7 +40,9 @@ obj-$(CONFIG_USB_EHCI_TEGRA)    +=ehci-tegra.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
+
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9e6de95..7922c61 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -79,13 +79,7 @@ static const char	hcd_name [] = "ohci_hcd";
 #include "pci-quirks.h"
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
-static int ohci_init (struct ohci_hcd *ohci);
-static void ohci_stop (struct usb_hcd *hcd);
-
-#if defined(CONFIG_PM) || defined(CONFIG_PCI)
-static int ohci_restart (struct ohci_hcd *ohci);
-#endif
-
+static void ohci_stop(struct usb_hcd *hcd);
 #ifdef CONFIG_PCI
 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
 #else
@@ -520,7 +514,7 @@ done:
 
 /* init memory, and kick BIOS/SMM off */
 
-static int ohci_init (struct ohci_hcd *ohci)
+int ohci_init(struct ohci_hcd *ohci)
 {
 	int ret;
 	struct usb_hcd *hcd = ohci_to_hcd(ohci);
@@ -590,6 +584,7 @@ static int ohci_init (struct ohci_hcd *ohci)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(ohci_init);
 
 /*-------------------------------------------------------------------------*/
 
@@ -597,11 +592,11 @@ static int ohci_init (struct ohci_hcd *ohci)
  * resets USB and controller
  * enable interrupts
  */
-static int ohci_run (struct ohci_hcd *ohci)
+static int ohci_run(struct usb_hcd *hcd)
 {
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	u32			mask, val;
 	int			first = ohci->fminterval == 0;
-	struct usb_hcd		*hcd = ohci_to_hcd(ohci);
 
 	ohci->rh_state = OHCI_RH_HALTED;
 
@@ -767,7 +762,37 @@ retry:
 
 	return 0;
 }
+/*------------------------------------------------------------------------*/
+
+/* ohci generic function for all OHCI bus glue */
+
+static int ohci_setup(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int retval;
+
+	ohci->sbrn = HCD_USB11;
+
+	/* data structure init */
+	retval = ohci_init(ohci);
+	if (retval)
+		return retval;
+	ohci_usb_reset(ohci);
+	return 0;
+}
 
+static int ohci_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int	ret;
+	ret = ohci_run(hcd);
+	if (ret < 0) {
+		ohci_err(ohci, "can't start\n");
+		ohci_stop(hcd);
+	}
+	return ret;
+}
+/*-------------------------------------------------------------------------*/
 /*-------------------------------------------------------------------------*/
 
 /* an interrupt happens */
@@ -949,11 +974,12 @@ static void ohci_stop (struct usb_hcd *hcd)
 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 
 /* must not be called from interrupt context */
-static int ohci_restart (struct ohci_hcd *ohci)
+int ohci_restart(struct ohci_hcd *ohci)
 {
 	int temp;
 	int i;
 	struct urb_priv *priv;
+	struct usb_hcd	*hcd;
 
 	spin_lock_irq(&ohci->lock);
 	ohci->rh_state = OHCI_RH_HALTED;
@@ -1001,19 +1027,22 @@ static int ohci_restart (struct ohci_hcd *ohci)
 	ohci->ed_controltail = NULL;
 	ohci->ed_bulktail    = NULL;
 
-	if ((temp = ohci_run (ohci)) < 0) {
-		ohci_err (ohci, "can't restart, %d\n", temp);
+	hcd = ohci_to_hcd(ohci);
+	temp = ohci_run(hcd);
+	if (temp < 0) {
+		ohci_err(ohci, "can't restart, %d\n", temp);
 		return temp;
 	}
 	ohci_dbg(ohci, "restart complete\n");
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_restart);
 
 #endif
 
 #ifdef CONFIG_PM
 
-static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
 	unsigned long	flags;
@@ -1031,9 +1060,9 @@ static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_suspend);
 
-
-static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
+int ohci_resume(struct usb_hcd *hcd, bool hibernated)
 {
 	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	int			port;
@@ -1081,11 +1110,73 @@ static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_resume);
 
 #endif
 
 /*-------------------------------------------------------------------------*/
 
+/*
+ * Generic structure: This gets copied for platform drivers so that
+ * individual entries can be overridden as needed.
+ */
+
+static const struct hc_driver ohci_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "OHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	*/
+	.irq =                  ohci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/*
+	* basic lifecycle operations
+	*/
+	.reset =		ohci_setup,
+	.start =                ohci_start,
+	.stop =                 ohci_stop,
+	.shutdown =             ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	*/
+	.urb_enqueue =          ohci_urb_enqueue,
+	.urb_dequeue =          ohci_urb_dequeue,
+	.endpoint_disable =     ohci_endpoint_disable,
+
+	/*
+	* scheduling support
+	*/
+	.get_frame_number =     ohci_get_frame,
+
+	/*
+	* root hub support
+	*/
+	.hub_status_data =      ohci_hub_status_data,
+	.hub_control =          ohci_hub_control,
+	.bus_suspend =          ohci_bus_suspend,
+	.bus_resume =           ohci_bus_resume,
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+void ohci_init_driver(struct hc_driver *drv,
+		const struct ohci_driver_overrides *over)
+{
+	/* Copy the generic table to drv and then apply the overrides */
+	*drv = ohci_hc_driver;
+
+	drv->product_desc = over->product_desc;
+	drv->hcd_priv_size += over->extra_priv_size;
+	if (over->reset)
+		drv->reset = over->reset;
+}
+EXPORT_SYMBOL_GPL(ohci_init_driver);
+
+/*-------------------------------------------------------------------------*/
+
 MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 951514e..0b34b59 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -288,7 +288,7 @@ static int ohci_pci_start (struct usb_hcd *hcd)
 	}
 #endif /* CONFIG_PM */
 
-	ret = ohci_run (ohci);
+	ret = ohci_run(hcd);
 	if (ret < 0) {
 		ohci_err (ohci, "can't start\n");
 		ohci_stop (hcd);
diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
index c3e7287..545c657 100644
--- a/drivers/usb/host/ohci-platform.c
+++ b/drivers/usb/host/ohci-platform.c
@@ -46,7 +46,7 @@ static int ohci_platform_start(struct usb_hcd *hcd)
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 	int err;
 
-	err = ohci_run(ohci);
+	err = ohci_run(hcd);
 	if (err < 0) {
 		ohci_err(ohci, "can't start\n");
 		ohci_stop(hcd);
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index d329914..455e9b1 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -357,7 +357,6 @@ struct ohci_hcd {
 	 * I/O memory used to communicate with the HC (dma-consistent)
 	 */
 	struct ohci_regs __iomem *regs;
-
 	/*
 	 * main memory used to communicate with the HC (dma-consistent).
 	 * hcd adds to schedule for a live hc any time, but removals finish
@@ -373,7 +372,6 @@ struct ohci_hcd {
 	struct ed		*periodic [NUM_INTS];	/* shadow int_table */
 
 	void (*start_hnp)(struct ohci_hcd *ohci);
-
 	/*
 	 * memory management for queue data structures
 	 */
@@ -392,7 +390,7 @@ struct ohci_hcd {
 	unsigned long		next_statechange;	/* suspend/resume */
 	u32			fminterval;		/* saved register */
 	unsigned		autostop:1;	/* rh auto stopping/stopped */
-
+	u8			sbrn;
 	unsigned long		flags;		/* for HC bugs */
 #define	OHCI_QUIRK_AMD756	0x01			/* erratum #4 */
 #define	OHCI_QUIRK_SUPERIO	0x02			/* natsemi */
@@ -718,3 +716,29 @@ static inline u32 roothub_status (struct ohci_hcd *hc)
 	{ return ohci_readl (hc, &hc->regs->roothub.status); }
 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+/* Declarations of things exported for use by ohci platform drivers */
+
+struct ohci_driver_overrides {
+	const char	*product_desc;
+	size_t		extra_priv_size;
+	int		(*reset)(struct usb_hcd *hcd);
+};
+
+extern void	ohci_init_driver(struct hc_driver *drv,
+				const struct ohci_driver_overrides *over);
+extern int	ohci_init(struct ohci_hcd *ohci);
+extern int	ohci_restart(struct ohci_hcd *ohci);
+#ifdef CONFIG_PM
+extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
+extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
+#else
+static inline int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+{
+	return 0;
+}
+static inline int ohci_resume(struct usb_hcd *hcd, bool hibernated)
+{
+	return 0;
+}
+#endif
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Tue May  7 05:50:53 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue,  7 May 2013 15:20:53 +0530
Subject: [RFC PATCH 2/2] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1367920253-15207-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1367920253-15207-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1367920253-15207-3-git-send-email-manjunath.goudar@linaro.org>

This patch splits the PCI portion of ohci-hcd out into its
own separate driver module, called ohci-pci.  Consistently with the
current practice, the decision whether to build this module is not
user-configurable.  If OHCI_PCI are enabled then the module will
be built, always.

V2:
  - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
    and rest of the generic code is written in ohci_start of ohci-hcd.c file.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig    |    9 ++-
 drivers/usb/host/Makefile   |    1 +
 drivers/usb/host/ohci-hcd.c |   19 +------
 drivers/usb/host/ohci-pci.c |  129 +++++++++++++------------------------------
 drivers/usb/host/ohci-q.c   |   13 +++++
 5 files changed, 60 insertions(+), 111 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 7a1a248..3620ecce 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -333,8 +333,13 @@ config USB_ISP1362_HCD
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1362-hcd.
 
+config USB_OHCI_PCI
+	tristate
+	depends on USB_OHCI_HCD && PCI
+	default y
+
 config USB_OHCI_HCD
-	tristate "OHCI HCD support"
+	tristate "OHCI HCD (USB 1.1) support"
 	depends on USB && USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	select USB_OTG_UTILS if ARCH_OMAP
@@ -402,7 +407,7 @@ config USB_OHCI_HCD_PPC_OF
 	default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE
 
 config USB_OHCI_HCD_PCI
-	bool "OHCI support for PCI-bus USB controllers"
+	tristate "OHCI support for PCI-bus USB controllers"
 	depends on USB_OHCI_HCD && PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
 	default y
 	select USB_OHCI_LITTLE_ENDIAN
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a38d76b..a20a8d9 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
 
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+obj-$(CONFIG_USB_OHCI_PCI)	+= ohci-pci.o
 
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 7922c61..2e62e7d 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -95,7 +95,6 @@ static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
 #include "ohci-mem.c"
 #include "ohci-q.c"
 
-
 /*
  * On architectures with edge-triggered interrupts we must never return
  * IRQ_NONE.
@@ -585,7 +584,6 @@ int ohci_init(struct ohci_hcd *ohci)
 	return ret;
 }
 EXPORT_SYMBOL_GPL(ohci_init);
-
 /*-------------------------------------------------------------------------*/
 
 /* Start an OHCI controller, set the BUS operational
@@ -1181,11 +1179,6 @@ MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
 
-#ifdef CONFIG_PCI
-#include "ohci-pci.c"
-#define PCI_DRIVER		ohci_pci_driver
-#endif
-
 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
 #include "ohci-sa1111.c"
 #define SA1111_DRIVER		ohci_hcd_sa1111_driver
@@ -1281,7 +1274,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_platform_driver
 #endif
 
-#if	!defined(PCI_DRIVER) &&		\
+#if	!IS_ENABLED(CONFIG_USB_OHCI_PCI) &&	\
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
@@ -1356,12 +1349,6 @@ static int __init ohci_hcd_mod_init(void)
 		goto error_sa1111;
 #endif
 
-#ifdef PCI_DRIVER
-	retval = pci_register_driver(&PCI_DRIVER);
-	if (retval < 0)
-		goto error_pci;
-#endif
-
 #ifdef SM501_OHCI_DRIVER
 	retval = platform_driver_register(&SM501_OHCI_DRIVER);
 	if (retval < 0)
@@ -1455,10 +1442,6 @@ static int __init ohci_hcd_mod_init(void)
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
  error_sm501:
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
- error_pci:
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
  error_sa1111:
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 0b34b59..20f6187 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -14,12 +14,19 @@
  * This file is licenced under the GPL.
  */
 
-#ifndef CONFIG_PCI
-#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
-#endif
-
-#include <linux/pci.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+#include "pci-quirks.h"
+
+#define DRIVER_DESC "OHCI PCI platform driver"
+
+static const char hcd_name[] = "ohci-pci";
 
 
 /*-------------------------------------------------------------------------*/
@@ -175,19 +182,6 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
 	return 0;
 }
 
-static void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	struct pci_dev *pdev;
-	u16 misc;
-
-	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
-	pci_read_config_word(pdev, 0x50, &misc);
-	if (on == 0)
-		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
-	else
-		pci_write_config_word(pdev, 0x50, misc | 0x0300);
-}
-
 /* List of quirks for OHCI */
 static const struct pci_device_id ohci_pci_quirks[] = {
 	{
@@ -261,95 +255,27 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
 			quirk = (void *)quirk_id->driver_data;
 			ret = quirk(hcd);
 		}
-	}
-	if (ret == 0) {
-		ohci_hcd_init (ohci);
-		return ohci_init (ohci);
-	}
-	return ret;
-}
-
-
-static int ohci_pci_start (struct usb_hcd *hcd)
-{
-	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
-	int		ret;
-
 #ifdef CONFIG_PM /* avoid warnings about unused pdev */
-	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
-
 		/* RWC may not be set for add-in PCI cards, since boot
 		 * firmware probably ignored them.  This transfers PCI
 		 * PM wakeup capabilities.
 		 */
 		if (device_can_wakeup(&pdev->dev))
 			ohci->hc_control |= OHCI_CTRL_RWC;
-	}
 #endif /* CONFIG_PM */
-
-	ret = ohci_run(hcd);
-	if (ret < 0) {
-		ohci_err (ohci, "can't start\n");
-		ohci_stop (hcd);
 	}
+	if (ret == 0)
+		return ohci_init(ohci);
 	return ret;
 }
 
+static struct hc_driver __read_mostly ohci_pci_hc_driver;
 
-/*-------------------------------------------------------------------------*/
-
-static const struct hc_driver ohci_pci_hc_driver = {
-	.description =		hcd_name,
-	.product_desc =		"OHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			ohci_irq,
-	.flags =		HCD_MEMORY | HCD_USB11,
-
-	/*
-	 * basic lifecycle operations
-	 */
+static const struct ohci_driver_overrides overrides = {
+	.product_desc =		"OHCI PCI host controller",
 	.reset =		ohci_pci_reset,
-	.start =		ohci_pci_start,
-	.stop =			ohci_stop,
-	.shutdown =		ohci_shutdown,
-
-#ifdef	CONFIG_PM
-	.pci_suspend =		ohci_suspend,
-	.pci_resume =		ohci_resume,
-#endif
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		ohci_urb_enqueue,
-	.urb_dequeue =		ohci_urb_dequeue,
-	.endpoint_disable =	ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data =	ohci_hub_status_data,
-	.hub_control =		ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend =		ohci_bus_suspend,
-	.bus_resume =		ohci_bus_resume,
-#endif
-	.start_port_reset =	ohci_start_port_reset,
 };
 
-/*-------------------------------------------------------------------------*/
-
-
 static const struct pci_device_id pci_ids [] = { {
 	/* handle any USB OHCI controller */
 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
@@ -377,3 +303,24 @@ static struct pci_driver ohci_pci_driver = {
 	},
 #endif
 };
+
+static int __init ohci_pci_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_pci_hc_driver, &overrides);
+	return pci_register_driver(&ohci_pci_driver);
+}
+module_init(ohci_pci_init);
+
+static void __exit ohci_pci_cleanup(void)
+{
+	pci_unregister_driver(&ohci_pci_driver);
+}
+module_exit(ohci_pci_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 88731b7..a7e8139 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -29,6 +29,19 @@ static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
 	kfree (urb_priv);
 }
 
+static void sb800_prefetch(struct ohci_hcd *ohci, int on)
+{
+	struct pci_dev *pdev;
+	u16 misc;
+
+	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
+	pci_read_config_word(pdev, 0x50, &misc);
+	if (on == 0)
+		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
+	else
+		pci_write_config_word(pdev, 0x50, misc | 0x0300);
+}
+
 /*-------------------------------------------------------------------------*/
 
 /*
-- 
1.7.9.5



From holt at sgi.com  Tue May  7 05:51:45 2013
From: holt at sgi.com (Robin Holt)
Date: Tue, 7 May 2013 04:51:45 -0500
Subject: How does commit 47ec340c not introduce a bug?
In-Reply-To: <CAN1soZyHx1XZzukunbKsj+v4h93MRQKjPPjJ3+i3u8BeBbhCGw@mail.gmail.com>
References: <20130507091734.GM3658@sgi.com>
 <20130507092428.GK23285@pengutronix.de>
 <CAN1soZyHx1XZzukunbKsj+v4h93MRQKjPPjJ3+i3u8BeBbhCGw@mail.gmail.com>
Message-ID: <20130507095145.GN3658@sgi.com>

On Tue, May 07, 2013 at 05:35:28PM +0800, Haojian Zhuang wrote:
> On Tue, May 7, 2013 at 5:24 PM, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
> > Hello,
> >
> > On Tue, May 07, 2013 at 04:17:34AM -0500, Robin Holt wrote:
> >> I noticed a warning while cross-compiling all arm defconfigs.
> >>
> >> The mmp2_defconfig gave this warning:
> >>
> >> drivers/video/backlight/max8925_bl.c: In function 'max8925_backlight_probe':
> >> drivers/video/backlight/max8925_bl.c:177:3: warning: statement with no effect [-Wunused-value]
> >>
> >> This appears to have been introduced by the above commit when !CONFIG_OF
> >>
> >> Looking at this more closely, I am not sure how this was ever intended
> >> to be handled or how the errors returned in the CONFIG_OF case were
> >> intended to be handled as the return from max8925_backlight_dt_init is
> >> always ignored.
> >>
> >> I think this needs some more attention, but do not feel like I know
> >> enough about it or have any means to test it to weigh in.
> >>
> >> Thanks,
> >> Robin
> >>
> >>
> >> commit 47ec340cb8e232671e7c4a4689ff32c3bdf329da
> >> Author: Qing Xu <qingx at marvell.com>
> >> Date:   Mon Feb 4 23:40:45 2013 +0800
> >>
> >>     mfd: max8925: Support dt for backlight
> >>
> >>     Add device tree support in max8925 backlight.
> >>
> >>     Signed-off-by: Qing Xu <qingx at marvell.com>
> >>     Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
> >>     Signed-off-by: Samuel Ortiz <sameo at linux.intel.com>
> >>
> >> diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c
> >> index 2c9bce0..5ca11b0 100644
> >> --- a/drivers/video/backlight/max8925_bl.c
> >> +++ b/drivers/video/backlight/max8925_bl.c
> >> @@ -101,6 +101,29 @@ static const struct backlight_ops max8925_backlight_ops = {
> >>       .get_brightness = max8925_backlight_get_brightness,
> >>  };
> >>
> >> +#ifdef CONFIG_OF
> >> +static int max8925_backlight_dt_init(struct platform_device *pdev,
> >> +                           struct max8925_backlight_pdata *pdata)
> >> +{
> >> +     struct device_node *nproot = pdev->dev.parent->of_node, *np;
> >> +     int dual_string;
> >> +
> >> +     if (!nproot)
> >> +             return -ENODEV;
> >> +     np = of_find_node_by_name(nproot, "backlight");
> >> +     if (!np) {
> >> +             dev_err(&pdev->dev, "failed to find backlight node\n");
> >> +             return -ENODEV;
> >> +     }
> >> +
> >> +     of_property_read_u32(np, "maxim,max8925-dual-string", &dual_string);
> >> +     pdata->dual_string = dual_string;
> >> +     return 0;
> >> +}
> >> +#else
> >> +#define max8925_backlight_dt_init(x, y)      (-1)
> > It's probably best to make this:
> >
> > static inline max8925_backlight_dt_init(struct platform_device *pdev,
> >                                 struct max8925_backlight_pdata *pdata)
> > {
> >         return -ENODEV;
> > }
> >
> 
> I've submitted this patch to fix this issue for a long time.
> 
> Samuel,
> 
> Should I send it again?

It fixes nothing.  The return value is not used.  There is more to this
bug report than the -1.  You need to handle that error case.  Otherwise,
you could just change it into a void return.

Robin


From will.deacon at arm.com  Tue May  7 05:52:17 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 May 2013 10:52:17 +0100
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130507093508.GL23285@pengutronix.de>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
 <20130507092209.GD25387@mudshark.cambridge.arm.com>
 <20130507093508.GL23285@pengutronix.de>
Message-ID: <20130507095217.GG25387@mudshark.cambridge.arm.com>

On Tue, May 07, 2013 at 10:35:08AM +0100, Uwe Kleine-K?nig wrote:
> Hello Will,

Hello,

> On Tue, May 07, 2013 at 10:22:09AM +0100, Will Deacon wrote:
> > On Mon, May 06, 2013 at 10:30:59AM +0100, Uwe Kleine-K?nig wrote:
> > > +#elif defined(CONFIG_CPU_V7M)
> > > +
> > > +#include <asm/io.h>
> > > +#include <asm/v7m.h>
> > > +
> > > +#define read_cpuid(reg)							\
> > > +	({								\
> > > +		WARN_ON_ONCE(1);					\
> > > +		0;							\
> > > +	})
> > 
> > We do have an MIDR in PMSAv7 (not to be confused with MPIDR), so why not read
> > that here?
> I don't know it and it's unrelated to this patch. But I will note it and
> check it. In the meantime I'm taking patches of course :-)

I don't think it is unrelated to this patch: I'm suggesting that you add an
MIDR read to read_cpuid, instead of the unconditional WARN_ON_ONCE which
you're adding here.

Then you can remove your v7m-specific read_cpuid_id implementation, because
read_cpuid(CPUID_ID) will do the right thing.

...or am I missing something?

Will


From sameo at linux.intel.com  Tue May  7 05:52:38 2013
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Tue, 7 May 2013 11:52:38 +0200
Subject: How does commit 47ec340c not introduce a bug?
In-Reply-To: <CAN1soZyHx1XZzukunbKsj+v4h93MRQKjPPjJ3+i3u8BeBbhCGw@mail.gmail.com>
References: <20130507091734.GM3658@sgi.com>
 <20130507092428.GK23285@pengutronix.de>
 <CAN1soZyHx1XZzukunbKsj+v4h93MRQKjPPjJ3+i3u8BeBbhCGw@mail.gmail.com>
Message-ID: <20130507095238.GA4387@zurbaran>

On Tue, May 07, 2013 at 05:35:28PM +0800, Haojian Zhuang wrote:
> > It's probably best to make this:
> >
> > static inline max8925_backlight_dt_init(struct platform_device *pdev,
> >                                 struct max8925_backlight_pdata *pdata)
> > {
> >         return -ENODEV;
> > }
> >
> 
> I've submitted this patch to fix this issue for a long time.
> 
> Samuel,
> 
> Should I send it again?
To the backlight maintainers, yes. I carried 47ec340c as it was part of an MFD
patchset, but now that it's upstream I shouldn't take any patches for it.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From lee.jones at linaro.org  Tue May  7 05:53:18 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 7 May 2013 10:53:18 +0100
Subject: [PATCH 54/63] ARM: ux500: Replace ST-E's home-brew DMA direction
 definition with the generic one
In-Reply-To: <20130507094205.GA32548@bnru10>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-55-git-send-email-lee.jones@linaro.org>
 <20130506071355.GA5552@bnru10> <20130507073921.GT24153@gmail.com>
 <20130507094205.GA32548@bnru10>
Message-ID: <20130507095318.GE3102@gmail.com>

On Tue, 07 May 2013, Srinidhi Kasagar wrote:

> On Tue, May 07, 2013 at 09:39:21 +0200, Lee Jones wrote:
> > On Mon, 06 May 2013, Srinidhi Kasagar wrote:
> > 
> > > On Fri, May 03, 2013 at 16:32:40 +0200, Lee Jones wrote:
> > > > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > > > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > > > duplicating such things.
> > > > 
> > > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > > > ---
> > > >  arch/arm/mach-ux500/board-mop500-audio.c |   12 ++++++------
> > > >  arch/arm/mach-ux500/board-mop500-sdi.c   |   16 ++++++++--------
> > > >  arch/arm/mach-ux500/board-mop500.c       |   22 +++++++++++-----------
> > > >  arch/arm/mach-ux500/usb.c                |    4 ++--
> > > >  4 files changed, 27 insertions(+), 27 deletions(-)
> > > 
> > > Hope you have taken care for all other files, because, I see
> > > few more instances in my tree apart from the above files.
> > 
> > Would you be kind enough to paste those files please?
> 
> arch/arm/mach-ux500/board-mop500-audio.c:       .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500-audio.c:       .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500-audio.c:       .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500-sdi.c: .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500.c:                             .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500.c:             .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/board-mop500.c:     .dir = STEDMA40_MEM_TO_PERIPH,
> arch/arm/mach-ux500/devices-db8500.c:   .dir = STEDMA40_MEM_TO_MEM,
> arch/arm/mach-ux500/devices-db8500.c:   .dir = STEDMA40_MEM_TO_MEM,
> arch/arm/mach-ux500/usb.c:              .dir = STEDMA40_MEM_TO_PERIPH, \

Yes, all those are dealt with.

Thanks Srinidhi.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From t.figa at samsung.com  Tue May  7 05:54:20 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 07 May 2013 11:54:20 +0200
Subject: [PATCH V2 2/3] ARM: dts: add Exynos audio subsystem clock
 controller node
In-Reply-To: <1367909016-19657-3-git-send-email-padma.v@samsung.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
 <1367909016-19657-3-git-send-email-padma.v@samsung.com>
Message-ID: <2829319.bZPJnVErnQ@amdc1227>

Hi Padmavathi,

On Tuesday 07 of May 2013 12:13:35 Padmavathi Venna wrote:
> Audio subsystem introduced in s5pv210 and exynos platforms
> which has a internal clock controller. This patch adds a node
> for the same on exynos5250.
> 
> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi index 36c9d8d..7026de0 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -72,6 +72,12 @@
>  		#clock-cells = <1>;
>  	};
> 
> +	clock_audss: audss-clock-controller at 0x03810000 {

Just a nitpick: this should be @3810000, without the 0x and leading zeroes.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Kernel and System Framework

> +		compatible = "samsung,exynos5250-audss-clock";
> +		reg = <0x03810000 0x0C>;
> +		#clock-cells = <1>;
> +	};
> +
>  	gic:interrupt-controller at 10481000 {
>  		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>  		#interrupt-cells = <3>;



From sebastian.hesselbarth at gmail.com  Tue May  7 06:03:32 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 07 May 2013 12:03:32 +0200
Subject: [PATCH 1/2] clk: si5351: Fix msynth_recalc_rate return value
 when fOUT is 0.
In-Reply-To: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
References: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <5188D174.90400@gmail.com>

On 05/07/2013 10:14 AM, Marek Belisko wrote:
> When p3 is eual to 0 then result for fOUT is 0. In that case we should
> return 0 not parent_rate;
>
> This issue was causing deadlock in si5351 chip when user set_rate for
> ms0->clk0 and then set_rate for ms1->clk1 (both ms sourced from plla).
> After that clk1 was 0 and it wasn't possible to enable it again (try also
> manually with i2cset commands). Only power cycle helps.

Marek,

does the fix below also affect the behavior above, i.e. not causing
si5351 to hang?

Anyway, your fix looks very sane to me and you get my

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>

> Signed-off-by: Marek Belisko<marek.belisko at streamunlimited.com>
> ---
>   drivers/clk/clk-si5351.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index fc215ce..a8fc0f4 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -607,7 +607,7 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
>   		si5351_read_parameters(hwdata->drvdata, reg,&hwdata->params);
>
>   	if (hwdata->params.p3 == 0)
> -		return parent_rate;
> +		return 0;
>
>   	/*
>   	 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)



From sebastian.hesselbarth at gmail.com  Tue May  7 06:07:39 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 07 May 2013 12:07:39 +0200
Subject: [PATCH 2/2] clk: si5351: Powerdown output when clock rate is
 0.
In-Reply-To: <1367914491-17445-2-git-send-email-marek.belisko@streamunlimited.com>
References: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
 <1367914491-17445-2-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <5188D26B.6020000@gmail.com>

On 05/07/2013 10:14 AM, Marek Belisko wrote:
> When rate is 0 powerdown clock output.
>
> Signed-off-by: Marek Belisko<marek.belisko at streamunlimited.com>
> ---
>   drivers/clk/clk-si5351.c |   32 +++++++++++++++++++-------------
>   1 file changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index a8fc0f4..e254e76 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -1042,20 +1042,22 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
>   	struct si5351_hw_data *hwdata =
>   		container_of(hw, struct si5351_hw_data, hw);
>   	unsigned long new_rate, new_err, err;
> -	unsigned char rdiv;
> +	unsigned char rdiv, pdn = 0;
>
>   	/* round to closed rdiv */
>   	rdiv = SI5351_OUTPUT_CLK_DIV_1;
> -	new_rate = parent_rate;
> -	err = abs(new_rate - rate);
> -	do {
> -		new_rate>>= 1;
> -		new_err = abs(new_rate - rate);
> -		if (new_err>  err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
> -			break;
> -		rdiv++;
> -		err = new_err;
> -	} while (1);
> +	if (rate) {
> +		new_rate = parent_rate;

Marek,

initalizing pdn to SI5351_CLK_POWERDOWN and skip (with goto) to 
powerup/down call on zero rate will save us a level of indention here.

> +		err = abs(new_rate - rate);
> +		do {
> +			new_rate>>= 1;
> +			new_err = abs(new_rate - rate);
> +			if (new_err>  err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
> +				break;
> +			rdiv++;
> +			err = new_err;
> +		} while (1);

of course, pdn should be set to 0 here.

> +	}
>
>   	/* write output divider */
>   	switch (hwdata->num) {
> @@ -1075,9 +1077,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
>   				rdiv<<  SI5351_OUTPUT_CLK_DIV_SHIFT);
>   	}
>
> -	/* powerup clkout */
> +	/* when rate is 0 powerdown output */
> +	if (rate == 0)
> +		pdn = SI5351_CLK_POWERDOWN;
> +
> +	/* powerup/down clkout */
>   	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
> -			SI5351_CLK_POWERDOWN, 0);
> +			SI5351_CLK_POWERDOWN, pdn);
>
>   	dev_dbg(&hwdata->drvdata->client->dev,
>   		"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",



From jonathan.austin at arm.com  Tue May  7 06:16:56 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 07 May 2013 11:16:56 +0100
Subject: [PATCHv2] arm: Preserve TPIDRURW on context switch
In-Reply-To: <51882E6A.6070302@dawncrow.de>
References: <517168BB.3070903@dawncrow.de>
 <20130422143616.GP14496@n2100.arm.linux.org.uk>
 <20130422151836.GA15665@mudshark.cambridge.arm.com>
 <5175A697.3080308@dawncrow.de>
 <20130423091536.GB17593@mudshark.cambridge.arm.com>
 <51770E4E.2040003@dawncrow.de>
 <20130424094251.GA21850@mudshark.cambridge.arm.com>
 <5182C480.3080001@dawncrow.de> <5183819E.50308@arm.com>
 <20130503095547.GD18614@n2100.arm.linux.org.uk> <5183D6C3.8090402@arm.com>
 <51882E6A.6070302@dawncrow.de>
Message-ID: <5188D498.9010203@arm.com>

Hi Andr?,

On 06/05/13 23:27, Andr? Hentschel wrote:
> Am 03.05.2013 17:24, schrieb Jonathan Austin:
>>> -	.macro set_tls_none, tp, tmp1, tmp2
>>> +	.macro switch_tls_none, base, tp, trw, tmp1, tmp2
>>>    	.endm
>>>
>>> -	.macro set_tls_v6k, tp, tmp1, tmp2
>>> +	.macro switch_tls_v6k, base, tp, trw, tmp1, tmp2
>>
>> How do you feel about calling tp and trw something different? tpidro
>> and tpidrw, or tp and tpuser?
>>
>> The naming threw me off slightly first time I read this new signature
>> (tp=thread_pointer/tls_pointer/etc).
>>
>
> FWIW i think tp&tpuser is more consistent.
>
>> Andr?, Assuming I've understood things okay, there's a patch that
>> uses Russell's asm stuff (with minor modifications, see the questions)
>> and includes the C-world changes too. Perhaps you could see that it
>> solves your problem?
>
> It works, but for various reasons i would like to suggest the patch below.
> Reasons include: My thoughts about tp&tpuser naming and the helper function for copy_thread, further i'd really like to get a bit credit for spending weeks on getting my second kernel patch in :)
> If that patch is fine for you and no one object, i'd be happy to test it, adapt the commit message and include:
> 	Reported-by: Andr? Hentschel <nerv at dawncrow.de>
> 	Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
> 	Signed-off-by: Will Deacon <will.deacon at arm.com>
> 	Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> 	Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>

I'm not worried about authorship, so you're welcome to be the author on 
the patch - assuming Russell's happy with that and with the change of 
register naming in your patch below.

As this will go through Russell's tree (probably via has patch system), 
you don't need his Signed-off-by - It'll get added as he takes the 
patch. As you're signing off, too, you don't need to list yourself as 
reporting the problem.

It'll look a bit weird to have 3 people signing off on quite a little 
patch (4 once it goes through Russell's tree) so it's best to make some 
notes in the commit message about the way this patch was written (IE 
many authors)

Hope that helps,
Jonny
>
> Not totally sure about the Signed-off-bys. Can i add a Signed-off-by for Russell King? Is it the right mail address for him/you?
>
>
>
>
> diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
> index cddda1f..d90be6d 100644
> --- a/arch/arm/include/asm/thread_info.h
> +++ b/arch/arm/include/asm/thread_info.h
> @@ -58,7 +58,7 @@ struct thread_info {
>   	struct cpu_context_save	cpu_context;	/* cpu context */
>   	__u32			syscall;	/* syscall number */
>   	__u8			used_cp[16];	/* thread used copro */
> -	unsigned long		tp_value;
> +	unsigned long		tp_value[2];	/* TLS registers */
>   #ifdef CONFIG_CRUNCH
>   	struct crunch_state	crunchstate;
>   #endif
> diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
> index 73409e6..d7d542b 100644
> --- a/arch/arm/include/asm/tls.h
> +++ b/arch/arm/include/asm/tls.h
> @@ -2,27 +2,30 @@
>   #define __ASMARM_TLS_H
>
>   #ifdef __ASSEMBLY__
> -	.macro set_tls_none, tp, tmp1, tmp2
> +#include <asm/asm-offsets.h>
> +	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
>   	.endm
>
> -	.macro set_tls_v6k, tp, tmp1, tmp2
> +	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
> +	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
>   	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
> -	mov	\tmp1, #0
> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> +	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
> +	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
>   	.endm
>
> -	.macro set_tls_v6, tp, tmp1, tmp2
> +	.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
>   	ldr	\tmp1, =elf_hwcap
>   	ldr	\tmp1, [\tmp1, #0]
>   	mov	\tmp2, #0xffff0fff
>   	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> -	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> -	movne	\tmp1, #0
> -	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
>   	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> +	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
> +	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> +	mcrne	p15, 0, \tpuser, c13, c0, 2	@ set user r/w register
> +	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
>   	.endm
>
> -	.macro set_tls_software, tp, tmp1, tmp2
> +	.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
>   	mov	\tmp1, #0xffff0fff
>   	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
>   	.endm
> @@ -31,19 +34,31 @@
>   #ifdef CONFIG_TLS_REG_EMUL
>   #define tls_emu		1
>   #define has_tls_reg		1
> -#define set_tls		set_tls_none
> +#define switch_tls	switch_tls_none
>   #elif defined(CONFIG_CPU_V6)
>   #define tls_emu		0
>   #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
> -#define set_tls		set_tls_v6
> +#define switch_tls	switch_tls_v6
>   #elif defined(CONFIG_CPU_32v6K)
>   #define tls_emu		0
>   #define has_tls_reg		1
> -#define set_tls		set_tls_v6k
> +#define switch_tls	switch_tls_v6k
>   #else
>   #define tls_emu		0
>   #define has_tls_reg		0
> -#define set_tls		set_tls_software
> +#define switch_tls	switch_tls_software
>   #endif
>
> +#ifndef __ASSEMBLY__
> +static inline unsigned long get_tlsuser(void)
> +{
> +	if (has_tls_reg && !tls_emu)
> +	{
> +		unsigned long t;
> +		__asm__("mcr p15, 0, %0, c13, c0, 2" : : "r" (t));
> +		return t;
> +	}
> +	return 0;
> +}
> +#endif
>   #endif	/* __ASMARM_TLS_H */
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index 0f82098..80f09fe 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -728,15 +728,15 @@ ENTRY(__switch_to)
>    UNWIND(.fnstart	)
>    UNWIND(.cantunwind	)
>   	add	ip, r1, #TI_CPU_SAVE
> -	ldr	r3, [r2, #TI_TP_VALUE]
>    ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
>    THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
>    THUMB(	str	sp, [ip], #4		   )
>    THUMB(	str	lr, [ip], #4		   )
> +	ldrd	r4, r5, [r2, #TI_TP_VALUE]
>   #ifdef CONFIG_CPU_USE_DOMAINS
>   	ldr	r6, [r2, #TI_CPU_DOMAIN]
>   #endif
> -	set_tls	r3, r4, r5
> +	switch_tls r1, r4, r5, r3, r7
>   #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
>   	ldr	r7, [r2, #TI_TASK]
>   	ldr	r8, =__stack_chk_guard
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 047d3e4..24dbc72 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -39,6 +39,7 @@
>   #include <asm/thread_notify.h>
>   #include <asm/stacktrace.h>
>   #include <asm/mach/time.h>
> +#include <asm/tls.h>
>
>   #ifdef CONFIG_CC_STACKPROTECTOR
>   #include <linux/stackprotector.h>
> @@ -395,7 +396,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
>   	clear_ptrace_hw_breakpoint(p);
>
>   	if (clone_flags & CLONE_SETTLS)
> -		thread->tp_value = childregs->ARM_r3;
> +		thread->tp_value[0] = childregs->ARM_r3;
> +	thread->tp_value[1] = get_tlsuser();
>
>   	thread_notify(THREAD_NOTIFY_COPY, thread);
>
> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
> index 03deeff..2bc1514 100644
> --- a/arch/arm/kernel/ptrace.c
> +++ b/arch/arm/kernel/ptrace.c
> @@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
>   #endif
>
>   		case PTRACE_GET_THREAD_AREA:
> -			ret = put_user(task_thread_info(child)->tp_value,
> +			ret = put_user(task_thread_info(child)->tp_value[0],
>   				       datap);
>   			break;
>
> diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
> index 1c08911..f9d6259 100644
> --- a/arch/arm/kernel/traps.c
> +++ b/arch/arm/kernel/traps.c
> @@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
>   		return regs->ARM_r0;
>
>   	case NR(set_tls):
> -		thread->tp_value = regs->ARM_r0;
> +		thread->tp_value[0] = regs->ARM_r0;
>   		if (tls_emu)
>   			return 0;
>   		if (has_tls_reg) {
> @@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
>   	int reg = (instr >> 12) & 15;
>   	if (reg == 15)
>   		return 1;
> -	regs->uregs[reg] = current_thread_info()->tp_value;
> +	regs->uregs[reg] = current_thread_info()->tp_value[0];
>   	regs->ARM_pc += 4;
>   	return 0;
>   }
>
>




From marek.belisko at streamunlimited.com  Tue May  7 06:17:32 2013
From: marek.belisko at streamunlimited.com (Marek Belisko)
Date: Tue, 07 May 2013 12:17:32 +0200
Subject: [PATCH 1/2] clk: si5351: Fix msynth_recalc_rate return value
 when fOUT is 0.
In-Reply-To: <5188D174.90400@gmail.com>
References: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
 <5188D174.90400@gmail.com>
Message-ID: <5188D4BC.8010603@streamunlimited.com>

On 05/07/2013 12:03 PM, Sebastian Hesselbarth wrote:
> On 05/07/2013 10:14 AM, Marek Belisko wrote:
>> When p3 is eual to 0 then result for fOUT is 0. In that case we should
>> return 0 not parent_rate;
>>
>> This issue was causing deadlock in si5351 chip when user set_rate for
>> ms0->clk0 and then set_rate for ms1->clk1 (both ms sourced from plla).
>> After that clk1 was 0 and it wasn't possible to enable it again (try also
>> manually with i2cset commands). Only power cycle helps.
>
> Marek,
>
> does the fix below also affect the behavior above, i.e. not causing
> si5351 to hang?
Yes this fix problems with si5351 hang. Didn't investigate why but I 
assume some wrong register access or something.
>
> Anyway, your fix looks very sane to me and you get my
>
> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
>
>> Signed-off-by: Marek Belisko<marek.belisko at streamunlimited.com>
>> ---
>>   drivers/clk/clk-si5351.c |    2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
>> index fc215ce..a8fc0f4 100644
>> --- a/drivers/clk/clk-si5351.c
>> +++ b/drivers/clk/clk-si5351.c
>> @@ -607,7 +607,7 @@ static unsigned long
>> si5351_msynth_recalc_rate(struct clk_hw *hw,
>>           si5351_read_parameters(hwdata->drvdata, reg,&hwdata->params);
>>
>>       if (hwdata->params.p3 == 0)
>> -        return parent_rate;
>> +        return 0;
>>
>>       /*
>>        * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
>
>

	~marek

-- 
Marek Belisko

Software Developer
StreamUnlimited Engineering GmbH
Gutheil Schodergasse 8-12
A-1100 Vienna, Austria

Office: +421 267200087

e-mail: marek.belisko at streamunlimited.com
http://www.streamunlimited.com

Meet us at:

High End - Munich, 09 - 12 May, Hall 4/F05
IFA - Berlin, 6-11 September
CEDIA - Denver, 25-28 September


From benh at kernel.crashing.org  Tue May  7 06:19:18 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Tue, 07 May 2013 20:19:18 +1000
Subject: [PATCH v8 1/3] of/pci: Unify pci_process_bridge_OF_ranges from
 Microblaze and PowerPC
In-Reply-To: <20130507080142.GA8808@arm.com>
References: <1366627295-16964-1-git-send-email-Andrew.Murray@arm.com>
 <1366627295-16964-2-git-send-email-Andrew.Murray@arm.com>
 <1367721709.11982.37.camel@pasglop> <20130507080142.GA8808@arm.com>
Message-ID: <1367921958.25488.8.camel@pasglop>

On Tue, 2013-05-07 at 09:01 +0100, Andrew Murray wrote:
> 
> There were no objections to this latest revision until now and it is
> currently sitting with Jason Cooper (mvebu-next/pcie). [1]

Ok, well I've just sent Linus a pull request for my changes so at least
drop the powerpc changes from your tree for the time being.

> This is a view that was also shared by Bjorn [2] when I attempted to
> submit a patchset which moves struct pci_controller to asm-generic.

Right, it's the logical way to go

> The motativation for my patchsets were to give a way for ARM PCI host
> bridge drivers to parse the DT ranges property, but this snow-balled
> into unifying pci_process_bridge_OF_ranges.

Which I understand, I would probably have done the same thing in your
shoes :-)

> My v8 patchset provides a of_pci_range_parser which is used directly
> by a few ARM PCI DT host bridge drivers, this has been generally
> accepted and tested. I don't see why this can't remain and so I'd
> really like to keep this around. 

Sure, no objection, in fact I should/could probably update my new code
to use it as well.

> Grant, Benjamin would you be happy for me to resubmit this series
> which provides the of_pci_range_parser which will be used by the
> separate implementations of pci_process_bridge_OF_ranges in
> PowerPC/Microblaze?

Sure, in fact feel free to update my new code if you have more bandwidth
than I do, it should hit Linus tree soon hopefully unless he objects to
me having a second pull request this merge window...

> Benjamin are you able to still use of_pci_range_parser in your
> 'Support per-aperture memory offset' patch?

I see no reason why not. I just haven't looked into it much, I admit,
being bogged down with a pile of new HW bringup in the lab etc...

Cheers,
Ben.



From jonathan.austin at arm.com  Tue May  7 06:30:50 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 07 May 2013 11:30:50 +0100
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130506093059.GH23285@pengutronix.de>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
Message-ID: <5188D7DA.8040609@arm.com>

On 06/05/13 10:30, Uwe Kleine-K?nig wrote:
> Hello,
>
> On Thu, Apr 18, 2013 at 11:10:19AM +0200, Uwe Kleine-K?nig wrote:
>> On Mon, Mar 18, 2013 at 11:28:56AM -0700, Stephen Boyd wrote:
>>> The ISAR0 register indicates support for the SDIV and UDIV
>>> instructions in both the Thumb and ARM instruction set. Read the
>>> register to detect the supported instructions and update the
>>> elf_hwcap mask as appropriate. This is better than adding more
>>> and more cpuid checks in proc-v7.S for each new cpu variant that
>>> supports these instructions.
>> you pointed out yesterday that this could work on v7-m, too. As I based
>> my patches on 3.9-rc1 this patch (8164f7af88) wasn't included. When
>> updating this results in a warning, because I have
>>
>> 	6ebd4d0 (ARM: stub out read_cpuid and read_cpuid_ext for CPU_CP15=n)
>>
>> from rmk's devel-stable branch.
>>
>>> Acked-by: Will Deacon <will.deacon at arm.com>
>>> Cc: Stepan Moskovchenko <stepanm at codeaurora.org>
>>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
>>> ---
>>>   arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>>>   arch/arm/mm/proc-v7.S   |  4 ++--
>>>   2 files changed, 22 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>>> index e2c8bbf..f3ac13f 100644
>>> --- a/arch/arm/kernel/setup.c
>>> +++ b/arch/arm/kernel/setup.c
>>> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>>>   	printk("%s", buf);
>>>   }
>>>
>>> +static void __init cpuid_init_hwcaps(void)
>>> +{
>>> +	unsigned int divide_instrs;
>>> +
>>> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
>>> +		return;
>>> +
>>> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
>> The problem is that read_cpuid_ext is called which doesn't map to
>> something useful for v7-m. So maybe add a check:
>>
>> 	if (!IS_ENABLED(CONFIG_CPU_CP15))
>> 		return;
>>
>> ?
> The patch below fixes the issue for me on V7-M. The only drawback is
> that the list of registers isn't shared. Maybe someone has a nice idea?

I looked at whether there was anything nice that we could do around this 
but it most things end up more ugly than a separate long list of 
defines... It also makes things hard to understand so I prefer having 
these extra defines.

On the other hand, I think that this is about the time to think about 
another file for V7M CPUID stuff...

This file is beginning to look a bit unruly with all the different cases 
(V7M, !CPU_CP15, as well as the functions like read_cpuid_part_number 
that have the same definition in all cases). Thoughts?

>
> BTW, there doesn't seem to be an equivalent register set for
> CPUID_{CACHETYPE,TCM,TLBTYPE,MPIDR} on v7-M.
>
> Best regards
> Uwe
>
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 4eb94a3..ec635ff 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -10,6 +10,22 @@
>   #define CPUID_TLBTYPE	3
>   #define CPUID_MPIDR	5
>
> +#ifdef CONFIG_CPU_V7M

Why not stick the

#include <asm/io.h>
#include <asm/v7m.h>

here?
> +#define CPUID_EXT_PFR0	0x40
> +#define CPUID_EXT_PFR1	0x44
> +#define CPUID_EXT_DFR0	0x48
> +#define CPUID_EXT_AFR0	0x4c
> +#define CPUID_EXT_MMFR0	0x50
> +#define CPUID_EXT_MMFR1	0x54
> +#define CPUID_EXT_MMFR2	0x58
> +#define CPUID_EXT_MMFR3	0x5c
> +#define CPUID_EXT_ISAR0	0x60
> +#define CPUID_EXT_ISAR1	0x64
> +#define CPUID_EXT_ISAR2	0x68
> +#define CPUID_EXT_ISAR3	0x6c
> +#define CPUID_EXT_ISAR4	0x70
> +#define CPUID_EXT_ISAR5	0x74
> +#else
>   #define CPUID_EXT_PFR0	"c1, 0"
>   #define CPUID_EXT_PFR1	"c1, 1"
>   #define CPUID_EXT_DFR0	"c1, 2"
> @@ -24,6 +40,7 @@
>   #define CPUID_EXT_ISAR3	"c2, 3"
>   #define CPUID_EXT_ISAR4	"c2, 4"
>   #define CPUID_EXT_ISAR5	"c2, 5"
> +#endif
>
>   #define MPIDR_SMP_BITMASK (0x3 << 30)
>   #define MPIDR_SMP_VALUE (0x2 << 30)
> @@ -79,7 +96,23 @@ extern unsigned int processor_id;
>   		__val;							\
>   	})
>
> -#else /* ifdef CONFIG_CPU_CP15 */
> +#elif defined(CONFIG_CPU_V7M)
> +
> +#include <asm/io.h>
> +#include <asm/v7m.h>
> +
> +#define read_cpuid(reg)							\
> +	({								\
> +		WARN_ON_ONCE(1);					\
> +		0;							\
> +	})
> +
> +static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
> +{
> +	return readl(BASEADDR_V7M_SCB + offset);
> +}
> +
> +#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
>
>   /*
>    * read_cpuid and read_cpuid_ext should only ever be called on machines that
> @@ -108,9 +141,6 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
>
>   #elif defined(CONFIG_CPU_V7M)
>
> -#include <asm/io.h>
> -#include <asm/v7m.h>
> -
>   static inline unsigned int __attribute_const__ read_cpuid_id(void)
>   {
>   	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
> index 000499c..0c93588 100644
> --- a/arch/arm/mm/proc-v7m.S
> +++ b/arch/arm/mm/proc-v7m.S
> @@ -144,7 +144,7 @@ __v7m_proc_info:
>   	b	__v7m_setup		@ proc_info_list.__cpu_flush
>   	.long	cpu_arch_name
>   	.long	cpu_elf_name
> -	.long	HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_IDIVT
> +	.long	HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
>   	.long	cpu_v7m_name
>   	.long	v7m_processor_functions	@ proc_info_list.proc
>   	.long	0			@ proc_info_list.tlb
>




From marek.belisko at streamunlimited.com  Tue May  7 06:40:56 2013
From: marek.belisko at streamunlimited.com (Marek Belisko)
Date: Tue, 07 May 2013 12:40:56 +0200
Subject: [PATCH 2/2] clk: si5351: Powerdown output when clock rate is
 0.
In-Reply-To: <5188D26B.6020000@gmail.com>
References: <1367914491-17445-1-git-send-email-marek.belisko@streamunlimited.com>
 <1367914491-17445-2-git-send-email-marek.belisko@streamunlimited.com>
 <5188D26B.6020000@gmail.com>
Message-ID: <5188DA38.9030405@streamunlimited.com>

On 05/07/2013 12:07 PM, Sebastian Hesselbarth wrote:
> On 05/07/2013 10:14 AM, Marek Belisko wrote:
>> When rate is 0 powerdown clock output.
>>
>> Signed-off-by: Marek Belisko<marek.belisko at streamunlimited.com>
>> ---
>>   drivers/clk/clk-si5351.c |   32 +++++++++++++++++++-------------
>>   1 file changed, 19 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
>> index a8fc0f4..e254e76 100644
>> --- a/drivers/clk/clk-si5351.c
>> +++ b/drivers/clk/clk-si5351.c
>> @@ -1042,20 +1042,22 @@ static int si5351_clkout_set_rate(struct
>> clk_hw *hw, unsigned long rate,
>>       struct si5351_hw_data *hwdata =
>>           container_of(hw, struct si5351_hw_data, hw);
>>       unsigned long new_rate, new_err, err;
>> -    unsigned char rdiv;
>> +    unsigned char rdiv, pdn = 0;
>>
>>       /* round to closed rdiv */
>>       rdiv = SI5351_OUTPUT_CLK_DIV_1;
>> -    new_rate = parent_rate;
>> -    err = abs(new_rate - rate);
>> -    do {
>> -        new_rate>>= 1;
>> -        new_err = abs(new_rate - rate);
>> -        if (new_err>  err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
>> -            break;
>> -        rdiv++;
>> -        err = new_err;
>> -    } while (1);
>> +    if (rate) {
>> +        new_rate = parent_rate;
>
> Marek,
>
> initalizing pdn to SI5351_CLK_POWERDOWN and skip (with goto) to
> powerup/down call on zero rate will save us a level of indention here.
OK will fix and resubmit in v2. Thanks.
>
>> +        err = abs(new_rate - rate);
>> +        do {
>> +            new_rate>>= 1;
>> +            new_err = abs(new_rate - rate);
>> +            if (new_err>  err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
>> +                break;
>> +            rdiv++;
>> +            err = new_err;
>> +        } while (1);
>
> of course, pdn should be set to 0 here.
>
>> +    }
>>
>>       /* write output divider */
>>       switch (hwdata->num) {
>> @@ -1075,9 +1077,13 @@ static int si5351_clkout_set_rate(struct clk_hw
>> *hw, unsigned long rate,
>>                   rdiv<<  SI5351_OUTPUT_CLK_DIV_SHIFT);
>>       }
>>
>> -    /* powerup clkout */
>> +    /* when rate is 0 powerdown output */
>> +    if (rate == 0)
>> +        pdn = SI5351_CLK_POWERDOWN;
>> +
>> +    /* powerup/down clkout */
>>       si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
>> -            SI5351_CLK_POWERDOWN, 0);
>> +            SI5351_CLK_POWERDOWN, pdn);
>>
>>       dev_dbg(&hwdata->drvdata->client->dev,
>>           "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
>
>

marek
-- 
Marek Belisko

Software Developer
StreamUnlimited Engineering GmbH
Gutheil Schodergasse 8-12
A-1100 Vienna, Austria

Office: +421 267200087

e-mail: marek.belisko at streamunlimited.com
http://www.streamunlimited.com

Meet us at:

High End - Munich, 09 - 12 May, Hall 4/F05
IFA - Berlin, 6-11 September
CEDIA - Denver, 25-28 September


From jonathan.austin at arm.com  Tue May  7 06:56:28 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 07 May 2013 11:56:28 +0100
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130507092209.GD25387@mudshark.cambridge.arm.com>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
 <20130507092209.GD25387@mudshark.cambridge.arm.com>
Message-ID: <5188DDDC.1000201@arm.com>

Hi Will,

On 07/05/13 10:22, Will Deacon wrote:
> On Mon, May 06, 2013 at 10:30:59AM +0100, Uwe Kleine-K?nig wrote:

>> +
>> +#define read_cpuid(reg)							\
>> +	({								\
>> +		WARN_ON_ONCE(1);					\
>> +		0;							\
>> +	})
>
> We do have an MIDR in PMSAv7 (not to be confused with MPIDR), so why not read
> that here?
We don't need to add/remove anything for PMSAv7 as that's already 
implemented...

For V7M we have something called CPUID Base Register, not MIDR - the 
layout looks the same though. That's the only one of the CPUID_X that we 
have, but it is never requested directly - only via read_cpuid_id (this 
is to support a hardcoded cpuid from kconfig) so what Uwe's got does 
work, though I agree that it'd be much nicer to implement the underlying 
function and have the accessor general for both AR and M.

Jonny




From lorenzo.pieralisi at arm.com  Tue May  7 06:59:55 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Tue, 7 May 2013 11:59:55 +0100
Subject: [RFC PATCH v2] drivers: bus: add ARM CCI support
In-Reply-To: <20130503151706.GB2756@e102654-lin.cambridge.arm.com>
References: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
 <20130503151706.GB2756@e102654-lin.cambridge.arm.com>
Message-ID: <20130507105955.GA19477@e102568-lin.cambridge.arm.com>

On Fri, May 03, 2013 at 04:17:07PM +0100, Javi Merino wrote:
> Hi Lorenzo,
> 
> On Wed, May 01, 2013 at 05:18:28PM +0100, Lorenzo Pieralisi wrote:
> > On ARM multi-cluster systems coherency between cores running on
> > different clusters is managed by the cache-coherent interconnect (CCI).
> > It allows broadcasting of TLB invalidates and memory barriers and it
> > guarantees cache coherency at system level through snooping of slave
> > interfaces connected to it.
> > 
> > This patch enables the basic infrastructure required in Linux to handle and
> > programme the CCI component.
> > 
> > Non-local variables used by the CCI management functions called by power
> > down function calls after disabling the cache must be flushed out to main
> > memory in advance, otherwise incoherency of those values may occur if they
> > are sitting in the cache of some other CPU when power down functions
> > execute. Driver code ensures that relevant data structures are flushed
> > from inner and outer caches after the driver probe is completed.
> > 
> > CCI slave port resources are linked to set of CPUs through bus masters
> > phandle properties that link the interface resources to masters node in
> > the device tree.
> > 
> > Documentation describing the CCI DT bindings is provided with the patch.
> > 
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> > ---
> 
> [...]
> 
> > diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
> > new file mode 100644
> > index 0000000..0e70942
> > --- /dev/null
> > +++ b/include/linux/arm-cci.h
> > @@ -0,0 +1,59 @@
> > +/*
> > + * CCI cache coherent interconnect support
> > + *
> > + * Copyright (C) 2013 ARM Ltd.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> > + */
> > +
> > +#ifndef __LINUX_ARM_CCI_H
> > +#define __LINUX_ARM_CCI_H
> > +
> > +#include <linux/errno.h>
> > +#include <linux/types.h>
> > +
> > +struct device_node;
> > +
> > +#ifdef CONFIG_ARM_CCI
> > +extern int cci_ace_get_port(struct device_node *dn);
> > +extern int cci_disable_port_by_cpu(u64 mpidr);
> > +extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
> > +extern int __cci_control_port_by_index(u32 port, bool enable);
> > +#else
> > +static inline int cci_ace_get_port(struct device_node *dn, bool cpu)
> 
> Builds with !CONFIG_ARM_CCI fail because this definition of
> cci_ace_get_port() takes two arguments whereas the one for
> CONFIG_ARM_CCI takes only one.

Yes, sorry, I missed that while refactoring the interface.

Thanks,
Lorenzo



From padma.kvr at gmail.com  Tue May  7 07:12:40 2013
From: padma.kvr at gmail.com (Padma Venkat)
Date: Tue, 7 May 2013 16:42:40 +0530
Subject: [PATCH] ASoC: Samsung: i2s: Fix crash in i2s driver
In-Reply-To: <2286960.PxJxnETVLS@amdc1227>
References: <1367897941-18439-1-git-send-email-padma.v@samsung.com>
 <2286960.PxJxnETVLS@amdc1227>
Message-ID: <CAAgF-BcgtjKPoSy8SPsk3WnS8T3P9f=5U2tt3WHb0fFM=M61+w@mail.gmail.com>

Hi Tomasz,

On Tue, May 7, 2013 at 3:20 PM, Tomasz Figa <t.figa at samsung.com> wrote:
> Hi Padmavathi,
>
> On Tuesday 07 of May 2013 09:09:01 Padmavathi Venna wrote:
>> This patch fixes a null pointer deference in i2s driver in DT
>> case
>>
>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>> ---
>>
>> This patch is dependent on below patch posted by Thomas Abraham.
>> https://patchwork.kernel.org/patch/2224801/
>>
>>  sound/soc/samsung/i2s.c |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
>> index 7ce7c50..eaf6439 100644
>> --- a/sound/soc/samsung/i2s.c
>> +++ b/sound/soc/samsung/i2s.c
>> @@ -1182,7 +1182,7 @@ static int samsung_i2s_probe(struct platform_device
>> *pdev) pri_dai->sec_dai = sec_dai;
>>       }
>>
>> -     if (i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
>> +     if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
>
> This is a problem that needs to be fixed indeed. However the same problem
> exists in samsung_i2s_remove() as well (at least in latest linux-next).

This will go off once Thomas "ASoC: samsung: let device core setup the
default pin configuration"
patch get merged.

>
> This makes me wonder what happens with i2s_pdata in DT case. Most of drivers
> allocate a pdata struct anyway and fill it with data parsed from device tree.
> This allows rest of the code to remain unmodified and consider DT and non-DT
> cases equal.

This driver doesn't allocate the i2s_pdata in DT case. It directly
parse the information form DT file
and assign that information to i2s_dai.

Thanks
Padma

>
> Best regards,
> --
> Tomasz Figa
> Samsung Poland R&D Center
> SW Solution Development, Kernel and System Framework
>


From padma.kvr at gmail.com  Tue May  7 07:14:03 2013
From: padma.kvr at gmail.com (Padma Venkat)
Date: Tue, 7 May 2013 16:44:03 +0530
Subject: [PATCH V2 2/3] ARM: dts: add Exynos audio subsystem clock
 controller node
In-Reply-To: <2829319.bZPJnVErnQ@amdc1227>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
 <1367909016-19657-3-git-send-email-padma.v@samsung.com>
 <2829319.bZPJnVErnQ@amdc1227>
Message-ID: <CAAgF-BdJK9oEVj2fBHTCN5VoGa7eZceW4w=yMMrjnDSdy=P0rA@mail.gmail.com>

Hi Tomasz,

On Tue, May 7, 2013 at 3:24 PM, Tomasz Figa <t.figa at samsung.com> wrote:
> Hi Padmavathi,
>
> On Tuesday 07 of May 2013 12:13:35 Padmavathi Venna wrote:
>> Audio subsystem introduced in s5pv210 and exynos platforms
>> which has a internal clock controller. This patch adds a node
>> for the same on exynos5250.
>>
>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>>  1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi index 36c9d8d..7026de0 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -72,6 +72,12 @@
>>               #clock-cells = <1>;
>>       };
>>
>> +     clock_audss: audss-clock-controller at 0x03810000 {
>
> Just a nitpick: this should be @3810000, without the 0x and leading zeroes.

Okey. I will change this.

>
> Best regards,
> --
> Tomasz Figa
> Samsung Poland R&D Center
> SW Solution Development, Kernel and System Framework
>
>> +             compatible = "samsung,exynos5250-audss-clock";
>> +             reg = <0x03810000 0x0C>;
>> +             #clock-cells = <1>;
>> +     };
>> +
>>       gic:interrupt-controller at 10481000 {
>>               compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>>               #interrupt-cells = <3>;
>
Thanks
Padma


From weiyj.lk at gmail.com  Tue May  7 07:48:22 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Tue, 7 May 2013 19:48:22 +0800
Subject: [PATCH] usb: gadget: s3c2410_udc: fix error return code in
 s3c2410_udc_probe()
Message-ID: <CAPgLHd9zzFi6dCBH0V=eeqVtd=UstiqM8fDcDsMCfujAfEDHTg@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Fix to return a negative error code in the gpio_to_irq() error handling
case instead of 0, as done elsewhere in this function.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 drivers/usb/gadget/s3c2410_udc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index d0e75e1..c974776 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -1851,6 +1851,7 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
 		irq = gpio_to_irq(udc_info->vbus_pin);
 		if (irq < 0) {
 			dev_err(dev, "no irq for gpio vbus pin\n");
+			retval = irq;
 			goto err_gpio_claim;
 		}
 



From weiyj.lk at gmail.com  Tue May  7 07:58:17 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Tue, 7 May 2013 19:58:17 +0800
Subject: [PATCH] [ARM] rpc: acornscsi: fix error return code in
 acornscsi_probe()
Message-ID: <CAPgLHd-M=0gj1_-ip51qbhHfBszSBkiW5VD8cp_-AVOjn7XP7A@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Fix to return -ENOMEM in the ecardm_iomap() error handling
case instead of 0, as done elsewhere in this function.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 drivers/scsi/arm/acornscsi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/arm/acornscsi.c b/drivers/scsi/arm/acornscsi.c
index 09ba186..bee7142 100644
--- a/drivers/scsi/arm/acornscsi.c
+++ b/drivers/scsi/arm/acornscsi.c
@@ -2961,8 +2961,10 @@ static int acornscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 
 	ashost->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 	ashost->fast = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
-	if (!ashost->base || !ashost->fast)
+	if (!ashost->base || !ashost->fast) {
+		ret = -ENOMEM;
 		goto out_put;
+	}
 
 	host->irq = ec->irq;
 	ashost->host = host;



From linux at arm.linux.org.uk  Tue May  7 08:02:02 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 May 2013 13:02:02 +0100
Subject: [GIT PULL] Urgent omap timer fix for current merge window
In-Reply-To: <20130506234610.GK28721@atomide.com>
References: <20130506234610.GK28721@atomide.com>
Message-ID: <20130507120202.GK21614@n2100.arm.linux.org.uk>

On Mon, May 06, 2013 at 04:46:11PM -0700, Tony Lindgren wrote:
> Vaibhav Hiremath (1):
>       ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a

Neither your pull request subject nor the above summary line really
sum up what the problem is - the real problem is "fix breakage causing
OMAP to fail to boot".

I've just been chasing this problem and the descriptions given on this
just suggest that it's a timer issue not a non-boot issue.


From stefano.stabellini at eu.citrix.com  Tue May  7 07:58:32 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 7 May 2013 12:58:32 +0100
Subject: [Xen-devel] [PATCH RFC v2 4/4] xen/arm: account for stolen ticks
In-Reply-To: <1367918270.26321.39.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918270.26321.39.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305071252350.4147@kaball.uk.xensource.com>

On Tue, 7 May 2013, Ian Campbell wrote:
> On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> > Register the runstate_memory_area with the hypervisor.
> > Use pv_time_ops.steal_clock to account for stolen ticks.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/xen/enlighten.c |   23 +++++++++++++++++++++++
> >  1 files changed, 23 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index ee86bfa..2a5cc82 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -14,7 +14,10 @@
> >  #include <xen/xen-ops.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> > +#include <asm/arch_timer.h>
> >  #include <asm/system_misc.h>
> > +#include <asm/paravirt.h>
> > +#include <linux/jump_label.h>
> >  #include <linux/interrupt.h>
> >  #include <linux/irqreturn.h>
> >  #include <linux/module.h>
> > @@ -152,6 +155,20 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
> >  }
> >  EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
> >  
> > +unsigned long long xen_stolen_accounting(int cpu)
> > +{
> > +	struct vcpu_runstate_info state;
> > +
> > +	if (cpu != get_cpu())
> 
> get_cpu disables preempt, so you need a matching put_cpu.

Oops, thanks.


> But actually I think you just want smp_processor_id and you probably
> want the BUG_ON form to get unlikely etc.
>
> That said, you don't use cpu for anything else, so why not drop it
> entirely?

Ah, that's right, legacy of the past. I'll do that.


> > +		BUG();
> > +
> > +	xen_get_runstate_snapshot(&state);
> > +
> > +	WARN_ON(state.state != RUNSTATE_running);
> > +
> > +	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
> > +}
> > +
> >  static void __init xen_percpu_init(void *unused)
> >  {
> >  	struct vcpu_register_vcpu_info info;
> > @@ -170,6 +187,8 @@ static void __init xen_percpu_init(void *unused)
> >  		BUG();
> >  	per_cpu(xen_vcpu, cpu) = vcpup;
> >  
> > +	xen_setup_runstate_info(cpu);
> > +
> >  	enable_percpu_irq(xen_events_irq, 0);
> >  }
> >  
> > @@ -301,6 +320,10 @@ static int __init xen_init_events(void)
> >  
> >  	on_each_cpu(xen_percpu_init, NULL, 0);
> >  
> > +	pv_time_ops.steal_clock = xen_stolen_accounting;
> > +	static_key_slow_inc(&paravirt_steal_enabled);
> > +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> 
> We don't seem to do this on x86 -- is that a bug on x86 on Xen?

On x86 we do all the accounting in do_stolen_accounting, called from our
own interrupt handler (xen_timer_interrupt).
I don't think we would gain anything by using the common infrastructure,
we would actually loose the idle ticks accounting we do there.

Speaking of which, I don't think that pv_time_ops.steal_clock would
properly increase CPUTIME_IDLE the way we do in do_stolen_accounting.

How much of an issue is that?


From ohad at wizery.com  Tue May  7 08:04:27 2013
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Tue, 7 May 2013 15:04:27 +0300
Subject: [GIT PULL] hwspinlock for 3.10
Message-ID: <CAK=WgbbLUya4MQeh3h6v3a8LcTryJ8H4P7uLK3u9vKBvQey=ag@mail.gmail.com>

The following changes since commit f6161aa153581da4a3867a2d1a7caf4be19b6ec9:

  Linux 3.9-rc2 (2013-03-10 16:54:19 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ohad/hwspinlock.git
tags/hwspinlock-3.10

for you to fetch changes up to 8ae053d62e88c400330ebaf27558bf02dde5a1fa:

  hwspinlock/omap: support OMAP5 as well (2013-04-05 09:11:17 +0300)

----------------------------------------------------------------
A single patch from Vincent extending OMAP's hwspinlock support to OMAP5.

----------------------------------------------------------------
Vincent Stehl? (1):
      hwspinlock/omap: support OMAP5 as well

 drivers/hwspinlock/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


From ohad at wizery.com  Tue May  7 08:04:54 2013
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Tue, 7 May 2013 15:04:54 +0300
Subject: [GIT PULL] rpmsg for 3.10
Message-ID: <CAK=WgbbuJt4V2c_hqSzcqDwts6J7EQvD5CkoK95QqxoqboS2Fg@mail.gmail.com>

The following changes since commit f6161aa153581da4a3867a2d1a7caf4be19b6ec9:

  Linux 3.9-rc2 (2013-03-10 16:54:19 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ohad/rpmsg.git tags/rpmsg-3.10

for you to fetch changes up to 397944df3290ddc46dcc6a08cd71fb560700431b:

  rpmsg: fix kconfig dependencies for VIRTIO (2013-04-21 16:32:29 +0300)

----------------------------------------------------------------
A small pull request consisting of:
- Make rpmsg process all pending messages instead of just
  one, from Robert Tivy
- Fix Kconfig dependency on VIRTUALIZATION, from Suman.
  Note: this was submitted late during the 3.9 rc cycle and it
  seemed appropriate to wait with it for the merge window.
- Belated addition of an rpmsg entry to the MAINTAINERS file.
  People seem to look for this.

----------------------------------------------------------------
Ohad Ben-Cohen (1):
      MAINTAINERS: add rpmsg entry

Robert Tivy (1):
      rpmsg: process _all_ pending messages in rpmsg_recv_done

Suman Anna (1):
      rpmsg: fix kconfig dependencies for VIRTIO

 MAINTAINERS                      |  8 +++++++
 drivers/rpmsg/Kconfig            |  1 +
 drivers/rpmsg/virtio_rpmsg_bus.c | 49 ++++++++++++++++++++++++++++------------
 3 files changed, 44 insertions(+), 14 deletions(-)


From rusty at rustcorp.com.au  Tue May  7 00:46:22 2013
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Tue, 07 May 2013 14:16:22 +0930
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
 <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
Message-ID: <87txmfo0rl.fsf@rustcorp.com.au>

Peter Maydell <peter.maydell at linaro.org> writes:
> On 6 May 2013 06:11, Rusty Russell <rusty at rustcorp.com.au> wrote:
>> Peter Maydell <peter.maydell at linaro.org> writes:
>>> To be actually useful we need to also specify something in
>>> the device tree to say "here is where you will find your
>>> emergency output and what it is".
>>
>> Hmm, I'm not sure that's true.  It looks like it needs:
>>
>> 1) An enhancment to the vdev->set_config callback to pass through (at
>>    least) an offset, probably offset and length.
>>
>> 2) An emerg_write() function ptr which can be called at any time, set by
>>    virtio_console.c's class_init:
>
> That all looks like sensible QEMU implementation possibilities
> but it seems to be a bit of a non-sequitur from "how do we
> tell the kernel to actually use this?"

You enable the feature in the virtio console device, and a kernel
compiled with EARLY_PRINTK will use it?

Cheers,
Rusty.


From stefano.stabellini at eu.citrix.com  Tue May  7 08:15:02 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 7 May 2013 13:15:02 +0100
Subject: [Xen-devel] [PATCH RFC v2 2/4] arm: introduce CONFIG_PARAVIRT
 and pv_time_ops
In-Reply-To: <1367918609.26321.43.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918609.26321.43.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305071301040.4147@kaball.uk.xensource.com>

On Tue, 7 May 2013, Ian Campbell wrote:
> On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> > Introduce CONFIG_PARAVIRT on ARM.
> 
> What about PARAVIRT_TIME_ACCOUNTING? I'm not sure what it is but it
> looks like a more lightweight version of pv stolen time?
 
PARAVIRT_TIME_ACCOUNTING selects PARAVIRT on x86 :-)


> > The only paravirt interface supported is pv_time_ops.steal_clock.
> > No runtime pvops patching yet.
> 
> Or indeed ever, I think. The use cases for patching on x86 are not
> things which carry over to ARM with virt extensions.

Agreed


> > This allows us to make us of steal_account_process_tick for stolen ticks
> > accounting.
> > 
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > CC: linux at arm.linux.org.uk
> > CC: will.deacon at arm.com
> > CC: nico at linaro.org
> > CC: marc.zyngier at arm.com
> > CC: cov at codeaurora.org
> > CC: arnd at arndb.de
> > CC: olof at lixom.net
> > ---
> >  arch/arm/Kconfig                |    9 +++++++++
> >  arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
> >  arch/arm/kernel/Makefile        |    1 +
> >  arch/arm/kernel/paravirt.c      |   32 ++++++++++++++++++++++++++++++++
> >  4 files changed, 61 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/include/asm/paravirt.h
> >  create mode 100644 arch/arm/kernel/paravirt.c
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 344e299..35cb10a 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1887,12 +1887,21 @@ config XEN_DOM0
> >  	def_bool y
> >  	depends on XEN
> >  
> > +config PARAVIRT
> > +	bool "Enable paravirtualization code"
> > +	---help---
> > +	  This changes the kernel so it can modify itself when it is run
> > +	  under a hypervisor, potentially improving performance significantly
> > +	  over full virtualization.  However, when run without a hypervisor
> > +	  the kernel is theoretically slower and slightly larger.
> 
> I'm not sure this description (carried over from x86) are really true
> for ARM. e.g. the downsides there when not virtualised are in the PV MMU
> (pte operations) and interrupt masking stuff, which should never make
> its way onto ARM.

Right


> I think it would be a worthwhile change to refactor the stolen time
> handling out from under the rather wide reaching umbrella of the x86
> PARAVIRT option. (assuming PARAVIRT_TIME_ACCOUNTING isn't already that)

Actually PARAVIRT doesn't mean much in common code, the only thing it
covers is stolen time.
What I mean to say is that just because we are introducing something
called "PARAVIRT" on ARM, it doesn't mean that it has to come with all
sort of baggage.


> > +
> >  config XEN
> >  	bool "Xen guest support on ARM (EXPERIMENTAL)"
> >  	depends on ARM && AEABI && OF
> >  	depends on CPU_V7 && !CPU_V6
> >  	depends on !GENERIC_ATOMIC64
> >  	select ARM_PSCI
> > +	select PARAVIRT
> >  	help
> >  	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
> >  
> > diff --git a/arch/arm/include/asm/paravirt.h b/arch/arm/include/asm/paravirt.h
> > new file mode 100644
> > index 0000000..3b95bc6
> > --- /dev/null
> > +++ b/arch/arm/include/asm/paravirt.h
> > @@ -0,0 +1,19 @@
> > +#ifndef _ASM_ARM_PARAVIRT_H
> > +#define _ASM_ARM_PARAVIRT_H
> > +
> > +struct static_key;
> > +extern struct static_key paravirt_steal_enabled;
> > +extern struct static_key paravirt_steal_rq_enabled;
> > +
> > +struct pv_time_ops {
> > +	unsigned long long (*steal_clock)(int cpu);
> > +};
> > +extern struct pv_time_ops pv_time_ops;
> > +
> > +static inline u64 paravirt_steal_clock(int cpu)
> > +{
> > +	return pv_time_ops.steal_clock(cpu);
> > +}
> > +
> > +
> > +#endif
> > diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> > index dd9d90a..6764f60 100644
> > --- a/arch/arm/kernel/Makefile
> > +++ b/arch/arm/kernel/Makefile
> > @@ -86,5 +86,6 @@ ifeq ($(CONFIG_ARM_PSCI),y)
> >  obj-y				+= psci.o
> >  obj-$(CONFIG_SMP)		+= psci_smp.o
> >  endif
> > +obj-$(CONFIG_PARAVIRT)	+= paravirt.o
> >  
> >  extra-y := $(head-y) vmlinux.lds
> > diff --git a/arch/arm/kernel/paravirt.c b/arch/arm/kernel/paravirt.c
> > new file mode 100644
> > index 0000000..3e73fc8
> > --- /dev/null
> > +++ b/arch/arm/kernel/paravirt.c
> > @@ -0,0 +1,32 @@
> > +/*
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * Copyright (C) 2013 Citrix Systems
> > + *
> > + * Author: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > + */
> > +
> > +#include <linux/export.h>
> > +#include <linux/jump_label.h>
> > +#include <linux/types.h>
> > +#include <asm/paravirt.h>
> > +
> > +struct static_key paravirt_steal_enabled;
> > +struct static_key paravirt_steal_rq_enabled;
> > +
> > +static u64 native_steal_clock(int cpu)
> > +{
> > +	return 0;
> > +}
> > +
> > +struct pv_time_ops pv_time_ops = {
> > +	.steal_clock = native_steal_clock,
> > +};
> > +EXPORT_SYMBOL_GPL(pv_time_ops);
> 
> This foo_ops.bar and native_bar thing is a bit of a hangover from the
> paravirt patching infrastructure on x86 and it doesn't really apply
> here.
> 
> Given that the call to paravirt_steal_time call is already protected by
> this static_key stuff I think it would be safe to leave the hook as NULL
> in the case where it is unused.
 
Good point


> Given all the different clock sources on ARM is there not an existing
> ops struct where this could live?

I am not sure, but I would be happy to move it something arch-specific.


From peter.maydell at linaro.org  Tue May  7 08:19:46 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Tue, 7 May 2013 13:19:46 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <87txmfo0rl.fsf@rustcorp.com.au>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
 <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
 <87txmfo0rl.fsf@rustcorp.com.au>
Message-ID: <CAFEAcA9jBSpN2p9ZaU+_gX41Ke3nvpSKVrWV8Rioy_ioadKCgg@mail.gmail.com>

On 7 May 2013 05:46, Rusty Russell <rusty at rustcorp.com.au> wrote:
> Peter Maydell <peter.maydell at linaro.org> writes:
>> That all looks like sensible QEMU implementation possibilities
>> but it seems to be a bit of a non-sequitur from "how do we
>> tell the kernel to actually use this?"
>
> You enable the feature in the virtio console device, and a kernel
> compiled with EARLY_PRINTK will use it?

Well, at the moment EARLY_PRINTK is hardcoded to
"use some specific UART or equivalent selected at
compile time". So the equivalent presumably would
be to hard-compile "use virtio-console", but then
how does that code know where the virtio-console
is in the address space?

-- PMM


From ohad at wizery.com  Tue May  7 08:19:52 2013
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Tue, 7 May 2013 15:19:52 +0300
Subject: [GIT PULL] remoteproc for 3.10
Message-ID: <CAK=WgbYBk=ut8M_Mn5hQ8V_b+gUijFz8RrOkyfKaC1Xk8p4+Jg@mail.gmail.com>

There's a trivial merge conflict with a Kconfig typo that got fixed
during the rc cycle,
but otherwise:

The following changes since commit f6161aa153581da4a3867a2d1a7caf4be19b6ec9:

  Linux 3.9-rc2 (2013-03-10 16:54:19 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
tags/remoteproc-3.10

for you to fetch changes up to b9777859ec015a78dae1476e317d04f851bfdd0d:

  remoteproc: fix kconfig dependencies for VIRTIO (2013-04-21 16:30:22 +0300)

----------------------------------------------------------------
This pull request contains:
- Some refactoring, cleanups and small improvements
  from Sjur Br?ndeland. The improvements are mainly
  about better supporting varios virtio properties
  (such as virtio's config space, status and features).
  I now see that I messed up while commiting one of Sjur's
  patches and erroneously put myself as the author, as well
  as letting a nasty typo sneak in. I will not fix this in
  order to avoid rebasing the patches. Sjur - sorry!
- A new remoteproc driver for OMAP-L13x (technically a
  DaVinci platform) from Robert Tivy.
- Extend OMAP support to OMAP5 as well, from Vincent Stehl?.
- Fix Kconfig VIRTUALIZATION dependency, from Suman Anna
  (a non-critical fix which arrived late during the rc cycle).

----------------------------------------------------------------
Ohad Ben-Cohen (1):
      remoteproc: perserve resource table data

Robert Tivy (2):
      remoteproc: support default firmware name in rproc_alloc()
      remoteproc/davinci: add a remoteproc driver for OMAP-L13x DSP

Sjur Br?ndeland (7):
      remoteproc: refactor rproc_elf_find_rsc_table()
      remoteproc: add find_loaded_rsc_table firmware ops
      remoteproc: parse STE-firmware and find resource table address
      remoteproc: code cleanup of resource parsing
      remoteproc: calculate max_notifyid by counting vrings
      remoteproc: support virtio config space.
      remoteproc: set vring addresses in resource table

Suman Anna (1):
      remoteproc: fix kconfig dependencies for VIRTIO

Vincent Stehl? (1):
      remoteproc/omap: support OMAP5 too

 drivers/remoteproc/Kconfig                 |  27 ++-
 drivers/remoteproc/Makefile                |   1 +
 drivers/remoteproc/da8xx_remoteproc.c      | 324 +++++++++++++++++++++++++++++
 drivers/remoteproc/remoteproc_core.c       | 211 ++++++++++++-------
 drivers/remoteproc/remoteproc_elf_loader.c | 100 ++++++---
 drivers/remoteproc/remoteproc_internal.h   |  15 +-
 drivers/remoteproc/remoteproc_virtio.c     |  79 +++++--
 drivers/remoteproc/ste_modem_rproc.c       |  45 ++--
 include/linux/remoteproc.h                 |  13 +-
 9 files changed, 677 insertions(+), 138 deletions(-)
 create mode 100644 drivers/remoteproc/da8xx_remoteproc.c


From u.kleine-koenig at pengutronix.de  Tue May  7 08:40:13 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 7 May 2013 14:40:13 +0200
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <5188DDDC.1000201@arm.com>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
 <20130507092209.GD25387@mudshark.cambridge.arm.com>
 <5188DDDC.1000201@arm.com>
Message-ID: <20130507124013.GM23285@pengutronix.de>

On Tue, May 07, 2013 at 11:56:28AM +0100, Jonathan Austin wrote:
> Hi Will,
> 
> On 07/05/13 10:22, Will Deacon wrote:
> >On Mon, May 06, 2013 at 10:30:59AM +0100, Uwe Kleine-K?nig wrote:
> 
> >>+
> >>+#define read_cpuid(reg)							\
> >>+	({								\
> >>+		WARN_ON_ONCE(1);					\
> >>+		0;							\
> >>+	})
> >
> >We do have an MIDR in PMSAv7 (not to be confused with MPIDR), so why not read
> >that here?
> We don't need to add/remove anything for PMSAv7 as that's already
> implemented...
> 
> For V7M we have something called CPUID Base Register, not MIDR - the
> layout looks the same though. That's the only one of the CPUID_X
> that we have, but it is never requested directly - only via
> read_cpuid_id (this is to support a hardcoded cpuid from kconfig) so
> what Uwe's got does work, though I agree that it'd be much nicer to
> implement the underlying function and have the accessor general for
> both AR and M.
The current state (that is next + the patch from this thread) is:

#ifdef CONFIG_CPU_CP15
	define read_cpuid and read_cpuid_ext using mrc p15
	read_cpuid_id = read_cpuid(CPUID_ID)
#elif defined (CONFIG_CPU_V7M)
	read_cpuid returns 0 (with a warning)
	read_cpuid_ext reads from SCB
	read_cpuid_id reads from V7M_SCB_CPUID
#else
	read_cpuid and read_cpuid_ext return 0 (with a warning)
	read_cpuid_id returns CONFIG_PROCESSOR_ID (a bit simplified)
#endif

Now, what is the "underlying function" that should be used to implement
which accessor? I assume you want to have

	read_cpuid_id = read_cpuid(CPUID_ID)

on v7-M, too? So what is the suggestion for read_cpuid?:

	if (reg == CPUID_ID)
		return readl(V7M_SCB_CPUID);
	else
		return 0;
	
That doesn't make much sense in my eyes. If I got you wrong, please give
more details.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From arnd at arndb.de  Tue May  7 08:48:19 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 May 2013 14:48:19 +0200
Subject: [GIT PULL] Urgent omap timer fix for current merge window
In-Reply-To: <20130506234610.GK28721@atomide.com>
References: <20130506234610.GK28721@atomide.com>
Message-ID: <201305071448.19868.arnd@arndb.de>

On Tuesday 07 May 2013, Tony Lindgren wrote:
> The following changes since commit dc2d3db8137fba0f62d7517e1bea8a47f69fcbc4:
> 
>   Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers (2013-04-08 19:30:48 +0200)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/fixes-for-merge-window
> 
> for you to fetch changes up to 08a48be32ff31d38bcfec7d210c954cb62fd5cd7:
> 
>   ARM: OMAP4: change the device names in usb_bind_phy (2013-05-06 16:39:16 -0700)
> 
> ----------------------------------------------------------------
> An urgent fix for a timer mismerge for and a regression fix for
> musb device naming change.
> 

Hi Tony,

Russell also ran into this problem, so I'm including these in the late/cleanup branch,
which I'll send to Linus later today.

Thanks,

	Arnd


From pdeschrijver at nvidia.com  Tue May  7 08:48:49 2013
From: pdeschrijver at nvidia.com (Peter De Schrijver)
Date: Tue, 7 May 2013 15:48:49 +0300
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>

On Mon, May 06, 2013 at 10:39:04PM +0200, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
> they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
> this, simply disable LP2 if the PCI driver and DT node are both enabled.
> 

Wouldn't it make more sense to disable LP2 when we actually detect a PCIe
device?

Cheers,

Peter.


From will.deacon at arm.com  Tue May  7 08:54:11 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 May 2013 13:54:11 +0100
Subject: [RFC PATCH] implement read_cpuid_ext for v7-M (Was: Re: [PATCHv2
 2/3] ARM: Detect support for SDIV/UDIV from ISAR0) register
In-Reply-To: <20130507124013.GM23285@pengutronix.de>
References: <1363631337-13816-1-git-send-email-sboyd@codeaurora.org>
 <1363631337-13816-3-git-send-email-sboyd@codeaurora.org>
 <20130418091019.GA21099@pengutronix.de>
 <20130506093059.GH23285@pengutronix.de>
 <20130507092209.GD25387@mudshark.cambridge.arm.com>
 <5188DDDC.1000201@arm.com> <20130507124013.GM23285@pengutronix.de>
Message-ID: <20130507125411.GA26694@mudshark.cambridge.arm.com>

On Tue, May 07, 2013 at 01:40:13PM +0100, Uwe Kleine-K?nig wrote:
> On Tue, May 07, 2013 at 11:56:28AM +0100, Jonathan Austin wrote:
> > For V7M we have something called CPUID Base Register, not MIDR - the
> > layout looks the same though. That's the only one of the CPUID_X
> > that we have, but it is never requested directly - only via
> > read_cpuid_id (this is to support a hardcoded cpuid from kconfig) so
> > what Uwe's got does work, though I agree that it'd be much nicer to
> > implement the underlying function and have the accessor general for
> > both AR and M.
> The current state (that is next + the patch from this thread) is:
> 
> #ifdef CONFIG_CPU_CP15
> 	define read_cpuid and read_cpuid_ext using mrc p15
> 	read_cpuid_id = read_cpuid(CPUID_ID)
> #elif defined (CONFIG_CPU_V7M)
> 	read_cpuid returns 0 (with a warning)
> 	read_cpuid_ext reads from SCB
> 	read_cpuid_id reads from V7M_SCB_CPUID
> #else
> 	read_cpuid and read_cpuid_ext return 0 (with a warning)
> 	read_cpuid_id returns CONFIG_PROCESSOR_ID (a bit simplified)
> #endif
> 
> Now, what is the "underlying function" that should be used to implement
> which accessor? I assume you want to have
> 
> 	read_cpuid_id = read_cpuid(CPUID_ID)
> 
> on v7-M, too? So what is the suggestion for read_cpuid?:
> 
> 	if (reg == CPUID_ID)
> 		return readl(V7M_SCB_CPUID);
> 	else
> 		return 0;

Yes, either switch on the reg or define CPUID_ID to be V7M_SCB_CPUID for
v7m, then just do the readl in read_cpuid. I'm not sure the warnings add
much (we can do read_cpuid(random integer) with cp15 and it will blindly
construct the mrc).

> That doesn't make much sense in my eyes. If I got you wrong, please give
> more details.

I'm just suggesting that we try and keep the functions similar between v7m and
cp15 where there isn't a good reason not to.

Up to you.

Will


From andre.przywara at linaro.org  Tue May  7 08:55:13 2013
From: andre.przywara at linaro.org (Andre Przywara)
Date: Tue,  7 May 2013 14:55:13 +0200
Subject: [PATCH] ARM: KVM: prevent NULL pointer dereference with KVM ioctl
Message-ID: <1367931313-14839-1-git-send-email-andre.przywara@linaro.org>

Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
with the KVM_ARM_VCPU_INIT ioctl before being used with further
requests. KVM_RUN checks whether this initialization has been
done, but other ioctls do not.
Namely KVM_GET_REG_LIST will dereference an array with index -1
without initialization and thus leads to a kernel oops.
Fix this by adding checks before executing the ioctl handlers.

Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
---
 arch/arm/kvm/arm.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index c1fe498..0c571ff 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -893,6 +893,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 	case KVM_SET_ONE_REG:
 	case KVM_GET_ONE_REG: {
 		struct kvm_one_reg reg;
+
+		/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
+		if (unlikely(vcpu->arch.target < 0))
+			return -ENOEXEC;
+
 		if (copy_from_user(&reg, argp, sizeof(reg)))
 			return -EFAULT;
 		if (ioctl == KVM_SET_ONE_REG)
@@ -905,6 +910,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 		struct kvm_reg_list reg_list;
 		unsigned n;
 
+		/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
+		if (unlikely(vcpu->arch.target < 0))
+			return -ENOEXEC;
+
 		if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 			return -EFAULT;
 		n = reg_list.n;
-- 
1.7.12.1



From Ian.Campbell at citrix.com  Tue May  7 08:56:16 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Tue, 7 May 2013 13:56:16 +0100
Subject: [Xen-devel] [PATCH RFC v2 2/4] arm: introduce CONFIG_PARAVIRT
 and pv_time_ops
In-Reply-To: <alpine.DEB.2.02.1305071301040.4147@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918609.26321.43.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305071301040.4147@kaball.uk.xensource.com>
Message-ID: <1367931376.26321.117.camel@zakaz.uk.xensource.com>

On Tue, 2013-05-07 at 13:15 +0100, Stefano Stabellini wrote:
> On Tue, 7 May 2013, Ian Campbell wrote:
> > On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> > > Introduce CONFIG_PARAVIRT on ARM.
> > 
> > What about PARAVIRT_TIME_ACCOUNTING? I'm not sure what it is but it
> > looks like a more lightweight version of pv stolen time?
>  
> PARAVIRT_TIME_ACCOUNTING selects PARAVIRT on x86 :-)

Ah, that's maybe what confused me.

TBH its not at all clear to me what distinction the core code is trying
to make with those two options, but do we not also want/need
PARAVIRT_TIME_ACCOUNTING? Having reread the help text it seems to be
some sort of "more accurate" accounting?

> > I think it would be a worthwhile change to refactor the stolen time
> > handling out from under the rather wide reaching umbrella of the x86
> > PARAVIRT option. (assuming PARAVIRT_TIME_ACCOUNTING isn't already that)
> 
> Actually PARAVIRT doesn't mean much in common code, the only thing it
> covers is stolen time.
> What I mean to say is that just because we are introducing something
> called "PARAVIRT" on ARM, it doesn't mean that it has to come with all
> sort of baggage.

I was more concerned with perceived baggage than actual trunks full of
skeletons.

Ian.



From Ian.Campbell at citrix.com  Tue May  7 08:56:41 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Tue, 7 May 2013 13:56:41 +0100
Subject: [Xen-devel] [PATCH RFC v2 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305071252350.4147@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918270.26321.39.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305071252350.4147@kaball.uk.xensource.com>
Message-ID: <1367931401.26321.118.camel@zakaz.uk.xensource.com>

> > > @@ -301,6 +320,10 @@ static int __init xen_init_events(void)
> > >  
> > >  	on_each_cpu(xen_percpu_init, NULL, 0);
> > >  
> > > +	pv_time_ops.steal_clock = xen_stolen_accounting;
> > > +	static_key_slow_inc(&paravirt_steal_enabled);
> > > +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> > 
> > We don't seem to do this on x86 -- is that a bug on x86 on Xen?
> 
> On x86 we do all the accounting in do_stolen_accounting, called from our
> own interrupt handler (xen_timer_interrupt).
> I don't think we would gain anything by using the common infrastructure,
> we would actually loose the idle ticks accounting we do there.
> 
> Speaking of which, I don't think that pv_time_ops.steal_clock would
> properly increase CPUTIME_IDLE the way we do in do_stolen_accounting.
> 
> How much of an issue is that?

Doesn't the generic account_idle_time handle this?

Ian.



From thierry.reding at avionic-design.de  Tue May  7 09:08:50 2013
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 7 May 2013 15:08:50 +0200
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
 <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>
Message-ID: <20130507130850.GA11202@avionic-0098.adnet.avionic-design.de>

On Tue, May 07, 2013 at 03:48:49PM +0300, Peter De Schrijver wrote:
> On Mon, May 06, 2013 at 10:39:04PM +0200, Stephen Warren wrote:
> > From: Stephen Warren <swarren at nvidia.com>
> > 
> > Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
> > they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
> > this, simply disable LP2 if the PCI driver and DT node are both enabled.
> > 
> 
> Wouldn't it make more sense to disable LP2 when we actually detect a PCIe
> device?

I'm not sure a patch to do so would be as simple as this one. For one,
the cpuidle framework will already have been initialized when PCIe
enumeration completes. So some way of permanently disabling one state at
runtime would be required and I don't think cpuidle provides an API to
do so. I know the latter isn't really a good reason, but I don't think
adding that kind of API just because Tegra20 seems to have a bug would
be appropriate.

Furthermore, it is quite likely that the PCIe controller will only be
enabled in DT for devices that actually have a PCIe device hooked up.

Thierry
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From eduardo.valentin at ti.com  Tue May  7 09:15:00 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Tue, 7 May 2013 09:15:00 -0400
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <20130507003651.GA26035@obsidianresearch.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
 <20130506223653.GA12089@obsidianresearch.com> <51884971.9050508@ti.com>
 <20130507003651.GA26035@obsidianresearch.com>
Message-ID: <5188FE54.6050200@ti.com>

Hello Jason,

On 06-05-2013 20:36, Jason Gunthorpe wrote:
> On Mon, May 06, 2013 at 08:23:13PM -0400, Eduardo Valentin wrote:
> 
>>> I get the impression it is desired to minimize driver kconfig
>>> dependencies to the minimum required to compile to increase build
>>> testing coverage, so maybe it would be appropriate to drop this
>>> entirely?
> 
>> Well, it is also desired to compile things to the correct target
>> right?
> 
> There is some of that too..
> 
> But broadly the direction seems that drivers should have minimal
> dependencies so, eg, the thermal maintainer compiling for x86 should
> be able to compile test/static analyze your driver..
> 

Well, I do not see much of this attempt actually. Do you have some link
/ evidene that shows someone who actually cares about compiling drivers
for targets that they are not used for? On this specific driver, I
actually have  had exactly the opposite advice [1]. I am not convinced
people actually want to do that.

>> Thats the idea behind this config option. It follows the same design as
>> CONFIG_ARCH_HAS_CPUFREQ, for instance.
> 
> That is entirely contained inside arch/arm and doesn't involve
> drivers.

It actually goes outside arch/arm.

> 
> Jason
> 
> 

[1] - https://patchwork.kernel.org/patch/1185431/

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From konrad.wilk at oracle.com  Tue May  7 09:33:17 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 May 2013 09:33:17 -0400
Subject: [Xen-devel] [PATCH RFC v2 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305071252350.4147@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918270.26321.39.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305071252350.4147@kaball.uk.xensource.com>
Message-ID: <20130507133317.GD31610@phenom.dumpdata.com>

On Tue, May 07, 2013 at 12:58:32PM +0100, Stefano Stabellini wrote:
> On Tue, 7 May 2013, Ian Campbell wrote:
> > On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> > > Register the runstate_memory_area with the hypervisor.
> > > Use pv_time_ops.steal_clock to account for stolen ticks.
> > > 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > ---
> > >  arch/arm/xen/enlighten.c |   23 +++++++++++++++++++++++
> > >  1 files changed, 23 insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > > index ee86bfa..2a5cc82 100644
> > > --- a/arch/arm/xen/enlighten.c
> > > +++ b/arch/arm/xen/enlighten.c
> > > @@ -14,7 +14,10 @@
> > >  #include <xen/xen-ops.h>
> > >  #include <asm/xen/hypervisor.h>
> > >  #include <asm/xen/hypercall.h>
> > > +#include <asm/arch_timer.h>
> > >  #include <asm/system_misc.h>
> > > +#include <asm/paravirt.h>
> > > +#include <linux/jump_label.h>
> > >  #include <linux/interrupt.h>
> > >  #include <linux/irqreturn.h>
> > >  #include <linux/module.h>
> > > @@ -152,6 +155,20 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
> > >  }
> > >  EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
> > >  
> > > +unsigned long long xen_stolen_accounting(int cpu)
> > > +{
> > > +	struct vcpu_runstate_info state;
> > > +
> > > +	if (cpu != get_cpu())
> > 
> > get_cpu disables preempt, so you need a matching put_cpu.
> 
> Oops, thanks.
> 
> 
> > But actually I think you just want smp_processor_id and you probably
> > want the BUG_ON form to get unlikely etc.
> >
> > That said, you don't use cpu for anything else, so why not drop it
> > entirely?
> 
> Ah, that's right, legacy of the past. I'll do that.
> 
> 
> > > +		BUG();
> > > +
> > > +	xen_get_runstate_snapshot(&state);
> > > +
> > > +	WARN_ON(state.state != RUNSTATE_running);
> > > +
> > > +	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
> > > +}
> > > +
> > >  static void __init xen_percpu_init(void *unused)
> > >  {
> > >  	struct vcpu_register_vcpu_info info;
> > > @@ -170,6 +187,8 @@ static void __init xen_percpu_init(void *unused)
> > >  		BUG();
> > >  	per_cpu(xen_vcpu, cpu) = vcpup;
> > >  
> > > +	xen_setup_runstate_info(cpu);
> > > +
> > >  	enable_percpu_irq(xen_events_irq, 0);
> > >  }
> > >  
> > > @@ -301,6 +320,10 @@ static int __init xen_init_events(void)
> > >  
> > >  	on_each_cpu(xen_percpu_init, NULL, 0);
> > >  
> > > +	pv_time_ops.steal_clock = xen_stolen_accounting;
> > > +	static_key_slow_inc(&paravirt_steal_enabled);
> > > +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> > 
> > We don't seem to do this on x86 -- is that a bug on x86 on Xen?
> 
> On x86 we do all the accounting in do_stolen_accounting, called from our
> own interrupt handler (xen_timer_interrupt).
> I don't think we would gain anything by using the common infrastructure,
> we would actually loose the idle ticks accounting we do there.
> 
> Speaking of which, I don't think that pv_time_ops.steal_clock would
> properly increase CPUTIME_IDLE the way we do in do_stolen_accounting.
> 
> How much of an issue is that?

Well, if you look in https://git.kernel.org/cgit/linux/kernel/git/konrad/xen.git/log/?h=devel/pvtime.v1.1
I tried to do use those two asm goto keys but it all started complaining
to me during bootup with some WARNs. Never figured out why, but if somebody
is interested in taking a look ...


From stefano.stabellini at eu.citrix.com  Tue May  7 09:34:59 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 7 May 2013 14:34:59 +0100
Subject: [Xen-devel] [PATCH RFC v2 2/4] arm: introduce CONFIG_PARAVIRT
 and pv_time_ops
In-Reply-To: <1367931376.26321.117.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918609.26321.43.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305071301040.4147@kaball.uk.xensource.com>
 <1367931376.26321.117.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305071433560.4147@kaball.uk.xensource.com>

On Tue, 7 May 2013, Ian Campbell wrote:
> On Tue, 2013-05-07 at 13:15 +0100, Stefano Stabellini wrote:
> > On Tue, 7 May 2013, Ian Campbell wrote:
> > > On Mon, 2013-05-06 at 15:51 +0100, Stefano Stabellini wrote:
> > > > Introduce CONFIG_PARAVIRT on ARM.
> > > 
> > > What about PARAVIRT_TIME_ACCOUNTING? I'm not sure what it is but it
> > > looks like a more lightweight version of pv stolen time?
> >  
> > PARAVIRT_TIME_ACCOUNTING selects PARAVIRT on x86 :-)
> 
> Ah, that's maybe what confused me.
> 
> TBH its not at all clear to me what distinction the core code is trying
> to make with those two options, but do we not also want/need
> PARAVIRT_TIME_ACCOUNTING? Having reread the help text it seems to be
> some sort of "more accurate" accounting?

It is not clear to me either.
I think that you are right, we probably want PARAVIRT_TIME_ACCOUNTING too.


From lorenzo.pieralisi at arm.com  Tue May  7 09:49:44 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Tue, 7 May 2013 14:49:44 +0100
Subject: [RFC PATCH v2] drivers: bus: add ARM CCI support
In-Reply-To: <alpine.LFD.2.03.1305011239240.11070@syhkavp.arg>
References: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
 <alpine.LFD.2.03.1305011239240.11070@syhkavp.arg>
Message-ID: <20130507134943.GB19477@e102568-lin.cambridge.arm.com>

On Mon, May 06, 2013 at 04:05:28PM +0100, Nicolas Pitre wrote:
> Review comments below.

Thanks Nico.

> On Wed, 1 May 2013, Lorenzo Pieralisi wrote:
> 
> > index 0000000..fb9e8e0
> > --- /dev/null
> > +++ b/drivers/bus/arm-cci.c
> > @@ -0,0 +1,372 @@
> > +/*
> > + * CCI cache coherent interconnect driver
> > + *
> > + * Copyright (C) 2013 ARM Ltd.
> > + * Author: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/arm-cci.h>
> > +#include <linux/device.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include <asm/cacheflush.h>
> > +#include <asm/dt_affinity.h>
> > +#include <asm/outercache.h>
> 
> You don't need this include anymore.

True.

> > +#include <asm/smp_plat.h>
> > +
> > +#define DRIVER_NAME          "CCI"
> > +
> > +#define CCI_PORT_CTRL                0x0
> > +#define CCI_CTRL_STATUS              0xc
> > +
> > +#define CCI_ENABLE_SNOOP_REQ 0x1
> > +#define CCI_ENABLE_DVM_REQ   0x2
> > +#define CCI_ENABLE_REQ               (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
> > +
> > +struct cci_nb_ports {
> > +     unsigned int nb_ace;
> > +     unsigned int nb_ace_lite;
> > +};
> > +
> > +enum cci_ace_port_type {
> > +     ACE_INVALID_PORT = 0x0,
> > +     ACE_PORT,
> > +     ACE_LITE_PORT,
> > +};
> > +
> > +struct cci_ace_port {
> > +     void __iomem *base;
> > +     int type;
> 
> You could use: enum cci_ace_port_type type;

Ok.

[...]

> > + * Disabling a CCI port for a CPU implies disabling the CCI port
> > + * controlling that CPU cluster. Code disabling CPU CCI ports
> > + * must make sure that the CPU running the code is the last active CPU
> > + * in the cluster ie all other CPUs are quiescent in a low power state.
> > + */
> > +int notrace cci_disable_port_by_cpu(u64 mpidr)
> > +{
> > +     int cpu = get_logical_index(mpidr & MPIDR_HWID_BITMASK);
> 
> This is dangerous.  Same reasoning for not using cpu_relax() above
> should apply here too.  Better avoid any external calls and cache things
> locally by marking cpu_port[] entries with MPIDR values directly.

Ok, I will stash them at boot.

> Furthermore, get_logical_index() might not be reliable when the cache or
> local coherency is off.  We'd have to flush all the data it might access
> to RAM just like it is done for our very own data structures in this
> code, but starting doing that outside of this driver would become rather
> ugly.

That's correct.

> > +     if (cpu < 0 || cpu_port[cpu] == INVALID_PORT_IDX)
> > +             return -ENODEV;
> > +     cci_port_control(cpu_port[cpu], false);
> > +     return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
> > +
> > +/*
> > + * __cci_control_port_by_device()
> > + *   @dn = device node pointer of the device whose CCI port should be
> > + *         controlled
> > + *   @enable = if true enables the port, if false disables it
> > + *   Returns:
> > + *           0 on success
> > + *           -ENODEV on port look-up failure
> > + */
> > +int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
> > +{
> > +     int port;
> > +
> > +     if (!dn)
> > +             return -ENODEV;
> > +
> > +     port = __cci_ace_get_port(dn, ACE_LITE_PORT);
> > +     if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
> > +                             dn->full_name))
> > +             return -ENODEV;
> > +     cci_port_control(port, enable);
> > +     return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
> > +
> > +/*
> > + * __cci_control_port_by_index()
> > + *   @port = port index previously retrieved with cci_ace_get_port()
> > + *   @enable = if true enables the port, if false disables it
> > + *   Returns:
> > + *           0 on success
> > + *           -ENODEV on port index out of range
> > + *           -EPERM if operation carried out on an ACE PORT
> > + */
> > +int notrace __cci_control_port_by_index(u32 port, bool enable)
> > +{
> > +     if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
> > +             return -ENODEV;
> > +     /*
> > +      * CCI control for ports connected to CPUS is extremely fragile
> > +      * and must be made to go through a specific and controlled
> > +      * interface (ie cci_disable_port_by_cpu(); control by general purpose
> > +      * indexing is therefore disabled for ACE ports.
> > +      */
> > +     if (ports[port].type == ACE_PORT)
> > +             return -EPERM;
> > +
> > +     cci_port_control(port, enable);
> > +     return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
> > +
> > +static const struct cci_nb_ports cci400_ports = {
> > +     .nb_ace = 2,
> > +     .nb_ace_lite = 3
> > +};
> > +
> > +static const struct of_device_id arm_cci_matches[] = {
> > +     {.compatible = "arm,cci-400", .data = &cci400_ports },
> > +     {},
> > +};
> > +
> > +static int __init cci_driver_probe(struct platform_device *pdev)
> > +{
> > +     const struct of_device_id *match;
> > +     struct cci_nb_ports const *cci_config;
> > +     int ret, i, nb_ace = 0, nb_ace_lite = 0;
> > +     struct device_node *np, *cp;
> > +     const char *match_str;
> > +     struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +
> > +     match = of_match_device(arm_cci_matches, &pdev->dev);
> > +
> > +     if (!match)
> > +             return -ENODEV;
> > +
> > +     cci_config = (struct cci_nb_ports const *)match->data;
> > +     nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
> > +     ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
> > +     if (!ports)
> > +             return -ENOMEM;
> > +
> > +     np = pdev->dev.of_node;
> > +
> > +     cci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
> > +
> > +     if (!cci_ctrl_base) {
> > +             dev_err(&pdev->dev, "unable to ioremap CCI ctrl\n");
> > +             ret = -ENXIO;
> > +             goto memalloc_err;
> > +     }
> > +
> > +     for_each_child_of_node(np, cp) {
> > +             i = nb_ace + nb_ace_lite;
> > +
> > +             if (i >= nb_cci_ports)
> > +                     break;
> > +
> > +             if (of_property_read_string(cp, "interface-type",
> > +                                         &match_str)) {
> > +                     dev_err(&pdev->dev, "node %s missing interface-type property\n",
> > +                               cp->full_name);
> > +                     continue;
> > +             }
> > +
> > +             if (strcmp(match_str, "ace")
> > +                             && strcmp(match_str, "ace-lite")) {
> > +                     dev_err(&pdev->dev, "node %s containing invalid interface-type property, skipping it\n",
> > +                                     cp->full_name);
> > +                     continue;
> > +             }
> > +
> > +             if (of_address_to_resource(cp, 0, res)) {
> > +                     dev_err(&pdev->dev, "node %s failure in retrieving resources\n",
> > +                             cp->full_name);
> > +                     continue;
> > +             }
> > +
> > +             ports[i].base = devm_request_and_ioremap(&pdev->dev, res);
> > +
> > +             if (!ports[i].base) {
> > +                     dev_err(&pdev->dev, "unable to ioremap CCI port %d\n",
> > +                                         i);
> > +                     continue;
> > +             }
> > +
> > +             if (!strcmp(match_str, "ace")) {
> > +                     if (WARN_ON(nb_ace >= cci_config->nb_ace))
> > +                             continue;
> > +                     ports[i].type = ACE_PORT;
> > +                     ++nb_ace;
> > +             } else if (!strcmp(match_str, "ace-lite")) {
> > +                     if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
> > +                             continue;
> > +                     ports[i].type = ACE_LITE_PORT;
> > +                     ++nb_ace_lite;
> > +             }
> > +             ports[i].dn = cp;
> > +     }
> > +      /* initialize a stashed array of ACE ports to speed-up look-up */
> > +     cci_ace_init_ports();
> > +
> > +     /*
> > +      * Multi-cluster systems may need this data when non-coherent, during
> > +      * cluster power-up/power-down. Make sure it reaches main memory.
> > +      */
> > +     sync_cache_w(&cci_ctrl_base);
> > +     __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
> 
> This is not enough to flush the cache for the memory referenced by the
> ports pointer.  The pointer value itself has to be flushed to RAM as
> well.

Gah, you are right.

> > +     __sync_cache_range_w(cpu_port, sizeof cpu_port);
> 
> You might be able to use sync_cache_w(&cpu_port) here instead given it
> is a fixed size array object.

Yes.

> > +     dev_info(&pdev->dev, "ARM CCI driver probed\n");
> > +     return 0;
> > +
> > +memalloc_err:
> > +
> > +     kfree(ports);
> > +     return ret;
> > +}
> > +
> > +static struct platform_driver cci_platform_driver = {
> > +     .driver = {
> > +                .owner = THIS_MODULE,
> > +                .name = DRIVER_NAME,
> > +                .of_match_table = arm_cci_matches,
> > +     },
> > +};
> > +/*
> > + * CCI is inherently a non-hotpluggable device, since it represents
> > + * the CPUs access point to the interconnect system.
> > + */
> > +static int __init cci_init(void)
> > +{
> > +     return platform_driver_probe(&cci_platform_driver, cci_driver_probe);
> > +}
> > +
> > +module_init(cci_init);
> 
> When compiled in, module_init() is translated into device_initcall().
> This is way too late for bringing up secondary CPUs during boot via the
> MCPM layer.  That is not an issue as far as the code presented here is
> concerned since there is no integration with MCPM yet, but eventually
> we'd want the MCPM power_up_setup method to integrate with the port
> discovery performed here instead of having them hardcoded in the
> assembly code.  This means it would have to become early_initcall()
> instead.  And at that point the driver infrastructure isn't fully
> operational, meaning that driver_probe() won't be usable either (looking
> at what we did to the TC2 spc init code is a good example of what I mean
> here).

Yes, I thought about that. This means that CCI driver should not rely on
platform device structs, and yes I can mirror SPC probing code to take care
of ordering issues. I am quite tempted to remove the platform device/driver
infrastructure altogether and just rely on the DT layer (as GIC, PL310
do) to initialize CCI. What do you think ? I think I will leave the
platform driver infrastructure, and at probe it will check if data
structures have already been initialized by an exported function, say:

cci_of_init()

if the data structures are already initialized basically the probe
function will do precious little and just succeeds otherwise it will
initialize the driver as it does now.

Is there really a point in having the CCI driver represented as a
platform driver ? Not sure at all.

Thanks,
Lorenzo



From stefano.stabellini at eu.citrix.com  Tue May  7 09:49:46 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 7 May 2013 14:49:46 +0100
Subject: [Xen-devel] [PATCH RFC v2 4/4] xen/arm: account for stolen ticks
In-Reply-To: <1367931401.26321.118.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1305061532310.4756@kaball.uk.xensource.com>
 <1367851878-21629-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <1367918270.26321.39.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1305071252350.4147@kaball.uk.xensource.com>
 <1367931401.26321.118.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305071448390.4147@kaball.uk.xensource.com>

On Tue, 7 May 2013, Ian Campbell wrote:
> > > > @@ -301,6 +320,10 @@ static int __init xen_init_events(void)
> > > >  
> > > >  	on_each_cpu(xen_percpu_init, NULL, 0);
> > > >  
> > > > +	pv_time_ops.steal_clock = xen_stolen_accounting;
> > > > +	static_key_slow_inc(&paravirt_steal_enabled);
> > > > +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> > > 
> > > We don't seem to do this on x86 -- is that a bug on x86 on Xen?
> > 
> > On x86 we do all the accounting in do_stolen_accounting, called from our
> > own interrupt handler (xen_timer_interrupt).
> > I don't think we would gain anything by using the common infrastructure,
> > we would actually loose the idle ticks accounting we do there.
> > 
> > Speaking of which, I don't think that pv_time_ops.steal_clock would
> > properly increase CPUTIME_IDLE the way we do in do_stolen_accounting.
> > 
> > How much of an issue is that?
> 
> Doesn't the generic account_idle_time handle this?

AFAICT only if the rq is idle, while do_stolen_accounting would account
for ticks in RUNSTATE_blocked


From pavel at denx.de  Tue May  7 09:57:52 2013
From: pavel at denx.de (Pavel Machek)
Date: Tue, 7 May 2013 15:57:52 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <201305062324.17080.arnd@arndb.de>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de>
 <20130506155304.GA6645@amd.pavel.ucw.cz>
 <201305062324.17080.arnd@arndb.de>
Message-ID: <20130507135752.GA3500@amd.pavel.ucw.cz>

On Mon 2013-05-06 23:24:16, Arnd Bergmann wrote:
> On Monday 06 May 2013, Pavel Machek wrote:
> > On Mon 2013-05-06 15:45:22, Arnd Bergmann wrote:
> > > On Monday 06 May 2013, Pavel Machek wrote:
> > > > 
> > > > Hi!
> > > > 
> > > > Ping? Previous version was tested by Dinh, and this one is based on
> > > > Jamie's updates, so I assume it is acceptable for him, too.
> > > > 
> > > > It brings two platforms closer together, and makes time actually work
> > > > on socfpga. It would be good to get it applied.
> > > 
> > > Who should apply it? I guess it needs to go through arm-soc with all the
> > > other clocksource changes already queued up there. Can we have an Ack
> > > from Jamie and from the clocksource maintainers?
> > 
> > Well, changes to arch/arm/mach-picoxcell are single line (and that's a
> > cleanup of duplicate include). 
> 
> The point is that Jamie had comments on the earlier version, so it would
> be good to see his Ack on the current one.

He sent his Ack this morning.

> > So I guess it should go through the timekeeping tree...?
> 
> I would prefer that, but we can also take it through arm-soc, it doesn't
> really matter.

I see no response from timekeeping people... so if you could take it,
that would be great.

Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From itooo at itooo.com  Tue May  7 10:14:01 2013
From: itooo at itooo.com (Greg)
Date: Tue, 07 May 2013 16:14:01 +0200
Subject: MVNETA irq with backport-3.8
Message-ID: <51890C29.8000504@itooo.com>

Thomas, Willy,

I'm trying to boot off the the backport-3.-8 kernel with armada-xp-db DT 
file.

When eth0 is brought up (I'm booting on NFS) the mvneta driver fails in 
mvneta_open, with the following error :
> mvneta d0070000.ethernet eth0: cannot request irq 25

The oddness is this is not the actual IRQ to be requested, and the DTS 
files explicitly specify the IRQ is 8 for this device.

I'm not familiar with the DT system, where should I start looking to 
find the source of the problem ?

Thanks!


From holt at sgi.com  Tue May  7 10:39:44 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:44 -0500
Subject: [PATCH -v8 00/11] Shutdown from reboot_cpuid without stopping other
 cpus.
Message-ID: <1367937595-32241-1-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.


Changes since -v7.
 - Fixed authorship for first patch.

 - Rebased to Linus' current tree (51a26ae7a).

Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From holt at sgi.com  Tue May  7 10:39:45 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:45 -0500
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-2-git-send-email-holt@sgi.com>

From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v6:
 - Added a #define for non-hotplug case.
---
 include/linux/cpu.h |  3 +++
 kernel/cpu.c        | 27 +++++++++------------------
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..3e450c0 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -141,6 +141,8 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
 }
 #endif
 
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 int cpu_up(unsigned int cpu);
 void notify_cpu_starting(unsigned int cpu);
 extern void cpu_maps_update_begin(void);
@@ -148,6 +150,7 @@ extern void cpu_maps_update_done(void);
 
 #else	/* CONFIG_SMP */
 
+#define cpu_hotplug_disable()	do { } while (0)
 #define cpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 
 static inline int register_cpu_notifier(struct notifier_block *nb)
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..28769f5 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -541,29 +541,20 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
  */
-void cpu_hotplug_disable_before_freeze(void)
+void cpu_hotplug_disable(void)
 {
 	cpu_maps_update_begin();
 	cpu_hotplug_disabled = 1;
 	cpu_maps_update_done();
 }
 
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
+void cpu_hotplug_enable(void)
 {
 	cpu_maps_update_begin();
 	cpu_hotplug_disabled = 0;
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:47 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:47 -0500
Subject: [PATCH -v8 03/11] Remove -stable friendly PF_THREAD_BOUND define
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-4-git-send-email-holt@sgi.com>

Remove the prior patch's #define for easier backporting to the stable
releases.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 kernel/sys.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index 14640d7..91d2d4e 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,11 +362,6 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
-/* Add backwards compatibility for stable trees. */
-#ifndef PF_NO_SETAFFINITY
-#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
-#endif
-
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:46 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:46 -0500
Subject: [PATCH -v8 02/11] Migrate shutdown/reboot to boot cpu.
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-3-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
boot cpu and then continuing with shutdown/reboot.

This also has the effect of not breaking x86's command line parameter for
specifying the reboot cpu.  Note, this code was shamelessly copied from
arch/x86/kernel/reboot.c with bits removed pertaining to the reboot_cpu
command line parameter.

Signed-off-by: Robin Holt <holt at sgi.com>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v6:
 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
 - Fixup s/reboot_cpu_id/reboot_cpu/
---
 kernel/sys.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c7..14640d7 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int reboot_cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(reboot_cpu))
+		reboot_cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu));
+}
+
 /**
  *	kernel_restart - reboot the system
  *	@cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
 	kernel_restart_prepare(cmd);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
 		printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
 	kernel_shutdown_prepare(SYSTEM_HALT);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
 	if (pm_power_off_prepare)
 		pm_power_off_prepare();
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:49 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:49 -0500
Subject: [PATCH -v8 05/11] checkpatch.pl the new kernel/reboot.c file.
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-6-git-send-email-holt@sgi.com>

Get the new file to pass scripts/checkpatch.pl

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since v6:
 - Removed last remaining line length warning.
---
 include/linux/reboot.h |  2 +-
 kernel/reboot.c        | 28 +++++++++++++---------------
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 23b3630..c6eba21 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -26,7 +26,7 @@ extern void machine_shutdown(void);
 struct pt_regs;
 extern void machine_crash_shutdown(struct pt_regs *);
 
-/* 
+/*
  * Architecture independent implemenations of sys_reboot commands.
  */
 
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 169f0b6..0a97794 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -4,6 +4,8 @@
  *  Copyright (C) 2013  Linus Torvalds
  */
 
+#define pr_fmt(fmt)	"reboot: " fmt
+
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -114,9 +116,9 @@ void kernel_restart(char *cmd)
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
+		pr_emerg("Restarting system\n");
 	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+		pr_emerg("Restarting system with command '%s'\n", cmd);
 	kmsg_dump(KMSG_DUMP_RESTART);
 	machine_restart(cmd);
 }
@@ -125,7 +127,7 @@ EXPORT_SYMBOL_GPL(kernel_restart);
 static void kernel_shutdown_prepare(enum system_states state)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
 	usermodehelper_disable();
 	device_shutdown();
@@ -140,11 +142,10 @@ void kernel_halt(void)
 	kernel_shutdown_prepare(SYSTEM_HALT);
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
+	pr_emerg("System halted\n");
 	kmsg_dump(KMSG_DUMP_HALT);
 	machine_halt();
 }
-
 EXPORT_SYMBOL_GPL(kernel_halt);
 
 /**
@@ -159,7 +160,7 @@ void kernel_power_off(void)
 		pm_power_off_prepare();
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
+	pr_emerg("Power down\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
 	machine_power_off();
 }
@@ -188,10 +189,10 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 
 	/* For safety, we require "magic" arguments. */
 	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			(magic2 != LINUX_REBOOT_MAGIC2 &&
+			magic2 != LINUX_REBOOT_MAGIC2A &&
 			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
+			magic2 != LINUX_REBOOT_MAGIC2C))
 		return -EINVAL;
 
 	/*
@@ -234,7 +235,8 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 		break;
 
 	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+		ret = strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1);
+		if (ret < 0) {
 			ret = -EFAULT;
 			break;
 		}
@@ -282,7 +284,6 @@ void ctrl_alt_del(void)
 	else
 		kill_cad_pid(SIGINT, 1);
 }
-	
 
 char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
 
@@ -301,14 +302,11 @@ static int __orderly_poweroff(bool force)
 		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
 		argv_free(argv);
 	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
 		ret = -ENOMEM;
 	}
 
 	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
+		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 		/*
 		 * I guess this should try to kick off some daemon to sync and
 		 * poweroff asap.  Or not even bother syncing if we're doing an
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:52 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:52 -0500
Subject: [PATCH -v8 08/11] arm,
 Remove unused restart_mode fields from some arm subarchs
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-9-git-send-email-holt@sgi.com>

These restart_mode fields are not used at all.  Remove them to make
moving the reboot= cmdline options to the general kernel easier.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/mach-ebsa110/core.c | 1 -
 arch/arm/mach-pxa/mioa701.c  | 1 -
 arch/arm/mach-pxa/spitz.c    | 3 ---
 arch/arm/mach-pxa/tosa.c     | 1 -
 4 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..69a9d5d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
 	.atag_offset	= 0x400,
 	.reserve_lp0	= 1,
 	.reserve_lp2	= 1,
-	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
 	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b9..dbea67a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -756,7 +756,6 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
 	.map_io		= &pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
 	.init_irq	= &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..c3c0042 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,7 +979,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -993,7 +992,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -1007,7 +1005,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e..a41992f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -969,7 +969,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-	.restart_mode	= 'g',
 	.fixup          = fixup_tosa,
 	.map_io         = pxa25x_map_io,
 	.nr_irqs	= TOSA_NR_IRQS,
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:51 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:51 -0500
Subject: [PATCH -v8 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-8-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/unicore32/kernel/process.c | 10 +++++-----
 arch/unicore32/kernel/setup.h   |  2 +-
 arch/unicore32/mm/mmu.c         |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index c944769..9dc6e48 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,14 +51,14 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static char reboot_mode = 'h';
+static enum reboot_mode reboot_mode;
 
 int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_WARM;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
@@ -88,7 +88,7 @@ void machine_restart(char *cmd)
 	 * we may need it to insert some 1:1 mappings so that
 	 * soft boot works.
 	 */
-	setup_mm_for_reboot(reboot_mode);
+	setup_mm_for_reboot();
 
 	/* Clean and invalidate caches */
 	flush_cache_all();
@@ -102,7 +102,7 @@ void machine_restart(char *cmd)
 	/*
 	 * Now handle reboot code.
 	 */
-	if (reboot_mode == 's') {
+	if (reboot_mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index 30f749d..f5c51b8 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
 extern void pci_puv3_preinit(void);
 extern void __init puv3_init_gpio(void);
 
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 
 extern char __stubs_start[], __stubs_end[];
 extern char __vectors_start[], __vectors_end[];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index 43c20b4..4f5a532 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -445,7 +445,7 @@ void __init paging_init(void)
  * the user-mode pages.  This will then ensure that we have predictable
  * results when turning the mmu off
  */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 	unsigned long base_pmdval;
 	pgd_t *pgd;
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:50 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:50 -0500
Subject: [PATCH -v8 06/11] x86,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-7-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Miguel Boton <mboton.lkml at gmail.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/x86/kernel/reboot.c | 12 +++++++-----
 include/linux/reboot.h   |  5 +++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 76fa1e9..d42e3b2 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,7 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static int reboot_mode;
+static enum reboot_mode reboot_mode = REBOOT_COLD;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -88,11 +88,11 @@ static int __init reboot_setup(char *str)
 
 		switch (*str) {
 		case 'w':
-			reboot_mode = 0x1234;
+			reboot_mode = REBOOT_WARM;
 			break;
 
 		case 'c':
-			reboot_mode = 0;
+			reboot_mode = REBOOT_COLD;
 			break;
 
 #ifdef CONFIG_SMP
@@ -536,6 +536,7 @@ static void native_machine_emergency_restart(void)
 	int i;
 	int attempt = 0;
 	int orig_reboot_type = reboot_type;
+	unsigned short mode;
 
 	if (reboot_emergency)
 		emergency_vmx_disable_all();
@@ -543,7 +544,8 @@ static void native_machine_emergency_restart(void)
 	tboot_shutdown(TB_SHUTDOWN_REBOOT);
 
 	/* Tell the BIOS if we want cold or warm reboot */
-	*((unsigned short *)__va(0x472)) = reboot_mode;
+	mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
+	*((unsigned short *)__va(0x472)) = mode;
 
 	for (;;) {
 		/* Could also try the reset bit in the Hammer NB */
@@ -585,7 +587,7 @@ static void native_machine_emergency_restart(void)
 
 		case BOOT_EFI:
 			if (efi_enabled(EFI_RUNTIME_SERVICES))
-				efi.reset_system(reboot_mode ?
+				efi.reset_system(reboot_mode == REBOOT_WARM ?
 						 EFI_RESET_WARM :
 						 EFI_RESET_COLD,
 						 EFI_SUCCESS, 0, NULL);
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index c6eba21..37d56c3 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -10,6 +10,11 @@
 #define SYS_HALT	0x0002	/* Notify of system halt */
 #define SYS_POWER_OFF	0x0003	/* Notify of system power off */
 
+enum reboot_mode {
+	REBOOT_COLD = 0,
+	REBOOT_WARM,
+};
+
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
 
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:53 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:53 -0500
Subject: [PATCH -v8 09/11] arm,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-10-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/include/asm/mach/arch.h   | 3 ++-
 arch/arm/kernel/process.c          | 8 ++++----
 arch/arm/kernel/setup.c            | 6 +++---
 arch/arm/mach-footbridge/cats-hw.c | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..e2b551e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -9,6 +9,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 
 struct tag;
 struct meminfo;
@@ -39,7 +40,7 @@ struct machine_desc {
 	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-	char			restart_mode;	/* default restart mode	*/
+	enum reboot_mode	reboot_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..161e66c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -174,14 +174,14 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-static char reboot_mode = 'h';
+enum reboot_mode reboot_mode;
 
-int __init reboot_setup(char *str)
+static int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_WARM;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 728007c..465e878 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -72,7 +72,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -758,8 +758,8 @@ void __init setup_arch(char **cmdline_p)
 
 	setup_dma_zone(mdesc);
 
-	if (mdesc->restart_mode)
-		reboot_setup(&mdesc->restart_mode);
+	if (mdesc->reboot_mode != REBOOT_COLD)
+		reboot_mode = mdesc->reboot_mode;
 
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09..14c9cb9 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
 	/* Maintainer: Philip Blundell */
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
+	.reboot_mode	= REBOOT_WARM,
 	.fixup		= fixup_cats,
 	.map_io		= footbridge_map_io,
 	.init_irq	= footbridge_init_irq,
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:55 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:55 -0500
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic kernel.
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-12-git-send-email-holt@sgi.com>

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 Documentation/kernel-parameters.txt      |  18 ++++-
 arch/arm/kernel/process.c                |  10 ---
 arch/unicore32/kernel/process.c          |  10 ---
 arch/x86/include/asm/emergency-restart.h |  12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |   2 +-
 arch/x86/kernel/reboot.c                 | 111 +------------------------------
 include/linux/reboot.h                   |  17 +++++
 kernel/reboot.c                          |  90 ++++++++++++++++++++++++-
 8 files changed, 125 insertions(+), 145 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c3bfacb..87e8dea 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2677,9 +2677,21 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old]] \
+				[,] s[mp]#### \
+				[,b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[,f[orce]
+			Format (all other archs):
+				[s[oft] | h[ard]] \
+				[,b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[,f[orce]]
+			Where reboot_mode is one of warm (soft) or cold,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					(in decimal) to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 58c0d7a..304b102 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_WARM;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 9dc6e48..fdb8e79 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_WARM;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index d42e3b2..563ed91 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,22 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode = REBOOT_COLD;
-enum reboot_type reboot_type = BOOT_ACPI;
-int reboot_force;
-
-/*
- * This variable is used privately to keep track of whether or not
- * reboot_type is still set to its default value (i.e., reboot= hasn't
- * been set on the command line).  This is needed so that we can
- * suppress DMI scanning for reboot quirks.  Without it, it's
- * impossible to override a faulty reboot quirk without recompiling.
- */
-static int reboot_default = 1;
-
-#ifdef CONFIG_SMP
-static int reboot_cpu = -1;
-#endif
 
 /*
  * This is set if we need to go through the 'emergency' path.
@@ -64,79 +48,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +527,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 26cf11b..bc77231 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,23 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 0a97794..e0f640b 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -87,7 +88,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu = 0;
+	int reboot_cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -343,3 +344,90 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+int reboot_default;
+enum reboot_mode reboot_mode = REBOOT_COLD;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
+/*
+ * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
+ * warm   Don't set the cold reboot flag
+ * cold   Set the cold reboot flag
+ * bios   Reboot by jumping through the BIOS
+ * smp    Reboot by executing reset on BSP or other CPU
+ * triple Force a triple fault (init)
+ * kbd    Use the keyboard controller. cold reset (default)
+ * acpi   Use the RESET_REG in the FADT
+ * efi    Use efi reset_system runtime service
+ * pci    Use the so-called "PCI reset register", CF9
+ * force  Avoid anything that could hang.
+ */
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+#ifdef CONFIG_SMP
+		case 's':
+			if (isdigit(*(str+1))) {
+				reboot_cpu = (int) (*(str+1) - '0');
+				if (isdigit(*(str+2)))
+					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
+			}
+			/*
+			 * We will leave sorting out the final value
+			 * when we are ready to reboot, since we might not
+			 * have detected BSP APIC ID or smp_num_cpu
+			 */
+			break;
+#endif /* CONFIG_SMP */
+
+#else
+		case 's':
+			reboot_mode = REBOOT_WARM;
+		case 'h':
+			reboot_mode = REBOOT_COLD;
+		case 'g':
+			reboot_mode = REBOOT_GPIO;
+#endif
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:48 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:48 -0500
Subject: [PATCH -v8 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-5-git-send-email-holt@sgi.com>

This patch is preparatory.  It moves reboot related syscall, etc
functions from kernel/sys.c to kernel/reboot.c.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v6:
 - Add include of linux/uaccess.h to allow building on arm.
---
 kernel/Makefile |   2 +-
 kernel/reboot.c | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/sys.c    | 331 -----------------------------------------------------
 3 files changed, 348 insertions(+), 332 deletions(-)
 create mode 100644 kernel/reboot.c

diff --git a/kernel/Makefile b/kernel/Makefile
index 271fd31..470839d 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y     = fork.o exec_domain.o panic.o printk.o \
 	    rcupdate.o extable.o params.o posix-timers.o \
 	    kthread.o wait.o sys_ni.o posix-cpu-timers.o mutex.o \
 	    hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-	    notifier.o ksysfs.o cred.o \
+	    notifier.o ksysfs.o cred.o reboot.o \
 	    async.o range.o groups.o lglock.o smpboot.o
 
 ifdef CONFIG_FUNCTION_TRACER
diff --git a/kernel/reboot.c b/kernel/reboot.c
new file mode 100644
index 0000000..169f0b6
--- /dev/null
+++ b/kernel/reboot.c
@@ -0,0 +1,347 @@
+/*
+ *  linux/kernel/reboot.c
+ *
+ *  Copyright (C) 2013  Linus Torvalds
+ */
+
+#include <linux/export.h>
+#include <linux/kexec.h>
+#include <linux/kmod.h>
+#include <linux/kmsg_dump.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h>
+#include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
+
+/*
+ * this indicates whether you can reboot with ctrl-alt-del: the default is yes
+ */
+
+int C_A_D = 1;
+struct pid *cad_pid;
+EXPORT_SYMBOL(cad_pid);
+
+/*
+ * If set, this is used for preparing the system to power off.
+ */
+
+void (*pm_power_off_prepare)(void);
+
+/**
+ *	emergency_restart - reboot the system
+ *
+ *	Without shutting down any hardware or taking any locks
+ *	reboot the system.  This is called when we know we are in
+ *	trouble so this is our best effort to reboot.  This is
+ *	safe to call in interrupt context.
+ */
+void emergency_restart(void)
+{
+	kmsg_dump(KMSG_DUMP_EMERG);
+	machine_emergency_restart();
+}
+EXPORT_SYMBOL_GPL(emergency_restart);
+
+void kernel_restart_prepare(char *cmd)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
+	system_state = SYSTEM_RESTART;
+	usermodehelper_disable();
+	device_shutdown();
+}
+
+/**
+ *	register_reboot_notifier - Register function to be called at reboot time
+ *	@nb: Info about notifier function to be called
+ *
+ *	Registers a function with the list of functions
+ *	to be called at reboot time.
+ *
+ *	Currently always returns zero, as blocking_notifier_chain_register()
+ *	always returns zero.
+ */
+int register_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(register_reboot_notifier);
+
+/**
+ *	unregister_reboot_notifier - Unregister previously registered reboot notifier
+ *	@nb: Hook to be unregistered
+ *
+ *	Unregisters a previously registered reboot
+ *	notifier function.
+ *
+ *	Returns zero on success, or %-ENOENT on failure.
+ */
+int unregister_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(unregister_reboot_notifier);
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int reboot_cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(reboot_cpu))
+		reboot_cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu));
+}
+
+/**
+ *	kernel_restart - reboot the system
+ *	@cmd: pointer to buffer containing command to execute for restart
+ *		or %NULL
+ *
+ *	Shutdown everything and perform a clean reboot.
+ *	This is not safe to call in interrupt context.
+ */
+void kernel_restart(char *cmd)
+{
+	kernel_restart_prepare(cmd);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	if (!cmd)
+		printk(KERN_EMERG "Restarting system.\n");
+	else
+		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+	kmsg_dump(KMSG_DUMP_RESTART);
+	machine_restart(cmd);
+}
+EXPORT_SYMBOL_GPL(kernel_restart);
+
+static void kernel_shutdown_prepare(enum system_states state)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list,
+		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+	system_state = state;
+	usermodehelper_disable();
+	device_shutdown();
+}
+/**
+ *	kernel_halt - halt the system
+ *
+ *	Shutdown everything and perform a clean system halt.
+ */
+void kernel_halt(void)
+{
+	kernel_shutdown_prepare(SYSTEM_HALT);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "System halted.\n");
+	kmsg_dump(KMSG_DUMP_HALT);
+	machine_halt();
+}
+
+EXPORT_SYMBOL_GPL(kernel_halt);
+
+/**
+ *	kernel_power_off - power_off the system
+ *
+ *	Shutdown everything and perform a clean system power_off.
+ */
+void kernel_power_off(void)
+{
+	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
+	if (pm_power_off_prepare)
+		pm_power_off_prepare();
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "Power down.\n");
+	kmsg_dump(KMSG_DUMP_POWEROFF);
+	machine_power_off();
+}
+EXPORT_SYMBOL_GPL(kernel_power_off);
+
+static DEFINE_MUTEX(reboot_mutex);
+
+/*
+ * Reboot system call: for obvious reasons only root may call it,
+ * and even root needs to set up some magic numbers in the registers
+ * so that some mistake won't make this reboot the whole machine.
+ * You can also set the meaning of the ctrl-alt-del-key here.
+ *
+ * reboot doesn't sync: do that yourself before calling this.
+ */
+SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
+		void __user *, arg)
+{
+	struct pid_namespace *pid_ns = task_active_pid_ns(current);
+	char buffer[256];
+	int ret = 0;
+
+	/* We only trust the superuser with rebooting the system. */
+	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
+		return -EPERM;
+
+	/* For safety, we require "magic" arguments. */
+	if (magic1 != LINUX_REBOOT_MAGIC1 ||
+	    (magic2 != LINUX_REBOOT_MAGIC2 &&
+	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			magic2 != LINUX_REBOOT_MAGIC2B &&
+	                magic2 != LINUX_REBOOT_MAGIC2C))
+		return -EINVAL;
+
+	/*
+	 * If pid namespaces are enabled and the current task is in a child
+	 * pid_namespace, the command is handled by reboot_pid_ns() which will
+	 * call do_exit().
+	 */
+	ret = reboot_pid_ns(pid_ns, cmd);
+	if (ret)
+		return ret;
+
+	/* Instead of trying to make the power_off code look like
+	 * halt when pm_power_off is not set do it the easy way.
+	 */
+	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
+		cmd = LINUX_REBOOT_CMD_HALT;
+
+	mutex_lock(&reboot_mutex);
+	switch (cmd) {
+	case LINUX_REBOOT_CMD_RESTART:
+		kernel_restart(NULL);
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_ON:
+		C_A_D = 1;
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_OFF:
+		C_A_D = 0;
+		break;
+
+	case LINUX_REBOOT_CMD_HALT:
+		kernel_halt();
+		do_exit(0);
+		panic("cannot halt");
+
+	case LINUX_REBOOT_CMD_POWER_OFF:
+		kernel_power_off();
+		do_exit(0);
+		break;
+
+	case LINUX_REBOOT_CMD_RESTART2:
+		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+			ret = -EFAULT;
+			break;
+		}
+		buffer[sizeof(buffer) - 1] = '\0';
+
+		kernel_restart(buffer);
+		break;
+
+#ifdef CONFIG_KEXEC
+	case LINUX_REBOOT_CMD_KEXEC:
+		ret = kernel_kexec();
+		break;
+#endif
+
+#ifdef CONFIG_HIBERNATION
+	case LINUX_REBOOT_CMD_SW_SUSPEND:
+		ret = hibernate();
+		break;
+#endif
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&reboot_mutex);
+	return ret;
+}
+
+static void deferred_cad(struct work_struct *dummy)
+{
+	kernel_restart(NULL);
+}
+
+/*
+ * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
+ * As it's called within an interrupt, it may NOT sync: the only choice
+ * is whether to reboot at once, or just ignore the ctrl-alt-del.
+ */
+void ctrl_alt_del(void)
+{
+	static DECLARE_WORK(cad_work, deferred_cad);
+
+	if (C_A_D)
+		schedule_work(&cad_work);
+	else
+		kill_cad_pid(SIGINT, 1);
+}
+	
+
+char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
+
+static int __orderly_poweroff(bool force)
+{
+	char **argv;
+	static char *envp[] = {
+		"HOME=/",
+		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
+		NULL
+	};
+	int ret;
+
+	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
+	if (argv) {
+		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
+		argv_free(argv);
+	} else {
+		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
+					 __func__, poweroff_cmd);
+		ret = -ENOMEM;
+	}
+
+	if (ret && force) {
+		printk(KERN_WARNING "Failed to start orderly shutdown: "
+					"forcing the issue\n");
+		/*
+		 * I guess this should try to kick off some daemon to sync and
+		 * poweroff asap.  Or not even bother syncing if we're doing an
+		 * emergency shutdown?
+		 */
+		emergency_sync();
+		kernel_power_off();
+	}
+
+	return ret;
+}
+
+static bool poweroff_force;
+
+static void poweroff_work_func(struct work_struct *work)
+{
+	__orderly_poweroff(poweroff_force);
+}
+
+static DECLARE_WORK(poweroff_work, poweroff_work_func);
+
+/**
+ * orderly_poweroff - Trigger an orderly system poweroff
+ * @force: force poweroff if command execution fails
+ *
+ * This may be called from any context to trigger a system shutdown.
+ * If the orderly shutdown fails, it will force an immediate shutdown.
+ */
+int orderly_poweroff(bool force)
+{
+	if (force) /* do not override the pending "true" */
+		poweroff_force = true;
+	schedule_work(&poweroff_work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(orderly_poweroff);
diff --git a/kernel/sys.c b/kernel/sys.c
index 91d2d4e..467a18f 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -116,20 +116,6 @@ EXPORT_SYMBOL(fs_overflowuid);
 EXPORT_SYMBOL(fs_overflowgid);
 
 /*
- * this indicates whether you can reboot with ctrl-alt-del: the default is yes
- */
-
-int C_A_D = 1;
-struct pid *cad_pid;
-EXPORT_SYMBOL(cad_pid);
-
-/*
- * If set, this is used for preparing the system to power off.
- */
-
-void (*pm_power_off_prepare)(void);
-
-/*
  * Returns true if current's euid is same as p's uid or euid,
  * or has CAP_SYS_NICE to p's user_ns.
  *
@@ -308,261 +294,6 @@ out_unlock:
 	return retval;
 }
 
-/**
- *	emergency_restart - reboot the system
- *
- *	Without shutting down any hardware or taking any locks
- *	reboot the system.  This is called when we know we are in
- *	trouble so this is our best effort to reboot.  This is
- *	safe to call in interrupt context.
- */
-void emergency_restart(void)
-{
-	kmsg_dump(KMSG_DUMP_EMERG);
-	machine_emergency_restart();
-}
-EXPORT_SYMBOL_GPL(emergency_restart);
-
-void kernel_restart_prepare(char *cmd)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
-	system_state = SYSTEM_RESTART;
-	usermodehelper_disable();
-	device_shutdown();
-}
-
-/**
- *	register_reboot_notifier - Register function to be called at reboot time
- *	@nb: Info about notifier function to be called
- *
- *	Registers a function with the list of functions
- *	to be called at reboot time.
- *
- *	Currently always returns zero, as blocking_notifier_chain_register()
- *	always returns zero.
- */
-int register_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(register_reboot_notifier);
-
-/**
- *	unregister_reboot_notifier - Unregister previously registered reboot notifier
- *	@nb: Hook to be unregistered
- *
- *	Unregisters a previously registered reboot
- *	notifier function.
- *
- *	Returns zero on success, or %-ENOENT on failure.
- */
-int unregister_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(unregister_reboot_notifier);
-
-static void migrate_to_reboot_cpu(void)
-{
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu = 0;
-
-	cpu_hotplug_disable();
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu))
-		reboot_cpu = cpumask_first(cpu_online_mask);
-
-	/* Prevent races with other tasks migrating this task */
-	current->flags |= PF_NO_SETAFFINITY;
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu));
-}
-
-/**
- *	kernel_restart - reboot the system
- *	@cmd: pointer to buffer containing command to execute for restart
- *		or %NULL
- *
- *	Shutdown everything and perform a clean reboot.
- *	This is not safe to call in interrupt context.
- */
-void kernel_restart(char *cmd)
-{
-	kernel_restart_prepare(cmd);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
-	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
-	kmsg_dump(KMSG_DUMP_RESTART);
-	machine_restart(cmd);
-}
-EXPORT_SYMBOL_GPL(kernel_restart);
-
-static void kernel_shutdown_prepare(enum system_states state)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
-	system_state = state;
-	usermodehelper_disable();
-	device_shutdown();
-}
-/**
- *	kernel_halt - halt the system
- *
- *	Shutdown everything and perform a clean system halt.
- */
-void kernel_halt(void)
-{
-	kernel_shutdown_prepare(SYSTEM_HALT);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
-	kmsg_dump(KMSG_DUMP_HALT);
-	machine_halt();
-}
-
-EXPORT_SYMBOL_GPL(kernel_halt);
-
-/**
- *	kernel_power_off - power_off the system
- *
- *	Shutdown everything and perform a clean system power_off.
- */
-void kernel_power_off(void)
-{
-	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
-	if (pm_power_off_prepare)
-		pm_power_off_prepare();
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
-	kmsg_dump(KMSG_DUMP_POWEROFF);
-	machine_power_off();
-}
-EXPORT_SYMBOL_GPL(kernel_power_off);
-
-static DEFINE_MUTEX(reboot_mutex);
-
-/*
- * Reboot system call: for obvious reasons only root may call it,
- * and even root needs to set up some magic numbers in the registers
- * so that some mistake won't make this reboot the whole machine.
- * You can also set the meaning of the ctrl-alt-del-key here.
- *
- * reboot doesn't sync: do that yourself before calling this.
- */
-SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
-		void __user *, arg)
-{
-	struct pid_namespace *pid_ns = task_active_pid_ns(current);
-	char buffer[256];
-	int ret = 0;
-
-	/* We only trust the superuser with rebooting the system. */
-	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
-		return -EPERM;
-
-	/* For safety, we require "magic" arguments. */
-	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
-			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
-		return -EINVAL;
-
-	/*
-	 * If pid namespaces are enabled and the current task is in a child
-	 * pid_namespace, the command is handled by reboot_pid_ns() which will
-	 * call do_exit().
-	 */
-	ret = reboot_pid_ns(pid_ns, cmd);
-	if (ret)
-		return ret;
-
-	/* Instead of trying to make the power_off code look like
-	 * halt when pm_power_off is not set do it the easy way.
-	 */
-	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
-		cmd = LINUX_REBOOT_CMD_HALT;
-
-	mutex_lock(&reboot_mutex);
-	switch (cmd) {
-	case LINUX_REBOOT_CMD_RESTART:
-		kernel_restart(NULL);
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_ON:
-		C_A_D = 1;
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_OFF:
-		C_A_D = 0;
-		break;
-
-	case LINUX_REBOOT_CMD_HALT:
-		kernel_halt();
-		do_exit(0);
-		panic("cannot halt");
-
-	case LINUX_REBOOT_CMD_POWER_OFF:
-		kernel_power_off();
-		do_exit(0);
-		break;
-
-	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
-			ret = -EFAULT;
-			break;
-		}
-		buffer[sizeof(buffer) - 1] = '\0';
-
-		kernel_restart(buffer);
-		break;
-
-#ifdef CONFIG_KEXEC
-	case LINUX_REBOOT_CMD_KEXEC:
-		ret = kernel_kexec();
-		break;
-#endif
-
-#ifdef CONFIG_HIBERNATION
-	case LINUX_REBOOT_CMD_SW_SUSPEND:
-		ret = hibernate();
-		break;
-#endif
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	mutex_unlock(&reboot_mutex);
-	return ret;
-}
-
-static void deferred_cad(struct work_struct *dummy)
-{
-	kernel_restart(NULL);
-}
-
-/*
- * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
- * As it's called within an interrupt, it may NOT sync: the only choice
- * is whether to reboot at once, or just ignore the ctrl-alt-del.
- */
-void ctrl_alt_del(void)
-{
-	static DECLARE_WORK(cad_work, deferred_cad);
-
-	if (C_A_D)
-		schedule_work(&cad_work);
-	else
-		kill_cad_pid(SIGINT, 1);
-}
-	
 /*
  * Unprivileged users may change the real gid to the effective gid
  * or vice versa.  (BSD-style)
@@ -2276,68 +2007,6 @@ SYSCALL_DEFINE3(getcpu, unsigned __user *, cpup, unsigned __user *, nodep,
 	return err ? -EFAULT : 0;
 }
 
-char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
-
-static int __orderly_poweroff(bool force)
-{
-	char **argv;
-	static char *envp[] = {
-		"HOME=/",
-		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
-		NULL
-	};
-	int ret;
-
-	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
-	if (argv) {
-		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
-		argv_free(argv);
-	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
-		ret = -ENOMEM;
-	}
-
-	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
-		/*
-		 * I guess this should try to kick off some daemon to sync and
-		 * poweroff asap.  Or not even bother syncing if we're doing an
-		 * emergency shutdown?
-		 */
-		emergency_sync();
-		kernel_power_off();
-	}
-
-	return ret;
-}
-
-static bool poweroff_force;
-
-static void poweroff_work_func(struct work_struct *work)
-{
-	__orderly_poweroff(poweroff_force);
-}
-
-static DECLARE_WORK(poweroff_work, poweroff_work_func);
-
-/**
- * orderly_poweroff - Trigger an orderly system poweroff
- * @force: force poweroff if command execution fails
- *
- * This may be called from any context to trigger a system shutdown.
- * If the orderly shutdown fails, it will force an immediate shutdown.
- */
-int orderly_poweroff(bool force)
-{
-	if (force) /* do not override the pending "true" */
-		poweroff_force = true;
-	schedule_work(&poweroff_work);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(orderly_poweroff);
-
 /**
  * do_sysinfo - fill in sysinfo struct
  * @info: pointer to buffer to fill
-- 
1.8.2.1



From holt at sgi.com  Tue May  7 10:39:54 2013
From: holt at sgi.com (Robin Holt)
Date: Tue,  7 May 2013 09:39:54 -0500
Subject: [PATCH -v8 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1367937595-32241-1-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
Message-ID: <1367937595-32241-11-git-send-email-holt@sgi.com>

Preparing to move the parsing of reboot= to generic kernel code
forces the change in reboot_mode handling to use the enum.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/include/asm/hardware/iop3xx.h         |  3 ++-
 arch/arm/include/asm/mach/arch.h               |  2 +-
 arch/arm/include/asm/system_misc.h             |  3 ++-
 arch/arm/kernel/process.c                      |  5 +++--
 arch/arm/mach-at91/at91rm9200.c                |  3 ++-
 arch/arm/mach-at91/generic.h                   |  5 +++--
 arch/arm/mach-bcm2835/bcm2835.c                |  4 ++--
 arch/arm/mach-clps711x/common.c                |  2 +-
 arch/arm/mach-clps711x/common.h                |  4 +++-
 arch/arm/mach-cns3xxx/core.h                   |  4 +++-
 arch/arm/mach-cns3xxx/pm.c                     |  2 +-
 arch/arm/mach-davinci/devices-da8xx.c          |  3 ++-
 arch/arm/mach-davinci/devices.c                |  3 ++-
 arch/arm/mach-davinci/include/mach/common.h    |  3 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h     |  3 ++-
 arch/arm/mach-davinci/include/mach/tnetv107x.h |  3 ++-
 arch/arm/mach-davinci/tnetv107x.c              |  3 ++-
 arch/arm/mach-dove/common.c                    |  2 +-
 arch/arm/mach-dove/common.h                    |  4 +++-
 arch/arm/mach-ebsa110/core.c                   |  2 +-
 arch/arm/mach-ep93xx/core.c                    |  3 ++-
 arch/arm/mach-ep93xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-exynos/common.c                  |  4 ++--
 arch/arm/mach-exynos/common.h                  |  5 +++--
 arch/arm/mach-footbridge/common.c              |  4 ++--
 arch/arm/mach-footbridge/common.h              |  3 ++-
 arch/arm/mach-footbridge/netwinder-hw.c        |  4 ++--
 arch/arm/mach-highbank/core.h                  |  4 +++-
 arch/arm/mach-highbank/system.c                |  5 +++--
 arch/arm/mach-imx/common.h                     |  4 +++-
 arch/arm/mach-imx/mach-imx6q.c                 |  3 ++-
 arch/arm/mach-imx/system.c                     |  2 +-
 arch/arm/mach-integrator/common.h              |  3 ++-
 arch/arm/mach-integrator/core.c                |  2 +-
 arch/arm/mach-iop13xx/include/mach/iop13xx.h   |  5 ++++-
 arch/arm/mach-iop13xx/setup.c                  |  2 +-
 arch/arm/mach-iop32x/n2100.c                   |  2 +-
 arch/arm/mach-ixp4xx/common.c                  |  4 ++--
 arch/arm/mach-ixp4xx/dsmg600-setup.c           |  1 +
 arch/arm/mach-ixp4xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-ixp4xx/include/mach/timex.h      |  2 +-
 arch/arm/mach-kirkwood/board-lsxl.c            |  2 +-
 arch/arm/mach-kirkwood/common.c                |  3 ++-
 arch/arm/mach-kirkwood/common.h                |  4 +++-
 arch/arm/mach-ks8695/generic.h                 |  2 +-
 arch/arm/mach-ks8695/time.c                    |  4 ++--
 arch/arm/mach-lpc32xx/common.c                 |  6 +++---
 arch/arm/mach-lpc32xx/common.h                 |  3 ++-
 arch/arm/mach-mmp/common.c                     |  2 +-
 arch/arm/mach-mmp/common.h                     |  3 ++-
 arch/arm/mach-mmp/include/mach/pxa168.h        |  4 +++-
 arch/arm/mach-mmp/pxa168.c                     |  2 +-
 arch/arm/mach-mv78xx0/common.c                 |  2 +-
 arch/arm/mach-mv78xx0/common.h                 |  4 +++-
 arch/arm/mach-mvebu/common.h                   |  4 +++-
 arch/arm/mach-mvebu/system-controller.c        |  3 ++-
 arch/arm/mach-mxs/mach-mxs.c                   |  4 +++-
 arch/arm/mach-netx/generic.c                   |  3 ++-
 arch/arm/mach-netx/generic.h                   |  4 +++-
 arch/arm/mach-nomadik/cpu-8815.c               |  2 +-
 arch/arm/mach-omap1/board-voiceblue.c          |  3 ++-
 arch/arm/mach-omap1/common.h                   |  3 ++-
 arch/arm/mach-omap1/reset.c                    |  3 ++-
 arch/arm/mach-omap2/am33xx-restart.c           |  3 ++-
 arch/arm/mach-omap2/common.h                   | 17 +++++++++--------
 arch/arm/mach-omap2/omap2-restart.c            |  2 +-
 arch/arm/mach-omap2/omap3-restart.c            |  3 ++-
 arch/arm/mach-omap2/omap4-common.c             |  3 ++-
 arch/arm/mach-orion5x/common.c                 |  2 +-
 arch/arm/mach-orion5x/common.h                 |  4 +++-
 arch/arm/mach-orion5x/ls-chl-setup.c           |  2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c           |  2 +-
 arch/arm/mach-orion5x/lsmini-setup.c           |  2 +-
 arch/arm/mach-picoxcell/common.c               |  3 ++-
 arch/arm/mach-prima2/common.h                  |  4 +++-
 arch/arm/mach-prima2/rstc.c                    |  3 ++-
 arch/arm/mach-pxa/corgi.c                      |  6 +++---
 arch/arm/mach-pxa/generic.h                    |  4 +++-
 arch/arm/mach-pxa/mioa701.c                    |  7 ++++---
 arch/arm/mach-pxa/poodle.c                     |  2 +-
 arch/arm/mach-pxa/reset.c                      |  8 ++++----
 arch/arm/mach-pxa/spitz.c                      |  5 +++--
 arch/arm/mach-pxa/tosa.c                       |  5 +++--
 arch/arm/mach-realview/realview_eb.c           |  3 ++-
 arch/arm/mach-realview/realview_pb1176.c       |  3 ++-
 arch/arm/mach-realview/realview_pb11mp.c       |  3 ++-
 arch/arm/mach-realview/realview_pba8.c         |  3 ++-
 arch/arm/mach-realview/realview_pbx.c          |  3 ++-
 arch/arm/mach-rpc/riscpc.c                     |  3 ++-
 arch/arm/mach-s3c24xx/common.h                 | 12 +++++++-----
 arch/arm/mach-s3c24xx/s3c2410.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2412.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2416.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2443.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c244x.c                |  5 +++--
 arch/arm/mach-s3c64xx/common.c                 |  5 +++--
 arch/arm/mach-s3c64xx/common.h                 |  4 +++-
 arch/arm/mach-s5p64x0/common.c                 |  5 +++--
 arch/arm/mach-s5p64x0/common.h                 |  4 +++-
 arch/arm/mach-s5pc100/common.c                 |  5 +++--
 arch/arm/mach-s5pc100/common.h                 |  4 +++-
 arch/arm/mach-s5pv210/common.c                 |  2 +-
 arch/arm/mach-s5pv210/common.h                 |  4 +++-
 arch/arm/mach-sa1100/generic.c                 |  5 +++--
 arch/arm/mach-sa1100/generic.h                 |  3 ++-
 arch/arm/mach-shark/core.c                     |  3 ++-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  3 ++-
 arch/arm/mach-shmobile/board-kzm9g.c           |  3 ++-
 arch/arm/mach-socfpga/socfpga.c                |  3 ++-
 arch/arm/mach-spear/generic.h                  |  4 +++-
 arch/arm/mach-spear/restart.c                  |  5 +++--
 arch/arm/mach-sunxi/sunxi.c                    |  3 ++-
 arch/arm/mach-tegra/board.h                    |  3 ++-
 arch/arm/mach-tegra/common.c                   |  3 ++-
 arch/arm/mach-u300/core.c                      |  6 +++---
 arch/arm/mach-versatile/core.c                 |  3 ++-
 arch/arm/mach-versatile/core.h                 |  3 ++-
 arch/arm/mach-vt8500/vt8500.c                  |  3 ++-
 arch/arm/mach-w90x900/cpu.c                    |  4 ++--
 arch/arm/mach-w90x900/nuc9xx.h                 |  5 ++++-
 arch/arm/plat-iop/gpio.c                       |  1 +
 arch/arm/plat-iop/restart.c                    |  2 +-
 drivers/power/reset/restart-poweroff.c         |  3 ++-
 drivers/power/reset/vexpress-poweroff.c        |  2 +-
 include/linux/reboot.h                         |  1 +
 include/linux/vexpress.h                       |  1 +
 126 files changed, 283 insertions(+), 167 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a..423744b 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e2b551e..2353bc3 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -54,7 +54,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	void			(*handle_irq)(struct pt_regs *);
 #endif
-	void			(*restart)(char, const char *);
+	void			(*restart)(enum reboot_mode, const char *);
 };
 
 /*
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e3..a3d61ad 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED	(1 << 0)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 161e66c..58c0d7a 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -112,7 +113,7 @@ void soft_restart(unsigned long addr)
 	BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +123,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..f70c239 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -304,7 +305,7 @@ static void at91rm9200_idle(void)
 	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	/*
 	 * Perform a hardware reset with the use of the Watchdog timer.
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..0723ed6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 740fa9e..deec4cc 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -53,7 +53,7 @@ static void bcm2835_setup_restart(void)
 	WARN(!wdt_regs, "failed to remap watchdog regs");
 }
 
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 val;
 
@@ -91,7 +91,7 @@ static void bcm2835_power_off(void)
 	writel_relaxed(val, wdt_regs + PM_RSTS);
 
 	/* Continue with normal reset mechanism */
-	bcm2835_restart(0, "");
+	bcm2835_restart(REBOOT_COLD, "");
 }
 
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..54f6a8d 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -345,7 +345,7 @@ void __init clps711x_timer_init(void)
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2da0ff5 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
  * Common bits.
  */
 
+#include <linux/reboot.h>
+
 #define CLPS711X_NR_IRQS	(33)
 #define CLPS711X_NR_GPIO	(4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit)	((prt) * 8 + (bit))
@@ -12,4 +14,4 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b..5218b61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
+#include <linux/reboot.h>
+
 extern void cns3xxx_timer_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 79e3d47..fb38c72 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..c80e189 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
 	.resource	= da8xx_watchdog_resources,
 };
 
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device *dev;
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3..5364f70 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
@@ -303,7 +304,7 @@ struct platform_device davinci_wdt_device = {
 	.resource	= wdt_resources,
 };
 
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
 	davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..cce316b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 extern void davinci_timer_init(void);
 
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..95b76a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,6 +17,7 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
@@ -106,7 +107,7 @@ int __init da850_register_vpif_display
 			(struct vpif_display_config *display_config);
 int __init da850_register_vpif_capture
 			(struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..bc9479d 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -54,7 +55,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d..4545667 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/map.h>
 
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
 	__raw_writel(1, &regs->kick);
 }
 
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
 	tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c6b3b2b..c37dd81 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -345,7 +345,7 @@ void __init dove_init(void)
 	dove_xor1_init();
 }
 
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index ee59fba..0a704ee 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 
 #endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 69a9d5d..62b928b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 
 arch_initcall(ebsa110_init);
 
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0x80000000);
 }
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3d..df8612f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
 	gpio_led_register_device(-1, &ep93xx_led_data);
 }
 
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b3..e256e0b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 46089fe..1158c0f 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -313,12 +313,12 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
-void exynos4_restart(char mode, const char *cmd)
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	u32 val;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index b17448c..670e8fb 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,6 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/reboot.h>
 #include <linux/of.h>
 
 extern void mct_init(void);
@@ -22,8 +23,8 @@ struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369..b0a7dd3 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
 	}
 }
 
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50..56607b3 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23f..807f49a 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
 
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206..aea1ec5 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
 
+#include <linux/reboot.h>
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384..9e56003 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
  */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 
 #include "core.h"
 #include "sysregs.h"
 
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 'h')
+	if (mode == REBOOT_COLD)
 		highbank_set_pwr_hard_reset();
 	else
 		highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 9fea252..299bc91 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct platform_device;
 struct clk;
 enum mxc_cpu_pwr_mode;
@@ -71,7 +73,7 @@ extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 99502ee..a8d10f4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -26,6 +26,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -72,7 +73,7 @@ static int imx6q_revision(void)
 	}
 }
 
-static void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..d7ec547 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -34,7 +34,7 @@ static void __iomem *wdog_base;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658b..ad0ac55 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d2..4cdfd73 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
  * To reset, we hit the on-board reset register in the system FPGA
  */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
 	cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58..17b4027 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 
 #ifndef __ASSEMBLY__
+
+#include <linux/reboot.h>
+
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61..97a4906 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -597,7 +597,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a..0691443 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
 		;
 }
 
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
 	gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
 	gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..b7ebbce 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
 					0xf, 0xfffffffe);
 }
 
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if ( 1 && mode == 's') {
+	if ( 1 && mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8..686ef34 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb6..4c4c6a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 #include <asm/types.h>
 
 #ifndef	__ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index c9e930f..729b2db 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -3,7 +3,7 @@
  * 
  */
 
-#include <mach/hardware.h>
+// #include <mach/hardware.h>
 
 /*
  * We use IXP425 General purpose timer for our timer needs, it runs at 
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..b54d0c7 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -35,7 +35,7 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
  */
 static void lsxl_power_off(void)
 {
-	kirkwood_restart('h', NULL);
+	kirkwood_restart(REBOOT_COLD, NULL);
 }
 
 void __init lsxl_init(void)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 49792a0..c3a8d30 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -695,7 +696,7 @@ void __init kirkwood_init(void)
 #endif
 }
 
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 3147be2..3560a02 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,7 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 			    int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce4..43253f8 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a386..1a728ff 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
 	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
 
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	unsigned int reg;
 
-	if (mode == 's')
+	if (reboot_mode == REBOOT_WARM)
 		soft_restart(0);
 
 	/* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c..a610434 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
 	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
 
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_WARM:
+	case REBOOT_COLD:
 		lpc32xx_watchdog_reset();
 		break;
 
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b2606..1cd8853 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 /*
  * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 
 
 /*
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..c03b4ab 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..991d7e9 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..459c2d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
 
+#include <linux/reboot.h>
+
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3..144e997 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 	return platform_device_register(&pxa168_device_usb_host);
 }
 
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0efa144..862ba67 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -407,7 +407,7 @@ void __init mv78xx0_init(void)
 	clk_init();
 }
 
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6889af2 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 
 extern void mv78xx0_timer_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..f7ad45e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,9 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-void mvebu_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df..f875124 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 static void __iomem *system_controller_base;
 
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
 	{ /* end of list */ },
 };
 
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!system_controller_base) {
 		pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index b5c1bdd..6132793 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -27,6 +27,8 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -560,7 +562,7 @@ static void __init mxs_machine_init(void)
 /*
  * Reset the system. It is called by machine_restart().
  */
-static void mxs_restart(char mode, const char *cmd)
+static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *reset_addr;
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68..db25b0c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 
 subsys_initcall(netx_init);
 
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
 	       NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26b..bb2ce47 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/reboot.h>
+
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..8aec5af 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -148,7 +148,7 @@ static void __init cpu8815_map_io(void)
 	iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
 
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1..4677a9c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
 	gpio_set_value(0, wdt_gpio_state);
 }
 
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e99..abec019 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <plat/i2c.h>
 
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e..72bf4bf 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
 
 
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8..1eae962 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..be9b930 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <asm/proc-fns.h>
 
@@ -118,33 +119,33 @@ static inline void omap_soc_device_init(void)
 #endif
 
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716..68423e2 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
  * Set the DPLL to bypass so that reboot completes successfully.  No
  * return value.
  */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 rate;
 
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582..5de2a0c 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 	omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ff..14c7bad 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -348,7 +349,7 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap44xx_restart(char mode, const char *cmd)
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* XXX Should save 'cmd' into scratchpad for use after reboot */
 	omap4_prminst_global_warm_sw_reset(); /* never returns */
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 2075bf8..88e097708 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -311,7 +311,7 @@ void __init orion5x_init(void)
 	orion5x_wdt_init();
 }
 
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index e603457..8304d6e 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -40,7 +42,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 044da5b..6dfdae5 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 
 static void lschl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_COLD, NULL);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index d49f934..417de0f 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 
 static void ls_hgl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_COLD, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 8e3965c..417bbd3 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_COLD, NULL);
 }
 
 
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..d298ed0 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,6 +15,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
@@ -70,7 +71,7 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Configure the watchdog to reset with the shortest possible timeout
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd..a630485 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..bdf57d4 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -82,7 +83,7 @@ int sirfsoc_reset_device(struct device *dev)
 
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fea..e1f527b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
 		/* Green LED off tells the bootloader to halt */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_COLD, NULL);
 }
 
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!machine_is_corgi())
 		/* Green LED on tells the bootloader to reboot */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-	pxa_restart('h', cmd);
+	pxa_restart(REBOOT_COLD, cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39..8963984 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/reboot.h>
+
 struct irq_data;
 
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
 
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dbea67a..01ebf50 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -691,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', NULL);
+	pxa_restart(REBOOT_WARM, NULL);
 }
 
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', cmd);
+	pxa_restart(REBOOT_WARM, cmd);
 }
 
 static struct gpio global_gpios[] = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..5d59bd4 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -422,7 +422,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 
 static void poodle_poweroff(void)
 {
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_COLD, NULL);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583..4a31c12 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
 	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
 	local_irq_disable();
 	local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
 	clear_reset_status(RESET_STATUS_ALL);
 
 	switch (mode) {
-	case 's':
+	case REBOOT_WARM:
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 		break;
-	case 'g':
+	case REBOOT_GPIO:
 		do_gpio_reset();
 		break;
-	case 'h':
+	case REBOOT_COLD:
 	default:
 		do_hw_reset();
 		break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c3c0042..2125df0 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -924,10 +925,10 @@ static inline void spitz_i2c_init(void) {}
  ******************************************************************************/
 static void spitz_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 	/* Bootloader magic for a reboot */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a41992f..0206b91 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bf..c85ddb2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
 	realview_eb_twd_init();
 }
 
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1..c5eade7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe21..f4b0962 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
 	realview_pb11mp_twd_init();
 }
 
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a..10a3e1d 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185..9d75493 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
 
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5..09d602b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 
 arch_initcall(rpc_init);
 
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
 	iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 307c371..84b2806 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 #ifdef CONFIG_CPU_S3C2410
@@ -20,7 +22,7 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -36,7 +38,7 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -51,7 +53,7 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -66,7 +68,7 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c244x_init_clocks(int xtal);
-extern void s3c244x_restart(char mode, const char *cmd);
+extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
@@ -96,7 +98,7 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5..2d5f102 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
@@ -195,9 +196,9 @@ int __init s3c2410a_init(void)
 	return s3c2410_init();
 }
 
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		soft_restart(0);
 	}
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0f864d4..58a40ca 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,9 +130,9 @@ static void s3c2412_idle(void)
 	cpu_do_idle();
 }
 
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	/* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index b9c5d38..425ce70 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -79,9 +80,9 @@ static struct device s3c2416_dev = {
 	.bus		= &s3c2416_subsys,
 };
 
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 8328cd6..e3ab653 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,9 +60,9 @@ static struct device s3c2443_dev = {
 	.bus		= &s3c2443_subsys,
 };
 
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb..34ded8d 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -197,9 +198,9 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
 	.resume		= s3c244x_resume,
 };
 
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_WARM)
 		soft_restart(0);
 
 	arch_wdt_reset();
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..a060fad 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,9 +376,9 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
 
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_WARM)
 		arch_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..e8f990b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
 
+#include <linux/reboot.h>
+
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
 
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..1af3e02 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -437,9 +438,9 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
 
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_WARM)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fd..f3a9b43 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5P6440
 
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..2855bed 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -216,9 +217,9 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_WARM)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index c41f912..08d782d 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
 
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e..023f1a7 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 	}
 };
 
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 0a1cc0ae..fe1beb5 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
 
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98..040ce1c 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <video/sa1100fb.h>
 
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
 	PMCR = PMCR_SF;
 }
 
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1..9a33695 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
  *
  * Author: Nicolas Pitre
  */
+#include <linux/reboot.h>
 
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 1535557..1d32c5e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
         short temp;
         /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 4dfe322..8db5c95 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -1277,7 +1278,7 @@ static void __init eva_add_early_devices(void)
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* Do soft power on reset */
 	writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a..2f223f0 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -33,6 +33,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -806,7 +807,7 @@ static void __init kzm_init(void)
 	sh73a0_pm_init();
 }
 
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
 	/* Do soft power on reset */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a0513..0fde6c0 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -90,7 +91,7 @@ static void __init socfpga_init_irq(void)
 	socfpga_sysmgr_init();
 }
 
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 temp;
 
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index 8ba7e75..104dc00 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -16,6 +16,8 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/pl08x.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 
 extern void spear13xx_timer_init(void);
@@ -37,7 +39,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
 
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 2b44500..38bab54 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -12,14 +12,15 @@
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* software reset, Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..f71923b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <linux/clk/sunxi.h>
 
@@ -36,7 +37,7 @@
 
 static void __iomem *wdt_base;
 
-static void sun4i_restart(char mode, const char *cmd)
+static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!wdt_base)
 		return;
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1787327..9a6659f 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 
 void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..2572e73 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip.h>
 #include <linux/clk/tegra.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -67,7 +68,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
 
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
 	u32 reg;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..c5177c23e 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -671,11 +671,11 @@ static void __init u300_init_machine(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-static void u300_restart(char mode, const char *cmd)
+static void u300_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_WARM:
+	case REBOOT_COLD:
 #ifdef CONFIG_COH901327_WATCHDOG
 		coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 25160ae..9d16f58 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif	/* CONFIG_LEDS */
 
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 	u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d..f06d576 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..de2b7eb 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +48,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (pmc_base)
 		writel(1, pmc_base + VT8500_PMSR_REG);
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b..c1f9eed 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define	WTE	(1 << 7)
 #define	WTRE	(1 << 1)
 
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_WARM) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b2..e3ab1e1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
  * published by the Free Software Foundation.
  *
  */
+
+#include <linux/reboot.h>
+
 struct map_desc;
 
 /* core initialisation functions */
 
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be..697de6d 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699..3a4d5e5 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
 
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	*IOP3XX_PCSR = 0x30;
 
diff --git a/drivers/power/reset/restart-poweroff.c b/drivers/power/reset/restart-poweroff.c
index 059cd15..6ebcc11 100644
--- a/drivers/power/reset/restart-poweroff.c
+++ b/drivers/power/reset/restart-poweroff.c
@@ -15,11 +15,12 @@
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 
 static void restart_poweroff_do_poweroff(void)
 {
-	arm_pm_restart('h', NULL);
+	arm_pm_restart(REBOOT_COLD, NULL);
 }
 
 static int restart_poweroff_probe(struct platform_device *pdev)
diff --git a/drivers/power/reset/vexpress-poweroff.c b/drivers/power/reset/vexpress-poweroff.c
index 469e696..476aa49 100644
--- a/drivers/power/reset/vexpress-poweroff.c
+++ b/drivers/power/reset/vexpress-poweroff.c
@@ -48,7 +48,7 @@ static void vexpress_power_off(void)
 
 static struct device *vexpress_restart_device;
 
-static void vexpress_restart(char str, const char *cmd)
+static void vexpress_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	vexpress_reset_do(vexpress_restart_device, "restart");
 }
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 37d56c3..26cf11b 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -13,6 +13,7 @@
 enum reboot_mode {
 	REBOOT_COLD = 0,
 	REBOOT_WARM,
+	REBOOT_GPIO,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index ea7168a..617c01b 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/reboot.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
-- 
1.8.2.1



From swarren at wwwdotorg.org  Tue May  7 10:54:31 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 07 May 2013 08:54:31 -0600
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <20130507130850.GA11202@avionic-0098.adnet.avionic-design.de>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
 <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>
 <20130507130850.GA11202@avionic-0098.adnet.avionic-design.de>
Message-ID: <518915A7.1020105@wwwdotorg.org>

On 05/07/2013 07:08 AM, Thierry Reding wrote:
> On Tue, May 07, 2013 at 03:48:49PM +0300, Peter De Schrijver
> wrote:
>> On Mon, May 06, 2013 at 10:39:04PM +0200, Stephen Warren wrote:
>>> From: Stephen Warren <swarren at nvidia.com>
>>> 
>>> Tegra20 HW appears to have a bug such that PCIe device
>>> interrupts, whether they are legacy IRQs or MSI, are lost when
>>> LP2 is enabled. To work around this, simply disable LP2 if the
>>> PCI driver and DT node are both enabled.
>>> 
>> 
>> Wouldn't it make more sense to disable LP2 when we actually
>> detect a PCIe device?

I did consider that, but rejected the idea for the reasons Thierry
mentioned.

> I'm not sure a patch to do so would be as simple as this one. For
> one, the cpuidle framework will already have been initialized when
> PCIe enumeration completes. So some way of permanently disabling
> one state at runtime would be required and I don't think cpuidle
> provides an API to do so. I know the latter isn't really a good
> reason, but I don't think adding that kind of API just because
> Tegra20 seems to have a bug would be appropriate.

There is a way to do this, since it can be done via sysfs, but I don't
think it's exposed as an API from cpuidle. I agree it seems a little
silly to expose it just to support this HW bug though.

> Furthermore, it is quite likely that the PCIe controller will only
> be enabled in DT for devices that actually have a PCIe device
> hooked up.

But this was my main reasoning.


From tony at atomide.com  Tue May  7 11:04:03 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 May 2013 08:04:03 -0700
Subject: [GIT PULL] Urgent omap timer fix for current merge window
In-Reply-To: <20130507120202.GK21614@n2100.arm.linux.org.uk>
References: <20130506234610.GK28721@atomide.com>
 <20130507120202.GK21614@n2100.arm.linux.org.uk>
Message-ID: <20130507150402.GP28721@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [130507 05:07]:
> On Mon, May 06, 2013 at 04:46:11PM -0700, Tony Lindgren wrote:
> > Vaibhav Hiremath (1):
> >       ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a
> 
> Neither your pull request subject nor the above summary line really
> sum up what the problem is - the real problem is "fix breakage causing
> OMAP to fail to boot".
> 
> I've just been chasing this problem and the descriptions given on this
> just suggest that it's a timer issue not a non-boot issue.

Oops yes sorry if the description was a bit unclear.

Regards,

Tony


From tony at atomide.com  Tue May  7 11:04:38 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 May 2013 08:04:38 -0700
Subject: [GIT PULL] Urgent omap timer fix for current merge window
In-Reply-To: <201305071448.19868.arnd@arndb.de>
References: <20130506234610.GK28721@atomide.com>
 <201305071448.19868.arnd@arndb.de>
Message-ID: <20130507150438.GQ28721@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [130507 05:54]:
> On Tuesday 07 May 2013, Tony Lindgren wrote:
> > The following changes since commit dc2d3db8137fba0f62d7517e1bea8a47f69fcbc4:
> > 
> >   Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers (2013-04-08 19:30:48 +0200)
> > 
> > are available in the git repository at:
> > 
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/fixes-for-merge-window
> > 
> > for you to fetch changes up to 08a48be32ff31d38bcfec7d210c954cb62fd5cd7:
> > 
> >   ARM: OMAP4: change the device names in usb_bind_phy (2013-05-06 16:39:16 -0700)
> > 
> > ----------------------------------------------------------------
> > An urgent fix for a timer mismerge for and a regression fix for
> > musb device naming change.
> > 
> 
> Hi Tony,
> 
> Russell also ran into this problem, so I'm including these in the late/cleanup branch,
> which I'll send to Linus later today.

Thanks!

Tony


From stern at rowland.harvard.edu  Tue May  7 11:15:34 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Tue, 7 May 2013 11:15:34 -0400 (EDT)
Subject: [RFC PATCH 1/2] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <1367920253-15207-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305071039560.1165-100000@iolanthe.rowland.org>

On Tue, 7 May 2013, Manjunath Goudar wrote:

> This patch prepares ohci-hcd for being split up into a core
> library and separate platform driver modules.  A generic
> ohci_hc_driver structure is created, containing all the "standard"
> values, and a new mechanism is added whereby a driver module can
> specify a set of overrides to those values.  In addition the
> ohci_restart(),ohci_suspend() and ohci_resume() routines need
> to be EXPORTed for use by the drivers.

This patch still has several problems.  For example, the description
doesn't mention the fact that ohci_init() was EXPORTed.

In fact, why was ohci_init() EXPORTed?  I don't see any reason for
this.  ohci_pci.c doesn't need to call it; just insert a call to
ohci_init() at the beginning of ohci_restart().

> In V2:
> -ohci_hcd_init(), ohci_run() and ohci_stop revert back to static routine.

They don't "revert" since they have never been non-static.  You should
say something more like "ohci_hcd_init(), ohci_run(), and ohci_stop()
are not made non-static."

> -ohci_setup() and ohci_start() functions written to generic OHCI initialization
>  for all ohci bus glue.

Fix the grammar in that sentence.  And you should mention these new
functions in the main part of the patch description, not just down here.

> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 58c14c1..a38d76b 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -40,7 +40,9 @@ obj-$(CONFIG_USB_EHCI_TEGRA)    +=ehci-tegra.o
>  obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
>  obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
>  obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
> +
>  obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
> +

You do not need to add these blank lines in this patch.  If you want,
you can add them in the ohci-pci patch.

>  obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
>  obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
>  obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
> diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
> index 9e6de95..7922c61 100644
> --- a/drivers/usb/host/ohci-hcd.c
> +++ b/drivers/usb/host/ohci-hcd.c
> @@ -79,13 +79,7 @@ static const char	hcd_name [] = "ohci_hcd";
>  #include "pci-quirks.h"
>  
>  static void ohci_dump (struct ohci_hcd *ohci, int verbose);
> -static int ohci_init (struct ohci_hcd *ohci);
> -static void ohci_stop (struct usb_hcd *hcd);

I thought ohci_stop() wasn't going to be changed in this patch.  Why
was this line updated?

> -
> -#if defined(CONFIG_PM) || defined(CONFIG_PCI)
> -static int ohci_restart (struct ohci_hcd *ohci);
> -#endif
> -
> +static void ohci_stop(struct usb_hcd *hcd);
>  #ifdef CONFIG_PCI
>  static void sb800_prefetch(struct ohci_hcd *ohci, int on);
>  #else
> @@ -520,7 +514,7 @@ done:
>  
>  /* init memory, and kick BIOS/SMM off */
>  
> -static int ohci_init (struct ohci_hcd *ohci)
> +int ohci_init(struct ohci_hcd *ohci)
>  {
>  	int ret;
>  	struct usb_hcd *hcd = ohci_to_hcd(ohci);
> @@ -590,6 +584,7 @@ static int ohci_init (struct ohci_hcd *ohci)
>  
>  	return ret;
>  }
> +EXPORT_SYMBOL_GPL(ohci_init);
>  
>  /*-------------------------------------------------------------------------*/
>  
> @@ -597,11 +592,11 @@ static int ohci_init (struct ohci_hcd *ohci)
>   * resets USB and controller
>   * enable interrupts
>   */
> -static int ohci_run (struct ohci_hcd *ohci)
> +static int ohci_run(struct usb_hcd *hcd)

Why did you change the signature of this function?  By doing so, you
just broke all the bus glue files.  (Except for ohci_pci and
ohci_platform, which explicitly get fixed below.)

Since this function remains static, there's no reason to change it.

>  {
> +	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
>  	u32			mask, val;
>  	int			first = ohci->fminterval == 0;
> -	struct usb_hcd		*hcd = ohci_to_hcd(ohci);
>  
>  	ohci->rh_state = OHCI_RH_HALTED;
>  
> @@ -767,7 +762,37 @@ retry:
>  
>  	return 0;
>  }
> +/*------------------------------------------------------------------------*/
> +
> +/* ohci generic function for all OHCI bus glue */
> +
> +static int ohci_setup(struct usb_hcd *hcd)
> +{
> +	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
> +	int retval;
> +
> +	ohci->sbrn = HCD_USB11;

What is this doing here?  Why did you add this "sbrn" member to struct
ohci_hcd?

> +
> +	/* data structure init */
> +	retval = ohci_init(ohci);
> +	if (retval)
> +		return retval;
> +	ohci_usb_reset(ohci);

Why is this call here?  Doesn't ohci_init() already call
ohci_usb_reset()?

> +	return 0;
> +}
>  
> +static int ohci_start(struct usb_hcd *hcd)
> +{
> +	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
> +	int	ret;

There should be a blank line between the declarations and the
executable statements.

> +	ret = ohci_run(hcd);
> +	if (ret < 0) {
> +		ohci_err(ohci, "can't start\n");
> +		ohci_stop(hcd);
> +	}
> +	return ret;
> +}
> +/*-------------------------------------------------------------------------*/
>  /*-------------------------------------------------------------------------*/

You should not duplicate this comment line.


> diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
> index 951514e..0b34b59 100644
> --- a/drivers/usb/host/ohci-pci.c
> +++ b/drivers/usb/host/ohci-pci.c
> @@ -288,7 +288,7 @@ static int ohci_pci_start (struct usb_hcd *hcd)
>  	}
>  #endif /* CONFIG_PM */
>  
> -	ret = ohci_run (ohci);
> +	ret = ohci_run(hcd);

If you hadn't changed ohci_run(), this wouldn't be needed.

>  	if (ret < 0) {
>  		ohci_err (ohci, "can't start\n");
>  		ohci_stop (hcd);
> diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
> index c3e7287..545c657 100644
> --- a/drivers/usb/host/ohci-platform.c
> +++ b/drivers/usb/host/ohci-platform.c
> @@ -46,7 +46,7 @@ static int ohci_platform_start(struct usb_hcd *hcd)
>  	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
>  	int err;
>  
> -	err = ohci_run(ohci);
> +	err = ohci_run(hcd);

Likewise here.

>  	if (err < 0) {
>  		ohci_err(ohci, "can't start\n");
>  		ohci_stop(hcd);
> diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
> index d329914..455e9b1 100644
> --- a/drivers/usb/host/ohci.h
> +++ b/drivers/usb/host/ohci.h
> @@ -357,7 +357,6 @@ struct ohci_hcd {
>  	 * I/O memory used to communicate with the HC (dma-consistent)
>  	 */
>  	struct ohci_regs __iomem *regs;
> -

You shouldn't make unrelated changes, like removing this blank line or 
the one below.

>  	/*
>  	 * main memory used to communicate with the HC (dma-consistent).
>  	 * hcd adds to schedule for a live hc any time, but removals finish
> @@ -373,7 +372,6 @@ struct ohci_hcd {
>  	struct ed		*periodic [NUM_INTS];	/* shadow int_table */
>  
>  	void (*start_hnp)(struct ohci_hcd *ohci);
> -
>  	/*
>  	 * memory management for queue data structures
>  	 */
> @@ -392,7 +390,7 @@ struct ohci_hcd {
>  	unsigned long		next_statechange;	/* suspend/resume */
>  	u32			fminterval;		/* saved register */
>  	unsigned		autostop:1;	/* rh auto stopping/stopped */
> -
> +	u8			sbrn;
>  	unsigned long		flags;		/* for HC bugs */
>  #define	OHCI_QUIRK_AMD756	0x01			/* erratum #4 */
>  #define	OHCI_QUIRK_SUPERIO	0x02			/* natsemi */
> @@ -718,3 +716,29 @@ static inline u32 roothub_status (struct ohci_hcd *hc)
>  	{ return ohci_readl (hc, &hc->regs->roothub.status); }
>  static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
>  	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
> +
> +/* Declarations of things exported for use by ohci platform drivers */
> +
> +struct ohci_driver_overrides {
> +	const char	*product_desc;
> +	size_t		extra_priv_size;
> +	int		(*reset)(struct usb_hcd *hcd);
> +};
> +
> +extern void	ohci_init_driver(struct hc_driver *drv,
> +				const struct ohci_driver_overrides *over);
> +extern int	ohci_init(struct ohci_hcd *ohci);
> +extern int	ohci_restart(struct ohci_hcd *ohci);
> +#ifdef CONFIG_PM
> +extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
> +extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
> +#else
> +static inline int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
> +{
> +	return 0;
> +}
> +static inline int ohci_resume(struct usb_hcd *hcd, bool hibernated)
> +{
> +	return 0;
> +}
> +#endif

The #else part of this isn't needed, and I doubt very much that it
would work correctly if it was needed.

Alan Stern



From nicolas.pitre at linaro.org  Tue May  7 11:20:42 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 7 May 2013 11:20:42 -0400 (EDT)
Subject: [RFC PATCH v2] drivers: bus: add ARM CCI support
In-Reply-To: <20130507134943.GB19477@e102568-lin.cambridge.arm.com>
References: <1367425108-4698-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1367425108-4698-2-git-send-email-lorenzo.pieralisi@arm.com>
 <alpine.LFD.2.03.1305011239240.11070@syhkavp.arg>
 <20130507134943.GB19477@e102568-lin.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305071113310.13109@syhkavp.arg>

On Tue, 7 May 2013, Lorenzo Pieralisi wrote:

> On Mon, May 06, 2013 at 04:05:28PM +0100, Nicolas Pitre wrote:
> > When compiled in, module_init() is translated into device_initcall().
> > This is way too late for bringing up secondary CPUs during boot via the
> > MCPM layer.  That is not an issue as far as the code presented here is
> > concerned since there is no integration with MCPM yet, but eventually
> > we'd want the MCPM power_up_setup method to integrate with the port
> > discovery performed here instead of having them hardcoded in the
> > assembly code.  This means it would have to become early_initcall()
> > instead.  And at that point the driver infrastructure isn't fully
> > operational, meaning that driver_probe() won't be usable either (looking
> > at what we did to the TC2 spc init code is a good example of what I mean
> > here).
> 
> Yes, I thought about that. This means that CCI driver should not rely on
> platform device structs, and yes I can mirror SPC probing code to take care
> of ordering issues. I am quite tempted to remove the platform device/driver
> infrastructure altogether and just rely on the DT layer (as GIC, PL310
> do) to initialize CCI. What do you think ?

I think that's probably the best approach.  That's what we ended up 
doing to the spc code for the same reasons.

> I think I will leave the
> platform driver infrastructure, and at probe it will check if data
> structures have already been initialized by an exported function, say:
> 
> cci_of_init()

Please let's try to avoid propagating the "of" acronym further.  We 
don't use Open Firmware here.  Using "dt" is more appropriate IMHO.

> if the data structures are already initialized basically the probe
> function will do precious little and just succeeds otherwise it will
> initialize the driver as it does now.
> 
> Is there really a point in having the CCI driver represented as a
> platform driver ? Not sure at all.

I'm not sure either.


Nicolas


From maxime.ripard at free-electrons.com  Tue May  7 11:27:15 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 07 May 2013 17:27:15 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51890C29.8000504@itooo.com>
References: <51890C29.8000504@itooo.com>
Message-ID: <51891D53.1030106@free-electrons.com>

Hi Greg,

Le 07/05/2013 16:14, Greg a ?crit :
> Thomas, Willy,

I'm not familiar with the Marvell code, so I won't be able to answer
your question, but the usual way of getting someone's attention is to
send him a mail directly, while keeping the list in Cc.

There's a high risk of your mail being overlooked or answered to very
late if you don't do so.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From Andrew.Murray at arm.com  Tue May  7 11:31:11 2013
From: Andrew.Murray at arm.com (Andrew Murray)
Date: Tue,  7 May 2013 16:31:11 +0100
Subject: [PATCH v9 0/3] of/pci: Provide common support for PCI DT parsing
Message-ID: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>

This patchset factors out duplicated code associated with parsing PCI
DT "ranges" properties across the architectures and introduces a
"ranges" parser. This parser "of_pci_range_parser" can be used directly
by ARM host bridge drivers enabling them to obtain ranges from device
trees.

I've included the Reviewed-by, Tested-by and Acked-by's received from
v5/v6/v7/v8 in this patchset, earlier versions of this patchset (v3) have been
tested-by:

Thierry Reding <thierry.reding at avionic-design.de>
Jingoo Han <jg1.han at samsung.com>

I've tested that this patchset builds and runs on ARM and that it builds on
PowerPC, x86_64, MIPS and Microblaze.

Compared to the v8 sent by Andrew Murray, the following changes have been made
(please note that the MIPS patch is unchanged from v8):

 * Remove the unification of pci_process_bridge_OF_ranges between PowerPC and
   Microblaze. Feedback from Bjorn and Benjamin (along with a NAK) suggested
   that this goes against their future direction (using more of struct
   pci_host_bridge and less of arch specific struct pci_controller).

Compared to the v7 sent by Andrew Murray, the following changes have been made
(please note that the first patch is unchanged from v7):

 * Rename of_pci_range_parser to of_pci_range_parser_init and
   of_pci_process_ranges to of_pci_range_parser_one as suggested by Grant
   Likely.

 * Reverted back to using a switch statement instead of if/else in
   pci_process_bridge_OF_ranges. Grant Likely highlighted this change from
   the original code which was unnecessary.

 * Squashed in a patch provided by Gabor Juhos which fixes build errors on
   MIPS found in the last patchset.

Compared to the v6 sent by Andrew Murray, the following changes have
been made in response to build errors/warnings:

 * Inclusion of linux/of_address.h in of_pci.c as suggested by Michal
   Simek to prevent compilation failures on Microblaze (and others) and his
   ack.

 * Use of externs, static inlines and a typo in linux/of_address.h in response
   to linker errors (multiple defination) on x86_64 as spotted by a kbuild test
   robot on (jcooper/linux.git mvebu/drivers)

 * Add EXPORT_SYMBOL_GPL to of_pci_range_parser function to be consistent
   with of_pci_process_ranges function

Compared to the v5 sent by Andrew Murray, the following changes have
been made:

 * Use of CONFIG_64BIT instead of CONFIG_[a32bitarch] as suggested by
   Rob Herring in drivers/of/of_pci.c

 * Added forward declaration of struct pci_controller in linux/of_pci.h
   to prevent compiler warning as suggested by Thomas Petazzoni

 * Improved error checking (!range check), removal of unnecessary be32_to_cpup
   call, improved formatting of struct of_pci_range_parser layout and
   replacement of macro with a static inline. All suggested by Rob Herring.

Compared to the v4 (incorrectly labelled v3) sent by Andrew Murray,
the following changes have been made:

 * Split the patch as suggested by Rob Herring

Compared to the v3 sent by Andrew Murray, the following changes have
been made:

 * Unify and move duplicate pci_process_bridge_OF_ranges functions to
   drivers/of/of_pci.c as suggested by Rob Herring

 * Fix potential build errors with Microblaze/MIPS

Compared to "[PATCH v5 01/17] of/pci: Provide support for parsing PCI DT
ranges property", the following changes have been made:

 * Correct use of IORESOURCE_* as suggested by Russell King

 * Improved interface and naming as suggested by Thierry Reding

Compared to the v2 sent by Andrew Murray, Thomas Petazzoni did:

 * Add a memset() on the struct of_pci_range_iter when starting the
   for loop in for_each_pci_range(). Otherwise, with an uninitialized
   of_pci_range_iter, of_pci_process_ranges() may crash.

 * Add parenthesis around 'res', 'np' and 'iter' in the
   for_each_of_pci_range macro definitions. Otherwise, passing
   something like &foobar as 'res' didn't work.

 * Rebased on top of 3.9-rc2, which required fixing a few conflicts in
   the Microblaze code.

v2:
  This follows on from suggestions made by Grant Likely
  (marc.info/?l=linux-kernel&m=136079602806328)

Andrew Murray (3):
  of/pci: Provide support for parsing PCI DT ranges property
  of/pci: mips: convert to common of_pci_range_parser
  of/pci: microblaze: convert to common of_pci_range_parser

 arch/microblaze/pci/pci-common.c |  106 ++++++++++++++------------------------
 arch/mips/pci/pci.c              |   50 ++++++-----------
 drivers/of/address.c             |   67 ++++++++++++++++++++++++
 include/linux/of_address.h       |   48 +++++++++++++++++
 4 files changed, 171 insertions(+), 100 deletions(-)



From Andrew.Murray at arm.com  Tue May  7 11:31:12 2013
From: Andrew.Murray at arm.com (Andrew Murray)
Date: Tue,  7 May 2013 16:31:12 +0100
Subject: [PATCH v9 1/3] of/pci: Provide support for parsing PCI DT ranges
 property
In-Reply-To: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>
References: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>
Message-ID: <1367940674-11987-2-git-send-email-Andrew.Murray@arm.com>

This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to write archiecture independent host bridge
drivers and mitigate against further duplication of DT parsing code.

This patch can be used in the following way:

	struct of_pci_range_parser parser;
	struct of_pci_range range;

	if (of_pci_range_parser_init(&parser, np))
		; //no ranges property

	for_each_of_pci_range(&parser, &range) {

		/*
			directly access properties of the address range, e.g.:
			range.pci_space, range.pci_addr, range.cpu_addr,
			range.size, range.flags

			alternatively obtain a struct resource, e.g.:
			struct resource res;
			of_pci_range_to_resource(&range, np, &res);
		*/
	}

Additionally the implementation takes care of adjacent ranges and merges them
into a single range (as was the case with powerpc and microblaze).

Signed-off-by: Andrew Murray <Andrew.Murray at arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Reviewed-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Tested-by: Linus Walleij <linus.walleij at linaro.org>
Tested-by: Jingoo Han <jg1.han at samsung.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/of/address.c       |   67 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/of_address.h |   48 +++++++++++++++++++++++++++++++
 2 files changed, 115 insertions(+), 0 deletions(-)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 04da786..fdd0636 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
 	return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
 }
 EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+
+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+				struct device_node *node)
+{
+	const int na = 3, ns = 2;
+	int rlen;
+
+	parser->node = node;
+	parser->pna = of_n_addr_cells(node);
+	parser->np = parser->pna + na + ns;
+
+	parser->range = of_get_property(node, "ranges", &rlen);
+	if (parser->range == NULL)
+		return -ENOENT;
+
+	parser->end = parser->range + rlen / sizeof(__be32);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
+
+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
+						struct of_pci_range *range)
+{
+	const int na = 3, ns = 2;
+
+	if (!range)
+		return NULL;
+
+	if (!parser->range || parser->range + parser->np > parser->end)
+		return NULL;
+
+	range->pci_space = parser->range[0];
+	range->flags = of_bus_pci_get_flags(parser->range);
+	range->pci_addr = of_read_number(parser->range + 1, ns);
+	range->cpu_addr = of_translate_address(parser->node,
+				parser->range + na);
+	range->size = of_read_number(parser->range + parser->pna + na, ns);
+
+	parser->range += parser->np;
+
+	/* Now consume following elements while they are contiguous */
+	while (parser->range + parser->np <= parser->end) {
+		u32 flags, pci_space;
+		u64 pci_addr, cpu_addr, size;
+
+		pci_space = be32_to_cpup(parser->range);
+		flags = of_bus_pci_get_flags(parser->range);
+		pci_addr = of_read_number(parser->range + 1, ns);
+		cpu_addr = of_translate_address(parser->node,
+				parser->range + na);
+		size = of_read_number(parser->range + parser->pna + na, ns);
+
+		if (flags != range->flags)
+			break;
+		if (pci_addr != range->pci_addr + range->size ||
+		    cpu_addr != range->cpu_addr + range->size)
+			break;
+
+		range->size += size;
+		parser->range += parser->np;
+	}
+
+	return range;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
+
 #endif /* CONFIG_PCI */
 
 /*
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index 0506eb5..4c2e6f2 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -4,6 +4,36 @@
 #include <linux/errno.h>
 #include <linux/of.h>
 
+struct of_pci_range_parser {
+	struct device_node *node;
+	const __be32 *range;
+	const __be32 *end;
+	int np;
+	int pna;
+};
+
+struct of_pci_range {
+	u32 pci_space;
+	u64 pci_addr;
+	u64 cpu_addr;
+	u64 size;
+	u32 flags;
+};
+
+#define for_each_of_pci_range(parser, range) \
+	for (; of_pci_range_parser_one(parser, range);)
+
+static inline void of_pci_range_to_resource(struct of_pci_range *range,
+					    struct device_node *np,
+					    struct resource *res)
+{
+	res->flags = range->flags;
+	res->start = range->cpu_addr;
+	res->end = range->cpu_addr + range->size - 1;
+	res->parent = res->child = res->sibling = NULL;
+	res->name = np->full_name;
+}
+
 #ifdef CONFIG_OF_ADDRESS
 extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
 extern bool of_can_translate_address(struct device_node *dev);
@@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
 #define pci_address_to_pio pci_address_to_pio
 #endif
 
+extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+			struct device_node *node);
+extern struct of_pci_range *of_pci_range_parser_one(
+					struct of_pci_range_parser *parser,
+					struct of_pci_range *range);
 #else /* CONFIG_OF_ADDRESS */
 #ifndef of_address_to_resource
 static inline int of_address_to_resource(struct device_node *dev, int index,
@@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
 {
 	return NULL;
 }
+
+static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+			struct device_node *node)
+{
+	return -1;
+}
+
+static inline struct of_pci_range *of_pci_range_parser_one(
+					struct of_pci_range_parser *parser,
+					struct of_pci_range *range)
+{
+	return NULL;
+}
 #endif /* CONFIG_OF_ADDRESS */
 
 
-- 
1.7.0.4



From Andrew.Murray at arm.com  Tue May  7 11:31:13 2013
From: Andrew.Murray at arm.com (Andrew Murray)
Date: Tue,  7 May 2013 16:31:13 +0100
Subject: [PATCH v9 2/3] of/pci: mips: convert to common of_pci_range_parser
In-Reply-To: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>
References: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>
Message-ID: <1367940674-11987-3-git-send-email-Andrew.Murray@arm.com>

This patch converts the pci_load_of_ranges function to use the new common
of_pci_range_parser.

Signed-off-by: Andrew Murray <Andrew.Murray at arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
Signed-off-by: Gabor Juhos <juhosg at openwrt.org>
Reviewed-by: Rob Herring <rob.herring at calxeda.com>
Reviewed-by: Grant Likely <grant.likely at secretlab.ca>
Tested-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/mips/pci/pci.c |   50 ++++++++++++++++++--------------------------------
 1 files changed, 18 insertions(+), 32 deletions(-)

diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0872f12..0d291e9 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -122,51 +122,37 @@ static void pcibios_scanbus(struct pci_controller *hose)
 #ifdef CONFIG_OF
 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
 {
-	const __be32 *ranges;
-	int rlen;
-	int pna = of_n_addr_cells(node);
-	int np = pna + 5;
+	struct of_pci_range range;
+	struct of_pci_range_parser parser;
 
 	pr_info("PCI host bridge %s ranges:\n", node->full_name);
-	ranges = of_get_property(node, "ranges", &rlen);
-	if (ranges == NULL)
-		return;
 	hose->of_node = node;
 
-	while ((rlen -= np * 4) >= 0) {
-		u32 pci_space;
+	if (of_pci_range_parser_init(&parser, node))
+		return;
+
+	for_each_of_pci_range(&parser, &range) {
 		struct resource *res = NULL;
-		u64 addr, size;
-
-		pci_space = be32_to_cpup(&ranges[0]);
-		addr = of_translate_address(node, ranges + 3);
-		size = of_read_number(ranges + pna + 3, 2);
-		ranges += np;
-		switch ((pci_space >> 24) & 0x3) {
-		case 1:		/* PCI IO space */
+
+		switch (range.flags & IORESOURCE_TYPE_BITS) {
+		case IORESOURCE_IO:
 			pr_info("  IO 0x%016llx..0x%016llx\n",
-					addr, addr + size - 1);
+				range.cpu_addr,
+				range.cpu_addr + range.size - 1);
 			hose->io_map_base =
-				(unsigned long)ioremap(addr, size);
+				(unsigned long)ioremap(range.cpu_addr,
+						       range.size);
 			res = hose->io_resource;
-			res->flags = IORESOURCE_IO;
 			break;
-		case 2:		/* PCI Memory space */
-		case 3:		/* PCI 64 bits Memory space */
+		case IORESOURCE_MEM:
 			pr_info(" MEM 0x%016llx..0x%016llx\n",
-					addr, addr + size - 1);
+				range.cpu_addr,
+				range.cpu_addr + range.size - 1);
 			res = hose->mem_resource;
-			res->flags = IORESOURCE_MEM;
 			break;
 		}
-		if (res != NULL) {
-			res->start = addr;
-			res->name = node->full_name;
-			res->end = res->start + size - 1;
-			res->parent = NULL;
-			res->sibling = NULL;
-			res->child = NULL;
-		}
+		if (res != NULL)
+			of_pci_range_to_resource(&range, node, res);
 	}
 }
 #endif
-- 
1.7.0.4



From Andrew.Murray at arm.com  Tue May  7 11:31:14 2013
From: Andrew.Murray at arm.com (Andrew Murray)
Date: Tue,  7 May 2013 16:31:14 +0100
Subject: [PATCH v9 3/3] of/pci: microblaze: convert to common
 of_pci_range_parser
In-Reply-To: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>
References: <1367940674-11987-1-git-send-email-Andrew.Murray@arm.com>
Message-ID: <1367940674-11987-4-git-send-email-Andrew.Murray@arm.com>

This patch converts the pci_load_of_ranges function to use the new common
of_pci_range_parser.

Signed-off-by: Andrew Murray <Andrew.Murray at arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
---
 arch/microblaze/pci/pci-common.c |  106 ++++++++++++++------------------------
 1 files changed, 38 insertions(+), 68 deletions(-)

diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 9ea521e..ba9e4a1 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -658,67 +658,42 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 				  struct device_node *dev, int primary)
 {
-	const u32 *ranges;
-	int rlen;
-	int pna = of_n_addr_cells(dev);
-	int np = pna + 5;
 	int memno = 0, isa_hole = -1;
-	u32 pci_space;
-	unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
 	unsigned long long isa_mb = 0;
 	struct resource *res;
+	struct of_pci_range range;
+	struct of_pci_range_parser parser;
 
 	pr_info("PCI host bridge %s %s ranges:\n",
 	       dev->full_name, primary ? "(primary)" : "");
 
-	/* Get ranges property */
-	ranges = of_get_property(dev, "ranges", &rlen);
-	if (ranges == NULL)
+	/* Check for ranges property */
+	if (of_pci_range_parser_init(&parser, dev))
 		return;
 
-	/* Parse it */
 	pr_debug("Parsing ranges property...\n");
-	while ((rlen -= np * 4) >= 0) {
+	for_each_of_pci_range(&parser, &range) {
 		/* Read next ranges element */
-		pci_space = ranges[0];
-		pci_addr = of_read_number(ranges + 1, 2);
-		cpu_addr = of_translate_address(dev, ranges + 3);
-		size = of_read_number(ranges + pna + 3, 2);
-
 		pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
-				pci_space, pci_addr);
+				range.pci_space, range.pci_addr);
 		pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
-					cpu_addr, size);
-
-		ranges += np;
+					range.cpu_addr, range.size);
 
 		/* If we failed translation or got a zero-sized region
 		 * (some FW try to feed us with non sensical zero sized regions
 		 * such as power3 which look like some kind of attempt
 		 * at exposing the VGA memory hole)
 		 */
-		if (cpu_addr == OF_BAD_ADDR || size == 0)
+		if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
 			continue;
 
-		/* Now consume following elements while they are contiguous */
-		for (; rlen >= np * sizeof(u32);
-		     ranges += np, rlen -= np * 4) {
-			if (ranges[0] != pci_space)
-				break;
-			pci_next = of_read_number(ranges + 1, 2);
-			cpu_next = of_translate_address(dev, ranges + 3);
-			if (pci_next != pci_addr + size ||
-			    cpu_next != cpu_addr + size)
-				break;
-			size += of_read_number(ranges + pna + 3, 2);
-		}
-
 		/* Act based on address space type */
 		res = NULL;
-		switch ((pci_space >> 24) & 0x3) {
-		case 1:		/* PCI IO space */
+		switch (range.flags & IORESOURCE_TYPE_BITS) {
+		case IORESOURCE_IO:
 			pr_info("  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
-			       cpu_addr, cpu_addr + size - 1, pci_addr);
+				range.cpu_addr, range.cpu_addr + range.size - 1,
+				range.pci_addr);
 
 			/* We support only one IO range */
 			if (hose->pci_io_size) {
@@ -726,11 +701,12 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 				continue;
 			}
 			/* On 32 bits, limit I/O space to 16MB */
-			if (size > 0x01000000)
-				size = 0x01000000;
+			if (range.size > 0x01000000)
+				range.size = 0x01000000;
 
 			/* 32 bits needs to map IOs here */
-			hose->io_base_virt = ioremap(cpu_addr, size);
+			hose->io_base_virt = ioremap(range.cpu_addr,
+						range.size);
 
 			/* Expect trouble if pci_addr is not 0 */
 			if (primary)
@@ -739,19 +715,20 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 			/* pci_io_size and io_base_phys always represent IO
 			 * space starting at 0 so we factor in pci_addr
 			 */
-			hose->pci_io_size = pci_addr + size;
-			hose->io_base_phys = cpu_addr - pci_addr;
+			hose->pci_io_size = range.pci_addr + range.size;
+			hose->io_base_phys = range.cpu_addr - range.pci_addr;
 
 			/* Build resource */
 			res = &hose->io_resource;
-			res->flags = IORESOURCE_IO;
-			res->start = pci_addr;
+			range.cpu_addr = range.pci_addr;
+
 			break;
-		case 2:		/* PCI Memory space */
-		case 3:		/* PCI 64 bits Memory space */
+		case IORESOURCE_MEM:
 			pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
-			       cpu_addr, cpu_addr + size - 1, pci_addr,
-			       (pci_space & 0x40000000) ? "Prefetch" : "");
+				range.cpu_addr, range.cpu_addr + range.size - 1,
+				range.pci_addr,
+				(range.pci_space & 0x40000000) ?
+				"Prefetch" : "");
 
 			/* We support only 3 memory ranges */
 			if (memno >= 3) {
@@ -759,13 +736,13 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 				continue;
 			}
 			/* Handles ISA memory hole space here */
-			if (pci_addr == 0) {
-				isa_mb = cpu_addr;
+			if (range.pci_addr == 0) {
+				isa_mb = range.cpu_addr;
 				isa_hole = memno;
 				if (primary || isa_mem_base == 0)
-					isa_mem_base = cpu_addr;
-				hose->isa_mem_phys = cpu_addr;
-				hose->isa_mem_size = size;
+					isa_mem_base = range.cpu_addr;
+				hose->isa_mem_phys = range.cpu_addr;
+				hose->isa_mem_size = range.size;
 			}
 
 			/* We get the PCI/Mem offset from the first range or
@@ -773,30 +750,23 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 			 * hole. If they don't match, bugger.
 			 */
 			if (memno == 0 ||
-			    (isa_hole >= 0 && pci_addr != 0 &&
+			    (isa_hole >= 0 && range.pci_addr != 0 &&
 			     hose->pci_mem_offset == isa_mb))
-				hose->pci_mem_offset = cpu_addr - pci_addr;
-			else if (pci_addr != 0 &&
-				 hose->pci_mem_offset != cpu_addr - pci_addr) {
+				hose->pci_mem_offset = range.cpu_addr -
+							range.pci_addr;
+			else if (range.pci_addr != 0 &&
+				 hose->pci_mem_offset != range.cpu_addr -
+							range.pci_addr) {
 				pr_info(" \\--> Skipped (offset mismatch) !\n");
 				continue;
 			}
 
 			/* Build resource */
 			res = &hose->mem_resources[memno++];
-			res->flags = IORESOURCE_MEM;
-			if (pci_space & 0x40000000)
-				res->flags |= IORESOURCE_PREFETCH;
-			res->start = cpu_addr;
 			break;
 		}
-		if (res != NULL) {
-			res->name = dev->full_name;
-			res->end = res->start + size - 1;
-			res->parent = NULL;
-			res->sibling = NULL;
-			res->child = NULL;
-		}
+		if (res != NULL)
+			of_pci_range_to_resource(&range, dev, res);
 	}
 
 	/* If there's an ISA hole and the pci_mem_offset is -not- matching
-- 
1.7.0.4



From jesper.nilsson at axis.com  Tue May  7 11:31:31 2013
From: jesper.nilsson at axis.com (Jesper Nilsson)
Date: Tue, 7 May 2013 17:31:31 +0200
Subject: [PATCH] proc: Use PDE attribute setting accessor functions
In-Reply-To: <1367918426-7076-1-git-send-email-geert@linux-m68k.org>
References: <1367918426-7076-1-git-send-email-geert@linux-m68k.org>
Message-ID: <20130507153131.GP8853@axis.com>

On Tue, May 07, 2013 at 11:20:26AM +0200, Geert Uytterhoeven wrote:
> arch/arm/mach-msm/last_radio_log.c: In function 'msm_init_last_radio_log':
> arch/arm/mach-msm/last_radio_log.c:69:7: error: dereferencing pointer to incomplete type
> 
> arch/cris/kernel/profile.c: In function 'init_cris_profile':
> arch/cris/kernel/profile.c:79:8: error: dereferencing pointer to incomplete type
> 
> Use proc_set_size(), cfr. commit 271a15eabe094538d958dc68ccfc9c36b699247a
> ("proc: Supply PDE attribute setting accessor functions")
> 
> Signed-off-by: Geert Uytterhoeven <geert at linux-m68k.org>

For the CRIS-part:

Acked-by: Jesper Nilsson <jesper.nilsson at axis.com>

/^JN - Jesper Nilsson
-- 
               Jesper Nilsson -- jesper.nilsson at axis.com


From cov at codeaurora.org  Tue May  7 11:48:26 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Tue, 07 May 2013 11:48:26 -0400
Subject: [RFC PATCH 0/2] ARM: Remove any correlation between IPC and
 BogoMips value
In-Reply-To: <20130507090849.GC25387@mudshark.cambridge.arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <5187EFF3.6010005@codeaurora.org>
 <20130507090849.GC25387@mudshark.cambridge.arm.com>
Message-ID: <5189224A.70501@codeaurora.org>

On 05/07/2013 05:08 AM, Will Deacon wrote:
> On Mon, May 06, 2013 at 07:01:23PM +0100, Christopher Covington wrote:
>> Hi Will,
>>
>> On 05/03/2013 01:35 PM, Will Deacon wrote:
>>> Hi all,
>>>
>>> This small patch set may look a little over a month late, but there is a
>>> serious reason for posting it.
>>>
>>> When I moved the ARM delay loop over to using the architected timers
>>> rather than the CPU spinning loop (which has all the problems associated
>>> with cpu frequency scaling and what-not) I thought I was doing something
>>> useful for the port. However, it turns out that a surprising number of
>>> people have complained, and continue to complain, about the drop in
>>> their `BogoMIPs score'.
>>
>> Have you considered adding the old code back in, but in a form that's not at
>> all referenced by the delay loop code and just calculates CPU-based bogomips?
> 
> That seems like a lot of effort in order to preserve something that isn't
> even meaningful. We might be better just zeroing the value, but then we'll
> inevitably get bug reports of it being `wrong'.

If I were in to filing bug reports about bogomips values, I would be just as
likely to do it for 1, 10000, 99999, and get_random_bytes(...) as for 0.

> Plus, the calibration during boot introduces a brief delay when onlining
> each core whereas this can be skipped when using a constant timer.

If it were configurable, that might give people a reason to weigh whether they
really cared about knowing bogomips at the cost of boot time.

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From valentin.longchamp at keymile.com  Tue May  7 11:52:18 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Tue,  7 May 2013 17:52:18 +0200
Subject: [RFC PATCH] Alternative clk gate ctrl for Kirkwood variants
Message-ID: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>

This series introduces a clk gate ctrl for the kirkwood variants embedded in the
Prestera SoCs.

This would allow to get rid of the workaround for the km_kirkwood board support
file that was added previously because of the lack of DT clk gate support.

Valentin Longchamp (3):
  clk: mvebu: add gate ctrl for Prestera kirkwood variants
  ARM: kirkwood: look for alternative gate ctrl of node
  ARM: kirkwood: remove clock gating disabling for km_kirkwood

 .../devicetree/bindings/clock/mvebu-gated-clock.txt   | 17 +++++++++++++++++
 arch/arm/boot/dts/kirkwood-98dx4122.dtsi              |  7 +++++++
 arch/arm/mach-kirkwood/board-dt.c                     |  4 ++++
 arch/arm/mach-kirkwood/board-km_kirkwood.c            | 15 ---------------
 drivers/clk/mvebu/clk-gating-ctrl.c                   | 19 +++++++++++++++++++
 5 files changed, 47 insertions(+), 15 deletions(-)

-- 
1.8.0.1



From valentin.longchamp at keymile.com  Tue May  7 11:52:20 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Tue,  7 May 2013 17:52:20 +0200
Subject: [PATCH 2/3] ARM: kirkwood: look for alternative gate ctrl of node
In-Reply-To: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <1367941941-19152-3-git-send-email-valentin.longchamp@keymile.com>

The search for the gate ctrl of node must now also look for the
introduced compatible node.

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
---
 arch/arm/mach-kirkwood/board-dt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 7904758..3e607c9 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -44,6 +44,10 @@ static void __init kirkwood_legacy_clk_init(void)
 	struct of_phandle_args clkspec;
 	struct clk *clk;
 
+	if (np == NULL)
+		np = of_find_compatible_node(NULL, NULL,
+			"marvell,prestera-kw-gating-clock");
+
 	clkspec.np = np;
 	clkspec.args_count = 1;
 
-- 
1.8.0.1



From valentin.longchamp at keymile.com  Tue May  7 11:52:21 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Tue,  7 May 2013 17:52:21 +0200
Subject: [PATCH 3/3] ARM: kirkwood: remove clock gating disabling for
 km_kirkwood
In-Reply-To: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <1367941941-19152-4-git-send-email-valentin.longchamp@keymile.com>

A new clock gating controller is available for the prestera-kw kirkwood
variant. This controller does not enable the unavailable clk gates.

This patch removes the fixes from the board-km_kirkwood file and enables
the correct clk gating controller for kirkwood-98dx4122.dtsi.

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
---
 arch/arm/boot/dts/kirkwood-98dx4122.dtsi   |  7 +++++++
 arch/arm/mach-kirkwood/board-km_kirkwood.c | 15 ---------------
 2 files changed, 7 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
index 3271e4c..8c73673 100644
--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
@@ -27,5 +27,12 @@
 				marvell,function = "uart1";
 			};
 		};
+
+		gate_clk: clock-gating-control at 2011c {
+			compatible = "marvell,prestera-kw-gating-clock";
+			reg = <0x2011c 0x4>;
+			clocks = <&core_clk 0>;
+			#clock-cells = <1>;
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
index 44e4605..f1a6ab7 100644
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -25,20 +25,5 @@ static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
 
 void __init km_kirkwood_init(void)
 {
-	struct clk *sata_clk;
-	/*
-	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
-	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
-	 * devices are also not present in this variant, their clocks get
-	 * disabled because unused when clk_disable_unused() gets called.
-	 * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
-	 */
-	sata_clk = clk_get_sys("sata_mv.0", "0");
-	if (!IS_ERR(sata_clk))
-		sata_clk->flags |= CLK_IGNORE_UNUSED;
-	sata_clk = clk_get_sys("sata_mv.0", "1");
-	if (!IS_ERR(sata_clk))
-		sata_clk->flags |= CLK_IGNORE_UNUSED;
-
 	kirkwood_ge00_init(&km_kirkwood_ge00_data);
 }
-- 
1.8.0.1



From valentin.longchamp at keymile.com  Tue May  7 11:52:19 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Tue,  7 May 2013 17:52:19 +0200
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood variants
In-Reply-To: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>

The kirkwood device found in the Prestera SoCs does not have all the
peripherals of its the usual kirkwood SoCs. There are hence missing
clocks in the SoCs.

This patch registers another gate controller for the kirkwood that
registers only the available clocks of this kirkwood variant.

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
---
 .../devicetree/bindings/clock/mvebu-gated-clock.txt   | 17 +++++++++++++++++
 drivers/clk/mvebu/clk-gating-ctrl.c                   | 19 +++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index cffc93d..7f494e90 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -92,10 +92,27 @@ ID	Clock	Peripheral
 19	ge1	Gigabit Ethernet 1
 20	tdm	Time Division Mplx
 
+The following is a list of provided IDs for Kirkwood Prestera variant:
+ID	Clock	Peripheral
+-----------------------------------
+0	ge0	Gigabit Ethernet 0
+2	pex0	PCIe Cntrl 0
+3	usb0	USB Host 0
+4	sdio	SDIO Cntrl
+5	tsu	Transp. Stream Unit
+6	dunit	SDRAM Cntrl
+7	runit	Runit
+8	xor0	XOR DMA 0
+16	xor1	XOR DMA 1
+17	crypto	CESA engine
+19	ge1	Gigabit Ethernet 1
+
+
 Required properties:
 - compatible : shall be one of the following:
 	"marvell,dove-gating-clock" - for Dove SoC clock gating
 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
+	"marvell,prestera-kw-gating-clock" - for Preseta SoC clock gating
 - reg : shall be the register address of the Clock Gating Control register
 - #clock-cells : from common clock binding; shall be set to 1
 
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index ebf141d..ba37802 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -203,6 +203,21 @@ static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
 	{ "tdm", NULL, 20 },
 	{ }
 };
+
+static const struct mvebu_soc_descr __initconst prestera_kw_gating_descr[] = {
+	{ "ge0", NULL, 0 },
+	{ "pex0", NULL, 2 },
+	{ "usb0", NULL, 3 },
+	{ "sdio", NULL, 4 },
+	{ "tsu", NULL, 5 },
+	{ "runit", NULL, 7 },
+	{ "xor0", NULL, 8 },
+	{ "powersave", "cpuclk", 11 },
+	{ "xor1", NULL, 16 },
+	{ "crypto", NULL, 17 },
+	{ "ge1", NULL, 19 },
+	{ }
+};
 #endif
 
 static const __initdata struct of_device_id clk_gating_match[] = {
@@ -232,6 +247,10 @@ static const __initdata struct of_device_id clk_gating_match[] = {
 		.compatible = "marvell,kirkwood-gating-clock",
 		.data = kirkwood_gating_descr,
 	},
+	{
+		.compatible = "marvell,prestera-kw-gating-clock",
+		.data = prestera_kw_gating_descr,
+	},
 #endif
 
 	{ }
-- 
1.8.0.1



From cov at codeaurora.org  Tue May  7 11:52:45 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Tue, 07 May 2013 11:52:45 -0400
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <CAFEAcA9jBSpN2p9ZaU+_gX41Ke3nvpSKVrWV8Rioy_ioadKCgg@mail.gmail.com>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
 <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
 <87txmfo0rl.fsf@rustcorp.com.au>
 <CAFEAcA9jBSpN2p9ZaU+_gX41Ke3nvpSKVrWV8Rioy_ioadKCgg@mail.gmail.com>
Message-ID: <5189234D.3040208@codeaurora.org>

On 05/07/2013 08:19 AM, Peter Maydell wrote:
> On 7 May 2013 05:46, Rusty Russell <rusty at rustcorp.com.au> wrote:
>> Peter Maydell <peter.maydell at linaro.org> writes:
>>> That all looks like sensible QEMU implementation possibilities
>>> but it seems to be a bit of a non-sequitur from "how do we
>>> tell the kernel to actually use this?"
>>
>> You enable the feature in the virtio console device, and a kernel
>> compiled with EARLY_PRINTK will use it?
> 
> Well, at the moment EARLY_PRINTK is hardcoded to
> "use some specific UART or equivalent selected at
> compile time". So the equivalent presumably would
> be to hard-compile "use virtio-console", but then
> how does that code know where the virtio-console
> is in the address space?

arm64 uses a kernel argument.

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From peter.maydell at linaro.org  Tue May  7 11:58:23 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Tue, 7 May 2013 16:58:23 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <5189234D.3040208@codeaurora.org>
References: <1366974299-17877-1-git-send-email-pranavkumar@linaro.org>
 <BA2076A6-0688-4E5C-85F9-A9CA8FD75782@suse.de>
 <87obcyc9sh.fsf@rustcorp.com.au>
 <336C59AA-D5D7-472E-A8DA-EEB413DD6C68@suse.de>
 <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
 <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
 <87txmfo0rl.fsf@rustcorp.com.au>
 <CAFEAcA9jBSpN2p9ZaU+_gX41Ke3nvpSKVrWV8Rioy_ioadKCgg@mail.gmail.com>
 <5189234D.3040208@codeaurora.org>
Message-ID: <CAFEAcA-eSB=_UT0-L7o=2o6JGv0WkXZv5UPxPVqLRxjUZQegFA@mail.gmail.com>

On 7 May 2013 16:52, Christopher Covington <cov at codeaurora.org> wrote:
> On 05/07/2013 08:19 AM, Peter Maydell wrote:
>> Well, at the moment EARLY_PRINTK is hardcoded to
>> "use some specific UART or equivalent selected at
>> compile time". So the equivalent presumably would
>> be to hard-compile "use virtio-console", but then
>> how does that code know where the virtio-console
>> is in the address space?
>
> arm64 uses a kernel argument.

This mixes up "information that the user provides to the
kernel" (ie configuration) with "information that QEMU or
kvmtool should provide to the kernel" (ie hardware
description), and would require QEMU/kvmtool to parse
the user's commandline tool to figure out if they
needed to override it or edit it (or alternatively,
would require the user to know internal details of
QEMU/kvmtool's address map for the guest). I think it
would be nicer to keep them separate.

thanks
-- PMM


From itooo at itooo.com  Tue May  7 12:01:14 2013
From: itooo at itooo.com (Greg)
Date: Tue, 07 May 2013 18:01:14 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51891D53.1030106@free-electrons.com>
References: <51890C29.8000504@itooo.com> <51891D53.1030106@free-electrons.com>
Message-ID: <5189254A.7010703@itooo.com>

Le 07/05/2013 17:27, Maxime Ripard a ?crit :
> Hi Greg,
>
> Le 07/05/2013 16:14, Greg a ?crit :
>> Thomas, Willy,
> I'm not familiar with the Marvell code, so I won't be able to answer
> your question, but the usual way of getting someone's attention is to
> send him a mail directly, while keeping the list in Cc.
>
> There's a high risk of your mail being overlooked or answered to very
> late if you don't do so.
>
>
Thanks for the advice!

By the way, the problem might not be marvell-related since the irq 
number is given by :
> irq_of_parse_and_map(dn, 0);

I enabled debug output in drivers/of/irq.c and it reads :
> of_irq_map_one: dev=/soc/ethernet at d0070000, index=0
>  intspec=8 intlen=1
>  intsize=1 intlen=1
> of_irq_map_raw: par=/interrupt-controller at d0020000,intspec=[0x00000008 
> 0x00000003...],ointsize=1
> of_irq_map_raw: ipar=/interrupt-controller at d0020000, size=1
>  -> addrsize=1
>  -> got it !

I'll continue digging into this once the headache I got while reading 
the code is gone ;-)


From arnd at arndb.de  Tue May  7 12:02:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 18:02:10 +0200
Subject: [GIT PULL] ARM: arm-soc platform updates for 3.10, part 2
In-Reply-To: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
Message-ID: <1367942534-2934003-2-git-send-email-arnd@arndb.de>

These patches are all for Renesas shmobile, and depend on the earlier
pinctrl updates. Remarkably, this adds support for three new SoCs:
r8a73a4, r8a73a4 and r8a7778. The bulk of the code added for these is
for pinctrl (using the new subsystem) and for clocks (not yet using the
common clock subsystem). The latter will have to get converted in one
of the upcoming releases, but shmobile is not ready for that yet.

The series also contains Renesas shmobile board changes, adding one
board file for each of the three new SoCs.  These boards are using a
mix of classic and device-tree based probing, as there is still a lot of
infrastructure in shmobile that has not been converted to DT yet. Once
those are resolved to the degree that no board specific setup code is
needed, they can get folded into the respective SoC setup files.

Conflicts:
- A line added in board-armadillo800eva.c conflicts with a
  changed line.


-------------------------------------------------------------

The following changes since commit

   150a8dc Merge tag 'boards-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/soc-for-linus-2

you to fetch changes up to

   9251c6c Merge tag 'renesas-boards-lager-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2


-------------------------------------------------------------

Arnd Bergmann (3):
      Merge tag 'renesas-defconfig-bockw-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2
      Merge tag 'renesas-boards-bockw-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2
      Merge tag 'soc-for-linus-2' into for-next

Bastian Hecht (1):
      ARM: shmobile: r8a7740: Migrate from INTC to GIC

Guennadi Liakhovetski (9):
      ARM: shmobile: sh73a0: wait for completion when kicking the clock
      ARM: shmobile: sh73a0: add irqpin DT nodes
      ARM: shmobile: sh73a0: add a TWD clock
      ARM: shmobile: kzm9g-reference: add ethernet support
      ARM: shmobile: mackerel: SDHI resources do not have to be numbered
      ARM: shmobile: mackerel: remove OCR masks, where regulators are used
      ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio
      ARM: shmobile: mackerel: add interrupt names for SDHI0
      ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection

Kuninori Morimoto (21):
      ARM: shmobile: add R8A7778 basis support
      ARM: shmobile: r8a7778 SCIF support
      ARM: shmobile: r8a73a4: add thermal driver support
      ARM: shmobile: sh73a0: remove DIV4_ZT* clocks
      ARM: shmobile: sh7372: remove DIV4_ZT* clocks
      ARM: shmobile: add struct clk_ratio and fixed ratio clock macro
      ARM: shmobile: sh7372: use fixed ratio clock
      ARM: shmobile: sh73a0: use fixed ratio clock
      ARM: shmobile: r8a7740: tidyup comment/implementation mismatch
      ARM: shmobile: r8a7740: use fixed ratio clock
      ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock
      ARM: shmobile: sh7372: move global functions to sh7372.h
      ARM: shmobile: sh73a0: move global functions to sh73a0.h
      ARM: shmobile: r8a7740: move global functions to r8a7740.h
      ARM: shmobile: r8a7779: move global functions to r8a7779.h
      ARM: shmobile: add R-Car M1A Bock-W platform support
      ARM: shmobile: r8a7778: remove pointless PLATFORM_INFO()
      ARM: shmobile: r8a7778: add r8a7778_init_irq_extpin()
      ARM: shmobile: bockw: enable SMSC ethernet on defconfig
      ARM: shmobile: bockw: add SMSC ethernet support
      ARM: shmobile: bockw: enable network settings on bootargs

Laurent Pinchart (14):
      sh-pfc: Fix compiler warning when BUG()
      sh: sh7269: Fix compilation by adding missing includes
      sh-pfc: r8a7779: Remove function GPIOs
      sh-pfc: r8a7779: Don't use GPIO enum entries
      ARM: shmobile: r8a7779: Remove all GPIOs
      gpio-rcar: Add pinctrl support
      ARM: shmobile: marzen: Add GPIO LEDs
      sh-pfc: Make function GPIOs support optional
      sh-pfc: Make GPIO support optional
      sh-pfc: Skip gpiochip registration when no GPIO resource is found
      sh-pfc: Configure pins as GPIOs at request time when handled externally
      ARM: shmobile: r8a7779: Register GPIO devices
      sh-pfc: r8a7779: Remove GPIO data
      sh-pfc: r8a7779: Split DU input and output pixel clocks

Magnus Damm (30):
      ARM: shmobile: Initial r8a73a4 SoC support V3
      ARM: shmobile: r8a73a4 SCIF support V3
      ARM: shmobile: r8a73a4 IRQC support V2
      ARM: shmobile: r8a73a4 PFC support
      ARM: shmobile: Disallow PINCTRL without GPIOLIB
      ARM: shmobile: Initial r8a7790 SoC support
      ARM: shmobile: r8a7790 SCIF support
      ARM: shmobile: r8a7790 IRQC support
      ARM: shmobile: r8a7790 PFC support
      gpio: Renesas R-Car GPIO driver V3
      sh-pfc: Add r8a73a4 pinmux support
      sh-pfc: r8a73a4: Support sparse GPIO numbers
      sh-pfc: r8a73a4: GPIO IRQ support
      sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
      sh-pfc: r8a73a4: Add SCIF pin groups and functions
      sh-pfc: r8a73a4: Add IRQC pin groups and functions
      sh-pfc: r8a73a4: Remove SCIF function GPIOS
      sh-pfc: r8a73a4: Remove IRQC function GPIOS
      ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
      ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
      sh-pfc: r8a73a4: Remove function GPIOs
      ARM: shmobile: r8a73a4: Remove all GPIO enums
      sh-pfc: r8a73a4: Remove unused GPIO bias data
      ARM: shmobile: APE6EVM base support
      ARM: shmobile: APE6EVM PFC support
      ARM: shmobile: APE6EVM LAN9220 support
      ARM: shmobile: Initial r8a7790 Lager board support
      ARM: shmobile: Add second I/O range for r8a7790 PFC
      ARM: shmobile: force enable of r8a7790 arch timer
      ARM: shmobile: use r8a7790 timer setup code on Lager

Olof Johansson (2):
      Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2
      Merge tag 'renesas-boards-lager-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2

Sergei Shtylyov (1):
      ARM: shmobile: R8A7778: add Ether support

Simon Horman (5):
      Merge tag 'renesas-intc-external-irq2-for-v3.10' into soc-base
      Merge branch 'soc' into pinmux-base
      Merge tag 'renesas-pinmux2-for-v3.10' into boards-base
      Merge branch 'soc-r8a7778' into boards-bockw-base
      Merge branch 'soc-r8a7790' into boards-lager

Takashi YOSHII (2):
      ARM: shmobile: r8a73a4 SoC 64-bit DT support
      ARM: shmobile: r8a7790 SoC 64-bit DT support

 arch/arm/Kconfig                               |    2 +-
 arch/arm/boot/dts/Makefile                     |    3 +
 arch/arm/boot/dts/r8a73a4-ape6evm.dts          |   52 +
 arch/arm/boot/dts/r8a73a4.dtsi                 |   94 +
 arch/arm/boot/dts/r8a7778-bockw.dts            |   32 +
 arch/arm/boot/dts/r8a7778.dtsi                 |   35 +
 arch/arm/boot/dts/r8a7790-lager.dts            |   31 +
 arch/arm/boot/dts/r8a7790.dtsi                 |   63 +
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts   |   13 +
 arch/arm/boot/dts/sh73a0.dtsi                  |   81 +
 arch/arm/configs/bockw_defconfig               |   94 +
 arch/arm/mach-shmobile/Kconfig                 |   48 +-
 arch/arm/mach-shmobile/Makefile                |    6 +
 arch/arm/mach-shmobile/board-ape6evm.c         |   94 +
 arch/arm/mach-shmobile/board-armadillo800eva.c |   35 +-
 arch/arm/mach-shmobile/board-bockw.c           |   81 +
 arch/arm/mach-shmobile/board-lager.c           |   46 +
 arch/arm/mach-shmobile/board-mackerel.c        |  111 +-
 arch/arm/mach-shmobile/board-marzen.c          |   32 +
 arch/arm/mach-shmobile/clock-r8a73a4.c         |  115 ++
 arch/arm/mach-shmobile/clock-r8a7740.c         |  114 +-
 arch/arm/mach-shmobile/clock-r8a7778.c         |  107 +
 arch/arm/mach-shmobile/clock-r8a7779.c         |  196 +-
 arch/arm/mach-shmobile/clock-r8a7790.c         |   93 +
 arch/arm/mach-shmobile/clock-sh7372.c          |   50 +-
 arch/arm/mach-shmobile/clock-sh73a0.c          |  115 +-
 arch/arm/mach-shmobile/clock.c                 |   13 +
 arch/arm/mach-shmobile/include/mach/clock.h    |   39 +
 arch/arm/mach-shmobile/include/mach/common.h   |   54 -
 arch/arm/mach-shmobile/include/mach/r8a73a4.h  |    8 +
 arch/arm/mach-shmobile/include/mach/r8a7740.h  |    9 +
 arch/arm/mach-shmobile/include/mach/r8a7778.h  |   32 +
 arch/arm/mach-shmobile/include/mach/r8a7779.h  |  330 +--
 arch/arm/mach-shmobile/include/mach/r8a7790.h  |    9 +
 arch/arm/mach-shmobile/include/mach/sh7372.h   |   12 +
 arch/arm/mach-shmobile/include/mach/sh73a0.h   |   15 +
 arch/arm/mach-shmobile/intc-r8a7740.c          |  641 +-----
 arch/arm/mach-shmobile/setup-r8a73a4.c         |  202 ++
 arch/arm/mach-shmobile/setup-r8a7740.c         |  192 +-
 arch/arm/mach-shmobile/setup-r8a7778.c         |  244 +++
 arch/arm/mach-shmobile/setup-r8a7779.c         |   58 +-
 arch/arm/mach-shmobile/setup-r8a7790.c         |  150 ++
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c        |    2 +
 drivers/gpio/Kconfig                           |    6 +
 drivers/gpio/Makefile                          |    1 +
 drivers/gpio/gpio-rcar.c                       |  396 ++++
 drivers/pinctrl/sh-pfc/Kconfig                 |    5 +
 drivers/pinctrl/sh-pfc/Makefile                |    1 +
 drivers/pinctrl/sh-pfc/core.c                  |   41 +-
 drivers/pinctrl/sh-pfc/core.h                  |    1 +
 drivers/pinctrl/sh-pfc/gpio.c                  |   45 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c           | 2587 ++++++++++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c           |   64 +-
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c           |  479 +----
 drivers/pinctrl/sh-pfc/pinctrl.c               |   11 +
 include/linux/platform_data/gpio-rcar.h        |   26 +
 56 files changed, 5588 insertions(+), 1828 deletions(-)


From arnd at arndb.de  Tue May  7 12:02:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 18:02:11 +0200
Subject: [GIT PULL] ARM: arm-soc platform updates for 3.10, part 3
In-Reply-To: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
Message-ID: <1367942534-2934003-3-git-send-email-arnd@arndb.de>

This is the third and smallest of the SoC specific updates.
Changes include:

* SMP support for the Xilinx zynq platform
* Smaller imx changes
* LPAE support for mvebu
* Moving the orion5x, kirkwood, dove and mvebu platforms
  to a common "mbus" driver for their internal devices.

It would be good to get feedback on the location of the "mbus"
driver. Since this is used on multiple platforms may potentially
get shared with other architectures (powerpc and arm64), it
was moved to drivers/bus/. We expect other similar drivers to
get moved to the same place in order to avoid creating more
top-level directories under drivers/ or cluttering up the
messy drivers/misc/ even more.

Conflicts:
 - drivers/gpio/gpio-pl061.c had a trivial add/add conflict that
   got resolved in two different ways, both of which are ok.


-------------------------------------------------------------

The following changes since commit

   48f934c Merge tag 'soc-for-linus-2' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/soc-for-linus-3

you to fetch changes up to

   5c5f042 ARM: imx: reset_controller may be disabled

-------------------------------------------------------------

Anson Huang (3):
      ARM: imx: enable anatop suspend/resume
      ARM: imx: enable periphery well bias for suspend
      ARM: imx: enable RBC to support anatop LPM mode

Arnd Bergmann (6):
      Merge branch 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx into next/soc2
      Merge branch 'gic/cleanup' into next/soc2
      Merge tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-soc-r8a7778-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      ARM: imx: reset_controller may be disabled
      Merge tag 'soc-for-linus-3' into for-next

Fabio Estevam (3):
      ARM: mach-imx: anatop: Include "common.h"
      ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
      ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS

Gregory CLEMENT (1):
      ARM: mvebu: Limit the DMA zone when LPAE is selected

Gwenhael Goavec-Merou (1):
      ARM: imx1: mm: add call to mxc_device_init

Jason Cooper (2):
      Merge tag 'tags/cleanup_for_v3.10' into mvebu/soc
      Merge tag 'tags/drivers_for_v3.10' into mvebu/soc

Kuninori Morimoto (2):
      ARM: shmobile: r8a7779: add each clocks ratio on comment area
      sh-pfc: r8a7779: tidyup intc_irq3_b typo

Lior Amsalem (1):
      ARM: mvebu: Align the internal registers virtual base to support LPAE

Markus Pargmann (1):
      ARM: imx27, imx5: Add kconfig selects for cpufreq-cpu0

Martin Fuzzey (1):
      ARM: i.MX53 Add the cko1, cko2 clock outputs.

Michal Simek (7):
      arm: zynq: Load scu baseaddress at run time
      arm: zynq: Move slcr initialization to separate file
      arm: zynq: Add support for system reset
      arm: zynq: Get rid of xilinx function prefix
      arm: zynq: Add smp_twd timer
      arm: zynq: Add smp support
      arm: zynq: Add hotplug support

Neil Greatorex (1):
      bus: mvebu-mbus: Restore checking for coherency fabric hardware

Olof Johansson (6):
      Merge tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-pinmux-fixes-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-soc-r8a7790-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc2
      Merge tag 'soc_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/soc2

Philipp Zabel (14):
      ARM i.MX53: Add GPU clocks to clock tree
      ARM i.MX6q: export imx6q_revision
      ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
      ARM i.MX53: fix ldb di divider and selector clocks
      ARM i.MX6q: fix ldb di divider and selector clocks
      ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
      ARM i.MX6q: set the LDB serial clock parent to the video PLL
      ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
      staging: drm/imx: Use SRC to reset IPU
      ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
      ARM i.MX53: Remove unused tve_gate clkdev entry
      ARM i.MX53: make tve_ext_sel propagate rate change to PLL
      ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
      ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock

Sascha Hauer (1):
      ARM: i.MX5: Add PATA and SRTC clocks

Sergei Shtylyov (1):
      ARM: shmobile: R8A7779: add Ether support

Shawn Guo (6):
      Merge tag 'imx-fixes-3.9-5' into imx/soc
      Merge tag 'imx-cleanup-3.10' into imx/soc
      Merge remote-tracking branch 'pza/reset/for_v3.10' into imx/soc
      ARM: imx: do not use regmap_read for ANADIG_DIGPROG
      ARM: imx: add initial imx6dl support
      ARM: imx: do not bring up unavailable cores

Simon Guinot (1):
      ARM: Orion: add dbg_show function to gpio-orion driver

Thomas Petazzoni (8):
      bus: introduce an Marvell EBU MBus driver
      bus: mvebu: fix mistake in PCIe window target attribute for Kirkwood
      arm: mach-mvebu: convert to use mvebu-mbus driver
      arm: mach-kirkwood: convert to use mvebu-mbus driver
      arm: mach-dove: convert to use mvebu-mbus driver
      arm: mach-orion5x: convert to use mvebu-mbus driver
      arm: mach-mv78xx0: convert to use the mvebu-mbus driver
      arm: plat-orion: remove addr-map code

 .../devicetree/bindings/clock/imx5-clock.txt       |  14 +-
 .../devicetree/bindings/clock/imx6q-clock.txt      |   3 +
 .../devicetree/bindings/reset/fsl,imx-src.txt      |  49 ++
 .../bindings/staging/imx-drm/fsl-imx-drm.txt       |   3 +
 arch/arm/Kconfig                                   |   4 +
 arch/arm/Kconfig.debug                             |   4 +-
 arch/arm/boot/dts/armada-370-xp.dtsi               |   5 -
 arch/arm/boot/dts/zynq-7000.dtsi                   |   7 +
 arch/arm/configs/imx_v4_v5_defconfig               |   1 +
 arch/arm/configs/imx_v6_v7_defconfig               |   1 +
 arch/arm/include/debug/mvebu.S                     |   2 +-
 arch/arm/mach-dove/Makefile                        |   2 +-
 arch/arm/mach-dove/addr-map.c                      | 125 ---
 arch/arm/mach-dove/board-dt.c                      |   2 +-
 arch/arm/mach-dove/common.c                        |  39 +-
 arch/arm/mach-dove/common.h                        |   2 +-
 arch/arm/mach-dove/include/mach/dove.h             |   5 +
 arch/arm/mach-imx/Kconfig                          |  10 +-
 arch/arm/mach-imx/Makefile                         |   1 +
 arch/arm/mach-imx/anatop.c                         | 103 +++
 arch/arm/mach-imx/clk-imx51-imx53.c                |  75 +-
 arch/arm/mach-imx/clk-imx6q.c                      | 126 ++-
 arch/arm/mach-imx/clk.h                            |  17 +
 arch/arm/mach-imx/common.h                         |  10 +-
 arch/arm/mach-imx/gpc.c                            |  23 +-
 arch/arm/mach-imx/mach-imx6q.c                     |  74 +-
 arch/arm/mach-imx/mm-imx1.c                        |   2 +
 arch/arm/mach-imx/mxc.h                            |  11 +
 arch/arm/mach-imx/platsmp.c                        |   4 +-
 arch/arm/mach-imx/pm-imx6q.c                       |   4 +-
 arch/arm/mach-imx/src.c                            |  66 ++
 arch/arm/mach-kirkwood/Makefile                    |   2 +-
 arch/arm/mach-kirkwood/addr-map.c                  |  91 ---
 arch/arm/mach-kirkwood/board-dt.c                  |   2 +-
 arch/arm/mach-kirkwood/common.c                    |  38 +-
 arch/arm/mach-kirkwood/common.h                    |   2 +-
 arch/arm/mach-kirkwood/include/mach/kirkwood.h     |   7 +-
 arch/arm/mach-kirkwood/pcie.c                      |   1 -
 arch/arm/mach-mv78xx0/Makefile                     |   2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |  93 ---
 arch/arm/mach-mv78xx0/common.c                     |  10 +-
 arch/arm/mach-mv78xx0/include/mach/mv78xx0.h       |   9 +-
 arch/arm/mach-mv78xx0/pcie.c                       |  21 +-
 arch/arm/mach-mvebu/Kconfig                        |   2 +
 arch/arm/mach-mvebu/Makefile                       |   2 +-
 arch/arm/mach-mvebu/addr-map.c                     | 137 ----
 arch/arm/mach-mvebu/armada-370-xp.c                |  18 +
 arch/arm/mach-mvebu/armada-370-xp.h                |   8 +-
 arch/arm/mach-mvebu/platsmp.c                      |   2 +
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/addr-map.c                   | 155 ----
 arch/arm/mach-orion5x/board-dt.c                   |   2 +-
 arch/arm/mach-orion5x/common.c                     |  49 +-
 arch/arm/mach-orion5x/common.h                     |  13 +-
 arch/arm/mach-orion5x/d2net-setup.c                |   4 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |  13 +-
 arch/arm/mach-orion5x/dns323-setup.c               |   3 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |   4 +-
 arch/arm/mach-orion5x/include/mach/orion5x.h       |   6 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |   8 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |   4 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |   4 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |   4 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |   3 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |   3 +-
 arch/arm/mach-orion5x/net2big-setup.c              |   4 +-
 arch/arm/mach-orion5x/pci.c                        |   7 +-
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |   4 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |   4 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |   7 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |   4 +-
 arch/arm/mach-orion5x/ts209-setup.c                |   4 +-
 arch/arm/mach-orion5x/ts409-setup.c                |   4 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |   4 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |   4 +-
 arch/arm/mach-shmobile/clock-r8a7779.c             |  23 +-
 arch/arm/mach-shmobile/include/mach/r8a7779.h      |   2 +
 arch/arm/mach-shmobile/setup-r8a7779.c             |  23 +-
 arch/arm/mach-zynq/Kconfig                         |   1 +
 arch/arm/mach-zynq/Makefile                        |   6 +-
 arch/arm/mach-zynq/common.c                        |  67 +-
 arch/arm/mach-zynq/common.h                        |  20 +
 arch/arm/mach-zynq/headsmp.S                       |  24 +
 arch/arm/mach-zynq/hotplug.c                       | 104 +++
 arch/arm/mach-zynq/platsmp.c                       | 136 ++++
 arch/arm/mach-zynq/slcr.c                          | 125 +++
 arch/arm/plat-orion/Makefile                       |   6 -
 arch/arm/plat-orion/addr-map.c                     | 178 -----
 arch/arm/plat-orion/gpio.c                         |  59 ++
 drivers/bus/Kconfig                                |   7 +
 drivers/bus/Makefile                               |   1 +
 drivers/bus/mvebu-mbus.c                           | 870 +++++++++++++++++++++
 drivers/gpio/gpio-pl061.c                          |   2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c               |   2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-common.c        |  12 +-
 include/linux/mbus.h                               |  27 +-
 96 files changed, 2257 insertions(+), 1002 deletions(-)


From arnd at arndb.de  Tue May  7 12:02:09 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 18:02:09 +0200
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
Message-ID: <1367942534-2934003-1-git-send-email-arnd@arndb.de>

Hi Linus,

This is the third and final batch of branches for arm-soc for the
3.10 merge window. Following what Olof did earlier, I pushed out
a branch with the conflicts resolved named 'third-batch-resolved'
for reference.
We still have a bunch of outstanding bug fixes that we'll send
later this week.

I used a new script to create the pull requests this time, hope
I got it right now.

	Arnd


From arnd at arndb.de  Tue May  7 12:02:14 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 18:02:14 +0200
Subject: [GIT PULL] ARM: arm-soc: late Exynos multiplatform changes
In-Reply-To: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
Message-ID: <1367942534-2934003-6-git-send-email-arnd@arndb.de>

These continue the multiplatform support for exynos, adding support
for building most of the essential drivers (clocksource, clk, irqchip)
when combined with other platforms. As a result, it should become
really easy to add full multiplatform exynos support in 3.11, although
we don't yet enable it for 3.10.

The changes were not included in the earlier multiplatform series
in order to avoid clashes with the other Exynos updates.

This also includes work from Tomasz Figa to fix the pwm clocksource
code on Exynos, which is not strictly required for multiplatform,
but related to the other patches in this set and needed as a bug
fix for at least one board.

Conflicts:
- in arch/arm/mach-exynos/common.c, the irq_set_wake callback
  gets added, while a call to s5p_init_irq() gets removed and
  the prototype for combiner_init changes.


-------------------------------------------------------------

The following changes since commit

   e8b1270 Merge tag 'cleanup-for-linus-2' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/multiplatform-for-linus-2

you to fetch changes up to

   241a987 Merge branch 'exynos/pwm-clocksource' into late/multiplatform


-------------------------------------------------------------

Arnd Bergmann (12):
      clk: exynos: prepare for multiplatform
      clocksource: exynos_mct: remove platform header dependency
      ARM: exynos: add missing properties for combiner IRQs
      irqchip: exynos: pass max combiner number to combiner_init
      irqchip: exynos: allocate combiner_data dynamically
      irqchip: exynos: localize irq lookup for ATAGS
      irqchip: exynos: pass irq_base from platform
      irqchip: exynos: look up irq using irq_find_mapping
      Merge branch 'next/drivers' into late/multiplatform
      Merge branch 'samsung/exynos-multiplatform-drivers' into late/multiplatform
      Merge branch 'exynos/pwm-clocksource' into late/multiplatform
      Merge tag 'multiplatform-for-linus-2' into for-next

Olof Johansson (1):
      ARM: dts: exynops4210: really add universal_c210 dts

Tomasz Figa (13):
      clocksource: add samsung pwm timer driver
      Documentation: Add device tree bindings for Samsung PWM timers
      clocksource: samsung_pwm_timer: Let platforms select the driver
      clocksource: samsung_pwm_timer: Make PWM spinlock global
      clocksource: samsung_pwm_timer: Keep all driver data in a structure
      clocksource: samsung_pwm_timer: Drop unused samsung_pwm struct
      clocksource: samsung_pwm_timer: Add support for non-DT platforms
      clocksource: samsung_pwm_timer: Use proper clockevents max_delta
      clocksource: samsung_pwm_timer: Correct programming of clock events
      clocksource: samsung_pwm_timer: Work around rounding errors in clockevents core
      ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos
      ARM: dts: exynos4: Add node for PWM device
      ARM: dts: exynos4210: Add basic dts file for universal_c210 board

 .../devicetree/bindings/pwm/pwm-samsung.txt        |  43 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/exynos4.dtsi                     |   8 +
 arch/arm/boot/dts/exynos4210-universal_c210.dts    | 352 +++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi                  |   1 +
 arch/arm/boot/dts/exynos4212.dtsi                  |   9 +
 arch/arm/boot/dts/exynos4412.dtsi                  |   9 +
 arch/arm/mach-exynos/common.c                      |  35 +-
 arch/arm/mach-exynos/common.h                      |   7 +-
 arch/arm/plat-samsung/Kconfig                      |   4 +-
 drivers/clk/samsung/clk-exynos4.c                  |  93 ++--
 drivers/clk/samsung/clk-exynos5250.c               |   1 -
 drivers/clk/samsung/clk-exynos5440.c               |   1 -
 drivers/clk/samsung/clk.h                          |   2 -
 drivers/clocksource/Kconfig                        |   9 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/exynos_mct.c                   |  21 +-
 drivers/clocksource/samsung_pwm_timer.c            | 494 +++++++++++++++++++++
 drivers/irqchip/exynos-combiner.c                  | 125 +++---
 include/clocksource/samsung_pwm.h                  |  36 ++
 20 files changed, 1098 insertions(+), 154 deletions(-)


From arnd at arndb.de  Tue May  7 12:02:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 18:02:13 +0200
Subject: [GIT PULL] ARM: arm-soc: late cleanups
In-Reply-To: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
Message-ID: <1367942534-2934003-5-git-send-email-arnd@arndb.de>

These are cleanups and smaller changes that either depend on earlier
feature branches or came in late during the development cycle.
We normally try to get all cleanups early, so these are the exceptions:

- A follow-up on the clocksource reworks, hopefully the last time
  we need to merge clocksource subsystem changes through arm-soc.
  A first set of patches was part of the original 3.10 arm-soc cleanup
  series because of interdependencies with timer drivers now moved out
  of arch/arm.

- Migrating the SPEAr13xx platform away from using auxdata for DMA
  channel descriptions towards using information in device tree,
  based on the earlier SPEAr multiplatform series

- A few follow-ups on the Atmel SAMA5 support and other changes
  for Atmel at91 based on the larger at91 reworks.

- Moving the armada irqchip implementation to drivers/irqchip

- Several OMAP cleanups following up on the larger series already
  merged in 3.10.

There are a few more conflicts that we would like now:

Simple conflicts between unrelated add or del hunks:
- arch/arm/Kconfig
- arch/arm/mach-mvebu/Makefile
- arch/arm/mach-mvebu/armada-370-xp.c
- arch/arm/mach-spear/spear13xx.c
- drivers/irqchip/Makefile

And non-obvious ones:
- remove/modify conflict in arch/arm/mach-exynos/mach-exynos5-dt.c:
  keep the modified line
- multiple changes to arch/arm/mach-vexpress/v2m.c:
  keep of_clk_init(NULL), clocksource_of_init() and
  versatile_sched_clock_init() calls


-------------------------------------------------------------

The following changes since commit

   763e6b9 Merge tag 'dt-for-linus-2' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/cleanup-for-linus-2

you to fetch changes up to

   0592c21 Merge tag 'omap-for-v3.10/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/cleanup


-------------------------------------------------------------

Archit Taneja (13):
      arm: omap: board-2430: use generic dpi panel's gpio handling
      arm: omap: board-devkit8000: use generic dpi panel's gpio handling
      arm: omap: board-am3517: use generic dpi panel's gpio handling
      arm: omap: board-ldp: use generic dpi panel's gpio handling
      arm: omap: board-overo: use lb035q02 dpi panel's gpio handling
      arm: omap: board-omap3evm: use sharp panel's gpio handling
      arm: omap: board-sdp3430: use sharp panel's gpio handling
      arm: omap: board-rx-51: use acx565akm panel's gpio handling
      arm: omap: board-zoom: use NEC panel's gpio handling
      arm: omap: board-omap3pandora: use tpo panel's gpio handling
      arm: omap: dss-common: use picodlp panel's gpio handling
      arm: omap boards: Remove unnecessary platform_enable/disable callbacks for VENC devices
      arm: dss-common: don't use reset_gpio from omap4_panda_dvi_device

Arnd Bergmann (16):
      spi: pl022: use generic DMA slave configuration if possible
      serial: pl011: use generic DMA slave configuration if possible
      Merge branch 'spear/multiplatform' into spear/dma
      ARM: SPEAr13xx: Pass generic DW DMAC platform data from DT
      ARM: make machine_desc->init_time default to clocksource_of_init
      ARM: at91: suspend both memory controllers on at91sam9263
      ata: arasan: remove the need for platform_data
      Merge branch 'spear/multiplatform' into late/cleanup
      Merge branch 'spear/dwdma' into late/cleanup
      serial: amba-pl011: fix !CONFIG_DMA_ENGINE case
      ARM: OMAP: remove unused variable
      Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into late/cleanup
      ARM: SPEAr: conditionalize SMP code
      Merge branch 'late/clksrc' into late/cleanup
      Merge tag 'omap-for-v3.10/fixes-for-merge-window' of git://git.kernel.org/.../tmlind/linux-omap into late/cleanup
      Merge tag 'cleanup-for-linus-2' into for-next

Haojian Zhuang (1):
      devtree: add binding documentation for sp804

Kishon Vijay Abraham I (1):
      ARM: OMAP4: change the device names in usb_bind_phy

Ludovic Desroches (3):
      ARM: at91: dts: set #dma-cells to the correct value
      ARM: at91: dts: add i2c dma support
      ARM: at91: dts: add MCI DMA support

Nicolas Ferre (2):
      ARM: at91: change "Unknown" qualifier SoC subtype handling
      ARM: at91/sama5d34ek.dts: remove not needed compatibility string

Olof Johansson (7):
      Merge tag 'clksrc-cleanup-for-3.10-part2' of git://sources.calxeda.com/kernel/linux into late/clksrc
      Merge tag 'irqchip-3.10' of git://git.infradead.org/users/jcooper/linux into late/cleanup
      Merge branch 'omap/fixes-non-critical' into late/cleanup
      Merge branch 'omap/boards' into late/cleanup
      Merge tag 'omap-for-v3.10/dss-signed' of git://git.kernel.org/.../tmlind/linux-omap into late/cleanup
      Merge branch 'at91/soc' into late/cleanup
      Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into late/cleanup

Peter Ujfalusi (1):
      ARM: OMAP: zoom: Use pwm stack for lcd and keyboard backlight

Rob Herring (13):
      ARM: sched_clock: allow changing to higher frequency counter
      ARM: make sched_clock just call a function pointer
      ARM: arch_timer: use full 64-bit counter for sched_clock
      ARM: convert arm/arm64 arch timer to use CLKSRC_OF init
      OF: add empty of_device_is_available for !OF
      ARM: timer-sp: convert to use CLKSRC_OF init
      ARM: highbank: use OF init for sp804 timer
      ARM: vexpress: remove sp804 OF init
      ARM: dts: vexpress: disable CA9 core tile sp804 timer
      ARM: vexpress: remove extra timer-sp control register clearing
      ARM: versatile: add versatile dtbs to dtbs target
      ARM: versatile: use OF init for sp804 timer
      ARM: integrator-cp: convert use CLKSRC_OF for timer init

Stephen Boyd (1):
      ARM: arch_timer: Silence debug preempt warnings

Thomas Petazzoni (4):
      ARM: mvebu: move L2 cache initialization in init_early()
      irqchip: move IRQ driver for Armada 370/XP
      irqchip: armada-370-xp: move IRQ handler to avoid forward declaration
      irqchip: armada-370-xp: slightly cleanup irq controller driver

Tomi Valkeinen (1):
      arm: omap: board-cm-t35: use generic dpi panel's gpio handling

Tony Lindgren (1):
      Merge branch '3.10-lo/board-cleanup' of git://gitorious.org/linux-omap-dss2/linux into omap-for-v3.10/dss

Vaibhav Hiremath (1):
      ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a

 .../devicetree/bindings/arm/primecell.txt          |  19 ++-
 .../devicetree/bindings/ata/pata-arasan.txt        |  22 ++++
 Documentation/devicetree/bindings/serial/pl011.txt |  17 +++
 .../devicetree/bindings/spi/spi_pl022.txt          |  36 ++++++
 .../devicetree/bindings/timer/arm,sp804.txt        |  29 +++++
 arch/arm/Kconfig                                   |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   5 +
 arch/arm/boot/dts/at91sam9n12.dtsi                 |   9 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |  15 +++
 arch/arm/boot/dts/integratorcp.dts                 |   6 +-
 arch/arm/boot/dts/sama5d3.dtsi                     |  19 ++-
 arch/arm/boot/dts/sama5d34ek.dts                   |   2 +-
 arch/arm/boot/dts/spear1340.dtsi                   |   3 +
 arch/arm/boot/dts/spear13xx.dtsi                   |  25 +++-
 arch/arm/boot/dts/versatile-ab.dts                 |  12 ++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts             |   1 +
 arch/arm/common/timer-sp.c                         | 140 ++++++++++++++++++---
 arch/arm/include/asm/arch_timer.h                  |  13 +-
 arch/arm/include/asm/hardware/timer-sp.h           |  16 ++-
 arch/arm/include/asm/sched_clock.h                 |   2 +
 arch/arm/kernel/arch_timer.c                       |  29 ++---
 arch/arm/kernel/sched_clock.c                      |  15 ++-
 arch/arm/kernel/time.c                             |   7 +-
 arch/arm/mach-at91/cpuidle.c                       |   2 +
 arch/arm/mach-at91/include/mach/cpu.h              |   9 +-
 arch/arm/mach-at91/pm.c                            |   2 +
 arch/arm/mach-at91/pm.h                            |  30 ++++-
 arch/arm/mach-at91/setup.c                         |  22 ++--
 arch/arm/mach-highbank/highbank.c                  |  24 +---
 arch/arm/mach-integrator/integrator_cp.c           |  34 -----
 arch/arm/mach-mvebu/Makefile                       |   2 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |   9 +-
 arch/arm/mach-omap2/board-2430sdp.c                |  43 +------
 arch/arm/mach-omap2/board-3430sdp.c                |  53 +++-----
 arch/arm/mach-omap2/board-4430sdp.c                |   2 +-
 arch/arm/mach-omap2/board-am3517evm.c              |  74 +----------
 arch/arm/mach-omap2/board-cm-t35.c                 |  60 ++-------
 arch/arm/mach-omap2/board-devkit8000.c             |  27 +---
 arch/arm/mach-omap2/board-ldp.c                    |  61 ++-------
 arch/arm/mach-omap2/board-omap3evm.c               |  70 +++--------
 arch/arm/mach-omap2/board-omap3pandora.c           |   7 +-
 arch/arm/mach-omap2/board-omap3stalker.c           |  11 --
 arch/arm/mach-omap2/board-omap4panda.c             |   2 +-
 arch/arm/mach-omap2/board-overo.c                  |  58 +++------
 arch/arm/mach-omap2/board-rx51-video.c             |  26 ++--
 arch/arm/mach-omap2/board-zoom-display.c           |  38 ++----
 arch/arm/mach-omap2/dss-common.c                   |  54 +++-----
 arch/arm/mach-omap2/timer.c                        |   7 +-
 arch/arm/mach-shmobile/board-kzm9d.c               |   1 -
 arch/arm/mach-shmobile/setup-emev2.c               |   1 -
 arch/arm/mach-shmobile/setup-r8a7740.c             |   1 -
 arch/arm/mach-shmobile/setup-sh7372.c              |   1 -
 arch/arm/mach-shmobile/setup-sh73a0.c              |   1 -
 arch/arm/mach-shmobile/timer.c                     |   7 +-
 arch/arm/mach-spear/Makefile                       |   6 +-
 arch/arm/mach-spear/generic.h                      |   5 -
 arch/arm/mach-spear/include/mach/spear.h           |   2 -
 arch/arm/mach-spear/spear1310.c                    |  30 +----
 arch/arm/mach-spear/spear1340.c                    |  32 +----
 arch/arm/mach-spear/spear13xx-dma.h                | 128 -------------------
 arch/arm/mach-spear/spear13xx.c                    |  60 +--------
 arch/arm/mach-versatile/core.c                     |  26 ++--
 arch/arm/mach-versatile/versatile_dt.c             |   1 -
 arch/arm/mach-vexpress/v2m.c                       |  25 +---
 arch/arm/mach-virt/virt.c                          |   9 --
 arch/arm64/include/asm/arch_timer.h                |   5 +
 arch/arm64/kernel/time.c                           |   6 +-
 drivers/ata/pata_arasan_cf.c                       |  37 +++---
 drivers/clocksource/Kconfig                        |   1 +
 drivers/clocksource/arm_arch_timer.c               |  33 +++--
 drivers/clocksource/exynos_mct.c                   |   1 -
 drivers/irqchip/Makefile                           |   1 +
 .../irqchip}/irq-armada-370-xp.c                   | 106 ++++++++--------
 drivers/spi/spi-pl022.c                            |  43 ++++++-
 drivers/tty/serial/amba-pl011.c                    |  64 ++++++----
 include/clocksource/arm_arch_timer.h               |   6 -
 include/linux/of.h                                 |   5 +
 include/linux/pata_arasan_cf_data.h                |   2 -
 79 files changed, 777 insertions(+), 1041 deletions(-)


From arnd at arndb.de  Tue May  7 12:02:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 18:02:12 +0200
Subject: [GIT PULL] ARM: arm-soc device tree changes, part 2
In-Reply-To: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
Message-ID: <1367942534-2934003-4-git-send-email-arnd@arndb.de>

These are mostly new device tree bindings for existing drivers, as well
as changes to the device tree source files to add support for those
devices, and a couple of new boards, most notably Samsung's Exynos5
based Chromebook.

The changes depend on earlier platform specific updates and touch
the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci.

Conflicts:
 Simple add/add conflicts in arch/arm/boot/dts/exynos5250.dtsi and
 arch/arm/mach-omap2/omap_hwmod.c. In the former, be careful to
 include the closing curly braces and semicolon.


-------------------------------------------------------------

The following changes since commit

   9822346 Merge tag 'soc-for-linus-3' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/dt-for-linus-2

you to fetch changes up to

   4183bef Merge branch 'late/dt' into next/dt2


-------------------------------------------------------------

Alexander Graf (2):
      ARM: dts: Declare the gic as a15 compatible for exynos5250
      ARM: dts: Add architected timer nodes for exynos5250

Alexandre Belloni (3):
      ARM: cfa10036: add one wire bitbanging to the cfa10049
      pinctrl: pinctrl-mxs: document the missing pull-ups
      ARM: dts: cfa10036: Add touchscreen support to the CFA-10049

Alexandre Pereira da Silva (1):
      ARM: dts: imx23-olinuxino: mark sdcard cd as broken

Amit Daniel Kachhap (2):
      ARM: dts: Add PMIC node entry for Arndale board
      ARM: dts: Add cpufreq controller node for Exynos5440 SoC

Andrew Chew (2):
      ARM: tegra: fix the status of PWM DT nodes
      ARM: tegra: add PWM nodes to Tegra114 DT

Anil Kumar (3):
      ARM: dts: Add minimal DT support for DevKit8000
      ARM: dts: omap3-devkit8000: Enable audio support
      ARM: dts: omap3-devkit8000: Add NAND DT node

AnilKumar Ch (3):
      ARM: dts: AM33XX: Rename I2C and GPIO nodes
      ARM: dts: AM33XX: Add d_can instances to aliases
      ARM: dts: AM33XX: Add memory resource to d_can node

Arnd Bergmann (6):
      Merge branch 'mxs/cleanup' into next/dt2
      Merge tag 'mxs-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt2
      Merge branch 'tegra/clk' into next/dt2
      Merge tag 'tegra-for-3.10-dt' of git://git.kernel.org/.../swarren/linux-tegra into next/dt2
      Merge branch 'late/dt' into next/dt2
      Merge tag 'dt-for-linus-2' into for-next

Benoit Cousson (1):
      Merge tag 'omap-devel-b-for-3.10' of git://git.kernel.org/.../pjw/omap-pending into for_3.10/dts_merged

Byungho An (1):
      ARM: dts: Add node for GMAC for exynos5440

Christoph Fritz (1):
      ARM/dts: OMAP3: fix pinctrl-single configuration

Doug Anderson (4):
      ARM: dts: add usb 2.0 clock references to exynos5250 device tree
      ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings
      ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
      ARM: dts: Add sbs-battery for exynos5250-snow

Fabio Estevam (1):
      video: mxsfb: Introduce regulator support

Felipe Balbi (1):
      ARM: dts: OMAP5: Add SPI nodes

Florian Vaussard (3):
      ARM: dts: omap3-overo: Add support for pwm-leds
      ARM: dts: omap3-overo: Add audio support
      ARM: dts: OMAP3: Add GPMC controller

Giridhar Maruthy (1):
      ARM: dts: Add virtual GIC DT bindings for exynos5440

Gregory CLEMENT (3):
      ARM: dts: mvebu: Convert all the mvebu files to use the range property
      ARM: dts: mvebu: introduce internal-regs node
      ARM: dts: mvebu: Convert mvebu device tree files to 64 bits

Jason Cooper (2):
      Merge tag 'tags/mvebu_fixes_for_v3.9_round3' into mvebu/dt
      Merge tag 'tags/soc_for_v3.10' into mvebu/dt

Javier Martinez Canillas (5):
      ARM: dts: omap3: Add generic DT support for IGEP devices
      ARM: dts: omap3: Add support for IGEPv2 board
      ARM: dts: omap3: Add support for IGEP COM Module
      ARM: dts: OMAP3: reduce GPMC mapped registers address space
      Documentation: dt: gpio-omap: Move interrupt-controller from #interrupt-cells description

Jon Hunter (16):
      ARM: OMAP2+: Prepare for device-tree PMU support
      ARM: dts: OMAP2+: Add PMU nodes
      ARM: dts: OMAP2+: Add SDMA controller bindings and nodes
      ARM: dts: Add GPMC node for OMAP2, OMAP4 and OMAP5
      ARM: dts: Add OMAP2 gpio bindings
      ARM: dts: OMAP3+: Correct gpio #interrupts-cells property
      ARM: dts: OMAP3: Add reg and interrupt properties for gpio
      ARM: dts: OMAP3: Add support for OMAP3430 SDP board
      ARM: OMAP: Force dmtimer restore if context loss is not detectable
      ARM: OMAP: Add function to request timer by node
      ARM: dts: OMAP2+: Update DMTIMER compatibility property
      ARM: OMAP2+: Populate DMTIMER errata when using device-tree
      ARM: dts: OMAP2+: Identify GPIO banks that are always powered
      ARM: dts: Update OMAP3430 SDP NAND and ONENAND properties
      ARM: dts: Add NOR flash bindings for OMAP2420 H4
      ARM: dts: Add OMAP3430 SDP NOR flash memory binding

Joseph Lo (4):
      ARM: tegra: add power gpio keys to DT
      ARM: tegra: whistler: add wakeup source for KBC
      ARM: tegra: add non-removable and keep-power-in-suspend property for MMC
      ARM: dts: tegra: add the PM configurations of PMC

Kishon Vijay Abraham I (7):
      ARM: dts: OMAP4: Add omap control usb data
      ARM: dts: OMAP4: Add omap-usb2 data
      ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
      ARM: dts: OMAP5: Add OMAP control usb data
      ARM: dts: OMAP5: Add ocp2scp data
      ARM: dts: OMAP5: Add omap-usb3 and omap-usb2 data
      ARM: dts: OMAP5: add dwc3 omap and dwc3 core data

Kukjin Kim (1):
      ARM: dts: add device tree file for SD5v1 board

Laxman Dewangan (9):
      ARM: tegra: add APB DMA nodes to Tegra114 DT
      ARM: tegra: add I2C nodes to Tegra114 DT
      ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114
      ARM: tegra: add KBC nodes to Tegra114 DT
      ARM: tegra: add SPI nodes to Tegra114 DT
      ARM: tegra: add DT binding for i2c-tegra
      ARM: tegra: dalmore: add cpu regulator node
      ARM: tegra: dalmore: add TPS65090 node
      ARM: tegra: dalmore: add fixed regulator node

Leela Krishna Amudala (2):
      ARM: dts: Add FIMD node to exynos5
      ARM: dts: Add display timing node to exynos5250-smdk5250.dts

Lokesh Vutla (1):
      ARM: dts: OMAP5: Add watchdog timer node

Manjunathappa, Prakash (4):
      spi/davinci: no wildcards in DT compatible property
      ARM: davinci: da850: add SPI1 DT node
      ARM: davinci: da850: override SPI DT node device name
      ARM: davinci: da850-evm: add SPI flash support

Matthias Brugger (1):
      ARM: dts: omap3-igep: Add uart1 and uart2 to igep boards

Murali Karicheri (1):
      spi/davinci: add DT binding documentation

NeilBrown (1):
      ARM: OMAP: Simplify dmtimer context-loss handling

Nishanth Menon (6):
      ARM: dts: OMAP34xx/35xx: Add CPU OPP table
      ARM: dts: OMAP36xx: Add CPU OPP table
      ARM: dts: OMAP3: use twl4030 vdd1 regulator for CPU
      ARM: dts: OMAP443x: Add CPU OPP table
      ARM: dts: omap4-panda: move generic sections to panda-common
      ARM: dts: OMAP4460: Add CPU OPP table

Olof Johansson (10):
      Merge branch 'omap/fixes-non-critical' into next/dt2
      Merge branch 'omap/usb' into next/dt2
      Merge tag 'omap-for-v3.10/dt-signed-v2' of git://git.kernel.org/.../tmlind/linux-omap into next/dt2
      Merge tag 'dt-exynos-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/dt2
      Merge tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux into next/dt2
      Merge tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/.../nsekhar/linux-davinci into next/dt2
      Merge branch 'samsung/pinctrl-exynos' into late/dt
      Merge branch 'exynos/dt' into late/dt
      ARM: exynos: dts: cros5250: add EC device
      Merge tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into late/dt

Peter Ujfalusi (5):
      ARM: dts: twl4030: Add PWM support
      ARM: dts: twl6030: Add PWM support
      ARM: dts: omap3-beagle-xm: Use pwm-leds for pmu_stat LED
      ARM: dts: omap4-sdp: Add support for pwm-leds (keypad and charging LED)
      ARM: dts: omap4-sdp: Add support for pwm-backlight

Philip Avinash (2):
      ARM: dts: AM33XX: Corrects typo in interrupt field in SPI node
      ARM: davinci: da850: add EHRPWM & ECAP DT node

Prashant Gaikwad (1):
      clk: tegra: Fix cdev1 and cdev2 IDs

Pritesh Raithatha (2):
      ARM: tegra: add default pinctrl nodes for Dalmore
      ARM: tegra: add SDHCI nodes with common properties

Rajendra Nayak (1):
      ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Rhyland Klein (2):
      ARM: tegra: add SDHCI support for Dalmore
      ARM: tegra: Add sbs-battery node to Dalmore

Sachin Kamat (11):
      ARM: dts: Add G2D node to exynos4210.dtsi
      ARM: dts: Add G2D node to SMDKV310
      ARM: dts: Add G2D node to exynos4210-origen
      ARM: dts: Add G2D node to exynos4x12.dtsi
      ARM: dts: Add G2D node to SMDK4412
      ARM: dts: Add G2D node to exynos4412-origen
      ARM: dts: Add Samsung G2D DT bindings documentation
      ARM: dts: Add disable-wp for card slot on exynos5250-arndale
      ARM: dts: Add vmmc regulator support for Arndale board
      ARM: dts: Add MFC codec support for Arndale board
      ARM: dts: Add HDMI HPD and regulator node for Arndale board

Santosh Shilimkar (9):
      ARM: dts: omap5-evm: Update available memory to 2032 MB
      ARM: dts: OMAP5: Align the local timer dt node as per the current binding code
      ARM: dts: OMAP5: Move the gic node out of ocp space
      ARM: dts: OMAP5: Update the timer and GIC nodes for HYP kernel support
      ARM: dts: OMAP5: Update keypad reg property
      Documentation: dt: OMAP: l3-noc: Add *reg* in required properties
      ARM: dts: OMAP4/5: Update l3-noc DT nodes
      ARM: OMAP2+: hwmod: extract module address space from DT blob
      ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc

Sebastien Guiriec (1):
      ARM: dts: OMAP2+: Add SDMA Audio IPs bindings

Shawn Guo (16):
      net: fec: handle optional clk_ptp more gracefully
      ARM: mxs: remove unneeded enet_out clk initialization
      video: mxsfb: use devm_* managed functions
      video: mxsfb: remove fb_phys/fb_size from platform_data
      video: mxsfb: remove dotclk_delay from platform_data
      video: mxsfb: get display timings from device tree
      ARM: mxs: move display timing configurations into device tree
      video: mxsfb: remove mxsfb_platform_data
      ARM: dts: add generic DMA device tree binding for mxs-dma
      dma: mxs-dma: use devm_* managed functions
      dma: mxs-dma: move to generic device tree binding
      mmc: mxs-mmc: move to use generic DMA helper
      spi: mxs-spi: move to use generic DMA helper
      i2c: i2c-mxs: move to use generic DMA helper
      mtd: gpmi: move to use generic DMA helper
      serial: mxs-auart: move to use generic DMA helper

Sourav Poddar (4):
      ARM: dts: omap4-sdp: Add I2c pinctrl data
      ARM: dts: omap5-evm: Add I2c pinctrl data
      ARM: dts: omap4-panda: Add I2c pinctrl data
      ARM: dts: omap5-evm: Add mcspi data

Stephen Warren (5):
      ARM: tegra: device tree whitespace cleanup
      ARM: tegra: fix sort order of USB PHY nodes
      ARM: tegra: add clocks property to sound nodes
      ARM: tegra: add clocks property to AC'97 sound nodes
      ARM: tegra: keep power on to SD slot on Dalmore

Subash Patel (3):
      ARM: dts: add PMU support in exynos5440
      ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440
      ARM: dts: add PDMA0 changes for exynos5440

Sylwester Nawrocki (1):
      ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series

Thomas Abraham (7):
      ARM: dts: add pin state information in client nodes for Exynos4 platforms
      ARM: dts: add pin state information in client nodes for Exynos5 platforms
      ARM: dts: list the interrupts generated by pin-controller on Exynos5440
      ARM: dts: Fix gmac clock ids due to changes in Exynos5440
      ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
      ARM: dts: Add chip-id controller node on Exynos4/5 SoC
      ARM: dts: add mshc controller node for Exynos4x12 SoCs

Thomas Petazzoni (2):
      ARM: dts: mvebu: fix cpus section indentation
      ARM: dts: mvebu: move all peripherals inside soc

Tony Lindgren (1):
      Merge branch 'for_3.10/dts' of git://git.kernel.org/.../bcousson/linux-omap-dt into omap-for-v3.10/dt

Tushar Behera (2):
      ARM: dts: Add pin-control related changes for Arndale board
      ARM: dts: Add gpio-button entries for Arndale board

Vikas Sajjan (3):
      ARM: dts: Add FIMD node to exynos4
      ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts
      ARM: dts: Add FIMD DT binding Documentation

Wolfram Sang (2):
      net: freescale: fec: add support for optional enet_out clk
      ARM: dts: mxs: add enet_out clock to devicetree

 .../devicetree/bindings/arm/omap/l3-noc.txt        |   1 +
 .../devicetree/bindings/arm/omap/timer.txt         |  17 +-
 .../devicetree/bindings/arm/samsung/sysreg.txt     |   7 +
 .../devicetree/bindings/dma/fsl-mxs-dma.txt        |  49 +-
 Documentation/devicetree/bindings/fb/mxsfb.txt     |  36 +-
 .../devicetree/bindings/gpio/gpio-omap.txt         |   8 +-
 .../devicetree/bindings/gpu/samsung-g2d.txt        |  20 +
 Documentation/devicetree/bindings/i2c/i2c-mxs.txt  |  12 +-
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  60 ++
 Documentation/devicetree/bindings/mmc/mxs-mmc.txt  |  12 +-
 .../devicetree/bindings/mtd/gpmi-nand.txt          |  17 +-
 .../bindings/pinctrl/fsl,mxs-pinctrl.txt           |   4 +
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |   8 +
 .../sound/nvidia,tegra-audio-trimslice.txt         |   7 +
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |   8 +
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |   8 +
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |   8 +
 Documentation/devicetree/bindings/spi/mxs-spi.txt  |  12 +-
 .../devicetree/bindings/spi/spi-davinci.txt        |  51 ++
 .../bindings/tty/serial/fsl-mxs-auart.txt          |  16 +-
 .../devicetree/bindings/usb/exynos-usb.txt         |  10 +
 Documentation/devicetree/bindings/usb/omap-usb.txt |   1 +
 .../devicetree/bindings/video/samsung-fimd.txt     |  65 ++
 arch/arm/boot/dts/Makefile                         |   5 +
 arch/arm/boot/dts/am335x-bone.dts                  |  10 +-
 arch/arm/boot/dts/am335x-evm.dts                   |  18 +-
 arch/arm/boot/dts/am335x-evmsk.dts                 |  18 +-
 arch/arm/boot/dts/am33xx.dtsi                      |  40 +-
 arch/arm/boot/dts/am3517-evm.dts                   |   2 +-
 arch/arm/boot/dts/am3517_mt_ventoux.dts            |   2 +-
 arch/arm/boot/dts/armada-370-db.dts                | 134 ++--
 arch/arm/boot/dts/armada-370-mirabox.dts           | 176 ++--
 arch/arm/boot/dts/armada-370-rd.dts                |  96 +--
 arch/arm/boot/dts/armada-370-xp.dtsi               | 336 ++++----
 arch/arm/boot/dts/armada-370.dtsi                  | 330 ++++----
 arch/arm/boot/dts/armada-xp-db.dts                 | 202 ++---
 arch/arm/boot/dts/armada-xp-gp.dts                 | 222 ++---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           | 284 +++----
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           | 342 ++++----
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           | 484 +++++------
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   | 262 +++---
 arch/arm/boot/dts/armada-xp.dtsi                   | 202 ++---
 arch/arm/boot/dts/cros5250-common.dtsi             |  54 +-
 arch/arm/boot/dts/da850-evm.dts                    |  40 +
 arch/arm/boot/dts/da850.dtsi                       |  94 +++
 arch/arm/boot/dts/exynos4.dtsi                     |  32 +
 arch/arm/boot/dts/exynos4210-origen.dts            |   4 +
 arch/arm/boot/dts/exynos4210-smdkv310.dts          |  57 +-
 arch/arm/boot/dts/exynos4210.dtsi                  |   7 +
 arch/arm/boot/dts/exynos4412-origen.dts            |  21 +
 arch/arm/boot/dts/exynos4412-smdk4412.dts          |   8 +
 arch/arm/boot/dts/exynos4412.dtsi                  |   8 +
 arch/arm/boot/dts/exynos4x12.dtsi                  |   7 +
 arch/arm/boot/dts/exynos5250-arndale.dts           | 343 +++++++-
 arch/arm/boot/dts/exynos5250-pinctrl.dtsi          | 783 ++++++++++++++++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |  49 +-
 arch/arm/boot/dts/exynos5250-snow.dts              | 149 +++-
 arch/arm/boot/dts/exynos5250.dtsi                  | 348 +++-----
 arch/arm/boot/dts/exynos5440-sd5v1.dts             |  39 +
 arch/arm/boot/dts/exynos5440-ssdk5440.dts          |   6 +-
 arch/arm/boot/dts/exynos5440.dtsi                  |  55 +-
 arch/arm/boot/dts/imx23-evk.dts                    |  36 +-
 arch/arm/boot/dts/imx23-olinuxino.dts              |   1 +
 arch/arm/boot/dts/imx23.dtsi                       |  42 +-
 arch/arm/boot/dts/imx28-apf28dev.dts               |  25 +
 arch/arm/boot/dts/imx28-apx4devkit.dts             |  25 +
 arch/arm/boot/dts/imx28-cfa10049.dts               |  50 +-
 arch/arm/boot/dts/imx28-evk.dts                    |  36 +-
 arch/arm/boot/dts/imx28-m28evk.dts                 |  27 +
 arch/arm/boot/dts/imx28.dtsi                       |  62 +-
 arch/arm/boot/dts/imx6qdl.dtsi                     |   8 +-
 arch/arm/boot/dts/omap2.dtsi                       |  39 +-
 arch/arm/boot/dts/omap2420-h4.dts                  |  46 ++
 arch/arm/boot/dts/omap2420.dtsi                    |  67 +-
 arch/arm/boot/dts/omap2430.dtsi                    |  87 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts              |  26 +-
 arch/arm/boot/dts/omap3-beagle.dts                 |   8 +-
 arch/arm/boot/dts/omap3-devkit8000.dts             | 169 ++++
 arch/arm/boot/dts/omap3-evm.dts                    |  14 +-
 arch/arm/boot/dts/omap3-igep.dtsi                  | 122 +++
 arch/arm/boot/dts/omap3-igep0020.dts               |  56 ++
 arch/arm/boot/dts/omap3-igep0030.dts               |  44 +
 arch/arm/boot/dts/omap3-overo.dtsi                 |  31 +-
 arch/arm/boot/dts/omap3.dtsi                       | 142 +++-
 arch/arm/boot/dts/omap3430-sdp.dts                 | 190 +++++
 arch/arm/boot/dts/omap34xx.dtsi                    |  28 +
 arch/arm/boot/dts/omap36xx.dtsi                    |  13 +
 arch/arm/boot/dts/omap4-panda-a4.dts               |   5 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi          | 251 ++++++
 arch/arm/boot/dts/omap4-panda-es.dts               |   5 +-
 arch/arm/boot/dts/omap4-panda.dts                  | 201 +----
 arch/arm/boot/dts/omap4-sdp.dts                    |  74 +-
 arch/arm/boot/dts/omap4-var-som.dts                |   2 +-
 arch/arm/boot/dts/omap4.dtsi                       | 135 +++-
 arch/arm/boot/dts/omap443x.dtsi                    |  27 +
 arch/arm/boot/dts/omap4460.dtsi                    |  32 +
 arch/arm/boot/dts/omap5-evm.dts                    | 110 ++-
 arch/arm/boot/dts/omap5.dtsi                       | 245 +++++-
 arch/arm/boot/dts/tegra114-dalmore.dts             | 891 +++++++++++++++++++++
 arch/arm/boot/dts/tegra114.dtsi                    | 240 +++++-
 arch/arm/boot/dts/tegra20-colibri-512.dtsi         |  12 +
 arch/arm/boot/dts/tegra20-harmony.dts              |  20 +
 arch/arm/boot/dts/tegra20-medcom-wide.dts          |   7 +
 arch/arm/boot/dts/tegra20-paz00.dts                |  10 +
 arch/arm/boot/dts/tegra20-plutux.dts               |   3 +
 arch/arm/boot/dts/tegra20-seaboard.dts             |  11 +
 arch/arm/boot/dts/tegra20-tamonten.dtsi            |   6 +
 arch/arm/boot/dts/tegra20-tec.dts                  |   3 +
 arch/arm/boot/dts/tegra20-trimslice.dts            |  23 +
 arch/arm/boot/dts/tegra20-ventana.dts              |  22 +
 arch/arm/boot/dts/tegra20-whistler.dts             |  13 +
 arch/arm/boot/dts/tegra20.dtsi                     |  53 +-
 arch/arm/boot/dts/tegra30-beaver.dts               |   8 +
 arch/arm/boot/dts/tegra30-cardhu-a02.dts           |   1 +
 arch/arm/boot/dts/tegra30-cardhu-a04.dts           |   1 +
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |  11 +
 arch/arm/boot/dts/tegra30.dtsi                     |   1 +
 arch/arm/boot/dts/twl4030.dtsi                     |  18 +-
 arch/arm/boot/dts/twl6030.dtsi                     |  12 +
 arch/arm/mach-davinci/da8xx-dt.c                   |   6 +
 arch/arm/mach-exynos/common.c                      |  53 +-
 arch/arm/mach-exynos/include/mach/map.h            |   1 -
 arch/arm/mach-mxs/mach-mxs.c                       | 170 ----
 arch/arm/mach-omap2/board-generic.c                |   1 +
 arch/arm/mach-omap2/omap_hwmod.c                   |  48 +-
 arch/arm/mach-omap2/pmu.c                          |  14 +-
 arch/arm/mach-omap2/timer.c                        |   7 +-
 arch/arm/plat-omap/dmtimer.c                       | 241 +++---
 arch/arm/plat-omap/include/plat/dmtimer.h          |   1 +
 drivers/dma/mxs-dma.c                              | 109 ++-
 drivers/i2c/busses/i2c-mxs.c                       |  40 +-
 drivers/mmc/host/mxs-mmc.c                         |  48 +-
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c             |  51 +-
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h             |   3 +-
 drivers/net/ethernet/freescale/fec.h               |   1 +
 drivers/net/ethernet/freescale/fec_main.c          |  18 +-
 drivers/spi/spi-davinci.c                          |   4 +-
 drivers/spi/spi-mxs.c                              |  60 +-
 drivers/tty/serial/mxs-auart.c                     |  52 +-
 drivers/video/Kconfig                              |   2 +
 drivers/video/mxsfb.c                              | 260 +++---
 include/linux/mxsfb.h                              |  52 --
 include/linux/spi/mxs-spi.h                        |   4 +-
 143 files changed, 7751 insertions(+), 3048 deletions(-)


From jason at lakedaemon.net  Tue May  7 12:05:51 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 7 May 2013 12:05:51 -0400
Subject: [PATCH 3/3] ARM: kirkwood: remove clock gating disabling for
 km_kirkwood
In-Reply-To: <1367941941-19152-4-git-send-email-valentin.longchamp@keymile.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-4-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <20130507160551.GY31290@titan.lakedaemon.net>

Valentin,

Nice series!  I thought once the mv643xx_eth DT bindings take hold that
this was going to be one of the holdovers with a custom board init file.
Looks like that won't be the case ;-)

On Tue, May 07, 2013 at 05:52:21PM +0200, Valentin Longchamp wrote:
> A new clock gating controller is available for the prestera-kw kirkwood
> variant. This controller does not enable the unavailable clk gates.
> 
> This patch removes the fixes from the board-km_kirkwood file and enables
> the correct clk gating controller for kirkwood-98dx4122.dtsi.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
> ---
>  arch/arm/boot/dts/kirkwood-98dx4122.dtsi   |  7 +++++++
>  arch/arm/mach-kirkwood/board-km_kirkwood.c | 15 ---------------
>  2 files changed, 7 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
> index 3271e4c..8c73673 100644
> --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
> +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
> @@ -27,5 +27,12 @@
>  				marvell,function = "uart1";
>  			};
>  		};
> +
> +		gate_clk: clock-gating-control at 2011c {
> +			compatible = "marvell,prestera-kw-gating-clock";
> +			reg = <0x2011c 0x4>;
> +			clocks = <&core_clk 0>;
> +			#clock-cells = <1>;
> +		};
>  	};
>  };

--->8----

Please split this into two patches, one for the dtsi, and one for code
removal.  It'll prevent merge conflicts and branch dependencies for us.

thx,

Jason.

> diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
> index 44e4605..f1a6ab7 100644
> --- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
> +++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
> @@ -25,20 +25,5 @@ static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
>  
>  void __init km_kirkwood_init(void)
>  {
> -	struct clk *sata_clk;
> -	/*
> -	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
> -	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
> -	 * devices are also not present in this variant, their clocks get
> -	 * disabled because unused when clk_disable_unused() gets called.
> -	 * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
> -	 */
> -	sata_clk = clk_get_sys("sata_mv.0", "0");
> -	if (!IS_ERR(sata_clk))
> -		sata_clk->flags |= CLK_IGNORE_UNUSED;
> -	sata_clk = clk_get_sys("sata_mv.0", "1");
> -	if (!IS_ERR(sata_clk))
> -		sata_clk->flags |= CLK_IGNORE_UNUSED;
> -
>  	kirkwood_ge00_init(&km_kirkwood_ge00_data);
>  }
> -- 
> 1.8.0.1
> 


From gregory.clement at free-electrons.com  Tue May  7 12:11:44 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 07 May 2013 18:11:44 +0200
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood
 variants
In-Reply-To: <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <518927C0.6070600@free-electrons.com>

On 05/07/2013 05:52 PM, Valentin Longchamp wrote:
> The kirkwood device found in the Prestera SoCs does not have all the
> peripherals of its the usual kirkwood SoCs. There are hence missing
> clocks in the SoCs.
> 
> This patch registers another gate controller for the kirkwood that
> registers only the available clocks of this kirkwood variant.

Hi Valentin,

Overall the patch set looks OK, however I don't understand why you need
to declare a new gate controller. The list you delcared seemed to be
just a subset of the Kirkwood one, why can't you use this one?

Note that I am not an expert for the kirkwood hardware, so maybe I
missed something.

Regards,

> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
> ---
>  .../devicetree/bindings/clock/mvebu-gated-clock.txt   | 17 +++++++++++++++++
>  drivers/clk/mvebu/clk-gating-ctrl.c                   | 19 +++++++++++++++++++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> index cffc93d..7f494e90 100644
> --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> @@ -92,10 +92,27 @@ ID	Clock	Peripheral
>  19	ge1	Gigabit Ethernet 1
>  20	tdm	Time Division Mplx
>  
> +The following is a list of provided IDs for Kirkwood Prestera variant:
> +ID	Clock	Peripheral
> +-----------------------------------
> +0	ge0	Gigabit Ethernet 0
> +2	pex0	PCIe Cntrl 0
> +3	usb0	USB Host 0
> +4	sdio	SDIO Cntrl
> +5	tsu	Transp. Stream Unit
> +6	dunit	SDRAM Cntrl
> +7	runit	Runit
> +8	xor0	XOR DMA 0
> +16	xor1	XOR DMA 1
> +17	crypto	CESA engine
> +19	ge1	Gigabit Ethernet 1
> +
> +
>  Required properties:
>  - compatible : shall be one of the following:
>  	"marvell,dove-gating-clock" - for Dove SoC clock gating
>  	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
> +	"marvell,prestera-kw-gating-clock" - for Preseta SoC clock gating
>  - reg : shall be the register address of the Clock Gating Control register
>  - #clock-cells : from common clock binding; shall be set to 1
>  
> diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
> index ebf141d..ba37802 100644
> --- a/drivers/clk/mvebu/clk-gating-ctrl.c
> +++ b/drivers/clk/mvebu/clk-gating-ctrl.c
> @@ -203,6 +203,21 @@ static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
>  	{ "tdm", NULL, 20 },
>  	{ }
>  };
> +
> +static const struct mvebu_soc_descr __initconst prestera_kw_gating_descr[] = {
> +	{ "ge0", NULL, 0 },
> +	{ "pex0", NULL, 2 },
> +	{ "usb0", NULL, 3 },
> +	{ "sdio", NULL, 4 },
> +	{ "tsu", NULL, 5 },
> +	{ "runit", NULL, 7 },
> +	{ "xor0", NULL, 8 },
> +	{ "powersave", "cpuclk", 11 },
> +	{ "xor1", NULL, 16 },
> +	{ "crypto", NULL, 17 },
> +	{ "ge1", NULL, 19 },
> +	{ }
> +};
>  #endif
>  
>  static const __initdata struct of_device_id clk_gating_match[] = {
> @@ -232,6 +247,10 @@ static const __initdata struct of_device_id clk_gating_match[] = {
>  		.compatible = "marvell,kirkwood-gating-clock",
>  		.data = kirkwood_gating_descr,
>  	},
> +	{
> +		.compatible = "marvell,prestera-kw-gating-clock",
> +		.data = prestera_kw_gating_descr,
> +	},
>  #endif
>  
>  	{ }
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From cov at codeaurora.org  Tue May  7 12:17:55 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Tue, 07 May 2013 12:17:55 -0400
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <20130506143533.GF15278@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
 <20130506143533.GF15278@phenom.dumpdata.com>
Message-ID: <51892933.7090405@codeaurora.org>

Hi Konrad,

On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
>>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
>>> would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
>>> where the timer goes off. Nor does it make sense to require that the
>>> guest actually be running for 5 before injecting the timer because that
>>> would mean real time elapsed time for the timer would be 5+3 in the case
>>> where 3 are stolen.
>>
>> This is a bit of an aside, but I think that hiding time spent at higher
>> privilege levels can be a quite sensible approach to timekeeping in a
>> virtualized environment, but I understand that it's not the approach taken
>> with Xen, and as you pointed out above, adjusting the Virtual Offset Register
>> by itself isn't enough to implement that approach.
> 
> This is the approach taken by Xen and KVM. Look in CONFIG_PARAVIRT_CLOCK for
> implementation. In the user-space, the entry in 'top' of "stolen" (%st)
> is for this exact value.

I may have been unclear with my terms, sorry. When I refer to time being
"hidden", I mean that kernel level software (supervisor mode, EL1) cannot
detect the passage of that time at all. I don't know whether this would really
work, but I imagine one might be able to get close with the current
virtualization facilities for ARM.

Am I correct in interpreting that what you're referring to is the deployment
of paravirtualization code that ensures (observable) "stolen" time is factored
into kernel decision-making?

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From thomas.petazzoni at free-electrons.com  Tue May  7 12:18:23 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 7 May 2013 18:18:23 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51890C29.8000504@itooo.com>
References: <51890C29.8000504@itooo.com>
Message-ID: <20130507181823.23342ffb@skate>

Dear Greg,

On Tue, 07 May 2013 16:14:01 +0200, Greg wrote:

> I'm trying to boot off the the backport-3.-8 kernel with armada-xp-db DT 
> file.
> 
> When eth0 is brought up (I'm booting on NFS) the mvneta driver fails in 
> mvneta_open, with the following error :
> > mvneta d0070000.ethernet eth0: cannot request irq 25
> 
> The oddness is this is not the actual IRQ to be requested, and the DTS 
> files explicitly specify the IRQ is 8 for this device.
> 
> I'm not familiar with the DT system, where should I start looking to 
> find the source of the problem ?

This issue should be fixed by:

commit 7f23f62fc31c5c97947414c0937a72e08a947a41
Author: Gregory CLEMENT <gregory.clement at free-electrons.com>
Date:   Wed Mar 20 16:09:35 2013 +0100

    arm: mvebu: Use local interrupt only for the timer 0
    
    The commit 3a6f08a37 "arm: mvebu: Add support for local interrupt",
    managed the 28th first interrupts as local interrupt to match the
    hardware specification. Among these interrupts there are the Gigabits
    Ethernet ones used by the mvneta driver. Unfortunately the state of
    the percpu_irq API prevents the driver to use it.
    
    Indeed the interrupts have to be freed when the .stop() function is
    called. As the free_percpu_irq() function don't disable the interrupt
    line, we have to do it on each CPU before calling this. The function
    disable_percpu_irq() only disable the percpu on the current CPU and
    there is no function which allows to disable a percpu irq on a given
    CPU. Waiting for the extension of the percpu_irq API, this fix allows
    to use again the mvneta driver.
    
    Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
    Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
    Tested-by: Masami Hiramatsu <masami.hiramatsu.pt at hitachi.com>
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

which is part of the backport-3.8 branch, so I'm a bit confused. Are
you sure you're using the latest backport-3.8 branch? If so, then I'll
do a test here to check this.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From marc.zyngier at arm.com  Tue May  7 12:28:00 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 07 May 2013 17:28:00 +0100
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <20130502160906.GI20730@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
 <20130502160906.GI20730@arm.com>
Message-ID: <51892B90.8060706@arm.com>

On 02/05/13 17:09, Catalin Marinas wrote:
> On Mon, Apr 08, 2013 at 05:17:26PM +0100, Marc Zyngier wrote:
>>  static inline bool kvm_vcpu_reg_is_pc(const struct kvm_vcpu *vcpu, int reg)
>>  {
>> -	return false;
>> +	return (vcpu_mode_is_32bit(vcpu)) && reg == 15;
>>  }
> 
> On AArch64, would ESR_EL2 have SRT == 15 when the source/destination
> register is PC? The mapping between AArch32 and AArch64 registers
> suggests R13_hyp. Maybe 15 is correct but it's not clear to me from the
> spec.

The register reported by ESL_EL2 is indeed r15 when EL1 is in AARch32.
That's because we don't have PC as a GPR on AARch64.

> BTW, on arch/arm it looks like this is used when you get a data abort
> with PC as the destination register and you inject a prefetch abort in
> this case. Why isn't this a normal data abort? Once you get the
> information, you load it into PC but first you need to sort out the data
> abort (unless I don't understand how the kvm_inject_pabt works).

Indeed, it should be a data abort, as we correctly fetched the
instruction. Now, I wonder why we even bother trying to catch this case.
Fetching PC from MMIO looks quite silly, but I don't think anything
really forbids it in the architecture.

	M.
-- 
Jazz is not dead. It just smells funny...



From marc.zyngier at arm.com  Tue May  7 12:29:37 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 07 May 2013 17:29:37 +0100
Subject: [PATCH v3 07/32] arm64: KVM: fault injection into a guest
In-Reply-To: <20130429162652.GA16544@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-8-git-send-email-marc.zyngier@arm.com>
 <20130429162652.GA16544@arm.com>
Message-ID: <51892BF1.9070501@arm.com>

On 29/04/13 17:26, Catalin Marinas wrote:
> On Mon, Apr 08, 2013 at 05:17:09PM +0100, Marc Zyngier wrote:
>> +static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
>> +{
>> +	unsigned long cpsr = *vcpu_cpsr(vcpu);
>> +	int is_aarch32;
>> +	u32 esr = 0;
>> +
>> +	is_aarch32 = vcpu_mode_is_32bit(vcpu);
> 
> Minor thing - use bool here to match the function definition?

Sure, will do.

	M.
-- 
Jazz is not dead. It just smells funny...



From andrew at lunn.ch  Tue May  7 12:32:44 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 7 May 2013 18:32:44 +0200
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood
 variants
In-Reply-To: <518927C0.6070600@free-electrons.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
 <518927C0.6070600@free-electrons.com>
Message-ID: <20130507163244.GD9994@lunn.ch>

On Tue, May 07, 2013 at 06:11:44PM +0200, Gregory CLEMENT wrote:
> On 05/07/2013 05:52 PM, Valentin Longchamp wrote:
> > The kirkwood device found in the Prestera SoCs does not have all the
> > peripherals of its the usual kirkwood SoCs. There are hence missing
> > clocks in the SoCs.
> > 
> > This patch registers another gate controller for the kirkwood that
> > registers only the available clocks of this kirkwood variant.
> 
> Hi Valentin,
> 
> Overall the patch set looks OK, however I don't understand why you need
> to declare a new gate controller. The list you delcared seemed to be
> just a subset of the Kirkwood one, why can't you use this one?

Hi Gregory

Take a look at the code which gets deleted in patch 3/3.

       /*
        * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
        * SATA bits (14-15) of the Clock Gating Control Register. Since these
        * devices are also not present in this variant, their clocks get
        * disabled because unused when clk_disable_unused() gets called.
        * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
        */

By not defining these clocks in the first place, they never get turned
off...

	Andrew


From catalin.marinas at arm.com  Tue May  7 12:33:03 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 7 May 2013 17:33:03 +0100
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <51892B90.8060706@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
 <20130502160906.GI20730@arm.com> <51892B90.8060706@arm.com>
Message-ID: <20130507163303.GH29757@arm.com>

On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote:
> On 02/05/13 17:09, Catalin Marinas wrote:
> > BTW, on arch/arm it looks like this is used when you get a data abort
> > with PC as the destination register and you inject a prefetch abort in
> > this case. Why isn't this a normal data abort? Once you get the
> > information, you load it into PC but first you need to sort out the data
> > abort (unless I don't understand how the kvm_inject_pabt works).
> 
> Indeed, it should be a data abort, as we correctly fetched the
> instruction. Now, I wonder why we even bother trying to catch this case.
> Fetching PC from MMIO looks quite silly, but I don't think anything
> really forbids it in the architecture.

It's not forbidden and you should just treat it as any other data abort,
no need to check whether the register is PC. If you do the PC adjustment
further down in that function it will be overridden by the instruction
emulation anyway. There is no optimisation in checking for PC since such
fault is very unlikely in sane code anyway.

-- 
Catalin


From itooo at itooo.com  Tue May  7 12:33:46 2013
From: itooo at itooo.com (Greg)
Date: Tue, 07 May 2013 18:33:46 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <20130507181823.23342ffb@skate>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
Message-ID: <51892CEA.4050105@itooo.com>

Le 07/05/2013 18:18, Thomas Petazzoni a ?crit :
> Dear Greg,
>
> On Tue, 07 May 2013 16:14:01 +0200, Greg wrote:
>
>> I'm trying to boot off the the backport-3.-8 kernel with armada-xp-db DT
>> file.
>>
>> When eth0 is brought up (I'm booting on NFS) the mvneta driver fails in
>> mvneta_open, with the following error :
>>> mvneta d0070000.ethernet eth0: cannot request irq 25
>> The oddness is this is not the actual IRQ to be requested, and the DTS
>> files explicitly specify the IRQ is 8 for this device.
>>
>> I'm not familiar with the DT system, where should I start looking to
>> find the source of the problem ?
> This issue should be fixed by:
>
> commit 7f23f62fc31c5c97947414c0937a72e08a947a41
> Author: Gregory CLEMENT <gregory.clement at free-electrons.com>
> Date:   Wed Mar 20 16:09:35 2013 +0100
>
>      arm: mvebu: Use local interrupt only for the timer 0
>      
>      The commit 3a6f08a37 "arm: mvebu: Add support for local interrupt",
>      managed the 28th first interrupts as local interrupt to match the
>      hardware specification. Among these interrupts there are the Gigabits
>      Ethernet ones used by the mvneta driver. Unfortunately the state of
>      the percpu_irq API prevents the driver to use it.
>      
>      Indeed the interrupts have to be freed when the .stop() function is
>      called. As the free_percpu_irq() function don't disable the interrupt
>      line, we have to do it on each CPU before calling this. The function
>      disable_percpu_irq() only disable the percpu on the current CPU and
>      there is no function which allows to disable a percpu irq on a given
>      CPU. Waiting for the extension of the percpu_irq API, this fix allows
>      to use again the mvneta driver.
>      
>      Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
>      Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>      Tested-by: Masami Hiramatsu <masami.hiramatsu.pt at hitachi.com>
>      Signed-off-by: Jason Cooper <jason at lakedaemon.net>
>
> which is part of the backport-3.8 branch, so I'm a bit confused. Are
> you sure you're using the latest backport-3.8 branch? If so, then I'll
> do a test here to check this.
>
Thomas,

I could have done something wrong as I am not very familiar with git:
> root at axp-dev:/opt/linux-3.8-bp# git branch
> * backport-3.8
>   list
>   master
I cloned yesterday with :
> git clone -b backport-3.8 
> https://github.com/MISL-EBU-System-SW/mainline-public.git

is that ok ?

By the way I do have PCIe support enabled on the source tree I'm using.

Regards,



From sebastian.hesselbarth at gmail.com  Tue May  7 12:36:29 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 07 May 2013 18:36:29 +0200
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood
 variants
In-Reply-To: <518927C0.6070600@free-electrons.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
 <518927C0.6070600@free-electrons.com>
Message-ID: <51892D8D.4060704@gmail.com>

On 05/07/2013 06:11 PM, Gregory CLEMENT wrote:
> On 05/07/2013 05:52 PM, Valentin Longchamp wrote:
>> The kirkwood device found in the Prestera SoCs does not have all the
>> peripherals of its the usual kirkwood SoCs. There are hence missing
>> clocks in the SoCs.
>>
>> This patch registers another gate controller for the kirkwood that
>> registers only the available clocks of this kirkwood variant.
>
> Hi Valentin,
>
> Overall the patch set looks OK, however I don't understand why you need
> to declare a new gate controller. The list you delcared seemed to be
> just a subset of the Kirkwood one, why can't you use this one?
>
> Note that I am not an expert for the kirkwood hardware, so maybe I
> missed something.

I just checked my mails from late 2012 and there Valentin and I agreed,
that not the missing bits in clock gating control registers was the root
cause of km_kirkwood to hang. It was rather the phy gates (that do not/
not yet exist on DT) that caused it to hang, i.e. when accessing SATA
PHY registers.

Valentin, I am not against an extra clock-gating-ctrl for Prestera but
maybe having an kirkwood.dtsi fork without SATA and other peripherals
will also help?

And: Does DT-enabled km_kirkwood ever hang without the hack in it's
board setup? There should be no PHY gates on DT boards..

Sebastian


From marc.zyngier at arm.com  Tue May  7 12:36:52 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 07 May 2013 17:36:52 +0100
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com>	<5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
Message-ID: <51892DA4.4050401@arm.com>

On 24/04/13 18:17, Christoffer Dall wrote:
> On Wed, Apr 24, 2013 at 6:49 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> On 24/04/13 00:02, Christoffer Dall wrote:
>>> On Mon, Apr 08, 2013 at 05:17:32PM +0100, Marc Zyngier wrote:
>>>> Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
>>>> and providing sensible defaults out of reset state.
>>>>
>>>> This feature is of course conditioned by the presence of 32bit
>>>> capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
>>>> capability.
>>>>
>>>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
>>>> ---
>>>>  arch/arm64/include/asm/kvm_host.h |  2 +-
>>>>  arch/arm64/include/uapi/asm/kvm.h |  1 +
>>>>  arch/arm64/kvm/guest.c            |  6 ++++++
>>>>  arch/arm64/kvm/reset.c            | 25 ++++++++++++++++++++++++-
>>>>  include/uapi/linux/kvm.h          |  1 +
>>>>  5 files changed, 33 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
>>>> index d44064d..c3ec107 100644
>>>> --- a/arch/arm64/include/asm/kvm_host.h
>>>> +++ b/arch/arm64/include/asm/kvm_host.h
>>>> @@ -34,7 +34,7 @@
>>>>  #include <asm/kvm_vgic.h>
>>>>  #include <asm/kvm_arch_timer.h>
>>>>
>>>> -#define KVM_VCPU_MAX_FEATURES 1
>>>> +#define KVM_VCPU_MAX_FEATURES 2
>>>>
>>>>  /* We don't currently support large pages. */
>>>>  #define KVM_HPAGE_GFN_SHIFT(x)      0
>>>> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
>>>> index 5b1110c..5031f42 100644
>>>> --- a/arch/arm64/include/uapi/asm/kvm.h
>>>> +++ b/arch/arm64/include/uapi/asm/kvm.h
>>>> @@ -75,6 +75,7 @@ struct kvm_regs {
>>>>  #define KVM_VGIC_V2_CPU_SIZE                0x2000
>>>>
>>>>  #define KVM_ARM_VCPU_POWER_OFF              0 /* CPU is started in OFF state */
>>>> +#define KVM_ARM_VCPU_EL1_32BIT              1 /* CPU running a 32bit VM */
>>>>
>>>>  struct kvm_vcpu_init {
>>>>      __u32 target;
>>>> diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
>>>> index 47d3729..74ef7d5 100644
>>>> --- a/arch/arm64/kvm/guest.c
>>>> +++ b/arch/arm64/kvm/guest.c
>>>> @@ -93,6 +93,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
>>>>      if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
>>>>              unsigned long mode = (*(unsigned long *)valp) & COMPAT_PSR_MODE_MASK;
>>>>              switch (mode) {
>>>> +            case COMPAT_PSR_MODE_USR:
>>>> +            case COMPAT_PSR_MODE_FIQ:
>>>> +            case COMPAT_PSR_MODE_IRQ:
>>>> +            case COMPAT_PSR_MODE_SVC:
>>>> +            case COMPAT_PSR_MODE_ABT:
>>>> +            case COMPAT_PSR_MODE_UND:
>>>>              case PSR_MODE_EL0t:
>>>>              case PSR_MODE_EL1t:
>>>>              case PSR_MODE_EL1h:
>>>> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
>>>> index bc33e76..a282d35 100644
>>>> --- a/arch/arm64/kvm/reset.c
>>>> +++ b/arch/arm64/kvm/reset.c
>>>> @@ -35,11 +35,27 @@ static struct kvm_regs default_regs_reset = {
>>>>      .regs.pstate = PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
>>>>  };
>>>>
>>>> +static struct kvm_regs default_regs_reset32 = {
>>>> +    .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
>>>> +                    COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
>>>> +};
>>>> +
>>>> +static bool cpu_has_32bit_el1(void)
>>>> +{
>>>> +    u64 pfr0;
>>>> +
>>>> +    pfr0 = read_cpuid(ID_AA64PFR0_EL1);
>>>> +    return !!(pfr0 & 0x20);
>>>
>>> again we don't need the double negation
>>
>> I still hold that it makes things more readable.
>>
>>>> +}
>>>> +
>>>>  int kvm_arch_dev_ioctl_check_extention(long ext)
>>>>  {
>>>>      int r;
>>>>
>>>>      switch (ext) {
>>>> +    case KVM_CAP_ARM_EL1_32BIT:
>>>> +            r = cpu_has_32bit_el1();
>>>> +            break;
>>>>      default:
>>>>              r = 0;
>>>>      }
>>>> @@ -62,7 +78,14 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
>>>>
>>>>      switch (vcpu->arch.target) {
>>>>      default:
>>>> -            cpu_reset = &default_regs_reset;
>>>> +            if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
>>>> +                    if (!cpu_has_32bit_el1())
>>>> +                            return -EINVAL;
>>>
>>> I'm not sure EINVAL is appropriate here, the value specified was not
>>> incorrect, it's that the hardware doesn't support it. ENXIO, ENODEV, and
>>> add that in Documentation/virtual/kvm/api.txt ?
>>
>> Not sure. If you ended up here, it means you tried to start a 32bit
>> guest on a 64bit-only CPU, despite KVM_CAP_ARM_EL1_32BIT telling you
>> that your CPU is not 32bit capable.
>>
>> This is clearly an invalid input, isn't it?
>>
> check the API documentation for this ioctl, I don't think that's the
> type of invalid input meant when describing the meaning of EINVAL. If
> you feel strongly about it of course it's no big deal, but I think
> EINVAL is so overloaded anyway that telling the user something more
> specific would be great, but I'll leave it up to you.

[bit late on this one...]

Here's what the documentation says:
<quote>
4.77 KVM_ARM_VCPU_INIT

Capability: basic
Architectures: arm, arm64
Type: vcpu ioctl
Parameters: struct struct kvm_vcpu_init (in)
Returns: 0 on success; -1 on error
Errors:
  EINVAL:    the target is unknown, or the combination of features is invalid.
  ENOENT:    a features bit specified is unknown.
</quote>

When this call fails, it is because you've requested a feature
that is invalid for this CPU. To me, that exactly fits the
EINVAL entry copied above.

Or am I completely misunderstanding it?

	M.
-- 
Jazz is not dead. It just smells funny...



From john.stultz at linaro.org  Tue May  7 12:39:58 2013
From: john.stultz at linaro.org (John Stultz)
Date: Tue, 07 May 2013 09:39:58 -0700
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <20130507135752.GA3500@amd.pavel.ucw.cz>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de> <20130506155304.GA6645@amd.pavel.ucw.cz>
 <201305062324.17080.arnd@arndb.de> <20130507135752.GA3500@amd.pavel.ucw.cz>
Message-ID: <51892E5E.8090909@linaro.org>

On 05/07/2013 06:57 AM, Pavel Machek wrote:
>>> So I guess it should go through the timekeeping tree...?
>> I would prefer that, but we can also take it through arm-soc, it doesn't
>> really matter.
> I see no response from timekeeping people... so if you could take it,
> that would be great.

I don't think the original patch ever made it to my inbox.

thanks
-john




From itooo at itooo.com  Tue May  7 12:40:39 2013
From: itooo at itooo.com (Greg)
Date: Tue, 07 May 2013 18:40:39 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <20130507181823.23342ffb@skate>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
Message-ID: <51892E87.5020903@itooo.com>

Le 07/05/2013 18:18, Thomas Petazzoni a ?crit :
> Dear Greg,
>
> On Tue, 07 May 2013 16:14:01 +0200, Greg wrote:
>
>> I'm trying to boot off the the backport-3.-8 kernel with armada-xp-db DT
>> file.
>>
>> When eth0 is brought up (I'm booting on NFS) the mvneta driver fails in
>> mvneta_open, with the following error :
>>> mvneta d0070000.ethernet eth0: cannot request irq 25
>> The oddness is this is not the actual IRQ to be requested, and the DTS
>> files explicitly specify the IRQ is 8 for this device.
>>
>> I'm not familiar with the DT system, where should I start looking to
>> find the source of the problem ?
> This issue should be fixed by:
>
> commit 7f23f62fc31c5c97947414c0937a72e08a947a41
> Author: Gregory CLEMENT <gregory.clement at free-electrons.com>
> Date:   Wed Mar 20 16:09:35 2013 +0100
>
>      arm: mvebu: Use local interrupt only for the timer 0
>      
>      The commit 3a6f08a37 "arm: mvebu: Add support for local interrupt",
>      managed the 28th first interrupts as local interrupt to match the
>      hardware specification. Among these interrupts there are the Gigabits
>      Ethernet ones used by the mvneta driver. Unfortunately the state of
>      the percpu_irq API prevents the driver to use it.
>      
>      Indeed the interrupts have to be freed when the .stop() function is
>      called. As the free_percpu_irq() function don't disable the interrupt
>      line, we have to do it on each CPU before calling this. The function
>      disable_percpu_irq() only disable the percpu on the current CPU and
>      there is no function which allows to disable a percpu irq on a given
>      CPU. Waiting for the extension of the percpu_irq API, this fix allows
>      to use again the mvneta driver.
>      
>      Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
>      Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>      Tested-by: Masami Hiramatsu <masami.hiramatsu.pt at hitachi.com>
>      Signed-off-by: Jason Cooper <jason at lakedaemon.net>
>
> which is part of the backport-3.8 branch, so I'm a bit confused. Are
> you sure you're using the latest backport-3.8 branch? If so, then I'll
> do a test here to check this.
>
By the way, the patch IS applied to the source tree I'm compiling.
I can see this in arch/arm/mach-mvebu/irq-armada-370-xp.c which is using 
ARMADA_370_XP_TIMER0_PER_CPU_IRQ instead of ARMADA_370_XP_MAX_PER_CPU_IRQS

Cheers,


From jaswinder.singh at linaro.org  Tue May  7 12:56:07 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Tue, 7 May 2013 22:26:07 +0530
Subject: [PATCHv2 3/4] mailbox: pl320: Introduce common API driver
In-Reply-To: <51885FC4.7000401@gmail.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825063-6263-1-git-send-email-jaswinder.singh@linaro.org>
 <51885FC4.7000401@gmail.com>
Message-ID: <CAJe_ZheEut1fbifGeWfiZmar0zm_ZgdzygeaAYTOitSR_tqbiA@mail.gmail.com>

On 7 May 2013 07:28, Rob Herring <robherring2 at gmail.com> wrote:
> On 05/06/2013 02:24 AM, Jassi Brar wrote:
>> Convert the PL320 controller driver to work with the common
>> mailbox API. Also convert the only user of PL320, highbank-cpufreq.c
>> to work with thee API. Drop the obsoleted driver pl320-ipc.c
>>
>> Signed-off-by: Jassi Brar <jaswinder.singh at linaro.org>
>> ---
>>  drivers/cpufreq/highbank-cpufreq.c |   22 +++-
>>  drivers/mailbox/Makefile           |    2 +-
>>  drivers/mailbox/pl320-ipc.c        |  198 ---------------------------------
>>  drivers/mailbox/pl320.c            |  212 ++++++++++++++++++++++++++++++++++++
>
> Can you resend this using git format-patch -M option.
>
IIRC I already did that. Anyways I just checked -M doesn't produce
anything different for the patch. Except for headers, defines and
module init rituals, everything else is from scratch.

-Jassi


From torvalds at linux-foundation.org  Tue May  7 13:02:22 2013
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Tue, 7 May 2013 10:02:22 -0700
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
In-Reply-To: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
Message-ID: <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>

On Tue, May 7, 2013 at 9:02 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>
> I used a new script to create the pull requests this time, hope
> I got it right now.

So you seem to have blasted this series out with that automated
script, so they all got sent basically at the same timestamp, and they
are in the wrong order in my mailbox because email isn't that ordered.

Which is very annoying when there is no obvious way to tell what the
ordering between the pulls are *and* they are clearly not independent.
It turns out that I tried to merge "part 3" before "part 2", because I
hadn't noticed that small detail, and "part 3" was first in my inbox.

If you have pull requests that depend on each other, please number
them CLEARLY ("part 3" may sound clear, but it's not at all so when
I've done 123 merges in the last 10 days, and I can't remember if
perhaps two of those are earlier merges from you. Or at least delay
sending them out by a few seconds in between, so that email systems
don't tend to re-order them.

Or, in fact, preferably both.

Of course, when there aren't any dependencies between pull requests,
and the ordering doesn't matter, this isn't an issue. And *most* of
the time you either have sent out emails by hand (and there's been
that human delay and they arrived in the right order) or I've just
been lucky.

So if ordering matters, I really prefer to see [git pull 1/3] or
something like that at the beginning of the subject line. That is
visually clear, and unambiguous. And/or a few seconds or more between
sends - sure, email  may still get re-ordered, but in the modern world
that tends to be unlikely to happen for stuff that is more than a
second or two apart.

Please do NOT do what you did here. Everything got batched up and sent
in the same second, and the numbering was unclear AS HELL. There's a
"device tree changes, part 2", which isn't unreadable on its own (just
not very obvious), but THERE IS NO PART ONE! Similarly, there are
"arm-soc platform updates" parts 2 and 3, but again, there is no "part
1".

WTF? Seriously, I have no clue. Is the "late Exynos multiplatform
changes" the "part 1" of the device tree changes or the platform
changes? It could be either. And the "late cleanups"? Are they the
"part 1" of the other series (that didn't have the Exynos changes), or
are they "late" and come after everything?

Quite frankly, I'm not going to bother guessing after the first one I
took was clearly not the right one and gave the wrong diffstat etc, so
they are all thrown down the toilet.

Nothing pulled.

               Linus


From arnd at arndb.de  Tue May  7 13:19:53 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 May 2013 19:19:53 +0200
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
In-Reply-To: <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
 <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>
Message-ID: <201305071919.53353.arnd@arndb.de>

On Tuesday 07 May 2013, Linus Torvalds wrote:
> On Tue, May 7, 2013 at 9:02 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> >
> > I used a new script to create the pull requests this time, hope
> > I got it right now.
> 
> So you seem to have blasted this series out with that automated
> script, so they all got sent basically at the same timestamp, and they
> are in the wrong order in my mailbox because email isn't that ordered.

Yep, I'm very sorry about that. The old script I used had been a bit
fragile so I stopped using it for the last few merge windows
but tried something simpler this time. I had the sequence numbers
in the script but forgot to actually write them out in the subject.

> Of course, when there aren't any dependencies between pull requests,
> and the ordering doesn't matter, this isn't an issue. And *most* of
> the time you either have sent out emails by hand (and there's been
> that human delay and they arrived in the right order) or I've just
> been lucky.

I think it's the first time I made /this/ mistake, they were always
numbered in the past, and usually also had distinct time stamps.
 
> Quite frankly, I'm not going to bother guessing after the first one I
> took was clearly not the right one and gave the wrong diffstat etc, so
> they are all thrown down the toilet.
> 
> Nothing pulled.

Yes, of course. It was an obvious mistake and I would have rejected
it the same way coming from my downstream maintainers. Sorry about
bothering you with this and your lenghty reply. I hope you don't
mind the contents, and I'll follow up with the same pull requests
again, using sequence numbers.

	Arnd



From arnd at arndb.de  Tue May  7 13:26:09 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 19:26:09 +0200
Subject: [GIT PULL 0/5] ARM: Third batch of arm-soc changes for 3.10, again
Message-ID: <1367947574-2934383-1-git-send-email-arnd@arndb.de>

Hi Linus,

Here are the same pull requests as before, with numbers and distinct
time stamps. I hope I didn't screw up in a different way this time.

	Arnd


From arnd at arndb.de  Tue May  7 13:26:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 19:26:10 +0200
Subject: [GIT PULL 1/5] ARM: arm-soc platform updates for 3.10, part 2
In-Reply-To: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
Message-ID: <1367947574-2934383-2-git-send-email-arnd@arndb.de>

These patches are all for Renesas shmobile, and depend on the earlier
pinctrl updates. Remarkably, this adds support for three new SoCs:
r8a73a4, r8a73a4 and r8a7778. The bulk of the code added for these is
for pinctrl (using the new subsystem) and for clocks (not yet using the
common clock subsystem). The latter will have to get converted in one
of the upcoming releases, but shmobile is not ready for that yet.

The series also contains Renesas shmobile board changes, adding one
board file for each of the three new SoCs.  These boards are using a
mix of classic and device-tree based probing, as there is still a lot of
infrastructure in shmobile that has not been converted to DT yet. Once
those are resolved to the degree that no board specific setup code is
needed, they can get folded into the respective SoC setup files.

Conflicts:
- A line added in board-armadillo800eva.c conflicts with a
  changed line.


-------------------------------------------------------------

The following changes since commit

   150a8dc Merge tag 'boards-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/soc-for-linus-2

you to fetch changes up to

   9251c6c Merge tag 'renesas-boards-lager-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2


-------------------------------------------------------------

Arnd Bergmann (3):
      Merge tag 'renesas-defconfig-bockw-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2
      Merge tag 'renesas-boards-bockw-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2
      Merge tag 'soc-for-linus-2' into for-next

Bastian Hecht (1):
      ARM: shmobile: r8a7740: Migrate from INTC to GIC

Guennadi Liakhovetski (9):
      ARM: shmobile: sh73a0: wait for completion when kicking the clock
      ARM: shmobile: sh73a0: add irqpin DT nodes
      ARM: shmobile: sh73a0: add a TWD clock
      ARM: shmobile: kzm9g-reference: add ethernet support
      ARM: shmobile: mackerel: SDHI resources do not have to be numbered
      ARM: shmobile: mackerel: remove OCR masks, where regulators are used
      ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio
      ARM: shmobile: mackerel: add interrupt names for SDHI0
      ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection

Kuninori Morimoto (21):
      ARM: shmobile: add R8A7778 basis support
      ARM: shmobile: r8a7778 SCIF support
      ARM: shmobile: r8a73a4: add thermal driver support
      ARM: shmobile: sh73a0: remove DIV4_ZT* clocks
      ARM: shmobile: sh7372: remove DIV4_ZT* clocks
      ARM: shmobile: add struct clk_ratio and fixed ratio clock macro
      ARM: shmobile: sh7372: use fixed ratio clock
      ARM: shmobile: sh73a0: use fixed ratio clock
      ARM: shmobile: r8a7740: tidyup comment/implementation mismatch
      ARM: shmobile: r8a7740: use fixed ratio clock
      ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock
      ARM: shmobile: sh7372: move global functions to sh7372.h
      ARM: shmobile: sh73a0: move global functions to sh73a0.h
      ARM: shmobile: r8a7740: move global functions to r8a7740.h
      ARM: shmobile: r8a7779: move global functions to r8a7779.h
      ARM: shmobile: add R-Car M1A Bock-W platform support
      ARM: shmobile: r8a7778: remove pointless PLATFORM_INFO()
      ARM: shmobile: r8a7778: add r8a7778_init_irq_extpin()
      ARM: shmobile: bockw: enable SMSC ethernet on defconfig
      ARM: shmobile: bockw: add SMSC ethernet support
      ARM: shmobile: bockw: enable network settings on bootargs

Laurent Pinchart (14):
      sh-pfc: Fix compiler warning when BUG()
      sh: sh7269: Fix compilation by adding missing includes
      sh-pfc: r8a7779: Remove function GPIOs
      sh-pfc: r8a7779: Don't use GPIO enum entries
      ARM: shmobile: r8a7779: Remove all GPIOs
      gpio-rcar: Add pinctrl support
      ARM: shmobile: marzen: Add GPIO LEDs
      sh-pfc: Make function GPIOs support optional
      sh-pfc: Make GPIO support optional
      sh-pfc: Skip gpiochip registration when no GPIO resource is found
      sh-pfc: Configure pins as GPIOs at request time when handled externally
      ARM: shmobile: r8a7779: Register GPIO devices
      sh-pfc: r8a7779: Remove GPIO data
      sh-pfc: r8a7779: Split DU input and output pixel clocks

Magnus Damm (30):
      ARM: shmobile: Initial r8a73a4 SoC support V3
      ARM: shmobile: r8a73a4 SCIF support V3
      ARM: shmobile: r8a73a4 IRQC support V2
      ARM: shmobile: r8a73a4 PFC support
      ARM: shmobile: Disallow PINCTRL without GPIOLIB
      ARM: shmobile: Initial r8a7790 SoC support
      ARM: shmobile: r8a7790 SCIF support
      ARM: shmobile: r8a7790 IRQC support
      ARM: shmobile: r8a7790 PFC support
      gpio: Renesas R-Car GPIO driver V3
      sh-pfc: Add r8a73a4 pinmux support
      sh-pfc: r8a73a4: Support sparse GPIO numbers
      sh-pfc: r8a73a4: GPIO IRQ support
      sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
      sh-pfc: r8a73a4: Add SCIF pin groups and functions
      sh-pfc: r8a73a4: Add IRQC pin groups and functions
      sh-pfc: r8a73a4: Remove SCIF function GPIOS
      sh-pfc: r8a73a4: Remove IRQC function GPIOS
      ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
      ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
      sh-pfc: r8a73a4: Remove function GPIOs
      ARM: shmobile: r8a73a4: Remove all GPIO enums
      sh-pfc: r8a73a4: Remove unused GPIO bias data
      ARM: shmobile: APE6EVM base support
      ARM: shmobile: APE6EVM PFC support
      ARM: shmobile: APE6EVM LAN9220 support
      ARM: shmobile: Initial r8a7790 Lager board support
      ARM: shmobile: Add second I/O range for r8a7790 PFC
      ARM: shmobile: force enable of r8a7790 arch timer
      ARM: shmobile: use r8a7790 timer setup code on Lager

Olof Johansson (2):
      Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2
      Merge tag 'renesas-boards-lager-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/boards2

Sergei Shtylyov (1):
      ARM: shmobile: R8A7778: add Ether support

Simon Horman (5):
      Merge tag 'renesas-intc-external-irq2-for-v3.10' into soc-base
      Merge branch 'soc' into pinmux-base
      Merge tag 'renesas-pinmux2-for-v3.10' into boards-base
      Merge branch 'soc-r8a7778' into boards-bockw-base
      Merge branch 'soc-r8a7790' into boards-lager

Takashi YOSHII (2):
      ARM: shmobile: r8a73a4 SoC 64-bit DT support
      ARM: shmobile: r8a7790 SoC 64-bit DT support

 arch/arm/Kconfig                               |    2 +-
 arch/arm/boot/dts/Makefile                     |    3 +
 arch/arm/boot/dts/r8a73a4-ape6evm.dts          |   52 +
 arch/arm/boot/dts/r8a73a4.dtsi                 |   94 +
 arch/arm/boot/dts/r8a7778-bockw.dts            |   32 +
 arch/arm/boot/dts/r8a7778.dtsi                 |   35 +
 arch/arm/boot/dts/r8a7790-lager.dts            |   31 +
 arch/arm/boot/dts/r8a7790.dtsi                 |   63 +
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts   |   13 +
 arch/arm/boot/dts/sh73a0.dtsi                  |   81 +
 arch/arm/configs/bockw_defconfig               |   94 +
 arch/arm/mach-shmobile/Kconfig                 |   48 +-
 arch/arm/mach-shmobile/Makefile                |    6 +
 arch/arm/mach-shmobile/board-ape6evm.c         |   94 +
 arch/arm/mach-shmobile/board-armadillo800eva.c |   35 +-
 arch/arm/mach-shmobile/board-bockw.c           |   81 +
 arch/arm/mach-shmobile/board-lager.c           |   46 +
 arch/arm/mach-shmobile/board-mackerel.c        |  111 +-
 arch/arm/mach-shmobile/board-marzen.c          |   32 +
 arch/arm/mach-shmobile/clock-r8a73a4.c         |  115 ++
 arch/arm/mach-shmobile/clock-r8a7740.c         |  114 +-
 arch/arm/mach-shmobile/clock-r8a7778.c         |  107 +
 arch/arm/mach-shmobile/clock-r8a7779.c         |  196 +-
 arch/arm/mach-shmobile/clock-r8a7790.c         |   93 +
 arch/arm/mach-shmobile/clock-sh7372.c          |   50 +-
 arch/arm/mach-shmobile/clock-sh73a0.c          |  115 +-
 arch/arm/mach-shmobile/clock.c                 |   13 +
 arch/arm/mach-shmobile/include/mach/clock.h    |   39 +
 arch/arm/mach-shmobile/include/mach/common.h   |   54 -
 arch/arm/mach-shmobile/include/mach/r8a73a4.h  |    8 +
 arch/arm/mach-shmobile/include/mach/r8a7740.h  |    9 +
 arch/arm/mach-shmobile/include/mach/r8a7778.h  |   32 +
 arch/arm/mach-shmobile/include/mach/r8a7779.h  |  330 +--
 arch/arm/mach-shmobile/include/mach/r8a7790.h  |    9 +
 arch/arm/mach-shmobile/include/mach/sh7372.h   |   12 +
 arch/arm/mach-shmobile/include/mach/sh73a0.h   |   15 +
 arch/arm/mach-shmobile/intc-r8a7740.c          |  641 +-----
 arch/arm/mach-shmobile/setup-r8a73a4.c         |  202 ++
 arch/arm/mach-shmobile/setup-r8a7740.c         |  192 +-
 arch/arm/mach-shmobile/setup-r8a7778.c         |  244 +++
 arch/arm/mach-shmobile/setup-r8a7779.c         |   58 +-
 arch/arm/mach-shmobile/setup-r8a7790.c         |  150 ++
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c        |    2 +
 drivers/gpio/Kconfig                           |    6 +
 drivers/gpio/Makefile                          |    1 +
 drivers/gpio/gpio-rcar.c                       |  396 ++++
 drivers/pinctrl/sh-pfc/Kconfig                 |    5 +
 drivers/pinctrl/sh-pfc/Makefile                |    1 +
 drivers/pinctrl/sh-pfc/core.c                  |   41 +-
 drivers/pinctrl/sh-pfc/core.h                  |    1 +
 drivers/pinctrl/sh-pfc/gpio.c                  |   45 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c           | 2587 ++++++++++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c           |   64 +-
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c           |  479 +----
 drivers/pinctrl/sh-pfc/pinctrl.c               |   11 +
 include/linux/platform_data/gpio-rcar.h        |   26 +
 56 files changed, 5588 insertions(+), 1828 deletions(-)


From arnd at arndb.de  Tue May  7 13:26:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 19:26:11 +0200
Subject: [GIT PULL 2/5] ARM: arm-soc platform updates for 3.10, part 3
In-Reply-To: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
Message-ID: <1367947574-2934383-3-git-send-email-arnd@arndb.de>

This is the third and smallest of the SoC specific updates.
Changes include:

* SMP support for the Xilinx zynq platform
* Smaller imx changes
* LPAE support for mvebu
* Moving the orion5x, kirkwood, dove and mvebu platforms
  to a common "mbus" driver for their internal devices.

It would be good to get feedback on the location of the "mbus"
driver. Since this is used on multiple platforms may potentially
get shared with other architectures (powerpc and arm64), it
was moved to drivers/bus/. We expect other similar drivers to
get moved to the same place in order to avoid creating more
top-level directories under drivers/ or cluttering up the
messy drivers/misc/ even more.

Conflicts:
 - drivers/gpio/gpio-pl061.c had a trivial add/add conflict that
   got resolved in two different ways, both of which are ok.


-------------------------------------------------------------

The following changes since commit

   48f934c Merge tag 'soc-for-linus-2' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/soc-for-linus-3

you to fetch changes up to

   5c5f042 ARM: imx: reset_controller may be disabled

-------------------------------------------------------------

Anson Huang (3):
      ARM: imx: enable anatop suspend/resume
      ARM: imx: enable periphery well bias for suspend
      ARM: imx: enable RBC to support anatop LPM mode

Arnd Bergmann (6):
      Merge branch 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx into next/soc2
      Merge branch 'gic/cleanup' into next/soc2
      Merge tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-soc-r8a7778-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      ARM: imx: reset_controller may be disabled
      Merge tag 'soc-for-linus-3' into for-next

Fabio Estevam (3):
      ARM: mach-imx: anatop: Include "common.h"
      ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
      ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS

Gregory CLEMENT (1):
      ARM: mvebu: Limit the DMA zone when LPAE is selected

Gwenhael Goavec-Merou (1):
      ARM: imx1: mm: add call to mxc_device_init

Jason Cooper (2):
      Merge tag 'tags/cleanup_for_v3.10' into mvebu/soc
      Merge tag 'tags/drivers_for_v3.10' into mvebu/soc

Kuninori Morimoto (2):
      ARM: shmobile: r8a7779: add each clocks ratio on comment area
      sh-pfc: r8a7779: tidyup intc_irq3_b typo

Lior Amsalem (1):
      ARM: mvebu: Align the internal registers virtual base to support LPAE

Markus Pargmann (1):
      ARM: imx27, imx5: Add kconfig selects for cpufreq-cpu0

Martin Fuzzey (1):
      ARM: i.MX53 Add the cko1, cko2 clock outputs.

Michal Simek (7):
      arm: zynq: Load scu baseaddress at run time
      arm: zynq: Move slcr initialization to separate file
      arm: zynq: Add support for system reset
      arm: zynq: Get rid of xilinx function prefix
      arm: zynq: Add smp_twd timer
      arm: zynq: Add smp support
      arm: zynq: Add hotplug support

Neil Greatorex (1):
      bus: mvebu-mbus: Restore checking for coherency fabric hardware

Olof Johansson (6):
      Merge tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-pinmux-fixes-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'renesas-soc-r8a7790-for-v3.10' of git://git.kernel.org/.../horms/renesas into next/soc2
      Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc2
      Merge tag 'soc_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/soc2

Philipp Zabel (14):
      ARM i.MX53: Add GPU clocks to clock tree
      ARM i.MX6q: export imx6q_revision
      ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
      ARM i.MX53: fix ldb di divider and selector clocks
      ARM i.MX6q: fix ldb di divider and selector clocks
      ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
      ARM i.MX6q: set the LDB serial clock parent to the video PLL
      ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
      staging: drm/imx: Use SRC to reset IPU
      ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
      ARM i.MX53: Remove unused tve_gate clkdev entry
      ARM i.MX53: make tve_ext_sel propagate rate change to PLL
      ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
      ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock

Sascha Hauer (1):
      ARM: i.MX5: Add PATA and SRTC clocks

Sergei Shtylyov (1):
      ARM: shmobile: R8A7779: add Ether support

Shawn Guo (6):
      Merge tag 'imx-fixes-3.9-5' into imx/soc
      Merge tag 'imx-cleanup-3.10' into imx/soc
      Merge remote-tracking branch 'pza/reset/for_v3.10' into imx/soc
      ARM: imx: do not use regmap_read for ANADIG_DIGPROG
      ARM: imx: add initial imx6dl support
      ARM: imx: do not bring up unavailable cores

Simon Guinot (1):
      ARM: Orion: add dbg_show function to gpio-orion driver

Thomas Petazzoni (8):
      bus: introduce an Marvell EBU MBus driver
      bus: mvebu: fix mistake in PCIe window target attribute for Kirkwood
      arm: mach-mvebu: convert to use mvebu-mbus driver
      arm: mach-kirkwood: convert to use mvebu-mbus driver
      arm: mach-dove: convert to use mvebu-mbus driver
      arm: mach-orion5x: convert to use mvebu-mbus driver
      arm: mach-mv78xx0: convert to use the mvebu-mbus driver
      arm: plat-orion: remove addr-map code

 .../devicetree/bindings/clock/imx5-clock.txt       |  14 +-
 .../devicetree/bindings/clock/imx6q-clock.txt      |   3 +
 .../devicetree/bindings/reset/fsl,imx-src.txt      |  49 ++
 .../bindings/staging/imx-drm/fsl-imx-drm.txt       |   3 +
 arch/arm/Kconfig                                   |   4 +
 arch/arm/Kconfig.debug                             |   4 +-
 arch/arm/boot/dts/armada-370-xp.dtsi               |   5 -
 arch/arm/boot/dts/zynq-7000.dtsi                   |   7 +
 arch/arm/configs/imx_v4_v5_defconfig               |   1 +
 arch/arm/configs/imx_v6_v7_defconfig               |   1 +
 arch/arm/include/debug/mvebu.S                     |   2 +-
 arch/arm/mach-dove/Makefile                        |   2 +-
 arch/arm/mach-dove/addr-map.c                      | 125 ---
 arch/arm/mach-dove/board-dt.c                      |   2 +-
 arch/arm/mach-dove/common.c                        |  39 +-
 arch/arm/mach-dove/common.h                        |   2 +-
 arch/arm/mach-dove/include/mach/dove.h             |   5 +
 arch/arm/mach-imx/Kconfig                          |  10 +-
 arch/arm/mach-imx/Makefile                         |   1 +
 arch/arm/mach-imx/anatop.c                         | 103 +++
 arch/arm/mach-imx/clk-imx51-imx53.c                |  75 +-
 arch/arm/mach-imx/clk-imx6q.c                      | 126 ++-
 arch/arm/mach-imx/clk.h                            |  17 +
 arch/arm/mach-imx/common.h                         |  10 +-
 arch/arm/mach-imx/gpc.c                            |  23 +-
 arch/arm/mach-imx/mach-imx6q.c                     |  74 +-
 arch/arm/mach-imx/mm-imx1.c                        |   2 +
 arch/arm/mach-imx/mxc.h                            |  11 +
 arch/arm/mach-imx/platsmp.c                        |   4 +-
 arch/arm/mach-imx/pm-imx6q.c                       |   4 +-
 arch/arm/mach-imx/src.c                            |  66 ++
 arch/arm/mach-kirkwood/Makefile                    |   2 +-
 arch/arm/mach-kirkwood/addr-map.c                  |  91 ---
 arch/arm/mach-kirkwood/board-dt.c                  |   2 +-
 arch/arm/mach-kirkwood/common.c                    |  38 +-
 arch/arm/mach-kirkwood/common.h                    |   2 +-
 arch/arm/mach-kirkwood/include/mach/kirkwood.h     |   7 +-
 arch/arm/mach-kirkwood/pcie.c                      |   1 -
 arch/arm/mach-mv78xx0/Makefile                     |   2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |  93 ---
 arch/arm/mach-mv78xx0/common.c                     |  10 +-
 arch/arm/mach-mv78xx0/include/mach/mv78xx0.h       |   9 +-
 arch/arm/mach-mv78xx0/pcie.c                       |  21 +-
 arch/arm/mach-mvebu/Kconfig                        |   2 +
 arch/arm/mach-mvebu/Makefile                       |   2 +-
 arch/arm/mach-mvebu/addr-map.c                     | 137 ----
 arch/arm/mach-mvebu/armada-370-xp.c                |  18 +
 arch/arm/mach-mvebu/armada-370-xp.h                |   8 +-
 arch/arm/mach-mvebu/platsmp.c                      |   2 +
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/addr-map.c                   | 155 ----
 arch/arm/mach-orion5x/board-dt.c                   |   2 +-
 arch/arm/mach-orion5x/common.c                     |  49 +-
 arch/arm/mach-orion5x/common.h                     |  13 +-
 arch/arm/mach-orion5x/d2net-setup.c                |   4 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |  13 +-
 arch/arm/mach-orion5x/dns323-setup.c               |   3 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |   4 +-
 arch/arm/mach-orion5x/include/mach/orion5x.h       |   6 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |   8 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |   4 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |   4 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |   4 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |   3 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |   3 +-
 arch/arm/mach-orion5x/net2big-setup.c              |   4 +-
 arch/arm/mach-orion5x/pci.c                        |   7 +-
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |   4 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |   4 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |   7 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |   4 +-
 arch/arm/mach-orion5x/ts209-setup.c                |   4 +-
 arch/arm/mach-orion5x/ts409-setup.c                |   4 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |   4 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |   4 +-
 arch/arm/mach-shmobile/clock-r8a7779.c             |  23 +-
 arch/arm/mach-shmobile/include/mach/r8a7779.h      |   2 +
 arch/arm/mach-shmobile/setup-r8a7779.c             |  23 +-
 arch/arm/mach-zynq/Kconfig                         |   1 +
 arch/arm/mach-zynq/Makefile                        |   6 +-
 arch/arm/mach-zynq/common.c                        |  67 +-
 arch/arm/mach-zynq/common.h                        |  20 +
 arch/arm/mach-zynq/headsmp.S                       |  24 +
 arch/arm/mach-zynq/hotplug.c                       | 104 +++
 arch/arm/mach-zynq/platsmp.c                       | 136 ++++
 arch/arm/mach-zynq/slcr.c                          | 125 +++
 arch/arm/plat-orion/Makefile                       |   6 -
 arch/arm/plat-orion/addr-map.c                     | 178 -----
 arch/arm/plat-orion/gpio.c                         |  59 ++
 drivers/bus/Kconfig                                |   7 +
 drivers/bus/Makefile                               |   1 +
 drivers/bus/mvebu-mbus.c                           | 870 +++++++++++++++++++++
 drivers/gpio/gpio-pl061.c                          |   2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c               |   2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-common.c        |  12 +-
 include/linux/mbus.h                               |  27 +-
 96 files changed, 2257 insertions(+), 1002 deletions(-)


From arnd at arndb.de  Tue May  7 13:26:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 19:26:12 +0200
Subject: [GIT PULL 3/5] ARM: arm-soc device tree changes, part 2
In-Reply-To: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
Message-ID: <1367947574-2934383-4-git-send-email-arnd@arndb.de>

These are mostly new device tree bindings for existing drivers, as well
as changes to the device tree source files to add support for those
devices, and a couple of new boards, most notably Samsung's Exynos5
based Chromebook.

The changes depend on earlier platform specific updates and touch
the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci.

Conflicts:
 Simple add/add conflicts in arch/arm/boot/dts/exynos5250.dtsi and
 arch/arm/mach-omap2/omap_hwmod.c. In the former, be careful to
 include the closing curly braces and semicolon.


-------------------------------------------------------------

The following changes since commit

   9822346 Merge tag 'soc-for-linus-3' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/dt-for-linus-2

you to fetch changes up to

   4183bef Merge branch 'late/dt' into next/dt2


-------------------------------------------------------------

Alexander Graf (2):
      ARM: dts: Declare the gic as a15 compatible for exynos5250
      ARM: dts: Add architected timer nodes for exynos5250

Alexandre Belloni (3):
      ARM: cfa10036: add one wire bitbanging to the cfa10049
      pinctrl: pinctrl-mxs: document the missing pull-ups
      ARM: dts: cfa10036: Add touchscreen support to the CFA-10049

Alexandre Pereira da Silva (1):
      ARM: dts: imx23-olinuxino: mark sdcard cd as broken

Amit Daniel Kachhap (2):
      ARM: dts: Add PMIC node entry for Arndale board
      ARM: dts: Add cpufreq controller node for Exynos5440 SoC

Andrew Chew (2):
      ARM: tegra: fix the status of PWM DT nodes
      ARM: tegra: add PWM nodes to Tegra114 DT

Anil Kumar (3):
      ARM: dts: Add minimal DT support for DevKit8000
      ARM: dts: omap3-devkit8000: Enable audio support
      ARM: dts: omap3-devkit8000: Add NAND DT node

AnilKumar Ch (3):
      ARM: dts: AM33XX: Rename I2C and GPIO nodes
      ARM: dts: AM33XX: Add d_can instances to aliases
      ARM: dts: AM33XX: Add memory resource to d_can node

Arnd Bergmann (6):
      Merge branch 'mxs/cleanup' into next/dt2
      Merge tag 'mxs-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt2
      Merge branch 'tegra/clk' into next/dt2
      Merge tag 'tegra-for-3.10-dt' of git://git.kernel.org/.../swarren/linux-tegra into next/dt2
      Merge branch 'late/dt' into next/dt2
      Merge tag 'dt-for-linus-2' into for-next

Benoit Cousson (1):
      Merge tag 'omap-devel-b-for-3.10' of git://git.kernel.org/.../pjw/omap-pending into for_3.10/dts_merged

Byungho An (1):
      ARM: dts: Add node for GMAC for exynos5440

Christoph Fritz (1):
      ARM/dts: OMAP3: fix pinctrl-single configuration

Doug Anderson (4):
      ARM: dts: add usb 2.0 clock references to exynos5250 device tree
      ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings
      ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
      ARM: dts: Add sbs-battery for exynos5250-snow

Fabio Estevam (1):
      video: mxsfb: Introduce regulator support

Felipe Balbi (1):
      ARM: dts: OMAP5: Add SPI nodes

Florian Vaussard (3):
      ARM: dts: omap3-overo: Add support for pwm-leds
      ARM: dts: omap3-overo: Add audio support
      ARM: dts: OMAP3: Add GPMC controller

Giridhar Maruthy (1):
      ARM: dts: Add virtual GIC DT bindings for exynos5440

Gregory CLEMENT (3):
      ARM: dts: mvebu: Convert all the mvebu files to use the range property
      ARM: dts: mvebu: introduce internal-regs node
      ARM: dts: mvebu: Convert mvebu device tree files to 64 bits

Jason Cooper (2):
      Merge tag 'tags/mvebu_fixes_for_v3.9_round3' into mvebu/dt
      Merge tag 'tags/soc_for_v3.10' into mvebu/dt

Javier Martinez Canillas (5):
      ARM: dts: omap3: Add generic DT support for IGEP devices
      ARM: dts: omap3: Add support for IGEPv2 board
      ARM: dts: omap3: Add support for IGEP COM Module
      ARM: dts: OMAP3: reduce GPMC mapped registers address space
      Documentation: dt: gpio-omap: Move interrupt-controller from #interrupt-cells description

Jon Hunter (16):
      ARM: OMAP2+: Prepare for device-tree PMU support
      ARM: dts: OMAP2+: Add PMU nodes
      ARM: dts: OMAP2+: Add SDMA controller bindings and nodes
      ARM: dts: Add GPMC node for OMAP2, OMAP4 and OMAP5
      ARM: dts: Add OMAP2 gpio bindings
      ARM: dts: OMAP3+: Correct gpio #interrupts-cells property
      ARM: dts: OMAP3: Add reg and interrupt properties for gpio
      ARM: dts: OMAP3: Add support for OMAP3430 SDP board
      ARM: OMAP: Force dmtimer restore if context loss is not detectable
      ARM: OMAP: Add function to request timer by node
      ARM: dts: OMAP2+: Update DMTIMER compatibility property
      ARM: OMAP2+: Populate DMTIMER errata when using device-tree
      ARM: dts: OMAP2+: Identify GPIO banks that are always powered
      ARM: dts: Update OMAP3430 SDP NAND and ONENAND properties
      ARM: dts: Add NOR flash bindings for OMAP2420 H4
      ARM: dts: Add OMAP3430 SDP NOR flash memory binding

Joseph Lo (4):
      ARM: tegra: add power gpio keys to DT
      ARM: tegra: whistler: add wakeup source for KBC
      ARM: tegra: add non-removable and keep-power-in-suspend property for MMC
      ARM: dts: tegra: add the PM configurations of PMC

Kishon Vijay Abraham I (7):
      ARM: dts: OMAP4: Add omap control usb data
      ARM: dts: OMAP4: Add omap-usb2 data
      ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
      ARM: dts: OMAP5: Add OMAP control usb data
      ARM: dts: OMAP5: Add ocp2scp data
      ARM: dts: OMAP5: Add omap-usb3 and omap-usb2 data
      ARM: dts: OMAP5: add dwc3 omap and dwc3 core data

Kukjin Kim (1):
      ARM: dts: add device tree file for SD5v1 board

Laxman Dewangan (9):
      ARM: tegra: add APB DMA nodes to Tegra114 DT
      ARM: tegra: add I2C nodes to Tegra114 DT
      ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114
      ARM: tegra: add KBC nodes to Tegra114 DT
      ARM: tegra: add SPI nodes to Tegra114 DT
      ARM: tegra: add DT binding for i2c-tegra
      ARM: tegra: dalmore: add cpu regulator node
      ARM: tegra: dalmore: add TPS65090 node
      ARM: tegra: dalmore: add fixed regulator node

Leela Krishna Amudala (2):
      ARM: dts: Add FIMD node to exynos5
      ARM: dts: Add display timing node to exynos5250-smdk5250.dts

Lokesh Vutla (1):
      ARM: dts: OMAP5: Add watchdog timer node

Manjunathappa, Prakash (4):
      spi/davinci: no wildcards in DT compatible property
      ARM: davinci: da850: add SPI1 DT node
      ARM: davinci: da850: override SPI DT node device name
      ARM: davinci: da850-evm: add SPI flash support

Matthias Brugger (1):
      ARM: dts: omap3-igep: Add uart1 and uart2 to igep boards

Murali Karicheri (1):
      spi/davinci: add DT binding documentation

NeilBrown (1):
      ARM: OMAP: Simplify dmtimer context-loss handling

Nishanth Menon (6):
      ARM: dts: OMAP34xx/35xx: Add CPU OPP table
      ARM: dts: OMAP36xx: Add CPU OPP table
      ARM: dts: OMAP3: use twl4030 vdd1 regulator for CPU
      ARM: dts: OMAP443x: Add CPU OPP table
      ARM: dts: omap4-panda: move generic sections to panda-common
      ARM: dts: OMAP4460: Add CPU OPP table

Olof Johansson (10):
      Merge branch 'omap/fixes-non-critical' into next/dt2
      Merge branch 'omap/usb' into next/dt2
      Merge tag 'omap-for-v3.10/dt-signed-v2' of git://git.kernel.org/.../tmlind/linux-omap into next/dt2
      Merge tag 'dt-exynos-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into next/dt2
      Merge tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux into next/dt2
      Merge tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/.../nsekhar/linux-davinci into next/dt2
      Merge branch 'samsung/pinctrl-exynos' into late/dt
      Merge branch 'exynos/dt' into late/dt
      ARM: exynos: dts: cros5250: add EC device
      Merge tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/.../kgene/linux-samsung into late/dt

Peter Ujfalusi (5):
      ARM: dts: twl4030: Add PWM support
      ARM: dts: twl6030: Add PWM support
      ARM: dts: omap3-beagle-xm: Use pwm-leds for pmu_stat LED
      ARM: dts: omap4-sdp: Add support for pwm-leds (keypad and charging LED)
      ARM: dts: omap4-sdp: Add support for pwm-backlight

Philip Avinash (2):
      ARM: dts: AM33XX: Corrects typo in interrupt field in SPI node
      ARM: davinci: da850: add EHRPWM & ECAP DT node

Prashant Gaikwad (1):
      clk: tegra: Fix cdev1 and cdev2 IDs

Pritesh Raithatha (2):
      ARM: tegra: add default pinctrl nodes for Dalmore
      ARM: tegra: add SDHCI nodes with common properties

Rajendra Nayak (1):
      ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Rhyland Klein (2):
      ARM: tegra: add SDHCI support for Dalmore
      ARM: tegra: Add sbs-battery node to Dalmore

Sachin Kamat (11):
      ARM: dts: Add G2D node to exynos4210.dtsi
      ARM: dts: Add G2D node to SMDKV310
      ARM: dts: Add G2D node to exynos4210-origen
      ARM: dts: Add G2D node to exynos4x12.dtsi
      ARM: dts: Add G2D node to SMDK4412
      ARM: dts: Add G2D node to exynos4412-origen
      ARM: dts: Add Samsung G2D DT bindings documentation
      ARM: dts: Add disable-wp for card slot on exynos5250-arndale
      ARM: dts: Add vmmc regulator support for Arndale board
      ARM: dts: Add MFC codec support for Arndale board
      ARM: dts: Add HDMI HPD and regulator node for Arndale board

Santosh Shilimkar (9):
      ARM: dts: omap5-evm: Update available memory to 2032 MB
      ARM: dts: OMAP5: Align the local timer dt node as per the current binding code
      ARM: dts: OMAP5: Move the gic node out of ocp space
      ARM: dts: OMAP5: Update the timer and GIC nodes for HYP kernel support
      ARM: dts: OMAP5: Update keypad reg property
      Documentation: dt: OMAP: l3-noc: Add *reg* in required properties
      ARM: dts: OMAP4/5: Update l3-noc DT nodes
      ARM: OMAP2+: hwmod: extract module address space from DT blob
      ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc

Sebastien Guiriec (1):
      ARM: dts: OMAP2+: Add SDMA Audio IPs bindings

Shawn Guo (16):
      net: fec: handle optional clk_ptp more gracefully
      ARM: mxs: remove unneeded enet_out clk initialization
      video: mxsfb: use devm_* managed functions
      video: mxsfb: remove fb_phys/fb_size from platform_data
      video: mxsfb: remove dotclk_delay from platform_data
      video: mxsfb: get display timings from device tree
      ARM: mxs: move display timing configurations into device tree
      video: mxsfb: remove mxsfb_platform_data
      ARM: dts: add generic DMA device tree binding for mxs-dma
      dma: mxs-dma: use devm_* managed functions
      dma: mxs-dma: move to generic device tree binding
      mmc: mxs-mmc: move to use generic DMA helper
      spi: mxs-spi: move to use generic DMA helper
      i2c: i2c-mxs: move to use generic DMA helper
      mtd: gpmi: move to use generic DMA helper
      serial: mxs-auart: move to use generic DMA helper

Sourav Poddar (4):
      ARM: dts: omap4-sdp: Add I2c pinctrl data
      ARM: dts: omap5-evm: Add I2c pinctrl data
      ARM: dts: omap4-panda: Add I2c pinctrl data
      ARM: dts: omap5-evm: Add mcspi data

Stephen Warren (5):
      ARM: tegra: device tree whitespace cleanup
      ARM: tegra: fix sort order of USB PHY nodes
      ARM: tegra: add clocks property to sound nodes
      ARM: tegra: add clocks property to AC'97 sound nodes
      ARM: tegra: keep power on to SD slot on Dalmore

Subash Patel (3):
      ARM: dts: add PMU support in exynos5440
      ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440
      ARM: dts: add PDMA0 changes for exynos5440

Sylwester Nawrocki (1):
      ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series

Thomas Abraham (7):
      ARM: dts: add pin state information in client nodes for Exynos4 platforms
      ARM: dts: add pin state information in client nodes for Exynos5 platforms
      ARM: dts: list the interrupts generated by pin-controller on Exynos5440
      ARM: dts: Fix gmac clock ids due to changes in Exynos5440
      ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
      ARM: dts: Add chip-id controller node on Exynos4/5 SoC
      ARM: dts: add mshc controller node for Exynos4x12 SoCs

Thomas Petazzoni (2):
      ARM: dts: mvebu: fix cpus section indentation
      ARM: dts: mvebu: move all peripherals inside soc

Tony Lindgren (1):
      Merge branch 'for_3.10/dts' of git://git.kernel.org/.../bcousson/linux-omap-dt into omap-for-v3.10/dt

Tushar Behera (2):
      ARM: dts: Add pin-control related changes for Arndale board
      ARM: dts: Add gpio-button entries for Arndale board

Vikas Sajjan (3):
      ARM: dts: Add FIMD node to exynos4
      ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts
      ARM: dts: Add FIMD DT binding Documentation

Wolfram Sang (2):
      net: freescale: fec: add support for optional enet_out clk
      ARM: dts: mxs: add enet_out clock to devicetree

 .../devicetree/bindings/arm/omap/l3-noc.txt        |   1 +
 .../devicetree/bindings/arm/omap/timer.txt         |  17 +-
 .../devicetree/bindings/arm/samsung/sysreg.txt     |   7 +
 .../devicetree/bindings/dma/fsl-mxs-dma.txt        |  49 +-
 Documentation/devicetree/bindings/fb/mxsfb.txt     |  36 +-
 .../devicetree/bindings/gpio/gpio-omap.txt         |   8 +-
 .../devicetree/bindings/gpu/samsung-g2d.txt        |  20 +
 Documentation/devicetree/bindings/i2c/i2c-mxs.txt  |  12 +-
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  60 ++
 Documentation/devicetree/bindings/mmc/mxs-mmc.txt  |  12 +-
 .../devicetree/bindings/mtd/gpmi-nand.txt          |  17 +-
 .../bindings/pinctrl/fsl,mxs-pinctrl.txt           |   4 +
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |   8 +
 .../sound/nvidia,tegra-audio-trimslice.txt         |   7 +
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |   8 +
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |   8 +
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |   8 +
 Documentation/devicetree/bindings/spi/mxs-spi.txt  |  12 +-
 .../devicetree/bindings/spi/spi-davinci.txt        |  51 ++
 .../bindings/tty/serial/fsl-mxs-auart.txt          |  16 +-
 .../devicetree/bindings/usb/exynos-usb.txt         |  10 +
 Documentation/devicetree/bindings/usb/omap-usb.txt |   1 +
 .../devicetree/bindings/video/samsung-fimd.txt     |  65 ++
 arch/arm/boot/dts/Makefile                         |   5 +
 arch/arm/boot/dts/am335x-bone.dts                  |  10 +-
 arch/arm/boot/dts/am335x-evm.dts                   |  18 +-
 arch/arm/boot/dts/am335x-evmsk.dts                 |  18 +-
 arch/arm/boot/dts/am33xx.dtsi                      |  40 +-
 arch/arm/boot/dts/am3517-evm.dts                   |   2 +-
 arch/arm/boot/dts/am3517_mt_ventoux.dts            |   2 +-
 arch/arm/boot/dts/armada-370-db.dts                | 134 ++--
 arch/arm/boot/dts/armada-370-mirabox.dts           | 176 ++--
 arch/arm/boot/dts/armada-370-rd.dts                |  96 +--
 arch/arm/boot/dts/armada-370-xp.dtsi               | 336 ++++----
 arch/arm/boot/dts/armada-370.dtsi                  | 330 ++++----
 arch/arm/boot/dts/armada-xp-db.dts                 | 202 ++---
 arch/arm/boot/dts/armada-xp-gp.dts                 | 222 ++---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           | 284 +++----
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           | 342 ++++----
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           | 484 +++++------
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   | 262 +++---
 arch/arm/boot/dts/armada-xp.dtsi                   | 202 ++---
 arch/arm/boot/dts/cros5250-common.dtsi             |  54 +-
 arch/arm/boot/dts/da850-evm.dts                    |  40 +
 arch/arm/boot/dts/da850.dtsi                       |  94 +++
 arch/arm/boot/dts/exynos4.dtsi                     |  32 +
 arch/arm/boot/dts/exynos4210-origen.dts            |   4 +
 arch/arm/boot/dts/exynos4210-smdkv310.dts          |  57 +-
 arch/arm/boot/dts/exynos4210.dtsi                  |   7 +
 arch/arm/boot/dts/exynos4412-origen.dts            |  21 +
 arch/arm/boot/dts/exynos4412-smdk4412.dts          |   8 +
 arch/arm/boot/dts/exynos4412.dtsi                  |   8 +
 arch/arm/boot/dts/exynos4x12.dtsi                  |   7 +
 arch/arm/boot/dts/exynos5250-arndale.dts           | 343 +++++++-
 arch/arm/boot/dts/exynos5250-pinctrl.dtsi          | 783 ++++++++++++++++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |  49 +-
 arch/arm/boot/dts/exynos5250-snow.dts              | 149 +++-
 arch/arm/boot/dts/exynos5250.dtsi                  | 348 +++-----
 arch/arm/boot/dts/exynos5440-sd5v1.dts             |  39 +
 arch/arm/boot/dts/exynos5440-ssdk5440.dts          |   6 +-
 arch/arm/boot/dts/exynos5440.dtsi                  |  55 +-
 arch/arm/boot/dts/imx23-evk.dts                    |  36 +-
 arch/arm/boot/dts/imx23-olinuxino.dts              |   1 +
 arch/arm/boot/dts/imx23.dtsi                       |  42 +-
 arch/arm/boot/dts/imx28-apf28dev.dts               |  25 +
 arch/arm/boot/dts/imx28-apx4devkit.dts             |  25 +
 arch/arm/boot/dts/imx28-cfa10049.dts               |  50 +-
 arch/arm/boot/dts/imx28-evk.dts                    |  36 +-
 arch/arm/boot/dts/imx28-m28evk.dts                 |  27 +
 arch/arm/boot/dts/imx28.dtsi                       |  62 +-
 arch/arm/boot/dts/imx6qdl.dtsi                     |   8 +-
 arch/arm/boot/dts/omap2.dtsi                       |  39 +-
 arch/arm/boot/dts/omap2420-h4.dts                  |  46 ++
 arch/arm/boot/dts/omap2420.dtsi                    |  67 +-
 arch/arm/boot/dts/omap2430.dtsi                    |  87 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts              |  26 +-
 arch/arm/boot/dts/omap3-beagle.dts                 |   8 +-
 arch/arm/boot/dts/omap3-devkit8000.dts             | 169 ++++
 arch/arm/boot/dts/omap3-evm.dts                    |  14 +-
 arch/arm/boot/dts/omap3-igep.dtsi                  | 122 +++
 arch/arm/boot/dts/omap3-igep0020.dts               |  56 ++
 arch/arm/boot/dts/omap3-igep0030.dts               |  44 +
 arch/arm/boot/dts/omap3-overo.dtsi                 |  31 +-
 arch/arm/boot/dts/omap3.dtsi                       | 142 +++-
 arch/arm/boot/dts/omap3430-sdp.dts                 | 190 +++++
 arch/arm/boot/dts/omap34xx.dtsi                    |  28 +
 arch/arm/boot/dts/omap36xx.dtsi                    |  13 +
 arch/arm/boot/dts/omap4-panda-a4.dts               |   5 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi          | 251 ++++++
 arch/arm/boot/dts/omap4-panda-es.dts               |   5 +-
 arch/arm/boot/dts/omap4-panda.dts                  | 201 +----
 arch/arm/boot/dts/omap4-sdp.dts                    |  74 +-
 arch/arm/boot/dts/omap4-var-som.dts                |   2 +-
 arch/arm/boot/dts/omap4.dtsi                       | 135 +++-
 arch/arm/boot/dts/omap443x.dtsi                    |  27 +
 arch/arm/boot/dts/omap4460.dtsi                    |  32 +
 arch/arm/boot/dts/omap5-evm.dts                    | 110 ++-
 arch/arm/boot/dts/omap5.dtsi                       | 245 +++++-
 arch/arm/boot/dts/tegra114-dalmore.dts             | 891 +++++++++++++++++++++
 arch/arm/boot/dts/tegra114.dtsi                    | 240 +++++-
 arch/arm/boot/dts/tegra20-colibri-512.dtsi         |  12 +
 arch/arm/boot/dts/tegra20-harmony.dts              |  20 +
 arch/arm/boot/dts/tegra20-medcom-wide.dts          |   7 +
 arch/arm/boot/dts/tegra20-paz00.dts                |  10 +
 arch/arm/boot/dts/tegra20-plutux.dts               |   3 +
 arch/arm/boot/dts/tegra20-seaboard.dts             |  11 +
 arch/arm/boot/dts/tegra20-tamonten.dtsi            |   6 +
 arch/arm/boot/dts/tegra20-tec.dts                  |   3 +
 arch/arm/boot/dts/tegra20-trimslice.dts            |  23 +
 arch/arm/boot/dts/tegra20-ventana.dts              |  22 +
 arch/arm/boot/dts/tegra20-whistler.dts             |  13 +
 arch/arm/boot/dts/tegra20.dtsi                     |  53 +-
 arch/arm/boot/dts/tegra30-beaver.dts               |   8 +
 arch/arm/boot/dts/tegra30-cardhu-a02.dts           |   1 +
 arch/arm/boot/dts/tegra30-cardhu-a04.dts           |   1 +
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |  11 +
 arch/arm/boot/dts/tegra30.dtsi                     |   1 +
 arch/arm/boot/dts/twl4030.dtsi                     |  18 +-
 arch/arm/boot/dts/twl6030.dtsi                     |  12 +
 arch/arm/mach-davinci/da8xx-dt.c                   |   6 +
 arch/arm/mach-exynos/common.c                      |  53 +-
 arch/arm/mach-exynos/include/mach/map.h            |   1 -
 arch/arm/mach-mxs/mach-mxs.c                       | 170 ----
 arch/arm/mach-omap2/board-generic.c                |   1 +
 arch/arm/mach-omap2/omap_hwmod.c                   |  48 +-
 arch/arm/mach-omap2/pmu.c                          |  14 +-
 arch/arm/mach-omap2/timer.c                        |   7 +-
 arch/arm/plat-omap/dmtimer.c                       | 241 +++---
 arch/arm/plat-omap/include/plat/dmtimer.h          |   1 +
 drivers/dma/mxs-dma.c                              | 109 ++-
 drivers/i2c/busses/i2c-mxs.c                       |  40 +-
 drivers/mmc/host/mxs-mmc.c                         |  48 +-
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c             |  51 +-
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h             |   3 +-
 drivers/net/ethernet/freescale/fec.h               |   1 +
 drivers/net/ethernet/freescale/fec_main.c          |  18 +-
 drivers/spi/spi-davinci.c                          |   4 +-
 drivers/spi/spi-mxs.c                              |  60 +-
 drivers/tty/serial/mxs-auart.c                     |  52 +-
 drivers/video/Kconfig                              |   2 +
 drivers/video/mxsfb.c                              | 260 +++---
 include/linux/mxsfb.h                              |  52 --
 include/linux/spi/mxs-spi.h                        |   4 +-
 143 files changed, 7751 insertions(+), 3048 deletions(-)


From arnd at arndb.de  Tue May  7 13:26:14 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 19:26:14 +0200
Subject: [GIT PULL 5/5] ARM: arm-soc: late Exynos multiplatform changes
In-Reply-To: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
Message-ID: <1367947574-2934383-6-git-send-email-arnd@arndb.de>

These continue the multiplatform support for exynos, adding support
for building most of the essential drivers (clocksource, clk, irqchip)
when combined with other platforms. As a result, it should become
really easy to add full multiplatform exynos support in 3.11, although
we don't yet enable it for 3.10.

The changes were not included in the earlier multiplatform series
in order to avoid clashes with the other Exynos updates.

This also includes work from Tomasz Figa to fix the pwm clocksource
code on Exynos, which is not strictly required for multiplatform,
but related to the other patches in this set and needed as a bug
fix for at least one board.

Conflicts:
- in arch/arm/mach-exynos/common.c, the irq_set_wake callback
  gets added, while a call to s5p_init_irq() gets removed and
  the prototype for combiner_init changes.


-------------------------------------------------------------

The following changes since commit

   e8b1270 Merge tag 'cleanup-for-linus-2' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/multiplatform-for-linus-2

you to fetch changes up to

   241a987 Merge branch 'exynos/pwm-clocksource' into late/multiplatform


-------------------------------------------------------------

Arnd Bergmann (12):
      clk: exynos: prepare for multiplatform
      clocksource: exynos_mct: remove platform header dependency
      ARM: exynos: add missing properties for combiner IRQs
      irqchip: exynos: pass max combiner number to combiner_init
      irqchip: exynos: allocate combiner_data dynamically
      irqchip: exynos: localize irq lookup for ATAGS
      irqchip: exynos: pass irq_base from platform
      irqchip: exynos: look up irq using irq_find_mapping
      Merge branch 'next/drivers' into late/multiplatform
      Merge branch 'samsung/exynos-multiplatform-drivers' into late/multiplatform
      Merge branch 'exynos/pwm-clocksource' into late/multiplatform
      Merge tag 'multiplatform-for-linus-2' into for-next

Olof Johansson (1):
      ARM: dts: exynops4210: really add universal_c210 dts

Tomasz Figa (13):
      clocksource: add samsung pwm timer driver
      Documentation: Add device tree bindings for Samsung PWM timers
      clocksource: samsung_pwm_timer: Let platforms select the driver
      clocksource: samsung_pwm_timer: Make PWM spinlock global
      clocksource: samsung_pwm_timer: Keep all driver data in a structure
      clocksource: samsung_pwm_timer: Drop unused samsung_pwm struct
      clocksource: samsung_pwm_timer: Add support for non-DT platforms
      clocksource: samsung_pwm_timer: Use proper clockevents max_delta
      clocksource: samsung_pwm_timer: Correct programming of clock events
      clocksource: samsung_pwm_timer: Work around rounding errors in clockevents core
      ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos
      ARM: dts: exynos4: Add node for PWM device
      ARM: dts: exynos4210: Add basic dts file for universal_c210 board

 .../devicetree/bindings/pwm/pwm-samsung.txt        |  43 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/exynos4.dtsi                     |   8 +
 arch/arm/boot/dts/exynos4210-universal_c210.dts    | 352 +++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi                  |   1 +
 arch/arm/boot/dts/exynos4212.dtsi                  |   9 +
 arch/arm/boot/dts/exynos4412.dtsi                  |   9 +
 arch/arm/mach-exynos/common.c                      |  35 +-
 arch/arm/mach-exynos/common.h                      |   7 +-
 arch/arm/plat-samsung/Kconfig                      |   4 +-
 drivers/clk/samsung/clk-exynos4.c                  |  93 ++--
 drivers/clk/samsung/clk-exynos5250.c               |   1 -
 drivers/clk/samsung/clk-exynos5440.c               |   1 -
 drivers/clk/samsung/clk.h                          |   2 -
 drivers/clocksource/Kconfig                        |   9 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/exynos_mct.c                   |  21 +-
 drivers/clocksource/samsung_pwm_timer.c            | 494 +++++++++++++++++++++
 drivers/irqchip/exynos-combiner.c                  | 125 +++---
 include/clocksource/samsung_pwm.h                  |  36 ++
 20 files changed, 1098 insertions(+), 154 deletions(-)


From arnd at arndb.de  Tue May  7 13:26:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue,  7 May 2013 19:26:13 +0200
Subject: [GIT PULL 4/5] ARM: arm-soc: late cleanups
In-Reply-To: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
Message-ID: <1367947574-2934383-5-git-send-email-arnd@arndb.de>

These are cleanups and smaller changes that either depend on earlier
feature branches or came in late during the development cycle.
We normally try to get all cleanups early, so these are the exceptions:

- A follow-up on the clocksource reworks, hopefully the last time
  we need to merge clocksource subsystem changes through arm-soc.
  A first set of patches was part of the original 3.10 arm-soc cleanup
  series because of interdependencies with timer drivers now moved out
  of arch/arm.

- Migrating the SPEAr13xx platform away from using auxdata for DMA
  channel descriptions towards using information in device tree,
  based on the earlier SPEAr multiplatform series

- A few follow-ups on the Atmel SAMA5 support and other changes
  for Atmel at91 based on the larger at91 reworks.

- Moving the armada irqchip implementation to drivers/irqchip

- Several OMAP cleanups following up on the larger series already
  merged in 3.10.

There are a few more conflicts that we would like now:

Simple conflicts between unrelated add or del hunks:
- arch/arm/Kconfig
- arch/arm/mach-mvebu/Makefile
- arch/arm/mach-mvebu/armada-370-xp.c
- arch/arm/mach-spear/spear13xx.c
- drivers/irqchip/Makefile

And non-obvious ones:
- remove/modify conflict in arch/arm/mach-exynos/mach-exynos5-dt.c:
  keep the modified line
- multiple changes to arch/arm/mach-vexpress/v2m.c:
  keep of_clk_init(NULL), clocksource_of_init() and
  versatile_sched_clock_init() calls


-------------------------------------------------------------

The following changes since commit

   763e6b9 Merge tag 'dt-for-linus-2' into for-next

are available in the git repository at

   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/cleanup-for-linus-2

you to fetch changes up to

   0592c21 Merge tag 'omap-for-v3.10/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/cleanup


-------------------------------------------------------------

Archit Taneja (13):
      arm: omap: board-2430: use generic dpi panel's gpio handling
      arm: omap: board-devkit8000: use generic dpi panel's gpio handling
      arm: omap: board-am3517: use generic dpi panel's gpio handling
      arm: omap: board-ldp: use generic dpi panel's gpio handling
      arm: omap: board-overo: use lb035q02 dpi panel's gpio handling
      arm: omap: board-omap3evm: use sharp panel's gpio handling
      arm: omap: board-sdp3430: use sharp panel's gpio handling
      arm: omap: board-rx-51: use acx565akm panel's gpio handling
      arm: omap: board-zoom: use NEC panel's gpio handling
      arm: omap: board-omap3pandora: use tpo panel's gpio handling
      arm: omap: dss-common: use picodlp panel's gpio handling
      arm: omap boards: Remove unnecessary platform_enable/disable callbacks for VENC devices
      arm: dss-common: don't use reset_gpio from omap4_panda_dvi_device

Arnd Bergmann (16):
      spi: pl022: use generic DMA slave configuration if possible
      serial: pl011: use generic DMA slave configuration if possible
      Merge branch 'spear/multiplatform' into spear/dma
      ARM: SPEAr13xx: Pass generic DW DMAC platform data from DT
      ARM: make machine_desc->init_time default to clocksource_of_init
      ARM: at91: suspend both memory controllers on at91sam9263
      ata: arasan: remove the need for platform_data
      Merge branch 'spear/multiplatform' into late/cleanup
      Merge branch 'spear/dwdma' into late/cleanup
      serial: amba-pl011: fix !CONFIG_DMA_ENGINE case
      ARM: OMAP: remove unused variable
      Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into late/cleanup
      ARM: SPEAr: conditionalize SMP code
      Merge branch 'late/clksrc' into late/cleanup
      Merge tag 'omap-for-v3.10/fixes-for-merge-window' of git://git.kernel.org/.../tmlind/linux-omap into late/cleanup
      Merge tag 'cleanup-for-linus-2' into for-next

Haojian Zhuang (1):
      devtree: add binding documentation for sp804

Kishon Vijay Abraham I (1):
      ARM: OMAP4: change the device names in usb_bind_phy

Ludovic Desroches (3):
      ARM: at91: dts: set #dma-cells to the correct value
      ARM: at91: dts: add i2c dma support
      ARM: at91: dts: add MCI DMA support

Nicolas Ferre (2):
      ARM: at91: change "Unknown" qualifier SoC subtype handling
      ARM: at91/sama5d34ek.dts: remove not needed compatibility string

Olof Johansson (7):
      Merge tag 'clksrc-cleanup-for-3.10-part2' of git://sources.calxeda.com/kernel/linux into late/clksrc
      Merge tag 'irqchip-3.10' of git://git.infradead.org/users/jcooper/linux into late/cleanup
      Merge branch 'omap/fixes-non-critical' into late/cleanup
      Merge branch 'omap/boards' into late/cleanup
      Merge tag 'omap-for-v3.10/dss-signed' of git://git.kernel.org/.../tmlind/linux-omap into late/cleanup
      Merge branch 'at91/soc' into late/cleanup
      Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into late/cleanup

Peter Ujfalusi (1):
      ARM: OMAP: zoom: Use pwm stack for lcd and keyboard backlight

Rob Herring (13):
      ARM: sched_clock: allow changing to higher frequency counter
      ARM: make sched_clock just call a function pointer
      ARM: arch_timer: use full 64-bit counter for sched_clock
      ARM: convert arm/arm64 arch timer to use CLKSRC_OF init
      OF: add empty of_device_is_available for !OF
      ARM: timer-sp: convert to use CLKSRC_OF init
      ARM: highbank: use OF init for sp804 timer
      ARM: vexpress: remove sp804 OF init
      ARM: dts: vexpress: disable CA9 core tile sp804 timer
      ARM: vexpress: remove extra timer-sp control register clearing
      ARM: versatile: add versatile dtbs to dtbs target
      ARM: versatile: use OF init for sp804 timer
      ARM: integrator-cp: convert use CLKSRC_OF for timer init

Stephen Boyd (1):
      ARM: arch_timer: Silence debug preempt warnings

Thomas Petazzoni (4):
      ARM: mvebu: move L2 cache initialization in init_early()
      irqchip: move IRQ driver for Armada 370/XP
      irqchip: armada-370-xp: move IRQ handler to avoid forward declaration
      irqchip: armada-370-xp: slightly cleanup irq controller driver

Tomi Valkeinen (1):
      arm: omap: board-cm-t35: use generic dpi panel's gpio handling

Tony Lindgren (1):
      Merge branch '3.10-lo/board-cleanup' of git://gitorious.org/linux-omap-dss2/linux into omap-for-v3.10/dss

Vaibhav Hiremath (1):
      ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a

 .../devicetree/bindings/arm/primecell.txt          |  19 ++-
 .../devicetree/bindings/ata/pata-arasan.txt        |  22 ++++
 Documentation/devicetree/bindings/serial/pl011.txt |  17 +++
 .../devicetree/bindings/spi/spi_pl022.txt          |  36 ++++++
 .../devicetree/bindings/timer/arm,sp804.txt        |  29 +++++
 arch/arm/Kconfig                                   |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   5 +
 arch/arm/boot/dts/at91sam9n12.dtsi                 |   9 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |  15 +++
 arch/arm/boot/dts/integratorcp.dts                 |   6 +-
 arch/arm/boot/dts/sama5d3.dtsi                     |  19 ++-
 arch/arm/boot/dts/sama5d34ek.dts                   |   2 +-
 arch/arm/boot/dts/spear1340.dtsi                   |   3 +
 arch/arm/boot/dts/spear13xx.dtsi                   |  25 +++-
 arch/arm/boot/dts/versatile-ab.dts                 |  12 ++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts             |   1 +
 arch/arm/common/timer-sp.c                         | 140 ++++++++++++++++++---
 arch/arm/include/asm/arch_timer.h                  |  13 +-
 arch/arm/include/asm/hardware/timer-sp.h           |  16 ++-
 arch/arm/include/asm/sched_clock.h                 |   2 +
 arch/arm/kernel/arch_timer.c                       |  29 ++---
 arch/arm/kernel/sched_clock.c                      |  15 ++-
 arch/arm/kernel/time.c                             |   7 +-
 arch/arm/mach-at91/cpuidle.c                       |   2 +
 arch/arm/mach-at91/include/mach/cpu.h              |   9 +-
 arch/arm/mach-at91/pm.c                            |   2 +
 arch/arm/mach-at91/pm.h                            |  30 ++++-
 arch/arm/mach-at91/setup.c                         |  22 ++--
 arch/arm/mach-highbank/highbank.c                  |  24 +---
 arch/arm/mach-integrator/integrator_cp.c           |  34 -----
 arch/arm/mach-mvebu/Makefile                       |   2 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |   9 +-
 arch/arm/mach-omap2/board-2430sdp.c                |  43 +------
 arch/arm/mach-omap2/board-3430sdp.c                |  53 +++-----
 arch/arm/mach-omap2/board-4430sdp.c                |   2 +-
 arch/arm/mach-omap2/board-am3517evm.c              |  74 +----------
 arch/arm/mach-omap2/board-cm-t35.c                 |  60 ++-------
 arch/arm/mach-omap2/board-devkit8000.c             |  27 +---
 arch/arm/mach-omap2/board-ldp.c                    |  61 ++-------
 arch/arm/mach-omap2/board-omap3evm.c               |  70 +++--------
 arch/arm/mach-omap2/board-omap3pandora.c           |   7 +-
 arch/arm/mach-omap2/board-omap3stalker.c           |  11 --
 arch/arm/mach-omap2/board-omap4panda.c             |   2 +-
 arch/arm/mach-omap2/board-overo.c                  |  58 +++------
 arch/arm/mach-omap2/board-rx51-video.c             |  26 ++--
 arch/arm/mach-omap2/board-zoom-display.c           |  38 ++----
 arch/arm/mach-omap2/dss-common.c                   |  54 +++-----
 arch/arm/mach-omap2/timer.c                        |   7 +-
 arch/arm/mach-shmobile/board-kzm9d.c               |   1 -
 arch/arm/mach-shmobile/setup-emev2.c               |   1 -
 arch/arm/mach-shmobile/setup-r8a7740.c             |   1 -
 arch/arm/mach-shmobile/setup-sh7372.c              |   1 -
 arch/arm/mach-shmobile/setup-sh73a0.c              |   1 -
 arch/arm/mach-shmobile/timer.c                     |   7 +-
 arch/arm/mach-spear/Makefile                       |   6 +-
 arch/arm/mach-spear/generic.h                      |   5 -
 arch/arm/mach-spear/include/mach/spear.h           |   2 -
 arch/arm/mach-spear/spear1310.c                    |  30 +----
 arch/arm/mach-spear/spear1340.c                    |  32 +----
 arch/arm/mach-spear/spear13xx-dma.h                | 128 -------------------
 arch/arm/mach-spear/spear13xx.c                    |  60 +--------
 arch/arm/mach-versatile/core.c                     |  26 ++--
 arch/arm/mach-versatile/versatile_dt.c             |   1 -
 arch/arm/mach-vexpress/v2m.c                       |  25 +---
 arch/arm/mach-virt/virt.c                          |   9 --
 arch/arm64/include/asm/arch_timer.h                |   5 +
 arch/arm64/kernel/time.c                           |   6 +-
 drivers/ata/pata_arasan_cf.c                       |  37 +++---
 drivers/clocksource/Kconfig                        |   1 +
 drivers/clocksource/arm_arch_timer.c               |  33 +++--
 drivers/clocksource/exynos_mct.c                   |   1 -
 drivers/irqchip/Makefile                           |   1 +
 .../irqchip}/irq-armada-370-xp.c                   | 106 ++++++++--------
 drivers/spi/spi-pl022.c                            |  43 ++++++-
 drivers/tty/serial/amba-pl011.c                    |  64 ++++++----
 include/clocksource/arm_arch_timer.h               |   6 -
 include/linux/of.h                                 |   5 +
 include/linux/pata_arasan_cf_data.h                |   2 -
 79 files changed, 777 insertions(+), 1041 deletions(-)


From linux at arm.linux.org.uk  Tue May  7 13:32:31 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 May 2013 18:32:31 +0100
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
In-Reply-To: <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
 <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>
Message-ID: <20130507173231.GL18614@n2100.arm.linux.org.uk>

On Tue, May 07, 2013 at 10:02:22AM -0700, Linus Torvalds wrote:
> So you seem to have blasted this series out with that automated
> script, so they all got sent basically at the same timestamp, and they
> are in the wrong order in my mailbox because email isn't that ordered.

Interesting.  What I received here from the mailing list from Arnd
was:

Date: Tue,  7 May 2013 18:02:09 +0200
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10

Date: Tue,  7 May 2013 18:02:10 +0200
Subject: [GIT PULL] ARM: arm-soc platform updates for 3.10, part 2

Date: Tue,  7 May 2013 18:02:11 +0200
Subject: [GIT PULL] ARM: arm-soc platform updates for 3.10, part 3

Date: Tue,  7 May 2013 18:02:12 +0200
Subject: [GIT PULL] ARM: arm-soc device tree changes, part 2

Date: Tue,  7 May 2013 18:02:13 +0200
Subject: [GIT PULL] ARM: arm-soc: late cleanups

Date: Tue,  7 May 2013 18:02:14 +0200
Subject: [GIT PULL] ARM: arm-soc: late Exynos multiplatform changes

So they do each have a different timestamp, and do come out right if
sorted by date-sent.  Maybe one second is not long enough for gmail to
sort by date-sent?  Sure, allowing a longer delay reduces the
possibility of stuff being reordered by MTAs, but it will never totally
eliminate that reordering - it just makes it less likely.

FWIR, gmail orders messages by order-of-reception only, not by
date-anything, which makes using delays to try to anticipate the
order of reception quite fruitless.  And I suspect gmail doesn't show
you seconds (let alone give you Date: header.)

So I don't think that asking people to play games with delays between
consecutive messages is going to work all that well.

The only sure way would be to have it clearly marked in the subject
line, maybe in a similar way to how we mark patches using a
[GIT PULL N/M] thing.


From arnd at arndb.de  Tue May  7 13:42:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 May 2013 19:42:12 +0200
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
In-Reply-To: <20130507173231.GL18614@n2100.arm.linux.org.uk>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
 <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>
 <20130507173231.GL18614@n2100.arm.linux.org.uk>
Message-ID: <201305071942.12709.arnd@arndb.de>

On Tuesday 07 May 2013, Russell King - ARM Linux wrote:
> On Tue, May 07, 2013 at 10:02:22AM -0700, Linus Torvalds wrote:
> > So you seem to have blasted this series out with that automated
> > script, so they all got sent basically at the same timestamp, and they
> > are in the wrong order in my mailbox because email isn't that ordered.
> 
> Interesting.  What I received here from the mailing list from Arnd
> was:
> 
> Date: Tue,  7 May 2013 18:02:09 +0200
> Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
> 
> Date: Tue,  7 May 2013 18:02:10 +0200
> Subject: [GIT PULL] ARM: arm-soc platform updates for 3.10, part 2
> 
> Date: Tue,  7 May 2013 18:02:11 +0200
> Subject: [GIT PULL] ARM: arm-soc platform updates for 3.10, part 3
> 
> Date: Tue,  7 May 2013 18:02:12 +0200
> Subject: [GIT PULL] ARM: arm-soc device tree changes, part 2
> 
> Date: Tue,  7 May 2013 18:02:13 +0200
> Subject: [GIT PULL] ARM: arm-soc: late cleanups
> 
> Date: Tue,  7 May 2013 18:02:14 +0200
> Subject: [GIT PULL] ARM: arm-soc: late Exynos multiplatform changes
> 
> So they do each have a different timestamp, and do come out right if
> sorted by date-sent.  Maybe one second is not long enough for gmail to
> sort by date-sent?  Sure, allowing a longer delay reduces the
> possibility of stuff being reordered by MTAs, but it will never totally
> eliminate that reordering - it just makes it less likely.

Interestingly, the second version (with sequence numbers) has exactly the
same seconds, but 19:26 instead of 18:02 as the hour:minute. There is
probably some intentional logic in there that fills in these numbers.
I'm sure I waited more than a couple of seconds between each email this
time around, where the first time I just sent them all without any delay.

> So I don't think that asking people to play games with delays between
> consecutive messages is going to work all that well.
> 
> The only sure way would be to have it clearly marked in the subject
> line, maybe in a similar way to how we mark patches using a
> [GIT PULL N/M] thing.

Yes, that is certainly the right way to do it. I'm also very relieved
that this time lists.infradead.org didn't reject all emails sent in
reply to the introductory mail, which it previously did based on the
ground that it had an "in-reply-to" header to a mail with a different
subject.

	Arnd


From torvalds at linux-foundation.org  Tue May  7 13:44:59 2013
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Tue, 7 May 2013 10:44:59 -0700
Subject: [GIT PULL] ARM: Third batch of arm-soc changes for 3.10
In-Reply-To: <20130507173231.GL18614@n2100.arm.linux.org.uk>
References: <1367942534-2934003-1-git-send-email-arnd@arndb.de>
 <CA+55aFwMXmJ9V+3o62ELm-0NT1DaUCTvidmAhJSXzQcTMfJygA@mail.gmail.com>
 <20130507173231.GL18614@n2100.arm.linux.org.uk>
Message-ID: <CA+55aFwW1TyWwJs1CQxnj08Qe-A+eFD20B4fVVT8Te=6eBcTqw@mail.gmail.com>

On Tue, May 7, 2013 at 10:32 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
>
> So I don't think that asking people to play games with delays between
> consecutive messages is going to work all that well.

Actually, since this has happened before (a lot) with patch series,
I'm pretty sure it helps.

I used to get re-ordered patches from Andrew all the time, and asked
him to try to avoid it (yes, he also numbers them well, but alpine -
which is what I used for batching email when there are lots of patches
- had this annoying habit of ignoring the "[PATCH n]" part when asked
to sort subject alphabetically). These days, he seems to put a delay
of a second between his patch-bombings these days, and that has almost
entirely solved the problem (so in a series of over a hundred, I
seldom get any renumbering at all, and fixing it up manually if it
happens is much easier now).

But yes, it probably depends very much on where things get sent from,
and in particular if you have some slow SMTP server in one of the
hops. So it's possible that the reason I don't see it with Andrew any
more is simply due to issues like that.

                  Linus


From torvalds at linux-foundation.org  Tue May  7 14:01:21 2013
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Tue, 7 May 2013 11:01:21 -0700
Subject: [GIT PULL 0/5] ARM: Third batch of arm-soc changes for 3.10, again
In-Reply-To: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
Message-ID: <CA+55aFxJB3OG+-tu2SqAOzn9T7zDb0P9jgbUOMHnXs9m_nXNUA@mail.gmail.com>

On Tue, May 7, 2013 at 10:26 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>
> Here are the same pull requests as before, with numbers and distinct
> time stamps. I hope I didn't screw up in a different way this time.

Ok, I notice that you seem to have forgotten the "--summary" flag from
your diffstat in your new script.

Not a showstopper, but make sure that the diffstat flags are

  "git diff -M --stat --summary"

(And yes, I prefer "-M", not "-C", because while copy information is
interesting, it tends to hide the fact that the copying added a lot of
lines, so the "-C" flag ends up not giving as good line add/del
information, even if the data that something looks like a copy of
another file is interesting).

              Linus


From jgunthorpe at obsidianresearch.com  Tue May  7 14:27:11 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Tue, 7 May 2013 12:27:11 -0600
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <5188FE54.6050200@ti.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
 <20130506223653.GA12089@obsidianresearch.com>
 <51884971.9050508@ti.com>
 <20130507003651.GA26035@obsidianresearch.com>
 <5188FE54.6050200@ti.com>
Message-ID: <20130507182711.GB28628@obsidianresearch.com>

On Tue, May 07, 2013 at 09:15:00AM -0400, Eduardo Valentin wrote:
> > But broadly the direction seems that drivers should have minimal
> > dependencies so, eg, the thermal maintainer compiling for x86 should
> > be able to compile test/static analyze your driver..

> Well, I do not see much of this attempt actually. Do you have some link
> / evidene that shows someone who actually cares about compiling drivers
> for targets that they are not used for? On this specific driver, I
> actually have  had exactly the opposite advice [1]. I am not convinced
> people actually want to do that.

There was a discussion a bit ago, but I can't find a link.. The
context was subsystem maintainers are being asked to look after more
code with the DT transition moving things out of arch/arm and at least
one complained they couldn't even compile test on x86... But again, I
can't find a link and you are right, there are lots and lots of
'depends ARCH..' style things in kConfig already.

Lets just call it something to think about.

> >> Thats the idea behind this config option. It follows the same design as
> >> CONFIG_ARCH_HAS_CPUFREQ, for instance.
> > 
> > That is entirely contained inside arch/arm and doesn't involve
> > drivers.
> 
> It actually goes outside arch/arm.

Hm, must have missed that, seemed like all it did was control
including drivers/cpufreq/Kconfig within the ARM kconfigs.. And
unicore32 copied the name, but did the same thing.

Regards,
Jason


From arnd at arndb.de  Tue May  7 14:41:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 May 2013 20:41:37 +0200
Subject: [GIT PULL 0/5] ARM: Third batch of arm-soc changes for 3.10, again
In-Reply-To: <CA+55aFxJB3OG+-tu2SqAOzn9T7zDb0P9jgbUOMHnXs9m_nXNUA@mail.gmail.com>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
 <CA+55aFxJB3OG+-tu2SqAOzn9T7zDb0P9jgbUOMHnXs9m_nXNUA@mail.gmail.com>
Message-ID: <201305072041.37493.arnd@arndb.de>

On Tuesday 07 May 2013, Linus Torvalds wrote:
> On Tue, May 7, 2013 at 10:26 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> >
> > Here are the same pull requests as before, with numbers and distinct
> > time stamps. I hope I didn't screw up in a different way this time.
> 
> Ok, I notice that you seem to have forgotten the "--summary" flag from
> your diffstat in your new script.
> 
> Not a showstopper, but make sure that the diffstat flags are
> 
>   "git diff -M --stat --summary"
> 
> (And yes, I prefer "-M", not "-C", because while copy information is
> interesting, it tends to hide the fact that the copying added a lot of
> lines, so the "-C" flag ends up not giving as good line add/del
> information, even if the data that something looks like a copy of
> another file is interesting).

Right, another thing that I actually knew and then forgot to do. Olof
has just sent me the script he used the past few times, I'll use that
in the future.

	Arnd


From aaro.koskinen at iki.fi  Tue May  7 15:06:28 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 7 May 2013 22:06:28 +0300
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <20130507182711.GB28628@obsidianresearch.com>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
 <20130506223653.GA12089@obsidianresearch.com>
 <51884971.9050508@ti.com>
 <20130507003651.GA26035@obsidianresearch.com>
 <5188FE54.6050200@ti.com>
 <20130507182711.GB28628@obsidianresearch.com>
Message-ID: <20130507190628.GI5634@blackmetal.musicnaut.iki.fi>

On Tue, May 07, 2013 at 12:27:11PM -0600, Jason Gunthorpe wrote:
> On Tue, May 07, 2013 at 09:15:00AM -0400, Eduardo Valentin wrote:
> > > But broadly the direction seems that drivers should have minimal
> > > dependencies so, eg, the thermal maintainer compiling for x86 should
> > > be able to compile test/static analyze your driver..
> 
> > Well, I do not see much of this attempt actually. Do you have some link
> > / evidene that shows someone who actually cares about compiling drivers
> > for targets that they are not used for? On this specific driver, I
> > actually have  had exactly the opposite advice [1]. I am not convinced
> > people actually want to do that.
> 
> There was a discussion a bit ago, but I can't find a link.. The
> context was subsystem maintainers are being asked to look after more
> code with the DT transition moving things out of arch/arm and at least
> one complained they couldn't even compile test on x86... But again, I
> can't find a link and you are right, there are lots and lots of
> 'depends ARCH..' style things in kConfig already.
> 
> Lets just call it something to think about.

Tomi started a thread related to this recently:

	http://marc.info/?l=linux-kernel&m=136731558332265&w=2

I think there's some good reasons listed there, but I guess up to the
subsystem maintainers to decide what they prefer.

A.


From sergei.shtylyov at cogentembedded.com  Tue May  7 15:46:29 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Tue, 07 May 2013 23:46:29 +0400
Subject: [PATCH v6 3/3] ARM: shmobile: BOCK-W: add USB support
In-Reply-To: <201305010314.32153.sergei.shtylyov@cogentembedded.com>
References: <201305010309.07744.sergei.shtylyov@cogentembedded.com>
 <201305010314.32153.sergei.shtylyov@cogentembedded.com>
Message-ID: <51895A15.4090006@cogentembedded.com>

Hello.

On 05/01/2013 03:14 AM, Sergei Shtylyov wrote:

> Register the USB PHY device from bockw_init(), passing the platform  data to it.
> Set machine's init_late() method to r8a7778_init_late() in order for [EO]HCI to
> get registered too...
>
> The patch has been tested on the BOCK-W board.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

    Oops, the patch misses the USB pin setup. The USB pin groups in the 
sh-pfc
driver have also not been created. This needs to be addressed in the 
next iteration...

WBR, Sergei



From plagnioj at jcrosoft.com  Tue May  7 16:06:57 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue,  7 May 2013 22:06:57 +0200
Subject: [PATCH 1/1] ARM: at91: at91sam9x25ek: fix model name
Message-ID: <1367957217-3678-1-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9x25ek.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index 8ddbce0..4948648 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -11,7 +11,7 @@
 #include "at91sam9x5ek.dtsi"
 
 / {
-	model = "Atmel AT91SAM9G25-EK";
+	model = "Atmel AT91SAM9X25-EK";
 	compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 
 	ahb {
-- 
1.7.10.4



From pavel at denx.de  Tue May  7 16:11:26 2013
From: pavel at denx.de (Pavel Machek)
Date: Tue, 7 May 2013 22:11:26 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <51892E5E.8090909@linaro.org>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de>
 <20130506155304.GA6645@amd.pavel.ucw.cz>
 <201305062324.17080.arnd@arndb.de>
 <20130507135752.GA3500@amd.pavel.ucw.cz>
 <51892E5E.8090909@linaro.org>
Message-ID: <20130507201126.GA8169@amd.pavel.ucw.cz>

Hi!

> >>>So I guess it should go through the timekeeping tree...?
> >>I would prefer that, but we can also take it through arm-soc, it doesn't
> >>really matter.
> >I see no response from timekeeping people... so if you could take it,
> >that would be great.
> 
> I don't think the original patch ever made it to my inbox.

For some reason, I cced johnstul at us.ibm.com. (I guess
get_maintainer.pl? But it seems to behave now.) Anyway, patch is
below...

It would be great if you could apply it... Thanks,
							Pavel

----

It seems we made a mistake when creating dw_apb_timer_of.c:
picoxcell sched_clock had parts that were not related to
dw_apb_timer, yet we moved them to dw_apb_timer_of, and tried to
use them on socfpga.

This results in system where user/system time is not measured
properly, as demonstrated by
    
    time dd if=/dev/urandom of=/dev/zero bs=100000 count=100
    
So this patch switches sched_clock to hardware that exists on both
platforms, and adds missing of_node_put() in dw_apb_timer_init().
    
Signed-off-by: Pavel Machek <pavel at denx.de>
Acked-by: Jamie Iles <jamie at jamieiles.com>

diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
index 481b42a..237fb3b 100644
--- a/arch/arm/mach-picoxcell/common.h
+++ b/arch/arm/mach-picoxcell/common.h
@@ -12,6 +12,4 @@
 
 #include <asm/mach/time.h>
 
-extern void dw_apb_timer_init(void);
-
 #endif /* __PICOXCELL_COMMON_H__ */
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index 8c2a35f..460ac99 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -21,12 +21,6 @@
 #define APBT_MIN_PERIOD			4
 #define APBT_MIN_DELTA_USEC		200
 
-#define APBTMR_N_LOAD_COUNT		0x00
-#define APBTMR_N_CURRENT_VALUE		0x04
-#define APBTMR_N_CONTROL		0x08
-#define APBTMR_N_EOI			0x0c
-#define APBTMR_N_INT_STATUS		0x10
-
 #define APBTMRS_INT_STATUS		0xa0
 #define APBTMRS_EOI			0xa4
 #define APBTMRS_RAW_INT_STATUS		0xa8
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index ab09ed3..0fa3104 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -57,6 +57,15 @@ static void add_clockevent(struct device_node *event_timer)
 	dw_apb_clockevent_register(ced);
 }
 
+static void __iomem *sched_io_base;
+
+/* This is actually same as __apbt_read_clocksource(), but with
+   different interface */
+static u32 read_sched_clock_sptimer(void)
+{
+	return ~__raw_readl(sched_io_base + APBTMR_N_CURRENT_VALUE);
+}
+
 static void add_clocksource(struct device_node *source_timer)
 {
 	void __iomem *iobase;
@@ -71,41 +80,27 @@ static void add_clocksource(struct device_node *source_timer)
 
 	dw_apb_clocksource_start(cs);
 	dw_apb_clocksource_register(cs);
-}
 
-static void __iomem *sched_io_base;
-
-static u32 read_sched_clock(void)
-{
-	return __raw_readl(sched_io_base);
+	sched_io_base = iobase;
+	setup_sched_clock(read_sched_clock_sptimer, 32, rate);
 }
 
-static const struct of_device_id sptimer_ids[] __initconst = {
-	{ .compatible = "picochip,pc3x2-rtc" },
+static const struct of_device_id osctimer_ids[] __initconst = {
+	{ .compatible = "picochip,pc3x2-timer" },
+	{ .compatible = "snps,dw-apb-timer-osc" },
 	{ .compatible = "snps,dw-apb-timer-sp" },
-	{ /* Sentinel */ },
+	{  /* Sentinel */ },
 };
 
-static void init_sched_clock(void)
-{
-	struct device_node *sched_timer;
-	u32 rate;
-
-	sched_timer = of_find_matching_node(NULL, sptimer_ids);
-	if (!sched_timer)
-		panic("No RTC for sched clock to use");
+/*
+   You don't have to use dw_apb_timer for scheduler clock,
+   this should also work fine on arm:
 
-	timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
-	of_node_put(sched_timer);
+  twd_local_timer_of_register();
+  arch_timer_of_register();                 
+  arch_timer_sched_clock_init();
+*/
 
-	setup_sched_clock(read_sched_clock, 32, rate);
-}
-
-static const struct of_device_id osctimer_ids[] __initconst = {
-	{ .compatible = "picochip,pc3x2-timer" },
-	{ .compatible = "snps,dw-apb-timer-osc" },
-	{},
-};
 
 void __init dw_apb_timer_init(void)
 {
@@ -121,7 +116,6 @@ void __init dw_apb_timer_init(void)
 		panic("No timer for clocksource");
 	add_clocksource(source_timer);
 
+	of_node_put(event_timer);
 	of_node_put(source_timer);
-
-	init_sched_clock();
 }
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index dd755ce..a64c987 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -17,6 +17,12 @@
 #include <linux/clocksource.h>
 #include <linux/interrupt.h>
 
+#define APBTMR_N_LOAD_COUNT		0x00
+#define APBTMR_N_CURRENT_VALUE		0x04
+#define APBTMR_N_CONTROL		0x08
+#define APBTMR_N_EOI			0x0c
+#define APBTMR_N_INT_STATUS		0x10
+
 #define APBTMRS_REG_SIZE       0x14
 
 struct dw_apb_timer {


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html



From pavel at denx.de  Tue May  7 16:13:39 2013
From: pavel at denx.de (Pavel Machek)
Date: Tue, 7 May 2013 22:13:39 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <51892E5E.8090909@linaro.org>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de>
 <20130506155304.GA6645@amd.pavel.ucw.cz>
 <201305062324.17080.arnd@arndb.de>
 <20130507135752.GA3500@amd.pavel.ucw.cz>
 <51892E5E.8090909@linaro.org>
Message-ID: <20130507201339.GB8169@amd.pavel.ucw.cz>

Hi!

> >>>So I guess it should go through the timekeeping tree...?
> >>I would prefer that, but we can also take it through arm-soc, it doesn't
> >>really matter.
> >I see no response from timekeeping people... so if you could take it,
> >that would be great.
> 
> I don't think the original patch ever made it to my inbox.

Aha, so for 3.8, 

pavel at amd:/data/l/linux-n900$ scripts/get_maintainer.pl -f
drivers/clocksource/dw_apb_timer.c
John Stultz <johnstul at us.ibm.com> (supporter:TIMEKEEPING, NTP)
Thomas Gleixner <tglx at linutronix.de> (supporter:TIMEKEEPING, NTP)
linux-kernel at vger.kernel.org (open list)

for 3.9, it works ok.

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From ohaugan at codeaurora.org  Tue May  7 16:26:02 2013
From: ohaugan at codeaurora.org (Olav Haugan)
Date: Tue, 07 May 2013 13:26:02 -0700
Subject: [PATCH] documentation: iommu: add description of ARM System MMU
 binding
In-Reply-To: <20130424095501.GC21850@mudshark.cambridge.arm.com>
References: <1365094259-24847-1-git-send-email-will.deacon@arm.com>
 <515F37C1.4000109@codeaurora.org>
 <20130408092535.GA17476@mudshark.cambridge.arm.com>
 <5162F87A.7070409@codeaurora.org>
 <20130410173732.GQ26992@mudshark.cambridge.arm.com>
 <5169C7D1.8070300@codeaurora.org>
 <20130415131341.GG9827@mudshark.cambridge.arm.com>
 <516D9602.2010404@codeaurora.org>
 <20130418190131.GA12344@mudshark.cambridge.arm.com>
 <5177113D.7060300@codeaurora.org>
 <20130424095501.GC21850@mudshark.cambridge.arm.com>
Message-ID: <5189635A.8090504@codeaurora.org>

Hi Will,

On 4/24/2013 2:55 AM, Will Deacon wrote:
> On Tue, Apr 23, 2013 at 11:54:53PM +0100, Olav Haugan wrote:
>> On 4/18/2013 12:01 PM, Will Deacon wrote:
> Getting phandles has no dependencies on anything -- the only dependency is
> that the device is added to the bus on which the SMMU sits, just like every
> other IOMMU driver.
> 
>>> Why would a page table shared between devices require multiple context
>>> banks? Multiple SMRs and S2CRs, sure, but they would ultimately point at the
>>> same context bank (and hence same address space).
>>
>> What if you want to have 2 different VMID's being generated? Also, what
>> about TLB management? If I have two context banks I can invalidate only
>> entries associated with 1 of the context banks (if VMID differ for the
>> two context banks).
> 
> Huh? We allocate one VMID per domain. If you want more VMIDs, use more
> domains. TLB invalidation is per-domain, so there's no issue there.

If we allocate a new domain you would have another address space (page
table), no? I was just trying to figure out if your binding proposal
would allow for 2 context banks in one domain which it does not seem to
support.

>>> If a master needs to be in two address spaces at once, then it will need to
>>> attach it's StreamIDs to different domains. You can't place a single
>>> StreamID in two address spaces (this is an architectural constraint).
>>
>> Yes, you would have a separate domain. I am just wondering how I would
>> model this in DT using the bindings that you are proposing? How does it
>> work? The bindings specify bus masters to StreamIDs. So if I call attach
>> with the master device you will allocate a context bank and program the
>> StreamIDs as specified in the DT. So now if I want to have another
>> context bank associated with the same master device what do I do? I call
>> into attach with a new domain but with the same master device but the
>> master device is already attached to a context/domain.
> 
> Why would you want to place a StreamID into two domains? That doesn't make
> any sense and isn't even supported by the architecture (things like
> conflicting SMR entries may not even be reported).

I think you misunderstood me. I am talking about having for example 1
master with two (2) context banks so that StreamID "1" goes to CB0 and
StreamID "2" goes to CB1. This means that the master device is attached
to two different domains. How do I model this with the the device tree
bindings?



Olav Haugan

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From nerv at dawncrow.de  Tue May  7 16:51:00 2013
From: nerv at dawncrow.de (=?ISO-8859-15?Q?Andr=E9_Hentschel?=)
Date: Tue, 07 May 2013 22:51:00 +0200
Subject: [PATCHv3] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
Message-ID: <51896934.5080803@dawncrow.de>

From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>

Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
prevent it from being used as a covert channel between two tasks.

There are more and more applications coming to WinRT, Wine could support them,
but mostly they expect to have the thread environment block (TEB) in TPIDRURW.

This patch preserves that register per thread instead of clearing it.
Unlike the TPIDRURO, which is already switched, the TPIDRURW
can be updated from userspace so needs careful treatment in the case that we
modify TPIDRURW and call fork(). To avoid this we must always read
TPIDRURW in copy_thread.

Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com> 

---
This patch is against a86d52667d8eda5de39393ce737794403bdce1eb

I could only test it with kernel 3.4.6, beside using Wine for testing i also
used https://github.com/AndreRH/tpidrurw-test

Why so much Signed-off-bys? Some History:
The first patch had performance issues pointed out by Russel King,
so Will Deacon jumped in to help me with that. The second one again
had performance issues and the missing copy_thread part was uncovered.
After some iterations by me, Jonathan Austin proposed a patch and
Russel King sent his idea of the assembler part. All this was finally
merged and refined into this patch.
Thanks to everyone!

 arch/arm/include/asm/thread_info.h |    2 +-
 arch/arm/include/asm/tls.h         |   41 ++++++++++++++++++++++++++++-------------
 arch/arm/kernel/entry-armv.S       |    4 ++--
 arch/arm/kernel/process.c          |    4 +++-
 arch/arm/kernel/ptrace.c           |    2 +-
 arch/arm/kernel/traps.c            |    4 ++--
 6 files changed, 37 insertions(+), 20 deletions(-)



diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f..d90be6d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];	/* TLS registers */
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..22756ab 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-	.macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
 	.endm
 
-	.macro set_tls_v6k, tp, tmp1, tmp2
+	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
 	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_v6, tp, tmp1, tmp2
+	.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
 	ldr	\tmp1, =elf_hwcap
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
 	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	mcrne	p15, 0, \tpuser, c13, c0, 2	@ set user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_software, tp, tmp1, tmp2
+	.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
 	mov	\tmp1, #0xffff0fff
 	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
@@ -31,19 +34,31 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
-#define set_tls		set_tls_none
+#define switch_tls	switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
-#define set_tls		set_tls_v6
+#define switch_tls	switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
-#define set_tls		set_tls_v6k
+#define switch_tls	switch_tls_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
-#define set_tls		set_tls_software
+#define switch_tls	switch_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tlsuser(void)
+{
+	if (has_tls_reg && !tls_emu)
+	{
+		unsigned long t;
+		__asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (t));
+		return t;
+	}
+	return 0;
+}
+#endif
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..80f09fe 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,15 +728,15 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
+	ldrd	r4, r5, [r2, #TI_TP_VALUE]
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-	set_tls	r3, r4, r5
+	switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
 	ldr	r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e4..24dbc72 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -395,7 +396,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+		thread->tp_value[0] = childregs->ARM_r3;
+	thread->tp_value[1] = get_tlsuser();
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c08911..f9d6259 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }


From mturquette at linaro.org  Tue May  7 16:59:53 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 07 May 2013 13:59:53 -0700
Subject: [PATCH] clk: Always notify whole subtree when reparenting
In-Reply-To: <afe397e3-c674-4dc3-9f3e-feea9275bb91@TX2EHSMHS023.ehs.local>
References: <afe397e3-c674-4dc3-9f3e-feea9275bb91@TX2EHSMHS023.ehs.local>
Message-ID: <20130507205953.4542.62609@quantum>

Quoting Soren Brinkmann (2013-04-16 10:06:50)
> A clock's notifier count only reflects notifiers which are registered
> directly for that clock. A reparent operation though affects the whole
> subtree because of a potential rate change.
> When issuing the pre rate change notifications only the notifier count
> for the clock to be changed is considered and notifiers for subclocks
> may never be called. Resulting in clocks in the subtree which have
> registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE
> notification, without a PRE_RATE_CHANGE_NOTIFICATION.
> Therefore always traverse the whole subtree when issueing pre rate
> change notifications during a reparent operation.
> 
> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> ---
> This should probably be considered an RFC. There may be smarter ways to
> resolve this issue. E.g. forward notifier counts upstream the way it is done
> with enable counts.
> 

I've taken this patch for 3.11.

Thanks,
Mike

>         S?ren
> 
> 
>  drivers/clk/clk.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 20ce67f..1179cb5 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1481,8 +1481,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
>         }
>  
>         /* propagate PRE_RATE_CHANGE notifications */
> -       if (clk->notifier_count)
> -               ret = __clk_speculate_rates(clk, p_rate);
> +       ret = __clk_speculate_rates(clk, p_rate);
>  
>         /* abort if a driver objects */
>         if (ret & NOTIFY_STOP_MASK)
> -- 
> 1.8.2.1


From soren.brinkmann at xilinx.com  Tue May  7 17:08:57 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Tue, 7 May 2013 14:08:57 -0700
Subject: [PATCH] clk: Always notify whole subtree when reparenting
In-Reply-To: <20130507205953.4542.62609@quantum>
References: <afe397e3-c674-4dc3-9f3e-feea9275bb91@TX2EHSMHS023.ehs.local>
 <20130507205953.4542.62609@quantum>
Message-ID: <4ee1b52e-8c1d-4161-9034-62fc6c48fd12@CO9EHSMHS026.ehs.local>

On Tue, May 07, 2013 at 01:59:53PM -0700, Mike Turquette wrote:
> Quoting Soren Brinkmann (2013-04-16 10:06:50)
> > A clock's notifier count only reflects notifiers which are registered
> > directly for that clock. A reparent operation though affects the whole
> > subtree because of a potential rate change.
> > When issuing the pre rate change notifications only the notifier count
> > for the clock to be changed is considered and notifiers for subclocks
> > may never be called. Resulting in clocks in the subtree which have
> > registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE
> > notification, without a PRE_RATE_CHANGE_NOTIFICATION.
> > Therefore always traverse the whole subtree when issueing pre rate
> > change notifications during a reparent operation.
> > 
> > Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> > ---
> > This should probably be considered an RFC. There may be smarter ways to
> > resolve this issue. E.g. forward notifier counts upstream the way it is done
> > with enable counts.
> > 
> 
> I've taken this patch for 3.11.
thank you.

	S?ren




From gregory.clement at free-electrons.com  Tue May  7 17:27:48 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 07 May 2013 23:27:48 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51892E87.5020903@itooo.com>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
 <51892E87.5020903@itooo.com>
Message-ID: <518971D4.5000603@free-electrons.com>

Hi Greg,

On 05/07/2013 06:40 PM, Greg wrote:
> Le 07/05/2013 18:18, Thomas Petazzoni a ?crit :
>> Dear Greg,
>>
>> On Tue, 07 May 2013 16:14:01 +0200, Greg wrote:
>>
>>> I'm trying to boot off the the backport-3.-8 kernel with armada-xp-db DT
>>> file.
>>>
>>> When eth0 is brought up (I'm booting on NFS) the mvneta driver fails in
>>> mvneta_open, with the following error :
>>>> mvneta d0070000.ethernet eth0: cannot request irq 25
>>> The oddness is this is not the actual IRQ to be requested, and the DTS
>>> files explicitly specify the IRQ is 8 for this device.
>>>
>>> I'm not familiar with the DT system, where should I start looking to
>>> find the source of the problem ?
>> This issue should be fixed by:
>>
>> commit 7f23f62fc31c5c97947414c0937a72e08a947a41
>> Author: Gregory CLEMENT <gregory.clement at free-electrons.com>
>> Date:   Wed Mar 20 16:09:35 2013 +0100
>>
>>      arm: mvebu: Use local interrupt only for the timer 0
>>      
>>      The commit 3a6f08a37 "arm: mvebu: Add support for local interrupt",
>>      managed the 28th first interrupts as local interrupt to match the
>>      hardware specification. Among these interrupts there are the Gigabits
>>      Ethernet ones used by the mvneta driver. Unfortunately the state of
>>      the percpu_irq API prevents the driver to use it.
>>      
>>      Indeed the interrupts have to be freed when the .stop() function is
>>      called. As the free_percpu_irq() function don't disable the interrupt
>>      line, we have to do it on each CPU before calling this. The function
>>      disable_percpu_irq() only disable the percpu on the current CPU and
>>      there is no function which allows to disable a percpu irq on a given
>>      CPU. Waiting for the extension of the percpu_irq API, this fix allows
>>      to use again the mvneta driver.
>>      
>>      Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
>>      Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>>      Tested-by: Masami Hiramatsu <masami.hiramatsu.pt at hitachi.com>
>>      Signed-off-by: Jason Cooper <jason at lakedaemon.net>
>>
>> which is part of the backport-3.8 branch, so I'm a bit confused. Are
>> you sure you're using the latest backport-3.8 branch? If so, then I'll
>> do a test here to check this.
>>
> By the way, the patch IS applied to the source tree I'm compiling.
> I can see this in arch/arm/mach-mvebu/irq-armada-370-xp.c which is using 
> ARMADA_370_XP_TIMER0_PER_CPU_IRQ instead of ARMADA_370_XP_MAX_PER_CPU_IRQS

I built and tested backport-3.8 and indeed the Ethernet is broken.
It was cause by a recent batch of fixes that I added, now I have to
figure out why they have broken the ethernet whereas they were supposed
to make it work better!

Regards,

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From akpm at linux-foundation.org  Tue May  7 17:33:38 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Tue, 7 May 2013 14:33:38 -0700
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <1956593.M6NmITdEKh@avalon>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <201304300004.20320.arnd@arndb.de> <5182AF83.4080705@wwwdotorg.org>
 <1956593.M6NmITdEKh@avalon>
Message-ID: <20130507143338.79b3d893fcdc3bd79fbe9a57@linux-foundation.org>


We don't seem to have a well-defined path to travel here, and I don't
get the feeling that anyone has signed up to walk it?

So I'm inclined to merge Stephen's patch as-is into 3.10.  It's pretty
simple and standalone.  Any strenuous objections?

BTW, Olof told me off-list that this patch is a "critical piece" for
running mainline Linux on ARM Chromebooks.  That was important
information - more important than anything else we were told about this
patch!

So Stephen, could I please have a new changelog for this patch which
explains this application, and any other interesting/important things
which were left out?  Quickly, please.




From: Stephen Warren <swarren at wwwdotorg.org>
Subject: drivers/video: implement a simple framebuffer driver

A simple frame-buffer describes a raw memory region that may be rendered
to, with the assumption that the display hardware has already been set up
to scan out from that buffer.

This is useful in cases where a bootloader exists and has set up the
display hardware, but a Linux driver doesn't yet exist for the display
hardware.

[akpm at linux-foundation.org: make simplefb_formats[] static]
Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Cc: Rob Clark <robclark at gmail.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
Cc: Tomasz Figa <tomasz.figa at gmail.com>
Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Andrew Morton <akpm at linux-foundation.org>
---

 Documentation/devicetree/bindings/video/simple-framebuffer.txt |   25 +
 drivers/video/Kconfig                                          |   17 
 drivers/video/Makefile                                         |    1 
 drivers/video/simplefb.c                                       |  234 ++++++++++
 4 files changed, 277 insertions(+)

diff -puN /dev/null Documentation/devicetree/bindings/video/simple-framebuffer.txt
--- /dev/null
+++ a/Documentation/devicetree/bindings/video/simple-framebuffer.txt
@@ -0,0 +1,25 @@
+Simple Framebuffer
+
+A simple frame-buffer describes a raw memory region that may be rendered to,
+with the assumption that the display hardware has already been set up to scan
+out from that buffer.
+
+Required properties:
+- compatible: "simple-framebuffer"
+- reg: Should contain the location and size of the framebuffer memory.
+- width: The width of the framebuffer in pixels.
+- height: The height of the framebuffer in pixels.
+- stride: The number of bytes in each line of the framebuffer.
+- format: The format of the framebuffer surface. Valid values are:
+  - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b).
+
+Example:
+
+	framebuffer {
+		compatible = "simple-framebuffer";
+		reg = <0x1d385000 (1600 * 1200 * 2)>;
+		width = <1600>;
+		height = <1200>;
+		stride = <(1600 * 2)>;
+		format = "r5g6b5";
+	};
diff -puN drivers/video/Kconfig~drivers-video-implement-a-simple-framebuffer-driver drivers/video/Kconfig
--- a/drivers/video/Kconfig~drivers-video-implement-a-simple-framebuffer-driver
+++ a/drivers/video/Kconfig
@@ -2453,6 +2453,23 @@ config FB_HYPERV
 	help
 	  This framebuffer driver supports Microsoft Hyper-V Synthetic Video.
 
+config FB_SIMPLE
+	bool "Simple framebuffer support"
+	depends on (FB = y) && OF
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	help
+	  Say Y if you want support for a simple frame-buffer.
+
+	  This driver assumes that the display hardware has been initialized
+	  before the kernel boots, and the kernel will simply render to the
+	  pre-allocated frame buffer surface.
+
+	  Configuration re: surface address, size, and format must be provided
+	  through device tree, or potentially plain old platform data in the
+	  future.
+
 source "drivers/video/omap/Kconfig"
 source "drivers/video/omap2/Kconfig"
 source "drivers/video/exynos/Kconfig"
diff -puN drivers/video/Makefile~drivers-video-implement-a-simple-framebuffer-driver drivers/video/Makefile
--- a/drivers/video/Makefile~drivers-video-implement-a-simple-framebuffer-driver
+++ a/drivers/video/Makefile
@@ -166,6 +166,7 @@ obj-$(CONFIG_FB_MX3)		  += mx3fb.o
 obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
 obj-$(CONFIG_FB_MXS)		  += mxsfb.o
 obj-$(CONFIG_FB_SSD1307)	  += ssd1307fb.o
+obj-$(CONFIG_FB_SIMPLE)           += simplefb.o
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff -puN /dev/null drivers/video/simplefb.c
--- /dev/null
+++ a/drivers/video/simplefb.c
@@ -0,0 +1,234 @@
+/*
+ * Simplest possible simple frame-buffer driver, as a platform device
+ *
+ * Copyright (c) 2013, Stephen Warren
+ *
+ * Based on q40fb.c, which was:
+ * Copyright (C) 2001 Richard Zidlicky <rz at linux-m68k.org>
+ *
+ * Also based on offb.c, which was:
+ * Copyright (C) 1997 Geert Uytterhoeven
+ * Copyright (C) 1996 Paul Mackerras
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+static struct fb_fix_screeninfo simplefb_fix = {
+	.id		= "simple",
+	.type		= FB_TYPE_PACKED_PIXELS,
+	.visual		= FB_VISUAL_TRUECOLOR,
+	.accel		= FB_ACCEL_NONE,
+};
+
+static struct fb_var_screeninfo simplefb_var = {
+	.height		= -1,
+	.width		= -1,
+	.activate	= FB_ACTIVATE_NOW,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
+static int simplefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+			      u_int transp, struct fb_info *info)
+{
+	u32 *pal = info->pseudo_palette;
+	u32 cr = red >> (16 - info->var.red.length);
+	u32 cg = green >> (16 - info->var.green.length);
+	u32 cb = blue >> (16 - info->var.blue.length);
+	u32 value;
+
+	if (regno >= 16)
+		return -EINVAL;
+
+	value = (cr << info->var.red.offset) |
+		(cg << info->var.green.offset) |
+		(cb << info->var.blue.offset);
+	if (info->var.transp.length > 0) {
+		u32 mask = (1 << info->var.transp.length) - 1;
+		mask <<= info->var.transp.offset;
+		value |= mask;
+	}
+	pal[regno] = value;
+
+	return 0;
+}
+
+static struct fb_ops simplefb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_setcolreg	= simplefb_setcolreg,
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+};
+
+struct simplefb_format {
+	const char *name;
+	u32 bits_per_pixel;
+	struct fb_bitfield red;
+	struct fb_bitfield green;
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;
+};
+
+static struct simplefb_format simplefb_formats[] = {
+	{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0} },
+};
+
+struct simplefb_params {
+	u32 width;
+	u32 height;
+	u32 stride;
+	struct simplefb_format *format;
+};
+
+static int simplefb_parse_dt(struct platform_device *pdev,
+			   struct simplefb_params *params)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+	const char *format;
+	int i;
+
+	ret = of_property_read_u32(np, "width", &params->width);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't parse width property\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "height", &params->height);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't parse height property\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "stride", &params->stride);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't parse stride property\n");
+		return ret;
+	}
+
+	ret = of_property_read_string(np, "format", &format);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't parse format property\n");
+		return ret;
+	}
+	params->format = NULL;
+	for (i = 0; i < ARRAY_SIZE(simplefb_formats); i++) {
+		if (strcmp(format, simplefb_formats[i].name))
+			continue;
+		params->format = &simplefb_formats[i];
+		break;
+	}
+	if (!params->format) {
+		dev_err(&pdev->dev, "Invalid format value\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int simplefb_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct simplefb_params params;
+	struct fb_info *info;
+	struct resource *mem;
+
+	if (fb_get_options("simplefb", NULL))
+		return -ENODEV;
+
+	ret = simplefb_parse_dt(pdev, &params);
+	if (ret)
+		return ret;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "No memory resource\n");
+		return -EINVAL;
+	}
+
+	info = framebuffer_alloc(sizeof(u32) * 16, &pdev->dev);
+	if (!info)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, info);
+
+	info->fix = simplefb_fix;
+	info->fix.smem_start = mem->start;
+	info->fix.smem_len = resource_size(mem);
+	info->fix.line_length = params.stride;
+
+	info->var = simplefb_var;
+	info->var.xres = params.width;
+	info->var.yres = params.height;
+	info->var.xres_virtual = params.width;
+	info->var.yres_virtual = params.height;
+	info->var.bits_per_pixel = params.format->bits_per_pixel;
+	info->var.red = params.format->red;
+	info->var.green = params.format->green;
+	info->var.blue = params.format->blue;
+	info->var.transp = params.format->transp;
+
+	info->fbops = &simplefb_ops;
+	info->flags = FBINFO_DEFAULT;
+	info->screen_base = devm_ioremap(&pdev->dev, info->fix.smem_start,
+					 info->fix.smem_len);
+	if (!info->screen_base) {
+		framebuffer_release(info);
+		return -ENODEV;
+	}
+	info->pseudo_palette = (void *)(info + 1);
+
+	ret = register_framebuffer(info);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Unable to register simplefb: %d\n", ret);
+		framebuffer_release(info);
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "fb%d: simplefb registered!\n", info->node);
+
+	return 0;
+}
+
+static int simplefb_remove(struct platform_device *pdev)
+{
+	struct fb_info *info = platform_get_drvdata(pdev);
+
+	unregister_framebuffer(info);
+	framebuffer_release(info);
+
+	return 0;
+}
+
+static const struct of_device_id simplefb_of_match[] = {
+	{ .compatible = "simple-framebuffer", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, simplefb_of_match);
+
+static struct platform_driver simplefb_driver = {
+	.driver = {
+		.name = "simple-framebuffer",
+		.owner = THIS_MODULE,
+		.of_match_table = simplefb_of_match,
+	},
+	.probe = simplefb_probe,
+	.remove = simplefb_remove,
+};
+module_platform_driver(simplefb_driver);
+
+MODULE_AUTHOR("Stephen Warren <swarren at wwwdotorg.org>");
+MODULE_DESCRIPTION("Simple framebuffer driver");
+MODULE_LICENSE("GPL v2");
_



From w at 1wt.eu  Tue May  7 17:35:24 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Tue, 7 May 2013 23:35:24 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51892E87.5020903@itooo.com>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
 <51892E87.5020903@itooo.com>
Message-ID: <20130507213524.GB5414@1wt.eu>

Hi Greg,

On Tue, May 07, 2013 at 06:40:39PM +0200, Greg wrote:
> Le 07/05/2013 18:18, Thomas Petazzoni a ?crit :
> >Dear Greg,
> >
> >On Tue, 07 May 2013 16:14:01 +0200, Greg wrote:
> >
> >>I'm trying to boot off the the backport-3.-8 kernel with armada-xp-db DT
> >>file.
> >>
> >>When eth0 is brought up (I'm booting on NFS) the mvneta driver fails in
> >>mvneta_open, with the following error :
> >>>mvneta d0070000.ethernet eth0: cannot request irq 25
> >>The oddness is this is not the actual IRQ to be requested, and the DTS
> >>files explicitly specify the IRQ is 8 for this device.
> >>
> >>I'm not familiar with the DT system, where should I start looking to
> >>find the source of the problem ?
> >This issue should be fixed by:
> >
> >commit 7f23f62fc31c5c97947414c0937a72e08a947a41
> >Author: Gregory CLEMENT <gregory.clement at free-electrons.com>
> >Date:   Wed Mar 20 16:09:35 2013 +0100
> >
> >     arm: mvebu: Use local interrupt only for the timer 0
> >     
> >     The commit 3a6f08a37 "arm: mvebu: Add support for local interrupt",
> >     managed the 28th first interrupts as local interrupt to match the
> >     hardware specification. Among these interrupts there are the Gigabits
> >     Ethernet ones used by the mvneta driver. Unfortunately the state of
> >     the percpu_irq API prevents the driver to use it.
> >     
> >     Indeed the interrupts have to be freed when the .stop() function is
> >     called. As the free_percpu_irq() function don't disable the interrupt
> >     line, we have to do it on each CPU before calling this. The function
> >     disable_percpu_irq() only disable the percpu on the current CPU and
> >     there is no function which allows to disable a percpu irq on a given
> >     CPU. Waiting for the extension of the percpu_irq API, this fix allows
> >     to use again the mvneta driver.
> >     
> >     Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> >     Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> >     Tested-by: Masami Hiramatsu <masami.hiramatsu.pt at hitachi.com>
> >     Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> >
> >which is part of the backport-3.8 branch, so I'm a bit confused. Are
> >you sure you're using the latest backport-3.8 branch? If so, then I'll
> >do a test here to check this.
> >
> By the way, the patch IS applied to the source tree I'm compiling.
> I can see this in arch/arm/mach-mvebu/irq-armada-370-xp.c which is using 
> ARMADA_370_XP_TIMER0_PER_CPU_IRQ instead of ARMADA_370_XP_MAX_PER_CPU_IRQS

On my OpenBlocks AX3, I'm not experiencing this issue. However it runs
a slightly different kernel, it's 3.9 in which I have merged most of
the patches you find in backport-3.8.

One thing I don't know yet is if the bootloader installed on this box
is DT compatible or not, since I always append the DT to the end of my
kernels :

  cat arch/arm/boot/zImage arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dtb > zImage.dtb

Do you know if yours is compatible ? Did you append a DTB file to your
kernel ?

BTW, we have more or less similar hardware. My CPU is a 78260 and I have
4 ports, like you, so I suspect we should have the same IRQs. The original
kernel says the board is a "DB-78460-BP rev 2.0", just in case it can help,
but I suspect that your board is probably based on a similar design.

I'm seeing something odd though : when booting with the Marvell-patched
kernel provided with the AX3, here are my IRQs :

           CPU0       CPU1       
  8:          1          1   axp_irq  mv_eth
 10:          0          0   axp_irq  mv_eth
 31:          0          0   axp_irq  mv64xxx_i2c
 32:      14193          0   axp_irq  mv64xxx_i2c
 41:        182          0   axp_irq  serial
 45:          0          0   axp_irq  ehci_hcd:usb1
 46:          0          0   axp_irq  ehci_hcd:usb2
 47:          0          0   axp_irq  ehci_hcd:usb3
 55:        317          1   axp_irq  sata_mv
107:          0          0   axp_irq  axp-temp

But when booting on 3.9+patches from the Free-Electrons' team,
I have different IRQs :

           CPU0       CPU1       
 16:        348        321  armada_370_xp_irq  armada_370_xp_per_cpu_tick
 17:        198          0  armada_370_xp_irq  serial
 24:          1          0  armada_370_xp_irq  sata_mv
 25:          0          0  armada_370_xp_irq  mvneta
 27:          0          0  armada_370_xp_irq  mv64xxx_i2c
 28:         85          0  armada_370_xp_irq  mv64xxx_i2c
 30:          0          0  armada_370_xp_irq  ehci_hcd:usb1
 31:          0          0  armada_370_xp_irq  ehci_hcd:usb2
110:          2          0  armada_370_xp_irq  d0060900.xor
111:          2          0  armada_370_xp_irq  d0060900.xor
112:          2          0  armada_370_xp_irq  d00f0900.xor
113:          2          0  armada_370_xp_irq  d00f0900.xor

And precisely your failing IRQ is 25 (as I'm having here) and you said
you saw IRQ 8 somewhere. So probably something got remapped or not
completely remapped (I don't know).

Are you interested in trying my kernel+initrd ? They're easy to boot
over tftp.

Willy



From khilman at linaro.org  Tue May  7 17:39:25 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue,  7 May 2013 14:39:25 -0700
Subject: [PATCH] ARM: OMAP2+: omap_device: use late_initcall_sync
Message-ID: <1367962765-13912-1-git-send-email-khilman@linaro.org>

If DEBUG_LL and earlyprintk are enabled, and omap-serial.c is compiled
as a module, the kernel boot hangs early as the clocks for serial port
are cut while earlyprintk still uses the port.

The problem is a race between the late_initcall for omap_device (which
idles devices that have no drivers) and the late_initcall in
kernel/printk.c which turns off the earlyconsole.   Any printks
that happen between this omap_device late initcall and the earlyconsole
late initcall will crash when accessing the UART.

The fix is to ensure the omap_device initcall happens after the
earlyconsole initcall.

Reported-by: Tony Lindgren <tony at atomide.com>
Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
Based on v3.9-rc8

 arch/arm/mach-omap2/omap_device.c | 2 +-
 arch/arm/mach-omap2/soc.h         | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 381be7a..2d20d69 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -879,4 +879,4 @@ static int __init omap_device_late_init(void)
 	bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
 	return 0;
 }
-omap_late_initcall(omap_device_late_init);
+omap_late_initcall_sync(omap_device_late_init);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index c62116b..de88611 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -494,6 +494,7 @@ level(__##fn);
 #define omap_subsys_initcall(fn)	omap_initcall(subsys_initcall, fn)
 #define omap_device_initcall(fn)	omap_initcall(device_initcall, fn)
 #define omap_late_initcall(fn)		omap_initcall(late_initcall, fn)
+#define omap_late_initcall_sync(fn)	omap_initcall(late_initcall_sync, fn)
 
 #endif	/* __ASSEMBLY__ */
 
-- 
1.8.2



From robherring2 at gmail.com  Tue May  7 17:42:07 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 07 May 2013 16:42:07 -0500
Subject: [PATCH, RFC 03/22] cpuidle: calxeda: select ARM_CPU_SUSPEND
In-Reply-To: <1367507786-505303-4-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-4-git-send-email-arnd@arndb.de>
Message-ID: <5189752F.8030405@gmail.com>

On 05/02/2013 10:16 AM, Arnd Bergmann wrote:
> Like other ARM specific drivers, this one requires ARM_CPU_SUSPEND,
> as shown by this linker error:
> 
> drivers/built-in.o: In function `calxeda_pwrdown_idle':
> drivers/cpuidle/cpuidle-calxeda.c:84: undefined reference to `cpu_suspend'
> drivers/cpuidle/cpuidle-calxeda.c:86: undefined reference to `cpu_resume'
> 
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
> Cc: linux-pm at vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Rob Herring <rob.herring at calxeda.com>

> ---
>  drivers/cpuidle/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> index c4cc27e..e21cdfa 100644
> --- a/drivers/cpuidle/Kconfig
> +++ b/drivers/cpuidle/Kconfig
> @@ -36,6 +36,7 @@ if CPU_IDLE
>  config CPU_IDLE_CALXEDA
>  	bool "CPU Idle Driver for Calxeda processors"
>  	depends on ARCH_HIGHBANK
> +	select ARM_CPU_SUSPEND
>  	help
>  	  Select this to enable cpuidle on Calxeda processors.
>  
> 



From w at 1wt.eu  Tue May  7 17:42:56 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Tue, 7 May 2013 23:42:56 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <518971D4.5000603@free-electrons.com>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
 <51892E87.5020903@itooo.com> <518971D4.5000603@free-electrons.com>
Message-ID: <20130507214256.GC5414@1wt.eu>

Hi Gr?gory,

On Tue, May 07, 2013 at 11:27:48PM +0200, Gregory CLEMENT wrote:
> I built and tested backport-3.8 and indeed the Ethernet is broken.
> It was cause by a recent batch of fixes that I added, now I have to
> figure out why they have broken the ethernet whereas they were supposed
> to make it work better!

If that can help you, here is the list of (possibly relevant) patches
I have applied on top of 3.9 picked from your repository some time
ago (it's not up to date with the latest versions due to merge issues
inducing laziness on my side) :

$ git log --oneline --grep=free-electrons v3.9.. 
65d2b5c ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
26cabde ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
34b32e8 ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
31504c0 ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
8cc752e drivers: memory: Introduce Marvell EBU Device Bus driver
48c6ddc arm: mvebu: update defconfig with PCI and USB support
f4ed5ba arm: mvebu: PCIe Device Tree informations for Armada XP GP
b1ed2c5 arm: mvebu: PCIe Device Tree informations for Armada 370 DB
51e91a9 arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
402f9ba arm: mvebu: PCIe Device Tree informations for Armada XP DB
4899409 arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
fb6d69f arm: mvebu: add PCIe Device Tree informations for Armada XP
c523287 arm: mvebu: add PCIe Device Tree informations for Armada 370
998ee7a arm: mvebu: PCIe support is now available on mvebu
fc9b219 pci: PCIe driver for Marvell Armada 370/XP systems
4b765fb clk: mvebu: add more PCIe clocks for Armada XP
af3bcd9 clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
6cee09e arm: pci: add a align_resource hook
80fa698 pci: infrastructure to add drivers in drivers/pci/host
91ca5a7 of/pci: Provide support for parsing PCI DT ranges property
e46b3e7 arm: plat-orion: remove addr-map code
d11befe arm: mach-mv78xx0: convert to use the mvebu-mbus driver
a508a65 arm: mach-orion5x: convert to use mvebu-mbus driver
e249639 arm: mach-dove: convert to use mvebu-mbus driver
70efe5e arm: mach-kirkwood: convert to use mvebu-mbus driver
37e82515 arm: mach-mvebu: convert to use mvebu-mbus driver
035f910 bus: introduce an Marvell EBU MBus driver
527d658 arm: mach-orion5x: use mv_mbus_dram_info() in PCI code
c1b44db arm: plat-orion: use mv_mbus_dram_info() in PCIe code
59463f4 arm: plat-orion: only build addr-map.c when needed

With those my AX3 works fine. If that can help, I can send them all to
you off-list, in case you notice a minor difference with something.

Regards,
Willy



From s-anna at ti.com  Tue May  7 17:48:41 2013
From: s-anna at ti.com (Suman Anna)
Date: Tue, 7 May 2013 16:48:41 -0500
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
Message-ID: <518976B9.2030605@ti.com>

Hi Jassi,

> On 7 May 2013 05:15, Suman Anna <s-anna at ti.com> wrote:
>>>
>>>  The client(s) can always generate TX requests at a rate greater than
>>> the API could transmit on the physical link. So as much as we dislike
>>> it, we have to buffer TX requests, otherwise N clients would.
>>
>> The current code doesn't support N clients today anyway, and if they are
>> blocking mode on top of it, it would never need Tx buffering.
>>
> No, I meant if the API doesn't buffer TX requests, then N client
> drivers that simply need to send 2 or more messages would have to
> buffer them locally.
>  Also by buffering TX requests the API reduces TX latency by
> submitting the next request atomically as soon as it knows the last TX
> is done.

OK. I do not have an issue with Tx buffering, but the manner it is done.
As I said before, there is a big implementation detail on client users
keeping their pointers in tact until the actual Tx is done - it
increases the complexity of client code. I have proposed an idea below
on the size discussion.

>>>
>>> IMHO if clients on OMAP need to buffer RX, let us keep it OMAP
>>> specific. If number of such platforms rise in future we could move
>>> that as an _optional_ helper API on top, that does RX buffering on
>>> behalf of clients ?
>>
>> Yeah, that's my idea as well to put this in the OMAP mailbox controller
>> driver implementation. The IPC stacks on OMAP are quite established
>> (both in remoteproc and DSP/Bridge - different generations), so I cannot
>> afford to break the functionality of either of those. This already means
>> I have to export some API from my controller driver and there is no
>> other way or now.
>>
> Yes, I anticipated that.
> Though imho OMAP's mailbox client/controller drivers could have be better.
>  The controller has 8 instances of identical mailboxes/links which
> operate independent of each other. It is the s/w implementation that
> has tacit understanding of who sends/receives on which link. So
> ideally a client driver should simply, say for omap3430, ask for
> separate "mbox1" to read messages and "mbox0" to send messages to DSP.

I think this is a good example for link_ops specified with the link,
rather than the controller (send_data would be NULL on the Rx instance
for example). In anycase, there is not much to be bought implementing
this way on OMAP (maybe sometime in the far future if we assign receive
queues by processor, rather than defining the pair as a communication
link with some message decoding indicating tx processor), since our
remotes are processors and the link assignment configuration doesn't
change dynamically.

>  The unnecessary logical coupling of 0th and 1st links seems to be the
> cause of 'hacks' like mailbox_dis/enable_irq(), whereas it should have
> been release/request of the RX mbox.

The logical coupling is not the reason, but that's because of the IPC
protocol stack implementation in DSP/Bridge, that's a story for another
day. remoteproc does not suffer from this.

> Also logically coupling the independent physical links makes the
> controller driver not very portable - what if some other platform has
> usage of 3 send+receive and 2 send-only communications of the 8
> physical links? The controller h/w is perfectly capable of providing
> that, but its driver is not.

That's upto that controller driver, right?

>   Similarly something sure seems fishy about the client driver having
> to explicitly save and restore registers of controller. Anyways, OMAP'
> implementation of mailbox is a separate subject.

Yeah, not too concerned here, the save/restore part can be fixed rather
easily. I will look into that once we get the series and the initial
migration done.

>>>>
>>>  If the API provides shared ownership of a mailbox, it won't work for
>>> clients that need exclusive ownership (like 'server' side
>>> implementation of a protocol).
>>>  OTOH if the API provides exclusive ownership, it is still possible to
>>> emulate shared ownership by simply publishing the mailbox handle (void
>>> *chan) globally. It works for all.
>>
>> I am not saying provide this always. Have this dictated by the
>> controller or mailbox (look at my branch). The global publication works
>> well functionality-wise for Tx, but not so much for Rx.
>>
> Right now for RX the clients register a blocking notifier call within
> the API, you could move that out into the same code that publishes the
> TX handlle globally.  I am a bit hesitant because I want to make sure
> we don't push anything into the common API that isn't already done
> right in OMAP's implementation.
> 
>> In anycase,
>> global publication will have its own set of problems - mostly you are
>> implying another layer of implementation that provides this sharing
>> capability (since they have to be outside of any single client).
>>
> Yes. Though yet another way of doing it is for the controller driver
> to populate N logical per physical link that needs to be shared.

Yeah, I was implying the same idea.. The notifier chains in the current
driver really meant the logical and physical is the same as we are
returning the link handle, but with your current design of returning
ipc_chan as an opaque handle, you already have the base infrastructure
in place. Once we add tx callbacks, even the original mailbox series
would have transformed into having a similar concept as what you have.

> 
> BTW, there doesn't exist any code/dt that creates the "omap-rproc"
> platform_device so I may have misunderstood, but it seems the OMAP
> already acquires a mailbox only once and save it in the data structure
> representing the remote, which should simply work as such. No?

Yeah, the rproc device creation code is currently out of tree (you can
find it in Ohad's remoteproc tree on git.kernel.org), it is currently
disabled due to the lack of multi-platform support in mailbox
(dependencies on this series and other DT conversions). The runtime
support would have relinquished the mailboxes. remoteproc already looks
in certain messages for device management, and others it passes onto the
rpmsg bus, but that is rather tightly coupled.

> 
> 
>>>>
>>> Most of the clients won't queue more than 1 request at a time. And
>>> then, isn't it only natural that clients don't mess with requests
>>> after submitting them ?  I see mailbox clients working quite like I2C
>>> clients.
>>
>> The OMAP use-cases do this today, so not a good assumption to make. The
>> OMAP IPC is built upon simple transmitting and processing received
>> messages separately, we will not be using blocking mode or tx callbacks.
>> I really don't need the complexity of having to introduce tx callbacks
>> just because I need to know if my pointer can be freed, as I said - it
>> eliminates the simplicity of using local variables unless the send API
>> is blocking. void * works for OMAP since my payloads are only 4 bytes by
>> themselves (this is a discussion that came up during the earlier series
>> as well), but this is not flexible enough on the clients-side generally.
>>
> The OMAP simply pass by value a u32 as a message.  Why do you think it
> won't work ? (Please have a look at my implementation of the omap2
> controller driver)

I am talking about queueing more than 1 request, we simply send a
message that can be triggered by either remoteproc for PM purposes or by
different rpmsg clients sending a message. It is delivered into the
mailbox and there is no implicit ack needed on tx_done since that is
dealt by the client messaging protocol sitting above. We will not be
using blocking mode, so there can be multiple requests at the same time
(in the queue).

> 
>>>
>>>> Secondly, we may not need the logic around client knows_txdone and
>>>> tx_buffering together. I understand the need for buffering when you have
>>>> TX_POLL or TX_IRQ, but as far as TX_ACK is concerned, it is a client
>>>> protocol-level knowledge, and so the tx buffering logic can remain with
>>>> the client itself. This should simplify the code a little bit and get
>>>> rid of the ipc_client_txdone API.
>>>>
>>> Yeah I had it that way originally. But then I realized we could be
>>> running an 'ACK Packet' protocol over a controller that supports only
>>> POLL. In that case the controller's poll doesn't override client's
>>> knows_txdone because we want the client to cut-short the next poll
>>> delay as soon as it gets an ACK packet.
>>
>> I think the same can be achieved from the Rx path upon an interrupt in
>> the specific controller, without having to introduce the knows_txdone.
>>
> RX may not only be responses, it could very well be a remote command
> just before the response to the last local command. OR the RX
> responses may be out of order. So it can't be tied to the RX
> interrupt.

Do you have the same shared payload in both directions? If so, the above
will work. Otherwise, I understand the scenario.

>> It is knowledge intrinsic to a controller/mailbox. I really hope that
>> there are no controllers where you have to poll for Rx too :)
>>
> No, not intrinsic to controller, but to the high level protocol.
> Yes, I assume the RX to be always interrupt driven :)

Until someone (out of their minds) comes up with it :)

> 
>>>
>>>> Looking at the current use-cases, I think OMAP might be the only one
>>>> which needs the buffering. The API that Loic added suggests that he
>>>> either sends a message and expects a response, or just sends a message
>>>> if the transport is free (I am not sure if he is using the API that uses
>>>> buffering currently). PL320 is the same as the first scenario that Loic has.
>>>>
>>> Yeah I too expect TX buffering to be very rare.
>>
>> If so, can we eliminate this for the first pass, and leave it to the
>> controllers for now or dictate this based on a tx_buffering property? As
>> I see it, we do not yet have an agreement on the Tx buffering semantics.
>>
> As I said, among other advantages, TX buffering is needed to reduce
> latencies. My platform's protocol isn't yet clear as to whether use
> shared-memory (secure and non-secure versions) for not very large data
> transfers or interrupt payload. So if we get good enough speed we
> could save cost on dedicated memories.
> 
> I wrote the omap2 controller driver code to convey my proposal better.
> If you could please tell me how TX buffering is a problem for OMAP, it
> will help me understand your concern better.

It is not a problem for OMAP, it is about only maintaining the void * in
the Tx queue. Since OMAP uses only a u32 message, I could have used the
void * as the u32 message but not a pointer (same approach we had taken
in the previous series). I am talking in general about the void *, and
the limitations it poses on client users. The other thing is that you
have defined 10 as the queue length in the core, this should be dictated
by the controller or mailbox. What works for one platform may not work
for some others (this is what you saw as different config options
between OMAP and DBX500)


>>>
>>> Secondly, I believe we acknowledged the fact that a client can't do
>>> without controller specific knowledge. So in proper implementation the
>>> controller's header would look like
>>>
>>> struct foobar_con_mssg {
>>>    int datalen; /* size of received packet in bytes */
>>>    u8 *buf;  /* buffer that holds the packet data */
>>>     .....
>>> };
>>>
>>> So instead of telling the API the 'datalen' and the remaining
>>> structure of each message, we simply pass "struct foobar_con_mssg *"
>>> as a void* to the API.
>>
>> This has to be documented very well. And yes, I did acknowledge the
>> inter-dependencies portion for understanding the packet structure (there
>> is no way if you have a packet of 6 ints and you expect specific ints
>> for specific fields). The size and void * are generic enough that can be
>> present in the core to perform some error checking. The API would be
>> akin to memcpy then. The other motivation is based on the buffering
>> scheme (same comment as above on Tx buffering), which we haven't agreed
>> upon completely.
>>
> How could the core perform any meaningful sanity check?  What if we
> send/receive proper 'datalen' of garbage data?  What if the client
> sends a "Give me info in not more than 32-bytes at a time" command to
> the remote and the remote has valid info worth only 16 bytes?
> IMHO there is not much for core to verify in a packet in transit. The
> introduced checks are not worth it and actually limit some scenarios
> like above example.

OK, I had mainly two ideas, one telling the size of the void * on Tx,
with the controller driver specifying max (and maybe min sizes expected)
so that some base error check can be done. This may be a basic check,
but atleast provides some level of sanity checking. On Rx-side, send the
size of the void * back to the client driver. The example you gave is
upto the client communication protocol, the remote may not even choose
to send the data if it doesn't have 32 bytes.

The second (major reason) idea was driven by the kfifo implementation
for buffering in core code for which I need the size field, so that the
clients need not be intelligent about the status of its tx submission
and maintaining its pointer (if you have different calling contexts). I
guess both of us are coming from different perspectives here, you may
find kfifos inefficient and I may find the complexity in client driver
unnecessary for maintaining pointers. How about defining add and remove
buffer ops in the controller driver so that it can choose its
implementation, while we keep the overall flow architecture in the core
code?

> 
> 
>>>>
>>>> Assigning the tx_block at channel request time might not be flexible
>>>> enough. We should not impose that the client will request and release
>>>> channels with different modes if both scenarios are needed.
>>>>
>>> If there is one blocking request, no more could arrive (blocking or
>>> non-blocking).
>>
>> Well, you are assuming that there is only one thread from within the
>> client driver who is gonna use the send API. There is nothing in the
>> code that stops from say two threads/contexts queueing in the message
>> from the same client driver. I am ok from my side for this to be sorted
>> out later, since I won't be using the blocking mode,
>>
> Thanks
> 
>>>>
>>>> Do we need to add an API similar to mailbox_msg_send_receive_no_irq, or
>>>> are you leaving it to be client's responsibility?
>>>>
>>> Yes the API provides enough ways for a client to do that.
>>
>> I will let Loic comment on this, based on his usage/complexity in the
>> client. I think you got lucky with PL320 implementation since it fills
>> in the buffer on a Tx done, so you have folded that functionality in
>> send_data itself.
>>
> No, the pl320 models the links properly. The links could be used for
> RX or TX independently.
> Any RX channel will return data only from a remote. The TX returns
> data in tx-buffer which may or may not be changed by the remote after
> reading. The Highbank's protocol make use of that feature. Though I am
> interested to know if Loic has some unmet requirements still.

thanks for the clarification.

> 
> 
>>>>
>>> Yeah, I changed that to it last minute :)
>>> The API has no real use of controller nodes, it works solely on a
>>> global pool of mailboxes. I tried to reflect that in code.
>>
>> Can we go back to using controller nodes? I understand that the API
>> doesn't use much, but the list of controller nodes is gonna be static
>> anyway in the file. It just improves the search algorithm when looking
>> for a mailbox. We have a new device coming up (u-boot patches already
>> submitted) wherein we have 13 controller instances, each with about 4 to
>> 6 links, a linear search would be really painful.
>>
> OK I'll keep a local list of controllers.

Sure, thanks.

> 
> 
>>>>
>>> There are some highly programmable controllers that, if the driver is
>>> proper, could change behavior runtime. For ex, if the controller
>>> supports, a client might want to broadcast messages to multiple
>>> remotes or listen for messages from more than one remote source or
>>> both. The client could, say, specify bitmasks for such source/sink
>>> remotes via cntlr_data while requesting the mailbox.  PL320 could work
>>> in such mode if rest all fits.
>>
>> Are you configuring the specific mailbox or configuring the controller
>> on a whole in this particular example?
>>
> The cntlr_data is to configure the link/mailbox, not the controller.

then, can we rename this to 'link_data' or something that doesn't imply
controller to avoid confusion? I guess you meant it as controller driver
data rather than controller instance data, but the name is a bit misleading.

> 
>>>>
>>> A controller is assumed to be a bunch of identical links/mailboxes.
>>> However the cntlr_data could still help the client specify mode in
>>> which it wants a mailbox behave.
>>
>> Yeah, assumptions hold true until an unfortunate SoC comes up with it
>> :). The TI AM3352 has one link that doesn't behave quite like the other
>> (I am hoping to avoid using it), so I am ok with it for now. Guess we
>> can always change it when a concrete need arises.
>>
> It would work right now :)   If your controller has 2 types of links,
> the driver should register each bunch separately, each with its own
> ipc_link_ops, with the core. The core can already take care of the
> rest.

Yeah, it can be done that way, but that's a not-so-elegant work-around
IMHO. It's calling ipc_links_register twice on the same controller. Idea
was that the API would distinguish different controllers, not the same
one. Also, see the above example if you were to treat a link as Rx or Tx
only (functional behavior differences even though the link is exactly
the same type).

> 
>> I prefer to see the controller_ops for startup/shutdown atleast. This
>> will allow the controller code state machine to be much better
>> maintained and make the code look good. As I said, with our new device,
>> where we have 13 controllers this will be very helpful. Also from what
>> Andy explained, you seem to have two controllers that are quite
>> different from each other.
>>
> Yes, I have 2 types of controllers and I already thought about
> multiple controllers in a platform.
>  What do you expect to do in controller startup/shutdown? Since the
> API works on individual links, not the controllers, when would it call
> controller_start() and controller_shutdown()?  The ipc_link's
> startup/shutdown are already non-atomic, if the controller needs any
> setup it could do it in the first link's startup and teardown in the
> last link's shutdown. Not to forget the resources lke IRQ are usually
> per Link which should be acquired/released upon link's use/idle.
>  While writing the OMAP2 controller driver, did I miss any controller
> startup/shutdown ?

It just delineates the code better, and has flexibility later on to
extend any controller ops or exposing new controller-specific API. The
controller start and stop will be called in the same function as
ipc_request_channel. The other thing is adding a check for the presence
of startup ops before actually invoking it, that way controller
implementations with no special startup needed can avoid it. Controller
ops in ipc_controller and link_ops in ipc_link would give better
flexibility for controller driver implementations.

Yeah, the pm_runtime_enable cannot be called twice when mailbox is
invoked from multiple clients on separate links, so there has to a
controller-level logic/ref-counting for that. The clocking for us is on
the controller.

regards
Suman


From gregory.clement at free-electrons.com  Tue May  7 17:54:24 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 07 May 2013 23:54:24 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <20130507214256.GC5414@1wt.eu>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
 <51892E87.5020903@itooo.com> <518971D4.5000603@free-electrons.com>
 <20130507214256.GC5414@1wt.eu>
Message-ID: <51897810.8020002@free-electrons.com>

Hi Willy,

On 05/07/2013 11:42 PM, Willy Tarreau wrote:
> Hi Gr?gory,
> 
> On Tue, May 07, 2013 at 11:27:48PM +0200, Gregory CLEMENT wrote:
>> I built and tested backport-3.8 and indeed the Ethernet is broken.
>> It was cause by a recent batch of fixes that I added, now I have to
>> figure out why they have broken the ethernet whereas they were supposed
>> to make it work better!
> 
> If that can help you, here is the list of (possibly relevant) patches
> I have applied on top of 3.9 picked from your repository some time
> ago (it's not up to date with the latest versions due to merge issues
> inducing laziness on my side) :
> 
> $ git log --oneline --grep=free-electrons v3.9.. 
> 65d2b5c ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
> 26cabde ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
> 34b32e8 ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
> 31504c0 ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
> 8cc752e drivers: memory: Introduce Marvell EBU Device Bus driver
> 48c6ddc arm: mvebu: update defconfig with PCI and USB support
> f4ed5ba arm: mvebu: PCIe Device Tree informations for Armada XP GP
> b1ed2c5 arm: mvebu: PCIe Device Tree informations for Armada 370 DB
> 51e91a9 arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
> 402f9ba arm: mvebu: PCIe Device Tree informations for Armada XP DB
> 4899409 arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
> fb6d69f arm: mvebu: add PCIe Device Tree informations for Armada XP
> c523287 arm: mvebu: add PCIe Device Tree informations for Armada 370
> 998ee7a arm: mvebu: PCIe support is now available on mvebu
> fc9b219 pci: PCIe driver for Marvell Armada 370/XP systems
> 4b765fb clk: mvebu: add more PCIe clocks for Armada XP
> af3bcd9 clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
> 6cee09e arm: pci: add a align_resource hook
> 80fa698 pci: infrastructure to add drivers in drivers/pci/host
> 91ca5a7 of/pci: Provide support for parsing PCI DT ranges property
> e46b3e7 arm: plat-orion: remove addr-map code
> d11befe arm: mach-mv78xx0: convert to use the mvebu-mbus driver
> a508a65 arm: mach-orion5x: convert to use mvebu-mbus driver
> e249639 arm: mach-dove: convert to use mvebu-mbus driver
> 70efe5e arm: mach-kirkwood: convert to use mvebu-mbus driver
> 37e82515 arm: mach-mvebu: convert to use mvebu-mbus driver
> 035f910 bus: introduce an Marvell EBU MBus driver
> 527d658 arm: mach-orion5x: use mv_mbus_dram_info() in PCI code
> c1b44db arm: plat-orion: use mv_mbus_dram_info() in PCIe code
> 59463f4 arm: plat-orion: only build addr-map.c when needed
> 
> With those my AX3 works fine. If that can help, I can send them all to
> you off-list, in case you notice a minor difference with something.

Thanks for your help but I finally found the guilty commit, it was
"66d0539 net: mvneta: convert to percpu interrupt".

This commit was never submitted because finally I realized that it was
broken in SMP. Finally it was the commit "arm: mvebu: Use local
interrupt only for the timer 0" which was the correct solution.

With the first patch I had converted the mvneta driver to use percpu
IRQ, but as I explained in the log of the 2nd patch: "the interrupts
have to be freed when the .stop() function is called. As the
free_percpu_irq() function don't disable the interrupt line, we have
to do it on each CPU before calling this. The function
disable_percpu_irq() only disable the percpu on the current CPU and
there is no function which allows to disable a percpu irq on a given
CPU."

So Greg, the solution is just to revert the commit 66d0539. I am going
to update the backport-3.8 branch in a couple of minutes.

Regards,
-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From w at 1wt.eu  Tue May  7 18:12:37 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Wed, 8 May 2013 00:12:37 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51897810.8020002@free-electrons.com>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
 <51892E87.5020903@itooo.com> <518971D4.5000603@free-electrons.com>
 <20130507214256.GC5414@1wt.eu> <51897810.8020002@free-electrons.com>
Message-ID: <20130507221237.GD5414@1wt.eu>

Hi Gr?gory,

On Tue, May 07, 2013 at 11:54:24PM +0200, Gregory CLEMENT wrote:
> Thanks for your help but I finally found the guilty commit, it was
> "66d0539 net: mvneta: convert to percpu interrupt".

Cool! Indeed I remember about this one that you proposed to me to
fix a regression I was experiencing on my mirabox after I picked
this one :

   f492fcf arm: mvebu: Add support for local interrupt

> This commit was never submitted because finally I realized that it was
> broken in SMP.

Yes I remember you explained me this.

> Finally it was the commit "arm: mvebu: Use local
> interrupt only for the timer 0" which was the correct solution.

Perfect.

(...)
> So Greg, the solution is just to revert the commit 66d0539. I am going
> to update the backport-3.8 branch in a couple of minutes.

Maybe it could be useful to think about backport-3.9 soon ? :-)

Best regards,
Willy



From swarren at wwwdotorg.org  Tue May  7 18:53:52 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue,  7 May 2013 16:53:52 -0600
Subject: [PATCH] USB: set device dma_mask without reference to global data
Message-ID: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Many USB host drivers contain code such as:

if (!pdev->dev.dma_mask)
        pdev->dev.dma_mask = &tegra_ehci_dma_mask;

... where tegra_ehci_dma_mask is a global. I suspect this code originated
in commit 4a53f4e "USB: ehci-tegra: add probing through device tree" and
was simply copied everywhere else.

This works fine when the code is built-in, but can cause a crash when the
code is in a module. The first module load sets up the dma_mask pointer,
but if the module is removed and re-inserted, the value is now non-NULL,
and hence is not updated to point at the new location, and hence points
at a stale location within the previous module load address, which in
turn causes a crash if the pointer is de-referenced.

The simplest way of solving this seems to be to copy the code from
ehci-platform.c, which uses the coherent_dma_mask as the target for the
dma_mask pointer.

Suggested-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 drivers/usb/chipidea/ci13xxx_imx.c |   15 ++++-----------
 drivers/usb/dwc3/dwc3-exynos.c     |    6 +++---
 drivers/usb/host/ehci-atmel.c      |    6 +++---
 drivers/usb/host/ehci-omap.c       |    8 ++++----
 drivers/usb/host/ehci-orion.c      |    6 +++---
 drivers/usb/host/ehci-s5p.c        |    4 +---
 drivers/usb/host/ehci-spear.c      |    6 +++---
 drivers/usb/host/ehci-tegra.c      |    6 +++---
 drivers/usb/host/ohci-at91.c       |    6 +++---
 drivers/usb/host/ohci-exynos.c     |    4 +---
 drivers/usb/host/ohci-omap3.c      |    8 ++++----
 drivers/usb/host/ohci-pxa27x.c     |    6 +++---
 drivers/usb/host/ohci-spear.c      |    6 +++---
 drivers/usb/host/uhci-platform.c   |    6 +++---
 14 files changed, 41 insertions(+), 52 deletions(-)

diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
index 8faec9d..73f9d5f 100644
--- a/drivers/usb/chipidea/ci13xxx_imx.c
+++ b/drivers/usb/chipidea/ci13xxx_imx.c
@@ -173,17 +173,10 @@ static int ci13xxx_imx_probe(struct platform_device *pdev)
 
 	ci13xxx_imx_platdata.phy = data->phy;
 
-	if (!pdev->dev.dma_mask) {
-		pdev->dev.dma_mask = devm_kzalloc(&pdev->dev,
-				      sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-		if (!pdev->dev.dma_mask) {
-			ret = -ENOMEM;
-			dev_err(&pdev->dev, "Failed to alloc dma_mask!\n");
-			goto err;
-		}
-		*pdev->dev.dma_mask = DMA_BIT_MASK(32);
-		dma_set_coherent_mask(&pdev->dev, *pdev->dev.dma_mask);
-	}
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	if (usbmisc_ops && usbmisc_ops->init) {
 		ret = usbmisc_ops->init(&pdev->dev);
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index a8afe6e..929e7dd 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -95,8 +95,6 @@ static int dwc3_exynos_remove_child(struct device *dev, void *unused)
 	return 0;
 }
 
-static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
-
 static int dwc3_exynos_probe(struct platform_device *pdev)
 {
 	struct dwc3_exynos	*exynos;
@@ -118,7 +116,9 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
 	 * Once we move to full device tree support this will vanish off.
 	 */
 	if (!dev->dma_mask)
-		dev->dma_mask = &dwc3_exynos_dma_mask;
+		dev->dma_mask = &dev->coherent_dma_mask;
+	if (!dev->coherent_dma_mask)
+		dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
 	platform_set_drvdata(pdev, exynos);
 
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index 6642009..02f4611 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -63,8 +63,6 @@ static void atmel_stop_ehci(struct platform_device *pdev)
 
 /*-------------------------------------------------------------------------*/
 
-static u64 at91_ehci_dma_mask = DMA_BIT_MASK(32);
-
 static int ehci_atmel_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
@@ -93,7 +91,9 @@ static int ehci_atmel_drv_probe(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &at91_ehci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
 	if (!hcd) {
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 3d1491b..16d7150 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -90,8 +90,6 @@ static const struct ehci_driver_overrides ehci_omap_overrides __initdata = {
 	.extra_priv_size = sizeof(struct omap_hcd),
 };
 
-static u64 omap_ehci_dma_mask = DMA_BIT_MASK(32);
-
 /**
  * ehci_hcd_omap_probe - initialize TI-based HCDs
  *
@@ -146,8 +144,10 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
 	 * Since shared usb code relies on it, set it here for now.
 	 * Once we have dma capability bindings this can go away.
 	 */
-	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &omap_ehci_dma_mask;
+	if (!dev->dma_mask)
+		dev->dma_mask = &dev->coherent_dma_mask;
+	if (!dev->coherent_dma_mask)
+		dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
 	hcd = usb_create_hcd(&ehci_omap_hc_driver, dev,
 			dev_name(dev));
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 54c5794..efbc588 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -137,8 +137,6 @@ ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
 	}
 }
 
-static u64 ehci_orion_dma_mask = DMA_BIT_MASK(32);
-
 static int ehci_orion_drv_probe(struct platform_device *pdev)
 {
 	struct orion_ehci_data *pd = pdev->dev.platform_data;
@@ -183,7 +181,9 @@ static int ehci_orion_drv_probe(struct platform_device *pdev)
 	 * now. Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &ehci_orion_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	if (!request_mem_region(res->start, resource_size(res),
 				ehci_orion_hc_driver.description)) {
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 6357752..a81465e 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -71,8 +71,6 @@ static void s5p_setup_vbus_gpio(struct platform_device *pdev)
 		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
 }
 
-static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
-
 static int s5p_ehci_probe(struct platform_device *pdev)
 {
 	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
@@ -90,7 +88,7 @@ static int s5p_ehci_probe(struct platform_device *pdev)
 	 * Once we move to full device tree support this will vanish off.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &ehci_s5p_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 	if (!pdev->dev.coherent_dma_mask)
 		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
index 61ecfb3..bd3e5cb 100644
--- a/drivers/usb/host/ehci-spear.c
+++ b/drivers/usb/host/ehci-spear.c
@@ -58,8 +58,6 @@ static int ehci_spear_drv_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(ehci_spear_pm_ops, ehci_spear_drv_suspend,
 		ehci_spear_drv_resume);
 
-static u64 spear_ehci_dma_mask = DMA_BIT_MASK(32);
-
 static int spear_ehci_hcd_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd ;
@@ -84,7 +82,9 @@ static int spear_ehci_hcd_drv_probe(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &spear_ehci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	usbh_clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(usbh_clk)) {
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index e3eddc3..59d111b 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -637,8 +637,6 @@ static void tegra_ehci_set_phcd(struct usb_phy *x, bool enable)
 	writel(val, base + TEGRA_USB_PORTSC1);
 }
 
-static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
-
 static int tegra_ehci_probe(struct platform_device *pdev)
 {
 	struct resource *res;
@@ -661,7 +659,9 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &tegra_ehci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	setup_vbus_gpio(pdev, pdata);
 
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a0cb44f..2ee1496 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -504,8 +504,6 @@ static const struct of_device_id at91_ohci_dt_ids[] = {
 
 MODULE_DEVICE_TABLE(of, at91_ohci_dt_ids);
 
-static u64 at91_ohci_dma_mask = DMA_BIT_MASK(32);
-
 static int ohci_at91_of_init(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -522,7 +520,9 @@ static int ohci_at91_of_init(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &at91_ohci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 	if (!pdata)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 07592c0..b0b542c 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -98,8 +98,6 @@ static const struct hc_driver exynos_ohci_hc_driver = {
 	.start_port_reset	= ohci_start_port_reset,
 };
 
-static u64 ohci_exynos_dma_mask = DMA_BIT_MASK(32);
-
 static int exynos_ohci_probe(struct platform_device *pdev)
 {
 	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
@@ -117,7 +115,7 @@ static int exynos_ohci_probe(struct platform_device *pdev)
 	 * Once we move to full device tree support this will vanish off.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &ohci_exynos_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 	if (!pdev->dev.coherent_dma_mask)
 		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c
index ddfc314..8663851 100644
--- a/drivers/usb/host/ohci-omap3.c
+++ b/drivers/usb/host/ohci-omap3.c
@@ -114,8 +114,6 @@ static const struct hc_driver ohci_omap3_hc_driver = {
 
 /*-------------------------------------------------------------------------*/
 
-static u64 omap_ohci_dma_mask = DMA_BIT_MASK(32);
-
 /*
  * configure so an HC device and id are always provided
  * always called with process context; sleeping is OK
@@ -168,8 +166,10 @@ static int ohci_hcd_omap3_probe(struct platform_device *pdev)
 	 * Since shared usb code relies on it, set it here for now.
 	 * Once we have dma capability bindings this can go away.
 	 */
-	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &omap_ohci_dma_mask;
+	if (!dev->dma_mask)
+		dev->dma_mask = &dev->coherent_dma_mask;
+	if (!dev->coherent_dma_mask)
+		dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
 	hcd = usb_create_hcd(&ohci_omap3_hc_driver, dev,
 			dev_name(dev));
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index efe71f3..279b2ef 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -282,8 +282,6 @@ static const struct of_device_id pxa_ohci_dt_ids[] = {
 
 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
 
-static u64 pxa_ohci_dma_mask = DMA_BIT_MASK(32);
-
 static int ohci_pxa_of_init(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -298,7 +296,9 @@ static int ohci_pxa_of_init(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &pxa_ohci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 	if (!pdata)
diff --git a/drivers/usb/host/ohci-spear.c b/drivers/usb/host/ohci-spear.c
index 9020bf0..3e19e01 100644
--- a/drivers/usb/host/ohci-spear.c
+++ b/drivers/usb/host/ohci-spear.c
@@ -91,8 +91,6 @@ static const struct hc_driver ohci_spear_hc_driver = {
 	.start_port_reset	= ohci_start_port_reset,
 };
 
-static u64 spear_ohci_dma_mask = DMA_BIT_MASK(32);
-
 static int spear_ohci_hcd_drv_probe(struct platform_device *pdev)
 {
 	const struct hc_driver *driver = &ohci_spear_hc_driver;
@@ -114,7 +112,9 @@ static int spear_ohci_hcd_drv_probe(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &spear_ohci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	usbh_clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(usbh_clk)) {
diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
index 8c4dace..f1db61a 100644
--- a/drivers/usb/host/uhci-platform.c
+++ b/drivers/usb/host/uhci-platform.c
@@ -60,8 +60,6 @@ static const struct hc_driver uhci_platform_hc_driver = {
 	.hub_control =		uhci_hub_control,
 };
 
-static u64 platform_uhci_dma_mask = DMA_BIT_MASK(32);
-
 static int uhci_hcd_platform_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
@@ -78,7 +76,9 @@ static int uhci_hcd_platform_probe(struct platform_device *pdev)
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
-		pdev->dev.dma_mask = &platform_uhci_dma_mask;
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	if (!pdev->dev.coherent_dma_mask)
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
 	hcd = usb_create_hcd(&uhci_platform_hc_driver, &pdev->dev,
 			pdev->name);
-- 
1.7.10.4



From gregkh at linuxfoundation.org  Tue May  7 19:04:45 2013
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Tue, 7 May 2013 16:04:45 -0700
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20130507230445.GC9105@kroah.com>

On Tue, May 07, 2013 at 04:53:52PM -0600, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Many USB host drivers contain code such as:
> 
> if (!pdev->dev.dma_mask)
>         pdev->dev.dma_mask = &tegra_ehci_dma_mask;
> 
> ... where tegra_ehci_dma_mask is a global. I suspect this code originated
> in commit 4a53f4e "USB: ehci-tegra: add probing through device tree" and
> was simply copied everywhere else.
> 
> This works fine when the code is built-in, but can cause a crash when the
> code is in a module. The first module load sets up the dma_mask pointer,
> but if the module is removed and re-inserted, the value is now non-NULL,
> and hence is not updated to point at the new location, and hence points
> at a stale location within the previous module load address, which in
> turn causes a crash if the pointer is de-referenced.
> 
> The simplest way of solving this seems to be to copy the code from
> ehci-platform.c, which uses the coherent_dma_mask as the target for the
> dma_mask pointer.
> 
> Suggested-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

So this needs to go in for 3.10, right?  Any older kernels as well?  If
so, which ones?

thanks,

greg k-h


From tony at atomide.com  Tue May  7 19:19:25 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 May 2013 16:19:25 -0700
Subject: [GIT PULL 4/5] ARM: arm-soc: late cleanups
In-Reply-To: <1367947574-2934383-5-git-send-email-arnd@arndb.de>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
 <1367947574-2934383-5-git-send-email-arnd@arndb.de>
Message-ID: <20130507231925.GR28721@atomide.com>

Linus,

* Arnd Bergmann <arnd at arndb.de> [130507 10:32]:
> The following changes since commit
> 
>    763e6b9 Merge tag 'dt-for-linus-2' into for-next
> 
> are available in the git repository at
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/cleanup-for-linus-2
...
 
> Vaibhav Hiremath (1):
>       ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a

Turns out this urgent boot fix got undone in the merge somehow.
Maybe just reapply it? The following should do it with some fuzz:

$ git show 626479696d2 | patch -p1

Or let me know if you want me to send you a patch.

Then in addition to the above, I'm also seeing a regression with commit
8a965b3b (mm, slab_common: Fix bootstrap creation of kmalloc caches),
but it seems to be related to some kconfig option. Seeing it on at least
omap and vexpress, I'll post more info on that once I've tracked it down:

[    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000054
[    0.000000] pgd = c0004000
[    0.000000] [00000054] *pgd=00000000
[    0.000000] Internal error: Oops: 5 [#1] SMP ARM
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.9.0-11485-gbb9055b #633
[    0.000000] task: c078d7d0 ti: c0782000 task.ti: c0782000
[    0.000000] PC is at kmem_cache_alloc_trace+0x50/0x178
[    0.000000] LR is at kmem_cache_alloc_trace+0x38/0x178
[    0.000000] pc : [<c010d058>]    lr : [<c010d040>]    psr: 600001d3
[    0.000000] sp : c0783f70  ip : 600001d3  fp : 00000000
[    0.000000] r10: 000000c0  r9 : c00a5444  r8 : 000080d0
[    0.000000] r7 : 00000000  r6 : 600001d3  r5 : 00000000  r4 : 00008000
[    0.000000] r3 : 00000050  r2 : c0782000  r1 : c078d7d0  r0 : c010d040
[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
[    0.000000] Control: 10c5387d  Table: 80004019  DAC: 00000015
[    0.000000] Process swapper/0 (pid: 0, stack limit = 0xc0782240)
[    0.000000] Stack: (0xc0783f70 to 0xc0784000)
[    0.000000] 3f60:                                     00002014 00000010 c07d6510 00000000
[    0.000000] 3f80: 00000000 00000000 00000000 413fc082 c078a480 c00a5444 c07d6510 00000000
[    0.000000] 3fa0: 00000010 c0766348 ffffffff c073cfb4 bfffffff c080d78c c080d780 c0720828
[    0.000000] 3fc0: ffffffff ffffffff c0720478 00000000 00000000 c0766348 00000000 10c5387d
[    0.000000] 3fe0: c078a4c8 c076674c c078ecb4 80004059 00000000 80008074 00000000 00000000
[    0.000000] [<c010d058>] (kmem_cache_alloc_trace+0x50/0x178) from [<c00a5444>] (alloc_desc+0x24/0xb4)
[    0.000000] [<c00a5444>] (alloc_desc+0x24/0xb4) from [<c073cfb4>] (early_irq_init+0x78/0xec)
[    0.000000] [<c073cfb4>] (early_irq_init+0x78/0xec) from [<c0720828>] (start_kernel+0x17c/0x33c)
[    0.000000] [<c0720828>] (start_kernel+0x17c/0x33c) from [<80008074>] (0x80008074)
[    0.000000] Code: e5923014 e2833014 e1a03103 e0873003 (e5931004)
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!

Regards,

Tony


From arnd at arndb.de  Tue May  7 19:42:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 01:42:11 +0200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <20130507230445.GC9105@kroah.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <20130507230445.GC9105@kroah.com>
Message-ID: <201305080142.12025.arnd@arndb.de>

On Wednesday 08 May 2013, Greg Kroah-Hartman wrote:
> On Tue, May 07, 2013 at 04:53:52PM -0600, Stephen Warren wrote:
> > From: Stephen Warren <swarren at nvidia.com>

> > Suggested-by: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Stephen Warren <swarren at nvidia.com>
> 
> So this needs to go in for 3.10, right?  Any older kernels as well?  If
> so, which ones?

The fix should definitely go into 3.10, but I'd suggest waiting with
the backport for a couple of -rc releases to avoid possible regressions.
We know that the current code is broken, but few people fully understand
what is going on with coherent_dma_mask, so it might cause new problems
in combination with some other unknown bug, and I don't see this as
urgent: none of the ARM defconfigs build this driver as a loadable
module and there is no bug in the built-in case. For some reason, only
the ARM back-end drivers are broken.

The first occurence was apparently in 3.3, but only in ehci-tegra.c,
while the other drivers subsequently copied the bug.

	Arnd


From rjw at sisk.pl  Tue May  7 20:26:34 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 08 May 2013 02:26:34 +0200
Subject: [PATCH,
 RFC 02/22] cpufreq: ARM_DT_BL_CPUFREQ needs ARM_CPU_TOPOLOGY
In-Reply-To: <CAKohponuYRm+D-FU5_7Ny1PPmwUhFLm9DkAR9iHURur+GFq_kA@mail.gmail.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-3-git-send-email-arnd@arndb.de>
 <CAKohponuYRm+D-FU5_7Ny1PPmwUhFLm9DkAR9iHURur+GFq_kA@mail.gmail.com>
Message-ID: <2500374.5Hpjds0B3f@vostro.rjw.lan>

On Saturday, May 04, 2013 12:09:40 PM Viresh Kumar wrote:
> On 2 May 2013 20:46, Arnd Bergmann <arnd at arndb.de> wrote:
> > The big.LITTLE cpufreq driver uses the CPU topology API, which
> > needs to be reflected in Kconfig to prevent broken configurations.
> >
> > warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
> > has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM && ARM_CPU_TOPOLOGY)
> >
> > Cc: Rafael J. Wysocki <rjw at sisk.pl>
> > Cc: Viresh Kumar <viresh.kumar at linaro.org>
> > Cc: cpufreq at vger.kernel.org
> > Cc: linux-pm at vger.kernel.org
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > ---
> >  drivers/cpufreq/Kconfig.arm | 1 +
> >  1 file changed, 1 insertion(+)
> 
> With all the discussions we had, please see if you can replace your
> patch with this one (Attached too for applying, copy/paste in gmail
> will break it):
> 
> From: Viresh Kumar <viresh.kumar at linaro.org>
> Date: Sat, 4 May 2013 12:03:54 +0530
> Subject: [PATCH] cpufreq: ARM big LITTLE: Fix Kconfig entries
> 
> This fixes usage of "depends on" and "select" options in Kconfig for ARM big
> LITTLE cpufreq driver. Otherwise we get these warnings:
> 
> warning: (ARM_DT_BL_CPUFREQ) selects ARM_BIG_LITTLE_CPUFREQ which
> has unmet direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ && ARM &&
> ARM_CPU_TOPOLOGY)
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>

Queued up as a fix for v3.10.

Thanks,
Rafael


> ---
>  drivers/cpufreq/Kconfig.arm | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 634e992..a924408 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -3,17 +3,17 @@
>  #
> 
>  config ARM_BIG_LITTLE_CPUFREQ
> -	tristate
> -	depends on ARM_CPU_TOPOLOGY
> -	select PM_OPP
> +	tristate "Generic ARM big LITTLE CPUfreq driver"
> +	depends on ARM_CPU_TOPOLOGY && PM_OPP && HAVE_CLK
> +	help
> +	  This enables the Generic CPUfreq driver for ARM big.LITTLE platforms.
> 
>  config ARM_DT_BL_CPUFREQ
> -	tristate "Generic ARM big LITTLE CPUfreq driver probed via DT"
> -	select ARM_BIG_LITTLE_CPUFREQ
> -	depends on OF && HAVE_CLK
> +	tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver"
> +	depends on ARM_BIG_LITTLE_CPUFREQ && OF
>  	help
> -	  This enables the Generic CPUfreq driver for ARM big.LITTLE platform.
> -	  This gets frequency tables from DT.
> +	  This enables probing via DT for Generic CPUfreq driver for ARM
> +	  big.LITTLE platform. This gets frequency tables from DT.
> 
>  config ARM_EXYNOS_CPUFREQ
>  	bool "SAMSUNG EXYNOS SoCs"
-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From john.stultz at linaro.org  Tue May  7 20:30:52 2013
From: john.stultz at linaro.org (John Stultz)
Date: Tue, 07 May 2013 17:30:52 -0700
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <20130507201126.GA8169@amd.pavel.ucw.cz>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de> <20130506155304.GA6645@amd.pavel.ucw.cz>
 <201305062324.17080.arnd@arndb.de> <20130507135752.GA3500@amd.pavel.ucw.cz>
 <51892E5E.8090909@linaro.org> <20130507201126.GA8169@amd.pavel.ucw.cz>
Message-ID: <51899CBC.6020003@linaro.org>

On 05/07/2013 01:11 PM, Pavel Machek wrote:
> It seems we made a mistake when creating dw_apb_timer_of.c:
> picoxcell sched_clock had parts that were not related to
> dw_apb_timer, yet we moved them to dw_apb_timer_of, and tried to
> use them on socfpga.
>
> This results in system where user/system time is not measured
> properly, as demonstrated by
>      
>      time dd if=/dev/urandom of=/dev/zero bs=100000 count=100
>      
> So this patch switches sched_clock to hardware that exists on both
> platforms, and adds missing of_node_put() in dw_apb_timer_init().
>      
> Signed-off-by: Pavel Machek <pavel at denx.de>
> Acked-by: Jamie Iles <jamie at jamieiles.com>

Ok. I'm still not a happy about the general issue of 
sched_clock/clockevent code being in drivers/clocksources (I know, 
everyone is sick of my griping about it :), so reviewing this sucks, but 
at least this patch technically isn't making that issue worse.

Additionally, this is an *ugly* driver in my opinion. Its split between 
arch specific logic in arch/x86/kernel/apb_timer.c, 
arch/arm/mach-picoxcell/common.c, and arch/arm/mach-socfpga/socfpga.c, 
and then arch independent logic in drivers/clocksource/dw_apb_timer.c 
and drivers/clocksource/dw_apb_timer_of.c, but then it seems like much 
of drivers/clocksource/dw_apb_timer_of.c is actually ARM specific.

Are there any plans to clean this up in the future?

Also, next time please run checkpatch.pl to catch trivial issues like 
trailing whitespace. :P

But I've gone ahead and queued this for 3.11.

thanks
-john



From torvalds at linux-foundation.org  Tue May  7 20:59:56 2013
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Tue, 7 May 2013 17:59:56 -0700
Subject: [GIT PULL 4/5] ARM: arm-soc: late cleanups
In-Reply-To: <20130507231925.GR28721@atomide.com>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
 <1367947574-2934383-5-git-send-email-arnd@arndb.de>
 <20130507231925.GR28721@atomide.com>
Message-ID: <CA+55aFxHZSYV3UZMf+ezADX5z2psLm5a9Wpp6qcDQho7n2J6SA@mail.gmail.com>

On Tue, May 7, 2013 at 4:19 PM, Tony Lindgren <tony at atomide.com> wrote:
>
>> Vaibhav Hiremath (1):
>>       ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a
>
> Turns out this urgent boot fix got undone in the merge somehow.

Those lines actually disappeared already much earlier in my merge 6fa52ed33bea:

    Merge tag 'drivers-for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

last Saturday.

And it's my bad. I even know how it happened: I ended up doing that
merge twice (because I had to go back and fix something else), and
then I "optimized" it the second time. With all the omap2 conflicts
from that tree came from duplicate commits from the ARM tree, and I
ended up just taking the drivers-for-linus side for
arch/arm/mach-omap2. Which was correct for the other two files in
there (gpmc.c and gpmc-onenand.c). but the timer.c file had changes
from the arm tree.

Sorry about that one.

                 Linus


From hzpeterchen at gmail.com  Tue May  7 21:13:56 2013
From: hzpeterchen at gmail.com (Peter Chen)
Date: Wed, 8 May 2013 09:13:56 +0800
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>

On Wed, May 8, 2013 at 6:53 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> From: Stephen Warren <swarren at nvidia.com>
>
> Many USB host drivers contain code such as:
>
> if (!pdev->dev.dma_mask)
>         pdev->dev.dma_mask = &tegra_ehci_dma_mask;
>
> ... where tegra_ehci_dma_mask is a global. I suspect this code originated
> in commit 4a53f4e "USB: ehci-tegra: add probing through device tree" and
> was simply copied everywhere else.
>

One question: why device tree can't do this when create device?


From jg1.han at samsung.com  Tue May  7 21:41:37 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 08 May 2013 10:41:37 +0900
Subject: [PATCH] usb: gadget: s3c2410_udc: fix error return code in
 s3c2410_udc_probe()
In-Reply-To: <CAPgLHd9zzFi6dCBH0V=eeqVtd=UstiqM8fDcDsMCfujAfEDHTg@mail.gmail.com>
References: <CAPgLHd9zzFi6dCBH0V=eeqVtd=UstiqM8fDcDsMCfujAfEDHTg@mail.gmail.com>
Message-ID: <001a01ce4b8d$2e22fd40$8a68f7c0$@samsung.com>

On Tuesday, May 07, 2013 8:48 PM, Wei Yongjun wrote:
> 
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> 
> Fix to return a negative error code in the gpio_to_irq() error handling
> case instead of 0, as done elsewhere in this function.
> 
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Reviewed-by: Jingoo Han <jg1.han at samsung.com>

Best regards,
Jingoo Han


> ---
>  drivers/usb/gadget/s3c2410_udc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
> index d0e75e1..c974776 100644
> --- a/drivers/usb/gadget/s3c2410_udc.c
> +++ b/drivers/usb/gadget/s3c2410_udc.c
> @@ -1851,6 +1851,7 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
>  		irq = gpio_to_irq(udc_info->vbus_pin);
>  		if (irq < 0) {
>  			dev_err(dev, "no irq for gpio vbus pin\n");
> +			retval = irq;
>  			goto err_gpio_claim;
>  		}
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From swarren at wwwdotorg.org  Tue May  7 22:26:07 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 07 May 2013 20:26:07 -0600
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
Message-ID: <5189B7BF.8070607@wwwdotorg.org>

On 05/07/2013 07:13 PM, Peter Chen wrote:
> On Wed, May 8, 2013 at 6:53 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren at nvidia.com>
>>
>> Many USB host drivers contain code such as:
>>
>> if (!pdev->dev.dma_mask)
>>         pdev->dev.dma_mask = &tegra_ehci_dma_mask;
>>
>> ... where tegra_ehci_dma_mask is a global. I suspect this code originated
>> in commit 4a53f4e "USB: ehci-tegra: add probing through device tree" and
>> was simply copied everywhere else.
> 
> One question: why device tree can't do this when create device?

This probably could be initialized from some DT property. However,
there's no such property defined right now, and considering that DT is
supposed to be an ABI, we'd always need the code in this patch as a
fallback for DTs that were created before any such property was defined.

Equally, since the data is SoC-specific rather than board-specific, and
is even fairly unlikely to vary between SoC versions since these values
are all 0xffffffff anyway, I don't really see much point in putting it
into DT, rather than just putting the static data into the driver.


From swarren at wwwdotorg.org  Tue May  7 22:36:38 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 07 May 2013 20:36:38 -0600
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <20130507143338.79b3d893fcdc3bd79fbe9a57@linux-foundation.org>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <201304300004.20320.arnd@arndb.de> <5182AF83.4080705@wwwdotorg.org>
 <1956593.M6NmITdEKh@avalon>
 <20130507143338.79b3d893fcdc3bd79fbe9a57@linux-foundation.org>
Message-ID: <5189BA36.9000105@wwwdotorg.org>

On 05/07/2013 03:33 PM, Andrew Morton wrote:
> 
> We don't seem to have a well-defined path to travel here, and I don't
> get the feeling that anyone has signed up to walk it?
> 
> So I'm inclined to merge Stephen's patch as-is into 3.10.  It's pretty
> simple and standalone.  Any strenuous objections?
> 
> BTW, Olof told me off-list that this patch is a "critical piece" for
> running mainline Linux on ARM Chromebooks.  That was important
> information - more important than anything else we were told about this
> patch!
> 
> So Stephen, could I please have a new changelog for this patch which
> explains this application, and any other interesting/important things
> which were left out?  Quickly, please.

OK, how about the version below:

----------
Subject: drivers/video: implement a simple framebuffer driver

A simple frame-buffer describes a raw memory region that may be rendered
to, with the assumption that the display hardware has already been set
up to scan out from that buffer.

This is useful in cases where a bootloader exists and has set up the
display hardware, but a Linux driver doesn't yet exist for the display
hardware.

Examples use-cases include:

* The built-in LCD panels on the Samsung ARM chromebook, and Tegra
devices, and likely many other ARM or embedded systems. These cannot yet
be supported using a full graphics driver, since the panel control
should be provided by the CDF (Common Display Framework), which has been
stuck in design/review for quite some time. One could support these
panels using custom SoC-specific code, but there is a desire to use
common infra-structure rather than having each SoC vendor invent their
own code, hence the desire to wait for CDF.

* Hardware for which a full graphics driver is not yet available, and
the path to obtain one upstream isn't yet clear. For example, the
Raspberry Pi.

* Any hardware in early stages of upstreaming, before a full graphics
driver has been tackled. This driver can provide a graphical boot
console (even full X support) much earlier in the upstreaming process,
thus making new SoC or board support more generally useful earlier.
----------

I assume you can just edit the patch you have and don't need me to
resend with the adjusted description.


From hzpeterchen at gmail.com  Tue May  7 22:54:48 2013
From: hzpeterchen at gmail.com (Peter Chen)
Date: Wed, 8 May 2013 10:54:48 +0800
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <5189B7BF.8070607@wwwdotorg.org>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
 <5189B7BF.8070607@wwwdotorg.org>
Message-ID: <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>

>
> This probably could be initialized from some DT property. However,
> there's no such property defined right now, and considering that DT is
> supposed to be an ABI, we'd always need the code in this patch as a
> fallback for DTs that were created before any such property was defined.
>
> Equally, since the data is SoC-specific rather than board-specific, and
> is even fairly unlikely to vary between SoC versions since these values
> are all 0xffffffff anyway, I don't really see much point in putting it
> into DT, rather than just putting the static data into the driver.

I mean there is already dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
at function of_platform_device_create, why can't add
dev->dev.dma_mask = &dev->dev.coherent_dma_mask after that?

If DT core can do above things, can we delete dma_mask assignment
at every driver?


--
BR,
Peter Chen


From tony at atomide.com  Tue May  7 23:17:59 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 May 2013 20:17:59 -0700
Subject: [GIT PULL 4/5] ARM: arm-soc: late cleanups
In-Reply-To: <CA+55aFxHZSYV3UZMf+ezADX5z2psLm5a9Wpp6qcDQho7n2J6SA@mail.gmail.com>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
 <1367947574-2934383-5-git-send-email-arnd@arndb.de>
 <20130507231925.GR28721@atomide.com>
 <CA+55aFxHZSYV3UZMf+ezADX5z2psLm5a9Wpp6qcDQho7n2J6SA@mail.gmail.com>
Message-ID: <20130508031758.GT28721@atomide.com>

* Linus Torvalds <torvalds at linux-foundation.org> [130507 18:05]:
> On Tue, May 7, 2013 at 4:19 PM, Tony Lindgren <tony at atomide.com> wrote:
> >
> >> Vaibhav Hiremath (1):
> >>       ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a
> >
> > Turns out this urgent boot fix got undone in the merge somehow.
> 
> Those lines actually disappeared already much earlier in my merge 6fa52ed33bea:
> 
>     Merge tag 'drivers-for-linus' of
> git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
> 
> last Saturday.

Yes then we patched it on Sunday, and Arnd merged it into his branch.
But then hose lines disappeared again for the third time :)
 
> And it's my bad. I even know how it happened: I ended up doing that
> merge twice (because I had to go back and fix something else), and
> then I "optimized" it the second time. With all the omap2 conflicts
> from that tree came from duplicate commits from the ARM tree, and I
> ended up just taking the drivers-for-linus side for
> arch/arm/mach-omap2. Which was correct for the other two files in
> there (gpmc.c and gpmc-onenand.c). but the timer.c file had changes
> from the arm tree.
> 
> Sorry about that one.

No problem, thanks for fixing it quickly.

Regards, 

Tony


From rob at landley.net  Tue May  7 01:02:13 2013
From: rob at landley.net (Rob Landley)
Date: Tue, 07 May 2013 00:02:13 -0500
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
 (from pranavkumar@linaro.org on Mon May  6 07:19:50 2013)
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
Message-ID: <1367902933.18069.212@driftwood>

On 05/06/2013 07:19:50 AM, Pranavkumar Sawargaonkar wrote:
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> ---
>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/virtual/virtio-spec.txt  
> b/Documentation/virtual/virtio-spec.txt
> index 0d6ec85..3ca38f8 100644
> --- a/Documentation/virtual/virtio-spec.txt
> +++ b/Documentation/virtual/virtio-spec.txt
> @@ -1927,11 +1927,16 @@ Ports 2 onwards only if  
> VIRTIO_CONSOLE_F_MULTIPORT is set
>      ports; configuration fields nr_ports and max_nr_ports are
>      valid and control virtqueues will be used.
> 
> +  VIRTIO_CONSOLE_F_EMERG_WRITE(2) Device has support for emergency
> +  write. Configuration filed emerg_wr is valid.

Emergency?

Really?

Out of morbid curiosity, what would constitute an _emergency_ in a  
virtual machine logging context?

Rob

From torvalds at linux-foundation.org  Tue May  7 23:48:05 2013
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Tue, 7 May 2013 20:48:05 -0700
Subject: [GIT PULL 4/5] ARM: arm-soc: late cleanups
In-Reply-To: <20130508031758.GT28721@atomide.com>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
 <1367947574-2934383-5-git-send-email-arnd@arndb.de>
 <20130507231925.GR28721@atomide.com>
 <CA+55aFxHZSYV3UZMf+ezADX5z2psLm5a9Wpp6qcDQho7n2J6SA@mail.gmail.com>
 <20130508031758.GT28721@atomide.com>
Message-ID: <CA+55aFxsQSrRxGDjvFW84ezYj4PZPX=hSpsyNG-AqewbJ7X4Bw@mail.gmail.com>

On Tue, May 7, 2013 at 8:17 PM, Tony Lindgren <tony at atomide.com> wrote:
>
> Yes then we patched it on Sunday, and Arnd merged it into his branch.
> But then hose lines disappeared again for the third time :)

Yes, but that's because it's entirely pointless to "fix" things in the
wrong branch, especially after a back-merge.

So what ended up happening is that when I then pulled the next time,
you had random back-merges in your ARM tree (well, not you personally,
but Arnd), and as a result the later merge didn't have just one merge
base, it actually had *five* separate merge bases: all independent
common ancestors of the two branches being merged (*).

And *some* of the common ancestors had the lines, some didn't. And my
mainline didn't. So git merge decides that "hey, those lines used to
exist in the common ancestor of this new merge, but they don't exist
in mainline, and they still exist in the thing getting merged"

What do you think happens? Think about it.

The only reasonable thing to do (and git always does reasonable
things) is to say "oh, mainline must have *removed* those lines".

Git goes "The branch I'm merging clearly didn't do anything at all to
the lines: they used to exist back in the shared history, and they
still exist in the exact same form in the branch I'm merging." So they
stay removed in mainline.

(Ok, so that's anthropomorphising git to a fairly extreme point, but
it's actually pretty close to being the technical truth. As far as the
merge was concerned, Arnd's branch didn't really add those lines at
all, because they already existed when his branch started. The fact
that they went away and came back again is totally immaterial).

And this, btw, is just one more reason why back-merges are not a good
idea. It makes it basically impossible to say "so did you add or
remove something"? When you have multiple independent points in
history that are common to both branches, it's fundamentally ambiguous
whether merging things adds something that went away and came back
again in that shared history.

Criss-crossing merges are a horrible horrible idea, and the only sane
way to not criss-cross is to say "avoid back-merging from upstream".

Side note: these kinds of issues are unusual. You really have to do
something special to trigger this, but this is not unique. We've had
similar things happen in the past, and you don't actually need a
mis-merge for it to happen. You do need criss-crossing merges, though,
because that's how you get "oh, we have N different commits that are
all shared points in history, but are not ancestors of each other" (ie
what git calls "merge bases").

And no, this kind of thing does not happen every time you have
multiple merge bases. But multiple merge bases, together with code
that has gone back and forth on some issue, really is a very very bad
idea. In this case, the mis-merge was just the thing that triggered
"code went back-and-forth", but similar things can happen when you
have code that gets reverted and then re-done, and you have multiple
merge bases (one of which has the revert, while one has the re-doing
of it..)

The good news is that this is very rarely a real problem. The bad news
is that it's such a rare problem that people aren't even aware of it
as a problem (and reasonably *shouldn't* be aware of it as a
problem!). So when it happens, people get confused, because they've
never seen it before, and they get even more confused when their
"solution" (back-merge from upstream, fix it there, ask upstream to
pull the fix) doesn't actually fix anything, because you just end up
in the same situation *again*..

                   Linus

(*) Why five merge bases? Look at what my merge of those late cleanups
actually had to contend with:

    git merge-base --all 1bf25e78af31^ 1bf25e78af31^2

and notice how you get five different commits. They are all commits
that are common to *both* parents of that merge. You can try do

    gitk 1bf25e78af31^...1bf25e78af31^2

and try to figure those kinds of things out by hand. You can't, unless
you're superhuman. Because the history is a f*cking mess due to all
the back-merges. Yeah, yeah, none of them are pulling from "me", but
all of them are pulling from random other branches that people had
asked me to pull earlier, so they were basically mixing up history.

The ARM history has gotten much much better, but it's full of these
kinds of incestuous merges. The pull requests I get are not truly
independent development, although especially the early pull requests
are much less tightly coupled than they used to be.


From olof at lixom.net  Wed May  8 00:27:34 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 7 May 2013 21:27:34 -0700
Subject: [GIT PULL 4/5] ARM: arm-soc: late cleanups
In-Reply-To: <CA+55aFxsQSrRxGDjvFW84ezYj4PZPX=hSpsyNG-AqewbJ7X4Bw@mail.gmail.com>
References: <1367947574-2934383-1-git-send-email-arnd@arndb.de>
 <1367947574-2934383-5-git-send-email-arnd@arndb.de>
 <20130507231925.GR28721@atomide.com>
 <CA+55aFxHZSYV3UZMf+ezADX5z2psLm5a9Wpp6qcDQho7n2J6SA@mail.gmail.com>
 <20130508031758.GT28721@atomide.com>
 <CA+55aFxsQSrRxGDjvFW84ezYj4PZPX=hSpsyNG-AqewbJ7X4Bw@mail.gmail.com>
Message-ID: <CAOesGMiWoB_4DrgUyMUx5MzO9dwMKBm=ZzVHosWUoC_+OpV_Zw@mail.gmail.com>

On Tue, May 7, 2013 at 8:48 PM, Linus Torvalds
<torvalds at linux-foundation.org> wrote:

> The ARM history has gotten much much better, but it's full of these
> kinds of incestuous merges. The pull requests I get are not truly
> independent development, although especially the early pull requests
> are much less tightly coupled than they used to be.

A lot of this comes from the way we structure the submaintainers
submissions to arm-soc: Cleanups on the bottom, then new SoC support,
then board and dt changes, etc. It means there are a lot of branches
that build on top of each other. It's not uncommon that a
submaintainer needs to build some new feature on top of both some
cleanup as well as some other new development, which is then what
causes some of these merges and backmerges.

While our splitting into categories (cleanup/soc/board/dt/drivers)
isn't 100% natural for each submaintainer, it does allow us to force
some thought into how it all fits together between vendors, and it
also allows us to split the code up into sets that make a bit more
sense (IMHO) when it's sent up to you.

Our lives (short-term) would be a lot easier if we just did one long
single branch and we sent that up, with mostly serial history. But I
also think it's been working reasonably well to expose a bit more
w.r.t. who's spending efforts on cleanup and refactoring old code
code, and who's pumping in new features and drivers.

I'm definitely open for suggestions on how to improve the way we do things.


-Olof


From linux at prisktech.co.nz  Wed May  8 01:11:25 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 08 May 2013 17:11:25 +1200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <5189DE7D.7060205@prisktech.co.nz>

On 08/05/13 10:53, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
>
> Many USB host drivers contain code such as:
>
> if (!pdev->dev.dma_mask)
>          pdev->dev.dma_mask = &tegra_ehci_dma_mask;
>
> ... where tegra_ehci_dma_mask is a global. I suspect this code originated
> in commit 4a53f4e "USB: ehci-tegra: add probing through device tree" and
> was simply copied everywhere else.
>
> This works fine when the code is built-in, but can cause a crash when the
> code is in a module. The first module load sets up the dma_mask pointer,
> but if the module is removed and re-inserted, the value is now non-NULL,
> and hence is not updated to point at the new location, and hence points
> at a stale location within the previous module load address, which in
> turn causes a crash if the pointer is de-referenced.
>
> The simplest way of solving this seems to be to copy the code from
> ehci-platform.c, which uses the coherent_dma_mask as the target for the
> dma_mask pointer.
>
> Suggested-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
In the case of uhci-platform you would be absolutely correct. I copied the
example from tegra when we first had the problem on arch-vt8500.Because we
have no NAND support yet, I have always booted myrootfs from USB so it's
always been builtin and the problem wasnever a problem. The same problem 
would
have existed on ehci-vt8500 but Arnd replaced it with ehci-platform due to
the multiplatform issues.

for uhci-platform.c
Acked-by: Tony Prisk <linux at prisktech.co.nz>

Regards
Tony P


From jaswinder.singh at linaro.org  Wed May  8 01:44:00 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Wed, 8 May 2013 11:14:00 +0530
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <518976B9.2030605@ti.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
 <518976B9.2030605@ti.com>
Message-ID: <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>

On 8 May 2013 03:18, Suman Anna <s-anna at ti.com> wrote:
> Hi Jassi,
>
>> On 7 May 2013 05:15, Suman Anna <s-anna at ti.com> wrote:
>>>>
>>>>  The client(s) can always generate TX requests at a rate greater than
>>>> the API could transmit on the physical link. So as much as we dislike
>>>> it, we have to buffer TX requests, otherwise N clients would.
>>>
>>> The current code doesn't support N clients today anyway, and if they are
>>> blocking mode on top of it, it would never need Tx buffering.
>>>
>> No, I meant if the API doesn't buffer TX requests, then N client
>> drivers that simply need to send 2 or more messages would have to
>> buffer them locally.
>>  Also by buffering TX requests the API reduces TX latency by
>> submitting the next request atomically as soon as it knows the last TX
>> is done.
>
> OK. I do not have an issue with Tx buffering,
>
OK, thanks for confirming.

> but the manner it is done.
> As I said before, there is a big implementation detail on client users
> keeping their pointers in tact until the actual Tx is done - it
> increases the complexity of client code. I have proposed an idea below
> on the size discussion.
>
What makes this API different that you want it to create internal
copies of clients' requests?
I2C clients have been working fine. I believe most other apis work
similarly. No client died of the burden of having to preserve request
pointers until the request is served by the API.

BTW, by forcing the API to not directly use request structures from
clients we kill chances of zero-copy transfer use-cases.

Sorry, I don't think just to make it "easy" for some rare client (that
issues non-blocking pass-by-reference requests and don't even care to
know if the message was ever sent), we should add complexity to the
API _and_ kill some important use-cases.


>> Also logically coupling the independent physical links makes the
>> controller driver not very portable - what if some other platform has
>> usage of 3 send+receive and 2 send-only communications of the 8
>> physical links? The controller h/w is perfectly capable of providing
>> that, but its driver is not.
>
> That's upto that controller driver, right?
>
Yes, I meant the OMAP's controller driver need to be re-written
properly so as to not couple 2 links together as one RX and one TX.


>>> In anycase,
>>> global publication will have its own set of problems - mostly you are
>>> implying another layer of implementation that provides this sharing
>>> capability (since they have to be outside of any single client).
>>>
>> Yes. Though yet another way of doing it is for the controller driver
>> to populate N logical per physical link that needs to be shared.
>
> Yeah, I was implying the same idea.. The notifier chains in the current
> driver really meant the logical and physical is the same as we are
> returning the link handle, but with your current design of returning
> ipc_chan as an opaque handle, you already have the base infrastructure
> in place. Once we add tx callbacks, even the original mailbox series
> would have transformed into having a similar concept as what you have.
>
Though I would still suggest you manage a remote by a local 'server'
code - not every client needs to be bothered with request/response for
every other client.
Also the OMAP might be lucky, but the remote may not always simply
respond to commands from local clients. The remote might also send
some SOS or similar command on behalf of the remote as a whole. Such
requests should be handled by that local 'server' code.


>> The OMAP simply pass by value a u32 as a message.  Why do you think it
>> won't work ? (Please have a look at my implementation of the omap2
>> controller driver)
>
> I am talking about queueing more than 1 request, we simply send a
> message that can be triggered by either remoteproc for PM purposes or by
> different rpmsg clients sending a message. It is delivered into the
> mailbox and there is no implicit ack needed on tx_done since that is
> dealt by the client messaging protocol sitting above. We will not be
> using blocking mode, so there can be multiple requests at the same time
> (in the queue).
>
Yes that's what I am talking about.  Multiple requests would still be
a u32 each.

Since for OMAP a message is just a 32-bit number, a client would queue
requests as
{
      u32 cmd;
      cmd = COMMAND_A;
      ipc_send_message(chan, (void *)cmd);
      cmd = COMMAND_B;
      ipc_send_message(chan, (void *)cmd);
      cmd = COMMAND_C;
      ipc_send_message(chan, (void *)cmd);
}

The controller driver retrieves each message from the API and transmit as
       writel((u32) voidptr_cmd,  txreg);

How could it get any simpler ?


>>> It is knowledge intrinsic to a controller/mailbox. I really hope that
>>> there are no controllers where you have to poll for Rx too :)
>>>
>> No, not intrinsic to controller, but to the high level protocol.
>> Yes, I assume the RX to be always interrupt driven :)
>
> Until someone (out of their minds) comes up with it :)
>
OR someone smart tries to run some IPC stack over, say, gpio bitbanging ;)


>>>
>> As I said, among other advantages, TX buffering is needed to reduce
>> latencies. My platform's protocol isn't yet clear as to whether use
>> shared-memory (secure and non-secure versions) for not very large data
>> transfers or interrupt payload. So if we get good enough speed we
>> could save cost on dedicated memories.
>>
>> I wrote the omap2 controller driver code to convey my proposal better.
>> If you could please tell me how TX buffering is a problem for OMAP, it
>> will help me understand your concern better.
>
> It is not a problem for OMAP
>
Thanks for confirming that it's not a problem for OMAP.


>  The other thing is that you
> have defined 10 as the queue length in the core, this should be dictated
> by the controller or mailbox. What works for one platform may not work
> for some others (this is what you saw as different config options
> between OMAP and DBX500)
>
Please read the multi-line comment over that single line define.
The buffer is cheap, just a void*, so we could make it even 50.
However I am not hung on that.
It purely depends upon how the client uses the link, so it can't be
driven by the controller. We could make it a Kconfig option. What do
you suggest ?


>>>
>> How could the core perform any meaningful sanity check?  What if we
>> send/receive proper 'datalen' of garbage data?  What if the client
>> sends a "Give me info in not more than 32-bytes at a time" command to
>> the remote and the remote has valid info worth only 16 bytes?
>> IMHO there is not much for core to verify in a packet in transit. The
>> introduced checks are not worth it and actually limit some scenarios
>> like above example.
>
> OK, I had mainly two ideas, one telling the size of the void * on Tx,
> with the controller driver specifying max (and maybe min sizes expected)
>
No, please. The controller driver is supposed to be reusable over
various protocols. A protocol dictates the length of each logical TX
unit. The max-min limits set by the controller driver might work for
one but fail some other higher level protocol.

>
> The second (major reason) idea was driven by the kfifo implementation
> for buffering in core code for which I need the size field, so that the
> clients need not be intelligent about the status of its tx submission
> and maintaining its pointer (if you have different calling contexts). I
> guess both of us are coming from different perspectives here, you may
> find kfifos inefficient and I may find the complexity in client driver
> unnecessary for maintaining pointers. How about defining add and remove
> buffer ops in the controller driver so that it can choose its
> implementation, while we keep the overall flow architecture in the core
> code?
>
As I said the API shouldn't keep internal copies of a client's
requests - it will only kill zero-copy use-cases while adding
complexity to the core.

Since it already works fine for OMAP, I request we leave it as such
for now at least.


>>>> There are some highly programmable controllers that, if the driver is
>>>> proper, could change behavior runtime. For ex, if the controller
>>>> supports, a client might want to broadcast messages to multiple
>>>> remotes or listen for messages from more than one remote source or
>>>> both. The client could, say, specify bitmasks for such source/sink
>>>> remotes via cntlr_data while requesting the mailbox.  PL320 could work
>>>> in such mode if rest all fits.
>>>
>>> Are you configuring the specific mailbox or configuring the controller
>>> on a whole in this particular example?
>>>
>> The cntlr_data is to configure the link/mailbox, not the controller.
>
> then, can we rename this to 'link_data' or something that doesn't imply
> controller to avoid confusion? I guess you meant it as controller driver
> data rather than controller instance data, but the name is a bit misleading.
>
OK, I'll call it  'link_data'  :)


>>>
>>> Yeah, assumptions hold true until an unfortunate SoC comes up with it
>>> :). The TI AM3352 has one link that doesn't behave quite like the other
>>> (I am hoping to avoid using it), so I am ok with it for now. Guess we
>>> can always change it when a concrete need arises.
>>>
>> It would work right now :)   If your controller has 2 types of links,
>> the driver should register each bunch separately, each with its own
>> ipc_link_ops, with the core. The core can already take care of the
>> rest.
>
> Yeah, it can be done that way, but that's a not-so-elegant work-around
>
OTOH I find it elegant and not a "work around".
Liberally estimating, hardly 10% of IPC controllers would have 2
classes of physical links. Having link_ops per controller reduces the
number of ipc_link_ops structures 11:20 as compared to per link.


> IMHO. It's calling ipc_links_register twice on the same controller. Idea
> was that the API would distinguish different controllers, not the same
> one. Also, see the above example if you were to treat a link as Rx or Tx
> only (functional behavior differences even though the link is exactly
> the same type).
>
Why is calling ipc_links_register() twice, for a controller with 2
classes of links, a problem ?

And, No, the API need not know if the link is "RX" or "TX", which is
purely a logical function.

Please do tell me which controller physically limits its links to do
only "RX" or only "TX"?  It's just the platform's firmware that
dictates who sends and who receives on which link, thereby giving the
illusion of a link being a "RX" or "TX" capable only.
Even if some h/w limits do exist on links of some controller, still
the API shouldn't try to discern a "RX" from a "TX" link. When a
client knows which link to open, it will also know if it should read
or write to it - this assumption already holds true. If the client
writes on a link that it's supposed to listen to remote on, no amount
of policing by the API could help.

Even if the API tries to differentiate "RX" and "TX" links, the
knowledge must come from a client (it's driven by the protocol on the
platform), and not the controller because each of its links are
physically equally capable to do RX or TX on each end.


>> Yes, I have 2 types of controllers and I already thought about
>> multiple controllers in a platform.
>>  What do you expect to do in controller startup/shutdown? Since the
>> API works on individual links, not the controllers, when would it call
>> controller_start() and controller_shutdown()?  The ipc_link's
>> startup/shutdown are already non-atomic, if the controller needs any
>> setup it could do it in the first link's startup and teardown in the
>> last link's shutdown. Not to forget the resources lke IRQ are usually
>> per Link which should be acquired/released upon link's use/idle.
>>  While writing the OMAP2 controller driver, did I miss any controller
>> startup/shutdown ?
>
> It just delineates the code better, and has flexibility later on to
> extend any controller ops or exposing new controller-specific API. The
> controller start and stop will be called in the same function as
> ipc_request_channel.
>
Already one call ipc_link_ops.startup() reaches the controller upon
ipc_request_channel.

Do you mean ?
       ipc_con_ops.startup();
       ipc_link_ops.startup();

Why have 2 contiguous calls to the controller, to perform similar
functions?  Not to forget the API and clients don't work on IPC
controllers, but only on links. So it would be out-of-line for them to
have to worry about the controller.

>
> Yeah, the pm_runtime_enable cannot be called twice when mailbox is
> invoked from multiple clients on separate links, so there has to a
> controller-level logic/ref-counting for that. The clocking for us is on
> the controller.
>
No.  You could call pm_runtime_enable/disable any number of times as
long as they are balanced. The core does refcounting. Anyways, I am
not in favour of controller ops for other reasons mentioned above.

May I suggest, atm, we care only about things that don't work for OMAP
or STE. And leave the design issues for later when/if some real and
compelling enough need arises otherwise. I am afraid we are reaching
the point where this thread could be called, what Linus.T termed as,
"mental masxxxx"  :O

Regards,
-Jassi


From tomi.valkeinen at ti.com  Wed May  8 02:04:34 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 8 May 2013 09:04:34 +0300
Subject: [RESEND][PATCH 1/3] arm: dts: introduce config HAS_BANDGAP
In-Reply-To: <20130507190628.GI5634@blackmetal.musicnaut.iki.fi>
References: <1367874058-2378-1-git-send-email-eduardo.valentin@ti.com>
 <1367874058-2378-2-git-send-email-eduardo.valentin@ti.com>
 <20130506213413.GH5634@blackmetal.musicnaut.iki.fi>
 <20130506223653.GA12089@obsidianresearch.com> <51884971.9050508@ti.com>
 <20130507003651.GA26035@obsidianresearch.com> <5188FE54.6050200@ti.com>
 <20130507182711.GB28628@obsidianresearch.com>
 <20130507190628.GI5634@blackmetal.musicnaut.iki.fi>
Message-ID: <5189EAF2.5020406@ti.com>

On 07/05/13 22:06, Aaro Koskinen wrote:
> On Tue, May 07, 2013 at 12:27:11PM -0600, Jason Gunthorpe wrote:
>> On Tue, May 07, 2013 at 09:15:00AM -0400, Eduardo Valentin wrote:
>>>> But broadly the direction seems that drivers should have minimal
>>>> dependencies so, eg, the thermal maintainer compiling for x86 should
>>>> be able to compile test/static analyze your driver..
>>
>>> Well, I do not see much of this attempt actually. Do you have some link
>>> / evidene that shows someone who actually cares about compiling drivers
>>> for targets that they are not used for? On this specific driver, I
>>> actually have  had exactly the opposite advice [1]. I am not convinced
>>> people actually want to do that.
>>
>> There was a discussion a bit ago, but I can't find a link.. The
>> context was subsystem maintainers are being asked to look after more
>> code with the DT transition moving things out of arch/arm and at least
>> one complained they couldn't even compile test on x86... But again, I
>> can't find a link and you are right, there are lots and lots of
>> 'depends ARCH..' style things in kConfig already.
>>
>> Lets just call it something to think about.
> 
> Tomi started a thread related to this recently:
> 
> 	http://marc.info/?l=linux-kernel&m=136731558332265&w=2
> 
> I think there's some good reasons listed there, but I guess up to the
> subsystem maintainers to decide what they prefer.

As Sam pointed out in that thread, there's no need to change the Kconfig
language for this. I did some testing with fb drivers, by having a
CONFIG_ALL_FB_DRIVERS option which "removes" the arch dependencies for
some fb drivers.

It does uglify the Kconfig files a bit:

-       depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
+       depends on FB && (SUPERH || ARCH_SHMOBILE || ALL_FB_DRIVERS) &&
HAVE_CLK

I'm still undecided if I want to pursue this with fb drivers, as it
seems that quite many of them do really depend on the arch code, and I'm
not interested in trying to fix them.

But if other subsystems would benefit of this also, perhaps we could
have a common CONFIG entry that would allow compiling a driver on any
arch. I just can't think of a good name for the config entry =).

 Tomi


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From dim at ch-martigues.fr  Wed May  8 01:55:51 2013
From: dim at ch-martigues.fr (=?windows-1251?B?zuvl4yDC6+Dk6Ozo8O7i6PcgIA==?=)
Date: Wed, 8 May 2013 08:55:51 +0300
Subject: =?windows-1251?B?7eDk7uHt+yDt4Ovo9+3u8fLo?=
Message-ID: <35E499D58DFF4FFFB151454E20A678F7@ujhvc>

Andy

  ????: http://bit.ly/16Hnlvo ??? ????????????? ??? ?????????? ???????????? ?? ????????? ? ????????????? ?????????? ????????? ?? ?????????? ? ?? ????? ????! ?? ????????? ??? ???????????????? ??? ???????? ??????! ? ?? ?????, ????? ???? ?? ????? ????? ??????? ? ???????? ??????, ???????? ???????? ??? ???????? ?? 1? ?????????. ?? ?????????? ?????? ???????? ???????? ?????????? ?????, ????? ??????? ? ????? ?????! 
 


From tomi.valkeinen at ti.com  Wed May  8 02:56:08 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 8 May 2013 09:56:08 +0300
Subject: [PATCHv2 0/2] Add support for the Solomon SSD1306 OLED Controller
In-Reply-To: <1366624555-5616-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1366624555-5616-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <5189F708.1040508@ti.com>

On 22/04/13 12:55, Maxime Ripard wrote:
> Hi,
> 
> This patchset adds the needed bits to the ssd1307fb driver to support the
> very similar Solomon SSD1306 controller.
> 
> Since the SSD1307 has been replaced by the SSD1306 in the latest CFA-10036
> production samples, we also need to change the device tree accordingly.
> 
> Thanks,
> Maxime
> 
> Changes from v1:
>   - Fix style errors
> 
> Maxime Ripard (2):
>   video: ssd1307fb: Add support for SSD1306 OLED controller
>   ARM: dts: cfa10036: Change the OLED display to SSD1306
> 
>  .../devicetree/bindings/video/ssd1307fb.txt        |   10 +-
>  arch/arm/boot/dts/imx28-cfa10036.dts               |   14 +-
>  arch/arm/boot/dts/imx28-cfa10049.dts               |    4 +-
>  drivers/video/ssd1307fb.c                          |  273 +++++++++++++++-----
>  4 files changed, 216 insertions(+), 85 deletions(-)

I've taken the first patch, "video: ssd1307fb: Add support for SSD1306
OLED controller" into fbdev 3.11 branch. The dts changes should
preferably go through arch tree.

 Tomi



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From tomi.valkeinen at iki.fi  Wed May  8 02:57:24 2013
From: tomi.valkeinen at iki.fi (Tomi Valkeinen)
Date: Wed, 08 May 2013 09:57:24 +0300
Subject: [PATCH 0/4] drivers: video: Optimisations for the ssd1307fb driver
In-Reply-To: <1366624945-5708-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1366624945-5708-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <5189F754.1030402@iki.fi>

On 22/04/13 13:02, Maxime Ripard wrote:
> Hi everyone,
> 
> This is a patchset to improve significantly (by an order of magnitude)
> the refreshing time of the SSD1306 and SSD1307.
> 
> We do so by sending the pixels by batches, instead of 8 at a time,
> combined with some additionnal features found on these controllers
> that allows to send a whole screen content at once.
> 
> This obviously removes the tearing effect that was previously seen
> with these controllers.
> 
> This patchset depends on the "Add support for the Solomon SSD1306 OLED
> Controller" I sent previously.
> 
> Thanks,
> Maxime
> 
> Maxime Ripard (4):
>   ARM: cfa10036: dt: Change i2c0 clock frequency
>   ssd1307fb: Rework the communication functions
>   ssd1307fb: Speed up the communication with the controller
>   ssd1307fb: Make use of horizontal addressing mode
> 
>  arch/arm/boot/dts/imx28-cfa10036.dts |    1 +
>  drivers/video/ssd1307fb.c            |  123 ++++++++++++++++++++++++----------
>  2 files changed, 89 insertions(+), 35 deletions(-)
> 

I've taken the patches 2-4 into fbdev 3.11 branch. The first patch "ARM:
cfa10036: dt: Change i2c0 clock frequency" should preferably go through
arch tree.

 Tomi



From hvaibhav at ti.com  Wed May  8 02:58:33 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 8 May 2013 12:28:33 +0530
Subject: [PATCH] ARM: OMAP3+: am33xx id: Add new am33xx specific function to
 check dev_feature
Message-ID: <1367996313-6676-1-git-send-email-hvaibhav@ti.com>

Layout of DEV_FEATURE register (offset = 0x604) is different
between TI81xx and AM33xx device, so create separate function
which will check for features available on specific AM33xx SoC
and set the flags accordingly.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
---
 arch/arm/mach-omap2/control.h |    5 +++++
 arch/arm/mach-omap2/id.c      |   13 +++++++++++++
 arch/arm/mach-omap2/io.c      |    2 +-
 arch/arm/mach-omap2/soc.h     |    1 +
 4 files changed, 20 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c3281..4acdfc5 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,11 @@
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)
 
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE		0x604
+#define AM33XX_SGX_SHIFT		29
+#define AM33XX_SGX_MASK			(1 << AM33XX_SGX_SHIFT)
+
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS	0x044c
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9bc5a18..02feef7 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -302,6 +302,19 @@ void __init ti81xx_check_features(void)
 	omap3_cpuinfo();
 }
 
+void __init am33xx_check_features(void)
+{
+	u32 status;
+
+	omap_features = OMAP3_HAS_NEON;
+
+	status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+	if (status & AM33XX_SGX_MASK)
+		omap_features |= OMAP3_HAS_SGX;
+
+	omap3_cpuinfo();
+}
+
 void __init omap3xxx_check_revision(void)
 {
 	const char *cpu_rev;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..06a8946 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -576,7 +576,7 @@ void __init am33xx_init_early(void)
 	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
 	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
 	omap3xxx_check_revision();
-	ti81xx_check_features();
+	am33xx_check_features();
 	am33xx_voltagedomains_init();
 	am33xx_powerdomains_init();
 	am33xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index ccef2dd..7d8722c 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -424,6 +424,7 @@ void omap4xxx_check_revision(void);
 void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
+void am33xx_check_features(void);
 void omap4xxx_check_features(void);
 
 /*
-- 
1.7.0.4



From valentin.longchamp at keymile.com  Wed May  8 03:04:32 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Wed, 08 May 2013 09:04:32 +0200
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood
 variants
In-Reply-To: <51892D8D.4060704@gmail.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
 <518927C0.6070600@free-electrons.com> <51892D8D.4060704@gmail.com>
Message-ID: <5189F900.6020809@keymile.com>

On 05/07/2013 06:36 PM, Sebastian Hesselbarth wrote:
> On 05/07/2013 06:11 PM, Gregory CLEMENT wrote:
>> On 05/07/2013 05:52 PM, Valentin Longchamp wrote:
>>> The kirkwood device found in the Prestera SoCs does not have all the
>>> peripherals of its the usual kirkwood SoCs. There are hence missing
>>> clocks in the SoCs.
>>>
>>> This patch registers another gate controller for the kirkwood that
>>> registers only the available clocks of this kirkwood variant.
>>
>> Hi Valentin,
>>
>> Overall the patch set looks OK, however I don't understand why you need
>> to declare a new gate controller. The list you delcared seemed to be
>> just a subset of the Kirkwood one, why can't you use this one?
>>
>> Note that I am not an expert for the kirkwood hardware, so maybe I
>> missed something.
> 
> I just checked my mails from late 2012 and there Valentin and I agreed,
> that not the missing bits in clock gating control registers was the root
> cause of km_kirkwood to hang. It was rather the phy gates (that do not/
> not yet exist on DT) that caused it to hang, i.e. when accessing SATA
> PHY registers.

Yeah you are right, I had forgotten about this test. I just had a look at the
board-km_kirkwood.c and I tried to figure out a way to make sure the clock gates
bits never get read/written, so never get initialized. But as you say, that's
not the real cause of the hang but

> 
> Valentin, I am not against an extra clock-gating-ctrl for Prestera but
> maybe having an kirkwood.dtsi fork without SATA and other peripherals
> will also help?

Since it's not the real problem having the extra clock-gating-ctrl would me more
consistent with the real Prestera HW, but maybe it's better to keep only one
that works for both as it's already the case, it's less code to maintain.

A better approach would be to work on the kirkwood.dtsi as you mention it. The
SATA node in kirkwood.dtsi is by default disabled, is this enough or should it
be moved to kirkwood-6281.dtsi for instance ?

> 
> And: Does DT-enabled km_kirkwood ever hang without the hack in it's
> board setup? There should be no PHY gates on DT boards..
> 

I have just tested it and it does not hang, so I will submit and patch that
simply removes this workaround since the PHY gates are not accessed anymore
(thanks to DT clock gates and that km_kirkwood does not enable the sata of node).

Valentin



From matthijs at stdin.nl  Wed May  8 03:11:37 2013
From: matthijs at stdin.nl (Matthijs Kooijman)
Date: Wed, 8 May 2013 09:11:37 +0200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
Message-ID: <20130508071137.GM25742@login.drsnuggles.stderr.nl>

Hi folks,

I also bumped into the question of how to set the dma_mask when enabling
the dwc2 driver on the ramips target and found there didn't seem to be
any clear way to get a dma_mask.

It seems to me that in the pre-DT era, a platform_device would get a
dma_mask when it was defined in the board / soc code, which makes sense
since that code knows if a dma_mask is required and what its value
should be (it seems to me that a driver can only know it needs a
dma_mask, but not what value it should have?).

> > This probably could be initialized from some DT property. However,
> > there's no such property defined right now, and considering that DT is
> > supposed to be an ABI, we'd always need the code in this patch as a
> > fallback for DTs that were created before any such property was defined.
It seems there has already been a patch to implement this. For
reference, this seems to be the most recent version:

https://lkml.org/lkml/2012/12/4/54

And here's the previous attempt, to which Rob Herring refers in a reply.

https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-March/013180.html

> > Equally, since the data is SoC-specific rather than board-specific, and
> > is even fairly unlikely to vary between SoC versions since these values
> > are all 0xffffffff anyway, I don't really see much point in putting it
> > into DT, rather than just putting the static data into the driver.
>
> I mean there is already dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
> at function of_platform_device_create, why can't add
> dev->dev.dma_mask = &dev->dev.coherent_dma_mask after that?
Perhaps it would sense to set the 32-bit mask as a default, but allow to
override this mask from the devicetree for boards that need another
value? Or perhaps override it from the soc code instead?

For the ramips target, the MIPS folks suggested another approach: The
soc code finds the platform_device generated by DT and adds the
dma_mask:

http://www.linux-mips.org/archives/linux-mips/2013-04/msg00162.html

> If DT core can do above things, can we delete dma_mask assignment
> at every driver?
That would seem like a likeably goal to me :-)


Gr.

Matthijs


From sebastian.hesselbarth at gmail.com  Wed May  8 03:21:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 08 May 2013 09:21:40 +0200
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood
 variants
In-Reply-To: <5189F900.6020809@keymile.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
 <518927C0.6070600@free-electrons.com> <51892D8D.4060704@gmail.com>
 <5189F900.6020809@keymile.com>
Message-ID: <5189FD04.8090308@gmail.com>

On 05/08/2013 09:04 AM, Valentin Longchamp wrote:
> On 05/07/2013 06:36 PM, Sebastian Hesselbarth wrote:
>> I just checked my mails from late 2012 and there Valentin and I agreed,
>> that not the missing bits in clock gating control registers was the root
>> cause of km_kirkwood to hang. It was rather the phy gates (that do not/
>> not yet exist on DT) that caused it to hang, i.e. when accessing SATA
>> PHY registers.
>
> Yeah you are right, I had forgotten about this test. I just had a look at the
> board-km_kirkwood.c and I tried to figure out a way to make sure the clock gates
> bits never get read/written, so never get initialized. But as you say, that's
> not the real cause of the hang but
>
>> Valentin, I am not against an extra clock-gating-ctrl for Prestera but
>> maybe having an kirkwood.dtsi fork without SATA and other peripherals
>> will also help?
>
> Since it's not the real problem having the extra clock-gating-ctrl would me more
> consistent with the real Prestera HW, but maybe it's better to keep only one
> that works for both as it's already the case, it's less code to maintain.
>
> A better approach would be to work on the kirkwood.dtsi as you mention it. The
> SATA node in kirkwood.dtsi is by default disabled, is this enough or should it
> be moved to kirkwood-6281.dtsi for instance ?

Valentin,

I guess for the long run, we will re-introduce phy gates either by
abusing clk gates or some other way. But they will depend on existing
OF nodes.

Considering this, it would be best to fork kirkwood.dtsi for Prestera
and leave out all OF nodes that are not implemented there. We could
have

kirkwood.dtsi -+-> kirkwood-kirkwood.dtsi -+-> kirkwood-6281.dtsi
                +-> kirkwood-prestera.dtsi  +-> kirkwood-6282.dtsi

or any other naming scheme. Maybe Andrew or Jason can comment on this.

>> And: Does DT-enabled km_kirkwood ever hang without the hack in it's
>> board setup? There should be no PHY gates on DT boards..
>
> I have just tested it and it does not hang, so I will submit and patch that
> simply removes this workaround since the PHY gates are not accessed anymore
> (thanks to DT clock gates and that km_kirkwood does not enable the sata of node).

Great! I suggest to also submit the dtsi changes above within the same
patch set.

Sebastian


From arnd at arndb.de  Wed May  8 03:24:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 09:24:44 +0200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
Message-ID: <201305080924.44622.arnd@arndb.de>

On Wednesday 08 May 2013, Peter Chen wrote:
> >
> > This probably could be initialized from some DT property. However,
> > there's no such property defined right now, and considering that DT is
> > supposed to be an ABI, we'd always need the code in this patch as a
> > fallback for DTs that were created before any such property was defined.
> >
> > Equally, since the data is SoC-specific rather than board-specific, and
> > is even fairly unlikely to vary between SoC versions since these values
> > are all 0xffffffff anyway, I don't really see much point in putting it
> > into DT, rather than just putting the static data into the driver.
> 
> I mean there is already dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
> at function of_platform_device_create, why can't add
> dev->dev.dma_mask = &dev->dev.coherent_dma_mask after that?
> 
> If DT core can do above things, can we delete dma_mask assignment
> at every driver?

It probably should. The main thing is that the dma_mask setting in
of_platform (and elsewhere) is a mess and that nobody so far had the
guts to try to get it right for good.

Setting a 32 bit DMA mask is /probably/ the right default on all
ARM systems, but there are caveats:

- Once you get to systems with larger than 32 bit addressing (powerpc64,
  arm64, arm32 with LPAE), it's not so obvious: you may have some devices
  that need a 32 bit mask and some that need a 64 bit mask.

- Some (very rare these days, thankfully) devices require a mask that is
  less than 32 bits. Since that knowledge is device specific, not platform
  specific, it should probably stay in the driver.

- There are cases (I know them only on powerpc, but they probably exist
  on ARM and other places too) where the mapping from bus addresses to
  physical addresses is not linear. There is a device-tree binding for
  a "dma-ranges" property that can accurately describe the specific
  mapping. Actually using this on architecture independent code requires
  not only setting the dma_mask but also supporting the remapping
  in the dma_map_ops.

- Things get more interesting in combination with an IOMMU. If we have
  an IOMMU, I think we should set the dma_mask pointer to the mask of
  the IOMMU and set the map_ops accordingly.

- Whether we actually need coherent_dma_mask these days is another hard
  question to answer. I suspect that the only thing really needing it
  was some version of the Itanium based Altix machine for its PCI
  devices and we'd be better off finding a simpler solution for platform
  devices. For all practical purposes I think coherent_dma_mask must be
  the same as dma_mask.

	Arnd


From B35083 at freescale.com  Wed May  8 03:26:04 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Wed, 8 May 2013 07:26:04 +0000
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <20130503074105.GA31873@S2101-09.ap.freescale.net>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
 <20130503074105.GA31873@S2101-09.ap.freescale.net>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851B455F@039-SN1MPN1-003.039d.mgd.msft.net>

>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo at linaro.org]
>Sent: Friday, May 03, 2013 3:41 PM
>To: Lu Jingchang-B35083
>Cc: linux-arm-kernel at lists.infradead.org; s.hauer at pengutronix.de
>Subject: Re: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
>
>> --git a/arch/arm/mach-imx/mach-mvf600.c
>> b/arch/arm/mach-imx/mach-mvf600.c new file mode 100644 index
>> 0000000..56d3fb0
>> --- /dev/null
>> +++ b/arch/arm/mach-imx/mach-mvf600.c
>> @@ -0,0 +1,118 @@
>> +/*
>> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> +modify
>> + * it under the terms of the GNU General Public License as published
>> +by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +
>> +#include <linux/types.h>
>> +#include <linux/sched.h>
>> +#include <linux/delay.h>
>> +#include <linux/pm.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/irq.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/init.h>
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clocksource.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/irqchip.h>
>> +#include <linux/irqchip/arm-gic.h>
>> +#include <asm/memory.h>
>> +#include <asm/irq.h>
>> +#include <asm/setup.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <asm/mach/time.h>
>> +#include <asm/hardware/cache-l2x0.h>
>> +#include <asm/system_misc.h>
>
>Please check if you really need all these headers.
>
>> +
>> +#include "common.h"
>> +
>> +
>> +void mvf_restart(char mode, const char *cmd) {
>> +	struct device_node *np;
>> +	void __iomem *wdog_base;
>> +	struct clk *wdog_clk;
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt");
>> +	wdog_base = of_iomap(np, 0);
>> +	if (!wdog_base)
>> +		goto soft;
>> +
>> +	wdog_clk = of_clk_get_by_name(np, "wdog");
>> +	if (!IS_ERR(wdog_clk))
>> +		clk_prepare_enable(wdog_clk);
>> +
>> +	/* enable wdog */
>> +	writew_relaxed(1 << 2, wdog_base);
>> +
>> +	/* wait for reset to assert ... */
>> +	mdelay(500);
>> +
>> +	pr_err("Watchdog reset failed to assert reset\n");
>> +
>> +	/* delay to allow the serial port to show the message */
>> +	mdelay(50);
>> +
>> +soft:
>> +	/* we'll take a jump through zero as a poor second */
>> +	soft_restart(0);
>> +}
>
>If mvf600 uses the same wdt IP block as imx, we should make this restart
>routine a common function to be used on mvf600, imx6q and imx6sl etc.
>
[Lu Jingchang-B35083] 
    Do you have plan to update the mxc_restart() function in system.c? We once used that common function for mvf600. But now this function cannot be used for mvf600 as the new clock framwork used.
    On the other hand, even we udpated the clk_get for the the common mxc_restart() funciton. different with i.MX6, the MVF600 need to enable the clock before using the wdt module, we still need some clue code for i.mx and mvf600. So I suggest keep the restart function for mvf600 currently. Thanks.



From matthijs at stdin.nl  Wed May  8 03:28:25 2013
From: matthijs at stdin.nl (Matthijs Kooijman)
Date: Wed, 8 May 2013 09:28:25 +0200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <20130508071137.GM25742@login.drsnuggles.stderr.nl>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
 <20130508071137.GM25742@login.drsnuggles.stderr.nl>
Message-ID: <20130508072825.GO25742@login.drsnuggles.stderr.nl>

Hi,

> For the ramips target, the MIPS folks suggested another approach: The
> soc code finds the platform_device generated by DT and adds the
> dma_mask:
> 
> http://www.linux-mips.org/archives/linux-mips/2013-04/msg00162.html

For completeness: It seems this approach is not going to be used after
all. The approach (not this particular patch) was conceived to get ehci
support on ramips, but now that echi also sets a default mask and it
turns out that the other setup needed is best done through a phy device,
this approach is probably not needed anymore for ehci. For dwc2, I guess
it should also set up a dma_mask like ehci does (at least until we sort
out this thread) :-)

Gr.

Matthijs


From u.kleine-koenig at pengutronix.de  Wed May  8 03:33:11 2013
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed,  8 May 2013 09:33:11 +0200
Subject: [PATCH] ARM: imx: fix build breakage in hotplug.c
Message-ID: <1367998391-12801-1-git-send-email-u.kleine-koenig@pengutronix.de>

Since commit bca7a5a (ARM: cpu hotplug: remove majority of cache
flushing from platforms) hotplug.c fails to compile (e.g. with
imx_v6_v7_defconfig) with:

	arch/arm/mach-imx/common.h:100:29: warning: 'struct pt_regs' declared inside parameter list [enabled by default]
	arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_die':
	arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function 'cpu_do_idle' [-Werror=implicit-function-declaration]
	arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_kill':
	arch/arm/mach-imx/hotplug.c:58:26: error: 'jiffies' undeclared (first use in this function)
	arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
	arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function 'msecs_to_jiffies' [-Werror=implicit-function-declaration]
	arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function 'time_after' [-Werror=implicit-function-declaration]
	cc1: some warnings being treated as errors

Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Hello Russell,

This patch applies on top of Linus' or your master branch.

Best regards
Uwe

 arch/arm/mach-imx/common.h  | 2 ++
 arch/arm/mach-imx/hotplug.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5bf4a97..5241d99b 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -96,6 +96,8 @@ enum mx3_cpu_pwr_mode {
 extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
+struct pt_regs;
+
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
 
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 5e91112..3daf1ed 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -11,7 +11,9 @@
  */
 
 #include <linux/errno.h>
+#include <linux/jiffies.h>
 #include <asm/cp15.h>
+#include <asm/proc-fns.h>
 
 #include "common.h"
 
-- 
1.8.2.rc2



From u.kleine-koenig at pengutronix.de  Wed May  8 03:48:10 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 8 May 2013 09:48:10 +0200
Subject: [PATCH] ARM: imx: compile fix for hotplug.c
In-Reply-To: <1367474331-3479-1-git-send-email-shawn.guo@linaro.org>
References: <1367474331-3479-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130508074810.GN23285@pengutronix.de>

Hello Shawn,

On Thu, May 02, 2013 at 01:58:51PM +0800, Shawn Guo wrote:
> Commit bca7a5a (ARM: cpu hotplug: remove majority of cache flushing
> from platforms) removes include of <asm/cacheflush.h> and hence
> discovers a few indirect inclusion and declaration problems as below.
> 
>   CC      arch/arm/mach-imx/hotplug.o
> In file included from arch/arm/mach-imx/hotplug.c:16:0:
> arch/arm/mach-imx/common.h:100:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
> arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
> arch/arm/mach-imx/common.h:101:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
> arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_die?:
> arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ?cpu_do_idle? [-Werror=implicit-function-declaration]
> arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_kill?:
> arch/arm/mach-imx/hotplug.c:58:26: error: ?jiffies? undeclared (first use in this function)
> arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
> arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ?msecs_to_jiffies? [-Werror=implicit-function-declaration]
> arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ?time_after? [-Werror=implicit-function-declaration]
> 
> Fix them by adding the needed inclusion and declaration.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
I just sent an equivalent patch for that issue (so:
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
).

Is this patch already queued somewhere?

Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Wed May  8 03:49:20 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 8 May 2013 09:49:20 +0200
Subject: [PATCH] ARM: imx: fix build breakage in hotplug.c
In-Reply-To: <1367998391-12801-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1367998391-12801-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20130508074920.GO23285@pengutronix.de>

Hello,

On Wed, May 08, 2013 at 09:33:11AM +0200, Uwe Kleine-K?nig wrote:
> Since commit bca7a5a (ARM: cpu hotplug: remove majority of cache
> flushing from platforms) hotplug.c fails to compile (e.g. with
> imx_v6_v7_defconfig) with:
> 
> 	arch/arm/mach-imx/common.h:100:29: warning: 'struct pt_regs' declared inside parameter list [enabled by default]
> 	arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_die':
> 	arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function 'cpu_do_idle' [-Werror=implicit-function-declaration]
> 	arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_kill':
> 	arch/arm/mach-imx/hotplug.c:58:26: error: 'jiffies' undeclared (first use in this function)
> 	arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
> 	arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function 'msecs_to_jiffies' [-Werror=implicit-function-declaration]
> 	arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function 'time_after' [-Werror=implicit-function-declaration]
> 	cc1: some warnings being treated as errors
> 
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> Hello Russell,
> 
> This patch applies on top of Linus' or your master branch.
> 
> Best regards
> Uwe
> 
>  arch/arm/mach-imx/common.h  | 2 ++
>  arch/arm/mach-imx/hotplug.c | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index 5bf4a97..5241d99b 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -96,6 +96,8 @@ enum mx3_cpu_pwr_mode {
>  extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
>  extern void imx_print_silicon_rev(const char *cpu, int srev);
>  
> +struct pt_regs;
> +
>  void avic_handle_irq(struct pt_regs *);
>  void tzic_handle_irq(struct pt_regs *);
>  
> diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
> index 5e91112..3daf1ed 100644
> --- a/arch/arm/mach-imx/hotplug.c
> +++ b/arch/arm/mach-imx/hotplug.c
> @@ -11,7 +11,9 @@
>   */
>  
>  #include <linux/errno.h>
> +#include <linux/jiffies.h>
>  #include <asm/cp15.h>
> +#include <asm/proc-fns.h>
>  
>  #include "common.h"
I just noticed that this patch was already posted by Shawn last week[1].

[1] http://www.spinics.net/lists/arm-kernel/msg241316.html

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From will.deacon at arm.com  Wed May  8 04:57:53 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 09:57:53 +0100
Subject: [PATCHv3] arm: Preserve the user r/w register TPIDRURW on
 context switch and fork
In-Reply-To: <51896934.5080803@dawncrow.de>
References: <51896934.5080803@dawncrow.de>
Message-ID: <20130508085753.GA15568@mudshark.cambridge.arm.com>

Hi Andre,

On Tue, May 07, 2013 at 09:51:00PM +0100, Andr? Hentschel wrote:
> From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>

Might just be my mailer, but you should check that your name is intact here
otherwise the git log will be mangled.

> Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
> prevent it from being used as a covert channel between two tasks.
> 
> There are more and more applications coming to WinRT, Wine could support them,
> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
> 
> This patch preserves that register per thread instead of clearing it.
> Unlike the TPIDRURO, which is already switched, the TPIDRURW
> can be updated from userspace so needs careful treatment in the case that we
> modify TPIDRURW and call fork(). To avoid this we must always read
> TPIDRURW in copy_thread.
> 
> Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com> 

[...]

> diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
> index 73409e6..22756ab 100644
> --- a/arch/arm/include/asm/tls.h
> +++ b/arch/arm/include/asm/tls.h
> @@ -2,27 +2,30 @@
>  #define __ASMARM_TLS_H
>  
>  #ifdef __ASSEMBLY__
> -	.macro set_tls_none, tp, tmp1, tmp2
> +#include <asm/asm-offsets.h>
> +	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
>  	.endm
>  
> -	.macro set_tls_v6k, tp, tmp1, tmp2
> +	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
> +	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
>  	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
> -	mov	\tmp1, #0
> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
> +	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
> +	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it

Why is this conditional?

>  	.endm
>  
> -	.macro set_tls_v6, tp, tmp1, tmp2
> +	.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
>  	ldr	\tmp1, =elf_hwcap
>  	ldr	\tmp1, [\tmp1, #0]
>  	mov	\tmp2, #0xffff0fff
>  	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
> -	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> -	movne	\tmp1, #0
> -	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
>  	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> +	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
> +	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> +	mcrne	p15, 0, \tpuser, c13, c0, 2	@ set user r/w register
> +	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
>  	.endm
>  
> -	.macro set_tls_software, tp, tmp1, tmp2
> +	.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
>  	mov	\tmp1, #0xffff0fff
>  	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
>  	.endm
> @@ -31,19 +34,31 @@
>  #ifdef CONFIG_TLS_REG_EMUL
>  #define tls_emu		1
>  #define has_tls_reg		1
> -#define set_tls		set_tls_none
> +#define switch_tls	switch_tls_none
>  #elif defined(CONFIG_CPU_V6)
>  #define tls_emu		0
>  #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
> -#define set_tls		set_tls_v6
> +#define switch_tls	switch_tls_v6
>  #elif defined(CONFIG_CPU_32v6K)
>  #define tls_emu		0
>  #define has_tls_reg		1
> -#define set_tls		set_tls_v6k
> +#define switch_tls	switch_tls_v6k
>  #else
>  #define tls_emu		0
>  #define has_tls_reg		0
> -#define set_tls		set_tls_software
> +#define switch_tls	switch_tls_software
>  #endif
>  
> +#ifndef __ASSEMBLY__
> +static inline unsigned long get_tlsuser(void)
> +{
> +	if (has_tls_reg && !tls_emu)
> +	{
> +		unsigned long t;
> +		__asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (t));
> +		return t;
> +	}
> +	return 0;

This isn't standard kernel coding style. Please do something like:

	static inline unsigned long get_tlsuser(void)
	{
		unsigned long reg = 0;

		if (has_tls_reg && !tls_emu)
			asm("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));

		return reg;
	}

Will


From will.deacon at arm.com  Wed May  8 05:06:44 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 10:06:44 +0100
Subject: [RFC PATCH 0/2] ARM: Remove any correlation between IPC and
 BogoMips value
In-Reply-To: <5189224A.70501@codeaurora.org>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <5187EFF3.6010005@codeaurora.org>
 <20130507090849.GC25387@mudshark.cambridge.arm.com>
 <5189224A.70501@codeaurora.org>
Message-ID: <20130508090644.GA15692@mudshark.cambridge.arm.com>

Hello Christopher,

On Tue, May 07, 2013 at 04:48:26PM +0100, Christopher Covington wrote:
> On 05/07/2013 05:08 AM, Will Deacon wrote:
> > That seems like a lot of effort in order to preserve something that isn't
> > even meaningful. We might be better just zeroing the value, but then we'll
> > inevitably get bug reports of it being `wrong'.
> 
> If I were in to filing bug reports about bogomips values, I would be just as
> likely to do it for 1, 10000, 99999, and get_random_bytes(...) as for 0.

That's a fair point, and one of the reasons I posted this as an RFC. I'd
basically like an `obviously bogus' value so that people don't think `hey,
my CPU sure it slow' and instead think `looks like this really is a bogus
value after all'.

However, you're probably right that there isn't a number which can convey
that information properly, so how about we just put a string in there along
the lines of "not reported" and leave it at that?

Will


From fabio.baltieri at linaro.org  Wed May  8 05:09:53 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Wed,  8 May 2013 11:09:53 +0200
Subject: [PATCH] ARM: ux500: update MSP1 pinctrl defintions
Message-ID: <1368004193-21213-1-git-send-email-fabio.baltieri@linaro.org>

Update MSP1 pinctrl definitions in mop500_family_pinmap by removing
sleep state and setting default ones as pin hogs, as those are used by
both ux500-msp-i2s.1 and ux500-msp-i2s.3.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-pins.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 947bd9e..3f92308 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -174,17 +174,12 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 	DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
 	DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
 	/* MSP1 for ALSA codec */
-	DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
-	DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
-	DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
-	DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-	DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-	DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-	/* MSP1 sleep state */
-	DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
-	DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-	DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-	DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
+	DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
+	DB8500_MUX_HOG("msp1_a_1", "msp1"),
+	DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
+	DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
+	DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
+	DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
 	/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
 	DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
 	DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
-- 
1.8.2



From pdeschrijver at nvidia.com  Wed May  8 05:40:04 2013
From: pdeschrijver at nvidia.com (Peter De Schrijver)
Date: Wed, 8 May 2013 12:40:04 +0300
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <518915A7.1020105@wwwdotorg.org>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
 <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>
 <20130507130850.GA11202@avionic-0098.adnet.avionic-design.de>
 <518915A7.1020105@wwwdotorg.org>
Message-ID: <20130508094004.GL7949@tbergstrom-lnx.Nvidia.com>

On Tue, May 07, 2013 at 04:54:31PM +0200, Stephen Warren wrote:
> On 05/07/2013 07:08 AM, Thierry Reding wrote:
> > On Tue, May 07, 2013 at 03:48:49PM +0300, Peter De Schrijver
> > wrote:
> >> On Mon, May 06, 2013 at 10:39:04PM +0200, Stephen Warren wrote:
> >>> From: Stephen Warren <swarren at nvidia.com>
> >>> 
> >>> Tegra20 HW appears to have a bug such that PCIe device
> >>> interrupts, whether they are legacy IRQs or MSI, are lost when
> >>> LP2 is enabled. To work around this, simply disable LP2 if the
> >>> PCI driver and DT node are both enabled.
> >>> 
> >> 
> >> Wouldn't it make more sense to disable LP2 when we actually
> >> detect a PCIe device?
> 
> I did consider that, but rejected the idea for the reasons Thierry
> mentioned.
> 
> > I'm not sure a patch to do so would be as simple as this one. For
> > one, the cpuidle framework will already have been initialized when
> > PCIe enumeration completes. So some way of permanently disabling
> > one state at runtime would be required and I don't think cpuidle
> > provides an API to do so. I know the latter isn't really a good
> > reason, but I don't think adding that kind of API just because
> > Tegra20 seems to have a bug would be appropriate.
> 
> There is a way to do this, since it can be done via sysfs, but I don't
> think it's exposed as an API from cpuidle. I agree it seems a little
> silly to expose it just to support this HW bug though.
> 
> > Furthermore, it is quite likely that the PCIe controller will only
> > be enabled in DT for devices that actually have a PCIe device
> > hooked up.
> 

That's not always true though. Eg Harmony has a miniPCIe slot, so it should be
listed in DT, but there is not necessarily a card present in the slot.

Cheers,

Peter.


From m.szyprowski at samsung.com  Wed May  8 05:44:02 2013
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 08 May 2013 11:44:02 +0200
Subject: DMA mapping API abuse in exynos-drm
In-Reply-To: <CAAQKjZONxDcHzKD3V+sJcM1+mSwqKg+y0Ak9g0ip0P4H937P6Q@mail.gmail.com>
References: <2146981.l1bUpBI0CH@flatron>
 <CAAQKjZONxDcHzKD3V+sJcM1+mSwqKg+y0Ak9g0ip0P4H937P6Q@mail.gmail.com>
Message-ID: <518A1E62.6070109@samsung.com>

Hello,

On 5/6/2013 7:59 AM, Inki Dae wrote:
> 2013/5/5 Tomasz Figa <tomasz.figa at gmail.com 
> <mailto:tomasz.figa at gmail.com>>
>
>     Hi,
>
>     Recently I've been working a bit on a DRM driver for the GPU of
>     Samsung
>     S3C6410 SoCs, which required me to familiarize a bit with
>     exynos-drm, as
>     it already contains a KMS driver which is compatible with the SoC I'm
>     working with, making it a good place to put my driver in.
>
>     Reading through exynos_drm_buf.c I stumbled across following (a
>     bit long)
>     piece of code:
>
>             dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &buf->dma_attrs);
>
>             nr_pages = buf->size >> PAGE_SHIFT;
>
>             if (!is_drm_iommu_supported(dev)) {
>                     dma_addr_t start_addr;
>                     unsigned int i = 0;
>
>                     buf->pages = kzalloc(sizeof(struct page) * nr_pages,
>                                             GFP_KERNEL);
>                     if (!buf->pages) {
>                             DRM_ERROR("failed to allocate pages.\n");
>                             return -ENOMEM;
>                     }
>
>                     buf->kvaddr = dma_alloc_attrs(dev->dev, buf->size,
>     &buf->dma_addr, GFP_KERNEL,
>     &buf->dma_attrs);
>                     if (!buf->kvaddr) {
>                             DRM_ERROR("failed to allocate buffer.\n");
>                             kfree(buf->pages);
>                             return -ENOMEM;
>                     }
>
>                     start_addr = buf->dma_addr;
>                     while (i < nr_pages) {
>                             buf->pages[i] = phys_to_page(start_addr);
>                             start_addr += PAGE_SIZE;
>                             i++;
>                     }
>             } else {
>
>                     buf->pages = dma_alloc_attrs(dev->dev, buf->size,
>     &buf->dma_addr, GFP_KERNEL,
>     &buf->dma_attrs);
>                     if (!buf->pages) {
>                             DRM_ERROR("failed to allocate buffer.\n");
>                             return -ENOMEM;
>                     }
>             }
>
>             buf->sgt = drm_prime_pages_to_sg(buf->pages, nr_pages);
>             if (!buf->sgt) {
>                     DRM_ERROR("failed to get sg table.\n");
>                     ret = -ENOMEM;
>                     goto err_free_attrs;
>             }
>
>     Notice that the value returned by dma_alloc_attrs() is assumed by this
>     code to be either a kernel virtual address (in
>     !is_drm_iommu_supported()
>     case) or struct pages ** (in is_drm_iommu_supported() case), which
>     seemed
>     a bit worrying to me, making me do a more in depth research on how
>     dma_alloc_attrs works.
>
>     This, in turn, led me to following excerpt of Documentation/DMA-
>     attributes.txt :
>
>     DMA_ATTR_NO_KERNEL_MAPPING
>     --------------------------
>
>     DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a
>     kernel
>     virtual mapping for the allocated buffer. On some architectures
>     creating
>     such mapping is non-trivial task and consumes very limited resources
>     (like kernel virtual address space or dma consistent address space).
>     Buffers allocated with this attribute can be only passed to user space
>     by calling dma_mmap_attrs(). By using this API, you are guaranteeing
>     that you won't dereference the pointer returned by
>     dma_alloc_attr(). You
>     can threat it as a cookie that must be passed to dma_mmap_attrs() and
>     dma_free_attrs(). Make sure that both of these also get this attribute
>     set on each call.
>
>     of which the following sentence is the most relevant:
>
>     By using this API, you are guaranteeing that you won't dereference the
>     pointer returned by dma_alloc_attr().
>
>     This statement is obviously ignored by buffer allocation code of
>     exynos-
>     drm.
>
>     A simple git blame revealed that this brokenness has been
>     introduced by
>     commit:
>
>     4744ad2 drm/exynos: use DMA_ATTR_NO_KERNEL_MAPPING attribute
>
>
>     and later fixed a bit by following depending patches (because the
>     original
>     patch apparently broke any allocations without IOMMU):
>
>     c704f1b drm/exynos: consider no iommu support to console framebuffer
>     694be45 drm/exynos: consider buffer allocation without iommu
>
>
>     Now, the real question is whether my reasoning is incorrect (sorry
>     for the
>     noise then) or this is really a bug which needs to be fixed?
>
>
> Hi Tomasz,
>
> Your question is reasonable to me. And below is my opinion,
>
> First, also the below attribute says like below,
>
> DMA_ATTR_NO_KERNEL_MAPPING
> --------------------------
> ...
> Since it is optional for platforms to implement
> DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
> attribute and exhibit default behavior.
>
>
> In case of ARM SoC, it seems like that it just ignores the attribute
> without iommu: in case of no iommu, dma_alloc_attr() always maps pages
> allocated from highmem with kernel space. So I think we make sure that
> exynos drm driver sets the attribute only with iommu to avoid such
> confusing. For this, will post it soon.

IMHO this case simply shows that ExynosDRM driver should manage IO address
space on it's own, because DMA-mapping api is too limited. ExynosDRM is
unlikely to be used on a hardware other than Samsung Exynos, so it can
better use hardware if it access IOMMU and CMA subsystems directly and
have its own address space manager to avoid hacking in internal structures
of dma-mapping.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From steve.capper at linaro.org  Wed May  8 05:52:32 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:32 +0100
Subject: [RFC PATCH v2 00/11] HugeTLB and THP support for ARM64.
Message-ID: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>

This series brings huge pages and transparent huge pages to ARM64.
The functionality is very similar to x86, and a lot of code that can
be used by both ARM64 and x86 is brought into mm to avoid the need
for code duplication.

One notable difference from x86 is that ARM64 supports normal pages
that are 64KB. When 64KB pages are enabled, huge page and
transparent huge pages are 512MB only, otherwise the sizes match
x86.

This series applies to 3.9, and requires one additional patch
ARM64: mm: Correct show_pte behaviour
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/164157.html

I've tested this under the ARMv8 models (Fast and Foundation) and
the x86 code has been tested in a KVM guest. libhugetlbfs was used
for testing under both architectures.

The most significant changes since the first RFC are:

   * PROT_NONE support added for HugeTLB and THP.
   * pmd_modify implementation fixed.
   * Superfluous huge dcache flushing code removed.
   * Simplified (and corrected) MAX_ORDER raise for THP && 64KB
     pages.
   * The MAX_ORDER check in huge_mm.h has been corrected.

I would be particularly interested in any feedback regarding the
first 4 patches in the series (the promotion of some huge page
code from x86 to mm), as this would also allow me to simplify
my patches for huge page support in ARM.

--

Steve Capper (11):
  mm: hugetlb: Copy huge_pmd_share from x86 to mm.
  x86: mm: Remove x86 version of huge_pmd_share.
  mm: hugetlb: Copy general hugetlb code from x86 to mm.
  x86: mm: Remove general hugetlb code from x86.
  mm: thp: Correct the HPAGE_PMD_ORDER check.
  ARM64: mm: Restore memblock limit when map_mem finished.
  ARM64: mm: Make PAGE_NONE pages read only and no-execute.
  ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE bits.
  ARM64: mm: HugeTLB support.
  ARM64: mm: Raise MAX_ORDER for 64KB pages and THP.
  ARM64: mm: THP support.

 arch/arm64/Kconfig                     |  17 +++
 arch/arm64/include/asm/hugetlb.h       | 121 ++++++++++++++++++
 arch/arm64/include/asm/pgtable-hwdef.h |  12 ++
 arch/arm64/include/asm/pgtable.h       |  80 ++++++++++--
 arch/arm64/include/asm/tlb.h           |   6 +
 arch/arm64/include/asm/tlbflush.h      |   2 +
 arch/arm64/mm/Makefile                 |   1 +
 arch/arm64/mm/fault.c                  |  19 +--
 arch/arm64/mm/hugetlbpage.c            |  70 +++++++++++
 arch/arm64/mm/mmu.c                    |  19 ++-
 arch/x86/Kconfig                       |   6 +
 arch/x86/mm/hugetlbpage.c              | 187 ----------------------------
 include/linux/huge_mm.h                |   2 +-
 include/linux/hugetlb.h                |   4 +
 mm/hugetlb.c                           | 219 +++++++++++++++++++++++++++++++--
 15 files changed, 539 insertions(+), 226 deletions(-)
 create mode 100644 arch/arm64/include/asm/hugetlb.h
 create mode 100644 arch/arm64/mm/hugetlbpage.c

-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:33 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:33 +0100
Subject: [RFC PATCH v2 01/11] mm: hugetlb: Copy huge_pmd_share from x86 to mm.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-2-git-send-email-steve.capper@linaro.org>

Under x86, multiple puds can be made to reference the same bank of
huge pmds provided that they represent a full PUD_SIZE of shared
huge memory that is aligned to a PUD_SIZE boundary.

The code to share pmds does not require any architecture specific
knowledge other than the fact that pmds can be indexed, thus can
be beneficial to some other architectures.

This patch copies the huge pmd sharing (and unsharing) logic from
x86/ to mm/ and introduces a new config option to activate it:
CONFIG_ARCH_WANTS_HUGE_PMD_SHARE

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 include/linux/hugetlb.h |   4 ++
 mm/hugetlb.c            | 122 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 126 insertions(+)

diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 16e4e9a..795c32d 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -68,6 +68,10 @@ void hugetlb_unreserve_pages(struct inode *inode, long offset, long freed);
 int dequeue_hwpoisoned_huge_page(struct page *page);
 void copy_huge_page(struct page *dst, struct page *src);
 
+#ifdef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud);
+#endif
+
 extern unsigned long hugepages_treat_as_movable;
 extern const unsigned long hugetlb_zero, hugetlb_infinity;
 extern int sysctl_hugetlb_shm_group;
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index ca9a7c6..41179b0 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -3142,6 +3142,128 @@ void hugetlb_unreserve_pages(struct inode *inode, long offset, long freed)
 	hugetlb_acct_memory(h, -(chg - freed));
 }
 
+#ifdef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+static unsigned long page_table_shareable(struct vm_area_struct *svma,
+				struct vm_area_struct *vma,
+				unsigned long addr, pgoff_t idx)
+{
+	unsigned long saddr = ((idx - svma->vm_pgoff) << PAGE_SHIFT) +
+				svma->vm_start;
+	unsigned long sbase = saddr & PUD_MASK;
+	unsigned long s_end = sbase + PUD_SIZE;
+
+	/* Allow segments to share if only one is marked locked */
+	unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED;
+	unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED;
+
+	/*
+	 * match the virtual addresses, permission and the alignment of the
+	 * page table page.
+	 */
+	if (pmd_index(addr) != pmd_index(saddr) ||
+	    vm_flags != svm_flags ||
+	    sbase < svma->vm_start || svma->vm_end < s_end)
+		return 0;
+
+	return saddr;
+}
+
+static int vma_shareable(struct vm_area_struct *vma, unsigned long addr)
+{
+	unsigned long base = addr & PUD_MASK;
+	unsigned long end = base + PUD_SIZE;
+
+	/*
+	 * check on proper vm_flags and page table alignment
+	 */
+	if (vma->vm_flags & VM_MAYSHARE &&
+	    vma->vm_start <= base && end <= vma->vm_end)
+		return 1;
+	return 0;
+}
+
+/*
+ * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
+ * and returns the corresponding pte. While this is not necessary for the
+ * !shared pmd case because we can allocate the pmd later as well, it makes the
+ * code much cleaner. pmd allocation is essential for the shared case because
+ * pud has to be populated inside the same i_mmap_mutex section - otherwise
+ * racing tasks could either miss the sharing (see huge_pte_offset) or select a
+ * bad pmd for sharing.
+ */
+pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
+{
+	struct vm_area_struct *vma = find_vma(mm, addr);
+	struct address_space *mapping = vma->vm_file->f_mapping;
+	pgoff_t idx = ((addr - vma->vm_start) >> PAGE_SHIFT) +
+			vma->vm_pgoff;
+	struct vm_area_struct *svma;
+	unsigned long saddr;
+	pte_t *spte = NULL;
+	pte_t *pte;
+
+	if (!vma_shareable(vma, addr))
+		return (pte_t *)pmd_alloc(mm, pud, addr);
+
+	mutex_lock(&mapping->i_mmap_mutex);
+	vma_interval_tree_foreach(svma, &mapping->i_mmap, idx, idx) {
+		if (svma == vma)
+			continue;
+
+		saddr = page_table_shareable(svma, vma, addr, idx);
+		if (saddr) {
+			spte = huge_pte_offset(svma->vm_mm, saddr);
+			if (spte) {
+				get_page(virt_to_page(spte));
+				break;
+			}
+		}
+	}
+
+	if (!spte)
+		goto out;
+
+	spin_lock(&mm->page_table_lock);
+	if (pud_none(*pud))
+		pud_populate(mm, pud,
+				(pmd_t *)((unsigned long)spte & PAGE_MASK));
+	else
+		put_page(virt_to_page(spte));
+	spin_unlock(&mm->page_table_lock);
+out:
+	pte = (pte_t *)pmd_alloc(mm, pud, addr);
+	mutex_unlock(&mapping->i_mmap_mutex);
+	return pte;
+}
+
+/*
+ * unmap huge page backed by shared pte.
+ *
+ * Hugetlb pte page is ref counted at the time of mapping.  If pte is shared
+ * indicated by page_count > 1, unmap is achieved by clearing pud and
+ * decrementing the ref count. If count == 1, the pte page is not shared.
+ *
+ * called with vma->vm_mm->page_table_lock held.
+ *
+ * returns: 1 successfully unmapped a shared pte page
+ *	    0 the underlying pte page is not shared, or it is the last user
+ */
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+	pgd_t *pgd = pgd_offset(mm, *addr);
+	pud_t *pud = pud_offset(pgd, *addr);
+
+	BUG_ON(page_count(virt_to_page(ptep)) == 0);
+	if (page_count(virt_to_page(ptep)) == 1)
+		return 0;
+
+	pud_clear(pud);
+	put_page(virt_to_page(ptep));
+	*addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
+	return 1;
+}
+#endif /* CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
+
 #ifdef CONFIG_MEMORY_FAILURE
 
 /* Should be called in hugetlb_lock */
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:38 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:38 +0100
Subject: [RFC PATCH v2 06/11] ARM64: mm: Restore memblock limit when map_mem
 finished.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-7-git-send-email-steve.capper@linaro.org>

In paging_init the memblock limit is set to restrict any addresses
returned by early_alloc to fit within the initial direct kernel
mapping in swapper_pg_dir. This allows map_mem to allocate puds,
pmds and ptes from the initial direct kernel mapping.

The limit stays low after paging_init() though, meaning any
bootmem allocations will be from a restricted subset of memory.
Gigabyte huge pages, for instance, are normally allocated from
bootmem as their order (18) is too large for the default buddy
allocator (MAX_ORDER = 11).

This patch restores the memblock limit when map_mem has finished,
allowing gigabyte huge pages (and other objects) to be allocated
from all of bootmem.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/mm/mmu.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 70b8cd4..d23188c 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -297,6 +297,16 @@ static void __init map_mem(void)
 {
 	struct memblock_region *reg;
 
+	/*
+	 * Temporarily limit the memblock range. We need to do this as
+	 * create_mapping requires puds, pmds and ptes to be allocated from
+	 * memory addressable from the initial direct kernel mapping.
+	 *
+	 * The initial direct kernel mapping, located at swapper_pg_dir,
+	 * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (aligned).
+	 */
+	memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
+
 	/* map all the memory banks */
 	for_each_memblock(memory, reg) {
 		phys_addr_t start = reg->base;
@@ -307,6 +317,9 @@ static void __init map_mem(void)
 
 		create_mapping(start, __phys_to_virt(start), end - start);
 	}
+
+	/* Limit no longer required. */
+	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 }
 
 /*
@@ -317,12 +330,6 @@ void __init paging_init(void)
 {
 	void *zero_page;
 
-	/*
-	 * Maximum PGDIR_SIZE addressable via the initial direct kernel
-	 * mapping in swapper_pg_dir.
-	 */
-	memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
-
 	init_mem_pgprot();
 	map_mem();
 
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:34 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:34 +0100
Subject: [RFC PATCH v2 02/11] x86: mm: Remove x86 version of huge_pmd_share.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-3-git-send-email-steve.capper@linaro.org>

The huge_pmd_share code has been copied over to mm/hugetlb.c to
make it accessible to other architectures.

Remove the x86 copy of the huge_pmd_share code and enable the
ARCH_WANT_HUGE_PMD_SHARE config flag. That way we reference the
general one.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/x86/Kconfig          |   3 ++
 arch/x86/mm/hugetlbpage.c | 120 ----------------------------------------------
 2 files changed, 3 insertions(+), 120 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 70c0f3d..60e3c402 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -212,6 +212,9 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
 	def_bool y
 
+config ARCH_WANT_HUGE_PMD_SHARE
+	def_bool y
+
 config ZONE_DMA32
 	bool
 	default X86_64
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index ae1aa71..7e522a3 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -16,126 +16,6 @@
 #include <asm/tlbflush.h>
 #include <asm/pgalloc.h>
 
-static unsigned long page_table_shareable(struct vm_area_struct *svma,
-				struct vm_area_struct *vma,
-				unsigned long addr, pgoff_t idx)
-{
-	unsigned long saddr = ((idx - svma->vm_pgoff) << PAGE_SHIFT) +
-				svma->vm_start;
-	unsigned long sbase = saddr & PUD_MASK;
-	unsigned long s_end = sbase + PUD_SIZE;
-
-	/* Allow segments to share if only one is marked locked */
-	unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED;
-	unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED;
-
-	/*
-	 * match the virtual addresses, permission and the alignment of the
-	 * page table page.
-	 */
-	if (pmd_index(addr) != pmd_index(saddr) ||
-	    vm_flags != svm_flags ||
-	    sbase < svma->vm_start || svma->vm_end < s_end)
-		return 0;
-
-	return saddr;
-}
-
-static int vma_shareable(struct vm_area_struct *vma, unsigned long addr)
-{
-	unsigned long base = addr & PUD_MASK;
-	unsigned long end = base + PUD_SIZE;
-
-	/*
-	 * check on proper vm_flags and page table alignment
-	 */
-	if (vma->vm_flags & VM_MAYSHARE &&
-	    vma->vm_start <= base && end <= vma->vm_end)
-		return 1;
-	return 0;
-}
-
-/*
- * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
- * and returns the corresponding pte. While this is not necessary for the
- * !shared pmd case because we can allocate the pmd later as well, it makes the
- * code much cleaner. pmd allocation is essential for the shared case because
- * pud has to be populated inside the same i_mmap_mutex section - otherwise
- * racing tasks could either miss the sharing (see huge_pte_offset) or select a
- * bad pmd for sharing.
- */
-static pte_t *
-huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
-{
-	struct vm_area_struct *vma = find_vma(mm, addr);
-	struct address_space *mapping = vma->vm_file->f_mapping;
-	pgoff_t idx = ((addr - vma->vm_start) >> PAGE_SHIFT) +
-			vma->vm_pgoff;
-	struct vm_area_struct *svma;
-	unsigned long saddr;
-	pte_t *spte = NULL;
-	pte_t *pte;
-
-	if (!vma_shareable(vma, addr))
-		return (pte_t *)pmd_alloc(mm, pud, addr);
-
-	mutex_lock(&mapping->i_mmap_mutex);
-	vma_interval_tree_foreach(svma, &mapping->i_mmap, idx, idx) {
-		if (svma == vma)
-			continue;
-
-		saddr = page_table_shareable(svma, vma, addr, idx);
-		if (saddr) {
-			spte = huge_pte_offset(svma->vm_mm, saddr);
-			if (spte) {
-				get_page(virt_to_page(spte));
-				break;
-			}
-		}
-	}
-
-	if (!spte)
-		goto out;
-
-	spin_lock(&mm->page_table_lock);
-	if (pud_none(*pud))
-		pud_populate(mm, pud, (pmd_t *)((unsigned long)spte & PAGE_MASK));
-	else
-		put_page(virt_to_page(spte));
-	spin_unlock(&mm->page_table_lock);
-out:
-	pte = (pte_t *)pmd_alloc(mm, pud, addr);
-	mutex_unlock(&mapping->i_mmap_mutex);
-	return pte;
-}
-
-/*
- * unmap huge page backed by shared pte.
- *
- * Hugetlb pte page is ref counted at the time of mapping.  If pte is shared
- * indicated by page_count > 1, unmap is achieved by clearing pud and
- * decrementing the ref count. If count == 1, the pte page is not shared.
- *
- * called with vma->vm_mm->page_table_lock held.
- *
- * returns: 1 successfully unmapped a shared pte page
- *	    0 the underlying pte page is not shared, or it is the last user
- */
-int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
-{
-	pgd_t *pgd = pgd_offset(mm, *addr);
-	pud_t *pud = pud_offset(pgd, *addr);
-
-	BUG_ON(page_count(virt_to_page(ptep)) == 0);
-	if (page_count(virt_to_page(ptep)) == 1)
-		return 0;
-
-	pud_clear(pud);
-	put_page(virt_to_page(ptep));
-	*addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
-	return 1;
-}
-
 pte_t *huge_pte_alloc(struct mm_struct *mm,
 			unsigned long addr, unsigned long sz)
 {
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:35 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:35 +0100
Subject: [RFC PATCH v2 03/11] mm: hugetlb: Copy general hugetlb code from x86
 to mm.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-4-git-send-email-steve.capper@linaro.org>

The huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d
functions in x86/mm/hugetlbpage.c do not rely on any architecture
specific knowledge other than the fact that pmds and puds can be
treated as huge ptes.

To allow other architectures to use this code (and reduce the need
for code duplication), this patch copies these functions into mm
and provides a config flag to activate them:
CONFIG_ARCH_WANT_GENERAL_HUGETLB

If CONFIG_ARCH_WANT_HUGE_PMD_SHARE is also active then the
huge_pmd_share code will be called by huge_pte_alloc (othewise we
call pmd_alloc and skip the sharing code).

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 mm/hugetlb.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 88 insertions(+), 9 deletions(-)

diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 41179b0..e1dc5ae 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -2915,15 +2915,6 @@ out_mutex:
 	return ret;
 }
 
-/* Can be overriden by architectures */
-__attribute__((weak)) struct page *
-follow_huge_pud(struct mm_struct *mm, unsigned long address,
-	       pud_t *pud, int write)
-{
-	BUG();
-	return NULL;
-}
-
 long follow_hugetlb_page(struct mm_struct *mm, struct vm_area_struct *vma,
 			 struct page **pages, struct vm_area_struct **vmas,
 			 unsigned long *position, unsigned long *nr_pages,
@@ -3262,8 +3253,96 @@ int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
 	*addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
 	return 1;
 }
+#define want_pmd_share()	(1)
+#else /* !CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
+pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
+{
+	return NULL;
+}
+#define want_pmd_share()	(0)
 #endif /* CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
 
+#ifdef CONFIG_ARCH_WANT_GENERAL_HUGETLB
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+			unsigned long addr, unsigned long sz)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pte_t *pte = NULL;
+
+	pgd = pgd_offset(mm, addr);
+	pud = pud_alloc(mm, pgd, addr);
+	if (pud) {
+		if (sz == PUD_SIZE) {
+			pte = (pte_t *)pud;
+		} else {
+			BUG_ON(sz != PMD_SIZE);
+			if (want_pmd_share() && pud_none(*pud))
+				pte = huge_pmd_share(mm, addr, pud);
+			else
+				pte = (pte_t *)pmd_alloc(mm, pud, addr);
+		}
+	}
+	BUG_ON(pte && !pte_none(*pte) && !pte_huge(*pte));
+
+	return pte;
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd = NULL;
+
+	pgd = pgd_offset(mm, addr);
+	if (pgd_present(*pgd)) {
+		pud = pud_offset(pgd, addr);
+		if (pud_present(*pud)) {
+			if (pud_large(*pud))
+				return (pte_t *)pud;
+			pmd = pmd_offset(pud, addr);
+		}
+	}
+	return (pte_t *) pmd;
+}
+
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+		pmd_t *pmd, int write)
+{
+	struct page *page;
+
+	page = pte_page(*(pte_t *)pmd);
+	if (page)
+		page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
+	return page;
+}
+
+struct page *
+follow_huge_pud(struct mm_struct *mm, unsigned long address,
+		pud_t *pud, int write)
+{
+	struct page *page;
+
+	page = pte_page(*(pte_t *)pud);
+	if (page)
+		page += ((address & ~PUD_MASK) >> PAGE_SHIFT);
+	return page;
+}
+
+#else /* !CONFIG_ARCH_WANT_GENERAL_HUGETLB */
+
+/* Can be overriden by architectures */
+__attribute__((weak)) struct page *
+follow_huge_pud(struct mm_struct *mm, unsigned long address,
+	       pud_t *pud, int write)
+{
+	BUG();
+	return NULL;
+}
+
+#endif /* CONFIG_ARCH_WANT_GENERAL_HUGETLB */
+
 #ifdef CONFIG_MEMORY_FAILURE
 
 /* Should be called in hugetlb_lock */
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:37 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:37 +0100
Subject: [RFC PATCH v2 05/11] mm: thp: Correct the HPAGE_PMD_ORDER check.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-6-git-send-email-steve.capper@linaro.org>

All Transparent Huge Pages are allocated by the buddy allocator.

A compile time check is in place that fails when the order of a
transparent huge page is too large to be allocated by the buddy
allocator. Unfortunately that compile time check passes when:
HPAGE_PMD_ORDER == MAX_ORDER
( which is incorrect as the buddy allocator can only allocate
memory of order strictly less than MAX_ORDER. )

This patch updates the compile time check to fail in the above
case.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 include/linux/huge_mm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h
index ee1c244..3d71e5c 100644
--- a/include/linux/huge_mm.h
+++ b/include/linux/huge_mm.h
@@ -119,7 +119,7 @@ extern void __split_huge_page_pmd(struct vm_area_struct *vma,
 	} while (0)
 extern void split_huge_page_pmd_mm(struct mm_struct *mm, unsigned long address,
 		pmd_t *pmd);
-#if HPAGE_PMD_ORDER > MAX_ORDER
+#if HPAGE_PMD_ORDER >= MAX_ORDER
 #error "hugepages can't be allocated by the buddy allocator"
 #endif
 extern int hugepage_madvise(struct vm_area_struct *vma,
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:36 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:36 +0100
Subject: [RFC PATCH v2 04/11] x86: mm: Remove general hugetlb code from x86.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-5-git-send-email-steve.capper@linaro.org>

huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d have
already been copied over to mm.

This patch removes the x86 copies of these functions and activates
the general ones by enabling:
CONFIG_ARCH_WANT_GENERAL_HUGETLB

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/x86/Kconfig          |  3 +++
 arch/x86/mm/hugetlbpage.c | 67 -----------------------------------------------
 2 files changed, 3 insertions(+), 67 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 60e3c402..db1ff87 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -215,6 +215,9 @@ config ARCH_SUSPEND_POSSIBLE
 config ARCH_WANT_HUGE_PMD_SHARE
 	def_bool y
 
+config ARCH_WANT_GENERAL_HUGETLB
+	def_bool y
+
 config ZONE_DMA32
 	bool
 	default X86_64
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index 7e522a3..7e73e8c 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -16,49 +16,6 @@
 #include <asm/tlbflush.h>
 #include <asm/pgalloc.h>
 
-pte_t *huge_pte_alloc(struct mm_struct *mm,
-			unsigned long addr, unsigned long sz)
-{
-	pgd_t *pgd;
-	pud_t *pud;
-	pte_t *pte = NULL;
-
-	pgd = pgd_offset(mm, addr);
-	pud = pud_alloc(mm, pgd, addr);
-	if (pud) {
-		if (sz == PUD_SIZE) {
-			pte = (pte_t *)pud;
-		} else {
-			BUG_ON(sz != PMD_SIZE);
-			if (pud_none(*pud))
-				pte = huge_pmd_share(mm, addr, pud);
-			else
-				pte = (pte_t *)pmd_alloc(mm, pud, addr);
-		}
-	}
-	BUG_ON(pte && !pte_none(*pte) && !pte_huge(*pte));
-
-	return pte;
-}
-
-pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
-{
-	pgd_t *pgd;
-	pud_t *pud;
-	pmd_t *pmd = NULL;
-
-	pgd = pgd_offset(mm, addr);
-	if (pgd_present(*pgd)) {
-		pud = pud_offset(pgd, addr);
-		if (pud_present(*pud)) {
-			if (pud_large(*pud))
-				return (pte_t *)pud;
-			pmd = pmd_offset(pud, addr);
-		}
-	}
-	return (pte_t *) pmd;
-}
-
 #if 0	/* This is just for testing */
 struct page *
 follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
@@ -120,30 +77,6 @@ int pud_huge(pud_t pud)
 	return !!(pud_val(pud) & _PAGE_PSE);
 }
 
-struct page *
-follow_huge_pmd(struct mm_struct *mm, unsigned long address,
-		pmd_t *pmd, int write)
-{
-	struct page *page;
-
-	page = pte_page(*(pte_t *)pmd);
-	if (page)
-		page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
-	return page;
-}
-
-struct page *
-follow_huge_pud(struct mm_struct *mm, unsigned long address,
-		pud_t *pud, int write)
-{
-	struct page *page;
-
-	page = pte_page(*(pte_t *)pud);
-	if (page)
-		page += ((address & ~PUD_MASK) >> PAGE_SHIFT);
-	return page;
-}
-
 #endif
 
 /* x86_64 also uses this file */
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:39 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:39 +0100
Subject: [RFC PATCH v2 07/11] ARM64: mm: Make PAGE_NONE pages read only and
 no-execute.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-8-git-send-email-steve.capper@linaro.org>

If we consider the following code sequence:

	my_pte = pte_modify(entry, myprot);
	x = pte_write(my_pte);
	y = pte_exec(my_pte);

If myprot comes from a PROT_NONE page, then x and y will both be
true which is undesireable behaviour.

This patch sets the no-execute and read-only bits for PAGE_NONE
such that the code above will return false for both x and y.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/include/asm/pgtable.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e333a24..b1a1b59 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -66,7 +66,7 @@ extern pgprot_t pgprot_default;
 
 #define _MOD_PROT(p, b)		__pgprot_modify(p, 0, b)
 
-#define PAGE_NONE		__pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE)
+#define PAGE_NONE		__pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_RDONLY | PTE_UXN)
 #define PAGE_SHARED		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
 #define PAGE_COPY		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
@@ -76,7 +76,7 @@ extern pgprot_t pgprot_default;
 #define PAGE_KERNEL		_MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
 #define PAGE_KERNEL_EXEC	_MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
 
-#define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
+#define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_RDONLY | PTE_UXN)
 #define __PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
 #define __PAGE_COPY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:40 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:40 +0100
Subject: [RFC PATCH v2 08/11] ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE bits.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-9-git-send-email-steve.capper@linaro.org>

Under ARM64, PTEs can be broadly categorised as follows:
   - Present and valid: Bit #0 is set. The PTE is valid and memory
     access to the region may fault.

   - Present and invalid: Bit #0 is clear and bit #1 is set.
     Represents present memory with PROT_NONE protection. The PTE
     is an invalid entry, and the user fault handler will raise a
     SIGSEGV.

   - Not present (file): Bits #0 and #1 are clear, bit #2 is set.
     Memory represented has been paged out. The PTE is an invalid
     entry, and the fault handler will try and re-populate the
     memory where necessary.

Huge PTEs are block descriptors that have bit #1 clear. If we wish
to represent PROT_NONE huge PTEs we then run into a problem as
there is no way to distinguish between regular and huge PTEs if we
set bit #1.

As huge PTEs are always present, the meaning of bits #1 and #2 can
be swapped for invalid PTEs. This patch swaps the PTE_FILE and
PTE_PROT_NONE constants, allowing us to represent PROT_NONE huge
PTEs.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/include/asm/pgtable.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b1a1b59..e245260 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -25,8 +25,8 @@
  * Software defined PTE bits definition.
  */
 #define PTE_VALID		(_AT(pteval_t, 1) << 0)
-#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 1)	/* only when !PTE_VALID */
-#define PTE_FILE		(_AT(pteval_t, 1) << 2)	/* only when !pte_present() */
+#define PTE_FILE		(_AT(pteval_t, 1) << 1)	/* only when !pte_present() */
+#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 2)	/* only when !PTE_VALID */
 #define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
 #define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
 
@@ -306,8 +306,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 
 /*
  * Encode and decode a file entry:
- *	bits 0-1:	present (must be zero)
- *	bit  2:		PTE_FILE
+ *	bits 0 & 2:	present (must be zero)
+ *	bit  1:		PTE_FILE
  *	bits 3-63:	file offset / PAGE_SIZE
  */
 #define pte_file(pte)		(pte_val(pte) & PTE_FILE)
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:42 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:42 +0100
Subject: [RFC PATCH v2 10/11] ARM64: mm: Raise MAX_ORDER for 64KB pages and
 THP.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-11-git-send-email-steve.capper@linaro.org>

The buddy allocator has a default MAX_ORDER of 11, which is too
low to allocate enough memory for 512MB Transparent HugePages if
our base page size is 64KB.

This patch introduces MAX_ZONE_ORDER and sets it to 14 when 64KB
pages are used in conjuction with THP, otherwise the default value
of 11 is used.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 053533b..a5f76cf 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -196,6 +196,11 @@ config ARCH_WANT_HUGE_PMD_SHARE
 
 source "mm/Kconfig"
 
+config FORCE_MAX_ZONEORDER
+	int
+	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
+	default "11"
+
 endmenu
 
 menu "Boot options"
-- 
1.8.1.4



From steve.capper at linaro.org  Wed May  8 05:52:41 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:41 +0100
Subject: [RFC PATCH v2 09/11] ARM64: mm: HugeTLB support.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-10-git-send-email-steve.capper@linaro.org>

Add huge page support to ARM64, different huge page sizes are
supported depending on the size of normal pages:

PAGE_SIZE is 4KB:
   2MB - (pmds) these can be allocated at any time.
1024MB - (puds) usually allocated on bootup with the command line
         with something like: hugepagesz=1G hugepages=6

PAGE_SIZE is 64KB:
 512MB - (pmds) usually allocated on bootup via command line.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/Kconfig                     |   9 +++
 arch/arm64/include/asm/hugetlb.h       | 121 +++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/pgtable-hwdef.h |   8 +++
 arch/arm64/include/asm/pgtable.h       |  13 +++-
 arch/arm64/mm/Makefile                 |   1 +
 arch/arm64/mm/fault.c                  |  19 ++----
 arch/arm64/mm/hugetlbpage.c            |  70 +++++++++++++++++++
 7 files changed, 224 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm64/include/asm/hugetlb.h
 create mode 100644 arch/arm64/mm/hugetlbpage.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 43b0e9f..053533b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -185,6 +185,15 @@ config HW_PERF_EVENTS
 	  Enable hardware performance counter support for perf events. If
 	  disabled, perf events will use software events only.
 
+config SYS_SUPPORTS_HUGETLBFS
+	def_bool y
+
+config ARCH_WANT_GENERAL_HUGETLB
+	def_bool y
+
+config ARCH_WANT_HUGE_PMD_SHARE
+	def_bool y if !ARM64_64K_PAGES
+
 source "mm/Kconfig"
 
 endmenu
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
new file mode 100644
index 0000000..fb08fbb
--- /dev/null
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -0,0 +1,121 @@
+/*
+ * arch/arm64/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_HUGETLB_H
+#define __ASM_HUGETLB_H
+
+#include <asm/page.h>
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+	return *ptep;
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+				   pte_t *ptep, pte_t pte)
+{
+	set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+					 unsigned long addr, pte_t *ptep)
+{
+	ptep_clear_flush(vma, addr, ptep);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+					   unsigned long addr, pte_t *ptep)
+{
+	ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+					    unsigned long addr, pte_t *ptep)
+{
+	return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+					     unsigned long addr, pte_t *ptep,
+					     pte_t pte, int dirty)
+{
+	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+					  unsigned long addr, unsigned long end,
+					  unsigned long floor,
+					  unsigned long ceiling)
+{
+	free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+					 unsigned long addr, unsigned long len)
+{
+	return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+					 unsigned long addr, unsigned long len)
+{
+	struct hstate *h = hstate_file(file);
+	if (len & ~huge_page_mask(h))
+		return -EINVAL;
+	if (addr & ~huge_page_mask(h))
+		return -EINVAL;
+	return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+	return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+	return pte_wrprotect(pte);
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+	return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+	clear_bit(PG_dcache_clean, &page->flags);
+}
+
+static inline int pud_large(pud_t pud)
+{
+	return !(pud_val(pud) & PUD_TABLE_BIT);
+}
+
+#endif /* __ASM_HUGETLB_H */
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 75fd13d..e6e0a0d 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -25,12 +25,19 @@
 /*
  * Hardware page table definitions.
  *
+ * Level 1 descriptor (PUD).
+ */
+
+#define PUD_TABLE_BIT		(_AT(pgdval_t, 1) << 1)
+
+/*
  * Level 2 descriptor (PMD).
  */
 #define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
 
 /*
  * Section
@@ -53,6 +60,7 @@
 #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
 #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
 #define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
 #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e245260..6bcbcfd 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -173,8 +173,17 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 /*
  * Huge pte definitions.
  */
-#define pte_huge(pte)		((pte_val(pte) & PTE_TYPE_MASK) == PTE_TYPE_HUGEPAGE)
-#define pte_mkhuge(pte)		(__pte((pte_val(pte) & ~PTE_TYPE_MASK) | PTE_TYPE_HUGEPAGE))
+#define pte_huge(pte)		(!(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+
+/*
+ * Hugetlb definitions.
+ */
+#define HUGE_MAX_HSTATE		2
+#define HPAGE_SHIFT		PMD_SHIFT
+#define HPAGE_SIZE		(_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
 
 #define __HAVE_ARCH_PTE_SPECIAL
 
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index 3140a2a..b51d364 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -2,3 +2,4 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
 				   cache.o copypage.o flush.o \
 				   ioremap.o mmap.o pgd.o mmu.o \
 				   context.o tlb.o proc.o
+obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 5263817..36e3080 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -363,17 +363,6 @@ static int __kprobes do_translation_fault(unsigned long addr,
 }
 
 /*
- * Some section permission faults need to be handled gracefully.  They can
- * happen due to a __{get,put}_user during an oops.
- */
-static int do_sect_fault(unsigned long addr, unsigned int esr,
-			 struct pt_regs *regs)
-{
-	do_bad_area(addr, esr, regs);
-	return 0;
-}
-
-/*
  * This abort handler always returns "fault".
  */
 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
@@ -396,12 +385,12 @@ static struct fault_info {
 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 2 translation fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved access flag fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 access flag fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved permission fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
-	{ do_sect_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 permission fault"	},
 	{ do_bad,		SIGBUS,  0,		"synchronous external abort"	},
 	{ do_bad,		SIGBUS,  0,		"asynchronous external abort"	},
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
new file mode 100644
index 0000000..2fc8258
--- /dev/null
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -0,0 +1,70 @@
+/*
+ * arch/arm64/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * Based on arch/x86/mm/hugetlbpage.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+#ifndef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+	return 0;
+}
+#endif
+
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+			      int write)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+int pmd_huge(pmd_t pmd)
+{
+	return !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
+
+int pud_huge(pud_t pud)
+{
+	return !(pud_val(pud) & PUD_TABLE_BIT);
+}
+
+static __init int setup_hugepagesz(char *opt)
+{
+	unsigned long ps = memparse(opt, &opt);
+	if (ps == PMD_SIZE) {
+		hugetlb_add_hstate(PMD_SHIFT - PAGE_SHIFT);
+	} else if (ps == PUD_SIZE) {
+		hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT);
+	} else {
+		pr_err("hugepagesz: Unsupported page size %lu M\n", ps >> 20);
+		return 0;
+	}
+	return 1;
+}
+__setup("hugepagesz=", setup_hugepagesz);
-- 
1.8.1.4



From marc.zyngier at arm.com  Wed May  8 05:53:28 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 08 May 2013 10:53:28 +0100
Subject: [PATCH] ARM: KVM: prevent NULL pointer dereference with KVM ioctl
In-Reply-To: <1367931313-14839-1-git-send-email-andre.przywara@linaro.org>
References: <1367931313-14839-1-git-send-email-andre.przywara@linaro.org>
Message-ID: <518A2098.9010909@arm.com>

On 07/05/13 13:55, Andre Przywara wrote:
> Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
> with the KVM_ARM_VCPU_INIT ioctl before being used with further
> requests. KVM_RUN checks whether this initialization has been
> done, but other ioctls do not.
> Namely KVM_GET_REG_LIST will dereference an array with index -1
> without initialization and thus leads to a kernel oops.
> Fix this by adding checks before executing the ioctl handlers.
> 
> Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
> ---
>  arch/arm/kvm/arm.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index c1fe498..0c571ff 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -893,6 +893,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
>  	case KVM_SET_ONE_REG:
>  	case KVM_GET_ONE_REG: {
>  		struct kvm_one_reg reg;
> +
> +		/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
> +		if (unlikely(vcpu->arch.target < 0))
> +			return -ENOEXEC;
> +
>  		if (copy_from_user(&reg, argp, sizeof(reg)))
>  			return -EFAULT;
>  		if (ioctl == KVM_SET_ONE_REG)
> @@ -905,6 +910,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
>  		struct kvm_reg_list reg_list;
>  		unsigned n;
>  
> +		/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
> +		if (unlikely(vcpu->arch.target < 0))
> +			return -ENOEXEC;
> +
>  		if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
>  			return -EFAULT;
>  		n = reg_list.n;
> 

So we also have the same snippet in kvm_arch_vcpu_ioctl_run().

Can you create a static function (kvm_vcpu_initialized?) containing that
code and make all three sites use it?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From steve.capper at linaro.org  Wed May  8 05:52:43 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed,  8 May 2013 10:52:43 +0100
Subject: [RFC PATCH v2 11/11] ARM64: mm: THP support.
In-Reply-To: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1368006763-30774-12-git-send-email-steve.capper@linaro.org>

Bring Transparent HugePage support to ARM. The size of a
transparent huge page depends on the normal page size. A
transparent huge page is always represented as a pmd.

If PAGE_SIZE is 4KB, THPs are 2MB.
If PAGE_SIZE is 64KB, THPs are 512MB.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/Kconfig                     |  3 ++
 arch/arm64/include/asm/pgtable-hwdef.h |  4 +++
 arch/arm64/include/asm/pgtable.h       | 55 ++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/tlb.h           |  6 ++++
 arch/arm64/include/asm/tlbflush.h      |  2 ++
 5 files changed, 70 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a5f76cf..93a3b9e 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -194,6 +194,9 @@ config ARCH_WANT_GENERAL_HUGETLB
 config ARCH_WANT_HUGE_PMD_SHARE
 	def_bool y if !ARM64_64K_PAGES
 
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+	def_bool y
+
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index e6e0a0d..63c9d0d 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -42,6 +42,10 @@
 /*
  * Section
  */
+#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_PROT_NONE	(_AT(pmdval_t, 1) << 2)
+#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
+#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
 #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 6bcbcfd..fd17e0b 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -188,6 +188,61 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 #define __HAVE_ARCH_PTE_SPECIAL
 
 /*
+ * Software PMD bits for THP
+ */
+
+#define PMD_SECT_DIRTY		(_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING	(_AT(pmdval_t, 1) << 57)
+
+/*
+ * THP definitions.
+ */
+#define pmd_young(pmd)		(pmd_val(pmd) & PMD_SECT_AF)
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)		(!(pmd_val(pmd) & PMD_SECT_RDONLY))
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)	(pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+
+PMD_BIT_FUNC(wrprotect,	|= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,	&= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+PMD_BIT_FUNC(mknotpresent, &= ~PMD_TYPE_MASK);
+
+#define pmd_mkhuge(pmd)		(__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+
+#define pmd_pfn(pmd)		(((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)	(__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)	pfn_pmd(page_to_pfn(page),prot)
+
+#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+	const pmdval_t mask = PMD_SECT_USER | PMD_SECT_PXN | PMD_SECT_UXN |
+			      PMD_SECT_RDONLY | PMD_SECT_PROT_NONE |
+			      PMD_SECT_VALID;
+	pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+	return pmd;
+}
+
+#define set_pmd_at(mm, addr, pmdp, pmd)	set_pmd(pmdp, pmd)
+
+static inline int has_transparent_hugepage(void)
+{
+	return 1;
+}
+
+/*
  * Mark the prot value as uncacheable and unbufferable.
  */
 #define pgprot_noncached(prot) \
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 654f096..46b3beb 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -187,4 +187,10 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 
 #define tlb_migrate_finish(mm)		do { } while (0)
 
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+	tlb_add_flush(tlb, addr);
+}
+
 #endif
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 122d632..8b48203 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -117,6 +117,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 	dsb();
 }
 
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
+
 #endif
 
 #endif
-- 
1.8.1.4



From mingo at kernel.org  Wed May  8 06:39:56 2013
From: mingo at kernel.org (Ingo Molnar)
Date: Wed, 8 May 2013 12:39:56 +0200
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <1367937595-32241-12-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
Message-ID: <20130508103956.GA7677@gmail.com>


* Robin Holt <holt at sgi.com> wrote:

> Merge together the unicore32, arm, and x86 reboot= command line
> parameter handling.

The series still has this CONFIG_X86 dependency that I inquired about 
previously:

> +static int __init reboot_setup(char *str)
> +{
> +	for (;;) {
> +		/*
> +		 * Having anything passed on the command line via
> +		 * reboot= will cause us to disable DMI checking
> +		 * below.
> +		 */
> +		reboot_default = 0;
> +
> +		switch (*str) {
> +#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
> +		case 'w':
> +			reboot_mode = REBOOT_WARM;
> +			break;
> +
> +		case 'c':
> +			reboot_mode = REBOOT_COLD;
> +			break;
> +
> +#ifdef CONFIG_SMP
> +		case 's':
> +			if (isdigit(*(str+1))) {
> +				reboot_cpu = (int) (*(str+1) - '0');
> +				if (isdigit(*(str+2)))
> +					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
> +			}
> +			/*
> +			 * We will leave sorting out the final value
> +			 * when we are ready to reboot, since we might not
> +			 * have detected BSP APIC ID or smp_num_cpu
> +			 */
> +			break;
> +#endif /* CONFIG_SMP */
> +
> +#else
> +		case 's':
> +			reboot_mode = REBOOT_WARM;
> +		case 'h':
> +			reboot_mode = REBOOT_COLD;
> +		case 'g':
> +			reboot_mode = REBOOT_GPIO;
> +#endif
> +
> +		case 'b':
> +		case 'a':
> +		case 'k':
> +		case 't':
> +		case 'e':
> +		case 'p':
> +			reboot_type = *str;
> +			break;
> +
> +		case 'f':
> +			reboot_force = 1;
> +			break;
> +		}
> +
> +		str = strchr(str, ',');
> +		if (str)
> +			str++;
> +		else
> +			break;
> +	}
> +	return 1;

To explain my concern more verbosely, if we cannot make it 'obviously 
generic' then there's no point in moving it to kernel/reboot.c ...

And yes, I realize that there's an option clash between architectures - 
see below for potential solutions to that.

To generalize it, firstly here's a summary of the existing reboot option 
mappings:

 x86-only:  w, c, s
 non-x86:         s, h, g
 generic:                  b, a, k, t, e, p, f


it appears that 'w', 'c', 'h', and 'g' could be made generic straight 
away.

Which leaves 's' as the only truly problematic option:

 - it means REBOOT_WARM on some non-x86 platform(s?)
 - while it means the SMP-cpu on x86.

Stupid question: which non-x86 platform(s) use 's'?

I think we should either change that platform to have 'w' as the warm 
reboot (and hope that no-one actually relies on the old 's' option: it's a 
truly rare option) - or change the x86 mapping from 's' to 'S' and 
generalize and unify it thusly.

Another cleanliness problem is the duality of reboot_mode and reboot_type. 
We should pick one and use it everywhere consistently.

[ Once these problems are solved and there's no objections from others to 
  this approach, I'd be willing to apply, test and push this series to 
  Linus. ]

Thanks,

	Ingo


From marc.zyngier at arm.com  Wed May  8 06:46:25 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 08 May 2013 11:46:25 +0100
Subject: [PATCH v2 1/5] ARM: KVM: be more thorough when invalidating TLBs
In-Reply-To: <20130502151302.GG20730@arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-2-git-send-email-marc.zyngier@arm.com>
 <20130502151302.GG20730@arm.com>
Message-ID: <518A2D01.1070904@arm.com>

On 02/05/13 16:13, Catalin Marinas wrote:
> On Thu, May 02, 2013 at 03:38:58PM +0100, Marc Zyngier wrote:
>> diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
>> index f7793df..9e2d906c 100644
>> --- a/arch/arm/kvm/interrupts.S
>> +++ b/arch/arm/kvm/interrupts.S
> ...
>> -static void clear_pte_entry(pte_t *pte)
>> +static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
>>  {
>>  	if (pte_present(*pte)) {
>>  		kvm_set_pte(pte, __pte(0));
>>  		put_page(virt_to_page(pte));
>> +		kvm_tlb_flush_vmid_ipa(kvm, addr);
>>  	}
>>  }
> ...
>>  static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
>>  {
>> -	unmap_range(kvm->arch.pgd, start, size);
>> +	unmap_range(kvm, kvm->arch.pgd, start, size);
>>  }
>>  
>>  /**
>> @@ -413,6 +425,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm)
>>  		return;
>>  
>>  	unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);
>> +	kvm_tlb_flush_vmid_ipa(kvm, 0);	/* Invalidate TLB ALL */
> 
> Do you still need this here if you invalidated each individual pte in
> clear_pte_entry()? I think you can remove it from clear_pte_entry() and
> just leave it here (more efficient probably) since you wouldn't free the
> actual pages pointed at by the pte before unmapping.

There is two cases we're trying to cater for:
- unmapping a single page from stage2 (page being swapped out, for example)
- unmapping the whole of stage2 (VM exiting)

We cannot loose the "local" operations, but the last one can indeed go.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From daniel.lezcano at linaro.org  Wed May  8 06:53:38 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 08 May 2013 12:53:38 +0200
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <518A2EB2.70006@linaro.org>

On 05/06/2013 10:39 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
> they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
> this, simply disable LP2 if the PCI driver and DT node are both enabled.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
> Thierry,
> 
> This patch is physically based on next-20130506 so that it doesn't
> conflict with any of the recent cpuidle cleanup work. I'm sending it with
> the expectation that you'll apply it to your PCIe development branch
> though. If you do that, you'll see some conflicts unless you rebase your
> dev branch onto something more recent than next-20130422; I assume you'll
> do that rebase soon enough anyway, but if you weren't planning to, I can
> resend the patch based on your current dev branch.
> 
>  arch/arm/mach-tegra/cpuidle-tegra20.c |   30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
> index 0cdba8d..d2c9349 100644
> --- a/arch/arm/mach-tegra/cpuidle-tegra20.c
> +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
> @@ -25,6 +25,7 @@
>  #include <linux/cpu_pm.h>
>  #include <linux/clockchips.h>
>  #include <linux/clk/tegra.h>
> +#include <linux/of.h>
>  
>  #include <asm/cpuidle.h>
>  #include <asm/proc-fns.h>
> @@ -212,10 +213,39 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
>  }
>  #endif
>  
> +static const struct of_device_id pcie_matches[] __initconst = {
> +	{ .compatible = "nvidia,tegra20-pcie" },
> +	{ }
> +};
> +
> +/*
> + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
> + * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
> + * this, simply disable LP2 if the PCI driver and DT node are both enabled.
> + */
> +static void __init tegra20_cpuidle_disable_lp2_with_pcie(void)
> +{
> +	struct device_node *np;
> +
> +	if (!IS_ENABLED(CONFIG_PCI_TEGRA))
> +		return;
> +
> +	np = of_find_matching_node(NULL, pcie_matches);
> +	if (!np)
> +		return;
> +
> +	if (!of_device_is_available(np))
> +		return;
> +
> +	pr_info("Disabling LP2 cpuidle state, since PCIe is enabled\n");
> +	tegra_idle_driver.state_count = 1;

Won't be more clear to have the state disabled in the init function like
this ?

int __init tegra20_cpuidle_init(void)
{
	...
	if (tegra20_has_lp2_pcie_bug(void))
		tegra_idle_driver.states[1].disabled = true;
	...
}

It is similar than:

https://git.kernel.org/cgit/linux/kernel/git/rafael/linux-pm.git/tree/arch/sh/kernel/cpu/shmobile/cpuidle.c

> +}
> +
>  int __init tegra20_cpuidle_init(void)
>  {
>  #ifdef CONFIG_PM_SLEEP
>  	tegra_tear_down_cpu = tegra20_tear_down_cpu;
>  #endif
> +	tegra20_cpuidle_disable_lp2_with_pcie();
>  	return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
>  }
> 


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

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From thierry.reding at avionic-design.de  Wed May  8 06:56:19 2013
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 8 May 2013 12:56:19 +0200
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <20130508094004.GL7949@tbergstrom-lnx.Nvidia.com>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
 <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>
 <20130507130850.GA11202@avionic-0098.adnet.avionic-design.de>
 <518915A7.1020105@wwwdotorg.org>
 <20130508094004.GL7949@tbergstrom-lnx.Nvidia.com>
Message-ID: <20130508105619.GA6682@avionic-0098.adnet.avionic-design.de>

On Wed, May 08, 2013 at 12:40:04PM +0300, Peter De Schrijver wrote:
> On Tue, May 07, 2013 at 04:54:31PM +0200, Stephen Warren wrote:
> > On 05/07/2013 07:08 AM, Thierry Reding wrote:
> > > On Tue, May 07, 2013 at 03:48:49PM +0300, Peter De Schrijver
> > > wrote:
> > >> On Mon, May 06, 2013 at 10:39:04PM +0200, Stephen Warren wrote:
> > >>> From: Stephen Warren <swarren at nvidia.com>
> > >>> 
> > >>> Tegra20 HW appears to have a bug such that PCIe device
> > >>> interrupts, whether they are legacy IRQs or MSI, are lost when
> > >>> LP2 is enabled. To work around this, simply disable LP2 if the
> > >>> PCI driver and DT node are both enabled.
> > >>> 
> > >> 
> > >> Wouldn't it make more sense to disable LP2 when we actually
> > >> detect a PCIe device?
> > 
> > I did consider that, but rejected the idea for the reasons Thierry
> > mentioned.
> > 
> > > I'm not sure a patch to do so would be as simple as this one. For
> > > one, the cpuidle framework will already have been initialized when
> > > PCIe enumeration completes. So some way of permanently disabling
> > > one state at runtime would be required and I don't think cpuidle
> > > provides an API to do so. I know the latter isn't really a good
> > > reason, but I don't think adding that kind of API just because
> > > Tegra20 seems to have a bug would be appropriate.
> > 
> > There is a way to do this, since it can be done via sysfs, but I don't
> > think it's exposed as an API from cpuidle. I agree it seems a little
> > silly to expose it just to support this HW bug though.
> > 
> > > Furthermore, it is quite likely that the PCIe controller will only
> > > be enabled in DT for devices that actually have a PCIe device
> > > hooked up.
> > 
> 
> That's not always true though. Eg Harmony has a miniPCIe slot, so it should be
> listed in DT, but there is not necessarily a card present in the slot.

That's true. I suppose one could argue that Harmony is a development
board and more typical setups wouldn't have user-accessible slots.

Then again it seems like LP2 causes some more fallout like very slow
output on the serial console and a decrease in FPS for some 2D/3D use-
cases I've been playing around with. While these are only performance
issues they still indicate that something is seriously flawed with the
current LP2 implementation (at least on Tegra20). So maybe it would be
preferable to disable it altogether if it cannot be fixed otherwise.

I was able to mitigate the problems a bit on Tamonten by reducing the
value of the nvidia,cpu-pwr-good-time and nvidia,cpu-pwr-off-time from
5000 us to 500 and 100 us respectively. That gives much better
performance for the serial console and 2D/3D test-cases, but the 2D/3D
performance is still down by about 10% compared to runs with LP2
disabled.

Now the 2D and 3D test-cases aren't very complex and there's certainly
much that could be improved with regard to job submission and such, but
neither removes the fundamental issue that LP2 is causing a lot of
problems that it shouldn't.

Thierry
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From broonie at kernel.org  Wed May  8 06:57:32 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 8 May 2013 11:57:32 +0100
Subject: [PATCH] ARM: ux500: update MSP1 pinctrl defintions
In-Reply-To: <1368004193-21213-1-git-send-email-fabio.baltieri@linaro.org>
References: <1368004193-21213-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <20130508105732.GD7478@sirena.org.uk>

On Wed, May 08, 2013 at 11:09:53AM +0200, Fabio Baltieri wrote:
> Update MSP1 pinctrl definitions in mop500_family_pinmap by removing
> sleep state and setting default ones as pin hogs, as those are used by
> both ux500-msp-i2s.1 and ux500-msp-i2s.3.

This presumably needs to go along with the ASoC side of this change but
as I said in reply to that this isn't an obvious improvement.
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From jagarwal at nvidia.com  Wed May  8 06:57:37 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 8 May 2013 16:27:37 +0530
Subject: [PATCH 1/4] ARM: tegra30: clocks: Fix pciex clock registration
Message-ID: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>

Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api 
gives warning and ultimately does not succeed to assert(deassert).
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
and should be applied on top of this.

Signed-off-by: Jay Agarwal <jagarwal at nvidia.com>
---
 drivers/clk/tegra/clk-tegra30.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51b..6a80b40 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1592,6 +1592,12 @@ static void __init tegra30_periph_clk_init(void)
 	clk_register_clkdev(clk, "afi", "tegra-pcie");
 	clks[afi] = clk;
 
+	/* pciex */
+	clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
+				    74, &periph_u_regs, periph_clk_enb_refcnt);
+	clk_register_clkdev(clk, "pciex", NULL);
+	clks[pciex] = clk;
+
 	/* kfuse */
 	clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
 				    TEGRA_PERIPH_ON_APB,
@@ -1710,11 +1716,6 @@ static void __init tegra30_fixed_clk_init(void)
 				1, 0, &cml_lock);
 	clk_register_clkdev(clk, "cml1", NULL);
 	clks[cml1] = clk;
-
-	/* pciex */
-	clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
-	clk_register_clkdev(clk, "pciex", NULL);
-	clks[pciex] = clk;
 }
 
 static void __init tegra30_osc_clk_init(void)
@@ -1930,7 +1931,6 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
 	TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
 	TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
 	TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
-	TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
 	TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
 	TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
 };
-- 
1.7.0.4



From jagarwal at nvidia.com  Wed May  8 06:57:39 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 8 May 2013 16:27:39 +0530
Subject: [PATCH 3/4] ARM: dts: tegra: Correct PCIe entry
In-Reply-To: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
Message-ID: <1368010660-31465-3-git-send-email-jagarwal@nvidia.com>

- Add interrupt-names property
- Correct downstream I/O size
- Correct cml clock name for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.

Signed-off-by: Jay Agarwal <jagarwal at nvidia.com>
---
 arch/arm/boot/dts/tegra30.dtsi |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5a270ff..289ef93 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -124,7 +124,7 @@
 		reg-names = "pads", "afi", "cs";
 		interrupts = <0 98 0x04   /* controller interrupt */
 		              0 99 0x04>; /* MSI interrupt */
-
+		interrupt-names = "intr", "msi";
 		bus-range = <0x00 0xff>;
 		#address-cells = <3>;
 		#size-cells = <2>;
@@ -132,13 +132,13 @@
 		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
 			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
 			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
-			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
+			  0x81000000 0 0          0x02000000 0 0x00100000   /* downstream I/O */
 			  0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
 			  0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
 
 		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
 			 <&tegra_car 118>, <&tegra_car 215>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml0";
 		status = "disabled";
 
 		pci at 1,0 {
-- 
1.7.0.4



From jagarwal at nvidia.com  Wed May  8 06:57:38 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 8 May 2013 16:27:38 +0530
Subject: [PATCH 2/4] ARM: tegra: pcie: Add tegra3 support
In-Reply-To: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
Message-ID: <1368010660-31465-2-git-send-email-jagarwal@nvidia.com>

- Enable PCIe root port 2 for Cardhu
- Make private data structure for each SoC
- Add required Tegra30 clocks and regulators
- Add Tegra30 specific code in enable controller
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.

Signed-off-by: Jay Agarwal <jagarwal at nvidia.com>
---
 .../bindings/pci/nvidia,tegra20-pcie.txt           |    1 +
 drivers/pci/host/pci-tegra.c                       |  145 +++++++++++++++++---
 2 files changed, 127 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 1ebc526..b4c4e42 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -91,6 +91,7 @@ Board DTS:
 	pcie-controller {
 		vdd-supply = <&pci_vdd_reg>;
 		pex-clk-supply = <&pci_clk_reg>;
+		avdd-supply = <&ldo2_reg>; /* required for tegra30 */
 		status = "okay";
 
 		/* root port 00:01.0 */
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 24085ed..f7fc650 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -51,7 +51,6 @@
 #include <mach/powergate.h>
 
 #define INT_PCI_MSI_NR (8 * 32)
-#define TEGRA_MAX_PORTS 2
 
 /* register definitions */
 
@@ -143,14 +142,15 @@
 #define  AFI_INTR_EN_DFPCI_DECERR	(1 << 5)
 #define  AFI_INTR_EN_AXI_DECERR		(1 << 6)
 #define  AFI_INTR_EN_FPCI_TIMEOUT	(1 << 7)
+#define AFI_INTR_EN_PRSNT_SENSE		(1 << 8)
 
 #define AFI_PCIE_CONFIG					0x0f8
 #define  AFI_PCIE_CONFIG_PCIE_DISABLE(x)		(1 << ((x) + 1))
 #define  AFI_PCIE_CONFIG_PCIE_DISABLE_ALL		0xe
 #define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK	(0xf << 20)
 #define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE	(0x0 << 20)
-#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420	(0x0 << 20)
 #define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL	(0x1 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420	(0x0 << 20)
 #define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222	(0x1 << 20)
 #define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411	(0x2 << 20)
 
@@ -161,8 +161,11 @@
 #define AFI_PEX1_CTRL			0x118
 #define AFI_PEX2_CTRL			0x128
 #define  AFI_PEX_CTRL_RST		(1 << 0)
+#define  AFI_PEX_CTRL_CLKREQ_EN		(1 << 1)
 #define  AFI_PEX_CTRL_REFCLK_EN		(1 << 3)
 
+#define  AFI_PEXBIAS_CTRL_0		0x168
+
 #define RP_VEND_XP	0x00000F00
 #define  RP_VEND_XP_DL_UP	(1 << 30)
 
@@ -176,7 +179,8 @@
 #define  PADS_CTL_TX_DATA_EN_1L	(1 << 6)
 #define  PADS_CTL_RX_DATA_EN_1L	(1 << 10)
 
-#define PADS_PLL_CTL				0x000000B8
+#define  PADS_PLL_CTL_T20			0x000000B8
+#define  PADS_PLL_CTL_T30			0x000000B4
 #define  PADS_PLL_CTL_RST_B4SM			(1 << 1)
 #define  PADS_PLL_CTL_LOCKDET			(1 << 8)
 #define  PADS_PLL_CTL_REFCLK_MASK		(0x3 << 16)
@@ -184,8 +188,11 @@
 #define  PADS_PLL_CTL_REFCLK_INTERNAL_CMOS	(1 << 16)
 #define  PADS_PLL_CTL_REFCLK_EXTERNAL		(2 << 16)
 #define  PADS_PLL_CTL_TXCLKREF_MASK		(0x1 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_BUF_EN		(1 << 22)
 #define  PADS_PLL_CTL_TXCLKREF_DIV10		(0 << 20)
 #define  PADS_PLL_CTL_TXCLKREF_DIV5		(1 << 20)
+#define  PADS_REFCLK_CFG0			0x000000C8
+#define  PADS_REFCLK_CFG1			0x000000CC
 
 struct tegra_msi {
 	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
@@ -196,6 +203,19 @@ struct tegra_msi {
 	int irq;
 };
 
+/* used to differentiate tegra chips code */
+struct tegra_pcie_soc_data {
+	unsigned int num_max_ports;
+	unsigned int pads_pll_ctl;
+	unsigned int tx_ref_sel;
+	unsigned int msi_base_shift;
+	bool pex_clkreq_en;
+	bool pex_bias_ctrl;
+	bool intr_prsnt_sense;
+	bool has_avdd_supply;
+	bool has_cml0_clk;
+};
+
 static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip)
 {
 	return container_of(chip, struct tegra_msi, chip);
@@ -220,6 +240,7 @@ struct tegra_pcie {
 	struct clk *afi_clk;
 	struct clk *pcie_xclk;
 	struct clk *pll_e;
+	struct clk *cml0_clk;
 
 	struct tegra_msi msi;
 
@@ -229,6 +250,9 @@ struct tegra_pcie {
 
 	struct regulator *pex_clk_supply;
 	struct regulator *vdd_supply;
+	struct regulator *avdd_supply;
+
+	struct tegra_pcie_soc_data *soc_data;
 };
 
 struct tegra_pcie_port {
@@ -511,12 +535,15 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
 
 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 {
+	struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
 	unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
 	unsigned long value;
 
 	/* enable reference clock */
 	value = afi_readl(port->pcie, ctrl);
 	value |= AFI_PEX_CTRL_REFCLK_EN;
+	if (soc->pex_clkreq_en)
+		value |= AFI_PEX_CTRL_CLKREQ_EN;
 	afi_writel(port->pcie, value, ctrl);
 
 	tegra_pcie_port_reset(port);
@@ -569,6 +596,8 @@ static void tegra_pcie_fixup_class(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
 
 /* Tegra PCIE requires relaxed ordering */
 static void tegra_pcie_relax_enable(struct pci_dev *dev)
@@ -749,6 +778,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 	struct tegra_pcie_port *port;
 	unsigned int timeout;
 	unsigned long value;
+	struct tegra_pcie_soc_data *soc = pcie->soc_data;
+
+	/* power down to PCIe slot clock bias pad */
+	if (soc->pex_bias_ctrl)
+		afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
 
 	/* configure mode and disable all ports */
 	value = afi_readl(pcie, AFI_PCIE_CONFIG);
@@ -776,26 +810,26 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 	 * Set up PHY PLL inputs select PLLE output as refclock,
 	 * set TX ref sel to div10 (not div5).
 	 */
-	value = pads_readl(pcie, PADS_PLL_CTL);
+	value = pads_readl(pcie, soc->pads_pll_ctl);
 	value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
-	value |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
-	pads_writel(pcie, value, PADS_PLL_CTL);
+	value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
+	pads_writel(pcie, value, soc->pads_pll_ctl);
 
 	/* take PLL out of reset  */
-	value = pads_readl(pcie, PADS_PLL_CTL);
+	value = pads_readl(pcie, soc->pads_pll_ctl);
 	value |= PADS_PLL_CTL_RST_B4SM;
-	pads_writel(pcie, value, PADS_PLL_CTL);
+	pads_writel(pcie, value, soc->pads_pll_ctl);
 
 	/*
 	 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
 	 * This doesn't exist in the documentation.
 	 */
-	pads_writel(pcie, 0xfa5cfa5c, 0xc8);
+	pads_writel(pcie, 0xfa5cfa5c, PADS_REFCLK_CFG0);
 
 	/* wait for the PLL to lock */
 	timeout = 300;
 	do {
-		value = pads_readl(pcie, PADS_PLL_CTL);
+		value = pads_readl(pcie, soc->pads_pll_ctl);
 		usleep_range(1000, 1000);
 		if (--timeout == 0) {
 			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
@@ -824,6 +858,8 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 	value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
 		AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
 		AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
+	if (soc->intr_prsnt_sense)
+		value |= AFI_INTR_EN_PRSNT_SENSE;
 	afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
 	afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
 
@@ -838,6 +874,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 
 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
 {
+	struct tegra_pcie_soc_data *soc = pcie->soc_data;
 	int err;
 
 	/* TODO: disable and unprepare clocks? */
@@ -849,19 +886,26 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
 	tegra_pmc_pcie_xclk_clamp(true);
 
+	if (soc->has_avdd_supply) {
+		err = regulator_disable(pcie->avdd_supply);
+		if (err < 0)
+			dev_warn(pcie->dev, "failed to disable AVDD regulator: %d\n",
+			err);
+	}
 	err = regulator_disable(pcie->pex_clk_supply);
 	if (err < 0)
-		dev_err(pcie->dev, "failed to disable pex-clk regulator: %d\n",
+		dev_warn(pcie->dev, "failed to disable pex-clk regulator: %d\n",
 			err);
 
 	err = regulator_disable(pcie->vdd_supply);
 	if (err < 0)
-		dev_err(pcie->dev, "failed to disable VDD regulator: %d\n",
+		dev_warn(pcie->dev, "failed to disable VDD regulator: %d\n",
 			err);
 }
 
 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 {
+	struct tegra_pcie_soc_data *soc = pcie->soc_data;
 	int err;
 
 	tegra_periph_reset_assert(pcie->pcie_xclk);
@@ -885,6 +929,15 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 		return err;
 	}
 
+	if (soc->has_avdd_supply) {
+		err = regulator_enable(pcie->avdd_supply);
+		if (err < 0) {
+			dev_err(pcie->dev, "failed to enable AVDD regulator: %d\n",
+				err);
+			return err;
+		}
+	}
+
 	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
 						pcie->pex_clk);
 	if (err) {
@@ -902,6 +955,15 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 		return err;
 	}
 
+	if (soc->has_cml0_clk) {
+		err = clk_prepare_enable(pcie->cml0_clk);
+		if (err < 0) {
+			dev_err(pcie->dev, "failed to enable cml0 clock: %d\n",
+				err);
+			return err;
+		}
+	}
+
 	err = clk_prepare_enable(pcie->pll_e);
 	if (err < 0) {
 		dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
@@ -913,6 +975,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 
 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
 {
+	struct tegra_pcie_soc_data *soc = pcie->soc_data;
+
 	pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
 	if (IS_ERR(pcie->pex_clk))
 		return PTR_ERR(pcie->pex_clk);
@@ -929,6 +993,11 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
 	if (IS_ERR(pcie->pll_e))
 		return PTR_ERR(pcie->pll_e);
 
+	if (soc->has_cml0_clk) {
+		pcie->cml0_clk = devm_clk_get(pcie->dev, "cml0");
+		if (IS_ERR(pcie->cml0_clk))
+			return PTR_ERR(pcie->cml0_clk);
+	}
 	return 0;
 }
 
@@ -1151,6 +1220,7 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
 {
 	struct platform_device *pdev = to_platform_device(pcie->dev);
 	struct tegra_msi *msi = &pcie->msi;
+	struct tegra_pcie_soc_data *soc = pcie->soc_data;
 	unsigned long base;
 	int err;
 	u32 reg;
@@ -1187,7 +1257,7 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
 	msi->pages = __get_free_pages(GFP_KERNEL, 3);
 	base = virt_to_phys((void *)msi->pages);
 
-	afi_writel(pcie, base, AFI_MSI_FPCI_BAR_ST);
+	afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
 	afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
 	/* this register is in 4K increments */
 	afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
@@ -1284,6 +1354,7 @@ static u32 tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes)
 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
 {
 	struct device_node *np = pcie->dev->of_node, *port;
+	struct tegra_pcie_soc_data *soc = pcie->soc_data;
 	const __be32 *range = NULL;
 	struct resource res;
 	u32 lanes = 0;
@@ -1297,6 +1368,12 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
 	if (IS_ERR(pcie->pex_clk_supply))
 		return PTR_ERR(pcie->pex_clk_supply);
 
+	if (soc->has_avdd_supply) {
+		pcie->avdd_supply = devm_regulator_get(pcie->dev, "avdd");
+		if (IS_ERR(pcie->avdd_supply))
+			return PTR_ERR(pcie->avdd_supply);
+	}
+
 	while ((range = of_pci_process_ranges(np, &res, range)) != NULL) {
 		switch (res.flags & IORESOURCE_TYPE_BITS) {
 		case IORESOURCE_IO:
@@ -1341,7 +1418,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
 
 		index = PCI_SLOT(err);
 
-		if (index < 1 || index > TEGRA_MAX_PORTS) {
+		if (index < 1 || index > pcie->soc_data->num_max_ports) {
 			dev_err(pcie->dev, "invalid port number: %d\n", index);
 			return -EINVAL;
 		}
@@ -1477,8 +1554,39 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie)
 	return 0;
 }
 
+static const struct tegra_pcie_soc_data tegra20_pcie_data = {
+	.num_max_ports = 2,
+	.pads_pll_ctl = PADS_PLL_CTL_T20,
+	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+	.msi_base_shift = 0,
+	.pex_clkreq_en = false,
+	.pex_bias_ctrl = false,
+	.intr_prsnt_sense = false,
+	.has_avdd_supply = false,
+	.has_cml0_clk = false,
+};
+
+static const struct tegra_pcie_soc_data tegra30_pcie_data = {
+	.num_max_ports = 3,
+	.pads_pll_ctl = PADS_PLL_CTL_T30,
+	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+	.msi_base_shift = 8,
+	.pex_clkreq_en = true,
+	.pex_bias_ctrl = true,
+	.intr_prsnt_sense = true,
+	.has_avdd_supply = true,
+	.has_cml0_clk = true,
+};
+
+static const struct of_device_id tegra_pcie_of_match[] = {
+	{ .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data},
+	{ .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data},
+	{ },
+};
+
 static int tegra_pcie_probe(struct platform_device *pdev)
 {
+	const struct of_device_id *match;
 	struct tegra_pcie *pcie;
 	int err;
 
@@ -1489,6 +1597,10 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 	INIT_LIST_HEAD(&pcie->busses);
 	INIT_LIST_HEAD(&pcie->ports);
 	pcie->dev = &pdev->dev;
+	match = of_match_device(tegra_pcie_of_match, &pdev->dev);
+	if (!match)
+		return -ENODEV;
+	pcie->soc_data = (struct tegra_pcie_soc_data *)match->data;
 
 	err = tegra_pcie_parse_dt(pcie);
 	if (err < 0)
@@ -1560,11 +1672,6 @@ static int tegra_pcie_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id tegra_pcie_of_match[] = {
-	{ .compatible = "nvidia,tegra20-pcie", },
-	{ },
-};
-
 static struct platform_driver tegra_pcie_driver = {
 	.driver = {
 		.name = "tegra-pcie",
-- 
1.7.0.4



From jagarwal at nvidia.com  Wed May  8 06:57:40 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 8 May 2013 16:27:40 +0530
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
Message-ID: <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>

- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.

Signed-off-by: Jay Agarwal <jagarwal at nvidia.com>
---
 arch/arm/boot/dts/tegra30-cardhu.dtsi |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index d2fdf95..8f8e07b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -27,6 +27,17 @@
 	model = "NVIDIA Tegra30 Cardhu evaluation board";
 	compatible = "nvidia,cardhu", "nvidia,tegra30";
 
+	pcie-controller {
+		status = "okay";
+		pex-clk-supply = <&pex_hvdd_3v3_reg>;
+		vdd-supply = <&ldo1_reg>;
+		avdd-supply = <&ldo2_reg>;
+
+		pci at 3,0 {
+			status = "okay";
+		};
+	};
+
 	host1x {
 		dc at 54200000 {
 			rgb {
-- 
1.7.0.4



From stefano.stabellini at eu.citrix.com  Wed May  8 07:19:52 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 12:19:52 +0100
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <51892933.7090405@codeaurora.org>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
 <20130506143533.GF15278@phenom.dumpdata.com> <51892933.7090405@codeaurora.org>
Message-ID: <alpine.DEB.2.02.1305081217010.18865@kaball.uk.xensource.com>

On Tue, 7 May 2013, Christopher Covington wrote:
> Hi Konrad,
> 
> On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
> >>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
> >>> would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
> >>> where the timer goes off. Nor does it make sense to require that the
> >>> guest actually be running for 5 before injecting the timer because that
> >>> would mean real time elapsed time for the timer would be 5+3 in the case
> >>> where 3 are stolen.
> >>
> >> This is a bit of an aside, but I think that hiding time spent at higher
> >> privilege levels can be a quite sensible approach to timekeeping in a
> >> virtualized environment, but I understand that it's not the approach taken
> >> with Xen, and as you pointed out above, adjusting the Virtual Offset Register
> >> by itself isn't enough to implement that approach.
> > 
> > This is the approach taken by Xen and KVM. Look in CONFIG_PARAVIRT_CLOCK for
> > implementation. In the user-space, the entry in 'top' of "stolen" (%st)
> > is for this exact value.
> 
> I may have been unclear with my terms, sorry. When I refer to time being
> "hidden", I mean that kernel level software (supervisor mode, EL1) cannot
> detect the passage of that time at all. I don't know whether this would really
> work, but I imagine one might be able to get close with the current
> virtualization facilities for ARM.
> 
> Am I correct in interpreting that what you're referring to is the deployment
> of paravirtualization code that ensures (observable) "stolen" time is factored
> into kernel decision-making?

Although it might be possible to hide the real time flow from the VM, it
is inadvisable: what would happen when the VM needs to deal with a real
hardware device? Or just send packets over the network?  This is why it
is much safer and more reliable to expose the stolen ticks to the VM.


From cov at codeaurora.org  Wed May  8 07:48:17 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Wed, 08 May 2013 07:48:17 -0400
Subject: [Xen-devel] [PATCH 1/3] arm_arch_timer: introduce
 arch_timer_stolen_ticks
In-Reply-To: <alpine.DEB.2.02.1305081217010.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305011939180.5398@kaball.uk.xensource.com>
 <1367436460-10183-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <51817CBE.4050003@codeaurora.org>
 <1367482772.21869.26.camel@zakaz.uk.xensource.com>
 <5182DBA9.9080609@codeaurora.org>
 <20130506143533.GF15278@phenom.dumpdata.com>
 <51892933.7090405@codeaurora.org>
 <alpine.DEB.2.02.1305081217010.18865@kaball.uk.xensource.com>
Message-ID: <518A3B81.3080308@codeaurora.org>

On 05/08/2013 07:19 AM, Stefano Stabellini wrote:
> On Tue, 7 May 2013, Christopher Covington wrote:
>> Hi Konrad,
>>
>> On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
>>>>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
>>>>> would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
>>>>> where the timer goes off. Nor does it make sense to require that the
>>>>> guest actually be running for 5 before injecting the timer because that
>>>>> would mean real time elapsed time for the timer would be 5+3 in the case
>>>>> where 3 are stolen.
>>>>
>>>> This is a bit of an aside, but I think that hiding time spent at higher
>>>> privilege levels can be a quite sensible approach to timekeeping in a
>>>> virtualized environment, but I understand that it's not the approach taken
>>>> with Xen, and as you pointed out above, adjusting the Virtual Offset Register
>>>> by itself isn't enough to implement that approach.
>>>
>>> This is the approach taken by Xen and KVM. Look in CONFIG_PARAVIRT_CLOCK for
>>> implementation. In the user-space, the entry in 'top' of "stolen" (%st)
>>> is for this exact value.
>>
>> I may have been unclear with my terms, sorry. When I refer to time being
>> "hidden", I mean that kernel level software (supervisor mode, EL1) cannot
>> detect the passage of that time at all. I don't know whether this would really
>> work, but I imagine one might be able to get close with the current
>> virtualization facilities for ARM.
>>
>> Am I correct in interpreting that what you're referring to is the deployment
>> of paravirtualization code that ensures (observable) "stolen" time is factored
>> into kernel decision-making?
> 
> Although it might be possible to hide the real time flow from the VM, it
> is inadvisable: what would happen when the VM needs to deal with a real
> hardware device? Or just send packets over the network?  This is why it
> is much safer and more reliable to expose the stolen ticks to the VM.

One would probably have to emulate all the hardware. I don't mean to imply
that I think this is useful for everyday virtualization, but I speculate that
such an approach might enable the analysis of kernels infected with
VM-detecting malware or other niche use-cases.

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From kirill at shutemov.name  Wed May  8 08:44:17 2013
From: kirill at shutemov.name (Kirill A. Shutemov)
Date: Wed, 8 May 2013 15:44:17 +0300
Subject: [RFC PATCH v2 05/11] mm: thp: Correct the HPAGE_PMD_ORDER check.
In-Reply-To: <1368006763-30774-6-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-6-git-send-email-steve.capper@linaro.org>
Message-ID: <20130508124417.GA29631@shutemov.name>

On Wed, May 08, 2013 at 10:52:37AM +0100, Steve Capper wrote:
> All Transparent Huge Pages are allocated by the buddy allocator.
> 
> A compile time check is in place that fails when the order of a
> transparent huge page is too large to be allocated by the buddy
> allocator. Unfortunately that compile time check passes when:
> HPAGE_PMD_ORDER == MAX_ORDER
> ( which is incorrect as the buddy allocator can only allocate
> memory of order strictly less than MAX_ORDER. )

It looks confusing to me. Shouldn't we fix what MAX_ORDER means instead?

-- 
 Kirill A. Shutemov


From amit.virdi at st.com  Wed May  8 07:57:04 2013
From: amit.virdi at st.com (Amit Virdi)
Date: Wed, 8 May 2013 17:27:04 +0530
Subject: Problem in mounting flat filesystem with Kernel v3.9
Message-ID: <518A3D90.5060901@st.com>

Hi all,

For my MMU-less SoC, I'm facing problems with mounting the filesystem 
with Kernel versions 3.6 onwards.

I'm using a flat cramfs format FS.

This FS works perfectly till Kernel v3.5

However, when I rebase on v3.6 things start breaking. The Kernel doesn't 
boot at all. The processor generated Synchronous Data Abort exception 
because of alignment fault (during read operation). I debugged the code 
and noticed that start_kernel ran successfully till the end. It is the 
execution of rest_init that generates the alignment fault.

Same behavior was observed for v3.7.

With Kernel v3.8 and V3.9, the execution proceeds with probing of all 
the devices. However, here the Kernel couldn't mount the FS and is 
generating panic. The boot logs are:

-- 
<snip>
Creating 4 MTD partitions on "NOR":
0x000000000000-0x000000010000 : "X-loader"
0x000000010000-0x000000040000 : "U-Boot"
0x000000040000-0x000000240000 : "Kernel"
0x000000240000-0x000001000000 : "Root File System"
Warning: unable to open an initial console.
VFS: Cannot open root device "mtdblock3" or unknown-block(31,3): error -14
Please append a correct "root=" boot option; here are the available 
partitions:
1f00              64 mtdblock0  (driver?)
1f01             192 mtdblock1  (driver?)
1f02            2048 mtdblock2  (driver?)
1f03           14080 mtdblock3  (driver?)
Kernel panic - not syncing: VFS: Unable to mount root fs on 
unknown-block(31,3)
[<2000c9f8>] (unwind_backtrace+0x0/0xf8) from [<20186f10>] 
(panic+0x8c/0x1d8)
[<20186f10>] (panic+0x8c/0x1d8) from [<201f9d58>] 
(mount_block_root+0x1fc/0x2b8)
[<201f9d58>] (mount_block_root+0x1fc/0x2b8) from [<201fa0c0>] 
(prepare_namespace+0x160/0x1b8)
[<201fa0c0>] (prepare_namespace+0x160/0x1b8) from [<201f9a0c>] 
(kernel_init_freeable+0x168/0x1ac)
[<201f9a0c>] (kernel_init_freeable+0x168/0x1ac) from [<20186398>] 
(kernel_init+0x8/0xe4)
[<20186398>] (kernel_init+0x8/0xe4) from [<20008e98>] 
(ret_from_fork+0x14/0x3c)
-- 

Can anyone suggest what might be wrong here? Due to this filesystem 
mounting problem, I'm stuck with Kernel v3.5.

Regards
Amit Virdi


From steve.capper at linaro.org  Wed May  8 08:03:08 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Wed, 8 May 2013 13:03:08 +0100
Subject: [RFC PATCH v2 05/11] mm: thp: Correct the HPAGE_PMD_ORDER check.
In-Reply-To: <20130508124417.GA29631@shutemov.name>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-6-git-send-email-steve.capper@linaro.org>
 <20130508124417.GA29631@shutemov.name>
Message-ID: <20130508120307.GA1407@linaro.org>

On Wed, May 08, 2013 at 03:44:17PM +0300, Kirill A. Shutemov wrote:
> On Wed, May 08, 2013 at 10:52:37AM +0100, Steve Capper wrote:
> > All Transparent Huge Pages are allocated by the buddy allocator.
> > 
> > A compile time check is in place that fails when the order of a
> > transparent huge page is too large to be allocated by the buddy
> > allocator. Unfortunately that compile time check passes when:
> > HPAGE_PMD_ORDER == MAX_ORDER
> > ( which is incorrect as the buddy allocator can only allocate
> > memory of order strictly less than MAX_ORDER. )
> 
> It looks confusing to me. Shouldn't we fix what MAX_ORDER means instead?
> 

It confused me as I originally had 13 as the order and couldn't
allocate any 512MB THPs :-).

MAX_ORDER appears to be used quite a lot so I think it would be
safer to change the use case here rather than its meaning.

Cheers,
-- 
Steve


From stefano.stabellini at eu.citrix.com  Wed May  8 08:10:30 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 13:10:30 +0100
Subject: [PATCH 0/3] Xen ARM fixes for 3.10-RC1
Message-ID: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>

Hi all,
this small patch series fixes few Xen on ARM problems I found with more
testing:

- in order to work in dom0, we need to delay the initilization of the pm
  functions after arch_init;

- VCPUOP_register_vcpu_info needs to be executed by each online cpu
  separately;

- VCPUOP_register_vcpu_info is not actually supposed to fail.



Stefano Stabellini (3):
      xen/arm: initialize pm functions later
      xen/arm: do not handle VCPUOP_register_vcpu_info failures
      xen: rename xen_secondary_init and run it on every online cpu

 arch/arm/xen/enlighten.c |   34 +++++++++++++++-------------------
 1 files changed, 15 insertions(+), 19 deletions(-)


From stefano.stabellini at eu.citrix.com  Wed May  8 08:11:18 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 13:11:18 +0100
Subject: [PATCH 1/3] xen/arm: initialize pm functions later
In-Reply-To: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
Message-ID: <1368015080-5182-1-git-send-email-stefano.stabellini@eu.citrix.com>

If we are running in dom0, we have to wait for the arch specific code to
complete the initialization in order for us to successfully reset the
power_off and pm_restart functions.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index d30042e..83d13b0 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -272,12 +272,18 @@ static int __init xen_guest_init(void)
 	if (!xen_initial_domain())
 		xenbus_probe(NULL);
 
+	return 0;
+}
+core_initcall(xen_guest_init);
+
+static int __init xen_pm_init(void)
+{
 	pm_power_off = xen_power_off;
 	arm_pm_restart = xen_restart;
 
 	return 0;
 }
-core_initcall(xen_guest_init);
+subsys_initcall(xen_pm_init);
 
 static irqreturn_t xen_arm_callback(int irq, void *arg)
 {
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  8 08:11:19 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 13:11:19 +0100
Subject: [PATCH 2/3] xen/arm: do not handle VCPUOP_register_vcpu_info failures
In-Reply-To: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
Message-ID: <1368015080-5182-2-git-send-email-stefano.stabellini@eu.citrix.com>

We expect VCPUOP_register_vcpu_info to succeed, do not try to handle
failures.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   11 ++++-------
 1 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 83d13b0..519acf9 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -165,13 +165,10 @@ static int __init xen_secondary_init(unsigned int cpu)
 	info.offset = offset_in_page(vcpup);
 
 	err = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, cpu, &info);
-	if (err) {
-		pr_debug("register_vcpu_info failed: err=%d\n", err);
-	} else {
-		/* This cpu is using the registered vcpu info, even if
-		   later ones fail to. */
-		per_cpu(xen_vcpu, cpu) = vcpup;
-	}
+	if (err)
+		BUG();
+	per_cpu(xen_vcpu, cpu) = vcpup;
+
 	return 0;
 }
 
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  8 08:11:20 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 13:11:20 +0100
Subject: [PATCH 3/3] xen: rename xen_secondary_init and run it on every online
 cpu
In-Reply-To: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
Message-ID: <1368015080-5182-3-git-send-email-stefano.stabellini@eu.citrix.com>

Rename xen_secondary_init to xen_percpu_init.
Run xen_percpu_init on the each online cpu, reuse the current on_each_cpu call.
Merge xen_percpu_enable_events into xen_percpu_init.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   15 ++++-----------
 1 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 519acf9..ee86bfa 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -152,11 +152,12 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
 }
 EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 
-static int __init xen_secondary_init(unsigned int cpu)
+static void __init xen_percpu_init(void *unused)
 {
 	struct vcpu_register_vcpu_info info;
 	struct vcpu_info *vcpup;
 	int err;
+	int cpu = get_cpu();
 
 	pr_info("Xen: initializing cpu%d\n", cpu);
 	vcpup = per_cpu_ptr(xen_vcpu_info, cpu);
@@ -169,7 +170,7 @@ static int __init xen_secondary_init(unsigned int cpu)
 		BUG();
 	per_cpu(xen_vcpu, cpu) = vcpup;
 
-	return 0;
+	enable_percpu_irq(xen_events_irq, 0);
 }
 
 static void xen_restart(char str, const char *cmd)
@@ -205,7 +206,6 @@ static int __init xen_guest_init(void)
 	const char *version = NULL;
 	const char *xen_prefix = "xen,xen-";
 	struct resource res;
-	int i;
 
 	node = of_find_compatible_node(NULL, NULL, "xen,xen");
 	if (!node) {
@@ -262,8 +262,6 @@ static int __init xen_guest_init(void)
 			                       sizeof(struct vcpu_info));
 	if (xen_vcpu_info == NULL)
 		return -ENOMEM;
-	for_each_online_cpu(i)
-		xen_secondary_init(i);
 
 	gnttab_init();
 	if (!xen_initial_domain())
@@ -288,11 +286,6 @@ static irqreturn_t xen_arm_callback(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static __init void xen_percpu_enable_events(void *unused)
-{
-	enable_percpu_irq(xen_events_irq, 0);
-}
-
 static int __init xen_init_events(void)
 {
 	if (!xen_domain() || xen_events_irq < 0)
@@ -306,7 +299,7 @@ static int __init xen_init_events(void)
 		return -EINVAL;
 	}
 
-	on_each_cpu(xen_percpu_enable_events, NULL, 0);
+	on_each_cpu(xen_percpu_init, NULL, 0);
 
 	return 0;
 }
-- 
1.7.2.5



From arnd at arndb.de  Wed May  8 08:12:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 14:12:13 +0200
Subject: [PATCH v2] thermal: cpu_cooling: fix stub function
In-Reply-To: <51829A45.7040307@ti.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <201305021829.37343.arnd@arndb.de> <51829A45.7040307@ti.com>
Message-ID: <201305081412.14201.arnd@arndb.de>

On Thursday 02 May 2013, Eduardo Valentin wrote:
> Rui, Arnd,
> 
> On 02-05-2013 12:29, Arnd Bergmann wrote:
> > The function stub for cpufreq_cooling_get_level introduced
> > in 57df81069 "Thermal: exynos: fix cooling state translation"
> > is not syntactically correct C and needs to be fixed to avoid
> > this error:
> > 
> > In file included from drivers/thermal/db8500_thermal.c:20:0:
> >  include/linux/cpu_cooling.h: In function 'cpufreq_cooling_get_level':
> > include/linux/cpu_cooling.h:57:1:
> >  error: parameter name omitted  unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)  ^
> >  include/linux/cpu_cooling.h:57:1: error: parameter name omitted
> > 
> > Cc: Eduardo Valentin <eduardo.valentin at ti.com>
> > Cc: Zhang Rui <rui.zhang at intel.com>
> > Cc: Amit Daniel kachhap <amit.daniel at samsung.com>
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> 
> Acked-by: Eduardo Valentin <eduardo.valentin at ti.com>

Rui,

Could you please merge that into your thermal/next tree?  Right now,
linux-next fails to build because of this, and you probably don't
want to send the current version to Linus without fixing it.

	Arnd


From jaccon.bastiaansen at gmail.com  Wed May  8 08:14:40 2013
From: jaccon.bastiaansen at gmail.com (Jaccon Bastiaansen)
Date: Wed, 8 May 2013 14:14:40 +0200
Subject: [RFC] Bug in ARM v6+ implementation of cmpxchg64() ?
Message-ID: <CAGzjT4cikbZ4rRJxzMM4P0MZYpWumYC15qVW3OaPd7GESS5mwg@mail.gmail.com>

Hello,

The ARM implementation of cmpxchg64() for ARM arch v6 and v7 casts
parameter 2 and 3 (the old and new 64 values) to an unsigned long
before calling the atomic_cmpxchg64() function:

#define cmpxchg64(ptr, o, n) \
((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr), \
atomic64_t, \
counter), \
     (unsigned long)(o), \
     (unsigned long)(n)))


To me it seems that now the top 32 bits of the old and new value are
stripped before calling atomic64_cmpxchg(), causing incorrect value to
be "compare-exchanged". Is this correct?

Browsing in the git history, I found commit

3e0f5a15f5003f4576c35498814f0f1567860449

which changed
-#define cmpxchg64(ptr,o,n)                                             \
-       ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),                      \
-                                           (unsigned long long)(o),    \
-                                           (unsigned long long)(n)))


into

+#define cmpxchg64(ptr, o, n)                                           \
+       ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr),       \
+                                               atomic64_t,             \
+                                               counter),               \
+                                             (unsigned long)(o),       \
+                                             (unsigned long)(n)))



Regards,
  Jaccon


From arnd at arndb.de  Wed May  8 08:16:06 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 14:16:06 +0200
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <20130501225748.GD6517@verge.net.au>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>
 <20130501225748.GD6517@verge.net.au>
Message-ID: <201305081416.06611.arnd@arndb.de>

On Thursday 02 May 2013, Simon Horman wrote:
> > > diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
> > > index 8871f77..5dc57f1 100644
> > > --- a/arch/arm/mach-shmobile/intc-r8a7740.c
> > > +++ b/arch/arm/mach-shmobile/intc-r8a7740.c
> > > @@ -53,14 +53,23 @@ static void __init r8a7740_init_irq_common(void)
> > >
> > >  void __init r8a7740_init_irq_of(void)
> > >  {
> > > +       if (!IS_ENABLED(CONFIG_OF))
> > > +               return;
> > > +
> > >         irqchip_init();
> > 
> > Why not have an empty irqchip_init? I'd guess we'll need this on other
> > platforms and your default mach.
> 
> Thanks, I think that could work.
> 
> I will see about making it so.

Ping

Linux-next is still broken for me. There is also anothe shmobile build bug,
I'll send a separate patch for that, which also needs to go into your tree.

	Arnd


From Ian.Campbell at citrix.com  Wed May  8 08:17:01 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Wed, 8 May 2013 13:17:01 +0100
Subject: [PATCH 2/3] xen/arm: do not handle VCPUOP_register_vcpu_info
 failures
In-Reply-To: <1368015080-5182-2-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305081303310.18865@kaball.uk.xensource.com>
 <1368015080-5182-2-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <1368015421.26321.263.camel@zakaz.uk.xensource.com>

On Wed, 2013-05-08 at 13:11 +0100, Stefano Stabellini wrote:
> We expect VCPUOP_register_vcpu_info to succeed, do not try to handle
> failures.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   11 ++++-------
>  1 files changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 83d13b0..519acf9 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -165,13 +165,10 @@ static int __init xen_secondary_init(unsigned int cpu)
>  	info.offset = offset_in_page(vcpup);
>  
>  	err = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, cpu, &info);
> -	if (err) {
> -		pr_debug("register_vcpu_info failed: err=%d\n", err);
> -	} else {
> -		/* This cpu is using the registered vcpu info, even if
> -		   later ones fail to. */
> -		per_cpu(xen_vcpu, cpu) = vcpup;
> -	}
> +	if (err)
> +		BUG();

AKA BUG_ON(err);

Acked-by: Ian Campbell <ian.campbell at citrix.com>

> +	per_cpu(xen_vcpu, cpu) = vcpup;
> +
>  	return 0;
>  }
>  




From arnd at arndb.de  Wed May  8 08:18:04 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 14:18:04 +0200
Subject: [PATCH] ARM: shmobile: fix sleep-r8a7740.S miscompiles
Message-ID: <201305081418.05091.arnd@arndb.de>

The newly added sleep-r8a7740.S file in shmobile does not
actually build because of renamed symbols.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Bastian Hecht <hechtb+renesas at gmail.com>
Cc: Simon Horman <horms+renesas at verge.net.au>
---

Simon, please apply to whichever branch of yours has the broken commit,
or fold this patch into Bastian's patch.

linux-next doesn't build for me because of this, mainline is still fine.

diff --git a/arch/arm/mach-shmobile/sleep-r8a7740.S b/arch/arm/mach-shmobile/sleep-r8a7740.S
index 435531b..982eacb 100644
--- a/arch/arm/mach-shmobile/sleep-r8a7740.S
+++ b/arch/arm/mach-shmobile/sleep-r8a7740.S
@@ -32,7 +32,7 @@ ENTRY(r8a7740_shutdown)
 wfi_loop:
 	bl	cpu_v7_do_idle
 	b wfi_loop
-ENDPROC(r8a7740)
+ENDPROC(r8a7740_shutdown)
 
 	.text
 ENTRY(v7_cpu_resume)
@@ -53,5 +53,5 @@ ENDPROC(v7_cpu_resume)
 ENTRY(r8a7740_resume)
 	ldr	pc, 1f
 1:	.long	v7_cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(r8a7740_resume_core_standby)
+ENDPROC(r8a7740_resume)
 #endif


From giridhar.maruthy at linaro.org  Wed May  8 08:23:04 2013
From: giridhar.maruthy at linaro.org (Giridhar Maruthy)
Date: Wed, 8 May 2013 17:53:04 +0530
Subject: [RFC PATCH V2] ARM: EXYNOS: Fix hotplug when CPUs boot in HYP mode
In-Reply-To: <5188C18D.10103@arm.com>
References: <1367905910-30913-1-git-send-email-giridhar.m@samsung.com>
 <CAHuqX+HUWcX_sTXKCjSQ9pR1K8obLc+T7vYK_zTn_gqO8ULPVQ@mail.gmail.com>
 <5188C18D.10103@arm.com>
Message-ID: <CAHuqX+GOLO_H81B3bwcqF7Sp0srctBn+6J9mbRF_kbPRTXC-ng@mail.gmail.com>

On 7 May 2013 14:25, Marc Zyngier <marc.zyngier at arm.com> wrote:
> On 07/05/13 06:54, Giridhar Maruthy wrote:
>> This patch is a modification from the Christoffer Dall's u-boot
>> patch. This is required to put the secondary processors in hyp
>> mode during cpu hotplug when u-boot is no longer alive.
>>
>> Marc Zyngier suggested this logic to go into firmware or, u-boot
>> putting a trampoline code into a page /memreserve/d by DT. But
>> this seemed to have a problem. Once the cpu is hotplugged in
>> runtime, the control is in ROM code and waits for event.
>> Kernel provides a return address in kernel to which the processor
>> jumps once it gets an event. If the control branches to the
>> trampoline code here, this trampoline code has no kernel return
>> address.
>>
>> Someone with better logic or better placement of this logic
>> elsewhere is welcome.
>
> What prevents you from writing the kernel address in the memreserved
> page? Some obvious location, like the last word of the page? You only
> have to do it once (from the boot CPU, for example).
>
> Or did I miss something else?

Thanks Marc, I think I understand now.

I guess I also need to put the primary cpu boot mode into a temporary location.

-Giridhar


From will.deacon at arm.com  Wed May  8 08:46:40 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 13:46:40 +0100
Subject: [RFC] Bug in ARM v6+ implementation of cmpxchg64() ?
In-Reply-To: <CAGzjT4cikbZ4rRJxzMM4P0MZYpWumYC15qVW3OaPd7GESS5mwg@mail.gmail.com>
References: <CAGzjT4cikbZ4rRJxzMM4P0MZYpWumYC15qVW3OaPd7GESS5mwg@mail.gmail.com>
Message-ID: <20130508124639.GA339@mudshark.cambridge.arm.com>

On Wed, May 08, 2013 at 01:14:40PM +0100, Jaccon Bastiaansen wrote:
> Hello,

Hi Jaccon,

> The ARM implementation of cmpxchg64() for ARM arch v6 and v7 casts
> parameter 2 and 3 (the old and new 64 values) to an unsigned long
> before calling the atomic_cmpxchg64() function:
> 
> #define cmpxchg64(ptr, o, n) \
> ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr), \
> atomic64_t, \
> counter), \
>      (unsigned long)(o), \
>      (unsigned long)(n)))
> 
> 
> To me it seems that now the top 32 bits of the old and new value are
> stripped before calling atomic64_cmpxchg(), causing incorrect value to
> be "compare-exchanged". Is this correct?
> 
> Browsing in the git history, I found commit
> 
> 3e0f5a15f5003f4576c35498814f0f1567860449
> 
> which changed
> -#define cmpxchg64(ptr,o,n)                                             \
> -       ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),                      \
> -                                           (unsigned long long)(o),    \
> -                                           (unsigned long long)(n)))
> 
> 
> into
> 
> +#define cmpxchg64(ptr, o, n)                                           \
> +       ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr),       \
> +                                               atomic64_t,             \
> +                                               counter),               \
> +                                             (unsigned long)(o),       \
> +                                             (unsigned long)(n)))

Damn, that's what happens when you work on arm and arm64 in parallel. Yes,
this is a bug.

Wondering why this hasn't been spotted until now, I grepped around and it
looks like the only user is sched_clock. Since ARM's sched_clock is 32-bit
only (patches are currently in the works iirc), it seems as though we've
managed to get away with this.

Are you happy to send a patch fixing the casts please?

Cheers,

Will


From marc.zyngier at arm.com  Wed May  8 08:57:26 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 08 May 2013 13:57:26 +0100
Subject: [RFC PATCH V2] ARM: EXYNOS: Fix hotplug when CPUs boot in HYP mode
In-Reply-To: <CAHuqX+GOLO_H81B3bwcqF7Sp0srctBn+6J9mbRF_kbPRTXC-ng@mail.gmail.com>
References: <1367905910-30913-1-git-send-email-giridhar.m@samsung.com>
 <CAHuqX+HUWcX_sTXKCjSQ9pR1K8obLc+T7vYK_zTn_gqO8ULPVQ@mail.gmail.com>
 <5188C18D.10103@arm.com>
 <CAHuqX+GOLO_H81B3bwcqF7Sp0srctBn+6J9mbRF_kbPRTXC-ng@mail.gmail.com>
Message-ID: <518A4BB6.5020801@arm.com>

On 08/05/13 13:23, Giridhar Maruthy wrote:
> On 7 May 2013 14:25, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> On 07/05/13 06:54, Giridhar Maruthy wrote:
>>> This patch is a modification from the Christoffer Dall's u-boot
>>> patch. This is required to put the secondary processors in hyp
>>> mode during cpu hotplug when u-boot is no longer alive.
>>>
>>> Marc Zyngier suggested this logic to go into firmware or, u-boot
>>> putting a trampoline code into a page /memreserve/d by DT. But
>>> this seemed to have a problem. Once the cpu is hotplugged in
>>> runtime, the control is in ROM code and waits for event.
>>> Kernel provides a return address in kernel to which the processor
>>> jumps once it gets an event. If the control branches to the
>>> trampoline code here, this trampoline code has no kernel return
>>> address.
>>>
>>> Someone with better logic or better placement of this logic
>>> elsewhere is welcome.
>>
>> What prevents you from writing the kernel address in the memreserved
>> page? Some obvious location, like the last word of the page? You only
>> have to do it once (from the boot CPU, for example).
>>
>> Or did I miss something else?
> 
> Thanks Marc, I think I understand now.
> 
> I guess I also need to put the primary cpu boot mode into a temporary location.

Indeed. You'll need that for your secondaries to enter in the same mode
as the primary.

	M.
-- 
Jazz is not dead. It just smells funny...



From shawn.guo at linaro.org  Wed May  8 09:05:52 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 21:05:52 +0800
Subject: [PATCH 0/3] ARM: imx/mxs: fixes for 3.10-rc1
Message-ID: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>

Hi Arnd, Olof,

It seems that you will have a few other fixes to send mainline for
3.10-rc1 inclusion before merge window closes.  In that case, can you
please include the following 3 which fix imx/mxs compile errors that
are currently seen on mainline?

Shawn

Fabio Estevam (2):
  ARM: imx: Select GENERIC_ALLOCATOR
  video: mxsfb: Adapt to new videomode API

Shawn Guo (1):
  ARM: imx: compile fix for hotplug.c

 arch/arm/mach-imx/Kconfig              |    5 +--
 arch/arm/mach-imx/Makefile             |    1 -
 arch/arm/mach-imx/common.h             |    1 +
 arch/arm/mach-imx/hotplug.c            |    2 +
 arch/arm/mach-imx/iram_alloc.c         |   73 --------------------------------
 drivers/video/Kconfig                  |    2 +-
 drivers/video/mxsfb.c                  |    8 ++--
 include/linux/platform_data/imx-iram.h |   41 ------------------
 8 files changed, 9 insertions(+), 124 deletions(-)
 delete mode 100644 arch/arm/mach-imx/iram_alloc.c
 delete mode 100644 include/linux/platform_data/imx-iram.h

-- 
1.7.9.5




From shawn.guo at linaro.org  Wed May  8 09:05:53 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 21:05:53 +0800
Subject: [PATCH 1/3] ARM: imx: compile fix for hotplug.c
In-Reply-To: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
References: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368018355-26014-2-git-send-email-shawn.guo@linaro.org>

Commit bca7a5a (ARM: cpu hotplug: remove majority of cache flushing
from platforms) removes include of <asm/cacheflush.h> and hence
discovers a few indirect inclusion and declaration problems as below.

  CC      arch/arm/mach-imx/hotplug.o
In file included from arch/arm/mach-imx/hotplug.c:16:0:
arch/arm/mach-imx/common.h:100:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
arch/arm/mach-imx/common.h:101:29: warning: ?struct pt_regs? declared inside parameter list [enabled by default]
arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_die?:
arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ?cpu_do_idle? [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c: In function ?imx_cpu_kill?:
arch/arm/mach-imx/hotplug.c:58:26: error: ?jiffies? undeclared (first use in this function)
arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ?msecs_to_jiffies? [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ?time_after? [-Werror=implicit-function-declaration]

Fix them by adding the needed inclusion and declaration.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/common.h  |    1 +
 arch/arm/mach-imx/hotplug.c |    2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4cba7db..c08ae3f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -12,6 +12,7 @@
 #define __ASM_ARCH_MXC_COMMON_H__
 
 struct platform_device;
+struct pt_regs;
 struct clk;
 enum mxc_cpu_pwr_mode;
 
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 5e91112..3daf1ed 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -11,7 +11,9 @@
  */
 
 #include <linux/errno.h>
+#include <linux/jiffies.h>
 #include <asm/cp15.h>
+#include <asm/proc-fns.h>
 
 #include "common.h"
 
-- 
1.7.9.5




From shawn.guo at linaro.org  Wed May  8 09:05:54 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 21:05:54 +0800
Subject: [PATCH 2/3] ARM: imx: Select GENERIC_ALLOCATOR
In-Reply-To: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
References: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368018355-26014-3-git-send-email-shawn.guo@linaro.org>

From: Fabio Estevam <fabio.estevam at freescale.com>

Since commit 657eee7 (media: coda: use genalloc API) the following build
error happens with imx_v4_v5_defconfig:

drivers/built-in.o: In function 'coda_remove':
clk-composite.c:(.text+0x112180): undefined reference to 'gen_pool_free'
drivers/built-in.o: In function 'coda_probe':
clk-composite.c:(.text+0x112310): undefined reference to 'of_get_named_gen_pool'
clk-composite.c:(.text+0x1123f4): undefined reference to 'gen_pool_alloc'
clk-composite.c:(.text+0x11240c): undefined reference to 'gen_pool_virt_to_phys'
clk-composite.c:(.text+0x112458): undefined reference to 'dev_get_gen_pool'

Select GENERIC_ALLOCATOR and get rid of the custom IRAM_ALLOC.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig              |    5 +--
 arch/arm/mach-imx/Makefile             |    1 -
 arch/arm/mach-imx/iram_alloc.c         |   73 --------------------------------
 include/linux/platform_data/imx-iram.h |   41 ------------------
 4 files changed, 1 insertion(+), 119 deletions(-)
 delete mode 100644 arch/arm/mach-imx/iram_alloc.c
 delete mode 100644 include/linux/platform_data/imx-iram.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 78f795d..ba44328 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -5,6 +5,7 @@ config ARCH_MXC
 	select AUTO_ZRELADDR if !ZBOOT_ROM
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
+	select GENERIC_ALLOCATOR
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_IRQ_CHIP
 	select MULTI_IRQ_HANDLER
@@ -61,10 +62,6 @@ config MXC_ULPI
 config ARCH_HAS_RNGA
 	bool
 
-config IRAM_ALLOC
-	bool
-	select GENERIC_ALLOCATOR
-
 config HAVE_IMX_ANATOP
 	bool
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9309589..70ae7c4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 
-obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/arch/arm/mach-imx/iram_alloc.c b/arch/arm/mach-imx/iram_alloc.c
deleted file mode 100644
index e05cf40..0000000
--- a/arch/arm/mach-imx/iram_alloc.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/genalloc.h>
-#include "linux/platform_data/imx-iram.h"
-
-static unsigned long iram_phys_base;
-static void __iomem *iram_virt_base;
-static struct gen_pool *iram_pool;
-
-static inline void __iomem *iram_phys_to_virt(unsigned long p)
-{
-	return iram_virt_base + (p - iram_phys_base);
-}
-
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-	if (!iram_pool)
-		return NULL;
-
-	*dma_addr = gen_pool_alloc(iram_pool, size);
-	pr_debug("iram alloc - %dB at 0x%lX\n", size, *dma_addr);
-	if (!*dma_addr)
-		return NULL;
-	return iram_phys_to_virt(*dma_addr);
-}
-EXPORT_SYMBOL(iram_alloc);
-
-void iram_free(unsigned long addr, unsigned int size)
-{
-	if (!iram_pool)
-		return;
-
-	gen_pool_free(iram_pool, addr, size);
-}
-EXPORT_SYMBOL(iram_free);
-
-int __init iram_init(unsigned long base, unsigned long size)
-{
-	iram_phys_base = base;
-
-	iram_pool = gen_pool_create(PAGE_SHIFT, -1);
-	if (!iram_pool)
-		return -ENOMEM;
-
-	gen_pool_add(iram_pool, base, size, -1);
-	iram_virt_base = ioremap(iram_phys_base, size);
-	if (!iram_virt_base)
-		return -EIO;
-
-	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, iram_virt_base);
-	return 0;
-}
diff --git a/include/linux/platform_data/imx-iram.h b/include/linux/platform_data/imx-iram.h
deleted file mode 100644
index 022690c..0000000
--- a/include/linux/platform_data/imx-iram.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/errno.h>
-
-#ifdef CONFIG_IRAM_ALLOC
-
-int __init iram_init(unsigned long base, unsigned long size);
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
-void iram_free(unsigned long dma_addr, unsigned int size);
-
-#else
-
-static inline int __init iram_init(unsigned long base, unsigned long size)
-{
-	return -ENOMEM;
-}
-
-static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-	return NULL;
-}
-
-static inline void iram_free(unsigned long base, unsigned long size) {}
-
-#endif
-- 
1.7.9.5




From shawn.guo at linaro.org  Wed May  8 09:05:55 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 21:05:55 +0800
Subject: [PATCH 3/3] video: mxsfb: Adapt to new videomode API
In-Reply-To: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
References: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368018355-26014-4-git-send-email-shawn.guo@linaro.org>

From: Fabio Estevam <fabio.estevam at freescale.com>

commit 6cd2c7db4 (videomode: videomode_from_timing work) changed the name of
the function from videomode_from_timing() to videomode_from_timings().

commit 32ed6ef1 (videomode: create enum for videomode's display flags) changed
the 'data_flags' field in videomode structure to 'flags'

Adapt to these changes in order to fix the following errors:

drivers/video/mxsfb.c:761:3: error: too many arguments to function 'videomode_from_timing'
drivers/video/mxsfb.c:761:7: error: void value not ignored as it ought to be
drivers/video/mxsfb.c:768:9: error: 'struct videomode' has no member named 'data_flags'
drivers/video/mxsfb.c:770:9: error: 'struct videomode' has no member named 'data_flags'

Also, select VIDEOMODE_HELPER instead of OF_VIDEOMODE, as this one is
deprecated.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/video/Kconfig |    2 +-
 drivers/video/mxsfb.c |    8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index c04ccdf..1687058 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2429,7 +2429,7 @@ config FB_MXS
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
 	select FB_MODE_HELPERS
-	select OF_VIDEOMODE
+	select VIDEOMODE_HELPERS
 	help
 	  Framebuffer support for the MXS SoC.
 
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 1b2c26d..21223d4 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -42,7 +42,6 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/of_device.h>
-#include <video/of_display_timing.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
@@ -50,6 +49,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/fb.h>
 #include <linux/regulator/consumer.h>
+#include <video/of_display_timing.h>
 #include <video/videomode.h>
 
 #define REG_SET	4
@@ -777,16 +777,16 @@ static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
 		struct videomode vm;
 		struct fb_videomode fb_vm;
 
-		ret = videomode_from_timing(timings, &vm, i);
+		ret = videomode_from_timings(timings, &vm, i);
 		if (ret < 0)
 			goto put_timings_node;
 		ret = fb_videomode_from_videomode(&vm, &fb_vm);
 		if (ret < 0)
 			goto put_timings_node;
 
-		if (vm.data_flags & DISPLAY_FLAGS_DE_HIGH)
+		if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 			host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
-		if (vm.data_flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+		if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 			host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
 		fb_add_videomode(&fb_vm, &fb_info->modelist);
 	}
-- 
1.7.9.5




From hechtb at gmail.com  Wed May  8 09:20:04 2013
From: hechtb at gmail.com (Bastian Hecht)
Date: Wed,  8 May 2013 15:20:04 +0200
Subject: [PATCH] irqchip: Add irqchip_init dummy function
Message-ID: <1368019204-24448-1-git-send-email-hechtb+renesas@gmail.com>

We add an empty irqchip_init dummy function for cases in which
CONFIG_IRQCHIP is not used. In these cases irqchip.c is not compiled,
but a funtion call may still be present in architecture code, that in
runtime doesn't get hit.

E.g. this is needed in the arch/arm/mach-shmobile/intc-r8a7740.c
interrupt setup code where OF use and non OF us is both handled in one
file.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
---
 include/linux/irqchip.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
index e0006f1..78527ba 100644
--- a/include/linux/irqchip.h
+++ b/include/linux/irqchip.h
@@ -11,6 +11,10 @@
 #ifndef _LINUX_IRQCHIP_H
 #define _LINUX_IRQCHIP_H
 
+#ifdef CONFIG_IRQCHIP
 void irqchip_init(void);
+#else
+void irqchip_init(void) {};
+#endif
 
 #endif
-- 
1.7.9.5



From hechtb at gmail.com  Wed May  8 09:22:22 2013
From: hechtb at gmail.com (Bastian Hecht)
Date: Wed, 8 May 2013 15:22:22 +0200
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <201305081416.06611.arnd@arndb.de>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>
 <20130501225748.GD6517@verge.net.au>
 <201305081416.06611.arnd@arndb.de>
Message-ID: <CABYn4sxrcGmnTAJcQR23nMGy8JvqyDrgPOXF4yBFFU_4C8Pc_g@mail.gmail.com>

Hi,

2013/5/8 Arnd Bergmann <arnd at arndb.de>:
> On Thursday 02 May 2013, Simon Horman wrote:
>> > > diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
>> > > index 8871f77..5dc57f1 100644
>> > > --- a/arch/arm/mach-shmobile/intc-r8a7740.c
>> > > +++ b/arch/arm/mach-shmobile/intc-r8a7740.c
>> > > @@ -53,14 +53,23 @@ static void __init r8a7740_init_irq_common(void)
>> > >
>> > >  void __init r8a7740_init_irq_of(void)
>> > >  {
>> > > +       if (!IS_ENABLED(CONFIG_OF))
>> > > +               return;
>> > > +
>> > >         irqchip_init();
>> >
>> > Why not have an empty irqchip_init? I'd guess we'll need this on other
>> > platforms and your default mach.
>>
>> Thanks, I think that could work.
>>
>> I will see about making it so.
>
> Ping

I have sent out a patch adding an empty irqchip_init() when
CONFIG_IRQCHIP is not set with the subject
[PATCH] irqchip: Add irqchip_init dummy function

> Linux-next is still broken for me. There is also anothe shmobile build bug,
> I'll send a separate patch for that, which also needs to go into your tree.

Oh thanks Arnd for this fix!

Cheers,

 Bastian


From jason at lakedaemon.net  Wed May  8 09:25:53 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 8 May 2013 09:25:53 -0400
Subject: [PATCH 1/3] clk: mvebu: add gate ctrl for Prestera kirkwood
 variants
In-Reply-To: <5189FD04.8090308@gmail.com>
References: <1367941941-19152-1-git-send-email-valentin.longchamp@keymile.com>
 <1367941941-19152-2-git-send-email-valentin.longchamp@keymile.com>
 <518927C0.6070600@free-electrons.com> <51892D8D.4060704@gmail.com>
 <5189F900.6020809@keymile.com> <5189FD04.8090308@gmail.com>
Message-ID: <20130508132553.GB31290@titan.lakedaemon.net>

On Wed, May 08, 2013 at 09:21:40AM +0200, Sebastian Hesselbarth wrote:
> On 05/08/2013 09:04 AM, Valentin Longchamp wrote:
> >On 05/07/2013 06:36 PM, Sebastian Hesselbarth wrote:
> >>I just checked my mails from late 2012 and there Valentin and I agreed,
> >>that not the missing bits in clock gating control registers was the root
> >>cause of km_kirkwood to hang. It was rather the phy gates (that do not/
> >>not yet exist on DT) that caused it to hang, i.e. when accessing SATA
> >>PHY registers.
> >
> >Yeah you are right, I had forgotten about this test. I just had a look at the
> >board-km_kirkwood.c and I tried to figure out a way to make sure the clock gates
> >bits never get read/written, so never get initialized. But as you say, that's
> >not the real cause of the hang but
> >
> >>Valentin, I am not against an extra clock-gating-ctrl for Prestera but
> >>maybe having an kirkwood.dtsi fork without SATA and other peripherals
> >>will also help?
> >
> >Since it's not the real problem having the extra clock-gating-ctrl would me more
> >consistent with the real Prestera HW, but maybe it's better to keep only one
> >that works for both as it's already the case, it's less code to maintain.
> >
> >A better approach would be to work on the kirkwood.dtsi as you mention it. The
> >SATA node in kirkwood.dtsi is by default disabled, is this enough or should it
> >be moved to kirkwood-6281.dtsi for instance ?
> 
> Valentin,
> 
> I guess for the long run, we will re-introduce phy gates either by
> abusing clk gates or some other way. But they will depend on existing
> OF nodes.
> 
> Considering this, it would be best to fork kirkwood.dtsi for Prestera
> and leave out all OF nodes that are not implemented there. We could
> have
> 
> kirkwood.dtsi -+-> kirkwood-kirkwood.dtsi -+-> kirkwood-6281.dtsi
>                +-> kirkwood-prestera.dtsi  +-> kirkwood-6282.dtsi

or,

kirkwood.dtsi
prestera.dtsi

-pinctrl-
kirkwood-98dx4122.dtsi (should rename to prestera-, but seems churn-ish)
kirkwood-6281.dtsi
kirkwood-6282.dtsi

-dts-
kirkwood-km_kirkwood.dts (rename/churn prestera-?)
  |-prestera.dtsi
  \-kirkwood-98dx4122.dtsi

or, honestly, how many boards are going to be based on prestera?  If
it's just the one, why not combine all the nodes into
kirkwood-km_kirkwood.dts?


thx,

Jason.


From shawn.guo at linaro.org  Wed May  8 09:25:52 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 21:25:52 +0800
Subject: [PATCH] ARM: imx: compile fix for hotplug.c
In-Reply-To: <20130508074810.GN23285@pengutronix.de>
References: <1367474331-3479-1-git-send-email-shawn.guo@linaro.org>
 <20130508074810.GN23285@pengutronix.de>
Message-ID: <20130508132549.GA26072@S2101-09.ap.freescale.net>

Hi Uwe,

On Wed, May 08, 2013 at 09:48:10AM +0200, Uwe Kleine-K?nig wrote:
> I just sent an equivalent patch for that issue (so:
> Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Thanks.

> ).
> 
> Is this patch already queued somewhere?
> 
I just resend it to Arnd for 3.10-rc1 inclusion.

Shawn



From lee.jones at linaro.org  Wed May  8 09:29:00 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:00 +0100
Subject: [PATCH 0/9] Important ux500 fixups due for the v3.10 -rc:s
Message-ID: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>

This patch-set straightens out some serious errors incurred during
the v3.10 merge window, including:

Patch 1: Possible over-write of DB8500-PRCMU platform data
Patch 2: Fail to register AB8500 GPIO driver
Patch 3: Fail to start Ethernet when using ATAGS - Clocks
Patch 4: Fail to probe DB8500 Thermal driver - No pdata
Patch 5: Fail to use Early Printk - Incorrect virtual addresses
Patch 6: Fail to start Ethernet with using Device Tree - Clocks
Patch 7: Oops kernel during driver fail - Null pointer
Patch 8: Fail to probe AB8500 GPIO driver - Incorrect platform ID
Patch 8: Fail to probe AB8500 GPADC driver - Regulators

 arch/arm/include/debug/ux500.S     |    6 +++---
 arch/arm/mach-ux500/board-mop500.c |    6 +++---
 arch/arm/mach-ux500/cpu-db8500.c   |    6 ++----
 arch/arm/mach-ux500/setup.h        |    2 +-
 drivers/clk/ux500/u8500_clk.c      |    2 +-
 drivers/mfd/ab8500-core.c          |    9 ++++++---
 drivers/mfd/db8500-prcmu.c         |    1 +
 drivers/pinctrl/pinctrl-abx500.c   |   30 ++++++++++++++----------------
 8 files changed, 31 insertions(+), 31 deletions(-)



From lee.jones at linaro.org  Wed May  8 09:29:01 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:01 +0100
Subject: [PATCH 1/9] ARM: ux500: Remove duplicated assignment of
 ab8500_platdata
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-2-git-send-email-lee.jones@linaro.org>

Since: "05ec260 mfd: db8500-prcmu: update resource passing", the AB8500's
platform data 'ab8500_platdata' is passed directly as an attribute to
'db8500_prcmu_pdata', so there's no requirement to assign it a second
time. In fact, it's only due to an ordering issue that the entire
'db8500_prcmu_pdata' data structure isn't completely over-written by the
assignment in u8500_init_devices().

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    6 +++---
 arch/arm/mach-ux500/cpu-db8500.c   |    4 +---
 arch/arm/mach-ux500/setup.h        |    2 +-
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 9bc762a..14a3598 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -623,7 +623,7 @@ static void __init mop500_init_machine(void)
 	sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
 
 	mop500_pinmaps_init();
-	parent = u8500_init_devices(&ab8500_platdata);
+	parent = u8500_init_devices();
 
 	for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
 		mop500_platform_devs[i]->dev.parent = parent;
@@ -660,7 +660,7 @@ static void __init snowball_init_machine(void)
 	sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
 
 	snowball_pinmaps_init();
-	parent = u8500_init_devices(&ab8500_platdata);
+	parent = u8500_init_devices();
 
 	for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
 		snowball_platform_devs[i]->dev.parent = parent;
@@ -698,7 +698,7 @@ static void __init hrefv60_init_machine(void)
 	sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
 
 	hrefv60_pinmaps_init();
-	parent = u8500_init_devices(&ab8500_platdata);
+	parent = u8500_init_devices();
 
 	for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
 		mop500_platform_devs[i]->dev.parent = parent;
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 995928b..8c2590c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -206,7 +206,7 @@ static struct device * __init db8500_soc_device_init(void)
 /*
  * This function is called from the board init
  */
-struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
+struct device * __init u8500_init_devices(void)
 {
 	struct device *parent;
 	int i;
@@ -220,8 +220,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 	for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
 		platform_devs[i]->dev.parent = parent;
 
-	db8500_prcmu_device.dev.platform_data = ab8500;
-
 	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
 	return parent;
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index bddce2b..cad3ca8 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -18,7 +18,7 @@
 void __init ux500_map_io(void);
 extern void __init u8500_map_io(void);
 
-extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500);
+extern struct device * __init u8500_init_devices(void);
 
 extern void __init ux500_init_irq(void);
 extern void __init ux500_init_late(void);
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:02 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:02 +0100
Subject: [PATCH 2/9] mfd: ab8500-core: Use the correct driver name when
 enabling gpio/pinctrl
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-3-git-send-email-lee.jones@linaro.org>

When we're using Device Tree to enable GPIO drivers we're forced to be
OS agnostic, thus we are forbidden use names like pinctrl as they are
specific only to Linux. However, when we are registering devices using
internal systems such as MFD or platform registration, we can use such
terminology. In this case we can and should use the platform device ID
mechanism to specify which device we wish to utilise by detailing
pinctrl-<device_name>.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/ab8500-core.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 42abd3a..2047485 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -1106,7 +1106,7 @@ static struct mfd_cell ab8500_devs[] = {
 		.of_compatible = "stericsson,ab8500-denc",
 	},
 	{
-		.name = "ab8500-gpio",
+		.name = "pinctrl-ab8500",
 		.of_compatible = "stericsson,ab8500-gpio",
 	},
 	{
@@ -1243,7 +1243,7 @@ static struct mfd_cell ab8505_devs[] = {
 		.name = "ab8500-leds",
 	},
 	{
-		.name = "ab8500-gpio",
+		.name = "pinctrl-ab8505",
 	},
 	{
 		.name = "ab8500-usb",
@@ -1311,7 +1311,7 @@ static struct mfd_cell ab8540_devs[] = {
 		.resources = ab8500_temp_resources,
 	},
 	{
-		.name = "ab8500-gpio",
+		.name = "pinctrl-ab8540",
 	},
 	{
 		.name = "ab8540-usb",
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:03 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:03 +0100
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix for
 SMSC911x
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-4-git-send-email-lee.jones@linaro.org>

First Ethernet device has a ".0" appended onto the device name. It
appears that we need this in order to obtain the correct clock.

Cc: Ulf Hansson <ulf.hansson at linaro.org>
Cc: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/clk/ux500/u8500_clk.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 0b4f35a..80069c3 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
 				BIT(0), 0);
 	clk_register_clkdev(clk, "fsmc", NULL);
-	clk_register_clkdev(clk, NULL, "smsc911x");
+	clk_register_clkdev(clk, NULL, "smsc911x.0");
 
 	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
 				BIT(1), 0);
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:05 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:05 +0100
Subject: [PATCH 5/9] ARM: ux500: Fix incorrect DEBUG UART virtual addresses
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-6-git-send-email-lee.jones@linaro.org>

A recent move to rid header files which were hindering multiplatform
support forced address allocations out of the headers and into the
files which were using them. We also lost some useful macros such as
IO_ADDRESS(), so physical -> virtual addressing has been carried out
manually in this case. Unfortunately the incorrect value was converted.
This patch rectifies the error and ensures earlyprintk works again.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/include/debug/ux500.S |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S
index 2848857..fbd24be 100644
--- a/arch/arm/include/debug/ux500.S
+++ b/arch/arm/include/debug/ux500.S
@@ -24,9 +24,9 @@
 #define U8500_UART0_PHYS_BASE	(0x80120000)
 #define U8500_UART1_PHYS_BASE	(0x80121000)
 #define U8500_UART2_PHYS_BASE	(0x80007000)
-#define U8500_UART0_VIRT_BASE	(0xa8120000)
-#define U8500_UART1_VIRT_BASE	(0xa8121000)
-#define U8500_UART2_VIRT_BASE	(0xa8007000)
+#define U8500_UART0_VIRT_BASE	(0xf8120000)
+#define U8500_UART1_VIRT_BASE	(0xf8121000)
+#define U8500_UART2_VIRT_BASE	(0xf8007000)
 #define __UX500_PHYS_UART(n)	U8500_UART##n##_PHYS_BASE
 #define __UX500_VIRT_UART(n)	U8500_UART##n##_VIRT_BASE
 #endif
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:06 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:06 +0100
Subject: [PATCH 6/9] ARM: ux500: Provide device enumeration number suffix for
 SMSC911x
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-7-git-send-email-lee.jones@linaro.org>

First Ethernet device has a ".0" appended onto the device name. It
appears that we need this in order to obtain the correct clock.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 8c2590c..718e707 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -276,7 +276,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
-	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
+	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:04 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:04 +0100
Subject: [PATCH 4/9] mfd: db8500-prcmu: Supply the pdata_size attribute for
 db8500-thermal
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-5-git-send-email-lee.jones@linaro.org>

The MFD subsystem requires drivers to state the size of any platform
data passed, or it will fail to assign it to the device. This will
culminate in a NULL platform_data attribute and normally a failure to
probe() or a kernel Oops.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/db8500-prcmu.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 319b8ab..5389368 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -3095,6 +3095,7 @@ static struct mfd_cell db8500_prcmu_devs[] = {
 		.num_resources = ARRAY_SIZE(db8500_thsens_resources),
 		.resources = db8500_thsens_resources,
 		.platform_data = &db8500_thsens_data,
+		.pdata_size = sizeof(db8500_thsens_data),
 	},
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:07 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:07 +0100
Subject: [PATCH 7/9] pinctrl: abx500: Specify failed sub-driver by ID instead
 of driver_data
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-8-git-send-email-lee.jones@linaro.org>

If a sub-driver has not been specified correctly, there is a good chance
that plat_id is NULL, hence using an attribute of plat_id in the error
message is likely to not only fail the driver but Oops the kernel. Use
the failed ID instead.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/pinctrl/pinctrl-abx500.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index aa17f75..2a2a9df 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -900,8 +900,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
 		abx500_pinctrl_ab8505_init(&pct->soc);
 		break;
 	default:
-		dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
-				(int) platid->driver_data);
+		dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
 		mutex_destroy(&pct->lock);
 		return -EINVAL;
 	}
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:08 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:08 +0100
Subject: [PATCH 8/9] pinctrl: abx500: Rejiggle platform data and DT
 initialisation
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-9-git-send-email-lee.jones@linaro.org>

A pointer to GPIO platform data is always passed to the driver now, so
there's little point in checking for 'pdata' and executing the DT case if
it's not there. The difference between booting with DT and !DT is when
booting with DT, plat_id is not populated. Thus, in the DT case we have
to use a DT match table in order to find out which platform we're
executing on. So, we're changing the semantics here to only use the
match table if no plat_id is supplied though platform data.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/pinctrl/pinctrl-abx500.c |   27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index 2a2a9df..6d45327 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -851,23 +851,12 @@ static int abx500_gpio_probe(struct platform_device *pdev)
 
 	if (abx500_pdata)
 		pdata = abx500_pdata->gpio;
-	if (!pdata) {
-		if (np) {
-			const struct of_device_id *match;
 
-			match = of_match_device(abx500_gpio_match, &pdev->dev);
-			if (!match)
-				return -ENODEV;
-			id = (unsigned long)match->data;
-		} else {
-			dev_err(&pdev->dev, "gpio dt and platform data missing\n");
-			return -ENODEV;
-		}
+	if (!(pdata || np)) {
+		dev_err(&pdev->dev, "gpio dt and platform data missing\n");
+		return -ENODEV;
 	}
 
-	if (platid)
-		id = platid->driver_data;
-
 	pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
 				   GFP_KERNEL);
 	if (pct == NULL) {
@@ -882,6 +871,16 @@ static int abx500_gpio_probe(struct platform_device *pdev)
 	pct->chip.dev = &pdev->dev;
 	pct->chip.base = (np) ? -1 : pdata->gpio_base;
 
+	if (platid)
+		id = platid->driver_data;
+	else if (np) {
+		const struct of_device_id *match;
+
+		match = of_match_device(abx500_gpio_match, &pdev->dev);
+		if (match)
+			id = (unsigned long)match->data;
+	}
+
 	/* initialize the lock */
 	mutex_init(&pct->lock);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May  8 09:29:09 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed,  8 May 2013 14:29:09 +0100
Subject: [PATCH 9/9] mfd: ab8500-core: Pass GPADC compatible string to MFD core
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368019749-19455-10-git-send-email-lee.jones@linaro.org>

When booting with Device Tree enabled the MFD core uses each device's
compatible string to find and allocate its associated of_node pointer,
which in turn is passed to the driver via the platform_device struct.
Without it, the driver won't be able to interrogate the Device Tree or
locate suitable regulators and will most likely fail to probe.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/ab8500-core.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 2047485..983eb1e 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -1060,6 +1060,7 @@ static struct mfd_cell ab8500_devs[] = {
 	},
 	{
 		.name = "ab8500-gpadc",
+		.of_compatible = "stericsson,ab8500-gpadc",
 		.num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
 		.resources = ab8500_gpadc_resources,
 	},
@@ -1217,6 +1218,7 @@ static struct mfd_cell ab8505_devs[] = {
 	},
 	{
 		.name = "ab8500-gpadc",
+		.of_compatible = "stericsson,ab8500-gpadc",
 		.num_resources = ARRAY_SIZE(ab8505_gpadc_resources),
 		.resources = ab8505_gpadc_resources,
 	},
@@ -1280,6 +1282,7 @@ static struct mfd_cell ab8540_devs[] = {
 	},
 	{
 		.name = "ab8500-gpadc",
+		.of_compatible = "stericsson,ab8500-gpadc",
 		.num_resources = ARRAY_SIZE(ab8505_gpadc_resources),
 		.resources = ab8505_gpadc_resources,
 	},
-- 
1.7.10.4



From arnd at arndb.de  Wed May  8 09:34:08 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 15:34:08 +0200
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <CABYn4sxrcGmnTAJcQR23nMGy8JvqyDrgPOXF4yBFFU_4C8Pc_g@mail.gmail.com>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <201305081416.06611.arnd@arndb.de>
 <CABYn4sxrcGmnTAJcQR23nMGy8JvqyDrgPOXF4yBFFU_4C8Pc_g@mail.gmail.com>
Message-ID: <201305081534.08336.arnd@arndb.de>

On Wednesday 08 May 2013, Bastian Hecht wrote:
> 
> 2013/5/8 Arnd Bergmann <arnd at arndb.de>:
> 
> I have sent out a patch adding an empty irqchip_init() when
> CONFIG_IRQCHIP is not set with the subject
> [PATCH] irqchip: Add irqchip_init dummy function

Ah, I missed that one. Is it already in linux-next?

	Arnd


From lee.jones at linaro.org  Wed May  8 09:37:07 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 May 2013 14:37:07 +0100
Subject: [PATCH 0/9] Important ux500 fixups due for the v3.10 -rc:s
In-Reply-To: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20130508133707.GH3459@gmail.com>

Hi, Sam, Mike & Ulf

I see that you weren't on the list for the 0/9 patch, so here FYI:

> This patch-set straightens out some serious errors incurred during
> the v3.10 merge window, including:
> 
> Patch 1: Possible over-write of DB8500-PRCMU platform data
> Patch 2: Fail to register AB8500 GPIO driver
> Patch 3: Fail to start Ethernet when using ATAGS - Clocks
> Patch 4: Fail to probe DB8500 Thermal driver - No pdata
> Patch 5: Fail to use Early Printk - Incorrect virtual addresses
> Patch 6: Fail to start Ethernet with using Device Tree - Clocks
> Patch 7: Oops kernel during driver fail - Null pointer
> Patch 8: Fail to probe AB8500 GPIO driver - Incorrect platform ID
> Patch 9: Fail to probe AB8500 GPADC driver - Regulators
> 
>  arch/arm/include/debug/ux500.S     |    6 +++---
>  arch/arm/mach-ux500/board-mop500.c |    6 +++---
>  arch/arm/mach-ux500/cpu-db8500.c   |    6 ++----
>  arch/arm/mach-ux500/setup.h        |    2 +-
>  drivers/clk/ux500/u8500_clk.c      |    2 +-
>  drivers/mfd/ab8500-core.c          |    9 ++++++---
>  drivers/mfd/db8500-prcmu.c         |    1 +
>  drivers/pinctrl/pinctrl-abx500.c   |   30 ++++++++++++++----------------
>  8 files changed, 31 insertions(+), 31 deletions(-)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From robherring2 at gmail.com  Wed May  8 09:50:36 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 08 May 2013 08:50:36 -0500
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <20130508071137.GM25742@login.drsnuggles.stderr.nl>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
 <20130508071137.GM25742@login.drsnuggles.stderr.nl>
Message-ID: <518A582C.8070600@gmail.com>

On 05/08/2013 02:11 AM, Matthijs Kooijman wrote:
> Hi folks,
> 
> I also bumped into the question of how to set the dma_mask when enabling
> the dwc2 driver on the ramips target and found there didn't seem to be
> any clear way to get a dma_mask.
> 
> It seems to me that in the pre-DT era, a platform_device would get a
> dma_mask when it was defined in the board / soc code, which makes sense
> since that code knows if a dma_mask is required and what its value
> should be (it seems to me that a driver can only know it needs a
> dma_mask, but not what value it should have?).
> 
>>> This probably could be initialized from some DT property. However,
>>> there's no such property defined right now, and considering that DT is
>>> supposed to be an ABI, we'd always need the code in this patch as a
>>> fallback for DTs that were created before any such property was defined.
> It seems there has already been a patch to implement this. For
> reference, this seems to be the most recent version:
> 
> https://lkml.org/lkml/2012/12/4/54
> 
> And here's the previous attempt, to which Rob Herring refers in a reply.
> 
> https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-March/013180.html

I believe most of the issues have been around supporting ARM LPAE
systems. There is a much more simple approach to address this by using
the dma_addr_t size to set the coherent_dma_mask which I have queued for
3.11:

https://patchwork-mail1.kernel.org/patch/2495861/

This does not set dma_mask though. There's always been some mystery
around why there are separate masks. I think for most systems dma_mask
can be set to coherent_dma_mask based on what Arnd found:

http://pastebin.com/E7fFVJyq

This can always be overridden by a platform with a bus notifier or by a
driver if needed.

Rob

> 
>>> Equally, since the data is SoC-specific rather than board-specific, and
>>> is even fairly unlikely to vary between SoC versions since these values
>>> are all 0xffffffff anyway, I don't really see much point in putting it
>>> into DT, rather than just putting the static data into the driver.
>>
>> I mean there is already dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
>> at function of_platform_device_create, why can't add
>> dev->dev.dma_mask = &dev->dev.coherent_dma_mask after that?
> Perhaps it would sense to set the 32-bit mask as a default, but allow to
> override this mask from the devicetree for boards that need another
> value? Or perhaps override it from the soc code instead?
> 
> For the ramips target, the MIPS folks suggested another approach: The
> soc code finds the platform_device generated by DT and adds the
> dma_mask:
> 
> http://www.linux-mips.org/archives/linux-mips/2013-04/msg00162.html
> 
>> If DT core can do above things, can we delete dma_mask assignment
>> at every driver?
> That would seem like a likeably goal to me :-)
> 
> 
> Gr.
> 
> Matthijs
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From ulf.hansson at linaro.org  Wed May  8 09:57:26 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 8 May 2013 15:57:26 +0200
Subject: [PATCH 1/8] crypto: ux500/hash - Prepare clock before enabling it
In-Reply-To: <1367491790-9727-2-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
 <1367491790-9727-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CAPDyKFrJsGhB9yRtF2a09Ob5_4Jz-gaBQxeuriCGaXqYwkSyeg@mail.gmail.com>

On 2 May 2013 12:49, Lee Jones <lee.jones at linaro.org> wrote:
> If we fail to prepare the ux500-hash clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/crypto/ux500/hash/hash_core.c |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
> index 632c333..1e8b2f3 100644
> --- a/drivers/crypto/ux500/hash/hash_core.c
> +++ b/drivers/crypto/ux500/hash/hash_core.c
> @@ -1727,11 +1727,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
>                 goto out_regulator;
>         }
>
> +       ret = clk_prepare(device_data->clk);
> +       if (ret) {
> +               dev_err(dev, "[%s] clk_prepare() failed!", __func__);
> +               goto out_clk;
> +       }
> +
>         /* Enable device power (and clock) */
>         ret = hash_enable_power(device_data, false);
>         if (ret) {
>                 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
> -               goto out_clk;
> +               goto out_clk_unprepare;
>         }
>
>         ret = hash_check_hw(device_data);
> @@ -1763,6 +1769,9 @@ static int ux500_hash_probe(struct platform_device *pdev)
>  out_power:
>         hash_disable_power(device_data, false);
>
> +out_clk_unprepare:
> +       clk_unprepare(device_data->clk);
> +
>  out_clk:
>         clk_put(device_data->clk);
>
> @@ -1827,6 +1836,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
>                 dev_err(dev, "[%s]: hash_disable_power() failed",
>                         __func__);
>
> +       clk_unprepare(device_data->clk);
>         clk_put(device_data->clk);
>         regulator_put(device_data->regulator);
>
> --
> 1.7.10.4
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From ulf.hansson at linaro.org  Wed May  8 09:57:51 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 8 May 2013 15:57:51 +0200
Subject: [PATCH 4/8] crypto: ux500/cryp - Prepare clock before enabling it
In-Reply-To: <1367491790-9727-5-git-send-email-lee.jones@linaro.org>
References: <1367491790-9727-1-git-send-email-lee.jones@linaro.org>
 <1367491790-9727-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CAPDyKFrZo7Eg4wmYVfD4MYr=Ae1Z1u6pJQOjv4X1QK+FKPH7FA@mail.gmail.com>

On 2 May 2013 12:49, Lee Jones <lee.jones at linaro.org> wrote:
> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/crypto/ux500/cryp/cryp_core.c |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
> index 22c9063..bf78d60 100644
> --- a/drivers/crypto/ux500/cryp/cryp_core.c
> +++ b/drivers/crypto/ux500/cryp/cryp_core.c
> @@ -1459,11 +1459,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
>                 goto out_regulator;
>         }
>
> +       ret = clk_prepare(device_data->clk);
> +       if (ret) {
> +               dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
> +               goto out_clk;
> +       }
> +
>         /* Enable device power (and clock) */
>         ret = cryp_enable_power(device_data->dev, device_data, false);
>         if (ret) {
>                 dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
> -               goto out_clk;
> +               goto out_clk_unprepare;
>         }
>
>         cryp_error = cryp_check(device_data);
> @@ -1524,6 +1530,9 @@ static int ux500_cryp_probe(struct platform_device *pdev)
>  out_power:
>         cryp_disable_power(device_data->dev, device_data, false);
>
> +out_clk_unprepare:
> +       clk_unprepare(device_data->clk);
> +
>  out_clk:
>         clk_put(device_data->clk);
>
> @@ -1594,6 +1603,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
>                 dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
>                         __func__);
>
> +       clk_unprepare(device_data->clk);
>         clk_put(device_data->clk);
>         regulator_put(device_data->pwr_regulator);
>
> --
> 1.7.10.4
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From ulf.hansson at linaro.org  Wed May  8 09:59:08 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 8 May 2013 15:59:08 +0200
Subject: [PATCH 36/63] crypto: ux500/hash - Prepare clock before enabling
 it
In-Reply-To: <1367591569-32197-37-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-37-git-send-email-lee.jones@linaro.org>
Message-ID: <CAPDyKFqD93K_vBKpoWmLjFHaY06seARDpxb-KJJFv4LAzXa1Vw@mail.gmail.com>

On 3 May 2013 16:32, Lee Jones <lee.jones at linaro.org> wrote:
> If we fail to prepare the ux500-hash clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/crypto/ux500/hash/hash_core.c |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
> index 632c333..1e8b2f3 100644
> --- a/drivers/crypto/ux500/hash/hash_core.c
> +++ b/drivers/crypto/ux500/hash/hash_core.c
> @@ -1727,11 +1727,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
>                 goto out_regulator;
>         }
>
> +       ret = clk_prepare(device_data->clk);
> +       if (ret) {
> +               dev_err(dev, "[%s] clk_prepare() failed!", __func__);
> +               goto out_clk;
> +       }
> +
>         /* Enable device power (and clock) */
>         ret = hash_enable_power(device_data, false);
>         if (ret) {
>                 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
> -               goto out_clk;
> +               goto out_clk_unprepare;
>         }
>
>         ret = hash_check_hw(device_data);
> @@ -1763,6 +1769,9 @@ static int ux500_hash_probe(struct platform_device *pdev)
>  out_power:
>         hash_disable_power(device_data, false);
>
> +out_clk_unprepare:
> +       clk_unprepare(device_data->clk);
> +
>  out_clk:
>         clk_put(device_data->clk);
>
> @@ -1827,6 +1836,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
>                 dev_err(dev, "[%s]: hash_disable_power() failed",
>                         __func__);
>
> +       clk_unprepare(device_data->clk);
>         clk_put(device_data->clk);
>         regulator_put(device_data->regulator);
>
> --
> 1.7.10.4
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From ulf.hansson at linaro.org  Wed May  8 09:59:35 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 8 May 2013 15:59:35 +0200
Subject: [PATCH 39/63] crypto: ux500/cryp - Prepare clock before enabling
 it
In-Reply-To: <1367591569-32197-40-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-40-git-send-email-lee.jones@linaro.org>
Message-ID: <CAPDyKFqiLt=xC8NNXxKZpKh49+ewHuLt=0r+HogZ-aFrKh99NQ@mail.gmail.com>

On 3 May 2013 16:32, Lee Jones <lee.jones at linaro.org> wrote:
> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/crypto/ux500/cryp/cryp_core.c |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
> index 22c9063..bf78d60 100644
> --- a/drivers/crypto/ux500/cryp/cryp_core.c
> +++ b/drivers/crypto/ux500/cryp/cryp_core.c
> @@ -1459,11 +1459,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
>                 goto out_regulator;
>         }
>
> +       ret = clk_prepare(device_data->clk);
> +       if (ret) {
> +               dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
> +               goto out_clk;
> +       }
> +
>         /* Enable device power (and clock) */
>         ret = cryp_enable_power(device_data->dev, device_data, false);
>         if (ret) {
>                 dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
> -               goto out_clk;
> +               goto out_clk_unprepare;
>         }
>
>         cryp_error = cryp_check(device_data);
> @@ -1524,6 +1530,9 @@ static int ux500_cryp_probe(struct platform_device *pdev)
>  out_power:
>         cryp_disable_power(device_data->dev, device_data, false);
>
> +out_clk_unprepare:
> +       clk_unprepare(device_data->clk);
> +
>  out_clk:
>         clk_put(device_data->clk);
>
> @@ -1594,6 +1603,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
>                 dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
>                         __func__);
>
> +       clk_unprepare(device_data->clk);
>         clk_put(device_data->clk);
>         regulator_put(device_data->pwr_regulator);
>
> --
> 1.7.10.4
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From ulf.hansson at linaro.org  Wed May  8 10:00:03 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 8 May 2013 16:00:03 +0200
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CAPDyKFqsZ=z6OcRs45_DUO1Zpp_C1qUeZ2tsGCjD08H_b4L-jg@mail.gmail.com>

On 8 May 2013 15:29, Lee Jones <lee.jones at linaro.org> wrote:
> First Ethernet device has a ".0" appended onto the device name. It
> appears that we need this in order to obtain the correct clock.
>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/clk/ux500/u8500_clk.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
> index 0b4f35a..80069c3 100644
> --- a/drivers/clk/ux500/u8500_clk.c
> +++ b/drivers/clk/ux500/u8500_clk.c
> @@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
>         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
>                                 BIT(0), 0);
>         clk_register_clkdev(clk, "fsmc", NULL);
> -       clk_register_clkdev(clk, NULL, "smsc911x");
> +       clk_register_clkdev(clk, NULL, "smsc911x.0");
>
>         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
>                                 BIT(1), 0);
> --
> 1.7.10.4
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From shawn.guo at linaro.org  Wed May  8 10:00:06 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 22:00:06 +0800
Subject: [PATCH 2/2] ARM: dts: cfa10036: Change the OLED display to SSD1306
In-Reply-To: <1366624555-5616-3-git-send-email-maxime.ripard@free-electrons.com>
References: <1366624555-5616-1-git-send-email-maxime.ripard@free-electrons.com>
 <1366624555-5616-3-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130508140004.GC26072@S2101-09.ap.freescale.net>

On Mon, Apr 22, 2013 at 11:55:55AM +0200, Maxime Ripard wrote:
> The SSD1307 was used in an early prototype that will never get
> distributed. The final board now has a SSD1306 instead, that has its own
> power generation unit and thus doesn't need any PWM. The panel attached
> to it also changed.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Applied, thanks.



From shawn.guo at linaro.org  Wed May  8 10:01:02 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 22:01:02 +0800
Subject: [PATCH 1/4] ARM: cfa10036: dt: Change i2c0 clock frequency
In-Reply-To: <1366624945-5708-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1366624945-5708-1-git-send-email-maxime.ripard@free-electrons.com>
 <1366624945-5708-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130508140101.GD26072@S2101-09.ap.freescale.net>

On Mon, Apr 22, 2013 at 12:02:22PM +0200, Maxime Ripard wrote:
> The OLED display can work faster. Change the i2c controller clock
> frequency to remove the tearing effect that can be seen on the display.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Applied, thanks.



From stefano.stabellini at eu.citrix.com  Wed May  8 09:50:44 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 14:50:44 +0100
Subject: [PATCH v3 0/4] xen/arm: CONFIG_PARAVIRT and stolen ticks
 accounting
Message-ID: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>

Hi all,
this patch series introduces stolen ticks accounting for Xen on ARM.
Stolen ticks are clocksource ticks that have been "stolen" from the cpu,
typically because Linux is running in a virtual machine and the vcpu has
been descheduled.
To account for these ticks we introduce CONFIG_PARAVIRT and pv_time_ops
so that we can make use of:

kernel/sched/cputime.c:steal_account_process_tick



Stefano Stabellini (4):
      xen: move xen_setup_runstate_info and get_runstate_snapshot to drivers/xen/time.c
      kernel: missing include in cputime.c
      arm: introduce CONFIG_PARAVIRT, PARAVIRT_TIME_ACCOUNTING and pv_time_ops
      xen/arm: account for stolen ticks

 arch/arm/Kconfig                |   20 +++++++++
 arch/arm/include/asm/paravirt.h |   19 ++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   25 +++++++++++
 arch/arm/xen/enlighten.c        |   22 +++++++++
 arch/ia64/xen/time.c            |   48 +++------------------
 arch/x86/xen/time.c             |   76 +--------------------------------
 drivers/xen/Makefile            |    2 +-
 drivers/xen/time.c              |   91 +++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h           |    5 ++
 kernel/sched/cputime.c          |    1 +
 11 files changed, 192 insertions(+), 118 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c
 create mode 100644 drivers/xen/time.c


git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_3

Cheers,

Stefano


From arnd at arndb.de  Wed May  8 10:07:54 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 16:07:54 +0200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <518A582C.8070600@gmail.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <20130508071137.GM25742@login.drsnuggles.stderr.nl>
 <518A582C.8070600@gmail.com>
Message-ID: <201305081607.54839.arnd@arndb.de>

On Wednesday 08 May 2013, Rob Herring wrote:
> On 05/08/2013 02:11 AM, Matthijs Kooijman wrote:

> > https://lkml.org/lkml/2012/12/4/54
> > 
> > And here's the previous attempt, to which Rob Herring refers in a reply.
> > 
> > https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-March/013180.html
> 
> I believe most of the issues have been around supporting ARM LPAE
> systems. There is a much more simple approach to address this by using
> the dma_addr_t size to set the coherent_dma_mask which I have queued for
> 3.11:
> 
> https://patchwork-mail1.kernel.org/patch/2495861/

Hmm, this approach seems wrong -- a lot of devices I expect cannot
actually do DMA to addresses beyond 4GB. A better default would
be to use a 32 bit mask for all devices and override the ones that
actually matter for performance and are known to be 64-bit DMA
capable.

Laura, you obviously tried this code on an LPAE-enabled system. Have
you had a look in the hardware manual which DMA masters in the
system are actually 64-bit capable?

	Arnd


From stern at rowland.harvard.edu  Wed May  8 10:14:13 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Wed, 8 May 2013 10:14:13 -0400 (EDT)
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <201305080142.12025.arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305081011480.1450-100000@iolanthe.rowland.org>

On Wed, 8 May 2013, Arnd Bergmann wrote:

> On Wednesday 08 May 2013, Greg Kroah-Hartman wrote:
> > On Tue, May 07, 2013 at 04:53:52PM -0600, Stephen Warren wrote:
> > > From: Stephen Warren <swarren at nvidia.com>
> 
> > > Suggested-by: Arnd Bergmann <arnd at arndb.de>
> > > Signed-off-by: Stephen Warren <swarren at nvidia.com>
> > 
> > So this needs to go in for 3.10, right?  Any older kernels as well?  If
> > so, which ones?
> 
> The fix should definitely go into 3.10, but I'd suggest waiting with
> the backport for a couple of -rc releases to avoid possible regressions.
> We know that the current code is broken, but few people fully understand
> what is going on with coherent_dma_mask, so it might cause new problems
> in combination with some other unknown bug, and I don't see this as
> urgent: none of the ARM defconfigs build this driver as a loadable
> module and there is no bug in the built-in case. For some reason, only
> the ARM back-end drivers are broken.
> 
> The first occurence was apparently in 3.3, but only in ehci-tegra.c,
> while the other drivers subsequently copied the bug.

An alternative solution -- perhaps not better but also not relying on
coherent_dma_mask -- is to clear pdev->dev.dma_mask in the remove
routine if it points to the static mask value.

Alan Stern



From srinivas.kandagatla at st.com  Wed May  8 10:09:47 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed,  8 May 2013 15:09:47 +0100
Subject: [RFC 0/8] ARM:STiH41x: Add STiH41x platform and board support
Message-ID: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>

From: Srinivas Kandagatla <srinivas.kandagatla at st.com>

This patch-set adds basic support for STMicroelectronics STiH41x SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.

STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU, designed for use in
Set-top-boxes.

The SOC support is divided into two parts which is plat-stixxxx and
mach-stih41x. plat-stixxxx contains code which is common across all
STMicroelectronics CE chips, and mach-stih41x contains support code for STiH415
and STiH416 SOCs.

Only device drivers included in this patch set are UART and pinctrl, other
drivers will be added in future.

The reason for adding two SOCs at this patch set is to show that no new C code
is required for second SOC(STiH416) support.

In the process of adding support to these SOCs we have added new code into sycon
and also added support for a9 global-timer.

I would appreciate any feedback on these patches.

Thanks,
srini

Srinivas Kandagatla (8):
  serial:st-asc: Add ST ASC driver.
  mfd:syscon: Introduce claim/read/write/release APIs
  pinctrl:stixxxx: Add pinctrl and pinconf support.
  ARM:stih41x: Add STiH415 SOC support
  ARM:stih41x: Add STiH416 SOC support
  ARM:stih41x: Add B2000 board support
  ARM:stih41x: Add B2020 board support

Stuart Menefy (1):
  ARM:global_timer: Add ARM global timer support.

 Documentation/arm/STiH41x/overview.txt             |   39 +
 Documentation/arm/STiH41x/stih415-overview.txt     |   12 +
 Documentation/arm/STiH41x/stih416-overview.txt     |   12 +
 Documentation/devicetree/bindings/arm/gt.txt       |   21 +
 .../bindings/pinctrl/pinctrl-stixxxx.txt           |  160 +++
 .../devicetree/bindings/tty/serial/st-asc.txt      |   18 +
 arch/arm/Kconfig                                   |    9 +
 arch/arm/Kconfig.debug                             |   38 +
 arch/arm/Makefile                                  |    2 +
 arch/arm/boot/dts/Makefile                         |    4 +
 arch/arm/boot/dts/stih415-b2000.dtsp               |   15 +
 arch/arm/boot/dts/stih415-b2020.dtsp               |   15 +
 arch/arm/boot/dts/stih415-clock.dtsi               |   38 +
 arch/arm/boot/dts/stih415-pinctrl.dtsi             |  480 ++++++++
 arch/arm/boot/dts/stih415.dtsi                     |   94 ++
 arch/arm/boot/dts/stih415.h                        |   20 +
 arch/arm/boot/dts/stih416-b2000.dtsp               |   16 +
 arch/arm/boot/dts/stih416-b2020.dtsp               |   16 +
 arch/arm/boot/dts/stih416-clock.dtsi               |   41 +
 arch/arm/boot/dts/stih416-pinctrl.dtsi             |  718 ++++++++++++
 arch/arm/boot/dts/stih416.dtsi                     |  103 ++
 arch/arm/boot/dts/stih416.h                        |   24 +
 arch/arm/boot/dts/stih41x-b2000.dtsi               |   41 +
 arch/arm/boot/dts/stih41x-b2020.dtsi               |   42 +
 arch/arm/boot/dts/stih41x.dtsi                     |   30 +
 arch/arm/boot/dts/stixxxx-pincfg.h                 |   95 ++
 arch/arm/configs/stih41x_defconfig                 |   95 ++
 arch/arm/include/asm/global_timer.h                |   12 +
 arch/arm/include/debug/stixxxx.S                   |   61 +
 arch/arm/kernel/Makefile                           |    1 +
 arch/arm/kernel/global_timer.c                     |  325 ++++++
 arch/arm/mach-stih41x/Kconfig                      |   44 +
 arch/arm/mach-stih41x/Makefile                     |    4 +
 arch/arm/mach-stih41x/board-dt.c                   |   80 ++
 arch/arm/mach-stih41x/stih41x.c                    |   82 ++
 arch/arm/mach-stih41x/stih41x.h                    |    7 +
 arch/arm/plat-stixxxx/Kconfig                      |    2 +
 arch/arm/plat-stixxxx/Makefile                     |    2 +
 arch/arm/plat-stixxxx/headsmp.S                    |   44 +
 arch/arm/plat-stixxxx/include/plat/hardware.h      |   20 +
 arch/arm/plat-stixxxx/include/plat/smp.h           |   19 +
 arch/arm/plat-stixxxx/platsmp.c                    |  144 +++
 drivers/mfd/syscon.c                               |  199 ++++
 drivers/pinctrl/Kconfig                            |   13 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-stixxxx.c                  | 1151 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-stixxxx.h                  |  197 ++++
 drivers/tty/serial/Kconfig                         |   19 +
 drivers/tty/serial/Makefile                        |    1 +
 drivers/tty/serial/st-asc.c                        |  821 ++++++++++++++
 drivers/tty/serial/st-asc.h                        |  146 +++
 include/linux/mfd/syscon.h                         |   43 +
 include/uapi/linux/serial_core.h                   |    3 +
 53 files changed, 5639 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/arm/STiH41x/overview.txt
 create mode 100644 Documentation/arm/STiH41x/stih415-overview.txt
 create mode 100644 Documentation/arm/STiH41x/stih416-overview.txt
 create mode 100644 Documentation/devicetree/bindings/arm/gt.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/st-asc.txt
 create mode 100644 arch/arm/boot/dts/stih415-b2000.dtsp
 create mode 100644 arch/arm/boot/dts/stih415-b2020.dtsp
 create mode 100644 arch/arm/boot/dts/stih415-clock.dtsi
 create mode 100644 arch/arm/boot/dts/stih415-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/stih415.dtsi
 create mode 100644 arch/arm/boot/dts/stih415.h
 create mode 100644 arch/arm/boot/dts/stih416-b2000.dtsp
 create mode 100644 arch/arm/boot/dts/stih416-b2020.dtsp
 create mode 100644 arch/arm/boot/dts/stih416-clock.dtsi
 create mode 100644 arch/arm/boot/dts/stih416-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/stih416.dtsi
 create mode 100644 arch/arm/boot/dts/stih416.h
 create mode 100644 arch/arm/boot/dts/stih41x-b2000.dtsi
 create mode 100644 arch/arm/boot/dts/stih41x-b2020.dtsi
 create mode 100644 arch/arm/boot/dts/stih41x.dtsi
 create mode 100644 arch/arm/boot/dts/stixxxx-pincfg.h
 create mode 100644 arch/arm/configs/stih41x_defconfig
 create mode 100644 arch/arm/include/asm/global_timer.h
 create mode 100644 arch/arm/include/debug/stixxxx.S
 create mode 100644 arch/arm/kernel/global_timer.c
 create mode 100644 arch/arm/mach-stih41x/Kconfig
 create mode 100644 arch/arm/mach-stih41x/Makefile
 create mode 100644 arch/arm/mach-stih41x/board-dt.c
 create mode 100644 arch/arm/mach-stih41x/stih41x.c
 create mode 100644 arch/arm/mach-stih41x/stih41x.h
 create mode 100644 arch/arm/plat-stixxxx/Kconfig
 create mode 100644 arch/arm/plat-stixxxx/Makefile
 create mode 100644 arch/arm/plat-stixxxx/headsmp.S
 create mode 100644 arch/arm/plat-stixxxx/include/plat/hardware.h
 create mode 100644 arch/arm/plat-stixxxx/include/plat/smp.h
 create mode 100644 arch/arm/plat-stixxxx/platsmp.c
 create mode 100644 drivers/pinctrl/pinctrl-stixxxx.c
 create mode 100644 drivers/pinctrl/pinctrl-stixxxx.h
 create mode 100644 drivers/tty/serial/st-asc.c
 create mode 100644 drivers/tty/serial/st-asc.h

-- 
1.7.6.5



From catalin.marinas at arm.com  Wed May  8 10:17:06 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 8 May 2013 15:17:06 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <CAFEAcA-eSB=_UT0-L7o=2o6JGv0WkXZv5UPxPVqLRxjUZQegFA@mail.gmail.com>
References: <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
 <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
 <87txmfo0rl.fsf@rustcorp.com.au>
 <CAFEAcA9jBSpN2p9ZaU+_gX41Ke3nvpSKVrWV8Rioy_ioadKCgg@mail.gmail.com>
 <5189234D.3040208@codeaurora.org>
 <CAFEAcA-eSB=_UT0-L7o=2o6JGv0WkXZv5UPxPVqLRxjUZQegFA@mail.gmail.com>
Message-ID: <20130508141706.GF2703@arm.com>

On Tue, May 07, 2013 at 04:58:23PM +0100, Peter Maydell wrote:
> On 7 May 2013 16:52, Christopher Covington <cov at codeaurora.org> wrote:
> > On 05/07/2013 08:19 AM, Peter Maydell wrote:
> >> Well, at the moment EARLY_PRINTK is hardcoded to
> >> "use some specific UART or equivalent selected at
> >> compile time". So the equivalent presumably would
> >> be to hard-compile "use virtio-console", but then
> >> how does that code know where the virtio-console
> >> is in the address space?
> >
> > arm64 uses a kernel argument.
> 
> This mixes up "information that the user provides to the
> kernel" (ie configuration) with "information that QEMU or
> kvmtool should provide to the kernel" (ie hardware
> description), and would require QEMU/kvmtool to parse
> the user's commandline tool to figure out if they
> needed to override it or edit it (or alternatively,
> would require the user to know internal details of
> QEMU/kvmtool's address map for the guest). I think it
> would be nicer to keep them separate.

I'm not sure it's worth it, the earlyprintk is meant for debugging the
early kernel booting code, not for general use (you have the normal
console for this). Someone doing platform port should know the address
of the uart and pass the right information on the kernel command line to
help debug early booting issues.

But if someone comes up with some bindings, I won't reject the patch.

-- 
Catalin


From robherring2 at gmail.com  Wed May  8 10:26:33 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 08 May 2013 09:26:33 -0500
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <518A6099.8070505@gmail.com>

On 05/08/2013 09:11 AM, Srinivas KANDAGATLA wrote:
> From: Stuart Menefy <stuart.menefy at st.com>
> 
> This is a simple driver for the global timer module found in the Cortex
> A9-MP cores from revision r1p0 onwards. This should be able to perform
> the functions of the system timer and the local timer in an SMP system.
> 
> The global timer has the following features:
>     The global timer is a 64-bit incrementing counter with an
> auto-incrementing feature. It continues incrementing after sending
> interrupts. The global timer is memory mapped in the private memory
> region.
>     The global timer is accessible to all Cortex-A9 processors in the
> cluster. Each Cortex-A9 processor has a private 64-bit comparator that
> is used to assert a private interrupt when the global timer has reached
> the comparator value. All the Cortex-A9 processors in a design use the
> banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
> Controller as a Private Peripheral Interrupt. The global timer is
> clocked by PERIPHCLK.

PERIPHCLK scales with cpu clock typically so the global timer is not a
suitable clocksource if you use cpufreq. You can deal with the scaling
on clockevents, but not a clocksource. I imagine the global timers is
also typically power-gated in some low power modes. This is why no one
has added support already. Are neither of those an issue or going to be
an issue for you?

Rob

> 
> Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> ---
>  Documentation/devicetree/bindings/arm/gt.txt |   21 ++
>  arch/arm/Kconfig                             |    6 +
>  arch/arm/include/asm/global_timer.h          |   12 +
>  arch/arm/kernel/Makefile                     |    1 +
>  arch/arm/kernel/global_timer.c               |  325 ++++++++++++++++++++++++++
>  5 files changed, 365 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/gt.txt
>  create mode 100644 arch/arm/include/asm/global_timer.h
>  create mode 100644 arch/arm/kernel/global_timer.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/gt.txt b/Documentation/devicetree/bindings/arm/gt.txt
> new file mode 100644
> index 0000000..4ec5fb0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/gt.txt
> @@ -0,0 +1,21 @@
> +
> +* ARM Global Timer
> +	Cortex-A9 are often associated with a per-core Global timer.
> +
> +** Timer node required properties:
> +
> +- compatible : Should be one of:
> +	"arm,cortex-a9-global-timer"
> +
> +- interrupts : One interrupt to each core
> +
> +- reg : Specify the base address and the size of the GT timer
> +	register window.
> +
> +Example:
> +
> +	gt-timer at 2c000600 {
> +		compatible = "arm,cortex-a9-global-timer";
> +		reg = <0x2c000600 0x20>;
> +		interrupts = <1 13 0xf01>;
> +	};
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1cacda4..c8c524e 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1606,6 +1606,12 @@ config HAVE_ARM_TWD
>  	help
>  	  This options enables support for the ARM timer and watchdog unit
>  
> +config HAVE_ARM_GT
> +	bool
> +	select CLKSRC_OF if OF
> +	help
> +	  This options enables support for the ARM global timer unit
> +
>  choice
>  	prompt "Memory split"
>  	default VMSPLIT_3G
> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
> new file mode 100644
> index 0000000..46f9188
> --- /dev/null
> +++ b/arch/arm/include/asm/global_timer.h
> @@ -0,0 +1,12 @@
> +/*
> + * arch/arm/include/asm/global_timer.h
> + *
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
> + * Author: Stuart Menefy <stuart.menefy at st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq);
> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> index 5f3338e..af51808 100644
> --- a/arch/arm/kernel/Makefile
> +++ b/arch/arm/kernel/Makefile
> @@ -35,6 +35,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
>  obj-$(CONFIG_SMP)		+= smp.o smp_tlb.o
>  obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
>  obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
> +obj-$(CONFIG_HAVE_ARM_GT)	+= global_timer.o
>  obj-$(CONFIG_ARM_ARCH_TIMER)	+= arch_timer.o
>  obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o insn.o
>  obj-$(CONFIG_FUNCTION_GRAPH_TRACER)	+= ftrace.o insn.o
> diff --git a/arch/arm/kernel/global_timer.c b/arch/arm/kernel/global_timer.c
> new file mode 100644
> index 0000000..0ab1af3
> --- /dev/null
> +++ b/arch/arm/kernel/global_timer.c
> @@ -0,0 +1,325 @@
> +/*
> + * linux/arch/arm/kernel/global_timer.c
> + *
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
> + * Author: Stuart Menefy <stuart.menefy at st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +
> +#include <asm/mach/irq.h>
> +#include <asm/global_timer.h>
> +#include <asm/localtimer.h>
> +
> +#define GT_COUNTER0	0x00
> +#define GT_COUNTER1	0x04
> +
> +#define GT_CONTROL	0x08
> +#define GT_CONTROL_TIMER_ENABLE		BIT(0)
> +#define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
> +#define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
> +#define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
> +
> +#define GT_INT_STATUS	0x0c
> +#define GT_INT_STATUS_EVENT_FLAG	BIT(0)
> +
> +#define GT_COMP0	0x10
> +#define GT_COMP1	0x14
> +#define GT_AUTO_INC	0x18
> +
> +/*
> + * We are expecting to be clocked by the ARM peripheral clock.
> + *
> + * Note: it is assumed we are using a prescaler value of zero, so this is
> + * the units for all operations.
> + */
> +static void __iomem *gt_base;
> +static struct clk *gt_clk;
> +static unsigned long gt_clk_rate;
> +static int gt_ppi;
> +static struct clock_event_device __percpu **gt_evt;
> +static DEFINE_PER_CPU(bool, percpu_init_called);
> +static DEFINE_PER_CPU(struct clock_event_device, gt_clockevent);
> +
> +union gt_counter {
> +	cycle_t cycles;
> +	struct {
> +		uint32_t lower;
> +		uint32_t upper;
> +	};
> +};
> +
> +static union gt_counter gt_counter_read(void)
> +{
> +	union gt_counter res;
> +	uint32_t upper;
> +
> +	upper = readl(gt_base + GT_COUNTER1);
> +	do {
> +		res.upper = upper;
> +		res.lower = readl(gt_base + GT_COUNTER0);
> +		upper = readl(gt_base + GT_COUNTER1);
> +	} while (upper != res.upper);
> +
> +	return res;
> +}
> +
> +static void gt_compare_set(unsigned long delta, int periodic)
> +{
> +	union gt_counter counter = gt_counter_read();
> +	unsigned long ctrl = readl(gt_base + GT_CONTROL);
> +
> +	BUG_ON(!(ctrl & GT_CONTROL_TIMER_ENABLE));
> +	BUG_ON(ctrl & (GT_CONTROL_COMP_ENABLE |
> +		       GT_CONTROL_IRQ_ENABLE |
> +		       GT_CONTROL_AUTO_INC));
> +
> +	counter.cycles += delta;
> +	writel(counter.lower, gt_base + GT_COMP0);
> +	writel(counter.upper, gt_base + GT_COMP1);
> +
> +	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
> +
> +	if (periodic) {
> +		writel(delta, gt_base + GT_AUTO_INC);
> +		ctrl |= GT_CONTROL_AUTO_INC;
> +	}
> +
> +	writel(ctrl, gt_base + GT_CONTROL);
> +}
> +
> +static void gt_clockevent_set_mode(enum clock_event_mode mode,
> +				   struct clock_event_device *clk)
> +{
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		gt_compare_set(gt_clk_rate/HZ, 1);
> +		break;
> +	case CLOCK_EVT_MODE_ONESHOT:
> +		/* period set, and timer enabled in 'next_event' hook */
> +		BUG_ON(readl(gt_base + GT_CONTROL) &
> +		       (GT_CONTROL_COMP_ENABLE |
> +			GT_CONTROL_IRQ_ENABLE |
> +			GT_CONTROL_AUTO_INC));
> +		/* Fall through */
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +	default:
> +		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
> +		break;
> +	}
> +}
> +
> +static int gt_clockevent_set_next_event(unsigned long evt,
> +					struct clock_event_device *unused)
> +{
> +	gt_compare_set(evt, 0);
> +	return 0;
> +}
> +
> +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
> +
> +	writel(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
> +{
> +	struct clock_event_device **this_cpu_clk;
> +	int cpu = smp_processor_id();
> +
> +	clk->name = "Global Timer CE";
> +	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
> +	clk->set_mode = gt_clockevent_set_mode;
> +	clk->set_next_event = gt_clockevent_set_next_event;
> +	this_cpu_clk = __this_cpu_ptr(gt_evt);
> +	*this_cpu_clk = clk;
> +	clk->irq = gt_ppi;
> +	clockevents_config_and_register(clk, gt_clk_rate,
> +					0xf, 0xffffffff);
> +	per_cpu(percpu_init_called, cpu) = true;
> +	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
> +	return 0;
> +}
> +
> +static void gt_clockevents_stop(struct clock_event_device *clk)
> +{
> +	gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
> +	disable_percpu_irq(clk->irq);
> +}
> +
> +static int __cpuinit gt_clockevents_setup(struct clock_event_device *clk)
> +{
> +	int cpu = smp_processor_id();
> +
> +	/* Use existing clock_event for boot cpu */
> +	if (per_cpu(percpu_init_called, cpu))
> +		return 0;
> +
> +	writel(0, gt_base + GT_CONTROL);
> +	writel(0, gt_base + GT_COUNTER0);
> +	writel(0, gt_base + GT_COUNTER1);
> +	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
> +
> +	return gt_clockevents_init(clk);
> +}
> +
> +static cycle_t gt_clocksource_read(struct clocksource *cs)
> +{
> +	union gt_counter res = gt_counter_read();
> +	return res.cycles;
> +}
> +
> +static struct clocksource gt_clocksource = {
> +	.name	= "Global Timer CS",
> +	.rating	= 300,
> +	.read	= gt_clocksource_read,
> +	.mask	= CLOCKSOURCE_MASK(64),
> +	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void __init gt_clocksource_init(void)
> +{
> +	writel(0, gt_base + GT_CONTROL);
> +	writel(0, gt_base + GT_COUNTER0);
> +	writel(0, gt_base + GT_COUNTER1);
> +	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
> +
> +	gt_clocksource.shift = 20;
> +	gt_clocksource.mult =
> +		clocksource_hz2mult(gt_clk_rate, gt_clocksource.shift);
> +	clocksource_register(&gt_clocksource);
> +}
> +
> +static struct clk *gt_get_clock(void)
> +{
> +	struct clk *clk;
> +	int err;
> +
> +	clk = clk_get_sys("gt", NULL);
> +	if (IS_ERR(clk)) {
> +		pr_err("global-timer: clock not found: %ld\n", PTR_ERR(clk));
> +		return clk;
> +	}
> +
> +	err = clk_prepare_enable(clk);
> +	if (err) {
> +		pr_err("global-timer: clock prepare+enable failed: %d\n", err);
> +		clk_put(clk);
> +		return ERR_PTR(err);
> +	}
> +
> +	return clk;
> +}
> +
> +static struct local_timer_ops gt_lt_ops __cpuinitdata = {
> +	.setup	= gt_clockevents_setup,
> +	.stop	= gt_clockevents_stop,
> +};
> +
> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq)
> +{
> +	unsigned int cpu = smp_processor_id();
> +	struct clock_event_device *evt = &per_cpu(gt_clockevent, cpu);
> +	int err = 0;
> +
> +	if (gt_base) {
> +		pr_warn("global-timer: invalid base address\n");
> +		return -EINVAL;
> +	}
> +
> +	gt_clk = gt_get_clock();
> +	if (IS_ERR(gt_clk)) {
> +		pr_warn("global-timer: clk not found\n");
> +		return -EINVAL;
> +	}
> +
> +	gt_evt = alloc_percpu(struct clock_event_device *);
> +	if (!gt_evt) {
> +		pr_warn("global-timer: can't allocate memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	err = request_percpu_irq(timer_irq, gt_clockevent_interrupt,
> +				 "gt", gt_evt);
> +	if (err) {
> +		pr_warn("global-timer: can't register interrupt %d (%d)\n",
> +			timer_irq, err);
> +		goto out_free;
> +	}
> +
> +	gt_base = base;
> +	gt_clk_rate = clk_get_rate(gt_clk);
> +
> +	evt->irq = timer_irq;
> +	gt_ppi = timer_irq;
> +	evt->cpumask = cpumask_of(cpu);
> +
> +	gt_clocksource_init();
> +	gt_clockevents_init(evt);
> +	err =  local_timer_register(&gt_lt_ops);
> +	if (err) {
> +		pr_warn("global-timer: unable to register local timer.\n");
> +		goto out_irq;
> +	}
> +
> +	return 0;
> +
> +out_irq:
> +	free_percpu_irq(timer_irq, gt_evt);
> +out_free:
> +	free_percpu(gt_evt);
> +	return err;
> +}
> +
> +#ifdef CONFIG_OF
> +static void __init global_timer_of_register(struct device_node *np)
> +{
> +	struct clk *clk;
> +	int err = 0;
> +	int gt_ppi;
> +	static void __iomem *gt_base;
> +
> +	gt_ppi = irq_of_parse_and_map(np, 0);
> +	if (!gt_ppi) {
> +		err = -EINVAL;
> +		goto out;
> +	}
> +
> +	gt_base = of_iomap(np, 0);
> +	if (!gt_base) {
> +		err = -ENOMEM;
> +		goto out;
> +	}
> +
> +	clk = of_clk_get(np, 0);
> +	if (!IS_ERR(clk))
> +		clk_register_clkdev(clk, NULL, "gt");
> +
> +	global_timer_init(gt_base, gt_ppi);
> +
> +out:
> +	WARN(err, "Global timer register failed (%d)\n", err);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(arm_gt_a9, "arm,cortex-a9-global-timer",
> +			global_timer_of_register);
> +#endif
> 



From will.deacon at arm.com  Wed May  8 10:30:04 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 15:30:04 +0100
Subject: [PATCH] ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of the
 old/new value
In-Reply-To: <1368021817-17309-1-git-send-email-jaccon.bastiaansen@gmail.com>
References: <1368021817-17309-1-git-send-email-jaccon.bastiaansen@gmail.com>
Message-ID: <20130508143004.GA20820@mudshark.cambridge.arm.com>

On Wed, May 08, 2013 at 03:03:37PM +0100, jaccon.bastiaansen at gmail.com wrote:
> From: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
> 
> The implementation of cmpxchg64() for the ARM v6 and v7 architecture
> casts parameter 2 and 3 (the old and new 64bit values) to an unsigned
> long before calling the atomic_cmpxchg64() function. This clears
> the top 32 bits of the old and new values, resulting in the wrong
> values being compare-exchanged.
> 
> This bug is introduced by commit 3e0f5a15f5003f4576c35498814f0f1567860449

Please truncate the commit id to 12 characters and stick the title string in
brackets afterwards, e.g. 123456789abc ("will's broken commit"),

> Change-Id: I8e8a4c09c525ed8056385c9dc4d65163c28307dc

You can drop the Change-Id.

> Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
> ---
>  arch/arm/include/asm/cmpxchg.h |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 7eb18c1..4f009c1 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -233,15 +233,15 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
>  	((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr),	\
>  						atomic64_t,		\
>  						counter),		\
> -					      (unsigned long)(o),	\
> -					      (unsigned long)(n)))
> +					      (unsigned long long)(o),	\
> +					      (unsigned long long)(n)))
>  
>  #define cmpxchg64_local(ptr, o, n)					\
>  	((__typeof__(*(ptr)))local64_cmpxchg(container_of((ptr),	\
>  						local64_t,		\
>  						a),			\
> -					     (unsigned long)(o),	\
> -					     (unsigned long)(n)))
> +					     (unsigned long long)(o),	\
> +					     (unsigned long long)(n)))
>  
>  #endif	/* __LINUX_ARM_ARCH__ >= 6 */

With the above cleanup:

  Acked-by: Will Deacon <will.deacon at arm.com>

Will


From arnd at arndb.de  Wed May  8 10:34:43 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 16:34:43 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <201305081634.43498.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>

> +*st-asc(Serial Port)
> +
> +Required properties:
> +- compatible : Should be "st,asc".

Are there any hardware revision numbers for the asc? If there are potentially
incompatible or backwards-compatible variants, it would be good to include
the version in this string.

> +- reg, reg-names, interrupts, interrupt-names	: Standard way to define device
> +			resources with names. look in
> +			Documentation/devicetree/bindings/resource-names.txt
> +
> +Optional properties:
> +- st,hw-flow-ctrl	bool flag to enable hardware flow control.
> +- st,force-m1		bool flat to force asc to be in Mode-1 recommeded
> +			for high bit rates (above 19.2K)
> +Example:
> +serial at fe440000{
> +    compatible    = "st,asc";
> +    reg         = <0xfe440000 0x2c>;
> +    interrupts     =  <0 209 0>;
> +};

I would also recommed adding a way to set the default baud rate through
a property. Following the example of the 8250 driver, you should probably
call that "current-speed".

> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 7e7006f..346f325 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1484,6 +1484,25 @@ config SERIAL_RP2_NR_UARTS
>  	  If multiple cards are present, the default limit of 32 ports may
>  	  need to be increased.
>  
> +config SERIAL_ST_ASC
> +	tristate "ST ASC serial port support"
> +	depends on PLAT_STIXXXX
> +	default y
> +	select SERIAL_CORE
> +	help
> +	  This driver is for the on-chip Asychronous Serial Controller on
> +	  STMicroelectronics STixxxx SoCs.
> +	  ASC is embedded in ST COMMS IP block. It supports Rx & Tx functionality.
> +	  It support all industry standard baud rates.
> +
> +	  If unsure, say N.

I would not make it "default y".

> +config SERIAL_ST_ASC_CONSOLE
> +	bool "Support for console on ST ASC"
> +	depends on SERIAL_ST_ASC
> +	default y
> +	select SERIAL_CORE_CONSOLE
> +
>  endmenu

This needs to be "depends on SERIAL_ST_ASC=y". You would get a link error
if you try to make SERIAL_ST_ASC a loadable module and SERIAL_ST_ASC_CONSOLE
built-in.

> +
> +static struct asc_port asc_ports[ASC_MAX_PORTS];
> +static struct uart_driver asc_uart_driver;
> +
> +/*---- Forward function declarations---------------------------*/
> +static irqreturn_t asc_interrupt(int irq, void *ptr);
> +static void asc_transmit_chars(struct uart_port *);
> +static int asc_set_baud(struct asc_port *ascport, int baud);
> +

Please remove all forward declarations, by reordering the functions in
the way they are called.


> diff --git a/drivers/tty/serial/st-asc.h b/drivers/tty/serial/st-asc.h
> new file mode 100644
> index 0000000..e59f818
> --- /dev/null
> +++ b/drivers/tty/serial/st-asc.h
> +#ifndef _ST_ASC_H
> +#define _ST_ASC_H
> +
> +#include <linux/serial_core.h>
> +#include <linux/clk.h>
> +
> +struct asc_port {
> +	struct uart_port port;
> +	struct clk *clk;
> +	unsigned int hw_flow_control:1;
> +	unsigned int check_parity:1;
> +	unsigned int force_m1:1;
> +};

Since this header file is only used in one place, just merge it into
the driver itself.

> +#define ASC_MAJOR		204
> +#define ASC_MINOR_START		40

I don't know what the current policy is on allocating major/minor numbers,
but I'm sure you cannot just reuse one that is already used.

Documentation/devices.txt lists the ones that are officially assigned.
Can't you use dynamic allocation here?

	Arnd


From shawn.guo at linaro.org  Wed May  8 10:38:21 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 May 2013 22:38:21 +0800
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851B455F@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
 <20130503074105.GA31873@S2101-09.ap.freescale.net>
 <B56CDBE15CE27145A4B77D2D24263E851B455F@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <20130508143819.GE26072@S2101-09.ap.freescale.net>

On Wed, May 08, 2013 at 07:26:04AM +0000, Lu Jingchang-B35083 wrote:
> >If mvf600 uses the same wdt IP block as imx, we should make this restart
> >routine a common function to be used on mvf600, imx6q and imx6sl etc.
> >
> [Lu Jingchang-B35083] 
>     Do you have plan to update the mxc_restart() function in system.c?

Yes, I plan to update it to support DT platforms.

> We once used that common function for mvf600. But now this function cannot be used for mvf600 as the new clock framwork used.
>     On the other hand, even we udpated the clk_get for the the common mxc_restart() funciton. different with i.MX6, the MVF600 need to enable the clock before using the wdt module, we still need some clue code for i.mx and mvf600. So I suggest keep the restart function for mvf600 currently. Thanks.
> 
Ok, you can keep it for mvf600 and I will consolidate it to use
mxc_restart() later.  But please make the compatible looks like the
following, so that mxc_restart() will look for "fsl,imx21-wdt" to find
the node in device tree.

	compatible = "fsl,mvf600-wdt", "fsl,imx21-wdt"

Shawn



From arnd at arndb.de  Wed May  8 10:38:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 16:38:22 +0200
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <201305081638.23100.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> From: Stuart Menefy <stuart.menefy at st.com>
> 
> This is a simple driver for the global timer module found in the Cortex
> A9-MP cores from revision r1p0 onwards. This should be able to perform
> the functions of the system timer and the local timer in an SMP system.
> 
> The global timer has the following features:
>     The global timer is a 64-bit incrementing counter with an
> auto-incrementing feature. It continues incrementing after sending
> interrupts. The global timer is memory mapped in the private memory
> region.
>     The global timer is accessible to all Cortex-A9 processors in the
> cluster. Each Cortex-A9 processor has a private 64-bit comparator that
> is used to assert a private interrupt when the global timer has reached
> the comparator value. All the Cortex-A9 processors in a design use the
> banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
> Controller as a Private Peripheral Interrupt. The global timer is
> clocked by PERIPHCLK.
> 
> Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>

Are you sure we don't already have a driver for this? It sounds unlikely
that you are the first one to do this when the hardware is so common.

>  Documentation/devicetree/bindings/arm/gt.txt |   21 ++
>  arch/arm/Kconfig                             |    6 +
>  arch/arm/include/asm/global_timer.h          |   12 +
>  arch/arm/kernel/Makefile                     |    1 +
>  arch/arm/kernel/global_timer.c               |  325 ++++++++++++++++++++++++++
>  5 files changed, 365 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/gt.txt
>  create mode 100644 arch/arm/include/asm/global_timer.h
>  create mode 100644 arch/arm/kernel/global_timer.c

Move it into drivers/clocksource?
 
> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
> new file mode 100644
> index 0000000..46f9188
> --- /dev/null
> +++ b/arch/arm/include/asm/global_timer.h
> @@ -0,0 +1,12 @@
> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq);

I don't see a need to call this from platform code for non-DT platforms, it
can easily be used with CLOCKSOURCE_OF_DECLARE() all the time I think.

	Arnd


From plagnioj at jcrosoft.com  Wed May  8 10:39:08 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 8 May 2013 16:39:08 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305081634.43498.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
Message-ID: <20130508143908.GJ24282@game.jcrosoft.org>

On 16:34 Wed 08 May     , Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> > From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> 
> > +*st-asc(Serial Port)
> > +
> > +Required properties:
> > +- compatible : Should be "st,asc".
> 
> Are there any hardware revision numbers for the asc? If there are potentially
> incompatible or backwards-compatible variants, it would be good to include
> the version in this string.

The st,asc come from st20 or st200 IIRC which was not ARM but a ST arch
and then used on st40 series

an the st,asc for st200 and st40 are not compatible completly
> 
> > +- reg, reg-names, interrupts, interrupt-names	: Standard way to define device
> > +			resources with names. look in
> > +			Documentation/devicetree/bindings/resource-names.txt
> > +
> > +Optional properties:
> > +- st,hw-flow-ctrl	bool flag to enable hardware flow control.
> > +- st,force-m1		bool flat to force asc to be in Mode-1 recommeded
> > +			for high bit rates (above 19.2K)
> > +Example:
> > +serial at fe440000{
> > +    compatible    = "st,asc";
> > +    reg         = <0xfe440000 0x2c>;
> > +    interrupts     =  <0 209 0>;
> > +};
> 
> I would also recommed adding a way to set the default baud rate through
> a property. Following the example of the 8250 driver, you should probably
> call that "current-speed".
on st it has always be 38k

> 
> > diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> > index 7e7006f..346f325 100644
> > --- a/drivers/tty/serial/Kconfig
> > +++ b/drivers/tty/serial/Kconfig
> > @@ -1484,6 +1484,25 @@ config SERIAL_RP2_NR_UARTS
> >  	  If multiple cards are present, the default limit of 32 ports may
> >  	  need to be increased.
> >  
> > +config SERIAL_ST_ASC
> > +	tristate "ST ASC serial port support"
> > +	depends on PLAT_STIXXXX
> > +	default y
> > +	select SERIAL_CORE
> > +	help
> > +	  This driver is for the on-chip Asychronous Serial Controller on
> > +	  STMicroelectronics STixxxx SoCs.
> > +	  ASC is embedded in ST COMMS IP block. It supports Rx & Tx functionality.
> > +	  It support all industry standard baud rates.
> > +
> > +	  If unsure, say N.
> 
> I would not make it "default y".
me too
> 
> > +config SERIAL_ST_ASC_CONSOLE
> > +	bool "Support for console on ST ASC"
> > +	depends on SERIAL_ST_ASC
> > +	default y
> > +	select SERIAL_CORE_CONSOLE
> > +
> >  endmenu
> 
> This needs to be "depends on SERIAL_ST_ASC=y". You would get a link error
> if you try to make SERIAL_ST_ASC a loadable module and SERIAL_ST_ASC_CONSOLE
> built-in.
> 
> > +
> > +static struct asc_port asc_ports[ASC_MAX_PORTS];
> > +static struct uart_driver asc_uart_driver;
> > +
> > +/*---- Forward function declarations---------------------------*/
> > +static irqreturn_t asc_interrupt(int irq, void *ptr);
> > +static void asc_transmit_chars(struct uart_port *);
> > +static int asc_set_baud(struct asc_port *ascport, int baud);
> > +
> 
> Please remove all forward declarations, by reordering the functions in
> the way they are called.
> 
and drop the dummy functions
> 
> > diff --git a/drivers/tty/serial/st-asc.h b/drivers/tty/serial/st-asc.h
> > new file mode 100644
> > index 0000000..e59f818
> > --- /dev/null
> > +++ b/drivers/tty/serial/st-asc.h
> > +#ifndef _ST_ASC_H
> > +#define _ST_ASC_H
> > +
> > +#include <linux/serial_core.h>
> > +#include <linux/clk.h>
> > +
> > +struct asc_port {
> > +	struct uart_port port;
> > +	struct clk *clk;
> > +	unsigned int hw_flow_control:1;
> > +	unsigned int check_parity:1;
> > +	unsigned int force_m1:1;
> > +};
> 
> Since this header file is only used in one place, just merge it into
> the driver itself.
> 
> > +#define ASC_MAJOR		204
> > +#define ASC_MINOR_START		40
> 
> I don't know what the current policy is on allocating major/minor numbers,
> but I'm sure you cannot just reuse one that is already used.
> 
> Documentation/devices.txt lists the ones that are officially assigned.
> Can't you use dynamic allocation here?
> 
> 	Arnd
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From Catalin.Marinas at arm.com  Wed May  8 10:49:19 2013
From: Catalin.Marinas at arm.com (Catalin Marinas)
Date: Wed, 8 May 2013 15:49:19 +0100
Subject: [GIT PULL] arm64 patches for 3.10-rc1
Message-ID: <20130508144919.GG2703@arm.com>

Hi Linus,

That's a second round of arm64 patches for this merging window. They are
based on top of my previous pull request (commit 16c85a1fd, which was
based on 3.9-rc3). There is a 'gic' branch which I already pushed
upstream via Olof (commit c2573077) and required to enable ARM_GIC
support on arm64, hence the merge into my branch as well. The diffstat
you should get from this pull is the one shown below, without the 'gic'
changes.

Thanks.

The following changes since commit 16c85a1fd73eade2ae290d759924c09b4595f504:

  arm64: Use acquire/release semantics instead of explicit DMB (2013-04-30 15:58:37 +0100)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git tags/arm64-for-linus

for you to fetch changes up to 420c158dcf96ee3a5758c9bf1586b163584c75c7:

  arm64: Treat the bitops index argument as an 'int' (2013-05-08 10:33:17 +0100)

----------------------------------------------------------------
- Since drivers/irqchip/irq-gic.c no longer has dependencies on arm32
  specifics (the 'gic' branch merged), it can be enabled on arm64.
- Enable arm64 support for poweroff/restart (for code under
  drivers/power/reset/).
- Fixes (dts file, exception handling, bitops)

----------------------------------------------------------------
Catalin Marinas (5):
      Merge branch 'gic' into HEAD
      arm64: Enable support for the ARM GIC interrupt controller
      arm64: vexpress: Add support for poweroff/restart
      arm64: Ignore the 'write' ESR flag on cache maintenance faults
      arm64: Treat the bitops index argument as an 'int'

Mark Rutland (1):
      arm64: dts: fix #address-cells for foundation-v8

 arch/arm64/Kconfig                    |  4 ++++
 arch/arm64/boot/dts/foundation-v8.dts |  2 +-
 arch/arm64/include/asm/system_misc.h  |  2 +-
 arch/arm64/kernel/process.c           |  8 ++++----
 arch/arm64/lib/bitops.S               | 10 +++++-----
 arch/arm64/mm/fault.c                 |  3 ++-
 6 files changed, 17 insertions(+), 12 deletions(-)


From will.deacon at arm.com  Wed May  8 10:49:07 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 15:49:07 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <201305081638.23100.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081638.23100.arnd@arndb.de>
Message-ID: <20130508144907.GB20820@mudshark.cambridge.arm.com>

On Wed, May 08, 2013 at 03:38:22PM +0100, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> > From: Stuart Menefy <stuart.menefy at st.com>
> > 
> > This is a simple driver for the global timer module found in the Cortex
> > A9-MP cores from revision r1p0 onwards. This should be able to perform
> > the functions of the system timer and the local timer in an SMP system.
> > 
> > The global timer has the following features:
> >     The global timer is a 64-bit incrementing counter with an
> > auto-incrementing feature. It continues incrementing after sending
> > interrupts. The global timer is memory mapped in the private memory
> > region.
> >     The global timer is accessible to all Cortex-A9 processors in the
> > cluster. Each Cortex-A9 processor has a private 64-bit comparator that
> > is used to assert a private interrupt when the global timer has reached
> > the comparator value. All the Cortex-A9 processors in a design use the
> > banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
> > Controller as a Private Peripheral Interrupt. The global timer is
> > clocked by PERIPHCLK.
> > 
> > Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> >
> 
> Are you sure we don't already have a driver for this? It sounds unlikely
> that you are the first one to do this when the hardware is so common.

An additional reason why people don't make use of this timer (on top of the
power domain concerns raised by Rob) is due to the following from the A9
TRM:

  `From r2p0 the comparators for each processor with the global timer fire
   when the timer value is greater than or equal to. In previous revisions
   the comparators fired when the timer value was equal to.'

So you'll get into all sorts of horrible races on those older revisions if
you're not careful.

Will


From arnd at arndb.de  Wed May  8 10:50:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 16:50:22 +0200
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <201305081650.23264.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> 
> This patch introduces syscon_claim, syscon_read, syscon_write,
> syscon_release APIs to help drivers to use syscon registers in much more
> flexible way.
> 
> With this patch, a driver can claim few/all bits in the syscon registers
> and do read/write and then release them when its totally finished with
> them, in the mean time if another driver requests same bits or registers
> the API will detect conflit and return error to the second request.
> 
> Reason to introduce this API.
> System configuration/control registers are very basic configuration
> registers arranged in groups across ST Settop Box parts. These registers
> are independent of IP itself. Many IPs, clock, pad and other functions
> are wired up to these registers.
> 
> In many cases a single syconf register contains bits related to multiple
> devices, and therefore it need to be shared across multiple drivers at
> bit level. The same IP block can have different syscon mappings on
> different SOCs.
> 
> Typically in a SOC there will be more than hundreds of these registers,
> which are again divided into groups.
> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> CC: Stuart Menefy <stuart.menefy at st.com>

My feeling is that syscon is the wrong place for this functionality,
since regmap already handles (some of?) these issues. If you need
additional synchronization, it's probably best to extend regmap
as needed so other code besides syscon can take advantage of that
as well.

	Arnd


From s.trumtrar at pengutronix.de  Wed May  8 10:51:24 2013
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Wed, 8 May 2013 16:51:24 +0200
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <201305081638.23100.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081638.23100.arnd@arndb.de>
Message-ID: <20130508145124.GA29391@pengutronix.de>

On Wed, May 08, 2013 at 04:38:22PM +0200, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> > From: Stuart Menefy <stuart.menefy at st.com>
> > 
> > This is a simple driver for the global timer module found in the Cortex
> > A9-MP cores from revision r1p0 onwards. This should be able to perform
> > the functions of the system timer and the local timer in an SMP system.
> > 
> > The global timer has the following features:
> >     The global timer is a 64-bit incrementing counter with an
> > auto-incrementing feature. It continues incrementing after sending
> > interrupts. The global timer is memory mapped in the private memory
> > region.
> >     The global timer is accessible to all Cortex-A9 processors in the
> > cluster. Each Cortex-A9 processor has a private 64-bit comparator that
> > is used to assert a private interrupt when the global timer has reached
> > the comparator value. All the Cortex-A9 processors in a design use the
> > banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
> > Controller as a Private Peripheral Interrupt. The global timer is
> > clocked by PERIPHCLK.
> > 
> > Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> >
> 
> Are you sure we don't already have a driver for this? It sounds unlikely
> that you are the first one to do this when the hardware is so common.
> 

Isn't this the same as arch/arm/kernel/smp_twd.c ?
That is atleast the timer I used with Cortex-A9. I don't think the core
has another one. But maybe I'm wrong.

> >  Documentation/devicetree/bindings/arm/gt.txt |   21 ++
> >  arch/arm/Kconfig                             |    6 +
> >  arch/arm/include/asm/global_timer.h          |   12 +
> >  arch/arm/kernel/Makefile                     |    1 +
> >  arch/arm/kernel/global_timer.c               |  325 ++++++++++++++++++++++++++
> >  5 files changed, 365 insertions(+), 0 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/gt.txt
> >  create mode 100644 arch/arm/include/asm/global_timer.h
> >  create mode 100644 arch/arm/kernel/global_timer.c
> 
> Move it into drivers/clocksource?
>  
> > diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
> > new file mode 100644
> > index 0000000..46f9188
> > --- /dev/null
> > +++ b/arch/arm/include/asm/global_timer.h
> > @@ -0,0 +1,12 @@
> > +int __init global_timer_init(void __iomem *base, unsigned int timer_irq);
> 
> I don't see a need to call this from platform code for non-DT platforms, it
> can easily be used with CLOCKSOURCE_OF_DECLARE() all the time I think.
> 

Regards,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From broonie at kernel.org  Wed May  8 11:01:41 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 8 May 2013 16:01:41 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <201305081650.23264.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
Message-ID: <20130508150141.GA5057@opensource.wolfsonmicro.com>

On Wed, May 08, 2013 at 04:50:22PM +0200, Arnd Bergmann wrote:

> > In many cases a single syconf register contains bits related to multiple
> > devices, and therefore it need to be shared across multiple drivers at
> > bit level. The same IP block can have different syscon mappings on
> > different SOCs.

> My feeling is that syscon is the wrong place for this functionality,
> since regmap already handles (some of?) these issues. If you need
> additional synchronization, it's probably best to extend regmap
> as needed so other code besides syscon can take advantage of that
> as well.

This sounds like regmap_update_bits() ought to be all that's needed.
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From lee.jones at linaro.org  Wed May  8 11:02:55 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 May 2013 16:02:55 +0100
Subject: [PATCH 19/63] dmaengine: ste_dma40: Separate Logical Global
 Interrupt Mask (GIM) unmasking
In-Reply-To: <CACRpkdZexk6a7yaWEzzOkihcHNGY_UQN3hYiz45LK1cuy0ob=g@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-20-git-send-email-lee.jones@linaro.org>
 <CACRpkdZexk6a7yaWEzzOkihcHNGY_UQN3hYiz45LK1cuy0ob=g@mail.gmail.com>
Message-ID: <20130508150255.GJ3459@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > During the initial setup of a logical channel, it is necessary to unmask
> > the GIM in order to receive generated terminal count and error interrupts.
> > We're separating out this required code so it will be possible to move
> > the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> > into the runtime_config() routine.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> These review comments are only partially accounted for:
> http://marc.info/?l=linux-kernel&m=136688761708399&w=2
> 
> Please supply a short changelog in the next submission
> so I know what was changed and why some things were not
> changed and if you split out other changes to other patches
> etc etc.

All of the comments are accounted for. The is_log argument is actually
removed in patch 20, as it's still used to only run the code within
the clause if the channel is physical.

... and yes, the dmatest works perfectly on patch 19.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From stuart.menefy at st.com  Wed May  8 11:06:36 2013
From: stuart.menefy at st.com (Stuart MENEFY)
Date: Wed, 08 May 2013 16:06:36 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <518A6099.8070505@gmail.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <518A6099.8070505@gmail.com>
Message-ID: <518A69FC.1090600@st.com>

On 08/05/13 15:26, Rob Herring wrote:
> On 05/08/2013 09:11 AM, Srinivas KANDAGATLA wrote:
>> From: Stuart Menefy <stuart.menefy at st.com>
>>
>> This is a simple driver for the global timer module found in the Cortex
>> A9-MP cores from revision r1p0 onwards. This should be able to perform
>> the functions of the system timer and the local timer in an SMP system.
>>
>> The global timer has the following features:
>>     The global timer is a 64-bit incrementing counter with an
>> auto-incrementing feature. It continues incrementing after sending
>> interrupts. The global timer is memory mapped in the private memory
>> region.
>>     The global timer is accessible to all Cortex-A9 processors in the
>> cluster. Each Cortex-A9 processor has a private 64-bit comparator that
>> is used to assert a private interrupt when the global timer has reached
>> the comparator value. All the Cortex-A9 processors in a design use the
>> banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
>> Controller as a Private Peripheral Interrupt. The global timer is
>> clocked by PERIPHCLK.
> 
> PERIPHCLK scales with cpu clock typically so the global timer is not a
> suitable clocksource if you use cpufreq. You can deal with the scaling
> on clockevents, but not a clocksource. I imagine the global timers is
> also typically power-gated in some low power modes. This is why no one
> has added support already. Are neither of those an issue or going to be
> an issue for you?

I agree but we're limited by the available hardware, the SoC designers
didn't put down any general purpose timers unfortunately, so we have to
use the global timer as a clocksource.

The full version of this code has a cpufreq notifier to try and cope with
changes, but we didn't include that as the rest of the cpufreq code is
missing in this first post. There will be inaccuracies of course, but its
the best we can do.

There is no power gating on these devices, and clock gating only occurs
at the clock input to the A9 subsystem including the cores and timers,
so we don't have that issue.

Stuart

>> Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> ---
>>  Documentation/devicetree/bindings/arm/gt.txt |   21 ++
>>  arch/arm/Kconfig                             |    6 +
>>  arch/arm/include/asm/global_timer.h          |   12 +
>>  arch/arm/kernel/Makefile                     |    1 +
>>  arch/arm/kernel/global_timer.c               |  325 ++++++++++++++++++++++++++
>>  5 files changed, 365 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/gt.txt
>>  create mode 100644 arch/arm/include/asm/global_timer.h
>>  create mode 100644 arch/arm/kernel/global_timer.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/gt.txt b/Documentation/devicetree/bindings/arm/gt.txt
>> new file mode 100644
>> index 0000000..4ec5fb0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/gt.txt
>> @@ -0,0 +1,21 @@
>> +
>> +* ARM Global Timer
>> +	Cortex-A9 are often associated with a per-core Global timer.
>> +
>> +** Timer node required properties:
>> +
>> +- compatible : Should be one of:
>> +	"arm,cortex-a9-global-timer"
>> +
>> +- interrupts : One interrupt to each core
>> +
>> +- reg : Specify the base address and the size of the GT timer
>> +	register window.
>> +
>> +Example:
>> +
>> +	gt-timer at 2c000600 {
>> +		compatible = "arm,cortex-a9-global-timer";
>> +		reg = <0x2c000600 0x20>;
>> +		interrupts = <1 13 0xf01>;
>> +	};
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 1cacda4..c8c524e 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -1606,6 +1606,12 @@ config HAVE_ARM_TWD
>>  	help
>>  	  This options enables support for the ARM timer and watchdog unit
>>  
>> +config HAVE_ARM_GT
>> +	bool
>> +	select CLKSRC_OF if OF
>> +	help
>> +	  This options enables support for the ARM global timer unit
>> +
>>  choice
>>  	prompt "Memory split"
>>  	default VMSPLIT_3G
>> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
>> new file mode 100644
>> index 0000000..46f9188
>> --- /dev/null
>> +++ b/arch/arm/include/asm/global_timer.h
>> @@ -0,0 +1,12 @@
>> +/*
>> + * arch/arm/include/asm/global_timer.h
>> + *
>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
>> + * Author: Stuart Menefy <stuart.menefy at st.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq);
>> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
>> index 5f3338e..af51808 100644
>> --- a/arch/arm/kernel/Makefile
>> +++ b/arch/arm/kernel/Makefile
>> @@ -35,6 +35,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
>>  obj-$(CONFIG_SMP)		+= smp.o smp_tlb.o
>>  obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
>>  obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
>> +obj-$(CONFIG_HAVE_ARM_GT)	+= global_timer.o
>>  obj-$(CONFIG_ARM_ARCH_TIMER)	+= arch_timer.o
>>  obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o insn.o
>>  obj-$(CONFIG_FUNCTION_GRAPH_TRACER)	+= ftrace.o insn.o
>> diff --git a/arch/arm/kernel/global_timer.c b/arch/arm/kernel/global_timer.c
>> new file mode 100644
>> index 0000000..0ab1af3
>> --- /dev/null
>> +++ b/arch/arm/kernel/global_timer.c
>> @@ -0,0 +1,325 @@
>> +/*
>> + * linux/arch/arm/kernel/global_timer.c
>> + *
>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
>> + * Author: Stuart Menefy <stuart.menefy at st.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/clocksource.h>
>> +#include <linux/clockchips.h>
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_address.h>
>> +
>> +#include <asm/mach/irq.h>
>> +#include <asm/global_timer.h>
>> +#include <asm/localtimer.h>
>> +
>> +#define GT_COUNTER0	0x00
>> +#define GT_COUNTER1	0x04
>> +
>> +#define GT_CONTROL	0x08
>> +#define GT_CONTROL_TIMER_ENABLE		BIT(0)
>> +#define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
>> +#define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
>> +#define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
>> +
>> +#define GT_INT_STATUS	0x0c
>> +#define GT_INT_STATUS_EVENT_FLAG	BIT(0)
>> +
>> +#define GT_COMP0	0x10
>> +#define GT_COMP1	0x14
>> +#define GT_AUTO_INC	0x18
>> +
>> +/*
>> + * We are expecting to be clocked by the ARM peripheral clock.
>> + *
>> + * Note: it is assumed we are using a prescaler value of zero, so this is
>> + * the units for all operations.
>> + */
>> +static void __iomem *gt_base;
>> +static struct clk *gt_clk;
>> +static unsigned long gt_clk_rate;
>> +static int gt_ppi;
>> +static struct clock_event_device __percpu **gt_evt;
>> +static DEFINE_PER_CPU(bool, percpu_init_called);
>> +static DEFINE_PER_CPU(struct clock_event_device, gt_clockevent);
>> +
>> +union gt_counter {
>> +	cycle_t cycles;
>> +	struct {
>> +		uint32_t lower;
>> +		uint32_t upper;
>> +	};
>> +};
>> +
>> +static union gt_counter gt_counter_read(void)
>> +{
>> +	union gt_counter res;
>> +	uint32_t upper;
>> +
>> +	upper = readl(gt_base + GT_COUNTER1);
>> +	do {
>> +		res.upper = upper;
>> +		res.lower = readl(gt_base + GT_COUNTER0);
>> +		upper = readl(gt_base + GT_COUNTER1);
>> +	} while (upper != res.upper);
>> +
>> +	return res;
>> +}
>> +
>> +static void gt_compare_set(unsigned long delta, int periodic)
>> +{
>> +	union gt_counter counter = gt_counter_read();
>> +	unsigned long ctrl = readl(gt_base + GT_CONTROL);
>> +
>> +	BUG_ON(!(ctrl & GT_CONTROL_TIMER_ENABLE));
>> +	BUG_ON(ctrl & (GT_CONTROL_COMP_ENABLE |
>> +		       GT_CONTROL_IRQ_ENABLE |
>> +		       GT_CONTROL_AUTO_INC));
>> +
>> +	counter.cycles += delta;
>> +	writel(counter.lower, gt_base + GT_COMP0);
>> +	writel(counter.upper, gt_base + GT_COMP1);
>> +
>> +	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
>> +
>> +	if (periodic) {
>> +		writel(delta, gt_base + GT_AUTO_INC);
>> +		ctrl |= GT_CONTROL_AUTO_INC;
>> +	}
>> +
>> +	writel(ctrl, gt_base + GT_CONTROL);
>> +}
>> +
>> +static void gt_clockevent_set_mode(enum clock_event_mode mode,
>> +				   struct clock_event_device *clk)
>> +{
>> +	switch (mode) {
>> +	case CLOCK_EVT_MODE_PERIODIC:
>> +		gt_compare_set(gt_clk_rate/HZ, 1);
>> +		break;
>> +	case CLOCK_EVT_MODE_ONESHOT:
>> +		/* period set, and timer enabled in 'next_event' hook */
>> +		BUG_ON(readl(gt_base + GT_CONTROL) &
>> +		       (GT_CONTROL_COMP_ENABLE |
>> +			GT_CONTROL_IRQ_ENABLE |
>> +			GT_CONTROL_AUTO_INC));
>> +		/* Fall through */
>> +	case CLOCK_EVT_MODE_UNUSED:
>> +	case CLOCK_EVT_MODE_SHUTDOWN:
>> +	default:
>> +		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
>> +		break;
>> +	}
>> +}
>> +
>> +static int gt_clockevent_set_next_event(unsigned long evt,
>> +					struct clock_event_device *unused)
>> +{
>> +	gt_compare_set(evt, 0);
>> +	return 0;
>> +}
>> +
>> +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
>> +
>> +	writel(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
>> +	evt->event_handler(evt);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
>> +{
>> +	struct clock_event_device **this_cpu_clk;
>> +	int cpu = smp_processor_id();
>> +
>> +	clk->name = "Global Timer CE";
>> +	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
>> +	clk->set_mode = gt_clockevent_set_mode;
>> +	clk->set_next_event = gt_clockevent_set_next_event;
>> +	this_cpu_clk = __this_cpu_ptr(gt_evt);
>> +	*this_cpu_clk = clk;
>> +	clk->irq = gt_ppi;
>> +	clockevents_config_and_register(clk, gt_clk_rate,
>> +					0xf, 0xffffffff);
>> +	per_cpu(percpu_init_called, cpu) = true;
>> +	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
>> +	return 0;
>> +}
>> +
>> +static void gt_clockevents_stop(struct clock_event_device *clk)
>> +{
>> +	gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
>> +	disable_percpu_irq(clk->irq);
>> +}
>> +
>> +static int __cpuinit gt_clockevents_setup(struct clock_event_device *clk)
>> +{
>> +	int cpu = smp_processor_id();
>> +
>> +	/* Use existing clock_event for boot cpu */
>> +	if (per_cpu(percpu_init_called, cpu))
>> +		return 0;
>> +
>> +	writel(0, gt_base + GT_CONTROL);
>> +	writel(0, gt_base + GT_COUNTER0);
>> +	writel(0, gt_base + GT_COUNTER1);
>> +	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
>> +
>> +	return gt_clockevents_init(clk);
>> +}
>> +
>> +static cycle_t gt_clocksource_read(struct clocksource *cs)
>> +{
>> +	union gt_counter res = gt_counter_read();
>> +	return res.cycles;
>> +}
>> +
>> +static struct clocksource gt_clocksource = {
>> +	.name	= "Global Timer CS",
>> +	.rating	= 300,
>> +	.read	= gt_clocksource_read,
>> +	.mask	= CLOCKSOURCE_MASK(64),
>> +	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
>> +};
>> +
>> +static void __init gt_clocksource_init(void)
>> +{
>> +	writel(0, gt_base + GT_CONTROL);
>> +	writel(0, gt_base + GT_COUNTER0);
>> +	writel(0, gt_base + GT_COUNTER1);
>> +	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
>> +
>> +	gt_clocksource.shift = 20;
>> +	gt_clocksource.mult =
>> +		clocksource_hz2mult(gt_clk_rate, gt_clocksource.shift);
>> +	clocksource_register(&gt_clocksource);
>> +}
>> +
>> +static struct clk *gt_get_clock(void)
>> +{
>> +	struct clk *clk;
>> +	int err;
>> +
>> +	clk = clk_get_sys("gt", NULL);
>> +	if (IS_ERR(clk)) {
>> +		pr_err("global-timer: clock not found: %ld\n", PTR_ERR(clk));
>> +		return clk;
>> +	}
>> +
>> +	err = clk_prepare_enable(clk);
>> +	if (err) {
>> +		pr_err("global-timer: clock prepare+enable failed: %d\n", err);
>> +		clk_put(clk);
>> +		return ERR_PTR(err);
>> +	}
>> +
>> +	return clk;
>> +}
>> +
>> +static struct local_timer_ops gt_lt_ops __cpuinitdata = {
>> +	.setup	= gt_clockevents_setup,
>> +	.stop	= gt_clockevents_stop,
>> +};
>> +
>> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq)
>> +{
>> +	unsigned int cpu = smp_processor_id();
>> +	struct clock_event_device *evt = &per_cpu(gt_clockevent, cpu);
>> +	int err = 0;
>> +
>> +	if (gt_base) {
>> +		pr_warn("global-timer: invalid base address\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	gt_clk = gt_get_clock();
>> +	if (IS_ERR(gt_clk)) {
>> +		pr_warn("global-timer: clk not found\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	gt_evt = alloc_percpu(struct clock_event_device *);
>> +	if (!gt_evt) {
>> +		pr_warn("global-timer: can't allocate memory\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	err = request_percpu_irq(timer_irq, gt_clockevent_interrupt,
>> +				 "gt", gt_evt);
>> +	if (err) {
>> +		pr_warn("global-timer: can't register interrupt %d (%d)\n",
>> +			timer_irq, err);
>> +		goto out_free;
>> +	}
>> +
>> +	gt_base = base;
>> +	gt_clk_rate = clk_get_rate(gt_clk);
>> +
>> +	evt->irq = timer_irq;
>> +	gt_ppi = timer_irq;
>> +	evt->cpumask = cpumask_of(cpu);
>> +
>> +	gt_clocksource_init();
>> +	gt_clockevents_init(evt);
>> +	err =  local_timer_register(&gt_lt_ops);
>> +	if (err) {
>> +		pr_warn("global-timer: unable to register local timer.\n");
>> +		goto out_irq;
>> +	}
>> +
>> +	return 0;
>> +
>> +out_irq:
>> +	free_percpu_irq(timer_irq, gt_evt);
>> +out_free:
>> +	free_percpu(gt_evt);
>> +	return err;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +static void __init global_timer_of_register(struct device_node *np)
>> +{
>> +	struct clk *clk;
>> +	int err = 0;
>> +	int gt_ppi;
>> +	static void __iomem *gt_base;
>> +
>> +	gt_ppi = irq_of_parse_and_map(np, 0);
>> +	if (!gt_ppi) {
>> +		err = -EINVAL;
>> +		goto out;
>> +	}
>> +
>> +	gt_base = of_iomap(np, 0);
>> +	if (!gt_base) {
>> +		err = -ENOMEM;
>> +		goto out;
>> +	}
>> +
>> +	clk = of_clk_get(np, 0);
>> +	if (!IS_ERR(clk))
>> +		clk_register_clkdev(clk, NULL, "gt");
>> +
>> +	global_timer_init(gt_base, gt_ppi);
>> +
>> +out:
>> +	WARN(err, "Global timer register failed (%d)\n", err);
>> +}
>> +
>> +CLOCKSOURCE_OF_DECLARE(arm_gt_a9, "arm,cortex-a9-global-timer",
>> +			global_timer_of_register);
>> +#endif
>>
> 




From catalin.marinas at arm.com  Wed May  8 11:08:00 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 8 May 2013 16:08:00 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
References: <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
Message-ID: <20130508150800.GI2703@arm.com>

On Sat, May 04, 2013 at 09:21:27AM +0100, Ming Lei wrote:
> On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
> >>
> >> I assume that you inhibited the call to flush_dcache_page() in
> >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
> >> with warnings.
> >
> > I haven't done any stress testing so I don't think I hit this code path,
> > so no warning. But yes, it should have triggered. Anyway, in this case
> > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
> > harmless anyway if we also ignore this bit in __sync_icache_dcache for
> > non-aliasing caches).
> 
> Yes, maybe we can do a little optimization for O_DIRECT since no
> dcache alias and I/D coherency problem in this case on ARMv7, how
> about below change?
> 
> diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> index 1c8f7f5..962a657 100644
> --- a/arch/arm/mm/flush.c
> +++ b/arch/arm/mm/flush.c
> @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
>  	    mapping && !mapping_mapped(mapping))
>  		clear_bit(PG_dcache_clean, &page->flags);
>  	else {
> +		if (!mapping && cache_is_vipt_nonaliasing())
> +			return;
>  		__flush_dcache_page(mapping, page);
>  		if (mapping && cache_is_vivt())
>  			__flush_dcache_aliases(mapping, page);

I wonder whether we could move the:

	if (!mapping)
		return

at the top of this function, IOW don't touch any anonymous pages. Would
anything be broken (apart from wrong API use)?

-- 
Catalin


From arnd at arndb.de  Wed May  8 11:10:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 17:10:23 +0200
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <Pine.LNX.4.44L0.1305081011480.1450-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305081011480.1450-100000@iolanthe.rowland.org>
Message-ID: <201305081710.23489.arnd@arndb.de>

On Wednesday 08 May 2013, Alan Stern wrote:
> > The first occurence was apparently in 3.3, but only in ehci-tegra.c,
> > while the other drivers subsequently copied the bug.
> 
> An alternative solution -- perhaps not better but also not relying on
> coherent_dma_mask -- is to clear pdev->dev.dma_mask in the remove
> routine if it points to the static mask value.
> 

Yes, I thought about that, but couldn't see any advantage one way
or the other and this one seemed simpler.

	Arnd


From plagnioj at jcrosoft.com  Wed May  8 11:06:29 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 8 May 2013 17:06:29 +0200
Subject: [RFC 4/8] pinctrl:stixxxx: Add pinctrl and pinconf support.
In-Reply-To: <1368022284-2283-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022284-2283-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <20130508150629.GA3041@game.jcrosoft.org>

On 15:11 Wed 08 May     , Srinivas KANDAGATLA wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> 
> This patch add pinctrl support to ST SoCs.
> 
> About hardware:
> ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
> pin configurations.
> 
> Each multi-function pin is controlled, driven and routed through the PIO
> multiplexing block. Each pin supports GPIO functionality (ALT0) and
> multiple alternate functions(ALT1 - ALTx) that directly connect the pin
> to different hardware blocks. When a pin is in GPIO mode, Output Enable
> (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
> block. Otherwise the PIO multiplexing block configures these parameters
> and retiming the signal.
> 
g> About driver:
> This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
> pinconf, pinmux, gpio subsystems. All the pinctrl related config
> information can only come from device trees.
> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> CC: Stephen Gallimore <stephen.gallimore at st.com>
> CC: Stuart Menefy <stuart.menefy at st.com>
> ---
>  .../bindings/pinctrl/pinctrl-stixxxx.txt           |  160 +++
>  drivers/pinctrl/Kconfig                            |   13 +
>  drivers/pinctrl/Makefile                           |    1 +
>  drivers/pinctrl/pinctrl-stixxxx.c                  | 1151 ++++++++++++++++++++
>  drivers/pinctrl/pinctrl-stixxxx.h                  |  197 ++++
the pinctrl is present in older SoC ST40 not only stixxx

and you must provide a proper name not stixxxx

>  5 files changed, 1522 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>  create mode 100644 drivers/pinctrl/pinctrl-stixxxx.c
>  create mode 100644 drivers/pinctrl/pinctrl-stixxxx.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
> new file mode 100644
> index 0000000..b0a93b5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
> @@ -0,0 +1,160 @@
> +*ST pin controller.
> +
> +Each multi-function pin is controlled, driven and routed through the
> +PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
> +and multiple alternate functions(ALT1 - ALTx) that directly connect
> +the pin to different hardware blocks.
> +
> +When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
> +Pull Up (PU) are driven by the related PIO block.
HighZ too

this driver look very similar with AT91 we should consolidate at binding and C
level
> 
> ---
> +
> +ST pinctrl driver controls PIO multiplexing block and also interacts with
> +gpio driver to configure a pin.
> +
> +Required properties: (PIO multiplexing block)
> +- compatible	: should be "st,stixxxx-pinctrl"
> +			each subnode should set "st,stixxxx-gpio"
> +			as compatible for each gpio-controller bank.
first soc where the IP is present
> +- gpio-controller : Indicates this device is a GPIO controller
> +- #gpio-cells	  : Should be one. The first cell is the pin number.
> +- #retime-delay-cells	: Should be number of possible retime delays.
> +- st,retime-in-delay	: Should be array of delays in nsecs.
> +- st,retime-out-delay	: Should be array of delays in nsecs.
> +- retime-style		: Should indicate which type of retime is used.
> +			possible values are "none", "packed" and "dedicated".
always prefix st, when specific property
st,
> +- st,retime-offset	: phandle to retime offsets in retime registers.
> +		These are not necessary for "dedicated" retime-style registers.
> +	- clk1notclk0	: Should define offset for clk1not clk0 in retime register.
> +	- delay-lsb	: Should define offset for delay-lsb in retime register.
> +	- delay-msb	: Should define offset for delay msb in retime register.
> +	- invertclk	: Should define offset for invertclk in retime register.
> +	- retime	: Should define offset for retime in retime register.
> +	- clknotdata	: Should define offset for clknotdata in retime register.
> +	- double_edge	: Should define offset for double edge in retime register.

As much as I like to describe the IP in the DT, I think it's too much this
time move this to C and use the compatible or detect it on the hardware to
handle this 

> +- st,alt-control		: Should be sysconf to control alternate function on pio.
> +- st,oe-control		: Should be sysconf to control output enable on pio.
> +- st,pu-control		: Should be sysconf to control pull up on pio.
> +- st,od-control		: Should be sysconf to control open drain on pio.
> +- st,retime-style		: Should indicate which type of retime is used.
> +			possible values are "none", "packed" and "dedicated".
> +- st,retime-pin-mask	: Should be mask to specify which pins can be retimed.
> +- retime-control[0...N]: These properties point to sysconfs which control retime.
> +			Depending on retime-style the number of retime-controls
> +			vary: 2 for "packed"; 8 for "dedicated".


> +- st,bank-name		: Should be a name string for this bank.
> +
> +Example:
> +	pio_retime_offset: pio-retime-offset {
> +		clk1notclk0	= <0>;
> +		delay-lsb	= <2>;
> +		delay-msb	= <3>;
> +		invertclk	= <4>;
> +		retime		= <5>;
> +		clknotdata	= <6>;
> +		double-edge	= <7>;
> +	};
> +
> +	pin-controller {
> +		#retime-delay-cells = <4>;
> +		compatible = "st,stixxxx-pinctrl", "simple-bus";
> +		st,retime-offset = <&pio_retime_offset>;
> +		st,retime-in-delay = <0 500 1000 1500>;
> +		st,retime-out-delay = <0 1000 2000 3000>;
> +		ranges;
> +		PIO0: pinctrl at fe610000 {
> +			gpio-controller;
> +			#gpio-cells = <1>;
> +			compatible = "st,stixxxx-gpio";
> +			reg = <0xfe610000 0x100>;
> +			st,bank-name  = "PIO0";
> +			st,alt-control = <&SYSCONF_SBC(0) 0 31>;
> +			st,oe-control = <&SYSCONF_SBC(5)  0 7>;
> +			st,pu-control = <&SYSCONF_SBC(7)  0 7>;
> +			st,od-control = <&SYSCONF_SBC(9)  0 7>;
> +			st,retime-style = "packed";
> +			st,retime-pin-mask = <0xff>;
> +			st,retime-control0 = <&SYSCONF_SBC(16) 0 31>;
> +			st,retime-control1 = <&SYSCONF_SBC(17) 0 31>;
> +		};
> +		...
> +		pin-functions nodes follow...
> +	};
> +
> +
> +Contents of function subnode node:
> +----------------------
> +Required properties for pin configuration node:
> +- st,function	: Should be alternate function number associated
> +		with this set of pins.
> +		possible altfunction values:
> +		ALT1
> +		ALT2
> +		ALT3
> +		ALT4
> +		ALT5
> +		ALT6
> +		ALT7
use number in the DoC


> +
> +- st,pins	: Child node with list of pins with configuration.
> +
> +Below is the format of how each pin conf should look like.
> +
> +<bank offset mode rt_type rt_delay rt_clk>
> +
> +Every PIO is represented with 4-7 parameters depending on retime configuration.
> +Each parameter is explained as below.
> +
> +-bank		: Should be bank phandle to which this PIO belongs.
> +-offset		: Offset in the PIO bank.
> +-mode		:pin configuration is selected from one of the below values.
> +		IN
> +		IN_PU
> +		OUT
> +		BIDIR
> +		BIDIR_PU
ditto
> +
> +-rt_type	Retiming Configuration for the pin.
> +		Possible retime configuration are:
> +
> +		-------		-------------
> +		value		args
> +		-------		-------------
> +		NICLK		<delay> <clk>
> +		ICLK_IO		<delay> <clk>
> +		BYPASS		<delay>
> +		DE_IO		<delay> <clk>
> +		SE_ICLK_IO	<delay> <clk>
> +		SE_NICLK_IO	<delay> <clk>
> +
> +- delay	is retime delay in pico seconds.
> +		Possible values are: refer to retime-in/out-delays
> +
> +- rt_clk	:clk to be use for retime.
> +		Possible values are:
> +		CLK_A
> +		CLK_B
> +		CLK_C
> +		CLK_D
> +
> +Example of mmcclk pin which is a bi-direction pull pu with retime config
> +as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
> +
> +pin-controller {
> +	...
> +	mmc0 {
> +		pinctrl_mmc: mmc {
> +			st,function = <ALT4>;
> +			st,pins {
> +				mmcclk = <&PIO13 4 BIDIR_PU NICLK  0  CLK_B>;
> +				...
> +			};
> +		};
> +	...
> +	};
> +};
> +
> +sdhci0:sdhci at fe810000{
> +	...
> +	pinctrl-names = "default";
> +	pinctrl-0	= <&pinctrl_mmc>;
> +};
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 34f51d2..611a399 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -179,6 +179,19 @@ config PINCTRL_SUNXI
>  	select PINMUX
>  	select GENERIC_PINCONF
>  
> +config PINCTRL_STIXXXX
> +	bool "ST Microelectronics pin controller driver for STixxxx SoCs"
> +	depends on PLAT_STIXXXX
> +	select PINMUX
> +	select PINCONF
> +	select MFD_SYSCON
> +	help
> +	  Say yes here to support pinctrl interface on STixxxx SOCs.
> +	  This driver is used to control both PIO block and PIO-mux
> +	  block to configure a pin.
> +
> +	  If unsure, say N.
> +
>  config PINCTRL_TEGRA
>  	bool
>  	select PINMUX
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index f82cc5b..99a2c78 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS)	+= pinctrl-exynos.o
>  obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
>  obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
>  obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
> +obj-$(CONFIG_PINCTRL_STIXXXX) 	+= pinctrl-stixxxx.o
>  
>  obj-$(CONFIG_PLAT_ORION)        += mvebu/
>  obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
> diff --git a/drivers/pinctrl/pinctrl-stixxxx.c b/drivers/pinctrl/pinctrl-stixxxx.c
> new file mode 100644
> index 0000000..7d2c59c
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-stixxxx.c
> @@ -0,0 +1,1151 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
> + * Authors:
> + *	Srinivas Kandagatla <srinivas.kandagatla at st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/platform_device.h>
> +#include "core.h"
> +#include "pinctrl-stixxxx.h"
> +
> +struct stixxxx_pinconf {
> +	int		pin;
> +	const char	*name;
> +	unsigned long	config;
> +};
> +
> +struct stixxxx_pmx_func {
> +	const char	*name;
> +	const char	**groups;
> +	unsigned	ngroups;
> +};
> +
> +struct stixxxx_pctl_group {
> +	const char		*name;
> +	unsigned int		*pins;
> +	unsigned		npins;
> +	int			altfunc;
> +	struct stixxxx_pinconf	*pin_conf;
> +};
> +
> +#define to_stixxxx_gpio_port(chip) \
> +		container_of(chip, struct stixxxx_gpio_port, gpio_chip)
> +
> +struct stixxxx_gpio_port {
> +	struct gpio_chip	gpio_chip;
> +	struct pinctrl_gpio_range range;
> +	void __iomem		*base;
> +	struct device_node	*of_node;
> +	const char		*bank_name;
> +};
> +
> +static struct stixxxx_gpio_port *gpio_ports[STIXXXX_MAX_GPIO_BANKS];
> +
> +struct stixxxx_pinctrl {
> +	struct device			*dev;
> +	struct pinctrl_dev		*pctl;
> +	int				nbanks;
> +	struct stixxxx_pmx_func		*functions;
> +	int				nfunctions;
> +	struct stixxxx_pctl_group	*groups;
> +	int				ngroups;
> +	struct stixxxx_pio_control	*pio_controls;
> +};
> +
> +/* Low level functions.. */
> +static void stixxxx_pinconf_set_direction(struct stixxxx_pio_control *pc,
> +				int pin_id, unsigned long config)
> +{
> +	struct syscon_field *output_enable;
> +	struct syscon_field *pull_up;
> +	struct syscon_field *open_drain;
> +	unsigned long oe_value, pu_value, od_value;
> +	unsigned long mask;
> +	int pin = stixxxx_gpio_pin(pin_id);
> +
> +	output_enable = pc->oe;
> +	pull_up = pc->pu;
> +	open_drain = pc->od;
> +
> +	mask = BIT(pin);
> +
> +	oe_value = syscon_read(output_enable);
> +	pu_value = syscon_read(pull_up);
> +	od_value = syscon_read(open_drain);
> +
> +	/* Clear old values */
> +	oe_value &= ~mask;
> +	pu_value &= ~mask;
> +	od_value &= ~mask;
> +
> +	if (config & STIXXXX_PINCONF_OE)
> +		oe_value |= mask;
> +	if (config & STIXXXX_PINCONF_PU)
> +		pu_value |= mask;
> +	if (config & STIXXXX_PINCONF_OD)
> +		od_value |= mask;
> +
> +	syscon_write(output_enable, oe_value);
> +	syscon_write(pull_up, pu_value);
> +	syscon_write(open_drain, od_value);
> +}
> +
> +static void stixxxx_pctl_set_function(struct stixxxx_pio_control *pc,
> +				int pin_id, int function)
> +{
> +	struct syscon_field *selector;
> +	int offset;
> +	unsigned long val;
> +	int pin = stixxxx_gpio_pin(pin_id);
> +
> +	selector = pc->alt;
> +	offset = pin * 4;
> +	val = syscon_read(selector);
> +	val &= ~(0xf << offset);
> +	val |= function << offset;
> +	syscon_write(selector, val);
> +}
> +
> +static unsigned long stixxxx_pinconf_delay_to_bit(unsigned int delay,
> +		const struct stixxxx_retime_params *rt_params,
> +		unsigned long config)
> +{
> +	unsigned int *delay_times;
> +	int num_delay_times, i, closest_index = -1;
> +	unsigned int closest_divergence = UINT_MAX;
> +
> +	if (STIXXXX_PINCONF_UNPACK_OE(config)) {
> +		delay_times = rt_params->delay_times_out;
> +		num_delay_times = rt_params->num_delay_times_out;
> +	} else {
> +		delay_times = rt_params->delay_times_in;
> +		num_delay_times = rt_params->num_delay_times_in;
> +	}
> +
> +	for (i = 0; i < num_delay_times; i++) {
> +		unsigned int divergence = abs(delay - delay_times[i]);
> +
> +		if (divergence == 0)
> +			return i;
> +
> +		if (divergence < closest_divergence) {
> +			closest_divergence = divergence;
> +			closest_index = i;
> +		}
> +	}
> +
> +	pr_warn("Attempt to set delay %d, closest available %d\n",
> +	     delay, delay_times[closest_index]);
> +
> +	return closest_index;
> +}
> +
> +static unsigned long stixxxx_pinconf_bit_to_delay(unsigned int index,
> +		const struct stixxxx_retime_params *rt_params,
> +		unsigned long output)
> +{
> +	unsigned int *delay_times;
> +	int num_delay_times;
> +
> +	if (output) {
> +		delay_times = rt_params->delay_times_out;
> +		num_delay_times = rt_params->num_delay_times_out;
> +	} else {
> +		delay_times = rt_params->delay_times_in;
> +		num_delay_times = rt_params->num_delay_times_in;
> +	}
> +
> +	if (index < num_delay_times) {
> +		return delay_times[index];
> +	} else {
> +		pr_warn("Delay not found in/out delay list\n");
> +		return 0;
> +	}
> +}
> +
> +static void stixxxx_pinconf_set_retime_packed(
> +		struct stixxxx_pio_control *pc,
> +		unsigned long config, int pin)
> +{
> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
> +	const struct stixxxx_retime_offset *offset = rt_params->retime_offset;
> +	struct syscon_field **regs;
> +	unsigned long values[2];
> +	unsigned long mask;
> +	int i, j;
> +	int clk = STIXXXX_PINCONF_UNPACK_RT_CLK(config);
> +	int clknotdata = STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config);
> +	int double_edge = STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
> +	int invertclk = STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config);
> +	int retime = STIXXXX_PINCONF_UNPACK_RT(config);
> +	unsigned long delay = stixxxx_pinconf_delay_to_bit(
> +			STIXXXX_PINCONF_UNPACK_RT_DELAY(config),
> +			pc->rt_params, config);
> +
> +	unsigned long rt_cfg =
> +		((clk		& 1) << offset->clk1notclk0_offset) |
> +		((clknotdata	& 1) << offset->clknotdata_offset) |
> +		((delay		& 1) << offset->delay_lsb_offset) |
> +		(((delay >> 1)  & 1) << offset->delay_msb_offset) |
> +		((double_edge	& 1) << offset->double_edge_offset) |
> +		((invertclk	& 1) << offset->invertclk_offset) |
> +		((retime	& 1) << offset->retime_offset);
> +
> +	regs = pc->retiming;
> +	values[0] = syscon_read(regs[0]);
> +	values[1] = syscon_read(regs[1]);
> +
> +	for (i = 0; i < 2; i++) {
> +		mask = BIT(pin);
> +		for (j = 0; j < 4; j++) {
> +			if (rt_cfg & 1)
> +				values[i] |= mask;
> +			else
> +				values[i] &= ~mask;
> +			mask <<= 8;
> +			rt_cfg >>= 1;
> +		}
> +	}
> +
> +	syscon_write(regs[0], values[0]);
> +	syscon_write(regs[1], values[1]);
> +}
> +
> +static void stixxxx_pinconf_set_retime_dedicated(
> +	struct stixxxx_pio_control *pc,
> +	unsigned long config, int pin)
> +{
> +	struct syscon_field *reg;
> +	int input = STIXXXX_PINCONF_UNPACK_OE(config) ? 0 : 1;
> +	int clk = STIXXXX_PINCONF_UNPACK_RT_CLK(config);
> +	int clknotdata = STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config);
> +	int double_edge = STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
> +	int invertclk = STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config);
> +	int retime = STIXXXX_PINCONF_UNPACK_RT(config);
> +	unsigned long delay = stixxxx_pinconf_delay_to_bit(
> +			STIXXXX_PINCONF_UNPACK_RT_DELAY(config),
> +			pc->rt_params, config);
> +
> +	unsigned long retime_config =
> +		((clk		& 0x3) << 0) |
> +		((clknotdata	& 0x1) << 2) |
> +		((delay		& 0xf) << 3) |
> +		((input		& 0x1) << 7) |
> +		((double_edge	& 0x1) << 8) |
> +		((invertclk	& 0x1) << 9) |
> +		((retime	& 0x1) << 10);
> +
> +	reg = pc->retiming[pin];
> +	syscon_write(reg, retime_config);
> +}
> +
> +static void stixxxx_pinconf_get_direction(struct stixxxx_pio_control *pc,
> +	int pin_id, unsigned long *config)
> +{
> +	unsigned long oe_value, pu_value, od_value;
> +	int pin = stixxxx_gpio_pin(pin_id);
> +
> +	oe_value = (syscon_read(pc->oe) >> pin) & 1;
> +	pu_value = (syscon_read(pc->pu) >> pin) & 1;
> +	od_value = (syscon_read(pc->od) >> pin) & 1;
> +
> +	STIXXXX_PINCONF_PACK_OE(*config, oe_value);
> +	STIXXXX_PINCONF_PACK_PU(*config, pu_value);
> +	STIXXXX_PINCONF_PACK_OD(*config, od_value);
> +}
> +
> +static int stixxxx_pinconf_get_retime_packed(
> +		struct stixxxx_pio_control *pc,
> +		int pin, unsigned long *config)
> +{
> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
> +	const struct stixxxx_retime_offset *offset = rt_params->retime_offset;
> +	unsigned long delay_bits, delay, rt_reduced;
> +	unsigned long rt_value[2];
> +	int i, j;
> +	int output = STIXXXX_PINCONF_UNPACK_OE(*config);
> +
> +	rt_value[0] = syscon_read(pc->retiming[0]);
> +	rt_value[1] = syscon_read(pc->retiming[1]);
> +
> +	rt_reduced = 0;
> +	for (i = 0; i < 2; i++) {
> +		for (j = 0; j < 4; j++) {
> +			if (rt_value[i] & (1<<((8*j)+pin)))
> +				rt_reduced |= 1 << ((i*4)+j);
> +		}
> +	}
> +
> +	STIXXXX_PINCONF_PACK_RT(*config,
> +			(rt_reduced >> offset->retime_offset) & 1);
> +	STIXXXX_PINCONF_PACK_RT_CLK(*config,
> +			(rt_reduced >> offset->clk1notclk0_offset) & 1);
> +	STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(*config,
> +			(rt_reduced >> offset->clknotdata_offset) & 1);
> +	STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(*config,
> +			(rt_reduced >> offset->double_edge_offset) & 1);
> +	STIXXXX_PINCONF_PACK_RT_INVERTCLK(*config,
> +			(rt_reduced >> offset->invertclk_offset) & 1);
> +
> +	delay_bits =  (((rt_reduced >> offset->delay_msb_offset) & 1)<<1) |
> +			((rt_reduced >> offset->delay_lsb_offset) & 1);
> +	delay =  stixxxx_pinconf_bit_to_delay(delay_bits, rt_params, output);
> +	STIXXXX_PINCONF_PACK_RT_DELAY(*config, delay);
> +	return 0;
> +}
> +
> +static int stixxxx_pinconf_get_retime_dedicated(
> +		struct stixxxx_pio_control *pc,
> +		int pin, unsigned long *config)
> +{
> +	unsigned long value;
> +	unsigned long delay_bits, delay;
> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
> +	int output = STIXXXX_PINCONF_UNPACK_OE(*config);
> +
> +	value = syscon_read(pc->retiming[pin]);
> +	STIXXXX_PINCONF_PACK_RT_CLK(*config, ((value >> 0) & 0x3));
> +	STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(*config, ((value >> 2) & 0x1));
> +	delay_bits = ((value >> 3) & 0xf);
> +	delay =  stixxxx_pinconf_bit_to_delay(delay_bits, rt_params, output);
> +	STIXXXX_PINCONF_PACK_RT_DELAY(*config, delay);
> +	STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(*config, ((value >> 8) & 0x1));
> +	STIXXXX_PINCONF_PACK_RT_INVERTCLK(*config, ((value >> 9) & 0x1));
> +	STIXXXX_PINCONF_PACK_RT(*config, ((value >> 10) & 0x1));
> +
> +	return 0;
> +}
> +
> +/* GPIO related functions */
> +
> +static inline void __stixxxx_gpio_set(struct stixxxx_gpio_port *port,
> +	unsigned offset, int value)
> +{
> +	if (value)
> +		writel(BIT(offset), port->base + REG_PIO_SET_POUT);
> +	else
> +		writel(BIT(offset), port->base + REG_PIO_CLR_POUT);
> +}
> +
> +static void stixxxx_gpio_direction(unsigned int gpio, unsigned int direction)
> +{
> +	int port_num = stixxxx_gpio_port(gpio);
> +	int offset = stixxxx_gpio_pin(gpio);
> +	struct stixxxx_gpio_port *port  = gpio_ports[port_num];
> +	int i = 0;
> +
> +	for (i = 0; i <= 2; i++) {
> +		if (direction & BIT(i))
> +			writel(BIT(offset), port->base + REG_PIO_SET_PC(i));
> +		else
> +			writel(BIT(offset), port->base + REG_PIO_CLR_PC(i));
> +	}
> +}
> +
> +static int stixxxx_gpio_request(struct gpio_chip *chip, unsigned offset)
> +{
> +	return pinctrl_request_gpio(chip->base + offset);
> +}
> +
> +static void stixxxx_gpio_free(struct gpio_chip *chip, unsigned offset)
> +{
> +	pinctrl_free_gpio(chip->base + offset);
> +}
> +
> +static int stixxxx_gpio_get(struct gpio_chip *chip, unsigned offset)
> +{
> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
> +
> +	return (readl(port->base + REG_PIO_PIN) >> offset) & 1;
> +}
> +
> +static void stixxxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
> +{
> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
> +	__stixxxx_gpio_set(port, offset, value);
> +}
> +
> +static int stixxxx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
> +{
> +	pinctrl_gpio_direction_input(chip->base + offset);
> +	return 0;
> +}
> +
> +static int stixxxx_gpio_direction_output(struct gpio_chip *chip,
> +	unsigned offset, int value)
> +{
> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
> +
> +	__stixxxx_gpio_set(port, offset, value);
> +	pinctrl_gpio_direction_output(chip->base + offset);
> +
> +	return 0;
> +}
> +
> +static int stixxxx_gpio_xlate(struct gpio_chip *gc,
> +			const struct of_phandle_args *gpiospec, u32 *flags)
> +{
> +	if (WARN_ON(gc->of_gpio_n_cells < 1))
> +		return -EINVAL;
> +
> +	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
> +		return -EINVAL;
> +
> +	if (gpiospec->args[0] > gc->ngpio)
> +		return -EINVAL;
> +
> +	return gpiospec->args[0];
> +}
> +
> +/* Pinctrl Groups */
> +static int stixxxx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +	return info->ngroups;
> +}
> +
> +static const char *stixxxx_pctl_get_group_name(struct pinctrl_dev *pctldev,
> +				       unsigned selector)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +	return info->groups[selector].name;
> +}
> +
> +static int stixxxx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
> +	unsigned selector, const unsigned **pins, unsigned *npins)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +	if (selector >= info->ngroups)
> +		return -EINVAL;
> +
> +	*pins = info->groups[selector].pins;
> +	*npins = info->groups[selector].npins;
> +
> +	return 0;
> +}
> +
> +static const inline struct stixxxx_pctl_group *stixxxx_pctl_find_group_by_name(
> +	const struct stixxxx_pinctrl *info, const char *name)
> +{
> +	int i;
> +
> +	for (i = 0; i < info->ngroups; i++) {
> +		if (!strcmp(info->groups[i].name, name))
> +			return &info->groups[i];
> +	}
> +
> +	return NULL;
> +}
> +
> +static int stixxxx_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
> +	struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	const struct stixxxx_pctl_group *grp;
> +	struct pinctrl_map *new_map;
> +	struct device_node *parent;
> +	int map_num, i;
> +
> +	grp = stixxxx_pctl_find_group_by_name(info, np->name);
> +	if (!grp) {
> +		dev_err(info->dev, "unable to find group for node %s\n",
> +			np->name);
> +		return -EINVAL;
> +	}
> +
> +	map_num = grp->npins + 1;
> +	new_map = devm_kzalloc(pctldev->dev,
> +				sizeof(*new_map) * map_num, GFP_KERNEL);
> +	if (!new_map)
> +		return -ENOMEM;
> +
> +	parent = of_get_parent(np);
> +	if (!parent) {
> +		devm_kfree(pctldev->dev, new_map);
> +		return -EINVAL;
> +	}
> +
> +	*map = new_map;
> +	*num_maps = map_num;
> +	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
> +	new_map[0].data.mux.function = parent->name;
> +	new_map[0].data.mux.group = np->name;
> +	of_node_put(parent);
> +
> +	/* create config map per pin */
> +	new_map++;
> +	for (i = 0; i < grp->npins; i++) {
> +		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
> +		new_map[i].data.configs.group_or_pin =
> +				pin_get_name(pctldev, grp->pins[i]);
> +		new_map[i].data.configs.configs = &grp->pin_conf[i].config;
> +		new_map[i].data.configs.num_configs = 1;
> +	}
> +	dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
> +		(*map)->data.mux.function, grp->name, map_num);
> +
> +	return 0;
> +}
> +
> +static void stixxxx_pctl_dt_free_map(struct pinctrl_dev *pctldev,
> +				struct pinctrl_map *map, unsigned num_maps)
> +{
> +}
> +
> +static struct pinctrl_ops stixxxx_pctlops = {
> +	.get_groups_count	= stixxxx_pctl_get_groups_count,
> +	.get_group_pins		= stixxxx_pctl_get_group_pins,
> +	.get_group_name		= stixxxx_pctl_get_group_name,
> +	.dt_node_to_map		= stixxxx_pctl_dt_node_to_map,
> +	.dt_free_map		= stixxxx_pctl_dt_free_map,
> +};
> +
> +/* Pinmux */
> +static int stixxxx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +	return info->nfunctions;
> +}
> +
> +const char *stixxxx_pmx_get_fname(struct pinctrl_dev *pctldev,
> +	unsigned selector)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +	return info->functions[selector].name;
> +}
> +
> +static int stixxxx_pmx_get_groups(struct pinctrl_dev *pctldev,
> +	unsigned selector, const char * const **grps, unsigned * const ngrps)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	*grps = info->functions[selector].groups;
> +	*ngrps = info->functions[selector].ngroups;
> +
> +	return 0;
> +}
> +
> +static struct stixxxx_pio_control *stixxxx_get_pio_control(
> +			struct stixxxx_pinctrl *info, int pin_id)
> +{
> +	int port = stixxxx_gpio_port(pin_id);
> +	return &info->pio_controls[port];
> +}
> +
> +static int stixxxx_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
> +		unsigned group)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	struct stixxxx_pinconf *conf = info->groups[group].pin_conf;
> +	struct stixxxx_pio_control *pc;
> +	int i;
> +
> +	for (i = 0; i < info->groups[group].npins; i++) {
> +		pc = stixxxx_get_pio_control(info, conf[i].pin);
> +		stixxxx_pctl_set_function(pc, conf[i].pin,
> +					info->groups[group].altfunc);
> +	}
> +
> +	return 0;
> +}
> +
> +static void stixxxx_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
> +		unsigned group)
> +{
> +}
> +
> +static int stixxxx_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
> +			struct pinctrl_gpio_range *range, unsigned gpio,
> +			bool input)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	struct stixxxx_pio_control *pc = &info->pio_controls[range->id];
> +	/*
> +	 * When a PIO port is used in its primary function mode (altfunc = 0)
> +	 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
> +	 * for the primary PIO functions are driven by the related PIO block
> +	 */
> +	stixxxx_pctl_set_function(pc, gpio, 0);
> +	stixxxx_gpio_direction(gpio, input ?
> +		STIXXXX_GPIO_DIRECTION_IN : STIXXXX_GPIO_DIRECTION_OUT);
> +
> +	return 0;
> +}
> +
> +static struct pinmux_ops stixxxx_pmxops = {
> +	.get_functions_count	= stixxxx_pmx_get_funcs_count,
> +	.get_function_name	= stixxxx_pmx_get_fname,
> +	.get_function_groups	= stixxxx_pmx_get_groups,
> +	.enable			= stixxxx_pmx_enable,
> +	.disable		= stixxxx_pmx_disable,
> +	.gpio_set_direction	= stixxxx_pmx_set_gpio_direction,
> +};
> +
> +/* Pinconf  */
> +static void stixxxx_pinconf_get_retime(struct stixxxx_pio_control *pc,
> +	int pin_id, unsigned long *config)
> +{
> +	int pin = stixxxx_gpio_pin(pin_id);
> +	if (pc->rt_style == stixxxx_retime_style_packed)
> +		stixxxx_pinconf_get_retime_packed(pc, pin, config);
> +	else if (pc->rt_style == stixxxx_retime_style_dedicated)
> +		if ((BIT(pin) & pc->rt_pin_mask))
> +			stixxxx_pinconf_get_retime_dedicated(pc, pin, config);
> +}
> +
> +static void stixxxx_pinconf_set_retime(struct stixxxx_pio_control *pc,
> +	int pin_id, unsigned long config)
> +{
> +	int pin = stixxxx_gpio_pin(pin_id);
> +
> +	if (pc->rt_style == stixxxx_retime_style_packed)
> +		stixxxx_pinconf_set_retime_packed(pc, config, pin);
> +	else if (pc->rt_style == stixxxx_retime_style_dedicated)
> +		if ((BIT(pin) & pc->rt_pin_mask))
> +			stixxxx_pinconf_set_retime_dedicated(pc, config, pin);
> +}
> +
> +static int stixxxx_pinconf_set(struct pinctrl_dev *pctldev,
> +			     unsigned pin_id, unsigned long config)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	struct stixxxx_pio_control *pc = stixxxx_get_pio_control(info, pin_id);
> +
> +	stixxxx_pinconf_set_direction(pc, pin_id, config);
> +	stixxxx_pinconf_set_retime(pc, pin_id, config);
> +	return 0;
> +}
> +
> +static int stixxxx_pinconf_get(struct pinctrl_dev *pctldev,
> +			     unsigned pin_id, unsigned long *config)
> +{
> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	struct stixxxx_pio_control *pc = stixxxx_get_pio_control(info, pin_id);
> +
> +	*config = 0;
> +	stixxxx_pinconf_get_direction(pc, pin_id, config);
> +	stixxxx_pinconf_get_retime(pc, pin_id, config);
> +
> +	return 0;
> +}
> +
> +static void stixxxx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> +				   struct seq_file *s, unsigned pin_id)
> +{
> +	unsigned long config;
> +	stixxxx_pinconf_get(pctldev, pin_id, &config);
> +
> +	seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n"
> +		"\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
> +		"de:%ld,rt-clk:%ld,rt-delay:%ld]",
> +		STIXXXX_PINCONF_UNPACK_OE(config),
> +		STIXXXX_PINCONF_UNPACK_PU(config),
> +		STIXXXX_PINCONF_UNPACK_OD(config),
> +		STIXXXX_PINCONF_UNPACK_RT(config),
> +		STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config),
> +		STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config),
> +		STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
> +		STIXXXX_PINCONF_UNPACK_RT_CLK(config),
> +		STIXXXX_PINCONF_UNPACK_RT_DELAY(config));
> +}
> +
> +static struct pinconf_ops stixxxx_confops = {
> +	.pin_config_get		= stixxxx_pinconf_get,
> +	.pin_config_set		= stixxxx_pinconf_set,
> +	.pin_config_dbg_show	= stixxxx_pinconf_dbg_show,
> +};
> +
> +/* pinctrl */
> +static struct pinctrl_desc stixxxx_pctl_desc = {
> +	.owner		= THIS_MODULE,
> +	.pctlops	= &stixxxx_pctlops,
> +	.pmxops		= &stixxxx_pmxops,
> +	.confops	= &stixxxx_confops,
> +};
> +
> +static int stixxxx_pinconf_dt_parse_rt_params(struct stixxxx_pinctrl *info,
> +	struct device_node *np,	struct stixxxx_retime_params *params)
> +{
> +	const __be32 *ip;
> +	struct device_node *offset_np;
> +	struct stixxxx_retime_offset *rt_offset;
> +	int delay_count = 0;
> +
> +	ip = of_get_property(np, "#retime-delay-cells", NULL);
> +	if (ip)
> +		delay_count = be32_to_cpup(ip);
> +	else
> +		pr_warn("No #retime-delay-cells specified\n");
> +
> +	params->num_delay_times_out = delay_count;
> +	params->num_delay_times_in = delay_count;
> +	params->delay_times_in = devm_kzalloc(info->dev,
> +				sizeof(u32) * delay_count, GFP_KERNEL);
> +	params->delay_times_out = devm_kzalloc(info->dev,
> +				sizeof(u32) * delay_count, GFP_KERNEL);
> +
> +	if (!params->delay_times_in || !params->delay_times_out)
> +		return -ENOMEM;
> +
> +	of_property_read_u32_array(np, "st,retime-in-delay",
> +				(u32 *)params->delay_times_in, delay_count);
> +	of_property_read_u32_array(np, "st,retime-out-delay",
> +				(u32 *)params->delay_times_out, delay_count);
> +
> +	offset_np = of_parse_phandle(np, "st,retime-offset", 0);
> +
> +	if (offset_np) {
> +		rt_offset = devm_kzalloc(info->dev,
> +				sizeof(*rt_offset), GFP_KERNEL);
> +		if (!rt_offset)
> +			return -ENOMEM;
> +
> +		params->retime_offset = rt_offset;
> +		WARN_ON(of_property_read_u32(offset_np, "retime",
> +					&rt_offset->retime_offset));
> +		WARN_ON(of_property_read_u32(offset_np, "clk1notclk0",
> +					&rt_offset->clk1notclk0_offset));
> +		WARN_ON(of_property_read_u32(offset_np, "clknotdata",
> +					&rt_offset->clknotdata_offset));
> +		WARN_ON(of_property_read_u32(offset_np, "double-edge",
> +					&rt_offset->double_edge_offset));
> +		WARN_ON(of_property_read_u32(offset_np, "invertclk",
> +					&rt_offset->invertclk_offset));
> +		WARN_ON(of_property_read_u32(offset_np, "delay-lsb",
> +					&rt_offset->delay_lsb_offset));
> +		WARN_ON(of_property_read_u32(offset_np, "delay-msb",
> +					&rt_offset->delay_msb_offset));
> +	}
> +
> +	return 0;
> +}
> +
> +static const char *gpio_compat = "st,stixxxx-gpio";
> +
> +static void stixxxx_pctl_dt_child_count(struct stixxxx_pinctrl *info,
> +				     struct device_node *np)
> +{
> +	struct device_node *child;
> +	for_each_child_of_node(np, child) {
> +		if (of_device_is_compatible(child, gpio_compat)) {
> +			info->nbanks++;
> +		} else {
> +			info->nfunctions++;
> +			info->ngroups += of_get_child_count(child);
> +		}
> +	}
> +}
> +
> +static int stixxxx_pctl_dt_get_retime_conf(struct device_node *np,
> +	struct stixxxx_pio_control *pc)
> +{
> +	const char *style;
> +	char name[20];
> +	unsigned int j;
> +	of_property_read_string(np, "st,retime-style", &style);
> +
> +	if (strcmp(style, "packed") == 0) {
> +		pc->rt_style = stixxxx_retime_style_packed;
> +		for (j = 0; j < 2; j++) {
> +			snprintf(name, sizeof(name), "st,retime-control%d", j);
> +			pc->retiming[j] = syscon_claim(np, name);
> +			if (!pc->retiming[j])
> +				return -ENODATA;
> +		}
> +	} else if (strcmp(style, "dedicated") == 0) {
> +		pc->rt_style = stixxxx_retime_style_dedicated;
> +		for (j = 0; j < 8; j++) {
> +			if ((1<<j) & pc->rt_pin_mask) {
> +				snprintf(name, sizeof(name),
> +						"st,retime-control%d", j);
> +				pc->retiming[j] = syscon_claim(np, name);
> +				if (!pc->retiming[j])
> +					return -ENODATA;
> +			}
> +		}
> +	} else if (strcmp(style, "none") == 0) {
> +		pc->rt_style = stixxxx_retime_style_none;
> +	}
> +
> +	return 0;
> +}
> +
> +static int stixxxx_pctl_dt_init(struct stixxxx_pinctrl *info,
> +			struct device_node *np)
> +{
> +	struct stixxxx_pio_control *pc;
> +	struct stixxxx_retime_params *rt_params;
> +	struct device *dev = info->dev;
> +	unsigned int i = 0;
> +	struct device_node *child = NULL;
> +
> +	pc = devm_kzalloc(dev, sizeof(*pc) * info->nbanks, GFP_KERNEL);
> +	rt_params = devm_kzalloc(dev, sizeof(*rt_params), GFP_KERNEL);
> +
> +	if (!pc || !rt_params)
> +		return -ENOMEM;
> +
> +	info->pio_controls = pc;
> +	if (stixxxx_pinconf_dt_parse_rt_params(info, np, rt_params))
> +		return -ENOMEM;
> +
> +	for_each_child_of_node(np, child) {
> +		if (of_device_is_compatible(child, gpio_compat)) {
> +			pc[i].rt_params = rt_params;
> +
> +			pc[i].alt = syscon_claim(child, "st,alt-control");
> +			if (!pc[i].alt)
> +				goto failed;
> +
> +			pc[i].oe = syscon_claim(child, "st,oe-control");
> +			if (!pc[i].oe)
> +				goto failed;
> +
> +			pc[i].pu = syscon_claim(child, "st,pu-control");
> +			if (!pc[i].pu)
> +				goto failed;
> +
> +			pc[i].od = syscon_claim(child, "st,od-control");
> +			if (!pc[i].od)
> +				goto failed;
> +
> +			of_property_read_u32(child, "st,retime-pin-mask",
> +							&pc[i].rt_pin_mask);
> +
> +			stixxxx_pctl_dt_get_retime_conf(child, &pc[i]);
> +			i++;
> +		}
> +	}
> +
> +	return 0;
> +failed:
> +	return -ENODATA;
> +}
> +
> +#define OF_GPIO_ARGS_MIN	(3)
> +/*
> + * Each pin is represented in of the below forms.
> + * <bank offset direction func rt_type rt_delay rt_clk>
> + */
> +static int stixxxx_pctl_dt_parse_groups(struct device_node *np,
> +	struct stixxxx_pctl_group *grp, struct stixxxx_pinctrl *info, int idx)
> +{
> +	/* bank pad direction val altfunction */
> +	const __be32 *list;
> +	struct property *pp;
> +	struct stixxxx_pinconf *conf;
> +	phandle phandle;
> +	struct device_node *pins;
> +	u32 pin;
> +	int i = 0, npins = 0, nr_props;
> +
> +	pins = of_get_child_by_name(np, "st,pins");
> +	if (!pins)
> +		return -ENODATA;
> +
> +	for_each_property_of_node(pins, pp) {
> +		/* Skip those we do not want to proceed */
> +		if (!strcmp(pp->name, "name"))
> +			continue;
> +
> +		if (pp  && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
> +			npins++;
> +		} else {
> +			pr_warn("Invalid st,pins in %s node\n", np->name);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	grp->npins = npins;
> +	grp->name = np->name;
> +	grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL);
> +	grp->pin_conf = devm_kzalloc(info->dev,
> +					npins * sizeof(*conf), GFP_KERNEL);
> +	of_property_read_u32(np, "st,function", &grp->altfunc);
> +
> +	if (!grp->pins || !grp->pin_conf)
> +		return -ENOMEM;
> +
> +	/* <bank offset direction func rt_type rt_delay rt_clk> */
> +	for_each_property_of_node(pins, pp) {
> +		if (!strcmp(pp->name, "name"))
> +			continue;
> +		nr_props = pp->length/sizeof(u32);
> +		list = pp->value;
> +		conf = &grp->pin_conf[i];
> +
> +		/* bank & offset */
> +		phandle = be32_to_cpup(list++);
> +		pin = be32_to_cpup(list++);
> +		conf->pin = of_get_named_gpio(pins, pp->name, 0);
> +		conf->name = pp->name;
> +		grp->pins[i] = conf->pin;
> +
> +		conf->config = 0;
> +		/* direction */
> +		conf->config |= be32_to_cpup(list++);
> +		/* rt_type rt_delay rt_clk */
> +		if (nr_props >= OF_GPIO_ARGS_MIN + 2) {
> +			/* rt_type */
> +			conf->config |= be32_to_cpup(list++);
> +			/* rt_delay */
> +			conf->config |= be32_to_cpup(list++);
> +			/* rt_clk */
> +			if (nr_props > OF_GPIO_ARGS_MIN + 2)
> +				conf->config |= be32_to_cpup(list++);
> +		}
> +		i++;
> +	}
> +	of_node_put(pins);
> +
> +	return 0;
> +}
> +
> +static int stixxxx_pctl_parse_functions(struct device_node *np,
> +			struct stixxxx_pinctrl *info, u32 index, int *grp_index)
> +{
> +	struct device_node *child;
> +	struct stixxxx_pmx_func *func;
> +	struct stixxxx_pctl_group *grp;
> +	int ret, i;
> +
> +	func = &info->functions[index];
> +	func->name = np->name;
> +	func->ngroups = of_get_child_count(np);
> +	if (func->ngroups <= 0) {
> +		dev_err(info->dev, "No groups defined\n");
> +		return -EINVAL;
> +	}
> +	func->groups = devm_kzalloc(info->dev,
> +			func->ngroups * sizeof(char *), GFP_KERNEL);
> +	if (!func->groups)
> +		return -ENOMEM;
> +
> +	i = 0;
> +	for_each_child_of_node(np, child) {
> +		func->groups[i] = child->name;
> +		grp = &info->groups[*grp_index];
> +		*grp_index += 1;
> +		ret = stixxxx_pctl_dt_parse_groups(child, grp, info, i++);
> +		if (ret)
> +			return ret;
> +	}
> +	dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
> +				index, func->name, func->ngroups);
> +
> +	return 0;
> +}
> +
> +static int stixxxx_pctl_probe_dt(struct platform_device *pdev,
> +				 struct stixxxx_pinctrl *info)
> +{
> +	int ret = 0;
> +	int i = 0, j = 0, k = 0;
> +	struct pinctrl_pin_desc *pdesc;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct device_node *child;
> +	int grp_index = 0;
> +
> +	stixxxx_pctl_dt_child_count(info, np);
> +	if (info->nbanks < 1) {
> +		dev_err(&pdev->dev, "you need atleast one gpio bank\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = stixxxx_pctl_dt_init(info, np);
> +	if (ret)
> +		return ret;
> +
> +	dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
> +	dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
> +	dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
> +	info->functions = devm_kzalloc(&pdev->dev,
> +		info->nfunctions * sizeof(*info->functions), GFP_KERNEL);
> +
> +	info->groups = devm_kzalloc(&pdev->dev,
> +		info->ngroups * sizeof(*info->groups) ,	GFP_KERNEL);
> +
> +	if (!info->functions || !info->groups)
> +		return -ENOMEM;
> +
> +	stixxxx_pctl_desc.npins = info->nbanks * STIXXXX_GPIO_PINS_PER_PORT;
> +	pdesc =	devm_kzalloc(&pdev->dev,
> +			sizeof(*pdesc) * stixxxx_pctl_desc.npins, GFP_KERNEL);
> +	if (!pdesc)
> +		return -ENOMEM;
> +
> +	stixxxx_pctl_desc.pins = pdesc;
> +
> +	for_each_child_of_node(np, child) {
> +		if (of_device_is_compatible(child, gpio_compat)) {
> +			for (j = 0; j < STIXXXX_GPIO_PINS_PER_PORT; j++, k++) {
> +				const char *port_name = NULL;
> +				pdesc->number = k;
> +				of_property_read_string(child, "st,bank-name",
> +							&port_name);
> +				pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
> +							port_name ? : "PIO",
> +							port_name ? j : k);
> +				pdesc++;
> +			}
> +		} else {
> +			ret = stixxxx_pctl_parse_functions(child, info,
> +							i++, &grp_index);
> +			if (ret) {
> +				dev_err(&pdev->dev, "No functions found.\n");
> +				return ret;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int stixxxx_pctl_probe(struct platform_device *pdev)
> +{
> +	struct stixxxx_pinctrl *info;
> +	int ret, i;
> +
> +	if (!pdev->dev.of_node) {
> +		dev_err(&pdev->dev, "device node not found.\n");
> +		return -EINVAL;
> +	}
> +
> +	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
> +	if (!info)
> +		return -ENOMEM;
> +
> +	info->dev = &pdev->dev;
> +	platform_set_drvdata(pdev, info);
> +	ret = stixxxx_pctl_probe_dt(pdev, info);
> +	if (ret)
> +		return ret;
> +
> +	stixxxx_pctl_desc.name = dev_name(&pdev->dev);
> +	info->pctl = pinctrl_register(&stixxxx_pctl_desc, &pdev->dev, info);
> +	if (IS_ERR(info->pctl)) {
> +		dev_err(&pdev->dev, "Failed pinctrl registration\n");
> +		return PTR_ERR(info->pctl);
> +	}
> +
> +	for (i = 0; i < info->nbanks; i++)
> +		pinctrl_add_gpio_range(info->pctl, &gpio_ports[i]->range);
> +
> +	return 0;
> +}
> +
> +static struct gpio_chip stixxxx_gpio_template = {
> +	.request		= stixxxx_gpio_request,
> +	.free			= stixxxx_gpio_free,
> +	.get			= stixxxx_gpio_get,
> +	.set			= stixxxx_gpio_set,
> +	.direction_input	= stixxxx_gpio_direction_input,
> +	.direction_output	= stixxxx_gpio_direction_output,
> +	.ngpio			= STIXXXX_GPIO_PINS_PER_PORT,
> +	.of_gpio_n_cells	= 1,
> +	.of_xlate		= stixxxx_gpio_xlate,
> +};
> +
> +static int stixxxx_gpio_probe(struct platform_device *pdev)
> +{
> +	struct stixxxx_gpio_port *port;
> +	struct pinctrl_gpio_range *range;
> +	struct device_node *np  = pdev->dev.of_node;
> +	int port_num = of_alias_get_id(np, "gpio");
> +	struct resource *res;
> +	int err;
> +
> +	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
> +	if (!port)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	port->base = devm_request_and_ioremap(&pdev->dev, res);
> +	if (!port->base) {
> +		dev_err(&pdev->dev, "Can't get IO memory mapping!\n");
> +		return -ENODEV;
> +	}
> +
> +	of_property_read_string(np, "st,bank-name", &port->bank_name);
> +	port->of_node = np;
> +
> +	port->gpio_chip = stixxxx_gpio_template;
> +	port->gpio_chip.base = port_num * STIXXXX_GPIO_PINS_PER_PORT;
> +	port->gpio_chip.ngpio = STIXXXX_GPIO_PINS_PER_PORT;
> +	port->gpio_chip.of_node = np;
> +	port->gpio_chip.label = dev_name(&pdev->dev);
> +
> +	dev_set_drvdata(&pdev->dev, port);
> +	range = &port->range;
> +	range->name = port->gpio_chip.label;
> +	range->id = port_num;
> +	range->pin_base = range->base = range->id * STIXXXX_GPIO_PINS_PER_PORT;
> +	range->npins = port->gpio_chip.ngpio;
> +	range->gc = &port->gpio_chip;
> +	gpio_ports[port_num] = port;
> +	err  = gpiochip_add(&port->gpio_chip);
> +	if (err) {
> +		dev_err(&pdev->dev, "Failed to add gpiochip(%d)!\n", port_num);
> +		return err;
> +	}
> +	dev_info(&pdev->dev, "gpioport[%s] Added as bank%d\n",
> +				port->bank_name, port_num);
> +	return 0;
> +}
> +
> +static struct of_device_id stixxxx_gpio_of_match[] = {
> +	{ .compatible = "st,stixxxx-gpio", },
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver stixxxx_gpio_driver = {
> +	.driver = {
> +		.name = "st-gpio",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_match_ptr(stixxxx_gpio_of_match),
> +	},
> +	.probe = stixxxx_gpio_probe,
> +};
> +
> +static struct of_device_id stixxxx_pctl_of_match[] = {
> +	{ .compatible = "st,stixxxx-pinctrl",},
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver stixxxx_pctl_driver = {
> +	.driver = {
> +		.name = "st-pinctrl",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_match_ptr(stixxxx_pctl_of_match),
> +	},
> +	.probe = stixxxx_pctl_probe,
> +};
> +
> +static int __init stixxxx_pctl_init(void)
> +{
> +	int ret = platform_driver_register(&stixxxx_gpio_driver);
> +	if (ret)
> +		return ret;
> +	return platform_driver_register(&stixxxx_pctl_driver);
> +}
> +arch_initcall(stixxxx_pctl_init);
> diff --git a/drivers/pinctrl/pinctrl-stixxxx.h b/drivers/pinctrl/pinctrl-stixxxx.h
> new file mode 100644
> index 0000000..a340964
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-stixxxx.h
> @@ -0,0 +1,197 @@
> +
> +/*
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
> + * Authors:
> + *	Srinivas Kandagatla <srinivas.kandagatla at st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __LINUX_DRIVERS_PINCTRL_STIXXXX_H
> +#define __LINUX_DRIVERS_PINCTRL_STIXXXX_H
> +
> +enum stixxxx_retime_style {
> +	stixxxx_retime_style_none,
> +	stixxxx_retime_style_packed,
> +	stixxxx_retime_style_dedicated,
> +};
> +
> +/* Byte positions in 2 syscon words, starts from 0 */
> +struct stixxxx_retime_offset {
> +	int retime_offset;
> +	int clk1notclk0_offset;
> +	int clknotdata_offset;
> +	int double_edge_offset;
> +	int invertclk_offset;
> +	int delay_lsb_offset;
> +	int delay_msb_offset;
> +};
> +
> +struct stixxxx_retime_params {
> +	const struct stixxxx_retime_offset *retime_offset;
> +	unsigned int *delay_times_in;
> +	int num_delay_times_in;
> +	unsigned int *delay_times_out;
> +	int num_delay_times_out;
> +};
> +
> +struct stixxxx_pio_control {
> +	enum stixxxx_retime_style rt_style;
> +	u32 rt_pin_mask;
> +	const struct stixxxx_retime_params *rt_params;
> +	struct syscon_field *alt;
> +	struct syscon_field *oe, *pu, *od;
> +	struct syscon_field *retiming[8];
> +};
> +
> +/* PIO Block registers */
> +/* PIO output */
> +#define REG_PIO_POUT			0x00
> +/* Set bits of POUT */
> +#define REG_PIO_SET_POUT		0x04
> +/* Clear bits of POUT */
> +#define REG_PIO_CLR_POUT		0x08
> +/* PIO input */
> +#define REG_PIO_PIN			0x10
> +/* PIO configuration */
> +#define REG_PIO_PC(n)			(0x20 + (n) * 0x10)
> +/* Set bits of PC[2:0] */
> +#define REG_PIO_SET_PC(n)		(0x24 + (n) * 0x10)
> +/* Clear bits of PC[2:0] */
> +#define REG_PIO_CLR_PC(n)		(0x28 + (n) * 0x10)
> +/* PIO input comparison */
> +#define REG_PIO_PCOMP			0x50
> +/* Set bits of PCOMP */
> +#define REG_PIO_SET_PCOMP		0x54
> +/* Clear bits of PCOMP */
> +#define REG_PIO_CLR_PCOMP		0x58
> +/* PIO input comparison mask */
> +#define REG_PIO_PMASK			0x60
> +/* Set bits of PMASK */
> +#define REG_PIO_SET_PMASK		0x64
> +/* Clear bits of PMASK */
> +#define REG_PIO_CLR_PMASK		0x68
> +
> +#define STIXXXX_MAX_GPIO_BANKS		32
> +
> +#define STIXXXX_GPIO_DIRECTION_BIDIR	0x1
> +#define STIXXXX_GPIO_DIRECTION_OUT	0x2
> +#define STIXXXX_GPIO_DIRECTION_IN	0x4
> +
> +#define STIXXXX_GPIO_PINS_PER_PORT	8
> +#define stixxxx_gpio_port(gpio) ((gpio) / STIXXXX_GPIO_PINS_PER_PORT)
> +#define stixxxx_gpio_pin(gpio) ((gpio) % STIXXXX_GPIO_PINS_PER_PORT)
> +
> +/* pinconf */
> +/*
> + * Pinconf is represented in an opaque unsigned long variable.
> + * Below is the bit allocation details for each possible configuration.
> + * All the bit fields can be encapsulated into four variables
> + * (direction, retime-type, retime-clk, retime-delay)
> + *
> + *	 +----------------+
> + *[31:28]| reserved-3     |
> + *	 +----------------+-------------
> + *[27]   |	oe	  |		|
> + *	 +----------------+		v
> + *[26]   |	pu	  |	[Direction	]
> + *	 +----------------+		^
> + *[25]   |	od	  |		|
> + *	 +----------------+-------------
> + *[24]   | reserved-2     |
> + *	 +----------------+-------------
> + *[23]   |    retime      |		|
> + *	 +----------------+		|
> + *[22]   | retime-invclk  |		|
> + *	 +----------------+		v
> + *[21]   |retime-clknotdat|	[Retime-type	]
> + *	 +----------------+		^
> + *[20]   | retime-de      |		|
> + *	 +----------------+-------------
> + *[19:18]| retime-clk     |------>[Retime-Clk	]
> + *	 +----------------+
> + *[17:16]|  reserved-1    |
> + *	 +----------------+
> + *[15..0]| retime-delay   |------>[Retime Delay]
> + *	 +----------------+
> + */
> +
> +#define STIXXXX_PINCONF_UNPACK(conf, param)\
> +				((conf >> STIXXXX_PINCONF_ ##param ##_SHIFT) \
> +				& STIXXXX_PINCONF_ ##param ##_MASK)
> +
> +#define STIXXXX_PINCONF_PACK(conf, val, param)	(conf |=\
> +				((val & STIXXXX_PINCONF_ ##param ##_MASK) << \
> +					STIXXXX_PINCONF_ ##param ##_SHIFT))
> +
> +/* Output enable */
> +#define STIXXXX_PINCONF_OE_MASK		0x1
> +#define STIXXXX_PINCONF_OE_SHIFT	27
> +#define STIXXXX_PINCONF_OE		BIT(27)
> +#define STIXXXX_PINCONF_UNPACK_OE(conf)	STIXXXX_PINCONF_UNPACK(conf, OE)
> +#define STIXXXX_PINCONF_PACK_OE(conf, val)  STIXXXX_PINCONF_PACK(conf, val, OE)
> +
> +/* Pull Up */
> +#define STIXXXX_PINCONF_PU_MASK		0x1
> +#define STIXXXX_PINCONF_PU_SHIFT	26
> +#define STIXXXX_PINCONF_PU		BIT(26)
> +#define STIXXXX_PINCONF_UNPACK_PU(conf)	STIXXXX_PINCONF_UNPACK(conf, PU)
> +#define STIXXXX_PINCONF_PACK_PU(conf, val) STIXXXX_PINCONF_PACK(conf, val, PU)
> +
> +/* Open Drain */
> +#define STIXXXX_PINCONF_OD_MASK		0x1
> +#define STIXXXX_PINCONF_OD_SHIFT	25
> +#define STIXXXX_PINCONF_OD		BIT(25)
> +#define STIXXXX_PINCONF_UNPACK_OD(conf)	STIXXXX_PINCONF_UNPACK(conf, OD)
> +#define STIXXXX_PINCONF_PACK_OD(conf, val) STIXXXX_PINCONF_PACK(conf, val, OD)
> +
> +#define STIXXXX_PINCONF_RT_MASK		0x1
> +#define STIXXXX_PINCONF_RT_SHIFT	23
> +#define STIXXXX_PINCONF_RT		BIT(23)
> +#define STIXXXX_PINCONF_UNPACK_RT(conf)	STIXXXX_PINCONF_UNPACK(conf, RT)
> +#define STIXXXX_PINCONF_PACK_RT(conf, val) STIXXXX_PINCONF_PACK(conf, val, RT)
> +
> +#define STIXXXX_PINCONF_RT_INVERTCLK_MASK	0x1
> +#define STIXXXX_PINCONF_RT_INVERTCLK_SHIFT	22
> +#define STIXXXX_PINCONF_RT_INVERTCLK		BIT(22)
> +#define STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(conf) \
> +			STIXXXX_PINCONF_UNPACK(conf, RT_INVERTCLK)
> +#define STIXXXX_PINCONF_PACK_RT_INVERTCLK(conf, val) \
> +			STIXXXX_PINCONF_PACK(conf, val, RT_INVERTCLK)
> +
> +#define STIXXXX_PINCONF_RT_CLKNOTDATA_MASK	0x1
> +#define STIXXXX_PINCONF_RT_CLKNOTDATA_SHIFT	21
> +#define STIXXXX_PINCONF_RT_CLKNOTDATA		BIT(21)
> +#define STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(conf)	\
> +				STIXXXX_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
> +#define STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(conf, val) \
> +				STIXXXX_PINCONF_PACK(conf, val, RT_CLKNOTDATA)
> +
> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE_MASK	0x1
> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE_SHIFT	20
> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE		BIT(20)
> +#define STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
> +				STIXXXX_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
> +#define STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(conf, val) \
> +				STIXXXX_PINCONF_PACK(conf, val, RT_DOUBLE_EDGE)
> +
> +#define STIXXXX_PINCONF_RT_CLK_MASK		0x3
> +#define STIXXXX_PINCONF_RT_CLK_SHIFT		18
> +#define STIXXXX_PINCONF_RT_CLK			BIT(18)
> +#define STIXXXX_PINCONF_UNPACK_RT_CLK(conf)	\
> +			STIXXXX_PINCONF_UNPACK(conf, RT_CLK)
> +#define STIXXXX_PINCONF_PACK_RT_CLK(conf, val) \
> +			STIXXXX_PINCONF_PACK(conf, val, RT_CLK)
> +
> +/* RETIME_DELAY in Pico Secs */
> +#define STIXXXX_PINCONF_RT_DELAY_MASK		0xffff
> +#define STIXXXX_PINCONF_RT_DELAY_SHIFT		0
> +#define STIXXXX_PINCONF_UNPACK_RT_DELAY(conf) \
> +				STIXXXX_PINCONF_UNPACK(conf, RT_DELAY)
> +#define STIXXXX_PINCONF_PACK_RT_DELAY(conf, val) \
> +				STIXXXX_PINCONF_PACK(conf, val, RT_DELAY)
> +
> +#endif /* __LINUX_DRIVERS_PINCTRL_STIXXXX_H */
> -- 
> 1.7.6.5
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From sergei.shtylyov at cogentembedded.com  Wed May  8 11:15:17 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 08 May 2013 19:15:17 +0400
Subject: [PATCH] irqchip: Add irqchip_init dummy function
In-Reply-To: <1368019204-24448-1-git-send-email-hechtb+renesas@gmail.com>
References: <1368019204-24448-1-git-send-email-hechtb+renesas@gmail.com>
Message-ID: <518A6C05.9030303@cogentembedded.com>

Hello.

On 08-05-2013 17:20, Bastian Hecht wrote:

> We add an empty irqchip_init dummy function for cases in which
> CONFIG_IRQCHIP is not used. In these cases irqchip.c is not compiled,
> but a funtion call may still be present in architecture code, that in
> runtime doesn't get hit.

> E.g. this is needed in the arch/arm/mach-shmobile/intc-r8a7740.c
> interrupt setup code where OF use and non OF us is both handled in one
> file.

> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> ---
>   include/linux/irqchip.h |    4 ++++
>   1 file changed, 4 insertions(+)

> diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
> index e0006f1..78527ba 100644
> --- a/include/linux/irqchip.h
> +++ b/include/linux/irqchip.h
> @@ -11,6 +11,10 @@
>   #ifndef _LINUX_IRQCHIP_H
>   #define _LINUX_IRQCHIP_H
>
> +#ifdef CONFIG_IRQCHIP
>   void irqchip_init(void);
> +#else
> +void irqchip_init(void) {};

    Semicolon not needed here.

> +#endif

WBR, Sergei



From liuj97 at gmail.com  Wed May  8 11:17:00 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed,  8 May 2013 23:17:00 +0800
Subject: [PATCH v5,
 part3 01/15] mm: fix build warnings caused by free_reserved_area()
In-Reply-To: <1368026235-5976-1-git-send-email-jiang.liu@huawei.com>
References: <1368026235-5976-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368026235-5976-2-git-send-email-jiang.liu@huawei.com>

Fix following build warnings cuased by free_reserved_area():

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
  free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
  ^
In file included from include/linux/mman.h:4:0,
                 from arch/arm/mm/init.c:15:
include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
 extern unsigned long free_reserved_area(unsigned long start, unsigned long end,

   mm/page_alloc.c: In function 'free_reserved_area':
>> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
   In file included from arch/mips/include/asm/page.h:49:0,
                    from include/linux/mmzone.h:20,
                    from include/linux/gfp.h:4,
                    from include/linux/mm.h:8,
                    from mm/page_alloc.c:18:
   arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
   mm/page_alloc.c: In function 'free_area_init_nodes':
   mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Reported-by: Arnd Bergmann <arnd at arndb.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-mm at kvack.org
---
 arch/arm/mm/init.c |    6 ++++--
 mm/page_alloc.c    |    2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc0..7a82fcd 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -600,7 +600,8 @@ void __init mem_init(void)
 
 #ifdef CONFIG_SA1111
 	/* now that our DMA memory is actually so designated, we can free it */
-	free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
+	free_reserved_area((unsigned long)__va(PHYS_PFN_OFFSET),
+			   (unsigned long)swapper_pg_dir, 0, NULL);
 #endif
 
 	free_highpages();
@@ -728,7 +729,8 @@ void free_initmem(void)
 	extern char __tcm_start, __tcm_end;
 
 	poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
-	free_reserved_area(&__tcm_start, &__tcm_end, 0, "TCM link");
+	free_reserved_area((unsigned long)&__tcm_start,
+			   (unsigned long)&__tcm_end, 0, "TCM link");
 #endif
 
 	poison_init_mem(__init_begin, __init_end - __init_begin);
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 843e33d..ce259c8 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5196,7 +5196,7 @@ unsigned long free_reserved_area(unsigned long start, unsigned long end,
 	for (pages = 0; pos < end; pos += PAGE_SIZE, pages++) {
 		if (poison)
 			memset((void *)pos, poison, PAGE_SIZE);
-		free_reserved_page(virt_to_page(pos));
+		free_reserved_page(virt_to_page((void *)pos));
 	}
 
 	if (pages && s)
-- 
1.7.9.5



From liuj97 at gmail.com  Wed May  8 11:17:02 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed,  8 May 2013 23:17:02 +0800
Subject: [PATCH v5, part3 03/15] mm/ARM64: kill poison_init_mem()
In-Reply-To: <1368026235-5976-1-git-send-email-jiang.liu@huawei.com>
References: <1368026235-5976-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368026235-5976-4-git-send-email-jiang.liu@huawei.com>

Use free_reserved_area() to poison initmem memory pages and kill
poison_init_mem() on ARM64.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm64/mm/init.c |   17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index e58dd7f..b87bdb8 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -197,14 +197,6 @@ void __init bootmem_init(void)
 	max_pfn = max_low_pfn = max;
 }
 
-/*
- * Poison init memory with an undefined instruction (0x0).
- */
-static inline void poison_init_mem(void *s, size_t count)
-{
-	memset(s, 0, count);
-}
-
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
 static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -386,8 +378,7 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-	poison_init_mem(__init_begin, __init_end - __init_begin);
-	free_initmem_default(-1);
+	free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -396,10 +387,8 @@ static int keep_initrd;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	if (!keep_initrd) {
-		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, -1, "initrd");
-	}
+	if (!keep_initrd)
+		free_reserved_area(start, end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
-- 
1.7.9.5



From lee.jones at linaro.org  Wed May  8 11:20:25 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 May 2013 16:20:25 +0100
Subject: [PATCH 20/63] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <CACRpkdbx_-wcatRaUpRw5LJY6qsoqDc3iqwk+UVmoBWR1M35KQ@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-21-git-send-email-lee.jones@linaro.org>
 <CACRpkdbx_-wcatRaUpRw5LJY6qsoqDc3iqwk+UVmoBWR1M35KQ@mail.gmail.com>
Message-ID: <20130508152025.GL3459@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > All configuration left in d40_phy_cfg() is runtime configurable and
> > there is already a call into it from d40_runtime_config(), so let's
> > rely on that.
> >
> > Acked-by: Vinod Koul <vnod.koul at intel.com>
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> (...)
> 
> > @@ -2027,6 +2027,14 @@ static int d40_config_memcpy(struct d40_chan *d40c)
> >         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
> >                    dma_has_cap(DMA_SLAVE, cap)) {
> >                 d40c->dma_cfg = dma40_memcpy_conf_phy;
> > +
> > +               /* Generate interrrupt at end of transfer or relink. */
> > +               d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
> > +
> > +               /* Generate interrupt on error. */
> > +               d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> > +               d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> > +
> 
> This hunk looks like it's fixing a bug introduced in patch 19/63.

What makes you say that?

This patch is removing the d40_phy_cfg() invocation from the channel
allocation code, as all slaves now call dmaengine_slave_config(),
where this should happen. The ramification is that memcpy channels
won't be configured correctly, as they do not call the runtime
configuration code. Hence this hunk. It's taking the only important
bit which is relevant for physical memcpy channels and placing it
here instead. It has nothing to do with a bugfix from patch 19.

> Do you try to run a memcpy test after patch 19?

Yes, it works fine.

> Breaking the drive in one patch and fixing it in the next is
> a no-no because of bisection.

We're not doing that.

> Maybe things work fine if you just move this hunk of the
> patch over to 19/63?

That makes no sense.

> Apart from this the patch looks fine.
> 
> Yours,
> Linus Walleij

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed May  8 11:24:58 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 May 2013 16:24:58 +0100
Subject: [PATCH 21/63] dmaengine: ste_dma40: Don't configure runtime
 configurable setup during allocate
In-Reply-To: <CACRpkdbZmzJhZuST+T+qomK_q3q9wt34CGS6sqk0JkZV-Q6O7A@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-22-git-send-email-lee.jones@linaro.org>
 <CACRpkdbZmzJhZuST+T+qomK_q3q9wt34CGS6sqk0JkZV-Q6O7A@mail.gmail.com>
Message-ID: <20130508152458.GM3459@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > Using the dmaengine API, allocating and configuring a channel are two
> > separate actions. Here we're removing logical channel configuration from
> > the channel allocating routines.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> (...)
> 
> > @@ -2024,6 +2024,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
> >                 d40c->dma_cfg = dma40_memcpy_conf_log;
> >                 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
> >
> > +               d40_log_cfg(&d40c->dma_cfg,
> > +                           &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> > +
> 
> So it only gets configured for memcpy now?
> 
> What happens if you use a logical channel for a device transfer?
> 
> Where will that be configured?

In d40_set_runtime_config()

> /* Fill in register values */
> if (chan_is_logical(d40c))
> 	d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> else
> 	d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);

> Have you tested this combo?

Yes. All ux500 based DMA use logical channels.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From catalin.marinas at arm.com  Wed May  8 11:28:19 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 8 May 2013 16:28:19 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130505222645.GA1433@schnuecks.de>
References: <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <20130505222645.GA1433@schnuecks.de>
Message-ID: <20130508152819.GJ2703@arm.com>

On Sun, May 05, 2013 at 11:26:47PM +0100, Simon Baatz wrote:
> On Fri, May 03, 2013 at 11:02:42AM +0100, Catalin Marinas wrote:
> > On Thu, May 02, 2013 at 08:38:36PM +0100, Simon Baatz wrote:
> ...
> > I haven't run the tests but I can see  why it fails without
> > flush_kernel_dcache_page(). So I think this function needs to be
> > implemented for aliasing VIPT or VIVT caches.
> > 
> > > It is even needed in flush_dcache_page() as long as everybody
> > > continues to use flush_dcache_page() instead of
> > > flush_kernel_dcache_page() when appropriate...
> > > (This is probably the main reason why the problem I reported is so
> > > uncommon: Everybody seems to use flush_dcache_page() and since it
> > > flushes the kernel mapping in these cases, everything is fine.)
> > 
> > That's why for non-aliasing VIPT we could make it just a clear_bit() and
> > let the callers fix their API usage.
> 
> Do you mean the unnecessary flush for anon pages or also the D/I
> flush for user space mapped page cache pages?

flush_dcache_page() should just ignore anonymous pages. The D/I
coherency would be handled in __sync_icache_dcache() later. Do we have
cases where a page is already mapped in user space (pte valid) and the
kernel writes any code to it? I don't think we have. PowerPC have a
simplified flush_dcache_page() and they haven't seen any issues.

> For anon pages, that was the content of the patch you acked ([1])
> once.  However, Russel did not like the idea to use the
> PG_dcache_clean bit also for anon pages.

I think Russell was right, the kernel does not have any guarantees about
the PG_arch_1 bit on anonymous pages. Do we could remove the !mapping
code path in flush_dcache_page().

> I have a newer version that does the following: Do nothing for
> mapping == NULL on non-aliasing VIPT in flush_dcache_page().  

Can this mapping == NULL be generalised for aliasing caches?

> In __sync_icache_dcache() flush if mapping == NULL (always on aliasing
> VIPT, only if pte_exec() on non-aliasing VIPT).

If the page is anonymous, do we expect user code to execute from a
clear page? When the page is first allocated, clear_user_highpage should
take care of the aliases already.

-- 
Catalin


From lee.jones at linaro.org  Wed May  8 11:28:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 May 2013 16:28:53 +0100
Subject: [PATCH 28/63] ARM: ux500: Stop passing UART's platform data for
 Device Tree boots
In-Reply-To: <CACRpkdYCABo0AULsiUgwm3g=906iKzp_ZDFKLj=HgDbNK9mNUQ@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-29-git-send-email-lee.jones@linaro.org>
 <CACRpkdYCABo0AULsiUgwm3g=906iKzp_ZDFKLj=HgDbNK9mNUQ@mail.gmail.com>
Message-ID: <20130508152853.GN3459@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > It was required to pass DMA channel configuration information to the
> > UART driver before the new DMA API was in place. Now that it is, and
> > is fully compatible with Device Tree we can stop doing that.
> >
> > Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> I can't apply this as it is clearly dependent on a patch to
> drivers/tty/serial/amba-pl011.c that is not yet upstream.

Right, I'll move this patch to the end of the patch-set.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From gregkh at linuxfoundation.org  Wed May  8 11:34:59 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Wed, 8 May 2013 08:34:59 -0700
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305081634.43498.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
Message-ID: <20130508153459.GA17186@kroah.com>

On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
> > +#define ASC_MAJOR		204
> > +#define ASC_MINOR_START		40
> 
> I don't know what the current policy is on allocating major/minor numbers,
> but I'm sure you cannot just reuse one that is already used.

I agree, why are you trying to create a new tty device name?  Can't you
use the existing ttyS name and minor number as you will not have any
other type of serial device on this system?

thanks,

greg k-h


From stefano.stabellini at eu.citrix.com  Wed May  8 11:41:52 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 16:41:52 +0100
Subject: [PATCH v3 2/4] kernel: missing include in cputime.c
In-Reply-To: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
Message-ID: <1368027714-14506-2-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: mingo at redhat.com
CC: peterz at infradead.org
---
 kernel/sched/cputime.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
index ed12cbb..488a5bf 100644
--- a/kernel/sched/cputime.c
+++ b/kernel/sched/cputime.c
@@ -5,6 +5,7 @@
 #include <linux/static_key.h>
 #include <linux/context_tracking.h>
 #include "sched.h"
+#include <asm/paravirt.h>
 
 
 #ifdef CONFIG_IRQ_TIME_ACCOUNTING
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  8 11:41:54 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 16:41:54 +0100
Subject: [PATCH v3 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
Message-ID: <1368027714-14506-4-git-send-email-stefano.stabellini@eu.citrix.com>

Register the runstate_memory_area with the hypervisor.
Use pv_time_ops.steal_clock to account for stolen ticks.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

Changes in v3:
- use BUG_ON and smp_processor_id.
---
 arch/arm/xen/enlighten.c |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 13609e0..dfa7738 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -14,7 +14,10 @@
 #include <xen/xen-ops.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <asm/arch_timer.h>
 #include <asm/system_misc.h>
+#include <asm/paravirt.h>
+#include <linux/jump_label.h>
 #include <linux/interrupt.h>
 #include <linux/irqreturn.h>
 #include <linux/module.h>
@@ -152,6 +155,19 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
 }
 EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 
+unsigned long long xen_stolen_accounting(int cpu)
+{
+	struct vcpu_runstate_info state;
+
+	BUG_ON(cpu != smp_processor_id());
+
+	xen_get_runstate_snapshot(&state);
+
+	WARN_ON(state.state != RUNSTATE_running);
+
+	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
+}
+
 static void __init xen_percpu_init(void *unused)
 {
 	struct vcpu_register_vcpu_info info;
@@ -169,6 +185,8 @@ static void __init xen_percpu_init(void *unused)
 	BUG_ON(err);
 	per_cpu(xen_vcpu, cpu) = vcpup;
 
+	xen_setup_runstate_info(cpu);
+
 	enable_percpu_irq(xen_events_irq, 0);
 }
 
@@ -300,6 +318,10 @@ static int __init xen_init_events(void)
 
 	on_each_cpu(xen_percpu_init, NULL, 0);
 
+	pv_time_ops.steal_clock = xen_stolen_accounting;
+	static_key_slow_inc(&paravirt_steal_enabled);
+	static_key_slow_inc(&paravirt_steal_rq_enabled);
+
 	return 0;
 }
 postcore_initcall(xen_init_events);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  8 11:41:51 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 16:41:51 +0100
Subject: [PATCH v3 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
Message-ID: <1368027714-14506-1-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:
- leave do_stolen_accounting in arch/x86/xen/time.c;
- use the new common functions in arch/ia64/xen/time.c.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell at citrix.com>
CC: konrad.wilk at oracle.com
---
 arch/ia64/xen/time.c  |   48 +++----------------------
 arch/x86/xen/time.c   |   76 +----------------------------------------
 drivers/xen/Makefile  |    2 +-
 drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h |    5 +++
 5 files changed, 104 insertions(+), 118 deletions(-)
 create mode 100644 drivers/xen/time.c

diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
index 1f8244a..79a0b8c 100644
--- a/arch/ia64/xen/time.c
+++ b/arch/ia64/xen/time.c
@@ -34,53 +34,17 @@
 
 #include "../kernel/fsyscall_gtod_data.h"
 
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
 static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
 static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
 
 /* taken from i386/kernel/time-xen.c */
 static void xen_init_missing_ticks_accounting(int cpu)
 {
-	struct vcpu_register_runstate_memory_area area;
-	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
-	int rc;
+	xen_setup_runstate_info(&runstate);
 
-	memset(runstate, 0, sizeof(*runstate));
-
-	area.addr.v = runstate;
-	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
-				&area);
-	WARN_ON(rc && rc != -ENOSYS);
-
-	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
-	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
-					    + runstate->time[RUNSTATE_offline];
-}
-
-/*
- * Runstate accounting
- */
-/* stolen from arch/x86/xen/time.c */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = state->state_entry_time;
-		rmb();
-		*res = *state;
-		rmb();
-	} while (state->state_entry_time != state_time);
+	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
+	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
+					    + runstate.time[RUNSTATE_offline];
 }
 
 #define NS_PER_TICK (1000000000LL/HZ)
@@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
 	struct vcpu_runstate_info runstate;
 	struct task_struct *p = current;
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	/*
 	 * Check for vcpu migration effect
@@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
 	 */
 	now = ia64_native_sched_clock();
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	WARN_ON(runstate.state != RUNSTATE_running);
 
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 0296a95..18d0104 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -30,9 +30,6 @@
 #define TIMER_SLOP	100000
 #define NS_PER_TICK	(1000000000LL / HZ)
 
-/* runstate info updated by Xen */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
-
 /* snapshots of runstate info */
 static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 
@@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 static DEFINE_PER_CPU(u64, xen_residual_stolen);
 static DEFINE_PER_CPU(u64, xen_residual_blocked);
 
-/* return an consistent snapshot of 64-bit time/counter value */
-static u64 get64(const u64 *p)
-{
-	u64 ret;
-
-	if (BITS_PER_LONG < 64) {
-		u32 *p32 = (u32 *)p;
-		u32 h, l;
-
-		/*
-		 * Read high then low, and then make sure high is
-		 * still the same; this will only loop if low wraps
-		 * and carries into high.
-		 * XXX some clean way to make this endian-proof?
-		 */
-		do {
-			h = p32[1];
-			barrier();
-			l = p32[0];
-			barrier();
-		} while (p32[1] != h);
-
-		ret = (((u64)h) << 32) | l;
-	} else
-		ret = *p;
-
-	return ret;
-}
-
-/*
- * Runstate accounting
- */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = get64(&state->state_entry_time);
-		barrier();
-		*res = *state;
-		barrier();
-	} while (get64(&state->state_entry_time) != state_time);
-}
-
-/* return true when a vcpu could run but has no real cpu to run on */
-bool xen_vcpu_stolen(int vcpu)
-{
-	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
-}
-
-void xen_setup_runstate_info(int cpu)
-{
-	struct vcpu_register_runstate_memory_area area;
-
-	area.addr.v = &per_cpu(xen_runstate, cpu);
-
-	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
-			       cpu, &area))
-		BUG();
-}
-
 static void do_stolen_accounting(void)
 {
 	struct vcpu_runstate_info state;
@@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
 	s64 blocked, runnable, offline, stolen;
 	cputime_t ticks;
 
-	get_runstate_snapshot(&state);
+	xen_get_runstate_snapshot(&state);
 
 	WARN_ON(state.state != RUNSTATE_running);
 
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index eabd0ee..2bf461a 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -3,7 +3,7 @@ obj-y	+= manage.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 endif
 obj-$(CONFIG_X86)			+= fallback.o
-obj-y	+= grant-table.o features.o events.o balloon.o
+obj-y	+= grant-table.o features.o events.o balloon.o time.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
diff --git a/drivers/xen/time.c b/drivers/xen/time.c
new file mode 100644
index 0000000..c2e39d3
--- /dev/null
+++ b/drivers/xen/time.c
@@ -0,0 +1,91 @@
+/*
+ * Xen stolen ticks accounting.
+ */
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/math64.h>
+#include <linux/gfp.h>
+
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+
+#include <xen/events.h>
+#include <xen/features.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/vcpu.h>
+#include <xen/xen-ops.h>
+
+/* runstate info updated by Xen */
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
+
+/* return an consistent snapshot of 64-bit time/counter value */
+static u64 get64(const u64 *p)
+{
+	u64 ret;
+
+	if (BITS_PER_LONG < 64) {
+		u32 *p32 = (u32 *)p;
+		u32 h, l;
+
+		/*
+		 * Read high then low, and then make sure high is
+		 * still the same; this will only loop if low wraps
+		 * and carries into high.
+		 * XXX some clean way to make this endian-proof?
+		 */
+		do {
+			h = p32[1];
+			barrier();
+			l = p32[0];
+			barrier();
+		} while (p32[1] != h);
+
+		ret = (((u64)h) << 32) | l;
+	} else
+		ret = *p;
+
+	return ret;
+}
+
+/*
+ * Runstate accounting
+ */
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
+{
+	u64 state_time;
+	struct vcpu_runstate_info *state;
+
+	BUG_ON(preemptible());
+
+	state = &__get_cpu_var(xen_runstate);
+
+	/*
+	 * The runstate info is always updated by the hypervisor on
+	 * the current CPU, so there's no need to use anything
+	 * stronger than a compiler barrier when fetching it.
+	 */
+	do {
+		state_time = get64(&state->state_entry_time);
+		barrier();
+		*res = *state;
+		barrier();
+	} while (get64(&state->state_entry_time) != state_time);
+}
+
+/* return true when a vcpu could run but has no real cpu to run on */
+bool xen_vcpu_stolen(int vcpu)
+{
+	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
+}
+
+void xen_setup_runstate_info(int cpu)
+{
+	struct vcpu_register_runstate_memory_area area;
+
+	area.addr.v = &per_cpu(xen_runstate, cpu);
+
+	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
+			       cpu, &area))
+		BUG();
+}
+
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index d6fe062..4fd4e47 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -3,6 +3,7 @@
 
 #include <linux/percpu.h>
 #include <asm/xen/interface.h>
+#include <xen/interface/vcpu.h>
 
 DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
 
@@ -16,6 +17,10 @@ void xen_mm_unpin_all(void);
 void xen_timer_resume(void);
 void xen_arch_resume(void);
 
+bool xen_vcpu_stolen(int vcpu);
+void xen_setup_runstate_info(int cpu);
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res);
+
 int xen_setup_shutdown_event(void);
 
 extern unsigned long *xen_contiguous_bitmap;
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Wed May  8 11:41:53 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 16:41:53 +0100
Subject: [PATCH v3 3/4] arm: introduce CONFIG_PARAVIRT,
 PARAVIRT_TIME_ACCOUNTING and pv_time_ops
In-Reply-To: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
Message-ID: <1368027714-14506-3-git-send-email-stefano.stabellini@eu.citrix.com>

Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.

The only paravirt interface supported is pv_time_ops.steal_clock, so no
runtime pvops patching needed.

This allows us to make use of steal_account_process_tick for stolen
ticks accounting.

Changes in v3:
- improve commit description and Kconfig help text;
- no need to initialize pv_time_ops;
- add PARAVIRT_TIME_ACCOUNTING.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: linux at arm.linux.org.uk
CC: will.deacon at arm.com
CC: nico at linaro.org
CC: marc.zyngier at arm.com
CC: cov at codeaurora.org
CC: arnd at arndb.de
CC: olof at lixom.net
---
 arch/arm/Kconfig                |   20 ++++++++++++++++++++
 arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   25 +++++++++++++++++++++++++
 4 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 344e299..89ee2f1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1887,12 +1887,32 @@ config XEN_DOM0
 	def_bool y
 	depends on XEN
 
+config PARAVIRT
+	bool "Enable paravirtualization code"
+	---help---
+	  This changes the kernel so it can modify itself when it is run
+	  under a hypervisor, potentially improving performance significantly
+	  over full virtualization.
+
+config PARAVIRT_TIME_ACCOUNTING
+	bool "Paravirtual steal time accounting"
+	select PARAVIRT
+	default n
+	---help---
+	  Select this option to enable fine granularity task steal time
+	  accounting. Time spent executing other tasks in parallel with
+	  the current vCPU is discounted from the vCPU power. To account for
+	  that, there can be a small performance impact.
+
+	  If in doubt, say N here.
+
 config XEN
 	bool "Xen guest support on ARM (EXPERIMENTAL)"
 	depends on ARM && AEABI && OF
 	depends on CPU_V7 && !CPU_V6
 	depends on !GENERIC_ATOMIC64
 	select ARM_PSCI
+	select PARAVIRT
 	help
 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
diff --git a/arch/arm/include/asm/paravirt.h b/arch/arm/include/asm/paravirt.h
new file mode 100644
index 0000000..3b95bc6
--- /dev/null
+++ b/arch/arm/include/asm/paravirt.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_PARAVIRT_H
+#define _ASM_ARM_PARAVIRT_H
+
+struct static_key;
+extern struct static_key paravirt_steal_enabled;
+extern struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops {
+	unsigned long long (*steal_clock)(int cpu);
+};
+extern struct pv_time_ops pv_time_ops;
+
+static inline u64 paravirt_steal_clock(int cpu)
+{
+	return pv_time_ops.steal_clock(cpu);
+}
+
+
+#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..d911db6 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 ifneq ($(CONFIG_ARCH_EBSA110),y)
   obj-y		+= io.o
 endif
+obj-$(CONFIG_PARAVIRT)	+= paravirt.o
 
 head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
diff --git a/arch/arm/kernel/paravirt.c b/arch/arm/kernel/paravirt.c
new file mode 100644
index 0000000..53f371e
--- /dev/null
+++ b/arch/arm/kernel/paravirt.c
@@ -0,0 +1,25 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 Citrix Systems
+ *
+ * Author: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
+ */
+
+#include <linux/export.h>
+#include <linux/jump_label.h>
+#include <linux/types.h>
+#include <asm/paravirt.h>
+
+struct static_key paravirt_steal_enabled;
+struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops pv_time_ops;
+EXPORT_SYMBOL_GPL(pv_time_ops);
-- 
1.7.2.5



From plagnioj at jcrosoft.com  Wed May  8 11:40:57 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 8 May 2013 17:40:57 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508153459.GA17186@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
 <20130508153459.GA17186@kroah.com>
Message-ID: <20130508154057.GB3041@game.jcrosoft.org>

On 08:34 Wed 08 May     , Greg KH wrote:
> On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
> > > +#define ASC_MAJOR		204
> > > +#define ASC_MINOR_START		40
> > 
> > I don't know what the current policy is on allocating major/minor numbers,
> > but I'm sure you cannot just reuse one that is already used.
> 
> I agree, why are you trying to create a new tty device name?  Can't you
> use the existing ttyS name and minor number as you will not have any
> other type of serial device on this system?

Greg on ST STB for more than 10 years we use ttyASC I'll prefer ttySx

on the DTB SoC you have one one IP present the st,asc

Best Regards,
J.
> 
> thanks,
> 
> greg k-h
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From stuart.menefy at st.com  Wed May  8 11:48:31 2013
From: stuart.menefy at st.com (Stuart MENEFY)
Date: Wed, 08 May 2013 16:48:31 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <20130508144907.GB20820@mudshark.cambridge.arm.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081638.23100.arnd@arndb.de>
 <20130508144907.GB20820@mudshark.cambridge.arm.com>
Message-ID: <518A73CF.8000309@st.com>

On 08/05/13 15:49, Will Deacon wrote:
> On Wed, May 08, 2013 at 03:38:22PM +0100, Arnd Bergmann wrote:
>> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>>> From: Stuart Menefy <stuart.menefy at st.com>
>>>
>>> This is a simple driver for the global timer module found in the Cortex
>>> A9-MP cores from revision r1p0 onwards. This should be able to perform
>>> the functions of the system timer and the local timer in an SMP system.
>>>
>>> The global timer has the following features:
>>>     The global timer is a 64-bit incrementing counter with an
>>> auto-incrementing feature. It continues incrementing after sending
>>> interrupts. The global timer is memory mapped in the private memory
>>> region.
>>>     The global timer is accessible to all Cortex-A9 processors in the
>>> cluster. Each Cortex-A9 processor has a private 64-bit comparator that
>>> is used to assert a private interrupt when the global timer has reached
>>> the comparator value. All the Cortex-A9 processors in a design use the
>>> banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
>>> Controller as a Private Peripheral Interrupt. The global timer is
>>> clocked by PERIPHCLK.
>>>
>>> Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
>>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>>
>>
>> Are you sure we don't already have a driver for this? It sounds unlikely
>> that you are the first one to do this when the hardware is so common.
> 
> An additional reason why people don't make use of this timer (on top of the
> power domain concerns raised by Rob) is due to the following from the A9
> TRM:
> 
>   `From r2p0 the comparators for each processor with the global timer fire
>    when the timer value is greater than or equal to. In previous revisions
>    the comparators fired when the timer value was equal to.'
> 
> So you'll get into all sorts of horrible races on those older revisions if
> you're not careful.

Fortunately the earliest version of these SoCs uses r2p2, so we avoided that
particular issue. But as the code doesn't attempt to work around these
problems a check on the version number might be a good idea to prevent other
people accidentally hitting it.

Stuart




From gregkh at linuxfoundation.org  Wed May  8 11:53:01 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Wed, 8 May 2013 08:53:01 -0700
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508154057.GB3041@game.jcrosoft.org>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
 <20130508153459.GA17186@kroah.com>
 <20130508154057.GB3041@game.jcrosoft.org>
Message-ID: <20130508155301.GB27273@kroah.com>

On Wed, May 08, 2013 at 05:40:57PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:34 Wed 08 May     , Greg KH wrote:
> > On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
> > > > +#define ASC_MAJOR		204
> > > > +#define ASC_MINOR_START		40
> > > 
> > > I don't know what the current policy is on allocating major/minor numbers,
> > > but I'm sure you cannot just reuse one that is already used.
> > 
> > I agree, why are you trying to create a new tty device name?  Can't you
> > use the existing ttyS name and minor number as you will not have any
> > other type of serial device on this system?
> 
> Greg on ST STB for more than 10 years we use ttyASC I'll prefer ttySx

For 10+ years you have had an out-of-tree serial driver?  What
major/minor numbers did you use for it?

> on the DTB SoC you have one one IP present the st,asc

I don't understand, what do you mean by this?

confused,

greg k-h


From liuj97 at gmail.com  Wed May  8 11:51:10 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed,  8 May 2013 23:51:10 +0800
Subject: [PATCH v5,
 part4 13/41] mm/ARM: prepare for removing num_physpages and simplify
 mem_init()
In-Reply-To: <1368028298-7401-1-git-send-email-jiang.liu@huawei.com>
References: <1368028298-7401-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368028298-7401-14-git-send-email-jiang.liu@huawei.com>

Prepare for removing num_physpages and simplify mem_init().

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mm/init.c |   47 ++---------------------------------------------
 1 file changed, 2 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index add4fcb..7a911d1 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -582,9 +582,6 @@ static void __init free_highpages(void)
  */
 void __init mem_init(void)
 {
-	unsigned long reserved_pages, free_pages;
-	struct memblock_region *reg;
-	int i;
 #ifdef CONFIG_HAVE_TCM
 	/* These pointers are filled in on TCM detection */
 	extern u32 dtcm_end;
@@ -605,47 +602,7 @@ void __init mem_init(void)
 
 	free_highpages();
 
-	reserved_pages = free_pages = 0;
-
-	for_each_bank(i, &meminfo) {
-		struct membank *bank = &meminfo.bank[i];
-		unsigned int pfn1, pfn2;
-		struct page *page, *end;
-
-		pfn1 = bank_pfn_start(bank);
-		pfn2 = bank_pfn_end(bank);
-
-		page = pfn_to_page(pfn1);
-		end  = pfn_to_page(pfn2 - 1) + 1;
-
-		do {
-			if (PageReserved(page))
-				reserved_pages++;
-			else if (!page_count(page))
-				free_pages++;
-			page++;
-		} while (page < end);
-	}
-
-	/*
-	 * Since our memory may not be contiguous, calculate the
-	 * real number of pages we have in this system
-	 */
-	printk(KERN_INFO "Memory:");
-	num_physpages = 0;
-	for_each_memblock(memory, reg) {
-		unsigned long pages = memblock_region_memory_end_pfn(reg) -
-			memblock_region_memory_base_pfn(reg);
-		num_physpages += pages;
-		printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-	}
-	printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-	printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
-		nr_free_pages() << (PAGE_SHIFT-10),
-		free_pages << (PAGE_SHIFT-10),
-		reserved_pages << (PAGE_SHIFT-10),
-		totalhigh_pages << (PAGE_SHIFT-10));
+	mem_init_print_info(NULL);
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -711,7 +668,7 @@ void __init mem_init(void)
 	BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE	> PAGE_OFFSET);
 #endif
 
-	if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+	if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
 		extern int sysctl_overcommit_memory;
 		/*
 		 * On a machine this small we won't get
-- 
1.7.9.5



From liuj97 at gmail.com  Wed May  8 11:51:11 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed,  8 May 2013 23:51:11 +0800
Subject: [PATCH v5,
 part4 14/41] mm/ARM64: prepare for removing num_physpages and
 simplify mem_init()
In-Reply-To: <1368028298-7401-1-git-send-email-jiang.liu@huawei.com>
References: <1368028298-7401-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368028298-7401-15-git-send-email-jiang.liu@huawei.com>

Prepare for removing num_physpages and simplify mem_init().

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm64/mm/init.c |   48 +++---------------------------------------------
 1 file changed, 3 insertions(+), 45 deletions(-)

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 0f2cf5d..821e788 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -272,59 +272,17 @@ static void __init free_unused_memmap(void)
  */
 void __init mem_init(void)
 {
-	unsigned long reserved_pages, free_pages;
-	struct memblock_region *reg;
-
 	arm64_swiotlb_init();
 
 	max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
-	/* this will put all unused low memory onto the freelists */
 	free_unused_memmap();
 #endif
-
+	/* this will put all unused low memory onto the freelists */
 	free_all_bootmem();
 
-	reserved_pages = free_pages = 0;
-
-	for_each_memblock(memory, reg) {
-		unsigned int pfn1, pfn2;
-		struct page *page, *end;
-
-		pfn1 = __phys_to_pfn(reg->base);
-		pfn2 = pfn1 + __phys_to_pfn(reg->size);
-
-		page = pfn_to_page(pfn1);
-		end  = pfn_to_page(pfn2 - 1) + 1;
-
-		do {
-			if (PageReserved(page))
-				reserved_pages++;
-			else if (!page_count(page))
-				free_pages++;
-			page++;
-		} while (page < end);
-	}
-
-	/*
-	 * Since our memory may not be contiguous, calculate the real number
-	 * of pages we have in this system.
-	 */
-	pr_info("Memory:");
-	num_physpages = 0;
-	for_each_memblock(memory, reg) {
-		unsigned long pages = memblock_region_memory_end_pfn(reg) -
-			memblock_region_memory_base_pfn(reg);
-		num_physpages += pages;
-		printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-	}
-	printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-	pr_notice("Memory: %luk/%luk available, %luk reserved\n",
-		  nr_free_pages() << (PAGE_SHIFT-10),
-		  free_pages << (PAGE_SHIFT-10),
-		  reserved_pages << (PAGE_SHIFT-10));
+	mem_init_print_info();
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -366,7 +324,7 @@ void __init mem_init(void)
 	BUILD_BUG_ON(TASK_SIZE_64			> MODULES_VADDR);
 	BUG_ON(TASK_SIZE_64				> MODULES_VADDR);
 
-	if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+	if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
 		extern int sysctl_overcommit_memory;
 		/*
 		 * On a machine this small we won't get anywhere without
-- 
1.7.9.5



From marc.zyngier at arm.com  Wed May  8 12:03:47 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 08 May 2013 17:03:47 +0100
Subject: [PATCH v3 3/4] arm: introduce CONFIG_PARAVIRT,
 PARAVIRT_TIME_ACCOUNTING and pv_time_ops
In-Reply-To: <1368027714-14506-3-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-3-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <518A7763.4050509@arm.com>

Hi Stefano,

On 08/05/13 16:41, Stefano Stabellini wrote:
> Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.
> 
> The only paravirt interface supported is pv_time_ops.steal_clock, so no
> runtime pvops patching needed.
> 
> This allows us to make use of steal_account_process_tick for stolen
> ticks accounting.
> 
> Changes in v3:
> - improve commit description and Kconfig help text;
> - no need to initialize pv_time_ops;
> - add PARAVIRT_TIME_ACCOUNTING.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> CC: linux at arm.linux.org.uk
> CC: will.deacon at arm.com
> CC: nico at linaro.org
> CC: marc.zyngier at arm.com
> CC: cov at codeaurora.org
> CC: arnd at arndb.de
> CC: olof at lixom.net
> ---
>  arch/arm/Kconfig                |   20 ++++++++++++++++++++
>  arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
>  arch/arm/kernel/Makefile        |    1 +
>  arch/arm/kernel/paravirt.c      |   25 +++++++++++++++++++++++++
>  4 files changed, 65 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/include/asm/paravirt.h
>  create mode 100644 arch/arm/kernel/paravirt.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 344e299..89ee2f1 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1887,12 +1887,32 @@ config XEN_DOM0
>  	def_bool y
>  	depends on XEN
>  
> +config PARAVIRT
> +	bool "Enable paravirtualization code"
> +	---help---
> +	  This changes the kernel so it can modify itself when it is run
> +	  under a hypervisor, potentially improving performance significantly
> +	  over full virtualization.
> +
> +config PARAVIRT_TIME_ACCOUNTING
> +	bool "Paravirtual steal time accounting"
> +	select PARAVIRT

Surely you meant "depends on" instead of "select" here? Otherwise I
don't really see the point of PARAVIRT...

> +	default n
> +	---help---
> +	  Select this option to enable fine granularity task steal time
> +	  accounting. Time spent executing other tasks in parallel with
> +	  the current vCPU is discounted from the vCPU power. To account for
> +	  that, there can be a small performance impact.
> +
> +	  If in doubt, say N here.
> +
>  config XEN
>  	bool "Xen guest support on ARM (EXPERIMENTAL)"
>  	depends on ARM && AEABI && OF
>  	depends on CPU_V7 && !CPU_V6
>  	depends on !GENERIC_ATOMIC64
>  	select ARM_PSCI
> +	select PARAVIRT
>  	help
>  	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
>  
-- 
Jazz is not dead. It just smells funny...



From plagnioj at jcrosoft.com  Wed May  8 12:03:05 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 9 May 2013 00:03:05 +0800
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508155301.GB27273@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de> <20130508153459.GA17186@kroah.com>
 <20130508154057.GB3041@game.jcrosoft.org> <20130508155301.GB27273@kroah.com>
Message-ID: <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>


On May 8, 2013, at 11:53 PM, Greg KH <gregkh at linuxfoundation.org> wrote:

> On Wed, May 08, 2013 at 05:40:57PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 08:34 Wed 08 May     , Greg KH wrote:
>>> On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
>>>>> +#define ASC_MAJOR		204
>>>>> +#define ASC_MINOR_START		40
>>>> 
>>>> I don't know what the current policy is on allocating major/minor numbers,
>>>> but I'm sure you cannot just reuse one that is already used.
>>> 
>>> I agree, why are you trying to create a new tty device name?  Can't you
>>> use the existing ttyS name and minor number as you will not have any
>>> other type of serial device on this system?
>> 
>> Greg on ST STB for more than 10 years we use ttyASC I'll prefer ttySx
> 
> For 10+ years you have had an out-of-tree serial driver?
yes ST have it out of tree for very long time even I puts them to come mainline

>  What
> major/minor numbers did you use for it?

http://git.stlinux.com/?p=havana/com.st.havana.kernel.git;a=blob;f=drivers/serial/stm-asc.h;h=79e003ffeb21df55a6af94774fc9c4b3d8de18e9;hb=HEAD

  52 #define ASC_MAJOR               204
  53 #define ASC_MINOR_START         40

same as in this patch

> 
>> on the DTB SoC you have one one IP present the st,asc
> 
> I don't understand, what do you mean by this?
> 
> confused,

just mention there is not hardware reason to not use the generic ttySx in place of ttyAS
as we have only one IP that handle serial on this family of SoC

personally I'll switch to ttySx

Best Regards,
J.

From stefano.stabellini at eu.citrix.com  Wed May  8 12:07:06 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 17:07:06 +0100
Subject: [PATCH v3 3/4] arm: introduce CONFIG_PARAVIRT,
 PARAVIRT_TIME_ACCOUNTING and pv_time_ops
In-Reply-To: <518A7763.4050509@arm.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <518A7763.4050509@arm.com>
Message-ID: <alpine.DEB.2.02.1305081704530.18865@kaball.uk.xensource.com>

On Wed, 8 May 2013, Marc Zyngier wrote:
> Hi Stefano,
> 
> On 08/05/13 16:41, Stefano Stabellini wrote:
> > Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.
> > 
> > The only paravirt interface supported is pv_time_ops.steal_clock, so no
> > runtime pvops patching needed.
> > 
> > This allows us to make use of steal_account_process_tick for stolen
> > ticks accounting.
> > 
> > Changes in v3:
> > - improve commit description and Kconfig help text;
> > - no need to initialize pv_time_ops;
> > - add PARAVIRT_TIME_ACCOUNTING.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > CC: linux at arm.linux.org.uk
> > CC: will.deacon at arm.com
> > CC: nico at linaro.org
> > CC: marc.zyngier at arm.com
> > CC: cov at codeaurora.org
> > CC: arnd at arndb.de
> > CC: olof at lixom.net
> > ---
> >  arch/arm/Kconfig                |   20 ++++++++++++++++++++
> >  arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
> >  arch/arm/kernel/Makefile        |    1 +
> >  arch/arm/kernel/paravirt.c      |   25 +++++++++++++++++++++++++
> >  4 files changed, 65 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/include/asm/paravirt.h
> >  create mode 100644 arch/arm/kernel/paravirt.c
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 344e299..89ee2f1 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1887,12 +1887,32 @@ config XEN_DOM0
> >  	def_bool y
> >  	depends on XEN
> >  
> > +config PARAVIRT
> > +	bool "Enable paravirtualization code"
> > +	---help---
> > +	  This changes the kernel so it can modify itself when it is run
> > +	  under a hypervisor, potentially improving performance significantly
> > +	  over full virtualization.
> > +
> > +config PARAVIRT_TIME_ACCOUNTING
> > +	bool "Paravirtual steal time accounting"
> > +	select PARAVIRT
> 
> Surely you meant "depends on" instead of "select" here? Otherwise I
> don't really see the point of PARAVIRT...

I agree with you that "depends on" seems to be the right thing here, but
on x86 is actually select.

The original commit is 095c0aa83e52d6c3dd7168610746703921f570af.


From marc.zyngier at arm.com  Wed May  8 12:07:18 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 08 May 2013 17:07:18 +0100
Subject: [PATCH v3 4/4] xen/arm: account for stolen ticks
In-Reply-To: <1368027714-14506-4-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-4-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <518A7836.4030705@arm.com>

Hi Stefano,

On 08/05/13 16:41, Stefano Stabellini wrote:
> Register the runstate_memory_area with the hypervisor.
> Use pv_time_ops.steal_clock to account for stolen ticks.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> 
> Changes in v3:
> - use BUG_ON and smp_processor_id.
> ---
>  arch/arm/xen/enlighten.c |   22 ++++++++++++++++++++++
>  1 files changed, 22 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 13609e0..dfa7738 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -14,7 +14,10 @@
>  #include <xen/xen-ops.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
> +#include <asm/arch_timer.h>
>  #include <asm/system_misc.h>
> +#include <asm/paravirt.h>
> +#include <linux/jump_label.h>
>  #include <linux/interrupt.h>
>  #include <linux/irqreturn.h>
>  #include <linux/module.h>
> @@ -152,6 +155,19 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
>  }
>  EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
>  
> +unsigned long long xen_stolen_accounting(int cpu)
> +{
> +	struct vcpu_runstate_info state;
> +
> +	BUG_ON(cpu != smp_processor_id());
> +
> +	xen_get_runstate_snapshot(&state);
> +
> +	WARN_ON(state.state != RUNSTATE_running);
> +
> +	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
> +}
> +
>  static void __init xen_percpu_init(void *unused)
>  {
>  	struct vcpu_register_vcpu_info info;
> @@ -169,6 +185,8 @@ static void __init xen_percpu_init(void *unused)
>  	BUG_ON(err);
>  	per_cpu(xen_vcpu, cpu) = vcpup;
>  
> +	xen_setup_runstate_info(cpu);
> +
>  	enable_percpu_irq(xen_events_irq, 0);
>  }
>  
> @@ -300,6 +318,10 @@ static int __init xen_init_events(void)
>  
>  	on_each_cpu(xen_percpu_init, NULL, 0);
>  
> +	pv_time_ops.steal_clock = xen_stolen_accounting;

What guarantee do we have that this is done before the rest of the
kernel calls paravirt_steal_clock()? What if we have Xen support enabled
but don't run as a Xen guest?

> +	static_key_slow_inc(&paravirt_steal_enabled);
> +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> +
>  	return 0;
>  }
>  postcore_initcall(xen_init_events);
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From stephen.gallimore at st.com  Wed May  8 12:10:48 2013
From: stephen.gallimore at st.com (Stephen GALLIMORE)
Date: Wed, 8 May 2013 18:10:48 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508153459.GA17186@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de> <20130508153459.GA17186@kroah.com>
Message-ID: <A3BF01DB4A606149A4C20C4C4C808F6C3189E576C2@SAFEX1MAIL1.st.com>


>On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
> > > +#define ASC_MAJOR		204
> > > +#define ASC_MINOR_START		40
> > 
> > I don't know what the current policy is on allocating major/minor 
> > numbers, but I'm sure you cannot just reuse one that is already used.

First, our apologies, this issue was raised internally and then got forgotten about, there's always something I guess.
 
> >I agree, why are you trying to create a new tty device name?  Can't you use the existing ttyS name and minor number as you will not have any other type of serial
> >device on this system?

That is an interesting question Greg; I believe it probably stems from historic ST SoCs that had two different types of serial devices, something that is no longer the case. We will review our approach to this again, although we are not sure we can use the existing ttyS major/minor (even if that is an acceptable thing to do) because of the (remote) possibility of someone using a standard PCIe attached serial card.

Regards,
-stephen




From gregkh at linuxfoundation.org  Wed May  8 12:15:27 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Wed, 8 May 2013 09:15:27 -0700
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
 <20130508153459.GA17186@kroah.com>
 <20130508154057.GB3041@game.jcrosoft.org>
 <20130508155301.GB27273@kroah.com>
 <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
Message-ID: <20130508161527.GA28080@kroah.com>

On Thu, May 09, 2013 at 12:03:05AM +0800, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> On May 8, 2013, at 11:53 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> 
> > On Wed, May 08, 2013 at 05:40:57PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> On 08:34 Wed 08 May     , Greg KH wrote:
> >>> On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
> >>>>> +#define ASC_MAJOR		204
> >>>>> +#define ASC_MINOR_START		40
> >>>> 
> >>>> I don't know what the current policy is on allocating major/minor numbers,
> >>>> but I'm sure you cannot just reuse one that is already used.
> >>> 
> >>> I agree, why are you trying to create a new tty device name?  Can't you
> >>> use the existing ttyS name and minor number as you will not have any
> >>> other type of serial device on this system?
> >> 
> >> Greg on ST STB for more than 10 years we use ttyASC I'll prefer ttySx
> > 
> > For 10+ years you have had an out-of-tree serial driver?
> yes ST have it out of tree for very long time even I puts them to come mainline

Crazy...

> >  What
> > major/minor numbers did you use for it?
> 
> http://git.stlinux.com/?p=havana/com.st.havana.kernel.git;a=blob;f=drivers/serial/stm-asc.h;h=79e003ffeb21df55a6af94774fc9c4b3d8de18e9;hb=HEAD
> 
>   52 #define ASC_MAJOR               204
>   53 #define ASC_MINOR_START         40
> 
> same as in this patch

Ok, but just because you have been using an out-of-tree name, and
non-reserved major/minor, doesn't mean we have to accept it.  As you are
probably using a tool like udev/devtmpfs on your systems, the
major/minor number shouldn't matter, only the name.

And I'd argue that we should change the name as well.

> >> on the DTB SoC you have one one IP present the st,asc
> > 
> > I don't understand, what do you mean by this?
> > 
> > confused,
> 
> just mention there is not hardware reason to not use the generic ttySx
> in place of ttyAS as we have only one IP that handle serial on this
> family of SoC
> 
> personally I'll switch to ttySx

Great, then you can use the same major/minor range as well, so there's
no more objection from me about this :)

thanks,

greg k-h


From cov at codeaurora.org  Wed May  8 12:17:35 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Wed, 08 May 2013 12:17:35 -0400
Subject: [RFC PATCH v2 08/11] ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE
 bits.
In-Reply-To: <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
Message-ID: <518A7A9F.9080105@codeaurora.org>

Hi Steve,

On 05/08/2013 05:52 AM, Steve Capper wrote:
> Under ARM64, PTEs can be broadly categorised as follows:
>    - Present and valid: Bit #0 is set. The PTE is valid and memory
>      access to the region may fault.
> 
>    - Present and invalid: Bit #0 is clear and bit #1 is set.
>      Represents present memory with PROT_NONE protection. The PTE
>      is an invalid entry, and the user fault handler will raise a
>      SIGSEGV.
> 
>    - Not present (file): Bits #0 and #1 are clear, bit #2 is set.
>      Memory represented has been paged out. The PTE is an invalid
>      entry, and the fault handler will try and re-populate the
>      memory where necessary.
> 
> Huge PTEs are block descriptors that have bit #1 clear. If we wish
> to represent PROT_NONE huge PTEs we then run into a problem as
> there is no way to distinguish between regular and huge PTEs if we
> set bit #1.
> 
> As huge PTEs are always present, the meaning of bits #1 and #2 can
> be swapped for invalid PTEs. This patch swaps the PTE_FILE and
> PTE_PROT_NONE constants, allowing us to represent PROT_NONE huge
> PTEs.

[...]

> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h

[...]

> @@ -306,8 +306,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
>  
>  /*
>   * Encode and decode a file entry:
> - *	bits 0-1:	present (must be zero)
> - *	bit  2:		PTE_FILE
> + *	bits 0 & 2:	present (must be zero)

Consider using punctuation like "bits 0, 2" here to disambiguate from the
binary and operation.

[...]

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From arnd at arndb.de  Wed May  8 12:18:01 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 18:18:01 +0200
Subject: [RFC 5/8] ARM:stih41x: Add STiH415 SOC support
In-Reply-To: <1368022297-2334-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022297-2334-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <201305081818.01927.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> 
> The STiH415 is the next generation of HD, AVC set-top box processors for
> satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
> 1.0 GHz, dual-core CPU.
> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> CC: Stephen Gallimore <stephen.gallimore at st.com>
> CC: Stuart Menefy <stuart.menefy at st.com>
> ---
>  Documentation/arm/STiH41x/overview.txt         |   39 ++
>  Documentation/arm/STiH41x/stih415-overview.txt |   12 +
>  arch/arm/Kconfig                               |    3 +
>  arch/arm/Kconfig.debug                         |   38 ++
>  arch/arm/Makefile                              |    2 +
>  arch/arm/boot/dts/stih415-clock.dtsi           |   38 ++
>  arch/arm/boot/dts/stih415-pinctrl.dtsi         |  480 ++++++++++++++++++++++++
>  arch/arm/boot/dts/stih415.dtsi                 |   94 +++++
>  arch/arm/boot/dts/stih415.h                    |   20 +
>  arch/arm/boot/dts/stih41x.dtsi                 |   30 ++
>  arch/arm/boot/dts/stixxxx-pincfg.h             |   95 +++++
>  arch/arm/configs/stih41x_defconfig             |   94 +++++
>  arch/arm/include/debug/stixxxx.S               |   61 +++
>  arch/arm/mach-stih41x/Kconfig                  |   35 ++
>  arch/arm/mach-stih41x/Makefile                 |    4 +
>  arch/arm/mach-stih41x/board-dt.c               |   76 ++++
>  arch/arm/mach-stih41x/stih41x.c                |   82 ++++
>  arch/arm/mach-stih41x/stih41x.h                |    7 +
>  arch/arm/plat-stixxxx/Kconfig                  |    2 +
>  arch/arm/plat-stixxxx/Makefile                 |    2 +
>  arch/arm/plat-stixxxx/headsmp.S                |   44 +++
>  arch/arm/plat-stixxxx/include/plat/hardware.h  |   20 +
>  arch/arm/plat-stixxxx/include/plat/smp.h       |   19 +
>  arch/arm/plat-stixxxx/platsmp.c                |  144 +++++++

I think there is no point in having a separate mach- and plat- directory
here, given that modern machines require very little code. You can probably
fold the three files in mach-stih41x (board-dt.c, stih41x.c and stih41x.h)
into a single file and rename plat-stixxxx to mach-stixxxx

> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 9b31f43..42a5193 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -447,6 +447,16 @@ choice
>  		  This option selects UART0 on VIA/Wondermedia System-on-a-chip
>  		  devices, including VT8500, WM8505, WM8650 and WM8850.
>  
> +	config DEBUG_STIH41X_UART
> +		depends on ARCH_STIH41X
> +		bool "Use StiH415/416 ASC for low-level debug"
> +		help
> +		  Say Y here if you want kernel low-level debugging support
> +		  on StiH415/416 based platforms like B2000, B2020.
> +		  It support UART2 and SBC_UART1.
> +
> +		  If unsure, say N.
> +
>  	config DEBUG_LL_UART_NONE
>  		bool "No low-level debugging UART"
>  		depends on !ARCH_MULTIPLATFORM

I would split out the debug code into a separate patch though.

> @@ -600,6 +637,7 @@ config DEBUG_LL_INCLUDE
>  	default "debug/vt8500.S" if DEBUG_VT8500_UART0
>  	default "debug/tegra.S" if DEBUG_TEGRA_UART
>  	default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
> +	default "debug/stixxxx.S" if DEBUG_STIH41X_UART
>  	default "mach/debug-macro.S"

Please keep this in alphabetical order.

> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		#interrupt-cells = <3>;
> +		interrupt-parent = <&intc>;

The "#interrupt-cells" property doesn't belong here I think.

> +
> +		uart2: uart at fed32000 {
> +			compatible	= "st,asc";
> +			status 		= "disabled";
> +			reg		= <0xfed32000 0x2c>;
> +			interrupts	= <0 197 0>;
> +			pinctrl-names 	= "default";
> +			pinctrl-0 	= <&pinctrl_uart2>;
> +			clocks		= <&CLKS_ICN_REG_0>;
> +		};
> +
> +		/* SBC comms block ASCs in SASG1 */
> +		sbc_uart1: uart at fe531000 {
> +			compatible	= "st,asc";
> +			status 		= "disabled";
> +			reg		= <0xfe531000 0x2c>;
> +			interrupts	= <0 210 0>;
> +			clocks		= <&CLK_SYSIN>;
> +			pinctrl-names 	= "default";
> +			pinctrl-0	= <&pinctrl_sbc_uart1>;
> +		};
> +	};

Please name these devices "serial", not "uart".

> diff --git a/arch/arm/configs/stih41x_defconfig b/arch/arm/configs/stih41x_defconfig
> new file mode 100644
> index 0000000..dd9268b
> --- /dev/null
> +++ b/arch/arm/configs/stih41x_defconfig

I would prefer to have this be part of multi_v7_defconfig, unless
you have strong reason why it can't be.

> diff --git a/arch/arm/mach-stih41x/Kconfig b/arch/arm/mach-stih41x/Kconfig
> new file mode 100644
> index 0000000..9c40540
> --- /dev/null
> +++ b/arch/arm/mach-stih41x/Kconfig
> @@ -0,0 +1,35 @@
> +config ARCH_STIH41X
> +	bool "STMicroelectronics STiH41x SOCs with Flattened Device Tree" if ARCH_MULTI_V7
> +	select GENERIC_CLOCKEVENTS
> +	select CLKDEV_LOOKUP
> +	select ARM_GIC


> +if ARCH_STIH41X
> +menu "STMicroelectronics Consumer Electronics SOCs"

You can use 'menuconfig' to combine these two.

> +static void __init stih41x_timer_init(void)
> +{
> +	of_clk_init(NULL);
> +	clocksource_of_init();
> +	stih41x_l2x0_init();
> +}

I'm hoping we can kill make the clk and l2x0 init work by default in 3.11,
as clocksource_of_init already does, so you won't need this function
any more.

> +/*
> + * A basic implementation of irq_set_wake that ensures wakeup source
> + * interrupts are not disabled during PM_SUSPEND_FREEZE.
> + */
> +static int stih41x_set_wake(struct irq_data *d, unsigned int on)
> +{
> +	struct irq_desc *desc = irq_to_desc(d->irq);
> +
> +	if (on) {
> +		if (desc->action)
> +			desc->action->flags |= IRQF_NO_SUSPEND;
> +	} else {
> +		if (desc->action)
> +			desc->action->flags &= ~IRQF_NO_SUSPEND;
> +	}
> +	return 0;
> +}
> +
> +static void __init stih41x_irq_init(void)
> +{
> +	gic_arch_extn.irq_set_wake = stih41x_set_wake;
> +	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
> +
> +	irqchip_init();
> +}

This looks like it should be generic. Why do you need this?

> +void __init stih41x_dt_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table,
> +				NULL, NULL);
> +	return;
> +}

This is already not needed in 3.10.

> +static struct map_desc stih41x_io_desc[] __initdata = {
> +#ifdef CONFIG_SMP
> +	{
> +		.virtual	= IO_ADDRESS(MPE41_SCU_BASE),
> +		.pfn		= __phys_to_pfn(MPE41_SCU_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	},
> +#endif

> +void __init stih41x_map_io(void)
> +{
> +#ifdef CONFIG_SMP
> +	stixxxx_scu_base_addr = ((void __iomem *)IO_ADDRESS(MPE41_SCU_BASE));
> +#endif
> +	iotable_init(stih41x_io_desc, ARRAY_SIZE(stih41x_io_desc));
> +}

IIRC the SCU no longer needs to be mapped this early, so you can use
ioremap these days.

> +void __init stih41x_l2x0_init(void)
> +{
> +	u32 way_size = 0x4;
> +	u32 aux_ctrl;
> +
> +	aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
> +		(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
> +		(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
> +		(way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
> +
> +	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
> +}

I don't know where we stand on this, but I think we should kill all
calls like these.

	Arnd


From arnd at arndb.de  Wed May  8 12:20:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 18:20:23 +0200
Subject: [RFC 7/8] ARM:stih41x: Add B2000 board support
In-Reply-To: <1368022329-2424-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022329-2424-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <201305081820.23968.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> diff --git a/arch/arm/mach-stih41x/board-dt.c b/arch/arm/mach-stih41x/board-dt.c
> index 8005f71..1f23aca 100644
> --- a/arch/arm/mach-stih41x/board-dt.c
> +++ b/arch/arm/mach-stih41x/board-dt.c
> @@ -63,6 +63,8 @@ void __init stih41x_dt_init(void)
>  }
>  
>  static const char *stih41x_dt_match[] __initdata = {
> +       "st,stih415-b2000",
> +       "st,stih416-b2000",
>         NULL
>  };

I probably wouldn't bother listing all the boards here. Just make sure
the .dts file lists both the name of the board and of the soc in
its compatible property, and list all the SoCs here that you can boot on.

	Arnd


From arnd at arndb.de  Wed May  8 12:23:59 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 18:23:59 +0200
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <518A73CF.8000309@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <20130508144907.GB20820@mudshark.cambridge.arm.com> <518A73CF.8000309@st.com>
Message-ID: <201305081823.59938.arnd@arndb.de>

On Wednesday 08 May 2013, Stuart MENEFY wrote:
> Fortunately the earliest version of these SoCs uses r2p2, so we avoided that
> particular issue. But as the code doesn't attempt to work around these
> problems a check on the version number might be a good idea to prevent other
> people accidentally hitting it.
> 

Yes, good idea. I would put the version number in the compatible property
and document both the working and non-working versions in the binding,
but put a comment explaining the situation into the driver.

	Arnd


From plagnioj at jcrosoft.com  Wed May  8 12:21:21 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 8 May 2013 18:21:21 +0200
Subject: [RFC 5/8] ARM:stih41x: Add STiH415 SOC support
In-Reply-To: <201305081818.01927.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022297-2334-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081818.01927.arnd@arndb.de>
Message-ID: <20130508162121.GD3041@game.jcrosoft.org>

On 18:18 Wed 08 May     , Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> > From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> > 
> > The STiH415 is the next generation of HD, AVC set-top box processors for
> > satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
> > 1.0 GHz, dual-core CPU.
> > 
> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> > CC: Stephen Gallimore <stephen.gallimore at st.com>
> > CC: Stuart Menefy <stuart.menefy at st.com>
> > ---
patch no receive on the ML

please resend

Best Regards,
J.


From plagnioj at jcrosoft.com  Wed May  8 12:24:07 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 8 May 2013 18:24:07 +0200
Subject: [RFC 7/8] ARM:stih41x: Add B2000 board support
In-Reply-To: <201305081820.23968.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022329-2424-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081820.23968.arnd@arndb.de>
Message-ID: <20130508162407.GE3041@game.jcrosoft.org>

On 18:20 Wed 08 May     , Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> > diff --git a/arch/arm/mach-stih41x/board-dt.c b/arch/arm/mach-stih41x/board-dt.c
> > index 8005f71..1f23aca 100644
> > --- a/arch/arm/mach-stih41x/board-dt.c
> > +++ b/arch/arm/mach-stih41x/board-dt.c
> > @@ -63,6 +63,8 @@ void __init stih41x_dt_init(void)
> >  }
> >  
> >  static const char *stih41x_dt_match[] __initdata = {
> > +       "st,stih415-b2000",
> > +       "st,stih416-b2000",
> >         NULL
> >  };
> 
> I probably wouldn't bother listing all the boards here. Just make sure
> the .dts file lists both the name of the board and of the soc in
> its compatible property, and list all the SoCs here that you can boot on.

was going to do the same comment

Best Regards,
J.
> 
> 	Arnd
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From arnd at arndb.de  Wed May  8 12:31:48 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 18:31:48 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508161527.GA28080@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
 <20130508161527.GA28080@kroah.com>
Message-ID: <201305081831.48566.arnd@arndb.de>

On Wednesday 08 May 2013, Greg KH wrote:
> > just mention there is not hardware reason to not use the generic ttySx
> > in place of ttyAS as we have only one IP that handle serial on this
> > family of SoC
> > 
> > personally I'll switch to ttySx
> 
> Great, then you can use the same major/minor range as well, so there's
> no more objection from me about this :)

Does that work these days when you have kernel with multiple built-in
uart drivers?

I think it would be good if all uarts were using the same name space
and major/minor numbers, but I think the mess we currently have is
the result of the tty_register_driver() interface reserving the
device number range at driver load time, independent of the presence
of devices.  I would assume that normal distro kernels always ship
with an 8250 driver built-in to allow using that as the console,
and if I read the code correctly, that currently prevents another
uart driver from registering the same major/minor numbers.

	Arnd


From srinivas.kandagatla at st.com  Wed May  8 12:27:41 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 17:27:41 +0100
Subject: [RFC 4/8] pinctrl:stixxxx: Add pinctrl and pinconf support.
In-Reply-To: <20130508150629.GA3041@game.jcrosoft.org>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022284-2283-1-git-send-email-srinivas.kandagatla@st.com>
 <20130508150629.GA3041@game.jcrosoft.org>
Message-ID: <518A7CFD.1010602@st.com>

Thankyou for the comments.
On 08/05/13 16:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:11 Wed 08 May     , Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>
>> This patch add pinctrl support to ST SoCs.
>>
>> About hardware:
>> ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
>> pin configurations.
>>
>> Each multi-function pin is controlled, driven and routed through the PIO
>> multiplexing block. Each pin supports GPIO functionality (ALT0) and
>> multiple alternate functions(ALT1 - ALTx) that directly connect the pin
>> to different hardware blocks. When a pin is in GPIO mode, Output Enable
>> (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
>> block. Otherwise the PIO multiplexing block configures these parameters
>> and retiming the signal.
>>
> g> About driver:
>> This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
>> pinconf, pinmux, gpio subsystems. All the pinctrl related config
>> information can only come from device trees.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> CC: Stephen Gallimore <stephen.gallimore at st.com>
>> CC: Stuart Menefy <stuart.menefy at st.com>
>> ---
>>  .../bindings/pinctrl/pinctrl-stixxxx.txt           |  160 +++
>>  drivers/pinctrl/Kconfig                            |   13 +
>>  drivers/pinctrl/Makefile                           |    1 +
>>  drivers/pinctrl/pinctrl-stixxxx.c                  | 1151 ++++++++++++++++++++
>>  drivers/pinctrl/pinctrl-stixxxx.h                  |  197 ++++
> the pinctrl is present in older SoC ST40 not only stixxx
>
> and you must provide a proper name not stixxxx
The reason for giving it stixxxx name is all the set-top-box based SOCs
have the naming convention of stixxxx like stih7108, stih415, stih416
and stig125.. and so on..

>>  5 files changed, 1522 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>>  create mode 100644 drivers/pinctrl/pinctrl-stixxxx.c
>>  create mode 100644 drivers/pinctrl/pinctrl-stixxxx.h
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>> new file mode 100644
>> index 0000000..b0a93b5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>> @@ -0,0 +1,160 @@
>> +*ST pin controller.
>> +
>> +Each multi-function pin is controlled, driven and routed through the
>> +PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
>> +and multiple alternate functions(ALT1 - ALTx) that directly connect
>> +the pin to different hardware blocks.
>> +
>> +When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
>> +Pull Up (PU) are driven by the related PIO block.
> HighZ too
>
> this driver look very similar with AT91 we should consolidate at binding and C
> level
Yes, it look very similar to at91, however they are very much different
w.r.t pinconf.
>> ---
>> +
>> +ST pinctrl driver controls PIO multiplexing block and also interacts with
>> +gpio driver to configure a pin.
>> +
>> +Required properties: (PIO multiplexing block)
>> +- compatible	: should be "st,stixxxx-pinctrl"
>> +			each subnode should set "st,stixxxx-gpio"
>> +			as compatible for each gpio-controller bank.
> first soc where the IP is present
>> +- gpio-controller : Indicates this device is a GPIO controller
>> +- #gpio-cells	  : Should be one. The first cell is the pin number.
>> +- #retime-delay-cells	: Should be number of possible retime delays.
>> +- st,retime-in-delay	: Should be array of delays in nsecs.
>> +- st,retime-out-delay	: Should be array of delays in nsecs.
>> +- retime-style		: Should indicate which type of retime is used.
>> +			possible values are "none", "packed" and "dedicated".
> always prefix st, when specific property
> st,
Its a typo, will fix it.
>> +- st,retime-offset	: phandle to retime offsets in retime registers.
>> +		These are not necessary for "dedicated" retime-style registers.
>> +	- clk1notclk0	: Should define offset for clk1not clk0 in retime register.
>> +	- delay-lsb	: Should define offset for delay-lsb in retime register.
>> +	- delay-msb	: Should define offset for delay msb in retime register.
>> +	- invertclk	: Should define offset for invertclk in retime register.
>> +	- retime	: Should define offset for retime in retime register.
>> +	- clknotdata	: Should define offset for clknotdata in retime register.
>> +	- double_edge	: Should define offset for double edge in retime register.
> As much as I like to describe the IP in the DT, I think it's too much this
> time move this to C and use the compatible or detect it on the hardware to
> handle this 
That is a good idea.
>
>> +- st,alt-control		: Should be sysconf to control alternate function on pio.
>> +- st,oe-control		: Should be sysconf to control output enable on pio.
>> +- st,pu-control		: Should be sysconf to control pull up on pio.
>> +- st,od-control		: Should be sysconf to control open drain on pio.
>> +- st,retime-style		: Should indicate which type of retime is used.
>> +			possible values are "none", "packed" and "dedicated".
>> +- st,retime-pin-mask	: Should be mask to specify which pins can be retimed.
>> +- retime-control[0...N]: These properties point to sysconfs which control retime.
>> +			Depending on retime-style the number of retime-controls
>> +			vary: 2 for "packed"; 8 for "dedicated".
>
>> +- st,bank-name		: Should be a name string for this bank.
>> +
>> +Example:
>> +	pio_retime_offset: pio-retime-offset {
>> +		clk1notclk0	= <0>;
>> +		delay-lsb	= <2>;
>> +		delay-msb	= <3>;
>> +		invertclk	= <4>;
>> +		retime		= <5>;
>> +		clknotdata	= <6>;
>> +		double-edge	= <7>;
>> +	};
>> +
>> +	pin-controller {
>> +		#retime-delay-cells = <4>;
>> +		compatible = "st,stixxxx-pinctrl", "simple-bus";
>> +		st,retime-offset = <&pio_retime_offset>;
>> +		st,retime-in-delay = <0 500 1000 1500>;
>> +		st,retime-out-delay = <0 1000 2000 3000>;
>> +		ranges;
>> +		PIO0: pinctrl at fe610000 {
>> +			gpio-controller;
>> +			#gpio-cells = <1>;
>> +			compatible = "st,stixxxx-gpio";
>> +			reg = <0xfe610000 0x100>;
>> +			st,bank-name  = "PIO0";
>> +			st,alt-control = <&SYSCONF_SBC(0) 0 31>;
>> +			st,oe-control = <&SYSCONF_SBC(5)  0 7>;
>> +			st,pu-control = <&SYSCONF_SBC(7)  0 7>;
>> +			st,od-control = <&SYSCONF_SBC(9)  0 7>;
>> +			st,retime-style = "packed";
>> +			st,retime-pin-mask = <0xff>;
>> +			st,retime-control0 = <&SYSCONF_SBC(16) 0 31>;
>> +			st,retime-control1 = <&SYSCONF_SBC(17) 0 31>;
>> +		};
>> +		...
>> +		pin-functions nodes follow...
>> +	};
>> +
>> +
>> +Contents of function subnode node:
>> +----------------------
>> +Required properties for pin configuration node:
>> +- st,function	: Should be alternate function number associated
>> +		with this set of pins.
>> +		possible altfunction values:
>> +		ALT1
>> +		ALT2
>> +		ALT3
>> +		ALT4
>> +		ALT5
>> +		ALT6
>> +		ALT7
> use number in the DoC
Ok.
>
>> +
>> +- st,pins	: Child node with list of pins with configuration.
>> +
>> +Below is the format of how each pin conf should look like.
>> +
>> +<bank offset mode rt_type rt_delay rt_clk>
>> +
>> +Every PIO is represented with 4-7 parameters depending on retime configuration.
>> +Each parameter is explained as below.
>> +
>> +-bank		: Should be bank phandle to which this PIO belongs.
>> +-offset		: Offset in the PIO bank.
>> +-mode		:pin configuration is selected from one of the below values.
>> +		IN
>> +		IN_PU
>> +		OUT
>> +		BIDIR
>> +		BIDIR_PU
> ditto
Actually these modes are top level defines of three different variables,
OE, PU, OD used in the registers.
Its very common that driver might just be interested in one of listed modes.
>> +
>> +-rt_type	Retiming Configuration for the pin.
>> +		Possible retime configuration are:
>> +
>> +		-------		-------------
>> +		value		args
>> +		-------		-------------
>> +		NICLK		<delay> <clk>
>> +		ICLK_IO		<delay> <clk>
>> +		BYPASS		<delay>
>> +		DE_IO		<delay> <clk>
>> +		SE_ICLK_IO	<delay> <clk>
>> +		SE_NICLK_IO	<delay> <clk>
>> +
>> +- delay	is retime delay in pico seconds.
>> +		Possible values are: refer to retime-in/out-delays
>> +
>> +- rt_clk	:clk to be use for retime.
>> +		Possible values are:
>> +		CLK_A
>> +		CLK_B
>> +		CLK_C
>> +		CLK_D
>> +
>> +Example of mmcclk pin which is a bi-direction pull pu with retime config
>> +as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
>> +
>> +pin-controller {
>> +	...
>> +	mmc0 {
>> +		pinctrl_mmc: mmc {
>> +			st,function = <ALT4>;
>> +			st,pins {
>> +				mmcclk = <&PIO13 4 BIDIR_PU NICLK  0  CLK_B>;
>> +				...
>> +			};
>> +		};
>> +	...
>> +	};
>> +};
>> +
>> +sdhci0:sdhci at fe810000{
>> +	...
>> +	pinctrl-names = "default";
>> +	pinctrl-0	= <&pinctrl_mmc>;
>> +};
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index 34f51d2..611a399 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -179,6 +179,19 @@ config PINCTRL_SUNXI
>>  	select PINMUX
>>  	select GENERIC_PINCONF
>>  
>> +config PINCTRL_STIXXXX
>> +	bool "ST Microelectronics pin controller driver for STixxxx SoCs"
>> +	depends on PLAT_STIXXXX
>> +	select PINMUX
>> +	select PINCONF
>> +	select MFD_SYSCON
>> +	help
>> +	  Say yes here to support pinctrl interface on STixxxx SOCs.
>> +	  This driver is used to control both PIO block and PIO-mux
>> +	  block to configure a pin.
>> +
>> +	  If unsure, say N.
>> +
>>  config PINCTRL_TEGRA
>>  	bool
>>  	select PINMUX
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index f82cc5b..99a2c78 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS)	+= pinctrl-exynos.o
>>  obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
>>  obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
>>  obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
>> +obj-$(CONFIG_PINCTRL_STIXXXX) 	+= pinctrl-stixxxx.o
>>  
>>  obj-$(CONFIG_PLAT_ORION)        += mvebu/
>>  obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
>> diff --git a/drivers/pinctrl/pinctrl-stixxxx.c b/drivers/pinctrl/pinctrl-stixxxx.c
>> new file mode 100644
>> index 0000000..7d2c59c
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-stixxxx.c
>> @@ -0,0 +1,1151 @@
>> +/*
>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
>> + * Authors:
>> + *	Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_gpio.h>
>> +#include <linux/of_address.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +#include <linux/pinctrl/pinmux.h>
>> +#include <linux/pinctrl/pinconf.h>
>> +#include <linux/platform_device.h>
>> +#include "core.h"
>> +#include "pinctrl-stixxxx.h"
>> +
>> +struct stixxxx_pinconf {
>> +	int		pin;
>> +	const char	*name;
>> +	unsigned long	config;
>> +};
>> +
>> +struct stixxxx_pmx_func {
>> +	const char	*name;
>> +	const char	**groups;
>> +	unsigned	ngroups;
>> +};
>> +
>> +struct stixxxx_pctl_group {
>> +	const char		*name;
>> +	unsigned int		*pins;
>> +	unsigned		npins;
>> +	int			altfunc;
>> +	struct stixxxx_pinconf	*pin_conf;
>> +};
>> +
>> +#define to_stixxxx_gpio_port(chip) \
>> +		container_of(chip, struct stixxxx_gpio_port, gpio_chip)
>> +
>> +struct stixxxx_gpio_port {
>> +	struct gpio_chip	gpio_chip;
>> +	struct pinctrl_gpio_range range;
>> +	void __iomem		*base;
>> +	struct device_node	*of_node;
>> +	const char		*bank_name;
>> +};
>> +
>> +static struct stixxxx_gpio_port *gpio_ports[STIXXXX_MAX_GPIO_BANKS];
>> +
>> +struct stixxxx_pinctrl {
>> +	struct device			*dev;
>> +	struct pinctrl_dev		*pctl;
>> +	int				nbanks;
>> +	struct stixxxx_pmx_func		*functions;
>> +	int				nfunctions;
>> +	struct stixxxx_pctl_group	*groups;
>> +	int				ngroups;
>> +	struct stixxxx_pio_control	*pio_controls;
>> +};
>> +
>> +/* Low level functions.. */
>> +static void stixxxx_pinconf_set_direction(struct stixxxx_pio_control *pc,
>> +				int pin_id, unsigned long config)
>> +{
>> +	struct syscon_field *output_enable;
>> +	struct syscon_field *pull_up;
>> +	struct syscon_field *open_drain;
>> +	unsigned long oe_value, pu_value, od_value;
>> +	unsigned long mask;
>> +	int pin = stixxxx_gpio_pin(pin_id);
>> +
>> +	output_enable = pc->oe;
>> +	pull_up = pc->pu;
>> +	open_drain = pc->od;
>> +
>> +	mask = BIT(pin);
>> +
>> +	oe_value = syscon_read(output_enable);
>> +	pu_value = syscon_read(pull_up);
>> +	od_value = syscon_read(open_drain);
>> +
>> +	/* Clear old values */
>> +	oe_value &= ~mask;
>> +	pu_value &= ~mask;
>> +	od_value &= ~mask;
>> +
>> +	if (config & STIXXXX_PINCONF_OE)
>> +		oe_value |= mask;
>> +	if (config & STIXXXX_PINCONF_PU)
>> +		pu_value |= mask;
>> +	if (config & STIXXXX_PINCONF_OD)
>> +		od_value |= mask;
>> +
>> +	syscon_write(output_enable, oe_value);
>> +	syscon_write(pull_up, pu_value);
>> +	syscon_write(open_drain, od_value);
>> +}
>> +
>> +static void stixxxx_pctl_set_function(struct stixxxx_pio_control *pc,
>> +				int pin_id, int function)
>> +{
>> +	struct syscon_field *selector;
>> +	int offset;
>> +	unsigned long val;
>> +	int pin = stixxxx_gpio_pin(pin_id);
>> +
>> +	selector = pc->alt;
>> +	offset = pin * 4;
>> +	val = syscon_read(selector);
>> +	val &= ~(0xf << offset);
>> +	val |= function << offset;
>> +	syscon_write(selector, val);
>> +}
>> +
>> +static unsigned long stixxxx_pinconf_delay_to_bit(unsigned int delay,
>> +		const struct stixxxx_retime_params *rt_params,
>> +		unsigned long config)
>> +{
>> +	unsigned int *delay_times;
>> +	int num_delay_times, i, closest_index = -1;
>> +	unsigned int closest_divergence = UINT_MAX;
>> +
>> +	if (STIXXXX_PINCONF_UNPACK_OE(config)) {
>> +		delay_times = rt_params->delay_times_out;
>> +		num_delay_times = rt_params->num_delay_times_out;
>> +	} else {
>> +		delay_times = rt_params->delay_times_in;
>> +		num_delay_times = rt_params->num_delay_times_in;
>> +	}
>> +
>> +	for (i = 0; i < num_delay_times; i++) {
>> +		unsigned int divergence = abs(delay - delay_times[i]);
>> +
>> +		if (divergence == 0)
>> +			return i;
>> +
>> +		if (divergence < closest_divergence) {
>> +			closest_divergence = divergence;
>> +			closest_index = i;
>> +		}
>> +	}
>> +
>> +	pr_warn("Attempt to set delay %d, closest available %d\n",
>> +	     delay, delay_times[closest_index]);
>> +
>> +	return closest_index;
>> +}
>> +
>> +static unsigned long stixxxx_pinconf_bit_to_delay(unsigned int index,
>> +		const struct stixxxx_retime_params *rt_params,
>> +		unsigned long output)
>> +{
>> +	unsigned int *delay_times;
>> +	int num_delay_times;
>> +
>> +	if (output) {
>> +		delay_times = rt_params->delay_times_out;
>> +		num_delay_times = rt_params->num_delay_times_out;
>> +	} else {
>> +		delay_times = rt_params->delay_times_in;
>> +		num_delay_times = rt_params->num_delay_times_in;
>> +	}
>> +
>> +	if (index < num_delay_times) {
>> +		return delay_times[index];
>> +	} else {
>> +		pr_warn("Delay not found in/out delay list\n");
>> +		return 0;
>> +	}
>> +}
>> +
>> +static void stixxxx_pinconf_set_retime_packed(
>> +		struct stixxxx_pio_control *pc,
>> +		unsigned long config, int pin)
>> +{
>> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
>> +	const struct stixxxx_retime_offset *offset = rt_params->retime_offset;
>> +	struct syscon_field **regs;
>> +	unsigned long values[2];
>> +	unsigned long mask;
>> +	int i, j;
>> +	int clk = STIXXXX_PINCONF_UNPACK_RT_CLK(config);
>> +	int clknotdata = STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config);
>> +	int double_edge = STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
>> +	int invertclk = STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config);
>> +	int retime = STIXXXX_PINCONF_UNPACK_RT(config);
>> +	unsigned long delay = stixxxx_pinconf_delay_to_bit(
>> +			STIXXXX_PINCONF_UNPACK_RT_DELAY(config),
>> +			pc->rt_params, config);
>> +
>> +	unsigned long rt_cfg =
>> +		((clk		& 1) << offset->clk1notclk0_offset) |
>> +		((clknotdata	& 1) << offset->clknotdata_offset) |
>> +		((delay		& 1) << offset->delay_lsb_offset) |
>> +		(((delay >> 1)  & 1) << offset->delay_msb_offset) |
>> +		((double_edge	& 1) << offset->double_edge_offset) |
>> +		((invertclk	& 1) << offset->invertclk_offset) |
>> +		((retime	& 1) << offset->retime_offset);
>> +
>> +	regs = pc->retiming;
>> +	values[0] = syscon_read(regs[0]);
>> +	values[1] = syscon_read(regs[1]);
>> +
>> +	for (i = 0; i < 2; i++) {
>> +		mask = BIT(pin);
>> +		for (j = 0; j < 4; j++) {
>> +			if (rt_cfg & 1)
>> +				values[i] |= mask;
>> +			else
>> +				values[i] &= ~mask;
>> +			mask <<= 8;
>> +			rt_cfg >>= 1;
>> +		}
>> +	}
>> +
>> +	syscon_write(regs[0], values[0]);
>> +	syscon_write(regs[1], values[1]);
>> +}
>> +
>> +static void stixxxx_pinconf_set_retime_dedicated(
>> +	struct stixxxx_pio_control *pc,
>> +	unsigned long config, int pin)
>> +{
>> +	struct syscon_field *reg;
>> +	int input = STIXXXX_PINCONF_UNPACK_OE(config) ? 0 : 1;
>> +	int clk = STIXXXX_PINCONF_UNPACK_RT_CLK(config);
>> +	int clknotdata = STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config);
>> +	int double_edge = STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
>> +	int invertclk = STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config);
>> +	int retime = STIXXXX_PINCONF_UNPACK_RT(config);
>> +	unsigned long delay = stixxxx_pinconf_delay_to_bit(
>> +			STIXXXX_PINCONF_UNPACK_RT_DELAY(config),
>> +			pc->rt_params, config);
>> +
>> +	unsigned long retime_config =
>> +		((clk		& 0x3) << 0) |
>> +		((clknotdata	& 0x1) << 2) |
>> +		((delay		& 0xf) << 3) |
>> +		((input		& 0x1) << 7) |
>> +		((double_edge	& 0x1) << 8) |
>> +		((invertclk	& 0x1) << 9) |
>> +		((retime	& 0x1) << 10);
>> +
>> +	reg = pc->retiming[pin];
>> +	syscon_write(reg, retime_config);
>> +}
>> +
>> +static void stixxxx_pinconf_get_direction(struct stixxxx_pio_control *pc,
>> +	int pin_id, unsigned long *config)
>> +{
>> +	unsigned long oe_value, pu_value, od_value;
>> +	int pin = stixxxx_gpio_pin(pin_id);
>> +
>> +	oe_value = (syscon_read(pc->oe) >> pin) & 1;
>> +	pu_value = (syscon_read(pc->pu) >> pin) & 1;
>> +	od_value = (syscon_read(pc->od) >> pin) & 1;
>> +
>> +	STIXXXX_PINCONF_PACK_OE(*config, oe_value);
>> +	STIXXXX_PINCONF_PACK_PU(*config, pu_value);
>> +	STIXXXX_PINCONF_PACK_OD(*config, od_value);
>> +}
>> +
>> +static int stixxxx_pinconf_get_retime_packed(
>> +		struct stixxxx_pio_control *pc,
>> +		int pin, unsigned long *config)
>> +{
>> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
>> +	const struct stixxxx_retime_offset *offset = rt_params->retime_offset;
>> +	unsigned long delay_bits, delay, rt_reduced;
>> +	unsigned long rt_value[2];
>> +	int i, j;
>> +	int output = STIXXXX_PINCONF_UNPACK_OE(*config);
>> +
>> +	rt_value[0] = syscon_read(pc->retiming[0]);
>> +	rt_value[1] = syscon_read(pc->retiming[1]);
>> +
>> +	rt_reduced = 0;
>> +	for (i = 0; i < 2; i++) {
>> +		for (j = 0; j < 4; j++) {
>> +			if (rt_value[i] & (1<<((8*j)+pin)))
>> +				rt_reduced |= 1 << ((i*4)+j);
>> +		}
>> +	}
>> +
>> +	STIXXXX_PINCONF_PACK_RT(*config,
>> +			(rt_reduced >> offset->retime_offset) & 1);
>> +	STIXXXX_PINCONF_PACK_RT_CLK(*config,
>> +			(rt_reduced >> offset->clk1notclk0_offset) & 1);
>> +	STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(*config,
>> +			(rt_reduced >> offset->clknotdata_offset) & 1);
>> +	STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(*config,
>> +			(rt_reduced >> offset->double_edge_offset) & 1);
>> +	STIXXXX_PINCONF_PACK_RT_INVERTCLK(*config,
>> +			(rt_reduced >> offset->invertclk_offset) & 1);
>> +
>> +	delay_bits =  (((rt_reduced >> offset->delay_msb_offset) & 1)<<1) |
>> +			((rt_reduced >> offset->delay_lsb_offset) & 1);
>> +	delay =  stixxxx_pinconf_bit_to_delay(delay_bits, rt_params, output);
>> +	STIXXXX_PINCONF_PACK_RT_DELAY(*config, delay);
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_pinconf_get_retime_dedicated(
>> +		struct stixxxx_pio_control *pc,
>> +		int pin, unsigned long *config)
>> +{
>> +	unsigned long value;
>> +	unsigned long delay_bits, delay;
>> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
>> +	int output = STIXXXX_PINCONF_UNPACK_OE(*config);
>> +
>> +	value = syscon_read(pc->retiming[pin]);
>> +	STIXXXX_PINCONF_PACK_RT_CLK(*config, ((value >> 0) & 0x3));
>> +	STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(*config, ((value >> 2) & 0x1));
>> +	delay_bits = ((value >> 3) & 0xf);
>> +	delay =  stixxxx_pinconf_bit_to_delay(delay_bits, rt_params, output);
>> +	STIXXXX_PINCONF_PACK_RT_DELAY(*config, delay);
>> +	STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(*config, ((value >> 8) & 0x1));
>> +	STIXXXX_PINCONF_PACK_RT_INVERTCLK(*config, ((value >> 9) & 0x1));
>> +	STIXXXX_PINCONF_PACK_RT(*config, ((value >> 10) & 0x1));
>> +
>> +	return 0;
>> +}
>> +
>> +/* GPIO related functions */
>> +
>> +static inline void __stixxxx_gpio_set(struct stixxxx_gpio_port *port,
>> +	unsigned offset, int value)
>> +{
>> +	if (value)
>> +		writel(BIT(offset), port->base + REG_PIO_SET_POUT);
>> +	else
>> +		writel(BIT(offset), port->base + REG_PIO_CLR_POUT);
>> +}
>> +
>> +static void stixxxx_gpio_direction(unsigned int gpio, unsigned int direction)
>> +{
>> +	int port_num = stixxxx_gpio_port(gpio);
>> +	int offset = stixxxx_gpio_pin(gpio);
>> +	struct stixxxx_gpio_port *port  = gpio_ports[port_num];
>> +	int i = 0;
>> +
>> +	for (i = 0; i <= 2; i++) {
>> +		if (direction & BIT(i))
>> +			writel(BIT(offset), port->base + REG_PIO_SET_PC(i));
>> +		else
>> +			writel(BIT(offset), port->base + REG_PIO_CLR_PC(i));
>> +	}
>> +}
>> +
>> +static int stixxxx_gpio_request(struct gpio_chip *chip, unsigned offset)
>> +{
>> +	return pinctrl_request_gpio(chip->base + offset);
>> +}
>> +
>> +static void stixxxx_gpio_free(struct gpio_chip *chip, unsigned offset)
>> +{
>> +	pinctrl_free_gpio(chip->base + offset);
>> +}
>> +
>> +static int stixxxx_gpio_get(struct gpio_chip *chip, unsigned offset)
>> +{
>> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
>> +
>> +	return (readl(port->base + REG_PIO_PIN) >> offset) & 1;
>> +}
>> +
>> +static void stixxxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
>> +{
>> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
>> +	__stixxxx_gpio_set(port, offset, value);
>> +}
>> +
>> +static int stixxxx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
>> +{
>> +	pinctrl_gpio_direction_input(chip->base + offset);
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_gpio_direction_output(struct gpio_chip *chip,
>> +	unsigned offset, int value)
>> +{
>> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
>> +
>> +	__stixxxx_gpio_set(port, offset, value);
>> +	pinctrl_gpio_direction_output(chip->base + offset);
>> +
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_gpio_xlate(struct gpio_chip *gc,
>> +			const struct of_phandle_args *gpiospec, u32 *flags)
>> +{
>> +	if (WARN_ON(gc->of_gpio_n_cells < 1))
>> +		return -EINVAL;
>> +
>> +	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
>> +		return -EINVAL;
>> +
>> +	if (gpiospec->args[0] > gc->ngpio)
>> +		return -EINVAL;
>> +
>> +	return gpiospec->args[0];
>> +}
>> +
>> +/* Pinctrl Groups */
>> +static int stixxxx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +
>> +	return info->ngroups;
>> +}
>> +
>> +static const char *stixxxx_pctl_get_group_name(struct pinctrl_dev *pctldev,
>> +				       unsigned selector)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +
>> +	return info->groups[selector].name;
>> +}
>> +
>> +static int stixxxx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
>> +	unsigned selector, const unsigned **pins, unsigned *npins)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +
>> +	if (selector >= info->ngroups)
>> +		return -EINVAL;
>> +
>> +	*pins = info->groups[selector].pins;
>> +	*npins = info->groups[selector].npins;
>> +
>> +	return 0;
>> +}
>> +
>> +static const inline struct stixxxx_pctl_group *stixxxx_pctl_find_group_by_name(
>> +	const struct stixxxx_pinctrl *info, const char *name)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < info->ngroups; i++) {
>> +		if (!strcmp(info->groups[i].name, name))
>> +			return &info->groups[i];
>> +	}
>> +
>> +	return NULL;
>> +}
>> +
>> +static int stixxxx_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
>> +	struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +	const struct stixxxx_pctl_group *grp;
>> +	struct pinctrl_map *new_map;
>> +	struct device_node *parent;
>> +	int map_num, i;
>> +
>> +	grp = stixxxx_pctl_find_group_by_name(info, np->name);
>> +	if (!grp) {
>> +		dev_err(info->dev, "unable to find group for node %s\n",
>> +			np->name);
>> +		return -EINVAL;
>> +	}
>> +
>> +	map_num = grp->npins + 1;
>> +	new_map = devm_kzalloc(pctldev->dev,
>> +				sizeof(*new_map) * map_num, GFP_KERNEL);
>> +	if (!new_map)
>> +		return -ENOMEM;
>> +
>> +	parent = of_get_parent(np);
>> +	if (!parent) {
>> +		devm_kfree(pctldev->dev, new_map);
>> +		return -EINVAL;
>> +	}
>> +
>> +	*map = new_map;
>> +	*num_maps = map_num;
>> +	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
>> +	new_map[0].data.mux.function = parent->name;
>> +	new_map[0].data.mux.group = np->name;
>> +	of_node_put(parent);
>> +
>> +	/* create config map per pin */
>> +	new_map++;
>> +	for (i = 0; i < grp->npins; i++) {
>> +		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
>> +		new_map[i].data.configs.group_or_pin =
>> +				pin_get_name(pctldev, grp->pins[i]);
>> +		new_map[i].data.configs.configs = &grp->pin_conf[i].config;
>> +		new_map[i].data.configs.num_configs = 1;
>> +	}
>> +	dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
>> +		(*map)->data.mux.function, grp->name, map_num);
>> +
>> +	return 0;
>> +}
>> +
>> +static void stixxxx_pctl_dt_free_map(struct pinctrl_dev *pctldev,
>> +				struct pinctrl_map *map, unsigned num_maps)
>> +{
>> +}
>> +
>> +static struct pinctrl_ops stixxxx_pctlops = {
>> +	.get_groups_count	= stixxxx_pctl_get_groups_count,
>> +	.get_group_pins		= stixxxx_pctl_get_group_pins,
>> +	.get_group_name		= stixxxx_pctl_get_group_name,
>> +	.dt_node_to_map		= stixxxx_pctl_dt_node_to_map,
>> +	.dt_free_map		= stixxxx_pctl_dt_free_map,
>> +};
>> +
>> +/* Pinmux */
>> +static int stixxxx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +
>> +	return info->nfunctions;
>> +}
>> +
>> +const char *stixxxx_pmx_get_fname(struct pinctrl_dev *pctldev,
>> +	unsigned selector)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +
>> +	return info->functions[selector].name;
>> +}
>> +
>> +static int stixxxx_pmx_get_groups(struct pinctrl_dev *pctldev,
>> +	unsigned selector, const char * const **grps, unsigned * const ngrps)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +	*grps = info->functions[selector].groups;
>> +	*ngrps = info->functions[selector].ngroups;
>> +
>> +	return 0;
>> +}
>> +
>> +static struct stixxxx_pio_control *stixxxx_get_pio_control(
>> +			struct stixxxx_pinctrl *info, int pin_id)
>> +{
>> +	int port = stixxxx_gpio_port(pin_id);
>> +	return &info->pio_controls[port];
>> +}
>> +
>> +static int stixxxx_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
>> +		unsigned group)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +	struct stixxxx_pinconf *conf = info->groups[group].pin_conf;
>> +	struct stixxxx_pio_control *pc;
>> +	int i;
>> +
>> +	for (i = 0; i < info->groups[group].npins; i++) {
>> +		pc = stixxxx_get_pio_control(info, conf[i].pin);
>> +		stixxxx_pctl_set_function(pc, conf[i].pin,
>> +					info->groups[group].altfunc);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void stixxxx_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
>> +		unsigned group)
>> +{
>> +}
>> +
>> +static int stixxxx_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
>> +			struct pinctrl_gpio_range *range, unsigned gpio,
>> +			bool input)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +	struct stixxxx_pio_control *pc = &info->pio_controls[range->id];
>> +	/*
>> +	 * When a PIO port is used in its primary function mode (altfunc = 0)
>> +	 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
>> +	 * for the primary PIO functions are driven by the related PIO block
>> +	 */
>> +	stixxxx_pctl_set_function(pc, gpio, 0);
>> +	stixxxx_gpio_direction(gpio, input ?
>> +		STIXXXX_GPIO_DIRECTION_IN : STIXXXX_GPIO_DIRECTION_OUT);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct pinmux_ops stixxxx_pmxops = {
>> +	.get_functions_count	= stixxxx_pmx_get_funcs_count,
>> +	.get_function_name	= stixxxx_pmx_get_fname,
>> +	.get_function_groups	= stixxxx_pmx_get_groups,
>> +	.enable			= stixxxx_pmx_enable,
>> +	.disable		= stixxxx_pmx_disable,
>> +	.gpio_set_direction	= stixxxx_pmx_set_gpio_direction,
>> +};
>> +
>> +/* Pinconf  */
>> +static void stixxxx_pinconf_get_retime(struct stixxxx_pio_control *pc,
>> +	int pin_id, unsigned long *config)
>> +{
>> +	int pin = stixxxx_gpio_pin(pin_id);
>> +	if (pc->rt_style == stixxxx_retime_style_packed)
>> +		stixxxx_pinconf_get_retime_packed(pc, pin, config);
>> +	else if (pc->rt_style == stixxxx_retime_style_dedicated)
>> +		if ((BIT(pin) & pc->rt_pin_mask))
>> +			stixxxx_pinconf_get_retime_dedicated(pc, pin, config);
>> +}
>> +
>> +static void stixxxx_pinconf_set_retime(struct stixxxx_pio_control *pc,
>> +	int pin_id, unsigned long config)
>> +{
>> +	int pin = stixxxx_gpio_pin(pin_id);
>> +
>> +	if (pc->rt_style == stixxxx_retime_style_packed)
>> +		stixxxx_pinconf_set_retime_packed(pc, config, pin);
>> +	else if (pc->rt_style == stixxxx_retime_style_dedicated)
>> +		if ((BIT(pin) & pc->rt_pin_mask))
>> +			stixxxx_pinconf_set_retime_dedicated(pc, config, pin);
>> +}
>> +
>> +static int stixxxx_pinconf_set(struct pinctrl_dev *pctldev,
>> +			     unsigned pin_id, unsigned long config)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +	struct stixxxx_pio_control *pc = stixxxx_get_pio_control(info, pin_id);
>> +
>> +	stixxxx_pinconf_set_direction(pc, pin_id, config);
>> +	stixxxx_pinconf_set_retime(pc, pin_id, config);
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_pinconf_get(struct pinctrl_dev *pctldev,
>> +			     unsigned pin_id, unsigned long *config)
>> +{
>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>> +	struct stixxxx_pio_control *pc = stixxxx_get_pio_control(info, pin_id);
>> +
>> +	*config = 0;
>> +	stixxxx_pinconf_get_direction(pc, pin_id, config);
>> +	stixxxx_pinconf_get_retime(pc, pin_id, config);
>> +
>> +	return 0;
>> +}
>> +
>> +static void stixxxx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>> +				   struct seq_file *s, unsigned pin_id)
>> +{
>> +	unsigned long config;
>> +	stixxxx_pinconf_get(pctldev, pin_id, &config);
>> +
>> +	seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n"
>> +		"\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
>> +		"de:%ld,rt-clk:%ld,rt-delay:%ld]",
>> +		STIXXXX_PINCONF_UNPACK_OE(config),
>> +		STIXXXX_PINCONF_UNPACK_PU(config),
>> +		STIXXXX_PINCONF_UNPACK_OD(config),
>> +		STIXXXX_PINCONF_UNPACK_RT(config),
>> +		STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config),
>> +		STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config),
>> +		STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
>> +		STIXXXX_PINCONF_UNPACK_RT_CLK(config),
>> +		STIXXXX_PINCONF_UNPACK_RT_DELAY(config));
>> +}
>> +
>> +static struct pinconf_ops stixxxx_confops = {
>> +	.pin_config_get		= stixxxx_pinconf_get,
>> +	.pin_config_set		= stixxxx_pinconf_set,
>> +	.pin_config_dbg_show	= stixxxx_pinconf_dbg_show,
>> +};
>> +
>> +/* pinctrl */
>> +static struct pinctrl_desc stixxxx_pctl_desc = {
>> +	.owner		= THIS_MODULE,
>> +	.pctlops	= &stixxxx_pctlops,
>> +	.pmxops		= &stixxxx_pmxops,
>> +	.confops	= &stixxxx_confops,
>> +};
>> +
>> +static int stixxxx_pinconf_dt_parse_rt_params(struct stixxxx_pinctrl *info,
>> +	struct device_node *np,	struct stixxxx_retime_params *params)
>> +{
>> +	const __be32 *ip;
>> +	struct device_node *offset_np;
>> +	struct stixxxx_retime_offset *rt_offset;
>> +	int delay_count = 0;
>> +
>> +	ip = of_get_property(np, "#retime-delay-cells", NULL);
>> +	if (ip)
>> +		delay_count = be32_to_cpup(ip);
>> +	else
>> +		pr_warn("No #retime-delay-cells specified\n");
>> +
>> +	params->num_delay_times_out = delay_count;
>> +	params->num_delay_times_in = delay_count;
>> +	params->delay_times_in = devm_kzalloc(info->dev,
>> +				sizeof(u32) * delay_count, GFP_KERNEL);
>> +	params->delay_times_out = devm_kzalloc(info->dev,
>> +				sizeof(u32) * delay_count, GFP_KERNEL);
>> +
>> +	if (!params->delay_times_in || !params->delay_times_out)
>> +		return -ENOMEM;
>> +
>> +	of_property_read_u32_array(np, "st,retime-in-delay",
>> +				(u32 *)params->delay_times_in, delay_count);
>> +	of_property_read_u32_array(np, "st,retime-out-delay",
>> +				(u32 *)params->delay_times_out, delay_count);
>> +
>> +	offset_np = of_parse_phandle(np, "st,retime-offset", 0);
>> +
>> +	if (offset_np) {
>> +		rt_offset = devm_kzalloc(info->dev,
>> +				sizeof(*rt_offset), GFP_KERNEL);
>> +		if (!rt_offset)
>> +			return -ENOMEM;
>> +
>> +		params->retime_offset = rt_offset;
>> +		WARN_ON(of_property_read_u32(offset_np, "retime",
>> +					&rt_offset->retime_offset));
>> +		WARN_ON(of_property_read_u32(offset_np, "clk1notclk0",
>> +					&rt_offset->clk1notclk0_offset));
>> +		WARN_ON(of_property_read_u32(offset_np, "clknotdata",
>> +					&rt_offset->clknotdata_offset));
>> +		WARN_ON(of_property_read_u32(offset_np, "double-edge",
>> +					&rt_offset->double_edge_offset));
>> +		WARN_ON(of_property_read_u32(offset_np, "invertclk",
>> +					&rt_offset->invertclk_offset));
>> +		WARN_ON(of_property_read_u32(offset_np, "delay-lsb",
>> +					&rt_offset->delay_lsb_offset));
>> +		WARN_ON(of_property_read_u32(offset_np, "delay-msb",
>> +					&rt_offset->delay_msb_offset));
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static const char *gpio_compat = "st,stixxxx-gpio";
>> +
>> +static void stixxxx_pctl_dt_child_count(struct stixxxx_pinctrl *info,
>> +				     struct device_node *np)
>> +{
>> +	struct device_node *child;
>> +	for_each_child_of_node(np, child) {
>> +		if (of_device_is_compatible(child, gpio_compat)) {
>> +			info->nbanks++;
>> +		} else {
>> +			info->nfunctions++;
>> +			info->ngroups += of_get_child_count(child);
>> +		}
>> +	}
>> +}
>> +
>> +static int stixxxx_pctl_dt_get_retime_conf(struct device_node *np,
>> +	struct stixxxx_pio_control *pc)
>> +{
>> +	const char *style;
>> +	char name[20];
>> +	unsigned int j;
>> +	of_property_read_string(np, "st,retime-style", &style);
>> +
>> +	if (strcmp(style, "packed") == 0) {
>> +		pc->rt_style = stixxxx_retime_style_packed;
>> +		for (j = 0; j < 2; j++) {
>> +			snprintf(name, sizeof(name), "st,retime-control%d", j);
>> +			pc->retiming[j] = syscon_claim(np, name);
>> +			if (!pc->retiming[j])
>> +				return -ENODATA;
>> +		}
>> +	} else if (strcmp(style, "dedicated") == 0) {
>> +		pc->rt_style = stixxxx_retime_style_dedicated;
>> +		for (j = 0; j < 8; j++) {
>> +			if ((1<<j) & pc->rt_pin_mask) {
>> +				snprintf(name, sizeof(name),
>> +						"st,retime-control%d", j);
>> +				pc->retiming[j] = syscon_claim(np, name);
>> +				if (!pc->retiming[j])
>> +					return -ENODATA;
>> +			}
>> +		}
>> +	} else if (strcmp(style, "none") == 0) {
>> +		pc->rt_style = stixxxx_retime_style_none;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_pctl_dt_init(struct stixxxx_pinctrl *info,
>> +			struct device_node *np)
>> +{
>> +	struct stixxxx_pio_control *pc;
>> +	struct stixxxx_retime_params *rt_params;
>> +	struct device *dev = info->dev;
>> +	unsigned int i = 0;
>> +	struct device_node *child = NULL;
>> +
>> +	pc = devm_kzalloc(dev, sizeof(*pc) * info->nbanks, GFP_KERNEL);
>> +	rt_params = devm_kzalloc(dev, sizeof(*rt_params), GFP_KERNEL);
>> +
>> +	if (!pc || !rt_params)
>> +		return -ENOMEM;
>> +
>> +	info->pio_controls = pc;
>> +	if (stixxxx_pinconf_dt_parse_rt_params(info, np, rt_params))
>> +		return -ENOMEM;
>> +
>> +	for_each_child_of_node(np, child) {
>> +		if (of_device_is_compatible(child, gpio_compat)) {
>> +			pc[i].rt_params = rt_params;
>> +
>> +			pc[i].alt = syscon_claim(child, "st,alt-control");
>> +			if (!pc[i].alt)
>> +				goto failed;
>> +
>> +			pc[i].oe = syscon_claim(child, "st,oe-control");
>> +			if (!pc[i].oe)
>> +				goto failed;
>> +
>> +			pc[i].pu = syscon_claim(child, "st,pu-control");
>> +			if (!pc[i].pu)
>> +				goto failed;
>> +
>> +			pc[i].od = syscon_claim(child, "st,od-control");
>> +			if (!pc[i].od)
>> +				goto failed;
>> +
>> +			of_property_read_u32(child, "st,retime-pin-mask",
>> +							&pc[i].rt_pin_mask);
>> +
>> +			stixxxx_pctl_dt_get_retime_conf(child, &pc[i]);
>> +			i++;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +failed:
>> +	return -ENODATA;
>> +}
>> +
>> +#define OF_GPIO_ARGS_MIN	(3)
>> +/*
>> + * Each pin is represented in of the below forms.
>> + * <bank offset direction func rt_type rt_delay rt_clk>
>> + */
>> +static int stixxxx_pctl_dt_parse_groups(struct device_node *np,
>> +	struct stixxxx_pctl_group *grp, struct stixxxx_pinctrl *info, int idx)
>> +{
>> +	/* bank pad direction val altfunction */
>> +	const __be32 *list;
>> +	struct property *pp;
>> +	struct stixxxx_pinconf *conf;
>> +	phandle phandle;
>> +	struct device_node *pins;
>> +	u32 pin;
>> +	int i = 0, npins = 0, nr_props;
>> +
>> +	pins = of_get_child_by_name(np, "st,pins");
>> +	if (!pins)
>> +		return -ENODATA;
>> +
>> +	for_each_property_of_node(pins, pp) {
>> +		/* Skip those we do not want to proceed */
>> +		if (!strcmp(pp->name, "name"))
>> +			continue;
>> +
>> +		if (pp  && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
>> +			npins++;
>> +		} else {
>> +			pr_warn("Invalid st,pins in %s node\n", np->name);
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	grp->npins = npins;
>> +	grp->name = np->name;
>> +	grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL);
>> +	grp->pin_conf = devm_kzalloc(info->dev,
>> +					npins * sizeof(*conf), GFP_KERNEL);
>> +	of_property_read_u32(np, "st,function", &grp->altfunc);
>> +
>> +	if (!grp->pins || !grp->pin_conf)
>> +		return -ENOMEM;
>> +
>> +	/* <bank offset direction func rt_type rt_delay rt_clk> */
>> +	for_each_property_of_node(pins, pp) {
>> +		if (!strcmp(pp->name, "name"))
>> +			continue;
>> +		nr_props = pp->length/sizeof(u32);
>> +		list = pp->value;
>> +		conf = &grp->pin_conf[i];
>> +
>> +		/* bank & offset */
>> +		phandle = be32_to_cpup(list++);
>> +		pin = be32_to_cpup(list++);
>> +		conf->pin = of_get_named_gpio(pins, pp->name, 0);
>> +		conf->name = pp->name;
>> +		grp->pins[i] = conf->pin;
>> +
>> +		conf->config = 0;
>> +		/* direction */
>> +		conf->config |= be32_to_cpup(list++);
>> +		/* rt_type rt_delay rt_clk */
>> +		if (nr_props >= OF_GPIO_ARGS_MIN + 2) {
>> +			/* rt_type */
>> +			conf->config |= be32_to_cpup(list++);
>> +			/* rt_delay */
>> +			conf->config |= be32_to_cpup(list++);
>> +			/* rt_clk */
>> +			if (nr_props > OF_GPIO_ARGS_MIN + 2)
>> +				conf->config |= be32_to_cpup(list++);
>> +		}
>> +		i++;
>> +	}
>> +	of_node_put(pins);
>> +
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_pctl_parse_functions(struct device_node *np,
>> +			struct stixxxx_pinctrl *info, u32 index, int *grp_index)
>> +{
>> +	struct device_node *child;
>> +	struct stixxxx_pmx_func *func;
>> +	struct stixxxx_pctl_group *grp;
>> +	int ret, i;
>> +
>> +	func = &info->functions[index];
>> +	func->name = np->name;
>> +	func->ngroups = of_get_child_count(np);
>> +	if (func->ngroups <= 0) {
>> +		dev_err(info->dev, "No groups defined\n");
>> +		return -EINVAL;
>> +	}
>> +	func->groups = devm_kzalloc(info->dev,
>> +			func->ngroups * sizeof(char *), GFP_KERNEL);
>> +	if (!func->groups)
>> +		return -ENOMEM;
>> +
>> +	i = 0;
>> +	for_each_child_of_node(np, child) {
>> +		func->groups[i] = child->name;
>> +		grp = &info->groups[*grp_index];
>> +		*grp_index += 1;
>> +		ret = stixxxx_pctl_dt_parse_groups(child, grp, info, i++);
>> +		if (ret)
>> +			return ret;
>> +	}
>> +	dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
>> +				index, func->name, func->ngroups);
>> +
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_pctl_probe_dt(struct platform_device *pdev,
>> +				 struct stixxxx_pinctrl *info)
>> +{
>> +	int ret = 0;
>> +	int i = 0, j = 0, k = 0;
>> +	struct pinctrl_pin_desc *pdesc;
>> +	struct device_node *np = pdev->dev.of_node;
>> +	struct device_node *child;
>> +	int grp_index = 0;
>> +
>> +	stixxxx_pctl_dt_child_count(info, np);
>> +	if (info->nbanks < 1) {
>> +		dev_err(&pdev->dev, "you need atleast one gpio bank\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	ret = stixxxx_pctl_dt_init(info, np);
>> +	if (ret)
>> +		return ret;
>> +
>> +	dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
>> +	dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
>> +	dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
>> +	info->functions = devm_kzalloc(&pdev->dev,
>> +		info->nfunctions * sizeof(*info->functions), GFP_KERNEL);
>> +
>> +	info->groups = devm_kzalloc(&pdev->dev,
>> +		info->ngroups * sizeof(*info->groups) ,	GFP_KERNEL);
>> +
>> +	if (!info->functions || !info->groups)
>> +		return -ENOMEM;
>> +
>> +	stixxxx_pctl_desc.npins = info->nbanks * STIXXXX_GPIO_PINS_PER_PORT;
>> +	pdesc =	devm_kzalloc(&pdev->dev,
>> +			sizeof(*pdesc) * stixxxx_pctl_desc.npins, GFP_KERNEL);
>> +	if (!pdesc)
>> +		return -ENOMEM;
>> +
>> +	stixxxx_pctl_desc.pins = pdesc;
>> +
>> +	for_each_child_of_node(np, child) {
>> +		if (of_device_is_compatible(child, gpio_compat)) {
>> +			for (j = 0; j < STIXXXX_GPIO_PINS_PER_PORT; j++, k++) {
>> +				const char *port_name = NULL;
>> +				pdesc->number = k;
>> +				of_property_read_string(child, "st,bank-name",
>> +							&port_name);
>> +				pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
>> +							port_name ? : "PIO",
>> +							port_name ? j : k);
>> +				pdesc++;
>> +			}
>> +		} else {
>> +			ret = stixxxx_pctl_parse_functions(child, info,
>> +							i++, &grp_index);
>> +			if (ret) {
>> +				dev_err(&pdev->dev, "No functions found.\n");
>> +				return ret;
>> +			}
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int stixxxx_pctl_probe(struct platform_device *pdev)
>> +{
>> +	struct stixxxx_pinctrl *info;
>> +	int ret, i;
>> +
>> +	if (!pdev->dev.of_node) {
>> +		dev_err(&pdev->dev, "device node not found.\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
>> +	if (!info)
>> +		return -ENOMEM;
>> +
>> +	info->dev = &pdev->dev;
>> +	platform_set_drvdata(pdev, info);
>> +	ret = stixxxx_pctl_probe_dt(pdev, info);
>> +	if (ret)
>> +		return ret;
>> +
>> +	stixxxx_pctl_desc.name = dev_name(&pdev->dev);
>> +	info->pctl = pinctrl_register(&stixxxx_pctl_desc, &pdev->dev, info);
>> +	if (IS_ERR(info->pctl)) {
>> +		dev_err(&pdev->dev, "Failed pinctrl registration\n");
>> +		return PTR_ERR(info->pctl);
>> +	}
>> +
>> +	for (i = 0; i < info->nbanks; i++)
>> +		pinctrl_add_gpio_range(info->pctl, &gpio_ports[i]->range);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct gpio_chip stixxxx_gpio_template = {
>> +	.request		= stixxxx_gpio_request,
>> +	.free			= stixxxx_gpio_free,
>> +	.get			= stixxxx_gpio_get,
>> +	.set			= stixxxx_gpio_set,
>> +	.direction_input	= stixxxx_gpio_direction_input,
>> +	.direction_output	= stixxxx_gpio_direction_output,
>> +	.ngpio			= STIXXXX_GPIO_PINS_PER_PORT,
>> +	.of_gpio_n_cells	= 1,
>> +	.of_xlate		= stixxxx_gpio_xlate,
>> +};
>> +
>> +static int stixxxx_gpio_probe(struct platform_device *pdev)
>> +{
>> +	struct stixxxx_gpio_port *port;
>> +	struct pinctrl_gpio_range *range;
>> +	struct device_node *np  = pdev->dev.of_node;
>> +	int port_num = of_alias_get_id(np, "gpio");
>> +	struct resource *res;
>> +	int err;
>> +
>> +	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
>> +	if (!port)
>> +		return -ENOMEM;
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	port->base = devm_request_and_ioremap(&pdev->dev, res);
>> +	if (!port->base) {
>> +		dev_err(&pdev->dev, "Can't get IO memory mapping!\n");
>> +		return -ENODEV;
>> +	}
>> +
>> +	of_property_read_string(np, "st,bank-name", &port->bank_name);
>> +	port->of_node = np;
>> +
>> +	port->gpio_chip = stixxxx_gpio_template;
>> +	port->gpio_chip.base = port_num * STIXXXX_GPIO_PINS_PER_PORT;
>> +	port->gpio_chip.ngpio = STIXXXX_GPIO_PINS_PER_PORT;
>> +	port->gpio_chip.of_node = np;
>> +	port->gpio_chip.label = dev_name(&pdev->dev);
>> +
>> +	dev_set_drvdata(&pdev->dev, port);
>> +	range = &port->range;
>> +	range->name = port->gpio_chip.label;
>> +	range->id = port_num;
>> +	range->pin_base = range->base = range->id * STIXXXX_GPIO_PINS_PER_PORT;
>> +	range->npins = port->gpio_chip.ngpio;
>> +	range->gc = &port->gpio_chip;
>> +	gpio_ports[port_num] = port;
>> +	err  = gpiochip_add(&port->gpio_chip);
>> +	if (err) {
>> +		dev_err(&pdev->dev, "Failed to add gpiochip(%d)!\n", port_num);
>> +		return err;
>> +	}
>> +	dev_info(&pdev->dev, "gpioport[%s] Added as bank%d\n",
>> +				port->bank_name, port_num);
>> +	return 0;
>> +}
>> +
>> +static struct of_device_id stixxxx_gpio_of_match[] = {
>> +	{ .compatible = "st,stixxxx-gpio", },
>> +	{ /* sentinel */ }
>> +};
>> +
>> +static struct platform_driver stixxxx_gpio_driver = {
>> +	.driver = {
>> +		.name = "st-gpio",
>> +		.owner = THIS_MODULE,
>> +		.of_match_table = of_match_ptr(stixxxx_gpio_of_match),
>> +	},
>> +	.probe = stixxxx_gpio_probe,
>> +};
>> +
>> +static struct of_device_id stixxxx_pctl_of_match[] = {
>> +	{ .compatible = "st,stixxxx-pinctrl",},
>> +	{ /* sentinel */ }
>> +};
>> +
>> +static struct platform_driver stixxxx_pctl_driver = {
>> +	.driver = {
>> +		.name = "st-pinctrl",
>> +		.owner = THIS_MODULE,
>> +		.of_match_table = of_match_ptr(stixxxx_pctl_of_match),
>> +	},
>> +	.probe = stixxxx_pctl_probe,
>> +};
>> +
>> +static int __init stixxxx_pctl_init(void)
>> +{
>> +	int ret = platform_driver_register(&stixxxx_gpio_driver);
>> +	if (ret)
>> +		return ret;
>> +	return platform_driver_register(&stixxxx_pctl_driver);
>> +}
>> +arch_initcall(stixxxx_pctl_init);
>> diff --git a/drivers/pinctrl/pinctrl-stixxxx.h b/drivers/pinctrl/pinctrl-stixxxx.h
>> new file mode 100644
>> index 0000000..a340964
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-stixxxx.h
>> @@ -0,0 +1,197 @@
>> +
>> +/*
>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
>> + * Authors:
>> + *	Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#ifndef __LINUX_DRIVERS_PINCTRL_STIXXXX_H
>> +#define __LINUX_DRIVERS_PINCTRL_STIXXXX_H
>> +
>> +enum stixxxx_retime_style {
>> +	stixxxx_retime_style_none,
>> +	stixxxx_retime_style_packed,
>> +	stixxxx_retime_style_dedicated,
>> +};
>> +
>> +/* Byte positions in 2 syscon words, starts from 0 */
>> +struct stixxxx_retime_offset {
>> +	int retime_offset;
>> +	int clk1notclk0_offset;
>> +	int clknotdata_offset;
>> +	int double_edge_offset;
>> +	int invertclk_offset;
>> +	int delay_lsb_offset;
>> +	int delay_msb_offset;
>> +};
>> +
>> +struct stixxxx_retime_params {
>> +	const struct stixxxx_retime_offset *retime_offset;
>> +	unsigned int *delay_times_in;
>> +	int num_delay_times_in;
>> +	unsigned int *delay_times_out;
>> +	int num_delay_times_out;
>> +};
>> +
>> +struct stixxxx_pio_control {
>> +	enum stixxxx_retime_style rt_style;
>> +	u32 rt_pin_mask;
>> +	const struct stixxxx_retime_params *rt_params;
>> +	struct syscon_field *alt;
>> +	struct syscon_field *oe, *pu, *od;
>> +	struct syscon_field *retiming[8];
>> +};
>> +
>> +/* PIO Block registers */
>> +/* PIO output */
>> +#define REG_PIO_POUT			0x00
>> +/* Set bits of POUT */
>> +#define REG_PIO_SET_POUT		0x04
>> +/* Clear bits of POUT */
>> +#define REG_PIO_CLR_POUT		0x08
>> +/* PIO input */
>> +#define REG_PIO_PIN			0x10
>> +/* PIO configuration */
>> +#define REG_PIO_PC(n)			(0x20 + (n) * 0x10)
>> +/* Set bits of PC[2:0] */
>> +#define REG_PIO_SET_PC(n)		(0x24 + (n) * 0x10)
>> +/* Clear bits of PC[2:0] */
>> +#define REG_PIO_CLR_PC(n)		(0x28 + (n) * 0x10)
>> +/* PIO input comparison */
>> +#define REG_PIO_PCOMP			0x50
>> +/* Set bits of PCOMP */
>> +#define REG_PIO_SET_PCOMP		0x54
>> +/* Clear bits of PCOMP */
>> +#define REG_PIO_CLR_PCOMP		0x58
>> +/* PIO input comparison mask */
>> +#define REG_PIO_PMASK			0x60
>> +/* Set bits of PMASK */
>> +#define REG_PIO_SET_PMASK		0x64
>> +/* Clear bits of PMASK */
>> +#define REG_PIO_CLR_PMASK		0x68
>> +
>> +#define STIXXXX_MAX_GPIO_BANKS		32
>> +
>> +#define STIXXXX_GPIO_DIRECTION_BIDIR	0x1
>> +#define STIXXXX_GPIO_DIRECTION_OUT	0x2
>> +#define STIXXXX_GPIO_DIRECTION_IN	0x4
>> +
>> +#define STIXXXX_GPIO_PINS_PER_PORT	8
>> +#define stixxxx_gpio_port(gpio) ((gpio) / STIXXXX_GPIO_PINS_PER_PORT)
>> +#define stixxxx_gpio_pin(gpio) ((gpio) % STIXXXX_GPIO_PINS_PER_PORT)
>> +
>> +/* pinconf */
>> +/*
>> + * Pinconf is represented in an opaque unsigned long variable.
>> + * Below is the bit allocation details for each possible configuration.
>> + * All the bit fields can be encapsulated into four variables
>> + * (direction, retime-type, retime-clk, retime-delay)
>> + *
>> + *	 +----------------+
>> + *[31:28]| reserved-3     |
>> + *	 +----------------+-------------
>> + *[27]   |	oe	  |		|
>> + *	 +----------------+		v
>> + *[26]   |	pu	  |	[Direction	]
>> + *	 +----------------+		^
>> + *[25]   |	od	  |		|
>> + *	 +----------------+-------------
>> + *[24]   | reserved-2     |
>> + *	 +----------------+-------------
>> + *[23]   |    retime      |		|
>> + *	 +----------------+		|
>> + *[22]   | retime-invclk  |		|
>> + *	 +----------------+		v
>> + *[21]   |retime-clknotdat|	[Retime-type	]
>> + *	 +----------------+		^
>> + *[20]   | retime-de      |		|
>> + *	 +----------------+-------------
>> + *[19:18]| retime-clk     |------>[Retime-Clk	]
>> + *	 +----------------+
>> + *[17:16]|  reserved-1    |
>> + *	 +----------------+
>> + *[15..0]| retime-delay   |------>[Retime Delay]
>> + *	 +----------------+
>> + */
>> +
>> +#define STIXXXX_PINCONF_UNPACK(conf, param)\
>> +				((conf >> STIXXXX_PINCONF_ ##param ##_SHIFT) \
>> +				& STIXXXX_PINCONF_ ##param ##_MASK)
>> +
>> +#define STIXXXX_PINCONF_PACK(conf, val, param)	(conf |=\
>> +				((val & STIXXXX_PINCONF_ ##param ##_MASK) << \
>> +					STIXXXX_PINCONF_ ##param ##_SHIFT))
>> +
>> +/* Output enable */
>> +#define STIXXXX_PINCONF_OE_MASK		0x1
>> +#define STIXXXX_PINCONF_OE_SHIFT	27
>> +#define STIXXXX_PINCONF_OE		BIT(27)
>> +#define STIXXXX_PINCONF_UNPACK_OE(conf)	STIXXXX_PINCONF_UNPACK(conf, OE)
>> +#define STIXXXX_PINCONF_PACK_OE(conf, val)  STIXXXX_PINCONF_PACK(conf, val, OE)
>> +
>> +/* Pull Up */
>> +#define STIXXXX_PINCONF_PU_MASK		0x1
>> +#define STIXXXX_PINCONF_PU_SHIFT	26
>> +#define STIXXXX_PINCONF_PU		BIT(26)
>> +#define STIXXXX_PINCONF_UNPACK_PU(conf)	STIXXXX_PINCONF_UNPACK(conf, PU)
>> +#define STIXXXX_PINCONF_PACK_PU(conf, val) STIXXXX_PINCONF_PACK(conf, val, PU)
>> +
>> +/* Open Drain */
>> +#define STIXXXX_PINCONF_OD_MASK		0x1
>> +#define STIXXXX_PINCONF_OD_SHIFT	25
>> +#define STIXXXX_PINCONF_OD		BIT(25)
>> +#define STIXXXX_PINCONF_UNPACK_OD(conf)	STIXXXX_PINCONF_UNPACK(conf, OD)
>> +#define STIXXXX_PINCONF_PACK_OD(conf, val) STIXXXX_PINCONF_PACK(conf, val, OD)
>> +
>> +#define STIXXXX_PINCONF_RT_MASK		0x1
>> +#define STIXXXX_PINCONF_RT_SHIFT	23
>> +#define STIXXXX_PINCONF_RT		BIT(23)
>> +#define STIXXXX_PINCONF_UNPACK_RT(conf)	STIXXXX_PINCONF_UNPACK(conf, RT)
>> +#define STIXXXX_PINCONF_PACK_RT(conf, val) STIXXXX_PINCONF_PACK(conf, val, RT)
>> +
>> +#define STIXXXX_PINCONF_RT_INVERTCLK_MASK	0x1
>> +#define STIXXXX_PINCONF_RT_INVERTCLK_SHIFT	22
>> +#define STIXXXX_PINCONF_RT_INVERTCLK		BIT(22)
>> +#define STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(conf) \
>> +			STIXXXX_PINCONF_UNPACK(conf, RT_INVERTCLK)
>> +#define STIXXXX_PINCONF_PACK_RT_INVERTCLK(conf, val) \
>> +			STIXXXX_PINCONF_PACK(conf, val, RT_INVERTCLK)
>> +
>> +#define STIXXXX_PINCONF_RT_CLKNOTDATA_MASK	0x1
>> +#define STIXXXX_PINCONF_RT_CLKNOTDATA_SHIFT	21
>> +#define STIXXXX_PINCONF_RT_CLKNOTDATA		BIT(21)
>> +#define STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(conf)	\
>> +				STIXXXX_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
>> +#define STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(conf, val) \
>> +				STIXXXX_PINCONF_PACK(conf, val, RT_CLKNOTDATA)
>> +
>> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE_MASK	0x1
>> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE_SHIFT	20
>> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE		BIT(20)
>> +#define STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
>> +				STIXXXX_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
>> +#define STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(conf, val) \
>> +				STIXXXX_PINCONF_PACK(conf, val, RT_DOUBLE_EDGE)
>> +
>> +#define STIXXXX_PINCONF_RT_CLK_MASK		0x3
>> +#define STIXXXX_PINCONF_RT_CLK_SHIFT		18
>> +#define STIXXXX_PINCONF_RT_CLK			BIT(18)
>> +#define STIXXXX_PINCONF_UNPACK_RT_CLK(conf)	\
>> +			STIXXXX_PINCONF_UNPACK(conf, RT_CLK)
>> +#define STIXXXX_PINCONF_PACK_RT_CLK(conf, val) \
>> +			STIXXXX_PINCONF_PACK(conf, val, RT_CLK)
>> +
>> +/* RETIME_DELAY in Pico Secs */
>> +#define STIXXXX_PINCONF_RT_DELAY_MASK		0xffff
>> +#define STIXXXX_PINCONF_RT_DELAY_SHIFT		0
>> +#define STIXXXX_PINCONF_UNPACK_RT_DELAY(conf) \
>> +				STIXXXX_PINCONF_UNPACK(conf, RT_DELAY)
>> +#define STIXXXX_PINCONF_PACK_RT_DELAY(conf, val) \
>> +				STIXXXX_PINCONF_PACK(conf, val, RT_DELAY)
>> +
>> +#endif /* __LINUX_DRIVERS_PINCTRL_STIXXXX_H */
>> -- 
>> 1.7.6.5
>>
>> _______________________________________________
>> devicetree-discuss mailing list
>> devicetree-discuss at lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/devicetree-discuss



From arnd at arndb.de  Wed May  8 12:33:03 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 18:33:03 +0200
Subject: [PATCH] irqchip: Add irqchip_init dummy function
In-Reply-To: <518A6C05.9030303@cogentembedded.com>
References: <1368019204-24448-1-git-send-email-hechtb+renesas@gmail.com>
 <518A6C05.9030303@cogentembedded.com>
Message-ID: <201305081833.03716.arnd@arndb.de>

On Wednesday 08 May 2013, Sergei Shtylyov wrote:
> > --- a/include/linux/irqchip.h
> > +++ b/include/linux/irqchip.h
> > @@ -11,6 +11,10 @@
> >   #ifndef _LINUX_IRQCHIP_H
> >   #define _LINUX_IRQCHIP_H
> >
> > +#ifdef CONFIG_IRQCHIP
> >   void irqchip_init(void);
> > +#else
> > +void irqchip_init(void) {};
> 
>     Semicolon not needed here.
> 
> > +#endif
> 

More importantly, the function should be marked as "static inline", otherwise
you get a link error if this header is included in more than one place.

	Arnd


From gregkh at linuxfoundation.org  Wed May  8 12:36:13 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Wed, 8 May 2013 09:36:13 -0700
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305081831.48566.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
 <20130508161527.GA28080@kroah.com>
 <201305081831.48566.arnd@arndb.de>
Message-ID: <20130508163613.GA13761@kroah.com>

On Wed, May 08, 2013 at 06:31:48PM +0200, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Greg KH wrote:
> > > just mention there is not hardware reason to not use the generic ttySx
> > > in place of ttyAS as we have only one IP that handle serial on this
> > > family of SoC
> > > 
> > > personally I'll switch to ttySx
> > 
> > Great, then you can use the same major/minor range as well, so there's
> > no more objection from me about this :)
> 
> Does that work these days when you have kernel with multiple built-in
> uart drivers?

It "should", as the major/minor registration should only happen when the
hardware is found, but I haven't tested it out, so I can't say for sure.

> I think it would be good if all uarts were using the same name space
> and major/minor numbers, but I think the mess we currently have is
> the result of the tty_register_driver() interface reserving the
> device number range at driver load time, independent of the presence
> of devices.  I would assume that normal distro kernels always ship
> with an 8250 driver built-in to allow using that as the console,
> and if I read the code correctly, that currently prevents another
> uart driver from registering the same major/minor numbers.

We can always fix this if needed :)

thanks,

greg k-h


From swarren at wwwdotorg.org  Wed May  8 12:36:54 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 10:36:54 -0600
Subject: [PATCH 1/4] ARM: tegra30: clocks: Fix pciex clock registration
In-Reply-To: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
Message-ID: <518A7F26.3030605@wwwdotorg.org>

On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> Registering pciex as peripheral clock instead of fixed clock
> as tegra_perih_reset_assert(deassert) api of this clock api 
> gives warning and ultimately does not succeed to assert(deassert).

A few procedural comments: I believe this is at least the second version
of these patches that have been posted. As such, the email subject
should say e.e. "PATCH V2" not just "PATCH". You can pass
--subject-prefix='PATCH V2' to git format-patch to achieve this.

Since this is an updated version of the patches, each patch should
describe what changed in the patch, so that people know what issues
you've fixed in this version. Most people believe that the description
of changes should be below the --- line, so that it doesn't get included
in the commit description when the patch is applied.

> Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> and should be applied on top of this.

Those two lines should be below the --- line so that they don't get
included in the commit description when the patch is applied. git
metadata will provide clues re: who applied the patch and to which
branch, so there's no need to duplicate this information in the commit
description itself, but rather include it below --- so that it's still
present and people can see it.

Some comments on the patch and series below...

> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c

> +	/* pciex */
> +	clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
> +				    74, &periph_u_regs, periph_clk_enb_refcnt);
> +	clk_register_clkdev(clk, "pciex", NULL);
> +	clks[pciex] = clk;

Hmmm. This change perhaps isn't technically correct, but is the best we
can do for now, so it's fine. It's also consistent with how the Tegra20
clock driver is written.

This clock has a "reset" bit in the CLK_RST_* registers, but not an
"enable" bit in the CLK_ENB_* registers. Hence, representing this as a
gated clock isn't correct, since there is not gate control in HW. The
correct way to handle this would be to implement the new reset
controller API for Tegra, and expose the reset control only, and not
touch the clock registration at all. However, we do this exact same
thing for a number of Tegra clocks right now, hence I think this change
is fine for now; we'll clean this up, along with some other instances of
the same issue, once the reset API is implemented for Tegra. Of course,
if that happens before the PCI code is checked in, then my opinion will
change.

> @@ -1930,7 +1931,6 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
>  	TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
>  	TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
>  	TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
> -	TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),

That seems like an unrelated change, and isn't mentioned in the commit
description. Is the change strictly necessary? Is it cleanup that can
happen as a separate patch later in the series? Aren't you able to
remove the CLK_DUPLICATE() entries for other PCIe-related clocks too?


From will.deacon at arm.com  Wed May  8 12:40:19 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 17:40:19 +0100
Subject: [RFC PATCH v2 08/11] ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE
 bits.
In-Reply-To: <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
Message-ID: <20130508164018.GF20820@mudshark.cambridge.arm.com>

On Wed, May 08, 2013 at 10:52:40AM +0100, Steve Capper wrote:
> Under ARM64, PTEs can be broadly categorised as follows:
>    - Present and valid: Bit #0 is set. The PTE is valid and memory
>      access to the region may fault.
> 
>    - Present and invalid: Bit #0 is clear and bit #1 is set.
>      Represents present memory with PROT_NONE protection. The PTE
>      is an invalid entry, and the user fault handler will raise a
>      SIGSEGV.
> 
>    - Not present (file): Bits #0 and #1 are clear, bit #2 is set.
>      Memory represented has been paged out. The PTE is an invalid
>      entry, and the fault handler will try and re-populate the
>      memory where necessary.
> 
> Huge PTEs are block descriptors that have bit #1 clear. If we wish
> to represent PROT_NONE huge PTEs we then run into a problem as
> there is no way to distinguish between regular and huge PTEs if we
> set bit #1.
> 
> As huge PTEs are always present, the meaning of bits #1 and #2 can
> be swapped for invalid PTEs. This patch swaps the PTE_FILE and
> PTE_PROT_NONE constants, allowing us to represent PROT_NONE huge
> PTEs.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> ---
>  arch/arm64/include/asm/pgtable.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index b1a1b59..e245260 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -25,8 +25,8 @@
>   * Software defined PTE bits definition.
>   */
>  #define PTE_VALID		(_AT(pteval_t, 1) << 0)
> -#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 1)	/* only when !PTE_VALID */
> -#define PTE_FILE		(_AT(pteval_t, 1) << 2)	/* only when !pte_present() */
> +#define PTE_FILE		(_AT(pteval_t, 1) << 1)	/* only when !pte_present() */
> +#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 2)	/* only when !PTE_VALID */
>  #define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
>  #define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
>  
> @@ -306,8 +306,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
>  
>  /*
>   * Encode and decode a file entry:
> - *	bits 0-1:	present (must be zero)
> - *	bit  2:		PTE_FILE
> + *	bits 0 & 2:	present (must be zero)
> + *	bit  1:		PTE_FILE
>   *	bits 3-63:	file offset / PAGE_SIZE
>   */
>  #define pte_file(pte)		(pte_val(pte) & PTE_FILE)

Can you update the comment describing swp entries too please? I *think* the
__SWP_* defines can remain untouched, but the comment is now wrong.

Will


From plagnioj at jcrosoft.com  Wed May  8 12:38:37 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 9 May 2013 00:38:37 +0800
Subject: [RFC 4/8] pinctrl:stixxxx: Add pinctrl and pinconf support.
In-Reply-To: <518A7CFD.1010602@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022284-2283-1-git-send-email-srinivas.kandagatla@st.com>
 <20130508150629.GA3041@game.jcrosoft.org> <518A7CFD.1010602@st.com>
Message-ID: <A29022D9-CC3E-47D3-B7F7-AD2C8167438D@jcrosoft.com>


On May 9, 2013, at 12:27 AM, Srinivas KANDAGATLA <srinivas.kandagatla at st.com> wrote:

> Thankyou for the comments.
> On 08/05/13 16:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 15:11 Wed 08 May     , Srinivas KANDAGATLA wrote:
>>> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>> 
>>> This patch add pinctrl support to ST SoCs.
>>> 
>>> About hardware:
>>> ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
>>> pin configurations.
>>> 
>>> Each multi-function pin is controlled, driven and routed through the PIO
>>> multiplexing block. Each pin supports GPIO functionality (ALT0) and
>>> multiple alternate functions(ALT1 - ALTx) that directly connect the pin
>>> to different hardware blocks. When a pin is in GPIO mode, Output Enable
>>> (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
>>> block. Otherwise the PIO multiplexing block configures these parameters
>>> and retiming the signal.
>>> 
>> g> About driver:
>>> This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
>>> pinconf, pinmux, gpio subsystems. All the pinctrl related config
>>> information can only come from device trees.
>>> 
>>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>> CC: Stephen Gallimore <stephen.gallimore at st.com>
>>> CC: Stuart Menefy <stuart.menefy at st.com>
>>> ---
>>> .../bindings/pinctrl/pinctrl-stixxxx.txt           |  160 +++
>>> drivers/pinctrl/Kconfig                            |   13 +
>>> drivers/pinctrl/Makefile                           |    1 +
>>> drivers/pinctrl/pinctrl-stixxxx.c                  | 1151 ++++++++++++++++++++
>>> drivers/pinctrl/pinctrl-stixxxx.h                  |  197 ++++
>> the pinctrl is present in older SoC ST40 not only stixxx
>> 
>> and you must provide a proper name not stixxxx
> The reason for giving it stixxxx name is all the set-top-box based SOCs
> have the naming convention of stixxxx like stih7108, stih415, stih416
> and stig125.. and so on..
I known perfectly the ST SoCs for years (st20/st200 & co)

no you need to use the name of the first SoC using the IP

cf ePAR
> 
>>> 5 files changed, 1522 insertions(+), 0 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>>> create mode 100644 drivers/pinctrl/pinctrl-stixxxx.c
>>> create mode 100644 drivers/pinctrl/pinctrl-stixxxx.h
>>> 
>>> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>>> new file mode 100644
>>> index 0000000..b0a93b5
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-stixxxx.txt
>>> @@ -0,0 +1,160 @@
>>> +*ST pin controller.
>>> +
>>> +Each multi-function pin is controlled, driven and routed through the
>>> +PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
>>> +and multiple alternate functions(ALT1 - ALTx) that directly connect
>>> +the pin to different hardware blocks.
>>> +
>>> +When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
>>> +Pull Up (PU) are driven by the related PIO block.
>> HighZ too
>> 
>> this driver look very similar with AT91 we should consolidate at binding and C
>> level
> Yes, it look very similar to at91, however they are very much different
> w.r.t pinconf.

that's why I said we need to consolidate

>>> ---
>>> +
>>> +ST pinctrl driver controls PIO multiplexing block and also interacts with
>>> +gpio driver to configure a pin.
>>> +
>>> +Required properties: (PIO multiplexing block)
>>> +- compatible	: should be "st,stixxxx-pinctrl"
>>> +			each subnode should set "st,stixxxx-gpio"
>>> +			as compatible for each gpio-controller bank.
>> first soc where the IP is present
>>> +- gpio-controller : Indicates this device is a GPIO controller
>>> +- #gpio-cells	  : Should be one. The first cell is the pin number.
>>> +- #retime-delay-cells	: Should be number of possible retime delays.
>>> +- st,retime-in-delay	: Should be array of delays in nsecs.
>>> +- st,retime-out-delay	: Should be array of delays in nsecs.
>>> +- retime-style		: Should indicate which type of retime is used.
>>> +			possible values are "none", "packed" and "dedicated".
>> always prefix st, when specific property
>> st,
> Its a typo, will fix it.
>>> +- st,retime-offset	: phandle to retime offsets in retime registers.
>>> +		These are not necessary for "dedicated" retime-style registers.
>>> +	- clk1notclk0	: Should define offset for clk1not clk0 in retime register.
>>> +	- delay-lsb	: Should define offset for delay-lsb in retime register.
>>> +	- delay-msb	: Should define offset for delay msb in retime register.
>>> +	- invertclk	: Should define offset for invertclk in retime register.
>>> +	- retime	: Should define offset for retime in retime register.
>>> +	- clknotdata	: Should define offset for clknotdata in retime register.
>>> +	- double_edge	: Should define offset for double edge in retime register.
>> As much as I like to describe the IP in the DT, I think it's too much this
>> time move this to C and use the compatible or detect it on the hardware to
>> handle this 
> That is a good idea.

cf at91 pinctrl
>> 
>>> +- st,alt-control		: Should be sysconf to control alternate function on pio.
>>> +- st,oe-control		: Should be sysconf to control output enable on pio.
>>> +- st,pu-control		: Should be sysconf to control pull up on pio.
>>> +- st,od-control		: Should be sysconf to control open drain on pio.
>>> +- st,retime-style		: Should indicate which type of retime is used.
>>> +			possible values are "none", "packed" and "dedicated".
>>> +- st,retime-pin-mask	: Should be mask to specify which pins can be retimed.
>>> +- retime-control[0...N]: These properties point to sysconfs which control retime.
>>> +			Depending on retime-style the number of retime-controls
>>> +			vary: 2 for "packed"; 8 for "dedicated".
>> 
>>> +- st,bank-name		: Should be a name string for this bank.
>>> +
>>> +Example:
>>> +	pio_retime_offset: pio-retime-offset {
>>> +		clk1notclk0	= <0>;
>>> +		delay-lsb	= <2>;
>>> +		delay-msb	= <3>;
>>> +		invertclk	= <4>;
>>> +		retime		= <5>;
>>> +		clknotdata	= <6>;
>>> +		double-edge	= <7>;
>>> +	};
>>> +
>>> +	pin-controller {
>>> +		#retime-delay-cells = <4>;
>>> +		compatible = "st,stixxxx-pinctrl", "simple-bus";
>>> +		st,retime-offset = <&pio_retime_offset>;
>>> +		st,retime-in-delay = <0 500 1000 1500>;
>>> +		st,retime-out-delay = <0 1000 2000 3000>;
>>> +		ranges;
>>> +		PIO0: pinctrl at fe610000 {
>>> +			gpio-controller;
>>> +			#gpio-cells = <1>;
>>> +			compatible = "st,stixxxx-gpio";
>>> +			reg = <0xfe610000 0x100>;
>>> +			st,bank-name  = "PIO0";
>>> +			st,alt-control = <&SYSCONF_SBC(0) 0 31>;
>>> +			st,oe-control = <&SYSCONF_SBC(5)  0 7>;
>>> +			st,pu-control = <&SYSCONF_SBC(7)  0 7>;
>>> +			st,od-control = <&SYSCONF_SBC(9)  0 7>;
>>> +			st,retime-style = "packed";
>>> +			st,retime-pin-mask = <0xff>;
>>> +			st,retime-control0 = <&SYSCONF_SBC(16) 0 31>;
>>> +			st,retime-control1 = <&SYSCONF_SBC(17) 0 31>;
>>> +		};
>>> +		...
>>> +		pin-functions nodes follow...
>>> +	};
>>> +
>>> +
>>> +Contents of function subnode node:
>>> +----------------------
>>> +Required properties for pin configuration node:
>>> +- st,function	: Should be alternate function number associated
>>> +		with this set of pins.
>>> +		possible altfunction values:
>>> +		ALT1
>>> +		ALT2
>>> +		ALT3
>>> +		ALT4
>>> +		ALT5
>>> +		ALT6
>>> +		ALT7
>> use number in the DoC
> Ok.
>> 
>>> +
>>> +- st,pins	: Child node with list of pins with configuration.
>>> +
>>> +Below is the format of how each pin conf should look like.
>>> +
>>> +<bank offset mode rt_type rt_delay rt_clk>
>>> +
>>> +Every PIO is represented with 4-7 parameters depending on retime configuration.
>>> +Each parameter is explained as below.
>>> +
>>> +-bank		: Should be bank phandle to which this PIO belongs.
>>> +-offset		: Offset in the PIO bank.
>>> +-mode		:pin configuration is selected from one of the below values.
>>> +		IN
>>> +		IN_PU
>>> +		OUT
>>> +		BIDIR
>>> +		BIDIR_PU
>> ditto
> Actually these modes are top level defines of three different variables,
> OE, PU, OD used in the registers.
> Its very common that driver might just be interested in one of listed modes.

we need to represent the value in the doc as the Macro was just introduce recently for the Kernel only
It's not DT spec
>>> +
>>> +-rt_type	Retiming Configuration for the pin.
>>> +		Possible retime configuration are:
>>> +
>>> +		-------		-------------
>>> +		value		args
>>> +		-------		-------------
>>> +		NICLK		<delay> <clk>
>>> +		ICLK_IO		<delay> <clk>
>>> +		BYPASS		<delay>
>>> +		DE_IO		<delay> <clk>
>>> +		SE_ICLK_IO	<delay> <clk>
>>> +		SE_NICLK_IO	<delay> <clk>
>>> +
>>> +- delay	is retime delay in pico seconds.
>>> +		Possible values are: refer to retime-in/out-delays
>>> +
>>> +- rt_clk	:clk to be use for retime.
>>> +		Possible values are:
>>> +		CLK_A
>>> +		CLK_B
>>> +		CLK_C
>>> +		CLK_D
>>> +
>>> +Example of mmcclk pin which is a bi-direction pull pu with retime config
>>> +as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
>>> +
>>> +pin-controller {
>>> +	...
>>> +	mmc0 {
>>> +		pinctrl_mmc: mmc {
>>> +			st,function = <ALT4>;
>>> +			st,pins {
>>> +				mmcclk = <&PIO13 4 BIDIR_PU NICLK  0  CLK_B>;
>>> +				...
>>> +			};
>>> +		};
>>> +	...
>>> +	};
>>> +};
>>> +
>>> +sdhci0:sdhci at fe810000{
>>> +	...
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0	= <&pinctrl_mmc>;
>>> +};
>>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>>> index 34f51d2..611a399 100644
>>> --- a/drivers/pinctrl/Kconfig
>>> +++ b/drivers/pinctrl/Kconfig
>>> @@ -179,6 +179,19 @@ config PINCTRL_SUNXI
>>> 	select PINMUX
>>> 	select GENERIC_PINCONF
>>> 
>>> +config PINCTRL_STIXXXX
>>> +	bool "ST Microelectronics pin controller driver for STixxxx SoCs"
>>> +	depends on PLAT_STIXXXX
>>> +	select PINMUX
>>> +	select PINCONF
>>> +	select MFD_SYSCON
>>> +	help
>>> +	  Say yes here to support pinctrl interface on STixxxx SOCs.
>>> +	  This driver is used to control both PIO block and PIO-mux
>>> +	  block to configure a pin.
>>> +
>>> +	  If unsure, say N.
>>> +
>>> config PINCTRL_TEGRA
>>> 	bool
>>> 	select PINMUX
>>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>>> index f82cc5b..99a2c78 100644
>>> --- a/drivers/pinctrl/Makefile
>>> +++ b/drivers/pinctrl/Makefile
>>> @@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS)	+= pinctrl-exynos.o
>>> obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
>>> obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
>>> obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
>>> +obj-$(CONFIG_PINCTRL_STIXXXX) 	+= pinctrl-stixxxx.o
>>> 
>>> obj-$(CONFIG_PLAT_ORION)        += mvebu/
>>> obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
>>> diff --git a/drivers/pinctrl/pinctrl-stixxxx.c b/drivers/pinctrl/pinctrl-stixxxx.c
>>> new file mode 100644
>>> index 0000000..7d2c59c
>>> --- /dev/null
>>> +++ b/drivers/pinctrl/pinctrl-stixxxx.c
>>> @@ -0,0 +1,1151 @@
>>> +/*
>>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
>>> + * Authors:
>>> + *	Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + */
>>> +
>>> +#include <linux/init.h>
>>> +#include <linux/module.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/err.h>
>>> +#include <linux/io.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_gpio.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/pinctrl/pinctrl.h>
>>> +#include <linux/pinctrl/pinmux.h>
>>> +#include <linux/pinctrl/pinconf.h>
>>> +#include <linux/platform_device.h>
>>> +#include "core.h"
>>> +#include "pinctrl-stixxxx.h"
>>> +
>>> +struct stixxxx_pinconf {
>>> +	int		pin;
>>> +	const char	*name;
>>> +	unsigned long	config;
>>> +};
>>> +
>>> +struct stixxxx_pmx_func {
>>> +	const char	*name;
>>> +	const char	**groups;
>>> +	unsigned	ngroups;
>>> +};
>>> +
>>> +struct stixxxx_pctl_group {
>>> +	const char		*name;
>>> +	unsigned int		*pins;
>>> +	unsigned		npins;
>>> +	int			altfunc;
>>> +	struct stixxxx_pinconf	*pin_conf;
>>> +};
>>> +
>>> +#define to_stixxxx_gpio_port(chip) \
>>> +		container_of(chip, struct stixxxx_gpio_port, gpio_chip)
>>> +
>>> +struct stixxxx_gpio_port {
>>> +	struct gpio_chip	gpio_chip;
>>> +	struct pinctrl_gpio_range range;
>>> +	void __iomem		*base;
>>> +	struct device_node	*of_node;
>>> +	const char		*bank_name;
>>> +};
>>> +
>>> +static struct stixxxx_gpio_port *gpio_ports[STIXXXX_MAX_GPIO_BANKS];
>>> +
>>> +struct stixxxx_pinctrl {
>>> +	struct device			*dev;
>>> +	struct pinctrl_dev		*pctl;
>>> +	int				nbanks;
>>> +	struct stixxxx_pmx_func		*functions;
>>> +	int				nfunctions;
>>> +	struct stixxxx_pctl_group	*groups;
>>> +	int				ngroups;
>>> +	struct stixxxx_pio_control	*pio_controls;
>>> +};
>>> +
>>> +/* Low level functions.. */
>>> +static void stixxxx_pinconf_set_direction(struct stixxxx_pio_control *pc,
>>> +				int pin_id, unsigned long config)
>>> +{
>>> +	struct syscon_field *output_enable;
>>> +	struct syscon_field *pull_up;
>>> +	struct syscon_field *open_drain;
>>> +	unsigned long oe_value, pu_value, od_value;
>>> +	unsigned long mask;
>>> +	int pin = stixxxx_gpio_pin(pin_id);
>>> +
>>> +	output_enable = pc->oe;
>>> +	pull_up = pc->pu;
>>> +	open_drain = pc->od;
>>> +
>>> +	mask = BIT(pin);
>>> +
>>> +	oe_value = syscon_read(output_enable);
>>> +	pu_value = syscon_read(pull_up);
>>> +	od_value = syscon_read(open_drain);
>>> +
>>> +	/* Clear old values */
>>> +	oe_value &= ~mask;
>>> +	pu_value &= ~mask;
>>> +	od_value &= ~mask;
>>> +
>>> +	if (config & STIXXXX_PINCONF_OE)
>>> +		oe_value |= mask;
>>> +	if (config & STIXXXX_PINCONF_PU)
>>> +		pu_value |= mask;
>>> +	if (config & STIXXXX_PINCONF_OD)
>>> +		od_value |= mask;
>>> +
>>> +	syscon_write(output_enable, oe_value);
>>> +	syscon_write(pull_up, pu_value);
>>> +	syscon_write(open_drain, od_value);
>>> +}
>>> +
>>> +static void stixxxx_pctl_set_function(struct stixxxx_pio_control *pc,
>>> +				int pin_id, int function)
>>> +{
>>> +	struct syscon_field *selector;
>>> +	int offset;
>>> +	unsigned long val;
>>> +	int pin = stixxxx_gpio_pin(pin_id);
>>> +
>>> +	selector = pc->alt;
>>> +	offset = pin * 4;
>>> +	val = syscon_read(selector);
>>> +	val &= ~(0xf << offset);
>>> +	val |= function << offset;
>>> +	syscon_write(selector, val);
>>> +}
>>> +
>>> +static unsigned long stixxxx_pinconf_delay_to_bit(unsigned int delay,
>>> +		const struct stixxxx_retime_params *rt_params,
>>> +		unsigned long config)
>>> +{
>>> +	unsigned int *delay_times;
>>> +	int num_delay_times, i, closest_index = -1;
>>> +	unsigned int closest_divergence = UINT_MAX;
>>> +
>>> +	if (STIXXXX_PINCONF_UNPACK_OE(config)) {
>>> +		delay_times = rt_params->delay_times_out;
>>> +		num_delay_times = rt_params->num_delay_times_out;
>>> +	} else {
>>> +		delay_times = rt_params->delay_times_in;
>>> +		num_delay_times = rt_params->num_delay_times_in;
>>> +	}
>>> +
>>> +	for (i = 0; i < num_delay_times; i++) {
>>> +		unsigned int divergence = abs(delay - delay_times[i]);
>>> +
>>> +		if (divergence == 0)
>>> +			return i;
>>> +
>>> +		if (divergence < closest_divergence) {
>>> +			closest_divergence = divergence;
>>> +			closest_index = i;
>>> +		}
>>> +	}
>>> +
>>> +	pr_warn("Attempt to set delay %d, closest available %d\n",
>>> +	     delay, delay_times[closest_index]);
>>> +
>>> +	return closest_index;
>>> +}
>>> +
>>> +static unsigned long stixxxx_pinconf_bit_to_delay(unsigned int index,
>>> +		const struct stixxxx_retime_params *rt_params,
>>> +		unsigned long output)
>>> +{
>>> +	unsigned int *delay_times;
>>> +	int num_delay_times;
>>> +
>>> +	if (output) {
>>> +		delay_times = rt_params->delay_times_out;
>>> +		num_delay_times = rt_params->num_delay_times_out;
>>> +	} else {
>>> +		delay_times = rt_params->delay_times_in;
>>> +		num_delay_times = rt_params->num_delay_times_in;
>>> +	}
>>> +
>>> +	if (index < num_delay_times) {
>>> +		return delay_times[index];
>>> +	} else {
>>> +		pr_warn("Delay not found in/out delay list\n");
>>> +		return 0;
>>> +	}
>>> +}
>>> +
>>> +static void stixxxx_pinconf_set_retime_packed(
>>> +		struct stixxxx_pio_control *pc,
>>> +		unsigned long config, int pin)
>>> +{
>>> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
>>> +	const struct stixxxx_retime_offset *offset = rt_params->retime_offset;
>>> +	struct syscon_field **regs;
>>> +	unsigned long values[2];
>>> +	unsigned long mask;
>>> +	int i, j;
>>> +	int clk = STIXXXX_PINCONF_UNPACK_RT_CLK(config);
>>> +	int clknotdata = STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config);
>>> +	int double_edge = STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
>>> +	int invertclk = STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config);
>>> +	int retime = STIXXXX_PINCONF_UNPACK_RT(config);
>>> +	unsigned long delay = stixxxx_pinconf_delay_to_bit(
>>> +			STIXXXX_PINCONF_UNPACK_RT_DELAY(config),
>>> +			pc->rt_params, config);
>>> +
>>> +	unsigned long rt_cfg =
>>> +		((clk		& 1) << offset->clk1notclk0_offset) |
>>> +		((clknotdata	& 1) << offset->clknotdata_offset) |
>>> +		((delay		& 1) << offset->delay_lsb_offset) |
>>> +		(((delay >> 1)  & 1) << offset->delay_msb_offset) |
>>> +		((double_edge	& 1) << offset->double_edge_offset) |
>>> +		((invertclk	& 1) << offset->invertclk_offset) |
>>> +		((retime	& 1) << offset->retime_offset);
>>> +
>>> +	regs = pc->retiming;
>>> +	values[0] = syscon_read(regs[0]);
>>> +	values[1] = syscon_read(regs[1]);
>>> +
>>> +	for (i = 0; i < 2; i++) {
>>> +		mask = BIT(pin);
>>> +		for (j = 0; j < 4; j++) {
>>> +			if (rt_cfg & 1)
>>> +				values[i] |= mask;
>>> +			else
>>> +				values[i] &= ~mask;
>>> +			mask <<= 8;
>>> +			rt_cfg >>= 1;
>>> +		}
>>> +	}
>>> +
>>> +	syscon_write(regs[0], values[0]);
>>> +	syscon_write(regs[1], values[1]);
>>> +}
>>> +
>>> +static void stixxxx_pinconf_set_retime_dedicated(
>>> +	struct stixxxx_pio_control *pc,
>>> +	unsigned long config, int pin)
>>> +{
>>> +	struct syscon_field *reg;
>>> +	int input = STIXXXX_PINCONF_UNPACK_OE(config) ? 0 : 1;
>>> +	int clk = STIXXXX_PINCONF_UNPACK_RT_CLK(config);
>>> +	int clknotdata = STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config);
>>> +	int double_edge = STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
>>> +	int invertclk = STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config);
>>> +	int retime = STIXXXX_PINCONF_UNPACK_RT(config);
>>> +	unsigned long delay = stixxxx_pinconf_delay_to_bit(
>>> +			STIXXXX_PINCONF_UNPACK_RT_DELAY(config),
>>> +			pc->rt_params, config);
>>> +
>>> +	unsigned long retime_config =
>>> +		((clk		& 0x3) << 0) |
>>> +		((clknotdata	& 0x1) << 2) |
>>> +		((delay		& 0xf) << 3) |
>>> +		((input		& 0x1) << 7) |
>>> +		((double_edge	& 0x1) << 8) |
>>> +		((invertclk	& 0x1) << 9) |
>>> +		((retime	& 0x1) << 10);
>>> +
>>> +	reg = pc->retiming[pin];
>>> +	syscon_write(reg, retime_config);
>>> +}
>>> +
>>> +static void stixxxx_pinconf_get_direction(struct stixxxx_pio_control *pc,
>>> +	int pin_id, unsigned long *config)
>>> +{
>>> +	unsigned long oe_value, pu_value, od_value;
>>> +	int pin = stixxxx_gpio_pin(pin_id);
>>> +
>>> +	oe_value = (syscon_read(pc->oe) >> pin) & 1;
>>> +	pu_value = (syscon_read(pc->pu) >> pin) & 1;
>>> +	od_value = (syscon_read(pc->od) >> pin) & 1;
>>> +
>>> +	STIXXXX_PINCONF_PACK_OE(*config, oe_value);
>>> +	STIXXXX_PINCONF_PACK_PU(*config, pu_value);
>>> +	STIXXXX_PINCONF_PACK_OD(*config, od_value);
>>> +}
>>> +
>>> +static int stixxxx_pinconf_get_retime_packed(
>>> +		struct stixxxx_pio_control *pc,
>>> +		int pin, unsigned long *config)
>>> +{
>>> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
>>> +	const struct stixxxx_retime_offset *offset = rt_params->retime_offset;
>>> +	unsigned long delay_bits, delay, rt_reduced;
>>> +	unsigned long rt_value[2];
>>> +	int i, j;
>>> +	int output = STIXXXX_PINCONF_UNPACK_OE(*config);
>>> +
>>> +	rt_value[0] = syscon_read(pc->retiming[0]);
>>> +	rt_value[1] = syscon_read(pc->retiming[1]);
>>> +
>>> +	rt_reduced = 0;
>>> +	for (i = 0; i < 2; i++) {
>>> +		for (j = 0; j < 4; j++) {
>>> +			if (rt_value[i] & (1<<((8*j)+pin)))
>>> +				rt_reduced |= 1 << ((i*4)+j);
>>> +		}
>>> +	}
>>> +
>>> +	STIXXXX_PINCONF_PACK_RT(*config,
>>> +			(rt_reduced >> offset->retime_offset) & 1);
>>> +	STIXXXX_PINCONF_PACK_RT_CLK(*config,
>>> +			(rt_reduced >> offset->clk1notclk0_offset) & 1);
>>> +	STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(*config,
>>> +			(rt_reduced >> offset->clknotdata_offset) & 1);
>>> +	STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(*config,
>>> +			(rt_reduced >> offset->double_edge_offset) & 1);
>>> +	STIXXXX_PINCONF_PACK_RT_INVERTCLK(*config,
>>> +			(rt_reduced >> offset->invertclk_offset) & 1);
>>> +
>>> +	delay_bits =  (((rt_reduced >> offset->delay_msb_offset) & 1)<<1) |
>>> +			((rt_reduced >> offset->delay_lsb_offset) & 1);
>>> +	delay =  stixxxx_pinconf_bit_to_delay(delay_bits, rt_params, output);
>>> +	STIXXXX_PINCONF_PACK_RT_DELAY(*config, delay);
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_pinconf_get_retime_dedicated(
>>> +		struct stixxxx_pio_control *pc,
>>> +		int pin, unsigned long *config)
>>> +{
>>> +	unsigned long value;
>>> +	unsigned long delay_bits, delay;
>>> +	const struct stixxxx_retime_params *rt_params = pc->rt_params;
>>> +	int output = STIXXXX_PINCONF_UNPACK_OE(*config);
>>> +
>>> +	value = syscon_read(pc->retiming[pin]);
>>> +	STIXXXX_PINCONF_PACK_RT_CLK(*config, ((value >> 0) & 0x3));
>>> +	STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(*config, ((value >> 2) & 0x1));
>>> +	delay_bits = ((value >> 3) & 0xf);
>>> +	delay =  stixxxx_pinconf_bit_to_delay(delay_bits, rt_params, output);
>>> +	STIXXXX_PINCONF_PACK_RT_DELAY(*config, delay);
>>> +	STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(*config, ((value >> 8) & 0x1));
>>> +	STIXXXX_PINCONF_PACK_RT_INVERTCLK(*config, ((value >> 9) & 0x1));
>>> +	STIXXXX_PINCONF_PACK_RT(*config, ((value >> 10) & 0x1));
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +/* GPIO related functions */
>>> +
>>> +static inline void __stixxxx_gpio_set(struct stixxxx_gpio_port *port,
>>> +	unsigned offset, int value)
>>> +{
>>> +	if (value)
>>> +		writel(BIT(offset), port->base + REG_PIO_SET_POUT);
>>> +	else
>>> +		writel(BIT(offset), port->base + REG_PIO_CLR_POUT);
>>> +}
>>> +
>>> +static void stixxxx_gpio_direction(unsigned int gpio, unsigned int direction)
>>> +{
>>> +	int port_num = stixxxx_gpio_port(gpio);
>>> +	int offset = stixxxx_gpio_pin(gpio);
>>> +	struct stixxxx_gpio_port *port  = gpio_ports[port_num];
>>> +	int i = 0;
>>> +
>>> +	for (i = 0; i <= 2; i++) {
>>> +		if (direction & BIT(i))
>>> +			writel(BIT(offset), port->base + REG_PIO_SET_PC(i));
>>> +		else
>>> +			writel(BIT(offset), port->base + REG_PIO_CLR_PC(i));
>>> +	}
>>> +}
>>> +
>>> +static int stixxxx_gpio_request(struct gpio_chip *chip, unsigned offset)
>>> +{
>>> +	return pinctrl_request_gpio(chip->base + offset);
>>> +}
>>> +
>>> +static void stixxxx_gpio_free(struct gpio_chip *chip, unsigned offset)
>>> +{
>>> +	pinctrl_free_gpio(chip->base + offset);
>>> +}
>>> +
>>> +static int stixxxx_gpio_get(struct gpio_chip *chip, unsigned offset)
>>> +{
>>> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
>>> +
>>> +	return (readl(port->base + REG_PIO_PIN) >> offset) & 1;
>>> +}
>>> +
>>> +static void stixxxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
>>> +{
>>> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
>>> +	__stixxxx_gpio_set(port, offset, value);
>>> +}
>>> +
>>> +static int stixxxx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
>>> +{
>>> +	pinctrl_gpio_direction_input(chip->base + offset);
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_gpio_direction_output(struct gpio_chip *chip,
>>> +	unsigned offset, int value)
>>> +{
>>> +	struct stixxxx_gpio_port *port = to_stixxxx_gpio_port(chip);
>>> +
>>> +	__stixxxx_gpio_set(port, offset, value);
>>> +	pinctrl_gpio_direction_output(chip->base + offset);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_gpio_xlate(struct gpio_chip *gc,
>>> +			const struct of_phandle_args *gpiospec, u32 *flags)
>>> +{
>>> +	if (WARN_ON(gc->of_gpio_n_cells < 1))
>>> +		return -EINVAL;
>>> +
>>> +	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
>>> +		return -EINVAL;
>>> +
>>> +	if (gpiospec->args[0] > gc->ngpio)
>>> +		return -EINVAL;
>>> +
>>> +	return gpiospec->args[0];
>>> +}
>>> +
>>> +/* Pinctrl Groups */
>>> +static int stixxxx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +
>>> +	return info->ngroups;
>>> +}
>>> +
>>> +static const char *stixxxx_pctl_get_group_name(struct pinctrl_dev *pctldev,
>>> +				       unsigned selector)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +
>>> +	return info->groups[selector].name;
>>> +}
>>> +
>>> +static int stixxxx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
>>> +	unsigned selector, const unsigned **pins, unsigned *npins)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +
>>> +	if (selector >= info->ngroups)
>>> +		return -EINVAL;
>>> +
>>> +	*pins = info->groups[selector].pins;
>>> +	*npins = info->groups[selector].npins;
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static const inline struct stixxxx_pctl_group *stixxxx_pctl_find_group_by_name(
>>> +	const struct stixxxx_pinctrl *info, const char *name)
>>> +{
>>> +	int i;
>>> +
>>> +	for (i = 0; i < info->ngroups; i++) {
>>> +		if (!strcmp(info->groups[i].name, name))
>>> +			return &info->groups[i];
>>> +	}
>>> +
>>> +	return NULL;
>>> +}
>>> +
>>> +static int stixxxx_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
>>> +	struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +	const struct stixxxx_pctl_group *grp;
>>> +	struct pinctrl_map *new_map;
>>> +	struct device_node *parent;
>>> +	int map_num, i;
>>> +
>>> +	grp = stixxxx_pctl_find_group_by_name(info, np->name);
>>> +	if (!grp) {
>>> +		dev_err(info->dev, "unable to find group for node %s\n",
>>> +			np->name);
>>> +		return -EINVAL;
>>> +	}
>>> +
>>> +	map_num = grp->npins + 1;
>>> +	new_map = devm_kzalloc(pctldev->dev,
>>> +				sizeof(*new_map) * map_num, GFP_KERNEL);
>>> +	if (!new_map)
>>> +		return -ENOMEM;
>>> +
>>> +	parent = of_get_parent(np);
>>> +	if (!parent) {
>>> +		devm_kfree(pctldev->dev, new_map);
>>> +		return -EINVAL;
>>> +	}
>>> +
>>> +	*map = new_map;
>>> +	*num_maps = map_num;
>>> +	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
>>> +	new_map[0].data.mux.function = parent->name;
>>> +	new_map[0].data.mux.group = np->name;
>>> +	of_node_put(parent);
>>> +
>>> +	/* create config map per pin */
>>> +	new_map++;
>>> +	for (i = 0; i < grp->npins; i++) {
>>> +		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
>>> +		new_map[i].data.configs.group_or_pin =
>>> +				pin_get_name(pctldev, grp->pins[i]);
>>> +		new_map[i].data.configs.configs = &grp->pin_conf[i].config;
>>> +		new_map[i].data.configs.num_configs = 1;
>>> +	}
>>> +	dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
>>> +		(*map)->data.mux.function, grp->name, map_num);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void stixxxx_pctl_dt_free_map(struct pinctrl_dev *pctldev,
>>> +				struct pinctrl_map *map, unsigned num_maps)
>>> +{
>>> +}
>>> +
>>> +static struct pinctrl_ops stixxxx_pctlops = {
>>> +	.get_groups_count	= stixxxx_pctl_get_groups_count,
>>> +	.get_group_pins		= stixxxx_pctl_get_group_pins,
>>> +	.get_group_name		= stixxxx_pctl_get_group_name,
>>> +	.dt_node_to_map		= stixxxx_pctl_dt_node_to_map,
>>> +	.dt_free_map		= stixxxx_pctl_dt_free_map,
>>> +};
>>> +
>>> +/* Pinmux */
>>> +static int stixxxx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +
>>> +	return info->nfunctions;
>>> +}
>>> +
>>> +const char *stixxxx_pmx_get_fname(struct pinctrl_dev *pctldev,
>>> +	unsigned selector)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +
>>> +	return info->functions[selector].name;
>>> +}
>>> +
>>> +static int stixxxx_pmx_get_groups(struct pinctrl_dev *pctldev,
>>> +	unsigned selector, const char * const **grps, unsigned * const ngrps)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +	*grps = info->functions[selector].groups;
>>> +	*ngrps = info->functions[selector].ngroups;
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static struct stixxxx_pio_control *stixxxx_get_pio_control(
>>> +			struct stixxxx_pinctrl *info, int pin_id)
>>> +{
>>> +	int port = stixxxx_gpio_port(pin_id);
>>> +	return &info->pio_controls[port];
>>> +}
>>> +
>>> +static int stixxxx_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
>>> +		unsigned group)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +	struct stixxxx_pinconf *conf = info->groups[group].pin_conf;
>>> +	struct stixxxx_pio_control *pc;
>>> +	int i;
>>> +
>>> +	for (i = 0; i < info->groups[group].npins; i++) {
>>> +		pc = stixxxx_get_pio_control(info, conf[i].pin);
>>> +		stixxxx_pctl_set_function(pc, conf[i].pin,
>>> +					info->groups[group].altfunc);
>>> +	}
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void stixxxx_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
>>> +		unsigned group)
>>> +{
>>> +}
>>> +
>>> +static int stixxxx_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
>>> +			struct pinctrl_gpio_range *range, unsigned gpio,
>>> +			bool input)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +	struct stixxxx_pio_control *pc = &info->pio_controls[range->id];
>>> +	/*
>>> +	 * When a PIO port is used in its primary function mode (altfunc = 0)
>>> +	 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
>>> +	 * for the primary PIO functions are driven by the related PIO block
>>> +	 */
>>> +	stixxxx_pctl_set_function(pc, gpio, 0);
>>> +	stixxxx_gpio_direction(gpio, input ?
>>> +		STIXXXX_GPIO_DIRECTION_IN : STIXXXX_GPIO_DIRECTION_OUT);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static struct pinmux_ops stixxxx_pmxops = {
>>> +	.get_functions_count	= stixxxx_pmx_get_funcs_count,
>>> +	.get_function_name	= stixxxx_pmx_get_fname,
>>> +	.get_function_groups	= stixxxx_pmx_get_groups,
>>> +	.enable			= stixxxx_pmx_enable,
>>> +	.disable		= stixxxx_pmx_disable,
>>> +	.gpio_set_direction	= stixxxx_pmx_set_gpio_direction,
>>> +};
>>> +
>>> +/* Pinconf  */
>>> +static void stixxxx_pinconf_get_retime(struct stixxxx_pio_control *pc,
>>> +	int pin_id, unsigned long *config)
>>> +{
>>> +	int pin = stixxxx_gpio_pin(pin_id);
>>> +	if (pc->rt_style == stixxxx_retime_style_packed)
>>> +		stixxxx_pinconf_get_retime_packed(pc, pin, config);
>>> +	else if (pc->rt_style == stixxxx_retime_style_dedicated)
>>> +		if ((BIT(pin) & pc->rt_pin_mask))
>>> +			stixxxx_pinconf_get_retime_dedicated(pc, pin, config);
>>> +}
>>> +
>>> +static void stixxxx_pinconf_set_retime(struct stixxxx_pio_control *pc,
>>> +	int pin_id, unsigned long config)
>>> +{
>>> +	int pin = stixxxx_gpio_pin(pin_id);
>>> +
>>> +	if (pc->rt_style == stixxxx_retime_style_packed)
>>> +		stixxxx_pinconf_set_retime_packed(pc, config, pin);
>>> +	else if (pc->rt_style == stixxxx_retime_style_dedicated)
>>> +		if ((BIT(pin) & pc->rt_pin_mask))
>>> +			stixxxx_pinconf_set_retime_dedicated(pc, config, pin);
>>> +}
>>> +
>>> +static int stixxxx_pinconf_set(struct pinctrl_dev *pctldev,
>>> +			     unsigned pin_id, unsigned long config)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +	struct stixxxx_pio_control *pc = stixxxx_get_pio_control(info, pin_id);
>>> +
>>> +	stixxxx_pinconf_set_direction(pc, pin_id, config);
>>> +	stixxxx_pinconf_set_retime(pc, pin_id, config);
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_pinconf_get(struct pinctrl_dev *pctldev,
>>> +			     unsigned pin_id, unsigned long *config)
>>> +{
>>> +	struct stixxxx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>>> +	struct stixxxx_pio_control *pc = stixxxx_get_pio_control(info, pin_id);
>>> +
>>> +	*config = 0;
>>> +	stixxxx_pinconf_get_direction(pc, pin_id, config);
>>> +	stixxxx_pinconf_get_retime(pc, pin_id, config);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void stixxxx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>>> +				   struct seq_file *s, unsigned pin_id)
>>> +{
>>> +	unsigned long config;
>>> +	stixxxx_pinconf_get(pctldev, pin_id, &config);
>>> +
>>> +	seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n"
>>> +		"\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
>>> +		"de:%ld,rt-clk:%ld,rt-delay:%ld]",
>>> +		STIXXXX_PINCONF_UNPACK_OE(config),
>>> +		STIXXXX_PINCONF_UNPACK_PU(config),
>>> +		STIXXXX_PINCONF_UNPACK_OD(config),
>>> +		STIXXXX_PINCONF_UNPACK_RT(config),
>>> +		STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(config),
>>> +		STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(config),
>>> +		STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
>>> +		STIXXXX_PINCONF_UNPACK_RT_CLK(config),
>>> +		STIXXXX_PINCONF_UNPACK_RT_DELAY(config));
>>> +}
>>> +
>>> +static struct pinconf_ops stixxxx_confops = {
>>> +	.pin_config_get		= stixxxx_pinconf_get,
>>> +	.pin_config_set		= stixxxx_pinconf_set,
>>> +	.pin_config_dbg_show	= stixxxx_pinconf_dbg_show,
>>> +};
>>> +
>>> +/* pinctrl */
>>> +static struct pinctrl_desc stixxxx_pctl_desc = {
>>> +	.owner		= THIS_MODULE,
>>> +	.pctlops	= &stixxxx_pctlops,
>>> +	.pmxops		= &stixxxx_pmxops,
>>> +	.confops	= &stixxxx_confops,
>>> +};
>>> +
>>> +static int stixxxx_pinconf_dt_parse_rt_params(struct stixxxx_pinctrl *info,
>>> +	struct device_node *np,	struct stixxxx_retime_params *params)
>>> +{
>>> +	const __be32 *ip;
>>> +	struct device_node *offset_np;
>>> +	struct stixxxx_retime_offset *rt_offset;
>>> +	int delay_count = 0;
>>> +
>>> +	ip = of_get_property(np, "#retime-delay-cells", NULL);
>>> +	if (ip)
>>> +		delay_count = be32_to_cpup(ip);
>>> +	else
>>> +		pr_warn("No #retime-delay-cells specified\n");
>>> +
>>> +	params->num_delay_times_out = delay_count;
>>> +	params->num_delay_times_in = delay_count;
>>> +	params->delay_times_in = devm_kzalloc(info->dev,
>>> +				sizeof(u32) * delay_count, GFP_KERNEL);
>>> +	params->delay_times_out = devm_kzalloc(info->dev,
>>> +				sizeof(u32) * delay_count, GFP_KERNEL);
>>> +
>>> +	if (!params->delay_times_in || !params->delay_times_out)
>>> +		return -ENOMEM;
>>> +
>>> +	of_property_read_u32_array(np, "st,retime-in-delay",
>>> +				(u32 *)params->delay_times_in, delay_count);
>>> +	of_property_read_u32_array(np, "st,retime-out-delay",
>>> +				(u32 *)params->delay_times_out, delay_count);
>>> +
>>> +	offset_np = of_parse_phandle(np, "st,retime-offset", 0);
>>> +
>>> +	if (offset_np) {
>>> +		rt_offset = devm_kzalloc(info->dev,
>>> +				sizeof(*rt_offset), GFP_KERNEL);
>>> +		if (!rt_offset)
>>> +			return -ENOMEM;
>>> +
>>> +		params->retime_offset = rt_offset;
>>> +		WARN_ON(of_property_read_u32(offset_np, "retime",
>>> +					&rt_offset->retime_offset));
>>> +		WARN_ON(of_property_read_u32(offset_np, "clk1notclk0",
>>> +					&rt_offset->clk1notclk0_offset));
>>> +		WARN_ON(of_property_read_u32(offset_np, "clknotdata",
>>> +					&rt_offset->clknotdata_offset));
>>> +		WARN_ON(of_property_read_u32(offset_np, "double-edge",
>>> +					&rt_offset->double_edge_offset));
>>> +		WARN_ON(of_property_read_u32(offset_np, "invertclk",
>>> +					&rt_offset->invertclk_offset));
>>> +		WARN_ON(of_property_read_u32(offset_np, "delay-lsb",
>>> +					&rt_offset->delay_lsb_offset));
>>> +		WARN_ON(of_property_read_u32(offset_np, "delay-msb",
>>> +					&rt_offset->delay_msb_offset));
>>> +	}
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static const char *gpio_compat = "st,stixxxx-gpio";
>>> +
>>> +static void stixxxx_pctl_dt_child_count(struct stixxxx_pinctrl *info,
>>> +				     struct device_node *np)
>>> +{
>>> +	struct device_node *child;
>>> +	for_each_child_of_node(np, child) {
>>> +		if (of_device_is_compatible(child, gpio_compat)) {
>>> +			info->nbanks++;
>>> +		} else {
>>> +			info->nfunctions++;
>>> +			info->ngroups += of_get_child_count(child);
>>> +		}
>>> +	}
>>> +}
>>> +
>>> +static int stixxxx_pctl_dt_get_retime_conf(struct device_node *np,
>>> +	struct stixxxx_pio_control *pc)
>>> +{
>>> +	const char *style;
>>> +	char name[20];
>>> +	unsigned int j;
>>> +	of_property_read_string(np, "st,retime-style", &style);
>>> +
>>> +	if (strcmp(style, "packed") == 0) {
>>> +		pc->rt_style = stixxxx_retime_style_packed;
>>> +		for (j = 0; j < 2; j++) {
>>> +			snprintf(name, sizeof(name), "st,retime-control%d", j);
>>> +			pc->retiming[j] = syscon_claim(np, name);
>>> +			if (!pc->retiming[j])
>>> +				return -ENODATA;
>>> +		}
>>> +	} else if (strcmp(style, "dedicated") == 0) {
>>> +		pc->rt_style = stixxxx_retime_style_dedicated;
>>> +		for (j = 0; j < 8; j++) {
>>> +			if ((1<<j) & pc->rt_pin_mask) {
>>> +				snprintf(name, sizeof(name),
>>> +						"st,retime-control%d", j);
>>> +				pc->retiming[j] = syscon_claim(np, name);
>>> +				if (!pc->retiming[j])
>>> +					return -ENODATA;
>>> +			}
>>> +		}
>>> +	} else if (strcmp(style, "none") == 0) {
>>> +		pc->rt_style = stixxxx_retime_style_none;
>>> +	}
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_pctl_dt_init(struct stixxxx_pinctrl *info,
>>> +			struct device_node *np)
>>> +{
>>> +	struct stixxxx_pio_control *pc;
>>> +	struct stixxxx_retime_params *rt_params;
>>> +	struct device *dev = info->dev;
>>> +	unsigned int i = 0;
>>> +	struct device_node *child = NULL;
>>> +
>>> +	pc = devm_kzalloc(dev, sizeof(*pc) * info->nbanks, GFP_KERNEL);
>>> +	rt_params = devm_kzalloc(dev, sizeof(*rt_params), GFP_KERNEL);
>>> +
>>> +	if (!pc || !rt_params)
>>> +		return -ENOMEM;
>>> +
>>> +	info->pio_controls = pc;
>>> +	if (stixxxx_pinconf_dt_parse_rt_params(info, np, rt_params))
>>> +		return -ENOMEM;
>>> +
>>> +	for_each_child_of_node(np, child) {
>>> +		if (of_device_is_compatible(child, gpio_compat)) {
>>> +			pc[i].rt_params = rt_params;
>>> +
>>> +			pc[i].alt = syscon_claim(child, "st,alt-control");
>>> +			if (!pc[i].alt)
>>> +				goto failed;
>>> +
>>> +			pc[i].oe = syscon_claim(child, "st,oe-control");
>>> +			if (!pc[i].oe)
>>> +				goto failed;
>>> +
>>> +			pc[i].pu = syscon_claim(child, "st,pu-control");
>>> +			if (!pc[i].pu)
>>> +				goto failed;
>>> +
>>> +			pc[i].od = syscon_claim(child, "st,od-control");
>>> +			if (!pc[i].od)
>>> +				goto failed;
>>> +
>>> +			of_property_read_u32(child, "st,retime-pin-mask",
>>> +							&pc[i].rt_pin_mask);
>>> +
>>> +			stixxxx_pctl_dt_get_retime_conf(child, &pc[i]);
>>> +			i++;
>>> +		}
>>> +	}
>>> +
>>> +	return 0;
>>> +failed:
>>> +	return -ENODATA;
>>> +}
>>> +
>>> +#define OF_GPIO_ARGS_MIN	(3)
>>> +/*
>>> + * Each pin is represented in of the below forms.
>>> + * <bank offset direction func rt_type rt_delay rt_clk>
>>> + */
>>> +static int stixxxx_pctl_dt_parse_groups(struct device_node *np,
>>> +	struct stixxxx_pctl_group *grp, struct stixxxx_pinctrl *info, int idx)
>>> +{
>>> +	/* bank pad direction val altfunction */
>>> +	const __be32 *list;
>>> +	struct property *pp;
>>> +	struct stixxxx_pinconf *conf;
>>> +	phandle phandle;
>>> +	struct device_node *pins;
>>> +	u32 pin;
>>> +	int i = 0, npins = 0, nr_props;
>>> +
>>> +	pins = of_get_child_by_name(np, "st,pins");
>>> +	if (!pins)
>>> +		return -ENODATA;
>>> +
>>> +	for_each_property_of_node(pins, pp) {
>>> +		/* Skip those we do not want to proceed */
>>> +		if (!strcmp(pp->name, "name"))
>>> +			continue;
>>> +
>>> +		if (pp  && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
>>> +			npins++;
>>> +		} else {
>>> +			pr_warn("Invalid st,pins in %s node\n", np->name);
>>> +			return -EINVAL;
>>> +		}
>>> +	}
>>> +
>>> +	grp->npins = npins;
>>> +	grp->name = np->name;
>>> +	grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL);
>>> +	grp->pin_conf = devm_kzalloc(info->dev,
>>> +					npins * sizeof(*conf), GFP_KERNEL);
>>> +	of_property_read_u32(np, "st,function", &grp->altfunc);
>>> +
>>> +	if (!grp->pins || !grp->pin_conf)
>>> +		return -ENOMEM;
>>> +
>>> +	/* <bank offset direction func rt_type rt_delay rt_clk> */
>>> +	for_each_property_of_node(pins, pp) {
>>> +		if (!strcmp(pp->name, "name"))
>>> +			continue;
>>> +		nr_props = pp->length/sizeof(u32);
>>> +		list = pp->value;
>>> +		conf = &grp->pin_conf[i];
>>> +
>>> +		/* bank & offset */
>>> +		phandle = be32_to_cpup(list++);
>>> +		pin = be32_to_cpup(list++);
>>> +		conf->pin = of_get_named_gpio(pins, pp->name, 0);
>>> +		conf->name = pp->name;
>>> +		grp->pins[i] = conf->pin;
>>> +
>>> +		conf->config = 0;
>>> +		/* direction */
>>> +		conf->config |= be32_to_cpup(list++);
>>> +		/* rt_type rt_delay rt_clk */
>>> +		if (nr_props >= OF_GPIO_ARGS_MIN + 2) {
>>> +			/* rt_type */
>>> +			conf->config |= be32_to_cpup(list++);
>>> +			/* rt_delay */
>>> +			conf->config |= be32_to_cpup(list++);
>>> +			/* rt_clk */
>>> +			if (nr_props > OF_GPIO_ARGS_MIN + 2)
>>> +				conf->config |= be32_to_cpup(list++);
>>> +		}
>>> +		i++;
>>> +	}
>>> +	of_node_put(pins);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_pctl_parse_functions(struct device_node *np,
>>> +			struct stixxxx_pinctrl *info, u32 index, int *grp_index)
>>> +{
>>> +	struct device_node *child;
>>> +	struct stixxxx_pmx_func *func;
>>> +	struct stixxxx_pctl_group *grp;
>>> +	int ret, i;
>>> +
>>> +	func = &info->functions[index];
>>> +	func->name = np->name;
>>> +	func->ngroups = of_get_child_count(np);
>>> +	if (func->ngroups <= 0) {
>>> +		dev_err(info->dev, "No groups defined\n");
>>> +		return -EINVAL;
>>> +	}
>>> +	func->groups = devm_kzalloc(info->dev,
>>> +			func->ngroups * sizeof(char *), GFP_KERNEL);
>>> +	if (!func->groups)
>>> +		return -ENOMEM;
>>> +
>>> +	i = 0;
>>> +	for_each_child_of_node(np, child) {
>>> +		func->groups[i] = child->name;
>>> +		grp = &info->groups[*grp_index];
>>> +		*grp_index += 1;
>>> +		ret = stixxxx_pctl_dt_parse_groups(child, grp, info, i++);
>>> +		if (ret)
>>> +			return ret;
>>> +	}
>>> +	dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
>>> +				index, func->name, func->ngroups);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_pctl_probe_dt(struct platform_device *pdev,
>>> +				 struct stixxxx_pinctrl *info)
>>> +{
>>> +	int ret = 0;
>>> +	int i = 0, j = 0, k = 0;
>>> +	struct pinctrl_pin_desc *pdesc;
>>> +	struct device_node *np = pdev->dev.of_node;
>>> +	struct device_node *child;
>>> +	int grp_index = 0;
>>> +
>>> +	stixxxx_pctl_dt_child_count(info, np);
>>> +	if (info->nbanks < 1) {
>>> +		dev_err(&pdev->dev, "you need atleast one gpio bank\n");
>>> +		return -EINVAL;
>>> +	}
>>> +
>>> +	ret = stixxxx_pctl_dt_init(info, np);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
>>> +	dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
>>> +	dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
>>> +	info->functions = devm_kzalloc(&pdev->dev,
>>> +		info->nfunctions * sizeof(*info->functions), GFP_KERNEL);
>>> +
>>> +	info->groups = devm_kzalloc(&pdev->dev,
>>> +		info->ngroups * sizeof(*info->groups) ,	GFP_KERNEL);
>>> +
>>> +	if (!info->functions || !info->groups)
>>> +		return -ENOMEM;
>>> +
>>> +	stixxxx_pctl_desc.npins = info->nbanks * STIXXXX_GPIO_PINS_PER_PORT;
>>> +	pdesc =	devm_kzalloc(&pdev->dev,
>>> +			sizeof(*pdesc) * stixxxx_pctl_desc.npins, GFP_KERNEL);
>>> +	if (!pdesc)
>>> +		return -ENOMEM;
>>> +
>>> +	stixxxx_pctl_desc.pins = pdesc;
>>> +
>>> +	for_each_child_of_node(np, child) {
>>> +		if (of_device_is_compatible(child, gpio_compat)) {
>>> +			for (j = 0; j < STIXXXX_GPIO_PINS_PER_PORT; j++, k++) {
>>> +				const char *port_name = NULL;
>>> +				pdesc->number = k;
>>> +				of_property_read_string(child, "st,bank-name",
>>> +							&port_name);
>>> +				pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
>>> +							port_name ? : "PIO",
>>> +							port_name ? j : k);
>>> +				pdesc++;
>>> +			}
>>> +		} else {
>>> +			ret = stixxxx_pctl_parse_functions(child, info,
>>> +							i++, &grp_index);
>>> +			if (ret) {
>>> +				dev_err(&pdev->dev, "No functions found.\n");
>>> +				return ret;
>>> +			}
>>> +		}
>>> +	}
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int stixxxx_pctl_probe(struct platform_device *pdev)
>>> +{
>>> +	struct stixxxx_pinctrl *info;
>>> +	int ret, i;
>>> +
>>> +	if (!pdev->dev.of_node) {
>>> +		dev_err(&pdev->dev, "device node not found.\n");
>>> +		return -EINVAL;
>>> +	}
>>> +
>>> +	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
>>> +	if (!info)
>>> +		return -ENOMEM;
>>> +
>>> +	info->dev = &pdev->dev;
>>> +	platform_set_drvdata(pdev, info);
>>> +	ret = stixxxx_pctl_probe_dt(pdev, info);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	stixxxx_pctl_desc.name = dev_name(&pdev->dev);
>>> +	info->pctl = pinctrl_register(&stixxxx_pctl_desc, &pdev->dev, info);
>>> +	if (IS_ERR(info->pctl)) {
>>> +		dev_err(&pdev->dev, "Failed pinctrl registration\n");
>>> +		return PTR_ERR(info->pctl);
>>> +	}
>>> +
>>> +	for (i = 0; i < info->nbanks; i++)
>>> +		pinctrl_add_gpio_range(info->pctl, &gpio_ports[i]->range);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static struct gpio_chip stixxxx_gpio_template = {
>>> +	.request		= stixxxx_gpio_request,
>>> +	.free			= stixxxx_gpio_free,
>>> +	.get			= stixxxx_gpio_get,
>>> +	.set			= stixxxx_gpio_set,
>>> +	.direction_input	= stixxxx_gpio_direction_input,
>>> +	.direction_output	= stixxxx_gpio_direction_output,
>>> +	.ngpio			= STIXXXX_GPIO_PINS_PER_PORT,
>>> +	.of_gpio_n_cells	= 1,
>>> +	.of_xlate		= stixxxx_gpio_xlate,
>>> +};
>>> +
>>> +static int stixxxx_gpio_probe(struct platform_device *pdev)
>>> +{
>>> +	struct stixxxx_gpio_port *port;
>>> +	struct pinctrl_gpio_range *range;
>>> +	struct device_node *np  = pdev->dev.of_node;
>>> +	int port_num = of_alias_get_id(np, "gpio");
>>> +	struct resource *res;
>>> +	int err;
>>> +
>>> +	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
>>> +	if (!port)
>>> +		return -ENOMEM;
>>> +
>>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +	port->base = devm_request_and_ioremap(&pdev->dev, res);
>>> +	if (!port->base) {
>>> +		dev_err(&pdev->dev, "Can't get IO memory mapping!\n");
>>> +		return -ENODEV;
>>> +	}
>>> +
>>> +	of_property_read_string(np, "st,bank-name", &port->bank_name);
>>> +	port->of_node = np;
>>> +
>>> +	port->gpio_chip = stixxxx_gpio_template;
>>> +	port->gpio_chip.base = port_num * STIXXXX_GPIO_PINS_PER_PORT;
>>> +	port->gpio_chip.ngpio = STIXXXX_GPIO_PINS_PER_PORT;
>>> +	port->gpio_chip.of_node = np;
>>> +	port->gpio_chip.label = dev_name(&pdev->dev);
>>> +
>>> +	dev_set_drvdata(&pdev->dev, port);
>>> +	range = &port->range;
>>> +	range->name = port->gpio_chip.label;
>>> +	range->id = port_num;
>>> +	range->pin_base = range->base = range->id * STIXXXX_GPIO_PINS_PER_PORT;
>>> +	range->npins = port->gpio_chip.ngpio;
>>> +	range->gc = &port->gpio_chip;
>>> +	gpio_ports[port_num] = port;
>>> +	err  = gpiochip_add(&port->gpio_chip);
>>> +	if (err) {
>>> +		dev_err(&pdev->dev, "Failed to add gpiochip(%d)!\n", port_num);
>>> +		return err;
>>> +	}
>>> +	dev_info(&pdev->dev, "gpioport[%s] Added as bank%d\n",
>>> +				port->bank_name, port_num);
>>> +	return 0;
>>> +}
>>> +
>>> +static struct of_device_id stixxxx_gpio_of_match[] = {
>>> +	{ .compatible = "st,stixxxx-gpio", },
>>> +	{ /* sentinel */ }
>>> +};
>>> +
>>> +static struct platform_driver stixxxx_gpio_driver = {
>>> +	.driver = {
>>> +		.name = "st-gpio",
>>> +		.owner = THIS_MODULE,
>>> +		.of_match_table = of_match_ptr(stixxxx_gpio_of_match),
>>> +	},
>>> +	.probe = stixxxx_gpio_probe,
>>> +};
>>> +
>>> +static struct of_device_id stixxxx_pctl_of_match[] = {
>>> +	{ .compatible = "st,stixxxx-pinctrl",},
>>> +	{ /* sentinel */ }
>>> +};
>>> +
>>> +static struct platform_driver stixxxx_pctl_driver = {
>>> +	.driver = {
>>> +		.name = "st-pinctrl",
>>> +		.owner = THIS_MODULE,
>>> +		.of_match_table = of_match_ptr(stixxxx_pctl_of_match),
>>> +	},
>>> +	.probe = stixxxx_pctl_probe,
>>> +};
>>> +
>>> +static int __init stixxxx_pctl_init(void)
>>> +{
>>> +	int ret = platform_driver_register(&stixxxx_gpio_driver);
>>> +	if (ret)
>>> +		return ret;
>>> +	return platform_driver_register(&stixxxx_pctl_driver);
>>> +}
>>> +arch_initcall(stixxxx_pctl_init);
>>> diff --git a/drivers/pinctrl/pinctrl-stixxxx.h b/drivers/pinctrl/pinctrl-stixxxx.h
>>> new file mode 100644
>>> index 0000000..a340964
>>> --- /dev/null
>>> +++ b/drivers/pinctrl/pinctrl-stixxxx.h
>>> @@ -0,0 +1,197 @@
>>> +
>>> +/*
>>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
>>> + * Authors:
>>> + *	Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#ifndef __LINUX_DRIVERS_PINCTRL_STIXXXX_H
>>> +#define __LINUX_DRIVERS_PINCTRL_STIXXXX_H
>>> +
>>> +enum stixxxx_retime_style {
>>> +	stixxxx_retime_style_none,
>>> +	stixxxx_retime_style_packed,
>>> +	stixxxx_retime_style_dedicated,
>>> +};
>>> +
>>> +/* Byte positions in 2 syscon words, starts from 0 */
>>> +struct stixxxx_retime_offset {
>>> +	int retime_offset;
>>> +	int clk1notclk0_offset;
>>> +	int clknotdata_offset;
>>> +	int double_edge_offset;
>>> +	int invertclk_offset;
>>> +	int delay_lsb_offset;
>>> +	int delay_msb_offset;
>>> +};
>>> +
>>> +struct stixxxx_retime_params {
>>> +	const struct stixxxx_retime_offset *retime_offset;
>>> +	unsigned int *delay_times_in;
>>> +	int num_delay_times_in;
>>> +	unsigned int *delay_times_out;
>>> +	int num_delay_times_out;
>>> +};
>>> +
>>> +struct stixxxx_pio_control {
>>> +	enum stixxxx_retime_style rt_style;
>>> +	u32 rt_pin_mask;
>>> +	const struct stixxxx_retime_params *rt_params;
>>> +	struct syscon_field *alt;
>>> +	struct syscon_field *oe, *pu, *od;
>>> +	struct syscon_field *retiming[8];
>>> +};
>>> +
>>> +/* PIO Block registers */
>>> +/* PIO output */
>>> +#define REG_PIO_POUT			0x00
>>> +/* Set bits of POUT */
>>> +#define REG_PIO_SET_POUT		0x04
>>> +/* Clear bits of POUT */
>>> +#define REG_PIO_CLR_POUT		0x08
>>> +/* PIO input */
>>> +#define REG_PIO_PIN			0x10
>>> +/* PIO configuration */
>>> +#define REG_PIO_PC(n)			(0x20 + (n) * 0x10)
>>> +/* Set bits of PC[2:0] */
>>> +#define REG_PIO_SET_PC(n)		(0x24 + (n) * 0x10)
>>> +/* Clear bits of PC[2:0] */
>>> +#define REG_PIO_CLR_PC(n)		(0x28 + (n) * 0x10)
>>> +/* PIO input comparison */
>>> +#define REG_PIO_PCOMP			0x50
>>> +/* Set bits of PCOMP */
>>> +#define REG_PIO_SET_PCOMP		0x54
>>> +/* Clear bits of PCOMP */
>>> +#define REG_PIO_CLR_PCOMP		0x58
>>> +/* PIO input comparison mask */
>>> +#define REG_PIO_PMASK			0x60
>>> +/* Set bits of PMASK */
>>> +#define REG_PIO_SET_PMASK		0x64
>>> +/* Clear bits of PMASK */
>>> +#define REG_PIO_CLR_PMASK		0x68
>>> +
>>> +#define STIXXXX_MAX_GPIO_BANKS		32
>>> +
>>> +#define STIXXXX_GPIO_DIRECTION_BIDIR	0x1
>>> +#define STIXXXX_GPIO_DIRECTION_OUT	0x2
>>> +#define STIXXXX_GPIO_DIRECTION_IN	0x4
>>> +
>>> +#define STIXXXX_GPIO_PINS_PER_PORT	8
>>> +#define stixxxx_gpio_port(gpio) ((gpio) / STIXXXX_GPIO_PINS_PER_PORT)
>>> +#define stixxxx_gpio_pin(gpio) ((gpio) % STIXXXX_GPIO_PINS_PER_PORT)
>>> +
>>> +/* pinconf */
>>> +/*
>>> + * Pinconf is represented in an opaque unsigned long variable.
>>> + * Below is the bit allocation details for each possible configuration.
>>> + * All the bit fields can be encapsulated into four variables
>>> + * (direction, retime-type, retime-clk, retime-delay)
>>> + *
>>> + *	 +----------------+
>>> + *[31:28]| reserved-3     |
>>> + *	 +----------------+-------------
>>> + *[27]   |	oe	  |		|
>>> + *	 +----------------+		v
>>> + *[26]   |	pu	  |	[Direction	]
>>> + *	 +----------------+		^
>>> + *[25]   |	od	  |		|
>>> + *	 +----------------+-------------
>>> + *[24]   | reserved-2     |
>>> + *	 +----------------+-------------
>>> + *[23]   |    retime      |		|
>>> + *	 +----------------+		|
>>> + *[22]   | retime-invclk  |		|
>>> + *	 +----------------+		v
>>> + *[21]   |retime-clknotdat|	[Retime-type	]
>>> + *	 +----------------+		^
>>> + *[20]   | retime-de      |		|
>>> + *	 +----------------+-------------
>>> + *[19:18]| retime-clk     |------>[Retime-Clk	]
>>> + *	 +----------------+
>>> + *[17:16]|  reserved-1    |
>>> + *	 +----------------+
>>> + *[15..0]| retime-delay   |------>[Retime Delay]
>>> + *	 +----------------+
>>> + */
>>> +
>>> +#define STIXXXX_PINCONF_UNPACK(conf, param)\
>>> +				((conf >> STIXXXX_PINCONF_ ##param ##_SHIFT) \
>>> +				& STIXXXX_PINCONF_ ##param ##_MASK)
>>> +
>>> +#define STIXXXX_PINCONF_PACK(conf, val, param)	(conf |=\
>>> +				((val & STIXXXX_PINCONF_ ##param ##_MASK) << \
>>> +					STIXXXX_PINCONF_ ##param ##_SHIFT))
>>> +
>>> +/* Output enable */
>>> +#define STIXXXX_PINCONF_OE_MASK		0x1
>>> +#define STIXXXX_PINCONF_OE_SHIFT	27
>>> +#define STIXXXX_PINCONF_OE		BIT(27)
>>> +#define STIXXXX_PINCONF_UNPACK_OE(conf)	STIXXXX_PINCONF_UNPACK(conf, OE)
>>> +#define STIXXXX_PINCONF_PACK_OE(conf, val)  STIXXXX_PINCONF_PACK(conf, val, OE)
>>> +
>>> +/* Pull Up */
>>> +#define STIXXXX_PINCONF_PU_MASK		0x1
>>> +#define STIXXXX_PINCONF_PU_SHIFT	26
>>> +#define STIXXXX_PINCONF_PU		BIT(26)
>>> +#define STIXXXX_PINCONF_UNPACK_PU(conf)	STIXXXX_PINCONF_UNPACK(conf, PU)
>>> +#define STIXXXX_PINCONF_PACK_PU(conf, val) STIXXXX_PINCONF_PACK(conf, val, PU)
>>> +
>>> +/* Open Drain */
>>> +#define STIXXXX_PINCONF_OD_MASK		0x1
>>> +#define STIXXXX_PINCONF_OD_SHIFT	25
>>> +#define STIXXXX_PINCONF_OD		BIT(25)
>>> +#define STIXXXX_PINCONF_UNPACK_OD(conf)	STIXXXX_PINCONF_UNPACK(conf, OD)
>>> +#define STIXXXX_PINCONF_PACK_OD(conf, val) STIXXXX_PINCONF_PACK(conf, val, OD)
>>> +
>>> +#define STIXXXX_PINCONF_RT_MASK		0x1
>>> +#define STIXXXX_PINCONF_RT_SHIFT	23
>>> +#define STIXXXX_PINCONF_RT		BIT(23)
>>> +#define STIXXXX_PINCONF_UNPACK_RT(conf)	STIXXXX_PINCONF_UNPACK(conf, RT)
>>> +#define STIXXXX_PINCONF_PACK_RT(conf, val) STIXXXX_PINCONF_PACK(conf, val, RT)
>>> +
>>> +#define STIXXXX_PINCONF_RT_INVERTCLK_MASK	0x1
>>> +#define STIXXXX_PINCONF_RT_INVERTCLK_SHIFT	22
>>> +#define STIXXXX_PINCONF_RT_INVERTCLK		BIT(22)
>>> +#define STIXXXX_PINCONF_UNPACK_RT_INVERTCLK(conf) \
>>> +			STIXXXX_PINCONF_UNPACK(conf, RT_INVERTCLK)
>>> +#define STIXXXX_PINCONF_PACK_RT_INVERTCLK(conf, val) \
>>> +			STIXXXX_PINCONF_PACK(conf, val, RT_INVERTCLK)
>>> +
>>> +#define STIXXXX_PINCONF_RT_CLKNOTDATA_MASK	0x1
>>> +#define STIXXXX_PINCONF_RT_CLKNOTDATA_SHIFT	21
>>> +#define STIXXXX_PINCONF_RT_CLKNOTDATA		BIT(21)
>>> +#define STIXXXX_PINCONF_UNPACK_RT_CLKNOTDATA(conf)	\
>>> +				STIXXXX_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
>>> +#define STIXXXX_PINCONF_PACK_RT_CLKNOTDATA(conf, val) \
>>> +				STIXXXX_PINCONF_PACK(conf, val, RT_CLKNOTDATA)
>>> +
>>> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE_MASK	0x1
>>> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE_SHIFT	20
>>> +#define STIXXXX_PINCONF_RT_DOUBLE_EDGE		BIT(20)
>>> +#define STIXXXX_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
>>> +				STIXXXX_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
>>> +#define STIXXXX_PINCONF_PACK_RT_DOUBLE_EDGE(conf, val) \
>>> +				STIXXXX_PINCONF_PACK(conf, val, RT_DOUBLE_EDGE)
>>> +
>>> +#define STIXXXX_PINCONF_RT_CLK_MASK		0x3
>>> +#define STIXXXX_PINCONF_RT_CLK_SHIFT		18
>>> +#define STIXXXX_PINCONF_RT_CLK			BIT(18)
>>> +#define STIXXXX_PINCONF_UNPACK_RT_CLK(conf)	\
>>> +			STIXXXX_PINCONF_UNPACK(conf, RT_CLK)
>>> +#define STIXXXX_PINCONF_PACK_RT_CLK(conf, val) \
>>> +			STIXXXX_PINCONF_PACK(conf, val, RT_CLK)
>>> +
>>> +/* RETIME_DELAY in Pico Secs */
>>> +#define STIXXXX_PINCONF_RT_DELAY_MASK		0xffff
>>> +#define STIXXXX_PINCONF_RT_DELAY_SHIFT		0
>>> +#define STIXXXX_PINCONF_UNPACK_RT_DELAY(conf) \
>>> +				STIXXXX_PINCONF_UNPACK(conf, RT_DELAY)
>>> +#define STIXXXX_PINCONF_PACK_RT_DELAY(conf, val) \
>>> +				STIXXXX_PINCONF_PACK(conf, val, RT_DELAY)
>>> +
>>> +#endif /* __LINUX_DRIVERS_PINCTRL_STIXXXX_H */
>>> -- 
>>> 1.7.6.5
>>> 
>>> _______________________________________________
>>> devicetree-discuss mailing list
>>> devicetree-discuss at lists.ozlabs.org
>>> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 



From plagnioj at jcrosoft.com  Wed May  8 12:39:44 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 9 May 2013 00:39:44 +0800
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305081831.48566.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
 <20130508161527.GA28080@kroah.com> <201305081831.48566.arnd@arndb.de>
Message-ID: <0940EFC0-EB16-4C13-A3DE-4A8C4F5C6F4D@jcrosoft.com>


On May 9, 2013, at 12:31 AM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Wednesday 08 May 2013, Greg KH wrote:
>>> just mention there is not hardware reason to not use the generic ttySx
>>> in place of ttyAS as we have only one IP that handle serial on this
>>> family of SoC
>>> 
>>> personally I'll switch to ttySx
>> 
>> Great, then you can use the same major/minor range as well, so there's
>> no more objection from me about this :)
> 
> Does that work these days when you have kernel with multiple built-in
> uart drivers?

not for very long time and no this family
> 
> I think it would be good if all uarts were using the same name space
> and major/minor numbers, but I think the mess we currently have is
> the result of the tty_register_driver() interface reserving the
> device number range at driver load time, independent of the presence
> of devices.  I would assume that normal distro kernels always ship
> with an 8250 driver built-in to allow using that as the console,
> and if I read the code correctly, that currently prevents another
> uart driver from registering the same major/minor numbers.

so we need to fix this
> 
> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From will.deacon at arm.com  Wed May  8 12:43:41 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 17:43:41 +0100
Subject: [RFC PATCH v2 07/11] ARM64: mm: Make PAGE_NONE pages read only
 and no-execute.
In-Reply-To: <1368006763-30774-8-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-8-git-send-email-steve.capper@linaro.org>
Message-ID: <20130508164341.GG20820@mudshark.cambridge.arm.com>

On Wed, May 08, 2013 at 10:52:39AM +0100, Steve Capper wrote:
> If we consider the following code sequence:
> 
> 	my_pte = pte_modify(entry, myprot);
> 	x = pte_write(my_pte);
> 	y = pte_exec(my_pte);
> 
> If myprot comes from a PROT_NONE page, then x and y will both be
> true which is undesireable behaviour.
> 
> This patch sets the no-execute and read-only bits for PAGE_NONE
> such that the code above will return false for both x and y.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> ---
>  arch/arm64/include/asm/pgtable.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index e333a24..b1a1b59 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -66,7 +66,7 @@ extern pgprot_t pgprot_default;
>  
>  #define _MOD_PROT(p, b)		__pgprot_modify(p, 0, b)
>  
> -#define PAGE_NONE		__pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE)
> +#define PAGE_NONE		__pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_RDONLY | PTE_UXN)
>  #define PAGE_SHARED		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
>  #define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
>  #define PAGE_COPY		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
> @@ -76,7 +76,7 @@ extern pgprot_t pgprot_default;
>  #define PAGE_KERNEL		_MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
>  #define PAGE_KERNEL_EXEC	_MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
>  
> -#define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
> +#define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_RDONLY | PTE_UXN)
>  #define __PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
>  #define __PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
>  #define __PAGE_COPY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)

Whilst it's not strictly needed for pte_exec to work, I think you should
include PTE_PXN in the PAGE_NONE definitions as well.

Will


From nicolas.pitre at linaro.org  Wed May  8 12:45:12 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 8 May 2013 12:45:12 -0400 (EDT)
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305081831.48566.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
 <20130508161527.GA28080@kroah.com> <201305081831.48566.arnd@arndb.de>
Message-ID: <alpine.LFD.2.03.1305081239260.13109@syhkavp.arg>

On Wed, 8 May 2013, Arnd Bergmann wrote:

> On Wednesday 08 May 2013, Greg KH wrote:
> > > just mention there is not hardware reason to not use the generic ttySx
> > > in place of ttyAS as we have only one IP that handle serial on this
> > > family of SoC
> > > 
> > > personally I'll switch to ttySx
> > 
> > Great, then you can use the same major/minor range as well, so there's
> > no more objection from me about this :)
> 
> Does that work these days when you have kernel with multiple built-in
> uart drivers?
> 
> I think it would be good if all uarts were using the same name space
> and major/minor numbers, but I think the mess we currently have is
> the result of the tty_register_driver() interface reserving the
> device number range at driver load time, independent of the presence
> of devices.  I would assume that normal distro kernels always ship
> with an 8250 driver built-in to allow using that as the console,
> and if I read the code correctly, that currently prevents another
> uart driver from registering the same major/minor numbers.

I tried to fix this up over 10 years ago.  RMK tried as well. This 
failed because X86 people insisted on always having COM1 as /dev/ttyS0, 
COM3 as /dev/ttyS2 and so on, even when some of them weren't present.

A common and dynamic namespace eventually succeeded for hard disks.
Maybe people are ready to accept it for serial ports as well now?


Nicolas


From stephen.gallimore at st.com  Wed May  8 12:50:40 2013
From: stephen.gallimore at st.com (Stephen GALLIMORE)
Date: Wed, 8 May 2013 18:50:40 +0200
Subject: [RFC 5/8] ARM:stih41x: Add STiH415 SOC support
In-Reply-To: <201305081818.01927.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022297-2334-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081818.01927.arnd@arndb.de>
Message-ID: <A3BF01DB4A606149A4C20C4C4C808F6C3189E576E2@SAFEX1MAIL1.st.com>

Hi Arnd,

Thank you for the feedback so far.

> +/*
> + * A basic implementation of irq_set_wake that ensures wakeup source
> + * interrupts are not disabled during PM_SUSPEND_FREEZE.
> + */
> +static int stih41x_set_wake(struct irq_data *d, unsigned int on) {
> +	struct irq_desc *desc = irq_to_desc(d->irq);
> +
> +	if (on) {
> +		if (desc->action)
> +			desc->action->flags |= IRQF_NO_SUSPEND;
> +	} else {
> +		if (desc->action)
> +			desc->action->flags &= ~IRQF_NO_SUSPEND;
> +	}
> +	return 0;
> +}
> +
> +static void __init stih41x_irq_init(void) {
> +	gic_arch_extn.irq_set_wake = stih41x_set_wake;
> +	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
> +
> +	irqchip_init();
> +}
>
>This looks like it should be generic. Why do you need this?

On this point, I wrote it so I am happy to take some advice. Basically this was to allow us to wakeup from the new PM_SUSPEND_FREEZE state that was added at the beginning of the year, without having to pollute individual drivers (particularly the serial driver) with having to somehow change the IRQ flags, or uninstall/re-install the interrupt handler on suspend/resume when marked as a wakeup source with different flags. Those approaches all seemed too messy and not really the driver's responsibility and installing the interrupt handlers of all possible wakeup sources with IRQF_NO_SUSPEND regardless of if they are currently activated as a wakeup source or not also seemed wrong. The code I ended up with was inspired by the existing mach-mmp (mmp2) PM support which does the same thing, so it is not without precedent.

If you have a better solution, or a way to generalize this that would make sense for the ARM architecture as a whole, then we are more than happy to change.

Regards,
-stephen


From swarren at wwwdotorg.org  Wed May  8 12:53:53 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 10:53:53 -0600
Subject: [PATCH 2/4] ARM: tegra: pcie: Add tegra3 support
In-Reply-To: <1368010660-31465-2-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-2-git-send-email-jagarwal@nvidia.com>
Message-ID: <518A8321.6020401@wwwdotorg.org>

On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> - Enable PCIe root port 2 for Cardhu
> - Make private data structure for each SoC
> - Add required Tegra30 clocks and regulators
> - Add Tegra30 specific code in enable controller

> - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> - and should be applied on top of this.

Again, those two lines would go below the ---. And since that's all one
bullet point, why is the second line indented with a "-"?

> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

>  	pcie-controller {
>  		vdd-supply = <&pci_vdd_reg>;
>  		pex-clk-supply = <&pci_clk_reg>;
> +		avdd-supply = <&ldo2_reg>; /* required for tegra30 */

I would simply drop that comment, and perhaps even the whole line; this
is just an example after all, and doesn't need to cover the latest SoC.
Equally, the example SoC DTSI section is an example for Tegra20, so
making the example board DTS section contain a Tegra30 example would be
inconsistent. Tegra30 should be capitalized; it's a name.

Why is there no change to the "Required Properties" section of this
document? It should list the set of clocks and regulators that are
required. That section is the definitive reference, whereas the example
is just than; an example.

> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c

> +/* used to differentiate tegra chips code */
> +struct tegra_pcie_soc_data {
> +	unsigned int num_max_ports;

> +	unsigned int pads_pll_ctl;
> +	unsigned int tx_ref_sel;

Perhaps those 2 values should be u32 to match the readl/writel
parameters? They're HW register values after all.

> @@ -220,6 +240,7 @@ struct tegra_pcie {
>  	struct clk *afi_clk;
>  	struct clk *pcie_xclk;
>  	struct clk *pll_e;
> +	struct clk *cml0_clk;

I think this clock should be called "cml" not "cml0". The clocks within
the driver and DT binding should be named from the perspective of the
PCI HW unit, and not from the perspective of the system that surrounds
it and provides those clocks.

The only exception would be if some future Tegra version might end up
with multiple cml clocks to a single PCIe unit, and we need to number
them to identify them. However, that seems quite unlikely since the PCIe
unit already supports multiple ports, and multiple port support would be
about the only reason that I could think of to have multiple clock
instances.

I think I mentioned this when I reviewed the previous version of the
patch, but you didn't respond to the suggestion.

> @@ -749,6 +778,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
>  	struct tegra_pcie_port *port;
>  	unsigned int timeout;
>  	unsigned long value;
> +	struct tegra_pcie_soc_data *soc = pcie->soc_data;
> +
> +	/* power down to PCIe slot clock bias pad */
> +	if (soc->pex_bias_ctrl)
> +		afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);

Renaming pex_bias_ctrl to has_pex_bias_ctrl might make it more obvious
what that variable means.

A similar comment might apply to soc->pex_clkreq_en and
soc->intr_prsnt_sense.


From will.deacon at arm.com  Wed May  8 12:55:00 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 May 2013 17:55:00 +0100
Subject: [PATCH v2] ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of
 the old/new value
In-Reply-To: <1368025614-17820-1-git-send-email-jaccon.bastiaansen@gmail.com>
References: <20130508143004.GA20820@mudshark.cambridge.arm.com>
 <1368025614-17820-1-git-send-email-jaccon.bastiaansen@gmail.com>
Message-ID: <20130508165500.GH20820@mudshark.cambridge.arm.com>

On Wed, May 08, 2013 at 04:06:54PM +0100, Jaccon Bastiaansen wrote:
> The implementation of cmpxchg64() for the ARM v6 and v7 architecture
> casts parameter 2 and 3 (the old and new 64bit values) to an unsigned
> long before calling the atomic_cmpxchg64() function. This clears
> the top 32 bits of the old and new values, resulting in the wrong
> values being compare-exchanged.
> 
> This bug is introduced by commit 3e0f5a15f500 (ARM: 7404/1: cmpxchg64: use atomic64

Best to line-wrap this at 76 chars.

> and local64 routines for cmpxchg64)
> 
> Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>

Please add the following above your S-o-B:

  Cc: <stable at vger.kernel.org>
  Acked-by: Will Deacon <will.deacon at arm.com>

Then below your S-o-B, add:

  KernelVersion: 3.9

and send the patch to patches at arm.linux.org.uk

Cheers,

Will


From swarren at wwwdotorg.org  Wed May  8 12:56:34 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 10:56:34 -0600
Subject: [PATCH 3/4] ARM: dts: tegra: Correct PCIe entry
In-Reply-To: <1368010660-31465-3-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-3-git-send-email-jagarwal@nvidia.com>
Message-ID: <518A83C2.3070709@wwwdotorg.org>

On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> - Add interrupt-names property
> - Correct downstream I/O size
> - Correct cml clock name for Tegra30
> - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> - and should be applied on top of this.

Another change that needs to be made to this file (probably as a
separate change that Thierry can squash into one of his earlier changes)
is to move the pcie-controller node; it is currently not in the correct
place in the .dtsi file; it's not sorted by reg addresss.

> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi

>  		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
>  			 <&tegra_car 118>, <&tegra_car 215>;
> -		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
> +		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml0";

You could drop that change if the driver named the clock "cml" rather
than "cml0", which as I explained in my previous email seems like a good
idea anyway.

Applying the same reasoning, I wonder if for Tegra 20 too, the PCIe
driver shouldn't expect clock names of just "xclk" and "pll" rather than
"pcie_xclk" and "pll_e".


From stefano.stabellini at eu.citrix.com  Wed May  8 13:03:07 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 18:03:07 +0100
Subject: [PATCH v3 4/4] xen/arm: account for stolen ticks
In-Reply-To: <518A7836.4030705@arm.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <518A7836.4030705@arm.com>
Message-ID: <alpine.DEB.2.02.1305081712390.18865@kaball.uk.xensource.com>

On Wed, 8 May 2013, Marc Zyngier wrote:
> Hi Stefano,
> 
> On 08/05/13 16:41, Stefano Stabellini wrote:
> > Register the runstate_memory_area with the hypervisor.
> > Use pv_time_ops.steal_clock to account for stolen ticks.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > 
> > Changes in v3:
> > - use BUG_ON and smp_processor_id.
> > ---
> >  arch/arm/xen/enlighten.c |   22 ++++++++++++++++++++++
> >  1 files changed, 22 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index 13609e0..dfa7738 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -14,7 +14,10 @@
> >  #include <xen/xen-ops.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> > +#include <asm/arch_timer.h>
> >  #include <asm/system_misc.h>
> > +#include <asm/paravirt.h>
> > +#include <linux/jump_label.h>
> >  #include <linux/interrupt.h>
> >  #include <linux/irqreturn.h>
> >  #include <linux/module.h>
> > @@ -152,6 +155,19 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
> >  }
> >  EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
> >  
> > +unsigned long long xen_stolen_accounting(int cpu)
> > +{
> > +	struct vcpu_runstate_info state;
> > +
> > +	BUG_ON(cpu != smp_processor_id());
> > +
> > +	xen_get_runstate_snapshot(&state);
> > +
> > +	WARN_ON(state.state != RUNSTATE_running);
> > +
> > +	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
> > +}
> > +
> >  static void __init xen_percpu_init(void *unused)
> >  {
> >  	struct vcpu_register_vcpu_info info;
> > @@ -169,6 +185,8 @@ static void __init xen_percpu_init(void *unused)
> >  	BUG_ON(err);
> >  	per_cpu(xen_vcpu, cpu) = vcpup;
> >  
> > +	xen_setup_runstate_info(cpu);
> > +
> >  	enable_percpu_irq(xen_events_irq, 0);
> >  }
> >  
> > @@ -300,6 +318,10 @@ static int __init xen_init_events(void)
> >  
> >  	on_each_cpu(xen_percpu_init, NULL, 0);
> >  
> > +	pv_time_ops.steal_clock = xen_stolen_accounting;
> 
> What guarantee do we have that this is done before the rest of the
> kernel calls paravirt_steal_clock()?

That's not a problem: paravirt_steal_clock is not called unless
paravirt_steal_enabled or paravirt_steal_rq_enabled are set. Also
steal_clock is always increasing so loosing the first few updates is not
an issue.


> What if we have Xen support enabled but don't run as a Xen guest?

That's fine as long as the Xen runstate_memory_area interface is
available.
Usually I am a great fun of feature flags, so that every feature can be
dynamically enabled or disabled and an hypervisor interface can be only
partially implemented.

However the runstate_memory_area is very old and I would consider it
one of the core interfaces that need to be available in order to claim
"Xen compatibility".


> > +	static_key_slow_inc(&paravirt_steal_enabled);
> > +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> > +
> >  	return 0;
> >  }
> >  postcore_initcall(xen_init_events);
> > 


From swarren at wwwdotorg.org  Wed May  8 13:04:22 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 11:04:22 -0600
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
Message-ID: <518A8596.7070702@wwwdotorg.org>

On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> - Enable PCIe controller on Cardhu
> - Only port 2 is connected on this board
> - Add regulators required for Tegra30
> - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> - and should be applied on top of this.

> diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi

> +	pcie-controller {
> +		status = "okay";
> +		pex-clk-supply = <&pex_hvdd_3v3_reg>;
> +		vdd-supply = <&ldo1_reg>;
> +		avdd-supply = <&ldo2_reg>;
> +
> +		pci at 3,0 {
> +			status = "okay";
> +		};
> +	};

So, if I apply this series, I do see the PCIe bridge and Ethernet device
get enumerated, but I don't see the USB3 controller get enumerated. I
believe that is a PCIe device behind the same bridge on the same Tegra
PCIe port. Shouldn't this device show up?

The Ethernet interface gets an IP address by DHCP, so some amount of
data must be flowing. However, I cannot ping anything. If I run the same
kernel on a Tegra20 TrimSlice board, which has the same Ethernet chip,
then everything works as expected. Have you fully tested network
connectivity with these patches applied? Perhaps this is related to the
next problem:

According to the Cardhu schematics, the PCIe link to the dock is a
single lane. Hence, I believe that the Cardhu DT should describe a 411
port configuration. However, the Cardhu DT doesn't describe any
particular link configuration, but just inherits the default from
tegra30.dtsi, which describes a 222 link configuration. I would have
expected the following in the Cardhu DT:

		pci at 1,0 {
			nvidia,num-lanes = <4>;
		};

		pci at 2,0 {
			nvidia,num-lanes = <1>;
		};

		pci at 3,0 {
			status = "okay";
			nvidia,num-lanes = <1>;
		};

However, if I put that there, no PCIe links are detected at all. Why
does the driver work with the wrong link configuration, but fail with
the correct one?

Related, I notice that in Thierry's patches which you're building on,
tegra_pcie_get_xbar_config() still has a bug where a zero return value
is treated as an error, even though it's a valid HW register value.
Perhaps this is related?


From srinivas.kandagatla at st.com  Wed May  8 13:03:23 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 18:03:23 +0100
Subject: [RFC 5/8] ARM:stih41x: Add STiH415 SOC support
In-Reply-To: <201305081818.01927.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022297-2334-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081818.01927.arnd@arndb.de>
Message-ID: <518A855B.50500@st.com>

Thankyou for the comments.
On 08/05/13 17:18, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>
>> The STiH415 is the next generation of HD, AVC set-top box processors for
>> satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
>> 1.0 GHz, dual-core CPU.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> CC: Stephen Gallimore <stephen.gallimore at st.com>
>> CC: Stuart Menefy <stuart.menefy at st.com>
>> ---
>>  Documentation/arm/STiH41x/overview.txt         |   39 ++
>>  Documentation/arm/STiH41x/stih415-overview.txt |   12 +
>>  arch/arm/Kconfig                               |    3 +
>>  arch/arm/Kconfig.debug                         |   38 ++
>>  arch/arm/Makefile                              |    2 +
>>  arch/arm/boot/dts/stih415-clock.dtsi           |   38 ++
>>  arch/arm/boot/dts/stih415-pinctrl.dtsi         |  480 ++++++++++++++++++++++++
>>  arch/arm/boot/dts/stih415.dtsi                 |   94 +++++
>>  arch/arm/boot/dts/stih415.h                    |   20 +
>>  arch/arm/boot/dts/stih41x.dtsi                 |   30 ++
>>  arch/arm/boot/dts/stixxxx-pincfg.h             |   95 +++++
>>  arch/arm/configs/stih41x_defconfig             |   94 +++++
>>  arch/arm/include/debug/stixxxx.S               |   61 +++
>>  arch/arm/mach-stih41x/Kconfig                  |   35 ++
>>  arch/arm/mach-stih41x/Makefile                 |    4 +
>>  arch/arm/mach-stih41x/board-dt.c               |   76 ++++
>>  arch/arm/mach-stih41x/stih41x.c                |   82 ++++
>>  arch/arm/mach-stih41x/stih41x.h                |    7 +
>>  arch/arm/plat-stixxxx/Kconfig                  |    2 +
>>  arch/arm/plat-stixxxx/Makefile                 |    2 +
>>  arch/arm/plat-stixxxx/headsmp.S                |   44 +++
>>  arch/arm/plat-stixxxx/include/plat/hardware.h  |   20 +
>>  arch/arm/plat-stixxxx/include/plat/smp.h       |   19 +
>>  arch/arm/plat-stixxxx/platsmp.c                |  144 +++++++
> I think there is no point in having a separate mach- and plat- directory
> here, given that modern machines require very little code. You can probably
> fold the three files in mach-stih41x (board-dt.c, stih41x.c and stih41x.h)
> into a single file and rename plat-stixxxx to mach-stixxxx
Yep, sounds good.
>
>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
>> index 9b31f43..42a5193 100644
>> --- a/arch/arm/Kconfig.debug
>> +++ b/arch/arm/Kconfig.debug
>> @@ -447,6 +447,16 @@ choice
>>  		  This option selects UART0 on VIA/Wondermedia System-on-a-chip
>>  		  devices, including VT8500, WM8505, WM8650 and WM8850.
>>  
>> +	config DEBUG_STIH41X_UART
>> +		depends on ARCH_STIH41X
>> +		bool "Use StiH415/416 ASC for low-level debug"
>> +		help
>> +		  Say Y here if you want kernel low-level debugging support
>> +		  on StiH415/416 based platforms like B2000, B2020.
>> +		  It support UART2 and SBC_UART1.
>> +
>> +		  If unsure, say N.
>> +
>>  	config DEBUG_LL_UART_NONE
>>  		bool "No low-level debugging UART"
>>  		depends on !ARCH_MULTIPLATFORM
> I would split out the debug code into a separate patch though.
Will do this in next version.
>
>> @@ -600,6 +637,7 @@ config DEBUG_LL_INCLUDE
>>  	default "debug/vt8500.S" if DEBUG_VT8500_UART0
>>  	default "debug/tegra.S" if DEBUG_TEGRA_UART
>>  	default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
>> +	default "debug/stixxxx.S" if DEBUG_STIH41X_UART
>>  	default "mach/debug-macro.S"
> Please keep this in alphabetical order.
Yes.
>
>> +	soc {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		#interrupt-cells = <3>;
>> +		interrupt-parent = <&intc>;
> The "#interrupt-cells" property doesn't belong here I think.
>
>> +
>> +		uart2: uart at fed32000 {
>> +			compatible	= "st,asc";
>> +			status 		= "disabled";
>> +			reg		= <0xfed32000 0x2c>;
>> +			interrupts	= <0 197 0>;
>> +			pinctrl-names 	= "default";
>> +			pinctrl-0 	= <&pinctrl_uart2>;
>> +			clocks		= <&CLKS_ICN_REG_0>;
>> +		};
>> +
>> +		/* SBC comms block ASCs in SASG1 */
>> +		sbc_uart1: uart at fe531000 {
>> +			compatible	= "st,asc";
>> +			status 		= "disabled";
>> +			reg		= <0xfe531000 0x2c>;
>> +			interrupts	= <0 210 0>;
>> +			clocks		= <&CLK_SYSIN>;
>> +			pinctrl-names 	= "default";
>> +			pinctrl-0	= <&pinctrl_sbc_uart1>;
>> +		};
>> +	};
> Please name these devices "serial", not "uart".
Ok, I will rename them to serial.
>> diff --git a/arch/arm/configs/stih41x_defconfig b/arch/arm/configs/stih41x_defconfig
>> new file mode 100644
>> index 0000000..dd9268b
>> --- /dev/null
>> +++ b/arch/arm/configs/stih41x_defconfig
> I would prefer to have this be part of multi_v7_defconfig, unless
> you have strong reason why it can't be.
I think we can move this to multi_v7_defconfig.
>> diff --git a/arch/arm/mach-stih41x/Kconfig b/arch/arm/mach-stih41x/Kconfig
>> new file mode 100644
>> index 0000000..9c40540
>> --- /dev/null
>> +++ b/arch/arm/mach-stih41x/Kconfig
>> @@ -0,0 +1,35 @@
>> +config ARCH_STIH41X
>> +	bool "STMicroelectronics STiH41x SOCs with Flattened Device Tree" if ARCH_MULTI_V7
>> +	select GENERIC_CLOCKEVENTS
>> +	select CLKDEV_LOOKUP
>> +	select ARM_GIC
>
>> +if ARCH_STIH41X
>> +menu "STMicroelectronics Consumer Electronics SOCs"
> You can use 'menuconfig' to combine these two.
Thats a nice one.. Will use it.
>> +static void __init stih41x_timer_init(void)
>> +{
>> +	of_clk_init(NULL);
>> +	clocksource_of_init();
>> +	stih41x_l2x0_init();
>> +}
> I'm hoping we can kill make the clk and l2x0 init work by default in 3.11,
> as clocksource_of_init already does, so you won't need this function
> any more.
Ok.
>
>> +/*
>> + * A basic implementation of irq_set_wake that ensures wakeup source
>> + * interrupts are not disabled during PM_SUSPEND_FREEZE.
>> + */
>> +static int stih41x_set_wake(struct irq_data *d, unsigned int on)
>> +{
>> +	struct irq_desc *desc = irq_to_desc(d->irq);
>> +
>> +	if (on) {
>> +		if (desc->action)
>> +			desc->action->flags |= IRQF_NO_SUSPEND;
>> +	} else {
>> +		if (desc->action)
>> +			desc->action->flags &= ~IRQF_NO_SUSPEND;
>> +	}
>> +	return 0;
>> +}
>> +
>> +static void __init stih41x_irq_init(void)
>> +{
>> +	gic_arch_extn.irq_set_wake = stih41x_set_wake;
>> +	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
>> +
>> +	irqchip_init();
>> +}
> This looks like it should be generic. Why do you need this?

>
>> +void __init stih41x_dt_init(void)
>> +{
>> +	of_platform_populate(NULL, of_default_bus_match_table,
>> +				NULL, NULL);
>> +	return;
>> +}
> This is already not needed in 3.10.
Ok, cool... will get rid of this..
>
>> +static struct map_desc stih41x_io_desc[] __initdata = {
>> +#ifdef CONFIG_SMP
>> +	{
>> +		.virtual	= IO_ADDRESS(MPE41_SCU_BASE),
>> +		.pfn		= __phys_to_pfn(MPE41_SCU_BASE),
>> +		.length		= SZ_4K,
>> +		.type		= MT_DEVICE,
>> +	},
>> +#endif
>> +void __init stih41x_map_io(void)
>> +{
>> +#ifdef CONFIG_SMP
>> +	stixxxx_scu_base_addr = ((void __iomem *)IO_ADDRESS(MPE41_SCU_BASE));
>> +#endif
>> +	iotable_init(stih41x_io_desc, ARRAY_SIZE(stih41x_io_desc));
>> +}
> IIRC the SCU no longer needs to be mapped this early, so you can use
> ioremap these days.
yep, I agree.
>
>> +void __init stih41x_l2x0_init(void)
>> +{
>> +	u32 way_size = 0x4;
>> +	u32 aux_ctrl;
>> +
>> +	aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
>> +		(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
>> +		(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
>> +		(way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
>> +
>> +	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
>> +}
> I don't know where we stand on this, but I think we should kill all
> calls like these.
I agree, but we don't have other ways as of today..
>
> 	Arnd
>



From srinivas.kandagatla at st.com  Wed May  8 13:04:41 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 18:04:41 +0100
Subject: [RFC 7/8] ARM:stih41x: Add B2000 board support
In-Reply-To: <201305081820.23968.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022329-2424-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081820.23968.arnd@arndb.de>
Message-ID: <518A85A9.104@st.com>

On 08/05/13 17:20, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> diff --git a/arch/arm/mach-stih41x/board-dt.c b/arch/arm/mach-stih41x/board-dt.c
>> index 8005f71..1f23aca 100644
>> --- a/arch/arm/mach-stih41x/board-dt.c
>> +++ b/arch/arm/mach-stih41x/board-dt.c
>> @@ -63,6 +63,8 @@ void __init stih41x_dt_init(void)
>>  }
>>  
>>  static const char *stih41x_dt_match[] __initdata = {
>> +       "st,stih415-b2000",
>> +       "st,stih416-b2000",
>>         NULL
>>  };
> I probably wouldn't bother listing all the boards here. Just make sure
> the .dts file lists both the name of the board and of the soc in
> its compatible property, and list all the SoCs here that you can boot on.
I like that approach. Will change in the next version.
>
> 	Arnd
>



From dianders at chromium.org  Wed May  8 13:32:29 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed,  8 May 2013 10:32:29 -0700
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
Message-ID: <1368034349-15091-1-git-send-email-dianders@chromium.org>

If you've got MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'll be
missing the pincontrol definitions.  Add them for exynos5.

Signed-off-by: Doug Anderson <dianders at chromium.org>
---
 arch/arm/mach-exynos/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6e77432..cdcd7fa 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -428,6 +428,8 @@ config MACH_EXYNOS5_DT
 	depends on ARCH_EXYNOS5
 	select ARM_AMBA
 	select CLKSRC_OF
+	select PINCTRL
+	select PINCTRL_EXYNOS
 	select USB_ARCH_HAS_XHCI
 	select USE_OF
 	help
-- 
1.8.2.1



From dianders at chromium.org  Wed May  8 13:37:16 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed,  8 May 2013 10:37:16 -0700
Subject: [PATCH] ARM: exynos: dts: Fixed vbus-gpios
Message-ID: <1368034636-15865-1-git-send-email-dianders@chromium.org>

The 'samsung,vbus-gpio' was submitted before pinmux landed for
exynos5250 and uses the old-style gpio specifier.  Fix the two
exynos5250 boards that use it.

Signed-off-by: Doug Anderson <dianders at chromium.org>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +-
 arch/arm/boot/dts/exynos5250-snow.dts     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 26d856b..3e0c792 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -214,7 +214,7 @@
 	};
 
 	usb at 12110000 {
-		samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+		samsung,vbus-gpio = <&gpx2 6 0>;
 	};
 
 	dp-controller {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index bf4744b..d449feb 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -183,7 +183,7 @@
 	};
 
 	usb at 12110000 {
-		samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+		samsung,vbus-gpio = <&gpx1 1 0>;
 	};
 
 	fixed-rate-clocks {
-- 
1.8.2.1



From srinivas.kandagatla at st.com  Wed May  8 13:32:13 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 18:32:13 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <201305081650.23264.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
Message-ID: <518A8C1D.3090600@st.com>

Thankyou for your comments.
On 08/05/13 15:50, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>
>> This patch introduces syscon_claim, syscon_read, syscon_write,
>> syscon_release APIs to help drivers to use syscon registers in much more
>> flexible way.
>>
>> With this patch, a driver can claim few/all bits in the syscon registers
>> and do read/write and then release them when its totally finished with
>> them, in the mean time if another driver requests same bits or registers
>> the API will detect conflit and return error to the second request.
>>
>> Reason to introduce this API.
>> System configuration/control registers are very basic configuration
>> registers arranged in groups across ST Settop Box parts. These registers
>> are independent of IP itself. Many IPs, clock, pad and other functions
>> are wired up to these registers.
>>
>> In many cases a single syconf register contains bits related to multiple
>> devices, and therefore it need to be shared across multiple drivers at
>> bit level. The same IP block can have different syscon mappings on
>> different SOCs.
>>
>> Typically in a SOC there will be more than hundreds of these registers,
>> which are again divided into groups.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> CC: Stuart Menefy <stuart.menefy at st.com>
> My feeling is that syscon is the wrong place for this functionality,
> since regmap already handles (some of?) these issues. If you need
> additional synchronization, it's probably best to extend regmap
> as needed so other code besides syscon can take advantage of that
> as well.
Its not just synchronisation that we are looking for.
It also the usability, drivers want to just refer to a syscon
register/bits of it from device trees/non-devicetrees.

The extent of syscon usage is very high in ST set-top-box parts.
As example, ST pinctrl driver uses use bits of the syscon register to
control alternate functions, and many other parameters of pinconf.

In device tree we do something like:
        syscfg_sbc: syscon at fe600000{
            compatible      = "syscon";
            reg        = <0xfe600000 0xb4>;         
        };
and in pinctrl dts file
    st,alt-control    = <&syscfg_sbc  0 0 31>;
    st,od-control    = <&syscfg_sbc  9 0 7>;

the pinctrl driver calls syconf_claim(np, "st,alt-control) to get a
field and then do a read/write on the field.

Just in pinctrl driver we use around 50-100 sysconf registers scatters
across different groups.

Without these new APIs, its very difficult to pass this information to
the drivers.

Thanks,
srini
>
> 	Arnd
>



From nerv at dawncrow.de  Wed May  8 13:41:28 2013
From: nerv at dawncrow.de (=?ISO-8859-1?Q?Andr=E9_Hentschel?=)
Date: Wed, 08 May 2013 19:41:28 +0200
Subject: [PATCHv3] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
In-Reply-To: <20130508085753.GA15568@mudshark.cambridge.arm.com>
References: <51896934.5080803@dawncrow.de>
 <20130508085753.GA15568@mudshark.cambridge.arm.com>
Message-ID: <518A8E48.2080801@dawncrow.de>

Hi Will,

thx for having a look.

Am 08.05.2013 10:57, schrieb Will Deacon:> Hi Andre,
> 
> On Tue, May 07, 2013 at 09:51:00PM +0100, Andr? Hentschel wrote:
>> From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>
> 
> Might just be my mailer, but you should check that your name is intact here
> otherwise the git log will be mangled.

That's for my acute accent and already worked with my first linux patch, it's git generated.

>> Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
>> prevent it from being used as a covert channel between two tasks.
>>
>> There are more and more applications coming to WinRT, Wine could support them,
>> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
>>
>> This patch preserves that register per thread instead of clearing it.
>> Unlike the TPIDRURO, which is already switched, the TPIDRURW
>> can be updated from userspace so needs careful treatment in the case that we
>> modify TPIDRURW and call fork(). To avoid this we must always read
>> TPIDRURW in copy_thread.
>>
>> Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
>> Signed-off-by: Will Deacon <will.deacon at arm.com>
>> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com> 
> 
> [...]
> 
>> diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
>> index 73409e6..22756ab 100644
>> --- a/arch/arm/include/asm/tls.h
>> +++ b/arch/arm/include/asm/tls.h
>> @@ -2,27 +2,30 @@
>>  #define __ASMARM_TLS_H
>>  
>>  #ifdef __ASSEMBLY__
>> -	.macro set_tls_none, tp, tmp1, tmp2
>> +#include <asm/asm-offsets.h>
>> +	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
>>  	.endm
>>  
>> -	.macro set_tls_v6k, tp, tmp1, tmp2
>> +	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
>> +	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
>>  	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
>> -	mov	\tmp1, #0
>> -	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
>> +	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
>> +	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
> 
> Why is this conditional?


Seems like a copy&paste one, i'll send a v4




From srinivas.kandagatla at st.com  Wed May  8 13:42:04 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 18:42:04 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <20130508150141.GA5057@opensource.wolfsonmicro.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com>
Message-ID: <518A8E6C.6070907@st.com>

Thankyou for the comments.
On 08/05/13 16:01, Mark Brown wrote:
> On Wed, May 08, 2013 at 04:50:22PM +0200, Arnd Bergmann wrote:
>
>>> In many cases a single syconf register contains bits related to multiple
>>> devices, and therefore it need to be shared across multiple drivers at
>>> bit level. The same IP block can have different syscon mappings on
>>> different SOCs.
>> My feeling is that syscon is the wrong place for this functionality,
>> since regmap already handles (some of?) these issues. If you need
>> additional synchronization, it's probably best to extend regmap
>> as needed so other code besides syscon can take advantage of that
>> as well.
> This sounds like regmap_update_bits() ought to be all that's needed.

Ultimately the syscon_write use the regmap_update_bits, however we really want is the flexibility in using/referring the syscon registers/bits in both device-trees and non-device tree cases.

The reason for these APIs, is the extent of syscon usage is very high in ST set-top-box parts.

Without these new APIs, its very difficult to pass this information to
the drivers.

Thanks,
srini


From swarren at wwwdotorg.org  Wed May  8 13:53:24 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 11:53:24 -0600
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <518A8596.7070702@wwwdotorg.org>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
Message-ID: <518A9114.1040201@wwwdotorg.org>

On 05/08/2013 11:04 AM, Stephen Warren wrote:
> On 05/08/2013 04:57 AM, Jay Agarwal wrote:
>> - Enable PCIe controller on Cardhu
>> - Only port 2 is connected on this board
>> - Add regulators required for Tegra30
>> - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
>> - and should be applied on top of this.
> 
>> diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
> 
>> +	pcie-controller {
>> +		status = "okay";
>> +		pex-clk-supply = <&pex_hvdd_3v3_reg>;
>> +		vdd-supply = <&ldo1_reg>;
>> +		avdd-supply = <&ldo2_reg>;
>> +
>> +		pci at 3,0 {
>> +			status = "okay";
>> +		};
>> +	};
...
> According to the Cardhu schematics, the PCIe link to the dock is a
> single lane. Hence, I believe that the Cardhu DT should describe a 411
> port configuration. However, the Cardhu DT doesn't describe any
> particular link configuration, but just inherits the default from
> tegra30.dtsi, which describes a 222 link configuration. I would have
> expected the following in the Cardhu DT:
> 
> 		pci at 1,0 {
> 			nvidia,num-lanes = <4>;
> 		};
> 
> 		pci at 2,0 {
> 			nvidia,num-lanes = <1>;
> 		};
> 
> 		pci at 3,0 {
> 			status = "okay";
> 			nvidia,num-lanes = <1>;
> 		};
> 
> However, if I put that there, no PCIe links are detected at all. Why
> does the driver work with the wrong link configuration, but fail with
> the correct one?

I take this back. Fixing the DT as shown above to represent the correct
4/1/1 configuration does still yield a working system. Please
incorporate this into a future patch revision.

The issue is more that PCIe enumeration is only reliable after a cold
power cycle of the dock (the dock appears to be powered solely by its
power cable and never the battery in Cardhu, and hence isn't affected by
the main tablet PMIC's power on/off state like most of the board is). Is
there some reset signal to the dock that the bootloader or kernel should
be driving to solve this?


From konrad.wilk at oracle.com  Wed May  8 13:54:44 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 8 May 2013 13:54:44 -0400
Subject: [PATCH v3 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <1368027714-14506-1-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-1-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20130508175444.GB2800@phenom.dumpdata.com>

On Wed, May 08, 2013 at 04:41:51PM +0100, Stefano Stabellini wrote:
> Changes in v2:
> - leave do_stolen_accounting in arch/x86/xen/time.c;
> - use the new common functions in arch/ia64/xen/time.c.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> Acked-by: Ian Campbell <ian.campbell at citrix.com>
> CC: konrad.wilk at oracle.com

On the generic and x86 side it looks OK to me. I presume you did a sanity
check on x86 to make sure nothing was off?

> ---
>  arch/ia64/xen/time.c  |   48 +++----------------------
>  arch/x86/xen/time.c   |   76 +----------------------------------------
>  drivers/xen/Makefile  |    2 +-
>  drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
>  include/xen/xen-ops.h |    5 +++
>  5 files changed, 104 insertions(+), 118 deletions(-)
>  create mode 100644 drivers/xen/time.c
> 
> diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
> index 1f8244a..79a0b8c 100644
> --- a/arch/ia64/xen/time.c
> +++ b/arch/ia64/xen/time.c
> @@ -34,53 +34,17 @@
>  
>  #include "../kernel/fsyscall_gtod_data.h"
>  
> -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
>  static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
>  static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
>  
>  /* taken from i386/kernel/time-xen.c */
>  static void xen_init_missing_ticks_accounting(int cpu)
>  {
> -	struct vcpu_register_runstate_memory_area area;
> -	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
> -	int rc;
> +	xen_setup_runstate_info(&runstate);
>  
> -	memset(runstate, 0, sizeof(*runstate));
> -
> -	area.addr.v = runstate;
> -	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> -				&area);
> -	WARN_ON(rc && rc != -ENOSYS);
> -
> -	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
> -	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
> -					    + runstate->time[RUNSTATE_offline];
> -}
> -
> -/*
> - * Runstate accounting
> - */
> -/* stolen from arch/x86/xen/time.c */
> -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> -{
> -	u64 state_time;
> -	struct vcpu_runstate_info *state;
> -
> -	BUG_ON(preemptible());
> -
> -	state = &__get_cpu_var(xen_runstate);
> -
> -	/*
> -	 * The runstate info is always updated by the hypervisor on
> -	 * the current CPU, so there's no need to use anything
> -	 * stronger than a compiler barrier when fetching it.
> -	 */
> -	do {
> -		state_time = state->state_entry_time;
> -		rmb();
> -		*res = *state;
> -		rmb();
> -	} while (state->state_entry_time != state_time);
> +	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
> +	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
> +					    + runstate.time[RUNSTATE_offline];
>  }
>  
>  #define NS_PER_TICK (1000000000LL/HZ)
> @@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
>  	struct vcpu_runstate_info runstate;
>  	struct task_struct *p = current;
>  
> -	get_runstate_snapshot(&runstate);
> +	xen_get_runstate_snapshot(&runstate);
>  
>  	/*
>  	 * Check for vcpu migration effect
> @@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
>  	 */
>  	now = ia64_native_sched_clock();
>  
> -	get_runstate_snapshot(&runstate);
> +	xen_get_runstate_snapshot(&runstate);
>  
>  	WARN_ON(runstate.state != RUNSTATE_running);
>  
> diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
> index 0296a95..18d0104 100644
> --- a/arch/x86/xen/time.c
> +++ b/arch/x86/xen/time.c
> @@ -30,9 +30,6 @@
>  #define TIMER_SLOP	100000
>  #define NS_PER_TICK	(1000000000LL / HZ)
>  
> -/* runstate info updated by Xen */
> -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> -
>  /* snapshots of runstate info */
>  static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
>  
> @@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
>  static DEFINE_PER_CPU(u64, xen_residual_stolen);
>  static DEFINE_PER_CPU(u64, xen_residual_blocked);
>  
> -/* return an consistent snapshot of 64-bit time/counter value */
> -static u64 get64(const u64 *p)
> -{
> -	u64 ret;
> -
> -	if (BITS_PER_LONG < 64) {
> -		u32 *p32 = (u32 *)p;
> -		u32 h, l;
> -
> -		/*
> -		 * Read high then low, and then make sure high is
> -		 * still the same; this will only loop if low wraps
> -		 * and carries into high.
> -		 * XXX some clean way to make this endian-proof?
> -		 */
> -		do {
> -			h = p32[1];
> -			barrier();
> -			l = p32[0];
> -			barrier();
> -		} while (p32[1] != h);
> -
> -		ret = (((u64)h) << 32) | l;
> -	} else
> -		ret = *p;
> -
> -	return ret;
> -}
> -
> -/*
> - * Runstate accounting
> - */
> -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> -{
> -	u64 state_time;
> -	struct vcpu_runstate_info *state;
> -
> -	BUG_ON(preemptible());
> -
> -	state = &__get_cpu_var(xen_runstate);
> -
> -	/*
> -	 * The runstate info is always updated by the hypervisor on
> -	 * the current CPU, so there's no need to use anything
> -	 * stronger than a compiler barrier when fetching it.
> -	 */
> -	do {
> -		state_time = get64(&state->state_entry_time);
> -		barrier();
> -		*res = *state;
> -		barrier();
> -	} while (get64(&state->state_entry_time) != state_time);
> -}
> -
> -/* return true when a vcpu could run but has no real cpu to run on */
> -bool xen_vcpu_stolen(int vcpu)
> -{
> -	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> -}
> -
> -void xen_setup_runstate_info(int cpu)
> -{
> -	struct vcpu_register_runstate_memory_area area;
> -
> -	area.addr.v = &per_cpu(xen_runstate, cpu);
> -
> -	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> -			       cpu, &area))
> -		BUG();
> -}
> -
>  static void do_stolen_accounting(void)
>  {
>  	struct vcpu_runstate_info state;
> @@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
>  	s64 blocked, runnable, offline, stolen;
>  	cputime_t ticks;
>  
> -	get_runstate_snapshot(&state);
> +	xen_get_runstate_snapshot(&state);
>  
>  	WARN_ON(state.state != RUNSTATE_running);
>  
> diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
> index eabd0ee..2bf461a 100644
> --- a/drivers/xen/Makefile
> +++ b/drivers/xen/Makefile
> @@ -3,7 +3,7 @@ obj-y	+= manage.o
>  obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
>  endif
>  obj-$(CONFIG_X86)			+= fallback.o
> -obj-y	+= grant-table.o features.o events.o balloon.o
> +obj-y	+= grant-table.o features.o events.o balloon.o time.o
>  obj-y	+= xenbus/
>  
>  nostackp := $(call cc-option, -fno-stack-protector)
> diff --git a/drivers/xen/time.c b/drivers/xen/time.c
> new file mode 100644
> index 0000000..c2e39d3
> --- /dev/null
> +++ b/drivers/xen/time.c
> @@ -0,0 +1,91 @@
> +/*
> + * Xen stolen ticks accounting.
> + */
> +#include <linux/kernel.h>
> +#include <linux/kernel_stat.h>
> +#include <linux/math64.h>
> +#include <linux/gfp.h>
> +
> +#include <asm/xen/hypervisor.h>
> +#include <asm/xen/hypercall.h>
> +
> +#include <xen/events.h>
> +#include <xen/features.h>
> +#include <xen/interface/xen.h>
> +#include <xen/interface/vcpu.h>
> +#include <xen/xen-ops.h>
> +
> +/* runstate info updated by Xen */
> +static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> +
> +/* return an consistent snapshot of 64-bit time/counter value */
> +static u64 get64(const u64 *p)
> +{
> +	u64 ret;
> +
> +	if (BITS_PER_LONG < 64) {
> +		u32 *p32 = (u32 *)p;
> +		u32 h, l;
> +
> +		/*
> +		 * Read high then low, and then make sure high is
> +		 * still the same; this will only loop if low wraps
> +		 * and carries into high.
> +		 * XXX some clean way to make this endian-proof?
> +		 */
> +		do {
> +			h = p32[1];
> +			barrier();
> +			l = p32[0];
> +			barrier();
> +		} while (p32[1] != h);
> +
> +		ret = (((u64)h) << 32) | l;
> +	} else
> +		ret = *p;
> +
> +	return ret;
> +}
> +
> +/*
> + * Runstate accounting
> + */
> +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
> +{
> +	u64 state_time;
> +	struct vcpu_runstate_info *state;
> +
> +	BUG_ON(preemptible());
> +
> +	state = &__get_cpu_var(xen_runstate);
> +
> +	/*
> +	 * The runstate info is always updated by the hypervisor on
> +	 * the current CPU, so there's no need to use anything
> +	 * stronger than a compiler barrier when fetching it.
> +	 */
> +	do {
> +		state_time = get64(&state->state_entry_time);
> +		barrier();
> +		*res = *state;
> +		barrier();
> +	} while (get64(&state->state_entry_time) != state_time);
> +}
> +
> +/* return true when a vcpu could run but has no real cpu to run on */
> +bool xen_vcpu_stolen(int vcpu)
> +{
> +	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> +}
> +
> +void xen_setup_runstate_info(int cpu)
> +{
> +	struct vcpu_register_runstate_memory_area area;
> +
> +	area.addr.v = &per_cpu(xen_runstate, cpu);
> +
> +	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> +			       cpu, &area))
> +		BUG();
> +}
> +
> diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
> index d6fe062..4fd4e47 100644
> --- a/include/xen/xen-ops.h
> +++ b/include/xen/xen-ops.h
> @@ -3,6 +3,7 @@
>  
>  #include <linux/percpu.h>
>  #include <asm/xen/interface.h>
> +#include <xen/interface/vcpu.h>
>  
>  DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
>  
> @@ -16,6 +17,10 @@ void xen_mm_unpin_all(void);
>  void xen_timer_resume(void);
>  void xen_arch_resume(void);
>  
> +bool xen_vcpu_stolen(int vcpu);
> +void xen_setup_runstate_info(int cpu);
> +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res);
> +
>  int xen_setup_shutdown_event(void);
>  
>  extern unsigned long *xen_contiguous_bitmap;
> -- 
> 1.7.2.5
> 


From linux at arm.linux.org.uk  Wed May  8 14:03:43 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 May 2013 19:03:43 +0100
Subject: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support
In-Reply-To: <1367480285-26159-2-git-send-email-b35083@freescale.com>
References: <1367480285-26159-1-git-send-email-b35083@freescale.com>
 <1367480285-26159-2-git-send-email-b35083@freescale.com>
Message-ID: <20130508180343.GN18614@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 03:38:04PM +0800, Jingchang Lu wrote:
> +void mvf_restart(char mode, const char *cmd)
> +{
> +	struct device_node *np;
> +	void __iomem *wdog_base;
> +	struct clk *wdog_clk;
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt");
> +	wdog_base = of_iomap(np, 0);
> +	if (!wdog_base)
> +		goto soft;
> +
> +	wdog_clk = of_clk_get_by_name(np, "wdog");
> +	if (!IS_ERR(wdog_clk))
> +		clk_prepare_enable(wdog_clk);

I just spotted this in another email.  This is _not_ going to work
reliably.  This path gets called from all sorts of contexts, including
when the system has crashed.  It can also be called from unschedulable
contexts - and the above functions _will_ trigger might_sleep()
warnings as a result.

The only solution to this is to put this setup for this in a separate
function which is called at boot time.


From srinivas.kandagatla at st.com  Wed May  8 14:02:24 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 19:02:24 +0100
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305081634.43498.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
Message-ID: <518A9330.2010906@st.com>

Thankyou for the comments.
On 08/05/13 15:34, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> +*st-asc(Serial Port)
>> +
>> +Required properties:
>> +- compatible : Should be "st,asc".
> Are there any hardware revision numbers for the asc? If there are potentially
> incompatible or backwards-compatible variants, it would be good to include
> the version in this string.
Unfortunately, there is no version numbering for this IP.
>
>> +- reg, reg-names, interrupts, interrupt-names	: Standard way to define device
>> +			resources with names. look in
>> +			Documentation/devicetree/bindings/resource-names.txt
>> +
>> +Optional properties:
>> +- st,hw-flow-ctrl	bool flag to enable hardware flow control.
>> +- st,force-m1		bool flat to force asc to be in Mode-1 recommeded
>> +			for high bit rates (above 19.2K)
>> +Example:
>> +serial at fe440000{
>> +    compatible    = "st,asc";
>> +    reg         = <0xfe440000 0x2c>;
>> +    interrupts     =  <0 209 0>;
>> +};
> I would also recommed adding a way to set the default baud rate through
> a property. Following the example of the 8250 driver, you should probably
> call that "current-speed".
Yes, I will add this in the next version.
>
>> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
>> index 7e7006f..346f325 100644
>> --- a/drivers/tty/serial/Kconfig
>> +++ b/drivers/tty/serial/Kconfig
>> @@ -1484,6 +1484,25 @@ config SERIAL_RP2_NR_UARTS
>>  	  If multiple cards are present, the default limit of 32 ports may
>>  	  need to be increased.
>>  
>> +config SERIAL_ST_ASC
>> +	tristate "ST ASC serial port support"
>> +	depends on PLAT_STIXXXX
>> +	default y
>> +	select SERIAL_CORE
>> +	help
>> +	  This driver is for the on-chip Asychronous Serial Controller on
>> +	  STMicroelectronics STixxxx SoCs.
>> +	  ASC is embedded in ST COMMS IP block. It supports Rx & Tx functionality.
>> +	  It support all industry standard baud rates.
>> +
>> +	  If unsure, say N.
> I would not make it "default y".
Yep.
>> +config SERIAL_ST_ASC_CONSOLE
>> +	bool "Support for console on ST ASC"
>> +	depends on SERIAL_ST_ASC
>> +	default y
>> +	select SERIAL_CORE_CONSOLE
>> +
>>  endmenu
> This needs to be "depends on SERIAL_ST_ASC=y". You would get a link error
> if you try to make SERIAL_ST_ASC a loadable module and SERIAL_ST_ASC_CONSOLE
> built-in.
Ok, got it.
>
>> +
>> +static struct asc_port asc_ports[ASC_MAX_PORTS];
>> +static struct uart_driver asc_uart_driver;
>> +
>> +/*---- Forward function declarations---------------------------*/
>> +static irqreturn_t asc_interrupt(int irq, void *ptr);
>> +static void asc_transmit_chars(struct uart_port *);
>> +static int asc_set_baud(struct asc_port *ascport, int baud);
>> +
> Please remove all forward declarations, by reordering the functions in
> the way they are called.
Will do.
>
>
>> diff --git a/drivers/tty/serial/st-asc.h b/drivers/tty/serial/st-asc.h
>> new file mode 100644
>> index 0000000..e59f818
>> --- /dev/null
>> +++ b/drivers/tty/serial/st-asc.h
>> +#ifndef _ST_ASC_H
>> +#define _ST_ASC_H
>> +
>> +#include <linux/serial_core.h>
>> +#include <linux/clk.h>
>> +
>> +struct asc_port {
>> +	struct uart_port port;
>> +	struct clk *clk;
>> +	unsigned int hw_flow_control:1;
>> +	unsigned int check_parity:1;
>> +	unsigned int force_m1:1;
>> +};
> Since this header file is only used in one place, just merge it into
> the driver itself.
Ok, will do it.

>
>> +#define ASC_MAJOR		204
>> +#define ASC_MINOR_START		40
> I don't know what the current policy is on allocating major/minor numbers,
> but I'm sure you cannot just reuse one that is already used.
>
> Documentation/devices.txt lists the ones that are officially assigned.
> Can't you use dynamic allocation here?
>
> 	Arnd
>



From stefano.stabellini at eu.citrix.com  Wed May  8 14:13:00 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 May 2013 19:13:00 +0100
Subject: [PATCH v3 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <20130508175444.GB2800@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130508175444.GB2800@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1305081858220.18865@kaball.uk.xensource.com>

On Wed, 8 May 2013, Konrad Rzeszutek Wilk wrote:
> On Wed, May 08, 2013 at 04:41:51PM +0100, Stefano Stabellini wrote:
> > Changes in v2:
> > - leave do_stolen_accounting in arch/x86/xen/time.c;
> > - use the new common functions in arch/ia64/xen/time.c.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > Acked-by: Ian Campbell <ian.campbell at citrix.com>
> > CC: konrad.wilk at oracle.com
> 
> On the generic and x86 side it looks OK to me. I presume you did a sanity
> check on x86 to make sure nothing was off?

Yep, it seems to work.
However I couldn't even compile test the ia64 code.


From olof at lixom.net  Wed May  8 14:19:38 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed, 8 May 2013 11:19:38 -0700
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
In-Reply-To: <1368034349-15091-1-git-send-email-dianders@chromium.org>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
Message-ID: <CAOesGMia9kLGh6B6QJZAKS1UpBg86v32S2um+0fjx5HYjje3cw@mail.gmail.com>

Hi,

On Wed, May 8, 2013 at 10:32 AM, Doug Anderson <dianders at chromium.org> wrote:
> If you've got MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'll be
> missing the pincontrol definitions.  Add them for exynos5.
>
> Signed-off-by: Doug Anderson <dianders at chromium.org>
> ---
>  arch/arm/mach-exynos/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 6e77432..cdcd7fa 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -428,6 +428,8 @@ config MACH_EXYNOS5_DT
>         depends on ARCH_EXYNOS5
>         select ARM_AMBA
>         select CLKSRC_OF
> +       select PINCTRL
> +       select PINCTRL_EXYNOS

Nit:

Seems like this should be selected by the SoC (ARCH_EXYNOS5) instead
of the board. Actually, I'm not sure we need the board Kconfig entry
long-term; all boards will be dt-only.


-Olof


From linux at arm.linux.org.uk  Wed May  8 14:20:07 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 May 2013 19:20:07 +0100
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130508103956.GA7677@gmail.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508103956.GA7677@gmail.com>
Message-ID: <20130508182007.GO18614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 12:39:56PM +0200, Ingo Molnar wrote:
> To generalize it, firstly here's a summary of the existing reboot option 
> mappings:
> 
>  x86-only:  w, c, s
>  non-x86:         s, h, g
>  generic:                  b, a, k, t, e, p, f
> 
> 
> it appears that 'w', 'c', 'h', and 'g' could be made generic straight 
> away.
> 
> Which leaves 's' as the only truly problematic option:
> 
>  - it means REBOOT_WARM on some non-x86 platform(s?)
>  - while it means the SMP-cpu on x86.
> 
> Stupid question: which non-x86 platform(s) use 's'?

Let's try to get the meaning back.  On ARM, these are taken from the first
letter of the 'reboot=' command line argument, which was initially either
"hard" or "soft".  This refers to whether we hit some bit of hardware
which physically asserts some reset line in the system, or merely vector
the CPU via the reset vector (for some systems, this is the only
possibility.)

Then PXA happened, and there was a need for some platforms there to do
a hardware restart via toggling a GPIO output, which would then ultimately
assert the system reset line.  So we then added the "gpio" mode as well.
reboot via toggling a GPIO output.  So we then ended up with "gpio" as
well.

So, on ARM, the modes are: hard, soft, gpio, which get translated to a
single letter by the simple parsing code:

static char reboot_mode = 'h';

int __init reboot_setup(char *str)
{
        reboot_mode = str[0];
        return 1;
}

__setup("reboot=", reboot_setup);

Now, arguably, "hard" and "soft" have an entirely different meaning to
"warm" and "cold" in the normal parlence.  A "warm" reboot involves the
system doing less tasks at restart than a "cold" reboot.  This is not
necessarily the case between 'hard' and 'soft'.

So, while I don't entirely agree with mapping "hard" to "cold" and
"soft" to "warm", I guess for the sake of generalisation it's okay.
However, thinking about the future, if ARM becomes more server-like,
we might also want "cold" and "warm" reboot identifiers too.

I think the solution to this would be to have the new generic code
parse the entire argument, not just the first letter - certainly for
the 's' case.  If it's the x86 version, it'll be "s<number>".  If
it's the ARM version, it should be "soft".


From srinivas.kandagatla at st.com  Wed May  8 14:18:02 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Wed, 08 May 2013 19:18:02 +0100
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508143908.GJ24282@game.jcrosoft.org>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de> <20130508143908.GJ24282@game.jcrosoft.org>
Message-ID: <518A96DA.5060809@st.com>

On 08/05/13 15:39, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> +
>> > 
>> > Please remove all forward declarations, by reordering the functions in
>> > the way they are called.
>> > 
> and drop the dummy functions
We can not remove the dummy functions, as the serial-core does not check
it before using them.
>> > 
>>> > > diff --git a/drivers/tty/serial/st-asc.h b/drivers/tty/serial/st-asc.h
>>> > > new file mode 100644
>>> > > index 0000000..e59f818
>>> > > --- /dev/null
>>> > > +++ b/drivers/tty/serial/st-asc.h



From linux at arm.linux.org.uk  Wed May  8 14:23:05 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 May 2013 19:23:05 +0100
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <1367937595-32241-12-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
Message-ID: <20130508182304.GP18614@n2100.arm.linux.org.uk>

On Tue, May 07, 2013 at 09:39:55AM -0500, Robin Holt wrote:
> +		case 's':
> +			reboot_mode = REBOOT_WARM;
> +		case 'h':
> +			reboot_mode = REBOOT_COLD;
> +		case 'g':
> +			reboot_mode = REBOOT_GPIO;

Further to Ingo's comments, also note that the above is broken.  Any
of s,h,g will result in REBOOT_GPIO being set which is clearly wrong.


From hpa at zytor.com  Wed May  8 14:33:39 2013
From: hpa at zytor.com (H. Peter Anvin)
Date: Wed, 08 May 2013 11:33:39 -0700
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130508182007.GO18614@n2100.arm.linux.org.uk>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508103956.GA7677@gmail.com>
 <20130508182007.GO18614@n2100.arm.linux.org.uk>
Message-ID: <518A9A83.5010306@zytor.com>

On 05/08/2013 11:20 AM, Russell King - ARM Linux wrote:
> 
> Let's try to get the meaning back.  On ARM, these are taken from the first
> letter of the 'reboot=' command line argument, which was initially either
> "hard" or "soft".  This refers to whether we hit some bit of hardware
> which physically asserts some reset line in the system, or merely vector
> the CPU via the reset vector (for some systems, this is the only
> possibility.)
> 
> Then PXA happened, and there was a need for some platforms there to do
> a hardware restart via toggling a GPIO output, which would then ultimately
> assert the system reset line.  So we then added the "gpio" mode as well.
> reboot via toggling a GPIO output.  So we then ended up with "gpio" as
> well.
> 
> So, on ARM, the modes are: hard, soft, gpio, which get translated to a
> single letter by the simple parsing code:
> 
> static char reboot_mode = 'h';
> 
> int __init reboot_setup(char *str)
> {
>         reboot_mode = str[0];
>         return 1;
> }
> 
> __setup("reboot=", reboot_setup);
> 
> Now, arguably, "hard" and "soft" have an entirely different meaning to
> "warm" and "cold" in the normal parlence.  A "warm" reboot involves the
> system doing less tasks at restart than a "cold" reboot.  This is not
> necessarily the case between 'hard' and 'soft'.
> 
> So, while I don't entirely agree with mapping "hard" to "cold" and
> "soft" to "warm", I guess for the sake of generalisation it's okay.
> However, thinking about the future, if ARM becomes more server-like,
> we might also want "cold" and "warm" reboot identifiers too.
> 
> I think the solution to this would be to have the new generic code
> parse the entire argument, not just the first letter - certainly for
> the 's' case.  If it's the x86 version, it'll be "s<number>".  If
> it's the ARM version, it should be "soft".
> 

The s<number> thing is pretty awful, admittedly (it was supposed to be
smp<number>, but the parser, rather than *allowing* only the first
letter, seems to *require* that it is only the first letter.)

The problem I see is that we don't know what we'll break if we change
it, but Ingo seems to think it doesn't matter so much.

For the boolean letter argument, we could simply have the parser set a
bitmask of the letters seen; the x86 "s" argument is clearly an outlier.

We could handle it in a generic exception by looking for s<digit> or
smp<digit>, which will not match ARM's "soft" argument.  I suspect we
can worry about other argument-carrying options in a generic fashion
when the need arises; I would personally prefer the "subtag:argument"
format used by libata &c for that, and the presence of a ':' would be
indicative.

	-hpa



From arnd at arndb.de  Wed May  8 14:35:56 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 20:35:56 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <alpine.LFD.2.03.1305081239260.13109@syhkavp.arg>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081831.48566.arnd@arndb.de>
 <alpine.LFD.2.03.1305081239260.13109@syhkavp.arg>
Message-ID: <201305082035.57154.arnd@arndb.de>

On Wednesday 08 May 2013, Nicolas Pitre wrote:
> I tried to fix this up over 10 years ago.  RMK tried as well. This 
> failed because X86 people insisted on always having COM1 as /dev/ttyS0, 
> COM3 as /dev/ttyS2 and so on, even when some of them weren't present.
> 
> A common and dynamic namespace eventually succeeded for hard disks.
> Maybe people are ready to accept it for serial ports as well now?

Unfortunately it only worked for hard disks because the old name
space was abandoned entirely. It also caused a lot of surprises
for people upgrading their kernels, which is something we probably
don't want to repeat.

Now we could add a new dynamic registration facility to the tty
layer for drivers that don't already have a name and dev_t
associated with the driver, and then use it for all new drivers
as well as those that intentionally want to convert.

With DT aliases, we already have a way to enumerate serial ports
across device drivers, so if we are going to do something new,
we should make sure it works with the numbers defined there.

	Arnd


From swarren at wwwdotorg.org  Wed May  8 14:41:02 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 12:41:02 -0600
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <20130508094004.GL7949@tbergstrom-lnx.Nvidia.com>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
 <20130507124849.GM7949@tbergstrom-lnx.Nvidia.com>
 <20130507130850.GA11202@avionic-0098.adnet.avionic-design.de>
 <518915A7.1020105@wwwdotorg.org>
 <20130508094004.GL7949@tbergstrom-lnx.Nvidia.com>
Message-ID: <518A9C3E.2060803@wwwdotorg.org>

On 05/08/2013 03:40 AM, Peter De Schrijver wrote:
> On Tue, May 07, 2013 at 04:54:31PM +0200, Stephen Warren wrote:
>> On 05/07/2013 07:08 AM, Thierry Reding wrote:
>>> On Tue, May 07, 2013 at 03:48:49PM +0300, Peter De Schrijver
>>> wrote:
>>>> On Mon, May 06, 2013 at 10:39:04PM +0200, Stephen Warren wrote:
>>>>> From: Stephen Warren <swarren at nvidia.com>
>>>>>
>>>>> Tegra20 HW appears to have a bug such that PCIe device
>>>>> interrupts, whether they are legacy IRQs or MSI, are lost when
>>>>> LP2 is enabled. To work around this, simply disable LP2 if the
>>>>> PCI driver and DT node are both enabled.
>>>>>
>>>>
>>>> Wouldn't it make more sense to disable LP2 when we actually
>>>> detect a PCIe device?
>>
>> I did consider that, but rejected the idea for the reasons Thierry
>> mentioned.
...
>>> Furthermore, it is quite likely that the PCIe controller will only
>>> be enabled in DT for devices that actually have a PCIe device
>>> hooked up.
> 
> That's not always true though. Eg Harmony has a miniPCIe slot, so it should be
> listed in DT, but there is not necessarily a card present in the slot.

I initially thought that this issue only affected Tegra20, so I was
prepared to ignore the lack of optimality of this solution, since it
only affects Harmony. However, initial experimentation with Jay's
Tegra30 PCIe patches imply the same issue is present on Tegra30. I need
to do more research to confirm whether it's the same problem or
something else though. If this turns out to be true, we'll have to come
up with a more complex solution, since this current solution would
disable LP2 outright on all currently supported Tegra30 boards:-(


From linux at arm.linux.org.uk  Wed May  8 14:43:54 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 May 2013 19:43:54 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130508150800.GI2703@arm.com>
References: <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com> <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com> <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com> <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
 <20130508150800.GI2703@arm.com>
Message-ID: <20130508184354.GQ18614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 04:08:00PM +0100, Catalin Marinas wrote:
> On Sat, May 04, 2013 at 09:21:27AM +0100, Ming Lei wrote:
> > On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
> > >>
> > >> I assume that you inhibited the call to flush_dcache_page() in
> > >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
> > >> with warnings.
> > >
> > > I haven't done any stress testing so I don't think I hit this code path,
> > > so no warning. But yes, it should have triggered. Anyway, in this case
> > > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
> > > harmless anyway if we also ignore this bit in __sync_icache_dcache for
> > > non-aliasing caches).
> > 
> > Yes, maybe we can do a little optimization for O_DIRECT since no
> > dcache alias and I/D coherency problem in this case on ARMv7, how
> > about below change?
> > 
> > diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> > index 1c8f7f5..962a657 100644
> > --- a/arch/arm/mm/flush.c
> > +++ b/arch/arm/mm/flush.c
> > @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
> >  	    mapping && !mapping_mapped(mapping))
> >  		clear_bit(PG_dcache_clean, &page->flags);
> >  	else {
> > +		if (!mapping && cache_is_vipt_nonaliasing())
> > +			return;
> >  		__flush_dcache_page(mapping, page);
> >  		if (mapping && cache_is_vivt())
> >  			__flush_dcache_aliases(mapping, page);
> 
> I wonder whether we could move the:
> 
> 	if (!mapping)
> 		return
> 
> at the top of this function, IOW don't touch any anonymous pages. Would
> anything be broken (apart from wrong API use)?

I suspect you may be missing something - and I suggest reading the Sparc
version, which is where this PG_arch_1 stuff was first dreamed up (by
DaveM).

Are you positive that this path can be eliminated?  Totally sure?  Have
you checked the arg/env pages that fs/exec.c and the binfmt's insert into
the new process?

The comments against the Sparc version suggest that the "else" clause
is necessary ensure that case is adequately covered.


From swarren at wwwdotorg.org  Wed May  8 14:44:26 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 12:44:26 -0600
Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
In-Reply-To: <518A2EB2.70006@linaro.org>
References: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org>
 <518A2EB2.70006@linaro.org>
Message-ID: <518A9D0A.3010908@wwwdotorg.org>

On 05/08/2013 04:53 AM, Daniel Lezcano wrote:
> On 05/06/2013 10:39 PM, Stephen Warren wrote:
>> From: Stephen Warren <swarren at nvidia.com>
>>
>> Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
>> they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
>> this, simply disable LP2 if the PCI driver and DT node are both enabled.
>>
>> Signed-off-by: Stephen Warren <swarren at nvidia.com>
>> ---
>> Thierry,
>>
>> This patch is physically based on next-20130506 so that it doesn't
>> conflict with any of the recent cpuidle cleanup work. I'm sending it with
>> the expectation that you'll apply it to your PCIe development branch
>> though. If you do that, you'll see some conflicts unless you rebase your
>> dev branch onto something more recent than next-20130422; I assume you'll
>> do that rebase soon enough anyway, but if you weren't planning to, I can
>> resend the patch based on your current dev branch.
>>
>>  arch/arm/mach-tegra/cpuidle-tegra20.c |   30 ++++++++++++++++++++++++++++++
>>  1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
>> index 0cdba8d..d2c9349 100644
>> --- a/arch/arm/mach-tegra/cpuidle-tegra20.c
>> +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
>> @@ -25,6 +25,7 @@
>>  #include <linux/cpu_pm.h>
>>  #include <linux/clockchips.h>
>>  #include <linux/clk/tegra.h>
>> +#include <linux/of.h>
>>  
>>  #include <asm/cpuidle.h>
>>  #include <asm/proc-fns.h>
>> @@ -212,10 +213,39 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
>>  }
>>  #endif
>>  
>> +static const struct of_device_id pcie_matches[] __initconst = {
>> +	{ .compatible = "nvidia,tegra20-pcie" },
>> +	{ }
>> +};
>> +
>> +/*
>> + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
>> + * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
>> + * this, simply disable LP2 if the PCI driver and DT node are both enabled.
>> + */
>> +static void __init tegra20_cpuidle_disable_lp2_with_pcie(void)
>> +{
>> +	struct device_node *np;
>> +
>> +	if (!IS_ENABLED(CONFIG_PCI_TEGRA))
>> +		return;
>> +
>> +	np = of_find_matching_node(NULL, pcie_matches);
>> +	if (!np)
>> +		return;
>> +
>> +	if (!of_device_is_available(np))
>> +		return;
>> +
>> +	pr_info("Disabling LP2 cpuidle state, since PCIe is enabled\n");
>> +	tegra_idle_driver.state_count = 1;
> 
> Won't be more clear to have the state disabled in the init function like
> this ?
> 
> int __init tegra20_cpuidle_init(void)
> {
> 	...
> 	if (tegra20_has_lp2_pcie_bug(void))
> 		tegra_idle_driver.states[1].disabled = true;
> 	...
> }

I'm not sure that's any clearer on its own. One big advantage of that
technique is that if we end up with 3 cpuidle states and need to disable
the one in the middle, this alternative technique does work, whereas the
one in my patch doesn't. So, I'll convert to this technique.



From linux at arm.linux.org.uk  Wed May  8 14:45:55 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 May 2013 19:45:55 +0100
Subject: [PATCH v5, part3 01/15] mm: fix build warnings caused by
 free_reserved_area()
In-Reply-To: <1368026235-5976-2-git-send-email-jiang.liu@huawei.com>
References: <1368026235-5976-1-git-send-email-jiang.liu@huawei.com>
 <1368026235-5976-2-git-send-email-jiang.liu@huawei.com>
Message-ID: <20130508184555.GR18614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 11:17:00PM +0800, Jiang Liu wrote:
> Fix following build warnings cuased by free_reserved_area():
> 
> arch/arm/mm/init.c: In function 'mem_init':
> arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
>   free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
>   ^
> In file included from include/linux/mman.h:4:0,
>                  from arch/arm/mm/init.c:15:
> include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
>  extern unsigned long free_reserved_area(unsigned long start, unsigned long end,
> 
>    mm/page_alloc.c: In function 'free_reserved_area':
> >> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
>    In file included from arch/mips/include/asm/page.h:49:0,
>                     from include/linux/mmzone.h:20,
>                     from include/linux/gfp.h:4,
>                     from include/linux/mm.h:8,
>                     from mm/page_alloc.c:18:
>    arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
>    mm/page_alloc.c: In function 'free_area_init_nodes':
>    mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]
> 
> Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
> Reported-by: Arnd Bergmann <arnd at arndb.de>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> Cc: linux-mm at kvack.org
> ---
>  arch/arm/mm/init.c |    6 ++++--
>  mm/page_alloc.c    |    2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index 9a5cdc0..7a82fcd 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -600,7 +600,8 @@ void __init mem_init(void)
>  
>  #ifdef CONFIG_SA1111
>  	/* now that our DMA memory is actually so designated, we can free it */
> -	free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
> +	free_reserved_area((unsigned long)__va(PHYS_PFN_OFFSET),
> +			   (unsigned long)swapper_pg_dir, 0, NULL);

*YUCK*.

As I've said before, fixing the arguments on free_reserved_area() would
be much better than throwing these horrid casts all over the code.

You're casting pointers to integers, and then immediately casting them
back to pointers in free_reserved_area().  Please fix the function
argument types to be sane.


From dianders at chromium.org  Wed May  8 14:48:39 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed, 8 May 2013 11:48:39 -0700
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
In-Reply-To: <CAOesGMia9kLGh6B6QJZAKS1UpBg86v32S2um+0fjx5HYjje3cw@mail.gmail.com>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
 <CAOesGMia9kLGh6B6QJZAKS1UpBg86v32S2um+0fjx5HYjje3cw@mail.gmail.com>
Message-ID: <CAD=FV=X2n+zHZ3frorwW7L1yybnWWK1=-rWMQJQFus3eNiFFeQ@mail.gmail.com>

Olof,

On Wed, May 8, 2013 at 11:19 AM, Olof Johansson <olof at lixom.net> wrote:
> Seems like this should be selected by the SoC (ARCH_EXYNOS5) instead
> of the board. Actually, I'm not sure we need the board Kconfig entry
> long-term; all boards will be dt-only.

Good point.  Hopefully someone at Samsung can work on removing the
board itself?  If you'd like me to take this on then let me know and I
can put it on my list.

I'm happy to resubmit my patch under ARCH_EXYNOS5.  I'll move the
exynos4 one at the same time.

I'm going to make the assumption that PINCTRL_EXYNOS and
PINCTRL_EXYNOS5440 can happily coexist.  Certainly I've got both
defined in my tree right now and nothing blows up.  I haven't tested
on 5440 but things ought to be handled by "compatible" checks, right?

I'll also assume that eventually someone will move PINCTRL_EXYNOS5440
into PINCTRL_EXYNOS.  If PINCTRL_EXYNOS5440 won't eventually move
under PINCTRL_EXYNOS then it makes less sense to define PINCTRL_EXYNOS
for all exynos parts.

-Doug


From sergei.shtylyov at cogentembedded.com  Wed May  8 14:51:38 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 08 May 2013 22:51:38 +0400
Subject: [PATCH] irqchip: Add irqchip_init dummy function
In-Reply-To: <201305081833.03716.arnd@arndb.de>
References: <1368019204-24448-1-git-send-email-hechtb+renesas@gmail.com>
 <518A6C05.9030303@cogentembedded.com> <201305081833.03716.arnd@arndb.de>
Message-ID: <518A9EBA.6070609@cogentembedded.com>

Hello.

On 05/08/2013 08:33 PM, Arnd Bergmann wrote:

>
>>> --- a/include/linux/irqchip.h
>>> +++ b/include/linux/irqchip.h
>>> @@ -11,6 +11,10 @@
>>>    #ifndef _LINUX_IRQCHIP_H
>>>    #define _LINUX_IRQCHIP_H
>>>
>>> +#ifdef CONFIG_IRQCHIP
>>>    void irqchip_init(void);
>>> +#else
>>> +void irqchip_init(void) {};
>>      Semicolon not needed here.
>>
>>> +#endif
> More importantly, the function should be marked as "static inline", otherwise
> you get a link error if this header is included in more than one place.

     Right, I should have noticed that too. :-)

> 	Arnd

WBR, Sergei



From dianders at chromium.org  Wed May  8 14:52:48 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed,  8 May 2013 11:52:48 -0700
Subject: [PATCH v2] ARM: exynos: Select PINCTRL_EXYNOS for exynos4/5 at arch
 level
In-Reply-To: <1368034349-15091-1-git-send-email-dianders@chromium.org>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
Message-ID: <1368039168-24447-1-git-send-email-dianders@chromium.org>

Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
missing the pincontrol definitions.  Move PINCTRL selects to the arch
level since we should be enabling the code for all exynos variants.

It's expected that eventually exynos5440 (which seems to have its own
pinctrl code) will eventually move over to the common code.

Signed-off-by: Doug Anderson <dianders at chromium.org>
---
Changes in v2:
- Moved to the arch level as suggested by Olof.

 arch/arm/mach-exynos/Kconfig | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6e77432..7ee58b0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -17,6 +17,8 @@ config ARCH_EXYNOS4
 	select HAVE_ARM_SCU if SMP
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
+	select PINCTRL
+	select PINCTRL_EXYNOS
 	help
 	  Samsung EXYNOS4 SoCs based systems
 
@@ -24,6 +26,8 @@ config ARCH_EXYNOS5
 	bool "SAMSUNG EXYNOS5"
 	select HAVE_ARM_SCU if SMP
 	select HAVE_SMP
+	select PINCTRL
+	select PINCTRL_EXYNOS
 	help
 	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
@@ -78,7 +82,6 @@ config SOC_EXYNOS5440
 	select ARCH_HAS_OPP
 	select ARM_ARCH_TIMER
 	select AUTO_ZRELADDR
-	select PINCTRL
 	select PINCTRL_EXYNOS5440
 	select PM_OPP
 	help
@@ -412,8 +415,6 @@ config MACH_EXYNOS4_DT
 	select CLKSRC_OF
 	select CPU_EXYNOS4210
 	select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
-	select PINCTRL
-	select PINCTRL_EXYNOS
 	select S5P_DEV_MFC
 	select USE_OF
 	help
-- 
1.8.2.1



From arnd at arndb.de  Wed May  8 14:55:30 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 20:55:30 +0200
Subject: [RFC 5/8] ARM:stih41x: Add STiH415 SOC support
In-Reply-To: <A3BF01DB4A606149A4C20C4C4C808F6C3189E576E2@SAFEX1MAIL1.st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081818.01927.arnd@arndb.de>
 <A3BF01DB4A606149A4C20C4C4C808F6C3189E576E2@SAFEX1MAIL1.st.com>
Message-ID: <201305082055.31081.arnd@arndb.de>

On Wednesday 08 May 2013, Stephen GALLIMORE wrote:

> If you have a better solution, or a way to generalize this that would
> make sense for the ARM architecture as a whole, then we are more than
> happy to change.

No idea, sorry. Upon closer inspection I wonder if your code actually
does anything to the hardware that causes it to wake up on an interrupt.

	Arnd


From nerv at dawncrow.de  Wed May  8 15:03:55 2013
From: nerv at dawncrow.de (=?ISO-8859-15?Q?Andr=E9_Hentschel?=)
Date: Wed, 08 May 2013 21:03:55 +0200
Subject: [PATCHv4] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
Message-ID: <518AA19B.2020209@dawncrow.de>

From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>

Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
prevent it from being used as a covert channel between two tasks.

There are more and more applications coming to WinRT, Wine could support them,
but mostly they expect to have the thread environment block (TEB) in TPIDRURW.

This patch preserves that register per thread instead of clearing it.
Unlike the TPIDRURO, which is already switched, the TPIDRURW
can be updated from userspace so needs careful treatment in the case that we
modify TPIDRURW and call fork(). To avoid this we must always read
TPIDRURW in copy_thread.

Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com> 

---
This patch is against a86d52667d8eda5de39393ce737794403bdce1eb

Why so much Signed-off-bys? Some History:
The first patch had performance issues pointed out by Russel King,
so Will Deacon jumped in to help me with that. The second one again
had performance issues and the missing copy_thread part was uncovered.
After some iterations by me, Jonathan Austin proposed a patch and
Russel King sent his idea of the assembler part. All this was finally
merged and refined into this patch.
Thanks to everyone!

 arch/arm/include/asm/thread_info.h |    2 +-
 arch/arm/include/asm/tls.h         |   40 ++++++++++++++++++++++++------------
 arch/arm/kernel/entry-armv.S       |    4 ++--
 arch/arm/kernel/process.c          |    4 +++-
 arch/arm/kernel/ptrace.c           |    2 +-
 arch/arm/kernel/traps.c            |    4 ++--
 6 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f..d90be6d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];	/* TLS registers */
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..83259b8 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-	.macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
 	.endm
 
-	.macro set_tls_v6k, tp, tmp1, tmp2
+	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
 	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
+	str	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_v6, tp, tmp1, tmp2
+	.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
 	ldr	\tmp1, =elf_hwcap
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
 	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	mcrne	p15, 0, \tpuser, c13, c0, 2	@ set user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_software, tp, tmp1, tmp2
+	.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
 	mov	\tmp1, #0xffff0fff
 	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
@@ -31,19 +34,30 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
-#define set_tls		set_tls_none
+#define switch_tls	switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
-#define set_tls		set_tls_v6
+#define switch_tls	switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
-#define set_tls		set_tls_v6k
+#define switch_tls	switch_tls_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
-#define set_tls		set_tls_software
+#define switch_tls	switch_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tpuser(void)
+{
+	unsigned long reg = 0;
+
+	if (has_tls_reg && !tls_emu)
+		__asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
+
+	return reg;
+}
+#endif
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..80f09fe 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -728,15 +728,15 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
+	ldrd	r4, r5, [r2, #TI_TP_VALUE]
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-	set_tls	r3, r4, r5
+	switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
 	ldr	r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e4..7635879 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -395,7 +396,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+		thread->tp_value[0] = childregs->ARM_r3;
+	thread->tp_value[1] = get_tpuser();
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c08911..f9d6259 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }


From nm at ti.com  Wed May  8 15:06:15 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:15 -0500
Subject: [PATCH V5 5/6] ARM: OMAP2+: AM33XX: add lateinit hook for calling pm
 late init
In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
Message-ID: <1368039976-29648-6-git-send-email-nm@ti.com>

Call OMAP2+ generic lateinit hook from AM specific late init hook.
This allows the generic late initializations such as cpufreq hooks
to be active.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Kevin Hilman <khilman at deeprootsystems.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
Change in this revision compared to previous revision:
	- rebase, no functional change.
Previous version: http://marc.info/?l=linux-kernel&m=136580760924258&w=2

 arch/arm/mach-omap2/board-generic.c |    1 +
 arch/arm/mach-omap2/common.h        |    1 +
 arch/arm/mach-omap2/io.c            |    6 ++++++
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 88aa6b1..2c5c67c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -141,6 +141,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
 	.init_irq	= omap_intc_of_init,
 	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_generic_init,
+	.init_late	= am33xx_init_late,
 	.init_time	= omap3_gptimer_timer_init,
 	.dt_compat	= am33xx_boards_compat,
 	.restart	= am33xx_restart,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..e2d7ecf 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -107,6 +107,7 @@ void omap35xx_init_late(void);
 void omap3630_init_late(void);
 void am35xx_init_late(void);
 void ti81xx_init_late(void);
+void am33xx_init_late(void);
 int omap2_common_pm_late_init(void);
 
 #ifdef CONFIG_SOC_BUS
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..401e268 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -584,6 +584,12 @@ void __init am33xx_init_early(void)
 	omap_hwmod_init_postsetup();
 	omap_clk_init = am33xx_clk_init;
 }
+
+void __init am33xx_init_late(void)
+{
+	omap2_common_pm_late_init();
+}
+
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-- 
1.7.9.5



From nm at ti.com  Wed May  8 15:06:10 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:10 -0500
Subject: [PATCH V5 0/6] ARM: OMAP3+: support cpufreq-cpu0 for device tree boot
Message-ID: <1368039976-29648-1-git-send-email-nm@ti.com>

The following version 5 of the series arose from trying to use
BeagleBoard-XM (OMAP3 variant) for doing CPU DVFS using cpufreq-cpu0.
This series enables the generic cpufreq-cpu0 driver to be used in
device tree enabled boot while maintaining support of the legacy
omap-cpufreq driver when used in non device tree enabled boot.

However, in order to enable complete SoC entitlement for OMAP
platforms, with this series, key features are still pending on device
tree adaptation for OMAP:
A) clock framework data transition to DT - this series provides an
driver to allow device tree definition of clock node.
B) On processors that use voltage controller, voltage processor
(VC/VP hardware loop using I2C_SR path) - we have started work on
transitioning them to regulator framework driven by DT.
C) Adaptive Body Bias[2] and SmartReflex AVS conversion to DT.

Note: Common Clock Framework(CCF) could also control regulators[3] and
AVS to ensure proper sequencing required for full DVFS sequencing.
Once these conversions are complete, there might be minimal cleanup
work to switch to the new data structure changes.

Key benefit of the series is to allow all relevant TI platforms now to
use a single cpufreq driver and equivalent frameworks in addition be
part of the transition to device tree.

NOTE on this series:
1. omap-cpufreq will be used only in non device tree boot scenario. we
should delete this driver once the 100% DT conversion is complete.
2. Generic cpufreq-cpu0 will be used only in device tree boot scenario
boot systems
3. clock data movement as approached by Tero in [4] is not the
objective of this series
4. meant for post 3.10-rc1 tag

Key changes in version 5 since version 4:
	- rebase with master for 3.10-rc1 intermediate
	- review comments incorporated

version 4 of the series:
	http://marc.info/?l=linux-arm-kernel&m=136580742724210&w=2
	available at:
	https://github.com/nmenon/linux-2.6-playground/commits/push/cpufreq-cpu0-omap-all-v4

version 3 of the series:
	http://marc.info/?l=linux-pm&m=136450759315742&w=2
	available at:
	https://github.com/nmenon/linux-2.6-playground/commits/push/cpufreq-cpu0-omap-all-v3

version 2 of the series:
	http://marc.info/?t=136371570200003&r=1&w=2
	available at:
	https://github.com/nmenon/linux-2.6-playground/commits/push/cpufreq-cpu0-omap-all-v2

version 1 of the series:
	http://marc.info/?t=136329485400005&r=1&w=2
	available at:
	https://github.com/nmenon/linux-2.6-playground/commits/push/cpufreq-cpu0-omap-all-v1

[1] Original discussion thread which triggered this series:
	http://marc.info/?l=linux-pm&m=136304313700602&w=2
	https://patchwork.kernel.org/patch/2251841/
	https://patchwork.kernel.org/patch/2251851/
[2] ABB series: http://marc.info/?l=linux-omap&m=136751559523901&w=2 (ABB DTS merge pending)
[3] CCF DVFS patches:
https://patchwork.kernel.org/patch/2195431/
https://patchwork.kernel.org/patch/2195421/
https://patchwork.kernel.org/patch/2195451/
https://patchwork.kernel.org/patch/2195441/
https://patchwork.kernel.org/patch/2195461/
[4] http://marc.info/?t=136388745000001&r=1&w=2

Version 5 is now based on master since all requisite for-next branches have been merged.
	master 5af43c2 Merge branch 'akpm' (incoming from Andrew)

Version 4 is also available at:
	https://github.com/nmenon/linux-2.6-playground/commits/push/cpufreq-cpu0-omap-all-v5
	git link: git://github.com/nmenon/linux-2.6-playground.git
	branch: cpufreq-cpu0-omap-all-v5

Test coverage:
	test script:  http://pastebin.com/GsavxiDe
	(note - to allow testing, I followed the suggestion in https://lkml.org/lkml/2013/5/8/19 )

Platforms verified:
	beaglebone(rev A6a) - AM33xx compatible - http://pastebin.com/zANKsYBp
	beagleboard (rev C1D) - OMAP3430 compatible
		- DT enabled boot:  http://pastebin.com/q4qZYVaK
		- No DT enabled boot: http://pastebin.com/c1CbQmV5
	omap3-beagle-xm -OMAP3630 compatible - http://pastebin.com/ibUABcA0
	SDP4430 -(OMAP4430 ES2.2) - http://pastebin.com/wYwUc3fU
	Pandaboard-ES -(OMAP4460 ES1.1) - http://pastebin.com/FB2RiFp2

Nishanth Menon (6):
  clk: OMAP: introduce device tree binding to kernel clock data
[Clk driver probably belongs to mike's tree?]
  ARM: dts: OMAP3: add clock nodes for CPU
  ARM: dts: OMAP4: add clock nodes for CPU
  ARM: dts: AM33XX: add clock nodes for CPU
[The above probably belong to Benoit's tree]
  ARM: OMAP2+: AM33XX: add lateinit hook for calling pm late init
  ARM: OMAP3+: use cpu0-cpufreq driver in device tree supported boot
[The above probably belong to Kevin/Tony's tree]

 .../devicetree/bindings/clock/omap-clock.txt       |   40 +++++++++
 arch/arm/boot/dts/am33xx.dtsi                      |    7 ++
 arch/arm/boot/dts/omap3.dtsi                       |    7 ++
 arch/arm/boot/dts/omap4.dtsi                       |    7 ++
 arch/arm/mach-omap2/board-generic.c                |    1 +
 arch/arm/mach-omap2/cclock33xx_data.c              |    1 -
 arch/arm/mach-omap2/common.h                       |    1 +
 arch/arm/mach-omap2/io.c                           |    6 ++
 arch/arm/mach-omap2/pm.c                           |   11 ++-
 drivers/clk/Makefile                               |    1 +
 drivers/clk/omap/Makefile                          |    1 +
 drivers/clk/omap/clk.c                             |   91 ++++++++++++++++++++
 12 files changed, 170 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/omap-clock.txt
 create mode 100644 drivers/clk/omap/Makefile
 create mode 100644 drivers/clk/omap/clk.c

Regards,
Nishanth Menon
-- 
1.7.9.5



From nm at ti.com  Wed May  8 15:06:16 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:16 -0500
Subject: [PATCH V5 6/6] ARM: OMAP3+: use cpu0-cpufreq driver in device tree
 supported boot
In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
Message-ID: <1368039976-29648-7-git-send-email-nm@ti.com>

With OMAP3+ and AM33xx supported SoC having defined CPU device tree
entries with operating-points and clock nodes defined, we can now use
the SoC generic cpufreq-cpu0 driver by registering appropriate device.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Kevin Hilman <khilman at deeprootsystems.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
no change in current revision.
Previous version: http://marc.info/?l=linux-omap&m=136580759924239&w=2

 arch/arm/mach-omap2/pm.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e742118..11bd585 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -266,7 +266,12 @@ static void __init omap4_init_voltages(void)
 
 static inline void omap_init_cpufreq(void)
 {
-	struct platform_device_info devinfo = { .name = "omap-cpufreq", };
+	struct platform_device_info devinfo = { };
+
+	if (!of_have_populated_dt())
+		devinfo.name = "omap-cpufreq";
+	else
+		devinfo.name = "cpufreq-cpu0";
 	platform_device_register_full(&devinfo);
 }
 
@@ -300,9 +305,9 @@ int __init omap2_common_pm_late_init(void)
 		/* Smartreflex device init */
 		omap_devinit_smartreflex();
 
-		/* cpufreq dummy device instantiation */
-		omap_init_cpufreq();
 	}
+	/* cpufreq dummy device instantiation */
+	omap_init_cpufreq();
 
 #ifdef CONFIG_SUSPEND
 	suspend_set_ops(&omap_pm_ops);
-- 
1.7.9.5



From nm at ti.com  Wed May  8 15:06:12 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:12 -0500
Subject: [PATCH V5 2/6] ARM: dts: OMAP3: add clock nodes for CPU
In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
Message-ID: <1368039976-29648-3-git-send-email-nm@ti.com>

OMAP34xx and OMAP36xx platforms use dpll1 clock. Add same to common
definition.

Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
no change in current revision.
Previous version: http://marc.info/?l=linux-kernel&m=136580740024201&w=2

 arch/arm/boot/dts/omap3.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 4ad03d9..4f445ca 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -23,6 +23,8 @@
 	cpus {
 		cpu at 0 {
 			compatible = "arm,cortex-a8";
+			clocks = <&dpll1>;
+			clock-names = "cpu";
 		};
 	};
 
@@ -73,6 +75,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		dpll1: dpll1 {
+			#clock-cells = <0>;
+			compatible = "ti,omap-clock";
+		};
+
 		intc: interrupt-controller at 48200000 {
 			compatible = "ti,omap2-intc";
 			interrupt-controller;
-- 
1.7.9.5



From nm at ti.com  Wed May  8 15:06:13 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:13 -0500
Subject: [PATCH V5 3/6] ARM: dts: OMAP4: add clock nodes for CPU
In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
Message-ID: <1368039976-29648-4-git-send-email-nm@ti.com>

OMAP443x, OMAP446x and OMAP447x platforms use dpll_mpu clock.
Add same to common definition.

Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
no change in current revision.
Previous version: http://marc.info/?l=linux-kernel&m=136580751024225&w=2

 arch/arm/boot/dts/omap4.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..1c6d969 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -31,6 +31,8 @@
 		cpu at 0 {
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
+			clocks = <&dpll_mpu>;
+			clock-names = "cpu";
 		};
 		cpu at 1 {
 			compatible = "arm,cortex-a9";
@@ -106,6 +108,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		dpll_mpu: dpll_mpu {
+			#clock-cells = <0>;
+			compatible = "ti,omap-clock";
+		};
+
 		omap4_pmx_core: pinmux at 4a100040 {
 			compatible = "ti,omap4-padconf", "pinctrl-single";
 			reg = <0x4a100040 0x0196>;
-- 
1.7.9.5



From nm at ti.com  Wed May  8 15:06:14 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:14 -0500
Subject: [PATCH V5 4/6] ARM: dts: AM33XX: add clock nodes for CPU
In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
Message-ID: <1368039976-29648-5-git-send-email-nm@ti.com>

AM33XX based platforms use dpll_mpu clock. Add same to common dtsi
and remove the dummy clock node entry as AM33XX platform supports
only device tree based boot.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Kevin Hilman <khilman at deeprootsystems.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
Change in this revision from previous:
	- rebase, no functional change.
Previous version: http://marc.info/?l=linux-kernel&m=136580755324232&w=2

 arch/arm/boot/dts/am33xx.dtsi         |    7 +++++++
 arch/arm/mach-omap2/cclock33xx_data.c |    1 -
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index d110110..27f6eb1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -42,6 +42,8 @@
 				275000  1125000
 			>;
 			voltage-tolerance = <2>; /* 2 percentage */
+			clocks = <&dpll_mpu>;
+			clock-names = "cpu";
 			clock-latency = <300000>; /* From omap-cpufreq driver */
 		};
 	};
@@ -89,6 +91,11 @@
 			reg = <0x48200000 0x1000>;
 		};
 
+		dpll_mpu: dpll_mpu {
+			#clock-cells = <0>;
+			compatible = "ti,omap-clock";
+		};
+
 		gpio0: gpio at 44e07000 {
 			compatible = "ti,omap4-gpio";
 			ti,hwmods = "gpio1";
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 6ebc780..4e39171 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -860,7 +860,6 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck),
 	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck),
 	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck),
-	CLK("cpu0",	NULL,			&dpll_mpu_ck),
 	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck),
 	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck),
 	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck),
-- 
1.7.9.5



From nm at ti.com  Wed May  8 15:06:11 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 8 May 2013 14:06:11 -0500
Subject: [PATCH V5 1/6] clk: OMAP: introduce device tree binding to kernel
 clock data
In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
Message-ID: <1368039976-29648-2-git-send-email-nm@ti.com>

OMAP clock data is located in arch/arm/mach-omap2/cclockXYZ_data.c.
However, this presents an obstacle for using these clock nodes in
Device Tree definitions. This is especially true for board specific
clocks initially. The fixed clocks are currently found via clock
aliases table. There are many possible approaches to this problem as
discussed in the following thread:
http://marc.info/?t=136370325600009&r=1&w=2.
Highlights of the options:
a) device specific clk_add_alias:
   cons: driver handling required
b) using an generic clk node and indexing to reach the clock required.
   This is similar in approach taken by tegra and few other platforms.
   Example usage: clock = <&clk 5>;
   cons: potential to have mismatches in indexed table and associated
   dtb data. In addition, managing continued documentation in bindings
   as clock indexing increases. Even though readability angle could be
   improved by using preprocessing of DT using macros, indexed
   approach is inherently risky from cases like the following:
   clk indexes in kernel:
   1 - mpu_dpll
   2 - aux_clk1
   3 - core_clk
   DT entry for peripheral X uses <&clk 2> to reach aux_clk1. Now, let's
   say kernel updates indices to:
   1 - mpu_dpll
   2 - per_dpll
   3 - aux_clk1
   4 - core_clk
   using the old dtb(or dts missing an update), on new kernel which
   has updated indices will result in per_dpll now controlled for
   peripheral X without warning or any potential error detection.

   Even though we could claim this is user error, such errors are hard
   to track down and fix.

An alternate approach introduced here is to introduce device tree
bindings corresponding to the clock nodes required in DT definition
for SoC which automatically maps back to the definitions in
cclockXYZ_data.c.

The driver introduced here to do this mapping will eventually be the
place where the clock handling will migrate to. We need to consider
this angle as well so that the solution will be an valid transition
point for moving the clock data out of kernel image (into device tree
or firmware load etc..).

Overall strategy introduced here is simple: a clock node described in
device tree blob is used to identify the exact clock provided in the
SoC specific data. This is then linked back using of_clk_add_provider
to the device node to be accessible by of_clk_get.

Based on discussion contributions from Roger Quadros, Grygorii Strashko
and others.

Cc: Kevin Hilman <khilman at deeprootsystems.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
[tony at atomide.com: co-developed]
Signed-off-by: Tony Lindgren <tony at atomide.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
Changes in this version:
	- review comments incorporated.
Previous version of this patch was discussed in:
	http://marc.info/?t=136580758500001&r=1&w=2

 .../devicetree/bindings/clock/omap-clock.txt       |   40 +++++++++
 drivers/clk/Makefile                               |    1 +
 drivers/clk/omap/Makefile                          |    1 +
 drivers/clk/omap/clk.c                             |   91 ++++++++++++++++++++
 4 files changed, 133 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/omap-clock.txt
 create mode 100644 drivers/clk/omap/Makefile
 create mode 100644 drivers/clk/omap/clk.c

diff --git a/Documentation/devicetree/bindings/clock/omap-clock.txt b/Documentation/devicetree/bindings/clock/omap-clock.txt
new file mode 100644
index 0000000..047c1e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/omap-clock.txt
@@ -0,0 +1,40 @@
+Device Tree Clock bindings for Texas Instrument's OMAP compatible platforms
+
+This binding is an initial minimal binding that may be enhanced as part of
+transitioning OMAP clock data out of kernel image.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,omap-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+NOTE:
+node name should map to clock database in arch/arm/mach-omap2/cclock<SoC>_data.c
+Since all clocks are described with _ck, the node name is optimized to drop the
+usage of _ck. For example, a clock called dpll1_ck will be defined as dpll1.
+
+Example #1: describing clock node for CPU on OMAP34xx platform:
+Ref: arch/arm/mach-omap2/cclock3xxx_data.c
+describes the CPU clock to be as follows
+	CLK(NULL,	"dpll1_ck",	&dpll1_ck,	CK_3XXX),
+Corresponding binding will be:
+	dpll1: dpll1 {
+		#clock-cells = <0>;
+		compatible = "ti,omap-clock";
+	};
+And it's usage will be:
+		clocks = <&dpll1>;
+
+Example #2: describing clock node for auxilary clock #3 on OMAP443x platform:
+Ref: arch/arm/mach-omap2/cclock44xx_data.c
+describes the auxclk3 clock to be as follows:
+	CLK(NULL,	"auxclk3_ck",	&auxclk3_ck,	CK_443X),
+Corresponding binding will be:
+	auxclk3: auxclk3 {
+		#clock-cells = <0>;
+		compatible = "ti,omap-clock";
+	};
+And it's usage will be:
+	clocks = <&auxclk3>;
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..1d5a2ec 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= clk-zynq.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
+obj-$(CONFIG_ARCH_OMAP)		+= omap/
 
 obj-$(CONFIG_X86)		+= x86/
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
new file mode 100644
index 0000000..8195931
--- /dev/null
+++ b/drivers/clk/omap/Makefile
@@ -0,0 +1 @@
+obj-y					+= clk.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
new file mode 100644
index 0000000..5a3c6d9
--- /dev/null
+++ b/drivers/clk/omap/clk.c
@@ -0,0 +1,91 @@
+/*
+ * Texas Instruments OMAP Clock driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *	Nishanth Menon <nm at ti.com>
+ *	Tony Lindgren <tony at atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+
+static const struct of_device_id omap_clk_of_match[] = {
+	{.compatible = "ti,omap-clock",},
+	{},
+};
+
+/**
+ * omap_clk_src_get() - Get OMAP clock from node name when needed
+ * @clkspec:	clkspec argument
+ * @data:	unused
+ *
+ * REVISIT: We assume the following:
+ * 1. omap clock names end with _ck
+ * 2. omap clock names are under 32 characters in length
+ */
+static struct clk *omap_clk_src_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct clk *clk;
+	char clk_name[32];
+	struct device_node *np = clkspec->np;
+
+	snprintf(clk_name, 32, "%s_ck", np->name);
+	clk = clk_get(NULL, clk_name);
+	if (IS_ERR(clk))
+		pr_err("%s: could not get clock %s(%ld)\n", __func__,
+		       clk_name, PTR_ERR(clk));
+
+	return clk;
+}
+
+/**
+ * omap_clk_probe() - create link from DT definition to clock data
+ * @pdev:	device node
+ *
+ * NOTE: we look up the clock lazily when the consumer driver does
+ * of_clk_get() and initialize a NULL clock here.
+ */
+static int omap_clk_probe(struct platform_device *pdev)
+{
+	int res;
+	struct device_node *np = pdev->dev.of_node;
+
+	/* This allows the driver to of_clk_get() */
+	res = of_clk_add_provider(np, omap_clk_src_get, NULL);
+	if (res)
+		dev_err(&pdev->dev, "could not add provider(%d)\n", res);
+
+	return res;
+}
+
+static struct platform_driver omap_clk_driver = {
+	.probe = omap_clk_probe,
+	.driver = {
+		   .name = "omap_clk",
+		   .of_match_table = of_match_ptr(omap_clk_of_match),
+		   },
+};
+
+static int __init omap_clk_init(void)
+{
+	return platform_driver_register(&omap_clk_driver);
+}
+arch_initcall(omap_clk_init);
+
+MODULE_DESCRIPTION("OMAP Clock driver");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From soren.brinkmann at xilinx.com  Wed May  8 15:20:41 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Wed, 8 May 2013 12:20:41 -0700
Subject: [REGRESSION] SLAB allocator (on Zynq)
Message-ID: <9d9b2266-e09e-4366-80ef-3df5db775f25@TX2EHSMHS033.ehs.local>

Hi,

I compiled the latest kernel for Zynq and ran into issues when the SLAB
allocator is selected. Booting crashes early with a NULL pointer
dereference (boot log attached).
Switching to the SLUB allocator resolves the issue (boot log attached).

I tried bisecting the issue with the following result:
	There are only 'skip'ped commits left to test.
	The first bad commit could be any of:
	ca34956b804b7554fc4e88826773380d9d5122a8
	ce8eb6c424c794d7fb4d1a6667d267990ca28072
	2c59dd6544212faa5ce761920d2251f4152f408d
	c601fd6956e92b0eb268d4af754073c76155b99d
	9e5e8deca74603357626471a9b44f05dea9e32b1
	db8450673458e724229e91050ac9a92253b01234
	b1e0541674904db00e17ce646b0a1d54f59136a5
	f97d5f634d3b5133951424fae751db1f339548bd
	7d557b3cb69398d83ceabad9cf147c93a3aa97fd
	9425c58e5445277699ff3c2a87bac1cfebc1b48d
	633b076464da52b3c7bf0f62932fbfc0ea23d8b3
	95a05b428cc675694321c8f762591984f3fd2b1e
	338b2642290ef3193229ece8cfc776ac4fe8869d
	6a67368c36e2c0c2578ba62f6264ab739af08cce
	4d7868e6475d478172581828021bd8a356726679
	6744f087ba2a49f6d6935d9daa0b20a0f03567b5
	7cccd80b4397699902aced1ad3d692d384aaab77
	e33660165c901d18e7d3df2290db070d3e4b46df
	14e50c6a9bc2b283bb4021026226268312ceefdd
	ce6a50263d4ddeba1f0d08f16716a82770c03690
	345046673449b5c35840e5cc34a60059cbec9305
	6286ae97d10ea2b5cd90532163797ab217bfdbdf
	31ba7346f082f3468b8e06b45db475a6e25f01fc
	8a965b3baa89ffedc73c0fbc750006c631012ced
	69df2ac1288b456a95aceadafbf88cd891a577c8
	We cannot bisect more!

The skipped commits failed to compile.

I also attach my kernel config.

	Thanks,
	S??ren

-------------- next part --------------


U-Boot 2013.01-00001-g7926df4 (Apr 09 2013 - 09:45:48)

I2C:   ready
DRAM:  1 GiB
WARNING: Caches not enabled
MMC:   zynq_sdhci: 0
SF: Detected N25Q128A with page size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   Gem.e000b000
Hit any key to stop autoboot:  3  2  1  0 
TFTPing Linux to RAM...
Gem.e000b000 Waiting for PHY auto negotiation to complete...... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'uImage'.
Load address: 0x3000000
Loading: *#################################################################
	 #################################################################
	 ##################################
	 4.1 MiB/s
done
Bytes transferred = 2395288 (248c98 hex)
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete...... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'devicetree.dtb'.
Load address: 0x2a00000
Loading: *#
	 725.6 KiB/s
done
Bytes transferred = 2975 (b9f hex)
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete..... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'uramdisk.image.gz'.
Load address: 0x2000000
Loading: *#################################################################
	 #################################################################
	 #################################################################
	 ##
	 4.4 MiB/s
done
Bytes transferred = 2889895 (2c18a7 hex)
## Booting kernel from Legacy Image at 03000000 ...
   Image Name:   Linux-3.9.0-11591-g5af43c2
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2395224 Bytes = 2.3 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 02000000 ...
   Image Name:   
   Image Type:   ARM Linux RAMDisk Image (lzma compressed)
   Data Size:    2889831 Bytes = 2.8 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
   Booting using the fdt blob at 0x02a00000
   Loading Kernel Image ... OK
OK
   Loading Ramdisk to 1fd3e000, end 1ffff867 ... OK
   Loading Device Tree to 1fd3a000, end 1fd3db9e ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0

[    0.000000] Linux version 3.9.0-11591-g5af43c2 (sorenb at xsjandreislx) (gcc version 4.7.2 (Sourcery CodeBench Lite 2012.09-104) ) #46 SMP PREEMPT Wed May 8 11:57:37 PDT 2013

[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d

[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

[    0.000000] Machine: Xilinx Zynq Platform, model: Zynq ZC702 Development Board

[    0.000000] bootconsole [earlycon0] enabled

[    0.000000] cma: CMA: reserved 16 MiB at 2e800000

[    0.000000] Memory policy: ECC disabled, Data cache writealloc

[    0.000000] PERCPU: Embedded 9 pages/cpu @c1474000 s14016 r8192 d14656 u36864

[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260624

[    0.000000] Kernel command line: console=ttyPS1,115200 earlyprintk

[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)

[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)

[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)

[    0.000000] Memory: 1024MB = 1024MB total

[    0.000000] Memory: 1007504k/1007504k available, 41072k reserved, 270336K highmem

[    0.000000] Virtual kernel memory layout:

[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)

[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)

[    0.000000]     vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)

[    0.000000]     lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)

[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)

[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)

[    0.000000]       .text : 0xc0008000 - 0xc0633674   (6318 kB)

[    0.000000]       .init : 0xc0634000 - 0xc06856c0   ( 326 kB)

[    0.000000]       .data : 0xc0686000 - 0xc06d0bb0   ( 299 kB)

[    0.000000]        .bss : 0xc06d0bb0 - 0xc0c60d10   (5697 kB)

[    0.000000] Preemptible hierarchical RCU implementation.

[    0.000000] 	RCU lockdep checking is enabled.

[    0.000000] 	Additional per-CPU info printed with stalls.

[    0.000000] 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.

[    0.000000] NR_IRQS:16 nr_irqs:16 16

[    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000054

[    0.000000] pgd = c0004000

[    0.000000] [00000054] *pgd=00000000

[    0.000000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM

[    0.000000] Modules linked in:

[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.9.0-11591-g5af43c2 #46

[    0.000000] task: c0691b08 ti: c0686000 task.ti: c0686000

[    0.000000] PC is at kmem_cache_alloc_trace+0x74/0x290

[    0.000000] LR is at trace_hardirqs_off+0x14/0x18

[    0.000000] pc : [<c0100be4>]    lr : [<c00741e4>]    psr: 600001d3

[    0.000000] sp : c0687f38  ip : c0687f28  fp : c0687f6c

[    0.000000] r10: 000000c0  r9 : c00922d0  r8 : 000080d0

[    0.000000] r7 : 600001d3  r6 : 00000000  r5 : 00008000  r4 : 00000010

[    0.000000] r3 : 00000000  r2 : c0687f38  r1 : c0691b08  r0 : c0100bd0

[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel

[    0.000000] Control: 18c5387d  Table: 0000404a  DAC: 00000015

[    0.000000] Process swapper/0 (pid: 0, stack limit = 0xc0686238)

[    0.000000] Stack: (0xc0687f38 to 0xc0688000)

[    0.000000] 7f20:                                                       c0687f64 00000010

[    0.000000] 7f40: c069ba40 00000010 00000000 00002014 00000000 00000000 413fc090 00000000

[    0.000000] 7f60: c0687f94 c0687f70 c00922d0 c0100b7c 00000010 00000000 00002014 c0668f78

[    0.000000] 7f80: c1471480 00000000 c0687fb4 c0687f98 c0642554 c00922a8 c068f784 c0686000

[    0.000000] 7fa0: c06d0bc0 ffffffff c0687ff4 c0687fb8 c063475c c06424c8 ffffffff ffffffff

[    0.000000] 7fc0: c063433c 00000000 00000000 c0668f78 00000000 18c5387d c068e3f4 c0668f74

[    0.000000] 7fe0: c0692ef4 0000406a 00000000 c0687ff8 00008074 c06345b4 00000000 00000000

[    0.000000] [<c0100be4>] (kmem_cache_alloc_trace+0x74/0x290) from [<c00922d0>] (alloc_desc+0x34/0xc4)

[    0.000000] [<c00922d0>] (alloc_desc+0x34/0xc4) from [<c0642554>] (early_irq_init+0x98/0xe0)

[    0.000000] [<c0642554>] (early_irq_init+0x98/0xe0) from [<c063475c>] (start_kernel+0x1b4/0x328)

[    0.000000] [<c063475c>] (start_kernel+0x1b4/0x328) from [<00008074>] (0x8074)

[    0.000000] Code: e3c23d7f e3c3303f e5933014 e0863103 (e5931054) 

[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---

[    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!

-------------- next part --------------


U-Boot 2013.01-00001-g7926df4 (Apr 09 2013 - 09:45:48)

I2C:   ready
DRAM:  1 GiB
WARNING: Caches not enabled
MMC:   zynq_sdhci: 0
SF: Detected N25Q128A with page size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   Gem.e000b000
Hit any key to stop autoboot:  3  2  1  0 
TFTPing Linux to RAM...
Gem.e000b000 Waiting for PHY auto negotiation to complete...... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'uImage'.
Load address: 0x3000000
Loading: *#################################################################
	 #################################################################
	 ##################################
	 4.1 MiB/s
done
Bytes transferred = 2395544 (248d98 hex)
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete..... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'devicetree.dtb'.
Load address: 0x2a00000
Loading: *#
	 725.6 KiB/s
done
Bytes transferred = 2975 (b9f hex)
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete..... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'uramdisk.image.gz'.
Load address: 0x2000000
Loading: *#################################################################
	 #################################################################
	 #################################################################
	 ##
	 4.4 MiB/s
done
Bytes transferred = 2889895 (2c18a7 hex)
## Booting kernel from Legacy Image at 03000000 ...
   Image Name:   Linux-3.9.0-11591-g5af43c2
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2395480 Bytes = 2.3 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 02000000 ...
   Image Name:   
   Image Type:   ARM Linux RAMDisk Image (lzma compressed)
   Data Size:    2889831 Bytes = 2.8 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
   Booting using the fdt blob at 0x02a00000
   Loading Kernel Image ... OK
OK
   Loading Ramdisk to 1fd3e000, end 1ffff867 ... OK
   Loading Device Tree to 1fd3a000, end 1fd3db9e ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0

[    0.000000] Linux version 3.9.0-11591-g5af43c2 (sorenb at xsjandreislx) (gcc version 4.7.2 (Sourcery CodeBench Lite 2012.09-104) ) #45 SMP PREEMPT Wed May 8 11:55:01 PDT 2013

[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d

[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

[    0.000000] Machine: Xilinx Zynq Platform, model: Zynq ZC702 Development Board

[    0.000000] bootconsole [earlycon0] enabled

[    0.000000] cma: CMA: reserved 16 MiB at 2e800000

[    0.000000] Memory policy: ECC disabled, Data cache writealloc

[    0.000000] PERCPU: Embedded 9 pages/cpu @c1474000 s13888 r8192 d14784 u36864

[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260624

[    0.000000] Kernel command line: console=ttyPS1,115200 earlyprintk

[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)

[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)

[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)

[    0.000000] Memory: 1024MB = 1024MB total

[    0.000000] Memory: 1007504k/1007504k available, 41072k reserved, 270336K highmem

[    0.000000] Virtual kernel memory layout:

[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)

[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)

[    0.000000]     vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)

[    0.000000]     lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)

[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)

[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)

[    0.000000]       .text : 0xc0008000 - 0xc06338e0   (6319 kB)

[    0.000000]       .init : 0xc0634000 - 0xc0685640   ( 326 kB)

[    0.000000]       .data : 0xc0686000 - 0xc06d0d58   ( 300 kB)

[    0.000000]        .bss : 0xc06d0d58 - 0xc0c60e50   (5697 kB)

[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1

[    0.000000] Preemptible hierarchical RCU implementation.

[    0.000000] 	RCU lockdep checking is enabled.

[    0.000000] 	Additional per-CPU info printed with stalls.

[    0.000000] 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.

[    0.000000] NR_IRQS:16 nr_irqs:16 16

[    0.000000] slcr mapped to f0002000

[    0.000000] ttc0 #0 at f0004000, irq=43

[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms

[    0.000000] Console: colour dummy device 80x30

[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar

[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8

[    0.000000] ... MAX_LOCK_DEPTH:          48

[    0.000000] ... MAX_LOCKDEP_KEYS:        8191

[    0.000000] ... CLASSHASH_SIZE:          4096

[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384

[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768

[    0.000000] ... CHAINHASH_SIZE:          16384

[    0.000000]  memory used by lock dependency info: 3695 kB

[    0.000000]  per task-struct memory footprint: 1152 bytes

[    0.060000] Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)

[    0.150000] pid_max: default: 32768 minimum: 301

[    0.150000] Mount-cache hash table entries: 512

[    0.160000] CPU: Testing write buffer coherency: ok

[    0.160000] ftrace: allocating 15874 entries in 47 pages

[    0.190000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000

[    0.190000] Setting up static identity map for 0xc0455238 - 0xc0455290

[    0.200000] CPU1: Booted secondary processor

[    0.290000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001

[    0.290000] Brought up 2 CPUs

[    0.290000] SMP: Total of 2 processors activated (2664.03 BogoMIPS).

[    0.300000] CPU: All CPU(s) started in SVC mode.

[    0.310000] devtmpfs: initialized

[    0.330000] NET: Registered protocol family 16

[    0.330000] DMA: preallocated 256 KiB pool for atomic coherent allocations

[    0.340000] L310 cache controller enabled

[    0.340000] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 524288 B

[    0.360000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.

[    0.360000] hw-breakpoint: maximum watchpoint size is 4 bytes.

[    0.440000] bio: create slab <bio-0> at 0

[    0.440000] SCSI subsystem initialized

[    0.440000] usbcore: registered new interface driver usbfs

[    0.450000] usbcore: registered new interface driver hub

[    0.450000] usbcore: registered new device driver usb

[    0.470000] Switching to clocksource ttc_clocksource

[    0.620000] NET: Registered protocol family 2

[    0.620000] TCP established hash table entries: 8192 (order: 4, 65536 bytes)

[    0.620000] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)

[    0.640000] TCP: Hash tables configured (established 8192 bind 8192)

[    0.640000] TCP: reno registered

[    0.640000] UDP hash table entries: 512 (order: 3, 40960 bytes)

[    0.650000] UDP-Lite hash table entries: 512 (order: 3, 40960 bytes)

[    0.650000] NET: Registered protocol family 1

[    0.660000] RPC: Registered named UNIX socket transport module.

[    0.660000] RPC: Registered udp transport module.

[    0.670000] RPC: Registered tcp transport module.

[    0.670000] RPC: Registered tcp NFSv4.1 backchannel transport module.

[    0.680000] Trying to unpack rootfs image as initramfs...

[    3.190000] Freeing initrd memory: 2820K (dfd3e000 - dffff000)

[    3.200000] bounce pool size: 64 pages

[    3.250000] jffs2: version 2.2. (NAND) (SUMMARY)  ?? 2001-2006 Red Hat, Inc.

[    3.250000] msgmni has been set to 1477

[    3.260000] io scheduler noop registered

[    3.260000] io scheduler deadline registered

[    3.270000] io scheduler cfq registered (default)

[    3.280000] e0000000.uart: ttyPS0 at MMIO 0xe0000000 (irq = 59) is a xuartps

[    3.280000] e0001?[    3.290000] console [ttyPS1] enabled, bootconsole disabled
[    3.290000] console [ttyPS1] enabled, bootconsole disabled

[    3.330000] brd: module loaded
[    3.350000] loop: module loaded
[    3.370000] usbcore: registered new interface driver usb-storage
[    3.380000] mousedev: PS/2 mouse device common for all mice
[    3.390000] i2c /dev entries driver
[    3.400000] mpcore_wdt: MPcore Watchdog Timer: 0.1. mpcore_noboot=0 mpcore_margin=60 sec (nowayout= 0)
[    3.410000] cpuidle: using governor ladder
[    3.410000] cpuidle: using governor menu
[    3.420000] sdhci: Secure Digital Host Controller Interface driver
[    3.420000] sdhci: Copyright(c) Pierre Ossman
[    3.430000] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.430000] usbcore: registered new interface driver usbhid
[    3.440000] usbhid: USB HID core driver
[    3.440000] TCP: cubic registered
[    3.450000] NET: Registered protocol family 17
[    3.450000] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    3.460000] Registering SWP/SWPB emulation handler
[    3.470000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[    3.480000] Freeing unused kernel memory: 324K (c0634000 - c0685000)
Starting logging: OK
Starting mdev...
mdev: bad line 25
mdev: bad line 26
mdev: bad line 27
mdev: bad line 28
mdev: bad line 29
mdev: bad line 32
mdev: bad line 33
mdev: bad line 34
mdev: bad line 35
Initializing random number generator... done.
Starting network...
Starting dropbear sshd: generating rsa key... generating dsa key... OK

-------------- next part --------------
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.9.0 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_NO_IOPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
# CONFIG_KERNEL_GZIP is not set
CONFIG_KERNEL_LZMA=y
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_FHANDLE is not set
# CONFIG_AUDIT is not set
CONFIG_HAVE_GENERIC_HARDIRQS=y

#
# IRQ subsystem
#
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_SPARSE_IRQ=y
# CONFIG_ALWAYS_USE_PERSISTENT_CLOCK is not set
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set

#
# RCU Subsystem
#
CONFIG_TREE_PREEMPT_RCU=y
CONFIG_PREEMPT_RCU=y
CONFIG_RCU_STALL_COMMON=y
# CONFIG_RCU_USER_QS is not set
CONFIG_RCU_FANOUT=32
CONFIG_RCU_FANOUT_LEAF=16
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_RCU_FAST_NO_HZ is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_RCU_BOOST is not set
# CONFIG_RCU_NOCB_CPU is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_NAMESPACES is not set
CONFIG_UIDGID_CONVERTED=y
# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
# CONFIG_SCHED_AUTOGROUP is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
# CONFIG_RD_LZO is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_HAVE_UID16=y
CONFIG_HOTPLUG=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_TRACEPOINTS=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_FREEZER=y

#
# System Type
#
CONFIG_MMU=y
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P64X0 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP1 is not set

#
# Multiple platform selection
#

#
# CPU Core family selection
#
# CONFIG_ARCH_MULTI_V6 is not set
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MULTI_V6_V7=y
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_BCM is not set
CONFIG_GPIO_PCA953X=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_OMAP2PLUS is not set
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_PLAT_SPEAR is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_SIRF is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_U8500 is not set
CONFIG_ARCH_VEXPRESS=y

#
# Versatile Express platform type
#
# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
# CONFIG_ARCH_VEXPRESS_CA9X4 is not set
CONFIG_PLAT_VERSATILE_CLCD=y
CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y
# CONFIG_ARCH_VIRT is not set
# CONFIG_ARCH_WM8850 is not set
CONFIG_ARCH_ZYNQ=y
CONFIG_PLAT_VERSATILE=y
CONFIG_ARM_TIMER_SP804=y

#
# Processor Type
#
CONFIG_CPU_V7=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y

#
# Processor Features
#
# CONFIG_ARM_LPAE is not set
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
CONFIG_SWP_EMULATE=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_CACHE_L2X0=y
CONFIG_CACHE_PL310=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_ARM_NR_BANKS=8
CONFIG_MULTI_IRQ_HANDLER=y
# CONFIG_ARM_ERRATA_430973 is not set
CONFIG_PL310_ERRATA_588369=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_PL310_ERRATA_727915=y
CONFIG_PL310_ERRATA_753970=y
# CONFIG_ARM_ERRATA_754322 is not set
# CONFIG_ARM_ERRATA_754327 is not set
# CONFIG_ARM_ERRATA_764369 is not set
CONFIG_PL310_ERRATA_769419=y
CONFIG_ARM_ERRATA_775420=y
# CONFIG_ARM_ERRATA_798181 is not set
CONFIG_ICST=y

#
# Bus support
#
CONFIG_ARM_AMBA=y
# CONFIG_PCI_SYSCALL is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_HAVE_SMP=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_ARM_CPU_TOPOLOGY=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_HAVE_ARM_SCU=y
# CONFIG_HAVE_ARM_ARCH_TIMER is not set
CONFIG_HAVE_ARM_TWD=y
# CONFIG_MCPM is not set
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=4
CONFIG_HOTPLUG_CPU=y
# CONFIG_ARM_PSCI is not set
CONFIG_LOCAL_TIMERS=y
CONFIG_ARCH_NR_GPIO=0
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HW_PERF_EVENTS=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
# CONFIG_COMPACTION is not set
CONFIG_MIGRATION=y
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_BOUNCE=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_SECCOMP is not set
# CONFIG_CC_STACKPROTECTOR is not set
# CONFIG_XEN is not set

#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ATAGS=y
# CONFIG_DEPRECATED_PARAM_STRUCT is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_ARM_APPENDED_DTB is not set
CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_EXTEND is not set
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y

#
# CPU Power Management
#
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM_RUNTIME=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_APM_EMULATION is not set
CONFIG_PM_CLK=y
CONFIG_CPU_PM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=m
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_NET_IPVTI is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_LRO=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
# CONFIG_IPV6_PRIVACY is not set
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_SIT=m
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_GRE is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
CONFIG_HAVE_NET_DSA=y
CONFIG_VLAN_8021Q=m
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_MMAP is not set
# CONFIG_NETLINK_DIAG is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
CONFIG_BQL=y
# CONFIG_BPF_JIT is not set

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
# CONFIG_LIB80211 is not set

#
# CFG80211 needs to be enabled for MAC80211
#
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
CONFIG_HAVE_BPF_JIT=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
# CONFIG_DMA_SHARED_BUFFER is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=16
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7

#
# Bus devices
#
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AR7_PARTS is not set

#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
# CONFIG_MTD_PHYSMAP_COMPAT is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PLATRAM is not set

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_M25P80=y
# CONFIG_M25PXX_USE_FAST_READ is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_DOCG3 is not set
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_ECC_BCH is not set
# CONFIG_MTD_SM_COMMON is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_DENALI is not set
# CONFIG_MTD_NAND_GPIO is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_DOCG4 is not set
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_ONENAND is not set

#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set
# CONFIG_MTD_UBI is not set
CONFIG_DTC=y
CONFIG_OF=y

#
# Device Tree and Open Firmware support
#
CONFIG_PROC_DEVICETREE=y
# CONFIG_OF_SELFTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_DEVICE=y
CONFIG_OF_I2C=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
# CONFIG_BLK_DEV_RBD is not set

#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_ATMEL_PWM is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ATMEL_SSC is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_ARM_CHARLCD is not set
# CONFIG_BMP085_I2C is not set
# CONFIG_BMP085_SPI is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set

#
# Altera FPGA firmware download module
#
# CONFIG_ALTERA_STAPL is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
CONFIG_CHR_DEV_SG=y
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_LIBFC is not set
# CONFIG_LIBFCOE is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_HAVE_PATA_PLATFORM=y
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
CONFIG_NETDEVICES=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
CONFIG_MII=y
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set

#
# CAIF transport drivers
#

#
# Distributed Switch Architecture drivers
#
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_MV88E6060 is not set
# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
# CONFIG_NET_DSA_MV88E6131 is not set
# CONFIG_NET_DSA_MV88E6123_61_65 is not set
CONFIG_ETHERNET=y
CONFIG_NET_CADENCE=y
# CONFIG_ARM_AT91_ETHER is not set
CONFIG_MACB=y
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_NET_CALXEDA_XGMAC is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_DM9000 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_FARADAY is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_NET_VENDOR_I825XX=y
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y

#
# MII PHY device drivers
#
# CONFIG_AT803X_PHY is not set
# CONFIG_AMD_PHY is not set
CONFIG_MARVELL_PHY=y
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
CONFIG_VITESSE_PHY=y
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
CONFIG_MDIO_BITBANG=y
# CONFIG_MDIO_GPIO is not set
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set

#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
CONFIG_WLAN=y
# CONFIG_USB_ZD1201 is not set
# CONFIG_HOSTAP is not set
# CONFIG_WL_TI is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=y

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_AMBAKMI is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
# CONFIG_DEVKMEM is not set

#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIAL_KGDB_NMI is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
# CONFIG_SERIAL_ARC is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_HVC_DCC is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_PCA9541 is not set
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_HELPER_AUTO=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_VERSATILE is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX_PCI is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set

#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set

#
# Qualcomm MSM SSBI bus support
#
# CONFIG_SSBI is not set
# CONFIG_HSI is not set

#
# PPS support
#
# CONFIG_PPS is not set

#
# PPS generators support
#

#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# CONFIG_PTP_1588_CLOCK_PCH is not set
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_GPIOLIB=y
CONFIG_OF_GPIO=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y

#
# Memory mapped GPIO drivers:
#
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_EM is not set
# CONFIG_GPIO_PL061 is not set
# CONFIG_GPIO_RCAR is not set
# CONFIG_GPIO_TS5500 is not set
# CONFIG_GPIO_GRGPIO is not set

#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X_IRQ is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SX150X is not set
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_74X164 is not set

#
# AC97 GPIO expanders:
#

#
# MODULbus GPIO expanders:
#

#
# USB GPIO expanders:
#
# CONFIG_W1 is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_BATTERY_BQ27x00 is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GOLDFISH is not set
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
# CONFIG_POWER_AVS is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
# CONFIG_SENSORS_ADM1275 is not set
# CONFIG_SENSORS_LM25066 is not set
# CONFIG_SENSORS_LTC2978 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_UCD9000 is not set
CONFIG_SENSORS_UCD9200=y
# CONFIG_SENSORS_ZL6100 is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH56XX_COMMON is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
CONFIG_MPCORE_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y

#
# Broadcom specific AMBA
#
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
CONFIG_VEXPRESS_CONFIG=y
# CONFIG_REGULATOR is not set
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
# CONFIG_MEDIA_CAMERA_SUPPORT is not set
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_RC_SUPPORT is not set
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_TTPCI_EEPROM is not set

#
# Media drivers
#
# CONFIG_MEDIA_USB_SUPPORT is not set

#
# Supported MMC/SDIO adapters
#
# CONFIG_CYPRESS_FIRMWARE is not set

#
# Media ancillary drivers (tuners, sensors, i2c, frontends)
#

#
# Customise DVB Frontends
#
# CONFIG_DVB_TUNER_DIB0070 is not set
# CONFIG_DVB_TUNER_DIB0090 is not set

#
# Tools to develop new frontends
#
# CONFIG_DVB_DUMMY_FE is not set

#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_TEGRA_HOST1X is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_GOLDFISH is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_AUO_K190X is not set
# CONFIG_EXYNOS_VIDEO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
# CONFIG_LOGO is not set
# CONFIG_FB_SSD1307 is not set
# CONFIG_SOUND is not set

#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO_TPKBD is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_PS3REMOTE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# I2C HID support
#
# CONFIG_I2C_HID is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB_ARCH_HAS_XHCI is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_MUSB_HDRC is not set
# CONFIG_USB_RENESAS_USBHS is not set

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_CHIPIDEA is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HSIC_USB3503 is not set
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_OMAP_CONTROL_USB is not set
# CONFIG_OMAP_USB3 is not set
# CONFIG_SAMSUNG_USBPHY is not set
# CONFIG_SAMSUNG_USB2PHY is not set
# CONFIG_SAMSUNG_USB3PHY is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_RCAR_PHY is not set
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2

#
# USB Peripheral Controller
#
# CONFIG_USB_FUSB300 is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_DUMMY_HCD is not set
CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
# CONFIG_USB_ETH_EEM is not set
# CONFIG_USB_G_NCM is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FUNCTIONFS is not set
CONFIG_USB_MASS_STORAGE=m
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
# CONFIG_USB_G_ACM_MS is not set
# CONFIG_USB_G_MULTI is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_DBGP is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_UNSAFE_RESUME=y
# CONFIG_MMC_CLKGATE is not set

#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_SDHCI_PXAV3 is not set
# CONFIG_MMC_SDHCI_PXAV2 is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
CONFIG_RTC_DRV_PCF8563=y
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_DS3234 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_RX4581 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_DS2404 is not set

#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
# CONFIG_RTC_DRV_PL031 is not set
# CONFIG_RTC_DRV_SNVS is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
# CONFIG_AMBA_PL08X is not set
# CONFIG_DW_DMAC is not set
# CONFIG_TIMB_DMA is not set
CONFIG_PL330_DMA=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y

#
# DMA Clients
#
# CONFIG_NET_DMA is not set
# CONFIG_ASYNC_TX_DMA is not set
CONFIG_DMATEST=y
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=y
# CONFIG_UIO_PDRV is not set
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
# CONFIG_VIRT_DRIVERS is not set

#
# Virtio drivers
#
# CONFIG_VIRTIO_MMIO is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_STAGING is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
CONFIG_COMMON_CLK_DEBUG=y
CONFIG_COMMON_CLK_VERSATILE=y
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set

#
# Hardware Spinlock drivers
#
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CADENCE_TTC_TIMER=y
# CONFIG_MAILBOX is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_OF_IOMMU=y

#
# Remoteproc drivers
#
# CONFIG_STE_MODEM_RPROC is not set

#
# Rpmsg drivers
#
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
CONFIG_MEMORY=y
# CONFIG_IIO is not set
# CONFIG_PWM is not set
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
# CONFIG_IPACK_BUS is not set
CONFIG_RESET_CONTROLLER=y

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
CONFIG_EXT4_FS=y
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_QUOTACTL is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_TMPFS_XATTR is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_F2FS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_SWAP is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set

#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_HIGHMEM is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set

#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_REPEATEDLY is not set
CONFIG_PROVE_RCU_DELAY=y
CONFIG_SPARSE_RCU_POINTER=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
CONFIG_RCU_CPU_STALL_VERBOSE=y
CONFIG_RCU_CPU_STALL_INFO=y
# CONFIG_RCU_TRACE is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
# CONFIG_LKDTM is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_PROBE_EVENTS is not set
CONFIG_DYNAMIC_FTRACE=y
# CONFIG_FUNCTION_PROFILER is not set
CONFIG_FTRACE_MCOUNT_RECORD=y
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_DYNAMIC_DEBUG=y
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
CONFIG_KGDB_SERIAL_CONSOLE=y
# CONFIG_KGDB_TESTS is not set
CONFIG_KGDB_KDB=y
# CONFIG_KDB_KEYBOARD is not set
CONFIG_KDB_CONTINUE_CATASTROPHIC=0
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_STRICT_DEVMEM is not set
CONFIG_ARM_UNWIND=y
CONFIG_OLD_MCOUNT=y
# CONFIG_DEBUG_USER is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ZYNQ_UART0 is not set
CONFIG_DEBUG_ZYNQ_UART1=y
# CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set
# CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set
# CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_SEMIHOSTING is not set
CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S"
CONFIG_DEBUG_UNCOMPRESS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_EARLY_PRINTK=y
# CONFIG_OC_ETM is not set
# CONFIG_PID_IN_CONTEXTIDR is not set

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
# CONFIG_CRYPTO_FIPS is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=m
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_MANAGER2 is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_PCRYPT is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_TEST is not set

#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set

#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set

#
# Hash modes
#
# CONFIG_CRYPTO_CMAC is not set
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA1_ARM is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_ARM is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set

#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_ZLIB is not set
# CONFIG_CRYPTO_LZO is not set

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
CONFIG_CRYPTO_HW=y
CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
# CONFIG_XZ_DEC_ARM is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_BCJ is not set
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_NLATTR=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
# CONFIG_VIRTUALIZATION is not set


From jason at lakedaemon.net  Wed May  8 15:23:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  8 May 2013 19:23:32 +0000
Subject: [RFC PATCH 1/3] ARM: omap3: Seagate Wireless Plus board
In-Reply-To: <cover.1368038129.git.jason@lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
Message-ID: <3721abb26b5f3a54d88b4be9578b0c9d88c92ae0.1368038129.git.jason@lakedaemon.net>

Hynix include file copied from vendor supplied source code.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-omap2/board-generic.c                | 26 +++++++++++++++++++
 arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h | 30 ++++++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index e54a480..10b567c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -21,6 +21,7 @@
 #include "common.h"
 #include "common-board-devices.h"
 #include "dss-common.h"
+#include "sdram-hynix-h8kds0un0mer-4em.h"
 
 #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
 #define intc_of_init	NULL
@@ -51,6 +52,13 @@ static void __init omap_generic_init(void)
 		omap_4430sdp_display_init_of();
 }
 
+static void __init seagate_wireless_plus_init(void)
+{
+	omap_sdrc_init(h8kds0un0mer4em_sdrc_params, NULL);
+
+	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
+}
+
 #ifdef CONFIG_SOC_OMAP2420
 static const char *omap242x_boards_compat[] __initdata = {
 	"ti,omap2420",
@@ -90,6 +98,24 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
+static const char *seagate_wireless_plus_compat[] __initdata = {
+	"seagate,wireless-plus",
+	NULL,
+};
+
+DT_MACHINE_START(SEAGATE_WIRELESS_PLUS_DT, "Seagate Wireless Plus (Flattened Device Tree)")
+	.reserve	= omap_reserve,
+	.map_io		= omap3_map_io,
+	.init_early	= omap3430_init_early,
+	.init_irq	= omap_intc_of_init,
+	.handle_irq	= omap3_intc_handle_irq,
+	.init_machine	= seagate_wireless_plus_init,
+	.init_late	= omap3_init_late,
+	.init_time	= omap3_sync32k_timer_init,
+	.dt_compat	= seagate_wireless_plus_compat,
+	.restart	= omap3xxx_restart,
+MACHINE_END
+
 static const char *omap3_boards_compat[] __initdata = {
 	"ti,omap3",
 	NULL,
diff --git a/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h b/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
new file mode 100644
index 0000000..82b58131
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
@@ -0,0 +1,30 @@
+/*
+ * SDRC register values for the Hynix H8KDS0UN0MER-4EM
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8KDS0UN0MER4EM
+#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8KDS0UN0MER4EM
+
+#include "sdrc.h"
+
+/* Hynix H8KDS0UN0MER-4EM */
+static struct omap_sdrc_params h8kds0un0mer4em_sdrc_params[] = {
+	[0] = {
+		.rate        = 200000000,
+		.actim_ctrla = 0x92e1c4c6,
+		.actim_ctrlb = 0x0002111c,
+		.rfr_ctrl    = 0x0004dc01,
+		.mr          = 0x00000032,
+	},
+	[1] = {
+		.rate        = 0
+	},
+};
+
+#endif
-- 
1.8.2.1



From jason at lakedaemon.net  Wed May  8 15:23:31 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  8 May 2013 19:23:31 +0000
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
Message-ID: <cover.1368038129.git.jason@lakedaemon.net>

All,

This is a work in progress.  All mistakes are mine.  Seriously.  I've never
touched omap before.  It should be obvious.

History:

The Wireless Plus is a portable, 1TB HD with an ~ 4 hour battery, and a wifi
hotspot.  It's only external connection is the SATA port (GoFlex connector).

The Wireless Plus is the successor to the GoFlex Wireless.  Full source can be
found here [1] (GoFlex Wireless).  These appear to be exactly the same at the
hardware level.  The primary difference is drive capacity, and the Wireless
Plus exposes uart1 to an unpopulated header in the corner of the board, so I
chose to develop on it. :-)

Technical:

Both boards are using an AM3703 SoC and the tps6507x power regulator/battery
charger.  Both are using the Hynix h8kds0un0mer-4em RAM module.

Status:

The following patches are a work-in-progress and are based against v3.9.  It
basically boots (to rootfs panic) with patches 1 and 2.  The gpmc patch oops
out.  I've included it in the hopes that someone can laugh at me and maybe give
me a pointer.  I need it to work in order to add the child node for the nand,
and then the child nodes for the partitions.

Tony has been helping me out offline with this, and he suggested trying the
gpmc against Linus' ToT.  Which locks up before it even has a chance to get
going.  So this series is against v3.9.

The current state of the dts file has been to silence warnings/errors.  I
disabled a bunch of unused devices, and added the pinctrl nodes in order to
remove the pins not found kind of errors.  As for their correctness, I haven't
been able to test yet.

I've done a liberal amount of copying from the provided sources for u-boot and
the kernel.  If you're motivated, grepping those sources for 'satellite|vavni'
locates most of the changes made by Seagate.

Current Problem:

There are several gaps in my understanding of how far along TI's conversion to
DT is.  Should I be doing a separate board file for initializing the legacy
items?  I was hoping to do it all with DT.

Obviously, I don't expect anybody to run out and buy one of these, take it
apart, and try to boot this code.  But if the omap guys could take a look at
this and give me a few pointers, I'd appreciate it.  I'm kind of spinning my
wheels at the moment.

Primarily, I'd like to get nand and usb working, so that I can read/write,
mount a rootfs and do better testing.

thx,

Jason.

[1] http://www.seagate.com/support/downloads/item/satellite-gpl-fw-master-dl/

Jason Cooper (3):
  ARM: omap3: Seagate Wireless Plus board
  ARM: omap3: Seagate Wireless Plus DT entry
  ARM: omap3: wireless plus gpmc wip

 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/omap3-wireless_plus.dts          | 331 +++++++++++++++++++++
 arch/arm/mach-omap2/board-generic.c                |  26 ++
 arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h |  30 ++
 4 files changed, 388 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-wireless_plus.dts
 create mode 100644 arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h

-- 
1.8.2.1



From jason at lakedaemon.net  Wed May  8 15:23:34 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  8 May 2013 19:23:34 +0000
Subject: [RFC PATCH 3/3] ARM: omap3: wireless plus gpmc wip
In-Reply-To: <cover.1368038129.git.jason@lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
Message-ID: <35ebdefa151c2f2d49ccfed5ddba0cd627963581.1368038129.git.jason@lakedaemon.net>

Need this in order to add the nand node and then the partitions.

in it's current state, crashes the system. :(
---
 arch/arm/boot/dts/omap3-wireless_plus.dts | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap3-wireless_plus.dts b/arch/arm/boot/dts/omap3-wireless_plus.dts
index 8a0acdf..6f33731 100644
--- a/arch/arm/boot/dts/omap3-wireless_plus.dts
+++ b/arch/arm/boot/dts/omap3-wireless_plus.dts
@@ -17,6 +17,23 @@
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
+
+	gpmc: gpmc at 6800A000 {
+		compatible = "ti,omap2430-gpmc";
+		ti,hwmods = "gpmc";
+		reg = <0x6800A000 0x2000>;
+		/* interrupts = <100>; */
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpmc_pins>;
+
+		gpmc,num-cs = <8>;
+		gpmc,num-waitpins = <2>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0x08000000 0x10000000>;
+
+		/* child nodes go here */
+	};
 };
 
 &omap3_pmx_core {
@@ -26,7 +43,7 @@
 	 * itself during the boot (or just set them up in the bootloader)
 	 */
 	pinctrl-names = "default";
-	pinctrl-0 = <&sdrc_pins &gpmc_pins &hsusb1_pins>;
+	pinctrl-0 = <&sdrc_pins &hsusb1_pins>;
 
 	/* AM3703CUS pins for this board */
 	sdrc_pins: pinmux_sdrc_pins {
-- 
1.8.2.1



From jason at lakedaemon.net  Wed May  8 15:23:33 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  8 May 2013 19:23:33 +0000
Subject: [RFC PATCH 2/3] ARM: omap3: Seagate Wireless Plus DT entry
In-Reply-To: <cover.1368038129.git.jason@lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
Message-ID: <efaa16f8c19fecb6cca807654527490e98011fca.1368038129.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
NOTE: please see coverletter for details.

 arch/arm/boot/dts/Makefile                |   1 +
 arch/arm/boot/dts/omap3-wireless_plus.dts | 314 ++++++++++++++++++++++++++++++
 2 files changed, 315 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-wireless_plus.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c62558..a022a42 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	omap3-beagle-xm.dtb \
 	omap3-evm.dtb \
 	omap3-tobi.dtb \
+	omap3-wireless_plus.dtb \
 	omap4-panda.dtb \
 	omap4-panda-a4.dtb \
 	omap4-panda-es.dtb \
diff --git a/arch/arm/boot/dts/omap3-wireless_plus.dts b/arch/arm/boot/dts/omap3-wireless_plus.dts
new file mode 100644
index 0000000..8a0acdf
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-wireless_plus.dts
@@ -0,0 +1,314 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+	model = "Seagate Wireless Plus (AM3703)";
+	compatible = "seagate,wireless-plus", "ti,omap3";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+};
+
+&omap3_pmx_core {
+
+	/*
+	 * map all board specific static pins enabled by the pinctrl driver
+	 * itself during the boot (or just set them up in the bootloader)
+	 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdrc_pins &gpmc_pins &hsusb1_pins>;
+
+	/* AM3703CUS pins for this board */
+	sdrc_pins: pinmux_sdrc_pins {
+		pinctrl-single,pins = <
+			0x0000 0x100 /* SDRC_D0   (IEN  | PTD | DIS | M0) */
+			0x0002 0x100 /* SDRC_D1   (IEN  | PTD | DIS | M0) */
+			0x0004 0x100 /* SDRC_D2   (IEN  | PTD | DIS | M0) */
+			0x0006 0x100 /* SDRC_D3   (IEN  | PTD | DIS | M0) */
+			0x0008 0x100 /* SDRC_D4   (IEN  | PTD | DIS | M0) */
+			0x000A 0x100 /* SDRC_D5   (IEN  | PTD | DIS | M0) */
+			0x000C 0x100 /* SDRC_D6   (IEN  | PTD | DIS | M0) */
+			0x000E 0x100 /* SDRC_D7   (IEN  | PTD | DIS | M0) */
+			0x0010 0x100 /* SDRC_D8   (IEN  | PTD | DIS | M0) */
+			0x0012 0x100 /* SDRC_D9   (IEN  | PTD | DIS | M0) */
+			0x0014 0x100 /* SDRC_D10  (IEN  | PTD | DIS | M0) */
+			0x0016 0x100 /* SDRC_D11  (IEN  | PTD | DIS | M0) */
+			0x0018 0x100 /* SDRC_D12  (IEN  | PTD | DIS | M0) */
+			0x001A 0x100 /* SDRC_D13  (IEN  | PTD | DIS | M0) */
+			0x001C 0x100 /* SDRC_D14  (IEN  | PTD | DIS | M0) */
+			0x001E 0x100 /* SDRC_D15  (IEN  | PTD | DIS | M0) */
+			0x0020 0x100 /* SDRC_D16  (IEN  | PTD | DIS | M0) */
+			0x0022 0x100 /* SDRC_D17  (IEN  | PTD | DIS | M0) */
+			0x0024 0x100 /* SDRC_D18  (IEN  | PTD | DIS | M0) */
+			0x0026 0x100 /* SDRC_D19  (IEN  | PTD | DIS | M0) */
+			0x0028 0x100 /* SDRC_D20  (IEN  | PTD | DIS | M0) */
+			0x002A 0x100 /* SDRC_D21  (IEN  | PTD | DIS | M0) */
+			0x002C 0x100 /* SDRC_D22  (IEN  | PTD | DIS | M0) */
+			0x002E 0x100 /* SDRC_D23  (IEN  | PTD | DIS | M0) */
+			0x0030 0x100 /* SDRC_D24  (IEN  | PTD | DIS | M0) */
+			0x0032 0x100 /* SDRC_D25  (IEN  | PTD | DIS | M0) */
+			0x0034 0x100 /* SDRC_D26  (IEN  | PTD | DIS | M0) */
+			0x0036 0x100 /* SDRC_D27  (IEN  | PTD | DIS | M0) */
+			0x0038 0x100 /* SDRC_D28  (IEN  | PTD | DIS | M0) */
+			0x003A 0x100 /* SDRC_D29  (IEN  | PTD | DIS | M0) */
+			0x003C 0x100 /* SDRC_D30  (IEN  | PTD | DIS | M0) */
+			0x003E 0x100 /* SDRC_D31  (IEN  | PTD | DIS | M0) */
+			0x0040 0x100 /* SDRC_CLK  (IEN  | PTD | DIS | M0) */
+			0x0042 0x100 /* SDRC_DQS0 (IEN  | PTD | DIS | M0) */
+			0x0044 0x100 /* SDRC_DQS1 (IEN  | PTD | DIS | M0) */
+			0x0046 0x100 /* SDRC_DQS2 (IEN  | PTD | DIS | M0) */
+			0x0048 0x100 /* SDRC_DQS3 (IEN  | PTD | DIS | M0) */
+		>;
+	};
+
+	gpmc_pins: pinmux_gpmc_pins {
+		pinctrl-single,pins = <
+			0x004A 0x018 /* GPMC_A1	      (IDIS | PTU | EN  | M0) */
+			0x004C 0x018 /* GPMC_A2	      (IDIS | PTU | EN  | M0) */
+			0x004E 0x018 /* GPMC_A3	      (IDIS | PTU | EN  | M0) */
+			0x0050 0x018 /* GPMC_A4	      (IDIS | PTU | EN  | M0) */
+			0x0052 0x018 /* GPMC_A5	      (IDIS | PTU | EN  | M0) */
+			0x0054 0x018 /* GPMC_A6	      (IDIS | PTU | EN  | M0) */
+			0x0056 0x018 /* GPMC_A7	      (IDIS | PTU | EN  | M0) */
+			0x0058 0x018 /* GPMC_A8	      (IDIS | PTU | EN  | M0) */
+			0x005A 0x018 /* GPMC_A9	      (IDIS | PTU | EN  | M0) */
+			0x005C 0x018 /* GPMC_A10      (IDIS | PTU | EN  | M0) */
+			0x005E 0x118 /* GPMC_D0	      (IEN  | PTU | EN  | M0) */
+			0x0060 0x118 /* GPMC_D1	      (IEN  | PTU | EN  | M0) */
+			0x0062 0x118 /* GPMC_D2	      (IEN  | PTU | EN  | M0) */
+			0x0064 0x118 /* GPMC_D3	      (IEN  | PTU | EN  | M0) */
+			0x0066 0x118 /* GPMC_D4	      (IEN  | PTU | EN  | M0) */
+			0x0068 0x118 /* GPMC_D5	      (IEN  | PTU | EN  | M0) */
+			0x006A 0x118 /* GPMC_D6	      (IEN  | PTU | EN  | M0) */
+			0x006C 0x118 /* GPMC_D7	      (IEN  | PTU | EN  | M0) */
+			0x006E 0x118 /* GPMC_D8	      (IEN  | PTU | EN  | M0) */
+			0x0070 0x118 /* GPMC_D9	      (IEN  | PTU | EN  | M0) */
+			0x0072 0x118 /* GPMC_D1	      (IEN  | PTU | EN  | M0) */
+			0x0074 0x118 /* GPMC_D11      (IEN  | PTU | EN  | M0) */
+			0x0076 0x118 /* GPMC_D12      (IEN  | PTU | EN  | M0) */
+			0x0078 0x118 /* GPMC_D13      (IEN  | PTU | EN  | M0) */
+			0x007A 0x118 /* GPMC_D14      (IEN  | PTU | EN  | M0) */
+			0x007C 0x118 /* GPMC_D15      (IEN  | PTU | EN  | M0) */
+			0x007E 0x018 /* GPMC_NCS0     (IDIS | PTU | EN  | M0) */
+			0x0080 0x018 /* GPMC_NCS1     (IDIS | PTU | EN  | M0) */
+			0x0082 0x018 /* GPMC_NCS2     (IDIS | PTU | EN  | M0) */
+			0x0084 0x018 /* GPMC_NCS3     (IDIS | PTU | EN  | M0) */
+			0x0086 0x118 /* GPMC_NCS4     (IEN  | PTU | EN  | M0) */
+			0x0088 0x018 /* GPMC_NCS5     (IDIS | PTU | EN  | M0) */
+			0x008A 0x100 /* GPMC_NCS6     (IEN  | PTD | DIS | M0) */
+			0x008C 0x118 /* GPMC_NCS7     (IEN  | PTU | EN  | M0) */
+			0x008E 0x018 /* GPMC_CLK      (IDIS | PTU | EN  | M0) */
+			0x0090 0x000 /* GPMC_NADV_ALE (IDIS | PTD | DIS | M0) */
+			0x0092 0x000 /* GPMC_NOE      (IDIS | PTD | DIS | M0) */
+			0x0094 0x000 /* GPMC_NWE      (IDIS | PTD | DIS | M0) */
+			0x0096 0x018 /* GPMC_NBE0_CLE (IDIS | PTU | EN  | M0) */
+			0x0098 0x118 /* GPMC_NBE1     (IEN  | PTU | EN  | M0) */
+			0x009A 0x100 /* GPMC_NWP      (IEN  | PTD | DIS | M0) */
+			0x009C 0x118 /* GPMC_WAIT0    (IEN  | PTU | EN  | M0) */
+			0x009E 0x118 /* GPMC_WAIT1    (IEN  | PTU | EN  | M0) */
+			0x00A0 0x11C /* GPIO_64       (IEN  | PTU | EN  | M4) */
+			0x00A2 0x118 /* GPMC_WAIT3    (IEN  | PTU | EN  | M0) */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pincntl-single,pins = <
+			0x0114 0x018 /* MMC1_CLK  (IDIS | PTU | EN  | M0) */
+			0x0116 0x118 /* MMC1_CMD  (IEN  | PTU | EN  | M0) */
+			0x0118 0x118 /* MMC1_DAT0 (IEN  | PTU | EN  | M0) */
+			0x011A 0x118 /* MMC1_DAT1 (IEN  | PTU | EN  | M0) */
+			0x011C 0x118 /* MMC1_DAT2 (IEN  | PTU | EN  | M0) */
+			0x011E 0x118 /* MMC1_DAT3 (IEN  | PTU | EN  | M0) */
+			0x0120 0x118 /* MMC1_DAT4 (IEN  | PTU | EN  | M0) */
+			0x0122 0x118 /* MMC1_DAT5 (IEN  | PTU | EN  | M0) */
+			0x0124 0x118 /* MMC1_DAT6 (IEN  | PTU | EN  | M0) */
+			0x0126 0x118 /* MMC1_DAT7 (IEN  | PTU | EN  | M0) */
+		>;
+	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			0x0128 0x100 /* MMC2_CLK  (IEN  | PTD | DIS | M0) */
+			0x012A 0x118 /* MMC2_CMD  (IEN  | PTU | EN  | M0) */
+			0x012C 0x118 /* MMC2_DAT0 (IEN  | PTU | EN  | M0) */
+			0x012E 0x118 /* MMC2_DAT1 (IEN  | PTU | EN  | M0) */
+			0x0130 0x118 /* MMC2_DAT2 (IEN  | PTU | EN  | M0) */
+			0x0132 0x118 /* MMC2_DAT3 (IEN  | PTU | EN  | M0) */
+			0x0134 0x000 /* MMC2_DAT4 (IDIS | PTD | DIS | M0) */
+			0x0136 0x000 /* MMC2_DAT5 (IDIS | PTD | DIS | M0) */
+			0x0138 0x000 /* MMC2_DAT6 (IDIS | PTD | DIS | M0) */
+			0x013A 0x118 /* MMC2_DAT7 (IEN  | PTU | EN  | M0) */
+		>;
+	};
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			0x014C 0x000 /* UART1_TX  (IDIS | PTD | DIS | M0) */
+			0x014E 0x000 /* UART1_RTS (IDIS | PTD | DIS | M0) */
+			0x0150 0x110 /* UART1_CTS (IEN  | PTU | DIS | M0) */
+			0x0152 0x100 /* UART1_RX  (IEN  | PTD | DIS | M0) */
+		>;
+	};
+
+	hsusb1_pins: pinmux_hsusb1_pins {
+		pinctrl-single,pins = <
+			0x0172 0x100 /* HSUSB0_CLK   (IEN  | PTD | DIS | M0) */
+			0x0174 0x018 /* HSUSB0_STP   (IDIS | PTU | EN  | M0) */
+			0x0176 0x100 /* HSUSB0_DIR   (IEN  | PTD | DIS | M0) */
+			0x0178 0x100 /* HSUSB0_NXT   (IEN  | PTD | DIS | M0) */
+			0x017A 0x100 /* HSUSB0_DATA0 (IEN  | PTD | DIS | M0) */
+			0x017C 0x100 /* HSUSB0_DATA1 (IEN  | PTD | DIS | M0) */
+			0x017E 0x100 /* HSUSB0_DATA2 (IEN  | PTD | DIS | M0) */
+			0x0180 0x100 /* HSUSB0_DATA3 (IEN  | PTD | DIS | M0) */
+			0x0182 0x100 /* HSUSB0_DATA4 (IEN  | PTD | DIS | M0) */
+			0x0184 0x100 /* HSUSB0_DATA5 (IEN  | PTD | DIS | M0) */
+			0x0186 0x100 /* HSUSB0_DATA6 (IEN  | PTD | DIS | M0) */
+			0x0188 0x100 /* HSUSB0_DATA7 (IEN  | PTD | DIS | M0) */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x018A 0x118 /* I2C1_SCL (IEN  | PTU | EN  | M0) */
+			0x018C 0x118 /* I2C1_SDA (IEN  | PTU | EN  | M0) */
+		>;
+	};
+
+	i2c4_pins: pinmux_i2c4_pins {
+		pinctrl-single,pins = <
+			0x09D0 0x007 /* I2C4_SCL (IDIS  | PTD | DIS | M7) */
+			0x09D2 0x007 /* I2C4_SDA (IDIS  | PTD | DIS | M7) */
+		>;
+	};
+
+	gpio170_pin: pinmux_gpio170_pin {
+		/* GPIO_170 Power_ON pin */
+		pinctrl-single,pins = <
+			0x0196 0x01C /* HDQ_SIO (IDIS | PTU | EN | M4) */
+		>;
+	};
+
+	gpio95_pin: pinmux_gpio95_pin {
+		/* GPIO_95 WLAN RESET keep low */
+		pinctrl-single,pins = <
+			0x00DE 0x00C /* CAM_VS  (IDIS | PTD | EN | M4) */
+		>;
+	};
+
+
+
+
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	pmu: tps6507x at 48 {
+		compatible = "ti,tps6507x";
+		reg = <0x48>;
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vdcdc1_reg: regulator at 0 {
+				regulator-compatible = "VDCDC1";
+				reg = <0>;
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			vdcdc2_reg: regulator at 1 {
+				regulator-compatible = "VDCDC2";
+				reg = <1>;
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				defdcdc_default = <1>;
+			};
+			vdcdc3_reg: regulator at 2 {
+				regulator-compatible = "VDCDC3";
+				reg = <2>;
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				defdcdc_default = <1>;
+			};
+			ldo1_reg: regulator at 3 {
+				regulator-compatible = "LDO1";
+				reg = <3>;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+			ldo2_reg: regulator at 4 {
+				regulator-compatible = "LDO2";
+				reg = <4>;
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+/* optional on board WiFi */
+&mmc2 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&i2c3 {
+	status = "disabled";
+};
+
+&uart2 {
+	status = "disabled";
+};
+
+&uart3 {
+	status = "disabled";
+};
+
+&mcspi1 {
+	status = "disabled";
+};
+
+&mcspi2 {
+	status = "disabled";
+};
+
+&mcspi3 {
+	status = "disabled";
+};
+
+&mcspi4 {
+	status = "disabled";
+};
-- 
1.8.2.1



From olof at lixom.net  Wed May  8 15:28:28 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed, 8 May 2013 12:28:28 -0700
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <5189BA36.9000105@wwwdotorg.org>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <201304300004.20320.arnd@arndb.de> <5182AF83.4080705@wwwdotorg.org>
 <1956593.M6NmITdEKh@avalon>
 <20130507143338.79b3d893fcdc3bd79fbe9a57@linux-foundation.org>
 <5189BA36.9000105@wwwdotorg.org>
Message-ID: <CAOesGMhTu_eO564LCyWa2wL1VfposvsK1fxAu1RXCXLZJ0DSfQ@mail.gmail.com>

On Tue, May 7, 2013 at 7:36 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 05/07/2013 03:33 PM, Andrew Morton wrote:
>>
>> We don't seem to have a well-defined path to travel here, and I don't
>> get the feeling that anyone has signed up to walk it?
>>
>> So I'm inclined to merge Stephen's patch as-is into 3.10.  It's pretty
>> simple and standalone.  Any strenuous objections?
>>
>> BTW, Olof told me off-list that this patch is a "critical piece" for
>> running mainline Linux on ARM Chromebooks.  That was important
>> information - more important than anything else we were told about this
>> patch!
>>
>> So Stephen, could I please have a new changelog for this patch which
>> explains this application, and any other interesting/important things
>> which were left out?  Quickly, please.
>
> OK, how about the version below:
>
> ----------
> Subject: drivers/video: implement a simple framebuffer driver
>
> A simple frame-buffer describes a raw memory region that may be rendered
> to, with the assumption that the display hardware has already been set
> up to scan out from that buffer.
>
> This is useful in cases where a bootloader exists and has set up the
> display hardware, but a Linux driver doesn't yet exist for the display
> hardware.
>
> Examples use-cases include:
>
> * The built-in LCD panels on the Samsung ARM chromebook, and Tegra
> devices, and likely many other ARM or embedded systems. These cannot yet
> be supported using a full graphics driver, since the panel control
> should be provided by the CDF (Common Display Framework), which has been
> stuck in design/review for quite some time. One could support these
> panels using custom SoC-specific code, but there is a desire to use
> common infra-structure rather than having each SoC vendor invent their
> own code, hence the desire to wait for CDF.
>
> * Hardware for which a full graphics driver is not yet available, and
> the path to obtain one upstream isn't yet clear. For example, the
> Raspberry Pi.
>
> * Any hardware in early stages of upstreaming, before a full graphics
> driver has been tackled. This driver can provide a graphical boot
> console (even full X support) much earlier in the upstreaming process,
> thus making new SoC or board support more generally useful earlier.
> ----------
>
> I assume you can just edit the patch you have and don't need me to
> resend with the adjusted description.

Oh, looks like it never got a:

Acked-by: Olof Johansson <olof at lixom.net>

Either. Feel free to add, Andrew.


-Olof


From gmbnomis at gmail.com  Wed May  8 15:31:30 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Wed, 8 May 2013 21:31:30 +0200
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130508184354.GQ18614@n2100.arm.linux.org.uk>
References: <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
 <20130508150800.GI2703@arm.com>
 <20130508184354.GQ18614@n2100.arm.linux.org.uk>
Message-ID: <20130508193130.GA31678@schnuecks.de>

Hi Russel,

On Wed, May 08, 2013 at 07:43:54PM +0100, Russell King - ARM Linux wrote:
> On Wed, May 08, 2013 at 04:08:00PM +0100, Catalin Marinas wrote:
> > On Sat, May 04, 2013 at 09:21:27AM +0100, Ming Lei wrote:
> > > On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
> > > >>
> > > >> I assume that you inhibited the call to flush_dcache_page() in
> > > >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
> > > >> with warnings.
> > > >
> > > > I haven't done any stress testing so I don't think I hit this code path,
> > > > so no warning. But yes, it should have triggered. Anyway, in this case
> > > > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
> > > > harmless anyway if we also ignore this bit in __sync_icache_dcache for
> > > > non-aliasing caches).
> > > 
> > > Yes, maybe we can do a little optimization for O_DIRECT since no
> > > dcache alias and I/D coherency problem in this case on ARMv7, how
> > > about below change?
> > > 
> > > diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> > > index 1c8f7f5..962a657 100644
> > > --- a/arch/arm/mm/flush.c
> > > +++ b/arch/arm/mm/flush.c
> > > @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
> > >  	    mapping && !mapping_mapped(mapping))
> > >  		clear_bit(PG_dcache_clean, &page->flags);
> > >  	else {
> > > +		if (!mapping && cache_is_vipt_nonaliasing())
> > > +			return;
> > >  		__flush_dcache_page(mapping, page);
> > >  		if (mapping && cache_is_vivt())
> > >  			__flush_dcache_aliases(mapping, page);
> > 
> > I wonder whether we could move the:
> > 
> > 	if (!mapping)
> > 		return
> > 
> > at the top of this function, IOW don't touch any anonymous pages. Would
> > anything be broken (apart from wrong API use)?
> 
> I suspect you may be missing something - and I suggest reading the Sparc
> version, which is where this PG_arch_1 stuff was first dreamed up (by
> DaveM).
> 
> Are you positive that this path can be eliminated?  Totally sure?  Have
> you checked the arg/env pages that fs/exec.c and the binfmt's insert into
> the new process?
> 
> The comments against the Sparc version suggest that the "else" clause
> is necessary ensure that case is adequately covered.

At least the fs/exec.c and the binfmt stuff use
flush_kernel_dcache_page() for 5 years or so now (see commit b6a2fe). 
Which makes sense, since flush_dcache_page() is not supposed to
handle anon pages anyway.

The problem are the tons of flush_dcache_page() uses that wrongly
assume that no anon pages need to be handled (e.g. 
drivers/block/loop.c and crypto/scatterwalk.c just to name two).

- Simon


From paul at pwsan.com  Wed May  8 15:33:25 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 8 May 2013 19:33:25 +0000 (UTC)
Subject: OMAP baseline test results for v3.9-rc8
Message-ID: <alpine.DEB.2.00.1305081931470.19747@utopia.booyaka.com>



Here are some basic OMAP test results for Linux v3.9-rc8.
Logs and other details at:

    http://www.pwsan.com/omap/testlogs/test_v3.9-rc8/20130422154921/


Test summary
------------

Build:
    FAIL ( 2/16): am33xx_only, omap2plus_defconfig_2430sdp_only
    Pass (14/16): n800_multi_omap2xxx, n800_only_a, omap1_defconfig, 
                  omap1_defconfig_1510innovator_only, 
                  omap1_defconfig_5912osk_only, omap2plus_defconfig, 
                  omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, 
                  omap2plus_defconfig_omap2_4_only, 
                  omap2plus_defconfig_omap3_4_only, 
                  rmk_omap3430_ldp_allnoconfig, 
                  rmk_omap3430_ldp_oldconfig, 
                  rmk_omap4430_sdp_allnoconfig, 
                  rmk_omap4430_sdp_oldconfig

Boot to userspace:
    FAIL ( 1/11): am335xbone
    Pass (10/11): 2420n800, 2430sdp, 3517evm, 3530es3beagle,
                  3730beaglexm, 37xxevm, 4430es2panda, 4460pandaes,
                  5912osk, cmt3517

PM ret, suspend:
    FAIL ( 2/ 6): 2430sdp, 4430es2panda
    Pass ( 4/ 6): 3530es3beagle, 3730beaglexm, 37xxevm, 4460pandaes

PM ret, dynamic idle:
    FAIL ( 3/ 6): 2430sdp, 4430es2panda, 4460pandaes
    Pass ( 3/ 6): 3530es3beagle, 3730beaglexm, 37xxevm

PM off, suspend:
    FAIL ( 2/ 5): 4430es2panda, 4460pandaes
    Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm

PM off, dynamic idle:
    FAIL ( 2/ 5): 4430es2panda, 4460pandaes
    Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm



Failing tests: fixed by posted patches
--------------------------------------

Build:

* am33xx_only, omap2plus_defconfig_2430sdp_only: omap-{smp,hotplug}.c link errors
  - Discussion & RFC patch: http://www.spinics.net/lists/arm-kernel/msg230017.html
  - Still needs revision of the patch


Failing tests: needing investigation
------------------------------------

Boot tests:

* 3517EVM & CM-T3517: boot hangs with NFS root
  - Likely some Kconfig, board file, and PM issues with EMAC
  - Longstanding bug
  - Not currently part of the automated test suite

Boot warnings:

* CM-T3517: L3 in-band error with IPSS during boot
  - Cause unknown but see http://marc.info/?l=linux-omap&m=134833869730129&w=2
  - Longstanding issue; does not occur on the 3517EVM

PM tests:

* 2430sdp: power domains not entering retention
  - Cause unknown

* 4430es2panda, 4460pandaes: pwrdm state mismatch on CAM, DSS, ABE

* 4460pandaes: pwrdm state mismatch on IVAHD, TESLA 

* 4430es2panda: CORE, TESLA, IVAHD, L3INIT didn't enter target state
  - Probably due to lack of reset code for M3, DSP, SL2IF, FSUSB
    per discussion with Tero Kristo
  - Likely dependent on the bootloader version
    - fails with 2012.07-00136-g755de79
  - http://marc.info/?l=linux-arm-kernel&m=136432340618226&w=2

* 4460pandaes: chip not entering retention in dynamic idle
  - Presumably 4430es2panda also fails this
  - Suspend-to-RAM enters full chip retention

* 3730 Beagle XM: does not serial wake from off-idle suspend when console
  UART doesn't clock-gate ("debug ignore_loglevel")
  - Cause unknown
  - Not yet part of the automated test suite
  - Re-tested at v3.7; still failing:
    http://www.pwsan.com/omap/transcripts/20121211-3730beaglexm-3.7-pm-offmode-fail-debug.txt

Other:

* 4430es2panda: omap_hwmod: l3_instr: _wait_target_disable failed
  - Unknown cause; could be due to the lack of hierarchical enable/disable
    in hwmod code
  - Jon Hunter and Santosh Shilimkar report this does not appear with
    the same X-loader/bootloader on his 4430ES2.3 Panda, so could be
    ES-level dependent


Failing tests: reported by others 
---------------------------------

- MUSB broken after v3.9-rc6
  - due to commit 92702df3570e1ccfa050e135e50c450502251b79
  - discussion here: http://marc.info/?l=linux-omap&m=136544098331552&w=2
  - patch pending upstream:
    http://marc.info/?l=linux-omap&m=136562302329307&w=2



vmlinux object size
(delta in bytes from test_v3.9-rc7 
(41ef2d5678d83af030125550329b6ae8b74618fa)):
   text     data      bss    total  kernel
   +408       +8        0     +416  n800_multi_omap2xxx
   +408       +8        0     +416  n800_only_a
    +54       -8        0      +46  omap1_defconfig
    +58       -8        0      +50  omap1_defconfig_1510innovator_only
    +54      +24        0      +78  omap1_defconfig_5912osk_only
   +252      +96        0     +348  omap2plus_defconfig
  +4348      +72        0    +4420  omap2plus_defconfig_cpupm
   +388      +64        0     +452  omap2plus_defconfig_no_pm
   +252      +72        0     +324  omap2plus_defconfig_omap2_4_only
  +4236      +80        0    +4316  omap2plus_defconfig_omap3_4_only
   +168      +16      -40     +144  rmk_omap3430_ldp_allnoconfig
  -4040       -8        0    -4048  rmk_omap3430_ldp_oldconfig
   +168      +16      -40     +144  rmk_omap4430_sdp_allnoconfig
   +192        0       +8     +200  rmk_omap4430_sdp_oldconfig




From olof at lixom.net  Wed May  8 15:33:34 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed, 8 May 2013 12:33:34 -0700
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
In-Reply-To: <CAD=FV=X2n+zHZ3frorwW7L1yybnWWK1=-rWMQJQFus3eNiFFeQ@mail.gmail.com>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
 <CAOesGMia9kLGh6B6QJZAKS1UpBg86v32S2um+0fjx5HYjje3cw@mail.gmail.com>
 <CAD=FV=X2n+zHZ3frorwW7L1yybnWWK1=-rWMQJQFus3eNiFFeQ@mail.gmail.com>
Message-ID: <CAOesGMi=K4iJKjSk3RoynhiCMPPT98v5jADnqZ__TwX_YLw65Q@mail.gmail.com>

Hi,


On Wed, May 8, 2013 at 11:48 AM, Doug Anderson <dianders at chromium.org> wrote:
> Olof,
>
> On Wed, May 8, 2013 at 11:19 AM, Olof Johansson <olof at lixom.net> wrote:
>> Seems like this should be selected by the SoC (ARCH_EXYNOS5) instead
>> of the board. Actually, I'm not sure we need the board Kconfig entry
>> long-term; all boards will be dt-only.
>
> Good point.  Hopefully someone at Samsung can work on removing the
> board itself?  If you'd like me to take this on then let me know and I
> can put it on my list.

Nothing stops you from doing that on your own. I tend to push back
onto the maintainers to get them engaged in their own housekeeping,
but anyone is free to :)

> I'm happy to resubmit my patch under ARCH_EXYNOS5.  I'll move the
> exynos4 one at the same time.

Great.

> I'm going to make the assumption that PINCTRL_EXYNOS and
> PINCTRL_EXYNOS5440 can happily coexist.  Certainly I've got both
> defined in my tree right now and nothing blows up.  I haven't tested
> on 5440 but things ought to be handled by "compatible" checks, right?

Yes, if they can't coexist then that's a bug.

> I'll also assume that eventually someone will move PINCTRL_EXYNOS5440
> into PINCTRL_EXYNOS.  If PINCTRL_EXYNOS5440 won't eventually move
> under PINCTRL_EXYNOS then it makes less sense to define PINCTRL_EXYNOS
> for all exynos parts.

Yeah, it should -- this is just in transition since 5440 was first out
of the gate with pinctrl.



-Olof


From tony at atomide.com  Wed May  8 15:39:07 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 12:39:07 -0700
Subject: [REGRESSION] SLAB allocator (on Zynq)
In-Reply-To: <9d9b2266-e09e-4366-80ef-3df5db775f25@TX2EHSMHS033.ehs.local>
References: <9d9b2266-e09e-4366-80ef-3df5db775f25@TX2EHSMHS033.ehs.local>
Message-ID: <20130508193906.GC32546@atomide.com>

Hi,

* S?ren Brinkmann <soren.brinkmann at xilinx.com> [130508 12:26]:
> Hi,
> 
> I compiled the latest kernel for Zynq and ran into issues when the SLAB
> allocator is selected. Booting crashes early with a NULL pointer
> dereference (boot log attached).
> Switching to the SLUB allocator resolves the issue (boot log attached).

There's a fix for this now in lkml thread
"[GIT PULL] SLAB changes for v3.10":

http://lkml.org/lkml/2013/5/8/374#

Regards,

Tony


From paul at pwsan.com  Wed May  8 15:39:59 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 8 May 2013 19:39:59 +0000 (UTC)
Subject: OMAP baseline test results for v3.9
Message-ID: <alpine.DEB.2.00.1305081933270.19747@utopia.booyaka.com>


Here are some basic OMAP test results for Linux v3.9.
Logs and other details at:

    http://www.pwsan.com/omap/testlogs/test_v3.9/20130429104339/


Test summary
------------

Build:
    FAIL ( 2/16): am33xx_only, omap2plus_defconfig_2430sdp_only
    Pass (14/16): n800_multi_omap2xxx, n800_only_a, omap1_defconfig, 
                  omap1_defconfig_1510innovator_only, 
                  omap1_defconfig_5912osk_only, omap2plus_defconfig, 
                  omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, 
                  omap2plus_defconfig_omap2_4_only, 
                  omap2plus_defconfig_omap3_4_only, 
                  rmk_omap3430_ldp_allnoconfig, 
                  rmk_omap3430_ldp_oldconfig, 
                  rmk_omap4430_sdp_allnoconfig, 
                  rmk_omap4430_sdp_oldconfig

Boot to userspace:
    FAIL ( 1/11): am335xbone
    Pass (10/11): 2420n800, 2430sdp, 3517evm, 3530es3beagle,
                  3730beaglexm, 37xxevm, 4430es2panda, 4460pandaes,
                  5912osk, cmt3517

PM ret, suspend:
    FAIL ( 2/ 6): 2430sdp, 4430es2panda
    Pass ( 4/ 6): 3530es3beagle, 3730beaglexm, 37xxevm, 4460pandaes

PM ret, dynamic idle:
    FAIL ( 3/ 6): 2430sdp, 4430es2panda, 4460pandaes
    Pass ( 3/ 6): 3530es3beagle, 3730beaglexm, 37xxevm

PM off, suspend:
    FAIL ( 2/ 5): 4430es2panda, 4460pandaes
    Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm

PM off, dynamic idle:
    FAIL ( 2/ 5): 4430es2panda, 4460pandaes
    Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm



Failing tests: fixed by posted patches
--------------------------------------

Build:

* am33xx_only, omap2plus_defconfig_2430sdp_only: omap-{smp,hotplug}.c link errors
  - Discussion & RFC patch: http://www.spinics.net/lists/arm-kernel/msg230017.html
  - Still needs revision of the patch


Failing tests: needing investigation
------------------------------------

Boot tests:

* 3517EVM & CM-T3517: boot hangs with NFS root
  - Likely some Kconfig, board file, and PM issues with EMAC
  - Longstanding bug
  - Not currently part of the automated test suite

Boot warnings:

* CM-T3517: L3 in-band error with IPSS during boot
  - Cause unknown but see http://marc.info/?l=linux-omap&m=134833869730129&w=2
  - Longstanding issue; does not occur on the 3517EVM

PM tests:

* 2430sdp: power domains not entering retention
  - Cause unknown

* 4430es2panda, 4460pandaes: pwrdm state mismatch on CAM, DSS, ABE

* 4460pandaes: pwrdm state mismatch on IVAHD, TESLA 

* 4430es2panda: CORE, TESLA, IVAHD, L3INIT didn't enter target state
  - Probably due to lack of reset code for M3, DSP, SL2IF, FSUSB
    per discussion with Tero Kristo
  - Likely dependent on the bootloader version
    - fails with 2012.07-00136-g755de79
  - http://marc.info/?l=linux-arm-kernel&m=136432340618226&w=2

* 4460pandaes: chip not entering retention in dynamic idle
  - Presumably 4430es2panda also fails this
  - Suspend-to-RAM enters full chip retention

* 3730 Beagle XM: does not serial wake from off-idle suspend when console
  UART doesn't clock-gate ("debug ignore_loglevel")
  - Cause unknown
  - Not yet part of the automated test suite
  - Re-tested at v3.7; still failing:
    http://www.pwsan.com/omap/transcripts/20121211-3730beaglexm-3.7-pm-offmode-fail-debug.txt

Other:

* 4430es2panda: omap_hwmod: l3_instr: _wait_target_disable failed
  - Unknown cause; could be due to the lack of hierarchical enable/disable
    in hwmod code
  - Jon Hunter and Santosh Shilimkar report this does not appear with
    the same X-loader/bootloader on his 4430ES2.3 Panda, so could be
    ES-level dependent


vmlinux object size
(delta in bytes from test_v3.9-rc8 
(60d509fa6a9c4653a86ad830e4c4b30360b23f0e)):
   text     data      bss    total  kernel
   +176       +8        0     +184  n800_multi_omap2xxx
   +160       +8        0     +168  n800_only_a
   +120       +8        0     +128  omap1_defconfig
   +136       +8        0     +144  omap1_defconfig_1510innovator_only
   +152      -24        0     +128  omap1_defconfig_5912osk_only
   +204        0        0     +204  omap2plus_defconfig
   +204        0        0     +204  omap2plus_defconfig_cpupm
   +204        0        0     +204  omap2plus_defconfig_no_pm
   +204        0        0     +204  omap2plus_defconfig_omap2_4_only
   +204        0        0     +204  omap2plus_defconfig_omap3_4_only
   +132        0        0     +132  rmk_omap3430_ldp_allnoconfig
    +80        0        0      +80  rmk_omap3430_ldp_oldconfig
   +132        0        0     +132  rmk_omap4430_sdp_allnoconfig
    +96        0        0      +96  rmk_omap4430_sdp_oldconfig



vmlinux object size
(delta in bytes from test_v3.8 
(19f949f52599ba7c3f67a5897ac6be14bfcb1200)):
   text     data      bss    total  kernel
-549808   +23520    -9184  -535472  n800_multi_omap2xxx
-548359   +27432    -9268  -530195  n800_only_a
 +61909    +5680     +392   +67981  omap1_defconfig
 +62549    +5664     +424   +68637  omap1_defconfig_1510innovator_only
 +63725    +5672     +328   +69725  omap1_defconfig_5912osk_only
+215063   +40984    +1364  +257411  omap2plus_defconfig
+209163   +40088    +1364  +250615  omap2plus_defconfig_cpupm
+213279   +39256    +1364  +253899  omap2plus_defconfig_no_pm
+206200   +34440    +1428  +242068  omap2plus_defconfig_omap2_4_only
+200798   +44440    +1364  +246602  omap2plus_defconfig_omap3_4_only
  -5420    +9908    +2428    +6916  rmk_omap3430_ldp_allnoconfig
 +43627   +27696     +788   +72111  rmk_omap3430_ldp_oldconfig
  -5420    +9908    +2428    +6916  rmk_omap4430_sdp_allnoconfig
 +46204   +14712     +980   +61896  rmk_omap4430_sdp_oldconfig


Boot-time memory difference
(delta in bytes from test_v3.8 (19f949f52599ba7c3f67a5897ac6be14bfcb1200))
  avail  rsrvd   high  freed  board          kconfig
 -15904k 15904k      .     4k  2420n800       n800_only_a
 -16668k 16668k      .    12k  2430sdp        omap2plus_defconfig
 -16668k 16668k      .    12k  3517evm        omap2plus_defconfig
 -16668k 16668k      .    12k  3530es3beagle  omap2plus_defconfig
 -16668k 16668k      .    12k  3730beaglexm   omap2plus_defconfig
 -16668k 16668k      .    12k  37xxevm        omap2plus_defconfig
 -16660k 16660k      .    12k  4430es2panda   omap2plus_defconfig
 -16680k 16680k      .    12k  4460pandaes    omap2plus_defconfig
   -68k    68k      .     4k  5912osk        omap1_defconfig

16MiB of the reserved memory increase is probably due to CMA.



From tony at atomide.com  Wed May  8 15:45:04 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 12:45:04 -0700
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <cover.1368038129.git.jason@lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
Message-ID: <20130508194504.GD32546@atomide.com>

* Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> 
> Tony has been helping me out offline with this, and he suggested trying the
> gpmc against Linus' ToT.  Which locks up before it even has a chance to get
> going.  So this series is against v3.9.

You may have better luck with today's mainline treeand the following fix:

http://lkml.org/lkml/2013/5/8/374#

Regards,

Tony


From arnd at arndb.de  Wed May  8 15:48:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 21:48:10 +0200
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <518A8C1D.3090600@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de> <518A8C1D.3090600@st.com>
Message-ID: <201305082148.10933.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> the pinctrl driver calls syconf_claim(np, "st,alt-control) to get a
> field and then do a read/write on the field.
> 
> Just in pinctrl driver we use around 50-100 sysconf registers scatters
> across different groups.
> 
> Without these new APIs, its very difficult to pass this information to
> the drivers.

But are those necessarily things you would configure using DT?

If there are so many registers that are shared between mutliple
subsystems, maybe using drivers/mfd/syscon for that is taking things
further than you should, since it is unlike what any of the other
SoC families need from syscon.

Can you describe how your syscon registers are laid out?
Which subsystems beside pinctrl need to directly interact
with it? Is there any logical structure in it or do you just
have tons of bits scattered around an MMIO area?

	Arnd


From tony at atomide.com  Wed May  8 15:51:53 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 12:51:53 -0700
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <cover.1368038129.git.jason@lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
Message-ID: <20130508195152.GE32546@atomide.com>

* Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> 
> Current Problem:
> 
> There are several gaps in my understanding of how far along TI's conversion to
> DT is.  Should I be doing a separate board file for initializing the legacy
> items?  I was hoping to do it all with DT.

Sorry forgot to reply to this.. No seprate board file should be needed,
some devices may still need to be initialized with pdata based on the
compatible flag.
 
> Obviously, I don't expect anybody to run out and buy one of these, take it
> apart, and try to boot this code.  But if the omap guys could take a look at
> this and give me a few pointers, I'd appreciate it.  I'm kind of spinning my
> wheels at the moment.
> 
> Primarily, I'd like to get nand and usb working, so that I can read/write,
> mount a rootfs and do better testing.

The USB should be doable with device tree. At least both echi and
musb are working properly on pandaboard. I think people have been
using NAND with the gpmc DT patches, but I don't know the current
status for sure.

Is the hard drive on the EHCI bus or how is it connected to omap?

Regards,

Tony


From arnd at arndb.de  Wed May  8 15:55:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 May 2013 21:55:22 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <518A96DA.5060809@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <20130508143908.GJ24282@game.jcrosoft.org> <518A96DA.5060809@st.com>
Message-ID: <201305082155.23088.arnd@arndb.de>

On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
> 
> On 08/05/13 15:39, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> +
> >> > 
> >> > Please remove all forward declarations, by reordering the functions in
> >> > the way they are called.
> >> > 
> > and drop the dummy functions
>
> We can not remove the dummy functions, as the serial-core does not check
> it before using them.

None of them seem performance critical, so it sounds reasonable to change
this in the core so you don't have to provide them. It's up to Greg to decide
whether he'd like that change or not.

	Arnd


From soren.brinkmann at xilinx.com  Wed May  8 16:12:05 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Wed, 8 May 2013 13:12:05 -0700
Subject: [REGRESSION] SLAB allocator (on Zynq)
In-Reply-To: <20130508193906.GC32546@atomide.com>
References: <9d9b2266-e09e-4366-80ef-3df5db775f25@TX2EHSMHS033.ehs.local>
 <20130508193906.GC32546@atomide.com>
Message-ID: <35a77b0e-59cc-4fee-81cf-20c059462d12@DB8EHSMHS016.ehs.local>

On Wed, May 08, 2013 at 12:39:07PM -0700, Tony Lindgren wrote:
> Hi,
> 
> * S?ren Brinkmann <soren.brinkmann at xilinx.com> [130508 12:26]:
> > Hi,
> > 
> > I compiled the latest kernel for Zynq and ran into issues when the SLAB
> > allocator is selected. Booting crashes early with a NULL pointer
> > dereference (boot log attached).
> > Switching to the SLUB allocator resolves the issue (boot log attached).
> 
> There's a fix for this now in lkml thread
> "[GIT PULL] SLAB changes for v3.10":
> 
> http://lkml.org/lkml/2013/5/8/374#
Thanks for the quick response and apologies for not having it found
myself earlier.
With that patch it works again.

	Thanks,
	S?ren




From akpm at linux-foundation.org  Wed May  8 16:50:29 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Wed, 8 May 2013 13:50:29 -0700
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <1367937595-32241-12-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
Message-ID: <20130508135029.ffbeefa6b8154bee31e7bbbe@linux-foundation.org>

On Tue,  7 May 2013 09:39:55 -0500 Robin Holt <holt at sgi.com> wrote:

> Merge together the unicore32, arm, and x86 reboot= command line
> parameter handling.
> 
> ...
>
> +static int __init reboot_setup(char *str)
> +{
> +	for (;;) {
> +		/*
> +		 * Having anything passed on the command line via
> +		 * reboot= will cause us to disable DMI checking
> +		 * below.
> +		 */
> +		reboot_default = 0;
> +
> +		switch (*str) {
> +#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
> +		case 'w':
> +			reboot_mode = REBOOT_WARM;
> +			break;
> +
> +		case 'c':
> +			reboot_mode = REBOOT_COLD;
> +			break;
> +
> +#ifdef CONFIG_SMP
> +		case 's':
> +			if (isdigit(*(str+1))) {
> +				reboot_cpu = (int) (*(str+1) - '0');
> +				if (isdigit(*(str+2)))
> +					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
> +			}

Boy, that's some weird stuff.

What's wrong with doing

			if (isdigit(str[1])) {
				reboot_cpu = str[1] - '0';
				if (isdigit(str[2]))
					reboot_cpu = reboot_cpu * 10 +
							str[2] - '0';
			}

?

But it's still nonsense - we should eliminate its
you-have-less-than-101-CPUs restriction by using, you know, atoi().



From rob at landley.net  Wed May  8 16:58:30 2013
From: rob at landley.net (Rob Landley)
Date: Wed, 08 May 2013 15:58:30 -0500
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <5189BA36.9000105@wwwdotorg.org> (from swarren@wwwdotorg.org on
 Tue May  7 21:36:38 2013)
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <201304300004.20320.arnd@arndb.de> <5182AF83.4080705@wwwdotorg.org>
 <1956593.M6NmITdEKh@avalon>
 <20130507143338.79b3d893fcdc3bd79fbe9a57@linux-foundation.org>
 <5189BA36.9000105@wwwdotorg.org>
Message-ID: <1368046710.18069.217@driftwood>

On 05/07/2013 09:36:38 PM, Stephen Warren wrote:
> On 05/07/2013 03:33 PM, Andrew Morton wrote:
...
> Subject: drivers/video: implement a simple framebuffer driver
> 
> A simple frame-buffer describes a raw memory region that may be  
> rendered
> to, with the assumption that the display hardware has already been set
> up to scan out from that buffer.
> 
> This is useful in cases where a bootloader exists and has set up the
> display hardware, but a Linux driver doesn't yet exist for the display
> hardware.
> 
> Examples use-cases include:

Virtual environments such as QEMU.

Rob

From catalin.marinas at arm.com  Wed May  8 17:13:47 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 8 May 2013 22:13:47 +0100
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130508193130.GA31678@schnuecks.de>
References: <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
 <20130508150800.GI2703@arm.com>
 <20130508184354.GQ18614@n2100.arm.linux.org.uk>
 <20130508193130.GA31678@schnuecks.de>
Message-ID: <20130508211346.GA54480@MacBook-Pro.local>

On Wed, May 08, 2013 at 08:31:30PM +0100, Simon Baatz wrote:
> On Wed, May 08, 2013 at 07:43:54PM +0100, Russell King - ARM Linux wrote:
> > On Wed, May 08, 2013 at 04:08:00PM +0100, Catalin Marinas wrote:
> > > On Sat, May 04, 2013 at 09:21:27AM +0100, Ming Lei wrote:
> > > > On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
> > > > >>
> > > > >> I assume that you inhibited the call to flush_dcache_page() in
> > > > >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
> > > > >> with warnings.
> > > > >
> > > > > I haven't done any stress testing so I don't think I hit this code path,
> > > > > so no warning. But yes, it should have triggered. Anyway, in this case
> > > > > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
> > > > > harmless anyway if we also ignore this bit in __sync_icache_dcache for
> > > > > non-aliasing caches).
> > > > 
> > > > Yes, maybe we can do a little optimization for O_DIRECT since no
> > > > dcache alias and I/D coherency problem in this case on ARMv7, how
> > > > about below change?
> > > > 
> > > > diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> > > > index 1c8f7f5..962a657 100644
> > > > --- a/arch/arm/mm/flush.c
> > > > +++ b/arch/arm/mm/flush.c
> > > > @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
> > > >  	    mapping && !mapping_mapped(mapping))
> > > >  		clear_bit(PG_dcache_clean, &page->flags);
> > > >  	else {
> > > > +		if (!mapping && cache_is_vipt_nonaliasing())
> > > > +			return;
> > > >  		__flush_dcache_page(mapping, page);
> > > >  		if (mapping && cache_is_vivt())
> > > >  			__flush_dcache_aliases(mapping, page);
> > > 
> > > I wonder whether we could move the:
> > > 
> > > 	if (!mapping)
> > > 		return
> > > 
> > > at the top of this function, IOW don't touch any anonymous pages. Would
> > > anything be broken (apart from wrong API use)?
> > 
> > I suspect you may be missing something - and I suggest reading the Sparc
> > version, which is where this PG_arch_1 stuff was first dreamed up (by
> > DaveM).
> > 
> > Are you positive that this path can be eliminated?  Totally sure?  Have
> > you checked the arg/env pages that fs/exec.c and the binfmt's insert into
> > the new process?
> > 
> > The comments against the Sparc version suggest that the "else" clause
> > is necessary ensure that case is adequately covered.
> 
> At least the fs/exec.c and the binfmt stuff use
> flush_kernel_dcache_page() for 5 years or so now (see commit b6a2fe). 
> Which makes sense, since flush_dcache_page() is not supposed to
> handle anon pages anyway.

Indeed, the sparc comment on arg pages no longer applies. It was also
more of an optimisation which I'm not convinced it would have saved
anything on ARM.

-- 
Catalin


From sboyd at codeaurora.org  Wed May  8 17:47:51 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed,  8 May 2013 14:47:51 -0700
Subject: [PATCH] ARM: avoid mis-detecting some V7 cores in the decompressor
Message-ID: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>

From: Brian Swetland <swetland at google.com>

Currently v7 CPUs with an MIDR that has no bits set in the range
[16:12] will be detected as old ARM CPUs with no caches and so
the cache will never be turned on during decompression. ARM's
Cortex chips have an 0xC in the range [16:12] so they never match
this entry, but Qualcomm's Scorpion and Krait processors never
set these bits to anything besides 0 so they always match.

Skip this entry if we've compiled in support for v7 CPUs. This
allows kernel decompression to happen nearly instantly instead of
taking over 20 seconds.

Signed-off-by: Brian Swetland <swetland at google.com>
[sboyd: Clarified and extended commit text]
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/boot/compressed/head.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3..a236190 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -805,6 +805,8 @@ call_cache_fn:	adr	r12, proc_types
 		.align	2
 		.type	proc_types,#object
 proc_types:
+#if !defined(CONFIG_CPU_V7)
+		/* This collides with some V7 IDs, preventing correct detection */
 		.word	0x00000000		@ old ARM ID
 		.word	0x0000f000
 		mov	pc, lr
@@ -813,6 +815,7 @@ proc_types:
  THUMB(		nop				)
 		mov	pc, lr
  THUMB(		nop				)
+#endif
 
 		.word	0x41007000		@ ARM7/710
 		.word	0xfff8fe00
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Wed May  8 17:50:28 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 08 May 2013 14:50:28 -0700
Subject: [PATCH] ARM: avoid mis-detecting some V7 cores in the decompressor
In-Reply-To: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
References: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <518AC8A4.8070701@codeaurora.org>

On 05/08/13 14:47, Stephen Boyd wrote:
> From: Brian Swetland <swetland at google.com>
>
> Currently v7 CPUs with an MIDR that has no bits set in the range
> [16:12] will be detected as old ARM CPUs with no caches and so

I mean [15:12], sorry.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From jason at lakedaemon.net  Wed May  8 17:58:53 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 8 May 2013 17:58:53 -0400
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <20130508195152.GE32546@atomide.com>
References: <cover.1368038129.git.jason@lakedaemon.net>
 <20130508195152.GE32546@atomide.com>
Message-ID: <20130508215853.GD31290@titan.lakedaemon.net>

On Wed, May 08, 2013 at 12:51:53PM -0700, Tony Lindgren wrote:
> * Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> > 
> > Current Problem:
> > 
> > There are several gaps in my understanding of how far along TI's conversion to
> > DT is.  Should I be doing a separate board file for initializing the legacy
> > items?  I was hoping to do it all with DT.
> 
> Sorry forgot to reply to this.. No seprate board file should be needed,
> some devices may still need to be initialized with pdata based on the
> compatible flag.

ti,hwmod, right?

> > Obviously, I don't expect anybody to run out and buy one of these, take it
> > apart, and try to boot this code.  But if the omap guys could take a look at
> > this and give me a few pointers, I'd appreciate it.  I'm kind of spinning my
> > wheels at the moment.
> > 
> > Primarily, I'd like to get nand and usb working, so that I can read/write,
> > mount a rootfs and do better testing.
> 
> The USB should be doable with device tree. At least both echi and
> musb are working properly on pandaboard. I think people have been
> using NAND with the gpmc DT patches, but I don't know the current
> status for sure.

I'll try your suggestion in your other email for ToT and see if I can
get gpmc going.

> Is the hard drive on the EHCI bus or how is it connected to omap?

via ehci.  They brutalized the tps driver to detect if the goflex cable
was attached or not.  Once I get something stable, I'll probably write a
separate driver for that code.  Or, push it out to userspace.

thx,

Jason.


From tony at atomide.com  Wed May  8 18:08:42 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 15:08:42 -0700
Subject: [PATCH] ARM: OMAP4+: omap2plus_defconfig: Enable audio via
 TWL6040 as module
In-Reply-To: <acf32629312b1315da0d04598a757673@mail.kapsi.fi>
References: <1365584880-25810-1-git-send-email-peter.ujfalusi@ti.com>
 <acf32629312b1315da0d04598a757673@mail.kapsi.fi>
Message-ID: <20130508220841.GI32546@atomide.com>

* Jyri Sarha <oku at iki.fi> [130412 05:19]:
> On Wed, 10 Apr 2013 11:08:00 +0200, Peter Ujfalusi <peter.ujfalusi at ti.com>
> wrote:
> > Boards supported upstream all use TWL6040 as audio codec, enable the
> common
> > ASoC machine driver by default for them.
> > 
> > Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Tested-by: Jyri Sarha <jsarha at ti.com>
> 
> Brings a working PCM for TWL6040 trough McPDM legacy port on top of
> 8.3-rc3 for my Blaze and Panda.

Thanks applying into omap-for-v3.10/fixes.

Regards,

Tony

> > ---
> >  arch/arm/configs/omap2plus_defconfig | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm/configs/omap2plus_defconfig
> > b/arch/arm/configs/omap2plus_defconfig
> > index bd07864..eea501c 100644
> > --- a/arch/arm/configs/omap2plus_defconfig
> > +++ b/arch/arm/configs/omap2plus_defconfig
> > @@ -152,6 +152,7 @@ CONFIG_OMAP_WATCHDOG=y
> >  CONFIG_TWL4030_WATCHDOG=y
> >  CONFIG_MFD_TPS65217=y
> >  CONFIG_MFD_TPS65910=y
> > +CONFIG_TWL6040_CORE=y
> >  CONFIG_REGULATOR_TWL4030=y
> >  CONFIG_REGULATOR_TPS65023=y
> >  CONFIG_REGULATOR_TPS6507X=y
> > @@ -194,6 +195,7 @@ CONFIG_SND_USB_AUDIO=m
> >  CONFIG_SND_SOC=m
> >  CONFIG_SND_OMAP_SOC=m
> >  CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
> > +CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
> >  CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
> >  CONFIG_USB=y
> >  CONFIG_USB_DEBUG=y


From tony at atomide.com  Wed May  8 18:12:22 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 15:12:22 -0700
Subject: [PATCH] ARM: OMAP3: Beagle: Fix USB Host on beagle xM Ax/Bx
In-Reply-To: <1366024808-4691-1-git-send-email-rogerq@ti.com>
References: <1366024808-4691-1-git-send-email-rogerq@ti.com>
Message-ID: <20130508221221.GJ32546@atomide.com>

* Roger Quadros <rogerq at ti.com> [130415 04:25]:
> On Beagle xM Rev. Ax/Bx, the USB power enable GPIO logic is
> reversed when compared to other revisions i.e. it is
> active high instead of active low.
> 
> Use the beagle_config.usb_pwr_level flag correctly so that
> the power regulator can be configured at runtime.
> 
> Signed-off-by: Roger Quadros <rogerq at ti.com>

Thanks applying into omap-for-v3.10/fixes.

Regards,

Tony

> ---
>  arch/arm/mach-omap2/board-omap3beagle.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
> index 5382215..21136b2 100644
> --- a/arch/arm/mach-omap2/board-omap3beagle.c
> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> @@ -112,13 +112,13 @@ static u8 omap3_beagle_version;
>   */
>  static struct {
>  	int mmc1_gpio_wp;
> -	int usb_pwr_level;
> +	bool usb_pwr_level;	/* 0 - Active Low, 1 - Active High */
>  	int dvi_pd_gpio;
>  	int usr_button_gpio;
>  	int mmc_caps;
>  } beagle_config = {
>  	.mmc1_gpio_wp = -EINVAL,
> -	.usb_pwr_level = GPIOF_OUT_INIT_LOW,
> +	.usb_pwr_level = 0,
>  	.dvi_pd_gpio = -EINVAL,
>  	.usr_button_gpio = 4,
>  	.mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
> @@ -178,7 +178,7 @@ static void __init omap3_beagle_init_rev(void)
>  	case 0:
>  		printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
>  		omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
> -		beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH;
> +		beagle_config.usb_pwr_level = 1;
>  		beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
>  		break;
>  	case 2:
> -- 
> 1.7.4.1
> 


From tony at atomide.com  Wed May  8 18:17:20 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 15:17:20 -0700
Subject: Latest build results - errors/warnings - lots of them
In-Reply-To: <20130506124011.7e4c2806@notabene.brown>
References: <20130430081739.GP14496@n2100.arm.linux.org.uk>
 <20130502082218.GA21614@n2100.arm.linux.org.uk>
 <20130502153834.GR28721@atomide.com>
 <20130506124011.7e4c2806@notabene.brown>
Message-ID: <20130508221720.GK32546@atomide.com>

* NeilBrown <neilb at suse.de> [130505 19:45]:
> On Thu, 2 May 2013 08:38:34 -0700 Tony Lindgren <tony at atomide.com> wrote:
> 
> > > drivers/power/twl4030_charger.c: In function 'twl4030_charger_enable_usb':
> > > drivers/power/twl4030_charger.c:192:20: warning: ignoring return value of 'regulator_enable', declared with attribute warn_unused_result
> > 
> > Neil, care to provide a fix for this? It's from your commit ab37813
> > (twl4030_charger: Allow charger to control the regulator that feeds it).
> > 
> >
> This the sort of thing that might be appropriate?

Thanks looks good to me. Care to send it to the appropriate
mailing lists and maintainers for drivers/power?

Regards,

Tony
 
> From: NeilBrown <neilb at suse.de>
> Date: Mon, 6 May 2013 12:35:59 +1000
> Subject: [PATCH] twl4030_charger: don't ignore regulator_enable()
> 
> regulator_enable() doesn't like being ignored.  If it does fail there
> is nothing we can do except not set usb_enabled (which is necessary
> else a subsequent regulator_disable() will be unbalanced).
> 
> We cannot usefully return an error here as errors from
> twl4030_charger_enable_usb() are ignored.
> 
> Signed-off-by: NeilBrown <neilb at suse.de>
> 
> diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c
> index bed4581..8b0ec70 100644
> --- a/drivers/power/twl4030_charger.c
> +++ b/drivers/power/twl4030_charger.c
> @@ -189,8 +189,8 @@ static int twl4030_charger_enable_usb(struct twl4030_bci *bci, bool enable)
>  
>  		/* Need to keep regulator on */
>  		if (!bci->usb_enabled) {
> -			regulator_enable(bci->usb_reg);
> -			bci->usb_enabled = 1;
> +			if (regulator_enable(bci->usb_reg) == 0)
> +				bci->usb_enabled = 1;
>  		}
>  
>  		/* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */




From tony at atomide.com  Wed May  8 18:23:21 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 15:23:21 -0700
Subject: [PATCH] ARM: OMAP: RX-51: change probe order of touchscreen
 and panel SPI devices
In-Reply-To: <1367427597-30060-1-git-send-email-aaro.koskinen@iki.fi>
References: <1367427597-30060-1-git-send-email-aaro.koskinen@iki.fi>
Message-ID: <20130508222320.GL32546@atomide.com>

* Aaro Koskinen <aaro.koskinen at iki.fi> [130501 10:06]:
> Commit 9fdca9df (spi: omap2-mcspi: convert to module_platform_driver)
> broke the SPI display/panel driver probe on RX-51/N900. The exact cause is
> not fully understood, but it seems to be related to the probe order. SPI
> communication to the panel driver (spi1.2) fails unless the touchscreen
> (spi1.0) has been probed/initialized before. When the omap2-mcspi driver
> was converted to a platform driver, it resulted in that the devices are
> probed immediately after the board registers them in the order they are
> listed in the board file.
> 
> Fix the issue by moving the touchscreen before the panel in the SPI
> device list.
> 
> The patch fixes the following failure:
> 
> [    1.260955] acx565akm spi1.2: invalid display ID
> [    1.265899] panel-acx565akm display0: acx_panel_probe panel detect error
> [    1.273071] omapdss CORE error: driver probe failed: -19

Thanks for updating the description, applying into omap-for-v3.10/fixes.

Regards,

Tony


From andre.przywara at linaro.org  Wed May  8 18:28:06 2013
From: andre.przywara at linaro.org (Andre Przywara)
Date: Thu,  9 May 2013 00:28:06 +0200
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM VCPU
 ioctl
Message-ID: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>

Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
with the KVM_ARM_VCPU_INIT ioctl before being used with further
requests. KVM_RUN checks whether this initialization has been
done, but other ioctls do not.
Namely KVM_GET_REG_LIST will dereference an array with index -1
without initialization and thus leads to a kernel oops.
Fix this by adding checks before executing the ioctl handlers.

Changes from v1:
 * moved check into a static function with a meaningful name

Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
---
 arch/arm/kvm/arm.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index c1fe498..b73b587 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -676,6 +676,15 @@ static void vcpu_pause(struct kvm_vcpu *vcpu)
 	wait_event_interruptible(*wq, !vcpu->arch.pause);
 }
 
+/*
+ * Some ioctls require initialization by KVM_ARM_VCPU_INIT first, check
+ * this with this function
+ */
+static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
+{
+	return vcpu->arch.target >= 0;
+}
+
 /**
  * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
  * @vcpu:	The VCPU pointer
@@ -692,8 +701,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	int ret;
 	sigset_t sigsaved;
 
-	/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
-	if (unlikely(vcpu->arch.target < 0))
+	if (unlikely(!kvm_vcpu_initialized(vcpu)))
 		return -ENOEXEC;
 
 	ret = kvm_vcpu_first_run_init(vcpu);
@@ -893,6 +901,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 	case KVM_SET_ONE_REG:
 	case KVM_GET_ONE_REG: {
 		struct kvm_one_reg reg;
+
+		if (unlikely(!kvm_vcpu_initialized(vcpu)))
+			return -ENOEXEC;
+
 		if (copy_from_user(&reg, argp, sizeof(reg)))
 			return -EFAULT;
 		if (ioctl == KVM_SET_ONE_REG)
@@ -905,6 +917,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 		struct kvm_reg_list reg_list;
 		unsigned n;
 
+		if (unlikely(!kvm_vcpu_initialized(vcpu)))
+			return -ENOEXEC;
+
 		if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 			return -EFAULT;
 		n = reg_list.n;
-- 
1.7.12.1



From cdall at cs.columbia.edu  Wed May  8 18:29:49 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Wed, 8 May 2013 15:29:49 -0700
Subject: Problems while booting a linux system on fast models based
 CortexA15
In-Reply-To: <CAJ30i6HzvaKrKha7aVcR50=-5zmgivY-82J6NTqFw7Fh+sNzfQ@mail.gmail.com>
References: <CAJ30i6HzvaKrKha7aVcR50=-5zmgivY-82J6NTqFw7Fh+sNzfQ@mail.gmail.com>
Message-ID: <CAEDV+gLekd9PrX=YqFpKQyLxFHDuAV8F5NvaMkRKZQvR3q_yNg@mail.gmail.com>

On Wed, May 8, 2013 at 12:07 AM, Mai Daftedar <mai.daftedar at gmail.com> wrote:
> Dear All,
>  I am facing a problem with booting a fully working Linux system on the Fast
> Models based Cortex-A15 simulation platform.
>
> I'm using the "KVM on ARM guide" to configure KVM on the ARM fast models
> with CortexA15, however I get the following kernel panic error  when I use
> NFS to boot the kernel.
>
> VFS: Unable to mount root fs via NFS, trying floppy.
>
> Noting that the kernel semi-hosting arguments used are as follows:
> kernel uImage --fdt host-a15.dtb -- earlyprintk console=ttyAMA0 mem=2048M
> root=/dev/nfs nfsroot=192.168.x.x:/srv/nfsroot/ rw ip=dhcp
>
> Where can I be going wrong?
>
Is that literally the command line you use?

You may want to change those x's then to the actual IP address of your
host machine :)

You also need to make sure that your host machine has NFS configured properly.

-Christoffer


From tony at atomide.com  Wed May  8 18:30:27 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 15:30:27 -0700
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <20130508215853.GD31290@titan.lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
 <20130508195152.GE32546@atomide.com>
 <20130508215853.GD31290@titan.lakedaemon.net>
Message-ID: <20130508223027.GN32546@atomide.com>

* Jason Cooper <jason at lakedaemon.net> [130508 15:04]:
> On Wed, May 08, 2013 at 12:51:53PM -0700, Tony Lindgren wrote:
> > * Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> > > 
> > > Current Problem:
> > > 
> > > There are several gaps in my understanding of how far along TI's conversion to
> > > DT is.  Should I be doing a separate board file for initializing the legacy
> > > items?  I was hoping to do it all with DT.
> > 
> > Sorry forgot to reply to this.. No seprate board file should be needed,
> > some devices may still need to be initialized with pdata based on the
> > compatible flag.
> 
> ti,hwmod, right?

Yes.. see mach-omap2/devices.c for the list that's still not initialized
via DT.
 
> > > Obviously, I don't expect anybody to run out and buy one of these, take it
> > > apart, and try to boot this code.  But if the omap guys could take a look at
> > > this and give me a few pointers, I'd appreciate it.  I'm kind of spinning my
> > > wheels at the moment.
> > > 
> > > Primarily, I'd like to get nand and usb working, so that I can read/write,
> > > mount a rootfs and do better testing.
> > 
> > The USB should be doable with device tree. At least both echi and
> > musb are working properly on pandaboard. I think people have been
> > using NAND with the gpmc DT patches, but I don't know the current
> > status for sure.
> 
> I'll try your suggestion in your other email for ToT and see if I can
> get gpmc going.
> 
> > Is the hard drive on the EHCI bus or how is it connected to omap?
> 
> via ehci.  They brutalized the tps driver to detect if the goflex cable
> was attached or not.  Once I get something stable, I'll probably write a
> separate driver for that code.  Or, push it out to userspace.

OK. I guess you need to disconnect the drive from EHCI if the goflex
is attached to avoid disk corruption?

Regards,

Tony


From swarren at wwwdotorg.org  Wed May  8 18:42:04 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 May 2013 16:42:04 -0600
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
Message-ID: <518AD4BC.6090009@wwwdotorg.org>

On 05/07/2013 08:54 PM, Peter Chen wrote:
>>
>> This probably could be initialized from some DT property. However,
>> there's no such property defined right now, and considering that DT is
>> supposed to be an ABI, we'd always need the code in this patch as a
>> fallback for DTs that were created before any such property was defined.
>>
>> Equally, since the data is SoC-specific rather than board-specific, and
>> is even fairly unlikely to vary between SoC versions since these values
>> are all 0xffffffff anyway, I don't really see much point in putting it
>> into DT, rather than just putting the static data into the driver.
> 
> I mean there is already dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
> at function of_platform_device_create, why can't add
> dev->dev.dma_mask = &dev->dev.coherent_dma_mask after that?
> 
> If DT core can do above things, can we delete dma_mask assignment
> at every driver?

Perhaps. However, such a change has a much larger potential for regressions.

I would suggest going with the current patch for 3.10 and any later
backports in order to reduce risk. We can revisit better cleanup for
later kernels.


From tony at atomide.com  Wed May  8 19:10:34 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:10:34 -0700
Subject: [PATCH] ARM: OMAP1: DMA: fix error handling in
 omap1_system_dma_init()
In-Reply-To: <CAPgLHd-5cRFtN-rF8c5Jvg9cqE3jvxuOa6KaDgcoYHPM4DhbMQ@mail.gmail.com>
References: <CAPgLHd-5cRFtN-rF8c5Jvg9cqE3jvxuOa6KaDgcoYHPM4DhbMQ@mail.gmail.com>
Message-ID: <20130508231034.GP32546@atomide.com>

* Wei Yongjun <weiyj.lk at gmail.com> [130426 01:36]:
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> 
> Add the missing iounmap() before return from omap1_system_dma_init()
> in the error handling case.
> Also removed platform_device_del() on add resources error case which
> cause dup device delete.
> 
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> ---
> no compile test.

Seems to work, applying into omap-for-v3.10/fixes thanks.

Tony

>  arch/arm/mach-omap1/dma.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 1a4e887..68ab858 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -301,7 +301,7 @@ static int __init omap1_system_dma_init(void)
>  	if (ret) {
>  		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
>  			__func__, pdev->name, pdev->id);
> -		goto exit_device_put;
> +		goto exit_iounmap;
>  	}
>  
>  	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
> @@ -309,7 +309,7 @@ static int __init omap1_system_dma_init(void)
>  		dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
>  			__func__, pdev->name);
>  		ret = -ENOMEM;
> -		goto exit_device_del;
> +		goto exit_iounmap;
>  	}
>  
>  	d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
> @@ -402,8 +402,8 @@ exit_release_d:
>  	kfree(d);
>  exit_release_p:
>  	kfree(p);
> -exit_device_del:
> -	platform_device_del(pdev);
> +exit_iounmap:
> +	iounmap(dma_base);
>  exit_device_put:
>  	platform_device_put(pdev);
>  
> 


From tony at atomide.com  Wed May  8 19:14:46 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:14:46 -0700
Subject: [PATCH 0/2] ARM: dts: OMAP36xx/OMAP4460 Fix CPU OPP voltages
In-Reply-To: <1366997973-19120-1-git-send-email-nm@ti.com>
References: <1366997973-19120-1-git-send-email-nm@ti.com>
Message-ID: <20130508231445.GQ32546@atomide.com>

* Nishanth Menon <nm at ti.com> [130426 10:44]:
> Hi,
> It seems that I have not been paying close attention to
> actual voltage value seen on scope to map it back to verify the validity
> of the voltage value. Even though I did verify[1] that voltage did scale to
> values in DT entries, the values in the case of 3630 and 4460 were lower than
> what the spec voltage was as per opp_data files.
> 
> This series is based off Benoit's tree here:
> http://git.kernel.org/cgit/linux/kernel/git/bcousson/linux-omap-dt.git/log/?h=for_3.10/dts
> 
> Commit ID's in the patches to indicate regressions are from there as well.
> Would be good to have this fix merged to 3.10 dts entries.
> I have cross verified that OMAP3430,3630,4430 and 4460 entries now match that
> of corresponding opp*_data.c
> 
> My sincere apologies on the oversight.
> 
> Nishanth Menon (2):
>   ARM: dts: OMAP36xx: Fix CPU OPP voltages
>   ARM: dts: OMAP4460: Fix CPU OPP voltages
> 
>  arch/arm/boot/dts/omap36xx.dtsi |    6 +++---
>  arch/arm/boot/dts/omap4460.dtsi |    6 +++---
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> [1] http://marc.info/?l=linux-arm-kernel&m=136580742724210&w=2

Thanks applying both into omap-for-v3.10/dt-fixes.

Regards,

Tony


From tony at atomide.com  Wed May  8 19:17:36 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:17:36 -0700
Subject: [PATCH] ARM: OMAP2+: omap_device: use late_initcall_sync
In-Reply-To: <1367962765-13912-1-git-send-email-khilman@linaro.org>
References: <1367962765-13912-1-git-send-email-khilman@linaro.org>
Message-ID: <20130508231736.GR32546@atomide.com>

* Kevin Hilman <khilman at linaro.org> [130507 14:44]:
> If DEBUG_LL and earlyprintk are enabled, and omap-serial.c is compiled
> as a module, the kernel boot hangs early as the clocks for serial port
> are cut while earlyprintk still uses the port.
> 
> The problem is a race between the late_initcall for omap_device (which
> idles devices that have no drivers) and the late_initcall in
> kernel/printk.c which turns off the earlyconsole.   Any printks
> that happen between this omap_device late initcall and the earlyconsole
> late initcall will crash when accessing the UART.
> 
> The fix is to ensure the omap_device initcall happens after the
> earlyconsole initcall.
> 
> Reported-by: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Kevin Hilman <khilman at linaro.org>

Thanks applying into omap-for-v3.10/fixes.

Tony

> ---
> Based on v3.9-rc8
> 
>  arch/arm/mach-omap2/omap_device.c | 2 +-
>  arch/arm/mach-omap2/soc.h         | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
> index 381be7a..2d20d69 100644
> --- a/arch/arm/mach-omap2/omap_device.c
> +++ b/arch/arm/mach-omap2/omap_device.c
> @@ -879,4 +879,4 @@ static int __init omap_device_late_init(void)
>  	bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
>  	return 0;
>  }
> -omap_late_initcall(omap_device_late_init);
> +omap_late_initcall_sync(omap_device_late_init);
> diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
> index c62116b..de88611 100644
> --- a/arch/arm/mach-omap2/soc.h
> +++ b/arch/arm/mach-omap2/soc.h
> @@ -494,6 +494,7 @@ level(__##fn);
>  #define omap_subsys_initcall(fn)	omap_initcall(subsys_initcall, fn)
>  #define omap_device_initcall(fn)	omap_initcall(device_initcall, fn)
>  #define omap_late_initcall(fn)		omap_initcall(late_initcall, fn)
> +#define omap_late_initcall_sync(fn)	omap_initcall(late_initcall_sync, fn)
>  
>  #endif	/* __ASSEMBLY__ */
>  
> -- 
> 1.8.2
> 


From sergei.shtylyov at cogentembedded.com  Wed May  8 19:32:59 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 9 May 2013 03:32:59 +0400
Subject: [PATCH v7 0/3] Add USB support to R8A7778/BOCK-W
Message-ID: <201305090333.00333.sergei.shtylyov@cogentembedded.com>

Hello.

   Here's the set of 3 patches against the Simon Horman's 'renesas.git' repo,
'renesas-next-20130426' tag, the R8A7779/Marzen and sh-pfc patchset I've posted.
It was created to add support of R8A7778/BOCK-W USB to the platform code and
the USB common PHY driver, and so spans both arch/arm/mach-shmobile/ and
drivers/usb/phy/ subtrees.

[1/3] rcar-phy: add R8A7778 support
[2/3] ARM: shmobile: r8a7778: add USB support
[3/3] ARM: shmobile: BOCK-W: add USB support

The patch #4 (ARM: shmobile: BOCK-W: enable USB in defconfig) that has been
already merged, is not reposted.

WBR, Sergei


From tony at atomide.com  Wed May  8 19:33:06 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:33:06 -0700
Subject: [PATCH] ARM: OMAP2: AM33XX: id: Add support for new AM335x
 PG2.1 Si
In-Reply-To: <1367691820-11875-1-git-send-email-hvaibhav@ti.com>
References: <1367691820-11875-1-git-send-email-hvaibhav@ti.com>
Message-ID: <20130508233306.GU32546@atomide.com>

* Vaibhav Hiremath <hvaibhav at ti.com> [130504 11:29]:
> Add support for chip id detection of AM335x PG2.1 Silicon.
> 
> Currently omap3xxx_check_revision() detects PG1.0 and PG2.0 only,
> this patch extends it by adding PG2.1 Si support.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>

Thanks applying into omap-for-v3.10/fixes.

Tony

> ---
>  arch/arm/mach-omap2/id.c  |    8 ++++++--
>  arch/arm/mach-omap2/soc.h |    1 +
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 0f4c18e..9bc5a18 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -419,11 +419,15 @@ void __init omap3xxx_check_revision(void)
>  			cpu_rev = "1.0";
>  			break;
>  		case 1:
> -		/* FALLTHROUGH */
> -		default:
>  			omap_revision = AM335X_REV_ES2_0;
>  			cpu_rev = "2.0";
>  			break;
> +		case 2:
> +		/* FALLTHROUGH */
> +		default:
> +			omap_revision = AM335X_REV_ES2_1;
> +			cpu_rev = "2.1";
> +			break;
>  		}
>  		break;
>  	case 0xb8f2:
> diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
> index 18fdeeb..ccef2dd 100644
> --- a/arch/arm/mach-omap2/soc.h
> +++ b/arch/arm/mach-omap2/soc.h
> @@ -396,6 +396,7 @@ IS_OMAP_TYPE(3430, 0x3430)
>  #define AM335X_CLASS		0x33500033
>  #define AM335X_REV_ES1_0	AM335X_CLASS
>  #define AM335X_REV_ES2_0	(AM335X_CLASS | (0x1 << 8))
> +#define AM335X_REV_ES2_1	(AM335X_CLASS | (0x2 << 8))
> 
>  #define OMAP443X_CLASS		0x44300044
>  #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
> --
> 1.7.0.4
> 


From sboyd at codeaurora.org  Wed May  8 19:36:13 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 08 May 2013 16:36:13 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <518AE16D.5060501@codeaurora.org>

On 04/19/13 09:28, James Hogan wrote:
> This patchset adds support for automatic selection of the best parent
> for a clock mux, i.e. the one which can provide the closest clock rate
> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
> so that it doesn't happen unless explicitly allowed.
>
> This works by way of adding a new op, determine_rate, similar to
> round_rate but with an extra parameter to allow the clock driver to
> optionally select a different parent clock. This is used in
> clk_calc_new_rates to decide whether to initiate a set_parent operation.

Which tree is this based on? I get failures with git am on patch 2.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From sergei.shtylyov at cogentembedded.com  Wed May  8 19:37:45 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 9 May 2013 03:37:45 +0400
Subject: [PATCH v7 2/3] ARM: shmobile: r8a7778: add USB support
In-Reply-To: <201305090333.00333.sergei.shtylyov@cogentembedded.com>
References: <201305090333.00333.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305090337.45950.sergei.shtylyov@cogentembedded.com>

Add USB clock and EHCI, OHCI, and USB PHY platform devices for R8A7778 SoC;  add
a function to register PHY device with board-specific platform data and register
EHCI and OHCI platfrom devices from the init_late() board method.

Also,  don't forget to enable CONFIG_ARCH_HAS_[EO]HCI options for R8A7778 SoC in
Kconfig...

The patch has been tested on the BOCK-W board.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
Changes since version 5:
- renamed the R-Car PHY driver header file in #include.

Changes since version 4:
- annotated USB resources and '[eo]hci_info' as '__initdata' since they're
  kmemdup()'ed while registering the platform devices anyway;
- refreshed the patch.

Changes since version 3:
- resolved reject in the 'clock-r8a7778.c' file, refreshed the patch.

Changes since version 2:
- refreshed the patch.

Changes since the original posting:
- resolved rejects in the 'clock-r8a7778.c' file;
- lowercased the SoC name in the subject.

 arch/arm/mach-shmobile/Kconfig                |    2 
 arch/arm/mach-shmobile/clock-r8a7778.c        |    4 
 arch/arm/mach-shmobile/include/mach/r8a7778.h |    3 
 arch/arm/mach-shmobile/setup-r8a7778.c        |  108 ++++++++++++++++++++++++++
 4 files changed, 117 insertions(+)

Index: renesas/arch/arm/mach-shmobile/Kconfig
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/Kconfig
+++ renesas/arch/arm/mach-shmobile/Kconfig
@@ -41,6 +41,8 @@ config ARCH_R8A7778
 	select CPU_V7
 	select SH_CLK_CPG
 	select ARM_GIC
+	select USB_ARCH_HAS_EHCI
+	select USB_ARCH_HAS_OHCI
 
 config ARCH_R8A7779
 	bool "R-Car H1 (R8A77790)"
Index: renesas/arch/arm/mach-shmobile/clock-r8a7778.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/clock-r8a7778.c
+++ renesas/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -105,6 +105,7 @@ static struct clk *main_clks[] = {
 enum {
 	MSTP323, MSTP322, MSTP321,
 	MSTP114,
+	MSTP100,
 	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 	MSTP016, MSTP015,
 	MSTP_NR };
@@ -114,6 +115,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+	[MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1,  0, 0), /* USB0/1 */
 	[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
 	[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
 	[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
@@ -130,6 +132,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
 	CLKDEV_DEV_ID("sh-eth",	&mstp_clks[MSTP114]), /* Ether */
+	CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+	CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
Index: renesas/arch/arm/mach-shmobile/include/mach/r8a7778.h
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ renesas/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -20,10 +20,13 @@
 
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 
 extern void r8a7778_add_standard_devices(void);
 extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
Index: renesas/arch/arm/mach-shmobile/setup-r8a7778.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/setup-r8a7778.c
+++ renesas/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -30,6 +30,12 @@
 #include <linux/irqchip.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
+#include <linux/pm_runtime.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/dma-mapping.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <mach/common.h>
@@ -89,6 +95,99 @@ static struct sh_timer_config sh_tmu1_pl
 		&sh_tmu##idx##_platform_data,		\
 		sizeof(sh_tmu##idx##_platform_data))
 
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+	DEFINE_RES_MEM(0xffe70800, 0x100),
+	DEFINE_RES_MEM(0xffe76000, 0x100),
+};
+
+void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+	platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+					  usb_phy_resources,
+					  ARRAY_SIZE(usb_phy_resources),
+					  pdata, sizeof(*pdata));
+}
+
+/* USB */
+static struct usb_phy *phy;
+
+static int usb_power_on(struct platform_device *pdev)
+{
+	if (!phy)
+		return -EIO;
+
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_get_sync(&pdev->dev);
+
+	usb_phy_init(phy);
+
+	return 0;
+}
+
+static void usb_power_off(struct platform_device *pdev)
+{
+	if (!phy)
+		return;
+
+	usb_phy_shutdown(phy);
+
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+}
+
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+	/*
+	 * Below are recommended values from the datasheet;
+	 * see [USB :: Setting of EHCI Internal Buffer].
+	 */
+	/* EHCI IP internal buffer setting */
+	iowrite32(0x00ff0040, hcd->regs + 0x0094);
+	/* EHCI IP internal buffer enable */
+	iowrite32(0x00000001, hcd->regs + 0x009C);
+
+	return 0;
+}
+
+static struct usb_ehci_pdata ehci_pdata __initdata = {
+	.power_on	= usb_power_on,
+	.power_off	= usb_power_off,
+	.power_suspend	= usb_power_off,
+	.pre_setup	= ehci_init_internal_buffer,
+};
+
+static struct resource ehci_resources[] __initdata = {
+	DEFINE_RES_MEM(0xffe70000, 0x400),
+	DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+
+static struct usb_ohci_pdata ohci_pdata __initdata = {
+	.power_on	= usb_power_on,
+	.power_off	= usb_power_off,
+	.power_suspend	= usb_power_off,
+};
+
+static struct resource ohci_resources[] __initdata = {
+	DEFINE_RES_MEM(0xffe70400, 0x400),
+	DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+
+#define USB_PLATFORM_INFO(hci)					\
+static struct platform_device_info hci##_info __initdata = {	\
+	.parent		= &platform_bus,			\
+	.name		= #hci "-platform",			\
+	.id		= -1,					\
+	.res		= hci##_resources,			\
+	.num_res	= ARRAY_SIZE(hci##_resources),		\
+	.data		= &hci##_pdata,				\
+	.size_data	= sizeof(hci##_pdata),			\
+	.dma_mask	= DMA_BIT_MASK(32),			\
+}
+
+USB_PLATFORM_INFO(ehci);
+USB_PLATFORM_INFO(ohci);
+
 /* Ether */
 static struct resource ether_resources[] = {
 	DEFINE_RES_MEM(0xfde00000, 0x400),
@@ -197,6 +296,14 @@ void __init r8a7778_add_standard_devices
 	r8a7778_register_tmu(1);
 }
 
+void __init r8a7778_init_late(void)
+{
+	phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+	platform_device_register_full(&ehci_info);
+	platform_device_register_full(&ohci_info);
+}
+
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
 	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 	.sense_bitfield_width = 2,
@@ -310,6 +417,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8
 	.init_machine	= r8a7778_add_standard_devices_dt,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= r8a7778_compat_dt,
+	.init_late      = r8a7778_init_late,
 MACHINE_END
 
 #endif /* CONFIG_USE_OF */


From sergei.shtylyov at cogentembedded.com  Wed May  8 19:39:09 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 9 May 2013 03:39:09 +0400
Subject: [PATCH v7 3/3] ARM: shmobile: BOCK-W: add USB support
In-Reply-To: <201305090333.00333.sergei.shtylyov@cogentembedded.com>
References: <201305090333.00333.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305090339.10053.sergei.shtylyov@cogentembedded.com>

Register the USB PHY device from bockw_init(), passing the platform  data to it.
Set machine's init_late() method to r8a7778_init_late() in order for [EO]HCI to
get registered too...

Don't forget to add USB PENC0/1 pins to bockw_pinctrl_map[].

The patch has been tested on the BOCK-W board.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
Changes since version 6:
- added USB PENC0/1 pins to bockw_pinctrl_map[].

Changes since version 4:
- annotated 'usb_phy_platform_data' as '__initdata' since it's kmemdup()'ed
  while registering the platform device anyway;
- refreshed the patch.

Changes since version 3:
- removed initializer for 'usb_phy_platform_data' letting it be set to all 0s;
- refreshed the patch.

Changes since version 2:
- refreshed the patch.

Changes since the original posting:
- removed initializer for no longer existing field in 'usb_phy_platform_data',
  modified the comment to the 'ferrite_bead' field initializer.

 arch/arm/mach-shmobile/board-bockw.c |    8 ++++++++
 1 file changed, 8 insertions(+)

Index: renesas/arch/arm/mach-shmobile/board-bockw.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/board-bockw.c
+++ renesas/arch/arm/mach-shmobile/board-bockw.c
@@ -63,6 +63,8 @@ static struct sh_mobile_sdhi_info sdhi0_
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT,
 };
 
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
+
 static const struct pinctrl_map bockw_pinctrl_map[] = {
 	/* SCIF0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
@@ -78,6 +80,10 @@ static const struct pinctrl_map bockw_pi
 				  "sdhi0_data4", "sdhi0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 				  "sdhi0_wp", "sdhi0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+				  "usb0", "usb0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+				  "usb1", "usb1"),
 };
 
 #define FPGA	0x18200000
@@ -91,6 +97,7 @@ static void __init bockw_init(void)
 	r8a7778_clock_init();
 	r8a7778_init_irq_extpin(1);
 	r8a7778_add_standard_devices();
+	r8a7778_add_usb_phy_device(&usb_phy_platform_data);
 
 	pinctrl_register_mappings(bockw_pinctrl_map,
 				  ARRAY_SIZE(bockw_pinctrl_map));
@@ -146,4 +153,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw")
 	.init_machine	= bockw_init,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= bockw_boards_compat_dt,
+	.init_late      = r8a7778_init_late,
 MACHINE_END


From tony at atomide.com  Wed May  8 19:47:46 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:47:46 -0700
Subject: [PATCHv2] ARM:dts:omap4-panda:Update the LED support for the
 panda DTS
In-Reply-To: <51703BEF.6050804@ti.com>
References: <1366229760-4808-1-git-send-email-dmurphy@ti.com>
 <516FBD18.3060501@ti.com> <51703BEF.6050804@ti.com>
Message-ID: <20130508234745.GV32546@atomide.com>

* Dan Murphy <dmurphy at ti.com> [130418 11:35]:
> On 04/18/2013 04:30 AM, Vincent Stehl? wrote:
> >On 04/17/2013 10:16 PM, Dan Murphy wrote:
> >>The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> >>are different.
> >(..)
> >>diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> >>index 03bd60d..0c48f6b 100644
> >>--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> >>+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> >(..)
> >>@@ -135,6 +136,25 @@
> >>  			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
> >>  		>;
> >>  	};
> >>+
> >>+	led_gpio_pins: pinmux_leds_pins {
> >>+		pinctrl-single,pins = <
> >>+		>;
> >>+	};
> >>+};
> >Hi,
> >
> >FYI, there was a recent discussion precisely on this topic, where Tomy
> >suggested to remove the empty section:
> >http://marc.info/?l=linux-omap&m=136546635409232&w=2
> >
> >Apart from that, I just tested your patch on top of Tomy's
> >omap-for-v3.10/dt branch and it is working fine for me on PandaBoards
> >EA3, A4 and ES.
> >
> >Tested-by: Vincent Stehl? <v-stehle at ti.com>
> >
> >Best regards,
> >
> >V.
> >
> Thanks for testing Vincent
> 
> Is there a way to append the data to an already existing node?
> I do not see a clean way.

If you have something in omap4-panda-common.dtsi and the same entry
in the omap4-panda-es.dts, the entries in omap4-panda-es.dts will
override and append the entries in omap4-panda-common.dtsi.

So I think you can avoid the empty entry that way.

Regards,

Tony


From tony at atomide.com  Wed May  8 19:52:32 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:52:32 -0700
Subject: [PATCH] ARM: OMAP2+: omap-usb-host: clean up pin mux setup code
In-Reply-To: <1366624673-2684-1-git-send-email-rogerq@ti.com>
References: <1366624673-2684-1-git-send-email-rogerq@ti.com>
Message-ID: <20130508235232.GW32546@atomide.com>

* Roger Quadros <rogerq at ti.com> [130422 03:02]:
> The USB host pins are named quite differently between OMAP3 and
> OMAP4+ SoCs. To make this managable in code, we create a pin mapping
> table (pin_names) that maps pin function to pin name.
> 
> This pin mapping table is populated at runtime based on a pin
> name template. Templates are provided for OMAP3 and 4 SoCs.
> 
> The setup_io_mux() function uses the pin mapping table to
> setup the pin mux.
> 
> The resulting code is a lot more clean, manageable and scalable.

I'm planning to drop all the omap4 pdata soonish. Will post some
patches after -rc1 to do that. Do you still need this patch
considering that?

Regards,

Tony


From tony at atomide.com  Wed May  8 19:54:06 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 16:54:06 -0700
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <517F5126.5000509@ti.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com>
Message-ID: <20130508235404.GX32546@atomide.com>

* Sekhar Nori <nsekhar at ti.com> [130429 22:11]:
> 
> On 4/29/2013 1:25 PM, Gupta, Pekon wrote:
> > From: avinash philip <avinashphilip at ti.com>
> > 
> > NAND flash connected in am335x-evm on GPMC controller. This patch adds
> > device tree node in am3355-evm with GPMC contoller timing for NAND flash
> > interface, NAND partition table, ECC scheme, elm handle id.
> > 
> > Signed-off-by: Philip Avinash <avinashphilip at ti.com>
> > Tested-by: Pekon Gupta <pekon at ti.com>
> > 
> > ---
> > arch/arm/boot/dts/am335x-evm.dts |   98 +++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 97 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
> > index 0423298..1c2fd89 100644
> > --- a/arch/arm/boot/dts/am335x-evm.dts
> > +++ b/arch/arm/boot/dts/am335x-evm.dts
> > @@ -26,7 +26,8 @@
> >  
> >  	am33xx_pinmux: pinmux at 44e10800 {
> >  		pinctrl-names = "default";
> > -		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
> > +		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
> > +			&nandflash_pins_s0>;
> 
> Why add this to the board level fallback (called pinctrl hogs, I think)?
> This can be part of nand node you added below so that the pinctrl will
> take effect when nand gets probed instead of all the time.

Yes we should have all the pinctrl entries under the related drivers.
This makes it easy remux pins during runtime if needed, and also
allows unloading pinctrl-single.ko for development.

Regards,

Tony


From sergei.shtylyov at cogentembedded.com  Wed May  8 20:05:40 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 9 May 2013 04:05:40 +0400
Subject: [PATCH] ARM: shmobile: r8a7778: correct model name in Kconfig
Message-ID: <201305090405.41053.sergei.shtylyov@cogentembedded.com>

The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
M1S which is a SH based SoC.  

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
The patch is against the current Linus' tree.

 arch/arm/mach-shmobile/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: linux/arch/arm/mach-shmobile/Kconfig
===================================================================
--- linux.orig/arch/arm/mach-shmobile/Kconfig
+++ linux/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,7 @@ config ARCH_R8A7740
 	select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-	bool "R-Car M1 (R8A77780)"
+	bool "R-Car M1A (R8A77781)"
 	select CPU_V7
 	select SH_CLK_CPG
 	select ARM_GIC


From tony at atomide.com  Wed May  8 20:13:28 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 17:13:28 -0700
Subject: [GIT PULL] ARM: OMAP2+: GPMC fixes for v3.10
In-Reply-To: <517FCCF0.1030105@ti.com>
References: <517FCCF0.1030105@ti.com>
Message-ID: <20130509001328.GY32546@atomide.com>

* Jon Hunter <jon-hunter at ti.com> [130430 06:59]:
> The following changes since commit aecb65a34a780cd07fbaa652cc5d640f13f3ed5f:
> 
>   Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux into omap-for-v3.10/gpmc (2013-04-04 11:22:33 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/jonhunter/linux.git omap-gpmc-fixes-for-v3.10
> 
> for you to fetch changes up to b327b3627bb428eb7d98f25224532425a673d89e:
> 
>   ARM: OMAP2+: only WARN if a GPMC child probe function fail (2013-04-30 08:43:05 -0500)
> 
> ----------------------------------------------------------------
> GPMC fixes for v3.10. Main fix is to only search the GPMC node
> for GPMC child devices and not the entire device-tree (which was
> breaking ethernet support on some boards where the GPMC does not
> interface with the ethernet chip). This branch is based upon
> Tony's omap-for-v3.10/gpmc branch.

Thanks pulling into omap-for-v3.10/fixes.

Regards,

Tony

> ----------------------------------------------------------------
> Javier Martinez Canillas (3):
>       Documentation: dt: update TI GPMC ethernet binding properties
>       ARM: OMAP2+: only search for GPMC DT child nodes on probe
>       ARM: OMAP2+: only WARN if a GPMC child probe function fail
> 
> Jon Hunter (1):
>       Documentation: dt: update properties in TI GPMC NAND example
> 
>  .../devicetree/bindings/mtd/gpmc-nand.txt          |   28 +++++-----
>  Documentation/devicetree/bindings/net/gpmc-eth.txt |   56 ++++++++++----------
>  arch/arm/mach-omap2/gpmc.c                         |   38 +++++--------
>  3 files changed, 54 insertions(+), 68 deletions(-)


From tony at atomide.com  Wed May  8 20:16:07 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 May 2013 17:16:07 -0700
Subject: [PATCH v3,2/3] ARM: dts: AM33XX: Add GPMC node
In-Reply-To: <2645efefa3d36388ff1d4b64255d880b6587770f.1359007746.git.avinashphilip@ti.com>
References: <2645efefa3d36388ff1d4b64255d880b6587770f.1359007746.git.avinashphilip@ti.com>
Message-ID: <20130509001606.GZ32546@atomide.com>

* Gupta, Pekon <pekon at ti.com> [130502 02:49]:
> From: "Philip, Avinash" <avinashphilip at ti.com>
> 
> Add GPMC data node to AM33XX device tree file.
> 
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>
> Acked-by: Peter Korsgaard <jacmet at sunsite.dk>
> Signed-off-by: Pekon Gupta <pekon at ti.com>

Thanks adding into omap-for-v3.10/dt-fixes.

Tony
 
> ---
> Changes in v2:
> 	- Change number of chip select to 7
> 
>  arch/arm/boot/dts/am33xx.dtsi |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index 24fc835..1048795 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -407,5 +407,17 @@
>  			ti,hwmods = "elm";
>  			status = "disabled";
>  		};
> +
> +		gpmc: gpmc at 50000000 {
> +			compatible = "ti,am3352-gpmc";
> +			ti,hwmods = "gpmc";
> +			reg = <0x50000000 0x2000>;
> +			interrupts = <100>;
> +			num-cs = <7>;
> +			num-waitpins = <2>;
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			status = "disabled";
> +		};
>  	};
>  };


From jason at lakedaemon.net  Wed May  8 20:36:06 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 8 May 2013 20:36:06 -0400
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <20130508194504.GD32546@atomide.com>
References: <cover.1368038129.git.jason@lakedaemon.net>
 <20130508194504.GD32546@atomide.com>
Message-ID: <20130509003606.GE31290@titan.lakedaemon.net>

On Wed, May 08, 2013 at 12:45:04PM -0700, Tony Lindgren wrote:
> * Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> > 
> > Tony has been helping me out offline with this, and he suggested trying the
> > gpmc against Linus' ToT.  Which locks up before it even has a chance to get
> > going.  So this series is against v3.9.
> 
> You may have better luck with today's mainline treeand the following fix:
> 
> http://lkml.org/lkml/2013/5/8/374#

Ok, I'm attempting to do that, but got this for 'make dtbs':

ERROR (phandle_references): Reference to non-existent node or label "usb2_phy"

ERROR: Input tree has errors, aborting (use -f to force output)
make[1]: *** [arch/arm/boot/dts/omap3-wireless_plus.dtb] Error 2
make[1]: *** Waiting for unfinished jobs....
make: *** [dtbs] Error 2

which was created by:

  ad871c10 ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards

It assumes the board has twl4030 (and then includes it).  Bootlogs from
the vendor provided kernel don't show a single message from twl4030, so
I've omitted it.

Assuming I did the correct thing by omitting the twl4030, I think the
correct answer is to declare the phy in the dts files, like so:

---->8-----

commit c369d84600bd85b35d83807ce7ba893cea116fb4
Author: Jason Cooper <jason at lakedaemon.net>
Date:   Thu May 9 00:33:48 2013 +0000

    ARM: omap3: dts: don't assume boards are using twl4030
    
    If a board isn't using twl4030, then dtc will complain about the missing
    phandle (which is in twl4030.dtsi).  Move the phy declaration to the dts
    files.
    
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 5a31964..3046d1f 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -122,6 +122,7 @@
 
 &usb_otg_hs {
 	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
 	mode = <3>;
 	power = <50>;
 };
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 05f51e1..96d1c20 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -68,6 +68,7 @@
 
 &usb_otg_hs {
 	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
 	mode = <3>;
 	power = <50>;
 };
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index d4a7280..a626c50 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -73,6 +73,7 @@
 
 &usb_otg_hs {
 	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
 	mode = <3>;
 	power = <50>;
 };
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 4ad03d9..82a404d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -519,7 +519,6 @@
 			interrupts = <0 92 0x4>, <0 93 0x4>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
-			usb-phy = <&usb2_phy>;
 			multipoint = <1>;
 			num-eps = <16>;
 			ram-bits = <12>;


From s-anna at ti.com  Wed May  8 21:25:51 2013
From: s-anna at ti.com (Suman Anna)
Date: Wed, 8 May 2013 20:25:51 -0500
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
 <518976B9.2030605@ti.com>
 <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>
Message-ID: <518AFB1F.7010409@ti.com>

Hi Jassi,

>>>>>
>>>>>  The client(s) can always generate TX requests at a rate greater than
>>>>> the API could transmit on the physical link. So as much as we dislike
>>>>> it, we have to buffer TX requests, otherwise N clients would.
>>>>
>>>> The current code doesn't support N clients today anyway, and if they are
>>>> blocking mode on top of it, it would never need Tx buffering.
>>>>
>>> No, I meant if the API doesn't buffer TX requests, then N client
>>> drivers that simply need to send 2 or more messages would have to
>>> buffer them locally.
>>>  Also by buffering TX requests the API reduces TX latency by
>>> submitting the next request atomically as soon as it knows the last TX
>>> is done.
>>
>> OK. I do not have an issue with Tx buffering,
>>
> OK, thanks for confirming.
> 
>> but the manner it is done.
>> As I said before, there is a big implementation detail on client users
>> keeping their pointers in tact until the actual Tx is done - it
>> increases the complexity of client code. I have proposed an idea below
>> on the size discussion.
>>
> What makes this API different that you want it to create internal
> copies of clients' requests?
> I2C clients have been working fine. I believe most other apis work
> similarly. No client died of the burden of having to preserve request
> pointers until the request is served by the API.

You are implying that every client does need to implement a tx_callback,
or needs to care for because of the design in the common core code. I
cannot use local variables in whatever function I am sending the
requests. The example you have given below will fail when the client
doesn't care about tx callbacks neither is blocking, if the entire
request is implemented as a function.

> 
> BTW, by forcing the API to not directly use request structures from
> clients we kill chances of zero-copy transfer use-cases.

I doubt true zero-copy transfers can be achieved for most controllers,
you will almost always copy the client payload into the physical
transport payload. For true zero-copy, you would have to give out the
ioremapped transport payload ptr to a client.

> Sorry, I don't think just to make it "easy" for some rare client (that
> issues non-blocking pass-by-reference requests and don't even care to
> know if the message was ever sent), we should add complexity to the
> API _and_ kill some important use-cases.

The OMAP usecase (existing now) uses this approach, and we got lucky
because our payload is u32 and we will overwrite the ptr with the actual
message value instead of using it as a ptr. The existing API will fail
if I just have these two conditions met by a client - no blocking and no
tx callbacks.

>>> Also logically coupling the independent physical links makes the
>>> controller driver not very portable - what if some other platform has
>>> usage of 3 send+receive and 2 send-only communications of the 8
>>> physical links? The controller h/w is perfectly capable of providing
>>> that, but its driver is not.
>>
>> That's upto that controller driver, right?
>>
> Yes, I meant the OMAP's controller driver need to be re-written
> properly so as to not couple 2 links together as one RX and one TX.

Maybe for a different type of controller, but OMAP definitely doesn't
need this additional complexity for the foreseeable future, neither in
the client nor in the controller driver.

>>>> In anycase,
>>>> global publication will have its own set of problems - mostly you are
>>>> implying another layer of implementation that provides this sharing
>>>> capability (since they have to be outside of any single client).
>>>>
>>> Yes. Though yet another way of doing it is for the controller driver
>>> to populate N logical per physical link that needs to be shared.
>>
>> Yeah, I was implying the same idea.. The notifier chains in the current
>> driver really meant the logical and physical is the same as we are
>> returning the link handle, but with your current design of returning
>> ipc_chan as an opaque handle, you already have the base infrastructure
>> in place. Once we add tx callbacks, even the original mailbox series
>> would have transformed into having a similar concept as what you have.
>>
> Though I would still suggest you manage a remote by a local 'server'
> code - not every client needs to be bothered with request/response for
> every other client.

That's a client protocol or functional integration aspect of the
clients, remote and controller driver on the particular SoC, right?

> Also the OMAP might be lucky, but the remote may not always simply
> respond to commands from local clients. The remote might also send
> some SOS or similar command on behalf of the remote as a whole. Such
> requests should be handled by that local 'server' code.
> 
> 
>>> The OMAP simply pass by value a u32 as a message.  Why do you think it
>>> won't work ? (Please have a look at my implementation of the omap2
>>> controller driver)
>>
>> I am talking about queueing more than 1 request, we simply send a
>> message that can be triggered by either remoteproc for PM purposes or by
>> different rpmsg clients sending a message. It is delivered into the
>> mailbox and there is no implicit ack needed on tx_done since that is
>> dealt by the client messaging protocol sitting above. We will not be
>> using blocking mode, so there can be multiple requests at the same time
>> (in the queue).
>>
> Yes that's what I am talking about.  Multiple requests would still be
> a u32 each.

This discussion came about from your statement, "Most of the clients
won't queue more than 1 request at a time. And then, isn't it only
natural that clients don't mess with requests after submitting them?  I
see mailbox clients working quite like I2C clients."

> Since for OMAP a message is just a 32-bit number, a client would queue
> requests as
> {
>       u32 cmd;
>       cmd = COMMAND_A;
>       ipc_send_message(chan, (void *)cmd);
>       cmd = COMMAND_B;
>       ipc_send_message(chan, (void *)cmd);
>       cmd = COMMAND_C;
>       ipc_send_message(chan, (void *)cmd);
> }

This is the example I mentioned above (Make cmd a structure or an
integer array).

> 
> 
>>>>
>>> As I said, among other advantages, TX buffering is needed to reduce
>>> latencies. My platform's protocol isn't yet clear as to whether use
>>> shared-memory (secure and non-secure versions) for not very large data
>>> transfers or interrupt payload. So if we get good enough speed we
>>> could save cost on dedicated memories.
>>>
>>> I wrote the omap2 controller driver code to convey my proposal better.
>>> If you could please tell me how TX buffering is a problem for OMAP, it
>>> will help me understand your concern better.
>>
>> It is not a problem for OMAP
>>
> Thanks for confirming that it's not a problem for OMAP.
> 
> 
>>  The other thing is that you
>> have defined 10 as the queue length in the core, this should be dictated
>> by the controller or mailbox. What works for one platform may not work
>> for some others (this is what you saw as different config options
>> between OMAP and DBX500)
>>
> Please read the multi-line comment over that single line define.
> The buffer is cheap, just a void*, so we could make it even 50.
> However I am not hung on that.

OK good, because no single number would be good for all the controllers
or all possible clients.

> It purely depends upon how the client uses the link,

i guess you are saying this because of the possible blocking behavior of
a client, or the exclusive access to a link.

> so it can't be driven by the controller. We could make it a Kconfig option.
> What do you suggest?

I am saying controller/link because they are the ones that knows how the
physical transport is, and it may vary from one to another. I would
think that the client dependencies would become a subset of this.
Kconfig option is fine, but we have to think about the best way of
representing it from a multi-platform kernel support perspective.

>>>>
>>> How could the core perform any meaningful sanity check?  What if we
>>> send/receive proper 'datalen' of garbage data?  What if the client
>>> sends a "Give me info in not more than 32-bytes at a time" command to
>>> the remote and the remote has valid info worth only 16 bytes?
>>> IMHO there is not much for core to verify in a packet in transit. The
>>> introduced checks are not worth it and actually limit some scenarios
>>> like above example.
>>
>> OK, I had mainly two ideas, one telling the size of the void * on Tx,
>> with the controller driver specifying max (and maybe min sizes expected)
>>
> No, please. The controller driver is supposed to be reusable over
> various protocols. A protocol dictates the length of each logical TX
> unit. The max-min limits set by the controller driver might work for
> one but fail some other higher level protocol.
> 
>>
>> The second (major reason) idea was driven by the kfifo implementation
>> for buffering in core code for which I need the size field, so that the
>> clients need not be intelligent about the status of its tx submission
>> and maintaining its pointer (if you have different calling contexts). I
>> guess both of us are coming from different perspectives here, you may
>> find kfifos inefficient and I may find the complexity in client driver
>> unnecessary for maintaining pointers. How about defining add and remove
>> buffer ops in the controller driver so that it can choose its
>> implementation, while we keep the overall flow architecture in the core
>> code?
>>
> As I said the API shouldn't keep internal copies of a client's
> requests - it will only kill zero-copy use-cases while adding
> complexity to the core.

This is the reason I was suggesting the nature be dictated by a
controller, rather than 1 design in core code mandating a certain usage.
The client & controller together would know the functional integration
aspect.

> Since it already works fine for OMAP, I request we leave it as such
> for now at least.

OK, we should make a note of it in some documentation.

>>>>
>>>> Yeah, assumptions hold true until an unfortunate SoC comes up with it
>>>> :). The TI AM3352 has one link that doesn't behave quite like the other
>>>> (I am hoping to avoid using it), so I am ok with it for now. Guess we
>>>> can always change it when a concrete need arises.
>>>>
>>> It would work right now :)   If your controller has 2 types of links,
>>> the driver should register each bunch separately, each with its own
>>> ipc_link_ops, with the core. The core can already take care of the
>>> rest.
>>
>> Yeah, it can be done that way, but that's a not-so-elegant work-around
>>
> OTOH I find it elegant and not a "work around".
> Liberally estimating, hardly 10% of IPC controllers would have 2
> classes of physical links. Having link_ops per controller reduces the
> number of ipc_link_ops structures 11:20 as compared to per link.
> 
> 
>> IMHO. It's calling ipc_links_register twice on the same controller. Idea
>> was that the API would distinguish different controllers, not the same
>> one. Also, see the above example if you were to treat a link as Rx or Tx
>> only (functional behavior differences even though the link is exactly
>> the same type).
>>
> Why is calling ipc_links_register() twice, for a controller with 2
> classes of links, a problem ?

It will be inelegant, once you start maintaining the list of
ipc_controllers in the core code. You would have to search all the
controllers in the list with the matching name, and their links. You
will need to define multiple controller specific controller structures
and copy most of the elements from the actual h/w device into the
containing ipc_controller definition. As you said, the clients deal with
the links themselves, so making the ops part of the ipc_link definition
makes it easier on the controller implementations. You are anyway
caching the ops in ipc_chan (per link) and that is what you are using in
the core code. Majority of the time, you would be using the same ops for
all the links, but this gives the flexibility to links. You can avoid
having multiple controller instance denoting the h/w block, just because
of the difference in links behavior.

> 
> And, No, the API need not know if the link is "RX" or "TX", which is
> purely a logical function.
> 
> Please do tell me which controller physically limits its links to do
> only "RX" or only "TX"?  It's just the platform's firmware that
> dictates who sends and who receives on which link, thereby giving the
> illusion of a link being a "RX" or "TX" capable only.
> Even if some h/w limits do exist on links of some controller, still
> the API shouldn't try to discern a "RX" from a "TX" link. When a
> client knows which link to open, it will also know if it should read
> or write to it - this assumption already holds true. If the client
> writes on a link that it's supposed to listen to remote on, no amount
> of policing by the API could help.
>
> Even if the API tries to differentiate "RX" and "TX" links, the
> knowledge must come from a client (it's driven by the protocol on the
> platform), and not the controller because each of its links are
> physically equally capable to do RX or TX on each end.

The API never differentiates, but the controller implementation has to.
>From a controller driver implementation perspective, you still have to
make sure that no client is calling an op on which it is not supposed
to. When you have a mixture like this, a common code would include some
dead paths for certain links.

> 
> 
>>> Yes, I have 2 types of controllers and I already thought about
>>> multiple controllers in a platform.
>>>  What do you expect to do in controller startup/shutdown? Since the
>>> API works on individual links, not the controllers, when would it call
>>> controller_start() and controller_shutdown()?  The ipc_link's
>>> startup/shutdown are already non-atomic, if the controller needs any
>>> setup it could do it in the first link's startup and teardown in the
>>> last link's shutdown. Not to forget the resources lke IRQ are usually
>>> per Link which should be acquired/released upon link's use/idle.
>>>  While writing the OMAP2 controller driver, did I miss any controller
>>> startup/shutdown ?
>>
>> It just delineates the code better, and has flexibility later on to
>> extend any controller ops or exposing new controller-specific API. The
>> controller start and stop will be called in the same function as
>> ipc_request_channel.
>>
> Already one call ipc_link_ops.startup() reaches the controller upon
> ipc_request_channel.
> 
> Do you mean ?
>        ipc_con_ops.startup();
>        ipc_link_ops.startup();

Yes.

> 
> Why have 2 contiguous calls to the controller, to perform similar
> functions?  Not to forget the API and clients don't work on IPC
> controllers, but only on links. So it would be out-of-line for them to
> have to worry about the controller.

As I said, mainly to help dilineate the controller implementation code
better. I can live with it not being present, as my startup function
would anyway be refactored into two - one for the controller, and one
for the link itself. And I bet most would do the same if they have
multiple links in a controller.

> 
>>
>> Yeah, the pm_runtime_enable cannot be called twice when mailbox is
>> invoked from multiple clients on separate links, so there has to a
>> controller-level logic/ref-counting for that. The clocking for us is on
>> the controller.
>>
> No.  You could call pm_runtime_enable/disable any number of times as
> long as they are balanced. The core does refcounting.

Exactly, as long as they are balanced. I have two clients dealing with
two remotes (using two links) so pm_runtime_enable on the h/w block
needs to be called only when the first one comes in. Anyway, this is
just an FYI, as this file will obviously be different since I have to
not break my existing clients.

regards
Suman




From tom.leiming at gmail.com  Wed May  8 21:52:27 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Thu, 9 May 2013 09:52:27 +0800
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130508150800.GI2703@arm.com>
References: <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
 <20130508150800.GI2703@arm.com>
Message-ID: <CACVXFVMLu=18WyQKy3ucZXHxkHK9cSekrWgTOTt4Er1j46ko-g@mail.gmail.com>

On Wed, May 8, 2013 at 11:08 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> On Sat, May 04, 2013 at 09:21:27AM +0100, Ming Lei wrote:
>> On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
>> >>
>> >> I assume that you inhibited the call to flush_dcache_page() in
>> >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
>> >> with warnings.
>> >
>> > I haven't done any stress testing so I don't think I hit this code path,
>> > so no warning. But yes, it should have triggered. Anyway, in this case
>> > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
>> > harmless anyway if we also ignore this bit in __sync_icache_dcache for
>> > non-aliasing caches).
>>
>> Yes, maybe we can do a little optimization for O_DIRECT since no
>> dcache alias and I/D coherency problem in this case on ARMv7, how
>> about below change?
>>
>> diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
>> index 1c8f7f5..962a657 100644
>> --- a/arch/arm/mm/flush.c
>> +++ b/arch/arm/mm/flush.c
>> @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
>>           mapping && !mapping_mapped(mapping))
>>               clear_bit(PG_dcache_clean, &page->flags);
>>       else {
>> +             if (!mapping && cache_is_vipt_nonaliasing())
>> +                     return;
>>               __flush_dcache_page(mapping, page);
>>               if (mapping && cache_is_vivt())
>>                       __flush_dcache_aliases(mapping, page);
>
> I wonder whether we could move the:
>
>         if (!mapping)
>                 return
>
> at the top of this function, IOW don't touch any anonymous pages. Would
> anything be broken (apart from wrong API use)?

In case of O_DIRECT, the anonymous page may be shared, so looks it
should be flushed for vipt_aliasing cache.

Catalin, btw, would you mind give comments on the patch below(it might
be a 'fix' on one commit you submitted)?

      http://marc.info/?l=linux-arm-kernel&m=136757247311694&w=2

Thanks
-- 
Ming Lei


From horms at verge.net.au  Wed May  8 23:25:44 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 9 May 2013 12:25:44 +0900
Subject: [PATCH] ARM: shmobile: fix sleep-r8a7740.S miscompiles
In-Reply-To: <201305081418.05091.arnd@arndb.de>
References: <201305081418.05091.arnd@arndb.de>
Message-ID: <20130509032544.GB13994@verge.net.au>

On Wed, May 08, 2013 at 02:18:04PM +0200, Arnd Bergmann wrote:
> The newly added sleep-r8a7740.S file in shmobile does not
> actually build because of renamed symbols.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Bastian Hecht <hechtb+renesas at gmail.com>
> Cc: Simon Horman <horms+renesas at verge.net.au>
> ---
> 
> Simon, please apply to whichever branch of yours has the broken commit,
> or fold this patch into Bastian's patch.
> 
> linux-next doesn't build for me because of this, mainline is still fine.

Sure, will do.

I am traveling today so I may not be able to deal with this
properly until tomorrow.

> 
> diff --git a/arch/arm/mach-shmobile/sleep-r8a7740.S b/arch/arm/mach-shmobile/sleep-r8a7740.S
> index 435531b..982eacb 100644
> --- a/arch/arm/mach-shmobile/sleep-r8a7740.S
> +++ b/arch/arm/mach-shmobile/sleep-r8a7740.S
> @@ -32,7 +32,7 @@ ENTRY(r8a7740_shutdown)
>  wfi_loop:
>  	bl	cpu_v7_do_idle
>  	b wfi_loop
> -ENDPROC(r8a7740)
> +ENDPROC(r8a7740_shutdown)
>  
>  	.text
>  ENTRY(v7_cpu_resume)
> @@ -53,5 +53,5 @@ ENDPROC(v7_cpu_resume)
>  ENTRY(r8a7740_resume)
>  	ldr	pc, 1f
>  1:	.long	v7_cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
> -ENDPROC(r8a7740_resume_core_standby)
> +ENDPROC(r8a7740_resume)
>  #endif
> 


From horms at verge.net.au  Wed May  8 23:38:19 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 9 May 2013 12:38:19 +0900
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <CABYn4sxrcGmnTAJcQR23nMGy8JvqyDrgPOXF4yBFFU_4C8Pc_g@mail.gmail.com>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>
 <20130501225748.GD6517@verge.net.au>
 <201305081416.06611.arnd@arndb.de>
 <CABYn4sxrcGmnTAJcQR23nMGy8JvqyDrgPOXF4yBFFU_4C8Pc_g@mail.gmail.com>
Message-ID: <20130509033819.GC13994@verge.net.au>

On Wed, May 08, 2013 at 03:22:22PM +0200, Bastian Hecht wrote:
> Hi,
> 
> 2013/5/8 Arnd Bergmann <arnd at arndb.de>:
> > On Thursday 02 May 2013, Simon Horman wrote:
> >> > > diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
> >> > > index 8871f77..5dc57f1 100644
> >> > > --- a/arch/arm/mach-shmobile/intc-r8a7740.c
> >> > > +++ b/arch/arm/mach-shmobile/intc-r8a7740.c
> >> > > @@ -53,14 +53,23 @@ static void __init r8a7740_init_irq_common(void)
> >> > >
> >> > >  void __init r8a7740_init_irq_of(void)
> >> > >  {
> >> > > +       if (!IS_ENABLED(CONFIG_OF))
> >> > > +               return;
> >> > > +
> >> > >         irqchip_init();
> >> >
> >> > Why not have an empty irqchip_init? I'd guess we'll need this on other
> >> > platforms and your default mach.
> >>
> >> Thanks, I think that could work.
> >>
> >> I will see about making it so.
> >
> > Ping
> 
> I have sent out a patch adding an empty irqchip_init() when
> CONFIG_IRQCHIP is not set with the subject
> [PATCH] irqchip: Add irqchip_init dummy function

Thanks.

> > Linux-next is still broken for me. There is also anothe shmobile build bug,
> > I'll send a separate patch for that, which also needs to go into your tree.

Sorry about that. I though I had pushed your fix (the first hunk of the
patch that started this thread), but it seems that I did not.

> Oh thanks Arnd for this fix!
> 
> Cheers,
> 
>  Bastian


From b32955 at freescale.com  Wed May  8 23:28:58 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 11:28:58 +0800
Subject: [PATCH 0/5] add SPI/NOR for imx6q{dl}-sabreauto boards
Message-ID: <1368070143-1655-1-git-send-email-b32955@freescale.com>

this patch set add the SPI/NOR support for imx6q-sabreauto/imx6dl-sabreauto
boards.

Tested on both boards.

Huang Shijie (5):
  ARM: dts: imx6q: add a new device node for ecspi1
  ARM: dts: imx6dl: add a pinctrl for eCSPI1
  ARM: dts: imx6dl: add a gpio for hog
  ARM: dts: imx6q: add a gpio for hog
  ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards

 arch/arm/boot/dts/imx6dl-sabreauto.dts   |    1 +
 arch/arm/boot/dts/imx6dl.dtsi            |   10 +++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts    |    1 +
 arch/arm/boot/dts/imx6q.dtsi             |   11 ++++++++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
 5 files changed, 55 insertions(+), 0 deletions(-)




From b32955 at freescale.com  Wed May  8 23:29:00 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 11:29:00 +0800
Subject: [PATCH 2/5] ARM: dts: imx6dl: add a pinctrl for eCSPI1
In-Reply-To: <1368070143-1655-1-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
Message-ID: <1368070143-1655-3-git-send-email-b32955@freescale.com>

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 24544ed..4b13454 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -35,6 +35,16 @@
 				compatible = "fsl,imx6dl-iomuxc";
 				reg = <0x020e0000 0x4000>;
 
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+							MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+							MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+						>;
+					};
+				};
+
 				enet {
 					pinctrl_enet_1: enetgrp-1 {
 						fsl,pins = <
-- 
1.7.1




From b32955 at freescale.com  Wed May  8 23:29:02 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 11:29:02 +0800
Subject: [PATCH 4/5] ARM: dts: imx6q: add a gpio for hog
In-Reply-To: <1368070143-1655-1-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
Message-ID: <1368070143-1655-5-git-send-email-b32955@freescale.com>

The SPI/NOR needs this gpio for CS.
So add this gpio in the hog pinctrl.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q-sabreauto.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 49d6f28..9fb3e99 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -29,6 +29,7 @@
 			fsl,pins = <
 				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
 			>;
 		};
 	};
-- 
1.7.1




From b32955 at freescale.com  Wed May  8 23:29:01 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 11:29:01 +0800
Subject: [PATCH 3/5] ARM: dts: imx6dl: add a gpio for hog
In-Reply-To: <1368070143-1655-1-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
Message-ID: <1368070143-1655-4-git-send-email-b32955@freescale.com>

The SPI/NOR needs this gpio for CS.
So add this gpio in the hog pinctrl.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl-sabreauto.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 7adcec3..60f3038 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -25,6 +25,7 @@
 			fsl,pins = <
 				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
 			>;
 		};
 	};
-- 
1.7.1




From b32955 at freescale.com  Wed May  8 23:29:03 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 11:29:03 +0800
Subject: [PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards
In-Reply-To: <1368070143-1655-1-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
Message-ID: <1368070143-1655-6-git-send-email-b32955@freescale.com>

Since the SPI/NOR has pin conflict with the WEIM NOR,
we disable the spi/nor by default.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 7b561fb..b6b9e56 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -16,6 +16,38 @@
 	};
 };
 
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio3 19 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	status = "disabled";
+
+	flash: m25p80 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+
+		partition at 0 {
+			label = "U-Boot";
+			reg = <0x0 0x40000>;
+		};
+
+		partition at 40000 {
+			label = "U-Boot-ENV";
+			reg = <0x40000 0x10000>;
+			read-only;
+		};
+
+		partition at 50000 {
+			label = "Kernel";
+			reg = <0x50000 0x3b0000>;
+		};
+	};
+};
+
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet_2>;
-- 
1.7.1




From b32955 at freescale.com  Wed May  8 23:28:59 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 11:28:59 +0800
Subject: [PATCH 1/5] ARM: dts: imx6q: add a new device node for ecspi1
In-Reply-To: <1368070143-1655-1-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
Message-ID: <1368070143-1655-2-git-send-email-b32955@freescale.com>

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..5601026 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -59,6 +59,17 @@
 	soc {
 		aips-bus at 02000000 { /* AIPS1 */
 			spba-bus at 02000000 {
+				ecspi1: ecspi at 02008000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02008000 0x4000>;
+					interrupts = <0 31 0x04>;
+					clocks = <&clks 112>, <&clks 112>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
 				ecspi5: ecspi at 02018000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
-- 
1.7.1




From horms at verge.net.au  Wed May  8 23:44:11 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 9 May 2013 12:44:11 +0900
Subject: [PATCH] irqchip: Add irqchip_init dummy function
In-Reply-To: <518A9EBA.6070609@cogentembedded.com>
References: <1368019204-24448-1-git-send-email-hechtb+renesas@gmail.com>
 <518A6C05.9030303@cogentembedded.com>
 <201305081833.03716.arnd@arndb.de>
 <518A9EBA.6070609@cogentembedded.com>
Message-ID: <20130509034410.GD13994@verge.net.au>

On Wed, May 08, 2013 at 10:51:38PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 05/08/2013 08:33 PM, Arnd Bergmann wrote:
> 
> >
> >>>--- a/include/linux/irqchip.h
> >>>+++ b/include/linux/irqchip.h
> >>>@@ -11,6 +11,10 @@
> >>>   #ifndef _LINUX_IRQCHIP_H
> >>>   #define _LINUX_IRQCHIP_H
> >>>
> >>>+#ifdef CONFIG_IRQCHIP
> >>>   void irqchip_init(void);
> >>>+#else
> >>>+void irqchip_init(void) {};
> >>     Semicolon not needed here.
> >>
> >>>+#endif
> >More importantly, the function should be marked as "static inline", otherwise
> >you get a link error if this header is included in more than one place.
> 
>     Right, I should have noticed that too. :-)
> 
> >	Arnd

Thanks, I will queue-up the following in the intc-external-irq branch.


From: Bastian Hecht <hechtb at gmail.com>

irqchip: Add irqchip_init dummy function

We add an empty irqchip_init dummy function for cases in which
CONFIG_IRQCHIP is not used. In these cases irqchip.c is not compiled,
but a funtion call may still be present in architecture code, that in
runtime doesn't get hit.

E.g. this is needed in the arch/arm/mach-shmobile/intc-r8a7740.c
interrupt setup code where OF use and non OF us is both handled in one
file.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
[horms+renesas at verge.net.au: Make non-CONFIG_IRQCHIP version static inline
and remove trailing ';'.]
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
index e0006f1..14d7913 100644
--- a/include/linux/irqchip.h
+++ b/include/linux/irqchip.h
@@ -11,6 +11,10 @@
 #ifndef _LINUX_IRQCHIP_H
 #define _LINUX_IRQCHIP_H
 
+#ifdef CONFIG_IRQCHIP
 void irqchip_init(void);
+#else
+static inline void irqchip_init(void) {}
+#endif
 
 #endif


From skannan at codeaurora.org  Wed May  8 23:50:24 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 08 May 2013 20:50:24 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <518AE16D.5060501@codeaurora.org>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <518AE16D.5060501@codeaurora.org>
Message-ID: <518B1D00.5030700@codeaurora.org>

On 05/08/2013 04:36 PM, Stephen Boyd wrote:
> On 04/19/13 09:28, James Hogan wrote:
>> This patchset adds support for automatic selection of the best parent
>> for a clock mux, i.e. the one which can provide the closest clock rate
>> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
>> so that it doesn't happen unless explicitly allowed.
>>
>> This works by way of adding a new op, determine_rate, similar to
>> round_rate but with an extra parameter to allow the clock driver to
>> optionally select a different parent clock. This is used in
>> clk_calc_new_rates to decide whether to initiate a set_parent operation.
>
> Which tree is this based on? I get failures with git am on patch 2.
>

Mike's clk-for-3.10 branch.

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From pekon at ti.com  Thu May  9 00:12:10 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 9 May 2013 04:12:10 +0000
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <20130508235404.GX32546@atomide.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com> <20130508235404.GX32546@atomide.com>
Message-ID: <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>

> > >
> > >  	am33xx_pinmux: pinmux at 44e10800 {
> > >  		pinctrl-names = "default";
> > > -		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
> > > +		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
> > > +			&nandflash_pins_s0>;
> >
> > Why add this to the board level fallback (called pinctrl hogs, I think)?
> > This can be part of nand node you added below so that the pinctrl will
> > take effect when nand gets probed instead of all the time.
> 
> Yes we should have all the pinctrl entries under the related drivers.
> This makes it easy remux pins during runtime if needed, and also
> allows unloading pinctrl-single.ko for development.
> 
Yes, accepted. This has been already fixed in v3 of this patch set.
If all fine, then please pull this for next merge..

http://lists.infradead.org/pipermail/linux-mtd/2013-May/046712.html

http://lists.infradead.org/pipermail/linux-mtd/2013-May/046814.html (already pulled)

http://lists.infradead.org/pipermail/linux-mtd/2013-May/046710.html


with regards, pekon


From horms at verge.net.au  Thu May  9 00:20:31 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 9 May 2013 13:20:31 +0900
Subject: [PATCH] ARM: shmobile: fix sleep-r8a7740.S miscompiles
In-Reply-To: <20130509032544.GB13994@verge.net.au>
References: <201305081418.05091.arnd@arndb.de>
 <20130509032544.GB13994@verge.net.au>
Message-ID: <20130509042031.GA7832@verge.net.au>

On Thu, May 09, 2013 at 12:25:44PM +0900, Simon Horman wrote:
> On Wed, May 08, 2013 at 02:18:04PM +0200, Arnd Bergmann wrote:
> > The newly added sleep-r8a7740.S file in shmobile does not
> > actually build because of renamed symbols.
> > 
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > Cc: Bastian Hecht <hechtb+renesas at gmail.com>
> > Cc: Simon Horman <horms+renesas at verge.net.au>
> > ---
> > 
> > Simon, please apply to whichever branch of yours has the broken commit,
> > or fold this patch into Bastian's patch.
> > 
> > linux-next doesn't build for me because of this, mainline is still fine.
> 
> Sure, will do.
> 
> I am traveling today so I may not be able to deal with this
> properly until tomorrow.

I have queued this up in the soc-r8a7740 branch, where the problem was
added. I have pushed this branch along with a refreshed next branch.
This change should appear in linux-next in the not to distant future.


From horms at verge.net.au  Thu May  9 00:22:21 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 9 May 2013 13:22:21 +0900
Subject: [PATCH 03/21] ARM: shmobile: don't call irqchip_init
 unconditionally
In-Reply-To: <20130509033819.GC13994@verge.net.au>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <CAL_JsqJWJvxezXy0RGFutxzvBhca-8=uRH2GxdJgzbEGw+OL0A@mail.gmail.com>
 <20130501225748.GD6517@verge.net.au>
 <201305081416.06611.arnd@arndb.de>
 <CABYn4sxrcGmnTAJcQR23nMGy8JvqyDrgPOXF4yBFFU_4C8Pc_g@mail.gmail.com>
 <20130509033819.GC13994@verge.net.au>
Message-ID: <20130509042220.GB7832@verge.net.au>

On Thu, May 09, 2013 at 12:38:19PM +0900, Simon Horman wrote:
> On Wed, May 08, 2013 at 03:22:22PM +0200, Bastian Hecht wrote:
> > Hi,
> > 
> > 2013/5/8 Arnd Bergmann <arnd at arndb.de>:
> > > On Thursday 02 May 2013, Simon Horman wrote:
> > >> > > diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
> > >> > > index 8871f77..5dc57f1 100644
> > >> > > --- a/arch/arm/mach-shmobile/intc-r8a7740.c
> > >> > > +++ b/arch/arm/mach-shmobile/intc-r8a7740.c
> > >> > > @@ -53,14 +53,23 @@ static void __init r8a7740_init_irq_common(void)
> > >> > >
> > >> > >  void __init r8a7740_init_irq_of(void)
> > >> > >  {
> > >> > > +       if (!IS_ENABLED(CONFIG_OF))
> > >> > > +               return;
> > >> > > +
> > >> > >         irqchip_init();
> > >> >
> > >> > Why not have an empty irqchip_init? I'd guess we'll need this on other
> > >> > platforms and your default mach.
> > >>
> > >> Thanks, I think that could work.
> > >>
> > >> I will see about making it so.
> > >
> > > Ping
> > 
> > I have sent out a patch adding an empty irqchip_init() when
> > CONFIG_IRQCHIP is not set with the subject
> > [PATCH] irqchip: Add irqchip_init dummy function
> 
> Thanks.
> 
> > > Linux-next is still broken for me. There is also anothe shmobile build bug,
> > > I'll send a separate patch for that, which also needs to go into your tree.
> 
> Sorry about that. I though I had pushed your fix (the first hunk of the
> patch that started this thread), but it seems that I did not.

Sorry once again for the delay in addressing this.
I have pushed a refreshed next branch which includes
both Bastian's fix for irqchip_init() and the patch
that Arnd posted relating to symbol renames.

These changes should appear in linux-next in the not to distant future.


From skannan at codeaurora.org  Thu May  9 01:18:45 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed,  8 May 2013 22:18:45 -0700
Subject: [PATCH 2/3] clk: Disable unused clocks after deferred probing is done
In-Reply-To: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1368076726-11492-3-git-send-email-skannan@codeaurora.org>

With deferred probing, late_initcall() is too soon to declare a clock as
unused. Wait for deferred probing to finish before declaring a clock as
unused.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
 drivers/clk/clk.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index fe4055f..35de83b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -516,6 +516,8 @@ static int clk_disable_unused(void)
 		return 0;
 	}
 
+	wait_for_init_deferred_probe_done();
+
 	clk_prepare_lock();
 
 	hlist_for_each_entry(clk, &clk_root_list, child_node)
@@ -534,7 +536,7 @@ static int clk_disable_unused(void)
 
 	return 0;
 }
-late_initcall(clk_disable_unused);
+late_initcall_sync(clk_disable_unused);
 
 /***    helper functions   ***/
 
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May  9 01:18:43 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed,  8 May 2013 22:18:43 -0700
Subject: [PATCH 0/3] Fix disable of unused clk/regulator with deferred probe
Message-ID: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>

Clock and regulator frameworks have support for disabling unused clocks and
regulators at system init to save power when bootloaders leave them in a less
than desirable state. If no driver has requested for a clock/regulator to be
ON by the time kernel init reaches late_initcall level, they were considered
unused.

This worked well/good enough for compiled in drivers before deferred probe
was introduced. But with deferred probe, it's quite likely that devices that
match with compiled in drivers will continue to probe well past late_initcall
(at least as far as I can understand). So, we need to wait for deferred
probing during kernel init to complete before we do the disable of unused
clocks/regulators.

If there's a better or more obvious solution, I'm all ears. Another approach
would have been to add a "probe_done_initcall" level. But that seems overkill
and I don't think adding yet another initcall level is a great idea.

Thanks,
Saravana

Saravana Kannan (3):
  driver core: Add API to wait for deferred probe to complete during
    init
  clk: Disable unused clocks after deferred probing is done
  regulator: core: Disable unused regulators after deferred probing is
    done

 drivers/base/dd.c        |    8 ++++++++
 drivers/clk/clk.c        |    4 +++-
 drivers/regulator/core.c |    4 +++-
 include/linux/device.h   |    1 +
 4 files changed, 15 insertions(+), 2 deletions(-)

-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May  9 01:18:44 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed,  8 May 2013 22:18:44 -0700
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1368076726-11492-2-git-send-email-skannan@codeaurora.org>

Kernel framework (Eg: regulator, clock, etc) might want to do some clean up
work (Eg: turn off unclaimed resources) after all devices are done probing
during kernel init. Before deferred probing was introduced, this was
typically done using a late_initcall(). That approach still makes the
assumption that all drivers that are compiled in, register in one of the
earlier initcall levels.

With the introduction of deferred probing, even if the
assumption that all compiled in drivers register in one of the earlier
initcalls is ture, there is no longer a guarantee that all their matching
devices would have completed probing by late_initcall(). This is because
deferred probing loginc starts attempting the deferred probes only in a
late_initcall() function.

The most obvious fallback of using late_initcall_sync() also doesn't work
since the deferred probing work initated during late_initcall() is done in
a workqueue. So, frameworks that want to wait for all devices to finish
probing during init will now have to wait for the deferred workqueue to
finish it's work. This patch adds a wait_for_init_deferred_probe_done() API
that can by called from late_initcall_sync() or a workqueue started from
late_initcall_sync()

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
 drivers/base/dd.c      |    8 ++++++++
 include/linux/device.h |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index bb5645e..bb2b9c6 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -52,6 +52,7 @@ static DEFINE_MUTEX(deferred_probe_mutex);
 static LIST_HEAD(deferred_probe_pending_list);
 static LIST_HEAD(deferred_probe_active_list);
 static struct workqueue_struct *deferred_wq;
+DECLARE_COMPLETION(init_def_probe_done);
 
 /**
  * deferred_probe_work_func() - Retry probing devices in the active list.
@@ -105,6 +106,7 @@ static void deferred_probe_work_func(struct work_struct *work)
 		put_device(dev);
 	}
 	mutex_unlock(&deferred_probe_mutex);
+	complete_all(&init_def_probe_done);
 }
 static DECLARE_WORK(deferred_probe_work, deferred_probe_work_func);
 
@@ -179,6 +181,12 @@ static int deferred_probe_initcall(void)
 }
 late_initcall(deferred_probe_initcall);
 
+void wait_for_init_deferred_probe_done(void)
+{
+	wait_for_completion(&init_def_probe_done);
+}
+EXPORT_SYMBOL_GPL(wait_for_init_deferred_probe_done);
+
 static void driver_bound(struct device *dev)
 {
 	if (klist_node_attached(&dev->p->knode_driver)) {
diff --git a/include/linux/device.h b/include/linux/device.h
index 9d6464e..5c557f7 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -247,6 +247,7 @@ extern struct device_driver *driver_find(const char *name,
 					 struct bus_type *bus);
 extern int driver_probe_done(void);
 extern void wait_for_device_probe(void);
+extern void wait_for_init_deferred_probe_done(void);
 
 
 /* sysfs interface for exporting driver attributes */
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May  9 01:18:46 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed,  8 May 2013 22:18:46 -0700
Subject: [PATCH 3/3] regulator: core: Disable unused regulators after deferred
 probing is done
In-Reply-To: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1368076726-11492-4-git-send-email-skannan@codeaurora.org>

With deferred probing, late_initcall() is too soon to declare a regulator
as unused. Wait for deferred probing to finish before declaring a regulator
as unused.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
 drivers/regulator/core.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index e3661c2..11a0508 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -3812,6 +3812,8 @@ static int __init regulator_init_complete(void)
 	if (of_have_populated_dt())
 		has_full_constraints = true;
 
+	wait_for_init_deferred_probe_done();
+
 	mutex_lock(&regulator_list_mutex);
 
 	/* If we have a full configuration then disable any regulators
@@ -3864,4 +3866,4 @@ unlock:
 
 	return 0;
 }
-late_initcall(regulator_init_complete);
+late_initcall_sync(regulator_init_complete);
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From anup.patel at linaro.org  Thu May  9 01:53:33 2013
From: anup.patel at linaro.org (Anup Patel)
Date: Thu,  9 May 2013 11:23:33 +0530
Subject: [PATCH] arm64: KVM: Add bits for specifying memory type in stage2 PTE
Message-ID: <1368078813-16904-1-git-send-email-anup.patel@linaro.org>

We cannot use existing stage1 PTE_ATTRINDX() macro for specifying
stage2 memory type because stage1 ATTRINDX = PTE[4:2] and stage2
MEMATTR = PTE[5:2].

This patch adds bit definetions for specifying device, noncacheable,
writethrough, and writeback memory types in stage2 PTE and also uses
it in PAGE_S2 and PAGE_S2_DEVICE.

Signed-off-by: Anup Patel <anup.patel at linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
---
 arch/arm64/include/asm/pgtable-hwdef.h |    4 ++++
 arch/arm64/include/asm/pgtable.h       |    6 ++++--
 arch/arm64/mm/mmu.c                    |    9 +++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index c49cd61..555babb 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -73,6 +73,10 @@
  */
 #define PTE_S2_RDONLY		 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
 #define PTE_S2_RDWR		 (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+#define PTE_S2_MT_DEVICE	 (_AT(pteval_t, 0x0) << 2) /* MemAttr[3:0] */
+#define PTE_S2_MT_UNCACHED	 (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
+#define PTE_S2_MT_WRITETHROUGH	 (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
+#define PTE_S2_MT_WRITEBACK	 (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
 
 /*
  * EL2/HYP PTE/PMD definitions
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 43ce724..3003fd0 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -60,6 +60,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define _PAGE_DEFAULT		PTE_TYPE_PAGE | PTE_AF
 
 extern pgprot_t pgprot_default;
+extern pgprot_t pgprot_s2;
+extern pgprot_t pgprot_s2_device;
 
 #define __pgprot_modify(prot,mask,bits) \
 	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
@@ -79,8 +81,8 @@ extern pgprot_t pgprot_default;
 #define PAGE_HYP		_MOD_PROT(pgprot_default, PTE_HYP)
 #define PAGE_HYP_DEVICE		_MOD_PROT(__pgprot(PROT_DEVICE_nGnRE), PTE_HYP)
 
-#define PAGE_S2			_MOD_PROT(pgprot_default, PTE_S2_RDONLY)
-#define PAGE_S2_DEVICE		__pgprot_modify(__pgprot(PROT_DEVICE_nGnRE), PTE_PXN, PTE_S2_RDWR)
+#define PAGE_S2			_MOD_PROT(pgprot_s2, PTE_USER | PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, PTE_USER | PTE_S2_RDWR)
 
 #define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
 #define __PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 70b8cd4..ef26978 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -46,6 +46,12 @@ EXPORT_SYMBOL(empty_zero_page);
 pgprot_t pgprot_default;
 EXPORT_SYMBOL(pgprot_default);
 
+pgprot_t pgprot_s2;
+EXPORT_SYMBOL(pgprot_s2);
+
+pgprot_t pgprot_s2_device;
+EXPORT_SYMBOL(pgprot_s2_device);
+
 static pmdval_t prot_sect_kernel;
 
 struct cachepolicy {
@@ -147,6 +153,9 @@ static void __init init_mem_pgprot(void)
 	}
 
 	pgprot_default = __pgprot(PTE_TYPE_PAGE | PTE_AF | default_pgprot);
+
+	pgprot_s2 = __pgprot(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_S2_MT_WRITEBACK);
+	pgprot_s2_device = __pgprot(PTE_TYPE_PAGE | PTE_AF | PTE_S2_MT_DEVICE);
 }
 
 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-- 
1.7.9.5



From csd at broadcom.com  Thu May  9 01:55:42 2013
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 8 May 2013 22:55:42 -0700
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
Message-ID: <1368078942-31265-1-git-send-email-csd@broadcom.com>

Add SDHCI driver for the Broadcom 281xx SoCs. Also
add bindings for it into bcm281xx dts files.
Still missing:
 - power managemement

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
new file mode 100644
index 0000000..ad1c4bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
@@ -0,0 +1,16 @@
+Broadcom BCM281xx SDHCI driver
+
+This file documents differences between the core properties in mmc.txt
+and the properties in the bcm281xx driver.
+
+Required properties:
+- compatible : Should be "bcm,kona-sdhci"
+
+Example:
+
+sdio2: sdio at 0x3f1a0000 {
+	compatible = "bcm,kona-sdhci";
+	reg = <0x3f1a0000 0x10000>;
+	interrupts = <0x0 74 0x4>;
+};
+
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067c..9ae3404 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -27,4 +27,21 @@
 		status = "okay";
 	};
 
+	sdio0: sdio at 0x3f180000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		non-removable;
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index ad13588..6606b41 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,4 +47,33 @@
 		    cache-unified;
 		    cache-level = <2>;
 	};
+
+	sdio0: sdio at 0x3f180000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f180000 0x10000>;
+		interrupts = <0x0 77 0x4>;
+		status = "disabled";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f190000 0x10000>;
+		interrupts = <0x0 76 0x4>;
+		status = "disabled";
+	};
+
+	sdio2: sdio at 0x3f1a0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1a0000 0x10000>;
+		interrupts = <0x0 74 0x4>;
+		status = "disabled";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1b0000 0x10000>;
+		interrupts = <0x0 73 0x4>;
+		status = "disabled";
+	};
+
 };
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index e3bf2d6..65edf6d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index d88219e..e067c5a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
 
 	  YMMV.
 
+config MMC_SDHCI_BCM_KONA
+	tristate "SDHCI support on Broadcom KONA platform"
+	depends on ARCH_BCM && MMC_SDHCI_PLTFM
+	help
+	  This selects the Broadcom Kona Secure Digital Host Controller
+	  Interface(SDHCI) support.
+	  This is used in Broadcom mobile SoCs.
+
+	  If you have a controller with this interface, say Y or M here.
+
 config MMC_SDHCI_BCM2835
 	tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
 	depends on ARCH_BCM2835
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index c380e3c..a9f582b 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)		+= sdhci-dove.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
+obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
new file mode 100644
index 0000000..27188b9
--- /dev/null
+++ b/drivers/mmc/host/sdhci-bcm-kona.c
@@ -0,0 +1,486 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/highmem.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/version.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci.h"
+
+#define SDHCI_SOFT_RESET			0x01000000
+#define KONA_SDHOST_CORECTRL			0x8000
+#define KONA_SDHOST_CD_PINCTRL			0x00000008
+#define KONA_SDHOST_STOP_HCLK			0x00000004
+#define KONA_SDHOST_RESET			0x00000002
+#define KONA_SDHOST_EN				0x00000001
+
+#define KONA_SDHOST_CORESTAT			0x8004
+#define KONA_SDHOST_WP				0x00000002
+#define KONA_SDHOST_CD_SW			0x00000001
+
+#define KONA_SDHOST_COREIMR			0x8008
+#define KONA_SDHOST_IP				0x00000001
+
+#define KONA_SDHOST_COREISR			0x800C
+#define KONA_SDHOST_COREIMSR			0x8010
+#define KONA_SDHOST_COREDBG1			0x8014
+#define KONA_SDHOST_COREGPO_MASK		0x8018
+
+#define SD_DETECT_GPIO_DEBOUNCE_128MS		128
+
+#define KONA_MMC_AUTOSUSPEND_DELAY		(50)
+
+struct sdhci_bcm_kona_cfg {
+	unsigned int	max_freq;
+	int		is_8bit;
+	int		irq;
+	int		cd_gpio;
+	int		wp_gpio;
+	int		non_removable;
+};
+
+struct sdhci_bcm_kona_dev {
+	struct sdhci_bcm_kona_cfg *cfg;
+	struct device *dev;
+	struct sdhci_host *host;
+	struct clk *peri_clk;
+	struct clk *sleep_clk;
+};
+
+
+static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
+{
+	unsigned int val;
+	unsigned long timeout;
+
+	/* This timeout should be sufficent for core to reset */
+	timeout = jiffies + msecs_to_jiffies(100);
+
+	/* reset the host using the top level reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_RESET;
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
+		if (time_is_before_jiffies(timeout)) {
+			pr_err("Error: sd host is stuck in reset!!!\n");
+			return -EFAULT;
+		}
+	}
+
+	/* bring the host out of reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val &= ~KONA_SDHOST_RESET;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	udelay(1000);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	return 0;
+}
+
+static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
+{
+	unsigned int val;
+
+	/* enable the interrupt from the IP core */
+	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
+	val |= KONA_SDHOST_IP;
+	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
+
+	/* Enable the AHB clock gating module to the host */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_EN;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	udelay(1000);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+}
+
+/*
+ * Software emulation of the SD card insertion/removal. Set insert=1 for insert
+ * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
+ * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
+ * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
+ */
+static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
+{
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
+	u32 val;
+	unsigned long flags;
+
+	/* this function can be called from various contexts including ISR */
+	spin_lock_irqsave(&host->lock, flags);
+	/* Ensure SD bus scanning to detect media change */
+	host->mmc->rescan_disable = 0;
+
+	/*
+	 * Back-to-Back register write needs a delay of min 10uS.
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 * We keep 20uS
+	 */
+	udelay(20);
+	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
+
+	if (insert) {
+		if (kona_dev->cfg->wp_gpio >= 0) {
+			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
+
+			if (wp_status)
+				val |= KONA_SDHOST_WP;
+			else
+				val &= ~KONA_SDHOST_WP;
+		}
+
+		val |= KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	} else {
+		val &= ~KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	return 0;
+}
+
+/*
+ * SD card detection interrupt handler
+ */
+static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
+{
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
+
+	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
+		pr_debug("card inserted\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 1);
+	} else {
+		pr_debug("card removed\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Get the base clock. Use central clock source for now. Not sure if different
+ * clock speed to each dev is allowed
+ */
+static unsigned int sdhci_bcm_kona_get_max_clk(struct sdhci_host *host)
+{
+	struct sdhci_bcm_kona_dev *kona_dev;
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	kona_dev = pltfm_priv->priv;
+
+	return kona_dev->cfg->max_freq;
+}
+
+static unsigned int sdhci_bcm_kona_get_timeout_clock(struct sdhci_host *host)
+{
+	return sdhci_bcm_kona_get_max_clk(host);
+}
+
+static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
+				u8 power_mode)
+{
+	if (power_mode == MMC_POWER_OFF)
+		return;
+	else
+		mdelay(10);
+}
+
+static struct sdhci_ops sdhci_bcm_kona_ops = {
+	.get_max_clock = sdhci_bcm_kona_get_max_clk,
+	.get_timeout_clock = sdhci_bcm_kona_get_timeout_clock,
+	.platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
+};
+
+static struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
+	.ops    = &sdhci_bcm_kona_ops,
+	.quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
+		SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
+		SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
+		SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+static const struct of_device_id sdhci_bcm_kona_of_match[] __initdata = {
+	{ .compatible = "bcm,kona-sdhci", .data = &sdhci_pltfm_data_kona },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
+
+static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
+			struct platform_device *pdev)
+{
+	struct sdhci_bcm_kona_cfg *cfg;
+	struct device_node *np = pdev->dev.of_node;
+	u32 temp;
+
+	if (!np)
+		return NULL;
+
+	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
+	if (!cfg) {
+		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
+		return NULL;
+	}
+
+	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
+	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
+	if (of_get_property(np, "non-removable", NULL))
+		cfg->non_removable = 1;
+
+	if (of_property_read_u32(np, "bus-width", &temp) == 0 && temp == 8)
+		cfg->is_8bit = 1;
+
+	if (of_property_read_u32(np, "max-frequency", &cfg->max_freq)) {
+		dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
+		return NULL;
+	}
+	return cfg;
+}
+
+static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct sdhci_bcm_kona_cfg *kona_cfg = NULL;
+	const struct sdhci_pltfm_data *plat_data;
+	struct sdhci_bcm_kona_dev *kona_dev = NULL;
+	struct sdhci_pltfm_host *pltfm_priv;
+	struct device *dev = &pdev->dev;
+	struct sdhci_host *host;
+	int ret;
+	unsigned int irq;
+	ret = 0;
+
+	match = of_match_device(sdhci_bcm_kona_of_match, &pdev->dev);
+	if (!match)
+		plat_data = &sdhci_pltfm_data_kona;
+	else
+		plat_data = match->data;
+
+	host = sdhci_pltfm_init(pdev, (struct sdhci_pltfm_data *)plat_data);
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	kona_cfg = dev->platform_data;
+	if (!kona_cfg)
+		kona_cfg = sdhci_bcm_kona_parse_dt(pdev);
+
+	if (!kona_cfg) {
+		ret = -ENXIO;
+		goto err_pltfm_free;
+	}
+
+	dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
+
+	pltfm_priv = sdhci_priv(host);
+
+	kona_dev = devm_kzalloc(dev, sizeof(*kona_dev), GFP_KERNEL);
+	if (!kona_dev) {
+		dev_err(dev, "Can't allocate kona_dev\n");
+		ret = -ENOMEM;
+		goto err_pltfm_free;
+	}
+	kona_dev->cfg = kona_cfg;
+	kona_dev->dev = dev;
+	pltfm_priv->priv = kona_dev;
+
+	dev_dbg(dev, "non-removable=%c\n",
+		 (kona_cfg->non_removable) ? 'Y' : 'N');
+	dev_dbg(dev, "cd_gpio %d, wp_gpio %d\n", kona_cfg->cd_gpio,
+		 kona_cfg->wp_gpio);
+
+	if (kona_cfg->non_removable) {
+		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+	}
+
+	dev_dbg(dev, "is_8bit=%c\n", (kona_cfg->is_8bit) ? 'Y' : 'N');
+	if (kona_cfg->is_8bit)
+		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+	ret = sdhci_bcm_kona_sd_reset(host);
+	if (ret)
+		goto err_pltfm_free;
+
+	sdhci_bcm_kona_sd_init(host);
+
+	ret = sdhci_add_host(host);
+	if (ret) {
+		dev_err(dev, "Failed sdhci_add_host\n");
+		goto err_reset;
+	}
+
+	/* if device is eMMC, emulate card insert right here */
+	if (kona_cfg->non_removable) {
+		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
+		if (ret) {
+			dev_err(dev,
+				"unable to emulate card insertion\n");
+			goto err_remove_host;
+		}
+	} else if (kona_dev->cfg->cd_gpio >= 0) {
+		ret = devm_gpio_request(dev, kona_dev->cfg->cd_gpio, "sdio cd");
+		if (ret < 0) {
+			dev_err(kona_dev->dev,
+				"Unable to request GPIO pin %d\n",
+				kona_dev->cfg->cd_gpio);
+			goto err_remove_host;
+		}
+
+		gpio_direction_input(kona_dev->cfg->cd_gpio);
+
+		/* Set debounce for SD Card detect to maximum value (128ms)
+		 *
+		 * NOTE-1: If gpio_set_debounce() returns error we still
+		 * continue with the default debounce value set. Another reason
+		 * for doing this is that on rhea-ray boards the SD Detect GPIO
+		 * is on GPIO Expander and gpio_set_debounce() will return error
+		 * and if we return error from here, then probe() would fail and
+		 * SD detection would always fail.
+		 *
+		 * NOTE-2: We also give a msleep() of the "debounce" time here
+		 * so that we give enough time for the debounce to stabilize
+		 * before we read the gpio value in gpio_get_value_cansleep().
+		 */
+		ret = gpio_set_debounce(kona_dev->cfg->cd_gpio,
+				(SD_DETECT_GPIO_DEBOUNCE_128MS * 1000));
+		if (ret < 0) {
+			dev_err(kona_dev->dev,
+				"%s: gpio set debounce failed."
+				"default debounce value assumed\n", __func__);
+		}
+
+		/* Sleep for 128ms to allow debounce to stabilize */
+		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
+		/* request irq for cd_gpio after the gpio debounce is
+		 * stabilized, otherwise, some bogus gpio interrupts might be
+		 * triggered.
+		 */
+		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
+		ret = devm_request_threaded_irq(dev,
+				irq,
+				NULL,
+				sdhci_bcm_kona_pltfm_cd_interrupt,
+				IRQF_TRIGGER_FALLING|
+				IRQF_TRIGGER_RISING |
+				IRQF_ONESHOT |
+				IRQF_NO_SUSPEND, "sdio cd", host);
+		if (ret) {
+			dev_err(kona_dev->dev,
+				"Unable to request card detection irq=%d"
+				" for gpio=%d  ret=%d\n",
+				gpio_to_irq(kona_dev->cfg->cd_gpio),
+				kona_dev->cfg->cd_gpio, ret);
+			goto err_remove_host;
+		}
+		if (kona_dev->cfg->wp_gpio >= 0) {
+			ret = devm_gpio_request(dev,
+				kona_dev->cfg->wp_gpio, "sdio wp");
+			if (ret < 0) {
+				dev_err(&pdev->dev,
+					"Unable to request WP pin %d\n",
+					kona_dev->cfg->wp_gpio);
+				kona_dev->cfg->wp_gpio = -1;
+			} else {
+				gpio_direction_input(kona_dev->cfg->wp_gpio);
+			}
+		}
+
+		/*
+		 * Since the card detection GPIO interrupt is configured to be
+		 * edge sensitive, check the initial GPIO value here, emulate
+		 * only if the card is present
+		 */
+		if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0)
+			sdhci_bcm_kona_sd_card_emulate(host, 1);
+	}
+
+	dev_dbg(dev, "initialized properly\n");
+	return 0;
+
+err_remove_host:
+	sdhci_remove_host(host, 0);
+
+err_reset:
+	sdhci_bcm_kona_sd_reset(host);
+
+err_pltfm_free:
+	sdhci_pltfm_free(pdev);
+
+	dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
+	return ret;
+}
+
+static int __exit sdhci_bcm_kona_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_host->priv;
+	int dead;
+	u32 scratch;
+
+	dead = 0;
+	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
+	if (scratch == (u32)-1)
+		dead = 1;
+	sdhci_remove_host(host, dead);
+
+	sdhci_free_host(host);
+
+	return 0;
+}
+
+static struct platform_driver sdhci_bcm_kona_driver = {
+	.driver		= {
+		.name	= "sdhci-kona",
+		.owner	= THIS_MODULE,
+		.pm	= SDHCI_PLTFM_PMOPS,
+		.of_match_table = of_match_ptr(sdhci_bcm_kona_of_match),
+	},
+	.probe		= sdhci_bcm_kona_probe,
+	.remove		= __exit_p(sdhci_bcm_kona_remove),
+};
+module_platform_driver(sdhci_bcm_kona_driver);
+
+MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
+MODULE_AUTHOR("Broadcom");
+MODULE_LICENSE("GPL v2");
+
-- 
1.7.10.4




From plagnioj at jcrosoft.com  Thu May  9 02:35:03 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 9 May 2013 08:35:03 +0200
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1368078942-31265-1-git-send-email-csd@broadcom.com>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
Message-ID: <20130509063503.GF3041@game.jcrosoft.org>

On 22:55 Wed 08 May     , Christian Daudt wrote:
> Add SDHCI driver for the Broadcom 281xx SoCs. Also
> add bindings for it into bcm281xx dts files.
> Still missing:
>  - power managemement

split the dts/dtsi in an other patch
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> 
> diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
> new file mode 100644
> index 0000000..ad1c4bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
> @@ -0,0 +1,16 @@
> +Broadcom BCM281xx SDHCI driver
> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties in the bcm281xx driver.
> +
> +Required properties:
> +- compatible : Should be "bcm,kona-sdhci"
> +
> +Example:
> +
> +sdio2: sdio at 0x3f1a0000 {
> +	compatible = "bcm,kona-sdhci";
> +	reg = <0x3f1a0000 0x10000>;
> +	interrupts = <0x0 74 0x4>;
> +};
> +
> diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
> index 248067c..9ae3404 100644
> --- a/arch/arm/boot/dts/bcm11351-brt.dts
> +++ b/arch/arm/boot/dts/bcm11351-brt.dts
> @@ -27,4 +27,21 @@
>  		status = "okay";
>  	};
>  
> +	sdio0: sdio at 0x3f180000 {
> +		max-frequency = <48000000>;
> +		status = "okay";
> +	};
> +
> +	sdio1: sdio at 0x3f190000 {
> +		non-removable;
> +		max-frequency = <48000000>;
> +		status = "okay";
> +	};
> +
> +	sdio3: sdio at 0x3f1b0000 {
> +		max-frequency = <48000000>;
> +		status = "okay";
> +	};
> +
> +
>  };
> diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
> index ad13588..6606b41 100644
> --- a/arch/arm/boot/dts/bcm11351.dtsi
> +++ b/arch/arm/boot/dts/bcm11351.dtsi
> @@ -47,4 +47,33 @@
>  		    cache-unified;
>  		    cache-level = <2>;
>  	};
> +
> +	sdio0: sdio at 0x3f180000 {
> +		compatible = "bcm,kona-sdhci";
> +		reg = <0x3f180000 0x10000>;
> +		interrupts = <0x0 77 0x4>;
> +		status = "disabled";
> +	};
> +
> +	sdio1: sdio at 0x3f190000 {
> +		compatible = "bcm,kona-sdhci";
> +		reg = <0x3f190000 0x10000>;
> +		interrupts = <0x0 76 0x4>;
> +		status = "disabled";
> +	};
> +
> +	sdio2: sdio at 0x3f1a0000 {
> +		compatible = "bcm,kona-sdhci";
> +		reg = <0x3f1a0000 0x10000>;
> +		interrupts = <0x0 74 0x4>;
> +		status = "disabled";
> +	};
> +
> +	sdio3: sdio at 0x3f1b0000 {
> +		compatible = "bcm,kona-sdhci";
> +		reg = <0x3f1b0000 0x10000>;
> +		interrupts = <0x0 73 0x4>;
> +		status = "disabled";
> +	};
> +
>  };
> diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
> index e3bf2d6..65edf6d 100644
> --- a/arch/arm/configs/bcm_defconfig
> +++ b/arch/arm/configs/bcm_defconfig
> @@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
>  CONFIG_LCD_CLASS_DEVICE=y
>  CONFIG_BACKLIGHT_CLASS_DEVICE=y
>  # CONFIG_USB_SUPPORT is not set
> +CONFIG_MMC=y
> +CONFIG_MMC_UNSAFE_RESUME=y
> +CONFIG_MMC_BLOCK_MINORS=32
> +CONFIG_MMC_TEST=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_BCM_KONA=y
>  CONFIG_NEW_LEDS=y
>  CONFIG_LEDS_CLASS=y
>  CONFIG_LEDS_TRIGGERS=y
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index d88219e..e067c5a 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
>  
>  	  YMMV.
>  
> +config MMC_SDHCI_BCM_KONA
> +	tristate "SDHCI support on Broadcom KONA platform"
> +	depends on ARCH_BCM && MMC_SDHCI_PLTFM
select MMC_SDHCI_PLTFM
will be better
> +	help
> +	  This selects the Broadcom Kona Secure Digital Host Controller
> +	  Interface(SDHCI) support.
> +	  This is used in Broadcom mobile SoCs.
> +
> +	  If you have a controller with this interface, say Y or M here.
> +
>  config MMC_SDHCI_BCM2835
>  	tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
>  	depends on ARCH_BCM2835
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index c380e3c..a9f582b 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)		+= sdhci-dove.o
>  obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
>  obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
>  obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
> +obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
>  obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
>  
>  ifeq ($(CONFIG_CB710_DEBUG),y)
> diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
> new file mode 100644
> index 0000000..27188b9
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-bcm-kona.c
> @@ -0,0 +1,486 @@
> +/*
> + * Copyright (C) 2013 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/delay.h>
> +#include <linux/highmem.h>
> +#include <linux/platform_device.h>
> +#include <linux/mmc/host.h>
> +#include <linux/io.h>
> +#include <linux/gpio.h>
> +#include <linux/clk.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/version.h>
> +
> +#include "sdhci-pltfm.h"
> +#include "sdhci.h"
> +
> +#define SDHCI_SOFT_RESET			0x01000000
> +#define KONA_SDHOST_CORECTRL			0x8000
> +#define KONA_SDHOST_CD_PINCTRL			0x00000008
> +#define KONA_SDHOST_STOP_HCLK			0x00000004
> +#define KONA_SDHOST_RESET			0x00000002
> +#define KONA_SDHOST_EN				0x00000001
> +
> +#define KONA_SDHOST_CORESTAT			0x8004
> +#define KONA_SDHOST_WP				0x00000002
> +#define KONA_SDHOST_CD_SW			0x00000001
> +
> +#define KONA_SDHOST_COREIMR			0x8008
> +#define KONA_SDHOST_IP				0x00000001
> +
> +#define KONA_SDHOST_COREISR			0x800C
> +#define KONA_SDHOST_COREIMSR			0x8010
> +#define KONA_SDHOST_COREDBG1			0x8014
> +#define KONA_SDHOST_COREGPO_MASK		0x8018
> +
> +#define SD_DETECT_GPIO_DEBOUNCE_128MS		128
> +
> +#define KONA_MMC_AUTOSUSPEND_DELAY		(50)
> +
> +struct sdhci_bcm_kona_cfg {
> +	unsigned int	max_freq;
> +	int		is_8bit;
> +	int		irq;
> +	int		cd_gpio;
> +	int		wp_gpio;
> +	int		non_removable;
> +};
> +
> +struct sdhci_bcm_kona_dev {
> +	struct sdhci_bcm_kona_cfg *cfg;
> +	struct device *dev;
> +	struct sdhci_host *host;
> +	struct clk *peri_clk;
> +	struct clk *sleep_clk;
> +};
> +
> +
> +static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
> +{
> +	unsigned int val;
> +	unsigned long timeout;
> +
> +	/* This timeout should be sufficent for core to reset */
> +	timeout = jiffies + msecs_to_jiffies(100);
> +
> +	/* reset the host using the top level reset */
> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> +	val |= KONA_SDHOST_RESET;
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> +
> +	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
> +		if (time_is_before_jiffies(timeout)) {
> +			pr_err("Error: sd host is stuck in reset!!!\n");
> +			return -EFAULT;
> +		}
> +	}
> +
> +	/* bring the host out of reset */
> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> +	val &= ~KONA_SDHOST_RESET;
> +
> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	udelay(1000);
really a udelay of 1ms
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> +
> +	return 0;
> +}
> +
> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
> +{
> +	unsigned int val;
> +
> +	/* enable the interrupt from the IP core */
> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
> +	val |= KONA_SDHOST_IP;
> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
> +
> +	/* Enable the AHB clock gating module to the host */
> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> +	val |= KONA_SDHOST_EN;
> +
> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	udelay(1000);
ditto
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> +}
> +
> +/*
> + * Software emulation of the SD card insertion/removal. Set insert=1 for insert
> + * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
> + * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
> + * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
> + */
> +static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
> +{
> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
> +	u32 val;
> +	unsigned long flags;
> +
> +	/* this function can be called from various contexts including ISR */
> +	spin_lock_irqsave(&host->lock, flags);
> +	/* Ensure SD bus scanning to detect media change */
> +	host->mmc->rescan_disable = 0;
> +
> +	/*
> +	 * Back-to-Back register write needs a delay of min 10uS.
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 * We keep 20uS
> +	 */
> +	udelay(20);
> +	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
> +
> +	if (insert) {
> +		if (kona_dev->cfg->wp_gpio >= 0) {
gpio_is_valid
> +			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
> +
> +			if (wp_status)
> +				val |= KONA_SDHOST_WP;
> +			else
> +				val &= ~KONA_SDHOST_WP;
> +		}
> +
> +		val |= KONA_SDHOST_CD_SW;
> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
> +	} else {
> +		val &= ~KONA_SDHOST_CD_SW;
> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
> +	}
> +	spin_unlock_irqrestore(&host->lock, flags);
> +
> +	return 0;
> +}
> +
> +/*
> + * SD card detection interrupt handler
> + */
> +static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
> +
> +	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
> +		pr_debug("card inserted\n");
dev_dbg
> +		sdhci_bcm_kona_sd_card_emulate(host, 1);
> +	} else {
> +		pr_debug("card removed\n");
ditto
> +		sdhci_bcm_kona_sd_card_emulate(host, 0);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/*
> + * Get the base clock. Use central clock source for now. Not sure if different
> + * clock speed to each dev is allowed
> + */
> +static unsigned int sdhci_bcm_kona_get_max_clk(struct sdhci_host *host)
> +{
> +	struct sdhci_bcm_kona_dev *kona_dev;
> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
> +	kona_dev = pltfm_priv->priv;
> +
> +	return kona_dev->cfg->max_freq;
> +}
> +
> +static unsigned int sdhci_bcm_kona_get_timeout_clock(struct sdhci_host *host)
> +{
> +	return sdhci_bcm_kona_get_max_clk(host);
> +}
> +
> +static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
> +				u8 power_mode)
> +{
> +	if (power_mode == MMC_POWER_OFF)
> +		return;
> +	else
> +		mdelay(10);
> +}
> +
> +static struct sdhci_ops sdhci_bcm_kona_ops = {
> +	.get_max_clock = sdhci_bcm_kona_get_max_clk,
> +	.get_timeout_clock = sdhci_bcm_kona_get_timeout_clock,
> +	.platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
> +};
> +
> +static struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
> +	.ops    = &sdhci_bcm_kona_ops,
> +	.quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
> +		SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
> +		SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
> +		SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
> +		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +};
> +
> +static const struct of_device_id sdhci_bcm_kona_of_match[] __initdata = {
> +	{ .compatible = "bcm,kona-sdhci", .data = &sdhci_pltfm_data_kona },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
> +
> +static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
> +			struct platform_device *pdev)
> +{
> +	struct sdhci_bcm_kona_cfg *cfg;
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 temp;
> +
> +	if (!np)
> +		return NULL;
> +
> +	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
> +	if (!cfg) {
> +		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
> +		return NULL;
> +	}
> +
> +	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
> +	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
> +	if (of_get_property(np, "non-removable", NULL))
> +		cfg->non_removable = 1;
use of_property_read_bool
> +
> +	if (of_property_read_u32(np, "bus-width", &temp) == 0 && temp == 8)
> +		cfg->is_8bit = 1;
> +
> +	if (of_property_read_u32(np, "max-frequency", &cfg->max_freq)) {
> +		dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
> +		return NULL;
> +	}
> +	return cfg;
> +}
> +
> +static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
> +{
> +	const struct of_device_id *match;
> +	struct sdhci_bcm_kona_cfg *kona_cfg = NULL;
> +	const struct sdhci_pltfm_data *plat_data;
> +	struct sdhci_bcm_kona_dev *kona_dev = NULL;
> +	struct sdhci_pltfm_host *pltfm_priv;
> +	struct device *dev = &pdev->dev;
> +	struct sdhci_host *host;
> +	int ret;
> +	unsigned int irq;
> +	ret = 0;
> +
> +	match = of_match_device(sdhci_bcm_kona_of_match, &pdev->dev);
> +	if (!match)
> +		plat_data = &sdhci_pltfm_data_kona;
> +	else
> +		plat_data = match->data;
> +
> +	host = sdhci_pltfm_init(pdev, (struct sdhci_pltfm_data *)plat_data);
> +	if (IS_ERR(host))
> +		return PTR_ERR(host);
> +
> +	kona_cfg = dev->platform_data;
> +	if (!kona_cfg)
> +		kona_cfg = sdhci_bcm_kona_parse_dt(pdev);
> +
> +	if (!kona_cfg) {
> +		ret = -ENXIO;
> +		goto err_pltfm_free;
> +	}
> +
> +	dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
> +
> +	pltfm_priv = sdhci_priv(host);
> +
> +	kona_dev = devm_kzalloc(dev, sizeof(*kona_dev), GFP_KERNEL);
> +	if (!kona_dev) {
> +		dev_err(dev, "Can't allocate kona_dev\n");
> +		ret = -ENOMEM;
> +		goto err_pltfm_free;
> +	}
> +	kona_dev->cfg = kona_cfg;
> +	kona_dev->dev = dev;
> +	pltfm_priv->priv = kona_dev;
> +
> +	dev_dbg(dev, "non-removable=%c\n",
> +		 (kona_cfg->non_removable) ? 'Y' : 'N');
> +	dev_dbg(dev, "cd_gpio %d, wp_gpio %d\n", kona_cfg->cd_gpio,
> +		 kona_cfg->wp_gpio);
> +
> +	if (kona_cfg->non_removable) {
> +		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
> +		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
> +	}
> +
> +	dev_dbg(dev, "is_8bit=%c\n", (kona_cfg->is_8bit) ? 'Y' : 'N');
> +	if (kona_cfg->is_8bit)
> +		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
> +
> +	ret = sdhci_bcm_kona_sd_reset(host);
> +	if (ret)
> +		goto err_pltfm_free;
> +
> +	sdhci_bcm_kona_sd_init(host);
> +
> +	ret = sdhci_add_host(host);
> +	if (ret) {
> +		dev_err(dev, "Failed sdhci_add_host\n");
> +		goto err_reset;
> +	}
> +
> +	/* if device is eMMC, emulate card insert right here */
> +	if (kona_cfg->non_removable) {
> +		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
> +		if (ret) {
> +			dev_err(dev,
> +				"unable to emulate card insertion\n");
> +			goto err_remove_host;
> +		}
> +	} else if (kona_dev->cfg->cd_gpio >= 0) {
> +		ret = devm_gpio_request(dev, kona_dev->cfg->cd_gpio, "sdio cd");
> +		if (ret < 0) {
> +			dev_err(kona_dev->dev,
> +				"Unable to request GPIO pin %d\n",
> +				kona_dev->cfg->cd_gpio);
> +			goto err_remove_host;
> +		}
> +
> +		gpio_direction_input(kona_dev->cfg->cd_gpio);
> +
> +		/* Set debounce for SD Card detect to maximum value (128ms)
> +		 *
> +		 * NOTE-1: If gpio_set_debounce() returns error we still
> +		 * continue with the default debounce value set. Another reason
> +		 * for doing this is that on rhea-ray boards the SD Detect GPIO
> +		 * is on GPIO Expander and gpio_set_debounce() will return error
> +		 * and if we return error from here, then probe() would fail and
> +		 * SD detection would always fail.
> +		 *
> +		 * NOTE-2: We also give a msleep() of the "debounce" time here
> +		 * so that we give enough time for the debounce to stabilize
> +		 * before we read the gpio value in gpio_get_value_cansleep().
> +		 */
> +		ret = gpio_set_debounce(kona_dev->cfg->cd_gpio,
> +				(SD_DETECT_GPIO_DEBOUNCE_128MS * 1000));
> +		if (ret < 0) {
> +			dev_err(kona_dev->dev,
> +				"%s: gpio set debounce failed."
> +				"default debounce value assumed\n", __func__);
> +		}
> +
> +		/* Sleep for 128ms to allow debounce to stabilize */
> +		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
> +		/* request irq for cd_gpio after the gpio debounce is
> +		 * stabilized, otherwise, some bogus gpio interrupts might be
> +		 * triggered.
> +		 */
> +		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
> +		ret = devm_request_threaded_irq(dev,
> +				irq,
> +				NULL,
> +				sdhci_bcm_kona_pltfm_cd_interrupt,
> +				IRQF_TRIGGER_FALLING|
> +				IRQF_TRIGGER_RISING |
> +				IRQF_ONESHOT |
> +				IRQF_NO_SUSPEND, "sdio cd", host);
> +		if (ret) {
> +			dev_err(kona_dev->dev,
> +				"Unable to request card detection irq=%d"
> +				" for gpio=%d  ret=%d\n",
put the sting of the dev_err on one line so we can grep
> +				gpio_to_irq(kona_dev->cfg->cd_gpio),
> +				kona_dev->cfg->cd_gpio, ret);
> +			goto err_remove_host;
> +		}
> +		if (kona_dev->cfg->wp_gpio >= 0) {
> +			ret = devm_gpio_request(dev,
> +				kona_dev->cfg->wp_gpio, "sdio wp");
> +			if (ret < 0) {
> +				dev_err(&pdev->dev,
> +					"Unable to request WP pin %d\n",
> +					kona_dev->cfg->wp_gpio);
> +				kona_dev->cfg->wp_gpio = -1;
> +			} else {
> +				gpio_direction_input(kona_dev->cfg->wp_gpio);
> +			}
> +		}
> +
> +		/*
> +		 * Since the card detection GPIO interrupt is configured to be
> +		 * edge sensitive, check the initial GPIO value here, emulate
> +		 * only if the card is present
> +		 */
> +		if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0)
> +			sdhci_bcm_kona_sd_card_emulate(host, 1);
> +	}
> +
> +	dev_dbg(dev, "initialized properly\n");
> +	return 0;
> +
> +err_remove_host:
> +	sdhci_remove_host(host, 0);
> +
> +err_reset:
> +	sdhci_bcm_kona_sd_reset(host);
> +
> +err_pltfm_free:
> +	sdhci_pltfm_free(pdev);
> +
> +	dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
> +	return ret;
> +}
> +
> +static int __exit sdhci_bcm_kona_remove(struct platform_device *pdev)
> +{
> +	struct sdhci_host *host = platform_get_drvdata(pdev);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_host->priv;
> +	int dead;
> +	u32 scratch;
> +
> +	dead = 0;
> +	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
> +	if (scratch == (u32)-1)
> +		dead = 1;
> +	sdhci_remove_host(host, dead);
> +
> +	sdhci_free_host(host);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver sdhci_bcm_kona_driver = {
> +	.driver		= {
> +		.name	= "sdhci-kona",
> +		.owner	= THIS_MODULE,
> +		.pm	= SDHCI_PLTFM_PMOPS,
> +		.of_match_table = of_match_ptr(sdhci_bcm_kona_of_match),
> +	},
> +	.probe		= sdhci_bcm_kona_probe,
> +	.remove		= __exit_p(sdhci_bcm_kona_remove),
> +};
> +module_platform_driver(sdhci_bcm_kona_driver);
> +
> +MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
> +MODULE_AUTHOR("Broadcom");
> +MODULE_LICENSE("GPL v2");
> +
> -- 
> 1.7.10.4
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From sales at mts.nl  Thu May  9 02:32:01 2013
From: sales at mts.nl (laykoni)
Date: Thu, 9 May 2013 09:32:01 +0300
Subject: =?windows-1251?B?4eXn8+ru8Ojn7eXt7e7lIPDl+OXt6OUg5Ov/?=
 =?windows-1251?B?IOv+4fv1IOLg+Oj1IOLu7/Du8e7i?=
Message-ID: <12177D5D25C24FF082AF2AEB79A701A8@lqlketl>

????? ??????????? ??????????? ??? ???????????? ?????? ????? http://bit.ly/11JZlBU


? ???? ??? ?? ??????? ??????,


From shawn.guo at linaro.org  Thu May  9 03:08:22 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 May 2013 15:08:22 +0800
Subject: [PATCH] net: fec: enable hardware checksum only on imx6q-fec
Message-ID: <1368083302-12516-1-git-send-email-shawn.guo@linaro.org>

Commit 4c09eed (net: fec: Enable imx6 enet checksum acceleration.)
enables hardware checksum acceleration unconditionally for all fec
variants.  This is inappropriate, because some variants like imx5 have
no such support on hardware.  Consequently, fec is broken on these
platforms.  Fix it by enabling hardware checksum only on imx6q-fec type
of controllers.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/net/ethernet/freescale/fec_main.c |   20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index e25bf83..9ffa428 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -87,6 +87,8 @@
 #define FEC_QUIRK_HAS_GBIT		(1 << 3)
 /* Controller has extend desc buffer */
 #define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
+/* Controller has hardware checksum support */
+#define FEC_QUIRK_HAS_CSUM		(1 << 5)
 
 static struct platform_device_id fec_devtype[] = {
 	{
@@ -105,7 +107,7 @@ static struct platform_device_id fec_devtype[] = {
 	}, {
 		.name = "imx6q-fec",
 		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
-				FEC_QUIRK_HAS_BUFDESC_EX,
+				FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM,
 	}, {
 		.name = "mvf-fec",
 		.driver_data = FEC_QUIRK_ENET_MAC,
@@ -1723,6 +1725,8 @@ static const struct net_device_ops fec_netdev_ops = {
 static int fec_enet_init(struct net_device *ndev)
 {
 	struct fec_enet_private *fep = netdev_priv(ndev);
+	const struct platform_device_id *id_entry =
+				platform_get_device_id(fep->pdev);
 	struct bufdesc *cbd_base;
 
 	/* Allocate memory for buffer descriptors. */
@@ -1755,12 +1759,14 @@ static int fec_enet_init(struct net_device *ndev)
 	writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
 	netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
 
-	/* enable hw accelerator */
-	ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
-			| NETIF_F_RXCSUM);
-	ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
-			| NETIF_F_RXCSUM);
-	fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
+	if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
+		/* enable hw accelerator */
+		ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
+				| NETIF_F_RXCSUM);
+		ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
+				| NETIF_F_RXCSUM);
+		fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
+	}
 
 	fec_restart(ndev, 0);
 
-- 
1.7.9.5




From haojian.zhuang at linaro.org  Thu May  9 03:21:39 2013
From: haojian.zhuang at linaro.org (Haojian Zhuang)
Date: Thu, 9 May 2013 15:21:39 +0800
Subject: [PATCH 1/3] irqchip: move mmp irq driver
In-Reply-To: <1366537617-11328-1-git-send-email-haojian.zhuang@linaro.org>
References: <1366537617-11328-1-git-send-email-haojian.zhuang@linaro.org>
Message-ID: <CAD6h2NQc1YAh9nj6eCK+nkURFkeT6JidxTE7FBtEvk0fuvJ_tg@mail.gmail.com>

On 21 April 2013 17:46, Haojian Zhuang <haojian.zhuang at linaro.org> wrote:
> Move irq-mmp driver from mach-mmp directory into irqchip directory.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at linaro.org>
> ---
>  arch/arm/mach-mmp/Makefile                           |    2 +-
>  arch/arm/mach-mmp/common.h                           |    1 -
>  arch/arm/mach-mmp/include/mach/pxa168.h              |    1 +
>  arch/arm/mach-mmp/include/mach/pxa910.h              |    1 +
>  arch/arm/mach-mmp/pxa910.c                           |    1 +
>  drivers/irqchip/Makefile                             |    1 +
>  arch/arm/mach-mmp/irq.c => drivers/irqchip/irq-mmp.c |    2 --
>  7 files changed, 5 insertions(+), 4 deletions(-)
>  rename arch/arm/mach-mmp/irq.c => drivers/irqchip/irq-mmp.c (99%)
>
> diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
> index 095c155..9b702a1 100644
> --- a/arch/arm/mach-mmp/Makefile
> +++ b/arch/arm/mach-mmp/Makefile
> @@ -2,7 +2,7 @@
>  # Makefile for Marvell's PXA168 processors line
>  #
>
> -obj-y                          += common.o devices.o time.o irq.o
> +obj-y                          += common.o devices.o time.o
>
>  # SoC support
>  obj-$(CONFIG_CPU_PXA168)       += pxa168.o
> diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
> index 0bdc50b..9c1c9be 100644
> --- a/arch/arm/mach-mmp/common.h
> +++ b/arch/arm/mach-mmp/common.h
> @@ -2,7 +2,6 @@
>
>  extern void timer_init(int irq);
>
> -extern void __init icu_init_irq(void);
>  extern void __init mmp_map_io(void);
>  extern void mmp_restart(char, const char *);
>  extern void __init pxa168_clk_init(void);
> diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
> index 7ed1df2..e01dc2a 100644
> --- a/arch/arm/mach-mmp/include/mach/pxa168.h
> +++ b/arch/arm/mach-mmp/include/mach/pxa168.h
> @@ -2,6 +2,7 @@
>  #define __ASM_MACH_PXA168_H
>
>  extern void pxa168_timer_init(void);
> +extern void __init icu_init_irq(void);
>  extern void __init pxa168_init_irq(void);
>  extern void pxa168_restart(char, const char *);
>  extern void pxa168_clear_keypad_wakeup(void);
> diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
> index b914afa..9225320 100644
> --- a/arch/arm/mach-mmp/include/mach/pxa910.h
> +++ b/arch/arm/mach-mmp/include/mach/pxa910.h
> @@ -2,6 +2,7 @@
>  #define __ASM_MACH_PXA910_H
>
>  extern void pxa910_timer_init(void);
> +extern void __init icu_init_irq(void);
>  extern void __init pxa910_init_irq(void);
>
>  #include <linux/i2c.h>
> diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
> index ce6393a..a586742 100644
> --- a/arch/arm/mach-mmp/pxa910.c
> +++ b/arch/arm/mach-mmp/pxa910.c
> @@ -23,6 +23,7 @@
>  #include <mach/dma.h>
>  #include <mach/mfp.h>
>  #include <mach/devices.h>
> +#include <mach/pxa910.h>
>
>  #include "common.h"
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 8daa76a..9418f4b 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MXS)                  += irq-mxs.o
>  obj-$(CONFIG_ARCH_S3C24XX)             += irq-s3c24xx.o
>  obj-$(CONFIG_METAG)                    += irq-metag-ext.o
>  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)   += irq-metag.o
> +obj-$(CONFIG_ARCH_MMP)                 += irq-mmp.o
>  obj-$(CONFIG_ARCH_SUNXI)               += irq-sun4i.o
>  obj-$(CONFIG_ARCH_SPEAR3XX)            += spear-shirq.o
>  obj-$(CONFIG_ARM_GIC)                  += irq-gic.o
> diff --git a/arch/arm/mach-mmp/irq.c b/drivers/irqchip/irq-mmp.c
> similarity index 99%
> rename from arch/arm/mach-mmp/irq.c
> rename to drivers/irqchip/irq-mmp.c
> index 3c71246..dab6def 100644
> --- a/arch/arm/mach-mmp/irq.c
> +++ b/drivers/irqchip/irq-mmp.c
> @@ -30,8 +30,6 @@
>  #include <mach/pm-pxa910.h>
>  #endif
>
> -#include "common.h"
> -
>  #define MAX_ICU_NR             16
>
>  struct icu_chip_data {
> --
> 1.7.10.4
>

Hi Thomas,

Could this patch set be merged?

Regards
Haojian


From josh.wu at atmel.com  Thu May  9 03:34:53 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 9 May 2013 15:34:53 +0800
Subject: [PATCH 0/2] atmel_nand: remove cpu_is_xxx() in nand driver
Message-ID: <1368084895-18266-1-git-send-email-josh.wu@atmel.com>

avoid to use cpu_is_xxx() macro in driver, we use platform data and dts
for the different cpu.

Josh Wu (2):
  atmel_nand: at91/avr32/: Replace cpu_is_at32ap7000() with a nand
    platform data
  mtd: atmel_nand: add a new dt binding item for nand dma support

 .../devicetree/bindings/mtd/atmel-nand.txt         |    1 +
 arch/avr32/mach-at32ap/at32ap700x.c                |    3 +++
 drivers/mtd/nand/atmel_nand.c                      |   24 ++++++++------------
 include/linux/platform_data/atmel.h                |    4 ++++
 4 files changed, 17 insertions(+), 15 deletions(-)

-- 
1.7.9.5



From josh.wu at atmel.com  Thu May  9 03:34:54 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 9 May 2013 15:34:54 +0800
Subject: [PATCH 1/2] atmel_nand: at91/avr32/: Replace cpu_is_at32ap7000() with
 a nand platform data
In-Reply-To: <1368084895-18266-1-git-send-email-josh.wu@atmel.com>
References: <1368084895-18266-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368084895-18266-2-git-send-email-josh.wu@atmel.com>

The nand driver use cpu_is_at32ap7000() macro for a workaround. For the
multi-platform support, we will remove this cpu_is_xxx() macro.

This patch adds a boolean variable need_reset_workaround in structure
atmel_nand_data. Using this variable we can remove cpu_is_at32ap7000() macro.

Signed-off-by: Josh Wu <josh.wu at atmel.com>
Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
---
 arch/avr32/mach-at32ap/at32ap700x.c |    3 +++
 drivers/mtd/nand/atmel_nand.c       |   13 ++++++-------
 include/linux/platform_data/atmel.h |    3 +++
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index b323d8d..697ef58 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1979,6 +1979,9 @@ at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
 				ARRAY_SIZE(smc_cs3_resource)))
 		goto fail;
 
+	/* For at32ap7000, we use the reset workaround for nand driver */
+	data->need_reset_workaround = true;
+
 	if (platform_device_add_data(pdev, data,
 				sizeof(struct atmel_nand_data)))
 		goto fail;
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 2d23d29..7bf912b 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1174,10 +1174,9 @@ static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 	 * Workaround: Reset the parity registers before reading the
 	 * actual data.
 	 */
-	if (cpu_is_at32ap7000()) {
-		struct atmel_nand_host *host = chip->priv;
+	struct atmel_nand_host *host = chip->priv;
+	if (host->board.need_reset_workaround)
 		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
-	}
 
 	/* read the page */
 	chip->read_buf(mtd, p, eccsize);
@@ -1298,11 +1297,11 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
  */
 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
 {
-	if (cpu_is_at32ap7000()) {
-		struct nand_chip *nand_chip = mtd->priv;
-		struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd->priv;
+	struct atmel_nand_host *host = nand_chip->priv;
+
+	if (host->board.need_reset_workaround)
 		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
-	}
 }
 
 #if defined(CONFIG_OF)
diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
index 6a293b7..59f558d 100644
--- a/include/linux/platform_data/atmel.h
+++ b/include/linux/platform_data/atmel.h
@@ -71,6 +71,9 @@ struct atmel_nand_data {
 	u8		on_flash_bbt;		/* bbt on flash */
 	struct mtd_partition *parts;
 	unsigned int	num_parts;
+
+	/* default is false, only for at32ap7000 chip is true */
+	bool		need_reset_workaround;
 };
 
  /* Serial */
-- 
1.7.9.5



From josh.wu at atmel.com  Thu May  9 03:34:55 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 9 May 2013 15:34:55 +0800
Subject: [PATCH 2/2] mtd: atmel_nand: add a new dt binding item for nand dma
 support
In-Reply-To: <1368084895-18266-1-git-send-email-josh.wu@atmel.com>
References: <1368084895-18266-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368084895-18266-3-git-send-email-josh.wu@atmel.com>

This patch will set the nand dma support in dts. Since we will not use
cpu_is_xxx() in nand driver. We needn't include the mach/cpu.h any more.

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt         |    1 +
 drivers/mtd/nand/atmel_nand.c                      |   11 +++--------
 include/linux/platform_data/atmel.h                |    1 +
 3 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index d555421..b6eb484 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -15,6 +15,7 @@ Required properties:
   optional gpio and may be set to 0 if not present.
 
 Optional properties:
+- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 7bf912b..61d3869 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -43,8 +43,6 @@
 #include <linux/platform_data/atmel.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/cpu.h>
-
 static int use_dma = 1;
 module_param(use_dma, int, 0);
 
@@ -128,11 +126,6 @@ struct atmel_nand_host {
 
 static struct nand_ecclayout atmel_pmecc_oobinfo;
 
-static int cpu_has_dma(void)
-{
-	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
-}
-
 /*
  * Enable NAND.
  */
@@ -1336,6 +1329,8 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 
 	board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
 
+	board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
+
 	if (of_get_nand_bus_width(np) == 16)
 		board->bus_width_16 = 1;
 
@@ -1600,7 +1595,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 		nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
 	}
 
-	if (!cpu_has_dma())
+	if (!host->board.has_dma)
 		use_dma = 0;
 
 	if (use_dma) {
diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
index 59f558d..cea9f70 100644
--- a/include/linux/platform_data/atmel.h
+++ b/include/linux/platform_data/atmel.h
@@ -71,6 +71,7 @@ struct atmel_nand_data {
 	u8		on_flash_bbt;		/* bbt on flash */
 	struct mtd_partition *parts;
 	unsigned int	num_parts;
+	bool		has_dma;		/* support dma transfer */
 
 	/* default is false, only for at32ap7000 chip is true */
 	bool		need_reset_workaround;
-- 
1.7.9.5



From Ian.Campbell at citrix.com  Thu May  9 04:12:01 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 9 May 2013 09:12:01 +0100
Subject: [Xen-devel] [PATCH v3 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305081712390.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <518A7836.4030705@arm.com>
 <alpine.DEB.2.02.1305081712390.18865@kaball.uk.xensource.com>
Message-ID: <1368087121.17285.86.camel@zakaz.uk.xensource.com>

On Wed, 2013-05-08 at 18:03 +0100, Stefano Stabellini wrote:
> > What if we have Xen support enabled but don't run as a Xen guest?
> 
> That's fine as long as the Xen runstate_memory_area interface is
> available.
> Usually I am a great fun of feature flags, so that every feature can be
> dynamically enabled or disabled and an hypervisor interface can be only
> partially implemented.
> 
> However the runstate_memory_area is very old and I would consider it
> one of the core interfaces that need to be available in order to claim
> "Xen compatibility".

I think Marc meant "what if CONFIG_XEN=y but we are running on KVM?". In
that case we wont have set either of the paravirt_steal*_enabled static
keys and so the hook won't be called.

> > > +	static_key_slow_inc(&paravirt_steal_enabled);
> > > +	static_key_slow_inc(&paravirt_steal_rq_enabled);
> > > +


Ian.



From Ian.Campbell at citrix.com  Thu May  9 04:12:58 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 9 May 2013 09:12:58 +0100
Subject: [Xen-devel] [PATCH v3 1/4] xen: move xen_setup_runstate_info
 and get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305081858220.18865@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305081446580.18865@kaball.uk.xensource.com>
 <1368027714-14506-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130508175444.GB2800@phenom.dumpdata.com>
 <alpine.DEB.2.02.1305081858220.18865@kaball.uk.xensource.com>
Message-ID: <1368087178.17285.87.camel@zakaz.uk.xensource.com>

On Wed, 2013-05-08 at 19:13 +0100, Stefano Stabellini wrote:
> On Wed, 8 May 2013, Konrad Rzeszutek Wilk wrote:
> > On Wed, May 08, 2013 at 04:41:51PM +0100, Stefano Stabellini wrote:
> > > Changes in v2:
> > > - leave do_stolen_accounting in arch/x86/xen/time.c;
> > > - use the new common functions in arch/ia64/xen/time.c.
> > > 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > Acked-by: Ian Campbell <ian.campbell at citrix.com>
> > > CC: konrad.wilk at oracle.com
> > 
> > On the generic and x86 side it looks OK to me. I presume you did a sanity
> > check on x86 to make sure nothing was off?
> 
> Yep, it seems to work.
> However I couldn't even compile test the ia64 code.

The ia64 Xen on Linux support hasn't been touched since circa 2.6.35
AFAIK...

Ian.



From steve.capper at linaro.org  Thu May  9 04:15:05 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 9 May 2013 09:15:05 +0100
Subject: [RFC PATCH v2 08/11] ARM64: mm: Swap PTE_FILE and
 PTE_PROT_NONE bits.
In-Reply-To: <518A7A9F.9080105@codeaurora.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
 <518A7A9F.9080105@codeaurora.org>
Message-ID: <20130509081504.GA28545@linaro.org>

On Wed, May 08, 2013 at 12:17:35PM -0400, Christopher Covington wrote:
> Hi Steve,
> 
> On 05/08/2013 05:52 AM, Steve Capper wrote:
 
 [...]
> 
> > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> 
 [...]
> 
> > @@ -306,8 +306,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
> >  
> >  /*
> >   * Encode and decode a file entry:
> > - *	bits 0-1:	present (must be zero)
> > - *	bit  2:		PTE_FILE
> > + *	bits 0 & 2:	present (must be zero)
> 
> Consider using punctuation like "bits 0, 2" here to disambiguate from the
> binary and operation.
> 

Hi Christopher,
Thanks, I now have:
       bits 0, 2:      present (must both be zero)

Cheers,
-- 
Steve


From steve.capper at linaro.org  Thu May  9 04:22:36 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 9 May 2013 09:22:36 +0100
Subject: [RFC PATCH v2 08/11] ARM64: mm: Swap PTE_FILE and
 PTE_PROT_NONE bits.
In-Reply-To: <20130508164018.GF20820@mudshark.cambridge.arm.com>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
 <20130508164018.GF20820@mudshark.cambridge.arm.com>
Message-ID: <20130509082235.GB28545@linaro.org>

On Wed, May 08, 2013 at 05:40:19PM +0100, Will Deacon wrote:
> On Wed, May 08, 2013 at 10:52:40AM +0100, Steve Capper wrote:

 [...] 

> Can you update the comment describing swp entries too please? I *think* the
> __SWP_* defines can remain untouched, but the comment is now wrong.
> 
> Will

Ta Will, I've now changed the other comment.
The __SWP_* entries look ok to me. I'm going to run some swap tests though
to see if anything crops up.

Cheers,
-- 
Steve


From steve.capper at linaro.org  Thu May  9 04:27:13 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 9 May 2013 09:27:13 +0100
Subject: [RFC PATCH v2 07/11] ARM64: mm: Make PAGE_NONE pages read only
 and no-execute.
In-Reply-To: <20130508164341.GG20820@mudshark.cambridge.arm.com>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-8-git-send-email-steve.capper@linaro.org>
 <20130508164341.GG20820@mudshark.cambridge.arm.com>
Message-ID: <20130509082712.GA28801@linaro.org>

On Wed, May 08, 2013 at 05:43:41PM +0100, Will Deacon wrote:
> On Wed, May 08, 2013 at 10:52:39AM +0100, Steve Capper wrote:
 
> Whilst it's not strictly needed for pte_exec to work, I think you should
> include PTE_PXN in the PAGE_NONE definitions as well.

Agreed, it does look a little weird without it.

Cheers,
-- 
Steve


From linux at arm.linux.org.uk  Thu May  9 04:49:06 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 09:49:06 +0100
Subject: omap3430 fails to boot
Message-ID: <20130509084906.GL21614@n2100.arm.linux.org.uk>

I've not looked into the reason why yet, so this is a heads-up.  I
notice this morning that the LDP3430 failed to boot last night,
whereas it worked the previous night.  However, SDP4430 looks fine.

Nothing obvious in the diffstat between the two... but then the patch
between the two kernels is almost 1.5MB.  The arch/arm changes are
quite small though:

 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/Makefile                         |    4 +-
 arch/arm/boot/dts/xenvm-4.2.dts                    |   13 +
 arch/arm/include/asm/xen/hypercall.h               |    1 +
 arch/arm/mach-msm/last_radio_log.c                 |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c                |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c             |    2 +-
 arch/arm/mach-omap2/timer.c                        |    4 +
 arch/arm/mach-vexpress/v2m.c                       |    1 -
 arch/arm/mach-virt/virt.c                          |    1 +


From james.hogan at imgtec.com  Thu May  9 05:02:53 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Thu, 9 May 2013 10:02:53 +0100
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <518AE16D.5060501@codeaurora.org>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <518AE16D.5060501@codeaurora.org>
Message-ID: <518B663D.60806@imgtec.com>

On 09/05/13 00:36, Stephen Boyd wrote:
> On 04/19/13 09:28, James Hogan wrote:
>> This patchset adds support for automatic selection of the best parent
>> for a clock mux, i.e. the one which can provide the closest clock rate
>> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
>> so that it doesn't happen unless explicitly allowed.
>>
>> This works by way of adding a new op, determine_rate, similar to
>> round_rate but with an extra parameter to allow the clock driver to
>> optionally select a different parent clock. This is used in
>> clk_calc_new_rates to decide whether to initiate a set_parent operation.
> 
> Which tree is this based on? I get failures with git am on patch 2.
> 

It was based on v3.9-rc4.

Cheers
James



From linux at arm.linux.org.uk  Thu May  9 05:09:11 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 10:09:11 +0100
Subject: arch/arm/mach-omap2/id.c - IS_ERR_OR_NULL()
Message-ID: <20130509090911.GM21614@n2100.arm.linux.org.uk>

So, I eliminated all but a very few of these from arch/arm, and I notice
today that there's a new couple of instances introduced by:

commit 6770b211432564c562c856d612b43bbd42e4ab5e
Author: Ruslan Bilovol <ruslan.bilovol at ti.com>
Date:   Thu Feb 14 13:55:24 2013 +0200

    ARM: OMAP2+: Export SoC information to userspace

    In some situations it is useful for userspace to
    know some SoC-specific information. For example,
    this may be used for deciding what kernel module to
    use or how to better configure some settings etc.
    This patch exports OMAP SoC information to userspace
    using existing in Linux kernel SoC infrastructure.

    This information can be read under
    /sys/devices/socX directory

    Signed-off-by: Ruslan Bilovol <ruslan.bilovol at ti.com>
    [tony at atomide.com: updated for multiplatform changes]
    Signed-off-by: Tony Lindgren <tony at atomide.com>

+       soc_dev = soc_device_register(soc_dev_attr);
+       if (IS_ERR_OR_NULL(soc_dev)) {
+               kfree(soc_dev_attr);
+               return;
+       }
+
+       parent = soc_device_to_device(soc_dev);
+       if (!IS_ERR_OR_NULL(parent))
+               device_create_file(parent, &omap_soc_attr);

This is nonsense.  For the first, IS_ERR() is sufficient.  For the second,
tell me what error checking is required in the return value of this
function:

struct device *soc_device_to_device(struct soc_device *soc_dev)
{
        return &soc_dev->dev;
}

when you've already determined that the passed soc_dev is a valid pointer.
If you read the comments against the prototype:

/**
 * soc_device_to_device - helper function to fetch struct device
 * @soc: Previously registered SoC device container
 */
struct device *soc_device_to_device(struct soc_device *soc);

if "soc" is valid, it means the "previously registered SoC device container"
must have succeeded and that can only happen if the struct device has been
registered.  Ergo, there will always be a valid struct device pointer for
any registered SoC device container.  Therefore, if soc_device_register()
succeeds, then the return value from soc_device_to_device() will always be
valid and no error checking of it is required.

Simples.  The rule as ever applies here: get to know the APIs your using
and don't fumble around in the dark hoping that you'll get this stuff
right.


From marc.zyngier at arm.com  Thu May  9 05:32:12 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu, 09 May 2013 10:32:12 +0100
Subject: [PATCH] arm64: KVM: Add bits for specifying memory type in stage2
 PTE
In-Reply-To: <1368078813-16904-1-git-send-email-anup.patel@linaro.org>
References: <1368078813-16904-1-git-send-email-anup.patel@linaro.org>
Message-ID: <518B6D1C.3020603@arm.com>

[Looping in Catalin, as we just had an interesting discussion about this]

Hi Anup,

On 09/05/13 06:53, Anup Patel wrote:
> We cannot use existing stage1 PTE_ATTRINDX() macro for specifying
> stage2 memory type because stage1 ATTRINDX = PTE[4:2] and stage2
> MEMATTR = PTE[5:2].

You're right, this is a bug. But...

> This patch adds bit definetions for specifying device, noncacheable,
> writethrough, and writeback memory types in stage2 PTE and also uses
> it in PAGE_S2 and PAGE_S2_DEVICE.

... I have the feeling we don't need most of this:

Stage-2 memory attributes can only restrict what the guest puts in its
Stage-1. Which means that unless we really need to play some ugly tricks
on the guest (which we don't), it is probably best to leave everything
as Normal, Outer Write-Back, Inner Write-Back.

So I think the right fix is to get rid of of PAGE_S2_DEVICE, use PAGE_S2
for everything, and set MemAttr[3:0] to 0b1111.

I'll try that and cook a separate patch if it looks good enough (it is
likely to impact the 32bit code as well...).

> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> ---
>  arch/arm64/include/asm/pgtable-hwdef.h |    4 ++++
>  arch/arm64/include/asm/pgtable.h       |    6 ++++--
>  arch/arm64/mm/mmu.c                    |    9 +++++++++
>  3 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index c49cd61..555babb 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -73,6 +73,10 @@
>   */
>  #define PTE_S2_RDONLY		 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
>  #define PTE_S2_RDWR		 (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
> +#define PTE_S2_MT_DEVICE	 (_AT(pteval_t, 0x0) << 2) /* MemAttr[3:0] */
> +#define PTE_S2_MT_UNCACHED	 (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
> +#define PTE_S2_MT_WRITETHROUGH	 (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
> +#define PTE_S2_MT_WRITEBACK	 (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
>  
>  /*
>   * EL2/HYP PTE/PMD definitions
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 43ce724..3003fd0 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -60,6 +60,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
>  #define _PAGE_DEFAULT		PTE_TYPE_PAGE | PTE_AF
>  
>  extern pgprot_t pgprot_default;
> +extern pgprot_t pgprot_s2;
> +extern pgprot_t pgprot_s2_device;
>  
>  #define __pgprot_modify(prot,mask,bits) \
>  	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
> @@ -79,8 +81,8 @@ extern pgprot_t pgprot_default;
>  #define PAGE_HYP		_MOD_PROT(pgprot_default, PTE_HYP)
>  #define PAGE_HYP_DEVICE		_MOD_PROT(__pgprot(PROT_DEVICE_nGnRE), PTE_HYP)
>  
> -#define PAGE_S2			_MOD_PROT(pgprot_default, PTE_S2_RDONLY)
> -#define PAGE_S2_DEVICE		__pgprot_modify(__pgprot(PROT_DEVICE_nGnRE), PTE_PXN, PTE_S2_RDWR)
> +#define PAGE_S2			_MOD_PROT(pgprot_s2, PTE_USER | PTE_S2_RDONLY)
> +#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, PTE_USER | PTE_S2_RDWR)

Beware, you are reintroducing a bug I fixed a while ago (Stage-2 has no
USER bit).

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From jim_baxter at mentor.com  Thu May  9 05:35:15 2013
From: jim_baxter at mentor.com (Jim Baxter)
Date: Thu, 9 May 2013 10:35:15 +0100
Subject: [PATCH] net: fec: enable hardware checksum only on imx6q-fec
In-Reply-To: <1368083302-12516-1-git-send-email-shawn.guo@linaro.org>
References: <1368083302-12516-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <518B6DD3.1040201@mentor.com>

On 09/05/13 08:08, Shawn Guo wrote:
> Commit 4c09eed (net: fec: Enable imx6 enet checksum acceleration.)
> enables hardware checksum acceleration unconditionally for all fec
> variants.  This is inappropriate, because some variants like imx5 have
> no such support on hardware.  Consequently, fec is broken on these
> platforms.  Fix it by enabling hardware checksum only on imx6q-fec type
> of controllers.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Reviewed-by: Jim Baxter <jim_baxter at mentor.com>


From t.figa at samsung.com  Thu May  9 05:45:10 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 09 May 2013 11:45:10 +0200
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
In-Reply-To: <CAOesGMi=K4iJKjSk3RoynhiCMPPT98v5jADnqZ__TwX_YLw65Q@mail.gmail.com>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
 <CAD=FV=X2n+zHZ3frorwW7L1yybnWWK1=-rWMQJQFus3eNiFFeQ@mail.gmail.com>
 <CAOesGMi=K4iJKjSk3RoynhiCMPPT98v5jADnqZ__TwX_YLw65Q@mail.gmail.com>
Message-ID: <1614776.P66h1VoFPp@amdc1227>

Hi Doug, Olof,

On Wednesday 08 of May 2013 12:33:34 Olof Johansson wrote:
> Hi,
> 
> On Wed, May 8, 2013 at 11:48 AM, Doug Anderson <dianders at chromium.org> 
wrote:
> > Olof,
> > 
> > On Wed, May 8, 2013 at 11:19 AM, Olof Johansson <olof at lixom.net> wrote:
> >> Seems like this should be selected by the SoC (ARCH_EXYNOS5) instead
> >> of the board. Actually, I'm not sure we need the board Kconfig entry
> >> long-term; all boards will be dt-only.
> > 
> > Good point.  Hopefully someone at Samsung can work on removing the
> > board itself?  If you'd like me to take this on then let me know and I
> > can put it on my list.
> 
> Nothing stops you from doing that on your own. I tend to push back
> onto the maintainers to get them engaged in their own housekeeping,
> but anyone is free to :)
> 
> > I'm happy to resubmit my patch under ARCH_EXYNOS5.  I'll move the
> > exynos4 one at the same time.
> 
> Great.
> 
> > I'm going to make the assumption that PINCTRL_EXYNOS and
> > PINCTRL_EXYNOS5440 can happily coexist.  Certainly I've got both
> > defined in my tree right now and nothing blows up.  I haven't tested
> > on 5440 but things ought to be handled by "compatible" checks, right?
> 
> Yes, if they can't coexist then that's a bug.
> 
> > I'll also assume that eventually someone will move PINCTRL_EXYNOS5440
> > into PINCTRL_EXYNOS.  If PINCTRL_EXYNOS5440 won't eventually move
> > under PINCTRL_EXYNOS then it makes less sense to define PINCTRL_EXYNOS
> > for all exynos parts.
> 
> Yeah, it should -- this is just in transition since 5440 was first out
> of the gate with pinctrl.

AFAIK, Exynos5440 contains a completely different pin controller block, which 
is not compatible with pinctrl-samsung driver, so I don't see any point of 
moving it under PINCTRL_EXYNOS, which is currently used for Exynos 4210, 4x12 
and 5250, but will be also extended with driver data for S5PV210 as well.

I'd say that CPU_EXYNOS4210, SOC_EXYNOS4212, SOC_EXYNOS4412 and SOC_EXYNOS5250 
should select PINCTRL_EXYNOS and SOC_EXYNOS5440 should be left as is, 
selecting PINCTRL_EXYNOS5440.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Kernel and System Framework



From broonie at kernel.org  Thu May  9 05:51:43 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 9 May 2013 10:51:43 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <518A8E6C.6070907@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com>
 <518A8E6C.6070907@st.com>
Message-ID: <20130509095143.GB7478@sirena.org.uk>

On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:

Fix your mailer to word wrap within paragraphs.

> Ultimately the syscon_write use the regmap_update_bits, however we
> really want is the flexibility in using/referring the syscon
> registers/bits in both device-trees and non-device tree cases.

So what you're looking for here is some way to offload discovery of
register fields from the driver?

> The reason for these APIs, is the extent of syscon usage is very high
> in ST set-top-box parts.

> Without these new APIs, its very difficult to pass this information to
> the drivers.

I'm not 100% convinced that putting all this information into DT is a
good idea, and to the extent that it is sensible it feels like something
which might be useful with any device using register maps, not just
syscon.  For example many MFDs have similar needs - essentially the
system controllers are just a particular kind of MFD.  To me that says
that this should be outside syscon so other things can use it.
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From anup at brainfault.org  Thu May  9 06:03:29 2013
From: anup at brainfault.org (Anup Patel)
Date: Thu, 9 May 2013 15:33:29 +0530
Subject: [PATCH] arm64: KVM: Add bits for specifying memory type in stage2
 PTE
In-Reply-To: <518B6D1C.3020603@arm.com>
References: <1368078813-16904-1-git-send-email-anup.patel@linaro.org>
 <518B6D1C.3020603@arm.com>
Message-ID: <CAAhSdy35d3BKscxE=N5Ltb-_dnoHe-oy3YjsYwvk9qsh=t59_Q@mail.gmail.com>

On Thu, May 9, 2013 at 3:02 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> [Looping in Catalin, as we just had an interesting discussion about this]
>
> Hi Anup,
>
> On 09/05/13 06:53, Anup Patel wrote:
>> We cannot use existing stage1 PTE_ATTRINDX() macro for specifying
>> stage2 memory type because stage1 ATTRINDX = PTE[4:2] and stage2
>> MEMATTR = PTE[5:2].
>
> You're right, this is a bug. But...
>
>> This patch adds bit definetions for specifying device, noncacheable,
>> writethrough, and writeback memory types in stage2 PTE and also uses
>> it in PAGE_S2 and PAGE_S2_DEVICE.
>
> ... I have the feeling we don't need most of this:
>
> Stage-2 memory attributes can only restrict what the guest puts in its
> Stage-1. Which means that unless we really need to play some ugly tricks
> on the guest (which we don't), it is probably best to leave everything
> as Normal, Outer Write-Back, Inner Write-Back.
>
> So I think the right fix is to get rid of of PAGE_S2_DEVICE, use PAGE_S2
> for everything, and set MemAttr[3:0] to 0b1111.

IMHO, its good to have separate PAGE_S2_DEVICE because using this we
are enforcing strongly-ordered and non-cacheable memory for devices directly
accessed by guest (such as GIC CPU interface).

But ...

Having just PAGE_S2 will also work assuming that guest always uses
correct memory type for devices (specifically GIC CPU interface).

The most important thing on real HW is to have MemAttr = 0xF for proper
guest access to RAM.

>
> I'll try that and cook a separate patch if it looks good enough (it is
> likely to impact the 32bit code as well...).

Yes, 32bit code also has PAGE_S2_DEVICE macro.

I am fine with your suggestion. Go ahead with your patch.

>
>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>> ---
>>  arch/arm64/include/asm/pgtable-hwdef.h |    4 ++++
>>  arch/arm64/include/asm/pgtable.h       |    6 ++++--
>>  arch/arm64/mm/mmu.c                    |    9 +++++++++
>>  3 files changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
>> index c49cd61..555babb 100644
>> --- a/arch/arm64/include/asm/pgtable-hwdef.h
>> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
>> @@ -73,6 +73,10 @@
>>   */
>>  #define PTE_S2_RDONLY                 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
>>  #define PTE_S2_RDWR           (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
>> +#define PTE_S2_MT_DEVICE      (_AT(pteval_t, 0x0) << 2) /* MemAttr[3:0] */
>> +#define PTE_S2_MT_UNCACHED    (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
>> +#define PTE_S2_MT_WRITETHROUGH        (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
>> +#define PTE_S2_MT_WRITEBACK   (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
>>
>>  /*
>>   * EL2/HYP PTE/PMD definitions
>> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
>> index 43ce724..3003fd0 100644
>> --- a/arch/arm64/include/asm/pgtable.h
>> +++ b/arch/arm64/include/asm/pgtable.h
>> @@ -60,6 +60,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
>>  #define _PAGE_DEFAULT                PTE_TYPE_PAGE | PTE_AF
>>
>>  extern pgprot_t pgprot_default;
>> +extern pgprot_t pgprot_s2;
>> +extern pgprot_t pgprot_s2_device;
>>
>>  #define __pgprot_modify(prot,mask,bits) \
>>       __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
>> @@ -79,8 +81,8 @@ extern pgprot_t pgprot_default;
>>  #define PAGE_HYP             _MOD_PROT(pgprot_default, PTE_HYP)
>>  #define PAGE_HYP_DEVICE              _MOD_PROT(__pgprot(PROT_DEVICE_nGnRE), PTE_HYP)
>>
>> -#define PAGE_S2                      _MOD_PROT(pgprot_default, PTE_S2_RDONLY)
>> -#define PAGE_S2_DEVICE               __pgprot_modify(__pgprot(PROT_DEVICE_nGnRE), PTE_PXN, PTE_S2_RDWR)
>> +#define PAGE_S2                      _MOD_PROT(pgprot_s2, PTE_USER | PTE_S2_RDONLY)
>> +#define PAGE_S2_DEVICE               _MOD_PROT(pgprot_s2_device, PTE_USER | PTE_S2_RDWR)
>
> Beware, you are reintroducing a bug I fixed a while ago (Stage-2 has no
> USER bit).

My mistake. Thanks for pointing.

>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...
>
>
> _______________________________________________
> kvmarm mailing list
> kvmarm at lists.cs.columbia.edu
> https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm

Regards,
Anup


From tom.leiming at gmail.com  Thu May  9 06:07:56 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Thu, 9 May 2013 18:07:56 +0800
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
Message-ID: <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>

On Thu, May 9, 2013 at 1:18 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
>
> The most obvious fallback of using late_initcall_sync() also doesn't work
> since the deferred probing work initated during late_initcall() is done in
> a workqueue. So, frameworks that want to wait for all devices to finish
> probing during init will now have to wait for the deferred workqueue to
> finish it's work. This patch adds a wait_for_init_deferred_probe_done() API

flush_workqueue() has been added in deferred_probe_initcall(), so looks it
should be OK for your problem, doesn't it?


Thanks,
-- 
Ming Lei


From marc.zyngier at arm.com  Thu May  9 06:14:30 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu, 09 May 2013 11:14:30 +0100
Subject: [PATCH] arm64: KVM: Add bits for specifying memory type in stage2
 PTE
In-Reply-To: <CAAhSdy35d3BKscxE=N5Ltb-_dnoHe-oy3YjsYwvk9qsh=t59_Q@mail.gmail.com>
References: <1368078813-16904-1-git-send-email-anup.patel@linaro.org>
 <518B6D1C.3020603@arm.com>
 <CAAhSdy35d3BKscxE=N5Ltb-_dnoHe-oy3YjsYwvk9qsh=t59_Q@mail.gmail.com>
Message-ID: <518B7706.1080407@arm.com>

On 09/05/13 11:03, Anup Patel wrote:
> On Thu, May 9, 2013 at 3:02 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> [Looping in Catalin, as we just had an interesting discussion about this]
>>
>> Hi Anup,
>>
>> On 09/05/13 06:53, Anup Patel wrote:
>>> We cannot use existing stage1 PTE_ATTRINDX() macro for specifying
>>> stage2 memory type because stage1 ATTRINDX = PTE[4:2] and stage2
>>> MEMATTR = PTE[5:2].
>>
>> You're right, this is a bug. But...
>>
>>> This patch adds bit definetions for specifying device, noncacheable,
>>> writethrough, and writeback memory types in stage2 PTE and also uses
>>> it in PAGE_S2 and PAGE_S2_DEVICE.
>>
>> ... I have the feeling we don't need most of this:
>>
>> Stage-2 memory attributes can only restrict what the guest puts in its
>> Stage-1. Which means that unless we really need to play some ugly tricks
>> on the guest (which we don't), it is probably best to leave everything
>> as Normal, Outer Write-Back, Inner Write-Back.
>>
>> So I think the right fix is to get rid of of PAGE_S2_DEVICE, use PAGE_S2
>> for everything, and set MemAttr[3:0] to 0b1111.
> 
> IMHO, its good to have separate PAGE_S2_DEVICE because using this we
> are enforcing strongly-ordered and non-cacheable memory for devices directly
> accessed by guest (such as GIC CPU interface).
> 
> But ...
> 
> Having just PAGE_S2 will also work assuming that guest always uses
> correct memory type for devices (specifically GIC CPU interface).

That's the idea. If the guest screws up, we're not going to fix it up.

> The most important thing on real HW is to have MemAttr = 0xF for proper
> guest access to RAM.

Definitely.

>>
>> I'll try that and cook a separate patch if it looks good enough (it is
>> likely to impact the 32bit code as well...).
> 
> Yes, 32bit code also has PAGE_S2_DEVICE macro.
> 
> I am fine with your suggestion. Go ahead with your patch.

Just booted a v7 guest without PAGE_S2_device, and it seems happy
enough. I'll fix v8 accordingly and push the result out.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From mark.rutland at arm.com  Thu May  9 06:23:47 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Thu,  9 May 2013 11:23:47 +0100
Subject: [PATCHv2] net: smsc911x: don't artificially limit build
Message-ID: <1368095027-8448-1-git-send-email-mark.rutland@arm.com>

Currently the SMSC911X driver may only be built for a specific set of
architectures, being limited to do so by a Kconfig depends line. This
means that if a platform wishes to use the driver, its architecture must
be added to the list explicitly, introducing pointless churn.

This may have been due to the driver's use of the {read,write}s{b,w,l}
functions, which have since been replaced with the more standard
io{read,write}{8,16,32}_rep. We can instead depend on HAS_IOMEM, which
should prevent build issues while allowing the driver to be built for
currently unlisted architectures, including x86 and arm64.

This patch removes the explicit list of architectures from the driver's
depend line, and replaces it with a dependency on HAS_IOMEM.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Cc: David S. Miller <davem at davemloft.net>
Cc: Arnd Bergmann <arnd at arndb.de>
---
 drivers/net/ethernet/smsc/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig
index bb4c167..ff9e994 100644
--- a/drivers/net/ethernet/smsc/Kconfig
+++ b/drivers/net/ethernet/smsc/Kconfig
@@ -97,7 +97,7 @@ config SMC911X
 
 config SMSC911X
 	tristate "SMSC LAN911x/LAN921x families embedded ethernet support"
-	depends on (ARM || SUPERH || BLACKFIN || MIPS || MN10300)
+	depends on HAS_IOMEM
 	select CRC32
 	select NET_CORE
 	select MII
-- 
1.8.1.1



From srinivas.kandagatla at st.com  Thu May  9 06:17:37 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 09 May 2013 11:17:37 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <201305082148.10933.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de> <518A8C1D.3090600@st.com>
 <201305082148.10933.arnd@arndb.de>
Message-ID: <518B77C1.70107@st.com>

Hi Arnd,
Thankyou for extending the discussion.

On 08/05/13 20:48, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> the pinctrl driver calls syconf_claim(np, "st,alt-control) to get a
>> field and then do a read/write on the field.
>>
>> Just in pinctrl driver we use around 50-100 sysconf registers scatters
>> across different groups.
>>
>> Without these new APIs, its very difficult to pass this information to
>> the drivers.
> But are those necessarily things you would configure using DT?
In last comment.
>
> If there are so many registers that are shared between mutliple
> subsystems, maybe using drivers/mfd/syscon for that is taking things
> further than you should, since it is unlike what any of the other
> SoC families need from syscon.
I agree, my initial approach was having a dedicated driver specific to
ST syscon, however syscon seems to do things very much similar to what
we want, so I have integrated those 3 functions in syscon.
Am happy to go back with my first approach of adding ST specific syscon
driver if no one is actually going to benefit with such a change to
syscon driver.

>
> Can you describe how your syscon registers are laid out?
On STiH416 SOC we have 9 SYSCONF(aka System Configuration
Registers)named banks/groups, each bank has its own memory map.
Each sysconf bank has number of 32 bit registers which vary from bank to
bank, like sysconf bank "sbc" has range from SYSTEM_CONFIG0 to
SYSTEM_CONFIG999 where as  sysconf bank "front" has range of
SYSTEM_CONFIG1000 to SYSTEM_CONFIG1999 and so on.

Each register is assigned with a unique SYCONF number, example:
SYSTEM_CONFIG100, SYSTEM_CONFIG101 , .. and so on.
Each sysconf contains bits of the IP configurations wired-up to the
sysconf register bits.

As example:

- Each pinctrl entry for set of 8 pins uses around 8-10 sysconfig
register to control pinconf and pin functions.
- IPs like Ethernet have few bit like Ethernet-Mode selection external
or internal phyclk wired up to bits in sysconf registers,
- Few clocks are controlled by sysconf registers.
- Reset to IPs are wired up to bits of sysconf same registers.
- ARM core soft reset is wired up to the sysconf registers...
And most of the IPs have similar requirements ......

Total layout of the sysconf changes per SOC, and the bit arrangements
aswell, however the core IP(pinctrl, etherenet ...) and logic to drive
those bits remains exactly same.

As the code remains the same, the information about the hardware
configuration and offsets to the registers are passed by device trees
using the node properties.

In general the requirements of the sysconf support to the SOC/driver
support is.
1> It should be able to read/write a sysconf register bits without
having to "if" each SOC in the code. So that code is totally abstracted.
Which is currently achieved by passing the information from the device
trees and the driver just uses the property to get it.
2> The infrastructure should protect the claimed registers from
over-writing by other drivers. We do this by claim-read/write-release
style API.
3> The driver should be able to set a group of sysconf registers bits to
a particular values before initialises the IP. I was thinking of doing
this in a same way as pinctrl state.

Any suggestion is most appreciated?

Thanks,
srini

> Which subsystems beside pinctrl need to directly interact
> with it? Is there any logical structure in it or do you just
> have tons of bits scattered around an MMIO area?
>
> 	Arnd
>



From mark.rutland at arm.com  Thu May  9 06:26:50 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Thu, 9 May 2013 11:26:50 +0100
Subject: [PATCHv2] net: smsc911x: don't artificially limit build
In-Reply-To: <1368095027-8448-1-git-send-email-mark.rutland@arm.com>
References: <1368095027-8448-1-git-send-email-mark.rutland@arm.com>
Message-ID: <20130509102650.GC8258@e106331-lin.cambridge.arm.com>

This should of course be PATCH, not PATCHv2.

I blame my shell's command history completion.

Mark.

On Thu, May 09, 2013 at 11:23:47AM +0100, Mark Rutland wrote:
> Currently the SMSC911X driver may only be built for a specific set of
> architectures, being limited to do so by a Kconfig depends line. This
> means that if a platform wishes to use the driver, its architecture must
> be added to the list explicitly, introducing pointless churn.
> 
> This may have been due to the driver's use of the {read,write}s{b,w,l}
> functions, which have since been replaced with the more standard
> io{read,write}{8,16,32}_rep. We can instead depend on HAS_IOMEM, which
> should prevent build issues while allowing the driver to be built for
> currently unlisted architectures, including x86 and arm64.
> 
> This patch removes the explicit list of architectures from the driver's
> depend line, and replaces it with a dependency on HAS_IOMEM.
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Arnd Bergmann <arnd at arndb.de>
> ---
>  drivers/net/ethernet/smsc/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig
> index bb4c167..ff9e994 100644
> --- a/drivers/net/ethernet/smsc/Kconfig
> +++ b/drivers/net/ethernet/smsc/Kconfig
> @@ -97,7 +97,7 @@ config SMC911X
>  
>  config SMSC911X
>  	tristate "SMSC LAN911x/LAN921x families embedded ethernet support"
> -	depends on (ARM || SUPERH || BLACKFIN || MIPS || MN10300)
> +	depends on HAS_IOMEM
>  	select CRC32
>  	select NET_CORE
>  	select MII
> -- 
> 1.8.1.1
> 


From lorenzo.pieralisi at arm.com  Thu May  9 06:33:59 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu,  9 May 2013 11:33:59 +0100
Subject: [RFC PATCH v3] ARM CCI support
Message-ID: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>

This patch is an updated of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/166173.html

main changes in v3:
 - Changed init to early_initcall and added code to deal with init calls
   ordering issues
 - Removed platform driver infrastructure, replaced with DT layer
 - Added missing pointer flushing
 - Removed useless includes
 - Implemented MPIDR stashing
 - Added basic functions to initialize and carry out CPU ports look-ups
 - fixed !CONFIG_ARM_CCI compile issue

main changes in v2:
 - Changed way masters are connected to CCI slave ports in DT
   # now every master has to declare a phandle to a CCI control IF
 - Fixed warning split on different lines
 - Added comments to disable function
 - Moved driver to non-hotpluggable API (registration and probing bundled
   together)
 - Upgraded cache flushing API
 - Reworked the driver to use devm primitives
 - Added disable/enable by index API
 - Fixed port enable and added macro for snoops/DVM control

ARM multi-cluster systems rely on the cache coherent interconnect (CCI) to
support inter-cluster cache coherency and distributed virtual memory (DVM)
messaging.

CCI kernel driver requires tweaks to the kernel and device tree
bindings in order to link specific resources to groups of logical CPUs
so that resources can be associated to specific cpu sets (slave ports can
be associated with a set of CPUs which are part of a cluster).

CCI slave ports must be associated with specific bus masters in the system so
that whenever a CCI operation is requested for a specific master (ie disable
its CCI slave port, read its PMU counters) the association can be carried out
dynamically in the OS through dynamically built data structures.
Bus masters in the system connected to CCI ports must define device tree
properties, as described in the documentation contained in the patch, in order
to explicitly connect ports and allow the OS to build up the required data
structures.

The current CCI DT bindings define the CCI address space as the same one
as the root device tree node, which means that the CCI bus can address the
entire address space visible to CPUs.

Lorenzo Pieralisi (1):
  drivers: bus: add ARM CCI support

 Documentation/devicetree/bindings/arm/cci.txt | 161 ++++++++++
 drivers/bus/Kconfig                           |   7 +
 drivers/bus/Makefile                          |   2 +
 drivers/bus/arm-cci.c                         | 420 ++++++++++++++++++++++++++
 include/linux/arm-cci.h                       |  61 ++++
 5 files changed, 651 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cci.txt
 create mode 100644 drivers/bus/arm-cci.c
 create mode 100644 include/linux/arm-cci.h

-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Thu May  9 06:34:00 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu,  9 May 2013 11:34:00 +0100
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>

On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.

This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.

Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.

CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.

Documentation describing the CCI DT bindings is provided with the patch.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 Documentation/devicetree/bindings/arm/cci.txt | 161 ++++++++++
 drivers/bus/Kconfig                           |   7 +
 drivers/bus/Makefile                          |   2 +
 drivers/bus/arm-cci.c                         | 420 ++++++++++++++++++++++++++
 include/linux/arm-cci.h                       |  61 ++++
 5 files changed, 651 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cci.txt
 create mode 100644 drivers/bus/arm-cci.c
 create mode 100644 include/linux/arm-cci.h

diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
new file mode 100644
index 0000000..384b460
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -0,0 +1,161 @@
+=======================================================
+ARM CCI cache coherent interconnect binding description
+=======================================================
+
+ARM multi-cluster systems maintain intra-cluster coherency through a
+cache coherent interconnect (CCI) that is capable of monitoring bus
+transactions and manage coherency, TLB invalidations and memory barriers.
+
+It allows snooping and distributed virtual memory message broadcast across
+clusters, through memory mapped interface, with a global control register
+space and multiple sets of interface control registers, one per slave
+interface.
+
+Bindings for the CCI node follow the ePAPR standard, available from:
+
+www.power.org/documentation/epapr-version-1-1/
+
+with the addition of the bindings described in this document which are
+specific to ARM.
+
+* CCI interconnect node
+
+	Description: Describes a CCI cache coherent Interconnect component
+
+	Node name must be "cci".
+	Node's parent must be the root node /, and the address space visible
+	through the CCI interconnect is the same as the one seen from the
+	root node (ie from CPUs perspective as per DT standard).
+	Every CCI node has to define the following properties:
+
+	- compatible
+		Usage: required
+		Value type: <string>
+		Definition: must be set to
+			"arm,cci-400"
+
+	- reg
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property. Specifies base physical
+			    address of CCI control registers common to all
+			    interfaces.
+
+	- ranges:
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property. Follow rules in the ePAPR for
+			    hierarchical bus addressing. CCI interfaces
+			    addresses refer to the parent node addressing
+			    scheme to declare their register bases.
+
+	CCI interconnect node can define the following child nodes:
+
+	- CCI control interface nodes
+
+		Node name must be "slave-if".
+		Parent node must be CCI interconnect node.
+
+		A CCI interface node must contain the following properties:
+		- interface-type:
+			Usage: required
+			Value type: <string>
+			Definition: must be set to one of {"ace", "ace-lite"}
+				    depending on the interface type the node
+				    represents.
+
+		- reg:
+			Usage: required
+			Value type: <prop-encoded-array>
+			Definition: the base address and size of the
+				    corresponding interface programming
+				    registers.
+
+* CCI interconnect bus masters
+
+	Description: masters in the device tree connected to a CCI port
+		     (inclusive of CPUs and their cpu nodes).
+
+	A CCI interconnect bus master node must contain the following
+	properties:
+
+	- cci-control-port:
+		Usage: required
+		Value type: <phandle>
+		Definition: a phandle containing the CCI control interface node
+			    the master is connected to.
+
+Example:
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		CPU0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			cci-control-port = <&cci_control1>;
+			reg = <0x0>;
+		};
+
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			cci-control-port = <&cci_control1>;
+			reg = <0x1>;
+		};
+
+		CPU2: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			cci-control-port = <&cci_control2>;
+			reg = <0x100>;
+		};
+
+		CPU3: cpu at 101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			cci-control-port = <&cci_control2>;
+			reg = <0x101>;
+		};
+
+	};
+
+	dma0: dma at 3000000 {
+		compatible = "arm,pl330", "arm,primecell";
+		cci-control-port = <&cci_control0>;
+		reg = <0x0 0x3000000 0x0 0x1000>;
+		interrupts = <10>;
+		#dma-cells = <1>;
+		#dma-channels = <8>;
+		#dma-requests = <32>;
+	};
+
+	cci at 2c090000 {
+		compatible = "arm,cci";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x2c090000 0 0x1000>;
+		ranges = <0x0 0x0 0x2c090000 0x6000>;
+
+		cci_control0 : slave-if at 1000 {
+			interface-type = "ace-lite";
+			reg = <0x1000 0x1000>;
+		};
+
+		cci_control1 : slave-if at 4000 {
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+
+		cci_control2 : slave-if at 5000 {
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
+		};
+	};
+
+This CCI node corresponds to a CCI component whose control registers sits
+at address 0x000000002c090000.
+CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
+CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
+CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 0f51ed6..38ea85c 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -19,4 +19,11 @@ config OMAP_INTERCONNECT
 
 	help
 	  Driver to enable OMAP interconnect error handling driver.
+
+config ARM_CCI
+	bool "ARM CCI driver support"
+	depends on ARM
+	help
+	  Driver supporting the CCI cache coherent interconnect for ARM
+	  platforms.
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 45d997c..2bd9947 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
 # Interconnect bus driver for OMAP SoCs.
 obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
+# CCI cache coherent interconnect for ARM platforms
+obj-$(CONFIG_ARM_CCI)		+= arm-cci.o
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
new file mode 100644
index 0000000..000102f
--- /dev/null
+++ b/drivers/bus/arm-cci.c
@@ -0,0 +1,420 @@
+/*
+ * CCI cache coherent interconnect driver
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+
+#define DRIVER_NAME		"CCI"
+
+#define CCI_PORT_CTRL		0x0
+#define CCI_CTRL_STATUS		0xc
+
+#define CCI_ENABLE_SNOOP_REQ	0x1
+#define CCI_ENABLE_DVM_REQ	0x2
+#define CCI_ENABLE_REQ		(CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
+
+struct cci_nb_ports {
+	unsigned int nb_ace;
+	unsigned int nb_ace_lite;
+};
+
+enum cci_ace_port_type {
+	ACE_INVALID_PORT = 0x0,
+	ACE_PORT,
+	ACE_LITE_PORT,
+};
+
+struct cci_ace_port {
+	void __iomem *base;
+	enum cci_ace_port_type type;
+	struct device_node *dn;
+};
+
+static struct cci_ace_port *ports;
+static unsigned int nb_cci_ports;
+
+static void __iomem *cci_ctrl_base;
+
+struct cpu_port {
+	u64 mpidr;
+	u32 port;
+};
+/*
+ * Use the port MSB as valid flag, shift can be made dynamic
+ * by computing number of bits required for port indexes.
+ * Code disabling CCI cpu ports runs with D-cache invalidated
+ * and SCTLR bit clear so data accesses must be kept to a minimum
+ * to improve performance; for now shift is left static to
+ * avoid one more data access while disabling the CCI port.
+ */
+#define PORT_VALID_SHIFT	31
+#define PORT_VALID		(0x1 << PORT_VALID_SHIFT)
+
+static inline void init_cpu_port(struct cpu_port *port, u32 index, u32 mpidr)
+{
+	port->port = PORT_VALID | index;
+	port->mpidr = mpidr;
+}
+
+static inline bool cpu_port_is_valid(struct cpu_port *port)
+{
+	return !!(port->port & PORT_VALID);
+}
+
+static inline bool cpu_port_match(struct cpu_port *port, u32 mpidr)
+{
+	return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
+}
+
+static struct cpu_port cpu_port[NR_CPUS];
+
+/**
+ * __cci_ace_get_port - Function to retrieve the port index connected to
+ *			a cpu or device.
+ *
+ * @dn: device node of the device to look-up
+ * @type: port type
+ *
+ * Return value:
+ *	- CCI port index if success
+ *	- -ENODEV if failure
+ */
+static int __cci_ace_get_port(struct device_node *dn, int type)
+{
+	int i;
+	bool ace_match;
+	struct device_node *cci_portn;
+
+	cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
+	for (i = 0; i < nb_cci_ports; i++) {
+		ace_match = ports[i].type == type;
+		if (ace_match && cci_portn == ports[i].dn)
+			return i;
+	}
+	return -ENODEV;
+}
+
+int cci_ace_get_port(struct device_node *dn)
+{
+	return __cci_ace_get_port(dn, ACE_LITE_PORT);
+}
+EXPORT_SYMBOL_GPL(cci_ace_get_port);
+
+static void __init cci_ace_init_ports(void)
+{
+	int port, ac, cpu;
+	u64 hwid;
+	const u32 *cell;
+	struct device_node *cpun, *cpus;
+
+	cpus = of_find_node_by_path("/cpus");
+	if (WARN(!cpus, "Missing cpus node, bailing out\n"))
+		return;
+
+	if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
+		ac = of_n_addr_cells(cpus);
+
+	/*
+	 * Port index look-up speeds up the function disabling ports by CPU,
+	 * since the logical to port index mapping is done once and does
+	 * not change after system boot.
+	 * The stashed index array is initialized for all possible CPUs
+	 * at probe time.
+	 */
+	for_each_child_of_node(cpus, cpun) {
+		if (of_node_cmp(cpun->type, "cpu"))
+			continue;
+		cell = of_get_property(cpun, "reg", NULL);
+		if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
+			continue;
+
+		hwid = of_read_number(cell, ac);
+		cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
+
+		if (cpu < 0 || !cpu_possible(cpu))
+			continue;
+		port = __cci_ace_get_port(cpun, ACE_PORT);
+		if (port < 0)
+			continue;
+
+		init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
+	}
+
+	for_each_possible_cpu(cpu) {
+		WARN(!cpu_port_is_valid(&cpu_port[cpu]),
+			"CPU %u does not have an associated CCI port\n",
+			cpu);
+	}
+}
+/*
+ * Functions to enable/disable a CCI interconnect slave port
+ *
+ * They are called by low-level power management code to disable slave
+ * interfaces snoops and DVM broadcast.
+ * Since they may execute with cache data allocation disabled and
+ * after the caches have been cleaned and invalidated the functions provide
+ * no explicit locking since they may run with D-cache disabled, so normal
+ * cacheable kernel locks based on ldrex/strex may not work.
+ * Locking has to be provided by BSP implementations to ensure proper
+ * operations.
+ */
+
+/**
+ * cci_port_control() - function to control a CCI port
+ *
+ * @port: index of the port to setup
+ * @enable: if true enables the port, if false disables it
+ */
+static void notrace cci_port_control(unsigned int port, bool enable)
+{
+	void __iomem *base = ports[port].base;
+
+	writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
+	/*
+	 * This function is called from power down procedures
+	 * and must not execute any instruction that might
+	 * cause the processor to be put in a quiescent state
+	 * (eg wfi). Hence, cpu_relax() can not be added to this
+	 * read loop to optimize power, since it might hide possibly
+	 * disruptive operations.
+	 */
+	while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
+			;
+}
+
+/**
+ * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
+ *			       reference
+ *
+ * @mpidr: mpidr of the CPU whose CCI port should be disabled
+ *
+ * Disabling a CCI port for a CPU implies disabling the CCI port
+ * controlling that CPU cluster. Code disabling CPU CCI ports
+ * must make sure that the CPU running the code is the last active CPU
+ * in the cluster ie all other CPUs are quiescent in a low power state.
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port look-up failure
+ */
+int notrace cci_disable_port_by_cpu(u64 mpidr)
+{
+	int cpu;
+	bool is_valid;
+	for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
+		is_valid = cpu_port_is_valid(&cpu_port[cpu]);
+		if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
+			cci_port_control(cpu_port[cpu].port, false);
+			return 0;
+		}
+	}
+	return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
+
+/**
+ * __cci_control_port_by_device() - function to control a CCI port by device
+ *				    reference
+ *
+ * @dn: device node pointer of the device whose CCI port should be
+ *      controlled
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port look-up failure
+ */
+int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
+{
+	int port;
+
+	if (!dn)
+		return -ENODEV;
+
+	port = __cci_ace_get_port(dn, ACE_LITE_PORT);
+	if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
+				dn->full_name))
+		return -ENODEV;
+	cci_port_control(port, enable);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
+
+/**
+ * __cci_control_port_by_index() - function to control a CCI port by port index
+ *
+ * @port: port index previously retrieved with cci_ace_get_port()
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port index out of range
+ *	-EPERM if operation carried out on an ACE PORT
+ */
+int notrace __cci_control_port_by_index(u32 port, bool enable)
+{
+	if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
+		return -ENODEV;
+	/*
+	 * CCI control for ports connected to CPUS is extremely fragile
+	 * and must be made to go through a specific and controlled
+	 * interface (ie cci_disable_port_by_cpu(); control by general purpose
+	 * indexing is therefore disabled for ACE ports.
+	 */
+	if (ports[port].type == ACE_PORT)
+		return -EPERM;
+
+	cci_port_control(port, enable);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
+
+static const struct cci_nb_ports cci400_ports = {
+	.nb_ace = 2,
+	.nb_ace_lite = 3
+};
+
+static const struct of_device_id arm_cci_matches[] = {
+	{.compatible = "arm,cci-400", .data = &cci400_ports },
+	{},
+};
+
+static int __init cci_probe(void)
+{
+	struct cci_nb_ports const *cci_config;
+	int ret, i, nb_ace = 0, nb_ace_lite = 0;
+	struct device_node *np, *cp;
+	const char *match_str;
+	bool is_ace;
+
+	np = of_find_matching_node(NULL, arm_cci_matches);
+	if (!np)
+		return -ENODEV;
+
+	cci_config = of_match_node(arm_cci_matches, np)->data;
+	if (!cci_config)
+		return -ENODEV;
+
+	nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
+
+	ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
+	if (!ports)
+		return -ENOMEM;
+
+	cci_ctrl_base = of_iomap(np, 0);
+
+	if (!cci_ctrl_base) {
+		WARN(1, "unable to ioremap CCI ctrl\n");
+		ret = -ENXIO;
+		goto memalloc_err;
+	}
+
+	for_each_child_of_node(np, cp) {
+		i = nb_ace + nb_ace_lite;
+
+		if (i >= nb_cci_ports)
+			break;
+
+		if (of_property_read_string(cp, "interface-type",
+					&match_str)) {
+			WARN(1, "node %s missing interface-type property\n",
+				  cp->full_name);
+			continue;
+		}
+		is_ace = strcmp(match_str, "ace") == 0;
+		if (!is_ace && strcmp(match_str, "ace-lite")) {
+			WARN(1, "node %s containing invalid interface-type property, skipping it\n",
+					cp->full_name);
+			continue;
+		}
+
+		ports[i].base = of_iomap(cp, 0);
+
+		if (!ports[i].base) {
+			WARN(1, "unable to ioremap CCI port %d\n", i);
+			continue;
+		}
+
+		if (is_ace) {
+			if (WARN_ON(nb_ace >= cci_config->nb_ace))
+				continue;
+			ports[i].type = ACE_PORT;
+			++nb_ace;
+		} else {
+			if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
+				continue;
+			ports[i].type = ACE_LITE_PORT;
+			++nb_ace_lite;
+		}
+		ports[i].dn = cp;
+	}
+
+	 /* initialize a stashed array of ACE ports to speed-up look-up */
+	cci_ace_init_ports();
+
+	/*
+	 * Multi-cluster systems may need this data when non-coherent, during
+	 * cluster power-up/power-down. Make sure it reaches main memory.
+	 */
+	sync_cache_w(&cci_ctrl_base);
+	sync_cache_w(&ports);
+	sync_cache_w(&cpu_port);
+	__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
+	pr_info("ARM CCI driver probed\n");
+	return 0;
+
+memalloc_err:
+
+	kfree(ports);
+	return ret;
+}
+
+static int cci_init_status = -EAGAIN;
+static DEFINE_MUTEX(cci_probing);
+
+static int __init cci_init(void)
+{
+	if (cci_init_status != -EAGAIN)
+		return cci_init_status;
+
+	mutex_lock(&cci_probing);
+	if (cci_init_status == -EAGAIN)
+		cci_init_status = cci_probe();
+	mutex_unlock(&cci_probing);
+	return cci_init_status;
+}
+
+/*
+ * To sort out early init calls ordering a helper function is provided to
+ * check if the CCI driver has beed initialized. Function check if the driver
+ * has been initialized, if not it calls the init function that probes
+ * the driver and updates the return value.
+ */
+bool __init cci_probed(void)
+{
+	return cci_init() == 0;
+}
+EXPORT_SYMBOL_GPL(cci_probed);
+
+early_initcall(cci_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ARM CCI support");
diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
new file mode 100644
index 0000000..79d6edf
--- /dev/null
+++ b/include/linux/arm-cci.h
@@ -0,0 +1,61 @@
+/*
+ * CCI cache coherent interconnect support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_ARM_CCI_H
+#define __LINUX_ARM_CCI_H
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct device_node;
+
+#ifdef CONFIG_ARM_CCI
+extern bool cci_probed(void);
+extern int cci_ace_get_port(struct device_node *dn);
+extern int cci_disable_port_by_cpu(u64 mpidr);
+extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
+extern int __cci_control_port_by_index(u32 port, bool enable);
+#else
+static inline bool cci_probed(void) { return false; }
+static inline int cci_ace_get_port(struct device_node *dn)
+{
+	return -ENODEV;
+}
+static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
+static inline int __cci_control_port_by_device(struct device_node *dn,
+					       bool enable)
+{
+	return -ENODEV;
+}
+static inline int __cci_control_port_by_index(u32 port, bool enable)
+{
+	return -ENODEV;
+}
+#endif
+#define cci_disable_port_by_device(dev) \
+	__cci_control_port_by_device(dev, false)
+#define cci_enable_port_by_device(dev) \
+	__cci_control_port_by_device(dev, true)
+#define cci_disable_port_by_index(dev) \
+	__cci_control_port_by_index(dev, false)
+#define cci_enable_port_by_index(dev) \
+	__cci_control_port_by_index(dev, true)
+
+#endif
-- 
1.8.2.2




From b32955 at freescale.com  Thu May  9 06:38:45 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 9 May 2013 18:38:45 +0800
Subject: [PATCH 1/5] ARM: dts: imx6q: add a new device node for ecspi1
In-Reply-To: <1368070143-1655-2-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
 <1368070143-1655-2-git-send-email-b32955@freescale.com>
Message-ID: <518B7CB5.5040808@freescale.com>

? 2013?05?09? 11:28, Huang Shijie ??:
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..5601026 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -59,6 +59,17 @@
>  	soc {
>  		aips-bus at 02000000 { /* AIPS1 */
>  			spba-bus at 02000000 {
> +				ecspi1: ecspi at 02008000 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> +					reg = <0x02008000 0x4000>;
> +					interrupts = <0 31 0x04>;
> +					clocks = <&clks 112>, <&clks 112>;
> +					clock-names = "ipg", "per";
> +					status = "disabled";
> +				};
> +
>  				ecspi5: ecspi at 02018000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
Please ignore this single patch.

the eCSPI1 has been added in the imx6qdl.dtsi.

so this patch is redundant.

thanks
Huang Shijie



From yefremov.denis at gmail.com  Thu May  9 06:36:52 2013
From: yefremov.denis at gmail.com (Denis Efremov)
Date: Thu,  9 May 2013 14:36:52 +0400
Subject: [PATCH 14/21] arm64: delay: remove inline marking of EXPORT_SYMBOL
 functions
In-Reply-To: <1368086241-9357-1-git-send-email-yefremov.denis@gmail.com>
References: <1368086241-9357-1-git-send-email-yefremov.denis@gmail.com>
Message-ID: <1368095819-11011-3-git-send-email-yefremov.denis@gmail.com>

EXPORT_SYMBOL and inline directives are contradictory to each other.
The patch fixes this inconsistency.

Found by Linux Driver Verification project (linuxtesting.org).

Signed-off-by: Denis Efremov <yefremov.denis at gmail.com>
---
 arch/arm64/lib/delay.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c
index dad4ec9..368ca15 100644
--- a/arch/arm64/lib/delay.c
+++ b/arch/arm64/lib/delay.c
@@ -33,7 +33,7 @@ void __delay(unsigned long cycles)
 }
 EXPORT_SYMBOL(__delay);
 
-inline void __const_udelay(unsigned long xloops)
+void __const_udelay(unsigned long xloops)
 {
 	unsigned long loops;
 
-- 
1.8.1.4



From grant.likely at secretlab.ca  Thu May  9 06:39:22 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 9 May 2013 11:39:22 +0100
Subject: [PATCH 0/2] Early printk support for virtio console devices.
In-Reply-To: <20130508141706.GF2703@arm.com>
References: <CAAHg+Hj0tySbzUGnoFE9ybVYP291B-i8-Ck1EkwD57t8yG5wwg@mail.gmail.com>
 <C52CCDD4-D8FB-4AD6-B83D-3B5251A7A0F5@suse.de>
 <87sj27xxjr.fsf@rustcorp.com.au>
 <CAFEAcA9h8iSYfTBtf6n+Vk5sDtBR2yB2oafRxikHoWbKt0VRUw@mail.gmail.com>
 <87ip2wr8tp.fsf@rustcorp.com.au>
 <CAFEAcA_=BTXVdkN0WmajxVSjbDrmxc5z65hCbxr=7TqJVsE9EA@mail.gmail.com>
 <87txmfo0rl.fsf@rustcorp.com.au>
 <CAFEAcA9jBSpN2p9ZaU+_gX41Ke3nvpSKVrWV8Rioy_ioadKCgg@mail.gmail.com>
 <5189234D.3040208@codeaurora.org>
 <CAFEAcA-eSB=_UT0-L7o=2o6JGv0WkXZv5UPxPVqLRxjUZQegFA@mail.gmail.com>
 <20130508141706.GF2703@arm.com>
Message-ID: <CACxGe6tP=mos_j6gphK6gY=xCHLN4xtNKUpkzG4UHDzv=+fFUQ@mail.gmail.com>

On Wed, May 8, 2013 at 3:17 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
> On Tue, May 07, 2013 at 04:58:23PM +0100, Peter Maydell wrote:
>> On 7 May 2013 16:52, Christopher Covington <cov at codeaurora.org> wrote:
>> This mixes up "information that the user provides to the
>> kernel" (ie configuration) with "information that QEMU or
>> kvmtool should provide to the kernel" (ie hardware
>> description), and would require QEMU/kvmtool to parse
>> the user's commandline tool to figure out if they
>> needed to override it or edit it (or alternatively,
>> would require the user to know internal details of
>> QEMU/kvmtool's address map for the guest). I think it
>> would be nicer to keep them separate.
>
> I'm not sure it's worth it, the earlyprintk is meant for debugging the
> early kernel booting code, not for general use (you have the normal
> console for this). Someone doing platform port should know the address
> of the uart and pass the right information on the kernel command line to
> help debug early booting issues.
>
> But if someone comes up with some bindings, I won't reject the patch.

Nicolas and I have tossed back and forth the idea of having a trivial
binding in the DT which specifies a couple of physical addresses and a
mask; one write register, one status register, and the mask to say
which bit to care about in the status. Basically the bare minimum to
say "here is something that will output to an already set up serial
device" without any reference to what it actually is. Something like
that would theoretically work with any device that implements or
emulates a UART write register. The thinking is that if it is trivial
to parse then it becomes more useful as an early printk target and
usable by the zImage wrapper (arm32 bit of course). Neither of us ever
followed up on it though.

g.


From catalin.marinas at arm.com  Thu May  9 06:39:40 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 9 May 2013 11:39:40 +0100
Subject: [PATCH 14/21] arm64: delay: remove inline marking of
 EXPORT_SYMBOL functions
In-Reply-To: <1368095819-11011-3-git-send-email-yefremov.denis@gmail.com>
References: <1368086241-9357-1-git-send-email-yefremov.denis@gmail.com>
 <1368095819-11011-3-git-send-email-yefremov.denis@gmail.com>
Message-ID: <20130509103939.GD668@arm.com>

On Thu, May 09, 2013 at 11:36:52AM +0100, Denis Efremov wrote:
> EXPORT_SYMBOL and inline directives are contradictory to each other.
> The patch fixes this inconsistency.
> 
> Found by Linux Driver Verification project (linuxtesting.org).
> 
> Signed-off-by: Denis Efremov <yefremov.denis at gmail.com>
> ---
>  arch/arm64/lib/delay.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c
> index dad4ec9..368ca15 100644
> --- a/arch/arm64/lib/delay.c
> +++ b/arch/arm64/lib/delay.c
> @@ -33,7 +33,7 @@ void __delay(unsigned long cycles)
>  }
>  EXPORT_SYMBOL(__delay);
>  
> -inline void __const_udelay(unsigned long xloops)
> +void __const_udelay(unsigned long xloops)
>  {
>  	unsigned long loops;

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From yefremov.denis at gmail.com  Thu May  9 06:36:59 2013
From: yefremov.denis at gmail.com (Denis Efremov)
Date: Thu,  9 May 2013 14:36:59 +0400
Subject: [PATCH 21/21] ARM: remove inline marking of EXPORT_SYMBOL functions
In-Reply-To: <1368086241-9357-1-git-send-email-yefremov.denis@gmail.com>
References: <1368086241-9357-1-git-send-email-yefremov.denis@gmail.com>
Message-ID: <1368095819-11011-10-git-send-email-yefremov.denis@gmail.com>

EXPORT_SYMBOL and inline directives are contradictory to each other.
The patch fixes this inconsistency.

Found by Linux Driver Verification project (linuxtesting.org).

Signed-off-by: Denis Efremov <yefremov.denis at gmail.com>
---
 arch/arm/mach-sa1100/jornada720_ssp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index b143c46..737842c 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -33,7 +33,7 @@ static unsigned long jornada_ssp_flags;
  * we need to reverse all data we receive from the mcu due to its physical location
  * returns : 01110111 -> 11101110
  */
-u8 inline jornada_ssp_reverse(u8 byte)
+u8 jornada_ssp_reverse(u8 byte)
 {
 	return
 		((0x80 & byte) >> 7) |
-- 
1.8.1.4



From fabio.baltieri at linaro.org  Thu May  9 07:08:08 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu,  9 May 2013 13:08:08 +0200
Subject: [PATCH] mfd: ab8500-sysctrl: Always enable pm_power_off handler
Message-ID: <1368097688-17858-1-git-send-email-fabio.baltieri@linaro.org>

AB8500 sysctrl driver implements a pm_power_off handler, but that is
currently not registered until a specific platform data field is
enabled.

This patch drops the platform data field and always registers
ab8500_power_off if no other pm_power_off handler was defined before,
and also introduces the necessary cleanup code in the driver's remove
function.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 drivers/mfd/ab8500-sysctrl.c      | 6 +++++-
 include/linux/mfd/abx500/ab8500.h | 2 --
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/ab8500-sysctrl.c b/drivers/mfd/ab8500-sysctrl.c
index eadae4d..8e0dae5 100644
--- a/drivers/mfd/ab8500-sysctrl.c
+++ b/drivers/mfd/ab8500-sysctrl.c
@@ -193,7 +193,7 @@ static int ab8500_sysctrl_probe(struct platform_device *pdev)
 
 	sysctrl_dev = &pdev->dev;
 
-	if (plat->pm_power_off)
+	if (!pm_power_off)
 		pm_power_off = ab8500_power_off;
 
 	pdata = plat->sysctrl;
@@ -227,6 +227,10 @@ static int ab8500_sysctrl_probe(struct platform_device *pdev)
 static int ab8500_sysctrl_remove(struct platform_device *pdev)
 {
 	sysctrl_dev = NULL;
+
+	if (pm_power_off == ab8500_power_off)
+		pm_power_off = NULL;
+
 	return 0;
 }
 
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index b5780fd..6c119b5 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -374,7 +374,6 @@ struct ab8500_sysctrl_platform_data;
 /**
  * struct ab8500_platform_data - AB8500 platform data
  * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
- * @pm_power_off: Should machine pm power off hook be registered or not
  * @init: board-specific initialization after detection of ab8500
  * @num_regulator_reg_init: number of regulator init registers
  * @regulator_reg_init: regulator init registers
@@ -383,7 +382,6 @@ struct ab8500_sysctrl_platform_data;
  */
 struct ab8500_platform_data {
 	int irq_base;
-	bool pm_power_off;
 	void (*init) (struct ab8500 *);
 	int num_regulator_reg_init;
 	struct ab8500_regulator_reg_init *regulator_reg_init;
-- 
1.8.2



From stephen.gallimore at st.com  Thu May  9 07:09:25 2013
From: stephen.gallimore at st.com (Stephen GALLIMORE)
Date: Thu, 9 May 2013 13:09:25 +0200
Subject: [RFC 5/8] ARM:stih41x: Add STiH415 SOC support
In-Reply-To: <201305082055.31081.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081818.01927.arnd@arndb.de>
 <A3BF01DB4A606149A4C20C4C4C808F6C3189E576E2@SAFEX1MAIL1.st.com>
 <201305082055.31081.arnd@arndb.de>
Message-ID: <A3BF01DB4A606149A4C20C4C4C808F6C3189F99E90@SAFEX1MAIL1.st.com>

> If you have a better solution, or a way to generalize this that would 
> make sense for the ARM architecture as a whole, then we are more than 
> happy to change.
>
>No idea, sorry. Upon closer inspection I wonder if your code actually does anything to the hardware that causes it to wake up on an interrupt.

You are correct that it does not affect the hardware and as such it may be entirely the wrong approach to put this code here. However, as drivers or subsystems are expected to call enable/disable_irq_ wake() when appropriate it seemed a reasonable place to do it and of course in the future when we add in support for the other suspend states this is also expected to do something with the system standby controller, as is the case on other platforms. But we concede that in this first minimal version that it may look a little out of place.

To quickly summarize the issue we were trying to address, the new freeze state suspends the drivers but then rather than calling the arch suspend code simply goes to sleep on a wake queue. It is relying on wakeup source interrupt handlers actually being run (this is not the case in the other "traditional" suspend states) and that the driver or some subsystem code called as part of the driver's interrupt processing will call pm_wakeup_event() which signals the freeze wake queue and causes the generic suspend code to start going through its wakeup path. But the driver suspend code will suspend the calling of IRQ handlers, dpm_suspend_noirq() calls suspend_device_irqs(), except for those with the NO_SUSPEND flag set.

Now it is possible that we have simply tried to finesse the solution too much and that using the ASC serial device as a wakeup source was an unfortunate place to start, because most wakeup devices on a set top box have a single instance, e.g. the IR device for the remote control and you probably always want them to be a wakeup source. Maybe it would not have really mattered that much in the end if the ASC driver simply installed the interrupts for all UART ports with the flag, regardless of if the port was going to be used to wake up or not; but as I said in my previous response that solution left us feeling a bit uncomfortable which is why we went looking for another approach that was independent of the device driver and hooking into enable/disable_irq_wake() at the architecture level seemed more appropriate once we noticed it being used elsewhere. However, until you put it out there for comment it is hard to know if you have backed the right horse.

Regards,
-stephen



From holt at sgi.com  Thu May  9 07:20:48 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 9 May 2013 06:20:48 -0500
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <518A9A83.5010306@zytor.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508103956.GA7677@gmail.com>
 <20130508182007.GO18614@n2100.arm.linux.org.uk>
 <518A9A83.5010306@zytor.com>
Message-ID: <20130509112048.GT3672@sgi.com>

On Wed, May 08, 2013 at 11:33:39AM -0700, H. Peter Anvin wrote:
> On 05/08/2013 11:20 AM, Russell King - ARM Linux wrote:
> > 
> > Let's try to get the meaning back.  On ARM, these are taken from the first
> > letter of the 'reboot=' command line argument, which was initially either
> > "hard" or "soft".  This refers to whether we hit some bit of hardware
> > which physically asserts some reset line in the system, or merely vector
> > the CPU via the reset vector (for some systems, this is the only
> > possibility.)
> > 
> > Then PXA happened, and there was a need for some platforms there to do
> > a hardware restart via toggling a GPIO output, which would then ultimately
> > assert the system reset line.  So we then added the "gpio" mode as well.
> > reboot via toggling a GPIO output.  So we then ended up with "gpio" as
> > well.
> > 
> > So, on ARM, the modes are: hard, soft, gpio, which get translated to a
> > single letter by the simple parsing code:
> > 
> > static char reboot_mode = 'h';
> > 
> > int __init reboot_setup(char *str)
> > {
> >         reboot_mode = str[0];
> >         return 1;
> > }
> > 
> > __setup("reboot=", reboot_setup);
> > 
> > Now, arguably, "hard" and "soft" have an entirely different meaning to
> > "warm" and "cold" in the normal parlence.  A "warm" reboot involves the
> > system doing less tasks at restart than a "cold" reboot.  This is not
> > necessarily the case between 'hard' and 'soft'.
> > 
> > So, while I don't entirely agree with mapping "hard" to "cold" and
> > "soft" to "warm", I guess for the sake of generalisation it's okay.
> > However, thinking about the future, if ARM becomes more server-like,
> > we might also want "cold" and "warm" reboot identifiers too.
> > 
> > I think the solution to this would be to have the new generic code
> > parse the entire argument, not just the first letter - certainly for
> > the 's' case.  If it's the x86 version, it'll be "s<number>".  If
> > it's the ARM version, it should be "soft".
> > 
> 
> The s<number> thing is pretty awful, admittedly (it was supposed to be
> smp<number>, but the parser, rather than *allowing* only the first
> letter, seems to *require* that it is only the first letter.)
> 
> The problem I see is that we don't know what we'll break if we change
> it, but Ingo seems to think it doesn't matter so much.
> 
> For the boolean letter argument, we could simply have the parser set a
> bitmask of the letters seen; the x86 "s" argument is clearly an outlier.
> 
> We could handle it in a generic exception by looking for s<digit> or
> smp<digit>, which will not match ARM's "soft" argument.  I suspect we
> can worry about other argument-carrying options in a generic fashion
> when the need arises; I would personally prefer the "subtag:argument"
> format used by libata &c for that, and the presence of a ':' would be
> indicative.

Is there really a reason for having this conglomeration of disparate
options all merged together?  Why can't we go with having a separate
param(reboot_cpu, int, 0644); so it can be controlled via sysfs as
well?  If we are breaking the reboot=s## syntax, why not become a
little more standardized with the reboot_cpu?

Robin


From holt at sgi.com  Thu May  9 07:29:16 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 9 May 2013 06:29:16 -0500
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130508135029.ffbeefa6b8154bee31e7bbbe@linux-foundation.org>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508135029.ffbeefa6b8154bee31e7bbbe@linux-foundation.org>
Message-ID: <20130509112916.GU3672@sgi.com>

On Wed, May 08, 2013 at 01:50:29PM -0700, Andrew Morton wrote:
> On Tue,  7 May 2013 09:39:55 -0500 Robin Holt <holt at sgi.com> wrote:
> 
> > Merge together the unicore32, arm, and x86 reboot= command line
> > parameter handling.
> > 
> > ...
> >
> > +static int __init reboot_setup(char *str)
> > +{
> > +	for (;;) {
> > +		/*
> > +		 * Having anything passed on the command line via
> > +		 * reboot= will cause us to disable DMI checking
> > +		 * below.
> > +		 */
> > +		reboot_default = 0;
> > +
> > +		switch (*str) {
> > +#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
> > +		case 'w':
> > +			reboot_mode = REBOOT_WARM;
> > +			break;
> > +
> > +		case 'c':
> > +			reboot_mode = REBOOT_COLD;
> > +			break;
> > +
> > +#ifdef CONFIG_SMP
> > +		case 's':
> > +			if (isdigit(*(str+1))) {
> > +				reboot_cpu = (int) (*(str+1) - '0');
> > +				if (isdigit(*(str+2)))
> > +					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
> > +			}
> 
> Boy, that's some weird stuff.
> 
> What's wrong with doing
> 
> 			if (isdigit(str[1])) {
> 				reboot_cpu = str[1] - '0';
> 				if (isdigit(str[2]))
> 					reboot_cpu = reboot_cpu * 10 +
> 							str[2] - '0';
> 			}
> 
> ?
> 
> But it's still nonsense - we should eliminate its
> you-have-less-than-101-CPUs restriction by using, you know, atoi().

I had an earlier version which I must have dropped which handled the
larger parsing, but I do like your suggestion of using atoi.  I will
submit a -v9 in a few hours.

Robin


From holt at sgi.com  Thu May  9 07:29:41 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 9 May 2013 06:29:41 -0500
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130508182304.GP18614@n2100.arm.linux.org.uk>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508182304.GP18614@n2100.arm.linux.org.uk>
Message-ID: <20130509112941.GV3672@sgi.com>

On Wed, May 08, 2013 at 07:23:05PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 07, 2013 at 09:39:55AM -0500, Robin Holt wrote:
> > +		case 's':
> > +			reboot_mode = REBOOT_WARM;
> > +		case 'h':
> > +			reboot_mode = REBOOT_COLD;
> > +		case 'g':
> > +			reboot_mode = REBOOT_GPIO;
> 
> Further to Ingo's comments, also note that the above is broken.  Any
> of s,h,g will result in REBOOT_GPIO being set which is clearly wrong.

I couldn't be more of an idiot.  I will fix it in -v9.

Robin


From pranavkumar at linaro.org  Thu May  9 07:40:11 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Thu,  9 May 2013 17:10:11 +0530
Subject: [PATCH] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
Message-ID: <1368099611-4738-1-git-send-email-pranavkumar@linaro.org>

This patch does following fixes:

1. Make HCR_* flags as unsigned long long constants
Reason : By default, compiler assumes numeric constants as
signed hence sign extending it when assigned to unsigned variable
such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
HCR_CD making entire guest memory non-cacheable. On real HW, this
breaks Stage2 ttbl walks and also breaks VirtIO.

2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
---
 arch/arm64/include/asm/kvm_arm.h |   73 +++++++++++++++++++-------------------
 1 file changed, 37 insertions(+), 36 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 8ced0ca..0a951db 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -18,44 +18,45 @@
 #ifndef __ARM64_KVM_ARM_H__
 #define __ARM64_KVM_ARM_H__
 
+#include <linux/const.h>
 #include <asm/types.h>
 
 /* Hyp Configuration Register (HCR) bits */
-#define HCR_ID		(1 << 33)
-#define HCR_CD		(1 << 32)
+#define HCR_ID		(_AC(0x1, ULL) << 33)
+#define HCR_CD		(_AC(0x1, ULL) << 32)
 #define HCR_RW_SHIFT	31
-#define HCR_RW		(1 << HCR_RW_SHIFT)
-#define HCR_TRVM	(1 << 30)
-#define HCR_HCD		(1 << 29)
-#define HCR_TDZ		(1 << 28)
-#define HCR_TGE		(1 << 27)
-#define HCR_TVM		(1 << 26)
-#define HCR_TTLB	(1 << 25)
-#define HCR_TPU		(1 << 24)
-#define HCR_TPC		(1 << 23)
-#define HCR_TSW		(1 << 22)
-#define HCR_TAC		(1 << 21)
-#define HCR_TIDCP	(1 << 20)
-#define HCR_TSC		(1 << 19)
-#define HCR_TID3	(1 << 18)
-#define HCR_TID2	(1 << 17)
-#define HCR_TID1	(1 << 16)
-#define HCR_TID0	(1 << 15)
-#define HCR_TWE		(1 << 14)
-#define HCR_TWI		(1 << 13)
-#define HCR_DC		(1 << 12)
-#define HCR_BSU		(3 << 10)
-#define HCR_BSU_IS	(1 << 10)
-#define HCR_FB		(1 << 9)
-#define HCR_VA		(1 << 8)
-#define HCR_VI		(1 << 7)
-#define HCR_VF		(1 << 6)
-#define HCR_AMO		(1 << 5)
-#define HCR_IMO		(1 << 4)
-#define HCR_FMO		(1 << 3)
-#define HCR_PTW		(1 << 2)
-#define HCR_SWIO	(1 << 1)
-#define HCR_VM		(1)
+#define HCR_RW		(_AC(0x1, ULL) << HCR_RW_SHIFT)
+#define HCR_TRVM	(_AC(0x1, ULL) << 30)
+#define HCR_HCD		(_AC(0x1, ULL) << 29)
+#define HCR_TDZ		(_AC(0x1, ULL) << 28)
+#define HCR_TGE		(_AC(0x1, ULL) << 27)
+#define HCR_TVM		(_AC(0x1, ULL) << 26)
+#define HCR_TTLB	(_AC(0x1, ULL) << 25)
+#define HCR_TPU		(_AC(0x1, ULL) << 24)
+#define HCR_TPC		(_AC(0x1, ULL) << 23)
+#define HCR_TSW		(_AC(0x1, ULL) << 22)
+#define HCR_TAC		(_AC(0x1, ULL) << 21)
+#define HCR_TIDCP	(_AC(0x1, ULL) << 20)
+#define HCR_TSC		(_AC(0x1, ULL) << 19)
+#define HCR_TID3	(_AC(0x1, ULL) << 18)
+#define HCR_TID2	(_AC(0x1, ULL) << 17)
+#define HCR_TID1	(_AC(0x1, ULL) << 16)
+#define HCR_TID0	(_AC(0x1, ULL) << 15)
+#define HCR_TWE		(_AC(0x1, ULL) << 14)
+#define HCR_TWI		(_AC(0x1, ULL) << 13)
+#define HCR_DC		(_AC(0x1, ULL) << 12)
+#define HCR_BSU		(_AC(0x3, ULL) << 10)
+#define HCR_BSU_IS	(_AC(0x1, ULL) << 10)
+#define HCR_FB		(_AC(0x1, ULL) << 9)
+#define HCR_VA		(_AC(0x1, ULL) << 8)
+#define HCR_VI		(_AC(0x1, ULL) << 7)
+#define HCR_VF		(_AC(0x1, ULL) << 6)
+#define HCR_AMO		(_AC(0x1, ULL) << 5)
+#define HCR_IMO		(_AC(0x1, ULL) << 4)
+#define HCR_FMO		(_AC(0x1, ULL) << 3)
+#define HCR_PTW		(_AC(0x1, ULL) << 2)
+#define HCR_SWIO	(_AC(0x1, ULL) << 1)
+#define HCR_VM		(_AC(0x1, ULL))
 
 /*
  * The bits we set in HCR:
@@ -111,9 +112,9 @@
 #define VTCR_EL2_SH0_MASK	(3 << 12)
 #define VTCR_EL2_SH0_INNER	(3 << 12)
 #define VTCR_EL2_ORGN0_MASK	(3 << 10)
-#define VTCR_EL2_ORGN0_WBWA	(3 << 10)
+#define VTCR_EL2_ORGN0_WBWA	(1 << 10)
 #define VTCR_EL2_IRGN0_MASK	(3 << 8)
-#define VTCR_EL2_IRGN0_WBWA	(3 << 8)
+#define VTCR_EL2_IRGN0_WBWA	(1 << 8)
 #define VTCR_EL2_SL0_MASK	(3 << 6)
 #define VTCR_EL2_SL0_LVL1	(1 << 6)
 #define VTCR_EL2_T0SZ_MASK	0x3f
-- 
1.7.9.5



From grant.likely at secretlab.ca  Thu May  9 07:50:46 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 9 May 2013 12:50:46 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
Message-ID: <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>

On Thu, May 9, 2013 at 11:07 AM, Ming Lei <tom.leiming at gmail.com> wrote:
> On Thu, May 9, 2013 at 1:18 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
>>
>> The most obvious fallback of using late_initcall_sync() also doesn't work
>> since the deferred probing work initated during late_initcall() is done in
>> a workqueue. So, frameworks that want to wait for all devices to finish
>> probing during init will now have to wait for the deferred workqueue to
>> finish it's work. This patch adds a wait_for_init_deferred_probe_done() API
>
> flush_workqueue() has been added in deferred_probe_initcall(), so looks it
> should be OK for your problem, doesn't it?

It looks like Saravana is using a kernel that already does that based
on object bb5645e from the diff. So if he is still having problem,
then there is probably another deferred probe that is triggered after
the deferred probe lateinitcall is executed. It would be good to know
what driver is getting deferred past clearing the queue. Or has this
been rebased from an earlier kernel? It may no longer be necessary.

However, if a device that shuts down resources after init has
completed and then cannot turn those resources back on when another
driver requests them then it sounds like there is a bigger design
problem. We're in a hotplug world and most of the time a driver cannot
assume that a resource will never get requested after initcalls have
completed. It sounds like a design bug in the driver if it cannot
handle that use case.

g.


From srinivas.kandagatla at st.com  Thu May  9 07:58:01 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 09 May 2013 12:58:01 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <20130509095143.GB7478@sirena.org.uk>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com> <518A8E6C.6070907@st.com>
 <20130509095143.GB7478@sirena.org.uk>
Message-ID: <518B8F49.5020902@st.com>

On 09/05/13 10:51, Mark Brown wrote:
> On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
> 
> Fix your mailer to word wrap within paragraphs.
> 
Sorry about that.
>> Ultimately the syscon_write use the regmap_update_bits, however we
>> really want is the flexibility in using/referring the syscon
>> registers/bits in both device-trees and non-device tree cases.
> 
> So what you're looking for here is some way to offload discovery of
> register fields from the driver?

Exactly,

As the System configuration registers change per each SOC, and the
logic/code to drive still remain same across SOCs.

It makes sense to abstract the information of sysconf register and its
offsets from the driver, as we do not want to change the driver per each
SOC.

> 
>> The reason for these APIs, is the extent of syscon usage is very high
>> in ST set-top-box parts.
> 
>> Without these new APIs, its very difficult to pass this information to
>> the drivers.
> 
> I'm not 100% convinced that putting all this information into DT is a
> good idea,

Currently, we have two bits of information which come from device trees.
1> The syscon bank/group definition itself.
2> syscon register offsets and bits information to the drivers.

These are the 2 things which keep changing per each SOC.

There is no other way to pass this information to the drivers other than
passing them as part of their own device node and syscon node.

>  and to the extent that it is sensible it feels like something
> which might be useful with any device using register maps, not just
> syscon.

If you think this is going to be useful for other drivers, Am happy to
move this out of syscon to regmap something like adding
of_regmap_field_claim/regmap_field_claim/regmap_field_read/regmap_field_write/regmap_field_release
functions.

so any exiting drivers can still use the old syscon API to get the
regmap instance.
Alternatively they can use the new regmap APIs directly.

regmap_field_claim to claim bits of the register
of_regmap_field_claim DT version of reg_map_field_claim.
regmap_field_write to write to bits of register
regmap_field_read to bit of the register.
regmap_field_release to release the bits of the register.

For DT version it might involve adding new member to struct
regmap_config to lookup regmap by phandle, so that regmap can get hold
of regmap instance from device tree phandle.
syscon driver already does this in syscon_regmap_lookup_by_phandle()

On the device tree side it will look like:
syscfg_sbc:syscon at fe600000{
	compatible	= "syscon";
	reg		= <0xfe600000 0x1000>;
};

node {
	property-1 = <&syscfg_sbc 10 0 31>;
};

property has "phandle", register_offset, lsb, msb.

On the driver side, it can just use the API's like

field = of_regmap_field_claim(np, "property-1");
regmap_field_write(field, val);
regmap_field_release(field);

All this involves is very minimal code change in syscon and a new APIs
and DT awareness into regmap.

What do you think?

Thanks,
srini

>  For example many MFDs have similar needs - essentially the
> system controllers are just a particular kind of MFD.  To me that says
> that this should be outside syscon so other things can use it.

> 



From marc.zyngier at arm.com  Thu May  9 08:35:14 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu, 09 May 2013 13:35:14 +0100
Subject: [PATCH] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
In-Reply-To: <1368099611-4738-1-git-send-email-pranavkumar@linaro.org>
References: <1368099611-4738-1-git-send-email-pranavkumar@linaro.org>
Message-ID: <518B9802.1080505@arm.com>

Hi Pranav,

On 09/05/13 12:40, Pranavkumar Sawargaonkar wrote:
> This patch does following fixes:
> 
> 1. Make HCR_* flags as unsigned long long constants
> Reason : By default, compiler assumes numeric constants as
> signed hence sign extending it when assigned to unsigned variable
> such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
> HCR_CD making entire guest memory non-cacheable. On real HW, this
> breaks Stage2 ttbl walks and also breaks VirtIO.

Ah. Nice one. I fixed a couple of similar bugs already, but didn't
notice that one yet, for obvious reasons...

I'll probably rewrite that patch to use the UL(x) macro instead of
_AC(), as we don't need to have an unsigned long long, and that makes
the code look much nicer (sort of).

> 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.

Blah. Copy paste. Fucks me all the time.

> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> ---
>  arch/arm64/include/asm/kvm_arm.h |   73 +++++++++++++++++++-------------------
>  1 file changed, 37 insertions(+), 36 deletions(-)

Thanks a lot,

	M.
-- 
Jazz is not dead. It just smells funny...



From lee.jones at linaro.org  Thu May  9 08:50:55 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 May 2013 13:50:55 +0100
Subject: [PATCH] serial: pl011: protect attribute read from NULL platform data
 struct
Message-ID: <1368103855-28363-1-git-send-email-lee.jones@linaro.org>

It's completely feasible that platform data will be empty i.e. when
booting with Device Tree with no device AUXDATA. So we must protect
it's use in these use-cases, or risk a kernel Oops.

Cc: Russell King <linux at arm.linux.org.uk>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Jiri Slaby <jslaby at suse.cz>
Cc: linux-serial at vger.kernel.org
Cc: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
*******                                                        *******
If this issue has not already been fixed, this patch should be applied
during the v3.10 -rc:s, as it fixes a serious bug which was introduced
in the merge-window.
*******                                                        *******

 drivers/tty/serial/amba-pl011.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 8ab70a6..e2774f9 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -332,7 +332,7 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *
 		dmaengine_slave_config(chan, &rx_conf);
 		uap->dmarx.chan = chan;
 
-		if (plat->dma_rx_poll_enable) {
+		if (plat && plat->dma_rx_poll_enable) {
 			/* Set poll rate if specified. */
 			if (plat->dma_rx_poll_rate) {
 				uap->dmarx.auto_poll_rate = false;
-- 
1.7.10.4



From robert.jarzmik at free.fr  Thu May  9 08:59:47 2013
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Thu, 09 May 2013 14:59:47 +0200
Subject: GPIO sysfs : set a wake source
Message-ID: <87fvxwia0s.fsf@free.fr>

Hi Linus,

I was thinking on how to remove all "gpio_request()" from my board code
(arch/arm/mach-pxa/mioa701.c).

I have a small difficulty with the functionality provided by gpiolib in
userspace. This is what I need :
 - define a gpio as an input
 - define this gpio to be an interrupt source
 - define this interrupt to be a wake-up source

In kernel, I had : gpio_request(), request_irq(), and gpio_set_wake() (in
mioa701, this ends up in gsm_on_irq()).

In userspace I have :
 - echo 113 > /sys/class/gpio/export
 - echo in > /sys/class/gpio/gpio113/direction
 - echo both > /sys/class/gpio/gpio113/edge

And here, I don't know how to trigger a call to gpio_set_wake(113, 1). Do you
provide that API somewhere in sysfs that I didn't find ? Because that's what I
need to obliterate gpio calls from my board code.

Cheers.

-- 
Robert


From lee.jones at linaro.org  Thu May  9 09:01:00 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 9 May 2013 14:01:00 +0100
Subject: [PATCH 28/63] ARM: ux500: Stop passing UART's platform data for
 Device Tree boots
In-Reply-To: <CACRpkdYCABo0AULsiUgwm3g=906iKzp_ZDFKLj=HgDbNK9mNUQ@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-29-git-send-email-lee.jones@linaro.org>
 <CACRpkdYCABo0AULsiUgwm3g=906iKzp_ZDFKLj=HgDbNK9mNUQ@mail.gmail.com>
Message-ID: <20130509130100.GA12156@gmail.com>

On Fri, 03 May 2013, Linus Walleij wrote:

> On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > It was required to pass DMA channel configuration information to the
> > UART driver before the new DMA API was in place. Now that it is, and
> > is fully compatible with Device Tree we can stop doing that.
> >
> > Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> I can't apply this as it is clearly dependent on a patch to
> drivers/tty/serial/amba-pl011.c that is not yet upstream.

It is now.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From holt at sgi.com  Thu May  9 09:01:20 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 9 May 2013 08:01:20 -0500
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130509112048.GT3672@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508103956.GA7677@gmail.com>
 <20130508182007.GO18614@n2100.arm.linux.org.uk>
 <518A9A83.5010306@zytor.com> <20130509112048.GT3672@sgi.com>
Message-ID: <20130509130120.GW3672@sgi.com>

Is the what everyone is expecting?

Robin

---

>From ebed0c3119bc35248bdfdc4d9966cf339d8621b7 Mon Sep 17 00:00:00 2001
From: Robin Holt <holt at sgi.com>
Date: Wed, 24 Apr 2013 06:18:53 -0500
Subject: [PATCH -v9 11/11] Move arch/x86 reboot= handling to generic kernel.

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---
Changes since -v8
 - Add missing break statements.

 - Change parsing so #ifdef's are no longer needed.

 - Switch to using simple_strtoul to make parsing cleaner.
---
 Documentation/kernel-parameters.txt      |  14 +++-
 arch/arm/kernel/process.c                |  10 ---
 arch/unicore32/kernel/process.c          |  10 ---
 arch/x86/include/asm/emergency-restart.h |  12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |   2 +-
 arch/x86/kernel/reboot.c                 | 111 +------------------------------
 include/linux/reboot.h                   |  17 +++++
 kernel/reboot.c                          |  80 +++++++++++++++++++++-
 8 files changed, 111 insertions(+), 145 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c3bfacb..b2945ce 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2677,9 +2677,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old] | h[ard] | s[oft] | g[pio]] \
+				[[,]s[mp]#### \
+				[[,]b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[[,]f[orce]
+			Where reboot_mode is one of warm (soft) or cold (hard) or gpio,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 58c0d7a..304b102 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_WARM;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 9dc6e48..fdb8e79 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_WARM;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index d42e3b2..563ed91 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,22 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode = REBOOT_COLD;
-enum reboot_type reboot_type = BOOT_ACPI;
-int reboot_force;
-
-/*
- * This variable is used privately to keep track of whether or not
- * reboot_type is still set to its default value (i.e., reboot= hasn't
- * been set on the command line).  This is needed so that we can
- * suppress DMI scanning for reboot quirks.  Without it, it's
- * impossible to override a faulty reboot quirk without recompiling.
- */
-static int reboot_default = 1;
-
-#ifdef CONFIG_SMP
-static int reboot_cpu = -1;
-#endif
 
 /*
  * This is set if we need to go through the 'emergency' path.
@@ -64,79 +48,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +527,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 26cf11b..bc77231 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,23 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 0a97794..ff08af2 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -87,7 +88,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu = 0;
+	int reboot_cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -343,3 +344,80 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+int reboot_default;
+enum reboot_mode reboot_mode = REBOOT_COLD;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
+/*
+ * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
+ * warm   Don't set the cold reboot flag
+ * cold   Set the cold reboot flag
+ * bios   Reboot by jumping through the BIOS
+ * smp    Reboot by executing reset on BSP or other CPU
+ * triple Force a triple fault (init)
+ * kbd    Use the keyboard controller. cold reset (default)
+ * acpi   Use the RESET_REG in the FADT
+ * efi    Use efi reset_system runtime service
+ * pci    Use the so-called "PCI reset register", CF9
+ * force  Avoid anything that could hang.
+ */
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+		case 'h':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+		case 's':
+			if (isdigit(*(str+1)))
+				reboot_cpu = simple_strtoul(str+1);
+			else if (str[1] = 'm' && str[2] = 'p' &&
+							isdigit(*(str+3)))
+				reboot_cpu = simple_strtoul(str+3);
+			else
+				reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'g':
+			reboot_mode = REBOOT_GPIO;
+			break;
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From grant.likely at secretlab.ca  Thu May  9 09:25:18 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 9 May 2013 14:25:18 +0100
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org> <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
Message-ID: <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>

On Mon, May 6, 2013 at 9:12 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
>
>> My conclusion is that build and boot test systems just don't work in an
>> open source environment as no one actively checks the results.  Why would
>> they - maintainers already have enough to do with reading 6500+ emails a
>> month on mailing lists.  Why bother going to look at a website as well
>> which might give even more work.
>
> Point taken. I was in a discussion some time back with Greg and some
> other people and we concluded that unless the system mails you when
> something breaks it won't make a difference. And it mustn't flood you,
> just be very precise.
>
> Actually the autobuilder at kernel.org helped me out but then stopped
> building my trees at some point, but that was nice and the same thing
> doing boots would be great.

+1 on what has already been stated on this thread; An autobuilder does
work if it emails you when something breaks without spamming you. I've
also found the 0day build tester actually effective. It has caught
things that I've missed and I immediately was able to go an fix.

g.


From broonie at kernel.org  Thu May  9 09:26:00 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 9 May 2013 14:26:00 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <518B8F49.5020902@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com>
 <518A8E6C.6070907@st.com> <20130509095143.GB7478@sirena.org.uk>
 <518B8F49.5020902@st.com>
Message-ID: <20130509132600.GA3200@sirena.org.uk>

On Thu, May 09, 2013 at 12:58:01PM +0100, Srinivas KANDAGATLA wrote:

> Currently, we have two bits of information which come from device trees.
> 1> The syscon bank/group definition itself.
> 2> syscon register offsets and bits information to the drivers.

> These are the 2 things which keep changing per each SOC.

> There is no other way to pass this information to the drivers other than
> passing them as part of their own device node and syscon node.

Sure there is, for example the drivers could have this information
internally as part of knowing which device they're working with or they
could take advantage of some patterns in the register map to store some
higher level information that they use to configure.

> >  and to the extent that it is sensible it feels like something
> > which might be useful with any device using register maps, not just
> > syscon.

> If you think this is going to be useful for other drivers, Am happy to
> move this out of syscon to regmap something like adding
> of_regmap_field_claim/regmap_field_claim/regmap_field_read/regmap_field_write/regmap_field_release
> functions.

> so any exiting drivers can still use the old syscon API to get the
> regmap instance.
> Alternatively they can use the new regmap APIs directly.

Well, I'd need to see the code to decide if it was sane but I do think
that if this is a good approach it's not syscon specific.  Anything like
this needs to be independent of DT too since not all architectures use
DT.
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From linux at arm.linux.org.uk  Thu May  9 09:36:43 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 14:36:43 +0100
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130509130120.GW3672@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508103956.GA7677@gmail.com>
 <20130508182007.GO18614@n2100.arm.linux.org.uk> <518A9A83.5010306@zytor.com>
 <20130509112048.GT3672@sgi.com> <20130509130120.GW3672@sgi.com>
Message-ID: <20130509133643.GU18614@n2100.arm.linux.org.uk>

On Thu, May 09, 2013 at 08:01:20AM -0500, Robin Holt wrote:
> diff --git a/include/linux/reboot.h b/include/linux/reboot.h
> index 26cf11b..bc77231 100644
> --- a/include/linux/reboot.h
> +++ b/include/linux/reboot.h
> @@ -15,6 +15,23 @@ enum reboot_mode {
> +extern enum reboot_type reboot_type;
> +
> +extern int reboot_default;
> +extern int reboot_cpu;
> +extern int reboot_force;

Okay, these are globals...

> diff --git a/kernel/reboot.c b/kernel/reboot.c
> index 0a97794..ff08af2 100644
> --- a/kernel/reboot.c
> +++ b/kernel/reboot.c
> @@ -87,7 +88,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
>  static void migrate_to_reboot_cpu(void)
>  {
>  	/* The boot cpu is always logical cpu 0 */
> -	int reboot_cpu = 0;
> +	int reboot_cpu = reboot_cpu;

Hmm, are you sure about that?

> @@ -343,3 +344,80 @@ int orderly_poweroff(bool force)
>  	return 0;
>  }
>  EXPORT_SYMBOL_GPL(orderly_poweroff);
> +
> +int reboot_default;
> +enum reboot_mode reboot_mode = REBOOT_COLD;
> +int reboot_cpu;
> +enum reboot_type reboot_type = BOOT_ACPI;
> +int reboot_force;

As you seem to want to reference these above, wouldn't it make sense to
move them higher in the file?

> +		case 'c':
> +		case 'h':
> +			reboot_mode = REBOOT_COLD;
> +			break;

I'm still not entirely convinced by making "hard" and "cold" mean the
same thing, likewise "soft" and "warm".  As I previously explained but
everyone seems to have ignored, solely focusing on the 's' problem
instead.


From plagnioj at jcrosoft.com  Thu May  9 09:36:45 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 9 May 2013 15:36:45 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <201305082035.57154.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081831.48566.arnd@arndb.de>
 <alpine.LFD.2.03.1305081239260.13109@syhkavp.arg>
 <201305082035.57154.arnd@arndb.de>
Message-ID: <20130509133645.GG3041@game.jcrosoft.org>

On 20:35 Wed 08 May     , Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Nicolas Pitre wrote:
> > I tried to fix this up over 10 years ago.  RMK tried as well. This 
> > failed because X86 people insisted on always having COM1 as /dev/ttyS0, 
> > COM3 as /dev/ttyS2 and so on, even when some of them weren't present.
> > 
> > A common and dynamic namespace eventually succeeded for hard disks.
> > Maybe people are ready to accept it for serial ports as well now?
> 
> Unfortunately it only worked for hard disks because the old name
> space was abandoned entirely. It also caused a lot of surprises
> for people upgrading their kernels, which is something we probably
> don't want to repeat.
> 
> Now we could add a new dynamic registration facility to the tty
> layer for drivers that don't already have a name and dev_t
> associated with the driver, and then use it for all new drivers
> as well as those that intentionally want to convert.

specially that we use devtmpfs and udev

we do not care much about minor/major
> 
> With DT aliases, we already have a way to enumerate serial ports
> across device drivers, so if we are going to do something new,
> we should make sure it works with the numbers defined there.
> 
> 	Arnd


From broonie at kernel.org  Thu May  9 09:50:17 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 9 May 2013 14:50:17 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
Message-ID: <20130509135017.GD3200@sirena.org.uk>

On Thu, May 09, 2013 at 12:50:46PM +0100, Grant Likely wrote:

> However, if a device that shuts down resources after init has
> completed and then cannot turn those resources back on when another
> driver requests them then it sounds like there is a bigger design
> problem. We're in a hotplug world and most of the time a driver cannot
> assume that a resource will never get requested after initcalls have
> completed. It sounds like a design bug in the driver if it cannot
> handle that use case.

Even if the driver copes fine it can still be desirable to avoid the
power down/up cycle if it involves some user visible effect - things
like blinking the display off then on for example.  That said I am a
little suspicious about this approach, it doesn't feel as robust as it
should to go round individual callers.
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From srinivas.kandagatla at st.com  Thu May  9 10:00:16 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 09 May 2013 15:00:16 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <20130509132600.GA3200@sirena.org.uk>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com> <518A8E6C.6070907@st.com>
 <20130509095143.GB7478@sirena.org.uk> <518B8F49.5020902@st.com>
 <20130509132600.GA3200@sirena.org.uk>
Message-ID: <518BABF0.7040201@st.com>

On 09/05/13 14:26, Mark Brown wrote:
> On Thu, May 09, 2013 at 12:58:01PM +0100, Srinivas KANDAGATLA wrote:
> 
>> Currently, we have two bits of information which come from device trees.
>> 1> The syscon bank/group definition itself.
>> 2> syscon register offsets and bits information to the drivers.
> 
>> These are the 2 things which keep changing per each SOC.
> 
>> There is no other way to pass this information to the drivers other than
>> passing them as part of their own device node and syscon node.
> 
> Sure there is, for example the drivers could have this information
> internally as part of knowing which device they're working with or they
> could take advantage of some patterns in the register map to store some
> higher level information that they use to configure.
> 
Some of layouts of the sysconf registers are totally changed for each SOC.

Looking at driver by driver maybe some drivers can take advantage of the
patterns, but Am not sure if this will be a sustainable solution for all
the drivers.

The big disadvantage of this approach is that
- Every driver has to be touched for new SOC,
- Secondly the drivers will end up having more of such information than
code over a time.

>>>  and to the extent that it is sensible it feels like something
>>> which might be useful with any device using register maps, not just
>>> syscon.
> 
>> If you think this is going to be useful for other drivers, Am happy to
>> move this out of syscon to regmap something like adding
>> of_regmap_field_claim/regmap_field_claim/regmap_field_read/regmap_field_write/regmap_field_release
>> functions.
> 
>> so any exiting drivers can still use the old syscon API to get the
>> regmap instance.
>> Alternatively they can use the new regmap APIs directly.
> 
> Well, I'd need to see the code to decide if it was sane but I do think
> that if this is a good approach it's not syscon specific.  Anything like
> this needs to be independent of DT too since not all architectures use
> DT.
In the suggested approach, the API supports, both DT and non-DT style.

for DT style user can use.
of_regmap_field_claim -> regmap_field_read -> regmap_field_write-
->regmap_field_release

and for NON-DT user can use
regmap_field_claim  -> regmap_field_read -> regmap_field_write-
->regmap_field_release


thanks,
srini


> 



From srinivas.kandagatla at st.com  Thu May  9 10:07:59 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 09 May 2013 15:07:59 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <201305081638.23100.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081638.23100.arnd@arndb.de>
Message-ID: <518BADBF.4070303@st.com>

On 08/05/13 15:38, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Stuart Menefy <stuart.menefy at st.com>
>>
>> This is a simple driver for the global timer module found in the Cortex
>> A9-MP cores from revision r1p0 onwards. This should be able to perform
>> the functions of the system timer and the local timer in an SMP system.
>>
>> The global timer has the following features:
>>     The global timer is a 64-bit incrementing counter with an
>> auto-incrementing feature. It continues incrementing after sending
>> interrupts. The global timer is memory mapped in the private memory
>> region.
>>     The global timer is accessible to all Cortex-A9 processors in the
>> cluster. Each Cortex-A9 processor has a private 64-bit comparator that
>> is used to assert a private interrupt when the global timer has reached
>> the comparator value. All the Cortex-A9 processors in a design use the
>> banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
>> Controller as a Private Peripheral Interrupt. The global timer is
>> clocked by PERIPHCLK.
>>
>> Signed-off-by: Stuart Menefy <stuart.menefy at st.com>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>>
> 
> Are you sure we don't already have a driver for this? It sounds unlikely
> that you are the first one to do this when the hardware is so common.

Yes, in mainline we do not have support to this.

> 
>>  Documentation/devicetree/bindings/arm/gt.txt |   21 ++
>>  arch/arm/Kconfig                             |    6 +
>>  arch/arm/include/asm/global_timer.h          |   12 +
>>  arch/arm/kernel/Makefile                     |    1 +
>>  arch/arm/kernel/global_timer.c               |  325 ++++++++++++++++++++++++++
>>  5 files changed, 365 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/gt.txt
>>  create mode 100644 arch/arm/include/asm/global_timer.h
>>  create mode 100644 arch/arm/kernel/global_timer.c
> 
> Move it into drivers/clocksource?

Sure, I will move this in the next version.

>  
>> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
>> new file mode 100644
>> index 0000000..46f9188
>> --- /dev/null
>> +++ b/arch/arm/include/asm/global_timer.h
>> @@ -0,0 +1,12 @@
>> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq);
> 
> I don't see a need to call this from platform code for non-DT platforms, it
> can easily be used with CLOCKSOURCE_OF_DECLARE() all the time I think.

sorry Am confused here.
How would this work for non-DT?

Looking at the code in clocksource_of_init it just goes through the
of_device_id table, which is not used in case of non-DT.
> 
> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> 



From linux at arm.linux.org.uk  Thu May  9 10:14:45 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 15:14:45 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <20130509135017.GD3200@sirena.org.uk>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
Message-ID: <20130509141444.GV18614@n2100.arm.linux.org.uk>

On Thu, May 09, 2013 at 02:50:17PM +0100, Mark Brown wrote:
> On Thu, May 09, 2013 at 12:50:46PM +0100, Grant Likely wrote:
> 
> > However, if a device that shuts down resources after init has
> > completed and then cannot turn those resources back on when another
> > driver requests them then it sounds like there is a bigger design
> > problem. We're in a hotplug world and most of the time a driver cannot
> > assume that a resource will never get requested after initcalls have
> > completed. It sounds like a design bug in the driver if it cannot
> > handle that use case.
> 
> Even if the driver copes fine it can still be desirable to avoid the
> power down/up cycle if it involves some user visible effect - things
> like blinking the display off then on for example.  That said I am a
> little suspicious about this approach, it doesn't feel as robust as it
> should to go round individual callers.

What if the driver for something like your display is a module which
needs to be loaded from userland?

Where the design bug lies is in the "lets probe all the drivers and then
shut down resources which drivers haven't claimed".  That contains an
implied assumption: that all drivers have been loaded and probed at the
point where you shut down those resources.

That simply may not be true in todays kernel - it's not true for a start
if you have modular drivers, and you have built most of the drivers as
modules (as a distro would want to with single zImage).  It's
coincidentally not true if you have deferred probing and some drivers
defer.

The real problem is this: at what point has the system actually finished
"booting" in the sense that all drivers for a platform have been
initialised?  With user loadable modules and deferred probing, that's
actually a very fuzzy concept.

As you can't really tell when that point has been reached, how can you
decide to shut down resources which "aren't being used" in a sane way
without avoiding the down/up cycle?  Basically, you can't.

So, trying to solve the problem may be totally fruitless because you
can't actually solve it - you can only put a sticky plaster over it and
hope that it catches most of the problem.  But reality is that you can't
have both a shutdown of unused resources _and_ avoid the down/up cycle.


From tom.leiming at gmail.com  Thu May  9 10:32:04 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Thu, 9 May 2013 22:32:04 +0800
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
Message-ID: <CACVXFVO3gPMXwzX0WUS4+-FA-SKEKnJt+aK4nL80aTAcEWNLPA@mail.gmail.com>

On Thu, May 9, 2013 at 1:18 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> Kernel framework (Eg: regulator, clock, etc) might want to do some clean up
> work (Eg: turn off unclaimed resources) after all devices are done probing
> during kernel init. Before deferred probing was introduced, this was

Generally, system resources should be configured as disabled
at default, and for drivers, the correct usage should be only requesting
and enabling the resources just in need, then the sort of 'cleanup' things
can be avoided.


Thanks,
-- 
Ming Lei


From broonie at kernel.org  Thu May  9 10:37:02 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 9 May 2013 15:37:02 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <20130509141444.GV18614@n2100.arm.linux.org.uk>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
 <20130509141444.GV18614@n2100.arm.linux.org.uk>
Message-ID: <20130509143702.GE3200@sirena.org.uk>

On Thu, May 09, 2013 at 03:14:45PM +0100, Russell King - ARM Linux wrote:
> On Thu, May 09, 2013 at 02:50:17PM +0100, Mark Brown wrote:

> > Even if the driver copes fine it can still be desirable to avoid the
> > power down/up cycle if it involves some user visible effect - things
> > like blinking the display off then on for example.  That said I am a
> > little suspicious about this approach, it doesn't feel as robust as it
> > should to go round individual callers.

> What if the driver for something like your display is a module which
> needs to be loaded from userland?

That's clearly a "don't do that then" sort of thing; while we don't want
to be unhelpful there's no guarantees with this approach.

> Where the design bug lies is in the "lets probe all the drivers and then
> shut down resources which drivers haven't claimed".  That contains an
> implied assumption: that all drivers have been loaded and probed at the
> point where you shut down those resources.

Well, that's not really the intention - it's not a strong guarantee,
it never has been given things like the module case you mention.

> So, trying to solve the problem may be totally fruitless because you
> can't actually solve it - you can only put a sticky plaster over it and
> hope that it catches most of the problem.  But reality is that you can't
> have both a shutdown of unused resources _and_ avoid the down/up cycle.

Yes, exactly - all we're trying to do here is cover the 90% case, not
solve all the possible problems since as you say that's not achievable.  
There's a clear and reasonable desire to turn off resources we know
aren't in use at the current time, but equally well doing so as soon as
we start controlling the resources is pretty much guranteed to introduce
user visible issues on some systems so it's a question of picking some
reasonable point after that.

Another option here which is more in tune with deferred probing and
hotplugging would be to switch the delay over to be time based rather
than initcall based; do the shutdown at some point based on the time the
last resource was registered.  That still won't cover everything
though we could make the delay tunable.
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From broonie at kernel.org  Thu May  9 10:40:55 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 9 May 2013 15:40:55 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <518BABF0.7040201@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com>
 <518A8E6C.6070907@st.com> <20130509095143.GB7478@sirena.org.uk>
 <518B8F49.5020902@st.com> <20130509132600.GA3200@sirena.org.uk>
 <518BABF0.7040201@st.com>
Message-ID: <20130509144055.GF3200@sirena.org.uk>

On Thu, May 09, 2013 at 03:00:16PM +0100, Srinivas KANDAGATLA wrote:

> Some of layouts of the sysconf registers are totally changed for each SOC.

> Looking at driver by driver maybe some drivers can take advantage of the
> patterns, but Am not sure if this will be a sustainable solution for all
> the drivers.

So what exactly is the driver doing then?  If the register maps look
nothing like each other then what's the common functionality the driver
is providing?
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From arnd at arndb.de  Thu May  9 10:51:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 May 2013 16:51:13 +0200
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <518BADBF.4070303@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081638.23100.arnd@arndb.de> <518BADBF.4070303@st.com>
Message-ID: <201305091651.13896.arnd@arndb.de>

On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
> >> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
> >> new file mode 100644
> >> index 0000000..46f9188
> >> --- /dev/null
> >> +++ b/arch/arm/include/asm/global_timer.h
> >> @@ -0,0 +1,12 @@
> >> +int __init global_timer_init(void __iomem *base, unsigned int timer_irq);
> > 
> > I don't see a need to call this from platform code for non-DT platforms, it
> > can easily be used with CLOCKSOURCE_OF_DECLARE() all the time I think.
> 
> sorry Am confused here.
> How would this work for non-DT?

It won't.

> Looking at the code in clocksource_of_init it just goes through the
> of_device_id table, which is not used in case of non-DT.

All new platforms are DT-only, and none of the old platforms use this
driver, so it does not matter.

	Arnd


From srinivas.kandagatla at st.com  Thu May  9 10:47:36 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 09 May 2013 15:47:36 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <20130509144055.GF3200@sirena.org.uk>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com> <518A8E6C.6070907@st.com>
 <20130509095143.GB7478@sirena.org.uk> <518B8F49.5020902@st.com>
 <20130509132600.GA3200@sirena.org.uk> <518BABF0.7040201@st.com>
 <20130509144055.GF3200@sirena.org.uk>
Message-ID: <518BB708.7040505@st.com>

On 09/05/13 15:40, Mark Brown wrote:
> So what exactly is the driver doing then?  If the register maps look
> nothing like each other then what's the common functionality the driver
> is providing?
What I meant here is that, sysconf registers are reassigned per SOC, so
the sysconf register definitions change per SOC, not the register map of
the device itself.

The register map of the device itself still looks the same, however few
bits of the IP are wired up to the global sysconf registers, which is
what keeps changing, w.r.t sysconf number or bits of the sysconf itself.






From srinivas.kandagatla at st.com  Thu May  9 10:51:17 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 09 May 2013 15:51:17 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <201305091651.13896.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081638.23100.arnd@arndb.de> <518BADBF.4070303@st.com>
 <201305091651.13896.arnd@arndb.de>
Message-ID: <518BB7E5.4070402@st.com>

On 09/05/13 15:51, Arnd Bergmann wrote:
> It won't.
> 
>> > Looking at the code in clocksource_of_init it just goes through the
>> > of_device_id table, which is not used in case of non-DT.
> All new platforms are DT-only, and none of the old platforms use this
> driver, so it does not matter.
> 
It makes sense, I will remove the header file.
> 	Arnd
> 



From linux at arm.linux.org.uk  Thu May  9 11:07:50 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 16:07:50 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <20130509143702.GE3200@sirena.org.uk>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
 <20130509141444.GV18614@n2100.arm.linux.org.uk>
 <20130509143702.GE3200@sirena.org.uk>
Message-ID: <20130509150750.GW18614@n2100.arm.linux.org.uk>

On Thu, May 09, 2013 at 03:37:02PM +0100, Mark Brown wrote:
> On Thu, May 09, 2013 at 03:14:45PM +0100, Russell King - ARM Linux wrote:
> > On Thu, May 09, 2013 at 02:50:17PM +0100, Mark Brown wrote:
> 
> > > Even if the driver copes fine it can still be desirable to avoid the
> > > power down/up cycle if it involves some user visible effect - things
> > > like blinking the display off then on for example.  That said I am a
> > > little suspicious about this approach, it doesn't feel as robust as it
> > > should to go round individual callers.
> 
> > What if the driver for something like your display is a module which
> > needs to be loaded from userland?
> 
> That's clearly a "don't do that then" sort of thing; while we don't want
> to be unhelpful there's no guarantees with this approach.

That's not a "don't do that then" thing, because in this case it's
unreasonable to say that.  The display subsystems like fbdev and
DRM represent quite a sizable chunk:

- Base DRM is around 200k.
- DRM drivers typically around 100k each.
- Base FBdev is around 100k.

It won't take long before you're into the territory of having a
significant portion of your kernel being display drivers of one
type or other, much of which won't be usable on any one specific
platform.  So to say "don't build your display drivers as modules"
is an unreasonable position to take.

> Yes, exactly - all we're trying to do here is cover the 90% case, not
> solve all the possible problems since as you say that's not achievable.  
> There's a clear and reasonable desire to turn off resources we know
> aren't in use at the current time, but equally well doing so as soon as
> we start controlling the resources is pretty much guranteed to introduce
> user visible issues on some systems so it's a question of picking some
> reasonable point after that.

I beg to differ on whether it's possible to solve it completely.

> Another option here which is more in tune with deferred probing and
> hotplugging would be to switch the delay over to be time based rather
> than initcall based; do the shutdown at some point based on the time the
> last resource was registered.  That still won't cover everything
> though we could make the delay tunable.

Yuck.  That's crap design.  Really, time based stuff is crap.  I've seen
this too many times with the gnome crap in Ubuntu 12.04 - where if you
boot this off SD card it will complain that some applets fail to start
(and sure enough, half your panel is missing.)  Boot it off eSATA and
it works 100% reliably.

Time based stuff to guess when stuff has finished is never a good thing
and can never be reliable.

A better solution may be to avoid the problem in kernel space altogether.
That's already done in the past with the scsi_wait_scan module.  Make the
the shutdown of stuff a separate loadable module which userspace can load
at the appropriate time to trigger the shutdown of unused resources.  Or
provide a different method for userspace to trigger that action.

With that kind of solution, it is possible to know that the system has
finished booting (many userspace implementations already do this with
stuff like not permitting login via network until after the system has
finished booting despite sshd et.al. already being started.)


From tony at atomide.com  Thu May  9 11:20:48 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 08:20:48 -0700
Subject: omap3430 fails to boot
In-Reply-To: <20130509084906.GL21614@n2100.arm.linux.org.uk>
References: <20130509084906.GL21614@n2100.arm.linux.org.uk>
Message-ID: <20130509152047.GA32546@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [130509 01:54]:
> I've not looked into the reason why yet, so this is a heads-up.  I
> notice this morning that the LDP3430 failed to boot last night,
> whereas it worked the previous night.  However, SDP4430 looks fine.
> 
> Nothing obvious in the diffstat between the two... but then the patch
> between the two kernels is almost 1.5MB.  The arch/arm changes are
> quite small though:
> 
>  arch/arm/Kconfig                                   |    1 +
>  arch/arm/boot/dts/Makefile                         |    4 +-
>  arch/arm/boot/dts/xenvm-4.2.dts                    |   13 +
>  arch/arm/include/asm/xen/hypercall.h               |    1 +
>  arch/arm/mach-msm/last_radio_log.c                 |    2 +-
>  arch/arm/mach-omap2/board-4430sdp.c                |    2 +-
>  arch/arm/mach-omap2/board-omap4panda.c             |    2 +-
>  arch/arm/mach-omap2/timer.c                        |    4 +
>  arch/arm/mach-vexpress/v2m.c                       |    1 -
>  arch/arm/mach-virt/virt.c                          |    1 +

Since one boots and one won't, you're probably missing this one:

956e46ef mm/slab: Fix crash during slab init

Looking at your diffstat you probably have this as otherwise
nothing boots:

9affd6be arm: fix mismerge of arch/arm/mach-omap2/timer.c

Let me know if you still have the issue after updating to 956e46ef.

Regards,

Tony


From tony at atomide.com  Thu May  9 11:39:33 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 08:39:33 -0700
Subject: arch/arm/mach-omap2/id.c - IS_ERR_OR_NULL()
In-Reply-To: <20130509090911.GM21614@n2100.arm.linux.org.uk>
References: <20130509090911.GM21614@n2100.arm.linux.org.uk>
Message-ID: <20130509153933.GA31554@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [130509 02:14]:
> So, I eliminated all but a very few of these from arch/arm, and I notice
> today that there's a new couple of instances introduced by:

Sorry I should have noticed that fnord, I had it in my muttrc but had
a an unnecessary \ in the expression so it did not work.  

Here's a patch to fix the issue.

Hmm maybe we could redefine IS_ERR_OR_NULL as error in some ARM header
as long as drivers don't include it?

Regards,

Tony


From: Tony Lindgren <tony at atomide.com>
Date: Thu, 9 May 2013 08:27:25 -0700
Subject: [PATCH] ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c

Commit 6770b211 (ARM: OMAP2+: Export SoC information to userspace)
had some broken return value handling as noted by Russell King:

+       soc_dev = soc_device_register(soc_dev_attr);
+       if (IS_ERR_OR_NULL(soc_dev)) {
+               kfree(soc_dev_attr);
+               return;
+       }
+
+       parent = soc_device_to_device(soc_dev);
+       if (!IS_ERR_OR_NULL(parent))
+               device_create_file(parent, &omap_soc_attr);

This is nonsense.  For the first, IS_ERR() is sufficient.  For the second,
tell me what error checking is required in the return value of this
function:

struct device *soc_device_to_device(struct soc_device *soc_dev)
{
        return &soc_dev->dev;
}

when you've already determined that the passed soc_dev is a valid pointer.
If you read the comments against the prototype:

/**
 * soc_device_to_device - helper function to fetch struct device
 * @soc: Previously registered SoC device container
 */
struct device *soc_device_to_device(struct soc_device *soc);

if "soc" is valid, it means the "previously registered SoC device container"
must have succeeded and that can only happen if the struct device has been
registered.  Ergo, there will always be a valid struct device pointer for
any registered SoC device container.  Therefore, if soc_device_register()
succeeds, then the return value from soc_device_to_device() will always be
valid and no error checking of it is required.

Simples.  The rule as ever applies here: get to know the APIs your using
and don't fumble around in the dark hoping that you'll get this stuff
right.

Fix it as noted by Russell.

Reported-by: Russell King <rmk+kernel at arm.linux.org.uk>
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9bc5a18..1272c41 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -648,13 +648,12 @@ void __init omap_soc_device_init(void)
 	soc_dev_attr->revision = soc_rev;
 
 	soc_dev = soc_device_register(soc_dev_attr);
-	if (IS_ERR_OR_NULL(soc_dev)) {
+	if (IS_ERR(soc_dev)) {
 		kfree(soc_dev_attr);
 		return;
 	}
 
 	parent = soc_device_to_device(soc_dev);
-	if (!IS_ERR_OR_NULL(parent))
-		device_create_file(parent, &omap_soc_attr);
+	device_create_file(parent, &omap_soc_attr);
 }
 #endif /* CONFIG_SOC_BUS */


From broonie at kernel.org  Thu May  9 11:43:52 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 9 May 2013 16:43:52 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <20130509150750.GW18614@n2100.arm.linux.org.uk>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
 <20130509141444.GV18614@n2100.arm.linux.org.uk>
 <20130509143702.GE3200@sirena.org.uk>
 <20130509150750.GW18614@n2100.arm.linux.org.uk>
Message-ID: <20130509154352.GG3200@sirena.org.uk>

On Thu, May 09, 2013 at 04:07:50PM +0100, Russell King - ARM Linux wrote:
> On Thu, May 09, 2013 at 03:37:02PM +0100, Mark Brown wrote:

> > That's clearly a "don't do that then" sort of thing; while we don't want
> > to be unhelpful there's no guarantees with this approach.

> That's not a "don't do that then" thing, because in this case it's
> unreasonable to say that.  The display subsystems like fbdev and
> DRM represent quite a sizable chunk:

> - Base DRM is around 200k.
> - DRM drivers typically around 100k each.
> - Base FBdev is around 100k.

> It won't take long before you're into the territory of having a
> significant portion of your kernel being display drivers of one
> type or other, much of which won't be usable on any one specific
> platform.  So to say "don't build your display drivers as modules"
> is an unreasonable position to take.

Sure, it's unhelpful for distro style kernels.  Like I say, 90%.

> > Another option here which is more in tune with deferred probing and
> > hotplugging would be to switch the delay over to be time based rather
> > than initcall based; do the shutdown at some point based on the time the
> > last resource was registered.  That still won't cover everything
> > though we could make the delay tunable.

> Yuck.  That's crap design.  Really, time based stuff is crap.  I've seen
> this too many times with the gnome crap in Ubuntu 12.04 - where if you
> boot this off SD card it will complain that some applets fail to start
> (and sure enough, half your panel is missing.)  Boot it off eSATA and
> it works 100% reliably.

No argument here, there's a reason I immediately went to the "make it
tunable" fudge factor.

> A better solution may be to avoid the problem in kernel space altogether.
> That's already done in the past with the scsi_wait_scan module.  Make the
> the shutdown of stuff a separate loadable module which userspace can load
> at the appropriate time to trigger the shutdown of unused resources.  Or
> provide a different method for userspace to trigger that action.

> With that kind of solution, it is possible to know that the system has
> finished booting (many userspace implementations already do this with
> stuff like not permitting login via network until after the system has
> finished booting despite sshd et.al. already being started.)

This works fine for boot but if we're going to solve this properly and
asking userspace to make changes we probably ought to be trying to
handle the actual hotplug case (which the current bodge doesn't cope
with at all) as well.  A similar tactic with asking for handshaking from
userspace for hotplug notifications should work though it'd be a bit
more hassle to deploy.

Or perhaps given that it should be simple for userspace and there's
probably other uses for the information we just put the hook in there
anyway even if this particular problem gets a better solution later on.
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From liuj97 at gmail.com  Thu May  9 11:42:00 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Thu,  9 May 2013 23:42:00 +0800
Subject: [PATCH] mm: change signature of free_reserved_area() to fix building
 warnings
In-Reply-To: <20130508184555.GR18614@n2100.arm.linux.org.uk>
References: <20130508184555.GR18614@n2100.arm.linux.org.uk>
Message-ID: <1368114120-21716-1-git-send-email-jiang.liu@huawei.com>

Change signature of free_reserved_area() according to Russell King's
suggestion to fix following build warnings:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
  free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
  ^
In file included from include/linux/mman.h:4:0,
                 from arch/arm/mm/init.c:15:
include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
 extern unsigned long free_reserved_area(unsigned long start, unsigned long end,

   mm/page_alloc.c: In function 'free_reserved_area':
>> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
   In file included from arch/mips/include/asm/page.h:49:0,
                    from include/linux/mmzone.h:20,
                    from include/linux/gfp.h:4,
                    from include/linux/mm.h:8,
                    from mm/page_alloc.c:18:
   arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
   mm/page_alloc.c: In function 'free_area_init_nodes':
   mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Reported-by: Arnd Bergmann <arnd at arndb.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-mm at kvack.org
---
Hi Russell,
	Thanks for your review. How about this change to fix the building
warning by change signature of free_reserved_area()?
	Thanks!
	Gerry
---
 arch/alpha/kernel/sys_nautilus.c |    4 ++--
 arch/alpha/mm/init.c             |    2 +-
 arch/arc/mm/init.c               |    2 +-
 arch/arm/mm/init.c               |    2 +-
 arch/arm64/mm/init.c             |    2 +-
 arch/avr32/mm/init.c             |    2 +-
 arch/blackfin/mm/init.c          |    2 +-
 arch/c6x/mm/init.c               |    2 +-
 arch/frv/mm/init.c               |    2 +-
 arch/h8300/mm/init.c             |    2 +-
 arch/ia64/mm/init.c              |    3 +--
 arch/m32r/mm/init.c              |    2 +-
 arch/m68k/mm/init.c              |    2 +-
 arch/metag/mm/init.c             |    3 ++-
 arch/microblaze/mm/init.c        |    2 +-
 arch/mips/mm/init.c              |    3 ++-
 arch/mn10300/mm/init.c           |    3 ++-
 arch/openrisc/mm/init.c          |    2 +-
 arch/parisc/mm/init.c            |    3 ++-
 arch/powerpc/kernel/kvm.c        |    2 +-
 arch/powerpc/mm/mem.c            |    2 +-
 arch/s390/mm/init.c              |    3 ++-
 arch/score/mm/init.c             |    3 ++-
 arch/sh/mm/init.c                |    2 +-
 arch/sparc/mm/init_32.c          |    4 ++--
 arch/sparc/mm/init_64.c          |    4 ++--
 arch/um/kernel/mem.c             |    2 +-
 arch/unicore32/mm/init.c         |    2 +-
 arch/xtensa/mm/init.c            |    2 +-
 include/linux/mm.h               |    5 ++---
 mm/page_alloc.c                  |   16 ++++++++--------
 31 files changed, 48 insertions(+), 44 deletions(-)

diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 1d4aabf..891bd27 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -238,8 +238,8 @@ nautilus_init_pci(void)
 	if (pci_mem < memtop)
 		memtop = pci_mem;
 	if (memtop > alpha_mv.min_mem_address) {
-		free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
-				   (unsigned long)__va(memtop), 0, NULL);
+		free_reserved_area(__va(alpha_mv.min_mem_address),
+				   __va(memtop), 0, NULL);
 		printk("nautilus_init_pci: %ldk freed\n",
 			(memtop - alpha_mv.min_mem_address) >> 10);
 	}
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 0ba85ee..d54848d 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -326,6 +326,6 @@ free_initmem(void)
 void
 free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 4a17736..dce02e4 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -152,7 +152,7 @@ void __init_refok free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc0..59d6f76 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -744,7 +744,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index f497ca7..6041e40 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -398,7 +398,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index e66e840..5a79fa0 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -154,6 +154,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 82d01a7..8e9eab2 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -133,7 +133,7 @@ void __init mem_init(void)
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
 #ifndef CONFIG_MPU
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 #endif
 }
 #endif
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
index a9fcd89..97914e5 100644
--- a/arch/c6x/mm/init.c
+++ b/arch/c6x/mm/init.c
@@ -77,7 +77,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index dee354f..a67f3a5 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -173,6 +173,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 } /* end free_initrd_mem() */
 #endif
diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c
index ff349d7..57e03c5 100644
--- a/arch/h8300/mm/init.c
+++ b/arch/h8300/mm/init.c
@@ -161,7 +161,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index d1fe4b4..da568c2 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -154,8 +154,7 @@ ia64_init_addr_space (void)
 void
 free_initmem (void)
 {
-	free_reserved_area((unsigned long)ia64_imva(__init_begin),
-			   (unsigned long)ia64_imva(__init_end),
+	free_reserved_area(ia64_imva(__init_begin), ia64_imva(__init_end),
 			   0, "unused kernel");
 }
 
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index ab4cbce..d80412d 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -191,6 +191,6 @@ void free_initmem(void)
  *======================================================================*/
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 1af2ca3..95de725 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -202,6 +202,6 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index d05b845..5e2238d 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -414,7 +414,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 4ec137d..73a49c4 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -235,7 +235,7 @@ void __init setup_memory(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 3d0346d..3931be5 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -439,7 +439,8 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 5a8ace6..e19049d 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -152,6 +152,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index b3cbc67..ab11332 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -261,7 +261,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 157b931..7fd8c8d 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -1099,6 +1099,7 @@ void flush_tlb_all(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, 0, "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end, 0,
+					    "initrd");
 }
 #endif
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 6782221..5e4830a 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -756,7 +756,7 @@ static __init void kvm_free_tmp(void)
 	end = (ulong)&kvm_tmp[ARRAY_SIZE(kvm_tmp)] & PAGE_MASK;
 
 	/* Free the tmp space we don't need */
-	free_reserved_area(start, end, 0, NULL);
+	free_reserved_area((void *)start, (void *)end, 0, NULL);
 }
 
 static int __init kvm_guest_init(void)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 0988a26..347c5b1 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -407,7 +407,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 0b09b23..4c01c3a 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -170,7 +170,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index 1592aad..7b78bd1 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -110,7 +110,8 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 20f9ead..b892a9b 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -505,7 +505,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index af472cf..d5f9c02 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -372,8 +372,8 @@ void free_initmem (void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index a717199..a54cdcd 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2124,8 +2124,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 9df292b..2aa7a24 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -244,7 +244,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 63df12d..220755c 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -486,7 +486,7 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index bba125b..4d658ef 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -214,7 +214,7 @@ extern int initrd_is_mapped;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (initrd_is_mapped)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 1a7f19e..4daa3d1 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1301,7 +1301,7 @@ extern void free_initmem(void);
  * "poison" if it's non-zero.
  * Return pages freed into the buddy system.
  */
-extern unsigned long free_reserved_area(unsigned long start, unsigned long end,
+extern unsigned long free_reserved_area(void *start, void *end,
 					int poison, char *s);
 #ifdef	CONFIG_HIGHMEM
 /*
@@ -1345,8 +1345,7 @@ static inline unsigned long free_initmem_default(int poison)
 {
 	extern char __init_begin[], __init_end[];
 
-	return free_reserved_area(PAGE_ALIGN((unsigned long)&__init_begin) ,
-				  ((unsigned long)&__init_end) & PAGE_MASK,
+	return free_reserved_area(&__init_begin, &__init_end,
 				  poison, "unused kernel");
 }
 
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 843e33d..91ceebc 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5186,21 +5186,21 @@ early_param("movablecore", cmdline_parse_movablecore);
 
 #endif /* CONFIG_HAVE_MEMBLOCK_NODE_MAP */
 
-unsigned long free_reserved_area(unsigned long start, unsigned long end,
-				 int poison, char *s)
+unsigned long free_reserved_area(void *start, void *end, int poison, char *s)
 {
-	unsigned long pages, pos;
+	void *pos;
+	unsigned long pages = 0;
 
-	pos = start = PAGE_ALIGN(start);
-	end &= PAGE_MASK;
-	for (pages = 0; pos < end; pos += PAGE_SIZE, pages++) {
+	start = (void *)PAGE_ALIGN((unsigned long)start);
+	end = (void *)((unsigned long)end & PAGE_MASK);
+	for (pos = start; pos < end; pos += PAGE_SIZE, pages++) {
 		if (poison)
-			memset((void *)pos, poison, PAGE_SIZE);
+			memset(pos, poison, PAGE_SIZE);
 		free_reserved_page(virt_to_page(pos));
 	}
 
 	if (pages && s)
-		pr_info("Freeing %s memory: %ldK (%lx - %lx)\n",
+		pr_info("Freeing %s memory: %ldK (%p - %p)\n",
 			s, pages << (PAGE_SHIFT - 10), start, end);
 
 	return pages;
-- 
1.7.9.5



From pranavkumar at linaro.org  Thu May  9 11:51:49 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Thu, 9 May 2013 21:21:49 +0530
Subject: [PATCH] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
In-Reply-To: <518B9802.1080505@arm.com>
References: <1368099611-4738-1-git-send-email-pranavkumar@linaro.org>
 <518B9802.1080505@arm.com>
Message-ID: <CAAHg+HhO873_Cs_ucKL_T_NO9sV61dRBh1cvtRD3VAiM3sq8Yg@mail.gmail.com>

Hi Marc,

On 9 May 2013 18:05, Marc Zyngier <marc.zyngier at arm.com> wrote:
> Hi Pranav,
>
> On 09/05/13 12:40, Pranavkumar Sawargaonkar wrote:
>> This patch does following fixes:
>>
>> 1. Make HCR_* flags as unsigned long long constants
>> Reason : By default, compiler assumes numeric constants as
>> signed hence sign extending it when assigned to unsigned variable
>> such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
>> HCR_CD making entire guest memory non-cacheable. On real HW, this
>> breaks Stage2 ttbl walks and also breaks VirtIO.
>
> Ah. Nice one. I fixed a couple of similar bugs already, but didn't
> notice that one yet, for obvious reasons...
>
> I'll probably rewrite that patch to use the UL(x) macro instead of
> _AC(), as we don't need to have an unsigned long long, and that makes
> the code look much nicer (sort of).
>

Sure I will resubmit with UL change.
Yeah this issue keeps wondering me and anup, unexpected VIRTIO
behavior on board for sometime on board till finally realized :)

>> 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.
>
> Blah. Copy paste. Fucks me all the time.
>
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>> ---
>>  arch/arm64/include/asm/kvm_arm.h |   73 +++++++++++++++++++-------------------
>>  1 file changed, 37 insertions(+), 36 deletions(-)
>
> Thanks a lot,
>
>         M.
> --
> Jazz is not dead. It just smells funny...
>

Thanks,
Pranav


From stern at rowland.harvard.edu  Thu May  9 11:54:42 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 9 May 2013 11:54:42 -0400 (EDT)
Subject: [RFC PATCH 1/2] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <CAJFYCKGSctw1_nXoETYwyVkgAncHyBb8dmZ9aBV-av=8S0rw4A@mail.gmail.com>
Message-ID: <Pine.LNX.4.44L0.1305091108130.1796-100000@iolanthe.rowland.org>

On Thu, 9 May 2013, Manjunath Goudar wrote:

> > > @@ -767,7 +762,37 @@ retry:
> > >
> > >       return 0;
> > >  }
> > >
> > +/*------------------------------------------------------------------------*/
> > > +
> > > +/* ohci generic function for all OHCI bus glue */
> > > +
> > > +static int ohci_setup(struct usb_hcd *hcd)
> > > +{
> > > +     struct ohci_hcd *ohci = hcd_to_ohci(hcd);
> > > +     int retval;
> > > +
> > > +     ohci->sbrn = HCD_USB11;
> >
> > What is this doing here?  Why did you add this "sbrn" member to struct
> > ohci_hcd?
> >
> > not required so reverted.
> 
> > > +
> > > +     /* data structure init */
> > > +     retval = ohci_init(ohci);
> > > +     if (retval)
> > > +             return retval;
> > > +     ohci_usb_reset(ohci);
> >
> > Why is this call here?  Doesn't ohci_init() already call
> > ohci_usb_reset()?
> >
> >
> ohci_init is not called in ohci_usb_reset() its called in ohci_restart() so
> I think ohci_init needed.

It sounds like you did not understand what I wrote.

ohci_setup does not need to call ohci_usb_reset.  ohci_setup calls
ohci_init, and ohci_init calls ohci_usb_reset.


> > The #else part of this isn't needed, and I doubt very much that it
> > would work correctly if it was needed.
> >
> > As Arnd suggestion,so I written else part.

The existing code doesn't have a #else part, and I don't think you need 
to add one.

Alan Stern



From tony at atomide.com  Thu May  9 11:56:45 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 08:56:45 -0700
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <20130509003606.GE31290@titan.lakedaemon.net>
References: <cover.1368038129.git.jason@lakedaemon.net>
 <20130508194504.GD32546@atomide.com>
 <20130509003606.GE31290@titan.lakedaemon.net>
Message-ID: <20130509155645.GB31554@atomide.com>

* Jason Cooper <jason at lakedaemon.net> [130508 17:41]:
> On Wed, May 08, 2013 at 12:45:04PM -0700, Tony Lindgren wrote:
> > * Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> > > 
> > > Tony has been helping me out offline with this, and he suggested trying the
> > > gpmc against Linus' ToT.  Which locks up before it even has a chance to get
> > > going.  So this series is against v3.9.
> > 
> > You may have better luck with today's mainline treeand the following fix:
> > 
> > http://lkml.org/lkml/2013/5/8/374#
> 
> Ok, I'm attempting to do that, but got this for 'make dtbs':
> 
> ERROR (phandle_references): Reference to non-existent node or label "usb2_phy"
> 
> ERROR: Input tree has errors, aborting (use -f to force output)
> make[1]: *** [arch/arm/boot/dts/omap3-wireless_plus.dtb] Error 2
> make[1]: *** Waiting for unfinished jobs....
> make: *** [dtbs] Error 2
> 
> which was created by:
> 
>   ad871c10 ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
> 
> It assumes the board has twl4030 (and then includes it).  Bootlogs from
> the vendor provided kernel don't show a single message from twl4030, so
> I've omitted it.
> 
> Assuming I did the correct thing by omitting the twl4030, I think the
> correct answer is to declare the phy in the dts files, like so:

Thanks, that is correct. We should not assume any PMIC with a processor
as it can also be a custom chip. For example, Nokia n8x0 is using their
retu + tahvo chips instead of tps chips.

I'll apply your patch into omap-for-v3.10/fixes.

Regards,

Tony
 


From holt at sgi.com  Thu May  9 11:59:31 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 9 May 2013 10:59:31 -0500
Subject: [PATCH -v8 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <20130509133643.GU18614@n2100.arm.linux.org.uk>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-12-git-send-email-holt@sgi.com>
 <20130508103956.GA7677@gmail.com>
 <20130508182007.GO18614@n2100.arm.linux.org.uk>
 <518A9A83.5010306@zytor.com> <20130509112048.GT3672@sgi.com>
 <20130509130120.GW3672@sgi.com>
 <20130509133643.GU18614@n2100.arm.linux.org.uk>
Message-ID: <20130509155931.GY3672@sgi.com>

On Thu, May 09, 2013 at 02:36:43PM +0100, Russell King - ARM Linux wrote:
> On Thu, May 09, 2013 at 08:01:20AM -0500, Robin Holt wrote:
> > diff --git a/include/linux/reboot.h b/include/linux/reboot.h
> > index 26cf11b..bc77231 100644
> > --- a/include/linux/reboot.h
> > +++ b/include/linux/reboot.h
> > @@ -15,6 +15,23 @@ enum reboot_mode {
> > +extern enum reboot_type reboot_type;
> > +
> > +extern int reboot_default;
> > +extern int reboot_cpu;
> > +extern int reboot_force;
> 
> Okay, these are globals...
> 
> > diff --git a/kernel/reboot.c b/kernel/reboot.c
> > index 0a97794..ff08af2 100644
> > --- a/kernel/reboot.c
> > +++ b/kernel/reboot.c
> > @@ -87,7 +88,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
> >  static void migrate_to_reboot_cpu(void)
> >  {
> >  	/* The boot cpu is always logical cpu 0 */
> > -	int reboot_cpu = 0;
> > +	int reboot_cpu = reboot_cpu;
> 
> Hmm, are you sure about that?

Again, I am an idiot.  I will fix this.  Thank you.

> > @@ -343,3 +344,80 @@ int orderly_poweroff(bool force)
> >  	return 0;
> >  }
> >  EXPORT_SYMBOL_GPL(orderly_poweroff);
> > +
> > +int reboot_default;
> > +enum reboot_mode reboot_mode = REBOOT_COLD;
> > +int reboot_cpu;
> > +enum reboot_type reboot_type = BOOT_ACPI;
> > +int reboot_force;
> 
> As you seem to want to reference these above, wouldn't it make sense to
> move them higher in the file?
> 
> > +		case 'c':
> > +		case 'h':
> > +			reboot_mode = REBOOT_COLD;
> > +			break;
> 
> I'm still not entirely convinced by making "hard" and "cold" mean the
> same thing, likewise "soft" and "warm".  As I previously explained but
> everyone seems to have ignored, solely focusing on the 's' problem
> instead.

OK.  I took your earlier comments to mean you would tolerate this patch
as is.  I will make the -v9 introduce REBOOT_HARD, REBOOT_SOFT and make
their meaning consistent with what is there now.

Thanks,
Robin


From tony at atomide.com  Thu May  9 12:05:52 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 09:05:52 -0700
Subject: [RFC PATCH 0/3] ARM: omap3: add Seagate Wireless Plus board
In-Reply-To: <20130509155645.GB31554@atomide.com>
References: <cover.1368038129.git.jason@lakedaemon.net>
 <20130508194504.GD32546@atomide.com>
 <20130509003606.GE31290@titan.lakedaemon.net>
 <20130509155645.GB31554@atomide.com>
Message-ID: <20130509160551.GC31554@atomide.com>

* Tony Lindgren <tony at atomide.com> [130509 09:03]:
> * Jason Cooper <jason at lakedaemon.net> [130508 17:41]:
> > On Wed, May 08, 2013 at 12:45:04PM -0700, Tony Lindgren wrote:
> > > * Jason Cooper <jason at lakedaemon.net> [130508 12:29]:
> > > > 
> > > > Tony has been helping me out offline with this, and he suggested trying the
> > > > gpmc against Linus' ToT.  Which locks up before it even has a chance to get
> > > > going.  So this series is against v3.9.
> > > 
> > > You may have better luck with today's mainline treeand the following fix:
> > > 
> > > http://lkml.org/lkml/2013/5/8/374#
> > 
> > Ok, I'm attempting to do that, but got this for 'make dtbs':
> > 
> > ERROR (phandle_references): Reference to non-existent node or label "usb2_phy"
> > 
> > ERROR: Input tree has errors, aborting (use -f to force output)
> > make[1]: *** [arch/arm/boot/dts/omap3-wireless_plus.dtb] Error 2
> > make[1]: *** Waiting for unfinished jobs....
> > make: *** [dtbs] Error 2
> > 
> > which was created by:
> > 
> >   ad871c10 ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
> > 
> > It assumes the board has twl4030 (and then includes it).  Bootlogs from
> > the vendor provided kernel don't show a single message from twl4030, so
> > I've omitted it.
> > 
> > Assuming I did the correct thing by omitting the twl4030, I think the
> > correct answer is to declare the phy in the dts files, like so:
> 
> Thanks, that is correct. We should not assume any PMIC with a processor
> as it can also be a custom chip. For example, Nokia n8x0 is using their
> retu + tahvo chips instead of tps chips.
> 
> I'll apply your patch into omap-for-v3.10/fixes.

I mean omap-for-v3.10/dt-fixes instead of fixes since it's .dts changes.
 
> Regards,
> 
> Tony
>  
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From olof at lixom.net  Thu May  9 12:13:08 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 09:13:08 -0700
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
 <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>
Message-ID: <CAOesGMiqrXSPdEtUzGCuAuhdE4K7FVe65zMM962XuOrO555hnQ@mail.gmail.com>

On Thu, May 9, 2013 at 6:25 AM, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Mon, May 6, 2013 at 9:12 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
>> On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>>
>>> My conclusion is that build and boot test systems just don't work in an
>>> open source environment as no one actively checks the results.  Why would
>>> they - maintainers already have enough to do with reading 6500+ emails a
>>> month on mailing lists.  Why bother going to look at a website as well
>>> which might give even more work.
>>
>> Point taken. I was in a discussion some time back with Greg and some
>> other people and we concluded that unless the system mails you when
>> something breaks it won't make a difference. And it mustn't flood you,
>> just be very precise.
>>
>> Actually the autobuilder at kernel.org helped me out but then stopped
>> building my trees at some point, but that was nice and the same thing
>> doing boots would be great.
>
> +1 on what has already been stated on this thread; An autobuilder does
> work if it emails you when something breaks without spamming you. I've
> also found the 0day build tester actually effective. It has caught
> things that I've missed and I immediately was able to go an fix.

Yes, a builder is quite useful. Several of us do our own builds as well.

When it comes to boot coverage, I'm not sure how successful a central
approach would be. It's something where I think Linaro could
contribute a lot for their member platforms, but I haven't seen much
engagement there yet.

Beyond there, I'd say the expectation is that each maintainer should
keep an eye on their own platforms. They _should_ try building and
booting linux-next on their platforms, to catch regressions early. And
definitely around now, I'd like to see people boot mainline on their
platforms to make sure we haven't added any severe regressions in the
3.10 merge window, etc. Some people are really good at this, others
less so.

What's the old saying, you can lead a horse to water but you can't
make him drink? You can build a boot test cluster but you can't make
anyone pay attention to it. :(

-Olof


From robert.jarzmik at free.fr  Thu May  9 12:35:12 2013
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Thu, 09 May 2013 18:35:12 +0200
Subject: [PATCH 1/2] Revert "drivers/rtc/rtc-pxa.c: fix set time sync time
 issue"
In-Reply-To: <1367889447-15619-2-git-send-email-chao.xie@marvell.com> (Chao
 Xie's message of "Mon, 6 May 2013 21:17:26 -0400")
References: <1367889447-15619-1-git-send-email-chao.xie@marvell.com>
 <1367889447-15619-2-git-send-email-chao.xie@marvell.com>
Message-ID: <877gj8i01r.fsf@free.fr>

Chao Xie <chao.xie at marvell.com> writes:

> This patch have something wrong.
> 1.The pxa_sync_time API is not needed. The RTC sync can be done
> by user space applications, so in kernel this API is not needed.
> 2.The pxa_rtc_open can not be deleted. This change has been
> declined during review at the mail list
> 3.Based on specification and talked with owner of driver, it
> does not matter to set WOM and DOW.
>
> Only need to keep PSBR control for pxa95x
>
> This reverts commit 57489fabb7f3fc02483df2125fdbfb8b1bb1fcd8.

This commit doesn't exist in Linus's tree. Maybe in linux-next ?

Anyway, as you are reverting, please consider this :
the commit that exists is : c4243de70f7d536d95196b8a31539298bb15238c
"drivers/rtc/rtc-pxa.c: drivers/rtc/rtc-pxa.c: fix alarm not match issue".

This commit should be reverted :
 - because it's wrong :
   > tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
   See how RYCR is used with a RDCR mask ...

 - because as maintainer I have already nacked this kind of patch :
   https://patchwork.kernel.org/patch/1819851/
   The reasons given here are still valid AFAIK.

I'm pretty sure I didn't receive this patch in my mailbox. After I refused
ChaoXie first patch, the second "same approach" patch from Liangs was sent in my
back. I don't understand how that could happen ...

Liangs, please make sure to add me to the reviewers next time ?

Cheers.

--
Robert


From jaswinder.singh at linaro.org  Thu May  9 12:35:27 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Thu, 9 May 2013 22:05:27 +0530
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <518AFB1F.7010409@ti.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
 <518976B9.2030605@ti.com>
 <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>
 <518AFB1F.7010409@ti.com>
Message-ID: <CAJe_ZheEZo7Akri40ixBhWzeefABxiJXG1Juc4zQOPNQqyahUw@mail.gmail.com>

Hi Suman,

On 9 May 2013 06:55, Suman Anna <s-anna at ti.com> wrote:

>> so it can't be driven by the controller. We could make it a Kconfig option.
>> What do you suggest?
>
> I am saying controller/link because they are the ones that knows how the
> physical transport is, and it may vary from one to another. I would
> think that the client dependencies would become a subset of this.
> Kconfig option is fine, but we have to think about the best way of
> representing it from a multi-platform kernel support perspective.
>
Actually it has more to do with clients and less with multiplatform.
Even on single platform the client that needs biggest buffer will
rule. Ditto on multi-platform.
Anyways I get your idea. I'll put a note there to revisit once number
of active clients increase on the platform.


>> As I said the API shouldn't keep internal copies of a client's
>> requests - it will only kill zero-copy use-cases while adding
>> complexity to the core.
>
> This is the reason I was suggesting the nature be dictated by a
> controller, rather than 1 design in core code mandating a certain usage.
> The client & controller together would know the functional integration
> aspect.
>
>> Since it already works fine for OMAP, I request we leave it as such
>> for now at least.
>
> OK, we should make a note of it in some documentation.
>
OK, will do. Thanks.


>>> IMHO. It's calling ipc_links_register twice on the same controller. Idea
>>> was that the API would distinguish different controllers, not the same
>>> one. Also, see the above example if you were to treat a link as Rx or Tx
>>> only (functional behavior differences even though the link is exactly
>>> the same type).
>>>
>> Why is calling ipc_links_register() twice, for a controller with 2
>> classes of links, a problem ?
>
> It will be inelegant, once you start maintaining the list of
> ipc_controllers in the core code. You would have to search all the
> controllers in the list with the matching name, and their links. You
> will need to define multiple controller specific controller structures
> and copy most of the elements from the actual h/w device into the
> containing ipc_controller definition. As you said, the clients deal with
> the links themselves, so making the ops part of the ipc_link definition
> makes it easier on the controller implementations. You are anyway
> caching the ops in ipc_chan (per link) and that is what you are using in
> the core code. Majority of the time, you would be using the same ops for
> all the links, but this gives the flexibility to links. You can avoid
> having multiple controller instance denoting the h/w block, just because
> of the difference in links behavior.
>
I don't see it as an issue, it's just how the code is designed on the
principle that the API works only on links, not controllers. Let us
wait for the driver of such a controller to show up. It should be easy
to change if we see the need.


>>
>> And, No, the API need not know if the link is "RX" or "TX", which is
>> purely a logical function.
>>
>> Please do tell me which controller physically limits its links to do
>> only "RX" or only "TX"?  It's just the platform's firmware that
>> dictates who sends and who receives on which link, thereby giving the
>> illusion of a link being a "RX" or "TX" capable only.
>> Even if some h/w limits do exist on links of some controller, still
>> the API shouldn't try to discern a "RX" from a "TX" link. When a
>> client knows which link to open, it will also know if it should read
>> or write to it - this assumption already holds true. If the client
>> writes on a link that it's supposed to listen to remote on, no amount
>> of policing by the API could help.
>>
>> Even if the API tries to differentiate "RX" and "TX" links, the
>> knowledge must come from a client (it's driven by the protocol on the
>> platform), and not the controller because each of its links are
>> physically equally capable to do RX or TX on each end.
>
> The API never differentiates, but the controller implementation has to.
> From a controller driver implementation perspective, you still have to
> make sure that no client is calling an op on which it is not supposed
> to. When you have a mixture like this, a common code would include some
> dead paths for certain links.
>
No, please. The controller driver should not implement any policy (of
allowing/disallowing requests). It should simply try to do as
directed. If the client screwed up even after getting info from
platform_data/DT, let it suffer.


>>>> Yes, I have 2 types of controllers and I already thought about
>>>> multiple controllers in a platform.
>>>>  What do you expect to do in controller startup/shutdown? Since the
>>>> API works on individual links, not the controllers, when would it call
>>>> controller_start() and controller_shutdown()?  The ipc_link's
>>>> startup/shutdown are already non-atomic, if the controller needs any
>>>> setup it could do it in the first link's startup and teardown in the
>>>> last link's shutdown. Not to forget the resources lke IRQ are usually
>>>> per Link which should be acquired/released upon link's use/idle.
>>>>  While writing the OMAP2 controller driver, did I miss any controller
>>>> startup/shutdown ?
>>>
>>> It just delineates the code better, and has flexibility later on to
>>> extend any controller ops or exposing new controller-specific API. The
>>> controller start and stop will be called in the same function as
>>> ipc_request_channel.
>>>
>> Already one call ipc_link_ops.startup() reaches the controller upon
>> ipc_request_channel.
>>
>> Do you mean ?
>>        ipc_con_ops.startup();
>>        ipc_link_ops.startup();
>
> Yes.
>
And let the controller startup()/shutdown() upon every
link_request/release?  If no, then the ipc_con_ops.startup() will be
really executed only upon probe or resume, which is controller
driver's internal matter.

BTW, I have seen my 2 controllers, OMAP, PL320 and read the dbx500
driver. Unsurprisingly none of these have any use for what you call a
special ipc_con_ops.startup().  Lets say if the call were there, what
would the OMAP put in it?


>>> Yeah, the pm_runtime_enable cannot be called twice when mailbox is
>>> invoked from multiple clients on separate links, so there has to a
>>> controller-level logic/ref-counting for that. The clocking for us is on
>>> the controller.
>>>
>> No.  You could call pm_runtime_enable/disable any number of times as
>> long as they are balanced. The core does refcounting.
>
> Exactly, as long as they are balanced. I have two clients dealing with
> two remotes (using two links) so pm_runtime_enable on the h/w block
> needs to be called only when the first one comes in.
>
Actually you just gave another reason why the API messing around with
controller's power state is a bad idea.
See how mailbox_startup() tries to balance mbox->ops->startup() and
mailbox_fini() the mbox->ops->shutdown()  That's very fragile and the
cause of imbalance between rpm enable/disable, unless your clients are
buggy.

Regards,
-Jassi


From s-anna at ti.com  Thu May  9 12:31:07 2013
From: s-anna at ti.com (Suman Anna)
Date: Thu, 9 May 2013 11:31:07 -0500
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <518BCF4B.1060504@ti.com>

Hi Jassi,

On 05/06/2013 02:24 AM, Jassi Brar wrote:
> +++ b/include/linux/mailbox_client.h
> @@ -0,0 +1,85 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MAILBOX_CLIENT_H
> +#define __MAILBOX_CLIENT_H
> +
> +#include <linux/mailbox.h>
> +
> +/**
> + * struct ipc_client - User of a mailbox
> + * @chan_name: the "controller:channel" this client wants
> + * @rxcb: atomic callback to provide client the data received
> + * @txcb: atomic callback to tell client of data transmission
> + * @tx_block: if the ipc_send_message should block until data is transmitted
> + * @tx_tout: Max block period in ms before TX is assumed failure
> + * @knows_txdone: if the client could run the TX state machine. Usually if
> + *    the client receives some ACK packet for transmission. Unused if the
> + *    controller already has TX_Done/RTR IRQ.
> + * @cntlr_data: Optional controller specific parameters during channel request
> + */
> +struct ipc_client {
> +	char *chan_name;
> +	void (*rxcb)(void *data);
> +	void (*txcb)(request_token_t t, enum xfer_result r);

We have to introduce a callback data pointer, so that the calling
clients can retrieve a context object variable or some other useful
data within the callback functions, just like most normal callback
function declarations and registrations do.

> +	bool tx_block;
> +	unsigned long tx_tout;
> +	bool knows_txdone;
> +	void *cntlr_data;
> +};

regards
Suman






From grant.likely at secretlab.ca  Thu May  9 12:39:03 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 9 May 2013 17:39:03 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <20130509141444.GV18614@n2100.arm.linux.org.uk>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
 <20130509141444.GV18614@n2100.arm.linux.org.uk>
Message-ID: <CACxGe6sO7kEZgg6km4bzP1cq+2MqGb=D4cZbuWELoz+yhaO6KQ@mail.gmail.com>

On Thu, May 9, 2013 at 3:14 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, May 09, 2013 at 02:50:17PM +0100, Mark Brown wrote:
>> On Thu, May 09, 2013 at 12:50:46PM +0100, Grant Likely wrote:
>>
>> > However, if a device that shuts down resources after init has
>> > completed and then cannot turn those resources back on when another
>> > driver requests them then it sounds like there is a bigger design
>> > problem. We're in a hotplug world and most of the time a driver cannot
>> > assume that a resource will never get requested after initcalls have
>> > completed. It sounds like a design bug in the driver if it cannot
>> > handle that use case.
>>
>> Even if the driver copes fine it can still be desirable to avoid the
>> power down/up cycle if it involves some user visible effect - things
>> like blinking the display off then on for example.  That said I am a
>> little suspicious about this approach, it doesn't feel as robust as it
>> should to go round individual callers.
>
> What if the driver for something like your display is a module which
> needs to be loaded from userland?
>
> Where the design bug lies is in the "lets probe all the drivers and then
> shut down resources which drivers haven't claimed".  That contains an
> implied assumption: that all drivers have been loaded and probed at the
> point where you shut down those resources.
>
> That simply may not be true in todays kernel - it's not true for a start
> if you have modular drivers, and you have built most of the drivers as
> modules (as a distro would want to with single zImage).  It's
> coincidentally not true if you have deferred probing and some drivers
> defer.
>
> The real problem is this: at what point has the system actually finished
> "booting" in the sense that all drivers for a platform have been
> initialised?  With user loadable modules and deferred probing, that's
> actually a very fuzzy concept.
>
> As you can't really tell when that point has been reached, how can you
> decide to shut down resources which "aren't being used" in a sane way
> without avoiding the down/up cycle?  Basically, you can't.
>
> So, trying to solve the problem may be totally fruitless because you
> can't actually solve it - you can only put a sticky plaster over it and
> hope that it catches most of the problem.  But reality is that you can't
> have both a shutdown of unused resources _and_ avoid the down/up cycle.

+1. You can /minimize/ up-down cycles with the kind of optimization
that is being attempted here, but the driver still *must* deal with
bringing resources back up if they get requested "later than you would
otherwise like".

g.



--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From jaswinder.singh at linaro.org  Thu May  9 12:41:10 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Thu, 9 May 2013 22:11:10 +0530
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <518BCF4B.1060504@ti.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
 <518BCF4B.1060504@ti.com>
Message-ID: <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>

On 9 May 2013 22:01, Suman Anna <s-anna at ti.com> wrote:
> Hi Jassi,
>
> On 05/06/2013 02:24 AM, Jassi Brar wrote:
>> +++ b/include/linux/mailbox_client.h
>> @@ -0,0 +1,85 @@
>> +/*
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#ifndef __MAILBOX_CLIENT_H
>> +#define __MAILBOX_CLIENT_H
>> +
>> +#include <linux/mailbox.h>
>> +
>> +/**
>> + * struct ipc_client - User of a mailbox
>> + * @chan_name: the "controller:channel" this client wants
>> + * @rxcb: atomic callback to provide client the data received
>> + * @txcb: atomic callback to tell client of data transmission
>> + * @tx_block: if the ipc_send_message should block until data is transmitted
>> + * @tx_tout: Max block period in ms before TX is assumed failure
>> + * @knows_txdone: if the client could run the TX state machine. Usually if
>> + *    the client receives some ACK packet for transmission. Unused if the
>> + *    controller already has TX_Done/RTR IRQ.
>> + * @cntlr_data: Optional controller specific parameters during channel request
>> + */
>> +struct ipc_client {
>> +     char *chan_name;
>> +     void (*rxcb)(void *data);
>> +     void (*txcb)(request_token_t t, enum xfer_result r);
>
> We have to introduce a callback data pointer, so that the calling
> clients can retrieve a context object variable or some other useful
> data within the callback functions, just like most normal callback
> function declarations and registrations do.
>
I meant the request_token_t for the purpose. That's how we do with DMAEngine.

Regards,
-Jassi


From s-anna at ti.com  Thu May  9 12:40:55 2013
From: s-anna at ti.com (Suman Anna)
Date: Thu, 9 May 2013 11:40:55 -0500
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
 <518BCF4B.1060504@ti.com>
 <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>
Message-ID: <518BD197.2030502@ti.com>

On 05/09/2013 11:41 AM, Jassi Brar wrote:
> On 9 May 2013 22:01, Suman Anna <s-anna at ti.com> wrote:
>> Hi Jassi,
>>
>> On 05/06/2013 02:24 AM, Jassi Brar wrote:
>>> +++ b/include/linux/mailbox_client.h
>>> @@ -0,0 +1,85 @@
>>> +/*
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + */
>>> +
>>> +#ifndef __MAILBOX_CLIENT_H
>>> +#define __MAILBOX_CLIENT_H
>>> +
>>> +#include <linux/mailbox.h>
>>> +
>>> +/**
>>> + * struct ipc_client - User of a mailbox
>>> + * @chan_name: the "controller:channel" this client wants
>>> + * @rxcb: atomic callback to provide client the data received
>>> + * @txcb: atomic callback to tell client of data transmission
>>> + * @tx_block: if the ipc_send_message should block until data is transmitted
>>> + * @tx_tout: Max block period in ms before TX is assumed failure
>>> + * @knows_txdone: if the client could run the TX state machine. Usually if
>>> + *    the client receives some ACK packet for transmission. Unused if the
>>> + *    controller already has TX_Done/RTR IRQ.
>>> + * @cntlr_data: Optional controller specific parameters during channel request
>>> + */
>>> +struct ipc_client {
>>> +     char *chan_name;
>>> +     void (*rxcb)(void *data);
>>> +     void (*txcb)(request_token_t t, enum xfer_result r);
>>
>> We have to introduce a callback data pointer, so that the calling
>> clients can retrieve a context object variable or some other useful
>> data within the callback functions, just like most normal callback
>> function declarations and registrations do.
>>
> I meant the request_token_t for the purpose. That's how we do with DMAEngine.

I faced this issue on the rxcb while adopting the
omap_rproc_mbox_callback. omap_remoteproc is a common driver for all the
OMAP co-processors and there can be multiple instances, providing the
same set of features. Look at the code in
drivers/remoteproc/omap_remoteproc.c and you will get the idea. But in
general, the users registering callback functions would prefer to get
some context pointer back.

regards
Suman



From skannan at codeaurora.org  Thu May  9 12:52:35 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Thu, 09 May 2013 09:52:35 -0700
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
Message-ID: <518BD453.2010602@codeaurora.org>

On 05/09/2013 04:50 AM, Grant Likely wrote:
> On Thu, May 9, 2013 at 11:07 AM, Ming Lei <tom.leiming at gmail.com> wrote:
>> On Thu, May 9, 2013 at 1:18 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
>>>
>>> The most obvious fallback of using late_initcall_sync() also doesn't work
>>> since the deferred probing work initated during late_initcall() is done in
>>> a workqueue. So, frameworks that want to wait for all devices to finish
>>> probing during init will now have to wait for the deferred workqueue to
>>> finish it's work. This patch adds a wait_for_init_deferred_probe_done() API
>>
>> flush_workqueue() has been added in deferred_probe_initcall(), so looks it
>> should be OK for your problem, doesn't it?
>
> It looks like Saravana is using a kernel that already does that based
> on object bb5645e from the diff. So if he is still having problem,
> then there is probably another deferred probe that is triggered after
> the deferred probe lateinitcall is executed. It would be good to know
> what driver is getting deferred past clearing the queue. Or has this
> been rebased from an earlier kernel? It may no longer be necessary.

Sorry, it was mindless rebase late at night. I missed the addition of 
the flush_workqueue(). That takes care of my immediate needs. Sorry for 
wasting your time.

But the other patches to move clock and regulator calls to 
late_init_sync should still be necessary. Right? Or are we going to 
depend on the Makefile ordering to determine the order of the lateinit 
calls? (I would rather not).

But the rest of the discussion is still interesting and relevant and 
something I would like to see resolved too. I'll reply to that part of 
the discussion in one of the later emails.

Thanks,
Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From jassisinghbrar at gmail.com  Thu May  9 13:48:18 2013
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Thu, 9 May 2013 23:18:18 +0530
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <518BD197.2030502@ti.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
 <518BCF4B.1060504@ti.com>
 <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>
 <518BD197.2030502@ti.com>
Message-ID: <CABb+yY2CnO5RiQNdcB_L5ZiGi829Ys0ODH2UmhtZxj=aJo3ioQ@mail.gmail.com>

On Thu, May 9, 2013 at 10:10 PM, Suman Anna <s-anna at ti.com> wrote:
> On 05/09/2013 11:41 AM, Jassi Brar wrote:
>> On 9 May 2013 22:01, Suman Anna <s-anna at ti.com> wrote:
>>> Hi Jassi,
>>>
>>> On 05/06/2013 02:24 AM, Jassi Brar wrote:
>>>> +++ b/include/linux/mailbox_client.h
>>>> @@ -0,0 +1,85 @@
>>>> +/*
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License version 2 as
>>>> + * published by the Free Software Foundation.
>>>> + */
>>>> +
>>>> +#ifndef __MAILBOX_CLIENT_H
>>>> +#define __MAILBOX_CLIENT_H
>>>> +
>>>> +#include <linux/mailbox.h>
>>>> +
>>>> +/**
>>>> + * struct ipc_client - User of a mailbox
>>>> + * @chan_name: the "controller:channel" this client wants
>>>> + * @rxcb: atomic callback to provide client the data received
>>>> + * @txcb: atomic callback to tell client of data transmission
>>>> + * @tx_block: if the ipc_send_message should block until data is transmitted
>>>> + * @tx_tout: Max block period in ms before TX is assumed failure
>>>> + * @knows_txdone: if the client could run the TX state machine. Usually if
>>>> + *    the client receives some ACK packet for transmission. Unused if the
>>>> + *    controller already has TX_Done/RTR IRQ.
>>>> + * @cntlr_data: Optional controller specific parameters during channel request
>>>> + */
>>>> +struct ipc_client {
>>>> +     char *chan_name;
>>>> +     void (*rxcb)(void *data);
>>>> +     void (*txcb)(request_token_t t, enum xfer_result r);
>>>
>>> We have to introduce a callback data pointer, so that the calling
>>> clients can retrieve a context object variable or some other useful
>>> data within the callback functions, just like most normal callback
>>> function declarations and registrations do.
>>>
>> I meant the request_token_t for the purpose. That's how we do with DMAEngine.
>
> I faced this issue on the rxcb while adopting the
> omap_rproc_mbox_callback. omap_remoteproc is a common driver for all the
> OMAP co-processors and there can be multiple instances, providing the
> same set of features. Look at the code in
> drivers/remoteproc/omap_remoteproc.c and you will get the idea. But in
> general, the users registering callback functions would prefer to get
> some context pointer back.
>
Of course they do. The request_token_t returned corresponds to the
request they submit via ipc_send_message.

Perhaps we should change the following

   void ipc_link_txdone(struct ipc_link *link, enum xfer_result r)
to
   void ipc_link_txdone(struct ipc_link *link, enum xfer_result r, void *data)

So that the API could pass that onto clients ?

regards,
jassi


From fathi.boudra at linaro.org  Thu May  9 13:51:57 2013
From: fathi.boudra at linaro.org (Fathi Boudra)
Date: Thu, 9 May 2013 20:51:57 +0300
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CAOesGMiqrXSPdEtUzGCuAuhdE4K7FVe65zMM962XuOrO555hnQ@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org>
 <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
 <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>
 <CAOesGMiqrXSPdEtUzGCuAuhdE4K7FVe65zMM962XuOrO555hnQ@mail.gmail.com>
Message-ID: <CAGNsrLDw0_yX9nkLYDg0e8-551P7r43UxziTp1TXyyxdiKR5nA@mail.gmail.com>

On 9 May 2013 19:13, Olof Johansson <olof at lixom.net> wrote:
> On Thu, May 9, 2013 at 6:25 AM, Grant Likely <grant.likely at secretlab.ca> wrote:
>> On Mon, May 6, 2013 at 9:12 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
>>> On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
> Yes, a builder is quite useful. Several of us do our own builds as well.
>
> When it comes to boot coverage, I'm not sure how successful a central
> approach would be. It's something where I think Linaro could
> contribute a lot for their member platforms, but I haven't seen much
> engagement there yet.

My previous post was lost. Sorry to repost..

We've got a jenkins instance doing daily builds on various trees and
boot testing on the few boards we've got in the lab:
https://ci.linaro.org/jenkins/view/kernel-ci/

But it hasn't attracted much interest so far... It's been here since a year.

> Beyond there, I'd say the expectation is that each maintainer should
> keep an eye on their own platforms. They _should_ try building and
> booting linux-next on their platforms, to catch regressions early. And
> definitely around now, I'd like to see people boot mainline on their
> platforms to make sure we haven't added any severe regressions in the
> 3.10 merge window, etc. Some people are really good at this, others
> less so.
>
> What's the old saying, you can lead a horse to water but you can't
> make him drink? You can build a boot test cluster but you can't make
> anyone pay attention to it. :(
>
> -Olof

Cheers,

Fathi


From dmurphy at ti.com  Thu May  9 14:08:23 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Thu, 9 May 2013 13:08:23 -0500
Subject: [PATCHv2] ARM:dts:omap4-panda:Update the LED support for the
 panda DTS
In-Reply-To: <20130508234745.GV32546@atomide.com>
References: <1366229760-4808-1-git-send-email-dmurphy@ti.com>
 <516FBD18.3060501@ti.com> <51703BEF.6050804@ti.com>
 <20130508234745.GV32546@atomide.com>
Message-ID: <518BE617.1080509@ti.com>

Tony
On 05/08/2013 06:47 PM, Tony Lindgren wrote:
> * Dan Murphy <dmurphy at ti.com> [130418 11:35]:
>> On 04/18/2013 04:30 AM, Vincent Stehl? wrote:
>>> On 04/17/2013 10:16 PM, Dan Murphy wrote:
>>>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>>>> are different.
>>> (..)
>>>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> index 03bd60d..0c48f6b 100644
>>>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> (..)
>>>> @@ -135,6 +136,25 @@
>>>>  			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
>>>>  		>;
>>>>  	};
>>>> +
>>>> +	led_gpio_pins: pinmux_leds_pins {
>>>> +		pinctrl-single,pins = <
>>>> +		>;
>>>> +	};
>>>> +};
>>> Hi,
>>>
>>> FYI, there was a recent discussion precisely on this topic, where Tomy
>>> suggested to remove the empty section:
>>> http://marc.info/?l=linux-omap&m=136546635409232&w=2
>>>
>>> Apart from that, I just tested your patch on top of Tomy's
>>> omap-for-v3.10/dt branch and it is working fine for me on PandaBoards
>>> EA3, A4 and ES.
>>>
>>> Tested-by: Vincent Stehl? <v-stehle at ti.com>
>>>
>>> Best regards,
>>>
>>> V.
>>>
>> Thanks for testing Vincent
>>
>> Is there a way to append the data to an already existing node?
>> I do not see a clean way.
> If you have something in omap4-panda-common.dtsi and the same entry
> in the omap4-panda-es.dts, the entries in omap4-panda-es.dts will
> override and append the entries in omap4-panda-common.dtsi.
>
> So I think you can avoid the empty entry that way.
>
> Regards,
>
> Tony
Thanks but the issue is the led entry would not appear in the common file so there is nothing to override.
Can we cleanly append to omap4_pmx_core without overriding the whole node?
I don't want to recreate the pmx_core node in the es file.

Dan

-- 
------------------
Dan Murphy



From grant.likely at secretlab.ca  Thu May  9 14:09:47 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 9 May 2013 19:09:47 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <518BD453.2010602@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <518BD453.2010602@codeaurora.org>
Message-ID: <CACxGe6vPHsyacOkyJb9UGCdqPsYbW90sGG8HcZOZ0mJrV7QWkA@mail.gmail.com>

On Thu, May 9, 2013 at 5:52 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 05/09/2013 04:50 AM, Grant Likely wrote:
>>
>> On Thu, May 9, 2013 at 11:07 AM, Ming Lei <tom.leiming at gmail.com> wrote:
>>>
>>> On Thu, May 9, 2013 at 1:18 PM, Saravana Kannan <skannan at codeaurora.org>
>>> wrote:
>>>>
>>>>
>>>> The most obvious fallback of using late_initcall_sync() also doesn't
>>>> work
>>>> since the deferred probing work initated during late_initcall() is done
>>>> in
>>>> a workqueue. So, frameworks that want to wait for all devices to finish
>>>> probing during init will now have to wait for the deferred workqueue to
>>>> finish it's work. This patch adds a wait_for_init_deferred_probe_done()
>>>> API
>>>
>>>
>>> flush_workqueue() has been added in deferred_probe_initcall(), so looks
>>> it
>>> should be OK for your problem, doesn't it?
>>
>>
>> It looks like Saravana is using a kernel that already does that based
>> on object bb5645e from the diff. So if he is still having problem,
>> then there is probably another deferred probe that is triggered after
>> the deferred probe lateinitcall is executed. It would be good to know
>> what driver is getting deferred past clearing the queue. Or has this
>> been rebased from an earlier kernel? It may no longer be necessary.
>
>
> Sorry, it was mindless rebase late at night. I missed the addition of the
> flush_workqueue(). That takes care of my immediate needs. Sorry for wasting
> your time.
>
> But the other patches to move clock and regulator calls to late_init_sync
> should still be necessary. Right? Or are we going to depend on the Makefile
> ordering to determine the order of the lateinit calls? (I would rather not).

You'll need to make sure the regulator and clocks defer to after all
the late initcalls are complete. That will ensure that the deferred
queue has been processed.

g.


From cdall at cs.columbia.edu  Thu May  9 14:11:01 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Thu, 9 May 2013 11:11:01 -0700
Subject: [RFC PATCH 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130509181101.GA17253@gmail.com>

On Fri, May 03, 2013 at 03:02:52PM +0100, Marc Zyngier wrote:
> As KVM/arm64 is looming on the horizon, it makes sense to move some
> of the common code to a single location in order to reduce duplication.
> 
> The code could live anywhere. Actually, most of KVM is already built
> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
> not exactly talking about style here. But maybe it is time to start
> moving into a less ugly direction.
> 
> The include files must be in a "public" location, as they are accessed
> from non-KVM files (arch/arm/kernel/asm-offsets.c).
> 
> For this purpose, introduce two new locations:
> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>   virt/kvm, so this could be seen as a (very ugly) precedent.
> - include/kvm/  : there is already an include/xen, and while the
>   intent is slightly different, this seems as good a location as
>   any

This overall looks ok, just a few points:

1. Should we have a namespace per arch in the include directory, as in
   include/kvm/arm?

2. We could drop the kvm_ prefix from the include files now

> 
> Eventually, we should probably have independant Makefiles at every
> levels (just like everywhere else in the kernel), but this is just
> the first step.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_host.h                        | 4 ++--
>  arch/arm/kvm/Makefile                                  | 7 ++++---
>  {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
>  {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
>  6 files changed, 8 insertions(+), 7 deletions(-)
>  rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
>  rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
> 
> diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
> index ff49193..4ad51e6 100644
> --- a/arch/arm/include/asm/kvm_host.h
> +++ b/arch/arm/include/asm/kvm_host.h
> @@ -23,7 +23,7 @@
>  #include <asm/kvm_asm.h>
>  #include <asm/kvm_mmio.h>
>  #include <asm/fpstate.h>
> -#include <asm/kvm_arch_timer.h>
> +#include <kvm/kvm_arch_timer.h>
>  
>  #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
>  #define KVM_USER_MEM_SLOTS 32
> @@ -38,7 +38,7 @@
>  #define KVM_NR_PAGE_SIZES	1
>  #define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
>  
> -#include <asm/kvm_vgic.h>
> +#include <kvm/kvm_vgic.h>
>  
>  struct kvm_vcpu;
>  u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
> index 53c5ed8..110d6da 100644
> --- a/arch/arm/kvm/Makefile
> +++ b/arch/arm/kvm/Makefile
> @@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
>  AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
>  AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
>  
> -kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
> +KVM := ../../../virt/kvm
> +kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
>  
>  obj-y += kvm-arm.o init.o interrupts.o
>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
>  obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
> -obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
> -obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
> +obj-$(CONFIG_KVM_ARM_VGIC) += $(addprefix $(KVM)/arm/, vgic.o)
> +obj-$(CONFIG_KVM_ARM_TIMER) += $(addprefix $(KVM)/arm/, arch_timer.o)
> diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/include/kvm/kvm_arch_timer.h
> similarity index 100%
> rename from arch/arm/include/asm/kvm_arch_timer.h
> rename to include/kvm/kvm_arch_timer.h
> diff --git a/arch/arm/include/asm/kvm_vgic.h b/include/kvm/kvm_vgic.h
> similarity index 100%
> rename from arch/arm/include/asm/kvm_vgic.h
> rename to include/kvm/kvm_vgic.h
> diff --git a/arch/arm/kvm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> similarity index 99%
> rename from arch/arm/kvm/arch_timer.c
> rename to virt/kvm/arm/arch_timer.c
> index 49a7516..0728904 100644
> --- a/arch/arm/kvm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -25,8 +25,8 @@
>  #include <clocksource/arm_arch_timer.h>
>  #include <asm/arch_timer.h>
>  
> -#include <asm/kvm_vgic.h>
> -#include <asm/kvm_arch_timer.h>
> +#include <kvm/kvm_vgic.h>
> +#include <kvm/kvm_arch_timer.h>
>  
>  static struct timecounter *timecounter;
>  static struct workqueue_struct *wqueue;
> diff --git a/arch/arm/kvm/vgic.c b/virt/kvm/arm/vgic.c
> similarity index 100%
> rename from arch/arm/kvm/vgic.c
> rename to virt/kvm/arm/vgic.c
> -- 
> 1.8.2.1
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From s-anna at ti.com  Thu May  9 14:05:26 2013
From: s-anna at ti.com (Suman Anna)
Date: Thu, 9 May 2013 13:05:26 -0500
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <CABb+yY2CnO5RiQNdcB_L5ZiGi829Ys0ODH2UmhtZxj=aJo3ioQ@mail.gmail.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
 <518BCF4B.1060504@ti.com>
 <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>
 <518BD197.2030502@ti.com>
 <CABb+yY2CnO5RiQNdcB_L5ZiGi829Ys0ODH2UmhtZxj=aJo3ioQ@mail.gmail.com>
Message-ID: <518BE566.5090504@ti.com>

Jassi,

On 05/09/2013 12:48 PM, Jassi Brar wrote:
> On Thu, May 9, 2013 at 10:10 PM, Suman Anna <s-anna at ti.com> wrote:
>> On 05/09/2013 11:41 AM, Jassi Brar wrote:
>>> On 9 May 2013 22:01, Suman Anna <s-anna at ti.com> wrote:
>>>> Hi Jassi,
>>>>
>>>> On 05/06/2013 02:24 AM, Jassi Brar wrote:
>>>>> +++ b/include/linux/mailbox_client.h
>>>>> @@ -0,0 +1,85 @@
>>>>> +/*
>>>>> + * This program is free software; you can redistribute it and/or modify
>>>>> + * it under the terms of the GNU General Public License version 2 as
>>>>> + * published by the Free Software Foundation.
>>>>> + */
>>>>> +
>>>>> +#ifndef __MAILBOX_CLIENT_H
>>>>> +#define __MAILBOX_CLIENT_H
>>>>> +
>>>>> +#include <linux/mailbox.h>
>>>>> +
>>>>> +/**
>>>>> + * struct ipc_client - User of a mailbox
>>>>> + * @chan_name: the "controller:channel" this client wants
>>>>> + * @rxcb: atomic callback to provide client the data received
>>>>> + * @txcb: atomic callback to tell client of data transmission
>>>>> + * @tx_block: if the ipc_send_message should block until data is transmitted
>>>>> + * @tx_tout: Max block period in ms before TX is assumed failure
>>>>> + * @knows_txdone: if the client could run the TX state machine. Usually if
>>>>> + *    the client receives some ACK packet for transmission. Unused if the
>>>>> + *    controller already has TX_Done/RTR IRQ.
>>>>> + * @cntlr_data: Optional controller specific parameters during channel request
>>>>> + */
>>>>> +struct ipc_client {
>>>>> +     char *chan_name;
>>>>> +     void (*rxcb)(void *data);
>>>>> +     void (*txcb)(request_token_t t, enum xfer_result r);
>>>>
>>>> We have to introduce a callback data pointer, so that the calling
>>>> clients can retrieve a context object variable or some other useful
>>>> data within the callback functions, just like most normal callback
>>>> function declarations and registrations do.
>>>>
>>> I meant the request_token_t for the purpose. That's how we do with DMAEngine.
>>
>> I faced this issue on the rxcb while adopting the
>> omap_rproc_mbox_callback. omap_remoteproc is a common driver for all the
>> OMAP co-processors and there can be multiple instances, providing the
>> same set of features. Look at the code in
>> drivers/remoteproc/omap_remoteproc.c and you will get the idea. But in
>> general, the users registering callback functions would prefer to get
>> some context pointer back.
>>
> Of course they do. The request_token_t returned corresponds to the
> request they submit via ipc_send_message.
> 
> Perhaps we should change the following
> 
>    void ipc_link_txdone(struct ipc_link *link, enum xfer_result r)
> to
>    void ipc_link_txdone(struct ipc_link *link, enum xfer_result r, void *data)
> 
> So that the API could pass that onto clients ?

That's if the controller needs to pass some data back to client. I am
fine with that as well, but I am talking mainly about providing a client
user data ptr back to it during callbacks.

struct ipc_client {
	char *chan_name;
+	void *cl_data; /* store it to ipc_chan as well */
-	void (*rxcb)(void *data);
-	void (*txcb)(request_token_t t, enum xfer_result r);
+	void (*rxcb)(void *cl_data, void *data);
+	void (*txcb)(request_token_t t, enum xfer_result r, void *cl_data);
	...
}

I am obviously interested in the rxcb. The controller implementations do
not see the cl_data.

regards
Suman


From dianders at chromium.org  Thu May  9 14:11:10 2013
From: dianders at chromium.org (Doug Anderson)
Date: Thu, 9 May 2013 11:11:10 -0700
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
In-Reply-To: <1614776.P66h1VoFPp@amdc1227>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
 <CAD=FV=X2n+zHZ3frorwW7L1yybnWWK1=-rWMQJQFus3eNiFFeQ@mail.gmail.com>
 <CAOesGMi=K4iJKjSk3RoynhiCMPPT98v5jADnqZ__TwX_YLw65Q@mail.gmail.com>
 <1614776.P66h1VoFPp@amdc1227>
Message-ID: <CAD=FV=X1XL++O43GBcJK5Js=ci8pfoj=uSADMcqq_jGJEvhXdQ@mail.gmail.com>

Tomasz / Olof,

On Thu, May 9, 2013 at 2:45 AM, Tomasz Figa <t.figa at samsung.com> wrote:
>> Nothing stops you from doing that on your own. I tend to push back
>> onto the maintainers to get them engaged in their own housekeeping,
>> but anyone is free to :)

I will probably leave this to the maintainers at this point...  ;)

>> Yeah, it should -- this is just in transition since 5440 was first out
>> of the gate with pinctrl.
>
> AFAIK, Exynos5440 contains a completely different pin controller block, which
> is not compatible with pinctrl-samsung driver, so I don't see any point of
> moving it under PINCTRL_EXYNOS, which is currently used for Exynos 4210, 4x12
> and 5250, but will be also extended with driver data for S5PV210 as well.
>
> I'd say that CPU_EXYNOS4210, SOC_EXYNOS4212, SOC_EXYNOS4412 and SOC_EXYNOS5250
> should select PINCTRL_EXYNOS and SOC_EXYNOS5440 should be left as is,
> selecting PINCTRL_EXYNOS5440.

OK, sounds reasonable.  I didn't dig into all of the details of the
5440 pin control driver and don't have a user manual in front of me.
I will do as you say.

New patch coming shortly.

-Doug


From skannan at codeaurora.org  Thu May  9 14:12:24 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Thu, 09 May 2013 11:12:24 -0700
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <CACxGe6vPHsyacOkyJb9UGCdqPsYbW90sGG8HcZOZ0mJrV7QWkA@mail.gmail.com>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <518BD453.2010602@codeaurora.org>
 <CACxGe6vPHsyacOkyJb9UGCdqPsYbW90sGG8HcZOZ0mJrV7QWkA@mail.gmail.com>
Message-ID: <518BE708.8040005@codeaurora.org>

On 05/09/2013 11:09 AM, Grant Likely wrote:
> On Thu, May 9, 2013 at 5:52 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
>> On 05/09/2013 04:50 AM, Grant Likely wrote:
>>>
>>> On Thu, May 9, 2013 at 11:07 AM, Ming Lei <tom.leiming at gmail.com> wrote:
>>>>
>>>> On Thu, May 9, 2013 at 1:18 PM, Saravana Kannan <skannan at codeaurora.org>
>>>> wrote:
>>>>>
>>>>>
>>>>> The most obvious fallback of using late_initcall_sync() also doesn't
>>>>> work
>>>>> since the deferred probing work initated during late_initcall() is done
>>>>> in
>>>>> a workqueue. So, frameworks that want to wait for all devices to finish
>>>>> probing during init will now have to wait for the deferred workqueue to
>>>>> finish it's work. This patch adds a wait_for_init_deferred_probe_done()
>>>>> API
>>>>
>>>>
>>>> flush_workqueue() has been added in deferred_probe_initcall(), so looks
>>>> it
>>>> should be OK for your problem, doesn't it?
>>>
>>>
>>> It looks like Saravana is using a kernel that already does that based
>>> on object bb5645e from the diff. So if he is still having problem,
>>> then there is probably another deferred probe that is triggered after
>>> the deferred probe lateinitcall is executed. It would be good to know
>>> what driver is getting deferred past clearing the queue. Or has this
>>> been rebased from an earlier kernel? It may no longer be necessary.
>>
>>
>> Sorry, it was mindless rebase late at night. I missed the addition of the
>> flush_workqueue(). That takes care of my immediate needs. Sorry for wasting
>> your time.
>>
>> But the other patches to move clock and regulator calls to late_init_sync
>> should still be necessary. Right? Or are we going to depend on the Makefile
>> ordering to determine the order of the lateinit calls? (I would rather not).
>
> You'll need to make sure the regulator and clocks defer to after all
> the late initcalls are complete. That will ensure that the deferred
> queue has been processed.
>

Ok, then I guess I'll still need to send out the other 2 patches.

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From egtvedt at samfundet.no  Thu May  9 14:12:40 2013
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Thu, 9 May 2013 20:12:40 +0200
Subject: [PATCH 1/2] atmel_nand: at91/avr32/: Replace
 cpu_is_at32ap7000() with a nand platform data
In-Reply-To: <1368084895-18266-2-git-send-email-josh.wu@atmel.com>
References: <1368084895-18266-1-git-send-email-josh.wu@atmel.com>
 <1368084895-18266-2-git-send-email-josh.wu@atmel.com>
Message-ID: <20130509181240.GA4260@samfundet.no>

Around Thu 09 May 2013 15:34:54 +0800 or thereabout, Josh Wu wrote:
> The nand driver use cpu_is_at32ap7000() macro for a workaround. For the
> multi-platform support, we will remove this cpu_is_xxx() macro.
> 
> This patch adds a boolean variable need_reset_workaround in structure
> atmel_nand_data. Using this variable we can remove cpu_is_at32ap7000() macro.
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>

Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>

> ---
>  arch/avr32/mach-at32ap/at32ap700x.c |    3 +++
>  drivers/mtd/nand/atmel_nand.c       |   13 ++++++-------
>  include/linux/platform_data/atmel.h |    3 +++
>  3 files changed, 12 insertions(+), 7 deletions(-)

Feel free to push this through the mtd tree, if they won't accept it I'm
working on getting my workflow up on the linux-avr32.git tree.

<snipp diff>

-- 
HcE


From dianders at chromium.org  Thu May  9 14:12:50 2013
From: dianders at chromium.org (Doug Anderson)
Date: Thu,  9 May 2013 11:12:50 -0700
Subject: [PATCH v3] ARM: exynos: Select PINCTRL_EXYNOS for exynos4/5 at chip
 level
In-Reply-To: <1368039168-24447-1-git-send-email-dianders@chromium.org>
References: <1368039168-24447-1-git-send-email-dianders@chromium.org>
Message-ID: <1368123170-22906-1-git-send-email-dianders@chromium.org>

Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
missing the pincontrol definitions.  Move PINCTRL selects to the arch
level since we should be enabling the code for all exynos variants.

Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not
for exynos5440.  Also add basic dependencies for the PINCTRL_EXYNOS
kernel config.

Signed-off-by: Doug Anderson <dianders at chromium.org>
---
Changes in v3:
- Moved to chip level as per Tomasz.
- Update PINCTRL Kconfig for exynos.

Changes in v2:
- Moved to the arch level as suggested by Olof.

 arch/arm/mach-exynos/Kconfig | 9 ++++++---
 drivers/pinctrl/Kconfig      | 5 +++--
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6e77432..4139d7f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -17,6 +17,7 @@ config ARCH_EXYNOS4
 	select HAVE_ARM_SCU if SMP
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
+	select PINCTRL
 	help
 	  Samsung EXYNOS4 SoCs based systems
 
@@ -24,6 +25,7 @@ config ARCH_EXYNOS5
 	bool "SAMSUNG EXYNOS5"
 	select HAVE_ARM_SCU if SMP
 	select HAVE_SMP
+	select PINCTRL
 	help
 	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
@@ -34,6 +36,7 @@ config CPU_EXYNOS4210
 	default y
 	depends on ARCH_EXYNOS4
 	select ARM_CPU_SUSPEND if PM
+	select PINCTRL_EXYNOS
 	select PM_GENERIC_DOMAINS
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
@@ -45,6 +48,7 @@ config SOC_EXYNOS4212
 	bool "SAMSUNG EXYNOS4212"
 	default y
 	depends on ARCH_EXYNOS4
+	select PINCTRL_EXYNOS
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
 	select SAMSUNG_DMADEV
@@ -55,6 +59,7 @@ config SOC_EXYNOS4412
 	bool "SAMSUNG EXYNOS4412"
 	default y
 	depends on ARCH_EXYNOS4
+	select PINCTRL_EXYNOS
 	select SAMSUNG_DMADEV
 	help
 	  Enable EXYNOS4412 SoC support
@@ -63,6 +68,7 @@ config SOC_EXYNOS5250
 	bool "SAMSUNG EXYNOS5250"
 	default y
 	depends on ARCH_EXYNOS5
+	select PINCTRL_EXYNOS
 	select PM_GENERIC_DOMAINS if PM
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
@@ -78,7 +84,6 @@ config SOC_EXYNOS5440
 	select ARCH_HAS_OPP
 	select ARM_ARCH_TIMER
 	select AUTO_ZRELADDR
-	select PINCTRL
 	select PINCTRL_EXYNOS5440
 	select PM_OPP
 	help
@@ -412,8 +417,6 @@ config MACH_EXYNOS4_DT
 	select CLKSRC_OF
 	select CPU_EXYNOS4210
 	select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
-	select PINCTRL
-	select PINCTRL_EXYNOS
 	select S5P_DEV_MFC
 	select USE_OF
 	help
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f66924..a1c6dd3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,12 +207,13 @@ config PINCTRL_SAMSUNG
 	select PINCONF
 
 config PINCTRL_EXYNOS
-	bool "Pinctrl driver data for Samsung EXYNOS SoCs"
-	depends on OF && GPIOLIB
+	bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
+	depends on OF && GPIOLIB && ARCH_EXYNOS
 	select PINCTRL_SAMSUNG
 
 config PINCTRL_EXYNOS5440
 	bool "Samsung EXYNOS5440 SoC pinctrl driver"
+	depends on SOC_EXYNOS5440
 	select PINMUX
 	select PINCONF
 
-- 
1.8.2.1



From skannan at codeaurora.org  Thu May  9 14:35:01 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Thu,  9 May 2013 11:35:01 -0700
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing is
 done
In-Reply-To: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>

With deferred probing, late_initcall() is too soon to declare a clock as
unused. Wait for deferred probing to finish before declaring a clock as
unused. Since deferred probing is done in late_initcall(), do the unused
check to late_initcall_sync.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
 drivers/clk/clk.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index fe4055f..5ecb64c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -534,7 +534,7 @@ static int clk_disable_unused(void)
 
 	return 0;
 }
-late_initcall(clk_disable_unused);
+late_initcall_sync(clk_disable_unused);
 
 /***    helper functions   ***/
 
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May  9 14:35:02 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Thu,  9 May 2013 11:35:02 -0700
Subject: [PATCH 2/2] regulator: core: Disable unused regulators after deferred
 probing is done
In-Reply-To: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
References: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1368124502-18830-2-git-send-email-skannan@codeaurora.org>

With deferred probing, late_initcall() is too soon to declare a regulator
as unused. Wait for deferred probing to finish before declaring a regulator
as unused. Since deferred probing is done in late_initcall(), do the unused
check to late_initcall_sync.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
 drivers/regulator/core.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index e3661c2..0e85c2c 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -3864,4 +3864,4 @@ unlock:
 
 	return 0;
 }
-late_initcall(regulator_init_complete);
+late_initcall_sync(regulator_init_complete);
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From plagnioj at jcrosoft.com  Thu May  9 14:39:53 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 9 May 2013 20:39:53 +0200
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <20130509150750.GW18614@n2100.arm.linux.org.uk>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
 <20130509141444.GV18614@n2100.arm.linux.org.uk>
 <20130509143702.GE3200@sirena.org.uk>
 <20130509150750.GW18614@n2100.arm.linux.org.uk>
Message-ID: <20130509183953.GH3041@game.jcrosoft.org>

On 16:07 Thu 09 May     , Russell King - ARM Linux wrote:
> On Thu, May 09, 2013 at 03:37:02PM +0100, Mark Brown wrote:
> > On Thu, May 09, 2013 at 03:14:45PM +0100, Russell King - ARM Linux wrote:
> > > On Thu, May 09, 2013 at 02:50:17PM +0100, Mark Brown wrote:
> > 
> > > > Even if the driver copes fine it can still be desirable to avoid the
> > > > power down/up cycle if it involves some user visible effect - things
> > > > like blinking the display off then on for example.  That said I am a
> > > > little suspicious about this approach, it doesn't feel as robust as it
> > > > should to go round individual callers.
> > 
> > > What if the driver for something like your display is a module which
> > > needs to be loaded from userland?
> > 
> > That's clearly a "don't do that then" sort of thing; while we don't want
> > to be unhelpful there's no guarantees with this approach.
> 
> That's not a "don't do that then" thing, because in this case it's
> unreasonable to say that.  The display subsystems like fbdev and
> DRM represent quite a sizable chunk:
> 
> - Base DRM is around 200k.
> - DRM drivers typically around 100k each.
> - Base FBdev is around 100k.
> 
> It won't take long before you're into the territory of having a
> significant portion of your kernel being display drivers of one
> type or other, much of which won't be usable on any one specific
> platform.  So to say "don't build your display drivers as modules"
> is an unreasonable position to take.
> 
> > Yes, exactly - all we're trying to do here is cover the 90% case, not
> > solve all the possible problems since as you say that's not achievable.  
> > There's a clear and reasonable desire to turn off resources we know
> > aren't in use at the current time, but equally well doing so as soon as
> > we start controlling the resources is pretty much guranteed to introduce
> > user visible issues on some systems so it's a question of picking some
> > reasonable point after that.
> 
> I beg to differ on whether it's possible to solve it completely.
> 
> > Another option here which is more in tune with deferred probing and
> > hotplugging would be to switch the delay over to be time based rather
> > than initcall based; do the shutdown at some point based on the time the
> > last resource was registered.  That still won't cover everything
> > though we could make the delay tunable.
> 
> Yuck.  That's crap design.  Really, time based stuff is crap.  I've seen
> this too many times with the gnome crap in Ubuntu 12.04 - where if you
> boot this off SD card it will complain that some applets fail to start
> (and sure enough, half your panel is missing.)  Boot it off eSATA and
> it works 100% reliably.
> 
> Time based stuff to guess when stuff has finished is never a good thing
> and can never be reliable.
> 
> A better solution may be to avoid the problem in kernel space altogether.
> That's already done in the past with the scsi_wait_scan module.  Make the
> the shutdown of stuff a separate loadable module which userspace can load
> at the appropriate time to trigger the shutdown of unused resources.  Or
> provide a different method for userspace to trigger that action.
> 
> With that kind of solution, it is possible to know that the system has
> finished booting (many userspace implementations already do this with
> stuff like not permitting login via network until after the system has
> finished booting despite sshd et.al. already being started.)
I agree with Russell, your bootlaoder setup the splash screen and you did not
load the framebuffer or DRM driver. if you shutdown the clock you loose the
splashscreen

It's a crap way to do

Best Regards,
J.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From tony at atomide.com  Thu May  9 14:45:48 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 11:45:48 -0700
Subject: [PATCHv2] ARM:dts:omap4-panda:Update the LED support for the
 panda DTS
In-Reply-To: <518BE617.1080509@ti.com>
References: <1366229760-4808-1-git-send-email-dmurphy@ti.com>
 <516FBD18.3060501@ti.com> <51703BEF.6050804@ti.com>
 <20130508234745.GV32546@atomide.com> <518BE617.1080509@ti.com>
Message-ID: <20130509184548.GH31554@atomide.com>

* Dan Murphy <dmurphy at ti.com> [130509 11:13]:
>
> Can we cleanly append to omap4_pmx_core without overriding the whole node?
> I don't want to recreate the pmx_core node in the es file.

Yes that should work just fine.

Regards,

Tony


From tony at atomide.com  Thu May  9 14:46:51 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 11:46:51 -0700
Subject: [GIT PULL 1/2] omap fixes for v3.10 merge window part2
Message-ID: <pull-1368125211-439797>

The following changes since commit 956e46efb2478ebff7a871138458fa8124fd18dd:

  mm/slab: Fix crash during slab init (2013-05-08 15:02:33 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/fixes-for-merge-window-part2

for you to fetch changes up to b1dd11d60e5357c13d3f3decfb69bd07dde159bd:

  ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c (2013-05-09 09:06:27 -0700)

----------------------------------------------------------------
Omap fixes for things that were discovered during the merge window:

- Few GPMC fixes and binding doc updates noted after sending
  pull requests for the GPMC branch.

- Board fixes for beagle usb host and rx51 spi probe order

- SoC fixes dt earlyprintk, omap1 dma and omap2+ id.c error
  handling fixes

Then few minor things that are not strictly fixes but are good
to get out of the way:

- Add missing legacy mux registers for am/dm73x gpio

- Add detection for am33xx pg2.1 silicon

- Enable twl4030 audio modules in defconfig

----------------------------------------------------------------
Aaro Koskinen (1):
      ARM: OMAP: RX-51: change probe order of touchscreen and panel SPI devices

Christoph Fritz (1):
      omap: mux: add AM/DM37x gpios

Javier Martinez Canillas (3):
      Documentation: dt: update TI GPMC ethernet binding properties
      ARM: OMAP2+: only search for GPMC DT child nodes on probe
      ARM: OMAP2+: only WARN if a GPMC child probe function fail

Jon Hunter (1):
      Documentation: dt: update properties in TI GPMC NAND example

Kevin Hilman (1):
      ARM: OMAP2+: omap_device: use late_initcall_sync

Peter Ujfalusi (1):
      ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module

Roger Quadros (1):
      ARM: OMAP3: Beagle: Fix USB Host on beagle xM Ax/Bx

Tony Lindgren (2):
      Merge branch 'omap-gpmc-fixes-for-v3.10' of git://github.com/jonhunter/linux into fixes
      ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c

Vaibhav Hiremath (1):
      ARM: OMAP2: AM33XX: id: Add support for new AM335x PG2.1 Si

Wei Yongjun (1):
      ARM: OMAP1: DMA: fix error handling in omap1_system_dma_init()

 .../devicetree/bindings/mtd/gpmc-nand.txt          | 28 +++++------
 Documentation/devicetree/bindings/net/gpmc-eth.txt | 56 +++++++++++-----------
 arch/arm/configs/omap2plus_defconfig               |  2 +
 arch/arm/mach-omap1/dma.c                          |  8 ++--
 arch/arm/mach-omap2/board-omap3beagle.c            |  6 +--
 arch/arm/mach-omap2/board-rx51-peripherals.c       |  4 +-
 arch/arm/mach-omap2/gpmc.c                         | 38 +++++----------
 arch/arm/mach-omap2/id.c                           | 13 +++--
 arch/arm/mach-omap2/mux34xx.h                      |  6 ++-
 arch/arm/mach-omap2/omap_device.c                  |  2 +-
 arch/arm/mach-omap2/soc.h                          |  2 +
 11 files changed, 81 insertions(+), 84 deletions(-)


From tony at atomide.com  Thu May  9 14:46:51 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 11:46:51 -0700
Subject: [GIT PULL 2/2] omap device tree fixes for v3.10 merge window
In-Reply-To: <pull-1368125211-439797>
Message-ID: <mailman.4.1368125244.1125.linux-arm-kernel@lists.infradead.org>

The following changes since commit bb9055b2744ada735a2fe555c4196ad39a83ef2a:

  Merge tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc (2013-05-07 11:28:42 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/dt-fixes-for-merge-window

for you to fetch changes up to 914dc329ee11d6b1ecbebef802962dc06e78b942:

  ARM: dts: don't assume boards are using twl4030 for omap3 (2013-05-09 09:06:57 -0700)

----------------------------------------------------------------
Omap device tree fixes for issue discovered during the merge window:

- Fix triggering for GPIO interrupts that's needed for 4430sdp
  Ethernet. Otherwise booting with nfsroot won't work.

- Fix CPU operating point values

- Fix wrong assumption that twl PMIC is always connected to omap3

- Add gpmc for am33xx so beaglebone users can use the bus

- Cosmetic fix for mcspi pin muxing to avoid confusion

----------------------------------------------------------------
Jason Cooper (1):
      ARM: dts: don't assume boards are using twl4030 for omap3

Jon Hunter (1):
      ARM: dts: OMAP4: Fix ethernet IRQ for OMAP4 boards

Nishanth Menon (2):
      ARM: dts: OMAP36xx: Fix CPU OPP voltages
      ARM: dts: OMAP4460: Fix CPU OPP voltages

Philip Avinash (1):
      ARM: dts: AM33XX: Add GPMC node

Tony Lindgren (1):
      ARM: dts: Configure and fix the McSPI pins for 4430sdp

 arch/arm/boot/dts/am33xx.dtsi         | 12 ++++++++++++
 arch/arm/boot/dts/omap3-beagle-xm.dts |  1 +
 arch/arm/boot/dts/omap3-evm.dts       |  1 +
 arch/arm/boot/dts/omap3-overo.dtsi    |  1 +
 arch/arm/boot/dts/omap3.dtsi          |  1 -
 arch/arm/boot/dts/omap36xx.dtsi       |  6 +++---
 arch/arm/boot/dts/omap4-sdp.dts       | 14 +++++++++++++-
 arch/arm/boot/dts/omap4-var-som.dts   |  2 +-
 arch/arm/boot/dts/omap4460.dtsi       |  6 +++---
 9 files changed, 35 insertions(+), 9 deletions(-)


From jaswinder.singh at linaro.org  Thu May  9 14:49:31 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Fri, 10 May 2013 00:19:31 +0530
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <518BE566.5090504@ti.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
 <518BCF4B.1060504@ti.com>
 <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>
 <518BD197.2030502@ti.com>
 <CABb+yY2CnO5RiQNdcB_L5ZiGi829Ys0ODH2UmhtZxj=aJo3ioQ@mail.gmail.com>
 <518BE566.5090504@ti.com>
Message-ID: <CAJe_Zhffm9FOk83dAdX194gN3r5JnG78sdcWNv6WnWCsTF3YuA@mail.gmail.com>

On 9 May 2013 23:35, Suman Anna <s-anna at ti.com> wrote:

>>
>> Perhaps we should change the following
>>
>>    void ipc_link_txdone(struct ipc_link *link, enum xfer_result r)
>> to
>>    void ipc_link_txdone(struct ipc_link *link, enum xfer_result r, void *data)
>>
>> So that the API could pass that onto clients ?
>
> That's if the controller needs to pass some data back to client. I am
> fine with that as well,
No, I misunderstood you wanted request_token_t to be replaced with the
pointer of request that was executed.

> but I am talking mainly about providing a client
> user data ptr back to it during callbacks.
>
> struct ipc_client {
>         char *chan_name;
> +       void *cl_data; /* store it to ipc_chan as well */
> -       void (*rxcb)(void *data);
> -       void (*txcb)(request_token_t t, enum xfer_result r);
> +       void (*rxcb)(void *cl_data, void *data);
> +       void (*txcb)(request_token_t t, enum xfer_result r, void *cl_data);
>         ...
> }
>
> I am obviously interested in the rxcb. The controller implementations do
> not see the cl_data.
>
OK I see what you mean. However the API storing and passing back
ad-hoc data to clients doesn't seem very neat.

Such purposes are usually served by :

- void (*rxcb)(void *data);
+ void (*rxcb)(struct ipc_client *cl, void *data);  /* client for
which data was received */

- void (*txcb)(request_token_t t, enum xfer_result r);
+ void (*txcb)(struct ipc_client *cl, request_token_t t, enum
xfer_result r); /* client whose data was sent */

You could then get relevant omap_rproc using container_of() on 'cl',
in rxcb() and txcb().


Apart from this, in txcb, perhaps we should drop request_token_t in
favor of the request's pointer (void *data) that was last executed.
That should make things easier for clients.

regards,
-jassi


From holt at sgi.com  Thu May  9 15:23:14 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:14 -0500
Subject: [PATCH -v8 00/11] Shutdown from reboot_cpuid without stopping other
 cpus.
Message-ID: <1368127405-112717-1-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.


Changes since -v8
 - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.

 - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.

 - Fixed case statement bug.

 - Went to using simple_strtoul for parsing reboot_cpu=smp###.

 - Made parsing of reboot= not use any #ifdef'd code.

Changes since -v7.
 - Fixed authorship for first patch.

 - Rebased to Linus' current tree (51a26ae7a).

Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From holt at sgi.com  Thu May  9 15:23:15 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:15 -0500
Subject: [PATCH -v9 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-2-git-send-email-holt@sgi.com>

From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v6:
 - Added a #define for non-hotplug case.
---
 include/linux/cpu.h |  3 +++
 kernel/cpu.c        | 27 +++++++++------------------
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..3e450c0 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -141,6 +141,8 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
 }
 #endif
 
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 int cpu_up(unsigned int cpu);
 void notify_cpu_starting(unsigned int cpu);
 extern void cpu_maps_update_begin(void);
@@ -148,6 +150,7 @@ extern void cpu_maps_update_done(void);
 
 #else	/* CONFIG_SMP */
 
+#define cpu_hotplug_disable()	do { } while (0)
 #define cpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 
 static inline int register_cpu_notifier(struct notifier_block *nb)
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..28769f5 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -541,29 +541,20 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
  */
-void cpu_hotplug_disable_before_freeze(void)
+void cpu_hotplug_disable(void)
 {
 	cpu_maps_update_begin();
 	cpu_hotplug_disabled = 1;
 	cpu_maps_update_done();
 }
 
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
+void cpu_hotplug_enable(void)
 {
 	cpu_maps_update_begin();
 	cpu_hotplug_disabled = 0;
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:16 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:16 -0500
Subject: [PATCH -v9 02/11] Migrate shutdown/reboot to boot cpu.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-3-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
boot cpu and then continuing with shutdown/reboot.

This also has the effect of not breaking x86's command line parameter for
specifying the reboot cpu.  Note, this code was shamelessly copied from
arch/x86/kernel/reboot.c with bits removed pertaining to the reboot_cpu
command line parameter.

Signed-off-by: Robin Holt <holt at sgi.com>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v8
 - Change stack parameter to make future patches cleaner.

Changes since -v6:
 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
 - Fixup s/reboot_cpu_id/reboot_cpu/
---
 kernel/sys.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c7..2bbd9a7 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
 /**
  *	kernel_restart - reboot the system
  *	@cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
 	kernel_restart_prepare(cmd);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
 		printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
 	kernel_shutdown_prepare(SYSTEM_HALT);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
 	if (pm_power_off_prepare)
 		pm_power_off_prepare();
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:17 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:17 -0500
Subject: [PATCH -v9 03/11] Remove -stable friendly PF_THREAD_BOUND define
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-4-git-send-email-holt@sgi.com>

Remove the prior patch's #define for easier backporting to the stable
releases.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 kernel/sys.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index 2bbd9a7..17bb8d3 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,11 +362,6 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
-/* Add backwards compatibility for stable trees. */
-#ifndef PF_NO_SETAFFINITY
-#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
-#endif
-
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:19 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:19 -0500
Subject: [PATCH -v9 05/11] checkpatch.pl the new kernel/reboot.c file.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-6-git-send-email-holt@sgi.com>

Get the new file to pass scripts/checkpatch.pl

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since v6:
 - Removed last remaining line length warning.
---
 include/linux/reboot.h |  2 +-
 kernel/reboot.c        | 28 +++++++++++++---------------
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 23b3630..c6eba21 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -26,7 +26,7 @@ extern void machine_shutdown(void);
 struct pt_regs;
 extern void machine_crash_shutdown(struct pt_regs *);
 
-/* 
+/*
  * Architecture independent implemenations of sys_reboot commands.
  */
 
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 0616483..abb6a04 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -4,6 +4,8 @@
  *  Copyright (C) 2013  Linus Torvalds
  */
 
+#define pr_fmt(fmt)	"reboot: " fmt
+
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -114,9 +116,9 @@ void kernel_restart(char *cmd)
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
+		pr_emerg("Restarting system\n");
 	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+		pr_emerg("Restarting system with command '%s'\n", cmd);
 	kmsg_dump(KMSG_DUMP_RESTART);
 	machine_restart(cmd);
 }
@@ -125,7 +127,7 @@ EXPORT_SYMBOL_GPL(kernel_restart);
 static void kernel_shutdown_prepare(enum system_states state)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
 	usermodehelper_disable();
 	device_shutdown();
@@ -140,11 +142,10 @@ void kernel_halt(void)
 	kernel_shutdown_prepare(SYSTEM_HALT);
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
+	pr_emerg("System halted\n");
 	kmsg_dump(KMSG_DUMP_HALT);
 	machine_halt();
 }
-
 EXPORT_SYMBOL_GPL(kernel_halt);
 
 /**
@@ -159,7 +160,7 @@ void kernel_power_off(void)
 		pm_power_off_prepare();
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
+	pr_emerg("Power down\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
 	machine_power_off();
 }
@@ -188,10 +189,10 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 
 	/* For safety, we require "magic" arguments. */
 	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			(magic2 != LINUX_REBOOT_MAGIC2 &&
+			magic2 != LINUX_REBOOT_MAGIC2A &&
 			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
+			magic2 != LINUX_REBOOT_MAGIC2C))
 		return -EINVAL;
 
 	/*
@@ -234,7 +235,8 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 		break;
 
 	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+		ret = strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1);
+		if (ret < 0) {
 			ret = -EFAULT;
 			break;
 		}
@@ -282,7 +284,6 @@ void ctrl_alt_del(void)
 	else
 		kill_cad_pid(SIGINT, 1);
 }
-	
 
 char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
 
@@ -301,14 +302,11 @@ static int __orderly_poweroff(bool force)
 		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
 		argv_free(argv);
 	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
 		ret = -ENOMEM;
 	}
 
 	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
+		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 		/*
 		 * I guess this should try to kick off some daemon to sync and
 		 * poweroff asap.  Or not even bother syncing if we're doing an
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:18 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:18 -0500
Subject: [PATCH -v9 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-5-git-send-email-holt@sgi.com>

This patch is preparatory.  It moves reboot related syscall, etc
functions from kernel/sys.c to kernel/reboot.c.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v6:
 - Add include of linux/uaccess.h to allow building on arm.
---
 kernel/Makefile |   2 +-
 kernel/reboot.c | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/sys.c    | 331 -----------------------------------------------------
 3 files changed, 348 insertions(+), 332 deletions(-)
 create mode 100644 kernel/reboot.c

diff --git a/kernel/Makefile b/kernel/Makefile
index 271fd31..470839d 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y     = fork.o exec_domain.o panic.o printk.o \
 	    rcupdate.o extable.o params.o posix-timers.o \
 	    kthread.o wait.o sys_ni.o posix-cpu-timers.o mutex.o \
 	    hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-	    notifier.o ksysfs.o cred.o \
+	    notifier.o ksysfs.o cred.o reboot.o \
 	    async.o range.o groups.o lglock.o smpboot.o
 
 ifdef CONFIG_FUNCTION_TRACER
diff --git a/kernel/reboot.c b/kernel/reboot.c
new file mode 100644
index 0000000..0616483
--- /dev/null
+++ b/kernel/reboot.c
@@ -0,0 +1,347 @@
+/*
+ *  linux/kernel/reboot.c
+ *
+ *  Copyright (C) 2013  Linus Torvalds
+ */
+
+#include <linux/export.h>
+#include <linux/kexec.h>
+#include <linux/kmod.h>
+#include <linux/kmsg_dump.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h>
+#include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
+
+/*
+ * this indicates whether you can reboot with ctrl-alt-del: the default is yes
+ */
+
+int C_A_D = 1;
+struct pid *cad_pid;
+EXPORT_SYMBOL(cad_pid);
+
+/*
+ * If set, this is used for preparing the system to power off.
+ */
+
+void (*pm_power_off_prepare)(void);
+
+/**
+ *	emergency_restart - reboot the system
+ *
+ *	Without shutting down any hardware or taking any locks
+ *	reboot the system.  This is called when we know we are in
+ *	trouble so this is our best effort to reboot.  This is
+ *	safe to call in interrupt context.
+ */
+void emergency_restart(void)
+{
+	kmsg_dump(KMSG_DUMP_EMERG);
+	machine_emergency_restart();
+}
+EXPORT_SYMBOL_GPL(emergency_restart);
+
+void kernel_restart_prepare(char *cmd)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
+	system_state = SYSTEM_RESTART;
+	usermodehelper_disable();
+	device_shutdown();
+}
+
+/**
+ *	register_reboot_notifier - Register function to be called at reboot time
+ *	@nb: Info about notifier function to be called
+ *
+ *	Registers a function with the list of functions
+ *	to be called at reboot time.
+ *
+ *	Currently always returns zero, as blocking_notifier_chain_register()
+ *	always returns zero.
+ */
+int register_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(register_reboot_notifier);
+
+/**
+ *	unregister_reboot_notifier - Unregister previously registered reboot notifier
+ *	@nb: Hook to be unregistered
+ *
+ *	Unregisters a previously registered reboot
+ *	notifier function.
+ *
+ *	Returns zero on success, or %-ENOENT on failure.
+ */
+int unregister_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(unregister_reboot_notifier);
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
+/**
+ *	kernel_restart - reboot the system
+ *	@cmd: pointer to buffer containing command to execute for restart
+ *		or %NULL
+ *
+ *	Shutdown everything and perform a clean reboot.
+ *	This is not safe to call in interrupt context.
+ */
+void kernel_restart(char *cmd)
+{
+	kernel_restart_prepare(cmd);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	if (!cmd)
+		printk(KERN_EMERG "Restarting system.\n");
+	else
+		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+	kmsg_dump(KMSG_DUMP_RESTART);
+	machine_restart(cmd);
+}
+EXPORT_SYMBOL_GPL(kernel_restart);
+
+static void kernel_shutdown_prepare(enum system_states state)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list,
+		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+	system_state = state;
+	usermodehelper_disable();
+	device_shutdown();
+}
+/**
+ *	kernel_halt - halt the system
+ *
+ *	Shutdown everything and perform a clean system halt.
+ */
+void kernel_halt(void)
+{
+	kernel_shutdown_prepare(SYSTEM_HALT);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "System halted.\n");
+	kmsg_dump(KMSG_DUMP_HALT);
+	machine_halt();
+}
+
+EXPORT_SYMBOL_GPL(kernel_halt);
+
+/**
+ *	kernel_power_off - power_off the system
+ *
+ *	Shutdown everything and perform a clean system power_off.
+ */
+void kernel_power_off(void)
+{
+	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
+	if (pm_power_off_prepare)
+		pm_power_off_prepare();
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "Power down.\n");
+	kmsg_dump(KMSG_DUMP_POWEROFF);
+	machine_power_off();
+}
+EXPORT_SYMBOL_GPL(kernel_power_off);
+
+static DEFINE_MUTEX(reboot_mutex);
+
+/*
+ * Reboot system call: for obvious reasons only root may call it,
+ * and even root needs to set up some magic numbers in the registers
+ * so that some mistake won't make this reboot the whole machine.
+ * You can also set the meaning of the ctrl-alt-del-key here.
+ *
+ * reboot doesn't sync: do that yourself before calling this.
+ */
+SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
+		void __user *, arg)
+{
+	struct pid_namespace *pid_ns = task_active_pid_ns(current);
+	char buffer[256];
+	int ret = 0;
+
+	/* We only trust the superuser with rebooting the system. */
+	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
+		return -EPERM;
+
+	/* For safety, we require "magic" arguments. */
+	if (magic1 != LINUX_REBOOT_MAGIC1 ||
+	    (magic2 != LINUX_REBOOT_MAGIC2 &&
+	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			magic2 != LINUX_REBOOT_MAGIC2B &&
+	                magic2 != LINUX_REBOOT_MAGIC2C))
+		return -EINVAL;
+
+	/*
+	 * If pid namespaces are enabled and the current task is in a child
+	 * pid_namespace, the command is handled by reboot_pid_ns() which will
+	 * call do_exit().
+	 */
+	ret = reboot_pid_ns(pid_ns, cmd);
+	if (ret)
+		return ret;
+
+	/* Instead of trying to make the power_off code look like
+	 * halt when pm_power_off is not set do it the easy way.
+	 */
+	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
+		cmd = LINUX_REBOOT_CMD_HALT;
+
+	mutex_lock(&reboot_mutex);
+	switch (cmd) {
+	case LINUX_REBOOT_CMD_RESTART:
+		kernel_restart(NULL);
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_ON:
+		C_A_D = 1;
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_OFF:
+		C_A_D = 0;
+		break;
+
+	case LINUX_REBOOT_CMD_HALT:
+		kernel_halt();
+		do_exit(0);
+		panic("cannot halt");
+
+	case LINUX_REBOOT_CMD_POWER_OFF:
+		kernel_power_off();
+		do_exit(0);
+		break;
+
+	case LINUX_REBOOT_CMD_RESTART2:
+		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+			ret = -EFAULT;
+			break;
+		}
+		buffer[sizeof(buffer) - 1] = '\0';
+
+		kernel_restart(buffer);
+		break;
+
+#ifdef CONFIG_KEXEC
+	case LINUX_REBOOT_CMD_KEXEC:
+		ret = kernel_kexec();
+		break;
+#endif
+
+#ifdef CONFIG_HIBERNATION
+	case LINUX_REBOOT_CMD_SW_SUSPEND:
+		ret = hibernate();
+		break;
+#endif
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&reboot_mutex);
+	return ret;
+}
+
+static void deferred_cad(struct work_struct *dummy)
+{
+	kernel_restart(NULL);
+}
+
+/*
+ * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
+ * As it's called within an interrupt, it may NOT sync: the only choice
+ * is whether to reboot at once, or just ignore the ctrl-alt-del.
+ */
+void ctrl_alt_del(void)
+{
+	static DECLARE_WORK(cad_work, deferred_cad);
+
+	if (C_A_D)
+		schedule_work(&cad_work);
+	else
+		kill_cad_pid(SIGINT, 1);
+}
+	
+
+char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
+
+static int __orderly_poweroff(bool force)
+{
+	char **argv;
+	static char *envp[] = {
+		"HOME=/",
+		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
+		NULL
+	};
+	int ret;
+
+	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
+	if (argv) {
+		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
+		argv_free(argv);
+	} else {
+		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
+					 __func__, poweroff_cmd);
+		ret = -ENOMEM;
+	}
+
+	if (ret && force) {
+		printk(KERN_WARNING "Failed to start orderly shutdown: "
+					"forcing the issue\n");
+		/*
+		 * I guess this should try to kick off some daemon to sync and
+		 * poweroff asap.  Or not even bother syncing if we're doing an
+		 * emergency shutdown?
+		 */
+		emergency_sync();
+		kernel_power_off();
+	}
+
+	return ret;
+}
+
+static bool poweroff_force;
+
+static void poweroff_work_func(struct work_struct *work)
+{
+	__orderly_poweroff(poweroff_force);
+}
+
+static DECLARE_WORK(poweroff_work, poweroff_work_func);
+
+/**
+ * orderly_poweroff - Trigger an orderly system poweroff
+ * @force: force poweroff if command execution fails
+ *
+ * This may be called from any context to trigger a system shutdown.
+ * If the orderly shutdown fails, it will force an immediate shutdown.
+ */
+int orderly_poweroff(bool force)
+{
+	if (force) /* do not override the pending "true" */
+		poweroff_force = true;
+	schedule_work(&poweroff_work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(orderly_poweroff);
diff --git a/kernel/sys.c b/kernel/sys.c
index 17bb8d3..467a18f 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -116,20 +116,6 @@ EXPORT_SYMBOL(fs_overflowuid);
 EXPORT_SYMBOL(fs_overflowgid);
 
 /*
- * this indicates whether you can reboot with ctrl-alt-del: the default is yes
- */
-
-int C_A_D = 1;
-struct pid *cad_pid;
-EXPORT_SYMBOL(cad_pid);
-
-/*
- * If set, this is used for preparing the system to power off.
- */
-
-void (*pm_power_off_prepare)(void);
-
-/*
  * Returns true if current's euid is same as p's uid or euid,
  * or has CAP_SYS_NICE to p's user_ns.
  *
@@ -308,261 +294,6 @@ out_unlock:
 	return retval;
 }
 
-/**
- *	emergency_restart - reboot the system
- *
- *	Without shutting down any hardware or taking any locks
- *	reboot the system.  This is called when we know we are in
- *	trouble so this is our best effort to reboot.  This is
- *	safe to call in interrupt context.
- */
-void emergency_restart(void)
-{
-	kmsg_dump(KMSG_DUMP_EMERG);
-	machine_emergency_restart();
-}
-EXPORT_SYMBOL_GPL(emergency_restart);
-
-void kernel_restart_prepare(char *cmd)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
-	system_state = SYSTEM_RESTART;
-	usermodehelper_disable();
-	device_shutdown();
-}
-
-/**
- *	register_reboot_notifier - Register function to be called at reboot time
- *	@nb: Info about notifier function to be called
- *
- *	Registers a function with the list of functions
- *	to be called at reboot time.
- *
- *	Currently always returns zero, as blocking_notifier_chain_register()
- *	always returns zero.
- */
-int register_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(register_reboot_notifier);
-
-/**
- *	unregister_reboot_notifier - Unregister previously registered reboot notifier
- *	@nb: Hook to be unregistered
- *
- *	Unregisters a previously registered reboot
- *	notifier function.
- *
- *	Returns zero on success, or %-ENOENT on failure.
- */
-int unregister_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(unregister_reboot_notifier);
-
-static void migrate_to_reboot_cpu(void)
-{
-	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
-
-	cpu_hotplug_disable();
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(cpu))
-		cpu = cpumask_first(cpu_online_mask);
-
-	/* Prevent races with other tasks migrating this task */
-	current->flags |= PF_NO_SETAFFINITY;
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(cpu));
-}
-
-/**
- *	kernel_restart - reboot the system
- *	@cmd: pointer to buffer containing command to execute for restart
- *		or %NULL
- *
- *	Shutdown everything and perform a clean reboot.
- *	This is not safe to call in interrupt context.
- */
-void kernel_restart(char *cmd)
-{
-	kernel_restart_prepare(cmd);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
-	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
-	kmsg_dump(KMSG_DUMP_RESTART);
-	machine_restart(cmd);
-}
-EXPORT_SYMBOL_GPL(kernel_restart);
-
-static void kernel_shutdown_prepare(enum system_states state)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
-	system_state = state;
-	usermodehelper_disable();
-	device_shutdown();
-}
-/**
- *	kernel_halt - halt the system
- *
- *	Shutdown everything and perform a clean system halt.
- */
-void kernel_halt(void)
-{
-	kernel_shutdown_prepare(SYSTEM_HALT);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
-	kmsg_dump(KMSG_DUMP_HALT);
-	machine_halt();
-}
-
-EXPORT_SYMBOL_GPL(kernel_halt);
-
-/**
- *	kernel_power_off - power_off the system
- *
- *	Shutdown everything and perform a clean system power_off.
- */
-void kernel_power_off(void)
-{
-	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
-	if (pm_power_off_prepare)
-		pm_power_off_prepare();
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
-	kmsg_dump(KMSG_DUMP_POWEROFF);
-	machine_power_off();
-}
-EXPORT_SYMBOL_GPL(kernel_power_off);
-
-static DEFINE_MUTEX(reboot_mutex);
-
-/*
- * Reboot system call: for obvious reasons only root may call it,
- * and even root needs to set up some magic numbers in the registers
- * so that some mistake won't make this reboot the whole machine.
- * You can also set the meaning of the ctrl-alt-del-key here.
- *
- * reboot doesn't sync: do that yourself before calling this.
- */
-SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
-		void __user *, arg)
-{
-	struct pid_namespace *pid_ns = task_active_pid_ns(current);
-	char buffer[256];
-	int ret = 0;
-
-	/* We only trust the superuser with rebooting the system. */
-	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
-		return -EPERM;
-
-	/* For safety, we require "magic" arguments. */
-	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
-			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
-		return -EINVAL;
-
-	/*
-	 * If pid namespaces are enabled and the current task is in a child
-	 * pid_namespace, the command is handled by reboot_pid_ns() which will
-	 * call do_exit().
-	 */
-	ret = reboot_pid_ns(pid_ns, cmd);
-	if (ret)
-		return ret;
-
-	/* Instead of trying to make the power_off code look like
-	 * halt when pm_power_off is not set do it the easy way.
-	 */
-	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
-		cmd = LINUX_REBOOT_CMD_HALT;
-
-	mutex_lock(&reboot_mutex);
-	switch (cmd) {
-	case LINUX_REBOOT_CMD_RESTART:
-		kernel_restart(NULL);
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_ON:
-		C_A_D = 1;
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_OFF:
-		C_A_D = 0;
-		break;
-
-	case LINUX_REBOOT_CMD_HALT:
-		kernel_halt();
-		do_exit(0);
-		panic("cannot halt");
-
-	case LINUX_REBOOT_CMD_POWER_OFF:
-		kernel_power_off();
-		do_exit(0);
-		break;
-
-	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
-			ret = -EFAULT;
-			break;
-		}
-		buffer[sizeof(buffer) - 1] = '\0';
-
-		kernel_restart(buffer);
-		break;
-
-#ifdef CONFIG_KEXEC
-	case LINUX_REBOOT_CMD_KEXEC:
-		ret = kernel_kexec();
-		break;
-#endif
-
-#ifdef CONFIG_HIBERNATION
-	case LINUX_REBOOT_CMD_SW_SUSPEND:
-		ret = hibernate();
-		break;
-#endif
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	mutex_unlock(&reboot_mutex);
-	return ret;
-}
-
-static void deferred_cad(struct work_struct *dummy)
-{
-	kernel_restart(NULL);
-}
-
-/*
- * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
- * As it's called within an interrupt, it may NOT sync: the only choice
- * is whether to reboot at once, or just ignore the ctrl-alt-del.
- */
-void ctrl_alt_del(void)
-{
-	static DECLARE_WORK(cad_work, deferred_cad);
-
-	if (C_A_D)
-		schedule_work(&cad_work);
-	else
-		kill_cad_pid(SIGINT, 1);
-}
-	
 /*
  * Unprivileged users may change the real gid to the effective gid
  * or vice versa.  (BSD-style)
@@ -2276,68 +2007,6 @@ SYSCALL_DEFINE3(getcpu, unsigned __user *, cpup, unsigned __user *, nodep,
 	return err ? -EFAULT : 0;
 }
 
-char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
-
-static int __orderly_poweroff(bool force)
-{
-	char **argv;
-	static char *envp[] = {
-		"HOME=/",
-		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
-		NULL
-	};
-	int ret;
-
-	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
-	if (argv) {
-		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
-		argv_free(argv);
-	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
-		ret = -ENOMEM;
-	}
-
-	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
-		/*
-		 * I guess this should try to kick off some daemon to sync and
-		 * poweroff asap.  Or not even bother syncing if we're doing an
-		 * emergency shutdown?
-		 */
-		emergency_sync();
-		kernel_power_off();
-	}
-
-	return ret;
-}
-
-static bool poweroff_force;
-
-static void poweroff_work_func(struct work_struct *work)
-{
-	__orderly_poweroff(poweroff_force);
-}
-
-static DECLARE_WORK(poweroff_work, poweroff_work_func);
-
-/**
- * orderly_poweroff - Trigger an orderly system poweroff
- * @force: force poweroff if command execution fails
- *
- * This may be called from any context to trigger a system shutdown.
- * If the orderly shutdown fails, it will force an immediate shutdown.
- */
-int orderly_poweroff(bool force)
-{
-	if (force) /* do not override the pending "true" */
-		poweroff_force = true;
-	schedule_work(&poweroff_work);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(orderly_poweroff);
-
 /**
  * do_sysinfo - fill in sysinfo struct
  * @info: pointer to buffer to fill
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:20 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:20 -0500
Subject: [PATCH -v9 06/11] x86,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-7-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Miguel Boton <mboton.lkml at gmail.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/x86/kernel/reboot.c | 12 +++++++-----
 include/linux/reboot.h   |  5 +++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 76fa1e9..f770340 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,7 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static int reboot_mode;
+static enum reboot_mode reboot_mode;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -88,11 +88,11 @@ static int __init reboot_setup(char *str)
 
 		switch (*str) {
 		case 'w':
-			reboot_mode = 0x1234;
+			reboot_mode = REBOOT_WARM;
 			break;
 
 		case 'c':
-			reboot_mode = 0;
+			reboot_mode = REBOOT_COLD;
 			break;
 
 #ifdef CONFIG_SMP
@@ -536,6 +536,7 @@ static void native_machine_emergency_restart(void)
 	int i;
 	int attempt = 0;
 	int orig_reboot_type = reboot_type;
+	unsigned short mode;
 
 	if (reboot_emergency)
 		emergency_vmx_disable_all();
@@ -543,7 +544,8 @@ static void native_machine_emergency_restart(void)
 	tboot_shutdown(TB_SHUTDOWN_REBOOT);
 
 	/* Tell the BIOS if we want cold or warm reboot */
-	*((unsigned short *)__va(0x472)) = reboot_mode;
+	mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
+	*((unsigned short *)__va(0x472)) = mode;
 
 	for (;;) {
 		/* Could also try the reset bit in the Hammer NB */
@@ -585,7 +587,7 @@ static void native_machine_emergency_restart(void)
 
 		case BOOT_EFI:
 			if (efi_enabled(EFI_RUNTIME_SERVICES))
-				efi.reset_system(reboot_mode ?
+				efi.reset_system(reboot_mode == REBOOT_WARM ?
 						 EFI_RESET_WARM :
 						 EFI_RESET_COLD,
 						 EFI_SUCCESS, 0, NULL);
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index c6eba21..37d56c3 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -10,6 +10,11 @@
 #define SYS_HALT	0x0002	/* Notify of system halt */
 #define SYS_POWER_OFF	0x0003	/* Notify of system power off */
 
+enum reboot_mode {
+	REBOOT_COLD = 0,
+	REBOOT_WARM,
+};
+
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
 
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:21 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:21 -0500
Subject: [PATCH -v9 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-8-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/unicore32/kernel/process.c | 10 +++++-----
 arch/unicore32/kernel/setup.h   |  2 +-
 arch/unicore32/mm/mmu.c         |  2 +-
 include/linux/reboot.h          |  2 ++
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index c944769..93dd035 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,14 +51,14 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static char reboot_mode = 'h';
+static enum reboot_mode reboot_mode = REBOOT_HARD;
 
 int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
@@ -88,7 +88,7 @@ void machine_restart(char *cmd)
 	 * we may need it to insert some 1:1 mappings so that
 	 * soft boot works.
 	 */
-	setup_mm_for_reboot(reboot_mode);
+	setup_mm_for_reboot();
 
 	/* Clean and invalidate caches */
 	flush_cache_all();
@@ -102,7 +102,7 @@ void machine_restart(char *cmd)
 	/*
 	 * Now handle reboot code.
 	 */
-	if (reboot_mode == 's') {
+	if (reboot_mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index 30f749d..f5c51b8 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
 extern void pci_puv3_preinit(void);
 extern void __init puv3_init_gpio(void);
 
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 
 extern char __stubs_start[], __stubs_end[];
 extern char __vectors_start[], __vectors_end[];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index 43c20b4..4f5a532 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -445,7 +445,7 @@ void __init paging_init(void)
  * the user-mode pages.  This will then ensure that we have predictable
  * results when turning the mmu off
  */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 	unsigned long base_pmdval;
 	pgd_t *pgd;
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 37d56c3..ca29a6f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -13,6 +13,8 @@
 enum reboot_mode {
 	REBOOT_COLD = 0,
 	REBOOT_WARM,
+	REBOOT_HARD,
+	REBOOT_SOFT,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:22 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:22 -0500
Subject: [PATCH -v9 08/11] arm,
 Remove unused restart_mode fields from some arm subarchs
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-9-git-send-email-holt@sgi.com>

These restart_mode fields are not used at all.  Remove them to make
moving the reboot= cmdline options to the general kernel easier.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/mach-ebsa110/core.c | 1 -
 arch/arm/mach-pxa/mioa701.c  | 1 -
 arch/arm/mach-pxa/spitz.c    | 3 ---
 arch/arm/mach-pxa/tosa.c     | 1 -
 4 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..69a9d5d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
 	.atag_offset	= 0x400,
 	.reserve_lp0	= 1,
 	.reserve_lp2	= 1,
-	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
 	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b9..dbea67a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -756,7 +756,6 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
 	.map_io		= &pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
 	.init_irq	= &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..c3c0042 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,7 +979,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -993,7 +992,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -1007,7 +1005,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e..a41992f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -969,7 +969,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-	.restart_mode	= 'g',
 	.fixup          = fixup_tosa,
 	.map_io         = pxa25x_map_io,
 	.nr_irqs	= TOSA_NR_IRQS,
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:25 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:25 -0500
Subject: [PATCH -v9 11/11] Move arch/x86 reboot= handling to generic kernel.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-12-git-send-email-holt@sgi.com>

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---
Changes since -v8
 - Add missing break statements.

 - Change parsing so #ifdef's are no longer needed.

 - Switch to using simple_strtoul to make parsing cleaner.

 - Add handling of REBOOT_HARD/SOFT
---
 Documentation/kernel-parameters.txt      | 14 ++++-
 arch/arm/kernel/process.c                | 10 ----
 arch/unicore32/kernel/process.c          | 10 ----
 arch/x86/include/asm/emergency-restart.h | 12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |  2 +-
 arch/x86/kernel/reboot.c                 | 96 +-------------------------------
 include/linux/reboot.h                   | 17 ++++++
 kernel/reboot.c                          | 76 ++++++++++++++++++++++++-
 8 files changed, 107 insertions(+), 130 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c3bfacb..b2945ce 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2677,9 +2677,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old] | h[ard] | s[oft] | g[pio]] \
+				[[,]s[mp]#### \
+				[[,]b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[[,]f[orce]
+			Where reboot_mode is one of warm (soft) or cold (hard) or gpio,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 42856fc..304b102 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode = REBOOT_HARD;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 93dd035..778ebba 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode = REBOOT_HARD;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index f770340..d568dfb 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -64,79 +63,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +542,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 5a5d7f7..8e00f9f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -17,6 +17,23 @@ enum reboot_mode {
 	REBOOT_SOFT,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index abb6a04..269ed93 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -24,6 +25,18 @@ int C_A_D = 1;
 struct pid *cad_pid;
 EXPORT_SYMBOL(cad_pid);
 
+#if defined(CONFIG_ARM) || defined(CONFIG_UNICORE32)
+#define DEFAULT_REBOOT_MODE		= REBOOT_HARD
+#else
+#define DEFAULT_REBOOT_MODE
+#endif
+enum reboot_mode reboot_mode DEFAULT_REBOOT_MODE;
+
+int reboot_default;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
 /*
  * If set, this is used for preparing the system to power off.
  */
@@ -87,7 +100,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
+	int cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -343,3 +356,64 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+		case 'h':
+			reboot_mode = REBOOT_HARD;
+			break;
+
+		case 's':
+			if (isdigit(*(str+1)))
+				reboot_cpu = simple_strtoul(str+1, NULL, 0);
+			else if (str[1] == 'm' && str[2] == 'p' &&
+							isdigit(*(str+3)))
+				reboot_cpu = simple_strtoul(str+3, NULL, 0);
+			else
+				reboot_mode = REBOOT_SOFT;
+			break;
+
+		case 'g':
+			reboot_mode = REBOOT_GPIO;
+			break;
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:23 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:23 -0500
Subject: [PATCH -v9 09/11] arm,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-10-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/arm/include/asm/mach/arch.h   | 3 ++-
 arch/arm/kernel/process.c          | 8 ++++----
 arch/arm/kernel/setup.c            | 6 +++---
 arch/arm/mach-footbridge/cats-hw.c | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..e2b551e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -9,6 +9,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 
 struct tag;
 struct meminfo;
@@ -39,7 +40,7 @@ struct machine_desc {
 	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-	char			restart_mode;	/* default restart mode	*/
+	enum reboot_mode	reboot_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..92b47df 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -174,14 +174,14 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-static char reboot_mode = 'h';
+enum reboot_mode reboot_mode = REBOOT_HARD;
 
-int __init reboot_setup(char *str)
+static int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 728007c..1450029 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -72,7 +72,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -758,8 +758,8 @@ void __init setup_arch(char **cmdline_p)
 
 	setup_dma_zone(mdesc);
 
-	if (mdesc->restart_mode)
-		reboot_setup(&mdesc->restart_mode);
+	if (mdesc->reboot_mode != REBOOT_HARD)
+		reboot_mode = mdesc->reboot_mode;
 
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09..9669cc0 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
 	/* Maintainer: Philip Blundell */
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
+	.reboot_mode	= REBOOT_SOFT,
 	.fixup		= fixup_cats,
 	.map_io		= footbridge_map_io,
 	.init_irq	= footbridge_init_irq,
-- 
1.8.2.1



From holt at sgi.com  Thu May  9 15:23:24 2013
From: holt at sgi.com (Robin Holt)
Date: Thu,  9 May 2013 14:23:24 -0500
Subject: [PATCH -v9 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <1368127405-112717-11-git-send-email-holt@sgi.com>

Preparing to move the parsing of reboot= to generic kernel code
forces the change in reboot_mode handling to use the enum.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/include/asm/hardware/iop3xx.h         |  3 ++-
 arch/arm/include/asm/mach/arch.h               |  2 +-
 arch/arm/include/asm/system_misc.h             |  3 ++-
 arch/arm/kernel/process.c                      |  5 +++--
 arch/arm/mach-at91/at91rm9200.c                |  3 ++-
 arch/arm/mach-at91/generic.h                   |  5 +++--
 arch/arm/mach-bcm2835/bcm2835.c                |  4 ++--
 arch/arm/mach-clps711x/common.c                |  2 +-
 arch/arm/mach-clps711x/common.h                |  4 +++-
 arch/arm/mach-cns3xxx/core.h                   |  4 +++-
 arch/arm/mach-cns3xxx/pm.c                     |  2 +-
 arch/arm/mach-davinci/devices-da8xx.c          |  3 ++-
 arch/arm/mach-davinci/devices.c                |  3 ++-
 arch/arm/mach-davinci/include/mach/common.h    |  3 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h     |  3 ++-
 arch/arm/mach-davinci/include/mach/tnetv107x.h |  3 ++-
 arch/arm/mach-davinci/tnetv107x.c              |  3 ++-
 arch/arm/mach-dove/common.c                    |  2 +-
 arch/arm/mach-dove/common.h                    |  4 +++-
 arch/arm/mach-ebsa110/core.c                   |  2 +-
 arch/arm/mach-ep93xx/core.c                    |  3 ++-
 arch/arm/mach-ep93xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-exynos/common.c                  |  4 ++--
 arch/arm/mach-exynos/common.h                  |  5 +++--
 arch/arm/mach-footbridge/common.c              |  4 ++--
 arch/arm/mach-footbridge/common.h              |  3 ++-
 arch/arm/mach-footbridge/netwinder-hw.c        |  4 ++--
 arch/arm/mach-highbank/core.h                  |  4 +++-
 arch/arm/mach-highbank/system.c                |  5 +++--
 arch/arm/mach-imx/common.h                     |  4 +++-
 arch/arm/mach-imx/mach-imx6q.c                 |  3 ++-
 arch/arm/mach-imx/system.c                     |  2 +-
 arch/arm/mach-integrator/common.h              |  3 ++-
 arch/arm/mach-integrator/core.c                |  2 +-
 arch/arm/mach-iop13xx/include/mach/iop13xx.h   |  5 ++++-
 arch/arm/mach-iop13xx/setup.c                  |  2 +-
 arch/arm/mach-iop32x/n2100.c                   |  2 +-
 arch/arm/mach-ixp4xx/common.c                  |  4 ++--
 arch/arm/mach-ixp4xx/dsmg600-setup.c           |  1 +
 arch/arm/mach-ixp4xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-ixp4xx/include/mach/timex.h      |  2 +-
 arch/arm/mach-kirkwood/board-lsxl.c            |  2 +-
 arch/arm/mach-kirkwood/common.c                |  3 ++-
 arch/arm/mach-kirkwood/common.h                |  4 +++-
 arch/arm/mach-ks8695/generic.h                 |  2 +-
 arch/arm/mach-ks8695/time.c                    |  4 ++--
 arch/arm/mach-lpc32xx/common.c                 |  6 +++---
 arch/arm/mach-lpc32xx/common.h                 |  3 ++-
 arch/arm/mach-mmp/common.c                     |  2 +-
 arch/arm/mach-mmp/common.h                     |  3 ++-
 arch/arm/mach-mmp/include/mach/pxa168.h        |  4 +++-
 arch/arm/mach-mmp/pxa168.c                     |  2 +-
 arch/arm/mach-mv78xx0/common.c                 |  2 +-
 arch/arm/mach-mv78xx0/common.h                 |  4 +++-
 arch/arm/mach-mvebu/common.h                   |  4 +++-
 arch/arm/mach-mvebu/system-controller.c        |  3 ++-
 arch/arm/mach-mxs/mach-mxs.c                   |  4 +++-
 arch/arm/mach-netx/generic.c                   |  3 ++-
 arch/arm/mach-netx/generic.h                   |  4 +++-
 arch/arm/mach-nomadik/cpu-8815.c               |  2 +-
 arch/arm/mach-omap1/board-voiceblue.c          |  3 ++-
 arch/arm/mach-omap1/common.h                   |  3 ++-
 arch/arm/mach-omap1/reset.c                    |  3 ++-
 arch/arm/mach-omap2/am33xx-restart.c           |  3 ++-
 arch/arm/mach-omap2/common.h                   | 17 +++++++++--------
 arch/arm/mach-omap2/omap2-restart.c            |  2 +-
 arch/arm/mach-omap2/omap3-restart.c            |  3 ++-
 arch/arm/mach-omap2/omap4-common.c             |  3 ++-
 arch/arm/mach-orion5x/common.c                 |  2 +-
 arch/arm/mach-orion5x/common.h                 |  4 +++-
 arch/arm/mach-orion5x/ls-chl-setup.c           |  2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c           |  2 +-
 arch/arm/mach-orion5x/lsmini-setup.c           |  2 +-
 arch/arm/mach-picoxcell/common.c               |  3 ++-
 arch/arm/mach-prima2/common.h                  |  4 +++-
 arch/arm/mach-prima2/rstc.c                    |  3 ++-
 arch/arm/mach-pxa/corgi.c                      |  6 +++---
 arch/arm/mach-pxa/generic.h                    |  4 +++-
 arch/arm/mach-pxa/mioa701.c                    |  7 ++++---
 arch/arm/mach-pxa/poodle.c                     |  2 +-
 arch/arm/mach-pxa/reset.c                      |  8 ++++----
 arch/arm/mach-pxa/spitz.c                      |  5 +++--
 arch/arm/mach-pxa/tosa.c                       |  5 +++--
 arch/arm/mach-realview/realview_eb.c           |  3 ++-
 arch/arm/mach-realview/realview_pb1176.c       |  3 ++-
 arch/arm/mach-realview/realview_pb11mp.c       |  3 ++-
 arch/arm/mach-realview/realview_pba8.c         |  3 ++-
 arch/arm/mach-realview/realview_pbx.c          |  3 ++-
 arch/arm/mach-rpc/riscpc.c                     |  3 ++-
 arch/arm/mach-s3c24xx/common.h                 | 12 +++++++-----
 arch/arm/mach-s3c24xx/s3c2410.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2412.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2416.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2443.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c244x.c                |  5 +++--
 arch/arm/mach-s3c64xx/common.c                 |  5 +++--
 arch/arm/mach-s3c64xx/common.h                 |  4 +++-
 arch/arm/mach-s5p64x0/common.c                 |  5 +++--
 arch/arm/mach-s5p64x0/common.h                 |  4 +++-
 arch/arm/mach-s5pc100/common.c                 |  5 +++--
 arch/arm/mach-s5pc100/common.h                 |  4 +++-
 arch/arm/mach-s5pv210/common.c                 |  2 +-
 arch/arm/mach-s5pv210/common.h                 |  4 +++-
 arch/arm/mach-sa1100/generic.c                 |  5 +++--
 arch/arm/mach-sa1100/generic.h                 |  3 ++-
 arch/arm/mach-shark/core.c                     |  3 ++-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  3 ++-
 arch/arm/mach-shmobile/board-kzm9g.c           |  3 ++-
 arch/arm/mach-socfpga/socfpga.c                |  3 ++-
 arch/arm/mach-spear/generic.h                  |  4 +++-
 arch/arm/mach-spear/restart.c                  |  5 +++--
 arch/arm/mach-sunxi/sunxi.c                    |  3 ++-
 arch/arm/mach-tegra/board.h                    |  3 ++-
 arch/arm/mach-tegra/common.c                   |  3 ++-
 arch/arm/mach-u300/core.c                      |  6 +++---
 arch/arm/mach-versatile/core.c                 |  3 ++-
 arch/arm/mach-versatile/core.h                 |  3 ++-
 arch/arm/mach-vt8500/vt8500.c                  |  3 ++-
 arch/arm/mach-w90x900/cpu.c                    |  4 ++--
 arch/arm/mach-w90x900/nuc9xx.h                 |  5 ++++-
 arch/arm/plat-iop/gpio.c                       |  1 +
 arch/arm/plat-iop/restart.c                    |  2 +-
 drivers/power/reset/restart-poweroff.c         |  3 ++-
 drivers/power/reset/vexpress-poweroff.c        |  2 +-
 include/linux/reboot.h                         |  1 +
 include/linux/vexpress.h                       |  1 +
 126 files changed, 283 insertions(+), 167 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a..423744b 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e2b551e..2353bc3 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -54,7 +54,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	void			(*handle_irq)(struct pt_regs *);
 #endif
-	void			(*restart)(char, const char *);
+	void			(*restart)(enum reboot_mode, const char *);
 };
 
 /*
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e3..a3d61ad 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED	(1 << 0)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 92b47df..42856fc 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -112,7 +113,7 @@ void soft_restart(unsigned long addr)
 	BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +123,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..f70c239 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -304,7 +305,7 @@ static void at91rm9200_idle(void)
 	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	/*
 	 * Perform a hardware reset with the use of the Watchdog timer.
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..0723ed6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 740fa9e..40686d7 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -53,7 +53,7 @@ static void bcm2835_setup_restart(void)
 	WARN(!wdt_regs, "failed to remap watchdog regs");
 }
 
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 val;
 
@@ -91,7 +91,7 @@ static void bcm2835_power_off(void)
 	writel_relaxed(val, wdt_regs + PM_RSTS);
 
 	/* Continue with normal reset mechanism */
-	bcm2835_restart(0, "");
+	bcm2835_restart(REBOOT_HARD, "");
 }
 
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..54f6a8d 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -345,7 +345,7 @@ void __init clps711x_timer_init(void)
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2da0ff5 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
  * Common bits.
  */
 
+#include <linux/reboot.h>
+
 #define CLPS711X_NR_IRQS	(33)
 #define CLPS711X_NR_GPIO	(4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit)	((prt) * 8 + (bit))
@@ -12,4 +14,4 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b..5218b61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
+#include <linux/reboot.h>
+
 extern void cns3xxx_timer_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 79e3d47..fb38c72 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..c80e189 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
 	.resource	= da8xx_watchdog_resources,
 };
 
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device *dev;
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3..5364f70 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
@@ -303,7 +304,7 @@ struct platform_device davinci_wdt_device = {
 	.resource	= wdt_resources,
 };
 
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
 	davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..cce316b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 extern void davinci_timer_init(void);
 
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..95b76a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,6 +17,7 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
@@ -106,7 +107,7 @@ int __init da850_register_vpif_display
 			(struct vpif_display_config *display_config);
 int __init da850_register_vpif_capture
 			(struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..bc9479d 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -54,7 +55,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d..4545667 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/map.h>
 
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
 	__raw_writel(1, &regs->kick);
 }
 
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
 	tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..cbdb88b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -382,7 +382,7 @@ void __init dove_init(void)
 	dove_xor1_init();
 }
 
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index e863479..1d72522 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 
 #endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 69a9d5d..62b928b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 
 arch_initcall(ebsa110_init);
 
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0x80000000);
 }
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3d..df8612f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
 	gpio_led_register_device(-1, &ep93xx_led_data);
 }
 
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b3..e256e0b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 745e304..e3a2802 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -302,12 +302,12 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
-void exynos4_restart(char mode, const char *cmd)
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	u32 val;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 60dd35c..da1130b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,6 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/reboot.h>
 #include <linux/of.h>
 
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
@@ -22,8 +23,8 @@ struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369..2739ca2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
 	}
 }
 
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50..56607b3 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23f..1fd2cf0 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
 
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206..aea1ec5 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
 
+#include <linux/reboot.h>
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384..2df5870 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
  */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 
 #include "core.h"
 #include "sysregs.h"
 
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 'h')
+	if (mode == REBOOT_HARD)
 		highbank_set_pwr_hard_reset();
 	else
 		highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4cba7db..3401fee 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct platform_device;
 struct clk;
 enum mxc_cpu_pwr_mode;
@@ -71,7 +73,7 @@ extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..6fdb478 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -26,6 +26,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -66,7 +67,7 @@ static void __init imx6q_init_revision(void)
 	mxc_set_cpu_type(rev >> 16 & 0xff);
 }
 
-static void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..d7ec547 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -34,7 +34,7 @@ static void __iomem *wdog_base;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658b..ad0ac55 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d2..4cdfd73 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
  * To reset, we hit the on-board reset register in the system FPGA
  */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
 	cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58..17b4027 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 
 #ifndef __ASSEMBLY__
+
+#include <linux/reboot.h>
+
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61..97a4906 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -597,7 +597,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a..0691443 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
 		;
 }
 
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
 	gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
 	gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..33e4630 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
 					0xf, 0xfffffffe);
 }
 
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if ( 1 && mode == 's') {
+	if ( 1 && mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8..686ef34 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb6..4c4c6a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 #include <asm/types.h>
 
 #ifndef	__ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index c9e930f..729b2db 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -3,7 +3,7 @@
  * 
  */
 
-#include <mach/hardware.h>
+// #include <mach/hardware.h>
 
 /*
  * We use IXP425 General purpose timer for our timer needs, it runs at 
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..c44f8b2 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -35,7 +35,7 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
  */
 static void lsxl_power_off(void)
 {
-	kirkwood_restart('h', NULL);
+	kirkwood_restart(REBOOT_HARD, NULL);
 }
 
 void __init lsxl_init(void)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c2cae69..f54fdf9 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -729,7 +730,7 @@ void __init kirkwood_init(void)
 #endif
 }
 
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..2a109df 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,7 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 			    int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce4..43253f8 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a386..426c976 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
 	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
 
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	unsigned int reg;
 
-	if (mode == 's')
+	if (reboot_mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c..d7aa54c 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
 	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
 
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 		lpc32xx_watchdog_reset();
 		break;
 
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b2606..1cd8853 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 /*
  * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 
 
 /*
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..c03b4ab 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..991d7e9 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..459c2d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
 
+#include <linux/reboot.h>
+
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3..144e997 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 	return platform_device_register(&pxa168_device_usb_host);
 }
 
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 749a7f8..75062ef 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -413,7 +413,7 @@ void __init mv78xx0_init(void)
 	clk_init();
 }
 
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6889af2 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 
 extern void mv78xx0_timer_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..f7ad45e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,9 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-void mvebu_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df..f875124 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 static void __iomem *system_controller_base;
 
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
 	{ /* end of list */ },
 };
 
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!system_controller_base) {
 		pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..79ddcaf 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -26,6 +26,8 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -390,7 +392,7 @@ static void __init mxs_machine_init(void)
 /*
  * Reset the system. It is called by machine_restart().
  */
-static void mxs_restart(char mode, const char *cmd)
+static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *reset_addr;
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68..db25b0c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 
 subsys_initcall(netx_init);
 
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
 	       NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26b..bb2ce47 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/reboot.h>
+
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..8aec5af 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -148,7 +148,7 @@ static void __init cpu8815_map_io(void)
 	iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
 
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1..4677a9c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
 	gpio_set_value(0, wdt_gpio_state);
 }
 
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e99..abec019 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <plat/i2c.h>
 
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e..72bf4bf 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
 
 
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8..1eae962 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..be9b930 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <asm/proc-fns.h>
 
@@ -118,33 +119,33 @@ static inline void omap_soc_device_init(void)
 #endif
 
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716..68423e2 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
  * Set the DPLL to bypass so that reboot completes successfully.  No
  * return value.
  */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 rate;
 
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582..5de2a0c 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 	omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ff..14c7bad 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -348,7 +349,7 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap44xx_restart(char mode, const char *cmd)
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* XXX Should save 'cmd' into scratchpad for use after reboot */
 	omap4_prminst_global_warm_sw_reset(); /* never returns */
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b97fd67..98dd90c 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -354,7 +354,7 @@ void __init orion5x_init(void)
 	orion5x_wdt_init();
 }
 
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index cdaa01f..a909afb 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -29,7 +31,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 24f4e14..6234977 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 
 static void lschl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fc653bb..fe04c4b 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 
 static void ls_hgl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 18e66e6..ca4dbe9 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..d298ed0 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,6 +15,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
@@ -70,7 +71,7 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Configure the watchdog to reset with the shortest possible timeout
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd..a630485 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..bdf57d4 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -82,7 +83,7 @@ int sirfsoc_reset_device(struct device *dev)
 
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fea..f162f1b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
 		/* Green LED off tells the bootloader to halt */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!machine_is_corgi())
 		/* Green LED on tells the bootloader to reboot */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-	pxa_restart('h', cmd);
+	pxa_restart(REBOOT_HARD, cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39..8963984 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/reboot.h>
+
 struct irq_data;
 
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
 
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dbea67a..76f5e46 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -691,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', NULL);
+	pxa_restart(REBOOT_SOFT, NULL);
 }
 
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', cmd);
+	pxa_restart(REBOOT_SOFT, cmd);
 }
 
 static struct gpio global_gpios[] = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..711d37e 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -422,7 +422,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 
 static void poodle_poweroff(void)
 {
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583..0d5dd64 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
 	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
 	local_irq_disable();
 	local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
 	clear_reset_status(RESET_STATUS_ALL);
 
 	switch (mode) {
-	case 's':
+	case REBOOT_SOFT:
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 		break;
-	case 'g':
+	case REBOOT_GPIO:
 		do_gpio_reset();
 		break;
-	case 'h':
+	case REBOOT_HARD:
 	default:
 		do_hw_reset();
 		break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c3c0042..2125df0 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -924,10 +925,10 @@ static inline void spitz_i2c_init(void) {}
  ******************************************************************************/
 static void spitz_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 	/* Bootloader magic for a reboot */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a41992f..0206b91 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bf..c85ddb2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
 	realview_eb_twd_init();
 }
 
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1..c5eade7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe21..f4b0962 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
 	realview_pb11mp_twd_init();
 }
 
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a..10a3e1d 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185..9d75493 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
 
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5..09d602b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 
 arch_initcall(rpc_init);
 
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
 	iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 307c371..84b2806 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 #ifdef CONFIG_CPU_S3C2410
@@ -20,7 +22,7 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -36,7 +38,7 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -51,7 +53,7 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -66,7 +68,7 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c244x_init_clocks(int xtal);
-extern void s3c244x_restart(char mode, const char *cmd);
+extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
@@ -96,7 +98,7 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5..f68ccf0 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
@@ -195,9 +196,9 @@ int __init s3c2410a_init(void)
 	return s3c2410_init();
 }
 
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		soft_restart(0);
 	}
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0f864d4..0251650 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,9 +130,9 @@ static void s3c2412_idle(void)
 	cpu_do_idle();
 }
 
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index b9c5d38..9ef3ccf 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -79,9 +80,9 @@ static struct device s3c2416_dev = {
 	.bus		= &s3c2416_subsys,
 };
 
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 8328cd6..b6c7191 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,9 +60,9 @@ static struct device s3c2443_dev = {
 	.bus		= &s3c2443_subsys,
 };
 
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb..de88598 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -197,9 +198,9 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
 	.resume		= s3c244x_resume,
 };
 
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	arch_wdt_reset();
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..c13d90d 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,9 +376,9 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
 
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..e8f990b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
 
+#include <linux/reboot.h>
+
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
 
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..5f515e1 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -437,9 +438,9 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
 
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fd..f3a9b43 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5P6440
 
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..e6cc829 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -216,9 +217,9 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index c41f912..08d782d 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
 
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e..023f1a7 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 	}
 };
 
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 0a1cc0ae..fe1beb5 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
 
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98..f25b611 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <video/sa1100fb.h>
 
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
 	PMCR = PMCR_SF;
 }
 
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1..9a33695 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
  *
  * Author: Nicolas Pitre
  */
+#include <linux/reboot.h>
 
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 1535557..1d32c5e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
         short temp;
         /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b288..fde2e4f 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -1277,7 +1278,7 @@ static void __init eva_add_early_devices(void)
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* Do soft power on reset */
 	writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a..2f223f0 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -33,6 +33,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -806,7 +807,7 @@ static void __init kzm_init(void)
 	sh73a0_pm_init();
 }
 
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
 	/* Do soft power on reset */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a0513..0fde6c0 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -90,7 +91,7 @@ static void __init socfpga_init_irq(void)
 	socfpga_sysmgr_init();
 }
 
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 temp;
 
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index a9fd453..904f2c9 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -16,6 +16,8 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/pl08x.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 
 extern void spear13xx_timer_init(void);
@@ -32,7 +34,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
 
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 2b44500..ce5e098 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -12,14 +12,15 @@
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* software reset, Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..f71923b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <linux/clk/sunxi.h>
 
@@ -36,7 +37,7 @@
 
 static void __iomem *wdt_base;
 
-static void sun4i_restart(char mode, const char *cmd)
+static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!wdt_base)
 		return;
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1787327..9a6659f 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 
 void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..2572e73 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip.h>
 #include <linux/clk/tegra.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -67,7 +68,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
 
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
 	u32 reg;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..3e7af05 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -671,11 +671,11 @@ static void __init u300_init_machine(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-static void u300_restart(char mode, const char *cmd)
+static void u300_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 #ifdef CONFIG_COH901327_WATCHDOG
 		coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 54bb80b..3b0572f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif	/* CONFIG_LEDS */
 
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 	u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d..f06d576 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..de2b7eb 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +48,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (pmc_base)
 		writel(1, pmc_base + VT8500_PMSR_REG);
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b..b1eabaa 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define	WTE	(1 << 7)
 #define	WTRE	(1 << 1)
 
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b2..e3ab1e1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
  * published by the Free Software Foundation.
  *
  */
+
+#include <linux/reboot.h>
+
 struct map_desc;
 
 /* core initialisation functions */
 
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be..697de6d 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699..3a4d5e5 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
 
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	*IOP3XX_PCSR = 0x30;
 
diff --git a/drivers/power/reset/restart-poweroff.c b/drivers/power/reset/restart-poweroff.c
index 059cd15..5758033 100644
--- a/drivers/power/reset/restart-poweroff.c
+++ b/drivers/power/reset/restart-poweroff.c
@@ -15,11 +15,12 @@
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 
 static void restart_poweroff_do_poweroff(void)
 {
-	arm_pm_restart('h', NULL);
+	arm_pm_restart(REBOOT_HARD, NULL);
 }
 
 static int restart_poweroff_probe(struct platform_device *pdev)
diff --git a/drivers/power/reset/vexpress-poweroff.c b/drivers/power/reset/vexpress-poweroff.c
index 469e696..476aa49 100644
--- a/drivers/power/reset/vexpress-poweroff.c
+++ b/drivers/power/reset/vexpress-poweroff.c
@@ -48,7 +48,7 @@ static void vexpress_power_off(void)
 
 static struct device *vexpress_restart_device;
 
-static void vexpress_restart(char str, const char *cmd)
+static void vexpress_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	vexpress_reset_do(vexpress_restart_device, "restart");
 }
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index ca29a6f..5a5d7f7 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,7 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_HARD,
 	REBOOT_SOFT,
+	REBOOT_GPIO,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index ea7168a..617c01b 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/reboot.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
-- 
1.8.2.1



From arnd at arndb.de  Thu May  9 15:25:01 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 May 2013 21:25:01 +0200
Subject: [RFC PATCH 1/2] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <Pine.LNX.4.44L0.1305091108130.1796-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305091108130.1796-100000@iolanthe.rowland.org>
Message-ID: <201305092125.01607.arnd@arndb.de>

On Thursday 09 May 2013, Alan Stern wrote:
> > > The #else part of this isn't needed, and I doubt very much that it
> > > would work correctly if it was needed.
> >
> > As Arnd suggestion,so I written else part.
> 
> The existing code doesn't have a #else part, and I don't think you need 
> to add one.

I had commented in an earlier (Linaro internal) review that function
declarations should not be hidden inside of an #ifdef unless there
is an #else clause defining an alternative.

I did not want to suggest with that adding an #else for the fun of it,
of course it should only be there if actually needed.

	Arnd


From stern at rowland.harvard.edu  Thu May  9 15:36:26 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 9 May 2013 15:36:26 -0400 (EDT)
Subject: [RFC PATCH 1/2] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <201305092125.01607.arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305091530330.1796-100000@iolanthe.rowland.org>

On Thu, 9 May 2013, Arnd Bergmann wrote:

> On Thursday 09 May 2013, Alan Stern wrote:
> > > > The #else part of this isn't needed, and I doubt very much that it
> > > > would work correctly if it was needed.
> > >
> > > As Arnd suggestion,so I written else part.
> > 
> > The existing code doesn't have a #else part, and I don't think you need 
> > to add one.
> 
> I had commented in an earlier (Linaro internal) review that function
> declarations should not be hidden inside of an #ifdef unless there
> is an #else clause defining an alternative.
> 
> I did not want to suggest with that adding an #else for the fun of it,
> of course it should only be there if actually needed.

Well, empty inline function definitions don't have any runtime cost, so
there's nothing really wrong with it.  But it does give the impression
that it's okay to try calling these routines when CONFIG_PM isn't
enabled, which isn't true.  Either the result won't be what you
expected, or else you shouldn't be calling them in the first place.

Alan Stern

PS: If the proposed __pm annotation is added (see 
http://marc.info/?l=linux-pm&m=136811978510598&w=2) then this whole 
discussion will become moot.  :-)



From sboyd at codeaurora.org  Thu May  9 15:48:41 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 09 May 2013 12:48:41 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <518B663D.60806@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <518AE16D.5060501@codeaurora.org> <518B663D.60806@imgtec.com>
Message-ID: <518BFD99.2010208@codeaurora.org>

On 05/09/13 02:02, James Hogan wrote:
> On 09/05/13 00:36, Stephen Boyd wrote:
>> On 04/19/13 09:28, James Hogan wrote:
>>> This patchset adds support for automatic selection of the best parent
>>> for a clock mux, i.e. the one which can provide the closest clock rate
>>> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
>>> so that it doesn't happen unless explicitly allowed.
>>>
>>> This works by way of adding a new op, determine_rate, similar to
>>> round_rate but with an extra parameter to allow the clock driver to
>>> optionally select a different parent clock. This is used in
>>> clk_calc_new_rates to decide whether to initiate a set_parent operation.
>> Which tree is this based on? I get failures with git am on patch 2.
>>
> It was based on v3.9-rc4.
>

Thanks. Would it be possible for you to update to Mike's for-next
branch? I've done the rebase myself for now and it seems to work well
enough. I'll need to add the set_rate_and_parent() op on top.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Thu May  9 16:01:27 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 09 May 2013 13:01:27 -0700
Subject: [PATCH v2 2/3] clk: add support for clock reparent on set_rate
In-Reply-To: <1366388904-13903-3-git-send-email-james.hogan@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <1366388904-13903-3-git-send-email-james.hogan@imgtec.com>
Message-ID: <518C0097.50300@codeaurora.org>

On 04/19/13 09:28, James Hogan wrote:
> Add core support to allow clock implementations to select the best
> parent clock when rounding a rate, e.g. the one which can provide the
> closest clock rate to that requested. This is by way of adding a new
> clock op, determine_rate(), which is like round_rate() but has an extra
> parameter to allow the clock implementation to optionally select a
> different parent clock. The core then takes care of reparenting the
> clock when setting the rate.
>
> The parent change takes place with the help of two new private data
> members. struct clk::new_parent specifies a clock's new parent (NULL
> indicates no change), and struct clk::new_child specifies a clock's new
> child (whose new_parent member points back to it). The purpose of these
> are to allow correct walking of the future tree for notifications prior
> to actually reparenting any clocks, specifically to skip child clocks
> who are being reparented to another clock (they will be notified via the
> new parent), and to include any new child clock. These pointers are set
> by clk_calc_subtree(), and the new_child pointer gets cleared when a
> child is actually reparented to avoid duplicate POST_RATE_CHANGE
> notifications.
>
> Each place where round_rate() is called, determine_rate is checked first
> and called in preference, passing NULL to the new parent argument if not
> needed (e.g. in __clk_round_rate). This restructures a few of the call
> sites to simplify the logic into if/else blocks.
>
> A new __clk_set_parent_no_recalc() is created similar to
> clk_set_parent() but without calling __clk_recalc_rates(). This is for
> clk_change_rate() to use, where rate recalculation and notifications are
> already handled.
>
> Signed-off-by: James Hogan <james.hogan at imgtec.com>

I believe we'll need to update the check in __clk_init() to allow you to
have either a .round_rate or a .determine_rate op if you have a
.recalc_rate op. Right now it fails to register the clock and then
oopses later on while setting up clock debugfs.

Here's a (probably whitespace damaged) patch for the first one.

----8<-----

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index e6e759e..d56291c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1668,8 +1668,8 @@ int __clk_init(struct device *dev, struct clk *clk)
 
        /* check that clk_ops are sane.  See Documentation/clk.txt */
        if (clk->ops->set_rate &&
-                       !(clk->ops->round_rate && clk->ops->recalc_rate)) {
-               pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
+                       !((clk->ops->round_rate || clk->ops->determine_rate) && clk->ops->recalc_rate)) {
+               pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
                                __func__, clk->name);
                ret = -EINVAL;
                goto out;

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From olof at lixom.net  Thu May  9 16:08:21 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:08:21 -0700
Subject: [PATCH 0/3] ARM: imx/mxs: fixes for 3.10-rc1
In-Reply-To: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
References: <1368018355-26014-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130509200821.GA21293@quad.lixom.net>

On Wed, May 08, 2013 at 09:05:52PM +0800, Shawn Guo wrote:
> Hi Arnd, Olof,
> 
> It seems that you will have a few other fixes to send mainline for
> 3.10-rc1 inclusion before merge window closes.  In that case, can you
> please include the following 3 which fix imx/mxs compile errors that
> are currently seen on mainline?

Thanks, applied all three. For framebuffer fixes, it seems that we tend to
route them through Andrew Morton for the most part, so future patches should
probably go through him.


-Olof


From olof at lixom.net  Thu May  9 16:11:05 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:11:05 -0700
Subject: [GIT PULL] Two ux500 fixes for the v3.10 series
In-Reply-To: <CACRpkdYV26xRiASZ8L3PuPqoqyPKx1Jq-okN6LgD40ffgS6zdg@mail.gmail.com>
References: <CACRpkdYeWi2cx2weXao9=2f78eM0_J=gK-8o6gKjcG7pjYFAxA@mail.gmail.com>
 <201305032240.46483.arnd@arndb.de>
 <CACRpkdYV26xRiASZ8L3PuPqoqyPKx1Jq-okN6LgD40ffgS6zdg@mail.gmail.com>
Message-ID: <20130509201105.GB21293@quad.lixom.net>

On Fri, May 03, 2013 at 10:43:10PM +0200, Linus Walleij wrote:
> On Fri, May 3, 2013 at 10:40 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Friday 03 May 2013, Linus Walleij wrote:
> >> Hi ARM SoC folks,
> >>
> >> here are two ux500 fixes for the v3.10 series, please pull
> >> them in. Since -rc1 is not out this is based on Torvald's
> >> HEAD from yesterday.
> >
> > We try hard to avoid doing bug fixes on top of random HEADs.
> > Can you send these on top of the minimum set of branches?
> 
> I think I'll just wait for -rc1.
> 
> It's not *that* urgent, just wanted to clean my desk.

I've got a branch started at a non-rc for fixes right now, since we want some
of them in before the first -rc. So I'll cherry-pick these over while I'm at
it.


-Olof


From olof at lixom.net  Thu May  9 16:15:04 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:15:04 -0700
Subject: [GIT PULL 1/2] omap fixes for v3.10 merge window part2
In-Reply-To: <518bef23.e79f320a.5202.ffffc873SMTPIN_ADDED_BROKEN@mx.google.com>
References: <518bef23.e79f320a.5202.ffffc873SMTPIN_ADDED_BROKEN@mx.google.com>
Message-ID: <20130509201504.GA21598@quad.lixom.net>

On Thu, May 09, 2013 at 11:46:51AM -0700, Tony Lindgren wrote:
> The following changes since commit 956e46efb2478ebff7a871138458fa8124fd18dd:
> 
>   mm/slab: Fix crash during slab init (2013-05-08 15:02:33 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/fixes-for-merge-window-part2
> 
> for you to fetch changes up to b1dd11d60e5357c13d3f3decfb69bd07dde159bd:
> 
>   ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c (2013-05-09 09:06:27 -0700)

Pulled, thanks.

As Arnd mentioned on an ux500 pull request earlier, we usually don't like
fixes branches on non-rc bases, but since this is targeting pre-rc1 but
post-what-we-merged, there's not much else to do.


-Olof


From olof at lixom.net  Thu May  9 16:15:15 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:15:15 -0700
Subject: [GIT PULL 2/2] omap device tree fixes for v3.10 merge window
In-Reply-To: <E1UaVsF-0001Zt-HW@merlin.infradead.org>
References: <pull-1368125211-439797> <E1UaVsF-0001Zt-HW@merlin.infradead.org>
Message-ID: <20130509201515.GB21598@quad.lixom.net>

On Thu, May 09, 2013 at 11:46:51AM -0700, Tony Lindgren wrote:
> The following changes since commit bb9055b2744ada735a2fe555c4196ad39a83ef2a:
> 
>   Merge tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc (2013-05-07 11:28:42 -0700)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/dt-fixes-for-merge-window
> 
> for you to fetch changes up to 914dc329ee11d6b1ecbebef802962dc06e78b942:
> 
>   ARM: dts: don't assume boards are using twl4030 for omap3 (2013-05-09 09:06:57 -0700)


Pulled, thanks.


-Olof


From olof at lixom.net  Thu May  9 16:22:08 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:22:08 -0700
Subject: [PATCH] ARM: EXYNOS5: Fix kernel dump in AFTR idle mode
In-Reply-To: <1367235107-31328-1-git-send-email-inderpal.singh@linaro.org>
References: <1367235107-31328-1-git-send-email-inderpal.singh@linaro.org>
Message-ID: <20130509202208.GA21831@quad.lixom.net>

On Mon, Apr 29, 2013 at 05:01:47PM +0530, Inderpal Singh wrote:
> The kernel crashes while resuming from AFTR idle mode. It happens
> because L2 cache was not going into retention state.
> 
> This patch configures the USE_RETENTION bit of ARM_L2_OPTION register
> so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of
> ARM_COMMON_OPTION register for L2RSTDISABLE signal.
> 
> Signed-off-by: Inderpal Singh <inderpal.singh at linaro.org>

I haven't seen any activity from Kgene on this, but it seems reasonably bad
(and the fix is self-contained). Applying to arm-soc fixes branch.


-Olof


From olof at lixom.net  Thu May  9 16:25:34 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:25:34 -0700
Subject: [PATCH] ARM: exynos: dts: Fixed vbus-gpios
In-Reply-To: <1368034636-15865-1-git-send-email-dianders@chromium.org>
References: <1368034636-15865-1-git-send-email-dianders@chromium.org>
Message-ID: <20130509202534.GB21831@quad.lixom.net>

On Wed, May 08, 2013 at 10:37:16AM -0700, Doug Anderson wrote:
> The 'samsung,vbus-gpio' was submitted before pinmux landed for
> exynos5250 and uses the old-style gpio specifier.  Fix the two
> exynos5250 boards that use it.
> 
> Signed-off-by: Doug Anderson <dianders at chromium.org>


Applied to arm-soc fixes.

Thanks,


-Olof


From tony at atomide.com  Thu May  9 16:30:58 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 May 2013 13:30:58 -0700
Subject: [GIT PULL 1/2] omap fixes for v3.10 merge window part2
In-Reply-To: <20130509201504.GA21598@quad.lixom.net>
References: <518bef23.e79f320a.5202.ffffc873SMTPIN_ADDED_BROKEN@mx.google.com>
 <20130509201504.GA21598@quad.lixom.net>
Message-ID: <20130509203057.GJ31554@atomide.com>

* Olof Johansson <olof at lixom.net> [130509 13:20]:
> On Thu, May 09, 2013 at 11:46:51AM -0700, Tony Lindgren wrote:
> > The following changes since commit 956e46efb2478ebff7a871138458fa8124fd18dd:
> > 
> >   mm/slab: Fix crash during slab init (2013-05-08 15:02:33 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10/fixes-for-merge-window-part2
> > 
> > for you to fetch changes up to b1dd11d60e5357c13d3f3decfb69bd07dde159bd:
> > 
> >   ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c (2013-05-09 09:06:27 -0700)
> 
> Pulled, thanks.
> 
> As Arnd mentioned on an ux500 pull request earlier, we usually don't like
> fixes branches on non-rc bases, but since this is targeting pre-rc1 but
> post-what-we-merged, there's not much else to do.

Yes, sorry I should have mentioned that the commit these were based
on is the one that fixed boot issues for me. So not a random commit
of the day, and some of these had dependencies to the patches already
merged.

Regards,

Tony


From olof at lixom.net  Thu May  9 16:44:34 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:44:34 -0700
Subject: [PATCH V2] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <1367542653-955-1-git-send-email-csd@broadcom.com>
References: <1367542653-955-1-git-send-email-csd@broadcom.com>
Message-ID: <20130509204434.GA16724@quad.lixom.net>

On Thu, May 02, 2013 at 05:57:33PM -0700, Christian Daudt wrote:
> Rev A2 SoCs have an unorthodox memory re-mapping and this needs
> to be reflected in the cache operations.
> This patch adds new outer cache functions for the l2x0 driver
> to support this SoC revision. It also adds a new compatible
> value for the cache to enable this functionality.
> 
> Updates from V1:
> - remove section 1 altogether and note that in comments
> - simplify section selection caused by section 1 removal
> - BUG_ON just in case section 1 shows up
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>

This patch mostly covers code that is on Russells plate, so please feed
this to his tracker to be picked up by him. Feel free to add:

Acked-by: Olof Johansson <olof at lixom.net>


Thanks,

-Olof


From akpm at linux-foundation.org  Thu May  9 16:51:00 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Thu, 9 May 2013 13:51:00 -0700
Subject: [PATCH -v9 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1368127405-112717-5-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
 <1368127405-112717-5-git-send-email-holt@sgi.com>
Message-ID: <20130509135100.13947d1805a583703ee8488b@linux-foundation.org>

On Thu,  9 May 2013 14:23:18 -0500 Robin Holt <holt at sgi.com> wrote:

> This patch is preparatory.  It moves reboot related syscall, etc
> functions from kernel/sys.c to kernel/reboot.c.

This doesn't apply.

> -static void migrate_to_reboot_cpu(void)
> -{
> -	/* The boot cpu is always logical cpu 0 */
> -	int cpu = 0;
> -
> -	cpu_hotplug_disable();
> -
> -	/* Make certain the cpu I'm about to reboot on is online */
> -	if (!cpu_online(cpu))
> -		cpu = cpumask_first(cpu_online_mask);

Here it's deleting code which was already modified by "[PATCH -v9
02/11] Migrate shutdown/reboot to boot cpu.".  So patch [4/11]
generates rejects when applied on top of [patch 2/11].

There are several similar glitches.



From olof at lixom.net  Thu May  9 16:54:13 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 13:54:13 -0700
Subject: [GIT PULL] ARM: arm-soc fixes and a few straggler patches for 3.10
Message-ID: <20130509205413.GA16897@quad.lixom.net>

Hi Linus,

The following changes since commit 8cbc95ee748741939222c3d38584a40c92bedcdd:

  Merge tag 'nfs-for-3.10-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs (2013-05-09 10:24:54 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-for-linus

for you to fetch changes up to c58c1a4c118ba2ed49f72de9b42ef13bc8ee71e5:

  ARM: exynos: dts: Fixed vbus-gpios (2013-05-09 13:25:23 -0700)

----------------------------------------------------------------
ARM: arm-soc fixes and straggler patches for 3.10

A collection of fixes for fall out from 3.10 merge window, some build
fixes and warning cleanups and a small handful of patches that were
small and contained and made sense to still include in 3.10 (some of
these have also been in -next since the merge window opened).

Largest continous series is for OMAP, but there's a handful for other
platforms.

For i.MX, one of the patches are framebuffer fixups due to fallout during
the merge window, and the other removes some stale and broken code.

----------------------------------------------------------------
Aaro Koskinen (1):
      ARM: OMAP: RX-51: change probe order of touchscreen and panel SPI devices

Arnd Bergmann (7):
      ARM: default machine descriptor for multiplatform
      ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
      ARM: OMAP: build SMP code only for OMAP4/5
      ARM: imx: build CPU suspend code only when needed
      ARM: SPEAr: conditionalize l2x0 support
      ARM: SIRF: select SMP_ON_UP only on SMP builds
      ARM: ux500: always select ABX500_CORE

Christoph Fritz (1):
      omap: mux: add AM/DM37x gpios

Doug Anderson (1):
      ARM: exynos: dts: Fixed vbus-gpios

Fabio Baltieri (1):
      ARM: ux500: read the correct soc_id number

Fabio Estevam (2):
      ARM: imx: Select GENERIC_ALLOCATOR
      video: mxsfb: Adapt to new videomode API

Inderpal Singh (1):
      ARM: EXYNOS5: Fix kernel dump in AFTR idle mode

Jason Cooper (1):
      ARM: dts: don't assume boards are using twl4030 for omap3

Javier Martinez Canillas (3):
      Documentation: dt: update TI GPMC ethernet binding properties
      ARM: OMAP2+: only search for GPMC DT child nodes on probe
      ARM: OMAP2+: only WARN if a GPMC child probe function fail

Jon Hunter (2):
      Documentation: dt: update properties in TI GPMC NAND example
      ARM: dts: OMAP4: Fix ethernet IRQ for OMAP4 boards

Kevin Hilman (1):
      ARM: OMAP2+: omap_device: use late_initcall_sync

Lee Jones (1):
      ARM: ux500: Rid ignored return value of regulator_enable() compiler warning

Nishanth Menon (2):
      ARM: dts: OMAP36xx: Fix CPU OPP voltages
      ARM: dts: OMAP4460: Fix CPU OPP voltages

Olof Johansson (4):
      Merge branch 'late/fixes' into fixes
      ARM: exynos: dts: cros5250: add cyapa trackpad
      Merge tag 'omap-for-v3.10/fixes-for-merge-window-part2' of git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge tag 'omap-for-v3.10/dt-fixes-for-merge-window' of git://git.kernel.org/.../tmlind/linux-omap into fixes

Peter Ujfalusi (1):
      ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module

Philip Avinash (1):
      ARM: dts: AM33XX: Add GPMC node

Roger Quadros (1):
      ARM: OMAP3: Beagle: Fix USB Host on beagle xM Ax/Bx

Shawn Guo (1):
      ARM: imx: compile fix for hotplug.c

Tony Lindgren (4):
      ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP
      Merge branch 'omap-gpmc-fixes-for-v3.10' of git://github.com/jonhunter/linux into fixes
      ARM: dts: Configure and fix the McSPI pins for 4430sdp
      ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c

Vaibhav Hiremath (1):
      ARM: OMAP2: AM33XX: id: Add support for new AM335x PG2.1 Si

Wei Yongjun (1):
      ARM: OMAP1: DMA: fix error handling in omap1_system_dma_init()

 .../devicetree/bindings/mtd/gpmc-nand.txt          | 28 ++++-----
 Documentation/devicetree/bindings/net/gpmc-eth.txt | 56 ++++++++---------
 arch/arm/Kconfig                                   |  1 -
 arch/arm/boot/dts/am33xx.dtsi                      | 12 ++++
 arch/arm/boot/dts/cros5250-common.dtsi             |  8 +++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |  2 +-
 arch/arm/boot/dts/exynos5250-snow.dts              |  2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts              |  1 +
 arch/arm/boot/dts/omap3-evm.dts                    |  1 +
 arch/arm/boot/dts/omap3-overo.dtsi                 |  1 +
 arch/arm/boot/dts/omap3.dtsi                       |  1 -
 arch/arm/boot/dts/omap36xx.dtsi                    |  6 +-
 arch/arm/boot/dts/omap4-sdp.dts                    | 14 ++++-
 arch/arm/boot/dts/omap4-var-som.dts                |  2 +-
 arch/arm/boot/dts/omap4460.dtsi                    |  6 +-
 arch/arm/configs/omap2plus_defconfig               |  4 ++
 arch/arm/kernel/devtree.c                          |  7 +++
 arch/arm/kernel/setup.c                            | 13 +++-
 arch/arm/mach-exynos/include/mach/regs-pmu.h       |  1 +
 arch/arm/mach-exynos/pmu.c                         |  5 +-
 arch/arm/mach-imx/Kconfig                          |  5 +-
 arch/arm/mach-imx/Makefile                         |  1 -
 arch/arm/mach-imx/common.h                         |  1 +
 arch/arm/mach-imx/headsmp.S                        |  2 +-
 arch/arm/mach-imx/hotplug.c                        |  2 +
 arch/arm/mach-imx/iram_alloc.c                     | 73 ----------------------
 arch/arm/mach-omap1/dma.c                          |  8 +--
 arch/arm/mach-omap2/Kconfig                        |  2 -
 arch/arm/mach-omap2/Makefile                       |  8 +--
 arch/arm/mach-omap2/board-omap3beagle.c            |  6 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c       |  4 +-
 arch/arm/mach-omap2/gpmc.c                         | 38 ++++-------
 arch/arm/mach-omap2/id.c                           | 13 ++--
 arch/arm/mach-omap2/mux34xx.h                      |  6 +-
 arch/arm/mach-omap2/omap_device.c                  |  2 +-
 arch/arm/mach-omap2/soc.h                          |  2 +
 arch/arm/mach-prima2/Kconfig                       |  2 +-
 arch/arm/mach-spear/spear13xx.c                    |  2 +
 arch/arm/mach-tegra/Kconfig                        |  1 +
 arch/arm/mach-ux500/Kconfig                        |  2 +
 arch/arm/mach-ux500/board-mop500.c                 |  4 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |  2 +-
 drivers/video/Kconfig                              |  2 +-
 drivers/video/mxsfb.c                              |  8 +--
 include/linux/platform_data/imx-iram.h             | 41 ------------
 45 files changed, 173 insertions(+), 235 deletions(-)
 delete mode 100644 arch/arm/mach-imx/iram_alloc.c
 delete mode 100644 include/linux/platform_data/imx-iram.h


From olof at lixom.net  Thu May  9 16:58:19 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu,  9 May 2013 13:58:19 -0700
Subject: [PATCH] ARM: exynos: defconfig update
Message-ID: <1368133099-16997-1-git-send-email-olof@lixom.net>

This turns on a number of configs that are useful on the Chromebook, but also
good to have on in general:

* USB host and MMC drivers(!)
* I2C GPIO arbitration driver
* CYAPA trackpad driver
* simplefb
* CROS EC and keyboard drivers
* MAX77686 drivers
* DEVTMPFS + mount
* DM_CRYPT (as module)
* CRYPTOLOOP
* HIGHMEM
* PRINTK timestamps

This also turns off DEBUG_LL, and switches the hardcoded Samsung lowlevel
uart to uart 3 (which is only used to show the "uncompressing kernel"
message at boot, it seems).

Signed-off-by: Olof Johansson <olof at lixom.net>
Cc: Kukjin Kim <kgene.kim at samsung.com>
---

(Note that the simplefb driver is still not merged up for 3.10, but it
hopefully will be).

 arch/arm/configs/exynos_defconfig | 49 ++++++++++++++++++++++++++++++++-------
 1 file changed, 41 insertions(+), 8 deletions(-)

diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index e40b435..469b5cc 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -1,4 +1,4 @@
-CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
@@ -7,17 +7,18 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_ARCH_EXYNOS=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_S3C_LOWLEVEL_UART_PORT=3
 CONFIG_S3C24XX_PWM=y
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_MACH_EXYNOS4_DT=y
-CONFIG_MACH_EXYNOS5_DT=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
@@ -30,35 +31,54 @@ CONFIG_NET_KEY=y
 CONFIG_INET=y
 CONFIG_RFKILL_REGULATOR=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=m
 CONFIG_NETDEVICES=y
 CONFIG_SMSC911X=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
+CONFIG_KEYBOARD_CROS_EC=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_MOUSE_CYAPA=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_SAMSUNG=y
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_HW_RANDOM=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
 CONFIG_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_I2C_S3C2410=y
+CONFIG_DEBUG_GPIO=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_I2C=y
+CONFIG_MFD_MAX77686=y
 CONFIG_MFD_TPS65090=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
 CONFIG_EXYNOS_VIDEO=y
 CONFIG_EXYNOS_MIPI_DSI=y
 CONFIG_EXYNOS_DP=y
@@ -67,6 +87,19 @@ CONFIG_FONTS=y
 CONFIG_FONT_7x14=y
 CONFIG_LOGO=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_S5P=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_PHY=y
+CONFIG_SAMSUNG_USB2PHY=y
+CONFIG_SAMSUNG_USB3PHY=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_IDMAC=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
@@ -79,6 +112,7 @@ CONFIG_ROMFS_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
@@ -87,6 +121,5 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_SHA256=y
 CONFIG_CRC_CCITT=y
-- 
1.8.2.1



From davem at davemloft.net  Thu May  9 17:04:33 2013
From: davem at davemloft.net (David Miller)
Date: Thu, 09 May 2013 14:04:33 -0700 (PDT)
Subject: [PATCHv2] net: smsc911x: don't artificially limit build
In-Reply-To: <20130509102650.GC8258@e106331-lin.cambridge.arm.com>
References: <1368095027-8448-1-git-send-email-mark.rutland@arm.com>
 <20130509102650.GC8258@e106331-lin.cambridge.arm.com>
Message-ID: <20130509.140433.661245947462377290.davem@davemloft.net>

From: Mark Rutland <mark.rutland at arm.com>
Date: Thu, 9 May 2013 11:26:50 +0100

> This should of course be PATCH, not PATCHv2.
> 
> I blame my shell's command history completion.

That's the least of your problems.

Every single list posting bounces when it is sent to your address,
with error "550 Envelope blocked - User Entry - http://www.mimecast.com/knowledgebase/KBID10473.htm#550"

I've unsubscribed you and I'm ignoring your patch submissions until
your email is actually working properly.


From linux at arm.linux.org.uk  Thu May  9 17:33:49 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 22:33:49 +0100
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <201305080142.12025.arnd@arndb.de>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <20130507230445.GC9105@kroah.com> <201305080142.12025.arnd@arndb.de>
Message-ID: <20130509213349.GN21614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 01:42:11AM +0200, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Greg Kroah-Hartman wrote:
> > On Tue, May 07, 2013 at 04:53:52PM -0600, Stephen Warren wrote:
> > > From: Stephen Warren <swarren at nvidia.com>
> 
> > > Suggested-by: Arnd Bergmann <arnd at arndb.de>
> > > Signed-off-by: Stephen Warren <swarren at nvidia.com>
> > 
> > So this needs to go in for 3.10, right?  Any older kernels as well?  If
> > so, which ones?
> 
> The fix should definitely go into 3.10, but I'd suggest waiting with
> the backport for a couple of -rc releases to avoid possible regressions.
> We know that the current code is broken, but few people fully understand
> what is going on with coherent_dma_mask, so it might cause new problems
> in combination with some other unknown bug, and I don't see this as
> urgent: none of the ARM defconfigs build this driver as a loadable
> module and there is no bug in the built-in case. For some reason, only
> the ARM back-end drivers are broken.
> 
> The first occurence was apparently in 3.3, but only in ehci-tegra.c,
> while the other drivers subsequently copied the bug.

I've already suggested this approach:

diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index dc662fc..51bb740 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -22,6 +22,7 @@ struct dev_archdata {
 struct omap_device;
 
 struct pdev_archdata {
+	u64 dma_mask;
 #ifdef CONFIG_ARCH_OMAP
 	struct omap_device *od;
 #endif

And then we can have dev->dma_mask pointed at that instead, which fully
eliminates any possible problems of things like dma_set_mask() interfering
with dma_set_coherent_mask().

Even better - because this is a common problem - would be to make 'dma_mask'
be a member of struct platform_device so that all arches can sort this
out once and for all (correction: generic code/drivers can in an arch-
independent way.)  IOW:

diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 9abf1db..121c74c 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -26,6 +26,7 @@ struct platform_device {
 	struct device	dev;
 	u32		num_resources;
 	struct resource	*resource;
+	u64		dma_mask;
 
 	const struct platform_device_id	*id_entry;
 



From linux at arm.linux.org.uk  Thu May  9 17:36:37 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 22:36:37 +0100
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <CAL411-qVnm0_wwdAiAp9eq_hYkXzFSmRMLAmknpSAG7Jb3bM9A@mail.gmail.com>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
Message-ID: <20130509213637.GO21614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 10:54:48AM +0800, Peter Chen wrote:
> >
> > This probably could be initialized from some DT property. However,
> > there's no such property defined right now, and considering that DT is
> > supposed to be an ABI, we'd always need the code in this patch as a
> > fallback for DTs that were created before any such property was defined.
> >
> > Equally, since the data is SoC-specific rather than board-specific, and
> > is even fairly unlikely to vary between SoC versions since these values
> > are all 0xffffffff anyway, I don't really see much point in putting it
> > into DT, rather than just putting the static data into the driver.
> 
> I mean there is already dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
> at function of_platform_device_create, why can't add
> dev->dev.dma_mask = &dev->dev.coherent_dma_mask after that?

Because technically they're different things, and if we have a driver
somewhere which uses the DMA API correctly by making use of
dma_set_mask() and dma_set_coherent_mask(), the two will interfere with
each other.

These two masks have always been separate.


From linux at arm.linux.org.uk  Thu May  9 17:39:08 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 May 2013 22:39:08 +0100
Subject: [PATCH] USB: set device dma_mask without reference to global data
In-Reply-To: <201305080924.44622.arnd@arndb.de>
References: <1367967232-10128-1-git-send-email-swarren@wwwdotorg.org>
 <5189B7BF.8070607@wwwdotorg.org>
 <CAL411-pY_i19otiE2pLux6eR_OFHhfhK=+6BF=H6wABDsGCP6Q@mail.gmail.com>
 <201305080924.44622.arnd@arndb.de>
Message-ID: <20130509213908.GP21614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 09:24:44AM +0200, Arnd Bergmann wrote:
> It probably should. The main thing is that the dma_mask setting in
> of_platform (and elsewhere) is a mess and that nobody so far had the
> guts to try to get it right for good.
> 
> Setting a 32 bit DMA mask is /probably/ the right default on all
> ARM systems, but there are caveats:
> 
> - Once you get to systems with larger than 32 bit addressing (powerpc64,
>   arm64, arm32 with LPAE), it's not so obvious: you may have some devices
>   that need a 32 bit mask and some that need a 64 bit mask.

This is precisely why drivers should be using dma_set_mask() and the
coherent version to provide the mask for which the driver knows about
- iow, if the device itself is only capable of 32-bit DMA, then the
device must use dma_set_mask(dev, DMA_BIT_MASK(32)).


From akpm at linux-foundation.org  Thu May  9 18:01:21 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Thu, 9 May 2013 15:01:21 -0700
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1367937595-32241-2-git-send-email-holt@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-2-git-send-email-holt@sgi.com>
Message-ID: <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>

On Tue,  7 May 2013 09:39:45 -0500 Robin Holt <holt at sgi.com> wrote:

> From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>
> 
> There are instances in the kernel where we would like to disable
> CPU hotplug (from sysfs) during some important operation. Today
> the freezer code depends on this and the code to do it was kinda
> tailor-made for that.
> 
> Restructure the code and make it generic enough to be useful for
> other usecases too.
> 
> ...
>
> --- a/include/linux/cpu.h
> +++ b/include/linux/cpu.h
> @@ -141,6 +141,8 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
>  }
>  #endif
>  
> +extern void cpu_hotplug_disable(void);
> +extern void cpu_hotplug_enable(void);
>  int cpu_up(unsigned int cpu);
>  void notify_cpu_starting(unsigned int cpu);
>  extern void cpu_maps_update_begin(void);
> @@ -148,6 +150,7 @@ extern void cpu_maps_update_done(void);
>  
>  #else	/* CONFIG_SMP */
>  
> +#define cpu_hotplug_disable()	do { } while (0)
>  #define cpu_notifier(fn, pri)	do { (void)(fn); } while (0)
>  

Breaks alpha allmodconfig because cpu_hotplug_disable() is absent from
vmlinux.

cpu_hotplug_disable() doesn't get compiled unless we've defined
CONFIG_PM_SLEEP_SMP.  I cannot begin to imagine what the logic is
behind that!

I'll stick this in there and see what happens.

--- a/include/linux/cpu.h~cpu-hotplug-provide-a-generic-helper-to-disable-enable-cpu-hotplug-fix
+++ a/include/linux/cpu.h
@@ -141,8 +141,6 @@ static inline void unregister_cpu_notifi
 }
 #endif
 
-extern void cpu_hotplug_disable(void);
-extern void cpu_hotplug_enable(void);
 int cpu_up(unsigned int cpu);
 void notify_cpu_starting(unsigned int cpu);
 extern void cpu_maps_update_begin(void);
@@ -150,7 +148,6 @@ extern void cpu_maps_update_done(void);
 
 #else	/* CONFIG_SMP */
 
-#define cpu_hotplug_disable()	do { } while (0)
 #define cpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 
 static inline int register_cpu_notifier(struct notifier_block *nb)
@@ -171,6 +168,15 @@ static inline void cpu_maps_update_done(
 }
 
 #endif /* CONFIG_SMP */
+
+#ifdef CONFIG_PM_SLEEP_SMP
+extern void cpu_hotplug_enable(void);
+extern void cpu_hotplug_disable(void);
+#else
+#define cpu_hotplug_enable()	do { } while (0)
+#define cpu_hotplug_disable()	do { } while (0)
+#endif
+
 extern struct bus_type cpu_subsys;
 
 #ifdef CONFIG_HOTPLUG_CPU



From dianders at chromium.org  Thu May  9 18:07:25 2013
From: dianders at chromium.org (Doug Anderson)
Date: Thu, 9 May 2013 15:07:25 -0700
Subject: [PATCH] ARM: exynos: defconfig update
In-Reply-To: <1368133099-16997-1-git-send-email-olof@lixom.net>
References: <1368133099-16997-1-git-send-email-olof@lixom.net>
Message-ID: <CAD=FV=VMCLk0h0XxJv1Q3EkpottVkpwKEa87McmmipdJA7TN+A@mail.gmail.com>

Olof,

On Thu, May 9, 2013 at 1:58 PM, Olof Johansson <olof at lixom.net> wrote:
> +CONFIG_ZBOOT_ROM_TEXT=0x0
> +CONFIG_ZBOOT_ROM_BSS=0x0

Probably these aren't needed, but don't hurt since the default is 0.
This seems to pop up a lot since there are lots of legacy configs that
have 0x0 here.

Either with or without that fixup, this looks reasonable to me.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From kgene.kim at samsung.com  Thu May  9 19:29:40 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 May 2013 08:29:40 +0900
Subject: [PATCH] ARM: exynos: Select PINCTRL_EXYNOS for exynos5
In-Reply-To: <CAD=FV=X1XL++O43GBcJK5Js=ci8pfoj=uSADMcqq_jGJEvhXdQ@mail.gmail.com>
References: <1368034349-15091-1-git-send-email-dianders@chromium.org>
 <CAD=FV=X2n+zHZ3frorwW7L1yybnWWK1=-rWMQJQFus3eNiFFeQ@mail.gmail.com>
 <CAOesGMi=K4iJKjSk3RoynhiCMPPT98v5jADnqZ__TwX_YLw65Q@mail.gmail.com>
 <1614776.P66h1VoFPp@amdc1227>
 <CAD=FV=X1XL++O43GBcJK5Js=ci8pfoj=uSADMcqq_jGJEvhXdQ@mail.gmail.com>
Message-ID: <044901ce4d0d$142a8e90$3c7fabb0$%kim@samsung.com>

Doug Anderson wrote:
> 
> Tomasz / Olof,
> 
Hi Doug, Tomasz and Olof

> On Thu, May 9, 2013 at 2:45 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> >> Nothing stops you from doing that on your own. I tend to push back
> >> onto the maintainers to get them engaged in their own housekeeping,
> >> but anyone is free to :)
> 
> I will probably leave this to the maintainers at this point...  ;)
> 


> >> Yeah, it should -- this is just in transition since 5440 was first out
> >> of the gate with pinctrl.
> >
> > AFAIK, Exynos5440 contains a completely different pin controller block,
> which
> > is not compatible with pinctrl-samsung driver, so I don't see any point
> of
> > moving it under PINCTRL_EXYNOS, which is currently used for Exynos 4210,
> 4x12
> > and 5250, but will be also extended with driver data for S5PV210 as
well.
> >
> > I'd say that CPU_EXYNOS4210, SOC_EXYNOS4212, SOC_EXYNOS4412 and
> SOC_EXYNOS5250
> > should select PINCTRL_EXYNOS and SOC_EXYNOS5440 should be left as is,
> > selecting PINCTRL_EXYNOS5440.
> 
> OK, sounds reasonable.  I didn't dig into all of the details of the
> 5440 pin control driver and don't have a user manual in front of me.
> I will do as you say.
> 
Tomasz is right. The current exynos pinctrl stuff is quite different with
exynos5440 pinctrl, it means there is no reason to move exynos5440 pinctrl
under exynos pinctrl. Of course, both can be built together without problem.

> New patch coming shortly.
> 
Thanks, the PINCTRL_EXYNOS can be moved into under SoC condition not board.

- Kukjin



From kgene.kim at samsung.com  Thu May  9 19:32:07 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 May 2013 08:32:07 +0900
Subject: [PATCH] ARM: EXYNOS5: Fix kernel dump in AFTR idle mode
In-Reply-To: <20130509202208.GA21831@quad.lixom.net>
References: <1367235107-31328-1-git-send-email-inderpal.singh@linaro.org>
 <20130509202208.GA21831@quad.lixom.net>
Message-ID: <044a01ce4d0d$6bf36570$43da3050$%kim@samsung.com>

Olof Johansson wrote:
> 
> On Mon, Apr 29, 2013 at 05:01:47PM +0530, Inderpal Singh wrote:
> > The kernel crashes while resuming from AFTR idle mode. It happens
> > because L2 cache was not going into retention state.
> >
> > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register
> > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of
> > ARM_COMMON_OPTION register for L2RSTDISABLE signal.
> >
> > Signed-off-by: Inderpal Singh <inderpal.singh at linaro.org>
> 
> I haven't seen any activity from Kgene on this, but it seems reasonably
> bad

I spent time with my family last week...

> (and the fix is self-contained). Applying to arm-soc fixes branch.
> 
Anyway, thanks.

- Kukjin



From olof at lixom.net  Thu May  9 19:47:54 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 16:47:54 -0700
Subject: [GIT PULL] Late Exynos stuff for v3.10
In-Reply-To: <51794E10.1010205@samsung.com>
References: <5176B499.1000208@samsung.com> <51770697.7080504@samsung.com>
 <20130424000638.GA9067@quad.lixom.net>
 <51794E10.1010205@samsung.com>
Message-ID: <CAOesGMjA5_XUXMcCL3roZiLC1S=ypMoVHn2tF7bzUuKr+eLw2A@mail.gmail.com>

Kukjin,

On Thu, Apr 25, 2013 at 8:38 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:

>> It doesn't have to be something super-elaborate, but I'd like it to be
>> sort of
>> self-documenting in a way that I don't have to look through the series of
>> patches to get an overview of what's in the branch. Of course we'll also
>> do
>> that to review the code, but having the description there makes things
>> easier
>> for us to tell if we should even be looking at it, etc.
>>
>>
> OK, I see. Let me do it more carefully.
>
> And let me send pull-request again for fix and late dt branch with separated
> branches in a couple of hours not including usb stuff...

Refresh my memory here, what was the reason for dropping the USB DTS
updates? (Yes, I am aware it might because I asked you not to send
them in but I don't remember :-).

Also, when you drop stuff, please, please don't keep it in your own
for-next branch. The end result is that we'll keep testing something
on linux-next with the anticipation that it will work when it lands in
the merge window, when that's not the truth if you're not going to
send the pull requests up.

So, if you decide to keep code like this out of the merge window (or
if we push back at it and say no to it), then remove it from your
for-next branch as well.

In particular, the usb phy node for usb2 would ber very good to get in
for 3.10, since it's a critical piece to get usb2 working on the
Chromebook.

-Olof


From s-anna at ti.com  Thu May  9 19:43:59 2013
From: s-anna at ti.com (Suman Anna)
Date: Thu, 9 May 2013 18:43:59 -0500
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <CAJe_Zhffm9FOk83dAdX194gN3r5JnG78sdcWNv6WnWCsTF3YuA@mail.gmail.com>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
 <518BCF4B.1060504@ti.com>
 <CAJe_Zhd=FDV3YP=XR8Yay1iy_geAt3tqj+diUxrVkd2BFSfb-g@mail.gmail.com>
 <518BD197.2030502@ti.com>
 <CABb+yY2CnO5RiQNdcB_L5ZiGi829Ys0ODH2UmhtZxj=aJo3ioQ@mail.gmail.com>
 <518BE566.5090504@ti.com>
 <CAJe_Zhffm9FOk83dAdX194gN3r5JnG78sdcWNv6WnWCsTF3YuA@mail.gmail.com>
Message-ID: <518C34BF.7080408@ti.com>

Jassi,

>>>
>>> Perhaps we should change the following
>>>
>>>    void ipc_link_txdone(struct ipc_link *link, enum xfer_result r)
>>> to
>>>    void ipc_link_txdone(struct ipc_link *link, enum xfer_result r, void *data)
>>>
>>> So that the API could pass that onto clients ?
>>
>> That's if the controller needs to pass some data back to client. I am
>> fine with that as well,
> No, I misunderstood you wanted request_token_t to be replaced with the
> pointer of request that was executed.
> 
>> but I am talking mainly about providing a client
>> user data ptr back to it during callbacks.
>>
>> struct ipc_client {
>>         char *chan_name;
>> +       void *cl_data; /* store it to ipc_chan as well */
>> -       void (*rxcb)(void *data);
>> -       void (*txcb)(request_token_t t, enum xfer_result r);
>> +       void (*rxcb)(void *cl_data, void *data);
>> +       void (*txcb)(request_token_t t, enum xfer_result r, void *cl_data);
>>         ...
>> }
>>
>> I am obviously interested in the rxcb. The controller implementations do
>> not see the cl_data.
>>
> OK I see what you mean. However the API storing and passing back
> ad-hoc data to clients doesn't seem very neat.
> 
> Such purposes are usually served by :
> 
> - void (*rxcb)(void *data);
> + void (*rxcb)(struct ipc_client *cl, void *data);  /* client for
> which data was received */
> 
> - void (*txcb)(request_token_t t, enum xfer_result r);
> + void (*txcb)(struct ipc_client *cl, request_token_t t, enum
> xfer_result r); /* client whose data was sent */
> 
> You could then get relevant omap_rproc using container_of() on 'cl',
> in rxcb() and txcb().

The reason that I didn't suggest that way is because we do not use
ipc_client for any runtime API, and we would have to store the returned
handle anyway. I see ipc_client simply as a ipc_channel_request_info
structure, a one-time usage perspective. I made the suggestion as it
seemed in line if you had a xxx_register_callback API wherein you would
use a void *context if you want something back.

> 
> Apart from this, in txcb, perhaps we should drop request_token_t in
> favor of the request's pointer (void *data) that was last executed.
> That should make things easier for clients.

Yes, that would be nice too.

regards
Suman



From olof at lixom.net  Thu May  9 19:49:58 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 16:49:58 -0700
Subject: [PATCH] ARM: EXYNOS5: Fix kernel dump in AFTR idle mode
In-Reply-To: <044a01ce4d0d$6bf36570$43da3050$%kim@samsung.com>
References: <1367235107-31328-1-git-send-email-inderpal.singh@linaro.org>
 <20130509202208.GA21831@quad.lixom.net>
 <044a01ce4d0d$6bf36570$43da3050$%kim@samsung.com>
Message-ID: <CAOesGMi0KnkXt0ihWtvVXpWiAq7WvySDC6Rg0=4PTs8d5tTxig@mail.gmail.com>

On Thu, May 9, 2013 at 4:32 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Olof Johansson wrote:
>>
>> On Mon, Apr 29, 2013 at 05:01:47PM +0530, Inderpal Singh wrote:
>> > The kernel crashes while resuming from AFTR idle mode. It happens
>> > because L2 cache was not going into retention state.
>> >
>> > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register
>> > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of
>> > ARM_COMMON_OPTION register for L2RSTDISABLE signal.
>> >
>> > Signed-off-by: Inderpal Singh <inderpal.singh at linaro.org>
>>
>> I haven't seen any activity from Kgene on this, but it seems reasonably
>> bad
>
> I spent time with my family last week...
>
>> (and the fix is self-contained). Applying to arm-soc fixes branch.
>>
> Anyway, thanks.

No worries. :)


-Olof


From olof at lixom.net  Thu May  9 19:55:33 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 9 May 2013 16:55:33 -0700
Subject: [PATCH 0/2] ARM: tegra: a couple clock bug-fixes
In-Reply-To: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
References: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20130509235533.GA19697@quad.lixom.net>

On Mon, May 06, 2013 at 03:11:09PM -0600, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Arnd, Olof,
> 
> The following two patches fix a couple issues in the Tegra20 clock driver
> that show up on specific platforms. They were sent a little late for 3.9,
> and I forgot to include them for 3.10 since they weren't reposted:-(

Applied to fixes now, sorry for missing them earlier.

> Patch 1 is clearly a bug-fix. Someone pedantic could argue that patch 2
> is a new feature since it's the last piece to enabling AC'97 support, but
> I'd argue that it's a bug in the clock driver that it didn't support this
> clock when it was first written:-)

For very early -rc we can be a bit more flexible, so this is ok with me at the
moment.

> These patches logically belong to Tegra's for-3.10/clk branch, but feel
> free to apply them where is easiest; it'd be fine to defer them to a post-
> 3.10-rc1 fixes branch too if you want.

Postponed in effect due to missing them earlier.

Btw, since the drivers have moved and most of the churn is completed, fixes
like these really can go straight to Mike Turquette from here on out.


-Olof



From holt at sgi.com  Thu May  9 20:05:53 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 9 May 2013 19:05:53 -0500
Subject: [PATCH -v9 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <20130509135100.13947d1805a583703ee8488b@linux-foundation.org>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
 <1368127405-112717-5-git-send-email-holt@sgi.com>
 <20130509135100.13947d1805a583703ee8488b@linux-foundation.org>
Message-ID: <20130510000552.GX3658@sgi.com>

On Thu, May 09, 2013 at 01:51:00PM -0700, Andrew Morton wrote:
> On Thu,  9 May 2013 14:23:18 -0500 Robin Holt <holt at sgi.com> wrote:
> 
> > This patch is preparatory.  It moves reboot related syscall, etc
> > functions from kernel/sys.c to kernel/reboot.c.
> 
> This doesn't apply.

Weird, I just grabbed a recent Linus kernel tree and all 11 applied.
I then did an update to linus' tree to commit 70eba4226 and now I get
rejects on arm.  I will resubmit a -v10 fixed up shortly.

Robin

> 
> > -static void migrate_to_reboot_cpu(void)
> > -{
> > -	/* The boot cpu is always logical cpu 0 */
> > -	int cpu = 0;
> > -
> > -	cpu_hotplug_disable();
> > -
> > -	/* Make certain the cpu I'm about to reboot on is online */
> > -	if (!cpu_online(cpu))
> > -		cpu = cpumask_first(cpu_online_mask);
> 
> Here it's deleting code which was already modified by "[PATCH -v9
> 02/11] Migrate shutdown/reboot to boot cpu.".  So patch [4/11]
> generates rejects when applied on top of [patch 2/11].
> 
> There are several similar glitches.


From john.stultz at linaro.org  Thu May  9 20:10:48 2013
From: john.stultz at linaro.org (John Stultz)
Date: Thu,  9 May 2013 17:10:48 -0700
Subject: [PATCH 0/3] ARM: KDB FIQ debugger
Message-ID: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>

Hey all,
	Just wanted to try to revive Anton's KDB FIQ patches
which have been sent out a number of times since last October
and have gotten almost no response at all.

I've simply updated them to apply to Linus' current HEAD,
and figured I'd send them out again to try to spur some
interest.

Any feedback would be appreciated!

thanks
-john

Short description of the KDB/FIQ debugger:

 The FIQ debugger is a facility that can be used to debug situations when
 the kernel stuck in uninterruptable sections, e.g. the kernel infinitely
 loops or deadlocked in an interrupt or with interrupts disabled. On some
 development boards there is even a special NMI button, which is very
 useful for debugging weird kernel hangs.

 And FIQ is basically an NMI, it has a higher priority than IRQs, and upon
 IRQ exception FIQs are not disabled. It is still possible to disable FIQs
 (as well as some "NMIs" on other architectures), but via special means.

Old changelogs and a full rationale for these patches can be found here:

	v1-v5, rationale: http://lkml.org/lkml/2012/9/10/2
	v6: http://lkml.org/lkml/2012/9/10/2
	v7: http://lkml.org/lkml/2012/9/13/367
	v8: http://lkml.org/lkml/2012/9/19/525
	v9: http://lkml.org/lkml/2012/9/24/538


Cc: Anton Vorontsov <anton.vorontsov at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Wessel <jason.wessel at windriver.com>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: kernel-team at android.com


Anton Vorontsov (3):
  ARM: Move some macros from entry-armv to entry-header
  ARM: Add KGDB/KDB FIQ debugger generic code
  ARM: versatile: Make able to use UART ports for KGDB FIQ debugger

 arch/arm/Kconfig                   |  19 +++++
 arch/arm/include/asm/kgdb.h        |   7 ++
 arch/arm/kernel/Makefile           |   1 +
 arch/arm/kernel/entry-armv.S       | 169 +-----------------------------------
 arch/arm/kernel/entry-header.S     | 171 +++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/kgdb_fiq.c         | 118 +++++++++++++++++++++++++
 arch/arm/kernel/kgdb_fiq_entry.S   |  87 +++++++++++++++++++
 arch/arm/mach-versatile/Makefile   |   1 +
 arch/arm/mach-versatile/kgdb_fiq.c |  55 ++++++++++++
 9 files changed, 460 insertions(+), 168 deletions(-)
 create mode 100644 arch/arm/kernel/kgdb_fiq.c
 create mode 100644 arch/arm/kernel/kgdb_fiq_entry.S
 create mode 100644 arch/arm/mach-versatile/kgdb_fiq.c

-- 
1.8.1.2



From john.stultz at linaro.org  Thu May  9 20:10:49 2013
From: john.stultz at linaro.org (John Stultz)
Date: Thu,  9 May 2013 17:10:49 -0700
Subject: [PATCH 1/3] ARM: Move some macros from entry-armv to entry-header
In-Reply-To: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
References: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
Message-ID: <1368144651-11250-2-git-send-email-john.stultz@linaro.org>

From: Anton Vorontsov <anton.vorontsov at linaro.org>

Just move the macros into header file as we would want to use them for
KGDB FIQ entry code.

The following macros were moved:

 - svc_entry
 - usr_entry
 - kuser_cmpxchg_check
 - vector_stub

To make kuser_cmpxchg_check actually work across different files, we
also have to make kuser_cmpxchg64_fixup global.

Cc: Anton Vorontsov <anton.vorontsov at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Wessel <jason.wessel at windriver.com>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: kernel-team at android.com
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
Signed-off-by: John Stultz <john.stultz at linaro.org>
---
 arch/arm/kernel/entry-armv.S   | 169 +---------------------------------------
 arch/arm/kernel/entry-header.S | 171 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 172 insertions(+), 168 deletions(-)

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582b405..35b19cd 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -136,57 +136,6 @@ common_invalid:
 	b	bad_mode
 ENDPROC(__und_invalid)
 
-/*
- * SVC mode handlers
- */
-
-#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
-#define SPFIX(code...) code
-#else
-#define SPFIX(code...)
-#endif
-
-	.macro	svc_entry, stack_hole=0
- UNWIND(.fnstart		)
- UNWIND(.save {r0 - pc}		)
-	sub	sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
-#ifdef CONFIG_THUMB2_KERNEL
- SPFIX(	str	r0, [sp]	)	@ temporarily saved
- SPFIX(	mov	r0, sp		)
- SPFIX(	tst	r0, #4		)	@ test original stack alignment
- SPFIX(	ldr	r0, [sp]	)	@ restored
-#else
- SPFIX(	tst	sp, #4		)
-#endif
- SPFIX(	subeq	sp, sp, #4	)
-	stmia	sp, {r1 - r12}
-
-	ldmia	r0, {r3 - r5}
-	add	r7, sp, #S_SP - 4	@ here for interlock avoidance
-	mov	r6, #-1			@  ""  ""      ""       ""
-	add	r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
- SPFIX(	addeq	r2, r2, #4	)
-	str	r3, [sp, #-4]!		@ save the "real" r0 copied
-					@ from the exception stack
-
-	mov	r3, lr
-
-	@
-	@ We are now ready to fill in the remaining blanks on the stack:
-	@
-	@  r2 - sp_svc
-	@  r3 - lr_svc
-	@  r4 - lr_<exception>, already fixed up for correct return/restart
-	@  r5 - spsr_<exception>
-	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
-	@
-	stmia	r7, {r2 - r6}
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-	bl	trace_hardirqs_off
-#endif
-	.endm
-
 	.align	5
 __dabt_svc:
 	svc_entry
@@ -305,72 +254,7 @@ ENDPROC(__pabt_svc)
 
 /*
  * User mode handlers
- *
- * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
  */
-
-#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
-#error "sizeof(struct pt_regs) must be a multiple of 8"
-#endif
-
-	.macro	usr_entry
- UNWIND(.fnstart	)
- UNWIND(.cantunwind	)	@ don't unwind the user space
-	sub	sp, sp, #S_FRAME_SIZE
- ARM(	stmib	sp, {r1 - r12}	)
- THUMB(	stmia	sp, {r0 - r12}	)
-
-	ldmia	r0, {r3 - r5}
-	add	r0, sp, #S_PC		@ here for interlock avoidance
-	mov	r6, #-1			@  ""  ""     ""        ""
-
-	str	r3, [sp]		@ save the "real" r0 copied
-					@ from the exception stack
-
-	@
-	@ We are now ready to fill in the remaining blanks on the stack:
-	@
-	@  r4 - lr_<exception>, already fixed up for correct return/restart
-	@  r5 - spsr_<exception>
-	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
-	@
-	@ Also, separately save sp_usr and lr_usr
-	@
-	stmia	r0, {r4 - r6}
- ARM(	stmdb	r0, {sp, lr}^			)
- THUMB(	store_user_sp_lr r0, r1, S_SP - S_PC	)
-
-	@
-	@ Enable the alignment trap while in kernel mode
-	@
-	alignment_trap r0
-
-	@
-	@ Clear FP to mark the first stack frame
-	@
-	zero_fp
-
-#ifdef CONFIG_IRQSOFF_TRACER
-	bl	trace_hardirqs_off
-#endif
-	ct_user_exit save = 0
-	.endm
-
-	.macro	kuser_cmpxchg_check
-#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
-#ifndef CONFIG_MMU
-#warning "NPTL on non MMU needs fixing"
-#else
-	@ Make sure our user space atomic helper is restarted
-	@ if it was interrupted in a critical region.  Here we
-	@ perform a quick test inline since it should be false
-	@ 99.9999% of the time.  The rest is done out of line.
-	cmp	r4, #TASK_SIZE
-	blhs	kuser_cmpxchg64_fixup
-#endif
-#endif
-	.endm
-
 	.align	5
 __dabt_usr:
 	usr_entry
@@ -803,6 +687,7 @@ __kuser_cmpxchg64:				@ 0xffff0f60
 	ldmfd	sp!, {r4, r5, r6, pc}
 
 	.text
+	.global kuser_cmpxchg64_fixup
 kuser_cmpxchg64_fixup:
 	@ Called from kuser_cmpxchg_fixup.
 	@ r4 = address of interrupted insn (must be preserved).
@@ -933,58 +818,6 @@ __kuser_helper_end:
 
  THUMB(	.thumb	)
 
-/*
- * Vector stubs.
- *
- * This code is copied to 0xffff0200 so we can use branches in the
- * vectors, rather than ldr's.  Note that this code must not
- * exceed 0x300 bytes.
- *
- * Common stub entry macro:
- *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
- *
- * SP points to a minimal amount of processor-private memory, the address
- * of which is copied into r0 for the mode specific abort handler.
- */
-	.macro	vector_stub, name, mode, correction=0
-	.align	5
-
-vector_\name:
-	.if \correction
-	sub	lr, lr, #\correction
-	.endif
-
-	@
-	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
-	@ (parent CPSR)
-	@
-	stmia	sp, {r0, lr}		@ save r0, lr
-	mrs	lr, spsr
-	str	lr, [sp, #8]		@ save spsr
-
-	@
-	@ Prepare for SVC32 mode.  IRQs remain disabled.
-	@
-	mrs	r0, cpsr
-	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
-	msr	spsr_cxsf, r0
-
-	@
-	@ the branch table must immediately follow this code
-	@
-	and	lr, lr, #0x0f
- THUMB(	adr	r0, 1f			)
- THUMB(	ldr	lr, [r0, lr, lsl #2]	)
-	mov	r0, sp
- ARM(	ldr	lr, [pc, lr, lsl #2]	)
-	movs	pc, lr			@ branch to handler in SVC mode
-ENDPROC(vector_\name)
-
-	.align	2
-	@ handler addresses follow this label
-1:
-	.endm
-
 	.globl	__stubs_start
 __stubs_start:
 /*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 160f337..41de38b 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -73,6 +73,109 @@
 	msr	cpsr_c, \rtemp			@ switch back to the SVC mode
 	.endm
 
+/*
+ * Vector stubs.
+ *
+ * This code is copied to 0xffff0200 so we can use branches in the
+ * vectors, rather than ldr's.  Note that this code must not
+ * exceed 0x300 bytes.
+ *
+ * Common stub entry macro:
+ *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
+ *
+ * SP points to a minimal amount of processor-private memory, the address
+ * of which is copied into r0 for the mode specific abort handler.
+ */
+	.macro	vector_stub, name, mode, correction=0
+	.align	5
+
+vector_\name:
+	.if \correction
+	sub	lr, lr, #\correction
+	.endif
+
+	@
+	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
+	@ (parent CPSR)
+	@
+	stmia	sp, {r0, lr}		@ save r0, lr
+	mrs	lr, spsr
+	str	lr, [sp, #8]		@ save spsr
+
+	@
+	@ Prepare for SVC32 mode.  IRQs remain disabled.
+	@
+	mrs	r0, cpsr
+	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
+	msr	spsr_cxsf, r0
+
+	@
+	@ the branch table must immediately follow this code
+	@
+	and	lr, lr, #0x0f
+ THUMB(	adr	r0, 1f			)
+ THUMB(	ldr	lr, [r0, lr, lsl #2]	)
+	mov	r0, sp
+ ARM(	ldr	lr, [pc, lr, lsl #2]	)
+	movs	pc, lr			@ branch to handler in SVC mode
+ENDPROC(vector_\name)
+
+	.align	2
+	@ handler addresses follow this label
+1:
+	.endm
+
+/*
+ * SVC mode handlers
+ */
+
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
+#define SPFIX(code...) code
+#else
+#define SPFIX(code...)
+#endif
+
+	.macro	svc_entry, stack_hole=0
+ UNWIND(.fnstart		)
+ UNWIND(.save {r0 - pc}		)
+	sub	sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+#ifdef CONFIG_THUMB2_KERNEL
+ SPFIX(	str	r0, [sp]	)	@ temporarily saved
+ SPFIX(	mov	r0, sp		)
+ SPFIX(	tst	r0, #4		)	@ test original stack alignment
+ SPFIX(	ldr	r0, [sp]	)	@ restored
+#else
+ SPFIX(	tst	sp, #4		)
+#endif
+ SPFIX(	subeq	sp, sp, #4	)
+	stmia	sp, {r1 - r12}
+
+	ldmia	r0, {r3 - r5}
+	add	r7, sp, #S_SP - 4	@ here for interlock avoidance
+	mov	r6, #-1			@  ""  ""      ""       ""
+	add	r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+ SPFIX(	addeq	r2, r2, #4	)
+	str	r3, [sp, #-4]!		@ save the "real" r0 copied
+					@ from the exception stack
+
+	mov	r3, lr
+
+	@
+	@ We are now ready to fill in the remaining blanks on the stack:
+	@
+	@  r2 - sp_svc
+	@  r3 - lr_svc
+	@  r4 - lr_<exception>, already fixed up for correct return/restart
+	@  r5 - spsr_<exception>
+	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
+	@
+	stmia	r7, {r2 - r6}
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+	bl	trace_hardirqs_off
+#endif
+	.endm
+
 #ifndef CONFIG_THUMB2_KERNEL
 	.macro	svc_exit, rpsr, irq = 0
 	.if	\irq != 0
@@ -226,6 +329,74 @@
 	.endm
 
 /*
+ * User mode handlers
+ *
+ * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
+ */
+
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
+#error "sizeof(struct pt_regs) must be a multiple of 8"
+#endif
+
+	.macro	usr_entry
+ UNWIND(.fnstart	)
+ UNWIND(.cantunwind	)	@ don't unwind the user space
+	sub	sp, sp, #S_FRAME_SIZE
+ ARM(	stmib	sp, {r1 - r12}	)
+ THUMB(	stmia	sp, {r0 - r12}	)
+
+	ldmia	r0, {r3 - r5}
+	add	r0, sp, #S_PC		@ here for interlock avoidance
+	mov	r6, #-1			@  ""  ""     ""        ""
+
+	str	r3, [sp]		@ save the "real" r0 copied
+					@ from the exception stack
+
+	@
+	@ We are now ready to fill in the remaining blanks on the stack:
+	@
+	@  r4 - lr_<exception>, already fixed up for correct return/restart
+	@  r5 - spsr_<exception>
+	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
+	@
+	@ Also, separately save sp_usr and lr_usr
+	@
+	stmia	r0, {r4 - r6}
+ ARM(	stmdb	r0, {sp, lr}^			)
+ THUMB(	store_user_sp_lr r0, r1, S_SP - S_PC	)
+
+	@
+	@ Enable the alignment trap while in kernel mode
+	@
+	alignment_trap r0
+
+	@
+	@ Clear FP to mark the first stack frame
+	@
+	zero_fp
+
+#ifdef CONFIG_IRQSOFF_TRACER
+	bl	trace_hardirqs_off
+#endif
+	ct_user_exit save = 0
+	.endm
+
+	.macro	kuser_cmpxchg_check
+#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
+#ifndef CONFIG_MMU
+#warning "NPTL on non MMU needs fixing"
+#else
+	@ Make sure our user space atomic helper is restarted
+	@ if it was interrupted in a critical region.  Here we
+	@ perform a quick test inline since it should be false
+	@ 99.9999% of the time.  The rest is done out of line.
+	cmp	r4, #TASK_SIZE
+	blhs	kuser_cmpxchg64_fixup
+#endif
+#endif
+	.endm
+
+/*
  * These are the registers used in the syscall handler, and allow us to
  * have in theory up to 7 arguments to a function - r0 to r6.
  *
-- 
1.8.1.2



From john.stultz at linaro.org  Thu May  9 20:10:50 2013
From: john.stultz at linaro.org (John Stultz)
Date: Thu,  9 May 2013 17:10:50 -0700
Subject: [PATCH 2/3] ARM: Add KGDB/KDB FIQ debugger generic code
In-Reply-To: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
References: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
Message-ID: <1368144651-11250-3-git-send-email-john.stultz@linaro.org>

From: Anton Vorontsov <anton.vorontsov at linaro.org>

The FIQ debugger may be used to debug situations when the kernel stuck
in uninterruptable sections, e.g. the kernel infinitely loops or
deadlocked in an interrupt or with interrupts disabled.

By default KGDB FIQ is disabled in runtime, but can be enabled with
kgdb_fiq.enable=1 kernel command line option.

Cc: Anton Vorontsov <anton.vorontsov at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Wessel <jason.wessel at windriver.com>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: kernel-team at android.com
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
Signed-off-by: John Stultz <john.stultz at linaro.org>
---
 arch/arm/Kconfig                 |  18 ++++++
 arch/arm/include/asm/kgdb.h      |   7 +++
 arch/arm/kernel/Makefile         |   1 +
 arch/arm/kernel/kgdb_fiq.c       | 118 +++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/kgdb_fiq_entry.S |  87 +++++++++++++++++++++++++++++
 5 files changed, 231 insertions(+)
 create mode 100644 arch/arm/kernel/kgdb_fiq.c
 create mode 100644 arch/arm/kernel/kgdb_fiq_entry.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1e31dac..66a9076 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -203,6 +203,24 @@ config GENERIC_ISA_DMA
 config FIQ
 	bool
 
+config ARCH_MIGHT_HAVE_KGDB_FIQ
+	bool
+
+config KGDB_FIQ
+	bool "KGDB/KDB FIQ debugger"
+	depends on KGDB_KDB && ARCH_MIGHT_HAVE_KGDB_FIQ && !THUMB2_KERNEL
+	select FIQ
+	help
+	  The FIQ debugger may be used to debug situations when the
+	  kernel stuck in uninterruptable sections, e.g. the kernel
+	  infinitely loops or deadlocked in an interrupt or with
+	  interrupts disabled.
+
+	  By default KGDB FIQ is disabled in runtime, but can be
+	  enabled with kgdb_fiq.enable=1 kernel command line option.
+
+	  If unsure, say N.
+
 config NEED_RET_TO_USER
 	bool
 
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h
index 48066ce..75019984 100644
--- a/arch/arm/include/asm/kgdb.h
+++ b/arch/arm/include/asm/kgdb.h
@@ -11,6 +11,8 @@
 #define __ARM_KGDB_H__
 
 #include <linux/ptrace.h>
+#include <linux/linkage.h>
+#include <asm/exception.h>
 
 /*
  * GDB assumes that we're a user process being debugged, so
@@ -47,6 +49,11 @@ static inline void arch_kgdb_breakpoint(void)
 extern void kgdb_handle_bus_error(void);
 extern int kgdb_fault_expected;
 
+extern char kgdb_fiq_handler;
+extern char kgdb_fiq_handler_end;
+asmlinkage void __exception_irq_entry kgdb_fiq_do_handle(struct pt_regs *regs);
+extern int __init kgdb_register_fiq(void (*mach_kgdb_enable_fiq)(bool on),
+				    bool (*mach_is_kgdb_fiq)(void));
 #endif /* !__ASSEMBLY__ */
 
 /*
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..863d266 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -56,6 +56,7 @@ endif
 obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
+obj-$(CONFIG_KGDB_FIQ)		+= kgdb_fiq_entry.o kgdb_fiq.o
 obj-$(CONFIG_ARM_UNWIND)	+= unwind.o
 obj-$(CONFIG_HAVE_TCM)		+= tcm.o
 obj-$(CONFIG_OF)		+= devtree.o
diff --git a/arch/arm/kernel/kgdb_fiq.c b/arch/arm/kernel/kgdb_fiq.c
new file mode 100644
index 0000000..bede9be
--- /dev/null
+++ b/arch/arm/kernel/kgdb_fiq.c
@@ -0,0 +1,118 @@
+/*
+ * KGDB FIQ
+ *
+ * Copyright 2010 Google, Inc.
+ *		  Arve Hj?nnev?g <arve at android.com>
+ *		  Colin Cross <ccross at android.com>
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/hardirq.h>
+#include <linux/atomic.h>
+#include <linux/kdb.h>
+#include <linux/kgdb.h>
+#include <asm/fiq.h>
+#include <asm/exception.h>
+
+static int kgdb_fiq_enabled;
+module_param_named(enable, kgdb_fiq_enabled, int, 0600);
+MODULE_PARM_DESC(enable, "set to 1 to enable FIQ KGDB");
+
+static bool (*is_kgdb_fiq)(void);
+static void (*kgdb_enable_fiq)(bool on);
+
+asmlinkage void __exception_irq_entry kgdb_fiq_do_handle(struct pt_regs *regs)
+{
+	if (!is_kgdb_fiq())
+		return;
+	if (!kgdb_nmi_poll_knock())
+		return;
+
+	nmi_enter();
+	kgdb_handle_exception(1, 0, 0, regs);
+	nmi_exit();
+}
+
+static struct fiq_handler kgdb_fiq_desc = {
+	.name = "kgdb",
+};
+
+static long kgdb_fiq_setup_stack(void *info)
+{
+	struct pt_regs regs;
+
+	regs.ARM_sp = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER) +
+			THREAD_START_SP;
+	WARN_ON(!regs.ARM_sp);
+
+	set_fiq_regs(&regs);
+	return 0;
+}
+
+/**
+ * kgdb_fiq_enable_nmi - Manage NMI-triggered entry to KGDB
+ * @on: Flag to either enable or disable an NMI
+ *
+ * This function manages NMIs that usually cause KGDB to enter. That is, not
+ * all NMIs should be enabled or disabled, but only those that issue
+ * kgdb_handle_exception().
+ *
+ * The call counts disable requests, and thus allows to nest disables. But
+ * trying to enable already enabled NMI is an error.
+ */
+static void kgdb_fiq_enable_nmi(bool on)
+{
+	static atomic_t cnt;
+	int ret;
+
+	ret = atomic_add_return(on ? 1 : -1, &cnt);
+	if (ret > 1 && on) {
+		/*
+		 * There should be only one instance that calls this function
+		 * in "enable, disable" order. All other users must call
+		 * disable first, then enable. If not, something is wrong.
+		 */
+		WARN_ON(1);
+		return;
+	}
+
+	kgdb_enable_fiq(ret > 0);
+}
+
+int __init kgdb_register_fiq(void (*mach_kgdb_enable_fiq)(bool on),
+			     bool (*mach_is_kgdb_fiq)(void))
+{
+	int err;
+	int cpu;
+
+	if (!kgdb_fiq_enabled)
+		return -ENODEV;
+
+	kgdb_enable_fiq = mach_kgdb_enable_fiq;
+	is_kgdb_fiq = mach_is_kgdb_fiq;
+
+	err = claim_fiq(&kgdb_fiq_desc);
+	if (err) {
+		pr_warn("%s: unable to claim fiq", __func__);
+		return err;
+	}
+
+	for_each_possible_cpu(cpu)
+		work_on_cpu(cpu, kgdb_fiq_setup_stack, NULL);
+
+	set_fiq_handler(&kgdb_fiq_handler,
+			&kgdb_fiq_handler_end - &kgdb_fiq_handler);
+
+	arch_kgdb_ops.enable_nmi = kgdb_fiq_enable_nmi;
+	return 0;
+}
diff --git a/arch/arm/kernel/kgdb_fiq_entry.S b/arch/arm/kernel/kgdb_fiq_entry.S
new file mode 100644
index 0000000..d6becca
--- /dev/null
+++ b/arch/arm/kernel/kgdb_fiq_entry.S
@@ -0,0 +1,87 @@
+/*
+ * KGDB FIQ entry
+ *
+ * Copyright 1996,1997,1998 Russell King.
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <asm/unwind.h>
+#include "entry-header.S"
+
+	.text
+
+@ This is needed for usr_entry/alignment_trap
+.LCcralign:
+	.long	cr_alignment
+.LCdohandle:
+	.long	kgdb_fiq_do_handle
+
+	.macro	fiq_handler
+	ldr	r1, =.LCdohandle
+	mov	r0, sp
+	adr	lr, BSYM(9997f)
+	ldr	pc, [r1]
+9997:
+	.endm
+
+	.align	5
+__fiq_svc:
+	svc_entry
+	fiq_handler
+	mov	r0, sp
+	ldmib	r0, {r1 - r14}
+	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	add	r8, r0, #S_PC
+	ldr	r9, [r0, #S_PSR]
+	msr	spsr_cxsf, r9
+	ldr	r0, [r0, #S_R0]
+	ldmia	r8, {pc}^
+
+ UNWIND(.fnend		)
+ENDPROC(__fiq_svc)
+	.ltorg
+
+	.align	5
+__fiq_usr:
+	usr_entry
+	kuser_cmpxchg_check
+	fiq_handler
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user_from_irq
+ UNWIND(.fnend		)
+ENDPROC(__fiq_usr)
+	.ltorg
+
+	.global kgdb_fiq_handler
+kgdb_fiq_handler:
+
+	vector_stub	fiq, FIQ_MODE, 4
+
+	.long	__fiq_usr			@  0  (USR_26 / USR_32)
+	.long	__fiq_svc			@  1  (FIQ_26 / FIQ_32)
+	.long	__fiq_svc			@  2  (IRQ_26 / IRQ_32)
+	.long	__fiq_svc			@  3  (SVC_26 / SVC_32)
+	.long	__fiq_svc			@  4
+	.long	__fiq_svc			@  5
+	.long	__fiq_svc			@  6
+	.long	__fiq_svc			@  7
+	.long	__fiq_svc			@  8
+	.long	__fiq_svc			@  9
+	.long	__fiq_svc			@  a
+	.long	__fiq_svc			@  b
+	.long	__fiq_svc			@  c
+	.long	__fiq_svc			@  d
+	.long	__fiq_svc			@  e
+	.long	__fiq_svc			@  f
+
+	.global kgdb_fiq_handler_end
+kgdb_fiq_handler_end:
-- 
1.8.1.2



From john.stultz at linaro.org  Thu May  9 20:10:51 2013
From: john.stultz at linaro.org (John Stultz)
Date: Thu,  9 May 2013 17:10:51 -0700
Subject: [PATCH 3/3] ARM: versatile: Make able to use UART ports for KGDB FIQ
 debugger
In-Reply-To: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
References: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
Message-ID: <1368144651-11250-4-git-send-email-john.stultz@linaro.org>

From: Anton Vorontsov <anton.vorontsov at linaro.org>

If enabled, kernel will able to enter KGDB upon serial line activity on
UART ports.

Note that even with this patch and CONFIG_KGDB_FIQ is enabled, you still
need to pass kgdb_fiq.enable=1 kernel command line option, otherwise UART
will behave in a normal way.

By default UART0 is used, but this can be changed via kgdb_fiq.uart_num
kernel command line option.

Cc: Anton Vorontsov <anton.vorontsov at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Wessel <jason.wessel at windriver.com>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: kernel-team at android.com
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
Signed-off-by: John Stultz <john.stultz at linaro.org>
---
 arch/arm/Kconfig                   |  1 +
 arch/arm/mach-versatile/Makefile   |  1 +
 arch/arm/mach-versatile/kgdb_fiq.c | 55 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 57 insertions(+)
 create mode 100644 arch/arm/mach-versatile/kgdb_fiq.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 66a9076..9909af3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -364,6 +364,7 @@ config ARCH_VERSATILE
 	select PLAT_VERSATILE_CLCD
 	select PLAT_VERSATILE_CLOCK
 	select VERSATILE_FPGA_IRQ
+	select ARCH_MIGHT_HAVE_KGDB_FIQ
 	help
 	  This enables support for ARM Ltd Versatile board.
 
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 81fa3fe..bfd761f 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_ARCH_VERSATILE_PB)		+= versatile_pb.o
 obj-$(CONFIG_MACH_VERSATILE_AB)		+= versatile_ab.o
 obj-$(CONFIG_MACH_VERSATILE_DT)		+= versatile_dt.o
 obj-$(CONFIG_PCI)			+= pci.o
+obj-$(CONFIG_KGDB_FIQ)			+= kgdb_fiq.o
diff --git a/arch/arm/mach-versatile/kgdb_fiq.c b/arch/arm/mach-versatile/kgdb_fiq.c
new file mode 100644
index 0000000..dd92e40
--- /dev/null
+++ b/arch/arm/mach-versatile/kgdb_fiq.c
@@ -0,0 +1,55 @@
+/*
+ * KGDB FIQ board support
+ *
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kgdb.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <asm/hardware/vic.h>
+
+static void *kgdb_irq_base;
+
+static int kgdb_irq;
+module_param_named(uart_num, kgdb_irq, int, 0600);
+MODULE_PARM_DESC(uart_num, "UART<number> port to use for KGDB FIQ");
+
+static void kgdb_fiq_select(bool on)
+{
+	void __iomem *sel = kgdb_irq_base + VIC_INT_SELECT;
+	u32 msk = 1 << kgdb_irq;
+	u32 val;
+
+	pr_debug("rerouting VIC vector %d to %s\n", kgdb_irq,
+		 on ? "FIQ" : "IRQ");
+
+	val = readl(sel);
+	val &= ~msk;
+	if (on)
+		val |= msk;
+	writel(val, sel);
+}
+
+static bool kgdb_is_fiq_rised(void)
+{
+	return readl(kgdb_irq_base + VIC_FIQ_STATUS) & (1 << kgdb_irq);
+}
+
+static int __init kgdb_fiq_init(void)
+{
+	kgdb_irq_base = __io_address(VERSATILE_VIC_BASE);
+	kgdb_irq += INT_UARTINT0;
+	WARN_ON(kgdb_irq > INT_UARTINT2);
+
+	return kgdb_register_fiq(kgdb_fiq_select, kgdb_is_fiq_rised);
+}
+console_initcall(kgdb_fiq_init);
-- 
1.8.1.2



From tomasz.figa at gmail.com  Thu May  9 20:21:19 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 10 May 2013 02:21:19 +0200
Subject: [PATCH V2 1/3] clk: samsung: register audio subsystem clocks
 using common clock framework
In-Reply-To: <1367909016-19657-2-git-send-email-padma.v@samsung.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
 <1367909016-19657-2-git-send-email-padma.v@samsung.com>
Message-ID: <1730722.Al2EYiRntt@flatron>

Hi Padmavathi,

I managed to review the patch a bit more thoroughly and I had few more 
comments. You can find them inline.

On Tuesday 07 of May 2013 12:13:34 Padmavathi Venna wrote:
> Audio subsystem is introduced in s5pv210 and exynos platforms.
> This has seperate clock controller which can control i2s0 and
> pcm0 clocks. This patch registers the audio subsystem clocks
> with the common clock framework.
> 
> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
> ---
>  .../bindings/clock/clk-samsung-audss.txt           |   64 +++++++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-samsung-audss.c            |  137
> ++++++++++++++++++++ include/dt-bindings/clk/samsung-audss-clk.h       
> |   25 ++++ 4 files changed, 227 insertions(+), 0 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/clock/clk-samsung-audss.txt create
> mode 100644 drivers/clk/samsung/clk-samsung-audss.c
>  create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
> b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt new
> file mode 100644
> index 0000000..ec2cd0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
> @@ -0,0 +1,64 @@
> +* Samsung Audio Subsystem Clock Controller
> +
> +The Samsung Audio Subsystem clock controller generates and supplies
> clocks +to Audio Subsystem block available in the S5PV210 and Exynos
> SoCs. The clock +binding described here is applicable to all SoC's in
> the S5PV210 and Exynos +family.
> +
> +Required Properties:
> +
> +- compatible: should be one of the following:
> +  - "samsung,s5pv210-audss-clock" - controller compatible with all
> S5PV210 SoCs. +  - "samsung,exynos4210-audss-clock" - controller
> compatible with all Exynos4 SoCs. +  - "samsung,exynos5250-audss-clock"
> - controller compatible with all Exynos5 SoCs. +
> +- reg: physical base address and length of the controller's register
> set. +
> +- #clock-cells: should be 1.
> +
> +The following is the list of clocks generated by the controller. Each
> clock is +assigned an identifier and client nodes use this identifier
> to specify the +clock which they consume. Some of the clocks are
> available only on a particular +Exynos4 SoC and this is specified where
> applicable.
> +
> +Provided clocks:
> +
> +Clock           ID      SoC (if specific)
> +-----------------------------------------------
> +
> +mout_audss      0
> +mout_i2s        1
> +dout_srp        2
> +dout_bus        3
> +dout_i2s        4
> +srp_clk         5
> +i2s_bus         6
> +sclk_i2s        7
> +pcm_bus         8
> +sclk_pcm        9
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +clock_audss: audss-clock-controller at 03810000 {
> +	compatible = "samsung,exynos5250-audss-clock";
> +	reg = <0x03810000 0x0C>;
> +	#clock-cells = <1>;
> +};
> +
> +Example 2: I2S controller node that consumes the clock generated by the
> clock +           controller. Refer to the standard clock bindings for
> information +           about 'clocks' and 'clock-names' property.
> +
> + i2s0: i2s at 03830000 {
> +		compatible = "samsung,i2s-v5";
> +		reg = <0x03830000 0x100>;
> +		dmas = <&pdma0 10
> +			&pdma0 9
> +			&pdma0 8>;
> +		dma-names = "tx", "rx", "tx-sec";
> +		clocks = <&clock_audss SAMSUNG_I2S_BUS>,
> +			<&clock_audss SAMSUNG_I2S_BUS>,
> +			<&clock_audss SAMSUNG_SCLK_I2S>;
> +		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
> +};
> +
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index b7c232e..5425fa8 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
>  obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
>  obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
>  obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
> +obj-$(CONFIG_PLAT_SAMSUNG)	+= clk-samsung-audss.o
> diff --git a/drivers/clk/samsung/clk-samsung-audss.c
> b/drivers/clk/samsung/clk-samsung-audss.c new file mode 100644
> index 0000000..97526b7
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-samsung-audss.c
> @@ -0,0 +1,137 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Padmavathi Venna <padma.v at samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as +
> * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Audio Subsystem Clock Controller.
> +*/
> +
> +#include <linux/clkdev.h>
> +#include <linux/io.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/syscore_ops.h>
> +
> +#include <dt-bindings/clk/samsung-audss-clk.h>
> +
> +static DEFINE_SPINLOCK(lock);
> +static struct clk **clk_table;
> +static void __iomem *reg_base;
> +static struct clk_onecell_data clk_data;
> +
> +#define ASS_CLK_SRC 0x0
> +#define ASS_CLK_DIV 0x4
> +#define ASS_CLK_GATE 0x8
> +
> +static unsigned long reg_save[][2] = {
> +	{ASS_CLK_SRC,  0},
> +	{ASS_CLK_DIV,  0},
> +	{ASS_CLK_GATE, 0},
> +};
> +
> +/* list of all parent clock list */
> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
> +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0",
> "sclk_audio0" }; +
> +#ifdef CONFIG_PM_SLEEP
> +static int samsung_audss_clk_suspend(void)
> +{
> +	int i;
> +
> +	for (i = 0; i < 3; i++)
> +		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
> +
> +	return 0;
> +}
> +
> +static void samsung_audss_clk_resume(void)
> +{
> +	int i;
> +
> +	for (i = 0; i < 3; i++)
> +		writel(reg_save[i][1], reg_base + reg_save[i][0]);
> +}
> +
> +static struct syscore_ops samsung_audss_clk_syscore_ops = {
> +	.suspend	= samsung_audss_clk_suspend,
> +	.resume		= samsung_audss_clk_resume,
> +};
> +#endif /* CONFIG_PM_SLEEP */
> +
> +/* register samsung_audss clocks */
> +void __init samsung_audss_clk_init(struct device_node *np)
> +{
> +	reg_base = of_iomap(np, 0);
> +	if (!reg_base) {
> +		pr_err("%s: failed to map audss registers\n", __func__);
> +		return;
> +	}
> +
> +	clk_table = kzalloc(sizeof(struct clk *) * SAMSUNG_AUDSS_MAX_CLKS,
> +				GFP_KERNEL);
> +	if (!clk_table) {
> +		pr_err("%s: could not allocate clock lookup table\n", 
__func__);
> +		return;
> +	}
> +
> +	clk_data.clks = clk_table;
> +	clk_data.clk_num = SAMSUNG_AUDSS_MAX_CLKS;
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +
> +	clk_table[SAMSUNG_MOUT_AUDSS] = clk_register_mux(NULL, 
"mout_audss",
> +				mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
> +				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
> +	clk_register_clkdev(clk_table[SAMSUNG_MOUT_AUDSS], "mout_audss",
> NULL); +

Is there are a reason for this clkdev lookup to be registered?

This driver seems to be used only in DT-case, so DT-based lookup should be 
enough.

> +	clk_table[SAMSUNG_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
> +				mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
> +				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
> +	clk_register_clkdev(clk_table[SAMSUNG_MOUT_I2S], "mout_i2s", 
NULL);

Same here.

> +
> +	clk_table[SAMSUNG_DOUT_SRP] = clk_register_divider(NULL, 
"dout_srp",
> +				"mout_audss", 0, reg_base + ASS_CLK_DIV, 
0, 4,
> +				0, &lock);
> +
> +	clk_table[SAMSUNG_DOUT_BUS] = clk_register_divider(NULL, 
"dout_bus",
> +				"dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 
4, 0,
> +				&lock);
> +
> +	clk_table[SAMSUNG_DOUT_I2S] = clk_register_divider(NULL, 
"dout_i2s",
> +				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 
4, 0,
> +				&lock);
> +
> +	clk_table[SAMSUNG_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
> +				"dout_srp", CLK_SET_RATE_PARENT,
> +				reg_base + ASS_CLK_GATE, 0, 0, &lock);
> +
> +	clk_table[SAMSUNG_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
> +				"dout_bus", CLK_SET_RATE_PARENT,
> +				reg_base + ASS_CLK_GATE, 2, 0, &lock);
> +
> +	clk_table[SAMSUNG_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
> +				"dout_i2s", CLK_SET_RATE_PARENT,
> +				reg_base + ASS_CLK_GATE, 3, 0, &lock);
> +
> +	clk_table[SAMSUNG_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
> +				 "sclk_pcm", CLK_SET_RATE_PARENT,
> +				reg_base + ASS_CLK_GATE, 4, 0, &lock);
> +
> +	clk_table[SAMSUNG_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
> +				"div_pcm0", CLK_SET_RATE_PARENT,
> +				reg_base + ASS_CLK_GATE, 5, 0, &lock);
> +
> +#ifdef CONFIG_PM_SLEEP
> +	register_syscore_ops(&samsung_audss_clk_syscore_ops);
> +#endif
> +
> +	pr_info("Exynos: Audss: clock setup completed\n");
> +}
> +CLK_OF_DECLARE(s5pv210_audss_clk, "samsung,s5pv210-audss-clock",
> +		samsung_audss_clk_init);

I'm wondering if this driver in its current state is really compatible 
with S5PV210. Quick look at documentation shows that CLK_GATE and CLK_DIV 
registers on this SoC have different layout than on Exynos SoCs.

I guess that for now the best choice would be to remove any mentions about 
S5PV210 from the patch and add them back after the driver gets proper 
support for this SoC.

> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
> +		samsung_audss_clk_init);
> +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
> +		samsung_audss_clk_init);

Also if both Exynos4210 and Exynos5250 have exactly the same audss clock 
layout, there is no reason to have two compatibles for them - the 
convention is that just the first model that had this hardware is enough - 
in this case Exynos4210.

Having two different compatibles suggests that those two SoCs differ in a 
way that needs special handling, which is misleading, based on the fact 
that there is no such special handling in the driver.

Best regards,
Tomasz



From s-anna at ti.com  Thu May  9 20:18:49 2013
From: s-anna at ti.com (Suman Anna)
Date: Thu, 9 May 2013 19:18:49 -0500
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <CAJe_ZheEZo7Akri40ixBhWzeefABxiJXG1Juc4zQOPNQqyahUw@mail.gmail.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
 <518976B9.2030605@ti.com>
 <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>
 <518AFB1F.7010409@ti.com>
 <CAJe_ZheEZo7Akri40ixBhWzeefABxiJXG1Juc4zQOPNQqyahUw@mail.gmail.com>
Message-ID: <518C3CE9.1010603@ti.com>

Hi Jassi,
>
> On 9 May 2013 06:55, Suman Anna <s-anna at ti.com> wrote:
> 
>>> so it can't be driven by the controller. We could make it a Kconfig option.
>>> What do you suggest?
>>
>> I am saying controller/link because they are the ones that knows how the
>> physical transport is, and it may vary from one to another. I would
>> think that the client dependencies would become a subset of this.
>> Kconfig option is fine, but we have to think about the best way of
>> representing it from a multi-platform kernel support perspective.
>>
> Actually it has more to do with clients and less with multiplatform.
> Even on single platform the client that needs biggest buffer will
> rule. Ditto on multi-platform.
> Anyways I get your idea. I'll put a note there to revisit once number
> of active clients increase on the platform.

OK thanks.

>>>> IMHO. It's calling ipc_links_register twice on the same controller. Idea
>>>> was that the API would distinguish different controllers, not the same
>>>> one. Also, see the above example if you were to treat a link as Rx or Tx
>>>> only (functional behavior differences even though the link is exactly
>>>> the same type).
>>>>
>>> Why is calling ipc_links_register() twice, for a controller with 2
>>> classes of links, a problem ?
>>
>> It will be inelegant, once you start maintaining the list of
>> ipc_controllers in the core code. You would have to search all the
>> controllers in the list with the matching name, and their links. You
>> will need to define multiple controller specific controller structures
>> and copy most of the elements from the actual h/w device into the
>> containing ipc_controller definition. As you said, the clients deal with
>> the links themselves, so making the ops part of the ipc_link definition
>> makes it easier on the controller implementations. You are anyway
>> caching the ops in ipc_chan (per link) and that is what you are using in
>> the core code. Majority of the time, you would be using the same ops for
>> all the links, but this gives the flexibility to links. You can avoid
>> having multiple controller instance denoting the h/w block, just because
>> of the difference in links behavior.
>>
> I don't see it as an issue, it's just how the code is designed on the
> principle that the API works only on links, not controllers. Let us
> wait for the driver of such a controller to show up. It should be easy
> to change if we see the need.

OK fine, I brought it up since we are defining the API, and defining it
the first time with flexibility eliminates the need later on.

> 
>>>
>>> And, No, the API need not know if the link is "RX" or "TX", which is
>>> purely a logical function.
>>>
>>> Please do tell me which controller physically limits its links to do
>>> only "RX" or only "TX"?  It's just the platform's firmware that
>>> dictates who sends and who receives on which link, thereby giving the
>>> illusion of a link being a "RX" or "TX" capable only.
>>> Even if some h/w limits do exist on links of some controller, still
>>> the API shouldn't try to discern a "RX" from a "TX" link. When a
>>> client knows which link to open, it will also know if it should read
>>> or write to it - this assumption already holds true. If the client
>>> writes on a link that it's supposed to listen to remote on, no amount
>>> of policing by the API could help.
>>>
>>> Even if the API tries to differentiate "RX" and "TX" links, the
>>> knowledge must come from a client (it's driven by the protocol on the
>>> platform), and not the controller because each of its links are
>>> physically equally capable to do RX or TX on each end.
>>
>> The API never differentiates, but the controller implementation has to.
>> From a controller driver implementation perspective, you still have to
>> make sure that no client is calling an op on which it is not supposed
>> to. When you have a mixture like this, a common code would include some
>> dead paths for certain links.
>>
> No, please. The controller driver should not implement any policy (of
> allowing/disallowing requests). It should simply try to do as
> directed. If the client screwed up even after getting info from
> platform_data/DT, let it suffer.

This would be the same as a client trying to misconfigure a link, you
cannot blame on a client screw up. The controller driver has to take
care of what it ought to check for in the startup.

> 
>>>>> Yes, I have 2 types of controllers and I already thought about
>>>>> multiple controllers in a platform.
>>>>>  What do you expect to do in controller startup/shutdown? Since the
>>>>> API works on individual links, not the controllers, when would it call
>>>>> controller_start() and controller_shutdown()?  The ipc_link's
>>>>> startup/shutdown are already non-atomic, if the controller needs any
>>>>> setup it could do it in the first link's startup and teardown in the
>>>>> last link's shutdown. Not to forget the resources lke IRQ are usually
>>>>> per Link which should be acquired/released upon link's use/idle.
>>>>>  While writing the OMAP2 controller driver, did I miss any controller
>>>>> startup/shutdown ?
>>>>
>>>> It just delineates the code better, and has flexibility later on to
>>>> extend any controller ops or exposing new controller-specific API. The
>>>> controller start and stop will be called in the same function as
>>>> ipc_request_channel.
>>>>
>>> Already one call ipc_link_ops.startup() reaches the controller upon
>>> ipc_request_channel.
>>>
>>> Do you mean ?
>>>        ipc_con_ops.startup();
>>>        ipc_link_ops.startup();
>>
>> Yes.
>>
> And let the controller startup()/shutdown() upon every
> link_request/release? 

Yes, and the controller driver can take care of any ref-counting or
whatever other logic it needs to maintain. You see this outside in the
previous mailbox code, but that is not the responsibility of the core code.

> 
> BTW, I have seen my 2 controllers, OMAP, PL320 and read the dbx500
> driver. Unsurprisingly none of these have any use for what you call a
> special ipc_con_ops.startup().  Lets say if the call were there, what
> would the OMAP put in it?

Enabling the clock for the device. The clock is for the entire IP, a
link has no power/clock dependencies.

> 
>>>> Yeah, the pm_runtime_enable cannot be called twice when mailbox is
>>>> invoked from multiple clients on separate links, so there has to a
>>>> controller-level logic/ref-counting for that. The clocking for us is on
>>>> the controller.
>>>>
>>> No.  You could call pm_runtime_enable/disable any number of times as
>>> long as they are balanced. The core does refcounting.
>>
>> Exactly, as long as they are balanced. I have two clients dealing with
>> two remotes (using two links) so pm_runtime_enable on the h/w block
>> needs to be called only when the first one comes in.
>>
> Actually you just gave another reason why the API messing around with
> controller's power state is a bad idea.

Where do you expect to power up the device (obviously this depends on
the SoC, and its functional purpose)?

> See how mailbox_startup() tries to balance mbox->ops->startup() and
> mailbox_fini() the mbox->ops->shutdown()  That's very fragile and the
> cause of imbalance between rpm enable/disable, unless your clients are
> buggy.

Yeah, it is kinda messed up in the existing code, the startup defined
there is really for the controller and not the link, and that's why you
see all the ref-counting balancing logic. The rpm enable/disable being
called is on the controller's dev, not the link's dev - maybe that's
what confused you.

regards
Suman



From tomasz.figa at gmail.com  Thu May  9 20:24:38 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 10 May 2013 02:24:38 +0200
Subject: [PATCH V2 0/3] clk: Samsung: audss: Register audio subsytem
 clocks using common clk framework
In-Reply-To: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
Message-ID: <1561518.UR9S1ZDj1n@flatron>

Hi Padmavathi,

On Tuesday 07 of May 2013 12:13:33 Padmavathi Venna wrote:
> Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This
> subsystem has a internal clock controller which controls i2s0 and pcm0
> clocks. This patch series adds the Samsung audio subsytem clock to the
> common clock framework and provides the I2S controllers clock
> information in the dtsi file.
> 
> This patch series is dependent on
> https://patchwork.kernel.org/patch/2532091/
> http://www.spinics.net/lists/linux-kbuild/msg07616.html
> 
> This patch series is made based on Kukjin Kim for-next branch
> 
> Changes since V1:
> 	- Reworked on all review comments by Sylwester Nawrocki
> 	- Added a header file for all clock indexes as requested by 
Sylwester
> 	- Added different compatible names for s5pv210, exynos4 and 
exynos5
> 	- Registered the pcm clocks with common clock framework
> 
> Padmavathi Venna (3):
>   clk: samsung: register audio subsystem clocks using common clock
>     framework
>   ARM: dts: add Exynos audio subsystem clock controller node
>   ARM: dts: add clock provider information for i2s controllers in
>     Exynos5250
> 
>  .../bindings/clock/clk-samsung-audss.txt           |   64 +++++++++
>  arch/arm/boot/dts/exynos5250.dtsi                  |   16 +++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-samsung-audss.c            |  137
> ++++++++++++++++++++ include/dt-bindings/clk/samsung-audss-clk.h       
> |   25 ++++ 5 files changed, 243 insertions(+), 0 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/clock/clk-samsung-audss.txt create
> mode 100644 drivers/clk/samsung/clk-samsung-audss.c
>  create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h

Also, I think that this series lacks

Cc: Mike Turquette <mturquette at linaro.org>

as he's the maintainer of the clk subsystem.

Best regards,
Tomasz



From kgene.kim at samsung.com  Thu May  9 20:31:11 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 May 2013 09:31:11 +0900
Subject: [GIT PULL] Late Exynos stuff for v3.10
In-Reply-To: <CAOesGMjA5_XUXMcCL3roZiLC1S=ypMoVHn2tF7bzUuKr+eLw2A@mail.gmail.com>
References: <5176B499.1000208@samsung.com> <51770697.7080504@samsung.com>
 <20130424000638.GA9067@quad.lixom.net> <51794E10.1010205@samsung.com>
 <CAOesGMjA5_XUXMcCL3roZiLC1S=ypMoVHn2tF7bzUuKr+eLw2A@mail.gmail.com>
Message-ID: <046301ce4d15$ac1592b0$0440b810$%kim@samsung.com>

Olof Johansson wrote:
> 
> Kukjin,
> 
Hi Olof,

[...]

> > And let me send pull-request again for fix and late dt branch with
> separated
> > branches in a couple of hours not including usb stuff...
> 
> Refresh my memory here, what was the reason for dropping the USB DTS
> updates? (Yes, I am aware it might because I asked you not to send
> them in but I don't remember :-).
> 
Hmm...let me see, yeah, the USB DTS updates dropped because of late
pull-request stuff as you concerned.
http://www.spinics.net/lists/arm-kernel/msg240105.html

Since I didn't want to make a noise at that time, so I dropped for v3.10, it
has been included in my tree for some time though.

> Also, when you drop stuff, please, please don't keep it in your own

Ooops, it's my mistake. I didn't updated my tree not in my local :-(

> for-next branch. The end result is that we'll keep testing something
> on linux-next with the anticipation that it will work when it lands in
> the merge window, when that's not the truth if you're not going to
> send the pull requests up.
> 
> So, if you decide to keep code like this out of the merge window (or
> if we push back at it and say no to it), then remove it from your
> for-next branch as well.
> 
Perfectly right and I agree.

> In particular, the usb phy node for usb2 would ber very good to get in
> for 3.10, since it's a critical piece to get usb2 working on the
> Chromebook.
> 
Yes, I think so, let me sort them out.

Thanks.

- Kukjin



From kgene.kim at samsung.com  Thu May  9 20:32:05 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 May 2013 09:32:05 +0900
Subject: [PATCH v5] pinctrl: Add pinctrl-s3c24xx driver
In-Reply-To: <201305031552.45410.heiko@sntech.de>
References: <201305031552.45410.heiko@sntech.de>
Message-ID: <046401ce4d15$ccba0c80$662e2580$%kim@samsung.com>

Heiko St?bner wrote:
> 
> The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
> can therefore reuse the already introduced infrastructure.
> 
> The s3c24xx SoCs have one design oddity in that the first 4 external
> interrupts do not reside in the eint pending register but in the main
> interrupt controller instead. We solve this by forwarding the external
> interrupt from the main controller into the irq domain of the pin bank.
> The masking/acking of these interrupts is handled in the same way.
> 
> Furthermore the S3C2412/2413 SoCs contain another oddity in that they
> keep the same 4 eints in the main interrupt controller and eintpend
> register and requiring ack operations to happen in both. This is solved
> by using different compatible properties for the wakeup eint node which
> set a property accordingly.
> 
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> Reviewed-by: Tomasz Figa <t.figa at samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Looks good to me.

Linus, if you want me to take into samsung tree, please let me know.

Thanks.

- Kukjin

> ---
> changes since v4:
> - fix wrong s3c2413 naming
>   between s3c2412 and s3c2413, the s3c2412 is the base type. Till v4 the
>   naming was mixed up, with parts being labeled as s3c2412* and others
>   as s3c2413*. Fix this by renaming the s3c2413* parts to s3c2412.
>   No functional changes.
> 
> changes since v3:
> - address comments from Sylwester Nawrocki:
>   (typos, wrong comments, etc)
> 
> changes since v2:
> - address more comments from Tomasz Figa:
>   * remove obsolete ctrl_type references
>   * remove redundant check for parent_chip
>   * update docs and commit message
> 
> changes since v1:
> - address comments from Tomasz Figa:
>   * split handling functions for eints 0-3 for s3c2412 and all others
>   * change the handling for s3c2412 eints 0-3 in that they now use
>     chained_irq_* for the outer parent interrupt
> 
>  .../bindings/pinctrl/samsung-pinctrl.txt           |    8 +
>  drivers/gpio/gpio-samsung.c                        |    4 +
>  drivers/pinctrl/Kconfig                            |    5 +
>  drivers/pinctrl/Makefile                           |    1 +
>  drivers/pinctrl/pinctrl-s3c24xx.c                  |  652 ++++++++++++++++++++
>  drivers/pinctrl/pinctrl-samsung.c                  |   10 +
>  drivers/pinctrl/pinctrl-samsung.h                  |    4 +
>  7 files changed, 684 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/pinctrl/pinctrl-s3c24xx.c
> 
[...]



From swarren at wwwdotorg.org  Thu May  9 22:54:33 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 09 May 2013 20:54:33 -0600
Subject: [PATCH 0/2] ARM: tegra: a couple clock bug-fixes
In-Reply-To: <20130509235533.GA19697@quad.lixom.net>
References: <1367874671-11474-1-git-send-email-swarren@wwwdotorg.org>
 <20130509235533.GA19697@quad.lixom.net>
Message-ID: <518C6169.5050709@wwwdotorg.org>

On 05/09/2013 05:55 PM, Olof Johansson wrote:
> On Mon, May 06, 2013 at 03:11:09PM -0600, Stephen Warren wrote:
>> From: Stephen Warren <swarren at nvidia.com>
>>
>> Arnd, Olof,
>>
>> The following two patches fix a couple issues in the Tegra20 clock driver
>> that show up on specific platforms. They were sent a little late for 3.9,
>> and I forgot to include them for 3.10 since they weren't reposted:-(
> 
> Applied to fixes now, sorry for missing them earlier.

Great, thanks. Just to be clear; it was me who missed picking them up; I
don't think they'd been forwarded to you before with all the acks in place.



From elen.song at atmel.com  Thu May  9 22:59:58 2013
From: elen.song at atmel.com (Elen Song)
Date: Fri, 10 May 2013 10:59:58 +0800
Subject: [PATCH 0/2 V4] DMA: AT91: Fix get residue function in at_hdmac.c 
Message-ID: <1368154798-9279-1-git-send-email-elen.song@atmel.com>

The residue actually means the bytes remain in transfer identified by current cookie.
The get residue api did not return the correct values in at_hdmac.c.
This patch serial focus on fix the issue.

This patch serials is based on DMA: AT91: Get residual bytes in dma buffer v2.
It is split into 3 aimed patch, the first one is to get transmit buswidth,
the second one is to get resiude in cookie, it use the buswidth to get residual bytes,
the third part is to handle the status that there are still some bytes remain in dma fifo.

Compare to v2, this patch serials improve:
1) consider buswidth to get correct residue.
2) handle dma fifo empty status.

Compare to v3, this patch serials improve:
1) To state clearly, replace buswidth with transfer width.
2) Do not pause dma when get residue.
3) Let issue pending handler remain work if data remain in dma fifo, polling empty flag is too time consuming.

Elen Song (2):
  DMA: AT91: Get transfer width
  DMA: AT91: Get residual bytes in dma buffer

 drivers/dma/at_hdmac.c      |  151 ++++++++++++++++++++++++++++++++++++++-----
 drivers/dma/at_hdmac_regs.h |    5 ++
 2 files changed, 139 insertions(+), 17 deletions(-)

-- 
1.7.9.5



From elen.song at atmel.com  Thu May  9 23:00:50 2013
From: elen.song at atmel.com (Elen Song)
Date: Fri, 10 May 2013 11:00:50 +0800
Subject: [PATCH 1/2 V4] DMA: AT91: Get transfer width
Message-ID: <1368154850-9354-1-git-send-email-elen.song@atmel.com>

In one dma transfer, the data transfer width can be configured and it is limited by source or destination peripheral width,
tx_width will save the transfer width, but for memcpy, either source or destination transfer width is taken as tx_width.

Signed-off-by: Elen Song <elen.song at atmel.com>
---
 drivers/dma/at_hdmac.c      |    3 +++
 drivers/dma/at_hdmac_regs.h |    2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 6e13f26..a4d427e 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -613,6 +613,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->len = len;
+	first->tx_width = src_width;
 
 	/* set end-of-link to the last link descriptor of list*/
 	set_desc_eol(desc);
@@ -759,6 +760,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->len = total_len;
+	first->tx_width = reg_width;
 
 	/* first link descriptor of list is responsible of flags */
 	first->txd.flags = flags; /* client is in control of this ack */
@@ -917,6 +919,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->len = buf_len;
+	first->tx_width = reg_width;
 
 	return &first->txd;
 
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index 0eb3c13..d27942f 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -182,6 +182,7 @@ struct at_lli {
  * @txd: support for the async_tx api
  * @desc_node: node on the channed descriptors list
  * @len: total transaction bytecount
+ * @tx_width: transfer width
  */
 struct at_desc {
 	/* FIRST values the hardware uses */
@@ -192,6 +193,7 @@ struct at_desc {
 	struct dma_async_tx_descriptor	txd;
 	struct list_head		desc_node;
 	size_t				len;
+	u32				tx_width;
 };
 
 static inline struct at_desc *
-- 
1.7.9.5



From elen.song at atmel.com  Thu May  9 23:01:46 2013
From: elen.song at atmel.com (Elen Song)
Date: Fri, 10 May 2013 11:01:46 +0800
Subject: [PATCH 2/2 V4] DMA: AT91: Get residual bytes in dma buffer
Message-ID: <1368154906-9450-1-git-send-email-elen.song@atmel.com>

Add support for returning the residue for current transfer cookie by
reading the transfered buffer size(BTSIZE) in CTRLA register.

For a single buffer cookie, the descriptor length minus BTSIZE
can get the residue.

For a lli cookie, remain_desc will record remain descriptor length
when last descriptor finish, the remain_desc minus BTSIZE can get the
current residue.

If the cookie has completed successfully, the residue will be zero.
If the cookie is in progress, it will be the number of bytes yet to be transferred.
If get residue error, the cookie will be turn into error status.

Check dma fifo to see if data remain, let issue pending finish remain work if there is.
Signed-off-by: Elen Song <elen.song at atmel.com>
---
 drivers/dma/at_hdmac.c      |  130 +++++++++++++++++++++++++++++++++++++------
 drivers/dma/at_hdmac_regs.h |    3 +
 2 files changed, 115 insertions(+), 18 deletions(-)

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index a4d427e..cd68f8e 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -53,6 +53,7 @@ MODULE_PARM_DESC(init_nr_desc_per_channel,
 
 /* prototypes */
 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
+static void atc_issue_pending(struct dma_chan *chan);
 
 
 /*----------------------------------------------------------------------*/
@@ -229,6 +230,94 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
 	vdbg_dump_regs(atchan);
 }
 
+/*
+ * atc_get_current_descriptors -
+ * locate the descriptor which equal to physical address in DSCR
+ * @atchan: the channel we want to start
+ * @dscr_addr: physical descriptor address in DSCR
+ */
+static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan,
+							u32 dscr_addr)
+{
+	struct at_desc  *desc, *_desc, *child, *desc_cur = NULL;
+
+	list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
+		if (desc->lli.dscr == dscr_addr) {
+			desc_cur = desc;
+			break;
+		}
+
+		list_for_each_entry(child, &desc->tx_list, desc_node) {
+			if (child->lli.dscr == dscr_addr) {
+				desc_cur = child;
+				break;
+			}
+		}
+	}
+
+	return desc_cur;
+}
+
+/*
+ * atc_get_bytes_left -
+ * Get the number of bytes residue in dma buffer,
+ * @chan: the channel we want to start
+ */
+static int atc_get_bytes_left(struct dma_chan *chan)
+{
+	struct at_dma_chan      *atchan = to_at_dma_chan(chan);
+	struct at_dma           *atdma = to_at_dma(chan->device);
+	int	chan_id = atchan->chan_common.chan_id;
+	struct at_desc *desc_first = atc_first_active(atchan);
+	struct at_desc *desc_cur;
+	int ret = 0, count = 0;
+
+	/*
+	 * Initialize necessary values in the first time.
+	 * remain_desc record remain desc length.
+	 */
+	if (atchan->remain_desc == 0)
+		/* First descriptor embedds the transaction length */
+		atchan->remain_desc = desc_first->len;
+
+	/*
+	 * This happens when current descriptor transfer complete.
+	 * The residual buffer size should reduce current descriptor length.
+	 */
+	if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) {
+		clear_bit(ATC_IS_BTC, &atchan->status);
+		desc_cur = atc_get_current_descriptors(atchan,
+						channel_readl(atchan, DSCR));
+		if (!desc_cur) {
+			ret = -EINVAL;
+			goto out;
+		}
+		atchan->remain_desc -= (desc_cur->lli.ctrla & ATC_BTSIZE_MAX)
+						<< (desc_first->tx_width);
+		if (atchan->remain_desc < 0) {
+			ret = -EINVAL;
+			goto out;
+		} else
+			ret = atchan->remain_desc;
+	} else {
+		/*
+		 * Get residual bytes when current
+		 * descriptor transfer in progress.
+		 */
+		count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX)
+				<< (desc_first->tx_width);
+		ret = atchan->remain_desc - count;
+	}
+	/*
+	 * Check fifo empty.
+	 */
+	if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id)))
+		atc_issue_pending(chan);
+
+out:
+	return ret;
+}
+
 /**
  * atc_chain_complete - finish work for one transaction chain
  * @atchan: channel we work on
@@ -494,6 +583,8 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
 					/* Give information to tasklet */
 					set_bit(ATC_IS_ERROR, &atchan->status);
 				}
+				if (pending & AT_DMA_BTC(i))
+					set_bit(ATC_IS_BTC, &atchan->status);
 				tasklet_schedule(&atchan->tasklet);
 				ret = IRQ_HANDLED;
 			}
@@ -1033,34 +1124,35 @@ atc_tx_status(struct dma_chan *chan,
 		struct dma_tx_state *txstate)
 {
 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
 	unsigned long		flags;
 	enum dma_status		ret;
-
-	spin_lock_irqsave(&atchan->lock, flags);
+	int bytes = 0;
 
 	ret = dma_cookie_status(chan, cookie, txstate);
-	if (ret != DMA_SUCCESS) {
-		atc_cleanup_descriptors(atchan);
+	if (ret == DMA_SUCCESS)
+		return ret;
+	/*
+	 * There's no point calculating the residue if there's
+	 * no txstate to store the value.
+	 */
+	if (!txstate)
+		return DMA_ERROR;
 
-		ret = dma_cookie_status(chan, cookie, txstate);
-	}
+	spin_lock_irqsave(&atchan->lock, flags);
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
+	/*  Get number of bytes left in the active transactions */
+	bytes = atc_get_bytes_left(chan);
 
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
-	if (ret != DMA_SUCCESS)
-		dma_set_residue(txstate, atc_first_active(atchan)->len);
-
-	if (atc_chan_is_paused(atchan))
-		ret = DMA_PAUSED;
+	if (unlikely(bytes < 0)) {
+		dev_vdbg(chan2dev(chan), "get residual bytes error\n");
+		return DMA_ERROR;
+	} else
+		dma_set_residue(txstate, bytes);
 
-	dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n",
-		 ret, cookie, last_complete ? last_complete : 0,
-		 last_used ? last_used : 0);
+	dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
+		 ret, cookie, bytes);
 
 	return ret;
 }
@@ -1146,6 +1238,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&atchan->lock, flags);
 	atchan->descs_allocated = i;
+	atchan->remain_desc = 0;
 	list_splice(&tmp_list, &atchan->free_list);
 	dma_cookie_init(chan);
 	spin_unlock_irqrestore(&atchan->lock, flags);
@@ -1188,6 +1281,7 @@ static void atc_free_chan_resources(struct dma_chan *chan)
 	list_splice_init(&atchan->free_list, &list);
 	atchan->descs_allocated = 0;
 	atchan->status = 0;
+	atchan->remain_desc = 0;
 
 	dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
 }
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index d27942f..443d62b 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -213,6 +213,7 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd)
 enum atc_status {
 	ATC_IS_ERROR = 0,
 	ATC_IS_PAUSED = 1,
+	ATC_IS_BTC = 2,
 	ATC_IS_CYCLIC = 24,
 };
 
@@ -228,6 +229,7 @@ enum atc_status {
  * @save_cfg: configuration register that is saved on suspend/resume cycle
  * @save_dscr: for cyclic operations, preserve next descriptor address in
  *             the cyclic list on suspend/resume cycle
+ * @remain_desc: to save remain desc length
  * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
  * @lock: serializes enqueue/dequeue operations to descriptors lists
  * @active_list: list of descriptors dmaengine is being running on
@@ -244,6 +246,7 @@ struct at_dma_chan {
 	struct tasklet_struct	tasklet;
 	u32			save_cfg;
 	u32			save_dscr;
+	u32			remain_desc;
 	struct dma_slave_config dma_sconfig;
 
 	spinlock_t		lock;
-- 
1.7.9.5



From sachin.kamat at linaro.org  Fri May 10 02:15:26 2013
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Fri, 10 May 2013 11:45:26 +0530
Subject: [PATCH 1/1] ARM: mcpm: Fix build error with gic_secondary_init call
Message-ID: <1368166526-12525-1-git-send-email-sachin.kamat@linaro.org>

Commit c0114709ed ("irqchip: gic: Perform the gic_secondary_init()
call via CPU notifier") removed all platform calls to gic_secondary_init.
Since this file got merged after the removal of the above call, this
function got left out in the current file which is causing the following
build error:
arch/arm/common/mcpm_platsmp.c:52:2: error: implicit declaration of function
?gic_secondary_init? [-Werror=implicit-function-declaration]
gic_secondary_init(0);

Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Nicolas Pitre <nico at linaro.org>
---
Compile tested only.
---
 arch/arm/common/mcpm_platsmp.c |    3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
index 52b88d8..3caed0d 100644
--- a/arch/arm/common/mcpm_platsmp.c
+++ b/arch/arm/common/mcpm_platsmp.c
@@ -15,8 +15,6 @@
 #include <linux/smp.h>
 #include <linux/spinlock.h>
 
-#include <linux/irqchip/arm-gic.h>
-
 #include <asm/mcpm.h>
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
@@ -49,7 +47,6 @@ static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *i
 static void __cpuinit mcpm_secondary_init(unsigned int cpu)
 {
 	mcpm_cpu_powered_up();
-	gic_secondary_init(0);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-- 
1.7.9.5



From tushar.behera at linaro.org  Fri May 10 02:47:35 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 10 May 2013 12:17:35 +0530
Subject: [PATCH] ARM: dts: add max8997 device node for exynos4210-origen
 board
In-Reply-To: <50EA598D.6090604@linaro.org>
References: <1353664412-17678-1-git-send-email-thomas.abraham@linaro.org>
 <50EA598D.6090604@linaro.org>
Message-ID: <518C9807.80906@linaro.org>

On 01/07/2013 10:43 AM, Tushar Behera wrote:
> On 11/23/2012 03:23 PM, Thomas Abraham wrote:
>> Add max8997 regulator device node for exynos4210-origen board and list
>> all the supported regulators.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> 
> Tested-by: Tushar Behera <tushar.behera at linaro.org>
> 
Kukjin,

This patch got missed for 3.10 merge window. This patch still applies on
the latest mainline kernel and is essential for Origen board. Would you
please take this patch?

-- 
Tushar Behera


From plagnioj at jcrosoft.com  Fri May 10 02:45:20 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 08:45:20 +0200
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred
 probing is done
In-Reply-To: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
Message-ID: <20130510064520.GI3041@game.jcrosoft.org>

On 11:35 Thu 09 May     , Saravana Kannan wrote:
> With deferred probing, late_initcall() is too soon to declare a clock as
> unused. Wait for deferred probing to finish before declaring a clock as
> unused. Since deferred probing is done in late_initcall(), do the unused
> check to late_initcall_sync.

Nack for both regulator & clk

you can not known when the clock need to be shutdown

example display splash screen set by the bootloader and display as module

Best Regards,
J.
> 
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> ---
>  drivers/clk/clk.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index fe4055f..5ecb64c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -534,7 +534,7 @@ static int clk_disable_unused(void)
>  
>  	return 0;
>  }
> -late_initcall(clk_disable_unused);
> +late_initcall_sync(clk_disable_unused);
>  
>  /***    helper functions   ***/
>  
> -- 
> 1.7.8.3
> 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From tushar.behera at linaro.org  Fri May 10 02:55:05 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 10 May 2013 12:25:05 +0530
Subject: [PATCH] ARM: exynos: defconfig update
In-Reply-To: <1368133099-16997-1-git-send-email-olof@lixom.net>
References: <1368133099-16997-1-git-send-email-olof@lixom.net>
Message-ID: <518C99C9.1000708@linaro.org>

On 05/10/2013 02:28 AM, Olof Johansson wrote:
> This turns on a number of configs that are useful on the Chromebook, but also
> good to have on in general:
> 
> * USB host and MMC drivers(!)
> * I2C GPIO arbitration driver
> * CYAPA trackpad driver
> * simplefb
> * CROS EC and keyboard drivers
> * MAX77686 drivers
> * DEVTMPFS + mount
> * DM_CRYPT (as module)
> * CRYPTOLOOP
> * HIGHMEM
> * PRINTK timestamps
> 
> This also turns off DEBUG_LL, and switches the hardcoded Samsung lowlevel
> uart to uart 3 (which is only used to show the "uncompressing kernel"
> message at boot, it seems).
> 

Setting the UART to 2, I tested this to work well with Arndale board.
Though, I would also like to enable S5M8767 driver (for Arndale board),
MAX8997 driver and MMC SDHCI driver (for Origen board). I will be
sending a patch to enable them.

> Signed-off-by: Olof Johansson <olof at lixom.net>
> Cc: Kukjin Kim <kgene.kim at samsung.com>

Tested-by: Tushar Behera <tushar.behera at linaro.org>

-- 
Tushar Behera


From tushar.behera at linaro.org  Fri May 10 02:49:59 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 10 May 2013 12:19:59 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
Message-ID: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>

It updates following drivers for EXYNOS based DT platform.

* S5M8767 driver
* MAX8997 driver
* MMC SDHCI driver

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---

This patch is based on Olof's following patch.
"[PATCH] ARM: exynos: defconfig update"
https://lkml.org/lkml/2013/5/9/455

 arch/arm/configs/exynos_defconfig |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 469b5cc..eeae7bb 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -70,11 +70,15 @@ CONFIG_DEBUG_GPIO=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_I2C=y
 CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_TPS65090=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8997=y
 CONFIG_REGULATOR_MAX77686=y
+CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_FB=y
 CONFIG_FB_MODE_HELPERS=y
@@ -96,6 +100,8 @@ CONFIG_USB_PHY=y
 CONFIG_SAMSUNG_USB2PHY=y
 CONFIG_SAMSUNG_USB3PHY=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
-- 
1.7.9.5



From mingo at kernel.org  Fri May 10 03:06:16 2013
From: mingo at kernel.org (Ingo Molnar)
Date: Fri, 10 May 2013 09:06:16 +0200
Subject: [PATCH -v8 00/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <1368127405-112717-1-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
Message-ID: <20130510070616.GA5763@gmail.com>


* Robin Holt <holt at sgi.com> wrote:

> We recently noticed that reboot of a 1024 cpu machine takes approx 16
> minutes of just stopping the cpus.  The slowdown was tracked to commit
> f96972f.
> 
> The current implementation does all the work of hot removing the cpus
> before halting the system.  We are switching to just migrating to the
> reboot_cpu and then continuing with shutdown/reboot.
> 
> The patch set is broken into eleven parts.  The first two are planned for
> the stable release.  The others move the halt/shutdown/reboot related
> functions to their own kernel/reboot.c file and then move the handling
> of the kernel reboot= kernel parameter to generic kernel code.
> 
> 
> Changes since -v8
>  - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.
> 
>  - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.
> 
>  - Fixed case statement bug.
> 
>  - Went to using simple_strtoul for parsing reboot_cpu=smp###.
> 
>  - Made parsing of reboot= not use any #ifdef'd code.
> 
> Changes since -v7.
>  - Fixed authorship for first patch.
> 
>  - Rebased to Linus' current tree (51a26ae7a).
> 
> Changes since -v6.
>  - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
>    current).
> 
>  - Added a #define for non-hotplug case.
> 
>  - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
> 
>  - Fixup s/reboot_cpu_id/reboot_cpu/
> 
>  - Add include of linux/uaccess.h to allow building on arm.
> 
>  - Removed last remaining checkpatch.pl line length warning on
>    kernel/reboot.c.
> 
>  - Fixed the duplicate handling or the reboot= kernel parameter.
> 
> Changes since -v5.
>  - Moved the arch/x86 reboot= up to the generic kernel code.
> 
> Changes since -v4.
>  - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
>    function
> 
>  - Integrated comments by Srivatsa S. Bhat.
> 
>  - Made one more comment consistent with others in function.
> 
> Changes since -v3.
>  - Added a tested-by for the original reporter.
> 
>  - Fix compile failure found by Joe Perches.
> 
>  - Integrated comments by Joe Perches.
> 
> 
> To: Andrew Morton <akpm at linux-foundation.org>
> Cc: H. Peter Anvin <hpa at zytor.com>
> Cc: Russ Anderson <rja at sgi.com>
> Cc: Robin Holt <holt at sgi.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
> Cc: the arch/x86 maintainers <x86 at kernel.org>
> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

Looks nice now to me. For the x86 bits:

Acked-by: Ingo Molnar <mingo at kernel.org>

Thanks,

	Ingo


From marc.zyngier at arm.com  Fri May 10 03:23:56 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 10 May 2013 09:23:56 +0200
Subject: [RFC PATCH 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <20130509181101.GA17253@gmail.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>
 <20130509181101.GA17253@gmail.com>
Message-ID: <f816c184d2512dad242b383deac7453e@localhost>

On Thu, 9 May 2013 11:11:01 -0700, Christoffer Dall
<cdall at cs.columbia.edu>
wrote:
> On Fri, May 03, 2013 at 03:02:52PM +0100, Marc Zyngier wrote:
>> As KVM/arm64 is looming on the horizon, it makes sense to move some
>> of the common code to a single location in order to reduce duplication.
>> 
>> The code could live anywhere. Actually, most of KVM is already built
>> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
>> not exactly talking about style here. But maybe it is time to start
>> moving into a less ugly direction.
>> 
>> The include files must be in a "public" location, as they are accessed
>> from non-KVM files (arch/arm/kernel/asm-offsets.c).
>> 
>> For this purpose, introduce two new locations:
>> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>>   virt/kvm, so this could be seen as a (very ugly) precedent.
>> - include/kvm/  : there is already an include/xen, and while the
>>   intent is slightly different, this seems as good a location as
>>   any
> 
> This overall looks ok, just a few points:
> 
> 1. Should we have a namespace per arch in the include directory, as in
>    include/kvm/arm?

So I thought of that at one point, but discarded the idea because it seems
to convey the wrong message:
We're moving the include files because they are architecture independent,
and referring to an architecture name in the path feels a bit odd. Or maybe
arm-common?

I don't have strong feelings about it though...

> 2. We could drop the kvm_ prefix from the include files now

Agreed.

It would be interesting to see what the KVM maintainers think of all this.
Gleb? Paolo?

        M.
-- 
Fast, cheap, reliable. Pick two.


From pranavkumar at linaro.org  Fri May 10 03:23:50 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Fri, 10 May 2013 12:53:50 +0530
Subject: [PATCH V2] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
Message-ID: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org>

This patch does following fixes:

1. Make HCR_* flags as unsigned long long constants
Reason : By default, compiler assumes numeric constants as
signed hence sign extending it when assigned to unsigned variable
such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
HCR_CD making entire guest memory non-cacheable. On real HW, this
breaks Stage2 ttbl walks and also breaks VirtIO.

2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
---
 arch/arm64/include/asm/kvm_arm.h |   73 +++++++++++++++++++-------------------
 1 file changed, 37 insertions(+), 36 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 8ced0ca..14ead69 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -18,44 +18,45 @@
 #ifndef __ARM64_KVM_ARM_H__
 #define __ARM64_KVM_ARM_H__
 
+#include <linux/const.h>
 #include <asm/types.h>
 
 /* Hyp Configuration Register (HCR) bits */
-#define HCR_ID		(1 << 33)
-#define HCR_CD		(1 << 32)
+#define HCR_ID		(UL(0x1) << 33)
+#define HCR_CD		(UL(0x1) << 32)
 #define HCR_RW_SHIFT	31
-#define HCR_RW		(1 << HCR_RW_SHIFT)
-#define HCR_TRVM	(1 << 30)
-#define HCR_HCD		(1 << 29)
-#define HCR_TDZ		(1 << 28)
-#define HCR_TGE		(1 << 27)
-#define HCR_TVM		(1 << 26)
-#define HCR_TTLB	(1 << 25)
-#define HCR_TPU		(1 << 24)
-#define HCR_TPC		(1 << 23)
-#define HCR_TSW		(1 << 22)
-#define HCR_TAC		(1 << 21)
-#define HCR_TIDCP	(1 << 20)
-#define HCR_TSC		(1 << 19)
-#define HCR_TID3	(1 << 18)
-#define HCR_TID2	(1 << 17)
-#define HCR_TID1	(1 << 16)
-#define HCR_TID0	(1 << 15)
-#define HCR_TWE		(1 << 14)
-#define HCR_TWI		(1 << 13)
-#define HCR_DC		(1 << 12)
-#define HCR_BSU		(3 << 10)
-#define HCR_BSU_IS	(1 << 10)
-#define HCR_FB		(1 << 9)
-#define HCR_VA		(1 << 8)
-#define HCR_VI		(1 << 7)
-#define HCR_VF		(1 << 6)
-#define HCR_AMO		(1 << 5)
-#define HCR_IMO		(1 << 4)
-#define HCR_FMO		(1 << 3)
-#define HCR_PTW		(1 << 2)
-#define HCR_SWIO	(1 << 1)
-#define HCR_VM		(1)
+#define HCR_RW		(UL(0x1) << HCR_RW_SHIFT)
+#define HCR_TRVM	(UL(0x1) << 30)
+#define HCR_HCD		(UL(0x1) << 29)
+#define HCR_TDZ		(UL(0x1) << 28)
+#define HCR_TGE		(UL(0x1) << 27)
+#define HCR_TVM		(UL(0x1) << 26)
+#define HCR_TTLB	(UL(0x1) << 25)
+#define HCR_TPU		(UL(0x1) << 24)
+#define HCR_TPC		(UL(0x1) << 23)
+#define HCR_TSW		(UL(0x1) << 22)
+#define HCR_TAC		(UL(0x1) << 21)
+#define HCR_TIDCP	(UL(0x1) << 20)
+#define HCR_TSC		(UL(0x1) << 19)
+#define HCR_TID3	(UL(0x1) << 18)
+#define HCR_TID2	(UL(0x1) << 17)
+#define HCR_TID1	(UL(0x1) << 16)
+#define HCR_TID0	(UL(0x1) << 15)
+#define HCR_TWE		(UL(0x1) << 14)
+#define HCR_TWI		(UL(0x1) << 13)
+#define HCR_DC		(UL(0x1) << 12)
+#define HCR_BSU		(UL(0x3) << 10)
+#define HCR_BSU_IS	(UL(0x1) << 10)
+#define HCR_FB		(UL(0x1) << 9)
+#define HCR_VA		(UL(0x1) << 8)
+#define HCR_VI		(UL(0x1) << 7)
+#define HCR_VF		(UL(0x1) << 6)
+#define HCR_AMO		(UL(0x1) << 5)
+#define HCR_IMO		(UL(0x1) << 4)
+#define HCR_FMO		(UL(0x1) << 3)
+#define HCR_PTW		(UL(0x1) << 2)
+#define HCR_SWIO	(UL(0x1) << 1)
+#define HCR_VM		(UL(0x1))
 
 /*
  * The bits we set in HCR:
@@ -111,9 +112,9 @@
 #define VTCR_EL2_SH0_MASK	(3 << 12)
 #define VTCR_EL2_SH0_INNER	(3 << 12)
 #define VTCR_EL2_ORGN0_MASK	(3 << 10)
-#define VTCR_EL2_ORGN0_WBWA	(3 << 10)
+#define VTCR_EL2_ORGN0_WBWA	(1 << 10)
 #define VTCR_EL2_IRGN0_MASK	(3 << 8)
-#define VTCR_EL2_IRGN0_WBWA	(3 << 8)
+#define VTCR_EL2_IRGN0_WBWA	(1 << 8)
 #define VTCR_EL2_SL0_MASK	(3 << 6)
 #define VTCR_EL2_SL0_LVL1	(1 << 6)
 #define VTCR_EL2_T0SZ_MASK	0x3f
-- 
1.7.9.5



From horms+renesas at verge.net.au  Fri May 10 04:05:17 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Fri, 10 May 2013 17:05:17 +0900
Subject: [PATCH 0/2] ARM: shmobile: lager: enable Ether
Message-ID: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>

Hi,

this short series enables the on-board ethernet
of the r8a7790 SoC for on lager baord.

It is based on the renesas-next-20130509 tag of my renesas tree.

It has a run-time dependency on
"sh_eth: add support for r8a7790 SoC"

Simon Horman (2):
  ARM: shmobile: r8a7790: add Ether support
  ARM: shmobile: lager: enable Ether

 arch/arm/boot/dts/r8a7790-lager.dts           |  2 +-
 arch/arm/mach-shmobile/board-lager.c          | 26 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a7790.c        |  6 +++++-
 arch/arm/mach-shmobile/include/mach/r8a7790.h |  3 +++
 arch/arm/mach-shmobile/setup-r8a7790.c        | 15 +++++++++++++++
 5 files changed, 50 insertions(+), 2 deletions(-)

-- 
1.8.2.1



From horms+renesas at verge.net.au  Fri May 10 04:05:19 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Fri, 10 May 2013 17:05:19 +0900
Subject: [PATCH 2/2] ARM: shmobile: lager: enable Ether
In-Reply-To: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>

Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".
---
 arch/arm/boot/dts/r8a7790-lager.dts  |  2 +-
 arch/arm/mach-shmobile/board-lager.c | 26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 09a84fc..b2f61f0 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -16,7 +16,7 @@
 	compatible = "renesas,lager", "renesas,r8a7790";
 
 	chosen {
-		bootargs = "console=ttySC6,115200 ignore_loglevel";
+		bootargs = "console=ttySC6,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
 	};
 
 	memory at 40000000 {
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 6a1ba38..0b8112d 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
@@ -52,6 +53,15 @@ static struct gpio_led_platform_data lager_leds_pdata = {
 	.num_leds	= ARRAY_SIZE(lager_leds),
 };
 
+/* Ether */
+static struct sh_eth_plat_data ether_platdata = {
+	.phy			= 0x1,
+	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
+	.register_type		= SH_ETH_REG_FAST_RCAR,
+	.phy_interface		= PHY_INTERFACE_MODE_RMII,
+	.ether_link_active_low	= 1,
+};
+
 static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
@@ -59,6 +69,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* SCIF1 (CN20: DEBUG SERIAL1) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
 				  "scif1_data", "scif1"),
+	/* Ether */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_link", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_magic", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_mdio", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_rmii", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "intc_irq0", "intc"),
 };
 
 static void __init lager_add_standard_devices(void)
@@ -73,6 +94,11 @@ static void __init lager_add_standard_devices(void)
 	platform_device_register_data(&platform_bus, "leds-gpio", -1,
 				      &lager_leds_pdata,
 				      sizeof(lager_leds_pdata));
+
+	/* Ether RESET */
+	gpio_request_one(RCAR_GP_PIN(5, 31), GPIOF_OUT_INIT_HIGH, NULL);
+
+	r8a7790_add_ether_device(&ether_platdata);
 }
 
 static const char *lager_boards_compat_dt[] __initdata = {
-- 
1.8.2.1



From horms+renesas at verge.net.au  Fri May 10 04:05:18 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Fri, 10 May 2013 17:05:18 +0900
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: add Ether support
In-Reply-To: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368173119-27345-2-git-send-email-horms+renesas@verge.net.au>

Add Ether clock and platform device for R8A7779 SoC; add a function to
register this device with board-specific platform data.

Based on a similar change for the r8a7779 by Sergei Shtylyov.

Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".
---
 arch/arm/mach-shmobile/clock-r8a7790.c        |  6 +++++-
 arch/arm/mach-shmobile/include/mach/r8a7790.h |  3 +++
 arch/arm/mach-shmobile/setup-r8a7790.c        | 15 +++++++++++++++
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bedd20c..2c3123e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -49,6 +49,7 @@
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
 
 #define MODEMR		0xE6160060
 #define SDCKCR		0xE6150074
@@ -178,9 +179,11 @@ static struct clk div6_clks[DIV6_NR] = {
 };
 
 /* MSTP */
-enum { MSTP721, MSTP720,
+enum { MSTP813, MSTP812, MSTP721, MSTP720,
 	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
+	[MSTP812] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 12, 0), /* EtherAVB */
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
 	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
@@ -242,6 +245,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
 	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
 	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
+	CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP813]),
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e6..95b8f7e 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -1,9 +1,12 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
 
+#include <linux/sh_eth.h>
+
 void r8a7790_add_standard_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_timer_init(void);
+void r8a7790_add_ether_device(struct sh_eth_plat_data *pdata);
 
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index eeef5f6..8ed0d7b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -30,6 +30,21 @@
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
 
+
+/* Ether */
+static struct resource ether_resources[] = {
+	DEFINE_RES_MEM(0xee700000, 0x400),
+	DEFINE_RES_IRQ(gic_spi(162)), /* IRQ0 */
+};
+
+void __init r8a7790_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+	platform_device_register_resndata(&platform_bus, "sh-eth", -1,
+					  ether_resources,
+					  ARRAY_SIZE(ether_resources),
+					  pdata, sizeof(*pdata));
+}
+
 static const struct resource pfc_resources[] = {
 	DEFINE_RES_MEM(0xe6060000, 0x250),
 };
-- 
1.8.2.1



From pbonzini at redhat.com  Fri May 10 04:09:08 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Fri, 10 May 2013 10:09:08 +0200
Subject: [RFC PATCH 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <f816c184d2512dad242b383deac7453e@localhost>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>
 <20130509181101.GA17253@gmail.com>
 <f816c184d2512dad242b383deac7453e@localhost>
Message-ID: <518CAB24.3040000@redhat.com>

Il 10/05/2013 09:23, Marc Zyngier ha scritto:
> On Thu, 9 May 2013 11:11:01 -0700, Christoffer Dall
> <cdall at cs.columbia.edu>
> wrote:
>> On Fri, May 03, 2013 at 03:02:52PM +0100, Marc Zyngier wrote:
>>> As KVM/arm64 is looming on the horizon, it makes sense to move some
>>> of the common code to a single location in order to reduce duplication.
>>>
>>> The code could live anywhere. Actually, most of KVM is already built
>>> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
>>> not exactly talking about style here. But maybe it is time to start
>>> moving into a less ugly direction.
>>>
>>> The include files must be in a "public" location, as they are accessed
>>> from non-KVM files (arch/arm/kernel/asm-offsets.c).
>>>
>>> For this purpose, introduce two new locations:
>>> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>>>   virt/kvm, so this could be seen as a (very ugly) precedent.
>>> - include/kvm/  : there is already an include/xen, and while the
>>>   intent is slightly different, this seems as good a location as
>>>   any
>>
>> This overall looks ok, just a few points:
>>
>> 1. Should we have a namespace per arch in the include directory, as in
>>    include/kvm/arm?
> 
> So I thought of that at one point, but discarded the idea because it seems
> to convey the wrong message:
> We're moving the include files because they are architecture independent,
> and referring to an architecture name in the path feels a bit odd. Or maybe
> arm-common?
> 
> I don't have strong feelings about it though...
> 
>> 2. We could drop the kvm_ prefix from the include files now
> 
> Agreed.
> 
> It would be interesting to see what the KVM maintainers think of all this.
> Gleb? Paolo?

include/kvm is good, there is no user-level API to care about.  Perhaps
you can name the includes kvm/arm_vgic.h and kvm/arm_arch_timer.h.  It
keeps the tree shallow but at the same time it suggests some parallel
between the source tree and the include tree.

virt/kvm/arm is certainly better than anything else that comes to mind
:) but I'm not a big fan of $(addprefix); this looks tidier to me:

KVM := ../../../virt/kvm

kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
...
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o

Paolo


From pbonzini at redhat.com  Fri May 10 04:11:39 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Fri, 10 May 2013 10:11:39 +0200
Subject: [RFC PATCH 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <f816c184d2512dad242b383deac7453e@localhost>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>
 <20130509181101.GA17253@gmail.com>
 <f816c184d2512dad242b383deac7453e@localhost>
Message-ID: <518CABBB.7050909@redhat.com>

Il 10/05/2013 09:23, Marc Zyngier ha scritto:
>> > 1. Should we have a namespace per arch in the include directory, as in
>> >    include/kvm/arm?
> So I thought of that at one point, but discarded the idea because it seems
> to convey the wrong message:
> We're moving the include files because they are architecture independent,
> and referring to an architecture name in the path feels a bit odd. Or maybe
> arm-common?

As I wrote in the other message, Linux in general has a shallow include/
tree, so I think putting them in include/kvm/ is good.

Is there any precedent for naming stuff that is common to arm and
aarch64?  I think to 99% of the world they will both be "arm", but of
course the remaining 1% is likely over-represented among KVM-ARM
maintainers. :)

Paolo


From horms at verge.net.au  Fri May 10 04:20:55 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 10 May 2013 17:20:55 +0900
Subject: [PATCH] ARM: shmobile: r8a7778: correct model name in Kconfig
In-Reply-To: <201305090405.41053.sergei.shtylyov@cogentembedded.com>
References: <201305090405.41053.sergei.shtylyov@cogentembedded.com>
Message-ID: <20130510082055.GB27435@verge.net.au>

On Thu, May 09, 2013 at 04:05:40AM +0400, Sergei Shtylyov wrote:
> The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
> M1S which is a SH based SoC.  
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

Morimoto-san,

please review this change.

> 
> ---
> The patch is against the current Linus' tree.
> 
>  arch/arm/mach-shmobile/Kconfig |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Index: linux/arch/arm/mach-shmobile/Kconfig
> ===================================================================
> --- linux.orig/arch/arm/mach-shmobile/Kconfig
> +++ linux/arch/arm/mach-shmobile/Kconfig
> @@ -36,7 +36,7 @@ config ARCH_R8A7740
>  	select RENESAS_INTC_IRQPIN
>  
>  config ARCH_R8A7778
> -	bool "R-Car M1 (R8A77780)"
> +	bool "R-Car M1A (R8A77781)"
>  	select CPU_V7
>  	select SH_CLK_CPG
>  	select ARM_GIC
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From csd at broadcom.com  Fri May 10 03:29:35 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 10 May 2013 00:29:35 -0700
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <20130509063503.GF3041@game.jcrosoft.org>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
 <20130509063503.GF3041@game.jcrosoft.org>
Message-ID: <518CA1DF.5050008@broadcom.com>

Thanks for the feedback.

On 13-05-08 11:35 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:55 Wed 08 May     , Christian Daudt wrote:
>> Add SDHCI driver for the Broadcom 281xx SoCs. Also
>> add bindings for it into bcm281xx dts files.
>> Still missing:
>>   - power managemement
> split the dts/dtsi in an other patch
ok.
>> Signed-off-by: Christian Daudt <csd at broadcom.com>
>>
>> diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
>> index e3bf2d6..65edf6d 100644
>> --- a/arch/arm/configs/bcm_defconfig
>> +++ b/arch/arm/configs/bcm_defconfig
>> @@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
>>   CONFIG_LCD_CLASS_DEVICE=y
>>   CONFIG_BACKLIGHT_CLASS_DEVICE=y
>>   # CONFIG_USB_SUPPORT is not set
>> +CONFIG_MMC=y
>> +CONFIG_MMC_UNSAFE_RESUME=y
>> +CONFIG_MMC_BLOCK_MINORS=32
>> +CONFIG_MMC_TEST=y
>> +CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_PLTFM=y
>> +CONFIG_MMC_SDHCI_BCM_KONA=y
>>   CONFIG_NEW_LEDS=y
>>   CONFIG_LEDS_CLASS=y
>>   CONFIG_LEDS_TRIGGERS=y
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index d88219e..e067c5a 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
>>   
>>   	  YMMV.
>>   
>> +config MMC_SDHCI_BCM_KONA
>> +	tristate "SDHCI support on Broadcom KONA platform"
>> +	depends on ARCH_BCM && MMC_SDHCI_PLTFM
> select MMC_SDHCI_PLTFM
> will be better
Ok - changed it. Why is the select is better than the depends ?
>> +
>> +static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +	unsigned long timeout;
>> +
>> +	/* This timeout should be sufficent for core to reset */
>> +	timeout = jiffies + msecs_to_jiffies(100);
>> +
>> +	/* reset the host using the top level reset */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_RESET;
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +
>> +	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
>> +		if (time_is_before_jiffies(timeout)) {
>> +			pr_err("Error: sd host is stuck in reset!!!\n");
>> +			return -EFAULT;
>> +		}
>> +	}
>> +
>> +	/* bring the host out of reset */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val &= ~KONA_SDHOST_RESET;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	udelay(1000);
> really a udelay of 1ms
I'm trying to clarify on whether this is really necessary but it does 
seem that this is the case. I'll send a follow-up patch if I manage to 
get confirmation on a smaller safe number.

>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +
>> +	return 0;
>> +}
>> +
>> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +
>> +	/* enable the interrupt from the IP core */
>> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
>> +	val |= KONA_SDHOST_IP;
>> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
>> +
>> +	/* Enable the AHB clock gating module to the host */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_EN;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	udelay(1000);
> ditto
see above
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +}
>> +
>> +/*
>> + * Software emulation of the SD card insertion/removal. Set insert=1 for insert
>> + * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
>> + * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
>> + * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
>> + */
>> +static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +	u32 val;
>> +	unsigned long flags;
>> +
>> +	/* this function can be called from various contexts including ISR */
>> +	spin_lock_irqsave(&host->lock, flags);
>> +	/* Ensure SD bus scanning to detect media change */
>> +	host->mmc->rescan_disable = 0;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of min 10uS.
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 * We keep 20uS
>> +	 */
>> +	udelay(20);
>> +	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
>> +
>> +	if (insert) {
>> +		if (kona_dev->cfg->wp_gpio >= 0) {
> gpio_is_valid
done
>> +			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
>> +
>> +			if (wp_status)
>> +				val |= KONA_SDHOST_WP;
>> +			else
>> +				val &= ~KONA_SDHOST_WP;
>> +		}
>> +
>> +		val |= KONA_SDHOST_CD_SW;
>> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
>> +	} else {
>> +		val &= ~KONA_SDHOST_CD_SW;
>> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
>> +	}
>> +	spin_unlock_irqrestore(&host->lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * SD card detection interrupt handler
>> + */
>> +static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +
>> +	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
>> +		pr_debug("card inserted\n");
> dev_dbg
done
>> +		sdhci_bcm_kona_sd_card_emulate(host, 1);
>> +	} else {
>> +		pr_debug("card removed\n");
> ditto
done
>> +static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
>> +			struct platform_device *pdev)
>> +{
>> +	struct sdhci_bcm_kona_cfg *cfg;
>> +	struct device_node *np = pdev->dev.of_node;
>> +	u32 temp;
>> +
>> +	if (!np)
>> +		return NULL;
>> +
>> +	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
>> +	if (!cfg) {
>> +		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
>> +		return NULL;
>> +	}
>> +
>> +	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
>> +	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
>> +	if (of_get_property(np, "non-removable", NULL))
>> +		cfg->non_removable = 1;
> use of_property_read_bool
done
>> +		/* Sleep for 128ms to allow debounce to stabilize */
>> +		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
>> +		/* request irq for cd_gpio after the gpio debounce is
>> +		 * stabilized, otherwise, some bogus gpio interrupts might be
>> +		 * triggered.
>> +		 */
>> +		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
>> +		ret = devm_request_threaded_irq(dev,
>> +				irq,
>> +				NULL,
>> +				sdhci_bcm_kona_pltfm_cd_interrupt,
>> +				IRQF_TRIGGER_FALLING|
>> +				IRQF_TRIGGER_RISING |
>> +				IRQF_ONESHOT |
>> +				IRQF_NO_SUSPEND, "sdio cd", host);
>> +		if (ret) {
>> +			dev_err(kona_dev->dev,
>> +				"Unable to request card detection irq=%d"
>> +				" for gpio=%d  ret=%d\n",
> put the sting of the dev_err on one line so we can grep
merged it into single line


  Thanks,
    csd




From will.deacon at arm.com  Fri May 10 04:40:00 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 May 2013 09:40:00 +0100
Subject: [PATCH v2] ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of
 the old/new value
In-Reply-To: <20130508165500.GH20820@mudshark.cambridge.arm.com>
References: <20130508143004.GA20820@mudshark.cambridge.arm.com>
 <1368025614-17820-1-git-send-email-jaccon.bastiaansen@gmail.com>
 <20130508165500.GH20820@mudshark.cambridge.arm.com>
Message-ID: <20130510084000.GA10492@mudshark.cambridge.arm.com>

Hi Jaccon,

On Wed, May 08, 2013 at 05:55:00PM +0100, Will Deacon wrote:
> On Wed, May 08, 2013 at 04:06:54PM +0100, Jaccon Bastiaansen wrote:
> > The implementation of cmpxchg64() for the ARM v6 and v7 architecture
> > casts parameter 2 and 3 (the old and new 64bit values) to an unsigned
> > long before calling the atomic_cmpxchg64() function. This clears
> > the top 32 bits of the old and new values, resulting in the wrong
> > values being compare-exchanged.
> > 
> > This bug is introduced by commit 3e0f5a15f500 (ARM: 7404/1: cmpxchg64: use atomic64
> 
> Best to line-wrap this at 76 chars.
> 
> > and local64 routines for cmpxchg64)
> > 
> > Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
> 
> Please add the following above your S-o-B:
> 
>   Cc: <stable at vger.kernel.org>
>   Acked-by: Will Deacon <will.deacon at arm.com>
> 
> Then below your S-o-B, add:
> 
>   KernelVersion: 3.9
> 
> and send the patch to patches at arm.linux.org.uk

Did you manage to do this? I can't see anything pending or queued in rmk's
tree...

Cheers,

Will


From marc.zyngier at arm.com  Fri May 10 04:46:29 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 10 May 2013 09:46:29 +0100
Subject: [RFC PATCH 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <518CABBB.7050909@redhat.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-2-git-send-email-marc.zyngier@arm.com>
 <20130509181101.GA17253@gmail.com>
 <f816c184d2512dad242b383deac7453e@localhost> <518CABBB.7050909@redhat.com>
Message-ID: <518CB3E5.7090504@arm.com>

On 10/05/13 09:11, Paolo Bonzini wrote:
> Il 10/05/2013 09:23, Marc Zyngier ha scritto:
>>>> 1. Should we have a namespace per arch in the include directory, as in
>>>>    include/kvm/arm?
>> So I thought of that at one point, but discarded the idea because it seems
>> to convey the wrong message:
>> We're moving the include files because they are architecture independent,
>> and referring to an architecture name in the path feels a bit odd. Or maybe
>> arm-common?
> 
> As I wrote in the other message, Linux in general has a shallow include/
> tree, so I think putting them in include/kvm/ is good.
> 
> Is there any precedent for naming stuff that is common to arm and
> aarch64?  

So far, we have:
- include/linux/irqchip/arm-gic.h
- include/clocksource/arm_arch_timer.h

So the trend seems to use "arm" as a prefix, and I will rename the files
to match this convention (which you actually suggested in your other email).

> I think to 99% of the world they will both be "arm", but of
> course the remaining 1% is likely over-represented among KVM-ARM
> maintainers. :)

Who? What? ;-)

Do you have any comment about patch 2/2? It is a bit more invasive, but
it is a cleanup in my opinion.

Thanks for the feedback,

	M.
-- 
Jazz is not dead. It just smells funny...



From broonie at kernel.org  Fri May 10 05:30:07 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 10 May 2013 10:30:07 +0100
Subject: [PATCH 1/3] driver core: Add API to wait for deferred probe to
 complete during init
In-Reply-To: <CACxGe6sO7kEZgg6km4bzP1cq+2MqGb=D4cZbuWELoz+yhaO6KQ@mail.gmail.com>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368076726-11492-2-git-send-email-skannan@codeaurora.org>
 <CACVXFVMd_iRtEM8ZLK6Ps66gZO6SCp1mXSgY6JbWtRJjJUh+ag@mail.gmail.com>
 <CACxGe6uHBNUcbD9SeRP5c3E8NN-Z2yjVV+9VAhuoJnXoBtTu2w@mail.gmail.com>
 <20130509135017.GD3200@sirena.org.uk>
 <20130509141444.GV18614@n2100.arm.linux.org.uk>
 <CACxGe6sO7kEZgg6km4bzP1cq+2MqGb=D4cZbuWELoz+yhaO6KQ@mail.gmail.com>
Message-ID: <20130510093007.GL3200@sirena.org.uk>

On Thu, May 09, 2013 at 05:39:03PM +0100, Grant Likely wrote:

> +1. You can /minimize/ up-down cycles with the kind of optimization
> that is being attempted here, but the driver still *must* deal with
> bringing resources back up if they get requested "later than you would
> otherwise like".

Now that I think about it we should probably have a debug option like
the shared IRQ testing one which does actually disable all resources as
soon as the kernel gains control of them in order to help with test
coverage for this.
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From plagnioj at jcrosoft.com  Fri May 10 05:29:24 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 11:29:24 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CAGNsrLDw0_yX9nkLYDg0e8-551P7r43UxziTp1TXyyxdiKR5nA@mail.gmail.com>
References: <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
 <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>
 <CAOesGMiqrXSPdEtUzGCuAuhdE4K7FVe65zMM962XuOrO555hnQ@mail.gmail.com>
 <CAGNsrLDw0_yX9nkLYDg0e8-551P7r43UxziTp1TXyyxdiKR5nA@mail.gmail.com>
Message-ID: <20130510092924.GJ3041@game.jcrosoft.org>

Hi,

	so we need to consolidate I'll send a proposition during the day

Best Regards,
J.
On 20:51 Thu 09 May     , Fathi Boudra wrote:
> On 9 May 2013 19:13, Olof Johansson <olof at lixom.net> wrote:
> > On Thu, May 9, 2013 at 6:25 AM, Grant Likely <grant.likely at secretlab.ca> wrote:
> >> On Mon, May 6, 2013 at 9:12 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> >>> On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
> > Yes, a builder is quite useful. Several of us do our own builds as well.
> >
> > When it comes to boot coverage, I'm not sure how successful a central
> > approach would be. It's something where I think Linaro could
> > contribute a lot for their member platforms, but I haven't seen much
> > engagement there yet.
> 
> My previous post was lost. Sorry to repost..
> 
> We've got a jenkins instance doing daily builds on various trees and
> boot testing on the few boards we've got in the lab:
> https://ci.linaro.org/jenkins/view/kernel-ci/
> 
> But it hasn't attracted much interest so far... It's been here since a year.
> 
> > Beyond there, I'd say the expectation is that each maintainer should
> > keep an eye on their own platforms. They _should_ try building and
> > booting linux-next on their platforms, to catch regressions early. And
> > definitely around now, I'd like to see people boot mainline on their
> > platforms to make sure we haven't added any severe regressions in the
> > 3.10 merge window, etc. Some people are really good at this, others
> > less so.
> >
> > What's the old saying, you can lead a horse to water but you can't
> > make him drink? You can build a boot test cluster but you can't make
> > anyone pay attention to it. :(
> >
> > -Olof
> 
> Cheers,
> 
> Fathi


From pbonzini at redhat.com  Fri May 10 05:39:32 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Fri, 10 May 2013 11:39:32 +0200
Subject: [RFC PATCH 2/2] ARM: KVM: standalone Makefile for vgic and timers
In-Reply-To: <1367589773-5609-3-git-send-email-marc.zyngier@arm.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <518CC054.9070002@redhat.com>

Il 03/05/2013 16:02, Marc Zyngier ha scritto:
> On the road to turn KVM/arm64 into something more sensible, change
> the way we compile the VGIC and arch_timer code by using local
> Makefiles instead of the very backward method we used before.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  Makefile              | 2 +-
>  arch/arm/kvm/Makefile | 2 --
>  virt/Makefile         | 1 +
>  virt/kvm/Makefile     | 1 +
>  virt/kvm/arm/Makefile | 2 ++
>  5 files changed, 5 insertions(+), 3 deletions(-)
>  create mode 100644 virt/Makefile
>  create mode 100644 virt/kvm/Makefile
>  create mode 100644 virt/kvm/arm/Makefile
> 
> diff --git a/Makefile b/Makefile
> index 6db672b..19d51df 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -732,7 +732,7 @@ export mod_sign_cmd
>  
>  
>  ifeq ($(KBUILD_EXTMOD),)
> -core-y		+= kernel/ mm/ fs/ ipc/ security/ crypto/ block/
> +core-y		+= kernel/ mm/ fs/ ipc/ security/ crypto/ block/ virt/
>  
>  vmlinux-dirs	:= $(patsubst %/,%,$(filter %/, $(init-y) $(init-m) \
>  		     $(core-y) $(core-m) $(drivers-y) $(drivers-m) \
> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
> index 110d6da..e0540fd 100644
> --- a/arch/arm/kvm/Makefile
> +++ b/arch/arm/kvm/Makefile
> @@ -20,5 +20,3 @@ kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
>  obj-y += kvm-arm.o init.o interrupts.o
>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
>  obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
> -obj-$(CONFIG_KVM_ARM_VGIC) += $(addprefix $(KVM)/arm/, vgic.o)
> -obj-$(CONFIG_KVM_ARM_TIMER) += $(addprefix $(KVM)/arm/, arch_timer.o)
> diff --git a/virt/Makefile b/virt/Makefile
> new file mode 100644
> index 0000000..c3b9ad0
> --- /dev/null
> +++ b/virt/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_KVM)	+= kvm/
> diff --git a/virt/kvm/Makefile b/virt/kvm/Makefile
> new file mode 100644
> index 0000000..dc87943
> --- /dev/null
> +++ b/virt/kvm/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_KVM_ARM_HOST)	+= arm/
> diff --git a/virt/kvm/arm/Makefile b/virt/kvm/arm/Makefile
> new file mode 100644
> index 0000000..4df943b
> --- /dev/null
> +++ b/virt/kvm/arm/Makefile
> @@ -0,0 +1,2 @@
> +obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
> +obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
> 

I'm not sure it is a good idea to do this just for ARM, and I think the
patch would look quite different if you were to support x86 (because x86
builds KVM as a module).  So I would hold off this for now.

OTOH, it is a good idea to use the same idiom to access
../../../virt/kvm from the arch directories.  Can you change
x86/PPC/s390/ia64 as well to use $(KVM) instead of $(addprefix)?

Paolo


From holt at sgi.com  Fri May 10 05:50:14 2013
From: holt at sgi.com (Robin Holt)
Date: Fri, 10 May 2013 04:50:14 -0500
Subject: [PATCH -v9 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <20130510000552.GX3658@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
 <1368127405-112717-5-git-send-email-holt@sgi.com>
 <20130509135100.13947d1805a583703ee8488b@linux-foundation.org>
 <20130510000552.GX3658@sgi.com>
Message-ID: <20130510095014.GY3658@sgi.com>

On Thu, May 09, 2013 at 07:05:53PM -0500, Robin Holt wrote:
> On Thu, May 09, 2013 at 01:51:00PM -0700, Andrew Morton wrote:
> > On Thu,  9 May 2013 14:23:18 -0500 Robin Holt <holt at sgi.com> wrote:
> > 
> > > This patch is preparatory.  It moves reboot related syscall, etc
> > > functions from kernel/sys.c to kernel/reboot.c.
> > 
> > This doesn't apply.
> 
> Weird, I just grabbed a recent Linus kernel tree and all 11 applied.
> I then did an update to linus' tree to commit 70eba4226 and now I get
> rejects on arm.  I will resubmit a -v10 fixed up shortly.

I wonder what you are seeing.  I get all 11 to apply fairly cleanly with
only arch/arm/mach-imx/common.h getting conflicts on a commits after 009e63f
which are related to context.  Otherwise, they applied cleanly.  I assume
you removed the earlier version before trying to apply.

I can resubmit (and will add Ingo's Acked-by), but am not sure it is
going to help the situation.  How would you like me to proceed?

Robin


From ruslan.bilovol at gmail.com  Fri May 10 05:50:42 2013
From: ruslan.bilovol at gmail.com (Ruslan Bilovol)
Date: Fri, 10 May 2013 12:50:42 +0300
Subject: arch/arm/mach-omap2/id.c - IS_ERR_OR_NULL()
In-Reply-To: <20130509090911.GM21614@n2100.arm.linux.org.uk>
References: <20130509090911.GM21614@n2100.arm.linux.org.uk>
Message-ID: <CAB=otbRXPoHWPb3O+AYhdq5BccmLWRE=ZPPPQYQXge6w332+fQ@mail.gmail.com>

Hi Russell,

On Thu, May 9, 2013 at 12:09 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> So, I eliminated all but a very few of these from arch/arm, and I notice
> today that there's a new couple of instances introduced by:
>
> commit 6770b211432564c562c856d612b43bbd42e4ab5e
> Author: Ruslan Bilovol <ruslan.bilovol at ti.com>
> Date:   Thu Feb 14 13:55:24 2013 +0200
>
>     ARM: OMAP2+: Export SoC information to userspace
>
>     In some situations it is useful for userspace to
>     know some SoC-specific information. For example,
>     this may be used for deciding what kernel module to
>     use or how to better configure some settings etc.
>     This patch exports OMAP SoC information to userspace
>     using existing in Linux kernel SoC infrastructure.
>
>     This information can be read under
>     /sys/devices/socX directory
>
>     Signed-off-by: Ruslan Bilovol <ruslan.bilovol at ti.com>
>     [tony at atomide.com: updated for multiplatform changes]
>     Signed-off-by: Tony Lindgren <tony at atomide.com>
>
> +       soc_dev = soc_device_register(soc_dev_attr);
> +       if (IS_ERR_OR_NULL(soc_dev)) {
> +               kfree(soc_dev_attr);
> +               return;
> +       }
> +
> +       parent = soc_device_to_device(soc_dev);
> +       if (!IS_ERR_OR_NULL(parent))
> +               device_create_file(parent, &omap_soc_attr);
>
> This is nonsense.  For the first, IS_ERR() is sufficient.  For the second,
> tell me what error checking is required in the return value of this
> function:
>
> struct device *soc_device_to_device(struct soc_device *soc_dev)
> {
>         return &soc_dev->dev;
> }
>
> when you've already determined that the passed soc_dev is a valid pointer.
> If you read the comments against the prototype:
>
> /**
>  * soc_device_to_device - helper function to fetch struct device
>  * @soc: Previously registered SoC device container
>  */
> struct device *soc_device_to_device(struct soc_device *soc);
>
> if "soc" is valid, it means the "previously registered SoC device container"
> must have succeeded and that can only happen if the struct device has been
> registered.  Ergo, there will always be a valid struct device pointer for
> any registered SoC device container.  Therefore, if soc_device_register()
> succeeds, then the return value from soc_device_to_device() will always be
> valid and no error checking of it is required.
>
> Simples.  The rule as ever applies here: get to know the APIs your using
> and don't fumble around in the dark hoping that you'll get this stuff
> right.

The interesting thing is that extra IS_ERR_OR_NULL checking was
introduced by author
of the SoC API in his implementation for the arm/mach-ux500 platform
and I used the same checking in my implementation when looked into his
implementation for reference.
Thanks for pointing on this, I will be more careful in the future.

Regards,
Ruslan

> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From marc.zyngier at arm.com  Fri May 10 05:59:10 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 10 May 2013 10:59:10 +0100
Subject: [RFC PATCH 2/2] ARM: KVM: standalone Makefile for vgic and timers
In-Reply-To: <518CC054.9070002@redhat.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <1367589773-5609-3-git-send-email-marc.zyngier@arm.com>
 <518CC054.9070002@redhat.com>
Message-ID: <518CC4EE.5060906@arm.com>

On 10/05/13 10:39, Paolo Bonzini wrote:
> Il 03/05/2013 16:02, Marc Zyngier ha scritto:
>> On the road to turn KVM/arm64 into something more sensible, change
>> the way we compile the VGIC and arch_timer code by using local
>> Makefiles instead of the very backward method we used before.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
>> ---
>>  Makefile              | 2 +-
>>  arch/arm/kvm/Makefile | 2 --
>>  virt/Makefile         | 1 +
>>  virt/kvm/Makefile     | 1 +
>>  virt/kvm/arm/Makefile | 2 ++
>>  5 files changed, 5 insertions(+), 3 deletions(-)
>>  create mode 100644 virt/Makefile
>>  create mode 100644 virt/kvm/Makefile
>>  create mode 100644 virt/kvm/arm/Makefile
>>
>> diff --git a/Makefile b/Makefile
>> index 6db672b..19d51df 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -732,7 +732,7 @@ export mod_sign_cmd
>>  
>>  
>>  ifeq ($(KBUILD_EXTMOD),)
>> -core-y		+= kernel/ mm/ fs/ ipc/ security/ crypto/ block/
>> +core-y		+= kernel/ mm/ fs/ ipc/ security/ crypto/ block/ virt/
>>  
>>  vmlinux-dirs	:= $(patsubst %/,%,$(filter %/, $(init-y) $(init-m) \
>>  		     $(core-y) $(core-m) $(drivers-y) $(drivers-m) \
>> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
>> index 110d6da..e0540fd 100644
>> --- a/arch/arm/kvm/Makefile
>> +++ b/arch/arm/kvm/Makefile
>> @@ -20,5 +20,3 @@ kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
>>  obj-y += kvm-arm.o init.o interrupts.o
>>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
>>  obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
>> -obj-$(CONFIG_KVM_ARM_VGIC) += $(addprefix $(KVM)/arm/, vgic.o)
>> -obj-$(CONFIG_KVM_ARM_TIMER) += $(addprefix $(KVM)/arm/, arch_timer.o)
>> diff --git a/virt/Makefile b/virt/Makefile
>> new file mode 100644
>> index 0000000..c3b9ad0
>> --- /dev/null
>> +++ b/virt/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_KVM)	+= kvm/
>> diff --git a/virt/kvm/Makefile b/virt/kvm/Makefile
>> new file mode 100644
>> index 0000000..dc87943
>> --- /dev/null
>> +++ b/virt/kvm/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_KVM_ARM_HOST)	+= arm/
>> diff --git a/virt/kvm/arm/Makefile b/virt/kvm/arm/Makefile
>> new file mode 100644
>> index 0000000..4df943b
>> --- /dev/null
>> +++ b/virt/kvm/arm/Makefile
>> @@ -0,0 +1,2 @@
>> +obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
>> +obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
>>
> 
> I'm not sure it is a good idea to do this just for ARM, and I think the
> patch would look quite different if you were to support x86 (because x86
> builds KVM as a module).  So I would hold off this for now.

Fair enough.

> OTOH, it is a good idea to use the same idiom to access
> ../../../virt/kvm from the arch directories.  Can you change
> x86/PPC/s390/ia64 as well to use $(KVM) instead of $(addprefix)?

Sure. I'll rework the series to include the other arches.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From csd at broadcom.com  Fri May 10 03:23:12 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 10 May 2013 00:23:12 -0700
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <20130509063503.GF3041@game.jcrosoft.org>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
 <20130509063503.GF3041@game.jcrosoft.org>
Message-ID: <518CA060.5090802@broadcom.com>

Thanks for the feedback.

On 13-05-08 11:35 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:55 Wed 08 May     , Christian Daudt wrote:
>> Add SDHCI driver for the Broadcom 281xx SoCs. Also
>> add bindings for it into bcm281xx dts files.
>> Still missing:
>>   - power managemement
> split the dts/dtsi in an other patch
ok.
>> Signed-off-by: Christian Daudt <csd at broadcom.com>
>>
>> diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
>> index e3bf2d6..65edf6d 100644
>> --- a/arch/arm/configs/bcm_defconfig
>> +++ b/arch/arm/configs/bcm_defconfig
>> @@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
>>   CONFIG_LCD_CLASS_DEVICE=y
>>   CONFIG_BACKLIGHT_CLASS_DEVICE=y
>>   # CONFIG_USB_SUPPORT is not set
>> +CONFIG_MMC=y
>> +CONFIG_MMC_UNSAFE_RESUME=y
>> +CONFIG_MMC_BLOCK_MINORS=32
>> +CONFIG_MMC_TEST=y
>> +CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_PLTFM=y
>> +CONFIG_MMC_SDHCI_BCM_KONA=y
>>   CONFIG_NEW_LEDS=y
>>   CONFIG_LEDS_CLASS=y
>>   CONFIG_LEDS_TRIGGERS=y
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index d88219e..e067c5a 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
>>   
>>   	  YMMV.
>>   
>> +config MMC_SDHCI_BCM_KONA
>> +	tristate "SDHCI support on Broadcom KONA platform"
>> +	depends on ARCH_BCM && MMC_SDHCI_PLTFM
> select MMC_SDHCI_PLTFM
> will be better
Ok - changed it. Why is the select is better than the depends ?
>> +
>> +static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +	unsigned long timeout;
>> +
>> +	/* This timeout should be sufficent for core to reset */
>> +	timeout = jiffies + msecs_to_jiffies(100);
>> +
>> +	/* reset the host using the top level reset */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_RESET;
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +
>> +	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
>> +		if (time_is_before_jiffies(timeout)) {
>> +			pr_err("Error: sd host is stuck in reset!!!\n");
>> +			return -EFAULT;
>> +		}
>> +	}
>> +
>> +	/* bring the host out of reset */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val &= ~KONA_SDHOST_RESET;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	udelay(1000);
> really a udelay of 1ms
I'm trying to clarify on whether this is really necessary but it does 
seem that this is the case. I'll send a follow-up patch if I manage to 
get confirmation on a smaller safe number.

>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +
>> +	return 0;
>> +}
>> +
>> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +
>> +	/* enable the interrupt from the IP core */
>> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
>> +	val |= KONA_SDHOST_IP;
>> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
>> +
>> +	/* Enable the AHB clock gating module to the host */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_EN;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	udelay(1000);
> ditto
see above
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +}
>> +
>> +/*
>> + * Software emulation of the SD card insertion/removal. Set insert=1 for insert
>> + * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
>> + * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
>> + * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
>> + */
>> +static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +	u32 val;
>> +	unsigned long flags;
>> +
>> +	/* this function can be called from various contexts including ISR */
>> +	spin_lock_irqsave(&host->lock, flags);
>> +	/* Ensure SD bus scanning to detect media change */
>> +	host->mmc->rescan_disable = 0;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of min 10uS.
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 * We keep 20uS
>> +	 */
>> +	udelay(20);
>> +	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
>> +
>> +	if (insert) {
>> +		if (kona_dev->cfg->wp_gpio >= 0) {
> gpio_is_valid
done
>> +			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
>> +
>> +			if (wp_status)
>> +				val |= KONA_SDHOST_WP;
>> +			else
>> +				val &= ~KONA_SDHOST_WP;
>> +		}
>> +
>> +		val |= KONA_SDHOST_CD_SW;
>> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
>> +	} else {
>> +		val &= ~KONA_SDHOST_CD_SW;
>> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
>> +	}
>> +	spin_unlock_irqrestore(&host->lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * SD card detection interrupt handler
>> + */
>> +static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +
>> +	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
>> +		pr_debug("card inserted\n");
> dev_dbg
done
>> +		sdhci_bcm_kona_sd_card_emulate(host, 1);
>> +	} else {
>> +		pr_debug("card removed\n");
> ditto
done
>> +static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
>> +			struct platform_device *pdev)
>> +{
>> +	struct sdhci_bcm_kona_cfg *cfg;
>> +	struct device_node *np = pdev->dev.of_node;
>> +	u32 temp;
>> +
>> +	if (!np)
>> +		return NULL;
>> +
>> +	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
>> +	if (!cfg) {
>> +		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
>> +		return NULL;
>> +	}
>> +
>> +	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
>> +	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
>> +	if (of_get_property(np, "non-removable", NULL))
>> +		cfg->non_removable = 1;
> use of_property_read_bool
done
>> +		/* Sleep for 128ms to allow debounce to stabilize */
>> +		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
>> +		/* request irq for cd_gpio after the gpio debounce is
>> +		 * stabilized, otherwise, some bogus gpio interrupts might be
>> +		 * triggered.
>> +		 */
>> +		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
>> +		ret = devm_request_threaded_irq(dev,
>> +				irq,
>> +				NULL,
>> +				sdhci_bcm_kona_pltfm_cd_interrupt,
>> +				IRQF_TRIGGER_FALLING|
>> +				IRQF_TRIGGER_RISING |
>> +				IRQF_ONESHOT |
>> +				IRQF_NO_SUSPEND, "sdio cd", host);
>> +		if (ret) {
>> +			dev_err(kona_dev->dev,
>> +				"Unable to request card detection irq=%d"
>> +				" for gpio=%d  ret=%d\n",
> put the sting of the dev_err on one line so we can grep
merged it into single line


  Thanks,
    csd




From nicolas.ferre at atmel.com  Fri May 10 06:05:14 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 12:05:14 +0200
Subject: [PATCH] mmc: atmel-mci: convert to dma_request_slave_channel_compat()
In-Reply-To: <517F7B6F.4070907@atmel.com>
References: <517F7B6F.4070907@atmel.com>
Message-ID: <1368180314-13665-1-git-send-email-nicolas.ferre@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Use generic DMA DT helper. Platforms booting with or without DT populated are
both supported.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Hi Chris,

This patch is part of a series by Ludovic and is adding the generic slave
DMA request channel function, as we now have the support for DMA bindings.

This is the only patch of the series that should go through your tree. And it
seems that my little reminder didn't catch your attention in time for 3.10 merge
window but I still hope that we can make it for 3.10-final... It is also true
that we didn't put you in copy of the original message and that the subject
line was somehow malformed ;-)

Here is the Linux arm kernel patchwork reference of previous discussion:
https://patchwork.kernel.org/patch/2463641/

Thanks, best regards,

 drivers/mmc/host/atmel-mci.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e75774f..aca59d9 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2230,10 +2230,15 @@ static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
 	mmc_free_host(slot->mmc);
 }
 
-static bool atmci_filter(struct dma_chan *chan, void *slave)
+static bool atmci_filter(struct dma_chan *chan, void *pdata)
 {
-	struct mci_dma_data	*sl = slave;
+	struct mci_platform_data *sl_pdata = pdata;
+	struct mci_dma_data *sl;
 
+	if (!sl_pdata)
+		return false;
+
+	sl = sl_pdata->dma_slave;
 	if (sl && find_slave_dev(sl) == chan->device->dev) {
 		chan->private = slave_data_ptr(sl);
 		return true;
@@ -2245,24 +2250,18 @@ static bool atmci_filter(struct dma_chan *chan, void *slave)
 static bool atmci_configure_dma(struct atmel_mci *host)
 {
 	struct mci_platform_data	*pdata;
+	dma_cap_mask_t mask;
 
 	if (host == NULL)
 		return false;
 
 	pdata = host->pdev->dev.platform_data;
 
-	if (!pdata)
-		return false;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
 
-	if (pdata->dma_slave && find_slave_dev(pdata->dma_slave)) {
-		dma_cap_mask_t mask;
-
-		/* Try to grab a DMA channel */
-		dma_cap_zero(mask);
-		dma_cap_set(DMA_SLAVE, mask);
-		host->dma.chan =
-			dma_request_channel(mask, atmci_filter, pdata->dma_slave);
-	}
+	host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
+							  &host->pdev->dev, "rxtx");
 	if (!host->dma.chan) {
 		dev_warn(&host->pdev->dev, "no DMA channel available\n");
 		return false;
-- 
1.8.0



From jaswinder.singh at linaro.org  Fri May 10 06:06:14 2013
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Fri, 10 May 2013 15:36:14 +0530
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <518C3CE9.1010603@ti.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
 <518976B9.2030605@ti.com>
 <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>
 <518AFB1F.7010409@ti.com>
 <CAJe_ZheEZo7Akri40ixBhWzeefABxiJXG1Juc4zQOPNQqyahUw@mail.gmail.com>
 <518C3CE9.1010603@ti.com>
Message-ID: <CAJe_ZhfFs5svKPABHWdKA83+LhxA5+Q3LKuJyqyRj_4SMMm_hg@mail.gmail.com>

Hello Suman,

On 10 May 2013 05:48, Suman Anna <s-anna at ti.com> wrote:

>> No, please. The controller driver should not implement any policy (of
>> allowing/disallowing requests). It should simply try to do as
>> directed. If the client screwed up even after getting info from
>> platform_data/DT, let it suffer.
>
> This would be the same as a client trying to misconfigure a link, you
> cannot blame on a client screw up.
>
One kernel code should not suspect other kernel code's intentions. The
safety/security is in allowing only well written and trusted code
inside the kernel space.
If a client misconfigures a link, the best we could do is call it
buggy. BTW such a hell-bent client would rather screw up with a BUG(),
what do we do then?
So no please, I am not convinced the controller driver should have
anything to do with allow/disallow policy, or any policy at all.

>>>>>
>>>> Already one call ipc_link_ops.startup() reaches the controller upon
>>>> ipc_request_channel.
>>>>
>>>> Do you mean ?
>>>>        ipc_con_ops.startup();
>>>>        ipc_link_ops.startup();
>>>
>>> Yes.
>>>
>> And let the controller startup()/shutdown() upon every
>> link_request/release?
>
> Yes, and the controller driver can take care of any ref-counting or
> whatever other logic it needs to maintain. You see this outside in the
> previous mailbox code, but that is not the responsibility of the core code.
>
The pm_runtime imbalance that you mentioned is the result of OMAP's
API trying to do just that.

>>
>> BTW, I have seen my 2 controllers, OMAP, PL320 and read the dbx500
>> driver. Unsurprisingly none of these have any use for what you call a
>> special ipc_con_ops.startup().  Lets say if the call were there, what
>> would the OMAP put in it?
>
> Enabling the clock for the device. The clock is for the entire IP, a
> link has no power/clock dependencies.
>
OMAP controller driver doesn't do clocks.
It does do rpm though, which does a better job of what OMAP needs.
Please see how pm_runtime_xxx calls are made without worry at each
ipc_link_ops.startup/shutdown.

For controllers that do do clocks, having contiguous
        ipc_con_ops.startup();
        ipc_link_ops.startup();
doesn't save them any complexity. They still have to keep track of
first ipc_link_ops.startup() call in ipc_con_ops.startup() and last
ipc_link_ops.shutdown() call in ipc_con_ops.shutdown()
Which they could very well do in link_ops, if not rpm.

>>
>>>>> Yeah, the pm_runtime_enable cannot be called twice when mailbox is
>>>>> invoked from multiple clients on separate links, so there has to a
>>>>> controller-level logic/ref-counting for that. The clocking for us is on
>>>>> the controller.
>>>>>
>>>> No.  You could call pm_runtime_enable/disable any number of times as
>>>> long as they are balanced. The core does refcounting.
>>>
>>> Exactly, as long as they are balanced. I have two clients dealing with
>>> two remotes (using two links) so pm_runtime_enable on the h/w block
>>> needs to be called only when the first one comes in.
>>>
>> Actually you just gave another reason why the API messing around with
>> controller's power state is a bad idea.
>
> Where do you expect to power up the device (obviously this depends on
> the SoC, and its functional purpose)?
>
Use RPM.  Just like OMAP controller driver already does -
unconditionally call pm_runtime_get upon each link request and
pm_runtime_put upon each link release. Neither the controller nor the
API would have to do refcounting.  If rpm isn't supported, only then
the controller should do refcounting within linp_ops.startup/shutdown
(anyways you want the con_ops and link_ops to be always contiguous).


>> See how mailbox_startup() tries to balance mbox->ops->startup() and
>> mailbox_fini() the mbox->ops->shutdown()  That's very fragile and the
>> cause of imbalance between rpm enable/disable, unless your clients are
>> buggy.
>
> Yeah, it is kinda messed up in the existing code, the startup defined
> there is really for the controller and not the link, and that's why you
> see all the ref-counting balancing logic. The rpm enable/disable being
> called is on the controller's dev, not the link's dev - maybe that's
> what confused you.
>
I wrote the driver for this api, so I do realize the rpm is on
controller. Links are not devices anyways.

cheers,
jassi


From nicolas.ferre at atmel.com  Fri May 10 06:19:53 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 12:19:53 +0200
Subject: [PATCH 1/1] ARM: at91: at91sam9x25ek: fix model name
In-Reply-To: <1367957217-3678-1-git-send-email-plagnioj@jcrosoft.com>
References: <1367957217-3678-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <518CC9C9.2000806@atmel.com>

On 07/05/2013 22:06, Jean-Christophe PLAGNIOL-VILLARD :
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

added the stable tag:

Cc: stable <stable at vger.kernel.org> # 3.8+

and pushed in at91-3.10-fixes branch.
Thanks.

> ---
>   arch/arm/boot/dts/at91sam9x25ek.dts |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
> index 8ddbce0..4948648 100644
> --- a/arch/arm/boot/dts/at91sam9x25ek.dts
> +++ b/arch/arm/boot/dts/at91sam9x25ek.dts
> @@ -11,7 +11,7 @@
>   #include "at91sam9x5ek.dtsi"
>
>   / {
> -	model = "Atmel AT91SAM9G25-EK";
> +	model = "Atmel AT91SAM9X25-EK";
>   	compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
>
>   	ahb {
>

-- 
Nicolas Ferre


From csd at broadcom.com  Fri May 10 03:45:00 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 10 May 2013 00:45:00 -0700
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <20130509063503.GF3041@game.jcrosoft.org>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
 <20130509063503.GF3041@game.jcrosoft.org>
Message-ID: <518CA57C.3000302@broadcom.com>

Thanks for the feedback.

On 13-05-08 11:35 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:55 Wed 08 May     , Christian Daudt wrote:
>> Add SDHCI driver for the Broadcom 281xx SoCs. Also
>> add bindings for it into bcm281xx dts files.
>> Still missing:
>>   - power managemement
> split the dts/dtsi in an other patch
ok.
>> Signed-off-by: Christian Daudt <csd at broadcom.com>
>>
>> diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
>> index e3bf2d6..65edf6d 100644
>> --- a/arch/arm/configs/bcm_defconfig
>> +++ b/arch/arm/configs/bcm_defconfig
>> @@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
>>   CONFIG_LCD_CLASS_DEVICE=y
>>   CONFIG_BACKLIGHT_CLASS_DEVICE=y
>>   # CONFIG_USB_SUPPORT is not set
>> +CONFIG_MMC=y
>> +CONFIG_MMC_UNSAFE_RESUME=y
>> +CONFIG_MMC_BLOCK_MINORS=32
>> +CONFIG_MMC_TEST=y
>> +CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_PLTFM=y
>> +CONFIG_MMC_SDHCI_BCM_KONA=y
>>   CONFIG_NEW_LEDS=y
>>   CONFIG_LEDS_CLASS=y
>>   CONFIG_LEDS_TRIGGERS=y
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index d88219e..e067c5a 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
>>
>>   	  YMMV.
>>
>> +config MMC_SDHCI_BCM_KONA
>> +	tristate "SDHCI support on Broadcom KONA platform"
>> +	depends on ARCH_BCM && MMC_SDHCI_PLTFM
> select MMC_SDHCI_PLTFM
> will be better
Ok - changed it. Why is the select is better than the depends ?
>> +
>> +static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +	unsigned long timeout;
>> +
>> +	/* This timeout should be sufficent for core to reset */
>> +	timeout = jiffies + msecs_to_jiffies(100);
>> +
>> +	/* reset the host using the top level reset */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_RESET;
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +
>> +	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
>> +		if (time_is_before_jiffies(timeout)) {
>> +			pr_err("Error: sd host is stuck in reset!!!\n");
>> +			return -EFAULT;
>> +		}
>> +	}
>> +
>> +	/* bring the host out of reset */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val &= ~KONA_SDHOST_RESET;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	udelay(1000);
> really a udelay of 1ms
I'm trying to clarify on whether this is really necessary but it does 
seem that this is the case. I'll send a follow-up patch if I manage to 
get confirmation on a smaller safe number.

>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +
>> +	return 0;
>> +}
>> +
>> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +
>> +	/* enable the interrupt from the IP core */
>> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
>> +	val |= KONA_SDHOST_IP;
>> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
>> +
>> +	/* Enable the AHB clock gating module to the host */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_EN;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	udelay(1000);
> ditto
see above
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +}
>> +
>> +/*
>> + * Software emulation of the SD card insertion/removal. Set insert=1 for insert
>> + * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
>> + * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
>> + * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
>> + */
>> +static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +	u32 val;
>> +	unsigned long flags;
>> +
>> +	/* this function can be called from various contexts including ISR */
>> +	spin_lock_irqsave(&host->lock, flags);
>> +	/* Ensure SD bus scanning to detect media change */
>> +	host->mmc->rescan_disable = 0;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of min 10uS.
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 * We keep 20uS
>> +	 */
>> +	udelay(20);
>> +	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
>> +
>> +	if (insert) {
>> +		if (kona_dev->cfg->wp_gpio >= 0) {
> gpio_is_valid
done
>> +			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
>> +
>> +			if (wp_status)
>> +				val |= KONA_SDHOST_WP;
>> +			else
>> +				val &= ~KONA_SDHOST_WP;
>> +		}
>> +
>> +		val |= KONA_SDHOST_CD_SW;
>> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
>> +	} else {
>> +		val &= ~KONA_SDHOST_CD_SW;
>> +		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
>> +	}
>> +	spin_unlock_irqrestore(&host->lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * SD card detection interrupt handler
>> + */
>> +static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +
>> +	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
>> +		pr_debug("card inserted\n");
> dev_dbg
done
>> +		sdhci_bcm_kona_sd_card_emulate(host, 1);
>> +	} else {
>> +		pr_debug("card removed\n");
> ditto
done
>> +static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
>> +			struct platform_device *pdev)
>> +{
>> +	struct sdhci_bcm_kona_cfg *cfg;
>> +	struct device_node *np = pdev->dev.of_node;
>> +	u32 temp;
>> +
>> +	if (!np)
>> +		return NULL;
>> +
>> +	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
>> +	if (!cfg) {
>> +		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
>> +		return NULL;
>> +	}
>> +
>> +	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
>> +	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
>> +	if (of_get_property(np, "non-removable", NULL))
>> +		cfg->non_removable = 1;
> use of_property_read_bool
done
>> +		/* Sleep for 128ms to allow debounce to stabilize */
>> +		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
>> +		/* request irq for cd_gpio after the gpio debounce is
>> +		 * stabilized, otherwise, some bogus gpio interrupts might be
>> +		 * triggered.
>> +		 */
>> +		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
>> +		ret = devm_request_threaded_irq(dev,
>> +				irq,
>> +				NULL,
>> +				sdhci_bcm_kona_pltfm_cd_interrupt,
>> +				IRQF_TRIGGER_FALLING|
>> +				IRQF_TRIGGER_RISING |
>> +				IRQF_ONESHOT |
>> +				IRQF_NO_SUSPEND, "sdio cd", host);
>> +		if (ret) {
>> +			dev_err(kona_dev->dev,
>> +				"Unable to request card detection irq=%d"
>> +				" for gpio=%d  ret=%d\n",
> put the sting of the dev_err on one line so we can grep
merged it into single line


  Thanks,
    csd




From sergei.shtylyov at cogentembedded.com  Fri May 10 06:26:50 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 10 May 2013 14:26:50 +0400
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: add Ether support
In-Reply-To: <1368173119-27345-2-git-send-email-horms+renesas@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <518CCB6A.2060303@cogentembedded.com>

Hello.

On 10-05-2013 12:05, Simon Horman wrote:

> Add Ether clock and platform device for R8A7779 SoC; add a function to
> register this device with board-specific platform data.

> Based on a similar change for the r8a7779 by Sergei Shtylyov.

> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

> ---

> This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".
> ---
>   arch/arm/mach-shmobile/clock-r8a7790.c        |  6 +++++-
>   arch/arm/mach-shmobile/include/mach/r8a7790.h |  3 +++
>   arch/arm/mach-shmobile/setup-r8a7790.c        | 15 +++++++++++++++
>   3 files changed, 23 insertions(+), 1 deletion(-)

> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> index bedd20c..2c3123e 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
[...]
> @@ -178,9 +179,11 @@ static struct clk div6_clks[DIV6_NR] = {
>   };
>
>   /* MSTP */
> -enum { MSTP721, MSTP720,
> +enum { MSTP813, MSTP812,

    I think these two should be on a line of their own...

> MSTP721, MSTP720,
>   	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
>   static struct clk mstp_clks[MSTP_NR] = {
> +	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
> +	[MSTP812] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 12, 0), /* EtherAVB */
>   	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
>   	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
>   	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
[...]
> diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> index 2e919e6..95b8f7e 100644
> --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
> +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> @@ -1,9 +1,12 @@
>   #ifndef __ASM_R8A7790_H__
>   #define __ASM_R8A7790_H__
>
> +#include <linux/sh_eth.h>
> +
>   void r8a7790_add_standard_devices(void);
>   void r8a7790_clock_init(void);
>   void r8a7790_pinmux_init(void);
>   void r8a7790_timer_init(void);
> +void r8a7790_add_ether_device(struct sh_eth_plat_data *pdata);

    Perhaps better place is right after r8a7790_add_standard_devices()...

>   #endif /* __ASM_R8A7790_H__ */
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> index eeef5f6..8ed0d7b 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> @@ -30,6 +30,21 @@
>   #include <mach/r8a7790.h>
>   #include <asm/mach/arch.h>
>
> +
> +/* Ether */
> +static struct resource ether_resources[] = {

    You missed the '__initdata' annotation.

> +	DEFINE_RES_MEM(0xee700000, 0x400),
> +	DEFINE_RES_IRQ(gic_spi(162)), /* IRQ0 */
> +};

WBR, Sergei



From nicolas.ferre at atmel.com  Fri May 10 06:30:07 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 12:30:07 +0200
Subject: [PATCH] ARM: at91: dts: request only spi cs-gpios used on sama5d3x
 cpu module
Message-ID: <1368181807-15182-1-git-send-email-nicolas.ferre@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Instead of requesting all available spi cs-gpios, request only the ones used on
the board, in our case on the cpu module.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/sama5d3.dtsi    | 10 ----------
 arch/arm/boot/dts/sama5d3xcm.dtsi |  4 ++++
 2 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..dee5e2f 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -75,11 +75,6 @@
 				compatible = "atmel,at91sam9x5-spi";
 				reg = <0xf0004000 0x100>;
 				interrupts = <24 4 3>;
-				cs-gpios = <&pioD 13 0
-					    &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
-					    &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
-					    &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
-					   >;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -203,11 +198,6 @@
 				compatible = "atmel,at91sam9x5-spi";
 				reg = <0xf8008000 0x100>;
 				interrupts = <25 4 3>;
-				cs-gpios = <&pioC 25 0
-					    &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
-					    &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
-					    &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
-					   >;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f8ed40..b336e77 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -32,6 +32,10 @@
 
 	ahb {
 		apb {
+			spi0: spi at f0004000 {
+				cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
+			};
+
 			macb0: ethernet at f0028000 {
 				phy-mode = "rgmii";
 			};
-- 
1.8.0



From nicolas.ferre at atmel.com  Fri May 10 06:31:51 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 12:31:51 +0200
Subject: [PATCH] ARM: at91: dts: request only spi cs-gpios used on sama5d3x
 cpu module
In-Reply-To: <1368181807-15182-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368181807-15182-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <518CCC97.904@atmel.com>

On 10/05/2013 12:30, Nicolas Ferre :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Instead of requesting all available spi cs-gpios, request only the ones used on
> the board, in our case on the cpu module.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

And stacked on at91-3.10-fixes branch.

> ---
>   arch/arm/boot/dts/sama5d3.dtsi    | 10 ----------
>   arch/arm/boot/dts/sama5d3xcm.dtsi |  4 ++++
>   2 files changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
> index 2e643ea..dee5e2f 100644
> --- a/arch/arm/boot/dts/sama5d3.dtsi
> +++ b/arch/arm/boot/dts/sama5d3.dtsi
> @@ -75,11 +75,6 @@
>   				compatible = "atmel,at91sam9x5-spi";
>   				reg = <0xf0004000 0x100>;
>   				interrupts = <24 4 3>;
> -				cs-gpios = <&pioD 13 0
> -					    &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
> -					    &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
> -					    &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
> -					   >;
>   				pinctrl-names = "default";
>   				pinctrl-0 = <&pinctrl_spi0>;
>   				status = "disabled";
> @@ -203,11 +198,6 @@
>   				compatible = "atmel,at91sam9x5-spi";
>   				reg = <0xf8008000 0x100>;
>   				interrupts = <25 4 3>;
> -				cs-gpios = <&pioC 25 0
> -					    &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
> -					    &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
> -					    &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
> -					   >;
>   				pinctrl-names = "default";
>   				pinctrl-0 = <&pinctrl_spi1>;
>   				status = "disabled";
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index 1f8ed40..b336e77 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -32,6 +32,10 @@
>
>   	ahb {
>   		apb {
> +			spi0: spi at f0004000 {
> +				cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
> +			};
> +
>   			macb0: ethernet at f0028000 {
>   				phy-mode = "rgmii";
>   			};
>


-- 
Nicolas Ferre


From plagnioj at jcrosoft.com  Fri May 10 06:26:58 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 12:26:58 +0200
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <518CA1DF.5050008@broadcom.com>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
 <20130509063503.GF3041@game.jcrosoft.org>
 <518CA1DF.5050008@broadcom.com>
Message-ID: <20130510102658.GK3041@game.jcrosoft.org>

On 00:29 Fri 10 May     , Christian Daudt wrote:
> Thanks for the feedback.
> 
> On 13-05-08 11:35 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >On 22:55 Wed 08 May     , Christian Daudt wrote:
> >>Add SDHCI driver for the Broadcom 281xx SoCs. Also
> >>add bindings for it into bcm281xx dts files.
> >>Still missing:
> >>  - power managemement
> >split the dts/dtsi in an other patch
> ok.
> >>Signed-off-by: Christian Daudt <csd at broadcom.com>
> >>
> >>diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
> >>index e3bf2d6..65edf6d 100644
> >>--- a/arch/arm/configs/bcm_defconfig
> >>+++ b/arch/arm/configs/bcm_defconfig
> >>@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
> >>  CONFIG_LCD_CLASS_DEVICE=y
> >>  CONFIG_BACKLIGHT_CLASS_DEVICE=y
> >>  # CONFIG_USB_SUPPORT is not set
> >>+CONFIG_MMC=y
> >>+CONFIG_MMC_UNSAFE_RESUME=y
> >>+CONFIG_MMC_BLOCK_MINORS=32
> >>+CONFIG_MMC_TEST=y
> >>+CONFIG_MMC_SDHCI=y
> >>+CONFIG_MMC_SDHCI_PLTFM=y
> >>+CONFIG_MMC_SDHCI_BCM_KONA=y
> >>  CONFIG_NEW_LEDS=y
> >>  CONFIG_LEDS_CLASS=y
> >>  CONFIG_LEDS_TRIGGERS=y
> >>diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> >>index d88219e..e067c5a 100644
> >>--- a/drivers/mmc/host/Kconfig
> >>+++ b/drivers/mmc/host/Kconfig
> >>@@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
> >>  	  YMMV.
> >>+config MMC_SDHCI_BCM_KONA
> >>+	tristate "SDHCI support on Broadcom KONA platform"
> >>+	depends on ARCH_BCM && MMC_SDHCI_PLTFM
> >select MMC_SDHCI_PLTFM
> >will be better
> Ok - changed it. Why is the select is better than the depends ?
> >>+
> >>+static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
> >>+{
> >>+	unsigned int val;
> >>+	unsigned long timeout;
> >>+
> >>+	/* This timeout should be sufficent for core to reset */
> >>+	timeout = jiffies + msecs_to_jiffies(100);
> >>+
> >>+	/* reset the host using the top level reset */
> >>+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> >>+	val |= KONA_SDHOST_RESET;
> >>+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> >>+
> >>+	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
> >>+		if (time_is_before_jiffies(timeout)) {
> >>+			pr_err("Error: sd host is stuck in reset!!!\n");
> >>+			return -EFAULT;
> >>+		}
> >>+	}
> >>+
> >>+	/* bring the host out of reset */
> >>+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> >>+	val &= ~KONA_SDHOST_RESET;
> >>+
> >>+	/*
> >>+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> >>+	 * Back-to-Back writes to same register needs delay when SD bus clock
> >>+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> >>+	 * insert-removal.
> >>+	 */
> >>+	udelay(1000);
> >really a udelay of 1ms
> I'm trying to clarify on whether this is really necessary but it
> does seem that this is the case. I'll send a follow-up patch if I
> manage to get confirmation on a smaller safe number.

a smaller delay will be better otherwise a msleep(1)

Best Regards,
J.
> 
> >>+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> >>+
> >>+	return 0;
> >>+}
> >>+
> >>+static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
> >>+{
> >>+	unsigned int val;
> >>+
> >>+	/* enable the interrupt from the IP core */
> >>+	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
> >>+	val |= KONA_SDHOST_IP;
> >>+	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
> >>+
> >>+	/* Enable the AHB clock gating module to the host */
> >>+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> >>+	val |= KONA_SDHOST_EN;
> >>+
> >>+	/*
> >>+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> >>+	 * Back-to-Back writes to same register needs delay when SD bus clock
> >>+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> >>+	 * insert-removal.
> >>+	 */
> >>+	udelay(1000);
> >ditto
> see above
> >>+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> >>+}
> >>+
> >>+/*
> >>+ * Software emulation of the SD card insertion/removal. Set insert=1 for insert
> >>+ * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
> >>+ * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
> >>+ * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
> >>+ */
> >>+static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
> >>+{
> >>+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
> >>+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
> >>+	u32 val;
> >>+	unsigned long flags;
> >>+
> >>+	/* this function can be called from various contexts including ISR */
> >>+	spin_lock_irqsave(&host->lock, flags);
> >>+	/* Ensure SD bus scanning to detect media change */
> >>+	host->mmc->rescan_disable = 0;
> >>+
> >>+	/*
> >>+	 * Back-to-Back register write needs a delay of min 10uS.
> >>+	 * Back-to-Back writes to same register needs delay when SD bus clock
> >>+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> >>+	 * insert-removal.
> >>+	 * We keep 20uS
> >>+	 */
> >>+	udelay(20);
> >>+	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
> >>+
> >>+	if (insert) {
> >>+		if (kona_dev->cfg->wp_gpio >= 0) {
> >gpio_is_valid
> done
> >>+			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
> >>+
> >>+			if (wp_status)
> >>+				val |= KONA_SDHOST_WP;
> >>+			else
> >>+				val &= ~KONA_SDHOST_WP;
> >>+		}
> >>+
> >>+		val |= KONA_SDHOST_CD_SW;
> >>+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
> >>+	} else {
> >>+		val &= ~KONA_SDHOST_CD_SW;
> >>+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
> >>+	}
> >>+	spin_unlock_irqrestore(&host->lock, flags);
> >>+
> >>+	return 0;
> >>+}
> >>+
> >>+/*
> >>+ * SD card detection interrupt handler
> >>+ */
> >>+static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
> >>+{
> >>+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
> >>+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
> >>+
> >>+	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
> >>+		pr_debug("card inserted\n");
> >dev_dbg
> done
> >>+		sdhci_bcm_kona_sd_card_emulate(host, 1);
> >>+	} else {
> >>+		pr_debug("card removed\n");
> >ditto
> done
> >>+static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
> >>+			struct platform_device *pdev)
> >>+{
> >>+	struct sdhci_bcm_kona_cfg *cfg;
> >>+	struct device_node *np = pdev->dev.of_node;
> >>+	u32 temp;
> >>+
> >>+	if (!np)
> >>+		return NULL;
> >>+
> >>+	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
> >>+	if (!cfg) {
> >>+		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
> >>+		return NULL;
> >>+	}
> >>+
> >>+	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
> >>+	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
> >>+	if (of_get_property(np, "non-removable", NULL))
> >>+		cfg->non_removable = 1;
> >use of_property_read_bool
> done
> >>+		/* Sleep for 128ms to allow debounce to stabilize */
> >>+		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
> >>+		/* request irq for cd_gpio after the gpio debounce is
> >>+		 * stabilized, otherwise, some bogus gpio interrupts might be
> >>+		 * triggered.
> >>+		 */
> >>+		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
> >>+		ret = devm_request_threaded_irq(dev,
> >>+				irq,
> >>+				NULL,
> >>+				sdhci_bcm_kona_pltfm_cd_interrupt,
> >>+				IRQF_TRIGGER_FALLING|
> >>+				IRQF_TRIGGER_RISING |
> >>+				IRQF_ONESHOT |
> >>+				IRQF_NO_SUSPEND, "sdio cd", host);
> >>+		if (ret) {
> >>+			dev_err(kona_dev->dev,
> >>+				"Unable to request card detection irq=%d"
> >>+				" for gpio=%d  ret=%d\n",
> >put the sting of the dev_err on one line so we can grep
> merged it into single line
> 
> 
>  Thanks,
>    csd
> 
> 


From sergei.shtylyov at cogentembedded.com  Fri May 10 06:35:01 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 10 May 2013 14:35:01 +0400
Subject: [PATCH 2/2] ARM: shmobile: lager: enable Ether
In-Reply-To: <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>
Message-ID: <518CCD55.6070101@cogentembedded.com>

Hello.

On 10-05-2013 12:05, Simon Horman wrote:

> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

> ---

> This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".
> ---
>   arch/arm/boot/dts/r8a7790-lager.dts  |  2 +-
>   arch/arm/mach-shmobile/board-lager.c | 26 ++++++++++++++++++++++++++
>   2 files changed, 27 insertions(+), 1 deletion(-)

> diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
> index 09a84fc..b2f61f0 100644
> --- a/arch/arm/boot/dts/r8a7790-lager.dts
> +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> @@ -16,7 +16,7 @@
>   	compatible = "renesas,lager", "renesas,r8a7790";
>
>   	chosen {
> -		bootargs = "console=ttySC6,115200 ignore_loglevel";
> +		bootargs = "console=ttySC6,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
>   	};
>
>   	memory at 40000000 {

    Perhaps you shouldn't mix .dts changes with source changes?

> diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
> index 6a1ba38..0b8112d 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
[...]
> @@ -59,6 +69,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
>   	/* SCIF1 (CN20: DEBUG SERIAL1) */
>   	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
>   				  "scif1_data", "scif1"),
> +	/* Ether */
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_link", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_magic", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_mdio", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_rmii", "eth"),

     I thought MDIO bus was a part of RMII. At least Wikipedia told me 
so. :-)

WBR, Sergei



From james.hogan at imgtec.com  Fri May 10 06:41:10 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 11:41:10 +0100
Subject: [PATCH v2 2/3] clk: add support for clock reparent on set_rate
In-Reply-To: <518C0097.50300@codeaurora.org>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <1366388904-13903-3-git-send-email-james.hogan@imgtec.com>
 <518C0097.50300@codeaurora.org>
Message-ID: <518CCEC6.5050507@imgtec.com>

On 09/05/13 21:01, Stephen Boyd wrote:
> I believe we'll need to update the check in __clk_init() to allow you to
> have either a .round_rate or a .determine_rate op if you have a
> .recalc_rate op. Right now it fails to register the clock and then
> oopses later on while setting up clock debugfs.
> 
> Here's a (probably whitespace damaged) patch for the first one.

Thanks, I'll incorporate that.

Cheers
James



From james.hogan at imgtec.com  Fri May 10 06:43:53 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 11:43:53 +0100
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <518BFD99.2010208@codeaurora.org>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <518AE16D.5060501@codeaurora.org> <518B663D.60806@imgtec.com>
 <518BFD99.2010208@codeaurora.org>
Message-ID: <518CCF69.9040200@imgtec.com>

On 09/05/13 20:48, Stephen Boyd wrote:
> On 05/09/13 02:02, James Hogan wrote:
>> On 09/05/13 00:36, Stephen Boyd wrote:
>>> Which tree is this based on? I get failures with git am on patch 2.
>>>
>> It was based on v3.9-rc4.
>>
> 
> Thanks. Would it be possible for you to update to Mike's for-next
> branch? I've done the rebase myself for now and it seems to work well
> enough. I'll need to add the set_rate_and_parent() op on top.
> 

Yes, I will do that before reposting. Thanks for giving it a spin.

Cheers
James



From broonie at kernel.org  Fri May 10 06:55:45 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 10 May 2013 11:55:45 +0100
Subject: [RFC 23/42] drivers/spi: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-24-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-24-git-send-email-wsa@the-dreams.de>
Message-ID: <20130510105545.GO3200@sirena.org.uk>

On Fri, May 10, 2013 at 10:17:08AM +0200, Wolfram Sang wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From rjw at sisk.pl  Fri May 10 07:11:51 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Fri, 10 May 2013 13:11:51 +0200
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-2-git-send-email-holt@sgi.com>
 <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>
Message-ID: <1651579.orCh9JNVz6@vostro.rjw.lan>

On Thursday, May 09, 2013 03:01:21 PM Andrew Morton wrote:
> On Tue,  7 May 2013 09:39:45 -0500 Robin Holt <holt at sgi.com> wrote:
> 
> > From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>
> > 
> > There are instances in the kernel where we would like to disable
> > CPU hotplug (from sysfs) during some important operation. Today
> > the freezer code depends on this and the code to do it was kinda
> > tailor-made for that.
> > 
> > Restructure the code and make it generic enough to be useful for
> > other usecases too.
> > 
> > ...
> >
> > --- a/include/linux/cpu.h
> > +++ b/include/linux/cpu.h
> > @@ -141,6 +141,8 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
> >  }
> >  #endif
> >  
> > +extern void cpu_hotplug_disable(void);
> > +extern void cpu_hotplug_enable(void);
> >  int cpu_up(unsigned int cpu);
> >  void notify_cpu_starting(unsigned int cpu);
> >  extern void cpu_maps_update_begin(void);
> > @@ -148,6 +150,7 @@ extern void cpu_maps_update_done(void);
> >  
> >  #else	/* CONFIG_SMP */
> >  
> > +#define cpu_hotplug_disable()	do { } while (0)
> >  #define cpu_notifier(fn, pri)	do { (void)(fn); } while (0)
> >  
> 
> Breaks alpha allmodconfig because cpu_hotplug_disable() is absent from
> vmlinux.
> 
> cpu_hotplug_disable() doesn't get compiled unless we've defined
> CONFIG_PM_SLEEP_SMP.  I cannot begin to imagine what the logic is
> behind that!

I suppose it was only used by suspend/hibernate code paths when this was
introduced.

Thanks,
Rafael



From marex at denx.de  Fri May 10 08:26:34 2013
From: marex at denx.de (Marek Vasut)
Date: Fri, 10 May 2013 14:26:34 +0200
Subject: [PATCH 1/2] ARM: mxs: Add default AUART2 pinmux
Message-ID: <1368188795-9114-1-git-send-email-marex@denx.de>

Add pinmux for AUART2 pins where they are in mux0.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx28.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 7ba4966..13799cf 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -308,6 +308,17 @@
 					fsl,pull-up = <0>;
 				};
 
+				auart2_2pins_b: auart2-2pins at 1 {
+					reg = <1>;
+					fsl,pinmux-ids = <
+						0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
+						0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
+					>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
 				auart3_pins_a: auart3 at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
-- 
1.7.10.4



From marex at denx.de  Fri May 10 08:26:35 2013
From: marex at denx.de (Marek Vasut)
Date: Fri, 10 May 2013 14:26:35 +0200
Subject: [PATCH 2/2] ARM: mxs: Fix UARTs on M28EVK
In-Reply-To: <1368188795-9114-1-git-send-email-marex@denx.de>
References: <1368188795-9114-1-git-send-email-marex@denx.de>
Message-ID: <1368188795-9114-2-git-send-email-marex@denx.de>

Make use of RTS/CTS lines on AUART0 and register AUART1 and AUART2
which are routed onto a pin header.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx28-m28evk.dts |   14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index fd36e1c..ed1f1c0 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -195,7 +195,19 @@
 
 			auart0: serial at 8006a000 {
 				pinctrl-names = "default";
-				pinctrl-0 = <&auart0_2pins_a>;
+				pinctrl-0 = <&auart0_pins_a>;
+				status = "okay";
+			};
+
+			auart1: serial at 8006c000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&auart1_pins_a>;
+				status = "okay";
+			};
+
+			auart2: serial at 8006e000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&auart2_2pins_b>;
 				status = "okay";
 			};
 		};
-- 
1.7.10.4



From pavel at denx.de  Fri May 10 08:38:23 2013
From: pavel at denx.de (Pavel Machek)
Date: Fri, 10 May 2013 14:38:23 +0200
Subject: dw_apb_timer_of.c: remove parts that were picoxcell-specific
In-Reply-To: <51899CBC.6020003@linaro.org>
References: <20130426121433.GA16249@amd.pavel.ucw.cz>
 <201305061545.22587.arnd@arndb.de>
 <20130506155304.GA6645@amd.pavel.ucw.cz>
 <201305062324.17080.arnd@arndb.de>
 <20130507135752.GA3500@amd.pavel.ucw.cz>
 <51892E5E.8090909@linaro.org>
 <20130507201126.GA8169@amd.pavel.ucw.cz>
 <51899CBC.6020003@linaro.org>
Message-ID: <20130510123823.GA6451@amd.pavel.ucw.cz>

On Tue 2013-05-07 17:30:52, John Stultz wrote:
> On 05/07/2013 01:11 PM, Pavel Machek wrote:
> >It seems we made a mistake when creating dw_apb_timer_of.c:
> >picoxcell sched_clock had parts that were not related to
> >dw_apb_timer, yet we moved them to dw_apb_timer_of, and tried to
> >use them on socfpga.
> >
> >This results in system where user/system time is not measured
> >properly, as demonstrated by
> >     time dd if=/dev/urandom of=/dev/zero bs=100000 count=100
> >So this patch switches sched_clock to hardware that exists on both
> >platforms, and adds missing of_node_put() in dw_apb_timer_init().
> >Signed-off-by: Pavel Machek <pavel at denx.de>
> >Acked-by: Jamie Iles <jamie at jamieiles.com>
> 
> Ok. I'm still not a happy about the general issue of
> sched_clock/clockevent code being in drivers/clocksources (I know,
> everyone is sick of my griping about it :), so reviewing this sucks,
> but at least this patch technically isn't making that issue worse.

Is there anything concrete you'd like to improve?

Yes, clocksource/clockevent split is confusing, doubly so because it
is same hardware driving both. Would it make sense to create "use this
clocksource for sched_clock()" helper?

> Additionally, this is an *ugly* driver in my opinion. Its split
> between arch specific logic in arch/x86/kernel/apb_timer.c,
> arch/arm/mach-picoxcell/common.c, and
> arch/arm/mach-socfpga/socfpga.c, and 

Can you elaborate? There's very little logic in socfpga.c, just single
line

        .timer          = &dw_apb_timer,

> then arch independent logic in
> drivers/clocksource/dw_apb_timer.c and
> drivers/clocksource/dw_apb_timer_of.c, but then it seems like much
> of drivers/clocksource/dw_apb_timer_of.c is actually ARM specific.

dw_apb_timer_of.c ... it should not be arm specific. Yes, it was
originally separated from picoxcell code, and so far only picoxcell &
socfpga use it, but it should work on other architectures, too..

> Are there any plans to clean this up in the future?

I can try, but I'd need a bit better idea what needs to be done. Would
"use this clocksource for sched_clock()" helper be acceptable?

> But I've gone ahead and queued this for 3.11.

Thanks!
								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From nicolas.pitre at linaro.org  Fri May 10 08:41:38 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 10 May 2013 08:41:38 -0400 (EDT)
Subject: [PATCH 1/1] ARM: mcpm: Fix build error with gic_secondary_init
 call
In-Reply-To: <1368166526-12525-1-git-send-email-sachin.kamat@linaro.org>
References: <1368166526-12525-1-git-send-email-sachin.kamat@linaro.org>
Message-ID: <alpine.LFD.2.03.1305100840390.13109@syhkavp.arg>

On Fri, 10 May 2013, Sachin Kamat wrote:

> Commit c0114709ed ("irqchip: gic: Perform the gic_secondary_init()
> call via CPU notifier") removed all platform calls to gic_secondary_init.
> Since this file got merged after the removal of the above call, this
> function got left out in the current file which is causing the following
> build error:
> arch/arm/common/mcpm_platsmp.c:52:2: error: implicit declaration of function
> ?gic_secondary_init? [-Werror=implicit-function-declaration]
> gic_secondary_init(0);
> 
> Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Nicolas Pitre <nico at linaro.org>

I already submitted a patch to fix this:
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7715/1


Nicolas

From james.hogan at imgtec.com  Fri May 10 08:44:22 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 13:44:22 +0100
Subject: [PATCH] clk: add specified-rate clock
Message-ID: <1368189862-17119-1-git-send-email-james.hogan@imgtec.com>

The frequency of some SoC's external oscillators (for example TZ1090's
XTAL1) are configured by the board using pull-ups/pull-downs of
configuration pins, the logic values of which are automatically latched
on reset and available in an SoC register. Add a generic clock component
and DT bindings to handle this.

It behaves similar to a fixed rate clock (read-only), except it needs
information about a register field (reg, shift, width), and the
clock-frequency is a mapping from register field values to clock
frequencies.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Lars-Peter Clausen <lars at metafoo.de>
---
 .../devicetree/bindings/clock/specified-clock.txt  |  39 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-specified-rate.c                   | 201 +++++++++++++++++++++
 include/linux/clk-provider.h                       |  37 ++++
 4 files changed, 278 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/specified-clock.txt
 create mode 100644 drivers/clk/clk-specified-rate.c

diff --git a/Documentation/devicetree/bindings/clock/specified-clock.txt b/Documentation/devicetree/bindings/clock/specified-clock.txt
new file mode 100644
index 0000000..b36ccf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/specified-clock.txt
@@ -0,0 +1,39 @@
+Binding for fixed-rate clock sources with readable configuration.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : Shall be "specified-clock".
+- #clock-cells       : From common clock binding; shall be set to 0.
+- reg                : Address of configuration register.
+- shift              : Shift of config value field in configuration register.
+- width              : Width of config value field in configuration register.
+- clock-frequency    : Frequency mapping of clock. Consecutive pairs of cells
+                       represent the config value to match and the clock
+                       frequency in Hz for that config value.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+	clock {
+		compatible = "specified-clock";
+		#clock-cells = <0>;
+		reg = <0x02004004 0x4>;	/* CR_PERIP_RESET_CFG */
+		shift = <8>;		/* FXTAL */
+		width = <4>;
+		clock-frequency =
+		/*	 FXTAL	Frequency */
+			<0	16384000>,
+			<1	19200000>,
+			<2	24000000>,
+			<3	24576000>,
+			<4	26000000>,
+			<5	36000000>,
+			<6	36864000>,
+			<7	38400000>,
+			<8	40000000>;
+		clock-output-names = "xtal1";
+	};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e7f7fe9..1343179 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-specified-rate.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
diff --git a/drivers/clk/clk-specified-rate.c b/drivers/clk/clk-specified-rate.c
new file mode 100644
index 0000000..8f78033
--- /dev/null
+++ b/drivers/clk/clk-specified-rate.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Fixed rate clock implementation with rate specified in a register field.
+ * Based on fixed rate clock implementation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+/*
+ * DOC: basic specified-rate clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parents are prepared
+ * enable - clk_enable only ensures parents are enabled
+ * rate - rate is always a fixed value.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_specified_rate(_hw) \
+	container_of(_hw, struct clk_specified_rate, hw)
+
+static unsigned long clk_specified_rate_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_specified_rate *specified = to_clk_specified_rate(hw);
+	struct clk_specified_rate_entry *entry;
+	u32 val;
+	unsigned int i;
+
+	/* read configuration field */
+	val = readl(specified->reg);
+	val >>= specified->shift;
+	val &= (1 << specified->width) - 1;
+
+	/* match the value in the mapping */
+	for (i = 0; i < specified->num_rates; ++i) {
+		entry = &specified->rates[i];
+		if (val == entry->value)
+			return entry->rate;
+	}
+
+	/* unknown rate! */
+	return 0;
+}
+
+const struct clk_ops clk_specified_rate_ops = {
+	.recalc_rate = clk_specified_rate_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_specified_rate_ops);
+
+/**
+ * clk_register_specified_rate - register specified-rate clock
+ * @dev:		device that is registering this clock
+ * @name:		name of this clock
+ * @parent_name:	name of clock's parent
+ * @flags:		framework-specific flags
+ * @reg:		config register
+ * @shift:		shift into config register of frequency field
+ * @width:		width of frequency field in config register
+ * @rates:		value->rate mapping entries
+ * @num_rates:		number of rates in @rates
+ */
+struct clk *clk_register_specified_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		struct clk_specified_rate_entry *rates,
+		unsigned long num_rates)
+{
+	struct clk_specified_rate *specified;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate specified-rate clock */
+	specified = kzalloc(sizeof(struct clk_specified_rate), GFP_KERNEL);
+	if (!specified) {
+		pr_err("%s(%s): could not allocate specified clk\n",
+		       __func__, name);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &clk_specified_rate_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	/* struct clk_specified_rate assignments */
+	specified->reg = reg;
+	specified->shift = shift;
+	specified->width = width;
+	specified->rates = rates;
+	specified->num_rates = num_rates;
+	specified->hw.init = &init;
+
+	/* register the clock */
+	clk = clk_register(dev, &specified->hw);
+
+	if (IS_ERR(clk))
+		kfree(specified);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+/**
+ * of_specified_clk_setup() - Setup function for specified fixed rate clock
+ */
+void __init of_specified_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	u32 shift, width, rate;
+	void __iomem *reg;
+	int len, num_rates, i;
+	struct property *prop;
+	struct clk_specified_rate_entry *rates;
+	const __be32 *p;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	if (of_property_read_u32(node, "shift", &shift)) {
+		pr_err("%s(%s): could not read shift property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "width", &width)) {
+		pr_err("%s(%s): could not read width property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s(%s): of_iomap failed\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	/* check clock-frequency exists */
+	prop = of_find_property(node, "clock-frequency", &len);
+	if (!prop) {
+		pr_err("%s(%s): could not find clock-frequency property\n",
+		       __func__, clk_name);
+		goto err_iounmap;
+	}
+
+	if (len & (sizeof(u32)*2 - 1)) {
+		pr_err("%s(%s): clock-frequency has invalid size of %d bytes\n",
+		       __func__, clk_name, len);
+		goto err_iounmap;
+	}
+	num_rates = len / (sizeof(*rates)*2);
+
+	rates = kzalloc(sizeof(*rates)*num_rates, GFP_KERNEL);
+	if (!rates) {
+		pr_err("%s(%s): could not allocate %d rate mapping entries\n",
+		       __func__, clk_name, num_rates);
+		goto err_iounmap;
+	}
+
+	/* extract rate mapping */
+	for (i = 0, p = of_prop_next_u32(prop, NULL, &rates[0].value);
+	     p;
+	     ++i, p = of_prop_next_u32(prop, p, &rates[i].value)) {
+		p = of_prop_next_u32(prop, p, &rate);
+		rates[i].rate = rate;
+		pr_debug("%s(%s): map %u -> %lu Hz\n",
+			 __func__, clk_name, rates[i].value, rates[i].rate);
+	}
+
+	clk = clk_register_specified_rate(NULL, clk_name, NULL, CLK_IS_ROOT,
+					  reg, shift, width, rates, num_rates);
+	if (IS_ERR(clk))
+		goto err_kfree;
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+
+err_kfree:
+	kfree(rates);
+err_iounmap:
+	iounmap(reg);
+}
+EXPORT_SYMBOL_GPL(of_specified_clk_setup);
+CLK_OF_DECLARE(specified_clk, "specified-clock", of_specified_clk_setup);
+#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1186098..218a406 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -196,6 +196,43 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 void of_fixed_clk_setup(struct device_node *np);
 
 /**
+ * struct clk_specified_rate_entry - a single possible specified rate
+ * @value:	value to match in config register
+ * @rate:	rate to use when config register matches @value
+ */
+struct clk_specified_rate_entry {
+	u32		value;
+	unsigned long	rate;
+};
+
+/**
+ * struct clk_specified_rate - specified-rate clock
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register containing rate specifier field
+ * @shift:	shift to rate specifier field
+ * @width:	width of rate specifier field
+ * @rates:	mapping of specified frequencies
+ * @num_rates:	number of rates in array
+ */
+struct clk_specified_rate {
+	struct		clk_hw hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	struct clk_specified_rate_entry	*rates;
+	unsigned int	num_rates;
+};
+
+extern const struct clk_ops clk_specified_rate_ops;
+struct clk *clk_register_specified_rate(struct device *dev, const char *name,
+		const char *parent_names, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		struct clk_specified_rate_entry *rates,
+		unsigned long num_rates);
+
+void of_specified_clk_setup(struct device_node *np);
+
+/**
  * struct clk_gate - gating clock
  *
  * @hw:		handle between common and hardware-specific interfaces
-- 
1.8.1.2




From srinivas.kandagatla at st.com  Fri May 10 08:51:14 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 10 May 2013 13:51:14 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <20130509095143.GB7478@sirena.org.uk>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022272-2241-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081650.23264.arnd@arndb.de>
 <20130508150141.GA5057@opensource.wolfsonmicro.com> <518A8E6C.6070907@st.com>
 <20130509095143.GB7478@sirena.org.uk>
Message-ID: <518CED42.7010700@st.com>

Hi Marc,

I would like to explain you bit more about "ST System Configuration
registers".

The SOCs are assembled from existing IP blocks, which don't change very
often. However these blocks are assembled in different configurations to
meet the device requirements. So most IP blocks as well as having a bus
interface through which their own registers are accessible, will also
have a number of bristles(wires) which are signals that are going in and
out of the IP for configuration and status. To make these signals
accessible to software they are wired to "System Configuration Registers".

Drivers target the IP blocks, which don't change much. Where as the
mapping of IP specific bristles(wires) to "System Configuration
Registers" do change per each SOC, and therefore we do not want this
information to be part of the driver.

Having a System Configuration infrastructure gives much flexibility and
abstraction to drivers to configure them.

Given the comments on the patch, I am inclined not to use syscon for ST
specific "System Configuration Registers", alternatively I would like to
create a separate mfd system configuration driver specific to ST.

This is how we did it initially in the out-of-tree kernel.
http://git.stlinux.com/?p=stm/linux-stm.git;a=blob;f=drivers/stm/sysconf.c

Any suggestions?


thanks,
srini

On 09/05/13 10:51, Mark Brown wrote:
> On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
> 
> Fix your mailer to word wrap within paragraphs.
> 
>> Ultimately the syscon_write use the regmap_update_bits, however we
>> really want is the flexibility in using/referring the syscon
>> registers/bits in both device-trees and non-device tree cases.
> 
> So what you're looking for here is some way to offload discovery of
> register fields from the driver?
> 
>> The reason for these APIs, is the extent of syscon usage is very high
>> in ST set-top-box parts.
> 
>> Without these new APIs, its very difficult to pass this information to
>> the drivers.
> 
> I'm not 100% convinced that putting all this information into DT is a
> good idea, and to the extent that it is sensible it feels like something
> which might be useful with any device using register maps, not just
> syscon.  For example many MFDs have similar needs - essentially the
> system controllers are just a particular kind of MFD.  To me that says
> that this should be outside syscon so other things can use it.
> 



From nicolas.ferre at atmel.com  Fri May 10 09:19:13 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 15:19:13 +0200
Subject: [PATCH 1/3] dmaengine: at_hdmac/trivial: correct typo in comment
Message-ID: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/dma/at_hdmac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index e923cda..cd49420 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -1120,7 +1120,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
 		 */
 		BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
 
-		/* if cfg configuration specified take it instad of default */
+		/* if cfg configuration specified take it instead of default */
 		if (atslave->cfg)
 			cfg = atslave->cfg;
 	}
-- 
1.8.0



From nicolas.ferre at atmel.com  Fri May 10 09:19:14 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 15:19:14 +0200
Subject: [PATCH 2/3] dmaengine: at_hdmac: extend hardware handshaking
 interface identification
In-Reply-To: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>
References: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>
Message-ID: <136a15966daabbb99360411f225adc14fcc763f3.1368191734.git.nicolas.ferre@atmel.com>

Peripheral handshaking identification numbers can be bigger than 15, so new
fields have been created in the CFG register.
Add macros to take this modification into account and use them in
at_dma_xlate() function.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/dma/at_hdmac.c                  | 2 ++
 include/linux/platform_data/dma-atmel.h | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index cd49420..78c3fb4 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -1230,6 +1230,8 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
 	per_id = dma_spec->args[1];
 	atslave->cfg = ATC_FIFOCFG_HALFFIFO | ATC_DST_H2SEL_HW
 		      | ATC_SRC_H2SEL_HW | ATC_DST_PER(per_id)
+		      | ATC_DST_PER_MSB(per_id)
+		      | ATC_SRC_PER_MSB(per_id)
 		      | ATC_SRC_PER(per_id);
 	atslave->dma_dev = &dmac_pdev->dev;
 
diff --git a/include/linux/platform_data/dma-atmel.h b/include/linux/platform_data/dma-atmel.h
index cab0997..e95f19c 100644
--- a/include/linux/platform_data/dma-atmel.h
+++ b/include/linux/platform_data/dma-atmel.h
@@ -35,16 +35,20 @@ struct at_dma_slave {
 
 
 /* Platform-configurable bits in CFG */
+#define ATC_PER_MSB(h)	((0x30U & (h)) >> 4)	/* Extract most significant bits of a handshaking identifier */
+
 #define	ATC_SRC_PER(h)		(0xFU & (h))	/* Channel src rq associated with periph handshaking ifc h */
 #define	ATC_DST_PER(h)		((0xFU & (h)) <<  4)	/* Channel dst rq associated with periph handshaking ifc h */
 #define	ATC_SRC_REP		(0x1 <<  8)	/* Source Replay Mod */
 #define	ATC_SRC_H2SEL		(0x1 <<  9)	/* Source Handshaking Mod */
 #define		ATC_SRC_H2SEL_SW	(0x0 <<  9)
 #define		ATC_SRC_H2SEL_HW	(0x1 <<  9)
+#define	ATC_SRC_PER_MSB(h)	(ATC_PER_MSB(h) << 10)	/* Channel src rq (most significant bits) */
 #define	ATC_DST_REP		(0x1 << 12)	/* Destination Replay Mod */
 #define	ATC_DST_H2SEL		(0x1 << 13)	/* Destination Handshaking Mod */
 #define		ATC_DST_H2SEL_SW	(0x0 << 13)
 #define		ATC_DST_H2SEL_HW	(0x1 << 13)
+#define	ATC_DST_PER_MSB(h)	(ATC_PER_MSB(h) << 14)	/* Channel dst rq (most significant bits) */
 #define	ATC_SOD			(0x1 << 16)	/* Stop On Done */
 #define	ATC_LOCK_IF		(0x1 << 20)	/* Interface Lock */
 #define	ATC_LOCK_B		(0x1 << 21)	/* AHB Bus Lock */
-- 
1.8.0



From nicolas.ferre at atmel.com  Fri May 10 09:19:15 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 May 2013 15:19:15 +0200
Subject: [PATCH 3/3] dmaengine: at_hdmac/trivial: rearrange CFG register bits
 assignment
In-Reply-To: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>
References: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>
Message-ID: <c188abd0dbab3af0789d6d35ac37a5402f4b808d.1368191734.git.nicolas.ferre@atmel.com>

No modification in CFG register configuration, just rearrange
bits directives to group logically and make it more readable.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/dma/at_hdmac.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 78c3fb4..9e1ad73 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -1228,11 +1228,10 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
 	 * ignored depending on DMA transfer direction.
 	 */
 	per_id = dma_spec->args[1];
-	atslave->cfg = ATC_FIFOCFG_HALFFIFO | ATC_DST_H2SEL_HW
-		      | ATC_SRC_H2SEL_HW | ATC_DST_PER(per_id)
-		      | ATC_DST_PER_MSB(per_id)
-		      | ATC_SRC_PER_MSB(per_id)
-		      | ATC_SRC_PER(per_id);
+	atslave->cfg = ATC_FIFOCFG_HALFFIFO
+		     | ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW
+		     | ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id)
+		     | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id);
 	atslave->dma_dev = &dmac_pdev->dev;
 
 	chan = dma_request_channel(mask, at_dma_filter, atslave);
-- 
1.8.0



From nm at ti.com  Fri May 10 10:02:00 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 10 May 2013 09:02:00 -0500
Subject: [PATCH v2 0/6] ARM; OMAP2+: hwmod and SERIAL: Remove sysc
 handling from driver
In-Reply-To: <87ppxhxixu.fsf@linaro.org>
References: <1366973695-2088-1-git-send-email-rnayak@ti.com>
 <87ppxhxixu.fsf@linaro.org>
Message-ID: <20130510140200.GA11267@kahuna>

On 11:09-20130426, Kevin Hilman wrote:
> Rajendra Nayak <rnayak at ti.com> writes:
> 
> [...]
> 
> > OMAP UART IP needs manual idle modes based on functional state of the
> > IP. Currently this is handled by the driver with function pointers
> > implemented in platform code.
> >
> > This however breaks in case of device tree because of missing
> > idle handling. 
> >
> > The series tries to address the issue and tries to remove complete
> > sysc handling from serial driver.
> 
> Other than the minor nit about the order of the series for bisect, 
> 
> Reviewed-by: Kevin Hilman <khilman at linaro.org>
> 
> Also tested this on OMAP4/Panda where I was having the sluggish console
> issues using DT boot, and and can confirm that this fixes the problem:
> 
> Tested-by: Kevin Hilman <khilman at linaro.org>  # OMAP4/Panda
> 
I saw the same let of console sluggishness on SDP4430, Panda, Panda-ES
as well on latest linus master.

For reference, I have rebased the series to latest master and fixes the
sequencing:
https://github.com/nmenon/linux-2.6-playground/commits/push/uart-fixes-sidle-3.10
based on:
master 70eba42 Merge tag 'please-pull-pstore' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux

Rajendra,
Would you be able to repost this series so that we can get this into
3.10-rc2+?

-- 
Regards,
Nishanth Menon


From thomas.petazzoni at free-electrons.com  Fri May 10 10:17:10 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 10 May 2013 16:17:10 +0200
Subject: [PATCH 3/3] ARM: versatile: Make able to use UART ports for
 KGDB FIQ debugger
In-Reply-To: <1368144651-11250-4-git-send-email-john.stultz@linaro.org>
References: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
 <1368144651-11250-4-git-send-email-john.stultz@linaro.org>
Message-ID: <20130510161710.45b18866@skate>

Dear John Stultz,

On Thu,  9 May 2013 17:10:51 -0700, John Stultz wrote:

> +static void kgdb_fiq_select(bool on)
> +{
> +	void __iomem *sel = kgdb_irq_base + VIC_INT_SELECT;
> +	u32 msk = 1 << kgdb_irq;
> +	u32 val;
> +
> +	pr_debug("rerouting VIC vector %d to %s\n", kgdb_irq,
> +		 on ? "FIQ" : "IRQ");
> +
> +	val = readl(sel);
> +	val &= ~msk;
> +	if (on)
> +		val |= msk;
> +	writel(val, sel);
> +}
> +
> +static bool kgdb_is_fiq_rised(void)

Shouldn't this function be kgdb_is_fiq_raised() ?

> +{
> +	return readl(kgdb_irq_base + VIC_FIQ_STATUS) & (1 << kgdb_irq);
> +}
> +
> +static int __init kgdb_fiq_init(void)
> +{
> +	kgdb_irq_base = __io_address(VERSATILE_VIC_BASE);
> +	kgdb_irq += INT_UARTINT0;
> +	WARN_ON(kgdb_irq > INT_UARTINT2);
> +
> +	return kgdb_register_fiq(kgdb_fiq_select, kgdb_is_fiq_rised);
> +}
> +console_initcall(kgdb_fiq_init);

Also, this code that uses hardcoded addresses and IRQ numbers doesn't
seem to play really well with the DT. I was considering toying around
with this thing on the mach-mvebu platform, but don't have those
hardcoded addresses and IRQs, and the register offsets of the IRQ
controller driver are not exposed in an header file. Shouldn't IRQ
controller driver be exposing a the fiq_select() functionality instead?
Like a new flag for irq_chip->irq_set_type(), or a completely new hook
irq_chip->irq_set_mode() or something like that?

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From plagnioj at jcrosoft.com  Fri May 10 10:20:02 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 16:20:02 +0200
Subject: [PATCH 1/3] dmaengine: at_hdmac/trivial: correct typo in comment
In-Reply-To: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>
References: <042cac60509755c1340d141315a9a8eb1965438a.1368191734.git.nicolas.ferre@atmel.com>
Message-ID: <20130510142002.GL3041@game.jcrosoft.org>

on all

Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

On 15:19 Fri 10 May     , Nicolas Ferre wrote:
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
>  drivers/dma/at_hdmac.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
> index e923cda..cd49420 100644
> --- a/drivers/dma/at_hdmac.c
> +++ b/drivers/dma/at_hdmac.c
> @@ -1120,7 +1120,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
>  		 */
>  		BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
>  
> -		/* if cfg configuration specified take it instad of default */
> +		/* if cfg configuration specified take it instead of default */
>  		if (atslave->cfg)
>  			cfg = atslave->cfg;
>  	}
> -- 
> 1.8.0
> 


From plagnioj at jcrosoft.com  Fri May 10 10:30:34 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 16:30:34 +0200
Subject: [RFC 18/42] drivers/pinctrl: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-19-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-19-git-send-email-wsa@the-dreams.de>
Message-ID: <20130510143034.GA22508@game.jcrosoft.org>

On 10:17 Fri 10 May     , Wolfram Sang wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
> 
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
> ---
>  drivers/pinctrl/pinctrl-at91.c       |    7 +------
for at91
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

>  drivers/pinctrl/pinctrl-coh901.c     |    5 -----
>  drivers/pinctrl/pinctrl-exynos5440.c |    5 -----
>  drivers/pinctrl/pinctrl-samsung.c    |    5 -----
>  drivers/pinctrl/pinctrl-xway.c       |    4 ----
>  5 files changed, 1 insertion(+), 25 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 5d7529e..b90a3a0 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -1543,12 +1543,6 @@ static int at91_gpio_probe(struct platform_device *pdev)
>  		goto err;
>  	}
>  
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		ret = -ENOENT;
> -		goto err;
> -	}
> -
>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0) {
>  		ret = irq;
> @@ -1561,6 +1555,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
>  		goto err;
>  	}
>  
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(at91_chip->regbase)) {
>  		ret = PTR_ERR(at91_chip->regbase);
> diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
> index edde3ac..a67af41 100644
> --- a/drivers/pinctrl/pinctrl-coh901.c
> +++ b/drivers/pinctrl/pinctrl-coh901.c
> @@ -713,11 +713,6 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
>  	gpio->dev = &pdev->dev;
>  
>  	memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!memres) {
> -		dev_err(gpio->dev, "could not get GPIO memory resource\n");
> -		return -ENODEV;
> -	}
> -
>  	gpio->base = devm_ioremap_resource(&pdev->dev, memres);
>  	if (IS_ERR(gpio->base))
>  		return PTR_ERR(gpio->base);
> diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
> index 6038503..32a48f4 100644
> --- a/drivers/pinctrl/pinctrl-exynos5440.c
> +++ b/drivers/pinctrl/pinctrl-exynos5440.c
> @@ -1000,11 +1000,6 @@ static int exynos5440_pinctrl_probe(struct platform_device *pdev)
>  	}
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(dev, "cannot find IO resource\n");
> -		return -ENOENT;
> -	}
> -
>  	priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(priv->reg_base))
>  		return PTR_ERR(priv->reg_base);
> diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
> index 9763668..055d016 100644
> --- a/drivers/pinctrl/pinctrl-samsung.c
> +++ b/drivers/pinctrl/pinctrl-samsung.c
> @@ -932,11 +932,6 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
>  	drvdata->dev = dev;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(dev, "cannot find IO resource\n");
> -		return -ENOENT;
> -	}
> -
>  	drvdata->virt_base = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(drvdata->virt_base))
>  		return PTR_ERR(drvdata->virt_base);
> diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
> index f2977cf..e92132c 100644
> --- a/drivers/pinctrl/pinctrl-xway.c
> +++ b/drivers/pinctrl/pinctrl-xway.c
> @@ -716,10 +716,6 @@ static int pinmux_xway_probe(struct platform_device *pdev)
>  
>  	/* get and remap our register range */
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(&pdev->dev, "Failed to get resource\n");
> -		return -ENOENT;
> -	}
>  	xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(xway_info.membase[0]))
>  		return PTR_ERR(xway_info.membase[0]);
> -- 
> 1.7.10.4
> 


From gxt at mprc.pku.edu.cn  Fri May 10 11:05:21 2013
From: gxt at mprc.pku.edu.cn (Xuetao Guan)
Date: Fri, 10 May 2013 23:05:21 +0800 (CST)
Subject: [PATCH -v9 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368127405-112717-8-git-send-email-holt@sgi.com>
References: <1368127405-112717-1-git-send-email-holt@sgi.com>
 <1368127405-112717-8-git-send-email-holt@sgi.com>
Message-ID: <53078.128.237.228.195.1368198321.squirrel@mprc.pku.edu.cn>

> This patch prepares for the moving the parsing of reboot= to the generic
> kernel code by making reboot_mode into a more generic form.
>
> Signed-off-by: Robin Holt <holt at sgi.com>
> To: Andrew Morton <akpm at linux-foundation.org>
> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
> Cc: Russ Anderson <rja at sgi.com>
> Cc: Robin Holt <holt at sgi.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: H. Peter Anvin <hpa at zytor.com>
> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
> Cc: the arch/x86 maintainers <x86 at kernel.org>
> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

Thanks for your hard work.

For UniCore32 bits: (Though I can't compile and test it in recent months)
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>


>
> ---
>
> Changes since -v8
>  - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
> ---
>  arch/unicore32/kernel/process.c | 10 +++++-----
>  arch/unicore32/kernel/setup.h   |  2 +-
>  arch/unicore32/mm/mmu.c         |  2 +-
>  include/linux/reboot.h          |  2 ++
>  4 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/unicore32/kernel/process.c
> b/arch/unicore32/kernel/process.c
> index c944769..93dd035 100644
> --- a/arch/unicore32/kernel/process.c
> +++ b/arch/unicore32/kernel/process.c
> @@ -51,14 +51,14 @@ void arch_cpu_idle(void)
>  	local_irq_enable();
>  }
>
> -static char reboot_mode = 'h';
> +static enum reboot_mode reboot_mode = REBOOT_HARD;
>
>  int __init reboot_setup(char *str)
>  {
> -	reboot_mode = str[0];
> +	if ('s' == str[0])
> +		reboot_mode = REBOOT_SOFT;
>  	return 1;
>  }
> -
>  __setup("reboot=", reboot_setup);
>
>  void machine_halt(void)
> @@ -88,7 +88,7 @@ void machine_restart(char *cmd)
>  	 * we may need it to insert some 1:1 mappings so that
>  	 * soft boot works.
>  	 */
> -	setup_mm_for_reboot(reboot_mode);
> +	setup_mm_for_reboot();
>
>  	/* Clean and invalidate caches */
>  	flush_cache_all();
> @@ -102,7 +102,7 @@ void machine_restart(char *cmd)
>  	/*
>  	 * Now handle reboot code.
>  	 */
> -	if (reboot_mode == 's') {
> +	if (reboot_mode == REBOOT_SOFT) {
>  		/* Jump into ROM at address 0xffff0000 */
>  		cpu_reset(VECTORS_BASE);
>  	} else {
> diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
> index 30f749d..f5c51b8 100644
> --- a/arch/unicore32/kernel/setup.h
> +++ b/arch/unicore32/kernel/setup.h
> @@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
>  extern void pci_puv3_preinit(void);
>  extern void __init puv3_init_gpio(void);
>
> -extern void setup_mm_for_reboot(char mode);
> +extern void setup_mm_for_reboot(void);
>
>  extern char __stubs_start[], __stubs_end[];
>  extern char __vectors_start[], __vectors_end[];
> diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
> index 43c20b4..4f5a532 100644
> --- a/arch/unicore32/mm/mmu.c
> +++ b/arch/unicore32/mm/mmu.c
> @@ -445,7 +445,7 @@ void __init paging_init(void)
>   * the user-mode pages.  This will then ensure that we have predictable
>   * results when turning the mmu off
>   */
> -void setup_mm_for_reboot(char mode)
> +void setup_mm_for_reboot(void)
>  {
>  	unsigned long base_pmdval;
>  	pgd_t *pgd;
> diff --git a/include/linux/reboot.h b/include/linux/reboot.h
> index 37d56c3..ca29a6f 100644
> --- a/include/linux/reboot.h
> +++ b/include/linux/reboot.h
> @@ -13,6 +13,8 @@
>  enum reboot_mode {
>  	REBOOT_COLD = 0,
>  	REBOOT_WARM,
> +	REBOOT_HARD,
> +	REBOOT_SOFT,
>  };
>
>  extern int register_reboot_notifier(struct notifier_block *);
> --
> 1.8.2.1
>



From plagnioj at jcrosoft.com  Fri May 10 10:34:04 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 16:34:04 +0200
Subject: [PATCH] ARM: at91: dts: request only spi cs-gpios used on
 sama5d3x cpu module
In-Reply-To: <1368181807-15182-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368181807-15182-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20130510143404.GB22508@game.jcrosoft.org>

On 12:30 Fri 10 May     , Nicolas Ferre wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Instead of requesting all available spi cs-gpios, request only the ones used on
> the board, in our case on the cpu module.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Best Regards,
J.
> ---
>  arch/arm/boot/dts/sama5d3.dtsi    | 10 ----------
>  arch/arm/boot/dts/sama5d3xcm.dtsi |  4 ++++
>  2 files changed, 4 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
> index 2e643ea..dee5e2f 100644
> --- a/arch/arm/boot/dts/sama5d3.dtsi
> +++ b/arch/arm/boot/dts/sama5d3.dtsi
> @@ -75,11 +75,6 @@
>  				compatible = "atmel,at91sam9x5-spi";
>  				reg = <0xf0004000 0x100>;
>  				interrupts = <24 4 3>;
> -				cs-gpios = <&pioD 13 0
> -					    &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
> -					    &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
> -					    &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
> -					   >;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&pinctrl_spi0>;
>  				status = "disabled";
> @@ -203,11 +198,6 @@
>  				compatible = "atmel,at91sam9x5-spi";
>  				reg = <0xf8008000 0x100>;
>  				interrupts = <25 4 3>;
> -				cs-gpios = <&pioC 25 0
> -					    &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
> -					    &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
> -					    &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
> -					   >;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&pinctrl_spi1>;
>  				status = "disabled";
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index 1f8ed40..b336e77 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -32,6 +32,10 @@
>  
>  	ahb {
>  		apb {
> +			spi0: spi at f0004000 {
> +				cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
> +			};
> +
>  			macb0: ethernet at f0028000 {
>  				phy-mode = "rgmii";
>  			};
> -- 
> 1.8.0
> 


From plagnioj at jcrosoft.com  Fri May 10 10:37:01 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 May 2013 16:37:01 +0200
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <518CA1DF.5050008@broadcom.com>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
 <20130509063503.GF3041@game.jcrosoft.org>
 <518CA1DF.5050008@broadcom.com>
Message-ID: <20130510143701.GC22508@game.jcrosoft.org>

On 00:29 Fri 10 May     , Christian Daudt wrote:
> Thanks for the feedback.
> 
> On 13-05-08 11:35 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >On 22:55 Wed 08 May     , Christian Daudt wrote:
> >>Add SDHCI driver for the Broadcom 281xx SoCs. Also
> >>add bindings for it into bcm281xx dts files.
> >>Still missing:
> >>  - power managemement
> >split the dts/dtsi in an other patch
> ok.
> >>Signed-off-by: Christian Daudt <csd at broadcom.com>
> >>
> >>diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
> >>index e3bf2d6..65edf6d 100644
> >>--- a/arch/arm/configs/bcm_defconfig
> >>+++ b/arch/arm/configs/bcm_defconfig
> >>@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
> >>  CONFIG_LCD_CLASS_DEVICE=y
> >>  CONFIG_BACKLIGHT_CLASS_DEVICE=y
> >>  # CONFIG_USB_SUPPORT is not set
> >>+CONFIG_MMC=y
> >>+CONFIG_MMC_UNSAFE_RESUME=y
> >>+CONFIG_MMC_BLOCK_MINORS=32
> >>+CONFIG_MMC_TEST=y
> >>+CONFIG_MMC_SDHCI=y
> >>+CONFIG_MMC_SDHCI_PLTFM=y
> >>+CONFIG_MMC_SDHCI_BCM_KONA=y
> >>  CONFIG_NEW_LEDS=y
> >>  CONFIG_LEDS_CLASS=y
> >>  CONFIG_LEDS_TRIGGERS=y
> >>diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> >>index d88219e..e067c5a 100644
> >>--- a/drivers/mmc/host/Kconfig
> >>+++ b/drivers/mmc/host/Kconfig
> >>@@ -238,6 +238,16 @@ config MMC_SDHCI_S3C_DMA
> >>  	  YMMV.
> >>+config MMC_SDHCI_BCM_KONA
> >>+	tristate "SDHCI support on Broadcom KONA platform"
> >>+	depends on ARCH_BCM && MMC_SDHCI_PLTFM
> >select MMC_SDHCI_PLTFM
> >will be better
> Ok - changed it. Why is the select is better than the depends ?

so you do not need to enable MMC_SDHCI_PLTFM

and you can drop one line in the savdefconfig

if tomorrow you need regulator select it so a old defconfig will continue to
work

Best Regards,
J.


From ben.dooks at codethink.co.uk  Fri May 10 10:45:15 2013
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Fri, 10 May 2013 16:45:15 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508153459.GA17186@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de> <20130508153459.GA17186@kroah.com>
Message-ID: <518D07FB.7010606@codethink.co.uk>

On 08/05/13 17:34, Greg KH wrote:
> On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
>>> +#define ASC_MAJOR		204
>>> +#define ASC_MINOR_START		40
>>
>> I don't know what the current policy is on allocating major/minor numbers,
>> but I'm sure you cannot just reuse one that is already used.
>
> I agree, why are you trying to create a new tty device name?  Can't you
> use the existing ttyS name and minor number as you will not have any
> other type of serial device on this system?

This would be an issue on systems that either accept plug-in cards
such as PCMCIA/CardBus/PCI or have additional off SoC IO spaces
where 8250 compatible UARTS could live.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius


From james.hogan at imgtec.com  Fri May 10 11:02:02 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:02:02 +0100
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
Message-ID: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>

This adds a metag architecture specific clk-gate and clk-mux which
extends the generic ones to use global lock2 to protect the register
fields. It is common with metag to have an RTOS running on a different
thread or core with access to different bits in the same register (which
contain clock gate/switch bits for other clocks). Access to such
registers must be serialised with a global lock such as the one provided
by the metag architecture port in <asm/global_lock.h>

RFC because despite extending the generic clocks there's still a bit of
duplicated code necessary. One alternative is to add special cases to
the generic clock components for when a global or callback function
based lock is desired instead of a spinlock, but I wasn't sure if that
sort of hack would really be appreciated in the generic drivers.

Comments?

James Hogan (2):
  clk: metag/clk-gate: add metag specific clock gate
  clk: metag/clk-mux: add metag specific clk-mux

 .../bindings/clock/img,meta-gate-clock.txt         |  28 +++
 .../bindings/clock/img,meta-mux-clock.txt          |  33 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/metag/Makefile                         |   3 +
 drivers/clk/metag/clk-gate.c                       | 179 +++++++++++++++++
 drivers/clk/metag/clk-mux.c                        | 211 +++++++++++++++++++++
 6 files changed, 455 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
 create mode 100644 drivers/clk/metag/Makefile
 create mode 100644 drivers/clk/metag/clk-gate.c
 create mode 100644 drivers/clk/metag/clk-mux.c

-- 
1.8.1.2




From james.hogan at imgtec.com  Fri May 10 11:02:03 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:02:03 +0100
Subject: [PATCH RFC 1/2] clk: metag/clk-gate: add metag specific clock gate
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368198127-1295-2-git-send-email-james.hogan@imgtec.com>

Add a metag architecture specific clk-gate which extends the generic one
to use global lock2 to protect the register fields. It is common with
metag to have an RTOS running on a different thread or core with access
to different bits in the same register (in this case clock gate bits for
other clocks). Access to such registers must be serialised with a global
lock such as the one provided by the metag architecture port in
<asm/global_lock.h>

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 .../bindings/clock/img,meta-gate-clock.txt         |  28 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/metag/Makefile                         |   2 +
 drivers/clk/metag/clk-gate.c                       | 179 +++++++++++++++++++++
 4 files changed, 210 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
 create mode 100644 drivers/clk/metag/Makefile
 create mode 100644 drivers/clk/metag/clk-gate.c

diff --git a/Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt b/Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
new file mode 100644
index 0000000..483097c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
@@ -0,0 +1,28 @@
+Binding for clock gate requiring global Meta locking.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : Shall be "img,meta-mux-clock".
+- #clock-cells       : From common clock binding; shall be set to 0.
+- reg                : Address of configuration register.
+- bit                : Bit number of gate switch in configuration register.
+- clocks             : From common clock binding.
+
+Required source clocks:
+- 0                  : Input clock that can be gated (doesn't have to be named).
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+	clock {
+		compatible = "img,meta-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&sys_clk>;
+		reg = <0x02004010 0x4>;
+		bit = <0>;
+		clock-output-names = "scb0";
+	};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e7f7fe9..a800077 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= clk-zynq.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 
+obj-$(CONFIG_METAG)		+= metag/
 obj-$(CONFIG_X86)		+= x86/
 
 # Chip specific
diff --git a/drivers/clk/metag/Makefile b/drivers/clk/metag/Makefile
new file mode 100644
index 0000000..8e9a6ac
--- /dev/null
+++ b/drivers/clk/metag/Makefile
@@ -0,0 +1,2 @@
+# metag clock types
+obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
diff --git a/drivers/clk/metag/clk-gate.c b/drivers/clk/metag/clk-gate.c
new file mode 100644
index 0000000..63da8d9
--- /dev/null
+++ b/drivers/clk/metag/clk-gate.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Metag gated clock implementation
+ * Based on gated clock implementation, but does appropriate locking to protect
+ * registers shared between hardware threads.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <asm/global_lock.h>
+
+/**
+ * struct clk_metag_gate - metag gating clock
+ *
+ * @mux:	the parent class
+ * @ops:	pointer to clk_ops of parent class
+ *
+ * Clock which can gate its output. Extends basic mux by using a global
+ * exclusive lock when read-modify-writing the mux field so that multiple
+ * threads/cores can use different fields in the same register.
+ */
+struct clk_metag_gate {
+	struct clk_gate		gate;
+	const struct clk_ops	*ops;
+};
+
+static inline struct clk_metag_gate *to_clk_metag_gate(struct clk_hw *hw)
+{
+	struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
+
+	return container_of(gate, struct clk_metag_gate, gate);
+}
+
+/* Acquire exclusive lock since other cores may access the same register */
+static int clk_metag_gate_enable(struct clk_hw *hw)
+{
+	struct clk_metag_gate *gate = to_clk_metag_gate(hw);
+	int ret;
+	unsigned long flags;
+
+	__global_lock2(flags);
+	ret = gate->ops->enable(&gate->gate.hw);
+	__global_unlock2(flags);
+
+	return ret;
+}
+
+/* Acquire exclusive lock since other cores may access the same register */
+static void clk_metag_gate_disable(struct clk_hw *hw)
+{
+	struct clk_metag_gate *gate = to_clk_metag_gate(hw);
+	unsigned long flags;
+
+	__global_lock2(flags);
+	gate->ops->disable(&gate->gate.hw);
+	__global_unlock2(flags);
+}
+
+static int clk_metag_gate_is_enabled(struct clk_hw *hw)
+{
+	struct clk_metag_gate *gate = to_clk_metag_gate(hw);
+
+	return gate->ops->is_enabled(&gate->gate.hw);
+}
+
+static const struct clk_ops clk_metag_gate_ops = {
+	.enable = clk_metag_gate_enable,
+	.disable = clk_metag_gate_disable,
+	.is_enabled = clk_metag_gate_is_enabled,
+};
+
+/**
+ * clk_register_metag_gate - register a Meta gate clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ */
+static struct clk *__init clk_register_metag_gate(struct device *dev,
+		const char *name, const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx, u8 clk_gate_flags)
+{
+	struct clk_metag_gate *gate;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the gate */
+	gate = kzalloc(sizeof(struct clk_metag_gate), GFP_KERNEL);
+	if (!gate) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &clk_metag_gate_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	/* struct clk_gate assignments */
+	gate->gate.reg = reg;
+	gate->gate.bit_idx = bit_idx;
+	gate->gate.flags = clk_gate_flags;
+	gate->gate.hw.init = &init;
+
+	/* struct clk_metag_gate assignments */
+	gate->ops = &clk_gate_ops;
+
+	clk = clk_register(dev, &gate->gate.hw);
+
+	if (IS_ERR(clk))
+		kfree(gate);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+/**
+ * of_metag_gate_clk_setup() - Setup function for simple fixed rate clock
+ */
+static void __init of_metag_gate_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	u32 bit_idx;
+	void __iomem *reg;
+	const char *parent_name;
+	u8 flags = 0;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	if (of_property_read_u32(node, "bit", &bit_idx)) {
+		pr_err("%s(%s): could not read bit property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	parent_name = of_clk_get_parent_name(node, 0);
+	if (!parent_name) {
+		pr_err("%s(%s): could not read parent clock\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s(%s): of_iomap failed\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	clk = clk_register_metag_gate(NULL, clk_name, parent_name,
+				      CLK_SET_RATE_PARENT, reg, bit_idx, flags);
+	if (IS_ERR(clk))
+		goto err_iounmap;
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+
+err_iounmap:
+	iounmap(reg);
+}
+CLK_OF_DECLARE(metag_gate_clk, "img,meta-gate-clock", of_metag_gate_clk_setup);
+#endif /* CONFIG_OF */
-- 
1.8.1.2




From james.hogan at imgtec.com  Fri May 10 11:02:05 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:02:05 +0100
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368198127-1295-4-git-send-email-james.hogan@imgtec.com>

This adds a metag architecture specific clk-gate and clk-mux which
extends the generic ones to use global lock2 to protect the register
fields. It is common with metag to have an RTOS running on a different
thread or core with access to different bits in the same register (which
contain clock gate/switch bits for other clocks). Access to such
registers must be serialised with a global lock such as the one provided
by the metag architecture port in <asm/global_lock.h>

RFC because despite extending the generic clocks there's still a bit of
duplicated code necessary. One alternative is to add special cases to
the generic clock components for when a global or callback function
based lock is desired instead of a spinlock, but I wasn't sure if that
sort of hack would really be appreciated in the generic drivers.

Comments?

James Hogan (2):
  clk: metag/clk-gate: add metag specific clock gate
  clk: metag/clk-mux: add metag specific clk-mux

 .../bindings/clock/img,meta-gate-clock.txt         |  28 +++
 .../bindings/clock/img,meta-mux-clock.txt          |  33 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/metag/Makefile                         |   3 +
 drivers/clk/metag/clk-gate.c                       | 179 +++++++++++++++++
 drivers/clk/metag/clk-mux.c                        | 211 +++++++++++++++++++++
 6 files changed, 455 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
 create mode 100644 drivers/clk/metag/Makefile
 create mode 100644 drivers/clk/metag/clk-gate.c
 create mode 100644 drivers/clk/metag/clk-mux.c

-- 
1.8.1.2




From james.hogan at imgtec.com  Fri May 10 11:02:04 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:02:04 +0100
Subject: [PATCH RFC 2/2] clk: metag/clk-mux: add metag specific clk-mux
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368198127-1295-3-git-send-email-james.hogan@imgtec.com>

Add a metag architecture specific clk-mux which extends the generic one
to use global lock2 to protect the register fields. It is common with
metag to have an RTOS running on a different thread or core with access
to different bits in the same register (in this case clock switch bits
for other clocks). Access to such registers must be serialised with a
global lock such as the one provided by the metag architecture port in
<asm/global_lock.h>

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 .../bindings/clock/img,meta-mux-clock.txt          |  33 ++++
 drivers/clk/metag/Makefile                         |   1 +
 drivers/clk/metag/clk-mux.c                        | 211 +++++++++++++++++++++
 3 files changed, 245 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
 create mode 100644 drivers/clk/metag/clk-mux.c

diff --git a/Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt b/Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
new file mode 100644
index 0000000..7802939
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
@@ -0,0 +1,33 @@
+Binding for clock multiplexer requiring global Meta locking.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : Shall be "img,meta-mux-clock".
+- #clock-cells       : From common clock binding; shall be set to 0.
+- reg                : Address of configuration register.
+- shift              : Shift of mux value field in configuration register.
+- width              : Width of mux value field in configuration register.
+- clocks             : From common clock binding.
+
+Required source clocks:
+- 0..(1<<width)-1    : Input clocks to multiplex (don't have to be named).
+
+Optional properties:
+- clock-output-names : From common clock binding.
+- default-clock      : Mux value to set initially.
+
+Example:
+	clock {
+		compatible = "img,meta-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&xtal1>,
+			 <&xtal2>;
+		reg = <0x02005908 0x4>;
+		shift = <0>;
+		width = <1>;
+		clock-output-names = "sysclk0_sw";
+		default-clock = <1>; /* default to xtal2 */
+	};
diff --git a/drivers/clk/metag/Makefile b/drivers/clk/metag/Makefile
index 8e9a6ac..c53ccb2 100644
--- a/drivers/clk/metag/Makefile
+++ b/drivers/clk/metag/Makefile
@@ -1,2 +1,3 @@
 # metag clock types
 obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
diff --git a/drivers/clk/metag/clk-mux.c b/drivers/clk/metag/clk-mux.c
new file mode 100644
index 0000000..5afedde
--- /dev/null
+++ b/drivers/clk/metag/clk-mux.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Metag simple multiplexer clock implementation
+ * Based on simple multiplexer clock implementation, but does appropriate
+ * locking to protect registers shared between hardware threads.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <asm/global_lock.h>
+
+/**
+ * struct clk_metag_mux - metag multiplexer clock
+ *
+ * @mux:	the parent class
+ * @ops:	pointer to clk_ops of parent class
+ *
+ * Clock with multiple selectable parents. Extends basic mux by using a global
+ * exclusive lock when read-modify-writing the mux field so that multiple
+ * threads/cores can use different fields in the same register.
+ */
+struct clk_metag_mux {
+	struct clk_mux		mux;
+	const struct clk_ops	*ops;
+};
+
+static inline struct clk_metag_mux *to_clk_metag_mux(struct clk_hw *hw)
+{
+	struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
+
+	return container_of(mux, struct clk_metag_mux, mux);
+}
+
+static u8 clk_metag_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_metag_mux *mux = to_clk_metag_mux(hw);
+
+	return mux->ops->get_parent(&mux->mux.hw);
+}
+
+/* Acquire exclusive lock since other cores may access the same register */
+static int clk_metag_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_metag_mux *mux = to_clk_metag_mux(hw);
+	int ret;
+	unsigned long flags;
+
+	__global_lock2(flags);
+	ret = mux->ops->set_parent(&mux->mux.hw, index);
+	__global_unlock2(flags);
+
+	return ret;
+}
+
+static const struct clk_ops clk_metag_mux_ops = {
+	.get_parent = clk_metag_mux_get_parent,
+	.set_parent = clk_metag_mux_set_parent,
+};
+
+static struct clk *__init clk_register_metag_mux(struct device *dev,
+		const char *name, const char **parent_names, u8 num_parents,
+		s32 default_parent, unsigned long flags, void __iomem *reg,
+		u8 shift, u8 width, u8 clk_mux_flags)
+{
+	struct clk_metag_mux *mux;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the mux */
+	mux = kzalloc(sizeof(struct clk_metag_mux), GFP_KERNEL);
+	if (!mux) {
+		pr_err("%s: could not allocate metag mux clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &clk_metag_mux_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* struct clk_mux assignments */
+	mux->mux.reg = reg;
+	mux->mux.shift = shift;
+	mux->mux.mask = BIT(width) - 1;
+	mux->mux.flags = clk_mux_flags;
+	mux->mux.hw.init = &init;
+
+	/* struct clk_metag_mux assignments */
+	mux->ops = &clk_mux_ops;
+
+	/* set default value */
+	if (default_parent >= 0)
+		clk_metag_mux_set_parent(&mux->mux.hw, default_parent);
+
+	clk = clk_register(dev, &mux->mux.hw);
+
+	if (IS_ERR(clk))
+		kfree(mux);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+/**
+ * of_metag_mux_clk_setup() - Setup function for simple fixed rate clock
+ */
+static void __init of_metag_mux_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	u32 shift, width, default_clock;
+	void __iomem *reg;
+	int len, i;
+	struct property *prop;
+	const char **parent_names;
+	unsigned int num_parents;
+	u8 flags = 0;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	if (of_property_read_u32(node, "shift", &shift)) {
+		pr_err("%s(%s): could not read shift property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "width", &width)) {
+		pr_err("%s(%s): could not read width property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	/* count maximum number of parent clocks */
+	prop = of_find_property(node, "clocks", &len);
+	if (!prop) {
+		pr_err("%s(%s): could not find clocks property\n",
+		       __func__, clk_name);
+		return;
+	}
+	/*
+	 * There cannot be more parents than entries in "clocks" property (which
+	 * may include additional args too. It also needs to fit in a u8.
+	 */
+	num_parents = len / sizeof(u32);
+	num_parents = min(num_parents, 0xffu);
+
+	/* allocate an array of parent names */
+	parent_names = kzalloc(sizeof(const char *)*num_parents, GFP_KERNEL);
+	if (!parent_names) {
+		pr_err("%s(%s): could not allocate %u parent names\n",
+		       __func__, clk_name, num_parents);
+		goto err_kfree;
+	}
+
+	/* fill in the parent names */
+	for (i = 0; i < num_parents; ++i) {
+		parent_names[i] = of_clk_get_parent_name(node, i);
+		if (!parent_names[i]) {
+			/* truncate array length if we hit the end early */
+			num_parents = i;
+			break;
+		}
+	}
+
+	/* default parent clock (mux value) */
+	if (!of_property_read_u32(node, "default-clock", &default_clock)) {
+		if (default_clock >= num_parents) {
+			pr_err("%s(%s): default-clock %u out of range (%u bits)\n",
+			       __func__, clk_name, default_clock, width);
+			goto err_kfree;
+		}
+	} else {
+		default_clock = -1;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s(%s): of_iomap failed\n",
+		       __func__, clk_name);
+		goto err_kfree;
+	}
+
+	clk = clk_register_metag_mux(NULL, clk_name, parent_names, num_parents,
+				     default_clock, 0, reg, shift,
+				     width, flags);
+	if (IS_ERR(clk))
+		goto err_iounmap;
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+
+err_iounmap:
+	iounmap(reg);
+err_kfree:
+	kfree(parent_names);
+}
+CLK_OF_DECLARE(metag_mux_clk, "img,meta-mux-clock", of_metag_mux_clk_setup);
+#endif /* CONFIG_OF */
-- 
1.8.1.2




From james.hogan at imgtec.com  Fri May 10 11:02:06 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:02:06 +0100
Subject: [PATCH RFC 1/2] clk: metag/clk-gate: add metag specific clock gate
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368198127-1295-5-git-send-email-james.hogan@imgtec.com>

Add a metag architecture specific clk-gate which extends the generic one
to use global lock2 to protect the register fields. It is common with
metag to have an RTOS running on a different thread or core with access
to different bits in the same register (in this case clock gate bits for
other clocks). Access to such registers must be serialised with a global
lock such as the one provided by the metag architecture port in
<asm/global_lock.h>

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 .../bindings/clock/img,meta-gate-clock.txt         |  28 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/metag/Makefile                         |   2 +
 drivers/clk/metag/clk-gate.c                       | 179 +++++++++++++++++++++
 4 files changed, 210 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
 create mode 100644 drivers/clk/metag/Makefile
 create mode 100644 drivers/clk/metag/clk-gate.c

diff --git a/Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt b/Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
new file mode 100644
index 0000000..483097c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
@@ -0,0 +1,28 @@
+Binding for clock gate requiring global Meta locking.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : Shall be "img,meta-mux-clock".
+- #clock-cells       : From common clock binding; shall be set to 0.
+- reg                : Address of configuration register.
+- bit                : Bit number of gate switch in configuration register.
+- clocks             : From common clock binding.
+
+Required source clocks:
+- 0                  : Input clock that can be gated (doesn't have to be named).
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+	clock {
+		compatible = "img,meta-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&sys_clk>;
+		reg = <0x02004010 0x4>;
+		bit = <0>;
+		clock-output-names = "scb0";
+	};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e7f7fe9..a800077 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= clk-zynq.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 
+obj-$(CONFIG_METAG)		+= metag/
 obj-$(CONFIG_X86)		+= x86/
 
 # Chip specific
diff --git a/drivers/clk/metag/Makefile b/drivers/clk/metag/Makefile
new file mode 100644
index 0000000..8e9a6ac
--- /dev/null
+++ b/drivers/clk/metag/Makefile
@@ -0,0 +1,2 @@
+# metag clock types
+obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
diff --git a/drivers/clk/metag/clk-gate.c b/drivers/clk/metag/clk-gate.c
new file mode 100644
index 0000000..63da8d9
--- /dev/null
+++ b/drivers/clk/metag/clk-gate.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Metag gated clock implementation
+ * Based on gated clock implementation, but does appropriate locking to protect
+ * registers shared between hardware threads.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <asm/global_lock.h>
+
+/**
+ * struct clk_metag_gate - metag gating clock
+ *
+ * @mux:	the parent class
+ * @ops:	pointer to clk_ops of parent class
+ *
+ * Clock which can gate its output. Extends basic mux by using a global
+ * exclusive lock when read-modify-writing the mux field so that multiple
+ * threads/cores can use different fields in the same register.
+ */
+struct clk_metag_gate {
+	struct clk_gate		gate;
+	const struct clk_ops	*ops;
+};
+
+static inline struct clk_metag_gate *to_clk_metag_gate(struct clk_hw *hw)
+{
+	struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
+
+	return container_of(gate, struct clk_metag_gate, gate);
+}
+
+/* Acquire exclusive lock since other cores may access the same register */
+static int clk_metag_gate_enable(struct clk_hw *hw)
+{
+	struct clk_metag_gate *gate = to_clk_metag_gate(hw);
+	int ret;
+	unsigned long flags;
+
+	__global_lock2(flags);
+	ret = gate->ops->enable(&gate->gate.hw);
+	__global_unlock2(flags);
+
+	return ret;
+}
+
+/* Acquire exclusive lock since other cores may access the same register */
+static void clk_metag_gate_disable(struct clk_hw *hw)
+{
+	struct clk_metag_gate *gate = to_clk_metag_gate(hw);
+	unsigned long flags;
+
+	__global_lock2(flags);
+	gate->ops->disable(&gate->gate.hw);
+	__global_unlock2(flags);
+}
+
+static int clk_metag_gate_is_enabled(struct clk_hw *hw)
+{
+	struct clk_metag_gate *gate = to_clk_metag_gate(hw);
+
+	return gate->ops->is_enabled(&gate->gate.hw);
+}
+
+static const struct clk_ops clk_metag_gate_ops = {
+	.enable = clk_metag_gate_enable,
+	.disable = clk_metag_gate_disable,
+	.is_enabled = clk_metag_gate_is_enabled,
+};
+
+/**
+ * clk_register_metag_gate - register a Meta gate clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ */
+static struct clk *__init clk_register_metag_gate(struct device *dev,
+		const char *name, const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx, u8 clk_gate_flags)
+{
+	struct clk_metag_gate *gate;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the gate */
+	gate = kzalloc(sizeof(struct clk_metag_gate), GFP_KERNEL);
+	if (!gate) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &clk_metag_gate_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	/* struct clk_gate assignments */
+	gate->gate.reg = reg;
+	gate->gate.bit_idx = bit_idx;
+	gate->gate.flags = clk_gate_flags;
+	gate->gate.hw.init = &init;
+
+	/* struct clk_metag_gate assignments */
+	gate->ops = &clk_gate_ops;
+
+	clk = clk_register(dev, &gate->gate.hw);
+
+	if (IS_ERR(clk))
+		kfree(gate);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+/**
+ * of_metag_gate_clk_setup() - Setup function for simple fixed rate clock
+ */
+static void __init of_metag_gate_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	u32 bit_idx;
+	void __iomem *reg;
+	const char *parent_name;
+	u8 flags = 0;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	if (of_property_read_u32(node, "bit", &bit_idx)) {
+		pr_err("%s(%s): could not read bit property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	parent_name = of_clk_get_parent_name(node, 0);
+	if (!parent_name) {
+		pr_err("%s(%s): could not read parent clock\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s(%s): of_iomap failed\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	clk = clk_register_metag_gate(NULL, clk_name, parent_name,
+				      CLK_SET_RATE_PARENT, reg, bit_idx, flags);
+	if (IS_ERR(clk))
+		goto err_iounmap;
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+
+err_iounmap:
+	iounmap(reg);
+}
+CLK_OF_DECLARE(metag_gate_clk, "img,meta-gate-clock", of_metag_gate_clk_setup);
+#endif /* CONFIG_OF */
-- 
1.8.1.2




From james.hogan at imgtec.com  Fri May 10 11:02:07 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:02:07 +0100
Subject: [PATCH RFC 2/2] clk: metag/clk-mux: add metag specific clk-mux
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368198127-1295-6-git-send-email-james.hogan@imgtec.com>

Add a metag architecture specific clk-mux which extends the generic one
to use global lock2 to protect the register fields. It is common with
metag to have an RTOS running on a different thread or core with access
to different bits in the same register (in this case clock switch bits
for other clocks). Access to such registers must be serialised with a
global lock such as the one provided by the metag architecture port in
<asm/global_lock.h>

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 .../bindings/clock/img,meta-mux-clock.txt          |  33 ++++
 drivers/clk/metag/Makefile                         |   1 +
 drivers/clk/metag/clk-mux.c                        | 211 +++++++++++++++++++++
 3 files changed, 245 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
 create mode 100644 drivers/clk/metag/clk-mux.c

diff --git a/Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt b/Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
new file mode 100644
index 0000000..7802939
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
@@ -0,0 +1,33 @@
+Binding for clock multiplexer requiring global Meta locking.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : Shall be "img,meta-mux-clock".
+- #clock-cells       : From common clock binding; shall be set to 0.
+- reg                : Address of configuration register.
+- shift              : Shift of mux value field in configuration register.
+- width              : Width of mux value field in configuration register.
+- clocks             : From common clock binding.
+
+Required source clocks:
+- 0..(1<<width)-1    : Input clocks to multiplex (don't have to be named).
+
+Optional properties:
+- clock-output-names : From common clock binding.
+- default-clock      : Mux value to set initially.
+
+Example:
+	clock {
+		compatible = "img,meta-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&xtal1>,
+			 <&xtal2>;
+		reg = <0x02005908 0x4>;
+		shift = <0>;
+		width = <1>;
+		clock-output-names = "sysclk0_sw";
+		default-clock = <1>; /* default to xtal2 */
+	};
diff --git a/drivers/clk/metag/Makefile b/drivers/clk/metag/Makefile
index 8e9a6ac..c53ccb2 100644
--- a/drivers/clk/metag/Makefile
+++ b/drivers/clk/metag/Makefile
@@ -1,2 +1,3 @@
 # metag clock types
 obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
diff --git a/drivers/clk/metag/clk-mux.c b/drivers/clk/metag/clk-mux.c
new file mode 100644
index 0000000..5afedde
--- /dev/null
+++ b/drivers/clk/metag/clk-mux.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Metag simple multiplexer clock implementation
+ * Based on simple multiplexer clock implementation, but does appropriate
+ * locking to protect registers shared between hardware threads.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <asm/global_lock.h>
+
+/**
+ * struct clk_metag_mux - metag multiplexer clock
+ *
+ * @mux:	the parent class
+ * @ops:	pointer to clk_ops of parent class
+ *
+ * Clock with multiple selectable parents. Extends basic mux by using a global
+ * exclusive lock when read-modify-writing the mux field so that multiple
+ * threads/cores can use different fields in the same register.
+ */
+struct clk_metag_mux {
+	struct clk_mux		mux;
+	const struct clk_ops	*ops;
+};
+
+static inline struct clk_metag_mux *to_clk_metag_mux(struct clk_hw *hw)
+{
+	struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
+
+	return container_of(mux, struct clk_metag_mux, mux);
+}
+
+static u8 clk_metag_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_metag_mux *mux = to_clk_metag_mux(hw);
+
+	return mux->ops->get_parent(&mux->mux.hw);
+}
+
+/* Acquire exclusive lock since other cores may access the same register */
+static int clk_metag_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_metag_mux *mux = to_clk_metag_mux(hw);
+	int ret;
+	unsigned long flags;
+
+	__global_lock2(flags);
+	ret = mux->ops->set_parent(&mux->mux.hw, index);
+	__global_unlock2(flags);
+
+	return ret;
+}
+
+static const struct clk_ops clk_metag_mux_ops = {
+	.get_parent = clk_metag_mux_get_parent,
+	.set_parent = clk_metag_mux_set_parent,
+};
+
+static struct clk *__init clk_register_metag_mux(struct device *dev,
+		const char *name, const char **parent_names, u8 num_parents,
+		s32 default_parent, unsigned long flags, void __iomem *reg,
+		u8 shift, u8 width, u8 clk_mux_flags)
+{
+	struct clk_metag_mux *mux;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the mux */
+	mux = kzalloc(sizeof(struct clk_metag_mux), GFP_KERNEL);
+	if (!mux) {
+		pr_err("%s: could not allocate metag mux clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &clk_metag_mux_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* struct clk_mux assignments */
+	mux->mux.reg = reg;
+	mux->mux.shift = shift;
+	mux->mux.mask = BIT(width) - 1;
+	mux->mux.flags = clk_mux_flags;
+	mux->mux.hw.init = &init;
+
+	/* struct clk_metag_mux assignments */
+	mux->ops = &clk_mux_ops;
+
+	/* set default value */
+	if (default_parent >= 0)
+		clk_metag_mux_set_parent(&mux->mux.hw, default_parent);
+
+	clk = clk_register(dev, &mux->mux.hw);
+
+	if (IS_ERR(clk))
+		kfree(mux);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+/**
+ * of_metag_mux_clk_setup() - Setup function for simple fixed rate clock
+ */
+static void __init of_metag_mux_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	u32 shift, width, default_clock;
+	void __iomem *reg;
+	int len, i;
+	struct property *prop;
+	const char **parent_names;
+	unsigned int num_parents;
+	u8 flags = 0;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	if (of_property_read_u32(node, "shift", &shift)) {
+		pr_err("%s(%s): could not read shift property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "width", &width)) {
+		pr_err("%s(%s): could not read width property\n",
+		       __func__, clk_name);
+		return;
+	}
+
+	/* count maximum number of parent clocks */
+	prop = of_find_property(node, "clocks", &len);
+	if (!prop) {
+		pr_err("%s(%s): could not find clocks property\n",
+		       __func__, clk_name);
+		return;
+	}
+	/*
+	 * There cannot be more parents than entries in "clocks" property (which
+	 * may include additional args too. It also needs to fit in a u8.
+	 */
+	num_parents = len / sizeof(u32);
+	num_parents = min(num_parents, 0xffu);
+
+	/* allocate an array of parent names */
+	parent_names = kzalloc(sizeof(const char *)*num_parents, GFP_KERNEL);
+	if (!parent_names) {
+		pr_err("%s(%s): could not allocate %u parent names\n",
+		       __func__, clk_name, num_parents);
+		goto err_kfree;
+	}
+
+	/* fill in the parent names */
+	for (i = 0; i < num_parents; ++i) {
+		parent_names[i] = of_clk_get_parent_name(node, i);
+		if (!parent_names[i]) {
+			/* truncate array length if we hit the end early */
+			num_parents = i;
+			break;
+		}
+	}
+
+	/* default parent clock (mux value) */
+	if (!of_property_read_u32(node, "default-clock", &default_clock)) {
+		if (default_clock >= num_parents) {
+			pr_err("%s(%s): default-clock %u out of range (%u bits)\n",
+			       __func__, clk_name, default_clock, width);
+			goto err_kfree;
+		}
+	} else {
+		default_clock = -1;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s(%s): of_iomap failed\n",
+		       __func__, clk_name);
+		goto err_kfree;
+	}
+
+	clk = clk_register_metag_mux(NULL, clk_name, parent_names, num_parents,
+				     default_clock, 0, reg, shift,
+				     width, flags);
+	if (IS_ERR(clk))
+		goto err_iounmap;
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+
+err_iounmap:
+	iounmap(reg);
+err_kfree:
+	kfree(parent_names);
+}
+CLK_OF_DECLARE(metag_mux_clk, "img,meta-mux-clock", of_metag_mux_clk_setup);
+#endif /* CONFIG_OF */
-- 
1.8.1.2




From james.hogan at imgtec.com  Fri May 10 11:09:14 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 10 May 2013 16:09:14 +0100
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <1368198127-1295-4-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
 <1368198127-1295-4-git-send-email-james.hogan@imgtec.com>
Message-ID: <518D0D9A.5080502@imgtec.com>

On 10/05/13 16:02, James Hogan wrote:
> This adds a metag architecture specific clk-gate and clk-mux which
> extends the generic ones to use global lock2 to protect the register
> fields. It is common with metag to have an RTOS running on a different
> thread or core with access to different bits in the same register (which
> contain clock gate/switch bits for other clocks). Access to such
> registers must be serialised with a global lock such as the one provided
> by the metag architecture port in <asm/global_lock.h>

Hmm, sorry about the duplicated emails, I had *.patch twice in my git
send-email command line :(.



From gregkh at linuxfoundation.org  Fri May 10 11:23:55 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Fri, 10 May 2013 08:23:55 -0700
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <518D07FB.7010606@codethink.co.uk>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de>
 <20130508153459.GA17186@kroah.com>
 <518D07FB.7010606@codethink.co.uk>
Message-ID: <20130510152355.GB11227@kroah.com>

On Fri, May 10, 2013 at 04:45:15PM +0200, Ben Dooks wrote:
> On 08/05/13 17:34, Greg KH wrote:
> >On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
> >>>+#define ASC_MAJOR		204
> >>>+#define ASC_MINOR_START		40
> >>
> >>I don't know what the current policy is on allocating major/minor numbers,
> >>but I'm sure you cannot just reuse one that is already used.
> >
> >I agree, why are you trying to create a new tty device name?  Can't you
> >use the existing ttyS name and minor number as you will not have any
> >other type of serial device on this system?
> 
> This would be an issue on systems that either accept plug-in cards
> such as PCMCIA/CardBus/PCI or have additional off SoC IO spaces
> where 8250 compatible UARTS could live.

I thought these were set-top box systems that couldn't accept any
plug-in cards or anything else?  This is a SoC, right?

thanks,

greg k-h


From dianders at chromium.org  Fri May 10 11:31:05 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 10 May 2013 08:31:05 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <CAD=FV=UUaZZj0=B7335pReyeQp3V2UvckH-jy-k4SqAop7C2gw@mail.gmail.com>

Tushar,

On Thu, May 9, 2013 at 11:49 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
> It updates following drivers for EXYNOS based DT platform.
>
> * S5M8767 driver
> * MAX8997 driver
> * MMC SDHCI driver
>
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
> ---
>
> This patch is based on Olof's following patch.
> "[PATCH] ARM: exynos: defconfig update"
> https://lkml.org/lkml/2013/5/9/455
>
>  arch/arm/configs/exynos_defconfig |    6 ++++++
>  1 file changed, 6 insertions(+)

Your changes also look good to me.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From linux at arm.linux.org.uk  Fri May 10 11:28:57 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 10 May 2013 16:28:57 +0100
Subject: arch/arm/mach-omap2/id.c - IS_ERR_OR_NULL()
In-Reply-To: <CAB=otbRXPoHWPb3O+AYhdq5BccmLWRE=ZPPPQYQXge6w332+fQ@mail.gmail.com>
References: <20130509090911.GM21614@n2100.arm.linux.org.uk>
 <CAB=otbRXPoHWPb3O+AYhdq5BccmLWRE=ZPPPQYQXge6w332+fQ@mail.gmail.com>
Message-ID: <20130510152857.GQ21614@n2100.arm.linux.org.uk>

On Fri, May 10, 2013 at 12:50:42PM +0300, Ruslan Bilovol wrote:
> Hi Russell,
> 
> On Thu, May 9, 2013 at 12:09 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > So, I eliminated all but a very few of these from arch/arm, and I notice
> > today that there's a new couple of instances introduced by:
> >
> > commit 6770b211432564c562c856d612b43bbd42e4ab5e
> > Author: Ruslan Bilovol <ruslan.bilovol at ti.com>
> > Date:   Thu Feb 14 13:55:24 2013 +0200
> >
> >     ARM: OMAP2+: Export SoC information to userspace
> >
> >     In some situations it is useful for userspace to
> >     know some SoC-specific information. For example,
> >     this may be used for deciding what kernel module to
> >     use or how to better configure some settings etc.
> >     This patch exports OMAP SoC information to userspace
> >     using existing in Linux kernel SoC infrastructure.
> >
> >     This information can be read under
> >     /sys/devices/socX directory
> >
> >     Signed-off-by: Ruslan Bilovol <ruslan.bilovol at ti.com>
> >     [tony at atomide.com: updated for multiplatform changes]
> >     Signed-off-by: Tony Lindgren <tony at atomide.com>
> >
> > +       soc_dev = soc_device_register(soc_dev_attr);
> > +       if (IS_ERR_OR_NULL(soc_dev)) {
> > +               kfree(soc_dev_attr);
> > +               return;
> > +       }
> > +
> > +       parent = soc_device_to_device(soc_dev);
> > +       if (!IS_ERR_OR_NULL(parent))
> > +               device_create_file(parent, &omap_soc_attr);
> >
> > This is nonsense.  For the first, IS_ERR() is sufficient.  For the second,
> > tell me what error checking is required in the return value of this
> > function:
> >
> > struct device *soc_device_to_device(struct soc_device *soc_dev)
> > {
> >         return &soc_dev->dev;
> > }
> >
> > when you've already determined that the passed soc_dev is a valid pointer.
> > If you read the comments against the prototype:
> >
> > /**
> >  * soc_device_to_device - helper function to fetch struct device
> >  * @soc: Previously registered SoC device container
> >  */
> > struct device *soc_device_to_device(struct soc_device *soc);
> >
> > if "soc" is valid, it means the "previously registered SoC device container"
> > must have succeeded and that can only happen if the struct device has been
> > registered.  Ergo, there will always be a valid struct device pointer for
> > any registered SoC device container.  Therefore, if soc_device_register()
> > succeeds, then the return value from soc_device_to_device() will always be
> > valid and no error checking of it is required.
> >
> > Simples.  The rule as ever applies here: get to know the APIs your using
> > and don't fumble around in the dark hoping that you'll get this stuff
> > right.
> 
> The interesting thing is that extra IS_ERR_OR_NULL checking was
> introduced by author
> of the SoC API in his implementation for the arm/mach-ux500 platform
> and I used the same checking in my implementation when looked into his
> implementation for reference.
> Thanks for pointing on this, I will be more careful in the future.

Well, the whole reasoning here is that IS_ERR_OR_NULL() is far too easy
to get wrong - there are too many of this kind of crap in the kernel:

	foo = some_func();
	if (IS_ERR_OR_NULL(foo))
		return PTR_ERR(foo);

which is wrong, because if foo _is_ NULL, the function doesn't return an
error, it returns success instead.  Of course, if some_func() never ever
returns NULL in the first place, that can't happen, but then the additional
test there for a NULL pointer is, to put it bluntly, total bollocks.

Instead, what it shows is that the author of the code hasn't been bothered
to really check what the return conditions of the API actually are - and
yes, this kind of crap really has happened.  Where APIs return NULL on
failure and the author has used code similar to the above...

So, the general rule is... if you see IS_ERR_OR_NULL(), it probably is a
bug just waiting to happen in some way.

IS_ERR_OR_NULL() is not a subsitute for putting thought in.
IS_ERR_OR_NULL() is a trap for the unwary kernel programmer.

And there's moves to eliminate it from the kernel - I have a patch prepared
which has a lot of support to mark IS_ERR_OR_NULL() deprecated... that can't
go in until we've eliminated most of the current (probably incorrect) uses.


From ben.dooks at codethink.co.uk  Fri May 10 11:31:04 2013
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Fri, 10 May 2013 17:31:04 +0200
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130510152355.GB11227@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de> <20130508153459.GA17186@kroah.com>
 <518D07FB.7010606@codethink.co.uk> <20130510152355.GB11227@kroah.com>
Message-ID: <518D12B8.9070608@codethink.co.uk>

On 10/05/13 17:23, Greg KH wrote:
> On Fri, May 10, 2013 at 04:45:15PM +0200, Ben Dooks wrote:
>> On 08/05/13 17:34, Greg KH wrote:
>>> On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
>>>>> +#define ASC_MAJOR		204
>>>>> +#define ASC_MINOR_START		40
>>>>
>>>> I don't know what the current policy is on allocating major/minor numbers,
>>>> but I'm sure you cannot just reuse one that is already used.
>>>
>>> I agree, why are you trying to create a new tty device name?  Can't you
>>> use the existing ttyS name and minor number as you will not have any
>>> other type of serial device on this system?
>>
>> This would be an issue on systems that either accept plug-in cards
>> such as PCMCIA/CardBus/PCI or have additional off SoC IO spaces
>> where 8250 compatible UARTS could live.
>
> I thought these were set-top box systems that couldn't accept any
> plug-in cards or anything else?  This is a SoC, right?

The comment covers more than just this particular instance.

A lot of SoC devices have expansion interfaces which would accept
such UARTs.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius


From stuart.menefy at st.com  Fri May 10 11:40:58 2013
From: stuart.menefy at st.com (Stuart MENEFY)
Date: Fri, 10 May 2013 16:40:58 +0100
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130510152355.GB11227@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022248-2153-1-git-send-email-srinivas.kandagatla@st.com>
 <201305081634.43498.arnd@arndb.de> <20130508153459.GA17186@kroah.com>
 <518D07FB.7010606@codethink.co.uk> <20130510152355.GB11227@kroah.com>
Message-ID: <518D150A.7030807@st.com>

On 10/05/13 16:23, Greg KH wrote:
> On Fri, May 10, 2013 at 04:45:15PM +0200, Ben Dooks wrote:
>> On 08/05/13 17:34, Greg KH wrote:
>>> On Wed, May 08, 2013 at 04:34:43PM +0200, Arnd Bergmann wrote:
>>>>> +#define ASC_MAJOR		204
>>>>> +#define ASC_MINOR_START		40
>>>>
>>>> I don't know what the current policy is on allocating major/minor numbers,
>>>> but I'm sure you cannot just reuse one that is already used.
>>>
>>> I agree, why are you trying to create a new tty device name?  Can't you
>>> use the existing ttyS name and minor number as you will not have any
>>> other type of serial device on this system?
>>
>> This would be an issue on systems that either accept plug-in cards
>> such as PCMCIA/CardBus/PCI or have additional off SoC IO spaces
>> where 8250 compatible UARTS could live.
> 
> I thought these were set-top box systems that couldn't accept any
> plug-in cards or anything else?  This is a SoC, right?

Correct, it is a SoC intended for set-top-box systems. But they are also
expandable and have a PCIe root complex. In the final system this would
normally be used for things like WiFi, but in development boards these
are brought out to generic PCIe slots where pretty much anything can be
plugged in.

We've also had systems in the dim and distant past which used memory
mapped external super I/O controllers which had 8250 compatible serial
ports.

So while its not usual, we have had systems with both ASC and 8250
compatible serial ports, which is why we'd like to keep the option open.

Stuart


From csd at broadcom.com  Fri May 10 11:48:03 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 10 May 2013 08:48:03 -0700
Subject: [PATCH V2 2/2] ARM: mmc: bcm281xx SDHCI driver (dt mods)
In-Reply-To: <1368200883-15668-1-git-send-email-csd@broadcom.com>
References: <1368200883-15668-1-git-send-email-csd@broadcom.com>
Message-ID: <1368200883-15668-2-git-send-email-csd@broadcom.com>

Add SDHCI driver for the Broadcom 281xx SoCs. Also
add bindings for it into bcm281xx dts files.

Changes from V1:
 - split original patch into 2, one for driver and this one for dt

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
new file mode 100644
index 0000000..ad1c4bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
@@ -0,0 +1,16 @@
+Broadcom BCM281xx SDHCI driver
+
+This file documents differences between the core properties in mmc.txt
+and the properties in the bcm281xx driver.
+
+Required properties:
+- compatible : Should be "bcm,kona-sdhci"
+
+Example:
+
+sdio2: sdio at 0x3f1a0000 {
+	compatible = "bcm,kona-sdhci";
+	reg = <0x3f1a0000 0x10000>;
+	interrupts = <0x0 74 0x4>;
+};
+
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067c..9ae3404 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -27,4 +27,21 @@
 		status = "okay";
 	};
 
+	sdio0: sdio at 0x3f180000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		non-removable;
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index ad13588..6606b41 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,4 +47,33 @@
 		    cache-unified;
 		    cache-level = <2>;
 	};
+
+	sdio0: sdio at 0x3f180000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f180000 0x10000>;
+		interrupts = <0x0 77 0x4>;
+		status = "disabled";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f190000 0x10000>;
+		interrupts = <0x0 76 0x4>;
+		status = "disabled";
+	};
+
+	sdio2: sdio at 0x3f1a0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1a0000 0x10000>;
+		interrupts = <0x0 74 0x4>;
+		status = "disabled";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1b0000 0x10000>;
+		interrupts = <0x0 73 0x4>;
+		status = "disabled";
+	};
+
 };
-- 
1.7.10.4




From csd at broadcom.com  Fri May 10 11:48:02 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 10 May 2013 08:48:02 -0700
Subject: [PATCH V2 1/2] ARM: mmc: bcm281xx SDHCI driver
Message-ID: <1368200883-15668-1-git-send-email-csd@broadcom.com>

Add SDHCI driver for the Broadcom 281xx SoCs. Also
add bindings for it into bcm281xx dts files.
Still missing:
 - power managemement

Changes from V1:
 - split DT into separate patch
 - use gpio_is_valid instead of direct test
 - switch pr_debug calls to dev_dbg
 - use of_property_read_bool

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index e3bf2d6..65edf6d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index d88219e..ad11c7f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -238,6 +238,17 @@ config MMC_SDHCI_S3C_DMA
 
 	  YMMV.
 
+config MMC_SDHCI_BCM_KONA
+	tristate "SDHCI support on Broadcom KONA platform"
+	depends on ARCH_BCM
+	select MMC_SDHCI_PLTFM
+	help
+	  This selects the Broadcom Kona Secure Digital Host Controller
+	  Interface(SDHCI) support.
+	  This is used in Broadcom mobile SoCs.
+
+	  If you have a controller with this interface, say Y or M here.
+
 config MMC_SDHCI_BCM2835
 	tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
 	depends on ARCH_BCM2835
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index c380e3c..a9f582b 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)		+= sdhci-dove.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
+obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
new file mode 100644
index 0000000..337ee1a
--- /dev/null
+++ b/drivers/mmc/host/sdhci-bcm-kona.c
@@ -0,0 +1,485 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/highmem.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/version.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci.h"
+
+#define SDHCI_SOFT_RESET			0x01000000
+#define KONA_SDHOST_CORECTRL			0x8000
+#define KONA_SDHOST_CD_PINCTRL			0x00000008
+#define KONA_SDHOST_STOP_HCLK			0x00000004
+#define KONA_SDHOST_RESET			0x00000002
+#define KONA_SDHOST_EN				0x00000001
+
+#define KONA_SDHOST_CORESTAT			0x8004
+#define KONA_SDHOST_WP				0x00000002
+#define KONA_SDHOST_CD_SW			0x00000001
+
+#define KONA_SDHOST_COREIMR			0x8008
+#define KONA_SDHOST_IP				0x00000001
+
+#define KONA_SDHOST_COREISR			0x800C
+#define KONA_SDHOST_COREIMSR			0x8010
+#define KONA_SDHOST_COREDBG1			0x8014
+#define KONA_SDHOST_COREGPO_MASK		0x8018
+
+#define SD_DETECT_GPIO_DEBOUNCE_128MS		128
+
+#define KONA_MMC_AUTOSUSPEND_DELAY		(50)
+
+struct sdhci_bcm_kona_cfg {
+	unsigned int	max_freq;
+	int		is_8bit;
+	int		irq;
+	int		cd_gpio;
+	int		wp_gpio;
+	int		non_removable;
+};
+
+struct sdhci_bcm_kona_dev {
+	struct sdhci_bcm_kona_cfg *cfg;
+	struct device *dev;
+	struct sdhci_host *host;
+	struct clk *peri_clk;
+	struct clk *sleep_clk;
+};
+
+
+static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
+{
+	unsigned int val;
+	unsigned long timeout;
+
+	/* This timeout should be sufficent for core to reset */
+	timeout = jiffies + msecs_to_jiffies(100);
+
+	/* reset the host using the top level reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_RESET;
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
+		if (time_is_before_jiffies(timeout)) {
+			pr_err("Error: sd host is stuck in reset!!!\n");
+			return -EFAULT;
+		}
+	}
+
+	/* bring the host out of reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val &= ~KONA_SDHOST_RESET;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	mdelay(1);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	return 0;
+}
+
+static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
+{
+	unsigned int val;
+
+	/* enable the interrupt from the IP core */
+	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
+	val |= KONA_SDHOST_IP;
+	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
+
+	/* Enable the AHB clock gating module to the host */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_EN;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	mdelay(1);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+}
+
+/*
+ * Software emulation of the SD card insertion/removal. Set insert=1 for insert
+ * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
+ * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
+ * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
+ */
+static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
+{
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
+	u32 val;
+	unsigned long flags;
+
+	/* this function can be called from various contexts including ISR */
+	spin_lock_irqsave(&host->lock, flags);
+	/* Ensure SD bus scanning to detect media change */
+	host->mmc->rescan_disable = 0;
+
+	/*
+	 * Back-to-Back register write needs a delay of min 10uS.
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 * We keep 20uS
+	 */
+	udelay(20);
+	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
+
+	if (insert) {
+		if (gpio_is_valid(kona_dev->cfg->wp_gpio)) {
+			int wp_status = gpio_get_value(kona_dev->cfg->wp_gpio);
+
+			if (wp_status)
+				val |= KONA_SDHOST_WP;
+			else
+				val &= ~KONA_SDHOST_WP;
+		}
+
+		val |= KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	} else {
+		val &= ~KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	return 0;
+}
+
+/*
+ * SD card detection interrupt handler
+ */
+static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *host)
+{
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
+
+	if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0) {
+		dev_dbg(kona_dev->dev, "card inserted\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 1);
+	} else {
+		dev_dbg(kona_dev->dev, "card removed\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Get the base clock. Use central clock source for now. Not sure if different
+ * clock speed to each dev is allowed
+ */
+static unsigned int sdhci_bcm_kona_get_max_clk(struct sdhci_host *host)
+{
+	struct sdhci_bcm_kona_dev *kona_dev;
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	kona_dev = pltfm_priv->priv;
+
+	return kona_dev->cfg->max_freq;
+}
+
+static unsigned int sdhci_bcm_kona_get_timeout_clock(struct sdhci_host *host)
+{
+	return sdhci_bcm_kona_get_max_clk(host);
+}
+
+static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
+				u8 power_mode)
+{
+	if (power_mode == MMC_POWER_OFF)
+		return;
+	else
+		mdelay(10);
+}
+
+static struct sdhci_ops sdhci_bcm_kona_ops = {
+	.get_max_clock = sdhci_bcm_kona_get_max_clk,
+	.get_timeout_clock = sdhci_bcm_kona_get_timeout_clock,
+	.platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
+};
+
+static struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
+	.ops    = &sdhci_bcm_kona_ops,
+	.quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
+		SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
+		SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
+		SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+static const struct of_device_id sdhci_bcm_kona_of_match[] __initdata = {
+	{ .compatible = "bcm,kona-sdhci", .data = &sdhci_pltfm_data_kona },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
+
+static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
+			struct platform_device *pdev)
+{
+	struct sdhci_bcm_kona_cfg *cfg;
+	struct device_node *np = pdev->dev.of_node;
+	u32 temp;
+
+	if (!np)
+		return NULL;
+
+	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
+	if (!cfg) {
+		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
+		return NULL;
+	}
+
+	cfg->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
+	cfg->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
+	if (of_property_read_bool(np, "non-removable"))
+		cfg->non_removable = 1;
+
+	if (of_property_read_u32(np, "bus-width", &temp) == 0 && temp == 8)
+		cfg->is_8bit = 1;
+
+	if (of_property_read_u32(np, "max-frequency", &cfg->max_freq)) {
+		dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
+		return NULL;
+	}
+	return cfg;
+}
+
+static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct sdhci_bcm_kona_cfg *kona_cfg = NULL;
+	const struct sdhci_pltfm_data *plat_data;
+	struct sdhci_bcm_kona_dev *kona_dev = NULL;
+	struct sdhci_pltfm_host *pltfm_priv;
+	struct device *dev = &pdev->dev;
+	struct sdhci_host *host;
+	int ret;
+	unsigned int irq;
+	ret = 0;
+
+	match = of_match_device(sdhci_bcm_kona_of_match, &pdev->dev);
+	if (!match)
+		plat_data = &sdhci_pltfm_data_kona;
+	else
+		plat_data = match->data;
+
+	host = sdhci_pltfm_init(pdev, (struct sdhci_pltfm_data *)plat_data);
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	kona_cfg = dev->platform_data;
+	if (!kona_cfg)
+		kona_cfg = sdhci_bcm_kona_parse_dt(pdev);
+
+	if (!kona_cfg) {
+		ret = -ENXIO;
+		goto err_pltfm_free;
+	}
+
+	dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
+
+	pltfm_priv = sdhci_priv(host);
+
+	kona_dev = devm_kzalloc(dev, sizeof(*kona_dev), GFP_KERNEL);
+	if (!kona_dev) {
+		dev_err(dev, "Can't allocate kona_dev\n");
+		ret = -ENOMEM;
+		goto err_pltfm_free;
+	}
+	kona_dev->cfg = kona_cfg;
+	kona_dev->dev = dev;
+	pltfm_priv->priv = kona_dev;
+
+	dev_dbg(dev, "non-removable=%c\n",
+		 (kona_cfg->non_removable) ? 'Y' : 'N');
+	dev_dbg(dev, "cd_gpio %d, wp_gpio %d\n", kona_cfg->cd_gpio,
+		 kona_cfg->wp_gpio);
+
+	if (kona_cfg->non_removable) {
+		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+	}
+
+	dev_dbg(dev, "is_8bit=%c\n", (kona_cfg->is_8bit) ? 'Y' : 'N');
+	if (kona_cfg->is_8bit)
+		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+	ret = sdhci_bcm_kona_sd_reset(host);
+	if (ret)
+		goto err_pltfm_free;
+
+	sdhci_bcm_kona_sd_init(host);
+
+	ret = sdhci_add_host(host);
+	if (ret) {
+		dev_err(dev, "Failed sdhci_add_host\n");
+		goto err_reset;
+	}
+
+	/* if device is eMMC, emulate card insert right here */
+	if (kona_cfg->non_removable) {
+		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
+		if (ret) {
+			dev_err(dev,
+				"unable to emulate card insertion\n");
+			goto err_remove_host;
+		}
+	} else if (gpio_is_valid(kona_dev->cfg->cd_gpio)) {
+		ret = devm_gpio_request(dev, kona_dev->cfg->cd_gpio, "sdio cd");
+		if (ret < 0) {
+			dev_err(kona_dev->dev,
+				"Unable to request GPIO pin %d\n",
+				kona_dev->cfg->cd_gpio);
+			goto err_remove_host;
+		}
+
+		gpio_direction_input(kona_dev->cfg->cd_gpio);
+
+		/* Set debounce for SD Card detect to maximum value (128ms)
+		 *
+		 * NOTE-1: If gpio_set_debounce() returns error we still
+		 * continue with the default debounce value set. Another reason
+		 * for doing this is that on rhea-ray boards the SD Detect GPIO
+		 * is on GPIO Expander and gpio_set_debounce() will return error
+		 * and if we return error from here, then probe() would fail and
+		 * SD detection would always fail.
+		 *
+		 * NOTE-2: We also give a msleep() of the "debounce" time here
+		 * so that we give enough time for the debounce to stabilize
+		 * before we read the gpio value in gpio_get_value_cansleep().
+		 */
+		ret = gpio_set_debounce(kona_dev->cfg->cd_gpio,
+				(SD_DETECT_GPIO_DEBOUNCE_128MS * 1000));
+		if (ret < 0) {
+			dev_err(kona_dev->dev,
+				"%s: gpio set debounce failed."
+				"default debounce value assumed\n", __func__);
+		}
+
+		/* Sleep for 128ms to allow debounce to stabilize */
+		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
+		/* request irq for cd_gpio after the gpio debounce is
+		 * stabilized, otherwise, some bogus gpio interrupts might be
+		 * triggered.
+		 */
+		irq = gpio_to_irq(kona_dev->cfg->cd_gpio);
+		ret = devm_request_threaded_irq(dev,
+				irq,
+				NULL,
+				sdhci_bcm_kona_pltfm_cd_interrupt,
+				IRQF_TRIGGER_FALLING|
+				IRQF_TRIGGER_RISING |
+				IRQF_ONESHOT |
+				IRQF_NO_SUSPEND, "sdio cd", host);
+		if (ret) {
+			dev_err(kona_dev->dev,
+				"Failed irq %d request for gpio=%d ret=%d\n",
+				gpio_to_irq(kona_dev->cfg->cd_gpio),
+				kona_dev->cfg->cd_gpio, ret);
+			goto err_remove_host;
+		}
+		if (gpio_is_valid(kona_dev->cfg->wp_gpio)) {
+			ret = devm_gpio_request(dev,
+				kona_dev->cfg->wp_gpio, "sdio wp");
+			if (ret < 0) {
+				dev_err(&pdev->dev,
+					"Unable to request WP pin %d\n",
+					kona_dev->cfg->wp_gpio);
+				kona_dev->cfg->wp_gpio = -1;
+			} else {
+				gpio_direction_input(kona_dev->cfg->wp_gpio);
+			}
+		}
+
+		/*
+		 * Since the card detection GPIO interrupt is configured to be
+		 * edge sensitive, check the initial GPIO value here, emulate
+		 * only if the card is present
+		 */
+		if (gpio_get_value_cansleep(kona_dev->cfg->cd_gpio) == 0)
+			sdhci_bcm_kona_sd_card_emulate(host, 1);
+	}
+
+	dev_dbg(dev, "initialized properly\n");
+	return 0;
+
+err_remove_host:
+	sdhci_remove_host(host, 0);
+
+err_reset:
+	sdhci_bcm_kona_sd_reset(host);
+
+err_pltfm_free:
+	sdhci_pltfm_free(pdev);
+
+	dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
+	return ret;
+}
+
+static int __exit sdhci_bcm_kona_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = pltfm_host->priv;
+	int dead;
+	u32 scratch;
+
+	dead = 0;
+	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
+	if (scratch == (u32)-1)
+		dead = 1;
+	sdhci_remove_host(host, dead);
+
+	sdhci_free_host(host);
+
+	return 0;
+}
+
+static struct platform_driver sdhci_bcm_kona_driver = {
+	.driver		= {
+		.name	= "sdhci-kona",
+		.owner	= THIS_MODULE,
+		.pm	= SDHCI_PLTFM_PMOPS,
+		.of_match_table = of_match_ptr(sdhci_bcm_kona_of_match),
+	},
+	.probe		= sdhci_bcm_kona_probe,
+	.remove		= __exit_p(sdhci_bcm_kona_remove),
+};
+module_platform_driver(sdhci_bcm_kona_driver);
+
+MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
+MODULE_AUTHOR("Broadcom");
+MODULE_LICENSE("GPL v2");
+
-- 
1.7.10.4




From swarren at wwwdotorg.org  Fri May 10 12:37:44 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 May 2013 10:37:44 -0600
Subject: [RFC 23/42] drivers/spi: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-24-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-24-git-send-email-wsa@the-dreams.de>
Message-ID: <518D2258.2090403@wwwdotorg.org>

On 05/10/2013 02:17 AM, Wolfram Sang wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.

> diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c

> -	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!r) {
> -		dev_err(&pdev->dev, "No IO memory resource\n");
> -		ret = -ENODEV;
> -		goto exit_free_master;
> -	}
>  	tspi->phys = r->start;
> +	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

The tspi->phy assignment is broken there now.

> diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c

> -	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!r) {
> -		dev_err(&pdev->dev, "No IO memory resource\n");
> -		ret = -ENODEV;
> -		goto exit_free_master;
> -	}
>  	tspi->phys = r->start;
> +	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

Same here.



From itooo at itooo.com  Fri May 10 12:43:15 2013
From: itooo at itooo.com (Greg)
Date: Fri, 10 May 2013 18:43:15 +0200
Subject: MVNETA irq with backport-3.8
In-Reply-To: <51897810.8020002@free-electrons.com>
References: <51890C29.8000504@itooo.com> <20130507181823.23342ffb@skate>
 <51892E87.5020903@itooo.com> <518971D4.5000603@free-electrons.com>
 <20130507214256.GC5414@1wt.eu> <51897810.8020002@free-electrons.com>
Message-ID: <518D23A3.9020405@itooo.com>

Le 07/05/2013 23:54, Gregory CLEMENT a ?crit :
> Hi Willy,
>
> On 05/07/2013 11:42 PM, Willy Tarreau wrote:
>> Hi Gr?gory,
>>
>> On Tue, May 07, 2013 at 11:27:48PM +0200, Gregory CLEMENT wrote:
>>> I built and tested backport-3.8 and indeed the Ethernet is broken.
>>> It was cause by a recent batch of fixes that I added, now I have to
>>> figure out why they have broken the ethernet whereas they were supposed
>>> to make it work better!
>> If that can help you, here is the list of (possibly relevant) patches
>> I have applied on top of 3.9 picked from your repository some time
>> ago (it's not up to date with the latest versions due to merge issues
>> inducing laziness on my side) :
>>
>> $ git log --oneline --grep=free-electrons v3.9..
>> 65d2b5c ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
>> 26cabde ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
>> 34b32e8 ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
>> 31504c0 ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
>> 8cc752e drivers: memory: Introduce Marvell EBU Device Bus driver
>> 48c6ddc arm: mvebu: update defconfig with PCI and USB support
>> f4ed5ba arm: mvebu: PCIe Device Tree informations for Armada XP GP
>> b1ed2c5 arm: mvebu: PCIe Device Tree informations for Armada 370 DB
>> 51e91a9 arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
>> 402f9ba arm: mvebu: PCIe Device Tree informations for Armada XP DB
>> 4899409 arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
>> fb6d69f arm: mvebu: add PCIe Device Tree informations for Armada XP
>> c523287 arm: mvebu: add PCIe Device Tree informations for Armada 370
>> 998ee7a arm: mvebu: PCIe support is now available on mvebu
>> fc9b219 pci: PCIe driver for Marvell Armada 370/XP systems
>> 4b765fb clk: mvebu: add more PCIe clocks for Armada XP
>> af3bcd9 clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
>> 6cee09e arm: pci: add a align_resource hook
>> 80fa698 pci: infrastructure to add drivers in drivers/pci/host
>> 91ca5a7 of/pci: Provide support for parsing PCI DT ranges property
>> e46b3e7 arm: plat-orion: remove addr-map code
>> d11befe arm: mach-mv78xx0: convert to use the mvebu-mbus driver
>> a508a65 arm: mach-orion5x: convert to use mvebu-mbus driver
>> e249639 arm: mach-dove: convert to use mvebu-mbus driver
>> 70efe5e arm: mach-kirkwood: convert to use mvebu-mbus driver
>> 37e82515 arm: mach-mvebu: convert to use mvebu-mbus driver
>> 035f910 bus: introduce an Marvell EBU MBus driver
>> 527d658 arm: mach-orion5x: use mv_mbus_dram_info() in PCI code
>> c1b44db arm: plat-orion: use mv_mbus_dram_info() in PCIe code
>> 59463f4 arm: plat-orion: only build addr-map.c when needed
>>
>> With those my AX3 works fine. If that can help, I can send them all to
>> you off-list, in case you notice a minor difference with something.
> Thanks for your help but I finally found the guilty commit, it was
> "66d0539 net: mvneta: convert to percpu interrupt".
>
> This commit was never submitted because finally I realized that it was
> broken in SMP. Finally it was the commit "arm: mvebu: Use local
> interrupt only for the timer 0" which was the correct solution.
>
> With the first patch I had converted the mvneta driver to use percpu
> IRQ, but as I explained in the log of the 2nd patch: "the interrupts
> have to be freed when the .stop() function is called. As the
> free_percpu_irq() function don't disable the interrupt line, we have
> to do it on each CPU before calling this. The function
> disable_percpu_irq() only disable the percpu on the current CPU and
> there is no function which allows to disable a percpu irq on a given
> CPU."
>
> So Greg, the solution is just to revert the commit 66d0539. I am going
> to update the backport-3.8 branch in a couple of minutes.
>
>
Gregory,

I pulled the change and got it working fine.
I also got the PCIe link established, I haven't tried to stress it yet, 
I will do so quickly.

I got a backtrace that might interrest you, a "deadlock" condition while 
polling network counters :

Deadlock detection:
> INFO: rcu_sched self-detected stall on CPU { 0}  (t=2100 jiffies 
> g=4229 c=4228 q=421)
> [<c0014e24>] (unwind_backtrace+0x0/0xfc) from [<c006c5c8>] 
> (rcu_check_callbacks+0x1d0/0x734)
> [<c006c5c8>] (rcu_check_callbacks+0x1d0/0x734) from [<c002ca24>] 
> (update_process_times+0x38/0x4c)
> [<c002ca24>] (update_process_times+0x38/0x4c) from [<c0058eb8>] 
> (tick_sched_timer+0x68/0x210)
> [<c0058eb8>] (tick_sched_timer+0x68/0x210) from [<c0040040>] 
> (__run_hrtimer.isra.17+0x74/0x134)
> [<c0040040>] (__run_hrtimer.isra.17+0x74/0x134) from [<c0040860>] 
> (hrtimer_interrupt+0xf8/0x2cc)
> [<c0040860>] (hrtimer_interrupt+0xf8/0x2cc) from [<c03569c0>] 
> (armada_370_xp_timer_interrupt+0x3c/0x50)
> [<c03569c0>] (armada_370_xp_timer_interrupt+0x3c/0x50) from 
> [<c0067420>] (handle_percpu_devid_irq+0x64/0x84)
> [<c0067420>] (handle_percpu_devid_irq+0x64/0x84) from [<c0063d08>] 
> (generic_handle_irq+0x24/0x30)
> [<c0063d08>] (generic_handle_irq+0x24/0x30) from [<c000eef4>] 
> (handle_IRQ+0x38/0x94)
> [<c000eef4>] (handle_IRQ+0x38/0x94) from [<c0008610>] 
> (armada_370_xp_handle_irq+0xa0/0xb4)
> [<c0008610>] (armada_370_xp_handle_irq+0xa0/0xb4) from [<c000dca0>] 
> (__irq_svc+0x40/0x50)
> Exception stack(0xee69bd20 to 0xee69bd68)
> bd20: 0094809d 00000001 f0ab5a55 0094809d eeba3000 ee69be10 00000610 
> c031a500
> bd40: ee69bf10 ef0f6380 4c000001 00000000 00000618 ee69bd68 c031a518 
> c031a558
> bd60: 00000013 ffffffff
Hung process
> [<c000dca0>] (__irq_svc+0x40/0x50) from [<c031a558>] 
> (mvneta_get_stats64+0x58/0xc0)
> [<c031a558>] (mvneta_get_stats64+0x58/0xc0) from [<c0379974>] 
> (dev_get_stats+0x38/0xb4)
> [<c0379974>] (dev_get_stats+0x38/0xb4) from [<c0379b10>] 
> (dev_seq_printf_stats+0x1c/0x114)
> [<c0379b10>] (dev_seq_printf_stats+0x1c/0x114) from [<c037d83c>] 
> (dev_seq_show+0x10/0x2c)
> [<c037d83c>] (dev_seq_show+0x10/0x2c) from [<c00bfe3c>] 
> (seq_read+0x330/0x4c8)
> [<c00bfe3c>] (seq_read+0x330/0x4c8) from [<c00ea2ac>] 
> (proc_reg_read+0x8c/0xd0)
> [<c00ea2ac>] (proc_reg_read+0x8c/0xd0) from [<c00a0554>] 
> (vfs_read+0xa0/0x134)
> [<c00a0554>] (vfs_read+0xa0/0x134) from [<c00a0628>] (sys_read+0x40/0x6c)
> [<c00a0628>] (sys_read+0x40/0x6c) from [<c000dfe0>] 
> (ret_fast_syscall+0x0/0x30)

I noticed this using "ethstatus" tool, you can see the counters are not 
incrementing smoothly under traffic.

Cheers,


From tony at atomide.com  Fri May 10 12:46:18 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 10 May 2013 09:46:18 -0700
Subject: [RFC 38/42] arch/arm/plat-omap: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-39-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-39-git-send-email-wsa@the-dreams.de>
Message-ID: <20130510164617.GK31554@atomide.com>

* Wolfram Sang <wsa at the-dreams.de> [130510 01:23]:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
> 
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>

Acked-by: Tony Lindgren <tony at atomide.com>

> ---
>  arch/arm/plat-omap/dmtimer.c |    7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 869254c..da1a3f7 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -814,12 +814,6 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (unlikely(!mem)) {
> -		dev_err(dev, "%s: no memory resource.\n", __func__);
> -		return -ENODEV;
> -	}
> -
>  	timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
>  	if (!timer) {
>  		dev_err(dev, "%s: memory alloc failed!\n", __func__);
> @@ -827,6 +821,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
>  	}
>  
>  	timer->fclk = ERR_PTR(-ENODEV);
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	timer->io_base = devm_ioremap_resource(dev, mem);
>  	if (IS_ERR(timer->io_base))
>  		return PTR_ERR(timer->io_base);
> -- 
> 1.7.10.4
> 


From s-anna at ti.com  Fri May 10 12:41:42 2013
From: s-anna at ti.com (Suman Anna)
Date: Fri, 10 May 2013 11:41:42 -0500
Subject: [RFC 2/3] mailbox: Introduce a new common API
In-Reply-To: <CAJe_ZhfFs5svKPABHWdKA83+LhxA5+Q3LKuJyqyRj_4SMMm_hg@mail.gmail.com>
References: <CAJe_ZhdH+SCs5crguXrm6y-6bu+eGnTqeJS6cOS5H5Yz=m15Cw@mail.gmail.com>
 <1367086474-28614-1-git-send-email-jaswinder.singh@linaro.org>
 <51847070.8040400@ti.com>
 <CAJe_Zhdbnpu9n46s6L5KNFuTb2K87j+V4htKkmHYtBJ6w+etxQ@mail.gmail.com>
 <518840A2.5000205@ti.com>
 <CAJe_ZhedTM_wU7NGH_QRrL=O3JSYjt9ENDLYpOEQNSX3f7OgBA@mail.gmail.com>
 <518976B9.2030605@ti.com>
 <CAJe_ZhfpLQzDBSx=2VbD3W-499-g1JOovGDuFwxkE-Cq=HQDww@mail.gmail.com>
 <518AFB1F.7010409@ti.com>
 <CAJe_ZheEZo7Akri40ixBhWzeefABxiJXG1Juc4zQOPNQqyahUw@mail.gmail.com>
 <518C3CE9.1010603@ti.com>
 <CAJe_ZhfFs5svKPABHWdKA83+LhxA5+Q3LKuJyqyRj_4SMMm_hg@mail.gmail.com>
Message-ID: <518D2346.10805@ti.com>

Jassi,

>>> See how mailbox_startup() tries to balance mbox->ops->startup() and
>>> mailbox_fini() the mbox->ops->shutdown()  That's very fragile and the
>>> cause of imbalance between rpm enable/disable, unless your clients are
>>> buggy.
>>
>> Yeah, it is kinda messed up in the existing code, the startup defined
>> there is really for the controller and not the link, and that's why you
>> see all the ref-counting balancing logic. The rpm enable/disable being
>> called is on the controller's dev, not the link's dev - maybe that's
>> what confused you.
>>
> I wrote the driver for this api, so I do realize the rpm is on
> controller. Links are not devices anyways.
> 

You might be missing the minor detail. The pm_runtime_enable is in
startup, which is called for every link. So, I get an unbalanced
warning, when I have
	ipc_request_channel(client1);  -> link1.startup
	ipc_request_channel(clinet2);  -> link2.startup

Anyway, it is a non-issue since I understand the context and the fix.

regards
Suman





From akpm at linux-foundation.org  Fri May 10 13:03:24 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Fri, 10 May 2013 10:03:24 -0700
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1651579.orCh9JNVz6@vostro.rjw.lan>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-2-git-send-email-holt@sgi.com>
 <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>
 <1651579.orCh9JNVz6@vostro.rjw.lan>
Message-ID: <20130510100324.e1e066ab.akpm@linux-foundation.org>

On Fri, 10 May 2013 13:11:51 +0200 "Rafael J. Wysocki" <rjw at sisk.pl> wrote:

> ...
>
> > cpu_hotplug_disable() doesn't get compiled unless we've defined
> > CONFIG_PM_SLEEP_SMP.  I cannot begin to imagine what the logic is
> > behind that!
> 
> I suppose it was only used by suspend/hibernate code paths when this was
> introduced.

OK, well I suspect that what I have now is simply wrong for Robin's
application.  Robin, can you please check this?  We probably want to
make the does-something version of cpu_hotplug_disable/enable available
if CONFIG_HOTPLUG_CPU.




From soren.brinkmann at xilinx.com  Fri May 10 13:31:30 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Fri, 10 May 2013 10:31:30 -0700
Subject: [PATCH RFC] User space clock driver
Message-ID: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>

Hi,

is there any interest in exposing clock controls to userspace?
On Zynq we need/want this for a couple of clocks which are forwarded to
the FPGA part of the chip, in case no real device driver is taking care
of the clocks.
Additionally I can see this help debugging here and there. E.g. it can
be used to trigger rate change notifications. Hence I started this as a
generic driver instead of limiting it to my primary Zynq use-case.

The current state allows me to control the FPGA clocks on Zynq (other
clocks should work as well), so the functionality is basically there,
but I appreciate all feedback on the implementation. I suspect there
are better/other ways to do this.

	Thanks,
	S?ren

Soren Brinkmann (1):
  clk: Introduce userspace clock driver

 .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
 drivers/clk/Kconfig                                |   9 ++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
 4 files changed, 186 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
 create mode 100644 drivers/clk/clk-userspace.c

-- 
1.8.2.3



From soren.brinkmann at xilinx.com  Fri May 10 13:31:31 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Fri, 10 May 2013 10:31:31 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>

The userspace clock driver can be used to expose clock controls through
sysfs to userspace. The driver creates entries in /sys/class/clk.

Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
---
 .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
 drivers/clk/Kconfig                                |   9 ++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
 4 files changed, 186 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
 create mode 100644 drivers/clk/clk-userspace.c

diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
new file mode 100644
index 0000000..2d153c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
@@ -0,0 +1,7 @@
+
+Example:
+	usclk: usclk {
+		compatible = "clk-userspace";
+		clocks = <&foo 15>, <&bar>;
+		clock-count = <2>;
+	};
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 0357ac4..b35b62c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
 	  FPGAs. It is commonly used in Analog Devices' reference designs.
 
+config COMMON_CLK_USERSPACE
+	bool "Userspace Clock Controls"
+	depends on OF
+	depends on SYSFS
+	help
+	---help---
+	  Expose clock controls through sysfs to userspace. Clocks are selected
+	  through the device tree and the controls are exposed in
+	  /sys/class/clk.
 endmenu
 
 source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fa435bc..f2f68c8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
+obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
new file mode 100644
index 0000000..931cf92
--- /dev/null
+++ b/drivers/clk/clk-userspace.c
@@ -0,0 +1,169 @@
+/*
+ * Userspace clock driver
+ *
+ *  Copyright (C) 2013 Xilinx
+ *
+ *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Expose clock controls through sysfs to userspace.
+ *
+ * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
+ * that file returns the current state - 0 = disabled, 1 = enabled.
+ *
+ * Reading 'set_rate' returns the current clock frequency in Hz. Writing
+ * the file requests setting a new frequency in Hz.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/fs.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+
+#define DRIVER_NAME	"clk-userspace"
+
+struct usclk_data {
+	struct clk *clk;
+	int enabled;
+};
+
+static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct usclk_data *pdata = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
+}
+
+static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	unsigned long enable;
+	int ret;
+	struct usclk_data *pdata = dev_get_drvdata(dev);
+
+	ret = kstrtoul(buf, 0, &enable);
+	if (ret)
+		return -EINVAL;
+
+	enable = !!enable;
+	if (enable == pdata->enabled)
+		return count;
+
+	if (enable)
+		ret = clk_prepare_enable(pdata->clk);
+	else
+		clk_disable_unprepare(pdata->clk);
+
+	if (ret)
+		return -EBUSY;
+
+	pdata->enabled = enable;
+	return count;
+}
+
+static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
+
+static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct usclk_data *pdata = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
+}
+
+static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret = 0;
+	unsigned long rate;
+	struct usclk_data *pdata = dev_get_drvdata(dev);
+
+	ret = kstrtoul(buf, 0, &rate);
+	if (ret)
+		return -EINVAL;
+
+	rate = clk_round_rate(pdata->clk, rate);
+	ret = clk_set_rate(pdata->clk, rate);
+	if (ret)
+		return -EBUSY;
+
+	return count;
+}
+
+static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
+
+static const struct attribute *usclk_attrs[] = {
+	&dev_attr_enable.attr,
+	&dev_attr_set_rate.attr,
+	NULL
+};
+
+static const struct attribute_group usclk_attr_grp = {
+	.attrs = (struct attribute **)usclk_attrs,
+};
+
+static int usclk_setup(void)
+{
+	int ret;
+	int i;
+	struct usclk_data *pdata;
+	u32 clock_count;
+	struct class *clk_class;
+	struct device *dev;
+	struct device_node *np = of_find_compatible_node(NULL, NULL,
+			"clk-userspace");
+
+	ret = of_property_read_u32(np, "clock-count", &clock_count);
+	if (ret || !clock_count)
+		return ret;
+
+	pdata = kzalloc(clock_count * sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	clk_class = class_create(THIS_MODULE, "clk");
+	if (!clk_class) {
+		pr_err("unable to create class\n");
+		goto err_free;
+	}
+
+	for (i = 0; i < clock_count; i++) {
+		pdata[i].clk = of_clk_get(np, i);
+		if (IS_ERR(pdata[i].clk)) {
+			pr_warn("input clock #%u not found\n", i);
+			continue;
+		}
+
+		dev = device_create(clk_class, NULL, MKDEV(0, 0), NULL,
+				of_clk_get_parent_name(np, i));
+		if (!dev) {
+			pr_warn("unable to create device #%d\n", i);
+			continue;
+		}
+
+		dev_set_drvdata(dev, &pdata[i]);
+		sysfs_create_group(&dev->kobj, &usclk_attr_grp);
+	}
+
+	return 0;
+
+err_free:
+	kfree(pdata);
+
+	return ret;
+}
+late_initcall(usclk_setup);
-- 
1.8.2.3



From emilio at elopez.com.ar  Fri May 10 13:44:44 2013
From: emilio at elopez.com.ar (=?UTF-8?B?RW1pbGlvIEzDs3Bleg==?=)
Date: Fri, 10 May 2013 14:44:44 -0300
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <518D320C.4010707@elopez.com.ar>

Hi,

El 10/05/13 14:31, Soren Brinkmann escribi?:
> The userspace clock driver can be used to expose clock controls through
> sysfs to userspace. The driver creates entries in /sys/class/clk.
> 
> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> ---
>  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
>  drivers/clk/Kconfig                                |   9 ++
>  drivers/clk/Makefile                               |   1 +
>  drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
>  4 files changed, 186 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
>  create mode 100644 drivers/clk/clk-userspace.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> new file mode 100644
> index 0000000..2d153c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> @@ -0,0 +1,7 @@
> +
> +Example:
> +	usclk: usclk {
> +		compatible = "clk-userspace";
> +		clocks = <&foo 15>, <&bar>;
> +		clock-count = <2>;
> +	};

Does this belong on DT? It isn't describing hardware, is it?

> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 0357ac4..b35b62c 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
>  	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
>  	  FPGAs. It is commonly used in Analog Devices' reference designs.
>  
> +config COMMON_CLK_USERSPACE
> +	bool "Userspace Clock Controls"
> +	depends on OF
> +	depends on SYSFS
> +	help
> +	---help---
> +	  Expose clock controls through sysfs to userspace. Clocks are selected
> +	  through the device tree and the controls are exposed in
> +	  /sys/class/clk.
>  endmenu
>  
>  source "drivers/clk/mvebu/Kconfig"
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index fa435bc..f2f68c8 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
>  obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
>  obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
>  obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
> +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
>  
>  # SoCs specific
>  obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
> diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
> new file mode 100644
> index 0000000..931cf92
> --- /dev/null
> +++ b/drivers/clk/clk-userspace.c
> @@ -0,0 +1,169 @@
> +/*
> + * Userspace clock driver
> + *
> + *  Copyright (C) 2013 Xilinx
> + *
> + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License v2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * Expose clock controls through sysfs to userspace.
> + *
> + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
> + * that file returns the current state - 0 = disabled, 1 = enabled.
> + *
> + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
> + * the file requests setting a new frequency in Hz.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/fs.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +
> +#define DRIVER_NAME	"clk-userspace"
> +
> +struct usclk_data {
> +	struct clk *clk;
> +	int enabled;
> +};
> +
> +static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
> +		char *buf)
> +{
> +	struct usclk_data *pdata = dev_get_drvdata(dev);
> +
> +	return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
> +}
> +
> +static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
> +		const char *buf, size_t count)
> +{
> +	unsigned long enable;
> +	int ret;
> +	struct usclk_data *pdata = dev_get_drvdata(dev);
> +
> +	ret = kstrtoul(buf, 0, &enable);
> +	if (ret)
> +		return -EINVAL;
> +
> +	enable = !!enable;
> +	if (enable == pdata->enabled)
> +		return count;
> +
> +	if (enable)
> +		ret = clk_prepare_enable(pdata->clk);
> +	else
> +		clk_disable_unprepare(pdata->clk);
> +
> +	if (ret)
> +		return -EBUSY;
> +
> +	pdata->enabled = enable;
> +	return count;
> +}
> +
> +static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
> +
> +static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
> +		char *buf)
> +{
> +	struct usclk_data *pdata = dev_get_drvdata(dev);
> +
> +	return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
> +}
> +
> +static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
> +		const char *buf, size_t count)
> +{
> +	int ret = 0;
> +	unsigned long rate;
> +	struct usclk_data *pdata = dev_get_drvdata(dev);
> +
> +	ret = kstrtoul(buf, 0, &rate);
> +	if (ret)
> +		return -EINVAL;
> +
> +	rate = clk_round_rate(pdata->clk, rate);
> +	ret = clk_set_rate(pdata->clk, rate);
> +	if (ret)
> +		return -EBUSY;
> +
> +	return count;
> +}
> +
> +static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
> +
> +static const struct attribute *usclk_attrs[] = {
> +	&dev_attr_enable.attr,
> +	&dev_attr_set_rate.attr,
> +	NULL
> +};

For debugging purposes, being able to change parents would be nice too.
Maybe this belongs to debugfs instead of sysfs though.

> +
> +static const struct attribute_group usclk_attr_grp = {
> +	.attrs = (struct attribute **)usclk_attrs,
> +};
> +
> +static int usclk_setup(void)
> +{
> +	int ret;
> +	int i;
> +	struct usclk_data *pdata;
> +	u32 clock_count;
> +	struct class *clk_class;
> +	struct device *dev;
> +	struct device_node *np = of_find_compatible_node(NULL, NULL,
> +			"clk-userspace");
> +
> +	ret = of_property_read_u32(np, "clock-count", &clock_count);
> +	if (ret || !clock_count)
> +		return ret;
> +
> +	pdata = kzalloc(clock_count * sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	clk_class = class_create(THIS_MODULE, "clk");
> +	if (!clk_class) {
> +		pr_err("unable to create class\n");
> +		goto err_free;
> +	}
> +
> +	for (i = 0; i < clock_count; i++) {
> +		pdata[i].clk = of_clk_get(np, i);
> +		if (IS_ERR(pdata[i].clk)) {
> +			pr_warn("input clock #%u not found\n", i);
> +			continue;
> +		}
> +
> +		dev = device_create(clk_class, NULL, MKDEV(0, 0), NULL,
> +				of_clk_get_parent_name(np, i));
> +		if (!dev) {
> +			pr_warn("unable to create device #%d\n", i);
> +			continue;
> +		}
> +
> +		dev_set_drvdata(dev, &pdata[i]);
> +		sysfs_create_group(&dev->kobj, &usclk_attr_grp);
> +	}
> +
> +	return 0;
> +
> +err_free:
> +	kfree(pdata);
> +
> +	return ret;
> +}
> +late_initcall(usclk_setup);
> 



From linux at arm.linux.org.uk  Fri May 10 13:43:44 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 10 May 2013 18:43:44 +0100
Subject: [PATCH V2] ARM: bcm281xx: Add L2 support for Rev A2 chips
In-Reply-To: <20130509204434.GA16724@quad.lixom.net>
References: <1367542653-955-1-git-send-email-csd@broadcom.com>
 <20130509204434.GA16724@quad.lixom.net>
Message-ID: <20130510174344.GX18614@n2100.arm.linux.org.uk>

On Thu, May 09, 2013 at 01:44:34PM -0700, Olof Johansson wrote:
> On Thu, May 02, 2013 at 05:57:33PM -0700, Christian Daudt wrote:
> > Rev A2 SoCs have an unorthodox memory re-mapping and this needs
> > to be reflected in the cache operations.
> > This patch adds new outer cache functions for the l2x0 driver
> > to support this SoC revision. It also adds a new compatible
> > value for the cache to enable this functionality.
> > 
> > Updates from V1:
> > - remove section 1 altogether and note that in comments
> > - simplify section selection caused by section 1 removal
> > - BUG_ON just in case section 1 shows up
> > 
> > Signed-off-by: Christian Daudt <csd at broadcom.com>
> 
> This patch mostly covers code that is on Russells plate, so please feed
> this to his tracker to be picked up by him. Feel free to add:

Yes, but there's a problem.  I don't have bcm11351.dtsi to apply this
patch to.  This is one of the problems of splitting the SoC stuff
from core stuff - either I start doing cross-merges (which cause Linus
and everyone else pain as we've seen this time around) or we have to
stuff everything through a single tree.

Not happy.

Not applying until after -rc1.


From linux at prisktech.co.nz  Fri May 10 13:45:56 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 11 May 2013 05:45:56 +1200
Subject: [PATCH] pinctrl: vt8500: Fix incorrect data in WM8750 pinctrl table
Message-ID: <1368207956-32220-1-git-send-email-linux@prisktech.co.nz>

WMT_PIN_WAKEUP1 should be declared as WMT_PIN(0, 17) rather than
WMT_PIN(0, 16). This currently generates a runtime warning because
WMT_PIN_WAKEUP0 is already defined as WMT_PIN(0, 16).

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/pinctrl/vt8500/pinctrl-wm8750.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
index b964cc5..de43262 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8750.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
@@ -53,7 +53,7 @@ static const struct wmt_pinctrl_bank_registers wm8750_banks[] = {
 #define WMT_PIN_EXTGPIO6	WMT_PIN(0, 6)
 #define WMT_PIN_EXTGPIO7	WMT_PIN(0, 7)
 #define WMT_PIN_WAKEUP0		WMT_PIN(0, 16)
-#define WMT_PIN_WAKEUP1		WMT_PIN(0, 16)
+#define WMT_PIN_WAKEUP1		WMT_PIN(0, 17)
 #define WMT_PIN_SD0CD		WMT_PIN(0, 28)
 #define WMT_PIN_VDOUT0		WMT_PIN(1, 0)
 #define WMT_PIN_VDOUT1		WMT_PIN(1, 1)
-- 
1.7.9.5



From soren.brinkmann at xilinx.com  Fri May 10 14:03:22 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 10 May 2013 11:03:22 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <CAHp75Vcr10d=XesGQvrC_v+ijdp3nK+m=w5E7d6GCo1Z9ogWnw@mail.gmail.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <CAHp75Vcr10d=XesGQvrC_v+ijdp3nK+m=w5E7d6GCo1Z9ogWnw@mail.gmail.com>
Message-ID: <b3594fb6-0cbd-45e4-b1aa-813e5b5a3bcd@CO1EHSMHS006.ehs.local>

Hi  Andy,

first, can you please send plain text email? The formatting gets messed up a
bit for me otherwise.

On Fri, May 10, 2013 at 08:42:34PM +0300, Andy Shevchenko wrote:
>    10.5.2013 20.32 "Soren Brinkmann" <soren.brinkmann at xilinx.com> kirjoitti:
>    >
>    > The userspace clock driver can be used to expose clock controls through
>    > sysfs to userspace. The driver creates entries in /sys/class/clk.
>    >
>    > Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
>    > ---
>    >  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
>    >  drivers/clk/Kconfig                                |   9 ++
>    >  drivers/clk/Makefile                               |   1 +
>    >  drivers/clk/clk-userspace.c                        | 169
>    +++++++++++++++++++++
>    >  4 files changed, 186 insertions(+)
>    >  create mode 100644
>    Documentation/devicetree/bindings/clock/clk-userspace.txt
>    >  create mode 100644 drivers/clk/clk-userspace.c
>    >
>    > diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt
>    b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>    > new file mode 100644
>    > index 0000000..2d153c7
>    > --- /dev/null
>    > +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>    > @@ -0,0 +1,7 @@
>    > +
>    > +Example:
>    > +       usclk: usclk {
>    > +               compatible = "clk-userspace";
>    > +               clocks = <&foo 15>, <&bar>;
>    > +               clock-count = <2>;
>    > +       };
>    > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>    > index 0357ac4..b35b62c 100644
>    > --- a/drivers/clk/Kconfig
>    > +++ b/drivers/clk/Kconfig
>    > @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
>    >           Support for the Analog Devices axi-clkgen pcore clock
>    generator for Xilinx
>    >           FPGAs. It is commonly used in Analog Devices' reference
>    designs.
>    >
>    > +config COMMON_CLK_USERSPACE
>    > +       bool "Userspace Clock Controls"
>    > +       depends on OF
>    > +       depends on SYSFS
>    > +       help
>    > +       ---help---
>    > +         Expose clock controls through sysfs to userspace. Clocks are
>    selected
>    > +         through the device tree and the controls are exposed in
>    > +         /sys/class/clk.
>    >  endmenu
>    >
>    >  source "drivers/clk/mvebu/Kconfig"
>    > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>    > index fa435bc..f2f68c8 100644
>    > --- a/drivers/clk/Makefile
>    > +++ b/drivers/clk/Makefile
>    > @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)        += clk-fixed-rate.o
>    >  obj-$(CONFIG_COMMON_CLK)       += clk-gate.o
>    >  obj-$(CONFIG_COMMON_CLK)       += clk-mux.o
>    >  obj-$(CONFIG_COMMON_CLK)       += clk-composite.o
>    > +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
>    >
>    >  # SoCs specific
>    >  obj-$(CONFIG_ARCH_BCM2835)     += clk-bcm2835.o
>    > diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
>    > new file mode 100644
>    > index 0000000..931cf92
>    > --- /dev/null
>    > +++ b/drivers/clk/clk-userspace.c
>    > @@ -0,0 +1,169 @@
>    > +/*
>    > + * Userspace clock driver
>    > + *
>    > + *  Copyright (C) 2013 Xilinx
>    > + *
>    > + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
>    > + *
>    > + * This program is free software: you can redistribute it and/or modify
>    > + * it under the terms of the GNU General Public License v2 as published
>    by
>    > + * the Free Software Foundation.
>    > + *
>    > + * This program is distributed in the hope that it will be useful,
>    > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>    > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>    > + * GNU General Public License for more details.
>    > + *
>    > + * You should have received a copy of the GNU General Public License
>    > + * along with this program.  If not, see
>    <http://www.gnu.org/licenses/>.
>    > + *
>    > + * Expose clock controls through sysfs to userspace.
>    > + *
>    > + * By writing 0/1 to 'enable' the clock can be disabled/enabled.
>    Reading
>    > + * that file returns the current state - 0 = disabled, 1 = enabled.
>    > + *
>    > + * Reading 'set_rate' returns the current clock frequency in Hz.
>    Writing
>    > + * the file requests setting a new frequency in Hz.
>    > + */
>    > +
>    > +#include <linux/clk-provider.h>
>    > +#include <linux/fs.h>
>    > +#include <linux/module.h>
>    > +#include <linux/of.h>
>    > +#include <linux/device.h>
>    > +#include <linux/slab.h>
>    > +
>    > +#define DRIVER_NAME    "clk-userspace"
>    > +
>    > +struct usclk_data {
>    > +       struct clk *clk;
>    > +       int enabled;
>    > +};
>    > +
>    > +static ssize_t enable_show(struct device *dev, struct device_attribute
>    *attr,
>    > +               char *buf)
>    > +{
>    > +       struct usclk_data *pdata = dev_get_drvdata(dev);
>    > +
>    > +       return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
>    > +}
>    > +
>    > +static ssize_t enable_store(struct device *dev, struct device_attribute
>    *attr,
>    > +               const char *buf, size_t count)
>    > +{
>    > +       unsigned long enable;
>    > +       int ret;
>    > +       struct usclk_data *pdata = dev_get_drvdata(dev);
>    > +
>    > +       ret = kstrtoul(buf, 0, &enable);
> 
>    strbool()?
Can you explain this a little more, please? I grepped the kernel sources for
'strbool' and didn't get a single match.

	S?ren




From soren.brinkmann at xilinx.com  Fri May 10 14:15:25 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 10 May 2013 11:15:25 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <518D320C.4010707@elopez.com.ar>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
Message-ID: <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>

Hi Emilio,

On Fri, May 10, 2013 at 02:44:44PM -0300, Emilio L?pez wrote:
> Hi,
> 
> El 10/05/13 14:31, Soren Brinkmann escribi?:
> > The userspace clock driver can be used to expose clock controls through
> > sysfs to userspace. The driver creates entries in /sys/class/clk.
> > 
> > Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> > ---
> >  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
> >  drivers/clk/Kconfig                                |   9 ++
> >  drivers/clk/Makefile                               |   1 +
> >  drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
> >  4 files changed, 186 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
> >  create mode 100644 drivers/clk/clk-userspace.c
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> > new file mode 100644
> > index 0000000..2d153c7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> > @@ -0,0 +1,7 @@
> > +
> > +Example:
> > +	usclk: usclk {
> > +		compatible = "clk-userspace";
> > +		clocks = <&foo 15>, <&bar>;
> > +		clock-count = <2>;
> > +	};
> 
> Does this belong on DT? It isn't describing hardware, is it?
I guess, strictly speaking you are right. Do you have a good
alternative?

> 
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 0357ac4..b35b62c 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
> >  	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
> >  	  FPGAs. It is commonly used in Analog Devices' reference designs.
> >  
> > +config COMMON_CLK_USERSPACE
> > +	bool "Userspace Clock Controls"
> > +	depends on OF
> > +	depends on SYSFS
> > +	help
> > +	---help---
> > +	  Expose clock controls through sysfs to userspace. Clocks are selected
> > +	  through the device tree and the controls are exposed in
> > +	  /sys/class/clk.
> >  endmenu
> >  
> >  source "drivers/clk/mvebu/Kconfig"
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index fa435bc..f2f68c8 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
> >  obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
> >  obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
> >  obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
> > +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
> >  
> >  # SoCs specific
> >  obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
> > diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
> > new file mode 100644
> > index 0000000..931cf92
> > --- /dev/null
> > +++ b/drivers/clk/clk-userspace.c
> > @@ -0,0 +1,169 @@
> > +/*
> > + * Userspace clock driver
> > + *
> > + *  Copyright (C) 2013 Xilinx
> > + *
> > + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License v2 as published by
> > + * the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> > + *
> > + * Expose clock controls through sysfs to userspace.
> > + *
> > + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
> > + * that file returns the current state - 0 = disabled, 1 = enabled.
> > + *
> > + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
> > + * the file requests setting a new frequency in Hz.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/fs.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/device.h>
> > +#include <linux/slab.h>
> > +
> > +#define DRIVER_NAME	"clk-userspace"
> > +
> > +struct usclk_data {
> > +	struct clk *clk;
> > +	int enabled;
> > +};
> > +
> > +static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
> > +		char *buf)
> > +{
> > +	struct usclk_data *pdata = dev_get_drvdata(dev);
> > +
> > +	return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
> > +}
> > +
> > +static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
> > +		const char *buf, size_t count)
> > +{
> > +	unsigned long enable;
> > +	int ret;
> > +	struct usclk_data *pdata = dev_get_drvdata(dev);
> > +
> > +	ret = kstrtoul(buf, 0, &enable);
> > +	if (ret)
> > +		return -EINVAL;
> > +
> > +	enable = !!enable;
> > +	if (enable == pdata->enabled)
> > +		return count;
> > +
> > +	if (enable)
> > +		ret = clk_prepare_enable(pdata->clk);
> > +	else
> > +		clk_disable_unprepare(pdata->clk);
> > +
> > +	if (ret)
> > +		return -EBUSY;
> > +
> > +	pdata->enabled = enable;
> > +	return count;
> > +}
> > +
> > +static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
> > +
> > +static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
> > +		char *buf)
> > +{
> > +	struct usclk_data *pdata = dev_get_drvdata(dev);
> > +
> > +	return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
> > +}
> > +
> > +static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
> > +		const char *buf, size_t count)
> > +{
> > +	int ret = 0;
> > +	unsigned long rate;
> > +	struct usclk_data *pdata = dev_get_drvdata(dev);
> > +
> > +	ret = kstrtoul(buf, 0, &rate);
> > +	if (ret)
> > +		return -EINVAL;
> > +
> > +	rate = clk_round_rate(pdata->clk, rate);
> > +	ret = clk_set_rate(pdata->clk, rate);
> > +	if (ret)
> > +		return -EBUSY;
> > +
> > +	return count;
> > +}
> > +
> > +static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
> > +
> > +static const struct attribute *usclk_attrs[] = {
> > +	&dev_attr_enable.attr,
> > +	&dev_attr_set_rate.attr,
> > +	NULL
> > +};
> 
> For debugging purposes, being able to change parents would be nice too.
This is difficult and I don't have a good solution for it, hence it's
missing. A clock consumer like a device driver or this driver, just
knows about it's input clock, but not about the topology further up.
Therefore it is pretty much impossible to implement reparent operations
in a clock consumer, IMHO.
IOW: For a given input clock, how do you figure out it's possible
parents?

> Maybe this belongs to debugfs instead of sysfs though.
Well, the more generic use-case probably. My Zynq use-case rather not,
IMHO.

	S?ren




From emilio at elopez.com.ar  Fri May 10 14:49:01 2013
From: emilio at elopez.com.ar (=?UTF-8?B?RW1pbGlvIEzDs3Bleg==?=)
Date: Fri, 10 May 2013 15:49:01 -0300
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
Message-ID: <518D411D.9070209@elopez.com.ar>

Hi,

El 10/05/13 15:15, S?ren Brinkmann escribi?:
> Hi Emilio,
> 
> On Fri, May 10, 2013 at 02:44:44PM -0300, Emilio L?pez wrote:
>> Hi,
>>
>> El 10/05/13 14:31, Soren Brinkmann escribi?:
>>> The userspace clock driver can be used to expose clock controls through
>>> sysfs to userspace. The driver creates entries in /sys/class/clk.
>>>
>>> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
>>> ---
>>>  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
>>>  drivers/clk/Kconfig                                |   9 ++
>>>  drivers/clk/Makefile                               |   1 +
>>>  drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
>>>  4 files changed, 186 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>  create mode 100644 drivers/clk/clk-userspace.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>>> new file mode 100644
>>> index 0000000..2d153c7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>>> @@ -0,0 +1,7 @@
>>> +
>>> +Example:
>>> +	usclk: usclk {
>>> +		compatible = "clk-userspace";
>>> +		clocks = <&foo 15>, <&bar>;
>>> +		clock-count = <2>;
>>> +	};
>>
>> Does this belong on DT? It isn't describing hardware, is it?
> I guess, strictly speaking you are right. Do you have a good
> alternative?

If this was part of the framework instead of a consumer, I suppose a
flag on the DT node defining the clock that indicates it should be
exported would be acceptable.

Another possibility would be letting the user export what they need,
like GPIO does, see "Paths in Sysfs" in

https://www.kernel.org/doc/Documentation/gpio.txt

>>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>>> index 0357ac4..b35b62c 100644
>>> --- a/drivers/clk/Kconfig
>>> +++ b/drivers/clk/Kconfig
>>> @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
>>>  	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
>>>  	  FPGAs. It is commonly used in Analog Devices' reference designs.
>>>  
>>> +config COMMON_CLK_USERSPACE
>>> +	bool "Userspace Clock Controls"
>>> +	depends on OF
>>> +	depends on SYSFS
>>> +	help
>>> +	---help---
>>> +	  Expose clock controls through sysfs to userspace. Clocks are selected
>>> +	  through the device tree and the controls are exposed in
>>> +	  /sys/class/clk.
>>>  endmenu
>>>  
>>>  source "drivers/clk/mvebu/Kconfig"
>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>> index fa435bc..f2f68c8 100644
>>> --- a/drivers/clk/Makefile
>>> +++ b/drivers/clk/Makefile
>>> @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
>>>  obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
>>>  obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
>>>  obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
>>> +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
>>>  
>>>  # SoCs specific
>>>  obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
>>> diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
>>> new file mode 100644
>>> index 0000000..931cf92
>>> --- /dev/null
>>> +++ b/drivers/clk/clk-userspace.c
>>> @@ -0,0 +1,169 @@
>>> +/*
>>> + * Userspace clock driver
>>> + *
>>> + *  Copyright (C) 2013 Xilinx
>>> + *
>>> + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
>>> + *
>>> + * This program is free software: you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License v2 as published by
>>> + * the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>>> + *
>>> + * Expose clock controls through sysfs to userspace.
>>> + *
>>> + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
>>> + * that file returns the current state - 0 = disabled, 1 = enabled.
>>> + *
>>> + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
>>> + * the file requests setting a new frequency in Hz.
>>> + */
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/fs.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/device.h>
>>> +#include <linux/slab.h>
>>> +
>>> +#define DRIVER_NAME	"clk-userspace"
>>> +
>>> +struct usclk_data {
>>> +	struct clk *clk;
>>> +	int enabled;
>>> +};
>>> +
>>> +static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
>>> +		char *buf)
>>> +{
>>> +	struct usclk_data *pdata = dev_get_drvdata(dev);
>>> +
>>> +	return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
>>> +}
>>> +
>>> +static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
>>> +		const char *buf, size_t count)
>>> +{
>>> +	unsigned long enable;
>>> +	int ret;
>>> +	struct usclk_data *pdata = dev_get_drvdata(dev);
>>> +
>>> +	ret = kstrtoul(buf, 0, &enable);
>>> +	if (ret)
>>> +		return -EINVAL;
>>> +
>>> +	enable = !!enable;
>>> +	if (enable == pdata->enabled)
>>> +		return count;
>>> +
>>> +	if (enable)
>>> +		ret = clk_prepare_enable(pdata->clk);
>>> +	else
>>> +		clk_disable_unprepare(pdata->clk);
>>> +
>>> +	if (ret)
>>> +		return -EBUSY;
>>> +
>>> +	pdata->enabled = enable;
>>> +	return count;
>>> +}
>>> +
>>> +static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
>>> +
>>> +static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
>>> +		char *buf)
>>> +{
>>> +	struct usclk_data *pdata = dev_get_drvdata(dev);
>>> +
>>> +	return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
>>> +}
>>> +
>>> +static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
>>> +		const char *buf, size_t count)
>>> +{
>>> +	int ret = 0;
>>> +	unsigned long rate;
>>> +	struct usclk_data *pdata = dev_get_drvdata(dev);
>>> +
>>> +	ret = kstrtoul(buf, 0, &rate);
>>> +	if (ret)
>>> +		return -EINVAL;
>>> +
>>> +	rate = clk_round_rate(pdata->clk, rate);
>>> +	ret = clk_set_rate(pdata->clk, rate);
>>> +	if (ret)
>>> +		return -EBUSY;
>>> +
>>> +	return count;
>>> +}
>>> +
>>> +static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
>>> +
>>> +static const struct attribute *usclk_attrs[] = {
>>> +	&dev_attr_enable.attr,
>>> +	&dev_attr_set_rate.attr,
>>> +	NULL
>>> +};
>>
>> For debugging purposes, being able to change parents would be nice too.
> This is difficult and I don't have a good solution for it, hence it's
> missing. A clock consumer like a device driver or this driver, just
> knows about it's input clock, but not about the topology further up.
> Therefore it is pretty much impossible to implement reparent operations
> in a clock consumer, IMHO.
> IOW: For a given input clock, how do you figure out it's possible
> parents?

The parent is just a number

int (*set_parent)(struct clk_hw *hw, u8 index);
u8 (*get_parent)(struct clk_hw *hw);

If you are debugging, you know what the possible parents are, and you
can reparent with that information.

After checking the clk code however, I didn't find any exposed way to
reparent with just the parent indexes. Maybe an interface that takes a n
arbitrary string representing the parent name, and gets that clock and
then sets the parent would fit.

> 
>> Maybe this belongs to debugfs instead of sysfs though.
> Well, the more generic use-case probably. My Zynq use-case rather not,
> IMHO.

The framework already exposes some information on debugfs, maybe
expanding that instead of implementing it as a consumer on sysfs would
be best for the debugging use case. @Mike, what's your thoughts on this?

Emilio


From sergei.shtylyov at cogentembedded.com  Fri May 10 15:38:55 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 10 May 2013 23:38:55 +0400
Subject: [PATCH] ARM: shmobile: r8a7778: correct model name in Kconfig
In-Reply-To: <20130510082055.GB27435@verge.net.au>
References: <201305090405.41053.sergei.shtylyov@cogentembedded.com>
 <20130510082055.GB27435@verge.net.au>
Message-ID: <518D4CCF.5040706@cogentembedded.com>

Hello.

On 05/10/2013 12:20 PM, Simon Horman wrote:

>
>> The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
>> M1S which is a SH based SoC.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Morimoto-san,
>
> please review this change.
>

    This patch was based on the info found on this official Renesas webpage:

http://www.renesas.eu/applications/automotive/cis/cis_highend/rcar_m1as/index.jsp

WBR, Sergei



From sebastian.hesselbarth at gmail.com  Fri May 10 16:12:27 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 10 May 2013 22:12:27 +0200
Subject: [PATCH] ARM: plat-orion: add missing ehci include to common.h
Message-ID: <1368216747-28898-1-git-send-email-sebastian.hesselbarth@gmail.com>

Removing orion ehci include from board files will raise a compiler
error because plat/common.h is using an enum provided by orion ehci
but not including the include itself. This just adds the missing include.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/plat-orion/include/plat/common.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index e06fc5f..d9a24f6 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -10,6 +10,7 @@
 
 #ifndef __PLAT_COMMON_H
 #include <linux/mv643xx_eth.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 
 struct dsa_platform_data;
 struct mv_sata_platform_data;
-- 
1.7.10.4



From mturquette at linaro.org  Fri May 10 18:18:10 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 10 May 2013 15:18:10 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <518D411D.9070209@elopez.com.ar>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
Message-ID: <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>

On Fri, May 10, 2013 at 11:49 AM, Emilio L?pez <emilio at elopez.com.ar> wrote:
> Hi,
>
> El 10/05/13 15:15, S?ren Brinkmann escribi?:
>> Hi Emilio,
>>
>> On Fri, May 10, 2013 at 02:44:44PM -0300, Emilio L?pez wrote:
>>> Hi,
>>>
>>> El 10/05/13 14:31, Soren Brinkmann escribi?:
>>>> The userspace clock driver can be used to expose clock controls through
>>>> sysfs to userspace. The driver creates entries in /sys/class/clk.
>>>>
>>>> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
>>>> ---
>>>>  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
>>>>  drivers/clk/Kconfig                                |   9 ++
>>>>  drivers/clk/Makefile                               |   1 +
>>>>  drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
>>>>  4 files changed, 186 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>>  create mode 100644 drivers/clk/clk-userspace.c
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>> new file mode 100644
>>>> index 0000000..2d153c7
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>> @@ -0,0 +1,7 @@
>>>> +
>>>> +Example:
>>>> +   usclk: usclk {
>>>> +           compatible = "clk-userspace";
>>>> +           clocks = <&foo 15>, <&bar>;
>>>> +           clock-count = <2>;
>>>> +   };
>>>
>>> Does this belong on DT? It isn't describing hardware, is it?
>> I guess, strictly speaking you are right. Do you have a good
>> alternative?
>
> If this was part of the framework instead of a consumer, I suppose a
> flag on the DT node defining the clock that indicates it should be
> exported would be acceptable.
>
> Another possibility would be letting the user export what they need,
> like GPIO does, see "Paths in Sysfs" in
>
> https://www.kernel.org/doc/Documentation/gpio.txt
>
>>>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>>>> index 0357ac4..b35b62c 100644
>>>> --- a/drivers/clk/Kconfig
>>>> +++ b/drivers/clk/Kconfig
>>>> @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
>>>>       Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
>>>>       FPGAs. It is commonly used in Analog Devices' reference designs.
>>>>
>>>> +config COMMON_CLK_USERSPACE
>>>> +   bool "Userspace Clock Controls"
>>>> +   depends on OF
>>>> +   depends on SYSFS
>>>> +   help
>>>> +   ---help---
>>>> +     Expose clock controls through sysfs to userspace. Clocks are selected
>>>> +     through the device tree and the controls are exposed in
>>>> +     /sys/class/clk.
>>>>  endmenu
>>>>
>>>>  source "drivers/clk/mvebu/Kconfig"
>>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>>> index fa435bc..f2f68c8 100644
>>>> --- a/drivers/clk/Makefile
>>>> +++ b/drivers/clk/Makefile
>>>> @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)    += clk-fixed-rate.o
>>>>  obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
>>>>  obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
>>>>  obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
>>>> +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
>>>>
>>>>  # SoCs specific
>>>>  obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
>>>> diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
>>>> new file mode 100644
>>>> index 0000000..931cf92
>>>> --- /dev/null
>>>> +++ b/drivers/clk/clk-userspace.c
>>>> @@ -0,0 +1,169 @@
>>>> +/*
>>>> + * Userspace clock driver
>>>> + *
>>>> + *  Copyright (C) 2013 Xilinx
>>>> + *
>>>> + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
>>>> + *
>>>> + * This program is free software: you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License v2 as published by
>>>> + * the Free Software Foundation.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>> + * GNU General Public License for more details.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public License
>>>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>>>> + *
>>>> + * Expose clock controls through sysfs to userspace.
>>>> + *
>>>> + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
>>>> + * that file returns the current state - 0 = disabled, 1 = enabled.
>>>> + *
>>>> + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
>>>> + * the file requests setting a new frequency in Hz.
>>>> + */
>>>> +
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/fs.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/device.h>
>>>> +#include <linux/slab.h>
>>>> +
>>>> +#define DRIVER_NAME        "clk-userspace"
>>>> +
>>>> +struct usclk_data {
>>>> +   struct clk *clk;
>>>> +   int enabled;
>>>> +};
>>>> +
>>>> +static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
>>>> +           char *buf)
>>>> +{
>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>> +
>>>> +   return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
>>>> +}
>>>> +
>>>> +static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
>>>> +           const char *buf, size_t count)
>>>> +{
>>>> +   unsigned long enable;
>>>> +   int ret;
>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>> +
>>>> +   ret = kstrtoul(buf, 0, &enable);
>>>> +   if (ret)
>>>> +           return -EINVAL;
>>>> +
>>>> +   enable = !!enable;
>>>> +   if (enable == pdata->enabled)
>>>> +           return count;
>>>> +
>>>> +   if (enable)
>>>> +           ret = clk_prepare_enable(pdata->clk);
>>>> +   else
>>>> +           clk_disable_unprepare(pdata->clk);
>>>> +
>>>> +   if (ret)
>>>> +           return -EBUSY;
>>>> +
>>>> +   pdata->enabled = enable;
>>>> +   return count;
>>>> +}
>>>> +
>>>> +static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
>>>> +
>>>> +static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
>>>> +           char *buf)
>>>> +{
>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>> +
>>>> +   return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
>>>> +}
>>>> +
>>>> +static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
>>>> +           const char *buf, size_t count)
>>>> +{
>>>> +   int ret = 0;
>>>> +   unsigned long rate;
>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>> +
>>>> +   ret = kstrtoul(buf, 0, &rate);
>>>> +   if (ret)
>>>> +           return -EINVAL;
>>>> +
>>>> +   rate = clk_round_rate(pdata->clk, rate);
>>>> +   ret = clk_set_rate(pdata->clk, rate);
>>>> +   if (ret)
>>>> +           return -EBUSY;
>>>> +
>>>> +   return count;
>>>> +}
>>>> +
>>>> +static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
>>>> +
>>>> +static const struct attribute *usclk_attrs[] = {
>>>> +   &dev_attr_enable.attr,
>>>> +   &dev_attr_set_rate.attr,
>>>> +   NULL
>>>> +};
>>>
>>> For debugging purposes, being able to change parents would be nice too.
>> This is difficult and I don't have a good solution for it, hence it's
>> missing. A clock consumer like a device driver or this driver, just
>> knows about it's input clock, but not about the topology further up.
>> Therefore it is pretty much impossible to implement reparent operations
>> in a clock consumer, IMHO.
>> IOW: For a given input clock, how do you figure out it's possible
>> parents?
>
> The parent is just a number
>
> int (*set_parent)(struct clk_hw *hw, u8 index);
> u8 (*get_parent)(struct clk_hw *hw);
>
> If you are debugging, you know what the possible parents are, and you
> can reparent with that information.
>
> After checking the clk code however, I didn't find any exposed way to
> reparent with just the parent indexes. Maybe an interface that takes a n
> arbitrary string representing the parent name, and gets that clock and
> then sets the parent would fit.
>
>>
>>> Maybe this belongs to debugfs instead of sysfs though.
>> Well, the more generic use-case probably. My Zynq use-case rather not,
>> IMHO.
>
> The framework already exposes some information on debugfs, maybe
> expanding that instead of implementing it as a consumer on sysfs would
> be best for the debugging use case. @Mike, what's your thoughts on this?
>

In the previous thread on this topic we discussed a generic approach
to exposing clock controls via debugfs.

One way to do it is to introduce a new config option,
CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
every clock in the existing debugfs infrastructure.  The downside to
this approach is that it would get abused and ship in millions of
Android products using horrible userspace hacks to control clocks.
Maybe that's not our problem to solve, maybe it is.

If CONFIG_COMMON_CLK_DEBUG_CONTROL existed it might be a good idea to
intentionally break the abi compatibility with every new release.
That would certainly reinforce that this is not a condoned or stable
api (which is true for all debugfs).

I think that Soren wants something with a stable interface that he can
use for his Zynq use case.  Regarding that, why not write an actual
device driver to do what you want to do from userspace?

Regards,
Mike

> Emilio


From skannan at codeaurora.org  Fri May 10 19:01:25 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 10 May 2013 16:01:25 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
Message-ID: <518D7C45.2090602@codeaurora.org>

On 05/10/2013 03:18 PM, Mike Turquette wrote:
> On Fri, May 10, 2013 at 11:49 AM, Emilio L?pez <emilio at elopez.com.ar> wrote:
>> Hi,
>>
>> El 10/05/13 15:15, S?ren Brinkmann escribi?:
>>> Hi Emilio,
>>>
>>> On Fri, May 10, 2013 at 02:44:44PM -0300, Emilio L?pez wrote:
>>>> Hi,
>>>>
>>>> El 10/05/13 14:31, Soren Brinkmann escribi?:
>>>>> The userspace clock driver can be used to expose clock controls through
>>>>> sysfs to userspace. The driver creates entries in /sys/class/clk.
>>>>>
>>>>> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
>>>>> ---
>>>>>   .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
>>>>>   drivers/clk/Kconfig                                |   9 ++
>>>>>   drivers/clk/Makefile                               |   1 +
>>>>>   drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
>>>>>   4 files changed, 186 insertions(+)
>>>>>   create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>>>   create mode 100644 drivers/clk/clk-userspace.c
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>>> new file mode 100644
>>>>> index 0000000..2d153c7
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
>>>>> @@ -0,0 +1,7 @@
>>>>> +
>>>>> +Example:
>>>>> +   usclk: usclk {
>>>>> +           compatible = "clk-userspace";
>>>>> +           clocks = <&foo 15>, <&bar>;
>>>>> +           clock-count = <2>;
>>>>> +   };
>>>>
>>>> Does this belong on DT? It isn't describing hardware, is it?
>>> I guess, strictly speaking you are right. Do you have a good
>>> alternative?
>>
>> If this was part of the framework instead of a consumer, I suppose a
>> flag on the DT node defining the clock that indicates it should be
>> exported would be acceptable.
>>
>> Another possibility would be letting the user export what they need,
>> like GPIO does, see "Paths in Sysfs" in
>>
>> https://www.kernel.org/doc/Documentation/gpio.txt
>>
>>>>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>>>>> index 0357ac4..b35b62c 100644
>>>>> --- a/drivers/clk/Kconfig
>>>>> +++ b/drivers/clk/Kconfig
>>>>> @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
>>>>>        Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
>>>>>        FPGAs. It is commonly used in Analog Devices' reference designs.
>>>>>
>>>>> +config COMMON_CLK_USERSPACE
>>>>> +   bool "Userspace Clock Controls"
>>>>> +   depends on OF
>>>>> +   depends on SYSFS
>>>>> +   help
>>>>> +   ---help---
>>>>> +     Expose clock controls through sysfs to userspace. Clocks are selected
>>>>> +     through the device tree and the controls are exposed in
>>>>> +     /sys/class/clk.
>>>>>   endmenu
>>>>>
>>>>>   source "drivers/clk/mvebu/Kconfig"
>>>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>>>> index fa435bc..f2f68c8 100644
>>>>> --- a/drivers/clk/Makefile
>>>>> +++ b/drivers/clk/Makefile
>>>>> @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)    += clk-fixed-rate.o
>>>>>   obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
>>>>>   obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
>>>>>   obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
>>>>> +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
>>>>>
>>>>>   # SoCs specific
>>>>>   obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
>>>>> diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
>>>>> new file mode 100644
>>>>> index 0000000..931cf92
>>>>> --- /dev/null
>>>>> +++ b/drivers/clk/clk-userspace.c
>>>>> @@ -0,0 +1,169 @@
>>>>> +/*
>>>>> + * Userspace clock driver
>>>>> + *
>>>>> + *  Copyright (C) 2013 Xilinx
>>>>> + *
>>>>> + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
>>>>> + *
>>>>> + * This program is free software: you can redistribute it and/or modify
>>>>> + * it under the terms of the GNU General Public License v2 as published by
>>>>> + * the Free Software Foundation.
>>>>> + *
>>>>> + * This program is distributed in the hope that it will be useful,
>>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>> + * GNU General Public License for more details.
>>>>> + *
>>>>> + * You should have received a copy of the GNU General Public License
>>>>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>>>>> + *
>>>>> + * Expose clock controls through sysfs to userspace.
>>>>> + *
>>>>> + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
>>>>> + * that file returns the current state - 0 = disabled, 1 = enabled.
>>>>> + *
>>>>> + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
>>>>> + * the file requests setting a new frequency in Hz.
>>>>> + */
>>>>> +
>>>>> +#include <linux/clk-provider.h>
>>>>> +#include <linux/fs.h>
>>>>> +#include <linux/module.h>
>>>>> +#include <linux/of.h>
>>>>> +#include <linux/device.h>
>>>>> +#include <linux/slab.h>
>>>>> +
>>>>> +#define DRIVER_NAME        "clk-userspace"
>>>>> +
>>>>> +struct usclk_data {
>>>>> +   struct clk *clk;
>>>>> +   int enabled;
>>>>> +};
>>>>> +
>>>>> +static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
>>>>> +           char *buf)
>>>>> +{
>>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>>> +
>>>>> +   return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
>>>>> +}
>>>>> +
>>>>> +static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
>>>>> +           const char *buf, size_t count)
>>>>> +{
>>>>> +   unsigned long enable;
>>>>> +   int ret;
>>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>>> +
>>>>> +   ret = kstrtoul(buf, 0, &enable);
>>>>> +   if (ret)
>>>>> +           return -EINVAL;
>>>>> +
>>>>> +   enable = !!enable;
>>>>> +   if (enable == pdata->enabled)
>>>>> +           return count;
>>>>> +
>>>>> +   if (enable)
>>>>> +           ret = clk_prepare_enable(pdata->clk);
>>>>> +   else
>>>>> +           clk_disable_unprepare(pdata->clk);
>>>>> +
>>>>> +   if (ret)
>>>>> +           return -EBUSY;
>>>>> +
>>>>> +   pdata->enabled = enable;
>>>>> +   return count;
>>>>> +}
>>>>> +
>>>>> +static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
>>>>> +
>>>>> +static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
>>>>> +           char *buf)
>>>>> +{
>>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>>> +
>>>>> +   return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
>>>>> +}
>>>>> +
>>>>> +static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
>>>>> +           const char *buf, size_t count)
>>>>> +{
>>>>> +   int ret = 0;
>>>>> +   unsigned long rate;
>>>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
>>>>> +
>>>>> +   ret = kstrtoul(buf, 0, &rate);
>>>>> +   if (ret)
>>>>> +           return -EINVAL;
>>>>> +
>>>>> +   rate = clk_round_rate(pdata->clk, rate);
>>>>> +   ret = clk_set_rate(pdata->clk, rate);
>>>>> +   if (ret)
>>>>> +           return -EBUSY;
>>>>> +
>>>>> +   return count;
>>>>> +}
>>>>> +
>>>>> +static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
>>>>> +
>>>>> +static const struct attribute *usclk_attrs[] = {
>>>>> +   &dev_attr_enable.attr,
>>>>> +   &dev_attr_set_rate.attr,
>>>>> +   NULL
>>>>> +};
>>>>
>>>> For debugging purposes, being able to change parents would be nice too.
>>> This is difficult and I don't have a good solution for it, hence it's
>>> missing. A clock consumer like a device driver or this driver, just
>>> knows about it's input clock, but not about the topology further up.
>>> Therefore it is pretty much impossible to implement reparent operations
>>> in a clock consumer, IMHO.
>>> IOW: For a given input clock, how do you figure out it's possible
>>> parents?
>>
>> The parent is just a number
>>
>> int (*set_parent)(struct clk_hw *hw, u8 index);
>> u8 (*get_parent)(struct clk_hw *hw);
>>
>> If you are debugging, you know what the possible parents are, and you
>> can reparent with that information.
>>
>> After checking the clk code however, I didn't find any exposed way to
>> reparent with just the parent indexes. Maybe an interface that takes a n
>> arbitrary string representing the parent name, and gets that clock and
>> then sets the parent would fit.
>>
>>>
>>>> Maybe this belongs to debugfs instead of sysfs though.
>>> Well, the more generic use-case probably. My Zynq use-case rather not,
>>> IMHO.
>>
>> The framework already exposes some information on debugfs, maybe
>> expanding that instead of implementing it as a consumer on sysfs would
>> be best for the debugging use case. @Mike, what's your thoughts on this?
>>
>
> In the previous thread on this topic we discussed a generic approach
> to exposing clock controls via debugfs.
>
> One way to do it is to introduce a new config option,
> CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
> every clock in the existing debugfs infrastructure.  The downside to
> this approach is that it would get abused and ship in millions of
> Android products using horrible userspace hacks to control clocks.
> Maybe that's not our problem to solve, maybe it is.

We already have this for MSM. But I seem to have managed to keep our 
userspace guys away from abusing it. YMMV.

> If CONFIG_COMMON_CLK_DEBUG_CONTROL existed it might be a good idea to
> intentionally break the abi compatibility with every new release.
> That would certainly reinforce that this is not a condoned or stable
> api (which is true for all debugfs).

+1 if we can do this. Just in a minor way so that we don't end up making 
it unusable for humans. We also have userspace test scripts for that 
that we can try to upstream (I can't guarantees) -- so we can't go all 
crazy when we do the intentional ABI breaking. We could make them 
root-only in hopes of discouraging abuse of the API. In the sense, using 
this API introduces security concerns because their userspace will be 
running as root.

> I think that Soren wants something with a stable interface that he can
> use for his Zynq use case.  Regarding that, why not write an actual
> device driver to do what you want to do from userspace?

Exposing clock control to userspace production use is a terrible idea. A 
misbehaving userspace can easily kill the system. This is not so try for 
GPIO. So, exposing GPIOs to userspace is relatively less of a concern.

-Saravana
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Fri May 10 19:03:31 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 10 May 2013 16:03:31 -0700
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing
 is done
In-Reply-To: <20130510064520.GI3041@game.jcrosoft.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
 <20130510064520.GI3041@game.jcrosoft.org>
Message-ID: <518D7CC3.6050000@codeaurora.org>

On 05/09/2013 11:45 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:35 Thu 09 May     , Saravana Kannan wrote:
>> With deferred probing, late_initcall() is too soon to declare a clock as
>> unused. Wait for deferred probing to finish before declaring a clock as
>> unused. Since deferred probing is done in late_initcall(), do the unused
>> check to late_initcall_sync.
>
> Nack for both regulator & clk
>
> you can not known when the clock need to be shutdown
>
> example display splash screen set by the bootloader and display as module
>
> Best Regards,
> J.

You are joking right? This is already done in the kernel. If you don't 
want that, please rip out the code and try to get that picked up. I'm 
sending out this patch for fix what's currently in the kernel for those 
who care for the current feature.

Regards,
Saravana


-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From soren.brinkmann at xilinx.com  Fri May 10 19:06:33 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 10 May 2013 16:06:33 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <518D7C45.2090602@codeaurora.org>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
 <518D7C45.2090602@codeaurora.org>
Message-ID: <82612ce3-3be2-46fe-925c-3aa6ca743e7d@CO1EHSMHS004.ehs.local>

On Fri, May 10, 2013 at 04:01:25PM -0700, Saravana Kannan wrote:
> On 05/10/2013 03:18 PM, Mike Turquette wrote:
> >On Fri, May 10, 2013 at 11:49 AM, Emilio L?pez <emilio at elopez.com.ar> wrote:
> >>Hi,
> >>
> >>El 10/05/13 15:15, S?ren Brinkmann escribi?:
> >>>Hi Emilio,
> >>>
> >>>On Fri, May 10, 2013 at 02:44:44PM -0300, Emilio L?pez wrote:
> >>>>Hi,
> >>>>
> >>>>El 10/05/13 14:31, Soren Brinkmann escribi?:
> >>>>>The userspace clock driver can be used to expose clock controls through
> >>>>>sysfs to userspace. The driver creates entries in /sys/class/clk.
> >>>>>
> >>>>>Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> >>>>>---
> >>>>>  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
> >>>>>  drivers/clk/Kconfig                                |   9 ++
> >>>>>  drivers/clk/Makefile                               |   1 +
> >>>>>  drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
> >>>>>  4 files changed, 186 insertions(+)
> >>>>>  create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
> >>>>>  create mode 100644 drivers/clk/clk-userspace.c
> >>>>>
> >>>>>diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> >>>>>new file mode 100644
> >>>>>index 0000000..2d153c7
> >>>>>--- /dev/null
> >>>>>+++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> >>>>>@@ -0,0 +1,7 @@
> >>>>>+
> >>>>>+Example:
> >>>>>+   usclk: usclk {
> >>>>>+           compatible = "clk-userspace";
> >>>>>+           clocks = <&foo 15>, <&bar>;
> >>>>>+           clock-count = <2>;
> >>>>>+   };
> >>>>
> >>>>Does this belong on DT? It isn't describing hardware, is it?
> >>>I guess, strictly speaking you are right. Do you have a good
> >>>alternative?
> >>
> >>If this was part of the framework instead of a consumer, I suppose a
> >>flag on the DT node defining the clock that indicates it should be
> >>exported would be acceptable.
> >>
> >>Another possibility would be letting the user export what they need,
> >>like GPIO does, see "Paths in Sysfs" in
> >>
> >>https://www.kernel.org/doc/Documentation/gpio.txt
> >>
> >>>>>diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> >>>>>index 0357ac4..b35b62c 100644
> >>>>>--- a/drivers/clk/Kconfig
> >>>>>+++ b/drivers/clk/Kconfig
> >>>>>@@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
> >>>>>       Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
> >>>>>       FPGAs. It is commonly used in Analog Devices' reference designs.
> >>>>>
> >>>>>+config COMMON_CLK_USERSPACE
> >>>>>+   bool "Userspace Clock Controls"
> >>>>>+   depends on OF
> >>>>>+   depends on SYSFS
> >>>>>+   help
> >>>>>+   ---help---
> >>>>>+     Expose clock controls through sysfs to userspace. Clocks are selected
> >>>>>+     through the device tree and the controls are exposed in
> >>>>>+     /sys/class/clk.
> >>>>>  endmenu
> >>>>>
> >>>>>  source "drivers/clk/mvebu/Kconfig"
> >>>>>diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> >>>>>index fa435bc..f2f68c8 100644
> >>>>>--- a/drivers/clk/Makefile
> >>>>>+++ b/drivers/clk/Makefile
> >>>>>@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)    += clk-fixed-rate.o
> >>>>>  obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
> >>>>>  obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
> >>>>>  obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
> >>>>>+obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
> >>>>>
> >>>>>  # SoCs specific
> >>>>>  obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
> >>>>>diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
> >>>>>new file mode 100644
> >>>>>index 0000000..931cf92
> >>>>>--- /dev/null
> >>>>>+++ b/drivers/clk/clk-userspace.c
> >>>>>@@ -0,0 +1,169 @@
> >>>>>+/*
> >>>>>+ * Userspace clock driver
> >>>>>+ *
> >>>>>+ *  Copyright (C) 2013 Xilinx
> >>>>>+ *
> >>>>>+ *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
> >>>>>+ *
> >>>>>+ * This program is free software: you can redistribute it and/or modify
> >>>>>+ * it under the terms of the GNU General Public License v2 as published by
> >>>>>+ * the Free Software Foundation.
> >>>>>+ *
> >>>>>+ * This program is distributed in the hope that it will be useful,
> >>>>>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>>>>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>>>>+ * GNU General Public License for more details.
> >>>>>+ *
> >>>>>+ * You should have received a copy of the GNU General Public License
> >>>>>+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> >>>>>+ *
> >>>>>+ * Expose clock controls through sysfs to userspace.
> >>>>>+ *
> >>>>>+ * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
> >>>>>+ * that file returns the current state - 0 = disabled, 1 = enabled.
> >>>>>+ *
> >>>>>+ * Reading 'set_rate' returns the current clock frequency in Hz. Writing
> >>>>>+ * the file requests setting a new frequency in Hz.
> >>>>>+ */
> >>>>>+
> >>>>>+#include <linux/clk-provider.h>
> >>>>>+#include <linux/fs.h>
> >>>>>+#include <linux/module.h>
> >>>>>+#include <linux/of.h>
> >>>>>+#include <linux/device.h>
> >>>>>+#include <linux/slab.h>
> >>>>>+
> >>>>>+#define DRIVER_NAME        "clk-userspace"
> >>>>>+
> >>>>>+struct usclk_data {
> >>>>>+   struct clk *clk;
> >>>>>+   int enabled;
> >>>>>+};
> >>>>>+
> >>>>>+static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
> >>>>>+           char *buf)
> >>>>>+{
> >>>>>+   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>>>+
> >>>>>+   return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
> >>>>>+}
> >>>>>+
> >>>>>+static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
> >>>>>+           const char *buf, size_t count)
> >>>>>+{
> >>>>>+   unsigned long enable;
> >>>>>+   int ret;
> >>>>>+   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>>>+
> >>>>>+   ret = kstrtoul(buf, 0, &enable);
> >>>>>+   if (ret)
> >>>>>+           return -EINVAL;
> >>>>>+
> >>>>>+   enable = !!enable;
> >>>>>+   if (enable == pdata->enabled)
> >>>>>+           return count;
> >>>>>+
> >>>>>+   if (enable)
> >>>>>+           ret = clk_prepare_enable(pdata->clk);
> >>>>>+   else
> >>>>>+           clk_disable_unprepare(pdata->clk);
> >>>>>+
> >>>>>+   if (ret)
> >>>>>+           return -EBUSY;
> >>>>>+
> >>>>>+   pdata->enabled = enable;
> >>>>>+   return count;
> >>>>>+}
> >>>>>+
> >>>>>+static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
> >>>>>+
> >>>>>+static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
> >>>>>+           char *buf)
> >>>>>+{
> >>>>>+   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>>>+
> >>>>>+   return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
> >>>>>+}
> >>>>>+
> >>>>>+static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
> >>>>>+           const char *buf, size_t count)
> >>>>>+{
> >>>>>+   int ret = 0;
> >>>>>+   unsigned long rate;
> >>>>>+   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>>>+
> >>>>>+   ret = kstrtoul(buf, 0, &rate);
> >>>>>+   if (ret)
> >>>>>+           return -EINVAL;
> >>>>>+
> >>>>>+   rate = clk_round_rate(pdata->clk, rate);
> >>>>>+   ret = clk_set_rate(pdata->clk, rate);
> >>>>>+   if (ret)
> >>>>>+           return -EBUSY;
> >>>>>+
> >>>>>+   return count;
> >>>>>+}
> >>>>>+
> >>>>>+static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
> >>>>>+
> >>>>>+static const struct attribute *usclk_attrs[] = {
> >>>>>+   &dev_attr_enable.attr,
> >>>>>+   &dev_attr_set_rate.attr,
> >>>>>+   NULL
> >>>>>+};
> >>>>
> >>>>For debugging purposes, being able to change parents would be nice too.
> >>>This is difficult and I don't have a good solution for it, hence it's
> >>>missing. A clock consumer like a device driver or this driver, just
> >>>knows about it's input clock, but not about the topology further up.
> >>>Therefore it is pretty much impossible to implement reparent operations
> >>>in a clock consumer, IMHO.
> >>>IOW: For a given input clock, how do you figure out it's possible
> >>>parents?
> >>
> >>The parent is just a number
> >>
> >>int (*set_parent)(struct clk_hw *hw, u8 index);
> >>u8 (*get_parent)(struct clk_hw *hw);
> >>
> >>If you are debugging, you know what the possible parents are, and you
> >>can reparent with that information.
> >>
> >>After checking the clk code however, I didn't find any exposed way to
> >>reparent with just the parent indexes. Maybe an interface that takes a n
> >>arbitrary string representing the parent name, and gets that clock and
> >>then sets the parent would fit.
> >>
> >>>
> >>>>Maybe this belongs to debugfs instead of sysfs though.
> >>>Well, the more generic use-case probably. My Zynq use-case rather not,
> >>>IMHO.
> >>
> >>The framework already exposes some information on debugfs, maybe
> >>expanding that instead of implementing it as a consumer on sysfs would
> >>be best for the debugging use case. @Mike, what's your thoughts on this?
> >>
> >
> >In the previous thread on this topic we discussed a generic approach
> >to exposing clock controls via debugfs.
> >
> >One way to do it is to introduce a new config option,
> >CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
> >every clock in the existing debugfs infrastructure.  The downside to
> >this approach is that it would get abused and ship in millions of
> >Android products using horrible userspace hacks to control clocks.
> >Maybe that's not our problem to solve, maybe it is.
> 
> We already have this for MSM. But I seem to have managed to keep our
> userspace guys away from abusing it. YMMV.
> 
> >If CONFIG_COMMON_CLK_DEBUG_CONTROL existed it might be a good idea to
> >intentionally break the abi compatibility with every new release.
> >That would certainly reinforce that this is not a condoned or stable
> >api (which is true for all debugfs).
> 
> +1 if we can do this. Just in a minor way so that we don't end up
> making it unusable for humans. We also have userspace test scripts
> for that that we can try to upstream (I can't guarantees) -- so we
> can't go all crazy when we do the intentional ABI breaking. We could
> make them root-only in hopes of discouraging abuse of the API. In
> the sense, using this API introduces security concerns because their
> userspace will be running as root.
> 
> >I think that Soren wants something with a stable interface that he can
> >use for his Zynq use case.  Regarding that, why not write an actual
> >device driver to do what you want to do from userspace?
> 
> Exposing clock control to userspace production use is a terrible
> idea. A misbehaving userspace can easily kill the system. This is
> not so try for GPIO. So, exposing GPIOs to userspace is relatively
> less of a concern.
Well, the FPGA clocks are only used by stuff in the FPGA. They cannot
mess up the Linux on the A9s. I my use-case is kinda special. And people
request functionality to easily adjust the frequency for their FPGA
design in SW from Linux.
Nevertheless, there is no real protection from taking the driver I'm
proposing to control the FPGA clocks to control a clock vital to the
system.

	S?ren




From soren.brinkmann at xilinx.com  Fri May 10 19:08:27 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 10 May 2013 16:08:27 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
Message-ID: <399a6296-f77f-494e-93cd-98ac15a5196a@TX2EHSMHS012.ehs.local>

On Fri, May 10, 2013 at 03:18:10PM -0700, Mike Turquette wrote:
> On Fri, May 10, 2013 at 11:49 AM, Emilio L?pez <emilio at elopez.com.ar> wrote:
> > Hi,
> >
> > El 10/05/13 15:15, S?ren Brinkmann escribi?:
> >> Hi Emilio,
> >>
> >> On Fri, May 10, 2013 at 02:44:44PM -0300, Emilio L?pez wrote:
> >>> Hi,
> >>>
> >>> El 10/05/13 14:31, Soren Brinkmann escribi?:
> >>>> The userspace clock driver can be used to expose clock controls through
> >>>> sysfs to userspace. The driver creates entries in /sys/class/clk.
> >>>>
> >>>> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> >>>> ---
> >>>>  .../devicetree/bindings/clock/clk-userspace.txt    |   7 +
> >>>>  drivers/clk/Kconfig                                |   9 ++
> >>>>  drivers/clk/Makefile                               |   1 +
> >>>>  drivers/clk/clk-userspace.c                        | 169 +++++++++++++++++++++
> >>>>  4 files changed, 186 insertions(+)
> >>>>  create mode 100644 Documentation/devicetree/bindings/clock/clk-userspace.txt
> >>>>  create mode 100644 drivers/clk/clk-userspace.c
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/clock/clk-userspace.txt b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> >>>> new file mode 100644
> >>>> index 0000000..2d153c7
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/clock/clk-userspace.txt
> >>>> @@ -0,0 +1,7 @@
> >>>> +
> >>>> +Example:
> >>>> +   usclk: usclk {
> >>>> +           compatible = "clk-userspace";
> >>>> +           clocks = <&foo 15>, <&bar>;
> >>>> +           clock-count = <2>;
> >>>> +   };
> >>>
> >>> Does this belong on DT? It isn't describing hardware, is it?
> >> I guess, strictly speaking you are right. Do you have a good
> >> alternative?
> >
> > If this was part of the framework instead of a consumer, I suppose a
> > flag on the DT node defining the clock that indicates it should be
> > exported would be acceptable.
> >
> > Another possibility would be letting the user export what they need,
> > like GPIO does, see "Paths in Sysfs" in
> >
> > https://www.kernel.org/doc/Documentation/gpio.txt
> >
> >>>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> >>>> index 0357ac4..b35b62c 100644
> >>>> --- a/drivers/clk/Kconfig
> >>>> +++ b/drivers/clk/Kconfig
> >>>> @@ -81,6 +81,15 @@ config COMMON_CLK_AXI_CLKGEN
> >>>>       Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
> >>>>       FPGAs. It is commonly used in Analog Devices' reference designs.
> >>>>
> >>>> +config COMMON_CLK_USERSPACE
> >>>> +   bool "Userspace Clock Controls"
> >>>> +   depends on OF
> >>>> +   depends on SYSFS
> >>>> +   help
> >>>> +   ---help---
> >>>> +     Expose clock controls through sysfs to userspace. Clocks are selected
> >>>> +     through the device tree and the controls are exposed in
> >>>> +     /sys/class/clk.
> >>>>  endmenu
> >>>>
> >>>>  source "drivers/clk/mvebu/Kconfig"
> >>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> >>>> index fa435bc..f2f68c8 100644
> >>>> --- a/drivers/clk/Makefile
> >>>> +++ b/drivers/clk/Makefile
> >>>> @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)    += clk-fixed-rate.o
> >>>>  obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
> >>>>  obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
> >>>>  obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
> >>>> +obj-$(CONFIG_COMMON_CLK_USERSPACE) += clk-userspace.o
> >>>>
> >>>>  # SoCs specific
> >>>>  obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
> >>>> diff --git a/drivers/clk/clk-userspace.c b/drivers/clk/clk-userspace.c
> >>>> new file mode 100644
> >>>> index 0000000..931cf92
> >>>> --- /dev/null
> >>>> +++ b/drivers/clk/clk-userspace.c
> >>>> @@ -0,0 +1,169 @@
> >>>> +/*
> >>>> + * Userspace clock driver
> >>>> + *
> >>>> + *  Copyright (C) 2013 Xilinx
> >>>> + *
> >>>> + *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
> >>>> + *
> >>>> + * This program is free software: you can redistribute it and/or modify
> >>>> + * it under the terms of the GNU General Public License v2 as published by
> >>>> + * the Free Software Foundation.
> >>>> + *
> >>>> + * This program is distributed in the hope that it will be useful,
> >>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>>> + * GNU General Public License for more details.
> >>>> + *
> >>>> + * You should have received a copy of the GNU General Public License
> >>>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> >>>> + *
> >>>> + * Expose clock controls through sysfs to userspace.
> >>>> + *
> >>>> + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
> >>>> + * that file returns the current state - 0 = disabled, 1 = enabled.
> >>>> + *
> >>>> + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
> >>>> + * the file requests setting a new frequency in Hz.
> >>>> + */
> >>>> +
> >>>> +#include <linux/clk-provider.h>
> >>>> +#include <linux/fs.h>
> >>>> +#include <linux/module.h>
> >>>> +#include <linux/of.h>
> >>>> +#include <linux/device.h>
> >>>> +#include <linux/slab.h>
> >>>> +
> >>>> +#define DRIVER_NAME        "clk-userspace"
> >>>> +
> >>>> +struct usclk_data {
> >>>> +   struct clk *clk;
> >>>> +   int enabled;
> >>>> +};
> >>>> +
> >>>> +static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
> >>>> +           char *buf)
> >>>> +{
> >>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>> +
> >>>> +   return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
> >>>> +}
> >>>> +
> >>>> +static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
> >>>> +           const char *buf, size_t count)
> >>>> +{
> >>>> +   unsigned long enable;
> >>>> +   int ret;
> >>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>> +
> >>>> +   ret = kstrtoul(buf, 0, &enable);
> >>>> +   if (ret)
> >>>> +           return -EINVAL;
> >>>> +
> >>>> +   enable = !!enable;
> >>>> +   if (enable == pdata->enabled)
> >>>> +           return count;
> >>>> +
> >>>> +   if (enable)
> >>>> +           ret = clk_prepare_enable(pdata->clk);
> >>>> +   else
> >>>> +           clk_disable_unprepare(pdata->clk);
> >>>> +
> >>>> +   if (ret)
> >>>> +           return -EBUSY;
> >>>> +
> >>>> +   pdata->enabled = enable;
> >>>> +   return count;
> >>>> +}
> >>>> +
> >>>> +static DEVICE_ATTR(enable, 0644, enable_show, enable_store);
> >>>> +
> >>>> +static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr,
> >>>> +           char *buf)
> >>>> +{
> >>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>> +
> >>>> +   return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
> >>>> +}
> >>>> +
> >>>> +static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr,
> >>>> +           const char *buf, size_t count)
> >>>> +{
> >>>> +   int ret = 0;
> >>>> +   unsigned long rate;
> >>>> +   struct usclk_data *pdata = dev_get_drvdata(dev);
> >>>> +
> >>>> +   ret = kstrtoul(buf, 0, &rate);
> >>>> +   if (ret)
> >>>> +           return -EINVAL;
> >>>> +
> >>>> +   rate = clk_round_rate(pdata->clk, rate);
> >>>> +   ret = clk_set_rate(pdata->clk, rate);
> >>>> +   if (ret)
> >>>> +           return -EBUSY;
> >>>> +
> >>>> +   return count;
> >>>> +}
> >>>> +
> >>>> +static DEVICE_ATTR(set_rate, 0644, set_rate_show, set_rate_store);
> >>>> +
> >>>> +static const struct attribute *usclk_attrs[] = {
> >>>> +   &dev_attr_enable.attr,
> >>>> +   &dev_attr_set_rate.attr,
> >>>> +   NULL
> >>>> +};
> >>>
> >>> For debugging purposes, being able to change parents would be nice too.
> >> This is difficult and I don't have a good solution for it, hence it's
> >> missing. A clock consumer like a device driver or this driver, just
> >> knows about it's input clock, but not about the topology further up.
> >> Therefore it is pretty much impossible to implement reparent operations
> >> in a clock consumer, IMHO.
> >> IOW: For a given input clock, how do you figure out it's possible
> >> parents?
> >
> > The parent is just a number
> >
> > int (*set_parent)(struct clk_hw *hw, u8 index);
> > u8 (*get_parent)(struct clk_hw *hw);
> >
> > If you are debugging, you know what the possible parents are, and you
> > can reparent with that information.
> >
> > After checking the clk code however, I didn't find any exposed way to
> > reparent with just the parent indexes. Maybe an interface that takes a n
> > arbitrary string representing the parent name, and gets that clock and
> > then sets the parent would fit.
> >
> >>
> >>> Maybe this belongs to debugfs instead of sysfs though.
> >> Well, the more generic use-case probably. My Zynq use-case rather not,
> >> IMHO.
> >
> > The framework already exposes some information on debugfs, maybe
> > expanding that instead of implementing it as a consumer on sysfs would
> > be best for the debugging use case. @Mike, what's your thoughts on this?
> >
> 
> In the previous thread on this topic we discussed a generic approach
> to exposing clock controls via debugfs.
I have to search for this. I didn't see that discussion.

> 
> One way to do it is to introduce a new config option,
> CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
> every clock in the existing debugfs infrastructure.  The downside to
> this approach is that it would get abused and ship in millions of
> Android products using horrible userspace hacks to control clocks.
> Maybe that's not our problem to solve, maybe it is.
> 
> If CONFIG_COMMON_CLK_DEBUG_CONTROL existed it might be a good idea to
> intentionally break the abi compatibility with every new release.
> That would certainly reinforce that this is not a condoned or stable
> api (which is true for all debugfs).
I kinda like these ideas. The unstable API may be a problem though.
Also, I preferred a solution which limits the exposed controls to a few
selected clocks, instead of exposing them all. My thinking was, that I
have those mentioned FPGA clocks which are likely to be exported, but
everything else should not be exposed.
For debugging though, there is no reason for this limitation.

> 
> I think that Soren wants something with a stable interface that he can
> use for his Zynq use case.  Regarding that, why not write an actual
> device driver to do what you want to do from userspace?
An "actual device driver" would not look that different than this one,
would it?
I could change the probing mechanism a little bit to make it an actual
device - w/o being a physical device though. But I don't think it would
look much different.
So, in the end it would be a platform device which is calling clk_get()
and then exposes enable and set_rate functionality to sysfs. I.e. this
device driver is rather a dummy and could be used by anybody to control
any clock visible in DT, hence my approach to make it a generic driver.
I tried avoiding the 'device driver' solution, because that would mean
adding a device node in DT on the platform bus for something which is
not an actual device - which I ended up to do for this one anyway, but
making it part of debugfs and the core framework might work.

Looks a bit like, that the debugging use case and Zynq have too
different requirements.

	S?ren




From skannan at codeaurora.org  Fri May 10 19:25:45 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 10 May 2013 16:25:45 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <82612ce3-3be2-46fe-925c-3aa6ca743e7d@CO1EHSMHS004.ehs.local>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
 <518D7C45.2090602@codeaurora.org>
 <82612ce3-3be2-46fe-925c-3aa6ca743e7d@CO1EHSMHS004.ehs.local>
Message-ID: <518D81F9.1090105@codeaurora.org>

On 05/10/2013 04:06 PM, S?ren Brinkmann wrote:
> On Fri, May 10, 2013 at 04:01:25PM -0700, Saravana Kannan wrote:
>> On 05/10/2013 03:18 PM, Mike Turquette wrote:

>>> I think that Soren wants something with a stable interface that he can
>>> use for his Zynq use case.  Regarding that, why not write an actual
>>> device driver to do what you want to do from userspace?
>>
>> Exposing clock control to userspace production use is a terrible
>> idea. A misbehaving userspace can easily kill the system. This is
>> not so try for GPIO. So, exposing GPIOs to userspace is relatively
>> less of a concern.
> Well, the FPGA clocks are only used by stuff in the FPGA. They cannot
> mess up the Linux on the A9s. I my use-case is kinda special. And people
> request functionality to easily adjust the frequency for their FPGA
> design in SW from Linux.

How do you talk to the FPGA? What happens if the FPGA clock gets turned 
off when the Linux is communicating with it? At the least the I2C or 
whatever bus you used to talk to it could hang. You need to explain more 
about why it's "special" before people might turn around to give 
userspace ABI for clock control.

> Nevertheless, there is no real protection from taking the driver I'm
> proposing to control the FPGA clocks to control a clock vital to the
> system.

If we are talking about changing the kernel to control different clocks, 
that true for any driver.

If your idea of this driver was something that will take a clock name 
and rate and change that clock's rate, then that's not a good design. 
What Mike probably meant was a FPGA specific driver that will only 
clk_get() the clocks related to the FPGA, and expose options to 
userspace. Not the actual rate or enable/disable capability.

For example, opening the device could cause clk_prepare_enable() and 
closing it would cause clk_disable_unprepare(). You might have ioctls to 
let userspace pick one of different modes of operation with each 
corresponding to a different clock rate and other corresponding FPGA 
configuration changes, etc. That's just a rough sketch. If you write 
such a driver, userspace can't misuse it to mess with other clocks or 
leave the FPGA clock in a bad state.

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From linux at arm.linux.org.uk  Fri May 10 19:29:55 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 00:29:55 +0100
Subject: [RFC 1/8] serial:st-asc: Add ST ASC driver.
In-Reply-To: <20130508163613.GA13761@kroah.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <B5A00B86-5332-427E-A82A-5B71EC0979A8@jcrosoft.com>
 <20130508161527.GA28080@kroah.com> <201305081831.48566.arnd@arndb.de>
 <20130508163613.GA13761@kroah.com>
Message-ID: <20130510232955.GY18614@n2100.arm.linux.org.uk>

On Wed, May 08, 2013 at 09:36:13AM -0700, Greg KH wrote:
> On Wed, May 08, 2013 at 06:31:48PM +0200, Arnd Bergmann wrote:
> > On Wednesday 08 May 2013, Greg KH wrote:
> > > > just mention there is not hardware reason to not use the generic ttySx
> > > > in place of ttyAS as we have only one IP that handle serial on this
> > > > family of SoC
> > > > 
> > > > personally I'll switch to ttySx
> > > 
> > > Great, then you can use the same major/minor range as well, so there's
> > > no more objection from me about this :)
> > 
> > Does that work these days when you have kernel with multiple built-in
> > uart drivers?
> 
> It "should", as the major/minor registration should only happen when the
> hardware is found, but I haven't tested it out, so I can't say for sure.

serial stuff has never operated like that.  More specifically, it's a
limitation with the tty stuff that the way stuff works is that a
tty driver can only drive a single bunch of contiguous minor numbers.
No interleaving is allowed.

That limitation has existed for years, and I don't see it going away.
As long as that limitation exists, you can only ever have one serial
driver driving a set of contiguous minor numbers.

There has been an attempt to "work around" this by making the 8250
driver "special" which was a complete hack to get it to work.  That
was while I maintained this stuff and I outright refused to make one
serial driver magically special.


From soren.brinkmann at xilinx.com  Fri May 10 19:36:55 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 10 May 2013 16:36:55 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <518D81F9.1090105@codeaurora.org>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
 <518D7C45.2090602@codeaurora.org>
 <82612ce3-3be2-46fe-925c-3aa6ca743e7d@CO1EHSMHS004.ehs.local>
 <518D81F9.1090105@codeaurora.org>
Message-ID: <2f341b13-2a7a-44a2-b31e-7ca0afeaa962@AM1EHSMHS008.ehs.local>

On Fri, May 10, 2013 at 04:25:45PM -0700, Saravana Kannan wrote:
> On 05/10/2013 04:06 PM, S?ren Brinkmann wrote:
> >On Fri, May 10, 2013 at 04:01:25PM -0700, Saravana Kannan wrote:
> >>On 05/10/2013 03:18 PM, Mike Turquette wrote:
> 
> >>>I think that Soren wants something with a stable interface that he can
> >>>use for his Zynq use case.  Regarding that, why not write an actual
> >>>device driver to do what you want to do from userspace?
> >>
> >>Exposing clock control to userspace production use is a terrible
> >>idea. A misbehaving userspace can easily kill the system. This is
> >>not so try for GPIO. So, exposing GPIOs to userspace is relatively
> >>less of a concern.
> >Well, the FPGA clocks are only used by stuff in the FPGA. They cannot
> >mess up the Linux on the A9s. I my use-case is kinda special. And people
> >request functionality to easily adjust the frequency for their FPGA
> >design in SW from Linux.
> 
> How do you talk to the FPGA? What happens if the FPGA clock gets
> turned off when the Linux is communicating with it? At the least the
> I2C or whatever bus you used to talk to it could hang. You need to
> explain more about why it's "special" before people might turn
> around to give userspace ABI for clock control.
> 
> >Nevertheless, there is no real protection from taking the driver I'm
> >proposing to control the FPGA clocks to control a clock vital to the
> >system.
> 
> If we are talking about changing the kernel to control different
> clocks, that true for any driver.
> 
> If your idea of this driver was something that will take a clock
> name and rate and change that clock's rate, then that's not a good
> design. What Mike probably meant was a FPGA specific driver that
> will only clk_get() the clocks related to the FPGA, and expose
> options to userspace. Not the actual rate or enable/disable
> capability.
How? You do this through device tree. If you give that driver a
different clock than the one it should get it might mess up. But this
does apply to all device drivers. Assume you give you ethernet driver
the wrong clock reference. When it tries to adjust the link speed it
will mess up the clock. There is no protection against this.

> For example, opening the device could cause clk_prepare_enable() and
> closing it would cause clk_disable_unprepare().
In the current state: Enable/disable is explicitly done through the 'enable'
file in sysfs.  The driver takes care of that all enable/disable is
balanced. I.e. prepare_enable is called if non-zero is written to enable
and the driver didn't enable the clock yet and similar for disable.

> You might have
> ioctls to let userspace pick one of different modes of operation
> with each corresponding to a different clock rate and other
> corresponding FPGA configuration changes, etc.
It's an FPGA and therefore fully programmable even during runtime.

> That's just a rough
> sketch. If you write such a driver, userspace can't misuse it to
> mess with other clocks or leave the FPGA clock in a bad state.
Currently, you cannot mess with the enable counts and whether the
frequency is sane or not is up to the user. Unless you have a known
design and appropriate DT bindings there is no way of knowing this
upfront, which is kinda the point of having the driver.
The first use case in my mind is just some simple bring up. Having the
clocks let some LEDs blink and now let them blink faster/slower by
changing the frequency.

	S?ren




From cdall at cs.columbia.edu  Fri May 10 20:36:30 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Fri, 10 May 2013 17:36:30 -0700
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <20130507163303.GH29757@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
 <20130502160906.GI20730@arm.com> <51892B90.8060706@arm.com>
 <20130507163303.GH29757@arm.com>
Message-ID: <20130511003630.GD30999@chazy>

On Tue, May 07, 2013 at 05:33:03PM +0100, Catalin Marinas wrote:
> On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote:
> > On 02/05/13 17:09, Catalin Marinas wrote:
> > > BTW, on arch/arm it looks like this is used when you get a data abort
> > > with PC as the destination register and you inject a prefetch abort in
> > > this case. Why isn't this a normal data abort? Once you get the
> > > information, you load it into PC but first you need to sort out the data
> > > abort (unless I don't understand how the kvm_inject_pabt works).
> > 
> > Indeed, it should be a data abort, as we correctly fetched the
> > instruction. Now, I wonder why we even bother trying to catch this case.
> > Fetching PC from MMIO looks quite silly, but I don't think anything
> > really forbids it in the architecture.
> 
> It's not forbidden and you should just treat it as any other data abort,
> no need to check whether the register is PC. If you do the PC adjustment
> further down in that function it will be overridden by the instruction
> emulation anyway. There is no optimisation in checking for PC since such
> fault is very unlikely in sane code anyway.
> 
The reason is simply that it is most likely because of a bug that this
happens, and we would rather catch such an error in a meaningful way
than let this go crazy and have users track it down for a long time.

Especially, this was relevant when we did io instruction decoding and we
wanted to catch potential bugs in that when it was development code.

That all being said, we can remove the check.  I don't think, however,
that it being an unlikely thing is a good argument: if we remove the
check we need to make sure that the VM does whatever the architecture
dictates, which I assume is to not skip the MMIO instruction and support
setting the PC to the value returned from an I/O emulation device in
QEMU.

I think the scenario sounds crazy and is more than anything a sign of a
bug somewhere, and whether it should be a PABT or a DABT is a judgement
call, but I chose a PABT because the thing that's weird is jumping to an
I/O address, it's not that the memory address for the load is
problematic.

-Christoffer


From cdall at cs.columbia.edu  Fri May 10 20:38:42 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Fri, 10 May 2013 17:38:42 -0700
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <51892DA4.4050401@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com> <5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
 <51892DA4.4050401@arm.com>
Message-ID: <20130511003842.GE30999@chazy>

On Tue, May 07, 2013 at 05:36:52PM +0100, Marc Zyngier wrote:
> On 24/04/13 18:17, Christoffer Dall wrote:
> > On Wed, Apr 24, 2013 at 6:49 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> >> On 24/04/13 00:02, Christoffer Dall wrote:
> >>> On Mon, Apr 08, 2013 at 05:17:32PM +0100, Marc Zyngier wrote:
> >>>> Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
> >>>> and providing sensible defaults out of reset state.
> >>>>
> >>>> This feature is of course conditioned by the presence of 32bit
> >>>> capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
> >>>> capability.
> >>>>
> >>>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> >>>> ---
> >>>>  arch/arm64/include/asm/kvm_host.h |  2 +-
> >>>>  arch/arm64/include/uapi/asm/kvm.h |  1 +
> >>>>  arch/arm64/kvm/guest.c            |  6 ++++++
> >>>>  arch/arm64/kvm/reset.c            | 25 ++++++++++++++++++++++++-
> >>>>  include/uapi/linux/kvm.h          |  1 +
> >>>>  5 files changed, 33 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> >>>> index d44064d..c3ec107 100644
> >>>> --- a/arch/arm64/include/asm/kvm_host.h
> >>>> +++ b/arch/arm64/include/asm/kvm_host.h
> >>>> @@ -34,7 +34,7 @@
> >>>>  #include <asm/kvm_vgic.h>
> >>>>  #include <asm/kvm_arch_timer.h>
> >>>>
> >>>> -#define KVM_VCPU_MAX_FEATURES 1
> >>>> +#define KVM_VCPU_MAX_FEATURES 2
> >>>>
> >>>>  /* We don't currently support large pages. */
> >>>>  #define KVM_HPAGE_GFN_SHIFT(x)      0
> >>>> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> >>>> index 5b1110c..5031f42 100644
> >>>> --- a/arch/arm64/include/uapi/asm/kvm.h
> >>>> +++ b/arch/arm64/include/uapi/asm/kvm.h
> >>>> @@ -75,6 +75,7 @@ struct kvm_regs {
> >>>>  #define KVM_VGIC_V2_CPU_SIZE                0x2000
> >>>>
> >>>>  #define KVM_ARM_VCPU_POWER_OFF              0 /* CPU is started in OFF state */
> >>>> +#define KVM_ARM_VCPU_EL1_32BIT              1 /* CPU running a 32bit VM */
> >>>>
> >>>>  struct kvm_vcpu_init {
> >>>>      __u32 target;
> >>>> diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
> >>>> index 47d3729..74ef7d5 100644
> >>>> --- a/arch/arm64/kvm/guest.c
> >>>> +++ b/arch/arm64/kvm/guest.c
> >>>> @@ -93,6 +93,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
> >>>>      if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
> >>>>              unsigned long mode = (*(unsigned long *)valp) & COMPAT_PSR_MODE_MASK;
> >>>>              switch (mode) {
> >>>> +            case COMPAT_PSR_MODE_USR:
> >>>> +            case COMPAT_PSR_MODE_FIQ:
> >>>> +            case COMPAT_PSR_MODE_IRQ:
> >>>> +            case COMPAT_PSR_MODE_SVC:
> >>>> +            case COMPAT_PSR_MODE_ABT:
> >>>> +            case COMPAT_PSR_MODE_UND:
> >>>>              case PSR_MODE_EL0t:
> >>>>              case PSR_MODE_EL1t:
> >>>>              case PSR_MODE_EL1h:
> >>>> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
> >>>> index bc33e76..a282d35 100644
> >>>> --- a/arch/arm64/kvm/reset.c
> >>>> +++ b/arch/arm64/kvm/reset.c
> >>>> @@ -35,11 +35,27 @@ static struct kvm_regs default_regs_reset = {
> >>>>      .regs.pstate = PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
> >>>>  };
> >>>>
> >>>> +static struct kvm_regs default_regs_reset32 = {
> >>>> +    .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
> >>>> +                    COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
> >>>> +};
> >>>> +
> >>>> +static bool cpu_has_32bit_el1(void)
> >>>> +{
> >>>> +    u64 pfr0;
> >>>> +
> >>>> +    pfr0 = read_cpuid(ID_AA64PFR0_EL1);
> >>>> +    return !!(pfr0 & 0x20);
> >>>
> >>> again we don't need the double negation
> >>
> >> I still hold that it makes things more readable.
> >>
> >>>> +}
> >>>> +
> >>>>  int kvm_arch_dev_ioctl_check_extention(long ext)
> >>>>  {
> >>>>      int r;
> >>>>
> >>>>      switch (ext) {
> >>>> +    case KVM_CAP_ARM_EL1_32BIT:
> >>>> +            r = cpu_has_32bit_el1();
> >>>> +            break;
> >>>>      default:
> >>>>              r = 0;
> >>>>      }
> >>>> @@ -62,7 +78,14 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
> >>>>
> >>>>      switch (vcpu->arch.target) {
> >>>>      default:
> >>>> -            cpu_reset = &default_regs_reset;
> >>>> +            if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
> >>>> +                    if (!cpu_has_32bit_el1())
> >>>> +                            return -EINVAL;
> >>>
> >>> I'm not sure EINVAL is appropriate here, the value specified was not
> >>> incorrect, it's that the hardware doesn't support it. ENXIO, ENODEV, and
> >>> add that in Documentation/virtual/kvm/api.txt ?
> >>
> >> Not sure. If you ended up here, it means you tried to start a 32bit
> >> guest on a 64bit-only CPU, despite KVM_CAP_ARM_EL1_32BIT telling you
> >> that your CPU is not 32bit capable.
> >>
> >> This is clearly an invalid input, isn't it?
> >>
> > check the API documentation for this ioctl, I don't think that's the
> > type of invalid input meant when describing the meaning of EINVAL. If
> > you feel strongly about it of course it's no big deal, but I think
> > EINVAL is so overloaded anyway that telling the user something more
> > specific would be great, but I'll leave it up to you.
> 
> [bit late on this one...]
> 
> Here's what the documentation says:
> <quote>
> 4.77 KVM_ARM_VCPU_INIT
> 
> Capability: basic
> Architectures: arm, arm64
> Type: vcpu ioctl
> Parameters: struct struct kvm_vcpu_init (in)
> Returns: 0 on success; -1 on error
> Errors:
>   EINVAL:    the target is unknown, or the combination of features is invalid.
>   ENOENT:    a features bit specified is unknown.
> </quote>
> 
> When this call fails, it is because you've requested a feature
> that is invalid for this CPU. To me, that exactly fits the
> EINVAL entry copied above.
> 
> Or am I completely misunderstanding it?
> 
I read the EINVAL to say that you supplied something which is invalid
for the software interface and you should fix your user space code.

The fact that you're requesting a feature that your hardware doesn't
support is a different thing IMHO.

-Christoffer


From ebrower at nvidia.com  Fri May 10 20:40:29 2013
From: ebrower at nvidia.com (Eric Brower)
Date: Fri, 10 May 2013 17:40:29 -0700
Subject: [PATCH 1/1] ARM: DT: tegra: Add gpio-leds to Tegra30 Beaver
Message-ID: <1368232829-25716-1-git-send-email-ebrower@nvidia.com>

Add support for general-purpose LEDs present on Beaver

Signed-off-by: Eric Brower <ebrower at nvidia.com>
---
 arch/arm/boot/dts/tegra30-beaver.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 6248b24..d44cd81 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -383,4 +383,17 @@
 			vin-supply = <&sys_3v3_reg>;
 		};
 	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		gpled1 {
+			label = "LED1"; /* CR5A1 (blue) */
+			gpios = <&gpio 89 0>; /* gpio PL1 */
+		};
+		gpled2 {
+			label = "LED2"; /* CR4A2 (green) */
+			gpios = <&gpio 88 0>; /* gpio PL0 */
+		};
+	};
 };
-- 
1.8.1.5
nvpublic


From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:09 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:09 +0200
Subject: [PATCH 09/10] ARM: mvebu: move DT boards to SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-10-git-send-email-sebastian.hesselbarth@gmail.com>

SoC centric clock init for Armada 370/XP can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-mvebu/Kconfig         |    5 ++---
 arch/arm/mach-mvebu/armada-370-xp.c |    4 ++--
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb..6512837 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,9 +10,6 @@ config ARCH_MVEBU
 	select PLAT_ORION
 	select SPARSE_IRQ
 	select CLKDEV_LOOKUP
-	select MVEBU_CLK_CORE
-	select MVEBU_CLK_CPU
-	select MVEBU_CLK_GATING
 	select MVEBU_MBUS
 	select ZONE_DMA if ARM_LPAE
 
@@ -29,6 +26,7 @@ config MACH_ARMADA_370_XP
 
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boards"
+	select ARMADA_370_CLK
 	select MACH_ARMADA_370_XP
 	select PINCTRL_ARMADA_370
 	help
@@ -37,6 +35,7 @@ config MACH_ARMADA_370
 
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards"
+	select ARMADA_XP_CLK
 	select MACH_ARMADA_370_XP
 	select PINCTRL_ARMADA_XP
 	help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3..1d018e4 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,10 +14,10 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk-provider.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
 #include <linux/irqchip.h>
@@ -45,7 +45,7 @@ void __init armada_370_xp_map_io(void)
 
 void __init armada_370_xp_timer_and_clk_init(void)
 {
-	mvebu_clocks_init();
+	of_clk_init(NULL);
 	armada_370_xp_timer_init();
 }
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:03 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:03 +0200
Subject: [PATCH 03/10] clk: mvebu: add Dove SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-4-git-send-email-sebastian.hesselbarth@gmail.com>

This is moving core clock and clock gating init for Dove to its own
file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/Kconfig  |    4 +
 drivers/clk/mvebu/Makefile |    2 +
 drivers/clk/mvebu/dove.c   |  194 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 200 insertions(+)
 create mode 100644 drivers/clk/mvebu/dove.c

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 2c3cf95..bc5f05e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -9,3 +9,7 @@ config MVEBU_CLK_GATING
 
 config MVEBU_CLK_COMMON
 	bool
+
+config DOVE_CLK
+	bool
+	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 2143230..bfc3078 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,3 +2,5 @@ obj-$(CONFIG_MVEBU_CLK_COMMON)	+= common.o
 obj-$(CONFIG_MVEBU_CLK_CORE) 	+= clk.o clk-core.o
 obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
+
+obj-$(CONFIG_DOVE_CLK)		+= dove.o
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
new file mode 100644
index 0000000..79d7aed
--- /dev/null
+++ b/drivers/clk/mvebu/dove.c
@@ -0,0 +1,194 @@
+/*
+ * Marvell Dove SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Dove PLL sample-at-reset configuration
+ *
+ * SAR0[8:5]   : CPU frequency
+ *		 5  = 1000 MHz
+ *		 6  =  933 MHz
+ *		 7  =  933 MHz
+ *		 8  =  800 MHz
+ *		 9  =  800 MHz
+ *		 10 =  800 MHz
+ *		 11 = 1067 MHz
+ *		 12 =  667 MHz
+ *		 13 =  533 MHz
+ *		 14 =  400 MHz
+ *		 15 =  333 MHz
+ *		 others reserved.
+ *
+ * SAR0[11:9]  : CPU to L2 Clock divider ratio
+ *		 0 = (1/1) * CPU
+ *		 2 = (1/2) * CPU
+ *		 4 = (1/3) * CPU
+ *		 6 = (1/4) * CPU
+ *		 others reserved.
+ *
+ * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
+ *		 0  = (1/1) * CPU
+ *		 2  = (1/2) * CPU
+ *		 3  = (2/5) * CPU
+ *		 4  = (1/3) * CPU
+ *		 6  = (1/4) * CPU
+ *		 8  = (1/5) * CPU
+ *		 10 = (1/6) * CPU
+ *		 12 = (1/7) * CPU
+ *		 14 = (1/8) * CPU
+ *		 15 = (1/10) * CPU
+ *		 others reserved.
+ *
+ * SAR0[24:23] : TCLK frequency
+ *		 0 = 166 MHz
+ *		 1 = 125 MHz
+ *		 others reserved.
+ */
+
+#define SAR_DOVE_CPU_FREQ		5
+#define SAR_DOVE_CPU_FREQ_MASK		0xf
+#define SAR_DOVE_L2_RATIO		9
+#define SAR_DOVE_L2_RATIO_MASK		0x7
+#define SAR_DOVE_DDR_RATIO		12
+#define SAR_DOVE_DDR_RATIO_MASK		0xf
+#define SAR_DOVE_TCLK_FREQ		23
+#define SAR_DOVE_TCLK_FREQ_MASK		0x3
+
+enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = {
+	{ .id = DOVE_CPU_TO_L2, .name = "l2clk", },
+	{ .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static const u32 __initconst dove_tclk_freqs[] = {
+	166666667,
+	125000000,
+	0, 0
+};
+
+static u32 __init dove_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
+		SAR_DOVE_TCLK_FREQ_MASK;
+	return dove_tclk_freqs[opt];
+}
+
+static const u32 __initconst dove_cpu_freqs[] = {
+	0, 0, 0, 0, 0,
+	1000000000,
+	933333333, 933333333,
+	800000000, 800000000, 800000000,
+	1066666667,
+	666666667,
+	533333333,
+	400000000,
+	333333333
+};
+
+static u32 __init dove_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
+		SAR_DOVE_CPU_FREQ_MASK;
+	return dove_cpu_freqs[opt];
+}
+
+static const int __initconst dove_cpu_l2_ratios[8][2] = {
+	{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+	{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
+};
+
+static const int __initconst dove_cpu_ddr_ratios[16][2] = {
+	{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
+	{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
+	{ 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
+	{ 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
+};
+
+static void __init dove_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	switch (id) {
+	case DOVE_CPU_TO_L2:
+	{
+		u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
+			SAR_DOVE_L2_RATIO_MASK;
+		*mult = dove_cpu_l2_ratios[opt][0];
+		*div = dove_cpu_l2_ratios[opt][1];
+		break;
+	}
+	case DOVE_CPU_TO_DDR:
+	{
+		u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
+			SAR_DOVE_DDR_RATIO_MASK;
+		*mult = dove_cpu_ddr_ratios[opt][0];
+		*div = dove_cpu_ddr_ratios[opt][1];
+		break;
+	}
+	}
+}
+
+static const struct coreclk_soc_desc dove_coreclks = {
+	.get_tclk_freq = dove_get_tclk_freq,
+	.get_cpu_freq = dove_get_cpu_freq,
+	.get_clk_ratio = dove_get_clk_ratio,
+	.ratios = dove_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
+};
+
+static void __init dove_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &dove_coreclks);
+}
+CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = {
+	{ "usb0", NULL, 0, 0 },
+	{ "usb1", NULL, 1, 0 },
+	{ "ge",	"gephy", 2, 0 },
+	{ "sata", NULL, 3, 0 },
+	{ "pex0", NULL, 4, 0 },
+	{ "pex1", NULL, 5, 0 },
+	{ "sdio0", NULL, 8, 0 },
+	{ "sdio1", NULL, 9, 0 },
+	{ "nand", NULL, 10, 0 },
+	{ "camera", NULL, 11, 0 },
+	{ "i2s0", NULL, 12, 0 },
+	{ "i2s1", NULL, 13, 0 },
+	{ "crypto", NULL, 15, 0 },
+	{ "ac97", NULL, 21, 0 },
+	{ "pdma", NULL, 22, 0 },
+	{ "xor0", NULL, 23, 0 },
+	{ "xor1", NULL, 24, 0 },
+	{ "gephy", NULL, 30, 0 },
+	{ }
+};
+
+static void __init dove_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, dove_gating_desc);
+}
+CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
+	       dove_clk_gating_init);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:00 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:00 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
Message-ID: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>

Marvell EBU SoCs share some common clock functions that register core
clocks or clock gates from SoC specific data. These clock drivers are
organized by function and over time the drivers filled up with #ifdefs
to separate different SoC specific code.

This patch set first adds a new element to clock gate descriptors to
allow to pass clk flags per clock gate. (Patch 1)

Then it restructures MVEBU clock drivers into common clock setup and
SoC specific files and Kconfig options. The driver's init functions
are also registered to get called with of_clk_init. (Patches 2, 3-6)

It then switches Dove, Kirkwood, and Armada 370/XP to make use of
of_clk_init instead of mvebu_clocks_init. (Patches 7-9)

Finally, all obsolete files and Kconfig options are removed. (Patch 10)

It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
Armada 370 and XP are compile tested only and should get their Tested-by
from Thomas and Gregory, respectively.

@Mike: As this only touches MVEBU related code, I suggest to take it
all through the corresponding ARM branch.

Sebastian Hesselbarth (10):
  clk: mvebu: introduce per-clock-gate flags
  clk: mvebu: add common clock functions for core clk and clk gating
  clk: mvebu: add Dove SoC-centric clock init
  clk: mvebu: add Kirkwood SoC-centric clock init
  clk: mvebu: add Armada 370 SoC-centric clock init
  clk: mvebu: add Armada XP SoC-centric clock init
  ARM: dove: move DT boards to SoC-centric clock init
  ARM: kirkwood: move DT boards to SoC-centric clock init
  ARM: mvebu: move DT boards to SoC-centric clock init
  clk: mvebu: desintegrate obsolete file

 arch/arm/mach-dove/Kconfig          |    3 +-
 arch/arm/mach-dove/board-dt.c       |    3 +-
 arch/arm/mach-dove/common.c         |    1 -
 arch/arm/mach-kirkwood/Kconfig      |    3 +-
 arch/arm/mach-kirkwood/board-dt.c   |    3 +-
 arch/arm/mach-mvebu/Kconfig         |    5 +-
 arch/arm/mach-mvebu/armada-370-xp.c |    4 +-
 drivers/clk/mvebu/Kconfig           |   25 +-
 drivers/clk/mvebu/Makefile          |    8 +-
 drivers/clk/mvebu/armada-370.c      |  176 +++++++++
 drivers/clk/mvebu/armada-xp.c       |  204 +++++++++++
 drivers/clk/mvebu/clk-core.c        |  675 -----------------------------------
 drivers/clk/mvebu/clk-core.h        |   18 -
 drivers/clk/mvebu/clk-gating-ctrl.c |  250 -------------
 drivers/clk/mvebu/clk-gating-ctrl.h |   22 --
 drivers/clk/mvebu/clk.c             |   23 --
 drivers/clk/mvebu/common.c          |  163 +++++++++
 drivers/clk/mvebu/common.h          |   48 +++
 drivers/clk/mvebu/dove.c            |  194 ++++++++++
 drivers/clk/mvebu/kirkwood.c        |  247 +++++++++++++
 include/linux/clk/mvebu.h           |   22 --
 21 files changed, 1066 insertions(+), 1031 deletions(-)
 create mode 100644 drivers/clk/mvebu/armada-370.c
 create mode 100644 drivers/clk/mvebu/armada-xp.c
 delete mode 100644 drivers/clk/mvebu/clk-core.c
 delete mode 100644 drivers/clk/mvebu/clk-core.h
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
 delete mode 100644 drivers/clk/mvebu/clk.c
 create mode 100644 drivers/clk/mvebu/common.c
 create mode 100644 drivers/clk/mvebu/common.h
 create mode 100644 drivers/clk/mvebu/dove.c
 create mode 100644 drivers/clk/mvebu/kirkwood.c
 delete mode 100644 include/linux/clk/mvebu.h
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:08 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:08 +0200
Subject: [PATCH 08/10] ARM: kirkwood: move DT boards to SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-9-git-send-email-sebastian.hesselbarth@gmail.com>

SoC centric clock init for Kirkwood can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/Kconfig    |    3 +--
 arch/arm/mach-kirkwood/board-dt.c |    3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..79ee9f2 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -134,13 +134,12 @@ comment "Device tree entries"
 
 config ARCH_KIRKWOOD_DT
 	bool "Marvell Kirkwood Flattened Device Tree"
+	select KIRKWOOD_CLK
 	select POWER_SUPPLY
 	select POWER_RESET
 	select POWER_RESET_GPIO
 	select REGULATOR
 	select REGULATOR_FIXED_VOLTAGE
-	select MVEBU_CLK_CORE
-	select MVEBU_CLK_GATING
 	select USE_OF
 	help
 	  Say 'Y' here if you want your kernel to support the
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..2f695e5 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,7 +15,6 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -77,7 +76,7 @@ static void __init kirkwood_legacy_clk_init(void)
 
 static void __init kirkwood_of_clk_init(void)
 {
-	mvebu_clocks_init();
+	of_clk_init(NULL);
 	kirkwood_legacy_clk_init();
 }
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:04 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:04 +0200
Subject: [PATCH 04/10] clk: mvebu: add Kirkwood SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-5-git-send-email-sebastian.hesselbarth@gmail.com>

This is moving core clock and clock gating init for Kirkwood to its
own file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/Kconfig    |    4 +
 drivers/clk/mvebu/Makefile   |    1 +
 drivers/clk/mvebu/kirkwood.c |  247 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 252 insertions(+)
 create mode 100644 drivers/clk/mvebu/kirkwood.c

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index bc5f05e..211695c 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -13,3 +13,7 @@ config MVEBU_CLK_COMMON
 config DOVE_CLK
 	bool
 	select MVEBU_CLK_COMMON
+
+config KIRKWOOD_CLK
+	bool
+	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index bfc3078..97d1ab0 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
 
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
+obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
new file mode 100644
index 0000000..71d2461
--- /dev/null
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -0,0 +1,247 @@
+/*
+ * Marvell Kirkwood SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Kirkwood PLL sample-at-reset configuration
+ * (6180 has different SAR layout than other Kirkwood SoCs)
+ *
+ * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
+ *	4  =  600 MHz
+ *	6  =  800 MHz
+ *	7  = 1000 MHz
+ *	9  = 1200 MHz
+ *	12 = 1500 MHz
+ *	13 = 1600 MHz
+ *	14 = 1800 MHz
+ *	15 = 2000 MHz
+ *	others reserved.
+ *
+ * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
+ *	1 = (1/2) * CPU
+ *	3 = (1/3) * CPU
+ *	5 = (1/4) * CPU
+ *	others reserved.
+ *
+ * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
+ *	2 = (1/2) * CPU
+ *	4 = (1/3) * CPU
+ *	6 = (1/4) * CPU
+ *	7 = (2/9) * CPU
+ *	8 = (1/5) * CPU
+ *	9 = (1/6) * CPU
+ *	others reserved.
+ *
+ * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
+ *	5 = [CPU =  600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
+ *	6 = [CPU =  800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
+ *	7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
+ *	others reserved.
+ *
+ * SAR0[21] : TCLK frequency
+ *	0 = 200 MHz
+ *	1 = 166 MHz
+ *	others reserved.
+ */
+
+#define SAR_KIRKWOOD_CPU_FREQ(x)	\
+	(((x & (1 <<  1)) >>  1) |	\
+	 ((x & (1 << 22)) >> 21) |	\
+	 ((x & (3 <<  3)) >>  1))
+#define SAR_KIRKWOOD_L2_RATIO(x)	\
+	(((x & (3 <<  9)) >> 9) |	\
+	 (((x & (1 << 19)) >> 17)))
+#define SAR_KIRKWOOD_DDR_RATIO		5
+#define SAR_KIRKWOOD_DDR_RATIO_MASK	0xf
+#define SAR_MV88F6180_CLK		2
+#define SAR_MV88F6180_CLK_MASK		0x7
+#define SAR_KIRKWOOD_TCLK_FREQ		21
+#define SAR_KIRKWOOD_TCLK_FREQ_MASK	0x1
+
+enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
+	{ .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
+	{ .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
+		SAR_KIRKWOOD_TCLK_FREQ_MASK;
+	return (opt) ? 166666667 : 200000000;
+}
+
+static const u32 __initconst kirkwood_cpu_freqs[] = {
+	0, 0, 0, 0,
+	600000000,
+	0,
+	800000000,
+	1000000000,
+	0,
+	1200000000,
+	0, 0,
+	1500000000,
+	1600000000,
+	1800000000,
+	2000000000
+};
+
+static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
+	return kirkwood_cpu_freqs[opt];
+}
+
+static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
+	{ 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
+	{ 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
+};
+
+static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
+	{ 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+	{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
+	{ 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
+	{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+};
+
+static void __init kirkwood_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	switch (id) {
+	case KIRKWOOD_CPU_TO_L2:
+	{
+		u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
+		*mult = kirkwood_cpu_l2_ratios[opt][0];
+		*div = kirkwood_cpu_l2_ratios[opt][1];
+		break;
+	}
+	case KIRKWOOD_CPU_TO_DDR:
+	{
+		u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
+			SAR_KIRKWOOD_DDR_RATIO_MASK;
+		*mult = kirkwood_cpu_ddr_ratios[opt][0];
+		*div = kirkwood_cpu_ddr_ratios[opt][1];
+		break;
+	}
+	}
+}
+
+static const u32 __initconst mv88f6180_cpu_freqs[] = {
+	0, 0, 0, 0, 0,
+	600000000,
+	800000000,
+	1000000000
+};
+
+static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
+	return mv88f6180_cpu_freqs[opt];
+}
+
+static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
+	{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+	{ 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
+};
+
+static void __init mv88f6180_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	switch (id) {
+	case KIRKWOOD_CPU_TO_L2:
+	{
+		/* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
+		*mult = 1;
+		*div = 2;
+		break;
+	}
+	case KIRKWOOD_CPU_TO_DDR:
+	{
+		u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
+			SAR_MV88F6180_CLK_MASK;
+		*mult = mv88f6180_cpu_ddr_ratios[opt][0];
+		*div = mv88f6180_cpu_ddr_ratios[opt][1];
+		break;
+	}
+	}
+}
+
+static const struct coreclk_soc_desc kirkwood_coreclks = {
+	.get_tclk_freq = kirkwood_get_tclk_freq,
+	.get_cpu_freq = kirkwood_get_cpu_freq,
+	.get_clk_ratio = kirkwood_get_clk_ratio,
+	.ratios = kirkwood_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init kirkwood_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &kirkwood_coreclks);
+}
+CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
+	       kirkwood_coreclk_init);
+
+static const struct coreclk_soc_desc mv88f6180_coreclks = {
+	.get_tclk_freq = kirkwood_get_tclk_freq,
+	.get_cpu_freq = mv88f6180_get_cpu_freq,
+	.get_clk_ratio = mv88f6180_get_clk_ratio,
+	.ratios = kirkwood_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init mv88f6180_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &mv88f6180_coreclks);
+}
+CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
+	       mv88f6180_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
+	{ "ge0", NULL, 0, 0 },
+	{ "pex0", NULL, 2, 0 },
+	{ "usb0", NULL, 3, 0 },
+	{ "sdio", NULL, 4, 0 },
+	{ "tsu", NULL, 5, 0 },
+	{ "runit", NULL, 7, 0 },
+	{ "xor0", NULL, 8, 0 },
+	{ "audio", NULL, 9, 0 },
+	{ "powersave", "cpuclk", 11, 0 },
+	{ "sata0", NULL, 14, 0 },
+	{ "sata1", NULL, 15, 0 },
+	{ "xor1", NULL, 16, 0 },
+	{ "crypto", NULL, 17, 0 },
+	{ "pex1", NULL, 18, 0 },
+	{ "ge1", NULL, 19, 0 },
+	{ "tdm", NULL, 20, 0 },
+	{ }
+};
+
+static void __init kirkwood_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, kirkwood_gating_desc);
+}
+CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
+	       kirkwood_clk_gating_init);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:07 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:07 +0200
Subject: [PATCH 07/10] ARM: dove: move DT boards to SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-8-git-send-email-sebastian.hesselbarth@gmail.com>

SoC centric clock init for Dove can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/Kconfig    |    3 +--
 arch/arm/mach-dove/board-dt.c |    3 +--
 arch/arm/mach-dove/common.c   |    1 -
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d8..dff7b2f 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,8 +22,7 @@ config MACH_CM_A510
 
 config MACH_DOVE_DT
 	bool "Marvell Dove Flattened Device Tree"
-	select MVEBU_CLK_CORE
-	select MVEBU_CLK_GATING
+	select DOVE_CLK
 	select REGULATOR
 	select REGULATOR_FIXED_VOLTAGE
 	select USE_OF
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b14280..f3755ac 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,7 +10,6 @@
 
 #include <linux/init.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void)
 
 static void __init dove_of_clk_init(void)
 {
-	mvebu_clocks_init();
+	of_clk_init(NULL);
 	dove_legacy_clk_init();
 }
 
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..2a9443d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of.h>
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:02 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:02 +0200
Subject: [PATCH 02/10] clk: mvebu: add common clock functions for core clk and
 clk gating
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-3-git-send-email-sebastian.hesselbarth@gmail.com>

Based on the current common functions for core clocks and clock
gating control, new common functions are joined in a single file.
Given the opportunity, names of functions and structs are unified,
and also a Kconfig entry is added.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/Kconfig  |    3 +
 drivers/clk/mvebu/Makefile |    1 +
 drivers/clk/mvebu/common.c |  163 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mvebu/common.h |   48 +++++++++++++
 4 files changed, 215 insertions(+)
 create mode 100644 drivers/clk/mvebu/common.c
 create mode 100644 drivers/clk/mvebu/common.h

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 57323fd..2c3cf95 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -6,3 +6,6 @@ config MVEBU_CLK_CPU
 
 config MVEBU_CLK_GATING
        bool
+
+config MVEBU_CLK_COMMON
+	bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 58df3dc..2143230 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_MVEBU_CLK_COMMON)	+= common.o
 obj-$(CONFIG_MVEBU_CLK_CORE) 	+= clk.o clk-core.o
 obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
new file mode 100644
index 0000000..adaa4a1
--- /dev/null
+++ b/drivers/clk/mvebu/common.c
@@ -0,0 +1,163 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+static struct clk_onecell_data clk_data;
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+				const struct coreclk_soc_desc *desc)
+{
+	const char *tclk_name = "tclk";
+	const char *cpuclk_name = "cpuclk";
+	void __iomem *base;
+	unsigned long rate;
+	int n;
+
+	base = of_iomap(np, 0);
+	if (WARN_ON(!base))
+		return;
+
+	/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
+	clk_data.clk_num = 2 + desc->num_ratios;
+	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
+				GFP_KERNEL);
+	if (WARN_ON(!clk_data.clks))
+		return;
+
+	/* Register TCLK */
+	of_property_read_string_index(np, "clock-output-names", 0,
+				      &tclk_name);
+	rate = desc->get_tclk_freq(base);
+	clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
+						   CLK_IS_ROOT, rate);
+	WARN_ON(IS_ERR(clk_data.clks[0]));
+
+	/* Register CPU clock */
+	of_property_read_string_index(np, "clock-output-names", 1,
+				      &cpuclk_name);
+	rate = desc->get_cpu_freq(base);
+	clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
+						   CLK_IS_ROOT, rate);
+	WARN_ON(IS_ERR(clk_data.clks[1]));
+
+	/* Register fixed-factor clocks derived from CPU clock */
+	for (n = 0; n < desc->num_ratios; n++) {
+		const char *rclk_name = desc->ratios[n].name;
+		int mult, div;
+
+		of_property_read_string_index(np, "clock-output-names",
+					      2+n, &rclk_name);
+		desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
+		clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
+				       cpuclk_name, 0, mult, div);
+		WARN_ON(IS_ERR(clk_data.clks[2+n]));
+	};
+
+	/* SAR register isn't needed anymore */
+	iounmap(base);
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * Clock Gating Control
+ */
+
+struct clk_gating_ctrl {
+	spinlock_t lock;
+	struct clk **gates;
+	int num_gates;
+};
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static struct clk *clk_gating_get_src(
+	struct of_phandle_args *clkspec, void *data)
+{
+	struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
+	int n;
+
+	if (clkspec->args_count < 1)
+		return ERR_PTR(-EINVAL);
+
+	for (n = 0; n < ctrl->num_gates; n++) {
+		struct clk_gate *gate =
+			to_clk_gate(__clk_get_hw(ctrl->gates[n]));
+		if (clkspec->args[0] == gate->bit_idx)
+			return ctrl->gates[n];
+	}
+	return ERR_PTR(-ENODEV);
+}
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+				   const struct clk_gating_soc_desc *desc)
+{
+	struct clk_gating_ctrl *ctrl;
+	struct clk *clk;
+	void __iomem *base;
+	const char *default_parent = NULL;
+	int n;
+
+	base = of_iomap(np, 0);
+	if (WARN_ON(!base))
+		return;
+
+	clk = of_clk_get(np, 0);
+	if (!IS_ERR(clk)) {
+		default_parent = __clk_get_name(clk);
+		clk_put(clk);
+	}
+
+	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+	if (WARN_ON(!ctrl))
+		return;
+
+	spin_lock_init(&ctrl->lock);
+
+	/* Count, allocate, and register clock gates */
+	for (n = 0; desc[n].name;)
+		n++;
+
+	ctrl->num_gates = n;
+	ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
+			      GFP_KERNEL);
+	if (WARN_ON(!ctrl->gates)) {
+		kfree(ctrl);
+		return;
+	}
+
+	for (n = 0; n < ctrl->num_gates; n++) {
+		const char *parent =
+			(desc[n].parent) ? desc[n].parent : default_parent;
+		ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
+					desc[n].flags, base, desc[n].bit_idx,
+					0, &ctrl->lock);
+		WARN_ON(IS_ERR(ctrl->gates[n]));
+	}
+
+	of_clk_add_provider(np, clk_gating_get_src, ctrl);
+}
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
new file mode 100644
index 0000000..f968b4d
--- /dev/null
+++ b/drivers/clk/mvebu/common.h
@@ -0,0 +1,48 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CLK_MVEBU_COMMON_H_
+#define __CLK_MVEBU_COMMON_H_
+
+#include <linux/kernel.h>
+
+struct device_node;
+
+struct coreclk_ratio {
+	int id;
+	const char *name;
+};
+
+struct coreclk_soc_desc {
+	u32 (*get_tclk_freq)(void __iomem *sar);
+	u32 (*get_cpu_freq)(void __iomem *sar);
+	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+	const struct coreclk_ratio *ratios;
+	int num_ratios;
+};
+
+struct clk_gating_soc_desc {
+	const char *name;
+	const char *parent;
+	int bit_idx;
+	unsigned long flags;
+};
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+				const struct coreclk_soc_desc *desc);
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+				   const struct clk_gating_soc_desc *desc);
+
+#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:05 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:05 +0200
Subject: [PATCH 05/10] clk: mvebu: add Armada 370 SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-6-git-send-email-sebastian.hesselbarth@gmail.com>

This is moving core clock and clock gating init for Armada 370 to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/Kconfig      |    5 ++
 drivers/clk/mvebu/Makefile     |    1 +
 drivers/clk/mvebu/armada-370.c |  176 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 182 insertions(+)
 create mode 100644 drivers/clk/mvebu/armada-370.c

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 211695c..1daf61e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -10,6 +10,11 @@ config MVEBU_CLK_GATING
 config MVEBU_CLK_COMMON
 	bool
 
+config ARMADA_370_CLK
+	bool
+	select MVEBU_CLK_COMMON
+	select MVEBU_CLK_CPU
+
 config DOVE_CLK
 	bool
 	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 97d1ab0..367b72c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_MVEBU_CLK_CORE) 	+= clk.o clk-core.o
 obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
 
+obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 0000000..3c11550
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL				0	/* Low part [0:31] */
+#define	 SARL_A370_PCLK_FREQ_OPT	11
+#define	 SARL_A370_PCLK_FREQ_OPT_MASK	0xF
+#define	 SARL_A370_FAB_FREQ_OPT		15
+#define	 SARL_A370_FAB_FREQ_OPT_MASK	0x1F
+#define	 SARL_A370_TCLK_FREQ_OPT	20
+#define	 SARL_A370_TCLK_FREQ_OPT_MASK	0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+	{ .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+	{ .id = A370_CPU_TO_HCLK, .name = "hclk" },
+	{ .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+	16600000,
+	20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+	u8 tclk_freq_select = 0;
+
+	tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+			    SARL_A370_TCLK_FREQ_OPT_MASK);
+	return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+	400000000,
+	533000000,
+	667000000,
+	800000000,
+	1000000000,
+	1067000000,
+	1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+	u32 cpu_freq;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+			   SARL_A370_PCLK_FREQ_OPT_MASK);
+	if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+		pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+		cpu_freq = 0;
+	} else
+		cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+	return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 2}, {2, 2},
+	{1, 2}, {1, 2}, {1, 1}, {2, 3},
+	{0, 1}, {1, 2}, {2, 4}, {0, 1},
+	{1, 2}, {0, 1}, {0, 1}, {2, 2},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 6}, {2, 3},
+	{1, 3}, {1, 4}, {1, 2}, {2, 6},
+	{0, 1}, {1, 6}, {2, 10}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 2},
+	{2, 6}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 3}, {2, 3},
+	{1, 3}, {1, 2}, {1, 2}, {2, 6},
+	{0, 1}, {1, 3}, {2, 5}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+		SARL_A370_FAB_FREQ_OPT_MASK);
+
+	switch (id) {
+	case A370_CPU_TO_NBCLK:
+		*mult = a370_nbclk_ratios[opt][0];
+		*div = a370_nbclk_ratios[opt][1];
+		break;
+	case A370_CPU_TO_HCLK:
+		*mult = a370_hclk_ratios[opt][0];
+		*div = a370_hclk_ratios[opt][1];
+		break;
+	case A370_CPU_TO_DRAMCLK:
+		*mult = a370_dramclk_ratios[opt][0];
+		*div = a370_dramclk_ratios[opt][1];
+		break;
+	}
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+	.get_tclk_freq = a370_get_tclk_freq,
+	.get_cpu_freq = a370_get_cpu_freq,
+	.get_clk_ratio = a370_get_clk_ratio,
+	.ratios = a370_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+	       a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+	{ "audio", NULL, 0, 0 },
+	{ "pex0_en", NULL, 1, 0 },
+	{ "pex1_en", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex0", NULL, 5, 0 },
+	{ "pex1", NULL, 9, 0 },
+	{ "sata0", NULL, 15, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+	{ "sata1", NULL, 30, 0 },
+	{ }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+	       a370_clk_gating_init);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:06 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:06 +0200
Subject: [PATCH 06/10] clk: mvebu: add Armada XP SoC-centric clock init
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-7-git-send-email-sebastian.hesselbarth@gmail.com>

This is moving core clock and clock gating init for Armada XP to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/Kconfig     |    5 +
 drivers/clk/mvebu/Makefile    |    1 +
 drivers/clk/mvebu/armada-xp.c |  204 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 210 insertions(+)
 create mode 100644 drivers/clk/mvebu/armada-xp.c

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 1daf61e..8740d34 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -15,6 +15,11 @@ config ARMADA_370_CLK
 	select MVEBU_CLK_COMMON
 	select MVEBU_CLK_CPU
 
+config ARMADA_XP_CLK
+	bool
+	select MVEBU_CLK_COMMON
+	select MVEBU_CLK_CPU
+
 config DOVE_CLK
 	bool
 	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 367b72c..13f3d22 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
 
 obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 0000000..cf7612e
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,204 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL				0	/* Low part [0:31] */
+#define	 SARL_AXP_PCLK_FREQ_OPT		21
+#define	 SARL_AXP_PCLK_FREQ_OPT_MASK	0x7
+#define	 SARL_AXP_FAB_FREQ_OPT		24
+#define	 SARL_AXP_FAB_FREQ_OPT_MASK	0xF
+#define SARH				4	/* High part [32:63] */
+#define	 SARH_AXP_PCLK_FREQ_OPT		(52-32)
+#define	 SARH_AXP_PCLK_FREQ_OPT_MASK	0x1
+#define	 SARH_AXP_PCLK_FREQ_OPT_SHIFT	3
+#define	 SARH_AXP_FAB_FREQ_OPT		(51-32)
+#define	 SARH_AXP_FAB_FREQ_OPT_MASK	0x1
+#define	 SARH_AXP_FAB_FREQ_OPT_SHIFT	4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+	{ .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+	{ .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+	{ .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+	return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+	1000000000,
+	1066000000,
+	1200000000,
+	1333000000,
+	1500000000,
+	1666000000,
+	1800000000,
+	2000000000,
+	667000000,
+	0,
+	800000000,
+	1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+	u32 cpu_freq;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+			   SARL_AXP_PCLK_FREQ_OPT_MASK);
+	/*
+	 * The upper bit is not contiguous to the other ones and
+	 * located in the high part of the SAR registers
+	 */
+	cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+	     SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+	if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+		pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+		cpu_freq = 0;
+	} else
+		cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+	return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 2}, {2, 2},
+	{1, 2}, {1, 2}, {1, 1}, {2, 3},
+	{0, 1}, {1, 2}, {2, 4}, {0, 1},
+	{1, 2}, {0, 1}, {0, 1}, {2, 2},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 6}, {2, 3},
+	{1, 3}, {1, 4}, {1, 2}, {2, 6},
+	{0, 1}, {1, 6}, {2, 10}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 2},
+	{2, 6}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 3}, {2, 3},
+	{1, 3}, {1, 2}, {1, 2}, {2, 6},
+	{0, 1}, {1, 3}, {2, 5}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+	      SARL_AXP_FAB_FREQ_OPT_MASK);
+	/*
+	 * The upper bit is not contiguous to the other ones and
+	 * located in the high part of the SAR registers
+	 */
+	opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+		 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+	switch (id) {
+	case AXP_CPU_TO_NBCLK:
+		*mult = axp_nbclk_ratios[opt][0];
+		*div = axp_nbclk_ratios[opt][1];
+		break;
+	case AXP_CPU_TO_HCLK:
+		*mult = axp_hclk_ratios[opt][0];
+		*div = axp_hclk_ratios[opt][1];
+		break;
+	case AXP_CPU_TO_DRAMCLK:
+		*mult = axp_dramclk_ratios[opt][0];
+		*div = axp_dramclk_ratios[opt][1];
+		break;
+	}
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+	.get_tclk_freq = axp_get_tclk_freq,
+	.get_cpu_freq = axp_get_cpu_freq,
+	.get_clk_ratio = axp_get_clk_ratio,
+	.ratios = axp_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+	       axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+	{ "audio", NULL, 0, 0 },
+	{ "ge3", NULL, 1, 0 },
+	{ "ge2", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex0", NULL, 5, 0 },
+	{ "pex1", NULL, 6, 0 },
+	{ "pex2", NULL, 7, 0 },
+	{ "pex3", NULL, 8, 0 },
+	{ "bp", NULL, 13, 0 },
+	{ "sata0lnk", NULL, 14, 0 },
+	{ "sata0", "sata0lnk", 15, 0 },
+	{ "lcd", NULL, 16, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "usb0", NULL, 18, 0 },
+	{ "usb1", NULL, 19, 0 },
+	{ "usb2", NULL, 20, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ "crypto", NULL, 23, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "xor1", NULL, 28, 0 },
+	{ "sata1lnk", NULL, 29, 0 },
+	{ "sata1", "sata1lnk", 30, 0 },
+	{ }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+	       axp_clk_gating_init);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:10 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:10 +0200
Subject: [PATCH 10/10] clk: mvebu: desintegrate obsolete file
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-11-git-send-email-sebastian.hesselbarth@gmail.com>

Switch from function-centric to soc-centric clock drivers now makes
a bunch of files obsolete. This deletes all files and Kconfig options
that are not required anymore.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/Kconfig           |   10 +-
 drivers/clk/mvebu/Makefile          |    2 -
 drivers/clk/mvebu/clk-core.c        |  675 -----------------------------------
 drivers/clk/mvebu/clk-core.h        |   18 -
 drivers/clk/mvebu/clk-gating-ctrl.c |  241 -------------
 drivers/clk/mvebu/clk-gating-ctrl.h |   22 --
 drivers/clk/mvebu/clk.c             |   23 --
 include/linux/clk/mvebu.h           |   22 --
 8 files changed, 2 insertions(+), 1011 deletions(-)
 delete mode 100644 drivers/clk/mvebu/clk-core.c
 delete mode 100644 drivers/clk/mvebu/clk-core.h
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
 delete mode 100644 drivers/clk/mvebu/clk.c
 delete mode 100644 include/linux/clk/mvebu.h

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 8740d34..0b0f3e7 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -1,13 +1,7 @@
-config MVEBU_CLK_CORE
-       bool
+config MVEBU_CLK_COMMON
+	bool
 
 config MVEBU_CLK_CPU
-       bool
-
-config MVEBU_CLK_GATING
-       bool
-
-config MVEBU_CLK_COMMON
 	bool
 
 config ARMADA_370_CLK
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 13f3d22..1c7e70c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,7 +1,5 @@
 obj-$(CONFIG_MVEBU_CLK_COMMON)	+= common.o
-obj-$(CONFIG_MVEBU_CLK_CORE) 	+= clk.o clk-core.o
 obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
-obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
 
 obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
 obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
deleted file mode 100644
index 0a53edb..0000000
--- a/drivers/clk/mvebu/clk-core.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement at free-electrons.com>
- * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include "clk-core.h"
-
-struct core_ratio {
-	int id;
-	const char *name;
-};
-
-struct core_clocks {
-	u32 (*get_tclk_freq)(void __iomem *sar);
-	u32 (*get_cpu_freq)(void __iomem *sar);
-	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
-	const struct core_ratio *ratios;
-	int num_ratios;
-};
-
-static struct clk_onecell_data clk_data;
-
-static void __init mvebu_clk_core_setup(struct device_node *np,
-				 struct core_clocks *coreclk)
-{
-	const char *tclk_name = "tclk";
-	const char *cpuclk_name = "cpuclk";
-	void __iomem *base;
-	unsigned long rate;
-	int n;
-
-	base = of_iomap(np, 0);
-	if (WARN_ON(!base))
-		return;
-
-	/*
-	 * Allocate struct for TCLK, cpu clk, and core ratio clocks
-	 */
-	clk_data.clk_num = 2 + coreclk->num_ratios;
-	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
-				GFP_KERNEL);
-	if (WARN_ON(!clk_data.clks))
-		return;
-
-	/*
-	 * Register TCLK
-	 */
-	of_property_read_string_index(np, "clock-output-names", 0,
-				      &tclk_name);
-	rate = coreclk->get_tclk_freq(base);
-	clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
-						   CLK_IS_ROOT, rate);
-	WARN_ON(IS_ERR(clk_data.clks[0]));
-
-	/*
-	 * Register CPU clock
-	 */
-	of_property_read_string_index(np, "clock-output-names", 1,
-				      &cpuclk_name);
-	rate = coreclk->get_cpu_freq(base);
-	clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
-						   CLK_IS_ROOT, rate);
-	WARN_ON(IS_ERR(clk_data.clks[1]));
-
-	/*
-	 * Register fixed-factor clocks derived from CPU clock
-	 */
-	for (n = 0; n < coreclk->num_ratios; n++) {
-		const char *rclk_name = coreclk->ratios[n].name;
-		int mult, div;
-
-		of_property_read_string_index(np, "clock-output-names",
-					      2+n, &rclk_name);
-		coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
-				       &mult, &div);
-		clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
-				       cpuclk_name, 0, mult, div);
-		WARN_ON(IS_ERR(clk_data.clks[2+n]));
-	};
-
-	/*
-	 * SAR register isn't needed anymore
-	 */
-	iounmap(base);
-
-	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-#ifdef CONFIG_MACH_ARMADA_370_XP
-/*
- * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
- */
-
-#define SARL				    0	/* Low part [0:31] */
-#define	    SARL_AXP_PCLK_FREQ_OPT	    21
-#define	    SARL_AXP_PCLK_FREQ_OPT_MASK	    0x7
-#define	    SARL_A370_PCLK_FREQ_OPT	    11
-#define	    SARL_A370_PCLK_FREQ_OPT_MASK    0xF
-#define	    SARL_AXP_FAB_FREQ_OPT	    24
-#define	    SARL_AXP_FAB_FREQ_OPT_MASK	    0xF
-#define	    SARL_A370_FAB_FREQ_OPT	    15
-#define	    SARL_A370_FAB_FREQ_OPT_MASK	    0x1F
-#define	    SARL_A370_TCLK_FREQ_OPT	    20
-#define	    SARL_A370_TCLK_FREQ_OPT_MASK    0x1
-#define SARH				    4	/* High part [32:63] */
-#define	    SARH_AXP_PCLK_FREQ_OPT	    (52-32)
-#define	    SARH_AXP_PCLK_FREQ_OPT_MASK	    0x1
-#define	    SARH_AXP_PCLK_FREQ_OPT_SHIFT    3
-#define	    SARH_AXP_FAB_FREQ_OPT	    (51-32)
-#define	    SARH_AXP_FAB_FREQ_OPT_MASK	    0x1
-#define	    SARH_AXP_FAB_FREQ_OPT_SHIFT	    4
-
-static const u32 __initconst armada_370_tclk_frequencies[] = {
-	16600000,
-	20000000,
-};
-
-static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
-{
-	u8 tclk_freq_select = 0;
-
-	tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
-			    SARL_A370_TCLK_FREQ_OPT_MASK);
-	return armada_370_tclk_frequencies[tclk_freq_select];
-}
-
-static const u32 __initconst armada_370_cpu_frequencies[] = {
-	400000000,
-	533000000,
-	667000000,
-	800000000,
-	1000000000,
-	1067000000,
-	1200000000,
-};
-
-static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
-{
-	u32 cpu_freq;
-	u8 cpu_freq_select = 0;
-
-	cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
-			   SARL_A370_PCLK_FREQ_OPT_MASK);
-	if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
-		pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
-		cpu_freq = 0;
-	} else
-		cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
-
-	return cpu_freq;
-}
-
-enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
-
-static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
-	{ .id = A370_XP_NBCLK,	 .name = "nbclk" },
-	{ .id = A370_XP_HCLK,	 .name = "hclk" },
-	{ .id = A370_XP_DRAMCLK, .name = "dramclk" },
-};
-
-static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
-	{0, 1}, {1, 2}, {2, 2}, {2, 2},
-	{1, 2}, {1, 2}, {1, 1}, {2, 3},
-	{0, 1}, {1, 2}, {2, 4}, {0, 1},
-	{1, 2}, {0, 1}, {0, 1}, {2, 2},
-	{0, 1}, {0, 1}, {0, 1}, {1, 1},
-	{2, 3}, {0, 1}, {0, 1}, {0, 1},
-	{0, 1}, {0, 1}, {0, 1}, {1, 1},
-	{0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
-	{0, 1}, {1, 2}, {2, 6}, {2, 3},
-	{1, 3}, {1, 4}, {1, 2}, {2, 6},
-	{0, 1}, {1, 6}, {2, 10}, {0, 1},
-	{1, 4}, {0, 1}, {0, 1}, {2, 5},
-	{0, 1}, {0, 1}, {0, 1}, {1, 2},
-	{2, 6}, {0, 1}, {0, 1}, {0, 1},
-	{0, 1}, {0, 1}, {0, 1}, {1, 1},
-	{0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
-	{0, 1}, {1, 2}, {2, 3}, {2, 3},
-	{1, 3}, {1, 2}, {1, 2}, {2, 6},
-	{0, 1}, {1, 3}, {2, 5}, {0, 1},
-	{1, 4}, {0, 1}, {0, 1}, {2, 5},
-	{0, 1}, {0, 1}, {0, 1}, {1, 1},
-	{2, 3}, {0, 1}, {0, 1}, {0, 1},
-	{0, 1}, {0, 1}, {0, 1}, {1, 1},
-	{0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static void __init armada_370_xp_get_clk_ratio(u32 opt,
-	void __iomem *sar, int id, int *mult, int *div)
-{
-	switch (id) {
-	case A370_XP_NBCLK:
-		*mult = armada_370_xp_nbclk_ratios[opt][0];
-		*div = armada_370_xp_nbclk_ratios[opt][1];
-		break;
-	case A370_XP_HCLK:
-		*mult = armada_370_xp_hclk_ratios[opt][0];
-		*div = armada_370_xp_hclk_ratios[opt][1];
-		break;
-	case A370_XP_DRAMCLK:
-		*mult = armada_370_xp_dramclk_ratios[opt][0];
-		*div = armada_370_xp_dramclk_ratios[opt][1];
-		break;
-	}
-}
-
-static void __init armada_370_get_clk_ratio(
-	void __iomem *sar, int id, int *mult, int *div)
-{
-	u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
-		SARL_A370_FAB_FREQ_OPT_MASK);
-
-	armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-
-static const struct core_clocks armada_370_core_clocks = {
-	.get_tclk_freq = armada_370_get_tclk_freq,
-	.get_cpu_freq = armada_370_get_cpu_freq,
-	.get_clk_ratio = armada_370_get_clk_ratio,
-	.ratios = armada_370_xp_core_ratios,
-	.num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-static const u32 __initconst armada_xp_cpu_frequencies[] = {
-	1000000000,
-	1066000000,
-	1200000000,
-	1333000000,
-	1500000000,
-	1666000000,
-	1800000000,
-	2000000000,
-	667000000,
-	0,
-	800000000,
-	1600000000,
-};
-
-/* For Armada XP TCLK frequency is fix: 250MHz */
-static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
-{
-	return 250 * 1000 * 1000;
-}
-
-static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
-{
-	u32 cpu_freq;
-	u8 cpu_freq_select = 0;
-
-	cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
-			   SARL_AXP_PCLK_FREQ_OPT_MASK);
-	/*
-	 * The upper bit is not contiguous to the other ones and
-	 * located in the high part of the SAR registers
-	 */
-	cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
-			     SARH_AXP_PCLK_FREQ_OPT_MASK)
-			    << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
-	if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
-		pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
-		cpu_freq = 0;
-	} else
-		cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
-
-	return cpu_freq;
-}
-
-static void __init armada_xp_get_clk_ratio(
-	void __iomem *sar, int id, int *mult, int *div)
-{
-
-	u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
-	      SARL_AXP_FAB_FREQ_OPT_MASK);
-	/*
-	 * The upper bit is not contiguous to the other ones and
-	 * located in the high part of the SAR registers
-	 */
-	opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
-		SARH_AXP_FAB_FREQ_OPT_MASK)
-	       << SARH_AXP_FAB_FREQ_OPT_SHIFT);
-
-	armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-static const struct core_clocks armada_xp_core_clocks = {
-	.get_tclk_freq = armada_xp_get_tclk_freq,
-	.get_cpu_freq = armada_xp_get_cpu_freq,
-	.get_clk_ratio = armada_xp_get_clk_ratio,
-	.ratios = armada_370_xp_core_ratios,
-	.num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-#endif /* CONFIG_MACH_ARMADA_370_XP */
-
-/*
- * Dove PLL sample-at-reset configuration
- *
- * SAR0[8:5]   : CPU frequency
- *		 5  = 1000 MHz
- *		 6  =  933 MHz
- *		 7  =  933 MHz
- *		 8  =  800 MHz
- *		 9  =  800 MHz
- *		 10 =  800 MHz
- *		 11 = 1067 MHz
- *		 12 =  667 MHz
- *		 13 =  533 MHz
- *		 14 =  400 MHz
- *		 15 =  333 MHz
- *		 others reserved.
- *
- * SAR0[11:9]  : CPU to L2 Clock divider ratio
- *		 0 = (1/1) * CPU
- *		 2 = (1/2) * CPU
- *		 4 = (1/3) * CPU
- *		 6 = (1/4) * CPU
- *		 others reserved.
- *
- * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
- *		 0  = (1/1) * CPU
- *		 2  = (1/2) * CPU
- *		 3  = (2/5) * CPU
- *		 4  = (1/3) * CPU
- *		 6  = (1/4) * CPU
- *		 8  = (1/5) * CPU
- *		 10 = (1/6) * CPU
- *		 12 = (1/7) * CPU
- *		 14 = (1/8) * CPU
- *		 15 = (1/10) * CPU
- *		 others reserved.
- *
- * SAR0[24:23] : TCLK frequency
- *		 0 = 166 MHz
- *		 1 = 125 MHz
- *		 others reserved.
- */
-#ifdef CONFIG_ARCH_DOVE
-#define SAR_DOVE_CPU_FREQ		5
-#define SAR_DOVE_CPU_FREQ_MASK		0xf
-#define SAR_DOVE_L2_RATIO		9
-#define SAR_DOVE_L2_RATIO_MASK		0x7
-#define SAR_DOVE_DDR_RATIO		12
-#define SAR_DOVE_DDR_RATIO_MASK		0xf
-#define SAR_DOVE_TCLK_FREQ		23
-#define SAR_DOVE_TCLK_FREQ_MASK		0x3
-
-static const u32 __initconst dove_tclk_frequencies[] = {
-	166666667,
-	125000000,
-	0, 0
-};
-
-static u32 __init dove_get_tclk_freq(void __iomem *sar)
-{
-	u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
-		SAR_DOVE_TCLK_FREQ_MASK;
-	return dove_tclk_frequencies[opt];
-}
-
-static const u32 __initconst dove_cpu_frequencies[] = {
-	0, 0, 0, 0, 0,
-	1000000000,
-	933333333, 933333333,
-	800000000, 800000000, 800000000,
-	1066666667,
-	666666667,
-	533333333,
-	400000000,
-	333333333
-};
-
-static u32 __init dove_get_cpu_freq(void __iomem *sar)
-{
-	u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
-		SAR_DOVE_CPU_FREQ_MASK;
-	return dove_cpu_frequencies[opt];
-}
-
-enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
-
-static const struct core_ratio __initconst dove_core_ratios[] = {
-	{ .id = DOVE_CPU_TO_L2, .name = "l2clk", },
-	{ .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static const int __initconst dove_cpu_l2_ratios[8][2] = {
-	{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
-	{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
-};
-
-static const int __initconst dove_cpu_ddr_ratios[16][2] = {
-	{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
-	{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
-	{ 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
-	{ 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
-};
-
-static void __init dove_get_clk_ratio(
-	void __iomem *sar, int id, int *mult, int *div)
-{
-	switch (id) {
-	case DOVE_CPU_TO_L2:
-	{
-		u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
-			SAR_DOVE_L2_RATIO_MASK;
-		*mult = dove_cpu_l2_ratios[opt][0];
-		*div = dove_cpu_l2_ratios[opt][1];
-		break;
-	}
-	case DOVE_CPU_TO_DDR:
-	{
-		u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
-			SAR_DOVE_DDR_RATIO_MASK;
-		*mult = dove_cpu_ddr_ratios[opt][0];
-		*div = dove_cpu_ddr_ratios[opt][1];
-		break;
-	}
-	}
-}
-
-static const struct core_clocks dove_core_clocks = {
-	.get_tclk_freq = dove_get_tclk_freq,
-	.get_cpu_freq = dove_get_cpu_freq,
-	.get_clk_ratio = dove_get_clk_ratio,
-	.ratios = dove_core_ratios,
-	.num_ratios = ARRAY_SIZE(dove_core_ratios),
-};
-#endif /* CONFIG_ARCH_DOVE */
-
-/*
- * Kirkwood PLL sample-at-reset configuration
- * (6180 has different SAR layout than other Kirkwood SoCs)
- *
- * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
- *	4  =  600 MHz
- *	6  =  800 MHz
- *	7  = 1000 MHz
- *	9  = 1200 MHz
- *	12 = 1500 MHz
- *	13 = 1600 MHz
- *	14 = 1800 MHz
- *	15 = 2000 MHz
- *	others reserved.
- *
- * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
- *	1 = (1/2) * CPU
- *	3 = (1/3) * CPU
- *	5 = (1/4) * CPU
- *	others reserved.
- *
- * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
- *	2 = (1/2) * CPU
- *	4 = (1/3) * CPU
- *	6 = (1/4) * CPU
- *	7 = (2/9) * CPU
- *	8 = (1/5) * CPU
- *	9 = (1/6) * CPU
- *	others reserved.
- *
- * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
- *	5 = [CPU =  600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
- *	6 = [CPU =  800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
- *	7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
- *	others reserved.
- *
- * SAR0[21] : TCLK frequency
- *	0 = 200 MHz
- *	1 = 166 MHz
- *	others reserved.
- */
-#ifdef CONFIG_ARCH_KIRKWOOD
-#define SAR_KIRKWOOD_CPU_FREQ(x)	\
-	(((x & (1 <<  1)) >>  1) |	\
-	 ((x & (1 << 22)) >> 21) |	\
-	 ((x & (3 <<  3)) >>  1))
-#define SAR_KIRKWOOD_L2_RATIO(x)	\
-	(((x & (3 <<  9)) >> 9) |	\
-	 (((x & (1 << 19)) >> 17)))
-#define SAR_KIRKWOOD_DDR_RATIO		5
-#define SAR_KIRKWOOD_DDR_RATIO_MASK	0xf
-#define SAR_MV88F6180_CLK		2
-#define SAR_MV88F6180_CLK_MASK		0x7
-#define SAR_KIRKWOOD_TCLK_FREQ		21
-#define SAR_KIRKWOOD_TCLK_FREQ_MASK	0x1
-
-enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
-
-static const struct core_ratio __initconst kirkwood_core_ratios[] = {
-	{ .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
-	{ .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
-{
-	u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
-		SAR_KIRKWOOD_TCLK_FREQ_MASK;
-	return (opt) ? 166666667 : 200000000;
-}
-
-static const u32 __initconst kirkwood_cpu_frequencies[] = {
-	0, 0, 0, 0,
-	600000000,
-	0,
-	800000000,
-	1000000000,
-	0,
-	1200000000,
-	0, 0,
-	1500000000,
-	1600000000,
-	1800000000,
-	2000000000
-};
-
-static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
-{
-	u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
-	return kirkwood_cpu_frequencies[opt];
-}
-
-static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
-	{ 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
-	{ 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
-};
-
-static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
-	{ 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
-	{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
-	{ 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
-	{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
-};
-
-static void __init kirkwood_get_clk_ratio(
-	void __iomem *sar, int id, int *mult, int *div)
-{
-	switch (id) {
-	case KIRKWOOD_CPU_TO_L2:
-	{
-		u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
-		*mult = kirkwood_cpu_l2_ratios[opt][0];
-		*div = kirkwood_cpu_l2_ratios[opt][1];
-		break;
-	}
-	case KIRKWOOD_CPU_TO_DDR:
-	{
-		u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
-			SAR_KIRKWOOD_DDR_RATIO_MASK;
-		*mult = kirkwood_cpu_ddr_ratios[opt][0];
-		*div = kirkwood_cpu_ddr_ratios[opt][1];
-		break;
-	}
-	}
-}
-
-static const struct core_clocks kirkwood_core_clocks = {
-	.get_tclk_freq = kirkwood_get_tclk_freq,
-	.get_cpu_freq = kirkwood_get_cpu_freq,
-	.get_clk_ratio = kirkwood_get_clk_ratio,
-	.ratios = kirkwood_core_ratios,
-	.num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-
-static const u32 __initconst mv88f6180_cpu_frequencies[] = {
-	0, 0, 0, 0, 0,
-	600000000,
-	800000000,
-	1000000000
-};
-
-static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
-{
-	u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
-	return mv88f6180_cpu_frequencies[opt];
-}
-
-static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
-	{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
-	{ 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
-};
-
-static void __init mv88f6180_get_clk_ratio(
-	void __iomem *sar, int id, int *mult, int *div)
-{
-	switch (id) {
-	case KIRKWOOD_CPU_TO_L2:
-	{
-		/* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
-		*mult = 1;
-		*div = 2;
-		break;
-	}
-	case KIRKWOOD_CPU_TO_DDR:
-	{
-		u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
-			SAR_MV88F6180_CLK_MASK;
-		*mult = mv88f6180_cpu_ddr_ratios[opt][0];
-		*div = mv88f6180_cpu_ddr_ratios[opt][1];
-		break;
-	}
-	}
-}
-
-static const struct core_clocks mv88f6180_core_clocks = {
-	.get_tclk_freq = kirkwood_get_tclk_freq,
-	.get_cpu_freq = mv88f6180_get_cpu_freq,
-	.get_clk_ratio = mv88f6180_get_clk_ratio,
-	.ratios = kirkwood_core_ratios,
-	.num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-#endif /* CONFIG_ARCH_KIRKWOOD */
-
-static const __initdata struct of_device_id clk_core_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370_XP
-	{
-		.compatible = "marvell,armada-370-core-clock",
-		.data = &armada_370_core_clocks,
-	},
-	{
-		.compatible = "marvell,armada-xp-core-clock",
-		.data = &armada_xp_core_clocks,
-	},
-#endif
-#ifdef CONFIG_ARCH_DOVE
-	{
-		.compatible = "marvell,dove-core-clock",
-		.data = &dove_core_clocks,
-	},
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-	{
-		.compatible = "marvell,kirkwood-core-clock",
-		.data = &kirkwood_core_clocks,
-	},
-	{
-		.compatible = "marvell,mv88f6180-core-clock",
-		.data = &mv88f6180_core_clocks,
-	},
-#endif
-
-	{ }
-};
-
-void __init mvebu_core_clk_init(void)
-{
-	struct device_node *np;
-
-	for_each_matching_node(np, clk_core_match) {
-		const struct of_device_id *match =
-			of_match_node(clk_core_match, np);
-		mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
-	}
-}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
deleted file mode 100644
index 28b5e02..0000000
--- a/drivers/clk/mvebu/clk-core.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement at free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_CORE_H
-#define __MVEBU_CLK_CORE_H
-
-void __init mvebu_core_clk_init(void);
-
-#endif
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
deleted file mode 100644
index a88e09b..0000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Marvell MVEBU clock gating control.
- *
- * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
- * Andrew Lunn <andrew at lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mvebu_gating_ctrl {
-	spinlock_t lock;
-	struct clk **gates;
-	int num_gates;
-};
-
-struct mvebu_soc_descr {
-	const char *name;
-	const char *parent;
-	int bit_idx;
-	unsigned long flags;
-};
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static struct clk *mvebu_clk_gating_get_src(
-	struct of_phandle_args *clkspec, void *data)
-{
-	struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
-	int n;
-
-	if (clkspec->args_count < 1)
-		return ERR_PTR(-EINVAL);
-
-	for (n = 0; n < ctrl->num_gates; n++) {
-		struct clk_gate *gate =
-			to_clk_gate(__clk_get_hw(ctrl->gates[n]));
-		if (clkspec->args[0] == gate->bit_idx)
-			return ctrl->gates[n];
-	}
-	return ERR_PTR(-ENODEV);
-}
-
-static void __init mvebu_clk_gating_setup(
-	struct device_node *np, const struct mvebu_soc_descr *descr)
-{
-	struct mvebu_gating_ctrl *ctrl;
-	struct clk *clk;
-	void __iomem *base;
-	const char *default_parent = NULL;
-	int n;
-
-	base = of_iomap(np, 0);
-
-	clk = of_clk_get(np, 0);
-	if (!IS_ERR(clk)) {
-		default_parent = __clk_get_name(clk);
-		clk_put(clk);
-	}
-
-	ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
-	if (WARN_ON(!ctrl))
-		return;
-
-	spin_lock_init(&ctrl->lock);
-
-	/*
-	 * Count, allocate, and register clock gates
-	 */
-	for (n = 0; descr[n].name;)
-		n++;
-
-	ctrl->num_gates = n;
-	ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
-			      GFP_KERNEL);
-	if (WARN_ON(!ctrl->gates)) {
-		kfree(ctrl);
-		return;
-	}
-
-	for (n = 0; n < ctrl->num_gates; n++) {
-		const char *parent =
-			(descr[n].parent) ? descr[n].parent : default_parent;
-		ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
-					descr[n].flags, base, descr[n].bit_idx,
-					0, &ctrl->lock);
-		WARN_ON(IS_ERR(ctrl->gates[n]));
-	}
-	of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
-}
-
-/*
- * SoC specific clock gating control
- */
-
-#ifdef CONFIG_MACH_ARMADA_370
-static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
-	{ "audio", NULL, 0, 0 },
-	{ "pex0_en", NULL, 1, 0 },
-	{ "pex1_en", NULL,  2, 0 },
-	{ "ge1", NULL, 3, 0 },
-	{ "ge0", NULL, 4, 0 },
-	{ "pex0", NULL, 5, 0 },
-	{ "pex1", NULL, 9, 0 },
-	{ "sata0", NULL, 15, 0 },
-	{ "sdio", NULL, 17, 0 },
-	{ "tdm", NULL, 25, 0 },
-	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
-	{ "sata1", NULL, 30, 0 },
-	{ }
-};
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
-	{ "audio", NULL, 0, 0 },
-	{ "ge3", NULL, 1, 0 },
-	{ "ge2", NULL,  2, 0 },
-	{ "ge1", NULL, 3, 0 },
-	{ "ge0", NULL, 4, 0 },
-	{ "pex0", NULL, 5, 0 },
-	{ "pex1", NULL, 6, 0 },
-	{ "pex2", NULL, 7, 0 },
-	{ "pex3", NULL, 8, 0 },
-	{ "bp", NULL, 13, 0 },
-	{ "sata0lnk", NULL, 14, 0 },
-	{ "sata0", "sata0lnk", 15, 0 },
-	{ "lcd", NULL, 16, 0 },
-	{ "sdio", NULL, 17, 0 },
-	{ "usb0", NULL, 18, 0 },
-	{ "usb1", NULL, 19, 0 },
-	{ "usb2", NULL, 20, 0 },
-	{ "xor0", NULL, 22, 0 },
-	{ "crypto", NULL, 23, 0 },
-	{ "tdm", NULL, 25, 0 },
-	{ "xor1", NULL, 28, 0 },
-	{ "sata1lnk", NULL, 29, 0 },
-	{ "sata1", "sata1lnk", 30, 0 },
-	{ }
-};
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
-	{ "usb0", NULL, 0, 0 },
-	{ "usb1", NULL, 1, 0 },
-	{ "ge", "gephy", 2, 0 },
-	{ "sata", NULL, 3, 0 },
-	{ "pex0", NULL, 4, 0 },
-	{ "pex1", NULL, 5, 0 },
-	{ "sdio0", NULL, 8, 0 },
-	{ "sdio1", NULL, 9, 0 },
-	{ "nand", NULL, 10, 0 },
-	{ "camera", NULL, 11, 0 },
-	{ "i2s0", NULL, 12, 0 },
-	{ "i2s1", NULL, 13, 0 },
-	{ "crypto", NULL, 15, 0 },
-	{ "ac97", NULL, 21, 0 },
-	{ "pdma", NULL, 22, 0 },
-	{ "xor0", NULL, 23, 0 },
-	{ "xor1", NULL, 24, 0 },
-	{ "gephy", NULL, 30, 0 },
-	{ }
-};
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
-	{ "ge0", NULL, 0, 0 },
-	{ "pex0", NULL, 2, 0 },
-	{ "usb0", NULL, 3, 0 },
-	{ "sdio", NULL, 4, 0 },
-	{ "tsu", NULL, 5, 0 },
-	{ "runit", NULL, 7, 0 },
-	{ "xor0", NULL, 8, 0 },
-	{ "audio", NULL, 9, 0 },
-	{ "powersave", "cpuclk", 11, 0 },
-	{ "sata0", NULL, 14, 0 },
-	{ "sata1", NULL, 15, 0 },
-	{ "xor1", NULL, 16, 0 },
-	{ "crypto", NULL, 17, 0 },
-	{ "pex1", NULL, 18, 0 },
-	{ "ge1", NULL, 19, 0 },
-	{ "tdm", NULL, 20, 0 },
-	{ }
-};
-#endif
-
-static const __initdata struct of_device_id clk_gating_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370
-	{
-		.compatible = "marvell,armada-370-gating-clock",
-		.data = armada_370_gating_descr,
-	},
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-	{
-		.compatible = "marvell,armada-xp-gating-clock",
-		.data = armada_xp_gating_descr,
-	},
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-	{
-		.compatible = "marvell,dove-gating-clock",
-		.data = dove_gating_descr,
-	},
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-	{
-		.compatible = "marvell,kirkwood-gating-clock",
-		.data = kirkwood_gating_descr,
-	},
-#endif
-
-	{ }
-};
-
-void __init mvebu_gating_clk_init(void)
-{
-	struct device_node *np;
-
-	for_each_matching_node(np, clk_gating_match) {
-		const struct of_device_id *match =
-			of_match_node(clk_gating_match, np);
-		mvebu_clk_gating_setup(np,
-		       (const struct mvebu_soc_descr *)match->data);
-	}
-}
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h
deleted file mode 100644
index 9275d1e..0000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Marvell EBU gating clock handling
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_GATING_H
-#define __MVEBU_CLK_GATING_H
-
-#ifdef CONFIG_MVEBU_CLK_GATING
-void __init mvebu_gating_clk_init(void);
-#else
-void mvebu_gating_clk_init(void) {}
-#endif
-
-#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
deleted file mode 100644
index 29f10fb..0000000
--- a/drivers/clk/mvebu/clk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Marvell EBU SoC clock handling.
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement at free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include "clk-core.h"
-#include "clk-gating-ctrl.h"
-
-void __init mvebu_clocks_init(void)
-{
-	mvebu_core_clk_init();
-	mvebu_gating_clk_init();
-	of_clk_init(NULL);
-}
diff --git a/include/linux/clk/mvebu.h b/include/linux/clk/mvebu.h
deleted file mode 100644
index 8c4ae71..0000000
--- a/include/linux/clk/mvebu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __CLK_MVEBU_H_
-#define __CLK_MVEBU_H_
-
-void __init mvebu_clocks_init(void);
-
-#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Fri May 10 21:08:01 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 May 2013 03:08:01 +0200
Subject: [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1368234490-31416-2-git-send-email-sebastian.hesselbarth@gmail.com>

Clock gates found on MVEBU SoCs get registered by a common function.
To allow specific SoCs to provide tweaks introduce flags to the clock
gate descriptor instead of filling up the common function SoC specific
tweaks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/clk/mvebu/clk-gating-ctrl.c |  153 +++++++++++++++++------------------
 1 file changed, 72 insertions(+), 81 deletions(-)

diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index ebf141d..a88e09b 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
 	const char *name;
 	const char *parent;
 	int bit_idx;
+	unsigned long flags;
 };
 
 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
 	}
 
 	for (n = 0; n < ctrl->num_gates; n++) {
-		u8 flags = 0;
 		const char *parent =
 			(descr[n].parent) ? descr[n].parent : default_parent;
-
-		/*
-		 * On Armada 370, the DDR clock is a special case: it
-		 * isn't taken by any driver, but should anyway be
-		 * kept enabled, so we mark it as IGNORE_UNUSED for
-		 * now.
-		 */
-		if (!strcmp(descr[n].name, "ddr"))
-			flags |= CLK_IGNORE_UNUSED;
-
 		ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
-				   flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+					descr[n].flags, base, descr[n].bit_idx,
+					0, &ctrl->lock);
 		WARN_ON(IS_ERR(ctrl->gates[n]));
 	}
 	of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,93 +105,93 @@ static void __init mvebu_clk_gating_setup(
 
 #ifdef CONFIG_MACH_ARMADA_370
 static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
-	{ "audio", NULL, 0 },
-	{ "pex0_en", NULL, 1 },
-	{ "pex1_en", NULL,  2 },
-	{ "ge1", NULL, 3 },
-	{ "ge0", NULL, 4 },
-	{ "pex0", NULL, 5 },
-	{ "pex1", NULL, 9 },
-	{ "sata0", NULL, 15 },
-	{ "sdio", NULL, 17 },
-	{ "tdm", NULL, 25 },
-	{ "ddr", NULL, 28 },
-	{ "sata1", NULL, 30 },
+	{ "audio", NULL, 0, 0 },
+	{ "pex0_en", NULL, 1, 0 },
+	{ "pex1_en", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex0", NULL, 5, 0 },
+	{ "pex1", NULL, 9, 0 },
+	{ "sata0", NULL, 15, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+	{ "sata1", NULL, 30, 0 },
 	{ }
 };
 #endif
 
 #ifdef CONFIG_MACH_ARMADA_XP
 static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
-	{ "audio", NULL, 0 },
-	{ "ge3", NULL, 1 },
-	{ "ge2", NULL,  2 },
-	{ "ge1", NULL, 3 },
-	{ "ge0", NULL, 4 },
-	{ "pex0", NULL, 5 },
-	{ "pex1", NULL, 6 },
-	{ "pex2", NULL, 7 },
-	{ "pex3", NULL, 8 },
-	{ "bp", NULL, 13 },
-	{ "sata0lnk", NULL, 14 },
-	{ "sata0", "sata0lnk", 15 },
-	{ "lcd", NULL, 16 },
-	{ "sdio", NULL, 17 },
-	{ "usb0", NULL, 18 },
-	{ "usb1", NULL, 19 },
-	{ "usb2", NULL, 20 },
-	{ "xor0", NULL, 22 },
-	{ "crypto", NULL, 23 },
-	{ "tdm", NULL, 25 },
-	{ "xor1", NULL, 28 },
-	{ "sata1lnk", NULL, 29 },
-	{ "sata1", "sata1lnk", 30 },
+	{ "audio", NULL, 0, 0 },
+	{ "ge3", NULL, 1, 0 },
+	{ "ge2", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex0", NULL, 5, 0 },
+	{ "pex1", NULL, 6, 0 },
+	{ "pex2", NULL, 7, 0 },
+	{ "pex3", NULL, 8, 0 },
+	{ "bp", NULL, 13, 0 },
+	{ "sata0lnk", NULL, 14, 0 },
+	{ "sata0", "sata0lnk", 15, 0 },
+	{ "lcd", NULL, 16, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "usb0", NULL, 18, 0 },
+	{ "usb1", NULL, 19, 0 },
+	{ "usb2", NULL, 20, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ "crypto", NULL, 23, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "xor1", NULL, 28, 0 },
+	{ "sata1lnk", NULL, 29, 0 },
+	{ "sata1", "sata1lnk", 30, 0 },
 	{ }
 };
 #endif
 
 #ifdef CONFIG_ARCH_DOVE
 static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
-	{ "usb0", NULL, 0 },
-	{ "usb1", NULL, 1 },
-	{ "ge", "gephy", 2 },
-	{ "sata", NULL, 3 },
-	{ "pex0", NULL, 4 },
-	{ "pex1", NULL, 5 },
-	{ "sdio0", NULL, 8 },
-	{ "sdio1", NULL, 9 },
-	{ "nand", NULL, 10 },
-	{ "camera", NULL, 11 },
-	{ "i2s0", NULL, 12 },
-	{ "i2s1", NULL, 13 },
-	{ "crypto", NULL, 15 },
-	{ "ac97", NULL, 21 },
-	{ "pdma", NULL, 22 },
-	{ "xor0", NULL, 23 },
-	{ "xor1", NULL, 24 },
-	{ "gephy", NULL, 30 },
+	{ "usb0", NULL, 0, 0 },
+	{ "usb1", NULL, 1, 0 },
+	{ "ge", "gephy", 2, 0 },
+	{ "sata", NULL, 3, 0 },
+	{ "pex0", NULL, 4, 0 },
+	{ "pex1", NULL, 5, 0 },
+	{ "sdio0", NULL, 8, 0 },
+	{ "sdio1", NULL, 9, 0 },
+	{ "nand", NULL, 10, 0 },
+	{ "camera", NULL, 11, 0 },
+	{ "i2s0", NULL, 12, 0 },
+	{ "i2s1", NULL, 13, 0 },
+	{ "crypto", NULL, 15, 0 },
+	{ "ac97", NULL, 21, 0 },
+	{ "pdma", NULL, 22, 0 },
+	{ "xor0", NULL, 23, 0 },
+	{ "xor1", NULL, 24, 0 },
+	{ "gephy", NULL, 30, 0 },
 	{ }
 };
 #endif
 
 #ifdef CONFIG_ARCH_KIRKWOOD
 static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
-	{ "ge0", NULL, 0 },
-	{ "pex0", NULL, 2 },
-	{ "usb0", NULL, 3 },
-	{ "sdio", NULL, 4 },
-	{ "tsu", NULL, 5 },
-	{ "runit", NULL, 7 },
-	{ "xor0", NULL, 8 },
-	{ "audio", NULL, 9 },
-	{ "powersave", "cpuclk", 11 },
-	{ "sata0", NULL, 14 },
-	{ "sata1", NULL, 15 },
-	{ "xor1", NULL, 16 },
-	{ "crypto", NULL, 17 },
-	{ "pex1", NULL, 18 },
-	{ "ge1", NULL, 19 },
-	{ "tdm", NULL, 20 },
+	{ "ge0", NULL, 0, 0 },
+	{ "pex0", NULL, 2, 0 },
+	{ "usb0", NULL, 3, 0 },
+	{ "sdio", NULL, 4, 0 },
+	{ "tsu", NULL, 5, 0 },
+	{ "runit", NULL, 7, 0 },
+	{ "xor0", NULL, 8, 0 },
+	{ "audio", NULL, 9, 0 },
+	{ "powersave", "cpuclk", 11, 0 },
+	{ "sata0", NULL, 14, 0 },
+	{ "sata1", NULL, 15, 0 },
+	{ "xor1", NULL, 16, 0 },
+	{ "crypto", NULL, 17, 0 },
+	{ "pex1", NULL, 18, 0 },
+	{ "ge1", NULL, 19, 0 },
+	{ "tdm", NULL, 20, 0 },
 	{ }
 };
 #endif
-- 
1.7.10.4



From holt at sgi.com  Fri May 10 21:58:52 2013
From: holt at sgi.com (Robin Holt)
Date: Fri, 10 May 2013 20:58:52 -0500
Subject: [PATCH -v10 00/11] Shutdown from reboot_cpuid without stopping other
 cpus.
Message-ID: <1368237543-38532-1-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.

Changes since -v9
 - Added Ingo's Acked-by.

Changes since -v8
 - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.

 - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.

 - Fixed case statement bug.

 - Went to using simple_strtoul for parsing reboot_cpu=smp###.

 - Made parsing of reboot= not use any #ifdef'd code.

Changes since -v7.
 - Fixed authorship for first patch.

 - Rebased to Linus' current tree (51a26ae7a).

Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From tony at atomide.com  Fri May 10 22:35:58 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 10 May 2013 19:35:58 -0700
Subject: [PATCH] ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
Message-ID: <20130511023557.GB28602@atomide.com>

Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to
OMAP3+ boards) added support for MUSB on omap3 for device tree,
but added the interrupts the wrong way probably as they were
copied from the omap4.dtsi file. On omap3 we have TI specific
interrupt controller, not GIC.

Fix this by specifying the interrupt following the TI INTC
binding.

Without this fix MUSB won't work as it is trying to use
irq0 instead of irq92.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -516,7 +516,7 @@
 		usb_otg_hs: usb_otg_hs at 480ab000 {
 			compatible = "ti,omap3-musb";
 			reg = <0x480ab000 0x1000>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <92>, <93>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			multipoint = <1>;


From tony at atomide.com  Fri May 10 22:55:59 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 10 May 2013 19:55:59 -0700
Subject: [PATCH] ARM: dts: Fix musb interrupt for device tree booting
In-Reply-To: <20130511023557.GB28602@atomide.com>
References: <20130511023557.GB28602@atomide.com>
Message-ID: <20130511025558.GC28602@atomide.com>

Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to
OMAP3+ boards) added support for MUSB on omap3 for device tree,
but added the interrupts the wrong way probably as they were
copied from the omap4.dtsi file. On omap3 we have TI specific
interrupt controller, not GIC.

Fix this by specifying the interrupt following the TI INTC
binding.

Without this fix MUSB won't work as it is trying to use
irq0 instead of irq92.

Signed-off-by: Tony Lindgren <tony at atomide.com>

---
Sorry had the wrong subject in the previous mail. That was
for the breaking commit. Here's the patch again with correct
subject.

--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -516,7 +516,7 @@
 		usb_otg_hs: usb_otg_hs at 480ab000 {
 			compatible = "ti,omap3-musb";
 			reg = <0x480ab000 0x1000>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <92>, <93>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			multipoint = <1>;


From holt at sgi.com  Sat May 11 00:16:10 2013
From: holt at sgi.com (Robin Holt)
Date: Fri, 10 May 2013 23:16:10 -0500
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <20130510100324.e1e066ab.akpm@linux-foundation.org>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-2-git-send-email-holt@sgi.com>
 <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>
 <1651579.orCh9JNVz6@vostro.rjw.lan>
 <20130510100324.e1e066ab.akpm@linux-foundation.org>
Message-ID: <20130511041610.GZ3672@sgi.com>

On Fri, May 10, 2013 at 10:03:24AM -0700, Andrew Morton wrote:
> On Fri, 10 May 2013 13:11:51 +0200 "Rafael J. Wysocki" <rjw at sisk.pl> wrote:
> 
> > ...
> >
> > > cpu_hotplug_disable() doesn't get compiled unless we've defined
> > > CONFIG_PM_SLEEP_SMP.  I cannot begin to imagine what the logic is
> > > behind that!
> > 
> > I suppose it was only used by suspend/hibernate code paths when this was
> > introduced.
> 
> OK, well I suspect that what I have now is simply wrong for Robin's
> application.  Robin, can you please check this?  We probably want to
> make the does-something version of cpu_hotplug_disable/enable available
> if CONFIG_HOTPLUG_CPU.

This patch came from "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>,
I think I need to defer.

I spent all day trying to get an alpha cross compiler to build an
unmodified kernel and modules, only to find I didn't need to go that
far and could reproduce the failure with just building vmlinux.

Sorry for my slow response,
Robin


From swarren at nvidia.com  Sat May 11 00:28:22 2013
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 10 May 2013 22:28:22 -0600
Subject: [PATCH] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1368078942-31265-1-git-send-email-csd@broadcom.com>
References: <1368078942-31265-1-git-send-email-csd@broadcom.com>
Message-ID: <518DC8E6.5000606@nvidia.com>

On 05/08/2013 11:55 PM, Christian Daudt wrote:
> Add SDHCI driver for the Broadcom 281xx SoCs. Also
> add bindings for it into bcm281xx dts files.
> Still missing:
>  - power managemement

> diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c

> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	udelay(1000);
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);

This sounds very similar to the workaround in
drivers/mmc/host/sdhci-bcm2835.c. Is this the same IP block supported by
that driver? Perhaps not, since bcm2835 apparently needs other WARs such
as always using 32-bit IO and hence needing custom read/write w/b
functions to do read-modify-write which isn't here?


From jg1.han at samsung.com  Sat May 11 01:07:29 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 14:07:29 +0900
Subject: [PATCH] ARM: exynos: dts: Fixed vbus-gpios
In-Reply-To: <1368034636-15865-1-git-send-email-dianders@chromium.org>
References: <1368034636-15865-1-git-send-email-dianders@chromium.org>
Message-ID: <002501ce4e05$6fe4c630$4fae5290$@samsung.com>

On Thursday, May 09, 2013 2:37 AM, Doug Anderson wrote:
> 
> The 'samsung,vbus-gpio' was submitted before pinmux landed for
> exynos5250 and uses the old-style gpio specifier.  Fix the two
> exynos5250 boards that use it.
> 
> Signed-off-by: Doug Anderson <dianders at chromium.org>

Acked-by: Jingoo Han <jg1.han at samsung.com>

Best regards,
Jingoo Han

> ---
>  arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +-
>  arch/arm/boot/dts/exynos5250-snow.dts     | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 26d856b..3e0c792 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -214,7 +214,7 @@
>  	};
> 
>  	usb at 12110000 {
> -		samsung,vbus-gpio = <&gpx2 6 1 3 3>;
> +		samsung,vbus-gpio = <&gpx2 6 0>;
>  	};
> 
>  	dp-controller {
> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
> index bf4744b..d449feb 100644
> --- a/arch/arm/boot/dts/exynos5250-snow.dts
> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
> @@ -183,7 +183,7 @@
>  	};
> 
>  	usb at 12110000 {
> -		samsung,vbus-gpio = <&gpx1 1 1 3 3>;
> +		samsung,vbus-gpio = <&gpx1 1 0>;
>  	};
> 
>  	fixed-rate-clocks {
> --
> 1.8.2.1



From jg1.han at samsung.com  Sat May 11 01:15:05 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 14:15:05 +0900
Subject: [RFC 39/42] arch/arm/plat-samsung: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-40-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-40-git-send-email-wsa@the-dreams.de>
Message-ID: <002601ce4e06$7f68fbc0$7e3af340$@samsung.com>

On Friday, May 10, 2013 5:17 PM, Wolfram Sang wrote:
> 
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
> 
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>

Reviewed-by: Jingoo Han <jg1.han at samsung.com>

Best regards,
Jingoo Han

> ---
>  arch/arm/plat-samsung/adc.c |    5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> index ca07cb1..79690f2 100644
> --- a/arch/arm/plat-samsung/adc.c
> +++ b/arch/arm/plat-samsung/adc.c
> @@ -381,11 +381,6 @@ static int s3c_adc_probe(struct platform_device *pdev)
>  	}
> 
>  	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!regs) {
> -		dev_err(dev, "failed to find registers\n");
> -		return -ENXIO;
> -	}
> -
>  	adc->regs = devm_ioremap_resource(dev, regs);
>  	if (IS_ERR(adc->regs))
>  		return PTR_ERR(adc->regs);
> --
> 1.7.10.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From jg1.han at samsung.com  Sat May 11 01:18:50 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 14:18:50 +0900
Subject: [RFC 09/42] drivers/i2c/busses: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-10-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-10-git-send-email-wsa@the-dreams.de>
Message-ID: <002a01ce4e07$05839490$108abdb0$@samsung.com>

On Friday, May 10, 2013 5:17 PM, Wolfram Sang wrote:
> 
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
> 
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
> ---
>  drivers/i2c/busses/i2c-davinci.c            |    6 +-----
>  drivers/i2c/busses/i2c-designware-platdrv.c |    6 +-----
>  drivers/i2c/busses/i2c-imx.c                |    6 +-----
>  drivers/i2c/busses/i2c-omap.c               |    6 +-----
>  drivers/i2c/busses/i2c-rcar.c               |    7 +------
>  drivers/i2c/busses/i2c-s3c2410.c            |    5 -----

For drivers/i2c/busses/i2c-s3c2410.c

Reviewed-by: Jingoo Han <jg1.han at samsung.com>

Best regards,
Jingoo Han


>  drivers/i2c/busses/i2c-sirf.c               |    6 ------
>  drivers/i2c/busses/i2c-tegra.c              |    5 -----
>  8 files changed, 5 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
> index cf20e06..2ed3e7b 100644
> --- a/drivers/i2c/busses/i2c-davinci.c
> +++ b/drivers/i2c/busses/i2c-davinci.c
> @@ -647,11 +647,6 @@ static int davinci_i2c_probe(struct platform_device *pdev)
>  	int r;
> 
>  	/* NOTE: driver uses the static register mapping */
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!mem) {
> -		dev_err(&pdev->dev, "no mem resource?\n");
> -		return -ENODEV;
> -	}
> 
>  	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
>  	if (!irq) {
> @@ -697,6 +692,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	clk_prepare_enable(dev->clk);
> 
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dev->base = devm_ioremap_resource(&pdev->dev, mem);
>  	if (IS_ERR(dev->base)) {
>  		r = PTR_ERR(dev->base);
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
> index 8ec9133..6f3c612 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -87,11 +87,6 @@ static int dw_i2c_probe(struct platform_device *pdev)
>  	int irq, r;
> 
>  	/* NOTE: driver uses the static register mapping */
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!mem) {
> -		dev_err(&pdev->dev, "no mem resource?\n");
> -		return -EINVAL;
> -	}
> 
>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0) {
> @@ -103,6 +98,7 @@ static int dw_i2c_probe(struct platform_device *pdev)
>  	if (!dev)
>  		return -ENOMEM;
> 
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dev->base = devm_ioremap_resource(&pdev->dev, mem);
>  	if (IS_ERR(dev->base))
>  		return PTR_ERR(dev->base);
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
> index 82f20c6..b274ca1 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -500,17 +500,13 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
> 
>  	dev_dbg(&pdev->dev, "<%s>\n", __func__);
> 
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(&pdev->dev, "can't get device resources\n");
> -		return -ENOENT;
> -	}
>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0) {
>  		dev_err(&pdev->dev, "can't get irq number\n");
>  		return -ENOENT;
>  	}
> 
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	base = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(base))
>  		return PTR_ERR(base);
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index e02f9e3..8498ab7 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -1085,11 +1085,6 @@ omap_i2c_probe(struct platform_device *pdev)
>  	u16 minor, major, scheme;
> 
>  	/* NOTE: driver uses the static register mapping */
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!mem) {
> -		dev_err(&pdev->dev, "no mem resource?\n");
> -		return -ENODEV;
> -	}
> 
>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0) {
> @@ -1103,6 +1098,7 @@ omap_i2c_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  	}
> 
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dev->base = devm_ioremap_resource(&pdev->dev, mem);
>  	if (IS_ERR(dev->base))
>  		return PTR_ERR(dev->base);
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index 4ba4a95..0fc5858 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -623,12 +623,6 @@ static int rcar_i2c_probe(struct platform_device *pdev)
>  	u32 bus_speed;
>  	int ret;
> 
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(dev, "no mmio resources\n");
> -		return -ENODEV;
> -	}
> -
>  	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
>  	if (!priv) {
>  		dev_err(dev, "no mem for private data\n");
> @@ -642,6 +636,7 @@ static int rcar_i2c_probe(struct platform_device *pdev)
>  	if (ret < 0)
>  		return ret;
> 
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	priv->io = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(priv->io))
>  		return PTR_ERR(priv->io);
> diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
> index 6e8ee92..cab1c91 100644
> --- a/drivers/i2c/busses/i2c-s3c2410.c
> +++ b/drivers/i2c/busses/i2c-s3c2410.c
> @@ -1082,11 +1082,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
>  	/* map the registers */
> 
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (res == NULL) {
> -		dev_err(&pdev->dev, "cannot find IO resource\n");
> -		return -ENOENT;
> -	}
> -
>  	i2c->regs = devm_ioremap_resource(&pdev->dev, res);
> 
>  	if (IS_ERR(i2c->regs))
> diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c
> index 5a7ad24..a63c7d5 100644
> --- a/drivers/i2c/busses/i2c-sirf.c
> +++ b/drivers/i2c/busses/i2c-sirf.c
> @@ -303,12 +303,6 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
>  	adap->class = I2C_CLASS_HWMON;
> 
>  	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (mem_res == NULL) {
> -		dev_err(&pdev->dev, "Unable to get MEM resource\n");
> -		err = -EINVAL;
> -		goto out;
> -	}
> -
>  	siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
>  	if (IS_ERR(siic->base)) {
>  		err = PTR_ERR(siic->base);
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index b60ff90..9aa1b60 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -714,11 +714,6 @@ static int tegra_i2c_probe(struct platform_device *pdev)
>  	int ret = 0;
> 
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(&pdev->dev, "no mem resource\n");
> -		return -EINVAL;
> -	}
> -
>  	base = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(base))
>  		return PTR_ERR(base);
> --
> 1.7.10.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From jg1.han at samsung.com  Sat May 11 01:24:35 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 14:24:35 +0900
Subject: [RFC 23/42] drivers/spi: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-24-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-24-git-send-email-wsa@the-dreams.de>
Message-ID: <002b01ce4e07$d3087ed0$79197c70$@samsung.com>

On Friday, May 10, 2013 5:17 PM, Wolfram Sang wrote:
> 
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
> 
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
> ---
>  drivers/spi/spi-bcm63xx.c        |    8 +-------
>  drivers/spi/spi-ep93xx.c         |    8 +-------
>  drivers/spi/spi-omap2-mcspi.c    |    7 +------
>  drivers/spi/spi-s3c64xx.c        |    7 +------
>  drivers/spi/spi-sirf.c           |    7 +------
>  drivers/spi/spi-tegra114.c       |    7 +------
>  drivers/spi/spi-tegra20-sflash.c |    5 -----
>  drivers/spi/spi-tegra20-slink.c  |    7 +------
>  8 files changed, 7 insertions(+), 49 deletions(-)
> 

[.....]

> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 5000586..fd763cc 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -1243,12 +1243,6 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
> 
> -	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (mem_res == NULL) {
> -		dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
> -		return -ENXIO;
> -	}
> -

It breaks 'sdd->sfr_start' assignment as below:

1272         sdd->sfr_start = mem_res->start;


Best regards,
Jingoo Han

>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0) {
>  		dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
> @@ -1318,6 +1312,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
>  	/* the spi->mode bits understood by this driver: */
>  	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
> 
> +	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
>  	if (IS_ERR(sdd->regs)) {
>  		ret = PTR_ERR(sdd->regs);




From gmbnomis at gmail.com  Sat May 11 02:27:19 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Sat, 11 May 2013 08:27:19 +0200
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
References: <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
Message-ID: <20130511062719.GA10643@schnuecks.de>

On Sat, May 04, 2013 at 04:21:27PM +0800, Ming Lei wrote:
> On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
> >>
> >> I assume that you inhibited the call to flush_dcache_page() in
> >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
> >> with warnings.
> >
> > I haven't done any stress testing so I don't think I hit this code path,
> > so no warning. But yes, it should have triggered. Anyway, in this case
> > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
> > harmless anyway if we also ignore this bit in __sync_icache_dcache for
> > non-aliasing caches).
> 
> Yes, maybe we can do a little optimization for O_DIRECT since no
> dcache alias and I/D coherency problem in this case on ARMv7, how
> about below change?
> 
> diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> index 1c8f7f5..962a657 100644
> --- a/arch/arm/mm/flush.c
> +++ b/arch/arm/mm/flush.c
> @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
>  	    mapping && !mapping_mapped(mapping))
>  		clear_bit(PG_dcache_clean, &page->flags);
>  	else {
> +		if (!mapping && cache_is_vipt_nonaliasing())
> +			return;
>  		__flush_dcache_page(mapping, page);
>  		if (mapping && cache_is_vivt())
>  			__flush_dcache_aliases(mapping, page);
> 

Yes, this should not be needed. However, I seem to get funny pixel
errors on an Exynos 5 based Chromebook when not flushing in this
case.  Strange.  This is not on a mainline kernel, I will need to
have a look what happens here.


- Simon


From chenlibo.3 at gmail.com  Sat May 11 02:28:15 2013
From: chenlibo.3 at gmail.com (Libo Chen)
Date: Sat, 11 May 2013 14:28:15 +0800
Subject: [PATCH] usb: gadget: s3c2410: fix clk resource leak and update
Message-ID: <518DE4FF.1000702@gmail.com>

From: Libo Chen <libo.chen at huawei.com>

currently, when clk_get(NULL,"usb-device") fail, it does not
disable && put usb_bus_clock. It is incorrect.

this patch use new interface devm_xxx instead of xxx then
we no need to care about cleanup resource in err case that is boring
and reduce code size.

Signed-off-by: Libo Chen <libo.chen at huawei.com>
---
 drivers/usb/gadget/s3c2410_udc.c | 85
++++++++++++----------------------------
 1 file changed, 25 insertions(+), 60 deletions(-)

diff --git a/drivers/usb/gadget/s3c2410_udc.c
b/drivers/usb/gadget/s3c2410_udc.c
old mode 100644
new mode 100755
index d0e75e1..0c573a8
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -1780,7 +1780,7 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)

 	dev_dbg(dev, "%s()\n", __func__);

-	usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
+	usb_bus_clock = devm_clk_get(NULL, "usb-bus-gadget");
 	if (IS_ERR(usb_bus_clock)) {
 		dev_err(dev, "failed to get usb bus clock source\n");
 		return PTR_ERR(usb_bus_clock);
@@ -1788,8 +1788,9 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)

 	clk_enable(usb_bus_clock);

-	udc_clock = clk_get(NULL, "usb-device");
+	udc_clock = devm_clk_get(NULL, "usb-device");
 	if (IS_ERR(udc_clock)) {
+		clk_disable(usb_bus_clock);
 		dev_err(dev, "failed to get udc clock source\n");
 		return PTR_ERR(udc_clock);
 	}
@@ -1814,13 +1815,15 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)
 	rsrc_start = S3C2410_PA_USBDEV;
 	rsrc_len   = S3C24XX_SZ_USBDEV;

-	if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
-		return -EBUSY;
+	if (!devm_request_mem_region(rsrc_start, rsrc_len, gadget_name)) {
+		retval = -EBUSY;
+		goto out;
+	}

-	base_addr = ioremap(rsrc_start, rsrc_len);
+	base_addr = devm_ioremap(rsrc_start, rsrc_len);
 	if (!base_addr) {
 		retval = -ENOMEM;
-		goto err_mem;
+		goto out;
 	}

 	the_controller = udc;
@@ -1830,31 +1833,31 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)
 	s3c2410_udc_reinit(udc);

 	/* irq setup after old hardware state is cleaned up */
-	retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
+	retval = devm_request_irq(IRQ_USBD, s3c2410_udc_irq,
 			     0, gadget_name, udc);

 	if (retval != 0) {
 		dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
 		retval = -EBUSY;
-		goto err_map;
+		goto out;
 	}

 	dev_dbg(dev, "got irq %i\n", IRQ_USBD);

 	if (udc_info && udc_info->vbus_pin > 0) {
-		retval = gpio_request(udc_info->vbus_pin, "udc vbus");
+		retval = devm_gpio_request(udc_info->vbus_pin, "udc vbus");
 		if (retval < 0) {
 			dev_err(dev, "cannot claim vbus pin\n");
-			goto err_int;
+			goto out;
 		}

 		irq = gpio_to_irq(udc_info->vbus_pin);
 		if (irq < 0) {
 			dev_err(dev, "no irq for gpio vbus pin\n");
-			goto err_gpio_claim;
+			goto out;
 		}

-		retval = request_irq(irq, s3c2410_udc_vbus_irq,
+		retval = devm_request_irq(irq, s3c2410_udc_vbus_irq,
 				     IRQF_TRIGGER_RISING
 				     | IRQF_TRIGGER_FALLING | IRQF_SHARED,
 				     gadget_name, udc);
@@ -1863,7 +1866,7 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)
 			dev_err(dev, "can't get vbus irq %d, err %d\n",
 				irq, retval);
 			retval = -EBUSY;
-			goto err_gpio_claim;
+			goto out;
 		}

 		dev_dbg(dev, "got irq %i\n", irq);
@@ -1874,17 +1877,17 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)
 	if (udc_info && !udc_info->udc_command &&
 		gpio_is_valid(udc_info->pullup_pin)) {

-		retval = gpio_request_one(udc_info->pullup_pin,
+		retval = devm_gpio_request_one(udc_info->pullup_pin,
 				udc_info->vbus_pin_inverted ?
 				GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
 				"udc pullup");
 		if (retval)
-			goto err_vbus_irq;
+			goto out;
 	}

 	retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
 	if (retval)
-		goto err_add_udc;
+		goto out;

 	if (s3c2410_udc_debugfs_root) {
 		udc->regs_info = debugfs_create_file("registers", S_IRUGO,
@@ -1898,22 +1901,9 @@ static int s3c2410_udc_probe(struct
platform_device *pdev)

 	return 0;

-err_add_udc:
-	if (udc_info && !udc_info->udc_command &&
-			gpio_is_valid(udc_info->pullup_pin))
-		gpio_free(udc_info->pullup_pin);
-err_vbus_irq:
-	if (udc_info && udc_info->vbus_pin > 0)
-		free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
-err_gpio_claim:
-	if (udc_info && udc_info->vbus_pin > 0)
-		gpio_free(udc_info->vbus_pin);
-err_int:
-	free_irq(IRQ_USBD, udc);
-err_map:
-	iounmap(base_addr);
-err_mem:
-	release_mem_region(rsrc_start, rsrc_len);
+out:
+	clk_disable(udc_clock);
+	clk_disable(usb_bus_clock);

 	return retval;
 }
@@ -1931,36 +1921,11 @@ static int s3c2410_udc_remove(struct
platform_device *pdev)
 	if (udc->driver)
 		return -EBUSY;

-	usb_del_gadget_udc(&udc->gadget);
 	debugfs_remove(udc->regs_info);
+	usb_del_gadget_udc(&udc->gadget);

-	if (udc_info && !udc_info->udc_command &&
-		gpio_is_valid(udc_info->pullup_pin))
-		gpio_free(udc_info->pullup_pin);
-
-	if (udc_info && udc_info->vbus_pin > 0) {
-		irq = gpio_to_irq(udc_info->vbus_pin);
-		free_irq(irq, udc);
-	}
-
-	free_irq(IRQ_USBD, udc);
-
-	iounmap(base_addr);
-	release_mem_region(rsrc_start, rsrc_len);
-
-	platform_set_drvdata(pdev, NULL);
-
-	if (!IS_ERR(udc_clock) && udc_clock != NULL) {
-		clk_disable(udc_clock);
-		clk_put(udc_clock);
-		udc_clock = NULL;
-	}
-
-	if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
-		clk_disable(usb_bus_clock);
-		clk_put(usb_bus_clock);
-		usb_bus_clock = NULL;
-	}
+	clk_disable(udc_clock);
+	clk_disable(usb_bus_clock);

 	dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
 	return 0;
-- 
1.8.1.2



From jg1.han at samsung.com  Sat May 11 03:42:52 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 16:42:52 +0900
Subject: [PATCH 1/2] ARM: dts: add DP clock reference to exynos5250 device tree
Message-ID: <003001ce4e1b$24a28fc0$6de7af40$@samsung.com>

The transition to common clock happened; however, DP (Display Port)
clock node was not added. Thus, DP (Display Port) clock node should
be added to the device tree.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
Tested on Exynos5250

 arch/arm/boot/dts/exynos5250.dtsi |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9dfc6de..8b1f9b6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -651,6 +651,8 @@
 		reg = <0x145b0000 0x1000>;
 		interrupts = <10 3>;
 		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-- 
1.7.2.5




From jg1.han at samsung.com  Sat May 11 03:43:56 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 16:43:56 +0900
Subject: [PATCH 2/2] ARM: dts: Document DP clock in samsung, exynos5-dp binding
Message-ID: <003101ce4e1b$4acc0050$e06400f0$@samsung.com>

The exynos5-dp node needs a clock specified using the common clock
framework.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
Tested on Exynos5250

 .../devicetree/bindings/video/exynos_dp.txt        |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index c60da67..84f10c1 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -21,6 +21,10 @@ Required properties for dp-controller:
 		of memory mapped region.
 	-interrupts:
 		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
 	-interrupt-parent:
 		phandle to Interrupt combiner node.
 	-samsung,color-space:
@@ -61,6 +65,8 @@ SOC specific portion:
 		reg = <0x145b0000 0x10000>;
 		interrupts = <10 3>;
 		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
 
 		dptx-phy {
 			reg = <0x10040720>;
-- 
1.7.2.5




From peter.maydell at linaro.org  Sat May 11 03:51:42 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Sat, 11 May 2013 08:51:42 +0100
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <20130511003630.GD30999@chazy>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
 <20130502160906.GI20730@arm.com>
 <51892B90.8060706@arm.com> <20130507163303.GH29757@arm.com>
 <20130511003630.GD30999@chazy>
Message-ID: <CAFEAcA8fwdUbLPNH0Y_3VY4MztocBL7uqxf8TZDX=Q8Pvej5bg@mail.gmail.com>

On 11 May 2013 01:36, Christoffer Dall <cdall at cs.columbia.edu> wrote:
> That all being said, we can remove the check.  I don't think, however,
> that it being an unlikely thing is a good argument: if we remove the
> check we need to make sure that the VM does whatever the architecture
> dictates, which I assume is to not skip the MMIO instruction and support
> setting the PC to the value returned from an I/O emulation device in
> QEMU.
>
> I think the scenario sounds crazy and is more than anything a sign of a
> bug somewhere, and whether it should be a PABT or a DABT is a judgement
> call, but I chose a PABT because the thing that's weird is jumping to an
> I/O address, it's not that the memory address for the load is
> problematic.

I'm confused -- in your first paragraph you talk about loading
PC from an MMIO region but in the second you talk about jumping
to an MMIO region. This check is catching the former, right?

Loading PC from a device isn't totally unheard of: the VIC (common
on ARM7) has a register which returns "address of the next interrupt
to take", with the intention that the IRQ vector can just have a
single instruction directly loading PC from the VIC register:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/I1006455.html

Handling "executing code out of an MMIO region" is (a) rather
harder and (b) not necessary IMHO. QEMU's TCG emulation doesn't
support it and we haven't had huge "can't run this guest"
issues as a result.

thanks
-- PMM


From peter.maydell at linaro.org  Sat May 11 04:04:52 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Sat, 11 May 2013 09:04:52 +0100
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <20130511003842.GE30999@chazy>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com> <5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
 <51892DA4.4050401@arm.com> <20130511003842.GE30999@chazy>
Message-ID: <CAFEAcA-8cHk9Gv5j8XvK9dfkpZJeZ+hNfc4NekKCW_KBeHttKg@mail.gmail.com>

On 11 May 2013 01:38, Christoffer Dall <cdall at cs.columbia.edu> wrote:
> On Tue, May 07, 2013 at 05:36:52PM +0100, Marc Zyngier wrote:
>> Here's what the documentation says:
>> <quote>
>> 4.77 KVM_ARM_VCPU_INIT
>>
>> Capability: basic
>> Architectures: arm, arm64
>> Type: vcpu ioctl
>> Parameters: struct struct kvm_vcpu_init (in)
>> Returns: 0 on success; -1 on error
>> Errors:
>>   EINVAL:    the target is unknown, or the combination of features is invalid.
>>   ENOENT:    a features bit specified is unknown.
>> </quote>
>>
>> When this call fails, it is because you've requested a feature
>> that is invalid for this CPU. To me, that exactly fits the
>> EINVAL entry copied above.
>>
>> Or am I completely misunderstanding it?
>>
> I read the EINVAL to say that you supplied something which is invalid
> for the software interface and you should fix your user space code.

Well, more likely "tell the user they picked a bad feature combo";
I doubt userspace is going to bother specifically trying to track
which features don't go together when we can get a reliable answer
just by asking the kernel.

> The fact that you're requesting a feature that your hardware doesn't
> support is a different thing IMHO.

My reading of the docs above would be that "ENOENT" is "I have
no idea what feature you just asked me for" and "EINVAL" is
"I know those features but can't do them". That said, we don't
actually do anything with the error return yet so we should
feel free to clarify things so that it's clear what error is
returned for the cases we care about distinguishing. It seems
like it would be useful to have separate errors for:
 * the kernel doesn't support this CPU
 * the kernel doesn't support this feature bit
 * the combination of CPU and features doesn't make sense

and at the moment we've shoehorned two of those into one
errno, hence the confusion.

(do we need to distinguish "I know about but don't support X"
from "I have no idea what you mean when you say X" ?)

thanks
-- PMM


From jg1.han at samsung.com  Sat May 11 04:09:11 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Sat, 11 May 2013 17:09:11 +0900
Subject: [PATCH] ARM: dts: add pin state information for DP HPD support to
 Exynos5250
Message-ID: <000001ce4e1e$d1cc5de0$756519a0$@samsung.com>

Add pin state information for DP HPD support that requires
pin configuration support using pinctrl interface.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
Tested on Exynos5250

 arch/arm/boot/dts/exynos5250-pinctrl.dtsi |    7 +++++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts |    3 +++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb..e9cdee3 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -553,6 +553,13 @@
 			samsung,pin-pud = <0>;
 			samaung,pin-drv = <0>;
 		};
+
+		dp_hpd: dp_hpd {
+			samsung,pins = "gpx0-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samaung,pin-drv = <0>;
+		};
 	};
 
 	pinctrl at 13400000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792..d53ea34 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -224,6 +224,9 @@
 		samsung,color-depth = <1>;
 		samsung,link-rate = <0x0a>;
 		samsung,lane-count = <4>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&dp_hpd>;
 	};
 
 	display-timings {
-- 
1.7.2.5




From srivatsa.bhat at linux.vnet.ibm.com  Sat May 11 05:13:20 2013
From: srivatsa.bhat at linux.vnet.ibm.com (Srivatsa S. Bhat)
Date: Sat, 11 May 2013 14:43:20 +0530
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <20130511041610.GZ3672@sgi.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-2-git-send-email-holt@sgi.com>
 <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>
 <1651579.orCh9JNVz6@vostro.rjw.lan>
 <20130510100324.e1e066ab.akpm@linux-foundation.org>
 <20130511041610.GZ3672@sgi.com>
Message-ID: <518E0BB0.2000401@linux.vnet.ibm.com>

On 05/11/2013 09:46 AM, Robin Holt wrote:
> On Fri, May 10, 2013 at 10:03:24AM -0700, Andrew Morton wrote:
>> On Fri, 10 May 2013 13:11:51 +0200 "Rafael J. Wysocki" <rjw at sisk.pl> wrote:
>>
>>> ...
>>>
>>>> cpu_hotplug_disable() doesn't get compiled unless we've defined
>>>> CONFIG_PM_SLEEP_SMP.  I cannot begin to imagine what the logic is
>>>> behind that!
>>>
>>> I suppose it was only used by suspend/hibernate code paths when this was
>>> introduced.
>>
>> OK, well I suspect that what I have now is simply wrong for Robin's
>> application.  Robin, can you please check this?  We probably want to
>> make the does-something version of cpu_hotplug_disable/enable available
>> if CONFIG_HOTPLUG_CPU.
> 
> This patch came from "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>,
> I think I need to defer.

Here is a revised patch, which should address all the problems, IMHO.
Let me know if you face any issues. (And thanks a lot for fixing up the
!SMP case in the previous version.)

--------------------------------------------------------------------->

From: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Subject: [PATCH] CPU hotplug: Provide a generic helper to disable/enable CPU hotplug

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
---

 include/linux/cpu.h |    4 ++++
 kernel/cpu.c        |   55 +++++++++++++++++++++------------------------------
 2 files changed, 27 insertions(+), 32 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..9f3c7e8 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
 
 extern void get_online_cpus(void);
 extern void put_online_cpus(void);
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
@@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
 
 #define get_online_cpus()	do { } while (0)
 #define put_online_cpus()	do { } while (0)
+#define cpu_hotplug_disable()	do { } while (0)
+#define cpu_hotplug_enable()	do { } while (0)
 #define hotcpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 /* These aren't inline functions due to a GCC bug. */
 #define register_hotcpu_notifier(nb)	({ (void)(nb); 0; })
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..198a388 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
 	mutex_unlock(&cpu_hotplug.lock);
 }
 
+/*
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
+ */
+void cpu_hotplug_disable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 1;
+	cpu_maps_update_done();
+}
+
+void cpu_hotplug_enable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 0;
+	cpu_maps_update_done();
+}
+
 #else /* #if CONFIG_HOTPLUG_CPU */
 static void cpu_hotplug_begin(void) {}
 static void cpu_hotplug_done(void) {}
@@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
- */
-void cpu_hotplug_disable_before_freeze(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 1;
-	cpu_maps_update_done();
-}
-
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 0;
-	cpu_maps_update_done();
-}
-
-/*
  * When callbacks for CPU hotplug notifications are being executed, we must
  * ensure that the state of the system with respect to the tasks being frozen
  * or not, as reported by the notification, remains unchanged *throughout the
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:




From catalin.marinas at arm.com  Sat May 11 05:43:37 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Sat, 11 May 2013 10:43:37 +0100
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <20130511003630.GD30999@chazy>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
 <20130502160906.GI20730@arm.com> <51892B90.8060706@arm.com>
 <20130507163303.GH29757@arm.com> <20130511003630.GD30999@chazy>
Message-ID: <20130511094336.GA56525@MacBook-Pro.local>

On Sat, May 11, 2013 at 01:36:30AM +0100, Christoffer Dall wrote:
> On Tue, May 07, 2013 at 05:33:03PM +0100, Catalin Marinas wrote:
> > On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote:
> > > On 02/05/13 17:09, Catalin Marinas wrote:
> > > > BTW, on arch/arm it looks like this is used when you get a data abort
> > > > with PC as the destination register and you inject a prefetch abort in
> > > > this case. Why isn't this a normal data abort? Once you get the
> > > > information, you load it into PC but first you need to sort out the data
> > > > abort (unless I don't understand how the kvm_inject_pabt works).
> > > 
> > > Indeed, it should be a data abort, as we correctly fetched the
> > > instruction. Now, I wonder why we even bother trying to catch this case.
> > > Fetching PC from MMIO looks quite silly, but I don't think anything
> > > really forbids it in the architecture.
> > 
> > It's not forbidden and you should just treat it as any other data abort,
> > no need to check whether the register is PC. If you do the PC adjustment
> > further down in that function it will be overridden by the instruction
> > emulation anyway. There is no optimisation in checking for PC since such
> > fault is very unlikely in sane code anyway.
> > 
> The reason is simply that it is most likely because of a bug that this
> happens, and we would rather catch such an error in a meaningful way
> than let this go crazy and have users track it down for a long time.

It is probably a bug but it is a valid code sequence (and Peter even
gave an example).

> Especially, this was relevant when we did io instruction decoding and we
> wanted to catch potential bugs in that when it was development code.
> 
> That all being said, we can remove the check.  I don't think, however,
> that it being an unlikely thing is a good argument: if we remove the
> check we need to make sure that the VM does whatever the architecture
> dictates, which I assume is to not skip the MMIO instruction and support
> setting the PC to the value returned from an I/O emulation device in
> QEMU.
> 
> I think the scenario sounds crazy and is more than anything a sign of a
> bug somewhere, and whether it should be a PABT or a DABT is a judgement
> call, but I chose a PABT because the thing that's weird is jumping to an
> I/O address, it's not that the memory address for the load is
> problematic.

I think that's where things get confused. You are reading from an I/O
location with the destination being the PC and it is trapped by KVM.
This has nothing to do with PABT, it's purely a DABT on the I/O access.
You should emulate it and store the result in the PC. If the value
loaded in PC is wrong, you will get a subsequent PABT in the guest but
you must not translate the DABT on I/O memory (which would be generated
even if the destination is not PC) into a PABT which confuses the guest
further. By doing this you try to convince the guest that it really
branched to the I/O address (since you raise the PABT with the DFAR
value) when it simply tried to load an address from I/O and branch to
this new address.

IOW, these two are equivalent regarding PC:

	ldr	pc, [r0]	@ r0 is an I/O address

and 

	ldr	r1, [r0]	@ r0 is an I/O address
	mov	pc, r1

In the second scenario, you don't raise a PABT on the first instruction.
You may raise one on the second if PC is invalid but that's different
and most likely it will be a guest-only thing.

So for DABT emulation, checking whether the destination register is PC
is simply a minimal optimisation (if at all) of that case to avoid
storing the PC twice. Injecting PABT when you get a DABT is a bug. You
already catch PABT on I/O address in kvm_handle_guest_abort() and
correctly inject PABT into guest.

-- 
Catalin


From holt at sgi.com  Sat May 11 05:49:03 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 04:49:03 -0500
Subject: [PATCH -v8 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <518E0BB0.2000401@linux.vnet.ibm.com>
References: <1367937595-32241-1-git-send-email-holt@sgi.com>
 <1367937595-32241-2-git-send-email-holt@sgi.com>
 <20130509150121.8c3ef60b2fc748ce542a1a52@linux-foundation.org>
 <1651579.orCh9JNVz6@vostro.rjw.lan>
 <20130510100324.e1e066ab.akpm@linux-foundation.org>
 <20130511041610.GZ3672@sgi.com>
 <518E0BB0.2000401@linux.vnet.ibm.com>
Message-ID: <20130511094903.GC3658@sgi.com>

Thank you.  That fixed the alpha allmodconfig case for me.  I am currently
rebuilding all the arm defconfig files and will resubmit -v10 when that
is done.

Robin

On Sat, May 11, 2013 at 02:43:20PM +0530, Srivatsa S. Bhat wrote:
> On 05/11/2013 09:46 AM, Robin Holt wrote:
> > On Fri, May 10, 2013 at 10:03:24AM -0700, Andrew Morton wrote:
> >> On Fri, 10 May 2013 13:11:51 +0200 "Rafael J. Wysocki" <rjw at sisk.pl> wrote:
> >>
> >>> ...
> >>>
> >>>> cpu_hotplug_disable() doesn't get compiled unless we've defined
> >>>> CONFIG_PM_SLEEP_SMP.  I cannot begin to imagine what the logic is
> >>>> behind that!
> >>>
> >>> I suppose it was only used by suspend/hibernate code paths when this was
> >>> introduced.
> >>
> >> OK, well I suspect that what I have now is simply wrong for Robin's
> >> application.  Robin, can you please check this?  We probably want to
> >> make the does-something version of cpu_hotplug_disable/enable available
> >> if CONFIG_HOTPLUG_CPU.
> > 
> > This patch came from "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>,
> > I think I need to defer.
> 
> Here is a revised patch, which should address all the problems, IMHO.
> Let me know if you face any issues. (And thanks a lot for fixing up the
> !SMP case in the previous version.)
> 
> --------------------------------------------------------------------->
> 
> From: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
> Subject: [PATCH] CPU hotplug: Provide a generic helper to disable/enable CPU hotplug
> 
> There are instances in the kernel where we would like to disable
> CPU hotplug (from sysfs) during some important operation. Today
> the freezer code depends on this and the code to do it was kinda
> tailor-made for that.
> 
> Restructure the code and make it generic enough to be useful for
> other usecases too.
> 
> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
> ---
> 
>  include/linux/cpu.h |    4 ++++
>  kernel/cpu.c        |   55 +++++++++++++++++++++------------------------------
>  2 files changed, 27 insertions(+), 32 deletions(-)
> 
> diff --git a/include/linux/cpu.h b/include/linux/cpu.h
> index c6f6e08..9f3c7e8 100644
> --- a/include/linux/cpu.h
> +++ b/include/linux/cpu.h
> @@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
>  
>  extern void get_online_cpus(void);
>  extern void put_online_cpus(void);
> +extern void cpu_hotplug_disable(void);
> +extern void cpu_hotplug_enable(void);
>  #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
>  #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
>  #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
> @@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
>  
>  #define get_online_cpus()	do { } while (0)
>  #define put_online_cpus()	do { } while (0)
> +#define cpu_hotplug_disable()	do { } while (0)
> +#define cpu_hotplug_enable()	do { } while (0)
>  #define hotcpu_notifier(fn, pri)	do { (void)(fn); } while (0)
>  /* These aren't inline functions due to a GCC bug. */
>  #define register_hotcpu_notifier(nb)	({ (void)(nb); 0; })
> diff --git a/kernel/cpu.c b/kernel/cpu.c
> index b5e4ab2..198a388 100644
> --- a/kernel/cpu.c
> +++ b/kernel/cpu.c
> @@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
>  	mutex_unlock(&cpu_hotplug.lock);
>  }
>  
> +/*
> + * Wait for currently running CPU hotplug operations to complete (if any) and
> + * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
> + * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
> + * hotplug path before performing hotplug operations. So acquiring that lock
> + * guarantees mutual exclusion from any currently running hotplug operations.
> + */
> +void cpu_hotplug_disable(void)
> +{
> +	cpu_maps_update_begin();
> +	cpu_hotplug_disabled = 1;
> +	cpu_maps_update_done();
> +}
> +
> +void cpu_hotplug_enable(void)
> +{
> +	cpu_maps_update_begin();
> +	cpu_hotplug_disabled = 0;
> +	cpu_maps_update_done();
> +}
> +
>  #else /* #if CONFIG_HOTPLUG_CPU */
>  static void cpu_hotplug_begin(void) {}
>  static void cpu_hotplug_done(void) {}
> @@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
>  core_initcall(alloc_frozen_cpus);
>  
>  /*
> - * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
> - * hotplug when tasks are about to be frozen. Also, don't allow the freezer
> - * to continue until any currently running CPU hotplug operation gets
> - * completed.
> - * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
> - * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
> - * CPU hotplug path and released only after it is complete. Thus, we
> - * (and hence the freezer) will block here until any currently running CPU
> - * hotplug operation gets completed.
> - */
> -void cpu_hotplug_disable_before_freeze(void)
> -{
> -	cpu_maps_update_begin();
> -	cpu_hotplug_disabled = 1;
> -	cpu_maps_update_done();
> -}
> -
> -
> -/*
> - * When tasks have been thawed, re-enable regular CPU hotplug (which had been
> - * disabled while beginning to freeze tasks).
> - */
> -void cpu_hotplug_enable_after_thaw(void)
> -{
> -	cpu_maps_update_begin();
> -	cpu_hotplug_disabled = 0;
> -	cpu_maps_update_done();
> -}
> -
> -/*
>   * When callbacks for CPU hotplug notifications are being executed, we must
>   * ensure that the state of the system with respect to the tasks being frozen
>   * or not, as reported by the notification, remains unchanged *throughout the
> @@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
>  
>  	case PM_SUSPEND_PREPARE:
>  	case PM_HIBERNATION_PREPARE:
> -		cpu_hotplug_disable_before_freeze();
> +		cpu_hotplug_disable();
>  		break;
>  
>  	case PM_POST_SUSPEND:
>  	case PM_POST_HIBERNATION:
> -		cpu_hotplug_enable_after_thaw();
> +		cpu_hotplug_enable();
>  		break;
>  
>  	default:
> 


From padma.kvr at gmail.com  Sat May 11 06:13:42 2013
From: padma.kvr at gmail.com (Padma Venkat)
Date: Sat, 11 May 2013 15:43:42 +0530
Subject: [PATCH V2 1/3] clk: samsung: register audio subsystem clocks
 using common clock framework
In-Reply-To: <1730722.Al2EYiRntt@flatron>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
 <1367909016-19657-2-git-send-email-padma.v@samsung.com>
 <1730722.Al2EYiRntt@flatron>
Message-ID: <CAAgF-BfeCZn8-_W-QxXw1QhU-Day-TEMtApiykw1mr7_aA=qTQ@mail.gmail.com>

Hi Tomasz,

On Fri, May 10, 2013 at 5:51 AM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> Hi Padmavathi,
>
> I managed to review the patch a bit more thoroughly and I had few more
> comments. You can find them inline.

Thanks for the review.

>
> On Tuesday 07 of May 2013 12:13:34 Padmavathi Venna wrote:
>> Audio subsystem is introduced in s5pv210 and exynos platforms.
>> This has seperate clock controller which can control i2s0 and
>> pcm0 clocks. This patch registers the audio subsystem clocks
>> with the common clock framework.
>>
>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>> ---
>>  .../bindings/clock/clk-samsung-audss.txt           |   64 +++++++++
>>  drivers/clk/samsung/Makefile                       |    1 +
>>  drivers/clk/samsung/clk-samsung-audss.c            |  137
>> ++++++++++++++++++++ include/dt-bindings/clk/samsung-audss-clk.h
>> |   25 ++++ 4 files changed, 227 insertions(+), 0 deletions(-)
>>  create mode 100644
>> Documentation/devicetree/bindings/clock/clk-samsung-audss.txt create
>> mode 100644 drivers/clk/samsung/clk-samsung-audss.c
>>  create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
>> b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt new
>> file mode 100644
>> index 0000000..ec2cd0b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
>> @@ -0,0 +1,64 @@
>> +* Samsung Audio Subsystem Clock Controller
>> +
>> +The Samsung Audio Subsystem clock controller generates and supplies
>> clocks +to Audio Subsystem block available in the S5PV210 and Exynos
>> SoCs. The clock +binding described here is applicable to all SoC's in
>> the S5PV210 and Exynos +family.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following:
>> +  - "samsung,s5pv210-audss-clock" - controller compatible with all
>> S5PV210 SoCs. +  - "samsung,exynos4210-audss-clock" - controller
>> compatible with all Exynos4 SoCs. +  - "samsung,exynos5250-audss-clock"
>> - controller compatible with all Exynos5 SoCs. +
>> +- reg: physical base address and length of the controller's register
>> set. +
>> +- #clock-cells: should be 1.
>> +
>> +The following is the list of clocks generated by the controller. Each
>> clock is +assigned an identifier and client nodes use this identifier
>> to specify the +clock which they consume. Some of the clocks are
>> available only on a particular +Exynos4 SoC and this is specified where
>> applicable.
>> +
>> +Provided clocks:
>> +
>> +Clock           ID      SoC (if specific)
>> +-----------------------------------------------
>> +
>> +mout_audss      0
>> +mout_i2s        1
>> +dout_srp        2
>> +dout_bus        3
>> +dout_i2s        4
>> +srp_clk         5
>> +i2s_bus         6
>> +sclk_i2s        7
>> +pcm_bus         8
>> +sclk_pcm        9
>> +
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> +clock_audss: audss-clock-controller at 03810000 {
>> +     compatible = "samsung,exynos5250-audss-clock";
>> +     reg = <0x03810000 0x0C>;
>> +     #clock-cells = <1>;
>> +};
>> +
>> +Example 2: I2S controller node that consumes the clock generated by the
>> clock +           controller. Refer to the standard clock bindings for
>> information +           about 'clocks' and 'clock-names' property.
>> +
>> + i2s0: i2s at 03830000 {
>> +             compatible = "samsung,i2s-v5";
>> +             reg = <0x03830000 0x100>;
>> +             dmas = <&pdma0 10
>> +                     &pdma0 9
>> +                     &pdma0 8>;
>> +             dma-names = "tx", "rx", "tx-sec";
>> +             clocks = <&clock_audss SAMSUNG_I2S_BUS>,
>> +                     <&clock_audss SAMSUNG_I2S_BUS>,
>> +                     <&clock_audss SAMSUNG_SCLK_I2S>;
>> +             clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
>> +};
>> +
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index b7c232e..5425fa8 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)      += clk.o clk-pll.o
>>  obj-$(CONFIG_ARCH_EXYNOS4)   += clk-exynos4.o
>>  obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
>>  obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
>> +obj-$(CONFIG_PLAT_SAMSUNG)   += clk-samsung-audss.o
>> diff --git a/drivers/clk/samsung/clk-samsung-audss.c
>> b/drivers/clk/samsung/clk-samsung-audss.c new file mode 100644
>> index 0000000..97526b7
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-samsung-audss.c
>> @@ -0,0 +1,137 @@
>> +/*
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author: Padmavathi Venna <padma.v at samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Audio Subsystem Clock Controller.
>> +*/
>> +
>> +#include <linux/clkdev.h>
>> +#include <linux/io.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_address.h>
>> +#include <linux/syscore_ops.h>
>> +
>> +#include <dt-bindings/clk/samsung-audss-clk.h>
>> +
>> +static DEFINE_SPINLOCK(lock);
>> +static struct clk **clk_table;
>> +static void __iomem *reg_base;
>> +static struct clk_onecell_data clk_data;
>> +
>> +#define ASS_CLK_SRC 0x0
>> +#define ASS_CLK_DIV 0x4
>> +#define ASS_CLK_GATE 0x8
>> +
>> +static unsigned long reg_save[][2] = {
>> +     {ASS_CLK_SRC,  0},
>> +     {ASS_CLK_DIV,  0},
>> +     {ASS_CLK_GATE, 0},
>> +};
>> +
>> +/* list of all parent clock list */
>> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
>> +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0",
>> "sclk_audio0" }; +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int samsung_audss_clk_suspend(void)
>> +{
>> +     int i;
>> +
>> +     for (i = 0; i < 3; i++)
>> +             reg_save[i][1] = readl(reg_base + reg_save[i][0]);
>> +
>> +     return 0;
>> +}
>> +
>> +static void samsung_audss_clk_resume(void)
>> +{
>> +     int i;
>> +
>> +     for (i = 0; i < 3; i++)
>> +             writel(reg_save[i][1], reg_base + reg_save[i][0]);
>> +}
>> +
>> +static struct syscore_ops samsung_audss_clk_syscore_ops = {
>> +     .suspend        = samsung_audss_clk_suspend,
>> +     .resume         = samsung_audss_clk_resume,
>> +};
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +/* register samsung_audss clocks */
>> +void __init samsung_audss_clk_init(struct device_node *np)
>> +{
>> +     reg_base = of_iomap(np, 0);
>> +     if (!reg_base) {
>> +             pr_err("%s: failed to map audss registers\n", __func__);
>> +             return;
>> +     }
>> +
>> +     clk_table = kzalloc(sizeof(struct clk *) * SAMSUNG_AUDSS_MAX_CLKS,
>> +                             GFP_KERNEL);
>> +     if (!clk_table) {
>> +             pr_err("%s: could not allocate clock lookup table\n",
> __func__);
>> +             return;
>> +     }
>> +
>> +     clk_data.clks = clk_table;
>> +     clk_data.clk_num = SAMSUNG_AUDSS_MAX_CLKS;
>> +     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>> +
>> +     clk_table[SAMSUNG_MOUT_AUDSS] = clk_register_mux(NULL,
> "mout_audss",
>> +                             mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
>> +                             reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
>> +     clk_register_clkdev(clk_table[SAMSUNG_MOUT_AUDSS], "mout_audss",
>> NULL); +
>
> Is there are a reason for this clkdev lookup to be registered?
>
> This driver seems to be used only in DT-case, so DT-based lookup should be
> enough.

Ok. I will not register these clocks with clkdev. I will add as clock
entries into i2s0 node.

>
>> +     clk_table[SAMSUNG_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
>> +                             mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
>> +                             reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
>> +     clk_register_clkdev(clk_table[SAMSUNG_MOUT_I2S], "mout_i2s",
> NULL);
>
> Same here.
>
>> +
>> +     clk_table[SAMSUNG_DOUT_SRP] = clk_register_divider(NULL,
> "dout_srp",
>> +                             "mout_audss", 0, reg_base + ASS_CLK_DIV,
> 0, 4,
>> +                             0, &lock);
>> +
>> +     clk_table[SAMSUNG_DOUT_BUS] = clk_register_divider(NULL,
> "dout_bus",
>> +                             "dout_srp", 0, reg_base + ASS_CLK_DIV, 4,
> 4, 0,
>> +                             &lock);
>> +
>> +     clk_table[SAMSUNG_DOUT_I2S] = clk_register_divider(NULL,
> "dout_i2s",
>> +                             "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8,
> 4, 0,
>> +                             &lock);
>> +
>> +     clk_table[SAMSUNG_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
>> +                             "dout_srp", CLK_SET_RATE_PARENT,
>> +                             reg_base + ASS_CLK_GATE, 0, 0, &lock);
>> +
>> +     clk_table[SAMSUNG_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
>> +                             "dout_bus", CLK_SET_RATE_PARENT,
>> +                             reg_base + ASS_CLK_GATE, 2, 0, &lock);
>> +
>> +     clk_table[SAMSUNG_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
>> +                             "dout_i2s", CLK_SET_RATE_PARENT,
>> +                             reg_base + ASS_CLK_GATE, 3, 0, &lock);
>> +
>> +     clk_table[SAMSUNG_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
>> +                              "sclk_pcm", CLK_SET_RATE_PARENT,
>> +                             reg_base + ASS_CLK_GATE, 4, 0, &lock);
>> +
>> +     clk_table[SAMSUNG_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
>> +                             "div_pcm0", CLK_SET_RATE_PARENT,
>> +                             reg_base + ASS_CLK_GATE, 5, 0, &lock);
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +     register_syscore_ops(&samsung_audss_clk_syscore_ops);
>> +#endif
>> +
>> +     pr_info("Exynos: Audss: clock setup completed\n");
>> +}
>> +CLK_OF_DECLARE(s5pv210_audss_clk, "samsung,s5pv210-audss-clock",
>> +             samsung_audss_clk_init);
>
> I'm wondering if this driver in its current state is really compatible
> with S5PV210. Quick look at documentation shows that CLK_GATE and CLK_DIV
> registers on this SoC have different layout than on Exynos SoCs.

Yes. There are some differences. As of now I will remove v210.

>
> I guess that for now the best choice would be to remove any mentions about
> S5PV210 from the patch and add them back after the driver gets proper
> support for this SoC.
>
>> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
>> +             samsung_audss_clk_init);
>> +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
>> +             samsung_audss_clk_init);
>
> Also if both Exynos4210 and Exynos5250 have exactly the same audss clock
> layout, there is no reason to have two compatibles for them - the
> convention is that just the first model that had this hardware is enough -
> in this case Exynos4210.
>
> Having two different compatibles suggests that those two SoCs differ in a
> way that needs special handling, which is misleading, based on the fact
> that there is no such special handling in the driver.

There is only one difference between Exynos4 and Exynos5 is bit 1 of
CLK_GATE register where in Exynos5 it is reserved and Exynos4 it is
gate to IntMEM. I am not sure if we use this bit some where? So is it
okey to have same compatible with this diff?

I will post next version of patches after the dependencies are merged
into mainline(dtc+cpp patches by Stephen).

>
> Best regards,
> Tomasz
>
Thanks
Padma


From tomasz.figa at gmail.com  Sat May 11 06:15:56 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sat, 11 May 2013 12:15:56 +0200
Subject: [PATCH] usb: gadget: s3c2410: fix clk resource leak and update
In-Reply-To: <518DE4FF.1000702@gmail.com>
References: <518DE4FF.1000702@gmail.com>
Message-ID: <1684189.YrZqmJjoym@flatron>

Hi Libo,

On Saturday 11 of May 2013 14:28:15 Libo Chen wrote:
> From: Libo Chen <libo.chen at huawei.com>

The patch subject is slightly misleading. It suggests that the patch only 
changes clock handling, but in fact the biggest part of the patch is 
conversion to devm_ helpers.

I think following subject would suit this patch better:

[PATCH] usb: gadget: s3c2410: Convert to managed resource allocation

What do you think?

Also please see my comments inline.

> currently, when clk_get(NULL,"usb-device") fail, it does not
> disable && put usb_bus_clock. It is incorrect.
> 
> this patch use new interface devm_xxx instead of xxx then
> we no need to care about cleanup resource in err case that is boring
> and reduce code size.
> 
> Signed-off-by: Libo Chen <libo.chen at huawei.com>
> ---
>  drivers/usb/gadget/s3c2410_udc.c | 85
> ++++++++++++----------------------------
>  1 file changed, 25 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/usb/gadget/s3c2410_udc.c
> b/drivers/usb/gadget/s3c2410_udc.c
> old mode 100644
> new mode 100755
> index d0e75e1..0c573a8
> --- a/drivers/usb/gadget/s3c2410_udc.c
> +++ b/drivers/usb/gadget/s3c2410_udc.c
> @@ -1780,7 +1780,7 @@ static int s3c2410_udc_probe(struct
> platform_device *pdev)
> 
>  	dev_dbg(dev, "%s()\n", __func__);
> 
> -	usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
> +	usb_bus_clock = devm_clk_get(NULL, "usb-bus-gadget");

Passing NULL as the dev parameter of devm_ functions is a BUG. You need to 
pass a valid pointer to struct device to them, otherwise it doesn't make 
sense - the list of allocated resources is a part of struct device.

>  	if (IS_ERR(usb_bus_clock)) {
>  		dev_err(dev, "failed to get usb bus clock source\n");
>  		return PTR_ERR(usb_bus_clock);
> @@ -1788,8 +1788,9 @@ static int s3c2410_udc_probe(struct
> platform_device *pdev)
> 
>  	clk_enable(usb_bus_clock);

If you enable this clock after allocation of all resources instead, you 
won't have to disable it manually like in following chunk:
> 
> -	udc_clock = clk_get(NULL, "usb-device");
> +	udc_clock = devm_clk_get(NULL, "usb-device");
>  	if (IS_ERR(udc_clock)) {
> +		clk_disable(usb_bus_clock);
>  		dev_err(dev, "failed to get udc clock source\n");
>  		return PTR_ERR(udc_clock);
>  	}
> @@ -1814,13 +1815,15 @@ static int s3c2410_udc_probe(struct
> platform_device *pdev)
>  	rsrc_start = S3C2410_PA_USBDEV;
>  	rsrc_len   = S3C24XX_SZ_USBDEV;
> 
> -	if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
> -		return -EBUSY;
> +	if (!devm_request_mem_region(rsrc_start, rsrc_len, gadget_name)) {
> +		retval = -EBUSY;
> +		goto out;
> +	}
> 
> -	base_addr = ioremap(rsrc_start, rsrc_len);
> +	base_addr = devm_ioremap(rsrc_start, rsrc_len);

This won't even compile... Was this patch tested at all?

See the definition of devm_ioremap:
http://lxr.free-electrons.com/source/lib/devres.c#L25

In addition, a better function is available, devm_request_and_ioremap.
(http://lxr.free-electrons.com/source/lib/devres.c#L143)

You can use it instead of calling request_mem_region and ioremap 
separately.

>  	if (!base_addr) {
>  		retval = -ENOMEM;
> -		goto err_mem;
> +		goto out;
>  	}
> 
>  	the_controller = udc;
> @@ -1830,31 +1833,31 @@ static int s3c2410_udc_probe(struct
> platform_device *pdev)
>  	s3c2410_udc_reinit(udc);
> 
>  	/* irq setup after old hardware state is cleaned up */
> -	retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
> +	retval = devm_request_irq(IRQ_USBD, s3c2410_udc_irq,
>  			     0, gadget_name, udc);

This won't compile too.

>  	if (retval != 0) {
>  		dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, 
retval);
>  		retval = -EBUSY;
> -		goto err_map;
> +		goto out;
>  	}
> 
>  	dev_dbg(dev, "got irq %i\n", IRQ_USBD);
> 
>  	if (udc_info && udc_info->vbus_pin > 0) {
> -		retval = gpio_request(udc_info->vbus_pin, "udc vbus");
> +		retval = devm_gpio_request(udc_info->vbus_pin, "udc 
vbus");

Neither this will.

>  		if (retval < 0) {
>  			dev_err(dev, "cannot claim vbus pin\n");
> -			goto err_int;
> +			goto out;
>  		}
> 
>  		irq = gpio_to_irq(udc_info->vbus_pin);
>  		if (irq < 0) {
>  			dev_err(dev, "no irq for gpio vbus pin\n");
> -			goto err_gpio_claim;
> +			goto out;
>  		}
> 
> -		retval = request_irq(irq, s3c2410_udc_vbus_irq,
> +		retval = devm_request_irq(irq, s3c2410_udc_vbus_irq,
>  				     IRQF_TRIGGER_RISING

Neither this will.

> 
>  				     | IRQF_TRIGGER_FALLING | IRQF_SHARED,
> 
>  				     gadget_name, udc);
> @@ -1863,7 +1866,7 @@ static int s3c2410_udc_probe(struct
> platform_device *pdev)
>  			dev_err(dev, "can't get vbus irq %d, err %d\n",
>  				irq, retval);
>  			retval = -EBUSY;
> -			goto err_gpio_claim;
> +			goto out;
>  		}
> 
>  		dev_dbg(dev, "got irq %i\n", irq);
> @@ -1874,17 +1877,17 @@ static int s3c2410_udc_probe(struct
> platform_device *pdev)
>  	if (udc_info && !udc_info->udc_command &&
>  		gpio_is_valid(udc_info->pullup_pin)) {
> 
> -		retval = gpio_request_one(udc_info->pullup_pin,
> +		retval = devm_gpio_request_one(udc_info->pullup_pin,

Neither this will.

Well, this patch is a good idea, but a very poor implementation.

Please _test_ (compile and boot) your patch next time.

Best regards,
Tomasz



From chenlibo.3 at gmail.com  Sat May 11 07:27:48 2013
From: chenlibo.3 at gmail.com (Libo Chen)
Date: Sat, 11 May 2013 19:27:48 +0800
Subject: [PATCH] usb: gadget: s3c2410: fix clk resource leak and update
In-Reply-To: <1684189.YrZqmJjoym@flatron>
References: <518DE4FF.1000702@gmail.com> <1684189.YrZqmJjoym@flatron>
Message-ID: <518E2B34.7080503@gmail.com>

? 2013-5-11 18:15, Tomasz Figa ??:
> Hi Libo,
>
> On Saturday 11 of May 2013 14:28:15 Libo Chen wrote:
>> >From: Libo Chen<libo.chen at huawei.com>
> The patch subject is slightly misleading. It suggests that the patch only
> changes clock handling, but in fact the biggest part of the patch is
> conversion to devm_ helpers.
>
> I think following subject would suit this patch better:
>
> [PATCH] usb: gadget: s3c2410: Convert to managed resource allocation
>
> What do you think?
>
> Also please see my comments inline.
>

Hi Tomasz,

Thank you for your remind. Sorry, I forgeted to add RFC.

"Convert to managed resource allocation" is more suitable.

Your advice is very helpfull for me to understand those interfaces.
I will be careful in the future patches.

Thanks again




From heiko at sntech.de  Sat May 11 07:30:04 2013
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Sat, 11 May 2013 13:30:04 +0200
Subject: [RFC 0/4] ARM: S3C24XX: add dmaengine based dma-driver
Message-ID: <201305111330.05046.heiko@sntech.de>

This series tries to provide a basic dmaengine driver for the s3c24xx
SoCs.

The driver currently has some limitations, in that it does not support the
earlier s3c24xx socs, that cannot use every channel, but have special
channel requirements for specific slave-targets.

Another limitation is, that it currently does not support scatter-gather
lists with more than element, due to me not understanding sg at first.
While it does not hinder the usability, as all applicable Samsung drivers
currently use only 1-element-lists, I plan to fix this in the next revision.

In any case, I would be thankful for pointers to the obvious mistakes I'll
probably have made, due to this being my first travel into dmaengine-land.


Heiko Stuebner (4):
  ARM: S3C24XX: number the dma clocks
  dma: add dmaengine driver for Samsung s3c24xx SoCs
  ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
  ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device

 arch/arm/mach-s3c24xx/clock-s3c2412.c     |    8 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c    |   12 +-
 arch/arm/mach-s3c24xx/common.c            |  103 +++
 arch/arm/mach-s3c24xx/common.h            |    3 +
 arch/arm/plat-samsung/devs.c              |    5 +-
 drivers/dma/Kconfig                       |   12 +-
 drivers/dma/Makefile                      |    1 +
 drivers/dma/s3c24xx-dma.c                 | 1129 +++++++++++++++++++++++++++++
 include/linux/platform_data/dma-s3c24xx.h |   54 ++
 9 files changed, 1315 insertions(+), 12 deletions(-)
 create mode 100644 drivers/dma/s3c24xx-dma.c
 create mode 100644 include/linux/platform_data/dma-s3c24xx.h

-- 
1.7.2.3



From sylvester.nawrocki at gmail.com  Sat May 11 07:42:11 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sat, 11 May 2013 13:42:11 +0200
Subject: [PATCH V2 1/3] clk: samsung: register audio subsystem clocks
 using common clock framework
In-Reply-To: <CAAgF-BfeCZn8-_W-QxXw1QhU-Day-TEMtApiykw1mr7_aA=qTQ@mail.gmail.com>
References: <1367909016-19657-1-git-send-email-padma.v@samsung.com>
 <1367909016-19657-2-git-send-email-padma.v@samsung.com>
 <1730722.Al2EYiRntt@flatron>
 <CAAgF-BfeCZn8-_W-QxXw1QhU-Day-TEMtApiykw1mr7_aA=qTQ@mail.gmail.com>
Message-ID: <518E2E93.7030104@gmail.com>

Hi,

On 05/11/2013 12:13 PM, Padma Venkat wrote:
>>> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
>>> >>  +             samsung_audss_clk_init);
>>> >>  +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
>>> >>  +             samsung_audss_clk_init);
>> >
>> >  Also if both Exynos4210 and Exynos5250 have exactly the same audss clock
>> >  layout, there is no reason to have two compatibles for them - the
>> >  convention is that just the first model that had this hardware is enough -
>> >  in this case Exynos4210.
>> >
>> >  Having two different compatibles suggests that those two SoCs differ in a
>> >  way that needs special handling, which is misleading, based on the fact
>> >  that there is no such special handling in the driver.
>
> There is only one difference between Exynos4 and Exynos5 is bit 1 of
> CLK_GATE register where in Exynos5 it is reserved and Exynos4 it is
> gate to IntMEM. I am not sure if we use this bit some where? So is it
> okey to have same compatible with this diff?

I think such difference warrants separate compatible properties, as 
Exynos5250
seems to be not compatible with Exynos4210 in that case. Reserved bits 
should
be left untouched.

I wouldn't be surprised to see more differences we might be overlooking 
now.
IMHO it's better to be save than sorry, keeping both 'compatible' 
strings as
they are now.

Regards,
Sylwester


From holt at sgi.com  Sat May 11 07:57:19 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:19 -0500
Subject: [PATCH -v10 03/11] Remove -stable friendly PF_THREAD_BOUND define
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-4-git-send-email-holt@sgi.com>

Remove the prior patch's #define for easier backporting to the stable
releases.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 kernel/sys.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index 2bbd9a7..17bb8d3 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,11 +362,6 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
-/* Add backwards compatibility for stable trees. */
-#ifndef PF_NO_SETAFFINITY
-#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
-#endif
-
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:16 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:16 -0500
Subject: [PATCH -v10 00/11] Shutdown from reboot_cpuid without stopping other
 cpus.
Message-ID: <1368273447-11958-1-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.

Changes since -v9
 - Added Ingo's Acked-by for x86.

 - Added Guan's Acked-by for unicore32.

 - Replaced first patch with updated patch from Srivatsa S. Bhat.
   This compiles for alpha allmodconfig, all arm defconfigs, and a few
   test x86_64 defconfigs.  I have not tried more.

Changes since -v8
 - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.

 - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.

 - Fixed case statement bug.

 - Went to using simple_strtoul for parsing reboot_cpu=smp###.

 - Made parsing of reboot= not use any #ifdef'd code.

Changes since -v7.
 - Fixed authorship for first patch.

 - Rebased to Linus' current tree (51a26ae7a).

Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From holt at sgi.com  Sat May 11 07:57:18 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:18 -0500
Subject: [PATCH -v10 02/11] Migrate shutdown/reboot to boot cpu.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-3-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
boot cpu and then continuing with shutdown/reboot.

This also has the effect of not breaking x86's command line parameter for
specifying the reboot cpu.  Note, this code was shamelessly copied from
arch/x86/kernel/reboot.c with bits removed pertaining to the reboot_cpu
command line parameter.

Signed-off-by: Robin Holt <holt at sgi.com>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v8
 - Change stack parameter to make future patches cleaner.

Changes since -v6:
 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
 - Fixup s/reboot_cpu_id/reboot_cpu/
---
 kernel/sys.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c7..2bbd9a7 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
 /**
  *	kernel_restart - reboot the system
  *	@cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
 	kernel_restart_prepare(cmd);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
 		printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
 	kernel_shutdown_prepare(SYSTEM_HALT);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
 	if (pm_power_off_prepare)
 		pm_power_off_prepare();
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:17 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:17 -0500
Subject: [PATCH -v10 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-2-git-send-email-holt@sgi.com>

From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>
---
 include/linux/cpu.h |  4 ++++
 kernel/cpu.c        | 55 ++++++++++++++++++++++-------------------------------
 2 files changed, 27 insertions(+), 32 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..9f3c7e8 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
 
 extern void get_online_cpus(void);
 extern void put_online_cpus(void);
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
@@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
 
 #define get_online_cpus()	do { } while (0)
 #define put_online_cpus()	do { } while (0)
+#define cpu_hotplug_disable()	do { } while (0)
+#define cpu_hotplug_enable()	do { } while (0)
 #define hotcpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 /* These aren't inline functions due to a GCC bug. */
 #define register_hotcpu_notifier(nb)	({ (void)(nb); 0; })
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..198a388 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
 	mutex_unlock(&cpu_hotplug.lock);
 }
 
+/*
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
+ */
+void cpu_hotplug_disable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 1;
+	cpu_maps_update_done();
+}
+
+void cpu_hotplug_enable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 0;
+	cpu_maps_update_done();
+}
+
 #else /* #if CONFIG_HOTPLUG_CPU */
 static void cpu_hotplug_begin(void) {}
 static void cpu_hotplug_done(void) {}
@@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
- */
-void cpu_hotplug_disable_before_freeze(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 1;
-	cpu_maps_update_done();
-}
-
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 0;
-	cpu_maps_update_done();
-}
-
-/*
  * When callbacks for CPU hotplug notifications are being executed, we must
  * ensure that the state of the system with respect to the tasks being frozen
  * or not, as reported by the notification, remains unchanged *throughout the
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:23 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:23 -0500
Subject: [PATCH -v10 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-8-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>
---

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/unicore32/kernel/process.c | 10 +++++-----
 arch/unicore32/kernel/setup.h   |  2 +-
 arch/unicore32/mm/mmu.c         |  2 +-
 include/linux/reboot.h          |  2 ++
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index c944769..93dd035 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,14 +51,14 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static char reboot_mode = 'h';
+static enum reboot_mode reboot_mode = REBOOT_HARD;
 
 int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
@@ -88,7 +88,7 @@ void machine_restart(char *cmd)
 	 * we may need it to insert some 1:1 mappings so that
 	 * soft boot works.
 	 */
-	setup_mm_for_reboot(reboot_mode);
+	setup_mm_for_reboot();
 
 	/* Clean and invalidate caches */
 	flush_cache_all();
@@ -102,7 +102,7 @@ void machine_restart(char *cmd)
 	/*
 	 * Now handle reboot code.
 	 */
-	if (reboot_mode == 's') {
+	if (reboot_mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index 30f749d..f5c51b8 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
 extern void pci_puv3_preinit(void);
 extern void __init puv3_init_gpio(void);
 
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 
 extern char __stubs_start[], __stubs_end[];
 extern char __vectors_start[], __vectors_end[];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index 43c20b4..4f5a532 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -445,7 +445,7 @@ void __init paging_init(void)
  * the user-mode pages.  This will then ensure that we have predictable
  * results when turning the mmu off
  */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 	unsigned long base_pmdval;
 	pgd_t *pgd;
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 37d56c3..ca29a6f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -13,6 +13,8 @@
 enum reboot_mode {
 	REBOOT_COLD = 0,
 	REBOOT_WARM,
+	REBOOT_HARD,
+	REBOOT_SOFT,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:20 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:20 -0500
Subject: [PATCH -v10 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-5-git-send-email-holt@sgi.com>

This patch is preparatory.  It moves reboot related syscall, etc
functions from kernel/sys.c to kernel/reboot.c.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v6:
 - Add include of linux/uaccess.h to allow building on arm.
---
 kernel/Makefile |   2 +-
 kernel/reboot.c | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/sys.c    | 331 -----------------------------------------------------
 3 files changed, 348 insertions(+), 332 deletions(-)
 create mode 100644 kernel/reboot.c

diff --git a/kernel/Makefile b/kernel/Makefile
index 271fd31..470839d 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y     = fork.o exec_domain.o panic.o printk.o \
 	    rcupdate.o extable.o params.o posix-timers.o \
 	    kthread.o wait.o sys_ni.o posix-cpu-timers.o mutex.o \
 	    hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-	    notifier.o ksysfs.o cred.o \
+	    notifier.o ksysfs.o cred.o reboot.o \
 	    async.o range.o groups.o lglock.o smpboot.o
 
 ifdef CONFIG_FUNCTION_TRACER
diff --git a/kernel/reboot.c b/kernel/reboot.c
new file mode 100644
index 0000000..0616483
--- /dev/null
+++ b/kernel/reboot.c
@@ -0,0 +1,347 @@
+/*
+ *  linux/kernel/reboot.c
+ *
+ *  Copyright (C) 2013  Linus Torvalds
+ */
+
+#include <linux/export.h>
+#include <linux/kexec.h>
+#include <linux/kmod.h>
+#include <linux/kmsg_dump.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h>
+#include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
+
+/*
+ * this indicates whether you can reboot with ctrl-alt-del: the default is yes
+ */
+
+int C_A_D = 1;
+struct pid *cad_pid;
+EXPORT_SYMBOL(cad_pid);
+
+/*
+ * If set, this is used for preparing the system to power off.
+ */
+
+void (*pm_power_off_prepare)(void);
+
+/**
+ *	emergency_restart - reboot the system
+ *
+ *	Without shutting down any hardware or taking any locks
+ *	reboot the system.  This is called when we know we are in
+ *	trouble so this is our best effort to reboot.  This is
+ *	safe to call in interrupt context.
+ */
+void emergency_restart(void)
+{
+	kmsg_dump(KMSG_DUMP_EMERG);
+	machine_emergency_restart();
+}
+EXPORT_SYMBOL_GPL(emergency_restart);
+
+void kernel_restart_prepare(char *cmd)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
+	system_state = SYSTEM_RESTART;
+	usermodehelper_disable();
+	device_shutdown();
+}
+
+/**
+ *	register_reboot_notifier - Register function to be called at reboot time
+ *	@nb: Info about notifier function to be called
+ *
+ *	Registers a function with the list of functions
+ *	to be called at reboot time.
+ *
+ *	Currently always returns zero, as blocking_notifier_chain_register()
+ *	always returns zero.
+ */
+int register_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(register_reboot_notifier);
+
+/**
+ *	unregister_reboot_notifier - Unregister previously registered reboot notifier
+ *	@nb: Hook to be unregistered
+ *
+ *	Unregisters a previously registered reboot
+ *	notifier function.
+ *
+ *	Returns zero on success, or %-ENOENT on failure.
+ */
+int unregister_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(unregister_reboot_notifier);
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
+/**
+ *	kernel_restart - reboot the system
+ *	@cmd: pointer to buffer containing command to execute for restart
+ *		or %NULL
+ *
+ *	Shutdown everything and perform a clean reboot.
+ *	This is not safe to call in interrupt context.
+ */
+void kernel_restart(char *cmd)
+{
+	kernel_restart_prepare(cmd);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	if (!cmd)
+		printk(KERN_EMERG "Restarting system.\n");
+	else
+		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+	kmsg_dump(KMSG_DUMP_RESTART);
+	machine_restart(cmd);
+}
+EXPORT_SYMBOL_GPL(kernel_restart);
+
+static void kernel_shutdown_prepare(enum system_states state)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list,
+		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+	system_state = state;
+	usermodehelper_disable();
+	device_shutdown();
+}
+/**
+ *	kernel_halt - halt the system
+ *
+ *	Shutdown everything and perform a clean system halt.
+ */
+void kernel_halt(void)
+{
+	kernel_shutdown_prepare(SYSTEM_HALT);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "System halted.\n");
+	kmsg_dump(KMSG_DUMP_HALT);
+	machine_halt();
+}
+
+EXPORT_SYMBOL_GPL(kernel_halt);
+
+/**
+ *	kernel_power_off - power_off the system
+ *
+ *	Shutdown everything and perform a clean system power_off.
+ */
+void kernel_power_off(void)
+{
+	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
+	if (pm_power_off_prepare)
+		pm_power_off_prepare();
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "Power down.\n");
+	kmsg_dump(KMSG_DUMP_POWEROFF);
+	machine_power_off();
+}
+EXPORT_SYMBOL_GPL(kernel_power_off);
+
+static DEFINE_MUTEX(reboot_mutex);
+
+/*
+ * Reboot system call: for obvious reasons only root may call it,
+ * and even root needs to set up some magic numbers in the registers
+ * so that some mistake won't make this reboot the whole machine.
+ * You can also set the meaning of the ctrl-alt-del-key here.
+ *
+ * reboot doesn't sync: do that yourself before calling this.
+ */
+SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
+		void __user *, arg)
+{
+	struct pid_namespace *pid_ns = task_active_pid_ns(current);
+	char buffer[256];
+	int ret = 0;
+
+	/* We only trust the superuser with rebooting the system. */
+	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
+		return -EPERM;
+
+	/* For safety, we require "magic" arguments. */
+	if (magic1 != LINUX_REBOOT_MAGIC1 ||
+	    (magic2 != LINUX_REBOOT_MAGIC2 &&
+	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			magic2 != LINUX_REBOOT_MAGIC2B &&
+	                magic2 != LINUX_REBOOT_MAGIC2C))
+		return -EINVAL;
+
+	/*
+	 * If pid namespaces are enabled and the current task is in a child
+	 * pid_namespace, the command is handled by reboot_pid_ns() which will
+	 * call do_exit().
+	 */
+	ret = reboot_pid_ns(pid_ns, cmd);
+	if (ret)
+		return ret;
+
+	/* Instead of trying to make the power_off code look like
+	 * halt when pm_power_off is not set do it the easy way.
+	 */
+	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
+		cmd = LINUX_REBOOT_CMD_HALT;
+
+	mutex_lock(&reboot_mutex);
+	switch (cmd) {
+	case LINUX_REBOOT_CMD_RESTART:
+		kernel_restart(NULL);
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_ON:
+		C_A_D = 1;
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_OFF:
+		C_A_D = 0;
+		break;
+
+	case LINUX_REBOOT_CMD_HALT:
+		kernel_halt();
+		do_exit(0);
+		panic("cannot halt");
+
+	case LINUX_REBOOT_CMD_POWER_OFF:
+		kernel_power_off();
+		do_exit(0);
+		break;
+
+	case LINUX_REBOOT_CMD_RESTART2:
+		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+			ret = -EFAULT;
+			break;
+		}
+		buffer[sizeof(buffer) - 1] = '\0';
+
+		kernel_restart(buffer);
+		break;
+
+#ifdef CONFIG_KEXEC
+	case LINUX_REBOOT_CMD_KEXEC:
+		ret = kernel_kexec();
+		break;
+#endif
+
+#ifdef CONFIG_HIBERNATION
+	case LINUX_REBOOT_CMD_SW_SUSPEND:
+		ret = hibernate();
+		break;
+#endif
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&reboot_mutex);
+	return ret;
+}
+
+static void deferred_cad(struct work_struct *dummy)
+{
+	kernel_restart(NULL);
+}
+
+/*
+ * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
+ * As it's called within an interrupt, it may NOT sync: the only choice
+ * is whether to reboot at once, or just ignore the ctrl-alt-del.
+ */
+void ctrl_alt_del(void)
+{
+	static DECLARE_WORK(cad_work, deferred_cad);
+
+	if (C_A_D)
+		schedule_work(&cad_work);
+	else
+		kill_cad_pid(SIGINT, 1);
+}
+	
+
+char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
+
+static int __orderly_poweroff(bool force)
+{
+	char **argv;
+	static char *envp[] = {
+		"HOME=/",
+		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
+		NULL
+	};
+	int ret;
+
+	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
+	if (argv) {
+		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
+		argv_free(argv);
+	} else {
+		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
+					 __func__, poweroff_cmd);
+		ret = -ENOMEM;
+	}
+
+	if (ret && force) {
+		printk(KERN_WARNING "Failed to start orderly shutdown: "
+					"forcing the issue\n");
+		/*
+		 * I guess this should try to kick off some daemon to sync and
+		 * poweroff asap.  Or not even bother syncing if we're doing an
+		 * emergency shutdown?
+		 */
+		emergency_sync();
+		kernel_power_off();
+	}
+
+	return ret;
+}
+
+static bool poweroff_force;
+
+static void poweroff_work_func(struct work_struct *work)
+{
+	__orderly_poweroff(poweroff_force);
+}
+
+static DECLARE_WORK(poweroff_work, poweroff_work_func);
+
+/**
+ * orderly_poweroff - Trigger an orderly system poweroff
+ * @force: force poweroff if command execution fails
+ *
+ * This may be called from any context to trigger a system shutdown.
+ * If the orderly shutdown fails, it will force an immediate shutdown.
+ */
+int orderly_poweroff(bool force)
+{
+	if (force) /* do not override the pending "true" */
+		poweroff_force = true;
+	schedule_work(&poweroff_work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(orderly_poweroff);
diff --git a/kernel/sys.c b/kernel/sys.c
index 17bb8d3..467a18f 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -116,20 +116,6 @@ EXPORT_SYMBOL(fs_overflowuid);
 EXPORT_SYMBOL(fs_overflowgid);
 
 /*
- * this indicates whether you can reboot with ctrl-alt-del: the default is yes
- */
-
-int C_A_D = 1;
-struct pid *cad_pid;
-EXPORT_SYMBOL(cad_pid);
-
-/*
- * If set, this is used for preparing the system to power off.
- */
-
-void (*pm_power_off_prepare)(void);
-
-/*
  * Returns true if current's euid is same as p's uid or euid,
  * or has CAP_SYS_NICE to p's user_ns.
  *
@@ -308,261 +294,6 @@ out_unlock:
 	return retval;
 }
 
-/**
- *	emergency_restart - reboot the system
- *
- *	Without shutting down any hardware or taking any locks
- *	reboot the system.  This is called when we know we are in
- *	trouble so this is our best effort to reboot.  This is
- *	safe to call in interrupt context.
- */
-void emergency_restart(void)
-{
-	kmsg_dump(KMSG_DUMP_EMERG);
-	machine_emergency_restart();
-}
-EXPORT_SYMBOL_GPL(emergency_restart);
-
-void kernel_restart_prepare(char *cmd)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
-	system_state = SYSTEM_RESTART;
-	usermodehelper_disable();
-	device_shutdown();
-}
-
-/**
- *	register_reboot_notifier - Register function to be called at reboot time
- *	@nb: Info about notifier function to be called
- *
- *	Registers a function with the list of functions
- *	to be called at reboot time.
- *
- *	Currently always returns zero, as blocking_notifier_chain_register()
- *	always returns zero.
- */
-int register_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(register_reboot_notifier);
-
-/**
- *	unregister_reboot_notifier - Unregister previously registered reboot notifier
- *	@nb: Hook to be unregistered
- *
- *	Unregisters a previously registered reboot
- *	notifier function.
- *
- *	Returns zero on success, or %-ENOENT on failure.
- */
-int unregister_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(unregister_reboot_notifier);
-
-static void migrate_to_reboot_cpu(void)
-{
-	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
-
-	cpu_hotplug_disable();
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(cpu))
-		cpu = cpumask_first(cpu_online_mask);
-
-	/* Prevent races with other tasks migrating this task */
-	current->flags |= PF_NO_SETAFFINITY;
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(cpu));
-}
-
-/**
- *	kernel_restart - reboot the system
- *	@cmd: pointer to buffer containing command to execute for restart
- *		or %NULL
- *
- *	Shutdown everything and perform a clean reboot.
- *	This is not safe to call in interrupt context.
- */
-void kernel_restart(char *cmd)
-{
-	kernel_restart_prepare(cmd);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
-	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
-	kmsg_dump(KMSG_DUMP_RESTART);
-	machine_restart(cmd);
-}
-EXPORT_SYMBOL_GPL(kernel_restart);
-
-static void kernel_shutdown_prepare(enum system_states state)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
-	system_state = state;
-	usermodehelper_disable();
-	device_shutdown();
-}
-/**
- *	kernel_halt - halt the system
- *
- *	Shutdown everything and perform a clean system halt.
- */
-void kernel_halt(void)
-{
-	kernel_shutdown_prepare(SYSTEM_HALT);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
-	kmsg_dump(KMSG_DUMP_HALT);
-	machine_halt();
-}
-
-EXPORT_SYMBOL_GPL(kernel_halt);
-
-/**
- *	kernel_power_off - power_off the system
- *
- *	Shutdown everything and perform a clean system power_off.
- */
-void kernel_power_off(void)
-{
-	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
-	if (pm_power_off_prepare)
-		pm_power_off_prepare();
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
-	kmsg_dump(KMSG_DUMP_POWEROFF);
-	machine_power_off();
-}
-EXPORT_SYMBOL_GPL(kernel_power_off);
-
-static DEFINE_MUTEX(reboot_mutex);
-
-/*
- * Reboot system call: for obvious reasons only root may call it,
- * and even root needs to set up some magic numbers in the registers
- * so that some mistake won't make this reboot the whole machine.
- * You can also set the meaning of the ctrl-alt-del-key here.
- *
- * reboot doesn't sync: do that yourself before calling this.
- */
-SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
-		void __user *, arg)
-{
-	struct pid_namespace *pid_ns = task_active_pid_ns(current);
-	char buffer[256];
-	int ret = 0;
-
-	/* We only trust the superuser with rebooting the system. */
-	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
-		return -EPERM;
-
-	/* For safety, we require "magic" arguments. */
-	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
-			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
-		return -EINVAL;
-
-	/*
-	 * If pid namespaces are enabled and the current task is in a child
-	 * pid_namespace, the command is handled by reboot_pid_ns() which will
-	 * call do_exit().
-	 */
-	ret = reboot_pid_ns(pid_ns, cmd);
-	if (ret)
-		return ret;
-
-	/* Instead of trying to make the power_off code look like
-	 * halt when pm_power_off is not set do it the easy way.
-	 */
-	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
-		cmd = LINUX_REBOOT_CMD_HALT;
-
-	mutex_lock(&reboot_mutex);
-	switch (cmd) {
-	case LINUX_REBOOT_CMD_RESTART:
-		kernel_restart(NULL);
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_ON:
-		C_A_D = 1;
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_OFF:
-		C_A_D = 0;
-		break;
-
-	case LINUX_REBOOT_CMD_HALT:
-		kernel_halt();
-		do_exit(0);
-		panic("cannot halt");
-
-	case LINUX_REBOOT_CMD_POWER_OFF:
-		kernel_power_off();
-		do_exit(0);
-		break;
-
-	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
-			ret = -EFAULT;
-			break;
-		}
-		buffer[sizeof(buffer) - 1] = '\0';
-
-		kernel_restart(buffer);
-		break;
-
-#ifdef CONFIG_KEXEC
-	case LINUX_REBOOT_CMD_KEXEC:
-		ret = kernel_kexec();
-		break;
-#endif
-
-#ifdef CONFIG_HIBERNATION
-	case LINUX_REBOOT_CMD_SW_SUSPEND:
-		ret = hibernate();
-		break;
-#endif
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	mutex_unlock(&reboot_mutex);
-	return ret;
-}
-
-static void deferred_cad(struct work_struct *dummy)
-{
-	kernel_restart(NULL);
-}
-
-/*
- * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
- * As it's called within an interrupt, it may NOT sync: the only choice
- * is whether to reboot at once, or just ignore the ctrl-alt-del.
- */
-void ctrl_alt_del(void)
-{
-	static DECLARE_WORK(cad_work, deferred_cad);
-
-	if (C_A_D)
-		schedule_work(&cad_work);
-	else
-		kill_cad_pid(SIGINT, 1);
-}
-	
 /*
  * Unprivileged users may change the real gid to the effective gid
  * or vice versa.  (BSD-style)
@@ -2276,68 +2007,6 @@ SYSCALL_DEFINE3(getcpu, unsigned __user *, cpup, unsigned __user *, nodep,
 	return err ? -EFAULT : 0;
 }
 
-char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
-
-static int __orderly_poweroff(bool force)
-{
-	char **argv;
-	static char *envp[] = {
-		"HOME=/",
-		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
-		NULL
-	};
-	int ret;
-
-	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
-	if (argv) {
-		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
-		argv_free(argv);
-	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
-		ret = -ENOMEM;
-	}
-
-	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
-		/*
-		 * I guess this should try to kick off some daemon to sync and
-		 * poweroff asap.  Or not even bother syncing if we're doing an
-		 * emergency shutdown?
-		 */
-		emergency_sync();
-		kernel_power_off();
-	}
-
-	return ret;
-}
-
-static bool poweroff_force;
-
-static void poweroff_work_func(struct work_struct *work)
-{
-	__orderly_poweroff(poweroff_force);
-}
-
-static DECLARE_WORK(poweroff_work, poweroff_work_func);
-
-/**
- * orderly_poweroff - Trigger an orderly system poweroff
- * @force: force poweroff if command execution fails
- *
- * This may be called from any context to trigger a system shutdown.
- * If the orderly shutdown fails, it will force an immediate shutdown.
- */
-int orderly_poweroff(bool force)
-{
-	if (force) /* do not override the pending "true" */
-		poweroff_force = true;
-	schedule_work(&poweroff_work);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(orderly_poweroff);
-
 /**
  * do_sysinfo - fill in sysinfo struct
  * @info: pointer to buffer to fill
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:21 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:21 -0500
Subject: [PATCH -v10 05/11] checkpatch.pl the new kernel/reboot.c file.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-6-git-send-email-holt@sgi.com>

Get the new file to pass scripts/checkpatch.pl

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since v6:
 - Removed last remaining line length warning.
---
 include/linux/reboot.h |  2 +-
 kernel/reboot.c        | 28 +++++++++++++---------------
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 23b3630..c6eba21 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -26,7 +26,7 @@ extern void machine_shutdown(void);
 struct pt_regs;
 extern void machine_crash_shutdown(struct pt_regs *);
 
-/* 
+/*
  * Architecture independent implemenations of sys_reboot commands.
  */
 
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 0616483..abb6a04 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -4,6 +4,8 @@
  *  Copyright (C) 2013  Linus Torvalds
  */
 
+#define pr_fmt(fmt)	"reboot: " fmt
+
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -114,9 +116,9 @@ void kernel_restart(char *cmd)
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
+		pr_emerg("Restarting system\n");
 	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+		pr_emerg("Restarting system with command '%s'\n", cmd);
 	kmsg_dump(KMSG_DUMP_RESTART);
 	machine_restart(cmd);
 }
@@ -125,7 +127,7 @@ EXPORT_SYMBOL_GPL(kernel_restart);
 static void kernel_shutdown_prepare(enum system_states state)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
 	usermodehelper_disable();
 	device_shutdown();
@@ -140,11 +142,10 @@ void kernel_halt(void)
 	kernel_shutdown_prepare(SYSTEM_HALT);
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
+	pr_emerg("System halted\n");
 	kmsg_dump(KMSG_DUMP_HALT);
 	machine_halt();
 }
-
 EXPORT_SYMBOL_GPL(kernel_halt);
 
 /**
@@ -159,7 +160,7 @@ void kernel_power_off(void)
 		pm_power_off_prepare();
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
+	pr_emerg("Power down\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
 	machine_power_off();
 }
@@ -188,10 +189,10 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 
 	/* For safety, we require "magic" arguments. */
 	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			(magic2 != LINUX_REBOOT_MAGIC2 &&
+			magic2 != LINUX_REBOOT_MAGIC2A &&
 			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
+			magic2 != LINUX_REBOOT_MAGIC2C))
 		return -EINVAL;
 
 	/*
@@ -234,7 +235,8 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 		break;
 
 	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+		ret = strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1);
+		if (ret < 0) {
 			ret = -EFAULT;
 			break;
 		}
@@ -282,7 +284,6 @@ void ctrl_alt_del(void)
 	else
 		kill_cad_pid(SIGINT, 1);
 }
-	
 
 char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
 
@@ -301,14 +302,11 @@ static int __orderly_poweroff(bool force)
 		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
 		argv_free(argv);
 	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
 		ret = -ENOMEM;
 	}
 
 	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
+		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 		/*
 		 * I guess this should try to kick off some daemon to sync and
 		 * poweroff asap.  Or not even bother syncing if we're doing an
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:22 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:22 -0500
Subject: [PATCH -v10 06/11] x86,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-7-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Miguel Boton <mboton.lkml at gmail.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Ingo Molnar <mingo at kernel.org>
---
 arch/x86/kernel/reboot.c | 12 +++++++-----
 include/linux/reboot.h   |  5 +++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 76fa1e9..f770340 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,7 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static int reboot_mode;
+static enum reboot_mode reboot_mode;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -88,11 +88,11 @@ static int __init reboot_setup(char *str)
 
 		switch (*str) {
 		case 'w':
-			reboot_mode = 0x1234;
+			reboot_mode = REBOOT_WARM;
 			break;
 
 		case 'c':
-			reboot_mode = 0;
+			reboot_mode = REBOOT_COLD;
 			break;
 
 #ifdef CONFIG_SMP
@@ -536,6 +536,7 @@ static void native_machine_emergency_restart(void)
 	int i;
 	int attempt = 0;
 	int orig_reboot_type = reboot_type;
+	unsigned short mode;
 
 	if (reboot_emergency)
 		emergency_vmx_disable_all();
@@ -543,7 +544,8 @@ static void native_machine_emergency_restart(void)
 	tboot_shutdown(TB_SHUTDOWN_REBOOT);
 
 	/* Tell the BIOS if we want cold or warm reboot */
-	*((unsigned short *)__va(0x472)) = reboot_mode;
+	mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
+	*((unsigned short *)__va(0x472)) = mode;
 
 	for (;;) {
 		/* Could also try the reset bit in the Hammer NB */
@@ -585,7 +587,7 @@ static void native_machine_emergency_restart(void)
 
 		case BOOT_EFI:
 			if (efi_enabled(EFI_RUNTIME_SERVICES))
-				efi.reset_system(reboot_mode ?
+				efi.reset_system(reboot_mode == REBOOT_WARM ?
 						 EFI_RESET_WARM :
 						 EFI_RESET_COLD,
 						 EFI_SUCCESS, 0, NULL);
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index c6eba21..37d56c3 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -10,6 +10,11 @@
 #define SYS_HALT	0x0002	/* Notify of system halt */
 #define SYS_POWER_OFF	0x0003	/* Notify of system power off */
 
+enum reboot_mode {
+	REBOOT_COLD = 0,
+	REBOOT_WARM,
+};
+
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
 
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:24 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:24 -0500
Subject: [PATCH -v10 08/11] arm,
 Remove unused restart_mode fields from some arm subarchs
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-9-git-send-email-holt@sgi.com>

These restart_mode fields are not used at all.  Remove them to make
moving the reboot= cmdline options to the general kernel easier.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/mach-ebsa110/core.c | 1 -
 arch/arm/mach-pxa/mioa701.c  | 1 -
 arch/arm/mach-pxa/spitz.c    | 3 ---
 arch/arm/mach-pxa/tosa.c     | 1 -
 4 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..69a9d5d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
 	.atag_offset	= 0x400,
 	.reserve_lp0	= 1,
 	.reserve_lp2	= 1,
-	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
 	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b9..dbea67a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -756,7 +756,6 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
 	.map_io		= &pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
 	.init_irq	= &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..c3c0042 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,7 +979,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -993,7 +992,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -1007,7 +1005,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e..a41992f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -969,7 +969,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-	.restart_mode	= 'g',
 	.fixup          = fixup_tosa,
 	.map_io         = pxa25x_map_io,
 	.nr_irqs	= TOSA_NR_IRQS,
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:25 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:25 -0500
Subject: [PATCH -v10 09/11] arm,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-10-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
To: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/arm/include/asm/mach/arch.h   | 3 ++-
 arch/arm/kernel/process.c          | 8 ++++----
 arch/arm/kernel/setup.c            | 6 +++---
 arch/arm/mach-footbridge/cats-hw.c | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..e2b551e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -9,6 +9,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 
 struct tag;
 struct meminfo;
@@ -39,7 +40,7 @@ struct machine_desc {
 	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-	char			restart_mode;	/* default restart mode	*/
+	enum reboot_mode	reboot_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..92b47df 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -174,14 +174,14 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-static char reboot_mode = 'h';
+enum reboot_mode reboot_mode = REBOOT_HARD;
 
-int __init reboot_setup(char *str)
+static int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7a..e05df42 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -73,7 +73,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -769,8 +769,8 @@ void __init setup_arch(char **cmdline_p)
 
 	setup_dma_zone(mdesc);
 
-	if (mdesc->restart_mode)
-		reboot_setup(&mdesc->restart_mode);
+	if (mdesc->reboot_mode != REBOOT_HARD)
+		reboot_mode = mdesc->reboot_mode;
 
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09..9669cc0 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
 	/* Maintainer: Philip Blundell */
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
+	.reboot_mode	= REBOOT_SOFT,
 	.fixup		= fixup_cats,
 	.map_io		= footbridge_map_io,
 	.init_irq	= footbridge_init_irq,
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:27 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:27 -0500
Subject: [PATCH -v10 11/11] Move arch/x86 reboot= handling to generic kernel.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-12-git-send-email-holt@sgi.com>

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Ingo Molnar <mingo at kernel.org>
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>

---
Changes since -v8
 - Add missing break statements.

 - Change parsing so #ifdef's are no longer needed.

 - Switch to using simple_strtoul to make parsing cleaner.

 - Add handling of REBOOT_HARD/SOFT
---
 Documentation/kernel-parameters.txt      |  14 +++-
 arch/arm/kernel/process.c                |  10 ---
 arch/unicore32/kernel/process.c          |  10 ---
 arch/x86/include/asm/emergency-restart.h |  12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |   2 +-
 arch/x86/kernel/reboot.c                 | 111 +------------------------------
 include/linux/reboot.h                   |  17 +++++
 kernel/reboot.c                          |  76 ++++++++++++++++++++-
 8 files changed, 107 insertions(+), 145 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c3bfacb..b2945ce 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2677,9 +2677,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old] | h[ard] | s[oft] | g[pio]] \
+				[[,]s[mp]#### \
+				[[,]b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[[,]f[orce]
+			Where reboot_mode is one of warm (soft) or cold (hard) or gpio,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 42856fc..304b102 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode = REBOOT_HARD;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 93dd035..778ebba 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode = REBOOT_HARD;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index f770340..563ed91 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,22 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode;
-enum reboot_type reboot_type = BOOT_ACPI;
-int reboot_force;
-
-/*
- * This variable is used privately to keep track of whether or not
- * reboot_type is still set to its default value (i.e., reboot= hasn't
- * been set on the command line).  This is needed so that we can
- * suppress DMI scanning for reboot quirks.  Without it, it's
- * impossible to override a faulty reboot quirk without recompiling.
- */
-static int reboot_default = 1;
-
-#ifdef CONFIG_SMP
-static int reboot_cpu = -1;
-#endif
 
 /*
  * This is set if we need to go through the 'emergency' path.
@@ -64,79 +48,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +527,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 5a5d7f7..8e00f9f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -17,6 +17,23 @@ enum reboot_mode {
 	REBOOT_SOFT,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index abb6a04..269ed93 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -24,6 +25,18 @@ int C_A_D = 1;
 struct pid *cad_pid;
 EXPORT_SYMBOL(cad_pid);
 
+#if defined(CONFIG_ARM) || defined(CONFIG_UNICORE32)
+#define DEFAULT_REBOOT_MODE		= REBOOT_HARD
+#else
+#define DEFAULT_REBOOT_MODE
+#endif
+enum reboot_mode reboot_mode DEFAULT_REBOOT_MODE;
+
+int reboot_default;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
 /*
  * If set, this is used for preparing the system to power off.
  */
@@ -87,7 +100,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
+	int cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -343,3 +356,64 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+		case 'h':
+			reboot_mode = REBOOT_HARD;
+			break;
+
+		case 's':
+			if (isdigit(*(str+1)))
+				reboot_cpu = simple_strtoul(str+1, NULL, 0);
+			else if (str[1] == 'm' && str[2] == 'p' &&
+							isdigit(*(str+3)))
+				reboot_cpu = simple_strtoul(str+3, NULL, 0);
+			else
+				reboot_mode = REBOOT_SOFT;
+			break;
+
+		case 'g':
+			reboot_mode = REBOOT_GPIO;
+			break;
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 07:57:26 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 06:57:26 -0500
Subject: [PATCH -v10 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <1368273447-11958-11-git-send-email-holt@sgi.com>

Preparing to move the parsing of reboot= to generic kernel code
forces the change in reboot_mode handling to use the enum.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 arch/arm/include/asm/hardware/iop3xx.h         |  3 ++-
 arch/arm/include/asm/mach/arch.h               |  2 +-
 arch/arm/include/asm/system_misc.h             |  3 ++-
 arch/arm/kernel/process.c                      |  5 +++--
 arch/arm/mach-at91/at91rm9200.c                |  3 ++-
 arch/arm/mach-at91/generic.h                   |  5 +++--
 arch/arm/mach-bcm2835/bcm2835.c                |  4 ++--
 arch/arm/mach-clps711x/common.c                |  2 +-
 arch/arm/mach-clps711x/common.h                |  4 +++-
 arch/arm/mach-cns3xxx/core.h                   |  4 +++-
 arch/arm/mach-cns3xxx/pm.c                     |  2 +-
 arch/arm/mach-davinci/devices-da8xx.c          |  3 ++-
 arch/arm/mach-davinci/devices.c                |  3 ++-
 arch/arm/mach-davinci/include/mach/common.h    |  3 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h     |  3 ++-
 arch/arm/mach-davinci/include/mach/tnetv107x.h |  3 ++-
 arch/arm/mach-davinci/tnetv107x.c              |  3 ++-
 arch/arm/mach-dove/common.c                    |  2 +-
 arch/arm/mach-dove/common.h                    |  4 +++-
 arch/arm/mach-ebsa110/core.c                   |  2 +-
 arch/arm/mach-ep93xx/core.c                    |  3 ++-
 arch/arm/mach-ep93xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-exynos/common.c                  |  4 ++--
 arch/arm/mach-exynos/common.h                  |  5 +++--
 arch/arm/mach-footbridge/common.c              |  4 ++--
 arch/arm/mach-footbridge/common.h              |  3 ++-
 arch/arm/mach-footbridge/netwinder-hw.c        |  4 ++--
 arch/arm/mach-highbank/core.h                  |  4 +++-
 arch/arm/mach-highbank/system.c                |  5 +++--
 arch/arm/mach-imx/common.h                     |  4 +++-
 arch/arm/mach-imx/mach-imx6q.c                 |  3 ++-
 arch/arm/mach-imx/system.c                     |  2 +-
 arch/arm/mach-integrator/common.h              |  3 ++-
 arch/arm/mach-integrator/core.c                |  2 +-
 arch/arm/mach-iop13xx/include/mach/iop13xx.h   |  5 ++++-
 arch/arm/mach-iop13xx/setup.c                  |  2 +-
 arch/arm/mach-iop32x/n2100.c                   |  2 +-
 arch/arm/mach-ixp4xx/common.c                  |  4 ++--
 arch/arm/mach-ixp4xx/dsmg600-setup.c           |  1 +
 arch/arm/mach-ixp4xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-ixp4xx/include/mach/timex.h      |  2 +-
 arch/arm/mach-kirkwood/board-lsxl.c            |  2 +-
 arch/arm/mach-kirkwood/common.c                |  3 ++-
 arch/arm/mach-kirkwood/common.h                |  4 +++-
 arch/arm/mach-ks8695/generic.h                 |  2 +-
 arch/arm/mach-ks8695/time.c                    |  4 ++--
 arch/arm/mach-lpc32xx/common.c                 |  6 +++---
 arch/arm/mach-lpc32xx/common.h                 |  3 ++-
 arch/arm/mach-mmp/common.c                     |  2 +-
 arch/arm/mach-mmp/common.h                     |  3 ++-
 arch/arm/mach-mmp/include/mach/pxa168.h        |  4 +++-
 arch/arm/mach-mmp/pxa168.c                     |  2 +-
 arch/arm/mach-mv78xx0/common.c                 |  2 +-
 arch/arm/mach-mv78xx0/common.h                 |  4 +++-
 arch/arm/mach-mvebu/common.h                   |  4 +++-
 arch/arm/mach-mvebu/system-controller.c        |  3 ++-
 arch/arm/mach-mxs/mach-mxs.c                   |  4 +++-
 arch/arm/mach-netx/generic.c                   |  3 ++-
 arch/arm/mach-netx/generic.h                   |  4 +++-
 arch/arm/mach-nomadik/cpu-8815.c               |  2 +-
 arch/arm/mach-omap1/board-voiceblue.c          |  3 ++-
 arch/arm/mach-omap1/common.h                   |  3 ++-
 arch/arm/mach-omap1/reset.c                    |  3 ++-
 arch/arm/mach-omap2/am33xx-restart.c           |  3 ++-
 arch/arm/mach-omap2/common.h                   | 17 +++++++++--------
 arch/arm/mach-omap2/omap2-restart.c            |  2 +-
 arch/arm/mach-omap2/omap3-restart.c            |  3 ++-
 arch/arm/mach-omap2/omap4-common.c             |  3 ++-
 arch/arm/mach-orion5x/common.c                 |  2 +-
 arch/arm/mach-orion5x/common.h                 |  4 +++-
 arch/arm/mach-orion5x/ls-chl-setup.c           |  2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c           |  2 +-
 arch/arm/mach-orion5x/lsmini-setup.c           |  2 +-
 arch/arm/mach-picoxcell/common.c               |  3 ++-
 arch/arm/mach-prima2/common.h                  |  4 +++-
 arch/arm/mach-prima2/rstc.c                    |  3 ++-
 arch/arm/mach-pxa/corgi.c                      |  6 +++---
 arch/arm/mach-pxa/generic.h                    |  4 +++-
 arch/arm/mach-pxa/mioa701.c                    |  7 ++++---
 arch/arm/mach-pxa/poodle.c                     |  2 +-
 arch/arm/mach-pxa/reset.c                      |  8 ++++----
 arch/arm/mach-pxa/spitz.c                      |  5 +++--
 arch/arm/mach-pxa/tosa.c                       |  5 +++--
 arch/arm/mach-realview/realview_eb.c           |  3 ++-
 arch/arm/mach-realview/realview_pb1176.c       |  3 ++-
 arch/arm/mach-realview/realview_pb11mp.c       |  3 ++-
 arch/arm/mach-realview/realview_pba8.c         |  3 ++-
 arch/arm/mach-realview/realview_pbx.c          |  3 ++-
 arch/arm/mach-rpc/riscpc.c                     |  3 ++-
 arch/arm/mach-s3c24xx/common.h                 | 12 +++++++-----
 arch/arm/mach-s3c24xx/s3c2410.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2412.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2416.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2443.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c244x.c                |  5 +++--
 arch/arm/mach-s3c64xx/common.c                 |  5 +++--
 arch/arm/mach-s3c64xx/common.h                 |  4 +++-
 arch/arm/mach-s5p64x0/common.c                 |  5 +++--
 arch/arm/mach-s5p64x0/common.h                 |  4 +++-
 arch/arm/mach-s5pc100/common.c                 |  5 +++--
 arch/arm/mach-s5pc100/common.h                 |  4 +++-
 arch/arm/mach-s5pv210/common.c                 |  2 +-
 arch/arm/mach-s5pv210/common.h                 |  4 +++-
 arch/arm/mach-sa1100/generic.c                 |  5 +++--
 arch/arm/mach-sa1100/generic.h                 |  3 ++-
 arch/arm/mach-shark/core.c                     |  3 ++-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  3 ++-
 arch/arm/mach-shmobile/board-kzm9g.c           |  3 ++-
 arch/arm/mach-socfpga/socfpga.c                |  3 ++-
 arch/arm/mach-spear/generic.h                  |  4 +++-
 arch/arm/mach-spear/restart.c                  |  5 +++--
 arch/arm/mach-sunxi/sunxi.c                    |  3 ++-
 arch/arm/mach-tegra/board.h                    |  3 ++-
 arch/arm/mach-tegra/common.c                   |  3 ++-
 arch/arm/mach-u300/core.c                      |  6 +++---
 arch/arm/mach-versatile/core.c                 |  3 ++-
 arch/arm/mach-versatile/core.h                 |  3 ++-
 arch/arm/mach-vt8500/vt8500.c                  |  3 ++-
 arch/arm/mach-w90x900/cpu.c                    |  4 ++--
 arch/arm/mach-w90x900/nuc9xx.h                 |  5 ++++-
 arch/arm/plat-iop/gpio.c                       |  1 +
 arch/arm/plat-iop/restart.c                    |  2 +-
 drivers/power/reset/restart-poweroff.c         |  3 ++-
 drivers/power/reset/vexpress-poweroff.c        |  2 +-
 include/linux/reboot.h                         |  1 +
 include/linux/vexpress.h                       |  1 +
 126 files changed, 283 insertions(+), 167 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a..423744b 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e2b551e..2353bc3 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -54,7 +54,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	void			(*handle_irq)(struct pt_regs *);
 #endif
-	void			(*restart)(char, const char *);
+	void			(*restart)(enum reboot_mode, const char *);
 };
 
 /*
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e3..a3d61ad 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED	(1 << 0)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 92b47df..42856fc 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -112,7 +113,7 @@ void soft_restart(unsigned long addr)
 	BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +123,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..f70c239 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -304,7 +305,7 @@ static void at91rm9200_idle(void)
 	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	/*
 	 * Perform a hardware reset with the use of the Watchdog timer.
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..0723ed6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 740fa9e..40686d7 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -53,7 +53,7 @@ static void bcm2835_setup_restart(void)
 	WARN(!wdt_regs, "failed to remap watchdog regs");
 }
 
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 val;
 
@@ -91,7 +91,7 @@ static void bcm2835_power_off(void)
 	writel_relaxed(val, wdt_regs + PM_RSTS);
 
 	/* Continue with normal reset mechanism */
-	bcm2835_restart(0, "");
+	bcm2835_restart(REBOOT_HARD, "");
 }
 
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..54f6a8d 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -345,7 +345,7 @@ void __init clps711x_timer_init(void)
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2da0ff5 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
  * Common bits.
  */
 
+#include <linux/reboot.h>
+
 #define CLPS711X_NR_IRQS	(33)
 #define CLPS711X_NR_GPIO	(4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit)	((prt) * 8 + (bit))
@@ -12,4 +14,4 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b..5218b61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
+#include <linux/reboot.h>
+
 extern void cns3xxx_timer_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 79e3d47..fb38c72 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..c80e189 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
 	.resource	= da8xx_watchdog_resources,
 };
 
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device *dev;
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3..5364f70 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
@@ -303,7 +304,7 @@ struct platform_device davinci_wdt_device = {
 	.resource	= wdt_resources,
 };
 
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
 	davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..cce316b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 extern void davinci_timer_init(void);
 
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..95b76a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,6 +17,7 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
@@ -106,7 +107,7 @@ int __init da850_register_vpif_display
 			(struct vpif_display_config *display_config);
 int __init da850_register_vpif_capture
 			(struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..bc9479d 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -54,7 +55,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d..4545667 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/map.h>
 
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
 	__raw_writel(1, &regs->kick);
 }
 
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
 	tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..cbdb88b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -382,7 +382,7 @@ void __init dove_init(void)
 	dove_xor1_init();
 }
 
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index e863479..1d72522 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 
 #endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 69a9d5d..62b928b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 
 arch_initcall(ebsa110_init);
 
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0x80000000);
 }
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3d..df8612f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
 	gpio_led_register_device(-1, &ep93xx_led_data);
 }
 
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b3..e256e0b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 745e304..e3a2802 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -302,12 +302,12 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
-void exynos4_restart(char mode, const char *cmd)
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	u32 val;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 60dd35c..da1130b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,6 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/reboot.h>
 #include <linux/of.h>
 
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
@@ -22,8 +23,8 @@ struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369..2739ca2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
 	}
 }
 
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50..56607b3 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23f..1fd2cf0 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
 
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206..aea1ec5 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
 
+#include <linux/reboot.h>
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384..2df5870 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
  */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 
 #include "core.h"
 #include "sysregs.h"
 
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 'h')
+	if (mode == REBOOT_HARD)
 		highbank_set_pwr_hard_reset();
 	else
 		highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f..5740795 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct platform_device;
 struct pt_regs;
 struct clk;
@@ -72,7 +74,7 @@ extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..6fdb478 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -26,6 +26,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -66,7 +67,7 @@ static void __init imx6q_init_revision(void)
 	mxc_set_cpu_type(rev >> 16 & 0xff);
 }
 
-static void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..d7ec547 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -34,7 +34,7 @@ static void __iomem *wdog_base;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658b..ad0ac55 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d2..4cdfd73 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
  * To reset, we hit the on-board reset register in the system FPGA
  */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
 	cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58..17b4027 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 
 #ifndef __ASSEMBLY__
+
+#include <linux/reboot.h>
+
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61..97a4906 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -597,7 +597,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a..0691443 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
 		;
 }
 
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
 	gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
 	gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..33e4630 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
 					0xf, 0xfffffffe);
 }
 
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if ( 1 && mode == 's') {
+	if ( 1 && mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8..686ef34 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb6..4c4c6a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 #include <asm/types.h>
 
 #ifndef	__ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index c9e930f..729b2db 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -3,7 +3,7 @@
  * 
  */
 
-#include <mach/hardware.h>
+// #include <mach/hardware.h>
 
 /*
  * We use IXP425 General purpose timer for our timer needs, it runs at 
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..c44f8b2 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -35,7 +35,7 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
  */
 static void lsxl_power_off(void)
 {
-	kirkwood_restart('h', NULL);
+	kirkwood_restart(REBOOT_HARD, NULL);
 }
 
 void __init lsxl_init(void)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c2cae69..f54fdf9 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -729,7 +730,7 @@ void __init kirkwood_init(void)
 #endif
 }
 
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..2a109df 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,7 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 			    int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce4..43253f8 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a386..426c976 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
 	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
 
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	unsigned int reg;
 
-	if (mode == 's')
+	if (reboot_mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c..d7aa54c 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
 	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
 
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 		lpc32xx_watchdog_reset();
 		break;
 
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b2606..1cd8853 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 /*
  * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 
 
 /*
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..c03b4ab 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..991d7e9 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..459c2d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
 
+#include <linux/reboot.h>
+
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3..144e997 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 	return platform_device_register(&pxa168_device_usb_host);
 }
 
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 749a7f8..75062ef 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -413,7 +413,7 @@ void __init mv78xx0_init(void)
 	clk_init();
 }
 
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6889af2 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 
 extern void mv78xx0_timer_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..f7ad45e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,9 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-void mvebu_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df..f875124 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 static void __iomem *system_controller_base;
 
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
 	{ /* end of list */ },
 };
 
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!system_controller_base) {
 		pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..79ddcaf 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -26,6 +26,8 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -390,7 +392,7 @@ static void __init mxs_machine_init(void)
 /*
  * Reset the system. It is called by machine_restart().
  */
-static void mxs_restart(char mode, const char *cmd)
+static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *reset_addr;
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68..db25b0c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 
 subsys_initcall(netx_init);
 
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
 	       NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26b..bb2ce47 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/reboot.h>
+
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..8aec5af 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -148,7 +148,7 @@ static void __init cpu8815_map_io(void)
 	iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
 
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1..4677a9c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
 	gpio_set_value(0, wdt_gpio_state);
 }
 
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e99..abec019 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <plat/i2c.h>
 
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e..72bf4bf 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
 
 
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8..1eae962 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..be9b930 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <asm/proc-fns.h>
 
@@ -118,33 +119,33 @@ static inline void omap_soc_device_init(void)
 #endif
 
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716..68423e2 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
  * Set the DPLL to bypass so that reboot completes successfully.  No
  * return value.
  */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 rate;
 
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582..5de2a0c 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 	omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ff..14c7bad 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -348,7 +349,7 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap44xx_restart(char mode, const char *cmd)
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* XXX Should save 'cmd' into scratchpad for use after reboot */
 	omap4_prminst_global_warm_sw_reset(); /* never returns */
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b97fd67..98dd90c 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -354,7 +354,7 @@ void __init orion5x_init(void)
 	orion5x_wdt_init();
 }
 
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index cdaa01f..a909afb 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -29,7 +31,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 24f4e14..6234977 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 
 static void lschl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fc653bb..fe04c4b 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 
 static void ls_hgl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 18e66e6..ca4dbe9 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..d298ed0 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,6 +15,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
@@ -70,7 +71,7 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Configure the watchdog to reset with the shortest possible timeout
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd..a630485 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..bdf57d4 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -82,7 +83,7 @@ int sirfsoc_reset_device(struct device *dev)
 
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fea..f162f1b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
 		/* Green LED off tells the bootloader to halt */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!machine_is_corgi())
 		/* Green LED on tells the bootloader to reboot */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-	pxa_restart('h', cmd);
+	pxa_restart(REBOOT_HARD, cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39..8963984 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/reboot.h>
+
 struct irq_data;
 
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
 
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dbea67a..76f5e46 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -691,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', NULL);
+	pxa_restart(REBOOT_SOFT, NULL);
 }
 
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', cmd);
+	pxa_restart(REBOOT_SOFT, cmd);
 }
 
 static struct gpio global_gpios[] = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..711d37e 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -422,7 +422,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 
 static void poodle_poweroff(void)
 {
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583..0d5dd64 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
 	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
 	local_irq_disable();
 	local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
 	clear_reset_status(RESET_STATUS_ALL);
 
 	switch (mode) {
-	case 's':
+	case REBOOT_SOFT:
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 		break;
-	case 'g':
+	case REBOOT_GPIO:
 		do_gpio_reset();
 		break;
-	case 'h':
+	case REBOOT_HARD:
 	default:
 		do_hw_reset();
 		break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c3c0042..2125df0 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -924,10 +925,10 @@ static inline void spitz_i2c_init(void) {}
  ******************************************************************************/
 static void spitz_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 	/* Bootloader magic for a reboot */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a41992f..0206b91 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bf..c85ddb2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
 	realview_eb_twd_init();
 }
 
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1..c5eade7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe21..f4b0962 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
 	realview_pb11mp_twd_init();
 }
 
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a..10a3e1d 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185..9d75493 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
 
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5..09d602b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 
 arch_initcall(rpc_init);
 
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
 	iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 307c371..84b2806 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 #ifdef CONFIG_CPU_S3C2410
@@ -20,7 +22,7 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -36,7 +38,7 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -51,7 +53,7 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -66,7 +68,7 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c244x_init_clocks(int xtal);
-extern void s3c244x_restart(char mode, const char *cmd);
+extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
@@ -96,7 +98,7 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5..f68ccf0 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
@@ -195,9 +196,9 @@ int __init s3c2410a_init(void)
 	return s3c2410_init();
 }
 
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		soft_restart(0);
 	}
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0f864d4..0251650 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,9 +130,9 @@ static void s3c2412_idle(void)
 	cpu_do_idle();
 }
 
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index b9c5d38..9ef3ccf 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -79,9 +80,9 @@ static struct device s3c2416_dev = {
 	.bus		= &s3c2416_subsys,
 };
 
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 8328cd6..b6c7191 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,9 +60,9 @@ static struct device s3c2443_dev = {
 	.bus		= &s3c2443_subsys,
 };
 
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb..de88598 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -197,9 +198,9 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
 	.resume		= s3c244x_resume,
 };
 
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	arch_wdt_reset();
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..c13d90d 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,9 +376,9 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
 
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..e8f990b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
 
+#include <linux/reboot.h>
+
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
 
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..5f515e1 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -437,9 +438,9 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
 
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fd..f3a9b43 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5P6440
 
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..e6cc829 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -216,9 +217,9 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index c41f912..08d782d 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
 
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e..023f1a7 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 	}
 };
 
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 0a1cc0ae..fe1beb5 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
 
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98..f25b611 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <video/sa1100fb.h>
 
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
 	PMCR = PMCR_SF;
 }
 
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1..9a33695 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
  *
  * Author: Nicolas Pitre
  */
+#include <linux/reboot.h>
 
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 1535557..1d32c5e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
         short temp;
         /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b288..fde2e4f 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -1277,7 +1278,7 @@ static void __init eva_add_early_devices(void)
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* Do soft power on reset */
 	writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a..2f223f0 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -33,6 +33,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -806,7 +807,7 @@ static void __init kzm_init(void)
 	sh73a0_pm_init();
 }
 
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
 	/* Do soft power on reset */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a0513..0fde6c0 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -90,7 +91,7 @@ static void __init socfpga_init_irq(void)
 	socfpga_sysmgr_init();
 }
 
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 temp;
 
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index a9fd453..904f2c9 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -16,6 +16,8 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/pl08x.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 
 extern void spear13xx_timer_init(void);
@@ -32,7 +34,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
 
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 2b44500..ce5e098 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -12,14 +12,15 @@
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* software reset, Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..f71923b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <linux/clk/sunxi.h>
 
@@ -36,7 +37,7 @@
 
 static void __iomem *wdt_base;
 
-static void sun4i_restart(char mode, const char *cmd)
+static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!wdt_base)
 		return;
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1787327..9a6659f 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 
 void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..2572e73 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip.h>
 #include <linux/clk/tegra.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -67,7 +68,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
 
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
 	u32 reg;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..3e7af05 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -671,11 +671,11 @@ static void __init u300_init_machine(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-static void u300_restart(char mode, const char *cmd)
+static void u300_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 #ifdef CONFIG_COH901327_WATCHDOG
 		coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 54bb80b..3b0572f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif	/* CONFIG_LEDS */
 
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 	u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d..f06d576 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..de2b7eb 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +48,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (pmc_base)
 		writel(1, pmc_base + VT8500_PMSR_REG);
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b..b1eabaa 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define	WTE	(1 << 7)
 #define	WTRE	(1 << 1)
 
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b2..e3ab1e1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
  * published by the Free Software Foundation.
  *
  */
+
+#include <linux/reboot.h>
+
 struct map_desc;
 
 /* core initialisation functions */
 
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be..697de6d 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699..3a4d5e5 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
 
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	*IOP3XX_PCSR = 0x30;
 
diff --git a/drivers/power/reset/restart-poweroff.c b/drivers/power/reset/restart-poweroff.c
index 059cd15..5758033 100644
--- a/drivers/power/reset/restart-poweroff.c
+++ b/drivers/power/reset/restart-poweroff.c
@@ -15,11 +15,12 @@
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 
 static void restart_poweroff_do_poweroff(void)
 {
-	arm_pm_restart('h', NULL);
+	arm_pm_restart(REBOOT_HARD, NULL);
 }
 
 static int restart_poweroff_probe(struct platform_device *pdev)
diff --git a/drivers/power/reset/vexpress-poweroff.c b/drivers/power/reset/vexpress-poweroff.c
index 469e696..476aa49 100644
--- a/drivers/power/reset/vexpress-poweroff.c
+++ b/drivers/power/reset/vexpress-poweroff.c
@@ -48,7 +48,7 @@ static void vexpress_power_off(void)
 
 static struct device *vexpress_restart_device;
 
-static void vexpress_restart(char str, const char *cmd)
+static void vexpress_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	vexpress_reset_do(vexpress_restart_device, "restart");
 }
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index ca29a6f..5a5d7f7 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,7 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_HARD,
 	REBOOT_SOFT,
+	REBOOT_GPIO,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index ea7168a..617c01b 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/reboot.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
-- 
1.8.2.1



From linux at arm.linux.org.uk  Sat May 11 08:27:05 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 13:27:05 +0100
Subject: [PATCH -v10 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1368273447-11958-11-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-11-git-send-email-holt@sgi.com>
Message-ID: <20130511122705.GZ18614@n2100.arm.linux.org.uk>

On Sat, May 11, 2013 at 06:57:26AM -0500, Robin Holt wrote:
> diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
> index c9e930f..729b2db 100644
> --- a/arch/arm/mach-ixp4xx/include/mach/timex.h
> +++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
> @@ -3,7 +3,7 @@
>   * 
>   */
>  
> -#include <mach/hardware.h>
> +// #include <mach/hardware.h>
>  
>  /*
>   * We use IXP425 General purpose timer for our timer needs, it runs at 

Apart from this, everything else here looks fine from a quick scan.
If the above is needed to fix some build error, it should be a separate
patch sent to the arm-soc people.

Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>

Thanks.


From linux at arm.linux.org.uk  Sat May 11 08:27:40 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 13:27:40 +0100
Subject: [PATCH -v10 08/11] arm, Remove unused restart_mode fields from
 some arm subarchs
In-Reply-To: <1368273447-11958-9-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-9-git-send-email-holt@sgi.com>
Message-ID: <20130511122740.GA18614@n2100.arm.linux.org.uk>

On Sat, May 11, 2013 at 06:57:24AM -0500, Robin Holt wrote:
> These restart_mode fields are not used at all.  Remove them to make
> moving the reboot= cmdline options to the general kernel easier.

Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>


From linux at arm.linux.org.uk  Sat May 11 08:28:17 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 13:28:17 +0100
Subject: [PATCH -v10 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <1368273447-11958-12-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-12-git-send-email-holt@sgi.com>
Message-ID: <20130511122817.GB18614@n2100.arm.linux.org.uk>

On Sat, May 11, 2013 at 06:57:27AM -0500, Robin Holt wrote:
> Merge together the unicore32, arm, and x86 reboot= command line
> parameter handling.
> 
> Signed-off-by: Robin Holt <holt at sgi.com>
> To: Andrew Morton <akpm at linux-foundation.org>
> Cc: H. Peter Anvin <hpa at zytor.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
> Cc: Russ Anderson <rja at sgi.com>
> Cc: Robin Holt <holt at sgi.com>
> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
> Cc: the arch/x86 maintainers <x86 at kernel.org>
> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
> Acked-by: Ingo Molnar <mingo at kernel.org>
> Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>

Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>


From linux at arm.linux.org.uk  Sat May 11 08:29:40 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 13:29:40 +0100
Subject: [PATCH -v10 00/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <20130511122939.GC18614@n2100.arm.linux.org.uk>

On Sat, May 11, 2013 at 06:57:16AM -0500, Robin Holt wrote:
> We recently noticed that reboot of a 1024 cpu machine takes approx 16
> minutes of just stopping the cpus.  The slowdown was tracked to commit
> f96972f.
...
> Cc: Russell King <linux at arm.linux.org.uk>

Looks good now.  Acks supplied for relevant patches to ARM.  For the
remainder which will still have a Cc: line like the above, please
change it to use rmk+kernel at arm.linux.org.uk

Thanks.


From holt at sgi.com  Sat May 11 08:49:00 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 07:49:00 -0500
Subject: [PATCH -v10 00/11] Shutdown from reboot_cpuid without stopping
 other cpus.
In-Reply-To: <1368273447-11958-1-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
Message-ID: <20130511124900.GA3672@sgi.com>

I will resubmit a -v11 with Russell's comment about the wrongly added
^// in a bit.

Robin

On Sat, May 11, 2013 at 06:57:16AM -0500, Robin Holt wrote:
> We recently noticed that reboot of a 1024 cpu machine takes approx 16
> minutes of just stopping the cpus.  The slowdown was tracked to commit
> f96972f.
> 
> The current implementation does all the work of hot removing the cpus
> before halting the system.  We are switching to just migrating to the
> reboot_cpu and then continuing with shutdown/reboot.
> 
> The patch set is broken into eleven parts.  The first two are planned for
> the stable release.  The others move the halt/shutdown/reboot related
> functions to their own kernel/reboot.c file and then move the handling
> of the kernel reboot= kernel parameter to generic kernel code.
> 
> Changes since -v9
>  - Added Ingo's Acked-by for x86.
> 
>  - Added Guan's Acked-by for unicore32.
> 
>  - Replaced first patch with updated patch from Srivatsa S. Bhat.
>    This compiles for alpha allmodconfig, all arm defconfigs, and a few
>    test x86_64 defconfigs.  I have not tried more.
> 
> Changes since -v8
>  - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.
> 
>  - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.
> 
>  - Fixed case statement bug.
> 
>  - Went to using simple_strtoul for parsing reboot_cpu=smp###.
> 
>  - Made parsing of reboot= not use any #ifdef'd code.
> 
> Changes since -v7.
>  - Fixed authorship for first patch.
> 
>  - Rebased to Linus' current tree (51a26ae7a).
> 
> Changes since -v6.
>  - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
>    current).
> 
>  - Added a #define for non-hotplug case.
> 
>  - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
> 
>  - Fixup s/reboot_cpu_id/reboot_cpu/
> 
>  - Add include of linux/uaccess.h to allow building on arm.
> 
>  - Removed last remaining checkpatch.pl line length warning on
>    kernel/reboot.c.
> 
>  - Fixed the duplicate handling or the reboot= kernel parameter.
> 
> Changes since -v5.
>  - Moved the arch/x86 reboot= up to the generic kernel code.
> 
> Changes since -v4.
>  - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
>    function
> 
>  - Integrated comments by Srivatsa S. Bhat.
> 
>  - Made one more comment consistent with others in function.
> 
> Changes since -v3.
>  - Added a tested-by for the original reporter.
> 
>  - Fix compile failure found by Joe Perches.
> 
>  - Integrated comments by Joe Perches.
> 
> 
> To: Andrew Morton <akpm at linux-foundation.org>
> Cc: H. Peter Anvin <hpa at zytor.com>
> Cc: Russ Anderson <rja at sgi.com>
> Cc: Robin Holt <holt at sgi.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
> Cc: the arch/x86 maintainers <x86 at kernel.org>
> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


From linux at arm.linux.org.uk  Sat May 11 09:04:57 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 14:04:57 +0100
Subject: [PATCH -v10 09/11] arm, prepare reboot_mode for moving to
 generic kernel code.
In-Reply-To: <1368273447-11958-10-git-send-email-holt@sgi.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-10-git-send-email-holt@sgi.com>
Message-ID: <20130511130457.GD18614@n2100.arm.linux.org.uk>

On Sat, May 11, 2013 at 06:57:25AM -0500, Robin Holt wrote:
> This patch prepares for the moving the parsing of reboot= to the generic
> kernel code by making reboot_mode into a more generic form.
> 
> Signed-off-by: Robin Holt <holt at sgi.com>
> To: Andrew Morton <akpm at linux-foundation.org>
> To: Russell King <linux at arm.linux.org.uk>
> Cc: Russ Anderson <rja at sgi.com>
> Cc: Robin Holt <holt at sgi.com>
> Cc: H. Peter Anvin <hpa at zytor.com>
> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
> Cc: the arch/x86 maintainers <x86 at kernel.org>
> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

Almost-but-not-quite-Acked-by: Russell King <rmk+kernel at arm.linux.org.uk> :)

> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index f219703..92b47df 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -174,14 +174,14 @@ void arch_cpu_idle(void)
>  		default_idle();
>  }
>  
> -static char reboot_mode = 'h';
> +enum reboot_mode reboot_mode = REBOOT_HARD;
>  
> -int __init reboot_setup(char *str)
> +static int __init reboot_setup(char *str)
>  {
> -	reboot_mode = str[0];
> +	if ('s' == str[0])
> +		reboot_mode = REBOOT_SOFT;

Remember we talked about the 'gpio' mode as well, so you also need here
+	if ('g' == str[0])
		reboot_mode = REBOOT_GPIO;


From broonie at kernel.org  Fri May 10 17:24:22 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 10 May 2013 22:24:22 +0100
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <20130510212422.GY3200@sirena.org.uk>

On Fri, May 10, 2013 at 10:31:31AM -0700, Soren Brinkmann wrote:

> +Example:
> +	usclk: usclk {
> +		compatible = "clk-userspace";
> +		clocks = <&foo 15>, <&bar>;
> +		clock-count = <2>;
> +	};

This is clearly *very* Linux specific so needs to be a linux vendor
thing (everything should have a namespaced name anyway).  It's not at
all obvious to me that this should be in device tree, though, since it's
not hardware description but a detail of how the OS is currently
implemented.

For your use case should these things be exposed by the FPGA device
asking for that rather than by having the clocks available separately?
Or is this part of the DT blob that's loaded incrementally along with
the FPGA (which does make things more interesting of course...).

> + * Expose clock controls through sysfs to userspace.

> + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
> + * that file returns the current state - 0 = disabled, 1 = enabled.

> + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
> + * the file requests setting a new frequency in Hz.

This needs to be covered in Documentation/ABI since it's adding new
sysfs stuff.

> +	if (enable)
> +		ret = clk_prepare_enable(pdata->clk);
> +	else
> +		clk_disable_unprepare(pdata->clk);

> +	if (ret)
> +		return -EBUSY;

Why not pass back the actual error?

> +	pdata = kzalloc(clock_count * sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;

devm?

> +late_initcall(usclk_setup);

Why not just a regular driver?
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From holt at sgi.com  Sat May 11 10:19:09 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:09 -0500
Subject: [PATCH -v11 02/11] Migrate shutdown/reboot to boot cpu.
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-3-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
boot cpu and then continuing with shutdown/reboot.

This also has the effect of not breaking x86's command line parameter for
specifying the reboot cpu.  Note, this code was shamelessly copied from
arch/x86/kernel/reboot.c with bits removed pertaining to the reboot_cpu
command line parameter.

Signed-off-by: Robin Holt <holt at sgi.com>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v8
 - Change stack parameter to make future patches cleaner.

Changes since -v6:
 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
 - Fixup s/reboot_cpu_id/reboot_cpu/
---
 kernel/sys.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c7..2bbd9a7 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
 /**
  *	kernel_restart - reboot the system
  *	@cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
 	kernel_restart_prepare(cmd);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
 		printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
 	kernel_shutdown_prepare(SYSTEM_HALT);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
 	if (pm_power_off_prepare)
 		pm_power_off_prepare();
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:07 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:07 -0500
Subject: [PATCH -v11 00/11] Shutdown from reboot_cpuid without stopping other
 cpus.
Message-ID: <1368281958-26695-1-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.

Changes since -v10
 - Added Russell's Acked-by for arm.

 - Fixed an accidentally commented out line in an arm header file.

Changes since -v9
 - Added Ingo's Acked-by for x86.

 - Added Guan's Acked-by for unicore32.

 - Replaced first patch with updated patch from Srivatsa S. Bhat.
   This compiles for alpha allmodconfig, all arm defconfigs, and a few
   test x86_64 defconfigs.  I have not tried more.

Changes since -v8
 - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.

 - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.

 - Fixed case statement bug.

 - Went to using simple_strtoul for parsing reboot_cpu=smp###.

 - Made parsing of reboot= not use any #ifdef'd code.

Changes since -v7.
 - Fixed authorship for first patch.

 - Rebased to Linus' current tree (51a26ae7a).

Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From holt at sgi.com  Sat May 11 10:19:08 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:08 -0500
Subject: [PATCH -v11 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-2-git-send-email-holt@sgi.com>

From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>
---
 include/linux/cpu.h |  4 ++++
 kernel/cpu.c        | 55 ++++++++++++++++++++++-------------------------------
 2 files changed, 27 insertions(+), 32 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..9f3c7e8 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
 
 extern void get_online_cpus(void);
 extern void put_online_cpus(void);
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
@@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
 
 #define get_online_cpus()	do { } while (0)
 #define put_online_cpus()	do { } while (0)
+#define cpu_hotplug_disable()	do { } while (0)
+#define cpu_hotplug_enable()	do { } while (0)
 #define hotcpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 /* These aren't inline functions due to a GCC bug. */
 #define register_hotcpu_notifier(nb)	({ (void)(nb); 0; })
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..198a388 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
 	mutex_unlock(&cpu_hotplug.lock);
 }
 
+/*
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
+ */
+void cpu_hotplug_disable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 1;
+	cpu_maps_update_done();
+}
+
+void cpu_hotplug_enable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 0;
+	cpu_maps_update_done();
+}
+
 #else /* #if CONFIG_HOTPLUG_CPU */
 static void cpu_hotplug_begin(void) {}
 static void cpu_hotplug_done(void) {}
@@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
- */
-void cpu_hotplug_disable_before_freeze(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 1;
-	cpu_maps_update_done();
-}
-
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 0;
-	cpu_maps_update_done();
-}
-
-/*
  * When callbacks for CPU hotplug notifications are being executed, we must
  * ensure that the state of the system with respect to the tasks being frozen
  * or not, as reported by the notification, remains unchanged *throughout the
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:10 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:10 -0500
Subject: [PATCH -v11 03/11] Remove -stable friendly PF_THREAD_BOUND define
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-4-git-send-email-holt@sgi.com>

Remove the prior patch's #define for easier backporting to the stable
releases.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 kernel/sys.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index 2bbd9a7..17bb8d3 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,11 +362,6 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
-/* Add backwards compatibility for stable trees. */
-#ifndef PF_NO_SETAFFINITY
-#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
-#endif
-
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:11 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:11 -0500
Subject: [PATCH -v11 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-5-git-send-email-holt@sgi.com>

This patch is preparatory.  It moves reboot related syscall, etc
functions from kernel/sys.c to kernel/reboot.c.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v6:
 - Add include of linux/uaccess.h to allow building on arm.
---
 kernel/Makefile |   2 +-
 kernel/reboot.c | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/sys.c    | 331 -----------------------------------------------------
 3 files changed, 348 insertions(+), 332 deletions(-)
 create mode 100644 kernel/reboot.c

diff --git a/kernel/Makefile b/kernel/Makefile
index 271fd31..470839d 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y     = fork.o exec_domain.o panic.o printk.o \
 	    rcupdate.o extable.o params.o posix-timers.o \
 	    kthread.o wait.o sys_ni.o posix-cpu-timers.o mutex.o \
 	    hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-	    notifier.o ksysfs.o cred.o \
+	    notifier.o ksysfs.o cred.o reboot.o \
 	    async.o range.o groups.o lglock.o smpboot.o
 
 ifdef CONFIG_FUNCTION_TRACER
diff --git a/kernel/reboot.c b/kernel/reboot.c
new file mode 100644
index 0000000..0616483
--- /dev/null
+++ b/kernel/reboot.c
@@ -0,0 +1,347 @@
+/*
+ *  linux/kernel/reboot.c
+ *
+ *  Copyright (C) 2013  Linus Torvalds
+ */
+
+#include <linux/export.h>
+#include <linux/kexec.h>
+#include <linux/kmod.h>
+#include <linux/kmsg_dump.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h>
+#include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
+
+/*
+ * this indicates whether you can reboot with ctrl-alt-del: the default is yes
+ */
+
+int C_A_D = 1;
+struct pid *cad_pid;
+EXPORT_SYMBOL(cad_pid);
+
+/*
+ * If set, this is used for preparing the system to power off.
+ */
+
+void (*pm_power_off_prepare)(void);
+
+/**
+ *	emergency_restart - reboot the system
+ *
+ *	Without shutting down any hardware or taking any locks
+ *	reboot the system.  This is called when we know we are in
+ *	trouble so this is our best effort to reboot.  This is
+ *	safe to call in interrupt context.
+ */
+void emergency_restart(void)
+{
+	kmsg_dump(KMSG_DUMP_EMERG);
+	machine_emergency_restart();
+}
+EXPORT_SYMBOL_GPL(emergency_restart);
+
+void kernel_restart_prepare(char *cmd)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
+	system_state = SYSTEM_RESTART;
+	usermodehelper_disable();
+	device_shutdown();
+}
+
+/**
+ *	register_reboot_notifier - Register function to be called at reboot time
+ *	@nb: Info about notifier function to be called
+ *
+ *	Registers a function with the list of functions
+ *	to be called at reboot time.
+ *
+ *	Currently always returns zero, as blocking_notifier_chain_register()
+ *	always returns zero.
+ */
+int register_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(register_reboot_notifier);
+
+/**
+ *	unregister_reboot_notifier - Unregister previously registered reboot notifier
+ *	@nb: Hook to be unregistered
+ *
+ *	Unregisters a previously registered reboot
+ *	notifier function.
+ *
+ *	Returns zero on success, or %-ENOENT on failure.
+ */
+int unregister_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(unregister_reboot_notifier);
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
+/**
+ *	kernel_restart - reboot the system
+ *	@cmd: pointer to buffer containing command to execute for restart
+ *		or %NULL
+ *
+ *	Shutdown everything and perform a clean reboot.
+ *	This is not safe to call in interrupt context.
+ */
+void kernel_restart(char *cmd)
+{
+	kernel_restart_prepare(cmd);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	if (!cmd)
+		printk(KERN_EMERG "Restarting system.\n");
+	else
+		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+	kmsg_dump(KMSG_DUMP_RESTART);
+	machine_restart(cmd);
+}
+EXPORT_SYMBOL_GPL(kernel_restart);
+
+static void kernel_shutdown_prepare(enum system_states state)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list,
+		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+	system_state = state;
+	usermodehelper_disable();
+	device_shutdown();
+}
+/**
+ *	kernel_halt - halt the system
+ *
+ *	Shutdown everything and perform a clean system halt.
+ */
+void kernel_halt(void)
+{
+	kernel_shutdown_prepare(SYSTEM_HALT);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "System halted.\n");
+	kmsg_dump(KMSG_DUMP_HALT);
+	machine_halt();
+}
+
+EXPORT_SYMBOL_GPL(kernel_halt);
+
+/**
+ *	kernel_power_off - power_off the system
+ *
+ *	Shutdown everything and perform a clean system power_off.
+ */
+void kernel_power_off(void)
+{
+	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
+	if (pm_power_off_prepare)
+		pm_power_off_prepare();
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "Power down.\n");
+	kmsg_dump(KMSG_DUMP_POWEROFF);
+	machine_power_off();
+}
+EXPORT_SYMBOL_GPL(kernel_power_off);
+
+static DEFINE_MUTEX(reboot_mutex);
+
+/*
+ * Reboot system call: for obvious reasons only root may call it,
+ * and even root needs to set up some magic numbers in the registers
+ * so that some mistake won't make this reboot the whole machine.
+ * You can also set the meaning of the ctrl-alt-del-key here.
+ *
+ * reboot doesn't sync: do that yourself before calling this.
+ */
+SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
+		void __user *, arg)
+{
+	struct pid_namespace *pid_ns = task_active_pid_ns(current);
+	char buffer[256];
+	int ret = 0;
+
+	/* We only trust the superuser with rebooting the system. */
+	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
+		return -EPERM;
+
+	/* For safety, we require "magic" arguments. */
+	if (magic1 != LINUX_REBOOT_MAGIC1 ||
+	    (magic2 != LINUX_REBOOT_MAGIC2 &&
+	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			magic2 != LINUX_REBOOT_MAGIC2B &&
+	                magic2 != LINUX_REBOOT_MAGIC2C))
+		return -EINVAL;
+
+	/*
+	 * If pid namespaces are enabled and the current task is in a child
+	 * pid_namespace, the command is handled by reboot_pid_ns() which will
+	 * call do_exit().
+	 */
+	ret = reboot_pid_ns(pid_ns, cmd);
+	if (ret)
+		return ret;
+
+	/* Instead of trying to make the power_off code look like
+	 * halt when pm_power_off is not set do it the easy way.
+	 */
+	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
+		cmd = LINUX_REBOOT_CMD_HALT;
+
+	mutex_lock(&reboot_mutex);
+	switch (cmd) {
+	case LINUX_REBOOT_CMD_RESTART:
+		kernel_restart(NULL);
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_ON:
+		C_A_D = 1;
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_OFF:
+		C_A_D = 0;
+		break;
+
+	case LINUX_REBOOT_CMD_HALT:
+		kernel_halt();
+		do_exit(0);
+		panic("cannot halt");
+
+	case LINUX_REBOOT_CMD_POWER_OFF:
+		kernel_power_off();
+		do_exit(0);
+		break;
+
+	case LINUX_REBOOT_CMD_RESTART2:
+		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+			ret = -EFAULT;
+			break;
+		}
+		buffer[sizeof(buffer) - 1] = '\0';
+
+		kernel_restart(buffer);
+		break;
+
+#ifdef CONFIG_KEXEC
+	case LINUX_REBOOT_CMD_KEXEC:
+		ret = kernel_kexec();
+		break;
+#endif
+
+#ifdef CONFIG_HIBERNATION
+	case LINUX_REBOOT_CMD_SW_SUSPEND:
+		ret = hibernate();
+		break;
+#endif
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&reboot_mutex);
+	return ret;
+}
+
+static void deferred_cad(struct work_struct *dummy)
+{
+	kernel_restart(NULL);
+}
+
+/*
+ * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
+ * As it's called within an interrupt, it may NOT sync: the only choice
+ * is whether to reboot at once, or just ignore the ctrl-alt-del.
+ */
+void ctrl_alt_del(void)
+{
+	static DECLARE_WORK(cad_work, deferred_cad);
+
+	if (C_A_D)
+		schedule_work(&cad_work);
+	else
+		kill_cad_pid(SIGINT, 1);
+}
+	
+
+char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
+
+static int __orderly_poweroff(bool force)
+{
+	char **argv;
+	static char *envp[] = {
+		"HOME=/",
+		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
+		NULL
+	};
+	int ret;
+
+	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
+	if (argv) {
+		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
+		argv_free(argv);
+	} else {
+		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
+					 __func__, poweroff_cmd);
+		ret = -ENOMEM;
+	}
+
+	if (ret && force) {
+		printk(KERN_WARNING "Failed to start orderly shutdown: "
+					"forcing the issue\n");
+		/*
+		 * I guess this should try to kick off some daemon to sync and
+		 * poweroff asap.  Or not even bother syncing if we're doing an
+		 * emergency shutdown?
+		 */
+		emergency_sync();
+		kernel_power_off();
+	}
+
+	return ret;
+}
+
+static bool poweroff_force;
+
+static void poweroff_work_func(struct work_struct *work)
+{
+	__orderly_poweroff(poweroff_force);
+}
+
+static DECLARE_WORK(poweroff_work, poweroff_work_func);
+
+/**
+ * orderly_poweroff - Trigger an orderly system poweroff
+ * @force: force poweroff if command execution fails
+ *
+ * This may be called from any context to trigger a system shutdown.
+ * If the orderly shutdown fails, it will force an immediate shutdown.
+ */
+int orderly_poweroff(bool force)
+{
+	if (force) /* do not override the pending "true" */
+		poweroff_force = true;
+	schedule_work(&poweroff_work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(orderly_poweroff);
diff --git a/kernel/sys.c b/kernel/sys.c
index 17bb8d3..467a18f 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -116,20 +116,6 @@ EXPORT_SYMBOL(fs_overflowuid);
 EXPORT_SYMBOL(fs_overflowgid);
 
 /*
- * this indicates whether you can reboot with ctrl-alt-del: the default is yes
- */
-
-int C_A_D = 1;
-struct pid *cad_pid;
-EXPORT_SYMBOL(cad_pid);
-
-/*
- * If set, this is used for preparing the system to power off.
- */
-
-void (*pm_power_off_prepare)(void);
-
-/*
  * Returns true if current's euid is same as p's uid or euid,
  * or has CAP_SYS_NICE to p's user_ns.
  *
@@ -308,261 +294,6 @@ out_unlock:
 	return retval;
 }
 
-/**
- *	emergency_restart - reboot the system
- *
- *	Without shutting down any hardware or taking any locks
- *	reboot the system.  This is called when we know we are in
- *	trouble so this is our best effort to reboot.  This is
- *	safe to call in interrupt context.
- */
-void emergency_restart(void)
-{
-	kmsg_dump(KMSG_DUMP_EMERG);
-	machine_emergency_restart();
-}
-EXPORT_SYMBOL_GPL(emergency_restart);
-
-void kernel_restart_prepare(char *cmd)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
-	system_state = SYSTEM_RESTART;
-	usermodehelper_disable();
-	device_shutdown();
-}
-
-/**
- *	register_reboot_notifier - Register function to be called at reboot time
- *	@nb: Info about notifier function to be called
- *
- *	Registers a function with the list of functions
- *	to be called at reboot time.
- *
- *	Currently always returns zero, as blocking_notifier_chain_register()
- *	always returns zero.
- */
-int register_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(register_reboot_notifier);
-
-/**
- *	unregister_reboot_notifier - Unregister previously registered reboot notifier
- *	@nb: Hook to be unregistered
- *
- *	Unregisters a previously registered reboot
- *	notifier function.
- *
- *	Returns zero on success, or %-ENOENT on failure.
- */
-int unregister_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(unregister_reboot_notifier);
-
-static void migrate_to_reboot_cpu(void)
-{
-	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
-
-	cpu_hotplug_disable();
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(cpu))
-		cpu = cpumask_first(cpu_online_mask);
-
-	/* Prevent races with other tasks migrating this task */
-	current->flags |= PF_NO_SETAFFINITY;
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(cpu));
-}
-
-/**
- *	kernel_restart - reboot the system
- *	@cmd: pointer to buffer containing command to execute for restart
- *		or %NULL
- *
- *	Shutdown everything and perform a clean reboot.
- *	This is not safe to call in interrupt context.
- */
-void kernel_restart(char *cmd)
-{
-	kernel_restart_prepare(cmd);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
-	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
-	kmsg_dump(KMSG_DUMP_RESTART);
-	machine_restart(cmd);
-}
-EXPORT_SYMBOL_GPL(kernel_restart);
-
-static void kernel_shutdown_prepare(enum system_states state)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
-	system_state = state;
-	usermodehelper_disable();
-	device_shutdown();
-}
-/**
- *	kernel_halt - halt the system
- *
- *	Shutdown everything and perform a clean system halt.
- */
-void kernel_halt(void)
-{
-	kernel_shutdown_prepare(SYSTEM_HALT);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
-	kmsg_dump(KMSG_DUMP_HALT);
-	machine_halt();
-}
-
-EXPORT_SYMBOL_GPL(kernel_halt);
-
-/**
- *	kernel_power_off - power_off the system
- *
- *	Shutdown everything and perform a clean system power_off.
- */
-void kernel_power_off(void)
-{
-	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
-	if (pm_power_off_prepare)
-		pm_power_off_prepare();
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
-	kmsg_dump(KMSG_DUMP_POWEROFF);
-	machine_power_off();
-}
-EXPORT_SYMBOL_GPL(kernel_power_off);
-
-static DEFINE_MUTEX(reboot_mutex);
-
-/*
- * Reboot system call: for obvious reasons only root may call it,
- * and even root needs to set up some magic numbers in the registers
- * so that some mistake won't make this reboot the whole machine.
- * You can also set the meaning of the ctrl-alt-del-key here.
- *
- * reboot doesn't sync: do that yourself before calling this.
- */
-SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
-		void __user *, arg)
-{
-	struct pid_namespace *pid_ns = task_active_pid_ns(current);
-	char buffer[256];
-	int ret = 0;
-
-	/* We only trust the superuser with rebooting the system. */
-	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
-		return -EPERM;
-
-	/* For safety, we require "magic" arguments. */
-	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
-			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
-		return -EINVAL;
-
-	/*
-	 * If pid namespaces are enabled and the current task is in a child
-	 * pid_namespace, the command is handled by reboot_pid_ns() which will
-	 * call do_exit().
-	 */
-	ret = reboot_pid_ns(pid_ns, cmd);
-	if (ret)
-		return ret;
-
-	/* Instead of trying to make the power_off code look like
-	 * halt when pm_power_off is not set do it the easy way.
-	 */
-	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
-		cmd = LINUX_REBOOT_CMD_HALT;
-
-	mutex_lock(&reboot_mutex);
-	switch (cmd) {
-	case LINUX_REBOOT_CMD_RESTART:
-		kernel_restart(NULL);
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_ON:
-		C_A_D = 1;
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_OFF:
-		C_A_D = 0;
-		break;
-
-	case LINUX_REBOOT_CMD_HALT:
-		kernel_halt();
-		do_exit(0);
-		panic("cannot halt");
-
-	case LINUX_REBOOT_CMD_POWER_OFF:
-		kernel_power_off();
-		do_exit(0);
-		break;
-
-	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
-			ret = -EFAULT;
-			break;
-		}
-		buffer[sizeof(buffer) - 1] = '\0';
-
-		kernel_restart(buffer);
-		break;
-
-#ifdef CONFIG_KEXEC
-	case LINUX_REBOOT_CMD_KEXEC:
-		ret = kernel_kexec();
-		break;
-#endif
-
-#ifdef CONFIG_HIBERNATION
-	case LINUX_REBOOT_CMD_SW_SUSPEND:
-		ret = hibernate();
-		break;
-#endif
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	mutex_unlock(&reboot_mutex);
-	return ret;
-}
-
-static void deferred_cad(struct work_struct *dummy)
-{
-	kernel_restart(NULL);
-}
-
-/*
- * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
- * As it's called within an interrupt, it may NOT sync: the only choice
- * is whether to reboot at once, or just ignore the ctrl-alt-del.
- */
-void ctrl_alt_del(void)
-{
-	static DECLARE_WORK(cad_work, deferred_cad);
-
-	if (C_A_D)
-		schedule_work(&cad_work);
-	else
-		kill_cad_pid(SIGINT, 1);
-}
-	
 /*
  * Unprivileged users may change the real gid to the effective gid
  * or vice versa.  (BSD-style)
@@ -2276,68 +2007,6 @@ SYSCALL_DEFINE3(getcpu, unsigned __user *, cpup, unsigned __user *, nodep,
 	return err ? -EFAULT : 0;
 }
 
-char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
-
-static int __orderly_poweroff(bool force)
-{
-	char **argv;
-	static char *envp[] = {
-		"HOME=/",
-		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
-		NULL
-	};
-	int ret;
-
-	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
-	if (argv) {
-		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
-		argv_free(argv);
-	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
-		ret = -ENOMEM;
-	}
-
-	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
-		/*
-		 * I guess this should try to kick off some daemon to sync and
-		 * poweroff asap.  Or not even bother syncing if we're doing an
-		 * emergency shutdown?
-		 */
-		emergency_sync();
-		kernel_power_off();
-	}
-
-	return ret;
-}
-
-static bool poweroff_force;
-
-static void poweroff_work_func(struct work_struct *work)
-{
-	__orderly_poweroff(poweroff_force);
-}
-
-static DECLARE_WORK(poweroff_work, poweroff_work_func);
-
-/**
- * orderly_poweroff - Trigger an orderly system poweroff
- * @force: force poweroff if command execution fails
- *
- * This may be called from any context to trigger a system shutdown.
- * If the orderly shutdown fails, it will force an immediate shutdown.
- */
-int orderly_poweroff(bool force)
-{
-	if (force) /* do not override the pending "true" */
-		poweroff_force = true;
-	schedule_work(&poweroff_work);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(orderly_poweroff);
-
 /**
  * do_sysinfo - fill in sysinfo struct
  * @info: pointer to buffer to fill
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:13 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:13 -0500
Subject: [PATCH -v11 06/11] x86,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-7-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Miguel Boton <mboton.lkml at gmail.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Ingo Molnar <mingo at kernel.org>
---
 arch/x86/kernel/reboot.c | 12 +++++++-----
 include/linux/reboot.h   |  5 +++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 76fa1e9..f770340 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,7 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static int reboot_mode;
+static enum reboot_mode reboot_mode;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -88,11 +88,11 @@ static int __init reboot_setup(char *str)
 
 		switch (*str) {
 		case 'w':
-			reboot_mode = 0x1234;
+			reboot_mode = REBOOT_WARM;
 			break;
 
 		case 'c':
-			reboot_mode = 0;
+			reboot_mode = REBOOT_COLD;
 			break;
 
 #ifdef CONFIG_SMP
@@ -536,6 +536,7 @@ static void native_machine_emergency_restart(void)
 	int i;
 	int attempt = 0;
 	int orig_reboot_type = reboot_type;
+	unsigned short mode;
 
 	if (reboot_emergency)
 		emergency_vmx_disable_all();
@@ -543,7 +544,8 @@ static void native_machine_emergency_restart(void)
 	tboot_shutdown(TB_SHUTDOWN_REBOOT);
 
 	/* Tell the BIOS if we want cold or warm reboot */
-	*((unsigned short *)__va(0x472)) = reboot_mode;
+	mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
+	*((unsigned short *)__va(0x472)) = mode;
 
 	for (;;) {
 		/* Could also try the reset bit in the Hammer NB */
@@ -585,7 +587,7 @@ static void native_machine_emergency_restart(void)
 
 		case BOOT_EFI:
 			if (efi_enabled(EFI_RUNTIME_SERVICES))
-				efi.reset_system(reboot_mode ?
+				efi.reset_system(reboot_mode == REBOOT_WARM ?
 						 EFI_RESET_WARM :
 						 EFI_RESET_COLD,
 						 EFI_SUCCESS, 0, NULL);
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index c6eba21..37d56c3 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -10,6 +10,11 @@
 #define SYS_HALT	0x0002	/* Notify of system halt */
 #define SYS_POWER_OFF	0x0003	/* Notify of system power off */
 
+enum reboot_mode {
+	REBOOT_COLD = 0,
+	REBOOT_WARM,
+};
+
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
 
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:14 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:14 -0500
Subject: [PATCH -v11 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-8-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>
---

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/unicore32/kernel/process.c | 10 +++++-----
 arch/unicore32/kernel/setup.h   |  2 +-
 arch/unicore32/mm/mmu.c         |  2 +-
 include/linux/reboot.h          |  2 ++
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index c944769..93dd035 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,14 +51,14 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static char reboot_mode = 'h';
+static enum reboot_mode reboot_mode = REBOOT_HARD;
 
 int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
@@ -88,7 +88,7 @@ void machine_restart(char *cmd)
 	 * we may need it to insert some 1:1 mappings so that
 	 * soft boot works.
 	 */
-	setup_mm_for_reboot(reboot_mode);
+	setup_mm_for_reboot();
 
 	/* Clean and invalidate caches */
 	flush_cache_all();
@@ -102,7 +102,7 @@ void machine_restart(char *cmd)
 	/*
 	 * Now handle reboot code.
 	 */
-	if (reboot_mode == 's') {
+	if (reboot_mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index 30f749d..f5c51b8 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
 extern void pci_puv3_preinit(void);
 extern void __init puv3_init_gpio(void);
 
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 
 extern char __stubs_start[], __stubs_end[];
 extern char __vectors_start[], __vectors_end[];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index 43c20b4..4f5a532 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -445,7 +445,7 @@ void __init paging_init(void)
  * the user-mode pages.  This will then ensure that we have predictable
  * results when turning the mmu off
  */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 	unsigned long base_pmdval;
 	pgd_t *pgd;
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 37d56c3..ca29a6f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -13,6 +13,8 @@
 enum reboot_mode {
 	REBOOT_COLD = 0,
 	REBOOT_WARM,
+	REBOOT_HARD,
+	REBOOT_SOFT,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:15 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:15 -0500
Subject: [PATCH -v11 08/11] arm,
 Remove unused restart_mode fields from some arm subarchs
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-9-git-send-email-holt@sgi.com>

These restart_mode fields are not used at all.  Remove them to make
moving the reboot= cmdline options to the general kernel easier.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/mach-ebsa110/core.c | 1 -
 arch/arm/mach-pxa/mioa701.c  | 1 -
 arch/arm/mach-pxa/spitz.c    | 3 ---
 arch/arm/mach-pxa/tosa.c     | 1 -
 4 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..69a9d5d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
 	.atag_offset	= 0x400,
 	.reserve_lp0	= 1,
 	.reserve_lp2	= 1,
-	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
 	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b9..dbea67a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -756,7 +756,6 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
 	.map_io		= &pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
 	.init_irq	= &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..c3c0042 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,7 +979,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -993,7 +992,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -1007,7 +1005,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e..a41992f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -969,7 +969,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-	.restart_mode	= 'g',
 	.fixup          = fixup_tosa,
 	.map_io         = pxa25x_map_io,
 	.nr_irqs	= TOSA_NR_IRQS,
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:16 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:16 -0500
Subject: [PATCH -v11 09/11] arm,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-10-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>

---

Changes since -v10
 - Uncommented an accidentally commented out line.

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/arm/include/asm/mach/arch.h   | 3 ++-
 arch/arm/kernel/process.c          | 8 ++++----
 arch/arm/kernel/setup.c            | 6 +++---
 arch/arm/mach-footbridge/cats-hw.c | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..e2b551e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -9,6 +9,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 
 struct tag;
 struct meminfo;
@@ -39,7 +40,7 @@ struct machine_desc {
 	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-	char			restart_mode;	/* default restart mode	*/
+	enum reboot_mode	reboot_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..92b47df 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -174,14 +174,14 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-static char reboot_mode = 'h';
+enum reboot_mode reboot_mode = REBOOT_HARD;
 
-int __init reboot_setup(char *str)
+static int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7a..e05df42 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -73,7 +73,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -769,8 +769,8 @@ void __init setup_arch(char **cmdline_p)
 
 	setup_dma_zone(mdesc);
 
-	if (mdesc->restart_mode)
-		reboot_setup(&mdesc->restart_mode);
+	if (mdesc->reboot_mode != REBOOT_HARD)
+		reboot_mode = mdesc->reboot_mode;
 
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09..9669cc0 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
 	/* Maintainer: Philip Blundell */
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
+	.reboot_mode	= REBOOT_SOFT,
 	.fixup		= fixup_cats,
 	.map_io		= footbridge_map_io,
 	.init_irq	= footbridge_init_irq,
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:12 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:12 -0500
Subject: [PATCH -v11 05/11] checkpatch.pl the new kernel/reboot.c file.
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-6-git-send-email-holt@sgi.com>

Get the new file to pass scripts/checkpatch.pl

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since v6:
 - Removed last remaining line length warning.
---
 include/linux/reboot.h |  2 +-
 kernel/reboot.c        | 28 +++++++++++++---------------
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 23b3630..c6eba21 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -26,7 +26,7 @@ extern void machine_shutdown(void);
 struct pt_regs;
 extern void machine_crash_shutdown(struct pt_regs *);
 
-/* 
+/*
  * Architecture independent implemenations of sys_reboot commands.
  */
 
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 0616483..abb6a04 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -4,6 +4,8 @@
  *  Copyright (C) 2013  Linus Torvalds
  */
 
+#define pr_fmt(fmt)	"reboot: " fmt
+
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -114,9 +116,9 @@ void kernel_restart(char *cmd)
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
+		pr_emerg("Restarting system\n");
 	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+		pr_emerg("Restarting system with command '%s'\n", cmd);
 	kmsg_dump(KMSG_DUMP_RESTART);
 	machine_restart(cmd);
 }
@@ -125,7 +127,7 @@ EXPORT_SYMBOL_GPL(kernel_restart);
 static void kernel_shutdown_prepare(enum system_states state)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
 	usermodehelper_disable();
 	device_shutdown();
@@ -140,11 +142,10 @@ void kernel_halt(void)
 	kernel_shutdown_prepare(SYSTEM_HALT);
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
+	pr_emerg("System halted\n");
 	kmsg_dump(KMSG_DUMP_HALT);
 	machine_halt();
 }
-
 EXPORT_SYMBOL_GPL(kernel_halt);
 
 /**
@@ -159,7 +160,7 @@ void kernel_power_off(void)
 		pm_power_off_prepare();
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
+	pr_emerg("Power down\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
 	machine_power_off();
 }
@@ -188,10 +189,10 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 
 	/* For safety, we require "magic" arguments. */
 	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			(magic2 != LINUX_REBOOT_MAGIC2 &&
+			magic2 != LINUX_REBOOT_MAGIC2A &&
 			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
+			magic2 != LINUX_REBOOT_MAGIC2C))
 		return -EINVAL;
 
 	/*
@@ -234,7 +235,8 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 		break;
 
 	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+		ret = strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1);
+		if (ret < 0) {
 			ret = -EFAULT;
 			break;
 		}
@@ -282,7 +284,6 @@ void ctrl_alt_del(void)
 	else
 		kill_cad_pid(SIGINT, 1);
 }
-	
 
 char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
 
@@ -301,14 +302,11 @@ static int __orderly_poweroff(bool force)
 		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
 		argv_free(argv);
 	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
 		ret = -ENOMEM;
 	}
 
 	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
+		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 		/*
 		 * I guess this should try to kick off some daemon to sync and
 		 * poweroff asap.  Or not even bother syncing if we're doing an
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:18 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:18 -0500
Subject: [PATCH -v11 11/11] Move arch/x86 reboot= handling to generic kernel.
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-12-git-send-email-holt@sgi.com>

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Ingo Molnar <mingo at kernel.org>
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>

---
Changes since -v8
 - Add missing break statements.

 - Change parsing so #ifdef's are no longer needed.

 - Switch to using simple_strtoul to make parsing cleaner.

 - Add handling of REBOOT_HARD/SOFT
---
 Documentation/kernel-parameters.txt      |  14 +++-
 arch/arm/kernel/process.c                |  10 ---
 arch/unicore32/kernel/process.c          |  10 ---
 arch/x86/include/asm/emergency-restart.h |  12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |   2 +-
 arch/x86/kernel/reboot.c                 | 111 +------------------------------
 include/linux/reboot.h                   |  17 +++++
 kernel/reboot.c                          |  76 ++++++++++++++++++++-
 8 files changed, 107 insertions(+), 145 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c3bfacb..b2945ce 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2677,9 +2677,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old] | h[ard] | s[oft] | g[pio]] \
+				[[,]s[mp]#### \
+				[[,]b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[[,]f[orce]
+			Where reboot_mode is one of warm (soft) or cold (hard) or gpio,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 42856fc..304b102 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode = REBOOT_HARD;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 93dd035..778ebba 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode = REBOOT_HARD;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index f770340..563ed91 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,22 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode;
-enum reboot_type reboot_type = BOOT_ACPI;
-int reboot_force;
-
-/*
- * This variable is used privately to keep track of whether or not
- * reboot_type is still set to its default value (i.e., reboot= hasn't
- * been set on the command line).  This is needed so that we can
- * suppress DMI scanning for reboot quirks.  Without it, it's
- * impossible to override a faulty reboot quirk without recompiling.
- */
-static int reboot_default = 1;
-
-#ifdef CONFIG_SMP
-static int reboot_cpu = -1;
-#endif
 
 /*
  * This is set if we need to go through the 'emergency' path.
@@ -64,79 +48,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +527,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 5a5d7f7..8e00f9f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -17,6 +17,23 @@ enum reboot_mode {
 	REBOOT_SOFT,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index abb6a04..269ed93 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -24,6 +25,18 @@ int C_A_D = 1;
 struct pid *cad_pid;
 EXPORT_SYMBOL(cad_pid);
 
+#if defined(CONFIG_ARM) || defined(CONFIG_UNICORE32)
+#define DEFAULT_REBOOT_MODE		= REBOOT_HARD
+#else
+#define DEFAULT_REBOOT_MODE
+#endif
+enum reboot_mode reboot_mode DEFAULT_REBOOT_MODE;
+
+int reboot_default;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
 /*
  * If set, this is used for preparing the system to power off.
  */
@@ -87,7 +100,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
+	int cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -343,3 +356,64 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+		case 'h':
+			reboot_mode = REBOOT_HARD;
+			break;
+
+		case 's':
+			if (isdigit(*(str+1)))
+				reboot_cpu = simple_strtoul(str+1, NULL, 0);
+			else if (str[1] == 'm' && str[2] == 'p' &&
+							isdigit(*(str+3)))
+				reboot_cpu = simple_strtoul(str+3, NULL, 0);
+			else
+				reboot_mode = REBOOT_SOFT;
+			break;
+
+		case 'g':
+			reboot_mode = REBOOT_GPIO;
+			break;
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From holt at sgi.com  Sat May 11 10:19:17 2013
From: holt at sgi.com (Robin Holt)
Date: Sat, 11 May 2013 09:19:17 -0500
Subject: [PATCH -v11 10/11] arm, change reboot_mode to use enum reboot_mode
In-Reply-To: <1368281958-26695-1-git-send-email-holt@sgi.com>
References: <1368281958-26695-1-git-send-email-holt@sgi.com>
Message-ID: <1368281958-26695-11-git-send-email-holt@sgi.com>

Preparing to move the parsing of reboot= to generic kernel code
forces the change in reboot_mode handling to use the enum.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/include/asm/hardware/iop3xx.h         |  3 ++-
 arch/arm/include/asm/mach/arch.h               |  2 +-
 arch/arm/include/asm/system_misc.h             |  3 ++-
 arch/arm/kernel/process.c                      |  5 +++--
 arch/arm/mach-at91/at91rm9200.c                |  3 ++-
 arch/arm/mach-at91/generic.h                   |  5 +++--
 arch/arm/mach-bcm2835/bcm2835.c                |  4 ++--
 arch/arm/mach-clps711x/common.c                |  2 +-
 arch/arm/mach-clps711x/common.h                |  4 +++-
 arch/arm/mach-cns3xxx/core.h                   |  4 +++-
 arch/arm/mach-cns3xxx/pm.c                     |  2 +-
 arch/arm/mach-davinci/devices-da8xx.c          |  3 ++-
 arch/arm/mach-davinci/devices.c                |  3 ++-
 arch/arm/mach-davinci/include/mach/common.h    |  3 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h     |  3 ++-
 arch/arm/mach-davinci/include/mach/tnetv107x.h |  3 ++-
 arch/arm/mach-davinci/tnetv107x.c              |  3 ++-
 arch/arm/mach-dove/common.c                    |  2 +-
 arch/arm/mach-dove/common.h                    |  4 +++-
 arch/arm/mach-ebsa110/core.c                   |  2 +-
 arch/arm/mach-ep93xx/core.c                    |  3 ++-
 arch/arm/mach-ep93xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-exynos/common.c                  |  4 ++--
 arch/arm/mach-exynos/common.h                  |  5 +++--
 arch/arm/mach-footbridge/common.c              |  4 ++--
 arch/arm/mach-footbridge/common.h              |  3 ++-
 arch/arm/mach-footbridge/netwinder-hw.c        |  4 ++--
 arch/arm/mach-highbank/core.h                  |  4 +++-
 arch/arm/mach-highbank/system.c                |  5 +++--
 arch/arm/mach-imx/common.h                     |  4 +++-
 arch/arm/mach-imx/mach-imx6q.c                 |  3 ++-
 arch/arm/mach-imx/system.c                     |  2 +-
 arch/arm/mach-integrator/common.h              |  3 ++-
 arch/arm/mach-integrator/core.c                |  2 +-
 arch/arm/mach-iop13xx/include/mach/iop13xx.h   |  5 ++++-
 arch/arm/mach-iop13xx/setup.c                  |  2 +-
 arch/arm/mach-iop32x/n2100.c                   |  2 +-
 arch/arm/mach-ixp4xx/common.c                  |  4 ++--
 arch/arm/mach-ixp4xx/dsmg600-setup.c           |  1 +
 arch/arm/mach-ixp4xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-kirkwood/board-lsxl.c            |  2 +-
 arch/arm/mach-kirkwood/common.c                |  3 ++-
 arch/arm/mach-kirkwood/common.h                |  4 +++-
 arch/arm/mach-ks8695/generic.h                 |  2 +-
 arch/arm/mach-ks8695/time.c                    |  4 ++--
 arch/arm/mach-lpc32xx/common.c                 |  6 +++---
 arch/arm/mach-lpc32xx/common.h                 |  3 ++-
 arch/arm/mach-mmp/common.c                     |  2 +-
 arch/arm/mach-mmp/common.h                     |  3 ++-
 arch/arm/mach-mmp/include/mach/pxa168.h        |  4 +++-
 arch/arm/mach-mmp/pxa168.c                     |  2 +-
 arch/arm/mach-mv78xx0/common.c                 |  2 +-
 arch/arm/mach-mv78xx0/common.h                 |  4 +++-
 arch/arm/mach-mvebu/common.h                   |  4 +++-
 arch/arm/mach-mvebu/system-controller.c        |  3 ++-
 arch/arm/mach-mxs/mach-mxs.c                   |  4 +++-
 arch/arm/mach-netx/generic.c                   |  3 ++-
 arch/arm/mach-netx/generic.h                   |  4 +++-
 arch/arm/mach-nomadik/cpu-8815.c               |  2 +-
 arch/arm/mach-omap1/board-voiceblue.c          |  3 ++-
 arch/arm/mach-omap1/common.h                   |  3 ++-
 arch/arm/mach-omap1/reset.c                    |  3 ++-
 arch/arm/mach-omap2/am33xx-restart.c           |  3 ++-
 arch/arm/mach-omap2/common.h                   | 17 +++++++++--------
 arch/arm/mach-omap2/omap2-restart.c            |  2 +-
 arch/arm/mach-omap2/omap3-restart.c            |  3 ++-
 arch/arm/mach-omap2/omap4-common.c             |  3 ++-
 arch/arm/mach-orion5x/common.c                 |  2 +-
 arch/arm/mach-orion5x/common.h                 |  4 +++-
 arch/arm/mach-orion5x/ls-chl-setup.c           |  2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c           |  2 +-
 arch/arm/mach-orion5x/lsmini-setup.c           |  2 +-
 arch/arm/mach-picoxcell/common.c               |  3 ++-
 arch/arm/mach-prima2/common.h                  |  4 +++-
 arch/arm/mach-prima2/rstc.c                    |  3 ++-
 arch/arm/mach-pxa/corgi.c                      |  6 +++---
 arch/arm/mach-pxa/generic.h                    |  4 +++-
 arch/arm/mach-pxa/mioa701.c                    |  7 ++++---
 arch/arm/mach-pxa/poodle.c                     |  2 +-
 arch/arm/mach-pxa/reset.c                      |  8 ++++----
 arch/arm/mach-pxa/spitz.c                      |  5 +++--
 arch/arm/mach-pxa/tosa.c                       |  5 +++--
 arch/arm/mach-realview/realview_eb.c           |  3 ++-
 arch/arm/mach-realview/realview_pb1176.c       |  3 ++-
 arch/arm/mach-realview/realview_pb11mp.c       |  3 ++-
 arch/arm/mach-realview/realview_pba8.c         |  3 ++-
 arch/arm/mach-realview/realview_pbx.c          |  3 ++-
 arch/arm/mach-rpc/riscpc.c                     |  3 ++-
 arch/arm/mach-s3c24xx/common.h                 | 12 +++++++-----
 arch/arm/mach-s3c24xx/s3c2410.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2412.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2416.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2443.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c244x.c                |  5 +++--
 arch/arm/mach-s3c64xx/common.c                 |  5 +++--
 arch/arm/mach-s3c64xx/common.h                 |  4 +++-
 arch/arm/mach-s5p64x0/common.c                 |  5 +++--
 arch/arm/mach-s5p64x0/common.h                 |  4 +++-
 arch/arm/mach-s5pc100/common.c                 |  5 +++--
 arch/arm/mach-s5pc100/common.h                 |  4 +++-
 arch/arm/mach-s5pv210/common.c                 |  2 +-
 arch/arm/mach-s5pv210/common.h                 |  4 +++-
 arch/arm/mach-sa1100/generic.c                 |  5 +++--
 arch/arm/mach-sa1100/generic.h                 |  3 ++-
 arch/arm/mach-shark/core.c                     |  3 ++-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  3 ++-
 arch/arm/mach-shmobile/board-kzm9g.c           |  3 ++-
 arch/arm/mach-socfpga/socfpga.c                |  3 ++-
 arch/arm/mach-spear/generic.h                  |  4 +++-
 arch/arm/mach-spear/restart.c                  |  5 +++--
 arch/arm/mach-sunxi/sunxi.c                    |  3 ++-
 arch/arm/mach-tegra/board.h                    |  3 ++-
 arch/arm/mach-tegra/common.c                   |  3 ++-
 arch/arm/mach-u300/core.c                      |  6 +++---
 arch/arm/mach-versatile/core.c                 |  3 ++-
 arch/arm/mach-versatile/core.h                 |  3 ++-
 arch/arm/mach-vt8500/vt8500.c                  |  3 ++-
 arch/arm/mach-w90x900/cpu.c                    |  4 ++--
 arch/arm/mach-w90x900/nuc9xx.h                 |  5 ++++-
 arch/arm/plat-iop/gpio.c                       |  1 +
 arch/arm/plat-iop/restart.c                    |  2 +-
 drivers/power/reset/restart-poweroff.c         |  3 ++-
 drivers/power/reset/vexpress-poweroff.c        |  2 +-
 include/linux/reboot.h                         |  1 +
 include/linux/vexpress.h                       |  1 +
 125 files changed, 282 insertions(+), 166 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a..423744b 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e2b551e..2353bc3 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -54,7 +54,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	void			(*handle_irq)(struct pt_regs *);
 #endif
-	void			(*restart)(char, const char *);
+	void			(*restart)(enum reboot_mode, const char *);
 };
 
 /*
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e3..a3d61ad 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED	(1 << 0)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 92b47df..42856fc 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -112,7 +113,7 @@ void soft_restart(unsigned long addr)
 	BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +123,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..f70c239 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -304,7 +305,7 @@ static void at91rm9200_idle(void)
 	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	/*
 	 * Perform a hardware reset with the use of the Watchdog timer.
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..0723ed6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 740fa9e..40686d7 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -53,7 +53,7 @@ static void bcm2835_setup_restart(void)
 	WARN(!wdt_regs, "failed to remap watchdog regs");
 }
 
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 val;
 
@@ -91,7 +91,7 @@ static void bcm2835_power_off(void)
 	writel_relaxed(val, wdt_regs + PM_RSTS);
 
 	/* Continue with normal reset mechanism */
-	bcm2835_restart(0, "");
+	bcm2835_restart(REBOOT_HARD, "");
 }
 
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..54f6a8d 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -345,7 +345,7 @@ void __init clps711x_timer_init(void)
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2da0ff5 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
  * Common bits.
  */
 
+#include <linux/reboot.h>
+
 #define CLPS711X_NR_IRQS	(33)
 #define CLPS711X_NR_GPIO	(4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit)	((prt) * 8 + (bit))
@@ -12,4 +14,4 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b..5218b61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
+#include <linux/reboot.h>
+
 extern void cns3xxx_timer_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 79e3d47..fb38c72 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..c80e189 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
 	.resource	= da8xx_watchdog_resources,
 };
 
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device *dev;
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3..5364f70 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
@@ -303,7 +304,7 @@ struct platform_device davinci_wdt_device = {
 	.resource	= wdt_resources,
 };
 
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
 	davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..cce316b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 extern void davinci_timer_init(void);
 
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..95b76a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,6 +17,7 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
@@ -106,7 +107,7 @@ int __init da850_register_vpif_display
 			(struct vpif_display_config *display_config);
 int __init da850_register_vpif_capture
 			(struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..bc9479d 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -54,7 +55,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d..4545667 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/map.h>
 
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
 	__raw_writel(1, &regs->kick);
 }
 
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
 	tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..cbdb88b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -382,7 +382,7 @@ void __init dove_init(void)
 	dove_xor1_init();
 }
 
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index e863479..1d72522 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 
 #endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 69a9d5d..62b928b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 
 arch_initcall(ebsa110_init);
 
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0x80000000);
 }
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3d..df8612f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
 	gpio_led_register_device(-1, &ep93xx_led_data);
 }
 
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b3..e256e0b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 745e304..e3a2802 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -302,12 +302,12 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
-void exynos4_restart(char mode, const char *cmd)
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	u32 val;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 60dd35c..da1130b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,6 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/reboot.h>
 #include <linux/of.h>
 
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
@@ -22,8 +23,8 @@ struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369..2739ca2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
 	}
 }
 
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50..56607b3 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23f..1fd2cf0 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
 
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206..aea1ec5 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
 
+#include <linux/reboot.h>
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384..2df5870 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
  */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 
 #include "core.h"
 #include "sysregs.h"
 
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 'h')
+	if (mode == REBOOT_HARD)
 		highbank_set_pwr_hard_reset();
 	else
 		highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f..5740795 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct platform_device;
 struct pt_regs;
 struct clk;
@@ -72,7 +74,7 @@ extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..6fdb478 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -26,6 +26,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -66,7 +67,7 @@ static void __init imx6q_init_revision(void)
 	mxc_set_cpu_type(rev >> 16 & 0xff);
 }
 
-static void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..d7ec547 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -34,7 +34,7 @@ static void __iomem *wdog_base;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658b..ad0ac55 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d2..4cdfd73 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
  * To reset, we hit the on-board reset register in the system FPGA
  */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
 	cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58..17b4027 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 
 #ifndef __ASSEMBLY__
+
+#include <linux/reboot.h>
+
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61..97a4906 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -597,7 +597,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a..0691443 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
 		;
 }
 
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
 	gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
 	gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..33e4630 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
 					0xf, 0xfffffffe);
 }
 
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if ( 1 && mode == 's') {
+	if ( 1 && mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8..686ef34 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb6..4c4c6a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 #include <asm/types.h>
 
 #ifndef	__ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..c44f8b2 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -35,7 +35,7 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
  */
 static void lsxl_power_off(void)
 {
-	kirkwood_restart('h', NULL);
+	kirkwood_restart(REBOOT_HARD, NULL);
 }
 
 void __init lsxl_init(void)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c2cae69..f54fdf9 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -729,7 +730,7 @@ void __init kirkwood_init(void)
 #endif
 }
 
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..2a109df 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,7 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 			    int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce4..43253f8 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a386..426c976 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
 	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
 
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	unsigned int reg;
 
-	if (mode == 's')
+	if (reboot_mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c..d7aa54c 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
 	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
 
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 		lpc32xx_watchdog_reset();
 		break;
 
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b2606..1cd8853 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 /*
  * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 
 
 /*
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..c03b4ab 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..991d7e9 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..459c2d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
 
+#include <linux/reboot.h>
+
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3..144e997 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 	return platform_device_register(&pxa168_device_usb_host);
 }
 
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 749a7f8..75062ef 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -413,7 +413,7 @@ void __init mv78xx0_init(void)
 	clk_init();
 }
 
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6889af2 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 
 extern void mv78xx0_timer_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..f7ad45e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,9 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-void mvebu_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df..f875124 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 static void __iomem *system_controller_base;
 
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
 	{ /* end of list */ },
 };
 
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!system_controller_base) {
 		pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..79ddcaf 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -26,6 +26,8 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -390,7 +392,7 @@ static void __init mxs_machine_init(void)
 /*
  * Reset the system. It is called by machine_restart().
  */
-static void mxs_restart(char mode, const char *cmd)
+static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *reset_addr;
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68..db25b0c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 
 subsys_initcall(netx_init);
 
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
 	       NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26b..bb2ce47 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/reboot.h>
+
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..8aec5af 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -148,7 +148,7 @@ static void __init cpu8815_map_io(void)
 	iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
 
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1..4677a9c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
 	gpio_set_value(0, wdt_gpio_state);
 }
 
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e99..abec019 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <plat/i2c.h>
 
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e..72bf4bf 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
 
 
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8..1eae962 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..be9b930 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <asm/proc-fns.h>
 
@@ -118,33 +119,33 @@ static inline void omap_soc_device_init(void)
 #endif
 
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716..68423e2 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
  * Set the DPLL to bypass so that reboot completes successfully.  No
  * return value.
  */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 rate;
 
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582..5de2a0c 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 	omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ff..14c7bad 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -348,7 +349,7 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap44xx_restart(char mode, const char *cmd)
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* XXX Should save 'cmd' into scratchpad for use after reboot */
 	omap4_prminst_global_warm_sw_reset(); /* never returns */
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b97fd67..98dd90c 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -354,7 +354,7 @@ void __init orion5x_init(void)
 	orion5x_wdt_init();
 }
 
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index cdaa01f..a909afb 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -29,7 +31,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 24f4e14..6234977 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 
 static void lschl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fc653bb..fe04c4b 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 
 static void ls_hgl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 18e66e6..ca4dbe9 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..d298ed0 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,6 +15,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
@@ -70,7 +71,7 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Configure the watchdog to reset with the shortest possible timeout
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd..a630485 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..bdf57d4 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -82,7 +83,7 @@ int sirfsoc_reset_device(struct device *dev)
 
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fea..f162f1b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
 		/* Green LED off tells the bootloader to halt */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!machine_is_corgi())
 		/* Green LED on tells the bootloader to reboot */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-	pxa_restart('h', cmd);
+	pxa_restart(REBOOT_HARD, cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39..8963984 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/reboot.h>
+
 struct irq_data;
 
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
 
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dbea67a..76f5e46 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -691,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', NULL);
+	pxa_restart(REBOOT_SOFT, NULL);
 }
 
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', cmd);
+	pxa_restart(REBOOT_SOFT, cmd);
 }
 
 static struct gpio global_gpios[] = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..711d37e 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -422,7 +422,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 
 static void poodle_poweroff(void)
 {
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583..0d5dd64 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
 	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
 	local_irq_disable();
 	local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
 	clear_reset_status(RESET_STATUS_ALL);
 
 	switch (mode) {
-	case 's':
+	case REBOOT_SOFT:
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 		break;
-	case 'g':
+	case REBOOT_GPIO:
 		do_gpio_reset();
 		break;
-	case 'h':
+	case REBOOT_HARD:
 	default:
 		do_hw_reset();
 		break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c3c0042..2125df0 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -924,10 +925,10 @@ static inline void spitz_i2c_init(void) {}
  ******************************************************************************/
 static void spitz_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 	/* Bootloader magic for a reboot */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a41992f..0206b91 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bf..c85ddb2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
 	realview_eb_twd_init();
 }
 
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1..c5eade7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe21..f4b0962 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
 	realview_pb11mp_twd_init();
 }
 
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a..10a3e1d 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185..9d75493 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
 
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5..09d602b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 
 arch_initcall(rpc_init);
 
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
 	iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 307c371..84b2806 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 #ifdef CONFIG_CPU_S3C2410
@@ -20,7 +22,7 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -36,7 +38,7 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -51,7 +53,7 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -66,7 +68,7 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c244x_init_clocks(int xtal);
-extern void s3c244x_restart(char mode, const char *cmd);
+extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
@@ -96,7 +98,7 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5..f68ccf0 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
@@ -195,9 +196,9 @@ int __init s3c2410a_init(void)
 	return s3c2410_init();
 }
 
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		soft_restart(0);
 	}
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0f864d4..0251650 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,9 +130,9 @@ static void s3c2412_idle(void)
 	cpu_do_idle();
 }
 
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index b9c5d38..9ef3ccf 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -79,9 +80,9 @@ static struct device s3c2416_dev = {
 	.bus		= &s3c2416_subsys,
 };
 
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 8328cd6..b6c7191 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,9 +60,9 @@ static struct device s3c2443_dev = {
 	.bus		= &s3c2443_subsys,
 };
 
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb..de88598 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -197,9 +198,9 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
 	.resume		= s3c244x_resume,
 };
 
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	arch_wdt_reset();
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..c13d90d 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,9 +376,9 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
 
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..e8f990b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
 
+#include <linux/reboot.h>
+
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
 
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..5f515e1 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -437,9 +438,9 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
 
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fd..f3a9b43 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5P6440
 
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..e6cc829 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -216,9 +217,9 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index c41f912..08d782d 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
 
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e..023f1a7 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 	}
 };
 
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 0a1cc0ae..fe1beb5 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
 
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98..f25b611 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <video/sa1100fb.h>
 
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
 	PMCR = PMCR_SF;
 }
 
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1..9a33695 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
  *
  * Author: Nicolas Pitre
  */
+#include <linux/reboot.h>
 
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 1535557..1d32c5e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
         short temp;
         /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b288..fde2e4f 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -1277,7 +1278,7 @@ static void __init eva_add_early_devices(void)
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* Do soft power on reset */
 	writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a..2f223f0 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -33,6 +33,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -806,7 +807,7 @@ static void __init kzm_init(void)
 	sh73a0_pm_init();
 }
 
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
 	/* Do soft power on reset */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a0513..0fde6c0 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -90,7 +91,7 @@ static void __init socfpga_init_irq(void)
 	socfpga_sysmgr_init();
 }
 
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 temp;
 
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index a9fd453..904f2c9 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -16,6 +16,8 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/pl08x.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 
 extern void spear13xx_timer_init(void);
@@ -32,7 +34,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
 
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 2b44500..ce5e098 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -12,14 +12,15 @@
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* software reset, Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..f71923b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <linux/clk/sunxi.h>
 
@@ -36,7 +37,7 @@
 
 static void __iomem *wdt_base;
 
-static void sun4i_restart(char mode, const char *cmd)
+static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!wdt_base)
 		return;
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1787327..9a6659f 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 
 void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..2572e73 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip.h>
 #include <linux/clk/tegra.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -67,7 +68,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
 
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
 	u32 reg;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..3e7af05 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -671,11 +671,11 @@ static void __init u300_init_machine(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-static void u300_restart(char mode, const char *cmd)
+static void u300_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 #ifdef CONFIG_COH901327_WATCHDOG
 		coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 54bb80b..3b0572f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif	/* CONFIG_LEDS */
 
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 	u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d..f06d576 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..de2b7eb 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +48,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (pmc_base)
 		writel(1, pmc_base + VT8500_PMSR_REG);
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b..b1eabaa 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define	WTE	(1 << 7)
 #define	WTRE	(1 << 1)
 
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b2..e3ab1e1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
  * published by the Free Software Foundation.
  *
  */
+
+#include <linux/reboot.h>
+
 struct map_desc;
 
 /* core initialisation functions */
 
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be..697de6d 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699..3a4d5e5 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
 
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	*IOP3XX_PCSR = 0x30;
 
diff --git a/drivers/power/reset/restart-poweroff.c b/drivers/power/reset/restart-poweroff.c
index 059cd15..5758033 100644
--- a/drivers/power/reset/restart-poweroff.c
+++ b/drivers/power/reset/restart-poweroff.c
@@ -15,11 +15,12 @@
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 
 static void restart_poweroff_do_poweroff(void)
 {
-	arm_pm_restart('h', NULL);
+	arm_pm_restart(REBOOT_HARD, NULL);
 }
 
 static int restart_poweroff_probe(struct platform_device *pdev)
diff --git a/drivers/power/reset/vexpress-poweroff.c b/drivers/power/reset/vexpress-poweroff.c
index 469e696..476aa49 100644
--- a/drivers/power/reset/vexpress-poweroff.c
+++ b/drivers/power/reset/vexpress-poweroff.c
@@ -48,7 +48,7 @@ static void vexpress_power_off(void)
 
 static struct device *vexpress_restart_device;
 
-static void vexpress_restart(char str, const char *cmd)
+static void vexpress_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	vexpress_reset_do(vexpress_restart_device, "restart");
 }
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index ca29a6f..5a5d7f7 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,7 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_HARD,
 	REBOOT_SOFT,
+	REBOOT_GPIO,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index ea7168a..617c01b 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/reboot.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
-- 
1.8.2.1



From broonie at kernel.org  Sat May 11 10:21:32 2013
From: broonie at kernel.org (Mark Brown)
Date: Sat, 11 May 2013 18:21:32 +0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <518D7C45.2090602@codeaurora.org>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
 <518D7C45.2090602@codeaurora.org>
Message-ID: <20130511142132.GA3200@sirena.org.uk>

On Fri, May 10, 2013 at 04:01:25PM -0700, Saravana Kannan wrote:
> On 05/10/2013 03:18 PM, Mike Turquette wrote:

Guys please delete irrelevant context from replies...

> >One way to do it is to introduce a new config option,
> >CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
> >every clock in the existing debugfs infrastructure.  The downside to
> >this approach is that it would get abused and ship in millions of
> >Android products using horrible userspace hacks to control clocks.
> >Maybe that's not our problem to solve, maybe it is.

> We already have this for MSM. But I seem to have managed to keep our
> userspace guys away from abusing it. YMMV.

It's much harder when it's in the standard kernel and there's no contact
with some of the users.  I've pushed back pretty strongly on some of
your equivalent stuff for regulators for this reason.

> >I think that Soren wants something with a stable interface that he can
> >use for his Zynq use case.  Regarding that, why not write an actual
> >device driver to do what you want to do from userspace?

> Exposing clock control to userspace production use is a terrible
> idea. A misbehaving userspace can easily kill the system. This is
> not so try for GPIO. So, exposing GPIOs to userspace is relatively
> less of a concern.

Pick the wrong GPIO and you face the same issue.

Note that we do have a UIO framework in place so there is some concept
of doing this sort of thing; that is all about picking specific things
and exposing them (in a somewhat similar fashion to this) rather than a
default available thing though.
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From heiko at sntech.de  Sat May 11 11:26:49 2013
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Sat, 11 May 2013 17:26:49 +0200
Subject: [PATCH v5] pinctrl: Add pinctrl-s3c24xx driver
In-Reply-To: <046401ce4d15$ccba0c80$662e2580$%kim@samsung.com>
References: <201305031552.45410.heiko@sntech.de>
 <046401ce4d15$ccba0c80$662e2580$%kim@samsung.com>
Message-ID: <201305111726.49491.heiko@sntech.de>

Am Freitag, 10. Mai 2013, 02:32:05 schrieb Kukjin Kim:
> Heiko St?bner wrote:
> > The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
> > can therefore reuse the already introduced infrastructure.
> > 
> > The s3c24xx SoCs have one design oddity in that the first 4 external
> > interrupts do not reside in the eint pending register but in the main
> > interrupt controller instead. We solve this by forwarding the external
> > interrupt from the main controller into the irq domain of the pin bank.
> > The masking/acking of these interrupts is handled in the same way.
> > 
> > Furthermore the S3C2412/2413 SoCs contain another oddity in that they
> > keep the same 4 eints in the main interrupt controller and eintpend
> > register and requiring ack operations to happen in both. This is solved
> > by using different compatible properties for the wakeup eint node which
> > set a property accordingly.
> > 
> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> > Reviewed-by: Tomasz Figa <t.figa at samsung.com>
> > Reviewed-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Looks good to me.
> 
> Linus, if you want me to take into samsung tree, please let me know.

in v4 Linus said:

"Are you taking this through the Samsung tree?"

This would also enable me to put the s3c2416 devicetree support on top of it 
in this cycle, which of course needs the pinctrl driver.


Heiko


From kgene.kim at samsung.com  Sat May 11 11:28:50 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 12 May 2013 00:28:50 +0900
Subject: [PATCH v5] pinctrl: Add pinctrl-s3c24xx driver
In-Reply-To: <201305111726.49491.heiko@sntech.de>
References: <201305031552.45410.heiko@sntech.de>
 <046401ce4d15$ccba0c80$662e2580$%kim@samsung.com>
 <201305111726.49491.heiko@sntech.de>
Message-ID: <067401ce4e5c$3cee48d0$b6cada70$%kim@samsung.com>

Heiko St?bner wrote:
> 
> Am Freitag, 10. Mai 2013, 02:32:05 schrieb Kukjin Kim:
> > Heiko St?bner wrote:
> > > The s3c24xx pins follow a similar pattern as the other Samsung SoCs
> and
> > > can therefore reuse the already introduced infrastructure.
> > >
> > > The s3c24xx SoCs have one design oddity in that the first 4 external
> > > interrupts do not reside in the eint pending register but in the main
> > > interrupt controller instead. We solve this by forwarding the external
> > > interrupt from the main controller into the irq domain of the pin bank.
> > > The masking/acking of these interrupts is handled in the same way.
> > >
> > > Furthermore the S3C2412/2413 SoCs contain another oddity in that they
> > > keep the same 4 eints in the main interrupt controller and eintpend
> > > register and requiring ack operations to happen in both. This is
> solved
> > > by using different compatible properties for the wakeup eint node
> which
> > > set a property accordingly.
> > >
> > > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> > > Reviewed-by: Tomasz Figa <t.figa at samsung.com>
> > > Reviewed-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
> > > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> >
> > Looks good to me.
> >
> > Linus, if you want me to take into samsung tree, please let me know.
> 
> in v4 Linus said:
> 
> "Are you taking this through the Samsung tree?"
> 
> This would also enable me to put the s3c2416 devicetree support on top of
> it
> in this cycle, which of course needs the pinctrl driver.
> 
OK, will apply into samsung tree.

Thanks.

- Kukjin



From hpa at zytor.com  Sat May 11 11:47:28 2013
From: hpa at zytor.com (H. Peter Anvin)
Date: Sat, 11 May 2013 08:47:28 -0700
Subject: [PATCH -v10 09/11] arm,
 prepare reboot_mode for moving to	generic kernel code.
In-Reply-To: <20130511130457.GD18614@n2100.arm.linux.org.uk>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-10-git-send-email-holt@sgi.com>
 <20130511130457.GD18614@n2100.arm.linux.org.uk>
Message-ID: <588ed084-fed7-4bd9-bcd7-a32f40bd404a@email.android.com>

By the way, do we really need Yoda programming here?

Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

>On Sat, May 11, 2013 at 06:57:25AM -0500, Robin Holt wrote:
>> This patch prepares for the moving the parsing of reboot= to the
>generic
>> kernel code by making reboot_mode into a more generic form.
>> 
>> Signed-off-by: Robin Holt <holt at sgi.com>
>> To: Andrew Morton <akpm at linux-foundation.org>
>> To: Russell King <linux at arm.linux.org.uk>
>> Cc: Russ Anderson <rja at sgi.com>
>> Cc: Robin Holt <holt at sgi.com>
>> Cc: H. Peter Anvin <hpa at zytor.com>
>> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
>> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
>> Cc: the arch/x86 maintainers <x86 at kernel.org>
>> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
>
>Almost-but-not-quite-Acked-by: Russell King
><rmk+kernel at arm.linux.org.uk> :)
>
>> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
>> index f219703..92b47df 100644
>> --- a/arch/arm/kernel/process.c
>> +++ b/arch/arm/kernel/process.c
>> @@ -174,14 +174,14 @@ void arch_cpu_idle(void)
>>  		default_idle();
>>  }
>>  
>> -static char reboot_mode = 'h';
>> +enum reboot_mode reboot_mode = REBOOT_HARD;
>>  
>> -int __init reboot_setup(char *str)
>> +static int __init reboot_setup(char *str)
>>  {
>> -	reboot_mode = str[0];
>> +	if ('s' == str[0])
>> +		reboot_mode = REBOOT_SOFT;
>
>Remember we talked about the 'gpio' mode as well, so you also need here
>+	if ('g' == str[0])
>		reboot_mode = REBOOT_GPIO;

-- 
Sent from my mobile phone. Please excuse brevity and lack of formatting.


From cdall at cs.columbia.edu  Sat May 11 12:26:02 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sat, 11 May 2013 09:26:02 -0700
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <CAFEAcA-8cHk9Gv5j8XvK9dfkpZJeZ+hNfc4NekKCW_KBeHttKg@mail.gmail.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com> <5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
 <51892DA4.4050401@arm.com> <20130511003842.GE30999@chazy>
 <CAFEAcA-8cHk9Gv5j8XvK9dfkpZJeZ+hNfc4NekKCW_KBeHttKg@mail.gmail.com>
Message-ID: <CAEDV+gKJg9r+fwiqRAKrQdMVooXCUfKMdog-xveLnBkOgE+YUQ@mail.gmail.com>

On Sat, May 11, 2013 at 1:04 AM, Peter Maydell <peter.maydell at linaro.org> wrote:
> On 11 May 2013 01:38, Christoffer Dall <cdall at cs.columbia.edu> wrote:
>> On Tue, May 07, 2013 at 05:36:52PM +0100, Marc Zyngier wrote:
>>> Here's what the documentation says:
>>> <quote>
>>> 4.77 KVM_ARM_VCPU_INIT
>>>
>>> Capability: basic
>>> Architectures: arm, arm64
>>> Type: vcpu ioctl
>>> Parameters: struct struct kvm_vcpu_init (in)
>>> Returns: 0 on success; -1 on error
>>> Errors:
>>>   EINVAL:    the target is unknown, or the combination of features is invalid.
>>>   ENOENT:    a features bit specified is unknown.
>>> </quote>
>>>
>>> When this call fails, it is because you've requested a feature
>>> that is invalid for this CPU. To me, that exactly fits the
>>> EINVAL entry copied above.
>>>
>>> Or am I completely misunderstanding it?
>>>
>> I read the EINVAL to say that you supplied something which is invalid
>> for the software interface and you should fix your user space code.
>
> Well, more likely "tell the user they picked a bad feature combo";
> I doubt userspace is going to bother specifically trying to track
> which features don't go together when we can get a reliable answer
> just by asking the kernel.
>
>> The fact that you're requesting a feature that your hardware doesn't
>> support is a different thing IMHO.
>
> My reading of the docs above would be that "ENOENT" is "I have
> no idea what feature you just asked me for" and "EINVAL" is
> "I know those features but can't do them". That said, we don't
> actually do anything with the error return yet so we should
> feel free to clarify things so that it's clear what error is
> returned for the cases we care about distinguishing. It seems
> like it would be useful to have separate errors for:
>  * the kernel doesn't support this CPU
>  * the kernel doesn't support this feature bit
>  * the combination of CPU and features doesn't make sense
>
> and at the moment we've shoehorned two of those into one
> errno, hence the confusion.
>
> (do we need to distinguish "I know about but don't support X"
> from "I have no idea what you mean when you say X" ?)
>
I just think that saying "EINVAL: Invalid argument" for a perfectly
valid argument which is just not supported on this hardware is what's
wrong, I think ENXIO or ENODEV or whatever is more appropriate of
this.

-Christoffer


From peter.maydell at linaro.org  Sat May 11 12:31:32 2013
From: peter.maydell at linaro.org (Peter Maydell)
Date: Sat, 11 May 2013 17:31:32 +0100
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <CAEDV+gKJg9r+fwiqRAKrQdMVooXCUfKMdog-xveLnBkOgE+YUQ@mail.gmail.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com> <5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
 <51892DA4.4050401@arm.com> <20130511003842.GE30999@chazy>
 <CAFEAcA-8cHk9Gv5j8XvK9dfkpZJeZ+hNfc4NekKCW_KBeHttKg@mail.gmail.com>
 <CAEDV+gKJg9r+fwiqRAKrQdMVooXCUfKMdog-xveLnBkOgE+YUQ@mail.gmail.com>
Message-ID: <CAFEAcA-GvE_r-Pk-9uYQEK48ZZAxmvhFewPLYS9cDfnnC==x=Q@mail.gmail.com>

On 11 May 2013 17:26, Christoffer Dall <cdall at cs.columbia.edu> wrote:
> I just think that saying "EINVAL: Invalid argument" for a perfectly
> valid argument which is just not supported on this hardware is what's
> wrong, I think ENXIO or ENODEV or whatever is more appropriate of
> this.

That's fine with me. I don't mind as long as we document what
errnos we're using and (ideally) cleanly separate the different
things we're trying to report. At the moment QEMU doesn't try to
do anything clever with the errno at all anyway...

-- PMM


From soren.brinkmann at xilinx.com  Sat May 11 12:54:22 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Sat, 11 May 2013 09:54:22 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130510212422.GY3200@sirena.org.uk>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
Message-ID: <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>

On Fri, May 10, 2013 at 10:24:22PM +0100, Mark Brown wrote:
> On Fri, May 10, 2013 at 10:31:31AM -0700, Soren Brinkmann wrote:
> 
> > +Example:
> > +	usclk: usclk {
> > +		compatible = "clk-userspace";
> > +		clocks = <&foo 15>, <&bar>;
> > +		clock-count = <2>;
> > +	};
> 
> This is clearly *very* Linux specific so needs to be a linux vendor
> thing (everything should have a namespaced name anyway).  It's not at
> all obvious to me that this should be in device tree, though, since it's
> not hardware description but a detail of how the OS is currently
> implemented.
> 
> For your use case should these things be exposed by the FPGA device
> asking for that rather than by having the clocks available separately?
> Or is this part of the DT blob that's loaded incrementally along with
> the FPGA (which does make things more interesting of course...).
Here may be some misunderstanding.
The clocks are not in the FPGA. The clocks are always there and part of
the processing system (PS), they are just routed to the FPGA where they
can be used as clocks for the FPGA design.

So, hopefully, in most cases there will be a "normal" device drivers for the
IP in the FPGA. E.g. if there is a soft IP Ethernet core in the FPGA an
appropriate device driver will use clk_get() to claim the appropriate
clock from its provider, which can be one of these FPGA clocks.
In this case there is no userspace exposure needed at all and the here
proposed driver is not used.

But if your design isn't that complex or there is no device driver
available for it (yet), there is the desire to have simple userspace
controls to adjust the frequency easily during runtime. In this case the
proposed driver can be used to expose the clock controls for the wanted
clocks through sysfs.

I hope that will be the way it used. I didn't intent to provide a
userspace API people rely on for more than some simple adjustments.
The more complex the IP in the FPGA becomes, the requirements and
limitations on clocking become more complex too. Then people will have
to write/use a proper dedicated driver for the IP, IMHO.

> 
> > + * Expose clock controls through sysfs to userspace.
> 
> > + * By writing 0/1 to 'enable' the clock can be disabled/enabled. Reading
> > + * that file returns the current state - 0 = disabled, 1 = enabled.
> 
> > + * Reading 'set_rate' returns the current clock frequency in Hz. Writing
> > + * the file requests setting a new frequency in Hz.
> 
> This needs to be covered in Documentation/ABI since it's adding new
> sysfs stuff.
I wanted to avoid becoming the provider of a stable userspace API. We'll
see how this goes.

> 
> > +	if (enable)
> > +		ret = clk_prepare_enable(pdata->clk);
> > +	else
> > +		clk_disable_unprepare(pdata->clk);
> 
> > +	if (ret)
> > +		return -EBUSY;
> 
> Why not pass back the actual error?
Good question. Was there some spec saying, that these sysfs callbacks
should return this error? Otherwise this will be fixed.

> 
> > +	pdata = kzalloc(clock_count * sizeof(*pdata), GFP_KERNEL);
> > +	if (!pdata)
> > +		return -ENOMEM;
> 
> devm?
In the current state, there is no real device and devices aren't
destroyed either. If this changes the managed framework may become an
option.

> 
> > +late_initcall(usclk_setup);
> 
> Why not just a regular driver?
Looks like I'll go that way. I didn't want it originally, since there
is no physical HW for this driver. I wanted to use the clock probing
mechanism, but ran into problems with that because it takes place too
early during boot.


	S?ren




From liuj97 at gmail.com  Sat May 11 13:34:34 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Sun, 12 May 2013 01:34:34 +0800
Subject: [PATCH v6,
 part3 01/16] mm: change signature of free_reserved_area() to fix
 building warnings
In-Reply-To: <1368293689-16410-1-git-send-email-jiang.liu@huawei.com>
References: <1368293689-16410-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368293689-16410-2-git-send-email-jiang.liu@huawei.com>

Change signature of free_reserved_area() according to Russell King's
suggestion to fix following build warnings:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
  free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
  ^
In file included from include/linux/mman.h:4:0,
                 from arch/arm/mm/init.c:15:
include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
 extern unsigned long free_reserved_area(unsigned long start, unsigned long end,

   mm/page_alloc.c: In function 'free_reserved_area':
>> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
   In file included from arch/mips/include/asm/page.h:49:0,
                    from include/linux/mmzone.h:20,
                    from include/linux/gfp.h:4,
                    from include/linux/mm.h:8,
                    from mm/page_alloc.c:18:
   arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
   mm/page_alloc.c: In function 'free_area_init_nodes':
   mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Reported-by: Arnd Bergmann <arnd at arndb.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-mm at kvack.org
---
 arch/alpha/kernel/sys_nautilus.c |  4 ++--
 arch/alpha/mm/init.c             |  2 +-
 arch/arc/mm/init.c               |  2 +-
 arch/arm/mm/init.c               |  2 +-
 arch/arm64/mm/init.c             |  2 +-
 arch/avr32/mm/init.c             |  2 +-
 arch/blackfin/mm/init.c          |  2 +-
 arch/c6x/mm/init.c               |  2 +-
 arch/frv/mm/init.c               |  2 +-
 arch/h8300/mm/init.c             |  2 +-
 arch/ia64/mm/init.c              |  3 +--
 arch/m32r/mm/init.c              |  2 +-
 arch/m68k/mm/init.c              |  2 +-
 arch/metag/mm/init.c             |  3 ++-
 arch/microblaze/mm/init.c        |  2 +-
 arch/mips/mm/init.c              |  3 ++-
 arch/mn10300/mm/init.c           |  3 ++-
 arch/openrisc/mm/init.c          |  2 +-
 arch/parisc/mm/init.c            |  3 ++-
 arch/powerpc/kernel/kvm.c        |  2 +-
 arch/powerpc/mm/mem.c            |  2 +-
 arch/s390/mm/init.c              |  3 ++-
 arch/score/mm/init.c             |  3 ++-
 arch/sh/mm/init.c                |  2 +-
 arch/sparc/mm/init_32.c          |  4 ++--
 arch/sparc/mm/init_64.c          |  4 ++--
 arch/um/kernel/mem.c             |  2 +-
 arch/unicore32/mm/init.c         |  2 +-
 arch/xtensa/mm/init.c            |  2 +-
 include/linux/mm.h               |  5 ++---
 mm/page_alloc.c                  | 16 ++++++++--------
 31 files changed, 48 insertions(+), 44 deletions(-)

diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 1d4aabf..891bd27 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -238,8 +238,8 @@ nautilus_init_pci(void)
 	if (pci_mem < memtop)
 		memtop = pci_mem;
 	if (memtop > alpha_mv.min_mem_address) {
-		free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
-				   (unsigned long)__va(memtop), 0, NULL);
+		free_reserved_area(__va(alpha_mv.min_mem_address),
+				   __va(memtop), 0, NULL);
 		printk("nautilus_init_pci: %ldk freed\n",
 			(memtop - alpha_mv.min_mem_address) >> 10);
 	}
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 0ba85ee..d54848d 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -326,6 +326,6 @@ free_initmem(void)
 void
 free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 4a17736..dce02e4 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -152,7 +152,7 @@ void __init_refok free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc0..59d6f76 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -744,7 +744,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index f497ca7..6041e40 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -398,7 +398,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index e66e840..5a79fa0 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -154,6 +154,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 82d01a7..8e9eab2 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -133,7 +133,7 @@ void __init mem_init(void)
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
 #ifndef CONFIG_MPU
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 #endif
 }
 #endif
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
index a9fcd89..97914e5 100644
--- a/arch/c6x/mm/init.c
+++ b/arch/c6x/mm/init.c
@@ -77,7 +77,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index dee354f..a67f3a5 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -173,6 +173,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 } /* end free_initrd_mem() */
 #endif
diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c
index ff349d7..57e03c5 100644
--- a/arch/h8300/mm/init.c
+++ b/arch/h8300/mm/init.c
@@ -161,7 +161,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index d1fe4b4..da568c2 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -154,8 +154,7 @@ ia64_init_addr_space (void)
 void
 free_initmem (void)
 {
-	free_reserved_area((unsigned long)ia64_imva(__init_begin),
-			   (unsigned long)ia64_imva(__init_end),
+	free_reserved_area(ia64_imva(__init_begin), ia64_imva(__init_end),
 			   0, "unused kernel");
 }
 
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index ab4cbce..d80412d 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -191,6 +191,6 @@ void free_initmem(void)
  *======================================================================*/
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 1af2ca3..95de725 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -202,6 +202,6 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index d05b845..5e2238d 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -414,7 +414,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index b38ae3a..d7b8ada 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -235,7 +235,7 @@ void __init setup_memory(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 9b973e0..268f2a9 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -440,7 +440,8 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 5a8ace6..e19049d 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -152,6 +152,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index b3cbc67..ab11332 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -261,7 +261,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index ce939ac..59cec60 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -1101,6 +1101,7 @@ void flush_tlb_all(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, 0, "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end, 0,
+					    "initrd");
 }
 #endif
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 6782221..5e4830a 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -756,7 +756,7 @@ static __init void kvm_free_tmp(void)
 	end = (ulong)&kvm_tmp[ARRAY_SIZE(kvm_tmp)] & PAGE_MASK;
 
 	/* Free the tmp space we don't need */
-	free_reserved_area(start, end, 0, NULL);
+	free_reserved_area((void *)start, (void *)end, 0, NULL);
 }
 
 static int __init kvm_guest_init(void)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 0988a26..347c5b1 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -407,7 +407,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 89ebae4..0878c89 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -172,7 +172,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index d8f988a..3d79ecb 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -110,7 +110,8 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 20f9ead..b892a9b 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -505,7 +505,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index af472cf..d5f9c02 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -372,8 +372,8 @@ void free_initmem (void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index a717199..a54cdcd 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2124,8 +2124,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 9df292b..2aa7a24 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -244,7 +244,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 63df12d..220755c 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -486,7 +486,7 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index bba125b..4d658ef 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -214,7 +214,7 @@ extern int initrd_is_mapped;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (initrd_is_mapped)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e0c8528..771769f 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1307,7 +1307,7 @@ extern void free_initmem(void);
  * "poison" if it's non-zero.
  * Return pages freed into the buddy system.
  */
-extern unsigned long free_reserved_area(unsigned long start, unsigned long end,
+extern unsigned long free_reserved_area(void *start, void *end,
 					int poison, char *s);
 #ifdef	CONFIG_HIGHMEM
 /*
@@ -1351,8 +1351,7 @@ static inline unsigned long free_initmem_default(int poison)
 {
 	extern char __init_begin[], __init_end[];
 
-	return free_reserved_area(PAGE_ALIGN((unsigned long)&__init_begin) ,
-				  ((unsigned long)&__init_end) & PAGE_MASK,
+	return free_reserved_area(&__init_begin, &__init_end,
 				  poison, "unused kernel");
 }
 
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 34d42dc..9fe3061 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5188,21 +5188,21 @@ early_param("movablecore", cmdline_parse_movablecore);
 
 #endif /* CONFIG_HAVE_MEMBLOCK_NODE_MAP */
 
-unsigned long free_reserved_area(unsigned long start, unsigned long end,
-				 int poison, char *s)
+unsigned long free_reserved_area(void *start, void *end, int poison, char *s)
 {
-	unsigned long pages, pos;
+	void *pos;
+	unsigned long pages = 0;
 
-	pos = start = PAGE_ALIGN(start);
-	end &= PAGE_MASK;
-	for (pages = 0; pos < end; pos += PAGE_SIZE, pages++) {
+	start = (void *)PAGE_ALIGN((unsigned long)start);
+	end = (void *)((unsigned long)end & PAGE_MASK);
+	for (pos = start; pos < end; pos += PAGE_SIZE, pages++) {
 		if (poison)
-			memset((void *)pos, poison, PAGE_SIZE);
+			memset(pos, poison, PAGE_SIZE);
 		free_reserved_page(virt_to_page(pos));
 	}
 
 	if (pages && s)
-		pr_info("Freeing %s memory: %ldK (%lx - %lx)\n",
+		pr_info("Freeing %s memory: %ldK (%p - %p)\n",
 			s, pages << (PAGE_SHIFT - 10), start, end);
 
 	return pages;
-- 
1.8.1.2



From liuj97 at gmail.com  Sat May 11 13:34:36 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Sun, 12 May 2013 01:34:36 +0800
Subject: [PATCH v6, part3 03/16] mm/ARM64: kill poison_init_mem()
In-Reply-To: <1368293689-16410-1-git-send-email-jiang.liu@huawei.com>
References: <1368293689-16410-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368293689-16410-4-git-send-email-jiang.liu@huawei.com>

Use free_reserved_area() to poison initmem memory pages and kill
poison_init_mem() on ARM64.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm64/mm/init.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 997c634..a398eb9 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -197,14 +197,6 @@ void __init bootmem_init(void)
 	max_pfn = max_low_pfn = max;
 }
 
-/*
- * Poison init memory with an undefined instruction (0x0).
- */
-static inline void poison_init_mem(void *s, size_t count)
-{
-	memset(s, 0, count);
-}
-
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
 static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -386,8 +378,7 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-	poison_init_mem(__init_begin, __init_end - __init_begin);
-	free_initmem_default(-1);
+	free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -396,10 +387,8 @@ static int keep_initrd;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	if (!keep_initrd) {
-		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area((void *)start, (void *)end, -1, "initrd");
-	}
+	if (!keep_initrd)
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
-- 
1.8.1.2



From linux at arm.linux.org.uk  Sat May 11 15:10:52 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 May 2013 20:10:52 +0100
Subject: [PATCH -v10 09/11] arm, prepare reboot_mode for moving to
 generic kernel code.
In-Reply-To: <588ed084-fed7-4bd9-bcd7-a32f40bd404a@email.android.com>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-10-git-send-email-holt@sgi.com>
 <20130511130457.GD18614@n2100.arm.linux.org.uk>
 <588ed084-fed7-4bd9-bcd7-a32f40bd404a@email.android.com>
Message-ID: <20130511191051.GE18614@n2100.arm.linux.org.uk>

Please, stop this idiotic incomprehensible jargon.

On Sat, May 11, 2013 at 08:47:28AM -0700, H. Peter Anvin wrote:
> By the way, do we really need Yoda programming here?
> 
> Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> 
> >On Sat, May 11, 2013 at 06:57:25AM -0500, Robin Holt wrote:
> >> This patch prepares for the moving the parsing of reboot= to the
> >generic
> >> kernel code by making reboot_mode into a more generic form.
> >> 
> >> Signed-off-by: Robin Holt <holt at sgi.com>
> >> To: Andrew Morton <akpm at linux-foundation.org>
> >> To: Russell King <linux at arm.linux.org.uk>
> >> Cc: Russ Anderson <rja at sgi.com>
> >> Cc: Robin Holt <holt at sgi.com>
> >> Cc: H. Peter Anvin <hpa at zytor.com>
> >> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
> >> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
> >> Cc: the arch/x86 maintainers <x86 at kernel.org>
> >> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
> >
> >Almost-but-not-quite-Acked-by: Russell King
> ><rmk+kernel at arm.linux.org.uk> :)
> >
> >> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> >> index f219703..92b47df 100644
> >> --- a/arch/arm/kernel/process.c
> >> +++ b/arch/arm/kernel/process.c
> >> @@ -174,14 +174,14 @@ void arch_cpu_idle(void)
> >>  		default_idle();
> >>  }
> >>  
> >> -static char reboot_mode = 'h';
> >> +enum reboot_mode reboot_mode = REBOOT_HARD;
> >>  
> >> -int __init reboot_setup(char *str)
> >> +static int __init reboot_setup(char *str)
> >>  {
> >> -	reboot_mode = str[0];
> >> +	if ('s' == str[0])
> >> +		reboot_mode = REBOOT_SOFT;
> >
> >Remember we talked about the 'gpio' mode as well, so you also need here
> >+	if ('g' == str[0])
> >		reboot_mode = REBOOT_GPIO;
> 
> -- 
> Sent from my mobile phone. Please excuse brevity and lack of formatting.


From dianders at chromium.org  Sat May 11 17:25:15 2013
From: dianders at chromium.org (Doug Anderson)
Date: Sat, 11 May 2013 14:25:15 -0700
Subject: [PATCH 1/2] ARM: dts: add DP clock reference to exynos5250 device
 tree
In-Reply-To: <003001ce4e1b$24a28fc0$6de7af40$@samsung.com>
References: <003001ce4e1b$24a28fc0$6de7af40$@samsung.com>
Message-ID: <CAD=FV=V=exRoo1VAF5W7May_DFOWb6h_KL7BkqK3G2qmBQgUeA@mail.gmail.com>

Jingoo,

On Sat, May 11, 2013 at 12:42 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> The transition to common clock happened; however, DP (Display Port)
> clock node was not added. Thus, DP (Display Port) clock node should
> be added to the device tree.
>
> Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> ---
> Tested on Exynos5250
>
>  arch/arm/boot/dts/exynos5250.dtsi |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)

Clock number matches clock bindings for 5250 and clock name matches dp
driver, so this looks good.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From dianders at chromium.org  Sat May 11 17:26:07 2013
From: dianders at chromium.org (Doug Anderson)
Date: Sat, 11 May 2013 14:26:07 -0700
Subject: [PATCH 2/2] ARM: dts: Document DP clock in samsung,
 exynos5-dp binding
In-Reply-To: <003101ce4e1b$4acc0050$e06400f0$@samsung.com>
References: <003101ce4e1b$4acc0050$e06400f0$@samsung.com>
Message-ID: <CAD=FV=UjohPBxChbE2R4b8JWCbxZRXVx_9WuMYPgHTehMP6vvg@mail.gmail.com>

Jingoo,

On Sat, May 11, 2013 at 12:43 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> The exynos5-dp node needs a clock specified using the common clock
> framework.
>
> Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> ---
> Tested on Exynos5250
>
>  .../devicetree/bindings/video/exynos_dp.txt        |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)

Thanks for updating the bindings.  This looks good.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From dianders at chromium.org  Sat May 11 17:40:34 2013
From: dianders at chromium.org (Doug Anderson)
Date: Sat, 11 May 2013 14:40:34 -0700
Subject: [PATCH] ARM: dts: add pin state information for DP HPD support to
 Exynos5250
In-Reply-To: <000001ce4e1e$d1cc5de0$756519a0$@samsung.com>
References: <000001ce4e1e$d1cc5de0$756519a0$@samsung.com>
Message-ID: <CAD=FV=V9oBR1ZAEsMs5-x7NaD1fiHJO=9dn1mPAMg0MX6tnxYA@mail.gmail.com>

Jingoo,

On Sat, May 11, 2013 at 1:09 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> Add pin state information for DP HPD support that requires
> pin configuration support using pinctrl interface.
>
> Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> ---
> Tested on Exynos5250
>
>  arch/arm/boot/dts/exynos5250-pinctrl.dtsi |    7 +++++++
>  arch/arm/boot/dts/exynos5250-smdk5250.dts |    3 +++
>  2 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> index d1650fb..e9cdee3 100644
> --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> @@ -553,6 +553,13 @@
>                         samsung,pin-pud = <0>;
>                         samaung,pin-drv = <0>;
>                 };
> +
> +               dp_hpd: dp_hpd {
> +                       samsung,pins = "gpx0-7";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <0>;
> +                       samaung,pin-drv = <0>;
> +               };
>         };
>
>         pinctrl at 13400000 {
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 3e0c792..d53ea34 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -224,6 +224,9 @@
>                 samsung,color-depth = <1>;
>                 samsung,link-rate = <0x0a>;
>                 samsung,lane-count = <4>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&dp_hpd>;

I was going to suggest moving this to exynos5250.dtsi but then
realized that I saw a board recently that used a non-standard HPD pin
recently!  ...so keeping it in the board file (like you've done) is
good.

...so looks good to me.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From davem at davemloft.net  Sat May 11 19:12:57 2013
From: davem at davemloft.net (David Miller)
Date: Sat, 11 May 2013 16:12:57 -0700 (PDT)
Subject: [PATCH] net: fec: enable hardware checksum only on imx6q-fec
In-Reply-To: <1368083302-12516-1-git-send-email-shawn.guo@linaro.org>
References: <1368083302-12516-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130511.161257.1222305719812815291.davem@davemloft.net>

From: Shawn Guo <shawn.guo at linaro.org>
Date: Thu, 9 May 2013 15:08:22 +0800

> Commit 4c09eed (net: fec: Enable imx6 enet checksum acceleration.)
> enables hardware checksum acceleration unconditionally for all fec
> variants.  This is inappropriate, because some variants like imx5 have
> no such support on hardware.  Consequently, fec is broken on these
> platforms.  Fix it by enabling hardware checksum only on imx6q-fec type
> of controllers.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Applied.


From hpa at zytor.com  Sat May 11 22:49:20 2013
From: hpa at zytor.com (H. Peter Anvin)
Date: Sat, 11 May 2013 19:49:20 -0700
Subject: [PATCH -v10 09/11] arm,
 prepare reboot_mode for moving to	generic kernel code.
In-Reply-To: <20130511191051.GE18614@n2100.arm.linux.org.uk>
References: <1368273447-11958-1-git-send-email-holt@sgi.com>
 <1368273447-11958-10-git-send-email-holt@sgi.com>
 <20130511130457.GD18614@n2100.arm.linux.org.uk>
 <588ed084-fed7-4bd9-bcd7-a32f40bd404a@email.android.com>
 <20130511191051.GE18614@n2100.arm.linux.org.uk>
Message-ID: <6ea66d50-a577-4e08-b315-c7a332144f1d@email.android.com>

Sorry.  Yoga programming meaning reversing the arguments to ==.

Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

>Please, stop this idiotic incomprehensible jargon.
>
>On Sat, May 11, 2013 at 08:47:28AM -0700, H. Peter Anvin wrote:
>> By the way, do we really need Yoda programming here?
>> 
>> Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
>> 
>> >On Sat, May 11, 2013 at 06:57:25AM -0500, Robin Holt wrote:
>> >> This patch prepares for the moving the parsing of reboot= to the
>> >generic
>> >> kernel code by making reboot_mode into a more generic form.
>> >> 
>> >> Signed-off-by: Robin Holt <holt at sgi.com>
>> >> To: Andrew Morton <akpm at linux-foundation.org>
>> >> To: Russell King <linux at arm.linux.org.uk>
>> >> Cc: Russ Anderson <rja at sgi.com>
>> >> Cc: Robin Holt <holt at sgi.com>
>> >> Cc: H. Peter Anvin <hpa at zytor.com>
>> >> Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
>> >> Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
>> >> Cc: the arch/x86 maintainers <x86 at kernel.org>
>> >> Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
>> >
>> >Almost-but-not-quite-Acked-by: Russell King
>> ><rmk+kernel at arm.linux.org.uk> :)
>> >
>> >> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
>> >> index f219703..92b47df 100644
>> >> --- a/arch/arm/kernel/process.c
>> >> +++ b/arch/arm/kernel/process.c
>> >> @@ -174,14 +174,14 @@ void arch_cpu_idle(void)
>> >>  		default_idle();
>> >>  }
>> >>  
>> >> -static char reboot_mode = 'h';
>> >> +enum reboot_mode reboot_mode = REBOOT_HARD;
>> >>  
>> >> -int __init reboot_setup(char *str)
>> >> +static int __init reboot_setup(char *str)
>> >>  {
>> >> -	reboot_mode = str[0];
>> >> +	if ('s' == str[0])
>> >> +		reboot_mode = REBOOT_SOFT;
>> >
>> >Remember we talked about the 'gpio' mode as well, so you also need
>here
>> >+	if ('g' == str[0])
>> >		reboot_mode = REBOOT_GPIO;
>> 
>> -- 
>> Sent from my mobile phone. Please excuse brevity and lack of
>formatting.

-- 
Sent from my mobile phone. Please excuse brevity and lack of formatting.


From dt.tangr at gmail.com  Sun May 12 00:22:55 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:22:55 +1000
Subject: [RFC PATCHv3 0/6] arm: Initial TI-Nspire support
Message-ID: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>

Changes between http://archive.arm.linux.org.uk/lurker/message/20130408.113343.585af217.en.html and v2:
* Added new drivers to support the irqchip and timers on older models.
* Added new device trees to support the other models.

Changes between v2 and v3:
* Clean up keypad driver
* Update copyright messages (2012->2013)
* Added clock driver
* Fix keypad support for classic models
* Fix nspire-classic-timer code to use updated CLOCKSOURCE_OF_DECLARE
* Change CLCD code to use panel capabilities
* Change UART clock to match APB speed
* Support for reset


First time using git send-email, please forgive me if this turns pear shaped.

Daniel Tang (6):
  arm: Initial TI-Nspire support
  arm: Add device trees for TI-Nspire
  clk: Add TI-Nspire clock drivers
  clocksource: Add TI-Nspire timer drivers
  input: Add TI-Nspire keypad driver
  irqchip: Add TI-Nspire irqchip

 arch/arm/Kconfig                           |   2 +
 arch/arm/Kconfig.debug                     |  16 ++
 arch/arm/Makefile                          |   1 +
 arch/arm/boot/dts/Makefile                 |   3 +
 arch/arm/boot/dts/nspire-classic.dtsi      |  75 +++++++
 arch/arm/boot/dts/nspire-clp.dts           |  45 +++++
 arch/arm/boot/dts/nspire-cx.dts            | 112 ++++++++++
 arch/arm/boot/dts/nspire-tp.dts            |  44 ++++
 arch/arm/boot/dts/nspire.dtsi              | 182 +++++++++++++++++
 arch/arm/include/debug/nspire.S            |  28 +++
 arch/arm/mach-nspire/Kconfig               |  15 ++
 arch/arm/mach-nspire/Makefile              |   2 +
 arch/arm/mach-nspire/Makefile.boot         |   0
 arch/arm/mach-nspire/clcd.c                | 117 +++++++++++
 arch/arm/mach-nspire/clcd.h                |  14 ++
 arch/arm/mach-nspire/mmio.h                |  18 ++
 arch/arm/mach-nspire/nspire.c              |  99 +++++++++
 drivers/clk/Makefile                       |   1 +
 drivers/clk/clk-nspire.c                   | 141 +++++++++++++
 drivers/clocksource/Makefile               |   1 +
 drivers/clocksource/nspire-classic-timer.c | 199 ++++++++++++++++++
 drivers/input/keyboard/Kconfig             |  10 +
 drivers/input/keyboard/Makefile            |   1 +
 drivers/input/keyboard/nspire-keypad.c     | 315 +++++++++++++++++++++++++++++
 drivers/irqchip/Makefile                   |   1 +
 drivers/irqchip/irq-nspire-classic.c       | 177 ++++++++++++++++
 26 files changed, 1619 insertions(+)
 create mode 100644 arch/arm/boot/dts/nspire-classic.dtsi
 create mode 100644 arch/arm/boot/dts/nspire-clp.dts
 create mode 100644 arch/arm/boot/dts/nspire-cx.dts
 create mode 100644 arch/arm/boot/dts/nspire-tp.dts
 create mode 100644 arch/arm/boot/dts/nspire.dtsi
 create mode 100644 arch/arm/include/debug/nspire.S
 create mode 100644 arch/arm/mach-nspire/Kconfig
 create mode 100644 arch/arm/mach-nspire/Makefile
 create mode 100644 arch/arm/mach-nspire/Makefile.boot
 create mode 100644 arch/arm/mach-nspire/clcd.c
 create mode 100644 arch/arm/mach-nspire/clcd.h
 create mode 100644 arch/arm/mach-nspire/mmio.h
 create mode 100644 arch/arm/mach-nspire/nspire.c
 create mode 100644 drivers/clk/clk-nspire.c
 create mode 100644 drivers/clocksource/nspire-classic-timer.c
 create mode 100644 drivers/input/keyboard/nspire-keypad.c
 create mode 100644 drivers/irqchip/irq-nspire-classic.c

-- 
1.8.1.3



From dt.tangr at gmail.com  Sun May 12 00:22:56 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:22:56 +1000
Subject: [RFC PATCHv3 1/6] arm: Initial TI-Nspire support
In-Reply-To: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1368332581-94691-2-git-send-email-dt.tangr@gmail.com>


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 arch/arm/Kconfig                   |   2 +
 arch/arm/Kconfig.debug             |  16 +++++
 arch/arm/Makefile                  |   1 +
 arch/arm/include/debug/nspire.S    |  28 +++++++++
 arch/arm/mach-nspire/Kconfig       |  15 +++++
 arch/arm/mach-nspire/Makefile      |   2 +
 arch/arm/mach-nspire/Makefile.boot |   0
 arch/arm/mach-nspire/clcd.c        | 117 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-nspire/clcd.h        |  14 +++++
 arch/arm/mach-nspire/mmio.h        |  18 ++++++
 arch/arm/mach-nspire/nspire.c      |  99 +++++++++++++++++++++++++++++++
 11 files changed, 312 insertions(+)
 create mode 100644 arch/arm/include/debug/nspire.S
 create mode 100644 arch/arm/mach-nspire/Kconfig
 create mode 100644 arch/arm/mach-nspire/Makefile
 create mode 100644 arch/arm/mach-nspire/Makefile.boot
 create mode 100644 arch/arm/mach-nspire/clcd.c
 create mode 100644 arch/arm/mach-nspire/clcd.h
 create mode 100644 arch/arm/mach-nspire/mmio.h
 create mode 100644 arch/arm/mach-nspire/nspire.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..b8cb225 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -963,6 +963,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-nspire/Kconfig"
+
 source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908..fe07941 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -309,6 +309,20 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on MVEBU based platforms.
 
+	config DEBUG_NSPIRE_CLASSIC_UART
+		bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
+		depends on ARCH_NSPIRE
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on TI-NSPIRE classic models.
+
+	config DEBUG_NSPIRE_CX_UART
+		bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
+		depends on ARCH_NSPIRE
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on TI-NSPIRE CX models.
+
 	config DEBUG_NOMADIK_UART
 		bool "Kernel low-level debugging messages via NOMADIK UART"
 		depends on ARCH_NOMADIK
@@ -633,6 +647,8 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_IMX53_UART ||\
 				 DEBUG_IMX6Q_UART
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
+	default "debug/nspire.S" if 	DEBUG_NSPIRE_CX_UART || \
+					DEBUG_NSPIRE_CLASSIC_UART
 	default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
 	default "debug/nomadik.S" if DEBUG_NOMADIK_UART
 	default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 4737408..a4340d1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -164,6 +164,7 @@ machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_NETX)		+= netx
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
 machine-$(CONFIG_ARCH_OMAP1)		+= omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 0000000..886fd27
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
+/*
+ *	linux/arch/arm/include/debug/nspire.S
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE	   0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE	   0xfee20000
+
+.macro	addruart, rp, rv, tmp
+	ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE)		@ physical base address
+	ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE)		@ virtual base address
+.endm
+
+
+#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
+#include <asm/hardware/debug-pl01x.S>
+#endif
+
+#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
+#endif
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 0000000..a295b18
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_NSPIRE
+	bool "TI-NSPIRE based"
+	depends on ARCH_MULTI_V4_V5
+	depends on MMU
+	select CPU_ARM926T
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select SPARSE_IRQ
+	select ARM_AMBA
+	select ARM_VIC
+	select ARM_TIMER_SP804
+	select USE_OF
+	select CLKSRC_OF
+	help
+	  This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 0000000..1bec256
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
+obj-y				+= nspire.o
+obj-y				+= clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 0000000..a4b9f06
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,117 @@
+/*
+ *	linux/arch/arm/mach-nspire/clcd.c
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/dma-mapping.h>
+
+static struct clcd_panel nspire_cx_lcd_panel = {
+	.mode		= {
+		.name		= "Color LCD",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.sync		= 0,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.pixclock	= 1,
+		.hsync_len	= 6,
+		.vsync_len	= 1,
+		.right_margin	= 50,
+		.left_margin	= 38,
+		.lower_margin	= 3,
+		.upper_margin	= 17,
+	},
+	.width		= 65, /* ~6.50 cm */
+	.height		= 49, /* ~4.87 cm */
+	.tim2		= TIM2_IPC,
+	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
+	.bpp		= 16,
+};
+
+static struct clcd_panel nspire_classic_lcd_panel = {
+	.mode		= {
+		.name		= "Grayscale LCD",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.pixclock	= 1,
+		.hsync_len	= 6,
+		.vsync_len	= 1,
+		.right_margin	= 6,
+		.left_margin	= 6,
+	},
+	.width		= 71, /* 7.11cm */
+	.height		= 53, /* 5.33cm */
+	.tim2		= 0x80007d0,
+	.cntl		= CNTL_LCDMONO8,
+	.bpp		= 8,
+	.grayscale	= 1
+};
+
+int nspire_clcd_setup(struct clcd_fb *fb)
+{
+	struct clcd_panel *panel;
+	size_t panel_size;
+	const char *type;
+	dma_addr_t dma;
+	int err;
+
+	BUG_ON(!fb->dev->dev.of_node);
+
+	err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
+	if (err) {
+		pr_err("CLCD: Could not find lcd-type property\n");
+		return err;
+	}
+
+	if (!strcmp(type, "cx")) {
+		panel = &nspire_cx_lcd_panel;
+	} else if (!strcmp(type, "classic")) {
+		panel = &nspire_classic_lcd_panel;
+	} else {
+		pr_err("CLCD: Unknown lcd-type %s\n", type);
+		return -EINVAL;
+	}
+
+	panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
+	panel_size = ALIGN(panel_size, PAGE_SIZE);
+
+	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+		panel_size, &dma, GFP_KERNEL);
+
+	if (!fb->fb.screen_base) {
+		pr_err("CLCD: unable to map framebuffer\n");
+		return -ENOMEM;
+	}
+
+	fb->fb.fix.smem_start = dma;
+	fb->fb.fix.smem_len = panel_size;
+	fb->panel = panel;
+
+	return 0;
+}
+
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+	return dma_mmap_writecombine(&fb->dev->dev, vma,
+		fb->fb.screen_base, fb->fb.fix.smem_start,
+		fb->fb.fix.smem_len);
+}
+
+void nspire_clcd_remove(struct clcd_fb *fb)
+{
+	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+		fb->fb.screen_base, fb->fb.fix.smem_start);
+}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 0000000..8c33d2c
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
+/*
+ *	linux/arch/arm/mach-nspire/clcd.h
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+int nspire_clcd_setup(struct clcd_fb *fb);
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
+void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 0000000..9d45f59
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,18 @@
+/*
+ *	linux/arch/arm/mach-nspire/mmio.h
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE	0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE	0xFEE20000
+
+#define NSPIRE_MISC_PHYS_BASE		0x900A0000
+#define NSPIRE_MISC_HWRESET		0x08
+
+#define NSPIRE_LCD_PHYS_BASE		0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 0000000..821f3b2
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,99 @@
+/*
+ *	linux/arch/arm/mach-nspire/nspire.c
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-vic.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/hardware/timer-sp.h>
+
+#include "mmio.h"
+#include "clcd.h"
+
+static const char *nspire_dt_match[] __initconst = {
+	"arm,nspire",
+	"arm,nspire-cx",
+	"arm,nspire-tp",
+	"arm,nspire-clp",
+	NULL,
+};
+
+static struct map_desc nspire_io_desc[] __initdata = {
+	{
+		.virtual	=  NSPIRE_EARLY_UART_VIRT_BASE,
+		.pfn		= __phys_to_pfn(NSPIRE_EARLY_UART_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}
+};
+
+static void __init nspire_map_io(void)
+{
+	iotable_init(nspire_io_desc, ARRAY_SIZE(nspire_io_desc));
+}
+
+static struct clcd_board nspire_clcd_data = {
+	.name		= "LCD",
+	.caps		= CLCD_CAP_ALL,
+	.check		= clcdfb_check,
+	.decode		= clcdfb_decode,
+	.setup		= nspire_clcd_setup,
+	.mmap		= nspire_clcd_mmap,
+	.remove		= nspire_clcd_remove,
+};
+
+
+static struct of_dev_auxdata nspire_auxdata[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
+			NULL, &nspire_clcd_data),
+	{ }
+};
+
+static void __init nspire_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			nspire_auxdata, NULL);
+}
+
+static void __init nspire_init_time(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+static void nspire_restart(char mode, const char *cmd)
+{
+	void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
+	if (!base)
+		return;
+
+	writel(2, base + NSPIRE_MISC_HWRESET);
+}
+
+DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
+	.map_io		= nspire_map_io,
+	.init_irq	= irqchip_init,
+	.init_time	= nspire_init_time,
+	.init_machine	= nspire_init,
+	.dt_compat	= nspire_dt_match,
+	.restart	= nspire_restart,
+MACHINE_END
-- 
1.8.1.3



From dt.tangr at gmail.com  Sun May 12 00:22:57 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:22:57 +1000
Subject: [RFC PATCHv3 2/6] arm: Add device trees for TI-Nspire
In-Reply-To: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1368332581-94691-3-git-send-email-dt.tangr@gmail.com>


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 arch/arm/boot/dts/Makefile            |   3 +
 arch/arm/boot/dts/nspire-classic.dtsi |  75 ++++++++++++++
 arch/arm/boot/dts/nspire-clp.dts      |  45 +++++++++
 arch/arm/boot/dts/nspire-cx.dts       | 112 +++++++++++++++++++++
 arch/arm/boot/dts/nspire-tp.dts       |  44 ++++++++
 arch/arm/boot/dts/nspire.dtsi         | 182 ++++++++++++++++++++++++++++++++++
 6 files changed, 461 insertions(+)
 create mode 100644 arch/arm/boot/dts/nspire-classic.dtsi
 create mode 100644 arch/arm/boot/dts/nspire-clp.dts
 create mode 100644 arch/arm/boot/dts/nspire-cx.dts
 create mode 100644 arch/arm/boot/dts/nspire-tp.dts
 create mode 100644 arch/arm/boot/dts/nspire.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..5677d6c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx28-sps1.dtb \
 	imx28-tx28.dtb
 dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
+	nspire-tp.dtb \
+	nspire-clp.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	omap3430-sdp.dtb \
 	omap3-beagle.dtb \
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 0000000..eb1c2a2
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/boot/nspire-classic.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "nspire.dtsi"
+
+&lcd {
+	lcd-type = "classic";
+};
+
+&fast_timer {
+	/* compatible = "nspire-classic-timer"; */
+	reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+};
+
+&uart {
+	compatible = "ns16550";
+	reg-shift = <2>;
+	reg-io-width = <4>;
+	clocks = <&apb_pclk>;
+	clock-names = "apb_pclk";
+	no-loopback-test;
+};
+
+&timer0 {
+	/* compatible = "nspire-classic-timer"; */
+	reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+};
+
+&timer1 {
+	compatible = "nspire-classic-timer";
+	reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+};
+
+&keypad {
+	active-low;
+
+};
+
+&base_clk {
+	io-type = "classic";
+};
+
+&ahb_clk {
+	io-type = "classic";
+};
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x10000000 0x2000000>; /* 32 MB */
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		intc: interrupt-controller at DC000000 {
+			compatible = "nspire-classic-intc";
+			interrupt-controller;
+			reg = <0xDC000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+	};
+	chosen {
+		bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
+	};
+};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 0000000..7f25f44
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/boot/nspire-clp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00020039
+	0x0004002c 	0x00050034 	0x00060015
+	0x0007000b 	0x0008002d 	0x01000033
+	0x0101004e 	0x01020011 	0x01030004
+	0x0104002f 	0x01050003 	0x01060016
+	0x01070002 	0x01080014 	0x02000062
+	0x0201000c 	0x0202001f 	0x02030007
+	0x02040013 	0x02050006 	0x02060010
+	0x02070005 	0x02080019 	0x03000027
+	0x03010037 	0x03020018 	0x0303000a
+	0x03040031 	0x03050009 	0x03060032
+	0x03070008 	0x03080026 	0x04000028
+	0x04010035 	0x04020025 	0x04040024
+	0x04060017 	0x04080023 	0x05000028
+	0x05020022 	0x0503001b 	0x05040021
+	0x0505001a 	0x05060012 	0x0507006f
+	0x05080020 	0x0509002a 	0x0601001c
+	0x0602002e 	0x06030068 	0x06040030
+	0x0605006d 	0x0606001e 	0x06070001
+	0x0608002b 	0x0609000f 	0x07000067
+	0x0702006a 	0x0704006c 	0x07060069
+	0x0707000e 	0x0708001d 	0x070a000d
+	>;
+};
+
+/ {
+	model = "TI-NSPIRE Clickpad";
+	compatible = "arm,nspire-clp";
+};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 0000000..ac5c2ad
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/boot/nspire-cx.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire.dtsi"
+
+&lcd {
+	lcd-type = "cx";
+};
+
+&fast_timer {
+	/* compatible = "arm,sp804", "arm,primecell"; */
+};
+
+&uart {
+	compatible = "arm,pl011", "arm,primecell";
+
+	clocks = <&uart_clk>, <&apb_pclk>;
+	clock-names = "uart_clk", "apb_pclk";
+};
+
+&timer0 {
+	compatible = "arm,sp804", "arm,primecell";
+};
+
+&timer1 {
+	compatible = "arm,sp804", "arm,primecell";
+};
+
+&base_clk {
+	io-type = "cx";
+};
+
+&ahb_clk {
+	io-type = "cx";
+};
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
+
+/ {
+	model = "TI-NSPIRE CX";
+	compatible = "arm,nspire-cx";
+
+	memory {
+		device_type = "memory";
+		reg = <0x10000000 0x4000000>; /* 64 MB */
+	};
+
+	uart_clk: uart_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		intc: interrupt-controller at DC000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xDC000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		apb at 90000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			i2c at 90050000 {
+				compatible = "snps,designware-i2c";
+				reg = <0x90050000 0x1000>;
+				interrupts = <20>;
+			};
+		};
+	};
+	chosen {
+		bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
+	};
+};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 0000000..485d0ff
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
+/*
+ *  linux/arch/arm/boot/nspire-tp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
+
+/ {
+	model = "TI-NSPIRE Touchpad";
+	compatible = "arm,nspire-tp";
+};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 0000000..0e780f9
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,182 @@
+/*
+ *  linux/arch/arm/boot/nspire.dtsi
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	bootrom: bootrom at 00000000 {
+		reg = <0x00000000 0x80000>;
+	};
+
+	sram: sram at A4000000 {
+		device = "memory";
+		reg = <0xA4000000 0x20000>;
+	};
+
+	timer_clk: timer_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	base_clk: base_clk {
+		#clock-cells = <0>;
+		compatible = "nspire-clock";
+		reg = <0x900B0000 0x2>;
+	};
+
+	ahb_clk: ahb_clk {
+		#clock-cells = <0>;
+		compatible = "nspire-ahb-divider";
+		reg = <0x900B0000 0x2>;
+		clocks = <&base_clk>;
+		clock-names = "base_clk";
+	};
+
+	apb_pclk: apb_pclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <2>;
+		clock-mult = <1>;
+		clocks = <&ahb_clk>;
+		clock-names = "ahb_clk";
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		spi: spi at A9000000 {
+			reg = <0xA9000000 0x1000>;
+		};
+
+		usb0: usb at B0000000 {
+			reg = <0xB0000000 0x1000>;
+			interrupts = <8>;
+		};
+
+		usb1: usb at B4000000 {
+			reg = <0xB4000000 0x1000>;
+			interrupts = <9>;
+			status = "disabled";
+		};
+
+		lcd: lcd at C0000000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0xC0000000 0x1000>;
+			interrupts = <21>;
+
+			clocks = <&apb_pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		adc: adc at C4000000 {
+			reg = <0xC4000000 0x1000>;
+			interrupts = <11>;
+		};
+
+		tdes: crypto at C8010000 {
+			reg = <0xC8010000 0x1000>;
+		};
+
+		sha256: crypto at CC000000 {
+			reg = <0xCC000000 0x1000>;
+		};
+
+		apb at 90000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clock-ranges;
+			ranges;
+
+			gpio: gpio at 90000000 {
+				reg = <0x90000000 0x1000>;
+				interrupts = <7>;
+			};
+
+			fast_timer: timer at 90010000 {
+				reg = <0x90010000 0x1000>;
+				interrupts = <17>;
+			};
+
+			uart: serial at 90020000 {
+				reg = <0x90020000 0x1000>;
+				interrupts = <1>;
+			};
+
+			timer0: timer at 900C0000 {
+				reg = <0x900C0000 0x1000>;
+
+				clocks = <&timer_clk>;
+				clock-names = "timer_clk";
+			};
+
+			timer1: timer at 900D0000 {
+				reg = <0x900D0000 0x1000>;
+				interrupts = <19>;
+
+				clocks = <&timer_clk>;
+				clock-names = "timer_clk";
+			};
+
+			watchdog: watchdog at 90060000 {
+				compatible = "arm,amba-primecell";
+				reg = <0x90060000 0x1000>;
+				interrupts = <3>;
+			};
+
+			rtc: rtc at 90090000 {
+				reg = <0x90090000 0x1000>;
+				interrupts = <4>;
+			};
+
+			misc: misc at 900A0000 {
+				reg = <0x900A0000 0x1000>;
+			};
+
+			pwr: pwr at 900B0000 {
+				reg = <0x900B0000 0x1000>;
+				interrupts = <15>;
+			};
+
+			keypad: input at 900E0000 {
+				compatible = "nspire-keypad";
+				reg = <0x900E0000 0x1000>;
+				interrupts = <16>;
+
+				scan-interval = <1000>;
+				row-delay = <200>;
+
+				clocks = <&apb_pclk>;
+				clock-names = "apb_pclk";
+			};
+
+			contrast: contrast at 900F0000 {
+				reg = <0x900F0000 0x1000>;
+			};
+
+			led: led at 90110000 {
+				reg = <0x90110000 0x1000>;
+			};
+		};
+	};
+};
-- 
1.8.1.3



From dt.tangr at gmail.com  Sun May 12 00:22:58 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:22:58 +1000
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1368332581-94691-4-git-send-email-dt.tangr@gmail.com>


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-nspire.c | 141 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 142 insertions(+)
 create mode 100644 drivers/clk/clk-nspire.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..72ebbe1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
 obj-$(CONFIG_ARCH_NOMADIK)	+= clk-nomadik.o
 obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
+obj-$(CONFIG_ARCH_NSPIRE)	+= clk-nspire.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c
new file mode 100644
index 0000000..2a8d14c
--- /dev/null
+++ b/drivers/clk/clk-nspire.c
@@ -0,0 +1,141 @@
+/*
+ *  linux/drivers/clk/clk-nspire.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define MHZ (1000 * 1000)
+
+#define BASE_CPU_SHIFT		1
+#define BASE_CPU_MASK		0x7F
+
+#define CPU_AHB_SHIFT		12
+#define CPU_AHB_MASK		0x07
+
+#define FIXED_BASE_SHIFT	8
+#define FIXED_BASE_MASK		0x01
+
+#define CLASSIC_BASE_SHIFT	16
+#define CLASSIC_BASE_MASK	0x1F
+
+#define CX_BASE_SHIFT		15
+#define CX_BASE_MASK		0x3F
+
+#define CX_UNKNOWN_SHIFT	21
+#define CX_UNKNOWN_MASK		0x03
+
+#define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)
+
+struct nspire_clk_info {
+	u32 base_clock;
+	u16 base_cpu_ratio;
+	u16 base_ahb_ratio;
+};
+
+static int nspire_clk_read(struct device_node *node,
+		struct nspire_clk_info *clk)
+{
+	u32 val;
+	int ret;
+	void __iomem *io;
+	const char *type = NULL;
+
+	ret = of_property_read_string(node, "io-type", &type);
+	if (ret)
+		return ret;
+
+	io = of_iomap(node, 0);
+	if (!io)
+		return -ENOMEM;
+	val = readl(io);
+	iounmap(io);
+
+	if (!strcmp(type, "cx")) {
+		if (EXTRACT(val, FIXED_BASE)) {
+			clk->base_clock = 48 * MHZ;
+		} else {
+			clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
+		}
+
+		clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) *
+					EXTRACT(val, CX_UNKNOWN);
+		clk->base_ahb_ratio = clk->base_cpu_ratio *
+					(EXTRACT(val, CPU_AHB) + 1);
+	} else if (!strcmp(type, "classic")) {
+		if (EXTRACT(val, FIXED_BASE)) {
+			clk->base_clock = 27 * MHZ;
+		} else {
+			clk->base_clock = (300 -
+					6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
+		}
+
+		clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2;
+		clk->base_ahb_ratio = clk->base_cpu_ratio *
+					(EXTRACT(val, CPU_AHB) + 1);
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void __init nspire_ahbdiv_setup(struct device_node *node)
+{
+	int ret;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct nspire_clk_info info;
+
+	ret = nspire_clk_read(node, &info);
+	if (WARN_ON(ret))
+		return;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+					1, info.base_ahb_ratio);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static void __init nspire_clk_setup(struct device_node *node)
+{
+	int ret;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	struct nspire_clk_info info;
+
+	ret = nspire_clk_read(node, &info);
+	if (WARN_ON(ret))
+		return;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT,
+			info.base_clock);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	else
+		return;
+
+	pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n",
+		info.base_clock / MHZ,
+		info.base_clock / info.base_cpu_ratio / MHZ,
+		info.base_clock / info.base_ahb_ratio / MHZ);
+}
+
+CLK_OF_DECLARE(nspire_clk, "nspire-clock", nspire_clk_setup);
+CLK_OF_DECLARE(nspire_ahbdiv, "nspire-ahb-divider", nspire_ahbdiv_setup);
-- 
1.8.1.3



From dt.tangr at gmail.com  Sun May 12 00:22:59 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:22:59 +1000
Subject: [RFC PATCHv3 4/6] clocksource: Add TI-Nspire timer drivers
In-Reply-To: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 drivers/clocksource/Makefile               |   1 +
 drivers/clocksource/nspire-classic-timer.c | 199 +++++++++++++++++++++++++++++
 2 files changed, 200 insertions(+)
 create mode 100644 drivers/clocksource/nspire-classic-timer.c

diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c7..b9b56cb 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
+obj-$(CONFIG_ARCH_NSPIRE)	+= nspire-classic-timer.o
 obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
 obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
diff --git a/drivers/clocksource/nspire-classic-timer.c b/drivers/clocksource/nspire-classic-timer.c
new file mode 100644
index 0000000..4b92b61
--- /dev/null
+++ b/drivers/clocksource/nspire-classic-timer.c
@@ -0,0 +1,199 @@
+/*
+ *  linux/drivers/clocksource/nspire-classic-timer.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+
+#define DT_COMPAT	"nspire-classic-timer"
+
+#define IO_CURRENT_VAL	0x00
+#define IO_DIVIDER	0x04
+#define IO_CONTROL	0x08
+
+#define IO_TIMER1	0x00
+#define IO_TIMER2	0x0C
+
+#define IO_MATCH1	0x18
+#define IO_MATCH2	0x1C
+#define IO_MATCH3	0x20
+#define IO_MATCH4	0x24
+#define IO_MATCH5	0x28
+#define IO_MATCH6	0x2C
+
+#define IO_INTR_STS	0x00
+#define IO_INTR_ACK	0x00
+#define IO_INTR_MSK	0x04
+
+#define CNTL_STOP_TIMER	(1<<4)
+#define CNTL_RUN_TIMER	(0<<4)
+
+#define CNTL_INC	(1<<3)
+#define CNTL_DEC	(0<<3)
+
+#define CNTL_TOZERO	0
+#define CNTL_MATCH1	1
+#define CNTL_MATCH2	2
+#define CNTL_MATCH3	3
+#define CNTL_MATCH4	4
+#define CNTL_MATCH5	5
+#define CNTL_MATCH6	6
+#define CNTL_FOREVER	7
+
+struct nspire_timer {
+	void __iomem *base;
+	void __iomem *timer1, *timer2;
+	void __iomem *interrupt_regs;
+
+	int irqnr;
+
+	struct clk *clk;
+	struct clock_event_device clkevt;
+	struct irqaction clkevt_irq;
+
+	char clocksource_name[64];
+	char clockevent_name[64];
+};
+
+static int nspire_timer_set_event(unsigned long delta,
+		struct clock_event_device *dev)
+{
+	unsigned long flags;
+	struct nspire_timer *timer = container_of(dev,
+			struct nspire_timer,
+			clkevt);
+
+	local_irq_save(flags);
+
+	writel(delta, timer->timer1 + IO_CURRENT_VAL);
+	writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH1,
+			timer->timer1 + IO_CONTROL);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+static void nspire_timer_set_mode(enum clock_event_mode mode,
+		struct clock_event_device *evt)
+{
+	evt->mode = mode;
+}
+
+static irqreturn_t nspire_timer_interrupt(int irq, void *dev_id)
+{
+	struct nspire_timer *timer = dev_id;
+
+	writel((1<<0), timer->interrupt_regs + IO_INTR_ACK);
+	writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+
+	if (timer->clkevt.event_handler)
+		timer->clkevt.event_handler(&timer->clkevt);
+
+	return IRQ_HANDLED;
+}
+
+static int __init nspire_timer_add(struct device_node *node)
+{
+	struct nspire_timer *timer;
+	struct resource res;
+	int ret;
+
+	timer = kzalloc(sizeof(*timer), GFP_ATOMIC);
+	if (!timer)
+		return -ENOMEM;
+
+	timer->base = of_iomap(node, 0);
+	if (!timer->base) {
+		ret = -EINVAL;
+		goto error_free;
+	}
+	timer->timer1 = timer->base + IO_TIMER1;
+	timer->timer2 = timer->base + IO_TIMER2;
+
+	timer->clk = of_clk_get(node, 0);
+	if (IS_ERR(timer->clk)) {
+		ret = PTR_ERR(timer->clk);
+		pr_err("Timer clock not found! (error %d)\n", ret);
+		goto error_unmap;
+	}
+
+	timer->interrupt_regs = of_iomap(node, 1);
+	timer->irqnr = irq_of_parse_and_map(node, 0);
+
+	of_address_to_resource(node, 0, &res);
+	scnprintf(timer->clocksource_name, sizeof(timer->clocksource_name),
+			"%llx.%s_clocksource",
+			(unsigned long long)res.start, node->name);
+
+	scnprintf(timer->clockevent_name, sizeof(timer->clockevent_name),
+			"%llx.%s_clockevent",
+			(unsigned long long)res.start, node->name);
+
+	if (timer->interrupt_regs && timer->irqnr) {
+		timer->clkevt.name	= timer->clockevent_name;
+		timer->clkevt.set_next_event = nspire_timer_set_event;
+		timer->clkevt.set_mode	= nspire_timer_set_mode;
+		timer->clkevt.rating	= 200;
+		timer->clkevt.shift	= 32;
+		timer->clkevt.cpumask	= cpu_all_mask;
+		timer->clkevt.features	=
+			CLOCK_EVT_FEAT_ONESHOT;
+
+		writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+		writel(0, timer->timer1 + IO_DIVIDER);
+
+		/* Mask out interrupts except the one we're using */
+		writel((1<<0), timer->interrupt_regs + IO_INTR_MSK);
+		writel(0x3F, timer->interrupt_regs + IO_INTR_ACK);
+
+		/* Interrupt to occur when timer value matches 0 */
+		writel(0, timer->base + IO_MATCH1);
+
+		timer->clkevt_irq.name	= timer->clockevent_name;
+		timer->clkevt_irq.handler = nspire_timer_interrupt;
+		timer->clkevt_irq.dev_id = timer;
+		timer->clkevt_irq.flags	=
+			IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
+
+		setup_irq(timer->irqnr, &timer->clkevt_irq);
+
+		clockevents_config_and_register(&timer->clkevt,
+				clk_get_rate(timer->clk), 0x0001, 0xfffe);
+		pr_info("Added %s as clockevent\n", timer->clockevent_name);
+	}
+
+	writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
+			timer->timer2 + IO_CONTROL);
+
+	clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
+			timer->clocksource_name,
+			clk_get_rate(timer->clk),
+			200, 16,
+			clocksource_mmio_readw_up);
+
+	pr_info("Added %s as clocksource\n", timer->clocksource_name);
+
+	return 0;
+error_unmap:
+	iounmap(timer->base);
+error_free:
+	kfree(timer);
+	return ret;
+}
+
+CLOCKSOURCE_OF_DECLARE(nspire_classic_timer, DT_COMPAT, nspire_timer_add);
-- 
1.8.1.3



From dt.tangr at gmail.com  Sun May 12 00:23:00 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:23:00 +1000
Subject: [RFC PATCHv3 5/6] input: Add TI-Nspire keypad driver
In-Reply-To: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1368332581-94691-6-git-send-email-dt.tangr@gmail.com>


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 drivers/input/keyboard/Kconfig         |  10 ++
 drivers/input/keyboard/Makefile        |   1 +
 drivers/input/keyboard/nspire-keypad.c | 315 +++++++++++++++++++++++++++++++++
 3 files changed, 326 insertions(+)
 create mode 100644 drivers/input/keyboard/nspire-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 62a2c0e..bdbda87 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -418,6 +418,16 @@ config KEYBOARD_NOMADIK
 	  To compile this driver as a module, choose M here: the
 	  module will be called nmk-ske-keypad.
 
+config KEYBOARD_NSPIRE
+	tristate "TI-NSPIRE builtin keyboard"
+	depends on ARCH_NSPIRE
+	select INPUT_MATRIXKMAP
+	help
+	  Say Y here if you want to use the builtin keypad on the TI-NSPIRE.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called nspire-keypad.
+
 config KEYBOARD_TEGRA
 	tristate "NVIDIA Tegra internal matrix keyboard controller support"
 	depends on ARCH_TEGRA && OF
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 0c43e8c..a699b61 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_KEYBOARD_MCS)		+= mcs_touchkey.o
 obj-$(CONFIG_KEYBOARD_MPR121)		+= mpr121_touchkey.o
 obj-$(CONFIG_KEYBOARD_NEWTON)		+= newtonkbd.o
 obj-$(CONFIG_KEYBOARD_NOMADIK)		+= nomadik-ske-keypad.o
+obj-$(CONFIG_KEYBOARD_NSPIRE)		+= nspire-keypad.o
 obj-$(CONFIG_KEYBOARD_OMAP)		+= omap-keypad.o
 obj-$(CONFIG_KEYBOARD_OMAP4)		+= omap4-keypad.o
 obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
diff --git a/drivers/input/keyboard/nspire-keypad.c b/drivers/input/keyboard/nspire-keypad.c
new file mode 100644
index 0000000..e863f14
--- /dev/null
+++ b/drivers/input/keyboard/nspire-keypad.c
@@ -0,0 +1,315 @@
+/*
+ *  linux/drivers/input/keyboard/nspire-keypad.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/input/matrix_keypad.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#define KEYPAD_SCAN_MODE	0x00
+#define KEYPAD_CNTL		0x04
+#define KEYPAD_INT		0x08
+#define KEYPAD_INTMSK		0x0C
+
+#define KEYPAD_DATA		0x10
+#define KEYPAD_GPIO		0x30
+
+#define KEYPAD_UNKNOWN_INT	0x40
+#define KEYPAD_UNKNOWN_INT_STS	0x44
+
+#define KEYPAD_BITMASK_COLS	11
+#define KEYPAD_BITMASK_ROWS	8
+
+struct nspire_keypad {
+	spinlock_t lock;
+
+	void __iomem *reg_base;
+	int irq;
+	u32 int_mask;
+
+	struct input_dev *input;
+	struct clk *clk;
+
+	struct matrix_keymap_data *keymap;
+	int row_shift;
+
+	/* Maximum delay estimated assuming 33MHz APB */
+	u32 scan_interval;	/* In microseconds (~2000us max) */
+	u32 row_delay;		/* In microseconds (~500us max) */
+
+	bool active_low;
+};
+
+static inline void nspire_report_state(struct nspire_keypad *keypad,
+		int row, int col, unsigned int state)
+{
+	int code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+	unsigned short *keymap = keypad->input->keycode;
+
+	state = keypad->active_low ? !state : !!state;
+	input_report_key(keypad->input, keymap[code], state);
+}
+
+static irqreturn_t nspire_keypad_irq(int irq, void *dev_id)
+{
+	struct nspire_keypad *keypad = dev_id;
+	u32 int_sts;
+	u16 state[8];
+	int row, col;
+
+	int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask;
+
+	if (!int_sts)
+		return IRQ_NONE;
+
+	spin_lock(&keypad->lock);
+
+	memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state));
+
+	for (row = 0; row < KEYPAD_BITMASK_ROWS; row++) {
+		u16 bits = state[row];
+		for (col = 0; col < KEYPAD_BITMASK_COLS; col++)
+			nspire_report_state(keypad, row, col, bits & (1<<col));
+	}
+	input_sync(keypad->input);
+	writel(0x3, keypad->reg_base + KEYPAD_INT);
+
+	spin_unlock(&keypad->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int nspire_keypad_chip_init(struct nspire_keypad *keypad)
+{
+	unsigned long val = 0, cycles_per_us, delay_cycles, row_delay_cycles;
+
+	cycles_per_us = (clk_get_rate(keypad->clk) / 1000000);
+	if (cycles_per_us == 0)
+		cycles_per_us = 1;
+
+	delay_cycles = cycles_per_us * keypad->scan_interval;
+	WARN_ON(delay_cycles >= (1<<16)); /* Overflow */
+	delay_cycles &= 0xffff;
+
+	row_delay_cycles = cycles_per_us * keypad->row_delay;
+	WARN_ON(row_delay_cycles >= (1<<14)); /* Overflow */
+	row_delay_cycles &= 0x3fff;
+
+
+	val |= (3<<0); /* Set scan mode to 3 (continuous scan) */
+	val |= (row_delay_cycles<<2); /* Delay between scanning each row */
+	val |= (delay_cycles<<16); /* Delay between scans */
+	writel(val, keypad->reg_base + KEYPAD_SCAN_MODE);
+
+	val = (KEYPAD_BITMASK_ROWS & 0xff) | (KEYPAD_BITMASK_COLS & 0xff)<<8;
+	writel(val, keypad->reg_base + KEYPAD_CNTL);
+
+	/* Enable interrupts */
+	keypad->int_mask = (1<<1);
+	writel(keypad->int_mask, keypad->reg_base + 0xc);
+
+	/* Disable GPIO interrupts to prevent hanging on touchpad */
+	/* Possibly used to detect touchpad events */
+	writel(0, keypad->reg_base + KEYPAD_UNKNOWN_INT);
+	/* Acknowledge existing interrupts */
+	writel(~0, keypad->reg_base + KEYPAD_UNKNOWN_INT_STS);
+
+	return 0;
+}
+
+static int nspire_keypad_probe(struct platform_device *pdev)
+{
+	const struct device_node *of_node = pdev->dev.of_node;
+	struct nspire_keypad *keypad;
+	struct input_dev *input;
+	struct resource *res;
+	struct clk *clk;
+	int irq, error;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "failed to get keypad irq\n");
+		return -EINVAL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "missing platform resources\n");
+		return -EINVAL;
+	}
+
+	clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "unable to get clock\n");
+		return -EINVAL;
+	}
+
+	clk_prepare(clk);
+	error = clk_enable(clk);
+	if (error)
+		goto err_put_clk;
+
+	keypad = kzalloc(sizeof(struct nspire_keypad), GFP_KERNEL);
+	input = input_allocate_device();
+	if (!keypad || !input) {
+		dev_err(&pdev->dev, "failed to allocate keypad memory\n");
+		error = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	error = of_property_read_u32(of_node, "scan-interval",
+			&keypad->scan_interval);
+	if (error) {
+		dev_err(&pdev->dev, "failed to get scan-interval\n");
+		goto err_free_mem;
+	}
+
+	error = of_property_read_u32(of_node, "row-delay",
+			&keypad->row_delay);
+	if (error) {
+		dev_err(&pdev->dev, "failed to get row-delay\n");
+		goto err_free_mem;
+	}
+
+	keypad->active_low = of_property_read_bool(of_node,
+			"active-low");
+
+	keypad->keymap = NULL;
+
+	keypad->row_shift = get_count_order(KEYPAD_BITMASK_COLS);
+	keypad->irq = irq;
+	keypad->clk = clk;
+	keypad->input = input;
+	spin_lock_init(&keypad->lock);
+
+	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+		dev_err(&pdev->dev, "failed to request I/O memory\n");
+		error = -EBUSY;
+		goto err_free_mem;
+	}
+
+	keypad->reg_base = ioremap(res->start, resource_size(res));
+	if (!keypad->reg_base) {
+		dev_err(&pdev->dev, "failed to remap I/O memory\n");
+		error = -ENXIO;
+		goto err_free_mem_region;
+	}
+
+	input->id.bustype = BUS_HOST;
+	input->name = "nspire-keypad";
+	input->dev.parent = &pdev->dev;
+
+	set_bit(EV_KEY, input->evbit);
+	set_bit(EV_REP, input->evbit);
+
+	error = matrix_keypad_build_keymap(keypad->keymap, "keymap",
+			KEYPAD_BITMASK_ROWS, KEYPAD_BITMASK_COLS, NULL, input);
+	if (error) {
+		dev_err(&pdev->dev, "building keymap failed\n");
+		goto err_iounmap;
+	}
+
+	error = nspire_keypad_chip_init(keypad);
+	if (error) {
+		dev_err(&pdev->dev, "unable to init keypad hardware\n");
+		goto err_iounmap;
+	}
+
+	error = request_irq(keypad->irq, nspire_keypad_irq, 0,
+			"nspire_keypad", keypad);
+	if (error) {
+		dev_err(&pdev->dev, "allocate irq %d failed\n", keypad->irq);
+		goto err_iounmap;
+	}
+
+	error = input_register_device(input);
+	if (error) {
+		dev_err(&pdev->dev,
+				"unable to register input device: %d\n", error);
+		goto err_free_irq;
+	}
+
+	platform_set_drvdata(pdev, keypad);
+
+	dev_info(&pdev->dev, "TI-NSPIRE keypad at %#08x ("
+			"scan_interval=%uus,row_delay=%uus"
+			"%s)\n", res->start,
+			keypad->row_delay,
+			keypad->scan_interval,
+			keypad->active_low ? ",active_low" : "");
+
+	return 0;
+
+err_free_irq:
+	free_irq(keypad->irq, keypad);
+err_iounmap:
+	iounmap(keypad->reg_base);
+err_free_mem_region:
+	release_mem_region(res->start, resource_size(res));
+err_free_mem:
+	input_free_device(input);
+	kfree(keypad);
+
+	clk_disable(clk);
+err_put_clk:
+	clk_unprepare(clk);
+	clk_put(clk);
+	return error;
+}
+
+static int nspire_keypad_remove(struct platform_device *pdev)
+{
+	struct nspire_keypad *keypad = platform_get_drvdata(pdev);
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	free_irq(keypad->irq, keypad);
+
+	input_unregister_device(keypad->input);
+
+	iounmap(keypad->reg_base);
+	release_mem_region(res->start, resource_size(res));
+	kfree(keypad);
+
+	clk_disable(keypad->clk);
+	clk_unprepare(keypad->clk);
+	clk_put(keypad->clk);
+
+	return 0;
+}
+#ifdef CONFIG_OF
+static const struct of_device_id nspire_keypad_dt_match[] = {
+	{ .compatible = "nspire-keypad" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, nspire_keypad_dt_match);
+#endif
+
+static struct platform_driver nspire_keypad_driver = {
+	.driver = {
+		.name = "nspire-keypad",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_match_ptr(nspire_keypad_dt_match),
+	},
+	.remove = nspire_keypad_remove,
+	.probe = nspire_keypad_probe,
+};
+
+module_platform_driver(nspire_keypad_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("TI-NSPIRE Keypad Driver");
-- 
1.8.1.3



From dt.tangr at gmail.com  Sun May 12 00:23:01 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 14:23:01 +1000
Subject: [RFC PATCHv3 6/6] irqchip: Add TI-Nspire irqchip
In-Reply-To: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1368332581-94691-7-git-send-email-dt.tangr@gmail.com>


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 drivers/irqchip/Makefile             |   1 +
 drivers/irqchip/irq-nspire-classic.c | 177 +++++++++++++++++++++++++++++++++++
 2 files changed, 178 insertions(+)
 create mode 100644 drivers/irqchip/irq-nspire-classic.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5..056ad7d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
 obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_NSPIRE)		+= irq-nspire-classic.o
 obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
diff --git a/drivers/irqchip/irq-nspire-classic.c b/drivers/irqchip/irq-nspire-classic.c
new file mode 100644
index 0000000..9e6413a
--- /dev/null
+++ b/drivers/irqchip/irq-nspire-classic.c
@@ -0,0 +1,177 @@
+/*
+ *  linux/drivers/irqchip/irq-nspire-classic.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+
+#include "irqchip.h"
+
+#define IO_STATUS	0x000
+#define IO_RAW_STATUS	0x004
+#define IO_ENABLE	0x008
+#define IO_DISABLE	0x00C
+#define IO_CURRENT	0x020
+#define IO_RESET	0x028
+#define IO_MAX_PRIOTY	0x02C
+
+#define IO_IRQ_BASE	0x000
+#define IO_FIQ_BASE	0x100
+
+#define IO_INVERT_SEL	0x200
+#define IO_STICKY_SEL	0x204
+#define IO_PRIORITY_SEL	0x300
+
+#define MAX_INTRS	32
+#define FIQ_START	MAX_INTRS
+
+
+static void __iomem *irq_io_base;
+static struct irq_domain *nspire_irq_domain;
+
+static void nspire_irq_ack(struct irq_data *irqd)
+{
+	void __iomem *base = irq_io_base;
+
+	if (irqd->hwirq < FIQ_START)
+		base += IO_IRQ_BASE;
+	else
+		base += IO_FIQ_BASE;
+
+	readl(base + IO_RESET);
+}
+
+static void nspire_irq_unmask(struct irq_data *irqd)
+{
+	void __iomem *base = irq_io_base;
+	int irqnr = irqd->hwirq;
+
+	if (irqnr < FIQ_START) {
+		base += IO_IRQ_BASE;
+	} else {
+		irqnr -= MAX_INTRS;
+		base += IO_FIQ_BASE;
+	}
+
+	writel((1<<irqnr), base + IO_ENABLE);
+}
+
+static void nspire_irq_mask(struct irq_data *irqd)
+{
+	void __iomem *base = irq_io_base;
+	int irqnr = irqd->hwirq;
+
+	if (irqnr < FIQ_START) {
+		base += IO_IRQ_BASE;
+	} else {
+		irqnr -= FIQ_START;
+		base += IO_FIQ_BASE;
+	}
+
+	writel((1<<irqnr), base + IO_DISABLE);
+}
+
+static struct irq_chip nspire_irq_chip = {
+	.name		= "nspire_irq",
+	.irq_ack	= nspire_irq_ack,
+	.irq_mask	= nspire_irq_mask,
+	.irq_unmask	= nspire_irq_unmask,
+};
+
+
+static int nspire_irq_map(struct irq_domain *dom, unsigned int virq,
+		irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &nspire_irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops nspire_irq_ops = {
+	.map = nspire_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static void init_base(void __iomem *base)
+{
+	/* Disable all interrupts */
+	writel(~0, base + IO_DISABLE);
+
+	/* Accept interrupts of all priorities */
+	writel(0xF, base + IO_MAX_PRIOTY);
+
+	/* Reset existing interrupts */
+	readl(base + IO_RESET);
+}
+
+static int process_base(void __iomem *base, struct pt_regs *regs)
+{
+	int irqnr;
+
+
+	if (!readl(base + IO_STATUS))
+		return 0;
+
+	irqnr = readl(base + IO_CURRENT);
+	irqnr = irq_find_mapping(nspire_irq_domain, irqnr);
+	handle_IRQ(irqnr, regs);
+
+	return 1;
+}
+
+asmlinkage void __exception_irq_entry nspire_handle_irq(struct pt_regs *regs)
+{
+	while (process_base(irq_io_base + IO_FIQ_BASE, regs))
+		;
+	while (process_base(irq_io_base + IO_IRQ_BASE, regs))
+		;
+}
+
+static int __init nspire_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	if (WARN_ON(irq_io_base))
+		return -EBUSY;
+
+	irq_io_base = of_iomap(node, 0);
+	BUG_ON(!irq_io_base);
+
+	/* Do not invert interrupt status bits */
+	writel(~0, irq_io_base + IO_INVERT_SEL);
+
+	/* Disable sticky interrupts */
+	writel(0, irq_io_base + IO_STICKY_SEL);
+
+	/* We don't use IRQ priorities. Set each IRQ to highest priority. */
+	memset_io(irq_io_base + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));
+
+	/* Init IRQ and FIQ */
+	init_base(irq_io_base + IO_IRQ_BASE);
+	init_base(irq_io_base + IO_FIQ_BASE);
+
+	nspire_irq_domain = irq_domain_add_linear(node, MAX_INTRS,
+						 &nspire_irq_ops, NULL);
+
+	BUG_ON(!nspire_irq_domain);
+
+	set_handle_irq(nspire_handle_irq);
+
+	pr_info("TI-NSPIRE classic IRQ controller\n");
+	return 0;
+}
+
+IRQCHIP_DECLARE(nspire_classic_irq, "nspire-classic-intc", nspire_of_init);
-- 
1.8.1.3



From gmbnomis at gmail.com  Sun May 12 01:35:56 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Sun, 12 May 2013 07:35:56 +0200
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
Message-ID: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>

Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
it needs to handle are kernel mapped only.  However, for example when doing
direct I/O, pages with user space mappings may occur.

Thus, continue to do lazy flushing if there are no user space mappings.
Otherwise, flush the kernel cache lines directly.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Russell King <linux at arm.linux.org.uk>
---

Changes:

in V4:
- get back to simpler version of flush_kernel_dcache_page() and use the
  logic from __flush_dcache_page() to flush the kernel mapping (which
  also takes care of highmem pages)

in V3:
- Followed Catalin's suggestion to reverse the order of the patches

in V2:
- flush_kernel_dcache_page() follows flush_dcache_page() now, except that it
  does not flush the user mappings


 arch/arm/include/asm/cacheflush.h |    4 +---
 arch/arm/mm/flush.c               |   38 +++++++++++++++++++++++++++++++------
 2 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index bff7138..17d0ae8 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -320,9 +320,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 }
 
 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-static inline void flush_kernel_dcache_page(struct page *page)
-{
-}
+extern void flush_kernel_dcache_page(struct page *);
 
 #define flush_dcache_mmap_lock(mapping) \
 	spin_lock_irq(&(mapping)->tree_lock)
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 0d473cc..485ca96 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -160,13 +160,13 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 #endif
 }
 
-void __flush_dcache_page(struct address_space *mapping, struct page *page)
+/*
+ * Writeback any data associated with the kernel mapping of this
+ * page.  This ensures that data in the physical page is mutually
+ * coherent with the kernel's mapping.
+ */
+static void __flush_kernel_dcache_page(struct page *page)
 {
-	/*
-	 * Writeback any data associated with the kernel mapping of this
-	 * page.  This ensures that data in the physical page is mutually
-	 * coherent with the kernels mapping.
-	 */
 	if (!PageHighMem(page)) {
 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 	} else {
@@ -184,6 +184,11 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
 			}
 		}
 	}
+}
+
+void __flush_dcache_page(struct address_space *mapping, struct page *page)
+{
+	__flush_kernel_dcache_page(page);
 
 	/*
 	 * If this is a page cache page, and we have an aliasing VIPT cache,
@@ -301,6 +306,27 @@ void flush_dcache_page(struct page *page)
 EXPORT_SYMBOL(flush_dcache_page);
 
 /*
+ * Ensure cache coherency for kernel mapping of this page.
+ *
+ * If the page only exists in the page cache and there are no user
+ * space mappings, this is a no-op since the page was already marked
+ * dirty at creation.  Otherwise, we need to flush the dirty kernel
+ * cache lines directly.
+ */
+void flush_kernel_dcache_page(struct page *page)
+{
+	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
+		struct address_space *mapping;
+
+		mapping = page_mapping(page);
+
+		if (!mapping || mapping_mapped(mapping))
+			__flush_kernel_dcache_page(page);
+	}
+}
+EXPORT_SYMBOL(flush_kernel_dcache_page);
+
+/*
  * Flush an anonymous page so that users of get_user_pages()
  * can safely access the data.  The expected sequence is:
  *
-- 
1.7.9.5



From gleb at redhat.com  Sun May 12 05:03:59 2013
From: gleb at redhat.com (Gleb Natapov)
Date: Sun, 12 May 2013 12:03:59 +0300
Subject: [RFC PATCH 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
In-Reply-To: <5183DDD5.6000202@arm.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <CAAhSdy3s+beJRwh_BzsyHTkjeRFaSm4nac1WFRo6oEWYBQNx_g@mail.gmail.com>
 <5183DDD5.6000202@arm.com>
Message-ID: <20130512090359.GE10830@redhat.com>

On Fri, May 03, 2013 at 04:55:01PM +0100, Marc Zyngier wrote:
> On 03/05/13 16:31, Anup Patel wrote:
> > On Fri, May 3, 2013 at 7:32 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> >> As KVM/arm64 is looming on the horizon, it makes sense to move some
> >> of the common code to a single location in order to reduce duplication.
> >>
> >> The code could live anywhere. Actually, most of KVM is already built
> >> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
> >> not exactly talking about style here. But maybe it is time to start
> >> moving into a less ugly direction.
> >>
> >> The include files must be in a "public" location, as they are accessed
> >> from non-KVM files (arch/arm/kernel/asm-offsets.c).
> >>
> >> For this purpose, introduce two new locations:
> >> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
> >>   virt/kvm, so this could be seen as a (very ugly) precedent.
> >> - include/kvm/  : there is already an include/xen, and while the
> >>   intent is slightly different, this seems as good a location as
> >>   any
> >>
> >> Once the code has been moved, it becomes easy to build it in a
> >> less hackish way, which makes the code easily reusable by KVM/arm64.
> >>
> >> Marc Zyngier (2):
> >>   ARM: KVM: move GIC/timer code to a common location
> >>   ARM: KVM: standalone Makefile for vgic and timers
> >>
> >>  Makefile                                               | 2 +-
> >>  arch/arm/include/asm/kvm_host.h                        | 4 ++--
> >>  arch/arm/kvm/Makefile                                  | 5 ++---
> >>  {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
> >>  {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
> >>  virt/Makefile                                          | 1 +
> >>  virt/kvm/Makefile                                      | 1 +
> >>  virt/kvm/arm/Makefile                                  | 2 ++
> >>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
> >>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
> >>  10 files changed, 11 insertions(+), 8 deletions(-)
> >>  rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
> >>  rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
> >>  create mode 100644 virt/Makefile
> >>  create mode 100644 virt/kvm/Makefile
> >>  create mode 100644 virt/kvm/arm/Makefile
> >>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
> >>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
> >>
> >> --
> >> 1.8.2.1
> >>
> >>
> >>
> >> _______________________________________________
> >> kvmarm mailing list
> >> kvmarm at lists.cs.columbia.edu
> >> https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
> > 
> > The source files arch/arm/kvm/arm.c and arch/arm/kvm/mmu.c are also
> > shared between KVM ARM and KVM ARM64.
> > 
> > Can we move these files in virt/arm ?
> 
> I suggest we start by finding out if there is an agreement on the
> location, method and overall usefulness of this particular patch.
> 
> Moving core ARM code around is quite different from sharing what is
> basically device emulation stuff.
> 
Yes, so the question in this regard: are there any plans to eventually
merge arch/arm and arch/arm64 like it happened with arch/i386
and arch/x86_64?  Is it even feasible?  Looking at the dark days of
i386/x86_64 split there were a lot of ../../i386/ and -Iarch/i386/kernel
in arch/x86_64. Isn't there some code, outside of kvm, that can be shared
between arm/arm64? How will it be shared?

--
			Gleb.


From linux at arm.linux.org.uk  Sun May 12 05:06:10 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 12 May 2013 10:06:10 +0100
Subject: [RFC PATCHv3 1/6] arm: Initial TI-Nspire support
In-Reply-To: <1368332581-94691-2-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-2-git-send-email-dt.tangr@gmail.com>
Message-ID: <20130512090610.GF18614@n2100.arm.linux.org.uk>

On Sun, May 12, 2013 at 02:22:56PM +1000, Daniel Tang wrote:
> diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
> new file mode 100644
> index 0000000..a4b9f06
> --- /dev/null
> +++ b/arch/arm/mach-nspire/clcd.c
> @@ -0,0 +1,117 @@
> +/*
> + *	linux/arch/arm/mach-nspire/clcd.c
> + *
> + *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2, as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/amba/bus.h>
> +#include <linux/amba/clcd.h>
> +#include <linux/dma-mapping.h>
> +
> +static struct clcd_panel nspire_cx_lcd_panel = {
> +	.mode		= {
> +		.name		= "Color LCD",
> +		.refresh	= 60,
> +		.xres		= 320,
> +		.yres		= 240,
> +		.sync		= 0,
> +		.vmode		= FB_VMODE_NONINTERLACED,
> +		.pixclock	= 1,
> +		.hsync_len	= 6,
> +		.vsync_len	= 1,
> +		.right_margin	= 50,
> +		.left_margin	= 38,
> +		.lower_margin	= 3,
> +		.upper_margin	= 17,
> +	},
> +	.width		= 65, /* ~6.50 cm */
> +	.height		= 49, /* ~4.87 cm */
> +	.tim2		= TIM2_IPC,
> +	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
> +	.bpp		= 16,
> +};
> +
> +static struct clcd_panel nspire_classic_lcd_panel = {
> +	.mode		= {
> +		.name		= "Grayscale LCD",
> +		.refresh	= 60,
> +		.xres		= 320,
> +		.yres		= 240,
> +		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
> +		.vmode		= FB_VMODE_NONINTERLACED,
> +		.pixclock	= 1,
> +		.hsync_len	= 6,
> +		.vsync_len	= 1,
> +		.right_margin	= 6,
> +		.left_margin	= 6,
> +	},
> +	.width		= 71, /* 7.11cm */
> +	.height		= 53, /* 5.33cm */
> +	.tim2		= 0x80007d0,
> +	.cntl		= CNTL_LCDMONO8,
> +	.bpp		= 8,
> +	.grayscale	= 1
> +};

Still no capabilities in the above - how does the CLCD controller know
which of BGR or RGB output and which format these panels support?

Each entry needs a .caps = CLCD_CAP_xxx | CLCD_CAP_xxx listing the
formats supported there.

Unless panels and the board have a .caps entry, the caps system won't
be used.

> +static struct clcd_board nspire_clcd_data = {
> +       .name           = "LCD",
> +       .caps           = CLCD_CAP_ALL,

Your board has logic to support the RGB444/BGR444 mode?  If not, setting
CLCD_CAP_ALL is incorrect.


From dt.tangr at gmail.com  Sun May 12 05:22:45 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 12 May 2013 19:22:45 +1000
Subject: [RFC PATCHv3 1/6] arm: Initial TI-Nspire support
In-Reply-To: <20130512090610.GF18614@n2100.arm.linux.org.uk>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-2-git-send-email-dt.tangr@gmail.com>
 <20130512090610.GF18614@n2100.arm.linux.org.uk>
Message-ID: <453A23B8-7FE0-42D6-BBEC-B6CC3604EE01@gmail.com>


On 12/05/2013, at 7:06 PM, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> On Sun, May 12, 2013 at 02:22:56PM +1000, Daniel Tang wrote:
>> 
>> +	.bpp		= 8,
>> +	.grayscale	= 1
>> +};
> 
> Still no capabilities in the above - how does the CLCD controller know
> which of BGR or RGB output and which format these panels support?
> 
> Each entry needs a .caps = CLCD_CAP_xxx | CLCD_CAP_xxx listing the
> formats supported there.
> 
> Unless panels and the board have a .caps entry, the caps system won't
> be used.

Fair enough.

> 
>> +static struct clcd_board nspire_clcd_data = {
>> +       .name           = "LCD",
>> +       .caps           = CLCD_CAP_ALL,
> 
> Your board has logic to support the RGB444/BGR444 mode?  If not, setting
> CLCD_CAP_ALL is incorrect.

I believe the grayscale panel supports the xGx444 modes - unsure about the colour one. Since I'm using the same struct clcd_board for both panels, I thought I'd just set caps to work with both to simplify.

Should I set board caps to panel caps on setup?

Cheers,

From linux at prisktech.co.nz  Sun May 12 05:23:54 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sun, 12 May 2013 21:23:54 +1200
Subject: [PATCH] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs
Message-ID: <1368350634-12654-1-git-send-email-linux@prisktech.co.nz>

This patch adds support for the I2C bus controllers found on Wondermedia
8xxx-series SoCs. Only master-mode is supported.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 MAINTAINERS                                        |    1 +
 drivers/i2c/busses/Kconfig                         |   10 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  488 ++++++++++++++++++++
 5 files changed, 524 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 0000000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+	Valid values are 100000 and 400000.
+	Default to 100000 if not specified, or invalid value.
+
+Example :
+
+	i2c_0: i2c at d8280000 {
+		compatible = "wm,wm8505-i2c";
+		reg = <0xd8280000 0x1000>;
+		interrupts = <19>;
+		clocks = <&clki2c0>;
+		clock-frequency = <400000>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7782b..44ea994 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1285,6 +1285,7 @@ S:	Maintained
 F:	arch/arm/mach-vt8500/
 F:	drivers/clocksource/vt8500_timer.c
 F:	drivers/gpio/gpio-vt8500.c
+F:	drivers/i2c/busses/i2c-wmt.c
 F:	drivers/mmc/host/wmt-sdmmc.c
 F:	drivers/pwm/pwm-vt8500.c
 F:	drivers/rtc/rtc-vt8500.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 631736e..89e7ec2 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -724,6 +724,16 @@ config I2C_VERSATILE
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-versatile.
 
+config I2C_WMT
+	tristate "Wondermedia WM8xxx SoC I2C bus support"
+	depends on ARCH_VT8500
+	help
+	  Say yes if you want to support the I2C bus on Wondermedia 8xxx-series
+	  SoCs.
+
+	  This driver can also be built as a module. If so, the module will be
+	  called i2c-wmt.
+
 config I2C_OCTEON
 	tristate "Cavium OCTEON I2C bus support"
 	depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..3ba94a9 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)		+= i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)	+= i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 0000000..5cebb29
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,488 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ *  Derived from GPLv2+ licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2, or
+ *  (at your option) any later version. as published by the Free Software
+ *  Foundation
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define REG_CR		0x00
+#define REG_TCR		0x02
+#define REG_CSR		0x04
+#define REG_ISR		0x06
+#define REG_IMR		0x08
+#define REG_CDR		0x0A
+#define REG_TR		0x0C
+#define REG_MCR		0x0E
+#define REG_SLAVE_CR	0x10
+#define REG_SLAVE_SR	0x12
+#define REG_SLAVE_ISR	0x14
+#define REG_SLAVE_IMR	0x16
+#define REG_SLAVE_DR	0x18
+#define REG_SLAVE_TR	0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK		0x0000
+#define CR_ENABLE		0x0001
+#define CR_TX_NEXT_NO_ACK	0x0002
+#define CR_TX_END		0x0004
+#define CR_CPU_RDY		0x0008
+#define SLAV_MODE_SEL		0x8000
+
+/* REG_TCR Bit fields */
+#define TCR_STANDARD_MODE	0x0000
+#define TCR_MASTER_WRITE	0x0000
+#define TCR_HS_MODE		0x2000
+#define TCR_MASTER_READ		0x4000
+#define TCR_FAST_MODE		0x8000
+#define TCR_SLAVE_ADDR_MASK	0x007F
+
+/* REG_ISR Bit fields */
+#define ISR_NACK_ADDR		0x0001
+#define ISR_BYTE_END		0x0002
+#define ISR_SCL_TIMEOUT		0x0004
+#define ISR_WRITE_ALL		0x0007
+
+/* REG_IMR Bit fields */
+#define IMR_ENABLE_ALL		0x0007
+
+/* REG_CSR Bit fields */
+#define CSR_RCV_NOT_ACK		0x0001
+#define CSR_RCV_ACK_MASK	0x0001
+#define CSR_READY_MASK		0x0002
+
+/* REG_TR */
+#define SCL_TIMEOUT(x)		(((x) & 0xFF) << 16)
+#define TR_STD			0x0064
+#define TR_HS			0x0019
+
+#define I2C_MODE_STANDARD	0
+#define I2C_MODE_FAST		1
+
+struct wmt_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct completion	complete;
+	struct device		*dev;
+	void __iomem		*base;
+	struct clk		*clk;
+	int			mode;
+	int			irq;
+	u16			cmd_status;
+};
+
+static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
+{
+	u16 val;
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < 100000; i++) {
+		val = readw(i2c_dev->base + REG_CSR);
+		if (val & CSR_READY_MASK)
+			break;
+
+		udelay(1);
+	}
+	if (i >= 9999999)
+		ret = -EBUSY;
+
+	return ret;
+}
+
+static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
+{
+	int ret = 0;
+
+	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
+		ret = -EIO;
+
+	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
+		ret = -ETIMEDOUT;
+
+	return ret;
+}
+
+static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						   int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val, tcr_val;
+	int ret, wait_result;
+	int xfer_len = 0;
+
+	if (!restart) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (pmsg->len == 0) {
+		/*
+		 * We still need to run through the while (..) once, so
+		 * start at -1 and break out early from the loop
+		 */
+		xfer_len = -1;
+		writew(0, i2c_dev->base + REG_CDR);
+	} else {
+		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
+	}
+
+	if (!restart) {
+		val = readw(i2c_dev->base + REG_CR);
+		val &= ~CR_TX_END;
+		writew(val, i2c_dev->base + REG_CR);
+
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	while (xfer_len < pmsg->len) {
+		wait_result = wait_for_completion_timeout(&i2c_dev->complete,
+							  500 * HZ / 1000);
+
+		if (wait_result == 0)
+			return -ETIMEDOUT;
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			return ret;
+
+		xfer_len++;
+
+		val = readw(i2c_dev->base + REG_CSR);
+		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
+			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
+			return -EIO;
+		}
+
+		if (pmsg->len == 0) {
+			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
+			writew(val, i2c_dev->base + REG_CR);
+			break;
+		}
+
+		if (xfer_len == pmsg->len) {
+			if (last != 1)
+				writew(CR_ENABLE, i2c_dev->base + REG_CR);
+		} else {
+			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
+								REG_CDR);
+			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
+		}
+	}
+
+	return 0;
+}
+
+static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						  int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val, tcr_val;
+	int ret, wait_result;
+	u32 xfer_len = 0;
+
+	if (!restart) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_END;
+	writew(val, i2c_dev->base + REG_CR);
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_NEXT_NO_ACK;
+	writew(val, i2c_dev->base + REG_CR);
+
+	if (!restart) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	if (pmsg->len == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_TX_NEXT_NO_ACK;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	while (xfer_len < pmsg->len) {
+		wait_result = wait_for_completion_timeout(&i2c_dev->complete,
+							  500 * HZ / 1000);
+
+		if (!wait_result)
+			return -ETIMEDOUT;
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			return ret;
+
+		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
+		xfer_len++;
+
+		if (xfer_len == pmsg->len - 1) {
+			val = readw(i2c_dev->base + REG_CR);
+			val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
+			writew(val, i2c_dev->base + REG_CR);
+		} else {
+			val = readw(i2c_dev->base + REG_CR);
+			val |= CR_CPU_RDY;
+			writew(val, i2c_dev->base + REG_CR);
+		}
+	}
+
+	return 0;
+}
+
+static int wmt_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg msgs[],
+			int num)
+{
+	struct i2c_msg *pmsg;
+	int i, is_last, restart;
+	int ret = 0;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		is_last = ((i + 1) == num);
+		restart = (i != 0);
+
+		pmsg = &msgs[i];
+		if (pmsg->flags & I2C_M_NOSTART)
+			restart = 1;
+		if (pmsg->flags & I2C_M_RD)
+			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
+		else
+			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
+	}
+
+	return (ret < 0) ? ret : i;
+}
+
+static u32 wmt_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
+}
+
+static const struct i2c_algorithm wmt_i2c_algo = {
+	.master_xfer	= wmt_i2c_xfer,
+	.functionality	= wmt_i2c_func,
+};
+
+static irqreturn_t wmt_i2c_isr(int irq, void *data)
+{
+	struct wmt_i2c_dev *i2c_dev = data;
+
+	/* save the status and write-clear it */
+	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
+	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
+
+	complete(&i2c_dev->complete);
+
+	return IRQ_HANDLED;
+}
+
+static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
+{
+	int err;
+
+	err = clk_prepare_enable(i2c_dev->clk);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to enable clock\n");
+		return err;
+	}
+
+	err = clk_set_rate(i2c_dev->clk, 20000000);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
+		return err;
+	}
+
+	writew(0, i2c_dev->base + REG_CR);
+	writew(12, i2c_dev->base + REG_MCR);
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
+	writew(CR_ENABLE, i2c_dev->base + REG_CR);
+	readw(i2c_dev->base + REG_CSR);		/* read clear */
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
+	else
+		writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
+
+	return 0;
+}
+
+static int wmt_i2c_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct wmt_i2c_dev *i2c_dev;
+	struct i2c_adapter *adap;
+	struct resource *res;
+	int err;
+	u32 clk_rate;
+
+	if (!np) {
+		dev_err(&pdev->dev, "device node not found\n");
+		return -ENODEV;
+	}
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev) {
+		dev_err(&pdev->dev, "device memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(i2c_dev->base))
+		return PTR_ERR(i2c_dev->base);
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "irq missing or invalid\n");
+		return -EINVAL;
+	}
+
+	i2c_dev->clk = of_clk_get(np, 0);
+	if (IS_ERR(i2c_dev->clk)) {
+		dev_err(&pdev->dev, "unable to request clock\n");
+		return PTR_ERR(i2c_dev->clk);
+	}
+
+	i2c_dev->mode = I2C_MODE_STANDARD;
+	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
+	if ((!err) && (clk_rate == 400000))
+		i2c_dev->mode = I2C_MODE_FAST;
+
+	i2c_dev->dev = &pdev->dev;
+
+	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
+							"i2c", i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
+		return err;
+	}
+
+	adap = &i2c_dev->adapter;
+	i2c_set_adapdata(adap, i2c_dev);
+	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
+	adap->owner = THIS_MODULE;
+	adap->class = I2C_CLASS_HWMON;
+	adap->algo = &wmt_i2c_algo;
+	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
+	adap->nr = of_alias_get_id(pdev->dev.of_node, "i2c");
+
+	err = wmt_i2c_reset_hardware(i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "error initializing hardware\n");
+		return err;
+	}
+
+	if (adap->nr < 0)
+		err = i2c_add_adapter(adap);
+	else
+		err = i2c_add_numbered_adapter(adap);
+
+	if (err) {
+		dev_err(&pdev->dev, "failed to add adapter\n");
+		return err;
+	}
+
+	platform_set_drvdata(pdev, i2c_dev);
+
+	of_i2c_register_devices(adap);
+
+	return 0;
+}
+
+static int wmt_i2c_remove(struct platform_device *pdev)
+{
+	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	/* Disable interrupts, clock and delete adapter */
+	writew(0, i2c_dev->base + REG_IMR);
+	clk_disable_unprepare(i2c_dev->clk);
+	i2c_del_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static struct of_device_id wmt_i2c_dt_ids[] = {
+	{ .compatible = "wm,wm8505-i2c" },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver wmt_i2c_driver = {
+	.probe		= wmt_i2c_probe,
+	.remove		= wmt_i2c_remove,
+	.driver		= {
+		.name	= "wmt-i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = wmt_i2c_dt_ids,
+	},
+};
+
+module_platform_driver(wmt_i2c_driver);
+
+MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
+MODULE_AUTHOR("Tony Prisk <linux at prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
-- 
1.7.9.5



From catalin.marinas at arm.com  Sun May 12 06:23:18 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Sun, 12 May 2013 11:23:18 +0100
Subject: [RFC PATCH 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
In-Reply-To: <20130512090359.GE10830@redhat.com>
References: <1367589773-5609-1-git-send-email-marc.zyngier@arm.com>
 <CAAhSdy3s+beJRwh_BzsyHTkjeRFaSm4nac1WFRo6oEWYBQNx_g@mail.gmail.com>
 <5183DDD5.6000202@arm.com> <20130512090359.GE10830@redhat.com>
Message-ID: <20130512102317.GA58285@MacBook-Pro.local>

Hi Gleb,

On Sun, May 12, 2013 at 10:03:59AM +0100, Gleb Natapov wrote:
> On Fri, May 03, 2013 at 04:55:01PM +0100, Marc Zyngier wrote:
> > On 03/05/13 16:31, Anup Patel wrote:
> > > On Fri, May 3, 2013 at 7:32 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> > >> As KVM/arm64 is looming on the horizon, it makes sense to move some
> > >> of the common code to a single location in order to reduce duplication.
> > >>
> > >> The code could live anywhere. Actually, most of KVM is already built
> > >> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
> > >> not exactly talking about style here. But maybe it is time to start
> > >> moving into a less ugly direction.
> > >>
> > >> The include files must be in a "public" location, as they are accessed
> > >> from non-KVM files (arch/arm/kernel/asm-offsets.c).
> > >>
> > >> For this purpose, introduce two new locations:
> > >> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
> > >>   virt/kvm, so this could be seen as a (very ugly) precedent.
> > >> - include/kvm/  : there is already an include/xen, and while the
> > >>   intent is slightly different, this seems as good a location as
> > >>   any
> > >>
> > >> Once the code has been moved, it becomes easy to build it in a
> > >> less hackish way, which makes the code easily reusable by KVM/arm64.
> > >>
> > >> Marc Zyngier (2):
> > >>   ARM: KVM: move GIC/timer code to a common location
> > >>   ARM: KVM: standalone Makefile for vgic and timers
> > >>
> > >>  Makefile                                               | 2 +-
> > >>  arch/arm/include/asm/kvm_host.h                        | 4 ++--
> > >>  arch/arm/kvm/Makefile                                  | 5 ++---
> > >>  {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h | 0
> > >>  {arch/arm/include/asm => include/kvm}/kvm_vgic.h       | 0
> > >>  virt/Makefile                                          | 1 +
> > >>  virt/kvm/Makefile                                      | 1 +
> > >>  virt/kvm/arm/Makefile                                  | 2 ++
> > >>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c            | 4 ++--
> > >>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                  | 0
> > >>  10 files changed, 11 insertions(+), 8 deletions(-)
> > >>  rename {arch/arm/include/asm => include/kvm}/kvm_arch_timer.h (100%)
> > >>  rename {arch/arm/include/asm => include/kvm}/kvm_vgic.h (100%)
> > >>  create mode 100644 virt/Makefile
> > >>  create mode 100644 virt/kvm/Makefile
> > >>  create mode 100644 virt/kvm/arm/Makefile
> > >>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
> > >>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
> > > 
> > > The source files arch/arm/kvm/arm.c and arch/arm/kvm/mmu.c are also
> > > shared between KVM ARM and KVM ARM64.
> > > 
> > > Can we move these files in virt/arm ?
> > 
> > I suggest we start by finding out if there is an agreement on the
> > location, method and overall usefulness of this particular patch.
> > 
> > Moving core ARM code around is quite different from sharing what is
> > basically device emulation stuff.
> > 
> Yes, so the question in this regard: are there any plans to eventually
> merge arch/arm and arch/arm64 like it happened with arch/i386
> and arch/x86_64?  Is it even feasible?  Looking at the dark days of
> i386/x86_64 split there were a lot of ../../i386/ and -Iarch/i386/kernel
> in arch/x86_64. Isn't there some code, outside of kvm, that can be shared
> between arm/arm64? How will it be shared?

There are similarities between arm and arm64 (especially since the arm64
port started as a fork of arm) and few other bits that could be shared
but the benefits of a clean port outweigh a bit of code duplication.
Most of the SoC support is now going into drivers, so it's pretty much
architecture code left under arch/arm64.

KVM is the first to make references to ../arm/ from arm64 and I don't
see an easy solution (and I wouldn't like to see common arm/arm64 code
under the top kvm directory either, apart form device emulation). Of
course, a lot of the code like page table maintenance, mapping/unmapping
ranges is pretty generic and could be shared with other architectures
(e.g. x86) but it's not a trivial task.

-- 
Catalin


From maxime.ripard at free-electrons.com  Sun May 12 10:05:14 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 12 May 2013 16:05:14 +0200
Subject: [PATCH] irq-sun4i: Fix trivial build errors
In-Reply-To: <20130506142539.523110430@linutronix.de>
References: <20130506142539.523110430@linutronix.de>
Message-ID: <1368367514-21782-1-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe at obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Jean-Francois Moine <moinejf at free.fr>
Cc: Gerlando Falauto <gerlando.falauto at keymile.com>
Cc: Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/irqchip/irq-sun4i.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
index 0191f2c..cab36b1 100644
--- a/drivers/irqchip/irq-sun4i.c
+++ b/drivers/irqchip/irq-sun4i.c
@@ -46,7 +46,8 @@ static int __init sun4i_init_domain_chips(void)
 	struct irq_chip_generic *gc;
 	int i, ret, base = 0;
 
-	ret = irq_alloc_domain_generic_chips(d, SUN4I_IRQS_PER_CHIP, 1,
+	ret = irq_alloc_domain_generic_chips(sun4i_irq_domain,
+					     SUN4I_IRQS_PER_CHIP, 1,
 					     "sun4i_irq", handle_level_irq,
 					     clr, 0, IRQ_GC_INIT_MASK_CACHE);
 	if (ret)
@@ -57,9 +58,9 @@ static int __init sun4i_init_domain_chips(void)
 		gc->reg_base = sun4i_irq_base;
 		gc->chip_types[0].regs.mask = SUN4I_IRQ_ENABLE_REG(i);
 		gc->chip_types[0].regs.ack = SUN4I_IRQ_PENDING_REG(i);
-		gc->chip_types[0].chip.mask = irq_gc_mask_clr_bit;
-		gc->chip_types[0].chip.ack = irq_gc_ack_set_bit;
-		gc->chip_types[0].chip.unmask = irq_gc_mask_set_bit;
+		gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+		gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
+		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
 
 		/* Disable, mask and clear all pending interrupts */
 		writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(i));
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Sun May 12 10:08:13 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 12 May 2013 16:08:13 +0200
Subject: [patch 8/8] irqchip: sun4i: Convert to generic irq chip
In-Reply-To: <20130506142539.523110430@linutronix.de>
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
 <20130506142539.523110430@linutronix.de>
Message-ID: <518FA24D.80203@free-electrons.com>

Hi Thomas,

Le 06/05/2013 16:30, Thomas Gleixner a ?crit :
> Proof of concept patch to demonstrate the new irqdomain support for
> the generic irq chip. Untested !!
>
> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>
> Cc: Maxime Ripard <maxime.ripard at free-electrons.com>

I just tested it, and with the minor patch I sent, it's working fine.

You can add my
Acked-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Sun May 12 10:14:19 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 12 May 2013 16:14:19 +0200
Subject: [patch 8/8] irqchip: sun4i: Convert to generic irq chip
In-Reply-To: <518FA24D.80203@free-electrons.com>
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
 <20130506142539.523110430@linutronix.de> <518FA24D.80203@free-electrons.com>
Message-ID: <518FA3BB.7060806@free-electrons.com>

Le 12/05/2013 16:08, Maxime Ripard a ?crit :
> Hi Thomas,
> 
> Le 06/05/2013 16:30, Thomas Gleixner a ?crit :
>> Proof of concept patch to demonstrate the new irqdomain support for
>> the generic irq chip. Untested !!
>>
>> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
> 
> I just tested it, and with the minor patch I sent, it's working fine.
> 
> You can add my
> Acked-by: Maxime Ripard <maxime.ripard at free-electrons.com>

After addressing the comments RobH already made that is.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From shawn.guo at linaro.org  Sun May 12 10:21:44 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 12 May 2013 22:21:44 +0800
Subject: [PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards
In-Reply-To: <1368070143-1655-6-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
 <1368070143-1655-6-git-send-email-b32955@freescale.com>
Message-ID: <20130512142142.GA4648@S2101-09.ap.freescale.net>

On Thu, May 09, 2013 at 11:29:03AM +0800, Huang Shijie wrote:
> Since the SPI/NOR has pin conflict with the WEIM NOR,
> we disable the spi/nor by default.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
>  1 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index 7b561fb..b6b9e56 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -16,6 +16,38 @@
>  	};
>  };
>  
> +&ecspi1 {
> +	fsl,spi-num-chipselects = <1>;
> +	cs-gpios = <&gpio3 19 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1_1>;
> +	status = "disabled";

I added a comment to it as below, and applied patch #2~5.

	status = "disabled"; /* pin conflict with WEIM NOR */

Shawn



From broonie at kernel.org  Sun May 12 10:33:44 2013
From: broonie at kernel.org (Mark Brown)
Date: Sun, 12 May 2013 18:33:44 +0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
Message-ID: <20130512143344.GC3200@sirena.org.uk>

On Sat, May 11, 2013 at 09:54:22AM -0700, S?ren Brinkmann wrote:
> On Fri, May 10, 2013 at 10:24:22PM +0100, Mark Brown wrote:

> > For your use case should these things be exposed by the FPGA device
> > asking for that rather than by having the clocks available separately?
> > Or is this part of the DT blob that's loaded incrementally along with
> > the FPGA (which does make things more interesting of course...).

> Here may be some misunderstanding.
> The clocks are not in the FPGA. The clocks are always there and part of
> the processing system (PS), they are just routed to the FPGA where they
> can be used as clocks for the FPGA design.

No, there's no confusion here - the clocks that are being exposed to
userspace are the clocks which enter the FPGA.  The driver or whatever
that understands the FPGA can do what is needed to control them,
including routing them on to subdevices it instantiates or exposing them
to userspace.

> > > +		clk_disable_unprepare(pdata->clk);
> > 
> > > +	if (ret)
> > > +		return -EBUSY;
> > 
> > Why not pass back the actual error?

> Good question. Was there some spec saying, that these sysfs callbacks
> should return this error? Otherwise this will be fixed.

Not to my knowledge.
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From s.hauer at pengutronix.de  Sun May 12 10:43:39 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 12 May 2013 16:43:39 +0200
Subject: [PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards
In-Reply-To: <1368070143-1655-6-git-send-email-b32955@freescale.com>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
 <1368070143-1655-6-git-send-email-b32955@freescale.com>
Message-ID: <20130512144339.GD31135@pengutronix.de>

On Thu, May 09, 2013 at 11:29:03AM +0800, Huang Shijie wrote:
> Since the SPI/NOR has pin conflict with the WEIM NOR,
> we disable the spi/nor by default.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
>  1 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index 7b561fb..b6b9e56 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -16,6 +16,38 @@
>  	};
>  };
>  
> +&ecspi1 {
> +	fsl,spi-num-chipselects = <1>;
> +	cs-gpios = <&gpio3 19 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1_1>;
> +	status = "disabled";
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "st,m25p32";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +
> +		partition at 0 {
> +			label = "U-Boot";
> +			reg = <0x0 0x40000>;
> +		};
> +
> +		partition at 40000 {
> +			label = "U-Boot-ENV";
> +			reg = <0x40000 0x10000>;
> +			read-only;
> +		};
> +
> +		partition at 50000 {
> +			label = "Kernel";
> +			reg = <0x50000 0x3b0000>;
> +		};

I really object to enforcing partition layouts in the devicetree. That's
clearly usecase specific and should be filled by the bootloader. Having
no partitions normally is not harmful, but having the wrong layout just
because we start a mainline devicetree really can be harmful.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From viresh.kumar at linaro.org  Sun May 12 11:04:56 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sun, 12 May 2013 20:34:56 +0530
Subject: [PATCH] Cpufreq: Fix incorrect dependecies for ARM SA11xx drivers
In-Reply-To: <1367756288-13422-1-git-send-email-shc_work@mail.ru>
References: <1367756288-13422-1-git-send-email-shc_work@mail.ru>
Message-ID: <CAOh2x=mL-_fm8pxUCJCM1MWQxca2ygJWpDS_OTnOfcLS4ZHC1g@mail.gmail.com>

On Sun, May 5, 2013 at 5:48 PM, Alexander Shiyan <shc_work at mail.ru> wrote:
>
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  drivers/cpufreq/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
> index a1488f5..534fcb8 100644
> --- a/drivers/cpufreq/Kconfig
> +++ b/drivers/cpufreq/Kconfig
> @@ -47,7 +47,7 @@ config CPU_FREQ_STAT_DETAILS
>
>  choice
>         prompt "Default CPUFreq governor"
> -       default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || CPU_FREQ_SA1110
> +       default CPU_FREQ_DEFAULT_GOV_USERSPACE if ARM_SA1100_CPUFREQ || ARM_SA1110_CPUFREQ
>         default CPU_FREQ_DEFAULT_GOV_PERFORMANCE
>         help
>           This option sets which CPUFreq governor shall be loaded at

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From viresh.kumar at linaro.org  Sun May 12 11:10:21 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sun, 12 May 2013 20:40:21 +0530
Subject: [RFC 19/42] drivers/pinctrl/spear: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-20-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-20-git-send-email-wsa@the-dreams.de>
Message-ID: <CAOh2x=koaTpBCKqXUtzzx6HbENfTT=mhZvr03LT_QYbiGKgrmw@mail.gmail.com>

On Fri, May 10, 2013 at 1:47 PM, Wolfram Sang <wsa at the-dreams.de> wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
> ---
>  drivers/pinctrl/spear/pinctrl-plgpio.c |    7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
> index 3e5a887..6b090be 100644
> --- a/drivers/pinctrl/spear/pinctrl-plgpio.c
> +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
> @@ -528,18 +528,13 @@ static int plgpio_probe(struct platform_device *pdev)
>         struct resource *res;
>         int ret, irq, i;
>
> -       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -       if (!res) {
> -               dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
> -               return -EBUSY;
> -       }
> -
>         plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
>         if (!plgpio) {
>                 dev_err(&pdev->dev, "memory allocation fail\n");
>                 return -ENOMEM;
>         }
>
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>         plgpio->base = devm_ioremap_resource(&pdev->dev, res);
>         if (IS_ERR(plgpio->base))
>                 return PTR_ERR(plgpio->base);

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From viresh.kumar at linaro.org  Sun May 12 11:11:42 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sun, 12 May 2013 20:41:42 +0530
Subject: [RFC 22/42] drivers/rtc: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-23-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-23-git-send-email-wsa@the-dreams.de>
Message-ID: <CAOh2x==r81YBYKWtPSUs=E35P_yfbCYjUib6EbPttYHME22cww@mail.gmail.com>

On Fri, May 10, 2013 at 1:47 PM, Wolfram Sang <wsa at the-dreams.de> wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
> ---
>  drivers/rtc/rtc-spear.c  |    7 +------

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From viresh.kumar at linaro.org  Sun May 12 11:12:15 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sun, 12 May 2013 20:42:15 +0530
Subject: [RFC 20/42] drivers/pwm: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-21-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-21-git-send-email-wsa@the-dreams.de>
Message-ID: <CAOh2x=k6ugjuNo7XUHFhqwN=eQBe-F6nVyafsMkf30fRTxirdw@mail.gmail.com>

On Fri, May 10, 2013 at 1:47 PM, Wolfram Sang <wsa at the-dreams.de> wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
> ---
>  drivers/pwm/pwm-spear.c    |    7 +------

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From shawn.guo at linaro.org  Sun May 12 11:18:53 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 12 May 2013 23:18:53 +0800
Subject: [PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards
In-Reply-To: <20130512144339.GD31135@pengutronix.de>
References: <1368070143-1655-1-git-send-email-b32955@freescale.com>
 <1368070143-1655-6-git-send-email-b32955@freescale.com>
 <20130512144339.GD31135@pengutronix.de>
Message-ID: <20130512151850.GA24494@S2101-09.ap.freescale.net>

On Sun, May 12, 2013 at 04:43:39PM +0200, Sascha Hauer wrote:
> On Thu, May 09, 2013 at 11:29:03AM +0800, Huang Shijie wrote:
> > Since the SPI/NOR has pin conflict with the WEIM NOR,
> > we disable the spi/nor by default.
> > 
> > Signed-off-by: Huang Shijie <b32955 at freescale.com>
> > ---
> >  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
> >  1 files changed, 32 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> > index 7b561fb..b6b9e56 100644
> > --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> > +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> > @@ -16,6 +16,38 @@
> >  	};
> >  };
> >  
> > +&ecspi1 {
> > +	fsl,spi-num-chipselects = <1>;
> > +	cs-gpios = <&gpio3 19 0>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_ecspi1_1>;
> > +	status = "disabled";
> > +
> > +	flash: m25p80 at 0 {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "st,m25p32";
> > +		spi-max-frequency = <20000000>;
> > +		reg = <0>;
> > +
> > +		partition at 0 {
> > +			label = "U-Boot";
> > +			reg = <0x0 0x40000>;
> > +		};
> > +
> > +		partition at 40000 {
> > +			label = "U-Boot-ENV";
> > +			reg = <0x40000 0x10000>;
> > +			read-only;
> > +		};
> > +
> > +		partition at 50000 {
> > +			label = "Kernel";
> > +			reg = <0x50000 0x3b0000>;
> > +		};
> 
> I really object to enforcing partition layouts in the devicetree. That's
> clearly usecase specific and should be filled by the bootloader. Having
> no partitions normally is not harmful, but having the wrong layout just
> because we start a mainline devicetree really can be harmful.

Ah, yes.  I recall the discussion you had with people a couple of weeks
ago.  I agreed with your opinion.  Just fixed it up with partition
layouts removed.

Shawn



From cdall at cs.columbia.edu  Sun May 12 14:51:30 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sun, 12 May 2013 11:51:30 -0700
Subject: [PATCH v3 24/32] arm64: KVM: 32bit GP register access
In-Reply-To: <20130511094336.GA56525@MacBook-Pro.local>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-25-git-send-email-marc.zyngier@arm.com>
 <20130502160906.GI20730@arm.com> <51892B90.8060706@arm.com>
 <20130507163303.GH29757@arm.com> <20130511003630.GD30999@chazy>
 <20130511094336.GA56525@MacBook-Pro.local>
Message-ID: <20130512184536.GA58092@ubuntu>

On Sat, May 11, 2013 at 10:43:37AM +0100, Catalin Marinas wrote:
> On Sat, May 11, 2013 at 01:36:30AM +0100, Christoffer Dall wrote:
> > On Tue, May 07, 2013 at 05:33:03PM +0100, Catalin Marinas wrote:
> > > On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote:
> > > > On 02/05/13 17:09, Catalin Marinas wrote:
> > > > > BTW, on arch/arm it looks like this is used when you get a data abort
> > > > > with PC as the destination register and you inject a prefetch abort in
> > > > > this case. Why isn't this a normal data abort? Once you get the
> > > > > information, you load it into PC but first you need to sort out the data
> > > > > abort (unless I don't understand how the kvm_inject_pabt works).
> > > > 
> > > > Indeed, it should be a data abort, as we correctly fetched the
> > > > instruction. Now, I wonder why we even bother trying to catch this case.
> > > > Fetching PC from MMIO looks quite silly, but I don't think anything
> > > > really forbids it in the architecture.
> > > 
> > > It's not forbidden and you should just treat it as any other data abort,
> > > no need to check whether the register is PC. If you do the PC adjustment
> > > further down in that function it will be overridden by the instruction
> > > emulation anyway. There is no optimisation in checking for PC since such
> > > fault is very unlikely in sane code anyway.
> > > 
> > The reason is simply that it is most likely because of a bug that this
> > happens, and we would rather catch such an error in a meaningful way
> > than let this go crazy and have users track it down for a long time.
> 
> It is probably a bug but it is a valid code sequence (and Peter even
> gave an example).
> 
> > Especially, this was relevant when we did io instruction decoding and we
> > wanted to catch potential bugs in that when it was development code.
> > 
> > That all being said, we can remove the check.  I don't think, however,
> > that it being an unlikely thing is a good argument: if we remove the
> > check we need to make sure that the VM does whatever the architecture
> > dictates, which I assume is to not skip the MMIO instruction and support
> > setting the PC to the value returned from an I/O emulation device in
> > QEMU.
> > 
> > I think the scenario sounds crazy and is more than anything a sign of a
> > bug somewhere, and whether it should be a PABT or a DABT is a judgement
> > call, but I chose a PABT because the thing that's weird is jumping to an
> > I/O address, it's not that the memory address for the load is
> > problematic.
> 
> I think that's where things get confused. You are reading from an I/O
> location with the destination being the PC and it is trapped by KVM.
> This has nothing to do with PABT, it's purely a DABT on the I/O access.
> You should emulate it and store the result in the PC. If the value
> loaded in PC is wrong, you will get a subsequent PABT in the guest but
> you must not translate the DABT on I/O memory (which would be generated
> even if the destination is not PC) into a PABT which confuses the guest
> further. By doing this you try to convince the guest that it really
> branched to the I/O address (since you raise the PABT with the DFAR
> value) when it simply tried to load an address from I/O and branch to
> this new address.
> 
> IOW, these two are equivalent regarding PC:
> 
> 	ldr	pc, [r0]	@ r0 is an I/O address
> 
> and 
> 
> 	ldr	r1, [r0]	@ r0 is an I/O address
> 	mov	pc, r1
> 
> In the second scenario, you don't raise a PABT on the first instruction.
> You may raise one on the second if PC is invalid but that's different
> and most likely it will be a guest-only thing.
> 
> So for DABT emulation, checking whether the destination register is PC
> is simply a minimal optimisation (if at all) of that case to avoid
> storing the PC twice. Injecting PABT when you get a DABT is a bug. You
> already catch PABT on I/O address in kvm_handle_guest_abort() and
> correctly inject PABT into guest.
> 
Yeah, I got a little confused on the jump to an I/O address and load
the PC from an I/O address distinction, thanks for waking me up.

I will send out a patch that should address this issue by correctly
loading the value into the PC (and not inject a DABT).  Note that I
don't plan on doing any explicit checking for a case where the VM does
something like:

	ldrb	pc, [r0]	@ r0 is an I/O address

Because I assume that this is either an undefined instruction or the
behavior is unpredictable as per the architecture anyway, and we should
never get there unless we have a bug in our decoding implementation,
which I doubt at this point.

-Christoffer


From cdall at cs.columbia.edu  Sun May 12 14:58:55 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sun, 12 May 2013 11:58:55 -0700
Subject: [PATCH] ARM: KVM: Handle loads from I/O addresses to PC
Message-ID: <1368385135-60584-1-git-send-email-cdall@cs.columbia.edu>

If a VM does something like this:

ldr     pc, [r0]        @ r0 is an I/O address

Then simply let that value load into the PC on kvm_handle_mmio_return
overwriting the PC value set from kvm_skip_instr.

Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>
---
 arch/arm/kvm/mmio.c |    6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 72a12f2..b8e06b7 100644
--- a/arch/arm/kvm/mmio.c
+++ b/arch/arm/kvm/mmio.c
@@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
 	sign_extend = kvm_vcpu_dabt_issext(vcpu);
 	rt = kvm_vcpu_dabt_get_rd(vcpu);
 
-	if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
-		/* IO memory trying to read/write pc */
-		kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
-		return 1;
-	}
-
 	mmio->is_write = is_write;
 	mmio->phys_addr = fault_ipa;
 	mmio->len = len;
-- 
1.7.9.5



From soren.brinkmann at xilinx.com  Sun May 12 15:05:04 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Sun, 12 May 2013 12:05:04 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130512143344.GC3200@sirena.org.uk>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
Message-ID: <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>

On Sun, May 12, 2013 at 06:33:44PM +0400, Mark Brown wrote:
> On Sat, May 11, 2013 at 09:54:22AM -0700, S?ren Brinkmann wrote:
> > On Fri, May 10, 2013 at 10:24:22PM +0100, Mark Brown wrote:
> 
> > > For your use case should these things be exposed by the FPGA device
> > > asking for that rather than by having the clocks available separately?
> > > Or is this part of the DT blob that's loaded incrementally along with
> > > the FPGA (which does make things more interesting of course...).
> 
> > Here may be some misunderstanding.
> > The clocks are not in the FPGA. The clocks are always there and part of
> > the processing system (PS), they are just routed to the FPGA where they
> > can be used as clocks for the FPGA design.
> 
> No, there's no confusion here - the clocks that are being exposed to
> userspace are the clocks which enter the FPGA.  The driver or whatever
> that understands the FPGA can do what is needed to control them,
> including routing them on to subdevices it instantiates or exposing them
> to userspace.
Such a driver does not exist in general.
For some IP cores, Linux drivers do exist and then
they are supposed to directly use the CCF, IMHO, no need to expose
things to userspace in that case.
I'm trying to cover cases, in which there is no driver available/needed for
the FPGA design, other than some simple clock controls.

As simple example, if you wrote your own HW blinken lights design, you
wouldn't have nor need a Linux driver for it, but if you used these
clocks as inputs you could change the blinking speed by adjusting the
frequency.

	S?ren




From carlo.caione at gmail.com  Sun May 12 16:36:34 2013
From: carlo.caione at gmail.com (Carlo Caione)
Date: Sun, 12 May 2013 22:36:34 +0200
Subject: [PATCH] ARM: sunxi: New watchdog driver for Allwinner A10/A13
Message-ID: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>

This patch adds the driver for the watchdog found in the Allwinner A10 and
A13 SoCs. It has DT-support and uses the new watchdog framework.

Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
---
 drivers/watchdog/Kconfig     |  10 ++
 drivers/watchdog/Makefile    |   1 +
 drivers/watchdog/sunxi_wdt.c | 218 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 229 insertions(+)
 create mode 100644 drivers/watchdog/sunxi_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e89fc31..473e670 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -299,6 +299,16 @@ config ORION_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called orion_wdt.
 
+config SUNXI_WATCHDOG
+	tristate "Sunxi watchdog"
+	depends on ARCH_SUNXI
+	select WATCHDOG_CORE
+	help
+	  Say Y here to include support for the watchdog timer
+	  in Allwinner A10 and A13.
+	  To compile this driver as a module, choose M here: the
+	  module will be called sunxi_wdt.
+
 config COH901327_WATCHDOG
 	bool "ST-Ericsson COH 901 327 watchdog"
 	depends on ARCH_U300
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a300b94..5012d5f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
 obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
 obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
+obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
 obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
 obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
new file mode 100644
index 0000000..fe193b3
--- /dev/null
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -0,0 +1,218 @@
+/*
+ *      sunxi Watchdog Driver
+ *
+ *      Copyright (c) 2013 Carlo Caione
+ *                    2012 Henrik Nordstrom
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Based on xen_wdt.c
+ *      (c) Copyright 2010 Novell, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/watchdog.h>
+
+#define WDT_MAX_TIMEOUT         16
+#define WDT_MIN_TIMEOUT         1
+#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
+#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
+
+#define WDT_CTRL                0x00
+#define WDT_MODE                0x04
+
+#define WDT_MODE_RST_EN         (1 << 1)
+#define WDT_MODE_EN             (1 << 0)
+
+#define WDT_CTRL_RESTART        (1 << 0)
+#define WDT_CTRL_RESERVED       (0x0a57 << 1)
+#define DRV_NAME		"sunxi-wdt"
+#define DRV_VERSION		"1.0"
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+static int heartbeat = WDT_MAX_TIMEOUT;
+
+static const int wdt_timeout_map[] = {
+	[1] = 0b0001,
+	[2] = 0b0010,
+	[3] = 0b0011,
+	[4] = 0b0100,
+	[5] = 0b0101,
+	[6] = 0b0110,
+	[8] = 0b0111,
+	[10] = 0b1000,
+	[12] = 0b1001,
+	[14] = 0b1010,
+	[16] = 0b1011,
+};
+
+static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	reg = ioread32(wdt_base + WDT_CTRL);
+	reg |= (WDT_CTRL_RESTART | WDT_CTRL_RESERVED);
+	iowrite32(reg, wdt_base + WDT_CTRL);
+
+	return 0;
+}
+
+static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
+		unsigned int timeout)
+{
+	u32 reg;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout]))
+		return -EINVAL;
+
+	sunxi_wdt_dev->timeout = timeout;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg &= ~(WDT_TIMEOUT_MASK);
+	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	sunxi_wdt_ping(sunxi_wdt_dev);
+
+	return 0;
+}
+
+static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg &= ~(WDT_MODE_RST_EN | WDT_MODE_EN);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	return 0;
+}
+
+static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	int ret;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
+	if (ret < 0)
+		return ret;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	return 0;
+}
+
+static const struct watchdog_info sunxi_wdt_info = {
+	.identity	= DRV_NAME,
+	.options	= WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING |
+			  WDIOF_MAGICCLOSE,
+};
+
+static const struct watchdog_ops sunxi_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= sunxi_wdt_start,
+	.stop		= sunxi_wdt_stop,
+	.ping		= sunxi_wdt_ping,
+	.set_timeout	= sunxi_wdt_set_timeout,
+};
+
+static struct watchdog_device sunxi_wdt_dev = {
+	.info		= &sunxi_wdt_info,
+	.ops		= &sunxi_wdt_ops,
+	.timeout	= WDT_MAX_TIMEOUT,
+	.max_timeout	= WDT_MAX_TIMEOUT,
+	.min_timeout	= WDT_MIN_TIMEOUT,
+};
+
+static int __init sunxi_wdt_probe(struct platform_device *pdev)
+{
+	int err;
+	void __iomem *wdt_base;
+
+	wdt_base = of_iomap(pdev->dev.of_node, 0);
+	if (unlikely(!wdt_base)) {
+		err = -ENOMEM;
+		goto error_mem_out;
+	}
+
+	sunxi_wdt_dev.parent = &pdev->dev;
+	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
+	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
+
+	err = watchdog_register_device(&sunxi_wdt_dev);
+	if (unlikely(err))
+		goto error_wdt;
+
+	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
+
+	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
+			sunxi_wdt_dev.timeout, nowayout);
+	return 0;
+
+error_wdt:
+	iounmap(wdt_base);
+error_mem_out:
+	return err;
+}
+
+static int __exit sunxi_wdt_remove(struct platform_device *pdev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
+
+	sunxi_wdt_stop(&sunxi_wdt_dev);
+	watchdog_unregister_device(&sunxi_wdt_dev);
+	iounmap(wdt_base);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_wdt_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-wdt" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
+
+static struct platform_driver sunxi_wdt_driver = {
+	.probe		= sunxi_wdt_probe,
+	.remove		= sunxi_wdt_remove,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= DRV_NAME,
+		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
+	},
+};
+
+module_platform_driver(sunxi_wdt_driver);
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
+
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
+		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
+MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
+MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
+MODULE_VERSION(DRV_VERSION);
-- 
1.8.2.3



From termine at buergerhaus-der-walddoerfer.de  Sun May 12 18:59:30 2013
From: termine at buergerhaus-der-walddoerfer.de (=?koi8-r?Q?=EE=C1=C4=C5=D6=C4=C1_=E1=CE=D4=CF=CE=CF=D7=CE?= =?koi8-r?Q?=C1?=)
Date: Mon, 13 May 2013 01:59:30 +0300
Subject: =?koi8-r?Q?=EF=D3=D7=CF=C9=D4=D8_=D0=CF=D2=C1=DA=C9=D4=C5?=
 =?koi8-r?Q?=CC=D8=CE=CF_=D3=CB=CF=D2=CF?=
Message-ID: <8A8CCE1132A943ABAC5DA8033AA6313B@qpzyk>

  ????????: http://snurl.com/270obko . ???????????? ????????? ???????????? ???????? ????????? - ????????????? ?? ????. ?? ??????? ???????? ?? ???????????? ??????????????? ???????????? ????????? ?????. ?????????? ?????? ???????? ???????????, ????????? ??????????? ?????. ??????????? ????????. ???????????? ?????????? ???? ?????? ??????? ??????? . ???? ??? ?????????? ??? ?? ???????????. ???????????? ???????????? ??????. 
 

From linus.walleij at linaro.org  Sun May 12 19:36:23 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 May 2013 01:36:23 +0200
Subject: [PATCH] pinctrl: document the "GPIO mode" pitfall
In-Reply-To: <2359346.pRaN3J5Bl7@avalon>
References: <1363345636-2006-1-git-send-email-linus.walleij@stericsson.com>
 <1761651.lXztZzrj1S@avalon>
 <CACRpkdaMdU4DHWULnSB_dvGk8pTRbirL1HVTGqJ2rwqXR798uQ@mail.gmail.com>
 <2359346.pRaN3J5Bl7@avalon>
Message-ID: <CACRpkdauJ1DUn2FYWT7gqM3pW3QGzjimFnDgzqmDrZXMk9Yu0Q@mail.gmail.com>

On Sat, Apr 27, 2013 at 3:16 AM, Laurent Pinchart
<laurent.pinchart at ideasonboard.com> wrote:
> On Friday 26 April 2013 10:49:12 Linus Walleij wrote:

>> > Does DRIVE_* imply that the pin is driven by the selected function, and
>> > OUTPUT imply that the pin is driven to a fixed level ?
>>
>> That is unclear, but I suggest DRIVE* implies that everything on the pin
>> is driven according to that configuration. (Else it is getting ignored...)
>>
>> OUTPUT would be used when you don't know the particulars or when
>> the driving cannot be controlled in a fine-grained manner like with the
>> DRIVE* configs.
>>
>> Does this make sense?
>
> Kinda, but it's still unclear to me. While the options are (briefly)
> documented, how they interact isn't.

Do you think the sematics need to be etched in stone or do
you think it could be left as driver-specific, like if I write in the
defintion that the interaction of different config arguments is up
to the driver?

>> > What about cases where I want to drive the pin to a fixed level in a non
>> > low-power output mode (for instance because I need more current that what
>> > the low-power output mode provides) ?
>>
>> Just use pinconfig for that?
>
> How would you do so ? Only OUTPUT allows setting the output level explictly,
> the other DRIVE_* options don't specify the output level.

The PIN_CONFIG_DRIVE_STRENGTH argument is in mA.

Is this what you're after or something else?

Yours,
Linus Walleij


From kuninori.morimoto.gx at renesas.com  Sun May 12 20:18:41 2013
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Sun, 12 May 2013 17:18:41 -0700 (PDT)
Subject: [PATCH] ARM: shmobile: r8a7778: correct model name in Kconfig
In-Reply-To: <518D4CCF.5040706@cogentembedded.com>
References: <201305090405.41053.sergei.shtylyov@cogentembedded.com>
 <20130510082055.GB27435@verge.net.au>
 <518D4CCF.5040706@cogentembedded.com>
Message-ID: <87obcfn350.wl%kuninori.morimoto.gx@renesas.com>


Hi

> >> The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
> >> M1S which is a SH based SoC.
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> > Morimoto-san,
> >
> > please review this change.
> >
> 
>     This patch was based on the info found on this official Renesas webpage:
> 
> http://www.renesas.eu/applications/automotive/cis/cis_highend/rcar_m1as/index.jsp

Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Best regards
---
Kuninori Morimoto


From horms at verge.net.au  Sun May 12 20:40:01 2013
From: horms at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 09:40:01 +0900
Subject: [PATCH 2/2] ARM: shmobile: lager: enable Ether
In-Reply-To: <518CCD55.6070101@cogentembedded.com>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>
 <518CCD55.6070101@cogentembedded.com>
Message-ID: <20130513004001.GC22911@verge.net.au>

[ CC Laurent ]

On Fri, May 10, 2013 at 02:35:01PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 10-05-2013 12:05, Simon Horman wrote:
> 
> >Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> >---
> 
> >This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".
> >---
> >  arch/arm/boot/dts/r8a7790-lager.dts  |  2 +-
> >  arch/arm/mach-shmobile/board-lager.c | 26 ++++++++++++++++++++++++++
> >  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> >diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
> >index 09a84fc..b2f61f0 100644
> >--- a/arch/arm/boot/dts/r8a7790-lager.dts
> >+++ b/arch/arm/boot/dts/r8a7790-lager.dts
> >@@ -16,7 +16,7 @@
> >  	compatible = "renesas,lager", "renesas,r8a7790";
> >
> >  	chosen {
> >-		bootargs = "console=ttySC6,115200 ignore_loglevel";
> >+		bootargs = "console=ttySC6,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
> >  	};
> >
> >  	memory at 40000000 {
> 
>    Perhaps you shouldn't mix .dts changes with source changes?

Sure, I can break that out into a separate patch.

> 
> >diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
> >index 6a1ba38..0b8112d 100644
> >--- a/arch/arm/mach-shmobile/board-lager.c
> >+++ b/arch/arm/mach-shmobile/board-lager.c
> [...]
> >@@ -59,6 +69,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
> >  	/* SCIF1 (CN20: DEBUG SERIAL1) */
> >  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
> >  				  "scif1_data", "scif1"),
> >+	/* Ether */
> >+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >+				  "eth_link", "eth"),
> >+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >+				  "eth_magic", "eth"),
> >+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >+				  "eth_mdio", "eth"),
> >+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >+				  "eth_rmii", "eth"),
> 
>     I thought MDIO bus was a part of RMII. At least Wikipedia told
> me so. :-)

Is the implication that you think that the eth_mdio and eth_rmii
groups should be combined?


From horms at verge.net.au  Sun May 12 20:43:14 2013
From: horms at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 09:43:14 +0900
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: add Ether support
In-Reply-To: <518CCB6A.2060303@cogentembedded.com>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-2-git-send-email-horms+renesas@verge.net.au>
 <518CCB6A.2060303@cogentembedded.com>
Message-ID: <20130513004314.GD22911@verge.net.au>

On Fri, May 10, 2013 at 02:26:50PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 10-05-2013 12:05, Simon Horman wrote:
> 
> >Add Ether clock and platform device for R8A7779 SoC; add a function to
> >register this device with board-specific platform data.
> 
> >Based on a similar change for the r8a7779 by Sergei Shtylyov.
> 
> >Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> >---
> 
> >This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".
> >---
> >  arch/arm/mach-shmobile/clock-r8a7790.c        |  6 +++++-
> >  arch/arm/mach-shmobile/include/mach/r8a7790.h |  3 +++
> >  arch/arm/mach-shmobile/setup-r8a7790.c        | 15 +++++++++++++++
> >  3 files changed, 23 insertions(+), 1 deletion(-)
> 
> >diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> >index bedd20c..2c3123e 100644
> >--- a/arch/arm/mach-shmobile/clock-r8a7790.c
> >+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> [...]
> >@@ -178,9 +179,11 @@ static struct clk div6_clks[DIV6_NR] = {
> >  };
> >
> >  /* MSTP */
> >-enum { MSTP721, MSTP720,
> >+enum { MSTP813, MSTP812,
> 
>    I think these two should be on a line of their own...
> 
> >MSTP721, MSTP720,
> >  	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
> >  static struct clk mstp_clks[MSTP_NR] = {
> >+	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
> >+	[MSTP812] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 12, 0), /* EtherAVB */
> >  	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
> >  	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
> >  	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
> [...]
> >diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> >index 2e919e6..95b8f7e 100644
> >--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
> >+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> >@@ -1,9 +1,12 @@
> >  #ifndef __ASM_R8A7790_H__
> >  #define __ASM_R8A7790_H__
> >
> >+#include <linux/sh_eth.h>
> >+
> >  void r8a7790_add_standard_devices(void);
> >  void r8a7790_clock_init(void);
> >  void r8a7790_pinmux_init(void);
> >  void r8a7790_timer_init(void);
> >+void r8a7790_add_ether_device(struct sh_eth_plat_data *pdata);
> 
>    Perhaps better place is right after r8a7790_add_standard_devices()...

Is the implication that the struct sh_eth_plat_data can be defined
in setup-r8a7790.c? Or do you for see adding a struct sh_eth_plat_data
parameter to r8a7790_add_standard_devices() ?

> >  #endif /* __ASM_R8A7790_H__ */
> >diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> >index eeef5f6..8ed0d7b 100644
> >--- a/arch/arm/mach-shmobile/setup-r8a7790.c
> >+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> >@@ -30,6 +30,21 @@
> >  #include <mach/r8a7790.h>
> >  #include <asm/mach/arch.h>
> >
> >+
> >+/* Ether */
> >+static struct resource ether_resources[] = {
> 
>    You missed the '__initdata' annotation.

Thanks, I will fix that.

> 
> >+	DEFINE_RES_MEM(0xee700000, 0x400),
> >+	DEFINE_RES_IRQ(gic_spi(162)), /* IRQ0 */
> >+};


From shawn.guo at linaro.org  Sun May 12 21:16:02 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:16:02 +0800
Subject: [PATCH] pinctrl: enable build of pinctrl-imx6sl driver
Message-ID: <1368407762-12084-1-git-send-email-shawn.guo@linaro.org>

The pinctrl-imx6sl is in place.  Enable the build of it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/pinctrl/Makefile |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 9bdaeb8..34c4ae6 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_IMX51)	+= pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)	+= pinctrl-imx53.o
 obj-$(CONFIG_PINCTRL_IMX6Q)	+= pinctrl-imx6q.o
 obj-$(CONFIG_PINCTRL_IMX6Q)	+= pinctrl-imx6dl.o
+obj-$(CONFIG_PINCTRL_IMX6SL)	+= pinctrl-imx6sl.o
 obj-$(CONFIG_PINCTRL_FALCON)	+= pinctrl-falcon.o
 obj-$(CONFIG_PINCTRL_MXS)	+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o
-- 
1.7.9.5




From shawn.guo at linaro.org  Sun May 12 21:17:56 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:17:56 +0800
Subject: [PATCH 1/2] ARM: dts: imx6qdl: remove redundant usbmisc label
Message-ID: <1368407877-12171-1-git-send-email-shawn.guo@linaro.org>

There is a redundant label on usbmisc node.  Remove it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fd7cc6d..92169e6 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -640,7 +640,7 @@
 				status = "disabled";
 			};
 
-			usbmisc: usbmisc: usbmisc at 02184800 {
+			usbmisc: usbmisc at 02184800 {
 				#index-cells = <1>;
 				compatible = "fsl,imx6q-usbmisc";
 				reg = <0x02184800 0x200>;
-- 
1.7.9.5




From shawn.guo at linaro.org  Sun May 12 21:17:57 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:17:57 +0800
Subject: [PATCH 2/2] ARM: dts: imx6qdl: remove redundant ocotp node
In-Reply-To: <1368407877-12171-1-git-send-email-shawn.guo@linaro.org>
References: <1368407877-12171-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368407877-12171-2-git-send-email-shawn.guo@linaro.org>

There is a redundant ocotp node.  Remove it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 92169e6..42e461c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -754,11 +754,6 @@
 				reg = <0x021bc000 0x4000>;
 			};
 
-			ocotp at 021c0000 {
-				reg = <0x021c0000 0x4000>;
-				interrupts = <0 21 0x04>;
-			};
-
 			tzasc at 021d0000 { /* TZASC1 */
 				reg = <0x021d0000 0x4000>;
 				interrupts = <0 108 0x04>;
-- 
1.7.9.5




From shawn.guo at linaro.org  Sun May 12 21:32:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:32:05 +0800
Subject: [PATCH 0/3] ARM: imx: make mxs_restart() work for DT boot
Message-ID: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>

The mxs_restart() currently only works for non-DT platforms.  And per
Russell's comment, it's not going to work reliably, because the restart
routine could be called in atomic context while mxs_restart() is calling
clk_prepare() there.

The series fixes above potential problem by moving clk_prepare() into
initialization function mxc_arch_reset_init() and only keeping atomic
part clk_enable() in mxs_restart().

Then a DT variant initialization function imx_arch_reset_init() is
added, so that DT platforms can use mxs_restart() as well after invoking
the initialization function.

Shawn Guo (3):
  ARM: imx: include <asm/io.h> in hardware.h
  ARM: imx: move clk_prepare() out from mxs_restart()
  ARM: imx: create imx_arch_reset_init() for DT boot

 arch/arm/mach-imx/common.h     |    1 +
 arch/arm/mach-imx/hardware.h   |    1 +
 arch/arm/mach-imx/imx25-dt.c   |    2 ++
 arch/arm/mach-imx/imx27-dt.c   |    2 ++
 arch/arm/mach-imx/imx31-dt.c   |    2 ++
 arch/arm/mach-imx/imx51-dt.c   |    2 ++
 arch/arm/mach-imx/mach-imx53.c |    3 +++
 arch/arm/mach-imx/mm-imx1.c    |    2 +-
 arch/arm/mach-imx/mm-imx21.c   |    2 +-
 arch/arm/mach-imx/mm-imx25.c   |    2 +-
 arch/arm/mach-imx/mm-imx27.c   |    2 +-
 arch/arm/mach-imx/mm-imx3.c    |    4 ++--
 arch/arm/mach-imx/mm-imx5.c    |    3 +--
 arch/arm/mach-imx/system.c     |   47 +++++++++++++++++++++++++++++++---------
 14 files changed, 57 insertions(+), 18 deletions(-)

-- 
1.7.9.5




From shawn.guo at linaro.org  Sun May 12 21:32:06 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:32:06 +0800
Subject: [PATCH 1/3] ARM: imx: include <asm/io.h> in hardware.h
In-Reply-To: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368408728-12264-2-git-send-email-shawn.guo@linaro.org>

As IOMEM is referenced in hardware.h, <asm/io.h> should be included
there.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/hardware.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 356131f..a3b0b04 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -20,6 +20,7 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
 
+#include <asm/io.h>
 #include <asm/sizes.h>
 
 #define addr_in_module(addr, mod) \
-- 
1.7.9.5




From shawn.guo at linaro.org  Sun May 12 21:32:08 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:32:08 +0800
Subject: [PATCH 3/3] ARM: imx: create imx_arch_reset_init() for DT boot
In-Reply-To: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>

The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to
get clock.  It's suitable for non-DT boot but not for DT boot where
dynamic mapping and of_clk_get() should be used instead.  Create
imx_arch_reset_init() as the DT variant of mxc_arch_reset_init(),
and change DT platforms to use it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/common.h     |    1 +
 arch/arm/mach-imx/imx25-dt.c   |    3 +--
 arch/arm/mach-imx/imx27-dt.c   |    3 +--
 arch/arm/mach-imx/imx31-dt.c   |    3 +--
 arch/arm/mach-imx/imx51-dt.c   |    3 +--
 arch/arm/mach-imx/mach-imx53.c |    2 +-
 arch/arm/mach-imx/system.c     |   20 ++++++++++++++++++++
 7 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f..3ef909b 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -74,6 +74,7 @@ extern struct platform_device *mxc_register_gpio(char *name, int id,
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_restart(char, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
+extern void imx_arch_reset_init(void);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index ec33991..a2575267 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -15,12 +15,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "common.h"
-#include "hardware.h"
 #include "mx25.h"
 
 static void __init imx25_dt_init(void)
 {
-	mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+	imx_arch_reset_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 93aef1a..174e441 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -16,14 +16,13 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "hardware.h"
 #include "mx27.h"
 
 static void __init imx27_dt_init(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
-	mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+	imx_arch_reset_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index d8b3b22..a07cdec 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -16,12 +16,11 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "hardware.h"
 #include "mx31.h"
 
 static void __init imx31_dt_init(void)
 {
-	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+	imx_arch_reset_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 55f47a0..b2f5830 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -17,14 +17,13 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "hardware.h"
 #include "mx51.h"
 
 static void __init imx51_dt_init(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
-	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+	imx_arch_reset_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 7a56561..e0da2cc 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -39,7 +39,7 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
-	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+	imx_arch_reset_init();
 
 	if (of_machine_is_compatible("fsl,imx53-qsb"))
 		imx53_qsb_init();
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 02cf449..973f01d 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
@@ -75,3 +77,21 @@ void __init mxc_arch_reset_init(void __iomem *base)
 
 	clk_prepare(wdog_clk);
 }
+
+void __init imx_arch_reset_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
+	wdog_base = of_iomap(np, 0);
+	WARN_ON(!wdog_base);
+
+	wdog_clk = of_clk_get(np, 0);
+	if (IS_ERR(wdog_clk)) {
+		pr_warn("%s: failed to get wdog clock\n", __func__);
+		wdog_clk = NULL;
+		return;
+	}
+
+	clk_prepare(wdog_clk);
+}
-- 
1.7.9.5




From shawn.guo at linaro.org  Sun May 12 21:32:07 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 09:32:07 +0800
Subject: [PATCH 2/3] ARM: imx: move clk_prepare() out from mxs_restart()
In-Reply-To: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368408728-12264-3-git-send-email-shawn.guo@linaro.org>

It's inappropriate to call clk_prepare() in mxs_restart(), because the
restart routine could be called in atomic context.  Move clk_get() and
clk_prepare() into mxc_arch_reset_init() and only have the atomic part
clk_enable() be called in mxs_restart().

As a result, mxc_arch_reset_init() needs to be called after clk gets
initialized.

While there, it also changes printk(KERN_ERR ...) to pr_err() and adds
__init annotation for mxc_arch_reset_init().

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/imx25-dt.c   |    3 +++
 arch/arm/mach-imx/imx27-dt.c   |    3 +++
 arch/arm/mach-imx/imx31-dt.c   |    3 +++
 arch/arm/mach-imx/imx51-dt.c   |    3 +++
 arch/arm/mach-imx/mach-imx53.c |    3 +++
 arch/arm/mach-imx/mm-imx1.c    |    2 +-
 arch/arm/mach-imx/mm-imx21.c   |    2 +-
 arch/arm/mach-imx/mm-imx25.c   |    2 +-
 arch/arm/mach-imx/mm-imx27.c   |    2 +-
 arch/arm/mach-imx/mm-imx3.c    |    4 ++--
 arch/arm/mach-imx/mm-imx5.c    |    3 +--
 arch/arm/mach-imx/system.c     |   27 +++++++++++++++++----------
 12 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 8234839..ec33991 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -15,10 +15,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "common.h"
+#include "hardware.h"
 #include "mx25.h"
 
 static void __init imx25_dt_init(void)
 {
+	mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4aaead0..93aef1a 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -16,12 +16,15 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "hardware.h"
 #include "mx27.h"
 
 static void __init imx27_dt_init(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
+	mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
 	platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 67de611..d8b3b22 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -16,10 +16,13 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "hardware.h"
 #include "mx31.h"
 
 static void __init imx31_dt_init(void)
 {
+	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index ab24cc3..55f47a0 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -17,12 +17,15 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "hardware.h"
 #include "mx51.h"
 
 static void __init imx51_dt_init(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
+	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	platform_device_register_full(&devinfo);
 }
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index f579c61..7a56561 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -21,6 +21,7 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "hardware.h"
 #include "mx53.h"
 
 static void __init imx53_qsb_init(void)
@@ -38,6 +39,8 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
+	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+
 	if (of_machine_is_compatible("fsl,imx53-qsb"))
 		imx53_qsb_init();
 
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 3c609c5..e065fed 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -39,7 +39,6 @@ void __init mx1_map_io(void)
 void __init imx1_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX1);
-	mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
 	imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
 			MX1_NUM_GPIO_PORT);
 }
@@ -51,6 +50,7 @@ void __init mx1_init_irq(void)
 
 void __init imx1_soc_init(void)
 {
+	mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
 	mxc_device_init();
 
 	mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a..2e91ab2 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -66,7 +66,6 @@ void __init mx21_map_io(void)
 void __init imx21_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX21);
-	mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
 	imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
 			MX21_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = {
 
 void __init imx21_soc_init(void)
 {
+	mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
 	mxc_device_init();
 
 	mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707..e065c11 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -54,7 +54,6 @@ void __init imx25_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX25);
 	mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
-	mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 }
 
 void __init mx25_init_irq(void)
@@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = {
 
 void __init imx25_soc_init(void)
 {
+	mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 	mxc_device_init();
 
 	/* i.mx25 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65..7d82a5a 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -66,7 +66,6 @@ void __init mx27_map_io(void)
 void __init imx27_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX27);
-	mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
 	imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
 			MX27_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = {
 
 void __init imx27_soc_init(void)
 {
+	mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
 	mxc_device_init();
 
 	/* i.mx27 has the i.mx21 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a6..8f0f606 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -138,7 +138,6 @@ void __init mx31_map_io(void)
 void __init imx31_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX31);
-	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 	arch_ioremap_caller = imx3_ioremap_caller;
 	arm_pm_idle = imx3_idle;
 	mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
@@ -174,6 +173,7 @@ void __init imx31_soc_init(void)
 
 	imx3_init_l2x0();
 
+	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 	mxc_device_init();
 
 	mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
@@ -216,7 +216,6 @@ void __init imx35_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX35);
 	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 	arm_pm_idle = imx3_idle;
 	arch_ioremap_caller = imx3_ioremap_caller;
 	mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
@@ -272,6 +271,7 @@ void __init imx35_soc_init(void)
 
 	imx3_init_l2x0();
 
+	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 	mxc_device_init();
 
 	mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index b7c4e70..cf193d8 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -83,7 +83,6 @@ void __init imx51_init_early(void)
 	imx51_ipu_mipi_setup();
 	mxc_set_cpu_type(MXC_CPU_MX51);
 	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 	imx_src_init();
 }
 
@@ -91,7 +90,6 @@ void __init imx53_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX53);
 	mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 	imx_src_init();
 }
 
@@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = {
 
 void __init imx51_soc_init(void)
 {
+	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 	mxc_device_init();
 
 	/* i.mx51 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..02cf449 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -30,6 +30,7 @@
 #include "hardware.h"
 
 static void __iomem *wdog_base;
+static struct clk *wdog_clk;
 
 /*
  * Reset the system. It is called by machine_restart().
@@ -38,16 +39,13 @@ void mxc_restart(char mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
-	if (cpu_is_mx1()) {
-		wcr_enable = (1 << 0);
-	} else {
-		struct clk *clk;
+	if (wdog_clk)
+		clk_enable(wdog_clk);
 
-		clk = clk_get_sys("imx2-wdt.0", NULL);
-		if (!IS_ERR(clk))
-			clk_prepare_enable(clk);
+	if (cpu_is_mx1())
+		wcr_enable = (1 << 0);
+	else
 		wcr_enable = (1 << 2);
-	}
 
 	/* Assert SRS signal */
 	__raw_writew(wcr_enable, wdog_base);
@@ -55,7 +53,7 @@ void mxc_restart(char mode, const char *cmd)
 	/* wait for reset to assert... */
 	mdelay(500);
 
-	printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+	pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
 
 	/* delay to allow the serial port to show the message */
 	mdelay(50);
@@ -64,7 +62,16 @@ void mxc_restart(char mode, const char *cmd)
 	soft_restart(0);
 }
 
-void mxc_arch_reset_init(void __iomem *base)
+void __init mxc_arch_reset_init(void __iomem *base)
 {
 	wdog_base = base;
+
+	wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
+	if (IS_ERR(wdog_clk)) {
+		pr_warn("%s: failed to get wdog clock\n", __func__);
+		wdog_clk = NULL;
+		return;
+	}
+
+	clk_prepare(wdog_clk);
 }
-- 
1.7.9.5




From horms at verge.net.au  Sun May 12 21:33:22 2013
From: horms at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 10:33:22 +0900
Subject: [PATCH] ARM: shmobile: r8a7778: correct model name in Kconfig
In-Reply-To: <87obcfn350.wl%kuninori.morimoto.gx@renesas.com>
References: <201305090405.41053.sergei.shtylyov@cogentembedded.com>
 <20130510082055.GB27435@verge.net.au>
 <518D4CCF.5040706@cogentembedded.com>
 <87obcfn350.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <20130513013320.GD7826@verge.net.au>

On Sun, May 12, 2013 at 05:18:41PM -0700, Kuninori Morimoto wrote:
> 
> Hi
> 
> > >> The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
> > >> M1S which is a SH based SoC.
> > >>
> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> > > Morimoto-san,
> > >
> > > please review this change.
> > >
> > 
> >     This patch was based on the info found on this official Renesas webpage:
> > 
> > http://www.renesas.eu/applications/automotive/cis/cis_highend/rcar_m1as/index.jsp
> 
> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> 

Thanks, I have queued-up the following in the soc-r8a7778 branch.
There was a trivial conflict which I resolved. Please let me know
if I messed it up.

From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

ARM: shmobile: r8a7778: correct model name in Kconfig

The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
M1S which is a SH based SoC.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
[horms+renesas at verge.net.au: manually applied to soc-r8a7778 branch]
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3e7ad45..3c463ff 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,7 @@ config ARCH_R8A7740
 	select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-	bool "R-Car M1 (R8A77780)"
+	bool "R-Car M1A (R8A77781)"
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select CPU_V7
 	select SH_CLK_CPG
-- 
1.8.2.1



From ming.lei at canonical.com  Sun May 12 21:56:31 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Mon, 13 May 2013 09:56:31 +0800
Subject: [PATCH] ARM: DMA-mapping: mark all !DMA_TO_DEVICE pages in
 unmapping as clean
In-Reply-To: <1367572365-18905-1-git-send-email-ming.lei@canonical.com>
References: <1367572365-18905-1-git-send-email-ming.lei@canonical.com>
Message-ID: <CACVXFVMSibWd2+QG88QypJC0KYYE0oyyyt4iHpdnK5YR4AN-6g@mail.gmail.com>

Hello,

On Fri, May 3, 2013 at 5:12 PM, Ming Lei <ming.lei at canonical.com> wrote:
> It is common for one sg to include many pages, so mark all these
> pages as clean to avoid unnecessary flushing on them in
> set_pte_at() or update_mmu_cache().
>
> The patch might improve loading performance of applciation code a bit.
>
> On the below test code to read file(~1GByte size) from usb mass storage
> disk to buffer created with mmap(PROT_READ | PROT_EXEC) on
> Pandaboard, average ~1% improvement can be observed with the patch on
> 10 times test.
>
>
> #define _GNU_SOURCE
>
> #include <fcntl.h>
> #include <stdio.h>
> #include <unistd.h>
> #include <stdlib.h>
> #include <sys/mman.h>
> #include <sys/stat.h>
> #include <string.h>
> #include <assert.h>
>
> unsigned int sum = 0;
>
> static unsigned long tv_diff(struct timeval *tv1, struct timeval *tv2)
> {
>         return (tv2->tv_sec - tv1->tv_sec) * 1000000 +
>                 (tv2->tv_usec - tv1->tv_usec);
> }
>
> int main(int argc, char *argv[])
> {
>         char *mbuffer;
>         int fd;
>         int i;
>         unsigned long page_size, size;
>         struct stat stat;
>         struct timeval t1, t2;
>
>         page_size = getpagesize();
>         fd = open(argv[1], O_RDONLY);
>         assert(fd >= 0);
>
>         fstat(fd, &stat);
>         size = stat.st_size;
>         printf("%s: file %s, file size %lu, page size %lu\n", argv[0],
>                 read_filename, size, page_size);
>
>         gettimeofday(&t1, NULL);
>         mbuffer = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0);
>         for (i = 0 ; i < size ; i += page_size)
>                 sum += mbuffer[i];
>         munmap(mbuffer, page_size);
>         gettimeofday(&t2, NULL);
>         printf("\tread mmaped time: %luus\n", tv_diff(&t1, &t2));
>
>         close(fd);
> }
>
> Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Marek Szyprowski <m.szyprowski at samsung.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Signed-off-by: Ming Lei <ming.lei at canonical.com>

Gentle ping, :-)

Thanks,
--
Ming Lei


From shawn.guo at linaro.org  Sun May 12 22:29:21 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 10:29:21 +0800
Subject: [PATCH 1/2] ARM: mxs: Add default AUART2 pinmux
In-Reply-To: <1368188795-9114-1-git-send-email-marex@denx.de>
References: <1368188795-9114-1-git-send-email-marex@denx.de>
Message-ID: <20130513022919.GC24494@S2101-09.ap.freescale.net>

On Fri, May 10, 2013 at 02:26:34PM +0200, Marek Vasut wrote:
> Add pinmux for AUART2 pins where they are in mux0.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx28.dtsi |   11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 7ba4966..13799cf 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -308,6 +308,17 @@
>  					fsl,pull-up = <0>;
>  				};
>  
> +				auart2_2pins_b: auart2-2pins at 1 {
> +					reg = <1>;
> +					fsl,pinmux-ids = <
> +						0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
> +						0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
> +					>;
> +					fsl,drive-strength = <0>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +

I already applied a same patch from Eric B?nard.

Shawn

http://thread.gmane.org/gmane.linux.kernel/1471518/

>  				auart3_pins_a: auart3 at 0 {
>  					reg = <0>;
>  					fsl,pinmux-ids = <
> -- 
> 1.7.10.4
> 



From shawn.guo at linaro.org  Sun May 12 22:30:03 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 10:30:03 +0800
Subject: [PATCH 2/2] ARM: mxs: Fix UARTs on M28EVK
In-Reply-To: <1368188795-9114-2-git-send-email-marex@denx.de>
References: <1368188795-9114-1-git-send-email-marex@denx.de>
 <1368188795-9114-2-git-send-email-marex@denx.de>
Message-ID: <20130513023002.GD24494@S2101-09.ap.freescale.net>

On Fri, May 10, 2013 at 02:26:35PM +0200, Marek Vasut wrote:
> Make use of RTS/CTS lines on AUART0 and register AUART1 and AUART2
> which are routed onto a pin header.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.



From rusty at rustcorp.com.au  Sun May 12 21:16:07 2013
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Mon, 13 May 2013 10:46:07 +0930
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <1367902933.18069.212@driftwood>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
 <1367902933.18069.212@driftwood>
Message-ID: <87obcf3ciw.fsf@rustcorp.com.au>

Rob Landley <rob at landley.net> writes:
> On 05/06/2013 07:19:50 AM, Pranavkumar Sawargaonkar wrote:
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>> ---
>>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>> 
>> diff --git a/Documentation/virtual/virtio-spec.txt  
>> b/Documentation/virtual/virtio-spec.txt
>> index 0d6ec85..3ca38f8 100644
>> --- a/Documentation/virtual/virtio-spec.txt
>> +++ b/Documentation/virtual/virtio-spec.txt
>> @@ -1927,11 +1927,16 @@ Ports 2 onwards only if  
>> VIRTIO_CONSOLE_F_MULTIPORT is set
>>      ports; configuration fields nr_ports and max_nr_ports are
>>      valid and control virtqueues will be used.
>> 
>> +  VIRTIO_CONSOLE_F_EMERG_WRITE(2) Device has support for emergency
>> +  write. Configuration filed emerg_wr is valid.
>
> Emergency?
>
> Really?
>
> Out of morbid curiosity, what would constitute an _emergency_ in a  
> virtual machine logging context?

Usually, your console device is broken.  Or you can't set it up because
you can't allocate memory.  Or you oops before it is configured.

Terminology is a tricky thing, but the nuance here is that you don't
want to use this as your main console.  It may not do anything.  It may
drop characters.  It's definitely slow.

Cheers,
Rusty.


From rusty at rustcorp.com.au  Sun May 12 22:52:07 2013
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Mon, 13 May 2013 12:22:07 +0930
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
Message-ID: <8761yn382w.fsf@rustcorp.com.au>

Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> ---
>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)

OK, I applied this to the lyx master, with three changes:
1) Changed "filed" to "field".
2) Added ", or even acknowledging the feature" after "without
   initializing virtio queues".
3) Added an initial point to the Device Initialization section:

   1. If the VIRTIO_CONSOLE_F_EMERG_WRITE feature is offered, the
   emerg_wr field of the configuration can be written at any time. Thus
   it should work for very early boot debugging output as well as
   catastophic OS failures (eg. virtio ring corruption).

Thanks,
Rusty.

> diff --git a/Documentation/virtual/virtio-spec.txt b/Documentation/virtual/virtio-spec.txt
> index 0d6ec85..3ca38f8 100644
> --- a/Documentation/virtual/virtio-spec.txt
> +++ b/Documentation/virtual/virtio-spec.txt
> @@ -1927,11 +1927,16 @@ Ports 2 onwards only if VIRTIO_CONSOLE_F_MULTIPORT is set
>      ports; configuration fields nr_ports and max_nr_ports are
>      valid and control virtqueues will be used.
>  
> +  VIRTIO_CONSOLE_F_EMERG_WRITE(2) Device has support for emergency
> +  write. Configuration filed emerg_wr is valid.
> +
>    Device configuration layout The size of the console is supplied
>    in the configuration space if the VIRTIO_CONSOLE_F_SIZE feature
>    is set. Furthermore, if the VIRTIO_CONSOLE_F_MULTIPORT feature
>    is set, the maximum number of ports supported by the device can
> -  be fetched.struct virtio_console_config {
> +  be fetched. If VIRTIO_CONSOLE_F_EMERG_WRITE is set then one can
> +  use emergency write to output single character without initializing
> +  virtio queues. struct virtio_console_config {
>  
>  	u16 cols;
>  
> @@ -1941,6 +1946,7 @@ Ports 2 onwards only if VIRTIO_CONSOLE_F_MULTIPORT is set
>  
>  	u32 max_nr_ports;
>  
> +	u32 emerg_wr;
>  };
>  
>    Device Initialization
> -- 
> 1.7.9.5


From tom.leiming at gmail.com  Sun May 12 23:12:03 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Mon, 13 May 2013 11:12:03 +0800
Subject: [PATCH V3 2/2] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130511062719.GA10643@schnuecks.de>
References: <20130418135104.GA18616@arm.com>
 <20130421220629.GA25571@schnuecks.de>
 <20130430112225.GD29766@arm.com>
 <20130430210403.GA18076@schnuecks.de>
 <20130501142206.GB17387@arm.com>
 <20130501190441.GA22227@schnuecks.de>
 <20130502095431.GA20730@arm.com>
 <20130502193835.GA29144@schnuecks.de>
 <20130503100242.GB29962@arm.com>
 <CACVXFVPOuabwAa1VDmSnfDG=M-1Df02_kpbm0UVAVctCAB-U4Q@mail.gmail.com>
 <20130511062719.GA10643@schnuecks.de>
Message-ID: <CACVXFVM8OMmse1QwmY5S_cowhG0+gaDMOYwjrrbA1zr0JjV++g@mail.gmail.com>

On Sat, May 11, 2013 at 2:27 PM, Simon Baatz <gmbnomis at gmail.com> wrote:
> On Sat, May 04, 2013 at 04:21:27PM +0800, Ming Lei wrote:
>> On Fri, May 3, 2013 at 6:02 PM, Catalin Marinas <catalin.marinas at arm.com> wrote:
>> >>
>> >> I assume that you inhibited the call to flush_dcache_page() in
>> >> __get_user_pages() for anon pages.  Otherwise, you will be flooded
>> >> with warnings.
>> >
>> > I haven't done any stress testing so I don't think I hit this code path,
>> > so no warning. But yes, it should have triggered. Anyway, in this case
>> > flush_dcache_page() should have just ignored (clearing PG_arch_1 is
>> > harmless anyway if we also ignore this bit in __sync_icache_dcache for
>> > non-aliasing caches).
>>
>> Yes, maybe we can do a little optimization for O_DIRECT since no
>> dcache alias and I/D coherency problem in this case on ARMv7, how
>> about below change?
>>
>> diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
>> index 1c8f7f5..962a657 100644
>> --- a/arch/arm/mm/flush.c
>> +++ b/arch/arm/mm/flush.c
>> @@ -287,6 +287,8 @@ void flush_dcache_page(struct page *page)
>>           mapping && !mapping_mapped(mapping))
>>               clear_bit(PG_dcache_clean, &page->flags);
>>       else {
>> +             if (!mapping && cache_is_vipt_nonaliasing())
>> +                     return;
>>               __flush_dcache_page(mapping, page);
>>               if (mapping && cache_is_vivt())
>>                       __flush_dcache_aliases(mapping, page);
>>
>
> Yes, this should not be needed. However, I seem to get funny pixel
> errors on an Exynos 5 based Chromebook when not flushing in this
> case.  Strange.  This is not on a mainline kernel, I will need to
> have a look what happens here.

Yes, it is a bit strange, not sure how flush_dcache_page() is used
in memory mapped by mmap.(suppose the display buffer is mmaped)

I test O_DIRECT writing to USB mass storage with the patch, looks
the data written is correct.

[tom]$dd if=/mnt/nfs/test/usb/qieteing-512M.rmvb
of=/mnt/usb/tests/qieteing-512M.rmvb oflag=direct,sync bs=512M count=1
1+0 records in
1+0 records out
536870912 bytes (537 MB) copied, 111.631 s, 4.8 MB/s

#echo 3 > /proc/sys/vm/drop_caches

[tom]$cd /mnt/usb/tests/
[tom]$md5sum -c /mnt/nfs/test/usb/qieteing-512M.rmvb.md5
qieteing-512M.rmvb: OK


Thanks,
-- 
Ming Lei


From marex at denx.de  Sun May 12 23:34:30 2013
From: marex at denx.de (Marek Vasut)
Date: Mon, 13 May 2013 05:34:30 +0200
Subject: [PATCH 1/2] ARM: mxs: Add default AUART2 pinmux
In-Reply-To: <20130513022919.GC24494@S2101-09.ap.freescale.net>
References: <1368188795-9114-1-git-send-email-marex@denx.de>
 <20130513022919.GC24494@S2101-09.ap.freescale.net>
Message-ID: <201305130534.30850.marex@denx.de>

Dear Shawn Guo,

> On Fri, May 10, 2013 at 02:26:34PM +0200, Marek Vasut wrote:
> > Add pinmux for AUART2 pins where they are in mux0.
> > 
> > Signed-off-by: Marek Vasut <marex at denx.de>
> > Cc: Shawn Guo <shawn.guo at linaro.org>
> > Cc: Fabio Estevam <fabio.estevam at freescale.com>
> > ---
> > 
> >  arch/arm/boot/dts/imx28.dtsi |   11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> > index 7ba4966..13799cf 100644
> > --- a/arch/arm/boot/dts/imx28.dtsi
> > +++ b/arch/arm/boot/dts/imx28.dtsi
> > @@ -308,6 +308,17 @@
> > 
> >  					fsl,pull-up = <0>;
> >  				
> >  				};
> > 
> > +				auart2_2pins_b: auart2-2pins at 1 {
> > +					reg = <1>;
> > +					fsl,pinmux-ids = <
> > +						0x3080 /* 
MX28_PAD_AUART2_RX__AUART2_RX */
> > +						0x3090 /* 
MX28_PAD_AUART2_TX__AUART2_TX */
> > +					>;
> > +					fsl,drive-strength = <0>;
> > +					fsl,voltage = <1>;
> > +					fsl,pull-up = <0>;
> > +				};
> > +
> 
> I already applied a same patch from Eric B?nard.
> 
> Shawn
> 
> http://thread.gmane.org/gmane.linux.kernel/1471518/

Ok, looks like Eric was much faster :-) Sorry, I was doing this patchset on 
3.9.1 and didn't notice his patch.

Best regards,
Marek Vasut


From weiyj.lk at gmail.com  Mon May 13 00:25:23 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Mon, 13 May 2013 12:25:23 +0800
Subject: [PATCH] ARM: OMAP: fix error return code in omap1_system_dma_init()
Message-ID: <CAPgLHd8iPa4efHsYsCmGE-j-GzZw7DtWdSaQqpEuF60-BRtmbg@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Fix to return -ENOMEM in the d->chan alloc error handling
case instead of 0, as done elsewhere in this function.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 arch/arm/mach-omap1/dma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 68ab858..a94b3a7 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -345,6 +345,7 @@ static int __init omap1_system_dma_init(void)
 		dev_err(&pdev->dev,
 			"%s: Memory allocation failed for d->chan!\n",
 			__func__);
+		ret = -ENOMEM;
 		goto exit_release_d;
 	}
 



From cdall at cs.columbia.edu  Mon May 13 01:13:52 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sun, 12 May 2013 22:13:52 -0700
Subject: [PATCH] ARM: KVM: prevent NULL pointer dereference with KVM ioctl
In-Reply-To: <518A2098.9010909@arm.com>
References: <1367931313-14839-1-git-send-email-andre.przywara@linaro.org>
 <518A2098.9010909@arm.com>
Message-ID: <20130513051352.GA64337@ubuntu>

On Wed, May 08, 2013 at 10:53:28AM +0100, Marc Zyngier wrote:
> On 07/05/13 13:55, Andre Przywara wrote:
> > Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
> > with the KVM_ARM_VCPU_INIT ioctl before being used with further
> > requests. KVM_RUN checks whether this initialization has been
> > done, but other ioctls do not.
> > Namely KVM_GET_REG_LIST will dereference an array with index -1
> > without initialization and thus leads to a kernel oops.
> > Fix this by adding checks before executing the ioctl handlers.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
> > ---
> >  arch/arm/kvm/arm.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> > index c1fe498..0c571ff 100644
> > --- a/arch/arm/kvm/arm.c
> > +++ b/arch/arm/kvm/arm.c
> > @@ -893,6 +893,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
> >  	case KVM_SET_ONE_REG:
> >  	case KVM_GET_ONE_REG: {
> >  		struct kvm_one_reg reg;
> > +
> > +		/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
> > +		if (unlikely(vcpu->arch.target < 0))
> > +			return -ENOEXEC;
> > +
> >  		if (copy_from_user(&reg, argp, sizeof(reg)))
> >  			return -EFAULT;
> >  		if (ioctl == KVM_SET_ONE_REG)
> > @@ -905,6 +910,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
> >  		struct kvm_reg_list reg_list;
> >  		unsigned n;
> >  
> > +		/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
> > +		if (unlikely(vcpu->arch.target < 0))
> > +			return -ENOEXEC;
> > +
> >  		if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
> >  			return -EFAULT;
> >  		n = reg_list.n;
> > 
> 
> So we also have the same snippet in kvm_arch_vcpu_ioctl_run().
> 
> Can you create a static function (kvm_vcpu_initialized?) containing that
> code and make all three sites use it?
> 
Andre, will you re-spin your patch as per Marc's comments?

Thanks,
-Christoffer


From cdall at cs.columbia.edu  Mon May 13 01:17:37 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sun, 12 May 2013 22:17:37 -0700
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <20130502151753.GB25022@mudshark.cambridge.arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
 <20130502150355.GA25022@mudshark.cambridge.arm.com>
 <CAEDV+gJwYpHzehWZci2bmgYedJoBxMOGZFhjGeGRQ_cT8TKkyw@mail.gmail.com>
 <20130502151753.GB25022@mudshark.cambridge.arm.com>
Message-ID: <20130513051737.GB64337@ubuntu>

On Thu, May 02, 2013 at 04:17:53PM +0100, Will Deacon wrote:
> On Thu, May 02, 2013 at 04:15:05PM +0100, Christoffer Dall wrote:
> > On Thu, May 2, 2013 at 8:03 AM, Will Deacon <will.deacon at arm.com> wrote:
> > > On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> > >> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> > >> introduced code that flushes page tables to the point of coherency.
> > >> This is overkill (point of unification is enough and already done),
> > >> and actually not required if running on a SMP capable platform
> > >> (the HW PTW can snoop other cpus' L1).
> > >>
> > >> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> > >> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> > >> a no-op for SMP ARMv7.
> > >>
> > >> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> > >> Cc: Will Deacon <will.deacon at arm.com>
> > >> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> > >> ---
> > >>  arch/arm/kvm/mmu.c | 3 ---
> > >>  1 file changed, 3 deletions(-)
> > >>
> > >> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> > >> index 4a838db..d79b594 100644
> > >> --- a/arch/arm/kvm/mmu.c
> > >> +++ b/arch/arm/kvm/mmu.c
> > >> @@ -234,7 +234,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
> > >>               pte = pte_offset_kernel(pmd, addr);
> > >>               kvm_set_pte(pte, pfn_pte(pfn, prot));
> > >>               get_page(virt_to_page(pte));
> > >> -             kvm_flush_dcache_to_poc(pte, sizeof(*pte));
> > >>               pfn++;
> > >>       } while (addr += PAGE_SIZE, addr != end);
> > >
> > > Could you remove the flushing code out of kvm_set_pte, then flush the range
> > > after the loop? Then you get one flush and one barrier for the whole range.
> > >
> > that would be different from how it's done in the rest of the kernel
> > where you're expecting set_pte to do the necessary flushing for you,
> > no?
> 
> Correct, but since kvm_set_pte seems only to be called from this file, I'm
> not sure you need to match thes rest of the kernel.
> 
> > instead, if this optimization is worth it, the code could just use
> > pte_val(pte) = XX;
> 
> or just *pte = XX;
> 
That won't work with STRICT_M_TYPECHECKS though will it?

-Christoffer


From broonie at kernel.org  Mon May 13 01:21:35 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 13 May 2013 09:21:35 +0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
Message-ID: <20130513052135.GD6836@sirena.org.uk>

On Sun, May 12, 2013 at 12:05:04PM -0700, S?ren Brinkmann wrote:
> On Sun, May 12, 2013 at 06:33:44PM +0400, Mark Brown wrote:

> > No, there's no confusion here - the clocks that are being exposed to
> > userspace are the clocks which enter the FPGA.  The driver or whatever
> > that understands the FPGA can do what is needed to control them,
> > including routing them on to subdevices it instantiates or exposing them
> > to userspace.

> Such a driver does not exist in general.
> For some IP cores, Linux drivers do exist and then
> they are supposed to directly use the CCF, IMHO, no need to expose
> things to userspace in that case.
> I'm trying to cover cases, in which there is no driver available/needed for
> the FPGA design, other than some simple clock controls.

You're not understanding the point here.  If you've got a
reprogrammmable FPGA you at least need some way to get the FPGA image in
there.  This driver is presumably responsible for instantiating whatever
is needed to control what is on the FPGA, that could include punting the
clocks to userspace if that's sane.
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From linux at prisktech.co.nz  Mon May 13 01:47:07 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 17:47:07 +1200
Subject: [PATCHv6 0/3] Add support for velocity network driver on platform
 devices
Message-ID: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>

v6 changes:
Remove more bus specific code from velocity_probe()
Make velocity_(suspend/resume) accept a struct device *
Simplify PM code to use velocity_(suspend/resume) - remove the individual
pci and platform functions.
Add a struct pci_dev variable to velocity_get_pci_info() to reduce churn

v5 changes:
Remove velocity_info union. Change velocity_info->pdev back to struct pci_dev.
Remove more 'if (pci)' sections.
Remove 'void *pdev' function parameters.
Pass correct variable to velocity_choose_state()

v4 changes:
Code tidyup as requested by Francois Romieu
Removed '#ifdef PCI' around PCI code. Compile tested on (!)PCI and (!)PM.

v3 changes:
Rebased against net-next.
Fix errors in pm code.

v2 changes:
Drop patch #1 as requested by David Miller.
Correct the PHYID_ICPLUS_IP101A MII bits - should be ON, rather than OFF.
Read the platform rev_id from the correct register [regs->rev_id]. It's possible
this would work for the PCI version as well and would remove the need for the
'if (pci)' test to set vptr->rev_id.

v1:
The first three patches are general tidyup.

[DROPPED] Patch ## just alphabetizes the #includes to make it easier to read.

Patch #1 replaces vptr->dev with vptr->netdev, in preparation of adding a
struct device *dev in Patch #3

Patch #2 replaces the pci dma functions with the generic versions.

I have build tested these patches but don't have a PCI velocity to run-test it.
I can't see that they should introduce any problems as it is all renames and
function swapping.

Patch #3 adds support for the velocity driver on devicetree platform devices.
Binding document included. This patch is compile-tested for PCI, and boot
tested on a VIA APC8750.

I think it would be pertinent to get some tested-by's for PCI users.

Regards
Tony Prisk

Tony Prisk (3):
  net: velocity: Rename vptr->dev to vptr->netdev
  net: velocity: Convert to generic dma functions
  net: velocity: Add platform device support to VIA velocity driver

 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  497 +++++++++++++-------
 drivers/net/ethernet/via/via-velocity.h            |   35 +-
 4 files changed, 377 insertions(+), 178 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

-- 
1.7.9.5



From linux at prisktech.co.nz  Mon May 13 01:47:09 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 17:47:09 +1200
Subject: [PATCHv6 2/3] net: velocity: Convert to generic dma functions
In-Reply-To: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>
References: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368424030-15348-3-git-send-email-linux@prisktech.co.nz>

Remove the pci_* dma functions and replace with the more generic
versions.

In preparation of adding platform support, a new struct device *dev
is added to struct velocity_info which can be used by both the pci
and platform code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   51 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    1 +
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 187eef3..5996cee 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -46,6 +46,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 #include <linux/init.h>
+#include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
@@ -1459,7 +1460,6 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	struct velocity_opt *opt = &vptr->options;
 	const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
 	const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
-	struct pci_dev *pdev = vptr->pdev;
 	dma_addr_t pool_dma;
 	void *pool;
 	unsigned int i;
@@ -1467,13 +1467,13 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	/*
 	 * Allocate all RD/TD rings a single pool.
 	 *
-	 * pci_alloc_consistent() fulfills the requirement for 64 bytes
+	 * dma_alloc_coherent() fulfills the requirement for 64 bytes
 	 * alignment
 	 */
-	pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
-				    rx_ring_size, &pool_dma);
+	pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
+				    rx_ring_size, &pool_dma, GFP_ATOMIC);
 	if (!pool) {
-		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
+		dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
 			vptr->netdev->name);
 		return -ENOMEM;
 	}
@@ -1524,8 +1524,8 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	 */
 	skb_reserve(rd_info->skb,
 			64 - ((unsigned long) rd_info->skb->data & 63));
-	rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
-					vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
+					vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Fill in the descriptor to match
@@ -1588,8 +1588,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr)
 
 		if (!rd_info->skb)
 			continue;
-		pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-				 PCI_DMA_FROMDEVICE);
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
 		rd_info->skb_dma = 0;
 
 		dev_kfree_skb(rd_info->skb);
@@ -1670,7 +1670,7 @@ static void velocity_free_dma_rings(struct velocity_info *vptr)
 	const int size = vptr->options.numrx * sizeof(struct rx_desc) +
 		vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
 
-	pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
+	dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
 }
 
 static int velocity_init_rings(struct velocity_info *vptr, int mtu)
@@ -1727,8 +1727,8 @@ static void velocity_free_tx_buf(struct velocity_info *vptr,
 				pktlen = max_t(size_t, pktlen,
 						td->td_buf[i].size & ~TD_QUEUE);
 
-			pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
-					le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
+			dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
+					le16_to_cpu(pktlen), DMA_TO_DEVICE);
 		}
 	}
 	dev_kfree_skb_irq(skb);
@@ -1750,8 +1750,8 @@ static void velocity_free_td_ring_entry(struct velocity_info *vptr,
 	if (td_info->skb) {
 		for (i = 0; i < td_info->nskb_dma; i++) {
 			if (td_info->skb_dma[i]) {
-				pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
-					td_info->skb->len, PCI_DMA_TODEVICE);
+				dma_unmap_single(vptr->dev, td_info->skb_dma[i],
+					td_info->skb->len, DMA_TO_DEVICE);
 				td_info->skb_dma[i] = 0;
 			}
 		}
@@ -2029,7 +2029,6 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
  */
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
-	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
 	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
@@ -2047,8 +2046,8 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 
 	skb = rd_info->skb;
 
-	pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
-				    vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
+				    vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Drop frame not meeting IEEE 802.3
@@ -2061,19 +2060,18 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		}
 	}
 
-	pci_action = pci_dma_sync_single_for_device;
-
 	velocity_rx_csum(rd, skb);
 
 	if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
 		velocity_iph_realign(vptr, skb, pkt_len);
-		pci_action = pci_unmap_single;
 		rd_info->skb = NULL;
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
+	} else {
+		dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
+					   vptr->rx.buf_sz, DMA_FROM_DEVICE);
 	}
 
-	pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-		   PCI_DMA_FROMDEVICE);
-
 	skb_put(skb, pkt_len - 4);
 	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
@@ -2550,7 +2548,8 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	 *	add it to the transmit ring.
 	 */
 	tdinfo->skb = skb;
-	tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+	tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
+								DMA_TO_DEVICE);
 	td_ptr->tdesc0.len = cpu_to_le16(pktlen);
 	td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
 	td_ptr->td_buf[0].pa_high = 0;
@@ -2560,7 +2559,7 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
-		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(&vptr->pdev->dev,
+		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
 							  frag, 0,
 							  skb_frag_size(frag),
 							  DMA_TO_DEVICE);
@@ -2637,6 +2636,7 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
 {
 	memset(vptr, 0, sizeof(struct velocity_info));
 
+	vptr->dev = &pdev->dev;
 	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
@@ -2744,7 +2744,6 @@ static int velocity_found1(struct pci_dev *pdev,
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	vptr = netdev_priv(dev);
 
-
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
 			VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index ff8d7828..c38bbae 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1434,6 +1434,7 @@ struct velocity_opt {
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
 struct velocity_info {
+	struct device *dev;
 	struct pci_dev *pdev;
 	struct net_device *netdev;
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Mon May 13 01:47:08 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 17:47:08 +1200
Subject: [PATCHv6 1/3] net: velocity: Rename vptr->dev to vptr->netdev
In-Reply-To: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>
References: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368424030-15348-2-git-send-email-linux@prisktech.co.nz>

Improve the clarity of the code in preparation for converting the
dma functions to generic versions, which require a struct device *.

This makes it possible to store a 'struct device *dev' in the
velocity_info structure.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   66 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    4 +-
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index fb62489..187eef3 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -998,9 +998,9 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 {
 
 	if (vptr->mii_status & VELOCITY_LINK_FAIL) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
 	} else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
 
 		if (vptr->mii_status & VELOCITY_SPEED_1000)
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
@@ -1014,7 +1014,7 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 		else
 			VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
 	} else {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
 		switch (vptr->options.spd_dpx) {
 		case SPD_DPX_1000_FULL:
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
@@ -1319,7 +1319,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 	case VELOCITY_INIT_RESET:
 	case VELOCITY_INIT_WOL:
 
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/*
 		 *	Reset RX to prevent RX pointer not on the 4X location
@@ -1332,7 +1332,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1354,7 +1354,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 
 		mac_eeprom_reload(regs);
 		for (i = 0; i < 6; i++)
-			writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -1377,7 +1377,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		/*
 		 *	Set packet filter: Receive directed and broadcast address
 		 */
-		velocity_set_multi(vptr->dev);
+		velocity_set_multi(vptr->netdev);
 
 		/*
 		 *	Enable MII auto-polling
@@ -1404,14 +1404,14 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
 
 		mii_status = velocity_get_opt_media_mode(vptr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		mii_init(vptr, mii_status);
 
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1474,7 +1474,7 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 				    rx_ring_size, &pool_dma);
 	if (!pool) {
 		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
-			vptr->dev->name);
+			vptr->netdev->name);
 		return -ENOMEM;
 	}
 
@@ -1514,7 +1514,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 
-	rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx.buf_sz + 64);
+	rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
 	if (rd_info->skb == NULL)
 		return -ENOMEM;
 
@@ -1620,7 +1620,7 @@ static int velocity_init_rd_ring(struct velocity_info *vptr)
 
 	if (velocity_rx_refill(vptr) != vptr->options.numrx) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
-			"%s: failed to allocate RX buffer.\n", vptr->dev->name);
+			"%s: failed to allocate RX buffer.\n", vptr->netdev->name);
 		velocity_free_rd_ring(vptr);
 		goto out;
 	}
@@ -1809,7 +1809,7 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
 		BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
 		writew(TRDCSR_RUN, &regs->TDCSRClr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/* FIXME: port over the pci_device_failed code and use it
 		   here */
@@ -1850,10 +1850,10 @@ static void velocity_error(struct velocity_info *vptr, int status)
 
 		if (linked) {
 			vptr->mii_status &= ~VELOCITY_LINK_FAIL;
-			netif_carrier_on(vptr->dev);
+			netif_carrier_on(vptr->netdev);
 		} else {
 			vptr->mii_status |= VELOCITY_LINK_FAIL;
-			netif_carrier_off(vptr->dev);
+			netif_carrier_off(vptr->netdev);
 		}
 
 		velocity_print_link_status(vptr);
@@ -1867,9 +1867,9 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		enable_mii_autopoll(regs);
 
 		if (vptr->mii_status & VELOCITY_LINK_FAIL)
-			netif_stop_queue(vptr->dev);
+			netif_stop_queue(vptr->netdev);
 		else
-			netif_wake_queue(vptr->dev);
+			netif_wake_queue(vptr->netdev);
 
 	}
 	if (status & ISR_MIBFI)
@@ -1894,7 +1894,7 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	int idx;
 	int works = 0;
 	struct velocity_td_info *tdinfo;
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 
 	for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
 		for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
@@ -1939,9 +1939,9 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	 *	Look to see if we should kick the transmit network
 	 *	layer for more work.
 	 */
-	if (netif_queue_stopped(vptr->dev) && (full == 0) &&
+	if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
 	    (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
-		netif_wake_queue(vptr->dev);
+		netif_wake_queue(vptr->netdev);
 	}
 	return works;
 }
@@ -1989,7 +1989,7 @@ static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
 	if (pkt_size < rx_copybreak) {
 		struct sk_buff *new_skb;
 
-		new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
+		new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
 		if (new_skb) {
 			new_skb->ip_summed = rx_skb[0]->ip_summed;
 			skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
@@ -2030,14 +2030,14 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
 	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
 	struct sk_buff *skb;
 
 	if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
-		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->netdev->name);
 		stats->rx_length_errors++;
 		return -EINVAL;
 	}
@@ -2075,7 +2075,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		   PCI_DMA_FROMDEVICE);
 
 	skb_put(skb, pkt_len - 4);
-	skb->protocol = eth_type_trans(skb, vptr->dev);
+	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
 	if (rd->rdesc0.RSR & RSR_DETAG) {
 		u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
@@ -2100,7 +2100,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
  */
 static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
 {
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	int rd_curr = vptr->rx.curr;
 	int works = 0;
 
@@ -2292,7 +2292,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 	if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
-				vptr->dev->name);
+				vptr->netdev->name);
 		ret = -EINVAL;
 		goto out_0;
 	}
@@ -2314,7 +2314,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 			goto out_0;
 		}
 
-		tmp_vptr->dev = dev;
+		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
@@ -2692,7 +2692,7 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
  */
 static void velocity_print_info(struct velocity_info *vptr)
 {
-	struct net_device *dev = vptr->dev;
+	struct net_device *dev = vptr->netdev;
 
 	printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
 	printk(KERN_INFO "%s: Ethernet Address: %pM\n",
@@ -2755,7 +2755,7 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	velocity_init_info(pdev, vptr, info);
 
-	vptr->dev = dev;
+	vptr->netdev = dev;
 
 	ret = pci_enable_device(pdev);
 	if (ret < 0)
@@ -3010,10 +3010,10 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	struct velocity_info *vptr = netdev_priv(dev);
 	unsigned long flags;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
-	netif_device_detach(vptr->dev);
+	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
 	pci_save_state(pdev);
@@ -3078,7 +3078,7 @@ static int velocity_resume(struct pci_dev *pdev)
 	unsigned long flags;
 	int i;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
 	pci_set_power_state(pdev, PCI_D0);
@@ -3101,7 +3101,7 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	mac_enable_int(vptr->mac_regs);
 	spin_unlock_irqrestore(&vptr->lock, flags);
-	netif_device_attach(vptr->dev);
+	netif_device_attach(vptr->netdev);
 
 	return 0;
 }
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index 4cb9f13..ff8d7828 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1435,7 +1435,7 @@ struct velocity_opt {
 
 struct velocity_info {
 	struct pci_dev *pdev;
-	struct net_device *dev;
+	struct net_device *netdev;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
@@ -1514,7 +1514,7 @@ static inline int velocity_get_ip(struct velocity_info *vptr)
 	int res = -ENOENT;
 
 	rcu_read_lock();
-	in_dev = __in_dev_get_rcu(vptr->dev);
+	in_dev = __in_dev_get_rcu(vptr->netdev);
 	if (in_dev != NULL) {
 		ifa = (struct in_ifaddr *) in_dev->ifa_list;
 		if (ifa != NULL) {
-- 
1.7.9.5



From linux at prisktech.co.nz  Mon May 13 01:47:10 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 17:47:10 +1200
Subject: [PATCHv6 3/3] net: velocity: Add platform device support to VIA
 velocity driver
In-Reply-To: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>
References: <1368424030-15348-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368424030-15348-4-git-send-email-linux@prisktech.co.nz>

Add support for the VIA Velocity network driver to be bound to a
OF created platform device.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  388 ++++++++++++++------
 drivers/net/ethernet/via/via-velocity.h            |   32 +-
 4 files changed, 321 insertions(+), 122 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

diff --git a/Documentation/devicetree/bindings/net/via-velocity.txt b/Documentation/devicetree/bindings/net/via-velocity.txt
new file mode 100644
index 0000000..b3db469
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/via-velocity.txt
@@ -0,0 +1,20 @@
+* VIA Velocity 10/100/1000 Network Controller
+
+Required properties:
+- compatible : Should be "via,velocity-vt6110"
+- reg : Address and length of the io space
+- interrupts : Should contain the controller interrupt line
+
+Optional properties:
+- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
+	devices quite often set this data in uboot and do not provide an eeprom.
+	Specify this option if you have no external eeprom.
+
+Examples:
+
+eth0 at d8004000 {
+	compatible = "via,velocity-vt6110";
+	reg = <0xd8004000 0x400>;
+	interrupts = <10>;
+	no-eeprom;
+};
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
index 68a9ba6..6a87097 100644
--- a/drivers/net/ethernet/via/Kconfig
+++ b/drivers/net/ethernet/via/Kconfig
@@ -5,7 +5,6 @@
 config NET_VENDOR_VIA
 	bool "VIA devices"
 	default y
-	depends on PCI
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y
 	  and read the Ethernet-HOWTO, available from
@@ -45,7 +44,7 @@ config VIA_RHINE_MMIO
 
 config VIA_VELOCITY
 	tristate "VIA Velocity support"
-	depends on PCI
+	depends on (PCI || USE_OF)
 	select CRC32
 	select CRC_CCITT
 	select NET_CORE
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 5996cee..b30ab62 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -65,7 +65,11 @@
 #include <linux/if.h>
 #include <linux/uaccess.h>
 #include <linux/proc_fs.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
 #include <linux/inetdevice.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/ethtool.h>
 #include <linux/mii.h>
@@ -84,6 +88,16 @@
 static int velocity_nics;
 static int msglevel = MSG_LEVEL_INFO;
 
+static void velocity_set_power_state(struct velocity_info *vptr, char state)
+{
+	void *addr = vptr->mac_regs;
+
+	if (vptr->bustype == BUS_PCI)
+		pci_set_power_state(vptr->pdev, state);
+	else
+		writeb(state, addr + 0x154);
+}
+
 /**
  *	mac_get_cam_mask	-	Read a CAM mask
  *	@regs: register block for this velocity
@@ -362,12 +376,23 @@ static struct velocity_info_tbl chip_info_table[] = {
  *	Describe the PCI device identifiers that we support in this
  *	device driver. Used for hotplug autoloading.
  */
-static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
+
+static DEFINE_PCI_DEVICE_TABLE(velocity_pci_id_table) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
 	{ }
 };
 
-MODULE_DEVICE_TABLE(pci, velocity_id_table);
+MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
+
+/**
+ *	Describe the OF device identifiers that we support in this
+ *	device driver. Used for devicetree nodes.
+ */
+static struct of_device_id velocity_of_ids[] = {
+	{ .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, velocity_of_ids);
 
 /**
  *	get_chip_name	- 	identifier to name
@@ -386,29 +411,6 @@ static const char *get_chip_name(enum chip_type chip_id)
 }
 
 /**
- *	velocity_remove1	-	device unplug
- *	@pdev: PCI device being removed
- *
- *	Device unload callback. Called on an unplug or on module
- *	unload for each active device that is present. Disconnects
- *	the device from the network layer and frees all the resources
- */
-static void velocity_remove1(struct pci_dev *pdev)
-{
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
-
-	unregister_netdev(dev);
-	iounmap(vptr->mac_regs);
-	pci_release_regions(pdev);
-	pci_disable_device(pdev);
-	pci_set_drvdata(pdev, NULL);
-	free_netdev(dev);
-
-	velocity_nics--;
-}
-
-/**
  *	velocity_set_int_opt	-	parser for integer options
  *	@opt: pointer to option value
  *	@val: value the user requested (or -1 for default)
@@ -1181,6 +1183,17 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
 	u16 BMCR;
 
 	switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
+	case PHYID_ICPLUS_IP101A:
+		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
+						MII_ADVERTISE, vptr->mac_regs);
+		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		else
+			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
+		break;
 	case PHYID_CICADA_CS8201:
 		/*
 		 *	Reset to hardware default
@@ -1353,9 +1366,12 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		velocity_soft_reset(vptr);
 		mdelay(5);
 
-		mac_eeprom_reload(regs);
-		for (i = 0; i < 6; i++)
-			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
+		if (!vptr->no_eeprom) {
+			mac_eeprom_reload(regs);
+			for (i = 0; i < 6; i++)
+				writeb(vptr->netdev->dev_addr[i],
+							&(regs->PAR[i]));
+		}
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -2233,15 +2249,15 @@ static int velocity_open(struct net_device *dev)
 		goto out;
 
 	/* Ensure chip is running */
-	pci_set_power_state(vptr->pdev, PCI_D0);
+	velocity_set_power_state(vptr, PCI_D0);
 
 	velocity_init_registers(vptr, VELOCITY_INIT_COLD);
 
-	ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
+	ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
 			  dev->name, dev);
 	if (ret < 0) {
 		/* Power down the chip */
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 		velocity_free_rings(vptr);
 		goto out;
 	}
@@ -2314,6 +2330,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
+		tmp_vptr->dev = vptr->dev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
 
@@ -2413,7 +2430,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	   saving then we need to bring the device back up to talk to it */
 
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 
 	switch (cmd) {
 	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
@@ -2426,7 +2443,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 		ret = -EOPNOTSUPP;
 	}
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 
 
 	return ret;
@@ -2492,7 +2509,7 @@ static int velocity_close(struct net_device *dev)
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
 		velocity_get_ip(vptr);
 
-	free_irq(vptr->pdev->irq, dev);
+	free_irq(dev->irq, dev);
 
 	velocity_free_rings(vptr);
 
@@ -2631,13 +2648,9 @@ static const struct net_device_ops velocity_netdev_ops = {
  *	Set up the initial velocity_info struct for the device that has been
  *	discovered.
  */
-static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
-			       const struct velocity_info_tbl *info)
+static void velocity_init_info(struct velocity_info *vptr,
+				const struct velocity_info_tbl *info)
 {
-	memset(vptr, 0, sizeof(struct velocity_info));
-
-	vptr->dev = &pdev->dev;
-	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
 	vptr->multicast_limit = MCAM_SIZE;
@@ -2652,10 +2665,9 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
  *	Retrieve the PCI configuration space data that interests us from
  *	the kernel PCI layer
  */
-static int velocity_get_pci_info(struct velocity_info *vptr,
-				 struct pci_dev *pdev)
+static int velocity_get_pci_info(struct velocity_info *vptr)
 {
-	vptr->rev_id = pdev->revision;
+	struct pci_dev *pdev = vptr->pdev;
 
 	pci_set_master(pdev);
 
@@ -2678,7 +2690,37 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
 		dev_err(&pdev->dev, "region #1 is too small.\n");
 		return -EINVAL;
 	}
-	vptr->pdev = pdev;
+
+	return 0;
+}
+
+/**
+ *	velocity_get_platform_info - retrieve platform info for device
+ *	@vptr: velocity device
+ *	@pdev: platform device it matches
+ *
+ *	Retrieve the Platform configuration data that interests us
+ */
+static int velocity_get_platform_info(struct velocity_info *vptr)
+{
+	struct resource res;
+	int ret;
+
+	if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
+		vptr->no_eeprom = 1;
+
+	ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
+	if (ret) {
+		dev_err(vptr->dev, "unable to find memory address\n");
+		return ret;
+	}
+
+	vptr->memaddr = res.start;
+
+	if (resource_size(&res) < VELOCITY_IO_SIZE) {
+		dev_err(vptr->dev, "memory region is too small.\n");
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -2707,21 +2749,22 @@ static u32 velocity_get_link(struct net_device *dev)
 }
 
 /**
- *	velocity_found1		-	set up discovered velocity card
+ *	velocity_probe - set up discovered velocity device
  *	@pdev: PCI device
  *	@ent: PCI device table entry that matched
+ *	@bustype: bus that device is connected to
  *
  *	Configure a discovered adapter from scratch. Return a negative
  *	errno error code on failure paths.
  */
-static int velocity_found1(struct pci_dev *pdev,
-			   const struct pci_device_id *ent)
+static int velocity_probe(struct device *dev, int irq,
+			   const struct velocity_info_tbl *info,
+			   enum velocity_bus_type bustype)
 {
 	static int first = 1;
-	struct net_device *dev;
+	struct net_device *netdev;
 	int i;
 	const char *drv_string;
-	const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
 	struct velocity_info *vptr;
 	struct mac_regs __iomem *regs;
 	int ret = -ENOMEM;
@@ -2730,19 +2773,19 @@ static int velocity_found1(struct pci_dev *pdev,
 	 * can support more than MAX_UNITS.
 	 */
 	if (velocity_nics >= MAX_UNITS) {
-		dev_notice(&pdev->dev, "already found %d NICs.\n",
-			   velocity_nics);
+		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
 		return -ENODEV;
 	}
 
-	dev = alloc_etherdev(sizeof(struct velocity_info));
-	if (!dev)
+	netdev = alloc_etherdev(sizeof(struct velocity_info));
+	if (!netdev)
 		goto out;
 
 	/* Chain it all together */
 
-	SET_NETDEV_DEV(dev, &pdev->dev);
-	vptr = netdev_priv(dev);
+	SET_NETDEV_DEV(netdev, dev);
+	vptr = netdev_priv(netdev);
+	memset(vptr, 0, sizeof(struct velocity_info));
 
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
@@ -2752,41 +2795,41 @@ static int velocity_found1(struct pci_dev *pdev,
 		first = 0;
 	}
 
-	velocity_init_info(pdev, vptr, info);
-
-	vptr->netdev = dev;
+	netdev->irq = irq;
+	vptr->bustype = bustype;
+	vptr->netdev = netdev;
+	vptr->dev = dev;
 
-	ret = pci_enable_device(pdev);
-	if (ret < 0)
-		goto err_free_dev;
+	velocity_init_info(vptr, info);
 
-	ret = velocity_get_pci_info(vptr, pdev);
-	if (ret < 0) {
-		/* error message already printed */
-		goto err_disable;
-	}
+	if (vptr->bustype == BUS_PCI) {
+		vptr->pdev = to_pci_dev(dev);
 
-	ret = pci_request_regions(pdev, VELOCITY_NAME);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "No PCI resources.\n");
-		goto err_disable;
+		ret = velocity_get_pci_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
+	} else {
+		ret = velocity_get_platform_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
 	}
 
 	regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
 	if (regs == NULL) {
 		ret = -EIO;
-		goto err_release_res;
+		goto err_free_dev;
 	}
 
 	vptr->mac_regs = regs;
+	vptr->rev_id = readb(&regs->rev_id);
 
 	mac_wol_reset(regs);
 
 	for (i = 0; i < 6; i++)
-		dev->dev_addr[i] = readb(&regs->PAR[i]);
+		netdev->dev_addr[i] = readb(&regs->PAR[i]);
 
 
-	drv_string = dev_driver_string(&pdev->dev);
+	drv_string = dev_driver_string(dev);
 
 	velocity_get_options(&vptr->options, velocity_nics, drv_string);
 
@@ -2807,46 +2850,125 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
 
-	dev->netdev_ops = &velocity_netdev_ops;
-	dev->ethtool_ops = &velocity_ethtool_ops;
-	netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
+	netdev->netdev_ops = &velocity_netdev_ops;
+	netdev->ethtool_ops = &velocity_ethtool_ops;
+	netif_napi_add(netdev, &vptr->napi, velocity_poll,
+							VELOCITY_NAPI_WEIGHT);
 
-	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
+	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
 			   NETIF_F_HW_VLAN_CTAG_TX;
-	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_FILTER |
-			 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_IP_CSUM;
+	netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
+			NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
+			NETIF_F_IP_CSUM;
 
-	ret = register_netdev(dev);
+	ret = register_netdev(netdev);
 	if (ret < 0)
 		goto err_iounmap;
 
-	if (!velocity_get_link(dev)) {
-		netif_carrier_off(dev);
+	if (!velocity_get_link(netdev)) {
+		netif_carrier_off(netdev);
 		vptr->mii_status |= VELOCITY_LINK_FAIL;
 	}
 
 	velocity_print_info(vptr);
-	pci_set_drvdata(pdev, dev);
+	dev_set_drvdata(vptr->dev, netdev);
 
 	/* and leave the chip powered down */
 
-	pci_set_power_state(pdev, PCI_D3hot);
+	velocity_set_power_state(vptr, PCI_D3hot);
 	velocity_nics++;
 out:
 	return ret;
 
 err_iounmap:
 	iounmap(regs);
-err_release_res:
-	pci_release_regions(pdev);
-err_disable:
-	pci_disable_device(pdev);
 err_free_dev:
-	free_netdev(dev);
+	free_netdev(netdev);
 	goto out;
 }
 
-#ifdef CONFIG_PM
+/**
+ *	velocity_remove	- device unplug
+ *	@dev: device being removed
+ *
+ *	Device unload callback. Called on an unplug or on module
+ *	unload for each active device that is present. Disconnects
+ *	the device from the network layer and frees all the resources
+ */
+static int velocity_remove(struct device *dev)
+{
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
+
+	unregister_netdev(netdev);
+	iounmap(vptr->mac_regs);
+	free_netdev(netdev);
+	velocity_nics--;
+
+	return 0;
+}
+
+static int velocity_pci_probe(struct pci_dev *pdev,
+			   const struct pci_device_id *ent)
+{
+	int ret;
+	const struct velocity_info_tbl *info =
+					&chip_info_table[ent->driver_data];
+
+	ret = pci_enable_device(pdev);
+	if (ret < 0)
+		return ret;
+
+	ret = pci_request_regions(pdev, VELOCITY_NAME);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "No PCI resources.\n");
+		pci_disable_device(pdev);
+		return ret;
+	}
+
+	ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
+	if (ret < 0) {
+		pci_release_regions(pdev);
+		pci_disable_device(pdev);
+	}
+
+	return ret;
+}
+
+static void velocity_pci_remove(struct pci_dev *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+}
+
+static int velocity_platform_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	const struct velocity_info_tbl *info;
+	int irq;
+
+	of_id = of_match_device(velocity_of_ids, &pdev->dev);
+	if (!of_id)
+		return -EINVAL;
+	info = of_id->data;
+
+	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+	if (!irq)
+		return -EINVAL;
+
+	return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
+}
+
+static int velocity_platform_remove(struct platform_device *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
 /**
  *	wol_calc_crc		-	WOL CRC
  *	@pattern: data pattern
@@ -3003,10 +3125,10 @@ static void velocity_save_context(struct velocity_info *vptr, struct velocity_co
 
 }
 
-static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
+static int velocity_suspend(struct device *dev, pm_message_t state)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 
 	if (!netif_running(vptr->netdev))
@@ -3015,20 +3137,24 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
-	pci_save_state(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_save_state(vptr->pdev);
 
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
 		velocity_get_ip(vptr);
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
 		velocity_set_wol(vptr);
-		pci_enable_wake(pdev, PCI_D3hot, 1);
-		pci_set_power_state(pdev, PCI_D3hot);
+		if (vptr->bustype == BUS_PCI)
+			pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	} else {
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
-		pci_disable_device(pdev);
-		pci_set_power_state(pdev, pci_choose_state(pdev, state));
+		if (vptr->bustype == BUS_PCI)
+			pci_disable_device(vptr->pdev);
+		velocity_set_power_state(vptr,
+				velocity_choose_state(vptr->dev, state));
 	}
 
 	spin_unlock_irqrestore(&vptr->lock, flags);
@@ -3070,19 +3196,22 @@ static void velocity_restore_context(struct velocity_info *vptr, struct velocity
 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
 }
 
-static int velocity_resume(struct pci_dev *pdev)
+static int velocity_resume(struct device *dev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 	int i;
 
 	if (!netif_running(vptr->netdev))
 		return 0;
 
-	pci_set_power_state(pdev, PCI_D0);
-	pci_enable_wake(pdev, 0, 0);
-	pci_restore_state(pdev);
+	velocity_set_power_state(vptr, PCI_D0);
+
+	if (vptr->bustype == BUS_PCI) {
+		pci_enable_wake(vptr->pdev, 0, 0);
+		pci_restore_state(vptr->pdev);
+	}
 
 	mac_wol_reset(vptr->mac_regs);
 
@@ -3104,23 +3233,34 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	return 0;
 }
-#endif
+#endif	/* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
 
 /*
  *	Definition for our device driver. The PCI layer interface
  *	uses this to handle all our card discover and plugging
  */
-static struct pci_driver velocity_driver = {
+static struct pci_driver velocity_pci_driver = {
 	.name		= VELOCITY_NAME,
-	.id_table	= velocity_id_table,
-	.probe		= velocity_found1,
-	.remove		= velocity_remove1,
-#ifdef CONFIG_PM
-	.suspend	= velocity_suspend,
-	.resume		= velocity_resume,
-#endif
+	.id_table	= velocity_pci_id_table,
+	.probe		= velocity_pci_probe,
+	.remove		= velocity_pci_remove,
+	.driver = {
+		.pm = &velocity_pm_ops,
+	},
 };
 
+static struct platform_driver velocity_platform_driver = {
+	.probe		= velocity_platform_probe,
+	.remove		= velocity_platform_remove,
+	.driver = {
+		.name = "via-velocity",
+		.owner = THIS_MODULE,
+		.of_match_table = velocity_of_ids,
+		.pm = &velocity_pm_ops,
+	},
+};
 
 /**
  *	velocity_ethtool_up	-	pre hook for ethtool
@@ -3133,7 +3273,7 @@ static int velocity_ethtool_up(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 	return 0;
 }
 
@@ -3148,7 +3288,7 @@ static void velocity_ethtool_down(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 }
 
 static int velocity_get_settings(struct net_device *dev,
@@ -3270,7 +3410,11 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
 	struct velocity_info *vptr = netdev_priv(dev);
 	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
 	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
-	strlcpy(info->bus_info, pci_name(vptr->pdev), sizeof(info->bus_info));
+	if (vptr->bustype == BUS_PCI)
+		strlcpy(info->bus_info, pci_name(vptr->pdev),
+						sizeof(info->bus_info));
+	else
+		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
 }
 
 static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -3563,9 +3707,15 @@ static int __init velocity_init_module(void)
 	int ret;
 
 	velocity_register_notifier();
-	ret = pci_register_driver(&velocity_driver);
+
+	ret = pci_register_driver(&velocity_pci_driver);
+	if (ret < 0)
+		velocity_unregister_notifier();
+
+	ret = platform_driver_register(&velocity_platform_driver);
 	if (ret < 0)
 		velocity_unregister_notifier();
+
 	return ret;
 }
 
@@ -3580,7 +3730,9 @@ static int __init velocity_init_module(void)
 static void __exit velocity_cleanup_module(void)
 {
 	velocity_unregister_notifier();
-	pci_unregister_driver(&velocity_driver);
+
+	pci_unregister_driver(&velocity_pci_driver);
+	platform_driver_unregister(&velocity_platform_driver);
 }
 
 module_init(velocity_init_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index c38bbae..6be7e46 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1265,7 +1265,7 @@ struct velocity_context {
 #define PHYID_VT3216_64BIT  0x000FC600UL
 #define PHYID_MARVELL_1000  0x01410C50UL
 #define PHYID_MARVELL_1000S 0x01410C40UL
-
+#define PHYID_ICPLUS_IP101A 0x02430C54UL
 #define PHYID_REV_ID_MASK   0x0000000FUL
 
 #define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
@@ -1433,10 +1433,38 @@ struct velocity_opt {
 
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
+static inline char velocity_choose_state(struct device *dev,
+					   pm_message_t state)
+
+{
+	switch (state.event) {
+	case PM_EVENT_ON:
+		return PCI_D0;
+	case PM_EVENT_FREEZE:
+	case PM_EVENT_PRETHAW:
+		/* REVISIT both freeze and pre-thaw "should" use D0 */
+	case PM_EVENT_SUSPEND:
+	case PM_EVENT_HIBERNATE:
+		return PCI_D3hot;
+	default:
+		dev_info(dev, "unrecognized suspend event %d\n", state.event);
+		BUG();
+	}
+
+	return PCI_D0;
+}
+
+enum velocity_bus_type {
+	BUS_PCI,
+	BUS_PLATFORM,
+};
+
 struct velocity_info {
-	struct device *dev;
 	struct pci_dev *pdev;
+	struct device *dev;
 	struct net_device *netdev;
+	enum velocity_bus_type bustype;
+	int no_eeprom;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
-- 
1.7.9.5



From weiyj.lk at gmail.com  Mon May 13 01:49:13 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Mon, 13 May 2013 13:49:13 +0800
Subject: [PATCH] [media] s5p-tv: fix error return code in mxr_acquire_video()
Message-ID: <CAPgLHd80d_pLtTbDQLEAMiLzfoF6AZ5fpjxtxqAoAZ1myNKw+w@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Fix to return a negative error code in the vb2_dma_contig_init_ctx()
error handling case instead of 0, as done elsewhere in this function.
Also vb2_dma_contig_init_ctx() return ERR_PTR() in case of error and
never return NULL, so use IS_ERR() replace IS_ERR_OR_NULL().

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 drivers/media/platform/s5p-tv/mixer_video.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/s5p-tv/mixer_video.c b/drivers/media/platform/s5p-tv/mixer_video.c
index ef0efdf..641b1f0 100644
--- a/drivers/media/platform/s5p-tv/mixer_video.c
+++ b/drivers/media/platform/s5p-tv/mixer_video.c
@@ -81,8 +81,9 @@ int mxr_acquire_video(struct mxr_device *mdev,
 	}
 
 	mdev->alloc_ctx = vb2_dma_contig_init_ctx(mdev->dev);
-	if (IS_ERR_OR_NULL(mdev->alloc_ctx)) {
+	if (IS_ERR(mdev->alloc_ctx)) {
 		mxr_err(mdev, "could not acquire vb2 allocator\n");
+		ret = PTR_ERR(mdev->alloc_ctx);
 		goto fail_v4l2_dev;
 	}
 



From chao.xie at marvell.com  Mon May 13 01:51:32 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:32 -0400
Subject: [PATCh V10 01/12] usb: phy: protect phy init and shutdown for mutiple
 deivces
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-2-git-send-email-chao.xie@marvell.com>

Some USB devices will share same phy, so make the ->init
and ->shutdown to be protected.
Only first device will initialize the phy, and only last device
can shutdown phy.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/usb/phy/phy.c   |    6 ++++++
 include/linux/usb/phy.h |   22 ++++++++++++++++++----
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
index a9984c7..97dd396 100644
--- a/drivers/usb/phy/phy.c
+++ b/drivers/usb/phy/phy.c
@@ -329,6 +329,9 @@ int usb_add_phy(struct usb_phy *x, enum usb_phy_type type)
 		return -EINVAL;
 	}
 
+	mutex_init(&x->phy_mutex);
+	x->refcount = 0;
+
 	spin_lock_irqsave(&phy_lock, flags);
 
 	list_for_each_entry(phy, &phy_list, head) {
@@ -367,6 +370,9 @@ int usb_add_phy_dev(struct usb_phy *x)
 		return -EINVAL;
 	}
 
+	mutex_init(&x->phy_mutex);
+	x->refcount = 0;
+
 	spin_lock_irqsave(&phy_lock, flags);
 	list_for_each_entry(phy_bind, &phy_bind_list, list)
 		if (!(strcmp(phy_bind->phy_dev_name, dev_name(x->dev))))
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index 6b5978f..b645520 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -87,6 +87,14 @@ struct usb_phy {
 	/* to support controllers that have multiple transceivers */
 	struct list_head	head;
 
+	/*
+	 * PHY may be shared by multiple devices.
+	 * Being protected by phy_mutex and refcount, PHY is initialized
+	 * or shut down only once.
+	 */
+	struct mutex		phy_mutex;
+	unsigned int		refcount;
+
 	/* initialize/shutdown the OTG controller */
 	int	(*init)(struct usb_phy *x);
 	void	(*shutdown)(struct usb_phy *x);
@@ -150,17 +158,23 @@ static inline int usb_phy_io_write(struct usb_phy *x, u32 val, u32 reg)
 static inline int
 usb_phy_init(struct usb_phy *x)
 {
-	if (x->init)
-		return x->init(x);
+	int ret = 0;
 
-	return 0;
+	mutex_lock(&x->phy_mutex);
+	if (x->refcount++ == 0 && x->init)
+		ret = x->init(x);
+	mutex_unlock(&x->phy_mutex);
+
+	return ret;
 }
 
 static inline void
 usb_phy_shutdown(struct usb_phy *x)
 {
-	if (x->shutdown)
+	mutex_lock(&x->phy_mutex);
+	if (--x->refcount == 0 && x->shutdown)
 		x->shutdown(x);
+	mutex_unlock(&x->phy_mutex);
 }
 
 static inline int
-- 
1.7.4.1



From cdall at cs.columbia.edu  Mon May 13 01:52:53 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sun, 12 May 2013 22:52:53 -0700
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM
 VCPU ioctl
In-Reply-To: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
References: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
Message-ID: <20130513055253.GC64337@ubuntu>

On Thu, May 09, 2013 at 12:28:06AM +0200, Andre Przywara wrote:
> Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
> with the KVM_ARM_VCPU_INIT ioctl before being used with further
> requests. KVM_RUN checks whether this initialization has been
> done, but other ioctls do not.
> Namely KVM_GET_REG_LIST will dereference an array with index -1
> without initialization and thus leads to a kernel oops.
> Fix this by adding checks before executing the ioctl handlers.
> 
> Changes from v1:
>  * moved check into a static function with a meaningful name
> 
> Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
> ---
>  arch/arm/kvm/arm.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index c1fe498..b73b587 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -676,6 +676,15 @@ static void vcpu_pause(struct kvm_vcpu *vcpu)
>  	wait_event_interruptible(*wq, !vcpu->arch.pause);
>  }
>  
> +/*
> + * Some ioctls require initialization by KVM_ARM_VCPU_INIT first, check
> + * this with this function
> + */
> +static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
> +{
> +	return vcpu->arch.target >= 0;
> +}
> +

this should probably be a static inline in a header file instead, it's
likely that it could be called from another file.

>  /**
>   * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
>   * @vcpu:	The VCPU pointer
> @@ -692,8 +701,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
>  	int ret;
>  	sigset_t sigsaved;
>  
> -	/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
> -	if (unlikely(vcpu->arch.target < 0))
> +	if (unlikely(!kvm_vcpu_initialized(vcpu)))
>  		return -ENOEXEC;
>  
>  	ret = kvm_vcpu_first_run_init(vcpu);
> @@ -893,6 +901,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
>  	case KVM_SET_ONE_REG:
>  	case KVM_GET_ONE_REG: {
>  		struct kvm_one_reg reg;
> +
> +		if (unlikely(!kvm_vcpu_initialized(vcpu)))
> +			return -ENOEXEC;
> +
>  		if (copy_from_user(&reg, argp, sizeof(reg)))
>  			return -EFAULT;
>  		if (ioctl == KVM_SET_ONE_REG)
> @@ -905,6 +917,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
>  		struct kvm_reg_list reg_list;
>  		unsigned n;
>  
> +		if (unlikely(!kvm_vcpu_initialized(vcpu)))
> +			return -ENOEXEC;
> +
>  		if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
>  			return -EFAULT;
>  		n = reg_list.n;
> -- 
> 1.7.12.1
> 


From chao.xie at marvell.com  Mon May 13 01:51:06 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:06 -0400
Subject: [V9 PATCH 00/12] mv-usb phy driver
Message-ID: <1368424278-9735-1-git-send-email-chao.xie@marvell.com>

The patches create the mv-usb phy driver

The patches remove the callbacks in the platform data for phy
initialization and shutdown, and directly write a phy driver
and make udc/ehci/otg to call it.

  usb: phy: protect phy init and shutdown for mutiple deivces
  usb: phy: mv_usb2: add PHY driver for marvell usb2 controller
Above patches are marvell usb PHY driver support.

  usb: gadget: mv_udc: use PHY driver for udc
  usb: ehci: ehci-mv: use PHY driver for ehci
  usb: phy: phy-mv-usb: use USB2 PHY driver for otg
Above patches modify the udc/ehci/otg drivers to make use of PHY
driver.

  usb: mv_u3d: usb phy drivers for phy operation
Above patch is the fix for marvel usb3 gadget driver. It will make
use of PHY driver.

  arm: mmp2: change the defintion of usb devices
  arm: pxa910: change the defintion of usb devices
  arm: ttc_dkb: modify usb support
  arm: mmp: remove unused usb devices
  arm: brownstone: add usb support for the board
Above patches are the changes from SOCes.

  usb: mv_usb: remove the phy callbacks in pdata
Above patch finally remove the callbacks for PHY in pdata.

V2->V1:
  Change the Signed-off-by to be right email address

v3->v2
  re-format the patches to new code base

v4->v3
  1. make mv udc gadget driver depend on ARCH_PXA and ARCH_MMP
  2. remove __devinit and __devexit
  3. make the driver compiled successful if CONFIG_MV_USB2_PHY is not defined.
  The modified patches are
  usb: gadget: mv_udc: make mv_udc depends on ARCH_MMP or ARCH_PXA
  usb: phy: mv_usb2: add PHY driver for marvell usb2 controller

v5->v4
  make the struct mv_usb2_extern_chip member ->head to be
  struct atomic_notifier_head instead of struct atomic_notifier_head *.

v6->v5
  the bug fix patches are merged.
  Removed the dependcy of ARCH_MMP and ARCH_PXA, and make the driver can be
  compiled for x86.
  The device tree support patches need modification, remove them from this
  patch series, and they will be submitted in another series.


v7->v6
  Use usb_add_phy_dev and related APIs to add PHY drivers.
  Removed the device tree support in PHY driver. It will be added in another
  patch series.

v8->v7
  bugs fix in phy driver.
  directly use devm_usb_get_phy_dev return value for error return.

v9->v8
  Remove u2o_xxx.
  Add prefix for register definition
  Move mutex to common PHY layer
  Use module_platform_driver() to register driver
  Use usleep_range to replace udelay

V10->V9
  Grammar fix in comments.

Chao Xie (12):
  usb: phy: protect phy init and shutdown for mutiple deivces
  usb: phy: mv_usb2: add PHY driver for marvell usb2 controller
  usb: gadget: mv_udc: use PHY driver for udc
  usb: ehci: ehci-mv: use PHY driver for ehci
  usb: phy: phy-mv-usb: use USB2 PHY driver for otg
  usb: mv_u3d: usb phy drivers for phy operation
  arm: mmp2: change the defintion of usb devices
  arm: pxa910: change the defintion of usb devices
  arm: ttc_dkb: modify usb support
  arm: mmp: remove unused usb devices
  arm: brownstone: add usb support for the board
  usb: mv_usb: remove the phy callbacks in pdata

 arch/arm/mach-mmp/brownstone.c          |   56 +++++
 arch/arm/mach-mmp/include/mach/mmp2.h   |    4 +
 arch/arm/mach-mmp/include/mach/pxa910.h |    7 +-
 arch/arm/mach-mmp/mmp2.c                |    4 +
 arch/arm/mach-mmp/pxa910.c              |    4 +
 arch/arm/mach-mmp/ttc_dkb.c             |   39 +++-
 drivers/usb/gadget/mv_u3d.h             |    3 +-
 drivers/usb/gadget/mv_u3d_core.c        |   54 ++---
 drivers/usb/gadget/mv_udc.h             |    2 +-
 drivers/usb/gadget/mv_udc_core.c        |   50 ++---
 drivers/usb/host/ehci-mv.c              |   49 ++---
 drivers/usb/phy/Kconfig                 |    6 +
 drivers/usb/phy/Makefile                |    1 +
 drivers/usb/phy/phy-mv-usb.c            |   53 ++---
 drivers/usb/phy/phy-mv-usb.h            |    2 +-
 drivers/usb/phy/phy-mv-usb2.c           |  380 +++++++++++++++++++++++++++++++
 drivers/usb/phy/phy.c                   |    6 +
 include/linux/platform_data/mv_usb.h    |    3 -
 include/linux/usb/mv_usb2.h             |   29 +++
 include/linux/usb/phy.h                 |   22 ++-
 20 files changed, 624 insertions(+), 150 deletions(-)
 create mode 100644 drivers/usb/phy/phy-mv-usb2.c
 create mode 100644 include/linux/usb/mv_usb2.h

-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:34 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:34 -0400
Subject: [PATCh V10 03/12] usb: gadget: mv_udc: use PHY driver for udc
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-4-git-send-email-chao.xie@marvell.com>

Originaly, udc driver will call the callbacks in platform data
for PHY initialization and shut down.
With PHY driver, it will call the APIs provided by PHY driver
for PHY initialization and shut down. It removes the callbacks
in platform data, and at same time it removes one block in the
way of enabling device tree for udc driver.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/usb/gadget/mv_udc.h      |    2 +-
 drivers/usb/gadget/mv_udc_core.c |   50 +++++++++++++-------------------------
 2 files changed, 18 insertions(+), 34 deletions(-)

diff --git a/drivers/usb/gadget/mv_udc.h b/drivers/usb/gadget/mv_udc.h
index be77f20..02f36fe 100644
--- a/drivers/usb/gadget/mv_udc.h
+++ b/drivers/usb/gadget/mv_udc.h
@@ -180,7 +180,6 @@ struct mv_udc {
 
 	struct mv_cap_regs __iomem	*cap_regs;
 	struct mv_op_regs __iomem	*op_regs;
-	void __iomem                    *phy_regs;
 	unsigned int			max_eps;
 	struct mv_dqh			*ep_dqh;
 	size_t				ep_dqh_size;
@@ -217,6 +216,7 @@ struct mv_udc {
 	struct work_struct	vbus_work;
 	struct workqueue_struct *qwork;
 
+	struct usb_phy		*phy;
 	struct usb_phy		*transceiver;
 
 	struct mv_usb_platform_data     *pdata;
diff --git a/drivers/usb/gadget/mv_udc_core.c b/drivers/usb/gadget/mv_udc_core.c
index c2a5702..a6beef6 100644
--- a/drivers/usb/gadget/mv_udc_core.c
+++ b/drivers/usb/gadget/mv_udc_core.c
@@ -35,6 +35,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/platform_data/mv_usb.h>
+#include <linux/usb/mv_usb2.h>
 #include <asm/unaligned.h>
 
 #include "mv_udc.h"
@@ -1083,15 +1084,14 @@ static int mv_udc_enable_internal(struct mv_udc *udc)
 
 	dev_dbg(&udc->dev->dev, "enable udc\n");
 	udc_clock_enable(udc);
-	if (udc->pdata->phy_init) {
-		retval = udc->pdata->phy_init(udc->phy_regs);
-		if (retval) {
-			dev_err(&udc->dev->dev,
-				"init phy error %d\n", retval);
-			udc_clock_disable(udc);
-			return retval;
-		}
+	retval = usb_phy_init(udc->phy);
+	if (retval) {
+		dev_err(&udc->dev->dev,
+			"init phy error %d\n", retval);
+		udc_clock_disable(udc);
+		return retval;
 	}
+
 	udc->active = 1;
 
 	return 0;
@@ -1109,8 +1109,7 @@ static void mv_udc_disable_internal(struct mv_udc *udc)
 {
 	if (udc->active) {
 		dev_dbg(&udc->dev->dev, "disable udc\n");
-		if (udc->pdata->phy_deinit)
-			udc->pdata->phy_deinit(udc->phy_regs);
+		usb_phy_shutdown(udc->phy);
 		udc_clock_disable(udc);
 		udc->active = 0;
 	}
@@ -2124,17 +2123,10 @@ static int mv_udc_probe(struct platform_device *pdev)
 	udc->dev = pdev;
 
 	if (pdata->mode == MV_USB_MODE_OTG) {
-		udc->transceiver = devm_usb_get_phy(&pdev->dev,
-					USB_PHY_TYPE_USB2);
-		if (IS_ERR(udc->transceiver)) {
-			retval = PTR_ERR(udc->transceiver);
-
-			if (retval == -ENXIO)
-				return retval;
-
-			udc->transceiver = NULL;
-			return -EPROBE_DEFER;
-		}
+		udc->transceiver = devm_usb_get_phy_dev(&pdev->dev,
+					MV_USB2_OTG_PHY_INDEX);
+		if (IS_ERR_OR_NULL(udc->transceiver))
+			return PTR_ERR(udc->transceiver);
 	}
 
 	/* udc only have one sysclk. */
@@ -2142,7 +2134,7 @@ static int mv_udc_probe(struct platform_device *pdev)
 	if (IS_ERR(udc->clk))
 		return PTR_ERR(udc->clk);
 
-	r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
+	r = platform_get_resource(udc->dev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
 		dev_err(&pdev->dev, "no I/O memory resource defined\n");
 		return -ENODEV;
@@ -2155,17 +2147,9 @@ static int mv_udc_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
-		return -ENODEV;
-	}
-
-	udc->phy_regs = ioremap(r->start, resource_size(r));
-	if (udc->phy_regs == NULL) {
-		dev_err(&pdev->dev, "failed to map phy I/O memory\n");
-		return -EBUSY;
-	}
+	udc->phy = devm_usb_get_phy_dev(&pdev->dev, MV_USB2_PHY_INDEX);
+	if (IS_ERR_OR_NULL(udc->phy))
+		return PTR_ERR(udc->phy);
 
 	/* we will acces controller register, so enable the clk */
 	retval = mv_udc_enable_internal(udc);
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:35 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:35 -0400
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-5-git-send-email-chao.xie@marvell.com>

Originaly, ehci driver will call the callbacks in platform data
for PHY initialization and shut down.
With PHY driver, it will call the APIs provided by PHY driver
for PHY initialization and shutdown. It removes the callbacks
in platform data, and at same time it removes one block in the
way of enabling device tree for ehci driver.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/usb/host/ehci-mv.c |   49 +++++++++++++++----------------------------
 1 files changed, 17 insertions(+), 32 deletions(-)

diff --git a/drivers/usb/host/ehci-mv.c b/drivers/usb/host/ehci-mv.c
index 6bad41a..adfc11f 100644
--- a/drivers/usb/host/ehci-mv.c
+++ b/drivers/usb/host/ehci-mv.c
@@ -15,17 +15,18 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/mv_usb2.h>
 #include <linux/platform_data/mv_usb.h>
 
 #define CAPLENGTH_MASK         (0xff)
 
 struct ehci_hcd_mv {
 	struct usb_hcd *hcd;
+	struct usb_phy *phy;
 
 	/* Which mode does this ehci running OTG/Host ? */
 	int mode;
 
-	void __iomem *phy_regs;
 	void __iomem *cap_regs;
 	void __iomem *op_regs;
 
@@ -48,22 +49,15 @@ static void ehci_clock_disable(struct ehci_hcd_mv *ehci_mv)
 
 static int mv_ehci_enable(struct ehci_hcd_mv *ehci_mv)
 {
-	int retval;
-
 	ehci_clock_enable(ehci_mv);
-	if (ehci_mv->pdata->phy_init) {
-		retval = ehci_mv->pdata->phy_init(ehci_mv->phy_regs);
-		if (retval)
-			return retval;
-	}
 
-	return 0;
+	return usb_phy_init(ehci_mv->phy);
 }
 
 static void mv_ehci_disable(struct ehci_hcd_mv *ehci_mv)
 {
-	if (ehci_mv->pdata->phy_deinit)
-		ehci_mv->pdata->phy_deinit(ehci_mv->phy_regs);
+	usb_phy_shutdown(ehci_mv->phy);
+
 	ehci_clock_disable(ehci_mv);
 }
 
@@ -169,22 +163,7 @@ static int mv_ehci_probe(struct platform_device *pdev)
 		goto err_clear_drvdata;
 	}
 
-	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phyregs");
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
-		retval = -ENODEV;
-		goto err_clear_drvdata;
-	}
-
-	ehci_mv->phy_regs = devm_ioremap(&pdev->dev, r->start,
-					 resource_size(r));
-	if (ehci_mv->phy_regs == 0) {
-		dev_err(&pdev->dev, "failed to map phy I/O memory\n");
-		retval = -EFAULT;
-		goto err_clear_drvdata;
-	}
-
-	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "capregs");
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!r) {
 		dev_err(&pdev->dev, "no I/O memory resource defined\n");
 		retval = -ENODEV;
@@ -199,6 +178,14 @@ static int mv_ehci_probe(struct platform_device *pdev)
 		goto err_clear_drvdata;
 	}
 
+	ehci_mv->phy = devm_usb_get_phy_dev(&pdev->dev, MV_USB2_PHY_INDEX);
+	if (IS_ERR_OR_NULL(ehci_mv->phy)) {
+		retval = PTR_ERR(ehci_mv->phy);
+		if (retval != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "failed to get the outer phy\n");
+		goto err_clear_drvdata;
+	}
+
 	retval = mv_ehci_enable(ehci_mv);
 	if (retval) {
 		dev_err(&pdev->dev, "init phy error %d\n", retval);
@@ -225,14 +212,15 @@ static int mv_ehci_probe(struct platform_device *pdev)
 
 	ehci_mv->mode = pdata->mode;
 	if (ehci_mv->mode == MV_USB_MODE_OTG) {
-		ehci_mv->otg = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+		ehci_mv->otg = devm_usb_get_phy_dev(&pdev->dev,
+						MV_USB2_OTG_PHY_INDEX);
 		if (IS_ERR(ehci_mv->otg)) {
 			retval = PTR_ERR(ehci_mv->otg);
 
 			if (retval == -ENXIO)
 				dev_info(&pdev->dev, "MV_USB_MODE_OTG "
 						"must have CONFIG_USB_PHY enabled\n");
-			else
+			else if (retval != -EPROBE_DEFER)
 				dev_err(&pdev->dev,
 						"unable to find transceiver\n");
 			goto err_disable_clk;
@@ -259,9 +247,6 @@ static int mv_ehci_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (pdata->private_init)
-		pdata->private_init(ehci_mv->op_regs, ehci_mv->phy_regs);
-
 	dev_info(&pdev->dev,
 		 "successful find EHCI device with regs 0x%p irq %d"
 		 " working in %s mode\n", hcd->regs, hcd->irq,
-- 
1.7.4.1



From cdall at cs.columbia.edu  Mon May 13 01:53:54 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Sun, 12 May 2013 22:53:54 -0700
Subject: [PATCH] ARM: KVM: prevent NULL pointer dereference with KVM ioctl
In-Reply-To: <20130513051352.GA64337@ubuntu>
References: <1367931313-14839-1-git-send-email-andre.przywara@linaro.org>
 <518A2098.9010909@arm.com> <20130513051352.GA64337@ubuntu>
Message-ID: <CAEDV+g+difK63VWM5Q0yWfJ2Jtn2AUAUB2L6-z0RU1KQ1Y4HkQ@mail.gmail.com>

On Sun, May 12, 2013 at 10:13 PM, Christoffer Dall
<cdall at cs.columbia.edu> wrote:
> On Wed, May 08, 2013 at 10:53:28AM +0100, Marc Zyngier wrote:
>> On 07/05/13 13:55, Andre Przywara wrote:
>> > Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
>> > with the KVM_ARM_VCPU_INIT ioctl before being used with further
>> > requests. KVM_RUN checks whether this initialization has been
>> > done, but other ioctls do not.
>> > Namely KVM_GET_REG_LIST will dereference an array with index -1
>> > without initialization and thus leads to a kernel oops.
>> > Fix this by adding checks before executing the ioctl handlers.
>> >
>> > Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
>> > ---
>> >  arch/arm/kvm/arm.c | 9 +++++++++
>> >  1 file changed, 9 insertions(+)
>> >
>> > diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>> > index c1fe498..0c571ff 100644
>> > --- a/arch/arm/kvm/arm.c
>> > +++ b/arch/arm/kvm/arm.c
>> > @@ -893,6 +893,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
>> >     case KVM_SET_ONE_REG:
>> >     case KVM_GET_ONE_REG: {
>> >             struct kvm_one_reg reg;
>> > +
>> > +           /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
>> > +           if (unlikely(vcpu->arch.target < 0))
>> > +                   return -ENOEXEC;
>> > +
>> >             if (copy_from_user(&reg, argp, sizeof(reg)))
>> >                     return -EFAULT;
>> >             if (ioctl == KVM_SET_ONE_REG)
>> > @@ -905,6 +910,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
>> >             struct kvm_reg_list reg_list;
>> >             unsigned n;
>> >
>> > +           /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
>> > +           if (unlikely(vcpu->arch.target < 0))
>> > +                   return -ENOEXEC;
>> > +
>> >             if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
>> >                     return -EFAULT;
>> >             n = reg_list.n;
>> >
>>
>> So we also have the same snippet in kvm_arch_vcpu_ioctl_run().
>>
>> Can you create a static function (kvm_vcpu_initialized?) containing that
>> code and make all three sites use it?
>>
> Andre, will you re-spin your patch as per Marc's comments?
>
oh, never mind, missed it when I looked over the mails.

-Christoffer


From chao.xie at marvell.com  Mon May 13 01:51:39 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:39 -0400
Subject: [PATCh V10 08/12] arm: pxa910: change the defintion of usb devices
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-9-git-send-email-chao.xie@marvell.com>

because phy is seperated from the usb controller driver,
we can use the common pxa_device_desc for device register.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/mach-mmp/include/mach/pxa910.h |    4 ++++
 arch/arm/mach-mmp/pxa910.c              |    4 ++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index b914afa..c695982 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -22,6 +22,10 @@ extern struct pxa_device_desc pxa910_device_nand;
 extern struct platform_device pxa168_device_u2o;
 extern struct platform_device pxa168_device_u2ootg;
 extern struct platform_device pxa168_device_u2oehci;
+extern struct pxa_device_desc pxa910_device_u2o;
+extern struct pxa_device_desc pxa910_device_u2ootg;
+extern struct pxa_device_desc pxa910_device_u2oehci;
+extern struct pxa_device_desc pxa910_device_u2ophy;
 extern struct pxa_device_desc pxa910_device_disp;
 extern struct pxa_device_desc pxa910_device_fb;
 extern struct pxa_device_desc pxa910_device_panel;
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 36cb321..28fdce5 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -134,6 +134,10 @@ PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
 PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
+PXA910_DEVICE(u2ophy, "pxa910-usb-phy", -1, NONE, 0xd4207000, 0x1ff);
+PXA910_DEVICE(u2o, "mv-udc", -1, USB1, 0xd4208100, 0x1ff);
+PXA910_DEVICE(u2ootg, "mv-otg", -1, USB1, 0xd4208100, 0x1ff);
+PXA910_DEVICE(u2oehci, "mv-ehci", -1, USB1, 0xd4208100, 0x1ff);
 PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
 PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
 PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:42 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:42 -0400
Subject: [PATCh V10 11/12] arm: brownstone: add usb support for the board
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-12-git-send-email-chao.xie@marvell.com>

for brownstone board, add the udc/otg/ehci support

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/mach-mmp/brownstone.c |   56 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 2358011..aed553a 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -18,6 +18,9 @@
 #include <linux/regulator/max8649.h>
 #include <linux/regulator/fixed.h>
 #include <linux/mfd/max8925.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/mv_usb2.h>
+#include <linux/platform_data/mv_usb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -195,6 +198,20 @@ static struct sram_platdata mmp2_isram_platdata = {
 	.granularity	= SRAM_GRANULARITY,
 };
 
+#ifdef CONFIG_USB_SUPPORT
+
+#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)
+
+static struct mv_usb_platform_data brownstone_usb_pdata = {
+	.vbus		= NULL,
+	.mode		= MV_USB_MODE_OTG,
+	.otg_force_a_bus_req = 1,
+	.set_vbus	= NULL,
+};
+#endif
+#endif
+
+
 static void __init brownstone_init(void)
 {
 	mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
@@ -211,6 +228,45 @@ static void __init brownstone_init(void)
 
 	/* enable 5v regulator */
 	platform_device_register(&brownstone_v_5vp_device);
+
+#ifdef CONFIG_USB_SUPPORT
+	pxa_register_device(&mmp2_device_u2ophy, NULL, 0);
+#endif
+
+#ifdef CONFIG_USB_MV_UDC
+	/* for usb2 phy */
+	usb_bind_phy(mmp2_device_u2o.drv_name, MV_USB2_PHY_INDEX,
+		     mmp2_device_u2ophy.drv_name);
+#ifdef CONFIG_USB_MV_OTG
+	/* for usb2 otg phy */
+	usb_bind_phy(mmp2_device_u2o.drv_name, MV_USB2_OTG_PHY_INDEX,
+		     mmp2_device_u2ootg.drv_name);
+#endif
+	pxa_register_device(&mmp2_device_u2o, &brownstone_usb_pdata,
+			    sizeof(brownstone_usb_pdata));
+#endif
+
+#ifdef CONFIG_USB_EHCI_MV_U2O
+	/* for usb2 phy */
+	usb_bind_phy(mmp2_device_u2oehci.dev_name, MV_USB2_PHY_INDEX,
+		     mmp2_device_u2ophy.dev_name);
+#ifdef CONFIG_USB_MV_OTG
+	/* for usb2 otg phy */
+	usb_bind_phy(mmp2_device_u2oehci.drv_name, MV_USB2_OTG_PHY_INDEX,
+		     mmp2_device_u2ootg.drv_name);
+#endif
+	pxa_register_device(&mmp2_device_u2oehci, &brownstone_usb_pdata,
+			    sizeof(brownstone_usb_pdata));
+#endif
+
+#ifdef CONFIG_USB_MV_OTG
+	/* for usb2 phy */
+	usb_bind_phy(mmp2_device_u2ootg.dev_name, MV_USB2_PHY_INDEX,
+		     mmp2_device_u2ophy.dev_name);
+	pxa_register_device(&mmp2_device_u2ootg, &brownstone_usb_pdata,
+			    sizeof(brownstone_usb_pdata));
+#endif
+
 }
 
 MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:33 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:33 -0400
Subject: [PATCh V10 02/12] usb: phy: mv_usb2: add PHY driver for marvell usb2
 controller
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-3-git-send-email-chao.xie@marvell.com>

The PHY is seperated from usb controller.
The usb controller used in marvell pxa168/pxa910/mmp2 are same,
but PHY initialization may be different.
the usb controller can support udc/otg/ehci, and for each of
the mode, it need PHY to initialized before use the controller.
Direclty writing the phy driver will make the usb controller
driver to be simple and portable.
The PHY driver will be used by marvell udc/otg/ehci.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/usb/phy/Kconfig       |    9 +
 drivers/usb/phy/Makefile      |    1 +
 drivers/usb/phy/phy-mv-usb2.c |  379 +++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/mv_usb2.h   |   29 +++
 4 files changed, 418 insertions(+), 0 deletions(-)
 create mode 100644 drivers/usb/phy/phy-mv-usb2.c
 create mode 100644 include/linux/usb/mv_usb2.h

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 372db48..9c03da1 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -170,6 +170,15 @@ config USB_MV_OTG
 
 	  To compile this driver as a module, choose M here.
 
+config MV_USB2_PHY
+	tristate "Marvell USB 2.0 PHY Driver"
+	help
+	  Enable this to support Marvell USB 2.0 PHY driver for Marvell
+	  SoC. This driver will do the PHY initialization and shutdown.
+	  The PHY driver will be used by Marvell udc/ehci/otg driver.
+
+	  To compile this driver as a module, choose M here.
+
 config USB_MXS_PHY
 	tristate "Freescale MXS USB PHY support"
 	depends on ARCH_MXC || ARCH_MXS
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 33863c0..90cc5f5 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA)		+= phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)		+= phy-gpio-vbus-usb.o
 obj-$(CONFIG_USB_ISP1301)		+= phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)		+= phy-msm-usb.o
+obj-$(CONFIG_MV_USB2_PHY)		+= phy-mv-usb2.o
 obj-$(CONFIG_USB_MV_OTG)		+= phy-mv-usb.o
 obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o
 obj-$(CONFIG_USB_RCAR_PHY)		+= phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-mv-usb2.c b/drivers/usb/phy/phy-mv-usb2.c
new file mode 100644
index 0000000..43459ef
--- /dev/null
+++ b/drivers/usb/phy/phy-mv-usb2.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (C) 2013 Marvell Inc.
+ *
+ * Author:
+ *	Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/mv_usb.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/mv_usb2.h>
+
+/* phy regs */
+/* for pxa910 and mmp2, there is no revision register */
+#define MV_USB2_UTMI_REVISION		0x0
+#define MV_USB2_UTMI_CTRL		0x4
+#define MV_USB2_UTMI_PLL		0x8
+#define MV_USB2_UTMI_TX			0xc
+#define MV_USB2_UTMI_RX			0x10
+#define MV_USB2_UTMI_IVREF		0x14
+#define MV_USB2_UTMI_T0			0x18
+#define MV_USB2_UTMI_T1			0x1c
+#define MV_USB2_UTMI_T2			0x20
+#define MV_USB2_UTMI_T3			0x24
+#define MV_USB2_UTMI_T4			0x28
+#define MV_USB2_UTMI_T5			0x2c
+#define MV_USB2_UTMI_RESERVE		0x30
+#define MV_USB2_UTMI_USB_INT		0x34
+#define MV_USB2_UTMI_DBG_CTL		0x38
+#define MV_USB2_UTMI_OTG_ADDON		0x3c
+
+/* For UTMICTRL Register */
+#define MV_USB2_UTMI_CTRL_USB_CLK_EN			(1 << 31)
+/* pxa168 */
+#define MV_USB2_UTMI_CTRL_SUSPEND_SET1			(1 << 30)
+#define MV_USB2_UTMI_CTRL_SUSPEND_SET2			(1 << 29)
+#define MV_USB2_UTMI_CTRL_RXBUF_PDWN			(1 << 24)
+#define MV_USB2_UTMI_CTRL_TXBUF_PDWN			(1 << 11)
+
+#define MV_USB2_UTMI_CTRL_INPKT_DELAY_SHIFT		30
+#define MV_USB2_UTMI_CTRL_INPKT_DELAY_SOF_SHIFT		28
+#define MV_USB2_UTMI_CTRL_PU_REF_SHIFT			20
+#define MV_USB2_UTMI_CTRL_ARC_PULLDN_SHIFT		12
+#define MV_USB2_UTMI_CTRL_PLL_PWR_UP_SHIFT		1
+#define MV_USB2_UTMI_CTRL_PWR_UP_SHIFT			0
+
+/* For UTMI_PLL Register */
+#define MV_USB2_UTMI_PLL_PLLCALI12_SHIFT		29
+#define MV_USB2_UTMI_PLL_PLLCALI12_MASK			(0x3 << 29)
+
+#define MV_USB2_UTMI_PLL_PLLVDD18_SHIFT			27
+#define MV_USB2_UTMI_PLL_PLLVDD18_MASK			(0x3 << 27)
+
+#define MV_USB2_UTMI_PLL_PLLVDD12_SHIFT			25
+#define MV_USB2_UTMI_PLL_PLLVDD12_MASK			(0x3 << 25)
+
+#define MV_USB2_UTMI_PLL_PLL_READY			(0x1 << 23)
+#define MV_USB2_UTMI_PLL_KVCO_EXT			(0x1 << 22)
+#define MV_USB2_UTMI_PLL_VCOCAL_START			(0x1 << 21)
+
+#define MV_USB2_UTMI_PLL_KVCO_SHIFT			15
+#define MV_USB2_UTMI_PLL_KVCO_MASK			(0x7 << 15)
+
+#define MV_USB2_UTMI_PLL_ICP_SHIFT			12
+#define MV_USB2_UTMI_PLL_ICP_MASK			(0x7 << 12)
+
+#define MV_USB2_UTMI_PLL_FBDIV_SHIFT			4
+#define MV_USB2_UTMI_PLL_FBDIV_MASK			(0xFF << 4)
+
+#define MV_USB2_UTMI_PLL_REFDIV_SHIFT			0
+#define MV_USB2_UTMI_PLL_REFDIV_MASK			(0xF << 0)
+
+/* For UTMI_TX Register */
+#define MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_SHIFT		27
+#define MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_MASK		(0xf << 27)
+
+#define MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT	26
+#define MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_EN_MASK		(0x1 << 26)
+
+#define MV_USB2_UTMI_TX_TXVDD12_SHIFT			22
+#define MV_USB2_UTMI_TX_TXVDD12_MASK			(0x3 << 22)
+
+#define MV_USB2_UTMI_TX_CK60_PHSEL_SHIFT		17
+#define MV_USB2_UTMI_TX_CK60_PHSEL_MASK			(0xf << 17)
+
+#define MV_USB2_UTMI_TX_IMPCAL_VTH_SHIFT		14
+#define MV_USB2_UTMI_TX_IMPCAL_VTH_MASK			(0x7 << 14)
+
+#define MV_USB2_UTMI_TX_REG_RCAL_START			(0x1 << 12)
+
+#define MV_USB2_UTMI_TX_LOW_VDD_EN_SHIFT		11
+
+#define MV_USB2_UTMI_TX_AMP_SHIFT			0
+#define MV_USB2_UTMI_TX_AMP_MASK			(0x7 << 0)
+
+/* For UTMI_RX Register */
+#define MV_USB2_UTMI_RX_REG_SQ_LENGTH_SHIFT		15
+#define MV_USB2_UTMI_RX_REG_SQ_LENGTH_MASK		(0x3 << 15)
+
+#define MV_USB2_UTMI_RX_SQ_THRESH_SHIFT			4
+#define MV_USB2_UTMI_RX_SQ_THRESH_MASK			(0xf << 4)
+
+/* For UTMI_OTG_ADDON Register. Only for pxa168 */
+#define MV_USB2_UTMI_OTG_ADDON_OTG_ON			(1 << 0)
+
+enum mv_usb2_phy_type {
+	PXA168_USB,
+	PXA910_USB,
+	MMP2_USB,
+};
+
+static int _mv_usb2_phy_init(struct mv_usb2_phy *mv_phy)
+{
+	struct platform_device *pdev = mv_phy->pdev;
+	unsigned int loops = 0;
+	void __iomem *base = mv_phy->base;
+	unsigned int val;
+
+	val = readl(base + MV_USB2_UTMI_CTRL);
+	/* Initialize the USB PHY power */
+	if (mv_phy->type == PXA910_USB) {
+		val |= (1 << MV_USB2_UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
+			| (1 << MV_USB2_UTMI_CTRL_PU_REF_SHIFT);
+	}
+
+	val |= (1 << MV_USB2_UTMI_CTRL_PLL_PWR_UP_SHIFT)
+		| (1 << MV_USB2_UTMI_CTRL_PWR_UP_SHIFT);
+	writel(val, base + MV_USB2_UTMI_CTRL);
+
+	/* UTMI_PLL settings */
+	val = readl(base + MV_USB2_UTMI_PLL);
+	val &= ~(MV_USB2_UTMI_PLL_PLLVDD18_MASK
+		| MV_USB2_UTMI_PLL_PLLVDD12_MASK
+		| MV_USB2_UTMI_PLL_PLLCALI12_MASK
+		| MV_USB2_UTMI_PLL_FBDIV_MASK
+		| MV_USB2_UTMI_PLL_REFDIV_MASK
+		| MV_USB2_UTMI_PLL_ICP_MASK
+		| MV_USB2_UTMI_PLL_KVCO_MASK
+		| MV_USB2_UTMI_PLL_VCOCAL_START);
+
+	val |= (0xee << MV_USB2_UTMI_PLL_FBDIV_SHIFT)
+		| (0xb << MV_USB2_UTMI_PLL_REFDIV_SHIFT)
+		| (3 << MV_USB2_UTMI_PLL_PLLVDD18_SHIFT)
+		| (3 << MV_USB2_UTMI_PLL_PLLVDD12_SHIFT)
+		| (3 << MV_USB2_UTMI_PLL_PLLCALI12_SHIFT)
+		| (1 << MV_USB2_UTMI_PLL_ICP_SHIFT)
+		| (3 << MV_USB2_UTMI_PLL_KVCO_SHIFT);
+	writel(val, base + MV_USB2_UTMI_PLL);
+
+	/* UTMI_TX */
+	val = readl(base + MV_USB2_UTMI_TX);
+	val &= ~(MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
+		| MV_USB2_UTMI_TX_TXVDD12_MASK
+		| MV_USB2_UTMI_TX_CK60_PHSEL_MASK
+		| MV_USB2_UTMI_TX_IMPCAL_VTH_MASK
+		| MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_MASK
+		| MV_USB2_UTMI_TX_AMP_MASK
+		| MV_USB2_UTMI_TX_REG_RCAL_START);
+	val |= (3 << MV_USB2_UTMI_TX_TXVDD12_SHIFT)
+		| (4 << MV_USB2_UTMI_TX_CK60_PHSEL_SHIFT)
+		| (4 << MV_USB2_UTMI_TX_IMPCAL_VTH_SHIFT)
+		| (8 << MV_USB2_UTMI_TX_REG_EXT_FS_RCAL_SHIFT)
+		| (3 << MV_USB2_UTMI_TX_AMP_SHIFT);
+	writel(val, base + MV_USB2_UTMI_TX);
+
+	/* UTMI_RX */
+	val = readl(base + MV_USB2_UTMI_RX);
+	val &= ~(MV_USB2_UTMI_RX_SQ_THRESH_MASK
+		| MV_USB2_UTMI_RX_REG_SQ_LENGTH_MASK);
+	val |= (7 << MV_USB2_UTMI_RX_SQ_THRESH_SHIFT)
+		| (2 << MV_USB2_UTMI_RX_REG_SQ_LENGTH_SHIFT);
+	writel(val, base + MV_USB2_UTMI_RX);
+
+	/* UTMI_IVREF */
+	if (mv_phy->type == PXA168_USB)
+		/*
+		 * Fixing Microsoft Altair board interface with NEC hub issue -
+		 * Set UTMI_IVREF from 0x4a3 to 0x4bf.
+		 */
+		writel(0x4bf, base + MV_USB2_UTMI_IVREF);
+
+	/*
+	 * Toggle VCOCAL_START bit of UTMI_PLL. It is active at rising edge.
+	 * It is low level by UTMI_PLL initialization above.
+	 */
+	val = readl(base + MV_USB2_UTMI_PLL);
+	/*
+	 * Delay 200us for low level, and 40us for high level.
+	 * Make sure we can get a effective rising edege.
+	 * It should be set to low after issue rising edge.
+	 * The delay value is suggested by DE.
+	 */
+	usleep_range(200, 300);
+	val |= MV_USB2_UTMI_PLL_VCOCAL_START;
+	writel(val, base + MV_USB2_UTMI_PLL);
+	usleep_range(40, 50);
+	val &= ~MV_USB2_UTMI_PLL_VCOCAL_START;
+	writel(val, base + MV_USB2_UTMI_PLL);
+
+	/*
+	 * Toggle REG_RCAL_START bit of UTMI_TX.
+	 * it is low level by UTMI_TX initialization above.
+	 */
+	val = readl(base + MV_USB2_UTMI_TX);
+	/* same as VCOCAL_START, except it is triggered by low->high->low */
+	usleep_range(400, 500);
+	val |= MV_USB2_UTMI_TX_REG_RCAL_START;
+	writel(val, base + MV_USB2_UTMI_TX);
+	usleep_range(40, 50);
+	val &= ~MV_USB2_UTMI_TX_REG_RCAL_START;
+	writel(val, base + MV_USB2_UTMI_TX);
+	usleep_range(400, 500);
+
+	/* Make sure PHY PLL is ready */
+	loops = 0;
+	while (1) {
+		val = readl(base + MV_USB2_UTMI_PLL);
+		if (val & MV_USB2_UTMI_PLL_PLL_READY)
+			break;
+		usleep_range(1000, 1100);
+		loops++;
+		if (loops > 100) {
+			dev_warn(&pdev->dev, "calibrate timeout, UTMI_PLL %x\n",
+				 readl(base + MV_USB2_UTMI_PLL));
+			return -ETIME;
+		}
+	}
+
+	if (mv_phy->type == PXA168_USB) {
+		val = readl(base + MV_USB2_UTMI_RESERVE);
+		val |= (1 << 5);
+		writel(val, base + MV_USB2_UTMI_RESERVE);
+		/* Turn on UTMI PHY OTG extension */
+		writel(MV_USB2_UTMI_OTG_ADDON_OTG_ON,
+		       base + MV_USB2_UTMI_OTG_ADDON);
+	}
+
+	return 0;
+}
+
+static int _mv_usb2_phy_shutdown(struct mv_usb2_phy *mv_phy)
+{
+	void __iomem *base = mv_phy->base;
+	unsigned int val;
+
+	if (mv_phy->type == PXA168_USB)
+		writel(0, base + MV_USB2_UTMI_OTG_ADDON);
+
+	val = readl(base + MV_USB2_UTMI_CTRL);
+	val &= ~(MV_USB2_UTMI_CTRL_RXBUF_PDWN
+		| MV_USB2_UTMI_CTRL_TXBUF_PDWN
+		| MV_USB2_UTMI_CTRL_USB_CLK_EN
+		| (1 << MV_USB2_UTMI_CTRL_PWR_UP_SHIFT)
+		| (1 << MV_USB2_UTMI_CTRL_PLL_PWR_UP_SHIFT));
+
+	writel(val, base + MV_USB2_UTMI_CTRL);
+
+	return 0;
+}
+
+static int mv_usb2_phy_init(struct usb_phy *phy)
+{
+	struct mv_usb2_phy *mv_phy = container_of(phy, struct mv_usb2_phy, phy);
+
+	clk_prepare_enable(mv_phy->clk);
+	_mv_usb2_phy_init(mv_phy);
+
+	return 0;
+}
+
+static void mv_usb2_phy_shutdown(struct usb_phy *phy)
+{
+	struct mv_usb2_phy *mv_phy = container_of(phy, struct mv_usb2_phy, phy);
+
+	_mv_usb2_phy_shutdown(mv_phy);
+	clk_disable_unprepare(mv_phy->clk);
+}
+
+static int mv_usb2_phy_probe(struct platform_device *pdev)
+{
+	struct mv_usb2_phy *mv_phy;
+	struct resource *r;
+	const struct platform_device_id *id;
+
+	mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
+	if (mv_phy == NULL) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	id = platform_get_device_id(pdev);
+
+	if (id == NULL) {
+		dev_err(&pdev->dev, "missing id_entry\n");
+		return -ENODEV;
+	}
+
+	mv_phy->type = (unsigned int)(id->driver_data);
+	mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(mv_phy->clk)) {
+		dev_err(&pdev->dev, "failed to get clock.\n");
+		return PTR_ERR(mv_phy->clk);
+	}
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (r == NULL) {
+		dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
+		return -ENODEV;
+	}
+	mv_phy->base = devm_ioremap_resource(&pdev->dev, r);
+	if (mv_phy->base == NULL) {
+		dev_err(&pdev->dev, "error map register base\n");
+		return -EBUSY;
+	}
+
+	mv_phy->phy.dev = &pdev->dev;
+	mv_phy->phy.label = "mv-usb2";
+	mv_phy->phy.type = USB_PHY_TYPE_USB2;
+	mv_phy->phy.init = mv_usb2_phy_init;
+	mv_phy->phy.shutdown = mv_usb2_phy_shutdown;
+
+	usb_add_phy_dev(&mv_phy->phy);
+
+	platform_set_drvdata(pdev, mv_phy);
+
+	return 0;
+}
+
+static int mv_usb2_phy_remove(struct platform_device *pdev)
+{
+	struct mv_usb2_phy *mv_phy = platform_get_drvdata(pdev);
+
+	usb_remove_phy(&mv_phy->phy);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_device_id mv_usb2_phy_ids[] = {
+	{ .name = "pxa168-usb-phy",	.driver_data = PXA168_USB },
+	{ .name = "pxa910-usb-phy",	.driver_data = PXA910_USB },
+	{ .name = "mmp2-usb-phy",	.driver_data = MMP2_USB },
+	{}
+};
+
+static struct platform_driver mv_usb2_phy_driver = {
+	.probe	= mv_usb2_phy_probe,
+	.remove = mv_usb2_phy_remove,
+	.driver = {
+		.name   = "pxa168-usb-phy",
+	},
+	.id_table = mv_usb2_phy_ids,
+};
+
+module_platform_driver(mv_usb2_phy_driver);
+MODULE_ALIAS("platform: mv_usb2");
+MODULE_AUTHOR("Marvell Inc.");
+MODULE_DESCRIPTION("Marvell USB2 phy driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/usb/mv_usb2.h b/include/linux/usb/mv_usb2.h
new file mode 100644
index 0000000..dfabd4e
--- /dev/null
+++ b/include/linux/usb/mv_usb2.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Marvell Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MV_USB2_H
+#define __MV_USB2_H
+
+#define MV_USB2_PHY_INDEX	0
+#define MV_USB2_OTG_PHY_INDEX	1
+
+struct mv_usb2_phy {
+	struct usb_phy		phy;
+	struct platform_device	*pdev;
+	unsigned int		type;
+	void __iomem		*base;
+	struct clk		*clk;
+};
+
+#endif
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:31 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:31 -0400
Subject: [V9 PATCH 00/12] mv-usb phy driver
Message-ID: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>

The patches create the mv-usb phy driver

The patches remove the callbacks in the platform data for phy
initialization and shutdown, and directly write a phy driver
and make udc/ehci/otg to call it.

  usb: phy: protect phy init and shutdown for mutiple deivces
  usb: phy: mv_usb2: add PHY driver for marvell usb2 controller
Above patches are marvell usb PHY driver support.

  usb: gadget: mv_udc: use PHY driver for udc
  usb: ehci: ehci-mv: use PHY driver for ehci
  usb: phy: phy-mv-usb: use USB2 PHY driver for otg
Above patches modify the udc/ehci/otg drivers to make use of PHY
driver.

  usb: mv_u3d: usb phy drivers for phy operation
Above patch is the fix for marvel usb3 gadget driver. It will make
use of PHY driver.

  arm: mmp2: change the defintion of usb devices
  arm: pxa910: change the defintion of usb devices
  arm: ttc_dkb: modify usb support
  arm: mmp: remove unused usb devices
  arm: brownstone: add usb support for the board
Above patches are the changes from SOCes.

  usb: mv_usb: remove the phy callbacks in pdata
Above patch finally remove the callbacks for PHY in pdata.

V2->V1:
  Change the Signed-off-by to be right email address

v3->v2
  re-format the patches to new code base

v4->v3
  1. make mv udc gadget driver depend on ARCH_PXA and ARCH_MMP
  2. remove __devinit and __devexit
  3. make the driver compiled successful if CONFIG_MV_USB2_PHY is not defined.
  The modified patches are
  usb: gadget: mv_udc: make mv_udc depends on ARCH_MMP or ARCH_PXA
  usb: phy: mv_usb2: add PHY driver for marvell usb2 controller

v5->v4
  make the struct mv_usb2_extern_chip member ->head to be
  struct atomic_notifier_head instead of struct atomic_notifier_head *.

v6->v5
  the bug fix patches are merged.
  Removed the dependcy of ARCH_MMP and ARCH_PXA, and make the driver can be
  compiled for x86.
  The device tree support patches need modification, remove them from this
  patch series, and they will be submitted in another series.


v7->v6
  Use usb_add_phy_dev and related APIs to add PHY drivers.
  Removed the device tree support in PHY driver. It will be added in another
  patch series.

v8->v7
  bugs fix in phy driver.
  directly use devm_usb_get_phy_dev return value for error return.

v9->v8
  Remove u2o_xxx.
  Add prefix for register definition
  Move mutex to common PHY layer
  Use module_platform_driver() to register driver
  Use usleep_range to replace udelay

V10->V9
  Grammar fix in comments.

Chao Xie (12):
  usb: phy: protect phy init and shutdown for mutiple deivces
  usb: phy: mv_usb2: add PHY driver for marvell usb2 controller
  usb: gadget: mv_udc: use PHY driver for udc
  usb: ehci: ehci-mv: use PHY driver for ehci
  usb: phy: phy-mv-usb: use USB2 PHY driver for otg
  usb: mv_u3d: usb phy drivers for phy operation
  arm: mmp2: change the defintion of usb devices
  arm: pxa910: change the defintion of usb devices
  arm: ttc_dkb: modify usb support
  arm: mmp: remove unused usb devices
  arm: brownstone: add usb support for the board
  usb: mv_usb: remove the phy callbacks in pdata

 arch/arm/mach-mmp/brownstone.c          |   56 +++++
 arch/arm/mach-mmp/include/mach/mmp2.h   |    4 +
 arch/arm/mach-mmp/include/mach/pxa910.h |    7 +-
 arch/arm/mach-mmp/mmp2.c                |    4 +
 arch/arm/mach-mmp/pxa910.c              |    4 +
 arch/arm/mach-mmp/ttc_dkb.c             |   39 +++-
 drivers/usb/gadget/mv_u3d.h             |    3 +-
 drivers/usb/gadget/mv_u3d_core.c        |   54 ++---
 drivers/usb/gadget/mv_udc.h             |    2 +-
 drivers/usb/gadget/mv_udc_core.c        |   50 ++---
 drivers/usb/host/ehci-mv.c              |   49 ++---
 drivers/usb/phy/Kconfig                 |    6 +
 drivers/usb/phy/Makefile                |    1 +
 drivers/usb/phy/phy-mv-usb.c            |   53 ++---
 drivers/usb/phy/phy-mv-usb.h            |    2 +-
 drivers/usb/phy/phy-mv-usb2.c           |  380 +++++++++++++++++++++++++++++++
 drivers/usb/phy/phy.c                   |    6 +
 include/linux/platform_data/mv_usb.h    |    3 -
 include/linux/usb/mv_usb2.h             |   29 +++
 include/linux/usb/phy.h                 |   22 ++-
 20 files changed, 624 insertions(+), 150 deletions(-)
 create mode 100644 drivers/usb/phy/phy-mv-usb2.c
 create mode 100644 include/linux/usb/mv_usb2.h

-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:36 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:36 -0400
Subject: [PATCh V10 05/12] usb: phy: phy-mv-usb: use USB2 PHY driver for otg
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-6-git-send-email-chao.xie@marvell.com>

Originaly, otg driver will call the callbacks in platform data
for PHY initialization and shut down.
With PHY driver, it will call the APIs provided by PHY driver
for PHY initialization and shutdown. It removes the callbacks
in platform data, and at same time it removes one block in the
way of enabling device tree for otg driver.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/usb/phy/phy-mv-usb.c |   53 ++++++++++++++++++-----------------------
 drivers/usb/phy/phy-mv-usb.h |    2 +-
 2 files changed, 24 insertions(+), 31 deletions(-)

diff --git a/drivers/usb/phy/phy-mv-usb.c b/drivers/usb/phy/phy-mv-usb.c
index c987bbe..9938904 100644
--- a/drivers/usb/phy/phy-mv-usb.c
+++ b/drivers/usb/phy/phy-mv-usb.c
@@ -25,6 +25,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/hcd.h>
+#include <linux/usb/mv_usb2.h>
 #include <linux/platform_data/mv_usb.h>
 
 #include "phy-mv-usb.h"
@@ -255,15 +256,14 @@ static int mv_otg_enable_internal(struct mv_otg *mvotg)
 	dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
 
 	otg_clock_enable(mvotg);
-	if (mvotg->pdata->phy_init) {
-		retval = mvotg->pdata->phy_init(mvotg->phy_regs);
-		if (retval) {
-			dev_err(&mvotg->pdev->dev,
-				"init phy error %d\n", retval);
-			otg_clock_disable(mvotg);
-			return retval;
-		}
+	retval = usb_phy_init(mvotg->outer_phy);
+	if (retval) {
+		dev_err(&mvotg->pdev->dev,
+			"failed to initialize phy %d\n", retval);
+		otg_clock_disable(mvotg);
+		return retval;
 	}
+
 	mvotg->active = 1;
 
 	return 0;
@@ -282,8 +282,7 @@ static void mv_otg_disable_internal(struct mv_otg *mvotg)
 {
 	if (mvotg->active) {
 		dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
-		if (mvotg->pdata->phy_deinit)
-			mvotg->pdata->phy_deinit(mvotg->phy_regs);
+		usb_phy_shutdown(mvotg->outer_phy);
 		otg_clock_disable(mvotg);
 		mvotg->active = 0;
 	}
@@ -715,6 +714,7 @@ static int mv_otg_probe(struct platform_device *pdev)
 	/* OTG common part */
 	mvotg->pdev = pdev;
 	mvotg->phy.dev = &pdev->dev;
+	mvotg->phy.type = USB_PHY_TYPE_USB2;
 	mvotg->phy.otg = otg;
 	mvotg->phy.label = driver_name;
 	mvotg->phy.state = OTG_STATE_UNDEFINED;
@@ -727,23 +727,8 @@ static int mv_otg_probe(struct platform_device *pdev)
 	for (i = 0; i < OTG_TIMER_NUM; i++)
 		init_timer(&mvotg->otg_ctrl.timer[i]);
 
-	r = platform_get_resource_byname(mvotg->pdev,
-					 IORESOURCE_MEM, "phyregs");
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
-		retval = -ENODEV;
-		goto err_destroy_workqueue;
-	}
-
-	mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-	if (mvotg->phy_regs == NULL) {
-		dev_err(&pdev->dev, "failed to map phy I/O memory\n");
-		retval = -EFAULT;
-		goto err_destroy_workqueue;
-	}
-
-	r = platform_get_resource_byname(mvotg->pdev,
-					 IORESOURCE_MEM, "capregs");
+	r = platform_get_resource(mvotg->pdev,
+					 IORESOURCE_MEM, 0);
 	if (r == NULL) {
 		dev_err(&pdev->dev, "no I/O memory resource defined\n");
 		retval = -ENODEV;
@@ -757,6 +742,14 @@ static int mv_otg_probe(struct platform_device *pdev)
 		goto err_destroy_workqueue;
 	}
 
+	mvotg->outer_phy = devm_usb_get_phy_dev(&pdev->dev, MV_USB2_PHY_INDEX);
+	if (IS_ERR_OR_NULL(mvotg->outer_phy)) {
+		retval = PTR_ERR(mvotg->outer_phy);
+		if (retval != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "can not find outer phy\n");
+		goto err_destroy_workqueue;
+	}
+
 	/* we will acces controller register, so enable the udc controller */
 	retval = mv_otg_enable_internal(mvotg);
 	if (retval) {
@@ -816,7 +809,7 @@ static int mv_otg_probe(struct platform_device *pdev)
 		goto err_disable_clk;
 	}
 
-	retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
+	retval = usb_add_phy_dev(&mvotg->phy);
 	if (retval < 0) {
 		dev_err(&pdev->dev, "can't register transceiver, %d\n",
 			retval);
@@ -827,7 +820,7 @@ static int mv_otg_probe(struct platform_device *pdev)
 	if (retval < 0) {
 		dev_dbg(&pdev->dev,
 			"Can't register sysfs attr group: %d\n", retval);
-		goto err_remove_phy;
+		goto err_remove_otg_phy;
 	}
 
 	spin_lock_init(&mvotg->wq_lock);
@@ -842,7 +835,7 @@ static int mv_otg_probe(struct platform_device *pdev)
 
 	return 0;
 
-err_remove_phy:
+err_remove_otg_phy:
 	usb_remove_phy(&mvotg->phy);
 err_disable_clk:
 	mv_otg_disable_internal(mvotg);
diff --git a/drivers/usb/phy/phy-mv-usb.h b/drivers/usb/phy/phy-mv-usb.h
index 551da6e..6df6219 100644
--- a/drivers/usb/phy/phy-mv-usb.h
+++ b/drivers/usb/phy/phy-mv-usb.h
@@ -137,10 +137,10 @@ struct mv_otg_regs {
 
 struct mv_otg {
 	struct usb_phy phy;
+	struct usb_phy *outer_phy;
 	struct mv_otg_ctrl otg_ctrl;
 
 	/* base address */
-	void __iomem *phy_regs;
 	void __iomem *cap_regs;
 	struct mv_otg_regs __iomem *op_regs;
 
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:37 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:37 -0400
Subject: [PATCh V10 06/12] usb: mv_u3d: usb phy drivers for phy operation
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-7-git-send-email-chao.xie@marvell.com>

The phy_init and phy_deinit APIs are removed from the pdata.
Directly get the phy driver and invoke the callbacks of phy
drivers for phy initialization and shutdown.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/usb/gadget/mv_u3d.h      |    3 +-
 drivers/usb/gadget/mv_u3d_core.c |   54 ++++++++++++++-----------------------
 2 files changed, 23 insertions(+), 34 deletions(-)

diff --git a/drivers/usb/gadget/mv_u3d.h b/drivers/usb/gadget/mv_u3d.h
index e32a787..0a0c7e3 100644
--- a/drivers/usb/gadget/mv_u3d.h
+++ b/drivers/usb/gadget/mv_u3d.h
@@ -251,7 +251,6 @@ struct mv_u3d {
 	struct mv_u3d_cap_regs __iomem	*cap_regs;
 	struct mv_u3d_op_regs __iomem	*op_regs;
 	struct mv_u3d_vuc_regs __iomem	*vuc_regs;
-	void __iomem			*phy_regs;
 
 	unsigned int			max_eps;
 	struct mv_u3d_ep_context	*ep_context;
@@ -283,6 +282,8 @@ struct mv_u3d {
 	struct mv_usb_addon_irq *vbus;
 	unsigned int		power;
 
+	struct usb_phy		*phy;
+
 	struct clk		*clk;
 };
 
diff --git a/drivers/usb/gadget/mv_u3d_core.c b/drivers/usb/gadget/mv_u3d_core.c
index 58288e9..bb92c5b 100644
--- a/drivers/usb/gadget/mv_u3d_core.c
+++ b/drivers/usb/gadget/mv_u3d_core.c
@@ -24,6 +24,7 @@
 #include <linux/device.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/phy.h>
 #include <linux/pm.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -1109,7 +1110,6 @@ static int mv_u3d_controller_reset(struct mv_u3d *u3d)
 
 static int mv_u3d_enable(struct mv_u3d *u3d)
 {
-	struct mv_usb_platform_data *pdata = u3d->dev->platform_data;
 	int retval;
 
 	if (u3d->active)
@@ -1122,14 +1122,12 @@ static int mv_u3d_enable(struct mv_u3d *u3d)
 
 	dev_dbg(u3d->dev, "enable u3d\n");
 	clk_enable(u3d->clk);
-	if (pdata->phy_init) {
-		retval = pdata->phy_init(u3d->phy_regs);
-		if (retval) {
-			dev_err(u3d->dev,
-				"init phy error %d\n", retval);
-			clk_disable(u3d->clk);
-			return retval;
-		}
+	retval = usb_phy_init(u3d->phy);
+	if (retval) {
+		dev_err(u3d->dev,
+			"init phy error %d\n", retval);
+		clk_disable(u3d->clk);
+		return retval;
 	}
 	u3d->active = 1;
 
@@ -1138,11 +1136,9 @@ static int mv_u3d_enable(struct mv_u3d *u3d)
 
 static void mv_u3d_disable(struct mv_u3d *u3d)
 {
-	struct mv_usb_platform_data *pdata = u3d->dev->platform_data;
 	if (u3d->clock_gating && u3d->active) {
 		dev_dbg(u3d->dev, "disable u3d\n");
-		if (pdata->phy_deinit)
-			pdata->phy_deinit(u3d->phy_regs);
+		usb_phy_shutdown(u3d->phy);
 		clk_disable(u3d->clk);
 		u3d->active = 0;
 	}
@@ -1246,7 +1242,6 @@ static int mv_u3d_start(struct usb_gadget *g,
 		struct usb_gadget_driver *driver)
 {
 	struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
-	struct mv_usb_platform_data *pdata = u3d->dev->platform_data;
 	unsigned long flags;
 
 	if (u3d->driver)
@@ -1256,8 +1251,7 @@ static int mv_u3d_start(struct usb_gadget *g,
 
 	if (!u3d->clock_gating) {
 		clk_enable(u3d->clk);
-		if (pdata->phy_init)
-			pdata->phy_init(u3d->phy_regs);
+		usb_phy_init(u3d->phy);
 	}
 
 	/* hook up the driver ... */
@@ -1277,7 +1271,6 @@ static int mv_u3d_stop(struct usb_gadget *g,
 		struct usb_gadget_driver *driver)
 {
 	struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
-	struct mv_usb_platform_data *pdata = u3d->dev->platform_data;
 	unsigned long flags;
 
 	u3d->vbus_valid_detect = 0;
@@ -1285,8 +1278,7 @@ static int mv_u3d_stop(struct usb_gadget *g,
 
 	/* enable clock to access controller register */
 	clk_enable(u3d->clk);
-	if (pdata->phy_init)
-		pdata->phy_init(u3d->phy_regs);
+	usb_phy_init(u3d->phy);
 
 	mv_u3d_controller_stop(u3d);
 	/* stop all usb activities */
@@ -1294,8 +1286,7 @@ static int mv_u3d_stop(struct usb_gadget *g,
 	mv_u3d_stop_activity(u3d, driver);
 	mv_u3d_disable(u3d);
 
-	if (pdata->phy_deinit)
-		pdata->phy_deinit(u3d->phy_regs);
+	usb_phy_shutdown(u3d->phy);
 	clk_disable(u3d->clk);
 
 	spin_unlock_irqrestore(&u3d->lock, flags);
@@ -1827,7 +1818,7 @@ static int mv_u3d_probe(struct platform_device *dev)
 		goto err_get_clk;
 	}
 
-	r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
+	r = platform_get_resource_byname(dev, IORESOURCE_MEM, 0);
 	if (!r) {
 		dev_err(&dev->dev, "no I/O memory resource defined\n");
 		retval = -ENODEV;
@@ -1846,15 +1837,14 @@ static int mv_u3d_probe(struct platform_device *dev)
 			(unsigned long) u3d->cap_regs);
 	}
 
-	/* we will access controller register, so enable the u3d controller */
-	clk_enable(u3d->clk);
+	u3d->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB3);
+	if (IS_ERR_OR_NULL(u3d->phy))
+		goto err_u3d_enable;
 
-	if (pdata->phy_init) {
-		retval = pdata->phy_init(u3d->phy_regs);
-		if (retval) {
-			dev_err(&dev->dev, "init phy error %d\n", retval);
-			goto err_u3d_enable;
-		}
+	retval = usb_phy_init(u3d->phy);
+	if (retval) {
+		dev_err(&dev->dev, "init phy error %d\n", retval);
+		goto err_u3d_enable;
 	}
 
 	u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
@@ -1872,8 +1862,7 @@ static int mv_u3d_probe(struct platform_device *dev)
 	mv_u3d_controller_stop(u3d);
 	iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
 
-	if (pdata->phy_deinit)
-		pdata->phy_deinit(u3d->phy_regs);
+	usb_phy_shutdown(u3d->phy);
 	clk_disable(u3d->clk);
 
 	size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
@@ -1988,8 +1977,7 @@ err_alloc_trb_pool:
 	dma_free_coherent(&dev->dev, u3d->ep_context_size,
 		u3d->ep_context, u3d->ep_context_dma);
 err_alloc_ep_context:
-	if (pdata->phy_deinit)
-		pdata->phy_deinit(u3d->phy_regs);
+	usb_phy_shutdown(u3d->phy);
 	clk_disable(u3d->clk);
 err_u3d_enable:
 	iounmap(u3d->cap_regs);
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:38 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:38 -0400
Subject: [PATCh V10 07/12] arm: mmp2: change the defintion of usb devices
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-8-git-send-email-chao.xie@marvell.com>

add the udc/otg/ehci devices for mmp2

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/mach-mmp/include/mach/mmp2.h |    4 ++++
 arch/arm/mach-mmp/mmp2.c              |    4 ++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index 0764f4e..95b6bd7 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -29,6 +29,10 @@ extern struct pxa_device_desc mmp2_device_sdh2;
 extern struct pxa_device_desc mmp2_device_sdh3;
 extern struct pxa_device_desc mmp2_device_asram;
 extern struct pxa_device_desc mmp2_device_isram;
+extern struct pxa_device_desc mmp2_device_u2o;
+extern struct pxa_device_desc mmp2_device_u2ootg;
+extern struct pxa_device_desc mmp2_device_u2oehci;
+extern struct pxa_device_desc mmp2_device_u2ophy;
 
 extern struct platform_device mmp2_device_gpio;
 
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index d94d114..e7b7642 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -149,6 +149,10 @@ MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
 MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
 /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
 MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
+MMP2_DEVICE(u2ophy, "mmp2-usb-phy", -1, NONE, 0xd4207000, 0x1ff);
+MMP2_DEVICE(u2o, "mv-udc", -1, USB_OTG, 0xd4208100, 0x1ff);
+MMP2_DEVICE(u2ootg, "mv-otg", -1, USB_OTG, 0xd4208100, 0x1ff);
+MMP2_DEVICE(u2oehci, "mv-ehci", -1, USB_OTG, 0xd4208100, 0x1ff);
 
 struct resource mmp2_resource_gpio[] = {
 	{
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:40 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:40 -0400
Subject: [PATCh V10 09/12] arm: ttc_dkb: modify usb support
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-10-git-send-email-chao.xie@marvell.com>

for ttc_dkb board, we use phy driver for usb support.
Modify the usb support for udc/otg/ehci support.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/mach-mmp/ttc_dkb.c |   39 ++++++++++++++++++++++++++++++---------
 1 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 6528a5f..c8b9ed8 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -18,6 +18,8 @@
 #include <linux/i2c/pca953x.h>
 #include <linux/gpio.h>
 #include <linux/mfd/88pm860x.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/mv_usb2.h>
 #include <linux/platform_data/mv_usb.h>
 #include <linux/spi/spi.h>
 #include <linux/delay.h>
@@ -29,7 +31,6 @@
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
 #include <mach/irqs.h>
-#include <mach/regs-usb.h>
 
 #include "common.h"
 
@@ -166,8 +167,6 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
 	.vbus		= NULL,
 	.mode		= MV_USB_MODE_OTG,
 	.otg_force_a_bus_req = 1,
-	.phy_init	= pxa_usb_phy_init,
-	.phy_deinit	= pxa_usb_phy_deinit,
 	.set_vbus	= NULL,
 };
 #endif
@@ -280,19 +279,41 @@ static void __init ttc_dkb_init(void)
 	pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
 	platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 
+#ifdef CONFIG_USB_SUPPORT
+	pxa_register_device(&pxa910_device_u2ophy, NULL, 0);
+#endif
+
 #ifdef CONFIG_USB_MV_UDC
-	pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
-	platform_device_register(&pxa168_device_u2o);
+	/* for usb2 phy */
+	usb_bind_phy(pxa910_device_u2o.drv_name, MV_USB2_PHY_INDEX,
+		     pxa910_device_u2ophy.drv_name);
+#ifdef CONFIG_USB_MV_OTG
+	/* for usb2 otg phy */
+	usb_bind_phy(pxa910_device_u2o.drv_name, MV_USB2_OTG_PHY_INDEX,
+		     pxa910_device_u2ootg.drv_name);
+#endif
+	pxa_register_device(&pxa910_device_u2o, &ttc_usb_pdata,
+			    sizeof(ttc_usb_pdata));
 #endif
 
 #ifdef CONFIG_USB_EHCI_MV_U2O
-	pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
-	platform_device_register(&pxa168_device_u2oehci);
+	/* for usb2 phy */
+	usb_bind_phy(pxa910_device_u2oehci.drv_name, MV_USB2_PHY_INDEX,
+		     pxa910_device_u2ophy.drv_name);
+#ifdef CONFIG_USB_MV_OTG
+	/* for usb2 otg phy */
+	usb_bind_phy(pxa910_device_u2oehci.drv_name, MV_USB2_OTG_PHY_INDEX,
+		     pxa910_device_u2ootg.drv_name);
+#endif
+	pxa_register_device(&pxa910_device_u2oehci, &ttc_usb_pdata,
+			    sizeof(ttc_usb_pdata));
 #endif
 
 #ifdef CONFIG_USB_MV_OTG
-	pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
-	platform_device_register(&pxa168_device_u2ootg);
+	usb_bind_phy(pxa910_device_u2ootg.drv_name, MV_USB2_PHY_INDEX,
+		     pxa910_device_u2ophy.drv_name);
+	pxa_register_device(&pxa910_device_u2ootg, &ttc_usb_pdata,
+			    sizeof(ttc_usb_pdata));
 #endif
 
 #ifdef CONFIG_MMP_DISP
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:41 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:41 -0400
Subject: [PATCh V10 10/12] arm: mmp: remove unused usb devices
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-11-git-send-email-chao.xie@marvell.com>

We defined new usb devices for usb ehci/udc/otg/phy.
So remove the old definitions.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/mach-mmp/include/mach/pxa910.h |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index c695982..d17ffee 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -19,9 +19,6 @@ extern struct pxa_device_desc pxa910_device_pwm2;
 extern struct pxa_device_desc pxa910_device_pwm3;
 extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
-extern struct platform_device pxa168_device_u2o;
-extern struct platform_device pxa168_device_u2ootg;
-extern struct platform_device pxa168_device_u2oehci;
 extern struct pxa_device_desc pxa910_device_u2o;
 extern struct pxa_device_desc pxa910_device_u2ootg;
 extern struct pxa_device_desc pxa910_device_u2oehci;
-- 
1.7.4.1



From chao.xie at marvell.com  Mon May 13 01:51:43 2013
From: chao.xie at marvell.com (Chao Xie)
Date: Mon, 13 May 2013 01:51:43 -0400
Subject: [PATCh V10 12/12] usb: mv_usb: remove the phy callbacks in pdata
In-Reply-To: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
References: <1368424303-10629-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1368424303-10629-13-git-send-email-chao.xie@marvell.com>

The phy initialization code will be done by phy driver.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 include/linux/platform_data/mv_usb.h |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/include/linux/platform_data/mv_usb.h b/include/linux/platform_data/mv_usb.h
index 98b7925..b4b5d6f 100644
--- a/include/linux/platform_data/mv_usb.h
+++ b/include/linux/platform_data/mv_usb.h
@@ -45,9 +45,6 @@ struct mv_usb_platform_data {
 	/* Force a_bus_req to be asserted */
 	 unsigned int    otg_force_a_bus_req:1;
 
-	int	(*phy_init)(void __iomem *regbase);
-	void	(*phy_deinit)(void __iomem *regbase);
 	int	(*set_vbus)(unsigned int vbus);
-	int     (*private_init)(void __iomem *opregs, void __iomem *phyregs);
 };
 #endif
-- 
1.7.4.1



From viresh.kumar at linaro.org  Mon May 13 02:05:22 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 13 May 2013 11:35:22 +0530
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <5176A807.2090005@samsung.com>
References: <cover.1365079581.git.viresh.kumar@linaro.org>
 <2a5901ce31c9$95160980$bf421c80$%kim@samsung.com>
 <CAKohpokk1Q+0gRpeW=ts0a8D+rGAUpHu62X+7ejdpfom_B6FYA@mail.gmail.com>
 <1769336.FkfMpuXqqb@vostro.rjw.lan> <5176A807.2090005@samsung.com>
Message-ID: <CAKohpomV9-JEbuHWdmp6N+bKYt+83hXXcqg4aKXSY1a5zwpW9Q@mail.gmail.com>

On 23 April 2013 20:55, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 04/05/13 20:36, Rafael J. Wysocki wrote:
>>
>> On Friday, April 05, 2013 12:36:34 PM Viresh Kumar wrote:
>>>
>>> On 5 April 2013 12:18, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>>>>
>>>> Basically, this moving looks good to me, but should be re-worked based
>>>> on
>>>> for-next of samsung tree because this touches too many samsung stuff so
>>>> this
>>>> should be sent to upstream via samsung tree.
>>>
>>>
>>> Hmm... Its already applied in Rafael's tree. But it doesn't mean that
>>> it can't be
>>> moved to your tree if there is a issue.
>>
>>
>> Well, I'm dropping it.  Please merge via the Samsung tree.
>>
>
> Oops, I missed, maybe I have no more chance to send this to upstream for
> upcoming merge window :-(
>
> Rafael, please take this patch with my ack in your tree, sorry for noise.
>
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>
>
> If any problems, please kindly let me know.

Who is going to pick this patch now for next merge window?


From pranavkumar at linaro.org  Mon May 13 02:56:39 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Mon, 13 May 2013 12:26:39 +0530
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <8761yn382w.fsf@rustcorp.com.au>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
 <8761yn382w.fsf@rustcorp.com.au>
Message-ID: <CAAHg+Hi6BHqwOznnC9qxkc5pBWz7r5qpz9Nhh=EeNenhjhHohg@mail.gmail.com>

Hi Rusty,

On 13 May 2013 08:22, Rusty Russell <rusty at rustcorp.com.au> wrote:
> Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>> ---
>>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> OK, I applied this to the lyx master, with three changes:
> 1) Changed "filed" to "field".
> 2) Added ", or even acknowledging the feature" after "without
>    initializing virtio queues".
> 3) Added an initial point to the Device Initialization section:
>
>    1. If the VIRTIO_CONSOLE_F_EMERG_WRITE feature is offered, the
>    emerg_wr field of the configuration can be written at any time. Thus
>    it should work for very early boot debugging output as well as
>    catastophic OS failures (eg. virtio ring corruption).

Thanks for applying this patch.
Have you also applied first patch ([PATCH V2 1/3] virtio: console: Add
emergency writeonly register to config space)
with this?  (https://lkml.org/lkml/2013/5/6/169)

>
> Thanks,
> Rusty.

Thanks,
Pranav

>
>> diff --git a/Documentation/virtual/virtio-spec.txt b/Documentation/virtual/virtio-spec.txt
>> index 0d6ec85..3ca38f8 100644
>> --- a/Documentation/virtual/virtio-spec.txt
>> +++ b/Documentation/virtual/virtio-spec.txt
>> @@ -1927,11 +1927,16 @@ Ports 2 onwards only if VIRTIO_CONSOLE_F_MULTIPORT is set
>>      ports; configuration fields nr_ports and max_nr_ports are
>>      valid and control virtqueues will be used.
>>
>> +  VIRTIO_CONSOLE_F_EMERG_WRITE(2) Device has support for emergency
>> +  write. Configuration filed emerg_wr is valid.
>> +
>>    Device configuration layout The size of the console is supplied
>>    in the configuration space if the VIRTIO_CONSOLE_F_SIZE feature
>>    is set. Furthermore, if the VIRTIO_CONSOLE_F_MULTIPORT feature
>>    is set, the maximum number of ports supported by the device can
>> -  be fetched.struct virtio_console_config {
>> +  be fetched. If VIRTIO_CONSOLE_F_EMERG_WRITE is set then one can
>> +  use emergency write to output single character without initializing
>> +  virtio queues. struct virtio_console_config {
>>
>>       u16 cols;
>>
>> @@ -1941,6 +1946,7 @@ Ports 2 onwards only if VIRTIO_CONSOLE_F_MULTIPORT is set
>>
>>       u32 max_nr_ports;
>>
>> +     u32 emerg_wr;
>>  };
>>
>>    Device Initialization
>> --
>> 1.7.9.5


From monstr at monstr.eu  Mon May 13 03:02:37 2013
From: monstr at monstr.eu (Michal Simek)
Date: Mon, 13 May 2013 09:02:37 +0200
Subject: [RFC] device-tree.git automatic sync from linux.git
In-Reply-To: <1366800525.20256.266.camel@zakaz.uk.xensource.com>
References: <1366800525.20256.266.camel@zakaz.uk.xensource.com>
Message-ID: <5190900D.5020408@monstr.eu>

Hi Ian,


On 04/24/2013 12:48 PM, Ian Campbell wrote:
> Hi,
> 
> First off apologies for the large CC list -- I think this catches the
> arch list for all the arches with device tree source in the tree.
> 
> Various folks have expressed an interest in eventually splitting the
> device tree bindings out of the Linux git repository into a separate
> tree. This should help reduce the cross talk between the code and the
> bindings and to make it difficult to accidentally "co-evolve" the
> bindings and the code (i.e. break compatibility) etc. There are also
> other projects (such as Xen) which would also like to use device-tree as
> an OS agnostic description of the hardware.
> 
> I was talking to Grant about this at this Spring's LinaroConnect in Hong
> Kong and as a first step he was interested in a device-tree.git
> repository which is automatically kept insync with the main Linux tree.
> Somehow I found myself volunteering to set up that tree.
> 
> An RFC repository can be found at:
>         http://xenbits.xen.org/gitweb/?p=people/ianc/device-tree-rebasing.git
> 
> This is created using git filter-branch and retains the full history for
> the device tree source files up to v3.9-rc8.
> 
> The master branch contains everything including the required build
> infrastructure while upstream/master and upstream/dts contain the most
> recently converted upstream master branch and the pristine converted
> version respectively. Each upstream tag T is paired with a tag T-dts
> which is the converted version of that tag.
> 
> Note that the tree will be potentially rebasing (hence the name) for the
> time being while I'm still smoothing out the conversion process.
> 
> The paths to include in the conversion are described in
> scripts/rewrite-paths.sed. The generic cases are:
>         arch/ARCH/boot/dts/*.dts and *.dts? (for dtsi and dtsp etc)
> 	arch/ARCH/boot/*.dts and *.dts?
>         arch/ARCH/include/dts/* (currently unused?)
> which become src/ARCH/*.dts and *.dts? plus src/ARCH/include/*
> 
> There are also some special cases for some arches which don't follow
> this pattern and for older versions of the kernel which were less
> consistent. The paths were gleaned from git ls-tree + grep on every tag
> in the tree, so if a file was added and moved between two rcs then the
> original path may not be covered (so the move will look like it just
> adds the files).
> 
> In principal this supports the new .dtsp files and includes the required
> include paths in the conversion but none of them seem to be in mainline
> yet, so we'll have to see!
> 
> The initial conversion took in excess of 40 hours (running out of a
> ramdisk) so even if the result is stable in terms of commit ids etc a
> fresh conversion every time isn't an option for a ~daily sync so I had
> to create a slightly hacked around git-filter-branch (found in
> scripts/git-filter-branch) to support incremental filtering, which I
> intend to send to the git folks soon. 
> 
> Please let me know what you think.

I have seen that discussion on youtube about this and connection
to arm dtses in the kernel.

Let me describe Microblaze case because probably Microblaze was the first
architecture in the Linux kernel which was DT only from the beginning.

Just small overview it is a Xilinx soft core cpu where you can even setup
some parameters for core itself - multiplier, divider, BS, fpu, cache sizes, etc.
You have to also compose the whole system and every platform/configuration is different
because you can setup addresses, IP on the bus, IRQs, etc.
Based on this configuration we have created tcl script which is able to generate
DTS directly from Xilinx design tool and it is working quite well for several years
and everybody just use it without any problem.

As you see in your repo there is only one microblaze DTS which is for one of mine
ancient configuration which none used.
It means from microblaze point of view we can simple remove it from mainline kernel
because it is useless.

I also care about arm zynq platform where situation is partially different because
zynq is fixed block but you can add others thing to programmable logic.
It means for zynq case we are almost in the same situation where every zynq based
platform is using different configuration and that's why fpgas are so great.

It means for zynq case everybody will need different DTS but will be just good
to describe or show binding.
Currently we have just one dts for zc702 xilinx reference board.

Let's move to my point.
Based on our experience all xilinx boards don't depend on any dts in the linux kernel
and our users just understand the reason why they should use our tcl script for
DTS generation.

Back to your point about moving DTSes out of the kernel. For microblaze - no problem
just do it. For arm zynq this is more problematic because there is weird binding
for ARM. For example PMU which is out of bus and should be probably in cpu node.
Also scu devices, scutimers, watchdog which lie on the bus for our case and we
need to use PPI interrupt cpu mask. Different clock binding, maybe pinmux binding, etc.

It means from my point of view if binding is correct, no problem to move it
out of the kernel. If a kernel patch change binding, it is worth for me to change
dts in the kernel too to reflect this change and track this change too.
My proposal is, let's clean all DTSes in the arm kernel that all platform use
the same binding where all platforms are just correctly described.

The reaching this point I would suggest that for arm, arm-soc maintainers should
keep eyes on any dts binding change and all these changes require ACK from Rob or Grant
(like device-tree maintainers).

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From dedekind1 at gmail.com  Mon May 13 03:15:08 2013
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 13 May 2013 10:15:08 +0300
Subject: [PATCH] mtd: devices: added the 16mb winbond device
In-Reply-To: <516d0c68.e10b420a.287d.ffff894c@mx.google.com>
References: <516d0c68.e10b420a.287d.ffff894c@mx.google.com>
Message-ID: <1368429308.5360.6.camel@sauron.fi.intel.com>

On Tue, 2013-04-16 at 14:01 +0530, girishks2000 at gmail.com wrote:
> From: Girish K S <ks.giri at samsung.com>
> 
> added a 16mb winbond devce to the device list
> erase size = 64k and number of blocks = 256
> 
> Signed-off-by: Girish K S <ks.giri at samsung.com>

Pushed to l2-mtd.git, but please, remember to use better suffixes. E.g.,
mb may mean mega bytes, or mega bits. 16MiB device, 64KiB block size is
a lot less ambiguous way communicate the sizes.

I've amended your commit message.

-- 
Best Regards,
Artem Bityutskiy



From maarten.lankhorst at canonical.com  Mon May 13 04:00:52 2013
From: maarten.lankhorst at canonical.com (Maarten Lankhorst)
Date: Mon, 13 May 2013 10:00:52 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
Message-ID: <51909DB4.2060208@canonical.com>

Op 09-05-13 09:33, Inki Dae schreef:
> Hi all,
>
> This post introduces a new helper framework based on dma fence. And the
> purpose of this post is to collect other opinions and advices before RFC
> posting.
>
> First of all, this helper framework, called fence helper, is in progress
> yet so might not have enough comments in codes and also might need to be
> more cleaned up. Moreover, we might be missing some parts of the dma fence.
> However, I'd like to say that all things mentioned below has been tested
> with Linux platform and worked well.

> ....
>
> And tutorial for user process.
>         just before cpu access
>                 struct dma_buf_fence *df;
>
>                 df->type = DMA_BUF_ACCESS_READ or DMA_BUF_ACCESS_WRITE;
>                 ioctl(fd, DMA_BUF_GET_FENCE, &df);
>
>         after memset or memcpy
>                 ioctl(fd, DMA_BUF_PUT_FENCE, &df);
NAK.

Userspace doesn't need to trigger fences. It can do a buffer idle wait, and postpone submitting new commands until after it's done using the buffer.
Kernel space doesn't need the root hole you created by giving a dereferencing a pointer passed from userspace.
Your next exercise should be to write a security exploit from the api you created here. It's the only way to learn how to write safe code. Hint: df.ctx = mmap(..);

~Maarten


From linux at prisktech.co.nz  Mon May 13 04:20:58 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 20:20:58 +1200
Subject: [PATCH 0/2] clk: vt8500: updates for 3.11
Message-ID: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>

Hi Mike,

Two updates for the arch-vt8500 clock code:

#1: Add support for the WM8850 PLL.
#2: Remove a second divisor check in vt8500_dclk_set_rate() which causes the
divisor to be round-down too low.

Regards
Tony Prisk

Tony Prisk (2):
  clk: vt8500: Add support for clocks on the WM8850 SoCs
  clk: vt8500: Remove unnecessary divisor adjustment in
    vtwm_dclk_set_rate()

 Documentation/devicetree/bindings/clock/vt8500.txt |    2 +
 drivers/clk/clk-vt8500.c                           |   75 ++++++++++++++++++--
 2 files changed, 73 insertions(+), 4 deletions(-)

-- 
1.7.9.5



From linux at prisktech.co.nz  Mon May 13 04:21:00 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 20:21:00 +1200
Subject: [PATCH 2/2] clk: vt8500: Remove unnecessary divisor adjustment in
 vtwm_dclk_set_rate()
In-Reply-To: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>
References: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368433260-16073-3-git-send-email-linux@prisktech.co.nz>

The divisor adjustment code to ensure that a divisor is not rounded down,
thereby giving a rate higher than requested, is unnecessary and in some
instances results in the actual rate being much lower than requested due to
rounding errors.

The test is already performed in vtwm_dclk_round_rate(), which is always
called when clk_set_rate is called. Due to rounding errors in the line:
divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up
adjusting the divisor twice - first in round_rate and then again in set_rate.

This patch removes the test/adjustment in vtwm_dclk_set_rate.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/clk/clk-vt8500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 6d5b6e9..d8fd085 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -157,10 +157,6 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	divisor =  parent_rate / rate;
 
-	/* If prate / rate would be decimal, incr the divisor */
-	if (rate * divisor < parent_rate)
-		divisor++;
-
 	if (divisor == cdev->div_mask + 1)
 		divisor = 0;
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Mon May 13 04:20:59 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Mon, 13 May 2013 20:20:59 +1200
Subject: [PATCH 1/2] clk: vt8500: Add support for clocks on the WM8850 SoCs
In-Reply-To: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>
References: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368433260-16073-2-git-send-email-linux@prisktech.co.nz>

The WM8850 has a different PLL clock to the previous versions. This
patch adds support for the WM8850-style PLL clocks.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 Documentation/devicetree/bindings/clock/vt8500.txt |    2 +
 drivers/clk/clk-vt8500.c                           |   71 ++++++++++++++++++++
 2 files changed, 73 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
index a880c70..91d71cc 100644
--- a/Documentation/devicetree/bindings/clock/vt8500.txt
+++ b/Documentation/devicetree/bindings/clock/vt8500.txt
@@ -8,6 +8,8 @@ Required properties:
 - compatible : shall be one of the following:
 	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
 	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
+	"wm,wm8750-pll-clock" - for a WM8750 PLL clock
+	"wm,wm8850-pll-clock" - for a WM8850 PLL clock
 	"via,vt8500-device-clock" - for a VT/WM device clock
 
 Required properties for PLL clocks:
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index debf688..6d5b6e9 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -42,6 +42,7 @@ struct clk_device {
 #define PLL_TYPE_VT8500		0
 #define PLL_TYPE_WM8650		1
 #define PLL_TYPE_WM8750		2
+#define PLL_TYPE_WM8850		3
 
 struct clk_pll {
 	struct clk_hw	hw;
@@ -327,6 +328,15 @@ CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
 #define WM8750_BITS_TO_VAL(f, m, d1, d2)				\
 		((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
 
+/* Helper macros for PLL_WM8850 */
+#define WM8850_PLL_MUL(x)	((((x >> 16) & 0x7F) + 1) * 2)
+#define WM8850_PLL_DIV(x)	((((x >> 8) & 1) + 1) * (1 << (x & 3)))
+
+#define WM8850_BITS_TO_FREQ(r, m, d1, d2)				\
+				(r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
+
+#define WM8850_BITS_TO_VAL(m, d1, d2)					\
+		((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
 
 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 				u32 *multiplier, u32 *prediv)
@@ -466,6 +476,49 @@ static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	*divisor2 = best_div2;
 }
 
+static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+				u32 *multiplier, u32 *divisor1, u32 *divisor2)
+{
+	u32 mul, div1, div2;
+	u32 best_mul, best_div1, best_div2;
+	unsigned long tclk, rate_err, best_err;
+
+	best_err = (unsigned long)-1;
+
+	/* Find the closest match (lower or equal to requested) */
+	for (div1 = 1; div1 >= 0; div1--)
+		for (div2 = 3; div2 >= 0; div2--)
+			for (mul = 0; mul <= 127; mul++) {
+				tclk = parent_rate * ((mul + 1) * 2) /
+						((div1 + 1) * (1 << div2));
+				if (tclk > rate)
+					continue;
+				/* error will always be +ve */
+				rate_err = rate - tclk;
+				if (rate_err == 0) {
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
+					return;
+				}
+
+				if (rate_err < best_err) {
+					best_err = rate_err;
+					best_mul = mul;
+					best_div1 = div1;
+					best_div2 = div2;
+				}
+			}
+
+	/* if we got here, it wasn't an exact match */
+	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
+							rate - best_err);
+
+	*multiplier = best_mul;
+	*divisor1 = best_div1;
+	*divisor2 = best_div2;
+}
+
 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 				unsigned long parent_rate)
 {
@@ -489,6 +542,10 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 		wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
 		pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
 		break;
+	case PLL_TYPE_WM8850:
+		wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
+		pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
+		break;
 	default:
 		pr_err("%s: invalid pll type\n", __func__);
 		return 0;
@@ -525,6 +582,10 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 		wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
 		round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
 		break;
+	case PLL_TYPE_WM8850:
+		wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
+		round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
+		break;
 	default:
 		round_rate = 0;
 	}
@@ -552,6 +613,10 @@ static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
 		pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
 		pll_freq /= WM8750_PLL_DIV(pll_val);
 		break;
+	case PLL_TYPE_WM8850:
+		pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
+		pll_freq /= WM8850_PLL_DIV(pll_val);
+		break;
 	default:
 		pll_freq = 0;
 	}
@@ -628,6 +693,12 @@ static void __init wm8750_pll_init(struct device_node *node)
 }
 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
 
+static void __init wm8850_pll_init(struct device_node *node)
+{
+	vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
+}
+CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
+
 void __init vtwm_clk_init(void __iomem *base)
 {
 	if (!base)
-- 
1.7.9.5



From s.hauer at pengutronix.de  Mon May 13 04:25:35 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 May 2013 10:25:35 +0200
Subject: [PATCH 2/3] ARM: imx: move clk_prepare() out from mxs_restart()
In-Reply-To: <1368408728-12264-3-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
 <1368408728-12264-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130513082535.GM32299@pengutronix.de>

Hi Shawn,

In the subject:

s/mxs_restart/mxc_restart/

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon May 13 04:27:08 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 May 2013 10:27:08 +0200
Subject: [PATCH 3/3] ARM: imx: create imx_arch_reset_init() for DT boot
In-Reply-To: <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
 <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130513082708.GN32299@pengutronix.de>

On Mon, May 13, 2013 at 09:32:08AM +0800, Shawn Guo wrote:
> The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to
> get clock.  It's suitable for non-DT boot but not for DT boot where
> dynamic mapping and of_clk_get() should be used instead.  Create
> imx_arch_reset_init() as the DT variant of mxc_arch_reset_init(),
> and change DT platforms to use it.

Having mxc_arch_reset_init for !dt and the same functionality for dt
named imx_arch_reset_init is a bit confusing. Maybe add _dt_ to the
function name?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From pdeschrijver at nvidia.com  Mon May 13 04:31:03 2013
From: pdeschrijver at nvidia.com (Peter De Schrijver)
Date: Mon, 13 May 2013 11:31:03 +0300
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
Message-ID: <20130513083103.GC7949@tbergstrom-lnx.Nvidia.com>


> >>>
> >>> For debugging purposes, being able to change parents would be nice too.
> >> This is difficult and I don't have a good solution for it, hence it's
> >> missing. A clock consumer like a device driver or this driver, just
> >> knows about it's input clock, but not about the topology further up.
> >> Therefore it is pretty much impossible to implement reparent operations
> >> in a clock consumer, IMHO.
> >> IOW: For a given input clock, how do you figure out it's possible
> >> parents?
> >
> > The parent is just a number
> >
> > int (*set_parent)(struct clk_hw *hw, u8 index);
> > u8 (*get_parent)(struct clk_hw *hw);
> >
> > If you are debugging, you know what the possible parents are, and you
> > can reparent with that information.
> >
> > After checking the clk code however, I didn't find any exposed way to
> > reparent with just the parent indexes. Maybe an interface that takes a n
> > arbitrary string representing the parent name, and gets that clock and
> > then sets the parent would fit.
> >
> >>
> >>> Maybe this belongs to debugfs instead of sysfs though.
> >> Well, the more generic use-case probably. My Zynq use-case rather not,
> >> IMHO.
> >
> > The framework already exposes some information on debugfs, maybe
> > expanding that instead of implementing it as a consumer on sysfs would
> > be best for the debugging use case. @Mike, what's your thoughts on this?
> >
> 
> In the previous thread on this topic we discussed a generic approach
> to exposing clock controls via debugfs.
> 
> One way to do it is to introduce a new config option,
> CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
> every clock in the existing debugfs infrastructure.  The downside to
> this approach is that it would get abused and ship in millions of
> Android products using horrible userspace hacks to control clocks.
> Maybe that's not our problem to solve, maybe it is.
> 

We are doing the same. I don't think we can prevent people from abusing this.
If we don't provide it, they will just implement it themselves :)

> If CONFIG_COMMON_CLK_DEBUG_CONTROL existed it might be a good idea to
> intentionally break the abi compatibility with every new release.
> That would certainly reinforce that this is not a condoned or stable
> api (which is true for all debugfs).
> 

:) I would rather not have to change our automated tests for every new release
though...

Cheers,

Peter.


From maxime.ripard at free-electrons.com  Mon May 13 04:53:08 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 10:53:08 +0200
Subject: [PATCH] ARM: sunxi: select ARCH_REQUIRE_GPIOLIB
Message-ID: <1368435188-26965-1-git-send-email-maxime.ripard@free-electrons.com>

CONFIG_SUNXI currently doesn't enable a gpiolib, which causes build
problems when building a kernel with only the sunxi platform enabled.
Select ARCH_REQUIRE_GPIOLIB to solve this.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index d259c78..5b045e3 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_SUNXI
 	bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+	select ARCH_REQUIRE_GPIOLIB
 	select CLKSRC_MMIO
 	select CLKSRC_OF
 	select COMMON_CLK
-- 
1.8.1.2



From horms+renesas at verge.net.au  Mon May 13 04:53:52 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 17:53:52 +0900
Subject: [PATCH 2/3] ARM: shmobile: r8a7790: Configure R-Car GPIO for
 IRQ_TYPE_EDGE_BOTH
In-Reply-To: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368435233-8587-3-git-send-email-horms+renesas@verge.net.au>

"gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
not universal for all SoCs a flag, has_both_edge_trigger, has been
added to the platform data of the driver to allow this feature to be
enabled.

As the r8a7790 SoC hardware supports this feature enable it.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has a build-time dependency on
"gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH".
---
 arch/arm/mach-shmobile/setup-r8a7790.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index eeef5f6..b461d93 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -45,6 +45,7 @@ static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = {	\
 	.irq_base	= 0,						\
 	.number_of_pins	= 32,						\
 	.pctl_name	= "pfc-r8a7790",				\
+	.has_both_edge_trigger = 1,					\
 };									\
 
 R8A7790_GPIO(0);
-- 
1.8.2.1



From horms+renesas at verge.net.au  Mon May 13 04:53:53 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 17:53:53 +0900
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>

The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
This patch allows access to those pins as KEYS 1 - 4 using
gpio-keys.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has run time dependencies on
1. "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH"
2. "ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH"

Without those dependencies satisfied the gpio-keys driver will
fail to be initialise itself. The boot should be otherwise successful
and the board otherwise functional.
---
 arch/arm/mach-shmobile/board-lager.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 6a1ba38..4d1b42b 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -18,7 +18,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/interrupt.h>
+#include <linux/input.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
@@ -52,6 +55,22 @@ static struct gpio_led_platform_data lager_leds_pdata = {
 	.num_leds	= ARRAY_SIZE(lager_leds),
 };
 
+/* GPIO KEY */
+#define GPIO_KEY(c, g, d, ...) \
+	{ .code = c, .gpio = g, .desc = d, .active_low = 1 }
+
+static struct gpio_keys_button gpio_buttons[] = {
+	GPIO_KEY(KEY_4,		RCAR_GP_PIN(1, 28),	"SW2-pin4"),
+	GPIO_KEY(KEY_3,		RCAR_GP_PIN(1, 26),	"SW2-pin3"),
+	GPIO_KEY(KEY_2,		RCAR_GP_PIN(1, 24),	"SW2-pin2"),
+	GPIO_KEY(KEY_1,		RCAR_GP_PIN(1, 14),	"SW2-pin1"),
+};
+
+static struct gpio_keys_platform_data lager_keys_pdata = {
+	.buttons	= gpio_buttons,
+	.nbuttons	= ARRAY_SIZE(gpio_buttons),
+};
+
 static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
@@ -73,6 +92,9 @@ static void __init lager_add_standard_devices(void)
 	platform_device_register_data(&platform_bus, "leds-gpio", -1,
 				      &lager_leds_pdata,
 				      sizeof(lager_leds_pdata));
+	platform_device_register_data(&platform_bus, "gpio-keys", -1,
+				      &lager_keys_pdata,
+				      sizeof(lager_keys_pdata));
 }
 
 static const char *lager_boards_compat_dt[] __initdata = {
-- 
1.8.2.1



From horms+renesas at verge.net.au  Mon May 13 04:53:50 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 17:53:50 +0900
Subject: [PATCH 0/3] ARM: mach-shmobile: lager: support GPIO switche
Message-ID: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>

This short series adds support for accessing the 4 pins of SW2 as
gpio keys 1 - 4.

As the gpio-keys driver requires IRQ_TYPE_EDGE_BOTH support for this
has been added to the R-Car GPIO driver.

Simon Horman (3):
  gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
  ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH
  ARM: mach-shmobile: lager: support GPIO switches

 arch/arm/mach-shmobile/board-lager.c    | 22 ++++++++++++++++++++++
 arch/arm/mach-shmobile/setup-r8a7790.c  |  1 +
 drivers/gpio/gpio-rcar.c                | 27 ++++++++++++++++++++++-----
 include/linux/platform_data/gpio-rcar.h |  1 +
 4 files changed, 46 insertions(+), 5 deletions(-)

-- 
1.8.2.1



From horms+renesas at verge.net.au  Mon May 13 04:53:51 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 13 May 2013 17:53:51 +0900
Subject: [PATCH 1/3] gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
In-Reply-To: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368435233-8587-2-git-send-email-horms+renesas@verge.net.au>

As hardware support for this feature is not universal for all SoCs a flag,
has_both_edge_trigger, has been added to the platform data of the driver to
allow this feature to be enabled.

The motivation for this is to allow use of the gpio-keys driver on the
lager board which is based on the r8a7790 SoC. This patch has been lightly
exercised using that driver on that board.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 drivers/gpio/gpio-rcar.c                | 27 ++++++++++++++++++++++-----
 include/linux/platform_data/gpio-rcar.h |  1 +
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 0f3d647..33d8f6a 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 						  unsigned int hwirq,
 						  bool active_high_rising_edge,
-						  bool level_trigger)
+						  bool level_trigger,
+						  bool both)
 {
 	unsigned long flags;
 
@@ -111,6 +113,11 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 	/* Select "Interrupt Input Mode" in IOINTSEL */
 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
+	if (p->config.has_both_edge_trigger && !level_trigger) {
+		/* Select one edge or both edges in BOTHEDGE */
+		gpio_rcar_modify_bit(p, IOINTSEL, hwirq, both);
+	}
+
 	/* Write INTCLR in case of edge trigger */
 	if (!level_trigger)
 		gpio_rcar_write(p, INTCLR, BIT(hwirq));
@@ -127,16 +134,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_LEVEL_HIGH:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+						      false);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+						      false);
 		break;
 	case IRQ_TYPE_EDGE_RISING:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+						      false);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+						      false);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		if (!p->config.has_both_edge_trigger)
+			return -EINVAL;
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+						      true);
 		break;
 	default:
 		return -EINVAL;
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index cc472f6..dfea5c6 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -21,6 +21,7 @@ struct gpio_rcar_config {
 	unsigned int irq_base;
 	unsigned int number_of_pins;
 	const char *pctl_name;
+	unsigned has_both_edge_trigger:1;
 };
 
 #define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))
-- 
1.8.2.1



From will.deacon at arm.com  Mon May 13 04:58:03 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 May 2013 09:58:03 +0100
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <20130513051737.GB64337@ubuntu>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
 <20130502150355.GA25022@mudshark.cambridge.arm.com>
 <CAEDV+gJwYpHzehWZci2bmgYedJoBxMOGZFhjGeGRQ_cT8TKkyw@mail.gmail.com>
 <20130502151753.GB25022@mudshark.cambridge.arm.com>
 <20130513051737.GB64337@ubuntu>
Message-ID: <20130513085802.GA24455@mudshark.cambridge.arm.com>

On Mon, May 13, 2013 at 06:17:37AM +0100, Christoffer Dall wrote:
> On Thu, May 02, 2013 at 04:17:53PM +0100, Will Deacon wrote:
> > or just *pte = XX;
> > 
> That won't work with STRICT_M_TYPECHECKS though will it?

Depends if XX is a pte_t or not :)

Will


From marc.zyngier at arm.com  Mon May 13 05:01:57 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 13 May 2013 10:01:57 +0100
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <20130511003842.GE30999@chazy>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com> <5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
 <51892DA4.4050401@arm.com> <20130511003842.GE30999@chazy>
Message-ID: <5190AC05.5000304@arm.com>

On 11/05/13 01:38, Christoffer Dall wrote:
> On Tue, May 07, 2013 at 05:36:52PM +0100, Marc Zyngier wrote:
>> On 24/04/13 18:17, Christoffer Dall wrote:
>>> On Wed, Apr 24, 2013 at 6:49 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>>>> On 24/04/13 00:02, Christoffer Dall wrote:
>>>>> On Mon, Apr 08, 2013 at 05:17:32PM +0100, Marc Zyngier wrote:
>>>>>> Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
>>>>>> and providing sensible defaults out of reset state.
>>>>>>
>>>>>> This feature is of course conditioned by the presence of 32bit
>>>>>> capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
>>>>>> capability.
>>>>>>
>>>>>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
>>>>>> ---
>>>>>>  arch/arm64/include/asm/kvm_host.h |  2 +-
>>>>>>  arch/arm64/include/uapi/asm/kvm.h |  1 +
>>>>>>  arch/arm64/kvm/guest.c            |  6 ++++++
>>>>>>  arch/arm64/kvm/reset.c            | 25 ++++++++++++++++++++++++-
>>>>>>  include/uapi/linux/kvm.h          |  1 +
>>>>>>  5 files changed, 33 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
>>>>>> index d44064d..c3ec107 100644
>>>>>> --- a/arch/arm64/include/asm/kvm_host.h
>>>>>> +++ b/arch/arm64/include/asm/kvm_host.h
>>>>>> @@ -34,7 +34,7 @@
>>>>>>  #include <asm/kvm_vgic.h>
>>>>>>  #include <asm/kvm_arch_timer.h>
>>>>>>
>>>>>> -#define KVM_VCPU_MAX_FEATURES 1
>>>>>> +#define KVM_VCPU_MAX_FEATURES 2
>>>>>>
>>>>>>  /* We don't currently support large pages. */
>>>>>>  #define KVM_HPAGE_GFN_SHIFT(x)      0
>>>>>> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
>>>>>> index 5b1110c..5031f42 100644
>>>>>> --- a/arch/arm64/include/uapi/asm/kvm.h
>>>>>> +++ b/arch/arm64/include/uapi/asm/kvm.h
>>>>>> @@ -75,6 +75,7 @@ struct kvm_regs {
>>>>>>  #define KVM_VGIC_V2_CPU_SIZE                0x2000
>>>>>>
>>>>>>  #define KVM_ARM_VCPU_POWER_OFF              0 /* CPU is started in OFF state */
>>>>>> +#define KVM_ARM_VCPU_EL1_32BIT              1 /* CPU running a 32bit VM */
>>>>>>
>>>>>>  struct kvm_vcpu_init {
>>>>>>      __u32 target;
>>>>>> diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
>>>>>> index 47d3729..74ef7d5 100644
>>>>>> --- a/arch/arm64/kvm/guest.c
>>>>>> +++ b/arch/arm64/kvm/guest.c
>>>>>> @@ -93,6 +93,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
>>>>>>      if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
>>>>>>              unsigned long mode = (*(unsigned long *)valp) & COMPAT_PSR_MODE_MASK;
>>>>>>              switch (mode) {
>>>>>> +            case COMPAT_PSR_MODE_USR:
>>>>>> +            case COMPAT_PSR_MODE_FIQ:
>>>>>> +            case COMPAT_PSR_MODE_IRQ:
>>>>>> +            case COMPAT_PSR_MODE_SVC:
>>>>>> +            case COMPAT_PSR_MODE_ABT:
>>>>>> +            case COMPAT_PSR_MODE_UND:
>>>>>>              case PSR_MODE_EL0t:
>>>>>>              case PSR_MODE_EL1t:
>>>>>>              case PSR_MODE_EL1h:
>>>>>> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
>>>>>> index bc33e76..a282d35 100644
>>>>>> --- a/arch/arm64/kvm/reset.c
>>>>>> +++ b/arch/arm64/kvm/reset.c
>>>>>> @@ -35,11 +35,27 @@ static struct kvm_regs default_regs_reset = {
>>>>>>      .regs.pstate = PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
>>>>>>  };
>>>>>>
>>>>>> +static struct kvm_regs default_regs_reset32 = {
>>>>>> +    .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
>>>>>> +                    COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
>>>>>> +};
>>>>>> +
>>>>>> +static bool cpu_has_32bit_el1(void)
>>>>>> +{
>>>>>> +    u64 pfr0;
>>>>>> +
>>>>>> +    pfr0 = read_cpuid(ID_AA64PFR0_EL1);
>>>>>> +    return !!(pfr0 & 0x20);
>>>>>
>>>>> again we don't need the double negation
>>>>
>>>> I still hold that it makes things more readable.
>>>>
>>>>>> +}
>>>>>> +
>>>>>>  int kvm_arch_dev_ioctl_check_extention(long ext)
>>>>>>  {
>>>>>>      int r;
>>>>>>
>>>>>>      switch (ext) {
>>>>>> +    case KVM_CAP_ARM_EL1_32BIT:
>>>>>> +            r = cpu_has_32bit_el1();
>>>>>> +            break;
>>>>>>      default:
>>>>>>              r = 0;
>>>>>>      }
>>>>>> @@ -62,7 +78,14 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
>>>>>>
>>>>>>      switch (vcpu->arch.target) {
>>>>>>      default:
>>>>>> -            cpu_reset = &default_regs_reset;
>>>>>> +            if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
>>>>>> +                    if (!cpu_has_32bit_el1())
>>>>>> +                            return -EINVAL;
>>>>>
>>>>> I'm not sure EINVAL is appropriate here, the value specified was not
>>>>> incorrect, it's that the hardware doesn't support it. ENXIO, ENODEV, and
>>>>> add that in Documentation/virtual/kvm/api.txt ?
>>>>
>>>> Not sure. If you ended up here, it means you tried to start a 32bit
>>>> guest on a 64bit-only CPU, despite KVM_CAP_ARM_EL1_32BIT telling you
>>>> that your CPU is not 32bit capable.
>>>>
>>>> This is clearly an invalid input, isn't it?
>>>>
>>> check the API documentation for this ioctl, I don't think that's the
>>> type of invalid input meant when describing the meaning of EINVAL. If
>>> you feel strongly about it of course it's no big deal, but I think
>>> EINVAL is so overloaded anyway that telling the user something more
>>> specific would be great, but I'll leave it up to you.
>>
>> [bit late on this one...]
>>
>> Here's what the documentation says:
>> <quote>
>> 4.77 KVM_ARM_VCPU_INIT
>>
>> Capability: basic
>> Architectures: arm, arm64
>> Type: vcpu ioctl
>> Parameters: struct struct kvm_vcpu_init (in)
>> Returns: 0 on success; -1 on error
>> Errors:
>>   EINVAL:    the target is unknown, or the combination of features is invalid.
>>   ENOENT:    a features bit specified is unknown.
>> </quote>
>>
>> When this call fails, it is because you've requested a feature
>> that is invalid for this CPU. To me, that exactly fits the
>> EINVAL entry copied above.
>>
>> Or am I completely misunderstanding it?
>>
> I read the EINVAL to say that you supplied something which is invalid
> for the software interface and you should fix your user space code.

Exactly. The code should have checked for the corresponding capability
before blindly requesting that feature. That's exactly why we have
capabilities.

> The fact that you're requesting a feature that your hardware doesn't
> support is a different thing IMHO.

Well, if you're allowed to call into this without checking the
capabilities, then I suggest we remove them, because they are clearly
superfluous.

	M.
-- 
Jazz is not dead. It just smells funny...



From andreas.herrmann at calxeda.com  Mon May 13 05:07:24 2013
From: andreas.herrmann at calxeda.com (Andreas Herrmann)
Date: Mon, 13 May 2013 11:07:24 +0200
Subject: [PATCH] documentation: iommu: add description of ARM System MMU
 binding
In-Reply-To: <5189635A.8090504@codeaurora.org>
References: <20130408092535.GA17476@mudshark.cambridge.arm.com>
 <5162F87A.7070409@codeaurora.org>
 <20130410173732.GQ26992@mudshark.cambridge.arm.com>
 <5169C7D1.8070300@codeaurora.org>
 <20130415131341.GG9827@mudshark.cambridge.arm.com>
 <516D9602.2010404@codeaurora.org>
 <20130418190131.GA12344@mudshark.cambridge.arm.com>
 <5177113D.7060300@codeaurora.org>
 <20130424095501.GC21850@mudshark.cambridge.arm.com>
 <5189635A.8090504@codeaurora.org>
Message-ID: <20130513090724.GA10369@alberich>

On Tue, May 07, 2013 at 04:26:02PM -0400, Olav Haugan wrote:
> Hi Will,
> 
> On 4/24/2013 2:55 AM, Will Deacon wrote:
> > On Tue, Apr 23, 2013 at 11:54:53PM +0100, Olav Haugan wrote:
> >> On 4/18/2013 12:01 PM, Will Deacon wrote:
> > Getting phandles has no dependencies on anything -- the only dependency is
> > that the device is added to the bus on which the SMMU sits, just like every
> > other IOMMU driver.
> > 
> >>> Why would a page table shared between devices require multiple context
> >>> banks? Multiple SMRs and S2CRs, sure, but they would ultimately point at the
> >>> same context bank (and hence same address space).
> >>
> >> What if you want to have 2 different VMID's being generated? Also, what
> >> about TLB management? If I have two context banks I can invalidate only
> >> entries associated with 1 of the context banks (if VMID differ for the
> >> two context banks).
> > 
> > Huh? We allocate one VMID per domain. If you want more VMIDs, use more
> > domains. TLB invalidation is per-domain, so there's no issue there.
> 
> If we allocate a new domain you would have another address space (page
> table), no? I was just trying to figure out if your binding proposal
> would allow for 2 context banks in one domain which it does not seem to
> support.
> 
> >>> If a master needs to be in two address spaces at once, then it will need to
> >>> attach it's StreamIDs to different domains. You can't place a single
> >>> StreamID in two address spaces (this is an architectural constraint).
> >>
> >> Yes, you would have a separate domain. I am just wondering how I would
> >> model this in DT using the bindings that you are proposing? How does it
> >> work? The bindings specify bus masters to StreamIDs. So if I call attach
> >> with the master device you will allocate a context bank and program the
> >> StreamIDs as specified in the DT. So now if I want to have another
> >> context bank associated with the same master device what do I do? I call
> >> into attach with a new domain but with the same master device but the
> >> master device is already attached to a context/domain.
> > 
> > Why would you want to place a StreamID into two domains? That doesn't make
> > any sense and isn't even supported by the architecture (things like
> > conflicting SMR entries may not even be reported).
> 
> I think you misunderstood me. I am talking about having for example 1
> master with two (2) context banks so that StreamID "1" goes to CB0 and
> StreamID "2" goes to CB1. This means that the master device is attached
> to two different domains. How do I model this with the the device tree
> bindings?

Hi Olav,

I think with the proposed device tree binding you can't model this.

Do we have such use cases already? Or what future use cases would
require this?

I can imagine of multiple contexts per device for stuff similar to
what PASID in PCI Express are used for.

But in such a case you probably want to have some configurable bits in
the StreamID (that should be set by an SMMU driver). And the DT
binding should contain the number of contexts that a master device can
support.


Andreas


From marc.zyngier at arm.com  Mon May 13 05:08:12 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 13 May 2013 10:08:12 +0100
Subject: [PATCH] ARM: KVM: Handle loads from I/O addresses to PC
In-Reply-To: <1368385135-60584-1-git-send-email-cdall@cs.columbia.edu>
References: <1368385135-60584-1-git-send-email-cdall@cs.columbia.edu>
Message-ID: <5190AD7C.2000501@arm.com>

On 12/05/13 19:58, Christoffer Dall wrote:
> If a VM does something like this:
> 
> ldr     pc, [r0]        @ r0 is an I/O address
> 
> Then simply let that value load into the PC on kvm_handle_mmio_return
> overwriting the PC value set from kvm_skip_instr.
> 
> Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>

I've had a slightly more complete patch in my tree for a while (look at
bef0ef01ae75 on the kvm-arm64/kvm-3.10-rc0 branch).

> ---
>  arch/arm/kvm/mmio.c |    6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
> index 72a12f2..b8e06b7 100644
> --- a/arch/arm/kvm/mmio.c
> +++ b/arch/arm/kvm/mmio.c
> @@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
>  	sign_extend = kvm_vcpu_dabt_issext(vcpu);
>  	rt = kvm_vcpu_dabt_get_rd(vcpu);
>  
> -	if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
> -		/* IO memory trying to read/write pc */
> -		kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
> -		return 1;
> -	}
> -
>  	mmio->is_write = is_write;
>  	mmio->phys_addr = fault_ipa;
>  	mmio->len = len;
> 

Otherwise looks good to me.

	M.
-- 
Jazz is not dead. It just smells funny...



From catalin.marinas at arm.com  Mon May 13 05:18:31 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 13 May 2013 10:18:31 +0100
Subject: [PATCH] ARM: KVM: Handle loads from I/O addresses to PC
In-Reply-To: <1368385135-60584-1-git-send-email-cdall@cs.columbia.edu>
References: <1368385135-60584-1-git-send-email-cdall@cs.columbia.edu>
Message-ID: <20130513091830.GA18242@darko.cambridge.arm.com>

On Sun, May 12, 2013 at 07:58:55PM +0100, Christoffer Dall wrote:
> If a VM does something like this:
> 
> ldr     pc, [r0]        @ r0 is an I/O address
> 
> Then simply let that value load into the PC on kvm_handle_mmio_return
> overwriting the PC value set from kvm_skip_instr.
> 
> Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>
> ---
>  arch/arm/kvm/mmio.c |    6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
> index 72a12f2..b8e06b7 100644
> --- a/arch/arm/kvm/mmio.c
> +++ b/arch/arm/kvm/mmio.c
> @@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
>  	sign_extend = kvm_vcpu_dabt_issext(vcpu);
>  	rt = kvm_vcpu_dabt_get_rd(vcpu);
>  
> -	if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
> -		/* IO memory trying to read/write pc */
> -		kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
> -		return 1;

I haven't checked Marc's patch yet but I would get rid of
kvm_vcpu_reg_is_pc() as well, that's the only place where it is used.

-- 
Catalin


From inki.dae at samsung.com  Mon May 13 05:21:12 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Mon, 13 May 2013 18:21:12 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <51909DB4.2060208@canonical.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
Message-ID: <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>



> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
> Sent: Monday, May 13, 2013 5:01 PM
> To: Inki Dae
> Cc: Rob Clark; Daniel Vetter; DRI mailing list; linux-arm-
> kernel at lists.infradead.org; linux-media at vger.kernel.org; linux-fbdev;
> Kyungmin Park; myungjoo.ham; YoungJun Cho
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> Op 09-05-13 09:33, Inki Dae schreef:
> > Hi all,
> >
> > This post introduces a new helper framework based on dma fence. And the
> > purpose of this post is to collect other opinions and advices before RFC
> > posting.
> >
> > First of all, this helper framework, called fence helper, is in progress
> > yet so might not have enough comments in codes and also might need to be
> > more cleaned up. Moreover, we might be missing some parts of the dma
> fence.
> > However, I'd like to say that all things mentioned below has been tested
> > with Linux platform and worked well.
> 
> > ....
> >
> > And tutorial for user process.
> >         just before cpu access
> >                 struct dma_buf_fence *df;
> >
> >                 df->type = DMA_BUF_ACCESS_READ or DMA_BUF_ACCESS_WRITE;
> >                 ioctl(fd, DMA_BUF_GET_FENCE, &df);
> >
> >         after memset or memcpy
> >                 ioctl(fd, DMA_BUF_PUT_FENCE, &df);
> NAK.
> 
> Userspace doesn't need to trigger fences. It can do a buffer idle wait,
> and postpone submitting new commands until after it's done using the
> buffer.

Hi Maarten,

It seems that you say user should wait for a buffer like KDS does: KDS uses
select() to postpone submitting new commands. But I think this way assumes
that every data flows a DMA device to a CPU. For example, a CPU should keep
polling for the completion of a buffer access by a DMA device. This means
that the this way isn't considered for data flow to opposite case; CPU to
DMA device.

> Kernel space doesn't need the root hole you created by giving a
> dereferencing a pointer passed from userspace.
> Your next exercise should be to write a security exploit from the api you
> created here. It's the only way to learn how to write safe code. Hint:
> df.ctx = mmap(..);
> 

Also I'm not clear to use our way yet and that is why I posted. As you
mentioned, it seems like that using mmap() is more safe. But there is one
issue it makes me confusing. For your hint, df.ctx = mmap(..), the issue is
that dmabuf mmap can be used to map a dmabuf with user space. And the dmabuf
means a physical memory region allocated by some allocator such as drm gem
or ion.

There might be my missing point so could you please give me more comments?

Thanks,
Inki Dae



> ~Maarten



From jp.francois at cynove.com  Mon May 13 05:28:38 2013
From: jp.francois at cynove.com (jean-philippe francois)
Date: Mon, 13 May 2013 11:28:38 +0200
Subject: [PATCH] ARM: OMAP: fix __init section mismatch for _enable_preprogram
Message-ID: <CAGGh5h1_-zbe=gw+YtMeddGxGkVzos=siavOv9nbSOVZqk1nVw@mail.gmail.com>

Hi,

_enable_preprogram is marked as __init, but is called from _enable
which is not. Without this patch, the board oopses after init. Tested
on custom hardware and on beagle board xM.

Signed-off-by: Jean-Philippe Fran?ois <jp.francois at cynove.com>
-------------- next part --------------
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From jp.francois at cynove.com  Mon May 13 05:44:04 2013
From: jp.francois at cynove.com (jean-philippe francois)
Date: Mon, 13 May 2013 11:44:04 +0200
Subject: Board file to device tree migration
Message-ID: <CAGGh5h3MC=ruocV9u6Cig=oiTtqU8GtpQ6sRKUZmUNk-C7Houw@mail.gmail.com>

Hi,

I am maintaining a board file, which i did not submit since the board
was developped after the decision was taken to move to device tree,
and I figured no more board file would be accepted.

I can't move to full device tree, since if my understanding is
correct, the omap3-isp is not supported yet, and our board is a
camera, so isp is mandatory.

My question is, is it possible to do a mixed style init, with some of
the devices coming from a board file, and others from a dts file ? Is
there any example of board using this kind of mixed init ?

Regards,
Jean-Philippe Fran?ois


From maxime.ripard at free-electrons.com  Mon May 13 05:44:02 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:02 +0200
Subject: [PATCH 03/14] ARM: nomadik: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-4-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for nomadik as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-nomadik/cpu-8815.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..3d43f95 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -323,7 +323,6 @@ static const char * cpu8815_board_compat[] = {
 
 DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
 	.map_io		= cpu8815_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= cpu8815_timer_init_of,
 	.init_machine	= cpu8815_init_of,
 	.restart	= cpu8815_restart,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:03 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:03 +0200
Subject: [PATCH 04/14] ARM: picoxcell: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-5-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for picoxcell as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Jamie Iles <jamie at jamieiles.com>
---
 arch/arm/mach-picoxcell/common.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..b444947 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -87,7 +87,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
 	.map_io		= picoxcell_map_io,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_time	= dw_apb_timer_init,
 	.init_machine	= picoxcell_init_machine,
 	.dt_compat	= picoxcell_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:00 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:00 +0200
Subject: [PATCH 01/14] ARM: sunxi: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-2-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for sunxi as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-sunxi/sunxi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..4de1edf 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -117,7 +117,6 @@ static const char * const sunxi_board_dt_compat[] = {
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
 	.init_machine	= sunxi_dt_init,
 	.map_io		= sunxi_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sunxi_timer_init,
 	.dt_compat	= sunxi_board_dt_compat,
 MACHINE_END
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:01 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:01 +0200
Subject: [PATCH 02/14] ARM: zynq: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-3-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for zynq as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Michal Simek <monstr at monstr.eu>
---
 arch/arm/mach-zynq/common.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5bfe703..8bc3acb 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -106,7 +106,6 @@ static const char * const zynq_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
 	.smp		= smp_ops(zynq_smp_ops),
 	.map_io		= zynq_map_io,
-	.init_irq	= irqchip_init,
 	.init_machine	= zynq_init_machine,
 	.init_time	= zynq_timer_init,
 	.dt_compat	= zynq_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:43:59 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:43:59 +0200
Subject: [PATCH 00/14] Cleanup irqchip_init calls
Message-ID: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>

Hi everyone,

This is a splitted up version of the patch I previously sent to
remove the explicit declaration of irqchip_init as the init_irq callback in
the machine descriptions.

Since it was a pretty tricky patch to merge, since it was touching a lot of
different platforms, I splitted it for each platforms, and rebased it on top
of 3.10-rc1.

Thanks,
Maxime

Maxime Ripard (14):
  ARM: sunxi: Remove init_irq declaration in machine description
  ARM: zynq: Remove init_irq declaration in machine description
  ARM: nomadik: Remove init_irq declaration in machine description
  ARM: picoxcell: Remove init_irq declaration in machine description
  ARM: shmobile: Remove init_irq declaration in machine description
  ARM: bcm281xx: Remove init_irq declaration in machine description
  ARM: spear: Remove init_irq declaration in machine description
  ARM: msm: Remove init_irq declaration in machine description
  ARM: mvebu: Remove init_irq declaration in machine description
  ARM: mxs: Remove init_irq declaration in machine description
  ARM: sirf: Remove init_irq declaration in machine description
  ARM: vexpress: Remove init_irq declaration in machine description
  ARM: virt: Remove init_irq declaration in machine description
  ARM: vt8500: Remove init_irq declaration in machine description

 arch/arm/mach-bcm/board_bcm.c                  | 1 -
 arch/arm/mach-msm/board-dt-8660.c              | 1 -
 arch/arm/mach-msm/board-dt-8960.c              | 1 -
 arch/arm/mach-mvebu/armada-370-xp.c            | 1 -
 arch/arm/mach-mxs/mach-mxs.c                   | 1 -
 arch/arm/mach-nomadik/cpu-8815.c               | 1 -
 arch/arm/mach-picoxcell/common.c               | 1 -
 arch/arm/mach-prima2/common.c                  | 3 ---
 arch/arm/mach-shmobile/board-ape6evm.c         | 1 -
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 -
 arch/arm/mach-shmobile/board-lager.c           | 1 -
 arch/arm/mach-shmobile/setup-emev2.c           | 1 -
 arch/arm/mach-shmobile/setup-r8a73a4.c         | 1 -
 arch/arm/mach-shmobile/setup-r8a7790.c         | 1 -
 arch/arm/mach-shmobile/setup-sh73a0.c          | 1 -
 arch/arm/mach-spear/spear1310.c                | 1 -
 arch/arm/mach-spear/spear1340.c                | 1 -
 arch/arm/mach-spear/spear300.c                 | 1 -
 arch/arm/mach-spear/spear310.c                 | 1 -
 arch/arm/mach-spear/spear320.c                 | 1 -
 arch/arm/mach-spear/spear6xx.c                 | 1 -
 arch/arm/mach-sunxi/sunxi.c                    | 1 -
 arch/arm/mach-vexpress/v2m.c                   | 1 -
 arch/arm/mach-virt/virt.c                      | 1 -
 arch/arm/mach-vt8500/vt8500.c                  | 1 -
 arch/arm/mach-zynq/common.c                    | 1 -
 26 files changed, 28 deletions(-)

-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:13 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:13 +0200
Subject: [PATCH 14/14] ARM: vt8500: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-15-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for vt8500 as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-vt8500/vt8500.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..1585900 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -178,7 +178,6 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
 	.dt_compat	= vt8500_dt_compat,
 	.map_io		= vt8500_map_io,
-	.init_irq	= irqchip_init,
 	.init_machine	= vt8500_init,
 	.init_time	= clocksource_of_init,
 	.restart	= vt8500_restart,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:09 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:09 +0200
Subject: [PATCH 10/14] ARM: mxs: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-11-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for mxs as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..ef892b1 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -435,7 +435,6 @@ static const char *mxs_dt_compat[] __initdata = {
 
 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
 	.map_io		= debug_ll_io_init,
-	.init_irq	= irqchip_init,
 	.handle_irq	= icoll_handle_irq,
 	.init_time	= mxs_timer_init,
 	.init_machine	= mxs_machine_init,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:05 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:05 +0200
Subject: [PATCH 06/14] ARM: bcm281xx: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-7-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for bcm281xx as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-bcm/board_bcm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
index 22e8421..24556cf 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -54,7 +54,6 @@ static void __init board_init(void)
 static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
 
 DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
-	.init_irq = irqchip_init,
 	.init_time = clocksource_of_init,
 	.init_machine = board_init,
 	.dt_compat = bcm11351_dt_compat,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:11 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:11 +0200
Subject: [PATCH 12/14] ARM: vexpress: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-13-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for vexpress as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-vexpress/v2m.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 8802030..c419b76 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -458,7 +458,6 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
 	.smp		= smp_ops(vexpress_smp_ops),
 	.map_io		= v2m_dt_map_io,
 	.init_early	= v2m_dt_init_early,
-	.init_irq	= irqchip_init,
 	.init_time	= v2m_dt_timer_init,
 	.init_machine	= v2m_dt_init,
 MACHINE_END
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:12 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:12 +0200
Subject: [PATCH 13/14] ARM: virt: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-14-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for virt as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-virt/virt.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 061f283..2370a61 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -39,7 +39,6 @@ static const char *virt_dt_match[] = {
 extern struct smp_operations virt_smp_ops;
 
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-	.init_irq	= irqchip_init,
 	.init_machine	= virt_init,
 	.smp		= smp_ops(virt_smp_ops),
 	.dt_compat	= virt_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:08 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:08 +0200
Subject: [PATCH 09/14] ARM: mvebu: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-10-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for mvebu as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3..8500002 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -96,7 +96,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
 	.init_machine	= armada_370_xp_dt_init,
 	.map_io		= armada_370_xp_map_io,
 	.init_early	= armada_370_xp_init_early,
-	.init_irq	= irqchip_init,
 	.init_time	= armada_370_xp_timer_and_clk_init,
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_370_xp_dt_compat,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:07 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:07 +0200
Subject: [PATCH 08/14] ARM: msm: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-9-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for msm as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-msm/board-dt-8660.c | 1 -
 arch/arm/mach-msm/board-dt-8960.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 7dcfc53..1360226 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -44,7 +44,6 @@ static const char *msm8x60_fluid_match[] __initdata = {
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
 	.smp = smp_ops(msm_smp_ops),
 	.map_io = msm_map_msm8x60_io,
-	.init_irq = irqchip_init,
 	.init_machine = msm8x60_dt_init,
 	.init_late = msm8x60_init_late,
 	.init_time	= msm_dt_timer_init,
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index 7301936..1e8eb1d 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -31,7 +31,6 @@ static const char * const msm8960_dt_match[] __initconst = {
 DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
 	.smp = smp_ops(msm_smp_ops),
 	.map_io = msm_map_msm8960_io,
-	.init_irq = irqchip_init,
 	.init_time	= msm_dt_timer_init,
 	.init_machine = msm_dt_init,
 	.dt_compat = msm8960_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:10 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:10 +0200
Subject: [PATCH 11/14] ARM: sirf: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-12-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for sirf as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-prima2/common.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd8..52e28cf 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -55,7 +55,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.nr_irqs	= 128,
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
@@ -74,7 +73,6 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.nr_irqs	= 128,
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
@@ -94,7 +92,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.smp            = smp_ops(sirfsoc_smp_ops),
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:06 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:06 +0200
Subject: [PATCH 07/14] ARM: spear: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-8-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for spear as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-spear/spear1310.c | 1 -
 arch/arm/mach-spear/spear1340.c | 1 -
 arch/arm/mach-spear/spear300.c  | 1 -
 arch/arm/mach-spear/spear310.c  | 1 -
 arch/arm/mach-spear/spear320.c  | 1 -
 arch/arm/mach-spear/spear6xx.c  | 1 -
 6 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 9eaac2c..b2da424 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -60,7 +60,6 @@ static void __init spear1310_map_io(void)
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
 	.smp		=	smp_ops(spear13xx_smp_ops),
 	.map_io		=	spear1310_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear13xx_timer_init,
 	.init_machine	=	spear1310_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index a04a7fe..dae1167 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -155,7 +155,6 @@ static const char * const spear1340_dt_board_compat[] = {
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
 	.smp		=	smp_ops(spear13xx_smp_ops),
 	.map_io		=	spear13xx_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear13xx_timer_init,
 	.init_machine	=	spear1340_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c
index bac56e8..185b9ba 100644
--- a/arch/arm/mach-spear/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -212,7 +212,6 @@ static void __init spear300_map_io(void)
 
 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
 	.map_io		=	spear300_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear3xx_timer_init,
 	.init_machine	=	spear300_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c
index 6ffbc63..ebc07e6 100644
--- a/arch/arm/mach-spear/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -254,7 +254,6 @@ static void __init spear310_map_io(void)
 
 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
 	.map_io		=	spear310_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear3xx_timer_init,
 	.init_machine	=	spear310_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c
index 6eb3eec..1fa4929 100644
--- a/arch/arm/mach-spear/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -269,7 +269,6 @@ static void __init spear320_map_io(void)
 
 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
 	.map_io		=	spear320_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear3xx_timer_init,
 	.init_machine	=	spear320_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index ec8eefb..0359f2e 100644
--- a/arch/arm/mach-spear/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -423,7 +423,6 @@ static const char *spear600_dt_board_compat[] = {
 
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
 	.map_io		=	spear6xx_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear6xx_timer_init,
 	.init_machine	=	spear600_dt_init,
 	.restart	=	spear_restart,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 05:44:04 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 11:44:04 +0200
Subject: [PATCH 05/14] ARM: shmobile: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368438253-28218-6-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/board-ape6evm.c         | 1 -
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 -
 arch/arm/mach-shmobile/board-lager.c           | 1 -
 arch/arm/mach-shmobile/setup-emev2.c           | 1 -
 arch/arm/mach-shmobile/setup-r8a73a4.c         | 1 -
 arch/arm/mach-shmobile/setup-r8a7790.c         | 1 -
 arch/arm/mach-shmobile/setup-sh73a0.c          | 1 -
 7 files changed, 7 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 55b8c9f..913ce31 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -87,7 +87,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-	.init_irq	= irqchip_init,
 	.init_time	= shmobile_timer_init,
 	.init_machine	= ape6evm_add_standard_devices,
 	.dt_compat	= ape6evm_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d..eaec498 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -100,7 +100,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
 	.map_io		= sh73a0_map_io,
 	.init_early	= sh73a0_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= kzm_init,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= kzm9g_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187..c384c9f 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -39,7 +39,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
-	.init_irq	= irqchip_init,
 	.init_time	= r8a7790_timer_init,
 	.init_machine	= lager_add_standard_devices,
 	.dt_compat	= lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 899a86c..098ca63 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -454,7 +454,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
 	.smp		= smp_ops(emev2_smp_ops),
 	.init_early	= emev2_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= emev2_add_standard_devices_dt,
 	.dt_compat	= emev2_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c5a75a7..6b19d50 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -194,7 +194,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
-	.init_irq	= irqchip_init,
 	.init_machine	= r8a73a4_add_standard_devices_dt,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= r8a73a4_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d5..d639aad 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -142,7 +142,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
-	.init_irq	= irqchip_init,
 	.init_machine	= r8a7790_add_standard_devices_dt,
 	.init_time	= r8a7790_timer_init,
 	.dt_compat	= r8a7790_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..3a7d24a 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -1035,7 +1035,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 	.map_io		= sh73a0_map_io,
 	.init_early	= sh73a0_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= sh73a0_add_standard_devices_dt,
 	.dt_compat	= sh73a0_boards_compat_dt,
 MACHINE_END
-- 
1.8.1.2



From viresh.kumar at linaro.org  Mon May 13 05:46:06 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 13 May 2013 15:16:06 +0530
Subject: [PATCH 07/14] ARM: spear: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-8-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-8-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CAKohpo=TRXoZ2L0vUor4834QNbf0UxaB9AVYY-r-3mAKYTgjig@mail.gmail.com>

On 13 May 2013 15:14, Maxime Ripard <maxime.ripard at free-electrons.com> wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for spear as well.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-spear/spear1310.c | 1 -
>  arch/arm/mach-spear/spear1340.c | 1 -
>  arch/arm/mach-spear/spear300.c  | 1 -
>  arch/arm/mach-spear/spear310.c  | 1 -
>  arch/arm/mach-spear/spear320.c  | 1 -
>  arch/arm/mach-spear/spear6xx.c  | 1 -
>  6 files changed, 6 deletions(-)

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From andreas.herrmann at calxeda.com  Mon May 13 05:50:20 2013
From: andreas.herrmann at calxeda.com (Andreas Herrmann)
Date: Mon, 13 May 2013 11:50:20 +0200
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
Message-ID: <20130513095020.GB10369@alberich>

Hi Will,

so far, I thought, that this proposal is fine. After I have tried to
make use of the binding I have some points that might need further
disucssion.

Olav already asked (in another thread) how to model the mapping of
stream IDs to contexts for master devices that support multiple
contexts.  I doubt that this is fully covered yet.

I also think that it is more useful to move the stream-id property to
the device node of a master device. (It's a characteristic of the
master device not of the SMMU.) Currently with multiple stream IDs per
master device you have repeated entries in the mmu-master property.

But all that is needed is to point (once) to each mmu-master in the
SMMU device node. Then you should be able to look up the corresponding
stream IDs in the device node for each mmu-master.


Regars,
Andreas


On Fri, Apr 12, 2013 at 02:02:07PM -0400, Will Deacon wrote:
> This patch adds a description of the device tree binding for the ARM
> System MMU architecture.
> 
> Cc: Rob Herring <robherring2 at gmail.com>
> Cc: Andreas Herrmann <andreas.herrmann at calxeda.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  .../devicetree/bindings/iommu/arm,smmu.txt         | 66 ++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu.txt
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> new file mode 100644
> index 0000000..56de07c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -0,0 +1,66 @@
> +* ARM System MMU Architecture Implementation
> +
> +ARM SoCs may contain an implementation of the ARM System Memory
> +Management Unit Architecture, which can be used to provide 1 or 2 stages
> +of address translation to bus masters external to the CPU.
> +
> +The SMMU may also raise interrupts in response to various fault
> +conditions.
> +
> +** System MMU required properties:
> +
> +- compatible    : Should be one of:
> +
> +                        "arm,smmu-v1"
> +                        "arm,smmu-v2"
> +                        "arm,mmu-400"
> +
> +                  depending on the particular implementation and/or the
> +                  version of the architecture implemented.
> +
> +- reg           : Base address and size of the SMMU.
> +
> +- #global-interrupts : The number of global interrupts exposed by the
> +                       device.
> +
> +- interrupts    : Interrupt list, with the first #global-irqs entries
> +                  corresponding to the global interrupts and any
> +                  following entries corresponding to context interrupts,
> +                  specified in order of their indexing by the SMMU.
> +
> +- mmu-masters   : A list of phandles to device nodes representing bus
> +                  masters for which the SMMU can provide a translation.
> +
> +- stream-ids    : A list of 32-bit values corresponding to the StreamIDs
> +                  for the devices listed in the mmu-masters property.
> +                  This list must be same length as mmu-masters, so
> +                  masters with multiple stream-ids will have multiple
> +                  entries in mmu-masters.
> +
> +** System MMU optional properties:
> +
> +- smmu-parent   : When multiple SMMUs are chained together, this
> +                  property can be used to provide a phandle to the
> +                  parent SMMU (that is the next SMMU on the path going
> +                  from the mmu-masters towards memory) node for this
> +                  SMMU.
> +
> +Example:
> +
> +        smmu {
> +                compatible = "arm,smmu-v1";
> +                reg = <0xba5e0000 0x10000>;
> +                #global-interrupts = <2>;
> +                interrupts = <0 32 4>,
> +                             <0 33 4>,
> +                             <0 34 4>, /* This is the first context interrupt */
> +                             <0 35 4>,
> +                             <0 36 4>,
> +                             <0 37 4>;
> +                mmu-masters = <&dma0>,
> +                              <&dma0>,
> +                              <&dma1>;
> +                stream-ids  = <0xd01d>,
> +                              <0xd01e>,
> +                              <0xd11c>;
> +        };
> -- 
> 1.8.0
> 


From maarten.lankhorst at canonical.com  Mon May 13 05:52:24 2013
From: maarten.lankhorst at canonical.com (Maarten Lankhorst)
Date: Mon, 13 May 2013 11:52:24 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
Message-ID: <5190B7D8.3010803@canonical.com>

Op 13-05-13 11:21, Inki Dae schreef:
>
>> -----Original Message-----
>> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
>> Sent: Monday, May 13, 2013 5:01 PM
>> To: Inki Dae
>> Cc: Rob Clark; Daniel Vetter; DRI mailing list; linux-arm-
>> kernel at lists.infradead.org; linux-media at vger.kernel.org; linux-fbdev;
>> Kyungmin Park; myungjoo.ham; YoungJun Cho
>> Subject: Re: Introduce a new helper framework for buffer synchronization
>>
>> Op 09-05-13 09:33, Inki Dae schreef:
>>> Hi all,
>>>
>>> This post introduces a new helper framework based on dma fence. And the
>>> purpose of this post is to collect other opinions and advices before RFC
>>> posting.
>>>
>>> First of all, this helper framework, called fence helper, is in progress
>>> yet so might not have enough comments in codes and also might need to be
>>> more cleaned up. Moreover, we might be missing some parts of the dma
>> fence.
>>> However, I'd like to say that all things mentioned below has been tested
>>> with Linux platform and worked well.
>>> ....
>>>
>>> And tutorial for user process.
>>>         just before cpu access
>>>                 struct dma_buf_fence *df;
>>>
>>>                 df->type = DMA_BUF_ACCESS_READ or DMA_BUF_ACCESS_WRITE;
>>>                 ioctl(fd, DMA_BUF_GET_FENCE, &df);
>>>
>>>         after memset or memcpy
>>>                 ioctl(fd, DMA_BUF_PUT_FENCE, &df);
>> NAK.
>>
>> Userspace doesn't need to trigger fences. It can do a buffer idle wait,
>> and postpone submitting new commands until after it's done using the
>> buffer.
> Hi Maarten,
>
> It seems that you say user should wait for a buffer like KDS does: KDS uses
> select() to postpone submitting new commands. But I think this way assumes
> that every data flows a DMA device to a CPU. For example, a CPU should keep
> polling for the completion of a buffer access by a DMA device. This means
> that the this way isn't considered for data flow to opposite case; CPU to
> DMA device.
Not really. You do both things the same way. You first wait for the bo to be idle, this could be implemented by adding poll support to the dma-buf fd.
Then you either do your read or write. Since userspace is supposed to be the one controlling the bo it should stay idle at that point. If you have another thread queueing
the buffer againbefore your thread is done that's a bug in the application, and can be solved with userspace locking primitives. No need for the kernel to get involved.

>> Kernel space doesn't need the root hole you created by giving a
>> dereferencing a pointer passed from userspace.
>> Your next exercise should be to write a security exploit from the api you
>> created here. It's the only way to learn how to write safe code. Hint:
>> df.ctx = mmap(..);
>>
> Also I'm not clear to use our way yet and that is why I posted. As you
> mentioned, it seems like that using mmap() is more safe. But there is one
> issue it makes me confusing. For your hint, df.ctx = mmap(..), the issue is
> that dmabuf mmap can be used to map a dmabuf with user space. And the dmabuf
> means a physical memory region allocated by some allocator such as drm gem
> or ion.
>
> There might be my missing point so could you please give me more comments?
>
My point was that userspace could change df.ctx to some mmap'd memory, forcing the kernel to execute some code prepared by userspace.


From will.deacon at arm.com  Mon May 13 05:58:46 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 May 2013 10:58:46 +0100
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130513095020.GB10369@alberich>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
Message-ID: <20130513095846.GC29814@mudshark.cambridge.arm.com>

On Mon, May 13, 2013 at 10:50:20AM +0100, Andreas Herrmann wrote:
> Hi Will,

Hi Andreas,

> so far, I thought, that this proposal is fine. After I have tried to
> make use of the binding I have some points that might need further
> disucssion.

Sure, although I've been using the binding without issues so it would be
interesting to understand your use-case and why it's raising problems.

> Olav already asked (in another thread) how to model the mapping of
> stream IDs to contexts for master devices that support multiple
> contexts.  I doubt that this is fully covered yet.

Yeah, I've been meaning to reply to that. Given the way that the IOMMU API
is structure in Linux, I don't think having multiple stream IDs per (struct)
device, where each StreamID points at a different context (and therefore
address space) makes much sense. It also doesn't solve the more general
problem where StreamIDs for a device might have different SMMUs downstream.

To solve this, I think it is better to treat the device as having multiple
struct device instances, and managing the mappings in the device driver.

For most devices, I'd expect a single context to be enough. This is
certainly the case for device virtualisation at stage-2 and DMA at stage-1.

> I also think that it is more useful to move the stream-id property to
> the device node of a master device. (It's a characteristic of the
> master device not of the SMMU.) Currently with multiple stream IDs per
> master device you have repeated entries in the mmu-master property.

The problem with that approach is how to handle StreamID remastering. This
can and will happen, so the StreamID for a device is actually a property of
both the device *and* a particular point in the bus topology. Putting this
information in the device nodes will drag topology information all over the
place and I don't think it will make things clearer to read or easier to parse.

> But all that is needed is to point (once) to each mmu-master in the
> SMMU device node. Then you should be able to look up the corresponding
> stream IDs in the device node for each mmu-master.

Again, you also need to tie in topology information if you go down this
route.

Will


From will.deacon at arm.com  Mon May 13 06:04:11 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 May 2013 11:04:11 +0100
Subject: [PATCH] documentation: iommu: add description of ARM System MMU
 binding
In-Reply-To: <20130513090724.GA10369@alberich>
References: <5162F87A.7070409@codeaurora.org>
 <20130410173732.GQ26992@mudshark.cambridge.arm.com>
 <5169C7D1.8070300@codeaurora.org>
 <20130415131341.GG9827@mudshark.cambridge.arm.com>
 <516D9602.2010404@codeaurora.org>
 <20130418190131.GA12344@mudshark.cambridge.arm.com>
 <5177113D.7060300@codeaurora.org>
 <20130424095501.GC21850@mudshark.cambridge.arm.com>
 <5189635A.8090504@codeaurora.org> <20130513090724.GA10369@alberich>
Message-ID: <20130513100411.GD29814@mudshark.cambridge.arm.com>

On Mon, May 13, 2013 at 10:07:24AM +0100, Andreas Herrmann wrote:
> On Tue, May 07, 2013 at 04:26:02PM -0400, Olav Haugan wrote:
> > I think you misunderstood me. I am talking about having for example 1
> > master with two (2) context banks so that StreamID "1" goes to CB0 and
> > StreamID "2" goes to CB1. This means that the master device is attached
> > to two different domains. How do I model this with the the device tree
> > bindings?
> 
> Hi Olav,
> 
> I think with the proposed device tree binding you can't model this.
> 
> Do we have such use cases already? Or what future use cases would
> require this?
> 
> I can imagine of multiple contexts per device for stuff similar to
> what PASID in PCI Express are used for.
> 
> But in such a case you probably want to have some configurable bits in
> the StreamID (that should be set by an SMMU driver). And the DT
> binding should contain the number of contexts that a master device can
> support.

See my reply to your other thread, but I don't think this should be solved
in the SMMU driver. I really think that the device/domain configuration
should be driven by the master device drivers, rather than the device-tree.

Will


From magnus.damm at gmail.com  Mon May 13 06:14:41 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Mon, 13 May 2013 19:14:41 +0900
Subject: [PATCH 1/3] gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
In-Reply-To: <1368435233-8587-2-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <CANqRtoQ2gLVRz-a1PoQeuy_=XVKMR8x+47NDT9FFQWdRu17c7A@mail.gmail.com>

On Mon, May 13, 2013 at 5:53 PM, Simon Horman
<horms+renesas at verge.net.au> wrote:
> As hardware support for this feature is not universal for all SoCs a flag,
> has_both_edge_trigger, has been added to the platform data of the driver to
> allow this feature to be enabled.
>
> The motivation for this is to allow use of the gpio-keys driver on the
> lager board which is based on the r8a7790 SoC. This patch has been lightly
> exercised using that driver on that board.
>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  drivers/gpio/gpio-rcar.c                | 27 ++++++++++++++++++++++-----
>  include/linux/platform_data/gpio-rcar.h |  1 +
>  2 files changed, 23 insertions(+), 5 deletions(-)

Thanks for the patch, Simon!

> diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
> index 0f3d647..33d8f6a 100644
> --- a/drivers/gpio/gpio-rcar.c
> +++ b/drivers/gpio/gpio-rcar.c
> @@ -49,6 +49,7 @@ struct gpio_rcar_priv {
>  #define POSNEG 0x20
>  #define EDGLEVEL 0x24
>  #define FILONOFF 0x28
> +#define BOTHEDGE 0x4c
>
>  static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
>  {
> @@ -111,6 +113,11 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
>         /* Select "Interrupt Input Mode" in IOINTSEL */
>         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
>
> +       if (p->config.has_both_edge_trigger && !level_trigger) {
> +               /* Select one edge or both edges in BOTHEDGE */
> +               gpio_rcar_modify_bit(p, IOINTSEL, hwirq, both);
> +       }
> +
>         /* Write INTCLR in case of edge trigger */
>         if (!level_trigger)
>                 gpio_rcar_write(p, INTCLR, BIT(hwirq));

In your hunk above I suspect you want to setup the BOTHEDGE register
instead of IOINTSEL.

Also, I wonder how BOTHEDGE should be set in the case of level
trigger. Say that the user first selects edge trigger and then
reconfigures to level, then you probably want to make sure the
BOTHEDGE register is cleared.

So may want to do something like this (untested):

       if (p->config.has_both_edge_trigger) {
               /* Select one edge or both edges in BOTHEDGE */
               gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
       }

Also, please double check that the register access sequences in the
documentation are still kept, please see "6.7.1 Setting Edge-Sensitive
Interrupt Input Mode" in the H2 data sheet. It looks like you want to
move this setting so it happens before IOINTSEL.

Thanks!

/ magnus


From maxime.ripard at free-electrons.com  Mon May 13 06:16:06 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 12:16:06 +0200
Subject: [PATCH 1/4] ARM: mmu: Call debug_ll_io_init if no map_io function is
 specified
In-Reply-To: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368440169-29088-2-git-send-email-maxime.ripard@free-electrons.com>

More and more sub-architectures are using only the debug_ll_io_init
function as the map_io function. Make the core code call this function
if no function is specified in the machine description to remove some
boilerplate code.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mm/mmu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e0d8565..faa36d7 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1232,6 +1232,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 	 */
 	if (mdesc->map_io)
 		mdesc->map_io();
+	else
+		debug_ll_io_init();
 	fill_pmd_gaps();
 
 	/* Reserve fixed i/o space in VMALLOC region */
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 06:16:08 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 12:16:08 +0200
Subject: [PATCH 3/4] ARM: mxs: remove the .map_io declaration
In-Reply-To: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368440169-29088-4-git-send-email-maxime.ripard@free-electrons.com>

Now that the ARM core code calls debug_ll_io_init, we can remove it from
the machine_desc declaration.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..d67ecc1 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -434,7 +434,6 @@ static const char *mxs_dt_compat[] __initdata = {
 };
 
 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
-	.map_io		= debug_ll_io_init,
 	.init_irq	= irqchip_init,
 	.handle_irq	= icoll_handle_irq,
 	.init_time	= mxs_timer_init,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 06:16:05 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 12:16:05 +0200
Subject: [PATCH 0/4] ARM: Remove boilerplate debug_ll_io_init code
Message-ID: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

The recent introduction of debug_ll_io_init made possible to not rely
anymore on a custom map_io function but on debug_ll_io_init for the
early mapping and then on the various drivers to do the needed mappings for
the kernel to boot.

Some architectures begin to use only this function as the map_io callback in
the machine description.

In order to remove some boilerplate code, make the ARM mm code call
debug_ll_io_init by itself when no .map_io callback is defined.

This has been tested on the sunxi platform.

Thanks,
Maxime

Maxime Ripard (4):
  ARM: mmu: Call debug_ll_io_init if no map_io function is specified
  ARM: highbank: remove the .map_io declaration
  ARM: mxs: remove the .map_io declaration
  ARM: sunxi: Remove the .map_io function declaration

 arch/arm/mach-highbank/highbank.c |  1 -
 arch/arm/mach-mxs/mach-mxs.c      |  1 -
 arch/arm/mach-sunxi/sunxi.c       | 17 -----------------
 arch/arm/mach-sunxi/sunxi.h       | 20 --------------------
 arch/arm/mm/mmu.c                 |  2 ++
 5 files changed, 2 insertions(+), 39 deletions(-)
 delete mode 100644 arch/arm/mach-sunxi/sunxi.h

-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 06:16:07 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 12:16:07 +0200
Subject: [PATCH 2/4] ARM: highbank: remove the .map_io declaration
In-Reply-To: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368440169-29088-3-git-send-email-maxime.ripard@free-electrons.com>

Now that the ARM core code calls debug_ll_io_init, we can remove it from
the machine_desc declaration.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-highbank/highbank.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index e7df2dd..dc5d6be 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -176,7 +176,6 @@ static const char *highbank_match[] __initconst = {
 
 DT_MACHINE_START(HIGHBANK, "Highbank")
 	.smp		= smp_ops(highbank_smp_ops),
-	.map_io		= debug_ll_io_init,
 	.init_irq	= highbank_init_irq,
 	.init_time	= highbank_timer_init,
 	.init_machine	= highbank_init,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Mon May 13 06:16:09 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 12:16:09 +0200
Subject: [PATCH 4/4] ARM: sunxi: Remove the .map_io function declaration
In-Reply-To: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368440169-29088-5-git-send-email-maxime.ripard@free-electrons.com>

debug_ll_io_init should be enough to map the needed addresses at boot,
so remove the trivial map_io code, and let the core call
debug_ll_io_init.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-sunxi/sunxi.c | 17 -----------------
 arch/arm/mach-sunxi/sunxi.h | 20 --------------------
 2 files changed, 37 deletions(-)
 delete mode 100644 arch/arm/mach-sunxi/sunxi.h

diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..d1b5bc5 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -26,8 +26,6 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 
-#include "sunxi.h"
-
 #define SUN4I_WATCHDOG_CTRL_REG		0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART		(1 << 0)
 #define SUN4I_WATCHDOG_MODE_REG		0x04
@@ -81,20 +79,6 @@ static void sunxi_setup_restart(void)
 	arm_pm_restart = of_id->data;
 }
 
-static struct map_desc sunxi_io_desc[] __initdata = {
-	{
-		.virtual	= (unsigned long) SUNXI_REGS_VIRT_BASE,
-		.pfn		= __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
-		.length		= SUNXI_REGS_SIZE,
-		.type		= MT_DEVICE,
-	},
-};
-
-void __init sunxi_map_io(void)
-{
-	iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
-}
-
 static void __init sunxi_timer_init(void)
 {
 	sunxi_init_clocks();
@@ -116,7 +100,6 @@ static const char * const sunxi_board_dt_compat[] = {
 
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
 	.init_machine	= sunxi_dt_init,
-	.map_io		= sunxi_map_io,
 	.init_irq	= irqchip_init,
 	.init_time	= sunxi_timer_init,
 	.dt_compat	= sunxi_board_dt_compat,
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
deleted file mode 100644
index 33b5871..0000000
--- a/arch/arm/mach-sunxi/sunxi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Generic definitions for Allwinner SunXi SoCs
- *
- * Copyright (C) 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard at free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SUNXI_H
-#define __MACH_SUNXI_H
-
-#define SUNXI_REGS_PHYS_BASE	0x01c00000
-#define SUNXI_REGS_VIRT_BASE	IOMEM(0xf1c00000)
-#define SUNXI_REGS_SIZE		(SZ_2M + SZ_1M)
-
-#endif /* __MACH_SUNXI_H */
-- 
1.8.1.2



From andreas.herrmann at calxeda.com  Mon May 13 06:41:47 2013
From: andreas.herrmann at calxeda.com (Andreas Herrmann)
Date: Mon, 13 May 2013 12:41:47 +0200
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130513095846.GC29814@mudshark.cambridge.arm.com>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
 <20130513095846.GC29814@mudshark.cambridge.arm.com>
Message-ID: <20130513104147.GF10369@alberich>

On Mon, May 13, 2013 at 05:58:46AM -0400, Will Deacon wrote:
> On Mon, May 13, 2013 at 10:50:20AM +0100, Andreas Herrmann wrote:
> > Hi Will,
> 
> Hi Andreas,
> 
> > so far, I thought, that this proposal is fine. After I have tried to
> > make use of the binding I have some points that might need further
> > disucssion.
> 
> Sure, although I've been using the binding without issues so it would be
> interesting to understand your use-case and why it's raising problems.
> 
> > Olav already asked (in another thread) how to model the mapping of
> > stream IDs to contexts for master devices that support multiple
> > contexts.  I doubt that this is fully covered yet.
> 
> Yeah, I've been meaning to reply to that. Given the way that the IOMMU API
> is structure in Linux, I don't think having multiple stream IDs per (struct)
> device, where each StreamID points at a different context (and therefore
> address space) makes much sense. It also doesn't solve the more general
> problem where StreamIDs for a device might have different SMMUs downstream.
> 
> To solve this, I think it is better to treat the device as having multiple
> struct device instances, and managing the mappings in the device driver.

Ok.

> For most devices, I'd expect a single context to be enough. This is
> certainly the case for device virtualisation at stage-2 and DMA at stage-1.

Yep, that's the usual case.
(Just thought what other scenarios there are.)

So the DT binding is for the most common (single-context) use case only.
(And everything else needs special device driver treatment.)

> > I also think that it is more useful to move the stream-id property to
> > the device node of a master device. (It's a characteristic of the
> > master device not of the SMMU.) Currently with multiple stream IDs per
> > master device you have repeated entries in the mmu-master property.
> 
> The problem with that approach is how to handle StreamID remastering. This
> can and will happen, so the StreamID for a device is actually a property of
> both the device *and* a particular point in the bus topology. Putting this
> information in the device nodes will drag topology information all over the
> place and I don't think it will make things clearer to read or easier to parse.

Ok, good point, didn't think about that.
And agreed, adding remastered StreamIDs as a property to a device node is odd.

> > But all that is needed is to point (once) to each mmu-master in the
> > SMMU device node. Then you should be able to look up the corresponding
> > stream IDs in the device node for each mmu-master.
> 
> Again, you also need to tie in topology information if you go down this
> route.


Thanks,
Andreas


From rjw at sisk.pl  Mon May 13 06:51:48 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Mon, 13 May 2013 12:51:48 +0200
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <CAKohpomV9-JEbuHWdmp6N+bKYt+83hXXcqg4aKXSY1a5zwpW9Q@mail.gmail.com>
References: <cover.1365079581.git.viresh.kumar@linaro.org>
 <5176A807.2090005@samsung.com>
 <CAKohpomV9-JEbuHWdmp6N+bKYt+83hXXcqg4aKXSY1a5zwpW9Q@mail.gmail.com>
Message-ID: <105283277.osOpfTKkgk@vostro.rjw.lan>

On Monday, May 13, 2013 11:35:22 AM Viresh Kumar wrote:
> On 23 April 2013 20:55, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > On 04/05/13 20:36, Rafael J. Wysocki wrote:
> >>
> >> On Friday, April 05, 2013 12:36:34 PM Viresh Kumar wrote:
> >>>
> >>> On 5 April 2013 12:18, Kukjin Kim<kgene.kim at samsung.com>  wrote:
> >>>>
> >>>> Basically, this moving looks good to me, but should be re-worked based
> >>>> on
> >>>> for-next of samsung tree because this touches too many samsung stuff so
> >>>> this
> >>>> should be sent to upstream via samsung tree.
> >>>
> >>>
> >>> Hmm... Its already applied in Rafael's tree. But it doesn't mean that
> >>> it can't be
> >>> moved to your tree if there is a issue.
> >>
> >>
> >> Well, I'm dropping it.  Please merge via the Samsung tree.
> >>
> >
> > Oops, I missed, maybe I have no more chance to send this to upstream for
> > upcoming merge window :-(
> >
> > Rafael, please take this patch with my ack in your tree, sorry for noise.
> >
> > Acked-by: Kukjin Kim <kgene.kim at samsung.com>
> >
> > If any problems, please kindly let me know.
> 
> Who is going to pick this patch now for next merge window?

That doesn't matter I suppose.  I can take it, but please rebase it on top
of current linux-next.

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From lee.jones at linaro.org  Mon May 13 06:44:48 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 13 May 2013 11:44:48 +0100
Subject: [PATCH] mfd: ab8500-sysctrl: Always enable pm_power_off handler
In-Reply-To: <1368097688-17858-1-git-send-email-fabio.baltieri@linaro.org>
References: <1368097688-17858-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <20130513104448.GB3297@gmail.com>

On Thu, 09 May 2013, Fabio Baltieri wrote:

> AB8500 sysctrl driver implements a pm_power_off handler, but that is
> currently not registered until a specific platform data field is
> enabled.
> 
> This patch drops the platform data field and always registers
> ab8500_power_off if no other pm_power_off handler was defined before,
> and also introduces the necessary cleanup code in the driver's remove
> function.
> 
> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> ---
>  drivers/mfd/ab8500-sysctrl.c      | 6 +++++-
>  include/linux/mfd/abx500/ab8500.h | 2 --
>  2 files changed, 5 insertions(+), 3 deletions(-)

The code looks good to me, but I'd like Linus' or Mattias' Ack before
I apply it.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From viresh.kumar at linaro.org  Mon May 13 06:46:30 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 13 May 2013 16:16:30 +0530
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <105283277.osOpfTKkgk@vostro.rjw.lan>
References: <cover.1365079581.git.viresh.kumar@linaro.org>
 <5176A807.2090005@samsung.com>
 <CAKohpomV9-JEbuHWdmp6N+bKYt+83hXXcqg4aKXSY1a5zwpW9Q@mail.gmail.com>
 <105283277.osOpfTKkgk@vostro.rjw.lan>
Message-ID: <CAKohponkFB7ND38jv5oGnQLx8cq0b=uHTCmL3EERe6P54ijYhw@mail.gmail.com>

On 13 May 2013 16:21, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> That doesn't matter I suppose.  I can take it, but please rebase it on top
> of current linux-next.

I have already done that (attached). But i wasn't sure what Kukjin wants as
he may report conflicts again and i will ask the same question for 3.12 :)

--
viresh
-------------- next part --------------
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From hdoyu at nvidia.com  Mon May 13 07:06:59 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:06:59 +0300
Subject: [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines
Message-ID: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>

This patchset converts device tree files to use CLK defines.

This is against Stephen Warren's linux-next_common branch in:

  git://nv-tegra.nvidia.com/user/swarren/linux-2.6

If this is ok, I'll also convert enum variables to use CLK defines in
drivers/clk/tegra/clk-tegra{20,30,114}.c

Hiroshi Doyu (6):
  ARM: tegra20: create a DT header defining CLK IDs
  ARM: tegra20: convert device tree files to use CLK defines
  ARM: tegra30: create a DT header defining CLK IDs
  ARM: tegra30: convert device tree files to use CLK defines
  ARM: tegra114: create a DT header defining CLK IDs
  ARM: tegra114: convert device tree files to use CLK defines

 .../bindings/clock/nvidia,tegra114-car.txt         | 250 +--------------
 .../bindings/clock/nvidia,tegra20-car.txt          | 152 +--------
 .../bindings/clock/nvidia,tegra30-car.txt          | 209 +------------
 arch/arm/boot/dts/tegra114-dalmore.dts             |   4 +-
 arch/arm/boot/dts/tegra114.dtsi                    |  79 ++---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi         |   4 +-
 arch/arm/boot/dts/tegra20-harmony.dts              |   4 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts          |   4 +-
 arch/arm/boot/dts/tegra20-paz00.dts                |   7 +-
 arch/arm/boot/dts/tegra20-plutux.dts               |   4 +-
 arch/arm/boot/dts/tegra20-seaboard.dts             |   4 +-
 arch/arm/boot/dts/tegra20-tec.dts                  |   4 +-
 arch/arm/boot/dts/tegra20-trimslice.dts            |   4 +-
 arch/arm/boot/dts/tegra20-ventana.dts              |   4 +-
 arch/arm/boot/dts/tegra20-whistler.dts             |   4 +-
 arch/arm/boot/dts/tegra20.dtsi                     | 103 ++++---
 arch/arm/boot/dts/tegra30-beaver.dts               |   4 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |   4 +-
 arch/arm/boot/dts/tegra30.dtsi                     | 110 ++++---
 include/dt-bindings/clk/tegra114-car.h             | 342 +++++++++++++++++++++
 include/dt-bindings/clk/tegra20-car.h              | 158 ++++++++++
 include/dt-bindings/clk/tegra30-car.h              | 265 ++++++++++++++++
 22 files changed, 979 insertions(+), 744 deletions(-)
 create mode 100644 include/dt-bindings/clk/tegra114-car.h
 create mode 100644 include/dt-bindings/clk/tegra20-car.h
 create mode 100644 include/dt-bindings/clk/tegra30-car.h

-- 
1.8.1.5



From hdoyu at nvidia.com  Mon May 13 07:07:00 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:07:00 +0300
Subject: [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
In-Reply-To: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1368443225-16978-2-git-send-email-hdoyu@nvidia.com>

To replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 .../bindings/clock/nvidia,tegra20-car.txt          | 152 +-------------------
 include/dt-bindings/clk/tegra20-car.h              | 158 +++++++++++++++++++++
 2 files changed, 161 insertions(+), 149 deletions(-)
 create mode 100644 include/dt-bindings/clk/tegra20-car.h

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index e885680..edc30f6 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -3,6 +3,8 @@ NVIDIA Tegra20 Clock And Reset Controller
 This binding uses the common clock binding:
 Documentation/devicetree/bindings/clock/clock-bindings.txt
 
+You can find the actual assignment in "dt-bindings/clk/tegra20-car.h"
+
 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
 for muxing and gating Tegra's clocks, and setting their rates.
 
@@ -14,154 +16,6 @@ Required properties :
 - #clock-cells : Should be 1.
   In clock consumers, this cell represents the clock ID exposed by the CAR.
 
-  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 95 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-
-  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
-  above.
-
-  0	cpu
-  1	unassigned
-  2	unassigned
-  3	ac97
-  4	rtc
-  5	tmr
-  6	uart1
-  7	unassigned	(register bit affects uart2 and vfir)
-  8	gpio
-  9	sdmmc2
-  10	unassigned	(register bit affects spdif_in and spdif_out)
-  11	i2s1
-  12	i2c1
-  13	ndflash
-  14	sdmmc1
-  15	sdmmc4
-  16	twc
-  17	pwm
-  18	i2s2
-  19	epp
-  20	unassigned	(register bit affects vi and vi_sensor)
-  21	2d
-  22	usbd
-  23	isp
-  24	3d
-  25	ide
-  26	disp2
-  27	disp1
-  28	host1x
-  29	vcp
-  30	unassigned
-  31	cache2
-
-  32	mem
-  33	ahbdma
-  34	apbdma
-  35	unassigned
-  36	kbc
-  37	stat_mon
-  38	pmc
-  39	fuse
-  40	kfuse
-  41	sbc1
-  42	snor
-  43	spi1
-  44	sbc2
-  45	xio
-  46	sbc3
-  47	dvc
-  48	dsi
-  49	unassigned	(register bit affects tvo and cve)
-  50	mipi
-  51	hdmi
-  52	csi
-  53	tvdac
-  54	i2c2
-  55	uart3
-  56	unassigned
-  57	emc
-  58	usb2
-  59	usb3
-  60	mpe
-  61	vde
-  62	bsea
-  63	bsev
-
-  64	speedo
-  65	uart4
-  66	uart5
-  67	i2c3
-  68	sbc4
-  69	sdmmc3
-  70	pcie
-  71	owr
-  72	afi
-  73	csite
-  74	unassigned
-  75	avpucq
-  76	la
-  77	unassigned
-  78	unassigned
-  79	unassigned
-  80	unassigned
-  81	unassigned
-  82	unassigned
-  83	unassigned
-  84	irama
-  85	iramb
-  86	iramc
-  87	iramd
-  88	cram2
-  89	audio_2x	a/k/a audio_2x_sync_clk
-  90	clk_d
-  91	unassigned
-  92	sus
-  93	cdev2
-  94	cdev1
-  95	unassigned
-
-  96	uart2
-  97	vfir
-  98	spdif_in
-  99	spdif_out
-  100	vi
-  101	vi_sensor
-  102	tvo
-  103	cve
-  104	osc
-  105	clk_32k		a/k/a clk_s
-  106	clk_m
-  107	sclk
-  108	cclk
-  109	hclk
-  110	pclk
-  111	blink
-  112	pll_a
-  113	pll_a_out0
-  114	pll_c
-  115	pll_c_out1
-  116	pll_d
-  117	pll_d_out0
-  118	pll_e
-  119	pll_m
-  120	pll_m_out1
-  121	pll_p
-  122	pll_p_out1
-  123	pll_p_out2
-  124	pll_p_out3
-  125	pll_p_out4
-  126	pll_s
-  127	pll_u
-  128	pll_x
-  129	cop		a/k/a avp
-  130	audio		a/k/a audio_sync_clk
-  131	pll_ref
-  132	twd
-
 Example SoC include file:
 
 / {
@@ -172,7 +26,7 @@ Example SoC include file:
 	};
 
 	usb at c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car TEGRA20_CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/include/dt-bindings/clk/tegra20-car.h b/include/dt-bindings/clk/tegra20-car.h
new file mode 100644
index 0000000..e30b4bd
--- /dev/null
+++ b/include/dt-bindings/clk/tegra20-car.h
@@ -0,0 +1,158 @@
+/*
+ * This header provides constants for binding nvidia,tegra20-car.
+ *
+ * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 95 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLK_TEGRA20_CAR_H
+#define _DT_BINDINGS_CLK_TEGRA20_CAR_H
+
+#define TEGRA20_CLK_CPU 0
+/* 1 */
+/* 2 */
+#define TEGRA20_CLK_AC97 3
+#define TEGRA20_CLK_RTC 4
+#define TEGRA20_CLK_TIMER 5
+#define TEGRA20_CLK_UARTA 6
+/* 7 (register bit affects uart2 and vfir) */
+#define TEGRA20_CLK_GPIO 8
+#define TEGRA20_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA20_CLK_I2S1 11
+#define TEGRA20_CLK_I2C1 12
+#define TEGRA20_CLK_NDFLASH 13
+#define TEGRA20_CLK_SDMMC1 14
+#define TEGRA20_CLK_SDMMC4 15
+#define TEGRA20_CLK_TWC 16
+#define TEGRA20_CLK_PWM 17
+#define TEGRA20_CLK_I2S2 18
+#define TEGRA20_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA20_CLK_GR2D 21
+#define TEGRA20_CLK_USBD 22
+#define TEGRA20_CLK_ISP 23
+#define TEGRA20_CLK_GR3D 24
+#define TEGRA20_CLK_IDE 25
+#define TEGRA20_CLK_DISP2 26
+#define TEGRA20_CLK_DISP1 27
+#define TEGRA20_CLK_HOST1X 28
+#define TEGRA20_CLK_VCP 29
+/* 30 */
+#define TEGRA20_CLK_CACHE2 31
+
+#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_AHBDMA 33
+#define TEGRA20_CLK_APBDMA 34
+/* 35 */
+#define TEGRA20_CLK_KBC 36
+#define TEGRA20_CLK_STAT_MON 37
+#define TEGRA20_CLK_PMC 38
+#define TEGRA20_CLK_FUSE 39
+#define TEGRA20_CLK_KFUSE 40
+#define TEGRA20_CLK_SBC1 41
+#define TEGRA20_CLK_NOR 42
+#define TEGRA20_CLK_SPI 43
+#define TEGRA20_CLK_SBC2 44
+#define TEGRA20_CLK_XIO 45
+#define TEGRA20_CLK_SBC3 46
+#define TEGRA20_CLK_DVC 47
+#define TEGRA20_CLK_DSI 48
+/* 49 (register bit affects tvo and cve) */
+#define TEGRA20_CLK_MIPI 50
+#define TEGRA20_CLK_HDMI 51
+#define TEGRA20_CLK_CSI 52
+#define TEGRA20_CLK_TVDAC 53
+#define TEGRA20_CLK_I2C2 54
+#define TEGRA20_CLK_UARTC 55
+/* 56 */
+#define TEGRA20_CLK_EMC 57
+#define TEGRA20_CLK_USB2 58
+#define TEGRA20_CLK_USB3 59
+#define TEGRA20_CLK_MPE 60
+#define TEGRA20_CLK_VDE 61
+#define TEGRA20_CLK_BSEA 62
+#define TEGRA20_CLK_BSEV 63
+
+#define TEGRA20_CLK_SPEEDO 64
+#define TEGRA20_CLK_UARTD 65
+#define TEGRA20_CLK_UARTE 66
+#define TEGRA20_CLK_I2C3 67
+#define TEGRA20_CLK_SBC4 68
+#define TEGRA20_CLK_SDMMC3 69
+#define TEGRA20_CLK_PEX 70
+#define TEGRA20_CLK_OWR 71
+#define TEGRA20_CLK_AFI 72
+#define TEGRA20_CLK_CSITE 73
+#define TEGRA20_CLK_PCIE_XCLK 74
+#define TEGRA20_CLK_AVPUCQ 75
+#define TEGRA20_CLK_LA 76
+/* 77 */
+/* 78 */
+/* 79 */
+/* 80 */
+/* 81 */
+/* 82 */
+/* 83 */
+#define TEGRA20_CLK_IRAMA 84
+#define TEGRA20_CLK_IRAMB 85
+#define TEGRA20_CLK_IRAMC 86
+#define TEGRA20_CLK_IRAMD 87
+#define TEGRA20_CLK_CRAM2 88
+#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
+#define TEGRA20_CLK_CLK_D 90
+/* 91 */
+#define TEGRA20_CLK_CSUS 92
+#define TEGRA20_CLK_CDEV2 93
+#define TEGRA20_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA20_CLK_UARTB 96
+#define TEGRA20_CLK_VFIR 97
+#define TEGRA20_CLK_SPDIF_IN 98
+#define TEGRA20_CLK_SPDIF_OUT 99
+#define TEGRA20_CLK_VI 100
+#define TEGRA20_CLK_VI_SENSOR 101
+#define TEGRA20_CLK_TVO 102
+#define TEGRA20_CLK_CVE 103
+#define TEGRA20_CLK_OSC 104
+#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
+#define TEGRA20_CLK_CLK_M 106
+#define TEGRA20_CLK_SCLK 107
+#define TEGRA20_CLK_CCLK 108
+#define TEGRA20_CLK_HCLK 109
+#define TEGRA20_CLK_PCLK 110
+#define TEGRA20_CLK_BLINK 111
+#define TEGRA20_CLK_PLL_A 112
+#define TEGRA20_CLK_PLL_A_OUT0 113
+#define TEGRA20_CLK_PLL_C 114
+#define TEGRA20_CLK_PLL_C_OUT1 115
+#define TEGRA20_CLK_PLL_D 116
+#define TEGRA20_CLK_PLL_D_OUT0 117
+#define TEGRA20_CLK_PLL_E 118
+#define TEGRA20_CLK_PLL_M 119
+#define TEGRA20_CLK_PLL_M_OUT1 120
+#define TEGRA20_CLK_PLL_P 121
+#define TEGRA20_CLK_PLL_P_OUT1 122
+#define TEGRA20_CLK_PLL_P_OUT2 123
+#define TEGRA20_CLK_PLL_P_OUT3 124
+#define TEGRA20_CLK_PLL_P_OUT4 125
+#define TEGRA20_CLK_PLL_S 126
+#define TEGRA20_CLK_PLL_U 127
+
+#define TEGRA20_CLK_PLL_X 128
+#define TEGRA20_CLK_COP 129 /* a/k/a avp */
+#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
+#define TEGRA20_CLK_PLL_REF 131
+#define TEGRA20_CLK_TWD 132
+#define TEGRA20_CLK_CLK_MAX 133
+
+#endif	/* _DT_BINDINGS_CLK_TEGRA20_CAR_H */
-- 
1.8.1.5



From hdoyu at nvidia.com  Mon May 13 07:07:02 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:07:02 +0300
Subject: [PATCH 3/6] ARM: tegra30: create a DT header defining CLK IDs
In-Reply-To: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1368443225-16978-4-git-send-email-hdoyu@nvidia.com>

To replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 .../bindings/clock/nvidia,tegra30-car.txt          | 209 +---------------
 include/dt-bindings/clk/tegra30-car.h              | 265 +++++++++++++++++++++
 2 files changed, 268 insertions(+), 206 deletions(-)
 create mode 100644 include/dt-bindings/clk/tegra30-car.h

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index f3da3be..10e1700 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -3,6 +3,8 @@ NVIDIA Tegra30 Clock And Reset Controller
 This binding uses the common clock binding:
 Documentation/devicetree/bindings/clock/clock-bindings.txt
 
+You can find the actual assignment in "dt-bindings/clk/tegra30-car.h"
+
 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
 for muxing and gating Tegra's clocks, and setting their rates.
 
@@ -14,211 +16,6 @@ Required properties :
 - #clock-cells : Should be 1.
   In clock consumers, this cell represents the clock ID exposed by the CAR.
 
-  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-
-  0	cpu
-  1	unassigned
-  2	unassigned
-  3	unassigned
-  4	rtc
-  5	timer
-  6	uarta
-  7	unassigned	(register bit affects uartb and vfir)
-  8	gpio
-  9	sdmmc2
-  10	unassigned	(register bit affects spdif_in and spdif_out)
-  11	i2s1
-  12	i2c1
-  13	ndflash
-  14	sdmmc1
-  15	sdmmc4
-  16	unassigned
-  17	pwm
-  18	i2s2
-  19	epp
-  20	unassigned	(register bit affects vi and vi_sensor)
-  21	2d
-  22	usbd
-  23	isp
-  24	3d
-  25	unassigned
-  26	disp2
-  27	disp1
-  28	host1x
-  29	vcp
-  30	i2s0
-  31	cop_cache
-
-  32	mc
-  33	ahbdma
-  34	apbdma
-  35	unassigned
-  36	kbc
-  37	statmon
-  38	pmc
-  39	unassigned	(register bit affects fuse and fuse_burn)
-  40	kfuse
-  41	sbc1
-  42	nor
-  43	unassigned
-  44	sbc2
-  45	unassigned
-  46	sbc3
-  47	i2c5
-  48	dsia
-  49	unassigned	(register bit affects cve and tvo)
-  50	mipi
-  51	hdmi
-  52	csi
-  53	tvdac
-  54	i2c2
-  55	uartc
-  56	unassigned
-  57	emc
-  58	usb2
-  59	usb3
-  60	mpe
-  61	vde
-  62	bsea
-  63	bsev
-
-  64	speedo
-  65	uartd
-  66	uarte
-  67	i2c3
-  68	sbc4
-  69	sdmmc3
-  70	pcie
-  71	owr
-  72	afi
-  73	csite
-  74	pciex
-  75	avpucq
-  76	la
-  77	unassigned
-  78	unassigned
-  79	dtv
-  80	ndspeed
-  81	i2cslow
-  82	dsib
-  83	unassigned
-  84	irama
-  85	iramb
-  86	iramc
-  87	iramd
-  88	cram2
-  89	unassigned
-  90	audio_2x	a/k/a audio_2x_sync_clk
-  91	unassigned
-  92	csus
-  93	cdev2
-  94	cdev1
-  95	unassigned
-
-  96	cpu_g
-  97	cpu_lp
-  98	3d2
-  99	mselect
-  100	tsensor
-  101	i2s3
-  102	i2s4
-  103	i2c4
-  104	sbc5
-  105	sbc6
-  106	d_audio
-  107	apbif
-  108	dam0
-  109	dam1
-  110	dam2
-  111	hda2codec_2x
-  112	atomics
-  113	audio0_2x
-  114	audio1_2x
-  115	audio2_2x
-  116	audio3_2x
-  117	audio4_2x
-  118	audio5_2x
-  119	actmon
-  120	extern1
-  121	extern2
-  122	extern3
-  123	sata_oob
-  124	sata
-  125	hda
-  127	se
-  128	hda2hdmi
-  129	sata_cold
-
-  160	uartb
-  161	vfir
-  162	spdif_in
-  163	spdif_out
-  164	vi
-  165	vi_sensor
-  166	fuse
-  167	fuse_burn
-  168	cve
-  169	tvo
-
-  170	clk_32k
-  171	clk_m
-  172	clk_m_div2
-  173	clk_m_div4
-  174	pll_ref
-  175	pll_c
-  176	pll_c_out1
-  177	pll_m
-  178	pll_m_out1
-  179	pll_p
-  180	pll_p_out1
-  181	pll_p_out2
-  182	pll_p_out3
-  183	pll_p_out4
-  184	pll_a
-  185	pll_a_out0
-  186	pll_d
-  187	pll_d_out0
-  188	pll_d2
-  189	pll_d2_out0
-  190	pll_u
-  191	pll_x
-  192	pll_x_out0
-  193	pll_e
-  194	spdif_in_sync
-  195	i2s0_sync
-  196	i2s1_sync
-  197	i2s2_sync
-  198	i2s3_sync
-  199	i2s4_sync
-  200	vimclk
-  201	audio0
-  202	audio1
-  203	audio2
-  204	audio3
-  205	audio4
-  206	audio5
-  207	clk_out_1 (extern1)
-  208	clk_out_2 (extern2)
-  209	clk_out_3 (extern3)
-  210	sclk
-  211	blink
-  212	cclk_g
-  213	cclk_lp
-  214	twd
-  215	cml0
-  216	cml1
-  217	hclk
-  218	pclk
-
 Example SoC include file:
 
 / {
@@ -229,7 +26,7 @@ Example SoC include file:
 	};
 
 	usb at c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car TEGRA30_CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/include/dt-bindings/clk/tegra30-car.h b/include/dt-bindings/clk/tegra30-car.h
new file mode 100644
index 0000000..594f61e
--- /dev/null
+++ b/include/dt-bindings/clk/tegra30-car.h
@@ -0,0 +1,265 @@
+/*
+ * This header provides constants for binding nvidia,tegra30-car.
+ *
+ * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLK_TEGRA30_CAR_H
+#define _DT_BINDINGS_CLK_TEGRA30_CAR_H
+
+#define TEGRA30_CLK_CPU 0
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA30_CLK_RTC 4
+#define TEGRA30_CLK_TIMER 5
+#define TEGRA30_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA30_CLK_GPIO 8
+#define TEGRA30_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA30_CLK_I2S1 11
+#define TEGRA30_CLK_I2C1 12
+#define TEGRA30_CLK_NDFLASH 13
+#define TEGRA30_CLK_SDMMC1 14
+#define TEGRA30_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA30_CLK_PWM 17
+#define TEGRA30_CLK_I2S2 18
+#define TEGRA30_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA30_CLK_GR2D 21
+#define TEGRA30_CLK_USBD 22
+#define TEGRA30_CLK_ISP 23
+#define TEGRA30_CLK_GR3D 24
+/* 25 */
+#define TEGRA30_CLK_DISP2 26
+#define TEGRA30_CLK_DISP1 27
+#define TEGRA30_CLK_HOST1X 28
+#define TEGRA30_CLK_VCP 29
+#define TEGRA30_CLK_I2S0 30
+#define TEGRA30_CLK_COP_CACHE 31
+
+#define TEGRA30_CLK_MC 32
+#define TEGRA30_CLK_AHBDMA 33
+#define TEGRA30_CLK_APBDMA 34
+/* 35 */
+#define TEGRA30_CLK_KBC 36
+#define TEGRA30_CLK_STATMON 37
+#define TEGRA30_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA30_CLK_KFUSE 40
+#define TEGRA30_CLK_SBC1 41
+#define TEGRA30_CLK_NOR 42
+/* 43 */
+#define TEGRA30_CLK_SBC2 44
+/* 45 */
+#define TEGRA30_CLK_SBC3 46
+#define TEGRA30_CLK_I2C5 47
+#define TEGRA30_CLK_DSIA 48
+/* 49 (register bit affects cve and tvo) */
+#define TEGRA30_CLK_MIPI 50
+#define TEGRA30_CLK_HDMI 51
+#define TEGRA30_CLK_CSI 52
+#define TEGRA30_CLK_TVDAC 53
+#define TEGRA30_CLK_I2C2 54
+#define TEGRA30_CLK_UARTC 55
+/* 56 */
+#define TEGRA30_CLK_EMC 57
+#define TEGRA30_CLK_USB2 58
+#define TEGRA30_CLK_USB3 59
+#define TEGRA30_CLK_MPE 60
+#define TEGRA30_CLK_VDE 61
+#define TEGRA30_CLK_BSEA 62
+#define TEGRA30_CLK_BSEV 63
+
+#define TEGRA30_CLK_SPEEDO 64
+#define TEGRA30_CLK_UARTD 65
+#define TEGRA30_CLK_UARTE 66
+#define TEGRA30_CLK_I2C3 67
+#define TEGRA30_CLK_SBC4 68
+#define TEGRA30_CLK_SDMMC3 69
+#define TEGRA30_CLK_PCIE 70
+#define TEGRA30_CLK_OWR 71
+#define TEGRA30_CLK_AFI 72
+#define TEGRA30_CLK_CSITE 73
+#define TEGRA30_CLK_PCIEX 74
+#define TEGRA30_CLK_AVPUCQ 75
+#define TEGRA30_CLK_LA 76
+/* 77 */
+/* 78 */
+#define TEGRA30_CLK_DTV 79
+#define TEGRA30_CLK_NDSPEED 80
+#define TEGRA30_CLK_I2CSLOW 81
+#define TEGRA30_CLK_DSIB 82
+/* 83 */
+#define TEGRA30_CLK_IRAMA 84
+#define TEGRA30_CLK_IRAMB 85
+#define TEGRA30_CLK_IRAMC 86
+#define TEGRA30_CLK_IRAMD 87
+#define TEGRA30_CLK_CRAM2 88
+/* 89 */
+#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
+/* 91 */
+#define TEGRA30_CLK_CSUS 92
+#define TEGRA30_CLK_CDEV2 93
+#define TEGRA30_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA30_CLK_CPU_G 96
+#define TEGRA30_CLK_CPU_LP 97
+#define TEGRA30_CLK_GR3D2 98
+#define TEGRA30_CLK_MSELECT 99
+#define TEGRA30_CLK_TSENSOR 100
+#define TEGRA30_CLK_I2S3 101
+#define TEGRA30_CLK_I2S4 102
+#define TEGRA30_CLK_I2C4 103
+#define TEGRA30_CLK_SBC5 104
+#define TEGRA30_CLK_SBC6 105
+#define TEGRA30_CLK_D_AUDIO 106
+#define TEGRA30_CLK_APBIF 107
+#define TEGRA30_CLK_DAM0 108
+#define TEGRA30_CLK_DAM1 109
+#define TEGRA30_CLK_DAM2 110
+#define TEGRA30_CLK_HDA2CODEC_2X 111
+#define TEGRA30_CLK_ATOMICS 112
+#define TEGRA30_CLK_AUDIO0_2X 113
+#define TEGRA30_CLK_AUDIO1_2X 114
+#define TEGRA30_CLK_AUDIO2_2X 115
+#define TEGRA30_CLK_AUDIO3_2X 116
+#define TEGRA30_CLK_AUDIO4_2X 117
+#define TEGRA30_CLK_SPDIF_2X 118
+#define TEGRA30_CLK_ACTMON 119
+#define TEGRA30_CLK_EXTERN1 120
+#define TEGRA30_CLK_EXTERN2 121
+#define TEGRA30_CLK_EXTERN3 122
+#define TEGRA30_CLK_SATA_OOB 123
+#define TEGRA30_CLK_SATA 124
+#define TEGRA30_CLK_HDA 125
+/* 126 */
+#define TEGRA30_CLK_SE 127
+
+#define TEGRA30_CLK_HDA2HDMI 128
+#define TEGRA30_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 */
+/* 144 */
+/* 145 */
+/* 146 */
+/* 147 */
+/* 148 */
+/* 149 */
+/* 150 */
+/* 151 */
+/* 152 */
+/* 153 */
+/* 154 */
+/* 155 */
+/* 156 */
+/* 157 */
+/* 158 */
+/* 159 */
+
+#define TEGRA30_CLK_UARTB 160
+#define TEGRA30_CLK_VFIR 161
+#define TEGRA30_CLK_SPDIF_IN 162
+#define TEGRA30_CLK_SPDIF_OUT 163
+#define TEGRA30_CLK_VI 164
+#define TEGRA30_CLK_VI_SENSOR 165
+#define TEGRA30_CLK_FUSE 166
+#define TEGRA30_CLK_FUSE_BURN 167
+#define TEGRA30_CLK_CVE 168
+#define TEGRA30_CLK_TVO 169
+#define TEGRA30_CLK_CLK_32K 170
+#define TEGRA30_CLK_CLK_M 171
+#define TEGRA30_CLK_CLK_M_DIV2 172
+#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_PLL_REF 174
+#define TEGRA30_CLK_PLL_C 175
+#define TEGRA30_CLK_PLL_C_OUT1 176
+#define TEGRA30_CLK_PLL_M 177
+#define TEGRA30_CLK_PLL_M_OUT1 178
+#define TEGRA30_CLK_PLL_P 179
+#define TEGRA30_CLK_PLL_P_OUT1 180
+#define TEGRA30_CLK_PLL_P_OUT2 181
+#define TEGRA30_CLK_PLL_P_OUT3 182
+#define TEGRA30_CLK_PLL_P_OUT4 183
+#define TEGRA30_CLK_PLL_A 184
+#define TEGRA30_CLK_PLL_A_OUT0 185
+#define TEGRA30_CLK_PLL_D 186
+#define TEGRA30_CLK_PLL_D_OUT0 187
+#define TEGRA30_CLK_PLL_D2 188
+#define TEGRA30_CLK_PLL_D2_OUT0 189
+#define TEGRA30_CLK_PLL_U 190
+#define TEGRA30_CLK_PLL_X 191
+
+#define TEGRA30_CLK_PLL_X_OUT0 192
+#define TEGRA30_CLK_PLL_E 193
+#define TEGRA30_CLK_SPDIF_IN_SYNC 194
+#define TEGRA30_CLK_I2S0_SYNC 195
+#define TEGRA30_CLK_I2S1_SYNC 196
+#define TEGRA30_CLK_I2S2_SYNC 197
+#define TEGRA30_CLK_I2S3_SYNC 198
+#define TEGRA30_CLK_I2S4_SYNC 199
+#define TEGRA30_CLK_VIMCLK_SYNC 200
+#define TEGRA30_CLK_AUDIO0 201
+#define TEGRA30_CLK_AUDIO1 202
+#define TEGRA30_CLK_AUDIO2 203
+#define TEGRA30_CLK_AUDIO3 204
+#define TEGRA30_CLK_AUDIO4 205
+#define TEGRA30_CLK_SPDIF 206
+#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
+#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
+#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+#define TEGRA30_CLK_SCLK 210
+#define TEGRA30_CLK_BLINK 211
+#define TEGRA30_CLK_CCLK_G 212
+#define TEGRA30_CLK_CCLK_LP 213
+#define TEGRA30_CLK_TWD 214
+#define TEGRA30_CLK_CML0 215
+#define TEGRA30_CLK_CML1 216
+#define TEGRA30_CLK_HCLK 217
+#define TEGRA30_CLK_PCLK 218
+/* 219 */
+/* 220 */
+/* 221 */
+/* 222 */
+/* 223 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA30_CLK_CLK_OUT_1_MUX 300
+#define TEGRA30_CLK_CLK_MAX 301
+
+#endif	/* _DT_BINDINGS_CLK_TEGRA30_CAR_H */
-- 
1.8.1.5



From hdoyu at nvidia.com  Mon May 13 07:07:01 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:07:01 +0300
Subject: [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK defines
In-Reply-To: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1368443225-16978-3-git-send-email-hdoyu@nvidia.com>

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |   4 +-
 arch/arm/boot/dts/tegra20-harmony.dts      |   4 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |   4 +-
 arch/arm/boot/dts/tegra20-paz00.dts        |   7 +-
 arch/arm/boot/dts/tegra20-plutux.dts       |   4 +-
 arch/arm/boot/dts/tegra20-seaboard.dts     |   4 +-
 arch/arm/boot/dts/tegra20-tec.dts          |   4 +-
 arch/arm/boot/dts/tegra20-trimslice.dts    |   4 +-
 arch/arm/boot/dts/tegra20-ventana.dts      |   4 +-
 arch/arm/boot/dts/tegra20-whistler.dts     |   4 +-
 arch/arm/boot/dts/tegra20.dtsi             | 103 ++++++++++++++++-------------
 11 files changed, 89 insertions(+), 57 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index be008f7..7e1b120 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -487,7 +487,9 @@
 
 		nvidia,ac97-controller = <&ac97>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index acbba40..ba2a269 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -693,7 +693,9 @@
 		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
 			GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 85d5792..7599993 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -59,7 +59,9 @@
 		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 66f245a..02a5ace 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -277,7 +277,8 @@
 		clock-frequency = <80000>;
 		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 	};
 
@@ -526,7 +527,9 @@
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
 			GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 3374e16..4277552 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -53,7 +53,9 @@
 		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 4d52f64e..6f0d982 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -833,7 +833,9 @@
 		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9eaa962..b90a70e 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -54,7 +54,9 @@
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
 			GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index e6200cf..2a0ac6f 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -408,7 +408,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&codec>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 33ec764..5e5a690 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -645,7 +645,9 @@
 		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
 			GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d6cb373..3dfec0b 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -584,7 +584,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&codec>;
 
-		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0500179..f302ef8 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clk/tegra20-car.h>
 
 #include "skeleton.dtsi"
 
@@ -20,7 +21,7 @@
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car 28>;
+		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -31,48 +32,49 @@
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 60>;
+			clocks = <&tegra_car TEGRA20_CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 100>;
+			clocks = <&tegra_car TEGRA20_CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 19>;
+			clocks = <&tegra_car TEGRA20_CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 23>;
+			clocks = <&tegra_car TEGRA20_CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 21>;
+			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car 24>;
+			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 		};
 
 		dc at 54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 27>, <&tegra_car 121>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+			       	 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
 
 			rgb {
@@ -84,7 +86,8 @@
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 26>, <&tegra_car 121>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+			       	 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
 
 			rgb {
@@ -96,7 +99,8 @@
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 51>, <&tegra_car 117>;
+			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+			       	 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
@@ -105,14 +109,14 @@
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car TEGRA20_CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car 48>;
+			clocks = <&tegra_car TEGRA20_CLK_DSI>;
 			status = "disabled";
 		};
 	};
@@ -122,7 +126,7 @@
 		reg = <0x50040600 0x20>;
 		interrupts = <GIC_PPI 13
 			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-		clocks = <&tegra_car 132>;
+		clocks = <&tegra_car TEGRA20_CLK_TWD>;
 	};
 
 	intc: interrupt-controller {
@@ -149,7 +153,7 @@
 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 5>;
+		clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 	};
 
 	tegra_car: clock {
@@ -177,7 +181,7 @@
 			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 	};
 
 	ahb {
@@ -219,7 +223,7 @@
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
-		clocks = <&tegra_car 3>;
+		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		status = "disabled";
 	};
 
@@ -228,7 +232,7 @@
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
-		clocks = <&tegra_car 11>;
+		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		status = "disabled";
 	};
 
@@ -237,7 +241,7 @@
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
-		clocks = <&tegra_car 18>;
+		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		status = "disabled";
 	};
 
@@ -254,7 +258,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		status = "disabled";
 	};
 
@@ -264,7 +268,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		clocks = <&tegra_car 96>;
+		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		status = "disabled";
 	};
 
@@ -274,7 +278,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		status = "disabled";
 	};
 
@@ -284,7 +288,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		status = "disabled";
 	};
 
@@ -294,7 +298,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
-		clocks = <&tegra_car 66>;
+		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		status = "disabled";
 	};
 
@@ -302,7 +306,7 @@
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car TEGRA20_CLK_PWM>;
 		status = "disabled";
 	};
 
@@ -310,7 +314,7 @@
 		compatible = "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
 		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 4>;
+		clocks = <&tegra_car TEGRA20_CLK_RTC>;
 	};
 
 	i2c at 7000c000 {
@@ -319,7 +323,8 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 124>;
+		clocks = <&tegra_car TEGRA20_CLK_I2C1>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -331,7 +336,7 @@
 		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 43>;
+		clocks = <&tegra_car TEGRA20_CLK_SPI>;
 		status = "disabled";
 	};
 
@@ -341,7 +346,8 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>, <&tegra_car 124>;
+		clocks = <&tegra_car TEGRA20_CLK_I2C2>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -352,7 +358,8 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -363,7 +370,8 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>, <&tegra_car 124>;
+		clocks = <&tegra_car TEGRA20_CLK_DVC>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -375,7 +383,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 		status = "disabled";
 	};
 
@@ -386,7 +394,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 		status = "disabled";
 	};
 
@@ -397,7 +405,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 		status = "disabled";
 	};
 
@@ -408,7 +416,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 		status = "disabled";
 	};
 
@@ -416,14 +424,14 @@
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car TEGRA20_CLK_KBC>;
 		status = "disabled";
 	};
 
 	pmc {
 		compatible = "nvidia,tegra20-pmc";
 		reg = <0x7000e400 0x400>;
-		clocks = <&tegra_car 110>, <&clk32k_in>;
+		clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
 	};
 
@@ -453,7 +461,7 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
-		clocks = <&tegra_car 22>;
+		clocks = <&tegra_car TEGRA20_CLK_USBD>;
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -464,7 +472,8 @@
 		reg = <0xc5000400 0x3c00>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
-		clocks = <&tegra_car 22>, <&tegra_car 127>;
+		clocks = <&tegra_car TEGRA20_CLK_USBD>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_U>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -473,7 +482,7 @@
 		reg = <0xc5004000 0x4000>;
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
-		clocks = <&tegra_car 58>;
+		clocks = <&tegra_car TEGRA20_CLK_USB2>;
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -482,7 +491,8 @@
 		compatible = "nvidia,tegra20-usb-phy";
 		reg = <0xc5004400 0x3c00>;
 		phy_type = "ulpi";
-		clocks = <&tegra_car 93>, <&tegra_car 127>;
+		clocks = <&tegra_car TEGRA20_CLK_CDEV2>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_U>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -491,7 +501,7 @@
 		reg = <0xc5008000 0x4000>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
-		clocks = <&tegra_car 59>;
+		clocks = <&tegra_car TEGRA20_CLK_USB3>;
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
@@ -500,7 +510,8 @@
 		compatible = "nvidia,tegra20-usb-phy";
 		reg = <0xc5008400 0x3c00>;
 		phy_type = "utmi";
-		clocks = <&tegra_car 22>, <&tegra_car 127>;
+		clocks = <&tegra_car TEGRA20_CLK_USBD>,
+		       	 <&tegra_car TEGRA20_CLK_PLL_U>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -508,7 +519,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 		status = "disabled";
 	};
 
@@ -516,7 +527,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 		status = "disabled";
 	};
 
@@ -524,7 +535,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 		status = "disabled";
 	};
 
@@ -532,7 +543,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 		status = "disabled";
 	};
 
-- 
1.8.1.5



From hdoyu at nvidia.com  Mon May 13 07:07:03 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:07:03 +0300
Subject: [PATCH 4/6] ARM: tegra30: convert device tree files to use CLK defines
In-Reply-To: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1368443225-16978-5-git-send-email-hdoyu@nvidia.com>

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/boot/dts/tegra30-beaver.dts  |   4 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi |   4 +-
 arch/arm/boot/dts/tegra30.dtsi        | 110 +++++++++++++++++++---------------
 3 files changed, 69 insertions(+), 49 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 9f4b684..5f6dcff 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -413,7 +413,9 @@
 
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA30_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 85f26ba..fc3ffd8 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -534,7 +534,9 @@
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
 			GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA30_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 329465a..fe1904e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clk/tegra30-car.h>
 
 #include "skeleton.dtsi"
 
@@ -20,7 +21,7 @@
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car 28>;
+		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -31,35 +32,35 @@
 			compatible = "nvidia,tegra30-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 60>;
+			clocks = <&tegra_car TEGRA30_CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra30-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 164>;
+			clocks = <&tegra_car TEGRA30_CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra30-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 19>;
+			clocks = <&tegra_car TEGRA30_CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra30-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 23>;
+			clocks = <&tegra_car TEGRA30_CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 21>;
+			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 		};
 
 		gr3d {
@@ -73,7 +74,8 @@
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 27>, <&tegra_car 179>;
+			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+			       	 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
 
 			rgb {
@@ -85,7 +87,8 @@
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 26>, <&tegra_car 179>;
+			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+			       	 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
 
 			rgb {
@@ -97,7 +100,8 @@
 			compatible = "nvidia,tegra30-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 51>, <&tegra_car 189>;
+			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+			       	 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
@@ -106,14 +110,14 @@
 			compatible = "nvidia,tegra30-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 169>;
+			clocks = <&tegra_car TEGRA30_CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car 48>;
+			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 			status = "disabled";
 		};
 	};
@@ -123,7 +127,7 @@
 		reg = <0x50040600 0x20>;
 		interrupts = <GIC_PPI 13
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clocks = <&tegra_car 214>;
+		clocks = <&tegra_car TEGRA30_CLK_TWD>;
 	};
 
 	intc: interrupt-controller {
@@ -152,7 +156,7 @@
 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 5>;
+		clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 	};
 
 	tegra_car: clock {
@@ -196,7 +200,7 @@
 			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 	};
 
 	ahb: ahb {
@@ -241,7 +245,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		status = "disabled";
 	};
 
@@ -251,7 +255,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		clocks = <&tegra_car 160>;
+		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		status = "disabled";
 	};
 
@@ -261,7 +265,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		status = "disabled";
 	};
 
@@ -271,7 +275,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		status = "disabled";
 	};
 
@@ -281,7 +285,7 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
-		clocks = <&tegra_car 66>;
+		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		status = "disabled";
 	};
 
@@ -289,7 +293,7 @@
 		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car TEGRA30_CLK_PWM>;
 		status = "disabled";
 	};
 
@@ -297,7 +301,7 @@
 		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
 		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 4>;
+		clocks = <&tegra_car TEGRA30_CLK_RTC>;
 	};
 
 	i2c at 7000c000 {
@@ -306,7 +310,8 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 182>;
+		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -317,7 +322,8 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>, <&tegra_car 182>;
+		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -328,7 +334,8 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>, <&tegra_car 182>;
+		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -339,7 +346,8 @@
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 103>, <&tegra_car 182>;
+		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -350,7 +358,8 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>, <&tegra_car 182>;
+		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+		       	 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -362,7 +371,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 		status = "disabled";
 	};
 
@@ -373,7 +382,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 		status = "disabled";
 	};
 
@@ -384,7 +393,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 		status = "disabled";
 	};
 
@@ -395,7 +404,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 		status = "disabled";
 	};
 
@@ -406,7 +415,7 @@
 		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 104>;
+		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 		status = "disabled";
 	};
 
@@ -417,7 +426,7 @@
 		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 105>;
+		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 		status = "disabled";
 	};
 
@@ -425,14 +434,14 @@
 		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car TEGRA30_CLK_KBC>;
 		status = "disabled";
 	};
 
 	pmc {
 		compatible = "nvidia,tegra30-pmc";
 		reg = <0x7000e400 0x400>;
-		clocks = <&tegra_car 218>, <&clk32k_in>;
+		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
 	};
 
@@ -461,10 +470,17 @@
 		       0x70080200 0x100>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
-		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-			 <&tegra_car 110>, <&tegra_car 162>;
+		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+		       	 <&tegra_car TEGRA30_CLK_APBIF>,
+			 <&tegra_car TEGRA30_CLK_I2S0>,
+			 <&tegra_car TEGRA30_CLK_I2S1>,
+			 <&tegra_car TEGRA30_CLK_I2S2>,
+			 <&tegra_car TEGRA30_CLK_I2S3>,
+			 <&tegra_car TEGRA30_CLK_I2S4>,
+			 <&tegra_car TEGRA30_CLK_DAM0>,
+			 <&tegra_car TEGRA30_CLK_DAM1>,
+			 <&tegra_car TEGRA30_CLK_DAM2>,
+			 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in";
@@ -476,7 +492,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
-			clocks = <&tegra_car 30>;
+			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 			status = "disabled";
 		};
 
@@ -484,7 +500,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
-			clocks = <&tegra_car 11>;
+			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 			status = "disabled";
 		};
 
@@ -492,7 +508,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
-			clocks = <&tegra_car 18>;
+			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 			status = "disabled";
 		};
 
@@ -500,7 +516,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
-			clocks = <&tegra_car 101>;
+			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 			status = "disabled";
 		};
 
@@ -508,7 +524,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 			status = "disabled";
 		};
 	};
@@ -517,7 +533,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 		status = "disabled";
 	};
 
@@ -525,7 +541,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 		status = "disabled";
 	};
 
@@ -533,7 +549,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 		status = "disabled";
 	};
 
@@ -541,7 +557,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 		status = "disabled";
 	};
 
-- 
1.8.1.5



From hdoyu at nvidia.com  Mon May 13 07:07:04 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:07:04 +0300
Subject: [PATCH 5/6] ARM: tegra114: create a DT header defining CLK IDs
In-Reply-To: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1368443225-16978-6-git-send-email-hdoyu@nvidia.com>

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 .../bindings/clock/nvidia,tegra114-car.txt         | 250 +--------------
 include/dt-bindings/clk/tegra114-car.h             | 342 +++++++++++++++++++++
 2 files changed, 345 insertions(+), 247 deletions(-)
 create mode 100644 include/dt-bindings/clk/tegra114-car.h

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index d6cb083..5177196 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -3,6 +3,8 @@ NVIDIA Tegra114 Clock And Reset Controller
 This binding uses the common clock binding:
 Documentation/devicetree/bindings/clock/clock-bindings.txt
 
+You can find the actual assignment in "dt-bindings/clk/tegra114-car.h"
+
 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
 for muxing and gating Tegra's clocks, and setting their rates.
 
@@ -14,252 +16,6 @@ Required properties :
 - #clock-cells : Should be 1.
   In clock consumers, this cell represents the clock ID exposed by the CAR.
 
-  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-
-  0	unassigned
-  1	unassigned
-  2	unassigned
-  3	unassigned
-  4	rtc
-  5	timer
-  6	uarta
-  7	unassigned	(register bit affects uartb and vfir)
-  8	unassigned
-  9	sdmmc2
-  10	unassigned	(register bit affects spdif_in and spdif_out)
-  11	i2s1
-  12	i2c1
-  13	ndflash
-  14	sdmmc1
-  15	sdmmc4
-  16	unassigned
-  17	pwm
-  18	i2s2
-  19	epp
-  20	unassigned	(register bit affects vi and vi_sensor)
-  21	2d
-  22	usbd
-  23	isp
-  24	3d
-  25	unassigned
-  26	disp2
-  27	disp1
-  28	host1x
-  29	vcp
-  30	i2s0
-  31	unassigned
-
-  32	unassigned
-  33	unassigned
-  34	apbdma
-  35	unassigned
-  36	kbc
-  37	unassigned
-  38	unassigned
-  39	unassigned	(register bit affects fuse and fuse_burn)
-  40	kfuse
-  41	sbc1
-  42	nor
-  43	unassigned
-  44	sbc2
-  45	unassigned
-  46	sbc3
-  47	i2c5
-  48	dsia
-  49	unassigned
-  50	mipi
-  51	hdmi
-  52	csi
-  53	unassigned
-  54	i2c2
-  55	uartc
-  56	mipi-cal
-  57	emc
-  58	usb2
-  59	usb3
-  60	msenc
-  61	vde
-  62	bsea
-  63	bsev
-
-  64	unassigned
-  65	uartd
-  66	unassigned
-  67	i2c3
-  68	sbc4
-  69	sdmmc3
-  70	unassigned
-  71	owr
-  72	afi
-  73	csite
-  74	unassigned
-  75	unassigned
-  76	la
-  77	trace
-  78	soc_therm
-  79	dtv
-  80	ndspeed
-  81	i2cslow
-  82	dsib
-  83	tsec
-  84	unassigned
-  85	unassigned
-  86	unassigned
-  87	unassigned
-  88	unassigned
-  89	xusb_host
-  90	unassigned
-  91	msenc
-  92	csus
-  93	unassigned
-  94	unassigned
-  95	unassigned	(bit affects xusb_dev and xusb_dev_src)
-
-  96	unassigned
-  97	unassigned
-  98	unassigned
-  99	mselect
-  100	tsensor
-  101	i2s3
-  102	i2s4
-  103	i2c4
-  104	sbc5
-  105	sbc6
-  106	d_audio
-  107	apbif
-  108	dam0
-  109	dam1
-  110	dam2
-  111	hda2codec_2x
-  112	unassigned
-  113	audio0_2x
-  114	audio1_2x
-  115	audio2_2x
-  116	audio3_2x
-  117	audio4_2x
-  118	spdif_2x
-  119	actmon
-  120	extern1
-  121	extern2
-  122	extern3
-  123	unassigned
-  124	unassigned
-  125	hda
-  126	unassigned
-  127	se
-
-  128	hda2hdmi
-  129	unassigned
-  130	unassigned
-  131	unassigned
-  132	unassigned
-  133	unassigned
-  134	unassigned
-  135	unassigned
-  136	unassigned
-  137	unassigned
-  138	unassigned
-  139	unassigned
-  140	unassigned
-  141	unassigned
-  142	unassigned
-  143	unassigned	(bit affects xusb_falcon_src, xusb_fs_src,
-			 xusb_host_src and xusb_ss_src)
-  144	cilab
-  145	cilcd
-  146	cile
-  147	dsialp
-  148	dsiblp
-  149	unassigned
-  150	dds
-  151	unassigned
-  152	dp2
-  153	amx
-  154	adx
-  155	unassigned	(bit affects dfll_ref and dfll_soc)
-  156	xusb_ss
-
-  192	uartb
-  193	vfir
-  194	spdif_in
-  195	spdif_out
-  196	vi
-  197	vi_sensor
-  198	fuse
-  199	fuse_burn
-  200	clk_32k
-  201	clk_m
-  202	clk_m_div2
-  203	clk_m_div4
-  204	pll_ref
-  205	pll_c
-  206	pll_c_out1
-  207	pll_c2
-  208	pll_c3
-  209	pll_m
-  210	pll_m_out1
-  211	pll_p
-  212	pll_p_out1
-  213	pll_p_out2
-  214	pll_p_out3
-  215	pll_p_out4
-  216	pll_a
-  217	pll_a_out0
-  218	pll_d
-  219	pll_d_out0
-  220	pll_d2
-  221	pll_d2_out0
-  222	pll_u
-  223	pll_u_480M
-  224	pll_u_60M
-  225	pll_u_48M
-  226	pll_u_12M
-  227	pll_x
-  228	pll_x_out0
-  229	pll_re_vco
-  230	pll_re_out
-  231	pll_e_out0
-  232	spdif_in_sync
-  233	i2s0_sync
-  234	i2s1_sync
-  235	i2s2_sync
-  236	i2s3_sync
-  237	i2s4_sync
-  238	vimclk_sync
-  239	audio0
-  240	audio1
-  241	audio2
-  242	audio3
-  243	audio4
-  244	spdif
-  245	clk_out_1
-  246	clk_out_2
-  247	clk_out_3
-  248	blink
-  252	xusb_host_src
-  253	xusb_falcon_src
-  254	xusb_fs_src
-  255	xusb_ss_src
-  256	xusb_dev_src
-  257	xusb_dev
-  258	xusb_hs_src
-  259	sclk
-  260	hclk
-  261	pclk
-  262	cclk_g
-  263	cclk_lp
-  264	dfll_ref
-  265	dfll_soc
-
 Example SoC include file:
 
 / {
@@ -270,7 +26,7 @@ Example SoC include file:
 	};
 
 	usb at c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car TEGRA114_CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/include/dt-bindings/clk/tegra114-car.h b/include/dt-bindings/clk/tegra114-car.h
new file mode 100644
index 0000000..83ea208
--- /dev/null
+++ b/include/dt-bindings/clk/tegra114-car.h
@@ -0,0 +1,342 @@
+/*
+ * This header provides constants for binding nvidia,tegra114-car.
+ *
+ * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLK_TEGRA114_CAR_H
+#define _DT_BINDINGS_CLK_TEGRA114_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA114_CLK_RTC 4
+#define TEGRA114_CLK_TIMER 5
+#define TEGRA114_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA114_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA114_CLK_I2S1 11
+#define TEGRA114_CLK_I2C1 12
+#define TEGRA114_CLK_NDFLASH 13
+#define TEGRA114_CLK_SDMMC1 14
+#define TEGRA114_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA114_CLK_PWM 17
+#define TEGRA114_CLK_I2S2 18
+#define TEGRA114_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA114_CLK_GR_2D 21
+#define TEGRA114_CLK_USBD 22
+#define TEGRA114_CLK_ISP 23
+#define TEGRA114_CLK_GR_3D 24
+/* 25 */
+#define TEGRA114_CLK_DISP2 26
+#define TEGRA114_CLK_DISP1 27
+#define TEGRA114_CLK_HOST1X 28
+#define TEGRA114_CLK_VCP 29
+#define TEGRA114_CLK_I2S0 30
+/* 31 */
+
+/* 32 */
+/* 33 */
+#define TEGRA114_CLK_APBDMA 34
+/* 35 */
+#define TEGRA114_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA114_CLK_KFUSE 40
+#define TEGRA114_CLK_SBC1 41
+#define TEGRA114_CLK_NOR 42
+/* 43 */
+#define TEGRA114_CLK_SBC2 44
+/* 45 */
+#define TEGRA114_CLK_SBC3 46
+#define TEGRA114_CLK_I2C5 47
+#define TEGRA114_CLK_DSIA 48
+/* 49 */
+#define TEGRA114_CLK_MIPI 50
+#define TEGRA114_CLK_HDMI 51
+#define TEGRA114_CLK_CSI 52
+/* 53 */
+#define TEGRA114_CLK_I2C2 54
+#define TEGRA114_CLK_UARTC 55
+#define TEGRA114_CLK_MIPI_CAL 56
+#define TEGRA114_CLK_EMC 57
+#define TEGRA114_CLK_USB2 58
+#define TEGRA114_CLK_USB3 59
+/* 60 */
+#define TEGRA114_CLK_VDE 61
+#define TEGRA114_CLK_BSEA 62
+#define TEGRA114_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA114_CLK_UARTD 65
+/* 66 */
+#define TEGRA114_CLK_I2C3 67
+#define TEGRA114_CLK_SBC4 68
+#define TEGRA114_CLK_SDMMC3 69
+/* 70 */
+#define TEGRA114_CLK_OWR 71
+/* 72 */
+#define TEGRA114_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA114_CLK_LA 76
+#define TEGRA114_CLK_TRACE 77
+#define TEGRA114_CLK_SOC_THERM 78
+#define TEGRA114_CLK_DTV 79
+#define TEGRA114_CLK_NDSPEED 80
+#define TEGRA114_CLK_I2CSLOW 81
+#define TEGRA114_CLK_DSIB 82
+#define TEGRA114_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA114_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA114_CLK_MSENC 91
+#define TEGRA114_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA114_CLK_MSELECT 99
+#define TEGRA114_CLK_TSENSOR 100
+#define TEGRA114_CLK_I2S3 101
+#define TEGRA114_CLK_I2S4 102
+#define TEGRA114_CLK_I2C4 103
+#define TEGRA114_CLK_SBC5 104
+#define TEGRA114_CLK_SBC6 105
+#define TEGRA114_CLK_D_AUDIO 106
+#define TEGRA114_CLK_APBIF 107
+#define TEGRA114_CLK_DAM0 108
+#define TEGRA114_CLK_DAM1 109
+#define TEGRA114_CLK_DAM2 110
+#define TEGRA114_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA114_CLK_AUDIO0_2X 113
+#define TEGRA114_CLK_AUDIO1_2X 114
+#define TEGRA114_CLK_AUDIO2_2X 115
+#define TEGRA114_CLK_AUDIO3_2X 116
+#define TEGRA114_CLK_AUDIO4_2X 117
+#define TEGRA114_CLK_SPDIF_2X 118
+#define TEGRA114_CLK_ACTMON 119
+#define TEGRA114_CLK_EXTERN1 120
+#define TEGRA114_CLK_EXTERN2 121
+#define TEGRA114_CLK_EXTERN3 122
+/* 123 */
+/* 124 */
+#define TEGRA114_CLK_HDA 125
+/* 126 */
+#define TEGRA114_CLK_SE 127
+
+#define TEGRA114_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA114_CLK_CILAB 144
+#define TEGRA114_CLK_CILCD 145
+#define TEGRA114_CLK_CILE 146
+#define TEGRA114_CLK_DSIALP 147
+#define TEGRA114_CLK_DSIBLP 148
+/* 149 */
+#define TEGRA114_CLK_DDS 150
+/* 151 */
+#define TEGRA114_CLK_DP2 152
+#define TEGRA114_CLK_AMX 153
+#define TEGRA114_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA114_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+/* 166 */
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+/* 171 */
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+/* 176 */
+/* 177 */
+/* 178 */
+/* 179 */
+/* 180 */
+/* 181 */
+/* 182 */
+/* 183 */
+/* 184 */
+/* 185 */
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+
+#define TEGRA114_CLK_UARTB 192
+#define TEGRA114_CLK_VFIR 193
+#define TEGRA114_CLK_SPDIF_IN 194
+#define TEGRA114_CLK_SPDIF_OUT 195
+#define TEGRA114_CLK_VI 196
+#define TEGRA114_CLK_VI_SENSOR 197
+#define TEGRA114_CLK_FUSE 198
+#define TEGRA114_CLK_FUSE_BURN 199
+#define TEGRA114_CLK_CLK_32K 200
+#define TEGRA114_CLK_CLK_M 201
+#define TEGRA114_CLK_CLK_M_DIV2 202
+#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_PLL_REF 204
+#define TEGRA114_CLK_PLL_C 205
+#define TEGRA114_CLK_PLL_C_OUT1 206
+#define TEGRA114_CLK_PLL_C2 207
+#define TEGRA114_CLK_PLL_C3 208
+#define TEGRA114_CLK_PLL_M 209
+#define TEGRA114_CLK_PLL_M_OUT1 210
+#define TEGRA114_CLK_PLL_P 211
+#define TEGRA114_CLK_PLL_P_OUT1 212
+#define TEGRA114_CLK_PLL_P_OUT2 213
+#define TEGRA114_CLK_PLL_P_OUT3 214
+#define TEGRA114_CLK_PLL_P_OUT4 215
+#define TEGRA114_CLK_PLL_A 216
+#define TEGRA114_CLK_PLL_A_OUT0 217
+#define TEGRA114_CLK_PLL_D 218
+#define TEGRA114_CLK_PLL_D_OUT0 219
+#define TEGRA114_CLK_PLL_D2 220
+#define TEGRA114_CLK_PLL_D2_OUT0 221
+#define TEGRA114_CLK_PLL_U 222
+#define TEGRA114_CLK_PLL_U_480M 223
+
+#define TEGRA114_CLK_PLL_U_60M 224
+#define TEGRA114_CLK_PLL_U_48M 225
+#define TEGRA114_CLK_PLL_U_12M 226
+#define TEGRA114_CLK_PLL_X 227
+#define TEGRA114_CLK_PLL_X_OUT0 228
+#define TEGRA114_CLK_PLL_RE_VCO 229
+#define TEGRA114_CLK_PLL_RE_OUT 230
+#define TEGRA114_CLK_PLL_E_OUT0 231
+#define TEGRA114_CLK_SPDIF_IN_SYNC 232
+#define TEGRA114_CLK_I2S0_SYNC 233
+#define TEGRA114_CLK_I2S1_SYNC 234
+#define TEGRA114_CLK_I2S2_SYNC 235
+#define TEGRA114_CLK_I2S3_SYNC 236
+#define TEGRA114_CLK_I2S4_SYNC 237
+#define TEGRA114_CLK_VIMCLK_SYNC 238
+#define TEGRA114_CLK_AUDIO0 239
+#define TEGRA114_CLK_AUDIO1 240
+#define TEGRA114_CLK_AUDIO2 241
+#define TEGRA114_CLK_AUDIO3 242
+#define TEGRA114_CLK_AUDIO4 243
+#define TEGRA114_CLK_SPDIF 244
+#define TEGRA114_CLK_CLK_OUT_1 245
+#define TEGRA114_CLK_CLK_OUT_2 246
+#define TEGRA114_CLK_CLK_OUT_3 247
+#define TEGRA114_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA114_CLK_XUSB_HOST_SRC 252
+#define TEGRA114_CLK_XUSB_FALCON_SRC 253
+#define TEGRA114_CLK_XUSB_FS_SRC 254
+#define TEGRA114_CLK_XUSB_SS_SRC 255
+
+#define TEGRA114_CLK_XUSB_DEV_SRC 256
+#define TEGRA114_CLK_XUSB_DEV 257
+#define TEGRA114_CLK_XUSB_HS_SRC 258
+#define TEGRA114_CLK_SCLK 259
+#define TEGRA114_CLK_HCLK 260
+#define TEGRA114_CLK_PCLK 261
+#define TEGRA114_CLK_CCLK_G 262
+#define TEGRA114_CLK_CCLK_LP 263
+/* 264 */
+/* 265 */
+/* 266 */
+/* 267 */
+/* 268 */
+/* 269 */
+/* 270 */
+/* 271 */
+/* 272 */
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA114_CLK_AUDIO0_MUX 300
+#define TEGRA114_CLK_AUDIO1_MUX 301
+#define TEGRA114_CLK_AUDIO2_MUX 302
+#define TEGRA114_CLK_AUDIO3_MUX 303
+#define TEGRA114_CLK_AUDIO4_MUX 304
+#define TEGRA114_CLK_SPDIF_MUX 305
+#define TEGRA114_CLK_CLK_OUT_1_MUX 306
+#define TEGRA114_CLK_CLK_OUT_2_MUX 307
+#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+#define TEGRA114_CLK_DSIA_MUX 309
+#define TEGRA114_CLK_DSIB_MUX 310
+#define TEGRA114_CLK_CLK_MAX 311
+
+#endif	/* _DT_BINDINGS_CLK_TEGRA114_CAR_H */
-- 
1.8.1.5



From hdoyu at nvidia.com  Mon May 13 07:07:05 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 13 May 2013 14:07:05 +0300
Subject: [PATCH 6/6] ARM: tegra114: convert device tree files to use CLK
 defines
In-Reply-To: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1368443225-16978-7-git-send-email-hdoyu@nvidia.com>

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/boot/dts/tegra114-dalmore.dts |  4 +-
 arch/arm/boot/dts/tegra114.dtsi        | 79 +++++++++++++++++++---------------
 2 files changed, 47 insertions(+), 36 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 59695f01..cfcb3e2 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -957,7 +957,9 @@
 
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
 
-		clocks = <&tegra_car 216>, <&tegra_car 217>, <&tegra_car 120>;
+		clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
+		       	 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA114_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 15d1b58..1d3127e 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clk/tegra114-car.h>
 
 #include "skeleton.dtsi"
 
@@ -35,7 +36,7 @@
 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 5>;
+		clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 	};
 
 	tegra_car: clock {
@@ -79,7 +80,7 @@
 			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 	};
 
 	ahb: ahb {
@@ -125,7 +126,7 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		status = "disabled";
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 	};
 
 	uartb: serial at 70006040 {
@@ -135,7 +136,7 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		status = "disabled";
-		clocks = <&tegra_car 192>;
+		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 	};
 
 	uartc: serial at 70006200 {
@@ -145,7 +146,7 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		status = "disabled";
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 	};
 
 	uartd: serial at 70006300 {
@@ -155,14 +156,14 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		status = "disabled";
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 	};
 
 	pwm: pwm {
 		compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car TEGRA114_CLK_PWM>;
 		status = "disabled";
 	};
 
@@ -172,7 +173,7 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>;
+		clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 		clock-names = "div-clk";
 		status = "disabled";
 	};
@@ -183,7 +184,7 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>;
+		clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 		clock-names = "div-clk";
 		status = "disabled";
 	};
@@ -194,7 +195,7 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>;
+		clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 		clock-names = "div-clk";
 		status = "disabled";
 	};
@@ -205,7 +206,7 @@
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 103>;
+		clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 		clock-names = "div-clk";
 		status = "disabled";
 	};
@@ -216,7 +217,7 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>;
+		clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 		clock-names = "div-clk";
 		status = "disabled";
 	};
@@ -228,7 +229,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 		clock-names = "spi";
 		status = "disabled";
 	};
@@ -240,7 +241,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 		clock-names = "spi";
 		status = "disabled";
 	};
@@ -252,7 +253,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 		clock-names = "spi";
 		status = "disabled";
 	};
@@ -264,7 +265,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 		clock-names = "spi";
 		status = "disabled";
 	};
@@ -276,7 +277,7 @@
 		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 104>;
+		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 		clock-names = "spi";
 		status = "disabled";
 	};
@@ -288,7 +289,7 @@
 		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 105>;
+		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 		clock-names = "spi";
 		status = "disabled";
 	};
@@ -297,21 +298,21 @@
 		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
 		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 4>;
+		clocks = <&tegra_car TEGRA114_CLK_RTC>;
 	};
 
 	kbc {
 		compatible = "nvidia,tegra114-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car TEGRA114_CLK_KBC>;
 		status = "disabled";
 	};
 
 	pmc {
 		compatible = "nvidia,tegra114-pmc";
 		reg = <0x7000e400 0x400>;
-		clocks = <&tegra_car 261>, <&clk32k_in>;
+		clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
 	};
 
@@ -336,11 +337,19 @@
 			<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
 			<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
 			<&apbdma 29>;
-		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-			 <&tegra_car 110>, <&tegra_car 194>, <&tegra_car 153>,
-			 <&tegra_car 154>;
+		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+		       	 <&tegra_car TEGRA114_CLK_APBIF>,
+			 <&tegra_car TEGRA114_CLK_I2S0>,
+			 <&tegra_car TEGRA114_CLK_I2S1>,
+			 <&tegra_car TEGRA114_CLK_I2S2>,
+			 <&tegra_car TEGRA114_CLK_I2S3>,
+			 <&tegra_car TEGRA114_CLK_I2S4>,
+			 <&tegra_car TEGRA114_CLK_DAM0>,
+			 <&tegra_car TEGRA114_CLK_DAM1>,
+			 <&tegra_car TEGRA114_CLK_DAM2>,
+			 <&tegra_car TEGRA114_CLK_SPDIF_IN>,
+			 <&tegra_car TEGRA114_CLK_AMX>,
+			 <&tegra_car TEGRA114_CLK_ADX>;
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in", "amx", "adx";
@@ -352,7 +361,7 @@
 			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
-			clocks = <&tegra_car 30>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 			status = "disabled";
 		};
 
@@ -360,7 +369,7 @@
 			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
-			clocks = <&tegra_car 11>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 			status = "disabled";
 		};
 
@@ -368,7 +377,7 @@
 			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
-			clocks = <&tegra_car 18>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 			status = "disabled";
 		};
 
@@ -376,7 +385,7 @@
 			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
-			clocks = <&tegra_car 101>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 			status = "disabled";
 		};
 
@@ -384,7 +393,7 @@
 			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 			status = "disabled";
 		};
 	};
@@ -393,7 +402,7 @@
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 		status = "disable";
 	};
 
@@ -401,7 +410,7 @@
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 		status = "disable";
 	};
 
@@ -409,7 +418,7 @@
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 		status = "disable";
 	};
 
@@ -417,7 +426,7 @@
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 		status = "disable";
 	};
 
-- 
1.8.1.5



From inki.dae at samsung.com  Mon May 13 07:24:01 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Mon, 13 May 2013 20:24:01 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <5190B7D8.3010803@canonical.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
Message-ID: <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>



> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
> Sent: Monday, May 13, 2013 6:52 PM
> To: Inki Dae
> Cc: 'Rob Clark'; 'Daniel Vetter'; 'DRI mailing list'; linux-arm-
> kernel at lists.infradead.org; linux-media at vger.kernel.org; 'linux-fbdev';
> 'Kyungmin Park'; 'myungjoo.ham'; 'YoungJun Cho'
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> Op 13-05-13 11:21, Inki Dae schreef:
> >
> >> -----Original Message-----
> >> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
> >> Sent: Monday, May 13, 2013 5:01 PM
> >> To: Inki Dae
> >> Cc: Rob Clark; Daniel Vetter; DRI mailing list; linux-arm-
> >> kernel at lists.infradead.org; linux-media at vger.kernel.org; linux-fbdev;
> >> Kyungmin Park; myungjoo.ham; YoungJun Cho
> >> Subject: Re: Introduce a new helper framework for buffer
> synchronization
> >>
> >> Op 09-05-13 09:33, Inki Dae schreef:
> >>> Hi all,
> >>>
> >>> This post introduces a new helper framework based on dma fence. And
> the
> >>> purpose of this post is to collect other opinions and advices before
> RFC
> >>> posting.
> >>>
> >>> First of all, this helper framework, called fence helper, is in
> progress
> >>> yet so might not have enough comments in codes and also might need to
> be
> >>> more cleaned up. Moreover, we might be missing some parts of the dma
> >> fence.
> >>> However, I'd like to say that all things mentioned below has been
> tested
> >>> with Linux platform and worked well.
> >>> ....
> >>>
> >>> And tutorial for user process.
> >>>         just before cpu access
> >>>                 struct dma_buf_fence *df;
> >>>
> >>>                 df->type = DMA_BUF_ACCESS_READ or
DMA_BUF_ACCESS_WRITE;
> >>>                 ioctl(fd, DMA_BUF_GET_FENCE, &df);
> >>>
> >>>         after memset or memcpy
> >>>                 ioctl(fd, DMA_BUF_PUT_FENCE, &df);
> >> NAK.
> >>
> >> Userspace doesn't need to trigger fences. It can do a buffer idle wait,
> >> and postpone submitting new commands until after it's done using the
> >> buffer.
> > Hi Maarten,
> >
> > It seems that you say user should wait for a buffer like KDS does: KDS
> uses
> > select() to postpone submitting new commands. But I think this way
> assumes
> > that every data flows a DMA device to a CPU. For example, a CPU should
> keep
> > polling for the completion of a buffer access by a DMA device. This
> means
> > that the this way isn't considered for data flow to opposite case; CPU
> to
> > DMA device.
> Not really. You do both things the same way. You first wait for the bo to
> be idle, this could be implemented by adding poll support to the dma-buf
> fd.
> Then you either do your read or write. Since userspace is supposed to be
> the one controlling the bo it should stay idle at that point. If you have
> another thread queueing
> the buffer againbefore your thread is done that's a bug in the
application,
> and can be solved with userspace locking primitives. No need for the
> kernel to get involved.
> 

Yes, that is how we have synchronized buffer between CPU and DMA device
until now without buffer synchronization mechanism. I thought that it's best
to make user not considering anything: user can access a buffer regardless
of any DMA device controlling and the buffer synchronization is performed in
kernel level. Moreover, I think we could optimize graphics and multimedia
hardware performance because hardware can do more works: one thread accesses
a shared buffer and the other controls DMA device with the shared buffer in
parallel. Thus, we could avoid sequential processing and that is my
intention. Aren't you think about that we could improve hardware utilization
with such way or other? of course, there could be better way.

> >> Kernel space doesn't need the root hole you created by giving a
> >> dereferencing a pointer passed from userspace.
> >> Your next exercise should be to write a security exploit from the api
> you
> >> created here. It's the only way to learn how to write safe code. Hint:
> >> df.ctx = mmap(..);
> >>
> > Also I'm not clear to use our way yet and that is why I posted. As you
> > mentioned, it seems like that using mmap() is more safe. But there is
> one
> > issue it makes me confusing. For your hint, df.ctx = mmap(..), the issue
> is
> > that dmabuf mmap can be used to map a dmabuf with user space. And the
> dmabuf
> > means a physical memory region allocated by some allocator such as drm
> gem
> > or ion.
> >
> > There might be my missing point so could you please give me more
> comments?
> >
> My point was that userspace could change df.ctx to some mmap'd memory,
> forcing the kernel to execute some code prepared by userspace.

Understood. I have to find a better way. And for this, I'd like to listen
attentively more opinions and advices.

Thanks for comments,
Inki Dae



From maarten.lankhorst at canonical.com  Mon May 13 07:40:58 2013
From: maarten.lankhorst at canonical.com (Maarten Lankhorst)
Date: Mon, 13 May 2013 13:40:58 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
Message-ID: <5190D14A.7050904@canonical.com>

Op 13-05-13 13:24, Inki Dae schreef:
>> and can be solved with userspace locking primitives. No need for the
>> kernel to get involved.
>>
> Yes, that is how we have synchronized buffer between CPU and DMA device
> until now without buffer synchronization mechanism. I thought that it's best
> to make user not considering anything: user can access a buffer regardless
> of any DMA device controlling and the buffer synchronization is performed in
> kernel level. Moreover, I think we could optimize graphics and multimedia
> hardware performance because hardware can do more works: one thread accesses
> a shared buffer and the other controls DMA device with the shared buffer in
> parallel. Thus, we could avoid sequential processing and that is my
> intention. Aren't you think about that we could improve hardware utilization
> with such way or other? of course, there could be better way.
>
If you don't want to block the hardware the only option is to allocate a temp bo and blit to/from it using the hardware.
OpenGL already does that when you want to read back, because otherwise the entire pipeline can get stalled.
The overhead of command submission for that shouldn't be high, if it is you should really try to optimize that first
before coming up with this crazy scheme.

In that case you still wouldn't give userspace control over the fences. I don't see any way that can end well.
What if userspace never signals? What if userspace gets killed by oom killer. Who keeps track of that?

~Maarten


From festevam at gmail.com  Mon May 13 07:48:12 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 13 May 2013 08:48:12 -0300
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <20130324141758.GH6281@S2101-09.ap.freescale.net>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <20130304031716.GC30431@S2101-09.ap.freescale.net>
 <CAOMZO5Ai-msRVeAqQFiRhfAxkb2DMTYJvTcYihBhFt6GMCFwPQ@mail.gmail.com>
 <20130323135608.GG6281@S2101-09.ap.freescale.net>
 <CAOMZO5BvT3CUhPECTQZQq_Q2YEqMJzmXPL5pj-3Qmq35jnvm1A@mail.gmail.com>
 <20130324141758.GH6281@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5AeJUtyRC1BoAUiFihbjKtLMC2WBjaUXW0x+RE+QHYPnA@mail.gmail.com>

Hi Shawn,

On Sun, Mar 24, 2013 at 11:18 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Yes, when testing on next-20130322, it seems audio playback works.  But
> since when the patch gets applied on my mxs/dt branch, it breaks audio
> there, I still can not apply it.

Could you please apply the touchscreen patch now?


From Ian.Campbell at citrix.com  Mon May 13 07:59:12 2013
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Mon, 13 May 2013 12:59:12 +0100
Subject: [RFC] device-tree.git automatic sync from linux.git
In-Reply-To: <5190900D.5020408@monstr.eu>
References: <1366800525.20256.266.camel@zakaz.uk.xensource.com>
 <5190900D.5020408@monstr.eu>
Message-ID: <1368446352.537.81.camel@zakaz.uk.xensource.com>

On Mon, 2013-05-13 at 08:02 +0100, Michal Simek wrote:
> Just small overview it is a Xilinx soft core cpu where you can even setup
> some parameters for core itself - multiplier, divider, BS, fpu, cache sizes, etc.
> You have to also compose the whole system and every platform/configuration is different
> because you can setup addresses, IP on the bus, IRQs, etc.
> Based on this configuration we have created tcl script which is able to generate
> DTS directly from Xilinx design tool and it is working quite well for several years
> and everybody just use it without any problem.

That sounds very neat!

Does this tcl script live in the kernel tree? If so would you think it
would make sense for it to also migrate to device-tree.git? I'm not at
all sure if that makes sense but if you think it does please let me know
which paths need top be carried over.

> As you see in your repo there is only one microblaze DTS which is for one of mine
> ancient configuration which none used.
> It means from microblaze point of view we can simple remove it from mainline kernel
> because it is useless.

That will then naturally get propagated over to device-tree.git.

> I also care about arm zynq platform where situation is partially different because
> zynq is fixed block but you can add others thing to programmable logic.
> It means for zynq case we are almost in the same situation where every zynq based
> platform is using different configuration and that's why fpgas are so great.
> 
> It means for zynq case everybody will need different DTS but will be just good
> to describe or show binding.
> Currently we have just one dts for zc702 xilinx reference board.
> 
> Let's move to my point.
> Based on our experience all xilinx boards don't depend on any dts in the linux kernel
> and our users just understand the reason why they should use our tcl script for
> DTS generation.
> 
> Back to your point about moving DTSes out of the kernel.

I suppose you are now commenting on the Phase II bit where maintenance
of the DTS moves out of linux.git into device-tree.git, rather than
Phase I work, which is creating a split repo which is automatically
synchronised from linux.git but maintenance remains in linux.git, i.e.
what I'm doing here.

>  For microblaze - no problem
> just do it. For arm zynq this is more problematic because there is weird binding
> for ARM. For example PMU which is out of bus and should be probably in cpu node.
> Also scu devices, scutimers, watchdog which lie on the bus for our case and we
> need to use PPI interrupt cpu mask. Different clock binding, maybe pinmux binding, etc.
> 
> It means from my point of view if binding is correct, no problem to move it
> out of the kernel. If a kernel patch change binding, it is worth for me to change
> dts in the kernel too to reflect this change and track this change too.
> My proposal is, let's clean all DTSes in the arm kernel that all platform use
> the same binding where all platforms are just correctly described.

AIUI this split/move isn't intended to change the existing policy, which
is already that DTS files are supposed to remain compatible across
kernel versions and that "flag days" are to be avoided. The split is
supposed to make it harder (if not impossible) to accidentally break
that policy.

On the other hand I suppose there is an argument to be made for clearing
up the cruft *before* making the split.

Ultimately I think this will be up to Grant & co.

> The reaching this point I would suggest that for arm, arm-soc maintainers should
> keep eyes on any dts binding change and all these changes require ACK from Rob or Grant
> (like device-tree maintainers).

Yes, once we move onto Phase II I don't expect it will end up being me
that is the DTS maintainer -- I expect the maintenance will remain with
those who take care of it in linux.git today.

My involvement in Phase I is really just to help out with the transition
(ulterior motive: the Xen project would also like to use these DTS
files...) not to perform a "land grab" or take over maintenance etc. I
certainly don't think I am the right person to become the long term
maintainer of device-tree.git!

Ian.



From inki.dae at samsung.com  Mon May 13 08:21:18 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Mon, 13 May 2013 21:21:18 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <5190D14A.7050904@canonical.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
Message-ID: <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>



> -----Original Message-----
> From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
> owner at vger.kernel.org] On Behalf Of Maarten Lankhorst
> Sent: Monday, May 13, 2013 8:41 PM
> To: Inki Dae
> Cc: 'Rob Clark'; 'Daniel Vetter'; 'DRI mailing list'; linux-arm-
> kernel at lists.infradead.org; linux-media at vger.kernel.org; 'linux-fbdev';
> 'Kyungmin Park'; 'myungjoo.ham'; 'YoungJun Cho'
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> Op 13-05-13 13:24, Inki Dae schreef:
> >> and can be solved with userspace locking primitives. No need for the
> >> kernel to get involved.
> >>
> > Yes, that is how we have synchronized buffer between CPU and DMA device
> > until now without buffer synchronization mechanism. I thought that it's
> best
> > to make user not considering anything: user can access a buffer
> regardless
> > of any DMA device controlling and the buffer synchronization is
> performed in
> > kernel level. Moreover, I think we could optimize graphics and
> multimedia
> > hardware performance because hardware can do more works: one thread
> accesses
> > a shared buffer and the other controls DMA device with the shared buffer
> in
> > parallel. Thus, we could avoid sequential processing and that is my
> > intention. Aren't you think about that we could improve hardware
> utilization
> > with such way or other? of course, there could be better way.
> >
> If you don't want to block the hardware the only option is to allocate a
> temp bo and blit to/from it using the hardware.
> OpenGL already does that when you want to read back, because otherwise the
> entire pipeline can get stalled.
> The overhead of command submission for that shouldn't be high, if it is
> you should really try to optimize that first
> before coming up with this crazy scheme.
> 

I have considered all devices sharing buffer with CPU; multimedia, display
controller and graphics devices (including GPU). And we could provide
easy-to-use user interfaces for buffer synchronization. Of course, the
proposed user interfaces may be so ugly yet but at least, I think we need
something else for it.

> In that case you still wouldn't give userspace control over the fences. I
> don't see any way that can end well.
> What if userspace never signals? What if userspace gets killed by oom
> killer. Who keeps track of that?
> 

In all cases, all kernel resources to user fence will be released by kernel
once the fence is timed out: never signaling and process killing by oom
killer makes the fence timed out. And if we use mmap mechanism you mentioned
before, I think user resource could also be freed properly.

Thanks,
Inki Dae

> ~Maarten
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From pawel.moll at arm.com  Mon May 13 08:35:58 2013
From: pawel.moll at arm.com (Pawel Moll)
Date: Mon, 13 May 2013 13:35:58 +0100
Subject: [PATCH 12/14] ARM: vexpress: Remove init_irq declaration in
 machine description
In-Reply-To: <1368438253-28218-13-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-13-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368448558.3425.2.camel@hornet>

On Mon, 2013-05-13 at 10:44 +0100, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for vexpress as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-vexpress/v2m.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index 8802030..c419b76 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
> @@ -458,7 +458,6 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
>  	.smp		= smp_ops(vexpress_smp_ops),
>  	.map_io		= v2m_dt_map_io,
>  	.init_early	= v2m_dt_init_early,
> -	.init_irq	= irqchip_init,
>  	.init_time	= v2m_dt_timer_init,
>  	.init_machine	= v2m_dt_init,
>  MACHINE_END

Acked-by: Pawel Moll <pawel.moll at arm.com>

Thanks!

Pawel




From shawn.guo at linaro.org  Mon May 13 08:51:12 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 20:51:12 +0800
Subject: [PATCH 2/3] ARM: imx: move clk_prepare() out from mxs_restart()
In-Reply-To: <20130513082535.GM32299@pengutronix.de>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
 <1368408728-12264-3-git-send-email-shawn.guo@linaro.org>
 <20130513082535.GM32299@pengutronix.de>
Message-ID: <20130513125111.GB4440@S2101-09.ap.freescale.net>

On Mon, May 13, 2013 at 10:25:35AM +0200, Sascha Hauer wrote:
> Hi Shawn,
> 
> In the subject:
> 
> s/mxs_restart/mxc_restart/

Thanks, Sascha.  Fixed it and commit log as well.

Shawn



From shawn.guo at linaro.org  Mon May 13 08:52:17 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 20:52:17 +0800
Subject: [PATCH 3/3] ARM: imx: create imx_arch_reset_init() for DT boot
In-Reply-To: <20130513082708.GN32299@pengutronix.de>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
 <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
 <20130513082708.GN32299@pengutronix.de>
Message-ID: <20130513125215.GC4440@S2101-09.ap.freescale.net>

On Mon, May 13, 2013 at 10:27:08AM +0200, Sascha Hauer wrote:
> On Mon, May 13, 2013 at 09:32:08AM +0800, Shawn Guo wrote:
> > The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to
> > get clock.  It's suitable for non-DT boot but not for DT boot where
> > dynamic mapping and of_clk_get() should be used instead.  Create
> > imx_arch_reset_init() as the DT variant of mxc_arch_reset_init(),
> > and change DT platforms to use it.
> 
> Having mxc_arch_reset_init for !dt and the same functionality for dt
> named imx_arch_reset_init is a bit confusing. Maybe add _dt_ to the
> function name?

Ok, will change it to mxc_arch_reset_init_dt() avoid the confusion.

Shawn



From s.hauer at pengutronix.de  Mon May 13 08:54:33 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 May 2013 14:54:33 +0200
Subject: [PATCH 3/3] ARM: imx: create imx_arch_reset_init() for DT boot
In-Reply-To: <20130513125215.GC4440@S2101-09.ap.freescale.net>
References: <1368408728-12264-1-git-send-email-shawn.guo@linaro.org>
 <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
 <20130513082708.GN32299@pengutronix.de>
 <20130513125215.GC4440@S2101-09.ap.freescale.net>
Message-ID: <20130513125433.GS32299@pengutronix.de>

On Mon, May 13, 2013 at 08:52:17PM +0800, Shawn Guo wrote:
> On Mon, May 13, 2013 at 10:27:08AM +0200, Sascha Hauer wrote:
> > On Mon, May 13, 2013 at 09:32:08AM +0800, Shawn Guo wrote:
> > > The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to
> > > get clock.  It's suitable for non-DT boot but not for DT boot where
> > > dynamic mapping and of_clk_get() should be used instead.  Create
> > > imx_arch_reset_init() as the DT variant of mxc_arch_reset_init(),
> > > and change DT platforms to use it.
> > 
> > Having mxc_arch_reset_init for !dt and the same functionality for dt
> > named imx_arch_reset_init is a bit confusing. Maybe add _dt_ to the
> > function name?
> 
> Ok, will change it to mxc_arch_reset_init_dt() avoid the confusion.

I think we both prefer 'imx' over 'mxc', but maybe changing this is
topic for another patch.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sergei.shtylyov at cogentembedded.com  Mon May 13 09:04:41 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 13 May 2013 17:04:41 +0400
Subject: [PATCH 2/2] ARM: shmobile: lager: enable Ether
In-Reply-To: <20130513004001.GC22911@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>
 <518CCD55.6070101@cogentembedded.com> <20130513004001.GC22911@verge.net.au>
Message-ID: <5190E4E9.20100@cogentembedded.com>

On 13.05.2013 4:40, Simon Horman wrote:
> [ CC Laurent ]

>>> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

>>> ---

>>> This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".

[...]

>>> diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
>>> index 6a1ba38..0b8112d 100644
>>> --- a/arch/arm/mach-shmobile/board-lager.c
>>> +++ b/arch/arm/mach-shmobile/board-lager.c
>> [...]
>>> @@ -59,6 +69,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
>>>   	/* SCIF1 (CN20: DEBUG SERIAL1) */
>>>   	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
>>>   				  "scif1_data", "scif1"),
>>> +	/* Ether */
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
>>> +				  "eth_link", "eth"),
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
>>> +				  "eth_magic", "eth"),
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
>>> +				  "eth_mdio", "eth"),
>>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
>>> +				  "eth_rmii", "eth"),

>>      I thought MDIO bus was a part of RMII. At least Wikipedia told
>> me so. :-)

> Is the implication that you think that the eth_mdio and eth_rmii
> groups should be combined?

     Well, yes.

WBR, Sergei



From shawn.guo at linaro.org  Mon May 13 09:05:02 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 May 2013 21:05:02 +0800
Subject: [PATCH v2 3/3] ARM: imx: create mxc_arch_reset_init_dt() for DT boot
In-Reply-To: <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
Message-ID: <1368450302-9579-1-git-send-email-shawn.guo@linaro.org>

The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to
get clock.  It's suitable for non-DT boot but not for DT boot where
dynamic mapping and of_clk_get() should be used instead.  Create
mxc_arch_reset_init_dt() as the DT variant of mxc_arch_reset_init(),
and change DT platforms to use it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
Changes since v1:
 * Rename the new function as mxc_arch_reset_init_dt()

 arch/arm/mach-imx/common.h     |    1 +
 arch/arm/mach-imx/imx25-dt.c   |    3 +--
 arch/arm/mach-imx/imx27-dt.c   |    3 +--
 arch/arm/mach-imx/imx31-dt.c   |    3 +--
 arch/arm/mach-imx/imx51-dt.c   |    3 +--
 arch/arm/mach-imx/mach-imx53.c |    2 +-
 arch/arm/mach-imx/system.c     |   20 ++++++++++++++++++++
 7 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f..963971e1 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -74,6 +74,7 @@ extern struct platform_device *mxc_register_gpio(char *name, int id,
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_restart(char, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc_arch_reset_init_dt(void);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index ec33991..3e1ec5f 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -15,12 +15,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "common.h"
-#include "hardware.h"
 #include "mx25.h"
 
 static void __init imx25_dt_init(void)
 {
-	mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+	mxc_arch_reset_init_dt();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 93aef1a..4e235ec 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -16,14 +16,13 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "hardware.h"
 #include "mx27.h"
 
 static void __init imx27_dt_init(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
-	mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+	mxc_arch_reset_init_dt();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index d8b3b22..818a1cc 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -16,12 +16,11 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "hardware.h"
 #include "mx31.h"
 
 static void __init imx31_dt_init(void)
 {
-	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+	mxc_arch_reset_init_dt();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 55f47a0..53e43e5 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -17,14 +17,13 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "hardware.h"
 #include "mx51.h"
 
 static void __init imx51_dt_init(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
-	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+	mxc_arch_reset_init_dt();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 7a56561..74e7b94c 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -39,7 +39,7 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
-	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+	mxc_arch_reset_init_dt();
 
 	if (of_machine_is_compatible("fsl,imx53-qsb"))
 		imx53_qsb_init();
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 02cf449..7cdc79a 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
@@ -75,3 +77,21 @@ void __init mxc_arch_reset_init(void __iomem *base)
 
 	clk_prepare(wdog_clk);
 }
+
+void __init mxc_arch_reset_init_dt(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
+	wdog_base = of_iomap(np, 0);
+	WARN_ON(!wdog_base);
+
+	wdog_clk = of_clk_get(np, 0);
+	if (IS_ERR(wdog_clk)) {
+		pr_warn("%s: failed to get wdog clock\n", __func__);
+		wdog_clk = NULL;
+		return;
+	}
+
+	clk_prepare(wdog_clk);
+}
-- 
1.7.9.5




From sergei.shtylyov at cogentembedded.com  Mon May 13 09:07:49 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 13 May 2013 17:07:49 +0400
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: add Ether support
In-Reply-To: <20130513004314.GD22911@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-2-git-send-email-horms+renesas@verge.net.au>
 <518CCB6A.2060303@cogentembedded.com> <20130513004314.GD22911@verge.net.au>
Message-ID: <5190E5A5.8030605@cogentembedded.com>

Hello.

On 13-05-2013 4:43, Simon Horman wrote:

>>> Add Ether clock and platform device for R8A7779 SoC; add a function to
>>> register this device with board-specific platform data.

>>> Based on a similar change for the r8a7779 by Sergei Shtylyov.

>>> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

[...]

>>> diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
>>> index 2e919e6..95b8f7e 100644
>>> --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
>>> +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
>>> @@ -1,9 +1,12 @@
>>>   #ifndef __ASM_R8A7790_H__
>>>   #define __ASM_R8A7790_H__
>>>
>>> +#include <linux/sh_eth.h>
>>> +
>>>   void r8a7790_add_standard_devices(void);
>>>   void r8a7790_clock_init(void);
>>>   void r8a7790_pinmux_init(void);
>>>   void r8a7790_timer_init(void);
>>> +void r8a7790_add_ether_device(struct sh_eth_plat_data *pdata);

>>     Perhaps better place is right after r8a7790_add_standard_devices()...

> Is the implication that the struct sh_eth_plat_data can be defined
> in setup-r8a7790.c?

    No, why?

> Or do you for see adding a struct sh_eth_plat_data
> parameter to r8a7790_add_standard_devices() ?

    Not at all.

WBR, Sergei



From sergei.shtylyov at cogentembedded.com  Mon May 13 09:17:48 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 13 May 2013 17:17:48 +0400
Subject: [PATCH] ARM: shmobile: r8a7778: correct model name in Kconfig
In-Reply-To: <20130513013320.GD7826@verge.net.au>
References: <201305090405.41053.sergei.shtylyov@cogentembedded.com>
 <20130510082055.GB27435@verge.net.au> <518D4CCF.5040706@cogentembedded.com>
 <87obcfn350.wl%kuninori.morimoto.gx@renesas.com>
 <20130513013320.GD7826@verge.net.au>
Message-ID: <5190E7FC.5040809@cogentembedded.com>

On 13-05-2013 5:33, Simon Horman wrote:

>>>>> The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
>>>>> M1S which is a SH based SoC.

>>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>>> Morimoto-san,

>>>> please review this change.


>>>      This patch was based on the info found on this official Renesas webpage:

>>> http://www.renesas.eu/applications/automotive/cis/cis_highend/rcar_m1as/index.jsp

>> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>


> Thanks, I have queued-up the following in the soc-r8a7778 branch.
> There was a trivial conflict which I resolved. Please let me know
> if I messed it up.

    It's alright, thanks. I'm just not sure this fix is worth deferring 
for several more months...

WBR, Sergei



From sergei.shtylyov at cogentembedded.com  Mon May 13 09:25:50 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 13 May 2013 17:25:50 +0400
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
Message-ID: <5190E9DE.6000502@cogentembedded.com>

On 13-05-2013 12:53, Simon Horman wrote:

> The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
> This patch allows access to those pins as KEYS 1 - 4 using
> gpio-keys.

> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

[...]

> diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
> index 6a1ba38..4d1b42b 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
[...]
> @@ -52,6 +55,22 @@ static struct gpio_led_platform_data lager_leds_pdata = {
>   	.num_leds	= ARRAY_SIZE(lager_leds),
>   };
>
> +/* GPIO KEY */
> +#define GPIO_KEY(c, g, d, ...) \
> +	{ .code = c, .gpio = g, .desc = d, .active_low = 1 }
> +
> +static struct gpio_keys_button gpio_buttons[] = {
> +	GPIO_KEY(KEY_4,		RCAR_GP_PIN(1, 28),	"SW2-pin4"),
> +	GPIO_KEY(KEY_3,		RCAR_GP_PIN(1, 26),	"SW2-pin3"),
> +	GPIO_KEY(KEY_2,		RCAR_GP_PIN(1, 24),	"SW2-pin2"),
> +	GPIO_KEY(KEY_1,		RCAR_GP_PIN(1, 14),	"SW2-pin1"),
> +};
> +
> +static struct gpio_keys_platform_data lager_keys_pdata = {

    You forgot to annotate this with __initdata.

> +	.buttons	= gpio_buttons,
> +	.nbuttons	= ARRAY_SIZE(gpio_buttons),
> +};
> +
>   static const struct pinctrl_map lager_pinctrl_map[] = {
>   	/* SCIF0 (CN19: DEBUG SERIAL0) */
>   	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
> @@ -73,6 +92,9 @@ static void __init lager_add_standard_devices(void)
>   	platform_device_register_data(&platform_bus, "leds-gpio", -1,
>   				      &lager_leds_pdata,
>   				      sizeof(lager_leds_pdata));
> +	platform_device_register_data(&platform_bus, "gpio-keys", -1,
> +				      &lager_keys_pdata,
> +				      sizeof(lager_keys_pdata));
>   }

WBR, Sergei




From ulf.hansson at stericsson.com  Mon May 13 09:47:16 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 15:47:16 +0200
Subject: [PATCH 2/3] mmc: mmci: Adapt to register write restrictions
In-Reply-To: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368452837-31458-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

After a write to the MMCICLOCK register data cannot be written to this
register for three feedback clock cycles. Writes to the MMCIPOWER
register must be separated by three MCLK cycles. Previously no issues
has been observered, but using higher ARM clock frequencies on STE-
platforms has triggered this problem.

The MMCICLOCK register is written to in .set_ios and for some data
transmissions for SDIO. We do not need a delay at the data transmission
path, because sending and receiving data will require more than three
clock cycles. Then we use a simple logic to only delay in .set_ios and
thus we don't affect throughput performance.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Signed-off-by: Johan Rudholm <jrudholm at gmail.com>
---
 drivers/mmc/host/mmci.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 98b0c16..7815816 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -166,6 +166,21 @@ static int mmci_validate_data(struct mmci_host *host,
 	return 0;
 }
 
+static void mmci_reg_delay(struct mmci_host *host)
+{
+	/*
+	 * According to the spec, at least three feedback clock cycles
+	 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
+	 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
+	 * Worst delay time during card init is at 100 kHz => 30 us.
+	 * Worst delay time when up and running is at 25 MHz => 120 ns.
+	 */
+	if (host->cclk < 20000000)
+		udelay(30);
+	else
+		ndelay(120);
+}
+
 /*
  * This must be called with host->lock held
  */
@@ -1212,6 +1227,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	mmci_set_clkreg(host, ios->clock);
 	mmci_write_pwrreg(host, pwr);
+	mmci_reg_delay(host);
 
 	spin_unlock_irqrestore(&host->lock, flags);
 
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon May 13 09:47:15 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 15:47:15 +0200
Subject: [PATCH 1/3] mmc: mmci: Use optional sleep pinctrl state
In-Reply-To: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368452837-31458-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

By optionally putting the pins into sleep state in the .runtime_suspend
callback we can accomplish two things. One is to minimize current leakage
from pins and thus save power, second we can prevent the IP from driving
pins output in an uncontrolled manner, which may happen if the power domain
drops the domain regulator.

When returning from idle, entering .runtime_resume callback, the pins
are restored to default state.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   16 ++++++++++++++++
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038..98b0c16 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1437,6 +1437,12 @@ static int mmci_probe(struct amba_device *dev,
 	} else
 		dev_warn(&dev->dev, "could not get default pinstate\n");
 
+	/* fetch optional sleep state of pins */
+	host->pins_sleep = pinctrl_lookup_state(host->pinctrl,
+			PINCTRL_STATE_SLEEP);
+	if (IS_ERR(host->pins_sleep))
+		dev_dbg(&dev->dev, "could not get sleep pinstate\n");
+
 	/* Get regulators and the supported OCR mask */
 	mmc_regulator_get_supply(mmc);
 	if (!mmc->ocr_avail)
@@ -1680,6 +1686,11 @@ static int mmci_runtime_suspend(struct device *dev)
 
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
+
+		/* Optionally let pins go into sleep state */
+		if (!IS_ERR(host->pins_sleep))
+			pinctrl_select_state(host->pinctrl, host->pins_sleep);
+
 		clk_disable_unprepare(host->clk);
 	}
 
@@ -1693,7 +1704,12 @@ static int mmci_runtime_resume(struct device *dev)
 
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
+
 		clk_prepare_enable(host->clk);
+
+		/* Optionally enable pins to be muxed in and configured */
+		if (!IS_ERR(host->pins_default))
+			pinctrl_select_state(host->pinctrl, host->pins_default);
 	}
 
 	return 0;
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 1f33ad5..4e68c4c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -199,6 +199,7 @@ struct mmci_host {
 	/* pinctrl handles */
 	struct pinctrl		*pinctrl;
 	struct pinctrl_state	*pins_default;
+	struct pinctrl_state	*pins_sleep;
 
 #ifdef CONFIG_DMA_ENGINE
 	/* DMA stuff */
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon May 13 09:47:17 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 15:47:17 +0200
Subject: [PATCH 3/3] mmc: mmci: Save and restore register context
In-Reply-To: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368452837-31458-4-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

If a corresponding power domain exists for the device and it manages
to cut the domain regulator while the device is runtime suspended,
the IP loses it's registers context. We restore the context in the
.runtime_resume callback from the existing register caches to adapt
to this siutuation.

We also want to make sure the registers are in a known state while
restoring context in the case when the power domain did not drop the
power, since there are restrictions for the order of writing to these
registers. To handle this, we clear the registers in the
.runtime_suspend callback.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7815816..790d744 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -61,6 +61,7 @@ static unsigned int fmax = 515633;
  * @pwrreg_powerup: power up value for MMCIPOWER register
  * @signal_direction: input/out direction of bus signals can be indicated
  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
+ * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
  */
 struct variant_data {
 	unsigned int		clkreg;
@@ -74,6 +75,7 @@ struct variant_data {
 	u32			pwrreg_powerup;
 	bool			signal_direction;
 	bool			pwrreg_clkgate;
+	bool			pwrreg_nopower;
 };
 
 static struct variant_data variant_arm = {
@@ -107,6 +109,7 @@ static struct variant_data variant_u300 = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.pwrreg_nopower		= true,
 };
 
 static struct variant_data variant_nomadik = {
@@ -119,6 +122,7 @@ static struct variant_data variant_nomadik = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.pwrreg_nopower		= true,
 };
 
 static struct variant_data variant_ux500 = {
@@ -132,6 +136,7 @@ static struct variant_data variant_ux500 = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.pwrreg_nopower		= true,
 };
 
 static struct variant_data variant_ux500v2 = {
@@ -146,6 +151,7 @@ static struct variant_data variant_ux500v2 = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.pwrreg_nopower		= true,
 };
 
 /*
@@ -1695,6 +1701,39 @@ static int mmci_resume(struct device *dev)
 #endif
 
 #ifdef CONFIG_PM_RUNTIME
+static void mmci_save(struct mmci_host *host)
+{
+	unsigned long flags;
+
+	if (host->variant->pwrreg_nopower) {
+		spin_lock_irqsave(&host->lock, flags);
+
+		writel(0, host->base + MMCIMASK0);
+		writel(0, host->base + MMCIPOWER);
+		writel(0, host->base + MMCICLOCK);
+		mmci_reg_delay(host);
+
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+
+}
+
+static void mmci_restore(struct mmci_host *host)
+{
+	unsigned long flags;
+
+	if (host->variant->pwrreg_nopower) {
+		spin_lock_irqsave(&host->lock, flags);
+
+		writel(host->clk_reg, host->base + MMCICLOCK);
+		writel(host->pwr_reg, host->base + MMCIPOWER);
+		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+		mmci_reg_delay(host);
+
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+}
+
 static int mmci_runtime_suspend(struct device *dev)
 {
 	struct amba_device *adev = to_amba_device(dev);
@@ -1707,6 +1746,7 @@ static int mmci_runtime_suspend(struct device *dev)
 		if (!IS_ERR(host->pins_sleep))
 			pinctrl_select_state(host->pinctrl, host->pins_sleep);
 
+		mmci_save(host);
 		clk_disable_unprepare(host->clk);
 	}
 
@@ -1722,6 +1762,7 @@ static int mmci_runtime_resume(struct device *dev)
 		struct mmci_host *host = mmc_priv(mmc);
 
 		clk_prepare_enable(host->clk);
+		mmci_restore(host);
 
 		/* Optionally enable pins to be muxed in and configured */
 		if (!IS_ERR(host->pins_default))
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon May 13 09:47:14 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 15:47:14 +0200
Subject: [PATCH 0/3] mmc: mmci: Support ap_sleep in cpuidle for ux500
Message-ID: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

To be able to enter ap_sleep state in cpuidle were the APE power domain
regulator will be cut, a register save and restore mechanism needs to be
implemented. This patchset adapts to these restrictions.

Ulf Hansson (3):
  mmc: mmci: Use optional sleep pinctrl state
  mmc: mmci: Adapt to register write restrictions
  mmc: mmci: Save and restore register context

 drivers/mmc/host/mmci.c |   73 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 74 insertions(+)

-- 
1.7.10



From robdclark at gmail.com  Mon May 13 09:48:25 2013
From: robdclark at gmail.com (Rob Clark)
Date: Mon, 13 May 2013 09:48:25 -0400
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
Message-ID: <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>

On Mon, May 13, 2013 at 8:21 AM, Inki Dae <inki.dae at samsung.com> wrote:
>
>> In that case you still wouldn't give userspace control over the fences. I
>> don't see any way that can end well.
>> What if userspace never signals? What if userspace gets killed by oom
>> killer. Who keeps track of that?
>>
>
> In all cases, all kernel resources to user fence will be released by kernel
> once the fence is timed out: never signaling and process killing by oom
> killer makes the fence timed out. And if we use mmap mechanism you mentioned
> before, I think user resource could also be freed properly.


I tend to agree w/ Maarten here.. there is no good reason for
userspace to be *signaling* fences.  The exception might be some blob
gpu drivers which don't have enough knowledge in the kernel to figure
out what to do.  (In which case you can add driver private ioctls for
that.. still not the right thing to do but at least you don't make a
public API out of it.)

BR,
-R


From ulf.hansson at stericsson.com  Mon May 13 09:56:33 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 15:56:33 +0200
Subject: [PATCH] mmc: mmci: Use devm_clk_get API
Message-ID: <1368453393-1272-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Converting to devm_clk_get simplifies error handling in probe
and we can remove other corresponding calls to clk_put.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |    8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038..d57ce43 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1362,16 +1362,15 @@ static int mmci_probe(struct amba_device *dev,
 	dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
 	dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
 
-	host->clk = clk_get(&dev->dev, NULL);
+	host->clk = devm_clk_get(&dev->dev, NULL);
 	if (IS_ERR(host->clk)) {
 		ret = PTR_ERR(host->clk);
-		host->clk = NULL;
 		goto host_free;
 	}
 
 	ret = clk_prepare_enable(host->clk);
 	if (ret)
-		goto clk_free;
+		goto host_free;
 
 	host->plat = plat;
 	host->variant = variant;
@@ -1576,8 +1575,6 @@ static int mmci_probe(struct amba_device *dev,
 	iounmap(host->base);
  clk_disable:
 	clk_disable_unprepare(host->clk);
- clk_free:
-	clk_put(host->clk);
  host_free:
 	mmc_free_host(mmc);
  rel_regions:
@@ -1623,7 +1620,6 @@ static int mmci_remove(struct amba_device *dev)
 
 		iounmap(host->base);
 		clk_disable_unprepare(host->clk);
-		clk_put(host->clk);
 
 		mmc_free_host(mmc);
 
-- 
1.7.10



From stern at rowland.harvard.edu  Mon May 13 10:13:44 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Mon, 13 May 2013 10:13:44 -0400 (EDT)
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <1368424303-10629-5-git-send-email-chao.xie@marvell.com>
Message-ID: <Pine.LNX.4.44L0.1305131012090.1389-100000@iolanthe.rowland.org>

On Mon, 13 May 2013, Chao Xie wrote:

> Originaly, ehci driver will call the callbacks in platform data
> for PHY initialization and shut down.
> With PHY driver, it will call the APIs provided by PHY driver
> for PHY initialization and shutdown. It removes the callbacks
> in platform data, and at same time it removes one block in the
> way of enabling device tree for ehci driver.

I wonder if this is the sort of thing that should be handled in 
ehci-hcd.c rather than in all the different platform glue drivers.

Felipe, what do you think?  Are the required actions now sufficiently 
generic that a single source file can take care of them?

Alan Stern



From ulf.hansson at stericsson.com  Mon May 13 10:18:39 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 16:18:39 +0200
Subject: [PATCH] mmc: mmci: Set actual clock for debug purpose
Message-ID: <1368454719-16420-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Update cclk to the acutal used value and copy it to the actual_clock
variable in the mmc host for debug purpose.

Signed-off-by: Fredrik Soderstedt <fredrik.soderstedt at stericsson.com>
Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038..1170c9c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -196,6 +196,9 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 	struct variant_data *variant = host->variant;
 	u32 clk = variant->clkreg;
 
+	/* Make sure cclk reflects the current calculated clock */
+	host->cclk = 0;
+
 	if (desired) {
 		if (desired >= host->mclk) {
 			clk = MCI_CLK_BYPASS;
@@ -230,6 +233,9 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 		/* clk |= MCI_CLK_PWRSAVE; */
 	}
 
+	/* Set actual clock for debug */
+	host->mmc->actual_clock = host->cclk;
+
 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
 		clk |= MCI_4BIT_BUS;
 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon May 13 10:33:32 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 13 May 2013 16:33:32 +0200
Subject: [PATCH] mmc: mmci: Support for CMD23
Message-ID: <1368455612-20786-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Support added for transmission of CMD23 during multi block read or
write. In order to activate this feature, MMC_CAP_CMD23 flag needs
to be enabled in the capabilities field. Note that CMD23 support is
mandatory to support features like reliable write, data tag, context
ID, packed command.

This patch is based upon a patch from Saugata Das.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/mmc/host/mmci.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038..27f29bb 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -842,7 +842,7 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 			/* The error clause is handled above, success! */
 			data->bytes_xfered = data->blksz * data->blocks;
 
-		if (!data->stop) {
+		if (!data->stop || host->mrq->sbc) {
 			mmci_request_end(host, data->mrq);
 		} else {
 			mmci_start_command(host, data->stop, 0);
@@ -855,6 +855,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 	     unsigned int status)
 {
 	void __iomem *base = host->base;
+	bool sbc = (cmd == host->mrq->sbc);
 
 	host->cmd = NULL;
 
@@ -869,7 +870,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 		cmd->resp[3] = readl(base + MMCIRESPONSE3);
 	}
 
-	if (!cmd->data || cmd->error) {
+	if ((!sbc && !cmd->data) || cmd->error) {
 		if (host->data) {
 			/* Terminate the DMA transfer */
 			if (dma_inprogress(host)) {
@@ -878,7 +879,9 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 			}
 			mmci_stop_data(host);
 		}
-		mmci_request_end(host, cmd->mrq);
+		mmci_request_end(host, host->mrq);
+	} else if (sbc) {
+		mmci_start_command(host, host->mrq->cmd, 0);
 	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
 		mmci_start_data(host, cmd->data);
 	}
@@ -1119,7 +1122,10 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 		mmci_start_data(host, mrq->data);
 
-	mmci_start_command(host, mrq->cmd, 0);
+	if (mrq->sbc)
+		mmci_start_command(host, mrq->sbc, 0);
+	else
+		mmci_start_command(host, mrq->cmd, 0);
 
 	spin_unlock_irqrestore(&host->lock, flags);
 }
-- 
1.7.10



From thomas.petazzoni at free-electrons.com  Mon May 13 10:59:06 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 13 May 2013 16:59:06 +0200
Subject: Board file to device tree migration
In-Reply-To: <CAGGh5h3MC=ruocV9u6Cig=oiTtqU8GtpQ6sRKUZmUNk-C7Houw@mail.gmail.com>
References: <CAGGh5h3MC=ruocV9u6Cig=oiTtqU8GtpQ6sRKUZmUNk-C7Houw@mail.gmail.com>
Message-ID: <20130513165906.7cbcafcd@skate>

Dear jean-philippe francois,

On Mon, 13 May 2013 11:44:04 +0200, jean-philippe francois wrote:

> I am maintaining a board file, which i did not submit since the board
> was developped after the decision was taken to move to device tree,
> and I figured no more board file would be accepted.
> 
> I can't move to full device tree, since if my understanding is
> correct, the omap3-isp is not supported yet, and our board is a
> camera, so isp is mandatory.
> 
> My question is, is it possible to do a mixed style init, with some of
> the devices coming from a board file, and others from a dts file ? Is
> there any example of board using this kind of mixed init ?

Yes. We do this for many Marvell Kirkwood boards. For example, in
mach-kirkwood/board-dt.c, we have:

static void __init kirkwood_dt_init(void)
{
	[...]
        if (of_machine_is_compatible("globalscale,dreamplug"))
                dreamplug_init();

        if (of_machine_is_compatible("globalscale,guruplug"))
                guruplug_dt_init();
	[...]
}

DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
	[...]
        .init_machine   = kirkwood_dt_init,
	[...]
MACHINE_END

And then dreamplug_init(), guruplug_dt_init() are in their own board
file, and register the devices for which the driver does not (yet) have
a DT binding.

OMAP doesn't seem to do this much, but if you look at
mach-omap2/board-generic.c, you'll see that it is done for some display
devices:

static void __init omap_generic_init(void)
{
        omap_sdrc_init(NULL, NULL);

        of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);

        /*
         * HACK: call display setup code for selected boards to enable omapdss.
         * This will be removed when omapdss supports DT.
         */
        if (of_machine_is_compatible("ti,omap4-panda"))
                omap4_panda_display_init_of();
        else if (of_machine_is_compatible("ti,omap4-sdp"))
                omap_4430sdp_display_init_of();
}

I think having a mixed-style init is a very good thing, because it
allows a progressive and smooth migration the Device Tree, but the
reason why it is not more widespread in the OMAP world is unknown to me.

Maybe the OMAP maintainers can comment? I've Cc'ed Tony.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From s.hauer at pengutronix.de  Mon May 13 10:59:50 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 May 2013 16:59:50 +0200
Subject: [PATCH v2 3/3] ARM: imx: create mxc_arch_reset_init_dt() for DT
 boot
In-Reply-To: <1368450302-9579-1-git-send-email-shawn.guo@linaro.org>
References: <1368408728-12264-4-git-send-email-shawn.guo@linaro.org>
 <1368450302-9579-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130513145950.GU32299@pengutronix.de>

On Mon, May 13, 2013 at 09:05:02PM +0800, Shawn Guo wrote:
> The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to
> get clock.  It's suitable for non-DT boot but not for DT boot where
> dynamic mapping and of_clk_get() should be used instead.  Create
> mxc_arch_reset_init_dt() as the DT variant of mxc_arch_reset_init(),
> and change DT platforms to use it.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

(For the whole series)

Sascha

> ---
> Changes since v1:
>  * Rename the new function as mxc_arch_reset_init_dt()
> 
>  arch/arm/mach-imx/common.h     |    1 +
>  arch/arm/mach-imx/imx25-dt.c   |    3 +--
>  arch/arm/mach-imx/imx27-dt.c   |    3 +--
>  arch/arm/mach-imx/imx31-dt.c   |    3 +--
>  arch/arm/mach-imx/imx51-dt.c   |    3 +--
>  arch/arm/mach-imx/mach-imx53.c |    2 +-
>  arch/arm/mach-imx/system.c     |   20 ++++++++++++++++++++
>  7 files changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index c08ae3f..963971e1 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -74,6 +74,7 @@ extern struct platform_device *mxc_register_gpio(char *name, int id,
>  extern void mxc_set_cpu_type(unsigned int type);
>  extern void mxc_restart(char, const char *);
>  extern void mxc_arch_reset_init(void __iomem *);
> +extern void mxc_arch_reset_init_dt(void);
>  extern int mx53_revision(void);
>  extern int imx6q_revision(void);
>  extern int mx53_display_revision(void);
> diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
> index ec33991..3e1ec5f 100644
> --- a/arch/arm/mach-imx/imx25-dt.c
> +++ b/arch/arm/mach-imx/imx25-dt.c
> @@ -15,12 +15,11 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/time.h>
>  #include "common.h"
> -#include "hardware.h"
>  #include "mx25.h"
>  
>  static void __init imx25_dt_init(void)
>  {
> -	mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
> +	mxc_arch_reset_init_dt();
>  
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
> diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
> index 93aef1a..4e235ec 100644
> --- a/arch/arm/mach-imx/imx27-dt.c
> +++ b/arch/arm/mach-imx/imx27-dt.c
> @@ -16,14 +16,13 @@
>  #include <asm/mach/time.h>
>  
>  #include "common.h"
> -#include "hardware.h"
>  #include "mx27.h"
>  
>  static void __init imx27_dt_init(void)
>  {
>  	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
>  
> -	mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
> +	mxc_arch_reset_init_dt();
>  
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  
> diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
> index d8b3b22..818a1cc 100644
> --- a/arch/arm/mach-imx/imx31-dt.c
> +++ b/arch/arm/mach-imx/imx31-dt.c
> @@ -16,12 +16,11 @@
>  #include <asm/mach/time.h>
>  
>  #include "common.h"
> -#include "hardware.h"
>  #include "mx31.h"
>  
>  static void __init imx31_dt_init(void)
>  {
> -	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
> +	mxc_arch_reset_init_dt();
>  
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
> diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
> index 55f47a0..53e43e5 100644
> --- a/arch/arm/mach-imx/imx51-dt.c
> +++ b/arch/arm/mach-imx/imx51-dt.c
> @@ -17,14 +17,13 @@
>  #include <asm/mach/time.h>
>  
>  #include "common.h"
> -#include "hardware.h"
>  #include "mx51.h"
>  
>  static void __init imx51_dt_init(void)
>  {
>  	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
>  
> -	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
> +	mxc_arch_reset_init_dt();
>  
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  	platform_device_register_full(&devinfo);
> diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
> index 7a56561..74e7b94c 100644
> --- a/arch/arm/mach-imx/mach-imx53.c
> +++ b/arch/arm/mach-imx/mach-imx53.c
> @@ -39,7 +39,7 @@ static void __init imx53_qsb_init(void)
>  
>  static void __init imx53_dt_init(void)
>  {
> -	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
> +	mxc_arch_reset_init_dt();
>  
>  	if (of_machine_is_compatible("fsl,imx53-qsb"))
>  		imx53_qsb_init();
> diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
> index 02cf449..7cdc79a 100644
> --- a/arch/arm/mach-imx/system.c
> +++ b/arch/arm/mach-imx/system.c
> @@ -21,6 +21,8 @@
>  #include <linux/io.h>
>  #include <linux/err.h>
>  #include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
>  
>  #include <asm/system_misc.h>
>  #include <asm/proc-fns.h>
> @@ -75,3 +77,21 @@ void __init mxc_arch_reset_init(void __iomem *base)
>  
>  	clk_prepare(wdog_clk);
>  }
> +
> +void __init mxc_arch_reset_init_dt(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
> +	wdog_base = of_iomap(np, 0);
> +	WARN_ON(!wdog_base);
> +
> +	wdog_clk = of_clk_get(np, 0);
> +	if (IS_ERR(wdog_clk)) {
> +		pr_warn("%s: failed to get wdog clock\n", __func__);
> +		wdog_clk = NULL;
> +		return;
> +	}
> +
> +	clk_prepare(wdog_clk);
> +}
> -- 
> 1.7.9.5
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From cov at codeaurora.org  Mon May 13 11:14:06 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 13 May 2013 11:14:06 -0400
Subject: [RFC PATCH 0/2] ARM: Remove any correlation between IPC and
 BogoMips value
In-Reply-To: <20130508090644.GA15692@mudshark.cambridge.arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <5187EFF3.6010005@codeaurora.org>
 <20130507090849.GC25387@mudshark.cambridge.arm.com>
 <5189224A.70501@codeaurora.org>
 <20130508090644.GA15692@mudshark.cambridge.arm.com>
Message-ID: <5191033E.2000303@codeaurora.org>

Hi Will,

On 05/08/2013 05:06 AM, Will Deacon wrote:
> Hello Christopher,
> 
> On Tue, May 07, 2013 at 04:48:26PM +0100, Christopher Covington wrote:
>> On 05/07/2013 05:08 AM, Will Deacon wrote:
>>> That seems like a lot of effort in order to preserve something that isn't
>>> even meaningful. We might be better just zeroing the value, but then we'll
>>> inevitably get bug reports of it being `wrong'.
>>
>> If I were in to filing bug reports about bogomips values, I would be just as
>> likely to do it for 1, 10000, 99999, and get_random_bytes(...) as for 0.
> 
> That's a fair point, and one of the reasons I posted this as an RFC. I'd
> basically like an `obviously bogus' value so that people don't think `hey,
> my CPU sure it slow' and instead think `looks like this really is a bogus
> value after all'.
> 
> However, you're probably right that there isn't a number which can convey
> that information properly, so how about we just put a string in there along
> the lines of "not reported" and leave it at that?

That sounds reasonable to me.

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From jason at lakedaemon.net  Mon May 13 11:19:34 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 11:19:34 -0400
Subject: [PATCH 09/14] ARM: mvebu: Remove init_irq declaration in
 machine description
In-Reply-To: <1368438253-28218-10-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-10-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130513151934.GM31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 11:44:08AM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for mvebu as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-mvebu/armada-370-xp.c | 1 -
>  1 file changed, 1 deletion(-)

Maxime,

Do do want the individual submaintainers to take these?  Or, send one
branch to Arnd and Olof?  I'm fine with either one as any merge
conflicts should be trivial.

In either case,

Acked-by: Jason Cooper <jason at lakedaemon.net>

thx,

Jason.


From elezegarcia at gmail.com  Mon May 13 11:22:53 2013
From: elezegarcia at gmail.com (Ezequiel Garcia)
Date: Mon, 13 May 2013 12:22:53 -0300
Subject: [PATCH] ARM: mvebu: Add a ranges entry to translate devbus childs
Message-ID: <1368458573-18043-1-git-send-email-elezegarcia@gmail.com>

From: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>

With the latest device tree reorganization which introduced the
'internal-reg' node, now the only region translated is the internal register's.
This makes the description of the hardware incomplete, for it lacks the
Device Bus childs address space.

In order to fix this, it's required to add a 'ranges' entry with a suitable
address space to map Device Bus childs, on a per-board basis.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
---
Applies on v3.10-rc1. This is meant for v3.10.

 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index f14d36c..46b7850 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,6 +27,9 @@
 	};
 
 	soc {
+		ranges = <0          0 0xd0000000 0x100000
+			  0xf0000000 0 0xf0000000 0x8000000>;
+
 		internal-regs {
 			serial at 12000 {
 				clock-frequency = <250000000>;
-- 
1.8.1.5



From cov at codeaurora.org  Mon May 13 11:23:05 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 13 May 2013 11:23:05 -0400
Subject: [PATCH V2] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
In-Reply-To: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org>
References: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org>
Message-ID: <51910559.6060106@codeaurora.org>

Hi Pranavkumar,

On 05/10/2013 03:23 AM, Pranavkumar Sawargaonkar wrote:
> This patch does following fixes:
> 
> 1. Make HCR_* flags as unsigned long long constants
> Reason : By default, compiler assumes numeric constants as
> signed hence sign extending it when assigned to unsigned variable
> such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
> HCR_CD making entire guest memory non-cacheable. On real HW, this
> breaks Stage2 ttbl walks and also breaks VirtIO.
> 
> 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.
> 
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> ---
>  arch/arm64/include/asm/kvm_arm.h |   73 +++++++++++++++++++-------------------
>  1 file changed, 37 insertions(+), 36 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
> index 8ced0ca..14ead69 100644
> --- a/arch/arm64/include/asm/kvm_arm.h
> +++ b/arch/arm64/include/asm/kvm_arm.h
> @@ -18,44 +18,45 @@
>  #ifndef __ARM64_KVM_ARM_H__
>  #define __ARM64_KVM_ARM_H__
>  
> +#include <linux/const.h>
>  #include <asm/types.h>
>  
>  /* Hyp Configuration Register (HCR) bits */
> -#define HCR_ID		(1 << 33)
> -#define HCR_CD		(1 << 32)
> +#define HCR_ID		(UL(0x1) << 33)
> +#define HCR_CD		(UL(0x1) << 32)

Consider using the BIT() macro from linux/bitops.h to improve readability.

[...]

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From cdall at cs.columbia.edu  Mon May 13 11:46:44 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 13 May 2013 08:46:44 -0700
Subject: [PATCH v3 30/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <5190AC05.5000304@arm.com>
References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com>
 <1365437854-30214-31-git-send-email-marc.zyngier@arm.com>
 <20130423230229.GN20569@gmail.com> <5177E303.7050801@arm.com>
 <CAEDV+g+OL+37w9jA8=0WGea5FgW5y3mazqFzv9GLxDgjCe6dtg@mail.gmail.com>
 <51892DA4.4050401@arm.com> <20130511003842.GE30999@chazy>
 <5190AC05.5000304@arm.com>
Message-ID: <20130513154644.GA3529@ubuntu>

On Mon, May 13, 2013 at 10:01:57AM +0100, Marc Zyngier wrote:
> On 11/05/13 01:38, Christoffer Dall wrote:
> > On Tue, May 07, 2013 at 05:36:52PM +0100, Marc Zyngier wrote:
> >> On 24/04/13 18:17, Christoffer Dall wrote:
> >>> On Wed, Apr 24, 2013 at 6:49 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> >>>> On 24/04/13 00:02, Christoffer Dall wrote:
> >>>>> On Mon, Apr 08, 2013 at 05:17:32PM +0100, Marc Zyngier wrote:
> >>>>>> Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
> >>>>>> and providing sensible defaults out of reset state.
> >>>>>>
> >>>>>> This feature is of course conditioned by the presence of 32bit
> >>>>>> capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
> >>>>>> capability.
> >>>>>>
> >>>>>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> >>>>>> ---
> >>>>>>  arch/arm64/include/asm/kvm_host.h |  2 +-
> >>>>>>  arch/arm64/include/uapi/asm/kvm.h |  1 +
> >>>>>>  arch/arm64/kvm/guest.c            |  6 ++++++
> >>>>>>  arch/arm64/kvm/reset.c            | 25 ++++++++++++++++++++++++-
> >>>>>>  include/uapi/linux/kvm.h          |  1 +
> >>>>>>  5 files changed, 33 insertions(+), 2 deletions(-)
> >>>>>>
> >>>>>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> >>>>>> index d44064d..c3ec107 100644
> >>>>>> --- a/arch/arm64/include/asm/kvm_host.h
> >>>>>> +++ b/arch/arm64/include/asm/kvm_host.h
> >>>>>> @@ -34,7 +34,7 @@
> >>>>>>  #include <asm/kvm_vgic.h>
> >>>>>>  #include <asm/kvm_arch_timer.h>
> >>>>>>
> >>>>>> -#define KVM_VCPU_MAX_FEATURES 1
> >>>>>> +#define KVM_VCPU_MAX_FEATURES 2
> >>>>>>
> >>>>>>  /* We don't currently support large pages. */
> >>>>>>  #define KVM_HPAGE_GFN_SHIFT(x)      0
> >>>>>> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> >>>>>> index 5b1110c..5031f42 100644
> >>>>>> --- a/arch/arm64/include/uapi/asm/kvm.h
> >>>>>> +++ b/arch/arm64/include/uapi/asm/kvm.h
> >>>>>> @@ -75,6 +75,7 @@ struct kvm_regs {
> >>>>>>  #define KVM_VGIC_V2_CPU_SIZE                0x2000
> >>>>>>
> >>>>>>  #define KVM_ARM_VCPU_POWER_OFF              0 /* CPU is started in OFF state */
> >>>>>> +#define KVM_ARM_VCPU_EL1_32BIT              1 /* CPU running a 32bit VM */
> >>>>>>
> >>>>>>  struct kvm_vcpu_init {
> >>>>>>      __u32 target;
> >>>>>> diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
> >>>>>> index 47d3729..74ef7d5 100644
> >>>>>> --- a/arch/arm64/kvm/guest.c
> >>>>>> +++ b/arch/arm64/kvm/guest.c
> >>>>>> @@ -93,6 +93,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
> >>>>>>      if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
> >>>>>>              unsigned long mode = (*(unsigned long *)valp) & COMPAT_PSR_MODE_MASK;
> >>>>>>              switch (mode) {
> >>>>>> +            case COMPAT_PSR_MODE_USR:
> >>>>>> +            case COMPAT_PSR_MODE_FIQ:
> >>>>>> +            case COMPAT_PSR_MODE_IRQ:
> >>>>>> +            case COMPAT_PSR_MODE_SVC:
> >>>>>> +            case COMPAT_PSR_MODE_ABT:
> >>>>>> +            case COMPAT_PSR_MODE_UND:
> >>>>>>              case PSR_MODE_EL0t:
> >>>>>>              case PSR_MODE_EL1t:
> >>>>>>              case PSR_MODE_EL1h:
> >>>>>> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
> >>>>>> index bc33e76..a282d35 100644
> >>>>>> --- a/arch/arm64/kvm/reset.c
> >>>>>> +++ b/arch/arm64/kvm/reset.c
> >>>>>> @@ -35,11 +35,27 @@ static struct kvm_regs default_regs_reset = {
> >>>>>>      .regs.pstate = PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
> >>>>>>  };
> >>>>>>
> >>>>>> +static struct kvm_regs default_regs_reset32 = {
> >>>>>> +    .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
> >>>>>> +                    COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
> >>>>>> +};
> >>>>>> +
> >>>>>> +static bool cpu_has_32bit_el1(void)
> >>>>>> +{
> >>>>>> +    u64 pfr0;
> >>>>>> +
> >>>>>> +    pfr0 = read_cpuid(ID_AA64PFR0_EL1);
> >>>>>> +    return !!(pfr0 & 0x20);
> >>>>>
> >>>>> again we don't need the double negation
> >>>>
> >>>> I still hold that it makes things more readable.
> >>>>
> >>>>>> +}
> >>>>>> +
> >>>>>>  int kvm_arch_dev_ioctl_check_extention(long ext)
> >>>>>>  {
> >>>>>>      int r;
> >>>>>>
> >>>>>>      switch (ext) {
> >>>>>> +    case KVM_CAP_ARM_EL1_32BIT:
> >>>>>> +            r = cpu_has_32bit_el1();
> >>>>>> +            break;
> >>>>>>      default:
> >>>>>>              r = 0;
> >>>>>>      }
> >>>>>> @@ -62,7 +78,14 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
> >>>>>>
> >>>>>>      switch (vcpu->arch.target) {
> >>>>>>      default:
> >>>>>> -            cpu_reset = &default_regs_reset;
> >>>>>> +            if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
> >>>>>> +                    if (!cpu_has_32bit_el1())
> >>>>>> +                            return -EINVAL;
> >>>>>
> >>>>> I'm not sure EINVAL is appropriate here, the value specified was not
> >>>>> incorrect, it's that the hardware doesn't support it. ENXIO, ENODEV, and
> >>>>> add that in Documentation/virtual/kvm/api.txt ?
> >>>>
> >>>> Not sure. If you ended up here, it means you tried to start a 32bit
> >>>> guest on a 64bit-only CPU, despite KVM_CAP_ARM_EL1_32BIT telling you
> >>>> that your CPU is not 32bit capable.
> >>>>
> >>>> This is clearly an invalid input, isn't it?
> >>>>
> >>> check the API documentation for this ioctl, I don't think that's the
> >>> type of invalid input meant when describing the meaning of EINVAL. If
> >>> you feel strongly about it of course it's no big deal, but I think
> >>> EINVAL is so overloaded anyway that telling the user something more
> >>> specific would be great, but I'll leave it up to you.
> >>
> >> [bit late on this one...]
> >>
> >> Here's what the documentation says:
> >> <quote>
> >> 4.77 KVM_ARM_VCPU_INIT
> >>
> >> Capability: basic
> >> Architectures: arm, arm64
> >> Type: vcpu ioctl
> >> Parameters: struct struct kvm_vcpu_init (in)
> >> Returns: 0 on success; -1 on error
> >> Errors:
> >>   EINVAL:    the target is unknown, or the combination of features is invalid.
> >>   ENOENT:    a features bit specified is unknown.
> >> </quote>
> >>
> >> When this call fails, it is because you've requested a feature
> >> that is invalid for this CPU. To me, that exactly fits the
> >> EINVAL entry copied above.
> >>
> >> Or am I completely misunderstanding it?
> >>
> > I read the EINVAL to say that you supplied something which is invalid
> > for the software interface and you should fix your user space code.
> 
> Exactly. The code should have checked for the corresponding capability
> before blindly requesting that feature. That's exactly why we have
> capabilities.
> 
> > The fact that you're requesting a feature that your hardware doesn't
> > support is a different thing IMHO.
> 
> Well, if you're allowed to call into this without checking the
> capabilities, then I suggest we remove them, because they are clearly
> superfluous.
> 
I still see a useful distinction, but I don't care enough to keep
arguing.

-Christoffer


From maxime.ripard at free-electrons.com  Mon May 13 11:53:37 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 13 May 2013 17:53:37 +0200
Subject: [PATCH 09/14] ARM: mvebu: Remove init_irq declaration in machine
 description
In-Reply-To: <20130513151934.GM31290@titan.lakedaemon.net>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-10-git-send-email-maxime.ripard@free-electrons.com>
 <20130513151934.GM31290@titan.lakedaemon.net>
Message-ID: <51910C81.5050501@free-electrons.com>

Hi Jason,

Le 13/05/2013 17:19, Jason Cooper a ?crit :
> On Mon, May 13, 2013 at 11:44:08AM +0200, Maxime Ripard wrote:
>> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
>> specified") removed the need to explictly setup the init_irq field in
>> the machine description when using only irqchip_init. Remove that
>> declaration for mvebu as well.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>> ---
>>  arch/arm/mach-mvebu/armada-370-xp.c | 1 -
>>  1 file changed, 1 deletion(-)
> 
> Maxime,
> 
> Do do want the individual submaintainers to take these?  Or, send one
> branch to Arnd and Olof?  I'm fine with either one as any merge
> conflicts should be trivial.

I don't have a strong opinion on this one, I guess both will be fine.
Arnd, Olof, what do you prefer?

I'll probably have to send a v2 anyway, I forgot to remove the include
of the irqchip headers.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From jason at lakedaemon.net  Mon May 13 11:59:51 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 11:59:51 -0400
Subject: [PATCHv1 0/5] Marvell EBU irqchip improvements
In-Reply-To: <20130415194825.GT28693@titan.lakedaemon.net>
References: <1365542778-27959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130415194825.GT28693@titan.lakedaemon.net>
Message-ID: <20130513155951.GN31290@titan.lakedaemon.net>

On Mon, Apr 15, 2013 at 03:48:25PM -0400, Jason Cooper wrote:
> On Tue, Apr 09, 2013 at 11:26:13PM +0200, Thomas Petazzoni wrote:
...
> > Thomas Petazzoni (5):
...
> >   ARM: mvebu: do not duplicate the mpic alias
> 
> I already sent the PR for LPAE, which will conflict with this.  I'll add
> this to mvebu/fixes once v3.9 drops.

Obviously, I meant v3.10-rc1.  mvebu-next/fixes is now mvebu/fixes,
rebased onto v3.10-rc1.  This patch is included.

thx,

Jason.


From monstr at monstr.eu  Mon May 13 11:59:27 2013
From: monstr at monstr.eu (Michal Simek)
Date: Mon, 13 May 2013 17:59:27 +0200
Subject: [RFC] device-tree.git automatic sync from linux.git
In-Reply-To: <1368446352.537.81.camel@zakaz.uk.xensource.com>
References: <1366800525.20256.266.camel@zakaz.uk.xensource.com>
 <5190900D.5020408@monstr.eu> <1368446352.537.81.camel@zakaz.uk.xensource.com>
Message-ID: <51910DDF.9010202@monstr.eu>

On 05/13/2013 01:59 PM, Ian Campbell wrote:
> On Mon, 2013-05-13 at 08:02 +0100, Michal Simek wrote:
>> Just small overview it is a Xilinx soft core cpu where you can even setup
>> some parameters for core itself - multiplier, divider, BS, fpu, cache sizes, etc.
>> You have to also compose the whole system and every platform/configuration is different
>> because you can setup addresses, IP on the bus, IRQs, etc.
>> Based on this configuration we have created tcl script which is able to generate
>> DTS directly from Xilinx design tool and it is working quite well for several years
>> and everybody just use it without any problem.
> 
> That sounds very neat!
> 
> Does this tcl script live in the kernel tree? If so would you think it
> would make sense for it to also migrate to device-tree.git? I'm not at
> all sure if that makes sense but if you think it does please let me know
> which paths need top be carried over.

No. This script is here.
https://github.com/Xilinx/device-tree/tree/master-next

It is tightly connected to Xilinx design tool that's why I don't think it is useful
to add it to any other tree.


>> As you see in your repo there is only one microblaze DTS which is for one of mine
>> ancient configuration which none used.
>> It means from microblaze point of view we can simple remove it from mainline kernel
>> because it is useless.
> 
> That will then naturally get propagated over to device-tree.git.

I will think about it for a while and probably just remove it through my microblaze tree.


>> I also care about arm zynq platform where situation is partially different because
>> zynq is fixed block but you can add others thing to programmable logic.
>> It means for zynq case we are almost in the same situation where every zynq based
>> platform is using different configuration and that's why fpgas are so great.
>>
>> It means for zynq case everybody will need different DTS but will be just good
>> to describe or show binding.
>> Currently we have just one dts for zc702 xilinx reference board.
>>
>> Let's move to my point.
>> Based on our experience all xilinx boards don't depend on any dts in the linux kernel
>> and our users just understand the reason why they should use our tcl script for
>> DTS generation.
>>
>> Back to your point about moving DTSes out of the kernel.
> 
> I suppose you are now commenting on the Phase II bit where maintenance
> of the DTS moves out of linux.git into device-tree.git, rather than
> Phase I work, which is creating a split repo which is automatically
> synchronised from linux.git but maintenance remains in linux.git, i.e.
> what I'm doing here.

ok.

>>  For microblaze - no problem
>> just do it. For arm zynq this is more problematic because there is weird binding
>> for ARM. For example PMU which is out of bus and should be probably in cpu node.
>> Also scu devices, scutimers, watchdog which lie on the bus for our case and we
>> need to use PPI interrupt cpu mask. Different clock binding, maybe pinmux binding, etc.
>>
>> It means from my point of view if binding is correct, no problem to move it
>> out of the kernel. If a kernel patch change binding, it is worth for me to change
>> dts in the kernel too to reflect this change and track this change too.
>> My proposal is, let's clean all DTSes in the arm kernel that all platform use
>> the same binding where all platforms are just correctly described.
> 
> AIUI this split/move isn't intended to change the existing policy, which
> is already that DTS files are supposed to remain compatible across
> kernel versions and that "flag days" are to be avoided. The split is
> supposed to make it harder (if not impossible) to accidentally break
> that policy.
> 
> On the other hand I suppose there is an argument to be made for clearing
> up the cruft *before* making the split.
> 
> Ultimately I think this will be up to Grant & co.

ok.

>> The reaching this point I would suggest that for arm, arm-soc maintainers should
>> keep eyes on any dts binding change and all these changes require ACK from Rob or Grant
>> (like device-tree maintainers).
> 
> Yes, once we move onto Phase II I don't expect it will end up being me
> that is the DTS maintainer -- I expect the maintenance will remain with
> those who take care of it in linux.git today.
> 
> My involvement in Phase I is really just to help out with the transition
> (ulterior motive: the Xen project would also like to use these DTS
> files...) not to perform a "land grab" or take over maintenance etc. I
> certainly don't think I am the right person to become the long term
> maintainer of device-tree.git!

Ok. I see you point right now in connection to different project where
your Phase I make more sense.
Our flow, because of a lot of flexibility in fpga word, is more based on DTS which
we don't have in hand and everyone has to maintain it.
Starting to using not correct DTSes by another project will be problematic.

It is good step but it suggests that they can start to use it but one change
in the kernel binging will caused that it breaks another project.

From my point of view this Phase I is good to do for DTSes which are correct.
Then another project can be sure that they won't change a lot.

I have the same experience with our DTS driven Qemu that it works when description
is stable but till that time it is just pain because you need to be sure
that all binding changes are also done in Qemu.

Thanks,
Michal




-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From jason at lakedaemon.net  Mon May 13 12:01:38 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 12:01:38 -0400
Subject: [PATCH] Kirkwood: Enable PCIe port 1 on QNAP TS-11x/TS-21x
In-Reply-To: <20130429173022.GS32497@titan.lakedaemon.net>
References: <20130421152802.GA1408@jirafa.cyrius.com>
 <20130421154704.GV2824@lunn.ch>
 <20130421161400.GD26943@jirafa.cyrius.com>
 <20130429173022.GS32497@titan.lakedaemon.net>
Message-ID: <20130513160138.GO31290@titan.lakedaemon.net>

On Mon, Apr 29, 2013 at 01:30:22PM -0400, Jason Cooper wrote:
> On Sun, Apr 21, 2013 at 05:14:00PM +0100, Martin Michlmayr wrote:
> > Enable KW_PCIE1 on QNAP TS-11x/TS-21x devices as newer revisions
> > (rev 1.3) have a USB 3.0 chip from Etron on PCIe port 1.  Thanks
> > to Marek Vasut for identifying this issue!
> > 
> > Cc: <stable at kernel.org>
> > Signed-off-by: Martin Michlmayr <tbm at cyrius.com>
> > Tested-by: Marek Vasut <marex at denx.de>
> 
> Applied to mvebu-next/fixes.  This branch will be rebased onto v3.10-rc1
> once it drops.  I'll submit a pull request then.

mvebu-next/fixes is now mvebu/fixes and has been rebased onto
mvebu/fixes.  This patch is included.

thx,

Jason.


From marc.zyngier at arm.com  Mon May 13 12:02:12 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 13 May 2013 18:02:12 +0200
Subject: [PATCH V2] arm64: KVM: Fix
 =?UTF-8?Q?HCR=5FEL=32=20and=20VTCR=5FEL=32?=
 =?UTF-8?Q?=20configuration=20bits?=
In-Reply-To: <51910559.6060106@codeaurora.org>
References: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org>
 <51910559.6060106@codeaurora.org>
Message-ID: <fae8138d41c55928a3c71b7073aea3b0@localhost>

On Mon, 13 May 2013 11:23:05 -0400, Christopher Covington
<cov at codeaurora.org> wrote:
> Hi Pranavkumar,
> 
> On 05/10/2013 03:23 AM, Pranavkumar Sawargaonkar wrote:
>> This patch does following fixes:
>> 
>> 1. Make HCR_* flags as unsigned long long constants
>> Reason : By default, compiler assumes numeric constants as
>> signed hence sign extending it when assigned to unsigned variable
>> such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
>> HCR_CD making entire guest memory non-cacheable. On real HW, this
>> breaks Stage2 ttbl walks and also breaks VirtIO.
>> 
>> 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.
>> 
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>> ---
>>  arch/arm64/include/asm/kvm_arm.h |   73
>>  +++++++++++++++++++-------------------
>>  1 file changed, 37 insertions(+), 36 deletions(-)
>> 
>> diff --git a/arch/arm64/include/asm/kvm_arm.h
>> b/arch/arm64/include/asm/kvm_arm.h
>> index 8ced0ca..14ead69 100644
>> --- a/arch/arm64/include/asm/kvm_arm.h
>> +++ b/arch/arm64/include/asm/kvm_arm.h
>> @@ -18,44 +18,45 @@
>>  #ifndef __ARM64_KVM_ARM_H__
>>  #define __ARM64_KVM_ARM_H__
>>  
>> +#include <linux/const.h>
>>  #include <asm/types.h>
>>  
>>  /* Hyp Configuration Register (HCR) bits */
>> -#define HCR_ID		(1 << 33)
>> -#define HCR_CD		(1 << 32)
>> +#define HCR_ID		(UL(0x1) << 33)
>> +#define HCR_CD		(UL(0x1) << 32)
> 
> Consider using the BIT() macro from linux/bitops.h to improve
readability.

This would probably cause problems when using these macros from assembly
code.

        M.
-- 
Fast, cheap, reliable. Pick two.


From jason at lakedaemon.net  Mon May 13 12:04:33 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 12:04:33 -0400
Subject: [PATCH] ARM: plat-orion: add missing ehci include to common.h
In-Reply-To: <1368216747-28898-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368216747-28898-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130513160433.GP31290@titan.lakedaemon.net>

On Fri, May 10, 2013 at 10:12:27PM +0200, Sebastian Hesselbarth wrote:
> Removing orion ehci include from board files will raise a compiler
> error because plat/common.h is using an enum provided by orion ehci
> but not including the include itself. This just adds the missing include.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/plat-orion/include/plat/common.h |    1 +
>  1 file changed, 1 insertion(+)

Applied to mvebu/fixes

thx,

Jason.


From nicolas.ferre at atmel.com  Mon May 13 12:05:05 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 13 May 2013 18:05:05 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some SoC
Message-ID: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>

Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.

Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 Documentation/devicetree/bindings/net/macb.txt |  2 ++
 drivers/net/ethernet/cadence/macb.c            | 15 +++++++++++++--
 drivers/net/ethernet/cadence/macb.h            |  5 +++++
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 44afa0e..13ec4f6 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -6,6 +6,8 @@ Required properties:
   Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
   Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
   the Cadence GEM, or the generic form: "cdns,gem".
+  Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative
+  options enabled (ISR clear on write).
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
 - phy-mode: String, operation mode of the PHY interface.
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 6be513d..628f2b0 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -485,7 +485,8 @@ static void macb_tx_interrupt(struct macb *bp)
 	status = macb_readl(bp, TSR);
 	macb_writel(bp, TSR, status);
 
-	macb_writel(bp, ISR, MACB_BIT(TCOMP));
+	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+		macb_writel(bp, ISR, MACB_BIT(TCOMP));
 
 	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
 		(unsigned long)status);
@@ -738,7 +739,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
 			 * now.
 			 */
 			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
-			macb_writel(bp, ISR, MACB_BIT(RCOMP));
+			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+				macb_writel(bp, ISR, MACB_BIT(RCOMP));
 
 			if (napi_schedule_prep(&bp->napi)) {
 				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
@@ -1474,6 +1476,10 @@ static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "cdns,macb" },
 	{ .compatible = "cdns,pc302-gem" },
 	{ .compatible = "cdns,gem" },
+	{
+		.compatible = "cdns,zynq-7000-gem",
+		.data = (void *)MACB_CAPS_ISR_CLEAR_ON_WRITE,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, macb_dt_ids);
@@ -1484,6 +1490,7 @@ static int __init macb_probe(struct platform_device *pdev)
 	struct macb_platform_data *pdata;
 	struct resource *regs;
 	struct net_device *dev;
+	const struct of_device_id *dev_id;
 	struct macb *bp;
 	struct phy_device *phydev;
 	u32 config;
@@ -1558,6 +1565,10 @@ static int __init macb_probe(struct platform_device *pdev)
 
 	dev->base_addr = regs->start;
 
+	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
+	if (dev_id)
+		bp->caps = (u32)dev_id->data;
+
 	/* Set MII management clock divider */
 	config = macb_mdc_clk_div(bp);
 	config |= macb_dbw(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 993d703..5d622fe 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -323,6 +323,9 @@
 #define MACB_MAN_READ				2
 #define MACB_MAN_CODE				2
 
+/* Capability mask bits */
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x1
+
 /* Bit manipulation macros */
 #define MACB_BIT(name)					\
 	(1 << MACB_##name##_OFFSET)
@@ -574,6 +577,8 @@ struct macb {
 	unsigned int 		speed;
 	unsigned int 		duplex;
 
+	u32			caps;
+
 	phy_interface_t		phy_interface;
 
 	/* AT91RM9200 transmit */
-- 
1.8.0



From plagnioj at jcrosoft.com  Mon May 13 12:05:56 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 May 2013 00:05:56 +0800
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some
 SoC
In-Reply-To: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>


On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:

> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
> introduces clear-on-write on ISR register. This behavior is not always
> implemented when using Cadence MACB/GEM and is breaking other platforms.
> We are using a new Device Tree compatibility string and a capability
> property to actually activate this clear-on-write behavior on ISR.
> 
> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

can we detect it via the IP?
> ---
> Documentation/devicetree/bindings/net/macb.txt |  2 ++
> drivers/net/ethernet/cadence/macb.c            | 15 +++++++++++++--
> drivers/net/ethernet/cadence/macb.h            |  5 +++++
> 3 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
> index 44afa0e..13ec4f6 100644
> --- a/Documentation/devicetree/bindings/net/macb.txt
> +++ b/Documentation/devicetree/bindings/net/macb.txt
> @@ -6,6 +6,8 @@ Required properties:
>   Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
>   Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
>   the Cadence GEM, or the generic form: "cdns,gem".
> +  Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative
> +  options enabled (ISR clear on write).
> - reg: Address and length of the register set for the device
> - interrupts: Should contain macb interrupt
> - phy-mode: String, operation mode of the PHY interface.
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 6be513d..628f2b0 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -485,7 +485,8 @@ static void macb_tx_interrupt(struct macb *bp)
> 	status = macb_readl(bp, TSR);
> 	macb_writel(bp, TSR, status);
> 
> -	macb_writel(bp, ISR, MACB_BIT(TCOMP));
> +	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +		macb_writel(bp, ISR, MACB_BIT(TCOMP));
> 
> 	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
> 		(unsigned long)status);
> @@ -738,7 +739,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
> 			 * now.
> 			 */
> 			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
> -			macb_writel(bp, ISR, MACB_BIT(RCOMP));
> +			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +				macb_writel(bp, ISR, MACB_BIT(RCOMP));
> 
> 			if (napi_schedule_prep(&bp->napi)) {
> 				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
> @@ -1474,6 +1476,10 @@ static const struct of_device_id macb_dt_ids[] = {
> 	{ .compatible = "cdns,macb" },
> 	{ .compatible = "cdns,pc302-gem" },
> 	{ .compatible = "cdns,gem" },
> +	{
> +		.compatible = "cdns,zynq-7000-gem",
> +		.data = (void *)MACB_CAPS_ISR_CLEAR_ON_WRITE,
> +	},
> 	{ /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, macb_dt_ids);
> @@ -1484,6 +1490,7 @@ static int __init macb_probe(struct platform_device *pdev)
> 	struct macb_platform_data *pdata;
> 	struct resource *regs;
> 	struct net_device *dev;
> +	const struct of_device_id *dev_id;
> 	struct macb *bp;
> 	struct phy_device *phydev;
> 	u32 config;
> @@ -1558,6 +1565,10 @@ static int __init macb_probe(struct platform_device *pdev)
> 
> 	dev->base_addr = regs->start;
> 
> +	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
> +	if (dev_id)
> +		bp->caps = (u32)dev_id->data;
> +
> 	/* Set MII management clock divider */
> 	config = macb_mdc_clk_div(bp);
> 	config |= macb_dbw(bp);
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 993d703..5d622fe 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -323,6 +323,9 @@
> #define MACB_MAN_READ				2
> #define MACB_MAN_CODE				2
> 
> +/* Capability mask bits */
> +#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x1
> +
> /* Bit manipulation macros */
> #define MACB_BIT(name)					\
> 	(1 << MACB_##name##_OFFSET)
> @@ -574,6 +577,8 @@ struct macb {
> 	unsigned int 		speed;
> 	unsigned int 		duplex;
> 
> +	u32			caps;
> +
> 	phy_interface_t		phy_interface;
> 
> 	/* AT91RM9200 transmit */
> -- 
> 1.8.0
> 



From soren.brinkmann at xilinx.com  Mon May 13 12:09:47 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Mon, 13 May 2013 09:09:47 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130513052135.GD6836@sirena.org.uk>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
Message-ID: <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>

On Mon, May 13, 2013 at 09:21:35AM +0400, Mark Brown wrote:
> On Sun, May 12, 2013 at 12:05:04PM -0700, S?ren Brinkmann wrote:
> > On Sun, May 12, 2013 at 06:33:44PM +0400, Mark Brown wrote:
> 
> > > No, there's no confusion here - the clocks that are being exposed to
> > > userspace are the clocks which enter the FPGA.  The driver or whatever
> > > that understands the FPGA can do what is needed to control them,
> > > including routing them on to subdevices it instantiates or exposing them
> > > to userspace.
> 
> > Such a driver does not exist in general.
> > For some IP cores, Linux drivers do exist and then
> > they are supposed to directly use the CCF, IMHO, no need to expose
> > things to userspace in that case.
> > I'm trying to cover cases, in which there is no driver available/needed for
> > the FPGA design, other than some simple clock controls.
> 
> You're not understanding the point here.  If you've got a
> reprogrammmable FPGA you at least need some way to get the FPGA image in
> there.  This driver is presumably responsible for instantiating whatever
> is needed to control what is on the FPGA, that could include punting the
> clocks to userspace if that's sane.
Well, that driver actually exists. But that just programs a bitstream
you give it to program. It does not know anything about the design it
programs and cannot make any kind of decision whether the clocks should
be userspace controlled or not.

	S?ren




From Benoit.Lecardonnel at synopsys.com  Mon May 13 12:20:55 2013
From: Benoit.Lecardonnel at synopsys.com (Benoit Lecardonnel)
Date: Mon, 13 May 2013 17:20:55 +0100
Subject: arm64: Platform devices populated from a device_initcall
Message-ID: <519112E7.3040309@synopsys.com>

Hi all,

In the arm64 kernel, function arm64_device_probe 
(arch/arm64/kernel/setup.c) is in charge of populating the platform 
devices defined by the device tree.

Does anyone know why arm64_device_probe is a device_initcall?

This seems to be in conflict with some I2C drivers: see 
drivers/i2c/busses/i2c-designware-platdrv.c for example.
The driver calls platform_driver_probe from a subsys_initcall.
The probe fails because subsys_initcalls are executed before 
device_initcalls.

Maybe arm64_device_probe could be an arch_initcall?

Thanks,
-- 
Benoit Lecardonnel


From sebastian.hesselbarth at gmail.com  Mon May 13 12:21:13 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 13 May 2013 18:21:13 +0200
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
Message-ID: <519112F9.2010102@gmail.com>

On 05/13/13 18:09, S?ren Brinkmann wrote:
> On Mon, May 13, 2013 at 09:21:35AM +0400, Mark Brown wrote:
>> On Sun, May 12, 2013 at 12:05:04PM -0700, S?ren Brinkmann wrote:
>>> On Sun, May 12, 2013 at 06:33:44PM +0400, Mark Brown wrote:
>>>> No, there's no confusion here - the clocks that are being exposed to
>>>> userspace are the clocks which enter the FPGA.  The driver or whatever
>>>> that understands the FPGA can do what is needed to control them,
>>>> including routing them on to subdevices it instantiates or exposing them
>>>> to userspace.
>>
>>> Such a driver does not exist in general.
>>> For some IP cores, Linux drivers do exist and then
>>> they are supposed to directly use the CCF, IMHO, no need to expose
>>> things to userspace in that case.
>>> I'm trying to cover cases, in which there is no driver available/needed for
>>> the FPGA design, other than some simple clock controls.
>>
>> You're not understanding the point here.  If you've got a
>> reprogrammmable FPGA you at least need some way to get the FPGA image in
>> there.  This driver is presumably responsible for instantiating whatever
>> is needed to control what is on the FPGA, that could include punting the
>> clocks to userspace if that's sane.
> Well, that driver actually exists. But that just programs a bitstream
> you give it to program. It does not know anything about the design it
> programs and cannot make any kind of decision whether the clocks should
> be userspace controlled or not.

Soeren,

what Mark wants to point out is that you add fabric clocks to the Xilinx
driver instead. This way, you will have user-space controllable clocks
but only if you loaded the xilinx driver first.

IIRC the fabric clock controller provided by Zynq _is_ always there and
accessible from ARM CPUs. You just don't have a new generic driver
allowing to poke with all clocks, but a xilinx only driver allowing you
to set the (xilinx only) fabric clocks.

I've played with Zynq a while ago, did Xilinx mainline the bitfile
driver already? If not, why don't you give it a shot?

Sebastian


From jason at lakedaemon.net  Mon May 13 12:30:42 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 12:30:42 -0400
Subject: [PATCH] ARM: mvebu: Add a ranges entry to translate devbus childs
In-Reply-To: <1368458573-18043-1-git-send-email-elezegarcia@gmail.com>
References: <1368458573-18043-1-git-send-email-elezegarcia@gmail.com>
Message-ID: <20130513163042.GQ31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 12:22:53PM -0300, Ezequiel Garcia wrote:
> From: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> 
> With the latest device tree reorganization which introduced the
> 'internal-reg' node, now the only region translated is the internal register's.
> This makes the description of the hardware incomplete, for it lacks the
> Device Bus childs address space.
> 
> In order to fix this, it's required to add a 'ranges' entry with a suitable
> address space to map Device Bus childs, on a per-board basis.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> ---
> Applies on v3.10-rc1. This is meant for v3.10.
> 
>  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 +++
>  1 file changed, 3 insertions(+)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Mon May 13 12:45:36 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 12:45:36 -0400
Subject: [PATCH] Kirkwood: Enable PCIe port 1 on QNAP TS-11x/TS-21x
In-Reply-To: <20130429180338.GE16725@lunn.ch>
References: <20130421152802.GA1408@jirafa.cyrius.com>
 <20130421154704.GV2824@lunn.ch>
 <20130421161400.GD26943@jirafa.cyrius.com>
 <20130429173022.GS32497@titan.lakedaemon.net>
 <20130429180338.GE16725@lunn.ch>
Message-ID: <20130513164536.GS31290@titan.lakedaemon.net>

On Mon, Apr 29, 2013 at 08:03:38PM +0200, Andrew Lunn wrote:
> On Mon, Apr 29, 2013 at 01:30:22PM -0400, Jason Cooper wrote:
> > On Sun, Apr 21, 2013 at 05:14:00PM +0100, Martin Michlmayr wrote:
> > > Enable KW_PCIE1 on QNAP TS-11x/TS-21x devices as newer revisions
> > > (rev 1.3) have a USB 3.0 chip from Etron on PCIe port 1.  Thanks
> > > to Marek Vasut for identifying this issue!
> > > 
> > > Cc: <stable at kernel.org>
> > > Signed-off-by: Martin Michlmayr <tbm at cyrius.com>
> > > Tested-by: Marek Vasut <marex at denx.de>
> > 
> > Applied to mvebu-next/fixes.  This branch will be rebased onto v3.10-rc1
> > once it drops.  I'll submit a pull request then.
> > 
> > fyi: looks like this can be applied to stable all the way back to
> > v2.6.36.x, updated stable tag accordingly.
> 
> Hi Jason
> 
> Once we have v3.10-rc1 with the DT PCI patches, i will also make an
> update to them to enable both PCI ports where available.
> 
> We should also change the kirkwood_defconfig to enable the PCI USB
> 3.0. driver. I can do that as well.

Do you have these ready to post?  No rush, just didn't want to see it
fall off the table...

thx,

Jason.


From swarren at wwwdotorg.org  Mon May 13 12:46:27 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 10:46:27 -0600
Subject: [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
In-Reply-To: <1368443225-16978-2-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
 <1368443225-16978-2-git-send-email-hdoyu@nvidia.com>
Message-ID: <519118E3.4060907@wwwdotorg.org>

On 05/13/2013 05:07 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

I'd like slightly more description of the change here. What about:

=====
Create a header file to define the clock IDs used by the Tegra20 clock
binding. Remove the list of definitions from the binding documentation,
and refer the reader to the header file.

This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.
=====

I'm not sure exactly how these patches will get merged. For you
reference, I anticipate one of two things happening:

1)

* Patches 1, 3, 5 get put into a topic branch, and merged into both the
clk tree and the Tegra tree.

* Patches 2, 4, 6 get merged into the Tegra tree.

* The patches you're going to create for the drivers/clk code get merged
into Mike's clk tree

2)

* Mike ack's the patches you're going to create for the drivers/clk code.

* Everything gets merged through the Tegra tree.

This shouldn't impact you much, but just be aware that the drivers/clk
changes you create shouldn't depend on anything beyond patches 1, 3, 5
here and 3.10-rc1, then I can work out the merging with Mike without any
constraints.

> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

>  This binding uses the common clock binding:
>  Documentation/devicetree/bindings/clock/clock-bindings.txt
>  
> +You can find the actual assignment in "dt-bindings/clk/tegra20-car.h"

Can you move this text down into the description of clock-cells, i.e.
where you removed the original list of IDs? That'll keep the text in the
place it's most useful. I would also like to explicitly mention "include
file" and use <> rather than "", since that matches the syntax that
should be used in .dts files, i.e.:

=====
 - #clock-cells : Should be 1.
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clk/tegra20-car.h>.
=====

Similar comments for patches 3 and 5.


From swarren at wwwdotorg.org  Mon May 13 12:47:13 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 10:47:13 -0600
Subject: [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
In-Reply-To: <1368443225-16978-2-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
 <1368443225-16978-2-git-send-email-hdoyu@nvidia.com>
Message-ID: <51911911.2000107@wwwdotorg.org>

On 05/13/2013 05:07 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

> @@ -172,7 +26,7 @@ Example SoC include file:
>  	};
>  
>  	usb at c5004000 {
> -		clocks = <&tegra_car 58>; /* usb2 */
> +		clocks = <&tegra_car TEGRA20_CLK_USB2>; /* usb2 */

I forgot to mention: That comment isn't useful any more, since it's
obvious this represents the USB2 clock now that the actual cell data
uses a define.



From swarren at wwwdotorg.org  Mon May 13 12:54:36 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 10:54:36 -0600
Subject: [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK
 defines
In-Reply-To: <1368443225-16978-3-git-send-email-hdoyu@nvidia.com>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com>
 <1368443225-16978-3-git-send-email-hdoyu@nvidia.com>
Message-ID: <51911ACC.5010507@wwwdotorg.org>

On 05/13/2013 05:07 AM, Hiroshi Doyu wrote:
> Replace magic number in tegra_car:
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

Patches 2, 4, 6 look basically fine. I'd also like slightly more
explanation in the commit description here. How about:

=====
Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic
numbers in the device tree. For example,

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;
=====

> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi

>  #include <dt-bindings/gpio/tegra-gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clk/tegra20-car.h>

Can we keep the include files sorted?

One dependency issue with patches 2: There is a series of USB patches
(which Venu posted in the last couple of days) that fix the USB binding
to be complete. These will change the set of clocks referenced by the
EHCI and USB PHY nodes. I would like Venu's patches to be applied first,
since those DT changes will need to be merged into the USB tree so that
the USB tree can apply the subsequent driver changes. Can you hold off
on reposting your series until after I've applied Venu's changes, and
rebase this series on top of them? Hopefully it shouldn't take too long
to get Venu's series applied. Thanks.


From paul at pwsan.com  Mon May 13 13:02:59 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 13 May 2013 17:02:59 +0000 (UTC)
Subject: [PATCH] ARM: defconfigs: OMAP: omap2plus_defconfig missing
 CONFIG_ARCH_MULTI_V6=y
Message-ID: <alpine.DEB.2.00.1305131701270.7156@utopia.booyaka.com>


omap2plus_defconfig is missing CONFIG_ARCH_MULTI_V6.  This results in
undefined instruction traps in u-boot (and boot failures) on OMAP2xxx
SoCs, which are ARM11-based.  Fix by setting CONFIG_ARCH_MULTI_V7.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/configs/omap2plus_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index c1ef64b..f590902 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -20,6 +20,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MULTI_V6=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
-- 
1.7.10.4



From jason at lakedaemon.net  Mon May 13 13:03:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 13:03:25 -0400
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 1)
Message-ID: <20130513170325.GT31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-1

for you to fetch changes up to 00ed4a0bd964555fe9276f2299564c384d50ae7d:

  ARM: mvebu: Add a ranges entry to translate devbus childs (2013-05-13 16:23:47 +0000)

----------------------------------------------------------------
mvebu fixes for v3.10 round 1

 - mvebu
    - duplicate alias removal
    - augment new internal-regs dt node with proper ranges node

 - kirkwood
    - stable fix for QNAP TS-11x/TS-21x enabling PCIe port 1

 - plat-orion
    - missing ehci include in common.h.  needed within common.h.

----------------------------------------------------------------
Ezequiel Garcia (1):
      ARM: mvebu: Add a ranges entry to translate devbus childs

Martin Michlmayr (1):
      Kirkwood: Enable PCIe port 1 on QNAP TS-11x/TS-21x

Sebastian Hesselbarth (1):
      ARM: plat-orion: add missing ehci include to common.h

Thomas Petazzoni (1):
      ARM: mvebu: do not duplicate the mpic alias

 arch/arm/boot/dts/armada-370.dtsi                | 2 +-
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 +++
 arch/arm/boot/dts/armada-xp.dtsi                 | 2 +-
 arch/arm/mach-kirkwood/ts219-setup.c             | 2 +-
 arch/arm/plat-orion/include/plat/common.h        | 1 +
 5 files changed, 7 insertions(+), 3 deletions(-)


From paul at pwsan.com  Mon May 13 13:04:22 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 13 May 2013 17:04:22 +0000 (UTC)
Subject: [PATCH] ARM: defconfigs: OMAP: omap2plus_defconfig missing
 CONFIG_ARCH_MULTI_V6=y
In-Reply-To: <alpine.DEB.2.00.1305131701270.7156@utopia.booyaka.com>
References: <alpine.DEB.2.00.1305131701270.7156@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1305131703271.7156@utopia.booyaka.com>

On Mon, 13 May 2013, Paul Walmsley wrote:

> Fix by setting CONFIG_ARCH_MULTI_V7.

Well, obvious typo here.  Here's the updated version.


- Paul

From: Paul Walmsley <paul at pwsan.com>
Date: Mon, 13 May 2013 10:47:48 -0600
Subject: [PATCH] ARM: defconfigs: OMAP: omap2plus_defconfig missing CONFIG_ARCH_MULTI_V6=y

omap2plus_defconfig is missing CONFIG_ARCH_MULTI_V6.  This results in
undefined instruction traps in u-boot (and boot failures) on OMAP2xxx
SoCs, which are ARM11-based.  Fix by setting CONFIG_ARCH_MULTI_V6.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/configs/omap2plus_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index c1ef64b..f590902 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -20,6 +20,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MULTI_V6=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
-- 
1.7.10.4



From shc_work at mail.ru  Mon May 13 13:07:23 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:23 +0400
Subject: [PATCH 02/15] ARM: clps711x: Set PLL clock to zero if we work from 13
 mHz source
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-4-git-send-email-shc_work@mail.ru>

This clock will be used in audio subsystem. Since audio cannot work
without PLL we should indicate this.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..f42302e 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -301,6 +301,7 @@ void __init clps711x_timer_init(void)
 		cpu = ext;
 		bus = cpu;
 		spi = 135400;
+		pll = 0;
 	} else {
 		cpu = pll;
 		if (cpu >= 36864000)
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:20 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:20 +0400
Subject: [PATCH 01/15] ARM: clps711x: Remove NEED_MACH_MEMORY_H dependency
Message-ID: <1368464857-5038-1-git-send-email-shc_work@mail.ru>

This patch removes dependency of NEED_MACH_MEMORY_H for CLPS711X-target.
Since some board may have memory holes, define ARCH_HAS_HOLES_MEMORYMODEL
for these boards.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/Kconfig                             |  1 -
 arch/arm/mach-clps711x/Kconfig               |  3 +-
 arch/arm/mach-clps711x/include/mach/memory.h | 41 ----------------------------
 3 files changed, 1 insertion(+), 44 deletions(-)
 delete mode 100644 arch/arm/mach-clps711x/include/mach/memory.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f95674a..10cdfa9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -371,7 +371,6 @@ config ARCH_CLPS711X
 	select CPU_ARM720T
 	select GENERIC_CLOCKEVENTS
 	select MULTI_IRQ_HANDLER
-	select NEED_MACH_MEMORY_H
 	select SPARSE_IRQ
 	help
 	  Support for Cirrus Logic 711x/721x/731x based boards.
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 2d00165..01ad4d4 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -22,8 +22,7 @@ config ARCH_CLEP7312
 
 config ARCH_EDB7211
 	bool "EDB7211"
-	select ARCH_SELECT_MEMORY_MODEL
-	select ARCH_SPARSEMEM_ENABLE
+	select ARCH_HAS_HOLES_MEMORYMODEL
 	help
 	  Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
 	  evaluation board.
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
deleted file mode 100644
index fc0e028..0000000
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET	UL(0xc0000000)
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-
-#define SECTION_SIZE_BITS	24
-#define MAX_PHYSMEM_BITS	32
-
-#endif
-
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:24 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:24 +0400
Subject: [PATCH 03/15] ARM: clps711x: autcpu12: Move LCD DPOT definitions to
 board file
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-5-git-send-email-shc_work@mail.ru>

We do not have driver for Up/Down digital potentiometer (DPOT), so
just define pins as GPIOs and export these pins to user.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-autcpu12.c        | 14 ++++++++++++++
 arch/arm/mach-clps711x/include/mach/autcpu12.h |  8 --------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index 1e22cb4..78b528a 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -51,12 +51,18 @@
 #define AUTCPU12_SMC_BASE	(CS1_PHYS_BASE + 0x06000000)
 #define AUTCPU12_SMC_SEL_BASE	(AUTCPU12_SMC_BASE + 0x10)
 
+/* NAND flash */
 #define AUTCPU12_MMGPIO_BASE	(CLPS711X_NR_GPIO)
 #define AUTCPU12_SMC_NCE	(AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
 #define AUTCPU12_SMC_RDY	CLPS711X_GPIO(1, 2)
 #define AUTCPU12_SMC_ALE	CLPS711X_GPIO(1, 3)
 #define AUTCPU12_SMC_CLE	CLPS711X_GPIO(1, 3)
 
+/* LCD contrast digital potentiometer */
+#define AUTCPU12_DPOT_CS	CLPS711X_GPIO(4, 0)
+#define AUTCPU12_DPOT_CLK	CLPS711X_GPIO(4, 1)
+#define AUTCPU12_DPOT_UD	CLPS711X_GPIO(4, 2)
+
 static struct resource autcpu12_cs8900_resource[] __initdata = {
 	DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
 	DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
@@ -148,6 +154,12 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
 	},
 };
 
+static const struct gpio autcpu12_gpios[] __initconst = {
+	{ AUTCPU12_DPOT_CS,	GPIOF_OUT_INIT_HIGH,	"DPOT CS" },
+	{ AUTCPU12_DPOT_CLK,	GPIOF_OUT_INIT_LOW,	"DPOT CLK" },
+	{ AUTCPU12_DPOT_UD,	GPIOF_OUT_INIT_LOW,	"DPOT UD" },
+};
+
 static void __init autcpu12_init(void)
 {
 	clps711x_devices_init();
@@ -160,6 +172,8 @@ static void __init autcpu12_init(void)
 
 static void __init autcpu12_init_late(void)
 {
+	gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
+
 	if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
 		/* We are need both drivers to handle NAND */
 		platform_device_register(&autcpu12_nand_pdev);
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index 0452f5f..b95d60a 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -48,12 +48,4 @@
 
 #define AUTCPU12_PHYS_LPT              	CS1_PHYS_BASE +0x0E000000  /* physical */
 
-/*
-* defines for lcd contrast 
-*/
-#define AUTCPU12_DPOT_PORT_OFFSET	PEDR
-#define	AUTCPU12_DPOT_CS		(1<<0)
-#define AUTCPU12_DPOT_CLK    		(1<<1)
-#define	AUTCPU12_DPOT_UD		(1<<2)
-
 #endif
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:22 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:22 +0400
Subject: [PATCH RESEND v2 2/3] ARM: clps711x: Re-add GPIO support
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-3-git-send-email-shc_work@mail.ru>

arch_initcall was been removed from GPIO driver, so this patch
re-add support for GPIO into boards as platform_device.
Since some drivers (spi, nand, etc.) is not support deferred probe,
separate machine init calls is used in board code to make proper
loading sequence.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/Makefile         |  5 +---
 arch/arm/mach-clps711x/board-autcpu12.c |  2 ++
 arch/arm/mach-clps711x/board-cdb89712.c |  2 ++
 arch/arm/mach-clps711x/board-edb7211.c  |  7 +++++
 arch/arm/mach-clps711x/board-p720t.c    | 10 ++++---
 arch/arm/mach-clps711x/devices.c        | 48 +++++++++++++++++++++++++++++++++
 arch/arm/mach-clps711x/devices.h        | 12 +++++++++
 7 files changed, 78 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mach-clps711x/devices.c
 create mode 100644 arch/arm/mach-clps711x/devices.h

diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 992995a..f30ed2b 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,10 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= common.o
-obj-m			:=
-obj-n			:=
-obj-			:=
+obj-y				:= common.o devices.o
 
 obj-$(CONFIG_ARCH_AUTCPU12)	+= board-autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712)	+= board-cdb89712.o
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f385847..1e22cb4 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -43,6 +43,7 @@
 #include <mach/autcpu12.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define AUTCPU12_CS8900_BASE	(CS2_PHYS_BASE + 0x300)
 #define AUTCPU12_CS8900_IRQ	(IRQ_EINT3)
@@ -149,6 +150,7 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
 
 static void __init autcpu12_init(void)
 {
+	clps711x_devices_init();
 	platform_device_register_simple("video-clps711x", 0, NULL, 0);
 	platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
 					ARRAY_SIZE(autcpu12_cs8900_resource));
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index baab7da..a80ae57 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -39,6 +39,7 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define CDB89712_CS8900_BASE	(CS2_PHYS_BASE + 0x300)
 #define CDB89712_CS8900_IRQ	(IRQ_EINT3)
@@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = {
 
 static void __init cdb89712_init(void)
 {
+	clps711x_devices_init();
 	platform_device_register(&cdb89712_flash_pdev);
 	platform_device_register(&cdb89712_bootrom_pdev);
 	platform_device_register(&cdb89712_sram_pdev);
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 5f928e9..e1c5573 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -29,6 +29,7 @@
 #include <mach/hardware.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define VIDEORAM_SIZE		SZ_128K
 
@@ -151,6 +152,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
 
 static void __init edb7211_init(void)
 {
+	clps711x_devices_init();
+}
+
+static void __init edb7211_init_late(void)
+{
 	gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
 
 	platform_device_register(&edb7211_flash_pdev);
@@ -175,6 +181,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.init_machine	= edb7211_init,
+	.init_late	= edb7211_init_late,
 	.handle_irq	= clps711x_handle_irq,
 	.restart	= clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 8d3ee67..48d0737 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -43,6 +43,7 @@
 #include <video/platform_lcd.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define P720T_USERLED		CLPS711X_GPIO(3, 0)
 #define P720T_NAND_CLE		CLPS711X_GPIO(4, 0)
@@ -199,6 +200,11 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
 
 static void __init p720t_init(void)
 {
+	clps711x_devices_init();
+}
+
+static void __init p720t_init_late(void)
+{
 	platform_device_register(&p720t_nand_pdev);
 	platform_device_register_data(&platform_bus, "platform-lcd", 0,
 				      &p720t_lcd_power_pdata,
@@ -207,10 +213,6 @@ static void __init p720t_init(void)
 				      &p720t_lcd_backlight_pdata,
 				      sizeof(p720t_lcd_backlight_pdata));
 	platform_device_register_simple("video-clps711x", 0, NULL, 0);
-}
-
-static void __init p720t_init_late(void)
-{
 	platform_device_register_data(&platform_bus, "leds-gpio", 0,
 				      &p720t_gpio_led_pdata,
 				      sizeof(p720t_gpio_led_pdata));
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 0000000..21161ed
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,48 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Author: Alexander Shiyan <shc_work at mail.ru>, 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+
+static const phys_addr_t clps711x_gpios[][2] __initconst = {
+	{ PADR, PADDR },
+	{ PBDR, PBDDR },
+	{ PCDR, PCDDR },
+	{ PDDR, PDDDR },
+	{ PEDR, PEDDR },
+};
+
+static void __init clps711x_add_gpio(void)
+{
+	unsigned i;
+	struct resource gpio_res[2];
+
+	memset(gpio_res, 0, sizeof(gpio_res));
+
+	gpio_res[0].flags = IORESOURCE_MEM;
+	gpio_res[1].flags = IORESOURCE_MEM;
+
+	for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
+		gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
+		gpio_res[0].end = gpio_res[0].start;
+		gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
+		gpio_res[1].end = gpio_res[1].start;
+
+		platform_device_register_simple("clps711x-gpio", i,
+						gpio_res, ARRAY_SIZE(gpio_res));
+	}
+}
+
+void __init clps711x_devices_init(void)
+{
+	clps711x_add_gpio();
+}
diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h
new file mode 100644
index 0000000..a5efc17
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.h
@@ -0,0 +1,12 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Copyright (C) 2013 Alexander Shiyan <shc_work at mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+void clps711x_devices_init(void);
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:21 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:21 +0400
Subject: [PATCH RESEND v2 1/3] GPIO: clps711x: Rewrite driver for using
 generic GPIO code
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-2-git-send-email-shc_work@mail.ru>

This patch provides rewritten driver for CLPS711X GPIO which uses
generic GPIO code.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/gpio/Kconfig         |   5 +-
 drivers/gpio/gpio-clps711x.c | 226 +++++++++++--------------------------------
 2 files changed, 63 insertions(+), 168 deletions(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 30d89ed..b0d967b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,8 +109,11 @@ config GPIO_MAX730X
 comment "Memory mapped GPIO drivers:"
 
 config GPIO_CLPS711X
-	def_bool y
+	tristate "CLPS711X GPIO support"
 	depends on ARCH_CLPS711X
+	select GPIO_GENERIC
+	help
+	  Say yes here to support GPIO on CLPS711X SoCs.
 
 config GPIO_GENERIC_PLATFORM
 	tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
index ce63b75..6ce8a8c 100644
--- a/drivers/gpio/gpio-clps711x.c
+++ b/drivers/gpio/gpio-clps711x.c
@@ -1,7 +1,7 @@
 /*
  *  CLPS711X GPIO driver
  *
- *  Copyright (C) 2012 Alexander Shiyan <shc_work at mail.ru>
+ *  Copyright (C) 2012,2013 Alexander Shiyan <shc_work at mail.ru>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,191 +9,83 @@
  * (at your option) any later version.
  */
 
-#include <linux/io.h>
-#include <linux/slab.h>
+#include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
-
-#define CLPS711X_GPIO_PORTS	5
-#define CLPS711X_GPIO_NAME	"gpio-clps711x"
-
-struct clps711x_gpio {
-	struct gpio_chip	chip[CLPS711X_GPIO_PORTS];
-	spinlock_t		lock;
-};
-
-static void __iomem *clps711x_ports[] = {
-	CLPS711X_VIRT_BASE + PADR,
-	CLPS711X_VIRT_BASE + PBDR,
-	CLPS711X_VIRT_BASE + PCDR,
-	CLPS711X_VIRT_BASE + PDDR,
-	CLPS711X_VIRT_BASE + PEDR,
-};
-
-static void __iomem *clps711x_pdirs[] = {
-	CLPS711X_VIRT_BASE + PADDR,
-	CLPS711X_VIRT_BASE + PBDDR,
-	CLPS711X_VIRT_BASE + PCDDR,
-	CLPS711X_VIRT_BASE + PDDDR,
-	CLPS711X_VIRT_BASE + PEDDR,
-};
-
-#define clps711x_port(x)	clps711x_ports[x->base / 8]
-#define clps711x_pdir(x)	clps711x_pdirs[x->base / 8]
-
-static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
+static int clps711x_gpio_probe(struct platform_device *pdev)
 {
-	return !!(readb(clps711x_port(chip)) & (1 << offset));
-}
+	void __iomem *dat, *dir;
+	struct bgpio_chip *bgc;
+	struct resource *res;
+	int err, id = pdev->id;
 
-static void gpio_clps711x_set(struct gpio_chip *chip, unsigned offset,
-			      int value)
-{
-	int tmp;
-	unsigned long flags;
-	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+	if ((id < 0) || (id > 4))
+		return -ENODEV;
 
-	spin_lock_irqsave(&gpio->lock, flags);
-	tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-	if (value)
-		tmp |= 1 << offset;
-	writeb(tmp, clps711x_port(chip));
-	spin_unlock_irqrestore(&gpio->lock, flags);
-}
-
-static int gpio_clps711x_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-	int tmp;
-	unsigned long flags;
-	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-	spin_lock_irqsave(&gpio->lock, flags);
-	tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-	writeb(tmp, clps711x_pdir(chip));
-	spin_unlock_irqrestore(&gpio->lock, flags);
-
-	return 0;
-}
+	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
+	if (!bgc)
+		return -ENOMEM;
 
-static int gpio_clps711x_dir_out(struct gpio_chip *chip, unsigned offset,
-				 int value)
-{
-	int tmp;
-	unsigned long flags;
-	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dat = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dat))
+		return PTR_ERR(dat);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	dir = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dir))
+		return PTR_ERR(dir);
+
+	switch (id) {
+	case 3:
+		/* PORTD is inverted logic for direction register */
+		err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
+				 NULL, dir, 0);
+		break;
+	default:
+		err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
+				 dir, NULL, 0);
+		break;
+	}
 
-	spin_lock_irqsave(&gpio->lock, flags);
-	tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-	writeb(tmp, clps711x_pdir(chip));
-	tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-	if (value)
-		tmp |= 1 << offset;
-	writeb(tmp, clps711x_port(chip));
-	spin_unlock_irqrestore(&gpio->lock, flags);
+	if (err)
+		return err;
 
-	return 0;
-}
-
-static int gpio_clps711x_dir_in_inv(struct gpio_chip *chip, unsigned offset)
-{
-	int tmp;
-	unsigned long flags;
-	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+	switch (id) {
+	case 4:
+		/* PORTE is 3 lines only */
+		bgc->gc.ngpio = 3;
+		break;
+	default:
+		break;
+	}
 
-	spin_lock_irqsave(&gpio->lock, flags);
-	tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-	writeb(tmp, clps711x_pdir(chip));
-	spin_unlock_irqrestore(&gpio->lock, flags);
+	bgc->gc.base = id * 8;
+	platform_set_drvdata(pdev, bgc);
 
-	return 0;
+	return gpiochip_add(&bgc->gc);
 }
 
-static int gpio_clps711x_dir_out_inv(struct gpio_chip *chip, unsigned offset,
-				     int value)
+static int clps711x_gpio_remove(struct platform_device *pdev)
 {
-	int tmp;
-	unsigned long flags;
-	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+	struct bgpio_chip *bgc = platform_get_drvdata(pdev);
 
-	spin_lock_irqsave(&gpio->lock, flags);
-	tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-	writeb(tmp, clps711x_pdir(chip));
-	tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-	if (value)
-		tmp |= 1 << offset;
-	writeb(tmp, clps711x_port(chip));
-	spin_unlock_irqrestore(&gpio->lock, flags);
-
-	return 0;
+	return bgpio_remove(bgc);
 }
 
-static struct {
-	char	*name;
-	int	nr;
-	int	inv_dir;
-} clps711x_gpio_ports[] __initconst = {
-	{ "PORTA", 8, 0, },
-	{ "PORTB", 8, 0, },
-	{ "PORTC", 8, 0, },
-	{ "PORTD", 8, 1, },
-	{ "PORTE", 3, 0, },
+static struct platform_driver clps711x_gpio_driver = {
+	.driver	= {
+		.name	= "clps711x-gpio",
+		.owner	= THIS_MODULE,
+	},
+	.probe	= clps711x_gpio_probe,
+	.remove	= clps711x_gpio_remove,
 };
+module_platform_driver(clps711x_gpio_driver);
 
-static int __init gpio_clps711x_init(void)
-{
-	int i;
-	struct platform_device *pdev;
-	struct clps711x_gpio *gpio;
-
-	pdev = platform_device_alloc(CLPS711X_GPIO_NAME, 0);
-	if (!pdev) {
-		pr_err("Cannot create platform device: %s\n",
-		       CLPS711X_GPIO_NAME);
-		return -ENOMEM;
-	}
-
-	platform_device_add(pdev);
-
-	gpio = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_gpio),
-			    GFP_KERNEL);
-	if (!gpio) {
-		dev_err(&pdev->dev, "GPIO allocating memory error\n");
-		platform_device_unregister(pdev);
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(pdev, gpio);
-
-	spin_lock_init(&gpio->lock);
-
-	for (i = 0; i < CLPS711X_GPIO_PORTS; i++) {
-		gpio->chip[i].owner		= THIS_MODULE;
-		gpio->chip[i].dev		= &pdev->dev;
-		gpio->chip[i].label		= clps711x_gpio_ports[i].name;
-		gpio->chip[i].base		= i * 8;
-		gpio->chip[i].ngpio		= clps711x_gpio_ports[i].nr;
-		gpio->chip[i].get		= gpio_clps711x_get;
-		gpio->chip[i].set		= gpio_clps711x_set;
-		if (!clps711x_gpio_ports[i].inv_dir) {
-			gpio->chip[i].direction_input = gpio_clps711x_dir_in;
-			gpio->chip[i].direction_output = gpio_clps711x_dir_out;
-		} else {
-			gpio->chip[i].direction_input = gpio_clps711x_dir_in_inv;
-			gpio->chip[i].direction_output = gpio_clps711x_dir_out_inv;
-		}
-		WARN_ON(gpiochip_add(&gpio->chip[i]));
-	}
-
-	dev_info(&pdev->dev, "GPIO driver initialized\n");
-
-	return 0;
-}
-arch_initcall(gpio_clps711x_init);
-
-MODULE_LICENSE("GPL v2");
+MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Alexander Shiyan <shc_work at mail.ru>");
 MODULE_DESCRIPTION("CLPS711X GPIO driver");
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:25 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:25 +0400
Subject: [PATCH RESEND v2 3/3] GPIO: clps711x: Add DT support
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-6-git-send-email-shc_work@mail.ru>

Add DT support to the CLPS711X GPIO driver.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 .../devicetree/bindings/gpio/gpio-clps711x.txt     | 28 ++++++++++++++++++++++
 drivers/gpio/gpio-clps711x.c                       | 14 ++++++++---
 2 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-clps711x.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
new file mode 100644
index 0000000..e0d0446
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
@@ -0,0 +1,28 @@
+Cirrus Logic CLPS711X GPIO controller
+
+Required properties:
+- compatible: Should be "cirrus,clps711x-gpio"
+- reg: Physical base GPIO controller registers location and length.
+  There should be two registers, first is DATA register, the second
+  is DIRECTION.
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+    0 = active high
+    1 = active low
+
+Note: Each GPIO port should have an alias correctly numbered in "aliases"
+node.
+
+Example:
+
+aliases {
+	gpio0 = &porta;
+};
+
+porta: gpio at 80000000 {
+	compatible = "cirrus,clps711x-gpio";
+	reg = <0x80000000 0x1>, <0x80000040 0x1>;
+	gpio-controller;
+	#gpio-cells = <2>;
+};
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
index 6ce8a8c..0edaf2c 100644
--- a/drivers/gpio/gpio-clps711x.c
+++ b/drivers/gpio/gpio-clps711x.c
@@ -17,10 +17,11 @@
 
 static int clps711x_gpio_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	void __iomem *dat, *dir;
 	struct bgpio_chip *bgc;
 	struct resource *res;
-	int err, id = pdev->id;
+	int err, id = np ? of_alias_get_id(np, "gpio") : pdev->id;
 
 	if ((id < 0) || (id > 4))
 		return -ENODEV;
@@ -76,10 +77,17 @@ static int clps711x_gpio_remove(struct platform_device *pdev)
 	return bgpio_remove(bgc);
 }
 
+static const struct of_device_id clps711x_gpio_ids[] = {
+	{ .compatible = "cirrus,clps711x-gpio" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, clps711x_gpio_ids);
+
 static struct platform_driver clps711x_gpio_driver = {
 	.driver	= {
-		.name	= "clps711x-gpio",
-		.owner	= THIS_MODULE,
+		.name		= "clps711x-gpio",
+		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(clps711x_gpio_ids),
 	},
 	.probe	= clps711x_gpio_probe,
 	.remove	= clps711x_gpio_remove,
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:26 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:26 +0400
Subject: [PATCH 04/15] ARM: clps711x: autcpu12: Add support for NOR flash
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-7-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-autcpu12.c        | 39 ++++++++++++++++++++++++--
 arch/arm/mach-clps711x/include/mach/autcpu12.h |  5 ----
 2 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index 78b528a..3e22d0b 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -26,6 +26,7 @@
 #include <linux/gpio.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
 #include <linux/platform_device.h>
@@ -45,12 +46,17 @@
 #include "common.h"
 #include "devices.h"
 
-#define AUTCPU12_CS8900_BASE	(CS2_PHYS_BASE + 0x300)
-#define AUTCPU12_CS8900_IRQ	(IRQ_EINT3)
+/* NOR flash */
+#define AUTCPU12_FLASH_BASE	(CS0_PHYS_BASE)
 
+/* SmartMedia flash */
 #define AUTCPU12_SMC_BASE	(CS1_PHYS_BASE + 0x06000000)
 #define AUTCPU12_SMC_SEL_BASE	(AUTCPU12_SMC_BASE + 0x10)
 
+/* Ethernet */
+#define AUTCPU12_CS8900_BASE	(CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ	(IRQ_EINT3)
+
 /* NAND flash */
 #define AUTCPU12_MMGPIO_BASE	(CLPS711X_NR_GPIO)
 #define AUTCPU12_SMC_NCE	(AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
@@ -160,9 +166,38 @@ static const struct gpio autcpu12_gpios[] __initconst = {
 	{ AUTCPU12_DPOT_UD,	GPIOF_OUT_INIT_LOW,	"DPOT UD" },
 };
 
+static struct mtd_partition autcpu12_flash_partitions[] = {
+	{
+		.name	= "NOR.0",
+		.offset	= 0,
+		.size	= MTDPART_SIZ_FULL,
+	},
+};
+
+static struct physmap_flash_data autcpu12_flash_pdata = {
+	.width		= 4,
+	.parts		= autcpu12_flash_partitions,
+	.nr_parts	= ARRAY_SIZE(autcpu12_flash_partitions),
+};
+
+static struct resource autcpu12_flash_resources[] __initdata = {
+	DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
+};
+
+static struct platform_device autcpu12_flash_pdev __initdata = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.resource	= autcpu12_flash_resources,
+	.num_resources	= ARRAY_SIZE(autcpu12_flash_resources),
+	.dev		= {
+		.platform_data	= &autcpu12_flash_pdata,
+	},
+};
+
 static void __init autcpu12_init(void)
 {
 	clps711x_devices_init();
+	platform_device_register(&autcpu12_flash_pdev);
 	platform_device_register_simple("video-clps711x", 0, NULL, 0);
 	platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
 					ARRAY_SIZE(autcpu12_cs8900_resource));
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index b95d60a..0db6f18 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -20,11 +20,6 @@
 #ifndef __ASM_ARCH_AUTCPU12_H
 #define __ASM_ARCH_AUTCPU12_H
 
-/*
- * The flash bank is wired to chip select 0
- */
-#define AUTCPU12_PHYS_FLASH		CS0_PHYS_BASE		/* physical */
-
 /* offset for device specific information structure */
 #define AUTCPU12_LCDINFO_OFFS		(0x00010000)	
 
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:28 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:28 +0400
Subject: [PATCH 06/15] ARM: clps711x: autcpu12: Move remaining specific
 definitions to board file
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-9-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-autcpu12.c        |  9 +++++-
 arch/arm/mach-clps711x/include/mach/autcpu12.h | 44 --------------------------
 2 files changed, 8 insertions(+), 45 deletions(-)
 delete mode 100644 arch/arm/mach-clps711x/include/mach/autcpu12.h

diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index 91a3ab5..cd50314 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -42,7 +42,6 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
 
 #include "common.h"
 #include "devices.h"
@@ -50,6 +49,14 @@
 /* NOR flash */
 #define AUTCPU12_FLASH_BASE	(CS0_PHYS_BASE)
 
+/* Board specific hardware definitions */
+#define AUTCPU12_CHAR_LCD_BASE	(CS1_PHYS_BASE + 0x00000000)
+#define AUTCPU12_CSAUX1_BASE	(CS1_PHYS_BASE + 0x04000000)
+#define AUTCPU12_CAN_BASE	(CS1_PHYS_BASE + 0x08000000)
+#define AUTCPU12_TOUCH_BASE	(CS1_PHYS_BASE + 0x0a000000)
+#define AUTCPU12_IO_BASE	(CS1_PHYS_BASE + 0x0c000000)
+#define AUTCPU12_LPT_BASE	(CS1_PHYS_BASE + 0x0e000000)
+
 /* NVRAM */
 #define AUTCPU12_NVRAM_BASE	(CS1_PHYS_BASE + 0x02000000)
 
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
deleted file mode 100644
index 0e00148..0000000
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * AUTCPU12 specific defines
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner at autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_AUTCPU12_H
-#define __ASM_ARCH_AUTCPU12_H
-
-/* offset for device specific information structure */
-#define AUTCPU12_LCDINFO_OFFS		(0x00010000)	
-
-/* Videomemory in the internal SRAM (CS 6) */
-#define AUTCPU12_PHYS_VIDEO		CS6_PHYS_BASE
-
-/*
-* All special IO's are tied to CS1
-*/
-#define AUTCPU12_PHYS_CHAR_LCD         	CS1_PHYS_BASE +0x00000000  /* physical */
-
-#define AUTCPU12_PHYS_CSAUX1           	CS1_PHYS_BASE +0x04000000  /* physical */
-
-#define AUTCPU12_PHYS_CAN              	CS1_PHYS_BASE +0x08000000  /* physical */
-
-#define AUTCPU12_PHYS_TOUCH            	CS1_PHYS_BASE +0x0A000000  /* physical */
-
-#define AUTCPU12_PHYS_IO               	CS1_PHYS_BASE +0x0C000000  /* physical */
-
-#define AUTCPU12_PHYS_LPT              	CS1_PHYS_BASE +0x0E000000  /* physical */
-
-#endif
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:30 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:30 +0400
Subject: [PATCH 08/15] ARM: clps711x: Move specific definitions from
 hardware.h to boards files
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-11-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-edb7211.c         | 8 ++++++--
 arch/arm/mach-clps711x/include/mach/hardware.h | 7 -------
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index e1c5573..3ba4b9e 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -39,9 +39,13 @@
 
 #define EDB7211_FLASH0_BASE	(CS0_PHYS_BASE)
 #define EDB7211_FLASH1_BASE	(CS1_PHYS_BASE)
+
 #define EDB7211_CS8900_BASE	(CS2_PHYS_BASE + 0x300)
 #define EDB7211_CS8900_IRQ	(IRQ_EINT3)
 
+/* The extra 8 lines of the keyboard matrix */
+#define EDB7211_EXTKBD_BASE	(CS3_PHYS_BASE)
+
 static struct resource edb7211_cs8900_resource[] __initdata = {
 	DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
 	DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
@@ -113,8 +117,8 @@ static struct gpio edb7211_gpios[] __initconst = {
 
 static struct map_desc edb7211_io_desc[] __initdata = {
 	{	/* Memory-mapped extra keyboard row */
-		.virtual	= IO_ADDRESS(EP7211_PHYS_EXTKBD),
-		.pfn		= __phys_to_pfn(EP7211_PHYS_EXTKBD),
+		.virtual	= IO_ADDRESS(EDB7211_EXTKBD_BASE),
+		.pfn		= __phys_to_pfn(EDB7211_EXTKBD_BASE),
 		.length		= SZ_1M,
 		.type		= MT_DEVICE,
 	},
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 2f23dd5..c5a8ea6 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -70,11 +70,4 @@
 #define CLPS711X_SDRAM0_BASE	(0xc0000000)
 #define CLPS711X_SDRAM1_BASE	(0xd0000000)
 
-#if defined (CONFIG_ARCH_EDB7211)
-
-/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
-#define EP7211_PHYS_EXTKBD	CS3_PHYS_BASE
-
-#endif /* CONFIG_ARCH_EDB7211 */
-
 #endif
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:31 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:31 +0400
Subject: [PATCH 09/15] ARM: clps711x: Replace "arch_initcall" in common code
 with ".init_early"
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-12-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-autcpu12.c |  1 +
 arch/arm/mach-clps711x/board-cdb89712.c |  1 +
 arch/arm/mach-clps711x/board-clep7312.c |  1 +
 arch/arm/mach-clps711x/board-edb7211.c  |  1 +
 arch/arm/mach-clps711x/board-fortunet.c |  1 +
 arch/arm/mach-clps711x/board-p720t.c    |  1 +
 arch/arm/mach-clps711x/common.c         | 10 +++-------
 arch/arm/mach-clps711x/common.h         |  1 +
 8 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index cd50314..5867aeb 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -271,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
 	.atag_offset	= 0x20000,
 	.nr_irqs	= CLPS711X_NR_IRQS,
 	.map_io		= clps711x_map_io,
+	.init_early	= clps711x_init_early,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.init_machine	= autcpu12_init,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index a80ae57..a9e38c6 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -141,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
 	.atag_offset	= 0x100,
 	.nr_irqs	= CLPS711X_NR_IRQS,
 	.map_io		= clps711x_map_io,
+	.init_early	= clps711x_init_early,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.init_machine	= cdb89712_init,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 014aa3c..b476424 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
 	.nr_irqs	= CLPS711X_NR_IRQS,
 	.fixup		= fixup_clep7312,
 	.map_io		= clps711x_map_io,
+	.init_early	= clps711x_init_early,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.handle_irq	= clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 3ba4b9e..db804b4 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -182,6 +182,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
 	.fixup		= fixup_edb7211,
 	.reserve	= edb7211_reserve,
 	.map_io		= edb7211_map_io,
+	.init_early	= clps711x_init_early,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.init_machine	= edb7211_init,
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index c5675ef..b1561e3 100644
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
 	.nr_irqs	= CLPS711X_NR_IRQS,
 	.fixup		= fortunet_fixup,
 	.map_io		= clps711x_map_io,
+	.init_early	= clps711x_init_early,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.handle_irq	= clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 601ef38..dd81b06 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -366,6 +366,7 @@ MACHINE_START(P720T, "ARM-Prospector720T")
 	.nr_irqs	= CLPS711X_NR_IRQS,
 	.fixup		= fixup_p720t,
 	.map_io		= clps711x_map_io,
+	.init_early	= clps711x_init_early,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.init_machine	= p720t_init,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f42302e..768d41c6 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -354,15 +354,11 @@ void clps711x_restart(char mode, const char *cmd)
 static void clps711x_idle(void)
 {
 	clps_writel(1, HALT);
-	__asm__ __volatile__(
-	"mov    r0, r0\n\
-	mov     r0, r0");
+	asm("mov r0, r0");
+	asm("mov r0, r0");
 }
 
-static int __init clps711x_idle_init(void)
+void __init clps711x_init_early(void)
 {
 	arm_pm_idle = clps711x_idle;
-	return 0;
 }
-
-arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2a22f4c 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -13,3 +13,4 @@ extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_init_early(void);
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:27 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:27 +0400
Subject: [PATCH 05/15] ARM: clps711x: autcpu12: Special driver for handling
 memory is removed
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-8-git-send-email-shc_work@mail.ru>

This patch provide migration to using "mtd-ram" driver instead of using
special driver for handling NVRAM memory.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-autcpu12.c        |  68 ++++++++++---
 arch/arm/mach-clps711x/include/mach/autcpu12.h |   2 -
 drivers/mtd/maps/Kconfig                       |   7 --
 drivers/mtd/maps/Makefile                      |   1 -
 drivers/mtd/maps/autcpu12-nvram.c              | 129 -------------------------
 5 files changed, 56 insertions(+), 151 deletions(-)
 delete mode 100644 drivers/mtd/maps/autcpu12-nvram.c

diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index 3e22d0b..91a3ab5 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -27,6 +27,7 @@
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
 #include <linux/platform_device.h>
@@ -49,6 +50,9 @@
 /* NOR flash */
 #define AUTCPU12_FLASH_BASE	(CS0_PHYS_BASE)
 
+/* NVRAM */
+#define AUTCPU12_NVRAM_BASE	(CS1_PHYS_BASE + 0x02000000)
+
 /* SmartMedia flash */
 #define AUTCPU12_SMC_BASE	(CS1_PHYS_BASE + 0x06000000)
 #define AUTCPU12_SMC_SEL_BASE	(AUTCPU12_SMC_BASE + 0x10)
@@ -74,17 +78,6 @@ static struct resource autcpu12_cs8900_resource[] __initdata = {
 	DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
 };
 
-static struct resource autcpu12_nvram_resource[] __initdata = {
-	DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-
-static struct platform_device autcpu12_nvram_pdev __initdata = {
-	.name		= "autcpu12_nvram",
-	.id		= -1,
-	.resource	= autcpu12_nvram_resource,
-	.num_resources	= ARRAY_SIZE(autcpu12_nvram_resource),
-};
-
 static struct resource autcpu12_nand_resource[] __initdata = {
 	DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
 };
@@ -194,6 +187,57 @@ static struct platform_device autcpu12_flash_pdev __initdata = {
 	},
 };
 
+static struct resource autcpu12_nvram_resource[] __initdata = {
+	DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
+};
+
+static struct platdata_mtd_ram autcpu12_nvram_pdata = {
+	.bankwidth	= 4,
+};
+
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+	.name		= "mtd-ram",
+	.id		= 0,
+	.resource	= autcpu12_nvram_resource,
+	.num_resources	= ARRAY_SIZE(autcpu12_nvram_resource),
+	.dev		= {
+		.platform_data	= &autcpu12_nvram_pdata,
+	},
+};
+
+static void __init autcpu12_nvram_init(void)
+{
+	void __iomem *nvram;
+	unsigned int save[2];
+	resource_size_t nvram_size = SZ_128K;
+
+	/*
+	 * Check for 32K/128K
+	 * Read ofs 0K
+	 * Read ofs 64K
+	 * Write complement to ofs 64K
+	 * Read and check result on ofs 0K
+	 * Restore contents
+	 */
+	nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
+	if (nvram) {
+		save[0] = readl(nvram + 0);
+		save[1] = readl(nvram + SZ_64K);
+		writel(~save[0], nvram + SZ_64K);
+		if (readl(nvram + 0) != save[0]) {
+			writel(save[0], nvram + 0);
+			nvram_size = SZ_32K;
+		} else
+			writel(save[1], nvram + SZ_64K);
+		iounmap(nvram);
+
+		autcpu12_nvram_resource[0].end =
+			autcpu12_nvram_resource[0].start + nvram_size - 1;
+		platform_device_register(&autcpu12_nvram_pdev);
+	} else
+		pr_err("Failed to remap NVRAM resource\n");
+}
+
 static void __init autcpu12_init(void)
 {
 	clps711x_devices_init();
@@ -202,7 +246,7 @@ static void __init autcpu12_init(void)
 	platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
 					ARRAY_SIZE(autcpu12_cs8900_resource));
 	platform_device_register(&autcpu12_mmgpio_pdev);
-	platform_device_register(&autcpu12_nvram_pdev);
+	autcpu12_nvram_init();
 }
 
 static void __init autcpu12_init_late(void)
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index 0db6f18..0e00148 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -31,8 +31,6 @@
 */
 #define AUTCPU12_PHYS_CHAR_LCD         	CS1_PHYS_BASE +0x00000000  /* physical */
 
-#define AUTCPU12_PHYS_NVRAM            	CS1_PHYS_BASE +0x02000000  /* physical */
-
 #define AUTCPU12_PHYS_CSAUX1           	CS1_PHYS_BASE +0x04000000  /* physical */
 
 #define AUTCPU12_PHYS_CAN              	CS1_PHYS_BASE +0x08000000  /* physical */
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index bed9d58..8b27ca0 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -297,13 +297,6 @@ config MTD_IXP4XX
 	  IXDP425 and Coyote. If you have an IXP4xx based board and
 	  would like to use the flash chips on it, say 'Y'.
 
-config MTD_AUTCPU12
-	bool "NV-RAM mapping AUTCPU12 board"
-	depends on ARCH_AUTCPU12
-	help
-	  This enables access to the NV-RAM on autronix autcpu12 board.
-	  If you have such a board, say 'Y'.
-
 config MTD_IMPA7
 	tristate "JEDEC Flash device mapped on impA7"
 	depends on ARM && MTD_JEDECPROBE
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 395a124..9fdbd4b 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_MTD_VMAX)		+= vmax301.o
 obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o
 obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
 obj-$(CONFIG_MTD_PCI)		+= pci.o
-obj-$(CONFIG_MTD_AUTCPU12)	+= autcpu12-nvram.o
 obj-$(CONFIG_MTD_IMPA7)		+= impa7.o
 obj-$(CONFIG_MTD_UCLINUX)	+= uclinux.o
 obj-$(CONFIG_MTD_NETtel)	+= nettel.o
diff --git a/drivers/mtd/maps/autcpu12-nvram.c b/drivers/mtd/maps/autcpu12-nvram.c
deleted file mode 100644
index c3525d2..0000000
--- a/drivers/mtd/maps/autcpu12-nvram.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * NV-RAM memory access on autcpu12
- * (C) 2002 Thomas Gleixner (gleixner at autronix.de)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/err.h>
-#include <linux/sizes.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-
-struct autcpu12_nvram_priv {
-	struct mtd_info *mtd;
-	struct map_info map;
-};
-
-static int autcpu12_nvram_probe(struct platform_device *pdev)
-{
-	map_word tmp, save0, save1;
-	struct resource *res;
-	struct autcpu12_nvram_priv *priv;
-
-	priv = devm_kzalloc(&pdev->dev,
-			    sizeof(struct autcpu12_nvram_priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, priv);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "failed to get memory resource\n");
-		return -ENOENT;
-	}
-
-	priv->map.bankwidth	= 4;
-	priv->map.phys		= res->start;
-	priv->map.size		= resource_size(res);
-	priv->map.virt = devm_ioremap_resource(&pdev->dev, res);
-	strcpy((char *)priv->map.name, res->name);
-	if (IS_ERR(priv->map.virt))
-		return PTR_ERR(priv->map.virt);
-
-	simple_map_init(&priv->map);
-
-	/*
-	 * Check for 32K/128K
-	 * read ofs 0
-	 * read ofs 0x10000
-	 * Write complement to ofs 0x100000
-	 * Read	and check result on ofs 0x0
-	 * Restore contents
-	 */
-	save0 = map_read(&priv->map, 0);
-	save1 = map_read(&priv->map, 0x10000);
-	tmp.x[0] = ~save0.x[0];
-	map_write(&priv->map, tmp, 0x10000);
-	tmp = map_read(&priv->map, 0);
-	/* if we find this pattern on 0x0, we have 32K size */
-	if (!map_word_equal(&priv->map, tmp, save0)) {
-		map_write(&priv->map, save0, 0x0);
-		priv->map.size = SZ_32K;
-	} else
-		map_write(&priv->map, save1, 0x10000);
-
-	priv->mtd = do_map_probe("map_ram", &priv->map);
-	if (!priv->mtd) {
-		dev_err(&pdev->dev, "probing failed\n");
-		return -ENXIO;
-	}
-
-	priv->mtd->owner	= THIS_MODULE;
-	priv->mtd->erasesize	= 16;
-	priv->mtd->dev.parent	= &pdev->dev;
-	if (!mtd_device_register(priv->mtd, NULL, 0)) {
-		dev_info(&pdev->dev,
-			 "NV-RAM device size %ldKiB registered on AUTCPU12\n",
-			 priv->map.size / SZ_1K);
-		return 0;
-	}
-
-	map_destroy(priv->mtd);
-	dev_err(&pdev->dev, "NV-RAM device addition failed\n");
-	return -ENOMEM;
-}
-
-static int autcpu12_nvram_remove(struct platform_device *pdev)
-{
-	struct autcpu12_nvram_priv *priv = platform_get_drvdata(pdev);
-
-	mtd_device_unregister(priv->mtd);
-	map_destroy(priv->mtd);
-
-	return 0;
-}
-
-static struct platform_driver autcpu12_nvram_driver = {
-	.driver		= {
-		.name	= "autcpu12_nvram",
-		.owner	= THIS_MODULE,
-	},
-	.probe		= autcpu12_nvram_probe,
-	.remove		= autcpu12_nvram_remove,
-};
-module_platform_driver(autcpu12_nvram_driver);
-
-MODULE_AUTHOR("Thomas Gleixner");
-MODULE_DESCRIPTION("autcpu12 NVRAM map driver");
-MODULE_LICENSE("GPL");
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:32 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:32 +0400
Subject: [PATCH 10/15] ARM: clps711x: Add clocksource framework
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-13-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/Kconfig                |  1 +
 arch/arm/mach-clps711x/common.c | 48 ++++++++++++++++++++++++++++++++++-------
 2 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 10cdfa9..2af27f7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -367,6 +367,7 @@ config ARCH_CLPS711X
 	select ARCH_REQUIRE_GPIOLIB
 	select AUTO_ZRELADDR
 	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
 	select COMMON_CLK
 	select CPU_ARM720T
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 768d41c6..bd65839 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -27,12 +27,14 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clockchips.h>
+#include <linux/clocksource.h>
 #include <linux/clk-provider.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <asm/system_misc.h>
 
 #include <mach/hardware.h>
@@ -251,13 +253,32 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
 		handle_IRQ(fls16(irqstat) + 16, regs);
 }
 
+static u32 notrace clps711x_sched_clock_read(void)
+{
+	return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
+}
+
 static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
 					 struct clock_event_device *evt)
 {
+	disable_irq(IRQ_TC2OI);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		enable_irq(IRQ_TC2OI);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		/* Not supported */
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_RESUME:
+		/* Left event sources disabled, no more interrupts appear */
+		break;
+	}
 }
 
 static struct clock_event_device clockevent_clps711x = {
-	.name		= "CLPS711x Clockevents",
+	.name		= "clps711x-clockevent",
 	.rating		= 300,
 	.features	= CLOCK_EVT_FEAT_PERIODIC,
 	.set_mode	= clps711x_clockevent_set_mode,
@@ -271,8 +292,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction clps711x_timer_irq = {
-	.name		= "CLPS711x Timer Tick",
-	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.name		= "clps711x-timer",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
 	.handler	= clps711x_timer_interrupt,
 };
 
@@ -320,9 +341,9 @@ void __init clps711x_timer_init(void)
 		else
 			timh = 541440;
 	} else
-		timh = cpu / 144;
+		timh = DIV_ROUND_CLOSEST(cpu, 144);
 
-	timl = timh / 256;
+	timl = DIV_ROUND_CLOSEST(timh, 256);
 
 	/* All clocks are fixed */
 	add_fixed_clk(clk_pll, "pll", pll);
@@ -335,13 +356,24 @@ void __init clps711x_timer_init(void)
 
 	pr_info("CPU frequency set at %i Hz.\n", cpu);
 
+	/* Start Timer1 in free running mode (Low frequency) */
+	tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
+	clps_writel(tmp, SYSCON1);
+
+	setup_sched_clock(clps711x_sched_clock_read, 16, timl);
+
+	clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
+			      "clps711x_clocksource", timl, 300, 16,
+			      clocksource_mmio_readw_down);
+
+	/* Set Timer2 prescaler */
 	clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
 
-	tmp = clps_readl(SYSCON1);
-	tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+	/* Start Timer2 in prescale mode (High frequency)*/
+	tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
 	clps_writel(tmp, SYSCON1);
 
-	clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
+	clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
 
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:29 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:29 +0400
Subject: [PATCH 07/15] ARM: clps711x: p720t: Define PLD registers as GPIOs
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-10-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-p720t.c         | 245 +++++++++++++++++++++------
 arch/arm/mach-clps711x/include/mach/syspld.h | 116 -------------
 2 files changed, 193 insertions(+), 168 deletions(-)
 delete mode 100644 arch/arm/mach-clps711x/include/mach/syspld.h

diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 48d0737..601ef38 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -23,10 +23,12 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/leds.h>
 #include <linux/sizes.h>
 #include <linux/backlight.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
@@ -38,7 +40,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/syspld.h>
 
 #include <video/platform_lcd.h>
 
@@ -52,6 +53,178 @@
 
 #define P720T_NAND_BASE		(CLPS711X_SDRAM1_BASE)
 
+#define P720T_MMGPIO_BASE	(CLPS711X_NR_GPIO)
+
+#define SYSPLD_PHYS_BASE	IOMEM(CS1_PHYS_BASE)
+
+#define PLD_INT			(SYSPLD_PHYS_BASE + 0x000000)
+#define PLD_INT_MMGPIO_BASE	(P720T_MMGPIO_BASE + 0)
+#define PLD_INT_PENIRQ		(PLD_INT_MMGPIO_BASE + 5)
+#define PLD_INT_UCB_IRQ		(PLD_INT_MMGPIO_BASE + 1)
+#define PLD_INT_KBD_ATN		(PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
+
+#define PLD_PWR			(SYSPLD_PHYS_BASE + 0x000004)
+#define PLD_PWR_MMGPIO_BASE	(P720T_MMGPIO_BASE + 8)
+#define PLD_PWR_EXT		(PLD_PWR_MMGPIO_BASE + 5)
+#define PLD_PWR_MODE		(PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON		(PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
+#define PLD_S3_ON		(PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
+#define PLD_S2_ON		(PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
+#define PLD_S1_ON		(PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
+
+#define PLD_KBD			(SYSPLD_PHYS_BASE + 0x000008)
+#define PLD_KBD_MMGPIO_BASE	(P720T_MMGPIO_BASE + 16)
+#define PLD_KBD_WAKE		(PLD_KBD_MMGPIO_BASE + 1)
+#define PLD_KBD_EN		(PLD_KBD_MMGPIO_BASE + 0)
+
+#define PLD_SPI			(SYSPLD_PHYS_BASE + 0x00000c)
+#define PLD_SPI_MMGPIO_BASE	(P720T_MMGPIO_BASE + 24)
+#define PLD_SPI_EN		(PLD_SPI_MMGPIO_BASE + 0)
+
+#define PLD_IO			(SYSPLD_PHYS_BASE + 0x000010)
+#define PLD_IO_MMGPIO_BASE	(P720T_MMGPIO_BASE + 32)
+#define PLD_IO_BOOTSEL		(PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
+#define PLD_IO_USER		(PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
+#define PLD_IO_LED3		(PLD_IO_MMGPIO_BASE + 4)
+#define PLD_IO_LED2		(PLD_IO_MMGPIO_BASE + 3)
+#define PLD_IO_LED1		(PLD_IO_MMGPIO_BASE + 2)
+#define PLD_IO_LED0		(PLD_IO_MMGPIO_BASE + 1)
+#define PLD_IO_LEDEN		(PLD_IO_MMGPIO_BASE + 0)
+
+#define PLD_IRDA		(SYSPLD_PHYS_BASE + 0x000014)
+#define PLD_IRDA_MMGPIO_BASE	(P720T_MMGPIO_BASE + 40)
+#define PLD_IRDA_EN		(PLD_IRDA_MMGPIO_BASE + 0)
+
+#define PLD_COM2		(SYSPLD_PHYS_BASE + 0x000018)
+#define PLD_COM2_MMGPIO_BASE	(P720T_MMGPIO_BASE + 48)
+#define PLD_COM2_EN		(PLD_COM2_MMGPIO_BASE + 0)
+
+#define PLD_COM1		(SYSPLD_PHYS_BASE + 0x00001c)
+#define PLD_COM1_MMGPIO_BASE	(P720T_MMGPIO_BASE + 56)
+#define PLD_COM1_EN		(PLD_COM1_MMGPIO_BASE + 0)
+
+#define PLD_AUD			(SYSPLD_PHYS_BASE + 0x000020)
+#define PLD_AUD_MMGPIO_BASE	(P720T_MMGPIO_BASE + 64)
+#define PLD_AUD_DIV1		(PLD_AUD_MMGPIO_BASE + 6)
+#define PLD_AUD_DIV0		(PLD_AUD_MMGPIO_BASE + 5)
+#define PLD_AUD_CLK_SEL1	(PLD_AUD_MMGPIO_BASE + 4)
+#define PLD_AUD_CLK_SEL0	(PLD_AUD_MMGPIO_BASE + 3)
+#define PLD_AUD_MIC_PWR		(PLD_AUD_MMGPIO_BASE + 2)
+#define PLD_AUD_MIC_GAIN	(PLD_AUD_MMGPIO_BASE + 1)
+#define PLD_AUD_CODEC_EN	(PLD_AUD_MMGPIO_BASE + 0)
+
+#define PLD_CF			(SYSPLD_PHYS_BASE + 0x000024)
+#define PLD_CF_MMGPIO_BASE	(P720T_MMGPIO_BASE + 72)
+#define PLD_CF2_SLEEP		(PLD_CF_MMGPIO_BASE + 5)
+#define PLD_CF1_SLEEP		(PLD_CF_MMGPIO_BASE + 4)
+#define PLD_CF2_nPDREQ		(PLD_CF_MMGPIO_BASE + 3)
+#define PLD_CF1_nPDREQ		(PLD_CF_MMGPIO_BASE + 2)
+#define PLD_CF2_nIRQ		(PLD_CF_MMGPIO_BASE + 1)
+#define PLD_CF1_nIRQ		(PLD_CF_MMGPIO_BASE + 0)
+
+#define PLD_SDC			(SYSPLD_PHYS_BASE + 0x000028)
+#define PLD_SDC_MMGPIO_BASE	(P720T_MMGPIO_BASE + 80)
+#define PLD_SDC_INT_EN		(PLD_SDC_MMGPIO_BASE + 2)
+#define PLD_SDC_WP		(PLD_SDC_MMGPIO_BASE + 1)
+#define PLD_SDC_CD		(PLD_SDC_MMGPIO_BASE + 0)
+
+#define PLD_CODEC		(SYSPLD_PHYS_BASE + 0x400000)
+#define PLD_CODEC_MMGPIO_BASE	(P720T_MMGPIO_BASE + 88)
+#define PLD_CODEC_IRQ3		(PLD_CODEC_MMGPIO_BASE + 4)
+#define PLD_CODEC_IRQ2		(PLD_CODEC_MMGPIO_BASE + 3)
+#define PLD_CODEC_IRQ1		(PLD_CODEC_MMGPIO_BASE + 2)
+#define PLD_CODEC_EN		(PLD_CODEC_MMGPIO_BASE + 0)
+
+#define PLD_BRITE		(SYSPLD_PHYS_BASE + 0x400004)
+#define PLD_BRITE_MMGPIO_BASE	(P720T_MMGPIO_BASE + 96)
+#define PLD_BRITE_UP		(PLD_BRITE_MMGPIO_BASE + 1)
+#define PLD_BRITE_DN		(PLD_BRITE_MMGPIO_BASE + 0)
+
+#define PLD_LCDEN		(SYSPLD_PHYS_BASE + 0x400008)
+#define PLD_LCDEN_MMGPIO_BASE	(P720T_MMGPIO_BASE + 104)
+#define PLD_LCDEN_EN		(PLD_LCDEN_MMGPIO_BASE + 0)
+
+#define PLD_TCH			(SYSPLD_PHYS_BASE + 0x400010)
+#define PLD_TCH_MMGPIO_BASE	(P720T_MMGPIO_BASE + 112)
+#define PLD_TCH_PENIRQ		(PLD_TCH_MMGPIO_BASE + 1)
+#define PLD_TCH_EN		(PLD_TCH_MMGPIO_BASE + 0)
+
+#define PLD_GPIO		(SYSPLD_PHYS_BASE + 0x400014)
+#define PLD_GPIO_MMGPIO_BASE	(P720T_MMGPIO_BASE + 120)
+#define PLD_GPIO2		(PLD_GPIO_MMGPIO_BASE + 2)
+#define PLD_GPIO1		(PLD_GPIO_MMGPIO_BASE + 1)
+#define PLD_GPIO0		(PLD_GPIO_MMGPIO_BASE + 0)
+
+static struct gpio p720t_gpios[] __initconst = {
+	{ PLD_S1_ON,	GPIOF_OUT_INIT_LOW,	"PLD_S1_ON" },
+	{ PLD_S2_ON,	GPIOF_OUT_INIT_LOW,	"PLD_S2_ON" },
+	{ PLD_S3_ON,	GPIOF_OUT_INIT_LOW,	"PLD_S3_ON" },
+	{ PLD_S4_ON,	GPIOF_OUT_INIT_LOW,	"PLD_S4_ON" },
+	{ PLD_KBD_EN,	GPIOF_OUT_INIT_LOW,	"PLD_KBD_EN" },
+	{ PLD_SPI_EN,	GPIOF_OUT_INIT_LOW,	"PLD_SPI_EN" },
+	{ PLD_IO_USER,	GPIOF_OUT_INIT_LOW,	"PLD_IO_USER" },
+	{ PLD_IO_LED0,	GPIOF_OUT_INIT_LOW,	"PLD_IO_LED0" },
+	{ PLD_IO_LED1,	GPIOF_OUT_INIT_LOW,	"PLD_IO_LED1" },
+	{ PLD_IO_LED2,	GPIOF_OUT_INIT_LOW,	"PLD_IO_LED2" },
+	{ PLD_IO_LED3,	GPIOF_OUT_INIT_LOW,	"PLD_IO_LED3" },
+	{ PLD_IO_LEDEN,	GPIOF_OUT_INIT_LOW,	"PLD_IO_LEDEN" },
+	{ PLD_IRDA_EN,	GPIOF_OUT_INIT_LOW,	"PLD_IRDA_EN" },
+	{ PLD_COM1_EN,	GPIOF_OUT_INIT_HIGH,	"PLD_COM1_EN" },
+	{ PLD_COM2_EN,	GPIOF_OUT_INIT_HIGH,	"PLD_COM2_EN" },
+	{ PLD_CODEC_EN,	GPIOF_OUT_INIT_LOW,	"PLD_CODEC_EN" },
+	{ PLD_LCDEN_EN,	GPIOF_OUT_INIT_LOW,	"PLD_LCDEN_EN" },
+	{ PLD_TCH_EN,	GPIOF_OUT_INIT_LOW,	"PLD_TCH_EN" },
+	{ P720T_USERLED,GPIOF_OUT_INIT_LOW,	"USER_LED" },
+};
+
+static struct resource p720t_mmgpio_resource[] __initdata = {
+	DEFINE_RES_MEM_NAMED(0, 4, "dat"),
+};
+
+static struct bgpio_pdata p720t_mmgpio_pdata = {
+	.ngpio	= 8,
+};
+
+static struct platform_device p720t_mmgpio __initdata = {
+	.name		= "basic-mmio-gpio",
+	.id		= -1,
+	.resource	= p720t_mmgpio_resource,
+	.num_resources	= ARRAY_SIZE(p720t_mmgpio_resource),
+	.dev		= {
+		.platform_data	= &p720t_mmgpio_pdata,
+	},
+};
+
+static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
+{
+	p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
+	p720t_mmgpio_pdata.base = gpiobase;
+
+	platform_device_register(&p720t_mmgpio);
+}
+
+static struct {
+	void __iomem	*addrbase;
+	int		gpiobase;
+} mmgpios[] __initconst = {
+	{ PLD_INT,	PLD_INT_MMGPIO_BASE },
+	{ PLD_PWR,	PLD_PWR_MMGPIO_BASE },
+	{ PLD_KBD,	PLD_KBD_MMGPIO_BASE },
+	{ PLD_SPI,	PLD_SPI_MMGPIO_BASE },
+	{ PLD_IO,	PLD_IO_MMGPIO_BASE },
+	{ PLD_IRDA,	PLD_IRDA_MMGPIO_BASE },
+	{ PLD_COM2,	PLD_COM2_MMGPIO_BASE },
+	{ PLD_COM1,	PLD_COM1_MMGPIO_BASE },
+	{ PLD_AUD,	PLD_AUD_MMGPIO_BASE },
+	{ PLD_CF,	PLD_CF_MMGPIO_BASE },
+	{ PLD_SDC,	PLD_SDC_MMGPIO_BASE },
+	{ PLD_CODEC,	PLD_CODEC_MMGPIO_BASE },
+	{ PLD_BRITE,	PLD_BRITE_MMGPIO_BASE },
+	{ PLD_LCDEN,	PLD_LCDEN_MMGPIO_BASE },
+	{ PLD_TCH,	PLD_TCH_MMGPIO_BASE },
+	{ PLD_GPIO,	PLD_GPIO_MMGPIO_BASE },
+};
+
 static struct resource p720t_nand_resource[] __initdata = {
 	DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
 };
@@ -93,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = {
 static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
 {
 	if (power) {
-		PLD_LCDEN = PLD_LCDEN_EN;
-		PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+		gpio_set_value(PLD_LCDEN_EN, 1);
+		gpio_set_value(PLD_S1_ON, 1);
+		gpio_set_value(PLD_S2_ON, 1);
+		gpio_set_value(PLD_S4_ON, 1);
 	} else {
-		PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
-		PLD_LCDEN = 0;
+		gpio_set_value(PLD_S1_ON, 0);
+		gpio_set_value(PLD_S2_ON, 0);
+		gpio_set_value(PLD_S4_ON, 0);
+		gpio_set_value(PLD_LCDEN_EN, 0);
 	}
 }
 
@@ -107,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = {
 
 static void p720t_lcd_backlight_set_intensity(int intensity)
 {
-	if (intensity)
-		PLD_PWR |= PLD_S3_ON;
-	else
-		PLD_PWR = 0;
+	gpio_set_value(PLD_S3_ON, intensity);
 }
 
 static struct generic_bl_info p720t_lcd_backlight_pdata = {
@@ -120,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = {
 	.set_bl_intensity	= p720t_lcd_backlight_set_intensity,
 };
 
-/*
- * Map the P720T system PLD. It occupies two address spaces:
- * 0x10000000 and 0x10400000. We map both regions as one.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
-	{
-		.virtual	= SYSPLD_VIRT_BASE,
-		.pfn		= __phys_to_pfn(SYSPLD_PHYS_BASE),
-		.length		= SZ_8M,
-		.type		= MT_DEVICE,
-	},
-};
-
 static void __init
 fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
 {
@@ -158,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
 	}
 }
 
-static void __init p720t_map_io(void)
-{
-	clps711x_map_io();
-	iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-
-static void __init p720t_init_early(void)
-{
-	/*
-	 * Power down as much as possible in case we don't
-	 * have the drivers loaded.
-	 */
-	PLD_LCDEN = 0;
-	PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-
-	PLD_KBD   = 0;
-	PLD_IO    = 0;
-	PLD_IRDA  = 0;
-	PLD_CODEC = 0;
-	PLD_TCH   = 0;
-	PLD_SPI   = 0;
-	if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
-		PLD_COM2 = 0;
-		PLD_COM1 = 0;
-	}
-}
-
 static struct gpio_led p720t_gpio_leds[] = {
 	{
 		.name			= "User LED",
@@ -200,12 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
 
 static void __init p720t_init(void)
 {
+	int i;
+
 	clps711x_devices_init();
+
+	for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
+		p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
+
+	platform_device_register(&p720t_nand_pdev);
 }
 
 static void __init p720t_init_late(void)
 {
-	platform_device_register(&p720t_nand_pdev);
+	WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
+
 	platform_device_register_data(&platform_bus, "platform-lcd", 0,
 				      &p720t_lcd_power_pdata,
 				      sizeof(p720t_lcd_power_pdata));
@@ -223,8 +365,7 @@ MACHINE_START(P720T, "ARM-Prospector720T")
 	.atag_offset	= 0x100,
 	.nr_irqs	= CLPS711X_NR_IRQS,
 	.fixup		= fixup_p720t,
-	.map_io		= p720t_map_io,
-	.init_early	= p720t_init_early,
+	.map_io		= clps711x_map_io,
 	.init_irq	= clps711x_init_irq,
 	.init_time	= clps711x_timer_init,
 	.init_machine	= p720t_init,
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
deleted file mode 100644
index 9a43315..0000000
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/syspld.h
- *
- *  System Control PLD register definitions.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSPLD_H
-#define __ASM_ARCH_SYSPLD_H
-
-#define SYSPLD_PHYS_BASE	(0x10000000)
-#define SYSPLD_VIRT_BASE	IO_ADDRESS(SYSPLD_PHYS_BASE)
-
-#define SYSPLD_REG(type, off)	(*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
-
-#define PLD_INT		SYSPLD_REG(u32, 0x000000)
-#define PLD_INT_PENIRQ		(1 << 5)
-#define PLD_INT_UCB_IRQ		(1 << 1)
-#define PLD_INT_KBD_ATN		(1 << 0)	/* EINT1 */
-
-#define PLD_PWR		SYSPLD_REG(u32, 0x000004)
-#define PLD_PWR_EXT		(1 << 5)
-#define PLD_PWR_MODE		(1 << 4)	/* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON		(1 << 3)	/* LCD bias voltage enable */
-#define PLD_S3_ON		(1 << 2)	/* LCD backlight enable */
-#define PLD_S2_ON		(1 << 1)	/* LCD 3V3 supply enable */
-#define PLD_S1_ON		(1 << 0)	/* LCD 3V supply enable */
-
-#define PLD_KBD		SYSPLD_REG(u32, 0x000008)
-#define PLD_KBD_WAKE		(1 << 1)
-#define PLD_KBD_EN		(1 << 0)
-
-#define PLD_SPI		SYSPLD_REG(u32, 0x00000c)
-#define PLD_SPI_EN		(1 << 0)
-
-#define PLD_IO		SYSPLD_REG(u32, 0x000010)
-#define PLD_IO_BOOTSEL		(1 << 6)	/* boot sel switch */
-#define PLD_IO_USER		(1 << 5)	/* user defined switch */
-#define PLD_IO_LED3		(1 << 4)
-#define PLD_IO_LED2		(1 << 3)
-#define PLD_IO_LED1		(1 << 2)
-#define PLD_IO_LED0		(1 << 1)
-#define PLD_IO_LEDEN		(1 << 0)
-
-#define PLD_IRDA	SYSPLD_REG(u32, 0x000014)
-#define PLD_IRDA_EN		(1 << 0)
-
-#define PLD_COM2	SYSPLD_REG(u32, 0x000018)
-#define PLD_COM2_EN		(1 << 0)
-
-#define PLD_COM1	SYSPLD_REG(u32, 0x00001c)
-#define PLD_COM1_EN		(1 << 0)
-
-#define PLD_AUD		SYSPLD_REG(u32, 0x000020)
-#define PLD_AUD_DIV1		(1 << 6)
-#define PLD_AUD_DIV0		(1 << 5)
-#define PLD_AUD_CLK_SEL1	(1 << 4)
-#define PLD_AUD_CLK_SEL0	(1 << 3)
-#define PLD_AUD_MIC_PWR		(1 << 2)
-#define PLD_AUD_MIC_GAIN	(1 << 1)
-#define PLD_AUD_CODEC_EN	(1 << 0)
-
-#define PLD_CF		SYSPLD_REG(u32, 0x000024)
-#define PLD_CF2_SLEEP		(1 << 5)
-#define PLD_CF1_SLEEP		(1 << 4)
-#define PLD_CF2_nPDREQ		(1 << 3)
-#define PLD_CF1_nPDREQ		(1 << 2)
-#define PLD_CF2_nIRQ		(1 << 1)
-#define PLD_CF1_nIRQ		(1 << 0)
-
-#define PLD_SDC		SYSPLD_REG(u32, 0x000028)
-#define PLD_SDC_INT_EN		(1 << 2)
-#define PLD_SDC_WP		(1 << 1)
-#define PLD_SDC_CD		(1 << 0)
-
-#define PLD_FPGA	SYSPLD_REG(u32, 0x00002c)
-
-#define PLD_CODEC	SYSPLD_REG(u32, 0x400000)
-#define PLD_CODEC_IRQ3		(1 << 4)
-#define PLD_CODEC_IRQ2		(1 << 3)
-#define PLD_CODEC_IRQ1		(1 << 2)
-#define PLD_CODEC_EN		(1 << 0)
-
-#define PLD_BRITE	SYSPLD_REG(u32, 0x400004)
-#define PLD_BRITE_UP		(1 << 1)
-#define PLD_BRITE_DN		(1 << 0)
-
-#define PLD_LCDEN	SYSPLD_REG(u32, 0x400008)
-#define PLD_LCDEN_EN		(1 << 0)
-
-#define PLD_ID		SYSPLD_REG(u32, 0x40000c)
-
-#define PLD_TCH		SYSPLD_REG(u32, 0x400010)
-#define PLD_TCH_PENIRQ		(1 << 1)
-#define PLD_TCH_EN		(1 << 0)
-
-#define PLD_GPIO	SYSPLD_REG(u32, 0x400014)
-#define PLD_GPIO2		(1 << 2)
-#define PLD_GPIO1		(1 << 1)
-#define PLD_GPIO0		(1 << 0)
-
-#endif
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:36 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:36 +0400
Subject: [PATCH 14/15] ARM: clps711x: Add support for SYSCON driver
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-17-git-send-email-shc_work@mail.ru>

This patch adds support for SYSCON driver for CLPS711X targets.
At this time there are no users for this driver, but it is will
be used as start point to use in CLPS711X drivers and remove
<mach/xx> dependencies.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/Kconfig                               |  1 +
 arch/arm/mach-clps711x/devices.c               | 20 ++++++
 arch/arm/mach-clps711x/include/mach/clps711x.h | 88 +-----------------------
 drivers/mfd/syscon.c                           |  3 +
 include/linux/mfd/syscon/clps711x.h            | 94 ++++++++++++++++++++++++++
 5 files changed, 120 insertions(+), 86 deletions(-)
 create mode 100644 include/linux/mfd/syscon/clps711x.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2af27f7..6228676 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -371,6 +371,7 @@ config ARCH_CLPS711X
 	select COMMON_CLK
 	select CPU_ARM720T
 	select GENERIC_CLOCKEVENTS
+	select MFD_SYSCON
 	select MULTI_IRQ_HANDLER
 	select SPARSE_IRQ
 	help
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 21161ed..856b81c 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/platform_device.h>
+#include <linux/sizes.h>
 
 #include <mach/hardware.h>
 
@@ -42,7 +43,26 @@ static void __init clps711x_add_gpio(void)
 	}
 }
 
+const struct resource clps711x_syscon_res[] __initconst = {
+	/* SYSCON1, SYSFLG1 */
+	DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
+	/* SYSCON2, SYSFLG2 */
+	DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
+	/* SYSCON3 */
+	DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
+};
+
+static void __init clps711x_add_syscon(void)
+{
+	unsigned i;
+
+	for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
+		platform_device_register_simple("clps711x-syscon", i + 1,
+						&clps711x_syscon_res[i], 1);
+}
+
 void __init clps711x_devices_init(void)
 {
 	clps711x_add_gpio();
+	clps711x_add_syscon();
 }
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 01d1b95..0286f4b 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -21,6 +21,8 @@
 #ifndef __MACH_CLPS711X_H
 #define __MACH_CLPS711X_H
 
+#include <linux/mfd/syscon/clps711x.h>
+
 #define CLPS711X_PHYS_BASE	(0x80000000)
 
 #define PADR		(0x0000)
@@ -96,83 +98,9 @@
 #define RANDID2		(0x2708)
 #define RANDID3		(0x270c)
 
-/* common bits: SYSCON1 / SYSCON2 */
-#define SYSCON_UARTEN		(1 << 8)
-
-#define SYSCON1_KBDSCAN(x)	((x) & 15)
-#define SYSCON1_KBDSCANMASK	(15)
-#define SYSCON1_TC1M		(1 << 4)
-#define SYSCON1_TC1S		(1 << 5)
-#define SYSCON1_TC2M		(1 << 6)
-#define SYSCON1_TC2S		(1 << 7)
-#define SYSCON1_UART1EN		SYSCON_UARTEN
-#define SYSCON1_BZTOG		(1 << 9)
-#define SYSCON1_BZMOD		(1 << 10)
-#define SYSCON1_DBGEN		(1 << 11)
-#define SYSCON1_LCDEN		(1 << 12)
-#define SYSCON1_CDENTX		(1 << 13)
-#define SYSCON1_CDENRX		(1 << 14)
-#define SYSCON1_SIREN		(1 << 15)
-#define SYSCON1_ADCKSEL(x)	(((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK	(3 << 16)
-#define SYSCON1_EXCKEN		(1 << 18)
-#define SYSCON1_WAKEDIS		(1 << 19)
-#define SYSCON1_IRTXM		(1 << 20)
-
-/* common bits: SYSFLG1 / SYSFLG2 */
-#define SYSFLG_UBUSY		(1 << 11)
-#define SYSFLG_URXFE		(1 << 22)
-#define SYSFLG_UTXFF		(1 << 23)
-
-#define SYSFLG1_MCDR		(1 << 0)
-#define SYSFLG1_DCDET		(1 << 1)
-#define SYSFLG1_WUDR		(1 << 2)
-#define SYSFLG1_WUON		(1 << 3)
-#define SYSFLG1_CTS		(1 << 8)
-#define SYSFLG1_DSR		(1 << 9)
-#define SYSFLG1_DCD		(1 << 10)
-#define SYSFLG1_UBUSY		SYSFLG_UBUSY
-#define SYSFLG1_NBFLG		(1 << 12)
-#define SYSFLG1_RSTFLG		(1 << 13)
-#define SYSFLG1_PFFLG		(1 << 14)
-#define SYSFLG1_CLDFLG		(1 << 15)
-#define SYSFLG1_URXFE		SYSFLG_URXFE
-#define SYSFLG1_UTXFF		SYSFLG_UTXFF
-#define SYSFLG1_CRXFE		(1 << 24)
-#define SYSFLG1_CTXFF		(1 << 25)
-#define SYSFLG1_SSIBUSY		(1 << 26)
-#define SYSFLG1_ID		(1 << 29)
-#define SYSFLG1_VERID(x)	(((x) >> 30) & 3)
-#define SYSFLG1_VERID_MASK	(3 << 30)
-
-#define SYSFLG2_SSRXOF		(1 << 0)
-#define SYSFLG2_RESVAL		(1 << 1)
-#define SYSFLG2_RESFRM		(1 << 2)
-#define SYSFLG2_SS2RXFE		(1 << 3)
-#define SYSFLG2_SS2TXFF		(1 << 4)
-#define SYSFLG2_SS2TXUF		(1 << 5)
-#define SYSFLG2_CKMODE		(1 << 6)
-#define SYSFLG2_UBUSY		SYSFLG_UBUSY
-#define SYSFLG2_URXFE		SYSFLG_URXFE
-#define SYSFLG2_UTXFF		SYSFLG_UTXFF
-
 #define LCDCON_GSEN		(1 << 30)
 #define LCDCON_GSMD		(1 << 31)
 
-#define SYSCON2_SERSEL		(1 << 0)
-#define SYSCON2_KBD6		(1 << 1)
-#define SYSCON2_DRAMZ		(1 << 2)
-#define SYSCON2_KBWEN		(1 << 3)
-#define SYSCON2_SS2TXEN		(1 << 4)
-#define SYSCON2_PCCARD1		(1 << 5)
-#define SYSCON2_PCCARD2		(1 << 6)
-#define SYSCON2_SS2RXEN		(1 << 7)
-#define SYSCON2_UART2EN		SYSCON_UARTEN
-#define SYSCON2_SS2MAEN		(1 << 9)
-#define SYSCON2_OSTB		(1 << 12)
-#define SYSCON2_CLKENSL		(1 << 13)
-#define SYSCON2_BUZFREQ		(1 << 14)
-
 /* common bits: UARTDR1 / UARTDR2 */
 #define UARTDR_FRMERR		(1 << 8)
 #define UARTDR_PARERR		(1 << 9)
@@ -228,18 +156,6 @@
 #define DAI64FS_MCLK256EN	(1 << 3)
 #define DAI64FS_LOOPBACK	(1 << 5)
 
-#define SYSCON3_ADCCON		(1 << 0)
-#define SYSCON3_CLKCTL0		(1 << 1)
-#define SYSCON3_CLKCTL1		(1 << 2)
-#define SYSCON3_DAISEL		(1 << 3)
-#define SYSCON3_ADCCKNSEN	(1 << 4)
-#define SYSCON3_VERSN(x)	(((x) >> 5) & 7)
-#define SYSCON3_VERSN_MASK	(7 << 5)
-#define SYSCON3_FASTWAKE	(1 << 8)
-#define SYSCON3_DAIEN		(1 << 9)
-#define SYSCON3_128FS		SYSCON3_DAIEN
-#define SYSCON3_ENPD67		(1 << 10)
-
 #define SDCONF_ACTIVE		(1 << 10)
 #define SDCONF_CLKCTL		(1 << 9)
 #define SDCONF_WIDTH_4		(0 << 7)
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index 962a6e1..1a31512 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -159,6 +159,9 @@ static int syscon_probe(struct platform_device *pdev)
 
 static const struct platform_device_id syscon_ids[] = {
 	{ "syscon", },
+#ifdef CONFIG_ARCH_CLPS711X
+	{ "clps711x-syscon", },
+#endif
 	{ }
 };
 
diff --git a/include/linux/mfd/syscon/clps711x.h b/include/linux/mfd/syscon/clps711x.h
new file mode 100644
index 0000000..26355ab
--- /dev/null
+++ b/include/linux/mfd/syscon/clps711x.h
@@ -0,0 +1,94 @@
+/*
+ *  CLPS711X system register bits definitions
+ *
+ *  Copyright (C) 2013 Alexander Shiyan <shc_work at mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_CLPS711X_H_
+#define _LINUX_MFD_SYSCON_CLPS711X_H_
+
+#define SYSCON_OFFSET		(0x00)
+#define SYSFLG_OFFSET		(0x40)
+
+#define SYSCON1_KBDSCAN(x)	((x) & 15)
+#define SYSCON1_KBDSCAN_MASK	(15)
+#define SYSCON1_TC1M		(1 << 4)
+#define SYSCON1_TC1S		(1 << 5)
+#define SYSCON1_TC2M		(1 << 6)
+#define SYSCON1_TC2S		(1 << 7)
+#define SYSCON1_BZTOG		(1 << 9)
+#define SYSCON1_BZMOD		(1 << 10)
+#define SYSCON1_DBGEN		(1 << 11)
+#define SYSCON1_LCDEN		(1 << 12)
+#define SYSCON1_CDENTX		(1 << 13)
+#define SYSCON1_CDENRX		(1 << 14)
+#define SYSCON1_SIREN		(1 << 15)
+#define SYSCON1_ADCKSEL(x)	(((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK	(3 << 16)
+#define SYSCON1_EXCKEN		(1 << 18)
+#define SYSCON1_WAKEDIS		(1 << 19)
+#define SYSCON1_IRTXM		(1 << 20)
+
+#define SYSCON2_SERSEL		(1 << 0)
+#define SYSCON2_KBD6		(1 << 1)
+#define SYSCON2_DRAMZ		(1 << 2)
+#define SYSCON2_KBWEN		(1 << 3)
+#define SYSCON2_SS2TXEN		(1 << 4)
+#define SYSCON2_PCCARD1		(1 << 5)
+#define SYSCON2_PCCARD2		(1 << 6)
+#define SYSCON2_SS2RXEN		(1 << 7)
+#define SYSCON2_SS2MAEN		(1 << 9)
+#define SYSCON2_OSTB		(1 << 12)
+#define SYSCON2_CLKENSL		(1 << 13)
+#define SYSCON2_BUZFREQ		(1 << 14)
+
+#define SYSCON3_ADCCON		(1 << 0)
+#define SYSCON3_CLKCTL0		(1 << 1)
+#define SYSCON3_CLKCTL1		(1 << 2)
+#define SYSCON3_DAISEL		(1 << 3)
+#define SYSCON3_ADCCKNSEN	(1 << 4)
+#define SYSCON3_VERSN(x)	(((x) >> 5) & 7)
+#define SYSCON3_VERSN_MASK	(7 << 5)
+#define SYSCON3_FASTWAKE	(1 << 8)
+#define SYSCON3_DAIEN		(1 << 9)
+#define SYSCON3_128FS		SYSCON3_DAIEN
+#define SYSCON3_ENPD67		(1 << 10)
+
+#define SYSCON_UARTEN		(1 << 8)
+
+#define SYSFLG1_MCDR		(1 << 0)
+#define SYSFLG1_DCDET		(1 << 1)
+#define SYSFLG1_WUDR		(1 << 2)
+#define SYSFLG1_WUON		(1 << 3)
+#define SYSFLG1_CTS		(1 << 8)
+#define SYSFLG1_DSR		(1 << 9)
+#define SYSFLG1_DCD		(1 << 10)
+#define SYSFLG1_NBFLG		(1 << 12)
+#define SYSFLG1_RSTFLG		(1 << 13)
+#define SYSFLG1_PFFLG		(1 << 14)
+#define SYSFLG1_CLDFLG		(1 << 15)
+#define SYSFLG1_CRXFE		(1 << 24)
+#define SYSFLG1_CTXFF		(1 << 25)
+#define SYSFLG1_SSIBUSY		(1 << 26)
+#define SYSFLG1_ID		(1 << 29)
+#define SYSFLG1_VERID(x)	(((x) >> 30) & 3)
+#define SYSFLG1_VERID_MASK	(3 << 30)
+
+#define SYSFLG2_SSRXOF		(1 << 0)
+#define SYSFLG2_RESVAL		(1 << 1)
+#define SYSFLG2_RESFRM		(1 << 2)
+#define SYSFLG2_SS2RXFE		(1 << 3)
+#define SYSFLG2_SS2TXFF		(1 << 4)
+#define SYSFLG2_SS2TXUF		(1 << 5)
+#define SYSFLG2_CKMODE		(1 << 6)
+
+#define SYSFLG_UBUSY		(1 << 11)
+#define SYSFLG_URXFE		(1 << 22)
+#define SYSFLG_UTXFF		(1 << 23)
+
+#endif
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:37 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:37 +0400
Subject: [PATCH 15/15] ARM: clps711x: Update defconfig
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-18-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/configs/clps711x_defconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 1cd94c3..9e8c831 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -31,21 +31,18 @@ CONFIG_EP7211_DONGLE=y
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_AUTCPU12=y
 CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPIO=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 CONFIG_CS89x0=y
 CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -63,7 +60,11 @@ CONFIG_CS89x0_PLATFORM=y
 # CONFIG_VT is not set
 CONFIG_SERIAL_CLPS711X_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
+CONFIG_SPI_CLPS711X=y
+CONFIG_GPIO_CLPS711X=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
@@ -87,4 +88,3 @@ CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
-# CONFIG_CRC32 is not set
-- 
1.8.1.5



From shc_work at mail.ru  Mon May 13 13:07:33 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:33 +0400
Subject: [PATCH 11/15] ARM: clps711x: Optimize interrupt handling
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-14-git-send-email-shc_work@mail.ru>

This patch modify interrupt handler for processing all penging interrupts
at once.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/common.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index bd65839..f6d1746 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -215,7 +215,7 @@ void __init clps711x_init_irq(void)
 	}
 }
 
-inline u32 fls16(u32 x)
+static inline u32 fls16(u32 x)
 {
 	u32 r = 15;
 
@@ -239,18 +239,24 @@ inline u32 fls16(u32 x)
 
 asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
 {
-	u32 irqstat;
-	void __iomem *base = CLPS711X_VIRT_BASE;
+	do {
+		u32 irqstat;
+		void __iomem *base = CLPS711X_VIRT_BASE;
+
+		irqstat = readw_relaxed(base + INTSR1) &
+			  readw_relaxed(base + INTMR1);
+		if (irqstat)
+			handle_IRQ(fls16(irqstat), regs);
+
+		irqstat = readw_relaxed(base + INTSR2) &
+			  readw_relaxed(base + INTMR2);
+		if (irqstat) {
+			handle_IRQ(fls16(irqstat) + 16, regs);
+			continue;
+		}
 
-	irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
-	if (irqstat) {
-		handle_IRQ(fls16(irqstat), regs);
-		return;
-	}
-
-	irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
-	if (likely(irqstat))
-		handle_IRQ(fls16(irqstat) + 16, regs);
+		break;
+	} while (1);
 }
 
 static u32 notrace clps711x_sched_clock_read(void)
-- 
1.8.1.5



From olof at lixom.net  Mon May 13 13:09:00 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 13 May 2013 10:09:00 -0700
Subject: [PATCH 09/14] ARM: mvebu: Remove init_irq declaration in machine
 description
In-Reply-To: <51910C81.5050501@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-10-git-send-email-maxime.ripard@free-electrons.com>
 <20130513151934.GM31290@titan.lakedaemon.net>
 <51910C81.5050501@free-electrons.com>
Message-ID: <CAOesGMgD6j9BE-kVe1rJjNFRtoV=e08B=o9hyhk1xfKLjsRF2g@mail.gmail.com>

On Mon, May 13, 2013 at 8:53 AM, Maxime Ripard
<maxime.ripard at free-electrons.com> wrote:
> Hi Jason,
>
> Le 13/05/2013 17:19, Jason Cooper a ?crit :
>> On Mon, May 13, 2013 at 11:44:08AM +0200, Maxime Ripard wrote:
>>> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
>>> specified") removed the need to explictly setup the init_irq field in
>>> the machine description when using only irqchip_init. Remove that
>>> declaration for mvebu as well.
>>>
>>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>>> ---
>>>  arch/arm/mach-mvebu/armada-370-xp.c | 1 -
>>>  1 file changed, 1 deletion(-)
>>
>> Maxime,
>>
>> Do do want the individual submaintainers to take these?  Or, send one
>> branch to Arnd and Olof?  I'm fine with either one as any merge
>> conflicts should be trivial.
>
> I don't have a strong opinion on this one, I guess both will be fine.
> Arnd, Olof, what do you prefer?
>
> I'll probably have to send a v2 anyway, I forgot to remove the include
> of the irqchip headers.

Since each and every patch applies cleanly and things work well both
before and after, let's have each maintainer that is active apply
their own. If there are platforms that don't have a significant number
of patches, i.e. if they're not collecting a branch, then we can apply
those. Please follow up with us with the stragglers, I'll assume the
rest will come in through the respective maintainers.


-Olof


From cov at codeaurora.org  Mon May 13 13:16:51 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 13 May 2013 13:16:51 -0400
Subject: [PATCH V2] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
In-Reply-To: <fae8138d41c55928a3c71b7073aea3b0@localhost>
References: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org>
 <51910559.6060106@codeaurora.org>
 <fae8138d41c55928a3c71b7073aea3b0@localhost>
Message-ID: <51912003.6080406@codeaurora.org>

On 05/13/2013 12:02 PM, Marc Zyngier wrote:
> On Mon, 13 May 2013 11:23:05 -0400, Christopher Covington
> <cov at codeaurora.org> wrote:
>> Hi Pranavkumar,
>>
>> On 05/10/2013 03:23 AM, Pranavkumar Sawargaonkar wrote:
>>> This patch does following fixes:
>>>
>>> 1. Make HCR_* flags as unsigned long long constants
>>> Reason : By default, compiler assumes numeric constants as
>>> signed hence sign extending it when assigned to unsigned variable
>>> such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
>>> HCR_CD making entire guest memory non-cacheable. On real HW, this
>>> breaks Stage2 ttbl walks and also breaks VirtIO.
>>>
>>> 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.
>>>
>>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>>> ---
>>>  arch/arm64/include/asm/kvm_arm.h |   73
>>>  +++++++++++++++++++-------------------
>>>  1 file changed, 37 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/asm/kvm_arm.h
>>> b/arch/arm64/include/asm/kvm_arm.h
>>> index 8ced0ca..14ead69 100644
>>> --- a/arch/arm64/include/asm/kvm_arm.h
>>> +++ b/arch/arm64/include/asm/kvm_arm.h
>>> @@ -18,44 +18,45 @@
>>>  #ifndef __ARM64_KVM_ARM_H__
>>>  #define __ARM64_KVM_ARM_H__
>>>  
>>> +#include <linux/const.h>
>>>  #include <asm/types.h>
>>>  
>>>  /* Hyp Configuration Register (HCR) bits */
>>> -#define HCR_ID		(1 << 33)
>>> -#define HCR_CD		(1 << 32)
>>> +#define HCR_ID		(UL(0x1) << 33)
>>> +#define HCR_CD		(UL(0x1) << 32)
>>
>> Consider using the BIT() macro from linux/bitops.h to improve
> readability.
> 
> This would probably cause problems when using these macros from assembly
> code.

It does indeed cause problems. What a shame. How about a quick local
definition, to perhaps be eventually replaced by a more accessible shared
definition?

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From soren.brinkmann at xilinx.com  Mon May 13 13:24:33 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Mon, 13 May 2013 10:24:33 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <519112F9.2010102@gmail.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
Message-ID: <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>

On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
> On 05/13/13 18:09, S?ren Brinkmann wrote:
> >On Mon, May 13, 2013 at 09:21:35AM +0400, Mark Brown wrote:
> >>On Sun, May 12, 2013 at 12:05:04PM -0700, S?ren Brinkmann wrote:
> >>>On Sun, May 12, 2013 at 06:33:44PM +0400, Mark Brown wrote:
> >>>>No, there's no confusion here - the clocks that are being exposed to
> >>>>userspace are the clocks which enter the FPGA.  The driver or whatever
> >>>>that understands the FPGA can do what is needed to control them,
> >>>>including routing them on to subdevices it instantiates or exposing them
> >>>>to userspace.
> >>
> >>>Such a driver does not exist in general.
> >>>For some IP cores, Linux drivers do exist and then
> >>>they are supposed to directly use the CCF, IMHO, no need to expose
> >>>things to userspace in that case.
> >>>I'm trying to cover cases, in which there is no driver available/needed for
> >>>the FPGA design, other than some simple clock controls.
> >>
> >>You're not understanding the point here.  If you've got a
> >>reprogrammmable FPGA you at least need some way to get the FPGA image in
> >>there.  This driver is presumably responsible for instantiating whatever
> >>is needed to control what is on the FPGA, that could include punting the
> >>clocks to userspace if that's sane.
> >Well, that driver actually exists. But that just programs a bitstream
> >you give it to program. It does not know anything about the design it
> >programs and cannot make any kind of decision whether the clocks should
> >be userspace controlled or not.
> 
> Soeren,
> 
> what Mark wants to point out is that you add fabric clocks to the Xilinx
> driver instead. This way, you will have user-space controllable clocks
> but only if you loaded the xilinx driver first.
What "Xilinx driver", are we talking about?

> 
> IIRC the fabric clock controller provided by Zynq _is_ always there and
> accessible from ARM CPUs. You just don't have a new generic driver
> allowing to poke with all clocks, but a xilinx only driver allowing you
> to set the (xilinx only) fabric clocks.
Right.

> 
> I've played with Zynq a while ago, did Xilinx mainline the bitfile
> driver already? If not, why don't you give it a shot?
The device config driver is not in mainline, AFAIK. And I think it's in
rather bad shape and needs a lot of work before it is upstreamable. But
this is probably the right place to put this.
On the other hand, currently this driver is only required for
programming the FPGA from Linux, which is not required. One of the
bootloaders could do this for you earlier.

	S?ren




From jason at lakedaemon.net  Mon May 13 13:30:17 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 13:30:17 -0400
Subject: [PATCH 0/3] ARM: Kirkwood: Add DT support for (eSATA) Sheevaplug
In-Reply-To: <1366660500-26835-1-git-send-email-gmbnomis@gmail.com>
References: <1366660500-26835-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130513173017.GV31290@titan.lakedaemon.net>

On Mon, Apr 22, 2013 at 09:54:57PM +0200, Simon Baatz wrote:
> These patches add DT support for the Sheevaplugs by Globalscale
> Technologies.  There exists two versions, one with an eSATA port and
> one without.
> 
> Surprisingly, the conversion was not straight forward. In the eSATA
> version (board revision 1.3), the CD and WP pins are connected to GPIO
> lines, but I could not get this to work.  Apparently, I am not the only
> one ([1]).  I found that the pins are reversed on my hardware and use
> different active low/active high settings.
> 
> Thus, the first patch adds support for the GPIO active low/high flag in
> DT to the mvsdio driver.
> 
> With that, everything except the Gigabit Ethernet can be described in
> the DTS.  I have split the DTS and the board support files into two
> patches.  This way, we can drop the last patch once we can describe
> everything in the DTS or we can squash them together if we don't want
> to wait.
> 
> I could only test on an eSATA Sheevaplug. I found patches with
> different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
> someone with the hardware could give this a spin on a non-eSATA
> version.  Some additional testing of the change detect and write
> protect behaviour for sdio can't hurt either.  I hope that there aren't
> board revisions with different CD/WP pins out there.
> 
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/062567.html
> 
> Simon Baatz (3):
>   mmc: mvsdio: Support inverted CD and WP GPIO lines
>   ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug
>   ARM: Kirkwood: Add DT support for Sheevaplug and Sheevaplug eSATA

Simon,

Were you able to find any time to work on this?

thx,

Jason.


From cov at codeaurora.org  Mon May 13 13:36:59 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 13 May 2013 13:36:59 -0400
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <CAAHg+Hi6BHqwOznnC9qxkc5pBWz7r5qpz9Nhh=EeNenhjhHohg@mail.gmail.com>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
 <8761yn382w.fsf@rustcorp.com.au>
 <CAAHg+Hi6BHqwOznnC9qxkc5pBWz7r5qpz9Nhh=EeNenhjhHohg@mail.gmail.com>
Message-ID: <519124BB.9030709@codeaurora.org>

Hi Pranavkumar,

On 05/13/2013 02:56 AM, Pranavkumar Sawargaonkar wrote:
> Hi Rusty,
> 
> On 13 May 2013 08:22, Rusty Russell <rusty at rustcorp.com.au> wrote:
>> Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
>>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>>> ---
>>>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
>>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> OK, I applied this to the lyx master, with three changes:
>> 1) Changed "filed" to "field".
>> 2) Added ", or even acknowledging the feature" after "without
>>    initializing virtio queues".
>> 3) Added an initial point to the Device Initialization section:
>>
>>    1. If the VIRTIO_CONSOLE_F_EMERG_WRITE feature is offered, the
>>    emerg_wr field of the configuration can be written at any time. Thus
>>    it should work for very early boot debugging output as well as
>>    catastophic OS failures (eg. virtio ring corruption).
> 
> Thanks for applying this patch.
> Have you also applied first patch ([PATCH V2 1/3] virtio: console: Add
> emergency writeonly register to config space)
> with this?  (https://lkml.org/lkml/2013/5/6/169)

You seem to have omitted copying virtualization at lists.linux-foundation.org,
the mailing list documented in the MAINTAINERS file as appropriate for changes
relating to the virtio console driver.

[...]

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From sebastian.hesselbarth at gmail.com  Mon May 13 13:37:23 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 13 May 2013 19:37:23 +0200
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
Message-ID: <519124D3.2040403@gmail.com>

On 05/13/13 19:24, S?ren Brinkmann wrote:
> On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
>>> Well, that driver actually exists. But that just programs a bitstream
>>> you give it to program. It does not know anything about the design it
>>> programs and cannot make any kind of decision whether the clocks should
>>> be userspace controlled or not.
>>
>> what Mark wants to point out is that you add fabric clocks to the Xilinx
>> driver instead. This way, you will have user-space controllable clocks
>> but only if you loaded the xilinx driver first.
> What "Xilinx driver", are we talking about?

The device config driver you mention below.

>> IIRC the fabric clock controller provided by Zynq _is_ always there and
>> accessible from ARM CPUs. You just don't have a new generic driver
>> allowing to poke with all clocks, but a xilinx only driver allowing you
>> to set the (xilinx only) fabric clocks.
> Right.
>
>> I've played with Zynq a while ago, did Xilinx mainline the bitfile
>> driver already? If not, why don't you give it a shot?
> The device config driver is not in mainline, AFAIK. And I think it's in
> rather bad shape and needs a lot of work before it is upstreamable. But
> this is probably the right place to put this.

It is, as it will only expose clocks on Zynq and that's what Mark and
Mike are worried about. Expose clocks to user space and you will have
people mess with it for sure.

About the shape of it, I didn't expect that to change at all. Just
wondering, if it still requires you to manually end it's endianess
mess with the bitfiles. If you go at it, consider reading the magic
hidden in the bitfile and swap it when it is required. But that will
go OT here.

> On the other hand, currently this driver is only required for
> programming the FPGA from Linux, which is not required. One of the
> bootloaders could do this for you earlier.

Well, exposing clocks to user space is not required _at all_ on all
other platforms you can think of. So, if you have a Zynq, you can
always load a Zynq driver even if you are not going to use it's
bitfile programming capabilities but only to configure clocks.

If you don't want to merge both drivers, have a Zynq-only clock
fabric driver instead?

Sebastian


From soren.brinkmann at xilinx.com  Mon May 13 13:46:34 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Mon, 13 May 2013 10:46:34 -0700
Subject: [PATCH v2 0/5] Zynq: revised CCF code
Message-ID: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>

I rebased this series on v3.10-rc1 eliminating all dependencies and incorporated
Greg's feedback.
I'll push this also to my github repository.
https://github.com/sorenb-xlnx/linux-xlnx/tree/zynq/clkc

v2:
 - dropped the 'sort #includes' patches

	S?ren


Soren Brinkmann (5):
  tty: xuartps: Remove suspend/resume functions
  clk: zynq: Factor out PLL driver
  clk: zynq: Add clock controller driver
  arm: zynq: Migrate platform to clock controller
  clk: zynq: Remove deprecated clock code

 .../devicetree/bindings/clock/zynq-7000.txt        | 127 +++--
 arch/arm/boot/dts/zynq-7000.dtsi                   |  71 +--
 arch/arm/boot/dts/zynq-zc702.dts                   |   4 -
 arch/arm/mach-zynq/slcr.c                          |   2 +-
 drivers/clk/Makefile                               |   2 +-
 drivers/clk/clk-zynq.c                             | 378 ---------------
 drivers/clk/zynq/Makefile                          |   3 +
 drivers/clk/zynq/clkc.c                            | 533 +++++++++++++++++++++
 drivers/clk/zynq/pll.c                             | 235 +++++++++
 drivers/clocksource/cadence_ttc_timer.c            |  23 +-
 drivers/tty/serial/xilinx_uartps.c                 | 115 +++--
 include/linux/clk/zynq.h                           |   8 +-
 12 files changed, 974 insertions(+), 527 deletions(-)
 delete mode 100644 drivers/clk/clk-zynq.c
 create mode 100644 drivers/clk/zynq/Makefile
 create mode 100644 drivers/clk/zynq/clkc.c
 create mode 100644 drivers/clk/zynq/pll.c

-- 
1.8.2.3



From soren.brinkmann at xilinx.com  Mon May 13 13:46:35 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Mon, 13 May 2013 10:46:35 -0700
Subject: [PATCH v2 1/5] tty: xuartps: Remove suspend/resume functions
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <1368467199-8702-2-git-send-email-soren.brinkmann@xilinx.com>

Currently Zynq does not support suspend/resume.
The driver callbacks are never used or tested, broken and using the old
PM interface.

Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Jiri Slaby <jslaby at suse.cz>
Cc: linux-serial at vger.kernel.org
---
 drivers/tty/serial/xilinx_uartps.c | 30 ------------------------------
 1 file changed, 30 deletions(-)

diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index 4e5c778..b5f655d 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -1006,34 +1006,6 @@ static int xuartps_remove(struct platform_device *pdev)
 	return rc;
 }
 
-/**
- * xuartps_suspend - suspend event
- * @pdev: Pointer to the platform device structure
- * @state: State of the device
- *
- * Returns 0
- **/
-static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	/* Call the API provided in serial_core.c file which handles
-	 * the suspend.
-	 */
-	uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
-	return 0;
-}
-
-/**
- * xuartps_resume - Resume after a previous suspend
- * @pdev: Pointer to the platform device structure
- *
- * Returns 0
- **/
-static int xuartps_resume(struct platform_device *pdev)
-{
-	uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
-	return 0;
-}
-
 /* Match table for of_platform binding */
 static struct of_device_id xuartps_of_match[] = {
 	{ .compatible = "xlnx,xuartps", },
@@ -1044,8 +1016,6 @@ MODULE_DEVICE_TABLE(of, xuartps_of_match);
 static struct platform_driver xuartps_platform_driver = {
 	.probe   = xuartps_probe,		/* Probe method */
 	.remove  = xuartps_remove,		/* Detach method */
-	.suspend = xuartps_suspend,		/* Suspend */
-	.resume  = xuartps_resume,		/* Resume after a suspend */
 	.driver  = {
 		.owner = THIS_MODULE,
 		.name = XUARTPS_NAME,		/* Driver name */
-- 
1.8.2.3



From soren.brinkmann at xilinx.com  Mon May 13 13:46:36 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Mon, 13 May 2013 10:46:36 -0700
Subject: [PATCH v2 2/5] clk: zynq: Factor out PLL driver
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <1368467199-8702-3-git-send-email-soren.brinkmann@xilinx.com>

Refactor the PLL driver so it works with the clock controller driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
---
 drivers/clk/zynq/pll.c | 235 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 235 insertions(+)
 create mode 100644 drivers/clk/zynq/pll.c

diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
new file mode 100644
index 0000000..47e307c
--- /dev/null
+++ b/drivers/clk/zynq/pll.c
@@ -0,0 +1,235 @@
+/*
+ * Zynq PLL driver
+ *
+ *  Copyright (C) 2013 Xilinx
+ *
+ *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+/**
+ * struct zynq_pll
+ * @hw:		Handle between common and hardware-specific interfaces
+ * @pll_ctrl:	PLL control register
+ * @pll_status:	PLL status register
+ * @lock:	Register lock
+ * @lockbit:	Indicates the associated PLL_LOCKED bit in the PLL status
+ *		register.
+ */
+struct zynq_pll {
+	struct clk_hw	hw;
+	void __iomem	*pll_ctrl;
+	void __iomem	*pll_status;
+	spinlock_t	*lock;
+	u8		lockbit;
+};
+#define to_zynq_pll(_hw)	container_of(_hw, struct zynq_pll, hw)
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK	0x7f000
+#define PLLCTRL_FBDIV_SHIFT	12
+#define PLLCTRL_BPQUAL_MASK	(1 << 3)
+#define PLLCTRL_PWRDWN_MASK	2
+#define PLLCTRL_PWRDWN_SHIFT	1
+#define PLLCTRL_RESET_MASK	1
+#define PLLCTRL_RESET_SHIFT	0
+
+/**
+ * zynq_pll_round_rate() - Round a clock frequency
+ * @hw:		Handle between common and hardware-specific interfaces
+ * @rate:	Desired clock frequency
+ * @prate:	Clock frequency of parent clock
+ * Returns frequency closest to @rate the hardware can generate.
+ */
+static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long *prate)
+{
+	u32 fbdiv;
+
+	fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
+	if (fbdiv < 13)
+		fbdiv = 13;
+	else if (fbdiv > 66)
+		fbdiv = 66;
+
+	return *prate * fbdiv;
+}
+
+/**
+ * zynq_pll_recalc_rate() - Recalculate clock frequency
+ * @hw:			Handle between common and hardware-specific interfaces
+ * @parent_rate:	Clock frequency of parent clock
+ * Returns current clock frequency.
+ */
+static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct zynq_pll *clk = to_zynq_pll(hw);
+	u32 fbdiv;
+
+	/*
+	 * makes probably sense to redundantly save fbdiv in the struct
+	 * zynq_pll to save the IO access.
+	 */
+	fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+			PLLCTRL_FBDIV_SHIFT;
+
+	return parent_rate * fbdiv;
+}
+
+/**
+ * zynq_pll_is_enabled - Check if a clock is enabled
+ * @hw:		Handle between common and hardware-specific interfaces
+ * Returns 1 if the clock is enabled, 0 otherwise.
+ *
+ * Not sure this is a good idea, but since disabled means bypassed for
+ * this clock implementation we say we are always enabled.
+ */
+static int zynq_pll_is_enabled(struct clk_hw *hw)
+{
+	unsigned long flags = 0;
+	u32 reg;
+	struct zynq_pll *clk = to_zynq_pll(hw);
+
+	spin_lock_irqsave(clk->lock, flags);
+
+	reg = readl(clk->pll_ctrl);
+
+	spin_unlock_irqrestore(clk->lock, flags);
+
+	return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
+}
+
+/**
+ * zynq_pll_enable - Enable clock
+ * @hw:		Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static int zynq_pll_enable(struct clk_hw *hw)
+{
+	unsigned long flags = 0;
+	u32 reg;
+	struct zynq_pll *clk = to_zynq_pll(hw);
+
+	if (zynq_pll_is_enabled(hw))
+		return 0;
+
+	pr_info("PLL: enable\n");
+
+	/* Power up PLL and wait for lock */
+	spin_lock_irqsave(clk->lock, flags);
+
+	reg = readl(clk->pll_ctrl);
+	reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
+	writel(reg, clk->pll_ctrl);
+	while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
+		;
+
+	spin_unlock_irqrestore(clk->lock, flags);
+
+	return 0;
+}
+
+/**
+ * zynq_pll_disable - Disable clock
+ * @hw:		Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static void zynq_pll_disable(struct clk_hw *hw)
+{
+	unsigned long flags = 0;
+	u32 reg;
+	struct zynq_pll *clk = to_zynq_pll(hw);
+
+	if (!zynq_pll_is_enabled(hw))
+		return;
+
+	pr_info("PLL: shutdown\n");
+
+	/* shut down PLL */
+	spin_lock_irqsave(clk->lock, flags);
+
+	reg = readl(clk->pll_ctrl);
+	reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
+	writel(reg, clk->pll_ctrl);
+
+	spin_unlock_irqrestore(clk->lock, flags);
+}
+
+static const struct clk_ops zynq_pll_ops = {
+	.enable = zynq_pll_enable,
+	.disable = zynq_pll_disable,
+	.is_enabled = zynq_pll_is_enabled,
+	.round_rate = zynq_pll_round_rate,
+	.recalc_rate = zynq_pll_recalc_rate
+};
+
+/**
+ * clk_register_zynq_pll() - Register PLL with the clock framework
+ * @np	Pointer to the DT device node
+ */
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+		void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+		spinlock_t *lock)
+{
+	struct zynq_pll *pll;
+	struct clk *clk;
+	u32 reg;
+	const char *parent_arr[1] = {parent};
+	unsigned long flags = 0;
+	struct clk_init_data initd = {
+		.name = name,
+		.parent_names = parent_arr,
+		.ops = &zynq_pll_ops,
+		.num_parents = 1,
+		.flags = 0
+	};
+
+	pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll) {
+		pr_err("%s: Could not allocate Zynq PLL clk.\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* Populate the struct */
+	pll->hw.init = &initd;
+	pll->pll_ctrl = pll_ctrl;
+	pll->pll_status = pll_status;
+	pll->lockbit = lock_index;
+	pll->lock = lock;
+
+	spin_lock_irqsave(pll->lock, flags);
+
+	reg = readl(pll->pll_ctrl);
+	reg &= ~PLLCTRL_BPQUAL_MASK;
+	writel(reg, pll->pll_ctrl);
+
+	spin_unlock_irqrestore(pll->lock, flags);
+
+	clk = clk_register(NULL, &pll->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		goto free_pll;
+
+	return clk;
+
+free_pll:
+	kfree(pll);
+
+	return clk;
+}
-- 
1.8.2.3



From soren.brinkmann at xilinx.com  Mon May 13 13:46:38 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Mon, 13 May 2013 10:46:38 -0700
Subject: [PATCH v2 4/5] arm: zynq: Migrate platform to clock controller
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <1368467199-8702-5-git-send-email-soren.brinkmann@xilinx.com>

Migrate the Zynq platform and its drivers to use the new clock
controller driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
Cc: John Stultz <john.stultz at linaro.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Jiri Slaby <jslaby at suse.cz>
Cc: linux-serial at vger.kernel.org
---
 arch/arm/boot/dts/zynq-7000.dtsi        | 71 ++++++++-------------------
 arch/arm/boot/dts/zynq-zc702.dts        |  4 --
 arch/arm/mach-zynq/slcr.c               |  2 +-
 drivers/clk/Makefile                    |  2 +-
 drivers/clk/zynq/Makefile               |  3 ++
 drivers/clocksource/cadence_ttc_timer.c | 23 +++++++--
 drivers/tty/serial/xilinx_uartps.c      | 85 ++++++++++++++++++++++++++-------
 include/linux/clk/zynq.h                |  8 +++-
 8 files changed, 118 insertions(+), 80 deletions(-)
 create mode 100644 drivers/clk/zynq/Makefile

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 14fb2e6..0dbee2c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -49,16 +49,18 @@
 
 		uart0: uart at e0000000 {
 			compatible = "xlnx,xuartps";
+			clocks = <&clkc 23>, <&clkc 40>;
+			clock-names = "ref_clk", "aper_clk";
 			reg = <0xE0000000 0x1000>;
 			interrupts = <0 27 4>;
-			clocks = <&uart_clk 0>;
 		};
 
 		uart1: uart at e0001000 {
 			compatible = "xlnx,xuartps";
+			clocks = <&clkc 24>, <&clkc 41>;
+			clock-names = "ref_clk", "aper_clk";
 			reg = <0xE0001000 0x1000>;
 			interrupts = <0 50 4>;
-			clocks = <&uart_clk 1>;
 		};
 
 		slcr: slcr at f8000000 {
@@ -69,50 +71,21 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				ps_clk: ps_clk {
-					#clock-cells = <0>;
-					compatible = "fixed-clock";
-					/* clock-frequency set in board-specific file */
-					clock-output-names = "ps_clk";
-				};
-				armpll: armpll {
-					#clock-cells = <0>;
-					compatible = "xlnx,zynq-pll";
-					clocks = <&ps_clk>;
-					reg = <0x100 0x110>;
-					clock-output-names = "armpll";
-				};
-				ddrpll: ddrpll {
-					#clock-cells = <0>;
-					compatible = "xlnx,zynq-pll";
-					clocks = <&ps_clk>;
-					reg = <0x104 0x114>;
-					clock-output-names = "ddrpll";
-				};
-				iopll: iopll {
-					#clock-cells = <0>;
-					compatible = "xlnx,zynq-pll";
-					clocks = <&ps_clk>;
-					reg = <0x108 0x118>;
-					clock-output-names = "iopll";
-				};
-				uart_clk: uart_clk {
-					#clock-cells = <1>;
-					compatible = "xlnx,zynq-periph-clock";
-					clocks = <&iopll &armpll &ddrpll>;
-					reg = <0x154>;
-					clock-output-names = "uart0_ref_clk",
-							     "uart1_ref_clk";
-				};
-				cpu_clk: cpu_clk {
+				clkc: clkc {
 					#clock-cells = <1>;
-					compatible = "xlnx,zynq-cpu-clock";
-					clocks = <&iopll &armpll &ddrpll>;
-					reg = <0x120 0x1C4>;
-					clock-output-names = "cpu_6x4x",
-							     "cpu_3x2x",
-							     "cpu_2x",
-							     "cpu_1x";
+					compatible = "xlnx,ps7-clkc";
+					ps-clk-frequency = <33333333>;
+					clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+							"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+							"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+							"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+							"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+							"dma", "usb0_aper", "usb1_aper", "gem0_aper",
+							"gem1_aper", "sdio0_aper", "sdio1_aper",
+							"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+							"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+							"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+							"dbg_trc", "dbg_apb";
 				};
 			};
 		};
@@ -121,9 +94,8 @@
 			interrupt-parent = <&intc>;
 			interrupts = < 0 10 4 0 11 4 0 12 4 >;
 			compatible = "cdns,ttc";
+			clocks = <&clkc 6>;
 			reg = <0xF8001000 0x1000>;
-			clocks = <&cpu_clk 3>;
-			clock-names = "cpu_1x";
 			clock-ranges;
 		};
 
@@ -131,9 +103,8 @@
 			interrupt-parent = <&intc>;
 			interrupts = < 0 37 4 0 38 4 0 39 4 >;
 			compatible = "cdns,ttc";
+			clocks = <&clkc 6>;
 			reg = <0xF8002000 0x1000>;
-			clocks = <&cpu_clk 3>;
-			clock-names = "cpu_1x";
 			clock-ranges;
 		};
 		scutimer: scutimer at f8f00600 {
@@ -141,7 +112,7 @@
 			interrupts = < 1 13 0x301 >;
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = < 0xf8f00600 0x20 >;
-			clocks = <&cpu_clk 1>;
+			clocks = <&clkc 4>;
 		} ;
 	};
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 86f44d5..e25a307 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -28,7 +28,3 @@
 	};
 
 };
-
-&ps_clk {
-	clock-frequency = <33333330>;
-};
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c70969b..50d008d 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -117,7 +117,7 @@ int __init zynq_slcr_init(void)
 
 	pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 
-	xilinx_zynq_clocks_init(zynq_slcr_base);
+	zynq_clock_init(zynq_slcr_base);
 
 	of_node_put(np);
 
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..fa435bc 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 obj-$(CONFIG_ARCH_SUNXI)	+= sunxi/
 obj-$(CONFIG_ARCH_U8500)	+= ux500/
 obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
-obj-$(CONFIG_ARCH_ZYNQ)		+= clk-zynq.o
+obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
 
diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile
new file mode 100644
index 0000000..156d923
--- /dev/null
+++ b/drivers/clk/zynq/Makefile
@@ -0,0 +1,3 @@
+# Zynq clock specific Makefile
+
+obj-$(CONFIG_ARCH_ZYNQ)	+= clkc.o pll.o
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 685bc60..4cbe28c 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -51,6 +51,8 @@
 
 #define TTC_CNT_CNTRL_DISABLE_MASK	0x1
 
+#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
+
 /*
  * Setup the timers to use pre-scaling, using a fixed value for now that will
  * work across most input frequency, but it may need to be more dynamic
@@ -396,8 +398,9 @@ static void __init ttc_timer_init(struct device_node *timer)
 {
 	unsigned int irq;
 	void __iomem *timer_baseaddr;
-	struct clk *clk;
+	struct clk *clk_cs, *clk_ce;
 	static int initialized;
+	int clksel;
 
 	if (initialized)
 		return;
@@ -421,14 +424,24 @@ static void __init ttc_timer_init(struct device_node *timer)
 		BUG();
 	}
 
-	clk = of_clk_get_by_name(timer, "cpu_1x");
-	if (IS_ERR(clk)) {
+	clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
+	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+	clk_cs = of_clk_get(timer, clksel);
+	if (IS_ERR(clk_cs)) {
+		pr_err("ERROR: timer input clock not found\n");
+		BUG();
+	}
+
+	clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
+	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+	clk_ce = of_clk_get(timer, clksel);
+	if (IS_ERR(clk_ce)) {
 		pr_err("ERROR: timer input clock not found\n");
 		BUG();
 	}
 
-	ttc_setup_clocksource(clk, timer_baseaddr);
-	ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
+	ttc_setup_clocksource(clk_cs, timer_baseaddr);
+	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 
 	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
 }
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index b5f655d..916305a 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/slab.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/console.h>
@@ -139,6 +140,16 @@
 #define XUARTPS_SR_RXTRIG	0x00000001 /* Rx Trigger */
 
 /**
+ * struct xuartps - device data
+ * @refclk	Reference clock
+ * @aperclk	APB clock
+ */
+struct xuartps {
+	struct clk		*refclk;
+	struct clk		*aperclk;
+};
+
+/**
  * xuartps_isr - Interrupt handler
  * @irq: Irq number
  * @dev_id: Id of the port
@@ -936,34 +947,55 @@ static int xuartps_probe(struct platform_device *pdev)
 	int rc;
 	struct uart_port *port;
 	struct resource *res, *res2;
-	struct clk *clk;
+	struct xuartps *xuartps_data;
 
-	clk = of_clk_get(pdev->dev.of_node, 0);
-	if (IS_ERR(clk)) {
-		dev_err(&pdev->dev, "no clock specified\n");
-		return PTR_ERR(clk);
+	xuartps_data = kzalloc(sizeof(*xuartps_data), GFP_KERNEL);
+	if (!xuartps_data)
+		return -ENOMEM;
+
+	xuartps_data->aperclk = clk_get(&pdev->dev, "aper_clk");
+	if (IS_ERR(xuartps_data->aperclk)) {
+		dev_err(&pdev->dev, "aper_clk clock not found.\n");
+		rc = PTR_ERR(xuartps_data->aperclk);
+		goto err_out_free;
+	}
+	xuartps_data->refclk = clk_get(&pdev->dev, "ref_clk");
+	if (IS_ERR(xuartps_data->refclk)) {
+		dev_err(&pdev->dev, "ref_clk clock not found.\n");
+		rc = PTR_ERR(xuartps_data->refclk);
+		goto err_out_clk_put_aper;
 	}
 
-	rc = clk_prepare_enable(clk);
+	rc = clk_prepare_enable(xuartps_data->aperclk);
+	if (rc) {
+		dev_err(&pdev->dev, "Unable to enable APER clock.\n");
+		goto err_out_clk_put;
+	}
+	rc = clk_prepare_enable(xuartps_data->refclk);
 	if (rc) {
-		dev_err(&pdev->dev, "could not enable clock\n");
-		return -EBUSY;
+		dev_err(&pdev->dev, "Unable to enable device clock.\n");
+		goto err_out_clk_dis_aper;
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -ENODEV;
+	if (!res) {
+		rc = -ENODEV;
+		goto err_out_clk_disable;
+	}
 
 	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!res2)
-		return -ENODEV;
+	if (!res2) {
+		rc = -ENODEV;
+		goto err_out_clk_disable;
+	}
 
 	/* Initialize the port structure */
 	port = xuartps_get_port();
 
 	if (!port) {
 		dev_err(&pdev->dev, "Cannot get uart_port structure\n");
-		return -ENODEV;
+		rc = -ENODEV;
+		goto err_out_clk_disable;
 	} else {
 		/* Register the port.
 		 * This function also registers this device with the tty layer
@@ -972,18 +1004,31 @@ static int xuartps_probe(struct platform_device *pdev)
 		port->mapbase = res->start;
 		port->irq = res2->start;
 		port->dev = &pdev->dev;
-		port->uartclk = clk_get_rate(clk);
-		port->private_data = clk;
+		port->uartclk = clk_get_rate(xuartps_data->refclk);
+		port->private_data = xuartps_data;
 		dev_set_drvdata(&pdev->dev, port);
 		rc = uart_add_one_port(&xuartps_uart_driver, port);
 		if (rc) {
 			dev_err(&pdev->dev,
 				"uart_add_one_port() failed; err=%i\n", rc);
 			dev_set_drvdata(&pdev->dev, NULL);
-			return rc;
+			goto err_out_clk_disable;
 		}
 		return 0;
 	}
+
+err_out_clk_disable:
+	clk_disable_unprepare(xuartps_data->refclk);
+err_out_clk_dis_aper:
+	clk_disable_unprepare(xuartps_data->aperclk);
+err_out_clk_put:
+	clk_put(xuartps_data->refclk);
+err_out_clk_put_aper:
+	clk_put(xuartps_data->aperclk);
+err_out_free:
+	kfree(xuartps_data);
+
+	return rc;
 }
 
 /**
@@ -995,14 +1040,18 @@ static int xuartps_probe(struct platform_device *pdev)
 static int xuartps_remove(struct platform_device *pdev)
 {
 	struct uart_port *port = dev_get_drvdata(&pdev->dev);
-	struct clk *clk = port->private_data;
+	struct xuartps *xuartps_data = port->private_data;
 	int rc;
 
 	/* Remove the xuartps port from the serial core */
 	rc = uart_remove_one_port(&xuartps_uart_driver, port);
 	dev_set_drvdata(&pdev->dev, NULL);
 	port->mapbase = 0;
-	clk_disable_unprepare(clk);
+	clk_disable_unprepare(xuartps_data->refclk);
+	clk_disable_unprepare(xuartps_data->aperclk);
+	clk_put(xuartps_data->refclk);
+	clk_put(xuartps_data->aperclk);
+	kfree(xuartps_data);
 	return rc;
 }
 
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index 56be7cd..e062d31 100644
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2013 Xilinx Inc.
  * Copyright (C) 2012 National Instruments
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,6 +20,11 @@
 #ifndef __LINUX_CLK_ZYNQ_H_
 #define __LINUX_CLK_ZYNQ_H_
 
-void __init xilinx_zynq_clocks_init(void __iomem *slcr);
+#include <linux/spinlock.h>
 
+void zynq_clock_init(void __iomem *slcr);
+
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+		void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+		spinlock_t *lock);
 #endif
-- 
1.8.2.3



From soren.brinkmann at xilinx.com  Mon May 13 13:46:37 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Mon, 13 May 2013 10:46:37 -0700
Subject: [PATCH v2 3/5] clk: zynq: Add clock controller driver
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <1368467199-8702-4-git-send-email-soren.brinkmann@xilinx.com>

Add a clock controller driver and documentation.

Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
---
 .../devicetree/bindings/clock/zynq-7000.txt        |  98 ++++
 drivers/clk/zynq/clkc.c                            | 533 +++++++++++++++++++++
 2 files changed, 631 insertions(+)
 create mode 100644 drivers/clk/zynq/clkc.c

diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 23ae1db..30bfca9 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -6,6 +6,104 @@ The purpose of this document is to document their usage.
 See clock_bindings.txt for more information on the generic clock bindings.
 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
 
+== Clock Controller ==
+The clock controller is a logical abstration of Zynq's clock tree. It reads
+required input clock frequencies from the devictree and acts as clock provider
+for all clock consumers of PS clocks.
+
+Required properties:
+ - #clock-cells : Must be 1
+ - compatible : "xlnx,ps7-clkc"
+ - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
+		      (usually 33 MHz oscillators are used for Zynq platforms)
+ - clock-output-names : List of strings used to name the clock outputs. Shall be
+			a list of the outputs given below.
+
+Optional properties:
+ - clocks : as described in the clock bindings
+ - clock-names : as described in the clock bindings
+
+Clock inputs:
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source.
+ - swdt_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - mio_clk_XX		# with XX = 00..53
+...
+
+Clock outputs:
+ 0:  armpll
+ 1:  ddrpll
+ 2:  iopll
+ 3:  cpu_6or4x
+ 4:  cpu_3or2x
+ 5:  cpu_2x
+ 6:  cpu_1x
+ 7:  ddr2x
+ 8:  ddr3x
+ 9:  dci
+ 10: lqspi
+ 11: smc
+ 12: pcap
+ 13: gem0
+ 14: gem1
+ 15: fclk0
+ 16: fclk1
+ 17: fclk2
+ 18: fclk3
+ 19: can0
+ 20: can1
+ 21: sdio0
+ 22: sdio1
+ 23: uart0
+ 24: uart1
+ 25: spi0
+ 26: spi1
+ 27: dma
+ 28: usb0_aper
+ 29: usb1_aper
+ 30: gem0_aper
+ 31: gem1_aper
+ 32: sdio0_aper
+ 33: sdio1_aper
+ 34: spi0_aper
+ 35: spi1_aper
+ 36: can0_aper
+ 37: can1_aper
+ 38: i2c0_aper
+ 39: i2c1_aper
+ 40: uart0_aper
+ 41: uart1_aper
+ 42: gpio_aper
+ 43: lqspi_aper
+ 44: smc_aper
+ 45: swdt
+ 46: dbg_trc
+ 47: dbg_apb
+
+Example:
+	clkc: clkc {
+                #clock-cells = <1>;
+                compatible = "xlnx,ps7-clkc";
+                ps-clk-frequency = <33333333>;
+		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+				"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+				"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+				"dma", "usb0_aper", "usb1_aper", "gem0_aper",
+				"gem1_aper", "sdio0_aper", "sdio1_aper",
+				"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+				"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+				"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+				"dbg_trc", "dbg_apb";
+                # optional props
+		clocks = <&clkc 16>, <&clk_foo>;
+		clock-names = "gem1_emio_clk", "can_mio_clk_23";
+        };
+
+
 == PLLs ==
 
 Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
new file mode 100644
index 0000000..5c205b6
--- /dev/null
+++ b/drivers/clk/zynq/clkc.c
@@ -0,0 +1,533 @@
+/*
+ * Zynq clock controller
+ *
+ *  Copyright (C) 2012 - 2013 Xilinx
+ *
+ *  S?ren Brinkmann <soren.brinkmann at xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/io.h>
+
+static void __iomem *zynq_slcr_base_priv;
+
+#define SLCR_ARMPLL_CTRL		(zynq_slcr_base_priv + 0x100)
+#define SLCR_DDRPLL_CTRL		(zynq_slcr_base_priv + 0x104)
+#define SLCR_IOPLL_CTRL			(zynq_slcr_base_priv + 0x108)
+#define SLCR_PLL_STATUS			(zynq_slcr_base_priv + 0x10c)
+#define SLCR_ARM_CLK_CTRL		(zynq_slcr_base_priv + 0x120)
+#define SLCR_DDR_CLK_CTRL		(zynq_slcr_base_priv + 0x124)
+#define SLCR_DCI_CLK_CTRL		(zynq_slcr_base_priv + 0x128)
+#define SLCR_APER_CLK_CTRL		(zynq_slcr_base_priv + 0x12c)
+#define SLCR_GEM0_CLK_CTRL		(zynq_slcr_base_priv + 0x140)
+#define SLCR_GEM1_CLK_CTRL		(zynq_slcr_base_priv + 0x144)
+#define SLCR_SMC_CLK_CTRL		(zynq_slcr_base_priv + 0x148)
+#define SLCR_LQSPI_CLK_CTRL		(zynq_slcr_base_priv + 0x14c)
+#define SLCR_SDIO_CLK_CTRL		(zynq_slcr_base_priv + 0x150)
+#define SLCR_UART_CLK_CTRL		(zynq_slcr_base_priv + 0x154)
+#define SLCR_SPI_CLK_CTRL		(zynq_slcr_base_priv + 0x158)
+#define SLCR_CAN_CLK_CTRL		(zynq_slcr_base_priv + 0x15c)
+#define SLCR_CAN_MIOCLK_CTRL		(zynq_slcr_base_priv + 0x160)
+#define SLCR_DBG_CLK_CTRL		(zynq_slcr_base_priv + 0x164)
+#define SLCR_PCAP_CLK_CTRL		(zynq_slcr_base_priv + 0x168)
+#define SLCR_FPGA0_CLK_CTRL		(zynq_slcr_base_priv + 0x170)
+#define SLCR_621_TRUE			(zynq_slcr_base_priv + 0x1c4)
+#define SLCR_SWDT_CLK_SEL		(zynq_slcr_base_priv + 0x304)
+
+#define NUM_MIO_PINS	54
+
+enum zynq_clk {
+	armpll, ddrpll, iopll,
+	cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
+	ddr2x, ddr3x, dci,
+	lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
+	sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
+	usb0_aper, usb1_aper, gem0_aper, gem1_aper,
+	sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
+	i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
+	smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
+
+static struct clk *ps_clk;
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
+
+static DEFINE_SPINLOCK(armpll_lock);
+static DEFINE_SPINLOCK(ddrpll_lock);
+static DEFINE_SPINLOCK(iopll_lock);
+static DEFINE_SPINLOCK(armclk_lock);
+static DEFINE_SPINLOCK(ddrclk_lock);
+static DEFINE_SPINLOCK(dciclk_lock);
+static DEFINE_SPINLOCK(gem0clk_lock);
+static DEFINE_SPINLOCK(gem1clk_lock);
+static DEFINE_SPINLOCK(canclk_lock);
+static DEFINE_SPINLOCK(canmioclk_lock);
+static DEFINE_SPINLOCK(dbgclk_lock);
+static DEFINE_SPINLOCK(aperclk_lock);
+
+static const char dummy_nm[] __initconst = "dummy_name";
+
+static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
+static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
+static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
+static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
+static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
+static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
+	"can0_mio_mux"};
+static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
+	"can1_mio_mux"};
+static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
+	dummy_nm};
+
+static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
+static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
+static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
+static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
+
+static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
+		const char *clk_name, void __iomem *fclk_ctrl_reg,
+		const char **parents)
+{
+	struct clk *clk;
+	char *mux_name;
+	char *div0_name;
+	char *div1_name;
+	spinlock_t *fclk_lock;
+	spinlock_t *fclk_gate_lock;
+	void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
+
+	fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
+	if (!fclk_lock)
+		goto err;
+	fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
+	if (!fclk_gate_lock)
+		goto err;
+	spin_lock_init(fclk_lock);
+	spin_lock_init(fclk_gate_lock);
+
+	mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
+	div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
+	div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
+
+	clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+			fclk_ctrl_reg, 4, 2, 0, fclk_lock);
+
+	clk = clk_register_divider(NULL, div0_name, mux_name,
+			0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
+
+	clk = clk_register_divider(NULL, div1_name, div0_name,
+			CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
+			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+			fclk_lock);
+
+	clks[fclk] = clk_register_gate(NULL, clk_name,
+			div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
+			0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
+	kfree(mux_name);
+	kfree(div0_name);
+	kfree(div1_name);
+
+	return;
+
+err:
+	clks[fclk] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
+		enum zynq_clk clk1, const char *clk_name0,
+		const char *clk_name1, void __iomem *clk_ctrl,
+		const char **parents, unsigned int two_gates)
+{
+	struct clk *clk;
+	char *mux_name;
+	char *div_name;
+	spinlock_t *lock;
+
+	lock = kmalloc(sizeof(*lock), GFP_KERNEL);
+	if (!lock)
+		goto err;
+	spin_lock_init(lock);
+
+	mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
+	div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
+
+	clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+			clk_ctrl, 4, 2, 0, lock);
+
+	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
+			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
+
+	clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
+			CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
+	if (two_gates)
+		clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
+				CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
+
+	kfree(mux_name);
+	kfree(div_name);
+
+	return;
+
+err:
+	clks[clk0] = ERR_PTR(-ENOMEM);
+	if (two_gates)
+		clks[clk1] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_setup(struct device_node *np)
+{
+	int i;
+	u32 tmp;
+	int ret;
+	struct clk *clk;
+	char *clk_name;
+	const char *clk_output_name[clk_max];
+	const char *cpu_parents[4];
+	const char *periph_parents[4];
+	const char *swdt_ext_clk_mux_parents[2];
+	const char *can_mio_mux_parents[NUM_MIO_PINS];
+
+	pr_info("Zynq clock init\n");
+
+	/* get clock output names from DT */
+	for (i = 0; i < clk_max; i++) {
+		if (of_property_read_string_index(np, "clock-output-names",
+				  i, &clk_output_name[i])) {
+			pr_err("%s: clock output name not in DT\n", __func__);
+			BUG();
+		}
+	}
+	cpu_parents[0] = clk_output_name[armpll];
+	cpu_parents[1] = clk_output_name[armpll];
+	cpu_parents[2] = clk_output_name[ddrpll];
+	cpu_parents[3] = clk_output_name[iopll];
+	periph_parents[0] = clk_output_name[iopll];
+	periph_parents[1] = clk_output_name[iopll];
+	periph_parents[2] = clk_output_name[armpll];
+	periph_parents[3] = clk_output_name[ddrpll];
+
+	/* ps_clk */
+	ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
+	if (ret) {
+		pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
+		tmp = 33333333;
+	}
+	ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
+			tmp);
+
+	/* PLLs */
+	clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
+			SLCR_PLL_STATUS, 0, &armpll_lock);
+	clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
+			armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0,
+			&armpll_lock);
+
+	clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
+			SLCR_PLL_STATUS, 1, &ddrpll_lock);
+	clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
+			ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0,
+			&ddrpll_lock);
+
+	clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
+			SLCR_PLL_STATUS, 2, &iopll_lock);
+	clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
+			iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0,
+			&iopll_lock);
+
+	/* CPU clocks */
+	tmp = readl(SLCR_621_TRUE) & 1;
+	clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0,
+			SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock);
+	clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
+			SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
+
+	clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
+			"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
+
+	clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
+			1, 2);
+	clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
+			"cpu_3or2x_div", CLK_IGNORE_UNUSED,
+			SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
+
+	clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
+			2 + tmp);
+	clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
+			"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
+			26, 0, &armclk_lock);
+
+	clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
+			4 + 2 * tmp);
+	clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
+			"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
+			0, &armclk_lock);
+
+	/* Timers */
+	swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
+	for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
+		int idx = of_property_match_string(np, "clock-names",
+				swdt_ext_clk_input_names[i]);
+		if (idx >= 0)
+			swdt_ext_clk_mux_parents[i + 1] =
+				of_clk_get_parent_name(np, idx);
+		else
+			swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
+	}
+	clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
+			swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
+			SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
+
+	/* DDR clocks */
+	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
+			SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+	clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
+			"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
+	clk_prepare_enable(clks[ddr2x]);
+	clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
+			SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+	clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
+			"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
+	clk_prepare_enable(clks[ddr3x]);
+
+	clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
+			SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
+	clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
+			CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
+			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+			&dciclk_lock);
+	clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
+			CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
+			&dciclk_lock);
+	clk_prepare_enable(clks[dci]);
+
+	/* Peripheral clocks */
+	for (i = fclk0; i <= fclk3; i++)
+		zynq_clk_register_fclk(i, clk_output_name[i],
+				SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
+				periph_parents);
+
+	zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
+			SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+
+	zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
+			SLCR_SMC_CLK_CTRL, periph_parents, 0);
+
+	zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
+			SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+
+	zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
+			clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
+			periph_parents, 1);
+
+	zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
+			clk_output_name[uart1], SLCR_UART_CLK_CTRL,
+			periph_parents, 1);
+
+	zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
+			clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
+			periph_parents, 1);
+
+	for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
+		int idx = of_property_match_string(np, "clock-names",
+				gem0_emio_input_names[i]);
+		if (idx >= 0)
+			gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
+					idx);
+	}
+	clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0,
+			SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock);
+	clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
+			SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
+	clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
+			CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
+			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+			&gem0clk_lock);
+	clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
+			SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
+	clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
+			"gem0_emio_mux", CLK_SET_RATE_PARENT,
+			SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
+
+	for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
+		int idx = of_property_match_string(np, "clock-names",
+				gem1_emio_input_names[i]);
+		if (idx >= 0)
+			gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
+					idx);
+	}
+	clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0,
+			SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock);
+	clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
+			SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
+	clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
+			CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
+			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+			&gem1clk_lock);
+	clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
+			SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
+	clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
+			"gem1_emio_mux", CLK_SET_RATE_PARENT,
+			SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
+
+	tmp = strlen("mio_clk_00x");
+	clk_name = kmalloc(tmp, GFP_KERNEL);
+	for (i = 0; i < NUM_MIO_PINS; i++) {
+		int idx;
+
+		snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
+		idx = of_property_match_string(np, "clock-names", clk_name);
+		if (idx >= 0)
+			can_mio_mux_parents[i] = of_clk_get_parent_name(np,
+						idx);
+		else
+			can_mio_mux_parents[i] = dummy_nm;
+	}
+	kfree(clk_name);
+	clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0,
+			SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock);
+	clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
+			SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
+	clk = clk_register_divider(NULL, "can_div1", "can_div0",
+			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
+			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+			&canclk_lock);
+	clk = clk_register_gate(NULL, "can0_gate", "can_div1",
+			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
+			&canclk_lock);
+	clk = clk_register_gate(NULL, "can1_gate", "can_div1",
+			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
+			&canclk_lock);
+	clk = clk_register_mux(NULL, "can0_mio_mux",
+			can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+			SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock);
+	clk = clk_register_mux(NULL, "can1_mio_mux",
+			can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+			SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock);
+	clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
+			can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+			SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock);
+	clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
+			can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+			SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock);
+
+	for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
+		int idx = of_property_match_string(np, "clock-names",
+				dbgtrc_emio_input_names[i]);
+		if (idx >= 0)
+			dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
+					idx);
+	}
+	clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0,
+			SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock);
+	clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
+			SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+			CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
+	clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0,
+			SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock);
+	clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
+			"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
+			0, 0, &dbgclk_lock);
+	clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
+			clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
+			&dbgclk_lock);
+
+	/* One gated clock for all APER clocks. */
+	clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
+			clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
+			&aperclk_lock);
+	clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
+			&aperclk_lock);
+	clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
+			&aperclk_lock);
+	clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
+			&aperclk_lock);
+	clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
+			&aperclk_lock);
+	clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
+			&aperclk_lock);
+	clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
+			&aperclk_lock);
+	clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
+			&aperclk_lock);
+	clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
+			&aperclk_lock);
+	clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
+			&aperclk_lock);
+	clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
+			&aperclk_lock);
+	clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
+			&aperclk_lock);
+	clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
+			&aperclk_lock);
+	clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
+			&aperclk_lock);
+	clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
+			&aperclk_lock);
+	clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
+			&aperclk_lock);
+	clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
+			&aperclk_lock);
+	clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
+			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
+			&aperclk_lock);
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		if (IS_ERR(clks[i])) {
+			pr_err("Zynq clk %d: register failed with %ld\n",
+			       i, PTR_ERR(clks[i]));
+			BUG();
+		}
+	}
+
+	clk_data.clks = clks;
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
+
+void __init zynq_clock_init(void __iomem *slcr_base)
+{
+	zynq_slcr_base_priv = slcr_base;
+	of_clk_init(NULL);
+}
-- 
1.8.2.3



From soren.brinkmann at xilinx.com  Mon May 13 13:46:39 2013
From: soren.brinkmann at xilinx.com (Soren Brinkmann)
Date: Mon, 13 May 2013 10:46:39 -0700
Subject: [PATCH v2 5/5] clk: zynq: Remove deprecated clock code
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <1368467199-8702-6-git-send-email-soren.brinkmann@xilinx.com>

Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
---
 .../devicetree/bindings/clock/zynq-7000.txt        |  49 ---
 drivers/clk/clk-zynq.c                             | 378 ---------------------
 2 files changed, 427 deletions(-)
 delete mode 100644 drivers/clk/clk-zynq.c

diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 30bfca9..b013ec6 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -102,52 +102,3 @@ Example:
 		clocks = <&clkc 16>, <&clk_foo>;
 		clock-names = "gem1_emio_clk", "can_mio_clk_23";
         };
-
-
-== PLLs ==
-
-Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
-
-Required properties:
-- #clock-cells : shall be 0 (only one clock is output from this node)
-- compatible : "xlnx,zynq-pll"
-- reg : pair of u32 values, which are the address offsets within the SLCR
-        of the relevant PLL_CTRL register and PLL_CFG register respectively
-- clocks : phandle for parent clock.  should be the phandle for ps_clk
-
-Optional properties:
-- clock-output-names : name of the output clock
-
-Example:
-	armpll: armpll {
-		#clock-cells = <0>;
-		compatible = "xlnx,zynq-pll";
-		clocks = <&ps_clk>;
-		reg = <0x100 0x110>;
-		clock-output-names = "armpll";
-	};
-
-== Peripheral clocks ==
-
-Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
-
-Required properties:
-- #clock-cells : shall be 1
-- compatible : "xlnx,zynq-periph-clock"
-- reg : a single u32 value, describing the offset within the SLCR where
-        the CLK_CTRL register is found for this peripheral
-- clocks : phandle for parent clocks.  should hold phandles for
-           the IO_PLL, ARM_PLL, and DDR_PLL in order
-- clock-output-names : names of the output clock(s).  For peripherals that have
-                       two output clocks (for example, the UART), two clocks
-                       should be listed.
-
-Example:
-	uart_clk: uart_clk {
-		#clock-cells = <1>;
-		compatible = "xlnx,zynq-periph-clock";
-		clocks = <&iopll &armpll &ddrpll>;
-		reg = <0x154>;
-		clock-output-names = "uart0_ref_clk",
-				     "uart1_ref_clk";
-	};
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
deleted file mode 100644
index 3206297..0000000
--- a/drivers/clk/clk-zynq.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) 2012 National Instruments
- *
- * Josh Cartwright <josh.cartwright at ni.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/zynq.h>
-
-static void __iomem *slcr_base;
-
-struct zynq_pll_clk {
-	struct clk_hw	hw;
-	void __iomem	*pll_ctrl;
-	void __iomem	*pll_cfg;
-};
-
-#define to_zynq_pll_clk(hw)	container_of(hw, struct zynq_pll_clk, hw)
-
-#define CTRL_PLL_FDIV(x)	((x) >> 12)
-
-static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
-					  unsigned long parent_rate)
-{
-	struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
-	return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
-}
-
-static const struct clk_ops zynq_pll_clk_ops = {
-	.recalc_rate	= zynq_pll_recalc_rate,
-};
-
-static void __init zynq_pll_clk_setup(struct device_node *np)
-{
-	struct clk_init_data init;
-	struct zynq_pll_clk *pll;
-	const char *parent_name;
-	struct clk *clk;
-	u32 regs[2];
-	int ret;
-
-	ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
-	if (WARN_ON(ret))
-		return;
-
-	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-	if (WARN_ON(!pll))
-		return;
-
-	pll->pll_ctrl = slcr_base + regs[0];
-	pll->pll_cfg  = slcr_base + regs[1];
-
-	of_property_read_string(np, "clock-output-names", &init.name);
-
-	init.ops = &zynq_pll_clk_ops;
-	parent_name = of_clk_get_parent_name(np, 0);
-	init.parent_names = &parent_name;
-	init.num_parents = 1;
-
-	pll->hw.init = &init;
-
-	clk = clk_register(NULL, &pll->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return;
-
-	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-	if (WARN_ON(ret))
-		return;
-}
-CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
-
-struct zynq_periph_clk {
-	struct clk_hw		hw;
-	struct clk_onecell_data	onecell_data;
-	struct clk		*gates[2];
-	void __iomem		*clk_ctrl;
-	spinlock_t		clkact_lock;
-};
-
-#define to_zynq_periph_clk(hw)	container_of(hw, struct zynq_periph_clk, hw)
-
-static const u8 periph_clk_parent_map[] = {
-	0, 0, 1, 2
-};
-#define PERIPH_CLK_CTRL_SRC(x)	(periph_clk_parent_map[((x) & 0x30) >> 4])
-#define PERIPH_CLK_CTRL_DIV(x)	(((x) & 0x3F00) >> 8)
-
-static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
-					     unsigned long parent_rate)
-{
-	struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
-	return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
-}
-
-static u8 zynq_periph_get_parent(struct clk_hw *hw)
-{
-	struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
-	return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
-}
-
-static const struct clk_ops zynq_periph_clk_ops = {
-	.recalc_rate	= zynq_periph_recalc_rate,
-	.get_parent	= zynq_periph_get_parent,
-};
-
-static void __init zynq_periph_clk_setup(struct device_node *np)
-{
-	struct zynq_periph_clk *periph;
-	const char *parent_names[3];
-	struct clk_init_data init;
-	int clk_num = 0, err;
-	const char *name;
-	struct clk *clk;
-	u32 reg;
-	int i;
-
-	err = of_property_read_u32(np, "reg", &reg);
-	if (WARN_ON(err))
-		return;
-
-	periph = kzalloc(sizeof(*periph), GFP_KERNEL);
-	if (WARN_ON(!periph))
-		return;
-
-	periph->clk_ctrl = slcr_base + reg;
-	spin_lock_init(&periph->clkact_lock);
-
-	init.name = np->name;
-	init.ops = &zynq_periph_clk_ops;
-	for (i = 0; i < ARRAY_SIZE(parent_names); i++)
-		parent_names[i] = of_clk_get_parent_name(np, i);
-	init.parent_names = parent_names;
-	init.num_parents = ARRAY_SIZE(parent_names);
-
-	periph->hw.init = &init;
-
-	clk = clk_register(NULL, &periph->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return;
-
-	err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-	if (WARN_ON(err))
-		return;
-
-	err = of_property_read_string_index(np, "clock-output-names", 0,
-					    &name);
-	if (WARN_ON(err))
-		return;
-
-	periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
-					     periph->clk_ctrl, 0, 0,
-					     &periph->clkact_lock);
-	if (WARN_ON(IS_ERR(periph->gates[0])))
-		return;
-	clk_num++;
-
-	/* some periph clks have 2 downstream gates */
-	err = of_property_read_string_index(np, "clock-output-names", 1,
-					    &name);
-	if (err != -ENODATA) {
-		periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
-						     periph->clk_ctrl, 1, 0,
-						     &periph->clkact_lock);
-		if (WARN_ON(IS_ERR(periph->gates[1])))
-			return;
-		clk_num++;
-	}
-
-	periph->onecell_data.clks = periph->gates;
-	periph->onecell_data.clk_num = clk_num;
-
-	err = of_clk_add_provider(np, of_clk_src_onecell_get,
-				  &periph->onecell_data);
-	if (WARN_ON(err))
-		return;
-}
-CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
-
-/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
- * derivative rates depend on CLK_621_TRUE
- */
-
-struct zynq_cpu_clk {
-	struct clk_hw		hw;
-	struct clk_onecell_data	onecell_data;
-	struct clk		*subclks[4];
-	void __iomem		*clk_ctrl;
-	spinlock_t		clkact_lock;
-};
-
-#define to_zynq_cpu_clk(hw)	container_of(hw, struct zynq_cpu_clk, hw)
-
-static const u8 zynq_cpu_clk_parent_map[] = {
-	1, 1, 2, 0
-};
-#define CPU_CLK_SRCSEL(x)	(zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
-#define CPU_CLK_CTRL_DIV(x)	(((x) & 0x3F00) >> 8)
-
-static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
-{
-	struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
-	return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
-}
-
-static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
-					      unsigned long parent_rate)
-{
-	struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
-	return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
-}
-
-static const struct clk_ops zynq_cpu_clk_ops = {
-	.get_parent	= zynq_cpu_clk_get_parent,
-	.recalc_rate	= zynq_cpu_clk_recalc_rate,
-};
-
-struct zynq_cpu_subclk {
-	struct clk_hw	hw;
-	void __iomem	*clk_621;
-	enum {
-		CPU_SUBCLK_6X4X,
-		CPU_SUBCLK_3X2X,
-		CPU_SUBCLK_2X,
-		CPU_SUBCLK_1X,
-	} which;
-};
-
-#define CLK_621_TRUE(x)	((x) & 1)
-
-#define to_zynq_cpu_subclk(hw)	container_of(hw, struct zynq_cpu_subclk, hw);
-
-static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
-						 unsigned long parent_rate)
-{
-	unsigned long uninitialized_var(rate);
-	struct zynq_cpu_subclk *subclk;
-	bool is_621;
-
-	subclk = to_zynq_cpu_subclk(hw)
-	is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
-
-	switch (subclk->which) {
-	case CPU_SUBCLK_6X4X:
-		rate = parent_rate;
-		break;
-	case CPU_SUBCLK_3X2X:
-		rate = parent_rate / 2;
-		break;
-	case CPU_SUBCLK_2X:
-		rate = parent_rate / (is_621 ? 3 : 2);
-		break;
-	case CPU_SUBCLK_1X:
-		rate = parent_rate / (is_621 ? 6 : 4);
-		break;
-	};
-
-	return rate;
-}
-
-static const struct clk_ops zynq_cpu_subclk_ops = {
-	.recalc_rate	= zynq_cpu_subclk_recalc_rate,
-};
-
-static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
-					 void __iomem *clk_621)
-{
-	struct zynq_cpu_subclk *subclk;
-	struct clk_init_data init;
-	struct clk *clk;
-	int err;
-
-	err = of_property_read_string_index(np, "clock-output-names",
-					    which, &init.name);
-	if (WARN_ON(err))
-		goto err_read_output_name;
-
-	subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
-	if (!subclk)
-		goto err_subclk_alloc;
-
-	subclk->clk_621 = clk_621;
-	subclk->which = which;
-
-	init.ops = &zynq_cpu_subclk_ops;
-	init.parent_names = &np->name;
-	init.num_parents = 1;
-
-	subclk->hw.init = &init;
-
-	clk = clk_register(NULL, &subclk->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		goto err_clk_register;
-
-	return clk;
-
-err_clk_register:
-	kfree(subclk);
-err_subclk_alloc:
-err_read_output_name:
-	return ERR_PTR(-EINVAL);
-}
-
-static void __init zynq_cpu_clk_setup(struct device_node *np)
-{
-	struct zynq_cpu_clk *cpuclk;
-	const char *parent_names[3];
-	struct clk_init_data init;
-	void __iomem *clk_621;
-	struct clk *clk;
-	u32 reg[2];
-	int err;
-	int i;
-
-	err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
-	if (WARN_ON(err))
-		return;
-
-	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
-	if (WARN_ON(!cpuclk))
-		return;
-
-	cpuclk->clk_ctrl = slcr_base + reg[0];
-	clk_621 = slcr_base + reg[1];
-	spin_lock_init(&cpuclk->clkact_lock);
-
-	init.name = np->name;
-	init.ops = &zynq_cpu_clk_ops;
-	for (i = 0; i < ARRAY_SIZE(parent_names); i++)
-		parent_names[i] = of_clk_get_parent_name(np, i);
-	init.parent_names = parent_names;
-	init.num_parents = ARRAY_SIZE(parent_names);
-
-	cpuclk->hw.init = &init;
-
-	clk = clk_register(NULL, &cpuclk->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return;
-
-	err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-	if (WARN_ON(err))
-		return;
-
-	for (i = 0; i < 4; i++) {
-		cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
-		if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
-			return;
-	}
-
-	cpuclk->onecell_data.clks = cpuclk->subclks;
-	cpuclk->onecell_data.clk_num = i;
-
-	err = of_clk_add_provider(np, of_clk_src_onecell_get,
-				  &cpuclk->onecell_data);
-	if (WARN_ON(err))
-		return;
-}
-CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
-
-void __init xilinx_zynq_clocks_init(void __iomem *slcr)
-{
-	slcr_base = slcr;
-	of_clk_init(NULL);
-}
-- 
1.8.2.3



From linus.walleij at linaro.org  Mon May 13 13:48:48 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 May 2013 19:48:48 +0200
Subject: [PATCH 1/3] mmc: mmci: Use optional sleep pinctrl state
In-Reply-To: <1368452837-31458-2-git-send-email-ulf.hansson@stericsson.com>
References: <1368452837-31458-1-git-send-email-ulf.hansson@stericsson.com>
 <1368452837-31458-2-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdarH5FbegyN17n+--hoCgHqzEupUA0pjkXG3juCA9aW5w@mail.gmail.com>

On Mon, May 13, 2013 at 3:47 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> By optionally putting the pins into sleep state in the .runtime_suspend
> callback we can accomplish two things. One is to minimize current leakage
> from pins and thus save power, second we can prevent the IP from driving
> pins output in an uncontrolled manner, which may happen if the power domain
> drops the domain regulator.
>
> When returning from idle, entering .runtime_resume callback, the pins
> are restored to default state.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Looks straight-forward from a pinctrl point of view.
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From john.tobias.ph at gmail.com  Mon May 13 13:56:47 2013
From: john.tobias.ph at gmail.com (John Tobias)
Date: Mon, 13 May 2013 10:56:47 -0700
Subject: Marvel 8797 Wifi module using SDIO 3.0
Message-ID: <CACUGKYN+OGWOsd7kk68i-mj0QdykWjLJ8Hmmi4XWx8kPnbJx7g@mail.gmail.com>

Hi All,

I have a Wifi module based on 8797 Marvell chipset and it using SDIO
3.0. I am using iMX6 SD board and linux kernel 3.9 stable released
(https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/).
The 8797 module support the 4bit mode and the problem right now, the
SDHCI controller and the said module couldn't communicate to each
other (if using 4bit mode). But, If I force to use the 1bit mode, both
of them can communicate correctly. Also, I force the SDHCI to use ADMA
or SDMA, but there's no effect output.

I would like to know if anyone here solved the problem or an idea how
to deal with it?.

Regards,

John


From robdclark at gmail.com  Mon May 13 13:58:10 2013
From: robdclark at gmail.com (Rob Clark)
Date: Mon, 13 May 2013 13:58:10 -0400
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
Message-ID: <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>

On Mon, May 13, 2013 at 1:18 PM, Inki Dae <inki.dae at samsung.com> wrote:
>
>
> 2013/5/13 Rob Clark <robdclark at gmail.com>
>>
>> On Mon, May 13, 2013 at 8:21 AM, Inki Dae <inki.dae at samsung.com> wrote:
>> >
>> >> In that case you still wouldn't give userspace control over the fences.
>> >> I
>> >> don't see any way that can end well.
>> >> What if userspace never signals? What if userspace gets killed by oom
>> >> killer. Who keeps track of that?
>> >>
>> >
>> > In all cases, all kernel resources to user fence will be released by
>> > kernel
>> > once the fence is timed out: never signaling and process killing by oom
>> > killer makes the fence timed out. And if we use mmap mechanism you
>> > mentioned
>> > before, I think user resource could also be freed properly.
>>
>>
>> I tend to agree w/ Maarten here.. there is no good reason for
>> userspace to be *signaling* fences.  The exception might be some blob
>> gpu drivers which don't have enough knowledge in the kernel to figure
>> out what to do.  (In which case you can add driver private ioctls for
>> that.. still not the right thing to do but at least you don't make a
>> public API out of it.)
>>
>
> Please do not care whether those are generic or not. Let's see the following
> three things. First, it's cache operation. As you know, ARM SoC has ACP
> (Accelerator Coherency Port) and can be connected to DMA engine or similar
> devices. And this port is used for cache coherency between CPU cache and DMA
> device. However, most devices on ARM based embedded systems don't use the
> ACP port. So they need proper cache operation before and after of DMA or CPU
> access in case of using cachable mapping. Actually, I see many Linux based
> platforms call cache control interfaces directly for that. I think the
> reason, they do so, is that kernel isn't aware of when and how CPU accessed
> memory.

I think we had kicked around the idea of giving dmabuf's a
prepare/finish ioctl quite some time back.  This is probably something
that should be at least a bit decoupled from fences.  (Possibly
'prepare' waits for dma access to complete, but not the other way
around.)

And I did implement in omapdrm support for simulating coherency via
page fault-in / shoot-down..  It is one option that makes it
completely transparent to userspace, although there is some
performance const, so I suppose it depends a bit on your use-case.

> And second, user process has to do so many things in case of using shared
> memory with DMA device. User process should understand how DMA device is
> operated and when interfaces for controling the DMA device are called. Such
> things would make user application so complicated.
>
> And third, it's performance optimization to multimedia and graphics devices.
> As I mentioned already, we should consider sequential processing for buffer
> sharing between CPU and DMA device. This means that CPU should stay with
> idle until DMA device is completed and vise versa.
>
> That is why I proposed such user interfaces. Of course, these interfaces
> might be so ugly yet: for this, Maarten pointed already out and I agree with
> him. But there must be another better way. Aren't you think we need similar
> thing? With such interfaces, cache control and buffer synchronization can be
> performed in kernel level. Moreover, user applization doesn't need to
> consider DMA device controlling anymore. Therefore, one thread can access a
> shared buffer and the other can control DMA device with the shared buffer in
> parallel. We can really make the best use of CPU and DMA idle time. In other
> words, we can really make the best use of multi tasking OS, Linux.
>
> So could you please tell me about that there is any reason we don't use
> public API for it? I think we can add and use public API if NECESSARY.

well, for cache management, I think it is a better idea.. I didn't
really catch that this was the motivation from the initial patch, but
maybe I read it too quickly.  But cache can be decoupled from
synchronization, because CPU access is not asynchronous.  For
userspace/CPU access to buffer, you should:

  1) wait for buffer
  2) prepare-access
  3)  ... do whatever cpu access to buffer ...
  4) finish-access
  5) submit buffer for new dma-operation

I suppose you could combine the syscall for #1 and #2.. not sure if
that is a good idea or not.  But you don't need to.  And there is
never really any need for userspace to signal a fence.

BR,
-R

> Thanks,
> Inki Dae
>
>>
>> BR,
>> -R
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>


From soren.brinkmann at xilinx.com  Mon May 13 13:58:49 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Mon, 13 May 2013 10:58:49 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <519124D3.2040403@gmail.com>
References: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
Message-ID: <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>

On Mon, May 13, 2013 at 07:37:23PM +0200, Sebastian Hesselbarth wrote:
> On 05/13/13 19:24, S?ren Brinkmann wrote:
> >On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
> >>>Well, that driver actually exists. But that just programs a bitstream
> >>>you give it to program. It does not know anything about the design it
> >>>programs and cannot make any kind of decision whether the clocks should
> >>>be userspace controlled or not.
> >>
> >>what Mark wants to point out is that you add fabric clocks to the Xilinx
> >>driver instead. This way, you will have user-space controllable clocks
> >>but only if you loaded the xilinx driver first.
> >What "Xilinx driver", are we talking about?
> 
> The device config driver you mention below.
> 
> >>IIRC the fabric clock controller provided by Zynq _is_ always there and
> >>accessible from ARM CPUs. You just don't have a new generic driver
> >>allowing to poke with all clocks, but a xilinx only driver allowing you
> >>to set the (xilinx only) fabric clocks.
> >Right.
> >
> >>I've played with Zynq a while ago, did Xilinx mainline the bitfile
> >>driver already? If not, why don't you give it a shot?
> >The device config driver is not in mainline, AFAIK. And I think it's in
> >rather bad shape and needs a lot of work before it is upstreamable. But
> >this is probably the right place to put this.
> 
> It is, as it will only expose clocks on Zynq and that's what Mark and
> Mike are worried about. Expose clocks to user space and you will have
> people mess with it for sure.
Well, even if you contain it in that driver you can still mess with
other clocks. Just give it the "wrong" input clock references in DT and
you are free to control them. As I said before, there is no protection
against such misuse.

> 
> About the shape of it, I didn't expect that to change at all. Just
> wondering, if it still requires you to manually end it's endianess
> mess with the bitfiles. If you go at it, consider reading the magic
> hidden in the bitfile and swap it when it is required. But that will
> go OT here.
It still takes byteswapped, binary images as input, unfortunately.

> 
> >On the other hand, currently this driver is only required for
> >programming the FPGA from Linux, which is not required. One of the
> >bootloaders could do this for you earlier.
> 
> Well, exposing clocks to user space is not required _at all_ on all
> other platforms you can think of. So, if you have a Zynq, you can
> always load a Zynq driver even if you are not going to use it's
> bitfile programming capabilities but only to configure clocks.
> 
> If you don't want to merge both drivers, have a Zynq-only clock
> fabric driver instead?
That was my original intention. But due to the nature of it, it will
always be possible to use it with other clocks too. Hence my generic
approach.
I actually like the idea of making it part of the device config driver.
The downside of it is, that this driver seems a bit far from mainline.

	S?ren




From broonie at kernel.org  Mon May 13 14:16:25 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 13 May 2013 22:16:25 +0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <519112F9.2010102@gmail.com>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
Message-ID: <20130513181625.GB14811@sirena.org.uk>

On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
> On 05/13/13 18:09, S?ren Brinkmann wrote:

> >Well, that driver actually exists. But that just programs a bitstream
> >you give it to program. It does not know anything about the design it
> >programs and cannot make any kind of decision whether the clocks should
> >be userspace controlled or not.

> what Mark wants to point out is that you add fabric clocks to the Xilinx
> driver instead. This way, you will have user-space controllable clocks
> but only if you loaded the xilinx driver first.

Yup, that's part of it.  Though I have to say that if all we can do is
stuff a bitstream in there there is the question about how anything that
does require a real driver gets that driver instantiated...
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From sebastian.hesselbarth at gmail.com  Mon May 13 14:18:07 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 13 May 2013 20:18:07 +0200
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
References: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
Message-ID: <51912E5F.9090401@gmail.com>

On 05/13/13 19:58, S?ren Brinkmann wrote:
> On Mon, May 13, 2013 at 07:37:23PM +0200, Sebastian Hesselbarth wrote:
>> It is, as it will only expose clocks on Zynq and that's what Mark and
>> Mike are worried about. Expose clocks to user space and you will have
>> people mess with it for sure.
> Well, even if you contain it in that driver you can still mess with
> other clocks. Just give it the "wrong" input clock references in DT and
> you are free to control them. As I said before, there is no protection
> against such misuse.

Put the wrong clock in DT is not "misuse" but "bug" ;) More important,
it is quite static as you cannot change it easily by echo'ing into some
sysfs file. And to inject a DT you need access on boot loader level,
not kernel user space (yet).

>> About the shape of it, I didn't expect that to change at all. Just
>> wondering, if it still requires you to manually end it's endianess
>> mess with the bitfiles. If you go at it, consider reading the magic
>> hidden in the bitfile and swap it when it is required. But that will
>> go OT here.
> It still takes byteswapped, binary images as input, unfortunately.

Please, if you ever mainline any kernel driver for it, make it
auto-swap.

>> If you don't want to merge both drivers, have a Zynq-only clock
>> fabric driver instead?
> That was my original intention. But due to the nature of it, it will
> always be possible to use it with other clocks too. Hence my generic
> approach.

I already tried a generic "expose clocks to user space" and failed for
the very same reasons Mike and Mark are repeating over and over again -
and I agree with them.

> I actually like the idea of making it part of the device config driver.
> The downside of it is, that this driver seems a bit far from mainline.

Have a skeleton driver that exposes Zynq clocks first and implement
device config later? IIRC, device config isn't that complicated to
implement. Unfortunately, interpreting Xilinx datasheets or source code
is.

Sebastian


From sebastian.hesselbarth at gmail.com  Mon May 13 14:20:18 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 13 May 2013 20:20:18 +0200
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130513181625.GB14811@sirena.org.uk>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com> <20130513181625.GB14811@sirena.org.uk>
Message-ID: <51912EE2.6040909@gmail.com>

On 05/13/13 20:16, Mark Brown wrote:
> On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
>> what Mark wants to point out is that you add fabric clocks to the Xilinx
>> driver instead. This way, you will have user-space controllable clocks
>> but only if you loaded the xilinx driver first.
>
> Yup, that's part of it.  Though I have to say that if all we can do is
> stuff a bitstream in there there is the question about how anything that
> does require a real driver gets that driver instantiated...

Back when I played with Zynq, I remember looking at CONFIG_DYNAMIC_OF
discussions. ;)

Sebastian


From davidb at codeaurora.org  Mon May 13 14:26:49 2013
From: davidb at codeaurora.org (David Brown)
Date: Mon, 13 May 2013 11:26:49 -0700
Subject: [PATCH 08/14] ARM: msm: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-9-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-9-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130513182648.GA26913@codeaurora.org>

On Mon, May 13, 2013 at 11:44:07AM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for msm as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-msm/board-dt-8660.c | 1 -
>  arch/arm/mach-msm/board-dt-8960.c | 1 -
>  2 files changed, 2 deletions(-)

I'll pull this into my msm-cleanup tree.

David

-- 
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From broonie at kernel.org  Mon May 13 14:44:43 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 13 May 2013 22:44:43 +0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <51912EE2.6040909@gmail.com>
References: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <20130510212422.GY3200@sirena.org.uk>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com> <20130513181625.GB14811@sirena.org.uk>
 <51912EE2.6040909@gmail.com>
Message-ID: <20130513184443.GC14811@sirena.org.uk>

On Mon, May 13, 2013 at 08:20:18PM +0200, Sebastian Hesselbarth wrote:
> On 05/13/13 20:16, Mark Brown wrote:

> >Yup, that's part of it.  Though I have to say that if all we can do is
> >stuff a bitstream in there there is the question about how anything that
> >does require a real driver gets that driver instantiated...

> Back when I played with Zynq, I remember looking at CONFIG_DYNAMIC_OF
> discussions. ;)

Which then goes back to the whole idea of this being a device - and
possibly that this should be done as part of representing UIO in DT
rather than anything else.
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From linus.walleij at linaro.org  Mon May 13 15:05:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 May 2013 21:05:00 +0200
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>

On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
<srinivas.kandagatla at st.com> wrote:

Thomas Gleixner and John Stultz should always be included on timer code review.

This is one reason I really like to move the clocksource/clockevent/etc code out
of arch/arm, so that people can get their To: line right from MAINTAINERS.
(Whether it goes to drivers/clocksource or not is another issue.)

> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h

Using CLKSRC_OF_INIT() this header goes away entirely I guess.

> diff --git a/arch/arm/kernel/global_timer.c b/arch/arm/kernel/global_timer.c

> +#define GT_COUNTER0    0x00
> +#define GT_COUNTER1    0x04

So two counters, nice.

> +union gt_counter {
> +       cycle_t cycles;
> +       struct {
> +               uint32_t lower;
> +               uint32_t upper;

Just u32 is fine.

> +       };
> +};
> +
> +static union gt_counter gt_counter_read(void)
> +{
> +       union gt_counter res;
> +       uint32_t upper;

u32

> +
> +       upper = readl(gt_base + GT_COUNTER1);
> +       do {
> +               res.upper = upper;
> +               res.lower = readl(gt_base + GT_COUNTER0);
> +               upper = readl(gt_base + GT_COUNTER1);
> +       } while (upper != res.upper);
> +
> +       return res;
> +}

I guess this is some cleverness to avoid wrap-around...
A comment stating what's going on wouldn't hurt.

But why on earth do you need this complicated union
to hold the result? Have two local u32 variables and return
a u64 from this function.

Since this will be performance critical, isn't readl_relaxed() suffient
here, or what's the rationale for just using readl()?

> +static void gt_compare_set(unsigned long delta, int periodic)
> +{
> +       union gt_counter counter = gt_counter_read();

So here you get something easy to read like

u64 counter = gt_counter_read();

> +       unsigned long ctrl = readl(gt_base + GT_CONTROL);
> +
> +       BUG_ON(!(ctrl & GT_CONTROL_TIMER_ENABLE));
> +       BUG_ON(ctrl & (GT_CONTROL_COMP_ENABLE |
> +                      GT_CONTROL_IRQ_ENABLE |
> +                      GT_CONTROL_AUTO_INC));

Do you really have to check this *whenever the counter is set*?

Will it not suffice to do this once during initialization?

It looks like some leftover debug code. It also looks kind of clock
dangerous, can you explain exactly why this check is here?

> +
> +       counter.cycles += delta;
> +       writel(counter.lower, gt_base + GT_COMP0);
> +       writel(counter.upper, gt_base + GT_COMP1);

This is another instance of the union struct making things
complicated. With a u64 just:

counter += delta;
writel(lower_32_bits(counter), gt_base + GT_COMP0);
writel(upper_32_bits(counter), gt_base + GT_COMP1);

As you can see <linux/kernel.h> has really nice helpers in place
to deal with 64 bit arithmetics.

> +
> +       ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
> +
> +       if (periodic) {
> +               writel(delta, gt_base + GT_AUTO_INC);
> +               ctrl |= GT_CONTROL_AUTO_INC;
> +       }
> +
> +       writel(ctrl, gt_base + GT_CONTROL);
> +}
> +
> +static void gt_clockevent_set_mode(enum clock_event_mode mode,
> +                                  struct clock_event_device *clk)
> +{
> +       switch (mode) {
> +       case CLOCK_EVT_MODE_PERIODIC:
> +               gt_compare_set(gt_clk_rate/HZ, 1);

Use
gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
to get integer arithmetics right.

> +               break;
> +       case CLOCK_EVT_MODE_ONESHOT:
> +               /* period set, and timer enabled in 'next_event' hook */
> +               BUG_ON(readl(gt_base + GT_CONTROL) &
> +                      (GT_CONTROL_COMP_ENABLE |
> +                       GT_CONTROL_IRQ_ENABLE |
> +                       GT_CONTROL_AUTO_INC));

Here is another one of these checks. Why aren't you just
zeroing these flags if you don't want them, especially since
you're writing the register at the end of the function? Now it
looks like instead of setting up the timer the way you want it
you bug out if it isn't already set up as you want it (hint,
the name of this function).

> +               /* Fall through */
> +       case CLOCK_EVT_MODE_UNUSED:
> +       case CLOCK_EVT_MODE_SHUTDOWN:
> +       default:
> +               writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);

Why are you enabling the timer in unused and shutdown mode?

This doesn't make sense.

> +               break;
> +       }
> +}
> +
> +static int gt_clockevent_set_next_event(unsigned long evt,
> +                                       struct clock_event_device *unused)
> +{
> +       gt_compare_set(evt, 0);
> +       return 0;
> +}
> +
> +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
> +{
> +       struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
> +
> +       writel(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);

You're clearing the flag before checking if it was set. What happens
if this was a spurious interrupt that should be disregarded?

> +       evt->event_handler(evt);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
> +{
> +       struct clock_event_device **this_cpu_clk;
> +       int cpu = smp_processor_id();
> +
> +       clk->name = "Global Timer CE";

Name it after the hardware feature. "ARM global timer clock event"
there is no need to abbreviate randomly.

> +       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
> +       clk->set_mode = gt_clockevent_set_mode;
> +       clk->set_next_event = gt_clockevent_set_next_event;
> +       this_cpu_clk = __this_cpu_ptr(gt_evt);
> +       *this_cpu_clk = clk;
> +       clk->irq = gt_ppi;
> +       clockevents_config_and_register(clk, gt_clk_rate,
> +                                       0xf, 0xffffffff);

Why can't this clock event handle anything lower than 0xf?
Does that come from the datasheet or have you just copied some
code?

Further, since this clock event hardware *most definately* supports
using a delta upper bound *beyond* 32 bits, I think the clock event
core code should be altered to allow for registereing such clock
events, but TGLX may have some idea here. This will work but will
not expose the full potential of this 64-bit counter hardware.

> +       per_cpu(percpu_init_called, cpu) = true;
> +       enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
> +       return 0;
> +}
> +
> +static void gt_clockevents_stop(struct clock_event_device *clk)
> +{
> +       gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
> +       disable_percpu_irq(clk->irq);
> +}
> +
> +static int __cpuinit gt_clockevents_setup(struct clock_event_device *clk)
> +{
> +       int cpu = smp_processor_id();
> +
> +       /* Use existing clock_event for boot cpu */
> +       if (per_cpu(percpu_init_called, cpu))
> +               return 0;
> +
> +       writel(0, gt_base + GT_CONTROL);
> +       writel(0, gt_base + GT_COUNTER0);
> +       writel(0, gt_base + GT_COUNTER1);
> +       writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
> +
> +       return gt_clockevents_init(clk);
> +}
> +
> +static cycle_t gt_clocksource_read(struct clocksource *cs)
> +{
> +       union gt_counter res = gt_counter_read();
> +       return res.cycles;
> +}
> +
> +static struct clocksource gt_clocksource = {
> +       .name   = "Global Timer CS",

"ARM global timer clock source"

> +       .rating = 300,
> +       .read   = gt_clocksource_read,
> +       .mask   = CLOCKSOURCE_MASK(64),
> +       .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void __init gt_clocksource_init(void)
> +{
> +       writel(0, gt_base + GT_CONTROL);
> +       writel(0, gt_base + GT_COUNTER0);
> +       writel(0, gt_base + GT_COUNTER1);
> +       writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
> +
> +       gt_clocksource.shift = 20;

So how did you come up with that?

> +       gt_clocksource.mult =
> +               clocksource_hz2mult(gt_clk_rate, gt_clocksource.shift);
> +       clocksource_register(&gt_clocksource);

Why don't you just replace all of this hazzle with:

clocksource_register_hz(&gt_clocksource, gt_clk_rate);

That will calculate mult and shift for you? (Leave these
unassigned.)

Since the hpet timer does this it's pretty well tested...

No more comments right now...

Yours,
Linus Walleij


From loic.pallardy at st.com  Mon May 13 15:09:06 2013
From: loic.pallardy at st.com (Loic PALLARDY)
Date: Mon, 13 May 2013 21:09:06 +0200
Subject: [PATCHv2 2/4] mailbox: Introduce a new common API
In-Reply-To: <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
References: <1367824946-6160-1-git-send-email-jaswinder.singh@linaro.org>
 <1367825046-6229-1-git-send-email-jaswinder.singh@linaro.org>
Message-ID: <51913A52.1040106@st.com>

Hi Jassi,

Back at work :)
Where can I find last version of framework which integrates all
modifications discussed during the 3 last weeks?

I would like to review and work on last code version.

Regards,
Loic

On 05/06/2013 09:24 AM, Jassi Brar wrote:
> Introduce common framework for client/protocol drivers and
> controller drivers of Inter-Processor-Communication (IPC).
>
> Client driver developers should have a look at
>   include/linux/mailbox_client.h to understand the part of
> the API exposed to client drivers.
> Similarly controller driver developers should have a look
> at include/linux/mailbox_controller.h
>
> Signed-off-by: Jassi Brar<jaswinder.singh at linaro.org>
> ---
>   drivers/mailbox/Makefile           |    4 +
>   drivers/mailbox/mailbox.c          |  494 ++++++++++++++++++++++++++++++++++++
>   include/linux/mailbox.h            |   17 ++
>   include/linux/mailbox_client.h     |   85 +++++++
>   include/linux/mailbox_controller.h |  102 ++++++++
>   5 files changed, 702 insertions(+)
>   create mode 100644 drivers/mailbox/mailbox.c
>   create mode 100644 include/linux/mailbox.h
>   create mode 100644 include/linux/mailbox_client.h
>   create mode 100644 include/linux/mailbox_controller.h
>
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index 543ad6a..fefef7e 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -1 +1,5 @@
> +# Generic MAILBOX API
> +
> +obj-$(CONFIG_MAILBOX)          += mailbox.o
> +
>   obj-$(CONFIG_PL320_MBOX)       += pl320-ipc.o
> diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
> new file mode 100644
> index 0000000..a93c22f
> --- /dev/null
> +++ b/drivers/mailbox/mailbox.c
> @@ -0,0 +1,494 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<linux/interrupt.h>
> +#include<linux/spinlock.h>
> +#include<linux/mutex.h>
> +#include<linux/delay.h>
> +#include<linux/slab.h>
> +#include<linux/err.h>
> +#include<linux/module.h>
> +#include<linux/mailbox_client.h>
> +#include<linux/mailbox_controller.h>
> +
> +/*
> + * The length of circular buffer for queuing messages from a client.
> + * 'msg_count' tracks the number of buffered messages while 'msg_free'
> + * is the index where the next message would be buffered.
> + * We shouldn't need it too big because every transferr is interrupt
> + * triggered and if we have lots of data to transfer, the interrupt
> + * latencies are going to be the bottleneck, not the buffer length.
> + * Besides, ipc_send_message could be called from atomic context and
> + * the client could also queue another message from the notifier 'txcb'
> + * of the last transfer done.
> + */
> +#define MBOX_TX_QUEUE_LEN      10
> +
> +#define TXDONE_BY_IRQ  (1<<  0) /* controller has remote RTR irq */
> +#define TXDONE_BY_POLL (1<<  1) /* controller can read status of last TX */
> +#define TXDONE_BY_ACK  (1<<  2) /* S/W ACK recevied by Client ticks the TX */
> +
> +struct ipc_chan {
> +       char chan_name[32]; /* controller_name:link_name */
> +       unsigned txdone_method;
> +
> +       /* Cached values from controller */
> +       struct ipc_link *link;
> +       struct ipc_link_ops *link_ops;
> +
> +       /* Cached values from client */
> +       void (*rxcb)(void *data);
> +       void (*txcb)(request_token_t t, enum xfer_result r);
> +       bool tx_block;
> +       unsigned long tx_tout;
> +       struct completion tx_complete;
> +
> +       request_token_t active_token;
> +       unsigned msg_count, msg_free;
> +       void *msg_data[MBOX_TX_QUEUE_LEN];
> +       /* Timer shared by all links of a controller */
> +       struct tx_poll_timer *timer;
> +       bool assigned;
> +       /* Serialize access to the channel */
> +       spinlock_t lock;
> +       /* Hook to add to the global list of channels */
> +       struct list_head node;
> +       /* Notifier to all clients waiting on aquiring this channel */
> +       struct blocking_notifier_head avail;
> +};
> +
> +/*
> + * If the controller supports only TXDONE_BY_POLL, this
> + * timer polls all the links for txdone.
> + */
> +struct tx_poll_timer {
> +       struct timer_list poll;
> +       unsigned period;
> +};
> +
> +static LIST_HEAD(ipc_channels);
> +static DEFINE_MUTEX(chpool_mutex);
> +
> +static request_token_t _add_to_rbuf(struct ipc_chan *chan, void *data)
> +{
> +       request_token_t idx;
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&chan->lock, flags);
> +
> +       /* See if there is any space left */
> +       if (chan->msg_count == MBOX_TX_QUEUE_LEN) {
> +               spin_unlock_irqrestore(&chan->lock, flags);
> +               return 0;
> +       }
> +
> +       idx = chan->msg_free;
> +       chan->msg_data[idx] = data;
> +       chan->msg_count++;
> +
> +       if (idx == MBOX_TX_QUEUE_LEN - 1)
> +               chan->msg_free = 0;
> +       else
> +               chan->msg_free++;
> +
> +       spin_unlock_irqrestore(&chan->lock, flags);
> +
> +       return idx + 1;
> +}
> +
> +static void _msg_submit(struct ipc_chan *chan)
> +{
> +       struct ipc_link *link = chan->link;
> +       unsigned count, idx;
> +       unsigned long flags;
> +       void *data;
> +       int err;
> +
> +       spin_lock_irqsave(&chan->lock, flags);
> +
> +       if (!chan->msg_count || chan->active_token) {
> +               spin_unlock_irqrestore(&chan->lock, flags);
> +               return;
> +       }
> +
> +       count = chan->msg_count;
> +       idx = chan->msg_free;
> +       if (idx>= count)
> +               idx -= count;
> +       else
> +               idx += MBOX_TX_QUEUE_LEN - count;
> +
> +       data = chan->msg_data[idx];
> +
> +       /* Try to submit a message to the IPC controller */
> +       err = chan->link_ops->send_data(link, data);
> +       if (!err) {
> +               chan->active_token = idx + 1;
> +               chan->msg_count--;
> +       }
> +
> +       spin_unlock_irqrestore(&chan->lock, flags);
> +}
> +
> +static void tx_tick(struct ipc_chan *chan, enum xfer_result r)
> +{
> +       unsigned long flags;
> +       request_token_t t;
> +
> +       spin_lock_irqsave(&chan->lock, flags);
> +       t = chan->active_token;
> +       chan->active_token = 0;
> +       spin_unlock_irqrestore(&chan->lock, flags);
> +
> +       /* Submit next message */
> +       _msg_submit(chan);
> +
> +       /* Notify the client */
> +       if (chan->tx_block)
> +               complete(&chan->tx_complete);
> +       else if (t&&  chan->txcb)
> +               chan->txcb(t, r);
> +}
> +
> +static void poll_txdone(unsigned long data)
> +{
> +       struct tx_poll_timer *timer = (struct tx_poll_timer *)data;
> +       bool txdone, resched = false;
> +       struct ipc_chan *chan;
> +
> +       list_for_each_entry(chan,&ipc_channels, node) {
> +               if (chan->timer == timer
> +&&  chan->active_token&&  chan->assigned) {
> +                       resched = true;
> +                       txdone = chan->link_ops->last_tx_done(chan->link);
> +                       if (txdone)
> +                               tx_tick(chan, XFER_OK);
> +               }
> +       }
> +
> +       if (resched)
> +               mod_timer(&timer->poll,
> +                       jiffies + msecs_to_jiffies(timer->period));
> +}
> +
> +/*
> + * After 'startup' and before 'shutdown', the IPC controller driver
> + * notifies the API of data received over the link.
> + * The controller driver should make sure the 'RTR' is de-asserted since
> + * reception of the packet and until after this call returns.
> + * This call could be made from atomic context.
> + */
> +void ipc_link_received_data(struct ipc_link *link, void *data)
> +{
> +       struct ipc_chan *chan = (struct ipc_chan *)link->api_priv;
> +
> +       /* No buffering the received data */
> +       if (chan->rxcb)
> +               chan->rxcb(data);
> +}
> +EXPORT_SYMBOL(ipc_link_received_data);
> +
> +/*
> + * The IPC controller driver notifies the API that the remote has
> + * asserted RTR and it could now send another message on the link.
> + */
> +void ipc_link_txdone(struct ipc_link *link, enum xfer_result r)
> +{
> +       struct ipc_chan *chan = (struct ipc_chan *)link->api_priv;
> +
> +       if (unlikely(!(chan->txdone_method&  TXDONE_BY_IRQ))) {
> +               pr_err("Controller can't run the TX ticker\n");
> +               return;
> +       }
> +
> +       tx_tick(chan, r);
> +}
> +EXPORT_SYMBOL(ipc_link_txdone);
> +
> +/*
> + * The client/protocol had received some 'ACK' packet and it notifies
> + * the API that the last packet was sent successfully. This only works
> + * if the controller doesn't get IRQ for TX done.
> + */
> +void ipc_client_txdone(void *channel, enum xfer_result r)
> +{
> +       struct ipc_chan *chan = (struct ipc_chan *)channel;
> +       bool txdone = true;
> +
> +       if (unlikely(!(chan->txdone_method&  TXDONE_BY_ACK))) {
> +               pr_err("Client can't run the TX ticker\n");
> +               return;
> +       }
> +
> +       if (chan->txdone_method&  TXDONE_BY_POLL)
> +               txdone = chan->link_ops->last_tx_done(chan->link);
> +
> +       if (txdone)
> +               tx_tick(chan, r);
> +}
> +EXPORT_SYMBOL(ipc_client_txdone);
> +
> +/*
> + * Called by a client to "put data on the h/w channel" so that if
> + * everything else is fine we don't need to do anything more locally
> + * for the remote to receive the data intact.
> + * In reality, the remote may receive it intact, corrupted or not at all.
> + * This could be called from atomic context as it simply
> + * queues the data and returns a token (request_token_t)
> + * against the request.
> + * The client is later notified of successful transmission of
> + * data over the channel via the 'txcb'. The client could in
> + * turn queue more messages from txcb.
> + */
> +request_token_t ipc_send_message(void *channel, void *data)
> +{
> +       struct ipc_chan *chan = (struct ipc_chan *)channel;
> +       request_token_t t;
> +
> +       if (!chan || !chan->assigned)
> +               return 0;
> +
> +       t = _add_to_rbuf(chan, data);
> +       if (!t)
> +               pr_err("Try increasing MBOX_TX_QUEUE_LEN\n");
> +
> +       _msg_submit(chan);
> +
> +       if (chan->txdone_method == TXDONE_BY_POLL)
> +               poll_txdone((unsigned long)chan->timer);
> +
> +       if (chan->tx_block&&  chan->active_token) {
> +               int ret;
> +               init_completion(&chan->tx_complete);
> +               ret = wait_for_completion_timeout(&chan->tx_complete,
> +                       chan->tx_tout);
> +               if (ret == 0) {
> +                       t = 0;
> +                       tx_tick(chan, XFER_ERR);
> +               }
> +       }
> +
> +       return t;
> +}
> +EXPORT_SYMBOL(ipc_send_message);
> +
> +/*
> + * A client driver asks for exclusive use of a channel/mailbox.
> + * If assigned, the channel has to be 'freed' before it could
> + * be assigned to some other client.
> + * After assignment, any packet received on this channel will be
> + * handed over to the client via the 'rxcb' callback.
> + * The 'txcb' callback is used to notify client upon sending the
> + * packet over the channel, which may or may not have been yet
> + * read by the remote processor.
> + */
> +void *ipc_request_channel(struct ipc_client *cl)
> +{
> +       struct ipc_chan *chan;
> +       unsigned long flags;
> +       int ret = 0;
> +
> +       mutex_lock(&chpool_mutex);
> +
> +       list_for_each_entry(chan,&ipc_channels, node)
> +               if (!chan->assigned
> +&&  !strcmp(cl->chan_name, chan->chan_name)) {
> +                       spin_lock_irqsave(&chan->lock, flags);
> +                       chan->msg_free = 0;
> +                       chan->msg_count = 0;
> +                       chan->active_token = 0;
> +                       chan->rxcb = cl->rxcb;
> +                       chan->txcb = cl->txcb;
> +                       chan->assigned = true;
> +                       chan->tx_block = cl->tx_block;
> +                       if (!cl->tx_tout)
> +                               chan->tx_tout = ~0;
> +                       else
> +                               chan->tx_tout = msecs_to_jiffies(cl->tx_tout);
> +                       if (chan->txdone_method == TXDONE_BY_POLL
> +&&  cl->knows_txdone)
> +                               chan->txdone_method |= TXDONE_BY_ACK;
> +                       spin_unlock_irqrestore(&chan->lock, flags);
> +                       ret = 1;
> +                       break;
> +               }
> +
> +       mutex_unlock(&chpool_mutex);
> +
> +       if (!ret) {
> +               pr_err("Unable to assign mailbox(%s)\n", cl->chan_name);
> +               return NULL;
> +       }
> +
> +       ret = chan->link_ops->startup(chan->link, cl->cntlr_data);
> +       if (ret) {
> +               pr_err("Unable to startup the link\n");
> +               ipc_free_channel((void *)chan);
> +               return NULL;
> +       }
> +
> +       return (void *)chan;
> +}
> +EXPORT_SYMBOL(ipc_request_channel);
> +
> +/* Drop any messages queued and release the channel */
> +void ipc_free_channel(void *ch)
> +{
> +       struct ipc_chan *chan = (struct ipc_chan *)ch;
> +       unsigned long flags;
> +
> +       if (!chan || !chan->assigned)
> +               return;
> +
> +       chan->link_ops->shutdown(chan->link);
> +
> +       /* The queued TX requests are simply aborted, no callbacks are made */
> +       spin_lock_irqsave(&chan->lock, flags);
> +       chan->assigned = false;
> +       chan->active_token = 0;
> +       if (chan->txdone_method == (TXDONE_BY_POLL | TXDONE_BY_ACK))
> +               chan->txdone_method = TXDONE_BY_POLL;
> +       spin_unlock_irqrestore(&chan->lock, flags);
> +
> +       del_timer_sync(chan->timer);
> +
> +       blocking_notifier_call_chain(&chan->avail, 0, NULL);
> +}
> +EXPORT_SYMBOL(ipc_free_channel);
> +
> +static struct ipc_chan *name_to_chan(const char *name)
> +{
> +       struct ipc_chan *chan;
> +       int ret = 0;
> +
> +       mutex_lock(&chpool_mutex);
> +       list_for_each_entry(chan,&ipc_channels, node)
> +               if (!strcmp(name, chan->chan_name)) {
> +                       ret = 1;
> +                       break;
> +               }
> +       mutex_unlock(&chpool_mutex);
> +
> +       if (!ret)
> +               return NULL;
> +
> +       return chan;
> +}
> +
> +int ipc_notify_chan_register(const char *name, struct notifier_block *nb)
> +{
> +       struct ipc_chan *chan = name_to_chan(name);
> +
> +       if (chan&&  nb)
> +               return blocking_notifier_chain_register(&chan->avail, nb);
> +
> +       return -EINVAL;
> +}
> +EXPORT_SYMBOL(ipc_notify_chan_register);
> +
> +void ipc_notify_chan_unregister(const char *name, struct notifier_block *nb)
> +{
> +       struct ipc_chan *chan = name_to_chan(name);
> +
> +       if (chan&&  nb)
> +               blocking_notifier_chain_unregister(&chan->avail, nb);
> +}
> +EXPORT_SYMBOL(ipc_notify_chan_unregister);
> +
> +/*
> + * Call for IPC controller drivers to register a controller, adding
> + * its channels/mailboxes to the global pool.
> + */
> +int ipc_links_register(struct ipc_controller *ipc_con)
> +{
> +       struct tx_poll_timer *timer = NULL;
> +       struct ipc_chan *channel;
> +       int i, num_links, txdone;
> +
> +       /* Are you f***ing with us, sir? */
> +       if (!ipc_con || !ipc_con->ops)
> +               return -EINVAL;
> +
> +       for (i = 0; ipc_con->links[i]; i++)
> +               ;
> +       if (!i)
> +               return -EINVAL;
> +       num_links = i;
> +
> +       if (ipc_con->txdone_irq)
> +               txdone = TXDONE_BY_IRQ;
> +       else if (ipc_con->txdone_poll)
> +               txdone = TXDONE_BY_POLL;
> +       else /* It has to be at least ACK */
> +               txdone = TXDONE_BY_ACK;
> +
> +       if (txdone == TXDONE_BY_POLL) {
> +               timer = kzalloc(sizeof(struct tx_poll_timer), GFP_KERNEL);
> +               if (!timer)
> +                       return -ENOMEM;
> +               timer->period = ipc_con->txpoll_period;
> +               timer->poll.function =&poll_txdone;
> +               timer->poll.data = (unsigned long)timer;
> +               init_timer(&timer->poll);
> +       }
> +
> +       channel = kzalloc(sizeof(struct ipc_chan) * num_links, GFP_KERNEL);
> +       if (!channel) {
> +               kfree(timer);
> +               return -ENOMEM;
> +       }
> +
> +       for (i = 0; i<  num_links; i++) {
> +               channel[i].timer = timer;
> +               channel[i].assigned = false;
> +               channel[i].txdone_method = txdone;
> +               channel[i].link_ops = ipc_con->ops;
> +               channel[i].link = ipc_con->links[i];
> +               channel[i].link->api_priv =&channel[i];
> +               snprintf(channel[i].chan_name, 32, "%s:%s",
> +                       ipc_con->controller_name,
> +                       ipc_con->links[i]->link_name);
> +               spin_lock_init(&channel[i].lock);
> +               BLOCKING_INIT_NOTIFIER_HEAD(&channel[i].avail);
> +               mutex_lock(&chpool_mutex);
> +               list_add_tail(&channel[i].node,&ipc_channels);
> +               mutex_unlock(&chpool_mutex);
> +       }
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL(ipc_links_register);
> +
> +void ipc_links_unregister(struct ipc_controller *ipc_con)
> +{
> +       struct ipc_chan *chan, *t, *first = NULL;
> +       struct tx_poll_timer *timer = NULL;
> +       char *name;
> +       int i;
> +
> +       mutex_lock(&chpool_mutex);
> +       for (i = 0; ipc_con->links[i]; i++) {
> +               snprintf(name, 32, "%s:%s",
> +                       ipc_con->controller_name,
> +                       ipc_con->links[i]->link_name);
> +               list_for_each_entry_safe(chan, t,&ipc_channels, node) {
> +                       if (!strcmp(name, chan->chan_name)) {
> +                               if (!first)
> +                                       first = chan;
> +                               if (!timer)
> +                                       timer = chan->timer;
> +                               list_del(&chan->node);
> +                               ipc_free_channel((void *)chan);
> +                               break;
> +                       }
> +               }
> +       }
> +       mutex_unlock(&chpool_mutex);
> +
> +       kfree(first);
> +       kfree(timer);
> +}
> +EXPORT_SYMBOL(ipc_links_unregister);
> diff --git a/include/linux/mailbox.h b/include/linux/mailbox.h
> new file mode 100644
> index 0000000..232e2c4
> --- /dev/null
> +++ b/include/linux/mailbox.h
> @@ -0,0 +1,17 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MAILBOX_H
> +#define __MAILBOX_H
> +
> +enum xfer_result {
> +       XFER_OK = 0,
> +       XFER_ERR,
> +};
> +
> +typedef unsigned request_token_t;
> +
> +#endif /* __MAILBOX_H */
> diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h
> new file mode 100644
> index 0000000..232fdc7
> --- /dev/null
> +++ b/include/linux/mailbox_client.h
> @@ -0,0 +1,85 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MAILBOX_CLIENT_H
> +#define __MAILBOX_CLIENT_H
> +
> +#include<linux/mailbox.h>
> +
> +/**
> + * struct ipc_client - User of a mailbox
> + * @chan_name: the "controller:channel" this client wants
> + * @rxcb: atomic callback to provide client the data received
> + * @txcb: atomic callback to tell client of data transmission
> + * @tx_block: if the ipc_send_message should block until data is transmitted
> + * @tx_tout: Max block period in ms before TX is assumed failure
> + * @knows_txdone: if the client could run the TX state machine. Usually if
> + *    the client receives some ACK packet for transmission. Unused if the
> + *    controller already has TX_Done/RTR IRQ.
> + * @cntlr_data: Optional controller specific parameters during channel request
> + */
> +struct ipc_client {
> +       char *chan_name;
> +       void (*rxcb)(void *data);
> +       void (*txcb)(request_token_t t, enum xfer_result r);
> +       bool tx_block;
> +       unsigned long tx_tout;
> +       bool knows_txdone;
> +       void *cntlr_data;
> +};
> +
> +/**
> + * The Client specifies it requirements and capabilities while asking for
> + * a channel/mailbox by name. It can't be called from atomic context.
> + * The channel is exclusively allocated and can't be used by another
> + * client before the owner calls ipc_free_channel.
> + */
> +void *ipc_request_channel(struct ipc_client *cl);
> +
> +/**
> + * For client to submit data to the controller destined for a remote
> + * processor. If the client had set 'tx_block', the call will return
> + * either when the remote receives the data or when 'tx_tout' millisecs
> + * run out.
> + *  In non-blocking mode, the requests are buffered by the API and a
> + * non-zero token is returned for each queued request. If the queue
> + * was full the returned token will be 0. Upon failure or successful
> + * TX, the API calls 'txcb' from atomic context, from which the client
> + * could submit yet another request.
> + *  In blocking mode, 'txcb' is not called, effectively making the
> + * queue length 1. The returned value is 0 if TX timed out, some
> + * non-zero value upon success.
> + */
> +request_token_t ipc_send_message(void *channel, void *data);
> +
> +/**
> + * The way for a client to run the TX state machine. This works
> + * only if the client sets 'knows_txdone' and the IPC controller
> + * don't get an IRQ for TX_Done.
> + */
> +void ipc_client_txdone(void *channel, enum xfer_result r);
> +
> +/**
> + * The client relinquishes control of a mailbox by this call,
> + * make it available to other clients.
> + * The ipc_request/free_channel are light weight calls, so the
> + * client should avoid holding it when it doesn't need to
> + * transfer data.
> + */
> +void ipc_free_channel(void *ch);
> +
> +/**
> + * The client make ask the API to be notified when a particular channel
> + * becomes available to be acquired again.
> + */
> +int ipc_notify_chan_register(const char *name, struct notifier_block *nb);
> +
> +/**
> + * The client is no more interested in acquiring the channel.
> + */
> +void ipc_notify_chan_unregister(const char *name, struct notifier_block *nb);
> +
> +#endif /* __MAILBOX_CLIENT_H */
> diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h
> new file mode 100644
> index 0000000..23b80e3
> --- /dev/null
> +++ b/include/linux/mailbox_controller.h
> @@ -0,0 +1,102 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MAILBOX_CONTROLLER_H
> +#define __MAILBOX_CONTROLLER_H
> +
> +#include<linux/mailbox.h>
> +
> +/**
> + * struct ipc_link - s/w representation of a communication link
> + * @link_name: Literal name assigned to the link. Physically
> + *    identical channels may have the same name.
> + * @api_priv: hook for the API to map its private data on the link
> + *    Controller driver must not touch it.
> + */
> +struct ipc_link {
> +       char link_name[16];
> +       void *api_priv;
> +};
> +
> +/**
> + * struct ipc_link - s/w representation of a communication link
> + * @send_data: The API asks the IPC controller driver, in atomic
> + *    context try to transmit a message on the bus. Returns 0 if
> + *    data is accepted for transmission, -EBUSY while rejecting
> + *    if the remote hasn't yet read the last data sent. Actual
> + *    transmission of data is reported by the controller via
> + *    ipc_link_txdone (if it has some TX ACK irq). It must not
> + *    block.
> + * @startup: Called when a client requests the link. The controller
> + *    could ask clients for additional parameters of communication
> + *    to be provided via client's cntlr_data. This call may block.
> + *    After this call the Controller must forward any data received
> + *    on the link by calling ipc_link_received_data (which won't block)
> + * @shutdown: Called when a client relinquishes control of a link.
> + *    This call may block too. The controller must not forwared
> + *    any received data anymore.
> + * @last_tx_done: If the controller sets 'txdone_poll', the API calls
> + *    this to poll status of last TX. The controller must give priority
> + *    to IRQ method over polling and never set both txdone_poll and
> + *    txdone_irq. Only in polling mode 'send_data' is expected to
> + *    return -EBUSY. Used only if txdone_poll:=true&&  txdone_irq:=false
> + */
> +struct ipc_link_ops {
> +       int (*send_data)(struct ipc_link *link, void *data);
> +       int (*startup)(struct ipc_link *link, void *params);
> +       void (*shutdown)(struct ipc_link *link);
> +       bool (*last_tx_done)(struct ipc_link *link);
> +};
> +
> +/**
> + * struct ipc_controller - Controller of a class of communication links
> + * @controller_name: Literal name of the controller.
> + * @ops: Operators that work on each communication link
> + * @links: Null terminated array of links.
> + * @txdone_irq: Indicates if the controller can report to API when the
> + *    last transmitted data was read by the remote. Eg, if it has some
> + *    TX ACK irq.
> + * @txdone_poll: If the controller can read but not report the TX done.
> + *    Eg, is some register shows the TX status but no interrupt rises.
> + *    Ignored if 'txdone_irq' is set.
> + * @txpoll_period: If 'txdone_poll' is in effect, the API polls for
> + *    last TX's status after these many millisecs
> + */
> +struct ipc_controller {
> +       char controller_name[16];
> +       struct ipc_link_ops *ops;
> +       struct ipc_link **links;
> +       bool txdone_irq;
> +       bool txdone_poll;
> +       unsigned txpoll_period;
> +};
> +
> +/**
> + * The controller driver registers its communication links to the
> + * global pool managed by the API.
> + */
> +int ipc_links_register(struct ipc_controller *ipc_con);
> +
> +/**
> + * After startup and before shutdown any data received on the link
> + * is pused to the API via atomic ipc_link_received_data() API.
> + * The controller should ACK the RX only after this call returns.
> + */
> +void ipc_link_received_data(struct ipc_link *link, void *data);
> +
> +/**
> + * The controller the has IRQ for TX ACK calls this atomic API
> + * to tick the TX state machine. It works only if txdone_irq
> + * is set by the controller.
> + */
> +void ipc_link_txdone(struct ipc_link *link, enum xfer_result r);
> +
> +/**
> + * Purge the links from the global pool maintained by the API.
> + */
> +void ipc_links_unregister(struct ipc_controller *ipc_con);
> +
> +#endif /* __MAILBOX_CONTROLLER_H */
> --
> 1.7.10.4
>


From linus.walleij at linaro.org  Mon May 13 15:09:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 May 2013 21:09:38 +0200
Subject: [PATCH] serial: pl011: protect attribute read from NULL platform
 data struct
In-Reply-To: <1368103855-28363-1-git-send-email-lee.jones@linaro.org>
References: <1368103855-28363-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZR3AsGyCUH=cbskcZPs0PVBjH6QXUGkD+KG8SzGMMOKg@mail.gmail.com>

On Thu, May 9, 2013 at 2:50 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It's completely feasible that platform data will be empty i.e. when
> booting with Device Tree with no device AUXDATA. So we must protect
> it's use in these use-cases, or risk a kernel Oops.
>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: Jiri Slaby <jslaby at suse.cz>
> Cc: linux-serial at vger.kernel.org
> Cc: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
> *******                                                        *******
> If this issue has not already been fixed, this patch should be applied
> during the v3.10 -rc:s, as it fixes a serious bug which was introduced
> in the merge-window.
> *******                                                        *******

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

You should probably put Greg on To: so that he picks this up for
the -rc:s ASAP.

Yours,
Linus Walleij


From swarren at wwwdotorg.org  Mon May 13 15:24:30 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 13:24:30 -0600
Subject: [PATCH 2/4] ARM: tegra: create a DT header defining GPIO IDs
In-Reply-To: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
References: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1368473072-10145-2-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

All Tegra GPIOs are named after the GPIO bank and GPIO number within
the bank. Define a macro to calculate the GPIO ID based on those
parameters. Make the macro available via all Tegra .dtsip files.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 include/dt-bindings/gpio/tegra-gpio.h |   50 +++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 include/dt-bindings/gpio/tegra-gpio.h

diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
new file mode 100644
index 0000000..4d179c0
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -0,0 +1,50 @@
+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define TEGRA_GPIO_BANK_ID_A 0
+#define TEGRA_GPIO_BANK_ID_B 1
+#define TEGRA_GPIO_BANK_ID_C 2
+#define TEGRA_GPIO_BANK_ID_D 3
+#define TEGRA_GPIO_BANK_ID_E 4
+#define TEGRA_GPIO_BANK_ID_F 5
+#define TEGRA_GPIO_BANK_ID_G 6
+#define TEGRA_GPIO_BANK_ID_H 7
+#define TEGRA_GPIO_BANK_ID_I 8
+#define TEGRA_GPIO_BANK_ID_J 9
+#define TEGRA_GPIO_BANK_ID_K 10
+#define TEGRA_GPIO_BANK_ID_L 11
+#define TEGRA_GPIO_BANK_ID_M 12
+#define TEGRA_GPIO_BANK_ID_N 13
+#define TEGRA_GPIO_BANK_ID_O 14
+#define TEGRA_GPIO_BANK_ID_P 15
+#define TEGRA_GPIO_BANK_ID_Q 16
+#define TEGRA_GPIO_BANK_ID_R 17
+#define TEGRA_GPIO_BANK_ID_S 18
+#define TEGRA_GPIO_BANK_ID_T 19
+#define TEGRA_GPIO_BANK_ID_U 20
+#define TEGRA_GPIO_BANK_ID_V 21
+#define TEGRA_GPIO_BANK_ID_W 22
+#define TEGRA_GPIO_BANK_ID_X 23
+#define TEGRA_GPIO_BANK_ID_Y 24
+#define TEGRA_GPIO_BANK_ID_Z 25
+#define TEGRA_GPIO_BANK_ID_AA 26
+#define TEGRA_GPIO_BANK_ID_BB 27
+#define TEGRA_GPIO_BANK_ID_CC 28
+#define TEGRA_GPIO_BANK_ID_DD 29
+#define TEGRA_GPIO_BANK_ID_EE 30
+
+#define TEGRA_GPIO(bank, offset) \
+	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+
+#endif
-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May 13 15:24:29 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 13:24:29 -0600
Subject: [PATCH 1/4] ARM: tegra: use #include for all device trees
Message-ID: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.

This allows future use of #defines and header files in order to define
names for various constants, such as the IDs and flags in GPIO
specifiers. Use of those features will increase the readability of the
device tree files.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
This series will need some slight updates when rebased on top of Venu's
USB binding cleanup series, but I figured I may as well send this for
review as early as possible; I'll see if I can post an incremental patch
for the rebase.

 arch/arm/boot/dts/tegra114-dalmore.dts     |    2 +-
 arch/arm/boot/dts/tegra114-pluto.dts       |    2 +-
 arch/arm/boot/dts/tegra114.dtsi            |    2 +-
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |    2 +-
 arch/arm/boot/dts/tegra20-harmony.dts      |    2 +-
 arch/arm/boot/dts/tegra20-iris-512.dts     |    2 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |    2 +-
 arch/arm/boot/dts/tegra20-paz00.dts        |    2 +-
 arch/arm/boot/dts/tegra20-plutux.dts       |    2 +-
 arch/arm/boot/dts/tegra20-seaboard.dts     |    2 +-
 arch/arm/boot/dts/tegra20-tamonten.dtsi    |    2 +-
 arch/arm/boot/dts/tegra20-tec.dts          |    2 +-
 arch/arm/boot/dts/tegra20-trimslice.dts    |    2 +-
 arch/arm/boot/dts/tegra20-ventana.dts      |    2 +-
 arch/arm/boot/dts/tegra20-whistler.dts     |    2 +-
 arch/arm/boot/dts/tegra20.dtsi             |    2 +-
 arch/arm/boot/dts/tegra30-beaver.dts       |    2 +-
 arch/arm/boot/dts/tegra30-cardhu-a02.dts   |    2 +-
 arch/arm/boot/dts/tegra30-cardhu-a04.dts   |    2 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi      |    2 +-
 arch/arm/boot/dts/tegra30.dtsi             |    2 +-
 21 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 72c1f27..3c563af 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 
 / {
 	model = "NVIDIA Tegra114 Dalmore evaluation board";
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 6bbc8ef..d5f8d3e 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 
 / {
 	model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 629415f..aeeb53b 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra114";
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index a573b94..390a4fb 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "Toradex Colibri T20 512MB";
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e7d5de4..3f968f2 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "NVIDIA Tegra20 Harmony evaluation board";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 52f1103..248f7ea 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-colibri-512.dtsi"
+#include "tegra20-colibri-512.dtsi"
 
 / {
 	model = "Toradex Colibri T20 512MB on Iris";
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index ace2343..d7e32fa 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
 	model = "Avionic Design Medcom-Wide board";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e3e0c99..df57639 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "Toshiba AC100 / Dynabook AZ";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 1a17cc3..508e56a 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
 	model = "Avionic Design Plutux board";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index cee4c34..368e6fb 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "NVIDIA Seaboard";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 50b3ec1..eb6ba60 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "Avionic Design Tamonten SOM";
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 742f0b3..9a2a6a4 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
 	model = "Avionic Design Tamonten Evaluation Carrier";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9cc78a1..cf4fdce 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "Compulab TrimSlice board";
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index dd38f1f..9f9efec 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "NVIDIA Tegra20 Ventana evaluation board";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d2567f8..8c415f2 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
 	model = "NVIDIA Tegra20 Whistler evaluation board";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 56a9110..ed5f23f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra20";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b732f7c..b92ab8a 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 
 / {
 	model = "NVIDIA Tegra30 Beaver evaluation board";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index e392bd2..3934b0f 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 
 /* This dts file support the cardhu A02 version of board */
 
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index d0db6c7..af3ff7a 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 
 /* This dts file support the cardhu A04 and later versions of board */
 
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 01b4c26..e54eed2 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 
 /**
  * This file contains common DT entry for all fab version of Cardhu.
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15ded60..38967fd 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra30";
-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May 13 15:24:31 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 13:24:31 -0600
Subject: [PATCH 3/4] ARM: tegra: convert device tree files to use GPIO defines
In-Reply-To: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
References: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1368473072-10145-3-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra114-dalmore.dts     |   12 ++++----
 arch/arm/boot/dts/tegra114.dtsi            |    2 ++
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |   16 ++++++----
 arch/arm/boot/dts/tegra20-harmony.dts      |   46 ++++++++++++++++------------
 arch/arm/boot/dts/tegra20-iris-512.dts     |    2 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |    6 ++--
 arch/arm/boot/dts/tegra20-paz00.dts        |   24 +++++++++------
 arch/arm/boot/dts/tegra20-plutux.dts       |    6 ++--
 arch/arm/boot/dts/tegra20-seaboard.dts     |   39 ++++++++++++-----------
 arch/arm/boot/dts/tegra20-tamonten.dtsi    |    7 +++--
 arch/arm/boot/dts/tegra20-tec.dts          |    7 +++--
 arch/arm/boot/dts/tegra20-trimslice.dts    |   19 +++++++-----
 arch/arm/boot/dts/tegra20-ventana.dts      |   41 ++++++++++++++-----------
 arch/arm/boot/dts/tegra20-whistler.dts     |   10 +++---
 arch/arm/boot/dts/tegra20.dtsi             |    2 ++
 arch/arm/boot/dts/tegra30-beaver.dts       |   20 ++++++------
 arch/arm/boot/dts/tegra30-cardhu-a02.dts   |   14 ++++-----
 arch/arm/boot/dts/tegra30-cardhu-a04.dts   |   16 +++++-----
 arch/arm/boot/dts/tegra30-cardhu.dtsi      |   39 +++++++++++------------
 arch/arm/boot/dts/tegra30.dtsi             |    2 ++
 20 files changed, 182 insertions(+), 148 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 3c563af..718af25 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -828,7 +828,7 @@
 	};
 
 	sdhci at 78000400 {
-		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 		bus-width = <4>;
 		status = "okay";
 	};
@@ -873,7 +873,7 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			enable-active-high;
-			gpio = <&gpio 61 0>; /* GPIO PH5 */
+			gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
 		};
 
 		lcd_bl_en_reg: regulator at 2 {
@@ -883,7 +883,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 58 0>; /* GPIO PH2 */
+			gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 3 {
@@ -893,7 +893,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 108 0>; /* GPIO PN4 */
+			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
@@ -905,7 +905,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 86 0>; /* GPIO PK6 */
+			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
@@ -917,7 +917,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 81 0>; /* GPIO PK1 */
+			gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
 	};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index aeeb53b..6cd6d41 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 390a4fb..f5be14c 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -14,7 +14,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&i2c_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -443,17 +444,20 @@
 
 	ac97: ac97 {
 		status = "okay";
-		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
-		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+		nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 	};
 
 	clocks {
@@ -510,7 +514,7 @@
 			enable-active-high;
 			regulator-boot-on;
 			regulator-always-on;
-			gpio = <&gpio 217 0>;
+			gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 3f968f2..3cce7b0 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -262,7 +263,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -430,7 +431,8 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -438,22 +440,23 @@
 	};
 
 	usb-phy at c5004400 {
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000200 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 155 0>; /* gpio PT3 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
 	sdhci at c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <8>;
 	};
 
@@ -475,7 +478,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -618,7 +621,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -627,7 +630,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -637,7 +640,7 @@
 			regulator-name = "vdd_1v05";
 			regulator-min-microvolt = <1050000>;
 			regulator-max-microvolt = <1050000>;
-			gpio = <&pmic 2 0>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 			/* Hack until board-harmony-pcie.c is removed */
 			status = "disabled";
@@ -649,7 +652,7 @@
 			regulator-name = "vdd_pnl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 22 0>; /* gpio PC6 */
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -659,7 +662,7 @@
 			regulator-name = "vdd_bl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 176 0>; /* gpio PW0 */
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -682,10 +685,13 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
-		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 248f7ea..f1c5a64 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -73,7 +73,7 @@
 			regulator-max-microvolt = <5000000>;
 			regulator-boot-on;
 			regulator-always-on;
-			gpio = <&gpio 178 0>;
+			gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		vcc_sd_reg: regulator at 1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index d7e32fa..3adfbfe 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -15,7 +15,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -56,8 +56,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index df57639..d2b631d 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -274,7 +275,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clock-frequency = <80000>;
-		request-gpios = <&gpio 170 0>; /* gpio PV2 */
+		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
 		clocks = <&tegra_car 67>, <&tegra_car 124>;
 		clock-names = "div-clk", "fast-clk";
@@ -429,7 +430,8 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -437,14 +439,15 @@
 	};
 
 	usb-phy at c5004400 {
-		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000000 {
 		status = "okay";
-		cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-		wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
-		power-gpios = <&gpio 169 0>; /* gpio PV1 */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -472,7 +475,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -483,7 +486,7 @@
 
 		wifi {
 			label = "wifi-led";
-			gpios = <&gpio 24 0>; /* gpio PD0 */
+			gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "rfkill0";
 		};
 	};
@@ -520,7 +523,8 @@
 
 		nvidia,audio-codec = <&alc5632>;
 		nvidia,i2s-controller = <&tegra_i2s1>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 508e56a..3d8e69b 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -50,8 +50,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 368e6fb..519ae6b 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -313,7 +314,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -328,14 +329,14 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <202 0x04>; /* GPIO PZ2 */
+			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
 		};
 
 		gyrometer at 68 {
 			compatible = "invn,mpu3050";
 			reg = <0x68>;
 			interrupt-parent = <&gpio>;
-			interrupts = <204 0x04>; /* gpio PZ4 */
+			interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
 		};
 	};
 
@@ -511,7 +512,7 @@
 			compatible = "ak,ak8975";
 			reg = <0xc>;
 			interrupt-parent = <&gpio>;
-			interrupts = <109 0x04>; /* gpio PN5 */
+			interrupts = <TEGRA_GPIO(N, 5) 0x04>;
 		};
 	};
 
@@ -565,13 +566,14 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 		dr_mode = "otg";
 	};
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -579,21 +581,22 @@
 	};
 
 	usb-phy at c5004400 {
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000000 {
 		status = "okay";
-		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -621,14 +624,14 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
 
 		lid {
 			label = "Lid";
-			gpios = <&gpio 23 0>; /* gpio PC7 */
+			gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
@@ -795,7 +798,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -804,7 +807,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -827,8 +830,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index eb6ba60..78d50a3 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -14,7 +14,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -471,8 +472,8 @@
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		status = "okay";
 	};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9a2a6a4..db58bb7 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -50,8 +50,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index cf4fdce..0e097c1 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -311,12 +312,13 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -324,7 +326,8 @@
 	};
 
 	usb-phy at c5004400 {
-		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000000 {
@@ -334,8 +337,8 @@
 
 	sdhci at c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+		cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -357,7 +360,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 190 1>; /* gpio PX6, active low */
+			gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -365,7 +368,7 @@
 
 	poweroff {
 		compatible = "gpio-poweroff";
-		gpios = <&gpio 191 1>; /* gpio PX7, active low */
+		gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
 	};
 
 	regulators {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 9f9efec..60eb5a3 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -310,7 +311,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -325,7 +326,7 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <202 0x04>; /*gpio PZ2 */
+			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
 		};
 	};
 
@@ -507,7 +508,8 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -515,21 +517,22 @@
 	};
 
 	usb-phy at c5004400 {
-		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000000 {
 		status = "okay";
-		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -557,7 +560,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -583,7 +586,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -592,7 +595,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -602,7 +605,7 @@
 			regulator-name = "vdd_pnl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 22 0>; /* gpio PC6 */
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -612,7 +615,7 @@
 			regulator-name = "vdd_bl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 176 0>; /* gpio PW0 */
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -635,10 +638,12 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-		nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
-		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 8c415f2..010f481 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -508,18 +509,17 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+		nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+		nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+		wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
 		bus-width = <8>;
 	};
 
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ed5f23f..c6ceb8a 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b92ab8a..a11e375 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -264,9 +264,9 @@
 
 	sdhci at 78000000 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -312,7 +312,7 @@
 			regulator-boot-on;
 			regulator-always-on;
 			enable-active-high;
-			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		ddr_reg: regulator at 2 {
@@ -324,7 +324,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -337,7 +337,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 30 0>; /* gpio PD6 */
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -348,7 +348,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 68 0>; /* GPIO PI4 */
+			gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
@@ -360,7 +360,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 63 0>; /* GPIO PH7 */
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
@@ -374,7 +374,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -387,7 +387,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 95 0>; /* gpio PL7 */
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 3934b0f..1082c5e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -22,7 +22,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		sys_3v3_reg: regulator at 101 {
@@ -34,7 +34,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 102 {
@@ -44,7 +44,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 68 0>; /* GPIO PI4 */
+			gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 63 0>; /* GPIO PH7 */
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -68,7 +68,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&pmic 2 0>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl_reg: regulator at 105 {
@@ -80,13 +80,13 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 83 0>; /* GPIO PK3 */
+			gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	sdhci at 78000400 {
 		status = "okay";
-		power-gpios = <&gpio 28 0>; /* gpio PD4 */
+		power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index af3ff7a..bf012bdd 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -22,7 +22,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		sys_3v3_reg: regulator at 101 {
@@ -34,7 +34,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 102 {
@@ -44,7 +44,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 238 0>; /* GPIO PDD6 */
+			gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 236 0>; /* GPIO PDD4 */
+			gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -68,7 +68,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&pmic 8 0>;
+			gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl_reg: regulator at 105 {
@@ -80,7 +80,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 234 0>; /* GPIO PDD2 */
+			gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl2_reg: regulator at 106 {
@@ -92,13 +92,13 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 232 0>; /* GPIO PDD0 */
+			gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	sdhci at 78000400 {
 		status = "okay";
-		power-gpios = <&gpio 27 0>; /* gpio PD3 */
+		power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index e54eed2..c177fd9 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -146,7 +146,7 @@
 			compatible = "isil,isl29028";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <88 0x04>; /*gpio PL0 */
+			interrupts = <TEGRA_GPIO(L, 0) 0x04>;
 		};
 	};
 
@@ -163,7 +163,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <179 0x04>; /* gpio PW3 */
+			interrupts = <TEGRA_GPIO(W, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -318,9 +318,9 @@
 
 	sdhci at 78000000 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -364,7 +364,7 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			enable-active-high;
-			gpio = <&gpio 220 0>; /* gpio PBB4 */
+			gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vio_reg>;
 		};
 
@@ -377,7 +377,7 @@
 			regulator-boot-on;
 			regulator-always-on;
 			enable-active-high;
-			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		emmc_3v3_reg: regulator at 3 {
@@ -389,7 +389,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 25 0>; /* gpio PD1 */
+			gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -400,7 +400,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 30 0>; /* gpio PD6 */
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 		};
 
 		pex_hvdd_3v3_reg: regulator at 5 {
@@ -410,7 +410,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 95 0>; /* gpio PL7 */
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -421,7 +421,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			enable-active-high;
-			gpio = <&gpio 142 0>; /* gpio PR6 */
+			gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -432,7 +432,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			enable-active-high;
-			gpio = <&gpio 143 0>; /* gpio PR7 */
+			gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -443,7 +443,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 144 0>; /* gpio PS0 */
+			gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -456,7 +456,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 24 0>; /* gpio PD0 */
+			gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -467,7 +467,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 94 0>; /* gpio PL6 */
+			gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -480,7 +480,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 92 0>; /* gpio PL4 */
+			gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -491,7 +491,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 152 0>; /* GPIO PT0 */
+			gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -515,8 +515,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 38967fd..1fe8c3a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May 13 15:24:32 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 13:24:32 -0600
Subject: [PATCH 4/4] ARM: tegra: convert device tree files to use IRQ defines
In-Reply-To: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
References: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1368473072-10145-4-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Use the GIC and standard IRQ binding defines in all IRQ specifiers.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra114-dalmore.dts     |    2 +-
 arch/arm/boot/dts/tegra114.dtsi            |  151 ++++++++++++------------
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |    2 +-
 arch/arm/boot/dts/tegra20-harmony.dts      |    4 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |    2 +-
 arch/arm/boot/dts/tegra20-paz00.dts        |    4 +-
 arch/arm/boot/dts/tegra20-plutux.dts       |    2 +-
 arch/arm/boot/dts/tegra20-seaboard.dts     |   10 +-
 arch/arm/boot/dts/tegra20-tamonten.dtsi    |    2 +-
 arch/arm/boot/dts/tegra20-tec.dts          |    2 +-
 arch/arm/boot/dts/tegra20-ventana.dts      |    6 +-
 arch/arm/boot/dts/tegra20-whistler.dts     |    2 +-
 arch/arm/boot/dts/tegra20.dtsi             |  138 +++++++++++-----------
 arch/arm/boot/dts/tegra30-beaver.dts       |    2 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi      |    6 +-
 arch/arm/boot/dts/tegra30.dtsi             |  174 ++++++++++++++--------------
 16 files changed, 260 insertions(+), 249 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 718af25..b6f3c80 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -748,7 +748,7 @@
 			compatible = "ti,tps65090";
 			reg = <0x48>;
 			interrupt-parent = <&gpio>;
-			interrupts = <72 0x04>; /* gpio PJ0 */
+			interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
 
 			vsys1-supply = <&vdd_ac_bat_reg>;
 			vsys2-supply = <&vdd_ac_bat_reg>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 6cd6d41..c376a12 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -21,18 +22,19 @@
 		      <0x50042000 0x1000>,
 		      <0x50044000 0x2000>,
 		      <0x50046000 0x2000>;
-		interrupts = <1 9 0xf04>;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	timer at 60005000 {
 		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
-		interrupts = <0 0 0x04
-			      0 1 0x04
-			      0 41 0x04
-			      0 42 0x04
-			      0 121 0x04
-			      0 122 0x04>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 5>;
 	};
 
@@ -45,38 +47,38 @@
 	apbdma: dma {
 		compatible = "nvidia,tegra114-apbdma";
 		reg = <0x6000a000 0x1400>;
-		interrupts = <0 104 0x04
-			      0 105 0x04
-			      0 106 0x04
-			      0 107 0x04
-			      0 108 0x04
-			      0 109 0x04
-			      0 110 0x04
-			      0 111 0x04
-			      0 112 0x04
-			      0 113 0x04
-			      0 114 0x04
-			      0 115 0x04
-			      0 116 0x04
-			      0 117 0x04
-			      0 118 0x04
-			      0 119 0x04
-			      0 128 0x04
-			      0 129 0x04
-			      0 130 0x04
-			      0 131 0x04
-			      0 132 0x04
-			      0 133 0x04
-			      0 134 0x04
-			      0 135 0x04
-			      0 136 0x04
-			      0 137 0x04
-			      0 138 0x04
-			      0 139 0x04
-			      0 140 0x04
-			      0 141 0x04
-			      0 142 0x04
-			      0 143 0x04>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 34>;
 	};
 
@@ -88,14 +90,14 @@
 	gpio: gpio {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-		interrupts = <0 32 0x04
-			      0 33 0x04
-			      0 34 0x04
-			      0 35 0x04
-			      0 55 0x04
-			      0 87 0x04
-			      0 89 0x04
-			      0 125 0x04>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		#interrupt-cells = <2>;
@@ -120,7 +122,7 @@
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
-		interrupts = <0 36 0x04>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		status = "disabled";
 		clocks = <&tegra_car 6>;
@@ -130,7 +132,7 @@
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
-		interrupts = <0 37 0x04>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		status = "disabled";
 		clocks = <&tegra_car 192>;
@@ -140,7 +142,7 @@
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 46 0x04>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		status = "disabled";
 		clocks = <&tegra_car 55>;
@@ -150,7 +152,7 @@
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 90 0x04>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		status = "disabled";
 		clocks = <&tegra_car 65>;
@@ -167,7 +169,7 @@
 	i2c at 7000c000 {
 		compatible = "nvidia,tegra114-i2c";
 		reg = <0x7000c000 0x100>;
-		interrupts = <0 38 0x04>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 12>;
@@ -178,7 +180,7 @@
 	i2c at 7000c400 {
 		compatible = "nvidia,tegra114-i2c";
 		reg = <0x7000c400 0x100>;
-		interrupts = <0 84 0x04>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 54>;
@@ -189,7 +191,7 @@
 	i2c at 7000c500 {
 		compatible = "nvidia,tegra114-i2c";
 		reg = <0x7000c500 0x100>;
-		interrupts = <0 92 0x04>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 67>;
@@ -200,7 +202,7 @@
 	i2c at 7000c700 {
 		compatible = "nvidia,tegra114-i2c";
 		reg = <0x7000c700 0x100>;
-		interrupts = <0 120 0x04>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 103>;
@@ -211,7 +213,7 @@
 	i2c at 7000d000 {
 		compatible = "nvidia,tegra114-i2c";
 		reg = <0x7000d000 0x100>;
-		interrupts = <0 53 0x04>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 47>;
@@ -222,7 +224,7 @@
 	spi at 7000d400 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d400 0x200>;
-		interrupts = <0 59 0x04>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -234,7 +236,7 @@
 	spi at 7000d600 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d600 0x200>;
-		interrupts = <0 82 0x04>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -246,7 +248,7 @@
 	spi at 7000d800 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d800 0x200>;
-		interrupts = <0 83 0x04>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -258,7 +260,7 @@
 	spi at 7000da00 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000da00 0x200>;
-		interrupts = <0 93 0x04>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -270,7 +272,7 @@
 	spi at 7000dc00 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000dc00 0x200>;
-		interrupts = <0 94 0x04>;
+		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -282,7 +284,7 @@
 	spi at 7000de00 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000de00 0x200>;
-		interrupts = <0 79 0x04>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -294,14 +296,14 @@
 	rtc {
 		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
-		interrupts = <0 2 0x04>;
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 4>;
 	};
 
 	kbc {
 		compatible = "nvidia,tegra114-kbc";
 		reg = <0x7000e200 0x100>;
-		interrupts = <0 85 0x04>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 36>;
 		status = "disabled";
 	};
@@ -327,7 +329,7 @@
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-		interrupts = <0 14 0x04>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 14>;
 		status = "disable";
 	};
@@ -335,7 +337,7 @@
 	sdhci at 78000200 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000200 0x200>;
-		interrupts = <0 15 0x04>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 9>;
 		status = "disable";
 	};
@@ -343,7 +345,7 @@
 	sdhci at 78000400 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000400 0x200>;
-		interrupts = <0 19 0x04>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 69>;
 		status = "disable";
 	};
@@ -351,7 +353,7 @@
 	sdhci at 78000600 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000600 0x200>;
-		interrupts = <0 31 0x04>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 15>;
 		status = "disable";
 	};
@@ -387,9 +389,14 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 0xf08>,
-			     <1 14 0xf08>,
-			     <1 11 0xf08>,
-			     <1 10 0xf08>;
+		interrupts =
+			<GIC_PPI 13
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index f5be14c..be008f7 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -218,7 +218,7 @@
 		pmic: tps6586x at 34 {
 			compatible = "ti,tps6586x";
 			reg = <0x34>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			ti,system-power-controller;
 
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 3cce7b0..acbba40 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -263,7 +263,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -291,7 +291,7 @@
 		pmic: tps6586x at 34 {
 			compatible = "ti,tps6586x";
 			reg = <0x34>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			ti,system-power-controller;
 
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 3adfbfe..85d5792 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -15,7 +15,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index d2b631d..66f245a 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -271,7 +271,7 @@
 	nvec {
 		compatible = "nvidia,nvec";
 		reg = <0x7000c500 0x100>;
-		interrupts = <0 92 0x04>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clock-frequency = <80000>;
@@ -288,7 +288,7 @@
 		pmic: tps6586x at 34 {
 			compatible = "ti,tps6586x";
 			reg = <0x34>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			#gpio-cells = <2>;
 			gpio-controller;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 3d8e69b..3374e16 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 519ae6b..4d52f64e 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -314,7 +314,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -329,14 +329,14 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
+			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		gyrometer at 68 {
 			compatible = "invn,mpu3050";
 			reg = <0x68>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
+			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
 
@@ -389,7 +389,7 @@
 		pmic: tps6586x at 34 {
 			compatible = "ti,tps6586x";
 			reg = <0x34>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			ti,system-power-controller;
 
@@ -512,7 +512,7 @@
 			compatible = "ak,ak8975";
 			reg = <0xc>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(N, 5) 0x04>;
+			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 78d50a3..1d7382c 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -322,7 +322,7 @@
 		pmic: tps6586x at 34 {
 			compatible = "ti,tps6586x";
 			reg = <0x34>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			ti,system-power-controller;
 
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index db58bb7..9eaa962 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 60eb5a3..33ec764 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -311,7 +311,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -326,7 +326,7 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
+			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
 
@@ -372,7 +372,7 @@
 		pmic: tps6586x at 34 {
 			compatible = "ti,tps6586x";
 			reg = <0x34>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			ti,system-power-controller;
 
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 010f481..d6cb373 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -282,7 +282,7 @@
 		max8907 at 3c {
 			compatible = "maxim,max8907";
 			reg = <0x3c>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
 			maxim,system-power-controller;
 
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c6ceb8a..0500179 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -17,8 +18,8 @@
 	host1x {
 		compatible = "nvidia,tegra20-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
-		interrupts = <0 65 0x04   /* mpcore syncpt */
-			      0 67 0x04>; /* mpcore general */
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car 28>;
 
 		#address-cells = <1>;
@@ -29,35 +30,35 @@
 		mpe {
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
-			interrupts = <0 68 0x04>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 60>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
-			interrupts = <0 69 0x04>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 100>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
-			interrupts = <0 70 0x04>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 19>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
-			interrupts = <0 71 0x04>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 23>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
-			interrupts = <0 72 0x04>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 21>;
 		};
 
@@ -70,7 +71,7 @@
 		dc at 54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
-			interrupts = <0 73 0x04>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 27>, <&tegra_car 121>;
 			clock-names = "disp1", "parent";
 
@@ -82,7 +83,7 @@
 		dc at 54240000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
-			interrupts = <0 74 0x04>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 26>, <&tegra_car 121>;
 			clock-names = "disp2", "parent";
 
@@ -94,7 +95,7 @@
 		hdmi {
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
-			interrupts = <0 75 0x04>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 51>, <&tegra_car 117>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
@@ -103,7 +104,7 @@
 		tvo {
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
-			interrupts = <0 76 0x04>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 102>;
 			status = "disabled";
 		};
@@ -119,7 +120,8 @@
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
-		interrupts = <1 13 0x304>;
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		clocks = <&tegra_car 132>;
 	};
 
@@ -143,10 +145,10 @@
 	timer at 60005000 {
 		compatible = "nvidia,tegra20-timer";
 		reg = <0x60005000 0x60>;
-		interrupts = <0 0 0x04
-			      0 1 0x04
-			      0 41 0x04
-			      0 42 0x04>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 5>;
 	};
 
@@ -159,22 +161,22 @@
 	apbdma: dma {
 		compatible = "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1200>;
-		interrupts = <0 104 0x04
-			      0 105 0x04
-			      0 106 0x04
-			      0 107 0x04
-			      0 108 0x04
-			      0 109 0x04
-			      0 110 0x04
-			      0 111 0x04
-			      0 112 0x04
-			      0 113 0x04
-			      0 114 0x04
-			      0 115 0x04
-			      0 116 0x04
-			      0 117 0x04
-			      0 118 0x04
-			      0 119 0x04>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 34>;
 	};
 
@@ -186,13 +188,13 @@
 	gpio: gpio {
 		compatible = "nvidia,tegra20-gpio";
 		reg = <0x6000d000 0x1000>;
-		interrupts = <0 32 0x04
-			      0 33 0x04
-			      0 34 0x04
-			      0 35 0x04
-			      0 55 0x04
-			      0 87 0x04
-			      0 89 0x04>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		#interrupt-cells = <2>;
@@ -215,7 +217,7 @@
 	tegra_ac97: ac97 {
 		compatible = "nvidia,tegra20-ac97";
 		reg = <0x70002000 0x200>;
-		interrupts = <0 81 0x04>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car 3>;
 		status = "disabled";
@@ -224,7 +226,7 @@
 	tegra_i2s1: i2s at 70002800 {
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002800 0x200>;
-		interrupts = <0 13 0x04>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car 11>;
 		status = "disabled";
@@ -233,7 +235,7 @@
 	tegra_i2s2: i2s at 70002a00 {
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002a00 0x200>;
-		interrupts = <0 3 0x04>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car 18>;
 		status = "disabled";
@@ -250,7 +252,7 @@
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
-		interrupts = <0 36 0x04>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car 6>;
 		status = "disabled";
@@ -260,7 +262,7 @@
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
-		interrupts = <0 37 0x04>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car 96>;
 		status = "disabled";
@@ -270,7 +272,7 @@
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 46 0x04>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car 55>;
 		status = "disabled";
@@ -280,7 +282,7 @@
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 90 0x04>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car 65>;
 		status = "disabled";
@@ -290,7 +292,7 @@
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 91 0x04>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car 66>;
 		status = "disabled";
@@ -307,14 +309,14 @@
 	rtc {
 		compatible = "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
-		interrupts = <0 2 0x04>;
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 4>;
 	};
 
 	i2c at 7000c000 {
 		compatible = "nvidia,tegra20-i2c";
 		reg = <0x7000c000 0x100>;
-		interrupts = <0 38 0x04>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 12>, <&tegra_car 124>;
@@ -325,7 +327,7 @@
 	spi at 7000c380 {
 		compatible = "nvidia,tegra20-sflash";
 		reg = <0x7000c380 0x80>;
-		interrupts = <0 39 0x04>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -336,7 +338,7 @@
 	i2c at 7000c400 {
 		compatible = "nvidia,tegra20-i2c";
 		reg = <0x7000c400 0x100>;
-		interrupts = <0 84 0x04>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 54>, <&tegra_car 124>;
@@ -347,7 +349,7 @@
 	i2c at 7000c500 {
 		compatible = "nvidia,tegra20-i2c";
 		reg = <0x7000c500 0x100>;
-		interrupts = <0 92 0x04>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 67>, <&tegra_car 124>;
@@ -358,7 +360,7 @@
 	i2c at 7000d000 {
 		compatible = "nvidia,tegra20-i2c-dvc";
 		reg = <0x7000d000 0x200>;
-		interrupts = <0 53 0x04>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 47>, <&tegra_car 124>;
@@ -369,7 +371,7 @@
 	spi at 7000d400 {
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
-		interrupts = <0 59 0x04>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -380,7 +382,7 @@
 	spi at 7000d600 {
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
-		interrupts = <0 82 0x04>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -391,7 +393,7 @@
 	spi at 7000d800 {
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
-		interrupts = <0 83 0x04>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -402,7 +404,7 @@
 	spi at 7000da00 {
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
-		interrupts = <0 93 0x04>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -413,7 +415,7 @@
 	kbc {
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
-		interrupts = <0 85 0x04>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 36>;
 		status = "disabled";
 	};
@@ -429,7 +431,7 @@
 		compatible = "nvidia,tegra20-mc";
 		reg = <0x7000f000 0x024
 		       0x7000f03c 0x3c4>;
-		interrupts = <0 77 0x04>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	iommu {
@@ -448,7 +450,7 @@
 	usb at c5000000 {
 		compatible = "nvidia,tegra20-ehci", "usb-ehci";
 		reg = <0xc5000000 0x4000>;
-		interrupts = <0 20 0x04>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
 		clocks = <&tegra_car 22>;
@@ -469,7 +471,7 @@
 	usb at c5004000 {
 		compatible = "nvidia,tegra20-ehci", "usb-ehci";
 		reg = <0xc5004000 0x4000>;
-		interrupts = <0 21 0x04>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car 58>;
 		nvidia,phy = <&phy2>;
@@ -487,7 +489,7 @@
 	usb at c5008000 {
 		compatible = "nvidia,tegra20-ehci", "usb-ehci";
 		reg = <0xc5008000 0x4000>;
-		interrupts = <0 97 0x04>;
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car 59>;
 		nvidia,phy = <&phy3>;
@@ -505,7 +507,7 @@
 	sdhci at c8000000 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
-		interrupts = <0 14 0x04>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 14>;
 		status = "disabled";
 	};
@@ -513,7 +515,7 @@
 	sdhci at c8000200 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000200 0x200>;
-		interrupts = <0 15 0x04>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 9>;
 		status = "disabled";
 	};
@@ -521,7 +523,7 @@
 	sdhci at c8000400 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000400 0x200>;
-		interrupts = <0 19 0x04>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 69>;
 		status = "disabled";
 	};
@@ -529,7 +531,7 @@
 	sdhci at c8000600 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000600 0x200>;
-		interrupts = <0 31 0x04>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 15>;
 		status = "disabled";
 	};
@@ -553,7 +555,7 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 56 0x04
-			      0 57 0x04>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index a11e375..47b0865 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -133,7 +133,7 @@
 			compatible = "ti,tps65911";
 			reg = <0x2d>;
 
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index c177fd9..43f0139 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -146,7 +146,7 @@
 			compatible = "isil,isl29028";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(L, 0) 0x04>;
+			interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
 
@@ -163,7 +163,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(W, 3) 0x04>;
+			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -190,7 +190,7 @@
 			compatible = "ti,tps65911";
 			reg = <0x2d>;
 
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 1fe8c3a..329465a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -17,8 +18,8 @@
 	host1x {
 		compatible = "nvidia,tegra30-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
-		interrupts = <0 65 0x04   /* mpcore syncpt */
-			      0 67 0x04>; /* mpcore general */
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car 28>;
 
 		#address-cells = <1>;
@@ -29,35 +30,35 @@
 		mpe {
 			compatible = "nvidia,tegra30-mpe";
 			reg = <0x54040000 0x00040000>;
-			interrupts = <0 68 0x04>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 60>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra30-vi";
 			reg = <0x54080000 0x00040000>;
-			interrupts = <0 69 0x04>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 164>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra30-epp";
 			reg = <0x540c0000 0x00040000>;
-			interrupts = <0 70 0x04>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 19>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra30-isp";
 			reg = <0x54100000 0x00040000>;
-			interrupts = <0 71 0x04>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 23>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
-			interrupts = <0 72 0x04>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 21>;
 		};
 
@@ -71,7 +72,7 @@
 		dc at 54200000 {
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54200000 0x00040000>;
-			interrupts = <0 73 0x04>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 27>, <&tegra_car 179>;
 			clock-names = "disp1", "parent";
 
@@ -83,7 +84,7 @@
 		dc at 54240000 {
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54240000 0x00040000>;
-			interrupts = <0 74 0x04>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 26>, <&tegra_car 179>;
 			clock-names = "disp2", "parent";
 
@@ -95,7 +96,7 @@
 		hdmi {
 			compatible = "nvidia,tegra30-hdmi";
 			reg = <0x54280000 0x00040000>;
-			interrupts = <0 75 0x04>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 51>, <&tegra_car 189>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
@@ -104,7 +105,7 @@
 		tvo {
 			compatible = "nvidia,tegra30-tvo";
 			reg = <0x542c0000 0x00040000>;
-			interrupts = <0 76 0x04>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car 169>;
 			status = "disabled";
 		};
@@ -120,7 +121,8 @@
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
-		interrupts = <1 13 0xf04>;
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		clocks = <&tegra_car 214>;
 	};
 
@@ -144,12 +146,12 @@
 	timer at 60005000 {
 		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
-		interrupts = <0 0 0x04
-			      0 1 0x04
-			      0 41 0x04
-			      0 42 0x04
-			      0 121 0x04
-			      0 122 0x04>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 5>;
 	};
 
@@ -162,38 +164,38 @@
 	apbdma: dma {
 		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1400>;
-		interrupts = <0 104 0x04
-			      0 105 0x04
-			      0 106 0x04
-			      0 107 0x04
-			      0 108 0x04
-			      0 109 0x04
-			      0 110 0x04
-			      0 111 0x04
-			      0 112 0x04
-			      0 113 0x04
-			      0 114 0x04
-			      0 115 0x04
-			      0 116 0x04
-			      0 117 0x04
-			      0 118 0x04
-			      0 119 0x04
-			      0 128 0x04
-			      0 129 0x04
-			      0 130 0x04
-			      0 131 0x04
-			      0 132 0x04
-			      0 133 0x04
-			      0 134 0x04
-			      0 135 0x04
-			      0 136 0x04
-			      0 137 0x04
-			      0 138 0x04
-			      0 139 0x04
-			      0 140 0x04
-			      0 141 0x04
-			      0 142 0x04
-			      0 143 0x04>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 34>;
 	};
 
@@ -205,14 +207,14 @@
 	gpio: gpio {
 		compatible = "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-		interrupts = <0 32 0x04
-			      0 33 0x04
-			      0 34 0x04
-			      0 35 0x04
-			      0 55 0x04
-			      0 87 0x04
-			      0 89 0x04
-			      0 125 0x04>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		#interrupt-cells = <2>;
@@ -237,7 +239,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
-		interrupts = <0 36 0x04>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car 6>;
 		status = "disabled";
@@ -247,7 +249,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
-		interrupts = <0 37 0x04>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car 160>;
 		status = "disabled";
@@ -257,7 +259,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 46 0x04>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car 55>;
 		status = "disabled";
@@ -267,7 +269,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 90 0x04>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car 65>;
 		status = "disabled";
@@ -277,7 +279,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
-		interrupts = <0 91 0x04>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car 66>;
 		status = "disabled";
@@ -294,14 +296,14 @@
 	rtc {
 		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
-		interrupts = <0 2 0x04>;
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 4>;
 	};
 
 	i2c at 7000c000 {
 		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 		reg = <0x7000c000 0x100>;
-		interrupts = <0 38 0x04>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 12>, <&tegra_car 182>;
@@ -312,7 +314,7 @@
 	i2c at 7000c400 {
 		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 		reg = <0x7000c400 0x100>;
-		interrupts = <0 84 0x04>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 54>, <&tegra_car 182>;
@@ -323,7 +325,7 @@
 	i2c at 7000c500 {
 		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 		reg = <0x7000c500 0x100>;
-		interrupts = <0 92 0x04>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 67>, <&tegra_car 182>;
@@ -334,7 +336,7 @@
 	i2c at 7000c700 {
 		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 		reg = <0x7000c700 0x100>;
-		interrupts = <0 120 0x04>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 103>, <&tegra_car 182>;
@@ -345,7 +347,7 @@
 	i2c at 7000d000 {
 		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 		reg = <0x7000d000 0x100>;
-		interrupts = <0 53 0x04>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car 47>, <&tegra_car 182>;
@@ -356,7 +358,7 @@
 	spi at 7000d400 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
-		interrupts = <0 59 0x04>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -367,7 +369,7 @@
 	spi at 7000d600 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
-		interrupts = <0 82 0x04>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -378,7 +380,7 @@
 	spi at 7000d800 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
-		interrupts = <0 83 0x04>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -389,7 +391,7 @@
 	spi at 7000da00 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
-		interrupts = <0 93 0x04>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -400,7 +402,7 @@
 	spi at 7000dc00 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000dc00 0x200>;
-		interrupts = <0 94 0x04>;
+		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -411,7 +413,7 @@
 	spi at 7000de00 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000de00 0x200>;
-		interrupts = <0 79 0x04>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -422,7 +424,7 @@
 	kbc {
 		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
-		interrupts = <0 85 0x04>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 36>;
 		status = "disabled";
 	};
@@ -440,7 +442,7 @@
 		       0x7000f03c 0x1b4
 		       0x7000f200 0x028
 		       0x7000f284 0x17c>;
-		interrupts = <0 77 0x04>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	iommu {
@@ -457,7 +459,7 @@
 		compatible = "nvidia,tegra30-ahub";
 		reg = <0x70080000 0x200
 		       0x70080200 0x100>;
-		interrupts = <0 103 0x04>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
 			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
@@ -514,7 +516,7 @@
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000000 0x200>;
-		interrupts = <0 14 0x04>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 14>;
 		status = "disabled";
 	};
@@ -522,7 +524,7 @@
 	sdhci at 78000200 {
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000200 0x200>;
-		interrupts = <0 15 0x04>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 9>;
 		status = "disabled";
 	};
@@ -530,7 +532,7 @@
 	sdhci at 78000400 {
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000400 0x200>;
-		interrupts = <0 19 0x04>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 69>;
 		status = "disabled";
 	};
@@ -538,7 +540,7 @@
 	sdhci at 78000600 {
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000600 0x200>;
-		interrupts = <0 31 0x04>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car 15>;
 		status = "disabled";
 	};
@@ -574,9 +576,9 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 144 0x04
-			      0 145 0x04
-			      0 146 0x04
-			      0 147 0x04>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
-- 
1.7.10.4



From sboyd at codeaurora.org  Mon May 13 15:26:06 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:06 -0700
Subject: [PATCHv6 02/11] clocksource: add generic dummy timer driver
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-3-git-send-email-sboyd@codeaurora.org>

From: Mark Rutland <mark.rutland at arm.com>

Several architectures have a dummy timer driver tightly coupled with
their broadcast code to support machines without cpu-local timers (or
where there is a lack of driver support).

Since 12ad100046: "clockevents: Add generic timer broadcast function"
it's been possible to write broadcast-capable timer drivers decoupled
from the broadcast mechanism. We can use this functionality to implement
a generic dummy timer driver that can be shared by all architectures
with generic tick broadcast (ARCH_HAS_TICK_BROADCAST).

This patch implements a generic dummy timer using this facility.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Cc: John Stultz <john.stultz at linaro.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
[sboyd: Make percpu data static, use __this_cpu_ptr(), move to
        early_initcall to properly register on each CPU, only
	register if more than one CPU possible]
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/Makefile      |  1 +
 drivers/clocksource/dummy_timer.c | 69 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 drivers/clocksource/dummy_timer.c

diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c7..1a17d76 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
+obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST)	+= dummy_timer.o
diff --git a/drivers/clocksource/dummy_timer.c b/drivers/clocksource/dummy_timer.c
new file mode 100644
index 0000000..1f55f96
--- /dev/null
+++ b/drivers/clocksource/dummy_timer.c
@@ -0,0 +1,69 @@
+/*
+ *  linux/drivers/clocksource/dummy_timer.c
+ *
+ *  Copyright (C) 2013 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/cpumask.h>
+
+static DEFINE_PER_CPU(struct clock_event_device, dummy_timer_evt);
+
+static void dummy_timer_set_mode(enum clock_event_mode mode,
+			   struct clock_event_device *evt)
+{
+	/*
+	 * Core clockevents code will call this when exchanging timer devices.
+	 * We don't need to do anything here.
+	 */
+}
+
+static void __cpuinit dummy_timer_setup(void)
+{
+	int cpu = smp_processor_id();
+	struct clock_event_device *evt = __this_cpu_ptr(&dummy_timer_evt);
+
+	evt->name	= "dummy_timer";
+	evt->features	= CLOCK_EVT_FEAT_PERIODIC |
+			  CLOCK_EVT_FEAT_ONESHOT |
+			  CLOCK_EVT_FEAT_DUMMY;
+	evt->rating	= 100;
+	evt->set_mode	= dummy_timer_set_mode;
+	evt->cpumask	= cpumask_of(cpu);
+
+	clockevents_register_device(evt);
+}
+
+static int __cpuinit dummy_timer_cpu_notify(struct notifier_block *self,
+				      unsigned long action, void *hcpu)
+{
+	if ((action & ~CPU_TASKS_FROZEN) == CPU_STARTING)
+		dummy_timer_setup();
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block dummy_timer_cpu_nb __cpuinitdata = {
+	.notifier_call = dummy_timer_cpu_notify,
+};
+
+static int __init dummy_timer_register(void)
+{
+	int err = register_cpu_notifier(&dummy_timer_cpu_nb);
+	if (err)
+		return err;
+
+	/* We won't get a call on the boot CPU, so register immediately */
+	if (num_possible_cpus() > 1)
+		dummy_timer_setup();
+
+	return 0;
+}
+early_initcall(dummy_timer_register);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:05 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:05 -0700
Subject: [PATCHv6 01/11] clockevents: Prefer CPU local devices over global
 devices
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-2-git-send-email-sboyd@codeaurora.org>

On an SMP system with only one global clockevent and a dummy
clockevent per CPU we run into problems. We want the dummy
clockevents to be registered as the per CPU tick devices, but
we can only achieve that if we register the dummy clockevents
before the global clockevent or if we artificially inflate the
rating of the dummy clockevents to be higher than the rating
of the global clockevent. Failure to do so leads to boot
hangs when the dummy timers are registered on all other CPUs
besides the CPU that accepted the global clockevent as its tick
device and there is no broadcast timer to poke the dummy
devices.

If we're registering multiple clockevents and one clockevent is
global and the other is local to a particular CPU we should
choose to use the local clockevent regardless of the rating of
the device. This way, if the clockevent is a dummy it will take
the tick device duty as long as there isn't a higher rated tick
device and any global clockevent will be bumped out into
broadcast mode, fixing the problem described above.

Reported-by: Mark Rutland <mark.rutland at arm.com>
Tested-by: Mark Rutland <mark.rutland at arm.com>
Cc: John Stultz <john.stultz at linaro.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 kernel/time/tick-common.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/kernel/time/tick-common.c b/kernel/time/tick-common.c
index 5d3fb10..3da62de 100644
--- a/kernel/time/tick-common.c
+++ b/kernel/time/tick-common.c
@@ -254,9 +254,10 @@ static int tick_check_new_device(struct clock_event_device *newdev)
 		    !(newdev->features & CLOCK_EVT_FEAT_ONESHOT))
 			goto out_bc;
 		/*
-		 * Check the rating
+		 * Check the rating, but prefer CPU local devices
 		 */
-		if (curdev->rating >= newdev->rating)
+		if (curdev->rating >= newdev->rating &&
+		    cpumask_equal(curdev->cpumask, newdev->cpumask))
 			goto out_bc;
 	}
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:07 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:07 -0700
Subject: [PATCHv6 03/11] ARM: smp: Remove duplicate dummy timer implementation
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-4-git-send-email-sboyd@codeaurora.org>

Drop ARM's version of the dummy timer now that we have a generic
implementation in drivers/clocksource.

Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/kernel/smp.c | 22 ++--------------------
 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 47ab905..4dc883a 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -503,24 +503,6 @@ void tick_broadcast(const struct cpumask *mask)
 }
 #endif
 
-static void broadcast_timer_set_mode(enum clock_event_mode mode,
-	struct clock_event_device *evt)
-{
-}
-
-static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
-{
-	evt->name	= "dummy_timer";
-	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
-			  CLOCK_EVT_FEAT_PERIODIC |
-			  CLOCK_EVT_FEAT_DUMMY;
-	evt->rating	= 100;
-	evt->mult	= 1;
-	evt->set_mode	= broadcast_timer_set_mode;
-
-	clockevents_register_device(evt);
-}
-
 static struct local_timer_ops *lt_ops;
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -544,8 +526,8 @@ static void __cpuinit percpu_timer_setup(void)
 
 	evt->cpumask = cpumask_of(cpu);
 
-	if (!lt_ops || lt_ops->setup(evt))
-		broadcast_timer_setup(evt);
+	if (lt_ops)
+		lt_ops->setup(evt);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:04 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:04 -0700
Subject: [PATCHv6 00/11] Remove ARM local timer API
Message-ID: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>

In light of Mark Rutland's recent work on divorcing the ARM architected
timers from the ARM local timer API and introducing a generic arch hook for
broadcast it seems that we should remove the local timer API entirely.
Doing so will reduce the architecture dependencies of our timer drivers,
reduce code in ARM core, and simplify timer drivers because they no longer
go through an architecture layer that is essentially a hotplug notifier.

Previous attempts have been made[1] unsuccessfully. I'm hoping this can
be accepted now so that we can clean up the timer drivers that are
used in both UP and SMP situations. Right now these drivers have to ignore
the timer setup callback on the boot CPU to avoid registering clockevents
twice. This is not very symmetric and causes convuluted code that does
the same thing in two places.

Patches based on next-20130418

I'm still looking for Acks/Tested-by on EXYNOS and PRIMA2.

[1] http://article.gmane.org/gmane.linux.ports.arm.kernel/145705

Note: A hotplug notifier is used by both x86 for the apb_timer (see 
apbt_cpuhp_notify) and by metag (see arch_timer_cpu_notify in
metag_generic.c) so this is not new.

Changes since v5:
 * Rebased onto v3.10-rc1
 * Rebase caused minor updates to mct patch

Changes since v4:
 * Rebased onto next-20130418
 * Rebase caused minor updates to mct patch and twd Kconfig

Changes since v3:
 * New patch to fix SMP with dummy timers registered after a global timer
 * Push this_cpu_ptr lower to avoid preemptible false positive warnings
 * Collected acks/tested-bys

Changes since v2:
 * Bug fixes in smp_twd from Tony Lindgren's testing
 * Move smp_twd to use late_time_init hook
 * Collected Acks

Changes since v1:
 * Picked up Mark's generic dummy timer driver
 * Split out omap changes into new patch

Mark Rutland (1):
  clocksource: add generic dummy timer driver

Stephen Boyd (10):
  clockevents: Prefer CPU local devices over global devices
  ARM: smp: Remove duplicate dummy timer implementation
  ARM: smp_twd: Divorce smp_twd from local timer API
  ARM: OMAP2+: Divorce from local timer API
  ARM: EXYNOS4: Divorce mct from local timer API
  ARM: PRIMA2: Divorce timer-marco from local timer API
  ARM: msm: Divorce msm_timer from local timer API
  clocksource: time-armada-370-xp: Fix sparse warning
  clocksource: time-armada-370-xp: Divorce from local timer API
  ARM: smp: Remove local timer API

 arch/arm/Kconfig                         |  12 +--
 arch/arm/include/asm/localtimer.h        |  34 ---------
 arch/arm/kernel/smp.c                    |  87 ---------------------
 arch/arm/kernel/smp_twd.c                |  64 ++++++++++------
 arch/arm/mach-highbank/Kconfig           |   2 +-
 arch/arm/mach-imx/Kconfig                |   2 +-
 arch/arm/mach-msm/timer.c                | 126 +++++++++++++++++--------------
 arch/arm/mach-omap2/Kconfig              |   3 +-
 arch/arm/mach-omap2/timer.c              |   7 --
 arch/arm/mach-realview/Kconfig           |   8 +-
 arch/arm/mach-spear/Kconfig              |   2 +-
 arch/arm/mach-tegra/Kconfig              |   2 +-
 arch/arm/mach-ux500/Kconfig              |   2 +-
 arch/arm/mach-vexpress/Kconfig           |   2 +-
 arch/arm/mach-zynq/Kconfig               |   2 +-
 drivers/clocksource/Makefile             |   1 +
 drivers/clocksource/dummy_timer.c        |  69 +++++++++++++++++
 drivers/clocksource/exynos_mct.c         |  60 ++++++++++-----
 drivers/clocksource/time-armada-370-xp.c |  92 +++++++++++-----------
 drivers/clocksource/timer-marco.c        | 100 +++++++++++++-----------
 include/linux/time-armada-370-xp.h       |   4 +-
 kernel/time/tick-common.c                |   5 +-
 22 files changed, 340 insertions(+), 346 deletions(-)
 delete mode 100644 arch/arm/include/asm/localtimer.h
 create mode 100644 drivers/clocksource/dummy_timer.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:12 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:12 -0700
Subject: [PATCHv6 08/11] ARM: msm: Divorce msm_timer from local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-9-git-send-email-sboyd@codeaurora.org>

Separate the msm_timer from the local timer API. This will allow
us to remove ARM local timer support in the near future and gets
us closer to moving this driver to drivers/clocksource.

Acked-by: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/timer.c | 126 +++++++++++++++++++++++++---------------------
 1 file changed, 70 insertions(+), 56 deletions(-)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 284313f..df947aa 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -16,6 +16,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -25,7 +26,6 @@
 #include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
-#include <asm/localtimer.h>
 #include <asm/sched_clock.h>
 
 #include "common.h"
@@ -49,7 +49,7 @@ static void __iomem *sts_base;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
-	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+	struct clock_event_device *evt = dev_id;
 	/* Stop the timer tick */
 	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
 		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
@@ -101,18 +101,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
 	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 }
 
-static struct clock_event_device msm_clockevent = {
-	.name		= "gp_timer",
-	.features	= CLOCK_EVT_FEAT_ONESHOT,
-	.rating		= 200,
-	.set_next_event	= msm_timer_set_next_event,
-	.set_mode	= msm_timer_set_mode,
-};
-
-static union {
-	struct clock_event_device *evt;
-	struct clock_event_device * __percpu *percpu_evt;
-} msm_evt;
+static struct clock_event_device __percpu *msm_evt;
 
 static void __iomem *source_base;
 
@@ -138,37 +127,65 @@ static struct clocksource msm_clocksource = {
 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-#ifdef CONFIG_LOCAL_TIMERS
+static int msm_timer_irq;
+static int msm_timer_has_ppi;
+
 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 {
-	/* Use existing clock_event for cpu 0 */
-	if (!smp_processor_id())
-		return 0;
-
-	evt->irq = msm_clockevent.irq;
-	evt->name = "local_timer";
-	evt->features = msm_clockevent.features;
-	evt->rating = msm_clockevent.rating;
+	int cpu = smp_processor_id();
+	int err;
+
+	evt->irq = msm_timer_irq;
+	evt->name = "msm_timer";
+	evt->features = CLOCK_EVT_FEAT_ONESHOT;
+	evt->rating = 200;
 	evt->set_mode = msm_timer_set_mode;
 	evt->set_next_event = msm_timer_set_next_event;
+	evt->cpumask = cpumask_of(cpu);
+
+	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
+
+	if (msm_timer_has_ppi) {
+		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
+	} else {
+		err = request_irq(evt->irq, msm_timer_interrupt,
+				IRQF_TIMER | IRQF_NOBALANCING |
+				IRQF_TRIGGER_RISING, "gp_timer", evt);
+		if (err)
+			pr_err("request_irq failed\n");
+	}
 
-	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
-	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
-	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
 	return 0;
 }
 
-static void msm_local_timer_stop(struct clock_event_device *evt)
+static void __cpuinit msm_local_timer_stop(struct clock_event_device *evt)
 {
 	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 	disable_percpu_irq(evt->irq);
 }
 
-static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
-	.setup	= msm_local_timer_setup,
-	.stop	= msm_local_timer_stop,
+static int __cpuinit msm_timer_cpu_notify(struct notifier_block *self,
+					   unsigned long action, void *hcpu)
+{
+	/*
+	 * Grab cpu pointer in each case to avoid spurious
+	 * preemptible warnings
+	 */
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_STARTING:
+		msm_local_timer_setup(this_cpu_ptr(msm_evt));
+		break;
+	case CPU_DYING:
+		msm_local_timer_stop(this_cpu_ptr(msm_evt));
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block msm_timer_cpu_nb __cpuinitdata = {
+	.notifier_call = msm_timer_cpu_notify,
 };
-#endif /* CONFIG_LOCAL_TIMERS */
 
 static notrace u32 msm_sched_clock_read(void)
 {
@@ -178,38 +195,35 @@ static notrace u32 msm_sched_clock_read(void)
 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
 				  bool percpu)
 {
-	struct clock_event_device *ce = &msm_clockevent;
 	struct clocksource *cs = &msm_clocksource;
-	int res;
+	int res = 0;
+
+	msm_timer_irq = irq;
+	msm_timer_has_ppi = percpu;
+
+	msm_evt = alloc_percpu(struct clock_event_device);
+	if (!msm_evt) {
+		pr_err("memory allocation failed for clockevents\n");
+		goto err;
+	}
 
-	ce->cpumask = cpumask_of(0);
-	ce->irq = irq;
+	if (percpu)
+		res = request_percpu_irq(irq, msm_timer_interrupt,
+					 "gp_timer", msm_evt);
 
-	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
-	if (percpu) {
-		msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
-		if (!msm_evt.percpu_evt) {
-			pr_err("memory allocation failed for %s\n", ce->name);
+	if (res) {
+		pr_err("request_percpu_irq failed\n");
+	} else {
+		res = register_cpu_notifier(&msm_timer_cpu_nb);
+		if (res) {
+			free_percpu_irq(irq, msm_evt);
 			goto err;
 		}
-		*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
-		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
-					 ce->name, msm_evt.percpu_evt);
-		if (!res) {
-			enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
-#ifdef CONFIG_LOCAL_TIMERS
-			local_timer_register(&msm_local_timer_ops);
-#endif
-		}
-	} else {
-		msm_evt.evt = ce;
-		res = request_irq(ce->irq, msm_timer_interrupt,
-				  IRQF_TIMER | IRQF_NOBALANCING |
-				  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
+
+		/* Immediately configure the timer on the boot CPU */
+		msm_local_timer_setup(__this_cpu_ptr(msm_evt));
 	}
 
-	if (res)
-		pr_err("request_irq failed for %s\n", ce->name);
 err:
 	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
 	res = clocksource_register_hz(cs, dgt_hz);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:11 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:11 -0700
Subject: [PATCHv6 07/11] ARM: PRIMA2: Divorce timer-marco from local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-8-git-send-email-sboyd@codeaurora.org>

Separate the marco local timers from the local timer API. This
will allow us to remove ARM local timer support in the near future
and gets us closer to moving this driver to drivers/clocksource.

Cc: Barry Song <baohua.song at csr.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/timer-marco.c | 100 ++++++++++++++++++++------------------
 1 file changed, 54 insertions(+), 46 deletions(-)

diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index 97738db..ba97bc1 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -10,6 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
 #include <linux/clocksource.h>
+#include <linux/cpu.h>
 #include <linux/bitops.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
@@ -18,7 +19,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <asm/sched_clock.h>
-#include <asm/localtimer.h>
 #include <asm/mach/time.h>
 
 #define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
@@ -151,13 +151,7 @@ static void sirfsoc_clocksource_resume(struct clocksource *cs)
 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 }
 
-static struct clock_event_device sirfsoc_clockevent = {
-	.name = "sirfsoc_clockevent",
-	.rating = 200,
-	.features = CLOCK_EVT_FEAT_ONESHOT,
-	.set_mode = sirfsoc_timer_set_mode,
-	.set_next_event = sirfsoc_timer_set_next_event,
-};
+static struct clock_event_device __percpu *sirfsoc_clockevent;
 
 static struct clocksource sirfsoc_clocksource = {
 	.name = "sirfsoc_clocksource",
@@ -173,11 +167,8 @@ static struct irqaction sirfsoc_timer_irq = {
 	.name = "sirfsoc_timer0",
 	.flags = IRQF_TIMER | IRQF_NOBALANCING,
 	.handler = sirfsoc_timer_interrupt,
-	.dev_id = &sirfsoc_clockevent,
 };
 
-#ifdef CONFIG_LOCAL_TIMERS
-
 static struct irqaction sirfsoc_timer1_irq = {
 	.name = "sirfsoc_timer1",
 	.flags = IRQF_TIMER | IRQF_NOBALANCING,
@@ -186,56 +177,77 @@ static struct irqaction sirfsoc_timer1_irq = {
 
 static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
 {
-	/* Use existing clock_event for cpu 0 */
-	if (!smp_processor_id())
-		return 0;
+	int cpu = smp_processor_id();
+	struct irqaction *action;
+
+	if (cpu == 0)
+		action = &sirfsoc_timer_irq;
+	else
+		action = &sirfsoc_timer1_irq;
 
-	ce->irq = sirfsoc_timer1_irq.irq;
+	ce->irq = action->irq;
 	ce->name = "local_timer";
-	ce->features = sirfsoc_clockevent.features;
-	ce->rating = sirfsoc_clockevent.rating;
+	ce->features = CLOCK_EVT_FEAT_ONESHOT;
+	ce->rating = 200;
 	ce->set_mode = sirfsoc_timer_set_mode;
 	ce->set_next_event = sirfsoc_timer_set_next_event;
-	ce->shift = sirfsoc_clockevent.shift;
-	ce->mult = sirfsoc_clockevent.mult;
-	ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
-	ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
+	clockevents_calc_mult_shift(ce, CLOCK_TICK_RATE, 60);
+	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
+	ce->min_delta_ns = clockevent_delta2ns(2, ce);
+	ce->cpumask = cpumask_of(cpu);
 
-	sirfsoc_timer1_irq.dev_id = ce;
-	BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
-	irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
+	action->dev_id = ce;
+	BUG_ON(setup_irq(ce->irq, action));
+	irq_set_affinity(action->irq, cpumask_of(cpu));
 
 	clockevents_register_device(ce);
 	return 0;
 }
 
-static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
+static void __cpuinit sirfsoc_local_timer_stop(struct clock_event_device *ce)
 {
+	int cpu = smp_processor_id();
+
 	sirfsoc_timer_count_disable(1);
 
-	remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
+	if (cpu == 0)
+		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
+	else
+		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
 }
 
-static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
-	.setup	= sirfsoc_local_timer_setup,
-	.stop	= sirfsoc_local_timer_stop,
+static int __cpuinit sirfsoc_cpu_notify(struct notifier_block *self,
+					   unsigned long action, void *hcpu)
+{
+	/*
+	 * Grab cpu pointer in each case to avoid spurious
+	 * preemptible warnings
+	 */
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_STARTING:
+		sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
+		break;
+	case CPU_DYING:
+		sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block sirfsoc_cpu_nb __cpuinitdata = {
+	.notifier_call = sirfsoc_cpu_notify,
 };
-#endif /* CONFIG_LOCAL_TIMERS */
 
 static void __init sirfsoc_clockevent_init(void)
 {
-	clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
-
-	sirfsoc_clockevent.max_delta_ns =
-		clockevent_delta2ns(-2, &sirfsoc_clockevent);
-	sirfsoc_clockevent.min_delta_ns =
-		clockevent_delta2ns(2, &sirfsoc_clockevent);
-
-	sirfsoc_clockevent.cpumask = cpumask_of(0);
-	clockevents_register_device(&sirfsoc_clockevent);
-#ifdef CONFIG_LOCAL_TIMERS
-	local_timer_register(&sirfsoc_local_timer_ops);
-#endif
+	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
+	BUG_ON(!sirfsoc_clockevent);
+
+	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
+
+	/* Immediately configure the timer on the boot CPU */
+	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
 }
 
 /* initialize the kernel jiffy timer source */
@@ -273,8 +285,6 @@ static void __init sirfsoc_marco_timer_init(void)
 
 	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
 
-	BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
-
 	sirfsoc_clockevent_init();
 }
 
@@ -288,11 +298,9 @@ static void __init sirfsoc_of_timer_init(struct device_node *np)
 	if (!sirfsoc_timer_irq.irq)
 		panic("No irq passed for timer0 via DT\n");
 
-#ifdef CONFIG_LOCAL_TIMERS
 	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
 	if (!sirfsoc_timer1_irq.irq)
 		panic("No irq passed for timer1 via DT\n");
-#endif
 
 	sirfsoc_marco_timer_init();
 }
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:10 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:10 -0700
Subject: [PATCHv6 06/11] ARM: EXYNOS4: Divorce mct from local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-7-git-send-email-sboyd@codeaurora.org>

Separate the mct local timers from the local timer API. This will
allow us to remove ARM local timer support in the near future and
gets us closer to moving this driver to drivers/clocksource.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Thomas Abraham <thomas.abraham at linaro.org>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/exynos_mct.c | 60 ++++++++++++++++++++++++++++------------
 1 file changed, 43 insertions(+), 17 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 662fcc0..1c3f5a6 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -16,6 +16,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/cpu.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/percpu.h>
@@ -24,7 +25,6 @@
 #include <linux/of_address.h>
 #include <linux/clocksource.h>
 
-#include <asm/localtimer.h>
 #include <asm/mach/time.h>
 
 #define EXYNOS4_MCTREG(x)		(x)
@@ -80,7 +80,7 @@ static unsigned int mct_int_type;
 static int mct_irqs[MCT_NR_IRQS];
 
 struct mct_clock_event_device {
-	struct clock_event_device *evt;
+	struct clock_event_device evt;
 	unsigned long base;
 	char name[10];
 };
@@ -295,8 +295,6 @@ static void exynos4_clockevent_init(void)
 	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 }
 
-#ifdef CONFIG_LOCAL_TIMERS
-
 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 
 /* Clock event handling */
@@ -369,7 +367,7 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
 
 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 {
-	struct clock_event_device *evt = mevt->evt;
+	struct clock_event_device *evt = &mevt->evt;
 
 	/*
 	 * This is for supporting oneshot mode.
@@ -391,7 +389,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 {
 	struct mct_clock_event_device *mevt = dev_id;
-	struct clock_event_device *evt = mevt->evt;
+	struct clock_event_device *evt = &mevt->evt;
 
 	exynos4_mct_tick_clear(mevt);
 
@@ -417,8 +415,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 	struct mct_clock_event_device *mevt;
 	unsigned int cpu = smp_processor_id();
 
-	mevt = this_cpu_ptr(&percpu_mct_tick);
-	mevt->evt = evt;
+	mevt = container_of(evt, struct mct_clock_event_device, evt);
 
 	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 	sprintf(mevt->name, "mct_tick%d", cpu);
@@ -452,7 +449,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 	return 0;
 }
 
-static void exynos4_local_timer_stop(struct clock_event_device *evt)
+static void __cpuinit exynos4_local_timer_stop(struct clock_event_device *evt)
 {
 	unsigned int cpu = smp_processor_id();
 	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
@@ -465,14 +462,37 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
 		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 }
 
-static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
-	.setup	= exynos4_local_timer_setup,
-	.stop	= exynos4_local_timer_stop,
+static int __cpuinit exynos4_mct_cpu_notify(struct notifier_block *self,
+					   unsigned long action, void *hcpu)
+{
+	struct mct_clock_event_device *mevt;
+
+	/*
+	 * Grab cpu pointer in each case to avoid spurious
+	 * preemptible warnings
+	 */
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_STARTING:
+		mevt = this_cpu_ptr(&percpu_mct_tick);
+		exynos4_local_timer_setup(&mevt->evt);
+		break;
+	case CPU_DYING:
+		mevt = this_cpu_ptr(&percpu_mct_tick);
+		exynos4_local_timer_stop(&mevt->evt);
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block exynos4_mct_cpu_nb __cpuinitdata = {
+	.notifier_call = exynos4_mct_cpu_notify,
 };
-#endif /* CONFIG_LOCAL_TIMERS */
 
 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
 {
+	int err;
+	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 	struct clk *mct_clk, *tick_clk;
 
 	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
@@ -490,9 +510,7 @@ static void __init exynos4_timer_resources(struct device_node *np, void __iomem
 	if (!reg_base)
 		panic("%s: unable to ioremap mct address space\n", __func__);
 
-#ifdef CONFIG_LOCAL_TIMERS
 	if (mct_int_type == MCT_INT_PPI) {
-		int err;
 
 		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
 					 exynos4_mct_tick_isr, "MCT",
@@ -501,8 +519,16 @@ static void __init exynos4_timer_resources(struct device_node *np, void __iomem
 		     mct_irqs[MCT_L0_IRQ], err);
 	}
 
-	local_timer_register(&exynos4_mct_tick_ops);
-#endif /* CONFIG_LOCAL_TIMERS */
+	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
+	if (err)
+		goto out_irq;
+
+	/* Immediately configure the timer on the boot CPU */
+	exynos4_local_timer_setup(&mevt->evt);
+	return;
+
+out_irq:
+	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
 }
 
 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:08 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:08 -0700
Subject: [PATCHv6 04/11] ARM: smp_twd: Divorce smp_twd from local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-5-git-send-email-sboyd@codeaurora.org>

Separate the smp_twd timers from the local timer API. This will
allow us to remove ARM local timer support in the near future and
gets us closer to moving this driver to drivers/clocksource.

Cc: Russell King <linux at arm.linux.org.uk>
Cc: Tony Lindgren <tony at atomide.com>
Tested-by: Mark Rutland <mark.rutland at arm.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/Kconfig               |  2 +-
 arch/arm/kernel/smp_twd.c      | 64 ++++++++++++++++++++++++++++--------------
 arch/arm/mach-highbank/Kconfig |  2 +-
 arch/arm/mach-imx/Kconfig      |  2 +-
 arch/arm/mach-omap2/Kconfig    |  2 +-
 arch/arm/mach-realview/Kconfig |  8 +++---
 arch/arm/mach-spear/Kconfig    |  2 +-
 arch/arm/mach-tegra/Kconfig    |  2 +-
 arch/arm/mach-ux500/Kconfig    |  2 +-
 arch/arm/mach-vexpress/Kconfig |  2 +-
 arch/arm/mach-zynq/Kconfig     |  2 +-
 11 files changed, 56 insertions(+), 34 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..177cb39 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -636,7 +636,7 @@ config ARCH_SHMOBILE
 	select CLKDEV_LOOKUP
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_CLK
 	select HAVE_MACH_CLKDEV
 	select HAVE_SMP
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 90525d9..aac1495 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -24,7 +25,6 @@
 
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
-#include <asm/localtimer.h>
 
 /* set up by the platform code */
 static void __iomem *twd_base;
@@ -33,7 +33,7 @@ static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
 static DEFINE_PER_CPU(bool, percpu_setup_called);
 
-static struct clock_event_device __percpu **twd_evt;
+static struct clock_event_device __percpu *twd_evt;
 static int twd_ppi;
 
 static void twd_set_mode(enum clock_event_mode mode,
@@ -90,8 +90,10 @@ static int twd_timer_ack(void)
 	return 0;
 }
 
-static void twd_timer_stop(struct clock_event_device *clk)
+static void twd_timer_stop(void)
 {
+	struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
+
 	twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 	disable_percpu_irq(clk->irq);
 }
@@ -106,7 +108,7 @@ static void twd_update_frequency(void *new_rate)
 {
 	twd_timer_rate = *((unsigned long *) new_rate);
 
-	clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
+	clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
 }
 
 static int twd_rate_change(struct notifier_block *nb,
@@ -132,7 +134,7 @@ static struct notifier_block twd_clk_nb = {
 
 static int twd_clk_init(void)
 {
-	if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
+	if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
 		return clk_notifier_register(twd_clk, &twd_clk_nb);
 
 	return 0;
@@ -151,7 +153,7 @@ static void twd_update_frequency(void *data)
 {
 	twd_timer_rate = clk_get_rate(twd_clk);
 
-	clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
+	clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
 }
 
 static int twd_cpufreq_transition(struct notifier_block *nb,
@@ -177,7 +179,7 @@ static struct notifier_block twd_cpufreq_nb = {
 
 static int twd_cpufreq_init(void)
 {
-	if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
+	if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
 		return cpufreq_register_notifier(&twd_cpufreq_nb,
 			CPUFREQ_TRANSITION_NOTIFIER);
 
@@ -228,7 +230,7 @@ static void __cpuinit twd_calibrate_rate(void)
 
 static irqreturn_t twd_handler(int irq, void *dev_id)
 {
-	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+	struct clock_event_device *evt = dev_id;
 
 	if (twd_timer_ack()) {
 		evt->event_handler(evt);
@@ -265,9 +267,9 @@ static void twd_get_clock(struct device_node *np)
 /*
  * Setup the local clock events for a CPU.
  */
-static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
+static void __cpuinit twd_timer_setup(void)
 {
-	struct clock_event_device **this_cpu_clk;
+	struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
 	int cpu = smp_processor_id();
 
 	/*
@@ -276,9 +278,9 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 	 */
 	if (per_cpu(percpu_setup_called, cpu)) {
 		__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
-		clockevents_register_device(*__this_cpu_ptr(twd_evt));
+		clockevents_register_device(clk);
 		enable_percpu_irq(clk->irq, 0);
-		return 0;
+		return;
 	}
 	per_cpu(percpu_setup_called, cpu) = true;
 
@@ -297,27 +299,37 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 	clk->set_mode = twd_set_mode;
 	clk->set_next_event = twd_set_next_event;
 	clk->irq = twd_ppi;
-
-	this_cpu_clk = __this_cpu_ptr(twd_evt);
-	*this_cpu_clk = clk;
+	clk->cpumask = cpumask_of(cpu);
 
 	clockevents_config_and_register(clk, twd_timer_rate,
 					0xf, 0xffffffff);
 	enable_percpu_irq(clk->irq, 0);
+}
 
-	return 0;
+static int __cpuinit twd_timer_cpu_notify(struct notifier_block *self,
+					   unsigned long action, void *hcpu)
+{
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_STARTING:
+		twd_timer_setup();
+		break;
+	case CPU_DYING:
+		twd_timer_stop();
+		break;
+	}
+
+	return NOTIFY_OK;
 }
 
-static struct local_timer_ops twd_lt_ops __cpuinitdata = {
-	.setup	= twd_timer_setup,
-	.stop	= twd_timer_stop,
+static struct notifier_block twd_timer_cpu_nb __cpuinitdata = {
+	.notifier_call = twd_timer_cpu_notify,
 };
 
 static int __init twd_local_timer_common_register(struct device_node *np)
 {
 	int err;
 
-	twd_evt = alloc_percpu(struct clock_event_device *);
+	twd_evt = alloc_percpu(struct clock_event_device);
 	if (!twd_evt) {
 		err = -ENOMEM;
 		goto out_free;
@@ -329,12 +341,22 @@ static int __init twd_local_timer_common_register(struct device_node *np)
 		goto out_free;
 	}
 
-	err = local_timer_register(&twd_lt_ops);
+	err = register_cpu_notifier(&twd_timer_cpu_nb);
 	if (err)
 		goto out_irq;
 
 	twd_get_clock(np);
 
+	/*
+	 * Immediately configure the timer on the boot CPU, unless we need
+	 * jiffies to be incrementing to calibrate the rate in which case
+	 * setup the timer in late_time_init.
+	 */
+	if (twd_timer_rate)
+		twd_timer_setup();
+	else
+		late_time_init = twd_timer_setup;
+
 	return 0;
 
 out_irq:
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index cd9fcb1..6acbdab 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -12,7 +12,7 @@ config ARCH_HIGHBANK
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
 	select MAILBOX
 	select PL320_MBOX
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328..c8adc79 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -798,7 +798,7 @@ config SOC_IMX6Q
 	select COMMON_CLK
 	select CPU_V7
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_IMX_ANATOP
 	select HAVE_IMX_GPC
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..edb950a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -90,7 +90,7 @@ config ARCH_OMAP4
 	select CACHE_L2X0
 	select CPU_V7
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
 	select LOCAL_TIMERS if SMP
 	select OMAP_INTERCONNECT
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index d210c0f9..9db2029 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -13,7 +13,7 @@ config REALVIEW_EB_A9MP
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	help
@@ -26,7 +26,7 @@ config REALVIEW_EB_ARM11MP
 	select ARCH_HAS_BARRIERS if SMP
 	select CPU_V6K
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	help
@@ -48,7 +48,7 @@ config MACH_REALVIEW_PB11MP
 	select ARM_GIC
 	select CPU_V6K
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_PATA_PLATFORM
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
@@ -92,7 +92,7 @@ config MACH_REALVIEW_PBX
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ARM_GIC
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_PATA_PLATFORM
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 442917e..df0d59a 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -23,7 +23,7 @@ config ARCH_SPEAR13XX
 	select CPU_V7
 	select GPIO_SPEAR_SPICS
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc..1f3ea1f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -8,7 +8,7 @@ config ARCH_TEGRA
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_CLK
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 6a4387e..0614ee2 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,7 +8,7 @@ config ARCH_U8500
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	help
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 5907e10..5bfdd73 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -10,7 +10,7 @@ config ARCH_VEXPRESS
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select HAVE_CLK
 	select HAVE_PATA_PLATFORM
 	select HAVE_SMP
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index c1d61f2..04f8a4a 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -6,7 +6,7 @@ config ARCH_ZYNQ
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_ARM_TWD if SMP
 	select ICST
 	select MIGHT_HAVE_CACHE_L2X0
 	select USE_OF
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:14 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:14 -0700
Subject: [PATCHv6 10/11] clocksource: time-armada-370-xp: Divorce from local
 timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-11-git-send-email-sboyd@codeaurora.org>

Separate the armada 370xp local timers from the local timer API.
This will allow us to remove ARM local timer support in the near
future and makes this driver multi-architecture friendly.

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/time-armada-370-xp.c | 89 +++++++++++++++-----------------
 1 file changed, 41 insertions(+), 48 deletions(-)

diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index efe4aef..4a31e86 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/cpu.h>
 #include <linux/timer.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -31,7 +32,6 @@
 #include <linux/time-armada-370-xp.h>
 
 #include <asm/sched_clock.h>
-#include <asm/localtimer.h>
 /*
  * Timer block registers.
  */
@@ -70,7 +70,7 @@ static bool timer25Mhz = true;
  */
 static u32 ticks_per_jiffy;
 
-static struct clock_event_device __percpu **percpu_armada_370_xp_evt;
+static struct clock_event_device __percpu *armada_370_xp_evt;
 
 static u32 notrace armada_370_xp_read_sched_clock(void)
 {
@@ -143,21 +143,14 @@ armada_370_xp_clkevt_mode(enum clock_event_mode mode,
 	}
 }
 
-static struct clock_event_device armada_370_xp_clkevt = {
-	.name		= "armada_370_xp_per_cpu_tick",
-	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-	.shift		= 32,
-	.rating		= 300,
-	.set_next_event	= armada_370_xp_clkevt_next_event,
-	.set_mode	= armada_370_xp_clkevt_mode,
-};
+static int armada_370_xp_clkevt_irq;
 
 static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
 {
 	/*
 	 * ACK timer interrupt and call event handler.
 	 */
-	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+	struct clock_event_device *evt = dev_id;
 
 	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 	evt->event_handler(evt);
@@ -173,42 +166,55 @@ static int __cpuinit armada_370_xp_timer_setup(struct clock_event_device *evt)
 	u32 u;
 	int cpu = smp_processor_id();
 
-	/* Use existing clock_event for cpu 0 */
-	if (!smp_processor_id())
-		return 0;
-
 	u = readl(local_base + TIMER_CTRL_OFF);
 	if (timer25Mhz)
 		writel(u | TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
 	else
 		writel(u & ~TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
 
-	evt->name		= armada_370_xp_clkevt.name;
-	evt->irq		= armada_370_xp_clkevt.irq;
-	evt->features		= armada_370_xp_clkevt.features;
-	evt->shift		= armada_370_xp_clkevt.shift;
-	evt->rating		= armada_370_xp_clkevt.rating,
+	evt->name		= "armada_370_xp_per_cpu_tick",
+	evt->features		= CLOCK_EVT_FEAT_ONESHOT |
+				  CLOCK_EVT_FEAT_PERIODIC;
+	evt->shift		= 32,
+	evt->rating		= 300,
 	evt->set_next_event	= armada_370_xp_clkevt_next_event,
 	evt->set_mode		= armada_370_xp_clkevt_mode,
+	evt->irq		= armada_370_xp_clkevt_irq;
 	evt->cpumask		= cpumask_of(cpu);
 
-	*__this_cpu_ptr(percpu_armada_370_xp_evt) = evt;
-
 	clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
 	enable_percpu_irq(evt->irq, 0);
 
 	return 0;
 }
 
-static void  armada_370_xp_timer_stop(struct clock_event_device *evt)
+static void __cpuinit armada_370_xp_timer_stop(struct clock_event_device *evt)
 {
 	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 	disable_percpu_irq(evt->irq);
 }
 
-static struct local_timer_ops armada_370_xp_local_timer_ops __cpuinitdata = {
-	.setup	= armada_370_xp_timer_setup,
-	.stop	=  armada_370_xp_timer_stop,
+static int __cpuinit armada_370_xp_timer_cpu_notify(struct notifier_block *self,
+					   unsigned long action, void *hcpu)
+{
+	/*
+	 * Grab cpu pointer in each case to avoid spurious
+	 * preemptible warnings
+	 */
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_STARTING:
+		armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
+		break;
+	case CPU_DYING:
+		armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block armada_370_xp_timer_cpu_nb __cpuinitdata = {
+	.notifier_call = armada_370_xp_timer_cpu_notify,
 };
 
 void __init armada_370_xp_timer_init(void)
@@ -224,9 +230,6 @@ void __init armada_370_xp_timer_init(void)
 
 	if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
 		/* The fixed 25MHz timer is available so let's use it */
-		u = readl(local_base + TIMER_CTRL_OFF);
-		writel(u | TIMER0_25MHZ,
-		       local_base + TIMER_CTRL_OFF);
 		u = readl(timer_base + TIMER_CTRL_OFF);
 		writel(u | TIMER0_25MHZ,
 		       timer_base + TIMER_CTRL_OFF);
@@ -236,9 +239,6 @@ void __init armada_370_xp_timer_init(void)
 		struct clk *clk = of_clk_get(np, 0);
 		WARN_ON(IS_ERR(clk));
 		rate =  clk_get_rate(clk);
-		u = readl(local_base + TIMER_CTRL_OFF);
-		writel(u & ~(TIMER0_25MHZ),
-		       local_base + TIMER_CTRL_OFF);
 
 		u = readl(timer_base + TIMER_CTRL_OFF);
 		writel(u & ~(TIMER0_25MHZ),
@@ -252,7 +252,7 @@ void __init armada_370_xp_timer_init(void)
 	 * We use timer 0 as clocksource, and private(local) timer 0
 	 * for clockevents
 	 */
-	armada_370_xp_clkevt.irq = irq_of_parse_and_map(np, 4);
+	armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
 
 	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
 
@@ -277,26 +277,19 @@ void __init armada_370_xp_timer_init(void)
 			      "armada_370_xp_clocksource",
 			      timer_clk, 300, 32, clocksource_mmio_readl_down);
 
-	/* Register the clockevent on the private timer of CPU 0 */
-	armada_370_xp_clkevt.cpumask = cpumask_of(0);
-	clockevents_config_and_register(&armada_370_xp_clkevt,
-					timer_clk, 1, 0xfffffffe);
+	register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
 
-	percpu_armada_370_xp_evt = alloc_percpu(struct clock_event_device *);
+	armada_370_xp_evt = alloc_percpu(struct clock_event_device);
 
 
 	/*
 	 * Setup clockevent timer (interrupt-driven).
 	 */
-	*__this_cpu_ptr(percpu_armada_370_xp_evt) = &armada_370_xp_clkevt;
-	res = request_percpu_irq(armada_370_xp_clkevt.irq,
+	res = request_percpu_irq(armada_370_xp_clkevt_irq,
 				armada_370_xp_timer_interrupt,
-				armada_370_xp_clkevt.name,
-				percpu_armada_370_xp_evt);
-	if (!res) {
-		enable_percpu_irq(armada_370_xp_clkevt.irq, 0);
-#ifdef CONFIG_LOCAL_TIMERS
-		local_timer_register(&armada_370_xp_local_timer_ops);
-#endif
-	}
+				"armada_370_xp_per_cpu_tick",
+				armada_370_xp_evt);
+	/* Immediately configure the timer on the boot CPU */
+	if (!res)
+		armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 }
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:09 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:09 -0700
Subject: [PATCHv6 05/11] ARM: OMAP2+: Divorce from local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-6-git-send-email-sboyd@codeaurora.org>

Now that the TWD doesn't rely on the local timer API, OMAP can
stop selecting it in Kconfig and relying on the config option to
decide if it should call smp_twd functions.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Tony Lindgren <tony at atomide.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-omap2/Kconfig | 1 -
 arch/arm/mach-omap2/timer.c | 7 -------
 2 files changed, 8 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index edb950a..4e0049a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -92,7 +92,6 @@ config ARCH_OMAP4
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if SMP
 	select HAVE_SMP
-	select LOCAL_TIMERS if SMP
 	select OMAP_INTERCONNECT
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f8b23b8..60e9cf8 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -600,7 +600,6 @@ static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-#ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
 {
@@ -619,12 +618,6 @@ void __init omap4_local_timer_init(void)
 			pr_err("twd_local_timer_register failed %d\n", err);
 	}
 }
-#else /* CONFIG_LOCAL_TIMERS */
-void __init omap4_local_timer_init(void)
-{
-	omap4_sync32k_timer_init();
-}
-#endif /* CONFIG_LOCAL_TIMERS */
 #endif /* CONFIG_ARCH_OMAP4 */
 
 #ifdef CONFIG_SOC_OMAP5
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:15 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:15 -0700
Subject: [PATCHv6 11/11] ARM: smp: Remove local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-12-git-send-email-sboyd@codeaurora.org>

There are no more users of this API, remove it.

Cc: Russell King <linux at arm.linux.org.uk>
Acked-by: Tony Lindgren <tony at atomide.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/Kconfig                  | 10 ------
 arch/arm/include/asm/localtimer.h | 34 -------------------
 arch/arm/kernel/smp.c             | 69 ---------------------------------------
 3 files changed, 113 deletions(-)
 delete mode 100644 arch/arm/include/asm/localtimer.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 177cb39..626a272 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1542,16 +1542,6 @@ config ARM_PSCI
 	  0022A ("Power State Coordination Interface System Software on
 	  ARM processors").
 
-config LOCAL_TIMERS
-	bool "Use local timer interrupts"
-	depends on SMP
-	default y
-	help
-	  Enable support for local timers on SMP platforms, rather then the
-	  legacy IPI broadcast method.  Local timers allows the system
-	  accounting to be spread across the timer interval, preventing a
-	  "thundering herd" at every timer tick.
-
 # The GPIO number here must be sorted by descending number. In case of
 # a multiplatform kernel, we just want the highest value required by the
 # selected platforms.
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
deleted file mode 100644
index f77ffc1..0000000
--- a/arch/arm/include/asm/localtimer.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *  arch/arm/include/asm/localtimer.h
- *
- *  Copyright (C) 2004-2005 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_LOCALTIMER_H
-#define __ASM_ARM_LOCALTIMER_H
-
-#include <linux/errno.h>
-
-struct clock_event_device;
-
-struct local_timer_ops {
-	int  (*setup)(struct clock_event_device *);
-	void (*stop)(struct clock_event_device *);
-};
-
-#ifdef CONFIG_LOCAL_TIMERS
-/*
- * Register a local timer driver
- */
-int local_timer_register(struct local_timer_ops *);
-#else
-static inline int local_timer_register(struct local_timer_ops *ops)
-{
-	return -ENXIO;
-}
-#endif
-
-#endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 4dc883a..54aa994 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -41,7 +41,6 @@
 #include <asm/sections.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
-#include <asm/localtimer.h>
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
@@ -133,8 +132,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static void percpu_timer_stop(void);
-
 static int platform_cpu_kill(unsigned int cpu)
 {
 	if (smp_ops.cpu_kill)
@@ -178,11 +175,6 @@ int __cpuinit __cpu_disable(void)
 	migrate_irqs();
 
 	/*
-	 * Stop the local timer for this CPU.
-	 */
-	percpu_timer_stop();
-
-	/*
 	 * Flush user cache and TLB mappings, and then remove this CPU
 	 * from the vm mask set of all processes.
 	 *
@@ -303,8 +295,6 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
 	store_cpu_topology(cpuid);
 }
 
-static void percpu_timer_setup(void);
-
 /*
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
@@ -359,11 +349,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
 	set_cpu_online(cpu, true);
 	complete(&cpu_running);
 
-	/*
-	 * Setup the percpu timer for this CPU.
-	 */
-	percpu_timer_setup();
-
 	local_irq_enable();
 	local_fiq_enable();
 
@@ -410,12 +395,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 		max_cpus = ncores;
 	if (ncores > 1 && max_cpus) {
 		/*
-		 * Enable the local timer or broadcast device for the
-		 * boot CPU, but only if we have more than one CPU.
-		 */
-		percpu_timer_setup();
-
-		/*
 		 * Initialise the present map, which describes the set of CPUs
 		 * actually populated at the present time. A platform should
 		 * re-initialize the map in the platforms smp_prepare_cpus()
@@ -491,11 +470,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
 	return sum;
 }
 
-/*
- * Timer (local or broadcast) support
- */
-static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
-
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 void tick_broadcast(const struct cpumask *mask)
 {
@@ -503,49 +477,6 @@ void tick_broadcast(const struct cpumask *mask)
 }
 #endif
 
-static struct local_timer_ops *lt_ops;
-
-#ifdef CONFIG_LOCAL_TIMERS
-int local_timer_register(struct local_timer_ops *ops)
-{
-	if (!is_smp() || !setup_max_cpus)
-		return -ENXIO;
-
-	if (lt_ops)
-		return -EBUSY;
-
-	lt_ops = ops;
-	return 0;
-}
-#endif
-
-static void __cpuinit percpu_timer_setup(void)
-{
-	unsigned int cpu = smp_processor_id();
-	struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
-
-	evt->cpumask = cpumask_of(cpu);
-
-	if (lt_ops)
-		lt_ops->setup(evt);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-/*
- * The generic clock events code purposely does not stop the local timer
- * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it
- * manually here.
- */
-static void percpu_timer_stop(void)
-{
-	unsigned int cpu = smp_processor_id();
-	struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
-
-	if (lt_ops)
-		lt_ops->stop(evt);
-}
-#endif
-
 static DEFINE_RAW_SPINLOCK(stop_lock);
 
 /*
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:26:13 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:26:13 -0700
Subject: [PATCHv6 09/11] clocksource: time-armada-370-xp: Fix sparse warning
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368473175-4841-10-git-send-email-sboyd@codeaurora.org>

drivers/clocksource/time-armada-370-xp.c:217:13: warning: symbol
'armada_370_xp_timer_init' was not declared. Should it be static?

Also remove the __init marking in the prototype as it's
unnecessary and drop the init.h file.

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/time-armada-370-xp.c | 3 ++-
 include/linux/time-armada-370-xp.h       | 4 +---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 47a6730..efe4aef 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -27,10 +27,11 @@
 #include <linux/of_address.h>
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/percpu.h>
+#include <linux/time-armada-370-xp.h>
 
 #include <asm/sched_clock.h>
 #include <asm/localtimer.h>
-#include <linux/percpu.h>
 /*
  * Timer block registers.
  */
diff --git a/include/linux/time-armada-370-xp.h b/include/linux/time-armada-370-xp.h
index dfdfdc0..6fb0856 100644
--- a/include/linux/time-armada-370-xp.h
+++ b/include/linux/time-armada-370-xp.h
@@ -11,8 +11,6 @@
 #ifndef __TIME_ARMADA_370_XPPRCMU_H
 #define __TIME_ARMADA_370_XPPRCMU_H
 
-#include <linux/init.h>
-
-void __init armada_370_xp_timer_init(void);
+void armada_370_xp_timer_init(void);
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From swarren at wwwdotorg.org  Mon May 13 15:29:02 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 13:29:02 -0600
Subject: [PATCH 1/2] ARM: tegra: dalmore: populate key mapping
In-Reply-To: <1365594454-20614-1-git-send-email-ldewangan@nvidia.com>
References: <1365594454-20614-1-git-send-email-ldewangan@nvidia.com>
Message-ID: <51913EFE.6030103@wwwdotorg.org>

On 04/10/2013 05:47 AM, Laxman Dewangan wrote:
> Keys on Dalmore interfaced through Tegra KBC controller
> in key matrix topology.
> 
> Add the key mapping for the keys.
> 
> Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
> ---
> The system is booted on Dalmore SKU1000 with the fastboot.

I don't intend applying these two patches.

For Dalmore, there are two SKUs, one using KBC and one using GPIOs for
the buttons/keys. The SKU that uses GPIOs is far more common, so we've
decided to support that one upstream.

We aren't actively pursuing Pluto support upstream; it's likely that
I'll send a patch to remove tegra114-pluto.dts in the near future.


From tomasz.figa at gmail.com  Mon May 13 15:29:08 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Mon, 13 May 2013 21:29:08 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
Message-ID: <4008658.mlznVFUzcs@flatron>

Hi,

On Monday 13 of May 2013 20:24:01 Inki Dae wrote:
> > -----Original Message-----
> > From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
> > Sent: Monday, May 13, 2013 6:52 PM
> > To: Inki Dae
> > Cc: 'Rob Clark'; 'Daniel Vetter'; 'DRI mailing list'; linux-arm-
> > kernel at lists.infradead.org; linux-media at vger.kernel.org;
> > 'linux-fbdev';
> > 'Kyungmin Park'; 'myungjoo.ham'; 'YoungJun Cho'
> > Subject: Re: Introduce a new helper framework for buffer
> > synchronization> 
> > Op 13-05-13 11:21, Inki Dae schreef:
> > >> -----Original Message-----
> > >> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
> > >> Sent: Monday, May 13, 2013 5:01 PM
> > >> To: Inki Dae
> > >> Cc: Rob Clark; Daniel Vetter; DRI mailing list; linux-arm-
> > >> kernel at lists.infradead.org; linux-media at vger.kernel.org;
> > >> linux-fbdev;
> > >> Kyungmin Park; myungjoo.ham; YoungJun Cho
> > >> Subject: Re: Introduce a new helper framework for buffer
> > 
> > synchronization
> > 
> > >> Op 09-05-13 09:33, Inki Dae schreef:
> > >>> Hi all,
> > >>> 
> > >>> This post introduces a new helper framework based on dma fence.
> > >>> And
> > 
> > the
> > 
> > >>> purpose of this post is to collect other opinions and advices
> > >>> before
> > 
> > RFC
> > 
> > >>> posting.
> > >>> 
> > >>> First of all, this helper framework, called fence helper, is in
> > 
> > progress
> > 
> > >>> yet so might not have enough comments in codes and also might need
> > >>> to
> > 
> > be
> > 
> > >>> more cleaned up. Moreover, we might be missing some parts of the
> > >>> dma
> > >> 
> > >> fence.
> > >> 
> > >>> However, I'd like to say that all things mentioned below has been
> > 
> > tested
> > 
> > >>> with Linux platform and worked well.
> > >>> ....
> > >>> 
> > >>> And tutorial for user process.
> > >>> 
> > >>>         just before cpu access
> > >>>         
> > >>>                 struct dma_buf_fence *df;
> > >>>                 
> > >>>                 df->type = DMA_BUF_ACCESS_READ or
> 
> DMA_BUF_ACCESS_WRITE;
> 
> > >>>                 ioctl(fd, DMA_BUF_GET_FENCE, &df);
> > >>>         
> > >>>         after memset or memcpy
> > >>>         
> > >>>                 ioctl(fd, DMA_BUF_PUT_FENCE, &df);
> > >> 
> > >> NAK.
> > >> 
> > >> Userspace doesn't need to trigger fences. It can do a buffer idle
> > >> wait,
> > >> and postpone submitting new commands until after it's done using
> > >> the
> > >> buffer.
> > > 
> > > Hi Maarten,
> > > 
> > > It seems that you say user should wait for a buffer like KDS does:
> > > KDS
> > 
> > uses
> > 
> > > select() to postpone submitting new commands. But I think this way
> > 
> > assumes
> > 
> > > that every data flows a DMA device to a CPU. For example, a CPU
> > > should
> > 
> > keep
> > 
> > > polling for the completion of a buffer access by a DMA device. This
> > 
> > means
> > 
> > > that the this way isn't considered for data flow to opposite case;
> > > CPU
> > 
> > to
> > 
> > > DMA device.
> > 
> > Not really. You do both things the same way. You first wait for the bo
> > to be idle, this could be implemented by adding poll support to the
> > dma-buf fd.
> > Then you either do your read or write. Since userspace is supposed to
> > be the one controlling the bo it should stay idle at that point. If
> > you have another thread queueing
> > the buffer againbefore your thread is done that's a bug in the
> 
> application,
> 
> > and can be solved with userspace locking primitives. No need for the
> > kernel to get involved.
> 
> Yes, that is how we have synchronized buffer between CPU and DMA device
> until now without buffer synchronization mechanism. I thought that it's
> best to make user not considering anything: user can access a buffer
> regardless of any DMA device controlling and the buffer synchronization
> is performed in kernel level. Moreover, I think we could optimize
> graphics and multimedia hardware performance because hardware can do
> more works: one thread accesses a shared buffer and the other controls
> DMA device with the shared buffer in parallel.

Could you explain this point? I thought that if there is a shared buffer 
accessible for user and DMA device, only one of them can use it at the 
moment, i.e. the buffer is useless for the reading user (or read DMA) 
until (write) DMA (or writing user) finishes writing for it. Is it 
incorrect? Or this is not the point here?

I'm not an expert here and I'm just trying to understand the idea, so 
correct me if I'm wrong. Thanks in advance.

Best regards,
Tomasz

> Thus, we could avoid
> sequential processing and that is my intention. Aren't you think about
> that we could improve hardware utilization with such way or other? of
> course, there could be better way.
> 
> > >> Kernel space doesn't need the root hole you created by giving a
> > >> dereferencing a pointer passed from userspace.
> > >> Your next exercise should be to write a security exploit from the
> > >> api
> > 
> > you
> > 
> > >> created here. It's the only way to learn how to write safe code.
> > >> Hint:
> > >> df.ctx = mmap(..);
> > > 
> > > Also I'm not clear to use our way yet and that is why I posted. As
> > > you
> > > mentioned, it seems like that using mmap() is more safe. But there
> > > is
> > 
> > one
> > 
> > > issue it makes me confusing. For your hint, df.ctx = mmap(..), the
> > > issue> 
> > is
> > 
> > > that dmabuf mmap can be used to map a dmabuf with user space. And
> > > the
> > 
> > dmabuf
> > 
> > > means a physical memory region allocated by some allocator such as
> > > drm
> > 
> > gem
> > 
> > > or ion.
> > > 
> > > There might be my missing point so could you please give me more
> > 
> > comments?
> > 
> > My point was that userspace could change df.ctx to some mmap'd memory,
> > forcing the kernel to execute some code prepared by userspace.
> 
> Understood. I have to find a better way. And for this, I'd like to
> listen attentively more opinions and advices.
> 
> Thanks for comments,
> Inki Dae
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel


From tglx at linutronix.de  Mon May 13 15:30:30 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 13 May 2013 21:30:30 +0200 (CEST)
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1305132114490.2863@ionos>

On Mon, 13 May 2013, Linus Walleij wrote:
> On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
> > +       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
> > +       clk->set_mode = gt_clockevent_set_mode;
> > +       clk->set_next_event = gt_clockevent_set_next_event;
> > +       this_cpu_clk = __this_cpu_ptr(gt_evt);
> > +       *this_cpu_clk = clk;
> > +       clk->irq = gt_ppi;
> > +       clockevents_config_and_register(clk, gt_clk_rate,
> > +                                       0xf, 0xffffffff);
> 
> Why can't this clock event handle anything lower than 0xf?
> Does that come from the datasheet or have you just copied some
> code?
> 
> Further, since this clock event hardware *most definately* supports
> using a delta upper bound *beyond* 32 bits, I think the clock event
> core code should be altered to allow for registereing such clock
> events, but TGLX may have some idea here. This will work but will
> not expose the full potential of this 64-bit counter hardware.

That requires a full source tree sweep to change all set_next_event
callbacks in one go. Easy to do with coccinelle, but that needs the
proper timing, i.e. right after a -rc1.

Thanks,

	tglx


From jason at lakedaemon.net  Mon May 13 15:38:59 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 15:38:59 -0400
Subject: [PATCH] ARM: Orion: Remove redundent init_dma_coherent_pool_size()
In-Reply-To: <516F0AF1.2090905@free-electrons.com>
References: <1352356737-14413-1-git-send-email-m.szyprowski@samsung.com>
 <1352655079-1005-1-git-send-email-andrew@lunn.ch>
 <20130417203806.GE27197@titan.lakedaemon.net>
 <516F0AF1.2090905@free-electrons.com>
Message-ID: <20130513193859.GW31290@titan.lakedaemon.net>

On Wed, Apr 17, 2013 at 10:49:53PM +0200, Gregory CLEMENT wrote:
> On 04/17/2013 10:38 PM, Jason Cooper wrote:
> > Andrew,
> > 
> > Now that we finally have Soren Moch's (sp? sorry) cache exhaustion
> > solved, can we respin this for v3.11?  I'd like to include mvebu as well
> > if possible.
> 
> For mvebu, I can do a follow-up patch, or Andrew can directly add it to his
> patch.

Applied to mvebu/cleanup with a few minor typo corrections and I added
the hunk for mach-mvebu/.

thx,

Jason.


> > On Sun, Nov 11, 2012 at 06:31:19PM +0100, Andrew Lunn wrote:
> >> The patch:
> >>
> >> mm: dmapool: use provided gfp flags for all dma_alloc_coherent() calls
> >>
> >> makes these calls on Kirkword and Orion5x redundent. The drivers are
> >> not making atomic requests for coherent memory and hence the default
> >> pool size is now sufficient.
> >>
> >> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> >> ---
> >>  arch/arm/mach-kirkwood/common.c |    7 -------
> >>  arch/arm/mach-orion5x/common.c  |    7 -------
> >>  2 files changed, 14 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> >> index 2c6c218..8080ceb 100644
> >> --- a/arch/arm/mach-kirkwood/common.c
> >> +++ b/arch/arm/mach-kirkwood/common.c
> >> @@ -505,13 +505,6 @@ void __init kirkwood_wdt_init(void)
> >>  void __init kirkwood_init_early(void)
> >>  {
> >>  	orion_time_set_base(TIMER_VIRT_BASE);
> >> -
> >> -	/*
> >> -	 * Some Kirkwood devices allocate their coherent buffers from atomic
> >> -	 * context. Increase size of atomic coherent pool to make sure such
> >> -	 * the allocations won't fail.
> >> -	 */
> >> -	init_dma_coherent_pool_size(SZ_1M);
> >>  }
> >>  
> >>  int kirkwood_tclk;
> >> diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
> >> index b3eb3da..3e07f52 100644
> >> --- a/arch/arm/mach-orion5x/common.c
> >> +++ b/arch/arm/mach-orion5x/common.c
> >> @@ -194,13 +194,6 @@ void __init orion5x_wdt_init(void)
> >>  void __init orion5x_init_early(void)
> >>  {
> >>  	orion_time_set_base(TIMER_VIRT_BASE);
> >> -
> >> -	/*
> >> -	 * Some Orion5x devices allocate their coherent buffers from atomic
> >> -	 * context. Increase size of atomic coherent pool to make sure such
> >> -	 * the allocations won't fail.
> >> -	 */
> >> -	init_dma_coherent_pool_size(SZ_1M);
> >>  }
> >>  
> >>  int orion5x_tclk;
> >> -- 
> >> 1.7.10.4
> >>
> >>
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel at lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> 
> -- 
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mturquette at linaro.org  Mon May 13 15:47:03 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Mon, 13 May 2013 12:47:03 -0700
Subject: [PATCH 2/5] clk: hi3xxx: add clock support
In-Reply-To: <1366368567-17322-2-git-send-email-haojian.zhuang@linaro.org>
References: <1366368567-17322-1-git-send-email-haojian.zhuang@linaro.org>
 <1366368567-17322-2-git-send-email-haojian.zhuang@linaro.org>
Message-ID: <20130513194703.10068.4450@quantum>

Quoting Haojian Zhuang (2013-04-19 03:49:24)
> diff --git a/drivers/clk/clk-hi3xxx.c b/drivers/clk/clk-hi3xxx.c
> new file mode 100644
> index 0000000..e93e583
> --- /dev/null
> +++ b/drivers/clk/clk-hi3xxx.c
> @@ -0,0 +1,641 @@
> +/*
> + * Hisilicon clock driver
> + *
> + * Copyright (c) 2012-2013 Hisilicon Limited.
> + * Copyright (c) 2012-2013 Linaro Limited.
> + *
> + * Author: Haojian Zhuang <haojian.zhuang at linaro.org>
> + *        Xin Li <li.xin at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk-private.h>

clk-private.h is deprecated and can no longer be included by any new
clock drivers.  It will hopefully be removed in 3.11.  Please remove it
in your next version.

> +#include <linux/clkdev.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/slab.h>
> +#include <linux/clk.h>
> +
> +#define HI3620_DISABLE_OFF             0x4
> +#define HI3620_STATUS_OFF              0x8
> +
> +#define WIDTH_TO_MASK(width)   ((1 << (width)) - 1)
> +
> +/*
> + * The reverse of DIV_ROUND_UP: The maximum number which
> + * divided by m is r
> + */
> +#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
> +
> +struct hi3620_periclk {
> +       struct clk_hw   hw;
> +       void __iomem    *enable;        /* enable register */
> +       void __iomem    *reset;         /* reset register */
> +       u32             ebits;          /* bits in enable/disable register */
> +       u32             rbits;          /* bits in reset/unreset register */
> +       spinlock_t      *lock;
> +};
> +
> +struct hi3620_muxclk {
> +       struct clk_hw   hw;
> +       void __iomem    *reg;           /* mux register */
> +       u8              shift;
> +       u8              width;
> +       u32             mbits;          /* mask bits in mux register */

You need shift, width AND a mask?  Normally either shift+width OR a mask
would suffice.

> +       spinlock_t      *lock;
> +};
> +
> +struct hi3620_divclk {
> +       struct clk_hw   hw;
> +       void __iomem    *reg;           /* divider register */
> +       u8              shift;
> +       u8              width;
> +       u32             mbits;          /* mask bits in divider register */

Ditto.

> +       const struct clk_div_table      *table;
> +       spinlock_t      *lock;
> +};
> +
> +struct hs_clk {
> +       void __iomem    *pmctrl;
> +       void __iomem    *sctrl;
> +       spinlock_t      lock;
> +};
> +
> +static struct hs_clk hs_clk;
> +
> +static void __init hs_init_clocks(void)
> +{
> +       struct device_node *node = NULL;
> +
> +       if (!hs_clk.pmctrl) {
> +               /* map pmctrl registers */
> +               node = of_find_compatible_node(NULL, NULL, "hisilicon,pmctrl");
> +               hs_clk.pmctrl = of_iomap(node, 0);
> +               WARN_ON(!hs_clk.pmctrl);
> +       }
> +
> +       if (!hs_clk.sctrl) {
> +               node = of_find_compatible_node(NULL, NULL, "hisilicon,sctrl");
> +               hs_clk.sctrl = of_iomap(node, 0);
> +       }
> +}
> +
> +static int hi3620_clkgate_prepare(struct clk_hw *hw)
> +{
> +       struct hi3620_periclk *pclk;
> +       unsigned long flags = 0;
> +
> +       pclk = container_of(hw, struct hi3620_periclk, hw);
> +
> +       if (pclk->lock)
> +               spin_lock_irqsave(pclk->lock, flags);
> +       writel_relaxed(pclk->ebits, pclk->enable + HI3620_DISABLE_OFF);
> +       writel_relaxed(pclk->rbits, pclk->reset + HI3620_DISABLE_OFF);
> +       readl_relaxed(pclk->reset + HI3620_STATUS_OFF);
> +       if (pclk->lock)
> +               spin_unlock_irqrestore(pclk->lock, flags);
> +       return 0;
> +}
> +
> +static int hi3620_clkgate_enable(struct clk_hw *hw)
> +{
> +       struct hi3620_periclk *pclk;
> +       unsigned long flags = 0;
> +
> +       pclk = container_of(hw, struct hi3620_periclk, hw);
> +       if (pclk->lock)
> +               spin_lock_irqsave(pclk->lock, flags);
> +       writel_relaxed(pclk->ebits, pclk->enable);
> +       readl_relaxed(pclk->enable + HI3620_STATUS_OFF);
> +       if (pclk->lock)
> +               spin_unlock_irqrestore(pclk->lock, flags);
> +       return 0;
> +}
> +
> +static void hi3620_clkgate_disable(struct clk_hw *hw)
> +{
> +       struct hi3620_periclk *pclk;
> +       unsigned long flags = 0;
> +
> +       pclk = container_of(hw, struct hi3620_periclk, hw);
> +       if (pclk->lock)
> +               spin_lock_irqsave(pclk->lock, flags);
> +       writel_relaxed(pclk->ebits, pclk->enable + HI3620_DISABLE_OFF);
> +       readl_relaxed(pclk->enable + HI3620_STATUS_OFF);
> +       if (pclk->lock)
> +               spin_unlock_irqrestore(pclk->lock, flags);
> +}
> +
> +static struct clk_ops hi3620_clkgate_ops = {
> +       .prepare        = hi3620_clkgate_prepare,
> +       .enable         = hi3620_clkgate_enable,
> +       .disable        = hi3620_clkgate_disable,

.unprepare?

> +};
> +
> +static void __init hi3620_clkgate_setup(struct device_node *np)
> +{
> +       struct hi3620_periclk *pclk;
> +       struct clk_init_data *init;
> +       struct clk *clk;
> +       const char *clk_name, *name, **parent_names;
> +       u32 rdata[2], gdata[2];
> +
> +       if (!hs_clk.sctrl)
> +               return;
> +
> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
> +               return;
> +       if (of_property_read_u32_array(np, "hisilicon,hi3620-clkreset",
> +                                      &rdata[0], 2))
> +               return;
> +       if (of_property_read_u32_array(np, "hisilicon,hi3620-clkgate",
> +                                      &gdata[0], 2))
> +               return;
> +
> +       /* gate only has the fixed parent */
> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> +       if (!parent_names)
> +               return;
> +       parent_names[0] = of_clk_get_parent_name(np, 0);
> +
> +       pclk = kzalloc(sizeof(*pclk), GFP_KERNEL);
> +       if (!pclk)
> +               goto err_pclk;
> +
> +       init = kzalloc(sizeof(*init), GFP_KERNEL);
> +       if (!init)
> +               goto err_init;
> +       init->name = kstrdup(clk_name, GFP_KERNEL);
> +       init->ops = &hi3620_clkgate_ops;
> +       init->flags = CLK_SET_RATE_PARENT;
> +       init->parent_names = parent_names;
> +       init->num_parents = 1;
> +
> +       pclk->reset = hs_clk.sctrl + rdata[0];
> +       pclk->rbits = rdata[1];
> +       pclk->enable = hs_clk.sctrl + gdata[0];
> +       pclk->ebits = gdata[1];
> +       pclk->lock = &hs_clk.lock;
> +       pclk->hw.init = init;
> +
> +       clk = clk_register(NULL, &pclk->hw);
> +       if (IS_ERR(clk))
> +               goto err_clk;
> +       if (!of_property_read_string(np, "clock-names", &name))
> +               clk_register_clkdev(clk, name, NULL);
> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +       return;
> +err_clk:
> +       kfree(init);
> +err_init:
> +       kfree(pclk);
> +err_pclk:
> +       kfree(parent_names);
> +}
> +
> +static u8 hi3620_clk_get_parent(struct clk_hw *hw)
> +{
> +       struct hi3620_muxclk *mclk;
> +       u32 data;
> +       unsigned long flags = 0;
> +
> +       mclk = container_of(hw, struct hi3620_muxclk, hw);
> +
> +       if (mclk->lock)
> +               spin_lock_irqsave(mclk->lock, flags);
> +
> +       data = readl_relaxed(mclk->reg) >> mclk->shift;
> +       data &= WIDTH_TO_MASK(mclk->width);
> +
> +       if (mclk->lock)
> +               spin_unlock_irqrestore(mclk->lock, flags);
> +
> +       if (data >= __clk_get_num_parents(hw->clk))
> +               return -EINVAL;
> +
> +       return (u8)data;
> +}
> +
> +static int hi3620_clk_set_parent(struct clk_hw *hw, u8 index)
> +{
> +       struct hi3620_muxclk *mclk;
> +       u32 data;
> +       unsigned long flags = 0;
> +
> +       mclk = container_of(hw, struct hi3620_muxclk, hw);
> +
> +       if (mclk->lock)
> +               spin_lock_irqsave(mclk->lock, flags);
> +
> +       data = readl_relaxed(mclk->reg);
> +       data &= ~(WIDTH_TO_MASK(mclk->width) << mclk->shift);
> +       data |= index << mclk->shift;
> +       writel_relaxed(data, mclk->reg);
> +       /* set mask enable bits */
> +       data |= mclk->mbits;
> +       writel_relaxed(data, mclk->reg);

Is mclk->mbits equivalent to (mclk->width << mclk->shift)?  If so you
can drop shift+width and use only the mask + helpers like ffs().  If
that is the case then this clock can probably use the generic clk-mux
type.

> +
> +       if (mclk->lock)
> +               spin_unlock_irqrestore(mclk->lock, flags);
> +
> +       return 0;
> +}
> +
> +static struct clk_ops hi3620_clkmux_ops = {
> +       .get_parent     = hi3620_clk_get_parent,
> +       .set_parent     = hi3620_clk_set_parent,
> +};
> +
> +static void __init hi3620_clkmux_setup(struct device_node *np)
> +{
> +       struct hi3620_muxclk *mclk;
> +       struct clk_init_data *init;
> +       struct clk *clk;
> +       const char *clk_name, **parent_names;
> +       u32 rdata[2];
> +       u8 num_parents;
> +       int i;
> +
> +       hs_init_clocks();
> +       if (!hs_clk.sctrl)
> +               return;
> +
> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
> +               return;
> +       if (of_property_read_u32_array(np, "hisilicon,hi3620-clkmux",
> +                                      &rdata[0], 2))
> +               return;
> +       /* get the count of items in mux */
> +       for (i = 0; ; i++) {
> +               /* parent's #clock-cells property is always 0 */
> +               if (!of_parse_phandle(np, "clocks", i))
> +                       break;
> +       }
> +       parent_names = kzalloc(sizeof(char *) * i, GFP_KERNEL);
> +       if (!parent_names)
> +               return;
> +
> +       for (num_parents = i, i = 0; i < num_parents; i++)
> +               parent_names[i] = of_clk_get_parent_name(np, i);
> +
> +       mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
> +       if (!mclk)
> +               goto err_mclk;
> +       init = kzalloc(sizeof(*init), GFP_KERNEL);
> +       if (!init)
> +               goto err_init;
> +       init->name = kstrdup(clk_name, GFP_KERNEL);
> +       init->ops = &hi3620_clkmux_ops;
> +       init->flags = CLK_SET_RATE_PARENT;
> +       init->parent_names = parent_names;
> +       init->num_parents = num_parents;
> +
> +       mclk->reg = hs_clk.sctrl + rdata[0];
> +       /* enable_mask bits are in higher 16bits */
> +       mclk->mbits = rdata[1] << 16;
> +       mclk->shift = ffs(rdata[1]) - 1;
> +       mclk->width = fls(rdata[1]) - ffs(rdata[1]) + 1;
> +       mclk->lock = &hs_clk.lock;
> +       mclk->hw.init = init;
> +
> +       clk = clk_register(NULL, &mclk->hw);
> +       if (IS_ERR(clk))
> +               goto err_clk;
> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +
> +       return;
> +err_clk:
> +       kfree(init);
> +err_init:
> +       kfree(mclk);
> +err_mclk:
> +       kfree(parent_names);
> +}
> +
> +static void __init hs_clkgate_setup(struct device_node *np)
> +{
> +       struct clk *clk;
> +       const char *clk_name, **parent_names, *name;
> +       unsigned long flags = 0;
> +       u32 data[2];
> +
> +       hs_init_clocks();
> +       if (!hs_clk.sctrl)
> +               return;
> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
> +               return;
> +       if (of_property_read_u32_array(np, "hisilicon,clkgate",
> +                                      &data[0], 2))
> +               return;
> +       if (of_property_read_bool(np, "hisilicon,clkgate-inverted"))
> +               flags = CLK_GATE_SET_TO_DISABLE;
> +       /* gate only has the fixed parent */
> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> +       if (!parent_names)
> +               return;
> +       parent_names[0] = of_clk_get_parent_name(np, 0);
> +
> +       clk = clk_register_gate(NULL, clk_name, parent_names[0], 0,
> +                               hs_clk.sctrl + data[0], (u8)data[1], flags,
> +                               &hs_clk.lock);
> +       if (IS_ERR(clk))
> +               goto err;
> +       if (!of_property_read_string(np, "clock-names", &name))
> +               clk_register_clkdev(clk, name, NULL);
> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +       return;
> +err:
> +       kfree(parent_names);
> +}

I'm working on clock bindings for the generic clock types, so hopefully
this can be replaced by those instead of using your own compatible
string to wrap around clk_register_gate.

> +
> +void __init hs_fixed_factor_setup(struct device_node *np)
> +{
> +       struct clk *clk;
> +       const char *clk_name, **parent_names;
> +       u32 data[2];
> +
> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
> +               return;
> +       if (of_property_read_u32_array(np, "hisilicon,fixed-factor",
> +                                      data, 2))
> +               return ;
> +       /* gate only has the fixed parent */
> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> +       if (!parent_names)
> +               return;
> +       parent_names[0] = of_clk_get_parent_name(np, 0);
> +
> +       clk = clk_register_fixed_factor(NULL, clk_name, parent_names[0], 0,
> +                                       data[0], data[1]);
> +       if (IS_ERR(clk))
> +               goto err;
> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +       return;
> +err:
> +       kfree(parent_names);
> +}

Ditto.

> +
> +static unsigned int hi3620_get_table_maxdiv(const struct clk_div_table *table)
> +{
> +       unsigned int maxdiv = 0;
> +       const struct clk_div_table *clkt;
> +
> +       for (clkt = table; clkt->div; clkt++)
> +               if (clkt->div > maxdiv)
> +                       maxdiv = clkt->div;
> +       return maxdiv;
> +}
> +
> +static unsigned int hi3620_get_table_div(const struct clk_div_table *table,
> +                                                       unsigned int val)
> +{
> +       const struct clk_div_table *clkt;
> +
> +       for (clkt = table; clkt->div; clkt++)
> +               if (clkt->val == val)
> +                       return clkt->div;
> +       return 0;
> +}
> +
> +static unsigned int hi3620_get_table_val(const struct clk_div_table *table,
> +                                        unsigned int div)
> +{
> +       const struct clk_div_table *clkt;
> +
> +       for (clkt = table; clkt->div; clkt++)
> +               if (clkt->div == div)
> +                       return clkt->val;
> +       return 0;
> +}
> +
> +static unsigned long hi3620_clkdiv_recalc_rate(struct clk_hw *hw,
> +                                              unsigned long parent_rate)
> +{
> +       struct hi3620_divclk *dclk = container_of(hw, struct hi3620_divclk, hw);
> +       unsigned int div, val;
> +
> +       val = readl_relaxed(dclk->reg) >> dclk->shift;
> +       val &= WIDTH_TO_MASK(dclk->width);
> +
> +       div = hi3620_get_table_div(dclk->table, val);
> +       if (!div) {
> +               pr_warning("%s: Invalid divisor for clock %s\n", __func__,
> +                          __clk_get_name(hw->clk));
> +               return parent_rate;
> +       }
> +
> +       return parent_rate / div;
> +}
> +
> +static bool hi3620_is_valid_table_div(const struct clk_div_table *table,
> +                                     unsigned int div)
> +{
> +       const struct clk_div_table *clkt;
> +
> +       for (clkt = table; clkt->div; clkt++)
> +               if (clkt->div == div)
> +                       return true;
> +       return false;
> +}
> +
> +static int hi3620_clkdiv_bestdiv(struct clk_hw *hw, unsigned long rate,
> +                                unsigned long *best_parent_rate)
> +{
> +       struct hi3620_divclk *dclk = container_of(hw, struct hi3620_divclk, hw);
> +       struct clk *clk_parent = __clk_get_parent(hw->clk);
> +       int i, bestdiv = 0;
> +       unsigned long parent_rate, best = 0, now, maxdiv;
> +
> +       maxdiv = hi3620_get_table_maxdiv(dclk->table);
> +
> +       if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
> +               parent_rate = *best_parent_rate;
> +               bestdiv = DIV_ROUND_UP(parent_rate, rate);
> +               bestdiv = bestdiv == 0 ? 1 : bestdiv;
> +               bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> +               return bestdiv;
> +       }
> +
> +       /*
> +        * The maximum divider we can use without overflowing
> +        * unsigned long in rate * i below
> +        */
> +       maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> +       for (i = 1; i <= maxdiv; i++) {
> +               if (!hi3620_is_valid_table_div(dclk->table, i))
> +                       continue;
> +               parent_rate = __clk_round_rate(clk_parent,
> +                                              MULT_ROUND_UP(rate, i));
> +               now = parent_rate / i;
> +               if (now <= rate && now > best) {
> +                       bestdiv = i;
> +                       best = now;
> +                       *best_parent_rate = parent_rate;
> +               }
> +       }
> +
> +       if (!bestdiv) {
> +               bestdiv = hi3620_get_table_maxdiv(dclk->table);
> +               *best_parent_rate = __clk_round_rate(clk_parent, 1);
> +       }
> +
> +       return bestdiv;
> +}
> +
> +static long hi3620_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,
> +                                    unsigned long *prate)
> +{
> +       int div;
> +
> +       if (!rate)
> +               rate = 1;
> +       div = hi3620_clkdiv_bestdiv(hw, rate, prate);
> +
> +       return *prate / div;
> +}
> +
> +static int hi3620_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,
> +                                 unsigned long parent_rate)
> +{
> +       struct hi3620_divclk *dclk = container_of(hw, struct hi3620_divclk, hw);
> +       unsigned int div, value;
> +       unsigned long flags = 0;
> +       u32 data;
> +
> +       div = parent_rate / rate;
> +       value = hi3620_get_table_val(dclk->table, div);
> +
> +       if (value > WIDTH_TO_MASK(dclk->width))
> +               value = WIDTH_TO_MASK(dclk->width);
> +
> +       if (dclk->lock)
> +               spin_lock_irqsave(dclk->lock, flags);
> +
> +       data = readl_relaxed(dclk->reg);
> +       data &= ~(WIDTH_TO_MASK(dclk->width) << dclk->shift);
> +       data |= value << dclk->shift;
> +       data |= dclk->mbits;
> +       writel_relaxed(data, dclk->reg);
> +
> +       if (dclk->lock)
> +               spin_unlock_irqrestore(dclk->lock, flags);
> +
> +       return 0;
> +}
> +
> +static struct clk_ops hi3620_clkdiv_ops = {
> +       .recalc_rate = hi3620_clkdiv_recalc_rate,
> +       .round_rate = hi3620_clkdiv_round_rate,
> +       .set_rate = hi3620_clkdiv_set_rate,
> +};
> +
> +void __init hi3620_clkdiv_setup(struct device_node *np)
> +{
> +       struct clk *clk;
> +       const char *clk_name, **parent_names;
> +       struct clk_init_data *init;
> +       struct clk_div_table *table;
> +       struct hi3620_divclk *dclk;
> +       unsigned int table_num;
> +       int i;
> +       u32 data[2];
> +       const char *propname = "hisilicon,clkdiv-table";
> +       const char *cellname = "#hisilicon,clkdiv-table-cells";
> +       struct of_phandle_args div_table;
> +
> +       hs_init_clocks();
> +       if (!hs_clk.sctrl)
> +               return;
> +
> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
> +               return;
> +       if (of_property_read_u32_array(np, "hisilicon,clkdiv",
> +                                      &data[0], 2))
> +               return;
> +
> +       /*process the div_table*/
> +       for (i = 0; ; i++) {
> +               if (of_parse_phandle_with_args(np, propname, cellname,
> +                                              i, &div_table))
> +                       break;
> +       }
> +
> +       /*table ends with <0, 0>, so plus one to table_num*/
> +       table_num = i + 1;
> +
> +       table = kzalloc(sizeof(struct clk_div_table) * table_num, GFP_KERNEL);
> +       if (!table)
> +               return ;
> +
> +       for (i = 0; ; i++) {
> +               if (of_parse_phandle_with_args(np, propname, cellname,
> +                                              i, &div_table))
> +                       break;
> +
> +               table[i].val = div_table.args[0];
> +               table[i].div = div_table.args[1];
> +       }
> +
> +       /* gate only has the fixed parent */
> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> +       if (!parent_names)
> +               goto err_par;
> +       parent_names[0] = of_clk_get_parent_name(np, 0);
> +
> +       dclk = kzalloc(sizeof(*dclk), GFP_KERNEL);
> +       if (!dclk)
> +               goto err_dclk;
> +       init = kzalloc(sizeof(*init), GFP_KERNEL);
> +       if (!init)
> +               goto err_init;
> +       init->name = kstrdup(clk_name, GFP_KERNEL);
> +       init->ops = &hi3620_clkdiv_ops;
> +       init->parent_names = parent_names;
> +       init->num_parents = 1;
> +
> +       dclk->reg = hs_clk.sctrl + data[0];
> +       dclk->shift = ffs(data[1]) - 1;
> +       dclk->width = fls(data[1]) - ffs(data[1]) + 1;
> +       dclk->mbits = data[1] << 16;
> +       dclk->lock = &hs_clk.lock;
> +       dclk->hw.init = init;
> +       dclk->table = table;
> +       clk = clk_register(NULL, &dclk->hw);
> +       if (IS_ERR(clk))
> +               goto err_clk;
> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +       return;
> +err_clk:
> +       kfree(init);
> +err_init:
> +       kfree(dclk);
> +err_dclk:
> +       kfree(parent_names);
> +err_par:
> +       kfree(table);
> +}

This looks like it was copy/pasted from the generic clk-divider type.
Is there some reason you cannot use that instead of duplicating all of
that code here?

Thanks,
Mike

> +CLK_OF_DECLARE(hi3620_mux, "hisilicon,hi3620-clk-mux", hi3620_clkmux_setup)
> +CLK_OF_DECLARE(hi3620_gate, "hisilicon,hi3620-clk-gate", hi3620_clkgate_setup)
> +CLK_OF_DECLARE(hi3620_div, "hisilicon,hi3620-clk-div", hi3620_clkdiv_setup)
> +CLK_OF_DECLARE(hs_gate, "hisilicon,clk-gate", hs_clkgate_setup)
> +CLK_OF_DECLARE(hs_fixed, "hisilicon,clk-fixed-factor", hs_fixed_factor_setup)
> -- 
> 1.7.10.4


From swarren at wwwdotorg.org  Mon May 13 15:47:31 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 13:47:31 -0600
Subject: [PATCH] ARM: tegra: fix memory size on Beaver
Message-ID: <1368474451-11176-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Tegra30's boot ROM masks the top 1MiB of RAM. Fix the memory node in
Beaver's DT file to reflect this.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra30-beaver.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 47b0865..87f0cf5 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -7,7 +7,7 @@
 	compatible = "nvidia,beaver", "nvidia,tegra30";
 
 	memory {
-		reg = <0x80000000 0x80000000>;
+		reg = <0x80000000 0x7ff00000>;
 	};
 
 	pinmux {
-- 
1.7.10.4



From emilio at elopez.com.ar  Mon May 13 15:54:05 2013
From: emilio at elopez.com.ar (=?ISO-8859-1?Q?Emilio_L=F3pez?=)
Date: Mon, 13 May 2013 16:54:05 -0300
Subject: [PATCH] ARM: sunxi: select ARCH_REQUIRE_GPIOLIB
In-Reply-To: <1368435188-26965-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368435188-26965-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <519144DD.1090101@elopez.com.ar>

Hi Maxime,

El 13/05/13 05:53, Maxime Ripard escribi?:
> CONFIG_SUNXI currently doesn't enable a gpiolib, which causes build
> problems when building a kernel with only the sunxi platform enabled.
> Select ARCH_REQUIRE_GPIOLIB to solve this.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-sunxi/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index d259c78..5b045e3 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -1,5 +1,6 @@
>  config ARCH_SUNXI
>  	bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
> +	select ARCH_REQUIRE_GPIOLIB
>  	select CLKSRC_MMIO
>  	select CLKSRC_OF
>  	select COMMON_CLK
> 

Tested-by: Emilio L?pez <emilio at elopez.com.ar>

This fixes the build breakage I was seeing.

Thanks!

Emilio


From sboyd at codeaurora.org  Mon May 13 15:56:33 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:56:33 -0700
Subject: [PATCHv3 0/4] Memory mapped architected timers
Message-ID: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>

This patchset adds support for memory mapped architected timers. We
don't have any other global broadcast timer in our system, so we use the
mmio timer during low power modes. The first patch is the binding.
The next two patches lay some groundwork so that the last patch is simpler.
The final patch adds support for mmio timers.

Patches are based on a patch from Mark that removes the
physical count reading (clocksource: arch_timer: use virtual counter,
message id <1364404312-4427-4-git-send-email-mark.rutland at arm.com>).

Updates since v2:
 * Rebased onto v3.10-rc1

Updates since v1:
 * Assigned counter reading function and commented why for arm64
 * Updated DT binding to replace frame-id with frame-number and use status
   property

Stephen Boyd (4):
  Documentation: Add memory mapped ARM architected timer binding
  clocksource: arch_timer: Pass clock event to set_mode callback
  clocksource: arch_timer: Push the read/write wrappers deeper
  clocksource: arch_timer: Add support for memory mapped timers

 .../devicetree/bindings/arm/arch_timer.txt         |  59 ++-
 arch/arm/include/asm/arch_timer.h                  |   5 +-
 arch/arm64/include/asm/arch_timer.h                |   4 +-
 drivers/clocksource/arm_arch_timer.c               | 452 +++++++++++++++++----
 include/clocksource/arm_arch_timer.h               |   4 +-
 5 files changed, 448 insertions(+), 76 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:56:34 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:56:34 -0700
Subject: [PATCHv3 1/4] Documentation: Add memory mapped ARM architected timer
 binding
In-Reply-To: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
References: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368474997-10859-2-git-send-email-sboyd@codeaurora.org>

Add a binding for the arm architected timer hardware's memory
mapped interface. The mmio timer hardware is made up of one base
frame and a collection of up to 8 timer frames, where each of the
8 timer frames can have either one or two views. A frame
typically maps to a privilege level (user/kernel, hypervisor,
secure). The first view has full access to the registers within a
frame, while the second view can be restricted to particular
registers within a frame. Each frame must support a physical
timer. It's optional for a frame to support a virtual timer.

Cc: devicetree-discuss at lists.ozlabs.org
Cc: Marc Zyngier <Marc.Zyngier at arm.com>
Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Rob Herring <robherring2 at gmail.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 .../devicetree/bindings/arm/arch_timer.txt         | 59 ++++++++++++++++++++--
 1 file changed, 56 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index 20746e5..06fc760 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -1,10 +1,14 @@
 * ARM architected timer
 
-ARM cores may have a per-core architected timer, which provides per-cpu timers.
+ARM cores may have a per-core architected timer, which provides per-cpu timers,
+or a memory mapped architected timer, which provides up to 8 frames with a
+physical and optional virtual timer per frame.
 
-The timer is attached to a GIC to deliver its per-processor interrupts.
+The per-core architected timer is attached to a GIC to deliver its
+per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
+to deliver its interrupts via SPIs.
 
-** Timer node properties:
+** CP15 Timer node properties:
 
 - compatible : Should at least contain one of
 	"arm,armv7-timer"
@@ -26,3 +30,52 @@ Example:
 			     <1 10 0xf08>;
 		clock-frequency = <100000000>;
 	};
+
+** Memory mapped timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer-mem".
+
+- clock-frequency : The frequency of the main counter, in Hz. Optional.
+
+- reg : The control frame base address.
+
+Note that #address-cells, #size-cells, and ranges shall be present to ensure
+the CPU can address a frame's registers.
+
+A timer node has up to 8 frame sub-nodes, each with the following properties:
+
+- frame-number: 0 to 7.
+
+- interrupts : Interrupt list for physical and virtual timers in that order.
+  The virtual timer interrupt is optional.
+
+- reg : The first and second view base addresses in that order. The second view
+  base address is optional.
+
+- status : "disabled" indicates the frame is not available for use. Optional.
+
+Example:
+
+	timer at f0000000 {
+		compatible = "arm,armv7-timer-mem";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		reg = <0xf0000000 0x1000>;
+		clock-frequency = <50000000>;
+
+		frame at f0001000 {
+			frame-number = <0>
+			interrupts = <0 13 0x8>,
+				     <0 14 0x8>;
+			reg = <0xf0001000 0x1000>,
+			      <0xf0002000 0x1000>;
+		};
+
+		frame at f0003000 {
+			frame-number = <1>
+			interrupts = <0 15 0x8>;
+			reg = <0xf0003000 0x1000>;
+			status = "disabled";
+		};
+	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:56:35 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:56:35 -0700
Subject: [PATCHv3 2/4] clocksource: arch_timer: Pass clock event to set_mode
 callback
In-Reply-To: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
References: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368474997-10859-3-git-send-email-sboyd@codeaurora.org>

There isn't any reason why we don't pass the event here and we'll
need it in the near future for memory mapped arch timers anyway.

Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Marc Zyngier <Marc.Zyngier at arm.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/arm_arch_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 053d846..220da0c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -140,7 +140,7 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 
 	clk->cpumask = cpumask_of(smp_processor_id());
 
-	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
+	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
 
 	clockevents_config_and_register(clk, arch_timer_rate,
 					0xf, 0x7fffffff);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:56:37 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:56:37 -0700
Subject: [PATCHv3 4/4] clocksource: arch_timer: Add support for memory mapped
 timers
In-Reply-To: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
References: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368474997-10859-5-git-send-email-sboyd@codeaurora.org>

Add support for the memory mapped timers by filling in the
read/write functions and adding some parsing code. Note that we
only register one clocksource, preferring the cp15 based
clocksource over the mmio one.

To keep things simple we register one global clockevent. This
covers the case of UP and SMP systems with only mmio hardware and
systems where the memory mapped timers are used as the broadcast
timer in low power modes.

The DT binding allows for per-CPU memory mapped timers in case we
want to support that in the future, but the code isn't added
here. We also don't do much for hypervisor support, although it
should be possible to support it by searching for at least two
frames where one frame has the virtual capability and then
updating KVM timers to support it.

Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Marc Zyngier <Marc.Zyngier at arm.com>
Cc: Rob Herring <robherring2 at gmail.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/clocksource/arm_arch_timer.c | 412 ++++++++++++++++++++++++++++++-----
 include/clocksource/arm_arch_timer.h |   4 +-
 2 files changed, 360 insertions(+), 56 deletions(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 3de030a..78a9479 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -16,13 +16,39 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <asm/arch_timer.h>
 #include <asm/virt.h>
 
 #include <clocksource/arm_arch_timer.h>
 
+#define CNTTIDR		0x08
+#define CNTTIDR_VIRT(n)	(BIT(1) << ((n) * 4))
+
+#define CNTVCT_LO	0x08
+#define CNTVCT_HI	0x0c
+#define CNTFRQ		0x10
+#define CNTP_TVAL	0x28
+#define CNTP_CTL	0x2c
+#define CNTV_TVAL	0x38
+#define CNTV_CTL	0x3c
+
+#define ARCH_CP15_TIMER	BIT(0)
+#define ARCH_MEM_TIMER	BIT(1)
+static unsigned arch_timers_present __initdata;
+
+static void __iomem *arch_counter_base;
+
+struct arch_timer {
+	void __iomem *base;
+	struct clock_event_device evt;
+};
+
+#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
+
 static u32 arch_timer_rate;
 
 enum ppi_nr {
@@ -38,6 +64,7 @@ static int arch_timer_ppi[MAX_TIMER_PPI];
 static struct clock_event_device __percpu *arch_timer_evt;
 
 static bool arch_timer_use_virtual = true;
+static bool arch_timer_mem_use_virtual;
 
 /*
  * Architected system timer support.
@@ -46,13 +73,69 @@ static bool arch_timer_use_virtual = true;
 static inline void arch_timer_reg_write(int access, int reg, u32 val,
 					struct clock_event_device *clk)
 {
-	arch_timer_reg_write_cp15(access, reg, val);
+	if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
+		struct arch_timer *timer = to_arch_timer(clk);
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			writel_relaxed(val, timer->base + CNTP_CTL);
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			writel_relaxed(val, timer->base + CNTP_TVAL);
+			break;
+		default:
+			BUILD_BUG();
+		}
+	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
+		struct arch_timer *timer = to_arch_timer(clk);
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			writel_relaxed(val, timer->base + CNTV_CTL);
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			writel_relaxed(val, timer->base + CNTV_TVAL);
+			break;
+		default:
+			BUILD_BUG();
+		}
+	} else {
+		arch_timer_reg_write_cp15(access, reg, val);
+	}
 }
 
 static inline u32 arch_timer_reg_read(int access, int reg,
 				      struct clock_event_device *clk)
 {
-	return arch_timer_reg_read_cp15(access, reg);
+	u32 val;
+
+	if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
+		struct arch_timer *timer = to_arch_timer(clk);
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			val = readl_relaxed(timer->base + CNTP_CTL);
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			val = readl_relaxed(timer->base + CNTP_TVAL);
+			break;
+		default:
+			BUILD_BUG();
+		}
+	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
+		struct arch_timer *timer = to_arch_timer(clk);
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			val = readl_relaxed(timer->base + CNTV_CTL);
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			val = readl_relaxed(timer->base + CNTV_TVAL);
+			break;
+		default:
+			BUILD_BUG();
+		}
+	} else {
+		val = arch_timer_reg_read_cp15(access, reg);
+	}
+
+	return val;
 }
 
 static inline irqreturn_t timer_handler(const int access,
@@ -84,6 +167,20 @@ static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 }
 
+static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
+}
+
+static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
+}
+
 static inline void timer_set_mode(const int access, int mode,
 				  struct clock_event_device *clk)
 {
@@ -112,6 +209,18 @@ static void arch_timer_set_mode_phys(enum clock_event_mode mode,
 	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
 }
 
+static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
+					 struct clock_event_device *clk)
+{
+	timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
+}
+
+static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
+					 struct clock_event_device *clk)
+{
+	timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
+}
+
 static inline void set_next_event(const int access, unsigned long evt,
 				  struct clock_event_device *clk)
 {
@@ -137,27 +246,62 @@ static int arch_timer_set_next_event_phys(unsigned long evt,
 	return 0;
 }
 
-static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
+static int arch_timer_set_next_event_virt_mem(unsigned long evt,
+					      struct clock_event_device *clk)
 {
-	clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
-	clk->name = "arch_sys_timer";
-	clk->rating = 450;
-	if (arch_timer_use_virtual) {
-		clk->irq = arch_timer_ppi[VIRT_PPI];
-		clk->set_mode = arch_timer_set_mode_virt;
-		clk->set_next_event = arch_timer_set_next_event_virt;
+	set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
+	return 0;
+}
+
+static int arch_timer_set_next_event_phys_mem(unsigned long evt,
+					      struct clock_event_device *clk)
+{
+	set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
+	return 0;
+}
+
+static void __cpuinit __arch_timer_setup(unsigned type,
+				       struct clock_event_device *clk)
+{
+	clk->features = CLOCK_EVT_FEAT_ONESHOT;
+
+	if (type == ARCH_CP15_TIMER) {
+		clk->features |= CLOCK_EVT_FEAT_C3STOP;
+		clk->name = "arch_sys_timer";
+		clk->rating = 450;
+		clk->cpumask = cpumask_of(smp_processor_id());
+		if (arch_timer_use_virtual) {
+			clk->irq = arch_timer_ppi[VIRT_PPI];
+			clk->set_mode = arch_timer_set_mode_virt;
+			clk->set_next_event = arch_timer_set_next_event_virt;
+		} else {
+			clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
+			clk->set_mode = arch_timer_set_mode_phys;
+			clk->set_next_event = arch_timer_set_next_event_phys;
+		}
 	} else {
-		clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
-		clk->set_mode = arch_timer_set_mode_phys;
-		clk->set_next_event = arch_timer_set_next_event_phys;
+		clk->name = "arch_mem_timer";
+		clk->rating = 400;
+		clk->cpumask = cpu_all_mask;
+		if (arch_timer_mem_use_virtual) {
+			clk->set_mode = arch_timer_set_mode_virt_mem;
+			clk->set_next_event =
+				arch_timer_set_next_event_virt_mem;
+		} else {
+			clk->set_mode = arch_timer_set_mode_phys_mem;
+			clk->set_next_event =
+				arch_timer_set_next_event_phys_mem;
+		}
 	}
 
-	clk->cpumask = cpumask_of(smp_processor_id());
-
 	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
 
-	clockevents_config_and_register(clk, arch_timer_rate,
-					0xf, 0x7fffffff);
+	clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
+}
+
+static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
+{
+	__arch_timer_setup(ARCH_CP15_TIMER, clk);
 
 	if (arch_timer_use_virtual)
 		enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
@@ -172,27 +316,41 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 	return 0;
 }
 
-static int arch_timer_available(void)
+static void
+arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
 {
-	u32 freq;
-
-	if (arch_timer_rate == 0) {
-		freq = arch_timer_get_cntfrq();
-
-		/* Check the timer frequency. */
-		if (freq == 0) {
-			pr_warn("Architected timer frequency not available\n");
-			return -EINVAL;
-		}
+	/* Who has more than one independent system counter? */
+	if (arch_timer_rate)
+		return;
 
-		arch_timer_rate = freq;
+	/* Try to determine the frequency from the device tree or CNTFRQ */
+	if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
+		if (cntbase)
+			arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
+		else
+			arch_timer_rate = arch_timer_get_cntfrq();
 	}
 
-	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
+	/* Check the timer frequency. */
+	if (arch_timer_rate == 0)
+		pr_warn("Architected timer frequency not available\n");
+}
+
+static void arch_timer_banner(unsigned type)
+{
+	pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
+		     type & ARCH_CP15_TIMER ? "cp15" : "",
+		     type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  " and " : "",
+		     type & ARCH_MEM_TIMER ? "mmio" : "",
 		     (unsigned long)arch_timer_rate / 1000000,
 		     (unsigned long)(arch_timer_rate / 10000) % 100,
-		     arch_timer_use_virtual ? "virt" : "phys");
-	return 0;
+		     type & ARCH_CP15_TIMER ?
+			arch_timer_use_virtual ? "virt" : "phys" :
+			"",
+		     type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  "/" : "",
+		     type & ARCH_MEM_TIMER ?
+			arch_timer_mem_use_virtual ? "virt" : "phys" :
+			"");
 }
 
 u32 arch_timer_get_rate(void)
@@ -200,19 +358,35 @@ u32 arch_timer_get_rate(void)
 	return arch_timer_rate;
 }
 
-u64 arch_timer_read_counter(void)
+static u64 arch_counter_get_cntvct_mem(void)
 {
-	return arch_counter_get_cntvct();
+	u32 vct_lo, vct_hi, tmp_hi;
+
+	do {
+		vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
+		vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
+		tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
+	} while (vct_hi != tmp_hi);
+
+	return ((u64) vct_hi << 32) | vct_lo;
 }
 
+/*
+ * Default to cp15 based access because arm64 uses this function for
+ * sched_clock() before DT is probed and the cp15 method is guaranteed
+ * to exist on arm64. arm doesn't use this before DT is probed so even
+ * if we don't have the cp15 accessors we won't have a problem.
+ */
+u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
+
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
-	return arch_counter_get_cntvct();
+	return arch_timer_read_counter();
 }
 
 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
 {
-	return arch_counter_get_cntvct();
+	return arch_timer_read_counter();
 }
 
 static struct clocksource clocksource_counter = {
@@ -235,6 +409,23 @@ struct timecounter *arch_timer_get_timecounter(void)
 	return &timecounter;
 }
 
+static void __init arch_counter_register(unsigned type)
+{
+	u64 start_count;
+
+	/* Register the CP15 based counter if we have one */
+	if (type & ARCH_CP15_TIMER)
+		arch_timer_read_counter = arch_counter_get_cntvct;
+	else
+		arch_timer_read_counter = arch_counter_get_cntvct_mem;
+
+	start_count = arch_timer_read_counter();
+	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+	cyclecounter.mult = clocksource_counter.mult;
+	cyclecounter.shift = clocksource_counter.shift;
+	timecounter_init(&timecounter, &cyclecounter, start_count);
+}
+
 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
 	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
@@ -279,22 +470,12 @@ static int __init arch_timer_register(void)
 	int err;
 	int ppi;
 
-	err = arch_timer_available();
-	if (err)
-		goto out;
-
 	arch_timer_evt = alloc_percpu(struct clock_event_device);
 	if (!arch_timer_evt) {
 		err = -ENOMEM;
 		goto out;
 	}
 
-	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
-	cyclecounter.mult = clocksource_counter.mult;
-	cyclecounter.shift = clocksource_counter.shift;
-	timecounter_init(&timecounter, &cyclecounter,
-			 arch_counter_get_cntvct());
-
 	if (arch_timer_use_virtual) {
 		ppi = arch_timer_ppi[VIRT_PPI];
 		err = request_percpu_irq(ppi, arch_timer_handler_virt,
@@ -345,24 +526,77 @@ out:
 	return err;
 }
 
+static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
+{
+	int ret;
+	irq_handler_t func;
+	struct arch_timer *t;
+
+	t = kzalloc(sizeof(*t), GFP_KERNEL);
+	if (!t)
+		return -ENOMEM;
+
+	t->base = base;
+	t->evt.irq = irq;
+	__arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
+
+	if (arch_timer_mem_use_virtual)
+		func = arch_timer_handler_virt_mem;
+	else
+		func = arch_timer_handler_phys_mem;
+
+	ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
+	if (ret) {
+		pr_err("arch_timer: Failed to request mem timer irq\n");
+		kfree(t);
+	}
+
+	return ret;
+}
+
+static const struct of_device_id arch_timer_of_match[] __initconst = {
+	{ .compatible   = "arm,armv7-timer",    },
+	{ .compatible   = "arm,armv8-timer",    },
+	{},
+};
+
+static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
+	{ .compatible   = "arm,armv7-timer-mem", },
+	{},
+};
+
+static void __init arch_timer_common_init(void)
+{
+	unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
+
+	/* Wait until both nodes are probed if we have two timers */
+	if ((arch_timers_present & mask) != mask) {
+		if (of_find_matching_node(NULL, arch_timer_mem_of_match) &&
+				!(arch_timers_present & ARCH_MEM_TIMER))
+			return;
+		if (of_find_matching_node(NULL, arch_timer_of_match) &&
+				!(arch_timers_present & ARCH_CP15_TIMER))
+			return;
+	}
+
+	arch_timer_banner(arch_timers_present);
+	arch_counter_register(arch_timers_present);
+	arch_timer_arch_init();
+}
+
 static void __init arch_timer_init(struct device_node *np)
 {
-	u32 freq;
 	int i;
 
-	if (arch_timer_get_rate()) {
+	if (arch_timers_present & ARCH_CP15_TIMER) {
 		pr_warn("arch_timer: multiple nodes in dt, skipping\n");
 		return;
 	}
 
-	/* Try to determine the frequency from the device tree or CNTFRQ */
-	if (!of_property_read_u32(np, "clock-frequency", &freq))
-		arch_timer_rate = freq;
-
+	arch_timers_present |= ARCH_CP15_TIMER;
 	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
 		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
-
-	of_node_put(np);
+	arch_timer_detect_rate(NULL, np);
 
 	/*
 	 * If HYP mode is available, we know that the physical timer
@@ -383,7 +617,75 @@ static void __init arch_timer_init(struct device_node *np)
 	}
 
 	arch_timer_register();
-	arch_timer_arch_init();
+	arch_timer_common_init();
 }
 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
+
+static void __init arch_timer_mem_init(struct device_node *np)
+{
+	struct device_node *frame, *best_frame = NULL;
+	void __iomem *cntctlbase, *base;
+	unsigned int irq;
+	u32 cnttidr;
+
+	arch_timers_present |= ARCH_MEM_TIMER;
+	cntctlbase = of_iomap(np, 0);
+	if (!cntctlbase) {
+		pr_err("arch_timer: Can't find CNTCTLBase\n");
+		return;
+	}
+
+	cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
+	iounmap(cntctlbase);
+
+	/*
+	 * Try to find a virtual capable frame. Otherwise fall back to a
+	 * physical capable frame.
+	 */
+	for_each_available_child_of_node(np, frame) {
+		int n;
+
+		if (of_property_read_u32(frame, "frame-number", &n)) {
+			pr_err("arch_timer: Missing frame-number\n");
+			of_node_put(best_frame);
+			of_node_put(frame);
+			return;
+		}
+
+		if (cnttidr & CNTTIDR_VIRT(n)) {
+			of_node_put(best_frame);
+			best_frame = frame;
+			arch_timer_mem_use_virtual = true;
+			break;
+		}
+		of_node_put(best_frame);
+		best_frame = of_node_get(frame);
+	}
+
+	base = arch_counter_base = of_iomap(best_frame, 0);
+	if (!base) {
+		pr_err("arch_timer: Can't map frame's registers\n");
+		of_node_put(best_frame);
+		return;
+	}
+
+	if (arch_timer_mem_use_virtual)
+		irq = irq_of_parse_and_map(best_frame, 1);
+	else
+		irq = irq_of_parse_and_map(best_frame, 0);
+	if (!irq) {
+		pr_err("arch_timer: Frame missing %s irq",
+				arch_timer_mem_use_virtual ? "virt" : "phys");
+		of_node_put(best_frame);
+		return;
+	}
+
+	arch_timer_detect_rate(base, best_frame);
+	of_node_put(best_frame);
+
+	arch_timer_mem_register(base, irq);
+	arch_timer_common_init();
+}
+CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
+		       arch_timer_mem_init);
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index c463ce9..ae53fa1 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -28,11 +28,13 @@
 
 #define ARCH_TIMER_PHYS_ACCESS		0
 #define ARCH_TIMER_VIRT_ACCESS		1
+#define ARCH_TIMER_MEM_PHYS_ACCESS	2
+#define ARCH_TIMER_MEM_VIRT_ACCESS	3
 
 #ifdef CONFIG_ARM_ARCH_TIMER
 
 extern u32 arch_timer_get_rate(void);
-extern u64 arch_timer_read_counter(void);
+extern u64 (*arch_timer_read_counter)(void);
 extern struct timecounter *arch_timer_get_timecounter(void);
 
 #else
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 13 15:56:36 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 May 2013 12:56:36 -0700
Subject: [PATCHv3 3/4] clocksource: arch_timer: Push the read/write wrappers
 deeper
In-Reply-To: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
References: <1368474997-10859-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1368474997-10859-4-git-send-email-sboyd@codeaurora.org>

We're going to introduce support to read and write the memory
mapped timer registers in the next patch, so push the cp15
read/write functions one level deeper. This simplifies the next
patch and makes it clearer what's going on.

Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Marc Zyngier <Marc.Zyngier at arm.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/include/asm/arch_timer.h    |  5 ++--
 arch/arm64/include/asm/arch_timer.h  |  4 ++--
 drivers/clocksource/arm_arch_timer.c | 44 ++++++++++++++++++++++++------------
 3 files changed, 34 insertions(+), 19 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index accefe0..6c0e297 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -17,7 +17,8 @@ int arch_timer_arch_init(void);
  * nicely work out which register we want, and chuck away the rest of
  * the code. At least it does so with a recent GCC (4.6.3).
  */
-static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
+static inline void arch_timer_reg_write_cp15(const int access, const int reg,
+					  u32 val)
 {
 	if (access == ARCH_TIMER_PHYS_ACCESS) {
 		switch (reg) {
@@ -44,7 +45,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
 	isb();
 }
 
-static inline u32 arch_timer_reg_read(const int access, const int reg)
+static inline u32 arch_timer_reg_read_cp15(const int access, const int reg)
 {
 	u32 val = 0;
 
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index d56ed11..1cd3c55 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -26,7 +26,7 @@
 
 #include <clocksource/arm_arch_timer.h>
 
-static inline void arch_timer_reg_write(int access, int reg, u32 val)
+static inline void arch_timer_reg_write_cp15(int access, int reg, u32 val)
 {
 	if (access == ARCH_TIMER_PHYS_ACCESS) {
 		switch (reg) {
@@ -57,7 +57,7 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val)
 	isb();
 }
 
-static inline u32 arch_timer_reg_read(int access, int reg)
+static inline u32 arch_timer_reg_read_cp15(int access, int reg)
 {
 	u32 val;
 
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 220da0c..3de030a 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -43,14 +43,26 @@ static bool arch_timer_use_virtual = true;
  * Architected system timer support.
  */
 
+static inline void arch_timer_reg_write(int access, int reg, u32 val,
+					struct clock_event_device *clk)
+{
+	arch_timer_reg_write_cp15(access, reg, val);
+}
+
+static inline u32 arch_timer_reg_read(int access, int reg,
+				      struct clock_event_device *clk)
+{
+	return arch_timer_reg_read_cp15(access, reg);
+}
+
 static inline irqreturn_t timer_handler(const int access,
 					struct clock_event_device *evt)
 {
 	unsigned long ctrl;
-	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
 	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 		evt->event_handler(evt);
 		return IRQ_HANDLED;
 	}
@@ -72,15 +84,16 @@ static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 }
 
-static inline void timer_set_mode(const int access, int mode)
+static inline void timer_set_mode(const int access, int mode,
+				  struct clock_event_device *clk)
 {
 	unsigned long ctrl;
 	switch (mode) {
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
-		ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+		ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
-		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 		break;
 	default:
 		break;
@@ -90,36 +103,37 @@ static inline void timer_set_mode(const int access, int mode)
 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
 				     struct clock_event_device *clk)
 {
-	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
+	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
 }
 
 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
 				     struct clock_event_device *clk)
 {
-	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
+	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
 }
 
-static inline void set_next_event(const int access, unsigned long evt)
+static inline void set_next_event(const int access, unsigned long evt,
+				  struct clock_event_device *clk)
 {
 	unsigned long ctrl;
-	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 	ctrl |= ARCH_TIMER_CTRL_ENABLE;
 	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
-	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
-	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
+	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 }
 
 static int arch_timer_set_next_event_virt(unsigned long evt,
-					  struct clock_event_device *unused)
+					  struct clock_event_device *clk)
 {
-	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
+	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 	return 0;
 }
 
 static int arch_timer_set_next_event_phys(unsigned long evt,
-					  struct clock_event_device *unused)
+					  struct clock_event_device *clk)
 {
-	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
+	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 	return 0;
 }
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From mturquette at linaro.org  Mon May 13 15:57:46 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Mon, 13 May 2013 12:57:46 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130513195746.10068.92303@quantum>

Quoting James Hogan (2013-04-19 09:28:21)
> This patchset adds support for automatic selection of the best parent
> for a clock mux, i.e. the one which can provide the closest clock rate
> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
> so that it doesn't happen unless explicitly allowed.
> 

I'm not sure about the new flag.  One of my regrets during the early
development of the common struct clk is the CLK_SET_RATE_PARENT flag.
In hindsight I would have preferred to make parent-propagation of rate
changes the default behavior, and instead provide a flag to prevent that
behavior, such as CLK_SET_RATE_NO_PROPAGATE.

One reason for this is the difficulty some have had with setting flags
from DT bindings.  Another reason is that a core goal of the framework
is to remove topology info from drivers; having to set a flag explicitly
on each clock to propagate rate changes is an impediment to that goal.

So perhaps CLK_SET_RATE_REMUX is a similar situation.  What do you think
about making remuxing the default and providing a flag to prevent it?
And also we can assume for the immediate future that users of
.determine_rate WANT to remux, since .round_rate won't do it.  Though
eventually it might be wise to convert all users of .round_rate over to
.determine_rate and deprecate .round_rate entirely.

Regards,
Mike

> This works by way of adding a new op, determine_rate, similar to
> round_rate but with an extra parameter to allow the clock driver to
> optionally select a different parent clock. This is used in
> clk_calc_new_rates to decide whether to initiate a set_parent operation.
> 
> Changes in v2:
> 
> I've moved the mux determine_rate implementation into a core helper, but
> I haven't pushed it fully into the core, as I think it just wouldn't
> work correctly for more complex clocks, e.g. if you (theoretically) had
> a combined mux and divide, you'd want to intercept the determine_rate
> and ask for a larger rate from the parent clocks, then return the
> divided rate. This should be possible by wrapping the mux determine_rate
> helper.
> 
> Patch 1 still exports the __clk_get_parent_by_index as it seems like it
> might be a useful thing for clock implementations to have access to if
> they ever wanted to do something more fancy with changing clock parents.
> 
> I haven't made any attempt to implement the atomic set_parent+set_rate
> as I don't have hardware that could take proper advantage of it, but it
> shouldn't be too difficult for others to implement if they wanted since
> they're fairly close to one another (in clk_change_rate()).
> 
> * switched to using new determine_rate op rather than adding an argument
>   to round_rate.
> * moved mux implementation into a single helper which should be usable
>   from more complex clocks which can mux.
> * rewrite main implementation so that no changes are made until after
>   the PRE notifications have been sent, and in a way that should ensure
>   correct notifications without duplicates, and I think should be safe
>   in the event of a notification failing.
> * various tidy ups and fixes.
> 
> James Hogan (3):
>   clk: abstract parent cache
>   clk: add support for clock reparent on set_rate
>   clk: clk-mux: implement remuxing on set_rate
> 
>  Documentation/clk.txt        |   4 +
>  drivers/clk/clk-mux.c        |   1 +
>  drivers/clk/clk.c            | 216 +++++++++++++++++++++++++++++++++----------
>  include/linux/clk-private.h  |   2 +
>  include/linux/clk-provider.h |  12 +++
>  5 files changed, 185 insertions(+), 50 deletions(-)
> 
> -- 
> 1.8.1.2


From jason at lakedaemon.net  Mon May 13 16:00:02 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:00:02 -0400
Subject: [PATCH] pinctrl: dove: add PMU functions to pinctrl
In-Reply-To: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130513200002.GY31290@titan.lakedaemon.net>

On Tue, May 07, 2013 at 01:36:08AM +0200, Sebastian Hesselbarth wrote:
> Dove power management unit can mux some special functions to mpp0-15.
> This patch adds support to set/get the current PMU function mapped
> to the corresponding mpp pins. The device tree documentation is also
> updated accordingly.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Stephen Warren <swarren at wwwdotorg.org>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   49 ++--
>  drivers/pinctrl/mvebu/pinctrl-dove.c               |  244 +++++++++++++++++---
>  2 files changed, 249 insertions(+), 44 deletions(-)

Sebastian,

Do you intend to have anything depending on these changes in this merge
window?

thx,

Jason.


From mturquette at linaro.org  Mon May 13 16:01:23 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Mon, 13 May 2013 13:01:23 -0700
Subject: [PATCH v2 1/3] clk: abstract parent cache
In-Reply-To: <1366388904-13903-2-git-send-email-james.hogan@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <1366388904-13903-2-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130513200123.10068.57183@quantum>

Quoting James Hogan (2013-04-19 09:28:22)
> Abstract access to the clock parent cache by defining
> __clk_get_parent_by_index(clk, index). This allows access to parent
> clocks from clock drivers.
> 
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> ---
>  drivers/clk/clk.c            | 21 ++++++++++++++-------
>  include/linux/clk-provider.h |  1 +
>  2 files changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index ed87b24..79d5deb 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -415,6 +415,19 @@ struct clk *__clk_get_parent(struct clk *clk)
>         return !clk ? NULL : clk->parent;
>  }
>  
> +struct clk *__clk_get_parent_by_index(struct clk *clk, u8 index)

This looks good, but in the next version can you remove the double
underscore?  I'm getting rid of a lot of those double underscore
helpers now that the reentrancy patch is merged and I think this is a
reasonable top-level API for a clock provider to have.

Thanks,
Mike

> +{
> +       if (!clk || index >= clk->num_parents)
> +               return NULL;
> +       else if (!clk->parents)
> +               return __clk_lookup(clk->parent_names[index]);
> +       else if (!clk->parents[index])
> +               return clk->parents[index] =
> +                       __clk_lookup(clk->parent_names[index]);
> +       else
> +               return clk->parents[index];
> +}
> +
>  unsigned int __clk_get_enable_count(struct clk *clk)
>  {
>         return !clk ? 0 : clk->enable_count;
> @@ -1150,13 +1163,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
>                         kzalloc((sizeof(struct clk*) * clk->num_parents),
>                                         GFP_KERNEL);
>  
> -       if (!clk->parents)
> -               ret = __clk_lookup(clk->parent_names[index]);
> -       else if (!clk->parents[index])
> -               ret = clk->parents[index] =
> -                       __clk_lookup(clk->parent_names[index]);
> -       else
> -               ret = clk->parents[index];
> +       ret = __clk_get_parent_by_index(clk, index);
>  
>  out:
>         return ret;
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 7f197d7..4e0b634 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -347,6 +347,7 @@ const char *__clk_get_name(struct clk *clk);
>  struct clk_hw *__clk_get_hw(struct clk *clk);
>  u8 __clk_get_num_parents(struct clk *clk);
>  struct clk *__clk_get_parent(struct clk *clk);
> +struct clk *__clk_get_parent_by_index(struct clk *clk, u8 index);
>  unsigned int __clk_get_enable_count(struct clk *clk);
>  unsigned int __clk_get_prepare_count(struct clk *clk);
>  unsigned long __clk_get_rate(struct clk *clk);
> -- 
> 1.8.1.2


From sebastian.hesselbarth at gmail.com  Mon May 13 16:03:57 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 13 May 2013 22:03:57 +0200
Subject: [PATCH] pinctrl: dove: add PMU functions to pinctrl
In-Reply-To: <20130513200002.GY31290@titan.lakedaemon.net>
References: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130513200002.GY31290@titan.lakedaemon.net>
Message-ID: <5191472D.7060601@gmail.com>

On 05/13/2013 10:00 PM, Jason Cooper wrote:
> On Tue, May 07, 2013 at 01:36:08AM +0200, Sebastian Hesselbarth wrote:
>> Dove power management unit can mux some special functions to mpp0-15.
>> This patch adds support to set/get the current PMU function mapped
>> to the corresponding mpp pins. The device tree documentation is also
>> updated accordingly.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>
> Do you intend to have anything depending on these changes in this merge
> window?

Jason,

I don't. There will be pmu and pmic support someday but I am not working
on it.

Sebastian


From jason at lakedaemon.net  Mon May 13 16:08:10 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:08:10 -0400
Subject: [PATCH] ARM: mvebu: Add support for USB storage class in
 mvebu_defconfig
In-Reply-To: <1366228294-24437-1-git-send-email-ezequiel.garcia@free-electrons.com>
References: <1366228294-24437-1-git-send-email-ezequiel.garcia@free-electrons.com>
Message-ID: <20130513200810.GZ31290@titan.lakedaemon.net>

On Wed, Apr 17, 2013 at 04:51:34PM -0300, Ezequiel Garcia wrote:
> Some boards can have built-in USB storage class controllers so
> it's better to have this option included by default.
> 
> Currently this option is needed to support built-in USB MMC controller
> found in Globalscale Mirabox board.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> ---
> This is not important and can be delayed for v3.11 if it's already
> too late for v3.10. The change is harmless in any case.
> 
>  arch/arm/configs/mvebu_defconfig | 1 +
>  1 file changed, 1 insertion(+)

Applied to mvebu/defconfig

thx,

Jason.


From csd at broadcom.com  Mon May 13 16:06:30 2013
From: csd at broadcom.com (Christian Daudt)
Date: Mon, 13 May 2013 13:06:30 -0700
Subject: [PATCH 06/14] ARM: bcm281xx: Remove init_irq declaration in
 machine description
In-Reply-To: <1368438253-28218-7-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-7-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <519147C6.6080004@broadcom.com>

On 13-05-13 02:44 AM, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for bcm281xx as well.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>   arch/arm/mach-bcm/board_bcm.c | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
> index 22e8421..24556cf 100644
> --- a/arch/arm/mach-bcm/board_bcm.c
> +++ b/arch/arm/mach-bcm/board_bcm.c
> @@ -54,7 +54,6 @@ static void __init board_init(void)
>   static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
>   
>   DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
> -	.init_irq = irqchip_init,
>   	.init_time = clocksource_of_init,
>   	.init_machine = board_init,
>   	.dt_compat = bcm11351_dt_compat,
Acked-by: Christian Daudt <csd at broadcom.com>


  thanks,
    csd




From jason at lakedaemon.net  Mon May 13 16:10:15 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:10:15 -0400
Subject: [PATCH] pinctrl: dove: add PMU functions to pinctrl
In-Reply-To: <5191472D.7060601@gmail.com>
References: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130513200002.GY31290@titan.lakedaemon.net>
 <5191472D.7060601@gmail.com>
Message-ID: <20130513201015.GA31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 10:03:57PM +0200, Sebastian Hesselbarth wrote:
> On 05/13/2013 10:00 PM, Jason Cooper wrote:
> >On Tue, May 07, 2013 at 01:36:08AM +0200, Sebastian Hesselbarth wrote:
> >>Dove power management unit can mux some special functions to mpp0-15.
> >>This patch adds support to set/get the current PMU function mapped
> >>to the corresponding mpp pins. The device tree documentation is also
> >>updated accordingly.
> >>
> >>Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> >
> >Do you intend to have anything depending on these changes in this merge
> >window?
> 
> I don't. There will be pmu and pmic support someday but I am not working
> on it.

Ok, in that case, assuming LinusW is ok with it:

Acked-by: Jason Cooper <jason at lakedaemon.net>

thx,

Jason.


From jason at lakedaemon.net  Mon May 13 16:12:34 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:12:34 -0400
Subject: [PATCH] drivers: memory: Introduce Marvell EBU Device Bus driver
In-Reply-To: <20130423195556.GA3335@localhost>
References: <1366744886-3019-1-git-send-email-elezegarcia@gmail.com>
 <20130423194822.GA7214@kroah.com> <20130423195556.GA3335@localhost>
Message-ID: <20130513201234.GB31290@titan.lakedaemon.net>

On Tue, Apr 23, 2013 at 04:55:58PM -0300, Ezequiel Garcia wrote:
> On Tue, Apr 23, 2013 at 12:48:22PM -0700, Greg KH wrote:
> > On Tue, Apr 23, 2013 at 04:21:26PM -0300, Ezequiel Garcia wrote:
> > > From: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> > > 
> > > Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and
> > > Discovery (mv78xx0) supports a Device Bus controller to access several
> > > kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA).
> > > 
> > > This commit adds a driver to handle this controller. So far only
> > > Armada 370, Armada XP and Discovery SoCs are supported.
> > > 
> > > The driver must be registered through a device tree node;
> > > as explained in the binding document.
> > > 
> > > For each child node in the device tree, this driver will:
> > >   * set timing parameters
> > >   * register a child device
> > >   * setup an address decoding window, using the mbus driver
> > > 
> > > Keep in mind the address decoding window setup is only a temporary hack.
> > > This code will be removed from this devbus driver as soon as a proper device
> > > tree binding for the mbus driver is added.
> > > 
> > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> > > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > > ---
> > > Hi Greg,
> > > 
> > > This patch Applies on today linux-next.
> > > I don't know if we are still in time for you to take this
> > > and merge it into v3.10.
> > > 
> > > All of the DT related changes are in linux-next through arm-soc,
> > > but this driver was left out and, unless you take it, will
> > > get queued for v3.11. So it's up to you.
> > 
> > It's way too late for new drivers for 3.10, sorry.  I'll hold on to this
> > and merge it to my trees after 3.10-rc1 is out for inclusion in 3.11.
> > 
> 
> That's fine, no problem.

Ezequiel,

I'm dropping this from my tree as Greg has said he would take it.

thx,

Jason.


From jason at lakedaemon.net  Mon May 13 16:20:56 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:20:56 -0400
Subject: [PATCH] ARM: dove: add si5351 clock driver to CuBox DT
In-Reply-To: <1367342675-15312-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367342675-15312-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130513202056.GC31290@titan.lakedaemon.net>

On Tue, Apr 30, 2013 at 07:24:35PM +0200, Sebastian Hesselbarth wrote:
> This patch adds the device tree node for si5351 clock generator
> and the corresponding oscillator connected to it. It also limits
> i2c frequency to 100kHz as there are bus locks reported on higher
> frequencies.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/boot/dts/dove-cubox.dts |   51 +++++++++++++++++++++++++++++++++++++-
>  1 files changed, 50 insertions(+), 1 deletions(-)

Applied to mvebu/dt

thx,

Jason.


From jason at lakedaemon.net  Mon May 13 16:25:29 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:25:29 -0400
Subject: [GIT PULL] ARM: mvebu: cleanups for v3.11 (round 1)
Message-ID: <20130513202529.GD31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/cleanup-3.11-1

for you to fetch changes up to 49ed97f751bfaea133ae5c44f1247db09b9ca144:

  ARM: Orion: Remove redundant init_dma_coherent_pool_size() (2013-05-13 19:35:39 +0000)

----------------------------------------------------------------
mvebu cleanup for v3.11 (round 1)

 - orion5x/kirkwood/mvebu
    - remove init_dma_coherent_pool_size() as it's no longer needed

----------------------------------------------------------------
Andrew Lunn (1):
      ARM: Orion: Remove redundant init_dma_coherent_pool_size()

 arch/arm/mach-kirkwood/common.c     | 6 ------
 arch/arm/mach-mvebu/armada-370-xp.c | 7 -------
 arch/arm/mach-orion5x/common.c      | 7 -------
 3 files changed, 20 deletions(-)


From jason at lakedaemon.net  Mon May 13 16:29:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:29:32 -0400
Subject: [GIT PULL] ARM: mvebu: defconfig changes for v3.11 (round 1)
Message-ID: <20130513202932.GE31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/defconfig-3.11-1

for you to fetch changes up to 366c0b76416ed15feb90ba4ef0bd8f03d62d1091:

  ARM: mvebu: Add support for USB storage class in mvebu_defconfig (2013-05-13 20:06:06 +0000)

----------------------------------------------------------------
mvebu defconfig changes for v3.11 (round 1)

 - mvebu
    - add usb-storage to mvebu_defconfig

----------------------------------------------------------------
Ezequiel Garcia (1):
      ARM: mvebu: Add support for USB storage class in mvebu_defconfig

 arch/arm/configs/mvebu_defconfig | 1 +
 1 file changed, 1 insertion(+)


From jason at lakedaemon.net  Mon May 13 16:31:18 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 16:31:18 -0400
Subject: [GIT PULL] ARM: mvebu: dt changes for v3.11 (round 1)
Message-ID: <20130513203118.GF31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/dt-3.11-1

for you to fetch changes up to 53e9cb1dcde882cc667497328eca776a9835f965:

  ARM: dove: add si5351 clock driver to CuBox DT (2013-05-13 20:14:56 +0000)

----------------------------------------------------------------
mvebu dt changes for v3.11 (round 1)

 - dove
    - CuBox clock driver

----------------------------------------------------------------
Sebastian Hesselbarth (1):
      ARM: dove: add si5351 clock driver to CuBox DT

 arch/arm/boot/dts/dove-cubox.dts | 51 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)


From aaro.koskinen at iki.fi  Mon May 13 16:53:02 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Mon, 13 May 2013 23:53:02 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
Message-ID: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>

Hi,

I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:

[    2.264221] retu-mfd 2-0001: Retu v3.2 found
[    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
[    2.300140] retu-mfd: probe of 2-0001 failed with error -12

The error is coming from regmap code. According to git bisect, it is
caused by:

	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
	Author: Jon Hunter <jon-hunter at ti.com>
	Date:   Fri Mar 1 11:22:47 2013 -0600

	    gpio/omap: convert gpio irq domain to linear mapping

The commit does not anymore revert cleanly, and I haven't yet tried
crafting a manual revert, so any fix proposals/ideas are welcome...

Thanks,

A.


From gmbnomis at gmail.com  Mon May 13 17:18:54 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:54 +0200
Subject: [PATCH V2 03/10] mmc: tmio-mmc: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-4-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/tmio_mmc_pio.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c
index f508ecb..f1a9d4a 100644
--- a/drivers/mmc/host/tmio_mmc_pio.c
+++ b/drivers/mmc/host/tmio_mmc_pio.c
@@ -988,7 +988,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host,
 	if (!mmc)
 		return -ENOMEM;
 
-	mmc_of_parse(mmc);
+	ret = mmc_of_parse(mmc);
+	if (ret < 0)
+		goto host_free;
 
 	pdata->dev = &pdev->dev;
 	_host = mmc_priv(mmc);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:56 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:56 +0200
Subject: [PATCH V2 05/10] mmc: sdhi-pxav3: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-6-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/sdhci-pxav3.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 1ae358e..67ea388 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -252,7 +252,9 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 
 	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 	if (match) {
-		mmc_of_parse(host->mmc);
+		ret = mmc_of_parse(host->mmc);
+		if (ret)
+			goto err_of_parse;
 		sdhci_get_of_property(pdev);
 		pdata = pxav3_get_mmc_pdata(dev);
 	} else if (pdata) {
@@ -313,10 +315,11 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 
 	return 0;
 
+err_of_parse:
+err_cd_req:
 err_add_host:
 	clk_disable_unprepare(clk);
 	clk_put(clk);
-err_cd_req:
 err_clk_get:
 	sdhci_pltfm_free(pdev);
 	kfree(pxa);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:55 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:55 +0200
Subject: [PATCH V2 04/10] mmc: mxcmmc: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-5-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/mxcmmc.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index d503635..f47546f 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -1067,7 +1067,9 @@ static int mxcmci_probe(struct platform_device *pdev)
 		goto out_release_mem;
 	}
 
-	mmc_of_parse(mmc);
+	ret = mmc_of_parse(mmc);
+	if (ret)
+		goto out_free;
 	mmc->ops = &mxcmci_ops;
 
 	/* For devicetree parsing, the bus width is read from devicetree */
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:57 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:57 +0200
Subject: [PATCH V2 06/10] mmc: tegra: handle mmc_of_parse() errors during probe
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-7-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/sdhci-tegra.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index e0dba74..7eb62f8 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -205,7 +205,7 @@ static const struct of_device_id sdhci_tegra_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
 
-static void sdhci_tegra_parse_dt(struct device *dev)
+static int sdhci_tegra_parse_dt(struct device *dev)
 {
 	struct device_node *np = dev->of_node;
 	struct sdhci_host *host = dev_get_drvdata(dev);
@@ -213,7 +213,7 @@ static void sdhci_tegra_parse_dt(struct device *dev)
 	struct sdhci_tegra *tegra_host = pltfm_host->priv;
 
 	tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
-	mmc_of_parse(host->mmc);
+	return mmc_of_parse(host->mmc);
 }
 
 static int sdhci_tegra_probe(struct platform_device *pdev)
@@ -245,7 +245,9 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 	tegra_host->soc_data = soc_data;
 	pltfm_host->priv = tegra_host;
 
-	sdhci_tegra_parse_dt(&pdev->dev);
+	rc = sdhci_tegra_parse_dt(&pdev->dev);
+	if (rc)
+		goto err_parse_dt;
 
 	if (gpio_is_valid(tegra_host->power_gpio)) {
 		rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
@@ -278,6 +280,7 @@ err_add_host:
 err_clk_get:
 	if (gpio_is_valid(tegra_host->power_gpio))
 		gpio_free(tegra_host->power_gpio);
+err_parse_dt:
 err_power_req:
 err_alloc_tegra_host:
 	sdhci_pltfm_free(pdev);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:52 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:52 +0200
Subject: [PATCH V2 01/10] mmc: return mmc_of_parse() errors to caller
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-2-git-send-email-gmbnomis@gmail.com>

In addition to just logging errors encountered during DT parsing or
allocating GPIO slots for CD/WP, mmc_of_parse() now returns with an
error.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/core/host.c  |   24 +++++++++++++++++++-----
 include/linux/mmc/host.h |    2 +-
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 2a3593d..45122cc 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -306,7 +306,7 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
  * parse the properties and set respective generic mmc-host flags and
  * parameters.
  */
-void mmc_of_parse(struct mmc_host *host)
+int mmc_of_parse(struct mmc_host *host)
 {
 	struct device_node *np;
 	u32 bus_width;
@@ -315,7 +315,7 @@ void mmc_of_parse(struct mmc_host *host)
 	int len, ret, gpio;
 
 	if (!host->parent || !host->parent->of_node)
-		return;
+		return 0;
 
 	np = host->parent->of_node;
 
@@ -338,6 +338,7 @@ void mmc_of_parse(struct mmc_host *host)
 	default:
 		dev_err(host->parent,
 			"Invalid \"bus-width\" value %ud!\n", bus_width);
+		return -EINVAL;
 	}
 
 	/* f_max is obtained from the optional "max-frequency" property */
@@ -372,13 +373,15 @@ void mmc_of_parse(struct mmc_host *host)
 				gpio_inv_cd = true;
 
 			ret = mmc_gpio_request_cd(host, gpio);
-			if (ret < 0)
+			if (ret < 0) {
 				dev_err(host->parent,
 					"Failed to request CD GPIO #%d: %d!\n",
 					gpio, ret);
-			else
+				return ret;
+			} else {
 				dev_info(host->parent, "Got CD GPIO #%d.\n",
 					 gpio);
+			}
 		}
 
 		if (explicit_inv_cd ^ gpio_inv_cd)
@@ -394,9 +397,14 @@ void mmc_of_parse(struct mmc_host *host)
 			gpio_inv_wp = true;
 
 		ret = mmc_gpio_request_ro(host, gpio);
-		if (ret < 0)
+		if (ret < 0) {
 			dev_err(host->parent,
 				"Failed to request WP GPIO: %d!\n", ret);
+			goto out;
+		} else {
+				dev_info(host->parent, "Got WP GPIO #%d.\n",
+					 gpio);
+		}
 	}
 	if (explicit_inv_wp ^ gpio_inv_wp)
 		host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
@@ -413,6 +421,12 @@ void mmc_of_parse(struct mmc_host *host)
 		host->pm_caps |= MMC_PM_KEEP_POWER;
 	if (of_find_property(np, "enable-sdio-wakeup", &len))
 		host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
+
+	return 0;
+
+out:
+	mmc_gpio_free_cd(host);
+	return ret;
 }
 
 EXPORT_SYMBOL(mmc_of_parse);
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index e326ae2..c8c4fbc 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -369,7 +369,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *);
 int mmc_add_host(struct mmc_host *);
 void mmc_remove_host(struct mmc_host *);
 void mmc_free_host(struct mmc_host *);
-void mmc_of_parse(struct mmc_host *host);
+int mmc_of_parse(struct mmc_host *host);
 
 static inline void *mmc_priv(struct mmc_host *host)
 {
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:53 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:53 +0200
Subject: [PATCH V2 02/10] mmc: sh_mmcif: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-3-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/sh_mmcif.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index ba76a53..6ded7fb 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -1369,7 +1369,11 @@ static int sh_mmcif_probe(struct platform_device *pdev)
 		ret = -ENOMEM;
 		goto ealloch;
 	}
-	mmc_of_parse(mmc);
+
+	ret = mmc_of_parse(mmc);
+	if (ret < 0)
+		goto eofparse;
+
 	host		= mmc_priv(mmc);
 	host->mmc	= mmc;
 	host->addr	= reg;
@@ -1464,6 +1468,7 @@ eclkupdate:
 	clk_put(host->hclk);
 eclkget:
 	pm_runtime_disable(&pdev->dev);
+eofparse:
 	mmc_free_host(mmc);
 ealloch:
 	iounmap(reg);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:51 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:51 +0200
Subject: [PATCH V2 00/10] mmc_of_parse() adaptations,
 DT support for Sheevaplugs
Message-ID: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>

While adding DT support for the Sheevaplugs by Globalscale Technologies
(Kirkwood), it turned out that the DT binding of mvsdio lacked features to
properly support the hardware (active high/low of CD and WP pins could not
be described in DT).

This is standard functionality provided by the mmc_of_parse() helper
function.  However, mmc_of_parse() may allocate GPIO lines.  If the
allocation fails, it outputs an error, but does not return an error to its
caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.

The patch set is structured as follows:

1   Adapt mmc_of_parse() to return errors
2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
    only)
7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
    kirkwood)
9   Add dts files for (eSATA) Sheevaplug
10  Add DT support for (eSATA) Sheevaplug


I could only test on an eSATA Sheevaplug. I found patches with
different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
someone with the hardware could give this a spin on a non-eSATA
version.  Some additional testing of the change detect and write
protect behaviour for mvsdio can't hurt either.  I hope that there aren't
board revisions with different CD/WP pins out there.

Simon Baatz (10):
  mmc: return mmc_of_parse() errors to caller
  mmc: sh_mmcif: handle mmc_of_parse() errors during probe
  mmc: tmio-mmc: handle mmc_of_parse() errors during probe
  mmc: mxcmmc: handle mmc_of_parse() errors during probe
  mmc: sdhi-pxav3: handle mmc_of_parse() errors during probe
  mmc: tegra: handle mmc_of_parse() errors during probe
  ARM: mvebu: Use standard MMC binding for all users of mvsdio
  mmc: mvsdio: use standard MMC device-tree binding parser
    mmc_of_parse()
  ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug
  ARM: Kirkwood: add DT support for Sheevaplug and Sheevaplug eSATA

 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/armada-370-db.dts                |    1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |    1 +
 arch/arm/boot/dts/armada-370-rd.dts                |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    1 +
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |    1 +
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    2 +
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |    2 +-
 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi  |   97 ++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts    |   40 ++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug.dts          |   45 +++++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |    1 +
 arch/arm/boot/dts/kirkwood.dtsi                    |    4 +
 arch/arm/mach-kirkwood/Kconfig                     |    7 ++
 arch/arm/mach-kirkwood/Makefile                    |    1 +
 arch/arm/mach-kirkwood/board-dt.c                  |    4 +
 arch/arm/mach-kirkwood/board-sheevaplug.c          |   27 ++++++
 arch/arm/mach-kirkwood/common.h                    |    5 +
 drivers/mmc/core/host.c                            |   24 ++++-
 drivers/mmc/host/mvsdio.c                          |   73 ++++++++-------
 drivers/mmc/host/mxcmmc.c                          |    4 +-
 drivers/mmc/host/sdhci-pxav3.c                     |    7 +-
 drivers/mmc/host/sdhci-tegra.c                     |    9 +-
 drivers/mmc/host/sh_mmcif.c                        |    7 +-
 drivers/mmc/host/tmio_mmc_pio.c                    |    4 +-
 include/linux/mmc/host.h                           |    2 +-
 27 files changed, 328 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts
 create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c

-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:58 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:58 +0200
Subject: [PATCH V2 07/10] ARM: mvebu: Use standard MMC binding for all users
 of mvsdio
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-8-git-send-email-gmbnomis@gmail.com>

In order to prepare the switch to the standard MMC device tree parser
for mvsdio, adapt all current uses of mvsdio in the dts files to the
standard format.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 arch/arm/boot/dts/armada-370-db.dts                |    1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |    1 +
 arch/arm/boot/dts/armada-370-rd.dts                |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    4 ++++
 arch/arm/boot/dts/armada-xp-db.dts                 |    1 +
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |    1 +
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    2 ++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |    2 +-
 arch/arm/boot/dts/kirkwood-topkick.dts             |    1 +
 arch/arm/boot/dts/kirkwood.dtsi                    |    4 ++++
 10 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 2353b1f..beee169 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -74,6 +74,7 @@
 				 */
 				status = "disabled";
 				/* No CD or WP GPIOs */
+				broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 14e36e1..45b1077 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -99,6 +99,7 @@
 				 * No CD or WP GPIOs: SDIO interface used for
 				 * Wifi/Bluetooth chip
 				 */
+				 broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 130f839..89c2110 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,6 +64,7 @@
 				pinctrl-names = "default";
 				status = "okay";
 				/* No CD or WP GPIOs */
+				broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..031894e 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -142,6 +142,10 @@
 				reg = <0xd4000 0x200>;
 				interrupts = <54>;
 				clocks = <&gateclk 17>;
+				bus-width = <4>;
+				cap-sdio-irq;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index d6cc8bf..7c22a20 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -97,6 +97,7 @@
 				pinctrl-names = "default";
 				status = "okay";
 				/* No CD or WP GPIOs */
+				broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d..be16a84 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -79,6 +79,7 @@
 			pinctrl-names = "default";
 			status = "okay";
 			/* No CD or WP GPIOs */
+			broken-cd;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97d..484a2a6 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -72,6 +72,8 @@
 
 		mvsdio at 90000 {
 			status = "okay";
+			/* No CD or WP GPIOs */
+			broken-cd;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..bf3a58c 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -136,7 +136,7 @@
 			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
 			pinctrl-names = "default";
 			status = "okay";
-			cd-gpios = <&gpio1 15 0>;
+			cd-gpios = <&gpio1 15 1>;
 			/* No WP GPIO */
 		};
 	};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b..7dc14f4 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -154,6 +154,7 @@
 			pinctrl-names = "default";
 			status = "okay";
 			/* No CD or WP GPIOs */
+			broken-cd;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..e2a28db 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -200,6 +200,10 @@
 			reg = <0x90000 0x200>;
 			interrupts = <28>;
 			clocks = <&gate_clk 4>;
+			bus-width = <4>;
+			cap-sdio-irq;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
 			status = "disabled";
 		};
 	};
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:19:01 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:19:01 +0200
Subject: [PATCH V2 10/10] ARM: Kirkwood: add DT support for Sheevaplug and
 Sheevaplug eSATA
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-11-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig            |    7 +++++++
 arch/arm/mach-kirkwood/Makefile           |    1 +
 arch/arm/mach-kirkwood/board-dt.c         |    4 ++++
 arch/arm/mach-kirkwood/board-sheevaplug.c |   27 +++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h           |    5 +++++
 5 files changed, 44 insertions(+)
 create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..58518a2 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -296,6 +296,13 @@ config MACH_READYNAS_DT
 	  Say 'Y' here if you want your kernel to support the
 	  NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
+config MACH_SHEEVAPLUG_DT
+	bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell (eSATA) SheevaPlug (Flattened Device Tree).
+
 config MACH_TOPKICK_DT
 	bool "USI Topkick (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735..8846abf 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)		+= board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)	+= board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
+obj-$(CONFIG_MACH_SHEEVAPLUG_DT)	+= board-sheevaplug.o
 obj-$(CONFIG_MACH_TOPKICK_DT)		+= board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..a09dbac 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -112,6 +112,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("globalscale,guruplug"))
 		guruplug_dt_init();
 
+	if (of_machine_is_compatible("globalscale,sheevaplug"))
+		sheevaplug_dt_init();
+
 	if (of_machine_is_compatible("dlink,dns-kirkwood"))
 		dnskw_init();
 
@@ -165,6 +168,7 @@ static void __init kirkwood_dt_init(void)
 static const char * const kirkwood_dt_board_compat[] = {
 	"globalscale,dreamplug",
 	"globalscale,guruplug",
+	"globalscale,sheevaplug",
 	"dlink,dns-320",
 	"dlink,dns-325",
 	"iom,iconnect",
diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
new file mode 100644
index 0000000..fa38937
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-sheevaplug.c
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-kirkwood/board-sheevaplug.c
+ *
+ * Marvell Sheevaplug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+void __init sheevaplug_dt_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_ge00_init(&sheevaplug_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..974442e 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -65,6 +65,11 @@ void guruplug_dt_init(void);
 #else
 static inline void guruplug_dt_init(void) {};
 #endif
+#ifdef CONFIG_MACH_SHEEVAPLUG_DT
+void sheevaplug_dt_init(void);
+#else
+static inline void sheevaplug_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:18:59 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:18:59 +0200
Subject: [PATCH V2 08/10] mmc: mvsdio: use standard MMC device-tree binding
 parser mmc_of_parse()
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-9-git-send-email-gmbnomis@gmail.com>

Instead of parsing the DT binding on our own, use the standard parser
mmc_of_parse(), introduced by commit 6c56e7a.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/mvsdio.c |   73 +++++++++++++++++++++++++--------------------
 1 file changed, 40 insertions(+), 33 deletions(-)

diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c
index 8960fc8..edfc481 100644
--- a/drivers/mmc/host/mvsdio.c
+++ b/drivers/mmc/host/mvsdio.c
@@ -35,7 +35,7 @@
 
 #define DRIVER_NAME	"mvsdio"
 
-static int maxfreq = MVSD_CLOCKRATE_MAX;
+static int maxfreq;
 static int nodma;
 
 struct mvsd_host {
@@ -685,7 +685,6 @@ static int __init mvsd_probe(struct platform_device *pdev)
 	const struct mbus_dram_target_info *dram;
 	struct resource *r;
 	int ret, irq;
-	int gpio_card_detect, gpio_write_protect;
 	struct pinctrl *pinctrl;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -718,6 +717,20 @@ static int __init mvsd_probe(struct platform_device *pdev)
 	if (!IS_ERR(host->clk))
 		clk_prepare_enable(host->clk);
 
+	mmc->ops = &mvsd_ops;
+
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
+	mmc->f_max = MVSD_CLOCKRATE_MAX;
+
+	mmc->max_blk_size = 2048;
+	mmc->max_blk_count = 65535;
+
+	mmc->max_segs = 1;
+	mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
+	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+
 	if (np) {
 		if (IS_ERR(host->clk)) {
 			dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
@@ -726,35 +739,38 @@ static int __init mvsd_probe(struct platform_device *pdev)
 		}
 
 		host->base_clock = clk_get_rate(host->clk) / 2;
-		gpio_card_detect = of_get_named_gpio(np, "cd-gpios", 0);
-		gpio_write_protect = of_get_named_gpio(np, "wp-gpios", 0);
+		ret = mmc_of_parse(mmc);
+		if (ret < 0)
+			goto out;
 	} else {
 		const struct mvsdio_platform_data *mvsd_data;
+
 		mvsd_data = pdev->dev.platform_data;
 		if (!mvsd_data) {
 			ret = -ENXIO;
 			goto out;
 		}
+		mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
+			    MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
 		host->base_clock = mvsd_data->clock / 2;
-		gpio_card_detect = mvsd_data->gpio_card_detect ? : -EINVAL;
-		gpio_write_protect = mvsd_data->gpio_write_protect ? : -EINVAL;
-	}
-
-	mmc->ops = &mvsd_ops;
-
-	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
-		    MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
-
-	mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
-	mmc->f_max = maxfreq;
+		/* GPIO 0 regarded as invalid for backward compatibility */
+		if (mvsd_data->gpio_card_detect &&
+		    gpio_is_valid(mvsd_data->gpio_card_detect)) {
+			ret = mmc_gpio_request_cd(mmc,
+						  mvsd_data->gpio_card_detect);
+			if (ret)
+				goto out;
+		} else {
+			mmc->caps |= MMC_CAP_NEEDS_POLL;
+		}
 
-	mmc->max_blk_size = 2048;
-	mmc->max_blk_count = 65535;
+		if (mvsd_data->gpio_write_protect &&
+		    gpio_is_valid(mvsd_data->gpio_write_protect))
+			mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect);
+	}
 
-	mmc->max_segs = 1;
-	mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
-	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+	if (maxfreq)
+		mmc->f_max = maxfreq;
 
 	spin_lock_init(&host->lock);
 
@@ -777,15 +793,6 @@ static int __init mvsd_probe(struct platform_device *pdev)
 		goto out;
 	}
 
-	if (gpio_is_valid(gpio_card_detect)) {
-		ret = mmc_gpio_request_cd(mmc, gpio_card_detect);
-		if (ret)
-			goto out;
-	} else
-		mmc->caps |= MMC_CAP_NEEDS_POLL;
-
-	mmc_gpio_request_ro(mmc, gpio_write_protect);
-
 	setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
 	platform_set_drvdata(pdev, mmc);
 	ret = mmc_add_host(mmc);
@@ -793,10 +800,10 @@ static int __init mvsd_probe(struct platform_device *pdev)
 		goto out;
 
 	if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
-		dev_notice(&pdev->dev, "using GPIO %d for card detection\n",
-			   gpio_card_detect);
+		dev_notice(&pdev->dev, "using GPIO for card detection\n");
 	else
-		dev_notice(&pdev->dev, "lacking card detect (fall back to polling)\n");
+		dev_notice(&pdev->dev,
+			   "lacking card detect (fall back to polling)\n");
 	return 0;
 
 out:
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 13 17:19:00 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 May 2013 23:19:00 +0200
Subject: [PATCH V2 09/10] ARM: Kirkwood: Add dts files for Sheevaplug and
 eSATA Sheevaplug
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368479941-10084-10-git-send-email-gmbnomis@gmail.com>


Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 arch/arm/boot/dts/Makefile                        |    2 +
 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi |   97 +++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts   |   40 +++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug.dts         |   45 ++++++++++
 4 files changed, 184 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..e81a387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -84,6 +84,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
 	kirkwood-ns2max.dtb \
 	kirkwood-ns2mini.dtb \
 	kirkwood-nsa310.dtb \
+	kirkwood-sheevaplug.dtb \
+	kirkwood-sheevaplug-esata.dtb \
 	kirkwood-topkick.dtb \
 	kirkwood-ts219-6281.dtb \
 	kirkwood-ts219-6282.dtb \
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
new file mode 100644
index 0000000..9d59475
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -0,0 +1,97 @@
+/*
+ * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		pinctrl: pinctrl at 10000 {
+
+			pmx_usb_power_enable: pmx-usb-power-enable {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+			pmx_led_red: pmx-led-red {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_led_blue: pmx-led-blue {
+				marvell,pins = "mpp49";
+				marvell,function = "gpio";
+			};
+			pmx_sdio_cd: pmx-sdio-cd {
+				marvell,pins = "mpp44";
+				marvell,function = "gpio";
+			};
+			pmx_sdio_wp: pmx-sdio-wp {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+		};
+		serial at 12000 {
+			status = "okay";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x400000>;
+			};
+
+			partition at 500000 {
+				label = "root";
+				reg = <0x0500000 0x1fb00000>;
+			};
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_power: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 29 0>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		health {
+			label = "sheevaplug:blue:health";
+			gpios = <&gpio1 17 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
new file mode 100644
index 0000000..1c6946a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -0,0 +1,40 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+	model = "Globalscale Technologies eSATA SheevaPlug";
+	compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	ocp at f1000000 {
+		pinctrl: pinctrl at 10000 {
+
+			pinctrl-0 = < &pmx_nand &pmx_uart0
+				      &pmx_usb_power_enable
+				      &pmx_led_blue>;
+			pinctrl-names = "default";
+
+		};
+
+		sata at 80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+		mvsdio at 90000 {
+			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
+			pinctrl-names = "default";
+			status = "okay";
+			cd-gpios = <&gpio1 12 1>;
+			wp-gpios = <&gpio1 15 0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
new file mode 100644
index 0000000..f7684066
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -0,0 +1,45 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+	model = "Globalscale Technologies SheevaPlug";
+	compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	ocp at f1000000 {
+		pinctrl: pinctrl at 10000 {
+
+			pinctrl-0 = < &pmx_nand &pmx_uart0
+				      &pmx_usb_power_enable
+				      &pmx_led_red
+				      &pmx_led_blue>;
+			pinctrl-names = "default";
+
+		};
+
+		mvsdio at 90000 {
+			pinctrl-0 = <&pmx_sdio>;
+			pinctrl-names = "default";
+			status = "okay";
+			/* No CD or WP GPIOs */
+			broken-cd;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		misc {
+			label = "sheevaplug:red:misc";
+			gpios = <&gpio1 14 1>;
+		};
+	};
+};
-- 
1.7.9.5



From james.hogan at imgtec.com  Mon May 13 17:30:46 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 13 May 2013 22:30:46 +0100
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <20130513195746.10068.92303@quantum>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <20130513195746.10068.92303@quantum>
Message-ID: <CAAG0J991BCziPFddzBrx9vcwRxyRgcCd38A01uKXTDDK9xTnbQ@mail.gmail.com>

On 13 May 2013 20:57, Mike Turquette <mturquette at linaro.org> wrote:
> Quoting James Hogan (2013-04-19 09:28:21)
>> This patchset adds support for automatic selection of the best parent
>> for a clock mux, i.e. the one which can provide the closest clock rate
>> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
>> so that it doesn't happen unless explicitly allowed.
>>
>
> I'm not sure about the new flag.  One of my regrets during the early
> development of the common struct clk is the CLK_SET_RATE_PARENT flag.
> In hindsight I would have preferred to make parent-propagation of rate
> changes the default behavior, and instead provide a flag to prevent that
> behavior, such as CLK_SET_RATE_NO_PROPAGATE.
>
> One reason for this is the difficulty some have had with setting flags
> from DT bindings.

Could you elaborate on this? I've been adding flags to DT bindings for
this sort of thing, but it feels a bit like it's in that grey area of
not really describing the hardware itself. This information needs to
be specified somehow though.

> Another reason is that a core goal of the framework
> is to remove topology info from drivers; having to set a flag explicitly
> on each clock to propagate rate changes is an impediment to that goal.

(Something that I have found also where CLK_SET_RATE_PARENT doesn't
fit well is when you have a mux where you want the set_rate propagated
to one possible parent (e.g. a dedicated PLL) but not the other (e.g.
the system clock - which happens to be a divider). In this case what I
really want to say is "don't change the rate of this particular
clock", in fact I added a CLK_DIVIDER_READ_ONLY divider flag locally
for this purpose. Was there a particular use case of
CLK_SET_RATE_PARENT where you'd want a clock to be changed from one
child but not another?)

>
> So perhaps CLK_SET_RATE_REMUX is a similar situation.  What do you think
> about making remuxing the default and providing a flag to prevent it?

Yes, fine by me.

> And also we can assume for the immediate future that users of
> .determine_rate WANT to remux, since .round_rate won't do it.  Though
> eventually it might be wise to convert all users of .round_rate over to
> .determine_rate and deprecate .round_rate entirely.

True.

Cheers
James


From khilman at linaro.org  Mon May 13 17:53:27 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Mon, 13 May 2013 14:53:27 -0700
Subject: [PATCH] ARM: OMAP3+: am33xx id: Add new am33xx specific function
 to check dev_feature
In-Reply-To: <1367996313-6676-1-git-send-email-hvaibhav@ti.com> (Vaibhav
 Hiremath's message of "Wed, 8 May 2013 12:28:33 +0530")
References: <1367996313-6676-1-git-send-email-hvaibhav@ti.com>
Message-ID: <87bo8e1r8o.fsf@linaro.org>

Vaibhav Hiremath <hvaibhav at ti.com> writes:

> Layout of DEV_FEATURE register (offset = 0x604) is different
> between TI81xx and AM33xx device, so create separate function
> which will check for features available on specific AM33xx SoC
> and set the flags accordingly.
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>

Minor nit below, otherwise...

Reviewed-by: Kevin Hilman <khilman at linaro.org>

> ---
>  arch/arm/mach-omap2/control.h |    5 +++++
>  arch/arm/mach-omap2/id.c      |   13 +++++++++++++
>  arch/arm/mach-omap2/io.c      |    2 +-
>  arch/arm/mach-omap2/soc.h     |    1 +
>  4 files changed, 20 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index e6c3281..4acdfc5 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -358,6 +358,11 @@
>  #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
>  #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)
>  
> +/* DEV Feature register to identify AM33XX features */
> +#define AM33XX_DEV_FEATURE		0x604
> +#define AM33XX_SGX_SHIFT		29

You don't need the shift value anywhere in the code, so...

> +#define AM33XX_SGX_MASK			(1 << AM33XX_SGX_SHIFT)

#define AM33XX_SGX_MASK		BIT(29)

instead?

Otherwise, rest of patch looks fine.

Kevin


From andre.przywara at linaro.org  Mon May 13 18:23:15 2013
From: andre.przywara at linaro.org (Andre Przywara)
Date: Tue, 14 May 2013 00:23:15 +0200
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM
 VCPU ioctl
In-Reply-To: <20130513055253.GC64337@ubuntu>
References: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
 <20130513055253.GC64337@ubuntu>
Message-ID: <519167D3.4030600@linaro.org>

On 05/13/2013 07:52 AM, Christoffer Dall wrote:
> On Thu, May 09, 2013 at 12:28:06AM +0200, Andre Przywara wrote:
>> Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
>> with the KVM_ARM_VCPU_INIT ioctl before being used with further
>> requests. KVM_RUN checks whether this initialization has been
>> done, but other ioctls do not.
>> Namely KVM_GET_REG_LIST will dereference an array with index -1
>> without initialization and thus leads to a kernel oops.
>> Fix this by adding checks before executing the ioctl handlers.
>>
>> Changes from v1:
>>   * moved check into a static function with a meaningful name
>>
>> Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
>> ---
>>   arch/arm/kvm/arm.c | 19 +++++++++++++++++--
>>   1 file changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>> index c1fe498..b73b587 100644
>> --- a/arch/arm/kvm/arm.c
>> +++ b/arch/arm/kvm/arm.c
>> @@ -676,6 +676,15 @@ static void vcpu_pause(struct kvm_vcpu *vcpu)
>>   	wait_event_interruptible(*wq, !vcpu->arch.pause);
>>   }
>>
>> +/*
>> + * Some ioctls require initialization by KVM_ARM_VCPU_INIT first, check
>> + * this with this function
>> + */
>> +static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
>> +{
>> +	return vcpu->arch.target >= 0;
>> +}
>> +
>
> this should probably be a static inline in a header file instead, it's
> likely that it could be called from another file.

kvm_host.h looks like a natural candidate, but unfortunately struct 
kvm_vcpu is opaque here, so dereferencing it does not work without 
further changes which I do not deem to be justified. I used kvm_coproc.h 
instead, which is loosely related (KVM_[SG]ET_ONE_REG) and just simply 
works. If you don't think that's appropriate, just drop me a note. Patch 
follows in a separate mail.

Regards,
Andre.



From andre.przywara at linaro.org  Mon May 13 18:25:08 2013
From: andre.przywara at linaro.org (Andre Przywara)
Date: Tue, 14 May 2013 00:25:08 +0200
Subject: [PATCH v3] ARM: KVM: prevent NULL pointer dereferences with KVM VCPU
 ioctl
Message-ID: <1368483908-22274-1-git-send-email-andre.przywara@linaro.org>

Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
with the KVM_ARM_VCPU_INIT ioctl before being used with further
requests. KVM_RUN checks whether this initialization has been
done, but other ioctls do not.
Namely KVM_GET_REG_LIST will dereference an array with index -1
without initialization and thus leads to a kernel oops.
Fix this by adding checks before executing the ioctl handlers.

Changes from v1:
 * moved check into a static function with a meaningful name
Changes from v2:
 * moved function into a header file and marked it as inline

Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
---
 arch/arm/include/asm/kvm_coproc.h |  9 +++++++++
 arch/arm/kvm/arm.c                | 10 ++++++++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h
index 4917c2f7..80d0082 100644
--- a/arch/arm/include/asm/kvm_coproc.h
+++ b/arch/arm/include/asm/kvm_coproc.h
@@ -39,6 +39,15 @@ unsigned long kvm_arm_num_guest_msrs(struct kvm_vcpu *vcpu);
 int kvm_arm_copy_msrindices(struct kvm_vcpu *vcpu, u64 __user *uindices);
 void kvm_coproc_table_init(void);
 
+/*
+ * Some ioctls require initialization by KVM_ARM_VCPU_INIT first, check
+ * this with this function to avoid NULL pointer dereference
+ */
+static inline int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
+{
+	return vcpu->arch.target >= 0;
+}
+
 struct kvm_one_reg;
 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 37d216d..6800293 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -508,8 +508,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	int ret;
 	sigset_t sigsaved;
 
-	/* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
-	if (unlikely(vcpu->arch.target < 0))
+	if (unlikely(!kvm_vcpu_initialized(vcpu)))
 		return -ENOEXEC;
 
 	ret = kvm_vcpu_first_run_init(vcpu);
@@ -710,6 +709,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 	case KVM_SET_ONE_REG:
 	case KVM_GET_ONE_REG: {
 		struct kvm_one_reg reg;
+
+		if (unlikely(!kvm_vcpu_initialized(vcpu)))
+			return -ENOEXEC;
+
 		if (copy_from_user(&reg, argp, sizeof(reg)))
 			return -EFAULT;
 		if (ioctl == KVM_SET_ONE_REG)
@@ -722,6 +725,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 		struct kvm_reg_list reg_list;
 		unsigned n;
 
+		if (unlikely(!kvm_vcpu_initialized(vcpu)))
+			return -ENOEXEC;
+
 		if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 			return -EFAULT;
 		n = reg_list.n;
-- 
1.7.12.1



From laurent.pinchart at ideasonboard.com  Mon May 13 18:30:27 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 00:30:27 +0200
Subject: [PATCH 2/2] ARM: shmobile: lager: enable Ether
In-Reply-To: <5190E4E9.20100@cogentembedded.com>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <20130513004001.GC22911@verge.net.au> <5190E4E9.20100@cogentembedded.com>
Message-ID: <4649393.HiDLOXMspX@avalon>

On Monday 13 May 2013 17:04:41 Sergei Shtylyov wrote:
> On 13.05.2013 4:40, Simon Horman wrote:
> > [ CC Laurent ]
> > 
> >>> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >>> 
> >>> ---
> >>> 
> >>> This patch has a run-time dependency on "sh_eth: add support for r8a7790
> >>> SoC".
> [...]
> 
> >>> diff --git a/arch/arm/mach-shmobile/board-lager.c
> >>> b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..0b8112d 100644
> >>> --- a/arch/arm/mach-shmobile/board-lager.c
> >>> +++ b/arch/arm/mach-shmobile/board-lager.c
> >> 
> >> [...]
> >> 
> >>> @@ -59,6 +69,17 @@ static const struct pinctrl_map lager_pinctrl_map[] =
> >>> {
> >>> 
> >>>   	/* SCIF1 (CN20: DEBUG SERIAL1) */
> >>>   	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
> >>>   	
> >>>   				  "scif1_data", "scif1"),
> >>> 
> >>> +	/* Ether */
> >>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >>> +				  "eth_link", "eth"),
> >>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >>> +				  "eth_magic", "eth"),
> >>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >>> +				  "eth_mdio", "eth"),
> >>> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> >>> +				  "eth_rmii", "eth"),
> >>> 
> >>      I thought MDIO bus was a part of RMII. At least Wikipedia told
> >> 
> >> me so. :-)
> > 
> > Is the implication that you think that the eth_mdio and eth_rmii
> > groups should be combined?

MDIO is used by RMII, MII and (R)GMII. Merging eth_mdio and eth_rmii would 
require duplicating the pins in all those ethernet-related functions.

-- 
Regards,

Laurent Pinchart



From laurent.pinchart at ideasonboard.com  Mon May 13 18:31:48 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 00:31:48 +0200
Subject: [PATCH 2/2] ARM: shmobile: lager: enable Ether
In-Reply-To: <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-3-git-send-email-horms+renesas@verge.net.au>
Message-ID: <18756824.MCbTJbYVOF@avalon>

Hi Simon,

On Friday 10 May 2013 17:05:19 Simon Horman wrote:
> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> ---
> 
> This patch has a run-time dependency on "sh_eth: add support for r8a7790
> SoC". ---
>  arch/arm/boot/dts/r8a7790-lager.dts  |  2 +-
>  arch/arm/mach-shmobile/board-lager.c | 26 ++++++++++++++++++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
> b/arch/arm/boot/dts/r8a7790-lager.dts index 09a84fc..b2f61f0 100644
> --- a/arch/arm/boot/dts/r8a7790-lager.dts
> +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> @@ -16,7 +16,7 @@
>  	compatible = "renesas,lager", "renesas,r8a7790";
> 
>  	chosen {
> -		bootargs = "console=ttySC6,115200 ignore_loglevel";
> +		bootargs = "console=ttySC6,115200 ignore_loglevel root=/dev/nfs 
ip=dhcp
> nfsroot=,rsize=4096,wsize=4096 rw"; };
> 
>  	memory at 40000000 {
> diff --git a/arch/arm/mach-shmobile/board-lager.c
> b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..0b8112d 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
> @@ -18,6 +18,7 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> +#include <linux/gpio.h>
>  #include <linux/interrupt.h>
>  #include <linux/irqchip.h>
>  #include <linux/kernel.h>
> @@ -52,6 +53,15 @@ static struct gpio_led_platform_data lager_leds_pdata = {
> .num_leds	= ARRAY_SIZE(lager_leds),
>  };
> 
> +/* Ether */
> +static struct sh_eth_plat_data ether_platdata = {
> +	.phy			= 0x1,
> +	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
> +	.register_type		= SH_ETH_REG_FAST_RCAR,
> +	.phy_interface		= PHY_INTERFACE_MODE_RMII,
> +	.ether_link_active_low	= 1,
> +};
> +
>  static const struct pinctrl_map lager_pinctrl_map[] = {
>  	/* SCIF0 (CN19: DEBUG SERIAL0) */
>  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
> @@ -59,6 +69,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
>  	/* SCIF1 (CN20: DEBUG SERIAL1) */
>  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
>  				  "scif1_data", "scif1"),
> +	/* Ether */
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_link", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_magic", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_mdio", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_rmii", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "intc_irq0", "intc"),
>  };
> 
>  static void __init lager_add_standard_devices(void)
> @@ -73,6 +94,11 @@ static void __init lager_add_standard_devices(void)
>  	platform_device_register_data(&platform_bus, "leds-gpio", -1,
>  				      &lager_leds_pdata,
>  				      sizeof(lager_leds_pdata));
> +
> +	/* Ether RESET */
> +	gpio_request_one(RCAR_GP_PIN(5, 31), GPIOF_OUT_INIT_HIGH, NULL);

Please don't touch GPIOs directly from board files. The reset GPIO number 
should be passed to the related device through platform data (and/or DT), and 
GPIO handling should be moved to the driver.

> +	r8a7790_add_ether_device(&ether_platdata);
>  }
> 
>  static const char *lager_boards_compat_dt[] __initdata = {
-- 
Regards,

Laurent Pinchart



From laurent.pinchart at ideasonboard.com  Mon May 13 18:33:42 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 00:33:42 +0200
Subject: [PATCH 2/3] ARM: shmobile: r8a7790: Configure R-Car GPIO for
 IRQ_TYPE_EDGE_BOTH
In-Reply-To: <1368435233-8587-3-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-3-git-send-email-horms+renesas@verge.net.au>
Message-ID: <2257564.fgMO2c8G9k@avalon>

Hi Simon,

On Monday 13 May 2013 17:53:52 Simon Horman wrote:
> "gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
> driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
> not universal for all SoCs a flag, has_both_edge_trigger, has been
> added to the platform data of the driver to allow this feature to be
> enabled.

What about moving this information to a platform ID table in the gpio-rcar 
driver ?

> As the r8a7790 SoC hardware supports this feature enable it.
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> ---
> 
> This patch has a build-time dependency on
> "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH".
> ---
>  arch/arm/mach-shmobile/setup-r8a7790.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c
> b/arch/arm/mach-shmobile/setup-r8a7790.c index eeef5f6..b461d93 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> @@ -45,6 +45,7 @@ static struct gpio_rcar_config
> r8a7790_gpio##idx##_platform_data = {	\ .irq_base	= 0,						
\
>  	.number_of_pins	= 32,						\
>  	.pctl_name	= "pfc-r8a7790",				\
> +	.has_both_edge_trigger = 1,					\
>  };									\
> 
>  R8A7790_GPIO(0);
-- 
Regards,

Laurent Pinchart



From laurent.pinchart at ideasonboard.com  Mon May 13 18:35:20 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 00:35:20 +0200
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
Message-ID: <9256981.LFpgU8cctr@avalon>

Hi Simon,

Thank you for the patch.

On Monday 13 May 2013 17:53:53 Simon Horman wrote:
> The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
> This patch allows access to those pins as KEYS 1 - 4 using
> gpio-keys.
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> ---
> 
> This patch has run time dependencies on
> 1. "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH"
> 2. "ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH"
> 
> Without those dependencies satisfied the gpio-keys driver will
> fail to be initialise itself. The boot should be otherwise successful
> and the board otherwise functional.
> ---
>  arch/arm/mach-shmobile/board-lager.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/board-lager.c
> b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..4d1b42b 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
> @@ -18,7 +18,10 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> +#include <linux/gpio.h>
> +#include <linux/gpio_keys.h>
>  #include <linux/interrupt.h>
> +#include <linux/input.h>

My dictionary lists input before interrupt :-)

>  #include <linux/irqchip.h>
>  #include <linux/kernel.h>
>  #include <linux/leds.h>
> @@ -52,6 +55,22 @@ static struct gpio_led_platform_data lager_leds_pdata = {
> .num_leds	= ARRAY_SIZE(lager_leds),
>  };
> 
> +/* GPIO KEY */
> +#define GPIO_KEY(c, g, d, ...) \
> +	{ .code = c, .gpio = g, .desc = d, .active_low = 1 }
> +
> +static struct gpio_keys_button gpio_buttons[] = {
> +	GPIO_KEY(KEY_4,		RCAR_GP_PIN(1, 28),	"SW2-pin4"),
> +	GPIO_KEY(KEY_3,		RCAR_GP_PIN(1, 26),	"SW2-pin3"),
> +	GPIO_KEY(KEY_2,		RCAR_GP_PIN(1, 24),	"SW2-pin2"),
> +	GPIO_KEY(KEY_1,		RCAR_GP_PIN(1, 14),	"SW2-pin1"),
> +};
> +
> +static struct gpio_keys_platform_data lager_keys_pdata = {
> +	.buttons	= gpio_buttons,
> +	.nbuttons	= ARRAY_SIZE(gpio_buttons),
> +};
> +

Could you please also update the lager dts file ?

>  static const struct pinctrl_map lager_pinctrl_map[] = {
>  	/* SCIF0 (CN19: DEBUG SERIAL0) */
>  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
> @@ -73,6 +92,9 @@ static void __init lager_add_standard_devices(void)
>  	platform_device_register_data(&platform_bus, "leds-gpio", -1,
>  				      &lager_leds_pdata,
>  				      sizeof(lager_leds_pdata));
> +	platform_device_register_data(&platform_bus, "gpio-keys", -1,
> +				      &lager_keys_pdata,
> +				      sizeof(lager_keys_pdata));
>  }
> 
>  static const char *lager_boards_compat_dt[] __initdata = {
-- 
Regards,

Laurent Pinchart



From mpatocka at redhat.com  Mon May 13 18:37:40 2013
From: mpatocka at redhat.com (Mikulas Patocka)
Date: Mon, 13 May 2013 18:37:40 -0400 (EDT)
Subject: [PATCH] bcache: Fix link errors on ARM
In-Reply-To: <5175C06B.4020805@gmail.com>
References: <5170B4C6.1030300@gmail.com>
 <Pine.LNX.4.64.1304221318350.22065@file.rdu.redhat.com>
 <5175C06B.4020805@gmail.com>
Message-ID: <Pine.LNX.4.64.1305131831110.32345@file.rdu.redhat.com>



On Mon, 22 Apr 2013, Rob Herring wrote:

> On 04/22/2013 12:32 PM, Mikulas Patocka wrote:
> > 
> > 
> > On Thu, 18 Apr 2013, Rob Herring wrote:
> > 
> >> Current errors in linux-next for ARM multi-platform randconfig builds.
> >>
> >> Rob
> >>
> >> drivers/built-in.o:drivers/md/dm-cache-target.c:429: more undefined references to `__udivdi3' follow
> >> /var/lib/jenkins/jobs/linux-randconfig/workspace/drivers/md/dm-cache-target.c:429: undefined reference to `__udivdi3'
> >> /var/lib/jenkins/jobs/linux-randconfig/workspace/drivers/md/dm-cache-target.c:429: undefined reference to `__umoddi3'
> >> driversdrivers/md/dm-cache-target.c:429: more undefined references to `__udivdi3' follow
> >> drivers/md/dm-cache-target.c:429: undefined reference to `__udivdi3'
> >> drivers/md/dm-cache-target.c:429: undefined reference to `__umoddi3'
> > 
> > Hi
> > 
> > I tried to cross-compile dm-cache on linux-next for arm and there were no 
> > failures and no references to __udivdi3 and __umoddi3.
> > 
> > Please send the .config file that resulted in these faulures.
> 
> The config is attached. My guess is it might be related to CONFIG_AEABI
> not set. The compiler is "gcc version 4.6.3 (Ubuntu/Linaro
> 4.6.3-1ubuntu5)" which is ubuntu 12.04 arm cross compiler.
> 
> Rob

This is a problem in gcc-4.6. (gcc-4.7 is OK).

---

bcache: Fix link errors on ARM

gcc-4.6 on ARM has some problem, it creates a function block_div.part.8,
it references __udivdi3 and __umoddi3 and it is never called. The
references to __udivdi3 and __umoddi3 cause a link failure.

__always_inline works around the bug.

Signed-off-by: Mikulas Patocka <mpatocka at redhat.com>

Index: linux-2.6/drivers/md/dm-cache-target.c
===================================================================
--- linux-2.6.orig/drivers/md/dm-cache-target.c	2013-05-14 00:03:53.276986022 +0200
+++ linux-2.6/drivers/md/dm-cache-target.c	2013-05-14 00:34:09.128986023 +0200
@@ -425,6 +425,10 @@
 	return cache->sectors_per_block_shift >= 0;
 }
 
+/* gcc on ARM generates spurious references to __udivdi3 and __umoddi3 */
+#if defined(CONFIG_ARM) && __GNUC__ == 4 && __GNUC_MINOR__ <= 6
+__always_inline
+#endif
 static dm_block_t block_div(dm_block_t b, uint32_t n)
 {
 	do_div(b, n);


From cdall at cs.columbia.edu  Mon May 13 18:42:57 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 13 May 2013 15:42:57 -0700
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM
 VCPU ioctl
In-Reply-To: <519167D3.4030600@linaro.org>
References: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
 <20130513055253.GC64337@ubuntu> <519167D3.4030600@linaro.org>
Message-ID: <CAEDV+gKTYCh8zTPJAxSmwhuyWo7K5Ej75giryR-pv5oqHdURSQ@mail.gmail.com>

On Mon, May 13, 2013 at 3:23 PM, Andre Przywara
<andre.przywara at linaro.org> wrote:
> ooks like a natural candidate, but unfortunately struct kvm_vcpu is opaque
> here, so dereferencing it does not work without further changes which I do
> not deem to be justified. I used kvm_coproc.h instead, which is loosely
> related (KVM_[SG]ET_ONE_REG) and just simply works. If you don't think
> that's appropriate, just drop me a note. Patch follows in a separate mail.

eh, not crazy about the idea. x86 has
arch/x86/include/asm/kvm_guest.h, which may be the most appropriate,
or this could be generalized to other architectures as well and
included in include/linux/kvm_host.h.

we can just stick it in arch/arm/kvm/arm.c for now and move later if
need be, no need to create a fuzz.

-Christoffer


From jason at lakedaemon.net  Mon May 13 19:09:18 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 13 May 2013 19:09:18 -0400
Subject: [PATCH V2 07/10] ARM: mvebu: Use standard MMC binding for all
 users of mvsdio
In-Reply-To: <1368479941-10084-8-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-8-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130513230918.GG31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 11:18:58PM +0200, Simon Baatz wrote:
> In order to prepare the switch to the standard MMC device tree parser
> for mvsdio, adapt all current uses of mvsdio in the dts files to the
> standard format.
> 
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
...
> diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
> index 7588241..bf3a58c 100644
> --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
> +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
> @@ -136,7 +136,7 @@
>  			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
>  			pinctrl-names = "default";
>  			status = "okay";
> -			cd-gpios = <&gpio1 15 0>;
> +			cd-gpios = <&gpio1 15 1>;

Is this a bugfix that should be backported?

thx,

Jason.


From linux at arm.linux.org.uk  Mon May 13 19:07:59 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 14 May 2013 00:07:59 +0100
Subject: rmk not asking Linus to pull for a while...
Message-ID: <20130513230759.GG18614@n2100.arm.linux.org.uk>

Hi all,

In the spirit of keeping people in the picture...

I'm afraid that due to the move of git.linaro.org, I've lost access to
the server, which is where I ask Linus to pull my tree from.  (It was
only through the good graces of Arnd that I even had a heads-up on the
server move.)

I've asked folk at Linaro to investigate the situation is, but it seems
that I need to have something called a "launchpad" account and I've no
idea what one of those is.  So, I don't know how long it's going to take
for this to get sorted - but at least it's someone elses problem. :-)

Unfortunately, Linaro support folk seem to want to send me HTML-encoded
email, which ends up in my little read junk mailboxes, so this will
take a while to progress.

Luckily, I maintain the one on ftp.arm.linux.org.uk, and with most of
China blocked due to _severe_ abuse, the machine is seemingly stable,
albiet rather old and showing its age.  Linux-next hasn't had much
problems with it recently.  So, if I get desperate, I'll ask Linus to
pull from there again, but at the moment I don't have a whole lot of
commits in my tree.


From mturquette at linaro.org  Mon May 13 19:51:19 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Mon, 13 May 2013 16:51:19 -0700
Subject: [PATCH V5 1/6] clk: OMAP: introduce device tree binding to kernel
 clock data
In-Reply-To: <1368039976-29648-2-git-send-email-nm@ti.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
 <1368039976-29648-2-git-send-email-nm@ti.com>
Message-ID: <20130513235119.10068.47040@quantum>

Quoting Nishanth Menon (2013-05-08 12:06:11)
<snip>
> Overall strategy introduced here is simple: a clock node described in
> device tree blob is used to identify the exact clock provided in the
> SoC specific data. This is then linked back using of_clk_add_provider
> to the device node to be accessible by of_clk_get.
> 

FYI, I'm working on moving the OMAP clocks over to DT which is a better
alternative than this patch.  I'll share what I have on the list,
hopefully next week.

Regards,
Mike

> Based on discussion contributions from Roger Quadros, Grygorii Strashko
> and others.
> 
> Cc: Kevin Hilman <khilman at deeprootsystems.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> [tony at atomide.com: co-developed]
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Nishanth Menon <nm at ti.com>
> ---
> Changes in this version:
>         - review comments incorporated.
> Previous version of this patch was discussed in:
>         http://marc.info/?t=136580758500001&r=1&w=2
> 
>  .../devicetree/bindings/clock/omap-clock.txt       |   40 +++++++++
>  drivers/clk/Makefile                               |    1 +
>  drivers/clk/omap/Makefile                          |    1 +
>  drivers/clk/omap/clk.c                             |   91 ++++++++++++++++++++
>  4 files changed, 133 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/omap-clock.txt
>  create mode 100644 drivers/clk/omap/Makefile
>  create mode 100644 drivers/clk/omap/clk.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/omap-clock.txt b/Documentation/devicetree/bindings/clock/omap-clock.txt
> new file mode 100644
> index 0000000..047c1e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/omap-clock.txt
> @@ -0,0 +1,40 @@
> +Device Tree Clock bindings for Texas Instrument's OMAP compatible platforms
> +
> +This binding is an initial minimal binding that may be enhanced as part of
> +transitioning OMAP clock data out of kernel image.
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be "ti,omap-clock"
> +- #clock-cells : from common clock binding; shall be set to 0.
> +NOTE:
> +node name should map to clock database in arch/arm/mach-omap2/cclock<SoC>_data.c
> +Since all clocks are described with _ck, the node name is optimized to drop the
> +usage of _ck. For example, a clock called dpll1_ck will be defined as dpll1.
> +
> +Example #1: describing clock node for CPU on OMAP34xx platform:
> +Ref: arch/arm/mach-omap2/cclock3xxx_data.c
> +describes the CPU clock to be as follows
> +       CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
> +Corresponding binding will be:
> +       dpll1: dpll1 {
> +               #clock-cells = <0>;
> +               compatible = "ti,omap-clock";
> +       };
> +And it's usage will be:
> +               clocks = <&dpll1>;
> +
> +Example #2: describing clock node for auxilary clock #3 on OMAP443x platform:
> +Ref: arch/arm/mach-omap2/cclock44xx_data.c
> +describes the auxclk3 clock to be as follows:
> +       CLK(NULL,       "auxclk3_ck",   &auxclk3_ck,    CK_443X),
> +Corresponding binding will be:
> +       auxclk3: auxclk3 {
> +               #clock-cells = <0>;
> +               compatible = "ti,omap-clock";
> +       };
> +And it's usage will be:
> +       clocks = <&auxclk3>;
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 137d3e7..1d5a2ec 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_VT8500)     += clk-vt8500.o
>  obj-$(CONFIG_ARCH_ZYNQ)                += clk-zynq.o
>  obj-$(CONFIG_ARCH_TEGRA)       += tegra/
>  obj-$(CONFIG_PLAT_SAMSUNG)     += samsung/
> +obj-$(CONFIG_ARCH_OMAP)                += omap/
>  
>  obj-$(CONFIG_X86)              += x86/
>  
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> new file mode 100644
> index 0000000..8195931
> --- /dev/null
> +++ b/drivers/clk/omap/Makefile
> @@ -0,0 +1 @@
> +obj-y                                  += clk.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> new file mode 100644
> index 0000000..5a3c6d9
> --- /dev/null
> +++ b/drivers/clk/omap/clk.c
> @@ -0,0 +1,91 @@
> +/*
> + * Texas Instruments OMAP Clock driver
> + *
> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> + *     Nishanth Menon <nm at ti.com>
> + *     Tony Lindgren <tony at atomide.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/string.h>
> +
> +static const struct of_device_id omap_clk_of_match[] = {
> +       {.compatible = "ti,omap-clock",},
> +       {},
> +};
> +
> +/**
> + * omap_clk_src_get() - Get OMAP clock from node name when needed
> + * @clkspec:   clkspec argument
> + * @data:      unused
> + *
> + * REVISIT: We assume the following:
> + * 1. omap clock names end with _ck
> + * 2. omap clock names are under 32 characters in length
> + */
> +static struct clk *omap_clk_src_get(struct of_phandle_args *clkspec, void *data)
> +{
> +       struct clk *clk;
> +       char clk_name[32];
> +       struct device_node *np = clkspec->np;
> +
> +       snprintf(clk_name, 32, "%s_ck", np->name);
> +       clk = clk_get(NULL, clk_name);
> +       if (IS_ERR(clk))
> +               pr_err("%s: could not get clock %s(%ld)\n", __func__,
> +                      clk_name, PTR_ERR(clk));
> +
> +       return clk;
> +}
> +
> +/**
> + * omap_clk_probe() - create link from DT definition to clock data
> + * @pdev:      device node
> + *
> + * NOTE: we look up the clock lazily when the consumer driver does
> + * of_clk_get() and initialize a NULL clock here.
> + */
> +static int omap_clk_probe(struct platform_device *pdev)
> +{
> +       int res;
> +       struct device_node *np = pdev->dev.of_node;
> +
> +       /* This allows the driver to of_clk_get() */
> +       res = of_clk_add_provider(np, omap_clk_src_get, NULL);
> +       if (res)
> +               dev_err(&pdev->dev, "could not add provider(%d)\n", res);
> +
> +       return res;
> +}
> +
> +static struct platform_driver omap_clk_driver = {
> +       .probe = omap_clk_probe,
> +       .driver = {
> +                  .name = "omap_clk",
> +                  .of_match_table = of_match_ptr(omap_clk_of_match),
> +                  },
> +};
> +
> +static int __init omap_clk_init(void)
> +{
> +       return platform_driver_register(&omap_clk_driver);
> +}
> +arch_initcall(omap_clk_init);
> +
> +MODULE_DESCRIPTION("OMAP Clock driver");
> +MODULE_AUTHOR("Texas Instruments Inc.");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.7.9.5


From khilman at linaro.org  Mon May 13 20:06:56 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Mon, 13 May 2013 17:06:56 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 (Tushar Behera's message of "Fri, 10 May 2013 12:19:59 +0530")
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <87sj1qzaov.fsf@linaro.org>

Tushar Behera <tushar.behera at linaro.org> writes:

> It updates following drivers for EXYNOS based DT platform.
>
> * S5M8767 driver
> * MAX8997 driver
> * MMC SDHCI driver
>
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>

I tested this using v3.10-rc1 on Arndale, but still don't get any
support for the wired network.  Do you know if this is a Kconfig issue,
or a missing driver?

I suspect it may be related to the various "unable to find transceiver
of type USB2 PHY" messages I'm seeing?

Thanks,

Kevin


From horms at verge.net.au  Mon May 13 20:29:43 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 09:29:43 +0900
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: add Ether support
In-Reply-To: <5190E5A5.8030605@cogentembedded.com>
References: <1368173119-27345-1-git-send-email-horms+renesas@verge.net.au>
 <1368173119-27345-2-git-send-email-horms+renesas@verge.net.au>
 <518CCB6A.2060303@cogentembedded.com>
 <20130513004314.GD22911@verge.net.au>
 <5190E5A5.8030605@cogentembedded.com>
Message-ID: <20130514002943.GD12228@verge.net.au>

On Mon, May 13, 2013 at 05:07:49PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 13-05-2013 4:43, Simon Horman wrote:
> 
> >>>Add Ether clock and platform device for R8A7779 SoC; add a function to
> >>>register this device with board-specific platform data.
> 
> >>>Based on a similar change for the r8a7779 by Sergei Shtylyov.
> 
> >>>Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >>>Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> [...]
> 
> >>>diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> >>>index 2e919e6..95b8f7e 100644
> >>>--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
> >>>+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> >>>@@ -1,9 +1,12 @@
> >>>  #ifndef __ASM_R8A7790_H__
> >>>  #define __ASM_R8A7790_H__
> >>>
> >>>+#include <linux/sh_eth.h>
> >>>+
> >>>  void r8a7790_add_standard_devices(void);
> >>>  void r8a7790_clock_init(void);
> >>>  void r8a7790_pinmux_init(void);
> >>>  void r8a7790_timer_init(void);
> >>>+void r8a7790_add_ether_device(struct sh_eth_plat_data *pdata);
> 
> >>    Perhaps better place is right after r8a7790_add_standard_devices()...
> 
> >Is the implication that the struct sh_eth_plat_data can be defined
> >in setup-r8a7790.c?
> 
>    No, why?
> 
> >Or do you for see adding a struct sh_eth_plat_data
> >parameter to r8a7790_add_standard_devices() ?
> 
>    Not at all.

Sorry, I miss-read your previous email.


From horms at verge.net.au  Mon May 13 20:35:04 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 09:35:04 +0900
Subject: [PATCH 05/14] ARM: shmobile: Remove init_irq declaration in
 machine description
In-Reply-To: <1368438253-28218-6-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-6-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130514003504.GE12228@verge.net.au>

On Mon, May 13, 2013 at 11:44:04AM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.

Hi Maxime,

If possible, I would prefer separate patches for each board and SoC.

> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/board-ape6evm.c         | 1 -
>  arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 -
>  arch/arm/mach-shmobile/board-lager.c           | 1 -
>  arch/arm/mach-shmobile/setup-emev2.c           | 1 -
>  arch/arm/mach-shmobile/setup-r8a73a4.c         | 1 -
>  arch/arm/mach-shmobile/setup-r8a7790.c         | 1 -
>  arch/arm/mach-shmobile/setup-sh73a0.c          | 1 -
>  7 files changed, 7 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
> index 55b8c9f..913ce31 100644
> --- a/arch/arm/mach-shmobile/board-ape6evm.c
> +++ b/arch/arm/mach-shmobile/board-ape6evm.c
> @@ -87,7 +87,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(APE6EVM_DT, "ape6evm")
> -	.init_irq	= irqchip_init,
>  	.init_time	= shmobile_timer_init,
>  	.init_machine	= ape6evm_add_standard_devices,
>  	.dt_compat	= ape6evm_boards_compat_dt,
> diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
> index aefa50d..eaec498 100644
> --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
> +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
> @@ -100,7 +100,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
>  	.map_io		= sh73a0_map_io,
>  	.init_early	= sh73a0_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= kzm_init,
>  	.init_time	= shmobile_timer_init,
>  	.dt_compat	= kzm9g_boards_compat_dt,
> diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
> index f587187..c384c9f 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
> @@ -39,7 +39,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(LAGER_DT, "lager")
> -	.init_irq	= irqchip_init,
>  	.init_time	= r8a7790_timer_init,
>  	.init_machine	= lager_add_standard_devices,
>  	.dt_compat	= lager_boards_compat_dt,
> diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
> index 899a86c..098ca63 100644
> --- a/arch/arm/mach-shmobile/setup-emev2.c
> +++ b/arch/arm/mach-shmobile/setup-emev2.c
> @@ -454,7 +454,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
>  	.smp		= smp_ops(emev2_smp_ops),
>  	.init_early	= emev2_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= emev2_add_standard_devices_dt,
>  	.dt_compat	= emev2_boards_compat_dt,
>  MACHINE_END
> diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
> index c5a75a7..6b19d50 100644
> --- a/arch/arm/mach-shmobile/setup-r8a73a4.c
> +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
> @@ -194,7 +194,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
> -	.init_irq	= irqchip_init,
>  	.init_machine	= r8a73a4_add_standard_devices_dt,
>  	.init_time	= shmobile_timer_init,
>  	.dt_compat	= r8a73a4_boards_compat_dt,
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> index 49de2d5..d639aad 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> @@ -142,7 +142,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
> -	.init_irq	= irqchip_init,
>  	.init_machine	= r8a7790_add_standard_devices_dt,
>  	.init_time	= r8a7790_timer_init,
>  	.dt_compat	= r8a7790_boards_compat_dt,
> diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> index fdf3894..3a7d24a 100644
> --- a/arch/arm/mach-shmobile/setup-sh73a0.c
> +++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> @@ -1035,7 +1035,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
>  	.map_io		= sh73a0_map_io,
>  	.init_early	= sh73a0_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= sh73a0_add_standard_devices_dt,
>  	.dt_compat	= sh73a0_boards_compat_dt,
>  MACHINE_END
> -- 
> 1.8.1.2
> 


From shc_work at mail.ru  Mon May 13 13:07:35 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:35 +0400
Subject: [PATCH 13/15] ARM: clps711x: edb7211: Control LCD backlight via PWM
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-16-git-send-email-shc_work@mail.ru>

This patch provide control LCD backlight via PWM. GPIO is used
only for switch backlight ON and OFF.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-edb7211.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 970f4e1..9dfb990 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -109,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
 
 static void edb7211_lcd_backlight_set_intensity(int intensity)
 {
-	gpio_set_value(EDB7211_LCDBL, intensity);
+	gpio_set_value(EDB7211_LCDBL, !!intensity);
+	clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
 }
 
 static struct generic_bl_info edb7211_lcd_backlight_pdata = {
 	.name			= "lcd-backlight.0",
 	.default_intensity	= 0x01,
-	.max_intensity		= 0x01,
+	.max_intensity		= 0x0f,
 	.set_bl_intensity	= edb7211_lcd_backlight_set_intensity,
 };
 
-- 
1.8.1.5



From jg1.han at samsung.com  Mon May 13 21:19:40 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Tue, 14 May 2013 10:19:40 +0900
Subject: [PATCH] ARM: EXYNOS: add PM dependency to PM_GENERIC_DOMAINS for
 Exynos4210
Message-ID: <001a01ce5041$1b9ddd30$52d99790$@samsung.com>

PM_GENERIC_DOMAINS needs PM dependency.

Fixed build warning as below:

warning: (PLAT_S3C64XX && CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM)
warning: (PLAT_S3C64XX && CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM)
arch/arm/kernel/return_address.c:63:2: warning: #warning "TODO: return_address should use unwind tables" [-Wcpp]
drivers/base/power/domain.c: In function '__pm_genpd_add_device':
drivers/base/power/domain.c:1422:2: error: implicit declaration of function 'genpd_acquire_lock'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c:1466:2: error: implicit declaration of function 'genpd_release_lock'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c: In function 'pm_genpd_add_subdomain':
drivers/base/power/domain.c:1649:3: error: implicit declaration of function 'genpd_sd_counter_inc'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c: In function 'pm_genpd_remove_subdomain':
drivers/base/power/domain.c:1721:4: error: implicit declaration of function 'genpd_sd_counter_dec'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c: In function 'pm_genpd_attach_cpuidle':
drivers/base/power/domain.c:1887:2: error: implicit declaration of function 'genpd_recalc_cpu_exit_latency'
[-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
 arch/arm/mach-exynos/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d19edff..1f7ddb2 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -34,7 +34,7 @@ config CPU_EXYNOS4210
 	default y
 	depends on ARCH_EXYNOS4
 	select ARM_CPU_SUSPEND if PM
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
 	select SAMSUNG_DMADEV
-- 
1.7.2.5




From haojian.zhuang at linaro.org  Mon May 13 21:30:38 2013
From: haojian.zhuang at linaro.org (Haojian Zhuang)
Date: Tue, 14 May 2013 09:30:38 +0800
Subject: [PATCH 2/5] clk: hi3xxx: add clock support
In-Reply-To: <20130513194703.10068.4450@quantum>
References: <1366368567-17322-1-git-send-email-haojian.zhuang@linaro.org>
 <1366368567-17322-2-git-send-email-haojian.zhuang@linaro.org>
 <20130513194703.10068.4450@quantum>
Message-ID: <CAD6h2NRqR4Qzpj8x7XTZZ+T==yBf3rq_VooAXNO4HOHb74pGZQ@mail.gmail.com>

On 14 May 2013 03:47, Mike Turquette <mturquette at linaro.org> wrote:
> Quoting Haojian Zhuang (2013-04-19 03:49:24)
>> diff --git a/drivers/clk/clk-hi3xxx.c b/drivers/clk/clk-hi3xxx.c
>> new file mode 100644
>> index 0000000..e93e583
>> --- /dev/null
>> +++ b/drivers/clk/clk-hi3xxx.c
>> @@ -0,0 +1,641 @@
>> +/*
>> + * Hisilicon clock driver
>> + *
>> + * Copyright (c) 2012-2013 Hisilicon Limited.
>> + * Copyright (c) 2012-2013 Linaro Limited.
>> + *
>> + * Author: Haojian Zhuang <haojian.zhuang at linaro.org>
>> + *        Xin Li <li.xin at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, write to the Free Software Foundation, Inc.,
>> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>> + *
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/clk-private.h>
>
> clk-private.h is deprecated and can no longer be included by any new
> clock drivers.  It will hopefully be removed in 3.11.  Please remove it
> in your next version.
>
OK. I'll remove it.

>> +#include <linux/clkdev.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_device.h>
>> +#include <linux/slab.h>
>> +#include <linux/clk.h>
>> +
>> +#define HI3620_DISABLE_OFF             0x4
>> +#define HI3620_STATUS_OFF              0x8
>> +
>> +#define WIDTH_TO_MASK(width)   ((1 << (width)) - 1)
>> +
>> +/*
>> + * The reverse of DIV_ROUND_UP: The maximum number which
>> + * divided by m is r
>> + */
>> +#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
>> +
>> +struct hi3620_periclk {
>> +       struct clk_hw   hw;
>> +       void __iomem    *enable;        /* enable register */
>> +       void __iomem    *reset;         /* reset register */
>> +       u32             ebits;          /* bits in enable/disable register */
>> +       u32             rbits;          /* bits in reset/unreset register */
>> +       spinlock_t      *lock;
>> +};
>> +
>> +struct hi3620_muxclk {
>> +       struct clk_hw   hw;
>> +       void __iomem    *reg;           /* mux register */
>> +       u8              shift;
>> +       u8              width;
>> +       u32             mbits;          /* mask bits in mux register */
>
> You need shift, width AND a mask?  Normally either shift+width OR a mask
> would suffice.

No, it's a little different. In their mux registers, there're two
parts. One is lower
16 bits that are used to set mux, and the other is higher 16 bits that are
used to set mux mask.

At here, I use mbits for higher 16 bits and shift & width for lower 16 bits.

>
>> +       spinlock_t      *lock;
>> +};
>> +
>> +struct hi3620_divclk {
>> +       struct clk_hw   hw;
>> +       void __iomem    *reg;           /* divider register */
>> +       u8              shift;
>> +       u8              width;
>> +       u32             mbits;          /* mask bits in divider register */
>
> Ditto.

I can't replace. There's the same reason in above.

>
>> +       const struct clk_div_table      *table;
>> +       spinlock_t      *lock;
>> +};
>> +
>> +struct hs_clk {
>> +       void __iomem    *pmctrl;
>> +       void __iomem    *sctrl;
>> +       spinlock_t      lock;
>> +};
>> +
>> +static struct hs_clk hs_clk;
>> +
>> +static void __init hs_init_clocks(void)
>> +{
>> +       struct device_node *node = NULL;
>> +
>> +       if (!hs_clk.pmctrl) {
>> +               /* map pmctrl registers */
>> +               node = of_find_compatible_node(NULL, NULL, "hisilicon,pmctrl");
>> +               hs_clk.pmctrl = of_iomap(node, 0);
>> +               WARN_ON(!hs_clk.pmctrl);
>> +       }
>> +
>> +       if (!hs_clk.sctrl) {
>> +               node = of_find_compatible_node(NULL, NULL, "hisilicon,sctrl");
>> +               hs_clk.sctrl = of_iomap(node, 0);
>> +       }
>> +}
>> +
>> +static int hi3620_clkgate_prepare(struct clk_hw *hw)
>> +{
>> +       struct hi3620_periclk *pclk;
>> +       unsigned long flags = 0;
>> +
>> +       pclk = container_of(hw, struct hi3620_periclk, hw);
>> +
>> +       if (pclk->lock)
>> +               spin_lock_irqsave(pclk->lock, flags);
>> +       writel_relaxed(pclk->ebits, pclk->enable + HI3620_DISABLE_OFF);
>> +       writel_relaxed(pclk->rbits, pclk->reset + HI3620_DISABLE_OFF);
>> +       readl_relaxed(pclk->reset + HI3620_STATUS_OFF);
>> +       if (pclk->lock)
>> +               spin_unlock_irqrestore(pclk->lock, flags);
>> +       return 0;
>> +}
>> +
>> +static int hi3620_clkgate_enable(struct clk_hw *hw)
>> +{
>> +       struct hi3620_periclk *pclk;
>> +       unsigned long flags = 0;
>> +
>> +       pclk = container_of(hw, struct hi3620_periclk, hw);
>> +       if (pclk->lock)
>> +               spin_lock_irqsave(pclk->lock, flags);
>> +       writel_relaxed(pclk->ebits, pclk->enable);
>> +       readl_relaxed(pclk->enable + HI3620_STATUS_OFF);
>> +       if (pclk->lock)
>> +               spin_unlock_irqrestore(pclk->lock, flags);
>> +       return 0;
>> +}
>> +
>> +static void hi3620_clkgate_disable(struct clk_hw *hw)
>> +{
>> +       struct hi3620_periclk *pclk;
>> +       unsigned long flags = 0;
>> +
>> +       pclk = container_of(hw, struct hi3620_periclk, hw);
>> +       if (pclk->lock)
>> +               spin_lock_irqsave(pclk->lock, flags);
>> +       writel_relaxed(pclk->ebits, pclk->enable + HI3620_DISABLE_OFF);
>> +       readl_relaxed(pclk->enable + HI3620_STATUS_OFF);
>> +       if (pclk->lock)
>> +               spin_unlock_irqrestore(pclk->lock, flags);
>> +}
>> +
>> +static struct clk_ops hi3620_clkgate_ops = {
>> +       .prepare        = hi3620_clkgate_prepare,
>> +       .enable         = hi3620_clkgate_enable,
>> +       .disable        = hi3620_clkgate_disable,
>
> .unprepare?

I didn't implement unprepare at here. Since I find some device controller
as uart not working if I disable clocks in unprepare(). Now I leave it as
unimplemented.

>
>> +};
>> +
>> +static void __init hi3620_clkgate_setup(struct device_node *np)
>> +{
>> +       struct hi3620_periclk *pclk;
>> +       struct clk_init_data *init;
>> +       struct clk *clk;
>> +       const char *clk_name, *name, **parent_names;
>> +       u32 rdata[2], gdata[2];
>> +
>> +       if (!hs_clk.sctrl)
>> +               return;
>> +
>> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
>> +               return;
>> +       if (of_property_read_u32_array(np, "hisilicon,hi3620-clkreset",
>> +                                      &rdata[0], 2))
>> +               return;
>> +       if (of_property_read_u32_array(np, "hisilicon,hi3620-clkgate",
>> +                                      &gdata[0], 2))
>> +               return;
>> +
>> +       /* gate only has the fixed parent */
>> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
>> +       if (!parent_names)
>> +               return;
>> +       parent_names[0] = of_clk_get_parent_name(np, 0);
>> +
>> +       pclk = kzalloc(sizeof(*pclk), GFP_KERNEL);
>> +       if (!pclk)
>> +               goto err_pclk;
>> +
>> +       init = kzalloc(sizeof(*init), GFP_KERNEL);
>> +       if (!init)
>> +               goto err_init;
>> +       init->name = kstrdup(clk_name, GFP_KERNEL);
>> +       init->ops = &hi3620_clkgate_ops;
>> +       init->flags = CLK_SET_RATE_PARENT;
>> +       init->parent_names = parent_names;
>> +       init->num_parents = 1;
>> +
>> +       pclk->reset = hs_clk.sctrl + rdata[0];
>> +       pclk->rbits = rdata[1];
>> +       pclk->enable = hs_clk.sctrl + gdata[0];
>> +       pclk->ebits = gdata[1];
>> +       pclk->lock = &hs_clk.lock;
>> +       pclk->hw.init = init;
>> +
>> +       clk = clk_register(NULL, &pclk->hw);
>> +       if (IS_ERR(clk))
>> +               goto err_clk;
>> +       if (!of_property_read_string(np, "clock-names", &name))
>> +               clk_register_clkdev(clk, name, NULL);
>> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
>> +       return;
>> +err_clk:
>> +       kfree(init);
>> +err_init:
>> +       kfree(pclk);
>> +err_pclk:
>> +       kfree(parent_names);
>> +}
>> +
>> +static u8 hi3620_clk_get_parent(struct clk_hw *hw)
>> +{
>> +       struct hi3620_muxclk *mclk;
>> +       u32 data;
>> +       unsigned long flags = 0;
>> +
>> +       mclk = container_of(hw, struct hi3620_muxclk, hw);
>> +
>> +       if (mclk->lock)
>> +               spin_lock_irqsave(mclk->lock, flags);
>> +
>> +       data = readl_relaxed(mclk->reg) >> mclk->shift;
>> +       data &= WIDTH_TO_MASK(mclk->width);
>> +
>> +       if (mclk->lock)
>> +               spin_unlock_irqrestore(mclk->lock, flags);
>> +
>> +       if (data >= __clk_get_num_parents(hw->clk))
>> +               return -EINVAL;
>> +
>> +       return (u8)data;
>> +}
>> +
>> +static int hi3620_clk_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +       struct hi3620_muxclk *mclk;
>> +       u32 data;
>> +       unsigned long flags = 0;
>> +
>> +       mclk = container_of(hw, struct hi3620_muxclk, hw);
>> +
>> +       if (mclk->lock)
>> +               spin_lock_irqsave(mclk->lock, flags);
>> +
>> +       data = readl_relaxed(mclk->reg);
>> +       data &= ~(WIDTH_TO_MASK(mclk->width) << mclk->shift);
>> +       data |= index << mclk->shift;
>> +       writel_relaxed(data, mclk->reg);
>> +       /* set mask enable bits */
>> +       data |= mclk->mbits;
>> +       writel_relaxed(data, mclk->reg);
>
> Is mclk->mbits equivalent to (mclk->width << mclk->shift)?  If so you
> can drop shift+width and use only the mask + helpers like ffs().  If
> that is the case then this clock can probably use the generic clk-mux
> type.

No, I can't replace. Since they have higher 16 bits for mask bits.

>
>> +
>> +       if (mclk->lock)
>> +               spin_unlock_irqrestore(mclk->lock, flags);
>> +
>> +       return 0;
>> +}
>> +
>> +static struct clk_ops hi3620_clkmux_ops = {
>> +       .get_parent     = hi3620_clk_get_parent,
>> +       .set_parent     = hi3620_clk_set_parent,
>> +};
>> +
>> +static void __init hi3620_clkmux_setup(struct device_node *np)
>> +{
>> +       struct hi3620_muxclk *mclk;
>> +       struct clk_init_data *init;
>> +       struct clk *clk;
>> +       const char *clk_name, **parent_names;
>> +       u32 rdata[2];
>> +       u8 num_parents;
>> +       int i;
>> +
>> +       hs_init_clocks();
>> +       if (!hs_clk.sctrl)
>> +               return;
>> +
>> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
>> +               return;
>> +       if (of_property_read_u32_array(np, "hisilicon,hi3620-clkmux",
>> +                                      &rdata[0], 2))
>> +               return;
>> +       /* get the count of items in mux */
>> +       for (i = 0; ; i++) {
>> +               /* parent's #clock-cells property is always 0 */
>> +               if (!of_parse_phandle(np, "clocks", i))
>> +                       break;
>> +       }
>> +       parent_names = kzalloc(sizeof(char *) * i, GFP_KERNEL);
>> +       if (!parent_names)
>> +               return;
>> +
>> +       for (num_parents = i, i = 0; i < num_parents; i++)
>> +               parent_names[i] = of_clk_get_parent_name(np, i);
>> +
>> +       mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
>> +       if (!mclk)
>> +               goto err_mclk;
>> +       init = kzalloc(sizeof(*init), GFP_KERNEL);
>> +       if (!init)
>> +               goto err_init;
>> +       init->name = kstrdup(clk_name, GFP_KERNEL);
>> +       init->ops = &hi3620_clkmux_ops;
>> +       init->flags = CLK_SET_RATE_PARENT;
>> +       init->parent_names = parent_names;
>> +       init->num_parents = num_parents;
>> +
>> +       mclk->reg = hs_clk.sctrl + rdata[0];
>> +       /* enable_mask bits are in higher 16bits */
>> +       mclk->mbits = rdata[1] << 16;
>> +       mclk->shift = ffs(rdata[1]) - 1;
>> +       mclk->width = fls(rdata[1]) - ffs(rdata[1]) + 1;
>> +       mclk->lock = &hs_clk.lock;
>> +       mclk->hw.init = init;
>> +
>> +       clk = clk_register(NULL, &mclk->hw);
>> +       if (IS_ERR(clk))
>> +               goto err_clk;
>> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
>> +
>> +       return;
>> +err_clk:
>> +       kfree(init);
>> +err_init:
>> +       kfree(mclk);
>> +err_mclk:
>> +       kfree(parent_names);
>> +}
>> +
>> +static void __init hs_clkgate_setup(struct device_node *np)
>> +{
>> +       struct clk *clk;
>> +       const char *clk_name, **parent_names, *name;
>> +       unsigned long flags = 0;
>> +       u32 data[2];
>> +
>> +       hs_init_clocks();
>> +       if (!hs_clk.sctrl)
>> +               return;
>> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
>> +               return;
>> +       if (of_property_read_u32_array(np, "hisilicon,clkgate",
>> +                                      &data[0], 2))
>> +               return;
>> +       if (of_property_read_bool(np, "hisilicon,clkgate-inverted"))
>> +               flags = CLK_GATE_SET_TO_DISABLE;
>> +       /* gate only has the fixed parent */
>> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
>> +       if (!parent_names)
>> +               return;
>> +       parent_names[0] = of_clk_get_parent_name(np, 0);
>> +
>> +       clk = clk_register_gate(NULL, clk_name, parent_names[0], 0,
>> +                               hs_clk.sctrl + data[0], (u8)data[1], flags,
>> +                               &hs_clk.lock);
>> +       if (IS_ERR(clk))
>> +               goto err;
>> +       if (!of_property_read_string(np, "clock-names", &name))
>> +               clk_register_clkdev(clk, name, NULL);
>> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
>> +       return;
>> +err:
>> +       kfree(parent_names);
>> +}
>
> I'm working on clock bindings for the generic clock types, so hopefully
> this can be replaced by those instead of using your own compatible
> string to wrap around clk_register_gate.

It's great. Could you cc me when you send patches out?

>
>> +
>> +void __init hs_fixed_factor_setup(struct device_node *np)
>> +{
>> +       struct clk *clk;
>> +       const char *clk_name, **parent_names;
>> +       u32 data[2];
>> +
>> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
>> +               return;
>> +       if (of_property_read_u32_array(np, "hisilicon,fixed-factor",
>> +                                      data, 2))
>> +               return ;
>> +       /* gate only has the fixed parent */
>> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
>> +       if (!parent_names)
>> +               return;
>> +       parent_names[0] = of_clk_get_parent_name(np, 0);
>> +
>> +       clk = clk_register_fixed_factor(NULL, clk_name, parent_names[0], 0,
>> +                                       data[0], data[1]);
>> +       if (IS_ERR(clk))
>> +               goto err;
>> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
>> +       return;
>> +err:
>> +       kfree(parent_names);
>> +}
>
> Ditto.
>
>> +
>> +static unsigned int hi3620_get_table_maxdiv(const struct clk_div_table *table)
>> +{
>> +       unsigned int maxdiv = 0;
>> +       const struct clk_div_table *clkt;
>> +
>> +       for (clkt = table; clkt->div; clkt++)
>> +               if (clkt->div > maxdiv)
>> +                       maxdiv = clkt->div;
>> +       return maxdiv;
>> +}
>> +
>> +static unsigned int hi3620_get_table_div(const struct clk_div_table *table,
>> +                                                       unsigned int val)
>> +{
>> +       const struct clk_div_table *clkt;
>> +
>> +       for (clkt = table; clkt->div; clkt++)
>> +               if (clkt->val == val)
>> +                       return clkt->div;
>> +       return 0;
>> +}
>> +
>> +static unsigned int hi3620_get_table_val(const struct clk_div_table *table,
>> +                                        unsigned int div)
>> +{
>> +       const struct clk_div_table *clkt;
>> +
>> +       for (clkt = table; clkt->div; clkt++)
>> +               if (clkt->div == div)
>> +                       return clkt->val;
>> +       return 0;
>> +}
>> +
>> +static unsigned long hi3620_clkdiv_recalc_rate(struct clk_hw *hw,
>> +                                              unsigned long parent_rate)
>> +{
>> +       struct hi3620_divclk *dclk = container_of(hw, struct hi3620_divclk, hw);
>> +       unsigned int div, val;
>> +
>> +       val = readl_relaxed(dclk->reg) >> dclk->shift;
>> +       val &= WIDTH_TO_MASK(dclk->width);
>> +
>> +       div = hi3620_get_table_div(dclk->table, val);
>> +       if (!div) {
>> +               pr_warning("%s: Invalid divisor for clock %s\n", __func__,
>> +                          __clk_get_name(hw->clk));
>> +               return parent_rate;
>> +       }
>> +
>> +       return parent_rate / div;
>> +}
>> +
>> +static bool hi3620_is_valid_table_div(const struct clk_div_table *table,
>> +                                     unsigned int div)
>> +{
>> +       const struct clk_div_table *clkt;
>> +
>> +       for (clkt = table; clkt->div; clkt++)
>> +               if (clkt->div == div)
>> +                       return true;
>> +       return false;
>> +}
>> +
>> +static int hi3620_clkdiv_bestdiv(struct clk_hw *hw, unsigned long rate,
>> +                                unsigned long *best_parent_rate)
>> +{
>> +       struct hi3620_divclk *dclk = container_of(hw, struct hi3620_divclk, hw);
>> +       struct clk *clk_parent = __clk_get_parent(hw->clk);
>> +       int i, bestdiv = 0;
>> +       unsigned long parent_rate, best = 0, now, maxdiv;
>> +
>> +       maxdiv = hi3620_get_table_maxdiv(dclk->table);
>> +
>> +       if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
>> +               parent_rate = *best_parent_rate;
>> +               bestdiv = DIV_ROUND_UP(parent_rate, rate);
>> +               bestdiv = bestdiv == 0 ? 1 : bestdiv;
>> +               bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
>> +               return bestdiv;
>> +       }
>> +
>> +       /*
>> +        * The maximum divider we can use without overflowing
>> +        * unsigned long in rate * i below
>> +        */
>> +       maxdiv = min(ULONG_MAX / rate, maxdiv);
>> +
>> +       for (i = 1; i <= maxdiv; i++) {
>> +               if (!hi3620_is_valid_table_div(dclk->table, i))
>> +                       continue;
>> +               parent_rate = __clk_round_rate(clk_parent,
>> +                                              MULT_ROUND_UP(rate, i));
>> +               now = parent_rate / i;
>> +               if (now <= rate && now > best) {
>> +                       bestdiv = i;
>> +                       best = now;
>> +                       *best_parent_rate = parent_rate;
>> +               }
>> +       }
>> +
>> +       if (!bestdiv) {
>> +               bestdiv = hi3620_get_table_maxdiv(dclk->table);
>> +               *best_parent_rate = __clk_round_rate(clk_parent, 1);
>> +       }
>> +
>> +       return bestdiv;
>> +}
>> +
>> +static long hi3620_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,
>> +                                    unsigned long *prate)
>> +{
>> +       int div;
>> +
>> +       if (!rate)
>> +               rate = 1;
>> +       div = hi3620_clkdiv_bestdiv(hw, rate, prate);
>> +
>> +       return *prate / div;
>> +}
>> +
>> +static int hi3620_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,
>> +                                 unsigned long parent_rate)
>> +{
>> +       struct hi3620_divclk *dclk = container_of(hw, struct hi3620_divclk, hw);
>> +       unsigned int div, value;
>> +       unsigned long flags = 0;
>> +       u32 data;
>> +
>> +       div = parent_rate / rate;
>> +       value = hi3620_get_table_val(dclk->table, div);
>> +
>> +       if (value > WIDTH_TO_MASK(dclk->width))
>> +               value = WIDTH_TO_MASK(dclk->width);
>> +
>> +       if (dclk->lock)
>> +               spin_lock_irqsave(dclk->lock, flags);
>> +
>> +       data = readl_relaxed(dclk->reg);
>> +       data &= ~(WIDTH_TO_MASK(dclk->width) << dclk->shift);
>> +       data |= value << dclk->shift;
>> +       data |= dclk->mbits;
>> +       writel_relaxed(data, dclk->reg);
>> +
>> +       if (dclk->lock)
>> +               spin_unlock_irqrestore(dclk->lock, flags);
>> +
>> +       return 0;
>> +}
>> +
>> +static struct clk_ops hi3620_clkdiv_ops = {
>> +       .recalc_rate = hi3620_clkdiv_recalc_rate,
>> +       .round_rate = hi3620_clkdiv_round_rate,
>> +       .set_rate = hi3620_clkdiv_set_rate,
>> +};
>> +
>> +void __init hi3620_clkdiv_setup(struct device_node *np)
>> +{
>> +       struct clk *clk;
>> +       const char *clk_name, **parent_names;
>> +       struct clk_init_data *init;
>> +       struct clk_div_table *table;
>> +       struct hi3620_divclk *dclk;
>> +       unsigned int table_num;
>> +       int i;
>> +       u32 data[2];
>> +       const char *propname = "hisilicon,clkdiv-table";
>> +       const char *cellname = "#hisilicon,clkdiv-table-cells";
>> +       struct of_phandle_args div_table;
>> +
>> +       hs_init_clocks();
>> +       if (!hs_clk.sctrl)
>> +               return;
>> +
>> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
>> +               return;
>> +       if (of_property_read_u32_array(np, "hisilicon,clkdiv",
>> +                                      &data[0], 2))
>> +               return;
>> +
>> +       /*process the div_table*/
>> +       for (i = 0; ; i++) {
>> +               if (of_parse_phandle_with_args(np, propname, cellname,
>> +                                              i, &div_table))
>> +                       break;
>> +       }
>> +
>> +       /*table ends with <0, 0>, so plus one to table_num*/
>> +       table_num = i + 1;
>> +
>> +       table = kzalloc(sizeof(struct clk_div_table) * table_num, GFP_KERNEL);
>> +       if (!table)
>> +               return ;
>> +
>> +       for (i = 0; ; i++) {
>> +               if (of_parse_phandle_with_args(np, propname, cellname,
>> +                                              i, &div_table))
>> +                       break;
>> +
>> +               table[i].val = div_table.args[0];
>> +               table[i].div = div_table.args[1];
>> +       }
>> +
>> +       /* gate only has the fixed parent */
>> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
>> +       if (!parent_names)
>> +               goto err_par;
>> +       parent_names[0] = of_clk_get_parent_name(np, 0);
>> +
>> +       dclk = kzalloc(sizeof(*dclk), GFP_KERNEL);
>> +       if (!dclk)
>> +               goto err_dclk;
>> +       init = kzalloc(sizeof(*init), GFP_KERNEL);
>> +       if (!init)
>> +               goto err_init;
>> +       init->name = kstrdup(clk_name, GFP_KERNEL);
>> +       init->ops = &hi3620_clkdiv_ops;
>> +       init->parent_names = parent_names;
>> +       init->num_parents = 1;
>> +
>> +       dclk->reg = hs_clk.sctrl + data[0];
>> +       dclk->shift = ffs(data[1]) - 1;
>> +       dclk->width = fls(data[1]) - ffs(data[1]) + 1;
>> +       dclk->mbits = data[1] << 16;
>> +       dclk->lock = &hs_clk.lock;
>> +       dclk->hw.init = init;
>> +       dclk->table = table;
>> +       clk = clk_register(NULL, &dclk->hw);
>> +       if (IS_ERR(clk))
>> +               goto err_clk;
>> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
>> +       return;
>> +err_clk:
>> +       kfree(init);
>> +err_init:
>> +       kfree(dclk);
>> +err_dclk:
>> +       kfree(parent_names);
>> +err_par:
>> +       kfree(table);
>> +}
>
> This looks like it was copy/pasted from the generic clk-divider type.
> Is there some reason you cannot use that instead of duplicating all of
> that code here?

Yes, it's a copy. The registers are not wrapped in their silicon. In most
vendor's SoC, the registers are read/write.

But they links the read/write to different registers. So one clock divider
register is split into four registers, and they're set, unset, status & final
status.

And the other reason is that they use higher 16 bits as mask bits. So
they're not compatible with other vendor's SoC. Of course, I can also
use generic clk-divider/clk-mux type, but I need to change a lot in
common files, such as abstracting read/write. Is it OK for you?

Regards
Haojian

>
> Thanks,
> Mike
>
>> +CLK_OF_DECLARE(hi3620_mux, "hisilicon,hi3620-clk-mux", hi3620_clkmux_setup)
>> +CLK_OF_DECLARE(hi3620_gate, "hisilicon,hi3620-clk-gate", hi3620_clkgate_setup)
>> +CLK_OF_DECLARE(hi3620_div, "hisilicon,hi3620-clk-div", hi3620_clkdiv_setup)
>> +CLK_OF_DECLARE(hs_gate, "hisilicon,clk-gate", hs_clkgate_setup)
>> +CLK_OF_DECLARE(hs_fixed, "hisilicon,clk-fixed-factor", hs_fixed_factor_setup)
>> --
>> 1.7.10.4


From wlewis569 at gmail.com  Mon May 13 22:01:08 2013
From: wlewis569 at gmail.com (Walter Lewis)
Date: Mon, 13 May 2013 21:01:08 -0500
Subject: owfs hangup on Linux 3.0.4 using DS28EC20 Dallas 1-wire EEPROM
Message-ID: <40441033-818A-4634-8E02-20567162B98B@gmail.com>

Greetings,

I am implementing a Maxim 1-Wire DS28EC20 EEPROM on an embedded Linux application with the objective of writing identification information and manufacturing data on a removable component.  I have configured the kernel for 1-Wire support, and have applied the patch for the w1-gpio module implementation. When I insert the w1-gpio module, the /sys/bus/w1 directory becomes present and the target EEPROM is reported.  There is a file present named rw which I can cat (looks binary), but when I pipe data to it, and then read it back, it does not change. I suspect the block nature of the device and its control mechanisms require a more sophisticated write operation. I investigated the owfs which supports read and write on the DS_2433 EEPROM, and am attempting to implement it.  When I do not have the device attached, using owfs, I can 'ls' the owfs mount point.  When a device is attached and the Linux w1 directory (/sys/bus/w1/...) shows it, a 'ls' command on the owfs mount point causes the owfs application to become unresponsive and the ls command never completes. owfs in background mode does not respond to a control C and requires a kill -9 to stop, and once stopped, the ownership and permissions of the owfs mountpoint appear corrupted.  A power cycle restores the mount point. owfs in forground mode does respond to control C and leaves the ownership and permissions in a sane state.

In order to isolate the problem, I have attempted this implementation using owfs with the w1_kernel module and a file system mountpoint; owhttpd with the w1 kernel module and a web page display; and with a owserver with w1 kernel module and a socket connection paired with a owhttpd server attached to the socket connection and a web page display. None of these combinations has solved the hang up condition and output is not to the file system or web page. The 'looking for directory and directory not found' errors occur in owfs, owhttpd and owserver when the component becomes visible to the kernel. I have also tried this with DS2431 EEPROM with the same results.

Below is my system information.  To get to the place where the error occurs, search for: **** ERROR *** . Also, note that the looking for directory and directory not found errors occur in owhttpd and owserver when the component becomes visible to the kernel.

Thank you in advance for your help and assistance.  Please let me know if you need more information or have something you would like me to try.

Walter,

Details:

My target system is a Vendor's TI Omap 4460 based System On a Module, running the omap linux kernel version 3.0.4 (uname -a: Linux <HOST> 3.4.0-1489-omap4 #26~Custom SMP PREEMPT Sat May 11 10:56:25 CDT 2013 armv7l armv7l armv7l GNU/Linux.  I cannot advance this kernel revision until our Vendor supports a newer version. This is cross compiled from a Ubuntu development system, (uname -a: Linux <host> 3.2.0-41-generic #66-Ubuntu SMP Thu Apr 25 03:27:11 UTC 2013 x86_64 x86_64 x86_64 GNU/Linux) with the 'arm-linux-gnueabihf' cross compiler.

My kernel configuration options are:
(1-Wire)
    CONFIG_W1=m
    CONFIG_W1_CON=y
    CONFIG_W1_MASTER_DS1WM=m
    CONFIG_W1_MASTER_DS2482=m
    CONFIG_W1_MASTER_DS2490=m
    CONFIG_W1_MASTER_GPIO=m
    CONFIG_W1_SLAVE_BQ27000=m
    CONFIG_W1_SLAVE_DS2408=m
    CONFIG_W1_SLAVE_DS2423=m
    CONFIG_W1_SLAVE_DS2431=m
    CONFIG_W1_SLAVE_DS2433=m
    # CONFIG_W1_SLAVE_DS2433_CRC is not set
    CONFIG_W1_SLAVE_DS2760=m
    CONFIG_W1_SLAVE_DS2780=m
    # CONFIG_W1_SLAVE_DS2781 is not set
    CONFIG_W1_SLAVE_SMEM=m
    CONFIG_W1_SLAVE_THERM=m
(Fuse)
    CONFIG_FUSE_FS=y

I installed owfs by:
Downloading from SourceForge, the latest version of owfs (owfs-2.9p0.tar.gz), and copied it to the target system.
Logged in as root on the target system, I:
    expanded the download package on the target system, ran configure, make, and make install. 
    owfs was missing because the fuse.h file could not be found. 
    I ran apt-get install libfuse-dev
    I deleted the unzipped owfs directory, and performed the installation again.  This was successful.

I inserted the w1 modules using modprobe.  I have tried this with w1-gpio (+ wire); w1_ds2433 (+ wire); and w1_gpio and w1_ds2433 (+wire).  According to the Maxim datasheet, the DS28EC20 is highly backwards compatible with the 2433 part.

As described above, when the part is attached, the kernel shows the part's presence, bit the owfs mount point hangs up when attempting to display it.

Case 1: owfs implementation

Kernel /sys/bus without modules does not include a w1 directory

Load modules ---
10.20.30.41:/tmp# modprobe w1_gpio
10.20.30.41:/tmp# modprobe w1_ds2433
10.20.30.41:/tmp# lsmod | grep w
w1_ds2433               2233  0
w1_gpio                 1645  0
wire                   26865  2 w1_ds2433,w1_gpio

Kernel /sys/bus after loading modules includes a w1 directory
10.20.30.41:/tmp# ls /sys/bus/w1
total 0
drwxr-xr-x  4 root root    0 May 13 19:32 .
drwxr-xr-x 21 root root    0 Jan  1  2000 ..
drwxr-xr-x  2 root root    0 May 13 19:32 devices
drwxr-xr-x  4 root root    0 May 13 19:32 drivers
-rw-r--r--  1 root root 4.0K May 13 19:32 drivers_autoprobe
--w-------  1 root root 4.0K May 13 19:32 drivers_probe
--w-------  1 root root 4.0K May 13 19:32 uevent
10.20.30.41:/tmp# ls /sys/bus/w1/devices/
total 0
drwxr-xr-x 2 root root 0 May 13 19:32 .
drwxr-xr-x 4 root root 0 May 13 19:32 ..
lrwxrwxrwx 1 root root 0 May 13 19:33 w1_bus_master1 -> ../../../devices/w1_bus_master1

After attaching the 1-Wire EEPROM
10.20.30.41:/tmp# ls /sys/bus/w1/devices/
total 0
drwxr-xr-x 2 root root 0 May 13 19:32 .
drwxr-xr-x 4 root root 0 May 13 19:32 ..
lrwxrwxrwx 1 root root 0 May 13 19:34 43-0000003be97b -> ../../../devices/w1_bus_master1/43-0000003be97b
lrwxrwxrwx 1 root root 0 May 13 19:33 w1_bus_master1 -> ../../../devices/w1_bus_master1

Removed the 1-Wire EEPROM

owfs mount point without EEPROM present or owfs running

10.20.30.41:/tmp# ls /mnt
total 5.0K
drwxr-xr-x  5 root root 1.0K May 13 19:37 .
drwxr-xr-x 23 root root 1.0K May 13 11:33 ..
drwxr-xr-x  2 root root 1.0K Mar 31 19:35 jj
drwxr-xr-x  2 root root 1.0K Oct  9  2012 sda1
drwxr-xr-x  2 root root 1.0K May 13 14:31 w1
10.20.30.41:/tmp# ls /mnt/w1
total 2.0K
drwxr-xr-x 2 root root 1.0K May 13 14:31 .
drwxr-xr-x 5 root root 1.0K May 13 19:37 ..

Run owfs with debugging enabled
10.20.30.41:/tmp# owfs --foreground --error_level=9 --w1 -m /mnt/w1
CONNECT: owfs.c:(96) fuse mount point: /mnt/w1
CONNECT: ow_avahi_link.c:(68) No Avahi support. Library libavahi-client couldn't be loaded
CONNECT: ow_dnssd.c:(82) Zeroconf/Bonjour is disabled since dnssd library isn't found
   CALL: ow_parsename.c:(98) path=[]
  DEBUG: owlib.c:(81) Globals temp limits 0C 100C (for simulated adapters)
  DEBUG: fuse_line.c:(82) Added FUSE option 0 OWFS
  DEBUG: fuse_line.c:(82) Added FUSE option 1 /mnt/w1
  DEBUG: fuse_line.c:(82) Added FUSE option 2 -o
  DEBUG: fuse_line.c:(82) Added FUSE option 3 direct_io
  DEBUG: fuse_line.c:(82) Added FUSE option 4 -f
  DEBUG: fuse_line.c:(82) Added FUSE option 5 -d
  DEBUG: owfs.c:(121) fuse_mnt_opt=[(null)]
  DEBUG: owfs.c:(123) fuse_open_opt=[(null)]
  DEBUG: ow_w1_list.c:(54) Sending w1 bus master list message
  DEBUG: ow_w1_send.c:(132) Netlink send -----------------
NLMSGHDR: len=48 type=3 (NLMSG_DONE) flags=5 seq=0|1 pid=2921
CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=0|1 ack=1 len=12 flags=0
W1_NETLINK_MSG: type=6 (W1_LIST_MASTERS) len=0 id=0
W1_NETLINK_CMD: NULL w1c field
NULL data
  DEBUG: ow_w1_send.c:(143) NETLINK sent seq=1
  DEBUG: ow_w1_dispatch.c:(173) Dispatch loop
  DEBUG: ow_w1_parse.c:(113) Wait to peek at message
  DEBUG: ow_w1_parse.c:(121) Pre-parse header: 16 bytes len=52 type=3 seq=0|1 pid=0
  DEBUG: ow_w1_parse.c:(142) Netlink read -----------------
NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=0 seq=0|1 pid=0
CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=0|1 ack=0 len=16 flags=12141
W1_NETLINK_MSG: type=6 (W1_LIST_MASTERS) len=4 id=1768713839
W1_NETLINK_CMD: NULL w1c field
Byte buffer Data, length=4
--000: 01 00 00 00
   <....>
  DEBUG: ow_w1_dispatch.c:(88) Netlink message directed to root W1 master
  DEBUG: ow_w1_dispatch.c:(126) Sending this packet to root bus
  DEBUG: ow_w1_dispatch.c:(173) Dispatch loop
  DEBUG: ow_w1_parse.c:(113) Wait to peek at message
  DEBUG: ow_w1_parse.c:(121) Pre-parse header: 16 bytes len=48 type=3 seq=0|1 pid=0
  DEBUG: ow_w1_parse.c:(142) Netlink read -----------------
NLMSGHDR: len=48 type=3 (NLMSG_DONE) flags=0 seq=0|1 pid=0
CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=0|1 ack=1 len=12 flags=0
W1_NETLINK_MSG: type=6 (W1_LIST_MASTERS) len=0 id=0
W1_NETLINK_CMD: NULL w1c field
NULL data
  DEBUG: ow_w1_dispatch.c:(88) Netlink message directed to root W1 master
  DEBUG: ow_w1_dispatch.c:(126) Sending this packet to root bus
  DEBUG: ow_w1_dispatch.c:(173) Dispatch loop
  DEBUG: ow_w1_parse.c:(113) Wait to peek at message
  DEBUG: ow_w1_scan.c:(54) Netlink (w1) list all bus masters
  DEBUG: ow_w1_list.c:(64) W1 List 0 masters
  DEBUG: ow_w1_scan.c:(54) Netlink (w1) list all bus masters
  DEBUG: ow_w1_list.c:(64) W1 List 1 masters
  DEBUG: ow_w1_addremove.c:(55) Setup structure for w1_bus_master1
  DEBUG: ow_w1_addremove.c:(80) Request master be added: w1_bus_master1.
  DEBUG: ow_add_inflight.c:(26) Request master be added: w1_bus_master1
FUSE library version: 2.8.6
nullpath_ok: 0
unique: 1, opcode: INIT (26), nodeid: 0, insize: 56
INIT: 7.18
flags=0x0000047b
max_readahead=0x00020000
   INIT: 7.12
   flags=0x00000011
   max_readahead=0x00020000
   max_write=0x00020000
   unique: 1, success, outsize: 40

owfs mount point without EEPROM present but with owfs running

10.20.30.41:/tmp# ls /mnt
total 4.0K
drwxr-xr-x  5 root root 1.0K May 13 19:37 .
drwxr-xr-x 23 root root 1.0K May 13 11:33 ..
drwxr-xr-x  2 root root 1.0K Mar 31 19:35 jj
drwxr-xr-x  2 root root 1.0K Oct  9  2012 sda1
drwxr-xr-x  1 root root    8 May 13 19:40 w1

Output from owfs during last command
     unique: 2, opcode: GETATTR (3), nodeid: 1, insize: 56
     getattr /
        CALL: ow_fstat.c:(22) path=/
        CALL: ow_parsename.c:(98) path=[/]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/
      DEBUG: ow_parsename.c:(62) /
        unique: 2, success, outsize: 120
     unique: 3, opcode: GETXATTR (22), nodeid: 1, insize: 65
       unique: 3, error: -38 (Function not implemented), outsize: 16

10.20.30.41:/tmp# ls /mnt/w1
total 1.0K
drwxr-xr-x 1 root root    8 May 13 19:40 .
drwxr-xr-x 5 root root 1.0K May 13 19:37 ..
drwxr-xr-x 1 root root    8 May 13 19:40 bus.0
drwxr-xr-x 1 root root    8 May 13 19:40 bus.1
drwxr-xr-x 1 root root    8 May 13 19:40 settings
drwxr-xr-x 1 root root    8 May 13 19:40 statistics
drwxr-xr-x 1 root root   32 May 13 19:40 structure
drwxr-xr-x 1 root root    8 May 13 19:40 system
drwxr-xr-x 1 root root    8 May 13 19:40 uncached

Output from owfs during last command
     unique: 4, opcode: GETATTR (3), nodeid: 1, insize: 56
     getattr /
        CALL: ow_fstat.c:(22) path=/
        CALL: ow_parsename.c:(98) path=[/]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/
       DEBUG: ow_parsename.c:(62) /
        unique: 4, success, outsize: 120
     unique: 5, opcode: OPENDIR (27), nodeid: 1, insize: 48
        unique: 5, success, outsize: 32
     unique: 6, opcode: READDIR (28), nodeid: 1, insize: 80
     getdir[0]
        CALL: ow_parsename.c:(98) path=[/]
        CALL: owfs_callback.c:(177) GETDIR path=/
       DEBUG: ow_dir.c:(65) path=/
        CALL: ow_dir.c:(100) path=/
       DEBUG: ow_cache.c:(867) Looking for directory 00 00 00 00 00 00 00 00
       DEBUG: ow_cache.c:(880) Get from cache sn 00 00 00 00 00 00 00 00 pointer=0xb6fa0790 extension=1
       DEBUG: ow_cache.c:(909) Dir not found in cache
       DEBUG: ow_search.c:(32) Start of directory path=/ device=00 00 00 00 00 00 00 00
       DEBUG: ow_w1.c:(125) Sending w1 search (list devices) message
       DEBUG: ow_w1_send.c:(132) Netlink send -----------------
     NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=5 seq=1|1 pid=2921
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=1|1 ack=65537 len=16 flags=0
     W1_NETLINK_MSG: type=4 (W1_MASTER_CMD) len=4 id=1
     W1_NETLINK_CMD: cmd=2 (W1_CMD_SEARCH) len=0
     NULL data
       EBUG: ow_cache.c:(867) Looking for directory 00 00 00 00 00 00 00 00
       DEBUG: ow_cache.c:(880) Get from cache sn 00 00 00 00 00 00 00 00 pointer=0xb6fa0790 extension=0
       DEBUG: ow_cache.c:(909) Dir not found in cache
       DEBUG: ow_w1_parse.c:(121) Pre-parse header: 16 bytes len=52 type=3 seq=1|1 pid=0
       DEBUG: ow_w1_parse.c:(142) Netlink read -----------------
     NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=0 seq=1|1 pid=0
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=1|1 ack=0 len=16 flags=0
     W1_NETLINK_MSG: type=4 (W1_MASTER_CMD) len=4 id=1
     W1_NETLINK_CMD: cmd=2 (W1_CMD_SEARCH) len=0
     NULL data
       DEBUG: ow_w1_dispatch.c:(92) Netlink message directed to W1 bus master 1
       DEBUG: ow_w1_dispatch.c:(149) Sending this packet to w1_bus_master1
       DEBUG: ow_w1_dispatch.c:(173) Dispatch loop
       DEBUG: ow_w1_parse.c:(113) Wait to peek at message
       DEBUG: ow_w1_parse.c:(121) Pre-parse header: 16 bytes len=52 type=3 seq=1|1 pid=0
       DEBUG: ow_w1_parse.c:(142) Netlink read -----------------
     NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=0 seq=1|1 pid=0
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=1|1 ack=65537 len=16 flags=0
     W1_NETLINK_MSG: type=4 (W1_MASTER_CMD) len=4 id=1
     W1_NETLINK_CMD: cmd=2 (W1_CMD_SEARCH) len=0
     NULL data
       DEBUG: ow_w1_dispatch.c:(92) Netlink message directed to W1 bus master 1
       DEBUG: ow_w1_dispatch.c:(149) Sending this packet to w1_bus_master1
       DEBUG: ow_w1_dispatch.c:(173) Dispatch loop
       EBUG: ow_w1_parse.c:(113) Wait to peek at message
       DEBUG: ow_w1_send.c:(143) NETLINK sent seq=1
       DEBUG: ow_w1_parse.c:(225) Loop waiting for netlink piped message
       DEBUG: ow_w1_parse.c:(163) Pipe header: len=52 type=3 seq=1|1 pid=0
       DEBUG: ow_w1_parse.c:(191) Pipe read --------------------
     NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=0 seq=1|1 pid=0
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=1|1 ack=0 len=16 flags=0
     W1_NETLINK_MSG: type=4 (W1_MASTER_CMD) len=4 id=1
     W1_NETLINK_CMD: cmd=2 (W1_CMD_SEARCH) len=0
     NULL data
       DEBUG: ow_w1_parse.c:(245) About to call nrs_callback
       DEBUG: ow_w1_parse.c:(247) Called nrs_callback
       DEBUG: ow_w1_parse.c:(225) Loop waiting for netlink piped message
       DEBUG: ow_w1_parse.c:(163) Pipe header: len=52 type=3 seq=1|1 pid=0
       DEBUG: ow_w1_parse.c:(191) Pipe read --------------------
     NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=0 seq=1|1 pid=0
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=1|1 ack=65537 len=16 flags=0
     W1_NETLINK_MSG: type=4 (W1_MASTER_CMD) len=4 id=1
     W1_NETLINK_CMD: cmd=2 (W1_CMD_SEARCH) len=0
     NULL data
       DEBUG: ow_w1.c:(201) SN finished
        CALL: ow_parsename.c:(98) path=[/bus.1]
       DEBUG: ow_parsename.c:(62) /bus.1
        CALL: ow_parsename.c:(98) path=[/bus.0]
       DEBUG: ow_parsename.c:(62) /bus.0
        CALL: ow_parsename.c:(98) path=[/uncached]
       DEBUG: ow_parsename.c:(62) /uncached
        CALL: ow_parsename.c:(98) path=[/settings]
       DEBUG: ow_parsename.c:(62) /settings
        CALL: ow_parsename.c:(98) path=[/system]
       DEBUG: ow_parsename.c:(62) /system
        CALL: ow_parsename.c:(98) path=[/statistics]
       DEBUG: ow_parsename.c:(62) /statistics
        CALL: ow_parsename.c:(98) path=[/structure]
       DEBUG: ow_parsename.c:(62) /structure
       DEBUG: ow_dir.c:(195) ret=0
       DEBUG: ow_parsename.c:(62) /
        unique: 6, success, outsize: 320
     unique: 7, opcode: LOOKUP (1), nodeid: 1, insize: 46
     LOOKUP /bus.1
     getattr /bus.1
        CALL: ow_fstat.c:(22) path=/bus.1
        CALL: ow_parsename.c:(98) path=[/bus.1]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/bus.1
       DEBUG: ow_parsename.c:(62) /bus.1
        NODEID: 2
        unique: 7, success, outsize: 144
     unique: 8, opcode: LOOKUP (1), nodeid: 1, insize: 46
     LOOKUP /bus.0
     getattr /bus.0
        CALL: ow_fstat.c:(22) path=/bus.0
        CALL: ow_parsename.c:(98) path=[/bus.0]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/bus.0
       DEBUG: ow_parsename.c:(62) /bus.0
        NODEID: 3
        unique: 8, success, outsize: 144
     unique: 9, opcode: LOOKUP (1), nodeid: 1, insize: 49
     LOOKUP /uncached
     getattr /uncached
        CALL: ow_fstat.c:(22) path=/uncached
        CALL: ow_parsename.c:(98) path=[/uncached]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/uncached
       DEBUG: ow_parsename.c:(62) /uncached
        NODEID: 4
        unique: 9, success, outsize: 144
     unique: 10, opcode: LOOKUP (1), nodeid: 1, insize: 49
     LOOKUP /settings
     getattr /settings
        CALL: ow_fstat.c:(22) path=/settings
        CALL: ow_parsename.c:(98) path=[/settings]
        ALL: ow_fstat.c:(39) ATTRIBUTES path=/settings
       DEBUG: ow_parsename.c:(62) /settings
        NODEID: 5
        unique: 10, success, outsize: 144
     unique: 11, opcode: LOOKUP (1), nodeid: 1, insize: 47
     LOOKUP /system
     getattr /system
        CALL: ow_fstat.c:(22) path=/system
        CALL: ow_parsename.c:(98) path=[/system]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/system
       DEBUG: ow_parsename.c:(62) /system
        NODEID: 6
        unique: 11, success, outsize: 144
     unique: 12, opcode: LOOKUP (1), nodeid: 1, insize: 51
     LOOKUP /statistics
     getattr /statistics
        CALL: ow_fstat.c:(22) path=/statistics
        CALL: ow_parsename.c:(98) path=[/statistics]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/statistics
       DEBUG: ow_parsename.c:(62) /statistics
        NODEID: 7
        unique: 12, success, outsize: 144
     unique: 13, opcode: LOOKUP (1), nodeid: 1, insize: 50
     LOOKUP /structure
     getattr /structure
        CALL: ow_fstat.c:(22) path=/structure
        CALL: ow_parsename.c:(98) path=[/structure]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/structure
       DEBUG: ow_parsename.c:(62) /structure
        NODEID: 8
        unique: 13, success, outsize: 144
     unique: 14, opcode: GETATTR (3), nodeid: 1, insize: 56
     getattr /
        CALL: ow_fstat.c:(22) path=/
        CALL: ow_parsename.c:(98) path=[/]
       CALL: ow_fstat.c:(39) ATTRIBUTES path=/
       DEBUG: ow_parsename.c:(62) /
        unique: 14, success, outsize: 120
     unique: 15, opcode: READDIR (28), nodeid: 1, insize: 80
        unique: 15, success, outsize: 16
     unique: 16, opcode: RELEASEDIR (29), nodeid: 1, insize: 64
        unique: 16, success, outsize: 16

Attaching the 1-wire EEPROM
     output from owfs
       DEBUG: ow_w1_parse.c:(121) Pre-parse header: 16 bytes len=48 type=3 seq=0|4 pid=0
       DEBUG: ow_w1_parse.c:(142) Netlink read -----------------
     NLMSGHDR: len=48 type=3 (NLMSG_DONE) flags=0 seq=0|4 pid=0
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=0|4 ack=0 len=12 flags=0
     W1_NETLINK_MSG: type=0 (W1_SLAVE_ADD) len=0 id=1005157187
     W1_NETLINK_CMD: NULL w1c field
     NULL data
       DEBUG: ow_w1_dispatch.c:(88) Netlink message directed to root W1 master
       DEBUG: ow_w1_dispatch.c:(126) Sending this packet to root bus
       DEBUG: ow_w1_dispatch.c:(173) Dispatch loop
       DEBUG: ow_w1_parse.c:(113) Wait to peek at message
       DEBUG: ow_w1_scan.c:(69) Netlink (w1) Slave announcements (ignored)

ls on owfs mountpoint - **** ERROR *** - no output, hanges
10.20.30.41:/tmp# ls /mnt/w1

Output from owfs during last command
     unique: 17, opcode: GETATTR (3), nodeid: 1, insize: 56
     getattr /
        CALL: ow_fstat.c:(22) path=/
        CALL: ow_parsename.c:(98) path=[/]
        CALL: ow_fstat.c:(39) ATTRIBUTES path=/
       DEBUG: ow_parsename.c:(62) /
        unique: 17, success, outsize: 120
     unique: 18, opcode: OPENDIR (27), nodeid: 1, insize: 48
        unique: 18, success, outsize: 32
     unique: 19, opcode: READDIR (28), nodeid: 1, insize: 80
     getdir[0]
        CALL: ow_parsename.c:(98) path=[/]
        CALL: owfs_callback.c:(177) GETDIR path=/
       DEBUG: ow_dir.c:(65) path=/
        CALL: ow_dir.c:(100) path=/
       DEBUG: ow_cache.c:(867) Looking for directory 00 00 00 00 00 00 00 00
       DEBUG: ow_cache.c:(880) Get from cache sn 00 00 00 00 00 00 00 00 pointer=0xb6fa0790 extension=1
       DEBUG: ow_cache.c:(867) Looking for directory 00 00 00 00 00 00 00 00
      DEBUG: ow_cache.c:(880) Get from cache sn 00 00 00 00 00 00 00 00 pointer=0xb6fa0790 extension=0
      DEBUG: ow_cache.c:(909) Dir not found in cache
      DEBUG: ow_cache.c:(909) Dir not found in cache
      DEBUG: ow_search.c:(32) Start of directory path=/ device=00 00 00 00 00 00 00 00
       DEBUG: ow_w1.c:(125) Sending w1 search (list devices) message
      DEBUG: ow_w1_send.c:(132) Netlink send -----------------
     NLMSGHDR: len=52 type=3 (NLMSG_DONE) flags=5 seq=1|2 pid=2921
     CN_MSG: idx/val=3/1 (CN_W1_IDX) seq=1|2 ack=65538 len=16 flags=0
     W1_NETLINK_MSG: type=4 (W1_MASTER_CMD) len=4 id=1
     W1_NETLINK_CMD: cmd=2 (W1_CMD_SEARCH) len=0
     NULL data

From shawn.guo at linaro.org  Mon May 13 22:31:44 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 May 2013 10:31:44 +0800
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <CAOMZO5AeJUtyRC1BoAUiFihbjKtLMC2WBjaUXW0x+RE+QHYPnA@mail.gmail.com>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <20130304031716.GC30431@S2101-09.ap.freescale.net>
 <CAOMZO5Ai-msRVeAqQFiRhfAxkb2DMTYJvTcYihBhFt6GMCFwPQ@mail.gmail.com>
 <20130323135608.GG6281@S2101-09.ap.freescale.net>
 <CAOMZO5BvT3CUhPECTQZQq_Q2YEqMJzmXPL5pj-3Qmq35jnvm1A@mail.gmail.com>
 <20130324141758.GH6281@S2101-09.ap.freescale.net>
 <CAOMZO5AeJUtyRC1BoAUiFihbjKtLMC2WBjaUXW0x+RE+QHYPnA@mail.gmail.com>
Message-ID: <20130514023142.GA16250@S2101-09.ap.freescale.net>

On Mon, May 13, 2013 at 08:48:12AM -0300, Fabio Estevam wrote:
> Hi Shawn,
> 
> On Sun, Mar 24, 2013 at 11:18 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > Yes, when testing on next-20130322, it seems audio playback works.  But
> > since when the patch gets applied on my mxs/dt branch, it breaks audio
> > there, I still can not apply it.
> 
> Could you please apply the touchscreen patch now?

Have you tested it against v3.10-rc1?  The issue is still there in my
testing.

Shawn



From horms+renesas at verge.net.au  Mon May 13 22:39:28 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:39:28 +0900
Subject: [PATCH v2 0/3] 
Message-ID: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>

Hi,

this short series enables the on-board ethernet
of the r8a7790 SoC for on lager board.

It is based on the renesas-next-20130513 tag of my renesas tree.

Dependencies noted in individual patches.

Simon Horman (3):
  ARM: shmobile: r8a7790: add Ether support
  ARM: shmobile: lager: enable Ether
  ARM: shmobile: lager: enable nfsroot in DTS

 arch/arm/boot/dts/r8a7790-lager.dts           |  2 +-
 arch/arm/mach-shmobile/board-lager.c          | 25 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a7790.c        |  4 ++++
 arch/arm/mach-shmobile/include/mach/r8a7790.h |  3 +++
 arch/arm/mach-shmobile/setup-r8a7790.c        | 15 +++++++++++++++
 5 files changed, 48 insertions(+), 1 deletion(-)

-- 
1.8.2.1



From horms+renesas at verge.net.au  Mon May 13 22:39:31 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:39:31 +0900
Subject: [PATCH v2 3/3] ARM: shmobile: lager: enable nfsroot in DTS
In-Reply-To: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
References: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368499171-22427-4-git-send-email-horms+renesas@verge.net.au>

Now that Ether support has been added to the lager board
it is possible to use nfsroot. This configuration is
in line with that of other shmobile boards.

Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has a run-time dependency on "ARM: shmobile: lager: enable Ether"

v2
* Split out as a new patch from "ARM: shmobile: lager: enable Ether"
---
 arch/arm/boot/dts/r8a7790-lager.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 09a84fc..b2f61f0 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -16,7 +16,7 @@
 	compatible = "renesas,lager", "renesas,r8a7790";
 
 	chosen {
-		bootargs = "console=ttySC6,115200 ignore_loglevel";
+		bootargs = "console=ttySC6,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
 	};
 
 	memory at 40000000 {
-- 
1.8.2.1



From horms+renesas at verge.net.au  Mon May 13 22:39:30 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:39:30 +0900
Subject: [PATCH v2 2/3] ARM: shmobile: lager: enable Ether
In-Reply-To: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
References: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368499171-22427-3-git-send-email-horms+renesas@verge.net.au>

Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has a build-time dependency on "sh_eth: add support for gpio reset".
This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".

v2
* As suggested by Laurent Pinchart
  - Do not manipilate sh_eth reset GPIO directly,
    rather, do so through newly proposed support for this in
    the sh_eth driver.
* A suggested by Sergei Shtylyov
  - Move DTS portion into a separate patch
---
 arch/arm/mach-shmobile/board-lager.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 6a1ba38..c06f0da 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
@@ -52,6 +53,17 @@ static struct gpio_led_platform_data lager_leds_pdata = {
 	.num_leds	= ARRAY_SIZE(lager_leds),
 };
 
+/* Ether */
+static struct sh_eth_plat_data ether_platdata = {
+	.phy			= 0x1,
+	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
+	.register_type		= SH_ETH_REG_FAST_RCAR,
+	.phy_interface		= PHY_INTERFACE_MODE_RMII,
+	.ether_link_active_low	= 1,
+	.needs_gpio_reset	= 1,
+	.reset_gpio		= RCAR_GP_PIN(5, 31),
+};
+
 static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
@@ -59,6 +71,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* SCIF1 (CN20: DEBUG SERIAL1) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
 				  "scif1_data", "scif1"),
+	/* Ether */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_link", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_magic", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_mdio", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "eth_rmii", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
+				  "intc_irq0", "intc"),
 };
 
 static void __init lager_add_standard_devices(void)
@@ -73,6 +96,8 @@ static void __init lager_add_standard_devices(void)
 	platform_device_register_data(&platform_bus, "leds-gpio", -1,
 				      &lager_leds_pdata,
 				      sizeof(lager_leds_pdata));
+
+	r8a7790_add_ether_device(&ether_platdata);
 }
 
 static const char *lager_boards_compat_dt[] __initdata = {
-- 
1.8.2.1



From horms+renesas at verge.net.au  Mon May 13 22:39:29 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:39:29 +0900
Subject: [PATCH v2 1/3] ARM: shmobile: r8a7790: add Ether support
In-Reply-To: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
References: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368499171-22427-2-git-send-email-horms+renesas@verge.net.au>

Add Ether clock and platform device for R8A7779 SoC; add a function to
register this device with board-specific platform data.

Based on a similar change for the r8a7779 by Sergei Shtylyov.

Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

This patch has a run-time dependency on "sh_eth: add support for r8a7790 SoC".

v2
* Do not add MSTP812, EtherAVB. It is not used.
* As suggested by Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
  - Move Ethernet element of MSTP enum to a separate line
  - Move declaration of r8a7790_add_ether_device() to immediately
    after that of r8a7790_add_standard_devices()
  - Add __initdata annotation to ether_resource.
---
 arch/arm/mach-shmobile/clock-r8a7790.c        |  4 ++++
 arch/arm/mach-shmobile/include/mach/r8a7790.h |  3 +++
 arch/arm/mach-shmobile/setup-r8a7790.c        | 15 +++++++++++++++
 3 files changed, 22 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index b393592..b21ff6b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -50,6 +50,7 @@
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
 
 #define MODEMR		0xE6160060
 #define SDCKCR		0xE6150074
@@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+	MSTP813,
 	MSTP721, MSTP720,
 	MSTP304,
 	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@@ -187,6 +189,7 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
 	[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
@@ -249,6 +252,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
 	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
 	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
+	CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP813]),
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e6..89e4f70 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -1,7 +1,10 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
 
+#include <linux/sh_eth.h>
+
 void r8a7790_add_standard_devices(void);
+void r8a7790_add_ether_device(struct sh_eth_plat_data *pdata);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_timer_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index eeef5f6..c56deab 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -30,6 +30,21 @@
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
 
+
+/* Ether */
+static __initdata struct resource ether_resources[] = {
+	DEFINE_RES_MEM(0xee700000, 0x400),
+	DEFINE_RES_IRQ(gic_spi(162)), /* IRQ0 */
+};
+
+void __init r8a7790_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+	platform_device_register_resndata(&platform_bus, "sh-eth", -1,
+					  ether_resources,
+					  ARRAY_SIZE(ether_resources),
+					  pdata, sizeof(*pdata));
+}
+
 static const struct resource pfc_resources[] = {
 	DEFINE_RES_MEM(0xe6060000, 0x250),
 };
-- 
1.8.2.1



From horms at verge.net.au  Mon May 13 22:40:37 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:40:37 +0900
Subject: [PATCH 2/3] ARM: shmobile: r8a7790: Configure R-Car GPIO for
 IRQ_TYPE_EDGE_BOTH
In-Reply-To: <2257564.fgMO2c8G9k@avalon>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-3-git-send-email-horms+renesas@verge.net.au>
 <2257564.fgMO2c8G9k@avalon>
Message-ID: <20130514024034.GA20239@verge.net.au>

On Tue, May 14, 2013 at 12:33:42AM +0200, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Monday 13 May 2013 17:53:52 Simon Horman wrote:
> > "gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
> > driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
> > not universal for all SoCs a flag, has_both_edge_trigger, has been
> > added to the platform data of the driver to allow this feature to be
> > enabled.
> 
> What about moving this information to a platform ID table in the gpio-rcar 
> driver ?

Magnus, do you have an opinion on this?

> > As the r8a7790 SoC hardware supports this feature enable it.
> > 
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > 
> > ---
> > 
> > This patch has a build-time dependency on
> > "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH".
> > ---
> >  arch/arm/mach-shmobile/setup-r8a7790.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c
> > b/arch/arm/mach-shmobile/setup-r8a7790.c index eeef5f6..b461d93 100644
> > --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> > +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> > @@ -45,6 +45,7 @@ static struct gpio_rcar_config
> > r8a7790_gpio##idx##_platform_data = {	\ .irq_base	= 0,						
> \
> >  	.number_of_pins	= 32,						\
> >  	.pctl_name	= "pfc-r8a7790",				\
> > +	.has_both_edge_trigger = 1,					\
> >  };									\
> > 
> >  R8A7790_GPIO(0);
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From horms at verge.net.au  Mon May 13 22:44:44 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:44:44 +0900
Subject: [PATCH 1/3] gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
In-Reply-To: <CANqRtoQ2gLVRz-a1PoQeuy_=XVKMR8x+47NDT9FFQWdRu17c7A@mail.gmail.com>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-2-git-send-email-horms+renesas@verge.net.au>
 <CANqRtoQ2gLVRz-a1PoQeuy_=XVKMR8x+47NDT9FFQWdRu17c7A@mail.gmail.com>
Message-ID: <20130514024443.GB20239@verge.net.au>

On Mon, May 13, 2013 at 07:14:41PM +0900, Magnus Damm wrote:
> On Mon, May 13, 2013 at 5:53 PM, Simon Horman
> <horms+renesas at verge.net.au> wrote:
> > As hardware support for this feature is not universal for all SoCs a flag,
> > has_both_edge_trigger, has been added to the platform data of the driver to
> > allow this feature to be enabled.
> >
> > The motivation for this is to allow use of the gpio-keys driver on the
> > lager board which is based on the r8a7790 SoC. This patch has been lightly
> > exercised using that driver on that board.
> >
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > ---
> >  drivers/gpio/gpio-rcar.c                | 27 ++++++++++++++++++++++-----
> >  include/linux/platform_data/gpio-rcar.h |  1 +
> >  2 files changed, 23 insertions(+), 5 deletions(-)
> 
> Thanks for the patch, Simon!
> 
> > diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
> > index 0f3d647..33d8f6a 100644
> > --- a/drivers/gpio/gpio-rcar.c
> > +++ b/drivers/gpio/gpio-rcar.c
> > @@ -49,6 +49,7 @@ struct gpio_rcar_priv {
> >  #define POSNEG 0x20
> >  #define EDGLEVEL 0x24
> >  #define FILONOFF 0x28
> > +#define BOTHEDGE 0x4c
> >
> >  static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
> >  {
> > @@ -111,6 +113,11 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
> >         /* Select "Interrupt Input Mode" in IOINTSEL */
> >         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
> >
> > +       if (p->config.has_both_edge_trigger && !level_trigger) {
> > +               /* Select one edge or both edges in BOTHEDGE */
> > +               gpio_rcar_modify_bit(p, IOINTSEL, hwirq, both);
> > +       }
> > +
> >         /* Write INTCLR in case of edge trigger */
> >         if (!level_trigger)
> >                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
> 
> In your hunk above I suspect you want to setup the BOTHEDGE register
> instead of IOINTSEL.

Thanks, I will fix that.

> Also, I wonder how BOTHEDGE should be set in the case of level
> trigger. Say that the user first selects edge trigger and then
> reconfigures to level, then you probably want to make sure the
> BOTHEDGE register is cleared.
> 
> So may want to do something like this (untested):
> 
>        if (p->config.has_both_edge_trigger) {
>                /* Select one edge or both edges in BOTHEDGE */
>                gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
>        }

Sure, if you think so.

> Also, please double check that the register access sequences in the
> documentation are still kept, please see "6.7.1 Setting Edge-Sensitive
> Interrupt Input Mode" in the H2 data sheet. It looks like you want to
> move this setting so it happens before IOINTSEL.

Thanks, I will fix that.


From inki.dae at samsung.com  Mon May 13 22:52:20 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 14 May 2013 11:52:20 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
Message-ID: <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>



> -----Original Message-----
> From: Rob Clark [mailto:robdclark at gmail.com]
> Sent: Tuesday, May 14, 2013 2:58 AM
> To: Inki Dae
> Cc: linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham; YoungJun
> Cho; linux-arm-kernel at lists.infradead.org; linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Mon, May 13, 2013 at 1:18 PM, Inki Dae <inki.dae at samsung.com> wrote:
> >
> >
> > 2013/5/13 Rob Clark <robdclark at gmail.com>
> >>
> >> On Mon, May 13, 2013 at 8:21 AM, Inki Dae <inki.dae at samsung.com> wrote:
> >> >
> >> >> In that case you still wouldn't give userspace control over the
> fences.
> >> >> I
> >> >> don't see any way that can end well.
> >> >> What if userspace never signals? What if userspace gets killed by
> oom
> >> >> killer. Who keeps track of that?
> >> >>
> >> >
> >> > In all cases, all kernel resources to user fence will be released by
> >> > kernel
> >> > once the fence is timed out: never signaling and process killing by
> oom
> >> > killer makes the fence timed out. And if we use mmap mechanism you
> >> > mentioned
> >> > before, I think user resource could also be freed properly.
> >>
> >>
> >> I tend to agree w/ Maarten here.. there is no good reason for
> >> userspace to be *signaling* fences.  The exception might be some blob
> >> gpu drivers which don't have enough knowledge in the kernel to figure
> >> out what to do.  (In which case you can add driver private ioctls for
> >> that.. still not the right thing to do but at least you don't make a
> >> public API out of it.)
> >>
> >
> > Please do not care whether those are generic or not. Let's see the
> following
> > three things. First, it's cache operation. As you know, ARM SoC has ACP
> > (Accelerator Coherency Port) and can be connected to DMA engine or
> similar
> > devices. And this port is used for cache coherency between CPU cache and
> DMA
> > device. However, most devices on ARM based embedded systems don't use
> the
> > ACP port. So they need proper cache operation before and after of DMA or
> CPU
> > access in case of using cachable mapping. Actually, I see many Linux
> based
> > platforms call cache control interfaces directly for that. I think the
> > reason, they do so, is that kernel isn't aware of when and how CPU
> accessed
> > memory.
> 
> I think we had kicked around the idea of giving dmabuf's a
> prepare/finish ioctl quite some time back.  This is probably something
> that should be at least a bit decoupled from fences.  (Possibly
> 'prepare' waits for dma access to complete, but not the other way
> around.)
> 
> And I did implement in omapdrm support for simulating coherency via
> page fault-in / shoot-down..  It is one option that makes it
> completely transparent to userspace, although there is some
> performance const, so I suppose it depends a bit on your use-case.
> 
> > And second, user process has to do so many things in case of using
> shared
> > memory with DMA device. User process should understand how DMA device is
> > operated and when interfaces for controling the DMA device are called.
> Such
> > things would make user application so complicated.
> >
> > And third, it's performance optimization to multimedia and graphics
> devices.
> > As I mentioned already, we should consider sequential processing for
> buffer
> > sharing between CPU and DMA device. This means that CPU should stay with
> > idle until DMA device is completed and vise versa.
> >
> > That is why I proposed such user interfaces. Of course, these interfaces
> > might be so ugly yet: for this, Maarten pointed already out and I agree
> with
> > him. But there must be another better way. Aren't you think we need
> similar
> > thing? With such interfaces, cache control and buffer synchronization
> can be
> > performed in kernel level. Moreover, user applization doesn't need to
> > consider DMA device controlling anymore. Therefore, one thread can
> access a
> > shared buffer and the other can control DMA device with the shared
> buffer in
> > parallel. We can really make the best use of CPU and DMA idle time. In
> other
> > words, we can really make the best use of multi tasking OS, Linux.
> >
> > So could you please tell me about that there is any reason we don't use
> > public API for it? I think we can add and use public API if NECESSARY.
> 
> well, for cache management, I think it is a better idea.. I didn't
> really catch that this was the motivation from the initial patch, but
> maybe I read it too quickly.  But cache can be decoupled from
> synchronization, because CPU access is not asynchronous.  For
> userspace/CPU access to buffer, you should:
> 
>   1) wait for buffer
>   2) prepare-access
>   3)  ... do whatever cpu access to buffer ...
>   4) finish-access
>   5) submit buffer for new dma-operation
> 


For data flow from CPU to DMA device,
1) wait for buffer
2) prepare-access (dma_buf_begin_cpu_access)
3) cpu access to buffer


For data flow from DMA device to CPU
1) wait for buffer
2) finish-access (dma_buf_end _cpu_access)
3) dma access to buffer

1) and 2) are coupled with one function: we have implemented
fence_helper_commit_reserve() for it.

Cache control(cache clean or cache invalidate) is performed properly
checking previous access type and current access type.
And the below is actual codes for it,

static void fence_helper_cache_ops(struct fence_helper *fh)
{
	struct seqno_fence_dmabuf *sfd;

	list_for_each_entry(sfd, &fh->sf.sync_buf_list, list) {
		struct dma_buf *dmabuf = sfd->sync_buf;

		if (WARN_ON(!dmabuf))
			continue;

		/* first time access. */
		if (!dmabuf->access_type)
			goto out;

		if (dmabuf->access_type == DMA_BUF_ACCESS_WRITE &&
				((fh->type == (DMA_BUF_ACCESS_READ |
						DMA_BUF_ACCESS_DMA)) ||
				(fh->type == (DMA_BUF_ACCESS_WRITE |
					     DMA_BUF_ACCESS_DMA))))
			/* cache clean */
			dma_buf_end_cpu_access(dmabuf, 0, dmabuf->size,
						DMA_TO_DEVICE);
		else if (dmabuf->access_type == (DMA_BUF_ACCESS_WRITE |
						DMA_BUF_ACCESS_DMA) &&
				(fh->type == DMA_BUF_ACCESS_READ))
			/* cache invalidate */
			dma_buf_begin_cpu_access(dmabuf, 0, dmabuf->size,
							DMA_FROM_DEVICE);

out:
		/* Update access type to new one. */
		dmabuf->access_type = fh->type;
	}
}

The above function is called after wait for buffer.
Thus, we can check who (CPU or DMA) and how (READ or WRITE) accessed and
accesses buffer with this approach. In other words, now kernel is aware of
buffer access by CPU also.


Thanks,
Inki Dae

> I suppose you could combine the syscall for #1 and #2.. not sure if
> that is a good idea or not.  But you don't need to.  And there is
> never really any need for userspace to signal a fence.
> 
> BR,
> -R
> 
> > Thanks,
> > Inki Dae
> >
> >>
> >> BR,
> >> -R
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel at lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
> >



From horms at verge.net.au  Mon May 13 22:59:42 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 11:59:42 +0900
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <9256981.LFpgU8cctr@avalon>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
 <9256981.LFpgU8cctr@avalon>
Message-ID: <20130514025941.GC20239@verge.net.au>

On Tue, May 14, 2013 at 12:35:20AM +0200, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.
> 
> On Monday 13 May 2013 17:53:53 Simon Horman wrote:
> > The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
> > This patch allows access to those pins as KEYS 1 - 4 using
> > gpio-keys.
> > 
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > 
> > ---
> > 
> > This patch has run time dependencies on
> > 1. "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH"
> > 2. "ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH"
> > 
> > Without those dependencies satisfied the gpio-keys driver will
> > fail to be initialise itself. The boot should be otherwise successful
> > and the board otherwise functional.
> > ---
> >  arch/arm/mach-shmobile/board-lager.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/arch/arm/mach-shmobile/board-lager.c
> > b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..4d1b42b 100644
> > --- a/arch/arm/mach-shmobile/board-lager.c
> > +++ b/arch/arm/mach-shmobile/board-lager.c
> > @@ -18,7 +18,10 @@
> >   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> > USA */
> > 
> > +#include <linux/gpio.h>
> > +#include <linux/gpio_keys.h>
> >  #include <linux/interrupt.h>
> > +#include <linux/input.h>
> 
> My dictionary lists input before interrupt :-)

Thanks, I will fix that.

> >  #include <linux/irqchip.h>
> >  #include <linux/kernel.h>
> >  #include <linux/leds.h>
> > @@ -52,6 +55,22 @@ static struct gpio_led_platform_data lager_leds_pdata = {
> > .num_leds	= ARRAY_SIZE(lager_leds),
> >  };
> > 
> > +/* GPIO KEY */
> > +#define GPIO_KEY(c, g, d, ...) \
> > +	{ .code = c, .gpio = g, .desc = d, .active_low = 1 }
> > +
> > +static struct gpio_keys_button gpio_buttons[] = {
> > +	GPIO_KEY(KEY_4,		RCAR_GP_PIN(1, 28),	"SW2-pin4"),
> > +	GPIO_KEY(KEY_3,		RCAR_GP_PIN(1, 26),	"SW2-pin3"),
> > +	GPIO_KEY(KEY_2,		RCAR_GP_PIN(1, 24),	"SW2-pin2"),
> > +	GPIO_KEY(KEY_1,		RCAR_GP_PIN(1, 14),	"SW2-pin1"),
> > +};
> > +
> > +static struct gpio_keys_platform_data lager_keys_pdata = {
> > +	.buttons	= gpio_buttons,
> > +	.nbuttons	= ARRAY_SIZE(gpio_buttons),
> > +};
> > +
> 
> Could you please also update the lager dts file ?

I wonder if in that case we can remove the C code above.
And probably the C code for the GPIO leds too.

Magnus, could you clarify how you would like
C-code and DTS to look on the lager board?

> >  static const struct pinctrl_map lager_pinctrl_map[] = {
> >  	/* SCIF0 (CN19: DEBUG SERIAL0) */
> >  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
> > @@ -73,6 +92,9 @@ static void __init lager_add_standard_devices(void)
> >  	platform_device_register_data(&platform_bus, "leds-gpio", -1,
> >  				      &lager_leds_pdata,
> >  				      sizeof(lager_leds_pdata));
> > +	platform_device_register_data(&platform_bus, "gpio-keys", -1,
> > +				      &lager_keys_pdata,
> > +				      sizeof(lager_keys_pdata));
> >  }
> > 
> >  static const char *lager_boards_compat_dt[] __initdata = {


From tushar.behera at linaro.org  Mon May 13 23:07:53 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Tue, 14 May 2013 08:37:53 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <87sj1qzaov.fsf@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org>
Message-ID: <5191AA89.6010901@linaro.org>

On 05/14/2013 05:36 AM, Kevin Hilman wrote:
> Tushar Behera <tushar.behera at linaro.org> writes:
> 
>> It updates following drivers for EXYNOS based DT platform.
>>
>> * S5M8767 driver
>> * MAX8997 driver
>> * MMC SDHCI driver
>>
>> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
> 
> I tested this using v3.10-rc1 on Arndale, but still don't get any
> support for the wired network.  Do you know if this is a Kconfig issue,
> or a missing driver?
> 
> I suspect it may be related to the various "unable to find transceiver
> of type USB2 PHY" messages I'm seeing?
> 

Yes, right. The missing USB-PHY components are one of the issues (they
were there in linux-next when I last tested).

Also, on Arndale board, we need to reset the USB hub during EHCI
initialization (a couple of those patches are required, which I am not
sure if we would be able to upstream).

I am collecting a minimal set of patches that would enable USB and wired
network on Arndale with 3.10-rc1 kernel. Once done, I will let you know.

> Thanks,
> 
> Kevin
> 

Thanks for testing.


-- 
Tushar Behera


From shawn.guo at linaro.org  Mon May 13 23:30:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 May 2013 11:30:51 +0800
Subject: [PATCH 3/4] ARM: mxs: remove the .map_io declaration
In-Reply-To: <1368440169-29088-4-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368440169-29088-4-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130514033050.GB16250@S2101-09.ap.freescale.net>

On Mon, May 13, 2013 at 12:16:08PM +0200, Maxime Ripard wrote:
> Now that the ARM core code calls debug_ll_io_init, we can remove it from
> the machine_desc declaration.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> ---
>  arch/arm/mach-mxs/mach-mxs.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index 5b62b64..d67ecc1 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -434,7 +434,6 @@ static const char *mxs_dt_compat[] __initdata = {
>  };
>  
>  DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
> -	.map_io		= debug_ll_io_init,
>  	.init_irq	= irqchip_init,
>  	.handle_irq	= icoll_handle_irq,
>  	.init_time	= mxs_timer_init,
> -- 
> 1.8.1.2
> 



From marex at denx.de  Mon May 13 23:30:48 2013
From: marex at denx.de (Marek Vasut)
Date: Tue, 14 May 2013 05:30:48 +0200
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <20130514023142.GA16250@S2101-09.ap.freescale.net>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <CAOMZO5AeJUtyRC1BoAUiFihbjKtLMC2WBjaUXW0x+RE+QHYPnA@mail.gmail.com>
 <20130514023142.GA16250@S2101-09.ap.freescale.net>
Message-ID: <201305140530.48910.marex@denx.de>

Dear Shawn Guo,

> On Mon, May 13, 2013 at 08:48:12AM -0300, Fabio Estevam wrote:
> > Hi Shawn,
> > 
> > On Sun, Mar 24, 2013 at 11:18 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > > Yes, when testing on next-20130322, it seems audio playback works.  But
> > > since when the patch gets applied on my mxs/dt branch, it breaks audio
> > > there, I still can not apply it.
> > 
> > Could you please apply the touchscreen patch now?
> 
> Have you tested it against v3.10-rc1?  The issue is still there in my
> testing.

Are the block handling touchscreen (lradc) and the block handling audio 
(sgtl5000+ssi) not two completely separate blocks? How can one influence the 
other?

There is a possibility that there's some problem with broken clock bindings or 
clock structure maybe? That's the only thing that comes to mind that might cause 
it.

Best regards,
Marek Vasut


From shc_work at mail.ru  Mon May 13 13:07:34 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Mon, 13 May 2013 21:07:34 +0400
Subject: [PATCH 12/15] ARM: clps711x: edb7211: Add support for I2C
In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
References: <1368464857-5038-1-git-send-email-shc_work@mail.ru>
Message-ID: <1368464857-5038-15-git-send-email-shc_work@mail.ru>


Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/board-edb7211.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index db804b4..970f4e1 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -12,6 +12,7 @@
 #include <linux/delay.h>
 #include <linux/memblock.h>
 #include <linux/types.h>
+#include <linux/i2c-gpio.h>
 #include <linux/interrupt.h>
 #include <linux/backlight.h>
 #include <linux/platform_device.h>
@@ -37,6 +38,9 @@
 #define EDB7211_LCDEN		CLPS711X_GPIO(3, 2)
 #define EDB7211_LCDBL		CLPS711X_GPIO(3, 3)
 
+#define EDB7211_I2C_SDA		CLPS711X_GPIO(3, 4)
+#define EDB7211_I2C_SCL		CLPS711X_GPIO(3, 5)
+
 #define EDB7211_FLASH0_BASE	(CS0_PHYS_BASE)
 #define EDB7211_FLASH1_BASE	(CS1_PHYS_BASE)
 
@@ -46,6 +50,12 @@
 /* The extra 8 lines of the keyboard matrix */
 #define EDB7211_EXTKBD_BASE	(CS3_PHYS_BASE)
 
+static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
+	.sda_pin	= EDB7211_I2C_SDA,
+	.scl_pin	= EDB7211_I2C_SCL,
+	.scl_is_output_only = 1,
+};
+
 static struct resource edb7211_cs8900_resource[] __initdata = {
 	DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
 	DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
@@ -173,6 +183,9 @@ static void __init edb7211_init_late(void)
 	platform_device_register_simple("video-clps711x", 0, NULL, 0);
 	platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
 					ARRAY_SIZE(edb7211_cs8900_resource));
+	platform_device_register_data(&platform_bus, "i2c-gpio", 0,
+				      &edb7211_i2c_pdata,
+				      sizeof(edb7211_i2c_pdata));
 }
 
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
-- 
1.8.1.5



From andrew at lunn.ch  Tue May 14 01:17:12 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 14 May 2013 07:17:12 +0200
Subject: [PATCH] mv643xx_eth: fix NAPI weight being > 64
Message-ID: <1368508632-13742-1-git-send-email-andrew@lunn.ch>

3.10-rc1 issues the following warning:

netif_napi_add() called with weight 128 on device eth%d

This patch reduce the weight to 64.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index d0afeea..6b5471f 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2745,7 +2745,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
 	INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
 
-	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
+	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
 
 	init_timer(&mp->rx_oom);
 	mp->rx_oom.data = (unsigned long)mp;
-- 
1.7.10.4



From gmbnomis at gmail.com  Tue May 14 01:37:06 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 14 May 2013 07:37:06 +0200
Subject: [PATCH V2 07/10] ARM: mvebu: Use standard MMC binding for all
 users of mvsdio
In-Reply-To: <20130513230918.GG31290@titan.lakedaemon.net>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-8-git-send-email-gmbnomis@gmail.com>
 <20130513230918.GG31290@titan.lakedaemon.net>
Message-ID: <20130514053706.GA29922@schnuecks.de>

Hi Jason,

On Mon, May 13, 2013 at 07:09:18PM -0400, Jason Cooper wrote:
> On Mon, May 13, 2013 at 11:18:58PM +0200, Simon Baatz wrote:
> > In order to prepare the switch to the standard MMC device tree parser
> > for mvsdio, adapt all current uses of mvsdio in the dts files to the
> > standard format.
> > 
> > Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> > ---
> ...
> > diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
> > index 7588241..bf3a58c 100644
> > --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
> > +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
> > @@ -136,7 +136,7 @@
> >  			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
> >  			pinctrl-names = "default";
> >  			status = "okay";
> > -			cd-gpios = <&gpio1 15 0>;
> > +			cd-gpios = <&gpio1 15 1>;
> 
> Is this a bugfix that should be backported?

No, that should not be necessary. The old code implicitly used "1"
here regardless of the actual flag value.

- Simon


From tushar.behera at linaro.org  Tue May 14 01:40:35 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Tue, 14 May 2013 11:10:35 +0530
Subject: [GIT PULL] Late Exynos stuff for v3.10
In-Reply-To: <046301ce4d15$ac1592b0$0440b810$%kim@samsung.com>
References: <5176B499.1000208@samsung.com> <51770697.7080504@samsung.com>
 <20130424000638.GA9067@quad.lixom.net> <51794E10.1010205@samsung.com>
 <CAOesGMjA5_XUXMcCL3roZiLC1S=ypMoVHn2tF7bzUuKr+eLw2A@mail.gmail.com>
 <046301ce4d15$ac1592b0$0440b810$%kim@samsung.com>
Message-ID: <5191CE53.5050902@linaro.org>

>> Refresh my memory here, what was the reason for dropping the USB DTS
>> updates? (Yes, I am aware it might because I asked you not to send
>> them in but I don't remember :-).
>>
> Hmm...let me see, yeah, the USB DTS updates dropped because of late
> pull-request stuff as you concerned.
> http://www.spinics.net/lists/arm-kernel/msg240105.html
> 
> Since I didn't want to make a noise at that time, so I dropped for v3.10, it
> has been included in my tree for some time though.
> 

Will it be possible to queue them up for one of the RC releases? They
are only DTS entries, the drivers have already been merged.

-- 
Tushar Behera


From Baohua.Song at csr.com  Tue May 14 01:49:09 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Tue, 14 May 2013 13:49:09 +0800
Subject: [PATCH] mmc: sdhci-sirf: let device core setup the default pin
 configuration
Message-ID: <1368510549-7230-1-git-send-email-Baohua.Song@csr.com>

With device core now able to setup the default pin configuration, the call
to devm_pinctrl_get_select_default can be removed. And the pin configuration
code based on the deprecated Samsung specific gpio bindings is also removed.

CC: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/mmc/host/sdhci-sirf.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 09805af..04c81cf 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -46,15 +46,8 @@ static int sdhci_sirf_probe(struct platform_device *pdev)
 	struct sdhci_host *host;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct sdhci_sirf_priv *priv;
-	struct pinctrl *pinctrl;
 	int ret;
 
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl)) {
-		dev_err(&pdev->dev, "unable to get pinmux");
-		return PTR_ERR(pinctrl);
-	}
-
 	priv = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_sirf_priv),
 		GFP_KERNEL);
 	if (!priv) {
-- 
1.7.4.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From swarren at wwwdotorg.org  Tue May 14 01:56:16 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 May 2013 23:56:16 -0600
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
Message-ID: <5191D200.3040604@wwwdotorg.org>

On 04/12/2013 03:18 AM, Jongsung Kim wrote:
> The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all
> earlier ones have 16-byte FIFOs. This patch suggests a way to set the
> FIFO-size correctly & flexibly by using a
> function(vendor_data::get_fifosize) rather than using the
> vendor_data::fifosize variable. The function takes the UARTPeriphID, and
> returns the correct size.

This change (now part of 3.10-rc1) breaks the serial port on the BCM2835
ARM SoC (part of the Raspberry Pi). Sorry for not noticing this earlier;
a combination of my vacation and laziness I guess.

For reference, the AMBA periphid of the UART device there is 0x00341011.
The nibble "3" is the revision being tested in:

> +static unsigned int get_fifosize_arm(unsigned int periphid)
> +{
> +	unsigned int rev = (periphid >> 20) & 0xf;
> +	return rev < 3 ? 16 : 32;
> +}

Should that be <= not <, or is there just something more wrong in the
patch or bcm2835 HW? I wonder how r1p5 maps to 3 in the test above.


From plagnioj at jcrosoft.com  Tue May 14 01:52:56 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 May 2013 07:52:56 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for
 some SoC
In-Reply-To: <51918C23.7040106@yahoo.es>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
 <51918C23.7040106@yahoo.es>
Message-ID: <20130514055256.GD22508@game.jcrosoft.org>

On 08:58 Tue 14 May     , Hein Tibosch wrote:
> On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> >
> >> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
> >> introduces clear-on-write on ISR register. This behavior is not always
> >> implemented when using Cadence MACB/GEM and is breaking other platforms.
> >> We are using a new Device Tree compatibility string and a capability
> >> property to actually activate this clear-on-write behavior on ISR.
> >>
> >> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
> >> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> > can we detect it via the IP?
> 
> This was my first proposal, have it based on the value of MACB's
> register 'MID' (offset 0x00fc, lower 16 bits).
> On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
> 
> So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
> equals to 0x00000119?
so no it will not work

as the gem on sama5 is 00020119

so version 0x119 too

nico 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Best Regards,
J.
> 
> >> ---
> >> Documentation/devicetree/bindings/net/macb.txt |  2 ++
> >> drivers/net/ethernet/cadence/macb.c            | 15 +++++++++++++--
> >> drivers/net/ethernet/cadence/macb.h            |  5 +++++
> >> 3 files changed, 20 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
> >> index 44afa0e..13ec4f6 100644
> >>
> >> <snip>
> >>
> >> @@ -1474,6 +1476,10 @@ static const struct of_device_id macb_dt_ids[] = {
> >> 	{ .compatible = "cdns,macb" },
> >> 	{ .compatible = "cdns,pc302-gem" },
> >> 	{ .compatible = "cdns,gem" },
> >> +	{
> >> +		.compatible = "cdns,zynq-7000-gem",
> >> +		.data = (void *)MACB_CAPS_ISR_CLEAR_ON_WRITE,
> >> +	},
> >> 	{ /* sentinel */ }
> >> };
> >> MODULE_DEVICE_TABLE(of, macb_dt_ids);
> >> @@ -1484,6 +1490,7 @@ static int __init macb_probe(struct platform_device *pdev)
> >> 	struct macb_platform_data *pdata;
> >> 	struct resource *regs;
> >> 	struct net_device *dev;
> >> +	const struct of_device_id *dev_id;
> >> 	struct macb *bp;
> >> 	struct phy_device *phydev;
> >> 	u32 config;
> >> @@ -1558,6 +1565,10 @@ static int __init macb_probe(struct platform_device *pdev)
> >>
> >> 	dev->base_addr = regs->start;
> >>
> >> +	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
> As avr32 doesn't yet define CONFIG_OF:
>     macb.c:1601: error:  'macb_dt_ids' undeclared
> 
> Hein


From hdoyu at nvidia.com  Tue May 14 01:59:40 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 14 May 2013 07:59:40 +0200
Subject: [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
In-Reply-To: <519118E3.4060907@wwwdotorg.org>
References: <1368443225-16978-1-git-send-email-hdoyu@nvidia.com><1368443225-16978-2-git-send-email-hdoyu@nvidia.com><519118E3.4060907@wwwdotorg.org>
Message-ID: <20130514.085940.1807211932170883314.hdoyu@nvidia.com>

Stephen Warren <swarren at wwwdotorg.org> wrote @ Mon, 13 May 2013 18:46:27 +0200:

> I'm not sure exactly how these patches will get merged. For you
> reference, I anticipate one of two things happening:
> 
> 1)
> 
> * Patches 1, 3, 5 get put into a topic branch, and merged into both the
> clk tree and the Tegra tree.
> 
> * Patches 2, 4, 6 get merged into the Tegra tree.
> 
> * The patches you're going to create for the drivers/clk code get merged
> into Mike's clk tree
> 
> 2)
> 
> * Mike ack's the patches you're going to create for the drivers/clk code.
> 
> * Everything gets merged through the Tegra tree.
> 
> This shouldn't impact you much, but just be aware that the drivers/clk
> changes you create shouldn't depend on anything beyond patches 1, 3, 5
> here and 3.10-rc1, then I can work out the merging with Mike without any
> constraints.

Either way would work. Once Venu's USB patches are merged, mentioned
in [2/6], I'll resend the update version of this series.
drivers/clk/tegra replacement will follow, then.


From magnus.damm at gmail.com  Tue May 14 02:01:01 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Tue, 14 May 2013 15:01:01 +0900
Subject: [PATCH 2/3] ARM: shmobile: r8a7790: Configure R-Car GPIO for
 IRQ_TYPE_EDGE_BOTH
In-Reply-To: <20130514024034.GA20239@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-3-git-send-email-horms+renesas@verge.net.au>
 <2257564.fgMO2c8G9k@avalon> <20130514024034.GA20239@verge.net.au>
Message-ID: <CANqRtoR_BGFo+GRgom2WqXnaGtoB1T90S=twO_4G_t-JE8roTQ@mail.gmail.com>

Hi Simon, Laurent,

On Tue, May 14, 2013 at 11:40 AM, Simon Horman <horms at verge.net.au> wrote:
> On Tue, May 14, 2013 at 12:33:42AM +0200, Laurent Pinchart wrote:
>> Hi Simon,
>>
>> On Monday 13 May 2013 17:53:52 Simon Horman wrote:
>> > "gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
>> > driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
>> > not universal for all SoCs a flag, has_both_edge_trigger, has been
>> > added to the platform data of the driver to allow this feature to be
>> > enabled.
>>
>> What about moving this information to a platform ID table in the gpio-rcar
>> driver ?
>
> Magnus, do you have an opinion on this?

I don't mind so much as long as we:
a) can control things freely per driver instance
and
b) don't have to update all drivers for every new SoC

The current approach allows for that, so as an example if we can have
two slightly different GPIO hardware blocks then we can setup two GPIO
controller driver instances where the configuration can be selected
per-instance. Perhaps Laurent's proposal would allow for this too, I'm
not sure.

On top of that I'd like to avoid doing per-SoC string matching in
drivers. Those would force us to update every darn driver for every
new SoC. It is better to try to use a per-hardware device version in
the drivers and then configure each SoC to use the appropriate
version.

Thanks,

/ magnus


From magnus.damm at gmail.com  Tue May 14 02:09:08 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Tue, 14 May 2013 15:09:08 +0900
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <20130514025941.GC20239@verge.net.au>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
 <9256981.LFpgU8cctr@avalon> <20130514025941.GC20239@verge.net.au>
Message-ID: <CANqRtoTj+FnxrtOayxQYCxkyuP4XGeCaXpNUbPsFV4kyBD_48Q@mail.gmail.com>

Hi Simon and Laurent,

On Tue, May 14, 2013 at 11:59 AM, Simon Horman <horms at verge.net.au> wrote:
> On Tue, May 14, 2013 at 12:35:20AM +0200, Laurent Pinchart wrote:
>> Hi Simon,
>>
>> Thank you for the patch.
>>
>> On Monday 13 May 2013 17:53:53 Simon Horman wrote:
>> > The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
>> > This patch allows access to those pins as KEYS 1 - 4 using
>> > gpio-keys.
>> >
>> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>> >
>> > ---
>> >
>> > This patch has run time dependencies on
>> > 1. "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH"
>> > 2. "ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH"
>> >
>> > Without those dependencies satisfied the gpio-keys driver will
>> > fail to be initialise itself. The boot should be otherwise successful
>> > and the board otherwise functional.
>> > ---
>> >  arch/arm/mach-shmobile/board-lager.c | 22 ++++++++++++++++++++++
>> >  1 file changed, 22 insertions(+)
>> >
>> > diff --git a/arch/arm/mach-shmobile/board-lager.c
>> > b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..4d1b42b 100644
>> > --- a/arch/arm/mach-shmobile/board-lager.c
>> > +++ b/arch/arm/mach-shmobile/board-lager.c
>> > @@ -18,7 +18,10 @@
>> >   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301
>> > USA */
>> >
>> > +#include <linux/gpio.h>
>> > +#include <linux/gpio_keys.h>
>> >  #include <linux/interrupt.h>
>> > +#include <linux/input.h>
>>
>> My dictionary lists input before interrupt :-)
>
> Thanks, I will fix that.
>
>> >  #include <linux/irqchip.h>
>> >  #include <linux/kernel.h>
>> >  #include <linux/leds.h>
>> > @@ -52,6 +55,22 @@ static struct gpio_led_platform_data lager_leds_pdata = {
>> > .num_leds   = ARRAY_SIZE(lager_leds),
>> >  };
>> >
>> > +/* GPIO KEY */
>> > +#define GPIO_KEY(c, g, d, ...) \
>> > +   { .code = c, .gpio = g, .desc = d, .active_low = 1 }
>> > +
>> > +static struct gpio_keys_button gpio_buttons[] = {
>> > +   GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
>> > +   GPIO_KEY(KEY_3,         RCAR_GP_PIN(1, 26),     "SW2-pin3"),
>> > +   GPIO_KEY(KEY_2,         RCAR_GP_PIN(1, 24),     "SW2-pin2"),
>> > +   GPIO_KEY(KEY_1,         RCAR_GP_PIN(1, 14),     "SW2-pin1"),
>> > +};
>> > +
>> > +static struct gpio_keys_platform_data lager_keys_pdata = {
>> > +   .buttons        = gpio_buttons,
>> > +   .nbuttons       = ARRAY_SIZE(gpio_buttons),
>> > +};
>> > +
>>
>> Could you please also update the lager dts file ?
>
> I wonder if in that case we can remove the C code above.
> And probably the C code for the GPIO leds too.
>
> Magnus, could you clarify how you would like
> C-code and DTS to look on the lager board?

I'd like C and DTS to coexist in parallel until we can ditch C fully.
I believe there is a need for us to be able to back port the C code.
For the future we want to use DTS.

To support DTS for Lager I think you should create a -reference DTS
file for Lager where you put the DT version of your GPIO LED / switch
code. At the time when we can configure the PFC via PINCTRL DT then I
believe we should be able to replace most of the platform device code
with DT versions. At that we should hopefully be able to ditch all the
C board code, or maybe we need to keep some around until we have the
common clocks going...

Thanks,

/ magnus


From vinod.koul at intel.com  Tue May 14 01:39:43 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Tue, 14 May 2013 11:09:43 +0530
Subject: [PATCH 0/2 V4] DMA: AT91: Fix get residue function in at_hdmac.c
In-Reply-To: <1368154798-9279-1-git-send-email-elen.song@atmel.com>
References: <1368154798-9279-1-git-send-email-elen.song@atmel.com>
Message-ID: <20130514053943.GD27639@intel.com>

On Fri, May 10, 2013 at 10:59:58AM +0800, Elen Song wrote:
> The residue actually means the bytes remain in transfer identified by current cookie.
> The get residue api did not return the correct values in at_hdmac.c.
> This patch serial focus on fix the issue.
> 
> This patch serials is based on DMA: AT91: Get residual bytes in dma buffer v2.
> It is split into 3 aimed patch, the first one is to get transmit buswidth,
> the second one is to get resiude in cookie, it use the buswidth to get residual bytes,
> the third part is to handle the status that there are still some bytes remain in dma fifo.
Applied, Thanks

--
~Vinod
> 
> Compare to v2, this patch serials improve:
> 1) consider buswidth to get correct residue.
> 2) handle dma fifo empty status.
> 
> Compare to v3, this patch serials improve:
> 1) To state clearly, replace buswidth with transfer width.
> 2) Do not pause dma when get residue.
> 3) Let issue pending handler remain work if data remain in dma fifo, polling empty flag is too time consuming.
> 
> Elen Song (2):
>   DMA: AT91: Get transfer width
>   DMA: AT91: Get residual bytes in dma buffer
> 
>  drivers/dma/at_hdmac.c      |  151 ++++++++++++++++++++++++++++++++++++++-----
>  drivers/dma/at_hdmac_regs.h |    5 ++
>  2 files changed, 139 insertions(+), 17 deletions(-)
> 
> -- 
> 1.7.9.5
> 


From g.liakhovetski at gmx.de  Tue May 14 02:37:47 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Tue, 14 May 2013 08:37:47 +0200 (CEST)
Subject: [PATCH V2 00/10] mmc_of_parse() adaptations, DT support for
 Sheevaplugs
In-Reply-To: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <Pine.LNX.4.64.1305140819520.32151@axis700.grange>

Hi Simon

On Mon, 13 May 2013, Simon Baatz wrote:

> While adding DT support for the Sheevaplugs by Globalscale Technologies
> (Kirkwood), it turned out that the DT binding of mvsdio lacked features to
> properly support the hardware (active high/low of CD and WP pins could not
> be described in DT).
> 
> This is standard functionality provided by the mmc_of_parse() helper
> function.  However, mmc_of_parse() may allocate GPIO lines.  If the
> allocation fails, it outputs an error, but does not return an error to its
> caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.

Thanks for the patches. In principle I'm fine either way. It is a policy 
decision IMHO. E.g. consider a situation. You have a DT with an SD-card 
slot, where card-detection is performed by a GPIO. OTOH the same pin is 
used on some other (optional) interface on the same board. If that other 
competing interface is unused, the driver isn't loaded, you can use the 
GPIO for card-detection. However, if that other interface is used, your 
attempt to get the card-detect pin will fail, but you still can use the 
interface in polling mode. No, I don't think this is a good example of 
hardware design :) User experience would depend on driver probing order, 
but in principle it is imaginable. So, with the current mmc_of_parse() 
you're more tolerant. You get a warning in the log, but the interface 
might still be usable. And if you're surprised why your write protection 
status hasn't been properly detected - just look in the log.

You're proposing a change in behaviour. After your change any failure to 
obtain a resource in mmc_of_parse() will fail interface probing. 
Personally I don't think there are any users around, who would notice this 
change, still, we have to be aware of it. And I don't know whether we 
should do that. You know, we don't break user-space ;-)

So, technically I'm ok with the changes, but policy-wise I'm not sure how 
severe this change would be. We could go a bit slower and first add a 
return code as in your patch #1, but not fail drivers, like in your 
patches #2, 3,... but WARN_ON(mmc_of_parse() < 0); and continue for now. 
In 3.12 we could then replace those warnings with real failures. But maybe 
I'm just overcautious and we can just go ahead with your patches. You can 
add my

Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

for patches 1-3, and let's see what Chris thinks about this change.

Thanks
Guennadi

> The patch set is structured as follows:
> 
> 1   Adapt mmc_of_parse() to return errors
> 2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
>     only)
> 7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
>     kirkwood)
> 9   Add dts files for (eSATA) Sheevaplug
> 10  Add DT support for (eSATA) Sheevaplug
> 
> 
> I could only test on an eSATA Sheevaplug. I found patches with
> different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
> someone with the hardware could give this a spin on a non-eSATA
> version.  Some additional testing of the change detect and write
> protect behaviour for mvsdio can't hurt either.  I hope that there aren't
> board revisions with different CD/WP pins out there.
> 
> Simon Baatz (10):
>   mmc: return mmc_of_parse() errors to caller
>   mmc: sh_mmcif: handle mmc_of_parse() errors during probe
>   mmc: tmio-mmc: handle mmc_of_parse() errors during probe
>   mmc: mxcmmc: handle mmc_of_parse() errors during probe
>   mmc: sdhi-pxav3: handle mmc_of_parse() errors during probe
>   mmc: tegra: handle mmc_of_parse() errors during probe
>   ARM: mvebu: Use standard MMC binding for all users of mvsdio
>   mmc: mvsdio: use standard MMC device-tree binding parser
>     mmc_of_parse()
>   ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug
>   ARM: Kirkwood: add DT support for Sheevaplug and Sheevaplug eSATA

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From g.liakhovetski at gmx.de  Tue May 14 02:38:20 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Tue, 14 May 2013 08:38:20 +0200 (CEST)
Subject: [PATCH V2 05/10] mmc: sdhi-pxav3: handle mmc_of_parse() errors
 during probe
In-Reply-To: <1368479941-10084-6-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-6-git-send-email-gmbnomis@gmail.com>
Message-ID: <Pine.LNX.4.64.1305140837540.32151@axis700.grange>

There's a typo in the subject line - it's sdhci, not sdhi :)

Thanks
Guennadi

On Mon, 13 May 2013, Simon Baatz wrote:

> 
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  drivers/mmc/host/sdhci-pxav3.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 1ae358e..67ea388 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -252,7 +252,9 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>  
>  	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
>  	if (match) {
> -		mmc_of_parse(host->mmc);
> +		ret = mmc_of_parse(host->mmc);
> +		if (ret)
> +			goto err_of_parse;
>  		sdhci_get_of_property(pdev);
>  		pdata = pxav3_get_mmc_pdata(dev);
>  	} else if (pdata) {
> @@ -313,10 +315,11 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>  
>  	return 0;
>  
> +err_of_parse:
> +err_cd_req:
>  err_add_host:
>  	clk_disable_unprepare(clk);
>  	clk_put(clk);
> -err_cd_req:
>  err_clk_get:
>  	sdhci_pltfm_free(pdev);
>  	kfree(pxa);
> -- 
> 1.7.9.5
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From pranavkumar at linaro.org  Tue May 14 02:52:41 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Tue, 14 May 2013 12:22:41 +0530
Subject: [PATCH V2] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits
In-Reply-To: <51912003.6080406@codeaurora.org>
References: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org>
 <51910559.6060106@codeaurora.org>
 <fae8138d41c55928a3c71b7073aea3b0@localhost>
 <51912003.6080406@codeaurora.org>
Message-ID: <CAAHg+HhR4gvEs2F7WzbyQBWiDJSh9+s7=QFkmd0OWss1RfS4Tg@mail.gmail.com>

Hi Christopher,

On 13 May 2013 22:46, Christopher Covington <cov at codeaurora.org> wrote:
> On 05/13/2013 12:02 PM, Marc Zyngier wrote:
>> On Mon, 13 May 2013 11:23:05 -0400, Christopher Covington
>> <cov at codeaurora.org> wrote:
>>> Hi Pranavkumar,
>>>
>>> On 05/10/2013 03:23 AM, Pranavkumar Sawargaonkar wrote:
>>>> This patch does following fixes:
>>>>
>>>> 1. Make HCR_* flags as unsigned long long constants
>>>> Reason : By default, compiler assumes numeric constants as
>>>> signed hence sign extending it when assigned to unsigned variable
>>>> such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and
>>>> HCR_CD making entire guest memory non-cacheable. On real HW, this
>>>> breaks Stage2 ttbl walks and also breaks VirtIO.
>>>>
>>>> 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros.
>>>>
>>>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>>>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>>>> ---
>>>>  arch/arm64/include/asm/kvm_arm.h |   73
>>>>  +++++++++++++++++++-------------------
>>>>  1 file changed, 37 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/include/asm/kvm_arm.h
>>>> b/arch/arm64/include/asm/kvm_arm.h
>>>> index 8ced0ca..14ead69 100644
>>>> --- a/arch/arm64/include/asm/kvm_arm.h
>>>> +++ b/arch/arm64/include/asm/kvm_arm.h
>>>> @@ -18,44 +18,45 @@
>>>>  #ifndef __ARM64_KVM_ARM_H__
>>>>  #define __ARM64_KVM_ARM_H__
>>>>
>>>> +#include <linux/const.h>
>>>>  #include <asm/types.h>
>>>>
>>>>  /* Hyp Configuration Register (HCR) bits */
>>>> -#define HCR_ID             (1 << 33)
>>>> -#define HCR_CD             (1 << 32)
>>>> +#define HCR_ID             (UL(0x1) << 33)
>>>> +#define HCR_CD             (UL(0x1) << 32)
>>>
>>> Consider using the BIT() macro from linux/bitops.h to improve
>> readability.
>>
>> This would probably cause problems when using these macros from assembly
>> code.
>
> It does indeed cause problems. What a shame. How about a quick local
> definition, to perhaps be eventually replaced by a more accessible shared
> definition?

I have used UL to be synced with current arm64 code style (it has been
used in other files also).
Using BIT is good idea (not sure about local definition i.e. how good
it is when we have one inside bitops.h)
but if we want to use it is, then better idea is to use it everywhere.
>
> Christopher

Thanks,
Pranav

>
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> hosted by the Linux Foundation.


From s.trumtrar at pengutronix.de  Tue May 14 03:01:47 2013
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Tue, 14 May 2013 09:01:47 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for
 some SoC
In-Reply-To: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20130514070147.GB29391@pengutronix.de>

Hi!

On Mon, May 13, 2013 at 06:05:05PM +0200, Nicolas Ferre wrote:
> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
> introduces clear-on-write on ISR register. This behavior is not always
> implemented when using Cadence MACB/GEM and is breaking other platforms.
> We are using a new Device Tree compatibility string and a capability
> property to actually activate this clear-on-write behavior on ISR.
> 
> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
>  Documentation/devicetree/bindings/net/macb.txt |  2 ++
>  drivers/net/ethernet/cadence/macb.c            | 15 +++++++++++++--
>  drivers/net/ethernet/cadence/macb.h            |  5 +++++
>  3 files changed, 20 insertions(+), 2 deletions(-)
> 

Looks okay to me:

Acked-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>

Thanks,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From andre.przywara at linaro.org  Tue May 14 03:07:43 2013
From: andre.przywara at linaro.org (Andre Przywara)
Date: Tue, 14 May 2013 09:07:43 +0200
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM
 VCPU ioctl
In-Reply-To: <CAEDV+gKTYCh8zTPJAxSmwhuyWo7K5Ej75giryR-pv5oqHdURSQ@mail.gmail.com>
References: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
 <20130513055253.GC64337@ubuntu> <519167D3.4030600@linaro.org>
 <CAEDV+gKTYCh8zTPJAxSmwhuyWo7K5Ej75giryR-pv5oqHdURSQ@mail.gmail.com>
Message-ID: <5191E2BF.5040102@linaro.org>

On 05/14/2013 12:42 AM, Christoffer Dall wrote:
> On Mon, May 13, 2013 at 3:23 PM, Andre Przywara
> <andre.przywara at linaro.org> wrote:
>> ooks like a natural candidate, but unfortunately struct kvm_vcpu is opaque
>> here, so dereferencing it does not work without further changes which I do
>> not deem to be justified. I used kvm_coproc.h instead, which is loosely
>> related (KVM_[SG]ET_ONE_REG) and just simply works. If you don't think
>> that's appropriate, just drop me a note. Patch follows in a separate mail.
>
> eh, not crazy about the idea. x86 has
> arch/x86/include/asm/kvm_guest.h, which may be the most appropriate,
> or this could be generalized to other architectures as well and
> included in include/linux/kvm_host.h.
>
> we can just stick it in arch/arm/kvm/arm.c for now and move later if
> need be, no need to create a fuzz.

Ok, would you mind to commit v2 and add the "inline" on the way?

Thanks,
Andre.



From neidhard.kim at lge.com  Tue May 14 03:15:39 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Tue, 14 May 2013 16:15:39 +0900
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <5191D200.3040604@wwwdotorg.org>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org>
Message-ID: <01fd01ce5072$d6b9fcd0$842df670$@lge.com>

Stephen Warren <swarren at wwwdotorg.org> :
> For reference, the AMBA periphid of the UART device there is 0x00341011.
> The nibble "3" is the revision being tested in:

The UART device has periphid 0x00341011, and is compatible with the
original PL011 prior to r1p5. Not with r1p5. It could be a possible
way to specify the compatible periphid (such as 0x00241011) instead
of just 0x0 when initializing the amba_device for the UART.

> > +static unsigned int get_fifosize_arm(unsigned int periphid)
> > +{
> > +	unsigned int rev = (periphid >> 20) & 0xf;
> > +	return rev < 3 ? 16 : 32;
> > +}
>
> Should that be <= not <, or is there just something more wrong in the
> patch or bcm2835 HW? I wonder how r1p5 maps to 3 in the test above.

>From the PL011-r1p5 TRM, bits[7:4] of the UARTPeriphID2 register are
read as:

r1p0 - 0x0
r1p1 - 0x1
r1p3 - 0x2
r1p4 - 0x2
r1p5 - 0x3.

Doesn't the BCM2835 UART have anything different from the ARM PL011?
What about the UARTPCellID registers? They are set to 0xb105f00d with
the ARM PL011.



From 21cnbao at gmail.com  Tue May 14 03:17:36 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 14 May 2013 15:17:36 +0800
Subject: [PATCH] pinctrl:sirf:re-arch and add support for new SiRFatlas6
 SoC
In-Reply-To: <CACRpkda+ghKMkXFQzkJ7uauwGWGNrn4aqyYajt9U9RYkmvT-6g@mail.gmail.com>
References: <1363597988-7409-1-git-send-email-Barry.Song@csr.com>
 <CACRpkdYUTQ_7V1CbKbx05zgBONj6iUi=ekzSwmZz8dqeRx7ZJw@mail.gmail.com>
 <CAGsJ_4wmn-LxxX-JeSJzdkVFSUeJ=vQrKHJr9yUtsoxG2BFHtw@mail.gmail.com>
 <CACRpkdaMYTXpnfg8MhRP5Fs_Qn2gwv=Xuk3YSYejxt+vK9D6+w@mail.gmail.com>
 <CAGsJ_4xSk_fXjhM2kxy0Hd36e9BsGshfmM97KgcU3cC5avmxtQ@mail.gmail.com>
 <CACRpkda+ghKMkXFQzkJ7uauwGWGNrn4aqyYajt9U9RYkmvT-6g@mail.gmail.com>
Message-ID: <CAGsJ_4xUBHiSkgxXRMZNAm0-6nOrdKwSZi0Am+6Nh5PJRxFGMw@mail.gmail.com>

2013/4/9 Linus Walleij <linus.walleij at linaro.org>:
> On Sun, Apr 7, 2013 at 5:03 AM, Barry Song <21cnbao at gmail.com> wrote:
>> 2013/4/3 Linus Walleij <linus.walleij at linaro.org>:
>>> On Thu, Mar 28, 2013 at 7:27 AM, Barry Song <21cnbao at gmail.com> wrote:
>>>> 2013/3/28, Linus Walleij <linus.walleij at linaro.org>:
>>>
>>>>>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>>>>>
>>>>> This is OK but can you please:
>>>>
>>>> ok. one issue is recently Arnd has given another changes in
>>>> pinctrl-sirf in arm-soc multiple platform branch:
>>>> https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=prima2/multiplatform&id=67d71344fd09223820eb9de39b597ec29f035e89
>>>>
>>>> it makes us easily to get merging conflict. what is your suggestion
>>>> about taking all these changes in 3.10?
>>>
>>> Please send this to where the rest of the patches are with my ACK
>>> (I guess the ARM SoC tree?)
>>
>> unfortunately, this is not in arm soc:
>> Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>> pinctrl: sirf: using for_each_set_bit to simplify the code
>>
>> https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=3dcbd6f5789839c7fea8841088ed3a28688f81ed
>>
>> i think there will still be some merge conflict. so to make people
>> easy, i might wait for 3.11 and resend the patch with your ack, then
>> you apply it on pinctrl tree.
>
> OK let's do it like that.

done by "[PATCH RESEND] pinctrl:sirf:re-arch and add support for new
SiRFatlas6 SoC"

> Linus Walleij

-barry


From ulf.hansson at linaro.org  Tue May 14 03:20:14 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Tue, 14 May 2013 09:20:14 +0200
Subject: [PATCH V2 01/10] mmc: return mmc_of_parse() errors to caller
In-Reply-To: <1368479941-10084-2-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-2-git-send-email-gmbnomis@gmail.com>
Message-ID: <CAPDyKFoyVCYDFkXWrj8zL8uGCTx4EYk=rM2i7rKx1+aA7LCbPg@mail.gmail.com>

On 13 May 2013 23:18, Simon Baatz <gmbnomis at gmail.com> wrote:
> In addition to just logging errors encountered during DT parsing or
> allocating GPIO slots for CD/WP, mmc_of_parse() now returns with an
> error.
>
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  drivers/mmc/core/host.c  |   24 +++++++++++++++++++-----
>  include/linux/mmc/host.h |    2 +-
>  2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index 2a3593d..45122cc 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -306,7 +306,7 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
>   * parse the properties and set respective generic mmc-host flags and
>   * parameters.
>   */
> -void mmc_of_parse(struct mmc_host *host)
> +int mmc_of_parse(struct mmc_host *host)
>  {
>         struct device_node *np;
>         u32 bus_width;
> @@ -315,7 +315,7 @@ void mmc_of_parse(struct mmc_host *host)
>         int len, ret, gpio;
>
>         if (!host->parent || !host->parent->of_node)
> -               return;
> +               return 0;
>
>         np = host->parent->of_node;
>
> @@ -338,6 +338,7 @@ void mmc_of_parse(struct mmc_host *host)
>         default:
>                 dev_err(host->parent,
>                         "Invalid \"bus-width\" value %ud!\n", bus_width);
> +               return -EINVAL;
>         }
>
>         /* f_max is obtained from the optional "max-frequency" property */
> @@ -372,13 +373,15 @@ void mmc_of_parse(struct mmc_host *host)
>                                 gpio_inv_cd = true;
>
>                         ret = mmc_gpio_request_cd(host, gpio);
> -                       if (ret < 0)
> +                       if (ret < 0) {
>                                 dev_err(host->parent,
>                                         "Failed to request CD GPIO #%d: %d!\n",
>                                         gpio, ret);
> -                       else
> +                               return ret;
> +                       } else {
>                                 dev_info(host->parent, "Got CD GPIO #%d.\n",
>                                          gpio);
> +                       }
>                 }
>
>                 if (explicit_inv_cd ^ gpio_inv_cd)
> @@ -394,9 +397,14 @@ void mmc_of_parse(struct mmc_host *host)
>                         gpio_inv_wp = true;
>
>                 ret = mmc_gpio_request_ro(host, gpio);
> -               if (ret < 0)
> +               if (ret < 0) {
>                         dev_err(host->parent,
>                                 "Failed to request WP GPIO: %d!\n", ret);
> +                       goto out;
> +               } else {
> +                               dev_info(host->parent, "Got WP GPIO #%d.\n",
> +                                        gpio);
> +               }
>         }
>         if (explicit_inv_wp ^ gpio_inv_wp)
>                 host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
> @@ -413,6 +421,12 @@ void mmc_of_parse(struct mmc_host *host)
>                 host->pm_caps |= MMC_PM_KEEP_POWER;
>         if (of_find_property(np, "enable-sdio-wakeup", &len))
>                 host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
> +
> +       return 0;
> +
> +out:
> +       mmc_gpio_free_cd(host);
> +       return ret;
>  }
>
>  EXPORT_SYMBOL(mmc_of_parse);
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index e326ae2..c8c4fbc 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -369,7 +369,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *);
>  int mmc_add_host(struct mmc_host *);
>  void mmc_remove_host(struct mmc_host *);
>  void mmc_free_host(struct mmc_host *);
> -void mmc_of_parse(struct mmc_host *host);
> +int mmc_of_parse(struct mmc_host *host);
>
>  static inline void *mmc_priv(struct mmc_host *host)
>  {
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Reviewed-by: Ulf Hansson <ulf.hansson at linaro.org>


From plagnioj at jcrosoft.com  Tue May 14 03:22:05 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 May 2013 15:22:05 +0800
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some
 SoC
In-Reply-To: <5191E53B.9000106@yahoo.es>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
 <51918C23.7040106@yahoo.es> <20130514055256.GD22508@game.jcrosoft.org>
 <5191E53B.9000106@yahoo.es>
Message-ID: <C35C1E42-FCD6-4EE7-902B-FE01F362CD40@jcrosoft.com>


On May 14, 2013, at 3:18 PM, Hein Tibosch <hein_tibosch at yahoo.es> wrote:

> 
> On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 08:58 Tue 14 May     , Hein Tibosch wrote:
>>> On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>>>> 
>>>>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>>>>> introduces clear-on-write on ISR register. This behavior is not always
>>>>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>>>>> We are using a new Device Tree compatibility string and a capability
>>>>> property to actually activate this clear-on-write behavior on ISR.
>>>>> 
>>>>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>>>>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>>> can we detect it via the IP?
>>> This was my first proposal, have it based on the value of MACB's
>>> register 'MID' (offset 0x00fc, lower 16 bits).
>>> On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
>>> 
>>> So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
>>> equals to 0x00000119?
>> so no it will not work
>> 
>> as the gem on sama5 is 00020119
>> 
>> so version 0x119 too
>> 
>> nico
> 
> All right, that's a pity.
> 
> The only issue that remains then is the obligation to use CONFIG_OF,
> or:
> 
> +#if defined(CONFIG_OF)
> +	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
> +	if (dev_id)
> +		bp->caps = (u32)dev_id->data;
> +
> +#endif
> 
> ?

no need as of_match_device is a inline of !OF

Best Regards,
J.
> 
> Hein
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From davem at davemloft.net  Tue May 14 03:48:02 2013
From: davem at davemloft.net (David Miller)
Date: Tue, 14 May 2013 00:48:02 -0700 (PDT)
Subject: [PATCH] mv643xx_eth: fix NAPI weight being > 64
In-Reply-To: <1368508632-13742-1-git-send-email-andrew@lunn.ch>
References: <1368508632-13742-1-git-send-email-andrew@lunn.ch>
Message-ID: <20130514.004802.2003665831321985333.davem@davemloft.net>

From: Andrew Lunn <andrew at lunn.ch>
Date: Tue, 14 May 2013 07:17:12 +0200

> 3.10-rc1 issues the following warning:
> 
> netif_napi_add() called with weight 128 on device eth%d
> 
> This patch reduce the weight to 64.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>

We have a macro, NAPI_POLL_WEIGHT, for this, please use it.


From monstr at monstr.eu  Tue May 14 03:49:41 2013
From: monstr at monstr.eu (Michal Simek)
Date: Tue, 14 May 2013 09:49:41 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some
 SoC
In-Reply-To: <5191E855.5090908@yahoo.es>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
 <51918C23.7040106@yahoo.es> <20130514055256.GD22508@game.jcrosoft.org>
 <5191E53B.9000106@yahoo.es>
 <C35C1E42-FCD6-4EE7-902B-FE01F362CD40@jcrosoft.com>
 <5191E855.5090908@yahoo.es>
Message-ID: <5191EC95.2020704@monstr.eu>

On 05/14/2013 09:31 AM, Hein Tibosch wrote:
> On 5/14/2013 3:22 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On May 14, 2013, at 3:18 PM, Hein Tibosch <hein_tibosch at yahoo.es> wrote:
>>
>>> On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> On 08:58 Tue 14 May     , Hein Tibosch wrote:
>>>>> On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>>>> On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>>>>>>
>>>>>>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>>>>>>> introduces clear-on-write on ISR register. This behavior is not always
>>>>>>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>>>>>>> We are using a new Device Tree compatibility string and a capability
>>>>>>> property to actually activate this clear-on-write behavior on ISR.
>>>>>>>
>>>>>>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>>>>>>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>>>>> can we detect it via the IP?
>>>>> This was my first proposal, have it based on the value of MACB's
>>>>> register 'MID' (offset 0x00fc, lower 16 bits).
>>>>> On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
>>>>>
>>>>> So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
>>>>> equals to 0x00000119?
>>>> so no it will not work
>>>>
>>>> as the gem on sama5 is 00020119
>>>>
>>>> so version 0x119 too
>>>>
>>>> nico
>>> All right, that's a pity.
>>>
>>> The only issue that remains then is the obligation to use CONFIG_OF,
>>> or:
>>>
>>> +#if defined(CONFIG_OF)
>>> +	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
>>> +	if (dev_id)
>>> +		bp->caps = (u32)dev_id->data;
>>> +
>>> +#endif
>>>
>>> ?
>> no need as of_match_device is a inline of !OF
> Sorry, here's the complete compiler error:
> drivers/net/ethernet/cadence/macb.c: In function 'macb_probe':
> drivers/net/ethernet/cadence/macb.c:1601: error: 'macb_dt_ids' undeclared (first use in this function)
> 
> Earlier, 'macb_dt_ids' is only defined when using OF

The trick is in using of_match_ptr. It means remove that CONFIG_OF around macb_dt_ids too.

[linux-2.6.x]$ grep -rn "of_match_ptr" include/linux/
include/linux/of.h:314:#define of_match_ptr(_ptr)	(_ptr)
include/linux/of.h:508:#define of_match_ptr(_ptr)	NULL

Thanks,
Michal



-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From linus.walleij at linaro.org  Tue May 14 04:03:42 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:03:42 +0200
Subject: [RFC PATCHv3 4/6] clocksource: Add TI-Nspire timer drivers
In-Reply-To: <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>
Message-ID: <CACRpkdZBFbOnQ9rCehO0yKDN7fH9VR3VYCa_NkOGJz7KN+02FQ@mail.gmail.com>

On Sun, May 12, 2013 at 6:22 AM, Daniel Tang <dt.tangr at gmail.com> wrote:

> Signed-off-by: Daniel Tang <dt.tangr at gmail.com>

A commit message does not hurt.

>  drivers/clocksource/Makefile               |   1 +
>  drivers/clocksource/nspire-classic-timer.c | 199 +++++++++++++++++++++++++++++

This subsystem is managed by Thomas Gleixner and John Stultz so you
should include
them on the To: line in reviewes.

> +++ b/drivers/clocksource/nspire-classic-timer.c
(...)
> +struct nspire_timer {
> +       void __iomem *base;
> +       void __iomem *timer1, *timer2;
> +       void __iomem *interrupt_regs;
> +
> +       int irqnr;
> +
> +       struct clk *clk;
> +       struct clock_event_device clkevt;
> +       struct irqaction clkevt_irq;
> +
> +       char clocksource_name[64];
> +       char clockevent_name[64];
> +};
> +
> +static int nspire_timer_set_event(unsigned long delta,
> +               struct clock_event_device *dev)
> +{
> +       unsigned long flags;
> +       struct nspire_timer *timer = container_of(dev,
> +                       struct nspire_timer,
> +                       clkevt);
> +
> +       local_irq_save(flags);
> +
> +       writel(delta, timer->timer1 + IO_CURRENT_VAL);
> +       writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH1,
> +                       timer->timer1 + IO_CONTROL);
> +
> +       local_irq_restore(flags);
> +
> +       return 0;
> +}
> +static void nspire_timer_set_mode(enum clock_event_mode mode,
> +               struct clock_event_device *evt)
> +{
> +       evt->mode = mode;

So you support any mode?

Atleast handle CLOCK_EVT_MODE_SHUTDOWN and CLOCK_EVT_UNUSED
like any well-behaved clock event driver.

> +}
> +
> +static irqreturn_t nspire_timer_interrupt(int irq, void *dev_id)
> +{
> +       struct nspire_timer *timer = dev_id;
> +
> +       writel((1<<0), timer->interrupt_regs + IO_INTR_ACK);

write(0x1, timer->interrupt_regs + IO_INTR_ACK);

is no less intelligible, if you really want to point out that you're
setting bit 0, include <linux/bitops.h> and use BIT(0).

If there is a status bit you're clearing, maybe you should check
it first to watch for spurious IRQs?

> +       writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
> +
> +       if (timer->clkevt.event_handler)
> +               timer->clkevt.event_handler(&timer->clkevt);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static int __init nspire_timer_add(struct device_node *node)
> +{
> +       struct nspire_timer *timer;
> +       struct resource res;
> +       int ret;
> +
> +       timer = kzalloc(sizeof(*timer), GFP_ATOMIC);
> +       if (!timer)
> +               return -ENOMEM;
> +
> +       timer->base = of_iomap(node, 0);
> +       if (!timer->base) {
> +               ret = -EINVAL;
> +               goto error_free;
> +       }
> +       timer->timer1 = timer->base + IO_TIMER1;
> +       timer->timer2 = timer->base + IO_TIMER2;
> +
> +       timer->clk = of_clk_get(node, 0);
> +       if (IS_ERR(timer->clk)) {
> +               ret = PTR_ERR(timer->clk);
> +               pr_err("Timer clock not found! (error %d)\n", ret);
> +               goto error_unmap;
> +       }
> +
> +       timer->interrupt_regs = of_iomap(node, 1);

Check for errors.

> +       timer->irqnr = irq_of_parse_and_map(node, 0);

Check for errors.

> +
> +       of_address_to_resource(node, 0, &res);
> +       scnprintf(timer->clocksource_name, sizeof(timer->clocksource_name),
> +                       "%llx.%s_clocksource",
> +                       (unsigned long long)res.start, node->name);
> +
> +       scnprintf(timer->clockevent_name, sizeof(timer->clockevent_name),
> +                       "%llx.%s_clockevent",
> +                       (unsigned long long)res.start, node->name);
> +
> +       if (timer->interrupt_regs && timer->irqnr) {
> +               timer->clkevt.name      = timer->clockevent_name;
> +               timer->clkevt.set_next_event = nspire_timer_set_event;
> +               timer->clkevt.set_mode  = nspire_timer_set_mode;
> +               timer->clkevt.rating    = 200;
> +               timer->clkevt.shift     = 32;

Delete this shift. It will be set by clockevents_config_and_register().

> +               timer->clkevt.cpumask   = cpu_all_mask;
> +               timer->clkevt.features  =
> +                       CLOCK_EVT_FEAT_ONESHOT;
> +
> +               writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
> +               writel(0, timer->timer1 + IO_DIVIDER);

For a 16-bit counter I don't think it's wise to set the divider to 0
unless the clock frequency is very low. See further comments
below. (Assumes this is some prescaler.)

> +               /* Mask out interrupts except the one we're using */
> +               writel((1<<0), timer->interrupt_regs + IO_INTR_MSK);

Just 0x1 or BIT(0).

> +               writel(0x3F, timer->interrupt_regs + IO_INTR_ACK);

Hm magic number, I guess it's clearing all IRQ lines...

> +
> +               /* Interrupt to occur when timer value matches 0 */
> +               writel(0, timer->base + IO_MATCH1);
> +
> +               timer->clkevt_irq.name  = timer->clockevent_name;
> +               timer->clkevt_irq.handler = nspire_timer_interrupt;
> +               timer->clkevt_irq.dev_id = timer;
> +               timer->clkevt_irq.flags =
> +                       IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
> +
> +               setup_irq(timer->irqnr, &timer->clkevt_irq);
> +
> +               clockevents_config_and_register(&timer->clkevt,
> +                               clk_get_rate(timer->clk), 0x0001, 0xfffe);
> +               pr_info("Added %s as clockevent\n", timer->clockevent_name);
> +       }
> +
> +       writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
> +                       timer->timer2 + IO_CONTROL);
> +
> +       clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
> +                       timer->clocksource_name,
> +                       clk_get_rate(timer->clk),
> +                       200, 16,
> +                       clocksource_mmio_readw_up);

If this timer is really just 16 bits, it's a *pretty* good idea to use
the prescaler (I guess this is what IO_DIVIDER is) beacuse else you
will get short sleep times with CONFIG_NO_HZ_IDLE on this system,
and wake up unnecessarily often.

The same goes for the clock event.

See how we calculate the prescaler in arch/arm/mach-integrator/integrator_ap.c
for example.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 04:17:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:17:00 +0200
Subject: [PATCH 1/9] ARM: ux500: Remove duplicated assignment of
 ab8500_platdata
In-Reply-To: <1368019749-19455-2-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZSGiYDY=PbtLyVKZCFLTbhSq7crCDATwpeFkU9UOe3Fg@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Since: "05ec260 mfd: db8500-prcmu: update resource passing", the AB8500's
> platform data 'ab8500_platdata' is passed directly as an attribute to
> 'db8500_prcmu_pdata', so there's no requirement to assign it a second
> time. In fact, it's only due to an ordering issue that the entire
> 'db8500_prcmu_pdata' data structure isn't completely over-written by the
> assignment in u8500_init_devices().
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Good catch! Patch applied.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 04:23:17 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:23:17 +0200
Subject: [PATCH 2/9] mfd: ab8500-core: Use the correct driver name when
 enabling gpio/pinctrl
In-Reply-To: <1368019749-19455-3-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbBh1cF468zMbDNfpgsUKERPHONbLeY=VSDNBhG25B0gg@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> When we're using Device Tree to enable GPIO drivers we're forced to be
> OS agnostic, thus we are forbidden use names like pinctrl as they are
> specific only to Linux.

Oh that depends. I have hade lectures on pin control at the embedded
systems conference and there I treat it as a neutral term referring to this
kind of electronic constructions.

However how something is established in OF ontology I don't know so
you might be right there, but you're making it sound like
Documentation/devicetree/bindings/pinctrl/
should not exist and all those bindings be moved to gpio or
something if the assumption that "pin control" or the abbreviation
pinctrl is a Linux-specific term. (Which is not my interpretation.)

> However, when we are registering devices using
> internal systems such as MFD or platform registration, we can use such
> terminology. In this case we can and should use the platform device ID
> mechanism to specify which device we wish to utilise by detailing
> pinctrl-<device_name>.
>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

The commit message should state what regression it is actually
solving. Which is that when using a non-DT boot, the ABx500
pinctrl devices are not probed, right?

Apart from the commit message:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

On the patch as such.

Yours,
Linus Walleij


From maxime.ripard at free-electrons.com  Tue May 14 04:23:20 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 10:23:20 +0200
Subject: [PATCH 05/14] ARM: shmobile: Remove init_irq declaration in
 machine description
In-Reply-To: <20130514003504.GE12228@verge.net.au>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-6-git-send-email-maxime.ripard@free-electrons.com>
 <20130514003504.GE12228@verge.net.au>
Message-ID: <5191F478.4040800@free-electrons.com>

Hi Simon,

Le 14/05/2013 02:35, Simon Horman a ?crit :
> On Mon, May 13, 2013 at 11:44:04AM +0200, Maxime Ripard wrote:
>> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
>> specified") removed the need to explictly setup the init_irq field in
>> the machine description when using only irqchip_init. Remove that
>> declaration for shmobile as well.
> 
> Hi Maxime,
> 
> If possible, I would prefer separate patches for each board and SoC.

Ok, I'll split this and send it in the v2.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From linus.walleij at linaro.org  Tue May 14 04:25:15 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:25:15 +0200
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaWaEct1My5=gZ7Bbbizqsr3BBNSXiahMn3bS7L-SubLg@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> First Ethernet device has a ".0" appended onto the device name. It
> appears that we need this in order to obtain the correct clock.
>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From maxime.ripard at free-electrons.com  Tue May 14 04:25:39 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 10:25:39 +0200
Subject: [PATCH 06/14] ARM: bcm281xx: Remove init_irq declaration in
 machine description
In-Reply-To: <519147C6.6080004@broadcom.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-7-git-send-email-maxime.ripard@free-electrons.com>
 <519147C6.6080004@broadcom.com>
Message-ID: <5191F503.2070301@free-electrons.com>

Hi Christian,

Le 13/05/2013 22:06, Christian Daudt a ?crit :
> On 13-05-13 02:44 AM, Maxime Ripard wrote:
>> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
>> specified") removed the need to explictly setup the init_irq field in
>> the machine description when using only irqchip_init. Remove that
>> declaration for bcm281xx as well.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>> ---
>>   arch/arm/mach-bcm/board_bcm.c | 1 -
>>   1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-bcm/board_bcm.c
>> b/arch/arm/mach-bcm/board_bcm.c
>> index 22e8421..24556cf 100644
>> --- a/arch/arm/mach-bcm/board_bcm.c
>> +++ b/arch/arm/mach-bcm/board_bcm.c
>> @@ -54,7 +54,6 @@ static void __init board_init(void)
>>   static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351",
>> NULL, };
>>     DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
>> -    .init_irq = irqchip_init,
>>       .init_time = clocksource_of_init,
>>       .init_machine = board_init,
>>       .dt_compat = bcm11351_dt_compat,
> Acked-by: Christian Daudt <csd at broadcom.com>

Thanks!

I forgot to remove the include of irqchip.h into all these patches, so
I'll send a v2, and I guess you could probably merge it through your
tree after that directly.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From linus.walleij at linaro.org  Tue May 14 04:25:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:25:58 +0200
Subject: [PATCH 4/9] mfd: db8500-prcmu: Supply the pdata_size attribute
 for db8500-thermal
In-Reply-To: <1368019749-19455-5-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdakF3KSV9QM1E65X+Zipeu2=uA=wpMz2DMGZOCdM--Mdw@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The MFD subsystem requires drivers to state the size of any platform
> data passed, or it will fail to assign it to the device. This will
> culminate in a NULL platform_data attribute and normally a failure to
> probe() or a kernel Oops.
>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 04:27:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:27:31 +0200
Subject: [PATCH 5/9] ARM: ux500: Fix incorrect DEBUG UART virtual addresses
In-Reply-To: <1368019749-19455-6-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY669Af-DK9jPkW==u9PtqnL=pipiN9Rx8hi=PHO5mtyg@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> A recent move to rid header files which were hindering multiplatform
> support forced address allocations out of the headers and into the
> files which were using them. We also lost some useful macros such as
> IO_ADDRESS(), so physical -> virtual addressing has been carried out
> manually in this case. Unfortunately the incorrect value was converted.
> This patch rectifies the error and ensures earlyprintk works again.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Thanks for fixing this!

And sorry for screwing it up :-(

Patch applied!

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 04:30:18 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:30:18 +0200
Subject: [PATCH 6/9] ARM: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <1368019749-19455-7-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYz0HcdBovoJu6O-4QyRbXz93MaeWwAwCohbE8rv=8O7Q@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> First Ethernet device has a ".0" appended onto the device name. It
> appears that we need this in order to obtain the correct clock.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
(...)
> -       OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
> +       OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),

I guess what you want to say in the commit message is that
on a non-DT boot the ethernet will be named "smsc911x.0"
and since the clocks are not converted to device tree these
names need to be matched when providing the name from
auxdata.

Edited the commit message and applied!

Yours,
Linus Walleij


From maxime.ripard at free-electrons.com  Tue May 14 04:32:49 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 10:32:49 +0200
Subject: [PATCH 08/14] ARM: msm: Remove init_irq declaration in machine
 description
In-Reply-To: <20130513182648.GA26913@codeaurora.org>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-9-git-send-email-maxime.ripard@free-electrons.com>
 <20130513182648.GA26913@codeaurora.org>
Message-ID: <5191F6B1.9080000@free-electrons.com>

Hi David,

Le 13/05/2013 20:26, David Brown a ?crit :
> On Mon, May 13, 2013 at 11:44:07AM +0200, Maxime Ripard wrote:
>> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
>> specified") removed the need to explictly setup the init_irq field in
>> the machine description when using only irqchip_init. Remove that
>> declaration for msm as well.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>> ---
>>  arch/arm/mach-msm/board-dt-8660.c | 1 -
>>  arch/arm/mach-msm/board-dt-8960.c | 1 -
>>  2 files changed, 2 deletions(-)
> 
> I'll pull this into my msm-cleanup tree.

Like I said in other mails from this thread, I'll send a v2, so you
might want to hold off this patch until then.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From linus.walleij at linaro.org  Tue May 14 04:35:45 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:35:45 +0200
Subject: [PATCH 7/9] pinctrl: abx500: Specify failed sub-driver by ID
 instead of driver_data
In-Reply-To: <1368019749-19455-8-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYTBdtRkY1e-Qnzdk27wpKFkNKTtmXazjTDxTh1hmXmgw@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> If a sub-driver has not been specified correctly, there is a good chance
> that plat_id is NULL, hence using an attribute of plat_id in the error
> message is likely to not only fail the driver but Oops the kernel. Use
> the failed ID instead.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Good patch! Applied to the pinctrl fixes.

Yours,
Linus Walleij


From horms at verge.net.au  Tue May 14 04:38:17 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 14 May 2013 17:38:17 +0900
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <CANqRtoTj+FnxrtOayxQYCxkyuP4XGeCaXpNUbPsFV4kyBD_48Q@mail.gmail.com>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <1368435233-8587-4-git-send-email-horms+renesas@verge.net.au>
 <9256981.LFpgU8cctr@avalon> <20130514025941.GC20239@verge.net.au>
 <CANqRtoTj+FnxrtOayxQYCxkyuP4XGeCaXpNUbPsFV4kyBD_48Q@mail.gmail.com>
Message-ID: <20130514083816.GB24811@verge.net.au>

On Tue, May 14, 2013 at 03:09:08PM +0900, Magnus Damm wrote:
> Hi Simon and Laurent,
> 
> On Tue, May 14, 2013 at 11:59 AM, Simon Horman <horms at verge.net.au> wrote:
> > On Tue, May 14, 2013 at 12:35:20AM +0200, Laurent Pinchart wrote:
> >> Hi Simon,
> >>
> >> Thank you for the patch.
> >>
> >> On Monday 13 May 2013 17:53:53 Simon Horman wrote:
> >> > The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
> >> > This patch allows access to those pins as KEYS 1 - 4 using
> >> > gpio-keys.
> >> >
> >> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >> >
> >> > ---
> >> >
> >> > This patch has run time dependencies on
> >> > 1. "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH"
> >> > 2. "ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH"
> >> >
> >> > Without those dependencies satisfied the gpio-keys driver will
> >> > fail to be initialise itself. The boot should be otherwise successful
> >> > and the board otherwise functional.
> >> > ---
> >> >  arch/arm/mach-shmobile/board-lager.c | 22 ++++++++++++++++++++++
> >> >  1 file changed, 22 insertions(+)
> >> >
> >> > diff --git a/arch/arm/mach-shmobile/board-lager.c
> >> > b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..4d1b42b 100644
> >> > --- a/arch/arm/mach-shmobile/board-lager.c
> >> > +++ b/arch/arm/mach-shmobile/board-lager.c
> >> > @@ -18,7 +18,10 @@
> >> >   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301
> >> > USA */
> >> >
> >> > +#include <linux/gpio.h>
> >> > +#include <linux/gpio_keys.h>
> >> >  #include <linux/interrupt.h>
> >> > +#include <linux/input.h>
> >>
> >> My dictionary lists input before interrupt :-)
> >
> > Thanks, I will fix that.
> >
> >> >  #include <linux/irqchip.h>
> >> >  #include <linux/kernel.h>
> >> >  #include <linux/leds.h>
> >> > @@ -52,6 +55,22 @@ static struct gpio_led_platform_data lager_leds_pdata = {
> >> > .num_leds   = ARRAY_SIZE(lager_leds),
> >> >  };
> >> >
> >> > +/* GPIO KEY */
> >> > +#define GPIO_KEY(c, g, d, ...) \
> >> > +   { .code = c, .gpio = g, .desc = d, .active_low = 1 }
> >> > +
> >> > +static struct gpio_keys_button gpio_buttons[] = {
> >> > +   GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
> >> > +   GPIO_KEY(KEY_3,         RCAR_GP_PIN(1, 26),     "SW2-pin3"),
> >> > +   GPIO_KEY(KEY_2,         RCAR_GP_PIN(1, 24),     "SW2-pin2"),
> >> > +   GPIO_KEY(KEY_1,         RCAR_GP_PIN(1, 14),     "SW2-pin1"),
> >> > +};
> >> > +
> >> > +static struct gpio_keys_platform_data lager_keys_pdata = {
> >> > +   .buttons        = gpio_buttons,
> >> > +   .nbuttons       = ARRAY_SIZE(gpio_buttons),
> >> > +};
> >> > +
> >>
> >> Could you please also update the lager dts file ?
> >
> > I wonder if in that case we can remove the C code above.
> > And probably the C code for the GPIO leds too.
> >
> > Magnus, could you clarify how you would like
> > C-code and DTS to look on the lager board?
> 
> I'd like C and DTS to coexist in parallel until we can ditch C fully.
> I believe there is a need for us to be able to back port the C code.
> For the future we want to use DTS.
> 
> To support DTS for Lager I think you should create a -reference DTS
> file for Lager where you put the DT version of your GPIO LED / switch
> code. At the time when we can configure the PFC via PINCTRL DT then I
> believe we should be able to replace most of the platform device code
> with DT versions. At that we should hopefully be able to ditch all the
> C board code, or maybe we need to keep some around until we have the
> common clocks going...

Hi Magnus,

thanks for the clarification. That all sounds reasonable
and I will see about making it so.


From linus.walleij at linaro.org  Tue May 14 04:40:10 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:40:10 +0200
Subject: [PATCH 8/9] pinctrl: abx500: Rejiggle platform data and DT
 initialisation
In-Reply-To: <1368019749-19455-9-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-9-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZTU1gv3onjFF4eqxv-o1BQwd48u4gQ9NWqryWoMiKTDQ@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> A pointer to GPIO platform data is always passed to the driver now, so
> there's little point in checking for 'pdata' and executing the DT case if
> it's not there. The difference between booting with DT and !DT is when
> booting with DT, plat_id is not populated. Thus, in the DT case we have
> to use a DT match table in order to find out which platform we're
> executing on. So, we're changing the semantics here to only use the
> match table if no plat_id is supplied though platform data.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Is this really included in the [0/9] fire alarm wrapper statement
"Important ux500 fixups due for the v3.10 -rc:s"?

It seems more like a random refactoring to me.

The commit message fails to specify which regression this
is fixing, like if it's causing an oops or so.

So I've tentatively applied it to the pinctrl devel branch for
v3.11 unless something comes up...

Yours,
Linus Walleij


From shawn.guo at linaro.org  Tue May 14 04:44:32 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 May 2013 16:44:32 +0800
Subject: [GIT PULL] ARM: imx: fixes for 3.10
Message-ID: <20130514084430.GC16250@S2101-09.ap.freescale.net>

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.linaro.org/people/shawnguo/linux-2.6.git tags/imx-fixes-3.10

for you to fetch changes up to de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0:

  ARM: imx: fix typo in gpu3d_shader_sels (2013-05-12 21:39:51 +0800)

----------------------------------------------------------------
The imx fixes for 3.10:

* A few imx6 clock fixes.  Nothing is extremely important, but since
  we're still in early -rc, I send them for 3.10 inclusion.

* Having bootloader handle ARM errata, we will need to replicate the
  diagnostic register of boot cpu into secondary cores, since
  bootloader only sets up boot cpu.  Otherwise, errata workaround simply
  does not work.

----------------------------------------------------------------
Dirk Behme (1):
      ARM i.MX6: correct MLB clock configuration

Philipp Zabel (1):
      ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks

Shawn Guo (2):
      ARM: imx: replicate the diagnostic register of boot cpu into secondary cores
      ARM: imx: fix typo in gpu3d_shader_sels

 arch/arm/mach-imx/clk-imx6q.c |   11 ++++++-----
 arch/arm/mach-imx/headsmp.S   |   12 ++++++++++++
 arch/arm/mach-imx/platsmp.c   |   14 ++++++++++++++
 3 files changed, 32 insertions(+), 5 deletions(-)



From lee.jones at linaro.org  Tue May 14 04:45:37 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 09:45:37 +0100
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <CACRpkdaWaEct1My5=gZ7Bbbizqsr3BBNSXiahMn3bS7L-SubLg@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
 <CACRpkdaWaEct1My5=gZ7Bbbizqsr3BBNSXiahMn3bS7L-SubLg@mail.gmail.com>
Message-ID: <20130514084537.GD3297@gmail.com>

> > First Ethernet device has a ".0" appended onto the device name. It
> > appears that we need this in order to obtain the correct clock.
> >
> > Cc: Ulf Hansson <ulf.hansson at linaro.org>
> > Cc: Mike Turquette <mturquette at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>

> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>

Post -rc1 poke for Mike.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Tue May 14 04:46:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:46:58 +0200
Subject: [PATCH 9/9] mfd: ab8500-core: Pass GPADC compatible string to MFD
 core
In-Reply-To: <1368019749-19455-10-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-10-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY8SLRR0HQvD5AFUeNeeHRVt3XM-MOkwJs_h_EfeRctKw@mail.gmail.com>

On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:

> When booting with Device Tree enabled the MFD core uses each device's
> compatible string to find and allocate its associated of_node pointer,
> which in turn is passed to the driver via the platform_device struct.
> Without it, the driver won't be able to interrogate the Device Tree or
> locate suitable regulators and will most likely fail to probe.
>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Can you explain what regression this is causing since the GPADC
driver (drivers/mfd/ab8500-gpadc.c) does not support device tree
probing and does not have an .of_match_table defined in it's
driver struct? I mean, what could possibly match that
compatible string? The .name field will take care of naming
the device does it not?

For non-emergency merging though:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Since it matches the example in
Documentation/devicetree/bindings/mfd/ab8500.txt

But for this to make sense the AB8500 ADC driver needs
to be augmented for DT probing and preferrably also moved
to drivers/adc and made to utilize that subsystem.

Yours,
Linus Walleij


From lee.jones at linaro.org  Tue May 14 04:47:56 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 09:47:56 +0100
Subject: [PATCH 8/9] pinctrl: abx500: Rejiggle platform data and DT
 initialisation
In-Reply-To: <CACRpkdZTU1gv3onjFF4eqxv-o1BQwd48u4gQ9NWqryWoMiKTDQ@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZTU1gv3onjFF4eqxv-o1BQwd48u4gQ9NWqryWoMiKTDQ@mail.gmail.com>
Message-ID: <20130514084756.GE3297@gmail.com>

On Tue, 14 May 2013, Linus Walleij wrote:

> On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > A pointer to GPIO platform data is always passed to the driver now, so
> > there's little point in checking for 'pdata' and executing the DT case if
> > it's not there. The difference between booting with DT and !DT is when
> > booting with DT, plat_id is not populated. Thus, in the DT case we have
> > to use a DT match table in order to find out which platform we're
> > executing on. So, we're changing the semantics here to only use the
> > match table if no plat_id is supplied though platform data.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Is this really included in the [0/9] fire alarm wrapper statement
> "Important ux500 fixups due for the v3.10 -rc:s"?
> 
> It seems more like a random refactoring to me.
> 
> The commit message fails to specify which regression this
> is fixing, like if it's causing an oops or so.
> 
> So I've tentatively applied it to the pinctrl devel branch for
> v3.11 unless something comes up...

Perhaps the commit message is a bit weak, but yes, it _needs_ to go
into v3.10, or this driver will be _broken_ when we boot with DT.

Please apply this to your -fixes branch.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Tue May 14 04:48:54 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 09:48:54 +0100
Subject: [PATCH 6/9] ARM: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <CACRpkdYz0HcdBovoJu6O-4QyRbXz93MaeWwAwCohbE8rv=8O7Q@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-7-git-send-email-lee.jones@linaro.org>
 <CACRpkdYz0HcdBovoJu6O-4QyRbXz93MaeWwAwCohbE8rv=8O7Q@mail.gmail.com>
Message-ID: <20130514084854.GF3297@gmail.com>

On Tue, 14 May 2013, Linus Walleij wrote:

> On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > First Ethernet device has a ".0" appended onto the device name. It
> > appears that we need this in order to obtain the correct clock.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> (...)
> > -       OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
> > +       OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
> 
> I guess what you want to say in the commit message is that
> on a non-DT boot the ethernet will be named "smsc911x.0"
> and since the clocks are not converted to device tree these
> names need to be matched when providing the name from
> auxdata.
> 
> Edited the commit message and applied!

Thanks for the effort. :)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Tue May 14 04:49:14 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:49:14 +0200
Subject: [PATCH] mfd: ab8500-sysctrl: Always enable pm_power_off handler
In-Reply-To: <1368097688-17858-1-git-send-email-fabio.baltieri@linaro.org>
References: <1368097688-17858-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <CACRpkdYXAB03=bqAQ8OZ8wZ7Q9j+LwH-Uwtijw49OjXt70yiXQ@mail.gmail.com>

On Thu, May 9, 2013 at 1:08 PM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:

> AB8500 sysctrl driver implements a pm_power_off handler, but that is
> currently not registered until a specific platform data field is
> enabled.
>
> This patch drops the platform data field and always registers
> ab8500_power_off if no other pm_power_off handler was defined before,
> and also introduces the necessary cleanup code in the driver's remove
> function.
>
> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 04:50:51 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 10:50:51 +0200
Subject: [PATCH 8/9] pinctrl: abx500: Rejiggle platform data and DT
 initialisation
In-Reply-To: <20130514084756.GE3297@gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZTU1gv3onjFF4eqxv-o1BQwd48u4gQ9NWqryWoMiKTDQ@mail.gmail.com>
 <20130514084756.GE3297@gmail.com>
Message-ID: <CACRpkdbhHnrN3MGufubyYLNXdcCgZ2OpQ4a2CG6bwPJk88DZRg@mail.gmail.com>

On Tue, May 14, 2013 at 10:47 AM, Lee Jones <lee.jones at linaro.org> wrote:
> On Tue, 14 May 2013, Linus Walleij wrote:
>
>> On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > A pointer to GPIO platform data is always passed to the driver now, so
>> > there's little point in checking for 'pdata' and executing the DT case if
>> > it's not there. The difference between booting with DT and !DT is when
>> > booting with DT, plat_id is not populated. Thus, in the DT case we have
>> > to use a DT match table in order to find out which platform we're
>> > executing on. So, we're changing the semantics here to only use the
>> > match table if no plat_id is supplied though platform data.
>> >
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> Is this really included in the [0/9] fire alarm wrapper statement
>> "Important ux500 fixups due for the v3.10 -rc:s"?
>>
>> It seems more like a random refactoring to me.
>>
>> The commit message fails to specify which regression this
>> is fixing, like if it's causing an oops or so.
>>
>> So I've tentatively applied it to the pinctrl devel branch for
>> v3.11 unless something comes up...
>
> Perhaps the commit message is a bit weak, but yes, it _needs_ to go
> into v3.10, or this driver will be _broken_ when we boot with DT.
>
> Please apply this to your -fixes branch.

Quting myself from above:
  "The commit message fails to specify which regression this
  is fixing, like if it's causing an oops or so."

I'm happy to apply it but what do I write in the commit message?

Yours,
Linus Walleij


From srinivas.kandagatla at st.com  Tue May 14 04:46:38 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Tue, 14 May 2013 09:46:38 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>
Message-ID: <5191F9EE.6070008@st.com>

Thankyou for the comments.

On 13/05/13 20:05, Linus Walleij wrote:
> On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
> <srinivas.kandagatla at st.com> wrote:
> 
> Thomas Gleixner and John Stultz should always be included on timer code review.
> 
> This is one reason I really like to move the clocksource/clockevent/etc code out
> of arch/arm, so that people can get their To: line right from MAINTAINERS.
> (Whether it goes to drivers/clocksource or not is another issue.)
> 
>> diff --git a/arch/arm/include/asm/global_timer.h b/arch/arm/include/asm/global_timer.h
> 
> Using CLKSRC_OF_INIT() this header goes away entirely I guess.
> 
>> diff --git a/arch/arm/kernel/global_timer.c b/arch/arm/kernel/global_timer.c
> 
>> +#define GT_COUNTER0    0x00
>> +#define GT_COUNTER1    0x04
> 
> So two counters, nice.
> 
>> +union gt_counter {
>> +       cycle_t cycles;
>> +       struct {
>> +               uint32_t lower;
>> +               uint32_t upper;
> 
> Just u32 is fine.

It makes sense to remove this struct totally and use u64 as suggested.

> 
>> +       };
>> +};
>> +
>> +static union gt_counter gt_counter_read(void)
>> +{
>> +       union gt_counter res;
>> +       uint32_t upper;
> 
> u32
> 
>> +
>> +       upper = readl(gt_base + GT_COUNTER1);
>> +       do {
>> +               res.upper = upper;
>> +               res.lower = readl(gt_base + GT_COUNTER0);
>> +               upper = readl(gt_base + GT_COUNTER1);
>> +       } while (upper != res.upper);
>> +
>> +       return res;
>> +}
> 
> I guess this is some cleverness to avoid wrap-around...
> A comment stating what's going on wouldn't hurt.

This cleverness is defined in the datasheet
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407i/CIHGECHJ.html


I will add a comment here.

> 
> But why on earth do you need this complicated union
> to hold the result? Have two local u32 variables and return
> a u64 from this function.
> 
> Since this will be performance critical, isn't readl_relaxed() suffient
> here, or what's the rationale for just using readl()?

Yes, it makes sense to go for readl_relaxed here as it is device-memory
type.

> 
>> +static void gt_compare_set(unsigned long delta, int periodic)
>> +{
>> +       union gt_counter counter = gt_counter_read();
> 
> So here you get something easy to read like
> 
> u64 counter = gt_counter_read();
> 
>> +       unsigned long ctrl = readl(gt_base + GT_CONTROL);
>> +
>> +       BUG_ON(!(ctrl & GT_CONTROL_TIMER_ENABLE));
>> +       BUG_ON(ctrl & (GT_CONTROL_COMP_ENABLE |
>> +                      GT_CONTROL_IRQ_ENABLE |
>> +                      GT_CONTROL_AUTO_INC));
> 
> Do you really have to check this *whenever the counter is set*?
> 
> Will it not suffice to do this once during initialization?
> 
> It looks like some leftover debug code. It also looks kind of clock
> dangerous, can you explain exactly why this check is here?

I will get this debug out of here.

> 
>> +
>> +       counter.cycles += delta;
>> +       writel(counter.lower, gt_base + GT_COMP0);
>> +       writel(counter.upper, gt_base + GT_COMP1);
> 
> This is another instance of the union struct making things
> complicated. With a u64 just:
> 
> counter += delta;
> writel(lower_32_bits(counter), gt_base + GT_COMP0);
> writel(upper_32_bits(counter), gt_base + GT_COMP1);
> 
> As you can see <linux/kernel.h> has really nice helpers in place
> to deal with 64 bit arithmetics.
Same as first comment.

> 
>> +
>> +       ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
>> +
>> +       if (periodic) {
>> +               writel(delta, gt_base + GT_AUTO_INC);
>> +               ctrl |= GT_CONTROL_AUTO_INC;
>> +       }
>> +
>> +       writel(ctrl, gt_base + GT_CONTROL);
>> +}
>> +
>> +static void gt_clockevent_set_mode(enum clock_event_mode mode,
>> +                                  struct clock_event_device *clk)
>> +{
>> +       switch (mode) {
>> +       case CLOCK_EVT_MODE_PERIODIC:
>> +               gt_compare_set(gt_clk_rate/HZ, 1);
> 
> Use
> gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
> to get integer arithmetics right.

Will move to use DIV_ROUND_CLOSEST.
> 
>> +               break;
>> +       case CLOCK_EVT_MODE_ONESHOT:
>> +               /* period set, and timer enabled in 'next_event' hook */
>> +               BUG_ON(readl(gt_base + GT_CONTROL) &
>> +                      (GT_CONTROL_COMP_ENABLE |
>> +                       GT_CONTROL_IRQ_ENABLE |
>> +                       GT_CONTROL_AUTO_INC));
> 
> Here is another one of these checks. Why aren't you just
> zeroing these flags if you don't want them, especially since
> you're writing the register at the end of the function? Now it
> looks like instead of setting up the timer the way you want it
> you bug out if it isn't already set up as you want it (hint,
> the name of this function).
> 
>> +               /* Fall through */
>> +       case CLOCK_EVT_MODE_UNUSED:
>> +       case CLOCK_EVT_MODE_SHUTDOWN:
>> +       default:
>> +               writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
> 
> Why are you enabling the timer in unused and shutdown mode?
> 
> This doesn't make sense.

It is because we are using the global-timer block for both clocksource
and clockevents and we do not want the clocksource to disappear when
clockevent is unused/shutdown.

> 
>> +               break;
>> +       }
>> +}
>> +
>> +static int gt_clockevent_set_next_event(unsigned long evt,
>> +                                       struct clock_event_device *unused)
>> +{
>> +       gt_compare_set(evt, 0);
>> +       return 0;
>> +}
>> +
>> +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
>> +{
>> +       struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
>> +
>> +       writel(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
> 
> You're clearing the flag before checking if it was set. What happens
> if this was a spurious interrupt that should be disregarded?

Makes sense, I will add a check here.

> 
>> +       evt->event_handler(evt);
>> +
>> +       return IRQ_HANDLED;
>> +}
>> +
>> +static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
>> +{
>> +       struct clock_event_device **this_cpu_clk;
>> +       int cpu = smp_processor_id();
>> +
>> +       clk->name = "Global Timer CE";
> 
> Name it after the hardware feature. "ARM global timer clock event"
> there is no need to abbreviate randomly.

Yes, will change all such instances.

> 
>> +       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
>> +       clk->set_mode = gt_clockevent_set_mode;
>> +       clk->set_next_event = gt_clockevent_set_next_event;
>> +       this_cpu_clk = __this_cpu_ptr(gt_evt);
>> +       *this_cpu_clk = clk;
>> +       clk->irq = gt_ppi;
>> +       clockevents_config_and_register(clk, gt_clk_rate,
>> +                                       0xf, 0xffffffff);
> 
> Why can't this clock event handle anything lower than 0xf?
> Does that come from the datasheet or have you just copied some
> code?
There is no such limitation on the minimum clock ticks, I think it was
copied.

Will fix it in next version.

> 
> Further, since this clock event hardware *most definately* supports
> using a delta upper bound *beyond* 32 bits, I think the clock event
> core code should be altered to allow for registereing such clock
> events, but TGLX may have some idea here. This will work but will
> not expose the full potential of this 64-bit counter hardware.
> 
>> +       per_cpu(percpu_init_called, cpu) = true;
>> +       enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
>> +       return 0;
>> +}
>> +
>> +static void gt_clockevents_stop(struct clock_event_device *clk)
>> +{
>> +       gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
>> +       disable_percpu_irq(clk->irq);
>> +}
>> +
>> +static int __cpuinit gt_clockevents_setup(struct clock_event_device *clk)
>> +{
>> +       int cpu = smp_processor_id();
>> +
>> +       /* Use existing clock_event for boot cpu */
>> +       if (per_cpu(percpu_init_called, cpu))
>> +               return 0;
>> +
>> +       writel(0, gt_base + GT_CONTROL);
>> +       writel(0, gt_base + GT_COUNTER0);
>> +       writel(0, gt_base + GT_COUNTER1);
>> +       writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
>> +
>> +       return gt_clockevents_init(clk);
>> +}
>> +
>> +static cycle_t gt_clocksource_read(struct clocksource *cs)
>> +{
>> +       union gt_counter res = gt_counter_read();
>> +       return res.cycles;
>> +}
>> +
>> +static struct clocksource gt_clocksource = {
>> +       .name   = "Global Timer CS",
> 
> "ARM global timer clock source"
> 
>> +       .rating = 300,
>> +       .read   = gt_clocksource_read,
>> +       .mask   = CLOCKSOURCE_MASK(64),
>> +       .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
>> +};
>> +
>> +static void __init gt_clocksource_init(void)
>> +{
>> +       writel(0, gt_base + GT_CONTROL);
>> +       writel(0, gt_base + GT_COUNTER0);
>> +       writel(0, gt_base + GT_COUNTER1);
>> +       writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
>> +
>> +       gt_clocksource.shift = 20;
> 
> So how did you come up with that?
Hmm..
You are right, this should not be a constant here, I will use
clocksource_register_hz instead.

-srini

> 
>> +       gt_clocksource.mult =
>> +               clocksource_hz2mult(gt_clk_rate, gt_clocksource.shift);
>> +       clocksource_register(&gt_clocksource);
> 
> Why don't you just replace all of this hazzle with:
> 
> clocksource_register_hz(&gt_clocksource, gt_clk_rate);
> 
> That will calculate mult and shift for you? (Leave these
> unassigned.)
> 
> Since the hpet timer does this it's pretty well tested...
> 
> No more comments right now...
> 
> Yours,
> Linus Walleij
> 
> 



From linus.walleij at linaro.org  Tue May 14 05:01:34 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 11:01:34 +0200
Subject: [PATCH] mmc: sdhci-sirf: let device core setup the default pin
 configuration
In-Reply-To: <1368510549-7230-1-git-send-email-Baohua.Song@csr.com>
References: <1368510549-7230-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <CACRpkdY_Y1JWxS5QfPKwpt6nMvWzuYK4g=MX=ztsxNTE8dqyaA@mail.gmail.com>

On Tue, May 14, 2013 at 7:49 AM, Barry Song <Baohua.Song at csr.com> wrote:

> With device core now able to setup the default pin configuration, the call
> to devm_pinctrl_get_select_default can be removed. And the pin configuration
> code based on the deprecated Samsung specific gpio bindings is also removed.
>
> CC: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

Also delete this line:
#include <linux/pinctrl/consumer.h>

After that: Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 05:07:14 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 11:07:14 +0200
Subject: [PATCH] pinctrl: vt8500: Fix incorrect data in WM8750 pinctrl
 table
In-Reply-To: <1368207956-32220-1-git-send-email-linux@prisktech.co.nz>
References: <1368207956-32220-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <CACRpkdZC4RC-OnGJYNooRRoc7q5d1x8PH26+cnwBHw8ppzynEg@mail.gmail.com>

On Fri, May 10, 2013 at 7:45 PM, Tony Prisk <linux at prisktech.co.nz> wrote:

> WMT_PIN_WAKEUP1 should be declared as WMT_PIN(0, 17) rather than
> WMT_PIN(0, 16). This currently generates a runtime warning because
> WMT_PIN_WAKEUP0 is already defined as WMT_PIN(0, 16).
>
> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>

Applied to my fixes branch.

Yours,
Linus Walleij


From Baohua.Song at csr.com  Tue May 14 05:08:31 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Tue, 14 May 2013 17:08:31 +0800
Subject: [PATCH v2] mmc: sdhci-sirf: let device core setup the default pin
 configuration
Message-ID: <1368522511-26491-1-git-send-email-Baohua.Song@csr.com>

With device core now able to setup the default pin configuration, the call
to devm_pinctrl_get_select_default can be removed. And the pin configuration
code based on the deprecated Samsung specific gpio bindings is also removed.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2:
 delete "#include <linux/pinctrl/consumer.h>"

 drivers/mmc/host/sdhci-sirf.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 09805af..ccf12dd 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -13,7 +13,6 @@
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/mmc/slot-gpio.h>
-#include <linux/pinctrl/consumer.h>
 #include "sdhci-pltfm.h"
 
 struct sdhci_sirf_priv {
@@ -46,15 +45,8 @@ static int sdhci_sirf_probe(struct platform_device *pdev)
 	struct sdhci_host *host;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct sdhci_sirf_priv *priv;
-	struct pinctrl *pinctrl;
 	int ret;
 
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl)) {
-		dev_err(&pdev->dev, "unable to get pinmux");
-		return PTR_ERR(pinctrl);
-	}
-
 	priv = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_sirf_priv),
 		GFP_KERNEL);
 	if (!priv) {
-- 
1.7.4.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From nicolas.ferre at atmel.com  Tue May 14 05:16:10 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 May 2013 11:16:10 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some
 SoC
In-Reply-To: <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
Message-ID: <519200DA.8060102@atmel.com>

On 13/05/2013 18:05, Jean-Christophe PLAGNIOL-VILLARD :
>
> On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>
>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>> introduces clear-on-write on ISR register. This behavior is not always
>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>> We are using a new Device Tree compatibility string and a capability
>> property to actually activate this clear-on-write behavior on ISR.
>>
>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>
> can we detect it via the IP?

As said by Hein, we cannot use the IP revision number. *But* we may have 
the opportunity to read this integration configuration in the Design 
Configuration Register 1 (DCFG1 already used for determining data bus 
width).

So, Michal or Steffen, can you please tell me the value of:
-> bit 23 at register address 0x280: mine is "1" which should mean "IRQ 
read clear", yours should be "0".

Hein, in case of use of the MACB, we do not have this register included, 
so I will avoid to run the test when using MACB (we already have this 
information).

If it works, I plan to rewrite the patch but taking this information 
instead of the device tree compatibility string.

Best regards,

>> ---
>> Documentation/devicetree/bindings/net/macb.txt |  2 ++
>> drivers/net/ethernet/cadence/macb.c            | 15 +++++++++++++--
>> drivers/net/ethernet/cadence/macb.h            |  5 +++++
>> 3 files changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
>> index 44afa0e..13ec4f6 100644
>> --- a/Documentation/devicetree/bindings/net/macb.txt
>> +++ b/Documentation/devicetree/bindings/net/macb.txt
>> @@ -6,6 +6,8 @@ Required properties:
>>    Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
>>    Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
>>    the Cadence GEM, or the generic form: "cdns,gem".
>> +  Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative
>> +  options enabled (ISR clear on write).
>> - reg: Address and length of the register set for the device
>> - interrupts: Should contain macb interrupt
>> - phy-mode: String, operation mode of the PHY interface.
>> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
>> index 6be513d..628f2b0 100644
>> --- a/drivers/net/ethernet/cadence/macb.c
>> +++ b/drivers/net/ethernet/cadence/macb.c
>> @@ -485,7 +485,8 @@ static void macb_tx_interrupt(struct macb *bp)
>> 	status = macb_readl(bp, TSR);
>> 	macb_writel(bp, TSR, status);
>>
>> -	macb_writel(bp, ISR, MACB_BIT(TCOMP));
>> +	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
>> +		macb_writel(bp, ISR, MACB_BIT(TCOMP));
>>
>> 	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
>> 		(unsigned long)status);
>> @@ -738,7 +739,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
>> 			 * now.
>> 			 */
>> 			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
>> -			macb_writel(bp, ISR, MACB_BIT(RCOMP));
>> +			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
>> +				macb_writel(bp, ISR, MACB_BIT(RCOMP));
>>
>> 			if (napi_schedule_prep(&bp->napi)) {
>> 				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
>> @@ -1474,6 +1476,10 @@ static const struct of_device_id macb_dt_ids[] = {
>> 	{ .compatible = "cdns,macb" },
>> 	{ .compatible = "cdns,pc302-gem" },
>> 	{ .compatible = "cdns,gem" },
>> +	{
>> +		.compatible = "cdns,zynq-7000-gem",
>> +		.data = (void *)MACB_CAPS_ISR_CLEAR_ON_WRITE,
>> +	},
>> 	{ /* sentinel */ }
>> };
>> MODULE_DEVICE_TABLE(of, macb_dt_ids);
>> @@ -1484,6 +1490,7 @@ static int __init macb_probe(struct platform_device *pdev)
>> 	struct macb_platform_data *pdata;
>> 	struct resource *regs;
>> 	struct net_device *dev;
>> +	const struct of_device_id *dev_id;
>> 	struct macb *bp;
>> 	struct phy_device *phydev;
>> 	u32 config;
>> @@ -1558,6 +1565,10 @@ static int __init macb_probe(struct platform_device *pdev)
>>
>> 	dev->base_addr = regs->start;
>>
>> +	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
>> +	if (dev_id)
>> +		bp->caps = (u32)dev_id->data;
>> +
>> 	/* Set MII management clock divider */
>> 	config = macb_mdc_clk_div(bp);
>> 	config |= macb_dbw(bp);
>> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
>> index 993d703..5d622fe 100644
>> --- a/drivers/net/ethernet/cadence/macb.h
>> +++ b/drivers/net/ethernet/cadence/macb.h
>> @@ -323,6 +323,9 @@
>> #define MACB_MAN_READ				2
>> #define MACB_MAN_CODE				2
>>
>> +/* Capability mask bits */
>> +#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x1
>> +
>> /* Bit manipulation macros */
>> #define MACB_BIT(name)					\
>> 	(1 << MACB_##name##_OFFSET)
>> @@ -574,6 +577,8 @@ struct macb {
>> 	unsigned int 		speed;
>> 	unsigned int 		duplex;
>>
>> +	u32			caps;
>> +
>> 	phy_interface_t		phy_interface;
>>
>> 	/* AT91RM9200 transmit */
>> --
>> 1.8.0
>>
>
>


-- 
Nicolas Ferre


From 21cnbao at gmail.com  Tue May 14 05:16:29 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 14 May 2013 17:16:29 +0800
Subject: [RFC PATCH v3 11/17] ARM: dts: prima2: cpus/cpu node dts updates
In-Reply-To: <1366824502-19729-12-git-send-email-lorenzo.pieralisi@arm.com>
References: <1366824502-19729-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1366824502-19729-12-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <CAGsJ_4yudJGYqb_uc7=ZKw++g=wnoa4=8ExW_jhY=UF8N4P_jw@mail.gmail.com>

2013/4/25 Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>

Acked-by: Barry Song <Baohua.Song at csr.com>

> ---
>  arch/arm/boot/dts/prima2.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
> index 3329719..02edd89 100644
> --- a/arch/arm/boot/dts/prima2.dtsi
> +++ b/arch/arm/boot/dts/prima2.dtsi
> @@ -18,6 +18,8 @@
>                 #size-cells = <0>;
>
>                 cpu at 0 {
> +                       compatible = "arm,cortex-a9";
> +                       device_type = "cpu";
>                         reg = <0x0>;
>                         d-cache-line-size = <32>;
>                         i-cache-line-size = <32>;
> --


From 21cnbao at gmail.com  Tue May 14 05:17:48 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 14 May 2013 17:17:48 +0800
Subject: [PATCH 11/14] ARM: sirf: Remove init_irq declaration in machine
 description
In-Reply-To: <1368438253-28218-12-git-send-email-maxime.ripard@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-12-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CAGsJ_4wH2cEHdvzYUE4eeFbtr427kYdWFPDVR8DZ_-s5=sG7wQ@mail.gmail.com>

2013/5/13 Maxime Ripard <maxime.ripard at free-electrons.com>:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for sirf as well.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Acked-by: Barry Song <Baohua.Song at csr.com>

> ---
>  arch/arm/mach-prima2/common.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
> index 4f94cd8..52e28cf 100644
> --- a/arch/arm/mach-prima2/common.c
> +++ b/arch/arm/mach-prima2/common.c
> @@ -55,7 +55,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
>         /* Maintainer: Barry Song <baohua.song at csr.com> */
>         .nr_irqs        = 128,
>         .map_io         = sirfsoc_map_io,
> -       .init_irq       = irqchip_init,
>         .init_time      = sirfsoc_init_time,
>         .init_machine   = sirfsoc_mach_init,
>         .init_late      = sirfsoc_init_late,
> @@ -74,7 +73,6 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
>         /* Maintainer: Barry Song <baohua.song at csr.com> */
>         .nr_irqs        = 128,
>         .map_io         = sirfsoc_map_io,
> -       .init_irq       = irqchip_init,
>         .init_time      = sirfsoc_init_time,
>         .dma_zone_size  = SZ_256M,
>         .init_machine   = sirfsoc_mach_init,
> @@ -94,7 +92,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
>         /* Maintainer: Barry Song <baohua.song at csr.com> */
>         .smp            = smp_ops(sirfsoc_smp_ops),
>         .map_io         = sirfsoc_map_io,
> -       .init_irq       = irqchip_init,
>         .init_time      = sirfsoc_init_time,
>         .init_machine   = sirfsoc_mach_init,
>         .init_late      = sirfsoc_init_late,
> --
> 1.8.1.2


From nicolas.ferre at atmel.com  Tue May 14 05:20:00 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 May 2013 11:20:00 +0200
Subject: [RFC PATCH v3 05/17] ARM: dts: at91: cpus/cpu node dts updates
In-Reply-To: <517E4366.4040209@atmel.com>
References: <1366824502-19729-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1366824502-19729-6-git-send-email-lorenzo.pieralisi@arm.com>
 <517E4366.4040209@atmel.com>
Message-ID: <519201C0.2060908@atmel.com>

On 29/04/2013 11:54, Nicolas Ferre :
> On 04/24/2013 07:28 PM, Lorenzo Pieralisi :
>> This patch updates the in-kernel dts files according to the latest cpus
>> and cpu bindings updates for ARM.
>>
>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
>
> With changes in compatible string... ok then.
>
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Now that our Cortex-A5 is in mainline, can you please update the:

arch/arm/boot/dts/sama5d3.dtsi

as-well?

Thanks, best regards,

>> ---
>>   arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
>>   arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
>>   6 files changed, 35 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
>> index b0268a5..f16b3d4 100644
>> --- a/arch/arm/boot/dts/at91rm9200.dtsi
>> +++ b/arch/arm/boot/dts/at91rm9200.dtsi
>> @@ -34,8 +34,12 @@
>>   		ssc2 = &ssc2;
>>   	};
>>   	cpus {
>> -		cpu at 0 {
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>>   			compatible = "arm,arm920t";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
>> index cb7bcc5..c4eeef7 100644
>> --- a/arch/arm/boot/dts/at91sam9260.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
>> @@ -32,8 +32,12 @@
>>   		ssc0 = &ssc0;
>>   	};
>>   	cpus {
>> -		cpu at 0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
>> index 271d4de..f3b5c2a 100644
>> --- a/arch/arm/boot/dts/at91sam9263.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
>> @@ -29,8 +29,12 @@
>>   		ssc1 = &ssc1;
>>   	};
>>   	cpus {
>> -		cpu at 0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
>> index 6b1d4ca..6c18bd3 100644
>> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
>> @@ -35,8 +35,12 @@
>>   		ssc1 = &ssc1;
>>   	};
>>   	cpus {
>> -		cpu at 0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
>> index 7750f98..c3b11af 100644
>> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
>> @@ -31,8 +31,12 @@
>>   		ssc0 = &ssc0;
>>   	};
>>   	cpus {
>> -		cpu at 0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
>> index aa98e64..6c39d0f 100644
>> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
>> @@ -33,8 +33,12 @@
>>   		ssc0 = &ssc0;
>>   	};
>>   	cpus {
>> -		cpu at 0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>>
>
>


-- 
Nicolas Ferre


From lee.jones at linaro.org  Tue May 14 05:19:56 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 10:19:56 +0100
Subject: [GIT PULL] MFD: Fixes due for the v3.10 -rc:s
Message-ID: <20130514091956.GG3297@gmail.com>

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.linaro.org/people/ljones/mfd.git for-mfd-fixes

for you to fetch changes up to bc475aeb21c85f956c98014cae887f311c68b192:

  mfd: db8500-prcmu: Supply the pdata_size attribute for db8500-thermal (2013-05-14 09:58:15 +0100)

----------------------------------------------------------------
Arnd Bergmann (1):
      mfd: ab8500: Debugfs code depends on gpadc

Fabio Baltieri (4):
      mfd: abx500-core: Fix sparse warning
      mfd: ab8500-sysctrl: Fix sparse warning
      mfd: ab8500-sysctrl: Set sysctrl_dev during probe
      mfd: ab8500-sysctrl: Let sysctrl driver work without pdata

Lee Jones (3):
      mfd: ab8500-gpadc: Suppress 'ignoring regulator_enable() return value' warning
      mfd: ab8500-core: Use the correct driver name when enabling gpio/pinctrl
      mfd: db8500-prcmu: Supply the pdata_size attribute for db8500-thermal

Linus Walleij (1):
      mfd: ab8500: Pass AB8500 IRQ to debugfs code by resource

 drivers/mfd/Kconfig          |    2 +-
 drivers/mfd/ab8500-core.c    |   21 ++++++++++++++++++---
 drivers/mfd/ab8500-debugfs.c |   16 ++++++++++++----
 drivers/mfd/ab8500-gpadc.c   |    7 +++++--
 drivers/mfd/ab8500-sysctrl.c |    9 +++++----
 drivers/mfd/abx500-core.c    |    2 +-
 drivers/mfd/db8500-prcmu.c   |    1 +
 7 files changed, 43 insertions(+), 15 deletions(-)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From laurent.pinchart at ideasonboard.com  Tue May 14 05:21:39 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 11:21:39 +0200
Subject: [PATCH v2 2/3] ARM: shmobile: lager: enable Ether
In-Reply-To: <1368499171-22427-3-git-send-email-horms+renesas@verge.net.au>
References: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
 <1368499171-22427-3-git-send-email-horms+renesas@verge.net.au>
Message-ID: <9708378.xkqng7A9dx@avalon>

Hi Simon,

Thank you for the patch.

On Tuesday 14 May 2013 11:39:30 Simon Horman wrote:
> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

Is there any ongoing work on DT bindings for sh-eth ?

> ---
> 
> This patch has a build-time dependency on "sh_eth: add support for gpio
> reset". This patch has a run-time dependency on "sh_eth: add support for
> r8a7790 SoC".
> 
> v2
> * As suggested by Laurent Pinchart
>   - Do not manipilate sh_eth reset GPIO directly,
>     rather, do so through newly proposed support for this in
>     the sh_eth driver.
> * A suggested by Sergei Shtylyov
>   - Move DTS portion into a separate patch
> ---
>  arch/arm/mach-shmobile/board-lager.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/board-lager.c
> b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..c06f0da 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
> @@ -18,6 +18,7 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> +#include <linux/gpio.h>
>  #include <linux/interrupt.h>
>  #include <linux/irqchip.h>
>  #include <linux/kernel.h>
> @@ -52,6 +53,17 @@ static struct gpio_led_platform_data lager_leds_pdata = {
> .num_leds	= ARRAY_SIZE(lager_leds),
>  };
> 
> +/* Ether */
> +static struct sh_eth_plat_data ether_platdata = {
> +	.phy			= 0x1,
> +	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
> +	.register_type		= SH_ETH_REG_FAST_RCAR,
> +	.phy_interface		= PHY_INTERFACE_MODE_RMII,
> +	.ether_link_active_low	= 1,
> +	.needs_gpio_reset	= 1,
> +	.reset_gpio		= RCAR_GP_PIN(5, 31),
> +};
> +
>  static const struct pinctrl_map lager_pinctrl_map[] = {
>  	/* SCIF0 (CN19: DEBUG SERIAL0) */
>  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
> @@ -59,6 +71,17 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
>  	/* SCIF1 (CN20: DEBUG SERIAL1) */
>  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
>  				  "scif1_data", "scif1"),
> +	/* Ether */
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_link", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_magic", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_mdio", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "eth_rmii", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7790",
> +				  "intc_irq0", "intc"),
>  };
> 
>  static void __init lager_add_standard_devices(void)
> @@ -73,6 +96,8 @@ static void __init lager_add_standard_devices(void)
>  	platform_device_register_data(&platform_bus, "leds-gpio", -1,
>  				      &lager_leds_pdata,
>  				      sizeof(lager_leds_pdata));
> +
> +	r8a7790_add_ether_device(&ether_platdata);
>  }
> 
>  static const char *lager_boards_compat_dt[] __initdata = {

-- 
Regards,

Laurent Pinchart



From linus.walleij at linaro.org  Tue May 14 05:23:56 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 11:23:56 +0200
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <5191F9EE.6070008@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>
 <5191F9EE.6070008@st.com>
Message-ID: <CACRpkdYh72hQHSK-a9r8R9qfnQv06412YqVNeYpc_rZhMeiXww@mail.gmail.com>

On Tue, May 14, 2013 at 10:46 AM, Srinivas KANDAGATLA
<srinivas.kandagatla at st.com> wrote:
> On 13/05/13 20:05, Linus Walleij wrote:

>> Why are you enabling the timer in unused and shutdown mode?
>>
>> This doesn't make sense.
>
> It is because we are using the global-timer block for both clocksource
> and clockevents and we do not want the clocksource to disappear when
> clockevent is unused/shutdown.

As this is clearly a per-cpu timer (correct? atleast the driver is
written that way) and say you have 4 CPUs, why would you not shut down
the timer on cores 1,2,3 and only leave the timer on core 0 on?

The kernel will by necessity not shut down the clock event on core
0 anyway.

On a related note: don't you want to use the counter in this block as
sched_clock() as well? (I guess so, as you do not seem to have
anything else on this system.) It'd probably need to be a separate
Kconfig option and can surely be done later but keep it in mind.

Yours,
Linus Walleij


From laurent.pinchart at ideasonboard.com  Tue May 14 05:24:48 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 11:24:48 +0200
Subject: [PATCH 3/3] ARM: mach-shmobile: lager: support GPIO switches
In-Reply-To: <CANqRtoTj+FnxrtOayxQYCxkyuP4XGeCaXpNUbPsFV4kyBD_48Q@mail.gmail.com>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <20130514025941.GC20239@verge.net.au>
 <CANqRtoTj+FnxrtOayxQYCxkyuP4XGeCaXpNUbPsFV4kyBD_48Q@mail.gmail.com>
Message-ID: <18009427.QVeP3MCVSV@avalon>

Hi Magnus,

On Tuesday 14 May 2013 15:09:08 Magnus Damm wrote:
> On Tue, May 14, 2013 at 11:59 AM, Simon Horman <horms at verge.net.au> wrote:
> > On Tue, May 14, 2013 at 12:35:20AM +0200, Laurent Pinchart wrote:
> >> On Monday 13 May 2013 17:53:53 Simon Horman wrote:
> >> > The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
> >> > This patch allows access to those pins as KEYS 1 - 4 using
> >> > gpio-keys.
> >> > 
> >> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >> > 
> >> > ---
> >> > 
> >> > This patch has run time dependencies on
> >> > 1. "gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH"
> >> > 2. "ARM: shmobile: r8a7790: Configure R-Car GPIO for
> >> > IRQ_TYPE_EDGE_BOTH"
> >> > 
> >> > Without those dependencies satisfied the gpio-keys driver will
> >> > fail to be initialise itself. The boot should be otherwise successful
> >> > and the board otherwise functional.
> >> > ---
> >> > 
> >> >  arch/arm/mach-shmobile/board-lager.c | 22 ++++++++++++++++++++++
> >> >  1 file changed, 22 insertions(+)
> >> > 
> >> > diff --git a/arch/arm/mach-shmobile/board-lager.c
> >> > b/arch/arm/mach-shmobile/board-lager.c index 6a1ba38..4d1b42b 100644
> >> > --- a/arch/arm/mach-shmobile/board-lager.c
> >> > +++ b/arch/arm/mach-shmobile/board-lager.c
> >> > @@ -18,7 +18,10 @@
> >> > 
> >> >   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 
> >> >   02110-1301
> >> > 
> >> > USA */
> >> > 
> >> > +#include <linux/gpio.h>
> >> > +#include <linux/gpio_keys.h>
> >> > 
> >> >  #include <linux/interrupt.h>
> >> > 
> >> > +#include <linux/input.h>
> >> 
> >> My dictionary lists input before interrupt :-)
> > 
> > Thanks, I will fix that.
> > 
> >> >  #include <linux/irqchip.h>
> >> >  #include <linux/kernel.h>
> >> >  #include <linux/leds.h>
> >> > 
> >> > @@ -52,6 +55,22 @@ static struct gpio_led_platform_data
> >> > lager_leds_pdata = { .num_leds   = ARRAY_SIZE(lager_leds),
> >> > 
> >> >  };
> >> > 
> >> > +/* GPIO KEY */
> >> > +#define GPIO_KEY(c, g, d, ...) \
> >> > +   { .code = c, .gpio = g, .desc = d, .active_low = 1 }
> >> > +
> >> > +static struct gpio_keys_button gpio_buttons[] = {
> >> > +   GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
> >> > +   GPIO_KEY(KEY_3,         RCAR_GP_PIN(1, 26),     "SW2-pin3"),
> >> > +   GPIO_KEY(KEY_2,         RCAR_GP_PIN(1, 24),     "SW2-pin2"),
> >> > +   GPIO_KEY(KEY_1,         RCAR_GP_PIN(1, 14),     "SW2-pin1"),
> >> > +};
> >> > +
> >> > +static struct gpio_keys_platform_data lager_keys_pdata = {
> >> > +   .buttons        = gpio_buttons,
> >> > +   .nbuttons       = ARRAY_SIZE(gpio_buttons),
> >> > +};
> >> > +
> >> 
> >> Could you please also update the lager dts file ?
> > 
> > I wonder if in that case we can remove the C code above.
> > And probably the C code for the GPIO leds too.
> > 
> > Magnus, could you clarify how you would like
> > C-code and DTS to look on the lager board?
> 
> I'd like C and DTS to coexist in parallel until we can ditch C fully.
> I believe there is a need for us to be able to back port the C code.
> For the future we want to use DTS.
> 
> To support DTS for Lager I think you should create a -reference DTS
> file for Lager where you put the DT version of your GPIO LED / switch
> code. At the time when we can configure the PFC via PINCTRL DT then I
> believe we should be able to replace most of the platform device code
> with DT versions.

I've sent an RFC for gpio-rcar DT bindings, and I'll send one for sh-pfc in 
the next few days. DT support for GPIO and PINCTRL should then hopefully be 
available very soon.

> At that we should hopefully be able to ditch all the C board code,

Will we also ditch non-reference board files ?

> or maybe we need to keep some around until we have the common clocks
> going...

What's the status of CCF support development in sh-mobile ?

-- 
Regards,

Laurent Pinchart



From lee.jones at linaro.org  Tue May 14 05:26:14 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 10:26:14 +0100
Subject: [PATCH 9/9] mfd: ab8500-core: Pass GPADC compatible string to
 MFD core
In-Reply-To: <CACRpkdY8SLRR0HQvD5AFUeNeeHRVt3XM-MOkwJs_h_EfeRctKw@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-10-git-send-email-lee.jones@linaro.org>
 <CACRpkdY8SLRR0HQvD5AFUeNeeHRVt3XM-MOkwJs_h_EfeRctKw@mail.gmail.com>
Message-ID: <20130514092614.GH3297@gmail.com>

On Tue, 14 May 2013, Linus Walleij wrote:

> On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > When booting with Device Tree enabled the MFD core uses each device's
> > compatible string to find and allocate its associated of_node pointer,
> > which in turn is passed to the driver via the platform_device struct.
> > Without it, the driver won't be able to interrogate the Device Tree or
> > locate suitable regulators and will most likely fail to probe.
> >
> > Cc: Samuel Ortiz <sameo at linux.intel.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Can you explain what regression this is causing since the GPADC
> driver (drivers/mfd/ab8500-gpadc.c) does not support device tree

Yes it does. :)

> probing and does not have an .of_match_table defined in it's
> driver struct? I mean, what could possibly match that
> compatible string? The .name field will take care of naming
> the device does it not?

You only need that stuff if you require _extra_ bindings. Things like
regulators and interrupt numbers are configured behind the scenes.

> For non-emergency merging though:
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

If we don't put this into v3.10-rcX, then the GPADC driver will be
broken in v3.10 when booting with DT.

> Since it matches the example in
> Documentation/devicetree/bindings/mfd/ab8500.txt
> 
> But for this to make sense the AB8500 ADC driver needs
> to be augmented for DT probing and preferrably also moved
> to drivers/adc and made to utilize that subsystem.

Not sure I understand the reasoning for this. It works well as a plain
MFD device.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From anup.patel at linaro.org  Tue May 14 05:26:54 2013
From: anup.patel at linaro.org (Anup Patel)
Date: Tue, 14 May 2013 14:56:54 +0530
Subject: [PATCH] arm64: mm: Fix operands of clz in __flush_dcache_all
Message-ID: <1368523614-22484-1-git-send-email-anup.patel@linaro.org>

From: Sukanto Ghosh <sghosh at apm.com>

The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is
unchanged from ARMv7 architecture and the upper bits are RES0. This
implies that the 'way' field of the operand of 'dc cisw' occupies the
bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands
to 'clz', the existing implementation of __flush_dcache_all is incorrectly
placing the 'way' field in the bit-positions [63 .. (64-A)].

Signed-off-by: Sukanto Ghosh <sghosh at apm.com>
Tested-by: Anup Patel <anup.patel at linaro.org>
---
 arch/arm64/mm/cache.S |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index abe69b8..48a3860 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -52,7 +52,7 @@ loop1:
 	add	x2, x2, #4			// add 4 (line length offset)
 	mov	x4, #0x3ff
 	and	x4, x4, x1, lsr #3		// find maximum number on the way size
-	clz	x5, x4				// find bit position of way size increment
+	clz	w5, w4				// find bit position of way size increment
 	mov	x7, #0x7fff
 	and	x7, x7, x1, lsr #13		// extract max number of the index size
 loop2:
-- 
1.7.9.5



From linus.walleij at linaro.org  Tue May 14 05:29:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 11:29:12 +0200
Subject: GPIO sysfs : set a wake source
In-Reply-To: <87fvxwia0s.fsf@free.fr>
References: <87fvxwia0s.fsf@free.fr>
Message-ID: <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>

On Thu, May 9, 2013 at 2:59 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:

> I was thinking on how to remove all "gpio_request()" from my board code
> (arch/arm/mach-pxa/mioa701.c).
>
> I have a small difficulty with the functionality provided by gpiolib in
> userspace. This is what I need :
>  - define a gpio as an input
>  - define this gpio to be an interrupt source
>  - define this interrupt to be a wake-up source

This sounds like trying to remove board code by moving it to userspace
and basically starting to implement stuff that belongs in the kernel
in userspace just because someone says we should get rid of board
files :-)

Don't go down this path, let the kernel handle this kind of stuff.

Instead figure out how to make the subsystems we have and the
device trees express what you want to do.

In another thread I suggested that we add a GPIO "hogging"
mechanism to gpiolib, so that the gpio subsystem can by itself
"hog" (get) some GPIOs and set them up in certain modes.
This closely matches what the pin control subsystem will do
with some such things.

What do you think about this idea?

Yours,
Linus Walleij


From catalin.marinas at arm.com  Tue May 14 05:31:08 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 May 2013 10:31:08 +0100
Subject: arm64: Platform devices populated from a device_initcall
In-Reply-To: <519112E7.3040309@synopsys.com>
References: <519112E7.3040309@synopsys.com>
Message-ID: <20130514093108.GA15129@arm.com>

Hi Benoit,

On Mon, May 13, 2013 at 05:20:55PM +0100, Benoit Lecardonnel wrote:
> In the arm64 kernel, function arm64_device_probe 
> (arch/arm64/kernel/setup.c) is in charge of populating the platform 
> devices defined by the device tree.
> 
> Does anyone know why arm64_device_probe is a device_initcall?

It had to be somewhere after arch_initcall used by vexpress clocks
(but now I do it in arm64_of_clk_init()). The of_clk_init needs to be
after a core_inicall used by the vexpress sysreg initialisation.

> This seems to be in conflict with some I2C drivers: see 
> drivers/i2c/busses/i2c-designware-platdrv.c for example.
> The driver calls platform_driver_probe from a subsys_initcall.
> The probe fails because subsys_initcalls are executed before 
> device_initcalls.

Ah, this driver doesn't use platform_driver_register() but probe
directly, so it needs the platform devices to be populated.

> Maybe arm64_device_probe could be an arch_initcall?

I think we could put of_clk_init() and of_platform_populate() calls
under the same arch_initcall() just to keep their relative order.
Something like this (could even use arch_initcall_sync in case we get
some other arch_initcall in the future):


diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 6a9a532..add6ea6 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -282,12 +282,13 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
-static int __init arm64_of_clk_init(void)
+static int __init arm64_device_init(void)
 {
 	of_clk_init(NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	return 0;
 }
-arch_initcall(arm64_of_clk_init);
+arch_initcall(arm64_device_init);
 
 static DEFINE_PER_CPU(struct cpu, cpu_data);
 
@@ -305,13 +306,6 @@ static int __init topology_init(void)
 }
 subsys_initcall(topology_init);
 
-static int __init arm64_device_probe(void)
-{
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-	return 0;
-}
-device_initcall(arm64_device_probe);
-
 static const char *hwcap_str[] = {
 	"fp",
 	"asimd",


From Baohua.Song at csr.com  Tue May 14 05:32:03 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Tue, 14 May 2013 17:32:03 +0800
Subject: [PATCH] arm: prima2: use of_platform_populate instead of
 of_platform_bus_probe
Message-ID: <1368523923-27137-1-git-send-email-Baohua.Song@csr.com>

use of_platform_populate to populate platform devices, it is suitable
for creating devices which are children of the root node, then makes
things like pcm work.

Signed-off-by: Barry Song <Baohua.Song at csr.com>
Signed-off-by: Rongjun Ying <Rongjun.Ying at csr.com>
---
 arch/arm/mach-prima2/common.c |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd8..bb67b90 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -17,14 +17,9 @@
 #include <linux/of_platform.h>
 #include "common.h"
 
-static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
-	{ .compatible = "simple-bus", },
-	{},
-};
-
 void __init sirfsoc_mach_init(void)
 {
-	of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 void __init sirfsoc_init_late(void)
-- 
1.7.4.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From pebolle at tiscali.nl  Tue May 14 05:34:45 2013
From: pebolle at tiscali.nl (Paul Bolle)
Date: Tue, 14 May 2013 11:34:45 +0200
Subject: [PATCH] ARM: mach-bcm: drop "select GPIO_BCM"
Message-ID: <1368524085.1350.102.camel@x61.thuisdomein>

A select statement for the Kconfig symbol GPIO_BCM was added in v3.8.
But there's no symbol with that name. It's a nop so we can drop it.

Signed-off-by: Paul Bolle <pebolle at tiscali.nl>
---
0) Untested.

1) Patch assumes that https://lkml.org/lkml/2013/3/6/182 ("ARM:
mach-bcm: drop "select GENERIC_TIME""), which got a Reviewed-by tag from
Christian, was applied first.

 arch/arm/mach-bcm/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 764273e..322620d 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -8,7 +8,6 @@ config ARCH_BCM
 	select CPU_V7
 	select CLKSRC_OF
 	select GENERIC_CLOCKEVENTS
-	select GPIO_BCM
 	select SPARSE_IRQ
 	select TICK_ONESHOT
 	help
-- 
1.7.11.7



From lorenzo.pieralisi at arm.com  Tue May 14 05:34:40 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Tue, 14 May 2013 10:34:40 +0100
Subject: [RFC PATCH v3 05/17] ARM: dts: at91: cpus/cpu node dts updates
In-Reply-To: <519201C0.2060908@atmel.com>
References: <1366824502-19729-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1366824502-19729-6-git-send-email-lorenzo.pieralisi@arm.com>
 <517E4366.4040209@atmel.com> <519201C0.2060908@atmel.com>
Message-ID: <20130514093440.GA27767@e102568-lin.cambridge.arm.com>

On Tue, May 14, 2013 at 10:20:00AM +0100, Nicolas Ferre wrote:
> On 29/04/2013 11:54, Nicolas Ferre :
> > On 04/24/2013 07:28 PM, Lorenzo Pieralisi :
> >> This patch updates the in-kernel dts files according to the latest cpus
> >> and cpu bindings updates for ARM.
> >>
> >> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> >
> > With changes in compatible string... ok then.
> >
> > Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> 
> Now that our Cortex-A5 is in mainline, can you please update the:
> 
> arch/arm/boot/dts/sama5d3.dtsi
> 
> as-well?

I will, no problems.

> Thanks, best regards,

Cheers,
Lorenzo

> 
> >> ---
> >>   arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
> >>   arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
> >>   6 files changed, 35 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
> >> index b0268a5..f16b3d4 100644
> >> --- a/arch/arm/boot/dts/at91rm9200.dtsi
> >> +++ b/arch/arm/boot/dts/at91rm9200.dtsi
> >> @@ -34,8 +34,12 @@
> >>   		ssc2 = &ssc2;
> >>   	};
> >>   	cpus {
> >> -		cpu at 0 {
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >>   			compatible = "arm,arm920t";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> >> index cb7bcc5..c4eeef7 100644
> >> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> >> @@ -32,8 +32,12 @@
> >>   		ssc0 = &ssc0;
> >>   	};
> >>   	cpus {
> >> -		cpu at 0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
> >> index 271d4de..f3b5c2a 100644
> >> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> >> @@ -29,8 +29,12 @@
> >>   		ssc1 = &ssc1;
> >>   	};
> >>   	cpus {
> >> -		cpu at 0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> >> index 6b1d4ca..6c18bd3 100644
> >> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> >> @@ -35,8 +35,12 @@
> >>   		ssc1 = &ssc1;
> >>   	};
> >>   	cpus {
> >> -		cpu at 0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> >> index 7750f98..c3b11af 100644
> >> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> >> @@ -31,8 +31,12 @@
> >>   		ssc0 = &ssc0;
> >>   	};
> >>   	cpus {
> >> -		cpu at 0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> >> index aa98e64..6c39d0f 100644
> >> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> >> @@ -33,8 +33,12 @@
> >>   		ssc0 = &ssc0;
> >>   	};
> >>   	cpus {
> >> -		cpu at 0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >>
> >
> >
> 
> 
> -- 
> Nicolas Ferre
> 



From lee.jones at linaro.org  Tue May 14 05:40:36 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 10:40:36 +0100
Subject: [PATCH 8/9] pinctrl: abx500: Rejiggle platform data and DT
 initialisation
In-Reply-To: <CACRpkdbhHnrN3MGufubyYLNXdcCgZ2OpQ4a2CG6bwPJk88DZRg@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZTU1gv3onjFF4eqxv-o1BQwd48u4gQ9NWqryWoMiKTDQ@mail.gmail.com>
 <20130514084756.GE3297@gmail.com>
 <CACRpkdbhHnrN3MGufubyYLNXdcCgZ2OpQ4a2CG6bwPJk88DZRg@mail.gmail.com>
Message-ID: <20130514094036.GI3297@gmail.com>

On Tue, 14 May 2013, Linus Walleij wrote:

> On Tue, May 14, 2013 at 10:47 AM, Lee Jones <lee.jones at linaro.org> wrote:
> > On Tue, 14 May 2013, Linus Walleij wrote:
> >
> >> On Wed, May 8, 2013 at 3:29 PM, Lee Jones <lee.jones at linaro.org> wrote:
> >>
> >> > A pointer to GPIO platform data is always passed to the driver now, so
> >> > there's little point in checking for 'pdata' and executing the DT case if
> >> > it's not there. The difference between booting with DT and !DT is when
> >> > booting with DT, plat_id is not populated. Thus, in the DT case we have
> >> > to use a DT match table in order to find out which platform we're
> >> > executing on. So, we're changing the semantics here to only use the
> >> > match table if no plat_id is supplied though platform data.
> >> >
> >> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >>
> >> Is this really included in the [0/9] fire alarm wrapper statement
> >> "Important ux500 fixups due for the v3.10 -rc:s"?
> >>
> >> It seems more like a random refactoring to me.
> >>
> >> The commit message fails to specify which regression this
> >> is fixing, like if it's causing an oops or so.
> >>
> >> So I've tentatively applied it to the pinctrl devel branch for
> >> v3.11 unless something comes up...
> >
> > Perhaps the commit message is a bit weak, but yes, it _needs_ to go
> > into v3.10, or this driver will be _broken_ when we boot with DT.
> >
> > Please apply this to your -fixes branch.
> 
> Quting myself from above:
>   "The commit message fails to specify which regression this
>   is fixing, like if it's causing an oops or so."
> 
> I'm happy to apply it but what do I write in the commit message?

Platform Data is invariably populated for this driver, even when
booting with Device Tree. Thus the Device Tree probing code encased
within the first check for Platform Data will never executed, causing
the driver to fail when DT is enabled.

This patch fixes the aforementioned regression by rejigging the
probe() semantics to attempt to extract a platform ID from Device Tree
if one can not be sourced from platform data.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From andrew at lunn.ch  Tue May 14 05:54:20 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 14 May 2013 11:54:20 +0200
Subject: [PATCHv2] mv643xx_eth: fix NAPI weight being > 64
Message-ID: <1368525260-17556-1-git-send-email-andrew@lunn.ch>

3.10-rc1 issues the following warning:

netif_napi_add() called with weight 128 on device eth%d

This patch reduce the weight to 64, using NAPI_POLL_WEIGHT.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
v1->v2: Use NAPI_POLL_WEIGHT.

 drivers/net/ethernet/marvell/mv643xx_eth.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index d0afeea..8f63c36 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2745,7 +2745,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
 	INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
 
-	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
+	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
 
 	init_timer(&mp->rx_oom);
 	mp->rx_oom.data = (unsigned long)mp;
-- 
1.7.10.4



From catalin.marinas at arm.com  Tue May 14 06:25:36 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 May 2013 11:25:36 +0100
Subject: [PATCH] arm64: mm: Fix operands of clz in __flush_dcache_all
In-Reply-To: <1368523614-22484-1-git-send-email-anup.patel@linaro.org>
References: <1368523614-22484-1-git-send-email-anup.patel@linaro.org>
Message-ID: <20130514102536.GD15129@arm.com>

On Tue, May 14, 2013 at 10:26:54AM +0100, Anup Patel wrote:
> From: Sukanto Ghosh <sghosh at apm.com>
> 
> The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is
> unchanged from ARMv7 architecture and the upper bits are RES0. This
> implies that the 'way' field of the operand of 'dc cisw' occupies the
> bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands
> to 'clz', the existing implementation of __flush_dcache_all is incorrectly
> placing the 'way' field in the bit-positions [63 .. (64-A)].
> 
> Signed-off-by: Sukanto Ghosh <sghosh at apm.com>
> Tested-by: Anup Patel <anup.patel at linaro.org>
> ---
>  arch/arm64/mm/cache.S |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> index abe69b8..48a3860 100644
> --- a/arch/arm64/mm/cache.S
> +++ b/arch/arm64/mm/cache.S
> @@ -52,7 +52,7 @@ loop1:
>  	add	x2, x2, #4			// add 4 (line length offset)
>  	mov	x4, #0x3ff
>  	and	x4, x4, x1, lsr #3		// find maximum number on the way size
> -	clz	x5, x4				// find bit position of way size increment
> +	clz	w5, w4				// find bit position of way size increment
>  	mov	x7, #0x7fff
>  	and	x7, x7, x1, lsr #13		// extract max number of the index size
>  loop2:

Good catch. I'll queue it for 3.10-rc2.

Thanks.

-- 
Catalin


From srinivas.kandagatla at st.com  Tue May 14 06:26:26 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Tue, 14 May 2013 11:26:26 +0100
Subject: [RFC 2/8] ARM:global_timer: Add ARM global timer support.
In-Reply-To: <CACRpkdYh72hQHSK-a9r8R9qfnQv06412YqVNeYpc_rZhMeiXww@mail.gmail.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022260-2197-1-git-send-email-srinivas.kandagatla@st.com>
 <CACRpkdZCP=w=4Q3bnuMQxm=Oe-uZke+Cc5NgddM5vsQbgr9E-Q@mail.gmail.com>
 <5191F9EE.6070008@st.com>
 <CACRpkdYh72hQHSK-a9r8R9qfnQv06412YqVNeYpc_rZhMeiXww@mail.gmail.com>
Message-ID: <51921152.1000600@st.com>

On 14/05/13 10:23, Linus Walleij wrote:
> On Tue, May 14, 2013 at 10:46 AM, Srinivas KANDAGATLA
> <srinivas.kandagatla at st.com> wrote:
>> On 13/05/13 20:05, Linus Walleij wrote:
> 
>>> Why are you enabling the timer in unused and shutdown mode?
>>>
>>> This doesn't make sense.
>>
>> It is because we are using the global-timer block for both clocksource
>> and clockevents and we do not want the clocksource to disappear when
>> clockevent is unused/shutdown.
> 
> As this is clearly a per-cpu timer (correct? atleast the driver is
> written that way) and say you have 4 CPUs, why would you not shut down
> the timer on cores 1,2,3 and only leave the timer on core 0 on?
> 
I think it makes sense to shutdown the timer on other cores on request.
I will fix this.

> The kernel will by necessity not shut down the clock event on core
> 0 anyway.
> 
> On a related note: don't you want to use the counter in this block as
> sched_clock() as well? (I guess so, as you do not seem to have
> anything else on this system.) It'd probably need to be a separate
> Kconfig option and can surely be done later but keep it in mind.
Thankyou for the advice,
I will definitely try to implement this.

Thanks,
srini
> 
> Yours,
> Linus Walleij
> 



From lee.jones at linaro.org  Tue May 14 06:46:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 11:46:31 +0100
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
Message-ID: <20130514104631.GA28781@gmail.com>

Hi Greg,

> drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
>         In function ?synaptics_rmi4_resume?:
> drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
>         warning: ignoring return value of ?regulator_enable?, declared
>         with attribute warn_unused_result [-Wunused-result
> 
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: devel at driverdev.osuosl.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> index fe667dd..c4d013d 100644
> --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> @@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
>  	unsigned char intr_status;
>  	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
>  
> -	regulator_enable(rmi4_data->regulator);
> +	retval = regulator_enable(rmi4_data->regulator);
> +	if (retval < 0)
> +		return retval;
>  
>  	enable_irq(rmi4_data->i2c_client->irq);
>  	rmi4_data->touch_stopped = false;

Are you planning to take this into the v3.10 -rcs?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From gregkh at linuxfoundation.org  Tue May 14 07:05:13 2013
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Tue, 14 May 2013 07:05:13 -0400
Subject: [PATCH 4/4] staging: =?utf-8?Q?ste=5Fr?=
 =?utf-8?Q?mi4=3A_Suppress_'ignoring_return_value_of_=E2=80=98regulator=5F?=
 =?utf-8?B?ZW5hYmxlKCkn?= warning
In-Reply-To: <20130514104631.GA28781@gmail.com>
References: <1367509690-24022-1-git-send-email-lee.jones@linaro.org>
 <1367509690-24022-5-git-send-email-lee.jones@linaro.org>
 <20130514104631.GA28781@gmail.com>
Message-ID: <20130514110513.GA10354@kroah.com>

On Tue, May 14, 2013 at 11:46:31AM +0100, Lee Jones wrote:
> Hi Greg,
> 
> > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:
> >         In function ?synaptics_rmi4_resume?:
> > drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c:1090:18:
> >         warning: ignoring return value of ?regulator_enable?, declared
> >         with attribute warn_unused_result [-Wunused-result
> > 
> > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > Cc: devel at driverdev.osuosl.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > index fe667dd..c4d013d 100644
> > --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
> > @@ -1087,7 +1087,9 @@ static int synaptics_rmi4_resume(struct device *dev)
> >  	unsigned char intr_status;
> >  	struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
> >  
> > -	regulator_enable(rmi4_data->regulator);
> > +	retval = regulator_enable(rmi4_data->regulator);
> > +	if (retval < 0)
> > +		return retval;
> >  
> >  	enable_irq(rmi4_data->i2c_client->irq);
> >  	rmi4_data->touch_stopped = false;
> 
> Are you planning to take this into the v3.10 -rcs?

Yes, I was, give me some time to catch up on my pending patch queue (644
patches and counting).  Don't worry, it's not lost.

thanks,

greg k-h


From linus.walleij at linaro.org  Tue May 14 07:06:29 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 13:06:29 +0200
Subject: [PATCH 9/9] mfd: ab8500-core: Pass GPADC compatible string to MFD
 core
In-Reply-To: <20130514092614.GH3297@gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-10-git-send-email-lee.jones@linaro.org>
 <CACRpkdY8SLRR0HQvD5AFUeNeeHRVt3XM-MOkwJs_h_EfeRctKw@mail.gmail.com>
 <20130514092614.GH3297@gmail.com>
Message-ID: <CACRpkdaiZNeh9u_e7wSkHPmrxfaFQLeQEpZXEV4f+rXCCpW_eg@mail.gmail.com>

On Tue, May 14, 2013 at 11:26 AM, Lee Jones <lee.jones at linaro.org> wrote:

>> probing and does not have an .of_match_table defined in it's
>> driver struct? I mean, what could possibly match that
>> compatible string? The .name field will take care of naming
>> the device does it not?
>
> You only need that stuff if you require _extra_ bindings. Things like
> regulators and interrupt numbers are configured behind the scenes.

Sure, but isn't the idea with of_match_table that this should be
used in drivers when probing from device tree?

Surely it *works* with other schemes but I always thought about
them as some kind of rough fallback hacks. I would be way more
convenient with the patch if it added an of_match_table to
the ADC driver as well, because then I understand what is
going on.

>> For non-emergency merging though:
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>
> If we don't put this into v3.10-rcX, then the GPADC driver will be
> broken in v3.10 when booting with DT.

OK I think I understand why now...

>> But for this to make sense the AB8500 ADC driver needs
>> to be augmented for DT probing and preferrably also moved
>> to drivers/adc and made to utilize that subsystem.
>
> Not sure I understand the reasoning for this. It works well as a plain
> MFD device.

The commit message says:
 "Without it, the driver won't be able to interrogate the Device Tree or
  locate suitable regulators and will most likely fail to probe."

That commit message makes it sound like the driver is
interrogating (hm is that the right term...) the device tree, but
now you say it isn't (as you say it is a plain MFD device).
Of course the MFD core and drivers/of/platform.c is doing
all sorts of magic based on the device tree, and that is
what the patch fixes, right? Nothing to do with the driver
really?

I suspect the missing regulators due to how the OF core or
MFD core uses the device tree is the actual problem
solved by the patch?

Anyway I think I was after this:

Isn't the idea that all devices that get probed from a device tree
shall have corresponding bindings documented under
Documentation/devicetree/bindings/*?

And this driver is definately in the wrong subsystem (not your
fault) so I suspect the binding doc should be in
Documentation/devicetree/bindings/adc/ab8500.txt or
something. I'm not pointing that out as a problem in this
patch, I'm just discussing the mess we're in ...

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 07:09:05 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 13:09:05 +0200
Subject: [PATCH 8/9] pinctrl: abx500: Rejiggle platform data and DT
 initialisation
In-Reply-To: <20130514094036.GI3297@gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZTU1gv3onjFF4eqxv-o1BQwd48u4gQ9NWqryWoMiKTDQ@mail.gmail.com>
 <20130514084756.GE3297@gmail.com>
 <CACRpkdbhHnrN3MGufubyYLNXdcCgZ2OpQ4a2CG6bwPJk88DZRg@mail.gmail.com>
 <20130514094036.GI3297@gmail.com>
Message-ID: <CACRpkda5v5BOidCNEnGK5TFyvbBd0R85Enu5hdhBzdjbn45BNw@mail.gmail.com>

On Tue, May 14, 2013 at 11:40 AM, Lee Jones <lee.jones at linaro.org> wrote:

>> I'm happy to apply it but what do I write in the commit message?
>
> Platform Data is invariably populated for this driver, even when
> booting with Device Tree. Thus the Device Tree probing code encased
> within the first check for Platform Data will never executed, causing
> the driver to fail when DT is enabled.
>
> This patch fixes the aforementioned regression by rejigging the
> probe() semantics to attempt to extract a platform ID from Device Tree
> if one can not be sourced from platform data.

Thanks!
Copy/pasted into commit message and applied to fixes.

Yours,
Linus Walleij


From marc.zyngier at arm.com  Tue May 14 07:11:35 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:35 +0100
Subject: [PATCH v3 2/7] ARM: KVM: remove dead prototype for
 __kvm_tlb_flush_vmid
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-3-git-send-email-marc.zyngier@arm.com>

__kvm_tlb_flush_vmid has been renamed to __kvm_tlb_flush_vmid_ipa,
and the old prototype should have been removed when the code was
modified.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_asm.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d5032..6ae3d2a 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -72,8 +72,6 @@ extern char __kvm_hyp_vector[];
 extern char __kvm_hyp_code_start[];
 extern char __kvm_hyp_code_end[];
 
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
-
 extern void __kvm_flush_vm_context(void);
 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
 
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:39 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:39 +0100
Subject: [PATCH v3 6/7] ARM: KVM: get rid of S2_PGD_SIZE
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-7-git-send-email-marc.zyngier@arm.com>

S2_PGD_SIZE defines the number of pages used by a stage-2 PGD
and is unused, except for a VM_BUG_ON check that missuses the
define.

As the check is very unlikely to ever triggered except in
circumstances where KVM is the least of our worries, just kill
both the define and the VM_BUG_ON check.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_arm.h | 1 -
 arch/arm/kvm/mmu.c             | 3 ---
 2 files changed, 4 deletions(-)

diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 124623e..64e9696 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -135,7 +135,6 @@
 #define KVM_PHYS_MASK	(KVM_PHYS_SIZE - 1ULL)
 #define PTRS_PER_S2_PGD	(1ULL << (KVM_PHYS_SHIFT - 30))
 #define S2_PGD_ORDER	get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
-#define S2_PGD_SIZE	(1 << S2_PGD_ORDER)
 
 /* Virtualization Translation Control Register (VTCR) bits */
 #define VTCR_SH0	(3 << 12)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 451bad3..693d16c 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -382,9 +382,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
 	if (!pgd)
 		return -ENOMEM;
 
-	/* stage-2 pgd must be aligned to its size */
-	VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
-
 	memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
 	kvm_clean_pgd(pgd);
 	kvm->arch.pgd = pgd;
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:37 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:37 +0100
Subject: [PATCH v3 4/7] ARM: KVM: use phys_addr_t instead of unsigned long
 long for HYP PGDs
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-5-git-send-email-marc.zyngier@arm.com>

HYP PGDs are passed around as phys_addr_t, except just before calling
into the hypervisor init code, where they are cast to a rather weird
unsigned long long.

Just keep them around as phys_addr_t, which is what makes the most
sense.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_host.h | 4 ++--
 arch/arm/kvm/arm.c              | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786..ff49193 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -190,8 +190,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
 		int exception_index);
 
-static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
-				       unsigned long long pgd_ptr,
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+				       phys_addr_t pgd_ptr,
 				       unsigned long hyp_stack_ptr,
 				       unsigned long vector_ptr)
 {
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 37d216d..327a1fb 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -789,8 +789,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 static void cpu_init_hyp_mode(void *dummy)
 {
-	unsigned long long boot_pgd_ptr;
-	unsigned long long pgd_ptr;
+	phys_addr_t boot_pgd_ptr;
+	phys_addr_t pgd_ptr;
 	unsigned long hyp_stack_ptr;
 	unsigned long stack_page;
 	unsigned long vector_ptr;
@@ -798,8 +798,8 @@ static void cpu_init_hyp_mode(void *dummy)
 	/* Switch from the HYP stub to our own HYP init vector */
 	__hyp_set_vectors(kvm_get_idmap_vector());
 
-	boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
-	pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+	boot_pgd_ptr = kvm_mmu_get_boot_httbr();
+	pgd_ptr = kvm_mmu_get_httbr();
 	stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
 	hyp_stack_ptr = stack_page + PAGE_SIZE;
 	vector_ptr = (unsigned long)__kvm_hyp_vector;
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:33 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:33 +0100
Subject: [PATCH v3 0/7] ARM: KVM: various mmu related fixes for 3.10
Message-ID: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>

This patch series fixes a number of of KVM/ARM issues that have either
been spotted during the review of the arm64 code, or while reworking
related code.

Only the first patch fixes a potential (if unlikely) problem, the
others are either cosmetic or performance related.

Tested on TC-2, based on 3.10-rc1.

* From v2:
  - [1/7] Drop the unnecessary "TLB invalidate all", as we already do
  it on a page-per-page level.
  - [3/7] Add a cache cleaning primitive, move the cleaning outside of
  kvm_set_pte(), and clean a range as large as possible when inserting
  PTEs.
  - [4,5,7/7] New patches

Marc Zyngier (7):
  ARM: KVM: be more thorough when invalidating TLBs
  ARM: KVM: remove dead prototype for __kvm_tlb_flush_vmid
  ARM: KVM: relax cache maintainance when building page tables
  ARM: KVM: use phys_addr_t instead of unsigned long long for HYP PGDs
  ARM: KVM: don't special case PC when doing an MMIO
  ARM: KVM: get rid of S2_PGD_SIZE
  ARM: KVM: drop use of PAGE_S2_DEVICE

 arch/arm/include/asm/kvm_arm.h     |  1 -
 arch/arm/include/asm/kvm_asm.h     |  2 --
 arch/arm/include/asm/kvm_emulate.h |  5 ----
 arch/arm/include/asm/kvm_host.h    |  4 +--
 arch/arm/include/asm/kvm_mmu.h     | 17 +++++++-----
 arch/arm/include/asm/pgtable.h     |  2 --
 arch/arm/kvm/arm.c                 |  8 +++---
 arch/arm/kvm/mmio.c                |  6 -----
 arch/arm/kvm/mmu.c                 | 53 ++++++++++++++++++++++----------------
 arch/arm/mm/mmu.c                  |  6 ++---
 10 files changed, 50 insertions(+), 54 deletions(-)

-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:34 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:34 +0100
Subject: [PATCH v3 1/7] ARM: KVM: be more thorough when invalidating TLBs
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-2-git-send-email-marc.zyngier@arm.com>

The KVM/ARM MMU code doesn't take care of invalidating TLBs before
freeing a {pte,pmd} table. This could cause problems if the page
is reallocated and then speculated into by another CPU.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kvm/mmu.c | 41 ++++++++++++++++++++++++++---------------
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 9657065..84ba67b 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -43,7 +43,14 @@ static phys_addr_t hyp_idmap_vector;
 
 static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
 {
-	kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
+	/*
+	 * This function also gets called when dealing with HYP page
+	 * tables. As HYP doesn't have an associated struct kvm (and
+	 * the HYP page tables are fairly static), we don't do
+	 * anything there.
+	 */
+	if (kvm)
+		kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
 }
 
 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
@@ -78,18 +85,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
 	return p;
 }
 
-static void clear_pud_entry(pud_t *pud)
+static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
 {
 	pmd_t *pmd_table = pmd_offset(pud, 0);
 	pud_clear(pud);
+	kvm_tlb_flush_vmid_ipa(kvm, addr);
 	pmd_free(NULL, pmd_table);
 	put_page(virt_to_page(pud));
 }
 
-static void clear_pmd_entry(pmd_t *pmd)
+static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
 {
 	pte_t *pte_table = pte_offset_kernel(pmd, 0);
 	pmd_clear(pmd);
+	kvm_tlb_flush_vmid_ipa(kvm, addr);
 	pte_free_kernel(NULL, pte_table);
 	put_page(virt_to_page(pmd));
 }
@@ -100,11 +109,12 @@ static bool pmd_empty(pmd_t *pmd)
 	return page_count(pmd_page) == 1;
 }
 
-static void clear_pte_entry(pte_t *pte)
+static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
 {
 	if (pte_present(*pte)) {
 		kvm_set_pte(pte, __pte(0));
 		put_page(virt_to_page(pte));
+		kvm_tlb_flush_vmid_ipa(kvm, addr);
 	}
 }
 
@@ -114,7 +124,8 @@ static bool pte_empty(pte_t *pte)
 	return page_count(pte_page) == 1;
 }
 
-static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
+static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
+			unsigned long long start, u64 size)
 {
 	pgd_t *pgd;
 	pud_t *pud;
@@ -138,15 +149,15 @@ static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
 		}
 
 		pte = pte_offset_kernel(pmd, addr);
-		clear_pte_entry(pte);
+		clear_pte_entry(kvm, pte, addr);
 		range = PAGE_SIZE;
 
 		/* If we emptied the pte, walk back up the ladder */
 		if (pte_empty(pte)) {
-			clear_pmd_entry(pmd);
+			clear_pmd_entry(kvm, pmd, addr);
 			range = PMD_SIZE;
 			if (pmd_empty(pmd)) {
-				clear_pud_entry(pud);
+				clear_pud_entry(kvm, pud, addr);
 				range = PUD_SIZE;
 			}
 		}
@@ -165,14 +176,14 @@ void free_boot_hyp_pgd(void)
 	mutex_lock(&kvm_hyp_pgd_mutex);
 
 	if (boot_hyp_pgd) {
-		unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
-		unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+		unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
+		unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
 		kfree(boot_hyp_pgd);
 		boot_hyp_pgd = NULL;
 	}
 
 	if (hyp_pgd)
-		unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+		unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
 
 	kfree(init_bounce_page);
 	init_bounce_page = NULL;
@@ -200,9 +211,10 @@ void free_hyp_pgds(void)
 
 	if (hyp_pgd) {
 		for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
-			unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+			unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
 		for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
-			unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+			unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+
 		kfree(hyp_pgd);
 		hyp_pgd = NULL;
 	}
@@ -393,7 +405,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
  */
 static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
 {
-	unmap_range(kvm->arch.pgd, start, size);
+	unmap_range(kvm, kvm->arch.pgd, start, size);
 }
 
 /**
@@ -675,7 +687,6 @@ static void handle_hva_to_gpa(struct kvm *kvm,
 static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
 {
 	unmap_stage2_range(kvm, gpa, PAGE_SIZE);
-	kvm_tlb_flush_vmid_ipa(kvm, gpa);
 }
 
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:40 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:40 +0100
Subject: [PATCH v3 7/7] ARM: KVM: drop use of PAGE_S2_DEVICE
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>

At the moment, when mapping a device into Stage-2 for a guest,
we override whatever the guest uses by forcing a device memory
type in Stage-2.

While this is not exactly wrong, this isn't really the "spirit" of
the architecture. The hardware shouldn't have to cope for a broken
guest mapping to a device as normal memory.

As such, let's get rid of the memory type overrides, and map
everything as PAGE_S2 in Stage-2. This simplifies the code and
let the guest do its own thing, whether it is stupid or not.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/pgtable.h | 2 --
 arch/arm/kvm/mmu.c             | 2 +-
 arch/arm/mm/mmu.c              | 6 ++----
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262..c3410a8 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -81,7 +81,6 @@ extern pgprot_t		pgprot_user;
 extern pgprot_t		pgprot_kernel;
 extern pgprot_t		pgprot_hyp_device;
 extern pgprot_t		pgprot_s2;
-extern pgprot_t		pgprot_s2_device;
 
 #define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))
 
@@ -97,7 +96,6 @@ extern pgprot_t		pgprot_s2_device;
 #define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_HYP)
 #define PAGE_HYP_DEVICE		_MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
 #define PAGE_S2			_MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
-#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
 
 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 693d16c..f2a8416 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -495,7 +495,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
 	pfn = __phys_to_pfn(pa);
 
 	for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
-		pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
+		pte_t pte = pfn_pte(pfn, PAGE_S2);
 		kvm_set_s2pte_writable(&pte);
 
 		ret = mmu_topup_memory_cache(&cache, 2, 2);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e0d8565..bc001f5 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -60,7 +60,6 @@ pgprot_t pgprot_user;
 pgprot_t pgprot_kernel;
 pgprot_t pgprot_hyp_device;
 pgprot_t pgprot_s2;
-pgprot_t pgprot_s2_device;
 
 EXPORT_SYMBOL(pgprot_user);
 EXPORT_SYMBOL(pgprot_kernel);
@@ -343,7 +342,7 @@ static void __init build_mem_type_table(void)
 	struct cachepolicy *cp;
 	unsigned int cr = get_cr();
 	pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
-	pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
+	pteval_t hyp_device_pgprot, s2_pgprot;
 	int cpu_arch = cpu_architecture();
 	int i;
 
@@ -456,7 +455,7 @@ static void __init build_mem_type_table(void)
 	cp = &cache_policies[cachepolicy];
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 	s2_pgprot = cp->pte_s2;
-	hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
+	hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
 
 	/*
 	 * ARMv6 and above have extended page tables.
@@ -536,7 +535,6 @@ static void __init build_mem_type_table(void)
 	pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 				 L_PTE_DIRTY | kern_pgprot);
 	pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
-	pgprot_s2_device  = __pgprot(s2_device_pgprot);
 	pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
 
 	mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:36 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:36 +0100
Subject: [PATCH v3 3/7] ARM: KVM: relax cache maintainance when building page
 tables
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-4-git-send-email-marc.zyngier@arm.com>

Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
introduced code that flushes page tables to the point of coherency.
This is overkill (point of unification is enough and already done),
and actually not required if running on a SMP capable platform
(the HW PTW can snoop other cpus' L1).

Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
a no-op for SMP ARMv7.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_mmu.h | 17 +++++++++++------
 arch/arm/kvm/mmu.c             |  7 ++++---
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 472ac70..8c03c96 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -65,11 +65,6 @@ void kvm_clear_hyp_idmap(void);
 static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
 {
 	pte_val(*pte) = new_pte;
-	/*
-	 * flush_pmd_entry just takes a void pointer and cleans the necessary
-	 * cache entries, so we can reuse the function for ptes.
-	 */
-	flush_pmd_entry(pte);
 }
 
 static inline bool kvm_is_write_fault(unsigned long hsr)
@@ -83,9 +78,19 @@ static inline bool kvm_is_write_fault(unsigned long hsr)
 		return true;
 }
 
+static inline void kvm_clean_dcache_area(void *addr, size_t size)
+{
+	clean_dcache_area(addr, size);
+}
+
+static inline void kvm_clean_pte_entry(pte_t *pte)
+{
+	kvm_clean_dcache_area(pte, sizeof(*pte));
+}
+
 static inline void kvm_clean_pgd(pgd_t *pgd)
 {
-	clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
+	kvm_clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
 }
 
 static inline void kvm_clean_pmd_entry(pmd_t *pmd)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 84ba67b..451bad3 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -113,6 +113,7 @@ static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
 {
 	if (pte_present(*pte)) {
 		kvm_set_pte(pte, __pte(0));
+		kvm_clean_pte_entry(pte);
 		put_page(virt_to_page(pte));
 		kvm_tlb_flush_vmid_ipa(kvm, addr);
 	}
@@ -234,9 +235,10 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
 		pte = pte_offset_kernel(pmd, addr);
 		kvm_set_pte(pte, pfn_pte(pfn, prot));
 		get_page(virt_to_page(pte));
-		kvm_flush_dcache_to_poc(pte, sizeof(*pte));
 		pfn++;
 	} while (addr += PAGE_SIZE, addr != end);
+
+	kvm_clean_dcache_area((void *)start, end - start);
 }
 
 static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
@@ -261,7 +263,6 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
 			}
 			pmd_populate_kernel(NULL, pmd, pte);
 			get_page(virt_to_page(pmd));
-			kvm_flush_dcache_to_poc(pmd, sizeof(*pmd));
 		}
 
 		next = pmd_addr_end(addr, end);
@@ -299,7 +300,6 @@ static int __create_hyp_mappings(pgd_t *pgdp,
 			}
 			pud_populate(NULL, pud, pmd);
 			get_page(virt_to_page(pud));
-			kvm_flush_dcache_to_poc(pud, sizeof(*pud));
 		}
 
 		next = pgd_addr_end(addr, end);
@@ -469,6 +469,7 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
 	/* Create 2nd stage page table mapping - Level 3 */
 	old_pte = *pte;
 	kvm_set_pte(pte, *new_pte);
+	kvm_clean_pte_entry(pte);
 	if (pte_present(old_pte))
 		kvm_tlb_flush_vmid_ipa(kvm, addr);
 	else
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 07:11:38 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 12:11:38 +0100
Subject: [PATCH v3 5/7] ARM: KVM: don't special case PC when doing an MMIO
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368529900-22572-6-git-send-email-marc.zyngier@arm.com>

Admitedly, reading a MMIO register to load PC is very weird.
Writing PC to a MMIO register is probably even worse. But
the architecture doesn't forbid any of these, and injecting
a Prefetch Abort is the wrong thing to do anyway.

Remove this check altogether, and let the adventurous guest
wander into LaLaLand if they feel compelled to do so.

Reported-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_emulate.h | 5 -----
 arch/arm/kvm/mmio.c                | 6 ------
 2 files changed, 11 deletions(-)

diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 82b4bab..a464e8d 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -65,11 +65,6 @@ static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
 	return cpsr_mode > USR_MODE;;
 }
 
-static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
-{
-	return reg == 15;
-}
-
 static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
 {
 	return vcpu->arch.fault.hsr;
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 72a12f2..b8e06b7 100644
--- a/arch/arm/kvm/mmio.c
+++ b/arch/arm/kvm/mmio.c
@@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
 	sign_extend = kvm_vcpu_dabt_issext(vcpu);
 	rt = kvm_vcpu_dabt_get_rd(vcpu);
 
-	if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
-		/* IO memory trying to read/write pc */
-		kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
-		return 1;
-	}
-
 	mmio->is_write = is_write;
 	mmio->phys_addr = fault_ipa;
 	mmio->len = len;
-- 
1.8.2.3




From linux at arm.linux.org.uk  Tue May 14 07:16:42 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 14 May 2013 12:16:42 +0100
Subject: [PATCH] arm: mm: Use phys_addr_t properly for ioremap functions
In-Reply-To: <20130502180237.GY14496@n2100.arm.linux.org.uk>
References: <1366761098-4485-1-git-send-email-lauraa@codeaurora.org>
 <20130502180237.GY14496@n2100.arm.linux.org.uk>
Message-ID: <20130514111642.GH18614@n2100.arm.linux.org.uk>

On Thu, May 02, 2013 at 07:02:37PM +0100, Russell King - ARM Linux wrote:
> On Tue, Apr 23, 2013 at 04:51:38PM -0700, Laura Abbott wrote:
> > -	unsigned long last_addr;
> > - 	unsigned long offset = phys_addr & ~PAGE_MASK;
> > +	phys_addr_t last_addr;
> > +	phys_addr_t offset = phys_addr & ~PAGE_MASK;
> 
> BTW, this doesn't need to be phys_addr_t.  An offset of a page is always
> less than 32-bits.

As I said to Arnd on the 2nd May, I've dropped this patch because it was
causing too many other problems.  I'd much prefer to have a single patch
which made this change and fixed all the other places which Arnd identified
as well.  If you still want to make this change, please ensure that all
implementations and users of ioremap() are correctly updated in a single
patch and resubmit.  Thanks.


From jonathan.austin at arm.com  Tue May 14 07:27:22 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:27:22 +0100
Subject: [PATCH v2 0/3] Separate generic header usage from ARCH_MULTIPLATFORM
Message-ID: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>

The original aim of this series was to restore the ability to build a NOMMU
kernel for Versatile Express, something that was lost when we converted
ARCH_VEXPRESS for ARCH_MULTIPLATFORM.

In order to do this, it is necessary to abstract the use of generic headers
from selection of ARCH_MULTIPLATFORM so that the two can be used separately.
This is necessary becuase building a multiplatform kernel for processors
without and MMU doesn't make sense (it is necessary to hardcode certain mem-map
related data) and the versatile express can host NOMMU processors.

This series performs this separation, and then goes on to add a 'dummy'
ARCH_VEXPRESS_NOMMU platform that can be selected as standalone platform.

Patch 2 was sent to the list as an RFC some time ago where it was ACKd, but
alone is not sufficient to solve the problem, hence this follow-up series.

Changes since V1:
 - Rebase on to 3.10-rc1: fixup conflict from CONFIG_UNCOMPRESS_INCLUDE-foo

Jonathan Austin (3):
  ARM: allow platforms to use generic headers without
    ARCH_MULTIPLATFORM
  ARM: nommu: re-enable use of vexpress without ARCH_MULTIPLATFORM
  ARM: vexpress-nommu: add a Makefile.boot to restore single-platform
    build

 arch/arm/Kconfig                     |   21 +++++++++++++++++++++
 arch/arm/Kconfig.debug               |    4 ++--
 arch/arm/Makefile                    |    2 +-
 arch/arm/include/asm/timex.h         |    2 +-
 arch/arm/mach-mvebu/Makefile         |    2 +-
 arch/arm/mach-omap2/Makefile         |    2 +-
 arch/arm/mach-vexpress/Makefile      |    2 +-
 arch/arm/mach-vexpress/Makefile.boot |    4 ++++
 arch/arm/plat-omap/Makefile          |    2 +-
 arch/arm/plat-orion/Makefile         |    2 +-
 arch/arm/plat-versatile/Makefile     |    2 +-
 11 files changed, 35 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mach-vexpress/Makefile.boot

-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:27:23 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:27:23 +0100
Subject: [PATCH v2 1/3] ARM: allow platforms to use generic headers without
 ARCH_MULTIPLATFORM
In-Reply-To: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>

Currently the use of generic mach headers is only is controlled by the same
config option as selection of a multiplatform kernel (i.e.
ARCH_MULTIPLATFORM). However, there are cases where it is valid to use the
generic headers but still build a single platform kernel.

One such example is when using the vexpress platform with a core that does
not have an MMU; a multiplatform kernel does not make sense, but use of the
generic headers is required by the vexpress platform since 617276307cd4c
("ARM: vexpress: convert to multi-platform").

This patch untangles these two options by introducing a new
ARM_GENERIC_HEADERS config option that ARCH_MULTIPLATFORM selects. Other
platforms can now select ARM_GENERIC_HEADERS independently.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
CC: Rob Herring <rob.herring at calxeda.com>
CC: Pawel Moll <pawel.moll at arm.com>
CC: Jason Cooper <jason at lakedaemon.net>
CC: Andrew Lunn <andrew at lunn.ch>
CC: Gregory Clement <gregory.clement at free-electrons.com>
CC: Tony Lindgren <tony at atomide.com>
CC: Stephen Boyd <sboyd at codeaurora.org>
CC: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig                 |    4 ++++
 arch/arm/Kconfig.debug           |    4 ++--
 arch/arm/Makefile                |    2 +-
 arch/arm/include/asm/timex.h     |    2 +-
 arch/arm/mach-mvebu/Makefile     |    2 +-
 arch/arm/mach-omap2/Makefile     |    2 +-
 arch/arm/mach-vexpress/Makefile  |    2 +-
 arch/arm/plat-omap/Makefile      |    2 +-
 arch/arm/plat-orion/Makefile     |    2 +-
 arch/arm/plat-versatile/Makefile |    2 +-
 10 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..408eb33 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -206,6 +206,9 @@ config NEED_RET_TO_USER
 config ARCH_MTD_XIP
 	bool
 
+config ARM_GENERIC_HEADERS
+	bool
+
 config VECTORS_BASE
 	hex
 	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
@@ -295,6 +298,7 @@ config ARCH_MULTIPLATFORM
 	select MULTI_IRQ_HANDLER
 	select SPARSE_IRQ
 	select USE_OF
+	select ARM_GENERIC_HEADERS
 
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908..ede909b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -652,13 +652,13 @@ config DEBUG_LL_INCLUDE
 
 config DEBUG_UNCOMPRESS
 	bool
-	default y if ARCH_MULTIPLATFORM && DEBUG_LL && \
+	default y if ARM_GENERIC_HEADERS && DEBUG_LL && \
 		     !DEBUG_OMAP2PLUS_UART && \
 		     !DEBUG_TEGRA_UART
 
 config UNCOMPRESS_INCLUDE
 	string
-	default "debug/uncompress.h" if ARCH_MULTIPLATFORM
+	default "debug/uncompress.h" if ARM_GENERIC_HEADERS
 	default "mach/uncompress.h"
 
 config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 4737408..ab0416f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -229,7 +229,7 @@ endif
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
 
-ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+ifneq ($(CONFIG_ARM_GENERIC_HEADERS),y)
 ifeq ($(KBUILD_SRC),)
 KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
 else
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 83f2aa8..586a9c2 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,7 +12,7 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
-#ifdef CONFIG_ARCH_MULTIPLATFORM
+#ifdef CONFIG_ARM_GENERIC_HEADERS
 #define CLOCK_TICK_RATE 1000000
 #else
 #include <mach/timex.h>
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 2d04f0e..d3c0e0b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,4 +1,4 @@
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
 	-I$(srctree)/arch/arm/plat-orion/include
 
 AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..ab204bc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
 	-I$(srctree)/arch/arm/plat-omap/include
 
 # Common support
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8..6768e7f 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux kernel.
 #
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
 	-I$(srctree)/arch/arm/plat-versatile/include
 
 obj-y					:= v2m.o
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 3119941..3e1ba10 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
+ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/arch/arm/plat-omap/include
 
 # Common support
 obj-y := sram.o dma.o counter_32k.o
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 9433605..79a042ed 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux kernel.
 #
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include
 
 orion-gpio-$(CONFIG_GPIOLIB)      += gpio.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index f88d448..19495c6 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,4 +1,4 @@
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include
 
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:27:24 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:27:24 +0100
Subject: [PATCH v2 2/3] ARM: nommu: re-enable use of vexpress without
 ARCH_MULTIPLATFORM
In-Reply-To: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368530845-7415-3-git-send-email-jonathan.austin@arm.com>

Since 617276307cd4c ("ARM: vexpress: convert to multi-platform") it has been
impossible to select ARCH_VEXPRESS without ARCH_MULTIPLATFORM.

ARCH_MULTIPLATFORM doesn't make sense for NOMMU targets, not least because
of the need to hard-code the memory map. However, it should still be
possible to run NOMMU kernels on top of the Versatile Express by selecting
it as the only platform.

This patch creates a shim ARCH_VEXPRESS_NOMMU config option in the 'choice'
for "ARM system type" to make this possible again.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Acked-by: Nicolas Pitre <nico at fluxnic.net>
Acked-by: Arnd Bergmann <arnd at arndb.de>
CC: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/Kconfig |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 408eb33..541d90e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,6 +350,23 @@ config ARCH_VERSATILE
 	help
 	  This enables support for ARM Ltd Versatile board.
 
+config ARCH_VEXPRESS_NOMMU
+	bool "ARM Ltd. Versatile Express family for NOMMU"
+	depends on !MMU
+	select ARCH_VEXPRESS
+	select SPARSE_IRQ
+	select ARM_GENERIC_HEADERS
+	help
+	  This option enables support for systems using Cortex processor based
+	  ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
+	  in configurations WITHOUT an MMU. You must boot using a Flattened
+	  Device Tree - the traditional ATAGs boot method is not usable with
+	  this configuration.
+
+	  If your system has an MMU and you want to make use of it, you
+	  should instead choose to build a multiplatform kernel and
+	  select ARCH_VEXPRESS
+
 config ARCH_AT91
 	bool "Atmel AT91"
 	select ARCH_REQUIRE_GPIOLIB
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:27:25 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:27:25 +0100
Subject: [PATCH v2 3/3] ARM: vexpress-nommu: add a Makefile.boot to restore
 single-platform build
In-Reply-To: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368530845-7415-4-git-send-email-jonathan.austin@arm.com>

When a single-platform kernel is built, a machine-specific Makefile.boot is
expected. In the move to a multiplatform kernels this was removed for
vexpress. Assuming AUTO_ZRELADDR is selected and a DT is used, the values
recorded in it are no-longer required. However, the missing file breaks building
of a single platform kernel for vexpress, such as when using vexpress and a
platform without an MMU.

This patch re-instates Makefile.boot for vexpress in single platform
configuration, fixing single-platform build. This change does not affect the
multi-platform kernel.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
CC: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-vexpress/Makefile.boot |    4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 arch/arm/mach-vexpress/Makefile.boot

diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
new file mode 100644
index 0000000..8caa868
--- /dev/null
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -0,0 +1,4 @@
+# This is a dummy Makefile.boot for building ARCH_VEXPRESS as a standalone
+# platform as opposed with ARCH_MULTIPLATFORM. It is preferable to use
+# CONFIG_AUTO_ZRELADDR=y and DT but uncomment the line below if you need it.
+#   zreladdr-y	+= 0x00008000
-- 
1.7.9.5




From pawel.moll at arm.com  Tue May 14 07:31:21 2013
From: pawel.moll at arm.com (Pawel Moll)
Date: Tue, 14 May 2013 12:31:21 +0100
Subject: [PATCH v2 2/3] ARM: nommu: re-enable use of vexpress without
 ARCH_MULTIPLATFORM
In-Reply-To: <1368530845-7415-3-git-send-email-jonathan.austin@arm.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
 <1368530845-7415-3-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368531081.3159.2.camel@hornet>

On Tue, 2013-05-14 at 12:27 +0100, Jonathan Austin wrote:
> Since 617276307cd4c ("ARM: vexpress: convert to multi-platform") it has been
> impossible to select ARCH_VEXPRESS without ARCH_MULTIPLATFORM.
> 
> ARCH_MULTIPLATFORM doesn't make sense for NOMMU targets, not least because
> of the need to hard-code the memory map. However, it should still be
> possible to run NOMMU kernels on top of the Versatile Express by selecting
> it as the only platform.
> 
> This patch creates a shim ARCH_VEXPRESS_NOMMU config option in the 'choice'
> for "ARM system type" to make this possible again.
> 
> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Acked-by: Nicolas Pitre <nico at fluxnic.net>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> CC: Pawel Moll <pawel.moll at arm.com>

Acked-by: Pawel Moll <pawel.moll at arm.com>

Thanks!

Pawel




From lee.jones at linaro.org  Tue May 14 07:34:26 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 12:34:26 +0100
Subject: [PATCH 9/9] mfd: ab8500-core: Pass GPADC compatible string to
 MFD core
In-Reply-To: <CACRpkdaiZNeh9u_e7wSkHPmrxfaFQLeQEpZXEV4f+rXCCpW_eg@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-10-git-send-email-lee.jones@linaro.org>
 <CACRpkdY8SLRR0HQvD5AFUeNeeHRVt3XM-MOkwJs_h_EfeRctKw@mail.gmail.com>
 <20130514092614.GH3297@gmail.com>
 <CACRpkdaiZNeh9u_e7wSkHPmrxfaFQLeQEpZXEV4f+rXCCpW_eg@mail.gmail.com>
Message-ID: <20130514113426.GB28781@gmail.com>

> >> probing and does not have an .of_match_table defined in it's
> >> driver struct? I mean, what could possibly match that
> >> compatible string? The .name field will take care of naming
> >> the device does it not?
> >
> > You only need that stuff if you require _extra_ bindings. Things like
> > regulators and interrupt numbers are configured behind the scenes.
> 
> Sure, but isn't the idea with of_match_table that this should be
> used in drivers when probing from device tree?

We're not probing from Device Tree. We're registering from MFD.

> Surely it *works* with other schemes but I always thought about
> them as some kind of rough fallback hacks. I would be way more
> convenient with the patch if it added an of_match_table to
> the ADC driver as well, because then I understand what is
> going on.

They're not full-back hacks. All drivers obtain their interrupts this
way when using Device Tree.

> >> For non-emergency merging though:
> >> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> >
> > If we don't put this into v3.10-rcX, then the GPADC driver will be
> > broken in v3.10 when booting with DT.
> 
> OK I think I understand why now...
> 
> >> But for this to make sense the AB8500 ADC driver needs
> >> to be augmented for DT probing and preferrably also moved
> >> to drivers/adc and made to utilize that subsystem.
> >
> > Not sure I understand the reasoning for this. It works well as a plain
> > MFD device.
> 
> The commit message says:
>  "Without it, the driver won't be able to interrogate the Device Tree or
>   locate suitable regulators and will most likely fail to probe."
> 
> That commit message makes it sound like the driver is
> interrogating (hm is that the right term...) the device tree, but
> now you say it isn't (as you say it is a plain MFD device).
> Of course the MFD core and drivers/of/platform.c is doing
> all sorts of magic based on the device tree, and that is
> what the patch fixes, right? Nothing to do with the driver
> really?

I guess you're kind of correct. Yes, it's not the actual driver that's
interrogating (yes it's the right term) the Device Tree, other
subsystems are doing it on the driver's behalf. But the driver's node
is being used, which is why we need the compatible string.

> I suspect the missing regulators due to how the OF core or
> MFD core uses the device tree is the actual problem
> solved by the patch?
> 
> Anyway I think I was after this:
> 
> Isn't the idea that all devices that get probed from a device tree
> shall have corresponding bindings documented under
> Documentation/devicetree/bindings/*?

It has an entry in  Documentation/devicetree/bindings/mfd/ab8500.txt.

> And this driver is definately in the wrong subsystem (not your
> fault) so I suspect the binding doc should be in
> Documentation/devicetree/bindings/adc/ab8500.txt or
> something.

All of the AB8500 devices are covered in the aforementioned file and
to my knowledge none of them are represented in their respective
'real' driver type's binding doc folders (except Power).

> I'm not pointing that out as a problem in this
> patch, I'm just discussing the mess we're in ...

Sure.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From monstr at monstr.eu  Tue May 14 07:38:50 2013
From: monstr at monstr.eu (Michal Simek)
Date: Tue, 14 May 2013 13:38:50 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some
 SoC
In-Reply-To: <519200DA.8060102@atmel.com>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
 <519200DA.8060102@atmel.com>
Message-ID: <5192224A.7090303@monstr.eu>

On 05/14/2013 11:16 AM, Nicolas Ferre wrote:
> On 13/05/2013 18:05, Jean-Christophe PLAGNIOL-VILLARD :
>>
>> On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>>
>>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>>> introduces clear-on-write on ISR register. This behavior is not always
>>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>>> We are using a new Device Tree compatibility string and a capability
>>> property to actually activate this clear-on-write behavior on ISR.
>>>
>>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>
>> can we detect it via the IP?
> 
> As said by Hein, we cannot use the IP revision number. *But* we may have the opportunity to read this integration configuration in the Design Configuration Register 1 (DCFG1 already used for determining data bus width).
> 
> So, Michal or Steffen, can you please tell me the value of:
> -> bit 23 at register address 0x280: mine is "1" which should mean "IRQ read clear", yours should be "0".

here is the whole reg map for zynq.
Reg 0x280 is undocumented in our TRM.
Please decode it not sure if bit 0 is LSB or MSB.

U-Boot-PetaLinux> md e000b000
e000b000: 0000001c 000e0013 00000006 00000000    ................
e000b010: 00180704 00000021 3ffba2e4 3ffbd32c    ....!......?,..?
e000b020: 00000003 00000000 00000000 00000000    ................
e000b030: 07ffffff 63c66f08 00000000 0000ffff    .....o.c........
e000b040: 000003ff 000003ff 00000000 00000000    ................
e000b050: 00000000 00000000 00000000 00000000    ................
e000b060: 00000000 00000000 00000000 00000000    ................
e000b070: 00000000 00000000 00000000 00000000    ................
e000b080: 00000000 00000000 00350a00 00001c48    ..........5.H...
e000b090: 00000000 00000000 00000000 00000000    ................
e000b0a0: 00000000 00000000 00000000 00000000    ................
e000b0b0: 00000000 00000000 00000000 00000000    ................
e000b0c0: 00000000 00000000 00000000 00000000    ................
e000b0d0: 00000000 00000000 00000000 00000000    ................
e000b0e0: 00000000 00000000 00000000 00000000    ................
e000b0f0: 00000000 00000000 00000000 00020118    ................
U-Boot-PetaLinux>
e000b100: 00014796 00000000 0000051e 00000001    .G..............
e000b110: 00000000 00000000 0000051d 00000001    ................
e000b120: 00000000 00000000 00000000 00000000    ................
e000b130: 00000000 00000000 00000000 00000000    ................
e000b140: 00000000 00000000 00000000 00000000    ................
e000b150: 001e58b6 00000000 00000526 00000000    .X......&.......
e000b160: 00000004 00000000 00000004 00000001    ................
e000b170: 00000000 00000004 00000000 0000051d    ................
e000b180: 00000000 00000000 00000000 00000000    ................
e000b190: 00000000 00000000 00000000 00000000    ................
e000b1a0: 00000038 00000000 00000000 00000000    8...............
e000b1b0: 00000000 00000000 00000000 00000000    ................
e000b1c0: 00000000 00000000 00000000 00000000    ................
e000b1d0: 00000000 00000000 00000000 00000000    ................
e000b1e0: 00000000 00000000 00000000 00000000    ................
e000b1f0: 00000000 00000000 00000000 00000000    ................
U-Boot-PetaLinux>
e000b200: 00000000 00000000 00000000 00000000    ................
e000b210: 00000000 00000000 00000000 00000000    ................
e000b220: 00000000 00000000 00000000 00000000    ................
e000b230: 00000000 00000000 00000000 00000000    ................
e000b240: 00000000 00000000 00000000 00000000    ................
e000b250: 00000000 00000000 00000000 00000000    ................
e000b260: 00000000 00000000 00000000 00000000    ................
e000b270: 00000000 00000000 00000000 00000000    ................
e000b280: 02500111 2ab13fff 00000000 00000000    ..P..?.*........
e000b290: 002f2145 00000200 00000000 00000000    E!/.............
e000b2a0: 00000000 00000000 00000000 00000000    ................
e000b2b0: 00000000 00000000 00000000 00000000    ................
e000b2c0: 00000000 00000000 00000000 00000000    ................
e000b2d0: 00000000 00000000 00000000 00000000    ................
e000b2e0: 00000000 00000000 00000000 00000000    ................
e000b2f0: 00000000 00000000 00000000 00000000    ................
U-Boot-PetaLinux>



> 
> Hein, in case of use of the MACB, we do not have this register included, so I will avoid to run the test when using MACB (we already have this information).
> 
> If it works, I plan to rewrite the patch but taking this information instead of the device tree compatibility string.

yep. Will be good to detect it instead of new compatible string.

Also is there an option to remove "CONFIG_ARCH_AT91"?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From linus.walleij at linaro.org  Tue May 14 07:41:19 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 13:41:19 +0200
Subject: [PATCH] pinctrl: generic: Fix typos and clarify comments
In-Reply-To: <1366723718-5369-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1366723718-5369-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <CACRpkdZi2j-q7gtqCUj+XfH_MmrE-qqzrSUVr8h5qBHV_+_Q9w@mail.gmail.com>

On Tue, Apr 23, 2013 at 3:28 PM, Laurent Pinchart
<laurent.pinchart+renesas at ideasonboard.com> wrote:

> Drive strength controls both sink and source currents, clarify the
> description accordingly.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

All makes perfect sense.

Patch applied!

Yours,
Linus Walleij


From jonathan.austin at arm.com  Tue May 14 07:48:50 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:50 +0100
Subject: [PATCH 0/7] NOMMU fixes and preparation for NOMMU/SMP
Message-ID: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>

This patch series, mostly written by Will Deacon, contains fixes for
!CONFIG_MMU that are required in order to be able to run an SMP/NOMMU system.

These patches are required for Cortex-R7 and MPU support, that will be posted
to this list shortly.

This series represents my 'nommu' branch, which can be found at
http://www.linux-arm.org/git?p=linux-ja.git

These patches have been tested over the last year on Versatile Express/NOMMU.

Jonathan Austin (2):
  ARM: nommu: Don't build smp_tlb.c for !CONFIG_MMU
  ARM: nommu: add stub local_flush_bp_all() for !CONFIG_MMUU

Will Deacon (5):
  ARM: nommu: add entry point for secondary CPUs to head-nommu.S
  ARM: nommu: define dummy TLB operations for nommu configurations
  ARM: nommu: provide dummy cpu_switch_mm implementation
  ARM: nommu: do not initialise page tables in secondary_data structure
  ARM: suspend: fix CPU suspend code for !CONFIG_MMU configurations

 arch/arm/include/asm/proc-fns.h |    4 +++
 arch/arm/include/asm/smp_plat.h |    4 +++
 arch/arm/include/asm/tlbflush.h |   25 ++++++++++++++-
 arch/arm/kernel/Makefile        |    5 ++-
 arch/arm/kernel/head-nommu.S    |   50 +++++++++++++++++++++++++++---
 arch/arm/kernel/smp.c           |    2 ++
 arch/arm/kernel/suspend.c       |   64 ++++++++++++++++++++++-----------------
 arch/arm/mm/proc-v6.S           |    6 +++-
 arch/arm/mm/proc-v7.S           |   14 ++++++---
 9 files changed, 134 insertions(+), 40 deletions(-)

-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:53 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:53 +0100
Subject: [PATCH 3/7] ARM: nommu: provide dummy cpu_switch_mm implementation
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-4-git-send-email-jonathan.austin@arm.com>

From: Will Deacon <will.deacon at arm.com>

cpu_switch_mm is a logical nop on nommu systems, so define it as such
when !CONFIG_MMU.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/proc-fns.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb..a6c99fe 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -137,6 +137,10 @@ extern void cpu_resume(void);
 	})
 #endif
 
+#else	/*!CONFIG_MMU */
+
+#define cpu_switch_mm(pgd,mm)	{ }
+
 #endif
 
 #endif /* __ASSEMBLY__ */
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:52 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:52 +0100
Subject: [PATCH 2/7] ARM: nommu: define dummy TLB operations for nommu
 configurations
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-3-git-send-email-jonathan.austin@arm.com>

From: Will Deacon <will.deacon at arm.com>

nommu platforms do not perform address translation and therefore clearly
don't have TLBs. However, some SMP code assumes the presence of the TLB
flushing routines and will therefore fail to compile for a nommu system.

This patch defines dummy local_* TLB operations and #defines
tlb_ops_need_broadcast() as 0, therefore causing the usual ARM SMP TLB
operations to call the local variants instead.

Signed-off-by: Will Deacon <will.deacon at arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
CC: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/smp_plat.h |    4 ++++
 arch/arm/include/asm/tlbflush.h |   23 ++++++++++++++++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6..1c7b6f8 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -26,6 +26,9 @@ static inline bool is_smp(void)
 }
 
 /* all SMP configurations have the extended CPUID registers */
+#ifndef CONFIG_MMU
+#define tlb_ops_need_broadcast()	0
+#else
 static inline int tlb_ops_need_broadcast(void)
 {
 	if (!is_smp())
@@ -33,6 +36,7 @@ static inline int tlb_ops_need_broadcast(void)
 
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
+#endif
 
 #if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
 #define cache_ops_need_broadcast()	0
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d1..cc8517e 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -537,6 +537,27 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 #endif
 
-#endif /* CONFIG_MMU */
+#elif defined(CONFIG_SMP)	/* !CONFIG_MMU */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/mm_types.h>
+
+static inline void local_flush_tlb_all(void)									{ }
+static inline void local_flush_tlb_mm(struct mm_struct *mm)							{ }
+static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)			{ }
+static inline void local_flush_tlb_kernel_page(unsigned long kaddr)						{ }
+static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)	{ }
+static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)				{ }
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_kernel_page(unsigned long kaddr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+#endif	/* __ASSEMBLY__ */
+
+#endif
 
 #endif
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:51 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:51 +0100
Subject: [PATCH 1/7] ARM: nommu: add entry point for secondary CPUs to
 head-nommu.S
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-2-git-send-email-jonathan.austin@arm.com>

From: Will Deacon <will.deacon at arm.com>

This patch adds a secondary_startup entry point to head-nommu.S so that
we can boot secondary CPUs on an SMP nommu configuration.

Signed-off-by: Will Deacon <will.deacon at arm.com>
CC: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
CC: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/kernel/head-nommu.S |   50 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 46 insertions(+), 4 deletions(-)

diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6a2e09c..2d4bf12 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -59,12 +59,56 @@ ENTRY(stext)
 	movs	r10, r5				@ invalid processor (r5=0)?
 	beq	__error_p				@ yes, error 'p'
 
-	adr	lr, BSYM(__after_proc_init)	@ return (PIC) address
+	ldr	r13, =__mmap_switched		@ address to jump to after
+						@ initialising sctlr
+	adr	lr, BSYM(1f)			@ return (PIC) address
  ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
  THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
  THUMB(	mov	pc, r12				)
+ 1:	b	__after_proc_init
 ENDPROC(stext)
 
+#ifdef CONFIG_SMP
+	__CPUINIT
+ENTRY(secondary_startup)
+	/*
+	 * Common entry point for secondary CPUs.
+	 *
+	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+	 * the processor type - there is no need to check the machine type
+	 * as it has already been validated by the primary processor.
+	 */
+	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifndef CONFIG_CPU_CP15
+	ldr	r9, =CONFIG_PROCESSOR_ID
+#else
+	mrc	p15, 0, r9, c0, c0		@ get processor id
+#endif
+	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
+	movs	r10, r5				@ invalid processor?
+	beq	__error_p			@ yes, error 'p'
+
+	adr	r4, __secondary_data
+	ldmia	r4, {r7, r12}
+	adr	lr, BSYM(__after_proc_init)	@ return address
+	mov	r13, r12			@ __secondary_switched address
+ ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
+ THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
+ THUMB(	mov	pc, r12				)
+ENDPROC(secondary_startup)
+
+ENTRY(__secondary_switched)
+	ldr	sp, [r7, #8]			@ set up the stack pointer
+	mov	fp, #0
+	b	secondary_start_kernel
+ENDPROC(__secondary_switched)
+
+	.type	__secondary_data, %object
+__secondary_data:
+	.long	secondary_data
+	.long	__secondary_switched
+#endif /* CONFIG_SMP */
+
 /*
  * Set the Control Register and Read the process ID.
  */
@@ -95,9 +139,7 @@ __after_proc_init:
 #endif
 	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
 #endif /* CONFIG_CPU_CP15 */
-
-	b	__mmap_switched			@ clear the BSS and jump
-						@ to start_kernel
+	mov	pc, r13
 ENDPROC(__after_proc_init)
 	.ltorg
 
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:54 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:54 +0100
Subject: [PATCH 4/7] ARM: nommu: do not initialise page tables in
 secondary_data structure
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-5-git-send-email-jonathan.austin@arm.com>

From: Will Deacon <will.deacon at arm.com>

nommu systems do not require any page tables, so don't try to initialise
them when bringing up secondary cores.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/smp.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 47ab905..b476002 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -87,8 +87,10 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 	 * its stack and the page tables.
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
+#ifdef CONFIG_MMU
 	secondary_data.pgdir = virt_to_phys(idmap_pgd);
 	secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+#endif
 	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
 	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:55 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:55 +0100
Subject: [PATCH 5/7] ARM: suspend: fix CPU suspend code for !CONFIG_MMU
 configurations
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-6-git-send-email-jonathan.austin@arm.com>

From: Will Deacon <will.deacon at arm.com>

The ARM CPU suspend code can be selected even for a !CONFIG_MMU
configuration. The resulting kernel will not compile and, even if it did,
would access undefined co-processor registers when executing.

This patch fixes the v6 and v7 CPU suspend code for the nommu case.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Tested-by: Jonathan Austin <jonathan.austin at arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
CC: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/kernel/suspend.c |   64 +++++++++++++++++++++++++--------------------
 arch/arm/mm/proc-v6.S     |    6 ++++-
 arch/arm/mm/proc-v7.S     |   14 ++++++----
 3 files changed, 50 insertions(+), 34 deletions(-)

diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index c59c97e..38a5067 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -10,6 +10,42 @@
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
 
+#ifdef CONFIG_MMU
+/*
+ * Hide the first two arguments to __cpu_suspend - these are an implementation
+ * detail which platform code shouldn't have to know about.
+ */
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+	struct mm_struct *mm = current->active_mm;
+	int ret;
+
+	if (!idmap_pgd)
+		return -EINVAL;
+
+	/*
+	 * Provide a temporary page table with an identity mapping for
+	 * the MMU-enable code, required for resuming.  On successful
+	 * resume (indicated by a zero return code), we need to switch
+	 * back to the correct page tables.
+	 */
+	ret = __cpu_suspend(arg, fn);
+	if (ret == 0) {
+		cpu_switch_mm(mm->pgd, mm);
+		local_flush_bp_all();
+		local_flush_tlb_all();
+	}
+
+	return ret;
+}
+#else
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+	return __cpu_suspend(arg, fn);
+}
+#define	idmap_pgd	NULL
+#endif
+
 /*
  * This is called by __cpu_suspend() to save the state, and do whatever
  * flushing is required to ensure that when the CPU goes to sleep we have
@@ -46,31 +82,3 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
 	outer_clean_range(virt_to_phys(save_ptr),
 			  virt_to_phys(save_ptr) + sizeof(*save_ptr));
 }
-
-/*
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-	struct mm_struct *mm = current->active_mm;
-	int ret;
-
-	if (!idmap_pgd)
-		return -EINVAL;
-
-	/*
-	 * Provide a temporary page table with an identity mapping for
-	 * the MMU-enable code, required for resuming.  On successful
-	 * resume (indicated by a zero return code), we need to switch
-	 * back to the correct page tables.
-	 */
-	ret = __cpu_suspend(arg, fn);
-	if (ret == 0) {
-		cpu_switch_mm(mm->pgd, mm);
-		local_flush_bp_all();
-		local_flush_tlb_all();
-	}
-
-	return ret;
-}
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 919405e..2d1ef87 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -140,8 +140,10 @@ ENTRY(cpu_v6_set_pte_ext)
 ENTRY(cpu_v6_do_suspend)
 	stmfd	sp!, {r4 - r9, lr}
 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+#ifdef CONFIG_MMU
 	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
 	mrc	p15, 0, r6, c2, c0, 1	@ Translation table base 1
+#endif
 	mrc	p15, 0, r7, c1, c0, 1	@ auxiliary control register
 	mrc	p15, 0, r8, c1, c0, 2	@ co-processor access control
 	mrc	p15, 0, r9, c1, c0, 0	@ control register
@@ -158,14 +160,16 @@ ENTRY(cpu_v6_do_resume)
 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
 	ldmia	r0, {r4 - r9}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+#ifdef CONFIG_MMU
 	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
 	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
 	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
 	mcr	p15, 0, r1, c2, c0, 0	@ Translation table base 0
 	mcr	p15, 0, r6, c2, c0, 1	@ Translation table base 1
+	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
+#endif
 	mcr	p15, 0, r7, c1, c0, 1	@ auxiliary control register
 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
-	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
 	mcr	p15, 0, ip, c7, c5, 4	@ ISB
 	mov	r0, r9			@ control register
 	b	cpu_resume_mmu
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 2c73a73..a851e34 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -98,9 +98,11 @@ ENTRY(cpu_v7_do_suspend)
 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
 	stmia	r0!, {r4 - r5}
+#ifdef CONFIG_MMU
 	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
 	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
 	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
+#endif
 	mrc	p15, 0, r8, c1, c0, 0	@ Control register
 	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
 	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
@@ -110,13 +112,14 @@ ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
 	mov	ip, #0
-	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
 	ldmia	r0!, {r4 - r5}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
 	ldmia	r0, {r6 - r11}
+#ifdef CONFIG_MMU
+	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
 #ifndef CONFIG_ARM_LPAE
 	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
@@ -125,14 +128,15 @@ ENTRY(cpu_v7_do_resume)
 	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
 	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
 	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
-	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
-	teq	r4, r9			@ Is it already set?
-	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
-	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
 	ldr	r4, =PRRR		@ PRRR
 	ldr	r5, =NMRR		@ NMRR
 	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
 	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
+#endif	/* CONFIG_MMU */
+	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
+	teq	r4, r9			@ Is it already set?
+	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
+	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
 	isb
 	dsb
 	mov	r0, r8			@ control register
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:56 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:56 +0100
Subject: [PATCH 6/7] ARM: nommu: Don't build smp_tlb.c for !CONFIG_MMU
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-7-git-send-email-jonathan.austin@arm.com>

Without an MMU we don't need to do any TLB maintenance. Until the addition
of 93dc68876b60 (ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181
(TLBI/DSB operations)) building the tlb maintenance ops in smp_tlb.c worked,
though none of the contents were used.

Since that commit, however, SMP NOMMU has not been able to build. This patch
restores that ability by making the building of smp_tlb.c dependent on MMU.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
CC: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/Makefile |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..9314500 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -32,7 +32,10 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)		+= dma-isa.o
 obj-$(CONFIG_PCI)		+= bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
-obj-$(CONFIG_SMP)		+= smp.o smp_tlb.o
+obj-$(CONFIG_SMP)		+= smp.o
+ifdef CONFIG_MMU
+obj-$(CONFIG_SMP)		+= smp_tlb.o
+endif
 obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)	+= arch_timer.o
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 07:48:57 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 12:48:57 +0100
Subject: [PATCH 7/7] ARM: nommu: add stub local_flush_bp_all() for !CONFIG_MMUU
In-Reply-To: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
References: <1368532137-8871-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368532137-8871-8-git-send-email-jonathan.austin@arm.com>

Since the merging of Will's tlb-ops branch, specifically 89c7e4b8bbb3
(ARM: 7661/1: mm: perform explicit branch predictor maintenance when required),
building SMP without CONFIG_MMU has been broken.

The local_flush_bp_all function is only called for operations related to
changing the kernel's view of memory and ASID rollover - both of which are
irrelevant to an !MMU kernel.

This patch adds a stub local_flush_bp_all() function to the other tlb
maintenance stubs and restores the ability to build an SMP !MMU kernel.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Acked-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/tlbflush.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index cc8517e..ded7c16 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -549,6 +549,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned lon
 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)						{ }
 static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)	{ }
 static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)				{ }
+static inline void local_flush_bp_all(void)									{ }
 
 extern void flush_tlb_all(void);
 extern void flush_tlb_mm(struct mm_struct *mm);
@@ -556,6 +557,7 @@ extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
 extern void flush_tlb_kernel_page(unsigned long kaddr);
 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_bp_all(void);
 #endif	/* __ASSEMBLY__ */
 
 #endif
-- 
1.7.9.5




From dt.tangr at gmail.com  Tue May 14 07:51:10 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Tue, 14 May 2013 21:51:10 +1000
Subject: [RFC PATCHv3 4/6] clocksource: Add TI-Nspire timer drivers
In-Reply-To: <CACRpkdZBFbOnQ9rCehO0yKDN7fH9VR3VYCa_NkOGJz7KN+02FQ@mail.gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>
 <CACRpkdZBFbOnQ9rCehO0yKDN7fH9VR3VYCa_NkOGJz7KN+02FQ@mail.gmail.com>
Message-ID: <26FBB324-AAA9-4C10-8978-C2EC1C26672E@gmail.com>


On 14/05/2013, at 6:03 PM, Linus Walleij <linus.walleij at linaro.org> wrote:

>> +
>> +       timer->interrupt_regs = of_iomap(node, 1);
> 
> Check for errors.
> 
>> +       timer->irqnr = irq_of_parse_and_map(node, 0);
> 
> Check for errors.
>> +       if (timer->interrupt_regs && timer->irqnr) {
>> 

The idea with this is to make these properties optional. Each timer has two sub-timers but only one can generate interrupts. One will be added as a clockevent device and the other as a clocksource. If an IRQ number or interrupt acknowledge address is not passed through the DT, then the clockevents device is not added but the clocksource still is.

Should I comment it in the code to make it apparent what's happening or is there a better way to express this?

> 
>> +               writel(0x3F, timer->interrupt_regs + IO_INTR_ACK);
> 
> Hm magic number, I guess it's clearing all IRQ lines?

It's a bitmask of bits 0-5. 

> 
>> +
>> +               /* Interrupt to occur when timer value matches 0 */
>> +               writel(0, timer->base + IO_MATCH1);
>> +
>> +               timer->clkevt_irq.name  = timer->clockevent_name;
>> +               timer->clkevt_irq.handler = nspire_timer_interrupt;
>> +               timer->clkevt_irq.dev_id = timer;
>> +               timer->clkevt_irq.flags =
>> +                       IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
>> +
>> +               setup_irq(timer->irqnr, &timer->clkevt_irq);
>> +
>> +               clockevents_config_and_register(&timer->clkevt,
>> +                               clk_get_rate(timer->clk), 0x0001, 0xfffe);
>> +               pr_info("Added %s as clockevent\n", timer->clockevent_name);
>> +       }
>> +
>> +       writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
>> +                       timer->timer2 + IO_CONTROL);
>> +
>> +       clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
>> +                       timer->clocksource_name,
>> +                       clk_get_rate(timer->clk),
>> +                       200, 16,
>> +                       clocksource_mmio_readw_up);
> 
> If this timer is really just 16 bits, it's a *pretty* good idea to use
> the prescaler (I guess this is what IO_DIVIDER is) beacuse else you
> will get short sleep times with CONFIG_NO_HZ_IDLE on this system,
> and wake up unnecessarily often.
> 
> The same goes for the clock event.

The clock frequency is 32768Hz. Should I be scaling it down at that frequency?

> 
> See how we calculate the prescaler in arch/arm/mach-integrator/integrator_ap.c
> for example.
> 
> Yours,
> Linus Walleij

Cheers,
Daniel Tang

From Benoit.Lecardonnel at synopsys.com  Tue May 14 07:47:45 2013
From: Benoit.Lecardonnel at synopsys.com (Benoit Lecardonnel)
Date: Tue, 14 May 2013 12:47:45 +0100
Subject: arm64: Platform devices populated from a device_initcall
In-Reply-To: <20130514093108.GA15129@arm.com>
References: <519112E7.3040309@synopsys.com> <20130514093108.GA15129@arm.com>
Message-ID: <51922461.1020408@synopsys.com>

Hi Catalin,

On 2013-05-14 10:31, Catalin Marinas wrote:
> On Mon, May 13, 2013 at 05:20:55PM +0100, Benoit Lecardonnel wrote:
> I think we could put of_clk_init() and of_platform_populate() calls
> under the same arch_initcall() just to keep their relative order.
> Something like this (could even use arch_initcall_sync in case we get
> some other arch_initcall in the future)
>
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> [...]

Thanks for the patch, it works: the device is now probed properly.

Tested-by: Benoit Lecardonnel <Benoit.Lecardonnel at synopsys.com>

-- 
Benoit Lecardonnel


From linus.walleij at linaro.org  Tue May 14 08:02:55 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:02:55 +0200
Subject: [PATCH] ARM: U300: Add proper ifdef guard to fix build error when
 CONFIG_I2C_STU300=m
In-Reply-To: <1367824503.6190.1.camel@phoenix>
References: <1367824503.6190.1.camel@phoenix>
Message-ID: <CACRpkdYrN78Oae_4DKh6cdOWxiuNEZCQzicKKoN5dv1ws185LA@mail.gmail.com>

On Mon, May 6, 2013 at 9:15 AM, Axel Lin <axel.lin at ingics.com> wrote:

> I got below build error if CONFIG_I2C_STU300=m.
>
> ERROR: "i2c_register_board_info" [arch/arm/mach-u300/i2c.ko] undefined!
> make[1]: *** [__modpost] Error 1
> make: *** [modules] Error 2
>
> Fix it by adding proper ifdef guard in i2c.h and Makefile.
> So arch/arm/mach-u300/i2c.c will be compiled when CONFIG_I2C_STU300 is
> configured as built-in or as a module.
>
> Signed-off-by: Axel Lin <axel.lin at ingics.com>

This file will be deleted in v3.11, see:
http://marc.info/?l=linux-arm-kernel&m=136662534118633&w=2

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 08:07:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:07:58 +0200
Subject: [PATCH v3] ARM: exynos: Select PINCTRL_EXYNOS for exynos4/5 at
 chip level
In-Reply-To: <1368123170-22906-1-git-send-email-dianders@chromium.org>
References: <1368039168-24447-1-git-send-email-dianders@chromium.org>
 <1368123170-22906-1-git-send-email-dianders@chromium.org>
Message-ID: <CACRpkdZ3grCyf3x5dEbT6hAVDkpM3mwibVO5kT0Lv=a09-zBPA@mail.gmail.com>

On Thu, May 9, 2013 at 8:12 PM, Doug Anderson <dianders at chromium.org> wrote:

> Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
> missing the pincontrol definitions.  Move PINCTRL selects to the arch
> level since we should be enabling the code for all exynos variants.
>
> Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not
> for exynos5440.  Also add basic dependencies for the PINCTRL_EXYNOS
> kernel config.
>
> Signed-off-by: Doug Anderson <dianders at chromium.org>
> ---
> Changes in v3:
> - Moved to chip level as per Tomasz.
> - Update PINCTRL Kconfig for exynos.
>
> Changes in v2:
> - Moved to the arch level as suggested by Olof.

Acked-by: Linus Walleij <linus.walleij at linaro.org> for the pinctrl
part, I guess this will be merged through the Samsung tree?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 08:19:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:19:31 +0200
Subject: [RFC 18/42] drivers/pinctrl: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-19-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-19-git-send-email-wsa@the-dreams.de>
Message-ID: <CACRpkda8gNhcqCa6Yv7J1kHHz+EhrpYGQn=h_JMNCXbbOdMt1A@mail.gmail.com>

On Fri, May 10, 2013 at 10:17 AM, Wolfram Sang <wsa at the-dreams.de> wrote:

> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>

Patch applied with Jean-Christophe's ACK.

Thanks!
Linus Walleij


From kgene.kim at samsung.com  Tue May 14 08:25:13 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 14 May 2013 21:25:13 +0900
Subject: [PATCH v3] ARM: exynos: Select PINCTRL_EXYNOS for exynos4/5 at
 chip level
In-Reply-To: <CACRpkdZ3grCyf3x5dEbT6hAVDkpM3mwibVO5kT0Lv=a09-zBPA@mail.gmail.com>
References: <1368039168-24447-1-git-send-email-dianders@chromium.org>
 <1368123170-22906-1-git-send-email-dianders@chromium.org>
 <CACRpkdZ3grCyf3x5dEbT6hAVDkpM3mwibVO5kT0Lv=a09-zBPA@mail.gmail.com>
Message-ID: <093701ce509e$15ba0350$412e09f0$%kim@samsung.com>

Linus Walleij wrote:
> 
> On Thu, May 9, 2013 at 8:12 PM, Doug Anderson <dianders at chromium.org>
> wrote:
> 
> > Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
> > missing the pincontrol definitions.  Move PINCTRL selects to the arch
> > level since we should be enabling the code for all exynos variants.
> >
> > Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not
> > for exynos5440.  Also add basic dependencies for the PINCTRL_EXYNOS
> > kernel config.
> >
> > Signed-off-by: Doug Anderson <dianders at chromium.org>
> > ---
> > Changes in v3:
> > - Moved to chip level as per Tomasz.
> > - Update PINCTRL Kconfig for exynos.
> >
> > Changes in v2:
> > - Moved to the arch level as suggested by Olof.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org> for the pinctrl
> part, I guess this will be merged through the Samsung tree?
> 
Linus, thanks for your ack.

Let me take this into samsung tree.

- Kukjin



From jonathan.austin at arm.com  Tue May 14 08:26:55 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 13:26:55 +0100
Subject: [PATCH 0/3]  Support for the ARM Cortex-R7 Processor
Message-ID: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>

This series adds initial support for the ARM Cortex-R7 Processor. The R7 is an
SMP-capable R-class device. Among other things, R-Class cores differ from the
A-class in using a Memory Protection Unity (MPU) instead of an MMU.

Support for the MPU is required in order to use the R7 in an SMP configuration.
There are patches for MPU support that will be posted to this list shortly.

This series depends on:
 - The nommu fixes series I posted to this list earlier
   - http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168114.html
 - The ARCH_MULTIPLATFORM restructuring that I posted earlier in order to
   be able to use ARCH_VEXPRESS with NOMMU.
   - http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168106.html

This code is available in my r7 branch:
http://www.linux-arm.org/git?p=linux-ja.git;a=log;h=refs/heads/r7

Jonathan Austin (3):
  ARM: select CPU_CPU15_MMU/MPU appropriately
  ARM: add Cortex-R7 Processor Info
  ARM: vexpress: Add Cortex-R Series UART, selectable via DEBUG_LL

 arch/arm/Kconfig.debug            |   10 +++++++++-
 arch/arm/include/debug/vexpress.S |   10 ++++++++++
 arch/arm/mm/Kconfig               |    3 ++-
 arch/arm/mm/proc-v7.S             |   13 ++++++++++++-
 4 files changed, 33 insertions(+), 3 deletions(-)

-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 08:26:56 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 13:26:56 +0100
Subject: [PATCH 1/3] ARM: select CPU_CPU15_MMU/MPU appropriately
In-Reply-To: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>
References: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368534418-11287-2-git-send-email-jonathan.austin@arm.com>

Currently CPU_V7 selects CPU_CP15_MMU, however in the case of a V7 CPU
implementing the PMSA, such as the Cortex-R7, the CP15_MMU operations are
not available. Selecting CPU_CP15_MPU is appropriate in this case.

This patch makes CPU_CP15_MMU dependent on the use of the MMU, selecting
CPU_CP15_MPU for v7 processors when !MMU is chosen.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
---
 arch/arm/mm/Kconfig |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 35955b5..ca5c585 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -392,7 +392,8 @@ config CPU_V7
 	select CPU_CACHE_V7
 	select CPU_CACHE_VIPT
 	select CPU_COPY_V6 if MMU
-	select CPU_CP15_MMU
+	select CPU_CP15_MMU if MMU
+	select CPU_CP15_MPU if !MMU
 	select CPU_HAS_ASID if MMU
 	select CPU_PABRT_V7
 	select CPU_TLB_V7 if MMU
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 08:26:57 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 13:26:57 +0100
Subject: [PATCH 2/3] ARM: add Cortex-R7 Processor Info
In-Reply-To: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>
References: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368534418-11287-3-git-send-email-jonathan.austin@arm.com>

This patch adds processor info for ARM Ltd. Cortex-R7.

The R7 has many similarities to the A9 and though the ACTLR layout is not
identical, the bits associated with cache operations broadcasting and SMP
modes are the same for A9, A5 and R7 (Though in the A-class processors the
same bits toggle TLB-ops broadcasting as well as cache-ops)

HWCAP_IDIV need not be specified as this is now auto-detected

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
CC: Catalin Marinas <catalin.marinas at arm.com>
CC: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mm/proc-v7.S |   13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a851e34..f85ae8c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -159,7 +159,8 @@ ENDPROC(cpu_v7_do_resume)
  */
 __v7_ca5mp_setup:
 __v7_ca9mp_setup:
-	mov	r10, #(1 << 0)			@ TLB ops broadcasting
+__v7_cr7mp_setup:
+	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
 	b	1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
@@ -419,6 +420,16 @@ __v7_pj4b_proc_info:
 	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 
 	/*
+	 * ARM Ltd. Cortex R7 processor.
+	 */
+	.type	__v7_cr7mp_proc_info, #object
+__v7_cr7mp_proc_info:
+	.long	0x410fc170
+	.long	0xff0ffff0
+	__v7_proc __v7_cr7mp_setup
+	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
+
+	/*
 	 * ARM Ltd. Cortex A7 processor.
 	 */
 	.type	__v7_ca7mp_proc_info, #object
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 08:26:58 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 13:26:58 +0100
Subject: [PATCH 3/3] ARM: vexpress: Add Cortex-R Series UART,
 selectable via DEBUG_LL
In-Reply-To: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>
References: <1368534418-11287-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368534418-11287-4-git-send-email-jonathan.austin@arm.com>

The Cortex-R series processors on Versatile Express have a different memory
map to the RS1 and CA9X4 tiles. Most of the platform difference can be
expressed in device-trees, but the UART definitions for LL_DEBUG cannot.

This patch defines the UART location for R-Series processors on
versatile-express, allowing low-level debug and output from the decompressor.
These definitions are selectable via Kconfig

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
CC: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/Kconfig.debug            |   10 +++++++++-
 arch/arm/include/debug/vexpress.S |   10 ++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ede909b..e2ab50a 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -476,6 +476,13 @@ choice
 		  of the tiles using the RS1 memory map, including all new A-class
 		  core tiles, FPGA-based SMMs and software models.
 
+	config DEBUG_VEXPRESS_UART0_CRX
+		bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
+		depends on ARCH_VEXPRESS_NOMMU
+		help
+		  This option selects UART0 at 0xb0090000. This is appropriate for
+		  Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
+
 	config DEBUG_VT8500_UART0
 		bool "Use UART0 on VIA/Wondermedia SoCs"
 		depends on ARCH_VT8500
@@ -645,7 +652,8 @@ config DEBUG_LL_INCLUDE
 	default "debug/tegra.S" if DEBUG_TEGRA_UART
 	default "debug/ux500.S" if DEBUG_UX500_UART
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
-		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \
+		DEBUG_VEXPRESS_UART0_CRX
 	default "debug/vt8500.S" if DEBUG_VT8500_UART0
 	default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
 	default "mach/debug-macro.S"
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index dc8e882..acafb22 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -16,6 +16,8 @@
 #define DEBUG_LL_PHYS_BASE_RS1		0x1c000000
 #define DEBUG_LL_UART_OFFSET_RS1	0x00090000
 
+#define DEBUG_LL_UART_PHYS_CRX		0xb0090000
+
 #define DEBUG_LL_VIRT_BASE		0xf8000000
 
 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
@@ -67,6 +69,14 @@
 
 #include <asm/hardware/debug-pl01x.S>
 
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX)
+
+		.macro	addruart,rp,tmp,tmp2
+		ldr	\rp, =DEBUG_LL_UART_PHYS_CRX
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
+
 #else /* CONFIG_DEBUG_LL_UART_NONE */
 
 		.macro	addruart, rp, rv, tmp
-- 
1.7.9.5




From nicolas.ferre at atmel.com  Tue May 14 08:30:59 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 May 2013 14:30:59 +0200
Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some
 SoC
In-Reply-To: <5192224A.7090303@monstr.eu>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <FE065E51-1EAA-47ED-8C7B-0F2E6418F349@jcrosoft.com>
 <519200DA.8060102@atmel.com> <5192224A.7090303@monstr.eu>
Message-ID: <51922E83.2060002@atmel.com>

On 14/05/2013 13:38, Michal Simek :
> On 05/14/2013 11:16 AM, Nicolas Ferre wrote:
>> On 13/05/2013 18:05, Jean-Christophe PLAGNIOL-VILLARD :
>>>
>>> On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>>>
>>>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>>>> introduces clear-on-write on ISR register. This behavior is not always
>>>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>>>> We are using a new Device Tree compatibility string and a capability
>>>> property to actually activate this clear-on-write behavior on ISR.
>>>>
>>>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>>>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>>
>>> can we detect it via the IP?
>>
>> As said by Hein, we cannot use the IP revision number. *But* we may have the opportunity to read this integration configuration in the Design Configuration Register 1 (DCFG1 already used for determining data bus width).
>>
>> So, Michal or Steffen, can you please tell me the value of:
>> -> bit 23 at register address 0x280: mine is "1" which should mean "IRQ read clear", yours should be "0".
>
> here is the whole reg map for zynq.
> Reg 0x280 is undocumented in our TRM.
> Please decode it not sure if bit 0 is LSB or MSB.

Bit 0 is LSB.

Value of DCFG1 is 0x02500111 so I read '0' for this value which should 
be good.

I write a new patch immediately.


> U-Boot-PetaLinux> md e000b000
> e000b000: 0000001c 000e0013 00000006 00000000    ................
> e000b010: 00180704 00000021 3ffba2e4 3ffbd32c    ....!......?,..?
> e000b020: 00000003 00000000 00000000 00000000    ................
> e000b030: 07ffffff 63c66f08 00000000 0000ffff    .....o.c........
> e000b040: 000003ff 000003ff 00000000 00000000    ................
> e000b050: 00000000 00000000 00000000 00000000    ................
> e000b060: 00000000 00000000 00000000 00000000    ................
> e000b070: 00000000 00000000 00000000 00000000    ................
> e000b080: 00000000 00000000 00350a00 00001c48    ..........5.H...
> e000b090: 00000000 00000000 00000000 00000000    ................
> e000b0a0: 00000000 00000000 00000000 00000000    ................
> e000b0b0: 00000000 00000000 00000000 00000000    ................
> e000b0c0: 00000000 00000000 00000000 00000000    ................
> e000b0d0: 00000000 00000000 00000000 00000000    ................
> e000b0e0: 00000000 00000000 00000000 00000000    ................
> e000b0f0: 00000000 00000000 00000000 00020118    ................
> U-Boot-PetaLinux>
> e000b100: 00014796 00000000 0000051e 00000001    .G..............
> e000b110: 00000000 00000000 0000051d 00000001    ................
> e000b120: 00000000 00000000 00000000 00000000    ................
> e000b130: 00000000 00000000 00000000 00000000    ................
> e000b140: 00000000 00000000 00000000 00000000    ................
> e000b150: 001e58b6 00000000 00000526 00000000    .X......&.......
> e000b160: 00000004 00000000 00000004 00000001    ................
> e000b170: 00000000 00000004 00000000 0000051d    ................
> e000b180: 00000000 00000000 00000000 00000000    ................
> e000b190: 00000000 00000000 00000000 00000000    ................
> e000b1a0: 00000038 00000000 00000000 00000000    8...............
> e000b1b0: 00000000 00000000 00000000 00000000    ................
> e000b1c0: 00000000 00000000 00000000 00000000    ................
> e000b1d0: 00000000 00000000 00000000 00000000    ................
> e000b1e0: 00000000 00000000 00000000 00000000    ................
> e000b1f0: 00000000 00000000 00000000 00000000    ................
> U-Boot-PetaLinux>
> e000b200: 00000000 00000000 00000000 00000000    ................
> e000b210: 00000000 00000000 00000000 00000000    ................
> e000b220: 00000000 00000000 00000000 00000000    ................
> e000b230: 00000000 00000000 00000000 00000000    ................
> e000b240: 00000000 00000000 00000000 00000000    ................
> e000b250: 00000000 00000000 00000000 00000000    ................
> e000b260: 00000000 00000000 00000000 00000000    ................
> e000b270: 00000000 00000000 00000000 00000000    ................
> e000b280: 02500111 2ab13fff 00000000 00000000    ..P..?.*........
> e000b290: 002f2145 00000200 00000000 00000000    E!/.............
> e000b2a0: 00000000 00000000 00000000 00000000    ................
> e000b2b0: 00000000 00000000 00000000 00000000    ................
> e000b2c0: 00000000 00000000 00000000 00000000    ................
> e000b2d0: 00000000 00000000 00000000 00000000    ................
> e000b2e0: 00000000 00000000 00000000 00000000    ................
> e000b2f0: 00000000 00000000 00000000 00000000    ................
> U-Boot-PetaLinux>
>
>
>
>>
>> Hein, in case of use of the MACB, we do not have this register included, so I will avoid to run the test when using MACB (we already have this information).
>>
>> If it works, I plan to rewrite the patch but taking this information instead of the device tree compatibility string.
>
> yep. Will be good to detect it instead of new compatible string.
>
> Also is there an option to remove "CONFIG_ARCH_AT91"?

Okay, I have a look at this as-well.

Best regards,
-- 
Nicolas Ferre


From marc.zyngier at arm.com  Tue May 14 08:30:51 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 13:30:51 +0100
Subject: [PATCH v2 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
Message-ID: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

A second, tree-wide patch also removes the use of the addprefix used
to refer to the main KVM code from the arch code, and replace it with
a KVM variable that does the same thing.

Marc Zyngier (2):
  ARM: KVM: move GIC/timer code to a common location
  KVM: get rid of $(addprefix ../../../virt/kvm/, ...) in Makefiles

 arch/arm/include/asm/kvm_host.h                             |  4 ++--
 arch/arm/kvm/Makefile                                       |  7 ++++---
 arch/ia64/kvm/Makefile                                      |  7 ++++---
 arch/powerpc/kvm/Makefile                                   | 13 +++++++------
 arch/s390/kvm/Makefile                                      |  3 ++-
 arch/x86/kvm/Makefile                                       | 13 +++++++------
 .../asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h    |  0
 arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h   |  0
 {arch/arm/kvm => virt/kvm/arm}/arch_timer.c                 |  4 ++--
 {arch/arm/kvm => virt/kvm/arm}/vgic.c                       |  0
 10 files changed, 28 insertions(+), 23 deletions(-)
 rename arch/arm/include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h (100%)
 rename arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h (100%)
 rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
 rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)

-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 08:30:52 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 13:30:52 +0100
Subject: [PATCH v2 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
References: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368534653-23133-2-git-send-email-marc.zyngier@arm.com>

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

Eventually, we should probably have independant Makefiles at every
levels (just like everywhere else in the kernel), but this is just
the first step.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_host.h                                    | 4 ++--
 arch/arm/kvm/Makefile                                              | 7 ++++---
 .../include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h   | 0
 arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h          | 0
 {arch/arm/kvm => virt/kvm/arm}/arch_timer.c                        | 4 ++--
 {arch/arm/kvm => virt/kvm/arm}/vgic.c                              | 0
 6 files changed, 8 insertions(+), 7 deletions(-)
 rename arch/arm/include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h (100%)
 rename arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h (100%)
 rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
 rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index ff49193..1f3cee2 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,7 +23,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_arch_timer.h>
 
 #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
 #define KVM_USER_MEM_SLOTS 32
@@ -38,7 +38,7 @@
 #define KVM_NR_PAGE_SIZES	1
 #define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
 
-#include <asm/kvm_vgic.h>
+#include <kvm/arm_vgic.h>
 
 struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 53c5ed8..9184a49 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
-kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+KVM := ../../../virt/kvm
+kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
-obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/include/kvm/arm_arch_timer.h
similarity index 100%
rename from arch/arm/include/asm/kvm_arch_timer.h
rename to include/kvm/arm_arch_timer.h
diff --git a/arch/arm/include/asm/kvm_vgic.h b/include/kvm/arm_vgic.h
similarity index 100%
rename from arch/arm/include/asm/kvm_vgic.h
rename to include/kvm/arm_vgic.h
diff --git a/arch/arm/kvm/arch_timer.c b/virt/kvm/arm/arch_timer.c
similarity index 99%
rename from arch/arm/kvm/arch_timer.c
rename to virt/kvm/arm/arch_timer.c
index c55b608..2d00b29 100644
--- a/arch/arm/kvm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -25,8 +25,8 @@
 #include <clocksource/arm_arch_timer.h>
 #include <asm/arch_timer.h>
 
-#include <asm/kvm_vgic.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_vgic.h>
+#include <kvm/arm_arch_timer.h>
 
 static struct timecounter *timecounter;
 static struct workqueue_struct *wqueue;
diff --git a/arch/arm/kvm/vgic.c b/virt/kvm/arm/vgic.c
similarity index 100%
rename from arch/arm/kvm/vgic.c
rename to virt/kvm/arm/vgic.c
-- 
1.8.2.3




From kgene.kim at samsung.com  Tue May 14 08:31:09 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 14 May 2013 21:31:09 +0900
Subject: [GIT PULL] Late Exynos stuff for v3.10
In-Reply-To: <5191CE53.5050902@linaro.org>
References: <5176B499.1000208@samsung.com> <51770697.7080504@samsung.com>
 <20130424000638.GA9067@quad.lixom.net> <51794E10.1010205@samsung.com>
 <CAOesGMjA5_XUXMcCL3roZiLC1S=ypMoVHn2tF7bzUuKr+eLw2A@mail.gmail.com>
 <046301ce4d15$ac1592b0$0440b810$%kim@samsung.com>
 <5191CE53.5050902@linaro.org>
Message-ID: <093801ce509e$e98b2bf0$bca183d0$%kim@samsung.com>

Tushar Behera wrote:
> 
> >> Refresh my memory here, what was the reason for dropping the USB DTS
> >> updates? (Yes, I am aware it might because I asked you not to send
> >> them in but I don't remember :-).
> >>
> > Hmm...let me see, yeah, the USB DTS updates dropped because of late
> > pull-request stuff as you concerned.
> > http://www.spinics.net/lists/arm-kernel/msg240105.html
> >
> > Since I didn't want to make a noise at that time, so I dropped for
v3.10,
> it
> > has been included in my tree for some time though.
> >
> 
> Will it be possible to queue them up for one of the RC releases? They
> are only DTS entries, the drivers have already been merged.
> 
Well, I think, it's possible to send the usb phy node for usb2 for v3.10
because it's critical at this moment.

Others should be queued for v3.11.

Thanks.

- Kukjin



From marc.zyngier at arm.com  Tue May 14 08:30:53 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 13:30:53 +0100
Subject: [PATCH v2 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
References: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368534653-23133-3-git-send-email-marc.zyngier@arm.com>

As requested by the KVM maintainers, remove the addprefix used to
refer to the main KVM code from the arch code, and replace it with
a KVM variable that does the same thing.

Cc: Paolo Bonzini <pbonzini at redhat.com>
Cc: Gleb Natapov <gleb at redhat.com>
Cc: Christoffer Dall <cdall at cs.columbia.edu>
Cc: Xiantao Zhang <xiantao.zhang at intel.com>
Cc: Tony Luck <tony.luck at intel.com>
Cc: Fenghua Yu <fenghua.yu at intel.com>
Cc: Alexander Graf <agraf at suse.de>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: Christian Borntraeger <borntraeger at de.ibm.com>
Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kvm/Makefile     |  2 +-
 arch/ia64/kvm/Makefile    |  7 ++++---
 arch/powerpc/kvm/Makefile | 13 +++++++------
 arch/s390/kvm/Makefile    |  3 ++-
 arch/x86/kvm/Makefile     | 13 +++++++------
 5 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 9184a49..d99bee4 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
 KVM := ../../../virt/kvm
-kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
+kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
index 1a40537..18e45ec 100644
--- a/arch/ia64/kvm/Makefile
+++ b/arch/ia64/kvm/Makefile
@@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
 
 ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
 asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
+KVM := ../../../virt/kvm
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-		coalesced_mmio.o irq_comm.o)
+common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
+		$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
 
 ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
-common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
+common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
 endif
 
 kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 422de3f..008cd85 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -5,9 +5,10 @@
 subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
 ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
+KVM := ../../../virt/kvm
 
-common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
-						eventfd.o)
+common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
+		$(KVM)/eventfd.o
 
 CFLAGS_44x_tlb.o  := -I.
 CFLAGS_e500_mmu.o := -I.
@@ -53,7 +54,7 @@ kvm-e500mc-objs := \
 kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
 
 kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
-	../../../virt/kvm/coalesced_mmio.o \
+	$(KVM)/coalesced_mmio.o \
 	fpu.o \
 	book3s_paired_singles.o \
 	book3s_pr.o \
@@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
 	book3s_xics.o
 
 kvm-book3s_64-module-objs := \
-	../../../virt/kvm/kvm_main.o \
-	../../../virt/kvm/eventfd.o \
+	$(KVM)/kvm_main.o \
+	$(KVM)/eventfd.o \
 	powerpc.o \
 	emulate.o \
 	book3s.o \
@@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
 kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
 
 kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
-kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
+kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
 
 kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
 
diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
index 8fe9d65..40b4c64 100644
--- a/arch/s390/kvm/Makefile
+++ b/arch/s390/kvm/Makefile
@@ -6,7 +6,8 @@
 # it under the terms of the GNU General Public License (version 2 only)
 # as published by the Free Software Foundation.
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
+KVM := ../../../virt/kvm
+common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
 
 ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
 
diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
index d609e1d..21d5703 100644
--- a/arch/x86/kvm/Makefile
+++ b/arch/x86/kvm/Makefile
@@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
 CFLAGS_svm.o := -I.
 CFLAGS_vmx.o := -I.
 
-kvm-y			+= $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-				coalesced_mmio.o irq_comm.o eventfd.o \
-				irqchip.o)
-kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(addprefix ../../../virt/kvm/, \
-				assigned-dev.o iommu.o)
-kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(addprefix ../../../virt/kvm/, async_pf.o)
+KVM := ../../../virt/kvm
+
+kvm-y			+= $(KVM)/kvm_main.o $(KVM)/ioapic.o \
+				$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
+				$(KVM)/eventfd.o $(KVM)/irqchip.o
+kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(KVM)/assigned-dev.o $(KVM)/iommu.o
+kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(KVM)/async_pf.o
 
 kvm-y			+= x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
 			   i8254.o cpuid.o pmu.o
-- 
1.8.2.3




From kgene.kim at samsung.com  Tue May 14 08:36:42 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 14 May 2013 21:36:42 +0900
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <CAKohponkFB7ND38jv5oGnQLx8cq0b=uHTCmL3EERe6P54ijYhw@mail.gmail.com>
References: <cover.1365079581.git.viresh.kumar@linaro.org>
 <5176A807.2090005@samsung.com>
 <CAKohpomV9-JEbuHWdmp6N+bKYt+83hXXcqg4aKXSY1a5zwpW9Q@mail.gmail.com>
 <105283277.osOpfTKkgk@vostro.rjw.lan>
 <CAKohponkFB7ND38jv5oGnQLx8cq0b=uHTCmL3EERe6P54ijYhw@mail.gmail.com>
Message-ID: <093901ce509f$afe92f40$0fbb8dc0$%kim@samsung.com>

Viresh Kumar wrote:
> 
> On 13 May 2013 16:21, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> > That doesn't matter I suppose.  I can take it, but please rebase it on
> top
> > of current linux-next.
> 
> I have already done that (attached). But i wasn't sure what Kukjin wants
> as
> he may report conflicts again and i will ask the same question for 3.12 :)
> 
Since this missed last time, this would be sent to upstream via samsung tree
again. It means the conflicts should be handled by myself.

Rafael, if you don't mind, let me take this into Samsung tree for v3.11.

- Kukjin



From pbonzini at redhat.com  Tue May 14 08:37:07 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Tue, 14 May 2013 14:37:07 +0200
Subject: [PATCH v2 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <1368534653-23133-3-git-send-email-marc.zyngier@arm.com>
References: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
 <1368534653-23133-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <51922FF3.4060300@redhat.com>

Il 14/05/2013 14:30, Marc Zyngier ha scritto:
> As requested by the KVM maintainers, remove the addprefix used to
> refer to the main KVM code from the arch code, and replace it with
> a KVM variable that does the same thing.
> 
> Cc: Paolo Bonzini <pbonzini at redhat.com>
> Cc: Gleb Natapov <gleb at redhat.com>
> Cc: Christoffer Dall <cdall at cs.columbia.edu>
> Cc: Xiantao Zhang <xiantao.zhang at intel.com>
> Cc: Tony Luck <tony.luck at intel.com>
> Cc: Fenghua Yu <fenghua.yu at intel.com>
> Cc: Alexander Graf <agraf at suse.de>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: Christian Borntraeger <borntraeger at de.ibm.com>
> Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Thanks,

Reviewed-by: Paolo Bonzini <pbonzini at redhat.com>

> ---
>  arch/arm/kvm/Makefile     |  2 +-
>  arch/ia64/kvm/Makefile    |  7 ++++---
>  arch/powerpc/kvm/Makefile | 13 +++++++------
>  arch/s390/kvm/Makefile    |  3 ++-
>  arch/x86/kvm/Makefile     | 13 +++++++------
>  5 files changed, 21 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
> index 9184a49..d99bee4 100644
> --- a/arch/arm/kvm/Makefile
> +++ b/arch/arm/kvm/Makefile
> @@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
>  AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
>  
>  KVM := ../../../virt/kvm
> -kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
> +kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
>  
>  obj-y += kvm-arm.o init.o interrupts.o
>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
> diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
> index 1a40537..18e45ec 100644
> --- a/arch/ia64/kvm/Makefile
> +++ b/arch/ia64/kvm/Makefile
> @@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
>  
>  ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
>  asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
> +KVM := ../../../virt/kvm
>  
> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
> -		coalesced_mmio.o irq_comm.o)
> +common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
> +		$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
>  
>  ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
> -common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
> +common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
>  endif
>  
>  kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
> diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
> index 422de3f..008cd85 100644
> --- a/arch/powerpc/kvm/Makefile
> +++ b/arch/powerpc/kvm/Makefile
> @@ -5,9 +5,10 @@
>  subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
>  
>  ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
> +KVM := ../../../virt/kvm
>  
> -common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
> -						eventfd.o)
> +common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
> +		$(KVM)/eventfd.o
>  
>  CFLAGS_44x_tlb.o  := -I.
>  CFLAGS_e500_mmu.o := -I.
> @@ -53,7 +54,7 @@ kvm-e500mc-objs := \
>  kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
>  
>  kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
> -	../../../virt/kvm/coalesced_mmio.o \
> +	$(KVM)/coalesced_mmio.o \
>  	fpu.o \
>  	book3s_paired_singles.o \
>  	book3s_pr.o \
> @@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
>  	book3s_xics.o
>  
>  kvm-book3s_64-module-objs := \
> -	../../../virt/kvm/kvm_main.o \
> -	../../../virt/kvm/eventfd.o \
> +	$(KVM)/kvm_main.o \
> +	$(KVM)/eventfd.o \
>  	powerpc.o \
>  	emulate.o \
>  	book3s.o \
> @@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
>  kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
>  
>  kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
> -kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
> +kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
>  
>  kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
>  
> diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
> index 8fe9d65..40b4c64 100644
> --- a/arch/s390/kvm/Makefile
> +++ b/arch/s390/kvm/Makefile
> @@ -6,7 +6,8 @@
>  # it under the terms of the GNU General Public License (version 2 only)
>  # as published by the Free Software Foundation.
>  
> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
> +KVM := ../../../virt/kvm
> +common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
>  
>  ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
>  
> diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
> index d609e1d..21d5703 100644
> --- a/arch/x86/kvm/Makefile
> +++ b/arch/x86/kvm/Makefile
> @@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
>  CFLAGS_svm.o := -I.
>  CFLAGS_vmx.o := -I.
>  
> -kvm-y			+= $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
> -				coalesced_mmio.o irq_comm.o eventfd.o \
> -				irqchip.o)
> -kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(addprefix ../../../virt/kvm/, \
> -				assigned-dev.o iommu.o)
> -kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(addprefix ../../../virt/kvm/, async_pf.o)
> +KVM := ../../../virt/kvm
> +
> +kvm-y			+= $(KVM)/kvm_main.o $(KVM)/ioapic.o \
> +				$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
> +				$(KVM)/eventfd.o $(KVM)/irqchip.o
> +kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(KVM)/assigned-dev.o $(KVM)/iommu.o
> +kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(KVM)/async_pf.o
>  
>  kvm-y			+= x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
>  			   i8254.o cpuid.o pmu.o
> 



From pbonzini at redhat.com  Tue May 14 08:38:53 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Tue, 14 May 2013 14:38:53 +0200
Subject: [PATCH v2 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <1368534653-23133-2-git-send-email-marc.zyngier@arm.com>
References: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
 <1368534653-23133-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <5192305D.80804@redhat.com>

Il 14/05/2013 14:30, Marc Zyngier ha scritto:
> As KVM/arm64 is looming on the horizon, it makes sense to move some
> of the common code to a single location in order to reduce duplication.
> 
> The code could live anywhere. Actually, most of KVM is already built
> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
> not exactly talking about style here. But maybe it is time to start
> moving into a less ugly direction.
> 
> The include files must be in a "public" location, as they are accessed
> from non-KVM files (arch/arm/kernel/asm-offsets.c).
> 
> For this purpose, introduce two new locations:
> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>   virt/kvm, so this could be seen as a (very ugly) precedent.
> - include/kvm/  : there is already an include/xen, and while the
>   intent is slightly different, this seems as good a location as
>   any
> 
> Eventually, we should probably have independant Makefiles at every
> levels (just like everywhere else in the kernel), but this is just
> the first step.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Looks good.

Thanks,

Paolo

> ---
>  arch/arm/include/asm/kvm_host.h                                    | 4 ++--
>  arch/arm/kvm/Makefile                                              | 7 ++++---
>  .../include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h   | 0
>  arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h          | 0
>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c                        | 4 ++--
>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                              | 0
>  6 files changed, 8 insertions(+), 7 deletions(-)
>  rename arch/arm/include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h (100%)
>  rename arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h (100%)
>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
> 
> diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
> index ff49193..1f3cee2 100644
> --- a/arch/arm/include/asm/kvm_host.h
> +++ b/arch/arm/include/asm/kvm_host.h
> @@ -23,7 +23,7 @@
>  #include <asm/kvm_asm.h>
>  #include <asm/kvm_mmio.h>
>  #include <asm/fpstate.h>
> -#include <asm/kvm_arch_timer.h>
> +#include <kvm/arm_arch_timer.h>
>  
>  #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
>  #define KVM_USER_MEM_SLOTS 32
> @@ -38,7 +38,7 @@
>  #define KVM_NR_PAGE_SIZES	1
>  #define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
>  
> -#include <asm/kvm_vgic.h>
> +#include <kvm/arm_vgic.h>
>  
>  struct kvm_vcpu;
>  u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
> index 53c5ed8..9184a49 100644
> --- a/arch/arm/kvm/Makefile
> +++ b/arch/arm/kvm/Makefile
> @@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
>  AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
>  AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
>  
> -kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
> +KVM := ../../../virt/kvm
> +kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
>  
>  obj-y += kvm-arm.o init.o interrupts.o
>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
>  obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
> -obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
> -obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
> +obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
> +obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
> diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/include/kvm/arm_arch_timer.h
> similarity index 100%
> rename from arch/arm/include/asm/kvm_arch_timer.h
> rename to include/kvm/arm_arch_timer.h
> diff --git a/arch/arm/include/asm/kvm_vgic.h b/include/kvm/arm_vgic.h
> similarity index 100%
> rename from arch/arm/include/asm/kvm_vgic.h
> rename to include/kvm/arm_vgic.h
> diff --git a/arch/arm/kvm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> similarity index 99%
> rename from arch/arm/kvm/arch_timer.c
> rename to virt/kvm/arm/arch_timer.c
> index c55b608..2d00b29 100644
> --- a/arch/arm/kvm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -25,8 +25,8 @@
>  #include <clocksource/arm_arch_timer.h>
>  #include <asm/arch_timer.h>
>  
> -#include <asm/kvm_vgic.h>
> -#include <asm/kvm_arch_timer.h>
> +#include <kvm/arm_vgic.h>
> +#include <kvm/arm_arch_timer.h>
>  
>  static struct timecounter *timecounter;
>  static struct workqueue_struct *wqueue;
> diff --git a/arch/arm/kvm/vgic.c b/virt/kvm/arm/vgic.c
> similarity index 100%
> rename from arch/arm/kvm/vgic.c
> rename to virt/kvm/arm/vgic.c
> 



From kgene.kim at samsung.com  Tue May 14 08:40:47 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 14 May 2013 21:40:47 +0900
Subject: [PATCH RESEND] ARM: EXYNOS: no more support non-DT for EXYNOS SoCs
In-Reply-To: <5176975E.5000802@samsung.com>
References: <51642dab.e844440a.0ad1.ffffc13f@mx.google.com>
 <516571BC.9030909@samsung.com> <51756E98.9040606@samsung.com>
 <201304222111.45653.arnd@arndb.de> <5176975E.5000802@samsung.com>
Message-ID: <093a01ce50a0$42702bc0$c7508340$%kim@samsung.com>

Kukjin Kim wrote:
> 

[...]

> Note that I will send this removing non-DT exynos support patch to
> arm-soc tree after release v3.10-rc1.

Just note that, as we discussed, this patch will be queued for v3.11.

- Kukjin



From ulf.hansson at stericsson.com  Tue May 14 08:43:22 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Tue, 14 May 2013 14:43:22 +0200
Subject: [PATCH] mmc: mmci: Fixup regulator handling for vqmmc
Message-ID: <1368535402-8897-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

We can not rely on regulator_is_enabled to decide whether to
enable|disable the regulator. It would mean that the reference
counter for it is not balanced properly.

Instead keep track of our internal state by using a new flag in
the host struct, so we can take correct decisions.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   10 ++++++----
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038..2983c15 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1143,9 +1143,10 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		if (!IS_ERR(mmc->supply.vmmc))
 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 
-		if (!IS_ERR(mmc->supply.vqmmc) &&
-		    regulator_is_enabled(mmc->supply.vqmmc))
+		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
 			regulator_disable(mmc->supply.vqmmc);
+			host->vqmmc_enabled = false;
+		}
 
 		break;
 	case MMC_POWER_UP:
@@ -1161,12 +1162,13 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 		break;
 	case MMC_POWER_ON:
-		if (!IS_ERR(mmc->supply.vqmmc) &&
-		    !regulator_is_enabled(mmc->supply.vqmmc)) {
+		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
 			ret = regulator_enable(mmc->supply.vqmmc);
 			if (ret < 0)
 				dev_err(mmc_dev(mmc),
 					"failed to enable vqmmc regulator\n");
+			else
+				host->vqmmc_enabled = true;
 		}
 
 		pwr |= MCI_PWR_ON;
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 1f33ad5..1383c9c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -183,6 +183,7 @@ struct mmci_host {
 	unsigned int		cclk;
 	u32			pwr_reg;
 	u32			clk_reg;
+	bool			vqmmc_enabled;
 	struct mmci_platform_data *plat;
 	struct variant_data	*variant;
 
-- 
1.7.10



From linus.walleij at linaro.org  Tue May 14 08:47:19 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:47:19 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305111331.25405.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
Message-ID: <CACRpkda-wQyo8aYxbW9RJNcR3Kwe2w5AhaAuUHfaxBksa_Pm2A@mail.gmail.com>

On Sat, May 11, 2013 at 1:31 PM, Heiko St?bner <heiko at sntech.de> wrote:

> Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> with numerous virtual channels being mapped to a lot less physical ones.
> The driver therefore borrows a lot from the amba-pl08x driver in this
> regard. Functionality-wise the driver gains a memcpy ability in addition
> to the slave_sg one.
>
> The driver currently only supports the "newer" SoCs which can use any
> physical channel for any dma slave. Support for the older SoCs where
> each channel only supports a subset of possible dma slaves will have to
> be added later.
>
> Tested on a s3c2416-based board, memcpy using the dmatest module and
> slave_sg partially using the spi-s3c64xx driver.
>
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>

So have I understood correctly if I assume that *some* S3C
variants, i.e. this: arch/arm/mach-s3c64xx/dma.c
have a vanilla, unmodified, or just slightly modified
PL08x block, while this DMAC is something probably based on
the PL08x where some ASIC engineer has had a good time hacking
around in the VHDL code to meet some feature requirements.
Correct? Or plausible guess?

Exactly *how* far away from the pl08x hardware is it?

I guess you have already come to the conclusion that the
amba-pl08x.c driver cannot be augmented to handle this hardware
after some educated reading of that code?

But are really no parts reusable?

For example, if the LLIs have the same layout, could we split
out the LLI handling from amba-pl08x into a separate file and reuse
that?

The more you share with amba-pl08x the better for everyone,
I am positively sure. And please include Russell on the review
chain, he wrote the virtual channel abstraction.

If I was given the option amongst S3C work I would definatley
have augmented the amba-pl08x.c to handle the stuff in
arch/arm/mach-s3c64xx/dma.c *first* then started to work on
this driver, but I guess you might not be working on s3c64xx?

Yours,
Linus Walleij


From rjw at sisk.pl  Tue May 14 09:00:59 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Tue, 14 May 2013 15:00:59 +0200
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <093901ce509f$afe92f40$0fbb8dc0$%kim@samsung.com>
References: <cover.1365079581.git.viresh.kumar@linaro.org>
 <CAKohponkFB7ND38jv5oGnQLx8cq0b=uHTCmL3EERe6P54ijYhw@mail.gmail.com>
 <093901ce509f$afe92f40$0fbb8dc0$%kim@samsung.com>
Message-ID: <2001452.Fn2HjLbNED@vostro.rjw.lan>

On Tuesday, May 14, 2013 09:36:42 PM Kukjin Kim wrote:
> Viresh Kumar wrote:
> > 
> > On 13 May 2013 16:21, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> > > That doesn't matter I suppose.  I can take it, but please rebase it on
> > top
> > > of current linux-next.
> > 
> > I have already done that (attached). But i wasn't sure what Kukjin wants
> > as
> > he may report conflicts again and i will ask the same question for 3.12 :)
> > 
> Since this missed last time, this would be sent to upstream via samsung tree
> again. It means the conflicts should be handled by myself.
> 
> Rafael, if you don't mind, let me take this into Samsung tree for v3.11.

Sure, please go ahead.

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From linus.walleij at linaro.org  Tue May 14 08:54:50 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:54:50 +0200
Subject: [PATCH] pinctrl: enable build of pinctrl-imx6sl driver
In-Reply-To: <1368407762-12084-1-git-send-email-shawn.guo@linaro.org>
References: <1368407762-12084-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdaKJ-D2FbwSWNeqZrjDJ33nR3P26Yy_1mkPmX9zLTKrfA@mail.gmail.com>

On Mon, May 13, 2013 at 3:16 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> The pinctrl-imx6sl is in place.  Enable the build of it.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Applied for devel (v3.11) or is this to be considered a fix,
i.e. is someone compiling mainline kernels for the
IMX6SL already in v3.10?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 08:56:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:56:31 +0200
Subject: [RFC 19/42] drivers/pinctrl/spear: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368173847-5661-20-git-send-email-wsa@the-dreams.de>
References: <1368173847-5661-1-git-send-email-wsa@the-dreams.de>
 <1368173847-5661-20-git-send-email-wsa@the-dreams.de>
Message-ID: <CACRpkdYoDqsyE-oX5pBYx6v3txn=OjTLPoQOKkqaSLA5FNjYXw@mail.gmail.com>

On Fri, May 10, 2013 at 10:17 AM, Wolfram Sang <wsa at the-dreams.de> wrote:

> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>

Patch applied with Viresh's ACK.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Tue May 14 08:59:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 14:59:01 +0200
Subject: [PATCH] pinctrl: dove: add PMU functions to pinctrl
In-Reply-To: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367883368-27889-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdZVBiTJCPaSmPGTPs+aaRf2VQt+Zz=odL47ysg4a1c0RQ@mail.gmail.com>

On Tue, May 7, 2013 at 1:36 AM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> Dove power management unit can mux some special functions to mpp0-15.
> This patch adds support to set/get the current PMU function mapped
> to the corresponding mpp pins. The device tree documentation is also
> updated accordingly.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>

Patch applied with Jason's ACK.

Thanks!
LInus Walleij


From javi.merino at arm.com  Tue May 14 09:00:07 2013
From: javi.merino at arm.com (Javi Merino)
Date: Tue, 14 May 2013 14:00:07 +0100
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <20130514130005.GD29592@e102654-lin.cambridge.arm.com>

On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> On ARM multi-cluster systems coherency between cores running on
> different clusters is managed by the cache-coherent interconnect (CCI).
> It allows broadcasting of TLB invalidates and memory barriers and it
> guarantees cache coherency at system level through snooping of slave
> interfaces connected to it.
> 
> This patch enables the basic infrastructure required in Linux to handle and
> programme the CCI component.
> 
> Non-local variables used by the CCI management functions called by power
> down function calls after disabling the cache must be flushed out to main
> memory in advance, otherwise incoherency of those values may occur if they
> are sitting in the cache of some other CPU when power down functions
> execute. Driver code ensures that relevant data structures are flushed
> from inner and outer caches after the driver probe is completed.
> 
> CCI slave port resources are linked to set of CPUs through bus masters
> phandle properties that link the interface resources to masters node in
> the device tree.
> 
> Documentation describing the CCI DT bindings is provided with the patch.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> ---
>  Documentation/devicetree/bindings/arm/cci.txt | 161 ++++++++++
>  drivers/bus/Kconfig                           |   7 +
>  drivers/bus/Makefile                          |   2 +
>  drivers/bus/arm-cci.c                         | 420 ++++++++++++++++++++++++++
>  include/linux/arm-cci.h                       |  61 ++++
>  5 files changed, 651 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/cci.txt
>  create mode 100644 drivers/bus/arm-cci.c
>  create mode 100644 include/linux/arm-cci.h
> 

[...]

> diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> new file mode 100644
> index 0000000..000102f
> --- /dev/null
> +++ b/drivers/bus/arm-cci.c
> @@ -0,0 +1,420 @@
> +/*
> + * CCI cache coherent interconnect driver
> + *
> + * Copyright (C) 2013 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/arm-cci.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +
> +#include <asm/cacheflush.h>
> +#include <asm/smp_plat.h>
> +
> +#define DRIVER_NAME            "CCI"
> +
> +#define CCI_PORT_CTRL          0x0
> +#define CCI_CTRL_STATUS                0xc
> +
> +#define CCI_ENABLE_SNOOP_REQ   0x1
> +#define CCI_ENABLE_DVM_REQ     0x2
> +#define CCI_ENABLE_REQ         (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
> +
> +struct cci_nb_ports {
> +       unsigned int nb_ace;
> +       unsigned int nb_ace_lite;
> +};
> +
> +enum cci_ace_port_type {
> +       ACE_INVALID_PORT = 0x0,
> +       ACE_PORT,
> +       ACE_LITE_PORT,
> +};
> +
> +struct cci_ace_port {
> +       void __iomem *base;
> +       enum cci_ace_port_type type;
> +       struct device_node *dn;
> +};
> +
> +static struct cci_ace_port *ports;
> +static unsigned int nb_cci_ports;
> +
> +static void __iomem *cci_ctrl_base;
> +
> +struct cpu_port {
> +       u64 mpidr;
> +       u32 port;
> +};
> +/*
> + * Use the port MSB as valid flag, shift can be made dynamic
> + * by computing number of bits required for port indexes.
> + * Code disabling CCI cpu ports runs with D-cache invalidated
> + * and SCTLR bit clear so data accesses must be kept to a minimum
> + * to improve performance; for now shift is left static to
> + * avoid one more data access while disabling the CCI port.
> + */
> +#define PORT_VALID_SHIFT       31
> +#define PORT_VALID             (0x1 << PORT_VALID_SHIFT)
> +
> +static inline void init_cpu_port(struct cpu_port *port, u32 index, u32 mpidr)

The mpidr should be u64.

> +{
> +       port->port = PORT_VALID | index;
> +       port->mpidr = mpidr;
> +}
> +
> +static inline bool cpu_port_is_valid(struct cpu_port *port)
> +{
> +       return !!(port->port & PORT_VALID);
> +}
> +
> +static inline bool cpu_port_match(struct cpu_port *port, u32 mpidr)

Same here.

> +{
> +       return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
> +}
> +

Cheers,
Javi



From nicolas.ferre at atmel.com  Tue May 14 09:00:16 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 May 2013 15:00:16 +0200
Subject: [PATCH v2] net/macb: fix ISR clear-on-write behavior only for some SoC
In-Reply-To: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <1368536416-18364-1-git-send-email-nicolas.ferre@atmel.com>

Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.

Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
v2: - use DCFG1 bit 23 integration information instead of device tree
      compatibility string to retreive information about c-o-r vs. c-o-w ISR.
    - move configuration in macb_init_hw() function instead of probe() - at
      "open" time.

As I have changed the most of this patch, I will collect your Ack and feedback
just like a new patch. Thanks for your help...

Bye,

 drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++++++--
 drivers/net/ethernet/cadence/macb.h |  7 +++++++
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 6be513d..c89aa41 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -485,7 +485,8 @@ static void macb_tx_interrupt(struct macb *bp)
 	status = macb_readl(bp, TSR);
 	macb_writel(bp, TSR, status);
 
-	macb_writel(bp, ISR, MACB_BIT(TCOMP));
+	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+		macb_writel(bp, ISR, MACB_BIT(TCOMP));
 
 	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
 		(unsigned long)status);
@@ -738,7 +739,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
 			 * now.
 			 */
 			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
-			macb_writel(bp, ISR, MACB_BIT(RCOMP));
+			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+				macb_writel(bp, ISR, MACB_BIT(RCOMP));
 
 			if (napi_schedule_prep(&bp->napi)) {
 				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
@@ -1062,6 +1064,17 @@ static void macb_configure_dma(struct macb *bp)
 	}
 }
 
+/*
+ * Configure peripheral capacities according to integration options used
+ */
+static void macb_configure_caps(struct macb *bp)
+{
+	if (macb_is_gem(bp)) {
+		if (GEM_BF(IRQCOR, gem_readl(bp, DCFG1)) == 0)
+			bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
+	}
+}
+
 static void macb_init_hw(struct macb *bp)
 {
 	u32 config;
@@ -1084,6 +1097,7 @@ static void macb_init_hw(struct macb *bp)
 	bp->duplex = DUPLEX_HALF;
 
 	macb_configure_dma(bp);
+	macb_configure_caps(bp);
 
 	/* Initialize TX and RX buffers */
 	macb_writel(bp, RBQP, bp->rx_ring_dma);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 993d703..548c0ec 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -300,6 +300,8 @@
 #define MACB_REV_SIZE				16
 
 /* Bitfields in DCFG1. */
+#define GEM_IRQCOR_OFFSET			23
+#define GEM_IRQCOR_SIZE				1
 #define GEM_DBWDEF_OFFSET			25
 #define GEM_DBWDEF_SIZE				3
 
@@ -323,6 +325,9 @@
 #define MACB_MAN_READ				2
 #define MACB_MAN_CODE				2
 
+/* Capability mask bits */
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x1
+
 /* Bit manipulation macros */
 #define MACB_BIT(name)					\
 	(1 << MACB_##name##_OFFSET)
@@ -574,6 +579,8 @@ struct macb {
 	unsigned int 		speed;
 	unsigned int 		duplex;
 
+	u32			caps;
+
 	phy_interface_t		phy_interface;
 
 	/* AT91RM9200 transmit */
-- 
1.8.0



From sergei.shtylyov at cogentembedded.com  Tue May 14 09:02:15 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Tue, 14 May 2013 17:02:15 +0400
Subject: [PATCH v2 2/3] ARM: shmobile: lager: enable Ether
In-Reply-To: <9708378.xkqng7A9dx@avalon>
References: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
 <1368499171-22427-3-git-send-email-horms+renesas@verge.net.au>
 <9708378.xkqng7A9dx@avalon>
Message-ID: <519235D7.1050706@cogentembedded.com>

Hello.

On 14-05-2013 13:21, Laurent Pinchart wrote:

>> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
>> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

> Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

> Is there any ongoing work on DT bindings for sh-eth ?

    At least there was -- by Nobuhiro Iwamatsu. I don't think converting 
platform data to DT properties makes sense since sh_eth have some 
procedural platform data. I also don't think working on DT makes sense 
until the driver is cleaned up of all its #ifdef'ery (that work is 
partly being done by Nobuhiro and I'm planning to start the big #ifdef 
cleanup this week).

WBR, Sergei



From jonathan.austin at arm.com  Tue May 14 09:04:38 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:38 +0100
Subject: [PATCH 2/8] ARM: mpu: add header for MPU register layouts and region
 data
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-3-git-send-email-jonathan.austin@arm.com>

This commit adds definitions relevant to the ARM v7 PMSA compliant MPU.

The register layouts and region configuration data is made accessible to asm
as well as C-code so that it can be used in early bring-up of the MPU.

The mpu region information structs assume that the properties for the I/D side
are the same, though the implementation could be trivially extended for future
platforms where this is no-longer true.

The MPU_*_REGION defines are used for the basic, static MPU region setup.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/mpu.h |   72 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 arch/arm/include/asm/mpu.h

diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
new file mode 100644
index 0000000..bd48c0c
--- /dev/null
+++ b/arch/arm/include/asm/mpu.h
@@ -0,0 +1,72 @@
+#ifndef __ARM_MPU_H
+#define __ARM_MPU_H
+
+#ifdef CONFIG_ARM_MPU
+
+/* MPUIR layout */
+#define MPUIR_nU		1
+#define MPUIR_DREGION		8
+#define MPUIR_IREGION		16
+#define MPUIR_DREGION_SZMASK	(0xFF << MPUIR_DREGION)
+#define MPUIR_IREGION_SZMASK	(0xFF << MPUIR_IREGION)
+
+/* ID_MMFR0 data relevant to MPU */
+#define MMFR0_PMSA		(0xF << 4)
+#define MMFR0_PMSAv7		(3 << 4)
+
+/* MPU D/I Size Register fields */
+#define MPU_RSR_SZ		1
+#define MPU_RSR_EN		0
+
+/* The D/I RSR value for an enabled region spanning the whole of memory */
+#define MPU_RSR_ALL_MEM		63
+
+/* Individual bits in the DR/IR ACR */
+#define MPU_ACR_XN		(1 << 12)
+#define MPU_ACR_SHARED		(1 << 2)
+
+/* C, B and TEX[2:0] bits only have semantic meanings when grouped */
+#define MPU_RGN_CACHEABLE	0xB
+#define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#define MPU_RGN_STRONGLY_ORDERED 0
+
+/* Main region should only be shared for SMP */
+#ifdef CONFIG_SMP
+#define MPU_RGN_NORMAL		(MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#else
+#define MPU_RGN_NORMAL		MPU_RGN_CACHEABLE
+#endif
+
+/* Access permission bits of ACR (only define those that we use)*/
+#define MPU_AP_PL1RW_PL0RW	(0x3 << 8)
+#define MPU_AP_PL1RW_PL0R0	(0x2 << 8)
+#define MPU_AP_PL1RW_PL0NA	(0x1 << 8)
+
+/* For minimal static MPU region configurations */
+#define MPU_PROBE_REGION	0
+#define MPU_BG_REGION		1
+#define MPU_RAM_REGION		2
+
+/* Maximum number of regions Linux is interested in */
+#define MPU_MAX_REGIONS		16
+
+#ifndef __ASSEMBLY__
+
+struct mpu_rgn {
+	/* Assume same attributes for d/i-side  */
+	u32 drbar;
+	u32 drsr;
+	u32 dracr;
+};
+
+struct mpu_rgn_info {
+	u32 mpuir;
+	struct mpu_rgn rgns[MPU_MAX_REGIONS];
+};
+extern struct mpu_rgn_info mpu_rgn_info;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_MPU */
+
+#endif
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:39 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:39 +0100
Subject: [PATCH 3/8] ARM: mpu: add early bring-up code for the ARMv7
 PMSA-compliant MPU
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-4-git-send-email-jonathan.austin@arm.com>

This patch adds initial support for using the MPU, which is necessary for
SMP operation on PMSAv7 processors because it is the only way to ensure
memory is shared. This is an initial patch and full SMP support is added
later in this series.

The setup of the MPU is performed in a way analagous to that for the MMU:
Very early initialisation before the C environment is brought up, followed
by a sanity check and more complete initialisation in C.

This patch provides the simplest possible memory region configuration:
MPU_PROBE_REGION: Reserved for probing MPU details, not enabled
MPU_BG_REGION: A 'background' region that specifies all memory strongly ordered
MPU_RAM_REGION: A single shared, cacheable, normal region for the valid RAM.

In this early initialisation code we simply map the whole of the address
space with the BG_REGION and (at least) the kernel with the RAM_REGION. The
MPU has region alignment constraints that require us to round past the end
of the kernel.

As region 2 has a higher priority than region 1, it overrides the strongly-
ordered behaviour for RAM only.

Subsequent patches will add more complete initialisation from the C-world
and support for bringing up secondary CPUs.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
Cc: Hyok S. Choi <hyok.choi at samsung.com>
Cc: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/mpu.h   |    3 ++
 arch/arm/kernel/head-nommu.S |   87 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 90 insertions(+)

diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
index bd48c0c..0014834 100644
--- a/arch/arm/include/asm/mpu.h
+++ b/arch/arm/include/asm/mpu.h
@@ -50,6 +50,9 @@
 /* Maximum number of regions Linux is interested in */
 #define MPU_MAX_REGIONS		16
 
+#define MPU_DATA_SIDE		0
+#define MPU_INSTR_SIDE		1
+
 #ifndef __ASSEMBLY__
 
 struct mpu_rgn {
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 2d4bf12..0b0751f 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -17,8 +17,10 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/memory.h>
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
+#include <asm/mpu.h>
 
 /*
  * Kernel startup entry point.
@@ -59,6 +61,17 @@ ENTRY(stext)
 	movs	r10, r5				@ invalid processor (r5=0)?
 	beq	__error_p				@ yes, error 'p'
 
+#ifdef CONFIG_ARM_MPU
+	/* Calculate the size of a region covering just the kernel */
+	ldr	r5, =PHYS_OFFSET		@ Region start: PHYS_OFFSET
+	ldr     r6, =(_end)			@ Cover whole kernel
+	sub	r6, r6, r5			@ Minimum size of region to map
+	clz	r6, r6				@ Region size must be 2^N...
+	rsb	r6, r6, #31			@ ...so round up region size
+	lsl	r6, r6, #MPU_RSR_SZ		@ Put size in right field
+	orr	r6, r6, #(1 << MPU_RSR_EN)	@ Set region enabled bit
+	bl	__setup_mpu
+#endif
 	ldr	r13, =__mmap_switched		@ address to jump to after
 						@ initialising sctlr
 	adr	lr, BSYM(1f)			@ return (PIC) address
@@ -143,4 +156,78 @@ __after_proc_init:
 ENDPROC(__after_proc_init)
 	.ltorg
 
+#ifdef CONFIG_ARM_MPU
+
+
+/* Set which MPU region should be programmed */
+.macro set_region_nr tmp, rgnr
+	mov	\tmp, \rgnr			@ Use static region numbers
+	mcr	p15, 0, \tmp, c6, c2, 0		@ Write RGNR
+.endm
+
+/* Setup a single MPU region, either D or I side (D-side for unified) */
+.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
+	mcr	p15, 0, \bar, c6, c1, (0 + \side)	@ I/DRBAR
+	mcr	p15, 0, \acr, c6, c1, (4 + \side)	@ I/DRACR
+	mcr	p15, 0, \sr, c6, c1, (2 + \side)		@ I/DRSR
+.endm
+
+/*
+ * Setup the MPU and initial MPU Regions. We create the following regions:
+ * Region 0: Use this for probing the MPU details, so leave disabled.
+ * Region 1: Background region - covers the whole of RAM as strongly ordered
+ * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
+ *
+ * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
+*/
+
+ENTRY(__setup_mpu)
+
+	/* Probe for v7 PMSA compliance */
+	mrc	p15, 0, r0, c0, c1, 4		@ Read ID_MMFR0
+	and	r0, r0, #(MMFR0_PMSA)		@ PMSA field
+	teq	r0, #(MMFR0_PMSAv7)		@ PMSA v7
+	bne	__error_p			@ Fail: ARM_MPU on NOT v7 PMSA
+
+	/* Determine whether the D/I-side memory map is unified. We set the
+	 * flags here and continue to use them for the rest of this function */
+	mrc	p15, 0, r0, c0, c0, 4		@ MPUIR
+	ands	r5, r0, #MPUIR_DREGION_SZMASK	@ 0 size d region => No MPU
+	beq	__error_p			@ Fail: ARM_MPU and no MPU
+	tst	r0, #MPUIR_nU			@ MPUIR_nU = 0 for unified
+
+	/* Setup second region first to free up r6 */
+	set_region_nr r0, #MPU_RAM_REGION
+	isb
+	/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
+	ldr	r0, =PHYS_OFFSET		@ RAM starts at PHYS_OFFSET
+	ldr	r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
+
+	setup_region r0, r5, r6, MPU_DATA_SIDE	@ PHYS_OFFSET, shared, enabled
+	beq	1f				@ Memory-map not unified
+	setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
+1:	isb
+
+	/* First/background region */
+	set_region_nr r0, #MPU_BG_REGION
+	isb
+	/* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
+	mov	r0, #0				@ BG region starts at 0x0
+	ldr	r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
+	mov	r6, #MPU_RSR_ALL_MEM		@ 4GB region, enabled
+
+	setup_region r0, r5, r6, MPU_DATA_SIDE	@ 0x0, BG region, enabled
+	beq	2f				@ Memory-map not unified
+	setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
+2:	isb
+
+	/* Enable the MPU */
+	mrc	p15, 0, r0, c1, c0, 0		@ Read SCTLR
+	bic     r0, r0, #CR_BR			@ Disable the 'default mem-map'
+	orr	r0, r0, #CR_M			@ Set SCTRL.M (MPU on)
+	mcr	p15, 0, r0, c1, c0, 0		@ Enable MPU
+	isb
+	mov pc,lr
+ENDPROC(__setup_mpu)
+#endif
 #include "head-common.S"
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:36 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:36 +0100
Subject: [PATCH 0/8] ARM: MPU Support for PMSAv7 processors
Message-ID: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>

This patch series adds basic support for the PMSAv7-compliant MPU, which is
present on R-class cores.

The initial support implemented here lacks the ability to deal with setting
different region configurations for the I and D-side. No hardware is available
at the moment that supports this capability. It sets out a staic MPU mapping,
keeping one region for probing, one for the whole of memory and one for RAM.

The final patch in the series also creates a region protecting the vectors
from being accessed at PL0, reducing the possibility of programming errors
in userspace causing the kernel to panic as it is entered from user mode.

This series is the final step in enabling SMP with Cortex-R7 (and hence NOMMU)
by configuring the memory as shared.

In order to test these patches, you will need:
i) My nommu fixes series, which incorporates Will's NOMMU and SMP fixes
   - http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168106.html
ii) The Cortex-R7 support patches posted earlier to this list.
   - http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168128.html
iii) The multiplatform patches posted earlier to this list.
   - http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168106.html

Jonathan Austin (8):
  ARM: mpu: add PMSA related registers and bitfields to existing
    headers
  ARM: mpu: add header for MPU register layouts and region data
  ARM: mpu: add early bring-up code for the ARMv7 PMSA-compliant MPU
  ARM: mpu: add MPU probe and initialisation functions in C
  ARM: mpu: Complete initialisation of the MPU after reaching the
    C-world
  ARM: mpu: add MPU initialisation for secondary cores
  ARM: mpu: Allow enabling of the MPU via kconfig
  ARM: mpu: protect the vectors page with an MPU region

 arch/arm/Kconfig               |    4 +-
 arch/arm/Kconfig-nommu         |   11 ++
 arch/arm/include/asm/cp15.h    |    5 +
 arch/arm/include/asm/cputype.h |    1 +
 arch/arm/include/asm/mpu.h     |   76 ++++++++++++
 arch/arm/include/asm/smp.h     |    5 +-
 arch/arm/kernel/head-nommu.S   |  110 +++++++++++++++++
 arch/arm/kernel/signal.c       |    9 +-
 arch/arm/kernel/smp.c          |    8 +-
 arch/arm/mm/nommu.c            |  257 +++++++++++++++++++++++++++++++++++++++-
 10 files changed, 478 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/include/asm/mpu.h

-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:37 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:37 +0100
Subject: [PATCH 1/8] ARM: mpu: add PMSA related registers and bitfields to
 existing headers
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-2-git-send-email-jonathan.austin@arm.com>

This patch adds the following definitions relevant to the PMSA:

Add SCTLR bit 17, (CR_BR - Background Region bit) to the list of CR_*
bitfields. This bit determines whether to use the architecturally defined
memory map

Add the MPUIR to the available registers when using read_cpuid macro. The
MPUIR is the MPU type register.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
CC: "Uwe Kleine-K?nig" <u.kleine-koenig at pengutronix.de>
---
 arch/arm/include/asm/cp15.h    |    5 +++++
 arch/arm/include/asm/cputype.h |    1 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e..a524a23 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -23,6 +23,11 @@
 #define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
 #define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
 #define CR_DT	(1 << 16)
+#ifdef CONFIG_MMU
+#define CR_HA	(1 << 17)	/* Hardware management of Access Flag   */
+#else
+#define CR_BR	(1 << 17)	/* MPU Background region enable (PMSA)  */
+#endif
 #define CR_IT	(1 << 18)
 #define CR_ST	(1 << 19)
 #define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712..a29bc43 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,7 @@
 #define CPUID_CACHETYPE	1
 #define CPUID_TCM	2
 #define CPUID_TLBTYPE	3
+#define CPUID_MPUIR	4
 #define CPUID_MPIDR	5
 
 #define CPUID_EXT_PFR0	"c1, 0"
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:41 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:41 +0100
Subject: [PATCH 5/8] ARM: mpu: Complete initialisation of the MPU after
 reaching the C-world
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-6-git-send-email-jonathan.austin@arm.com>

Much like with the MMU, MPU initialisation is performed in two stages; the
first in the pre-C world and the 'real' initialisation during arch setup.

This patch wires in previously added MPU initialisation functions so that
the whole of memory is mapped with the appropriate region properties for
'normal' RAM (the appropriate properties depend on whether the system is
SMP).

Stub initialisation functions are added for the case that there MPU support
is not configured in to the kernel.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
CC: Hyok S. Choi <hyok.choi at samsung.com>
---
 arch/arm/mm/nommu.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 0a9eb24..44ccdd4 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -265,6 +265,9 @@ void __init mpu_setup(void)
 			mpu_max_regions());
 	}
 }
+#else
+static void sanity_check_meminfo_mpu(void) {}
+static void __init mpu_setup(void) {}
 #endif /* CONFIG_ARM_MPU */
 
 void __init arm_mm_memblock_reserve(void)
@@ -279,7 +282,9 @@ void __init arm_mm_memblock_reserve(void)
 
 void __init sanity_check_meminfo(void)
 {
-	phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+	phys_addr_t end;
+	sanity_check_meminfo_mpu();
+	end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
 	high_memory = __va(end - 1) + 1;
 }
 
@@ -290,6 +295,7 @@ void __init sanity_check_meminfo(void)
 void __init paging_init(struct machine_desc *mdesc)
 {
 	early_trap_init((void *)CONFIG_VECTORS_BASE);
+	mpu_setup();
 	bootmem_init();
 }
 
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:40 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:40 +0100
Subject: [PATCH 4/8] ARM: mpu: add MPU probe and initialisation functions in C
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-5-git-send-email-jonathan.austin@arm.com>

This patch adds new functions for probing and initialising the ARMv7
PMSA-compliant MPU.

These use the pre-defined and reserved MPU_PROBE_REGION for establishing
properties of the MPU, which is necessary because certain probe operations
require modifying region properties and reading back the results.

This patch also introduces a minimal sanity_check_meminfo_mpu function, that
ensures that the memory set-up passed to the kernel can be used in conjunction
with the MPU. The base address of a region must be aligned to the region size,
otherwise behavior is unpredictable and region sizes can only be specified as a
power-of-two. To simplify the satisfaction of these requirements this
implementation currently enforces that all memory is contiguous from
PHYS_OFFSET, merging banks that are contiguous but passed in separately.

The functions are added in this patch but wired in to the boot process later
in the series.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
CC: Hyok S. Choi <hyok.choi at samsung.com>
---
 arch/arm/mm/nommu.c |  249 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 249 insertions(+)

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f..0a9eb24 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -8,6 +8,7 @@
 #include <linux/pagemap.h>
 #include <linux/io.h>
 #include <linux/memblock.h>
+#include <linux/kernel.h>
 
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
@@ -15,9 +16,257 @@
 #include <asm/setup.h>
 #include <asm/traps.h>
 #include <asm/mach/arch.h>
+#include <asm/cputype.h>
+#include <asm/mpu.h>
 
 #include "mm.h"
 
+#ifdef CONFIG_ARM_MPU
+struct mpu_rgn_info mpu_rgn_info;
+
+/* Region number */
+static void rgnr_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
+}
+
+/* Data-side / unified region attributes */
+
+/* Region access control register */
+static void dracr_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
+}
+
+/* Region size register */
+static void drsr_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
+}
+
+/* Region base address register */
+static void drbar_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
+}
+
+static u32 drbar_read(void)
+{
+	u32 v;
+	asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
+	return v;
+}
+/* Optional instruction-side region attributes */
+
+/* I-side Region access control register */
+static void iracr_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
+}
+
+/* I-side Region size register */
+static void irsr_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
+}
+
+/* I-side Region base address register */
+static void irbar_write(u32 v)
+{
+	asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
+}
+
+static unsigned long irbar_read(void)
+{
+	unsigned long v;
+	asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
+	return v;
+}
+
+/* MPU initialisation functions */
+void __init sanity_check_meminfo_mpu(void)
+{
+	int i;
+	struct membank *bank = meminfo.bank;
+	phys_addr_t phys_offset = PHYS_OFFSET;
+	phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
+
+	/* Initially only use memory continuous from PHYS_OFFSET */
+	if (bank_phys_start(&bank[0]) != phys_offset)
+		panic("First memory bank must be contiguous from PHYS_OFFSET");
+
+	/* Banks have already been sorted by start address */
+	for (i = 1; i < meminfo.nr_banks; i++) {
+		if (bank[i].start <= bank_phys_end(&bank[0]) &&
+		    bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
+			bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
+		} else {
+			pr_notice("Ignoring RAM after 0x%.8lx. "
+			"First non-contiguous (ignored) bank start: 0x%.8lx\n",
+				(unsigned long)bank_phys_end(&bank[0]),
+				(unsigned long)bank_phys_start(&bank[i]));
+			break;
+		}
+	}
+	/* All contiguous banks are now merged in to the first bank */
+	meminfo.nr_banks = 1;
+	specified_mem_size = bank[0].size;
+
+	/*
+	 * MPU has curious alignment requirements: Size must be power of 2, and
+	 * region start must be aligned to the region size
+	 */
+	if (phys_offset != 0)
+		pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
+
+	/*
+	 * Maximum aligned region might overflow phys_addr_t if phys_offset is
+	 * 0. Hence we keep everything below 4G until we take the smaller of
+	 * the aligned_region_size and rounded_mem_size, one of which is
+	 * guaranteed to be smaller than the maximum physical address.
+	 */
+	aligned_region_size = (phys_offset - 1) ^ (phys_offset);
+	/* Find the max power-of-two sized region that fits inside our bank */
+	rounded_mem_size = (1 <<  __fls(bank[0].size)) - 1;
+
+	/* The actual region size is the smaller of the two */
+	aligned_region_size = aligned_region_size < rounded_mem_size
+				? aligned_region_size + 1
+				: rounded_mem_size + 1;
+
+	if (aligned_region_size != specified_mem_size)
+		pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
+				(unsigned long)specified_mem_size,
+				(unsigned long)aligned_region_size);
+
+	meminfo.bank[0].size = aligned_region_size;
+	pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
+		(unsigned long)phys_offset,
+		(unsigned long)aligned_region_size,
+		(unsigned long)bank_phys_end(&bank[0]));
+
+}
+
+static int mpu_present(void)
+{
+	return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
+}
+
+static int mpu_max_regions(void)
+{
+	/*
+	 * We don't support a different number of I/D side regions so if we
+	 * have separate instruction and data memory maps then return
+	 * whichever side has a smaller number of supported regions.
+	 */
+	u32 dregions, iregions, mpuir;
+	mpuir = read_cpuid(CPUID_MPUIR);
+
+	dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
+
+	/* Check for separate d-side and i-side memory maps */
+	if (mpuir & MPUIR_nU)
+		iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
+
+	/* Use the smallest of the two maxima */
+	return min(dregions, iregions);
+}
+
+static int mpu_iside_independent(void)
+{
+	/* MPUIR.nU specifies whether there is *not* a unified memory map */
+	return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
+}
+
+static int mpu_min_region_order(void)
+{
+	u32 drbar_result, irbar_result;
+	/* We've kept a region free for this probing */
+	rgnr_write(MPU_PROBE_REGION);
+	isb();
+	/*
+	 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
+	 * region order
+	*/
+	drbar_write(0xFFFFFFFC);
+	drbar_result = irbar_result = drbar_read();
+	drbar_write(0x0);
+	/* If the MPU is non-unified, we use the larger of the two minima*/
+	if (mpu_iside_independent()) {
+		irbar_write(0xFFFFFFFC);
+		irbar_result = irbar_read();
+		irbar_write(0x0);
+	}
+	isb(); /* Ensure that MPU region operations have completed */
+	/* Return whichever result is larger */
+	return __ffs(max(drbar_result, irbar_result));
+}
+
+static int mpu_setup_region(unsigned int number, phys_addr_t start,
+			unsigned int size_order, unsigned int properties)
+{
+	u32 size_data;
+
+	/* We kept a region free for probing resolution of MPU regions*/
+	if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
+		return -ENOENT;
+
+	if (size_order > 32)
+		return -ENOMEM;
+
+	if (size_order < mpu_min_region_order())
+		return -ENOMEM;
+
+	/* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
+	size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
+
+	dsb(); /* Ensure all previous data accesses occur with old mappings */
+	rgnr_write(number);
+	isb();
+	drbar_write(start);
+	dracr_write(properties);
+	isb(); /* Propagate properties before enabling region */
+	drsr_write(size_data);
+
+	/* Check for independent I-side registers */
+	if (mpu_iside_independent()) {
+		irbar_write(start);
+		iracr_write(properties);
+		isb();
+		irsr_write(size_data);
+	}
+	isb();
+
+	/* Store region info (we treat i/d side the same, so only store d) */
+	mpu_rgn_info.rgns[number].dracr = properties;
+	mpu_rgn_info.rgns[number].drbar = start;
+	mpu_rgn_info.rgns[number].drsr = size_data;
+	return 0;
+}
+
+/*
+* Set up default MPU regions, doing nothing if there is no MPU
+*/
+void __init mpu_setup(void)
+{
+	int region_err;
+	if (!mpu_present())
+		return;
+
+	region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
+					ilog2(meminfo.bank[0].size),
+					MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
+	if (region_err) {
+		panic("MPU region initialization failure! %d", region_err);
+	} else {
+		pr_info("Using ARMv7 PMSA Compliant MPU. "
+			 "Region independence: %s, Max regions: %d\n",
+			mpu_iside_independent() ? "Yes" : "No",
+			mpu_max_regions());
+	}
+}
+#endif /* CONFIG_ARM_MPU */
+
 void __init arm_mm_memblock_reserve(void)
 {
 	/*
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:43 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:43 +0100
Subject: [PATCH 7/8] ARM: mpu: Allow enabling of the MPU via kconfig
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-8-git-send-email-jonathan.austin@arm.com>

Allows the user to select MPU support when compiling for ARM processors
that support the PMSAv7.

This ensures that CONFIG_SMP depends on the MPU in the case that no MMU
is present.

CONFIG_SMP_ON_UP is not implemented for nommu, so introduce an MMU
dependency there.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig       |    4 ++--
 arch/arm/Kconfig-nommu |   11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..e337618 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1413,7 +1413,7 @@ config SMP
 	depends on CPU_V6K || CPU_V7
 	depends on GENERIC_CLOCKEVENTS
 	depends on HAVE_SMP
-	depends on MMU
+	depends on MMU || ARM_MPU
 	select USE_GENERIC_SMP_HELPERS
 	help
 	  This enables support for systems with more than one CPU. If you have
@@ -1434,7 +1434,7 @@ config SMP
 
 config SMP_ON_UP
 	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
-	depends on SMP && !XIP_KERNEL
+	depends on SMP && !XIP_KERNEL && MMU
 	default y
 	help
 	  SMP kernels contain instructions which fail on non-SMP processors.
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 2cef8e1..8ceed61 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -50,3 +50,14 @@ config REMAP_VECTORS_TO_RAM
 	  Otherwise, say 'y' here.  In this case, the kernel will require
 	  external support to redirect the hardware exception vectors to
 	  the writable versions located at DRAM_BASE.
+
+config ARM_MPU
+       bool 'Use the ARM v7 PMSA Compliant MPU'
+       default y
+       help
+         Some ARM systems without an MMU have instead a Memory Protection
+         Unit (MPU) that defines the type and permissions for regions of
+         memory.
+
+         If your CPU has an MPU then you should choose 'y' here unless you
+         know that you do not want to use the MPU.
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:42 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:42 +0100
Subject: [PATCH 6/8] ARM: mpu: add MPU initialisation for secondary cores
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-7-git-send-email-jonathan.austin@arm.com>

The MPU initialisation on the primary core is performed in two stages, one
minimal stage to ensure the CPU can boot and a second one after
sanity_check_meminfo. As the memory configuration is known by the time we
boot secondary cores only a single step is necessary, provided the values
for DRSR are passed to secondaries.

This patch implements this arrangement. The configuration generated for the
MPU regions is made available to the secondary core, which can then use the
asm MPU intialisation code to program a complete region configuration.

This is necessary for SMP configurations without an MMU, as the MPU
initialisation is the only way to ensure that memory is specified as
'shared'.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
CC: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/smp.h   |    5 ++++-
 arch/arm/kernel/head-nommu.S |    7 +++++++
 arch/arm/kernel/smp.c        |    8 ++++++--
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index d3a22be..a8cae71c 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -65,7 +65,10 @@ asmlinkage void secondary_start_kernel(void);
  * Initial data for bringing up a secondary CPU.
  */
 struct secondary_data {
-	unsigned long pgdir;
+	union {
+		unsigned long mpu_rgn_szr;
+		unsigned long pgdir;
+	};
 	unsigned long swapper_pg_dir;
 	void *stack;
 };
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 0b0751f..3d3071b 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -103,6 +103,13 @@ ENTRY(secondary_startup)
 
 	adr	r4, __secondary_data
 	ldmia	r4, {r7, r12}
+
+#ifdef CONFIG_ARM_MPU
+	/* Use MPU region info supplied by __cpu_up */
+	ldr	r6, [r7]			@ get secondary_data.mpu_szr
+	bl      __setup_mpu			@ Initialize the MPU
+#endif
+
 	adr	lr, BSYM(__after_proc_init)	@ return address
 	mov	r13, r12			@ __secondary_switched address
  ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index b476002..c53d5e9 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -45,6 +45,7 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
+#include <asm/mpu.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -87,6 +88,10 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 	 * its stack and the page tables.
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
+#ifdef CONFIG_ARM_MPU
+	secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
+#endif
+
 #ifdef CONFIG_MMU
 	secondary_data.pgdir = virt_to_phys(idmap_pgd);
 	secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
@@ -114,9 +119,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 		pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
 	}
 
-	secondary_data.stack = NULL;
-	secondary_data.pgdir = 0;
 
+	memset(&secondary_data, 0, sizeof(secondary_data));
 	return ret;
 }
 
-- 
1.7.9.5




From jonathan.austin at arm.com  Tue May 14 09:04:44 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 14 May 2013 14:04:44 +0100
Subject: [PATCH 8/8] ARM: mpu: protect the vectors page with an MPU region
In-Reply-To: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
References: <1368536684-13608-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1368536684-13608-9-git-send-email-jonathan.austin@arm.com>

Without an MMU it is possible for userspace programs to start executing code
in places that they have no business executing. The MPU allows some level of
protection against this.

This patch protects the vectors page from access by userspace processes.
Userspace tasks that dereference a null pointer are already protected by an
svc at 0x0 that kills them. However when tasks use an offset from a null
pointer (eg a function in a null struct) they miss this carefully placed svc
and enter the exception vectors in user mode, ending up in the kernel.

This patch causes programs that do this to receive a SEGV instead of happily
entering the kernel in user-mode, and hence avoid a 'Bad Mode' panic.

As part of this change it is necessary to make sigreturn happen via the
stack when there is not an sa_restorer function. This change is invisible to
userspace, and irrelevant to code compiled using a uClibc toolchain, which
always uses an sa_restorer function.

Because we don't get to remap the vectors in !MMU kuser_helpers are not
in a defined location, and hence aren't usable. This means we don't need to
worry about keeping them accessible from PL0

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
CC: Nicolas Pitre <nico at linaro.org>
CC: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/mpu.h   |    1 +
 arch/arm/kernel/head-nommu.S |   16 ++++++++++++++++
 arch/arm/kernel/signal.c     |    9 +++++++--
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
index 0014834..c3247cc 100644
--- a/arch/arm/include/asm/mpu.h
+++ b/arch/arm/include/asm/mpu.h
@@ -46,6 +46,7 @@
 #define MPU_PROBE_REGION	0
 #define MPU_BG_REGION		1
 #define MPU_RAM_REGION		2
+#define MPU_VECTORS_REGION	3
 
 /* Maximum number of regions Linux is interested in */
 #define MPU_MAX_REGIONS		16
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 3d3071b..0640704 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -21,6 +21,7 @@
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
 #include <asm/mpu.h>
+#include <asm/page.h>
 
 /*
  * Kernel startup entry point.
@@ -184,6 +185,7 @@ ENDPROC(__after_proc_init)
  * Region 0: Use this for probing the MPU details, so leave disabled.
  * Region 1: Background region - covers the whole of RAM as strongly ordered
  * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
+ * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
  *
  * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
 */
@@ -228,6 +230,20 @@ ENTRY(__setup_mpu)
 	setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
 2:	isb
 
+	/* Vectors region */
+	set_region_nr r0, #MPU_VECTORS_REGION
+	isb
+	/* Shared, inaccessible to PL0, rw PL1 */
+	mov	r0, #CONFIG_VECTORS_BASE	@ Cover from VECTORS_BASE
+	ldr	r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
+	/* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
+	mov	r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
+
+	setup_region r0, r5, r6, MPU_DATA_SIDE	@ VECTORS_BASE, PL0 NA, enabled
+	beq	3f				@ Memory-map not unified
+	setup_region r0, r5, r6, MPU_INSTR_SIDE	@ VECTORS_BASE, PL0 NA, enabled
+3:	isb
+
 	/* Enable the MPU */
 	mrc	p15, 0, r0, c1, c0, 0		@ Read SCTLR
 	bic     r0, r0, #CR_BR			@ Disable the 'default mem-map'
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 296786b..1c16c35 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -392,14 +392,19 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig,
 		if (ksig->ka.sa.sa_flags & SA_SIGINFO)
 			idx += 3;
 
+		/*
+		 * Put the sigreturn code on the stack no matter which return
+		 * mechanism we use in order to remain ABI compliant
+		 */
 		if (__put_user(sigreturn_codes[idx],   rc) ||
 		    __put_user(sigreturn_codes[idx+1], rc+1))
 			return 1;
 
-		if (cpsr & MODE32_BIT) {
+		if ((cpsr & MODE32_BIT) && !IS_ENABLED(CONFIG_ARM_MPU)) {
 			/*
 			 * 32-bit code can use the new high-page
-			 * signal return code support.
+			 * signal return code support except when the MPU has
+			 * protected the vectors page from PL0
 			 */
 			retcode = KERN_SIGRETURN_CODE + (idx << 2) + thumb;
 		} else {
-- 
1.7.9.5




From will.deacon at arm.com  Tue May 14 09:05:40 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 14 May 2013 14:05:40 +0100
Subject: [PATCH v3 3/7] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <1368529900-22572-4-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-4-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130514130539.GI21175@mudshark.cambridge.arm.com>

On Tue, May 14, 2013 at 12:11:36PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required if running on a SMP capable platform
> (the HW PTW can snoop other cpus' L1).
> 
> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> a no-op for SMP ARMv7.
> 
> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Acked-by: Will Deacon <will.deacon at arm.com>

Will


From 21cnbao at gmail.com  Tue May 14 09:07:52 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 14 May 2013 21:07:52 +0800
Subject: [PATCH] watchdog: sirf: add watchdog driver of CSR SiRFprimaII and
 SiRFatlasVI
Message-ID: <1368536872-2189-1-git-send-email-21cnbao@gmail.com>

From: Xianglong Du <Xianglong.Du at csr.com>

On CSR SiRFprimaII and SiRFatlasVI, the 6th timer can act as a Watchdog timer
when the Watchdog mode is enabled.

watchdog occur when TIMER watchdog counter matches the value software set, when
this event occur, the effect is the same as system software reset.

Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 .../devicetree/bindings/watchdog/sirfsoc_wdt.txt   |   15 ++
 arch/arm/boot/dts/atlas6.dtsi                      |    2 +-
 arch/arm/boot/dts/prima2.dtsi                      |    2 +-
 arch/arm/configs/prima2_defconfig                  |    3 +-
 drivers/watchdog/Kconfig                           |    8 +
 drivers/watchdog/Makefile                          |    1 +
 drivers/watchdog/sirfsoc_wdt.c                     |  250 ++++++++++++++++++++
 7 files changed, 278 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt
 create mode 100644 drivers/watchdog/sirfsoc_wdt.c

diff --git a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt
new file mode 100644
index 0000000..b2af5fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt
@@ -0,0 +1,15 @@
+SiRFSoC Timer and Watchdog Timer(WDT) Controller
+
+Required properties:
+- compatible: "sirf,prima2-tick", "sirf,prima2-wdt"
+- reg: Address range of tick timer/WDT register set
+- interrupts: interrupt number to the cpu
+
+Example:
+
+timer at b0020000 {
+	compatible = "sirf,prima2-tick", "sirf,prima2-wdt";
+	reg = <0xb0020000 0x1000>;
+	interrupts = <0>;
+};
+
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 7d1a279..c101f3e 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -155,7 +155,7 @@
 			       <0x56000000 0x56000000 0x1b00000>;
 
 			timer at b0020000 {
-				compatible = "sirf,prima2-tick";
+				compatible = "sirf,prima2-tick", "sirf,prima2-wdt";
 				reg = <0xb0020000 0x1000>;
 				interrupts = <0>;
 			};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..3c76dc2 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -172,7 +172,7 @@
 			ranges = <0xb0000000 0xb0000000 0x180000>;
 
 			timer at b0020000 {
-				compatible = "sirf,prima2-tick";
+				compatible = "sirf,prima2-tick", "sirf,prima2-wdt";
 				reg = <0xb0020000 0x1000>;
 				interrupts = <0>;
 			};
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index 002a1ce..a1d7c67 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_RELAY=y
@@ -39,6 +38,8 @@ CONFIG_SPI=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e89fc31..fe005a8 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -391,6 +391,14 @@ config RETU_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called retu_wdt.
 
+config SIRFSOC_WATCHDOG
+	tristate "SiRFSOC watchdog"
+	depends on ARCH_SIRF
+	default y
+	help
+	  Support for CSR SiRFprimaII and SiRFatlasVI watchdog. When
+	  the watchdog triggers the system will be reset.
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a300b94..9064f6a 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
 obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
 obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
 obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
+obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/sirfsoc_wdt.c b/drivers/watchdog/sirfsoc_wdt.c
new file mode 100644
index 0000000..ab3dd42
--- /dev/null
+++ b/drivers/watchdog/sirfsoc_wdt.c
@@ -0,0 +1,250 @@
+/*
+ * Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
+ *
+ * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/platform_device.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+
+#define SIRFSOC_TIMER_COUNTER_LO	0x0000
+#define SIRFSOC_TIMER_MATCH_0		0x0008
+#define SIRFSOC_TIMER_INT_EN		0x0024
+#define SIRFSOC_TIMER_WATCHDOG_EN	0x0028
+#define SIRFSOC_TIMER_LATCH		0x0030
+#define SIRFSOC_TIMER_LATCHED_LO	0x0034
+
+#define SIRFSOC_TIMER_WDT_INDEX		5
+
+#define SIRFSOC_WDT_MIN_TIMEOUT		30		/* 30 secs */
+#define SIRFSOC_WDT_MAX_TIMEOUT		(10 * 60)	/* 10 mins */
+#define SIRFSOC_WDT_DEFAULT_TIMEOUT	30		/* 30 secs */
+
+
+static unsigned int default_timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT;
+module_param(default_timeout, uint, 0);
+MODULE_PARM_DESC(default_timeout, "Default watchdog timeout (in seconds)");
+
+static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd)
+{
+	u32 counter, match;
+	int time_left;
+
+	counter = readl(watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_COUNTER_LO);
+	match = readl(watchdog_get_drvdata(wdd) +
+		SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
+
+	if (match >= counter) {
+		time_left = match-counter;
+	} else {
+		/* rollover */
+		time_left = (0xffffffffUL - counter) + match;
+	}
+
+	return time_left / CLOCK_TICK_RATE;
+}
+
+static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd)
+{
+	u32 counter, timeout_ticks;
+
+	timeout_ticks = wdd->timeout * CLOCK_TICK_RATE;
+
+	/* Enable the latch before reading the LATCH_LO register */
+	writel(1, watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_LATCH);
+
+	/* Set the TO value */
+	counter = readl(watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_LATCHED_LO);
+
+	if ((0xffffffffUL - counter) >= timeout_ticks) {
+		counter += timeout_ticks;
+	} else {
+		/* Rollover */
+		counter = timeout_ticks - (0xffffffffUL - counter);
+	}
+	writel(counter, watchdog_get_drvdata(wdd) +
+		SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
+
+	return 0;
+}
+
+static int sirfsoc_wdt_enable(struct watchdog_device *wdd)
+{
+	sirfsoc_wdt_updatetimeout(wdd);
+
+	/*
+	 * NOTE: If interrupt is not enabled
+	 * then WD-Reset doesn't get generated at all.
+	 */
+	writel(readl(watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_INT_EN)
+		| (1 << SIRFSOC_TIMER_WDT_INDEX),
+		watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_INT_EN);
+	writel(1, watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_WATCHDOG_EN);
+
+	return 0;
+}
+
+static int sirfsoc_wdt_disable(struct watchdog_device *wdd)
+{
+	writel(0, watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_WATCHDOG_EN);
+	writel(readl(watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_INT_EN)
+		& (~(1 << SIRFSOC_TIMER_WDT_INDEX)),
+		watchdog_get_drvdata(wdd) + SIRFSOC_TIMER_INT_EN);
+
+	return 0;
+}
+
+static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
+{
+	if (to < SIRFSOC_WDT_MIN_TIMEOUT)
+		to = SIRFSOC_WDT_MIN_TIMEOUT;
+	if (to > SIRFSOC_WDT_MAX_TIMEOUT)
+		to = SIRFSOC_WDT_MAX_TIMEOUT;
+	wdd->timeout = to;
+	sirfsoc_wdt_updatetimeout(wdd);
+
+	return 0;
+}
+
+#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
+
+static const struct watchdog_info sirfsoc_wdt_ident = {
+	.options          =     OPTIONS,
+	.firmware_version =	0,
+	.identity         =	"SiRFSOC Watchdog",
+};
+
+static struct watchdog_ops sirfsoc_wdt_ops = {
+	.owner = THIS_MODULE,
+	.start = sirfsoc_wdt_enable,
+	.stop = sirfsoc_wdt_disable,
+	.get_timeleft = sirfsoc_wdt_gettimeleft,
+	.ping = sirfsoc_wdt_updatetimeout,
+	.set_timeout = sirfsoc_wdt_settimeout,
+};
+
+static struct watchdog_device sirfsoc_wdd = {
+	.info = &sirfsoc_wdt_ident,
+	.ops = &sirfsoc_wdt_ops,
+	.timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT,
+	.min_timeout = SIRFSOC_WDT_MIN_TIMEOUT,
+	.max_timeout = SIRFSOC_WDT_MAX_TIMEOUT,
+};
+
+static int sirfsoc_wdt_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+	void __iomem *base;
+
+	/* reserve static register mappings */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "sirfsoc wdt: could not get mem resources\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (!base) {
+		dev_err(&pdev->dev, "sirfsoc wdt: could not remap the mem\n");
+		ret = -EADDRNOTAVAIL;
+		goto out;
+	}
+	watchdog_set_drvdata(&sirfsoc_wdd, base);
+
+	sirfsoc_wdd.timeout = default_timeout;
+
+	ret = watchdog_register_device(&sirfsoc_wdd);
+	if (!!ret)
+		goto out;
+
+	platform_set_drvdata(pdev, &sirfsoc_wdd);
+
+	return 0;
+
+out:
+	return ret;
+}
+
+static int sirfsoc_wdt_remove(struct platform_device *pdev)
+{
+	struct watchdog_device *wdd = platform_get_drvdata(pdev);
+
+	sirfsoc_wdt_disable(wdd);
+
+	return 0;
+}
+
+static void sirfsoc_wdt_shutdown(struct platform_device *pdev)
+{
+	struct watchdog_device *wdd = platform_get_drvdata(pdev);
+
+	sirfsoc_wdt_disable(wdd);
+}
+
+#ifdef	CONFIG_PM
+
+static int sirfsoc_wdt_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int sirfsoc_wdt_resume(struct device *dev)
+{
+	struct watchdog_device *wdd = dev_get_drvdata(dev);
+
+	/*
+	 * NOTE: Since timer controller registers settings are saved
+	 * and restored back by the timer-prima2.c, so we need not
+	 * update WD settings except refreshing timeout.
+	 */
+	sirfsoc_wdt_updatetimeout(wdd);
+
+	return 0;
+}
+
+#else
+#define	sirfsoc_wdt_suspend		NULL
+#define	sirfsoc_wdt_resume		NULL
+#endif
+
+static const struct dev_pm_ops sirfsoc_wdt_pm_ops = {
+	.suspend = sirfsoc_wdt_suspend,
+	.resume = sirfsoc_wdt_resume,
+};
+
+static const struct of_device_id sirfsoc_wdt_of_match[] = {
+	{ .compatible = "sirf,prima2-wdt"},
+	{},
+};
+MODULE_DEVICE_TABLE(of, sirfsoc_wdt_of_match);
+
+static struct platform_driver sirfsoc_wdt_driver = {
+	.driver = {
+		.name = "sirfsoc-wdt",
+		.owner = THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm = &sirfsoc_wdt_pm_ops,
+#endif
+		.of_match_table	= of_match_ptr(sirfsoc_wdt_of_match),
+	},
+	.probe = sirfsoc_wdt_probe,
+	.remove = sirfsoc_wdt_remove,
+	.shutdown = sirfsoc_wdt_shutdown,
+};
+module_platform_driver(sirfsoc_wdt_driver);
+
+MODULE_DESCRIPTION("SiRF SoC watchdog driver");
+MODULE_AUTHOR("Xianglong Du <Xianglong.Du at csr.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+MODULE_ALIAS("platform:sirfsoc-wdt");
-- 
1.7.4.1



From marc.zyngier at arm.com  Tue May 14 09:09:13 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 14:09:13 +0100
Subject: [PATCH v2 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <51922FF3.4060300@redhat.com>
References: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
 <1368534653-23133-3-git-send-email-marc.zyngier@arm.com>
 <51922FF3.4060300@redhat.com>
Message-ID: <51923779.7030304@arm.com>

On 14/05/13 13:37, Paolo Bonzini wrote:
> Il 14/05/2013 14:30, Marc Zyngier ha scritto:
>> As requested by the KVM maintainers, remove the addprefix used to
>> refer to the main KVM code from the arch code, and replace it with
>> a KVM variable that does the same thing.
>>
>> Cc: Paolo Bonzini <pbonzini at redhat.com>
>> Cc: Gleb Natapov <gleb at redhat.com>
>> Cc: Christoffer Dall <cdall at cs.columbia.edu>
>> Cc: Xiantao Zhang <xiantao.zhang at intel.com>
>> Cc: Tony Luck <tony.luck at intel.com>
>> Cc: Fenghua Yu <fenghua.yu at intel.com>
>> Cc: Alexander Graf <agraf at suse.de>
>> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
>> Cc: Christian Borntraeger <borntraeger at de.ibm.com>
>> Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> 
> Thanks,
> 
> Reviewed-by: Paolo Bonzini <pbonzini at redhat.com>

Actually, there's a catch (see below)...

>> ---
>>  arch/arm/kvm/Makefile     |  2 +-
>>  arch/ia64/kvm/Makefile    |  7 ++++---
>>  arch/powerpc/kvm/Makefile | 13 +++++++------
>>  arch/s390/kvm/Makefile    |  3 ++-
>>  arch/x86/kvm/Makefile     | 13 +++++++------
>>  5 files changed, 21 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
>> index 9184a49..d99bee4 100644
>> --- a/arch/arm/kvm/Makefile
>> +++ b/arch/arm/kvm/Makefile
>> @@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
>>  AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
>>  
>>  KVM := ../../../virt/kvm
>> -kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
>> +kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
>>  
>>  obj-y += kvm-arm.o init.o interrupts.o
>>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
>> diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
>> index 1a40537..18e45ec 100644
>> --- a/arch/ia64/kvm/Makefile
>> +++ b/arch/ia64/kvm/Makefile
>> @@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
>>  
>>  ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
>>  asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
>> +KVM := ../../../virt/kvm
>>  
>> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
>> -		coalesced_mmio.o irq_comm.o)
>> +common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
>> +		$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
>>  
>>  ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
>> -common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
>> +common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
>>  endif
>>  
>>  kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
>> diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
>> index 422de3f..008cd85 100644
>> --- a/arch/powerpc/kvm/Makefile
>> +++ b/arch/powerpc/kvm/Makefile
>> @@ -5,9 +5,10 @@
>>  subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
>>  
>>  ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
>> +KVM := ../../../virt/kvm
>>  
>> -common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
>> -						eventfd.o)
>> +common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
>> +		$(KVM)/eventfd.o
>>  
>>  CFLAGS_44x_tlb.o  := -I.
>>  CFLAGS_e500_mmu.o := -I.
>> @@ -53,7 +54,7 @@ kvm-e500mc-objs := \
>>  kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
>>  
>>  kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
>> -	../../../virt/kvm/coalesced_mmio.o \
>> +	$(KVM)/coalesced_mmio.o \
>>  	fpu.o \
>>  	book3s_paired_singles.o \
>>  	book3s_pr.o \
>> @@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
>>  	book3s_xics.o
>>  
>>  kvm-book3s_64-module-objs := \
>> -	../../../virt/kvm/kvm_main.o \
>> -	../../../virt/kvm/eventfd.o \
>> +	$(KVM)/kvm_main.o \
>> +	$(KVM)/eventfd.o \
>>  	powerpc.o \
>>  	emulate.o \
>>  	book3s.o \
>> @@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
>>  kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
>>  
>>  kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
>> -kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
>> +kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
>>  
>>  kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
>>  
>> diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
>> index 8fe9d65..40b4c64 100644
>> --- a/arch/s390/kvm/Makefile
>> +++ b/arch/s390/kvm/Makefile
>> @@ -6,7 +6,8 @@
>>  # it under the terms of the GNU General Public License (version 2 only)
>>  # as published by the Free Software Foundation.
>>  
>> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
>> +KVM := ../../../virt/kvm
>> +common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
>>  
>>  ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
>>  
>> diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
>> index d609e1d..21d5703 100644
>> --- a/arch/x86/kvm/Makefile
>> +++ b/arch/x86/kvm/Makefile
>> @@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
>>  CFLAGS_svm.o := -I.
>>  CFLAGS_vmx.o := -I.
>>  
>> -kvm-y			+= $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
>> -				coalesced_mmio.o irq_comm.o eventfd.o \
>> -				irqchip.o)
>> -kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(addprefix ../../../virt/kvm/, \
>> -				assigned-dev.o iommu.o)
>> -kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(addprefix ../../../virt/kvm/, async_pf.o)
>> +KVM := ../../../virt/kvm
>> +
>> +kvm-y			+= $(KVM)/kvm_main.o $(KVM)/ioapic.o \
>> +				$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o

... there's a missing backslash here, causing x86 to break. Sorry about
that. I'll resend the patch.

	M.
-- 
Jazz is not dead. It just smells funny...



From eric.dumazet at gmail.com  Tue May 14 09:10:08 2013
From: eric.dumazet at gmail.com (Eric Dumazet)
Date: Tue, 14 May 2013 06:10:08 -0700
Subject: [PATCHv2] mv643xx_eth: fix NAPI weight being > 64
In-Reply-To: <1368525260-17556-1-git-send-email-andrew@lunn.ch>
References: <1368525260-17556-1-git-send-email-andrew@lunn.ch>
Message-ID: <1368537008.4519.5.camel@edumazet-glaptop>

On Tue, 2013-05-14 at 11:54 +0200, Andrew Lunn wrote:
> 3.10-rc1 issues the following warning:
> 
> netif_napi_add() called with weight 128 on device eth%d
> 
> This patch reduce the weight to 64, using NAPI_POLL_WEIGHT.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> ---
> v1->v2: Use NAPI_POLL_WEIGHT.
> 
>  drivers/net/ethernet/marvell/mv643xx_eth.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
> index d0afeea..8f63c36 100644
> --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> @@ -2745,7 +2745,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
>  
>  	INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
>  
> -	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
> +	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
>  
>  	init_timer(&mp->rx_oom);
>  	mp->rx_oom.data = (unsigned long)mp;

Thanks Andrew.

Note that some other drivers need same change, would you mind sending a
patch for them as well ?

Acked-by: Eric Dumazet <edumazet at google.com>

drivers/s390/net/qeth_core.h:741:#define QETH_NAPI_WEIGHT 128
drivers/infiniband/hw/nes/nes_nic.c:1682:       netif_napi_add(netdev, &nesvnic->napi, nes_netdev_poll, 128);
drivers/infiniband/ulp/ipoib/ipoib_main.c:1356: netif_napi_add(dev, &priv->napi, ipoib_poll, 100);
drivers/net/can/janz-ican3.c:1794:      netif_napi_add(ndev, &mod->napi, ican3_napi, ICAN3_RX_BUFFERS);





From xiantao.zhang at intel.com  Tue May 14 09:14:15 2013
From: xiantao.zhang at intel.com (Zhang, Xiantao)
Date: Tue, 14 May 2013 13:14:15 +0000
Subject: [PATCH v2 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <1368534653-23133-3-git-send-email-marc.zyngier@arm.com>
References: <1368534653-23133-1-git-send-email-marc.zyngier@arm.com>
 <1368534653-23133-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <B6C2EB9186482D47BD0C5A9A4834564404308C1B@SHSMSX101.ccr.corp.intel.com>

Thanks!  Acked-by: Xiantao Zhang <xiantao.zhang at intel.com>

> -----Original Message-----
> From: Marc Zyngier [mailto:marc.zyngier at arm.com]
> Sent: Tuesday, May 14, 2013 8:31 PM
> To: linux-arm-kernel at lists.infradead.org; kvmarm at lists.cs.columbia.edu;
> kvm at vger.kernel.org
> Cc: Paolo Bonzini; Gleb Natapov; Christoffer Dall; Zhang, Xiantao; Luck, Tony;
> Yu, Fenghua; Alexander Graf; Benjamin Herrenschmidt; Christian Borntraeger;
> Cornelia Huck
> Subject: [PATCH v2 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/, ...) in
> Makefiles
> 
> As requested by the KVM maintainers, remove the addprefix used to
> refer to the main KVM code from the arch code, and replace it with
> a KVM variable that does the same thing.
> 
> Cc: Paolo Bonzini <pbonzini at redhat.com>
> Cc: Gleb Natapov <gleb at redhat.com>
> Cc: Christoffer Dall <cdall at cs.columbia.edu>
> Cc: Xiantao Zhang <xiantao.zhang at intel.com>
> Cc: Tony Luck <tony.luck at intel.com>
> Cc: Fenghua Yu <fenghua.yu at intel.com>
> Cc: Alexander Graf <agraf at suse.de>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: Christian Borntraeger <borntraeger at de.ibm.com>
> Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/kvm/Makefile     |  2 +-
>  arch/ia64/kvm/Makefile    |  7 ++++---
>  arch/powerpc/kvm/Makefile | 13 +++++++------
>  arch/s390/kvm/Makefile    |  3 ++-
>  arch/x86/kvm/Makefile     | 13 +++++++------
>  5 files changed, 21 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
> index 9184a49..d99bee4 100644
> --- a/arch/arm/kvm/Makefile
> +++ b/arch/arm/kvm/Makefile
> @@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
>  AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
> 
>  KVM := ../../../virt/kvm
> -kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
> +kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
> 
>  obj-y += kvm-arm.o init.o interrupts.o
>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
> diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
> index 1a40537..18e45ec 100644
> --- a/arch/ia64/kvm/Makefile
> +++ b/arch/ia64/kvm/Makefile
> @@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
> 
>  ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
>  asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
> +KVM := ../../../virt/kvm
> 
> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
> -		coalesced_mmio.o irq_comm.o)
> +common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
> +		$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
> 
>  ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
> -common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
> +common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
>  endif
> 
>  kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
> diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
> index 422de3f..008cd85 100644
> --- a/arch/powerpc/kvm/Makefile
> +++ b/arch/powerpc/kvm/Makefile
> @@ -5,9 +5,10 @@
>  subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
> 
>  ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
> +KVM := ../../../virt/kvm
> 
> -common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o
> \
> -						eventfd.o)
> +common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
> +		$(KVM)/eventfd.o
> 
>  CFLAGS_44x_tlb.o  := -I.
>  CFLAGS_e500_mmu.o := -I.
> @@ -53,7 +54,7 @@ kvm-e500mc-objs := \
>  kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
> 
>  kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
> -	../../../virt/kvm/coalesced_mmio.o \
> +	$(KVM)/coalesced_mmio.o \
>  	fpu.o \
>  	book3s_paired_singles.o \
>  	book3s_pr.o \
> @@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
>  	book3s_xics.o
> 
>  kvm-book3s_64-module-objs := \
> -	../../../virt/kvm/kvm_main.o \
> -	../../../virt/kvm/eventfd.o \
> +	$(KVM)/kvm_main.o \
> +	$(KVM)/eventfd.o \
>  	powerpc.o \
>  	emulate.o \
>  	book3s.o \
> @@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
>  kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
> 
>  kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
> -kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) +=
> $(addprefix ../../../virt/kvm/, irqchip.o)
> +kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
> 
>  kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
> 
> diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
> index 8fe9d65..40b4c64 100644
> --- a/arch/s390/kvm/Makefile
> +++ b/arch/s390/kvm/Makefile
> @@ -6,7 +6,8 @@
>  # it under the terms of the GNU General Public License (version 2 only)
>  # as published by the Free Software Foundation.
> 
> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
> +KVM := ../../../virt/kvm
> +common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
> 
>  ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
> 
> diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
> index d609e1d..21d5703 100644
> --- a/arch/x86/kvm/Makefile
> +++ b/arch/x86/kvm/Makefile
> @@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
>  CFLAGS_svm.o := -I.
>  CFLAGS_vmx.o := -I.
> 
> -kvm-y			+= $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
> -				coalesced_mmio.o irq_comm.o eventfd.o \
> -				irqchip.o)
> -kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+=
> $(addprefix ../../../virt/kvm/, \
> -				assigned-dev.o iommu.o)
> -kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(addprefix ../../../virt/kvm/,
> async_pf.o)
> +KVM := ../../../virt/kvm
> +
> +kvm-y			+= $(KVM)/kvm_main.o $(KVM)/ioapic.o \
> +				$(KVM)/coalesced_mmio.o
> $(KVM)/irq_comm.o
> +				$(KVM)/eventfd.o $(KVM)/irqchip.o
> +kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(KVM)/assigned-dev.o
> $(KVM)/iommu.o
> +kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(KVM)/async_pf.o
> 
>  kvm-y			+= x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
>  			   i8254.o cpuid.o pmu.o
> --
> 1.8.2.3
> 



From ulf.hansson at stericsson.com  Tue May 14 09:14:55 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Tue, 14 May 2013 15:14:55 +0200
Subject: [PATCH] mfd: db8500-prcmu: Update stored DSI PLL divider value
Message-ID: <1368537295-23459-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework were enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson at stericsson.com>
Cc: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/db8500-prcmu.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 5389368..66f8097 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n)
 
 	if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
 		divsel = dsiclk[n].divsel;
+	else
+		dsiclk[n].divsel = divsel;
 
 	switch (divsel) {
 	case PRCM_DSI_PLLOUT_SEL_PHI_4:
-- 
1.7.10



From marc.zyngier at arm.com  Tue May 14 09:31:01 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 14:31:01 +0100
Subject: [PATCH v3 1/2] ARM: KVM: move GIC/timer code to a common location
In-Reply-To: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
References: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368538262-25546-2-git-send-email-marc.zyngier@arm.com>

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

Eventually, we should probably have independant Makefiles at every
levels (just like everywhere else in the kernel), but this is just
the first step.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/kvm_host.h                                    | 4 ++--
 arch/arm/kvm/Makefile                                              | 7 ++++---
 .../include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h   | 0
 arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h          | 0
 {arch/arm/kvm => virt/kvm/arm}/arch_timer.c                        | 4 ++--
 {arch/arm/kvm => virt/kvm/arm}/vgic.c                              | 0
 6 files changed, 8 insertions(+), 7 deletions(-)
 rename arch/arm/include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h (100%)
 rename arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h (100%)
 rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
 rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index ff49193..1f3cee2 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,7 +23,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_arch_timer.h>
 
 #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
 #define KVM_USER_MEM_SLOTS 32
@@ -38,7 +38,7 @@
 #define KVM_NR_PAGE_SIZES	1
 #define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
 
-#include <asm/kvm_vgic.h>
+#include <kvm/arm_vgic.h>
 
 struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 53c5ed8..9184a49 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
-kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+KVM := ../../../virt/kvm
+kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
-obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/include/kvm/arm_arch_timer.h
similarity index 100%
rename from arch/arm/include/asm/kvm_arch_timer.h
rename to include/kvm/arm_arch_timer.h
diff --git a/arch/arm/include/asm/kvm_vgic.h b/include/kvm/arm_vgic.h
similarity index 100%
rename from arch/arm/include/asm/kvm_vgic.h
rename to include/kvm/arm_vgic.h
diff --git a/arch/arm/kvm/arch_timer.c b/virt/kvm/arm/arch_timer.c
similarity index 99%
rename from arch/arm/kvm/arch_timer.c
rename to virt/kvm/arm/arch_timer.c
index c55b608..2d00b29 100644
--- a/arch/arm/kvm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -25,8 +25,8 @@
 #include <clocksource/arm_arch_timer.h>
 #include <asm/arch_timer.h>
 
-#include <asm/kvm_vgic.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_vgic.h>
+#include <kvm/arm_arch_timer.h>
 
 static struct timecounter *timecounter;
 static struct workqueue_struct *wqueue;
diff --git a/arch/arm/kvm/vgic.c b/virt/kvm/arm/vgic.c
similarity index 100%
rename from arch/arm/kvm/vgic.c
rename to virt/kvm/arm/vgic.c
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 09:31:00 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 14:31:00 +0100
Subject: [PATCH v3 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
Message-ID: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

A second, tree-wide patch also removes the use of the addprefix used
to refer to the main KVM code from the arch code, and replace it with
a KVM variable that does the same thing.

* From v2:
  - Fix silly bug breaking compilation on x86...

Marc Zyngier (2):
  ARM: KVM: move GIC/timer code to a common location
  KVM: get rid of $(addprefix ../../../virt/kvm/, ...) in Makefiles

 arch/arm/include/asm/kvm_host.h                             |  4 ++--
 arch/arm/kvm/Makefile                                       |  7 ++++---
 arch/ia64/kvm/Makefile                                      |  7 ++++---
 arch/powerpc/kvm/Makefile                                   | 13 +++++++------
 arch/s390/kvm/Makefile                                      |  3 ++-
 arch/x86/kvm/Makefile                                       | 13 +++++++------
 .../asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h    |  0
 arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h   |  0
 {arch/arm/kvm => virt/kvm/arm}/arch_timer.c                 |  4 ++--
 {arch/arm/kvm => virt/kvm/arm}/vgic.c                       |  0
 10 files changed, 28 insertions(+), 23 deletions(-)
 rename arch/arm/include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h (100%)
 rename arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h (100%)
 rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
 rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)

-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 09:31:02 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 14:31:02 +0100
Subject: [PATCH v3 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
References: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368538262-25546-3-git-send-email-marc.zyngier@arm.com>

As requested by the KVM maintainers, remove the addprefix used to
refer to the main KVM code from the arch code, and replace it with
a KVM variable that does the same thing.

Cc: Paolo Bonzini <pbonzini at redhat.com>
Cc: Gleb Natapov <gleb at redhat.com>
Cc: Christoffer Dall <cdall at cs.columbia.edu>
Acked-by: Xiantao Zhang <xiantao.zhang at intel.com>
Cc: Tony Luck <tony.luck at intel.com>
Cc: Fenghua Yu <fenghua.yu at intel.com>
Cc: Alexander Graf <agraf at suse.de>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: Christian Borntraeger <borntraeger at de.ibm.com>
Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kvm/Makefile     |  2 +-
 arch/ia64/kvm/Makefile    |  7 ++++---
 arch/powerpc/kvm/Makefile | 13 +++++++------
 arch/s390/kvm/Makefile    |  3 ++-
 arch/x86/kvm/Makefile     | 13 +++++++------
 5 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 9184a49..d99bee4 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
 KVM := ../../../virt/kvm
-kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
+kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
index 1a40537..18e45ec 100644
--- a/arch/ia64/kvm/Makefile
+++ b/arch/ia64/kvm/Makefile
@@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
 
 ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
 asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
+KVM := ../../../virt/kvm
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-		coalesced_mmio.o irq_comm.o)
+common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
+		$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
 
 ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
-common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
+common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
 endif
 
 kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 422de3f..008cd85 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -5,9 +5,10 @@
 subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
 ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
+KVM := ../../../virt/kvm
 
-common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
-						eventfd.o)
+common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
+		$(KVM)/eventfd.o
 
 CFLAGS_44x_tlb.o  := -I.
 CFLAGS_e500_mmu.o := -I.
@@ -53,7 +54,7 @@ kvm-e500mc-objs := \
 kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
 
 kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
-	../../../virt/kvm/coalesced_mmio.o \
+	$(KVM)/coalesced_mmio.o \
 	fpu.o \
 	book3s_paired_singles.o \
 	book3s_pr.o \
@@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
 	book3s_xics.o
 
 kvm-book3s_64-module-objs := \
-	../../../virt/kvm/kvm_main.o \
-	../../../virt/kvm/eventfd.o \
+	$(KVM)/kvm_main.o \
+	$(KVM)/eventfd.o \
 	powerpc.o \
 	emulate.o \
 	book3s.o \
@@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
 kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
 
 kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
-kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
+kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
 
 kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
 
diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
index 8fe9d65..40b4c64 100644
--- a/arch/s390/kvm/Makefile
+++ b/arch/s390/kvm/Makefile
@@ -6,7 +6,8 @@
 # it under the terms of the GNU General Public License (version 2 only)
 # as published by the Free Software Foundation.
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
+KVM := ../../../virt/kvm
+common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
 
 ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
 
diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
index d609e1d..bf4fb04 100644
--- a/arch/x86/kvm/Makefile
+++ b/arch/x86/kvm/Makefile
@@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
 CFLAGS_svm.o := -I.
 CFLAGS_vmx.o := -I.
 
-kvm-y			+= $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-				coalesced_mmio.o irq_comm.o eventfd.o \
-				irqchip.o)
-kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(addprefix ../../../virt/kvm/, \
-				assigned-dev.o iommu.o)
-kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(addprefix ../../../virt/kvm/, async_pf.o)
+KVM := ../../../virt/kvm
+
+kvm-y			+= $(KVM)/kvm_main.o $(KVM)/ioapic.o \
+				$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o \
+				$(KVM)/eventfd.o $(KVM)/irqchip.o
+kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(KVM)/assigned-dev.o $(KVM)/iommu.o
+kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(KVM)/async_pf.o
 
 kvm-y			+= x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
 			   i8254.o cpuid.o pmu.o
-- 
1.8.2.3




From linus.walleij at linaro.org  Tue May 14 09:36:20 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 May 2013 15:36:20 +0200
Subject: [PATCH RESEND] pinctrl:sirf:re-arch and add support for new
 SiRFatlas6 SoC
In-Reply-To: <1368513446-22712-1-git-send-email-Baohua.Song@csr.com>
References: <1368513446-22712-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <CACRpkdZ72JqJXGnvdE31Bb4H91pHjvXA_FRKes2Fz1z4Qoo8iw@mail.gmail.com>

On Tue, May 14, 2013 at 8:37 AM, Barry Song <Baohua.Song at csr.com> wrote:

> atlas6 is a SoC very similar with primaII, the register layput of
> pinctrl is same, but the pads, groups and functions of atlas6 have
> different layout with prima2, this patch
> 1. pull the definition of pads, groups and functions out of the
> pinctrl-sirf driver,and put them into soc-specific files
> 2. add pads, groups and functions tables for atlas6
> 3. let pads, groups and functions tables become the config data of
>    the related dt compatible node, so the pinctrl-sirf can support
>    all SiRF SoCs with the config data as private data.
>
> In this patch,we create a sirf dir, and let
> the old drivers/pinctrl/pinctrl-sirf.c =
>         drivers/pinctrl/sirf/pinctrl-prima2.c +
>         drivers/pinctrl/sirf/pinctrl-sirf.c
>
> drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the
> pin layout of atlas6.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

This doesn't apply. Alas I have applied some cleanups to the Sirf
driver before this patch, but not *that* many changes... can you
rebase to the pinctrl "devel" branch?

Yours,
Linus Walleij


From robdclark at gmail.com  Tue May 14 09:38:40 2013
From: robdclark at gmail.com (Rob Clark)
Date: Tue, 14 May 2013 09:38:40 -0400
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
Message-ID: <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>

On Mon, May 13, 2013 at 10:52 PM, Inki Dae <inki.dae at samsung.com> wrote:
>> well, for cache management, I think it is a better idea.. I didn't
>> really catch that this was the motivation from the initial patch, but
>> maybe I read it too quickly.  But cache can be decoupled from
>> synchronization, because CPU access is not asynchronous.  For
>> userspace/CPU access to buffer, you should:
>>
>>   1) wait for buffer
>>   2) prepare-access
>>   3)  ... do whatever cpu access to buffer ...
>>   4) finish-access
>>   5) submit buffer for new dma-operation
>>
>
>
> For data flow from CPU to DMA device,
> 1) wait for buffer
> 2) prepare-access (dma_buf_begin_cpu_access)
> 3) cpu access to buffer
>
>
> For data flow from DMA device to CPU
> 1) wait for buffer

Right, but CPU access isn't asynchronous (from the point of view of
the CPU), so there isn't really any wait step at this point.  And if
you do want the CPU to be able to signal a fence from userspace for
some reason, you probably what something file/fd based so the
refcnting/cleanup when process dies doesn't leave some pending DMA
action wedged.  But I don't really see the point of that complexity
when the CPU access isn't asynchronous in the first place.

BR,
-R


> 2) finish-access (dma_buf_end _cpu_access)
> 3) dma access to buffer
>
> 1) and 2) are coupled with one function: we have implemented
> fence_helper_commit_reserve() for it.
>
> Cache control(cache clean or cache invalidate) is performed properly
> checking previous access type and current access type.
> And the below is actual codes for it,


From shawn.guo at linaro.org  Tue May 14 09:47:20 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 May 2013 21:47:20 +0800
Subject: [PATCH] pinctrl: enable build of pinctrl-imx6sl driver
In-Reply-To: <CACRpkdaKJ-D2FbwSWNeqZrjDJ33nR3P26Yy_1mkPmX9zLTKrfA@mail.gmail.com>
References: <1368407762-12084-1-git-send-email-shawn.guo@linaro.org>
 <CACRpkdaKJ-D2FbwSWNeqZrjDJ33nR3P26Yy_1mkPmX9zLTKrfA@mail.gmail.com>
Message-ID: <20130514134718.GD16250@S2101-09.ap.freescale.net>

On Tue, May 14, 2013 at 02:54:50PM +0200, Linus Walleij wrote:
> On Mon, May 13, 2013 at 3:16 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > The pinctrl-imx6sl is in place.  Enable the build of it.
> >
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> 
> Applied for devel (v3.11) or is this to be considered a fix,
> i.e. is someone compiling mainline kernels for the
> IMX6SL already in v3.10?

IMX6SL platform support is targeting v3.11, so it's fine to take the
patch as a v3.11 material.

Shawn



From heiko at sntech.de  Tue May 14 09:51:23 2013
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 14 May 2013 15:51:23 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <CACRpkda-wQyo8aYxbW9RJNcR3Kwe2w5AhaAuUHfaxBksa_Pm2A@mail.gmail.com>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
 <CACRpkda-wQyo8aYxbW9RJNcR3Kwe2w5AhaAuUHfaxBksa_Pm2A@mail.gmail.com>
Message-ID: <201305141551.24375.heiko@sntech.de>

Am Dienstag, 14. Mai 2013, 14:47:19 schrieb Linus Walleij:
> On Sat, May 11, 2013 at 1:31 PM, Heiko St?bner <heiko at sntech.de> wrote:
> > Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> > with numerous virtual channels being mapped to a lot less physical ones.
> > The driver therefore borrows a lot from the amba-pl08x driver in this
> > regard. Functionality-wise the driver gains a memcpy ability in addition
> > to the slave_sg one.
> > 
> > The driver currently only supports the "newer" SoCs which can use any
> > physical channel for any dma slave. Support for the older SoCs where
> > each channel only supports a subset of possible dma slaves will have to
> > be added later.
> > 
> > Tested on a s3c2416-based board, memcpy using the dmatest module and
> > slave_sg partially using the spi-s3c64xx driver.
> > 
> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> 
> So have I understood correctly if I assume that *some* S3C
> variants, i.e. this: arch/arm/mach-s3c64xx/dma.c
> have a vanilla, unmodified, or just slightly modified
> PL08x block, while this DMAC is something probably based on
> the PL08x where some ASIC engineer has had a good time hacking
> around in the VHDL code to meet some feature requirements.
> Correct? Or plausible guess?

You're guess is at good as mine :-) . The public s3c64xx (ARM11 based) 
documentation says that it is using s PL080 as dma controller while the 
s3c24xx (ARM9 based) SoCs have this one, which doesn't come with any label in 
the manuals.
Similar to the s3c64xx using a vic, while the s3c24xx uses something 
homegrown.

The relationship description was more based on the concepts used, i.e. the 
virtual channel concept and general handling of dma transfers feel somehow 
similar - as I said these are my first steps into this, so I still need to 
understand a lot.


> Exactly *how* far away from the pl08x hardware is it?
> 
> I guess you have already come to the conclusion that the
> amba-pl08x.c driver cannot be augmented to handle this hardware
> after some educated reading of that code?
> 
> But are really no parts reusable?
> 
> For example, if the LLIs have the same layout, could we split
> out the LLI handling from amba-pl08x into a separate file and reuse
> that?

The s3c24xx-dma doesn't have these. You simply put source and destination 
addresses on the bus, tell it the number of transfers and start it, while the 
pl080 seems to split these then into the LLIs, which seems to be some kind of 
hardware feature.

For the rest, the register-layout of the controller is completely different (I 
checked the PL080 manual), each channel has its own interrupt and the above 
mentioned missing LLIs.

Both drivers share somehow how they handle end of transfers, i.e. how they 
reuse the physical channel for a possible waiting virtual channel. But it 
didn't look like anything worth factoring out.


> The more you share with amba-pl08x the better for everyone,
> I am positively sure. And please include Russell on the review
> chain, he wrote the virtual channel abstraction.

I think the best feature is already factored out - the virtual channel 
handling, which was very nice to have.

I used the list from get_maintainer.pl, so sorry for forgetting Russel.


> If I was given the option amongst S3C work I would definatley
> have augmented the amba-pl08x.c to handle the stuff in
> arch/arm/mach-s3c64xx/dma.c *first* then started to work on
> this driver, but I guess you might not be working on s3c64xx?

correct, my pet-project is s3c2416-based [0], so I haven't seen any other 
Samsung stuff at all.


Heiko


[0] http://www.youtube.com/user/mmind81


From marc.zyngier at arm.com  Tue May 14 10:13:32 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:32 +0100
Subject: [PATCH v4 04/32] arm64: KVM: system register definitions for 64bit
 guests
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-5-git-send-email-marc.zyngier@arm.com>

Define the saved/restored registers for 64bit guests.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_asm.h | 68 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_asm.h

diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
new file mode 100644
index 0000000..591ac21
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_ASM_H__
+#define __ARM_KVM_ASM_H__
+
+/*
+ * 0 is reserved as an invalid value.
+ * Order *must* be kept in sync with the hyp switch code.
+ */
+#define	MPIDR_EL1	1	/* MultiProcessor Affinity Register */
+#define	CSSELR_EL1	2	/* Cache Size Selection Register */
+#define	SCTLR_EL1	3	/* System Control Register */
+#define	ACTLR_EL1	4	/* Auxilliary Control Register */
+#define	CPACR_EL1	5	/* Coprocessor Access Control */
+#define	TTBR0_EL1	6	/* Translation Table Base Register 0 */
+#define	TTBR1_EL1	7	/* Translation Table Base Register 1 */
+#define	TCR_EL1		8	/* Translation Control Register */
+#define	ESR_EL1		9	/* Exception Syndrome Register */
+#define	AFSR0_EL1	10	/* Auxilary Fault Status Register 0 */
+#define	AFSR1_EL1	11	/* Auxilary Fault Status Register 1 */
+#define	FAR_EL1		12	/* Fault Address Register */
+#define	MAIR_EL1	13	/* Memory Attribute Indirection Register */
+#define	VBAR_EL1	14	/* Vector Base Address Register */
+#define	CONTEXTIDR_EL1	15	/* Context ID Register */
+#define	TPIDR_EL0	16	/* Thread ID, User R/W */
+#define	TPIDRRO_EL0	17	/* Thread ID, User R/O */
+#define	TPIDR_EL1	18	/* Thread ID, Privileged */
+#define	AMAIR_EL1	19	/* Aux Memory Attribute Indirection Register */
+#define	CNTKCTL_EL1	20	/* Timer Control Register (EL1) */
+#define	NR_SYS_REGS	21
+
+#define ARM_EXCEPTION_IRQ	  0
+#define ARM_EXCEPTION_TRAP	  1
+
+#ifndef __ASSEMBLY__
+struct kvm;
+struct kvm_vcpu;
+
+extern char __kvm_hyp_init[];
+extern char __kvm_hyp_init_end[];
+
+extern char __kvm_hyp_vector[];
+
+extern char __kvm_hyp_code_start[];
+extern char __kvm_hyp_code_end[];
+
+extern void __kvm_flush_vm_context(void);
+extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+
+extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+#endif
+
+#endif /* __ARM_KVM_ASM_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:33 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:33 +0100
Subject: [PATCH v4 05/32] arm64: KVM: Basic ESR_EL2 helpers and vcpu register
 access
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-6-git-send-email-marc.zyngier@arm.com>

Implements helpers for dealing with the EL2 syndrome register as
well as accessing the vcpu registers.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_emulate.h | 158 +++++++++++++++++++++++++++++++++++
 1 file changed, 158 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_emulate.h

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
new file mode 100644
index 0000000..6c1725e
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/include/kvm_emulate.h
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_EMULATE_H__
+#define __ARM64_KVM_EMULATE_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmio.h>
+#include <asm/ptrace.h>
+
+void kvm_inject_undefined(struct kvm_vcpu *vcpu);
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
+
+static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
+{
+	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
+}
+
+static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
+{
+	return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
+}
+
+static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
+{
+	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
+}
+
+static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
+{
+	return false;	/* 32bit? Bahhh... */
+}
+
+static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
+{
+	return true;	/* No conditionals on arm64 */
+}
+
+static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+	*vcpu_pc(vcpu) += 4;
+}
+
+static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
+{
+}
+
+static inline unsigned long *vcpu_reg(const struct kvm_vcpu *vcpu, u8 reg_num)
+{
+	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.regs[reg_num];
+}
+
+/* Get vcpu SPSR for current mode */
+static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
+{
+	return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
+}
+
+static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
+{
+	u32 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
+
+	return mode != PSR_MODE_EL0t;
+}
+
+static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
+{
+	return vcpu->arch.fault.esr_el2;
+}
+
+static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
+{
+	return vcpu->arch.fault.far_el2;
+}
+
+static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
+{
+	return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
+}
+
+static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
+{
+	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);
+}
+
+static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
+{
+	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_WNR);
+}
+
+static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
+{
+	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SSE);
+}
+
+static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
+{
+	return (kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SRT_MASK) >> ESR_EL2_SRT_SHIFT;
+}
+
+static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
+{
+	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_EA);
+}
+
+static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
+{
+	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_S1PTW);
+}
+
+static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
+{
+	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SAS) >> ESR_EL2_SAS_SHIFT);
+}
+
+/* This one is not specific to Data Abort */
+static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
+{
+	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_IL);
+}
+
+static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
+{
+	return kvm_vcpu_get_hsr(vcpu) >> ESR_EL2_EC_SHIFT;
+}
+
+static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
+{
+	return kvm_vcpu_trap_get_class(vcpu) == ESR_EL2_EC_IABT;
+}
+
+static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
+{
+	return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE;
+}
+
+#endif /* __ARM64_KVM_EMULATE_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:30 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:30 +0100
Subject: [PATCH v4 02/32] arm64: KVM: HYP mode idmap support
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-3-git-send-email-marc.zyngier@arm.com>

Add the necessary infrastructure for identity-mapped HYP page
tables. Idmap-ed code must be in the ".hyp.idmap.text" linker
section.

The rest of the HYP ends up in ".hyp.text".

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kernel/vmlinux.lds.S | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 3fae2be..9635391 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -17,6 +17,19 @@ ENTRY(stext)
 
 jiffies = jiffies_64;
 
+#define HYPERVISOR_TEXT					\
+	/*						\
+	 * Force the alignment to be compatible with	\
+	 * the vectors requirements			\
+	 */						\
+	. = ALIGN(2048);				\
+	VMLINUX_SYMBOL(__hyp_idmap_text_start) = .;	\
+	*(.hyp.idmap.text)				\
+	VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;	\
+	VMLINUX_SYMBOL(__hyp_text_start) = .;		\
+	*(.hyp.text)					\
+	VMLINUX_SYMBOL(__hyp_text_end) = .;
+
 SECTIONS
 {
 	/*
@@ -49,6 +62,7 @@ SECTIONS
 			TEXT_TEXT
 			SCHED_TEXT
 			LOCK_TEXT
+			HYPERVISOR_TEXT
 			*(.fixup)
 			*(.gnu.warning)
 		. = ALIGN(16);
@@ -124,3 +138,9 @@ SECTIONS
 	STABS_DEBUG
 	.comment 0 : { *(.comment) }
 }
+
+/*
+ * The HYP init code can't be more than a page long.
+ */
+ASSERT(((__hyp_idmap_text_start + PAGE_SIZE) >= __hyp_idmap_text_end),
+       "HYP init code too big")
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:28 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:28 +0100
Subject: [PATCH v4 00/32] Port of KVM to arm64
Message-ID: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>

This series contains the fourth version of KVM for arm64.

It depends on the following branche:
- git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm/fixes
  a small number of fixes and other files being moved around

The code is unsurprisingly extremely similar to the KVM/arm code, and
a lot of it is actually shared with the 32bit version. Most of the
duplicated code has now been eliminated by moving it to a common,
architecture agnostic location.

In terms of features:
- Support for 4k and 64k pages
- Support for 32bit and 64bit guests
- PSCI support for SMP booting

Testing has been done on both AEMv8 and Foundation models, with
various 32 and 64bit guests running a variety of distributions (OE,
Ubuntu and openSUSE for 64bit, Debian and Ubuntu on 32bit).

The patches are also available on the following branch:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/kvm

As we do not have a 64bit QEMU port, it has been tested using
kvmtools. Note that some of the changes have broken the userspace ABI
in v2 and v3, and you must update and rebuild your kvmtools (the
previous versions won't work anymore):

git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/kvmtool

KVM maintainers: this series introduces a new capability
(KVM_CAP_ARM_EL1_32BIT, 93) and a new ONE_REG architecture
(KVM_REG_ARM64, 0x6000000000000000ULL). Can we make sure these won't
clash with any other upcoming patches? If they already do, can you
allocate safe and reserved numbers?

>From v3:
- Now relies on vgic/timer being moved to virt/kvm/arm
- Also relies on quite a few 32bit changes, and mimics some other 32bit
  fixes that have been merged already
- Fixed a number of MMU setup issues (Will, Catalin, Pranavkumar)
- Fixed a number of issues in the sys_regs interface, updated
  documentation (Christoffer)
- Add a short EL2 memory-map section to memory.txt

>From v2:
- Dropped the idmap code and use the new KVM/ARM boot protocol
- New KVM_CAP_ARM_EL1_32BIT capability to let userspace detect if EL1
  is 32bit capable
- Fixed a bug in arch/arm/entry.S, where EL0/EL1 breakpoint handling was
  mixed up (spotted by Catalin Marinas)
- Some sparse fixes (courtesy of Geoff Levand)
- Dropped the "shared" attribute from device mappings (spotted by Catalin)
- Add API documentation
- Add MAINTAINERS entry

>From v1:
- Rework of the world-switch to use common structure between host and
  guests (suggested by Christopher Covington)
- Some additional constants to make the EL1 fault injection clearer
  (suggested by Christopher Covington)
- Use of __u64 instead of "unsigned long" in the userspace API
  (suggested by Michael S. Tsirkin)
- Move the FP/SIMD registers into the "core" registers, dropping the
  specific accessors.
- Generic MPIDR implementation (suggested by Christopher Covington)
- Cleaner handling of the various host implementations

Marc Zyngier (32):
  arm64: KVM: define HYP and Stage-2 translation page flags
  arm64: KVM: HYP mode idmap support
  arm64: KVM: EL2 register definitions
  arm64: KVM: system register definitions for 64bit guests
  arm64: KVM: Basic ESR_EL2 helpers and vcpu register access
  arm64: KVM: fault injection into a guest
  arm64: KVM: architecture specific MMU backend
  arm64: KVM: user space interface
  arm64: KVM: system register handling
  arm64: KVM: CPU specific system registers handling
  arm64: KVM: virtual CPU reset
  arm64: KVM: kvm_arch and kvm_vcpu_arch definitions
  arm64: KVM: MMIO access backend
  arm64: KVM: guest one-reg interface
  arm64: KVM: hypervisor initialization code
  arm64: KVM: HYP mode world switch implementation
  arm64: KVM: Exit handling
  arm64: KVM: Plug the VGIC
  arm64: KVM: Plug the arch timer
  arm64: KVM: PSCI implementation
  arm64: KVM: Build system integration
  arm64: KVM: define 32bit specific registers
  arm64: KVM: 32bit GP register access
  arm64: KVM: 32bit conditional execution emulation
  arm64: KVM: 32bit handling of coprocessor traps
  arm64: KVM: CPU specific 32bit coprocessor access
  arm64: KVM: 32bit specific register world switch
  arm64: KVM: 32bit guest fault injection
  arm64: KVM: enable initialization of a 32bit vcpu
  arm64: KVM: userspace API documentation
  arm64: KVM: MAINTAINERS update
  arm64: KVM: document kernel object mappings in HYP

 Documentation/arm64/memory.txt         |    7 +
 Documentation/virtual/kvm/api.txt      |   58 +-
 MAINTAINERS                            |    9 +
 arch/arm64/Kconfig                     |    2 +
 arch/arm64/Makefile                    |    2 +-
 arch/arm64/include/asm/kvm_arm.h       |  245 ++++++++
 arch/arm64/include/asm/kvm_asm.h       |  104 ++++
 arch/arm64/include/asm/kvm_coproc.h    |   56 ++
 arch/arm64/include/asm/kvm_emulate.h   |  180 ++++++
 arch/arm64/include/asm/kvm_host.h      |  202 ++++++
 arch/arm64/include/asm/kvm_mmio.h      |   59 ++
 arch/arm64/include/asm/kvm_mmu.h       |  135 ++++
 arch/arm64/include/asm/kvm_psci.h      |   23 +
 arch/arm64/include/asm/memory.h        |    5 +
 arch/arm64/include/asm/pgtable-hwdef.h |   19 +
 arch/arm64/include/asm/pgtable.h       |   11 +
 arch/arm64/include/uapi/asm/kvm.h      |  168 +++++
 arch/arm64/kernel/asm-offsets.c        |   34 ++
 arch/arm64/kernel/vmlinux.lds.S        |   20 +
 arch/arm64/kvm/Kconfig                 |   59 ++
 arch/arm64/kvm/Makefile                |   23 +
 arch/arm64/kvm/emulate.c               |  158 +++++
 arch/arm64/kvm/guest.c                 |  259 ++++++++
 arch/arm64/kvm/handle_exit.c           |  124 ++++
 arch/arm64/kvm/hyp-init.S              |  112 ++++
 arch/arm64/kvm/hyp.S                   |  817 +++++++++++++++++++++++++
 arch/arm64/kvm/inject_fault.c          |  203 ++++++
 arch/arm64/kvm/regmap.c                |  168 +++++
 arch/arm64/kvm/reset.c                 |  100 +++
 arch/arm64/kvm/sys_regs.c              | 1050 ++++++++++++++++++++++++++++++++
 arch/arm64/kvm/sys_regs.h              |  138 +++++
 arch/arm64/kvm/sys_regs_generic_v8.c   |   95 +++
 include/uapi/linux/kvm.h               |    2 +
 virt/kvm/arm/arch_timer.c              |    1 +
 34 files changed, 4628 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm64/include/asm/kvm_arm.h
 create mode 100644 arch/arm64/include/asm/kvm_asm.h
 create mode 100644 arch/arm64/include/asm/kvm_coproc.h
 create mode 100644 arch/arm64/include/asm/kvm_emulate.h
 create mode 100644 arch/arm64/include/asm/kvm_host.h
 create mode 100644 arch/arm64/include/asm/kvm_mmio.h
 create mode 100644 arch/arm64/include/asm/kvm_mmu.h
 create mode 100644 arch/arm64/include/asm/kvm_psci.h
 create mode 100644 arch/arm64/include/uapi/asm/kvm.h
 create mode 100644 arch/arm64/kvm/Kconfig
 create mode 100644 arch/arm64/kvm/Makefile
 create mode 100644 arch/arm64/kvm/emulate.c
 create mode 100644 arch/arm64/kvm/guest.c
 create mode 100644 arch/arm64/kvm/handle_exit.c
 create mode 100644 arch/arm64/kvm/hyp-init.S
 create mode 100644 arch/arm64/kvm/hyp.S
 create mode 100644 arch/arm64/kvm/inject_fault.c
 create mode 100644 arch/arm64/kvm/regmap.c
 create mode 100644 arch/arm64/kvm/reset.c
 create mode 100644 arch/arm64/kvm/sys_regs.c
 create mode 100644 arch/arm64/kvm/sys_regs.h
 create mode 100644 arch/arm64/kvm/sys_regs_generic_v8.c

-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:36 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:36 +0100
Subject: [PATCH v4 08/32] arm64: KVM: user space interface
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-9-git-send-email-marc.zyngier@arm.com>

Provide the kvm.h file that defines the user space visible
interface.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/uapi/asm/kvm.h | 117 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)
 create mode 100644 arch/arm64/include/uapi/asm/kvm.h

diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
new file mode 100644
index 0000000..4e64570
--- /dev/null
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/include/uapi/asm/kvm.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+
+#define KVM_SPSR_EL1	0
+#define KVM_NR_SPSR	1
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_GUEST_DEBUG
+#define __KVM_HAVE_IRQ_LINE
+
+#define KVM_REG_SIZE(id)						\
+	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+struct kvm_regs {
+	struct user_pt_regs regs;	/* sp = sp_el0 */
+
+	__u64	sp_el1;
+	__u64	elr_el1;
+
+	__u64	spsr[KVM_NR_SPSR];
+
+	struct user_fpsimd_state fp_regs;
+};
+
+/* Supported Processor Types */
+#define KVM_ARM_TARGET_AEM_V8		0
+#define KVM_ARM_TARGET_FOUNDATION_V8	1
+#define KVM_ARM_TARGET_CORTEX_A57	2
+
+#define KVM_ARM_NUM_TARGETS		3
+
+/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
+#define KVM_ARM_DEVICE_TYPE_SHIFT	0
+#define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
+#define KVM_ARM_DEVICE_ID_SHIFT		16
+#define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)
+
+/* Supported device IDs */
+#define KVM_ARM_DEVICE_VGIC_V2		0
+
+/* Supported VGIC address types  */
+#define KVM_VGIC_V2_ADDR_TYPE_DIST	0
+#define KVM_VGIC_V2_ADDR_TYPE_CPU	1
+
+#define KVM_VGIC_V2_DIST_SIZE		0x1000
+#define KVM_VGIC_V2_CPU_SIZE		0x2000
+
+struct kvm_vcpu_init {
+	__u32 target;
+	__u32 features[7];
+};
+
+struct kvm_sregs {
+};
+
+struct kvm_fpu {
+};
+
+struct kvm_guest_debug_arch {
+};
+
+struct kvm_debug_exit_arch {
+};
+
+struct kvm_sync_regs {
+};
+
+struct kvm_arch_memory_slot {
+};
+
+/* KVM_IRQ_LINE irq field index values */
+#define KVM_ARM_IRQ_TYPE_SHIFT		24
+#define KVM_ARM_IRQ_TYPE_MASK		0xff
+#define KVM_ARM_IRQ_VCPU_SHIFT		16
+#define KVM_ARM_IRQ_VCPU_MASK		0xff
+#define KVM_ARM_IRQ_NUM_SHIFT		0
+#define KVM_ARM_IRQ_NUM_MASK		0xffff
+
+/* irq_type field */
+#define KVM_ARM_IRQ_TYPE_CPU		0
+#define KVM_ARM_IRQ_TYPE_SPI		1
+#define KVM_ARM_IRQ_TYPE_PPI		2
+
+/* out-of-kernel GIC cpu interrupt injection irq_number field */
+#define KVM_ARM_IRQ_CPU_IRQ		0
+#define KVM_ARM_IRQ_CPU_FIQ		1
+
+/* Highest supported SPI, from VGIC_NR_IRQS */
+#define KVM_ARM_IRQ_GIC_MAX		127
+
+#endif
+
+#endif /* __ARM_KVM_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:35 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:35 +0100
Subject: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-8-git-send-email-marc.zyngier@arm.com>

Define the arm64 specific MMU backend:
- HYP/kernel VA offset
- S2 4/64kB definitions
- S2 page table populating and flushing
- icache cleaning

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_mmu.h | 135 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 135 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_mmu.h

diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
new file mode 100644
index 0000000..efe609c
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_MMU_H__
+#define __ARM64_KVM_MMU_H__
+
+#include <asm/page.h>
+#include <asm/memory.h>
+
+/*
+ * As we only have the TTBR0_EL2 register, we cannot express
+ * "negative" addresses. This makes it impossible to directly share
+ * mappings with the kernel.
+ *
+ * Instead, give the HYP mode its own VA region at a fixed offset from
+ * the kernel by just masking the top bits (which are all ones for a
+ * kernel address).
+ */
+#define HYP_PAGE_OFFSET_SHIFT	VA_BITS
+#define HYP_PAGE_OFFSET_MASK	((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
+#define HYP_PAGE_OFFSET		(PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
+
+/*
+ * Our virtual mapping for the idmap-ed MMU-enable code. Must be
+ * shared across all the page-tables. Conveniently, we use the last
+ * possible page, where no kernel mapping will ever exist.
+ */
+#define TRAMPOLINE_VA		(HYP_PAGE_OFFSET_MASK & PAGE_MASK)
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Convert a kernel VA into a HYP VA.
+ * reg: VA to be converted.
+ */
+.macro kern_hyp_va	reg
+	and	\reg, \reg, #HYP_PAGE_OFFSET_MASK
+.endm
+
+#else
+
+#include <asm/cachetype.h>
+#include <asm/cacheflush.h>
+
+#define KERN_TO_HYP(kva)	((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
+
+/*
+ * Align KVM with the kernel's view of physical memory. Should be
+ * 40bit IPA, with PGD being 8kB aligned in the 4KB page configuration.
+ */
+#define KVM_PHYS_SHIFT	PHYS_MASK_SHIFT
+#define KVM_PHYS_SIZE	(1UL << KVM_PHYS_SHIFT)
+#define KVM_PHYS_MASK	(KVM_PHYS_SIZE - 1UL)
+
+/* Make sure we get the right size, and thus the right alignment */
+#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - PGDIR_SHIFT))
+#define S2_PGD_ORDER	get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
+
+int create_hyp_mappings(void *from, void *to);
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+void free_boot_hyp_pgd(void);
+void free_hyp_pgds(void);
+
+int kvm_alloc_stage2_pgd(struct kvm *kvm);
+void kvm_free_stage2_pgd(struct kvm *kvm);
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+			  phys_addr_t pa, unsigned long size);
+
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+
+phys_addr_t kvm_mmu_get_httbr(void);
+phys_addr_t kvm_mmu_get_boot_httbr(void);
+phys_addr_t kvm_get_idmap_vector(void);
+int kvm_mmu_init(void);
+void kvm_clear_hyp_idmap(void);
+
+#define	kvm_set_pte(ptep, pte)		set_pte(ptep, pte)
+
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+	unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
+
+	if (esr_ec == ESR_EL2_EC_IABT)
+		return false;
+
+	if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
+		return false;
+
+	return true;
+}
+
+static inline void kvm_clean_dcache_area(void *addr, size_t size) {}
+static inline void kvm_clean_pgd(pgd_t *pgd) {}
+static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
+static inline void kvm_clean_pte(pte_t *pte) {}
+static inline void kvm_clean_pte_entry(pte_t *pte) {}
+
+static inline void kvm_set_s2pte_writable(pte_t *pte)
+{
+	pte_val(*pte) |= PTE_S2_RDWR;
+}
+
+struct kvm;
+
+static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+	if (!icache_is_aliasing()) {		/* PIPT */
+		unsigned long hva = gfn_to_hva(kvm, gfn);
+		flush_icache_range(hva, hva + PAGE_SIZE);
+	} else if (!icache_is_aivivt()) {	/* non ASID-tagged VIVT */
+		/* any kind of VIPT cache */
+		__flush_icache_all();
+	}
+}
+
+#define kvm_flush_dcache_to_poc(a,l)	__flush_dcache_area((a), (l))
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARM64_KVM_MMU_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:29 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:29 +0100
Subject: [PATCH v4 01/32] arm64: KVM: define HYP and Stage-2 translation page
 flags
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-2-git-send-email-marc.zyngier@arm.com>

Add HYP and S2 page flags, for both normal and device memory.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/memory.h        |  5 +++++
 arch/arm64/include/asm/pgtable-hwdef.h | 19 +++++++++++++++++++
 arch/arm64/include/asm/pgtable.h       | 11 +++++++++++
 3 files changed, 35 insertions(+)

diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 381f556..15745a7c 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -90,6 +90,11 @@
 #define MT_NORMAL_NC		3
 #define MT_NORMAL		4
 
+/*
+ * Default memory type for Stage-2 translation
+ */
+#define MT_S2_NORMAL		0xf
+
 #ifndef __ASSEMBLY__
 
 extern phys_addr_t		memstart_addr;
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 75fd13d..66367c6 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -35,6 +35,7 @@
 /*
  * Section
  */
+#define PMD_SECT_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
 #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
@@ -68,6 +69,24 @@
 #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
 
 /*
+ * 2nd stage PTE definitions
+ */
+#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
+#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+
+/*
+ * Memory Attribute override for Stage-2 (MemAttr[3:0])
+ */
+#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
+#define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)
+
+/*
+ * EL2/HYP PTE/PMD definitions
+ */
+#define PMD_HYP			PMD_SECT_USER
+#define PTE_HYP			PTE_USER
+
+/*
  * 40-bit physical address supported.
  */
 #define PHYS_MASK_SHIFT		(40)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e333a24..34ba9ba 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -76,6 +76,11 @@ extern pgprot_t pgprot_default;
 #define PAGE_KERNEL		_MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
 #define PAGE_KERNEL_EXEC	_MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
 
+#define PAGE_HYP		_MOD_PROT(pgprot_default, PTE_HYP)
+#define PAGE_HYP_DEVICE		__pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
+
+#define PAGE_S2			__pgprot_modify(pgprot_default, PTE_S2_MEMATTR_MASK, PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
+
 #define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
 #define __PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
@@ -197,6 +202,12 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 
 #define pmd_bad(pmd)		(!(pmd_val(pmd) & 2))
 
+#define pmd_table(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
+				 PMD_TYPE_TABLE)
+#define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
+				 PMD_TYPE_SECT)
+
+
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
 	*pmdp = pmd;
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:34 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:34 +0100
Subject: [PATCH v4 06/32] arm64: KVM: fault injection into a guest
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-7-git-send-email-marc.zyngier@arm.com>

Implement the injection of a fault (undefined, data abort or
prefetch abort) into a 64bit guest.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/inject_fault.c | 126 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)
 create mode 100644 arch/arm64/kvm/inject_fault.c

diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
new file mode 100644
index 0000000..54f6562
--- /dev/null
+++ b/arch/arm64/kvm/inject_fault.c
@@ -0,0 +1,126 @@
+/*
+ * Fault injection for 64bit guests.
+ *
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Based on arch/arm/kvm/emulate.c
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/esr.h>
+
+#define PSTATE_FAULT_BITS_64 	(PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
+				 PSR_I_BIT | PSR_D_BIT)
+#define EL1_EXCEPT_SYNC_OFFSET	0x200
+
+static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
+{
+	unsigned long cpsr = *vcpu_cpsr(vcpu);
+	bool is_aarch32;
+	u32 esr = 0;
+
+	is_aarch32 = vcpu_mode_is_32bit(vcpu);
+
+	*vcpu_spsr(vcpu) = cpsr;
+	*vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+
+	*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
+	*vcpu_pc(vcpu) = vcpu_sys_reg(vcpu, VBAR_EL1) + EL1_EXCEPT_SYNC_OFFSET;
+
+	vcpu_sys_reg(vcpu, FAR_EL1) = addr;
+
+	/*
+	 * Build an {i,d}abort, depending on the level and the
+	 * instruction set. Report an external synchronous abort.
+	 */
+	if (kvm_vcpu_trap_il_is32bit(vcpu))
+		esr |= ESR_EL1_IL;
+
+	/*
+	 * Here, the guest runs in AArch64 mode when in EL1. If we get
+	 * an AArch32 fault, it means we managed to trap an EL0 fault.
+	 */
+	if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
+		esr |= (ESR_EL1_EC_IABT_EL0 << ESR_EL1_EC_SHIFT);
+	else
+		esr |= (ESR_EL1_EC_IABT_EL1 << ESR_EL1_EC_SHIFT);
+
+	if (!is_iabt)
+		esr |= ESR_EL1_EC_DABT_EL0;
+
+	vcpu_sys_reg(vcpu, ESR_EL1) = esr | ESR_EL2_EC_xABT_xFSR_EXTABT;
+}
+
+static void inject_undef64(struct kvm_vcpu *vcpu)
+{
+	unsigned long cpsr = *vcpu_cpsr(vcpu);
+	u32 esr = (ESR_EL1_EC_UNKNOWN << ESR_EL1_EC_SHIFT);
+
+	*vcpu_spsr(vcpu) = cpsr;
+	*vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+
+	*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
+	*vcpu_pc(vcpu) = vcpu_sys_reg(vcpu, VBAR_EL1) + EL1_EXCEPT_SYNC_OFFSET;
+
+	/*
+	 * Build an unknown exception, depending on the instruction
+	 * set.
+	 */
+	if (kvm_vcpu_trap_il_is32bit(vcpu))
+		esr |= ESR_EL1_IL;
+
+	vcpu_sys_reg(vcpu, ESR_EL1) = esr;
+}
+
+/**
+ * kvm_inject_dabt - inject a data abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+	inject_abt64(vcpu, false, addr);
+}
+
+/**
+ * kvm_inject_pabt - inject a prefetch abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+	inject_abt64(vcpu, true, addr);
+}
+
+/**
+ * kvm_inject_undefined - inject an undefined instruction into the guest
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_undefined(struct kvm_vcpu *vcpu)
+{
+	inject_undef64(vcpu);
+}
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:41 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:41 +0100
Subject: [PATCH v4 13/32] arm64: KVM: MMIO access backend
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-14-git-send-email-marc.zyngier@arm.com>

Define the necessary structures to perform an MMIO access.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_mmio.h | 59 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_mmio.h

diff --git a/arch/arm64/include/asm/kvm_mmio.h b/arch/arm64/include/asm/kvm_mmio.h
new file mode 100644
index 0000000..fc2f689
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_mmio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_MMIO_H__
+#define __ARM64_KVM_MMIO_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+
+/*
+ * This is annoying. The mmio code requires this, even if we don't
+ * need any decoding. To be fixed.
+ */
+struct kvm_decode {
+	unsigned long rt;
+	bool sign_extend;
+};
+
+/*
+ * The in-kernel MMIO emulation code wants to use a copy of run->mmio,
+ * which is an anonymous type. Use our own type instead.
+ */
+struct kvm_exit_mmio {
+	phys_addr_t	phys_addr;
+	u8		data[8];
+	u32		len;
+	bool		is_write;
+};
+
+static inline void kvm_prepare_mmio(struct kvm_run *run,
+				    struct kvm_exit_mmio *mmio)
+{
+	run->mmio.phys_addr	= mmio->phys_addr;
+	run->mmio.len		= mmio->len;
+	run->mmio.is_write	= mmio->is_write;
+	memcpy(run->mmio.data, mmio->data, mmio->len);
+	run->exit_reason	= KVM_EXIT_MMIO;
+}
+
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+		 phys_addr_t fault_ipa);
+
+#endif	/* __ARM64_KVM_MMIO_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:38 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:38 +0100
Subject: [PATCH v4 10/32] arm64: KVM: CPU specific system registers handling
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-11-git-send-email-marc.zyngier@arm.com>

Add the support code for CPU specific system registers. Not much
here yet.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/sys_regs_generic_v8.c | 85 ++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 arch/arm64/kvm/sys_regs_generic_v8.c

diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c b/arch/arm64/kvm/sys_regs_generic_v8.c
new file mode 100644
index 0000000..d4e8039
--- /dev/null
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Based on arch/arm/kvm/coproc_a15.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty at rustcorp.au>
+ *          Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kvm_host.h>
+#include <asm/cputype.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <linux/init.h>
+
+#include "sys_regs.h"
+
+static bool access_actlr(struct kvm_vcpu *vcpu,
+			 const struct sys_reg_params *p,
+			 const struct sys_reg_desc *r)
+{
+	if (p->is_write)
+		return ignore_write(vcpu, p);
+
+	*vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, ACTLR_EL1);
+	return true;
+}
+
+static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	u64 actlr;
+
+	asm volatile("mrs %0, actlr_el1\n" : "=r" (actlr));
+	vcpu_sys_reg(vcpu, ACTLR_EL1) = actlr;
+}
+
+/*
+ * Implementation specific sys-reg registers.
+ * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
+ */
+static const struct sys_reg_desc genericv8_sys_regs[] = {
+	/* ACTLR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
+	  access_actlr, reset_actlr, ACTLR_EL1 },
+};
+
+static struct kvm_sys_reg_target_table genericv8_target_table = {
+	.table64 = {
+		.table = genericv8_sys_regs,
+		.num = ARRAY_SIZE(genericv8_sys_regs),
+	},
+};
+
+static int __init sys_reg_genericv8_init(void)
+{
+	unsigned int i;
+
+	for (i = 1; i < ARRAY_SIZE(genericv8_sys_regs); i++)
+		BUG_ON(cmp_sys_reg(&genericv8_sys_regs[i-1],
+			       &genericv8_sys_regs[i]) >= 0);
+
+	kvm_register_target_sys_reg_table(KVM_ARM_TARGET_AEM_V8,
+					  &genericv8_target_table);
+	kvm_register_target_sys_reg_table(KVM_ARM_TARGET_FOUNDATION_V8,
+					  &genericv8_target_table);
+	kvm_register_target_sys_reg_table(KVM_ARM_TARGET_CORTEX_A57,
+					  &genericv8_target_table);
+	return 0;
+}
+late_initcall(sys_reg_genericv8_init);
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:31 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:31 +0100
Subject: [PATCH v4 03/32] arm64: KVM: EL2 register definitions
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-4-git-send-email-marc.zyngier@arm.com>

Define all the useful bitfields for EL2 registers.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_arm.h | 245 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 245 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_arm.h

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
new file mode 100644
index 0000000..a5f28e2
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_ARM_H__
+#define __ARM64_KVM_ARM_H__
+
+#include <asm/types.h>
+
+/* Hyp Configuration Register (HCR) bits */
+#define HCR_ID		(UL(1) << 33)
+#define HCR_CD		(UL(1) << 32)
+#define HCR_RW_SHIFT	31
+#define HCR_RW		(UL(1) << HCR_RW_SHIFT)
+#define HCR_TRVM	(UL(1) << 30)
+#define HCR_HCD		(UL(1) << 29)
+#define HCR_TDZ		(UL(1) << 28)
+#define HCR_TGE		(UL(1) << 27)
+#define HCR_TVM		(UL(1) << 26)
+#define HCR_TTLB	(UL(1) << 25)
+#define HCR_TPU		(UL(1) << 24)
+#define HCR_TPC		(UL(1) << 23)
+#define HCR_TSW		(UL(1) << 22)
+#define HCR_TAC		(UL(1) << 21)
+#define HCR_TIDCP	(UL(1) << 20)
+#define HCR_TSC		(UL(1) << 19)
+#define HCR_TID3	(UL(1) << 18)
+#define HCR_TID2	(UL(1) << 17)
+#define HCR_TID1	(UL(1) << 16)
+#define HCR_TID0	(UL(1) << 15)
+#define HCR_TWE		(UL(1) << 14)
+#define HCR_TWI		(UL(1) << 13)
+#define HCR_DC		(UL(1) << 12)
+#define HCR_BSU		(3 << 10)
+#define HCR_BSU_IS	(UL(1) << 10)
+#define HCR_FB		(UL(1) << 9)
+#define HCR_VA		(UL(1) << 8)
+#define HCR_VI		(UL(1) << 7)
+#define HCR_VF		(UL(1) << 6)
+#define HCR_AMO		(UL(1) << 5)
+#define HCR_IMO		(UL(1) << 4)
+#define HCR_FMO		(UL(1) << 3)
+#define HCR_PTW		(UL(1) << 2)
+#define HCR_SWIO	(UL(1) << 1)
+#define HCR_VM		(UL(1) << 0)
+
+/*
+ * The bits we set in HCR:
+ * RW:		64bit by default, can be overriden for 32bit VMs
+ * TAC:		Trap ACTLR
+ * TSC:		Trap SMC
+ * TSW:		Trap cache operations by set/way
+ * TWI:		Trap WFI
+ * TIDCP:	Trap L2CTLR/L2ECTLR
+ * BSU_IS:	Upgrade barriers to the inner shareable domain
+ * FB:		Force broadcast of all maintainance operations
+ * AMO:		Override CPSR.A and enable signaling with VA
+ * IMO:		Override CPSR.I and enable signaling with VI
+ * FMO:		Override CPSR.F and enable signaling with VF
+ * SWIO:	Turn set/way invalidates into set/way clean+invalidate
+ */
+#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
+			 HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
+			 HCR_SWIO | HCR_TIDCP | HCR_RW)
+#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
+
+/* Hyp System Control Register (SCTLR_EL2) bits */
+#define SCTLR_EL2_EE	(1 << 25)
+#define SCTLR_EL2_WXN	(1 << 19)
+#define SCTLR_EL2_I	(1 << 12)
+#define SCTLR_EL2_SA	(1 << 3)
+#define SCTLR_EL2_C	(1 << 2)
+#define SCTLR_EL2_A	(1 << 1)
+#define SCTLR_EL2_M	1
+#define SCTLR_EL2_FLAGS	(SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C |	\
+			 SCTLR_EL2_SA | SCTLR_EL2_I)
+
+/* TCR_EL2 Registers bits */
+#define TCR_EL2_TBI	(1 << 20)
+#define TCR_EL2_PS	(7 << 16)
+#define TCR_EL2_PS_40B	(2 << 16)
+#define TCR_EL2_TG0	(1 << 14)
+#define TCR_EL2_SH0	(3 << 12)
+#define TCR_EL2_ORGN0	(3 << 10)
+#define TCR_EL2_IRGN0	(3 << 8)
+#define TCR_EL2_T0SZ	0x3f
+#define TCR_EL2_MASK	(TCR_EL2_TG0 | TCR_EL2_SH0 | \
+			 TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
+
+#define TCR_EL2_FLAGS	(TCR_EL2_PS_40B)
+
+/* VTCR_EL2 Registers bits */
+#define VTCR_EL2_PS_MASK	(7 << 16)
+#define VTCR_EL2_PS_40B		(2 << 16)
+#define VTCR_EL2_TG0_MASK	(1 << 14)
+#define VTCR_EL2_TG0_4K		(0 << 14)
+#define VTCR_EL2_TG0_64K	(1 << 14)
+#define VTCR_EL2_SH0_MASK	(3 << 12)
+#define VTCR_EL2_SH0_INNER	(3 << 12)
+#define VTCR_EL2_ORGN0_MASK	(3 << 10)
+#define VTCR_EL2_ORGN0_WBWA	(1 << 10)
+#define VTCR_EL2_IRGN0_MASK	(3 << 8)
+#define VTCR_EL2_IRGN0_WBWA	(1 << 8)
+#define VTCR_EL2_SL0_MASK	(3 << 6)
+#define VTCR_EL2_SL0_LVL1	(1 << 6)
+#define VTCR_EL2_T0SZ_MASK	0x3f
+#define VTCR_EL2_T0SZ_40B	24
+
+#ifdef CONFIG_ARM64_64K_PAGES
+/*
+ * Stage2 translation configuration:
+ * 40bits output (PS = 2)
+ * 40bits input  (T0SZ = 24)
+ * 64kB pages (TG0 = 1)
+ * 2 level page tables (SL = 1)
+ */
+#define VTCR_EL2_FLAGS		(VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \
+				 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
+				 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
+				 VTCR_EL2_T0SZ_40B)
+#define VTTBR_X		(38 - VTCR_EL2_T0SZ_40B)
+#else
+/*
+ * Stage2 translation configuration:
+ * 40bits output (PS = 2)
+ * 40bits input  (T0SZ = 24)
+ * 4kB pages (TG0 = 0)
+ * 3 level page tables (SL = 1)
+ */
+#define VTCR_EL2_FLAGS		(VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \
+				 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
+				 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
+				 VTCR_EL2_T0SZ_40B)
+#define VTTBR_X		(37 - VTCR_EL2_T0SZ_40B)
+#endif
+
+#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
+#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_VMID_SHIFT  (48LLU)
+#define VTTBR_VMID_MASK	  (0xffLLU << VTTBR_VMID_SHIFT)
+
+/* Hyp System Trap Register */
+#define HSTR_EL2_TTEE	(1 << 16)
+#define HSTR_EL2_T(x)	(1 << x)
+
+/* Hyp Coprocessor Trap Register */
+#define CPTR_EL2_TCPAC	(1 << 31)
+#define CPTR_EL2_TTA	(1 << 20)
+#define CPTR_EL2_TFP	(1 << 10)
+
+/* Hyp Debug Configuration Register bits */
+#define MDCR_EL2_TDRA		(1 << 11)
+#define MDCR_EL2_TDOSA		(1 << 10)
+#define MDCR_EL2_TDA		(1 << 9)
+#define MDCR_EL2_TDE		(1 << 8)
+#define MDCR_EL2_HPME		(1 << 7)
+#define MDCR_EL2_TPM		(1 << 6)
+#define MDCR_EL2_TPMCR		(1 << 5)
+#define MDCR_EL2_HPMN_MASK	(0x1F)
+
+/* Exception Syndrome Register (ESR) bits */
+#define ESR_EL2_EC_SHIFT	(26)
+#define ESR_EL2_EC		(0x3fU << ESR_EL2_EC_SHIFT)
+#define ESR_EL2_IL		(1U << 25)
+#define ESR_EL2_ISS		(ESR_EL2_IL - 1)
+#define ESR_EL2_ISV_SHIFT	(24)
+#define ESR_EL2_ISV		(1U << ESR_EL2_ISV_SHIFT)
+#define ESR_EL2_SAS_SHIFT	(22)
+#define ESR_EL2_SAS		(3U << ESR_EL2_SAS_SHIFT)
+#define ESR_EL2_SSE		(1 << 21)
+#define ESR_EL2_SRT_SHIFT	(16)
+#define ESR_EL2_SRT_MASK	(0x1f << ESR_EL2_SRT_SHIFT)
+#define ESR_EL2_SF 		(1 << 15)
+#define ESR_EL2_AR 		(1 << 14)
+#define ESR_EL2_EA 		(1 << 9)
+#define ESR_EL2_CM 		(1 << 8)
+#define ESR_EL2_S1PTW 		(1 << 7)
+#define ESR_EL2_WNR		(1 << 6)
+#define ESR_EL2_FSC		(0x3f)
+#define ESR_EL2_FSC_TYPE	(0x3c)
+
+#define ESR_EL2_CV_SHIFT	(24)
+#define ESR_EL2_CV		(1U << ESR_EL2_CV_SHIFT)
+#define ESR_EL2_COND_SHIFT	(20)
+#define ESR_EL2_COND		(0xfU << ESR_EL2_COND_SHIFT)
+
+
+#define FSC_FAULT	(0x04)
+#define FSC_PERM	(0x0c)
+
+/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
+#define HPFAR_MASK	(~0xFUL)
+
+#define ESR_EL2_EC_UNKNOWN	(0x00)
+#define ESR_EL2_EC_WFI		(0x01)
+#define ESR_EL2_EC_CP15_32	(0x03)
+#define ESR_EL2_EC_CP15_64	(0x04)
+#define ESR_EL2_EC_CP14_MR	(0x05)
+#define ESR_EL2_EC_CP14_LS	(0x06)
+#define ESR_EL2_EC_FP_ASIMD	(0x07)
+#define ESR_EL2_EC_CP10_ID	(0x08)
+#define ESR_EL2_EC_CP14_64	(0x0C)
+#define ESR_EL2_EC_ILL_ISS	(0x0E)
+#define ESR_EL2_EC_SVC32	(0x11)
+#define ESR_EL2_EC_HVC32	(0x12)
+#define ESR_EL2_EC_SMC32	(0x13)
+#define ESR_EL2_EC_SVC64	(0x15)
+#define ESR_EL2_EC_HVC64	(0x16)
+#define ESR_EL2_EC_SMC64	(0x17)
+#define ESR_EL2_EC_SYS64	(0x18)
+#define ESR_EL2_EC_IABT		(0x20)
+#define ESR_EL2_EC_IABT_HYP	(0x21)
+#define ESR_EL2_EC_PC_ALIGN	(0x22)
+#define ESR_EL2_EC_DABT		(0x24)
+#define ESR_EL2_EC_DABT_HYP	(0x25)
+#define ESR_EL2_EC_SP_ALIGN	(0x26)
+#define ESR_EL2_EC_FP_EXC32	(0x28)
+#define ESR_EL2_EC_FP_EXC64	(0x2C)
+#define ESR_EL2_EC_SERRROR	(0x2F)
+#define ESR_EL2_EC_BREAKPT	(0x30)
+#define ESR_EL2_EC_BREAKPT_HYP	(0x31)
+#define ESR_EL2_EC_SOFTSTP	(0x32)
+#define ESR_EL2_EC_SOFTSTP_HYP	(0x33)
+#define ESR_EL2_EC_WATCHPT	(0x34)
+#define ESR_EL2_EC_WATCHPT_HYP	(0x35)
+#define ESR_EL2_EC_BKPT32	(0x38)
+#define ESR_EL2_EC_VECTOR32	(0x3A)
+#define ESR_EL2_EC_BRK64	(0x3C)
+
+#define ESR_EL2_EC_xABT_xFSR_EXTABT	0x10
+
+#endif /* __ARM64_KVM_ARM_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:42 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:42 +0100
Subject: [PATCH v4 14/32] arm64: KVM: guest one-reg interface
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-15-git-send-email-marc.zyngier@arm.com>

Let userspace play with the guest registers.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/guest.c | 253 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 253 insertions(+)
 create mode 100644 arch/arm64/kvm/guest.c

diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
new file mode 100644
index 0000000..c8d48b2
--- /dev/null
+++ b/arch/arm64/kvm/guest.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/kvm/guest.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <asm/cputype.h>
+#include <asm/uaccess.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+
+struct kvm_stats_debugfs_item debugfs_entries[] = {
+	{ NULL }
+};
+
+int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
+{
+	vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
+	return 0;
+}
+
+static u64 core_reg_offset_from_id(u64 id)
+{
+	return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
+
+static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	__u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
+	struct kvm_regs *regs = vcpu_gp_regs(vcpu);
+	int nr_regs = sizeof(*regs) / sizeof(__u32);
+	u32 off;
+
+	/* Our ID is an index into the kvm_regs struct. */
+	off = core_reg_offset_from_id(reg->id);
+	if (off >= nr_regs ||
+	    (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
+		return -ENOENT;
+
+	if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	__u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
+	struct kvm_regs *regs = vcpu_gp_regs(vcpu);
+	int nr_regs = sizeof(*regs) / sizeof(__u32);
+	__uint128_t tmp;
+	void *valp = &tmp;
+	u64 off;
+	int err = 0;
+
+	/* Our ID is an index into the kvm_regs struct. */
+	off = core_reg_offset_from_id(reg->id);
+	if (off >= nr_regs ||
+	    (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
+		return -ENOENT;
+
+	if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
+		return -EINVAL;
+
+	if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
+		err = -EFAULT;
+		goto out;
+	}
+
+	if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
+		u32 mode = (*(u32 *)valp) & COMPAT_PSR_MODE_MASK;
+		switch (mode) {
+		case PSR_MODE_EL0t:
+		case PSR_MODE_EL1t:
+		case PSR_MODE_EL1h:
+			break;
+		default:
+			err = -EINVAL;
+			goto out;
+		}
+	}
+
+	memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id));
+out:
+	return err;
+}
+
+int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+	return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+	return -EINVAL;
+}
+
+static unsigned long num_core_regs(void)
+{
+	return sizeof(struct kvm_regs) / sizeof(__u32);
+}
+
+/**
+ * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
+ *
+ * This is for all registers.
+ */
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
+{
+	return num_core_regs() + kvm_arm_num_sys_reg_descs(vcpu);
+}
+
+/**
+ * kvm_arm_copy_reg_indices - get indices of all registers.
+ *
+ * We do core registers right here, then we apppend system regs.
+ */
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+	unsigned int i;
+	const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE;
+
+	for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
+		if (put_user(core_reg | i, uindices))
+			return -EFAULT;
+		uindices++;
+	}
+
+	return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
+}
+
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	/* We currently use nothing arch-specific in upper 32 bits */
+	if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
+		return -EINVAL;
+
+	/* Register group 16 means we want a core register. */
+	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+		return get_core_reg(vcpu, reg);
+
+	return kvm_arm_sys_reg_get_reg(vcpu, reg);
+}
+
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	/* We currently use nothing arch-specific in upper 32 bits */
+	if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
+		return -EINVAL;
+
+	/* Register group 16 means we set a core register. */
+	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+		return set_core_reg(vcpu, reg);
+
+	return kvm_arm_sys_reg_set_reg(vcpu, reg);
+}
+
+int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
+				  struct kvm_sregs *sregs)
+{
+	return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
+				  struct kvm_sregs *sregs)
+{
+	return -EINVAL;
+}
+
+int __attribute_const__ kvm_target_cpu(void)
+{
+	unsigned long implementor = read_cpuid_implementor();
+	unsigned long part_number = read_cpuid_part_number();
+
+	if (implementor != ARM_CPU_IMP_ARM)
+		return -EINVAL;
+
+	switch (part_number) {
+	case ARM_CPU_PART_AEM_V8:
+		return KVM_ARM_TARGET_AEM_V8;
+	case ARM_CPU_PART_FOUNDATION:
+		return KVM_ARM_TARGET_FOUNDATION_V8;
+	case ARM_CPU_PART_CORTEX_A57:
+		/* Currently handled by the generic backend */
+		return KVM_ARM_TARGET_CORTEX_A57;
+	default:
+		return -EINVAL;
+	}
+}
+
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+			const struct kvm_vcpu_init *init)
+{
+	unsigned int i;
+	int phys_target = kvm_target_cpu();
+
+	if (init->target != phys_target)
+		return -EINVAL;
+
+	vcpu->arch.target = phys_target;
+	bitmap_zero(vcpu->arch.features, KVM_VCPU_MAX_FEATURES);
+
+	/* -ENOENT for unknown features, -EINVAL for invalid combinations. */
+	for (i = 0; i < sizeof(init->features) * 8; i++) {
+		if (init->features[i / 32] & (1 << (i % 32))) {
+			if (i >= KVM_VCPU_MAX_FEATURES)
+				return -ENOENT;
+			set_bit(i, vcpu->arch.features);
+		}
+	}
+
+	/* Now we know what it is, we can reset it. */
+	return kvm_reset_vcpu(vcpu);
+}
+
+int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+	return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+	return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
+				  struct kvm_translation *tr)
+{
+	return -EINVAL;
+}
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:43 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:43 +0100
Subject: [PATCH v4 15/32] arm64: KVM: hypervisor initialization code
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-16-git-send-email-marc.zyngier@arm.com>

Provide EL2 with page tables and stack, and set the vectors
to point to the full blown world-switch code.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_host.h |  13 +++++
 arch/arm64/kvm/hyp-init.S         | 112 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 arch/arm64/kvm/hyp-init.S

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 4a2622f..2500eb6 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -183,4 +183,17 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
 int kvm_perf_init(void);
 int kvm_perf_teardown(void);
 
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+				       phys_addr_t pgd_ptr,
+				       unsigned long hyp_stack_ptr,
+				       unsigned long vector_ptr)
+{
+	/*
+	 * Call initialization code, and switch to the full blown
+	 * HYP code.
+	 */
+	kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
+		     hyp_stack_ptr, vector_ptr);
+}
+
 #endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
new file mode 100644
index 0000000..4a9cfd2
--- /dev/null
+++ b/arch/arm64/kvm/hyp-init.S
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+
+	.text
+	.pushsection	.hyp.idmap.text, "ax"
+
+	.align	11
+
+__kvm_hyp_init:
+	.global	__kvm_hyp_init
+
+ENTRY(__kvm_hyp_init_vector)
+	ventry	__invalid		// Synchronous EL2t
+	ventry	__invalid		// IRQ EL2t
+	ventry	__invalid		// FIQ EL2t
+	ventry	__invalid		// Error EL2t
+
+	ventry	__invalid		// Synchronous EL2h
+	ventry	__invalid		// IRQ EL2h
+	ventry	__invalid		// FIQ EL2h
+	ventry	__invalid		// Error EL2h
+
+	ventry	__do_hyp_init		// Synchronous 64-bit EL1
+	ventry	__invalid		// IRQ 64-bit EL1
+	ventry	__invalid		// FIQ 64-bit EL1
+	ventry	__invalid		// Error 64-bit EL1
+
+	ventry	__invalid		// Synchronous 32-bit EL1
+	ventry	__invalid		// IRQ 32-bit EL1
+	ventry	__invalid		// FIQ 32-bit EL1
+	ventry	__invalid		// Error 32-bit EL1
+ENDPROC(__kvm_hyp_init_vector)
+
+__invalid:
+	b	.
+
+	/*
+	 * x0: HYP boot pgd
+	 * x1: HYP pgd
+	 * x2: HYP stack
+	 * x3: HYP vectors
+	 */
+__do_hyp_init:
+
+	msr	ttbr0_el2, x0
+
+	mrs	x4, tcr_el1
+	ldr	x5, =TCR_EL2_MASK
+	and	x4, x4, x5
+	ldr	x5, =TCR_EL2_FLAGS
+	orr	x4, x4, x5
+	msr	tcr_el2, x4
+
+	ldr	x4, =VTCR_EL2_FLAGS
+	msr	vtcr_el2, x4
+
+	mrs	x4, mair_el1
+	msr	mair_el2, x4
+	isb
+
+	mov	x4, #SCTLR_EL2_FLAGS
+	msr	sctlr_el2, x4
+	isb
+
+	/* MMU is now enabled. Get ready for the trampoline dance */
+	ldr	x4, =TRAMPOLINE_VA
+	adr	x5, target
+	bfi	x4, x5, #0, #PAGE_SHIFT
+	br	x4
+
+	nop
+
+target: /* We're now in the trampoline code, switch page tables */
+	msr	ttbr0_el2, x1
+	isb
+
+	/* Invalidate the old TLBs */
+	tlbi	alle2
+	dsb	sy
+
+	/* Set the stack and new vectors */
+	kern_hyp_va	x2
+	mov	sp, x2
+	kern_hyp_va	x3
+	msr	vbar_el2, x3
+
+	/* Hello, World! */
+	eret
+
+	.ltorg
+
+	.popsection
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:39 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:39 +0100
Subject: [PATCH v4 11/32] arm64: KVM: virtual CPU reset
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-12-git-send-email-marc.zyngier@arm.com>

Provide the reset code for a virtual CPU booted in 64bit mode.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/reset.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 arch/arm64/kvm/reset.c

diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
new file mode 100644
index 0000000..84112e0
--- /dev/null
+++ b/arch/arm64/kvm/reset.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/kvm/reset.c
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/errno.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm.h>
+
+#include <asm/cputype.h>
+#include <asm/ptrace.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_coproc.h>
+
+/*
+ * ARMv8 Reset Values
+ */
+static struct kvm_regs default_regs_reset = {
+	.regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
+			PSR_F_BIT | PSR_D_BIT),
+};
+
+int kvm_arch_dev_ioctl_check_extension(long ext)
+{
+	int r;
+
+	switch (ext) {
+	default:
+		r = 0;
+	}
+
+	return r;
+}
+
+
+/**
+ * kvm_reset_vcpu - sets core registers and sys_regs to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on
+ * the virtual CPU struct to their architectually defined reset
+ * values.
+ */
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
+{
+	struct kvm_regs *cpu_reset;
+
+	switch (vcpu->arch.target) {
+	default:
+		cpu_reset = &default_regs_reset;
+		break;
+	}
+
+	/* Reset core registers */
+	memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset));
+
+	/* Reset system registers */
+	kvm_reset_sys_regs(vcpu);
+
+	return 0;
+}
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:40 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:40 +0100
Subject: [PATCH v4 12/32] arm64: KVM: kvm_arch and kvm_vcpu_arch definitions
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-13-git-send-email-marc.zyngier@arm.com>

Provide the architecture dependent structures for VM and
vcpu abstractions.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_host.h | 186 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 186 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_host.h

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
new file mode 100644
index 0000000..4a2622f
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/include/asm/kvm_host.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_HOST_H__
+#define __ARM64_KVM_HOST_H__
+
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+
+#define KVM_MAX_VCPUS 4
+#define KVM_USER_MEM_SLOTS 32
+#define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+#include <kvm/arm_vgic.h>
+#include <kvm/arm_arch_timer.h>
+
+#define KVM_VCPU_MAX_FEATURES 0
+
+/* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x)	0
+#define KVM_NR_PAGE_SIZES	1
+#define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
+
+struct kvm_vcpu;
+int kvm_target_cpu(void);
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
+int kvm_arch_dev_ioctl_check_extension(long ext);
+
+struct kvm_arch {
+	/* The VMID generation used for the virt. memory system */
+	u64    vmid_gen;
+	u32    vmid;
+
+	/* 1-level 2nd stage table and lock */
+	spinlock_t pgd_lock;
+	pgd_t *pgd;
+
+	/* VTTBR value associated with above pgd and vmid */
+	u64    vttbr;
+
+	/* Interrupt controller */
+	struct vgic_dist	vgic;
+
+	/* Timer */
+	struct arch_timer_kvm	timer;
+};
+
+#define KVM_NR_MEM_OBJS     40
+
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+	int nobjs;
+	void *objects[KVM_NR_MEM_OBJS];
+};
+
+struct kvm_vcpu_fault_info {
+	u32 esr_el2;		/* Hyp Syndrom Register */
+	u64 far_el2;		/* Hyp Fault Address Register */
+	u64 hpfar_el2;		/* Hyp IPA Fault Address Register */
+};
+
+struct kvm_cpu_context {
+	struct kvm_regs	gp_regs;
+	u64 sys_regs[NR_SYS_REGS];
+};
+
+typedef struct kvm_cpu_context kvm_cpu_context_t;
+
+struct kvm_vcpu_arch {
+	struct kvm_cpu_context ctxt;
+
+	/* HYP configuration */
+	u64 hcr_el2;
+
+	/* Exception Information */
+	struct kvm_vcpu_fault_info fault;
+
+	/* Pointer to host CPU context */
+	kvm_cpu_context_t *host_cpu_context;
+
+	/* VGIC state */
+	struct vgic_cpu vgic_cpu;
+	struct arch_timer_cpu timer_cpu;
+
+	/*
+	 * Anything that is not used directly from assembly code goes
+	 * here.
+	 */
+	/* dcache set/way operation pending */
+	int last_pcpu;
+	cpumask_t require_dcache_flush;
+
+	/* Don't run the guest */
+	bool pause;
+
+	/* IO related fields */
+	struct kvm_decode mmio_decode;
+
+	/* Interrupt related fields */
+	u64 irq_lines;		/* IRQ and FIQ levels */
+
+	/* Cache some mmu pages needed inside spinlock regions */
+	struct kvm_mmu_memory_cache mmu_page_cache;
+
+	/* Target CPU and feature flags */
+	u32 target;
+	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
+
+	/* Detect first run of a vcpu */
+	bool has_run_once;
+};
+
+#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)
+#define vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])
+#define vcpu_cp15(v,r)		((v)->arch.ctxt.cp15[(r)])
+
+struct kvm_vm_stat {
+	u32 remote_tlb_flush;
+};
+
+struct kvm_vcpu_stat {
+	u32 halt_wakeup;
+};
+
+struct kvm_vcpu_init;
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+			const struct kvm_vcpu_init *init);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+struct kvm_one_reg;
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+struct kvm;
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
+int kvm_unmap_hva_range(struct kvm *kvm,
+			unsigned long start, unsigned long end);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+
+/* We do not have shadow page tables, hence the empty hooks */
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+	return 0;
+}
+
+static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
+{
+	return 0;
+}
+
+struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
+struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
+
+u64 kvm_call_hyp(void *hypfn, ...);
+
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+		int exception_index);
+
+int kvm_perf_init(void);
+int kvm_perf_teardown(void);
+
+#endif /* __ARM64_KVM_HOST_H__ */
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:44 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:44 +0100
Subject: [PATCH v4 16/32] arm64: KVM: HYP mode world switch implementation
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-17-git-send-email-marc.zyngier@arm.com>

The HYP mode world switch in all its glory.

Implements save/restore of host/guest registers, EL2 trapping,
IPA resolution, and additional services (tlb invalidation).

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kernel/asm-offsets.c |  34 +++
 arch/arm64/kvm/hyp.S            | 603 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 637 insertions(+)
 create mode 100644 arch/arm64/kvm/hyp.S

diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index a2a4d81..666e231 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -21,6 +21,7 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
+#include <linux/kvm_host.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/cputable.h>
@@ -104,5 +105,38 @@ int main(void)
   BLANK();
   DEFINE(TZ_MINWEST,		offsetof(struct timezone, tz_minuteswest));
   DEFINE(TZ_DSTTIME,		offsetof(struct timezone, tz_dsttime));
+  BLANK();
+#ifdef CONFIG_KVM_ARM_HOST
+  DEFINE(VCPU_CONTEXT,		offsetof(struct kvm_vcpu, arch.ctxt));
+  DEFINE(CPU_GP_REGS,		offsetof(struct kvm_cpu_context, gp_regs));
+  DEFINE(CPU_USER_PT_REGS,	offsetof(struct kvm_regs, regs));
+  DEFINE(CPU_FP_REGS,		offsetof(struct kvm_regs, fp_regs));
+  DEFINE(CPU_SP_EL1,		offsetof(struct kvm_regs, sp_el1));
+  DEFINE(CPU_ELR_EL1,		offsetof(struct kvm_regs, elr_el1));
+  DEFINE(CPU_SPSR,		offsetof(struct kvm_regs, spsr));
+  DEFINE(CPU_SYSREGS,		offsetof(struct kvm_cpu_context, sys_regs));
+  DEFINE(VCPU_ESR_EL2,		offsetof(struct kvm_vcpu, arch.fault.esr_el2));
+  DEFINE(VCPU_FAR_EL2,		offsetof(struct kvm_vcpu, arch.fault.far_el2));
+  DEFINE(VCPU_HPFAR_EL2,	offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
+  DEFINE(VCPU_HCR_EL2,		offsetof(struct kvm_vcpu, arch.hcr_el2));
+  DEFINE(VCPU_IRQ_LINES,	offsetof(struct kvm_vcpu, arch.irq_lines));
+  DEFINE(VCPU_HOST_CONTEXT,	offsetof(struct kvm_vcpu, arch.host_cpu_context));
+  DEFINE(VCPU_TIMER_CNTV_CTL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
+  DEFINE(VCPU_TIMER_CNTV_CVAL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
+  DEFINE(KVM_TIMER_CNTVOFF,	offsetof(struct kvm, arch.timer.cntvoff));
+  DEFINE(KVM_TIMER_ENABLED,	offsetof(struct kvm, arch.timer.enabled));
+  DEFINE(VCPU_KVM,		offsetof(struct kvm_vcpu, kvm));
+  DEFINE(VCPU_VGIC_CPU,		offsetof(struct kvm_vcpu, arch.vgic_cpu));
+  DEFINE(VGIC_CPU_HCR,		offsetof(struct vgic_cpu, vgic_hcr));
+  DEFINE(VGIC_CPU_VMCR,		offsetof(struct vgic_cpu, vgic_vmcr));
+  DEFINE(VGIC_CPU_MISR,		offsetof(struct vgic_cpu, vgic_misr));
+  DEFINE(VGIC_CPU_EISR,		offsetof(struct vgic_cpu, vgic_eisr));
+  DEFINE(VGIC_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_elrsr));
+  DEFINE(VGIC_CPU_APR,		offsetof(struct vgic_cpu, vgic_apr));
+  DEFINE(VGIC_CPU_LR,		offsetof(struct vgic_cpu, vgic_lr));
+  DEFINE(VGIC_CPU_NR_LR,	offsetof(struct vgic_cpu, nr_lr));
+  DEFINE(KVM_VTTBR,		offsetof(struct kvm, arch.vttbr));
+  DEFINE(KVM_VGIC_VCTRL,	offsetof(struct kvm, arch.vgic.vctrl_base));
+#endif
   return 0;
 }
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
new file mode 100644
index 0000000..e6884d3
--- /dev/null
+++ b/arch/arm64/kvm/hyp.S
@@ -0,0 +1,603 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/irqchip/arm-gic.h>
+
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <asm/asm-offsets.h>
+#include <asm/fpsimdmacros.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+
+#define CPU_GP_REG_OFFSET(x)	(CPU_GP_REGS + x)
+#define CPU_XREG_OFFSET(x)	CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
+#define CPU_SPSR_OFFSET(x)	CPU_GP_REG_OFFSET(CPU_SPSR + 8*x)
+#define CPU_SYSREG_OFFSET(x)	(CPU_SYSREGS + 8*x)
+
+	.text
+	.pushsection	.hyp.text, "ax"
+	.align	PAGE_SHIFT
+
+__kvm_hyp_code_start:
+	.globl __kvm_hyp_code_start
+
+.macro save_common_regs
+	// x2: base address for cpu context
+	// x3: tmp register
+
+	add	x3, x2, #CPU_XREG_OFFSET(19)
+	stp	x19, x20, [x3]
+	stp	x21, x22, [x3, #16]
+	stp	x23, x24, [x3, #32]
+	stp	x25, x26, [x3, #48]
+	stp	x27, x28, [x3, #64]
+	stp	x29, lr, [x3, #80]
+
+	mrs	x19, sp_el0
+	mrs	x20, elr_el2		// EL1 PC
+	mrs	x21, spsr_el2		// EL1 pstate
+
+	stp	x19, x20, [x3, #96]
+	str	x21, [x3, #112]
+
+	mrs	x22, sp_el1
+	mrs	x23, elr_el1
+	mrs	x24, spsr_el1
+
+	str	x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
+	str	x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
+	str	x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
+.endm
+
+.macro restore_common_regs
+	// x2: base address for cpu context
+	// x3: tmp register
+
+	ldr	x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
+	ldr	x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
+	ldr	x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
+
+	msr	sp_el1, x22
+	msr	elr_el1, x23
+	msr	spsr_el1, x24
+
+	add	x3, x2, #CPU_XREG_OFFSET(31)    // SP_EL0
+	ldp	x19, x20, [x3]
+	ldr	x21, [x3, #16]
+
+	msr	sp_el0, x19
+	msr	elr_el2, x20 				// EL1 PC
+	msr	spsr_el2, x21 				// EL1 pstate
+
+	add	x3, x2, #CPU_XREG_OFFSET(19)
+	ldp	x19, x20, [x3]
+	ldp	x21, x22, [x3, #16]
+	ldp	x23, x24, [x3, #32]
+	ldp	x25, x26, [x3, #48]
+	ldp	x27, x28, [x3, #64]
+	ldp	x29, lr, [x3, #80]
+.endm
+
+.macro save_host_regs
+	save_common_regs
+.endm
+
+.macro restore_host_regs
+	restore_common_regs
+.endm
+
+.macro save_fpsimd
+	// x2: cpu context address
+	// x3, x4: tmp regs
+	add	x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
+	fpsimd_save x3, 4
+.endm
+
+.macro restore_fpsimd
+	// x2: cpu context address
+	// x3, x4: tmp regs
+	add	x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
+	fpsimd_restore x3, 4
+.endm
+
+.macro save_guest_regs
+	// x0 is the vcpu address
+	// x1 is the return code, do not corrupt!
+	// x2 is the cpu context
+	// x3 is a tmp register
+	// Guest's x0-x3 are on the stack
+
+	// Compute base to save registers
+	add	x3, x2, #CPU_XREG_OFFSET(4)
+	stp	x4, x5, [x3]
+	stp	x6, x7, [x3, #16]
+	stp	x8, x9, [x3, #32]
+	stp	x10, x11, [x3, #48]
+	stp	x12, x13, [x3, #64]
+	stp	x14, x15, [x3, #80]
+	stp	x16, x17, [x3, #96]
+	str	x18, [x3, #112]
+
+	pop	x6, x7			// x2, x3
+	pop	x4, x5			// x0, x1
+
+	add	x3, x2, #CPU_XREG_OFFSET(0)
+	stp	x4, x5, [x3]
+	stp	x6, x7, [x3, #16]
+
+	save_common_regs
+.endm
+
+.macro restore_guest_regs
+	// x0 is the vcpu address.
+	// x2 is the cpu context
+	// x3 is a tmp register
+
+	// Prepare x0-x3 for later restore
+	add	x3, x2, #CPU_XREG_OFFSET(0)
+	ldp	x4, x5, [x3]
+	ldp	x6, x7, [x3, #16]
+	push	x4, x5		// Push x0-x3 on the stack
+	push	x6, x7
+
+	// x4-x18
+	ldp	x4, x5, [x3, #32]
+	ldp	x6, x7, [x3, #48]
+	ldp	x8, x9, [x3, #64]
+	ldp	x10, x11, [x3, #80]
+	ldp	x12, x13, [x3, #96]
+	ldp	x14, x15, [x3, #112]
+	ldp	x16, x17, [x3, #128]
+	ldr	x18, [x3, #144]
+
+	// x19-x29, lr, sp*, elr*, spsr*
+	restore_common_regs
+
+	// Last bits of the 64bit state
+	pop	x2, x3
+	pop	x0, x1
+
+	// Do not touch any register after this!
+.endm
+
+/*
+ * Macros to perform system register save/restore.
+ *
+ * Ordering here is absolutely critical, and must be kept consistent
+ * in {save,restore}_sysregs, {save,restore}_guest_32bit_state,
+ * and in kvm_asm.h.
+ *
+ * In other words, don't touch any of these unless you know what
+ * you are doing.
+ */
+.macro save_sysregs
+	// x2: base address for cpu context
+	// x3: tmp register
+
+	add	x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
+
+	mrs	x4,	vmpidr_el2
+	mrs	x5,	csselr_el1
+	mrs	x6,	sctlr_el1
+	mrs	x7,	actlr_el1
+	mrs	x8,	cpacr_el1
+	mrs	x9,	ttbr0_el1
+	mrs	x10,	ttbr1_el1
+	mrs	x11,	tcr_el1
+	mrs	x12,	esr_el1
+	mrs	x13, 	afsr0_el1
+	mrs	x14,	afsr1_el1
+	mrs	x15,	far_el1
+	mrs	x16,	mair_el1
+	mrs	x17,	vbar_el1
+	mrs	x18,	contextidr_el1
+	mrs	x19,	tpidr_el0
+	mrs	x20,	tpidrro_el0
+	mrs	x21,	tpidr_el1
+	mrs	x22, 	amair_el1
+	mrs	x23, 	cntkctl_el1
+
+	stp	x4, x5, [x3]
+	stp	x6, x7, [x3, #16]
+	stp	x8, x9, [x3, #32]
+	stp	x10, x11, [x3, #48]
+	stp	x12, x13, [x3, #64]
+	stp	x14, x15, [x3, #80]
+	stp	x16, x17, [x3, #96]
+	stp	x18, x19, [x3, #112]
+	stp	x20, x21, [x3, #128]
+	stp	x22, x23, [x3, #144]
+.endm
+
+.macro restore_sysregs
+	// x2: base address for cpu context
+	// x3: tmp register
+
+	add	x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
+
+	ldp	x4, x5, [x3]
+	ldp	x6, x7, [x3, #16]
+	ldp	x8, x9, [x3, #32]
+	ldp	x10, x11, [x3, #48]
+	ldp	x12, x13, [x3, #64]
+	ldp	x14, x15, [x3, #80]
+	ldp	x16, x17, [x3, #96]
+	ldp	x18, x19, [x3, #112]
+	ldp	x20, x21, [x3, #128]
+	ldp	x22, x23, [x3, #144]
+
+	msr	vmpidr_el2,	x4
+	msr	csselr_el1,	x5
+	msr	sctlr_el1,	x6
+	msr	actlr_el1,	x7
+	msr	cpacr_el1,	x8
+	msr	ttbr0_el1,	x9
+	msr	ttbr1_el1,	x10
+	msr	tcr_el1,	x11
+	msr	esr_el1,	x12
+	msr	afsr0_el1,	x13
+	msr	afsr1_el1,	x14
+	msr	far_el1,	x15
+	msr	mair_el1,	x16
+	msr	vbar_el1,	x17
+	msr	contextidr_el1,	x18
+	msr	tpidr_el0,	x19
+	msr	tpidrro_el0,	x20
+	msr	tpidr_el1,	x21
+	msr	amair_el1,	x22
+	msr	cntkctl_el1,	x23
+.endm
+
+.macro activate_traps
+	ldr	x2, [x0, #VCPU_IRQ_LINES]
+	ldr	x1, [x0, #VCPU_HCR_EL2]
+	orr	x2, x2, x1
+	msr	hcr_el2, x2
+
+	ldr	x2, =(CPTR_EL2_TTA)
+	msr	cptr_el2, x2
+
+	ldr	x2, =(1 << 15)	// Trap CP15 Cr=15
+	msr	hstr_el2, x2
+
+	mrs	x2, mdcr_el2
+	and	x2, x2, #MDCR_EL2_HPMN_MASK
+	orr	x2, x2, #(MDCR_EL2_TPM | MDCR_EL2_TPMCR)
+	msr	mdcr_el2, x2
+.endm
+
+.macro deactivate_traps
+	mov	x2, #HCR_RW
+	msr	hcr_el2, x2
+	msr	cptr_el2, xzr
+	msr	hstr_el2, xzr
+
+	mrs	x2, mdcr_el2
+	and	x2, x2, #MDCR_EL2_HPMN_MASK
+	msr	mdcr_el2, x2
+.endm
+
+.macro activate_vm
+	ldr	x1, [x0, #VCPU_KVM]
+	kern_hyp_va	x1
+	ldr	x2, [x1, #KVM_VTTBR]
+	msr	vttbr_el2, x2
+.endm
+
+.macro deactivate_vm
+	msr	vttbr_el2, xzr
+.endm
+
+__save_sysregs:
+	save_sysregs
+	ret
+
+__restore_sysregs:
+	restore_sysregs
+	ret
+
+__save_fpsimd:
+	save_fpsimd
+	ret
+
+__restore_fpsimd:
+	restore_fpsimd
+	ret
+
+/*
+ * u64 __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+ *
+ * This is the world switch. The first half of the function
+ * deals with entering the guest, and anything from __kvm_vcpu_return
+ * to the end of the function deals with reentering the host.
+ * On the enter path, only x0 (vcpu pointer) must be preserved until
+ * the last moment. On the exit path, x0 (vcpu pointer) and x1 (exception
+ * code) must both be preserved until the epilogue.
+ * In both cases, x2 points to the CPU context we're saving/restoring from/to.
+ */
+ENTRY(__kvm_vcpu_run)
+	kern_hyp_va	x0
+	msr	tpidr_el2, x0	// Save the vcpu register
+
+	// Host context
+	ldr	x2, [x0, #VCPU_HOST_CONTEXT]
+	kern_hyp_va x2
+
+	save_host_regs
+	bl __save_fpsimd
+	bl __save_sysregs
+
+	activate_traps
+	activate_vm
+
+	// Guest context
+	add	x2, x0, #VCPU_CONTEXT
+
+	bl __restore_sysregs
+	bl __restore_fpsimd
+	restore_guest_regs
+
+	// That's it, no more messing around.
+	clrex
+	eret
+
+__kvm_vcpu_return:
+	// Assume x0 is the vcpu pointer, x1 the return code
+	// Guest's x0-x3 are on the stack
+
+	// Guest context
+	add	x2, x0, #VCPU_CONTEXT
+
+	save_guest_regs
+	bl __save_fpsimd
+	bl __save_sysregs
+
+	deactivate_traps
+	deactivate_vm
+
+	// Host context
+	ldr	x2, [x0, #VCPU_HOST_CONTEXT]
+	kern_hyp_va x2
+
+	bl __restore_sysregs
+	bl __restore_fpsimd
+	restore_host_regs
+	mov	x0, x1
+	clrex
+	ret
+END(__kvm_vcpu_run)
+
+// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+ENTRY(__kvm_tlb_flush_vmid_ipa)
+	kern_hyp_va	x0
+	ldr	x2, [x0, #KVM_VTTBR]
+	msr	vttbr_el2, x2
+	isb
+
+	/*
+	 * We could do so much better if we had the VA as well.
+	 * Instead, we invalidate Stage-2 for this IPA, and the
+	 * whole of Stage-1. Weep...
+	 */
+	tlbi	ipas2e1is, x1
+	dsb	sy
+	tlbi	vmalle1is
+	dsb	sy
+	isb
+
+	msr	vttbr_el2, xzr
+	isb
+	ret
+ENDPROC(__kvm_tlb_flush_vmid_ipa)
+
+ENTRY(__kvm_flush_vm_context)
+	tlbi	alle1is
+	ic	ialluis
+	dsb	sy
+	isb
+	ret
+ENDPROC(__kvm_flush_vm_context)
+
+__kvm_hyp_panic:
+	adr	x0, __hyp_panic_str
+	adr	x1, 1f
+	ldp	x2, x3, [x1]
+	sub	x0, x0, x2
+	add	x0, x0, x3
+	mrs	x1, spsr_el2
+	mrs	x2, elr_el2
+	mrs	x3, esr_el2
+	mrs	x4, far_el2
+	mrs	x5, hpfar_el2
+	mrs	x6, tpidr_el2
+
+	mov	lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
+		      PSR_MODE_EL1h)
+	msr	spsr_el2, lr
+	ldr	lr, =panic
+	msr	elr_el2, lr
+	eret
+
+	.align	3
+1:	.quad	HYP_PAGE_OFFSET
+	.quad	PAGE_OFFSET
+ENDPROC(__kvm_hyp_panic)
+
+__hyp_panic_str:
+	.ascii	"HYP panic:\nPS:%08x PC:%p ESR:%p\nFAR:%p HPFAR:%p VCPU:%p\n\0"
+
+	.align	2
+
+ENTRY(kvm_call_hyp)
+	hvc	#0
+	ret
+ENDPROC(kvm_call_hyp)
+
+.macro invalid_vector	label, target
+	.align	2
+\label:
+	b \target
+ENDPROC(\label)
+.endm
+
+	/* None of these should ever happen */
+	invalid_vector	el2t_sync_invalid, __kvm_hyp_panic
+	invalid_vector	el2t_irq_invalid, __kvm_hyp_panic
+	invalid_vector	el2t_fiq_invalid, __kvm_hyp_panic
+	invalid_vector	el2t_error_invalid, __kvm_hyp_panic
+	invalid_vector	el2h_sync_invalid, __kvm_hyp_panic
+	invalid_vector	el2h_irq_invalid, __kvm_hyp_panic
+	invalid_vector	el2h_fiq_invalid, __kvm_hyp_panic
+	invalid_vector	el2h_error_invalid, __kvm_hyp_panic
+	invalid_vector	el1_sync_invalid, __kvm_hyp_panic
+	invalid_vector	el1_irq_invalid, __kvm_hyp_panic
+	invalid_vector	el1_fiq_invalid, __kvm_hyp_panic
+	invalid_vector	el1_error_invalid, __kvm_hyp_panic
+
+el1_sync:					// Guest trapped into EL2
+	push	x0, x1
+	push	x2, x3
+
+	mrs	x1, esr_el2
+	lsr	x2, x1, #ESR_EL2_EC_SHIFT
+
+	cmp	x2, #ESR_EL2_EC_HVC64
+	b.ne	el1_trap
+
+	mrs	x3, vttbr_el2			// If vttbr is valid, the 64bit guest
+	cbnz	x3, el1_trap			// called HVC
+
+	/* Here, we're pretty sure the host called HVC. */
+	pop	x2, x3
+	pop	x0, x1
+
+	push	lr, xzr
+
+	/*
+	 * Compute the function address in EL2, and shuffle the parameters.
+	 */
+	kern_hyp_va	x0
+	mov	lr, x0
+	mov	x0, x1
+	mov	x1, x2
+	mov	x2, x3
+	blr	lr
+
+	pop	lr, xzr
+	eret
+
+el1_trap:
+	/*
+	 * x1: ESR
+	 * x2: ESR_EC
+	 */
+	cmp	x2, #ESR_EL2_EC_DABT
+	mov	x0, #ESR_EL2_EC_IABT
+	ccmp	x2, x0, #4, ne
+	b.ne	1f		// Not an abort we care about
+
+	/* This is an abort. Check for permission fault */
+	and	x2, x1, #ESR_EL2_FSC_TYPE
+	cmp	x2, #FSC_PERM
+	b.ne	1f		// Not a permission fault
+
+	/*
+	 * Check for Stage-1 page table walk, which is guaranteed
+	 * to give a valid HPFAR_EL2.
+	 */
+	tbnz	x1, #7, 1f	// S1PTW is set
+
+	/*
+	 * Permission fault, HPFAR_EL2 is invalid.
+	 * Resolve the IPA the hard way using the guest VA.
+	 * Stage-1 translation already validated the memory access rights.
+	 * As such, we can use the EL1 translation regime, and don't have
+	 * to distinguish between EL0 and EL1 access.
+	 */
+	mrs	x2, far_el2
+	at	s1e1r, x2
+	isb
+
+	/* Read result */
+	mrs	x3, par_el1
+	tbnz	x3, #1, 3f		// Bail out if we failed the translation
+	ubfx	x3, x3, #12, #36	// Extract IPA
+	lsl	x3, x3, #4		// and present it like HPFAR
+	b	2f
+
+1:	mrs	x3, hpfar_el2
+	mrs	x2, far_el2
+
+2:	mrs	x0, tpidr_el2
+	str	x1, [x0, #VCPU_ESR_EL2]
+	str	x2, [x0, #VCPU_FAR_EL2]
+	str	x3, [x0, #VCPU_HPFAR_EL2]
+
+	mov	x1, #ARM_EXCEPTION_TRAP
+	b	__kvm_vcpu_return
+
+	/*
+	 * Translation failed. Just return to the guest and
+	 * let it fault again. Another CPU is probably playing
+	 * behind our back.
+	 */
+3:	pop	x2, x3
+	pop	x0, x1
+
+	eret
+
+el1_irq:
+	push	x0, x1
+	push	x2, x3
+	mrs	x0, tpidr_el2
+	mov	x1, #ARM_EXCEPTION_IRQ
+	b	__kvm_vcpu_return
+
+	.ltorg
+
+	.align 11
+
+ENTRY(__kvm_hyp_vector)
+	ventry	el2t_sync_invalid		// Synchronous EL2t
+	ventry	el2t_irq_invalid		// IRQ EL2t
+	ventry	el2t_fiq_invalid		// FIQ EL2t
+	ventry	el2t_error_invalid		// Error EL2t
+
+	ventry	el2h_sync_invalid		// Synchronous EL2h
+	ventry	el2h_irq_invalid		// IRQ EL2h
+	ventry	el2h_fiq_invalid		// FIQ EL2h
+	ventry	el2h_error_invalid		// Error EL2h
+
+	ventry	el1_sync			// Synchronous 64-bit EL1
+	ventry	el1_irq				// IRQ 64-bit EL1
+	ventry	el1_fiq_invalid			// FIQ 64-bit EL1
+	ventry	el1_error_invalid		// Error 64-bit EL1
+
+	ventry	el1_sync			// Synchronous 32-bit EL1
+	ventry	el1_irq				// IRQ 32-bit EL1
+	ventry	el1_fiq_invalid			// FIQ 32-bit EL1
+	ventry	el1_error_invalid		// Error 32-bit EL1
+ENDPROC(__kvm_hyp_vector)
+
+__kvm_hyp_code_end:
+	.globl	__kvm_hyp_code_end
+
+	.popsection
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:37 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:37 +0100
Subject: [PATCH v4 09/32] arm64: KVM: system register handling
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-10-git-send-email-marc.zyngier@arm.com>

Provide 64bit system register handling, modeled after the cp15
handling for ARM.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_coproc.h |  51 +++
 arch/arm64/include/uapi/asm/kvm.h   |  29 ++
 arch/arm64/kvm/sys_regs.c           | 883 ++++++++++++++++++++++++++++++++++++
 arch/arm64/kvm/sys_regs.h           | 138 ++++++
 include/uapi/linux/kvm.h            |   1 +
 5 files changed, 1102 insertions(+)
 create mode 100644 arch/arm64/include/asm/kvm_coproc.h
 create mode 100644 arch/arm64/kvm/sys_regs.c
 create mode 100644 arch/arm64/kvm/sys_regs.h

diff --git a/arch/arm64/include/asm/kvm_coproc.h b/arch/arm64/include/asm/kvm_coproc.h
new file mode 100644
index 0000000..9b4477a
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_coproc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/include/asm/kvm_coproc.h
+ * Copyright (C) 2012 Rusty Russell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_COPROC_H__
+#define __ARM64_KVM_COPROC_H__
+
+#include <linux/kvm_host.h>
+
+void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
+
+struct kvm_sys_reg_table {
+	const struct sys_reg_desc *table;
+	size_t num;
+};
+
+struct kvm_sys_reg_target_table {
+	struct kvm_sys_reg_table table64;
+};
+
+void kvm_register_target_sys_reg_table(unsigned int target,
+				       struct kvm_sys_reg_target_table *table);
+
+int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run);
+
+#define kvm_coproc_table_init kvm_sys_reg_table_init
+void kvm_sys_reg_table_init(void);
+
+struct kvm_one_reg;
+int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
+
+#endif /* __ARM64_KVM_COPROC_H__ */
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 4e64570..ebac919 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -92,6 +92,35 @@ struct kvm_sync_regs {
 struct kvm_arch_memory_slot {
 };
 
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000
+#define KVM_REG_ARM_COPROC_SHIFT	16
+
+/* Normal registers are mapped as coprocessor 16. */
+#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))
+
+/* Some registers need more space to represent values. */
+#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00
+#define KVM_REG_ARM_DEMUX_ID_SHIFT	8
+#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
+#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF
+#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0
+
+/* AArch64 system registers */
+#define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000
+#define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14
+#define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800
+#define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11
+#define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780
+#define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7
+#define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078
+#define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3
+#define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
+#define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0
+
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT		24
 #define KVM_ARM_IRQ_TYPE_MASK		0xff
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
new file mode 100644
index 0000000..52fff0a
--- /dev/null
+++ b/arch/arm64/kvm/sys_regs.c
@@ -0,0 +1,883 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/kvm/coproc.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty at rustcorp.com.au>
+ *          Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <linux/uaccess.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <trace/events/kvm.h>
+
+#include "sys_regs.h"
+
+/*
+ * All of this file is extremly similar to the ARM coproc.c, but the
+ * types are different. My gut feeling is that it should be pretty
+ * easy to merge, but that would be an ABI breakage -- again. VFP
+ * would also need to be abstracted.
+ */
+
+/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
+static u32 cache_levels;
+
+/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
+#define CSSELR_MAX 12
+
+/* Which cache CCSIDR represents depends on CSSELR value. */
+static u32 get_ccsidr(u32 csselr)
+{
+	u32 ccsidr;
+
+	/* Make sure noone else changes CSSELR during this! */
+	local_irq_disable();
+	/* Put value into CSSELR */
+	asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
+	isb();
+	/* Read result out of CCSIDR */
+	asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
+	local_irq_enable();
+
+	return ccsidr;
+}
+
+static void do_dc_cisw(u32 val)
+{
+	asm volatile("dc cisw, %x0" : : "r" (val));
+	dsb();
+}
+
+static void do_dc_csw(u32 val)
+{
+	asm volatile("dc csw, %x0" : : "r" (val));
+	dsb();
+}
+
+/* See note at ARM ARM B1.14.4 */
+static bool access_dcsw(struct kvm_vcpu *vcpu,
+			const struct sys_reg_params *p,
+			const struct sys_reg_desc *r)
+{
+	unsigned long val;
+	int cpu;
+
+	if (!p->is_write)
+		return read_from_write_only(vcpu, p);
+
+	cpu = get_cpu();
+
+	cpumask_setall(&vcpu->arch.require_dcache_flush);
+	cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
+
+	/* If we were already preempted, take the long way around */
+	if (cpu != vcpu->arch.last_pcpu) {
+		flush_cache_all();
+		goto done;
+	}
+
+	val = *vcpu_reg(vcpu, p->Rt);
+
+	switch (p->CRm) {
+	case 6:			/* Upgrade DCISW to DCCISW, as per HCR.SWIO */
+	case 14:		/* DCCISW */
+		do_dc_cisw(val);
+		break;
+
+	case 10:		/* DCCSW */
+		do_dc_csw(val);
+		break;
+	}
+
+done:
+	put_cpu();
+
+	return true;
+}
+
+/*
+ * We could trap ID_DFR0 and tell the guest we don't support performance
+ * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
+ * NAKed, so it will read the PMCR anyway.
+ *
+ * Therefore we tell the guest we have 0 counters.  Unfortunately, we
+ * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
+ * all PM registers, which doesn't crash the guest kernel at least.
+ */
+static bool pm_fake(struct kvm_vcpu *vcpu,
+		    const struct sys_reg_params *p,
+		    const struct sys_reg_desc *r)
+{
+	if (p->is_write)
+		return ignore_write(vcpu, p);
+	else
+		return read_zero(vcpu, p);
+}
+
+static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	u64 amair;
+
+	asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
+	vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
+}
+
+static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	/*
+	 * Simply map the vcpu_id into the Aff0 field of the MPIDR.
+	 */
+	vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
+}
+
+/*
+ * Architected system registers.
+ * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
+ */
+static const struct sys_reg_desc sys_reg_descs[] = {
+	/* DC ISW */
+	{ Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
+	  access_dcsw },
+	/* DC CSW */
+	{ Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
+	  access_dcsw },
+	/* DC CISW */
+	{ Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
+	  access_dcsw },
+
+	/* MPIDR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
+	  NULL, reset_mpidr, MPIDR_EL1 },
+	/* SCTLR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
+	  NULL, reset_val, SCTLR_EL1, 0x00C50078 },
+	/* CPACR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
+	  NULL, reset_val, CPACR_EL1, 0 },
+	/* TTBR0_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
+	  NULL, reset_unknown, TTBR0_EL1 },
+	/* TTBR1_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
+	  NULL, reset_unknown, TTBR1_EL1 },
+	/* TCR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
+	  NULL, reset_val, TCR_EL1, 0 },
+
+	/* AFSR0_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
+	  NULL, reset_unknown, AFSR0_EL1 },
+	/* AFSR1_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
+	  NULL, reset_unknown, AFSR1_EL1 },
+	/* ESR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
+	  NULL, reset_unknown, ESR_EL1 },
+	/* FAR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
+	  NULL, reset_unknown, FAR_EL1 },
+
+	/* PMINTENSET_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
+	  pm_fake },
+	/* PMINTENCLR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
+	  pm_fake },
+
+	/* MAIR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
+	  NULL, reset_unknown, MAIR_EL1 },
+	/* AMAIR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
+	  NULL, reset_amair_el1, AMAIR_EL1 },
+
+	/* VBAR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
+	  NULL, reset_val, VBAR_EL1, 0 },
+	/* CONTEXTIDR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
+	  NULL, reset_val, CONTEXTIDR_EL1, 0 },
+	/* TPIDR_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
+	  NULL, reset_unknown, TPIDR_EL1 },
+
+	/* CNTKCTL_EL1 */
+	{ Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
+	  NULL, reset_val, CNTKCTL_EL1, 0},
+
+	/* CSSELR_EL1 */
+	{ Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
+	  NULL, reset_unknown, CSSELR_EL1 },
+
+	/* PMCR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
+	  pm_fake },
+	/* PMCNTENSET_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
+	  pm_fake },
+	/* PMCNTENCLR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
+	  pm_fake },
+	/* PMOVSCLR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
+	  pm_fake },
+	/* PMSWINC_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
+	  pm_fake },
+	/* PMSELR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
+	  pm_fake },
+	/* PMCEID0_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
+	  pm_fake },
+	/* PMCEID1_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
+	  pm_fake },
+	/* PMCCNTR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
+	  pm_fake },
+	/* PMXEVTYPER_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
+	  pm_fake },
+	/* PMXEVCNTR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
+	  pm_fake },
+	/* PMUSERENR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
+	  pm_fake },
+	/* PMOVSSET_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
+	  pm_fake },
+
+	/* TPIDR_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
+	  NULL, reset_unknown, TPIDR_EL0 },
+	/* TPIDRRO_EL0 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
+	  NULL, reset_unknown, TPIDRRO_EL0 },
+};
+
+/* Target specific emulation tables */
+static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
+
+void kvm_register_target_sys_reg_table(unsigned int target,
+				       struct kvm_sys_reg_target_table *table)
+{
+	target_tables[target] = table;
+}
+
+/* Get specific register table for this target. */
+static const struct sys_reg_desc *get_target_table(unsigned target, size_t *num)
+{
+	struct kvm_sys_reg_target_table *table;
+
+	table = target_tables[target];
+	*num = table->table64.num;
+	return table->table64.table;
+}
+
+static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
+					 const struct sys_reg_desc table[],
+					 unsigned int num)
+{
+	unsigned int i;
+
+	for (i = 0; i < num; i++) {
+		const struct sys_reg_desc *r = &table[i];
+
+		if (params->Op0 != r->Op0)
+			continue;
+		if (params->Op1 != r->Op1)
+			continue;
+		if (params->CRn != r->CRn)
+			continue;
+		if (params->CRm != r->CRm)
+			continue;
+		if (params->Op2 != r->Op2)
+			continue;
+
+		return r;
+	}
+	return NULL;
+}
+
+static int emulate_sys_reg(struct kvm_vcpu *vcpu,
+			   const struct sys_reg_params *params)
+{
+	size_t num;
+	const struct sys_reg_desc *table, *r;
+
+	table = get_target_table(vcpu->arch.target, &num);
+
+	/* Search target-specific then generic table. */
+	r = find_reg(params, table, num);
+	if (!r)
+		r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
+
+	if (likely(r)) {
+		/*
+		 * Not having an accessor means that we have
+		 * configured a trap that we don't know how to
+		 * handle. This certainly qualifies as a gross bug
+		 * that should be fixed right away.
+		 */
+		BUG_ON(!r->access);
+
+		if (likely(r->access(vcpu, params, r))) {
+			/* Skip instruction, since it was emulated */
+			kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+			return 1;
+		}
+		/* If access function fails, it should complain. */
+	} else {
+		kvm_err("Unsupported guest sys_reg access at: %lx\n",
+			*vcpu_pc(vcpu));
+		print_sys_reg_instr(params);
+	}
+	kvm_inject_undefined(vcpu);
+	return 1;
+}
+
+static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
+			      const struct sys_reg_desc *table, size_t num)
+{
+	unsigned long i;
+
+	for (i = 0; i < num; i++)
+		if (table[i].reset)
+			table[i].reset(vcpu, &table[i]);
+}
+
+/**
+ * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	struct sys_reg_params params;
+	unsigned long esr = kvm_vcpu_get_hsr(vcpu);
+
+	params.Op0 = (esr >> 20) & 3;
+	params.Op1 = (esr >> 14) & 0x7;
+	params.CRn = (esr >> 10) & 0xf;
+	params.CRm = (esr >> 1) & 0xf;
+	params.Op2 = (esr >> 17) & 0x7;
+	params.Rt = (esr >> 5) & 0x1f;
+	params.is_write = !(esr & 1);
+
+	return emulate_sys_reg(vcpu, &params);
+}
+
+/******************************************************************************
+ * Userspace API
+ *****************************************************************************/
+
+static bool index_to_params(u64 id, struct sys_reg_params *params)
+{
+	switch (id & KVM_REG_SIZE_MASK) {
+	case KVM_REG_SIZE_U64:
+		/* Any unused index bits means it's not valid. */
+		if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
+			      | KVM_REG_ARM_COPROC_MASK
+			      | KVM_REG_ARM64_SYSREG_OP0_MASK
+			      | KVM_REG_ARM64_SYSREG_OP1_MASK
+			      | KVM_REG_ARM64_SYSREG_CRN_MASK
+			      | KVM_REG_ARM64_SYSREG_CRM_MASK
+			      | KVM_REG_ARM64_SYSREG_OP2_MASK))
+			return false;
+		params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
+			       >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
+		params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
+			       >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
+		params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
+			       >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
+		params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
+			       >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
+		params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
+			       >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
+		return true;
+	default:
+		return false;
+	}
+}
+
+/* Decode an index value, and find the sys_reg_desc entry. */
+static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
+						    u64 id)
+{
+	size_t num;
+	const struct sys_reg_desc *table, *r;
+	struct sys_reg_params params;
+
+	/* We only do sys_reg for now. */
+	if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
+		return NULL;
+
+	if (!index_to_params(id, &params))
+		return NULL;
+
+	table = get_target_table(vcpu->arch.target, &num);
+	r = find_reg(&params, table, num);
+	if (!r)
+		r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
+
+	/* Not saved in the sys_reg array? */
+	if (r && !r->reg)
+		r = NULL;
+
+	return r;
+}
+
+/*
+ * These are the invariant sys_reg registers: we let the guest see the
+ * host versions of these, so they're part of the guest state.
+ *
+ * A future CPU may provide a mechanism to present different values to
+ * the guest, or a future kvm may trap them.
+ */
+
+#define FUNCTION_INVARIANT(reg)						\
+	static void get_##reg(struct kvm_vcpu *v,			\
+			      const struct sys_reg_desc *r)		\
+	{								\
+		u64 val;						\
+									\
+		asm volatile("mrs %0, " __stringify(reg) "\n"		\
+			     : "=r" (val));				\
+		((struct sys_reg_desc *)r)->val = val;			\
+	}
+
+FUNCTION_INVARIANT(midr_el1)
+FUNCTION_INVARIANT(ctr_el0)
+FUNCTION_INVARIANT(revidr_el1)
+FUNCTION_INVARIANT(id_pfr0_el1)
+FUNCTION_INVARIANT(id_pfr1_el1)
+FUNCTION_INVARIANT(id_dfr0_el1)
+FUNCTION_INVARIANT(id_afr0_el1)
+FUNCTION_INVARIANT(id_mmfr0_el1)
+FUNCTION_INVARIANT(id_mmfr1_el1)
+FUNCTION_INVARIANT(id_mmfr2_el1)
+FUNCTION_INVARIANT(id_mmfr3_el1)
+FUNCTION_INVARIANT(id_isar0_el1)
+FUNCTION_INVARIANT(id_isar1_el1)
+FUNCTION_INVARIANT(id_isar2_el1)
+FUNCTION_INVARIANT(id_isar3_el1)
+FUNCTION_INVARIANT(id_isar4_el1)
+FUNCTION_INVARIANT(id_isar5_el1)
+FUNCTION_INVARIANT(clidr_el1)
+FUNCTION_INVARIANT(aidr_el1)
+
+/* ->val is filled in by kvm_sys_reg_table_init() */
+static struct sys_reg_desc invariant_sys_regs[] = {
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
+	  NULL, get_midr_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
+	  NULL, get_revidr_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
+	  NULL, get_id_pfr0_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
+	  NULL, get_id_pfr1_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
+	  NULL, get_id_dfr0_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
+	  NULL, get_id_afr0_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
+	  NULL, get_id_mmfr0_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
+	  NULL, get_id_mmfr1_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
+	  NULL, get_id_mmfr2_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
+	  NULL, get_id_mmfr3_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
+	  NULL, get_id_isar0_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
+	  NULL, get_id_isar1_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
+	  NULL, get_id_isar2_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
+	  NULL, get_id_isar3_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
+	  NULL, get_id_isar4_el1 },
+	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
+	  NULL, get_id_isar5_el1 },
+	{ Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
+	  NULL, get_clidr_el1 },
+	{ Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
+	  NULL, get_aidr_el1 },
+	{ Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
+	  NULL, get_ctr_el0 },
+};
+
+static int reg_from_user(void *val, const void __user *uaddr, u64 id)
+{
+	/* This Just Works because we are little endian. */
+	if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
+		return -EFAULT;
+	return 0;
+}
+
+static int reg_to_user(void __user *uaddr, const void *val, u64 id)
+{
+	/* This Just Works because we are little endian. */
+	if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
+		return -EFAULT;
+	return 0;
+}
+
+static int get_invariant_sys_reg(u64 id, void __user *uaddr)
+{
+	struct sys_reg_params params;
+	const struct sys_reg_desc *r;
+
+	if (!index_to_params(id, &params))
+		return -ENOENT;
+
+	r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
+	if (!r)
+		return -ENOENT;
+
+	return reg_to_user(uaddr, &r->val, id);
+}
+
+static int set_invariant_sys_reg(u64 id, void __user *uaddr)
+{
+	struct sys_reg_params params;
+	const struct sys_reg_desc *r;
+	int err;
+	u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
+
+	if (!index_to_params(id, &params))
+		return -ENOENT;
+	r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
+	if (!r)
+		return -ENOENT;
+
+	err = reg_from_user(&val, uaddr, id);
+	if (err)
+		return err;
+
+	/* This is what we mean by invariant: you can't change it. */
+	if (r->val != val)
+		return -EINVAL;
+
+	return 0;
+}
+
+static bool is_valid_cache(u32 val)
+{
+	u32 level, ctype;
+
+	if (val >= CSSELR_MAX)
+		return -ENOENT;
+
+	/* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
+	level = (val >> 1);
+	ctype = (cache_levels >> (level * 3)) & 7;
+
+	switch (ctype) {
+	case 0: /* No cache */
+		return false;
+	case 1: /* Instruction cache only */
+		return (val & 1);
+	case 2: /* Data cache only */
+	case 4: /* Unified cache */
+		return !(val & 1);
+	case 3: /* Separate instruction and data caches */
+		return true;
+	default: /* Reserved: we can't know instruction or data. */
+		return false;
+	}
+}
+
+static int demux_c15_get(u64 id, void __user *uaddr)
+{
+	u32 val;
+	u32 __user *uval = uaddr;
+
+	/* Fail if we have unknown bits set. */
+	if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+		   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+		return -ENOENT;
+
+	switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+	case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+		if (KVM_REG_SIZE(id) != 4)
+			return -ENOENT;
+		val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+			>> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+		if (!is_valid_cache(val))
+			return -ENOENT;
+
+		return put_user(get_ccsidr(val), uval);
+	default:
+		return -ENOENT;
+	}
+}
+
+static int demux_c15_set(u64 id, void __user *uaddr)
+{
+	u32 val, newval;
+	u32 __user *uval = uaddr;
+
+	/* Fail if we have unknown bits set. */
+	if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+		   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+		return -ENOENT;
+
+	switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+	case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+		if (KVM_REG_SIZE(id) != 4)
+			return -ENOENT;
+		val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+			>> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+		if (!is_valid_cache(val))
+			return -ENOENT;
+
+		if (get_user(newval, uval))
+			return -EFAULT;
+
+		/* This is also invariant: you can't change it. */
+		if (newval != get_ccsidr(val))
+			return -EINVAL;
+		return 0;
+	default:
+		return -ENOENT;
+	}
+}
+
+int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	const struct sys_reg_desc *r;
+	void __user *uaddr = (void __user *)(unsigned long)reg->addr;
+
+	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+		return demux_c15_get(reg->id, uaddr);
+
+	if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
+		return -ENOENT;
+
+	r = index_to_sys_reg_desc(vcpu, reg->id);
+	if (!r)
+		return get_invariant_sys_reg(reg->id, uaddr);
+
+	return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
+}
+
+int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	const struct sys_reg_desc *r;
+	void __user *uaddr = (void __user *)(unsigned long)reg->addr;
+
+	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+		return demux_c15_set(reg->id, uaddr);
+
+	if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
+		return -ENOENT;
+
+	r = index_to_sys_reg_desc(vcpu, reg->id);
+	if (!r)
+		return set_invariant_sys_reg(reg->id, uaddr);
+
+	return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
+}
+
+static unsigned int num_demux_regs(void)
+{
+	unsigned int i, count = 0;
+
+	for (i = 0; i < CSSELR_MAX; i++)
+		if (is_valid_cache(i))
+			count++;
+
+	return count;
+}
+
+static int write_demux_regids(u64 __user *uindices)
+{
+	u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
+	unsigned int i;
+
+	val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
+	for (i = 0; i < CSSELR_MAX; i++) {
+		if (!is_valid_cache(i))
+			continue;
+		if (put_user(val | i, uindices))
+			return -EFAULT;
+		uindices++;
+	}
+	return 0;
+}
+
+static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
+{
+	return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
+		KVM_REG_ARM64_SYSREG |
+		(reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
+		(reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
+		(reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
+		(reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
+		(reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
+}
+
+static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
+{
+	if (!*uind)
+		return true;
+
+	if (put_user(sys_reg_to_index(reg), *uind))
+		return false;
+
+	(*uind)++;
+	return true;
+}
+
+/* Assumed ordered tables, see kvm_sys_reg_table_init. */
+static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
+{
+	const struct sys_reg_desc *i1, *i2, *end1, *end2;
+	unsigned int total = 0;
+	size_t num;
+
+	/* We check for duplicates here, to allow arch-specific overrides. */
+	i1 = get_target_table(vcpu->arch.target, &num);
+	end1 = i1 + num;
+	i2 = sys_reg_descs;
+	end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
+
+	BUG_ON(i1 == end1 || i2 == end2);
+
+	/* Walk carefully, as both tables may refer to the same register. */
+	while (i1 || i2) {
+		int cmp = cmp_sys_reg(i1, i2);
+		/* target-specific overrides generic entry. */
+		if (cmp <= 0) {
+			/* Ignore registers we trap but don't save. */
+			if (i1->reg) {
+				if (!copy_reg_to_user(i1, &uind))
+					return -EFAULT;
+				total++;
+			}
+		} else {
+			/* Ignore registers we trap but don't save. */
+			if (i2->reg) {
+				if (!copy_reg_to_user(i2, &uind))
+					return -EFAULT;
+				total++;
+			}
+		}
+
+		if (cmp <= 0 && ++i1 == end1)
+			i1 = NULL;
+		if (cmp >= 0 && ++i2 == end2)
+			i2 = NULL;
+	}
+	return total;
+}
+
+unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
+{
+	return ARRAY_SIZE(invariant_sys_regs)
+		+ num_demux_regs()
+		+ walk_sys_regs(vcpu, (u64 __user *)NULL);
+}
+
+int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+	unsigned int i;
+	int err;
+
+	/* Then give them all the invariant registers' indices. */
+	for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
+		if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
+			return -EFAULT;
+		uindices++;
+	}
+
+	err = walk_sys_regs(vcpu, uindices);
+	if (err < 0)
+		return err;
+	uindices += err;
+
+	return write_demux_regids(uindices);
+}
+
+void kvm_sys_reg_table_init(void)
+{
+	unsigned int i;
+	struct sys_reg_desc clidr;
+
+	/* Make sure tables are unique and in order. */
+	for (i = 1; i < ARRAY_SIZE(sys_reg_descs); i++)
+		BUG_ON(cmp_sys_reg(&sys_reg_descs[i-1], &sys_reg_descs[i]) >= 0);
+
+	/* We abuse the reset function to overwrite the table itself. */
+	for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
+		invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
+
+	/*
+	 * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
+	 *
+	 *   If software reads the Cache Type fields from Ctype1
+	 *   upwards, once it has seen a value of 0b000, no caches
+	 *   exist at further-out levels of the hierarchy. So, for
+	 *   example, if Ctype3 is the first Cache Type field with a
+	 *   value of 0b000, the values of Ctype4 to Ctype7 must be
+	 *   ignored.
+	 */
+	get_clidr_el1(NULL, &clidr); /* Ugly... */
+	cache_levels = clidr.val;
+	for (i = 0; i < 7; i++)
+		if (((cache_levels >> (i*3)) & 7) == 0)
+			break;
+	/* Clear all higher bits. */
+	cache_levels &= (1 << (i*3))-1;
+}
+
+/**
+ * kvm_reset_sys_regs - sets system registers to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on the
+ * virtual CPU struct to their architecturally defined reset values.
+ */
+void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
+{
+	size_t num;
+	const struct sys_reg_desc *table;
+
+	/* Catch someone adding a register without putting in reset entry. */
+	memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
+
+	/* Generic chip reset first (so target could override). */
+	reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
+
+	table = get_target_table(vcpu->arch.target, &num);
+	reset_sys_reg_descs(vcpu, table, num);
+
+	for (num = 1; num < NR_SYS_REGS; num++)
+		if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
+			panic("Didn't reset vcpu_sys_reg(%zi)", num);
+}
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
new file mode 100644
index 0000000..d50d372
--- /dev/null
+++ b/arch/arm64/kvm/sys_regs.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/kvm/coproc.h
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
+#define __ARM64_KVM_SYS_REGS_LOCAL_H__
+
+struct sys_reg_params {
+	u8	Op0;
+	u8	Op1;
+	u8	CRn;
+	u8	CRm;
+	u8	Op2;
+	u8	Rt;
+	bool	is_write;
+};
+
+struct sys_reg_desc {
+	/* MRS/MSR instruction which accesses it. */
+	u8	Op0;
+	u8	Op1;
+	u8	CRn;
+	u8	CRm;
+	u8	Op2;
+
+	/* Trapped access from guest, if non-NULL. */
+	bool (*access)(struct kvm_vcpu *,
+		       const struct sys_reg_params *,
+		       const struct sys_reg_desc *);
+
+	/* Initialization for vcpu. */
+	void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
+
+	/* Index into sys_reg[], or 0 if we don't need to save it. */
+	int reg;
+
+	/* Value (usually reset value) */
+	u64 val;
+};
+
+static inline void print_sys_reg_instr(const struct sys_reg_params *p)
+{
+	/* Look, we even formatted it for you to paste into the table! */
+	kvm_pr_unimpl(" { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
+		      p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
+}
+
+static inline bool ignore_write(struct kvm_vcpu *vcpu,
+				const struct sys_reg_params *p)
+{
+	return true;
+}
+
+static inline bool read_zero(struct kvm_vcpu *vcpu,
+			     const struct sys_reg_params *p)
+{
+	*vcpu_reg(vcpu, p->Rt) = 0;
+	return true;
+}
+
+static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
+				      const struct sys_reg_params *params)
+{
+	kvm_debug("sys_reg write to read-only register at: %lx\n",
+		  *vcpu_pc(vcpu));
+	print_sys_reg_instr(params);
+	return false;
+}
+
+static inline bool read_from_write_only(struct kvm_vcpu *vcpu,
+					const struct sys_reg_params *params)
+{
+	kvm_debug("sys_reg read to write-only register at: %lx\n",
+		  *vcpu_pc(vcpu));
+	print_sys_reg_instr(params);
+	return false;
+}
+
+/* Reset functions */
+static inline void reset_unknown(struct kvm_vcpu *vcpu,
+				 const struct sys_reg_desc *r)
+{
+	BUG_ON(!r->reg);
+	BUG_ON(r->reg >= NR_SYS_REGS);
+	vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
+}
+
+static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	BUG_ON(!r->reg);
+	BUG_ON(r->reg >= NR_SYS_REGS);
+	vcpu_sys_reg(vcpu, r->reg) = r->val;
+}
+
+static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
+			      const struct sys_reg_desc *i2)
+{
+	BUG_ON(i1 == i2);
+	if (!i1)
+		return 1;
+	else if (!i2)
+		return -1;
+	if (i1->Op0 != i2->Op0)
+		return i1->Op0 - i2->Op0;
+	if (i1->Op1 != i2->Op1)
+		return i1->Op1 - i2->Op1;
+	if (i1->CRn != i2->CRn)
+		return i1->CRn - i2->CRn;
+	if (i1->CRm != i2->CRm)
+		return i1->CRm - i2->CRm;
+	return i1->Op2 - i2->Op2;
+}
+
+
+#define Op0(_x) 	.Op0 = _x
+#define Op1(_x) 	.Op1 = _x
+#define CRn(_x)		.CRn = _x
+#define CRm(_x) 	.CRm = _x
+#define Op2(_x) 	.Op2 = _x
+
+#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index a5c86fc..2d1bcb8 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
 #define KVM_REG_IA64		0x3000000000000000ULL
 #define KVM_REG_ARM		0x4000000000000000ULL
 #define KVM_REG_S390		0x5000000000000000ULL
+#define KVM_REG_ARM64		0x6000000000000000ULL
 
 #define KVM_REG_SIZE_SHIFT	52
 #define KVM_REG_SIZE_MASK	0x00f0000000000000ULL
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:14:00 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:14:00 +0100
Subject: [PATCH v4 32/32] arm64: KVM: document kernel object mappings in HYP
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-33-git-send-email-marc.zyngier@arm.com>

HYP mode has access to some of the kernel pages. Document the
memory mapping and the offset between kernel VA and HYP VA.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 Documentation/arm64/memory.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index 5f583af..78a37712 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -73,3 +73,10 @@ Translation table lookup with 64KB pages:
  |                 |    +--------------------------> [41:29] L2 index (only 38:29 used)
  |                 +-------------------------------> [47:42] L1 index (not used)
  +-------------------------------------------------> [63] TTBR0/1
+
+When using KVM, the hypervisor maps kernel pages in EL2, at a fixed
+offset from the kernel VA (top 24bits of the kernel VA set to zero):
+
+Start			End			Size		Use
+-----------------------------------------------------------------------
+0000004000000000	0000007fffffffff	 256GB		kernel objects mapped in HYP
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:57 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:57 +0100
Subject: [PATCH v4 29/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-30-git-send-email-marc.zyngier@arm.com>

Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
and providing sensible defaults out of reset state.

This feature is of course conditioned by the presence of 32bit
capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
capability.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_host.h |  2 +-
 arch/arm64/include/uapi/asm/kvm.h |  1 +
 arch/arm64/kvm/guest.c            |  6 ++++++
 arch/arm64/kvm/reset.c            | 25 ++++++++++++++++++++++++-
 include/uapi/linux/kvm.h          |  1 +
 5 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 3f5830b..644d739 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -34,7 +34,7 @@
 #include <kvm/arm_vgic.h>
 #include <kvm/arm_arch_timer.h>
 
-#define KVM_VCPU_MAX_FEATURES 1
+#define KVM_VCPU_MAX_FEATURES 2
 
 /* We don't currently support large pages. */
 #define KVM_HPAGE_GFN_SHIFT(x)	0
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 5b1110c..5031f42 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -75,6 +75,7 @@ struct kvm_regs {
 #define KVM_VGIC_V2_CPU_SIZE		0x2000
 
 #define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */
+#define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
 
 struct kvm_vcpu_init {
 	__u32 target;
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index c8d48b2..e0d6b2c 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -93,6 +93,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 	if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
 		u32 mode = (*(u32 *)valp) & COMPAT_PSR_MODE_MASK;
 		switch (mode) {
+		case COMPAT_PSR_MODE_USR:
+		case COMPAT_PSR_MODE_FIQ:
+		case COMPAT_PSR_MODE_IRQ:
+		case COMPAT_PSR_MODE_SVC:
+		case COMPAT_PSR_MODE_ABT:
+		case COMPAT_PSR_MODE_UND:
 		case PSR_MODE_EL0t:
 		case PSR_MODE_EL1t:
 		case PSR_MODE_EL1h:
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 84112e0..c2cb9cc 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -36,11 +36,27 @@ static struct kvm_regs default_regs_reset = {
 			PSR_F_BIT | PSR_D_BIT),
 };
 
+static struct kvm_regs default_regs_reset32 = {
+	.regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
+			COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
+};
+
+static bool cpu_has_32bit_el1(void)
+{
+	u64 pfr0;
+
+	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
+	return !!(pfr0 & 0x20);
+}
+
 int kvm_arch_dev_ioctl_check_extension(long ext)
 {
 	int r;
 
 	switch (ext) {
+	case KVM_CAP_ARM_EL1_32BIT:
+		r = cpu_has_32bit_el1();
+		break;
 	default:
 		r = 0;
 	}
@@ -63,7 +79,14 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 
 	switch (vcpu->arch.target) {
 	default:
-		cpu_reset = &default_regs_reset;
+		if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
+			if (!cpu_has_32bit_el1())
+				return -EINVAL;
+			cpu_reset = &default_regs_reset32;
+			vcpu->arch.hcr_el2 &= ~HCR_RW;
+		} else {
+			cpu_reset = &default_regs_reset;
+		}
 		break;
 	}
 
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 2d1bcb8..aac2764 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -666,6 +666,7 @@ struct kvm_ppc_smmu_info {
 #define KVM_CAP_IRQ_MPIC 90
 #define KVM_CAP_PPC_RTAS 91
 #define KVM_CAP_IRQ_XICS 92
+#define KVM_CAP_ARM_EL1_32BIT 93
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:59 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:59 +0100
Subject: [PATCH v4 31/32] arm64: KVM: MAINTAINERS update
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-32-git-send-email-marc.zyngier@arm.com>

Elect myself as the KVM/arm64 maintainer.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7782b..d7e7bbb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4700,6 +4700,15 @@ F:	arch/arm/include/uapi/asm/kvm*
 F:	arch/arm/include/asm/kvm*
 F:	arch/arm/kvm/
 
+KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)
+M:	Marc Zyngier <marc.zyngier at arm.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+L:	kvmarm at lists.cs.columbia.edu
+S:	Maintained
+F:	arch/arm64/include/uapi/asm/kvm*
+F:	arch/arm64/include/asm/kvm*
+F:	arch/arm64/kvm/
+
 KEXEC
 M:	Eric Biederman <ebiederm at xmission.com>
 W:	http://kernel.org/pub/linux/utils/kernel/kexec/
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:55 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:55 +0100
Subject: [PATCH v4 27/32] arm64: KVM: 32bit specific register world switch
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-28-git-send-email-marc.zyngier@arm.com>

Allow registers specific to 32bit guests to be saved/restored
during the world switch.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/hyp.S | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
index 926dc7e..e175f84 100644
--- a/arch/arm64/kvm/hyp.S
+++ b/arch/arm64/kvm/hyp.S
@@ -266,6 +266,74 @@ __kvm_hyp_code_start:
 	msr	cntkctl_el1,	x23
 .endm
 
+.macro skip_32bit_state tmp, target
+	// Skip 32bit state if not needed
+	mrs	\tmp, hcr_el2
+	tbnz	\tmp, #HCR_RW_SHIFT, \target
+.endm
+
+.macro skip_tee_state tmp, target
+	// Skip ThumbEE state if not needed
+	mrs	\tmp, id_pfr0_el1
+	tbz	\tmp, #12, \target
+.endm
+
+.macro save_guest_32bit_state
+	skip_32bit_state x3, 1f
+
+	add	x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
+	mrs	x4, spsr_abt
+	mrs	x5, spsr_und
+	mrs	x6, spsr_irq
+	mrs	x7, spsr_fiq
+	stp	x4, x5, [x3]
+	stp	x6, x7, [x3, #16]
+
+	add	x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
+	mrs	x4, dacr32_el2
+	mrs	x5, ifsr32_el2
+	mrs	x6, fpexc32_el2
+	mrs	x7, dbgvcr32_el2
+	stp	x4, x5, [x3]
+	stp	x6, x7, [x3, #16]
+
+	skip_tee_state x8, 1f
+
+	add	x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
+	mrs	x4, teecr32_el1
+	mrs	x5, teehbr32_el1
+	stp	x4, x5, [x3]
+1:
+.endm
+
+.macro restore_guest_32bit_state
+	skip_32bit_state x3, 1f
+
+	add	x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
+	ldp	x4, x5, [x3]
+	ldp	x6, x7, [x3, #16]
+	msr	spsr_abt, x4
+	msr	spsr_und, x5
+	msr	spsr_irq, x6
+	msr	spsr_fiq, x7
+
+	add	x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
+	ldp	x4, x5, [x3]
+	ldp	x6, x7, [x3, #16]
+	msr	dacr32_el2, x4
+	msr	ifsr32_el2, x5
+	msr	fpexc32_el2, x6
+	msr	dbgvcr32_el2, x7
+
+	skip_tee_state x8, 1f
+
+	add	x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
+	ldp	x4, x5, [x3]
+	msr	teecr32_el1, x4
+	msr	teehbr32_el1, x5
+1:
+.endm
+
 .macro activate_traps
 	ldr	x2, [x0, #VCPU_IRQ_LINES]
 	ldr	x1, [x0, #VCPU_HCR_EL2]
@@ -494,6 +562,7 @@ ENTRY(__kvm_vcpu_run)
 
 	bl __restore_sysregs
 	bl __restore_fpsimd
+	restore_guest_32bit_state
 	restore_guest_regs
 
 	// That's it, no more messing around.
@@ -510,6 +579,7 @@ __kvm_vcpu_return:
 	save_guest_regs
 	bl __save_fpsimd
 	bl __save_sysregs
+	save_guest_32bit_state
 
 	save_timer_state
 	save_vgic_state
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:58 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:58 +0100
Subject: [PATCH v4 30/32] arm64: KVM: userspace API documentation
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-31-git-send-email-marc.zyngier@arm.com>

Unsurprisingly, the arm64 userspace API is extremely similar to
the 32bit one, the only significant difference being the ONE_REG
register mapping.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 Documentation/virtual/kvm/api.txt | 58 ++++++++++++++++++++++++++-------------
 1 file changed, 39 insertions(+), 19 deletions(-)

diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 5f91eda..9bfadeb 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -280,7 +280,7 @@ kvm_run' (see below).
 4.11 KVM_GET_REGS
 
 Capability: basic
-Architectures: all except ARM
+Architectures: all except ARM, arm64
 Type: vcpu ioctl
 Parameters: struct kvm_regs (out)
 Returns: 0 on success, -1 on error
@@ -301,7 +301,7 @@ struct kvm_regs {
 4.12 KVM_SET_REGS
 
 Capability: basic
-Architectures: all except ARM
+Architectures: all except ARM, arm64
 Type: vcpu ioctl
 Parameters: struct kvm_regs (in)
 Returns: 0 on success, -1 on error
@@ -587,7 +587,7 @@ struct kvm_fpu {
 4.24 KVM_CREATE_IRQCHIP
 
 Capability: KVM_CAP_IRQCHIP
-Architectures: x86, ia64, ARM
+Architectures: x86, ia64, ARM, arm64
 Type: vm ioctl
 Parameters: none
 Returns: 0 on success, -1 on error
@@ -595,14 +595,14 @@ Returns: 0 on success, -1 on error
 Creates an interrupt controller model in the kernel.  On x86, creates a virtual
 ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a
 local APIC.  IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23
-only go to the IOAPIC.  On ia64, a IOSAPIC is created. On ARM, a GIC is
+only go to the IOAPIC.  On ia64, a IOSAPIC is created. On ARM/arm64, a GIC is
 created.
 
 
 4.25 KVM_IRQ_LINE
 
 Capability: KVM_CAP_IRQCHIP
-Architectures: x86, ia64, arm
+Architectures: x86, ia64, arm, arm64
 Type: vm ioctl
 Parameters: struct kvm_irq_level
 Returns: 0 on success, -1 on error
@@ -612,9 +612,10 @@ On some architectures it is required that an interrupt controller model has
 been previously created with KVM_CREATE_IRQCHIP.  Note that edge-triggered
 interrupts require the level to be set to 1 and then back to 0.
 
-ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip
-(GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for
-specific cpus.  The irq field is interpreted like this:
+ARM/arm64 can signal an interrupt either at the CPU level, or at the
+in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to
+use PPIs designated for specific cpus.  The irq field is interpreted
+like this:
 
  ?bits:  | 31 ... 24 | 23  ... 16 | 15    ...    0 |
   field: | irq_type  | vcpu_index |     irq_id     |
@@ -1831,6 +1832,22 @@ ARM 32-bit VFP control registers have the following id bit patterns:
 ARM 64-bit FP registers have the following id bit patterns:
   0x4030 0000 0012 0 <regno:12>
 
+
+arm64 registers are mapped using the lower 32 bits. The upper 16 of
+that is the register group type, or coprocessor number:
+
+arm64 core/FP-SIMD registers have the following id bit patterns. Note
+that the size of the access is variable, as the kvm_regs structure
+contains elements ranging from 32 to 128 bits. The index is a 32bit
+value in the kvm_regs structure seen as a 32bit array.
+  0x60x0 0000 0010 <index into the kvm_regs struct:16>
+
+arm64 CCSIDR registers are demultiplexed by CSSELR value:
+  0x6020 0000 0011 00 <csselr:8>
+
+arm64 system registers have the following id bit patterns:
+  0x6030 0000 0013 <op0:2> <op1:3> <crn:4> <crm:4> <op2:3>
+
 4.69 KVM_GET_ONE_REG
 
 Capability: KVM_CAP_ONE_REG
@@ -2264,7 +2281,7 @@ current state.  "addr" is ignored.
 4.77 KVM_ARM_VCPU_INIT
 
 Capability: basic
-Architectures: arm
+Architectures: arm, arm64
 Type: vcpu ioctl
 Parameters: struct struct kvm_vcpu_init (in)
 Returns: 0 on success; -1 on error
@@ -2283,12 +2300,14 @@ should be created before this ioctl is invoked.
 Possible features:
 	- KVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state.
 	  Depends on KVM_CAP_ARM_PSCI.
+	- KVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode.
+	  Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only).
 
 
 4.78 KVM_GET_REG_LIST
 
 Capability: basic
-Architectures: arm
+Architectures: arm, arm64
 Type: vcpu ioctl
 Parameters: struct kvm_reg_list (in/out)
 Returns: 0 on success; -1 on error
@@ -2308,7 +2327,7 @@ KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
 4.80 KVM_ARM_SET_DEVICE_ADDR
 
 Capability: KVM_CAP_ARM_SET_DEVICE_ADDR
-Architectures: arm
+Architectures: arm, arm64
 Type: vm ioctl
 Parameters: struct kvm_arm_device_address (in)
 Returns: 0 on success, -1 on error
@@ -2329,18 +2348,19 @@ can access emulated or directly exposed devices, which the host kernel needs
 to know about. The id field is an architecture specific identifier for a
 specific device.
 
-ARM divides the id field into two parts, a device id and an address type id
-specific to the individual device.
+ARM/arm64 divides the id field into two parts, a device id and an
+address type id specific to the individual device.
 
  ?bits:  | 63        ...       32 | 31    ...    16 | 15    ...    0 |
   field: |        0x00000000      |     device id   |  addr type id  |
 
-ARM currently only require this when using the in-kernel GIC support for the
-hardware VGIC features, using KVM_ARM_DEVICE_VGIC_V2 as the device id.  When
-setting the base address for the guest's mapping of the VGIC virtual CPU
-and distributor interface, the ioctl must be called after calling
-KVM_CREATE_IRQCHIP, but before calling KVM_RUN on any of the VCPUs.  Calling
-this ioctl twice for any of the base addresses will return -EEXIST.
+ARM/arm64 currently only require this when using the in-kernel GIC
+support for the hardware VGIC features, using KVM_ARM_DEVICE_VGIC_V2
+as the device id.  When setting the base address for the guest's
+mapping of the VGIC virtual CPU and distributor interface, the ioctl
+must be called after calling KVM_CREATE_IRQCHIP, but before calling
+KVM_RUN on any of the VCPUs.  Calling this ioctl twice for any of the
+base addresses will return -EEXIST.
 
 4.82 KVM_PPC_RTAS_DEFINE_TOKEN
 
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:47 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:47 +0100
Subject: [PATCH v4 19/32] arm64: KVM: Plug the arch timer
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-20-git-send-email-marc.zyngier@arm.com>

Add support for the in-kernel timer emulation.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/hyp.S      | 56 +++++++++++++++++++++++++++++++++++++++++++++++
 virt/kvm/arm/arch_timer.c |  1 +
 2 files changed, 57 insertions(+)

diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
index 06a69af4..926dc7e 100644
--- a/arch/arm64/kvm/hyp.S
+++ b/arch/arm64/kvm/hyp.S
@@ -390,6 +390,60 @@ __kvm_hyp_code_start:
 2:
 .endm
 
+.macro save_timer_state
+	// x0: vcpu pointer
+	ldr	x2, [x0, #VCPU_KVM]
+	kern_hyp_va x2
+	ldr	w3, [x2, #KVM_TIMER_ENABLED]
+	cbz	w3, 1f
+
+	mrs	x3, cntv_ctl_el0
+	and	x3, x3, #3
+	str	w3, [x0, #VCPU_TIMER_CNTV_CTL]
+	bic	x3, x3, #1		// Clear Enable
+	msr	cntv_ctl_el0, x3
+
+	isb
+
+	mrs	x3, cntv_cval_el0
+	str	x3, [x0, #VCPU_TIMER_CNTV_CVAL]
+
+1:
+	// Allow physical timer/counter access for the host
+	mrs	x2, cnthctl_el2
+	orr	x2, x2, #3
+	msr	cnthctl_el2, x2
+
+	// Clear cntvoff for the host
+	msr	cntvoff_el2, xzr
+.endm
+
+.macro restore_timer_state
+	// x0: vcpu pointer
+	// Disallow physical timer access for the guest
+	// Physical counter access is allowed
+	mrs	x2, cnthctl_el2
+	orr	x2, x2, #1
+	bic	x2, x2, #2
+	msr	cnthctl_el2, x2
+
+	ldr	x2, [x0, #VCPU_KVM]
+	kern_hyp_va x2
+	ldr	w3, [x2, #KVM_TIMER_ENABLED]
+	cbz	w3, 1f
+
+	ldr	x3, [x2, #KVM_TIMER_CNTVOFF]
+	msr	cntvoff_el2, x3
+	ldr	x2, [x0, #VCPU_TIMER_CNTV_CVAL]
+	msr	cntv_cval_el0, x2
+	isb
+
+	ldr	w2, [x0, #VCPU_TIMER_CNTV_CTL]
+	and	x2, x2, #3
+	msr	cntv_ctl_el0, x2
+1:
+.endm
+
 __save_sysregs:
 	save_sysregs
 	ret
@@ -433,6 +487,7 @@ ENTRY(__kvm_vcpu_run)
 	activate_vm
 
 	restore_vgic_state
+	restore_timer_state
 
 	// Guest context
 	add	x2, x0, #VCPU_CONTEXT
@@ -456,6 +511,7 @@ __kvm_vcpu_return:
 	bl __save_fpsimd
 	bl __save_sysregs
 
+	save_timer_state
 	save_vgic_state
 
 	deactivate_traps
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 2d00b29..6f485ea 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -195,6 +195,7 @@ static struct notifier_block kvm_timer_cpu_nb = {
 
 static const struct of_device_id arch_timer_of_match[] = {
 	{ .compatible	= "arm,armv7-timer",	},
+	{ .compatible	= "arm,armv8-timer",	},
 	{},
 };
 
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:50 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:50 +0100
Subject: [PATCH v4 22/32] arm64: KVM: define 32bit specific registers
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-23-git-send-email-marc.zyngier@arm.com>

Define the 32bit specific registers (SPSRs, cp15...).

Most CPU registers are directly mapped to a 64bit register
(r0->x0...). Only the SPSRs have separate registers.

cp15 registers are also mapped into their 64bit counterpart in most
cases.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_asm.h  | 38 +++++++++++++++++++++++++++++++++++++-
 arch/arm64/include/asm/kvm_host.h |  5 ++++-
 arch/arm64/include/uapi/asm/kvm.h |  7 ++++++-
 3 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 591ac21..c92de41 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -42,7 +42,43 @@
 #define	TPIDR_EL1	18	/* Thread ID, Privileged */
 #define	AMAIR_EL1	19	/* Aux Memory Attribute Indirection Register */
 #define	CNTKCTL_EL1	20	/* Timer Control Register (EL1) */
-#define	NR_SYS_REGS	21
+/* 32bit specific registers. Keep them at the end of the range */
+#define	DACR32_EL2	21	/* Domain Access Control Register */
+#define	IFSR32_EL2	22	/* Instruction Fault Status Register */
+#define	FPEXC32_EL2	23	/* Floating-Point Exception Control Register */
+#define	DBGVCR32_EL2	24	/* Debug Vector Catch Register */
+#define	TEECR32_EL1	25	/* ThumbEE Configuration Register */
+#define	TEEHBR32_EL1	26	/* ThumbEE Handler Base Register */
+#define	NR_SYS_REGS	27
+
+/* 32bit mapping */
+#define c0_MPIDR	(MPIDR_EL1 * 2)	/* MultiProcessor ID Register */
+#define c0_CSSELR	(CSSELR_EL1 * 2)/* Cache Size Selection Register */
+#define c1_SCTLR	(SCTLR_EL1 * 2)	/* System Control Register */
+#define c1_ACTLR	(ACTLR_EL1 * 2)	/* Auxiliary Control Register */
+#define c1_CPACR	(CPACR_EL1 * 2)	/* Coprocessor Access Control */
+#define c2_TTBR0	(TTBR0_EL1 * 2)	/* Translation Table Base Register 0 */
+#define c2_TTBR0_high	(c2_TTBR0 + 1)	/* TTBR0 top 32 bits */
+#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */
+#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */
+#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */
+#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */
+#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */
+#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */
+#define c5_ADFSR	(AFSR0_EL1 * 2)	/* Auxiliary Data Fault Status R */
+#define c5_AIFSR	(AFSR1_EL1 * 2)	/* Auxiliary Instr Fault Status R */
+#define c6_DFAR		(FAR_EL1 * 2)	/* Data Fault Address Register */
+#define c6_IFAR		(c6_DFAR + 1)	/* Instruction Fault Address Register */
+#define c10_PRRR	(MAIR_EL1 * 2)	/* Primary Region Remap Register */
+#define c10_NMRR	(c10_PRRR + 1)	/* Normal Memory Remap Register */
+#define c12_VBAR	(VBAR_EL1 * 2)	/* Vector Base Address Register */
+#define c13_CID		(CONTEXTIDR_EL1 * 2)	/* Context ID Register */
+#define c13_TID_URW	(TPIDR_EL0 * 2)	/* Thread ID, User R/W */
+#define c13_TID_URO	(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
+#define c13_TID_PRIV	(TPIDR_EL1 * 2)	/* Thread ID, Privileged */
+#define c10_AMAIR	(AMAIR_EL1 * 2)	/* Aux Memory Attr Indirection Reg */
+#define c14_CNTKCTL	(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+#define NR_CP15_REGS	(NR_SYS_REGS * 2)
 
 #define ARM_EXCEPTION_IRQ	  0
 #define ARM_EXCEPTION_TRAP	  1
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 2fdeb32..3f5830b 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -84,7 +84,10 @@ struct kvm_vcpu_fault_info {
 
 struct kvm_cpu_context {
 	struct kvm_regs	gp_regs;
-	u64 sys_regs[NR_SYS_REGS];
+	union {
+		u64 sys_regs[NR_SYS_REGS];
+		u32 cp15[NR_CP15_REGS];
+	};
 };
 
 typedef struct kvm_cpu_context kvm_cpu_context_t;
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index fb60f90..5b1110c 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -23,7 +23,12 @@
 #define __ARM_KVM_H__
 
 #define KVM_SPSR_EL1	0
-#define KVM_NR_SPSR	1
+#define KVM_SPSR_SVC	KVM_SPSR_EL1
+#define KVM_SPSR_ABT	1
+#define KVM_SPSR_UND	2
+#define KVM_SPSR_IRQ	3
+#define KVM_SPSR_FIQ	4
+#define KVM_NR_SPSR	5
 
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:52 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:52 +0100
Subject: [PATCH v4 24/32] arm64: KVM: 32bit conditional execution emulation
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-25-git-send-email-marc.zyngier@arm.com>

As conditional instructions can trap on AArch32, add the thinest
possible emulation layer to keep 32bit guests happy.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_emulate.h |  13 ++-
 arch/arm64/kvm/Makefile              |   2 +-
 arch/arm64/kvm/emulate.c             | 158 +++++++++++++++++++++++++++++++++++
 3 files changed, 170 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/kvm/emulate.c

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 20a1a39..eec0738 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -31,6 +31,9 @@
 unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
 unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
 
+bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
+void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
+
 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
@@ -57,12 +60,18 @@ static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
 
 static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
 {
-	return true;	/* No conditionals on arm64 */
+	if (vcpu_mode_is_32bit(vcpu))
+		return kvm_condition_valid32(vcpu);
+
+	return true;
 }
 
 static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
 {
-	*vcpu_pc(vcpu) += 4;
+	if (vcpu_mode_is_32bit(vcpu))
+		kvm_skip_instr32(vcpu, is_wide_instr);
+	else
+		*vcpu_pc(vcpu) += 4;
 }
 
 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index b0f82da..fa78b7d 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -15,7 +15,7 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/psci.o $(ARM)/perf.o
 
-kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o
+kvm-$(CONFIG_KVM_ARM_HOST) += emulate.o inject_fault.o regmap.o
 kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o
 kvm-$(CONFIG_KVM_ARM_HOST) += guest.o reset.o sys_regs.o sys_regs_generic_v8.o
 
diff --git a/arch/arm64/kvm/emulate.c b/arch/arm64/kvm/emulate.c
new file mode 100644
index 0000000..124418d
--- /dev/null
+++ b/arch/arm64/kvm/emulate.c
@@ -0,0 +1,158 @@
+/*
+ * (not much of an) Emulation layer for 32bit guests.
+ *
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * based on arch/arm/kvm/emulate.c
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+
+/*
+ * stolen from arch/arm/kernel/opcodes.c
+ *
+ * condition code lookup table
+ * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
+ *
+ * bit position in short is condition code: NZCV
+ */
+static const unsigned short cc_map[16] = {
+	0xF0F0,			/* EQ == Z set            */
+	0x0F0F,			/* NE                     */
+	0xCCCC,			/* CS == C set            */
+	0x3333,			/* CC                     */
+	0xFF00,			/* MI == N set            */
+	0x00FF,			/* PL                     */
+	0xAAAA,			/* VS == V set            */
+	0x5555,			/* VC                     */
+	0x0C0C,			/* HI == C set && Z clear */
+	0xF3F3,			/* LS == C clear || Z set */
+	0xAA55,			/* GE == (N==V)           */
+	0x55AA,			/* LT == (N!=V)           */
+	0x0A05,			/* GT == (!Z && (N==V))   */
+	0xF5FA,			/* LE == (Z || (N!=V))    */
+	0xFFFF,			/* AL always              */
+	0			/* NV                     */
+};
+
+static int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
+{
+	u32 esr = kvm_vcpu_get_hsr(vcpu);
+
+	if (esr & ESR_EL2_CV)
+		return (esr & ESR_EL2_COND) >> ESR_EL2_COND_SHIFT;
+
+	return -1;
+}
+
+/*
+ * Check if a trapped instruction should have been executed or not.
+ */
+bool kvm_condition_valid32(const struct kvm_vcpu *vcpu)
+{
+	unsigned long cpsr;
+	u32 cpsr_cond;
+	int cond;
+
+	/* Top two bits non-zero?  Unconditional. */
+	if (kvm_vcpu_get_hsr(vcpu) >> 30)
+		return true;
+
+	/* Is condition field valid? */
+	cond = kvm_vcpu_get_condition(vcpu);
+	if (cond == 0xE)
+		return true;
+
+	cpsr = *vcpu_cpsr(vcpu);
+
+	if (cond < 0) {
+		/* This can happen in Thumb mode: examine IT state. */
+		unsigned long it;
+
+		it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
+
+		/* it == 0 => unconditional. */
+		if (it == 0)
+			return true;
+
+		/* The cond for this insn works out as the top 4 bits. */
+		cond = (it >> 4);
+	}
+
+	cpsr_cond = cpsr >> 28;
+
+	if (!((cc_map[cond] >> cpsr_cond) & 1))
+		return false;
+
+	return true;
+}
+
+/**
+ * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
+ * @vcpu:	The VCPU pointer
+ *
+ * When exceptions occur while instructions are executed in Thumb IF-THEN
+ * blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
+ * to do this little bit of work manually. The fields map like this:
+ *
+ * IT[7:0] -> CPSR[26:25],CPSR[15:10]
+ */
+static void kvm_adjust_itstate(struct kvm_vcpu *vcpu)
+{
+	unsigned long itbits, cond;
+	unsigned long cpsr = *vcpu_cpsr(vcpu);
+	bool is_arm = !(cpsr & COMPAT_PSR_T_BIT);
+
+	BUG_ON(is_arm && (cpsr & COMPAT_PSR_IT_MASK));
+
+	if (!(cpsr & COMPAT_PSR_IT_MASK))
+		return;
+
+	cond = (cpsr & 0xe000) >> 13;
+	itbits = (cpsr & 0x1c00) >> (10 - 2);
+	itbits |= (cpsr & (0x3 << 25)) >> 25;
+
+	/* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
+	if ((itbits & 0x7) == 0)
+		itbits = cond = 0;
+	else
+		itbits = (itbits << 1) & 0x1f;
+
+	cpsr &= ~COMPAT_PSR_IT_MASK;
+	cpsr |= cond << 13;
+	cpsr |= (itbits & 0x1c) << (10 - 2);
+	cpsr |= (itbits & 0x3) << 25;
+	*vcpu_cpsr(vcpu) = cpsr;
+}
+
+/**
+ * kvm_skip_instr - skip a trapped instruction and proceed to the next
+ * @vcpu: The vcpu pointer
+ */
+void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+	bool is_thumb;
+
+	is_thumb = !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_T_BIT);
+	if (is_thumb && !is_wide_instr)
+		*vcpu_pc(vcpu) += 2;
+	else
+		*vcpu_pc(vcpu) += 4;
+	kvm_adjust_itstate(vcpu);
+}
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:48 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:48 +0100
Subject: [PATCH v4 20/32] arm64: KVM: PSCI implementation
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-21-git-send-email-marc.zyngier@arm.com>

Wire the PSCI backend into the exit handling code.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_host.h |  2 +-
 arch/arm64/include/asm/kvm_psci.h | 23 +++++++++++++++++++++++
 arch/arm64/include/uapi/asm/kvm.h | 16 ++++++++++++++++
 arch/arm64/kvm/handle_exit.c      | 16 +++++++---------
 4 files changed, 47 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm64/include/asm/kvm_psci.h

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 2500eb6..2fdeb32 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -34,7 +34,7 @@
 #include <kvm/arm_vgic.h>
 #include <kvm/arm_arch_timer.h>
 
-#define KVM_VCPU_MAX_FEATURES 0
+#define KVM_VCPU_MAX_FEATURES 1
 
 /* We don't currently support large pages. */
 #define KVM_HPAGE_GFN_SHIFT(x)	0
diff --git a/arch/arm64/include/asm/kvm_psci.h b/arch/arm64/include/asm/kvm_psci.h
new file mode 100644
index 0000000..e301a48
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_psci.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_PSCI_H__
+#define __ARM64_KVM_PSCI_H__
+
+bool kvm_psci_call(struct kvm_vcpu *vcpu);
+
+#endif /* __ARM64_KVM_PSCI_H__ */
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index ebac919..fb60f90 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -69,6 +69,8 @@ struct kvm_regs {
 #define KVM_VGIC_V2_DIST_SIZE		0x1000
 #define KVM_VGIC_V2_CPU_SIZE		0x2000
 
+#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */
+
 struct kvm_vcpu_init {
 	__u32 target;
 	__u32 features[7];
@@ -141,6 +143,20 @@ struct kvm_arch_memory_slot {
 /* Highest supported SPI, from VGIC_NR_IRQS */
 #define KVM_ARM_IRQ_GIC_MAX		127
 
+/* PSCI interface */
+#define KVM_PSCI_FN_BASE		0x95c1ba5e
+#define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))
+
+#define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)
+#define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)
+#define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)
+#define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)
+
+#define KVM_PSCI_RET_SUCCESS		0
+#define KVM_PSCI_RET_NI			((unsigned long)-1)
+#define KVM_PSCI_RET_INVAL		((unsigned long)-2)
+#define KVM_PSCI_RET_DENIED		((unsigned long)-3)
+
 #endif
 
 #endif /* __ARM_KVM_H__ */
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index c65d115..4766b7f 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -24,26 +24,24 @@
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_coproc.h>
 #include <asm/kvm_mmu.h>
+#include <asm/kvm_psci.h>
 
 typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
 
 static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-	/*
-	 * Guest called HVC instruction:
-	 * Let it know we don't want that by injecting an undefined exception.
-	 */
-	kvm_debug("hvc: %x (at %08lx)", kvm_vcpu_get_hsr(vcpu) & ((1 << 16) - 1),
-		  *vcpu_pc(vcpu));
-	kvm_debug("         HSR: %8x", kvm_vcpu_get_hsr(vcpu));
+	if (kvm_psci_call(vcpu))
+		return 1;
+
 	kvm_inject_undefined(vcpu);
 	return 1;
 }
 
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-	/* We don't support SMC; don't do that. */
-	kvm_debug("smc: at %08lx", *vcpu_pc(vcpu));
+	if (kvm_psci_call(vcpu))
+		return 1;
+
 	kvm_inject_undefined(vcpu);
 	return 1;
 }
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:54 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:54 +0100
Subject: [PATCH v4 26/32] arm64: KVM: CPU specific 32bit coprocessor access
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-27-git-send-email-marc.zyngier@arm.com>

Enable handling of CPU specific 32bit coprocessor access. Not much
here either.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/sys_regs_generic_v8.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c b/arch/arm64/kvm/sys_regs_generic_v8.c
index d4e8039..4268ab9 100644
--- a/arch/arm64/kvm/sys_regs_generic_v8.c
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -59,11 +59,21 @@ static const struct sys_reg_desc genericv8_sys_regs[] = {
 	  access_actlr, reset_actlr, ACTLR_EL1 },
 };
 
+static const struct sys_reg_desc genericv8_cp15_regs[] = {
+	/* ACTLR */
+	{ Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
+	  access_actlr },
+};
+
 static struct kvm_sys_reg_target_table genericv8_target_table = {
 	.table64 = {
 		.table = genericv8_sys_regs,
 		.num = ARRAY_SIZE(genericv8_sys_regs),
 	},
+	.table32 = {
+		.table = genericv8_cp15_regs,
+		.num = ARRAY_SIZE(genericv8_cp15_regs),
+	},
 };
 
 static int __init sys_reg_genericv8_init(void)
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:45 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:45 +0100
Subject: [PATCH v4 17/32] arm64: KVM: Exit handling
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-18-git-send-email-marc.zyngier@arm.com>

Handle the exit of a VM, decoding the exit reason from HYP mode
and calling the corresponding handler.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/handle_exit.c | 119 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)
 create mode 100644 arch/arm64/kvm/handle_exit.c

diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
new file mode 100644
index 0000000..c65d115
--- /dev/null
+++ b/arch/arm64/kvm/handle_exit.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/kvm/handle_exit.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/kvm_mmu.h>
+
+typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
+
+static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	/*
+	 * Guest called HVC instruction:
+	 * Let it know we don't want that by injecting an undefined exception.
+	 */
+	kvm_debug("hvc: %x (at %08lx)", kvm_vcpu_get_hsr(vcpu) & ((1 << 16) - 1),
+		  *vcpu_pc(vcpu));
+	kvm_debug("         HSR: %8x", kvm_vcpu_get_hsr(vcpu));
+	kvm_inject_undefined(vcpu);
+	return 1;
+}
+
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	/* We don't support SMC; don't do that. */
+	kvm_debug("smc: at %08lx", *vcpu_pc(vcpu));
+	kvm_inject_undefined(vcpu);
+	return 1;
+}
+
+/**
+ * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
+ * @vcpu:	the vcpu pointer
+ *
+ * Simply call kvm_vcpu_block(), which will halt execution of
+ * world-switches and schedule other host processes until there is an
+ * incoming IRQ or FIQ to the VM.
+ */
+static int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	kvm_vcpu_block(vcpu);
+	return 1;
+}
+
+static exit_handle_fn arm_exit_handlers[] = {
+	[ESR_EL2_EC_WFI]	= kvm_handle_wfi,
+	[ESR_EL2_EC_HVC64]	= handle_hvc,
+	[ESR_EL2_EC_SMC64]	= handle_smc,
+	[ESR_EL2_EC_SYS64]	= kvm_handle_sys_reg,
+	[ESR_EL2_EC_IABT]	= kvm_handle_guest_abort,
+	[ESR_EL2_EC_DABT]	= kvm_handle_guest_abort,
+};
+
+static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
+{
+	u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
+
+	if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
+	    !arm_exit_handlers[hsr_ec]) {
+		kvm_err("Unkown exception class: hsr: %#08x\n",
+			(unsigned int)kvm_vcpu_get_hsr(vcpu));
+		BUG();
+	}
+
+	return arm_exit_handlers[hsr_ec];
+}
+
+/*
+ * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
+ * proper exit to userspace.
+ */
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+		       int exception_index)
+{
+	exit_handle_fn exit_handler;
+
+	switch (exception_index) {
+	case ARM_EXCEPTION_IRQ:
+		return 1;
+	case ARM_EXCEPTION_TRAP:
+		/*
+		 * See ARM ARM B1.14.1: "Hyp traps on instructions
+		 * that fail their condition code check"
+		 */
+		if (!kvm_condition_valid(vcpu)) {
+			kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+			return 1;
+		}
+
+		exit_handler = kvm_get_exit_handler(vcpu);
+
+		return exit_handler(vcpu, run);
+	default:
+		kvm_pr_unimpl("Unsupported exception type: %d",
+			      exception_index);
+		run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		return 0;
+	}
+}
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:56 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:56 +0100
Subject: [PATCH v4 28/32] arm64: KVM: 32bit guest fault injection
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-29-git-send-email-marc.zyngier@arm.com>

Add fault injection capability for 32bit guests.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/inject_fault.c | 79 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
index 54f6562..81a02a8 100644
--- a/arch/arm64/kvm/inject_fault.c
+++ b/arch/arm64/kvm/inject_fault.c
@@ -1,5 +1,5 @@
 /*
- * Fault injection for 64bit guests.
+ * Fault injection for both 32 and 64bit guests.
  *
  * Copyright (C) 2012,2013 - ARM Ltd
  * Author: Marc Zyngier <marc.zyngier at arm.com>
@@ -29,6 +29,74 @@
 				 PSR_I_BIT | PSR_D_BIT)
 #define EL1_EXCEPT_SYNC_OFFSET	0x200
 
+static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
+{
+	unsigned long cpsr;
+	unsigned long new_spsr_value = *vcpu_cpsr(vcpu);
+	bool is_thumb = (new_spsr_value & COMPAT_PSR_T_BIT);
+	u32 return_offset = (is_thumb) ? 4 : 0;
+	u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
+
+	cpsr = mode | COMPAT_PSR_I_BIT;
+
+	if (sctlr & (1 << 30))
+		cpsr |= COMPAT_PSR_T_BIT;
+	if (sctlr & (1 << 25))
+		cpsr |= COMPAT_PSR_E_BIT;
+
+	*vcpu_cpsr(vcpu) = cpsr;
+
+	/* Note: These now point to the banked copies */
+	*vcpu_spsr(vcpu) = new_spsr_value;
+	*vcpu_reg(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
+
+	/* Branch to exception vector */
+	if (sctlr & (1 << 13))
+		vect_offset += 0xffff0000;
+	else /* always have security exceptions */
+		vect_offset += vcpu_cp15(vcpu, c12_VBAR);
+
+	*vcpu_pc(vcpu) = vect_offset;
+}
+
+static void inject_undef32(struct kvm_vcpu *vcpu)
+{
+	prepare_fault32(vcpu, COMPAT_PSR_MODE_UND, 4);
+}
+
+/*
+ * Modelled after TakeDataAbortException() and TakePrefetchAbortException
+ * pseudocode.
+ */
+static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
+			 unsigned long addr)
+{
+	u32 vect_offset;
+	u32 *far, *fsr;
+	bool is_lpae;
+
+	if (is_pabt) {
+		vect_offset = 12;
+		far = &vcpu_cp15(vcpu, c6_IFAR);
+		fsr = &vcpu_cp15(vcpu, c5_IFSR);
+	} else { /* !iabt */
+		vect_offset = 16;
+		far = &vcpu_cp15(vcpu, c6_DFAR);
+		fsr = &vcpu_cp15(vcpu, c5_DFSR);
+	}
+
+	prepare_fault32(vcpu, COMPAT_PSR_MODE_ABT | COMPAT_PSR_A_BIT, vect_offset);
+
+	*far = addr;
+
+	/* Give the guest an IMPLEMENTATION DEFINED exception */
+	is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
+	if (is_lpae)
+		*fsr = 1 << 9 | 0x34;
+	else
+		*fsr = 0x14;
+}
+
 static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
 {
 	unsigned long cpsr = *vcpu_cpsr(vcpu);
@@ -98,6 +166,9 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
  */
 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
 {
+	if (!(vcpu->arch.hcr_el2 & HCR_RW))
+		inject_abt32(vcpu, false, addr);
+
 	inject_abt64(vcpu, false, addr);
 }
 
@@ -111,6 +182,9 @@ void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
  */
 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
 {
+	if (!(vcpu->arch.hcr_el2 & HCR_RW))
+		inject_abt32(vcpu, true, addr);
+
 	inject_abt64(vcpu, true, addr);
 }
 
@@ -122,5 +196,8 @@ void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
  */
 void kvm_inject_undefined(struct kvm_vcpu *vcpu)
 {
+	if (!(vcpu->arch.hcr_el2 & HCR_RW))
+		inject_undef32(vcpu);
+
 	inject_undef64(vcpu);
 }
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:51 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:51 +0100
Subject: [PATCH v4 23/32] arm64: KVM: 32bit GP register access
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-24-git-send-email-marc.zyngier@arm.com>

Allow access to the 32bit register file through the usual API.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_emulate.h |  15 +++-
 arch/arm64/kvm/Makefile              |   2 +-
 arch/arm64/kvm/regmap.c              | 168 +++++++++++++++++++++++++++++++++++
 3 files changed, 183 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm64/kvm/regmap.c

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 6c1725e..20a1a39 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -28,6 +28,9 @@
 #include <asm/kvm_mmio.h>
 #include <asm/ptrace.h>
 
+unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
+unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
+
 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
@@ -49,7 +52,7 @@ static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
 
 static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
 {
-	return false;	/* 32bit? Bahhh... */
+	return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
 }
 
 static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
@@ -64,16 +67,23 @@ static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
 
 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
 {
+	*vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;
 }
 
 static inline unsigned long *vcpu_reg(const struct kvm_vcpu *vcpu, u8 reg_num)
 {
+	if (vcpu_mode_is_32bit(vcpu))
+		return vcpu_reg32(vcpu, reg_num);
+
 	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.regs[reg_num];
 }
 
 /* Get vcpu SPSR for current mode */
 static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
 {
+	if (vcpu_mode_is_32bit(vcpu))
+		return vcpu_spsr32(vcpu);
+
 	return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
 }
 
@@ -81,6 +91,9 @@ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
 {
 	u32 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
 
+	if (vcpu_mode_is_32bit(vcpu))
+		return mode > COMPAT_PSR_MODE_USR;
+
 	return mode != PSR_MODE_EL0t;
 }
 
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 75b8c48..b0f82da 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -15,7 +15,7 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/psci.o $(ARM)/perf.o
 
-kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o
+kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o
 kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o
 kvm-$(CONFIG_KVM_ARM_HOST) += guest.o reset.o sys_regs.o sys_regs_generic_v8.o
 
diff --git a/arch/arm64/kvm/regmap.c b/arch/arm64/kvm/regmap.c
new file mode 100644
index 0000000..bbc6ae3
--- /dev/null
+++ b/arch/arm64/kvm/regmap.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * Derived from arch/arm/kvm/emulate.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall at virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/ptrace.h>
+
+#define VCPU_NR_MODES 6
+#define REG_OFFSET(_reg) \
+	(offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long))
+
+#define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
+
+static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][16] = {
+	/* USR Registers */
+	{
+		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+		USR_REG_OFFSET(12), USR_REG_OFFSET(13),	USR_REG_OFFSET(14),
+		REG_OFFSET(pc)
+	},
+
+	/* FIQ Registers */
+	{
+		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+		USR_REG_OFFSET(6), USR_REG_OFFSET(7),
+		REG_OFFSET(compat_r8_fiq),  /* r8 */
+		REG_OFFSET(compat_r9_fiq),  /* r9 */
+		REG_OFFSET(compat_r10_fiq), /* r10 */
+		REG_OFFSET(compat_r11_fiq), /* r11 */
+		REG_OFFSET(compat_r12_fiq), /* r12 */
+		REG_OFFSET(compat_sp_fiq),  /* r13 */
+		REG_OFFSET(compat_lr_fiq),  /* r14 */
+		REG_OFFSET(pc)
+	},
+
+	/* IRQ Registers */
+	{
+		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+		USR_REG_OFFSET(12),
+		REG_OFFSET(compat_sp_irq), /* r13 */
+		REG_OFFSET(compat_lr_irq), /* r14 */
+		REG_OFFSET(pc)
+	},
+
+	/* SVC Registers */
+	{
+		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+		USR_REG_OFFSET(12),
+		REG_OFFSET(compat_sp_svc), /* r13 */
+		REG_OFFSET(compat_lr_svc), /* r14 */
+		REG_OFFSET(pc)
+	},
+
+	/* ABT Registers */
+	{
+		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+		USR_REG_OFFSET(12),
+		REG_OFFSET(compat_sp_abt), /* r13 */
+		REG_OFFSET(compat_lr_abt), /* r14 */
+		REG_OFFSET(pc)
+	},
+
+	/* UND Registers */
+	{
+		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+		USR_REG_OFFSET(12),
+		REG_OFFSET(compat_sp_und), /* r13 */
+		REG_OFFSET(compat_lr_und), /* r14 */
+		REG_OFFSET(pc)
+	},
+};
+
+/*
+ * Return a pointer to the register number valid in the current mode of
+ * the virtual CPU.
+ */
+unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num)
+{
+	unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs.regs;
+	unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
+
+	switch (mode) {
+	case COMPAT_PSR_MODE_USR ... COMPAT_PSR_MODE_SVC:
+		mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */
+		break;
+
+	case COMPAT_PSR_MODE_ABT:
+		mode = 4;
+		break;
+
+	case COMPAT_PSR_MODE_UND:
+		mode = 5;
+		break;
+
+	case COMPAT_PSR_MODE_SYS:
+		mode = 0;	/* SYS maps to USR */
+		break;
+
+	default:
+		BUG();
+	}
+
+	return reg_array + vcpu_reg_offsets[mode][reg_num];
+}
+
+/*
+ * Return the SPSR for the current mode of the virtual CPU.
+ */
+unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu)
+{
+	unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
+	switch (mode) {
+	case COMPAT_PSR_MODE_SVC:
+		mode = KVM_SPSR_SVC;
+		break;
+	case COMPAT_PSR_MODE_ABT:
+		mode = KVM_SPSR_ABT;
+		break;
+	case COMPAT_PSR_MODE_UND:
+		mode = KVM_SPSR_UND;
+		break;
+	case COMPAT_PSR_MODE_IRQ:
+		mode = KVM_SPSR_IRQ;
+		break;
+	case COMPAT_PSR_MODE_FIQ:
+		mode = KVM_SPSR_FIQ;
+		break;
+	default:
+		BUG();
+	}
+
+	return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[mode];
+}
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:46 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:46 +0100
Subject: [PATCH v4 18/32] arm64: KVM: Plug the VGIC
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-19-git-send-email-marc.zyngier@arm.com>

Add support for the in-kernel GIC emulation.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/kvm/hyp.S | 88 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
index e6884d3..06a69af4 100644
--- a/arch/arm64/kvm/hyp.S
+++ b/arch/arm64/kvm/hyp.S
@@ -306,6 +306,90 @@ __kvm_hyp_code_start:
 	msr	vttbr_el2, xzr
 .endm
 
+/*
+ * Save the VGIC CPU state into memory
+ * x0: Register pointing to VCPU struct
+ * Do not corrupt x1!!!
+ */
+.macro save_vgic_state
+	/* Get VGIC VCTRL base into x2 */
+	ldr	x2, [x0, #VCPU_KVM]
+	kern_hyp_va	x2
+	ldr	x2, [x2, #KVM_VGIC_VCTRL]
+	kern_hyp_va	x2
+	cbz	x2, 2f		// disabled
+
+	/* Compute the address of struct vgic_cpu */
+	add	x3, x0, #VCPU_VGIC_CPU
+
+	/* Save all interesting registers */
+	ldr	w4, [x2, #GICH_HCR]
+	ldr	w5, [x2, #GICH_VMCR]
+	ldr	w6, [x2, #GICH_MISR]
+	ldr	w7, [x2, #GICH_EISR0]
+	ldr	w8, [x2, #GICH_EISR1]
+	ldr	w9, [x2, #GICH_ELRSR0]
+	ldr	w10, [x2, #GICH_ELRSR1]
+	ldr	w11, [x2, #GICH_APR]
+
+	str	w4, [x3, #VGIC_CPU_HCR]
+	str	w5, [x3, #VGIC_CPU_VMCR]
+	str	w6, [x3, #VGIC_CPU_MISR]
+	str	w7, [x3, #VGIC_CPU_EISR]
+	str	w8, [x3, #(VGIC_CPU_EISR + 4)]
+	str	w9, [x3, #VGIC_CPU_ELRSR]
+	str	w10, [x3, #(VGIC_CPU_ELRSR + 4)]
+	str	w11, [x3, #VGIC_CPU_APR]
+
+	/* Clear GICH_HCR */
+	str	wzr, [x2, #GICH_HCR]
+
+	/* Save list registers */
+	add	x2, x2, #GICH_LR0
+	ldr	w4, [x3, #VGIC_CPU_NR_LR]
+	add	x3, x3, #VGIC_CPU_LR
+1:	ldr	w5, [x2], #4
+	str	w5, [x3], #4
+	sub	w4, w4, #1
+	cbnz	w4, 1b
+2:
+.endm
+
+/*
+ * Restore the VGIC CPU state from memory
+ * x0: Register pointing to VCPU struct
+ */
+.macro restore_vgic_state
+	/* Get VGIC VCTRL base into x2 */
+	ldr	x2, [x0, #VCPU_KVM]
+	kern_hyp_va	x2
+	ldr	x2, [x2, #KVM_VGIC_VCTRL]
+	kern_hyp_va	x2
+	cbz	x2, 2f		// disabled
+
+	/* Compute the address of struct vgic_cpu */
+	add	x3, x0, #VCPU_VGIC_CPU
+
+	/* We only restore a minimal set of registers */
+	ldr	w4, [x3, #VGIC_CPU_HCR]
+	ldr	w5, [x3, #VGIC_CPU_VMCR]
+	ldr	w6, [x3, #VGIC_CPU_APR]
+
+	str	w4, [x2, #GICH_HCR]
+	str	w5, [x2, #GICH_VMCR]
+	str	w6, [x2, #GICH_APR]
+
+	/* Restore list registers */
+	add	x2, x2, #GICH_LR0
+	ldr	w4, [x3, #VGIC_CPU_NR_LR]
+	add	x3, x3, #VGIC_CPU_LR
+1:	ldr	w5, [x3], #4
+	str	w5, [x2], #4
+	sub	w4, w4, #1
+	cbnz	w4, 1b
+2:
+.endm
+
 __save_sysregs:
 	save_sysregs
 	ret
@@ -348,6 +432,8 @@ ENTRY(__kvm_vcpu_run)
 	activate_traps
 	activate_vm
 
+	restore_vgic_state
+
 	// Guest context
 	add	x2, x0, #VCPU_CONTEXT
 
@@ -370,6 +456,8 @@ __kvm_vcpu_return:
 	bl __save_fpsimd
 	bl __save_sysregs
 
+	save_vgic_state
+
 	deactivate_traps
 	deactivate_vm
 
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:49 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:49 +0100
Subject: [PATCH v4 21/32] arm64: KVM: Build system integration
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/Kconfig      |  2 ++
 arch/arm64/Makefile     |  2 +-
 arch/arm64/kvm/Kconfig  | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm64/kvm/Makefile | 23 +++++++++++++++++++
 4 files changed, 85 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/kvm/Kconfig
 create mode 100644 arch/arm64/kvm/Makefile

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 48347dc..a74f6fd 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -237,6 +237,8 @@ source "drivers/Kconfig"
 
 source "fs/Kconfig"
 
+source "arch/arm64/kvm/Kconfig"
+
 source "arch/arm64/Kconfig.debug"
 
 source "security/Kconfig"
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index c95c5cb..ae89e63 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -36,7 +36,7 @@ TEXT_OFFSET := 0x00080000
 
 export	TEXT_OFFSET GZFLAGS
 
-core-y		+= arch/arm64/kernel/ arch/arm64/mm/
+core-y		+= arch/arm64/kernel/ arch/arm64/mm/ arch/arm64/kvm/
 libs-y		:= arch/arm64/lib/ $(libs-y)
 libs-y		+= $(LIBGCC)
 
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
new file mode 100644
index 0000000..a76be8b
--- /dev/null
+++ b/arch/arm64/kvm/Kconfig
@@ -0,0 +1,59 @@
+#
+# KVM configuration
+#
+
+source "virt/kvm/Kconfig"
+
+menuconfig VIRTUALIZATION
+	bool "Virtualization"
+	---help---
+	  Say Y here to get to see options for using your Linux host to run
+	  other operating systems inside virtual machines (guests).
+	  This option alone does not add any kernel code.
+
+	  If you say N, all options in this submenu will be skipped and
+	  disabled.
+
+if VIRTUALIZATION
+
+config KVM
+	bool "Kernel-based Virtual Machine (KVM) support"
+	select PREEMPT_NOTIFIERS
+	select ANON_INODES
+	select KVM_MMIO
+	select KVM_ARM_HOST
+	select KVM_ARM_VGIC
+	select KVM_ARM_TIMER
+	---help---
+	  Support hosting virtualized guest machines.
+
+	  This module provides access to the hardware capabilities through
+	  a character device node named /dev/kvm.
+
+	  If unsure, say N.
+
+config KVM_ARM_HOST
+	bool
+	depends on KVM
+	depends on MMU
+	select	MMU_NOTIFIER
+	---help---
+	  Provides host support for ARM processors.
+
+config KVM_ARM_VGIC
+        bool
+	depends on KVM_ARM_HOST && OF
+	select HAVE_KVM_IRQCHIP
+	---help---
+	  Adds support for a hardware assisted, in-kernel GIC emulation.
+
+config KVM_ARM_TIMER
+        bool
+	depends on KVM_ARM_VGIC
+	select HAVE_KVM_IRQCHIP
+	---help---
+	  Adds support for the Architected Timers in virtual machines
+
+source drivers/virtio/Kconfig
+
+endif # VIRTUALIZATION
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
new file mode 100644
index 0000000..75b8c48
--- /dev/null
+++ b/arch/arm64/kvm/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for Kernel-based Virtual Machine module
+#
+
+ccflags-y += -Ivirt/kvm -Iarch/arm64/kvm
+CFLAGS_arm.o := -I.
+CFLAGS_mmu.o := -I.
+
+KVM=../../../virt/kvm
+ARM=../../../arch/arm/kvm
+
+obj-$(CONFIG_KVM_ARM_HOST) += kvm.o
+
+kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
+kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o
+kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/psci.o $(ARM)/perf.o
+
+kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o
+kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o
+kvm-$(CONFIG_KVM_ARM_HOST) += guest.o reset.o sys_regs.o sys_regs_generic_v8.o
+
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
-- 
1.8.2.3




From marc.zyngier at arm.com  Tue May 14 10:13:53 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 14 May 2013 15:13:53 +0100
Subject: [PATCH v4 25/32] arm64: KVM: 32bit handling of coprocessor traps
In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1368540840-26750-26-git-send-email-marc.zyngier@arm.com>

Provide the necessary infrastructure to trap coprocessor accesses that
occur when running 32bit guests.

Also wire SMC and HVC trapped in 32bit mode while were at it.

Reviewed-by: Christopher Covington <cov at codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm64/include/asm/kvm_coproc.h |   5 +
 arch/arm64/kvm/handle_exit.c        |   7 ++
 arch/arm64/kvm/sys_regs.c           | 181 ++++++++++++++++++++++++++++++++++--
 3 files changed, 186 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_coproc.h b/arch/arm64/include/asm/kvm_coproc.h
index 9b4477a..9a59301 100644
--- a/arch/arm64/include/asm/kvm_coproc.h
+++ b/arch/arm64/include/asm/kvm_coproc.h
@@ -32,11 +32,16 @@ struct kvm_sys_reg_table {
 
 struct kvm_sys_reg_target_table {
 	struct kvm_sys_reg_table table64;
+	struct kvm_sys_reg_table table32;
 };
 
 void kvm_register_target_sys_reg_table(unsigned int target,
 				       struct kvm_sys_reg_target_table *table);
 
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run);
 
 #define kvm_coproc_table_init kvm_sys_reg_table_init
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 4766b7f..9beaca03 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -62,6 +62,13 @@ static int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
 
 static exit_handle_fn arm_exit_handlers[] = {
 	[ESR_EL2_EC_WFI]	= kvm_handle_wfi,
+	[ESR_EL2_EC_CP15_32]	= kvm_handle_cp15_32,
+	[ESR_EL2_EC_CP15_64]	= kvm_handle_cp15_64,
+	[ESR_EL2_EC_CP14_MR]	= kvm_handle_cp14_access,
+	[ESR_EL2_EC_CP14_LS]	= kvm_handle_cp14_load_store,
+	[ESR_EL2_EC_CP14_64]	= kvm_handle_cp14_access,
+	[ESR_EL2_EC_HVC32]	= handle_hvc,
+	[ESR_EL2_EC_SMC32]	= handle_smc,
 	[ESR_EL2_EC_HVC64]	= handle_hvc,
 	[ESR_EL2_EC_SMC64]	= handle_smc,
 	[ESR_EL2_EC_SYS64]	= kvm_handle_sys_reg,
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 52fff0a..9492360 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -38,6 +38,10 @@
  * types are different. My gut feeling is that it should be pretty
  * easy to merge, but that would be an ABI breakage -- again. VFP
  * would also need to be abstracted.
+ *
+ * For AArch32, we only take care of what is being trapped. Anything
+ * that has to do with init and userspace access has to go via the
+ * 64bit interface.
  */
 
 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
@@ -166,6 +170,16 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	{ Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 	  access_dcsw },
 
+	/* TEECR32_EL1 */
+	{ Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
+	  NULL, reset_val, TEECR32_EL1, 0 },
+	/* TEEHBR32_EL1 */
+	{ Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
+	  NULL, reset_val, TEEHBR32_EL1, 0 },
+	/* DBGVCR32_EL2 */
+	{ Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
+	  NULL, reset_val, DBGVCR32_EL2, 0 },
+
 	/* MPIDR_EL1 */
 	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 	  NULL, reset_mpidr, MPIDR_EL1 },
@@ -276,6 +290,39 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	/* TPIDRRO_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 	  NULL, reset_unknown, TPIDRRO_EL0 },
+
+	/* DACR32_EL2 */
+	{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
+	  NULL, reset_unknown, DACR32_EL2 },
+	/* IFSR32_EL2 */
+	{ Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
+	  NULL, reset_unknown, IFSR32_EL2 },
+	/* FPEXC32_EL2 */
+	{ Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
+	  NULL, reset_val, FPEXC32_EL2, 0x70 },
+};
+
+/* Trapped cp15 registers */
+static const struct sys_reg_desc cp15_regs[] = {
+	/*
+	 * DC{C,I,CI}SW operations:
+	 */
+	{ Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
+	{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
+	{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 0), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), pm_fake },
+	{ Op1( 0), CRn( 9), CRm(14), Op2( 2), pm_fake },
 };
 
 /* Target specific emulation tables */
@@ -288,13 +335,20 @@ void kvm_register_target_sys_reg_table(unsigned int target,
 }
 
 /* Get specific register table for this target. */
-static const struct sys_reg_desc *get_target_table(unsigned target, size_t *num)
+static const struct sys_reg_desc *get_target_table(unsigned target,
+						   bool mode_is_64,
+						   size_t *num)
 {
 	struct kvm_sys_reg_target_table *table;
 
 	table = target_tables[target];
-	*num = table->table64.num;
-	return table->table64.table;
+	if (mode_is_64) {
+		*num = table->table64.num;
+		return table->table64.table;
+	} else {
+		*num = table->table32.num;
+		return table->table32.table;
+	}
 }
 
 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
@@ -322,13 +376,126 @@ static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
 	return NULL;
 }
 
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	kvm_inject_undefined(vcpu);
+	return 1;
+}
+
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	kvm_inject_undefined(vcpu);
+	return 1;
+}
+
+static void emulate_cp15(struct kvm_vcpu *vcpu,
+			 const struct sys_reg_params *params)
+{
+	size_t num;
+	const struct sys_reg_desc *table, *r;
+
+	table = get_target_table(vcpu->arch.target, false, &num);
+
+	/* Search target-specific then generic table. */
+	r = find_reg(params, table, num);
+	if (!r)
+		r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
+
+	if (likely(r)) {
+		/*
+		 * Not having an accessor means that we have
+		 * configured a trap that we don't know how to
+		 * handle. This certainly qualifies as a gross bug
+		 * that should be fixed right away.
+		 */
+		BUG_ON(!r->access);
+
+		if (likely(r->access(vcpu, params, r))) {
+			/* Skip instruction, since it was emulated */
+			kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+			return;
+		}
+		/* If access function fails, it should complain. */
+	}
+
+	kvm_err("Unsupported guest CP15 access at: %08lx\n", *vcpu_pc(vcpu));
+	print_sys_reg_instr(params);
+	kvm_inject_undefined(vcpu);
+}
+
+/**
+ * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	struct sys_reg_params params;
+	u32 hsr = kvm_vcpu_get_hsr(vcpu);
+	int Rt2 = (hsr >> 10) & 0xf;
+
+	params.CRm = (hsr >> 1) & 0xf;
+	params.Rt = (hsr >> 5) & 0xf;
+	params.is_write = ((hsr & 1) == 0);
+
+	params.Op0 = 0;
+	params.Op1 = (hsr >> 16) & 0xf;
+	params.Op2 = 0;
+	params.CRn = 0;
+
+	/*
+	 * Massive hack here. Store Rt2 in the top 32bits so we only
+	 * have one register to deal with. As we use the same trap
+	 * backends between AArch32 and AArch64, we get away with it.
+	 */
+	if (params.is_write) {
+		u64 val = *vcpu_reg(vcpu, params.Rt);
+		val &= 0xffffffff;
+		val |= *vcpu_reg(vcpu, Rt2) << 32;
+		*vcpu_reg(vcpu, params.Rt) = val;
+	}
+
+	emulate_cp15(vcpu, &params);
+
+	/* Do the opposite hack for the read side */
+	if (!params.is_write) {
+		u64 val = *vcpu_reg(vcpu, params.Rt);
+		val >>= 32;
+		*vcpu_reg(vcpu, Rt2) = val;
+	}
+
+	return 1;
+}
+
+/**
+ * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	struct sys_reg_params params;
+	u32 hsr = kvm_vcpu_get_hsr(vcpu);
+
+	params.CRm = (hsr >> 1) & 0xf;
+	params.Rt  = (hsr >> 5) & 0xf;
+	params.is_write = ((hsr & 1) == 0);
+	params.CRn = (hsr >> 10) & 0xf;
+	params.Op0 = 0;
+	params.Op1 = (hsr >> 14) & 0x7;
+	params.Op2 = (hsr >> 17) & 0x7;
+
+	emulate_cp15(vcpu, &params);
+	return 1;
+}
+
 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
 			   const struct sys_reg_params *params)
 {
 	size_t num;
 	const struct sys_reg_desc *table, *r;
 
-	table = get_target_table(vcpu->arch.target, &num);
+	table = get_target_table(vcpu->arch.target, true, &num);
 
 	/* Search target-specific then generic table. */
 	r = find_reg(params, table, num);
@@ -438,7 +605,7 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
 	if (!index_to_params(id, &params))
 		return NULL;
 
-	table = get_target_table(vcpu->arch.target, &num);
+	table = get_target_table(vcpu->arch.target, true, &num);
 	r = find_reg(&params, table, num);
 	if (!r)
 		r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
@@ -762,7 +929,7 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
 	size_t num;
 
 	/* We check for duplicates here, to allow arch-specific overrides. */
-	i1 = get_target_table(vcpu->arch.target, &num);
+	i1 = get_target_table(vcpu->arch.target, true, &num);
 	end1 = i1 + num;
 	i2 = sys_reg_descs;
 	end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
@@ -874,7 +1041,7 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
 	/* Generic chip reset first (so target could override). */
 	reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 
-	table = get_target_table(vcpu->arch.target, &num);
+	table = get_target_table(vcpu->arch.target, true, &num);
 	reset_sys_reg_descs(vcpu, table, num);
 
 	for (num = 1; num < NR_SYS_REGS; num++)
-- 
1.8.2.3




From dmurphy at ti.com  Tue May 14 10:17:56 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Tue, 14 May 2013 09:17:56 -0500
Subject: [PATCH v3] ARM:dts:omap4-panda:Update the LED support for the panda
 DTS
Message-ID: <1368541076-6854-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   40 +++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..2b516af 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,7 +16,7 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "pandaboard::status1";
@@ -137,6 +137,20 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_wkgpio_pins
+	>;
+
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..8d1ba03 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,43 @@
 		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
 		>;
 };
+
+&leds {
+	compatible = "gpio-leds";
+	heartbeat {
+		label = "pandaboard::status1";
+		gpios = <&gpio4 14 0>;
+		linux,default-trigger = "heartbeat";
+	};
+	mmc {
+		label = "pandaboard::status2";
+		gpios = <&gpio1 8 0>;
+		linux,default-trigger = "gpio";
+	};
+};
+
+&omap4_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_gpio_pins
+	>;
+
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
+&omap4_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_wkgpio_pins
+	>;
+
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
-- 
1.7.9.5



From t.figa at samsung.com  Tue May 14 10:21:36 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 14 May 2013 16:21:36 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <CACRpkda-wQyo8aYxbW9RJNcR3Kwe2w5AhaAuUHfaxBksa_Pm2A@mail.gmail.com>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
 <CACRpkda-wQyo8aYxbW9RJNcR3Kwe2w5AhaAuUHfaxBksa_Pm2A@mail.gmail.com>
Message-ID: <3254712.MAHxRAdAN5@amdc1227>

Hi Linus, Heiko,

On Tuesday 14 of May 2013 14:47:19 Linus Walleij wrote:
> On Sat, May 11, 2013 at 1:31 PM, Heiko St?bner <heiko at sntech.de> wrote:
> > Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> > with numerous virtual channels being mapped to a lot less physical ones.
> > The driver therefore borrows a lot from the amba-pl08x driver in this
> > regard. Functionality-wise the driver gains a memcpy ability in addition
> > to the slave_sg one.
> > 
> > The driver currently only supports the "newer" SoCs which can use any
> > physical channel for any dma slave. Support for the older SoCs where
> > each channel only supports a subset of possible dma slaves will have to
> > be added later.
> > 
> > Tested on a s3c2416-based board, memcpy using the dmatest module and
> > slave_sg partially using the spi-s3c64xx driver.
> > 
> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> 
> So have I understood correctly if I assume that *some* S3C
> variants, i.e. this: arch/arm/mach-s3c64xx/dma.c
> have a vanilla, unmodified, or just slightly modified
> PL08x block, while this DMAC is something probably based on
> the PL08x where some ASIC engineer has had a good time hacking
> around in the VHDL code to meet some feature requirements.
> Correct? Or plausible guess?
> 
> Exactly *how* far away from the pl08x hardware is it?

AFAIK the DMAC of S3C24xx is completely different from PL08x. I think Heiko 
just meant that it uses similar concepts, like virtual channels.

> I guess you have already come to the conclusion that the
> amba-pl08x.c driver cannot be augmented to handle this hardware
> after some educated reading of that code?
> 
> But are really no parts reusable?
> 
> For example, if the LLIs have the same layout, could we split
> out the LLI handling from amba-pl08x into a separate file and reuse
> that?
> 
> The more you share with amba-pl08x the better for everyone,
> I am positively sure. And please include Russell on the review
> chain, he wrote the virtual channel abstraction.
> 
> If I was given the option amongst S3C work I would definatley
> have augmented the amba-pl08x.c to handle the stuff in
> arch/arm/mach-s3c64xx/dma.c *first* then started to work on
> this driver, but I guess you might not be working on s3c64xx?

Well, I still hope that someone will pick up the work on adapting PL08x driver 
to support PL080s of S3C64xx as well, but most likely it will end up with me 
doing it, as a part of DT support for S3C64xx.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Kernel and System Framework



From lee.jones at linaro.org  Tue May 14 10:40:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 14 May 2013 15:40:57 +0100
Subject: [PATCH] mfd: db8500-prcmu: Update stored DSI PLL divider value
In-Reply-To: <1368537295-23459-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368537295-23459-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <20130514144057.GH28781@gmail.com>

On Tue, 14 May 2013, Ulf Hansson wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
> 
> Previously the DSI PLL divider rate was initialised statically and
> assumed to be 1. Before the common clock framework were enabled for
> ux500, a call to clk_set_rate() would always update the HW registers
> no matter what the current setting was.
> 
> This patch makes sure the actual hw settings and the sw assumed
> settings are matched.
> 
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
> Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson at stericsson.com>
> Cc: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/mfd/db8500-prcmu.c |    2 ++
>  1 file changed, 2 insertions(+)

I understand that this is causing an issue for the Multimedia guys who
use this. As it's causing an issue and you are 'the' ST-E clock guru,
I'll tentatively apply this to my v3.10 -fixes branch.

If anyone has any arguments against it, please step forward.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From andrew at lunn.ch  Tue May 14 10:42:24 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 14 May 2013 16:42:24 +0200
Subject: [PATCH] ARM: Kirkwood: Enable USB 3.0 in kirkwood_defconfig
Message-ID: <1368542544-24743-1-git-send-email-andrew@lunn.ch>

Some QNAP devices has a USB 3.0 host controller on a PCIe bus.  Enable
the driver for this in the default configuration.

Reported-by: Marek Vasut <marex at denx.de>
Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/configs/kirkwood_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252..49c9872 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -140,6 +140,7 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_PRINTER=m
-- 
1.7.10.4



From csd at broadcom.com  Tue May 14 10:53:24 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 14 May 2013 07:53:24 -0700
Subject: [PATCH] ARM: mach-bcm: drop "select GPIO_BCM"
In-Reply-To: <1368524085.1350.102.camel@x61.thuisdomein>
References: <1368524085.1350.102.camel@x61.thuisdomein>
Message-ID: <51924FE4.5000803@broadcom.com>

On 13-05-14 02:34 AM, Paul Bolle wrote:
> A select statement for the Kconfig symbol GPIO_BCM was added in v3.8.
> But there's no symbol with that name. It's a nop so we can drop it.
>
> Signed-off-by: Paul Bolle <pebolle at tiscali.nl>
> ---
> 0) Untested.
>
> 1) Patch assumes that https://lkml.org/lkml/2013/3/6/182 ("ARM:
> mach-bcm: drop "select GENERIC_TIME""), which got a Reviewed-by tag from
> Christian, was applied first.
>
>   arch/arm/mach-bcm/Kconfig | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index 764273e..322620d 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -8,7 +8,6 @@ config ARCH_BCM
>   	select CPU_V7
>   	select CLKSRC_OF
>   	select GENERIC_CLOCKEVENTS
> -	select GPIO_BCM
>   	select SPARSE_IRQ
>   	select TICK_ONESHOT
>   	help
Hi Paul,
  We are planning on submitting the driver for this option for review 
over the next couple of weeks, to get it in the 3.11 cycle. So this 
patch won't be necessary.

  Thanks,
    csd




From csd at broadcom.com  Tue May 14 10:58:52 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 14 May 2013 07:58:52 -0700
Subject: [PATCH 06/14] ARM: bcm281xx: Remove init_irq declaration in
 machine description
In-Reply-To: <5191F503.2070301@free-electrons.com>
References: <1368438253-28218-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368438253-28218-7-git-send-email-maxime.ripard@free-electrons.com>
 <519147C6.6080004@broadcom.com> <5191F503.2070301@free-electrons.com>
Message-ID: <5192512C.6080006@broadcom.com>

On 13-05-14 01:25 AM, Maxime Ripard wrote:
> Hi Christian,
>
> Le 13/05/2013 22:06, Christian Daudt a ?crit :
>> On 13-05-13 02:44 AM, Maxime Ripard wrote:
>>> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
>>> specified") removed the need to explictly setup the init_irq field in
>>> the machine description when using only irqchip_init. Remove that
>>> declaration for bcm281xx as well.
>>>
>>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>>> ---
>>>    arch/arm/mach-bcm/board_bcm.c | 1 -
>>>    1 file changed, 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-bcm/board_bcm.c
>>> b/arch/arm/mach-bcm/board_bcm.c
>>> index 22e8421..24556cf 100644
>>> --- a/arch/arm/mach-bcm/board_bcm.c
>>> +++ b/arch/arm/mach-bcm/board_bcm.c
>>> @@ -54,7 +54,6 @@ static void __init board_init(void)
>>>    static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351",
>>> NULL, };
>>>      DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
>>> -    .init_irq = irqchip_init,
>>>        .init_time = clocksource_of_init,
>>>        .init_machine = board_init,
>>>        .dt_compat = bcm11351_dt_compat,
>> Acked-by: Christian Daudt <csd at broadcom.com>
> Thanks!
>
> I forgot to remove the include of irqchip.h into all these patches, so
> I'll send a v2, and I guess you could probably merge it through your
> tree after that directly.
Ok. will do.

  thanks,
    csd





From pebolle at tiscali.nl  Tue May 14 10:58:40 2013
From: pebolle at tiscali.nl (Paul Bolle)
Date: Tue, 14 May 2013 16:58:40 +0200
Subject: [PATCH] ARM: mach-bcm: drop "select GPIO_BCM"
In-Reply-To: <51924FE4.5000803@broadcom.com>
References: <1368524085.1350.102.camel@x61.thuisdomein>
 <51924FE4.5000803@broadcom.com>
Message-ID: <1368543520.1350.105.camel@x61.thuisdomein>

On Tue, 2013-05-14 at 07:53 -0700, Christian Daudt wrote:
> We are planning on submitting the driver for this option for review 
> over the next couple of weeks, to get it in the 3.11 cycle. So this 
> patch won't be necessary.

I see. Did my web searches miss something or will that be the first time
you submit that driver for review?

Thanks,


Paul Bolle



From csd at broadcom.com  Tue May 14 11:01:51 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 14 May 2013 08:01:51 -0700
Subject: [PATCH] ARM: mach-bcm: drop "select GPIO_BCM"
In-Reply-To: <1368543520.1350.105.camel@x61.thuisdomein>
References: <1368524085.1350.102.camel@x61.thuisdomein>
 <51924FE4.5000803@broadcom.com>
 <1368543520.1350.105.camel@x61.thuisdomein>
Message-ID: <519251DF.4070809@broadcom.com>

On 13-05-14 07:58 AM, Paul Bolle wrote:
> On Tue, 2013-05-14 at 07:53 -0700, Christian Daudt wrote:
>> We are planning on submitting the driver for this option for review
>> over the next couple of weeks, to get it in the 3.11 cycle. So this
>> patch won't be necessary.
> I see. Did my web searches miss something or will that be the first time
> you submit that driver for review?
Your web searches are correct. The driver was not ready for review at 
the time the initial SoC support was originally submitted, so the config 
should have been removed. It leaked out :)

  thanks,
    csd





From jamie at jamieiles.com  Tue May 14 11:03:16 2013
From: jamie at jamieiles.com (Jamie Iles)
Date: Tue, 14 May 2013 16:03:16 +0100
Subject: [PATCH] picoxcell: remove redundant common.h
Message-ID: <1368543796-19230-1-git-send-email-jamie@jamieiles.com>

We don't need this now - everything lives in common.c so no need for a
separate header.

Signed-off-by: Jamie Iles <jamie at jamieiles.com>
---
 arch/arm/mach-picoxcell/common.c |  2 --
 arch/arm/mach-picoxcell/common.h | 17 -----------------
 2 files changed, 19 deletions(-)
 delete mode 100644 arch/arm/mach-picoxcell/common.h

diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..f6f71bb 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -20,8 +20,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
-
 #define PHYS_TO_IO(x)			(((x) & 0x00ffffff) | 0xfe000000)
 #define PICOXCELL_PERIPH_BASE		0x80000000
 #define PICOXCELL_PERIPH_LENGTH		SZ_4M
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
deleted file mode 100644
index 481b42a..0000000
--- a/arch/arm/mach-picoxcell/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * All enquiries to support at picochip.com
- */
-#ifndef __PICOXCELL_COMMON_H__
-#define __PICOXCELL_COMMON_H__
-
-#include <asm/mach/time.h>
-
-extern void dw_apb_timer_init(void);
-
-#endif /* __PICOXCELL_COMMON_H__ */
-- 
1.8.1.2



From 21cnbao at gmail.com  Tue May 14 11:03:20 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 14 May 2013 23:03:20 +0800
Subject: [PATCH] dmaengine: sirf: set dma residue based on the current dma
 transfer position
Message-ID: <1368543800-20430-1-git-send-email-Baohua.Song@csr.com>

From: Rongjun Ying <Rongjun.Ying at csr.com>

read SIRFSOC_DMA_CH_ADDR register to get current dma transfer position, then
update dma residue so that things like ALSA drivers work as ALSA drivers need
the right residue value.

Signed-off-by: Rongjun Ying <Rongjun.Ying at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/dma/sirf-dma.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 1765a0a..716b23e 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -466,12 +466,29 @@ static enum dma_status
 sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	struct dma_tx_state *txstate)
 {
+	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
 	unsigned long flags;
 	enum dma_status ret;
+	struct sirfsoc_dma_desc *sdesc;
+	int cid = schan->chan.chan_id;
+	unsigned long dma_pos;
+	unsigned long dma_request_bytes;
+	unsigned long residue;
 
 	spin_lock_irqsave(&schan->lock, flags);
+
+	sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
+			node);
+	dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) *
+		(sdesc->width * SIRFSOC_DMA_WORD_LEN);
+
 	ret = dma_cookie_status(chan, cookie, txstate);
+	dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR)
+		<< 2;
+	residue = dma_request_bytes - (dma_pos - sdesc->addr);
+	dma_set_residue(txstate, residue);
+
 	spin_unlock_irqrestore(&schan->lock, flags);
 
 	return ret;
-- 
1.7.4.1



From pebolle at tiscali.nl  Tue May 14 11:07:21 2013
From: pebolle at tiscali.nl (Paul Bolle)
Date: Tue, 14 May 2013 17:07:21 +0200
Subject: [PATCH] ASoC: remove saarb and tavorevb3 machine drivers
Message-ID: <1368544041.1350.111.camel@x61.thuisdomein>

Support for PXA95x was removed in v3.8. This means that the Kconfig
symbols MACH_SAARB and MACH_TAVOREVB3 are no longer available. This
leaves the SoC Audio support for Marvell Saarb and Marvell Tavor EVB3
unbuildable. Remove these drivers too.

Signed-off-by: Paul Bolle <pebolle at tiscali.nl>
---
0) Basically untested.

1) To be specific: it was commit 49ea7fc094 ("ARM: pxa: remove pxa95x
support") that removed MACH_SAARB and MACH_TAVOREVB3.

 sound/soc/pxa/Kconfig     |  20 -----
 sound/soc/pxa/Makefile    |   4 -
 sound/soc/pxa/saarb.c     | 190 ----------------------------------------------
 sound/soc/pxa/tavorevb3.c | 189 ---------------------------------------------
 4 files changed, 403 deletions(-)
 delete mode 100644 sound/soc/pxa/saarb.c
 delete mode 100644 sound/soc/pxa/tavorevb3.c

diff --git a/sound/soc/pxa/Kconfig b/sound/soc/pxa/Kconfig
index 4d2e46f..b358094 100644
--- a/sound/soc/pxa/Kconfig
+++ b/sound/soc/pxa/Kconfig
@@ -130,26 +130,6 @@ config SND_PXA2XX_SOC_PALM27X
 	  Say Y if you want to add support for SoC audio on
 	  Palm T|X, T5, E2 or LifeDrive handheld computer.
 
-config SND_SOC_SAARB
-	tristate "SoC Audio support for Marvell Saarb"
-	depends on SND_PXA2XX_SOC && MACH_SAARB
-	select MFD_88PM860X
-	select SND_PXA_SOC_SSP
-	select SND_SOC_88PM860X
-	help
-	  Say Y if you want to add support for SoC audio on the
-	  Marvell Saarb reference platform.
-
-config SND_SOC_TAVOREVB3
-	tristate "SoC Audio support for Marvell Tavor EVB3"
-	depends on SND_PXA2XX_SOC && MACH_TAVOREVB3
-	select MFD_88PM860X
-	select SND_PXA_SOC_SSP
-	select SND_SOC_88PM860X
-	help
-	  Say Y if you want to add support for SoC audio on the
-	  Marvell Saarb reference platform.
-
 config SND_PXA910_SOC
 	tristate "SoC Audio for Marvell PXA910 chip"
 	depends on ARCH_MMP && SND
diff --git a/sound/soc/pxa/Makefile b/sound/soc/pxa/Makefile
index d8a265d..2cff67b 100644
--- a/sound/soc/pxa/Makefile
+++ b/sound/soc/pxa/Makefile
@@ -23,8 +23,6 @@ snd-soc-e800-objs := e800_wm9712.o
 snd-soc-spitz-objs := spitz.o
 snd-soc-em-x270-objs := em-x270.o
 snd-soc-palm27x-objs := palm27x.o
-snd-soc-saarb-objs := saarb.o
-snd-soc-tavorevb3-objs := tavorevb3.o
 snd-soc-zylonite-objs := zylonite.o
 snd-soc-hx4700-objs := hx4700.o
 snd-soc-magician-objs := magician.o
@@ -48,8 +46,6 @@ obj-$(CONFIG_SND_PXA2XX_SOC_HX4700) += snd-soc-hx4700.o
 obj-$(CONFIG_SND_PXA2XX_SOC_MAGICIAN) += snd-soc-magician.o
 obj-$(CONFIG_SND_PXA2XX_SOC_MIOA701) += snd-soc-mioa701.o
 obj-$(CONFIG_SND_PXA2XX_SOC_Z2) += snd-soc-z2.o
-obj-$(CONFIG_SND_SOC_SAARB) += snd-soc-saarb.o
-obj-$(CONFIG_SND_SOC_TAVOREVB3) += snd-soc-tavorevb3.o
 obj-$(CONFIG_SND_SOC_ZYLONITE) += snd-soc-zylonite.o
 obj-$(CONFIG_SND_PXA2XX_SOC_IMOTE2) += snd-soc-imote2.o
 obj-$(CONFIG_SND_SOC_RAUMFELD) += snd-soc-raumfeld.o
diff --git a/sound/soc/pxa/saarb.c b/sound/soc/pxa/saarb.c
deleted file mode 100644
index c34146b..0000000
--- a/sound/soc/pxa/saarb.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * saarb.c -- SoC audio for saarb
- *
- * Copyright (C) 2010 Marvell International Ltd.
- * 	Haojian Zhuang <haojian.zhuang at marvell.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/soc.h>
-#include <sound/jack.h>
-
-#include <asm/mach-types.h>
-
-#include "../codecs/88pm860x-codec.h"
-#include "pxa-ssp.h"
-
-static int saarb_pm860x_init(struct snd_soc_pcm_runtime *rtd);
-
-static struct platform_device *saarb_snd_device;
-
-static struct snd_soc_jack hs_jack, mic_jack;
-
-static struct snd_soc_jack_pin hs_jack_pins[] = {
-	{ .pin = "Headset Stereophone",	.mask = SND_JACK_HEADPHONE, },
-};
-
-static struct snd_soc_jack_pin mic_jack_pins[] = {
-	{ .pin = "Headset Mic 2",	.mask = SND_JACK_MICROPHONE, },
-};
-
-/* saarb machine dapm widgets */
-static const struct snd_soc_dapm_widget saarb_dapm_widgets[] = {
-	SND_SOC_DAPM_HP("Headphone Stereophone", NULL),
-	SND_SOC_DAPM_LINE("Lineout Out 1", NULL),
-	SND_SOC_DAPM_LINE("Lineout Out 2", NULL),
-	SND_SOC_DAPM_SPK("Ext Speaker", NULL),
-	SND_SOC_DAPM_MIC("Ext Mic 1", NULL),
-	SND_SOC_DAPM_MIC("Headset Mic", NULL),
-	SND_SOC_DAPM_MIC("Ext Mic 3", NULL),
-};
-
-/* saarb machine audio map */
-static const struct snd_soc_dapm_route saarb_audio_map[] = {
-	{"Headset Stereophone", NULL, "HS1"},
-	{"Headset Stereophone", NULL, "HS2"},
-
-	{"Ext Speaker", NULL, "LSP"},
-	{"Ext Speaker", NULL, "LSN"},
-
-	{"Lineout Out 1", NULL, "LINEOUT1"},
-	{"Lineout Out 2", NULL, "LINEOUT2"},
-
-	{"MIC1P", NULL, "Mic1 Bias"},
-	{"MIC1N", NULL, "Mic1 Bias"},
-	{"Mic1 Bias", NULL, "Ext Mic 1"},
-
-	{"MIC2P", NULL, "Mic1 Bias"},
-	{"MIC2N", NULL, "Mic1 Bias"},
-	{"Mic1 Bias", NULL, "Headset Mic 2"},
-
-	{"MIC3P", NULL, "Mic3 Bias"},
-	{"MIC3N", NULL, "Mic3 Bias"},
-	{"Mic3 Bias", NULL, "Ext Mic 3"},
-};
-
-static int saarb_i2s_hw_params(struct snd_pcm_substream *substream,
-				struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-	int width = snd_pcm_format_physical_width(params_format(params));
-	int ret;
-
-	ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_NET_PLL, 0,
-				     PM860X_CLK_DIR_OUT);
-	if (ret < 0)
-		return ret;
-
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 0, PM860X_CLK_DIR_OUT);
-	if (ret < 0)
-		return ret;
-
-	ret = snd_soc_dai_set_tdm_slot(cpu_dai, 3, 3, 2, width);
-
-	return ret;
-}
-
-static struct snd_soc_ops saarb_i2s_ops = {
-	.hw_params	= saarb_i2s_hw_params,
-};
-
-static struct snd_soc_dai_link saarb_dai[] = {
-	{
-		.name		= "88PM860x I2S",
-		.stream_name	= "I2S Audio",
-		.cpu_dai_name	= "pxa-ssp-dai.1",
-		.codec_dai_name	= "88pm860x-i2s",
-		.platform_name	= "pxa-pcm-audio",
-		.codec_name	= "88pm860x-codec",
-		.init		= saarb_pm860x_init,
-		.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-				  SND_SOC_DAIFMT_CBM_CFM,
-		.ops		= &saarb_i2s_ops,
-	},
-};
-
-static struct snd_soc_card snd_soc_card_saarb = {
-	.name = "Saarb",
-	.owner = THIS_MODULE,
-	.dai_link = saarb_dai,
-	.num_links = ARRAY_SIZE(saarb_dai),
-
-	.dapm_widgets = saarb_dapm_widgets,
-	.num_dapm_widgets = ARRAY_SIZE(saarb_dapm_widgets),
-	.dapm_routes = saarb_audio_map,
-	.num_dapm_routes = ARRAY_SIZE(saarb_audio_map),
-};
-
-static int saarb_pm860x_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_codec *codec = rtd->codec;
-	struct snd_soc_dapm_context *dapm = &codec->dapm;
-
-	/* connected pins */
-	snd_soc_dapm_enable_pin(dapm, "Ext Speaker");
-	snd_soc_dapm_enable_pin(dapm, "Ext Mic 1");
-	snd_soc_dapm_enable_pin(dapm, "Ext Mic 3");
-	snd_soc_dapm_disable_pin(dapm, "Headset Mic 2");
-	snd_soc_dapm_disable_pin(dapm, "Headset Stereophone");
-
-	/* Headset jack detection */
-	snd_soc_jack_new(codec, "Headphone Jack", SND_JACK_HEADPHONE
-			| SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
-			&hs_jack);
-	snd_soc_jack_add_pins(&hs_jack, ARRAY_SIZE(hs_jack_pins),
-			      hs_jack_pins);
-	snd_soc_jack_new(codec, "Microphone Jack", SND_JACK_MICROPHONE,
-			 &mic_jack);
-	snd_soc_jack_add_pins(&mic_jack, ARRAY_SIZE(mic_jack_pins),
-			      mic_jack_pins);
-
-	/* headphone, microphone detection & headset short detection */
-	pm860x_hs_jack_detect(codec, &hs_jack, SND_JACK_HEADPHONE,
-			      SND_JACK_BTN_0, SND_JACK_BTN_1, SND_JACK_BTN_2);
-	pm860x_mic_jack_detect(codec, &hs_jack, SND_JACK_MICROPHONE);
-	return 0;
-}
-
-static int __init saarb_init(void)
-{
-	int ret;
-
-	if (!machine_is_saarb())
-		return -ENODEV;
-	saarb_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!saarb_snd_device)
-		return -ENOMEM;
-
-	platform_set_drvdata(saarb_snd_device, &snd_soc_card_saarb);
-
-	ret = platform_device_add(saarb_snd_device);
-	if (ret)
-		platform_device_put(saarb_snd_device);
-
-	return ret;
-}
-
-static void __exit saarb_exit(void)
-{
-	platform_device_unregister(saarb_snd_device);
-}
-
-module_init(saarb_init);
-module_exit(saarb_exit);
-
-MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang at marvell.com>");
-MODULE_DESCRIPTION("ALSA SoC 88PM860x Saarb");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/pxa/tavorevb3.c b/sound/soc/pxa/tavorevb3.c
deleted file mode 100644
index 8b5ab8f..0000000
--- a/sound/soc/pxa/tavorevb3.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * tavorevb3.c -- SoC audio for Tavor EVB3
- *
- * Copyright (C) 2010 Marvell International Ltd.
- * 	Haojian Zhuang <haojian.zhuang at marvell.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/soc.h>
-#include <sound/jack.h>
-
-#include <asm/mach-types.h>
-
-#include "../codecs/88pm860x-codec.h"
-#include "pxa-ssp.h"
-
-static int evb3_pm860x_init(struct snd_soc_pcm_runtime *rtd);
-
-static struct platform_device *evb3_snd_device;
-
-static struct snd_soc_jack hs_jack, mic_jack;
-
-static struct snd_soc_jack_pin hs_jack_pins[] = {
-	{ .pin = "Headset Stereophone",	.mask = SND_JACK_HEADPHONE, },
-};
-
-static struct snd_soc_jack_pin mic_jack_pins[] = {
-	{ .pin = "Headset Mic 2",	.mask = SND_JACK_MICROPHONE, },
-};
-
-/* tavorevb3 machine dapm widgets */
-static const struct snd_soc_dapm_widget evb3_dapm_widgets[] = {
-	SND_SOC_DAPM_HP("Headset Stereophone", NULL),
-	SND_SOC_DAPM_LINE("Lineout Out 1", NULL),
-	SND_SOC_DAPM_LINE("Lineout Out 2", NULL),
-	SND_SOC_DAPM_SPK("Ext Speaker", NULL),
-	SND_SOC_DAPM_MIC("Ext Mic 1", NULL),
-	SND_SOC_DAPM_MIC("Headset Mic 2", NULL),
-	SND_SOC_DAPM_MIC("Ext Mic 3", NULL),
-};
-
-/* tavorevb3 machine audio map */
-static const struct snd_soc_dapm_route evb3_audio_map[] = {
-	{"Headset Stereophone", NULL, "HS1"},
-	{"Headset Stereophone", NULL, "HS2"},
-
-	{"Ext Speaker", NULL, "LSP"},
-	{"Ext Speaker", NULL, "LSN"},
-
-	{"Lineout Out 1", NULL, "LINEOUT1"},
-	{"Lineout Out 2", NULL, "LINEOUT2"},
-
-	{"MIC1P", NULL, "Mic1 Bias"},
-	{"MIC1N", NULL, "Mic1 Bias"},
-	{"Mic1 Bias", NULL, "Ext Mic 1"},
-
-	{"MIC2P", NULL, "Mic1 Bias"},
-	{"MIC2N", NULL, "Mic1 Bias"},
-	{"Mic1 Bias", NULL, "Headset Mic 2"},
-
-	{"MIC3P", NULL, "Mic3 Bias"},
-	{"MIC3N", NULL, "Mic3 Bias"},
-	{"Mic3 Bias", NULL, "Ext Mic 3"},
-};
-
-static int evb3_i2s_hw_params(struct snd_pcm_substream *substream,
-			      struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-	int width = snd_pcm_format_physical_width(params_format(params));
-	int ret;
-
-	ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_NET_PLL, 0,
-				     PM860X_CLK_DIR_OUT);
-	if (ret < 0)
-		return ret;
-
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 0, PM860X_CLK_DIR_OUT);
-	if (ret < 0)
-		return ret;
-
-	ret = snd_soc_dai_set_tdm_slot(cpu_dai, 3, 3, 2, width);
-	return ret;
-}
-
-static struct snd_soc_ops evb3_i2s_ops = {
-	.hw_params	= evb3_i2s_hw_params,
-};
-
-static struct snd_soc_dai_link evb3_dai[] = {
-	{
-		.name		= "88PM860x I2S",
-		.stream_name	= "I2S Audio",
-		.cpu_dai_name	= "pxa-ssp-dai.1",
-		.codec_dai_name	= "88pm860x-i2s",
-		.platform_name	= "pxa-pcm-audio",
-		.codec_name	= "88pm860x-codec",
-		.init		= evb3_pm860x_init,
-		.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-				  SND_SOC_DAIFMT_CBM_CFM,
-		.ops		= &evb3_i2s_ops,
-	},
-};
-
-static struct snd_soc_card snd_soc_card_evb3 = {
-	.name = "Tavor EVB3",
-	.owner = THIS_MODULE,
-	.dai_link = evb3_dai,
-	.num_links = ARRAY_SIZE(evb3_dai),
-
-	.dapm_widgets = evb3_dapm_widgets,
-	.num_dapm_widgets = ARRAY_SIZE(evb3_dapm_widgets),
-	.dapm_routes = evb3_audio_map,
-	.num_dapm_routes = ARRAY_SIZE(evb3_audio_map),
-};
-
-static int evb3_pm860x_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_codec *codec = rtd->codec;
-	struct snd_soc_dapm_context *dapm = &codec->dapm;
-
-	/* connected pins */
-	snd_soc_dapm_enable_pin(dapm, "Ext Speaker");
-	snd_soc_dapm_enable_pin(dapm, "Ext Mic 1");
-	snd_soc_dapm_enable_pin(dapm, "Ext Mic 3");
-	snd_soc_dapm_disable_pin(dapm, "Headset Mic 2");
-	snd_soc_dapm_disable_pin(dapm, "Headset Stereophone");
-
-	/* Headset jack detection */
-	snd_soc_jack_new(codec, "Headphone Jack", SND_JACK_HEADPHONE
-			| SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
-			&hs_jack);
-	snd_soc_jack_add_pins(&hs_jack, ARRAY_SIZE(hs_jack_pins),
-			      hs_jack_pins);
-	snd_soc_jack_new(codec, "Microphone Jack", SND_JACK_MICROPHONE,
-			 &mic_jack);
-	snd_soc_jack_add_pins(&mic_jack, ARRAY_SIZE(mic_jack_pins),
-			      mic_jack_pins);
-
-	/* headphone, microphone detection & headset short detection */
-	pm860x_hs_jack_detect(codec, &hs_jack, SND_JACK_HEADPHONE,
-			      SND_JACK_BTN_0, SND_JACK_BTN_1, SND_JACK_BTN_2);
-	pm860x_mic_jack_detect(codec, &hs_jack, SND_JACK_MICROPHONE);
-	return 0;
-}
-
-static int __init tavorevb3_init(void)
-{
-	int ret;
-
-	if (!machine_is_tavorevb3())
-		return -ENODEV;
-	evb3_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!evb3_snd_device)
-		return -ENOMEM;
-
-	platform_set_drvdata(evb3_snd_device, &snd_soc_card_evb3);
-
-	ret = platform_device_add(evb3_snd_device);
-	if (ret)
-		platform_device_put(evb3_snd_device);
-
-	return ret;
-}
-
-static void __exit tavorevb3_exit(void)
-{
-	platform_device_unregister(evb3_snd_device);
-}
-
-module_init(tavorevb3_init);
-module_exit(tavorevb3_exit);
-
-MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang at marvell.com>");
-MODULE_DESCRIPTION("ALSA SoC 88PM860x Tavor EVB3");
-MODULE_LICENSE("GPL");
-- 
1.7.11.7



From robherring2 at gmail.com  Tue May 14 11:07:23 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 14 May 2013 10:07:23 -0500
Subject: [PATCH v2 1/3] ARM: allow platforms to use generic headers without
 ARCH_MULTIPLATFORM
In-Reply-To: <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
 <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>
Message-ID: <5192532B.1070705@gmail.com>

On 05/14/2013 06:27 AM, Jonathan Austin wrote:
> Currently the use of generic mach headers is only is controlled by the same
> config option as selection of a multiplatform kernel (i.e.
> ARCH_MULTIPLATFORM). However, there are cases where it is valid to use the
> generic headers but still build a single platform kernel.
> 
> One such example is when using the vexpress platform with a core that does
> not have an MMU; a multiplatform kernel does not make sense, but use of the
> generic headers is required by the vexpress platform since 617276307cd4c
> ("ARM: vexpress: convert to multi-platform").
> 
> This patch untangles these two options by introducing a new
> ARM_GENERIC_HEADERS config option that ARCH_MULTIPLATFORM selects. Other
> platforms can now select ARM_GENERIC_HEADERS independently.

I find this name confusing. It is no headers you are selecting and
generic is a bit overused IMHO. So how about something like
NEED_NO_MACH_HEADERS to somewhat align to the other header related
config options (e.g. NEED_MACH_GPIO_H).

Rob

> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
> CC: Rob Herring <rob.herring at calxeda.com>
> CC: Pawel Moll <pawel.moll at arm.com>
> CC: Jason Cooper <jason at lakedaemon.net>
> CC: Andrew Lunn <andrew at lunn.ch>
> CC: Gregory Clement <gregory.clement at free-electrons.com>
> CC: Tony Lindgren <tony at atomide.com>
> CC: Stephen Boyd <sboyd at codeaurora.org>
> CC: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/Kconfig                 |    4 ++++
>  arch/arm/Kconfig.debug           |    4 ++--
>  arch/arm/Makefile                |    2 +-
>  arch/arm/include/asm/timex.h     |    2 +-
>  arch/arm/mach-mvebu/Makefile     |    2 +-
>  arch/arm/mach-omap2/Makefile     |    2 +-
>  arch/arm/mach-vexpress/Makefile  |    2 +-
>  arch/arm/plat-omap/Makefile      |    2 +-
>  arch/arm/plat-orion/Makefile     |    2 +-
>  arch/arm/plat-versatile/Makefile |    2 +-
>  10 files changed, 14 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d423d58..408eb33 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -206,6 +206,9 @@ config NEED_RET_TO_USER
>  config ARCH_MTD_XIP
>  	bool
>  
> +config ARM_GENERIC_HEADERS
> +	bool
> +
>  config VECTORS_BASE
>  	hex
>  	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
> @@ -295,6 +298,7 @@ config ARCH_MULTIPLATFORM
>  	select MULTI_IRQ_HANDLER
>  	select SPARSE_IRQ
>  	select USE_OF
> +	select ARM_GENERIC_HEADERS
>  
>  config ARCH_INTEGRATOR
>  	bool "ARM Ltd. Integrator family"
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 1d41908..ede909b 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -652,13 +652,13 @@ config DEBUG_LL_INCLUDE
>  
>  config DEBUG_UNCOMPRESS
>  	bool
> -	default y if ARCH_MULTIPLATFORM && DEBUG_LL && \
> +	default y if ARM_GENERIC_HEADERS && DEBUG_LL && \
>  		     !DEBUG_OMAP2PLUS_UART && \
>  		     !DEBUG_TEGRA_UART
>  
>  config UNCOMPRESS_INCLUDE
>  	string
> -	default "debug/uncompress.h" if ARCH_MULTIPLATFORM
> +	default "debug/uncompress.h" if ARM_GENERIC_HEADERS
>  	default "mach/uncompress.h"
>  
>  config EARLY_PRINTK
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 4737408..ab0416f 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -229,7 +229,7 @@ endif
>  machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>  platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
>  
> -ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
> +ifneq ($(CONFIG_ARM_GENERIC_HEADERS),y)
>  ifeq ($(KBUILD_SRC),)
>  KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
>  else
> diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
> index 83f2aa8..586a9c2 100644
> --- a/arch/arm/include/asm/timex.h
> +++ b/arch/arm/include/asm/timex.h
> @@ -12,7 +12,7 @@
>  #ifndef _ASMARM_TIMEX_H
>  #define _ASMARM_TIMEX_H
>  
> -#ifdef CONFIG_ARCH_MULTIPLATFORM
> +#ifdef CONFIG_ARM_GENERIC_HEADERS
>  #define CLOCK_TICK_RATE 1000000
>  #else
>  #include <mach/timex.h>
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> index 2d04f0e..d3c0e0b 100644
> --- a/arch/arm/mach-mvebu/Makefile
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -1,4 +1,4 @@
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
>  	-I$(srctree)/arch/arm/plat-orion/include
>  
>  AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 55a9d67..ab204bc 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -2,7 +2,7 @@
>  # Makefile for the linux kernel.
>  #
>  
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
>  	-I$(srctree)/arch/arm/plat-omap/include
>  
>  # Common support
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 42703e8..6768e7f 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -1,7 +1,7 @@
>  #
>  # Makefile for the linux kernel.
>  #
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
>  	-I$(srctree)/arch/arm/plat-versatile/include
>  
>  obj-y					:= v2m.o
> diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
> index 3119941..3e1ba10 100644
> --- a/arch/arm/plat-omap/Makefile
> +++ b/arch/arm/plat-omap/Makefile
> @@ -2,7 +2,7 @@
>  # Makefile for the linux kernel.
>  #
>  
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/arch/arm/plat-omap/include
>  
>  # Common support
>  obj-y := sram.o dma.o counter_32k.o
> diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
> index 9433605..79a042ed 100644
> --- a/arch/arm/plat-orion/Makefile
> +++ b/arch/arm/plat-orion/Makefile
> @@ -1,7 +1,7 @@
>  #
>  # Makefile for the linux kernel.
>  #
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include
>  
>  orion-gpio-$(CONFIG_GPIOLIB)      += gpio.o
>  obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
> diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
> index f88d448..19495c6 100644
> --- a/arch/arm/plat-versatile/Makefile
> +++ b/arch/arm/plat-versatile/Makefile
> @@ -1,4 +1,4 @@
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include
>  
>  obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
>  obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
> 



From gregory.clement at free-electrons.com  Tue May 14 11:28:42 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 14 May 2013 17:28:42 +0200
Subject: [PATCH][For 3.10-rc] ARM: zImage: Handle the case with 32bits memory
 size and address from ATAG and 64bits DTB
Message-ID: <1368545323-3621-1-git-send-email-gregory.clement@free-electrons.com>

Hello,

Memory description in the Armada XP based boards device tree files
have been converted to 64 bit in order to handle more than 4GB when
LPAE is activated. However most of these platforms still use old
bootloaders (ie not DT compatible) and the kernel hangs when it is
configured with CONFIG_ARM_APPENDED_DTB.

The problem was a bad conversion from 32bit ATAG information to 64bits
device tree information.

The following patch fix this bug and it is a 3.10-rc material.

Regards,

Gregory CLEMENT (1):
  ARM: zImage: Convert 32bits memory size and address from ATAG to
    64bits DTB

 arch/arm/boot/compressed/atags_to_fdt.c | 44 ++++++++++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 6 deletions(-)

-- 
1.8.1.2



From gregory.clement at free-electrons.com  Tue May 14 11:28:43 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 14 May 2013 17:28:43 +0200
Subject: [PATCH] ARM: zImage: Convert 32bits memory size and address from ATAG
 to 64bits DTB
In-Reply-To: <1368545323-3621-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368545323-3621-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368545323-3621-2-git-send-email-gregory.clement@free-electrons.com>

When CONFIG_ARM_APPENDED_DTB is selected, if the bootloader provides
an ATAG_MEM it replaces the memory size and the memory address in the
memory node of the device tree. In the case of a system which can
handle more than 4GB, the memory node cell size is 4: each data
(memory size and memory address) are 64 bits and then use 2 cells.

The current code in atags_to_fdt.c made the assumption of a cell size
of 2 (one cell for the memory size and one cell for the memory
address), this leads to an improper write of the data and ends with a
boot hang.

This patch writes the memory size and the memory address on the memory
node in the device tree depending of the size of the memory node (32
bits or 64 bits).

It has been tested in the 2 cases:
- with a dtb using skeleton.dtsi
- and with a dtb using skeleton64.dtsi

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/compressed/atags_to_fdt.c | 44 ++++++++++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index aabc02a..d1153c8 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path,
 	return fdt_getprop(fdt, offset, property, len);
 }
 
+static uint32_t get_cell_size(const void *fdt)
+{
+	int len;
+	uint32_t cell_size = 1;
+	const uint32_t *size_len =  getprop(fdt, "/", "#size-cells", &len);
+
+	if (size_len)
+		cell_size = fdt32_to_cpu(*size_len);
+	return cell_size;
+}
+
 static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 {
 	char cmdline[COMMAND_LINE_SIZE];
@@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 {
 	struct tag *atag = atag_list;
-	uint32_t mem_reg_property[2 * NR_BANKS];
+	/* In the case of 64 bits memory size, need to reserve 2 cells for
+	 * address and size for each bank */
+	uint32_t mem_reg_property[2 * 2 * NR_BANKS];
 	int memcount = 0;
-	int ret;
+	int ret, memsize;
 
 	/* make sure we've got an aligned pointer */
 	if ((u32)atag_list & 0x3)
@@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 				continue;
 			if (!atag->u.mem.size)
 				continue;
-			mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
-			mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
+			memsize = get_cell_size(fdt);
+
+			if (memsize == 2) {
+				/* if memsize is 2, that means that
+				 * each data needs 2 cells of 32 bits,
+				 * so the data are 64 bits */
+				uint64_t *mem_reg_prop64 =
+					(uint64_t *)mem_reg_property;
+				mem_reg_prop64[memcount++] =
+					cpu_to_fdt64(atag->u.mem.start);
+				mem_reg_prop64[memcount++] =
+					cpu_to_fdt64(atag->u.mem.size);
+			} else {
+				mem_reg_property[memcount++] =
+					cpu_to_fdt32(atag->u.mem.start);
+				mem_reg_property[memcount++] =
+					cpu_to_fdt32(atag->u.mem.size);
+			}
+
 		} else if (atag->hdr.tag == ATAG_INITRD2) {
 			uint32_t initrd_start, initrd_size;
 			initrd_start = atag->u.initrd.start;
@@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 		}
 	}
 
-	if (memcount)
-		setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
+	if (memcount) {
+		setprop(fdt, "/memory", "reg", mem_reg_property,
+			4 * memcount * memsize);
+	}
 
 	return fdt_pack(fdt);
 }
-- 
1.8.1.2



From laurent.pinchart at ideasonboard.com  Tue May 14 11:31:14 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 14 May 2013 17:31:14 +0200
Subject: [PATCH 2/3] ARM: shmobile: r8a7790: Configure R-Car GPIO for
 IRQ_TYPE_EDGE_BOTH
In-Reply-To: <CANqRtoR_BGFo+GRgom2WqXnaGtoB1T90S=twO_4G_t-JE8roTQ@mail.gmail.com>
References: <1368435233-8587-1-git-send-email-horms+renesas@verge.net.au>
 <20130514024034.GA20239@verge.net.au>
 <CANqRtoR_BGFo+GRgom2WqXnaGtoB1T90S=twO_4G_t-JE8roTQ@mail.gmail.com>
Message-ID: <1536782.qkoVNXIpLR@avalon>

Hi Magnus,

On Tuesday 14 May 2013 15:01:01 Magnus Damm wrote:
> On Tue, May 14, 2013 at 11:40 AM, Simon Horman <horms at verge.net.au> wrote:
> > On Tue, May 14, 2013 at 12:33:42AM +0200, Laurent Pinchart wrote:
> >> Hi Simon,
> >> 
> >> On Monday 13 May 2013 17:53:52 Simon Horman wrote:
> >> > "gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
> >> > driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
> >> > not universal for all SoCs a flag, has_both_edge_trigger, has been
> >> > added to the platform data of the driver to allow this feature to be
> >> > enabled.
> >> 
> >> What about moving this information to a platform ID table in the
> >> gpio-rcar driver ?
> > 
> > Magnus, do you have an opinion on this?
> 
> I don't mind so much as long as we:
> a) can control things freely per driver instance
> and
> b) don't have to update all drivers for every new SoC
> 
> The current approach allows for that, so as an example if we can have
> two slightly different GPIO hardware blocks then we can setup two GPIO
> controller driver instances where the configuration can be selected
> per-instance. Perhaps Laurent's proposal would allow for this too, I'm
> not sure.

I agree that parameters related to the instantiation of a GPIO IP core in a 
SoC should come from DT. Parameters related to the IP core version (usch as 
the ability to trigger on both edges) should in my opinion be computed by the 
GPIO driver based on the IP core version number.

> On top of that I'd like to avoid doing per-SoC string matching in drivers.
> Those would force us to update every darn driver for every new SoC. It is
> better to try to use a per-hardware device version in the drivers and then
> configure each SoC to use the appropriate version.

Agreed. Are the version numbers for the GPIO IP core available ?

-- 
Regards,

Laurent Pinchart



From maxime.ripard at free-electrons.com  Tue May 14 11:38:35 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:35 +0200
Subject: [PATCH 02/20] ARM: zynq: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-3-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for zynq as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Michal Simek <monstr at monstr.eu>
---
 arch/arm/mach-zynq/common.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5bfe703..4c0199b8 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -25,7 +25,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
-#include <linux/irqchip.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -106,7 +105,6 @@ static const char * const zynq_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
 	.smp		= smp_ops(zynq_smp_ops),
 	.map_io		= zynq_map_io,
-	.init_irq	= irqchip_init,
 	.init_machine	= zynq_init_machine,
 	.init_time	= zynq_timer_init,
 	.dt_compat	= zynq_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:37 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:37 +0200
Subject: [PATCH 04/20] ARM: picoxcell: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-5-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for picoxcell as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Jamie Iles <jamie at jamieiles.com>
---
 arch/arm/mach-picoxcell/common.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..c2721ce 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -9,7 +9,6 @@
  */
 #include <linux/delay.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -87,7 +86,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
 	.map_io		= picoxcell_map_io,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_time	= dw_apb_timer_init,
 	.init_machine	= picoxcell_init_machine,
 	.dt_compat	= picoxcell_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:36 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:36 +0200
Subject: [PATCH 03/20] ARM: nomadik: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-4-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for nomadik as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-nomadik/cpu-8815.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..46cce9b 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -25,7 +25,6 @@
 #include <linux/slab.h>
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
-#include <linux/irqchip.h>
 #include <linux/platform_data/clk-nomadik.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/pinctrl/machine.h>
@@ -323,7 +322,6 @@ static const char * cpu8815_board_compat[] = {
 
 DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
 	.map_io		= cpu8815_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= cpu8815_timer_init_of,
 	.init_machine	= cpu8815_init_of,
 	.restart	= cpu8815_restart,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:34 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:34 +0200
Subject: [PATCH 01/20] ARM: sunxi: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-2-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for sunxi as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-sunxi/sunxi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..08937a3 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -14,7 +14,6 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -117,7 +116,6 @@ static const char * const sunxi_board_dt_compat[] = {
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
 	.init_machine	= sunxi_dt_init,
 	.map_io		= sunxi_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sunxi_timer_init,
 	.dt_compat	= sunxi_board_dt_compat,
 MACHINE_END
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:33 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:33 +0200
Subject: [PATCHv2 00/20] Cleanup irqchip_init calls
Message-ID: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>

Hi everyone,

This is a splitted up version of the patch I previously sent to
remove the explicit declaration of irqchip_init as the init_irq callback in
the machine descriptions.

Since it was a pretty tricky patch to merge, since it was touching a lot of
different platforms, I splitted it for each platforms, and rebased it on top
of 3.10-rc1.

The best way to merge it is probably that each one of us take into their tree
the patches that are relevant for our architecture and send them to arm-soc
later on.

Thanks,
Maxime

Changes from v1:
  - Removed the dead include of linux/irqchip.h
  - Splitted the shmobile changes into several patches

Maxime Ripard (20):
  ARM: sunxi: Remove init_irq declaration in machine description
  ARM: zynq: Remove init_irq declaration in machine description
  ARM: nomadik: Remove init_irq declaration in machine description
  ARM: picoxcell: Remove init_irq declaration in machine description
  ARM: shmobile: ape6evm: Remove init_irq declaration in machine
    description
  ARM: shmobile: kzm9g: Remove init_irq declaration in machine
    description
  ARM: shmobile: lager: Remove init_irq declaration in machine
    description
  ARM: shmobile: emev2: Remove init_irq declaration in machine
    description
  ARM: shmobile: r8a73a4: Remove init_irq declaration in machine
    description
  ARM: shmobile: r8a7790: Remove init_irq declaration in machine
    description
  ARM: shmobile: sh73a0: Remove init_irq declaration in machine
    description
  ARM: bcm281xx: Remove init_irq declaration in machine description
  ARM: spear: Remove init_irq declaration in machine description
  ARM: msm: Remove init_irq declaration in machine description
  ARM: mvebu: Remove init_irq declaration in machine description
  ARM: mxs: Remove init_irq declaration in machine description
  ARM: sirf: Remove init_irq declaration in machine description
  ARM: vexpress: Remove init_irq declaration in machine description
  ARM: virt: Remove init_irq declaration in machine description
  ARM: vt8500: Remove init_irq declaration in machine description

 arch/arm/mach-bcm/board_bcm.c                  | 2 --
 arch/arm/mach-msm/board-dt-8660.c              | 2 --
 arch/arm/mach-msm/board-dt-8960.c              | 2 --
 arch/arm/mach-mvebu/armada-370-xp.c            | 2 --
 arch/arm/mach-mxs/mach-mxs.c                   | 2 --
 arch/arm/mach-nomadik/cpu-8815.c               | 2 --
 arch/arm/mach-picoxcell/common.c               | 2 --
 arch/arm/mach-prima2/common.c                  | 4 ----
 arch/arm/mach-shmobile/board-ape6evm.c         | 2 --
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 2 --
 arch/arm/mach-shmobile/board-lager.c           | 2 --
 arch/arm/mach-shmobile/setup-emev2.c           | 2 --
 arch/arm/mach-shmobile/setup-r8a73a4.c         | 2 --
 arch/arm/mach-shmobile/setup-r8a7790.c         | 2 --
 arch/arm/mach-shmobile/setup-sh73a0.c          | 2 --
 arch/arm/mach-spear/spear1310.c                | 2 --
 arch/arm/mach-spear/spear1340.c                | 2 --
 arch/arm/mach-spear/spear300.c                 | 2 --
 arch/arm/mach-spear/spear310.c                 | 2 --
 arch/arm/mach-spear/spear320.c                 | 2 --
 arch/arm/mach-spear/spear6xx.c                 | 2 --
 arch/arm/mach-sunxi/sunxi.c                    | 2 --
 arch/arm/mach-vexpress/v2m.c                   | 2 --
 arch/arm/mach-virt/virt.c                      | 2 --
 arch/arm/mach-vt8500/vt8500.c                  | 2 --
 arch/arm/mach-zynq/common.c                    | 2 --
 26 files changed, 54 deletions(-)

-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:39 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:39 +0200
Subject: [PATCH 06/20] ARM: shmobile: kzm9g: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-7-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d..b7ee96e 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -24,7 +24,6 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
@@ -100,7 +99,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
 	.map_io		= sh73a0_map_io,
 	.init_early	= sh73a0_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= kzm_init,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= kzm9g_boards_compat_dt,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:41 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:41 +0200
Subject: [PATCH 08/20] ARM: shmobile: emev2: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-9-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/setup-emev2.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 899a86c..66694e0 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,7 +20,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/gpio-em.h>
 #include <linux/of_platform.h>
@@ -454,7 +453,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
 	.smp		= smp_ops(emev2_smp_ops),
 	.init_early	= emev2_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= emev2_add_standard_devices_dt,
 	.dt_compat	= emev2_boards_compat_dt,
 MACHINE_END
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:49 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:49 +0200
Subject: [PATCH 16/20] ARM: mxs: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-17-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for mxs as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..66fe810 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -19,7 +19,6 @@
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/irqchip/mxs.h>
 #include <linux/micrel_phy.h>
 #include <linux/of_address.h>
@@ -435,7 +434,6 @@ static const char *mxs_dt_compat[] __initdata = {
 
 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
 	.map_io		= debug_ll_io_init,
-	.init_irq	= irqchip_init,
 	.handle_irq	= icoll_handle_irq,
 	.init_time	= mxs_timer_init,
 	.init_machine	= mxs_machine_init,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:42 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:42 +0200
Subject: [PATCH 09/20] ARM: shmobile: r8a73a4: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-10-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/setup-r8a73a4.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c5a75a7..0b78896 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
@@ -194,7 +193,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
-	.init_irq	= irqchip_init,
 	.init_machine	= r8a73a4_add_standard_devices_dt,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= r8a73a4_boards_compat_dt,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:40 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:40 +0200
Subject: [PATCH 07/20] ARM: shmobile: lager: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-8-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/board-lager.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187..b7488b8 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -19,7 +19,6 @@
  */
 
 #include <linux/interrupt.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
@@ -39,7 +38,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
-	.init_irq	= irqchip_init,
 	.init_time	= r8a7790_timer_init,
 	.init_machine	= lager_add_standard_devices,
 	.dt_compat	= lager_boards_compat_dt,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:44 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:44 +0200
Subject: [PATCH 11/20] ARM: shmobile: sh73a0: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-12-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/setup-sh73a0.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..73dd75b 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,7 +22,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -1035,7 +1034,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 	.map_io		= sh73a0_map_io,
 	.init_early	= sh73a0_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= sh73a0_add_standard_devices_dt,
 	.dt_compat	= sh73a0_boards_compat_dt,
 MACHINE_END
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:48 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:48 +0200
Subject: [PATCH 15/20] ARM: mvebu: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-16-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for mvebu as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-mvebu/armada-370-xp.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3..c04fed8 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -20,7 +20,6 @@
 #include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
-#include <linux/irqchip.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -96,7 +95,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
 	.init_machine	= armada_370_xp_dt_init,
 	.map_io		= armada_370_xp_map_io,
 	.init_early	= armada_370_xp_init_early,
-	.init_irq	= irqchip_init,
 	.init_time	= armada_370_xp_timer_and_clk_init,
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_370_xp_dt_compat,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:50 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:50 +0200
Subject: [PATCH 17/20] ARM: sirf: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-18-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for sirf as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/mach-prima2/common.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd8..a9f475c 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -9,7 +9,6 @@
 #include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/irqchip.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -55,7 +54,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.nr_irqs	= 128,
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
@@ -74,7 +72,6 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.nr_irqs	= 128,
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
@@ -94,7 +91,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.smp            = smp_ops(sirfsoc_smp_ops),
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:45 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:45 +0200
Subject: [PATCH 12/20] ARM: bcm281xx: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-13-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for bcm281xx as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Christian Daudt <csd at broadcom.com>
---
 arch/arm/mach-bcm/board_bcm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
index 22e8421..2859932 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/irqchip.h>
 #include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
@@ -54,7 +53,6 @@ static void __init board_init(void)
 static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
 
 DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
-	.init_irq = irqchip_init,
 	.init_time = clocksource_of_init,
 	.init_machine = board_init,
 	.dt_compat = bcm11351_dt_compat,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:52 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:52 +0200
Subject: [PATCH 19/20] ARM: virt: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-20-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for virt as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-virt/virt.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 061f283..bdf05f4 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -18,7 +18,6 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/irqchip.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/smp.h>
@@ -39,7 +38,6 @@ static const char *virt_dt_match[] = {
 extern struct smp_operations virt_smp_ops;
 
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-	.init_irq	= irqchip_init,
 	.init_machine	= virt_init,
 	.smp		= smp_ops(virt_smp_ops),
 	.dt_compat	= virt_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:47 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:47 +0200
Subject: [PATCH 14/20] ARM: msm: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-15-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for msm as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-msm/board-dt-8660.c | 2 --
 arch/arm/mach-msm/board-dt-8960.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 7dcfc53..492f5cd 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 
@@ -44,7 +43,6 @@ static const char *msm8x60_fluid_match[] __initdata = {
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
 	.smp = smp_ops(msm_smp_ops),
 	.map_io = msm_map_msm8x60_io,
-	.init_irq = irqchip_init,
 	.init_machine = msm8x60_dt_init,
 	.init_late = msm8x60_init_late,
 	.init_time	= msm_dt_timer_init,
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index 7301936..bb55309 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
@@ -31,7 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
 DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
 	.smp = smp_ops(msm_smp_ops),
 	.map_io = msm_map_msm8960_io,
-	.init_irq = irqchip_init,
 	.init_time	= msm_dt_timer_init,
 	.init_machine = msm_dt_init,
 	.dt_compat = msm8960_dt_match,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:38 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:38 +0200
Subject: [PATCH 05/20] ARM: shmobile: ape6evm: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-6-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/board-ape6evm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 55b8c9f..8dfbdba 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -20,7 +20,6 @@
 
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
@@ -87,7 +86,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-	.init_irq	= irqchip_init,
 	.init_time	= shmobile_timer_init,
 	.init_machine	= ape6evm_add_standard_devices,
 	.dt_compat	= ape6evm_boards_compat_dt,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:46 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:46 +0200
Subject: [PATCH 13/20] ARM: spear: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-14-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for spear as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar at linaro.org>
---
 arch/arm/mach-spear/spear1310.c | 2 --
 arch/arm/mach-spear/spear1340.c | 2 --
 arch/arm/mach-spear/spear300.c  | 2 --
 arch/arm/mach-spear/spear310.c  | 2 --
 arch/arm/mach-spear/spear320.c  | 2 --
 arch/arm/mach-spear/spear6xx.c  | 2 --
 6 files changed, 12 deletions(-)

diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 9eaac2c..7ad0030 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -14,7 +14,6 @@
 #define pr_fmt(fmt) "SPEAr1310: " fmt
 
 #include <linux/amba/pl022.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/pata_arasan_cf_data.h>
 #include <asm/mach/arch.h>
@@ -60,7 +59,6 @@ static void __init spear1310_map_io(void)
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
 	.smp		=	smp_ops(spear13xx_smp_ops),
 	.map_io		=	spear1310_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear13xx_timer_init,
 	.init_machine	=	spear1310_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index a04a7fe..3fb6834 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -17,7 +17,6 @@
 #include <linux/amba/serial.h>
 #include <linux/delay.h>
 #include <linux/of_platform.h>
-#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
 #include <mach/spear.h>
@@ -155,7 +154,6 @@ static const char * const spear1340_dt_board_compat[] = {
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
 	.smp		=	smp_ops(spear13xx_smp_ops),
 	.map_io		=	spear13xx_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear13xx_timer_init,
 	.init_machine	=	spear1340_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c
index bac56e8..b52e48f 100644
--- a/arch/arm/mach-spear/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -14,7 +14,6 @@
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
 #include <linux/amba/pl08x.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
@@ -212,7 +211,6 @@ static void __init spear300_map_io(void)
 
 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
 	.map_io		=	spear300_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear3xx_timer_init,
 	.init_machine	=	spear300_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c
index 6ffbc63..ed2029d 100644
--- a/arch/arm/mach-spear/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -15,7 +15,6 @@
 
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
@@ -254,7 +253,6 @@ static void __init spear310_map_io(void)
 
 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
 	.map_io		=	spear310_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear3xx_timer_init,
 	.init_machine	=	spear310_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c
index 6eb3eec..bf634b3 100644
--- a/arch/arm/mach-spear/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -269,7 +268,6 @@ static void __init spear320_map_io(void)
 
 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
 	.map_io		=	spear320_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear3xx_timer_init,
 	.init_machine	=	spear320_dt_init,
 	.restart	=	spear_restart,
diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index ec8eefb..8b0295a 100644
--- a/arch/arm/mach-spear/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl08x.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
@@ -423,7 +422,6 @@ static const char *spear600_dt_board_compat[] = {
 
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
 	.map_io		=	spear6xx_map_io,
-	.init_irq	=	irqchip_init,
 	.init_time	=	spear6xx_timer_init,
 	.init_machine	=	spear600_dt_init,
 	.restart	=	spear_restart,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:53 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:53 +0200
Subject: [PATCH 20/20] ARM: vt8500: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-21-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for vt8500 as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-vt8500/vt8500.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..70a5ac9 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -20,7 +20,6 @@
 
 #include <linux/clocksource.h>
 #include <linux/io.h>
-#include <linux/irqchip.h>
 #include <linux/pm.h>
 
 #include <asm/mach-types.h>
@@ -178,7 +177,6 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
 	.dt_compat	= vt8500_dt_compat,
 	.map_io		= vt8500_map_io,
-	.init_irq	= irqchip_init,
 	.init_machine	= vt8500_init,
 	.init_time	= clocksource_of_init,
 	.restart	= vt8500_restart,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:43 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:43 +0200
Subject: [PATCH 10/20] ARM: shmobile: r8a7790: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-11-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/mach-shmobile/setup-r8a7790.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d5..2a7a276 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -19,7 +19,6 @@
  */
 
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
@@ -142,7 +141,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
-	.init_irq	= irqchip_init,
 	.init_machine	= r8a7790_add_standard_devices_dt,
 	.init_time	= r8a7790_timer_init,
 	.dt_compat	= r8a7790_boards_compat_dt,
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Tue May 14 11:38:51 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 14 May 2013 17:38:51 +0200
Subject: [PATCH 18/20] ARM: vexpress: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1368545933-7430-19-git-send-email-maxime.ripard@free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for vexpress as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-vexpress/v2m.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 8802030..d601697 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -9,7 +9,6 @@
 #include <linux/clocksource.h>
 #include <linux/smp.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
@@ -458,7 +457,6 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
 	.smp		= smp_ops(vexpress_smp_ops),
 	.map_io		= v2m_dt_map_io,
 	.init_early	= v2m_dt_init_early,
-	.init_irq	= irqchip_init,
 	.init_time	= v2m_dt_timer_init,
 	.init_machine	= v2m_dt_init,
 MACHINE_END
-- 
1.8.1.2



From michal.simek at xilinx.com  Tue May 14 11:49:08 2013
From: michal.simek at xilinx.com (Michal Simek)
Date: Tue, 14 May 2013 17:49:08 +0200
Subject: [PATCH 02/20] ARM: zynq: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-3-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-3-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <4e7a6946-b165-4440-9785-e0d538b608e0@CO9EHSMHS013.ehs.local>

On 05/14/2013 05:38 PM, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for zynq as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Acked-by: Michal Simek <monstr at monstr.eu>
> ---
>  arch/arm/mach-zynq/common.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
> index 5bfe703..4c0199b8 100644
> --- a/arch/arm/mach-zynq/common.c
> +++ b/arch/arm/mach-zynq/common.c
> @@ -25,7 +25,6 @@
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
>  #include <linux/of.h>
> -#include <linux/irqchip.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> @@ -106,7 +105,6 @@ static const char * const zynq_dt_match[] = {
>  MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
>  	.smp		= smp_ops(zynq_smp_ops),
>  	.map_io		= zynq_map_io,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= zynq_init_machine,
>  	.init_time	= zynq_timer_init,
>  	.dt_compat	= zynq_dt_match,
> 

Subject should contain v2 but anyway I have added it my zynq repo.

Thanks,
Michal




From nicolas.ferre at atmel.com  Tue May 14 11:50:54 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 May 2013 17:50:54 +0200
Subject: [PATCH] ARM: at91/trivial: typo in GEM compatible string
Message-ID: <1368546654-20120-1-git-send-email-nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 Documentation/devicetree/bindings/net/macb.txt | 2 +-
 arch/arm/boot/dts/sama5d3.dtsi                 | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 44afa0e..4ff6504 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
   Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs.
   Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
-  Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
+  Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
   the Cadence GEM, or the generic form: "cdns,gem".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..5fce96b 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -156,7 +156,7 @@
 			};
 
 			macb0: ethernet at f0028000 {
-				compatible = "cnds,pc302-gem", "cdns,gem";
+				compatible = "cdns,pc302-gem", "cdns,gem";
 				reg = <0xf0028000 0x100>;
 				interrupts = <34 4 3>;
 				pinctrl-names = "default";
-- 
1.8.0



From mturquette at linaro.org  Tue May 14 11:58:35 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 08:58:35 -0700
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
Message-ID: <20130514155835.10068.93655@quantum>

Quoting Lee Jones (2013-05-08 06:29:03)
> First Ethernet device has a ".0" appended onto the device name. It
> appears that we need this in order to obtain the correct clock.
> 
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Looks good to me.  Can I take this into clk-next or are you looking for
an Ack?

Regards,
Mike

> ---
>  drivers/clk/ux500/u8500_clk.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
> index 0b4f35a..80069c3 100644
> --- a/drivers/clk/ux500/u8500_clk.c
> +++ b/drivers/clk/ux500/u8500_clk.c
> @@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
>         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
>                                 BIT(0), 0);
>         clk_register_clkdev(clk, "fsmc", NULL);
> -       clk_register_clkdev(clk, NULL, "smsc911x");
> +       clk_register_clkdev(clk, NULL, "smsc911x.0");
>  
>         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
>                                 BIT(1), 0);
> -- 
> 1.7.10.4


From jp.francois at cynove.com  Tue May 14 12:07:01 2013
From: jp.francois at cynove.com (jp.francois at cynove.com)
Date: Tue, 14 May 2013 18:07:01 +0200
Subject: [PATCH] ARM : omap : remove __init for _enable_preprogram
Message-ID: <1368547621-8570-1-git-send-email-jp.francois@cynove.com>

_enable_preprogram is marked as __init, but is called from _enable which is not.
This results in oops once init is freed.
Fix this by removing the __init marker.

Signed-off-by: Jean-Philippe Fran??ois <jp.francois at cynove.com>

Index: b/arch/arm/mach-omap2/omap_hwmod.c
===================================================================
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2066,7 +2066,7 @@
  * do so is present in the hwmod data, then call it and pass along the
  * return value; otherwise, return 0.
  */
-static int __init _enable_preprogram(struct omap_hwmod *oh)
+static int _enable_preprogram(struct omap_hwmod *oh)
 {
 	if (!oh->class->enable_preprogram)
 		return 0;


From swarren at wwwdotorg.org  Tue May 14 12:08:23 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 May 2013 10:08:23 -0600
Subject: GPIO sysfs : set a wake source
In-Reply-To: <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
Message-ID: <51926177.1050600@wwwdotorg.org>

On 05/14/2013 03:29 AM, Linus Walleij wrote:
> On Thu, May 9, 2013 at 2:59 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
> 
>> I was thinking on how to remove all "gpio_request()" from my board code
>> (arch/arm/mach-pxa/mioa701.c).
>>
>> I have a small difficulty with the functionality provided by gpiolib in
>> userspace. This is what I need :
>>  - define a gpio as an input
>>  - define this gpio to be an interrupt source
>>  - define this interrupt to be a wake-up source
> 
> This sounds like trying to remove board code by moving it to userspace
> and basically starting to implement stuff that belongs in the kernel
> in userspace just because someone says we should get rid of board
> files :-)
> 
> Don't go down this path, let the kernel handle this kind of stuff.
> 
> Instead figure out how to make the subsystems we have and the
> device trees express what you want to do.
> 
> In another thread I suggested that we add a GPIO "hogging"
> mechanism to gpiolib, so that the gpio subsystem can by itself
> "hog" (get) some GPIOs and set them up in certain modes.
> This closely matches what the pin control subsystem will do
> with some such things.
> 
> What do you think about this idea?

There's some merit to discussing the use of "GPIO hogging" for the
purpose of solving interactions between the IRQ and GPIO subsystems

However, the discussion above sounds like simply a list of GPIOs to
initialize at boot for the sole purpose of GPIO initialization. I
thought that had been discussed before and nak'd?


From jamie at jamieiles.com  Tue May 14 12:20:46 2013
From: jamie at jamieiles.com (Jamie Iles)
Date: Tue, 14 May 2013 17:20:46 +0100
Subject: [PATCH 04/20] ARM: picoxcell: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-5-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-5-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130514162046.GA16346@page>

Hi Maxime,

Thanks for this, I'll add it to my tree.  I've modified it slightly to 
kill off the other irq includes, hopefully that's okay with you.

Thanks,

Jamie

8<---

>From 4b83f75a7af388aaf5f79ccf72c37074bc9166da Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard at free-electrons.com>
Date: Tue, 14 May 2013 17:38:37 +0200
Subject: [PATCH] ARM: picoxcell: Remove init_irq declaration in machine
 description

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for picoxcell as well.

[ jiles: removed other, unused irq includes. ]

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Jamie Iles <jamie at jamieiles.com>
---
 arch/arm/mach-picoxcell/common.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index f6f71bb..b069fa6 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -8,12 +8,8 @@
  * All enquiries to support at picochip.com
  */
 #include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
-#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/dw_apb_timer.h>
 
@@ -85,7 +81,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
 	.map_io		= picoxcell_map_io,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_time	= dw_apb_timer_init,
 	.init_machine	= picoxcell_init_machine,
 	.dt_compat	= picoxcell_dt_match,
-- 
1.8.1.2



From mturquette at linaro.org  Tue May 14 12:22:19 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 09:22:19 -0700
Subject: [PATCH 2/5] clk: hi3xxx: add clock support
In-Reply-To: <CAD6h2NRqR4Qzpj8x7XTZZ+T==yBf3rq_VooAXNO4HOHb74pGZQ@mail.gmail.com>
References: <1366368567-17322-1-git-send-email-haojian.zhuang@linaro.org>
 <1366368567-17322-2-git-send-email-haojian.zhuang@linaro.org>
 <20130513194703.10068.4450@quantum>
 <CAD6h2NRqR4Qzpj8x7XTZZ+T==yBf3rq_VooAXNO4HOHb74pGZQ@mail.gmail.com>
Message-ID: <20130514162219.10068.9483@quantum>

Quoting Haojian Zhuang (2013-05-13 18:30:38)
> On 14 May 2013 03:47, Mike Turquette <mturquette at linaro.org> wrote:
> > Quoting Haojian Zhuang (2013-04-19 03:49:24)
> >> +struct hi3620_muxclk {
> >> +       struct clk_hw   hw;
> >> +       void __iomem    *reg;           /* mux register */
> >> +       u8              shift;
> >> +       u8              width;
> >> +       u32             mbits;          /* mask bits in mux register */
> >
> > You need shift, width AND a mask?  Normally either shift+width OR a mask
> > would suffice.
> 
> No, it's a little different. In their mux registers, there're two
> parts. One is lower
> 16 bits that are used to set mux, and the other is higher 16 bits that are
> used to set mux mask.
> 
> At here, I use mbits for higher 16 bits and shift & width for lower 16 bits.
> 

Ok, good to know.

<snip>

> >> +static struct clk_ops hi3620_clkgate_ops = {
> >> +       .prepare        = hi3620_clkgate_prepare,
> >> +       .enable         = hi3620_clkgate_enable,
> >> +       .disable        = hi3620_clkgate_disable,
> >
> > .unprepare?
> 
> I didn't implement unprepare at here. Since I find some device controller
> as uart not working if I disable clocks in unprepare(). Now I leave it as
> unimplemented.
> 

Sounds like the UART driver needs to be fixed.  Do you have plans to
look into that further?  Having only the prepare and not the unprepare
callback feels like a hack to me.

<snip>

> >> +static void __init hs_clkgate_setup(struct device_node *np)
> >> +{
> >> +       struct clk *clk;
> >> +       const char *clk_name, **parent_names, *name;
> >> +       unsigned long flags = 0;
> >> +       u32 data[2];
> >> +
> >> +       hs_init_clocks();
> >> +       if (!hs_clk.sctrl)
> >> +               return;
> >> +       if (of_property_read_string(np, "clock-output-names", &clk_name))
> >> +               return;
> >> +       if (of_property_read_u32_array(np, "hisilicon,clkgate",
> >> +                                      &data[0], 2))
> >> +               return;
> >> +       if (of_property_read_bool(np, "hisilicon,clkgate-inverted"))
> >> +               flags = CLK_GATE_SET_TO_DISABLE;
> >> +       /* gate only has the fixed parent */
> >> +       parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> >> +       if (!parent_names)
> >> +               return;
> >> +       parent_names[0] = of_clk_get_parent_name(np, 0);
> >> +
> >> +       clk = clk_register_gate(NULL, clk_name, parent_names[0], 0,
> >> +                               hs_clk.sctrl + data[0], (u8)data[1], flags,
> >> +                               &hs_clk.lock);
> >> +       if (IS_ERR(clk))
> >> +               goto err;
> >> +       if (!of_property_read_string(np, "clock-names", &name))
> >> +               clk_register_clkdev(clk, name, NULL);
> >> +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
> >> +       return;
> >> +err:
> >> +       kfree(parent_names);
> >> +}
> >
> > I'm working on clock bindings for the generic clock types, so hopefully
> > this can be replaced by those instead of using your own compatible
> > string to wrap around clk_register_gate.
> 
> It's great. Could you cc me when you send patches out?
> 

Yes I will Cc you.  I'll publish a gate-clock binding either this week
or next.  Do you want to wait for that and refactor your next version
based on it?

<snip>

> > This looks like it was copy/pasted from the generic clk-divider type.
> > Is there some reason you cannot use that instead of duplicating all of
> > that code here?
> 
> Yes, it's a copy. The registers are not wrapped in their silicon. In most
> vendor's SoC, the registers are read/write.
> 
> But they links the read/write to different registers. So one clock divider
> register is split into four registers, and they're set, unset, status & final
> status.
> 
> And the other reason is that they use higher 16 bits as mask bits. So
> they're not compatible with other vendor's SoC. Of course, I can also
> use generic clk-divider/clk-mux type, but I need to change a lot in
> common files, such as abstracting read/write. Is it OK for you?
> 

Ok, thanks for explaining that.  The purpose of the basic clock types
(like clk_divider) is to provide common code for platforms that use a
common programming model for their clock controls.  If you think that
you'll have other platforms with similar 4-register dividers then it
may be worth your time to try to abstract it.  However since no other
platforms have this sort of requirement it does not qualify as being
"common".  The choice is yours if you want to give it a shot.  If the
changes are very invasive and ugly for the common divider type (such as
modifying the existing registration function for all users) then I won't
take it.

An alternative might be to create a "superset" clock using the basic
divider.  An example of this is the i.MX divider which uses a "busy
bit".  See here: arch/arm/mach-imx/clk-busy.c

I think you're programming model may be to different to use that, I'm
not sure, but the idea is to reuse the code and just wrap the basic
clock type with your specific clock requirements.

Regards,
Mike

> Regards
> Haojian
> 
> >
> > Thanks,
> > Mike
> >
> >> +CLK_OF_DECLARE(hi3620_mux, "hisilicon,hi3620-clk-mux", hi3620_clkmux_setup)
> >> +CLK_OF_DECLARE(hi3620_gate, "hisilicon,hi3620-clk-gate", hi3620_clkgate_setup)
> >> +CLK_OF_DECLARE(hi3620_div, "hisilicon,hi3620-clk-div", hi3620_clkdiv_setup)
> >> +CLK_OF_DECLARE(hs_gate, "hisilicon,clk-gate", hs_clkgate_setup)
> >> +CLK_OF_DECLARE(hs_fixed, "hisilicon,clk-fixed-factor", hs_fixed_factor_setup)
> >> --
> >> 1.7.10.4


From gmbnomis at gmail.com  Tue May 14 12:26:52 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 14 May 2013 18:26:52 +0200
Subject: [PATCH V2 00/10] mmc_of_parse() adaptations, DT support for
 Sheevaplugs
In-Reply-To: <Pine.LNX.4.64.1305140819520.32151@axis700.grange>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <Pine.LNX.4.64.1305140819520.32151@axis700.grange>
Message-ID: <20130514162652.GA13801@schnuecks.de>

Hi Guennadi,

On Tue, May 14, 2013 at 08:37:47AM +0200, Guennadi Liakhovetski wrote:
> On Mon, 13 May 2013, Simon Baatz wrote:
> 
> > While adding DT support for the Sheevaplugs by Globalscale Technologies
> > (Kirkwood), it turned out that the DT binding of mvsdio lacked features to
> > properly support the hardware (active high/low of CD and WP pins could not
> > be described in DT).
> > 
> > This is standard functionality provided by the mmc_of_parse() helper
> > function.  However, mmc_of_parse() may allocate GPIO lines.  If the
> > allocation fails, it outputs an error, but does not return an error to its
> > caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.
> 
> Thanks for the patches. In principle I'm fine either way. It is a policy 
> decision IMHO. E.g. consider a situation. You have a DT with an SD-card 
> slot, where card-detection is performed by a GPIO. OTOH the same pin is 
> used on some other (optional) interface on the same board. If that other 
> competing interface is unused, the driver isn't loaded, you can use the 
> GPIO for card-detection. However, if that other interface is used, your 
> attempt to get the card-detect pin will fail, but you still can use the 
> interface in polling mode. No, I don't think this is a good example of 
> hardware design :) User experience would depend on driver probing order, 
> but in principle it is imaginable. So, with the current mmc_of_parse() 
> you're more tolerant. You get a warning in the log, but the interface 
> might still be usable. And if you're surprised why your write protection 
> status hasn't been properly detected - just look in the log.

Yes, there is value in both ways. As should be clear by now, I prefer
being more strict here :-).  But in the end, it is a policy decision
as you say.

There is also a "middle way" to split off the gpio allocation. This
has already been proposed in some other thread IIRC.

For example, split the current mmc_of_parse() into:

- mmc_of_parse(): Parses everything except the cd, wp gpios. It can't
  return an error and assumes sensible default values in case of a
  parse error (as it does today).

- mmc_of_gpio_cd(), mmc_of_gpio_wp(): Parses the cd/wp parts and
  requests the respective gpio (returning an error if that fails).

However, this means up to three calls instead of one in the
driver (and the respective error checking if needed).

On the other hand, it offers more flexibility: the driver can decide
whether to ignore the error, fall back to MMC_CAP_NEEDS_POLL or abort
the probe.

> You're proposing a change in behaviour. After your change any failure to 
> obtain a resource in mmc_of_parse() will fail interface probing. 
> Personally I don't think there are any users around, who would notice this 
> change, still, we have to be aware of it. And I don't know whether we 
> should do that. You know, we don't break user-space ;-)
> 
> So, technically I'm ok with the changes, but policy-wise I'm not sure how 
> severe this change would be. We could go a bit slower and first add a 
> return code as in your patch #1, but not fail drivers, like in your 
> patches #2, 3,... but WARN_ON(mmc_of_parse() < 0); and continue for now. 
> In 3.12 we could then replace those warnings with real failures. But maybe 
> I'm just overcautious and we can just go ahead with your patches. You can 
> add my
> 
> Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> 
> for patches 1-3, and let's see what Chris thinks about this change.

Thanks for the review and the ack! Of course, I am fine with a more
cautious way if that's required.

- Simon


From plagnioj at jcrosoft.com  Tue May 14 12:24:50 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 May 2013 18:24:50 +0200
Subject: [PATCH v2] net/macb: fix ISR clear-on-write behavior only for
 some SoC
In-Reply-To: <1368536416-18364-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <1368536416-18364-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20130514162450.GF22508@game.jcrosoft.org>

On 15:00 Tue 14 May     , Nicolas Ferre wrote:
> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
> introduces clear-on-write on ISR register. This behavior is not always
> implemented when using Cadence MACB/GEM and is breaking other platforms.
> We are using the Design Configuration Register 1 information and a capability
> property to actually activate this clear-on-write behavior on ISR.
> 
> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
> v2: - use DCFG1 bit 23 integration information instead of device tree
>       compatibility string to retreive information about c-o-r vs. c-o-w ISR.
>     - move configuration in macb_init_hw() function instead of probe() - at
>       "open" time.
> 
> As I have changed the most of this patch, I will collect your Ack and feedback
> just like a new patch. Thanks for your help...
> 
> Bye,
> 
>  drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++++++--
>  drivers/net/ethernet/cadence/macb.h |  7 +++++++
>  2 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 6be513d..c89aa41 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -485,7 +485,8 @@ static void macb_tx_interrupt(struct macb *bp)
>  	status = macb_readl(bp, TSR);
>  	macb_writel(bp, TSR, status);
>  
> -	macb_writel(bp, ISR, MACB_BIT(TCOMP));
> +	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +		macb_writel(bp, ISR, MACB_BIT(TCOMP));
>  
>  	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
>  		(unsigned long)status);
> @@ -738,7 +739,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
>  			 * now.
>  			 */
>  			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
> -			macb_writel(bp, ISR, MACB_BIT(RCOMP));
> +			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +				macb_writel(bp, ISR, MACB_BIT(RCOMP));
>  
>  			if (napi_schedule_prep(&bp->napi)) {
>  				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
> @@ -1062,6 +1064,17 @@ static void macb_configure_dma(struct macb *bp)
>  	}
>  }
>  
> +/*
> + * Configure peripheral capacities according to integration options used
> + */
> +static void macb_configure_caps(struct macb *bp)
> +{
> +	if (macb_is_gem(bp)) {
> +		if (GEM_BF(IRQCOR, gem_readl(bp, DCFG1)) == 0)
> +			bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
> +	}
> +}
> +
>  static void macb_init_hw(struct macb *bp)
>  {
>  	u32 config;
> @@ -1084,6 +1097,7 @@ static void macb_init_hw(struct macb *bp)
>  	bp->duplex = DUPLEX_HALF;
>  
>  	macb_configure_dma(bp);
> +	macb_configure_caps(bp);
>  
>  	/* Initialize TX and RX buffers */
>  	macb_writel(bp, RBQP, bp->rx_ring_dma);
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 993d703..548c0ec 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -300,6 +300,8 @@
>  #define MACB_REV_SIZE				16
>  
>  /* Bitfields in DCFG1. */
> +#define GEM_IRQCOR_OFFSET			23
> +#define GEM_IRQCOR_SIZE				1
>  #define GEM_DBWDEF_OFFSET			25
>  #define GEM_DBWDEF_SIZE				3
>  
> @@ -323,6 +325,9 @@
>  #define MACB_MAN_READ				2
>  #define MACB_MAN_CODE				2
>  
> +/* Capability mask bits */
> +#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x1
> +
>  /* Bit manipulation macros */
>  #define MACB_BIT(name)					\
>  	(1 << MACB_##name##_OFFSET)
> @@ -574,6 +579,8 @@ struct macb {
>  	unsigned int 		speed;
>  	unsigned int 		duplex;
>  
> +	u32			caps;
> +
>  	phy_interface_t		phy_interface;
>  
>  	/* AT91RM9200 transmit */
> -- 
> 1.8.0
> 


From mturquette at linaro.org  Tue May 14 12:46:11 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 09:46:11 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
References: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
Message-ID: <20130514164611.10068.46384@quantum>

Quoting S?ren Brinkmann (2013-05-13 10:58:49)
> On Mon, May 13, 2013 at 07:37:23PM +0200, Sebastian Hesselbarth wrote:
> > On 05/13/13 19:24, S?ren Brinkmann wrote:
> > >On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
> > >>>Well, that driver actually exists. But that just programs a bitstream
> > >>>you give it to program. It does not know anything about the design it
> > >>>programs and cannot make any kind of decision whether the clocks should
> > >>>be userspace controlled or not.
> > >>
> > >>what Mark wants to point out is that you add fabric clocks to the Xilinx
> > >>driver instead. This way, you will have user-space controllable clocks
> > >>but only if you loaded the xilinx driver first.
> > >What "Xilinx driver", are we talking about?
> > 
> > The device config driver you mention below.
> > 
> > >>IIRC the fabric clock controller provided by Zynq _is_ always there and
> > >>accessible from ARM CPUs. You just don't have a new generic driver
> > >>allowing to poke with all clocks, but a xilinx only driver allowing you
> > >>to set the (xilinx only) fabric clocks.
> > >Right.
> > >
> > >>I've played with Zynq a while ago, did Xilinx mainline the bitfile
> > >>driver already? If not, why don't you give it a shot?
> > >The device config driver is not in mainline, AFAIK. And I think it's in
> > >rather bad shape and needs a lot of work before it is upstreamable. But
> > >this is probably the right place to put this.
> > 
> > It is, as it will only expose clocks on Zynq and that's what Mark and
> > Mike are worried about. Expose clocks to user space and you will have
> > people mess with it for sure.
> Well, even if you contain it in that driver you can still mess with
> other clocks. Just give it the "wrong" input clock references in DT and
> you are free to control them. As I said before, there is no protection
> against such misuse.

My objections are not about creating the most secure platform ever.  My
objections are about lowering the barrier of entry for folks to misuse
the clk api.  Clearly anyone that can compile a kernel and flash it to a
device can misuse anything they want.  Likewise if someone can compile a
DTB and flash it then there is another vector for misuse.

However, making an api available to any userspace application
substantially lowers the barrier to misuse.  Physical access to the
device is no longer needed in case of flashing new stuff to nand, or
emmc or whatever.  And by misuse I do not only mean people trying to
steal your credit card (I would be impressed if controlling clocks was a
part of that!), but I do not want to encourage vendors to implement crap
userspace drivers to control clocks instead of upstreaming proper Linux
device drivers.  And it is clearly possible to destroy a device with
irresponsible clock control.

While most of us agree that exposing clock controls to userspace is
useful for debugging, at this point I do not think the positive aspects
of mainlining the feature are strong enough to overcome the negative
aspects.

I'm sure implementations of this functionality will exist out-of-tree
(as pointed out by Peter), but not everything should be merged to
mainline.

Regards,
Mike

> 
> > 
> > About the shape of it, I didn't expect that to change at all. Just
> > wondering, if it still requires you to manually end it's endianess
> > mess with the bitfiles. If you go at it, consider reading the magic
> > hidden in the bitfile and swap it when it is required. But that will
> > go OT here.
> It still takes byteswapped, binary images as input, unfortunately.
> 
> > 
> > >On the other hand, currently this driver is only required for
> > >programming the FPGA from Linux, which is not required. One of the
> > >bootloaders could do this for you earlier.
> > 
> > Well, exposing clocks to user space is not required _at all_ on all
> > other platforms you can think of. So, if you have a Zynq, you can
> > always load a Zynq driver even if you are not going to use it's
> > bitfile programming capabilities but only to configure clocks.
> > 
> > If you don't want to merge both drivers, have a Zynq-only clock
> > fabric driver instead?
> That was my original intention. But due to the nature of it, it will
> always be possible to use it with other clocks too. Hence my generic
> approach.
> I actually like the idea of making it part of the device config driver.
> The downside of it is, that this driver seems a bit far from mainline.
> 
>         S?ren


From robherring2 at gmail.com  Tue May 14 12:53:34 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 14 May 2013 11:53:34 -0500
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM
 VCPU ioctl
In-Reply-To: <5191E2BF.5040102@linaro.org>
References: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
 <20130513055253.GC64337@ubuntu> <519167D3.4030600@linaro.org>
 <CAEDV+gKTYCh8zTPJAxSmwhuyWo7K5Ej75giryR-pv5oqHdURSQ@mail.gmail.com>
 <5191E2BF.5040102@linaro.org>
Message-ID: <51926C0E.2000504@gmail.com>

On 05/14/2013 02:07 AM, Andre Przywara wrote:
> On 05/14/2013 12:42 AM, Christoffer Dall wrote:
>> On Mon, May 13, 2013 at 3:23 PM, Andre Przywara
>> <andre.przywara at linaro.org> wrote:
>>> ooks like a natural candidate, but unfortunately struct kvm_vcpu is
>>> opaque
>>> here, so dereferencing it does not work without further changes which
>>> I do
>>> not deem to be justified. I used kvm_coproc.h instead, which is loosely
>>> related (KVM_[SG]ET_ONE_REG) and just simply works. If you don't think
>>> that's appropriate, just drop me a note. Patch follows in a separate
>>> mail.
>>
>> eh, not crazy about the idea. x86 has
>> arch/x86/include/asm/kvm_guest.h, which may be the most appropriate,
>> or this could be generalized to other architectures as well and
>> included in include/linux/kvm_host.h.
>>
>> we can just stick it in arch/arm/kvm/arm.c for now and move later if
>> need be, no need to create a fuzz.
> 
> Ok, would you mind to commit v2 and add the "inline" on the way?

You don't really need the inline if it's not in a header. The compiler
will inline it anyway.

Rob



From mturquette at linaro.org  Tue May 14 12:59:37 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 09:59:37 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <CAAG0J991BCziPFddzBrx9vcwRxyRgcCd38A01uKXTDDK9xTnbQ@mail.gmail.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <20130513195746.10068.92303@quantum>
 <CAAG0J991BCziPFddzBrx9vcwRxyRgcCd38A01uKXTDDK9xTnbQ@mail.gmail.com>
Message-ID: <20130514165937.10068.18501@quantum>

Quoting James Hogan (2013-05-13 14:30:46)
> On 13 May 2013 20:57, Mike Turquette <mturquette at linaro.org> wrote:
> > Quoting James Hogan (2013-04-19 09:28:21)
> >> This patchset adds support for automatic selection of the best parent
> >> for a clock mux, i.e. the one which can provide the closest clock rate
> >> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
> >> so that it doesn't happen unless explicitly allowed.
> >>
> >
> > I'm not sure about the new flag.  One of my regrets during the early
> > development of the common struct clk is the CLK_SET_RATE_PARENT flag.
> > In hindsight I would have preferred to make parent-propagation of rate
> > changes the default behavior, and instead provide a flag to prevent that
> > behavior, such as CLK_SET_RATE_NO_PROPAGATE.
> >
> > One reason for this is the difficulty some have had with setting flags
> > from DT bindings.
> 
> Could you elaborate on this? I've been adding flags to DT bindings for
> this sort of thing, but it feels a bit like it's in that grey area of
> not really describing the hardware itself. This information needs to
> be specified somehow though.
> 

It depends on the flag.  A good example is the CLK_DIVIDER_ONE_BASED
flag which does describe the hardware.  It informs the binding that
indexing starts at 1, not 0, which is a valid part of the hardware
description.

However flags that deal with software policy do not belong on DT.
CLK_SET_RATE_PARENT certainly does not belong in the DT binding since
this is a pure Linux-ism.  Every binding just needs to be reviewed on a
case-by-case basis to make sure the flags are related only to the
hardware.

Regards,
Mike

> > Another reason is that a core goal of the framework
> > is to remove topology info from drivers; having to set a flag explicitly
> > on each clock to propagate rate changes is an impediment to that goal.
> 
> (Something that I have found also where CLK_SET_RATE_PARENT doesn't
> fit well is when you have a mux where you want the set_rate propagated
> to one possible parent (e.g. a dedicated PLL) but not the other (e.g.
> the system clock - which happens to be a divider). In this case what I
> really want to say is "don't change the rate of this particular
> clock", in fact I added a CLK_DIVIDER_READ_ONLY divider flag locally
> for this purpose. Was there a particular use case of
> CLK_SET_RATE_PARENT where you'd want a clock to be changed from one
> child but not another?)
> 
> >
> > So perhaps CLK_SET_RATE_REMUX is a similar situation.  What do you think
> > about making remuxing the default and providing a flag to prevent it?
> 
> Yes, fine by me.
> 
> > And also we can assume for the immediate future that users of
> > .determine_rate WANT to remux, since .round_rate won't do it.  Though
> > eventually it might be wise to convert all users of .round_rate over to
> > .determine_rate and deprecate .round_rate entirely.
> 
> True.
> 
> Cheers
> James


From will.deacon at arm.com  Tue May 14 13:00:12 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 14 May 2013 18:00:12 +0100
Subject: [PATCH] ARM: vfp: ensure VFP_arch is non-zero when VFP is not
 supported
Message-ID: <1368550812-30492-1-git-send-email-will.deacon@arm.com>

Commit d3f79584a8b5 ("ARM: cleanup undefined instruction entry code")
improved the register scheduling when handling undefined instructions.
A side effect of this is that r5 is now used as a temporary, whilst the
VFP probing code relies on r5 containing a non-zero value when VFP is
not supported.

This patch fixes the VFP detection code so that we don't rely on the
contents of r5. Without this patch, Linux dies loudly on CPUs without
VFP support.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/vfp/entry.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 323ce1a..46e1749 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -60,7 +60,7 @@ ENTRY(vfp_testing_entry)
 	str	r11, [r10, #TI_PREEMPT]
 #endif
 	ldr	r0, VFP_arch_address
-	str	r5, [r0]		@ known non-zero value
+	str	r0, [r0]		@ set to non-zero value
 	mov	pc, r9			@ we have handled the fault
 ENDPROC(vfp_testing_entry)
 
-- 
1.8.2.2



From cdall at cs.columbia.edu  Tue May 14 13:01:51 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Tue, 14 May 2013 10:01:51 -0700
Subject: [PATCH v2] ARM: KVM: prevent NULL pointer dereferences with KVM
 VCPU ioctl
In-Reply-To: <5191E2BF.5040102@linaro.org>
References: <1368052086-25059-1-git-send-email-andre.przywara@linaro.org>
 <20130513055253.GC64337@ubuntu> <519167D3.4030600@linaro.org>
 <CAEDV+gKTYCh8zTPJAxSmwhuyWo7K5Ej75giryR-pv5oqHdURSQ@mail.gmail.com>
 <5191E2BF.5040102@linaro.org>
Message-ID: <CAEDV+gJJzCB8HNDKhbVuGG7dOvqBS58PWD5McVBq2F5AmLBz2Q@mail.gmail.com>

On Tue, May 14, 2013 at 12:07 AM, Andre Przywara
<andre.przywara at linaro.org> wrote:
> On 05/14/2013 12:42 AM, Christoffer Dall wrote:
>>
>> On Mon, May 13, 2013 at 3:23 PM, Andre Przywara
>> <andre.przywara at linaro.org> wrote:
>>>
>>> ooks like a natural candidate, but unfortunately struct kvm_vcpu is
>>> opaque
>>> here, so dereferencing it does not work without further changes which I
>>> do
>>> not deem to be justified. I used kvm_coproc.h instead, which is loosely
>>> related (KVM_[SG]ET_ONE_REG) and just simply works. If you don't think
>>> that's appropriate, just drop me a note. Patch follows in a separate
>>> mail.
>>
>>
>> eh, not crazy about the idea. x86 has
>> arch/x86/include/asm/kvm_guest.h, which may be the most appropriate,
>> or this could be generalized to other architectures as well and
>> included in include/linux/kvm_host.h.
>>
>> we can just stick it in arch/arm/kvm/arm.c for now and move later if
>> need be, no need to create a fuzz.
>
>
> Ok, would you mind to commit v2 and add the "inline" on the way?
>
If it stays in arm.c it shouldn't have an inline on there, I'll commit
the patch, thanks.

-Christoffer


From cdall at cs.columbia.edu  Tue May 14 13:05:00 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Tue, 14 May 2013 10:05:00 -0700
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <20130513085802.GA24455@mudshark.cambridge.arm.com>
References: <1367505542-2231-1-git-send-email-marc.zyngier@arm.com>
 <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
 <20130502150355.GA25022@mudshark.cambridge.arm.com>
 <CAEDV+gJwYpHzehWZci2bmgYedJoBxMOGZFhjGeGRQ_cT8TKkyw@mail.gmail.com>
 <20130502151753.GB25022@mudshark.cambridge.arm.com>
 <20130513051737.GB64337@ubuntu>
 <20130513085802.GA24455@mudshark.cambridge.arm.com>
Message-ID: <CAEDV+gJr4wgAL=2DeJptmGM=NbHZvgxFcY3bPzOWUJph1zuBSA@mail.gmail.com>

On Mon, May 13, 2013 at 1:58 AM, Will Deacon <will.deacon at arm.com> wrote:
> On Mon, May 13, 2013 at 06:17:37AM +0100, Christoffer Dall wrote:
>> On Thu, May 02, 2013 at 04:17:53PM +0100, Will Deacon wrote:
>> > or just *pte = XX;
>> >
>> That won't work with STRICT_M_TYPECHECKS though will it?
>
> Depends if XX is a pte_t or not :)
>
this is silly :)


From nico at fluxnic.net  Tue May 14 13:08:03 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 14 May 2013 13:08:03 -0400 (EDT)
Subject: [PATCH] ARM: zImage: Convert 32bits memory size and address from
 ATAG to 64bits DTB
In-Reply-To: <1368545323-3621-2-git-send-email-gregory.clement@free-electrons.com>
References: <1368545323-3621-1-git-send-email-gregory.clement@free-electrons.com>
 <1368545323-3621-2-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <alpine.LFD.2.03.1305141306070.31158@syhkavp.arg>

On Tue, 14 May 2013, Gregory CLEMENT wrote:

> When CONFIG_ARM_APPENDED_DTB is selected, if the bootloader provides
> an ATAG_MEM it replaces the memory size and the memory address in the
> memory node of the device tree. In the case of a system which can
> handle more than 4GB, the memory node cell size is 4: each data
> (memory size and memory address) are 64 bits and then use 2 cells.
> 
> The current code in atags_to_fdt.c made the assumption of a cell size
> of 2 (one cell for the memory size and one cell for the memory
> address), this leads to an improper write of the data and ends with a
> boot hang.
> 
> This patch writes the memory size and the memory address on the memory
> node in the device tree depending of the size of the memory node (32
> bits or 64 bits).
> 
> It has been tested in the 2 cases:
> - with a dtb using skeleton.dtsi
> - and with a dtb using skeleton64.dtsi
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

Please send to RMK's patch system.

> ---
>  arch/arm/boot/compressed/atags_to_fdt.c | 44 ++++++++++++++++++++++++++++-----
>  1 file changed, 38 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
> index aabc02a..d1153c8 100644
> --- a/arch/arm/boot/compressed/atags_to_fdt.c
> +++ b/arch/arm/boot/compressed/atags_to_fdt.c
> @@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path,
>  	return fdt_getprop(fdt, offset, property, len);
>  }
>  
> +static uint32_t get_cell_size(const void *fdt)
> +{
> +	int len;
> +	uint32_t cell_size = 1;
> +	const uint32_t *size_len =  getprop(fdt, "/", "#size-cells", &len);
> +
> +	if (size_len)
> +		cell_size = fdt32_to_cpu(*size_len);
> +	return cell_size;
> +}
> +
>  static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
>  {
>  	char cmdline[COMMAND_LINE_SIZE];
> @@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
>  int atags_to_fdt(void *atag_list, void *fdt, int total_space)
>  {
>  	struct tag *atag = atag_list;
> -	uint32_t mem_reg_property[2 * NR_BANKS];
> +	/* In the case of 64 bits memory size, need to reserve 2 cells for
> +	 * address and size for each bank */
> +	uint32_t mem_reg_property[2 * 2 * NR_BANKS];
>  	int memcount = 0;
> -	int ret;
> +	int ret, memsize;
>  
>  	/* make sure we've got an aligned pointer */
>  	if ((u32)atag_list & 0x3)
> @@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
>  				continue;
>  			if (!atag->u.mem.size)
>  				continue;
> -			mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
> -			mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
> +			memsize = get_cell_size(fdt);
> +
> +			if (memsize == 2) {
> +				/* if memsize is 2, that means that
> +				 * each data needs 2 cells of 32 bits,
> +				 * so the data are 64 bits */
> +				uint64_t *mem_reg_prop64 =
> +					(uint64_t *)mem_reg_property;
> +				mem_reg_prop64[memcount++] =
> +					cpu_to_fdt64(atag->u.mem.start);
> +				mem_reg_prop64[memcount++] =
> +					cpu_to_fdt64(atag->u.mem.size);
> +			} else {
> +				mem_reg_property[memcount++] =
> +					cpu_to_fdt32(atag->u.mem.start);
> +				mem_reg_property[memcount++] =
> +					cpu_to_fdt32(atag->u.mem.size);
> +			}
> +
>  		} else if (atag->hdr.tag == ATAG_INITRD2) {
>  			uint32_t initrd_start, initrd_size;
>  			initrd_start = atag->u.initrd.start;
> @@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
>  		}
>  	}
>  
> -	if (memcount)
> -		setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
> +	if (memcount) {
> +		setprop(fdt, "/memory", "reg", mem_reg_property,
> +			4 * memcount * memsize);
> +	}
>  
>  	return fdt_pack(fdt);
>  }
> -- 
> 1.8.1.2
> 


From csd at broadcom.com  Tue May 14 14:04:50 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 14 May 2013 11:04:50 -0700
Subject: [PATCH 12/20] ARM: bcm281xx: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-13-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-13-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <51927CC2.7080101@broadcom.com>

On 13-05-14 08:38 AM, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for bcm281xx as well.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Acked-by: Christian Daudt <csd at broadcom.com>
> ---
>   arch/arm/mach-bcm/board_bcm.c | 2 --
>   1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
> index 22e8421..2859932 100644
> --- a/arch/arm/mach-bcm/board_bcm.c
> +++ b/arch/arm/mach-bcm/board_bcm.c
> @@ -15,7 +15,6 @@
>   #include <linux/init.h>
>   #include <linux/device.h>
>   #include <linux/platform_device.h>
> -#include <linux/irqchip.h>
>   #include <linux/clocksource.h>
>   
>   #include <asm/mach/arch.h>
> @@ -54,7 +53,6 @@ static void __init board_init(void)
>   static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
>   
>   DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
> -	.init_irq = irqchip_init,
>   	.init_time = clocksource_of_init,
>   	.init_machine = board_init,
>   	.dt_compat = bcm11351_dt_compat,
Applied.

  Thanks,
    csd




From khilman at linaro.org  Tue May 14 14:08:20 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 14 May 2013 11:08:20 -0700
Subject: [PATCH] ARM : omap : remove __init for _enable_preprogram
In-Reply-To: <1368547621-8570-1-git-send-email-jp.francois@cynove.com> (jp
 francois's message of "Tue, 14 May 2013 18:07:01 +0200")
References: <1368547621-8570-1-git-send-email-jp.francois@cynove.com>
Message-ID: <8738tpxwmj.fsf@linaro.org>

jp.francois at cynove.com writes:

> _enable_preprogram is marked as __init, but is called from _enable which is not.
> This results in oops once init is freed.
> Fix this by removing the __init marker.
>
> Signed-off-by: Jean-Philippe Fran?ois <jp.francois at cynove.com>

Acked-by: Kevin Hilman <khilman at linaro.org>

Tony, this should probably be queued for v3.10-rc, and tagged for stable.

Kevin

> Index: b/arch/arm/mach-omap2/omap_hwmod.c
> ===================================================================
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -2066,7 +2066,7 @@
>   * do so is present in the hwmod data, then call it and pass along the
>   * return value; otherwise, return 0.
>   */
> -static int __init _enable_preprogram(struct omap_hwmod *oh)
> +static int _enable_preprogram(struct omap_hwmod *oh)
>  {
>  	if (!oh->class->enable_preprogram)
>  		return 0;


From philip at balister.org  Tue May 14 14:09:47 2013
From: philip at balister.org (Philip Balister)
Date: Tue, 14 May 2013 14:09:47 -0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130514164611.10068.46384@quantum>
References: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum>
Message-ID: <51927DEB.7090001@balister.org>

On 05/14/2013 12:46 PM, Mike Turquette wrote:
> Quoting S?ren Brinkmann (2013-05-13 10:58:49)
>> On Mon, May 13, 2013 at 07:37:23PM +0200, Sebastian Hesselbarth wrote:
>>> On 05/13/13 19:24, S?ren Brinkmann wrote:
>>>> On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
>>>>>> Well, that driver actually exists. But that just programs a bitstream
>>>>>> you give it to program. It does not know anything about the design it
>>>>>> programs and cannot make any kind of decision whether the clocks should
>>>>>> be userspace controlled or not.
>>>>>
>>>>> what Mark wants to point out is that you add fabric clocks to the Xilinx
>>>>> driver instead. This way, you will have user-space controllable clocks
>>>>> but only if you loaded the xilinx driver first.
>>>> What "Xilinx driver", are we talking about?
>>>
>>> The device config driver you mention below.
>>>
>>>>> IIRC the fabric clock controller provided by Zynq _is_ always there and
>>>>> accessible from ARM CPUs. You just don't have a new generic driver
>>>>> allowing to poke with all clocks, but a xilinx only driver allowing you
>>>>> to set the (xilinx only) fabric clocks.
>>>> Right.
>>>>
>>>>> I've played with Zynq a while ago, did Xilinx mainline the bitfile
>>>>> driver already? If not, why don't you give it a shot?
>>>> The device config driver is not in mainline, AFAIK. And I think it's in
>>>> rather bad shape and needs a lot of work before it is upstreamable. But
>>>> this is probably the right place to put this.
>>>
>>> It is, as it will only expose clocks on Zynq and that's what Mark and
>>> Mike are worried about. Expose clocks to user space and you will have
>>> people mess with it for sure.
>> Well, even if you contain it in that driver you can still mess with
>> other clocks. Just give it the "wrong" input clock references in DT and
>> you are free to control them. As I said before, there is no protection
>> against such misuse.
>
> My objections are not about creating the most secure platform ever.  My
> objections are about lowering the barrier of entry for folks to misuse
> the clk api.  Clearly anyone that can compile a kernel and flash it to a
> device can misuse anything they want.  Likewise if someone can compile a
> DTB and flash it then there is another vector for misuse.
>
> However, making an api available to any userspace application
> substantially lowers the barrier to misuse.  Physical access to the
> device is no longer needed in case of flashing new stuff to nand, or
> emmc or whatever.  And by misuse I do not only mean people trying to
> steal your credit card (I would be impressed if controlling clocks was a
> part of that!), but I do not want to encourage vendors to implement crap
> userspace drivers to control clocks instead of upstreaming proper Linux
> device drivers.  And it is clearly possible to destroy a device with
> irresponsible clock control.
>
> While most of us agree that exposing clock controls to userspace is
> useful for debugging, at this point I do not think the positive aspects
> of mainlining the feature are strong enough to overcome the negative
> aspects.
>
> I'm sure implementations of this functionality will exist out-of-tree
> (as pointed out by Peter), but not everything should be merged to
> mainline.
>

I'm skimming this thread and am concerned there is a level of 
misunderstanding by many people how Zynq works :)

First of all, the driver that loads the bitstream into the fpga fabric 
does not know ANYTHING about what the bitstream does. So it cannot do 
any setup based on the contents of the file that is loaded. (And this 
can also be loaded during the SoC bootup, bypassing this driver completely)

Second, there are four clocks that feed the FPGA fabric. We will want to 
set these clocks from user space somehow. It is perfectly valid to use a 
uio driver to interface with logic in the fpga. If we take the approach 
of using such general purpose techniques to interface with fpga logic, 
we must have ways for the user to control the fpga clocks.

I give the Xilinx guys a lot of crap for not upstreaming their drivers 
fast enough for me :), so I feel obligated to help explain why users 
want to do this and I do not want to carry out of tree code that is 
critical to using these devices effectively.

I imagine the Altera soc-fpga parts will have similar issues. I suppose 
I should read the TRM for them one day.

Philip

> Regards,
> Mike
>
>>
>>>
>>> About the shape of it, I didn't expect that to change at all. Just
>>> wondering, if it still requires you to manually end it's endianess
>>> mess with the bitfiles. If you go at it, consider reading the magic
>>> hidden in the bitfile and swap it when it is required. But that will
>>> go OT here.
>> It still takes byteswapped, binary images as input, unfortunately.
>>
>>>
>>>> On the other hand, currently this driver is only required for
>>>> programming the FPGA from Linux, which is not required. One of the
>>>> bootloaders could do this for you earlier.
>>>
>>> Well, exposing clocks to user space is not required _at all_ on all
>>> other platforms you can think of. So, if you have a Zynq, you can
>>> always load a Zynq driver even if you are not going to use it's
>>> bitfile programming capabilities but only to configure clocks.
>>>
>>> If you don't want to merge both drivers, have a Zynq-only clock
>>> fabric driver instead?
>> That was my original intention. But due to the nature of it, it will
>> always be possible to use it with other clocks too. Hence my generic
>> approach.
>> I actually like the idea of making it part of the device config driver.
>> The downside of it is, that this driver seems a bit far from mainline.
>>
>>          S?ren



From philip at balister.org  Tue May 14 14:09:47 2013
From: philip at balister.org (Philip Balister)
Date: Tue, 14 May 2013 14:09:47 -0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130514164611.10068.46384@quantum>
References: <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <7e18bed3-ae6b-4aa0-bf23-b6c61ba8b85b@CO9EHSMHS030.ehs.local>
 <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum>
Message-ID: <51927DEB.7090001@balister.org>

On 05/14/2013 12:46 PM, Mike Turquette wrote:
> Quoting S?ren Brinkmann (2013-05-13 10:58:49)
>> On Mon, May 13, 2013 at 07:37:23PM +0200, Sebastian Hesselbarth wrote:
>>> On 05/13/13 19:24, S?ren Brinkmann wrote:
>>>> On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
>>>>>> Well, that driver actually exists. But that just programs a bitstream
>>>>>> you give it to program. It does not know anything about the design it
>>>>>> programs and cannot make any kind of decision whether the clocks should
>>>>>> be userspace controlled or not.
>>>>>
>>>>> what Mark wants to point out is that you add fabric clocks to the Xilinx
>>>>> driver instead. This way, you will have user-space controllable clocks
>>>>> but only if you loaded the xilinx driver first.
>>>> What "Xilinx driver", are we talking about?
>>>
>>> The device config driver you mention below.
>>>
>>>>> IIRC the fabric clock controller provided by Zynq _is_ always there and
>>>>> accessible from ARM CPUs. You just don't have a new generic driver
>>>>> allowing to poke with all clocks, but a xilinx only driver allowing you
>>>>> to set the (xilinx only) fabric clocks.
>>>> Right.
>>>>
>>>>> I've played with Zynq a while ago, did Xilinx mainline the bitfile
>>>>> driver already? If not, why don't you give it a shot?
>>>> The device config driver is not in mainline, AFAIK. And I think it's in
>>>> rather bad shape and needs a lot of work before it is upstreamable. But
>>>> this is probably the right place to put this.
>>>
>>> It is, as it will only expose clocks on Zynq and that's what Mark and
>>> Mike are worried about. Expose clocks to user space and you will have
>>> people mess with it for sure.
>> Well, even if you contain it in that driver you can still mess with
>> other clocks. Just give it the "wrong" input clock references in DT and
>> you are free to control them. As I said before, there is no protection
>> against such misuse.
>
> My objections are not about creating the most secure platform ever.  My
> objections are about lowering the barrier of entry for folks to misuse
> the clk api.  Clearly anyone that can compile a kernel and flash it to a
> device can misuse anything they want.  Likewise if someone can compile a
> DTB and flash it then there is another vector for misuse.
>
> However, making an api available to any userspace application
> substantially lowers the barrier to misuse.  Physical access to the
> device is no longer needed in case of flashing new stuff to nand, or
> emmc or whatever.  And by misuse I do not only mean people trying to
> steal your credit card (I would be impressed if controlling clocks was a
> part of that!), but I do not want to encourage vendors to implement crap
> userspace drivers to control clocks instead of upstreaming proper Linux
> device drivers.  And it is clearly possible to destroy a device with
> irresponsible clock control.
>
> While most of us agree that exposing clock controls to userspace is
> useful for debugging, at this point I do not think the positive aspects
> of mainlining the feature are strong enough to overcome the negative
> aspects.
>
> I'm sure implementations of this functionality will exist out-of-tree
> (as pointed out by Peter), but not everything should be merged to
> mainline.
>

I'm skimming this thread and am concerned there is a level of 
misunderstanding by many people how Zynq works :)

First of all, the driver that loads the bitstream into the fpga fabric 
does not know ANYTHING about what the bitstream does. So it cannot do 
any setup based on the contents of the file that is loaded. (And this 
can also be loaded during the SoC bootup, bypassing this driver completely)

Second, there are four clocks that feed the FPGA fabric. We will want to 
set these clocks from user space somehow. It is perfectly valid to use a 
uio driver to interface with logic in the fpga. If we take the approach 
of using such general purpose techniques to interface with fpga logic, 
we must have ways for the user to control the fpga clocks.

I give the Xilinx guys a lot of crap for not upstreaming their drivers 
fast enough for me :), so I feel obligated to help explain why users 
want to do this and I do not want to carry out of tree code that is 
critical to using these devices effectively.

I imagine the Altera soc-fpga parts will have similar issues. I suppose 
I should read the TRM for them one day.

Philip

> Regards,
> Mike
>
>>
>>>
>>> About the shape of it, I didn't expect that to change at all. Just
>>> wondering, if it still requires you to manually end it's endianess
>>> mess with the bitfiles. If you go at it, consider reading the magic
>>> hidden in the bitfile and swap it when it is required. But that will
>>> go OT here.
>> It still takes byteswapped, binary images as input, unfortunately.
>>
>>>
>>>> On the other hand, currently this driver is only required for
>>>> programming the FPGA from Linux, which is not required. One of the
>>>> bootloaders could do this for you earlier.
>>>
>>> Well, exposing clocks to user space is not required _at all_ on all
>>> other platforms you can think of. So, if you have a Zynq, you can
>>> always load a Zynq driver even if you are not going to use it's
>>> bitfile programming capabilities but only to configure clocks.
>>>
>>> If you don't want to merge both drivers, have a Zynq-only clock
>>> fabric driver instead?
>> That was my original intention. But due to the nature of it, it will
>> always be possible to use it with other clocks too. Hence my generic
>> approach.
>> I actually like the idea of making it part of the device config driver.
>> The downside of it is, that this driver seems a bit far from mainline.
>>
>>          S?ren




From mturquette at linaro.org  Tue May 14 14:13:18 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 11:13:18 -0700
Subject: [PATCH v2 2/3] clk: add support for clock reparent on set_rate
In-Reply-To: <1366388904-13903-3-git-send-email-james.hogan@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <1366388904-13903-3-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130514181318.10068.79002@quantum>

Quoting James Hogan (2013-04-19 09:28:23)
> Add core support to allow clock implementations to select the best
> parent clock when rounding a rate, e.g. the one which can provide the
> closest clock rate to that requested. This is by way of adding a new
> clock op, determine_rate(), which is like round_rate() but has an extra
> parameter to allow the clock implementation to optionally select a
> different parent clock. The core then takes care of reparenting the
> clock when setting the rate.
> 

Hi James,

Can you rebase this onto -rc1?  It does not apply cleanly.

Thanks,
Mike

> The parent change takes place with the help of two new private data
> members. struct clk::new_parent specifies a clock's new parent (NULL
> indicates no change), and struct clk::new_child specifies a clock's new
> child (whose new_parent member points back to it). The purpose of these
> are to allow correct walking of the future tree for notifications prior
> to actually reparenting any clocks, specifically to skip child clocks
> who are being reparented to another clock (they will be notified via the
> new parent), and to include any new child clock. These pointers are set
> by clk_calc_subtree(), and the new_child pointer gets cleared when a
> child is actually reparented to avoid duplicate POST_RATE_CHANGE
> notifications.
> 
> Each place where round_rate() is called, determine_rate is checked first
> and called in preference, passing NULL to the new parent argument if not
> needed (e.g. in __clk_round_rate). This restructures a few of the call
> sites to simplify the logic into if/else blocks.
> 
> A new __clk_set_parent_no_recalc() is created similar to
> clk_set_parent() but without calling __clk_recalc_rates(). This is for
> clk_change_rate() to use, where rate recalculation and notifications are
> already handled.
> 
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> ---
>  Documentation/clk.txt        |   4 ++
>  drivers/clk/clk.c            | 146 ++++++++++++++++++++++++++++++-------------
>  include/linux/clk-private.h  |   2 +
>  include/linux/clk-provider.h |   7 +++
>  4 files changed, 116 insertions(+), 43 deletions(-)
> 
> diff --git a/Documentation/clk.txt b/Documentation/clk.txt
> index 1943fae..502c033 100644
> --- a/Documentation/clk.txt
> +++ b/Documentation/clk.txt
> @@ -70,6 +70,10 @@ the operations defined in clk.h:
>                                                 unsigned long parent_rate);
>                 long            (*round_rate)(struct clk_hw *hw, unsigned long,
>                                                 unsigned long *);
> +               long            (*determine_rate)(struct clk_hw *hw,
> +                                               unsigned long rate,
> +                                               unsigned long *best_parent_rate,
> +                                               struct clk **best_parent_clk);
>                 int             (*set_parent)(struct clk_hw *hw, u8 index);
>                 u8              (*get_parent)(struct clk_hw *hw);
>                 int             (*set_rate)(struct clk_hw *hw, unsigned long);
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 79d5deb..cc0e618 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -27,6 +27,8 @@ static HLIST_HEAD(clk_root_list);
>  static HLIST_HEAD(clk_orphan_list);
>  static LIST_HEAD(clk_notifier_list);
>  
> +static int __clk_set_parent_no_recalc(struct clk *clk, struct clk *parent);
> +
>  /***        debugfs support        ***/
>  
>  #ifdef CONFIG_COMMON_CLK_DEBUG
> @@ -727,17 +729,20 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
>         if (!clk)
>                 return 0;
>  
> -       if (!clk->ops->round_rate) {
> -               if (clk->flags & CLK_SET_RATE_PARENT)
> -                       return __clk_round_rate(clk->parent, rate);
> -               else
> -                       return clk->rate;
> -       }
>  
>         if (clk->parent)
>                 parent_rate = clk->parent->rate;
>  
> -       return clk->ops->round_rate(clk->hw, rate, &parent_rate);
> +       if (clk->ops->determine_rate)
> +               return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
> +                                               NULL);
> +       else if (clk->ops->round_rate)
> +               return clk->ops->round_rate(clk->hw, rate, &parent_rate);
> +       else if (clk->flags & CLK_SET_RATE_PARENT)
> +               return __clk_round_rate(clk->parent, rate);
> +       else
> +               return clk->rate;
> +
>  }
>  
>  /**
> @@ -906,18 +911,23 @@ out:
>         return ret;
>  }
>  
> -static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
> +static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
> +                            struct clk *new_parent)
>  {
>         struct clk *child;
>  
>         clk->new_rate = new_rate;
> +       clk->new_parent = new_parent;
> +       clk->new_child = NULL;
> +       if (new_parent && new_parent != clk->parent)
> +               new_parent->new_child = clk;
>  
>         hlist_for_each_entry(child, &clk->children, child_node) {
>                 if (child->ops->recalc_rate)
>                         child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
>                 else
>                         child->new_rate = new_rate;
> -               clk_calc_subtree(child, child->new_rate);
> +               clk_calc_subtree(child, child->new_rate, NULL);
>         }
>  }
>  
> @@ -928,6 +938,7 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
>  static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
>  {
>         struct clk *top = clk;
> +       struct clk *old_parent, *parent;
>         unsigned long best_parent_rate = 0;
>         unsigned long new_rate;
>  
> @@ -936,42 +947,43 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
>                 return NULL;
>  
>         /* save parent rate, if it exists */
> -       if (clk->parent)
> -               best_parent_rate = clk->parent->rate;
> -
> -       /* never propagate up to the parent */
> -       if (!(clk->flags & CLK_SET_RATE_PARENT)) {
> -               if (!clk->ops->round_rate) {
> -                       clk->new_rate = clk->rate;
> -                       return NULL;
> -               }
> -               new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
> +       parent = old_parent = clk->parent;
> +       if (parent)
> +               best_parent_rate = parent->rate;
> +
> +       /* find the closest rate and parent clk/rate */
> +       if (clk->ops->determine_rate) {
> +               new_rate = clk->ops->determine_rate(clk->hw, rate,
> +                                                   &best_parent_rate,
> +                                                   &parent);
> +       } else if (clk->ops->round_rate) {
> +               new_rate = clk->ops->round_rate(clk->hw, rate,
> +                                               &best_parent_rate);
> +       } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
> +               /* pass-through clock without adjustable parent */
> +               clk->new_rate = clk->rate;
> +               return NULL;
> +       } else {
> +               /* pass-through clock with adjustable parent */
> +               top = clk_calc_new_rates(parent, rate);
> +               new_rate = parent->new_rate;
>                 goto out;
>         }
>  
> -       /* need clk->parent from here on out */
> -       if (!clk->parent) {
> -               pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
> +       /* some clocks must be gated to change parent */
> +       if (parent != old_parent &&
> +           (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
> +               pr_debug("%s: %s not gated but wants to reparent\n",
> +                        __func__, clk->name);
>                 return NULL;
>         }
>  
> -       if (!clk->ops->round_rate) {
> -               top = clk_calc_new_rates(clk->parent, rate);
> -               new_rate = clk->parent->new_rate;
> -
> -               goto out;
> -       }
> -
> -       new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
> -
> -       if (best_parent_rate != clk->parent->rate) {
> -               top = clk_calc_new_rates(clk->parent, best_parent_rate);
> -
> -               goto out;
> -       }
> +       if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
> +           best_parent_rate != parent->rate)
> +               top = clk_calc_new_rates(parent, best_parent_rate);
>  
>  out:
> -       clk_calc_subtree(clk, new_rate);
> +       clk_calc_subtree(clk, new_rate, parent);
>  
>         return top;
>  }
> @@ -983,7 +995,7 @@ out:
>   */
>  static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
>  {
> -       struct clk *child, *fail_clk = NULL;
> +       struct clk *child, *tmp_clk, *fail_clk = NULL;
>         int ret = NOTIFY_DONE;
>  
>         if (clk->rate == clk->new_rate)
> @@ -996,9 +1008,19 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
>         }
>  
>         hlist_for_each_entry(child, &clk->children, child_node) {
> -               clk = clk_propagate_rate_change(child, event);
> -               if (clk)
> -                       fail_clk = clk;
> +               /* Skip children who will be reparented to another clock */
> +               if (child->new_parent && child->new_parent != clk)
> +                       continue;
> +               tmp_clk = clk_propagate_rate_change(child, event);
> +               if (tmp_clk)
> +                       fail_clk = tmp_clk;
> +       }
> +
> +       /* handle the new child who might not be in clk->children yet */
> +       if (clk->new_child) {
> +               tmp_clk = clk_propagate_rate_change(clk->new_child, event);
> +               if (tmp_clk)
> +                       fail_clk = tmp_clk;
>         }
>  
>         return fail_clk;
> @@ -1016,6 +1038,10 @@ static void clk_change_rate(struct clk *clk)
>  
>         old_rate = clk->rate;
>  
> +       /* set parent */
> +       if (clk->new_parent && clk->new_parent != clk->parent)
> +               __clk_set_parent_no_recalc(clk, clk->new_parent);
> +
>         if (clk->parent)
>                 best_parent_rate = clk->parent->rate;
>  
> @@ -1030,8 +1056,15 @@ static void clk_change_rate(struct clk *clk)
>         if (clk->notifier_count && old_rate != clk->rate)
>                 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
>  
> -       hlist_for_each_entry(child, &clk->children, child_node)
> +       hlist_for_each_entry(child, &clk->children, child_node) {
> +               /* Skip children who will be reparented to another clock */
> +               if (child->new_parent && child->new_parent != clk)
> +                       continue;
>                 clk_change_rate(child);
> +       }
> +
> +       if (clk->new_child)
> +               clk_change_rate(clk->new_child);
>  }
>  
>  /**
> @@ -1169,7 +1202,7 @@ out:
>         return ret;
>  }
>  
> -void __clk_reparent(struct clk *clk, struct clk *new_parent)
> +void __clk_reparent_no_recalc(struct clk *clk, struct clk *new_parent)
>  {
>  #ifdef CONFIG_COMMON_CLK_DEBUG
>         struct dentry *d;
> @@ -1179,6 +1212,9 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
>         if (!clk || !new_parent)
>                 return;
>  
> +       if (new_parent->new_child == clk)
> +               new_parent->new_child = NULL;
> +
>         hlist_del(&clk->child_node);
>  
>         if (new_parent)
> @@ -1206,6 +1242,11 @@ out:
>  #endif
>  
>         clk->parent = new_parent;
> +}
> +
> +void __clk_reparent(struct clk *clk, struct clk *new_parent)
> +{
> +       __clk_reparent_no_recalc(clk, new_parent);
>  
>         __clk_recalc_rates(clk, POST_RATE_CHANGE);
>  }
> @@ -1270,6 +1311,25 @@ out:
>         return ret;
>  }
>  
> +static int __clk_set_parent_no_recalc(struct clk *clk, struct clk *parent)
> +{
> +       int ret = 0;
> +
> +       if (clk->parent == parent)
> +               goto out;
> +
> +       /* only re-parent if the clock is not in use */
> +       ret = __clk_set_parent(clk, parent);
> +       if (ret)
> +               goto out;
> +
> +       /* reparent, but don't propagate rate recalculation downstream */
> +       __clk_reparent_no_recalc(clk, parent);
> +
> +out:
> +       return ret;
> +}
> +
>  /**
>   * clk_set_parent - switch the parent of a mux clk
>   * @clk: the mux clk whose input we are switching
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index 9c7f580..0826a60 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -35,6 +35,8 @@ struct clk {
>         u8                      num_parents;
>         unsigned long           rate;
>         unsigned long           new_rate;
> +       struct clk              *new_parent;
> +       struct clk              *new_child;
>         unsigned long           flags;
>         unsigned int            enable_count;
>         unsigned int            prepare_count;
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 4e0b634..5fe1d38 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -71,6 +71,10 @@ struct clk_hw;
>   * @round_rate:        Given a target rate as input, returns the closest rate actually
>   *             supported by the clock.
>   *
> + * @determine_rate: Given a target rate as input, returns the closest rate
> + *             actually supported by the clock, and optionally the parent clock
> + *             that should be used to provide the clock rate.
> + *
>   * @get_parent:        Queries the hardware to determine the parent of a clock.  The
>   *             return value is a u8 which specifies the index corresponding to
>   *             the parent clock.  This index can be applied to either the
> @@ -116,6 +120,9 @@ struct clk_ops {
>                                         unsigned long parent_rate);
>         long            (*round_rate)(struct clk_hw *hw, unsigned long,
>                                         unsigned long *);
> +       long            (*determine_rate)(struct clk_hw *hw, unsigned long rate,
> +                                       unsigned long *best_parent_rate,
> +                                       struct clk **best_parent_clk);
>         int             (*set_parent)(struct clk_hw *hw, u8 index);
>         u8              (*get_parent)(struct clk_hw *hw);
>         int             (*set_rate)(struct clk_hw *hw, unsigned long,
> -- 
> 1.8.1.2


From david.lanzendoerfer at o2s.ch  Tue May 14 14:17:46 2013
From: david.lanzendoerfer at o2s.ch (David =?iso-8859-1?Q?Lanzend=F6rfer?=)
Date: Tue, 14 May 2013 20:17:46 +0200
Subject: Naming convention DSI + device tree
Message-ID: <20130514181745.GA2762@mail.o2s.ch>

Hello
I have the following issue:
In order to make the DSI controller react at all, I need to pass him a certain combination of pin states.
Until now within the code of the original android kernel which was using board files this has just been
done by doing bit banging.

namely:
	gpio_set_value(tf201_lvds_shutdown, 1);
	mdelay(20);
	gpio_set_value(TEGRA_GPIO_PH0, 1);
	mdelay(10);
	gpio_set_value(TEGRA_GPIO_PH2, 1);
	mdelay(15);
	gpio_set_value(TEGRA_GPIO_PU2, 0);
	gpio_set_value(TEGRA_GPIO_PU2, 1);
	mdelay(10);
	gpio_set_value(TEGRA_GPIO_PU2, 0);
	mdelay(10);
	gpio_set_value(TEGRA_GPIO_PU2, 1);
	mdelay(15);

Now with a device tree comes the question: Where should I put this?
Also because I don't have the schematics of the TF201 (for obvious reasons)
I won't be able to name the pin assignments of the DSI controller
in a generic driver correctly.
Would be neat if an ASUS engineer with the schematic at hand could
figure out what pins these are and could name the pin assignment.

best regards
David


From gregkh at linuxfoundation.org  Tue May 14 14:26:26 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Tue, 14 May 2013 14:26:26 -0400
Subject: [PATCH] ARM : omap : remove __init for _enable_preprogram
In-Reply-To: <1368547621-8570-1-git-send-email-jp.francois@cynove.com>
References: <1368547621-8570-1-git-send-email-jp.francois@cynove.com>
Message-ID: <20130514182626.GC32651@kroah.com>

On Tue, May 14, 2013 at 06:07:01PM +0200, jp.francois at cynove.com wrote:
> _enable_preprogram is marked as __init, but is called from _enable which is not.
> This results in oops once init is freed.
> Fix this by removing the __init marker.
> 
> Signed-off-by: Jean-Philippe Fran?ois <jp.francois at cynove.com>

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read Documentation/stable_kernel_rules.txt
for how to do this properly.

</formletter>


From ocean_ieee at yahoo.it  Tue May 14 14:31:47 2013
From: ocean_ieee at yahoo.it (ocean)
Date: Tue, 14 May 2013 20:31:47 +0200
Subject: SIGSEGV changing pc register (help for my master thesis on ARM/linux
 kernel)
Message-ID: <51928313.4010902@yahoo.it>

Hi all I'm a student in computer engineering and for my master thesis
(on the security of virtualization on ARM/linux) i really need to
understand this:

i'm trying to make a jump from kernel code (the actual instruction is
blx r3) to a location allocated using mmap, which results in a SIGSEGV:

  mmap_start = 0x57677000;
  mmap_size = sysconf(_SC_PAGE_SIZE);

  if (mmap((void*)mmap_start, mmap_size, PROT_READ|PROT_WRITE|PROT_EXEC,
	   MAP_SHARED|MAP_FIXED|MAP_ANONYMOUS, 0, 0) == MAP_FAILED) {
    printf("mmap failed\n");
    exit(1); }

the actual kernel code is:
0xc05819ec <+204>:	beq	0xc0581a08 <sock_diag_rcv_msg+232>
0xc05819f0 <+208>:	ldr	r3, [r3, #4]
0xc05819f4 <+212>:	mov	r1, r4
0xc05819f8 <+216>:	mov	r0, r6
0xc05819fc <+220>:	blx	r3
0xc0581a00 <+224>:	mov	r4, r0

(for those wondering it's related to CVE-2013-1763)

stepping or trying to change the value with gdb gives that SIGSEGV and
sometimes changes pc with 0x00000008 (that's strange too, i can't
understand why).

"(gdb) ni
KGDB only knows signal 9 (pass) and 15 (pass and disconnect)
Executing a continue without signal passing

Program received signal SIGSEGV, Segmentation fault.
0x00000008 in ?? ()


I've tried also other locations (all mapped correctly, i can read them
with x/x in GDB)

(gdb) set $pc=0x57677FF4
Cannot access memory at address 0x0
(gdb) set $pc=0x57677FF3
Cannot access memory at address 0x0
(gdb) set $pc=0x57677FF1
Cannot access memory at address 0x0
(gdb) set $pc=0x57670001
(gdb) ni
0x57670000 in ?? ()
Cannot access memory at address 0x57670000
(gdb)

strange enough (gdb) set $pc=0x57670001 don't give errors but then i
cannot step on....


Thank you if anyone would help me understand (i'm new to ARM learned all
i know in a few days so please excuse me if it's trivial)

Best Regards
Davide Quarta


From davem at davemloft.net  Tue May 14 14:33:19 2013
From: davem at davemloft.net (David Miller)
Date: Tue, 14 May 2013 11:33:19 -0700 (PDT)
Subject: [PATCHv2] mv643xx_eth: fix NAPI weight being > 64
In-Reply-To: <1368525260-17556-1-git-send-email-andrew@lunn.ch>
References: <1368525260-17556-1-git-send-email-andrew@lunn.ch>
Message-ID: <20130514.113319.1597275156031821180.davem@davemloft.net>

From: Andrew Lunn <andrew at lunn.ch>
Date: Tue, 14 May 2013 11:54:20 +0200

> 3.10-rc1 issues the following warning:
> 
> netif_napi_add() called with weight 128 on device eth%d
> 
> This patch reduce the weight to 64, using NAPI_POLL_WEIGHT.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>

Applied.


From mturquette at linaro.org  Tue May 14 14:54:17 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 11:54:17 -0700
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
Message-ID: <20130514185417.10068.5717@quantum>

Quoting Saravana Kannan (2013-04-30 21:42:08)
> Without this patch, the following race conditions are possible.
> 
> Race condition 1:
> * clk-A has two parents - clk-X and clk-Y.
> * All three are disabled and clk-X is current parent.
> * Thread A: clk_set_parent(clk-A, clk-Y).
> * Thread A: <snip execution flow>
> * Thread A: Grabs enable lock.
> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
> * Thread A: Updates clk-A SW parent to clk-Y
> * Thread A: Releases enable lock.
> * Thread B: clk_enable(clk-A).
> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.
> 
> clk-A is now enabled in software, but not clocking in hardware since the
> hardware parent is still clk-X.
> 
> The only way to avoid race conditions between clk_set_parent() and
> clk_enable/disable() is to ensure that clk_enable/disable() calls don't
> require changes to hardware enable state between changes to software clock
> topology and hardware clock topology.
> 
> There are options to achieve the above:
> 1. Grab the enable lock before changing software/hardware topology and
>    release it afterwards.
> 2. Keep the clock enabled for the duration of software/hardware topology
>    change so that any additional enable/disable calls don't try to change
>    the hardware state. Once the topology change is complete, the clock can
>    be put back in its original enable state.
> 
> Option (1) is not an acceptable solution since the set_parent() ops might
> need to sleep.
> 
> Therefore, this patch implements option (2).
> 
> This patch doesn't violate any API semantics. clk_disable() doesn't
> guarantee that the clock is actually disabled. So, no clients of a clock
> can assume that a clock is disabled after their last call to clk_disable().
> So, enabling the clock during a parent change is not a violation of any API
> semantics.
> 
> This also has the nice side effect of simplifying the error handling code.
> 
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>

I've taken this patch into clk-next for testing.  The code itself looks
fine.  The only thing that remains to be seen is if any platforms have a
problem with disabled clocks getting turned on during a reparent
operation.

On platforms that I have worked on this is OK, but I suppose there could
be some platform out there where a clock is prepared and disabled, and
briefly enabling the clock during the reparent operation somehow puts
the hardware in a bad state.

Anyways that's a long shot and this look OK until somebody screams.

Regards,
Mike

> ---
> It's been a while since I submitted a patch. So, apologies if I'm cc'ing
> people who no longer care about the state of the common clock framework.
> 
>  drivers/clk/clk.c |   72 +++++++++++++++++++++++-----------------------------
>  1 files changed, 32 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 934cfd1..fe4055f 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1377,67 +1377,59 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
>         unsigned long flags;
>         int ret = 0;
>         struct clk *old_parent = clk->parent;
> -       bool migrated_enable = false;
>  
> -       /* migrate prepare */
> -       if (clk->prepare_count)
> +       /*
> +        * Migrate prepare state between parents and prevent race with
> +        * clk_enable().
> +        *
> +        * If the clock is not prepared, then a race with
> +        * clk_enable/disable() is impossible since we already have the
> +        * prepare lock (future calls to clk_enable() need to be preceded by
> +        * a clk_prepare()).
> +        *
> +        * If the clock is prepared, migrate the prepared state to the new
> +        * parent and also protect against a race with clk_enable() by
> +        * forcing the clock and the new parent on.  This ensures that all
> +        * future calls to clk_enable() are practically NOPs with respect to
> +        * hardware and software states.
> +        */
> +       if (clk->prepare_count) {
>                 __clk_prepare(parent);
> -
> -       flags = clk_enable_lock();
> -
> -       /* migrate enable */
> -       if (clk->enable_count) {
> -               __clk_enable(parent);
> -               migrated_enable = true;
> +               clk_enable(parent);
> +               clk_enable(clk);
>         }
>  
>         /* update the clk tree topology */
> +       flags = clk_enable_lock();
>         clk_reparent(clk, parent);
> -
>         clk_enable_unlock(flags);
>  
>         /* change clock input source */
>         if (parent && clk->ops->set_parent)
>                 ret = clk->ops->set_parent(clk->hw, p_index);
> -
>         if (ret) {
> -               /*
> -                * The error handling is tricky due to that we need to release
> -                * the spinlock while issuing the .set_parent callback. This
> -                * means the new parent might have been enabled/disabled in
> -                * between, which must be considered when doing rollback.
> -                */
> -               flags = clk_enable_lock();
>  
> +               flags = clk_enable_lock();
>                 clk_reparent(clk, old_parent);
> -
> -               if (migrated_enable && clk->enable_count) {
> -                       __clk_disable(parent);
> -               } else if (migrated_enable && (clk->enable_count == 0)) {
> -                       __clk_disable(old_parent);
> -               } else if (!migrated_enable && clk->enable_count) {
> -                       __clk_disable(parent);
> -                       __clk_enable(old_parent);
> -               }
> -
>                 clk_enable_unlock(flags);
>  
> -               if (clk->prepare_count)
> +               if (clk->prepare_count) {
> +                       clk_disable(clk);
> +                       clk_disable(parent);
>                         __clk_unprepare(parent);
> -
> +               }
>                 return ret;
>         }
>  
> -       /* clean up enable for old parent if migration was done */
> -       if (migrated_enable) {
> -               flags = clk_enable_lock();
> -               __clk_disable(old_parent);
> -               clk_enable_unlock(flags);
> -       }
> -
> -       /* clean up prepare for old parent if migration was done */
> -       if (clk->prepare_count)
> +       /*
> +        * Finish the migration of prepare state and undo the changes done
> +        * for preventing a race with clk_enable().
> +        */
> +       if (clk->prepare_count) {
> +               clk_disable(clk);
> +               clk_disable(old_parent);
>                 __clk_unprepare(old_parent);
> +       }
>  
>         /* update debugfs with new clk tree topology */
>         clk_debug_reparent(clk, parent);
> -- 
> 1.7.8.3
> 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation


From mturquette at linaro.org  Tue May 14 15:06:41 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 12:06:41 -0700
Subject: [PATCH] clk: ux500: clk-sysctrl: handle clocks with no parents
In-Reply-To: <20130503090305.GA17733@balto.lan>
References: <1367325906-23045-1-git-send-email-fabio.baltieri@linaro.org>
 <CAPDyKFpZ+-6b3kPyNacPQ33=Ssdjs=fvFxkr4iSUT_hm1YzVTg@mail.gmail.com>
 <CAPDyKFq6iQ21QosEH_WqGCetXfaO1uecvK7+WzjZJDkK8r3SxA@mail.gmail.com>
 <20130503090305.GA17733@balto.lan>
Message-ID: <20130514190641.10068.14584@quantum>

Quoting Fabio Baltieri (2013-05-03 02:03:05)
> On Fri, May 03, 2013 at 10:54:09AM +0200, Ulf Hansson wrote:
> > On 3 May 2013 10:51, Ulf Hansson <ulf.hansson at linaro.org> wrote:
> > > On 30 April 2013 14:45, Fabio Baltieri <fabio.baltieri at linaro.org> wrote:
> > >> Fix clk_reg_sysctrl() to set main clock registers of new struct
> > >> clk_sysctrl even if the registered clock has no parents.
> > >>
> > >> This fixes an issue where "ulpclk" was registered with all clk->reg_*
> > >> fields uninitialized, causing a -EINVAL error from clk_prepare().
> > >>
> > >> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> > >> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> > >> ---
> > >>  drivers/clk/ux500/clk-sysctrl.c | 8 +++++++-
> > >>  1 file changed, 7 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
> > >> index bc7e9bd..e364c9d 100644
> > >> --- a/drivers/clk/ux500/clk-sysctrl.c
> > >> +++ b/drivers/clk/ux500/clk-sysctrl.c
> > >> @@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
> > >>                 return ERR_PTR(-ENOMEM);
> > >>         }
> > >>
> > >> -       for (i = 0; i < num_parents; i++) {
> > >> +       /* set main clock registers */
> > >> +       clk->reg_sel[0] = reg_sel[0];
> > >> +       clk->reg_bits[0] = reg_bits[0];
> > >> +       clk->reg_mask[0] = reg_mask[0];
> > >> +
> > >> +       /* handle clocks with more than one parent */
> > >> +       for (i = 1; i < num_parents; i++) {
> > >>                 clk->reg_sel[i] = reg_sel[i];
> > >>                 clk->reg_bits[i] = reg_bits[i];
> > >>                 clk->reg_mask[i] = reg_mask[i];
> > >> --
> > >> 1.8.2
> > >>
> > >
> > > Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> > >
> > > This is bugfix, should go "stable" as well?
> > 
> > Stable means 3.10 rcs, since the abx500 clk tree was added for 3.10.
> 
> Thanks!  Yes, it would be great if this could be queued up for an -rc.
> 

Taken into clk-fixes.

Thanks!
Mike

> Fabio
> 
> -- 
> Fabio Baltieri


From mturquette at linaro.org  Tue May 14 15:13:50 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 12:13:50 -0700
Subject: [PATCH v2] clk: si5351: Allow user to define disabled state for
 every clock output
In-Reply-To: <1367559207-20086-1-git-send-email-marek.belisko@streamunlimited.com>
References: <1367559207-20086-1-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <20130514191350.10068.22100@quantum>

Quoting Marek Belisko (2013-05-02 22:33:27)
> From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> 
> This patch adds platform data and DT bindings to allow to overwrite
> the stored disabled state for each clock output.
> 
> Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>

Taken into clk-next.

Thanks,
Mike

> ---
> Changes from v1->v2:
> Sebastian Hesselbarth send me updated version of patch which was based
> on v1. Resending with updates.
> 
>  .../devicetree/bindings/clock/silabs,si5351.txt    |    5 ++
>  drivers/clk/clk-si5351.c                           |   74 +++++++++++++++++++-
>  drivers/clk/clk-si5351.h                           |    1 +
>  include/linux/platform_data/si5351.h               |   18 +++++
>  4 files changed, 95 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
> index cc37465..66c75b2 100644
> --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt
> +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
> @@ -44,6 +44,11 @@ Optional child node properties:
>  - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
>    divider.
>  - silabs,pll-master: boolean, multisynth can change pll frequency.
> +- silabs,disable-state : clock output disable state, shall be
> +  0 = clock output is driven LOW when disabled
> +  1 = clock output is driven HIGH when disabled
> +  2 = clock output is FLOATING (HIGH-Z) when disabled
> +  3 = clock output is NEVER disabled
>  
>  ==Example==
>  
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index 8323c31..098f28b 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -851,6 +851,41 @@ static int _si5351_clkout_set_drive_strength(
>         return 0;
>  }
>  
> +static int _si5351_clkout_set_disable_state(
> +       struct si5351_driver_data *drvdata, int num,
> +       enum si5351_disable_state state)
> +{
> +       u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
> +               SI5351_CLK7_4_DISABLE_STATE;
> +       u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
> +       u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
> +       u8 val;
> +
> +       if (num > 8)
> +               return -EINVAL;
> +
> +       switch (state) {
> +       case SI5351_DISABLE_LOW:
> +               val = SI5351_CLK_DISABLE_STATE_LOW;
> +               break;
> +       case SI5351_DISABLE_HIGH:
> +               val = SI5351_CLK_DISABLE_STATE_HIGH;
> +               break;
> +       case SI5351_DISABLE_FLOATING:
> +               val = SI5351_CLK_DISABLE_STATE_FLOAT;
> +               break;
> +       case SI5351_DISABLE_NEVER:
> +               val = SI5351_CLK_DISABLE_STATE_NEVER;
> +               break;
> +       default:
> +               return 0;
> +       }
> +
> +       si5351_set_bits(drvdata, reg, mask, val << shift);
> +
> +       return 0;
> +}
> +
>  static int si5351_clkout_prepare(struct clk_hw *hw)
>  {
>         struct si5351_hw_data *hwdata =
> @@ -1225,6 +1260,33 @@ static int si5351_dt_parse(struct i2c_client *client)
>                         }
>                 }
>  
> +               if (!of_property_read_u32(child, "silabs,disable-state",
> +                                         &val)) {
> +                       switch (val) {
> +                       case 0:
> +                               pdata->clkout[num].disable_state =
> +                                       SI5351_DISABLE_LOW;
> +                               break;
> +                       case 1:
> +                               pdata->clkout[num].disable_state =
> +                                       SI5351_DISABLE_HIGH;
> +                               break;
> +                       case 2:
> +                               pdata->clkout[num].disable_state =
> +                                       SI5351_DISABLE_FLOATING;
> +                               break;
> +                       case 3:
> +                               pdata->clkout[num].disable_state =
> +                                       SI5351_DISABLE_NEVER;
> +                               break;
> +                       default:
> +                               dev_err(&client->dev,
> +                                       "invalid disable state %d for clkout %d\n",
> +                                       val, num);
> +                               return -EINVAL;
> +                       }
> +               }
> +
>                 if (!of_property_read_u32(child, "clock-frequency", &val))
>                         pdata->clkout[num].rate = val;
>  
> @@ -1281,9 +1343,6 @@ static int si5351_i2c_probe(struct i2c_client *client,
>  
>         /* Disable interrupts */
>         si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
> -       /* Set disabled output drivers to drive low */
> -       si5351_reg_write(drvdata, SI5351_CLK3_0_DISABLE_STATE, 0x00);
> -       si5351_reg_write(drvdata, SI5351_CLK7_4_DISABLE_STATE, 0x00);
>         /* Ensure pll select is on XTAL for Si5351A/B */
>         if (drvdata->variant != SI5351_VARIANT_C)
>                 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
> @@ -1327,6 +1386,15 @@ static int si5351_i2c_probe(struct i2c_client *client,
>                                 n, pdata->clkout[n].drive);
>                         return ret;
>                 }
> +
> +               ret = _si5351_clkout_set_disable_state(drvdata, n,
> +                                               pdata->clkout[n].disable_state);
> +               if (ret) {
> +                       dev_err(&client->dev,
> +                               "failed set disable state of clkout%d to %d\n",
> +                               n, pdata->clkout[n].disable_state);
> +                       return ret;
> +               }
>         }
>  
>         /* register xtal input clock gate */
> diff --git a/drivers/clk/clk-si5351.h b/drivers/clk/clk-si5351.h
> index af41b50..c0dbf26 100644
> --- a/drivers/clk/clk-si5351.h
> +++ b/drivers/clk/clk-si5351.h
> @@ -81,6 +81,7 @@
>  
>  #define SI5351_CLK3_0_DISABLE_STATE            24
>  #define SI5351_CLK7_4_DISABLE_STATE            25
> +#define  SI5351_CLK_DISABLE_STATE_MASK         3
>  #define  SI5351_CLK_DISABLE_STATE_LOW          0
>  #define  SI5351_CLK_DISABLE_STATE_HIGH         1
>  #define  SI5351_CLK_DISABLE_STATE_FLOAT                2
> diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h
> index 92dabca..5433439 100644
> --- a/include/linux/platform_data/si5351.h
> +++ b/include/linux/platform_data/si5351.h
> @@ -79,6 +79,23 @@ enum si5351_drive_strength {
>  };
>  
>  /**
> + * enum si5351_disable_state - Si5351 clock output disable state
> + * @SI5351_DISABLE_DEFAULT: default, do not change eeprom config
> + * @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled
> + * @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled
> + * @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when
> + *                             disabled
> + * @SI5351_DISABLE_NEVER: CLKx is NEVER disabled
> + */
> +enum si5351_disable_state {
> +       SI5351_DISABLE_DEFAULT = 0,
> +       SI5351_DISABLE_LOW,
> +       SI5351_DISABLE_HIGH,
> +       SI5351_DISABLE_FLOATING,
> +       SI5351_DISABLE_NEVER,
> +};
> +
> +/**
>   * struct si5351_clkout_config - Si5351 clock output configuration
>   * @clkout: clkout number
>   * @multisynth_src: multisynth source clock
> @@ -91,6 +108,7 @@ struct si5351_clkout_config {
>         enum si5351_multisynth_src multisynth_src;
>         enum si5351_clkout_src clkout_src;
>         enum si5351_drive_strength drive;
> +       enum si5351_disable_state disable_state;
>         bool pll_master;
>         unsigned long rate;
>  };
> -- 
> 1.7.9.5


From mturquette at linaro.org  Tue May 14 15:16:50 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 12:16:50 -0700
Subject: [PATCH v2 1/2] clk: si5351: Fix clkout rate computation.
In-Reply-To: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
References: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
Message-ID: <20130514191650.10068.92925@quantum>

Quoting Marek Belisko (2013-05-02 22:53:22)
> Rate was incorrectly computed because we read from wrong divider register.
> 
> Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>

Do either of these patches need to go into clk-fixes?  If so please be
explicit about it in the changelog, the section under the three dashes.

Regards,
Mike

> ---
>  drivers/clk/clk-si5351.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index 8927284..cf39e53 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
>         unsigned char reg;
>         unsigned char rdiv;
>  
> -       if (hwdata->num > 5)
> +       if (hwdata->num <= 5)
>                 reg = si5351_msynth_params_address(hwdata->num) + 2;
>         else
>                 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
> -- 
> 1.7.9.5


From mturquette at linaro.org  Tue May 14 15:22:48 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 12:22:48 -0700
Subject: [PATCH] clk: ux500: abx500-clk: rename ux500 audio codec aliases
In-Reply-To: <1366964092-7672-1-git-send-email-fabio.baltieri@linaro.org>
References: <1366964092-7672-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <20130514192248.10068.29001@quantum>

Quoting Fabio Baltieri (2013-04-26 01:14:52)
> Change soc-audio related clk_register_clkdev() device names to reflect
> the ones actually used in current snd-soc-mop500 and ab8500-codec
> drivers.
> 
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>

Taken into clk-next.

Thanks!
Mike

> ---
>  drivers/clk/ux500/abx500-clk.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c
> index a0fca00..e7bd62c 100644
> --- a/drivers/clk/ux500/abx500-clk.c
> +++ b/drivers/clk/ux500/abx500-clk.c
> @@ -45,7 +45,7 @@ static int ab8500_reg_clks(struct device *dev)
>                                 CLK_IS_ROOT);
>         clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
>         clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
> -       clk_register_clkdev(clk, "sysclk", "ab85xx-codec.0");
> +       clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
>         clk_register_clkdev(clk, "sysclk", "shrm_bus");
>  
>         /* ab8500_sysclk2 */
> @@ -70,19 +70,19 @@ static int ab8500_reg_clks(struct device *dev)
>                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
>                 AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
>                 38400000, 9000, CLK_IS_ROOT);
> -       clk_register_clkdev(clk, "ulpclk", "ab85xx-codec.0");
> +       clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0");
>  
>         /* ab8500_intclk */
>         clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
>                 intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
> -       clk_register_clkdev(clk, "intclk", "ab85xx-codec.0");
> +       clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0");
>         clk_register_clkdev(clk, NULL, "ab8500-pwm.1");
>  
>         /* ab8500_audioclk */
>         clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
>                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
>                 AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
> -       clk_register_clkdev(clk, "audioclk", "ab85xx-codec.0");
> +       clk_register_clkdev(clk, "audioclk", "ab8500-codec.0");
>  
>         return 0;
>  }
> -- 
> 1.8.1.3


From mturquette at linaro.org  Tue May 14 15:26:02 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 12:26:02 -0700
Subject: [PATCH 1/2] clk: sun5i: Add compatibles for Allwinner A13
In-Reply-To: <517FA8F7.1080609@elopez.com.ar>
References: <1367315783-21345-1-git-send-email-maxime.ripard@free-electrons.com>
 <1367315783-21345-2-git-send-email-maxime.ripard@free-electrons.com>
 <517FA8F7.1080609@elopez.com.ar>
Message-ID: <20130514192602.10068.53237@quantum>

Quoting Emilio L?pez (2013-04-30 04:20:23)
> Hi Maxime,
> 
> El 30/04/13 06:56, Maxime Ripard escribi?:
> > The A13 has a lot less clocks than the one found in the Allwinner A10.
> > Add these stripped down clocks to the clock driver and in the
> > documentation.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> 
> This patch looks good to me.
> 
> Acked-by: Emilio L?pez <emilio at elopez.com.ar>
> 

I've taken patch #1 into clk-next.

Thanks!
Mike

> > ---
> >  Documentation/devicetree/bindings/clock/sunxi.txt  | 117 +++------------------
> >  .../bindings/clock/sunxi/sun4i-a10-gates.txt       |  93 ++++++++++++++++
> >  .../bindings/clock/sunxi/sun5i-a13-gates.txt       |  58 ++++++++++
> >  drivers/clk/sunxi/clk-sunxi.c                      |  31 ++++--
> >  4 files changed, 187 insertions(+), 112 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> >  create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> > index 729f524..d495521 100644
> > --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> > @@ -12,22 +12,30 @@ Required properties:
> >       "allwinner,sun4i-axi-clk" - for the AXI clock
> >       "allwinner,sun4i-axi-gates-clk" - for the AXI gates
> >       "allwinner,sun4i-ahb-clk" - for the AHB clock
> > -     "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
> > +     "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
> > +     "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
> >       "allwinner,sun4i-apb0-clk" - for the APB0 clock
> > -     "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
> > +     "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
> > +     "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
> >       "allwinner,sun4i-apb1-clk" - for the APB1 clock
> >       "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
> > -     "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
> > +     "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
> > +     "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
> >  
> >  Required properties for all clocks:
> >  - reg : shall be the control register address for the clock.
> >  - clocks : shall be the input parent clock(s) phandle for the clock
> >  - #clock-cells : from common clock binding; shall be set to 0 except for
> > -     "allwinner,sun4i-*-gates-clk" where it shall be set to 1
> > +     "allwinner,*-gates-clk" where it shall be set to 1
> >  
> > -Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
> > +Additionally, "allwinner,*-gates-clk" clocks require:
> >  - clock-output-names : the corresponding gate names that the clock controls
> >  
> > +Clock consumers should specify the desired clocks they use with a
> > +"clocks" phandle cell. Consumers that are using a gated clock should
> > +provide an additional ID in their clock property. The values of this
> > +ID are documented in sunxi/<soc>-gates.txt.
> > +
> >  For example:
> >  
> >  osc24M: osc24M at 01c20050 {
> > @@ -50,102 +58,3 @@ cpu: cpu at 01c20054 {
> >       reg = <0x01c20054 0x4>;
> >       clocks = <&osc32k>, <&osc24M>, <&pll1>;
> >  };
> > -
> > -
> > -
> > -Gate clock outputs
> > -
> > -The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
> > -their corresponding offsets as present on sun4i are listed below. Note that
> > -some of these gates are not present on sun5i.
> > -
> > -  * AXI gates ("allwinner,sun4i-axi-gates-clk")
> > -
> > -    DRAM                                                                0
> > -
> > -  * AHB gates ("allwinner,sun4i-ahb-gates-clk")
> > -
> > -    USB0                                                                0
> > -    EHCI0                                                               1
> > -    OHCI0                                                               2*
> > -    EHCI1                                                               3
> > -    OHCI1                                                               4*
> > -    SS                                                                  5
> > -    DMA                                                                 6
> > -    BIST                                                                7
> > -    MMC0                                                                8
> > -    MMC1                                                                9
> > -    MMC2                                                                10
> > -    MMC3                                                                11
> > -    MS                                                                  12**
> > -    NAND                                                                13
> > -    SDRAM                                                               14
> > -
> > -    ACE                                                                 16
> > -    EMAC                                                                17
> > -    TS                                                                  18
> > -
> > -    SPI0                                                                20
> > -    SPI1                                                                21
> > -    SPI2                                                                22
> > -    SPI3                                                                23
> > -    PATA                                                                24
> > -    SATA                                                                25**
> > -    GPS                                                                 26*
> > -
> > -    VE                                                                  32
> > -    TVD                                                                 33
> > -    TVE0                                                                34
> > -    TVE1                                                                35
> > -    LCD0                                                                36
> > -    LCD1                                                                37
> > -
> > -    CSI0                                                                40
> > -    CSI1                                                                41
> > -
> > -    HDMI                                                                43
> > -    DE_BE0                                                              44
> > -    DE_BE1                                                              45
> > -    DE_FE0                                                              46
> > -    DE_FE1                                                              47
> > -
> > -    MP                                                                  50
> > -
> > -    MALI400                                                             52
> > -
> > -  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
> > -
> > -    CODEC                                                               0
> > -    SPDIF                                                               1*
> > -    AC97                                                                2
> > -    IIS                                                                 3
> > -
> > -    PIO                                                                 5
> > -    IR0                                                                 6
> > -    IR1                                                                 7
> > -
> > -    KEYPAD                                                              10
> > -
> > -  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
> > -
> > -    I2C0                                                                0
> > -    I2C1                                                                1
> > -    I2C2                                                                2
> > -
> > -    CAN                                                                 4
> > -    SCR                                                                 5
> > -    PS20                                                                6
> > -    PS21                                                                7
> > -
> > -    UART0                                                               16
> > -    UART1                                                               17
> > -    UART2                                                               18
> > -    UART3                                                               19
> > -    UART4                                                               20
> > -    UART5                                                               21
> > -    UART6                                                               22
> > -    UART7                                                               23
> > -
> > -Notation:
> > - [*]:  The datasheet didn't mention these, but they are present on AW code
> > - [**]: The datasheet had this marked as "NC" but they are used on AW code
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> > new file mode 100644
> > index 0000000..6a03475
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> > @@ -0,0 +1,93 @@
> > +Gate clock outputs
> > +------------------
> > +
> > +  * AXI gates ("allwinner,sun4i-axi-gates-clk")
> > +
> > +    DRAM                                     0
> > +
> > +  * AHB gates ("allwinner,sun4i-ahb-gates-clk")
> > +
> > +    USB0                                     0
> > +    EHCI0                                    1
> > +    OHCI0                                    2*
> > +    EHCI1                                    3
> > +    OHCI1                                    4*
> > +    SS                                               5
> > +    DMA                                              6
> > +    BIST                                     7
> > +    MMC0                                     8
> > +    MMC1                                     9
> > +    MMC2                                     10
> > +    MMC3                                     11
> > +    MS                                               12**
> > +    NAND                                     13
> > +    SDRAM                                    14
> > +
> > +    ACE                                              16
> > +    EMAC                                     17
> > +    TS                                               18
> > +
> > +    SPI0                                     20
> > +    SPI1                                     21
> > +    SPI2                                     22
> > +    SPI3                                     23
> > +    PATA                                     24
> > +    SATA                                     25**
> > +    GPS                                              26*
> > +
> > +    VE                                               32
> > +    TVD                                              33
> > +    TVE0                                     34
> > +    TVE1                                     35
> > +    LCD0                                     36
> > +    LCD1                                     37
> > +
> > +    CSI0                                     40
> > +    CSI1                                     41
> > +
> > +    HDMI                                     43
> > +    DE_BE0                                   44
> > +    DE_BE1                                   45
> > +    DE_FE1                                   46
> > +    DE_FE1                                   47
> > +
> > +    MP                                               50
> > +
> > +    MALI400                                  52
> > +
> > +  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
> > +
> > +    CODEC                                    0
> > +    SPDIF                                    1*
> > +    AC97                                     2
> > +    IIS                                              3
> > +
> > +    PIO                                              5
> > +    IR0                                              6
> > +    IR1                                              7
> > +
> > +    KEYPAD                                   10
> > +
> > +  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
> > +
> > +    I2C0                                     0
> > +    I2C1                                     1
> > +    I2C2                                     2
> > +
> > +    CAN                                              4
> > +    SCR                                              5
> > +    PS20                                     6
> > +    PS21                                     7
> > +
> > +    UART0                                    16
> > +    UART1                                    17
> > +    UART2                                    18
> > +    UART3                                    19
> > +    UART4                                    20
> > +    UART5                                    21
> > +    UART6                                    22
> > +    UART7                                    23
> > +
> > +Notation:
> > + [*]:  The datasheet didn't mention these, but they are present on AW code
> > + [**]: The datasheet had this marked as "NC" but they are used on AW code
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> > new file mode 100644
> > index 0000000..006b6df
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> > @@ -0,0 +1,58 @@
> > +Gate clock outputs
> > +------------------
> > +
> > +  * AXI gates ("allwinner,sun4i-axi-gates-clk")
> > +
> > +    DRAM                                     0
> > +
> > +  * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
> > +
> > +    USBOTG                                   0
> > +    EHCI                                     1
> > +    OHCI                                     2
> > +
> > +    SS                                               5
> > +    DMA                                              6
> > +    BIST                                     7
> > +    MMC0                                     8
> > +    MMC1                                     9
> > +    MMC2                                     10
> > +
> > +    NAND                                     13
> > +    SDRAM                                    14
> > +
> > +    SPI0                                     20
> > +    SPI1                                     21
> > +    SPI2                                     22
> > +
> > +    STIMER                                   28
> > +
> > +    VE                                               32
> > +
> > +    LCD                                              36
> > +
> > +    CSI                                              40
> > +
> > +    DE_BE                                    44
> > +
> > +    DE_FE                                    46
> > +
> > +    IEP                                              51
> > +    MALI400                                  52
> > +
> > +  * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
> > +
> > +    CODEC                                    0
> > +
> > +    PIO                                              5
> > +    IR                                               6
> > +
> > +  * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
> > +
> > +    I2C0                                     0
> > +    I2C1                                     1
> > +    I2C2                                     2
> > +
> > +    UART1                                    17
> > +
> > +    UART3                                    19
> > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> > index 8492ad1..930d36f 100644
> > --- a/drivers/clk/sunxi/clk-sunxi.c
> > +++ b/drivers/clk/sunxi/clk-sunxi.c
> > @@ -333,22 +333,34 @@ struct gates_data {
> >       DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> >  };
> >  
> > -static const __initconst struct gates_data axi_gates_data = {
> > +static const __initconst struct gates_data sun4i_axi_gates_data = {
> >       .mask = {1},
> >  };
> >  
> > -static const __initconst struct gates_data ahb_gates_data = {
> > +static const __initconst struct gates_data sun4i_ahb_gates_data = {
> >       .mask = {0x7F77FFF, 0x14FB3F},
> >  };
> >  
> > -static const __initconst struct gates_data apb0_gates_data = {
> > +static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
> > +     .mask = {0x107067e7, 0x185111},
> 
> If you send a v2 please use uppercase e and a below for consistency.
> 
> > +};
> > +
> > +static const __initconst struct gates_data sun4i_apb0_gates_data = {
> >       .mask = {0x4EF},
> >  };
> >  
> > -static const __initconst struct gates_data apb1_gates_data = {
> > +static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
> > +     .mask = {0x61},
> > +};
> > +
> > +static const __initconst struct gates_data sun4i_apb1_gates_data = {
> >       .mask = {0xFF00F7},
> >  };
> >  
> > +static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
> > +     .mask = {0xa0007},
> 
> > +};
> > +
> >  static void __init sunxi_gates_clk_setup(struct device_node *node,
> >                                        struct gates_data *data)
> >  {
> > @@ -428,10 +440,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
> >  
> >  /* Matches for gate clocks */
> >  static const __initconst struct of_device_id clk_gates_match[] = {
> > -     {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
> > -     {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
> > -     {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
> > -     {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
> > +     {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
> > +     {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
> > +     {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
> > +     {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
> > +     {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
> > +     {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
> > +     {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
> >       {}
> >  };
> >  
> > 
> 
> Thanks!
> 
> Emilio


From nicolas.pitre at linaro.org  Tue May 14 15:28:13 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 14 May 2013 15:28:13 -0400 (EDT)
Subject: [PATCH] ARM: DMA-mapping: mark all !DMA_TO_DEVICE pages in
 unmapping as clean
In-Reply-To: <1367572365-18905-1-git-send-email-ming.lei@canonical.com>
References: <1367572365-18905-1-git-send-email-ming.lei@canonical.com>
Message-ID: <alpine.LFD.2.03.1305141445480.31158@syhkavp.arg>

On Fri, 3 May 2013, Ming Lei wrote:

> It is common for one sg to include many pages, so mark all these
> pages as clean to avoid unnecessary flushing on them in
> set_pte_at() or update_mmu_cache().

[...]

> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index e9db6b4..e63124a 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -879,10 +879,23 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
>  	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
>  
>  	/*
> -	 * Mark the D-cache clean for this page to avoid extra flushing.
> +	 * Mark the D-cache clean for these pages to avoid extra flushing.
>  	 */
> -	if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
> -		set_bit(PG_dcache_clean, &page->flags);
> +	if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
> +		unsigned long pfn;
> +		size_t left = size;
> +
> +		pfn = page_to_pfn(page);

Could the offset ever be greater than a page?  The code in 
dma_cache_maint_page() appears to be written with that possibility in 
mind.  So you should have:

	pfn = page_to_pfn(page) + off / PAGE_SIZE;

> +		if (off) {
> +			pfn++;
> +			left -= PAGE_SIZE - off % PAGE_SIZE;
> +		}
> +		while (left >= PAGE_SIZE) {
> +			page = pfn_to_page(pfn++);
> +			set_bit(PG_dcache_clean, &page->flags);
> +			left -= PAGE_SIZE;
> +		}
> +	}
>  }

Otherwise this looks fine to me.


Nicolas


From lauraa at codeaurora.org  Tue May 14 15:33:50 2013
From: lauraa at codeaurora.org (Laura Abbott)
Date: Tue, 14 May 2013 12:33:50 -0700
Subject: [PATCHv2] arm: mm: Use phys_addr_t properly for ioremap functions
Message-ID: <1368560031-19367-1-git-send-email-lauraa@codeaurora.org>

Several of the ioremap functions use unsigned long in places
resulting in truncation if physical addresses greater than
4G are passed in. Change the types of the functions and the
callers accordingly.

Cc: Krzysztof Halasa <khc at pm.waw.pl>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Laura Abbott <lauraa at codeaurora.org>
---
 arch/arm/include/asm/io.h     |    8 ++++----
 arch/arm/mach-ebsa110/core.c  |    2 +-
 arch/arm/mach-imx/mm-imx3.c   |    2 +-
 arch/arm/mach-iop13xx/io.c    |    2 +-
 arch/arm/mach-ixp4xx/common.c |    2 +-
 arch/arm/mach-msm/common.h    |    2 +-
 arch/arm/mach-msm/io.c        |    2 +-
 arch/arm/mm/ioremap.c         |   10 +++++-----
 arch/arm/mm/nommu.c           |    6 +++---
 9 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 652b560..d070741 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -130,16 +130,16 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
  */
 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
 	size_t, unsigned int, void *);
-extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
+extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
 	void *);
 
 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
+extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
+extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
 extern void __arm_iounmap(volatile void __iomem *addr);
 
-extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
 	unsigned int, void *);
 extern void (*arch_iounmap)(volatile void __iomem *);
 
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..8a53f34 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void)
 	iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
 					    unsigned int flags, void *caller)
 {
 	return (void __iomem *)cookie;
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a6..eed32ca 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -65,7 +65,7 @@ static void imx3_idle(void)
 		: "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
 					 unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 183dc8b..faaf7d4 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,7 +23,7 @@
 
 #include "pci.h"
 
-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
 	size_t size, unsigned int mtype, void *caller)
 {
 	void __iomem * retval;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..d7223b3 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -559,7 +559,7 @@ void ixp4xx_restart(char mode, const char *cmd)
  * fallback to the default.
  */
 
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
 					   unsigned int mtype, void *caller)
 {
 	if (!is_pci_memory(addr))
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index ce8215a..421cf77 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,7 +23,7 @@ extern void msm_map_msm8x60_io(void);
 extern void msm_map_msm8960_io(void);
 extern void msm_map_qsd8x50_io(void);
 
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 					  unsigned int mtype, void *caller);
 
 extern struct smp_operations msm_smp_ops;
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 123ef9c..fd65b6d 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -172,7 +172,7 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
-void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 				   unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 04d9006..f123d6e 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -331,10 +331,10 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
 	return (void __iomem *) (offset + addr);
 }
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 	unsigned int mtype, void *caller)
 {
-	unsigned long last_addr;
+	phys_addr_t last_addr;
  	unsigned long offset = phys_addr & ~PAGE_MASK;
  	unsigned long pfn = __phys_to_pfn(phys_addr);
 
@@ -367,12 +367,12 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
 				      unsigned int, void *) =
 	__arm_ioremap_caller;
 
 void __iomem *
-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+__arm_ioremap(phys_addr_t phys_addr, size_t size, unsigned int mtype)
 {
 	return arch_ioremap_caller(phys_addr, size, mtype,
 		__builtin_return_address(0));
@@ -387,7 +387,7 @@ EXPORT_SYMBOL(__arm_ioremap);
  * CONFIG_GENERIC_ALLOCATOR for allocating external memory.
  */
 void __iomem *
-__arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
+__arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
 {
 	unsigned int mtype;
 
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f..31bd77b 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -81,16 +81,16 @@ void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
 	return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
 
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
 			    unsigned int mtype)
 {
 	return (void __iomem *)phys_addr;
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 				   unsigned int mtype, void *caller)
 {
 	return __arm_ioremap(phys_addr, size, mtype);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From nico at fluxnic.net  Tue May 14 15:54:51 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 14 May 2013 15:54:51 -0400 (EDT)
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <5188B8B2.5030601@arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz> <5188B8B2.5030601@arm.com>
Message-ID: <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>

[ Yes, I'm late to the party ]

On Tue, 7 May 2013, Marc Zyngier wrote:

> On 07/05/13 00:16, Pavel Machek wrote:
> 
> Hi Pawel,
> 
> >> Now that we support a timer-backed delay loop, I'm quickly getting sick
> >> and tired of people complaining that their beloved bogomips value has
> >> decreased. You know who you are!
> > 
> >> Unfortunately, we can't just remove the entry from /proc/cpuinfo, as it
> >> will likely break fragile userspace code which is parsing that stuff, so
> >> instead replace it with a dummy value that can be chosen in the
> >> Kconfig.
> > 
> > So, instead of removing it you silently report invalid value? Note
> 
> Removing it would be an ABI breakage. Unfortunately.

Did you really write this with a straight face?

> Name one userspace application that extracts meaningful information out
> of the BogoMIPS field. Just one.

Waitaminute... Didn't you just claim this would be an ABI break?

So if no application can be found, where is the ABI breakage?

This thread must be a joke.  Please just kill the damn thing out of 
/proc/cpuinfo and see if any application notices.  And if some do then 
they are already broken *today* and should be fixed.


Nicolas


From davem at davemloft.net  Tue May 14 16:04:50 2013
From: davem at davemloft.net (David Miller)
Date: Tue, 14 May 2013 13:04:50 -0700 (PDT)
Subject: [PATCH v2] net/macb: fix ISR clear-on-write behavior only for
 some SoC
In-Reply-To: <20130514162450.GF22508@game.jcrosoft.org>
References: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com>
 <1368536416-18364-1-git-send-email-nicolas.ferre@atmel.com>
 <20130514162450.GF22508@game.jcrosoft.org>
Message-ID: <20130514.130450.144239429801008287.davem@davemloft.net>

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Date: Tue, 14 May 2013 18:24:50 +0200

> On 15:00 Tue 14 May     , Nicolas Ferre wrote:
>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>> introduces clear-on-write on ISR register. This behavior is not always
>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>> We are using the Design Configuration Register 1 information and a capability
>> property to actually activate this clear-on-write behavior on ISR.
>> 
>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Applied, thanks.


From james.hogan at imgtec.com  Tue May 14 16:35:20 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Tue, 14 May 2013 21:35:20 +0100
Subject: [PATCH v2 2/3] clk: add support for clock reparent on set_rate
In-Reply-To: <20130514181318.10068.79002@quantum>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <1366388904-13903-3-git-send-email-james.hogan@imgtec.com>
 <20130514181318.10068.79002@quantum>
Message-ID: <CAAG0J9_ScDGDvk4NF_ojLb1MgB0mA60htR3ay2Z4EvFvNRT1Dw@mail.gmail.com>

On 14 May 2013 19:13, Mike Turquette <mturquette at linaro.org> wrote:
> Quoting James Hogan (2013-04-19 09:28:23)
>> Add core support to allow clock implementations to select the best
>> parent clock when rounding a rate, e.g. the one which can provide the
>> closest clock rate to that requested. This is by way of adding a new
>> clock op, determine_rate(), which is like round_rate() but has an extra
>> parameter to allow the clock implementation to optionally select a
>> different parent clock. The core then takes care of reparenting the
>> clock when setting the rate.
>>
>
> Hi James,
>
> Can you rebase this onto -rc1?  It does not apply cleanly.

Hi Mike,

Sure, I rebased onto clk-next the other day so I'll update to rc1 and
resubmit tomorrow.

Cheers
James


From robherring2 at gmail.com  Tue May 14 16:39:00 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 14 May 2013 15:39:00 -0500
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <CAGNsrLDw0_yX9nkLYDg0e8-551P7r43UxziTp1TXyyxdiKR5nA@mail.gmail.com>
References: <CAK5ve-KXdS8az=Gtja-mF=Z3_EeZVA7bLYSU0EE2mf5bHmSUKw@mail.gmail.com>
 <CAK5ve-KBDyvjNRVMcXgfnhYcajdcGsuAKaepzCBt+epiXoYvSw@mail.gmail.com>
 <517ED12B.8080502@wwwdotorg.org> <20130504133004.GC24282@game.jcrosoft.org>
 <CACRpkdbBVJtWrRO+J=pWjfLXTcVKX++x-eeJQXGeQn_WOURUNQ@mail.gmail.com>
 <20130505112819.GD24282@game.jcrosoft.org>
 <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
 <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>
 <CAOesGMiqrXSPdEtUzGCuAuhdE4K7FVe65zMM962XuOrO555hnQ@mail.gmail.com>
 <CAGNsrLDw0_yX9nkLYDg0e8-551P7r43UxziTp1TXyyxdiKR5nA@mail.gmail.com>
Message-ID: <5192A0E4.2070202@gmail.com>

On 05/09/2013 12:51 PM, Fathi Boudra wrote:
> On 9 May 2013 19:13, Olof Johansson <olof at lixom.net> wrote:
>> On Thu, May 9, 2013 at 6:25 AM, Grant Likely <grant.likely at secretlab.ca> wrote:
>>> On Mon, May 6, 2013 at 9:12 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
>>>> On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
>> Yes, a builder is quite useful. Several of us do our own builds as well.
>>
>> When it comes to boot coverage, I'm not sure how successful a central
>> approach would be. It's something where I think Linaro could
>> contribute a lot for their member platforms, but I haven't seen much
>> engagement there yet.
> 
> My previous post was lost. Sorry to repost..
> 
> We've got a jenkins instance doing daily builds on various trees and
> boot testing on the few boards we've got in the lab:
> https://ci.linaro.org/jenkins/view/kernel-ci/
> 
> But it hasn't attracted much interest so far... It's been here since a year.

Perhaps because there is no useful information there that I can find.
Where does it say what failed in the build? I see no artifacts or useful
console output.

It seems it was designed with Linaro's needs in mind and not kernel
maintainers' needs.

Rob

> 
>> Beyond there, I'd say the expectation is that each maintainer should
>> keep an eye on their own platforms. They _should_ try building and
>> booting linux-next on their platforms, to catch regressions early. And
>> definitely around now, I'd like to see people boot mainline on their
>> platforms to make sure we haven't added any severe regressions in the
>> 3.10 merge window, etc. Some people are really good at this, others
>> less so.
>>
>> What's the old saying, you can lead a horse to water but you can't
>> make him drink? You can build a boot test cluster but you can't make
>> anyone pay attention to it. :(
>>
>> -Olof
> 
> Cheers,
> 
> Fathi
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From james.hogan at imgtec.com  Tue May 14 17:01:18 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Tue, 14 May 2013 22:01:18 +0100
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <20130514165937.10068.18501@quantum>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <20130513195746.10068.92303@quantum>
 <CAAG0J991BCziPFddzBrx9vcwRxyRgcCd38A01uKXTDDK9xTnbQ@mail.gmail.com>
 <20130514165937.10068.18501@quantum>
Message-ID: <5192A61E.5020605@imgtec.com>

Hi Mike,

On 14/05/13 17:59, Mike Turquette wrote:
> Quoting James Hogan (2013-05-13 14:30:46)
>> On 13 May 2013 20:57, Mike Turquette <mturquette at linaro.org> wrote:
>>> One reason for this is the difficulty some have had with setting flags
>>> from DT bindings.
>>
>> Could you elaborate on this? I've been adding flags to DT bindings for
>> this sort of thing, but it feels a bit like it's in that grey area of
>> not really describing the hardware itself. This information needs to
>> be specified somehow though.
>>
> 
> It depends on the flag.  A good example is the CLK_DIVIDER_ONE_BASED
> flag which does describe the hardware.  It informs the binding that
> indexing starts at 1, not 0, which is a valid part of the hardware
> description.
> 
> However flags that deal with software policy do not belong on DT.
> CLK_SET_RATE_PARENT certainly does not belong in the DT binding since
> this is a pure Linux-ism.  Every binding just needs to be reviewed on a
> case-by-case basis to make sure the flags are related only to the
> hardware.

So given the desire to eliminate platform code, is there a particular
way that these other flags can be specified instead of DT bindings?

Cheers
James



From skannan at codeaurora.org  Tue May 14 17:03:04 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 14 May 2013 14:03:04 -0700
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <20130514185417.10068.5717@quantum>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <20130514185417.10068.5717@quantum>
Message-ID: <5192A688.3040007@codeaurora.org>

On 05/14/2013 11:54 AM, Mike Turquette wrote:
> Quoting Saravana Kannan (2013-04-30 21:42:08)
>> Without this patch, the following race conditions are possible.
>>
>> Race condition 1:
>> * clk-A has two parents - clk-X and clk-Y.
>> * All three are disabled and clk-X is current parent.
>> * Thread A: clk_set_parent(clk-A, clk-Y).
>> * Thread A: <snip execution flow>
>> * Thread A: Grabs enable lock.
>> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
>> * Thread A: Updates clk-A SW parent to clk-Y
>> * Thread A: Releases enable lock.
>> * Thread B: clk_enable(clk-A).
>> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.
>>
>> clk-A is now enabled in software, but not clocking in hardware since the
>> hardware parent is still clk-X.
>>
>> The only way to avoid race conditions between clk_set_parent() and
>> clk_enable/disable() is to ensure that clk_enable/disable() calls don't
>> require changes to hardware enable state between changes to software clock
>> topology and hardware clock topology.
>>
>> There are options to achieve the above:
>> 1. Grab the enable lock before changing software/hardware topology and
>>     release it afterwards.
>> 2. Keep the clock enabled for the duration of software/hardware topology
>>     change so that any additional enable/disable calls don't try to change
>>     the hardware state. Once the topology change is complete, the clock can
>>     be put back in its original enable state.
>>
>> Option (1) is not an acceptable solution since the set_parent() ops might
>> need to sleep.
>>
>> Therefore, this patch implements option (2).
>>
>> This patch doesn't violate any API semantics. clk_disable() doesn't
>> guarantee that the clock is actually disabled. So, no clients of a clock
>> can assume that a clock is disabled after their last call to clk_disable().
>> So, enabling the clock during a parent change is not a violation of any API
>> semantics.
>>
>> This also has the nice side effect of simplifying the error handling code.
>>
>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>
> I've taken this patch into clk-next for testing.  The code itself looks
> fine.

Thanks Mike. I'll send it out again with some typo/grammar corrections.

> The only thing that remains to be seen is if any platforms have a
> problem with disabled clocks getting turned on during a reparent
> operation.

I would think that would be a general issue with the clock APIs since 
disable doesn't guarantee a disable (since it's ref counted).

Also, those clocks could be marked as CLK_SET_PARENT_GATE if it's a real 
issue.

> On platforms that I have worked on this is OK, but I suppose there could
> be some platform out there where a clock is prepared and disabled, and
> briefly enabling the clock during the reparent operation somehow puts
> the hardware in a bad state.

I can't think of any either, but as I mentioned, we have 
CLK_SET_PARENT_GATE for that.

Thanks,
Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From swarren at wwwdotorg.org  Tue May 14 17:03:14 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 May 2013 15:03:14 -0600
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
Message-ID: <5192A692.4010700@wwwdotorg.org>

On 05/14/2013 01:15 AM, Jongsung Kim wrote:
> Stephen Warren <swarren at wwwdotorg.org> :
>> For reference, the AMBA periphid of the UART device there is 0x00341011.
>> The nibble "3" is the revision being tested in:
> 
> The UART device has periphid 0x00341011, and is compatible with the
> original PL011 prior to r1p5. Not with r1p5. It could be a possible
> way to specify the compatible periphid (such as 0x00241011) instead
> of just 0x0 when initializing the amba_device for the UART.
> 
>>> +static unsigned int get_fifosize_arm(unsigned int periphid)
>>> +{
>>> +	unsigned int rev = (periphid >> 20) & 0xf;
>>> +	return rev < 3 ? 16 : 32;
>>> +}
...
> Doesn't the BCM2835 UART have anything different from the ARM PL011?
> What about the UARTPCellID registers? They are set to 0xb105f00d with
> the ARM PL011.

Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
for the BCM2835 chip), I see:

=====
The UART provides:
* Separate 16x8 transmit and 16x12 receive FIFO memory.
...
For the in-depth UART overview, please, refer to the ARM PrimeCell UART
(PL011) Revision: r1p5 Technical Reference Manual.
=====

That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO. Perhaps this is a configurable property of the IP block, not
something that all r1p5 have?

I can't check the UARTPCellID registers right now.


From tony at atomide.com  Tue May 14 17:13:29 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 14 May 2013 14:13:29 -0700
Subject: OMAP baseline test results for v3.9
In-Reply-To: <alpine.DEB.2.00.1305081933270.19747@utopia.booyaka.com>
References: <alpine.DEB.2.00.1305081933270.19747@utopia.booyaka.com>
Message-ID: <20130514211328.GC5600@atomide.com>

Hi,

* Paul Walmsley <paul at pwsan.com> [130508 12:45]:
> 
> PM off, dynamic idle:
>     FAIL ( 2/ 5): 4430es2panda, 4460pandaes
>     Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm

Looking at your pm logs, 3730beaglexm won't hit off-idle.
I've pasted the relevant lines from your logs below.

Is this a known issue?

Regards,

Tony


3530es3beagle hits OFF:
core_pwrdm (ON),OFF:24,RET:41,INA:0,ON:66,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0

3730beaglexm won't hit OFF:
core_pwrdm (ON),OFF:0,RET:88,INA:0,ON:89,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0

37xxevm hits OFF:
core_pwrdm (ON),OFF:8,RET:10,INA:0,ON:19,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0


From paul at pwsan.com  Tue May 14 17:19:12 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 14 May 2013 21:19:12 +0000 (UTC)
Subject: OMAP baseline test results for v3.9
In-Reply-To: <20130514211328.GC5600@atomide.com>
References: <alpine.DEB.2.00.1305081933270.19747@utopia.booyaka.com>
 <20130514211328.GC5600@atomide.com>
Message-ID: <alpine.DEB.2.00.1305142116001.4368@utopia.booyaka.com>

On Tue, 14 May 2013, Tony Lindgren wrote:

> Hi,
> 
> * Paul Walmsley <paul at pwsan.com> [130508 12:45]:
> > 
> > PM off, dynamic idle:
> >     FAIL ( 2/ 5): 4430es2panda, 4460pandaes
> >     Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm
> 
> Looking at your pm logs, 3730beaglexm won't hit off-idle.
> I've pasted the relevant lines from your logs below.
> 
> Is this a known issue?

Yes, the Beagle XM in my testbed is a 3630ES1.0.  From the PM logs:

[   63.154418] omap3_pm_off_mode_enable: Core OFF disabled due to errata 
i583

I should probably clarify how this is reported in the test results.


- Paul


From pebolle at tiscali.nl  Tue May 14 18:02:57 2013
From: pebolle at tiscali.nl (Paul Bolle)
Date: Wed, 15 May 2013 00:02:57 +0200
Subject: hwrng: picoxcell: PICOXCELL_PC3X3?
Message-ID: <1368568977.1350.142.camel@x61.thuisdomein>

0) Support for "Picochip picoXcell true random number generator[s]" was
added in commit 5efb94ee14 ("hwrng: pixocell - add support for picoxcell
TRNG"). Its Kconfig symbol (HW_RANDOM_PICOXCELL) depends on
PICOXCELL_PC3X3. But that symbol is not included in mainline. I found no
trace of it ever since support for this TRNG got added in v2.6.39. This
means this code has never been buildable in mainline.

Why does this code depend on PICOXCELL_PC3X3?

1) Slightly related: by what magic are picoxcell-pc7302-pc3x3.dts and
picoxcell-pc3x3.dtsi hooked into the build system? Or are dts and dtsi
files, well, special and not directly linked into the build system?


Paul Bolle



From laurent.pinchart at ideasonboard.com  Tue May 14 18:07:54 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 00:07:54 +0200
Subject: [PATCH 1/3] ARM: shmobile: irqpin: fix handling of spurious
 interrupts in DT case
In-Reply-To: <20130328053044.GA25938@verge.net.au>
References: <Pine.LNX.4.64.1303211659580.32438@axis700.grange>
 <20130327104747.GE3040@verge.net.au> <20130328053044.GA25938@verge.net.au>
Message-ID: <9440947.bdAq5SKB5F@avalon>

On Thursday 28 March 2013 14:30:45 Simon Horman wrote:
> On Wed, Mar 27, 2013 at 07:47:47PM +0900, Simon Horman wrote:
> > On Thu, Mar 21, 2013 at 05:05:36PM +0100, Guennadi Liakhovetski wrote:
> > > To disable spurious interrupts, that get triggered on certain hardware,
> > > the irqpin driver masks them on the parent interrupt controller. To
> > > specify such broken devices a .control_parent parameter can be provided
> > > in the platform data. In the DT case we need a property, to do the same.
> > > However, this is not enough to correctly handle spurious interrupts in
> > > the DT case. In the non-DT case all interrupts get mapped statically
> > > during probing, therefore, if a spurious interrupt arrives, it can
> > > easily be mapped back to hardware registers and bits and handled. In the
> > > DT case interrupts are mapped only when a device, using that interrupt
> > > is instantiated from DT. So, spurious interrupts occur unmapped and thus
> > > cannot be handled properly. This patch fixes this by mapping such
> > > interrupts as they occur.
> > > 
> > > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> > 
> > Thanks, queued up for v3.10 in the intc-external-irq branch of the renesas
> > tree.
>
> As requested by Magnus I have dropped this patch.

I'm running into similar spurious interrupt issues on both kzm9g-reference and 
marzen-reference. Magnus, you've rejected this patch, how would you like the 
issue to be fixed ? Could you please provide a patch ? This is blocking 
pinctrl DT testing, as I can't get any board to boot properly through DT with 
ethernet support.

-- 
Regards,

Laurent Pinchart



From mturquette at linaro.org  Tue May 14 18:15:25 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 14 May 2013 15:15:25 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <5192A61E.5020605@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <20130513195746.10068.92303@quantum>
 <CAAG0J991BCziPFddzBrx9vcwRxyRgcCd38A01uKXTDDK9xTnbQ@mail.gmail.com>
 <20130514165937.10068.18501@quantum> <5192A61E.5020605@imgtec.com>
Message-ID: <20130514221525.10068.86581@quantum>

Quoting James Hogan (2013-05-14 14:01:18)
> Hi Mike,
> 
> On 14/05/13 17:59, Mike Turquette wrote:
> > Quoting James Hogan (2013-05-13 14:30:46)
> >> On 13 May 2013 20:57, Mike Turquette <mturquette at linaro.org> wrote:
> >>> One reason for this is the difficulty some have had with setting flags
> >>> from DT bindings.
> >>
> >> Could you elaborate on this? I've been adding flags to DT bindings for
> >> this sort of thing, but it feels a bit like it's in that grey area of
> >> not really describing the hardware itself. This information needs to
> >> be specified somehow though.
> >>
> > 
> > It depends on the flag.  A good example is the CLK_DIVIDER_ONE_BASED
> > flag which does describe the hardware.  It informs the binding that
> > indexing starts at 1, not 0, which is a valid part of the hardware
> > description.
> > 
> > However flags that deal with software policy do not belong on DT.
> > CLK_SET_RATE_PARENT certainly does not belong in the DT binding since
> > this is a pure Linux-ism.  Every binding just needs to be reviewed on a
> > case-by-case basis to make sure the flags are related only to the
> > hardware.
> 
> So given the desire to eliminate platform code, is there a particular
> way that these other flags can be specified instead of DT bindings?
> 

I haven't put too much thought into this.  There have been many
discussions lately about where to put configuration data, which would
include the "policy" flags.  Some folks have discussed using DT, but
keeping the config data separate from the hardware description data (one
thread I read called the idea "config tree").  Examples of this are
setting parents for mux clocks, or setting clock rates at boot-time.
This data is important, but it is a configuration of the hardware.  Not
a description of it.

Anyways it is a general problem, so I'm hoping someone will find a
general solution.  For now I've seen a couple instance of clock drivers
including clk-private.h to modify the flags at registration time, which
is beyond horrible.  But again those users may not have a better option,
short of a new clk_set_flags() function, which is also horrible.

Regards,
Mike

> Cheers
> James


From tomasz.figa at gmail.com  Tue May 14 18:10:06 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Wed, 15 May 2013 00:10:06 +0200
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <20130514185417.10068.5717@quantum>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <20130514185417.10068.5717@quantum>
Message-ID: <9066674.E2RzuEn3ap@flatron>

Hi,

On Tuesday 14 of May 2013 11:54:17 Mike Turquette wrote:
> Quoting Saravana Kannan (2013-04-30 21:42:08)
> 
> > Without this patch, the following race conditions are possible.
> > 
> > Race condition 1:
> > * clk-A has two parents - clk-X and clk-Y.
> > * All three are disabled and clk-X is current parent.
> > * Thread A: clk_set_parent(clk-A, clk-Y).
> > * Thread A: <snip execution flow>
> > * Thread A: Grabs enable lock.
> > * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
> > * Thread A: Updates clk-A SW parent to clk-Y
> > * Thread A: Releases enable lock.
> > * Thread B: clk_enable(clk-A).
> > * Thread B: clk_enable() enables clk-Y, then enabled clk-A and
> > returns.
> > 
> > clk-A is now enabled in software, but not clocking in hardware since
> > the hardware parent is still clk-X.
> > 
> > The only way to avoid race conditions between clk_set_parent() and
> > clk_enable/disable() is to ensure that clk_enable/disable() calls
> > don't
> > require changes to hardware enable state between changes to software
> > clock topology and hardware clock topology.
> > 
> > There are options to achieve the above:
> > 1. Grab the enable lock before changing software/hardware topology and
> > 
> >    release it afterwards.
> > 
> > 2. Keep the clock enabled for the duration of software/hardware
> > topology> 
> >    change so that any additional enable/disable calls don't try to
> >    change
> >    the hardware state. Once the topology change is complete, the clock
> >    can
> >    be put back in its original enable state.
> > 
> > Option (1) is not an acceptable solution since the set_parent() ops
> > might need to sleep.
> > 
> > Therefore, this patch implements option (2).
> > 
> > This patch doesn't violate any API semantics. clk_disable() doesn't
> > guarantee that the clock is actually disabled. So, no clients of a
> > clock can assume that a clock is disabled after their last call to
> > clk_disable(). So, enabling the clock during a parent change is not a
> > violation of any API semantics.
> > 
> > This also has the nice side effect of simplifying the error handling
> > code.
> > 
> > Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> 
> I've taken this patch into clk-next for testing.  The code itself looks
> fine.  The only thing that remains to be seen is if any platforms have a
> problem with disabled clocks getting turned on during a reparent
> operation.

IMHO this behavior should be documented somewhere, with a note that the 
clock must not be prepared to keep it disabled during reparent operation 
and possibly also pointing to the CLK_SET_PARENT_GATE flag.

> On platforms that I have worked on this is OK, but I suppose there could
> be some platform out there where a clock is prepared and disabled, and
> briefly enabling the clock during the reparent operation somehow puts
> the hardware in a bad state.

Well, on any platform where default clock settings are not completely 
correct this is likely to cause problems, because some device might get 
too high frequency for some period of time, which might crash it alone as 
well as the whole system.

Best regards,
Tomasz

> Anyways that's a long shot and this look OK until somebody screams.
> 
> Regards,
> Mike
> 
> > ---
> > It's been a while since I submitted a patch. So, apologies if I'm
> > cc'ing people who no longer care about the state of the common clock
> > framework.> 
> >  drivers/clk/clk.c |   72
> >  +++++++++++++++++++++++----------------------------- 1 files
> >  changed, 32 insertions(+), 40 deletions(-)
> > 
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index 934cfd1..fe4055f 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -1377,67 +1377,59 @@ static int __clk_set_parent(struct clk *clk,
> > struct clk *parent, u8 p_index)> 
> >         unsigned long flags;
> >         int ret = 0;
> >         struct clk *old_parent = clk->parent;
> > 
> > -       bool migrated_enable = false;
> > 
> > -       /* migrate prepare */
> > -       if (clk->prepare_count)
> > +       /*
> > +        * Migrate prepare state between parents and prevent race with
> > +        * clk_enable().
> > +        *
> > +        * If the clock is not prepared, then a race with
> > +        * clk_enable/disable() is impossible since we already have
> > the
> > +        * prepare lock (future calls to clk_enable() need to be
> > preceded by +        * a clk_prepare()).
> > +        *
> > +        * If the clock is prepared, migrate the prepared state to the
> > new +        * parent and also protect against a race with
> > clk_enable() by +        * forcing the clock and the new parent on. 
> > This ensures that all +        * future calls to clk_enable() are
> > practically NOPs with respect to +        * hardware and software
> > states.
> > +        */
> > +       if (clk->prepare_count) {
> > 
> >                 __clk_prepare(parent);
> > 
> > -
> > -       flags = clk_enable_lock();
> > -
> > -       /* migrate enable */
> > -       if (clk->enable_count) {
> > -               __clk_enable(parent);
> > -               migrated_enable = true;
> > +               clk_enable(parent);
> > +               clk_enable(clk);
> > 
> >         }
> >         
> >         /* update the clk tree topology */
> > 
> > +       flags = clk_enable_lock();
> > 
> >         clk_reparent(clk, parent);
> > 
> > -
> > 
> >         clk_enable_unlock(flags);
> >         
> >         /* change clock input source */
> >         if (parent && clk->ops->set_parent)
> >         
> >                 ret = clk->ops->set_parent(clk->hw, p_index);
> > 
> > -
> > 
> >         if (ret) {
> > 
> > -               /*
> > -                * The error handling is tricky due to that we need to
> > release -                * the spinlock while issuing the .set_parent
> > callback. This -                * means the new parent might have
> > been enabled/disabled in -                * between, which must be
> > considered when doing rollback. -                */
> > -               flags = clk_enable_lock();
> > 
> > +               flags = clk_enable_lock();
> > 
> >                 clk_reparent(clk, old_parent);
> > 
> > -
> > -               if (migrated_enable && clk->enable_count) {
> > -                       __clk_disable(parent);
> > -               } else if (migrated_enable && (clk->enable_count ==
> > 0)) { -                       __clk_disable(old_parent);
> > -               } else if (!migrated_enable && clk->enable_count) {
> > -                       __clk_disable(parent);
> > -                       __clk_enable(old_parent);
> > -               }
> > -
> > 
> >                 clk_enable_unlock(flags);
> > 
> > -               if (clk->prepare_count)
> > +               if (clk->prepare_count) {
> > +                       clk_disable(clk);
> > +                       clk_disable(parent);
> > 
> >                         __clk_unprepare(parent);
> > 
> > -
> > +               }
> > 
> >                 return ret;
> >         
> >         }
> > 
> > -       /* clean up enable for old parent if migration was done */
> > -       if (migrated_enable) {
> > -               flags = clk_enable_lock();
> > -               __clk_disable(old_parent);
> > -               clk_enable_unlock(flags);
> > -       }
> > -
> > -       /* clean up prepare for old parent if migration was done */
> > -       if (clk->prepare_count)
> > +       /*
> > +        * Finish the migration of prepare state and undo the changes
> > done +        * for preventing a race with clk_enable().
> > +        */
> > +       if (clk->prepare_count) {
> > +               clk_disable(clk);
> > +               clk_disable(old_parent);
> > 
> >                 __clk_unprepare(old_parent);
> > 
> > +       }
> > 
> >         /* update debugfs with new clk tree topology */
> >         clk_debug_reparent(clk, parent);
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From nicolas.pitre at linaro.org  Tue May 14 18:21:32 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 14 May 2013 18:21:32 -0400 (EDT)
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <20130514130005.GD29592@e102654-lin.cambridge.arm.com>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
 <20130514130005.GD29592@e102654-lin.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305141820280.31158@syhkavp.arg>

On Tue, 14 May 2013, Javi Merino wrote:

> On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> 
> > +static inline void init_cpu_port(struct cpu_port *port, u32 index, u32 mpidr)
> 
> The mpidr should be u64.

Why?


Nicolas


From robherring2 at gmail.com  Tue May 14 18:23:35 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 14 May 2013 17:23:35 -0500
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz>
 <5188B8B2.5030601@arm.com>
 <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
Message-ID: <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>

On Tue, May 14, 2013 at 2:54 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> [ Yes, I'm late to the party ]
>
> On Tue, 7 May 2013, Marc Zyngier wrote:
>
>> On 07/05/13 00:16, Pavel Machek wrote:
>>
>> Hi Pawel,
>>
>> >> Now that we support a timer-backed delay loop, I'm quickly getting sick
>> >> and tired of people complaining that their beloved bogomips value has
>> >> decreased. You know who you are!
>> >
>> >> Unfortunately, we can't just remove the entry from /proc/cpuinfo, as it
>> >> will likely break fragile userspace code which is parsing that stuff, so
>> >> instead replace it with a dummy value that can be chosen in the
>> >> Kconfig.
>> >
>> > So, instead of removing it you silently report invalid value? Note
>>
>> Removing it would be an ABI breakage. Unfortunately.
>
> Did you really write this with a straight face?
>
>> Name one userspace application that extracts meaningful information out
>> of the BogoMIPS field. Just one.
>
> Waitaminute... Didn't you just claim this would be an ABI break?
>
> So if no application can be found, where is the ABI breakage?

lscpu

But that is already "broken" on ARM because x86 uses "bogomips" and
ARM uses "BogoMIPS". I agree reporting BogoMIPS is silly, but there
are more differences between x86 and ARM. Somewhat meaningful fields
like "cpu MHz" are missing on ARM for example. These are mainly useful
for h/w inventory use which server folks tend to care about.

> This thread must be a joke.  Please just kill the damn thing out of
> /proc/cpuinfo and see if any application notices.  And if some do then
> they are already broken *today* and should be fixed.

And please do so for all arches then.

Rob


From skannan at codeaurora.org  Tue May 14 18:46:33 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 14 May 2013 15:46:33 -0700
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <9066674.E2RzuEn3ap@flatron>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <20130514185417.10068.5717@quantum> <9066674.E2RzuEn3ap@flatron>
Message-ID: <5192BEC9.1040104@codeaurora.org>

On 05/14/2013 03:10 PM, Tomasz Figa wrote:
> Hi,
>
> On Tuesday 14 of May 2013 11:54:17 Mike Turquette wrote:
>> Quoting Saravana Kannan (2013-04-30 21:42:08)
>>
>>> Without this patch, the following race conditions are possible.
>>>
>>> Race condition 1:
>>> * clk-A has two parents - clk-X and clk-Y.
>>> * All three are disabled and clk-X is current parent.
>>> * Thread A: clk_set_parent(clk-A, clk-Y).
>>> * Thread A: <snip execution flow>
>>> * Thread A: Grabs enable lock.
>>> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
>>> * Thread A: Updates clk-A SW parent to clk-Y
>>> * Thread A: Releases enable lock.
>>> * Thread B: clk_enable(clk-A).
>>> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and
>>> returns.
>>>
>>> clk-A is now enabled in software, but not clocking in hardware since
>>> the hardware parent is still clk-X.
>>>
>>> The only way to avoid race conditions between clk_set_parent() and
>>> clk_enable/disable() is to ensure that clk_enable/disable() calls
>>> don't
>>> require changes to hardware enable state between changes to software
>>> clock topology and hardware clock topology.
>>>
>>> There are options to achieve the above:
>>> 1. Grab the enable lock before changing software/hardware topology and
>>>
>>>     release it afterwards.
>>>
>>> 2. Keep the clock enabled for the duration of software/hardware
>>> topology>
>>>     change so that any additional enable/disable calls don't try to
>>>     change
>>>     the hardware state. Once the topology change is complete, the clock
>>>     can
>>>     be put back in its original enable state.
>>>
>>> Option (1) is not an acceptable solution since the set_parent() ops
>>> might need to sleep.
>>>
>>> Therefore, this patch implements option (2).
>>>
>>> This patch doesn't violate any API semantics. clk_disable() doesn't
>>> guarantee that the clock is actually disabled. So, no clients of a
>>> clock can assume that a clock is disabled after their last call to
>>> clk_disable(). So, enabling the clock during a parent change is not a
>>> violation of any API semantics.
>>>
>>> This also has the nice side effect of simplifying the error handling
>>> code.
>>>
>>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>>
>> I've taken this patch into clk-next for testing.  The code itself looks
>> fine.  The only thing that remains to be seen is if any platforms have a
>> problem with disabled clocks getting turned on during a reparent
>> operation.
>
> IMHO this behavior should be documented somewhere, with a note that the
> clock must not be prepared to keep it disabled during reparent operation
> and possibly also pointing to the CLK_SET_PARENT_GATE flag.

Reasonable request. I can update the documentation of clk_set_parent() 
to indicate that the clock might get turned on for the duration of the 
call and if they need a guarantee the GATE flag should be used.

>
>> On platforms that I have worked on this is OK, but I suppose there could
>> be some platform out there where a clock is prepared and disabled, and
>> briefly enabling the clock during the reparent operation somehow puts
>> the hardware in a bad state.
>
> Well, on any platform where default clock settings are not completely
> correct this is likely to cause problems, because some device might get
> too high frequency for some period of time, which might crash it alone as
> well as the whole system.
>

I don't think this is really a problem with this patch. It's present 
even without this patch.

The patch doesn't switch to some other unspecified parent. It only 
switches between the new/old parent. Even without this patch, if a clock 
is prepared while you reparent it, clk_enable() could be called at 
anytime between the parent switch and the future clock API calls to set 
up the new parent correctly. I think that's just crappy driver code to 
switch to a new parent before setting it up correctly. There's 
absolutely no good reason to do it that way.

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From dinguyen at altera.com  Tue May 14 18:52:31 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Tue, 14 May 2013 17:52:31 -0500
Subject: [PATCH 1/5] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Message-ID: <1368571955-6652-1-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 arch/arm/boot/dts/socfpga.dtsi         |   16 ++++++++++++++--
 arch/arm/boot/dts/socfpga_cyclone5.dts |   16 ++++++++++++++++
 arch/arm/boot/dts/socfpga_vt.dts       |    8 ++++++++
 3 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13..c42f835 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
 
 	aliases {
 		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		timer0 = &timer0;
@@ -238,13 +239,24 @@
 				};
 			};
 
-		gmac0: stmmac at ff700000 {
+		gmac0: ethernet at ff700000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff700000 0x2000>;
 			interrupts = <0 115 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			phy-mode = "gmii";
+			clocks = <&emac0_clk>;
+			clock-names = "stmmaceth";
+		};
+
+		gmac1: ethernet at ff702000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+			reg = <0xff702000 0x2000>;
+			interrupts = <0 120 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+			clocks = <&emac1_clk>;
+			clock-names = "stmmaceth";
 		};
 
 		L2: l2-cache at fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958..ece1a87 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
 	soc {
 		clkmgr at ffd04000 {
 			clocks {
@@ -41,6 +48,15 @@
 			};
 		};
 
+		ethernet at ff700000 {
+			status = "disabled";
+		};
+
+		ethernet at ff702000 {
+			phy-mode = "rgmii";
+			phy-addr = <0xffffffff>; /* probe for phy addr */
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d..f728471 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,14 @@
 			};
 		};
 
+		ethernet at ff700000 {
+			phy-mode = "gmii";
+		};
+
+		ethernet at ff702000 {
+			status = "disabled";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Tue May 14 18:52:34 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Tue, 14 May 2013 17:52:34 -0500
Subject: [PATCH 4/5] ARM: socfpga: dts: Add support for SD/MMC
In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368571955-6652-4-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for SD/MMC for SOCFPGA.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 .../devicetree/bindings/mmc/socfpga-dw-mshc.txt    |   59 ++++++++++++++++++++
 arch/arm/boot/dts/socfpga.dtsi                     |   11 ++++
 arch/arm/boot/dts/socfpga_cyclone5.dts             |   13 +++++
 arch/arm/boot/dts/socfpga_vt.dts                   |   13 +++++
 4 files changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
new file mode 100644
index 0000000..f4fda57
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
@@ -0,0 +1,59 @@
+* Altera SOCFPGA specific extensions to the Synopsis Designware Mobile
+  Storage Host Controller
+
+Required Properties:
+
+* compatible: should be
+	- "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA
+	  specific extentions.
+
+* altr,dw-mshc-ciu-div: Specifies the divider value for the card interface
+  unit (ciu) clock. For Altera's SOCFPGA, the divider value is fixed at 4.
+
+* altr,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
+  in transmit mode and CIU clock phase shift value in receive mode for single
+  data rate mode operation. Refer notes below for the order of the cells and the
+  valid values.
+
+  Notes for the sdr-timing values:
+
+    The order of the cells should be
+      - First Cell: CIU clock phase shift value for RX mode, smplsel bits in
+	the system manager SDMMC control group.
+      - Second Cell: CIU clock phase shift value for TX mode, drvsel bits in
+	the system manager SDMMC control group.
+
+    Valid values for SDR CIU clock timing for SOCFPGA:
+      - valid value for tx phase shift and rx phase shift is 0 to 7.
+
+Required properties for a slot:
+
+* bus-width: Data width for card slot. 4-bit or 8-bit data.
+
+Example:
+
+  The MSHC controller node can be split into two portions, SoC specific and
+  board specific portions as listed below.
+
+	dwmmc0 at ff704000 {
+		compatible = "altr,socfpga-dw-mshc";
+		reg = <0xff704000 0x1000>;
+		interrupts = <0 139 4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc0 at ff704000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x400>;
+		altr,dw-mshc-ciu-div = <4>;
+      		altr,dw-mshc-sdr-timing = <0 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+		};
+	};
+
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index ee8d1f1..6138edf 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -466,6 +466,17 @@
 			cache-level = <2>;
 		};
 
+		mmc: dwmmc0 at ff704000 {
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0xff704000 0x1000>;
+			interrupts = <0 139 4>;
+			fifo-depth = <0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+			clock-names = "biu", "ciu";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index ece1a87..dcb8c3a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -57,6 +57,19 @@
 			phy-addr = <0xffffffff>; /* probe for phy addr */
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <4>;
+			altr,dw-mshc-sdr-timing = <0 3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index f728471..1aec566 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -49,6 +49,19 @@
 			status = "disabled";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <4>;
+			pwr-en = <1>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Tue May 14 18:52:32 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Tue, 14 May 2013 17:52:32 -0500
Subject: [PATCH 2/5] ARM: socfpga: dts: Add gate-clock bindings
In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368571955-6652-2-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
the peripherals.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 .../devicetree/bindings/clock/altr_socfpga.txt     |    7 +
 arch/arm/boot/dts/socfpga.dtsi                     |  199 ++++++++++++++++++++
 2 files changed, 206 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index bd0c841..0045433 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -9,6 +9,9 @@ Required properties:
 	"altr,socfpga-pll-clock" - for a PLL clock
 	"altr,socfpga-perip-clock" - The peripheral clock divided from the
 		PLL clock.
+	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
 	either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+        and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+        and width.
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index c42f835..ee8d1f1 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -95,6 +95,12 @@
 						compatible = "fixed-clock";
 					};
 
+					f2s_periph_ref_clk: f2s_periph_ref_clk {
+						#clock-cells = <0>;
+						compatible = "fixed-clock";
+						clock-frequency = <10000000>;
+					};
+
 					main_pll: main_pll {
 						#address-cells = <1>;
 						#size-cells = <0>;
@@ -236,6 +242,199 @@
 							reg = <0xD4>;
 						};
 					};
+
+				mpu_periph_clk: mpu_periph_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <4>;
+					};
+
+				mpu_l2_ram_clk: mpu_l2_ram_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <2>;
+					};
+
+				l4_main_clk: l4_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					clk-gate = <0x60 0>;
+					};
+
+				l3_main_clk: l3_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					};
+
+				l3_mp_clk: l3_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 0 2>;
+					clk-gate = <0x60 1>;
+					};
+
+				l3_sp_clk: l3_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 2 2>;
+				};
+
+				l4_mp_clk: l4_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 4 3>;
+					clk-gate = <0x60 2>;
+					};
+
+				l4_sp_clk: l4_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 7 3>;
+					clk-gate = <0x60 3>;
+					};
+
+				dbg_at_clk: dbg_at_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 0 2>;
+					clk-gate = <0x60 4>;
+					};
+
+				dbg_clk: dbg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 2 2>;
+					clk-gate = <0x60 5>;
+					};
+
+				dbg_trace_clk: dbg_trace_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x6C 0 3>;
+					clk-gate = <0x60 6>;
+					};
+
+				dbg_timer_clk: dbg_timer_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					clk-gate = <0x60 7>;
+					};
+
+				cfg_clk: cfg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 8>;
+					};
+
+				s2f_user0_clk: s2f_user0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 9>;
+					};
+
+				emac_0_clk: emac_0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac0_clk>;
+					clk-gate = <0xa0 0>;
+					};
+
+				emac_1_clk: emac_1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac1_clk>;
+					clk-gate = <0xa0 1>;
+					};
+
+				usb_mp_clk: usb_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 2>;
+					div-reg = <0xa4 0 3>;
+					};
+
+				spi_m_clk: spi_m_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 3>;
+					div-reg = <0xa4 3 3>;
+					};
+
+				can0_clk: can0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 4>;
+					div-reg = <0xa4 6 3>;
+					};
+
+				can1_clk: can1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 5>;
+					div-reg = <0xa4 9 3>;
+					};
+
+				gpio_db_clk: gpio_db_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 6>;
+					div-reg = <0xa8 0 24>;
+					};
+
+				s2f_user1_clk: s2f_user1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&s2f_usr1_clk>;
+					clk-gate = <0xa0 7>;
+					};
+
+				sdmmc_clk: sdmmc_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 8>;
+					};
+
+				nand_x_clk: nand_x_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 9>;
+					};
+
+				nand_clk: nand_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 10>;
+					fixed-divider = <4>;
+					};
+
+				qspi_clk: qspi_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+					clk-gate = <0xa0 11>;
+					};
 				};
 			};
 
-- 
1.7.9.5




From dinguyen at altera.com  Tue May 14 18:52:35 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Tue, 14 May 2013 17:52:35 -0500
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368571955-6652-5-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add platform specific functionality for the DW SD/MMC driver for
SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
can use this define.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Seungwon Jeon <tgih.jun at samsung.com>
CC: Jaehoon Chung <jh80.chung at samsung.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: linux-mmc at vger.kernel.org
---
 drivers/mmc/host/Kconfig          |    8 +++
 drivers/mmc/host/Makefile         |    1 +
 drivers/mmc/host/dw_mmc-exynos.c  |    2 -
 drivers/mmc/host/dw_mmc-socfpga.c |  141 +++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h         |    1 +
 5 files changed, 151 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9ab8f8d..1be2289 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Exynos4 and Exynos5 SoC's.
 
+config MMC_DW_SOCFPGA
+	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
+	depends on MMC_DW
+	select MMC_DW_PLTFM
+	help
+	  This selects support for Altera SoCFPGA specific extensions to the
+	  Synopsys DesignWare Memory Card Interface driver.
+
 config MMC_DW_PCI
 	tristate "Synopsys Designware MCI support on PCI bus"
 	depends on MMC_DW && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cd32280..67718c1 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
 obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
 obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
 obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
+obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
 obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
 obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..866edef 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -31,8 +31,6 @@
 					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
 					SDMMC_CLKSEL_CCLK_DIVIDER(z))
 
-#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
-
 #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
 
diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
new file mode 100644
index 0000000..7eb3163
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -0,0 +1,141 @@
+/*
+ * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
+ *
+ *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Taken from dw_mmc_exynos.c
+ */
+#include <linux/clk.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
+#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
+	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+extern void __iomem *sys_manager_base_addr;
+
+/* SOCFPGA implementation specific driver private data */
+struct dw_mci_socfpga_priv_data {
+	u8	ciu_div;
+	u32	hs_timing;
+};
+
+static int dw_mci_socfpga_priv_init(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv;
+	struct device *dev = host->dev;
+	int pwr_en;
+
+	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(host->dev, "mem alloc failed for private data\n");
+		return -ENOMEM;
+	}
+
+	host->priv = priv;
+
+	if (of_property_read_u32(dev->of_node, "pwr-en", &pwr_en)) {
+		dev_info(dev, "couldn't determine pwr-en, assuming pwr-en = 0\n");
+		pwr_en = 0;
+	}
+
+	/* Set PWREN bit */
+	mci_writel(host, PWREN, pwr_en);
+
+	return 0;
+}
+
+static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	clk_disable(host->ciu_clk);
+	writel(priv->hs_timing, sys_manager_base_addr +
+		SYSMGR_SDMMCGRP_CTRL_OFFSET);
+	clk_enable(host->ciu_clk);
+
+	host->bus_hz /= priv->ciu_div;
+	return 0;
+}
+
+static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
+		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+	struct device_node *np = host->dev->of_node;
+	u32 timing[2];
+	u32 div = 0;
+	int ret;
+
+	of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
+	priv->ciu_div = div;
+
+	ret = of_property_read_u32_array(np,
+			"altr,dw-mshc-sdr-timing", timing, 2);
+	if (ret)
+		return ret;
+
+	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+	return 0;
+}
+
+static const struct dw_mci_drv_data socfpga_drv_data = {
+	.init			= dw_mci_socfpga_priv_init,
+	.setup_clock		= dw_mci_socfpga_setup_clock,
+	.prepare_command	= dw_mci_socfpga_prepare_command,
+	.parse_dt		= dw_mci_socfpga_parse_dt,
+};
+
+static const struct of_device_id dw_mci_socfpga_match[] = {
+	{ .compatible = "altr,socfpga-dw-mshc",
+			.data = &socfpga_drv_data, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
+
+int dw_mci_socfpga_probe(struct platform_device *pdev)
+{
+	const struct dw_mci_drv_data *drv_data;
+	const struct of_device_id *match;
+
+	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
+	drv_data = match->data;
+	return dw_mci_pltfm_register(pdev, drv_data);
+}
+
+static struct platform_driver dw_mci_socfpga_pltfm_driver = {
+	.probe		= dw_mci_socfpga_probe,
+	.remove		= __exit_p(dw_mci_pltfm_remove),
+	.driver		= {
+		.name		= "dwmmc_socfpga",
+		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
+		.pm		= &dw_mci_pltfm_pmops,
+	},
+};
+
+module_platform_driver(dw_mci_socfpga_pltfm_driver);
+
+MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:dwmmc-socfpga");
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0b74189..3700cb2 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
-- 
1.7.9.5




From dinguyen at altera.com  Tue May 14 18:52:33 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Tue, 14 May 2013 17:52:33 -0500
Subject: [PATCH 3/5] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368571955-6652-3-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Mike Turquette <mturquette at linaro.org>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 drivers/clk/socfpga/clk.c |  182 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 180 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315..a0551f2 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -26,6 +26,8 @@
 /* Clock Manager offsets */
 #define CLKMGR_CTRL    0x0
 #define CLKMGR_BYPASS 0x4
+#define CLKMGR_L4SRC	0x70
+#define CLKMGR_PERPLL_SRC	0xAC
 
 /* Clock bypass bits */
 #define MAINPLL_BYPASS (1<<0)
@@ -41,6 +43,16 @@
 #define SOCFPGA_PLL_DIVF_SHIFT	3
 #define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT	16
+#define SOCFGPA_MAX_PARENTS	3
+
+#define SOCFPGA_L4_MP_CLK			"l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK			"l4_sp_clk"
+#define SOCFPGA_NAND_CLK		"nand_clk"
+#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
+#define SOCFPGA_MMC_CLK			"mmc_clk"
+#define SOCFPGA_DB_CLK			"gpio_db_clk"
+
+#define div_mask(width)	((1 << (width)) - 1)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -49,6 +61,9 @@ struct socfpga_clk {
 	char *parent_name;
 	char *clk_name;
 	u32 fixed_div;
+	void __iomem *div_reg;
+	u32 width;
+	u32 shift;
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -132,8 +147,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 
 	socfpga_clk->hw.hw.init = &init;
 
-	if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
-			strcmp(clk_name, "sdram_pll")) {
+	if (strcmp(clk_name, "main_pll") == 0 ||
+			strcmp(clk_name, "periph_pll") == 0 ||
+			strcmp(clk_name, "sdram_pll") == 0) {
 		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
 		clk_pll_ops.enable = clk_gate_ops.enable;
 		clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +164,162 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 	return clk;
 }
 
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+	u32 l4_src;
+	u32 perpll_src;
+	u8 parent;
+
+	if (strcmp(hwclk->init->name, SOCFPGA_L4_MP_CLK) == 0) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		l4_src &= 0x1;
+		parent = l4_src;
+	} else if (strcmp(hwclk->init->name, SOCFPGA_L4_SP_CLK) == 0) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		l4_src = ((l4_src & 0x2) >> 1);
+		parent = l4_src;
+	} else {
+		perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (strcmp(hwclk->init->name, SOCFPGA_MMC_CLK) == 0)
+			perpll_src &= 0x3;
+		else if (strcmp(hwclk->init->name, SOCFPGA_NAND_CLK) == 0 ||
+			strcmp(hwclk->init->name, SOCFPGA_NAND_X_CLK) == 0)
+			perpll_src = ((perpll_src & 0xC) >> 2);
+		else /*QSPI clock */
+			perpll_src = ((perpll_src & 0x30) >> 4);
+		parent = perpll_src;
+	}
+
+	return parent;
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+	u32 src_reg;
+
+	if (strcmp(hwclk->init->name, SOCFPGA_L4_MP_CLK) == 0) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x1;
+		src_reg |= parent;
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else if (strcmp(hwclk->init->name, SOCFPGA_L4_SP_CLK) == 0) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x2;
+		src_reg |= (parent << 1);
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (strcmp(hwclk->init->name, SOCFPGA_MMC_CLK) == 0) {
+			src_reg &= ~0x3;
+			src_reg |= parent;
+		} else if (strcmp(hwclk->init->name, SOCFPGA_NAND_CLK) == 0 ||
+			strcmp(hwclk->init->name, SOCFPGA_NAND_X_CLK) == 0) {
+			src_reg &= ~0xC;
+			src_reg |= (parent << 2);
+		} else {/*QSPI clock */
+			src_reg &= ~0x30;
+			src_reg |= (parent << 4);
+		}
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	}
+
+	return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+	u32 div = 1, val;
+
+	if (socfpgaclk->fixed_div)
+		div = socfpgaclk->fixed_div;
+	else if (socfpgaclk->div_reg) {
+		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+		val &= div_mask(socfpgaclk->width);
+		if (strcmp(hwclk->init->name, SOCFPGA_DB_CLK) == 0)
+			div = val + 1;
+		else
+			div = (1 << val);
+	}
+
+	return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+	.recalc_rate = socfpga_clk_recalc_rate,
+	.get_parent = socfpga_clk_get_parent,
+	.set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 clk_gate[2];
+	u32 div_reg[3];
+	u32 fixed_div;
+	struct clk *clk;
+	struct socfpga_clk *socfpga_clk;
+	const char *clk_name = node->name;
+	const char *parent_name[SOCFGPA_MAX_PARENTS];
+	struct clk_init_data init;
+	int rc;
+	int i = 0;
+
+	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+	if (WARN_ON(!socfpga_clk))
+		return;
+
+	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+	if (rc)
+		clk_gate[0] = 0;
+
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		socfpga_clk->fixed_div = 0;
+	else
+		socfpga_clk->fixed_div = fixed_div;
+
+	if (clk_gate[0]) {
+		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+		socfpga_clk->hw.bit_idx = clk_gate[1];
+
+		gateclk_ops.enable = clk_gate_ops.enable;
+		gateclk_ops.disable = clk_gate_ops.disable;
+	}
+
+	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+	if (!rc) {
+		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+		socfpga_clk->shift = div_reg[1];
+		socfpga_clk->width = div_reg[2];
+	} else {
+		socfpga_clk->div_reg = 0;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+			of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	init.parent_names = parent_name;
+	init.num_parents = i;
+	socfpga_clk->hw.hw.init = &init;
+
+	clk = clk_register(NULL, &socfpga_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(socfpga_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(rc))
+		return;
+}
+
 static void __init socfpga_pll_init(struct device_node *node)
 {
 	socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +332,12 @@ static void __init socfpga_periph_init(struct device_node *node)
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
 
+static void __init socfpga_gate_init(struct device_node *node)
+{
+	socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
 void __init socfpga_init_clocks(void)
 {
 	struct clk *clk;
-- 
1.7.9.5




From tony at atomide.com  Tue May 14 18:52:21 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 14 May 2013 15:52:21 -0700
Subject: OMAP baseline test results for v3.9
In-Reply-To: <alpine.DEB.2.00.1305142116001.4368@utopia.booyaka.com>
References: <alpine.DEB.2.00.1305081933270.19747@utopia.booyaka.com>
 <20130514211328.GC5600@atomide.com>
 <alpine.DEB.2.00.1305142116001.4368@utopia.booyaka.com>
Message-ID: <20130514225221.GD5600@atomide.com>

* Paul Walmsley <paul at pwsan.com> [130514 14:24]:
> On Tue, 14 May 2013, Tony Lindgren wrote:
> 
> > Hi,
> > 
> > * Paul Walmsley <paul at pwsan.com> [130508 12:45]:
> > > 
> > > PM off, dynamic idle:
> > >     FAIL ( 2/ 5): 4430es2panda, 4460pandaes
> > >     Pass ( 3/ 5): 3530es3beagle, 3730beaglexm, 37xxevm
> > 
> > Looking at your pm logs, 3730beaglexm won't hit off-idle.
> > I've pasted the relevant lines from your logs below.
> > 
> > Is this a known issue?
> 
> Yes, the Beagle XM in my testbed is a 3630ES1.0.  From the PM logs:
> 
> [   63.154418] omap3_pm_off_mode_enable: Core OFF disabled due to errata 
> i583
> 
> I should probably clarify how this is reported in the test results.

Thanks that explains. BTW, the "PM off" naming might make some
people think that CONFIG_PM is not set :)

Regards,

Tony


From linux at arm.linux.org.uk  Tue May 14 18:50:54 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 14 May 2013 23:50:54 +0100
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <5192A692.4010700@wwwdotorg.org>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org>
Message-ID: <20130514225054.GI18614@n2100.arm.linux.org.uk>

On Tue, May 14, 2013 at 03:03:14PM -0600, Stephen Warren wrote:
> On 05/14/2013 01:15 AM, Jongsung Kim wrote:
> > Stephen Warren <swarren at wwwdotorg.org> :
> >> For reference, the AMBA periphid of the UART device there is 0x00341011.
> >> The nibble "3" is the revision being tested in:
> > 
> > The UART device has periphid 0x00341011, and is compatible with the
> > original PL011 prior to r1p5. Not with r1p5. It could be a possible
> > way to specify the compatible periphid (such as 0x00241011) instead
> > of just 0x0 when initializing the amba_device for the UART.
> > 
> >>> +static unsigned int get_fifosize_arm(unsigned int periphid)
> >>> +{
> >>> +	unsigned int rev = (periphid >> 20) & 0xf;
> >>> +	return rev < 3 ? 16 : 32;
> >>> +}
> ...
> > Doesn't the BCM2835 UART have anything different from the ARM PL011?
> > What about the UARTPCellID registers? They are set to 0xb105f00d with
> > the ARM PL011.
> 
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
> for the BCM2835 chip), I see:
> 
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
> 
> That seems to imply that not all r1p5 PL011s actually have a depth-32
> FIFO. Perhaps this is a configurable property of the IP block, not
> something that all r1p5 have?
> 
> I can't check the UARTPCellID registers right now.

The PCellID value is a marker for primecells, and is common to all primecells
which implement the ID scheme.  It's the other ID registers you want. :)


From nico at fluxnic.net  Tue May 14 19:56:51 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 14 May 2013 19:56:51 -0400 (EDT)
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz> <5188B8B2.5030601@arm.com>
 <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
 <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>
Message-ID: <alpine.LFD.2.03.1305141945160.31158@syhkavp.arg>

On Tue, 14 May 2013, Rob Herring wrote:

> On Tue, May 14, 2013 at 2:54 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > [ Yes, I'm late to the party ]
> >
> > On Tue, 7 May 2013, Marc Zyngier wrote:
> >
> >> On 07/05/13 00:16, Pavel Machek wrote:
> >>
> >> Hi Pawel,
> >>
> >> >> Now that we support a timer-backed delay loop, I'm quickly getting sick
> >> >> and tired of people complaining that their beloved bogomips value has
> >> >> decreased. You know who you are!
> >> >
> >> >> Unfortunately, we can't just remove the entry from /proc/cpuinfo, as it
> >> >> will likely break fragile userspace code which is parsing that stuff, so
> >> >> instead replace it with a dummy value that can be chosen in the
> >> >> Kconfig.
> >> >
> >> > So, instead of removing it you silently report invalid value? Note
> >>
> >> Removing it would be an ABI breakage. Unfortunately.
> >
> > Did you really write this with a straight face?
> >
> >> Name one userspace application that extracts meaningful information out
> >> of the BogoMIPS field. Just one.
> >
> > Waitaminute... Didn't you just claim this would be an ABI break?
> >
> > So if no application can be found, where is the ABI breakage?
> 
> lscpu
> 
> But that is already "broken" on ARM because x86 uses "bogomips" and
> ARM uses "BogoMIPS". 

So basically it won't be any more broken if the field disappears 
entirely, right?

> I agree reporting BogoMIPS is silly, but there
> are more differences between x86 and ARM. Somewhat meaningful fields
> like "cpu MHz" are missing on ARM for example. These are mainly useful
> for h/w inventory use which server folks tend to care about.

So... the tool must be coping well with missing fields already?  If 
/proc/cpuinfo is missing "important" fields on ARM then this is a 
different issue.

> > This thread must be a joke.  Please just kill the damn thing out of
> > /proc/cpuinfo and see if any application notices.  And if some do then
> > they are already broken *today* and should be fixed.
> 
> And please do so for all arches then.

Why?  It happens that the bogomips reporting on ARM is even more 
"broken" than on other architectures and therefore it deserves to be 
removed even more than on other architectures.  Who knows, maybe it 
still has some semblance of a meaning on those other architectures and 
that should be up to their respective maintainers to decide.


Nicolas


From tomasz.figa at gmail.com  Tue May 14 20:10:10 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Wed, 15 May 2013 02:10:10 +0200
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <5192BEC9.1040104@codeaurora.org>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <9066674.E2RzuEn3ap@flatron> <5192BEC9.1040104@codeaurora.org>
Message-ID: <8297704.vcdTNl69IU@flatron>

On Tuesday 14 of May 2013 15:46:33 Saravana Kannan wrote:
> On 05/14/2013 03:10 PM, Tomasz Figa wrote:
> > Hi,
> > 
> > On Tuesday 14 of May 2013 11:54:17 Mike Turquette wrote:
> >> Quoting Saravana Kannan (2013-04-30 21:42:08)
> >> 
> >>> Without this patch, the following race conditions are possible.
> >>> 
> >>> Race condition 1:
> >>> * clk-A has two parents - clk-X and clk-Y.
> >>> * All three are disabled and clk-X is current parent.
> >>> * Thread A: clk_set_parent(clk-A, clk-Y).
> >>> * Thread A: <snip execution flow>
> >>> * Thread A: Grabs enable lock.
> >>> * Thread A: Sees enable count of clk-A is 0, so doesn't enable
> >>> clk-Y.
> >>> * Thread A: Updates clk-A SW parent to clk-Y
> >>> * Thread A: Releases enable lock.
> >>> * Thread B: clk_enable(clk-A).
> >>> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and
> >>> returns.
> >>> 
> >>> clk-A is now enabled in software, but not clocking in hardware since
> >>> the hardware parent is still clk-X.
> >>> 
> >>> The only way to avoid race conditions between clk_set_parent() and
> >>> clk_enable/disable() is to ensure that clk_enable/disable() calls
> >>> don't
> >>> require changes to hardware enable state between changes to software
> >>> clock topology and hardware clock topology.
> >>> 
> >>> There are options to achieve the above:
> >>> 1. Grab the enable lock before changing software/hardware topology
> >>> and
> >>> 
> >>>     release it afterwards.
> >>> 
> >>> 2. Keep the clock enabled for the duration of software/hardware
> >>> topology>
> >>> 
> >>>     change so that any additional enable/disable calls don't try to
> >>>     change
> >>>     the hardware state. Once the topology change is complete, the
> >>>     clock
> >>>     can
> >>>     be put back in its original enable state.
> >>> 
> >>> Option (1) is not an acceptable solution since the set_parent() ops
> >>> might need to sleep.
> >>> 
> >>> Therefore, this patch implements option (2).
> >>> 
> >>> This patch doesn't violate any API semantics. clk_disable() doesn't
> >>> guarantee that the clock is actually disabled. So, no clients of a
> >>> clock can assume that a clock is disabled after their last call to
> >>> clk_disable(). So, enabling the clock during a parent change is not
> >>> a
> >>> violation of any API semantics.
> >>> 
> >>> This also has the nice side effect of simplifying the error handling
> >>> code.
> >>> 
> >>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> >> 
> >> I've taken this patch into clk-next for testing.  The code itself
> >> looks
> >> fine.  The only thing that remains to be seen is if any platforms
> >> have a problem with disabled clocks getting turned on during a
> >> reparent operation.
> > 
> > IMHO this behavior should be documented somewhere, with a note that
> > the
> > clock must not be prepared to keep it disabled during reparent
> > operation and possibly also pointing to the CLK_SET_PARENT_GATE flag.
> 
> Reasonable request. I can update the documentation of clk_set_parent()
> to indicate that the clock might get turned on for the duration of the
> call and if they need a guarantee the GATE flag should be used.
> 
> >> On platforms that I have worked on this is OK, but I suppose there
> >> could be some platform out there where a clock is prepared and
> >> disabled, and briefly enabling the clock during the reparent
> >> operation somehow puts the hardware in a bad state.
> > 
> > Well, on any platform where default clock settings are not completely
> > correct this is likely to cause problems, because some device might
> > get
> > too high frequency for some period of time, which might crash it alone
> > as well as the whole system.
> 
> I don't think this is really a problem with this patch. It's present
> even without this patch.
> 
> The patch doesn't switch to some other unspecified parent. It only
> switches between the new/old parent. Even without this patch, if a clock
> is prepared while you reparent it, clk_enable() could be called at
> anytime between the parent switch and the future clock API calls to set
> up the new parent correctly. I think that's just crappy driver code to
> switch to a new parent before setting it up correctly. There's
> absolutely no good reason to do it that way.

This is not exactly what I meant. I was just giving an example problem of 
turning a clock on, if it's not set up correctly yet.

AFAIK most (if not all) of current code either does necessary reparenting 
and initial rate setting early, before clk_prepare(), so it is not a 
problem or already after clk_enable() (in case of reparenting dynamically 
at runtime), so there shouldn't be any problem.

Best regards,
Tomasz



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:00 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:00 +0200
Subject: [PATCH v3 00/20] SH pinctrl DT support
Message-ID: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Hello,

Here's the third version of the SuperH and SH Mobile pin controllers (PFC) DT
support patch set.

The patches are based on tags/renesas-next-20130513 from Simon's tree
(git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git), the R-Car
GPIO DT bindings proposal ("[RFC/PATCH 0/2] R-Car GPIO DT bindings") and the
marzen-reference ethernet patches ("[PATCH 0/2] marzen-reference ethernet
patches") I've previously posted. The result is available in my tree at

        git://linuxtv.org/pinchartl/fbdev.git pinmux/3.9/dt

The series is pretty self-explanatory. DT bindings are added in patch 01/20,
and the following patches gradually move SoC code and board code over to the
device tree for the armadilla800eva-reference, kzm9g-reference and
marzen-reference boards. The code has been tested on the three boards, but
only kzm9g can currently boot to userspace with network support due to lack of
DT bindings or other ethernet issues on the two other boards. armadillo800eva
and marzen have thus received less testing.

Comments will be very appreciated on the DT bindings (01/20). Points I'm a bit
unsure about include:

- Should the driver support pin configuration subnodes as currently
  implemented, or should the subnodes be promoted to regular pin configuration
  nodes, with clients referencing multiple nodes ?
- Should the driver allow mixing function and configuration properties in a pin
  configuration node as currently implemented, or should it restrict the pin
  configuration nodes to either a function or one (or more) configuration(s) ?
- Should we specify common bindings for pinconf-generic instead of using
  Renesas-specific properties ? (If the answer to this question is yes, please
  help :-)).

Changes since v2:

- Added pin configuration properties
- Rewrote all arch changes

Changes since v1:

- Fixed gpio cell number 2 documentation
- Added missing gpio-controller and #gpio-cells properties to r8a7740 DT
- Split kzm9g DT patch into SoC and board patches
- Dropped pinctrl mappings move to DT

Laurent Pinchart (20):
  sh-pfc: Add DT support
  ARM: shmobile: r8a73a4: Add pin control device to device tree
  ARM: shmobile: r8a7740: Add pin control device to device tree
  ARM: shmobile: r8a7778: Add pin control device to device tree
  ARM: shmobile: r8a7778: Add GPIO controller devices to device tree
  ARM: shmobile: r8a7779: Add pin control device to device tree
  ARM: shmobile: r8a7779: Add GPIO controller devices to device tree
  ARM: shmobile: r8a7790: Add pin control device to device tree
  ARM: shmobile: r8a7790: Add GPIO controller devices to device tree
  ARM: shmobile: sh7372: Add pin control device to device tree
  ARM: shmobile: sh73a0: Add pin control device to device tree
  ARM: shmobile: armadillo-reference: Move pinctrl mappings to device
    tree
  ARM: shmobile: armadillo-reference: Add st1232 pin mappings
  ARM: shmobile: armadillo-reference: Move st1232 reset GPIO to DT
  ARM: shmobile: armadillo-reference: Add LED1-LED4 to the device tree
  ARM: shmobile: kzm9g-reference: Move pinctrl mappings to device tree
  ARM: shmobile: kzm9g-reference: Move SDHI regulators to DT
  ARM: shmobile: kzm9g-reference: Add LED1-LED4 to the device tree
  ARM: shmobile: marzen-reference: Move pinctrl mappings to device tree
  ARM: shmobile: marzen-reference: Add LED2-LED4 to the device tree

 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       | 143 ++++++++++++
 arch/arm/boot/dts/r8a73a4.dtsi                     |   7 +
 .../boot/dts/r8a7740-armadillo800eva-reference.dts |  33 +++
 arch/arm/boot/dts/r8a7740.dtsi                     |   8 +
 arch/arm/boot/dts/r8a7778.dtsi                     |  50 +++++
 arch/arm/boot/dts/r8a7779-marzen-reference.dts     |  48 ++++
 arch/arm/boot/dts/r8a7779.dtsi                     |  69 ++++++
 arch/arm/boot/dts/r8a7790.dtsi                     |  59 +++++
 arch/arm/boot/dts/sh7372.dtsi                      |   8 +
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts       |  89 +++++++-
 arch/arm/boot/dts/sh73a0.dtsi                      |   8 +
 .../board-armadillo800eva-reference.c              |  18 +-
 arch/arm/mach-shmobile/board-kzm9g-reference.c     |  47 ----
 arch/arm/mach-shmobile/board-marzen-reference.c    |  28 ---
 drivers/pinctrl/sh-pfc/core.c                      |  66 +++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   | 244 +++++++++++++++++++++
 16 files changed, 829 insertions(+), 96 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

-- 
Regards,

Laurent Pinchart



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:01 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:01 +0200
Subject: [PATCH v3 01/20] sh-pfc: Add DT support
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.

Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.

Cc: devicetree-discuss at lists.ozlabs.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       | 143 ++++++++++++
 drivers/pinctrl/sh-pfc/core.c                      |  66 +++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   | 244 +++++++++++++++++++++
 3 files changed, 451 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 0000000..e7aae39
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,143 @@
+* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
+
+The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
+SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
+
+
+Pin Control
+-----------
+
+Required Properties:
+
+  - compatible: should be one of the following.
+    - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
+    - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+    - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
+    - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+    - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+    - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
+    - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+
+  - reg: Base address and length of each memory resource used by the pin
+    controller hardware module.
+
+The PFC node also acts as a container for pin configuration nodes. Please refer
+to pinctrl-bindings.txt in this directory for the definition of the term "pin
+configuration node" and for the common pinctrl bindings used by client devices.
+
+Each pin configuration node represents a desired configuration for a pin, a
+pin group, or a list of pins or pin groups. The configuration can include the
+function to select on those pin(s) and pin configuration parameters (such as
+pull-up and pull-down).
+
+Pin configuration nodes contain pin configuration properties, either directly
+or grouped in child subnodes. Both pin muxing and configuration parameters can
+be grouped in that way and referenced as a single pin configuration node by
+client devices.
+
+A configuration node or subnode must reference at least one pin (through the
+pins or pin groups properties) and contain at least a function or one
+configuration parameter. When the function is present only pin groups can be
+used to reference pins.
+
+All pin configuration nodes and subnodes names are ignored. All of those nodes
+are parsed through phandles and processed purely based on their content.
+
+Pin Configuration Node Properties:
+
+- renesas,pins : An array of strings, each string containing the name of a pin.
+- renesas,groups : An array of strings, each string containing the name of a pin
+  group.
+
+- renesas,function: A string containing the name of the function to mux to the
+  pin group(s) specified by the renesas,groups property
+
+  Valid values for pin, group and function names can be found in the group and
+  function arrays of the PFC data file corresponding to the SoC
+  (drivers/pinctrl/sh-pfc/pfc-*.c)
+
+- renesas,pull-up: An integer representing the pull-up strength to be applied
+  to all pins specified by the renesas,pins and renesas-groups properties.
+  0 disables the pull-up, 1 enables it. Other values should not be used.
+- renesas,pull-down: An integer representing the pull-down strength to be
+  applied to all pins specified by the renesas,pins and renesas-groups
+  properties. 0 disables the pull-down, 1 enables it. Other values should not
+  be used.
+
+
+GPIO
+----
+
+Required Properties:
+
+  - gpio-controller: Marks the device node as a gpio controller.
+
+  - #gpio-cells: Should be 2. The first cell is the pin number and the second
+    cell is used to specify optional parameters as bit flags. Only the GPIO
+    active low flag (bit 0) is currently supported.
+
+The syntax of the gpio specifier used by client nodes should be the following
+with values derived from the SoC user manual.
+
+  <[phandle of the gpio controller node]
+   [pin number within the gpio controller]
+   [flags and pull up/down]>
+
+
+Examples
+--------
+
+Example 1: SH73A0 (SH-Mobile AG5) pin controller node
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-sh73a0";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+Example 2: A GPIO LED node that references a GPIO
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&pfc 20 1>; /* Active low */
+		};
+	};
+
+Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
+           for the MMCIF and SCIFA4 devices
+
+	&pfc {
+		pinctrl-0 = <&scifa4_pins>;
+		pinctrl-names = "default";
+
+		mmcif_pins: mmcif {
+			mux {
+				renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
+				renesas,function = "mmc0";
+			};
+			cfg {
+				renesas,groups = "mmc0_data8_0";
+				renesas,pins = "PORT279";
+				renesas,pull-up = <1>;
+			};
+		};
+
+		scifa4_pins: scifa4 {
+			renesas,groups = "scifa4_data", "scifa4_ctrl";
+			renesas,function = "scifa4";
+		};
+	};
+
+Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
+
+	&mmcif {
+		pinctrl-0 = <&mmcif_pins>;
+		pinctrl-names = "default";
+
+		bus-width = <8>;
+		vmmc-supply = <&reg_1p8v>;
+		status = "okay";
+	};
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 3b2fd43..5fa1c6b 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -18,6 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
@@ -348,14 +349,74 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id sh_pfc_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A73A4
+	{
+		.compatible = "renesas,pfc-r8a73a4",
+		.data = &r8a73a4_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7740
+	{
+		.compatible = "renesas,pfc-r8a7740",
+		.data = &r8a7740_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+	{
+		.compatible = "renesas,pfc-r8a7778",
+		.data = &r8a7778_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7779
+	{
+		.compatible = "renesas,pfc-r8a7779",
+		.data = &r8a7779_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+	{
+		.compatible = "renesas,pfc-r8a7790",
+		.data = &r8a7790_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7372
+	{
+		.compatible = "renesas,pfc-sh7372",
+		.data = &sh7372_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH73A0
+	{
+		.compatible = "renesas,pfc-sh73a0",
+		.data = &sh73a0_pinmux_info,
+	},
+#endif
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
+#endif
+
 static int sh_pfc_probe(struct platform_device *pdev)
 {
+	const struct platform_device_id *platid = platform_get_device_id(pdev);
+#ifdef CONFIG_OF
+	struct device_node *np = pdev->dev.of_node;
+#endif
 	const struct sh_pfc_soc_info *info;
 	struct sh_pfc *pfc;
 	int ret;
 
-	info = pdev->id_entry->driver_data
-	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
+	if (platid)
+		info = (const void *)platid->driver_data;
+#ifdef CONFIG_OF
+	else if (np)
+		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
+#endif
+	else
+		info = pdev->dev.platform_data;
+
 	if (info == NULL)
 		return -ENODEV;
 
@@ -501,6 +562,7 @@ static struct platform_driver sh_pfc_driver = {
 	.driver		= {
 		.name	= DRV_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(sh_pfc_of_table),
 	},
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 3492ec9..066c347 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -14,7 +14,9 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/pinctrl/pinctrl.h>
@@ -72,11 +74,253 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 	seq_printf(s, "%s", DRV_NAME);
 }
 
+static int sh_pfc_map_add_config(struct pinctrl_map *map,
+				 const char *group_or_pin,
+				 enum pinctrl_map_type type,
+				 unsigned long *configs,
+				 unsigned int num_configs)
+{
+	unsigned long *cfgs;
+
+	cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
+		       GFP_KERNEL);
+	if (cfgs == NULL)
+		return -ENOMEM;
+
+	map->type = type;
+	map->data.configs.group_or_pin = group_or_pin;
+	map->data.configs.configs = cfgs;
+	map->data.configs.num_configs = num_configs;
+
+	return 0;
+}
+
+static int sh_pfc_dt_parse_config(unsigned long **configs,
+				  unsigned int *num_configs,
+				  unsigned long config)
+{
+	unsigned int count = *num_configs + 1;
+	unsigned long *cfgs;
+
+	cfgs = krealloc(*configs, sizeof(*cfgs) * count, GFP_KERNEL);
+	if (cfgs == NULL)
+		return -ENOMEM;
+
+	cfgs[count - 1] = config;
+
+	*configs = cfgs;
+	*num_configs = count;
+
+	return 0;
+}
+
+struct sh_pfc_config_param {
+	const char *name;
+	enum pin_config_param param;
+};
+
+static const struct sh_pfc_config_param sh_pfc_config_params[] = {
+	{ "renesas,pull-up", PIN_CONFIG_BIAS_PULL_UP },
+	{ "renesas,pull-down", PIN_CONFIG_BIAS_PULL_DOWN },
+};
+
+static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
+				    struct pinctrl_map **map,
+				    unsigned int *num_maps, unsigned int *index)
+{
+	struct pinctrl_map *maps = *map;
+	unsigned int nmaps = *num_maps;
+	unsigned int idx = *index;
+	unsigned long *configs = NULL;
+	unsigned int num_configs = 0;
+	const char *function = NULL;
+	struct property *prop;
+	unsigned int num_pins;
+	const char *group;
+	const char *pin;
+	unsigned int i;
+	int ret;
+
+	/* Parse the function and configuration properties. At least a function
+	 * or one configuration must be specified.
+	 */
+	ret = of_property_read_string(np, "renesas,function", &function);
+	if (ret < 0 && ret != -EINVAL) {
+		dev_err(dev, "Invalid function in DT\n");
+		return ret;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sh_pfc_config_params); ++i) {
+		const struct sh_pfc_config_param *param =
+			&sh_pfc_config_params[i];
+		unsigned long config;
+		u32 val;
+
+		ret = of_property_read_u32(np, param->name, &val);
+		if (!ret) {
+			config = pinconf_to_config_packed(param->param, val);
+			ret = sh_pfc_dt_parse_config(&configs, &num_configs,
+						     config);
+			if (ret < 0)
+				goto done;
+		} else if (ret != -EINVAL) {
+			dev_err(dev, "Could not parse property %s\n",
+				param->name);
+		}
+	}
+
+	if (!function && num_configs == 0) {
+		dev_err(dev,
+			"DT node must contain at least a function or config\n");
+		goto done;
+	}
+
+	/* Count the number of pins and groups and reallocate mappings. */
+	ret = of_property_count_strings(np, "renesas,pins");
+	if (ret < 0 && ret != -EINVAL) {
+		dev_err(dev, "Invalid pins list in DT\n");
+		goto done;
+	}
+	num_pins = ret;
+
+	if (configs)
+		nmaps += ret;
+
+	ret = of_property_count_strings(np, "renesas,groups");
+	if (ret < 0 && ret != -EINVAL) {
+		dev_err(dev, "Invalid pin groups list in DT\n");
+		goto done;
+	}
+	num_pins += ret;
+
+	if (function)
+		nmaps += ret;
+	if (configs)
+		nmaps += ret;
+
+	if (!num_pins) {
+		dev_err(dev, "No pin or group provided in DT node\n");
+		ret = -ENODEV;
+		goto done;
+	}
+
+	maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
+	if (maps == NULL) {
+		ret = -ENOMEM;
+		goto done;
+	}
+
+	*map = maps;
+	*num_maps = nmaps;
+
+	/* Iterate over pins and groups and create the mappings. */
+	of_property_for_each_string(np, "renesas,groups", prop, group) {
+		if (function) {
+			maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
+			maps[idx].data.mux.group = group;
+			maps[idx].data.mux.function = function;
+			idx++;
+		}
+
+		if (configs) {
+			ret = sh_pfc_map_add_config(&maps[idx], group,
+						    PIN_MAP_TYPE_CONFIGS_GROUP,
+						    configs, num_configs);
+			if (ret < 0)
+				goto done;
+
+			idx++;
+		}
+	}
+
+	if (!configs) {
+		ret = 0;
+		goto done;
+	}
+
+	of_property_for_each_string(np, "renesas,pins", prop, pin) {
+		ret = sh_pfc_map_add_config(&maps[idx], pin,
+					    PIN_MAP_TYPE_CONFIGS_PIN,
+					    configs, num_configs);
+		if (ret < 0)
+			goto done;
+
+		idx++;
+	}
+
+done:
+	*index = idx;
+	kfree(configs);
+	return ret;
+}
+
+static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
+			       struct pinctrl_map *map, unsigned num_maps)
+{
+	unsigned int i;
+
+	if (map == NULL)
+		return;
+
+	for (i = 0; i < num_maps; ++i) {
+		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
+		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
+			kfree(map[i].data.configs.configs);
+	}
+
+	kfree(map);
+}
+
+static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
+				 struct device_node *np,
+				 struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+	struct device *dev = pmx->pfc->dev;
+	struct device_node *child;
+	unsigned int index;
+	int ret;
+
+	*map = NULL;
+	*num_maps = 0;
+	index = 0;
+
+	for_each_child_of_node(np, child) {
+		ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
+					       &index);
+		if (ret < 0)
+			goto done;
+	}
+
+	/* If no mapping has been found in child nodes try the config node. */
+	if (*num_maps == 0) {
+		ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
+		if (ret < 0)
+			goto done;
+	}
+
+	if (*num_maps == 0) {
+		dev_err(dev, "no mapping found in node %s\n", np->full_name);
+		ret = -EINVAL;
+		goto done;
+	}
+
+	ret = 0;
+
+done:
+	if (ret < 0)
+		sh_pfc_dt_free_map(pctldev, *map, *num_maps);
+
+	return ret;
+}
+
 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
 	.get_groups_count	= sh_pfc_get_groups_count,
 	.get_group_name		= sh_pfc_get_group_name,
 	.get_group_pins		= sh_pfc_get_group_pins,
 	.pin_dbg_show		= sh_pfc_pin_dbg_show,
+	.dt_node_to_map		= sh_pfc_dt_node_to_map,
+	.dt_free_map		= sh_pfc_dt_free_map,
 };
 
 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:02 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:02 +0200
Subject: [PATCH v3 02/20] ARM: shmobile: r8a73a4: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a73a4 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a73a4.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fde2a33..358898c 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -91,4 +91,11 @@
 		interrupt-parent = <&gic>;
 		interrupts = <0 69 4>;
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-r8a73a4";
+		reg = <0xe6050000 0x9000>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:03 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:03 +0200
Subject: [PATCH v3 03/20] ARM: shmobile: r8a7740: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-4-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7740 device tree and remove manual pinmux
initialization from the corresponding board files.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740.dtsi                           |  8 ++++++++
 arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 16 ++++++++--------
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 25dc930..2fa3708 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -135,4 +135,12 @@
 			      0 72 0x4
 			      0 73 0x4>;
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-r8a7740";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605800c 0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index 03b85fe..f25b6aa 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -121,7 +121,7 @@
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
 	/* SCIFA1 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "e6050000.pfc",
 				  "scifa1_data", "scifa1"),
 };
 
@@ -170,22 +170,22 @@ static void __init eva_init(void)
 	eva_clock_init();
 
 	pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
-	r8a7740_pinmux_init();
 
 	r8a7740_meram_workaround();
 
-	/*
-	 * Touchscreen
-	 * TODO: Move reset GPIO over to .dts when we can reference it
-	 */
-	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
-
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
 	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
 #endif
 
 	r8a7740_add_standard_devices_dt();
+
+	/*
+	 * Touchscreen
+	 * TODO: Move reset GPIO over to .dts when we can reference it
+	 */
+	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+
 	r8a7740_pm_init();
 }
 
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:04 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:04 +0200
Subject: [PATCH v3 04/20] ARM: shmobile: r8a7778: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-5-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7778 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7778.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 4743735..c8dbf14 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -32,4 +32,9 @@
 		reg = <0xfe438000 0x1000>,
 		      <0xfe430000 0x100>;
 	};
+
+	pfc: pfc at fffc0000 {
+		compatible = "renesas,pfc-r8a7778";
+		reg = <0xfffc000 0x118>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:05 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:05 +0200
Subject: [PATCH v3 05/20] ARM: shmobile: r8a7778: Add GPIO controller devices
 to device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-6-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add GPIO controller nodes to the r8a7778 core device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7778.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index c8dbf14..d612a9a 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -33,6 +33,51 @@
 		      <0xfe430000 0x100>;
 	};
 
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc40000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio1: gpio at ffc41000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc41000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio2: gpio at ffc42000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc42000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio3: gpio at ffc43000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc43000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio4: gpio at ffc44000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc44000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
 	pfc: pfc at fffc0000 {
 		compatible = "renesas,pfc-r8a7778";
 		reg = <0xfffc000 0x118>;
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:07 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:07 +0200
Subject: [PATCH v3 07/20] ARM: shmobile: r8a7779: Add GPIO controller devices
 to device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-8-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add GPIO controller nodes to the r8a7779 core device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 9dfc438..dc78ff7 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -48,6 +48,70 @@
                       <0xf0000100 0x100>;
         };
 
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc40000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 141 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio1: gpio at ffc41000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc41000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 142 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio2: gpio at ffc42000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc42000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 143 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio3: gpio at ffc43000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc43000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 144 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio4: gpio at ffc44000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc44000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 145 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio5: gpio at ffc45000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc45000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 146 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio6: gpio at ffc46000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc46000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 147 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#gpio-lines = <9>;
+	};
+
 	irqpin0: irqpin at fe780010 {
 		compatible = "renesas,intc-irqpin";
 		#interrupt-cells = <2>;
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:06 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:06 +0200
Subject: [PATCH v3 06/20] ARM: shmobile: r8a7779: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-7-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7779 device tree and remove manual pinmux
initialization from the corresponding board files.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779.dtsi                  |  5 +++++
 arch/arm/mach-shmobile/board-marzen-reference.c | 17 ++++++++---------
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 7f146c6..9dfc438 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -101,6 +101,11 @@
 		interrupts = <0 81 0x4>;
 	};
 
+	pfc: pfc at fffc0000 {
+		compatible = "renesas,pfc-r8a7779";
+		reg = <0xfffc0000 0x23c>;
+	};
+
 	thermal at ffc48000 {
 		compatible = "renesas,rcar-thermal";
 		reg = <0xffc48000 0x38>;
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 5332e89..fa7fc07 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -28,24 +28,24 @@
 
 static const struct pinctrl_map marzen_pinctrl_map[] = {
 	/* SCIF2 (CN18: DEBUG0) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "fffc0000.pfc",
 				  "scif2_data_c", "scif2"),
 	/* SCIF4 (CN19: DEBUG1) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "fffc0000.pfc",
 				  "scif4_data", "scif4"),
 	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_wp", "sdhi0"),
 	/* SMSC */
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
 				  "intc_irq1_b", "intc"),
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
 				  "lbsc_ex_cs0", "lbsc"),
 };
 
@@ -53,7 +53,6 @@ static void __init marzen_init(void)
 {
 	pinctrl_register_mappings(marzen_pinctrl_map,
 				  ARRAY_SIZE(marzen_pinctrl_map));
-	r8a7779_pinmux_init();
 
 	r8a7779_add_standard_devices_dt();
 }
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:08 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:08 +0200
Subject: [PATCH v3 08/20] ARM: shmobile: r8a7790: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-9-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7790 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7a17110..ee21061 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -60,4 +60,9 @@
 		interrupt-parent = <&gic>;
 		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>;
 	};
+
+	pfc: pfc at e6060000 {
+		compatible = "renesas,pfc-r8a7790";
+		reg = <0xe6060000 0x250>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:09 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:09 +0200
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller devices
 to device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add GPIO controller nodes to the r8a7790 core device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ee21061..b5fe51da 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -44,6 +44,60 @@
 		};
 	};
 
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0xffc40000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 4 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio1: gpio at ffc41000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0xffc41000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 5 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio2: gpio at ffc42000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0xffc42000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 6 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio3: gpio at ffc43000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0xffc43000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 7 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio4: gpio at ffc44000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0xffc44000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 8 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	gpio5: gpio at ffc45000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0xffc45000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 9 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <1 13 0xf08>,
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:10 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:10 +0200
Subject: [PATCH v3 10/20] ARM: shmobile: sh7372: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-11-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the sh7372 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh7372.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..ce19398 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -18,4 +18,12 @@
 			compatible = "arm,cortex-a8";
 		};
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-sh7372";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:11 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:11 +0200
Subject: [PATCH v3 11/20] ARM: shmobile: sh73a0: Add pin control device to
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-12-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the sh73a0 device tree and remove manual pinmux
initialization from the corresponding board files.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0.dtsi                  |  8 ++++++++
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 27 +++++++++++++-------------
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 17fd9c6..9b1e8f8 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -233,4 +233,12 @@
 		cap-sd-highspeed;
 		status = "disabled";
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-sh73a0";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 44055fe..6ff6ca2 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -40,35 +40,35 @@ static unsigned long pin_pullup_conf[] = {
 };
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
-	PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "e6050000.pfc",
 				  "i2c3_1", "i2c3"),
 	/* MMCIF */
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				  "mmc0_data8_0", "mmc0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				  "mmc0_ctrl_0", "mmc0"),
-	PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				    "PORT279", pin_pullup_conf),
-	PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				      "mmc0_data8_0", pin_pullup_conf),
 	/* SCIFA4 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
 				  "scifa4_data", "scifa4"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
 				  "scifa4_ctrl", "scifa4"),
 	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_wp", "sdhi0"),
 	/* SDHI2 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
 				  "sdhi2_data4", "sdhi2"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
 				  "sdhi2_ctrl", "sdhi2"),
 };
 
@@ -76,7 +76,6 @@ static void __init kzm_init(void)
 {
 	sh73a0_add_standard_devices_dt();
 	pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
-	sh73a0_pinmux_init();
 
 	/* enable SD */
 	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:13 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:13 +0200
Subject: [PATCH v3 13/20] ARM: shmobile: armadillo-reference: Add st1232 pin
 mappings
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-14-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add pin mappings for the st1232 device to the device tree and reference
them as the default state for the device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 4a7ae32..a6c6606 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -41,6 +41,8 @@
 		reg = <0x55>;
 		interrupt-parent = <&irqpin1>;
 		interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+		pinctrl-0 = <&st1232_pins>;
+		pinctrl-names = "default";
 	};
 };
 
@@ -52,4 +54,9 @@
 		renesas,groups = "scifa1_data";
 		renesas,function = "scifa1";
 	};
+
+	st1232_pins: st1232 {
+		renesas,groups = "intc_irq10";
+		renesas,function = "intc";
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:12 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:12 +0200
Subject: [PATCH v3 12/20] ARM: shmobile: armadillo-reference: Move pinctrl
 mappings to device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-13-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Replace the pinctrl mappings in board code by device tree mappings.
For devices that are still instantiated from board code reference the
mappings as the default pin controller state to apply them at boot time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts  | 10 ++++++++++
 arch/arm/mach-shmobile/board-armadillo800eva-reference.c |  9 ---------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 09ea22c..4a7ae32 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -43,3 +43,13 @@
 		interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
 	};
 };
+
+&pfc {
+	pinctrl-0 = <&scifa1_pins>;
+	pinctrl-names = "default";
+
+	scifa1_pins: scifa1 {
+		renesas,groups = "scifa1_data";
+		renesas,function = "scifa1";
+	};
+};
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index f25b6aa..4ddd299 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -24,7 +24,6 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <linux/pinctrl/machine.h>
 #include <mach/common.h>
 #include <mach/r8a7740.h>
 #include <asm/mach/arch.h>
@@ -119,12 +118,6 @@
  *	usbhsf_power_ctrl()
  */
 
-static const struct pinctrl_map eva_pinctrl_map[] = {
-	/* SCIFA1 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "e6050000.pfc",
-				  "scifa1_data", "scifa1"),
-};
-
 static void __init eva_clock_init(void)
 {
 	struct clk *system	= clk_get(NULL, "system_clk");
@@ -169,8 +162,6 @@ static void __init eva_init(void)
 	r8a7740_clock_init(MD_CK0 | MD_CK2);
 	eva_clock_init();
 
-	pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
-
 	r8a7740_meram_workaround();
 
 #ifdef CONFIG_CACHE_L2X0
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:15 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:15 +0200
Subject: [PATCH v3 15/20] ARM: shmobile: armadillo-reference: Add LED1-LED4 to
 the device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-16-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

LED1 to LED4 are GPIO LEDs. Add corresponding DT nodes.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index a037776..746c64a 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -33,6 +33,21 @@
 		regulator-boot-on;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&pfc 102 0>;
+		};
+		led2 {
+			gpios = <&pfc 111 0>;
+		};
+		led3 {
+			gpios = <&pfc 110 0>;
+		};
+		led4 {
+			gpios = <&pfc 177 0>;
+		};
+	};
 };
 
 &i2c0 {
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:14 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:14 +0200
Subject: [PATCH v3 14/20] ARM: shmobile: armadillo-reference: Move st1232
 reset GPIO to DT
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-15-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Reference the st1232 reset GPIO from the device tree and remove it from
board code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts  | 1 +
 arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 7 -------
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index a6c6606..a037776 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -43,6 +43,7 @@
 		interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
 		pinctrl-0 = <&st1232_pins>;
 		pinctrl-names = "default";
+		gpios = <&pfc 166 1>;
 	};
 };
 
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index 4ddd299..002d8d3 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -158,7 +158,6 @@ clock_error:
  */
 static void __init eva_init(void)
 {
-
 	r8a7740_clock_init(MD_CK0 | MD_CK2);
 	eva_clock_init();
 
@@ -171,12 +170,6 @@ static void __init eva_init(void)
 
 	r8a7740_add_standard_devices_dt();
 
-	/*
-	 * Touchscreen
-	 * TODO: Move reset GPIO over to .dts when we can reference it
-	 */
-	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
-
 	r8a7740_pm_init();
 }
 
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:17 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:17 +0200
Subject: [PATCH v3 17/20] ARM: shmobile: kzm9g-reference: Move SDHI regulators
 to DT
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-18-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Create two GPIO-controlled fixed-voltage regulators in the
kzm9g-reference DT and remove manual configuration of the corresponding
GPIOs from board code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts   | 22 ++++++++++++++++++++--
 arch/arm/mach-shmobile/board-kzm9g-reference.c |  6 ------
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 475535f..cdfd71a 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -58,6 +58,24 @@
 		regulator-boot-on;
 	};
 
+	vmmc_sdhi0: regulator at 2 {
+	        compatible = "regulator-fixed";
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pfc 15 0>;
+		enable-active-high;
+	};
+
+	vmmc_sdhi2: regulator at 3 {
+	        compatible = "regulator-fixed";
+		regulator-name = "SDHI2 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pfc 14 0>;
+		enable-active-high;
+	};
+
 	lan9220 at 10000000 {
 		compatible = "smsc,lan9220", "smsc,lan9115";
 		reg = <0x10000000 0x100>;
@@ -200,7 +218,7 @@
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
 
-	vmmc-supply = <&reg_3p3v>;
+	vmmc-supply = <&vmmc_sdhi0>;
 	bus-width = <4>;
 	status = "okay";
 };
@@ -209,7 +227,7 @@
 	pinctrl-0 = <&sdhi2_pins>;
 	pinctrl-names = "default";
 
-	vmmc-supply = <&reg_3p3v>;
+	vmmc-supply = <&vmmc_sdhi2>;
 	bus-width = <4>;
 	broken-cd;
 	status = "okay";
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index fc2bb37..1847b4d 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -21,7 +21,6 @@
  */
 
 #include <linux/delay.h>
-#include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
@@ -37,11 +36,6 @@ static void __init kzm_init(void)
 {
 	sh73a0_add_standard_devices_dt();
 
-	/* enable SD */
-	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
-	gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
 	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:16 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:16 +0200
Subject: [PATCH v3 16/20] ARM: shmobile: kzm9g-reference: Move pinctrl
 mappings to device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-17-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Replace the pinctrl mappings in board code by device tree mappings.
For devices that are still instantiated from board code reference the
mappings as the default pin controller state to apply them at boot time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts   | 51 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 40 --------------------
 2 files changed, 51 insertions(+), 40 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index b6f759e..475535f 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -145,19 +145,70 @@
 	};
 };
 
+&i2c3 {
+	pinctrl-0 = <&i2c3_pins>;
+	pinctrl-names = "default";
+};
+
 &mmcif {
+	pinctrl-0 = <&mmcif_pins>;
+	pinctrl-names = "default";
+
 	bus-width = <8>;
 	vmmc-supply = <&reg_1p8v>;
 	status = "okay";
 };
 
+&pfc {
+	pinctrl-0 = <&scifa4_pins>;
+	pinctrl-names = "default";
+
+	i2c3_pins: i2c3 {
+		renesas,groups = "i2c3_1";
+		renesas,function = "i2c3";
+	};
+
+	mmcif_pins: mmcif {
+		mux {
+			renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
+			renesas,function = "mmc0";
+		};
+		cfg {
+			renesas,groups = "mmc0_data8_0";
+			renesas,pins = "PORT279";
+			renesas,pull-up = <1>;
+		};
+	};
+
+	scifa4_pins: scifa4 {
+		renesas,groups = "scifa4_data", "scifa4_ctrl";
+		renesas,function = "scifa4";
+	};
+
+	sdhi0_pins: sdhi0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
+		renesas,function = "sdhi0";
+	};
+
+	sdhi2_pins: sdhi2 {
+		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+		renesas,function = "sdhi2";
+	};
+};
+
 &sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
 	vmmc-supply = <&reg_3p3v>;
 	bus-width = <4>;
 	status = "okay";
 };
 
 &sdhi2 {
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-names = "default";
+
 	vmmc-supply = <&reg_3p3v>;
 	bus-width = <4>;
 	broken-cd;
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 6ff6ca2..fc2bb37 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -27,55 +27,15 @@
 #include <linux/irqchip.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
 #include <mach/sh73a0.h>
 #include <mach/common.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-static unsigned long pin_pullup_conf[] = {
-	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
-};
-
-static const struct pinctrl_map kzm_pinctrl_map[] = {
-	PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "e6050000.pfc",
-				  "i2c3_1", "i2c3"),
-	/* MMCIF */
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				  "mmc0_data8_0", "mmc0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				  "mmc0_ctrl_0", "mmc0"),
-	PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				    "PORT279", pin_pullup_conf),
-	PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				      "mmc0_data8_0", pin_pullup_conf),
-	/* SCIFA4 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
-				  "scifa4_data", "scifa4"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
-				  "scifa4_ctrl", "scifa4"),
-	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_wp", "sdhi0"),
-	/* SDHI2 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
-				  "sdhi2_data4", "sdhi2"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
-				  "sdhi2_ctrl", "sdhi2"),
-};
-
 static void __init kzm_init(void)
 {
 	sh73a0_add_standard_devices_dt();
-	pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
 
 	/* enable SD */
 	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:18 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:18 +0200
Subject: [PATCH v3 18/20] ARM: shmobile: kzm9g-reference: Add LED1-LED4 to the
 device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-19-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

LED1 to LED4 are GPIO LEDs. Add corresponding DT nodes.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index cdfd71a..21b0fe3 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -88,6 +88,22 @@
 		vddvario-supply = <&reg_1p8v>;
 		vdd33a-supply = <&reg_3p3v>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&pfc 20 1>; /* Active low */
+		};
+		led2 {
+			gpios = <&pfc 21 1>; /* Active low */
+		};
+		led3 {
+			gpios = <&pfc 22 1>; /* Active low */
+		};
+		led4 {
+			gpios = <&pfc 23 1>; /* Active low */
+		};
+	};
 };
 
 &i2c0 {
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:19 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:19 +0200
Subject: [PATCH v3 19/20] ARM: shmobile: marzen-reference: Move pinctrl
 mappings to device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-20-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Replace the pinctrl mappings in board code by device tree mappings.
For devices that are still instantiated from board code reference the
mappings as the default pin controller state to apply them at boot time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts  | 35 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-marzen-reference.c | 27 -------------------
 2 files changed, 35 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 10cfc7f..07ef31f 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -37,6 +37,9 @@
 	lan0 at 18000000 {
 		compatible = "smsc,lan9220", "smsc,lan9115";
 		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&lan0_pins>;
+		pinctrl-names = "default";
+
 		phy-mode = "mii";
 		interrupt-parent = <&irqpin0>;
 		interrupts = <1 0x4>;
@@ -45,3 +48,35 @@
 		vdd33a-supply = <&fixedregulator3v3>;
 	};
 };
+
+&pfc {
+	pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>;
+	pinctrl-names = "default";
+
+	lan0_pins: lan0 {
+		intc {
+			renesas,groups = "intc_irq1_b";
+			renesas,function = "intc";
+		};
+		lbsc {
+			renesas,groups = "lbsc_ex_cs0";
+			renesas,function = "lbsc";
+		};
+	};
+
+	scif2_pins: scif2 {
+		renesas,groups = "scif2_data_c";
+		renesas,function = "scif2";
+	};
+
+	scif4_pins: scif4 {
+		renesas,groups = "scif4_data";
+		renesas,function = "scif4";
+	};
+
+	sdhi0_pins: sdhi0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd",
+				 "sdhi0_wp";
+		renesas,function = "sdhi0";
+	};
+};
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index fa7fc07..3d1c439 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,41 +19,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/pinctrl/machine.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
-static const struct pinctrl_map marzen_pinctrl_map[] = {
-	/* SCIF2 (CN18: DEBUG0) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "fffc0000.pfc",
-				  "scif2_data_c", "scif2"),
-	/* SCIF4 (CN19: DEBUG1) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "fffc0000.pfc",
-				  "scif4_data", "scif4"),
-	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_wp", "sdhi0"),
-	/* SMSC */
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
-				  "intc_irq1_b", "intc"),
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
-				  "lbsc_ex_cs0", "lbsc"),
-};
-
 static void __init marzen_init(void)
 {
-	pinctrl_register_mappings(marzen_pinctrl_map,
-				  ARRAY_SIZE(marzen_pinctrl_map));
-
 	r8a7779_add_standard_devices_dt();
 }
 
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 14 20:18:20 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 02:18:20 +0200
Subject: [PATCH v3 20/20] ARM: shmobile: marzen-reference: Add LED2-LED4 to
 the device tree
In-Reply-To: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1368577100-3530-21-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

LED2 to LED4 are GPIO LEDs. Add corresponding DT nodes.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 07ef31f..0533c31 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -47,6 +47,19 @@
 		vddvario-supply = <&fixedregulator3v3>;
 		vdd33a-supply = <&fixedregulator3v3>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 0>;
+		};
+		led3 {
+			gpios = <&gpio4 30 0>;
+		};
+		led4 {
+			gpios = <&gpio4 31 0>;
+		};
+	};
 };
 
 &pfc {
-- 
1.8.1.5



From tony at atomide.com  Tue May 14 20:25:37 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 14 May 2013 17:25:37 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
Message-ID: <20130515002537.GG5600@atomide.com>

Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
changed PM to not access IVA registers on omaps that don't have
them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
will stay on and block deeper idle states.

Signed-off-by: Tony Lindgren <tony at atomide.com>

---

Paul & Kevin, do you have better ideas for fixing this?

--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
 	/* Clear any pending PRCM interrupts */
 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-	if (omap3_has_iva())
-		omap3_iva_idle();
+	/*
+	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
+	 */
+	omap3_iva_idle();
 
 	omap3_d2d_idle();
 }


From jason at lakedaemon.net  Tue May 14 20:29:56 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 May 2013 20:29:56 -0400
Subject: [PATCH V2 07/10] ARM: mvebu: Use standard MMC binding for all
 users of mvsdio
In-Reply-To: <1368479941-10084-8-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-8-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130515002956.GH31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 11:18:58PM +0200, Simon Baatz wrote:
> In order to prepare the switch to the standard MMC device tree parser
> for mvsdio, adapt all current uses of mvsdio in the dts files to the
> standard format.
> 
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  arch/arm/boot/dts/armada-370-db.dts                |    1 +
>  arch/arm/boot/dts/armada-370-mirabox.dts           |    1 +
>  arch/arm/boot/dts/armada-370-rd.dts                |    1 +
>  arch/arm/boot/dts/armada-370-xp.dtsi               |    4 ++++
>  arch/arm/boot/dts/armada-xp-db.dts                 |    1 +
>  arch/arm/boot/dts/kirkwood-dreamplug.dts           |    1 +
>  .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    2 ++
>  arch/arm/boot/dts/kirkwood-mplcec4.dts             |    2 +-
>  arch/arm/boot/dts/kirkwood-topkick.dts             |    1 +
>  arch/arm/boot/dts/kirkwood.dtsi                    |    4 ++++
>  10 files changed, 17 insertions(+), 1 deletion(-)

Applied to mvebu/dt

thx,

Jason.


From jason at lakedaemon.net  Tue May 14 20:31:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 May 2013 20:31:32 -0400
Subject: [PATCH V2 09/10] ARM: Kirkwood: Add dts files for Sheevaplug
 and eSATA Sheevaplug
In-Reply-To: <1368479941-10084-10-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-10-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130515003132.GI31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 11:19:00PM +0200, Simon Baatz wrote:
> 
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  arch/arm/boot/dts/Makefile                        |    2 +
>  arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi |   97 +++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts   |   40 +++++++++
>  arch/arm/boot/dts/kirkwood-sheevaplug.dts         |   45 ++++++++++
>  4 files changed, 184 insertions(+)
>  create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
>  create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
>  create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts

Applied to mvebu/dt

thx,

Jason.


From jason at lakedaemon.net  Tue May 14 20:42:37 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 May 2013 20:42:37 -0400
Subject: [PATCH V2 10/10] ARM: Kirkwood: add DT support for Sheevaplug
 and Sheevaplug eSATA
In-Reply-To: <1368479941-10084-11-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <1368479941-10084-11-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130515004237.GJ31290@titan.lakedaemon.net>

On Mon, May 13, 2013 at 11:19:01PM +0200, Simon Baatz wrote:
> 
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  arch/arm/mach-kirkwood/Kconfig            |    7 +++++++
>  arch/arm/mach-kirkwood/Makefile           |    1 +
>  arch/arm/mach-kirkwood/board-dt.c         |    4 ++++
>  arch/arm/mach-kirkwood/board-sheevaplug.c |   27 +++++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h           |    5 +++++
>  5 files changed, 44 insertions(+)
>  create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c

Applied to mvebu/boards

thx,

Jason.


From jason at lakedaemon.net  Tue May 14 20:53:34 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 May 2013 00:53:34 +0000
Subject: [PATCH] ARM: kirkwood: enable Sheevaplug DT in defconfig
In-Reply-To: <1368479941-10084-11-git-send-email-gmbnomis@gmail.com>
References: <1368479941-10084-11-git-send-email-gmbnomis@gmail.com>
Message-ID: <1368579214-11532-1-git-send-email-jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
Just a heads up I'm adding this to the mvebu/defconfig tree.  v3.10-rc1 changed
a few things for defconfig, but it's so little, I'm not worrying about breaking
it out.

 arch/arm/configs/kirkwood_defconfig | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252..1916da6 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -50,6 +49,7 @@ CONFIG_MACH_NETSPACE_V2_DT=y
 CONFIG_MACH_NSA310_DT=y
 CONFIG_MACH_OPENBLOCKS_A6_DT=y
 CONFIG_MACH_READYNAS_DT=y
+CONFIG_MACH_SHEEVAPLUG_DT=y
 CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
@@ -68,14 +68,12 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
-CONFIG_NET_DSA=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
-- 
1.8.2.1



From jason at lakedaemon.net  Tue May 14 20:58:06 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 May 2013 20:58:06 -0400
Subject: [PATCH] ARM: Kirkwood: Enable USB 3.0 in kirkwood_defconfig
In-Reply-To: <1368542544-24743-1-git-send-email-andrew@lunn.ch>
References: <1368542544-24743-1-git-send-email-andrew@lunn.ch>
Message-ID: <20130515005806.GK31290@titan.lakedaemon.net>

On Tue, May 14, 2013 at 04:42:24PM +0200, Andrew Lunn wrote:
> Some QNAP devices has a USB 3.0 host controller on a PCIe bus.  Enable
> the driver for this in the default configuration.
> 
> Reported-by: Marek Vasut <marex at denx.de>
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> ---
>  arch/arm/configs/kirkwood_defconfig |    1 +
>  1 file changed, 1 insertion(+)

Applied to mvebu/defconfig

thx,

Jason.


From horms at verge.net.au  Tue May 14 20:59:07 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 09:59:07 +0900
Subject: [PATCH 05/20] ARM: shmobile: ape6evm: Remove init_irq
 declaration in machine description
In-Reply-To: <1368545933-7430-6-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-6-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515005907.GD12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:38PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/board-ape6evm.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
> index 55b8c9f..8dfbdba 100644
> --- a/arch/arm/mach-shmobile/board-ape6evm.c
> +++ b/arch/arm/mach-shmobile/board-ape6evm.c
> @@ -20,7 +20,6 @@
>  
>  #include <linux/gpio.h>
>  #include <linux/interrupt.h>
> -#include <linux/irqchip.h>
>  #include <linux/kernel.h>
>  #include <linux/pinctrl/machine.h>
>  #include <linux/platform_device.h>
> @@ -87,7 +86,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(APE6EVM_DT, "ape6evm")
> -	.init_irq	= irqchip_init,
>  	.init_time	= shmobile_timer_init,
>  	.init_machine	= ape6evm_add_standard_devices,
>  	.dt_compat	= ape6evm_boards_compat_dt,

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>



From horms at verge.net.au  Tue May 14 20:59:17 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 09:59:17 +0900
Subject: [PATCH 06/20] ARM: shmobile: kzm9g: Remove init_irq declaration
 in machine description
In-Reply-To: <1368545933-7430-7-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-7-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515005917.GE12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:39PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/board-kzm9g-reference.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
> index aefa50d..b7ee96e 100644
> --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
> +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
> @@ -24,7 +24,6 @@
>  #include <linux/gpio.h>
>  #include <linux/io.h>
>  #include <linux/irq.h>
> -#include <linux/irqchip.h>
>  #include <linux/input.h>
>  #include <linux/of_platform.h>
>  #include <linux/pinctrl/machine.h>
> @@ -100,7 +99,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
>  	.map_io		= sh73a0_map_io,
>  	.init_early	= sh73a0_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= kzm_init,
>  	.init_time	= shmobile_timer_init,
>  	.dt_compat	= kzm9g_boards_compat_dt,

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>



From horms at verge.net.au  Tue May 14 20:59:26 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 09:59:26 +0900
Subject: [PATCH 07/20] ARM: shmobile: lager: Remove init_irq declaration
 in machine description
In-Reply-To: <1368545933-7430-8-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-8-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515005926.GF12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:40PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/board-lager.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
> index f587187..b7488b8 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
> @@ -19,7 +19,6 @@
>   */
>  
>  #include <linux/interrupt.h>
> -#include <linux/irqchip.h>
>  #include <linux/kernel.h>
>  #include <linux/platform_device.h>
>  #include <mach/common.h>
> @@ -39,7 +38,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(LAGER_DT, "lager")
> -	.init_irq	= irqchip_init,
>  	.init_time	= r8a7790_timer_init,
>  	.init_machine	= lager_add_standard_devices,
>  	.dt_compat	= lager_boards_compat_dt,

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>



From horms at verge.net.au  Tue May 14 20:59:38 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 09:59:38 +0900
Subject: [PATCH 08/20] ARM: shmobile: emev2: Remove init_irq declaration
 in machine description
In-Reply-To: <1368545933-7430-9-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-9-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515005938.GG12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:41PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/setup-emev2.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
> index 899a86c..66694e0 100644
> --- a/arch/arm/mach-shmobile/setup-emev2.c
> +++ b/arch/arm/mach-shmobile/setup-emev2.c
> @@ -20,7 +20,6 @@
>  #include <linux/init.h>
>  #include <linux/interrupt.h>
>  #include <linux/irq.h>
> -#include <linux/irqchip.h>
>  #include <linux/platform_device.h>
>  #include <linux/platform_data/gpio-em.h>
>  #include <linux/of_platform.h>
> @@ -454,7 +453,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
>  	.smp		= smp_ops(emev2_smp_ops),
>  	.init_early	= emev2_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= emev2_add_standard_devices_dt,
>  	.dt_compat	= emev2_boards_compat_dt,
>  MACHINE_END

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>


From neidhard.kim at lge.com  Tue May 14 21:00:07 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Wed, 15 May 2013 10:00:07 +0900
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <5192A692.4010700@wwwdotorg.org>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org>
Message-ID: <022d01ce5107$8bc668e0$a3533aa0$@lge.com>

Stephen Warren <swarren at wwwdotorg.org> :
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
> the BCM2835 chip), I see:
>
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
>
> That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO.
> Perhaps this is a configurable property of the IP block, not something
that
> all r1p5 have?

All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
TRM:

r1p4-r1p5	Contains the following differences in functionality:
		* The receive and transmit FIFOs are increased to a depth of
32.
		* The Revision field in the UARTPeriphID2 Register on page
3-24
		  bits [7:4] now reads back as 0x3.



From horms at verge.net.au  Tue May 14 21:46:04 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:46:04 +0900
Subject: [PATCH 05/20] ARM: shmobile: ape6evm: Remove init_irq
 declaration in machine description
In-Reply-To: <20130515005907.GD12246@verge.net.au>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-6-git-send-email-maxime.ripard@free-electrons.com>
 <20130515005907.GD12246@verge.net.au>
Message-ID: <20130515014604.GK12246@verge.net.au>

On Wed, May 15, 2013 at 09:59:07AM +0900, Simon Horman wrote:
> On Tue, May 14, 2013 at 05:38:38PM +0200, Maxime Ripard wrote:
> > Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> > specified") removed the need to explictly setup the init_irq field in
> > the machine description when using only irqchip_init. Remove that
> > declaration for shmobile as well.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> > ---
> >  arch/arm/mach-shmobile/board-ape6evm.c | 2 --
> >  1 file changed, 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
> > index 55b8c9f..8dfbdba 100644
> > --- a/arch/arm/mach-shmobile/board-ape6evm.c
> > +++ b/arch/arm/mach-shmobile/board-ape6evm.c
> > @@ -20,7 +20,6 @@
> >  
> >  #include <linux/gpio.h>
> >  #include <linux/interrupt.h>
> > -#include <linux/irqchip.h>
> >  #include <linux/kernel.h>
> >  #include <linux/pinctrl/machine.h>
> >  #include <linux/platform_device.h>
> > @@ -87,7 +86,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
> >  };
> >  
> >  DT_MACHINE_START(APE6EVM_DT, "ape6evm")
> > -	.init_irq	= irqchip_init,
> >  	.init_time	= shmobile_timer_init,
> >  	.init_machine	= ape6evm_add_standard_devices,
> >  	.dt_compat	= ape6evm_boards_compat_dt,
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

Sorry, what I should have said is:

Queued up for v3.11 in the boards-spe6evm branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:46:22 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:46:22 +0900
Subject: [PATCH 06/20] ARM: shmobile: kzm9g: Remove init_irq declaration
 in machine description
In-Reply-To: <20130515005917.GE12246@verge.net.au>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-7-git-send-email-maxime.ripard@free-electrons.com>
 <20130515005917.GE12246@verge.net.au>
Message-ID: <20130515014622.GL12246@verge.net.au>

On Wed, May 15, 2013 at 09:59:17AM +0900, Simon Horman wrote:
> On Tue, May 14, 2013 at 05:38:39PM +0200, Maxime Ripard wrote:
> > Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> > specified") removed the need to explictly setup the init_irq field in
> > the machine description when using only irqchip_init. Remove that
> > declaration for shmobile as well.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> > ---
> >  arch/arm/mach-shmobile/board-kzm9g-reference.c | 2 --
> >  1 file changed, 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
> > index aefa50d..b7ee96e 100644
> > --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
> > +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
> > @@ -24,7 +24,6 @@
> >  #include <linux/gpio.h>
> >  #include <linux/io.h>
> >  #include <linux/irq.h>
> > -#include <linux/irqchip.h>
> >  #include <linux/input.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/pinctrl/machine.h>
> > @@ -100,7 +99,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
> >  	.map_io		= sh73a0_map_io,
> >  	.init_early	= sh73a0_init_delay,
> >  	.nr_irqs	= NR_IRQS_LEGACY,
> > -	.init_irq	= irqchip_init,
> >  	.init_machine	= kzm_init,
> >  	.init_time	= shmobile_timer_init,
> >  	.dt_compat	= kzm9g_boards_compat_dt,
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

Sorry, what I should have said is:

Queued up for v3.11 in the boards-kzm9g branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:46:39 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:46:39 +0900
Subject: [PATCH 07/20] ARM: shmobile: lager: Remove init_irq declaration
 in machine description
In-Reply-To: <1368545933-7430-8-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-8-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515014639.GM12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:40PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/board-lager.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
> index f587187..b7488b8 100644
> --- a/arch/arm/mach-shmobile/board-lager.c
> +++ b/arch/arm/mach-shmobile/board-lager.c
> @@ -19,7 +19,6 @@
>   */
>  
>  #include <linux/interrupt.h>
> -#include <linux/irqchip.h>
>  #include <linux/kernel.h>
>  #include <linux/platform_device.h>
>  #include <mach/common.h>
> @@ -39,7 +38,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(LAGER_DT, "lager")
> -	.init_irq	= irqchip_init,
>  	.init_time	= r8a7790_timer_init,
>  	.init_machine	= lager_add_standard_devices,
>  	.dt_compat	= lager_boards_compat_dt,

Sorry, what I should have said is:

Queued up for v3.11 in the boards-lager branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:47:24 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:47:24 +0900
Subject: [PATCH 08/20] ARM: shmobile: emev2: Remove init_irq declaration
 in machine description
In-Reply-To: <20130515005938.GG12246@verge.net.au>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-9-git-send-email-maxime.ripard@free-electrons.com>
 <20130515005938.GG12246@verge.net.au>
Message-ID: <20130515014724.GN12246@verge.net.au>

On Wed, May 15, 2013 at 09:59:38AM +0900, Simon Horman wrote:
> On Tue, May 14, 2013 at 05:38:41PM +0200, Maxime Ripard wrote:
> > Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> > specified") removed the need to explictly setup the init_irq field in
> > the machine description when using only irqchip_init. Remove that
> > declaration for shmobile as well.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> > ---
> >  arch/arm/mach-shmobile/setup-emev2.c | 2 --
> >  1 file changed, 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
> > index 899a86c..66694e0 100644
> > --- a/arch/arm/mach-shmobile/setup-emev2.c
> > +++ b/arch/arm/mach-shmobile/setup-emev2.c
> > @@ -20,7 +20,6 @@
> >  #include <linux/init.h>
> >  #include <linux/interrupt.h>
> >  #include <linux/irq.h>
> > -#include <linux/irqchip.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/platform_data/gpio-em.h>
> >  #include <linux/of_platform.h>
> > @@ -454,7 +453,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
> >  	.smp		= smp_ops(emev2_smp_ops),
> >  	.init_early	= emev2_init_delay,
> >  	.nr_irqs	= NR_IRQS_LEGACY,
> > -	.init_irq	= irqchip_init,
> >  	.init_machine	= emev2_add_standard_devices_dt,
> >  	.dt_compat	= emev2_boards_compat_dt,
> >  MACHINE_END
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

Sorry, what I should have said is:

Queued up for v3.11 in the soc-emev2 branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:47:44 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:47:44 +0900
Subject: [PATCH 09/20] ARM: shmobile: r8a73a4: Remove init_irq
 declaration in machine description
In-Reply-To: <1368545933-7430-10-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-10-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515014744.GO12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:42PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/setup-r8a73a4.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
> index c5a75a7..0b78896 100644
> --- a/arch/arm/mach-shmobile/setup-r8a73a4.c
> +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
> @@ -18,7 +18,6 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
>   */
>  #include <linux/irq.h>
> -#include <linux/irqchip.h>
>  #include <linux/kernel.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_data/irq-renesas-irqc.h>
> @@ -194,7 +193,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
> -	.init_irq	= irqchip_init,
>  	.init_machine	= r8a73a4_add_standard_devices_dt,
>  	.init_time	= shmobile_timer_init,
>  	.dt_compat	= r8a73a4_boards_compat_dt,

Queued up for v3.11 in the boards-r8a73a4 branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:48:09 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:48:09 +0900
Subject: [PATCH 10/20] ARM: shmobile: r8a7790: Remove init_irq
 declaration in machine description
In-Reply-To: <1368545933-7430-11-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-11-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515014809.GP12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:43PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/setup-r8a7790.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> index 49de2d5..2a7a276 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> @@ -19,7 +19,6 @@
>   */
>  
>  #include <linux/irq.h>
> -#include <linux/irqchip.h>
>  #include <linux/kernel.h>
>  #include <linux/of_platform.h>
>  #include <linux/serial_sci.h>
> @@ -142,7 +141,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
>  };
>  
>  DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
> -	.init_irq	= irqchip_init,
>  	.init_machine	= r8a7790_add_standard_devices_dt,
>  	.init_time	= r8a7790_timer_init,
>  	.dt_compat	= r8a7790_boards_compat_dt,

Queued up for v3.11 in the soc-r8a7790 branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:48:42 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:48:42 +0900
Subject: [PATCH 11/20] ARM: shmobile: sh73a0: Remove init_irq declaration
 in machine description
In-Reply-To: <1368545933-7430-12-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-12-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515014842.GQ12246@verge.net.au>

On Tue, May 14, 2013 at 05:38:44PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for shmobile as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-shmobile/setup-sh73a0.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> index fdf3894..73dd75b 100644
> --- a/arch/arm/mach-shmobile/setup-sh73a0.c
> +++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> @@ -22,7 +22,6 @@
>  #include <linux/init.h>
>  #include <linux/interrupt.h>
>  #include <linux/irq.h>
> -#include <linux/irqchip.h>
>  #include <linux/platform_device.h>
>  #include <linux/of_platform.h>
>  #include <linux/delay.h>
> @@ -1035,7 +1034,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
>  	.map_io		= sh73a0_map_io,
>  	.init_early	= sh73a0_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= irqchip_init,
>  	.init_machine	= sh73a0_add_standard_devices_dt,
>  	.dt_compat	= sh73a0_boards_compat_dt,
>  MACHINE_END

Queued up for v3.11 in the soc-sh73a0 branch of my renesas tree
on kernel.org. It is included in the renesas-next-20130515 tag of
that tree and should appear in linux-next in the not to distant future.



From horms at verge.net.au  Tue May 14 21:49:01 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 10:49:01 +0900
Subject: [PATCH 05/20] ARM: shmobile: ape6evm: Remove init_irq
 declaration in machine description
In-Reply-To: <20130515014604.GK12246@verge.net.au>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-6-git-send-email-maxime.ripard@free-electrons.com>
 <20130515005907.GD12246@verge.net.au>
 <20130515014604.GK12246@verge.net.au>
Message-ID: <20130515014901.GR12246@verge.net.au>

On Wed, May 15, 2013 at 10:46:04AM +0900, Simon Horman wrote:
> On Wed, May 15, 2013 at 09:59:07AM +0900, Simon Horman wrote:
> > On Tue, May 14, 2013 at 05:38:38PM +0200, Maxime Ripard wrote:
> > > Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> > > specified") removed the need to explictly setup the init_irq field in
> > > the machine description when using only irqchip_init. Remove that
> > > declaration for shmobile as well.
> > > 
> > > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> > > ---
> > >  arch/arm/mach-shmobile/board-ape6evm.c | 2 --
> > >  1 file changed, 2 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
> > > index 55b8c9f..8dfbdba 100644
> > > --- a/arch/arm/mach-shmobile/board-ape6evm.c
> > > +++ b/arch/arm/mach-shmobile/board-ape6evm.c
> > > @@ -20,7 +20,6 @@
> > >  
> > >  #include <linux/gpio.h>
> > >  #include <linux/interrupt.h>
> > > -#include <linux/irqchip.h>
> > >  #include <linux/kernel.h>
> > >  #include <linux/pinctrl/machine.h>
> > >  #include <linux/platform_device.h>
> > > @@ -87,7 +86,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
> > >  };
> > >  
> > >  DT_MACHINE_START(APE6EVM_DT, "ape6evm")
> > > -	.init_irq	= irqchip_init,
> > >  	.init_time	= shmobile_timer_init,
> > >  	.init_machine	= ape6evm_add_standard_devices,
> > >  	.dt_compat	= ape6evm_boards_compat_dt,
> > 
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> Sorry, what I should have said is:
> 
> Queued up for v3.11 in the boards-spe6evm branch of my renesas tree

s/spe6evm/ape6evm/

> on kernel.org. It is included in the renesas-next-20130515 tag of
> that tree and should appear in linux-next in the not to distant future.
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From mgreer at animalcreek.com  Tue May 14 21:52:12 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Tue, 14 May 2013 18:52:12 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130515002537.GG5600@atomide.com>
References: <20130515002537.GG5600@atomide.com>
Message-ID: <20130515015212.GB3268@animalcreek.com>

On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> changed PM to not access IVA registers on omaps that don't have
> them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
> will stay on and block deeper idle states.
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> ---
> 
> Paul & Kevin, do you have better ideas for fixing this?
> 
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
>  	/* Clear any pending PRCM interrupts */
>  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
>  
> -	if (omap3_has_iva())
> -		omap3_iva_idle();
> +	/*
> +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> +	 */
> +	omap3_iva_idle();
>  
>  	omap3_d2d_idle();
>  }

[Kevin, Paul, some background: Tony discovered that the am3703 needs
to have omap3_iva_idle() called even though its not supposed to have
an IVA.]

This is potentially bad for other SoC's that don't have an IVA so I don't
think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
flag for the am3703 only since its the one with the bug.  Maybe something
in id.c:omap3xxx_check_features() but I don't see any existing way to check
for an am3703 vs. other am37xx SoCs.  Any ideas?

Another option, I suppose, is a dts entry but I don't like that at all.

Mark
--


From haojian.zhuang at gmail.com  Tue May 14 21:58:30 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 15 May 2013 09:58:30 +0800
Subject: [PATCH] ASoC: remove saarb and tavorevb3 machine drivers
In-Reply-To: <1368544041.1350.111.camel@x61.thuisdomein>
References: <1368544041.1350.111.camel@x61.thuisdomein>
Message-ID: <CAN1soZyUQRvDWcmefS3SnN=92rOp1LVknHFKzwqO6q88__ULMw@mail.gmail.com>

On Tue, May 14, 2013 at 11:07 PM, Paul Bolle <pebolle at tiscali.nl> wrote:
> Support for PXA95x was removed in v3.8. This means that the Kconfig
> symbols MACH_SAARB and MACH_TAVOREVB3 are no longer available. This
> leaves the SoC Audio support for Marvell Saarb and Marvell Tavor EVB3
> unbuildable. Remove these drivers too.
>
> Signed-off-by: Paul Bolle <pebolle at tiscali.nl>

Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>


From dinguyen at altera.com  Tue May 14 22:58:02 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Tue, 14 May 2013 21:58:02 -0500
Subject: [RFC PATCH] ARM: SOCFPGA: Enable PMU through the CTI
Message-ID: <1368586682-19848-1-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

SOCFPGA has a PMU(Performance Measurement Unit) that has its
IRQs routed through Coresight using the CTI(Cross-Trigger Interface).

This patch enables the PMU and initializes the CTI for usage by
oprofile/perfmon.

A lot of the code/idea was taken from this:
https://patchwork.kernel.org/patch/1432541/

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Ming Lei <ming.lei at canonical.com>
CC: Will Deacon <will.deacon at arm.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Russell King <linux at arm.linux.org.uk>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
---
 arch/arm/boot/dts/socfpga.dtsi      |   18 +++++
 arch/arm/include/asm/pmu.h          |    3 +
 arch/arm/kernel/perf_event.c        |   16 +++++
 arch/arm/mach-socfpga/Makefile      |    1 +
 arch/arm/mach-socfpga/socfpga.c     |   21 +++++-
 arch/arm/mach-socfpga/socfpga_cti.c |  125 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-socfpga/socfpga_cti.h |   16 +++++
 7 files changed, 199 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/socfpga_cti.c
 create mode 100644 arch/arm/mach-socfpga/socfpga_cti.h

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13..0f10a0a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -255,6 +255,24 @@
 			cache-level = <2>;
 		};
 
+		pmu {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <0 176 4>, <0 177 4>;
+			ranges;
+
+			cti0: cti0 at ff118000 {
+				compatible = "arm,coresight-cti";
+				reg = <0xff118000 0x100>;
+			};
+
+			cti1: cti1 at ff119000 {
+				compatible = "arm,coresight-cti";
+				reg = <0xff119000 0x100>;
+			};
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index f24edad..60324b3 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -38,6 +38,9 @@ struct arm_pmu_platdata {
 				  irq_handler_t pmu_handler);
 	int (*runtime_resume)(struct device *dev);
 	int (*runtime_suspend)(struct device *dev);
+	int (*init)(struct platform_device *pdev);
+	int (*start)(struct platform_device *pdev);
+	int (*stop)(struct platform_device *pdev);
 };
 
 #ifdef CONFIG_HW_PERF_EVENTS
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 8c3094d..66e9206 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -305,6 +305,11 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
+	struct platform_device *plat_device = armpmu->plat_device;
+	struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
+
+	if (plat->stop)
+		plat->stop(plat_device);
 	armpmu->free_irq(armpmu);
 	pm_runtime_put_sync(&armpmu->plat_device->dev);
 }
@@ -314,6 +319,7 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
 	int err;
 	struct platform_device *pmu_device = armpmu->plat_device;
+	struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
 
 	if (!pmu_device)
 		return -ENODEV;
@@ -324,6 +330,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
 		armpmu_release_hardware(armpmu);
 		return err;
 	}
+	if (plat->start)
+		plat->start(pmu_device);
 
 	return 0;
 }
@@ -506,10 +514,18 @@ static void armpmu_init(struct arm_pmu *armpmu)
 
 int armpmu_register(struct arm_pmu *armpmu, int type)
 {
+	struct platform_device *plat_device = armpmu->plat_device;
+	struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
+
 	armpmu_init(armpmu);
 	pm_runtime_enable(&armpmu->plat_device->dev);
 	pr_info("enabled with %s PMU driver, %d counters available\n",
 			armpmu->name, armpmu->num_events);
+
+	/* Platform specific initialization. ie. CTI enable */
+	if (plat->init)
+		plat->init(plat_device);
+
 	return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
 }
 
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6dd7a93..c7401d3 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,3 +4,4 @@
 
 obj-y					:= socfpga.o
 obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o
+obj-$(CONFIG_HW_PERF_EVENTS) += socfpga_cti.o
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a0513..64f90a5 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -24,8 +24,10 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/pmu.h>
 
 #include "core.h"
+#include "socfpga_cti.h"
 
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
@@ -33,6 +35,22 @@ void __iomem *rst_manager_base_addr;
 void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
+#ifdef CONFIG_HW_PERF_EVENTS
+static struct arm_pmu_platdata socfpga_pmu_platdata = {
+	.handle_irq = socfpga_pmu_handler,
+	.init = socfpga_init_cti,
+	.start = socfpga_start_cti,
+	.stop = socfpga_stop_cti,
+};
+#endif
+
+static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = {
+#ifdef CONFIG_HW_PERF_EVENTS
+	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &socfpga_pmu_platdata),
+#endif
+	{ /* sentinel */ }
+};
+
 static struct map_desc scu_io_desc __initdata = {
 	.virtual	= SOCFPGA_SCU_VIRT_BASE,
 	.pfn		= 0, /* run-time */
@@ -106,7 +124,8 @@ static void socfpga_cyclone5_restart(char mode, const char *cmd)
 static void __init socfpga_cyclone5_init(void)
 {
 	l2x0_of_init(0, ~0UL);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+			socfpga_auxdata_lookup, NULL);
 	of_clk_init(NULL);
 	socfpga_init_clocks();
 }
diff --git a/arch/arm/mach-socfpga/socfpga_cti.c b/arch/arm/mach-socfpga/socfpga_cti.c
new file mode 100644
index 0000000..10072c8
--- /dev/null
+++ b/arch/arm/mach-socfpga/socfpga_cti.c
@@ -0,0 +1,125 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <asm/mach/map.h>
+#include <asm/cti.h>
+#include <asm/pmu.h>
+
+#include "core.h"
+#include "socfpga_cti.h"
+
+#define SOCFPGA_NUM_CTI	2
+
+struct cti socfpga_cti_data[SOCFPGA_NUM_CTI];
+
+irqreturn_t socfpga_pmu_handler(int irq, void *dev, irq_handler_t handler)
+{
+	unsigned int handled = 0;
+	int i;
+
+	for (i = 0; i < SOCFPGA_NUM_CTI; i++)
+		if (irq == socfpga_cti_data[i].irq) {
+			cti_irq_ack(&socfpga_cti_data[i]);
+			handled = handler(irq, dev);
+		}
+
+	return IRQ_RETVAL(handled);
+}
+
+int socfpga_init_cti(struct platform_device *pdev)
+{
+	struct device_node *np, *np2;
+	void __iomem *cti0_addr;
+	void __iomem *cti1_addr;
+	u32 irq0, irq1;
+
+	np = pdev->dev.of_node;
+	np2 = of_find_compatible_node(np, NULL, "arm,coresight-cti");
+	if (!np2) {
+		dev_err(&pdev->dev, "PMU: Unable to find coresight-cti\n");
+		return -1;
+	}
+	cti0_addr = of_iomap(np2, 0);
+	if (!cti0_addr) {
+		dev_err(&pdev->dev, "PMU: ioremap for CTI failed\n");
+		return -1;
+	}
+
+	irq0 = platform_get_irq(pdev, 0);
+	if (irq0 < 0)
+		goto free_irq0;
+
+	np2 = of_find_compatible_node(np2, NULL, "arm,coresight-cti");
+	if (!np2) {
+		dev_err(&pdev->dev, "PMU: Unable to find coresight-cti\n");
+		goto err_iounmap;
+	}
+	cti1_addr = of_iomap(np2, 0);
+	if (!cti1_addr)
+		goto err_iounmap;
+
+	irq1 = platform_get_irq(pdev, 1);
+	if (irq1 < 0)
+		goto free_irq1;
+
+	/*configure CTI0 for pmu irq routing*/
+	cti_init(&socfpga_cti_data[0], cti0_addr,
+		irq0, CTI_MPU_IRQ_TRIG_OUT);
+	cti_unlock(&socfpga_cti_data[0]);
+	cti_map_trigger(&socfpga_cti_data[0],
+		CTI_MPU_IRQ_TRIG_IN, CTI_MPU_IRQ_TRIG_OUT, PMU_CHANNEL_0);
+
+	/*configure CTI1 for pmu irq routing*/
+	cti_init(&socfpga_cti_data[1], cti1_addr,
+		irq1, CTI_MPU_IRQ_TRIG_OUT);
+	cti_unlock(&socfpga_cti_data[1]);
+	cti_map_trigger(&socfpga_cti_data[1],
+		CTI_MPU_IRQ_TRIG_IN, CTI_MPU_IRQ_TRIG_OUT, PMU_CHANNEL_1);
+
+	dev_info(&pdev->dev, "PMU:CTI successfully enabled\n");
+	return 0;
+
+free_irq1:
+	iounmap(cti1_addr);
+err_iounmap:
+	free_irq(irq0, pdev);
+free_irq0:
+	iounmap(cti0_addr);
+	return -1;
+}
+
+int socfpga_start_cti(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < SOCFPGA_NUM_CTI; i++)
+		cti_enable(&socfpga_cti_data[i]);
+
+	return 0;
+}
+
+int socfpga_stop_cti(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < SOCFPGA_NUM_CTI; i++)
+		cti_disable(&socfpga_cti_data[i]);
+
+	return 0;
+}
+
diff --git a/arch/arm/mach-socfpga/socfpga_cti.h b/arch/arm/mach-socfpga/socfpga_cti.h
new file mode 100644
index 0000000..cbeb063
--- /dev/null
+++ b/arch/arm/mach-socfpga/socfpga_cti.h
@@ -0,0 +1,16 @@
+#ifndef __SOCFPGA_CTI_H
+#define __SOCFPGA_CTI_H
+
+#define CTI_MPU_IRQ_TRIG_IN	1
+#define CTI_MPU_IRQ_TRIG_OUT	6
+
+#define PMU_CHANNEL_0	0
+#define PMU_CHANNEL_1	1
+
+#ifdef CONFIG_HW_PERF_EVENTS
+extern irqreturn_t socfpga_pmu_handler(int irq, void *dev, irq_handler_t handler);
+extern int socfpga_init_cti(struct platform_device *pdev);
+extern int socfpga_start_cti(struct platform_device *pdev);
+extern int socfpga_stop_cti(struct platform_device *pdev);
+#endif
+#endif /* __SOCFPGA_CTI_H */
-- 
1.7.9.5




From horms+renesas at verge.net.au  Tue May 14 22:57:29 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 11:57:29 +0900
Subject: [PATCH v2 3/4] ARM: shmobile: marzen-reference: Initialise irqpin
In-Reply-To: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368586650-26263-4-git-send-email-horms+renesas@verge.net.au>

Empirically it appears to be necessary to call r8a7779_init_irq_extpin(1)
in order to initialise irqpin for use with IRQ1. This is already done in
the marzen board code. This adds the call to the marzen-reference board
code.

The motivation for this is to allow use of SMSC LAN, which uses IRQ1, with
marzen-reference.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 5332e89..f83b6d1 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -63,12 +63,18 @@ static const char *marzen_boards_compat_dt[] __initdata = {
 	NULL,
 };
 
+void __init marzen_init_irq(void)
+{
+	r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
+	r8a7779_init_irq_dt();
+}
+
 DT_MACHINE_START(MARZEN, "marzen")
 	.smp		= smp_ops(r8a7779_smp_ops),
 	.map_io		= r8a7779_map_io,
 	.init_early	= r8a7779_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= r8a7779_init_irq_dt,
+	.init_irq	= marzen_init_irq,
 	.init_machine	= marzen_init,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= marzen_boards_compat_dt,
-- 
1.8.2.1



From horms+renesas at verge.net.au  Tue May 14 22:57:30 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 11:57:30 +0900
Subject: [PATCH v2 4/4] ARM: shmobile: marzen-reference: Set SMSC lan to use
 irq-push-pull
In-Reply-To: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368586650-26263-5-git-send-email-horms+renesas@verge.net.au>

This change makes the DTS consistent with the platform data
that exists in board-marzen.c.

Empirically it does not appear to be necessary.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 10cfc7f..fe32e1a 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -40,6 +40,7 @@
 		phy-mode = "mii";
 		interrupt-parent = <&irqpin0>;
 		interrupts = <1 0x4>;
+		smsc,irq-push-pull;
 		reg-io-width = <4>;
 		vddvario-supply = <&fixedregulator3v3>;
 		vdd33a-supply = <&fixedregulator3v3>;
-- 
1.8.2.1



From horms+renesas at verge.net.au  Tue May 14 22:57:27 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 11:57:27 +0900
Subject: [PATCH v2 1/4] ARM: shmobile: marzen-reference: Reference the correct
 IRQ for ethernet
In-Reply-To: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368586650-26263-2-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

The SMSC ethernet controller uses an external IRQ line that goes through
the irqpin controller. Set the interrupt parent to irqpin0 and fix the
interrupt number.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 72be4c8..10cfc7f 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -38,8 +38,8 @@
 		compatible = "smsc,lan9220", "smsc,lan9115";
 		reg = <0x18000000 0x100>;
 		phy-mode = "mii";
-		interrupt-parent = <&gic>;
-		interrupts = <0 28 0x4>;
+		interrupt-parent = <&irqpin0>;
+		interrupts = <1 0x4>;
 		reg-io-width = <4>;
 		vddvario-supply = <&fixedregulator3v3>;
 		vdd33a-supply = <&fixedregulator3v3>;
-- 
1.8.2.1



From horms+renesas at verge.net.au  Tue May 14 22:57:26 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 11:57:26 +0900
Subject: [PATCH v2 0/4] marzen-reference ethernet patches
Message-ID: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>

Hi,

this series builds on work by Laurent Pinchart and in turn
prior work by Guennadi Liakhovetski and myself.

The four small patches attepts to fix SMSC ethernet support for
the marzen-reference board. It does seem to be sufficient in order
to initialise the NIC and complete a boot using nfsroot.
However, as reported by Laurent earlier, there appear to be
some issues with spurious interrupts.

This series is based on the renesas-next-20130515v2 tag of
my renesas branch.

Laurent Pinchart (2):
  ARM: shmobile: marzen-reference: Reference the correct IRQ for
    ethernet
  ARM: shmobile: marzen-reference: Update lan device name in pinctrl
    maps

Simon Horman (2):
  ARM: shmobile: marzen-reference: Initialise irqpin
  ARM: shmobile: marzen-reference: Set SMSC lan to use irq-push-pull

 arch/arm/boot/dts/r8a7779-marzen-reference.dts  |  5 +++--
 arch/arm/mach-shmobile/board-marzen-reference.c | 12 +++++++++---
 2 files changed, 12 insertions(+), 5 deletions(-)

-- 
1.8.2.1



From horms+renesas at verge.net.au  Tue May 14 22:57:28 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 15 May 2013 11:57:28 +0900
Subject: [PATCH v2 2/4] ARM: shmobile: marzen-reference: Update lan device
 name in pinctrl maps
In-Reply-To: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1368586650-26263-3-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

The ethernet device is instantiated from the device tree, use the
correct name in the pinctrl mappings.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 480d882..5332e89 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -43,9 +43,9 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
 				  "sdhi0_wp", "sdhi0"),
 	/* SMSC */
-	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "pfc-r8a7779",
 				  "intc_irq1_b", "intc"),
-	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "pfc-r8a7779",
 				  "lbsc_ex_cs0", "lbsc"),
 };
 
-- 
1.8.2.1



From ming.lei at canonical.com  Tue May 14 22:59:00 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Wed, 15 May 2013 10:59:00 +0800
Subject: [PATCH] ARM: DMA-mapping: mark all !DMA_TO_DEVICE pages in
 unmapping as clean
In-Reply-To: <alpine.LFD.2.03.1305141445480.31158@syhkavp.arg>
References: <1367572365-18905-1-git-send-email-ming.lei@canonical.com>
 <alpine.LFD.2.03.1305141445480.31158@syhkavp.arg>
Message-ID: <CACVXFVOEOj0HMFh=b-CLhy=YCs_M=UEkUWwaGjNagbORePW_tg@mail.gmail.com>

Hi,

On Wed, May 15, 2013 at 3:28 AM, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> On Fri, 3 May 2013, Ming Lei wrote:
>
>> It is common for one sg to include many pages, so mark all these
>> pages as clean to avoid unnecessary flushing on them in
>> set_pte_at() or update_mmu_cache().
>
> [...]
>
>> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
>> index e9db6b4..e63124a 100644
>> --- a/arch/arm/mm/dma-mapping.c
>> +++ b/arch/arm/mm/dma-mapping.c
>> @@ -879,10 +879,23 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
>>       dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
>>
>>       /*
>> -      * Mark the D-cache clean for this page to avoid extra flushing.
>> +      * Mark the D-cache clean for these pages to avoid extra flushing.
>>        */
>> -     if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
>> -             set_bit(PG_dcache_clean, &page->flags);
>> +     if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
>> +             unsigned long pfn;
>> +             size_t left = size;
>> +
>> +             pfn = page_to_pfn(page);
>
> Could the offset ever be greater than a page?  The code in
> dma_cache_maint_page() appears to be written with that possibility in
> mind.  So you should have:
>
>         pfn = page_to_pfn(page) + off / PAGE_SIZE;

Good catch, you are right.

>
>> +             if (off) {
>> +                     pfn++;
>> +                     left -= PAGE_SIZE - off % PAGE_SIZE;
>> +             }
>> +             while (left >= PAGE_SIZE) {
>> +                     page = pfn_to_page(pfn++);
>> +                     set_bit(PG_dcache_clean, &page->flags);
>> +                     left -= PAGE_SIZE;
>> +             }
>> +     }
>>  }
>
> Otherwise this looks fine to me.

I will send v1 with your ack, thanks for your review.

Thanks,
--
Ming Lei


From ming.lei at canonical.com  Wed May 15 00:09:49 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Wed, 15 May 2013 12:09:49 +0800
Subject: [PATCH v1] ARM: DMA-mapping: mark all !DMA_TO_DEVICE pages in
 unmapping as clean
Message-ID: <1368590989-5433-1-git-send-email-ming.lei@canonical.com>

It is common for one sg to include many pages, so mark all these
pages as clean to avoid unnecessary flushing on them in
set_pte_at() or update_mmu_cache().

The patch might improve loading performance of applciation code a bit.

On the below test code to read file(~1GByte size) from usb mass storage
disk to buffer created with mmap(PROT_READ | PROT_EXEC) on
Pandaboard, average ~1% improvement can be observed with the patch on
10 times test.

unsigned int sum = 0;

static unsigned long tv_diff(struct timeval *tv1, struct timeval *tv2)
{
	return (tv2->tv_sec - tv1->tv_sec) * 1000000 +
		(tv2->tv_usec - tv1->tv_usec);
}

int main(int argc, char *argv[])
{
	char *mbuffer;
	int fd;
	int i;
	unsigned long page_size, size;
	struct stat stat;
	struct timeval t1, t2;

	page_size = getpagesize();
	fd = open(argv[1], O_RDONLY);
	assert(fd >= 0);

	fstat(fd, &stat);
	size = stat.st_size;
	printf("%s: file %s, file size %lu, page size %lu\n", argv[0],
		read_filename, size, page_size);

	gettimeofday(&t1, NULL);
	mbuffer = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0);
	for (i = 0 ; i < size ; i += page_size)
		sum += mbuffer[i];
	munmap(mbuffer, page_size);
	gettimeofday(&t2, NULL);
	printf("\tread mmaped time: %luus\n", tv_diff(&t1, &t2));

	close(fd);
}

Acked-by: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Marek Szyprowski <m.szyprowski at samsung.com>
Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Ming Lei <ming.lei at canonical.com>
---
v1:
	- fix one mistake on computing pfn, pointed out by Nicolas

 arch/arm/mm/dma-mapping.c |   20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ef3e0f3..c038ec0 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -880,10 +880,24 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
 
 	/*
-	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 * Mark the D-cache clean for these pages to avoid extra flushing.
 	 */
-	if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
-		set_bit(PG_dcache_clean, &page->flags);
+	if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
+		unsigned long pfn;
+		size_t left = size;
+
+		pfn = page_to_pfn(page) + off / PAGE_SIZE;
+		off %= PAGE_SIZE;
+		if (off) {
+			pfn++;
+			left -= PAGE_SIZE - off;
+		}
+		while (left >= PAGE_SIZE) {
+			page = pfn_to_page(pfn++);
+			set_bit(PG_dcache_clean, &page->flags);
+			left -= PAGE_SIZE;
+		}
+	}
 }
 
 /**
-- 
1.7.9.5



From jh80.chung at samsung.com  Wed May 15 00:28:16 2013
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Wed, 15 May 2013 13:28:16 +0900
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1368571955-6652-5-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-5-git-send-email-dinguyen@altera.com>
Message-ID: <51930EE0.3010007@samsung.com>

On 05/15/2013 07:52 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Seungwon Jeon <tgih.jun at samsung.com>
> CC: Jaehoon Chung <jh80.chung at samsung.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: linux-mmc at vger.kernel.org
> ---
>  drivers/mmc/host/Kconfig          |    8 +++
>  drivers/mmc/host/Makefile         |    1 +
>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>  drivers/mmc/host/dw_mmc-socfpga.c |  141 +++++++++++++++++++++++++++++++++++++
>  drivers/mmc/host/dw_mmc.h         |    1 +
>  5 files changed, 151 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 9ab8f8d..1be2289 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>  
> +config MMC_DW_SOCFPGA
SOCFPGA? I think good that should be changed more generic.
> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
> +	depends on MMC_DW
> +	select MMC_DW_PLTFM
> +	help
> +	  This selects support for Altera SoCFPGA specific extensions to the
> +	  Synopsys DesignWare Memory Card Interface driver.
> +
>  config MMC_DW_PCI
>  	tristate "Synopsys Designware MCI support on PCI bus"
>  	depends on MMC_DW && PCI
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index cd32280..67718c1 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index f013e7e..866edef 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -31,8 +31,6 @@
>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
>  
> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
> -
>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
>  
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> new file mode 100644
> index 0000000..7eb3163
> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> @@ -0,0 +1,141 @@
> +/*
> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
> + *
> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> + *  Copyright (C) 2013 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Taken from dw_mmc_exynos.c
> + */
> +#include <linux/clk.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/dw_mmc.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include "dw_mmc.h"
> +#include "dw_mmc-pltfm.h"
> +
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
Is it vendor specific register offset?
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
Change more readable. ((drvsel & 0x7) << 0 | (smplsel & 0x7) << 3)?
> +
> +extern void __iomem *sys_manager_base_addr;
> +
> +/* SOCFPGA implementation specific driver private data */
> +struct dw_mci_socfpga_priv_data {
> +	u8	ciu_div;
> +	u32	hs_timing;
> +};
> +
> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv;
> +	struct device *dev = host->dev;
> +	int pwr_en;
> +
> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv) {
> +		dev_err(host->dev, "mem alloc failed for private data\n");
> +		return -ENOMEM;
> +	}
> +
> +	host->priv = priv;
> +
> +	if (of_property_read_u32(dev->of_node, "pwr-en", &pwr_en)) {
> +		dev_info(dev, "couldn't determine pwr-en, assuming pwr-en = 0\n");
> +		pwr_en = 0;
> +	}
> +
> +	/* Set PWREN bit */
> +	mci_writel(host, PWREN, pwr_en);
What is this setting? In dw-mmc.c, PWREN register should be set.
> +
> +	return 0;
> +}
> +
> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	clk_disable(host->ciu_clk);
> +	writel(priv->hs_timing, sys_manager_base_addr +
> +		SYSMGR_SDMMCGRP_CTRL_OFFSET);
> +	clk_enable(host->ciu_clk);
Why do you use the clk_disable/enable at this point?
> +
> +	host->bus_hz /= priv->ciu_div;
Didn't consider the "divide by zero"?
> +	return 0;
> +}
> +
> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
> +}
> +
> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +	struct device_node *np = host->dev->of_node;
> +	u32 timing[2];
> +	u32 div = 0;
> +	int ret;
> +
> +	of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> +	priv->ciu_div = div;
> +
> +	ret = of_property_read_u32_array(np,
> +			"altr,dw-mshc-sdr-timing", timing, 2);
> +	if (ret)
> +		return ret;
> +
> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> +	return 0;
> +}
> +
> +static const struct dw_mci_drv_data socfpga_drv_data = {
> +	.init			= dw_mci_socfpga_priv_init,
> +	.setup_clock		= dw_mci_socfpga_setup_clock,
> +	.prepare_command	= dw_mci_socfpga_prepare_command,
> +	.parse_dt		= dw_mci_socfpga_parse_dt,
> +};
> +
> +static const struct of_device_id dw_mci_socfpga_match[] = {
> +	{ .compatible = "altr,socfpga-dw-mshc",
> +			.data = &socfpga_drv_data, },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
> +
> +int dw_mci_socfpga_probe(struct platform_device *pdev)
> +{
> +	const struct dw_mci_drv_data *drv_data;
> +	const struct of_device_id *match;
> +
> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
> +	drv_data = match->data;
> +	return dw_mci_pltfm_register(pdev, drv_data);
> +}
> +
> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
> +	.probe		= dw_mci_socfpga_probe,
> +	.remove		= __exit_p(dw_mci_pltfm_remove),
> +	.driver		= {
> +		.name		= "dwmmc_socfpga",
> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
> +		.pm		= &dw_mci_pltfm_pmops,
> +	},
> +};
> +
> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
> +
> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:dwmmc-socfpga");
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 0b74189..3700cb2 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -111,6 +111,7 @@
>  #define SDMMC_INT_ERROR			0xbfc2
>  /* Command register defines */
>  #define SDMMC_CMD_START			BIT(31)
> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>  #define SDMMC_CMD_UPD_CLK		BIT(21)
> 



From broonie at kernel.org  Wed May 15 00:46:04 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 15 May 2013 08:46:04 +0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <51927DEB.7090001@balister.org>
References: <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum>
 <51927DEB.7090001@balister.org>
Message-ID: <20130515044604.GA24524@sirena.org.uk>

On Tue, May 14, 2013 at 02:09:47PM -0400, Philip Balister wrote:

> First of all, the driver that loads the bitstream into the fpga
> fabric does not know ANYTHING about what the bitstream does. So it
> cannot do any setup based on the contents of the file that is
> loaded. (And this can also be loaded during the SoC bootup,
> bypassing this driver completely)

This is a problem that is going to need to be fixed - there will be some
things going on the FPGAs that do need drivers and so there needs to be
some way to instantiate a driver for a FPGA image.  Things like adding
extra DT blobs along with the FPGA image have been talked about

> Second, there are four clocks that feed the FPGA fabric. We will
> want to set these clocks from user space somehow. It is perfectly
> valid to use a uio driver to interface with logic in the fpga. If we
> take the approach of using such general purpose techniques to
> interface with fpga logic, we must have ways for the user to control
> the fpga clocks.

Right, and if the specific device is being controlled by UIO then having
UIO create some clocks makes sense but then that should be integrated
into the UIO instantiation rather than done as a separate thing.
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From swarren at wwwdotorg.org  Wed May 15 00:59:58 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 May 2013 22:59:58 -0600
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <022d01ce5107$8bc668e0$a3533aa0$@lge.com>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org> <022d01ce5107$8bc668e0$a3533aa0$@lge.com>
Message-ID: <5193164E.6050400@wwwdotorg.org>

On 05/14/2013 07:00 PM, Jongsung Kim wrote:
> Stephen Warren <swarren at wwwdotorg.org> :
>> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
>> the BCM2835 chip), I see:
>>
>> =====
>> The UART provides:
>> * Separate 16x8 transmit and 16x12 receive FIFO memory.
>> ...
>> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
>> (PL011) Revision: r1p5 Technical Reference Manual.
>> =====
>>
>> That seems to imply that not all r1p5 PL011s actually have a depth-32 FIFO.
>> Perhaps this is a configurable property of the IP block, not something that
>> all r1p5 have?
> 
> All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
> TRM:
> 
> r1p4-r1p5	Contains the following differences in functionality:
> 		* The receive and transmit FIFOs are increased to a depth of 32.
> 		* The Revision field in the UARTPeriphID2 Register on page 3-24
> 		  bits [7:4] now reads back as 0x3.

Well, that certainly isn't true in practice. I think we should revert
this commit until we can determine what the problem is.

I validated that the periphid register in HW contains the r1p5 revision
(3), and the pcellid register does indeed contain the expected
0xb105f00d value. However, if I run the following hacky code in U-Boot
to determine the FIFO depth, it comes out as 16, which explains the
symptoms I'm seeing:

void find_fifo_depth(void)
{
	volatile u8 *uart = 0x20201000;
	int depth = 0;

	/* Wait for TX FIFO empty */
	while (!(uart[0x18] & 0x80))
		;

	/* Disable UART */
	uart[0x30] &= ~1;

	/* Push chars into TX FIFO until full */
	for (;;) {
		uart[0] = 'A' + depth;
		depth++;
		/* Done if FIFO full */
		if (uart[0x18] & 0x20)
			break;
		if (depth > 64) {
			depth = -1;
			break;
		}
	}

	/* Re-enable UART */
	uart[0x30] |= 1;

	printf("FIFO depth: %d\n", depth);
}


From broonie at kernel.org  Wed May 15 00:59:42 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 15 May 2013 08:59:42 +0400
Subject: [PATCH] ASoC: remove saarb and tavorevb3 machine drivers
In-Reply-To: <1368544041.1350.111.camel@x61.thuisdomein>
References: <1368544041.1350.111.camel@x61.thuisdomein>
Message-ID: <20130515045942.GK24524@sirena.org.uk>

On Tue, May 14, 2013 at 05:07:21PM +0200, Paul Bolle wrote:
> Support for PXA95x was removed in v3.8. This means that the Kconfig
> symbols MACH_SAARB and MACH_TAVOREVB3 are no longer available. This
> leaves the SoC Audio support for Marvell Saarb and Marvell Tavor EVB3
> unbuildable. Remove these drivers too.

Applied, thanks.
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From inki.dae at samsung.com  Wed May 15 01:19:09 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Wed, 15 May 2013 14:19:09 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
Message-ID: <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>



> -----Original Message-----
> From: Rob Clark [mailto:robdclark at gmail.com]
> Sent: Tuesday, May 14, 2013 10:39 PM
> To: Inki Dae
> Cc: linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham; YoungJun
> Cho; linux-arm-kernel at lists.infradead.org; linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Mon, May 13, 2013 at 10:52 PM, Inki Dae <inki.dae at samsung.com> wrote:
> >> well, for cache management, I think it is a better idea.. I didn't
> >> really catch that this was the motivation from the initial patch, but
> >> maybe I read it too quickly.  But cache can be decoupled from
> >> synchronization, because CPU access is not asynchronous.  For
> >> userspace/CPU access to buffer, you should:
> >>
> >>   1) wait for buffer
> >>   2) prepare-access
> >>   3)  ... do whatever cpu access to buffer ...
> >>   4) finish-access
> >>   5) submit buffer for new dma-operation
> >>
> >
> >
> > For data flow from CPU to DMA device,
> > 1) wait for buffer
> > 2) prepare-access (dma_buf_begin_cpu_access)
> > 3) cpu access to buffer
> >
> >
> > For data flow from DMA device to CPU
> > 1) wait for buffer
> 
> Right, but CPU access isn't asynchronous (from the point of view of
> the CPU), so there isn't really any wait step at this point.  And if
> you do want the CPU to be able to signal a fence from userspace for
> some reason, you probably what something file/fd based so the
> refcnting/cleanup when process dies doesn't leave some pending DMA
> action wedged.  But I don't really see the point of that complexity
> when the CPU access isn't asynchronous in the first place.
>

There was my missing comments, please see the below sequence.

For data flow from CPU to DMA device and then from DMA device to CPU,
1) wait for buffer <- at user side - ioctl(fd, DMA_BUF_GET_FENCE, ...)
	- including prepare-access (dma_buf_begin_cpu_access)
2) cpu access to buffer
3) wait for buffer <- at device driver
	- but CPU is already accessing the buffer so blocked.
4) signal <- at user side - ioctl(fd, DMA_BUF_PUT_FENCE, ...)
5) the thread, blocked at 3), is waked up by 4).
	- and then finish-access (dma_buf_end_cpu_access)
6) dma access to buffer
7) wait for buffer <- at user side - ioctl(fd, DMA_BUF_GET_FENCE, ...)
	- but DMA is already accessing the buffer so blocked.
8) signal <- at device driver
9) the thread, blocked at 7), is waked up by 8)
	- and then prepare-access (dma_buf_begin_cpu_access)
10 cpu access to buffer

Basically, 'wait for buffer' includes buffer synchronization, committing
processing, and cache operation. The buffer synchronization means that a
current thread should wait for other threads accessing a shared buffer until
the completion of their access. And the committing processing means that a
current thread possesses the shared buffer so any trying to access the
shared buffer by another thread makes the thread to be blocked. However, as
I already mentioned before, it seems that these user interfaces are so ugly
yet. So we need better way.

Give me more comments if there is my missing point :)

Thanks,
Inki Dae

> BR,
> -R
> 
> 
> > 2) finish-access (dma_buf_end _cpu_access)
> > 3) dma access to buffer
> >
> > 1) and 2) are coupled with one function: we have implemented
> > fence_helper_commit_reserve() for it.
> >
> > Cache control(cache clean or cache invalidate) is performed properly
> > checking previous access type and current access type.
> > And the below is actual codes for it,



From rusty at rustcorp.com.au  Wed May 15 00:29:29 2013
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Wed, 15 May 2013 13:59:29 +0930
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <CAAHg+Hi6BHqwOznnC9qxkc5pBWz7r5qpz9Nhh=EeNenhjhHohg@mail.gmail.com>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
 <8761yn382w.fsf@rustcorp.com.au>
 <CAAHg+Hi6BHqwOznnC9qxkc5pBWz7r5qpz9Nhh=EeNenhjhHohg@mail.gmail.com>
Message-ID: <87hai427di.fsf@rustcorp.com.au>

Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
> Hi Rusty,
>
> On 13 May 2013 08:22, Rusty Russell <rusty at rustcorp.com.au> wrote:
>> Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
>>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>>> ---
>>>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
>>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> OK, I applied this to the lyx master, with three changes:
>> 1) Changed "filed" to "field".
>> 2) Added ", or even acknowledging the feature" after "without
>>    initializing virtio queues".
>> 3) Added an initial point to the Device Initialization section:
>>
>>    1. If the VIRTIO_CONSOLE_F_EMERG_WRITE feature is offered, the
>>    emerg_wr field of the configuration can be written at any time. Thus
>>    it should work for very early boot debugging output as well as
>>    catastophic OS failures (eg. virtio ring corruption).
>
> Thanks for applying this patch.
> Have you also applied first patch ([PATCH V2 1/3] virtio: console: Add
> emergency writeonly register to config space)
> with this?  (https://lkml.org/lkml/2013/5/6/169)

Would like Amit's Ack, since he's de-facto console maintainer.

I've reproduced it below.

Cheers,
Rusty.

Subject: [PATCH V2 1/3] virtio: console: Add emergency writeonly register to config space
Date: Mon,  6 May 2013 17:49:49 +0530
Message-Id: <1367842791-30285-2-git-send-email-pranavkumar at linaro.org>
X-Mailer: git-send-email 1.7.9.5
In-Reply-To: <1367842791-30285-1-git-send-email-pranavkumar at linaro.org>
References: <1367842791-30285-1-git-send-email-pranavkumar at linaro.org>
X-Gm-Message-State: ALoCoQmDOoCdPmDpT+VgLwYAlJHmkUTB8sEAHVSbrNxWBzYgPHFT9rQ2A9dR8fToM81cHDZDppGx

This patch adds an emerg_wr register (writeonly) in config space
of virtio console device which can be used for debugging.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 include/uapi/linux/virtio_console.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/uapi/linux/virtio_console.h b/include/uapi/linux/virtio_console.h
index ee13ab6..3fd0dce 100644
--- a/include/uapi/linux/virtio_console.h
+++ b/include/uapi/linux/virtio_console.h
@@ -38,6 +38,7 @@
 /* Feature bits */
 #define VIRTIO_CONSOLE_F_SIZE	0	/* Does host provide console size? */
 #define VIRTIO_CONSOLE_F_MULTIPORT 1	/* Does host provide multiple ports? */
+#define VIRTIO_CONSOLE_F_EMERG_WRITE 2 /* Does host support emergency write? */
 
 #define VIRTIO_CONSOLE_BAD_ID		(~(u32)0)
 
@@ -48,6 +49,8 @@ struct virtio_console_config {
 	__u16 rows;
 	/* max. number of ports this device can hold */
 	__u32 max_nr_ports;
+	/* emergency write register */
+	__u32 emerg_wr;
 } __attribute__((packed));
 
 /*




From nm at ti.com  Wed May 15 01:29:16 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 15 May 2013 00:29:16 -0500
Subject: [PATCH v3] ARM:dts:omap4-panda:Update the LED support for the
 panda DTS
In-Reply-To: <1368541076-6854-1-git-send-email-dmurphy@ti.com>
References: <1368541076-6854-1-git-send-email-dmurphy@ti.com>
Message-ID: <20130515052916.GA15607@kahuna>

$subject - add a space?
s/ARM:dts:omap4-panda:Update/ARM: dts: omap4-panda: Update/ ?

On 09:17-20130514, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
> 
> A1-A3 = gpio_wk7
Thanks for fixing this - this is a key fix else, GPIO_7 which controls
VSEL for VDD_MPU on PandaBoard-ES will create all kind of ruckus (change
voltage on heartbeat)!
> ES = gpio_110
> 
> There is no change to LED D2
> 
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
> 
> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> ---
[...]
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..8d1ba03 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,43 @@
>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>  		>;
>  };
> +
> +&leds {
> +	compatible = "gpio-leds";
> +	heartbeat {
> +		label = "pandaboard::status1";
> +		gpios = <&gpio4 14 0>;
> +		linux,default-trigger = "heartbeat";
> +	};
> +	mmc {
> +		label = "pandaboard::status2";
> +		gpios = <&gpio1 8 0>;
> +		linux,default-trigger = "gpio";
mmc0?
> +	};
> +};
> +
Other that that,
Tested-by: Nishanth Menon <nm at ti.com>
-- 
Regards,
Nishanth Menon


From amit.shah at redhat.com  Wed May 15 01:30:32 2013
From: amit.shah at redhat.com (Amit Shah)
Date: Wed, 15 May 2013 11:00:32 +0530
Subject: [PATCH V2 2/3] Documentation: virtio: Add emergency write
 (emerg_wr) config register in virtio console.
In-Reply-To: <87hai427di.fsf@rustcorp.com.au>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-3-git-send-email-pranavkumar@linaro.org>
 <8761yn382w.fsf@rustcorp.com.au>
 <CAAHg+Hi6BHqwOznnC9qxkc5pBWz7r5qpz9Nhh=EeNenhjhHohg@mail.gmail.com>
 <87hai427di.fsf@rustcorp.com.au>
Message-ID: <20130515053032.GA32133@amit.redhat.com>

On (Wed) 15 May 2013 [13:59:29], Rusty Russell wrote:
> Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
> > Hi Rusty,
> >
> > On 13 May 2013 08:22, Rusty Russell <rusty at rustcorp.com.au> wrote:
> >> Pranavkumar Sawargaonkar <pranavkumar at linaro.org> writes:
> >>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> >>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> >>> ---
> >>>  Documentation/virtual/virtio-spec.txt |    8 +++++++-
> >>>  1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >> OK, I applied this to the lyx master, with three changes:
> >> 1) Changed "filed" to "field".
> >> 2) Added ", or even acknowledging the feature" after "without
> >>    initializing virtio queues".
> >> 3) Added an initial point to the Device Initialization section:
> >>
> >>    1. If the VIRTIO_CONSOLE_F_EMERG_WRITE feature is offered, the
> >>    emerg_wr field of the configuration can be written at any time. Thus
> >>    it should work for very early boot debugging output as well as
> >>    catastophic OS failures (eg. virtio ring corruption).
> >
> > Thanks for applying this patch.
> > Have you also applied first patch ([PATCH V2 1/3] virtio: console: Add
> > emergency writeonly register to config space)
> > with this?  (https://lkml.org/lkml/2013/5/6/169)
> 
> Would like Amit's Ack, since he's de-facto console maintainer.

I've been away, and am reviewing the discussions here.  Expect a
response later today.

Thanks,

		Amit


From kishon at ti.com  Wed May 15 02:21:33 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Wed, 15 May 2013 11:51:33 +0530
Subject: [PATCH] ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
In-Reply-To: <20130511023557.GB28602@atomide.com>
References: <20130511023557.GB28602@atomide.com>
Message-ID: <5193296D.5040001@ti.com>

On Saturday 11 May 2013 08:05 AM, Tony Lindgren wrote:
> Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to
> OMAP3+ boards) added support for MUSB on omap3 for device tree,
> but added the interrupts the wrong way probably as they were
> copied from the omap4.dtsi file. On omap3 we have TI specific
> interrupt controller, not GIC.
>
> Fix this by specifying the interrupt following the TI INTC
> binding.
>
> Without this fix MUSB won't work as it is trying to use
> irq0 instead of irq92.
>
> Signed-off-by: Tony Lindgren <tony at atomide.com>
Tested in beagleboard-xm

Tested-by: Kishon Vijay Abraham I <kishon at ti.com>
>
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -516,7 +516,7 @@
>   		usb_otg_hs: usb_otg_hs at 480ab000 {
>   			compatible = "ti,omap3-musb";
>   			reg = <0x480ab000 0x1000>;
> -			interrupts = <0 92 0x4>, <0 93 0x4>;
> +			interrupts = <92>, <93>;
>   			interrupt-names = "mc", "dma";
>   			ti,hwmods = "usb_otg_hs";
>   			multipoint = <1>;
>



From kishon at ti.com  Wed May 15 02:42:41 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Wed, 15 May 2013 12:12:41 +0530
Subject: [PATCH] ARM: dts: omap3 beagle: Add usb otg hs dt data
Message-ID: <1368600161-10351-1-git-send-email-kishon@ti.com>

Added board specific dt data for omap3 beagle in omap3-beagle.dts
file.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap3-beagle.dts |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..02bf5d0 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -142,3 +142,10 @@
 	 */
 	ti,pulldowns = <0x03a1c4>;
 };
+
+&usb_otg_hs {
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        mode = <3>;
+        power = <50>;
+};
-- 
1.7.10.4



From maxime.ripard at free-electrons.com  Wed May 15 04:34:30 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 15 May 2013 10:34:30 +0200
Subject: [PATCH] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>
References: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>
Message-ID: <51934896.3000506@free-electrons.com>

Hi Carlo,

Le 12/05/2013 22:36, Carlo Caione a ?crit :
> This patch adds the driver for the watchdog found in the Allwinner A10 and
> A13 SoCs. It has DT-support and uses the new watchdog framework.
> 
> Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
> ---
>  drivers/watchdog/Kconfig     |  10 ++
>  drivers/watchdog/Makefile    |   1 +
>  drivers/watchdog/sunxi_wdt.c | 218 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 229 insertions(+)
>  create mode 100644 drivers/watchdog/sunxi_wdt.c
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index e89fc31..473e670 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -299,6 +299,16 @@ config ORION_WATCHDOG
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called orion_wdt.
>  
> +config SUNXI_WATCHDOG
> +	tristate "Sunxi watchdog"

Maybe mention what sunxi is? something like "Allwinner SoCs watchdog
support"

> +	depends on ARCH_SUNXI
> +	select WATCHDOG_CORE
> +	help
> +	  Say Y here to include support for the watchdog timer
> +	  in Allwinner A10 and A13.

I'd be more generic here. As far as we know, this code is found in A10,
A10s, A13, and can easily be adapted to support the A31 (and I suspect
the A20 as well). Something like "Allwinner SoCs"

> +	  To compile this driver as a module, choose M here: the
> +	  module will be called sunxi_wdt.
> +
>  config COH901327_WATCHDOG
>  	bool "ST-Ericsson COH 901 327 watchdog"
>  	depends on ARCH_U300
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index a300b94..5012d5f 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
>  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
>  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
>  obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
> +obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
>  obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
>  obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
>  obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
> diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
> new file mode 100644
> index 0000000..fe193b3
> --- /dev/null
> +++ b/drivers/watchdog/sunxi_wdt.c
> @@ -0,0 +1,218 @@
> +/*
> + *      sunxi Watchdog Driver
> + *
> + *      Copyright (c) 2013 Carlo Caione
> + *                    2012 Henrik Nordstrom
> + *
> + *      This program is free software; you can redistribute it and/or
> + *      modify it under the terms of the GNU General Public License
> + *      as published by the Free Software Foundation; either version
> + *      2 of the License, or (at your option) any later version.
> + *
> + *      Based on xen_wdt.c
> + *      (c) Copyright 2010 Novell, Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +#include <linux/watchdog.h>
> +
> +#define WDT_MAX_TIMEOUT         16
> +#define WDT_MIN_TIMEOUT         1
> +#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
> +#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
> +
> +#define WDT_CTRL                0x00
> +#define WDT_MODE                0x04
> +
> +#define WDT_MODE_RST_EN         (1 << 1)
> +#define WDT_MODE_EN             (1 << 0)
> +
> +#define WDT_CTRL_RESTART        (1 << 0)

I'd prefer to see the bits values just behind the register they belong to.

> +#define WDT_CTRL_RESERVED       (0x0a57 << 1)
> +#define DRV_NAME		"sunxi-wdt"
> +#define DRV_VERSION		"1.0"
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +static int heartbeat = WDT_MAX_TIMEOUT;
> +
> +static const int wdt_timeout_map[] = {
> +	[1] = 0b0001,
> +	[2] = 0b0010,
> +	[3] = 0b0011,
> +	[4] = 0b0100,
> +	[5] = 0b0101,
> +	[6] = 0b0110,
> +	[8] = 0b0111,
> +	[10] = 0b1000,
> +	[12] = 0b1001,
> +	[14] = 0b1010,
> +	[16] = 0b1011,
> +};

It would be great to have a comment about what this map is here for and
how you store the values.

You don't support the 0.5s timeout here as well. I know why, but some
new comer might not, so I guess it would be great to add it to the
comment as well.

Moreover, I'd really like this to be supported. Maybe, since obviously
we can't put a value at the index 0.5, maybe saying that the 0 index is
actually this 0.5ms timeout value?

> +
> +static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	reg = ioread32(wdt_base + WDT_CTRL);
> +	reg |= (WDT_CTRL_RESTART | WDT_CTRL_RESERVED);

The RESERVED part is not needed, especially if you OR the values already
there, it looks like it could trigger something nasty.

> +	iowrite32(reg, wdt_base + WDT_CTRL);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
> +		unsigned int timeout)
> +{
> +	u32 reg;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout]))
> +		return -EINVAL;
> +
> +	sunxi_wdt_dev->timeout = timeout;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg &= ~(WDT_TIMEOUT_MASK);
> +	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	sunxi_wdt_ping(sunxi_wdt_dev);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg &= ~(WDT_MODE_RST_EN | WDT_MODE_EN);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	int ret;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
> +	if (ret < 0)
> +		return ret;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	return 0;
> +}
> +
> +static const struct watchdog_info sunxi_wdt_info = {
> +	.identity	= DRV_NAME,
> +	.options	= WDIOF_SETTIMEOUT |
> +			  WDIOF_KEEPALIVEPING |
> +			  WDIOF_MAGICCLOSE,
> +};
> +
> +static const struct watchdog_ops sunxi_wdt_ops = {
> +	.owner		= THIS_MODULE,
> +	.start		= sunxi_wdt_start,
> +	.stop		= sunxi_wdt_stop,
> +	.ping		= sunxi_wdt_ping,
> +	.set_timeout	= sunxi_wdt_set_timeout,
> +};
> +
> +static struct watchdog_device sunxi_wdt_dev = {
> +	.info		= &sunxi_wdt_info,
> +	.ops		= &sunxi_wdt_ops,
> +	.timeout	= WDT_MAX_TIMEOUT,
> +	.max_timeout	= WDT_MAX_TIMEOUT,
> +	.min_timeout	= WDT_MIN_TIMEOUT,
> +};
> +
> +static int __init sunxi_wdt_probe(struct platform_device *pdev)
> +{
> +	int err;
> +	void __iomem *wdt_base;
> +
> +	wdt_base = of_iomap(pdev->dev.of_node, 0);
> +	if (unlikely(!wdt_base)) {
> +		err = -ENOMEM;
> +		goto error_mem_out;
> +	}
> +
> +	sunxi_wdt_dev.parent = &pdev->dev;
> +	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
> +	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
> +
> +	err = watchdog_register_device(&sunxi_wdt_dev);
> +	if (unlikely(err))
> +		goto error_wdt;
> +
> +	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
> +
> +	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
> +			sunxi_wdt_dev.timeout, nowayout);
> +	return 0;
> +
> +error_wdt:
> +	iounmap(wdt_base);
> +error_mem_out:
> +	return err;
> +}
> +
> +static int __exit sunxi_wdt_remove(struct platform_device *pdev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
> +
> +	sunxi_wdt_stop(&sunxi_wdt_dev);
> +	watchdog_unregister_device(&sunxi_wdt_dev);
> +	iounmap(wdt_base);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sunxi_wdt_dt_ids[] = {
> +	{ .compatible = "allwinner,sun4i-wdt" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
> +
> +static struct platform_driver sunxi_wdt_driver = {
> +	.probe		= sunxi_wdt_probe,
> +	.remove		= sunxi_wdt_remove,
> +	.driver		= {
> +		.owner		= THIS_MODULE,
> +		.name		= DRV_NAME,
> +		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
> +	},
> +};
> +
> +module_platform_driver(sunxi_wdt_driver);
> +
> +module_param(heartbeat, int, 0);
> +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
> +
> +module_param(nowayout, bool, 0);
> +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
> +		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
> +MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
> +MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
> +MODULE_VERSION(DRV_VERSION);
> 


-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Wed May 15 04:43:00 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 15 May 2013 10:43:00 +0200
Subject: [PATCH] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>
References: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>
Message-ID: <51934A94.3070503@free-electrons.com>

Hi,

Le 12/05/2013 22:36, Carlo Caione a ?crit :
> This patch adds the driver for the watchdog found in the Allwinner A10 and
> A13 SoCs. It has DT-support and uses the new watchdog framework.

I'd like to start some more general discussion here.

All the sunxi boards don't have a PMIC to do the reset properly, so we
chose to do the reboot hook using the watchdog.

How is that handled usually? Obviously, we could have a rather minimal
approach, like this one, where we have code duplication between the arch
code and the watchdog driver code, which is probably not so nice, but I
couldn't find either any convention for this, or a piece of
infrastructure to do so.

What could be the preferred solution?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From 21cnbao at gmail.com  Wed May 15 04:43:26 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 15 May 2013 16:43:26 +0800
Subject: [PATCH] drivers/rtc/rtc-sirfsoc.c: add rtc drivers for CSR
 SiRFprimaII and SiRFatlasVI
Message-ID: <1368607406-28474-1-git-send-email-21cnbao@gmail.com>

From: Xianglong Du <Xianglong.Du at csr.com>

On CSR SiRFprimaII/atlasVI, there is a programmable 16-bit divider (RTC_DIV)
that divides the input 32.768KHz clock to the frequency that users need
(E.g. 1 Hz). The divided real-time clock will be used to drive a 32-bit counter
(RTC_COUNTER) that provides users with the actual time.
In each cycle of the divided real-time clock, there is a Hertz interrupt generated
to the RISC. Users can also configure an alarm (RTC_ALARM). When RTC_COUNTER matches
the alarm, there will be an alarm interrupt generated to the RISC.
The system RTC can generate an alarm wake-up signal to notify the power controller
to wake up from power saving mode.

Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/boot/dts/atlas6.dtsi |    2 +-
 arch/arm/boot/dts/prima2.dtsi |    2 +-
 drivers/rtc/Kconfig           |    7 +
 drivers/rtc/Makefile          |    1 +
 drivers/rtc/rtc-sirfsoc.c     |  475 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 485 insertions(+), 2 deletions(-)
 create mode 100644 drivers/rtc/rtc-sirfsoc.c

diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index c101f3e..76ebcf2 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -613,7 +613,7 @@
 		};
 
 		rtc-iobg {
-			compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+			compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3c76dc2..45399b7 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -608,7 +608,7 @@
 		};
 
 		rtc-iobg {
-			compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+			compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x80030000 0x10000>;
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 0c81915..ba1fb8d 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1235,6 +1235,13 @@ config RTC_DRV_SNVS
 	   This driver can also be built as a module, if so, the module
 	   will be called "rtc-snvs".
 
+config RTC_DRV_SIRFSOC
+	tristate "SiRFSOC RTC"
+	depends on ARCH_SIRF
+	help
+	  Say "yes" here to support the real time clock on SiRF SOC chips.
+	  This driver can also be built as a module called rtc-sirfsoc.
+
 comment "HID Sensor RTC drivers"
 
 config RTC_DRV_HID_SENSOR_TIME
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index c33f86f..a4ddc5b 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -128,3 +128,4 @@ obj-$(CONFIG_RTC_DRV_VT8500)	+= rtc-vt8500.o
 obj-$(CONFIG_RTC_DRV_WM831X)	+= rtc-wm831x.o
 obj-$(CONFIG_RTC_DRV_WM8350)	+= rtc-wm8350.o
 obj-$(CONFIG_RTC_DRV_X1205)	+= rtc-x1205.o
+obj-$(CONFIG_RTC_DRV_SIRFSOC)	+= rtc-sirfsoc.o
diff --git a/drivers/rtc/rtc-sirfsoc.c b/drivers/rtc/rtc-sirfsoc.c
new file mode 100644
index 0000000..aa7ed4b
--- /dev/null
+++ b/drivers/rtc/rtc-sirfsoc.c
@@ -0,0 +1,475 @@
+/*
+ * SiRFSoC Real Time Clock interface for Linux
+ *
+ * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/rtc/sirfsoc_rtciobrg.h>
+
+
+#define RTC_CN			0x00
+#define RTC_ALARM0		0x04
+#define RTC_ALARM1		0x18
+#define RTC_STATUS		0x08
+#define RTC_SW_VALUE            0x40
+#define SIRFSOC_RTC_AL1E	(1<<6)
+#define SIRFSOC_RTC_AL1		(1<<4)
+#define SIRFSOC_RTC_HZE		(1<<3)
+#define SIRFSOC_RTC_AL0E	(1<<2)
+#define SIRFSOC_RTC_HZ		(1<<1)
+#define SIRFSOC_RTC_AL0		(1<<0)
+#define RTC_DIV			0x0c
+#define RTC_DEEP_CTRL		0x14
+#define RTC_CLOCK_SWITCH	0x1c
+#define SIRFSOC_RTC_CLK		0x03	/* others are reserved */
+
+/* Refer to RTC DIV switch */
+#define RTC_HZ			16
+
+/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
+#define RTC_SHIFT		4
+
+#define INTR_SYSRTC_CN		0x48
+
+struct sirfsoc_rtc_drv {
+	struct rtc_device	*rtc;
+	u32			rtc_base;
+	u32			irq;
+	/* Overflow for every 8 years extra time */
+	u32			overflow_rtc;
+#ifdef CONFIG_PM
+	u32		saved_counter;
+	u32		saved_overflow_rtc;
+#endif
+};
+
+static int sirfsoc_rtc_read_alarm(struct device *dev,
+		struct rtc_wkalrm *alrm)
+{
+	unsigned long rtc_alarm, rtc_count;
+	struct sirfsoc_rtc_drv *rtcdrv;
+
+	rtcdrv = (struct sirfsoc_rtc_drv *)dev_get_drvdata(dev);
+
+	local_irq_disable();
+
+	rtc_count = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
+
+	rtc_alarm = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_ALARM0);
+	memset(alrm, 0, sizeof(struct rtc_wkalrm));
+
+	/*
+	 * assume alarm interval not beyond one round counter overflow_rtc:
+	 * 0->0xffffffff
+	 */
+	/* if alarm is in next overflow cycle */
+	if (rtc_count > rtc_alarm)
+		rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
+				<< (BITS_PER_LONG - RTC_SHIFT)
+				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
+	else
+		rtc_time_to_tm(rtcdrv->overflow_rtc
+				<< (BITS_PER_LONG - RTC_SHIFT)
+				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
+	if (sirfsoc_rtc_iobrg_readl(
+			rtcdrv->rtc_base + RTC_STATUS) & SIRFSOC_RTC_AL0E)
+		alrm->enabled = 1;
+	local_irq_enable();
+
+	return 0;
+}
+
+static int sirfsoc_rtc_set_alarm(struct device *dev,
+		struct rtc_wkalrm *alrm)
+{
+	unsigned long rtc_status_reg, rtc_alarm;
+	struct sirfsoc_rtc_drv *rtcdrv;
+	rtcdrv = (struct sirfsoc_rtc_drv *)dev_get_drvdata(dev);
+
+	if (alrm->enabled) {
+		rtc_tm_to_time(&(alrm->time), &rtc_alarm);
+
+		local_irq_disable();
+
+		rtc_status_reg = sirfsoc_rtc_iobrg_readl(
+				rtcdrv->rtc_base + RTC_STATUS);
+		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
+			/*
+			 * An ongoing alarm in progress - ingore it and not
+			 * to return EBUSY
+			 */
+			dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
+		}
+
+		sirfsoc_rtc_iobrg_writel(
+			rtc_alarm << RTC_SHIFT, rtcdrv->rtc_base + RTC_ALARM0);
+		rtc_status_reg &= ~0x07; /* mask out the lower status bits */
+		/*
+		 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
+		 * Writing 1 into this bit will clear it
+		 */
+		rtc_status_reg |= SIRFSOC_RTC_AL0;
+		/* enable the RTC alarm interrupt */
+		rtc_status_reg |= SIRFSOC_RTC_AL0E;
+		sirfsoc_rtc_iobrg_writel(
+			rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
+		local_irq_enable();
+	} else {
+		/*
+		 * if this function was called with enabled=0
+		 * then it could mean that the application is
+		 * trying to cancel an ongoing alarm
+		 */
+		local_irq_disable();
+
+		rtc_status_reg = sirfsoc_rtc_iobrg_readl(
+				rtcdrv->rtc_base + RTC_STATUS);
+		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
+			/* clear the RTC status register's alarm bit */
+			rtc_status_reg &= ~0x07;
+			/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
+			rtc_status_reg |= (SIRFSOC_RTC_AL0);
+			/* Clear the Alarm enable bit */
+			rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
+
+			sirfsoc_rtc_iobrg_writel(rtc_status_reg,
+					rtcdrv->rtc_base + RTC_STATUS);
+		}
+
+		local_irq_enable();
+	}
+
+	return 0;
+}
+
+static int sirfsoc_rtc_read_time(struct device *dev,
+		struct rtc_time *tm)
+{
+	unsigned long tmp_rtc = 0;
+	struct sirfsoc_rtc_drv *rtcdrv;
+	rtcdrv = (struct sirfsoc_rtc_drv *)dev_get_drvdata(dev);
+	/*
+	 * This patch is taken from WinCE - Need to validate this for
+	 * correctness. To work around sirfsoc RTC counter double sync logic
+	 * fail, read several times to make sure get stable value.
+	 */
+	do {
+		tmp_rtc = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
+		cpu_relax();
+	} while (tmp_rtc != sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN));
+
+	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
+					tmp_rtc >> RTC_SHIFT, tm);
+	return 0;
+}
+
+static int sirfsoc_rtc_set_time(struct device *dev,
+		struct rtc_time *tm)
+{
+	unsigned long rtc_time;
+	struct sirfsoc_rtc_drv *rtcdrv;
+	rtcdrv = (struct sirfsoc_rtc_drv *)dev_get_drvdata(dev);
+
+	rtc_tm_to_time(tm, &rtc_time);
+
+	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
+
+	sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
+			rtcdrv->rtc_base + RTC_SW_VALUE);
+	sirfsoc_rtc_iobrg_writel(
+			rtc_time << RTC_SHIFT, rtcdrv->rtc_base + RTC_CN);
+
+	return 0;
+}
+
+static int sirfsoc_rtc_ioctl(struct device *dev, unsigned int cmd,
+		unsigned long arg)
+{
+	switch (cmd) {
+	case RTC_PIE_ON:
+	case RTC_PIE_OFF:
+	case RTC_UIE_ON:
+	case RTC_UIE_OFF:
+	case RTC_AIE_ON:
+	case RTC_AIE_OFF:
+		return 0;
+
+	default:
+		return -ENOIOCTLCMD;
+	}
+}
+
+static const struct rtc_class_ops sirfsoc_rtc_ops = {
+	.read_time = sirfsoc_rtc_read_time,
+	.set_time = sirfsoc_rtc_set_time,
+	.read_alarm = sirfsoc_rtc_read_alarm,
+	.set_alarm = sirfsoc_rtc_set_alarm,
+	.ioctl = sirfsoc_rtc_ioctl
+};
+
+static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
+{
+	struct sirfsoc_rtc_drv *rtcdrv = pdata;
+	unsigned long rtc_status_reg = 0x0;
+	unsigned long events = 0x0;
+
+	rtc_status_reg = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_STATUS);
+	/* this bit will be set ONLY if an alarm was active
+	 * and it expired NOW
+	 * So this is being used as an ASSERT
+	 */
+	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
+		/*
+		 * clear the RTC status register's alarm bit
+		 * mask out the lower status bits
+		 */
+		rtc_status_reg &= ~0x07;
+		/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
+		rtc_status_reg |= (SIRFSOC_RTC_AL0);
+		/* Clear the Alarm enable bit */
+		rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
+	}
+	sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
+	/* this should wake up any apps polling/waiting on the read
+	 * after setting the alarm
+	 */
+	events |= RTC_IRQF | RTC_AF;
+	rtc_update_irq(rtcdrv->rtc, 1, events);
+
+	return IRQ_HANDLED;
+}
+
+static const struct of_device_id sirfsoc_rtc_of_match[] = {
+	{ .compatible = "sirf,prima2-sysrtc"},
+	{},
+};
+MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
+
+static int sirfsoc_rtc_probe(struct platform_device *pdev)
+{
+	int err;
+	unsigned long rtc_div;
+	struct sirfsoc_rtc_drv *rtcdrv;
+	struct device_node *np = pdev->dev.of_node;
+
+	rtcdrv = devm_kzalloc(&pdev->dev,
+		sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
+	if (rtcdrv == NULL) {
+		dev_err(&pdev->dev,
+			"%s: can't alloc mem for drv struct\n",
+			pdev->name);
+		return -ENOMEM;
+	}
+
+	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
+	if (err) {
+		dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
+		goto error;
+	}
+
+	platform_set_drvdata(pdev, rtcdrv);
+
+	/* Register rtc alarm as a wakeup source */
+	device_init_wakeup(&pdev->dev, 1);
+
+	/*
+	 * Set SYS_RTC counter in RTC_HZ HZ Units
+	 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
+	 * If 16HZ, therefore RTC_DIV = 1023;
+	 */
+	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
+	sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
+
+	rtcdrv->rtc = rtc_device_register(pdev->name, &(pdev->dev),
+			&sirfsoc_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtcdrv->rtc)) {
+		err = PTR_ERR(rtcdrv->rtc);
+		dev_err(&pdev->dev, "can't register RTC device\n");
+		return err;
+	}
+
+	/* 0x3 -> RTC_CLK */
+	sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
+			rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
+
+	/* reset SYS RTC ALARM0 */
+	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
+
+	/* reset SYS RTC ALARM1 */
+	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
+
+	/* Restore RTC Overflow From Register After Command Reboot */
+	rtcdrv->overflow_rtc =
+		sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
+
+	rtcdrv->irq = platform_get_irq(pdev, 0);
+	err = devm_request_irq(
+			&pdev->dev,
+			rtcdrv->irq,
+			sirfsoc_rtc_irq_handler,
+			IRQF_SHARED,
+			pdev->name,
+			rtcdrv);
+	if (err) {
+		dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
+		goto error;
+	}
+
+	return 0;
+
+error:
+	if (rtcdrv->rtc)
+		rtc_device_unregister(rtcdrv->rtc);
+
+	return err;
+}
+
+static int sirfsoc_rtc_remove(struct platform_device *pdev)
+{
+	struct sirfsoc_rtc_drv *rtcdrv = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+	rtc_device_unregister(rtcdrv->rtc);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int sirfsoc_rtc_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sirfsoc_rtc_drv *rtcdrv = platform_get_drvdata(pdev);
+	rtcdrv->overflow_rtc =
+		sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
+
+	rtcdrv->saved_counter =
+		sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
+	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(rtcdrv->irq);
+
+	return 0;
+}
+
+static int sirfsoc_rtc_freeze(struct device *dev)
+{
+	sirfsoc_rtc_suspend(dev);
+
+	return 0;
+}
+
+static int sirfsoc_rtc_thaw(struct device *dev)
+{
+	u32 tmp;
+	struct sirfsoc_rtc_drv *rtcdrv;
+	rtcdrv = (struct sirfsoc_rtc_drv *)dev_get_drvdata(dev);
+
+	/*
+	 * if resume from snapshot and the rtc power is losed,
+	 * restroe the rtc settings
+	 */
+	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_iobrg_readl(
+			rtcdrv->rtc_base + RTC_CLOCK_SWITCH)) {
+		u32 rtc_div;
+		/* 0x3 -> RTC_CLK */
+		sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
+			rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
+		/*
+		 * Set SYS_RTC counter in RTC_HZ HZ Units
+		 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
+		 * If 16HZ, therefore RTC_DIV = 1023;
+		 */
+		rtc_div = ((32768 / RTC_HZ) / 2) - 1;
+
+		sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
+
+		/* reset SYS RTC ALARM0 */
+		sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
+
+		/* reset SYS RTC ALARM1 */
+		sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
+	}
+	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
+
+	/*
+	 * if current counter is small than previous,
+	 * it means overflow in sleep
+	 */
+	tmp = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
+	if (tmp <= rtcdrv->saved_counter)
+		rtcdrv->overflow_rtc++;
+	/*
+	 *PWRC Value Be Changed When Suspend, Restore Overflow
+	 * In Memory To Register
+	 */
+	sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
+			rtcdrv->rtc_base + RTC_SW_VALUE);
+
+	return 0;
+}
+
+static int sirfsoc_rtc_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sirfsoc_rtc_drv *rtcdrv = platform_get_drvdata(pdev);
+	sirfsoc_rtc_thaw(dev);
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(rtcdrv->irq);
+
+	return 0;
+}
+
+static int sirfsoc_rtc_restore(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sirfsoc_rtc_drv *rtcdrv = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(rtcdrv->irq);
+	return 0;
+}
+
+#else
+#define sirfsoc_rtc_suspend	NULL
+#define sirfsoc_rtc_resume	NULL
+#define sirfsoc_rtc_freeze	NULL
+#define sirfsoc_rtc_thaw	NULL
+#define sirfsoc_rtc_restore	NULL
+#endif
+
+static const struct dev_pm_ops sirfsoc_rtc_pm_ops = {
+	.suspend = sirfsoc_rtc_suspend,
+	.resume = sirfsoc_rtc_resume,
+	.freeze = sirfsoc_rtc_freeze,
+	.thaw = sirfsoc_rtc_thaw,
+	.restore = sirfsoc_rtc_restore,
+};
+
+static struct platform_driver sirfsoc_rtc_driver = {
+	.driver = {
+		.name = "sirfsoc-rtc",
+		.owner = THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm = &sirfsoc_rtc_pm_ops,
+#endif
+		.of_match_table = of_match_ptr(sirfsoc_rtc_of_match),
+	},
+	.probe = sirfsoc_rtc_probe,
+	.remove = sirfsoc_rtc_remove,
+};
+module_platform_driver(sirfsoc_rtc_driver);
+
+MODULE_DESCRIPTION("SiRF SoC rtc driver");
+MODULE_AUTHOR("Xianglong Du <Xianglong.Du at csr.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:sirfsoc-rtc");
-- 
1.7.4.1



From maxime.ripard at free-electrons.com  Wed May 15 04:53:23 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 15 May 2013 10:53:23 +0200
Subject: [PATCH 2/2] ARM: sun5i: Update the clock compatible strings
In-Reply-To: <517FABBA.5060902@elopez.com.ar>
References: <1367315783-21345-1-git-send-email-maxime.ripard@free-electrons.com>
 <1367315783-21345-3-git-send-email-maxime.ripard@free-electrons.com>
 <517FABBA.5060902@elopez.com.ar>
Message-ID: <51934D03.1090400@free-electrons.com>

Le 30/04/2013 13:32, Emilio L?pez a ?crit :
> Hi Maxime,
> 
> El 30/04/13 06:56, Maxime Ripard escribi?:
>> The Allwinner A13 has a smaller clock set than the one found in the A10.
>> Fix the A13 device tree and documentation to reflect this.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> 
> The patch looks fine to me.
> 
> Acked-by: Emilio L?pez <emilio at elopez.com.ar>

Ok, I just applied it to sunxi/dt-for-3.11

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From linus.walleij at linaro.org  Wed May 15 04:54:09 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 10:54:09 +0200
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <20130514155835.10068.93655@quantum>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
 <20130514155835.10068.93655@quantum>
Message-ID: <CACRpkdZjvQF9e_isiuUgmcH0RgoGGF=dmg_E7oQjs4oY9f+dFQ@mail.gmail.com>

On Tue, May 14, 2013 at 5:58 PM, Mike Turquette <mturquette at linaro.org> wrote:
> Quoting Lee Jones (2013-05-08 06:29:03)
>> First Ethernet device has a ".0" appended onto the device name. It
>> appears that we need this in order to obtain the correct clock.
>>
>> Cc: Ulf Hansson <ulf.hansson at linaro.org>
>> Cc: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>
> Looks good to me.  Can I take this into clk-next or are you looking for
> an Ack?

You can probably take it through the clk tree, but this series
deals with regression fixes so it should go into the -rc series
I think.

Yours,
Linus Walleij


From will.deacon at arm.com  Wed May 15 05:01:03 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 10:01:03 +0100
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <alpine.LFD.2.03.1305141945160.31158@syhkavp.arg>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz>
 <5188B8B2.5030601@arm.com>
 <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
 <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>
 <alpine.LFD.2.03.1305141945160.31158@syhkavp.arg>
Message-ID: <20130515090103.GA12907@mudshark.cambridge.arm.com>

Hi Nico,

On Wed, May 15, 2013 at 12:56:51AM +0100, Nicolas Pitre wrote:
> On Tue, 14 May 2013, Rob Herring wrote:
> > On Tue, May 14, 2013 at 2:54 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > > Waitaminute... Didn't you just claim this would be an ABI break?
> > >
> > > So if no application can be found, where is the ABI breakage?
> > 
> > lscpu
> > 
> > But that is already "broken" on ARM because x86 uses "bogomips" and
> > ARM uses "BogoMIPS". 
> 
> So basically it won't be any more broken if the field disappears 
> entirely, right?

It's not these sort of tools I was worried about. I was thinking about the
possibility of badly written parsers which want some other field from
cpuinfo, but use the bogomips line for context. Do these applications exist?
No idea.

My second (less stupid) version of the patch prints "not reported". I'd be
happy to remove the line altogether if people get behind the decision though.
In fact, I just tried it and at least my linaro filesystem seems happy
enough.

Will


From lee.jones at linaro.org  Wed May 15 05:04:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:04:49 +0100
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130514091956.GG3297@gmail.com>
References: <20130514091956.GG3297@gmail.com>
Message-ID: <20130515090449.GA3494@gmail.com>

Hi Sam,

Since v1 of my MFD -fixes pull-request, I have applied a few more
patches which really should be entered into the -rc:s. As it appears
that you have not yet pulled v1, I figured sending a v2 in its place
would be appropriate, so here it is.

-----

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.linaro.org/people/ljones/mfd.git for-mfd-fixes

for you to fetch changes up to 27df65e061f51f6bd2c8e9ad6b505c8dbab6460c:

  mfd: db8500-prcmu: Update stored DSI PLL divider value (2013-05-14 15:58:04 +0100)

----------------------------------------------------------------
Arnd Bergmann (1):
      mfd: ab8500: Debugfs code depends on gpadc

Fabio Baltieri (5):
      mfd: abx500-core: Fix sparse warning
      mfd: ab8500-sysctrl: Fix sparse warning
      mfd: ab8500-sysctrl: Set sysctrl_dev during probe
      mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
      mfd: ab8500-sysctrl: Always enable pm_power_off handler

Lee Jones (4):
      mfd: ab8500-gpadc: Suppress 'ignoring regulator_enable() return value' warning
      mfd: ab8500-core: Use the correct driver name when enabling gpio/pinctrl
      mfd: db8500-prcmu: Supply the pdata_size attribute for db8500-thermal
      mfd: ab8500-core: Pass GPADC compatible string to MFD core

Linus Walleij (1):
      mfd: ab8500: Pass AB8500 IRQ to debugfs code by resource

Ulf Hansson (1):
      mfd: db8500-prcmu: Update stored DSI PLL divider value

 drivers/mfd/Kconfig               |    2 +-
 drivers/mfd/ab8500-core.c         |   24 +++++++++++++++++++++---
 drivers/mfd/ab8500-debugfs.c      |   16 ++++++++++++----
 drivers/mfd/ab8500-gpadc.c        |    7 +++++--
 drivers/mfd/ab8500-sysctrl.c      |   15 ++++++++++-----
 drivers/mfd/abx500-core.c         |    2 +-
 drivers/mfd/db8500-prcmu.c        |    3 +++
 include/linux/mfd/abx500/ab8500.h |    2 --
 8 files changed, 53 insertions(+), 18 deletions(-)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed May 15 05:07:21 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:07:21 +0100
Subject: [PATCH 3/9] clk: ux500: Provide device enumeration number suffix
 for SMSC911x
In-Reply-To: <CACRpkdZjvQF9e_isiuUgmcH0RgoGGF=dmg_E7oQjs4oY9f+dFQ@mail.gmail.com>
References: <1368019749-19455-1-git-send-email-lee.jones@linaro.org>
 <1368019749-19455-4-git-send-email-lee.jones@linaro.org>
 <20130514155835.10068.93655@quantum>
 <CACRpkdZjvQF9e_isiuUgmcH0RgoGGF=dmg_E7oQjs4oY9f+dFQ@mail.gmail.com>
Message-ID: <20130515090721.GB3494@gmail.com>

On Wed, 15 May 2013, Linus Walleij wrote:

> On Tue, May 14, 2013 at 5:58 PM, Mike Turquette <mturquette at linaro.org> wrote:
> > Quoting Lee Jones (2013-05-08 06:29:03)
> >> First Ethernet device has a ".0" appended onto the device name. It
> >> appears that we need this in order to obtain the correct clock.
> >>
> >> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> >> Cc: Mike Turquette <mturquette at linaro.org>
> >> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >
> > Looks good to me.  Can I take this into clk-next or are you looking for
> > an Ack?
> 
> You can probably take it through the clk tree, but this series
> deals with regression fixes so it should go into the -rc series
> I think.

That's what Mike has done.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Wed May 15 05:12:05 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 10:12:05 +0100
Subject: [RFC PATCH] ARM: SOCFPGA: Enable PMU through the CTI
In-Reply-To: <1368586682-19848-1-git-send-email-dinguyen@altera.com>
References: <1368586682-19848-1-git-send-email-dinguyen@altera.com>
Message-ID: <20130515091205.GB12907@mudshark.cambridge.arm.com>

Hello,

[adding Jon Hunter]

On Wed, May 15, 2013 at 03:58:02AM +0100, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> SOCFPGA has a PMU(Performance Measurement Unit) that has its
> IRQs routed through Coresight using the CTI(Cross-Trigger Interface).
> 
> This patch enables the PMU and initializes the CTI for usage by
> oprofile/perfmon.
> 
> A lot of the code/idea was taken from this:
> https://patchwork.kernel.org/patch/1432541/
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Ming Lei <ming.lei at canonical.com>
> CC: Will Deacon <will.deacon at arm.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> Cc: Pavel Machek <pavel at denx.de>
> ---
>  arch/arm/boot/dts/socfpga.dtsi      |   18 +++++
>  arch/arm/include/asm/pmu.h          |    3 +
>  arch/arm/kernel/perf_event.c        |   16 +++++
>  arch/arm/mach-socfpga/Makefile      |    1 +
>  arch/arm/mach-socfpga/socfpga.c     |   21 +++++-
>  arch/arm/mach-socfpga/socfpga_cti.c |  125 +++++++++++++++++++++++++++++++++++
>  arch/arm/mach-socfpga/socfpga_cti.h |   16 +++++
>  7 files changed, 199 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-socfpga/socfpga_cti.c
>  create mode 100644 arch/arm/mach-socfpga/socfpga_cti.h

Whilst it's great to see somebody else making use of CTI, I think this would
benefit from Jon's separate CTI driver that he posted once:

  http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137156.html

Jon -- would you be interested in reviving that work so the socfpga guys can
make use of it?

> diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
> index f24edad..60324b3 100644
> --- a/arch/arm/include/asm/pmu.h
> +++ b/arch/arm/include/asm/pmu.h
> @@ -38,6 +38,9 @@ struct arm_pmu_platdata {
>  				  irq_handler_t pmu_handler);
>  	int (*runtime_resume)(struct device *dev);
>  	int (*runtime_suspend)(struct device *dev);
> +	int (*init)(struct platform_device *pdev);
> +	int (*start)(struct platform_device *pdev);
> +	int (*stop)(struct platform_device *pdev);

For omap4, we were planning to use the runtime PM callbacks for managing the
CTI iirc.

Will


From laurent.pinchart at ideasonboard.com  Wed May 15 05:15:01 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 11:15:01 +0200
Subject: [PATCH v2 4/4] ARM: shmobile: marzen-reference: Set SMSC lan to
 use irq-push-pull
In-Reply-To: <1368586650-26263-5-git-send-email-horms+renesas@verge.net.au>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
 <1368586650-26263-5-git-send-email-horms+renesas@verge.net.au>
Message-ID: <10371644.BMkVSLAUGy@avalon>

Hi Simon,

Thanks for the patch.

On Wednesday 15 May 2013 11:57:30 Simon Horman wrote:
> This change makes the DTS consistent with the platform data
> that exists in board-marzen.c.
> 
> Empirically it does not appear to be necessary.
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

> ---
>  arch/arm/boot/dts/r8a7779-marzen-reference.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 10cfc7f..fe32e1a
> 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> @@ -40,6 +40,7 @@
>  		phy-mode = "mii";
>  		interrupt-parent = <&irqpin0>;
>  		interrupts = <1 0x4>;
> +		smsc,irq-push-pull;
>  		reg-io-width = <4>;
>  		vddvario-supply = <&fixedregulator3v3>;
>  		vdd33a-supply = <&fixedregulator3v3>;
-- 
Regards,

Laurent Pinchart



From nicolas.ferre at atmel.com  Wed May 15 05:18:45 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 11:18:45 +0200
Subject: [PATCH 0/3 v3] net/macb: RX path enhancement
Message-ID: <cover.1368608928.git.nicolas.ferre@atmel.com>

Here is the patch series for modifying the RX path in macb driver.
This change applies on GEM variant of the Cadence IP and introduces
function pointers to match the path to the proper adapter. The move
to RX buffers adapted to MTU and that can be DMAed directly in SKB
is done in two steps but can be merged in a single patch.

v3: - rebased on top of net-next (containing recently added
      net/macb: fix ISR clear-on-write behavior only for some SoC)
    - added the ___cacheline_aligned_in_smp qualifier to napi field
      following Ben Hutchings' advice

v2: - gave up the idea of using non-coherent memory for
      rx buffers
    - addition of the struct macb layout optimization

Havard Skinnemoen (1):
  net/macb: Try to optimize struct macb layout

Nicolas Ferre (2):
  net/macb: increase RX buffer size for GEM
  net/macb: change RX path for GEM

 drivers/net/ethernet/cadence/macb.c | 323 +++++++++++++++++++++++++++++++-----
 drivers/net/ethernet/cadence/macb.h |  39 +++--
 2 files changed, 308 insertions(+), 54 deletions(-)

-- 
1.8.0



From nicolas.ferre at atmel.com  Wed May 15 05:18:46 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 11:18:46 +0200
Subject: [PATCH 1/3 v3] net/macb: increase RX buffer size for GEM
In-Reply-To: <cover.1368608928.git.nicolas.ferre@atmel.com>
References: <cover.1368608928.git.nicolas.ferre@atmel.com>
Message-ID: <4632e58c379c28ae2c4f3c1bfc2e849a20d8b769.1368608928.git.nicolas.ferre@atmel.com>

Macb Ethernet controller requires a RX buffer of 128 bytes. It is
highly sub-optimal for Gigabit-capable GEM that is able to use
a bigger DMA buffer. Change this constant and associated macros
with data stored in the private structure.
RX DMA buffer size has to be multiple of 64 bytes as indicated in
DMA Configuration Register specification.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/net/ethernet/cadence/macb.c | 45 ++++++++++++++++++++++++++++++-------
 drivers/net/ethernet/cadence/macb.h |  1 +
 2 files changed, 38 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index c89aa41..1d36d2b 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -32,7 +32,9 @@
 
 #include "macb.h"
 
-#define RX_BUFFER_SIZE		128
+#define MACB_RX_BUFFER_SIZE	128
+#define GEM_RX_BUFFER_SIZE	2048
+#define RX_BUFFER_MULTIPLE	64  /* bytes */
 #define RX_RING_SIZE		512 /* must be power of 2 */
 #define RX_RING_BYTES		(sizeof(struct macb_dma_desc) * RX_RING_SIZE)
 
@@ -92,7 +94,7 @@ static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
 
 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
 {
-	return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index);
+	return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
 }
 
 void macb_set_hwaddr(struct macb *bp)
@@ -575,7 +577,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
 	skb_put(skb, len);
 
 	for (frag = first_frag; ; frag++) {
-		unsigned int frag_len = RX_BUFFER_SIZE;
+		unsigned int frag_len = bp->rx_buffer_size;
 
 		if (offset + frag_len > len) {
 			BUG_ON(frag != last_frag);
@@ -583,7 +585,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
 		}
 		skb_copy_to_linear_data_offset(skb, offset,
 				macb_rx_buffer(bp, frag), frag_len);
-		offset += RX_BUFFER_SIZE;
+		offset += bp->rx_buffer_size;
 		desc = macb_rx_desc(bp, frag);
 		desc->addr &= ~MACB_BIT(RX_USED);
 
@@ -870,6 +872,30 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 }
 
+static void macb_init_rx_buffer_size(struct macb *bp)
+{
+	if (!macb_is_gem(bp)) {
+		bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
+	} else {
+		bp->rx_buffer_size = GEM_RX_BUFFER_SIZE;
+
+		if (bp->rx_buffer_size > PAGE_SIZE) {
+			netdev_warn(bp->dev,
+				    "RX buffer cannot be bigger than PAGE_SIZE, shrinking\n");
+			bp->rx_buffer_size = PAGE_SIZE;
+		}
+		if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
+			netdev_warn(bp->dev,
+				    "RX buffer must be multiple of %d bytes, shrinking\n",
+				    RX_BUFFER_MULTIPLE);
+			bp->rx_buffer_size =
+				rounddown(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
+		}
+		bp->rx_buffer_size = max(RX_BUFFER_MULTIPLE, GEM_RX_BUFFER_SIZE);
+	}
+}
+
+
 static void macb_free_consistent(struct macb *bp)
 {
 	if (bp->tx_skb) {
@@ -888,7 +914,7 @@ static void macb_free_consistent(struct macb *bp)
 	}
 	if (bp->rx_buffers) {
 		dma_free_coherent(&bp->pdev->dev,
-				  RX_RING_SIZE * RX_BUFFER_SIZE,
+				  RX_RING_SIZE * bp->rx_buffer_size,
 				  bp->rx_buffers, bp->rx_buffers_dma);
 		bp->rx_buffers = NULL;
 	}
@@ -921,7 +947,7 @@ static int macb_alloc_consistent(struct macb *bp)
 		   "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
 		   size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
 
-	size = RX_RING_SIZE * RX_BUFFER_SIZE;
+	size = RX_RING_SIZE * bp->rx_buffer_size;
 	bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
 					    &bp->rx_buffers_dma, GFP_KERNEL);
 	if (!bp->rx_buffers)
@@ -946,7 +972,7 @@ static void macb_init_rings(struct macb *bp)
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		bp->rx_ring[i].addr = addr;
 		bp->rx_ring[i].ctrl = 0;
-		addr += RX_BUFFER_SIZE;
+		addr += bp->rx_buffer_size;
 	}
 	bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
 
@@ -1056,7 +1082,7 @@ static void macb_configure_dma(struct macb *bp)
 
 	if (macb_is_gem(bp)) {
 		dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
-		dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
+		dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
 		dmacfg |= GEM_BF(FBLDO, 16);
 		dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
 		dmacfg &= ~GEM_BIT(ENDIA);
@@ -1244,6 +1270,9 @@ static int macb_open(struct net_device *dev)
 	if (!bp->phy_dev)
 		return -EAGAIN;
 
+	/* RX buffers initialization */
+	macb_init_rx_buffer_size(bp);
+
 	err = macb_alloc_consistent(bp);
 	if (err) {
 		netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 548c0ec..9b5e19f 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -551,6 +551,7 @@ struct macb {
 	unsigned int		rx_tail;
 	struct macb_dma_desc	*rx_ring;
 	void			*rx_buffers;
+	size_t			rx_buffer_size;
 
 	unsigned int		tx_head, tx_tail;
 	struct macb_dma_desc	*tx_ring;
-- 
1.8.0



From nicolas.ferre at atmel.com  Wed May 15 05:18:47 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 11:18:47 +0200
Subject: [PATCH 2/3 v3] net/macb: change RX path for GEM
In-Reply-To: <cover.1368608928.git.nicolas.ferre@atmel.com>
References: <cover.1368608928.git.nicolas.ferre@atmel.com>
Message-ID: <00f6c153b3714cda31cffe685b024ca81687bcb5.1368608928.git.nicolas.ferre@atmel.com>

GEM is able to adapt its DMA buffer size, so change
the RX path to take advantage of this possibility and
remove all kind of memcpy in this path.
This modification introduces function pointers for managing
differences between MACB and GEM adapter type.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/net/ethernet/cadence/macb.c | 308 ++++++++++++++++++++++++++++++------
 drivers/net/ethernet/cadence/macb.h |  13 ++
 2 files changed, 272 insertions(+), 49 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 1d36d2b..ea31b74 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -33,7 +33,6 @@
 #include "macb.h"
 
 #define MACB_RX_BUFFER_SIZE	128
-#define GEM_RX_BUFFER_SIZE	2048
 #define RX_BUFFER_MULTIPLE	64  /* bytes */
 #define RX_RING_SIZE		512 /* must be power of 2 */
 #define RX_RING_BYTES		(sizeof(struct macb_dma_desc) * RX_RING_SIZE)
@@ -530,6 +529,155 @@ static void macb_tx_interrupt(struct macb *bp)
 		netif_wake_queue(bp->dev);
 }
 
+static void gem_rx_refill(struct macb *bp)
+{
+	unsigned int		entry;
+	struct sk_buff		*skb;
+	struct macb_dma_desc	*desc;
+	dma_addr_t		paddr;
+
+	while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
+		u32 addr, ctrl;
+
+		entry = macb_rx_ring_wrap(bp->rx_prepared_head);
+		desc = &bp->rx_ring[entry];
+
+		/* Make hw descriptor updates visible to CPU */
+		rmb();
+
+		addr = desc->addr;
+		ctrl = desc->ctrl;
+		bp->rx_prepared_head++;
+
+		if ((addr & MACB_BIT(RX_USED)))
+			continue;
+
+		if (bp->rx_skbuff[entry] == NULL) {
+			/* allocate sk_buff for this free entry in ring */
+			skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
+			if (unlikely(skb == NULL)) {
+				netdev_err(bp->dev,
+					   "Unable to allocate sk_buff\n");
+				break;
+			}
+			bp->rx_skbuff[entry] = skb;
+
+			/* now fill corresponding descriptor entry */
+			paddr = dma_map_single(&bp->pdev->dev, skb->data,
+					       bp->rx_buffer_size, DMA_FROM_DEVICE);
+
+			if (entry == RX_RING_SIZE - 1)
+				paddr |= MACB_BIT(RX_WRAP);
+			bp->rx_ring[entry].addr = paddr;
+			bp->rx_ring[entry].ctrl = 0;
+
+			/* properly align Ethernet header */
+			skb_reserve(skb, NET_IP_ALIGN);
+		}
+	}
+
+	/* Make descriptor updates visible to hardware */
+	wmb();
+
+	netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
+		   bp->rx_prepared_head, bp->rx_tail);
+}
+
+/* Mark DMA descriptors from begin up to and not including end as unused */
+static void discard_partial_frame(struct macb *bp, unsigned int begin,
+				  unsigned int end)
+{
+	unsigned int frag;
+
+	for (frag = begin; frag != end; frag++) {
+		struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
+		desc->addr &= ~MACB_BIT(RX_USED);
+	}
+
+	/* Make descriptor updates visible to hardware */
+	wmb();
+
+	/*
+	 * When this happens, the hardware stats registers for
+	 * whatever caused this is updated, so we don't have to record
+	 * anything.
+	 */
+}
+
+static int gem_rx(struct macb *bp, int budget)
+{
+	unsigned int		len;
+	unsigned int		entry;
+	struct sk_buff		*skb;
+	struct macb_dma_desc	*desc;
+	int			count = 0;
+
+	while (count < budget) {
+		u32 addr, ctrl;
+
+		entry = macb_rx_ring_wrap(bp->rx_tail);
+		desc = &bp->rx_ring[entry];
+
+		/* Make hw descriptor updates visible to CPU */
+		rmb();
+
+		addr = desc->addr;
+		ctrl = desc->ctrl;
+
+		if (!(addr & MACB_BIT(RX_USED)))
+			break;
+
+		desc->addr &= ~MACB_BIT(RX_USED);
+		bp->rx_tail++;
+		count++;
+
+		if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
+			netdev_err(bp->dev,
+				   "not whole frame pointed by descriptor\n");
+			bp->stats.rx_dropped++;
+			break;
+		}
+		skb = bp->rx_skbuff[entry];
+		if (unlikely(!skb)) {
+			netdev_err(bp->dev,
+				   "inconsistent Rx descriptor chain\n");
+			bp->stats.rx_dropped++;
+			break;
+		}
+		/* now everything is ready for receiving packet */
+		bp->rx_skbuff[entry] = NULL;
+		len = MACB_BFEXT(RX_FRMLEN, ctrl);
+
+		netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
+
+		skb_put(skb, len);
+		addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
+		dma_unmap_single(&bp->pdev->dev, addr,
+				 len, DMA_FROM_DEVICE);
+
+		skb->protocol = eth_type_trans(skb, bp->dev);
+		skb_checksum_none_assert(skb);
+
+		bp->stats.rx_packets++;
+		bp->stats.rx_bytes += skb->len;
+
+#if defined(DEBUG) && defined(VERBOSE_DEBUG)
+		netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
+			    skb->len, skb->csum);
+		print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
+			       skb->mac_header, 16, true);
+		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
+			       skb->data, 32, true);
+#endif
+
+		netif_receive_skb(skb);
+	}
+
+	gem_rx_refill(bp);
+
+	return count;
+}
+
 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
 			 unsigned int last_frag)
 {
@@ -608,27 +756,6 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
 	return 0;
 }
 
-/* Mark DMA descriptors from begin up to and not including end as unused */
-static void discard_partial_frame(struct macb *bp, unsigned int begin,
-				  unsigned int end)
-{
-	unsigned int frag;
-
-	for (frag = begin; frag != end; frag++) {
-		struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
-		desc->addr &= ~MACB_BIT(RX_USED);
-	}
-
-	/* Make descriptor updates visible to hardware */
-	wmb();
-
-	/*
-	 * When this happens, the hardware stats registers for
-	 * whatever caused this is updated, so we don't have to record
-	 * anything.
-	 */
-}
-
 static int macb_rx(struct macb *bp, int budget)
 {
 	int received = 0;
@@ -689,7 +816,7 @@ static int macb_poll(struct napi_struct *napi, int budget)
 	netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
 		   (unsigned long)status, budget);
 
-	work_done = macb_rx(bp, budget);
+	work_done = bp->macbgem_ops.mog_rx(bp, budget);
 	if (work_done < budget) {
 		napi_complete(napi);
 
@@ -872,29 +999,63 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 }
 
-static void macb_init_rx_buffer_size(struct macb *bp)
+static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
 {
 	if (!macb_is_gem(bp)) {
 		bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
 	} else {
-		bp->rx_buffer_size = GEM_RX_BUFFER_SIZE;
+		bp->rx_buffer_size = size;
 
-		if (bp->rx_buffer_size > PAGE_SIZE) {
-			netdev_warn(bp->dev,
-				    "RX buffer cannot be bigger than PAGE_SIZE, shrinking\n");
-			bp->rx_buffer_size = PAGE_SIZE;
-		}
 		if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
-			netdev_warn(bp->dev,
-				    "RX buffer must be multiple of %d bytes, shrinking\n",
+			netdev_dbg(bp->dev,
+				    "RX buffer must be multiple of %d bytes, expanding\n",
 				    RX_BUFFER_MULTIPLE);
 			bp->rx_buffer_size =
-				rounddown(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
+				roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
 		}
-		bp->rx_buffer_size = max(RX_BUFFER_MULTIPLE, GEM_RX_BUFFER_SIZE);
 	}
+
+	netdev_dbg(bp->dev, "mtu [%d] rx_buffer_size [%d]\n",
+		   bp->dev->mtu, bp->rx_buffer_size);
 }
 
+static void gem_free_rx_buffers(struct macb *bp)
+{
+	struct sk_buff		*skb;
+	struct macb_dma_desc	*desc;
+	dma_addr_t		addr;
+	int i;
+
+	if (!bp->rx_skbuff)
+		return;
+
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		skb = bp->rx_skbuff[i];
+
+		if (skb == NULL)
+			continue;
+
+		desc = &bp->rx_ring[i];
+		addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
+		dma_unmap_single(&bp->pdev->dev, addr, skb->len,
+				 DMA_FROM_DEVICE);
+		dev_kfree_skb_any(skb);
+		skb = NULL;
+	}
+
+	kfree(bp->rx_skbuff);
+	bp->rx_skbuff = NULL;
+}
+
+static void macb_free_rx_buffers(struct macb *bp)
+{
+	if (bp->rx_buffers) {
+		dma_free_coherent(&bp->pdev->dev,
+				  RX_RING_SIZE * bp->rx_buffer_size,
+				  bp->rx_buffers, bp->rx_buffers_dma);
+		bp->rx_buffers = NULL;
+	}
+}
 
 static void macb_free_consistent(struct macb *bp)
 {
@@ -902,6 +1063,7 @@ static void macb_free_consistent(struct macb *bp)
 		kfree(bp->tx_skb);
 		bp->tx_skb = NULL;
 	}
+	bp->macbgem_ops.mog_free_rx_buffers(bp);
 	if (bp->rx_ring) {
 		dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
 				  bp->rx_ring, bp->rx_ring_dma);
@@ -912,12 +1074,37 @@ static void macb_free_consistent(struct macb *bp)
 				  bp->tx_ring, bp->tx_ring_dma);
 		bp->tx_ring = NULL;
 	}
-	if (bp->rx_buffers) {
-		dma_free_coherent(&bp->pdev->dev,
-				  RX_RING_SIZE * bp->rx_buffer_size,
-				  bp->rx_buffers, bp->rx_buffers_dma);
-		bp->rx_buffers = NULL;
-	}
+}
+
+static int gem_alloc_rx_buffers(struct macb *bp)
+{
+	int size;
+
+	size = RX_RING_SIZE * sizeof(struct sk_buff *);
+	bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
+	if (!bp->rx_skbuff)
+		return -ENOMEM;
+	else
+		netdev_dbg(bp->dev,
+			   "Allocated %d RX struct sk_buff entries at %p\n",
+			   RX_RING_SIZE, bp->rx_skbuff);
+	return 0;
+}
+
+static int macb_alloc_rx_buffers(struct macb *bp)
+{
+	int size;
+
+	size = RX_RING_SIZE * bp->rx_buffer_size;
+	bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
+					    &bp->rx_buffers_dma, GFP_KERNEL);
+	if (!bp->rx_buffers)
+		return -ENOMEM;
+	else
+		netdev_dbg(bp->dev,
+			   "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
+			   size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
+	return 0;
 }
 
 static int macb_alloc_consistent(struct macb *bp)
@@ -947,14 +1134,8 @@ static int macb_alloc_consistent(struct macb *bp)
 		   "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
 		   size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
 
-	size = RX_RING_SIZE * bp->rx_buffer_size;
-	bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
-					    &bp->rx_buffers_dma, GFP_KERNEL);
-	if (!bp->rx_buffers)
+	if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
 		goto out_err;
-	netdev_dbg(bp->dev,
-		   "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
-		   size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
 
 	return 0;
 
@@ -963,6 +1144,21 @@ out_err:
 	return -ENOMEM;
 }
 
+static void gem_init_rings(struct macb *bp)
+{
+	int i;
+
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		bp->tx_ring[i].addr = 0;
+		bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+	}
+	bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
+
+	bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
+
+	gem_rx_refill(bp);
+}
+
 static void macb_init_rings(struct macb *bp)
 {
 	int i;
@@ -1259,6 +1455,7 @@ EXPORT_SYMBOL_GPL(macb_set_rx_mode);
 static int macb_open(struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
+	size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
 	int err;
 
 	netdev_dbg(bp->dev, "open\n");
@@ -1271,7 +1468,7 @@ static int macb_open(struct net_device *dev)
 		return -EAGAIN;
 
 	/* RX buffers initialization */
-	macb_init_rx_buffer_size(bp);
+	macb_init_rx_buffer_size(bp, bufsz);
 
 	err = macb_alloc_consistent(bp);
 	if (err) {
@@ -1282,7 +1479,7 @@ static int macb_open(struct net_device *dev)
 
 	napi_enable(&bp->napi);
 
-	macb_init_rings(bp);
+	bp->macbgem_ops.mog_init_rings(bp);
 	macb_init_hw(bp);
 
 	/* schedule a link state check */
@@ -1601,6 +1798,19 @@ static int __init macb_probe(struct platform_device *pdev)
 
 	dev->base_addr = regs->start;
 
+	/* setup appropriated routines according to adapter type */
+	if (macb_is_gem(bp)) {
+		bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
+		bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
+		bp->macbgem_ops.mog_init_rings = gem_init_rings;
+		bp->macbgem_ops.mog_rx = gem_rx;
+	} else {
+		bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
+		bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
+		bp->macbgem_ops.mog_init_rings = macb_init_rings;
+		bp->macbgem_ops.mog_rx = macb_rx;
+	}
+
 	/* Set MII management clock divider */
 	config = macb_mdc_clk_div(bp);
 	config |= macb_dbw(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 9b5e19f..f407615 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -545,11 +545,22 @@ struct gem_stats {
 	u32	rx_udp_checksum_errors;
 };
 
+struct macb;
+
+struct macb_or_gem_ops {
+	int	(*mog_alloc_rx_buffers)(struct macb *bp);
+	void	(*mog_free_rx_buffers)(struct macb *bp);
+	void	(*mog_init_rings)(struct macb *bp);
+	int	(*mog_rx)(struct macb *bp, int budget);
+};
+
 struct macb {
 	void __iomem		*regs;
 
 	unsigned int		rx_tail;
+	unsigned int		rx_prepared_head;
 	struct macb_dma_desc	*rx_ring;
+	struct sk_buff		**rx_skbuff;
 	void			*rx_buffers;
 	size_t			rx_buffer_size;
 
@@ -574,6 +585,8 @@ struct macb {
 	dma_addr_t		tx_ring_dma;
 	dma_addr_t		rx_buffers_dma;
 
+	struct macb_or_gem_ops	macbgem_ops;
+
 	struct mii_bus		*mii_bus;
 	struct phy_device	*phy_dev;
 	unsigned int 		link;
-- 
1.8.0



From nicolas.ferre at atmel.com  Wed May 15 05:18:48 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 11:18:48 +0200
Subject: [PATCH 3/3 v3] net/macb: Try to optimize struct macb layout
In-Reply-To: <cover.1368608928.git.nicolas.ferre@atmel.com>
References: <cover.1368608928.git.nicolas.ferre@atmel.com>
Message-ID: <d0bc206ace3baaf681e111ba07c4d0b576839bb4.1368608928.git.nicolas.ferre@atmel.com>

From: Havard Skinnemoen <havard at skinnemoen.net>

Move TX-related fields to the top of the struct so that they end up on
the same cache line. Move the NAPI struct below that since it is used
from the interrupt handler. This field is also marked as
___cacheline_aligned_in_smp.
RX-related fields go below those.
Function pointers and capability mask are immediately after that as
they are also used in the hot path.

Move the spinlock before regs since they are usually used together.

Signed-off-by: Havard Skinnemoen <havard at skinnemoen.net>
[nicolas.ferre at atmel.com: adapt to newer kernel]
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/net/ethernet/cadence/macb.h | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index f407615..6c8e38a2 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -555,46 +555,47 @@ struct macb_or_gem_ops {
 };
 
 struct macb {
+	spinlock_t		lock;
 	void __iomem		*regs;
 
+	unsigned int		tx_head;
+	unsigned int		tx_tail;
+	struct macb_dma_desc	*tx_ring;
+	struct macb_tx_skb	*tx_skb;
+	dma_addr_t		tx_ring_dma;
+	struct work_struct	tx_error_task;
+
+	struct napi_struct	napi ____cacheline_aligned_in_smp;
+
 	unsigned int		rx_tail;
 	unsigned int		rx_prepared_head;
 	struct macb_dma_desc	*rx_ring;
 	struct sk_buff		**rx_skbuff;
 	void			*rx_buffers;
 	size_t			rx_buffer_size;
+	dma_addr_t		rx_ring_dma;
+	dma_addr_t		rx_buffers_dma;
 
-	unsigned int		tx_head, tx_tail;
-	struct macb_dma_desc	*tx_ring;
-	struct macb_tx_skb	*tx_skb;
+	struct macb_or_gem_ops	macbgem_ops;
+
+	u32			caps;
 
-	spinlock_t		lock;
 	struct platform_device	*pdev;
 	struct clk		*pclk;
 	struct clk		*hclk;
 	struct net_device	*dev;
-	struct napi_struct	napi;
-	struct work_struct	tx_error_task;
 	struct net_device_stats	stats;
 	union {
 		struct macb_stats	macb;
 		struct gem_stats	gem;
 	}			hw_stats;
 
-	dma_addr_t		rx_ring_dma;
-	dma_addr_t		tx_ring_dma;
-	dma_addr_t		rx_buffers_dma;
-
-	struct macb_or_gem_ops	macbgem_ops;
-
 	struct mii_bus		*mii_bus;
 	struct phy_device	*phy_dev;
 	unsigned int 		link;
 	unsigned int 		speed;
 	unsigned int 		duplex;
 
-	u32			caps;
-
 	phy_interface_t		phy_interface;
 
 	/* AT91RM9200 transmit */
-- 
1.8.0



From lee.jones at linaro.org  Wed May 15 05:23:22 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:23:22 +0100
Subject: [PATCH] serial: pl011: protect attribute read from NULL platform
 data struct
In-Reply-To: <CACRpkdZR3AsGyCUH=cbskcZPs0PVBjH6QXUGkD+KG8SzGMMOKg@mail.gmail.com>
References: <1368103855-28363-1-git-send-email-lee.jones@linaro.org>
 <CACRpkdZR3AsGyCUH=cbskcZPs0PVBjH6QXUGkD+KG8SzGMMOKg@mail.gmail.com>
Message-ID: <20130515092322.GC3494@gmail.com>

On Mon, 13 May 2013, Linus Walleij wrote:

> On Thu, May 9, 2013 at 2:50 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > It's completely feasible that platform data will be empty i.e. when
> > booting with Device Tree with no device AUXDATA. So we must protect
> > it's use in these use-cases, or risk a kernel Oops.
> >
> > Cc: Russell King <linux at arm.linux.org.uk>
> > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > Cc: Jiri Slaby <jslaby at suse.cz>
> > Cc: linux-serial at vger.kernel.org
> > Cc: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> > *******                                                        *******
> > If this issue has not already been fixed, this patch should be applied
> > during the v3.10 -rc:s, as it fixes a serious bug which was introduced
> > in the merge-window.
> > *******                                                        *******
> 
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> 
> You should probably put Greg on To: so that he picks this up for
> the -rc:s ASAP.

I spoke with Greg yesterday. He's catching up on mail.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From ard.biesheuvel at linaro.org  Wed May 15 05:27:00 2013
From: ard.biesheuvel at linaro.org (Ard Biesheuvel)
Date: Wed, 15 May 2013 11:27:00 +0200
Subject: [PATCH] ARM: crypto: sha1-armv4-large.S: fix SP handling
Message-ID: <1368610020-29219-1-git-send-email-ard.biesheuvel@linaro.org>

Make the SHA1 asm code ABI conformant by making sure all stack
accesses occur above the stack pointer.

Origin:
http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2

Signed-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
---
 arch/arm/crypto/sha1-armv4-large.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
index 92c6eed..99207c4 100644
--- a/arch/arm/crypto/sha1-armv4-large.S
+++ b/arch/arm/crypto/sha1-armv4-large.S
@@ -195,6 +195,7 @@ ENTRY(sha1_block_data_order)
 	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
 	cmp	r14,sp
 	bne	.L_00_15		@ [((11+4)*5+2)*3]
+	sub	sp,sp,#25*4
 #if __ARM_ARCH__<7
 	ldrb	r10,[r1,#2]
 	ldrb	r9,[r1,#3]
@@ -290,7 +291,6 @@ ENTRY(sha1_block_data_order)
 	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
 
 	ldr	r8,.LK_20_39		@ [+15+16*4]
-	sub	sp,sp,#25*4
 	cmn	sp,#0			@ [+3], clear carry to denote 20_39
 .L_20_39_or_60_79:
 	ldr	r9,[r14,#15*4]
-- 
1.8.1.2



From laurent.pinchart at ideasonboard.com  Wed May 15 05:28:15 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 11:28:15 +0200
Subject: [PATCH v2 3/4] ARM: shmobile: marzen-reference: Initialise irqpin
In-Reply-To: <1368586650-26263-4-git-send-email-horms+renesas@verge.net.au>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
 <1368586650-26263-4-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1482970.xQCySsLs8z@avalon>

Hi Simon,

Thanks for the patch.

On Wednesday 15 May 2013 11:57:29 Simon Horman wrote:
> Empirically it appears to be necessary to call r8a7779_init_irq_extpin(1)
> in order to initialise irqpin for use with IRQ1. This is already done in
> the marzen board code. This adds the call to the marzen-reference board
> code.
> 
> The motivation for this is to allow use of SMSC LAN, which uses IRQ1, with
> marzen-reference.

This is an acceptable workaround for now, but in the not-so-long term we want 
to move that code to the irqpin driver.

I've had a brief look at the irq-renesas-intc-irqpin driver, and it definitely 
looks like some love is needed there. I don't have any free time for that at 
the moment, but I could provide pointers if anyone wants to work on moving 
irqpin-related arch code to the driver.

> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/board-marzen-reference.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> b/arch/arm/mach-shmobile/board-marzen-reference.c index 5332e89..f83b6d1
> 100644
> --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> @@ -63,12 +63,18 @@ static const char *marzen_boards_compat_dt[] __initdata
> = { NULL,
>  };
> 
> +void __init marzen_init_irq(void)
> +{
> +	r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
> +	r8a7779_init_irq_dt();
> +}
> +
>  DT_MACHINE_START(MARZEN, "marzen")
>  	.smp		= smp_ops(r8a7779_smp_ops),
>  	.map_io		= r8a7779_map_io,
>  	.init_early	= r8a7779_init_delay,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= r8a7779_init_irq_dt,
> +	.init_irq	= marzen_init_irq,
>  	.init_machine	= marzen_init,
>  	.init_time	= shmobile_timer_init,
>  	.dt_compat	= marzen_boards_compat_dt,
-- 
Regards,

Laurent Pinchart



From David.Laight at ACULAB.COM  Wed May 15 05:37:22 2013
From: David.Laight at ACULAB.COM (David Laight)
Date: Wed, 15 May 2013 10:37:22 +0100
Subject: [PATCH 3/3 v3] net/macb: Try to optimize struct macb layout
In-Reply-To: <d0bc206ace3baaf681e111ba07c4d0b576839bb4.1368608928.git.nicolas.ferre@atmel.com>
References: <cover.1368608928.git.nicolas.ferre@atmel.com>
 <d0bc206ace3baaf681e111ba07c4d0b576839bb4.1368608928.git.nicolas.ferre@atmel.com>
Message-ID: <AE90C24D6B3A694183C094C60CF0A2F6026B723A@saturn3.aculab.com>

> From: Havard Skinnemoen <havard at skinnemoen.net>

> Move the NAPI struct below that since it is used
> from the interrupt handler. This field is also marked as
> ___cacheline_aligned_in_smp.

Is that a good idea if the cache line size is 256 bytes?
Indeed is that ever sane - except for a few special structures
that really need it, and are guaranteed to be allocated
with that much alignment.

	David





From David.Laight at ACULAB.COM  Wed May 15 05:38:44 2013
From: David.Laight at ACULAB.COM (David Laight)
Date: Wed, 15 May 2013 10:38:44 +0100
Subject: [PATCH 3/3 v3] net/macb: Try to optimize struct macb layout
In-Reply-To: <d0bc206ace3baaf681e111ba07c4d0b576839bb4.1368608928.git.nicolas.ferre@atmel.com>
References: <cover.1368608928.git.nicolas.ferre@atmel.com>
 <d0bc206ace3baaf681e111ba07c4d0b576839bb4.1368608928.git.nicolas.ferre@atmel.com>
Message-ID: <AE90C24D6B3A694183C094C60CF0A2F6026B723B@saturn3.aculab.com>

> Move TX-related fields to the top of the struct so that they end up on
> the same cache line. Move the NAPI struct below that since it is used
> from the interrupt handler. This field is also marked as
> ___cacheline_aligned_in_smp.
> RX-related fields go below those.
> Function pointers and capability mask are immediately after that as
> they are also used in the hot path.
> 
> Move the spinlock before regs since they are usually used together.

Haven't you introduced some holes in the structure?
I suspect that spinloack_t might only be 32bits on
some 64bit systems.
There is certainly one where 'caps' used to be.

...> 
>  struct macb {
> +	spinlock_t		lock;
>  	void __iomem		*regs;
...
> +	struct macb_or_gem_ops	macbgem_ops;
> +
> +	u32			caps;
> 
> -	spinlock_t		lock;
>  	struct platform_device	*pdev;

	David





From ulf.hansson at stericsson.com  Wed May 15 05:40:22 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Wed, 15 May 2013 11:40:22 +0200
Subject: [PATCH 4/4] mmc: mmci: Add card_busy function to improve UHS card
 support
In-Reply-To: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368610823-14113-5-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

To verify a signal voltage switch at initialization of UHS cards the
.card_busy callback is used. For some of the ST-variants, card busy
detection on the DAT0 pin is supported.

We extend the variant struct with a busy_detect flag to indicate
support for it. A corresponding busy detect function, which polls the
busy status bit, is then set to the .card_busy callback.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   33 ++++++++++++++++++++++++++++++++-
 drivers/mmc/host/mmci.h |    2 ++
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4530217..fa1a7d7 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -61,6 +61,7 @@ static unsigned int fmax = 515633;
  * @pwrreg_powerup: power up value for MMCIPOWER register
  * @signal_direction: input/out direction of bus signals can be indicated
  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
+ * @busy_detect: true if busy detection on dat0 is supported
  */
 struct variant_data {
 	unsigned int		clkreg;
@@ -74,6 +75,7 @@ struct variant_data {
 	u32			pwrreg_powerup;
 	bool			signal_direction;
 	bool			pwrreg_clkgate;
+	bool			busy_detect;
 };
 
 static struct variant_data variant_arm = {
@@ -132,6 +134,7 @@ static struct variant_data variant_ux500 = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.busy_detect		= true,
 };
 
 static struct variant_data variant_ux500v2 = {
@@ -146,8 +149,28 @@ static struct variant_data variant_ux500v2 = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.busy_detect		= true,
 };
 
+static int mmci_card_busy(struct mmc_host *mmc)
+{
+	struct mmci_host *host = mmc_priv(mmc);
+	unsigned long flags;
+	int busy = 0;
+
+	pm_runtime_get_sync(mmc_dev(mmc));
+
+	spin_lock_irqsave(&host->lock, flags);
+	if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
+		busy = 1;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	pm_runtime_mark_last_busy(mmc_dev(mmc));
+	pm_runtime_put_autosuspend(mmc_dev(mmc));
+
+	return busy;
+}
+
 /*
  * Validate mmc prerequisites
  */
@@ -193,6 +216,9 @@ static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
  */
 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
 {
+	/* Keep ST Micro busy mode if enabled */
+	datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
+
 	if (host->datactrl_reg != datactrl) {
 		host->datactrl_reg = datactrl;
 		writel(datactrl, host->base + MMCIDATACTRL);
@@ -1306,7 +1332,7 @@ static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static const struct mmc_host_ops mmci_ops = {
+static struct mmc_host_ops mmci_ops = {
 	.request	= mmci_request,
 	.pre_req	= mmci_pre_request,
 	.post_req	= mmci_post_request,
@@ -1443,6 +1469,11 @@ static int mmci_probe(struct amba_device *dev,
 		goto clk_disable;
 	}
 
+	if (variant->busy_detect) {
+		mmci_ops.card_busy = mmci_card_busy;
+		mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
+	}
+
 	mmc->ops = &mmci_ops;
 	/*
 	 * The ARM and ST versions of the block have slightly different
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 0b6cc54..69080fa 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -94,6 +94,7 @@
 /* Extended status bits for the ST Micro variants */
 #define MCI_ST_SDIOIT		(1 << 22)
 #define MCI_ST_CEATAEND		(1 << 23)
+#define MCI_ST_CARDBUSY		(1 << 24)
 
 #define MMCICLEAR		0x038
 #define MCI_CMDCRCFAILCLR	(1 << 0)
@@ -110,6 +111,7 @@
 /* Extended status bits for the ST Micro variants */
 #define MCI_ST_SDIOITC		(1 << 22)
 #define MCI_ST_CEATAENDC	(1 << 23)
+#define MCI_ST_BUSYENDC		(1 << 24)
 
 #define MMCIMASK0		0x03c
 #define MCI_CMDCRCFAILMASK	(1 << 0)
-- 
1.7.10



From ulf.hansson at stericsson.com  Wed May 15 05:40:19 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Wed, 15 May 2013 11:40:19 +0200
Subject: [PATCH 1/4] mmc: mmci: Fixup regulator handling for vqmmc
In-Reply-To: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368610823-14113-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

We can not rely on regulator_is_enabled to decide whether to
enable|disable the regulator. It would mean that the reference
counter for it is not balanced properly.

Instead keep track of our internal state by using a new flag in
the host struct, so we can take correct decisions.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   10 ++++++----
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038..2983c15 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1143,9 +1143,10 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		if (!IS_ERR(mmc->supply.vmmc))
 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 
-		if (!IS_ERR(mmc->supply.vqmmc) &&
-		    regulator_is_enabled(mmc->supply.vqmmc))
+		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
 			regulator_disable(mmc->supply.vqmmc);
+			host->vqmmc_enabled = false;
+		}
 
 		break;
 	case MMC_POWER_UP:
@@ -1161,12 +1162,13 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 		break;
 	case MMC_POWER_ON:
-		if (!IS_ERR(mmc->supply.vqmmc) &&
-		    !regulator_is_enabled(mmc->supply.vqmmc)) {
+		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
 			ret = regulator_enable(mmc->supply.vqmmc);
 			if (ret < 0)
 				dev_err(mmc_dev(mmc),
 					"failed to enable vqmmc regulator\n");
+			else
+				host->vqmmc_enabled = true;
 		}
 
 		pwr |= MCI_PWR_ON;
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 1f33ad5..1383c9c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -183,6 +183,7 @@ struct mmci_host {
 	unsigned int		cclk;
 	u32			pwr_reg;
 	u32			clk_reg;
+	bool			vqmmc_enabled;
 	struct mmci_platform_data *plat;
 	struct variant_data	*variant;
 
-- 
1.7.10



From ulf.hansson at stericsson.com  Wed May 15 05:40:21 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Wed, 15 May 2013 11:40:21 +0200
Subject: [PATCH 3/4] mmc: mmci: Cache MMCIDATACTRL register
In-Reply-To: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368610823-14113-4-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Add a cache variable in the host struct that reflects the current data in
the MMCIDATACTRL register. This patch will not introduce any functional
change but instead provide an easy option to keep specific bits in the
register between each data transfer.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   17 ++++++++++++++---
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 8d4ceb8..4530217 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -191,6 +191,17 @@ static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
 /*
  * This must be called with host->lock held
  */
+static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
+{
+	if (host->datactrl_reg != datactrl) {
+		host->datactrl_reg = datactrl;
+		writel(datactrl, host->base + MMCIDATACTRL);
+	}
+}
+
+/*
+ * This must be called with host->lock held
+ */
 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 {
 	struct variant_data *variant = host->variant;
@@ -275,7 +286,7 @@ static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
 
 static void mmci_stop_data(struct mmci_host *host)
 {
-	writel(0, host->base + MMCIDATACTRL);
+	mmci_write_datactrlreg(host, 0);
 	mmci_set_mask1(host, 0);
 	host->data = NULL;
 }
@@ -552,7 +563,7 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 	datactrl |= MCI_DPSM_DMAENABLE;
 
 	/* Trigger the DMA transfer */
-	writel(datactrl, host->base + MMCIDATACTRL);
+	mmci_write_datactrlreg(host, datactrl);
 
 	/*
 	 * Let the MMCI say when the data is ended and it's time
@@ -750,7 +761,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 		irqmask = MCI_TXFIFOHALFEMPTYMASK;
 	}
 
-	writel(datactrl, base + MMCIDATACTRL);
+	mmci_write_datactrlreg(host, datactrl);
 	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 	mmci_set_mask1(host, irqmask);
 }
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 1383c9c..0b6cc54 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -183,6 +183,7 @@ struct mmci_host {
 	unsigned int		cclk;
 	u32			pwr_reg;
 	u32			clk_reg;
+	u32			datactrl_reg;
 	bool			vqmmc_enabled;
 	struct mmci_platform_data *plat;
 	struct variant_data	*variant;
-- 
1.7.10



From ulf.hansson at stericsson.com  Wed May 15 05:40:18 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Wed, 15 May 2013 11:40:18 +0200
Subject: [PATCH 0/4] mmc: mmci: Add support for UHS cards
Message-ID: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

UHS cards in mode SDR12|25 operates at 1.8V I/O voltage. This patchset
adds support to handle the corresponding voltage switch from the default
2.7-3.6 I/O voltage to 1.8V.

The first patch, "Fixup regulator handling for vqmmc" has recently been
sent as a separate patch, since it is a pure bugfix. Nevertheless this
patchset depends on this patch, thus I decided to fold it here as well.

Host capabilities for SDR12 and SDR25 needs to be set to enable support,
but that will be handled outside this patchset.

Ulf Hansson (4):
  mmc: mmci: Fixup regulator handling for vqmmc
  mmc: mmci: Support signal voltage switch for UHS cards
  mmc: mmci: Cache MMCIDATACTRL register
  mmc: mmci: Add card_busy function to improve UHS card support

 drivers/mmc/host/mmci.c |   94 +++++++++++++++++++++++++++++++++++++++++++----
 drivers/mmc/host/mmci.h |    4 ++
 2 files changed, 90 insertions(+), 8 deletions(-)

-- 
1.7.10



From ulf.hansson at stericsson.com  Wed May 15 05:40:20 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Wed, 15 May 2013 11:40:20 +0200
Subject: [PATCH 2/4] mmc: mmci: Support signal voltage switch for UHS cards
In-Reply-To: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1368610823-14113-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Add .start_signal_voltage_switch callback to be able to support UHS cards.
The voltage switch requires the optional vqmmc regulator to exist since
the actual voltage switch will be performed directly on it.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/mmc/host/mmci.c |   34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 2983c15..8d4ceb8 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1253,6 +1253,39 @@ static int mmci_get_cd(struct mmc_host *mmc)
 	return status;
 }
 
+static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	int ret = 0;
+
+	if (!IS_ERR(mmc->supply.vqmmc)) {
+
+		pm_runtime_get_sync(mmc_dev(mmc));
+
+		switch (ios->signal_voltage) {
+		case MMC_SIGNAL_VOLTAGE_330:
+			ret = regulator_set_voltage(mmc->supply.vqmmc,
+						2700000, 3600000);
+			break;
+		case MMC_SIGNAL_VOLTAGE_180:
+			ret = regulator_set_voltage(mmc->supply.vqmmc,
+						1700000, 1950000);
+			break;
+		case MMC_SIGNAL_VOLTAGE_120:
+			ret = regulator_set_voltage(mmc->supply.vqmmc,
+						1100000, 1300000);
+			break;
+		}
+
+		if (ret)
+			dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
+
+		pm_runtime_mark_last_busy(mmc_dev(mmc));
+		pm_runtime_put_autosuspend(mmc_dev(mmc));
+	}
+
+	return ret;
+}
+
 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
 {
 	struct mmci_host *host = dev_id;
@@ -1269,6 +1302,7 @@ static const struct mmc_host_ops mmci_ops = {
 	.set_ios	= mmci_set_ios,
 	.get_ro		= mmci_get_ro,
 	.get_cd		= mmci_get_cd,
+	.start_signal_voltage_switch = mmci_sig_volt_switch,
 };
 
 #ifdef CONFIG_OF
-- 
1.7.10



From linux at arm.linux.org.uk  Wed May 15 05:37:13 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 May 2013 10:37:13 +0100
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <5193164E.6050400@wwwdotorg.org>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org> <022d01ce5107$8bc668e0$a3533aa0$@lge.com>
 <5193164E.6050400@wwwdotorg.org>
Message-ID: <20130515093713.GJ18614@n2100.arm.linux.org.uk>

On Tue, May 14, 2013 at 10:59:58PM -0600, Stephen Warren wrote:
> Well, that certainly isn't true in practice. I think we should revert
> this commit until we can determine what the problem is.
> 
> I validated that the periphid register in HW contains the r1p5 revision
> (3), and the pcellid register does indeed contain the expected
> 0xb105f00d value. However, if I run the following hacky code in U-Boot
> to determine the FIFO depth, it comes out as 16, which explains the
> symptoms I'm seeing:

We could do that, just like we do in 8250.c to check the FIFO depth.
There's not much harm in doing that at boot time, it just needs to be
done carefully so that it doesn't disrupt any existing use of the UART.


From pavel at denx.de  Wed May 15 05:46:31 2013
From: pavel at denx.de (Pavel Machek)
Date: Wed, 15 May 2013 11:46:31 +0200
Subject: [RFC PATCH] ARM: SOCFPGA: Enable PMU through the CTI
In-Reply-To: <1368586682-19848-1-git-send-email-dinguyen@altera.com>
References: <1368586682-19848-1-git-send-email-dinguyen@altera.com>
Message-ID: <20130515094631.GA5050@amd.pavel.ucw.cz>

Hi!

> SOCFPGA has a PMU(Performance Measurement Unit) that has its
> IRQs routed through Coresight using the CTI(Cross-Trigger Interface).
> 
> This patch enables the PMU and initializes the CTI for usage by
> oprofile/perfmon.
> 
> A lot of the code/idea was taken from this:
> https://patchwork.kernel.org/patch/1432541/

> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -305,6 +305,11 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
>  static void
>  armpmu_release_hardware(struct arm_pmu *armpmu)
>  {
> +	struct platform_device *plat_device = armpmu->plat_device;
> +	struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
> +
...
> @@ -314,6 +319,7 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
>  {
>  	int err;
>  	struct platform_device *pmu_device = armpmu->plat_device;

pmu_device == plat_device, AFAICT. One of them should be renamed for
consistency. Or maybe even make it "pdev" ... shorter and used in the
code below...

> +int socfpga_init_cti(struct platform_device *pdev)
> +{

> +	/*configure CTI0 for pmu irq routing*/

Comments should normally be "/* word */"...

I'll take a more detailed look later.

Thanks,
									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From jamie at jamieiles.com  Wed May 15 05:51:11 2013
From: jamie at jamieiles.com (Jamie Iles)
Date: Wed, 15 May 2013 10:51:11 +0100
Subject: hwrng: picoxcell: PICOXCELL_PC3X3?
In-Reply-To: <1368568977.1350.142.camel@x61.thuisdomein>
References: <1368568977.1350.142.camel@x61.thuisdomein>
Message-ID: <20130515095111.GB16346@page>

Hi Paul,

On Wed, May 15, 2013 at 12:02:57AM +0200, Paul Bolle wrote:
> 0) Support for "Picochip picoXcell true random number generator[s]" was
> added in commit 5efb94ee14 ("hwrng: pixocell - add support for picoxcell
> TRNG"). Its Kconfig symbol (HW_RANDOM_PICOXCELL) depends on
> PICOXCELL_PC3X3. But that symbol is not included in mainline. I found no
> trace of it ever since support for this TRNG got added in v2.6.39. This
> means this code has never been buildable in mainline.
> 
> Why does this code depend on PICOXCELL_PC3X3?

The driver went in before the machine support itself, which got reworked 
for device tree.  There's still some work needed to make the clocks work 
properly so that the driver can use them (they're currently maintained 
out of tree by Mindspeed, Picochip's new owner).

> 1) Slightly related: by what magic are picoxcell-pc7302-pc3x3.dts and
> picoxcell-pc3x3.dtsi hooked into the build system? Or are dts and dtsi
> files, well, special and not directly linked into the build system?

There isn't a defconfig at the moment - I've just done my dts builds 
manually.

Jamie


From lee.jones at linaro.org  Wed May 15 05:51:23 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:23 +0100
Subject: [PATCH 00/39] Continuation of DMA changes in ux500 based drivers
Message-ID: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>

A great deal of these patches have now been applied through various trees.
We now need to grab the attention of the outstanding DMA clients (MUSB and
Crypto) to progress.

Also, Linus could probably do with a hand from Vinod for the remaining
dmaengine patches.

Thanks in advance.

 Documentation/devicetree/bindings/dma/ste-dma40.txt |    4 ++
 Documentation/devicetree/bindings/usb/ux500-usb.txt |   50 ++++++++++++++++++
 arch/arm/mach-ux500/board-mop500-audio.c            |   12 ++---
 arch/arm/mach-ux500/board-mop500-sdi.c              |   16 +++---
 arch/arm/mach-ux500/board-mop500.c                  |   36 +++++--------
 arch/arm/mach-ux500/cpu-db8500.c                    |   34 ++++--------
 arch/arm/mach-ux500/devices-db8500.c                |   80 ----------------------------
 arch/arm/mach-ux500/usb.c                           |   37 +++----------
 drivers/crypto/ux500/cryp/cryp.h                    |    7 ++-
 drivers/crypto/ux500/cryp/cryp_core.c               |   31 ++++++++++-
 drivers/crypto/ux500/hash/hash_alg.h                |    5 +-
 drivers/crypto/ux500/hash/hash_core.c               |   24 ++++++++-
 drivers/dma/ste_dma40.c                             |  292 +++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------
 drivers/dma/ste_dma40_ll.c                          |  189 +++++++++++++++++++++++++++++++++--------------------------------
 drivers/dma/ste_dma40_ll.h                          |    3 +-
 drivers/usb/musb/ux500.c                            |   61 ++++++++++++++++++++-
 drivers/usb/musb/ux500_dma.c                        |   59 ++++++++++++---------
 include/linux/platform_data/dma-ste-dma40.h         |   25 ++-------
 include/linux/platform_data/usb-musb-ux500.h        |    5 +-
 sound/soc/ux500/ux500_pcm.c                         |   10 ++--
 20 files changed, 506 insertions(+), 474 deletions(-)



From lee.jones at linaro.org  Wed May 15 05:51:24 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:24 +0100
Subject: [PATCH 01/39] dmaengine: ste_dma40: Separate Logical Global Interrupt
 Mask (GIM) unmasking
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-2-git-send-email-lee.jones@linaro.org>

During the initial setup of a logical channel, it is necessary to unmask
the GIM in order to receive generated terminal count and error interrupts.
We're separating out this required code so it will be possible to move
the remaining code in d40_phy_cfg(), which is mostly runtime configuration
into the runtime_config() routine.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c    |    4 ++++
 drivers/dma/ste_dma40_ll.c |    5 -----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 5e9f6d6..759293e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2513,6 +2513,10 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 			d40c->lcpa = d40c->base->lcpa_base +
 				d40c->dma_cfg.dev_type *
 				D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
+
+		/* Unmask the Global Interrupt Mask. */
+		d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
+		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
 	}
 
 	dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 5eb6c10..435a223 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -107,11 +107,6 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 			src |= 1 << D40_SREG_CFG_PRI_POS;
 			dst |= 1 << D40_SREG_CFG_PRI_POS;
 		}
-
-	} else {
-		/* Logical channel */
-		dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
-		src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
 	}
 
 	if (cfg->src_info.big_endian)
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:25 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:25 +0100
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-3-git-send-email-lee.jones@linaro.org>

All configuration left in d40_phy_cfg() is runtime configurable and
there is already a call into it from d40_runtime_config(), so let's
rely on that.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c    |   14 +++---
 drivers/dma/ste_dma40_ll.c |  101 +++++++++++++++++++++-----------------------
 drivers/dma/ste_dma40_ll.h |    3 +-
 3 files changed, 58 insertions(+), 60 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 759293e..b7fe46b 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2043,6 +2043,14 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
 		d40c->dma_cfg = dma40_memcpy_conf_phy;
+
+		/* Generate interrrupt at end of transfer or relink. */
+		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
+
+		/* Generate interrupt on error. */
+		d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
+		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
+
 	} else {
 		chan_err(d40c, "No memcpy\n");
 		return -EINVAL;
@@ -2496,9 +2504,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	pm_runtime_get_sync(d40c->base->dev);
-	/* Fill in basic CFG register values */
-	d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
-		    &d40c->dst_def_cfg, chan_is_logical(d40c));
 
 	d40_set_prio_realtime(d40c);
 
@@ -2862,8 +2867,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	if (chan_is_logical(d40c))
 		d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
 	else
-		d40_phy_cfg(cfg, &d40c->src_def_cfg,
-			    &d40c->dst_def_cfg, false);
+		d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
 
 	/* These settings will take precedence later */
 	d40c->runtime_addr = config_addr;
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 435a223..ab5a2a7 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -50,63 +50,58 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 
 }
 
-/* Sets up SRC and DST CFG register for both logical and physical channels */
-void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
-		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
+void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 {
 	u32 src = 0;
 	u32 dst = 0;
 
-	if (!is_log) {
-		/* Physical channel */
-		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
-		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
-			/* Set master port to 1 */
-			src |= 1 << D40_SREG_CFG_MST_POS;
-			src |= D40_TYPE_TO_EVENT(cfg->dev_type);
-
-			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
-			else
-				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
-		}
-		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
-		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
-			/* Set master port to 1 */
-			dst |= 1 << D40_SREG_CFG_MST_POS;
-			dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
-
-			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
-			else
-				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
-		}
-		/* Interrupt on end of transfer for destination */
-		dst |= 1 << D40_SREG_CFG_TIM_POS;
-
-		/* Generate interrupt on error */
-		src |= 1 << D40_SREG_CFG_EIM_POS;
-		dst |= 1 << D40_SREG_CFG_EIM_POS;
-
-		/* PSIZE */
-		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
-			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
-			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
-		}
-		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
-			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
-			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
-		}
-
-		/* Element size */
-		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
-		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
-
-		/* Set the priority bit to high for the physical channel */
-		if (cfg->high_priority) {
-			src |= 1 << D40_SREG_CFG_PRI_POS;
-			dst |= 1 << D40_SREG_CFG_PRI_POS;
-		}
+	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
+	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+		/* Set master port to 1 */
+		src |= 1 << D40_SREG_CFG_MST_POS;
+		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
+
+		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
+			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
+		else
+			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
+	}
+	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
+	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+		/* Set master port to 1 */
+		dst |= 1 << D40_SREG_CFG_MST_POS;
+		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
+
+		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
+			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
+		else
+			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
+	}
+	/* Interrupt on end of transfer for destination */
+	dst |= 1 << D40_SREG_CFG_TIM_POS;
+
+	/* Generate interrupt on error */
+	src |= 1 << D40_SREG_CFG_EIM_POS;
+	dst |= 1 << D40_SREG_CFG_EIM_POS;
+
+	/* PSIZE */
+	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
+		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
+	}
+	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
+		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
+	}
+
+	/* Element size */
+	src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
+	dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
+
+	/* Set the priority bit to high for the physical channel */
+	if (cfg->high_priority) {
+		src |= 1 << D40_SREG_CFG_PRI_POS;
+		dst |= 1 << D40_SREG_CFG_PRI_POS;
 	}
 
 	if (cfg->src_info.big_endian)
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index fdde8ef..1b47312 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -432,8 +432,7 @@ enum d40_lli_flags {
 
 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 		 u32 *src_cfg,
-		 u32 *dst_cfg,
-		 bool is_log);
+		 u32 *dst_cfg);
 
 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 		 u32 *lcsp1,
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:27 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:27 +0100
Subject: [PATCH 04/39] ARM: ux500: Stop passing UART's platform data for
 Device Tree boots
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-5-git-send-email-lee.jones@linaro.org>

It was required to pass DMA channel configuration information to the
UART driver before the new DMA API was in place. Now that it is, and
is fully compatible with Device Tree we can stop doing that.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 38ebf2b..9b26fe2 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -230,9 +230,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 	/* Requires DMA bindings. */
-	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
-	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
-	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:26 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:26 +0100
Subject: [PATCH 03/39] dmaengine: ste_dma40: Don't configure runtime
 configurable setup during allocate
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-4-git-send-email-lee.jones@linaro.org>

Using the dmaengine API, allocating and configuring a channel are two
separate actions. Here we're removing logical channel configuration from
the channel allocating routines.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b7fe46b..ba84df8 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2040,6 +2040,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
 		d40c->dma_cfg = dma40_memcpy_conf_log;
 		d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
 
+		d40_log_cfg(&d40c->dma_cfg,
+			    &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
+
 	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
 		   dma_has_cap(DMA_SLAVE, cap)) {
 		d40c->dma_cfg = dma40_memcpy_conf_phy;
@@ -2508,9 +2511,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	d40_set_prio_realtime(d40c);
 
 	if (chan_is_logical(d40c)) {
-		d40_log_cfg(&d40c->dma_cfg,
-			    &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
-
 		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
 			d40c->lcpa = d40c->base->lcpa_base +
 				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:28 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:28 +0100
Subject: [PATCH 05/39] ARM: ux500: Stop passing MMC's platform data for Device
 Tree boots
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-6-git-send-email-lee.jones@linaro.org>

It was required to pass DMA channel configuration information to the
MMC driver before the new DMA API was in place. Now that it is, and
is fully compatible with Device Tree we can stop doing that.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 9b26fe2..96ddbae 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -234,10 +234,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
 	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  NULL),
 	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:34 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:34 +0100
Subject: [PATCH 11/39] ARM: ux500: Remove unnecessary attributes from DMA
 channel request pdata
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-12-git-send-email-lee.jones@linaro.org>

DMA data width and packet size information is only required at channel
configuration time. Any information passed from platform data is passed
directly to the DMA40 driver to use during channel allocation, but these
pieces of information are subsequently ignored by the driver, so we may
as well remove them.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 45af303..72754e3 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,19 +15,11 @@
 #define MUSB_DMA40_RX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_PERIPH_TO_MEM, \
-		.src_info.data_width = STEDMA40_WORD_WIDTH, \
-		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
-		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
 	}
 
 #define MUSB_DMA40_TX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
 		.dir = STEDMA40_MEM_TO_PERIPH, \
-		.src_info.data_width = STEDMA40_WORD_WIDTH, \
-		.dst_info.data_width = STEDMA40_WORD_WIDTH, \
-		.src_info.psize = STEDMA40_PSIZE_LOG_16, \
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
 	}
 
 static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:29 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:29 +0100
Subject: [PATCH 06/39] ARM: ux500: Move SDI (MMC) and UART devices under more
 descriptive heading
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-7-git-send-email-lee.jones@linaro.org>

Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
should be possible to remove them from the auxdata structure. However,
after doing so the drivers fail. Common clk is still reliant on the
dev_name() call to do device name matching, which will fail due to the
fact that Device Tree naming differs somewhat do the more traditional
conventions.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 96ddbae..b1c9241 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -230,15 +230,15 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 	/* Requires DMA bindings. */
+	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
 	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
 	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
-	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  NULL),
-	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:33 +0100
Subject: [PATCH 10/39] dmaengine: ste_dma40: Correct copy/paste error
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-11-git-send-email-lee.jones@linaro.org>

'struct stedma40_half_channel_info's header comment says that it's
called 'struct stedma40_chan_cfg'. Let's straighten that out.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/platform_data/dma-ste-dma40.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index af0064e..288dc24 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
 
 
 /**
- * struct stedma40_chan_cfg - dst/src channel configuration
+ * struct stedma40_half_channel_info - dst/src channel configuration
  *
  * @big_endian: true if the src/dst should be read as big endian
  * @data_width: Data width of the src/dst hardware
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:31 +0100
Subject: [PATCH 08/39] dmaengine: ste_dma40: Remove redundant address fetching
 function
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-9-git-send-email-lee.jones@linaro.org>

Addresses are now stored in local data structures and are easy to
obtain, thus a specialist function used to fetch them is now surplus
to requirement.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 57a127e..6ed7757 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2267,24 +2267,6 @@ err:
 	return NULL;
 }
 
-static dma_addr_t
-d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
-{
-	struct stedma40_platform_data *plat = chan->base->plat_data;
-	struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
-	dma_addr_t addr = 0;
-
-	if (chan->runtime_addr)
-		return chan->runtime_addr;
-
-	if (direction == DMA_DEV_TO_MEM)
-		addr = plat->dev_rx[cfg->dev_type];
-	else if (direction == DMA_MEM_TO_DEV)
-		addr = plat->dev_tx[cfg->dev_type];
-
-	return addr;
-}
-
 static struct dma_async_tx_descriptor *
 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
 	    struct scatterlist *sg_dst, unsigned int sg_len,
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:32 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:32 +0100
Subject: [PATCH 09/39] ARM: ux500: Remove DMA address look-up table
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-10-git-send-email-lee.jones@linaro.org>

DMA addresses are now passed as part of the dmaengine API by invoking
dmaengine_slave_config(). So there's no requirement for the DMA40
driver to look them up in a table provided by platform data. This
method does not fit in well using Device Tree either.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/devices-db8500.c        |   80 ---------------------------
 include/linux/platform_data/dma-ste-dma40.h |    2 -
 2 files changed, 82 deletions(-)

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index bed25a3..e21ffd8 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,87 +42,7 @@ static struct resource dma40_resources[] = {
 	}
 };
 
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
-	/* PrimeCells - run-time configured */
-	[DB8500_DMA_DEV0_SPI0] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2] = -1,
-	[DB8500_DMA_DEV8_SSP0] = -1,
-	[DB8500_DMA_DEV9_SSP1] = -1,
-	[DB8500_DMA_DEV11_UART2] = -1,
-	[DB8500_DMA_DEV12_UART1] = -1,
-	[DB8500_DMA_DEV13_UART0] = -1,
-	[DB8500_DMA_DEV28_SD_MM2] = -1,
-	[DB8500_DMA_DEV29_SD_MM0] = -1,
-	[DB8500_DMA_DEV32_SD_MM1] = -1,
-	[DB8500_DMA_DEV33_SPI2] = -1,
-	[DB8500_DMA_DEV35_SPI1] = -1,
-	[DB8500_DMA_DEV40_SPI3] = -1,
-	[DB8500_DMA_DEV41_SD_MM3] = -1,
-	[DB8500_DMA_DEV42_SD_MM4] = -1,
-	[DB8500_DMA_DEV43_SD_MM5] = -1,
-	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-	[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
-	/* PrimeCells */
-	[DB8500_DMA_DEV0_SPI0] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2] = -1,
-	[DB8500_DMA_DEV8_SSP0] = -1,
-	[DB8500_DMA_DEV9_SSP1] = -1,
-	[DB8500_DMA_DEV11_UART2] = -1,
-	[DB8500_DMA_DEV12_UART1] = -1,
-	[DB8500_DMA_DEV13_UART0] = -1,
-	[DB8500_DMA_DEV28_SD_MM2] = -1,
-	[DB8500_DMA_DEV29_SD_MM0] = -1,
-	[DB8500_DMA_DEV32_SD_MM1] = -1,
-	[DB8500_DMA_DEV33_SPI2] = -1,
-	[DB8500_DMA_DEV35_SPI1] = -1,
-	[DB8500_DMA_DEV40_SPI3] = -1,
-	[DB8500_DMA_DEV41_SD_MM3] = -1,
-	[DB8500_DMA_DEV42_SD_MM4] = -1,
-	[DB8500_DMA_DEV43_SD_MM5] = -1,
-	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
 struct stedma40_platform_data dma40_plat_data = {
-	.dev_rx = dma40_rx_map,
-	.dev_tx = dma40_tx_map,
 	.disabled_channels = {-1},
 };
 
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index c54af61..af0064e 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -152,8 +152,6 @@ struct stedma40_chan_cfg {
  * for 'multiple of 4' channels, like 8.
  */
 struct stedma40_platform_data {
-	const dma_addr_t		*dev_tx;
-	const dma_addr_t		*dev_rx;
 	int				 disabled_channels[STEDMA40_MAX_PHYS];
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:30 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:30 +0100
Subject: [PATCH 07/39] dmaengine: ste_dma40: Only use addresses passed as
 configuration information
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-8-git-send-email-lee.jones@linaro.org>

Addresses are passed in from the client's driver via the invocation of
dmaengine_slave_config(), so there's no need to fetch them from platform
data too, hardwired or otherwise. This is a great step forward, as it
elevates a large burden from platform data in the way of a look-up
table.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   51 ++++++++++-------------------------------------
 1 file changed, 11 insertions(+), 40 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index ba84df8..57a127e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1774,22 +1774,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
 		res = -EINVAL;
 	}
 
-	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
-	    d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid TX channel address (%d)\n",
-			 conf->dev_type);
-		res = -EINVAL;
-	}
-
-	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
-	    d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
-	    d40c->runtime_addr == 0) {
-		chan_err(d40c, "Invalid RX channel address (%d)\n",
-			 conf->dev_type);
-		res = -EINVAL;
-	}
-
 	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
 		/*
 		 * DMAC HW supports it. Will be added to this driver,
@@ -2327,14 +2311,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
 	if (sg_next(&sg_src[sg_len - 1]) == sg_src)
 		desc->cyclic = true;
 
-	if (direction != DMA_TRANS_NONE) {
-		dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
-
-		if (direction == DMA_DEV_TO_MEM)
-			src_dev_addr = dev_addr;
-		else if (direction == DMA_MEM_TO_DEV)
-			dst_dev_addr = dev_addr;
-	}
+	if (direction == DMA_DEV_TO_MEM)
+		src_dev_addr = chan->runtime_addr;
+	else if (direction == DMA_MEM_TO_DEV)
+		dst_dev_addr = chan->runtime_addr;
 
 	if (chan_is_logical(chan))
 		ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
@@ -2782,15 +2762,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	dst_maxburst = config->dst_maxburst;
 
 	if (config->direction == DMA_DEV_TO_MEM) {
-		dma_addr_t dev_addr_rx =
-			d40c->base->plat_data->dev_rx[cfg->dev_type];
-
 		config_addr = config->src_addr;
-		if (dev_addr_rx)
-			dev_dbg(d40c->base->dev,
-				"channel has a pre-wired RX address %08x "
-				"overriding with %08x\n",
-				dev_addr_rx, config_addr);
+
 		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for peripheral "
@@ -2805,15 +2778,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 			dst_maxburst = src_maxburst;
 
 	} else if (config->direction == DMA_MEM_TO_DEV) {
-		dma_addr_t dev_addr_tx =
-			d40c->base->plat_data->dev_tx[cfg->dev_type];
-
 		config_addr = config->dst_addr;
-		if (dev_addr_tx)
-			dev_dbg(d40c->base->dev,
-				"channel has a pre-wired TX address %08x "
-				"overriding with %08x\n",
-				dev_addr_tx, config_addr);
+
 		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for memory "
@@ -2833,6 +2799,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 		return -EINVAL;
 	}
 
+	if (config_addr <= 0) {
+		dev_err(d40c->base->dev, "no address supplied\n");
+		return -EINVAL;
+	}
+
 	if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
 		dev_err(d40c->base->dev,
 			"src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:41 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:41 +0100
Subject: [PATCH 18/39] crypto: ux500/[cryp|hash] - Show successful start-up in
 the bootlog
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-19-git-send-email-lee.jones@linaro.org>

The Cryp driver is currently silent and the Hash driver prints the
name of its probe function unnecessarily. Let's just put a nice
descriptive one-liner there instead.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |    2 ++
 drivers/crypto/ux500/hash/hash_core.c |    2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index d9c863d..4f8b11a 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1541,6 +1541,8 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_power;
 	}
 
+	dev_info(dev, "successfully registered\n");
+
 	return 0;
 
 out_power:
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 6269576..9ca6fbb 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1772,7 +1772,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_power;
 	}
 
-	dev_info(dev, "[%s] successfully probed\n", __func__);
+	dev_info(dev, "successfully registered\n");
 	return 0;
 
 out_power:
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:42 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:42 +0100
Subject: [PATCH 19/39] ARM: ux500: Register Cyrp and Hash platform drivers on
 Snowball
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-20-git-send-email-lee.jones@linaro.org>

These drivers are now operational and even use the latest common clk
and DMA APIs. There's no reason why we shouldn't start them up now.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 38e321c..ba26ae3 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -637,6 +637,8 @@ static void __init snowball_init_machine(void)
 
 	mop500_snowball_ethernet_clock_enable();
 
+	u8500_cryp1_hash1_init(parent);
+
 	/* This board has full regulator constraints */
 	regulator_has_full_constraints();
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:44 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:44 +0100
Subject: [PATCH 21/39] usb: musb: ux500: move the MUSB HDRC configuration into
 the driver
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-22-git-send-email-lee.jones@linaro.org>

The MUSB HDRC configuration never changes between each of the ux500
supported platforms, so there's little point passing it though platform
data. If we set it in the driver instead, we can make good use of it
when booting with either ATAGs or Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    8 --------
 drivers/usb/musb/ux500.c  |    8 ++++++++
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index a21c2e1..49d6e57 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -76,16 +76,8 @@ static struct ux500_musb_board_data musb_board_data = {
 
 static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
 
-static struct musb_hdrc_config musb_hdrc_config = {
-	.multipoint	= true,
-	.dyn_fifo	= true,
-	.num_eps	= 16,
-	.ram_bits	= 16,
-};
-
 static struct musb_hdrc_platform_data musb_platform_data = {
 	.mode = MUSB_OTG,
-	.config = &musb_hdrc_config,
 	.board_data = &musb_board_data,
 };
 
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 2c80004..371776f 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -30,6 +30,13 @@
 
 #include "musb_core.h"
 
+static struct musb_hdrc_config ux500_musb_hdrc_config = {
+	.multipoint	= true,
+	.dyn_fifo	= true,
+	.num_eps	= 16,
+	.ram_bits	= 16,
+};
+
 struct ux500_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
@@ -229,6 +236,7 @@ static int ux500_probe(struct platform_device *pdev)
 	glue->clk			= clk;
 
 	pdata->platform_ops		= &ux500_ops;
+	pdata->config 			= &ux500_musb_hdrc_config;
 
 	platform_set_drvdata(pdev, glue);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:39 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:39 +0100
Subject: [PATCH 16/39] crypto: ux500/cryp - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-17-git-send-email-lee.jones@linaro.org>

The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp.h      |    7 ++++++-
 drivers/crypto/ux500/cryp/cryp_core.c |   17 +++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp.h b/drivers/crypto/ux500/cryp/cryp.h
index 14cfd05..d1d6606 100644
--- a/drivers/crypto/ux500/cryp/cryp.h
+++ b/drivers/crypto/ux500/cryp/cryp.h
@@ -114,6 +114,9 @@ enum cryp_status_id {
 };
 
 /* Cryp DMA interface */
+#define CRYP_DMA_TX_FIFO	0x08
+#define CRYP_DMA_RX_FIFO	0x10
+
 enum cryp_dma_req_type {
 	CRYP_DMA_DISABLE_BOTH,
 	CRYP_DMA_ENABLE_IN_DATA,
@@ -217,7 +220,8 @@ struct cryp_dma {
 
 /**
  * struct cryp_device_data - structure for a cryp device.
- * @base: Pointer to the hardware base address.
+ * @base: Pointer to virtual base address of the cryp device.
+ * @phybase: Pointer to physical memory location of the cryp device.
  * @dev: Pointer to the devices dev structure.
  * @clk: Pointer to the device's clock control.
  * @pwr_regulator: Pointer to the device's power control.
@@ -232,6 +236,7 @@ struct cryp_dma {
  */
 struct cryp_device_data {
 	struct cryp_register __iomem *base;
+	phys_addr_t phybase;
 	struct device *dev;
 	struct clk *clk;
 	struct regulator *pwr_regulator;
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index ccdf173..d9c863d 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -475,6 +475,19 @@ static int cryp_get_device_data(struct cryp_ctx *ctx,
 static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
 				   struct device *dev)
 {
+	struct dma_slave_config mem2cryp = {
+		.direction = DMA_MEM_TO_DEV,
+		.dst_addr = device_data->phybase + CRYP_DMA_TX_FIFO,
+		.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.dst_maxburst = 4,
+        };
+	struct dma_slave_config cryp2mem = {
+		.direction = DMA_DEV_TO_MEM,
+		.src_addr = device_data->phybase + CRYP_DMA_RX_FIFO,
+		.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.src_maxburst = 4,
+        };
+
 	dma_cap_zero(device_data->dma.mask);
 	dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 
@@ -490,6 +503,9 @@ static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
 				    stedma40_filter,
 				    device_data->dma.cfg_cryp2mem);
 
+	dmaengine_slave_config(device_data->dma.chan_mem2cryp, &mem2cryp);
+	dmaengine_slave_config(device_data->dma.chan_cryp2mem, &cryp2mem);
+
 	init_completion(&device_data->dma.cryp_dma_complete);
 }
 
@@ -1431,6 +1447,7 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_kfree;
 	}
 
+	device_data->phybase = res->start;
 	device_data->base = ioremap(res->start, resource_size(res));
 	if (!device_data->base) {
 		dev_err(dev, "[%s]: ioremap failed!", __func__);
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:35 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:35 +0100
Subject: [PATCH 12/39] crypto: ux500/hash - Prepare clock before enabling it
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-13-git-send-email-lee.jones@linaro.org>

If we fail to prepare the ux500-hash clock before enabling it the
platform will fail to boot. Here we insure this happens.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_core.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index cf55089..4b02428 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1726,11 +1726,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_regulator;
 	}
 
+	ret = clk_prepare(device_data->clk);
+	if (ret) {
+		dev_err(dev, "[%s] clk_prepare() failed!", __func__);
+		goto out_clk;
+	}
+
 	/* Enable device power (and clock) */
 	ret = hash_enable_power(device_data, false);
 	if (ret) {
 		dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
-		goto out_clk;
+		goto out_clk_unprepare;
 	}
 
 	ret = hash_check_hw(device_data);
@@ -1762,6 +1768,9 @@ static int ux500_hash_probe(struct platform_device *pdev)
 out_power:
 	hash_disable_power(device_data, false);
 
+out_clk_unprepare:
+	clk_unprepare(device_data->clk);
+
 out_clk:
 	clk_put(device_data->clk);
 
@@ -1826,6 +1835,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
 		dev_err(dev, "[%s]: hash_disable_power() failed",
 			__func__);
 
+	clk_unprepare(device_data->clk);
 	clk_put(device_data->clk);
 	regulator_put(device_data->regulator);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:37 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:37 +0100
Subject: [PATCH 14/39] ARM: ux500: Stop passing Hash DMA channel config
 information though pdata
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-15-git-send-email-lee.jones@linaro.org>

DMA channel configuration information should be setup in the driver.
The Ux500 Hash driver now does this, so there's no need to send it
though here too.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 52ffe1c..ec916ca 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -446,11 +446,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
 		.dir = STEDMA40_MEM_TO_PERIPH,
 		.dev_type = DB8500_DMA_DEV50_HAC1_TX,
-		.src_info.data_width = STEDMA40_WORD_WIDTH,
-		.dst_info.data_width = STEDMA40_WORD_WIDTH,
 		.mode = STEDMA40_MODE_LOGICAL,
-		.src_info.psize = STEDMA40_PSIZE_LOG_16,
-		.dst_info.psize = STEDMA40_PSIZE_LOG_16,
 };
 
 static struct hash_platform_data u8500_hash1_platform_data = {
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:36 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:36 +0100
Subject: [PATCH 13/39] crypto: ux500/hash - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-14-git-send-email-lee.jones@linaro.org>

The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_alg.h  |    5 ++++-
 drivers/crypto/ux500/hash/hash_core.c |   10 ++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index cd9351c..be6eb54 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -11,6 +11,7 @@
 #include <linux/bitops.h>
 
 #define HASH_BLOCK_SIZE			64
+#define HASH_DMA_FIFO			4
 #define HASH_DMA_ALIGN_SIZE		4
 #define HASH_DMA_PERFORMANCE_MIN_SIZE	1024
 #define HASH_BYTES_PER_WORD		4
@@ -347,7 +348,8 @@ struct hash_req_ctx {
 
 /**
  * struct hash_device_data - structure for a hash device.
- * @base:		Pointer to the hardware base address.
+ * @base:		Pointer to virtual base address of the hash device.
+ * @phybase:		Pointer to physical memory location of the hash device.
  * @list_node:		For inclusion in klist.
  * @dev:		Pointer to the device dev structure.
  * @ctx_lock:		Spinlock for current_ctx.
@@ -361,6 +363,7 @@ struct hash_req_ctx {
  */
 struct hash_device_data {
 	struct hash_register __iomem	*base;
+	phys_addr_t             phybase;
 	struct klist_node	list_node;
 	struct device		*dev;
 	struct spinlock		ctx_lock;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 4b02428..6269576 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -122,6 +122,13 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				struct device *dev)
 {
 	struct hash_platform_data *platform_data = dev->platform_data;
+	struct dma_slave_config conf = {
+		.direction = DMA_MEM_TO_DEV,
+		.dst_addr = device_data->phybase + HASH_DMA_FIFO,
+		.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+		.dst_maxburst = 16,
+        };
+
 	dma_cap_zero(device_data->dma.mask);
 	dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 
@@ -131,6 +138,8 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				platform_data->dma_filter,
 				device_data->dma.cfg_mem2hash);
 
+	dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
+
 	init_completion(&device_data->dma.complete);
 }
 
@@ -1699,6 +1708,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out_kfree;
 	}
 
+	device_data->phybase = res->start;
 	device_data->base = ioremap(res->start, resource_size(res));
 	if (!device_data->base) {
 		dev_err(dev, "[%s] ioremap() failed!",
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:38 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:38 +0100
Subject: [PATCH 15/39] crypto: ux500/cryp - Prepare clock before enabling it
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-16-git-send-email-lee.jones@linaro.org>

If we fail to prepare the ux500-cryp clock before enabling it the
platform will fail to boot. Here we insure this happens.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: David S. Miller <davem at davemloft.net>
Cc: Andreas Westin <andreas.westin at stericsson.com>
Cc: linux-crypto at vger.kernel.org
Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 32f4806..ccdf173 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1458,11 +1458,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 		goto out_regulator;
 	}
 
+	ret = clk_prepare(device_data->clk);
+	if (ret) {
+		dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
+		goto out_clk;
+	}
+
 	/* Enable device power (and clock) */
 	ret = cryp_enable_power(device_data->dev, device_data, false);
 	if (ret) {
 		dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
-		goto out_clk;
+		goto out_clk_unprepare;
 	}
 
 	cryp_error = cryp_check(device_data);
@@ -1523,6 +1529,9 @@ static int ux500_cryp_probe(struct platform_device *pdev)
 out_power:
 	cryp_disable_power(device_data->dev, device_data, false);
 
+out_clk_unprepare:
+	clk_unprepare(device_data->clk);
+
 out_clk:
 	clk_put(device_data->clk);
 
@@ -1593,6 +1602,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
 		dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
 			__func__);
 
+	clk_unprepare(device_data->clk);
 	clk_put(device_data->clk);
 	regulator_put(device_data->pwr_regulator);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:40 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:40 +0100
Subject: [PATCH 17/39] ARM: ux500: Stop passing Cryp DMA channel config
 information though pdata
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-18-git-send-email-lee.jones@linaro.org>

DMA channel configuration information should be setup in the driver.
The Ux500 Cryp driver now does this, so there's no need to send it
though here too.

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ec916ca..38e321c 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -426,20 +426,12 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
 		.mem_to_engine = {
 				.dir = STEDMA40_MEM_TO_PERIPH,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
-				.src_info.data_width = STEDMA40_WORD_WIDTH,
-				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
-				.src_info.psize = STEDMA40_PSIZE_LOG_4,
-				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
 		},
 		.engine_to_mem = {
 				.dir = STEDMA40_PERIPH_TO_MEM,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
-				.src_info.data_width = STEDMA40_WORD_WIDTH,
-				.dst_info.data_width = STEDMA40_WORD_WIDTH,
 				.mode = STEDMA40_MODE_LOGICAL,
-				.src_info.psize = STEDMA40_PSIZE_LOG_4,
-				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
 		}
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:45 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:45 +0100
Subject: [PATCH 22/39] usb: musb: ux500: take the dma_mask from
 coherent_dma_mask
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-23-git-send-email-lee.jones@linaro.org>

The dma_mask will always be the same as the coherent_dma_mask, so let's
cut down on the platform_data burden and set it as such in the driver.
This also saves us from supporting it separately when we come to enable
this driver for Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c |    3 ---
 drivers/usb/musb/ux500.c  |    2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 49d6e57..2f9abe9 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -74,8 +74,6 @@ static struct ux500_musb_board_data musb_board_data = {
 	.dma_filter = stedma40_filter,
 };
 
-static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
-
 static struct musb_hdrc_platform_data musb_platform_data = {
 	.mode = MUSB_OTG,
 	.board_data = &musb_board_data,
@@ -98,7 +96,6 @@ struct platform_device ux500_musb_device = {
 	.id = 0,
 	.dev = {
 		.platform_data = &musb_platform_data,
-		.dma_mask = &ux500_musb_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
 	.num_resources = ARRAY_SIZE(usb_resources),
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 371776f..3cf10bc 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -228,7 +228,7 @@ static int ux500_probe(struct platform_device *pdev)
 	}
 
 	musb->dev.parent		= &pdev->dev;
-	musb->dev.dma_mask		= pdev->dev.dma_mask;
+	musb->dev.dma_mask		= &pdev->dev.coherent_dma_mask;
 	musb->dev.coherent_dma_mask	= pdev->dev.coherent_dma_mask;
 
 	glue->dev			= &pdev->dev;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:43 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:43 +0100
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge into
 the driver
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-21-git-send-email-lee.jones@linaro.org>

For all ux500 based platforms the maximum number of end-points are used.
Move this knowledge into the driver so we can relinquish the burden from
platform data. This also removes quite a bit of complexity from the driver
and will aid us when we come to enable the driver for Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/usb.c                    |   14 ++++++------
 drivers/usb/musb/ux500_dma.c                 |   30 ++++++++------------------
 include/linux/platform_data/usb-musb-ux500.h |    5 +----
 3 files changed, 16 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 72754e3..a21c2e1 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -22,7 +22,7 @@
 		.dir = STEDMA40_MEM_TO_PERIPH, \
 	}
 
-static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
 	= {
 	MUSB_DMA40_RX_CH,
 	MUSB_DMA40_RX_CH,
@@ -34,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
 	MUSB_DMA40_RX_CH
 };
 
-static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
 	= {
 	MUSB_DMA40_TX_CH,
 	MUSB_DMA40_TX_CH,
@@ -46,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
 	MUSB_DMA40_TX_CH,
 };
 
-static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
 	&musb_dma_rx_ch[0],
 	&musb_dma_rx_ch[1],
 	&musb_dma_rx_ch[2],
@@ -57,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
 	&musb_dma_rx_ch[7]
 };
 
-static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
 	&musb_dma_tx_ch[0],
 	&musb_dma_tx_ch[1],
 	&musb_dma_tx_ch[2],
@@ -71,8 +71,6 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
 static struct ux500_musb_board_data musb_board_data = {
 	.dma_rx_param_array = ux500_dma_rx_param_array,
 	.dma_tx_param_array = ux500_dma_tx_param_array,
-	.num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
-	.num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
 	.dma_filter = stedma40_filter,
 };
 
@@ -119,7 +117,7 @@ static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
 {
 	u32 idx;
 
-	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
+	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
 		musb_dma_rx_ch[idx].dev_type = dev_type[idx];
 }
 
@@ -127,7 +125,7 @@ static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
 {
 	u32 idx;
 
-	for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
+	for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
 		musb_dma_tx_ch[idx].dev_type = dev_type[idx];
 }
 
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 3381206..382291b 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -48,10 +48,8 @@ struct ux500_dma_channel {
 
 struct ux500_dma_controller {
 	struct dma_controller controller;
-	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
-	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
-	u32	num_rx_channels;
-	u32	num_tx_channels;
+	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
+	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
 	void *private_data;
 	dma_addr_t phy_base;
 };
@@ -144,19 +142,15 @@ static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
 	struct ux500_dma_channel *ux500_channel = NULL;
 	struct musb *musb = controller->private_data;
 	u8 ch_num = hw_ep->epnum - 1;
-	u32 max_ch;
 
-	/* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
+	/* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
 	 * to specified hw_ep. For example DMA channel 0 can only be allocated
 	 * to hw_ep 1 and 9.
 	 */
 	if (ch_num > 7)
 		ch_num -= 8;
 
-	max_ch = is_tx ? controller->num_tx_channels :
-			controller->num_rx_channels;
-
-	if (ch_num >= max_ch)
+	if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
 		return NULL;
 
 	ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
@@ -264,7 +258,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c)
 	struct dma_channel *channel;
 	u8 ch_num;
 
-	for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
+	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
 		channel = &controller->rx_channel[ch_num].channel;
 		ux500_channel = channel->private_data;
 
@@ -274,7 +268,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c)
 			dma_release_channel(ux500_channel->dma_chan);
 	}
 
-	for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
+	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
 		channel = &controller->tx_channel[ch_num].channel;
 		ux500_channel = channel->private_data;
 
@@ -303,26 +297,21 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 
 	void **param_array;
 	struct ux500_dma_channel *channel_array;
-	u32 ch_count;
 	dma_cap_mask_t mask;
 
-	if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
-		(data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
-		return -EINVAL;
 
-	controller->num_rx_channels = data->num_rx_channels;
-	controller->num_tx_channels = data->num_tx_channels;
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 
 	/* Prepare the loop for RX channels */
 	channel_array = controller->rx_channel;
-	ch_count = data->num_rx_channels;
 	param_array = data->dma_rx_param_array;
 
 	for (dir = 0; dir < 2; dir++) {
-		for (ch_num = 0; ch_num < ch_count; ch_num++) {
+		for (ch_num = 0;
+		     ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
+		     ch_num++) {
 			ux500_channel = &channel_array[ch_num];
 			ux500_channel->controller = controller;
 			ux500_channel->ch_num = ch_num;
@@ -350,7 +339,6 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 
 		/* Prepare the loop for TX channels */
 		channel_array = controller->tx_channel;
-		ch_count = data->num_tx_channels;
 		param_array = data->dma_tx_param_array;
 		is_tx = 1;
 	}
diff --git a/include/linux/platform_data/usb-musb-ux500.h b/include/linux/platform_data/usb-musb-ux500.h
index 4c1cc50..dd9c83a 100644
--- a/include/linux/platform_data/usb-musb-ux500.h
+++ b/include/linux/platform_data/usb-musb-ux500.h
@@ -9,14 +9,11 @@
 
 #include <linux/dmaengine.h>
 
-#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
-#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
+#define UX500_MUSB_DMA_NUM_RX_TX_CHANNELS 8
 
 struct ux500_musb_board_data {
 	void	**dma_rx_param_array;
 	void	**dma_tx_param_array;
-	u32	num_rx_channels;
-	u32	num_tx_channels;
 	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:49 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:49 +0100
Subject: [PATCH 26/39] ARM: ux500: Add an auxdata entry for MUSB for
 clock-name look-up
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-27-git-send-email-lee.jones@linaro.org>

The recently DT:ed MUSB driver will require clock-name by device-name
look-up capability, until common clk has is properly supported by the
ux500 platform.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index b1c9241..e20bc10 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -253,6 +253,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+	OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
 	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:47 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:47 +0100
Subject: [PATCH 24/39] usb: musb: ux500: attempt to find channels by name
 before using pdata
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-25-git-send-email-lee.jones@linaro.org>

If we can ever get to a state where we can solely search for DMA channels
by name, this will almost completely alleviate the requirement to pass
copious amounts of information though platform data. Here we take the
first step towards this. The next step will be to enable Device Tree
complete with name<->event_line mapping.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/usb/musb/ux500_dma.c |   20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 4bd5400..7d80699 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -34,6 +34,11 @@
 #include <linux/platform_data/usb-musb-ux500.h>
 #include "musb_core.h"
 
+static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
+					"iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
+static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
+					"oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
+
 struct ux500_dma_channel {
 	struct dma_channel channel;
 	struct ux500_dma_controller *controller;
@@ -291,6 +296,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct ux500_musb_board_data *data;
 	struct dma_channel *dma_channel = NULL;
+	char **chan_names;
 	u32 ch_num;
 	u8 dir;
 	u8 is_tx = 0;
@@ -312,6 +318,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	/* Prepare the loop for RX channels */
 	channel_array = controller->rx_channel;
 	param_array = data ? data->dma_rx_param_array : NULL;
+	chan_names = (char **)iep_chan_names;
 
 	for (dir = 0; dir < 2; dir++) {
 		for (ch_num = 0;
@@ -327,9 +334,15 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 			dma_channel->status = MUSB_DMA_STATUS_FREE;
 			dma_channel->max_len = SZ_16M;
 
-			ux500_channel->dma_chan = dma_request_channel(mask,
-							data->dma_filter,
-							param_array[ch_num]);
+			ux500_channel->dma_chan =
+				dma_request_slave_channel(dev, chan_names[ch_num]);
+
+			if (!ux500_channel->dma_chan)
+				ux500_channel->dma_chan =
+					dma_request_channel(mask,
+							    data->dma_filter,
+							    param_array[ch_num]);
+
 			if (!ux500_channel->dma_chan) {
 				ERR("Dma pipe allocation error dir=%d ch=%d\n",
 					dir, ch_num);
@@ -345,6 +358,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 		/* Prepare the loop for TX channels */
 		channel_array = controller->tx_channel;
 		param_array = data ? data->dma_tx_param_array : NULL;
+		chan_names = (char **)oep_chan_names;
 		is_tx = 1;
 	}
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:48 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:48 +0100
Subject: [PATCH 25/39] usb: musb: ux500: add device tree probing support
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-26-git-send-email-lee.jones@linaro.org>

This patch will allow ux500-musb to be probed and configured solely from
configuration found in Device Tree.

Cc: Felipe Balbi <balbi at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: linux-usb at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/usb/ux500-usb.txt          |   50 +++++++++++++++++++
 drivers/usb/musb/ux500.c                           |   51 ++++++++++++++++++++
 2 files changed, 101 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/ux500-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt
new file mode 100644
index 0000000..330d6ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ux500-usb.txt
@@ -0,0 +1,50 @@
+Ux500 MUSB
+
+Required properties:
+ - compatible : Should be "stericsson,db8500-musb"
+ - reg        : Offset and length of registers
+ - interrupts : Interrupt; mode, number and trigger
+ - dr_mode    : Dual-role; either host mode "host", peripheral mode "peripheral"
+                or both "otg"
+
+Optional properties:
+ - dmas       : A list of dma channels;
+                dma-controller, event-line, fixed-channel, flags
+ - dma-names  : An ordered list of channel names affiliated to the above
+
+Example:
+
+usb_per5 at a03e0000 {
+	compatible = "stericsson,db8500-musb", "mentor,musb";
+	reg = <0xa03e0000 0x10000>;
+	interrupts = <0 23 0x4>;
+	interrupt-names = "mc";
+
+	dr_mode = "otg";
+
+	dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+	       <&dma 38 0 0x0>, /* Logical - MemToDev */
+	       <&dma 37 0 0x2>, /* Logical - DevToMem */
+	       <&dma 37 0 0x0>, /* Logical - MemToDev */
+	       <&dma 36 0 0x2>, /* Logical - DevToMem */
+	       <&dma 36 0 0x0>, /* Logical - MemToDev */
+	       <&dma 19 0 0x2>, /* Logical - DevToMem */
+	       <&dma 19 0 0x0>, /* Logical - MemToDev */
+	       <&dma 18 0 0x2>, /* Logical - DevToMem */
+	       <&dma 18 0 0x0>, /* Logical - MemToDev */
+	       <&dma 17 0 0x2>, /* Logical - DevToMem */
+	       <&dma 17 0 0x0>, /* Logical - MemToDev */
+	       <&dma 16 0 0x2>, /* Logical - DevToMem */
+	       <&dma 16 0 0x0>, /* Logical - MemToDev */
+	       <&dma 39 0 0x2>, /* Logical - DevToMem */
+	       <&dma 39 0 0x0>; /* Logical - MemToDev */
+
+	dma-names = "iep_1_9",  "oep_1_9",
+		    "iep_2_10", "oep_2_10",
+		    "iep_3_11", "oep_3_11",
+		    "iep_4_12", "oep_4_12",
+		    "iep_5_13", "oep_5_13",
+		    "iep_6_14", "oep_6_14",
+		    "iep_7_15", "oep_7_15",
+		    "iep_8",    "oep_8";
+};
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 3cf10bc..f0beee7 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -25,6 +25,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/usb/musb-ux500.h>
 
@@ -194,14 +195,57 @@ static const struct musb_platform_ops ux500_ops = {
 	.set_vbus	= ux500_musb_set_vbus,
 };
 
+static struct musb_hdrc_platform_data *
+ux500_of_probe(struct platform_device *pdev, struct device_node *np)
+{
+	struct musb_hdrc_platform_data *pdata;
+	const char *mode;
+	int strlen;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	mode = of_get_property(np, "dr_mode", &strlen);
+	if (!mode) {
+		dev_err(&pdev->dev, "No 'dr_mode' property found\n");
+		return NULL;
+	}
+
+	if (strlen > 0) {
+		if (!strcmp(mode, "host"))
+			pdata->mode = MUSB_HOST;
+		if (!strcmp(mode, "otg"))
+			pdata->mode = MUSB_OTG;
+		if (!strcmp(mode, "peripheral"))
+			pdata->mode = MUSB_PERIPHERAL;
+	}
+
+	return pdata;
+}
+
 static int ux500_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
+	struct device_node		*np = pdev->dev.of_node;
 	struct platform_device		*musb;
 	struct ux500_glue		*glue;
 	struct clk			*clk;
 	int				ret = -ENOMEM;
 
+	if (!pdata) {
+		if (np) {
+			pdata = ux500_of_probe(pdev, np);
+			if (!pdata)
+				goto err0;
+
+			pdev->dev.platform_data = pdata;
+		} else {
+			dev_err(&pdev->dev, "no pdata or device tree found\n");
+			goto err0;
+		}
+	}
+
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
@@ -230,6 +274,7 @@ static int ux500_probe(struct platform_device *pdev)
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &pdev->dev.coherent_dma_mask;
 	musb->dev.coherent_dma_mask	= pdev->dev.coherent_dma_mask;
+	musb->dev.of_node		= pdev->dev.of_node;
 
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
@@ -328,12 +373,18 @@ static const struct dev_pm_ops ux500_pm_ops = {
 #define DEV_PM_OPS	NULL
 #endif
 
+static const struct of_device_id ux500_match[] = {
+        { .compatible = "stericsson,db8500-musb", },
+        {}
+};
+
 static struct platform_driver ux500_driver = {
 	.probe		= ux500_probe,
 	.remove		= ux500_remove,
 	.driver		= {
 		.name	= "musb-ux500",
 		.pm	= DEV_PM_OPS,
+		.of_match_table = ux500_match,
 	},
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:46 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:46 +0100
Subject: [PATCH 23/39] usb: musb: ux500: harden checks for platform data
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-24-git-send-email-lee.jones@linaro.org>

In its current state, the ux500-musb driver uses platform data pointers
blindly with no prior checking. If no platform data pointer is passed
this will Oops the kernel. In this patch we ensure platform data and
board data are present prior to using them.

Cc: Felipe Balbi <balbi at ti.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/usb/musb/ux500_dma.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 382291b..4bd5400 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -289,7 +289,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	struct musb *musb = controller->private_data;
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
-	struct ux500_musb_board_data *data = plat->board_data;
+	struct ux500_musb_board_data *data;
 	struct dma_channel *dma_channel = NULL;
 	u32 ch_num;
 	u8 dir;
@@ -299,14 +299,19 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 	struct ux500_dma_channel *channel_array;
 	dma_cap_mask_t mask;
 
+	if (!plat) {
+		dev_err(musb->controller, "No platform data\n");
+		return -EINVAL;
+	}
 
+	data = plat->board_data;
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 
 	/* Prepare the loop for RX channels */
 	channel_array = controller->rx_channel;
-	param_array = data->dma_rx_param_array;
+	param_array = data ? data->dma_rx_param_array : NULL;
 
 	for (dir = 0; dir < 2; dir++) {
 		for (ch_num = 0;
@@ -339,7 +344,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
 
 		/* Prepare the loop for TX channels */
 		channel_array = controller->tx_channel;
-		param_array = data->dma_tx_param_array;
+		param_array = data ? data->dma_tx_param_array : NULL;
 		is_tx = 1;
 	}
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:50 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:50 +0100
Subject: [PATCH 27/39] ARM: ux500: Remove ux500-musb platform registation when
 booting with DT
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-28-git-send-email-lee.jones@linaro.org>

Now the ux500-musb driver has been enabled for Device Tree, there is no
requirement to register it from platform code.

Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index e20bc10..f1e7a75 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -221,8 +221,6 @@ static struct device * __init u8500_of_init_devices(void)
 {
 	struct device *parent = db8500_soc_device_init();
 
-	db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
-
 	return parent;
 }
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:53 +0100
Subject: [PATCH 30/39] ARM: ux500: Replace ST-E's home-brew DMA direction
 definition with the generic one
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-31-git-send-email-lee.jones@linaro.org>

STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-audio.c |   12 ++++++------
 arch/arm/mach-ux500/board-mop500-sdi.c   |   16 ++++++++--------
 arch/arm/mach-ux500/board-mop500.c       |   22 +++++++++++-----------
 arch/arm/mach-ux500/usb.c                |    4 ++--
 4 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index ec87262..bfe443d 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -21,13 +21,13 @@
 
 static struct stedma40_chan_cfg msp0_dma_rx = {
 	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
 static struct stedma40_chan_cfg msp0_dma_tx = {
 	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
@@ -39,13 +39,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
 
 static struct stedma40_chan_cfg msp1_dma_rx = {
 	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV30_MSP3,
 };
 
 static struct stedma40_chan_cfg msp1_dma_tx = {
 	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV30_MSP1,
 };
 
@@ -57,13 +57,13 @@ struct msp_i2s_platform_data msp1_platform_data = {
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
 	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV14_MSP2,
 };
 
 static struct stedma40_chan_cfg msp2_dma_tx = {
 	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV14_MSP2,
 	.use_fixed_channel = true,
 	.phy_channel = 1,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 29be714..e6891d1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -34,13 +34,13 @@
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 #endif
@@ -81,13 +81,13 @@ void mop500_sdi_tc35892_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 #endif
@@ -112,13 +112,13 @@ struct mmci_platform_data mop500_sdi1_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type =  DB8500_DMA_DEV28_SD_MM2,
 };
 
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV28_SD_MM2,
 };
 #endif
@@ -144,13 +144,13 @@ struct mmci_platform_data mop500_sdi2_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type =  DB8500_DMA_DEV42_SD_MM4,
 };
 
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV42_SD_MM4,
 };
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ba26ae3..0b018c4 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -424,19 +424,19 @@ void mop500_snowball_ethernet_clock_enable(void)
 
 static struct cryp_platform_data u8500_cryp1_platform_data = {
 		.mem_to_engine = {
-				.dir = STEDMA40_MEM_TO_PERIPH,
+				.dir = DMA_MEM_TO_DEV,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
 				.mode = STEDMA40_MODE_LOGICAL,
 		},
 		.engine_to_mem = {
-				.dir = STEDMA40_PERIPH_TO_MEM,
+				.dir = DMA_DEV_TO_MEM,
 				.dev_type = DB8500_DMA_DEV48_CAC1,
 				.mode = STEDMA40_MODE_LOGICAL,
 		}
 };
 
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
-		.dir = STEDMA40_MEM_TO_PERIPH,
+		.dir = DMA_MEM_TO_DEV,
 		.dev_type = DB8500_DMA_DEV50_HAC1_TX,
 		.mode = STEDMA40_MODE_LOGICAL,
 };
@@ -455,13 +455,13 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV8_SSP0,
 };
 
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV8_SSP0,
 };
 #endif
@@ -490,37 +490,37 @@ static void __init mop500_spi_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_PERIPH_TO_MEM,
+	.dir = DMA_DEV_TO_MEM,
 	.dev_type = DB8500_DMA_DEV11_UART2,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_PERIPH,
+	.dir = DMA_MEM_TO_DEV,
 	.dev_type = DB8500_DMA_DEV11_UART2,
 };
 #endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2f9abe9..b7bd8d3 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -14,12 +14,12 @@
 
 #define MUSB_DMA40_RX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
-		.dir = STEDMA40_PERIPH_TO_MEM, \
+		.dir = DMA_DEV_TO_MEM, \
 	}
 
 #define MUSB_DMA40_TX_CH { \
 		.mode = STEDMA40_MODE_LOGICAL, \
-		.dir = STEDMA40_MEM_TO_PERIPH, \
+		.dir = DMA_MEM_TO_DEV, \
 	}
 
 static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:51 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:51 +0100
Subject: [PATCH 28/39] ARM: ux500: Remove empty function
 u8500_of_init_devices()
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-29-git-send-email-lee.jones@linaro.org>

As promised, now all devices which resided in u8500_of_init_devices()
have been enabled for Device Tree, we can completely remove it.

Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |   14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f1e7a75..b407601 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -215,15 +215,6 @@ struct device * __init u8500_init_devices(void)
 }
 
 #ifdef CONFIG_MACH_UX500_DT
-
-/* TODO: Once all pieces are DT:ed, remove completely. */
-static struct device * __init u8500_of_init_devices(void)
-{
-	struct device *parent = db8500_soc_device_init();
-
-	return parent;
-}
-
 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
@@ -283,7 +274,7 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
 
 static void __init u8500_init_machine(void)
 {
-	struct device *parent = NULL;
+	struct device *parent = db8500_soc_device_init();
 
 	/* Pinmaps must be in place before devices register */
 	if (of_machine_is_compatible("st-ericsson,mop500"))
@@ -296,9 +287,6 @@ static void __init u8500_init_machine(void)
 	else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
 		/* TODO: Add pinmaps for ccu9540 board. */
 
-	/* TODO: Export SoC, USB, cpu-freq and DMA40 */
-	parent = u8500_of_init_devices();
-
 	/* automatically probe child nodes of db8500 device */
 	of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:52 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:52 +0100
Subject: [PATCH 29/39] dmaengine: ste_dma40: Use the BIT macro to replace ugly
 '(1 << x)'s
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-30-git-send-email-lee.jones@linaro.org>

The aim is to make the code that little more readable.

Acked-by: Vinod Koul <vnod.koul at intel.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |   20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 6ed7757..08bc58a 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -54,8 +54,8 @@
 #define MAX_LCLA_ALLOC_ATTEMPTS 256
 
 /* Bit markings for allocation map */
-#define D40_ALLOC_FREE		(1 << 31)
-#define D40_ALLOC_PHY		(1 << 30)
+#define D40_ALLOC_FREE		BIT(31)
+#define D40_ALLOC_PHY		BIT(30)
 #define D40_ALLOC_LOG_FREE	0
 
 /* Reserved event lines for memcpy only. */
@@ -1738,7 +1738,7 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data)
 		}
 
 		/* ACK interrupt */
-		writel(1 << idx, base->virtbase + il[row].clr);
+		writel(BIT(idx), base->virtbase + il[row].clr);
 
 		spin_lock(&d40c->lock);
 
@@ -1828,8 +1828,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy,
 		if (phy->allocated_src == D40_ALLOC_FREE)
 			phy->allocated_src = D40_ALLOC_LOG_FREE;
 
-		if (!(phy->allocated_src & (1 << log_event_line))) {
-			phy->allocated_src |= 1 << log_event_line;
+		if (!(phy->allocated_src & BIT(log_event_line))) {
+			phy->allocated_src |= BIT(log_event_line);
 			goto found;
 		} else
 			goto not_found;
@@ -1840,8 +1840,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy,
 		if (phy->allocated_dst == D40_ALLOC_FREE)
 			phy->allocated_dst = D40_ALLOC_LOG_FREE;
 
-		if (!(phy->allocated_dst & (1 << log_event_line))) {
-			phy->allocated_dst |= 1 << log_event_line;
+		if (!(phy->allocated_dst & BIT(log_event_line))) {
+			phy->allocated_dst |= BIT(log_event_line);
 			goto found;
 		} else
 			goto not_found;
@@ -1871,11 +1871,11 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
 
 	/* Logical channel */
 	if (is_src) {
-		phy->allocated_src &= ~(1 << log_event_line);
+		phy->allocated_src &= ~BIT(log_event_line);
 		if (phy->allocated_src == D40_ALLOC_LOG_FREE)
 			phy->allocated_src = D40_ALLOC_FREE;
 	} else {
-		phy->allocated_dst &= ~(1 << log_event_line);
+		phy->allocated_dst &= ~BIT(log_event_line);
 		if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
 			phy->allocated_dst = D40_ALLOC_FREE;
 	}
@@ -2356,7 +2356,7 @@ static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
 	u32 rtreg;
 	u32 event = D40_TYPE_TO_EVENT(dev_type);
 	u32 group = D40_TYPE_TO_GROUP(dev_type);
-	u32 bit = 1 << event;
+	u32 bit = BIT(event);
 	u32 prioreg;
 	struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:55 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:55 +0100
Subject: [PATCH 32/39] ARM: ux500: Remove recently unused stedma40_xfer_dir
 enums
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-33-git-send-email-lee.jones@linaro.org>

We're now using the transfer direction definitions provided by the DMA
sub-system, so the home-brew ones have become obsolete.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/platform_data/dma-ste-dma40.h |   10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 288dc24..54ddca6 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -77,14 +77,6 @@ enum stedma40_periph_data_width {
 	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
 };
 
-enum stedma40_xfer_dir {
-	STEDMA40_MEM_TO_MEM = 1,
-	STEDMA40_MEM_TO_PERIPH,
-	STEDMA40_PERIPH_TO_MEM,
-	STEDMA40_PERIPH_TO_PERIPH
-};
-
-
 /**
  * struct stedma40_half_channel_info - dst/src channel configuration
  *
@@ -120,7 +112,7 @@ struct stedma40_half_channel_info {
  *
  */
 struct stedma40_chan_cfg {
-	enum stedma40_xfer_dir			 dir;
+	enum dma_transfer_direction		 dir;
 	bool					 high_priority;
 	bool					 realtime;
 	enum stedma40_mode			 mode;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:54 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:54 +0100
Subject: [PATCH 31/39] dmaengine: ste_dma40: Replace ST-E's home-brew DMA
 direction defs with generic ones
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-32-git-send-email-lee.jones@linaro.org>

STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c    |   56 ++++++++++++++++++++++----------------------
 drivers/dma/ste_dma40_ll.c |   24 +++++++++----------
 2 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 08bc58a..483da16 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -78,7 +78,7 @@ static int dma40_memcpy_channels[] = {
 /* Default configuration for physcial memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 	.mode = STEDMA40_MODE_PHYSICAL,
-	.dir = STEDMA40_MEM_TO_MEM,
+	.dir = DMA_MEM_TO_MEM,
 
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.src_info.psize = STEDMA40_PSIZE_PHY_1,
@@ -92,7 +92,7 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 /* Default configuration for logical memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 	.mode = STEDMA40_MODE_LOGICAL,
-	.dir = STEDMA40_MEM_TO_MEM,
+	.dir = DMA_MEM_TO_MEM,
 
 	.src_info.data_width = STEDMA40_BYTE_WIDTH,
 	.src_info.psize = STEDMA40_PSIZE_LOG_1,
@@ -843,7 +843,7 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
 		 * that uses linked lists.
 		 */
 		if (!(chan->phy_chan->use_soft_lli &&
-			chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM))
+			chan->dma_cfg.dir == DMA_DEV_TO_MEM))
 			curr_lcla = d40_lcla_alloc_one(chan, desc);
 
 		first_lcla = curr_lcla;
@@ -1311,12 +1311,12 @@ static void d40_config_set_event(struct d40_chan *d40c,
 	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
 
 	/* Enable event line connected to device (or memcpy) */
-	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+	if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
+	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
 		__d40_config_set_event(d40c, event_type, event,
 				       D40_CHAN_REG_SSLNK);
 
-	if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM)
+	if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
 		__d40_config_set_event(d40c, event_type, event,
 				       D40_CHAN_REG_SDLNK);
 }
@@ -1774,7 +1774,7 @@ static int d40_validate_conf(struct d40_chan *d40c,
 		res = -EINVAL;
 	}
 
-	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
+	if (conf->dir == DMA_DEV_TO_DEV) {
 		/*
 		 * DMAC HW supports it. Will be added to this driver,
 		 * in case any dma client requires it.
@@ -1905,11 +1905,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
 	phys = d40c->base->phy_res;
 	num_phy_chans = d40c->base->num_phy_chans;
 
-	if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
+	if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
 		log_num = 2 * dev_type;
 		is_src = true;
-	} else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-		   d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+	} else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+		   d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
 		/* dst event lines are used for logical memcpy */
 		log_num = 2 * dev_type + 1;
 		is_src = false;
@@ -1920,7 +1920,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
 	event_line = D40_TYPE_TO_EVENT(dev_type);
 
 	if (!is_log) {
-		if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+		if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
 			/* Find physical half channel */
 			if (d40c->dma_cfg.use_fixed_channel) {
 				i = d40c->dma_cfg.phy_channel;
@@ -2068,10 +2068,10 @@ static int d40_free_dma(struct d40_chan *d40c)
 		return -EINVAL;
 	}
 
-	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
+	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
 		is_src = false;
-	else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+	else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
 		is_src = true;
 	else {
 		chan_err(d40c, "Unknown direction\n");
@@ -2133,10 +2133,10 @@ static bool d40_is_paused(struct d40_chan *d40c)
 		goto _exit;
 	}
 
-	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
 		status = readl(chanbase + D40_CHAN_REG_SDLNK);
-	} else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
+	} else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
 		status = readl(chanbase + D40_CHAN_REG_SSLNK);
 	} else {
 		chan_err(d40c, "Unknown direction\n");
@@ -2387,12 +2387,12 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
 	if (d40c->base->rev < 3)
 		return;
 
-	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+	if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
+	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
 
-	if ((d40c->dma_cfg.dir ==  STEDMA40_MEM_TO_PERIPH) ||
-	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+	if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
+	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
 }
 
@@ -2423,11 +2423,11 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
 
 	switch (D40_DT_FLAGS_DIR(flags)) {
 	case 0:
-		cfg.dir = STEDMA40_MEM_TO_PERIPH;
+		cfg.dir = DMA_MEM_TO_DEV;
 		cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
 		break;
 	case 1:
-		cfg.dir = STEDMA40_PERIPH_TO_MEM;
+		cfg.dir = DMA_DEV_TO_MEM;
 		cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
 		break;
 	}
@@ -2473,7 +2473,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	d40_set_prio_realtime(d40c);
 
 	if (chan_is_logical(d40c)) {
-		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+		if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
 			d40c->lcpa = d40c->base->lcpa_base +
 				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
 		else
@@ -2746,12 +2746,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	if (config->direction == DMA_DEV_TO_MEM) {
 		config_addr = config->src_addr;
 
-		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
+		if (cfg->dir != DMA_DEV_TO_MEM)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for peripheral "
 				"to memory transfer (%d) overriding\n",
 				cfg->dir);
-		cfg->dir = STEDMA40_PERIPH_TO_MEM;
+		cfg->dir = DMA_DEV_TO_MEM;
 
 		/* Configure the memory side */
 		if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
@@ -2762,12 +2762,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 	} else if (config->direction == DMA_MEM_TO_DEV) {
 		config_addr = config->dst_addr;
 
-		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
+		if (cfg->dir != DMA_MEM_TO_DEV)
 			dev_dbg(d40c->base->dev,
 				"channel was not configured for memory "
 				"to peripheral transfer (%d) overriding\n",
 				cfg->dir);
-		cfg->dir = STEDMA40_MEM_TO_PERIPH;
+		cfg->dir = DMA_MEM_TO_DEV;
 
 		/* Configure the memory side */
 		if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index ab5a2a7..121c0ce 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -18,23 +18,23 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 	u32 l1 = 0; /* src */
 
 	/* src is mem? -> increase address pos */
-	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
-	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
+	if (cfg->dir ==  DMA_MEM_TO_DEV ||
+	    cfg->dir ==  DMA_MEM_TO_MEM)
 		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
 
 	/* dst is mem? -> increase address pos */
-	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
-	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
+	if (cfg->dir ==  DMA_DEV_TO_MEM ||
+	    cfg->dir ==  DMA_MEM_TO_MEM)
 		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
 
 	/* src is hw? -> master port 1 */
-	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
-	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
+	if (cfg->dir ==  DMA_DEV_TO_MEM ||
+	    cfg->dir ==  DMA_DEV_TO_DEV)
 		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
 
 	/* dst is hw? -> master port 1 */
-	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
-	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
+	if (cfg->dir ==  DMA_MEM_TO_DEV ||
+	    cfg->dir ==  DMA_DEV_TO_DEV)
 		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
 
 	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
@@ -55,8 +55,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 	u32 src = 0;
 	u32 dst = 0;
 
-	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
-	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+	if ((cfg->dir == DMA_DEV_TO_MEM) ||
+	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
 		src |= 1 << D40_SREG_CFG_MST_POS;
 		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
@@ -66,8 +66,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 		else
 			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
 	}
-	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
-	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+	if ((cfg->dir == DMA_MEM_TO_DEV) ||
+	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
 		dst |= 1 << D40_SREG_CFG_MST_POS;
 		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:56 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:56 +0100
Subject: [PATCH 33/39] dmaengine: ste_dma40_ll: Use the BIT macro to replace
 ugly '(1 << x)'s
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-34-git-send-email-lee.jones@linaro.org>

The aim is to make the code that little more readable.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40_ll.c |   44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 121c0ce..5ddd724 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -20,28 +20,28 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 	/* src is mem? -> increase address pos */
 	if (cfg->dir ==  DMA_MEM_TO_DEV ||
 	    cfg->dir ==  DMA_MEM_TO_MEM)
-		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
+		l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
 
 	/* dst is mem? -> increase address pos */
 	if (cfg->dir ==  DMA_DEV_TO_MEM ||
 	    cfg->dir ==  DMA_MEM_TO_MEM)
-		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
+		l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
 
 	/* src is hw? -> master port 1 */
 	if (cfg->dir ==  DMA_DEV_TO_MEM ||
 	    cfg->dir ==  DMA_DEV_TO_DEV)
-		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
+		l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
 
 	/* dst is hw? -> master port 1 */
 	if (cfg->dir ==  DMA_MEM_TO_DEV ||
 	    cfg->dir ==  DMA_DEV_TO_DEV)
-		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
+		l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
 
-	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
+	l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
 	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
 	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
 
-	l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
+	l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
 	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
 	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
 
@@ -58,39 +58,39 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 	if ((cfg->dir == DMA_DEV_TO_MEM) ||
 	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
-		src |= 1 << D40_SREG_CFG_MST_POS;
+		src |= BIT(D40_SREG_CFG_MST_POS);
 		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
 
 		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
+			src |= BIT(D40_SREG_CFG_PHY_TM_POS);
 		else
 			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
 	}
 	if ((cfg->dir == DMA_MEM_TO_DEV) ||
 	    (cfg->dir == DMA_DEV_TO_DEV)) {
 		/* Set master port to 1 */
-		dst |= 1 << D40_SREG_CFG_MST_POS;
+		dst |= BIT(D40_SREG_CFG_MST_POS);
 		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
 
 		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
-			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
+			dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
 		else
 			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
 	}
 	/* Interrupt on end of transfer for destination */
-	dst |= 1 << D40_SREG_CFG_TIM_POS;
+	dst |= BIT(D40_SREG_CFG_TIM_POS);
 
 	/* Generate interrupt on error */
-	src |= 1 << D40_SREG_CFG_EIM_POS;
-	dst |= 1 << D40_SREG_CFG_EIM_POS;
+	src |= BIT(D40_SREG_CFG_EIM_POS);
+	dst |= BIT(D40_SREG_CFG_EIM_POS);
 
 	/* PSIZE */
 	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
-		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
 		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
 	}
 	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
-		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+		dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
 		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
 	}
 
@@ -100,14 +100,14 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 
 	/* Set the priority bit to high for the physical channel */
 	if (cfg->high_priority) {
-		src |= 1 << D40_SREG_CFG_PRI_POS;
-		dst |= 1 << D40_SREG_CFG_PRI_POS;
+		src |= BIT(D40_SREG_CFG_PRI_POS);
+		dst |= BIT(D40_SREG_CFG_PRI_POS);
 	}
 
 	if (cfg->src_info.big_endian)
-		src |= 1 << D40_SREG_CFG_LBE_POS;
+		src |= BIT(D40_SREG_CFG_LBE_POS);
 	if (cfg->dst_info.big_endian)
-		dst |= 1 << D40_SREG_CFG_LBE_POS;
+		dst |= BIT(D40_SREG_CFG_LBE_POS);
 
 	*src_cfg = src;
 	*dst_cfg = dst;
@@ -157,15 +157,15 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 
 	/* If this scatter list entry is the last one, no next link */
 	if (next_lli == 0)
-		lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
+		lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
 	else
 		lli->reg_lnk = next_lli;
 
 	/* Set/clear interrupt generation on this link item.*/
 	if (term_int)
-		lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
+		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
 	else
-		lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
+		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
 
 	/* Post link */
 	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:58 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:58 +0100
Subject: [PATCH 35/39] dmaengine: ste_dma40_ll: Replace meaningless register
 set with comment
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-36-git-send-email-lee.jones@linaro.org>

Unsure of the author's intentions, rather than just removing the nop,
we're replacing it with a comment containing the possible intention
of the statement OR:ing with 0.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40_ll.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index a035dfe..27b818d 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -182,8 +182,10 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 	else
 		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
 
-	/* Post link */
-	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
+	/*
+	 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
+	 * Relink happens after transfer completion.
+	 */
 
 	return 0;
 }
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:57 +0100
Subject: [PATCH 34/39] dmaengine: ste_dma40: Convert data_width from register
 bit format to value
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-35-git-send-email-lee.jones@linaro.org>

When a DMA client requests and configures a DMA channel, it requests
data_width in Bytes. The DMA40 driver then swiftly converts it over to
the necessary register bit value. Unfortunately, for any subsequent
calculations we have to shift '1' by the bit pattern (1 << data_width)
times to make any sense of it.

This patch flips the semantics on its head and only converts the value
to its respective register bit pattern when writing to registers. This
way we can use the true data_width (in Bytes) value.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c                     |   63 +++++++++++----------------
 drivers/dma/ste_dma40_ll.c                  |   43 ++++++++++++------
 include/linux/platform_data/dma-ste-dma40.h |    9 +---
 sound/soc/ux500/ux500_pcm.c                 |   10 ++---
 4 files changed, 60 insertions(+), 65 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 483da16..76c255f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -80,11 +80,11 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 	.mode = STEDMA40_MODE_PHYSICAL,
 	.dir = DMA_MEM_TO_MEM,
 
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.src_info.psize = STEDMA40_PSIZE_PHY_1,
 	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.dst_info.psize = STEDMA40_PSIZE_PHY_1,
 	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 };
@@ -94,11 +94,11 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 	.mode = STEDMA40_MODE_LOGICAL,
 	.dir = DMA_MEM_TO_MEM,
 
-	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.src_info.psize = STEDMA40_PSIZE_LOG_1,
 	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 
-	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
 	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 };
@@ -1005,20 +1005,21 @@ static int d40_psize_2_burst_size(bool is_log, int psize)
 
 /*
  * The dma only supports transmitting packages up to
- * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
- * dma elements required to send the entire sg list
+ * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
+ *
+ * Calculate the total number of dma elements required to send the entire sg list.
  */
 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
 {
 	int dmalen;
 	u32 max_w = max(data_width1, data_width2);
 	u32 min_w = min(data_width1, data_width2);
-	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
 
 	if (seg_max > STEDMA40_MAX_SEG_SIZE)
-		seg_max -= (1 << max_w);
+		seg_max -= max_w;
 
-	if (!IS_ALIGNED(size, 1 << max_w))
+	if (!IS_ALIGNED(size, max_w))
 		return -EINVAL;
 
 	if (size <= seg_max)
@@ -1464,7 +1465,7 @@ static u32 d40_residue(struct d40_chan *d40c)
 			  >> D40_SREG_ELEM_PHY_ECNT_POS;
 	}
 
-	return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
+	return num_elt * d40c->dma_cfg.dst_info.data_width;
 }
 
 static bool d40_tx_is_linked(struct d40_chan *d40c)
@@ -1784,9 +1785,9 @@ static int d40_validate_conf(struct d40_chan *d40c,
 	}
 
 	if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
-	    (1 << conf->src_info.data_width) !=
+	    conf->src_info.data_width !=
 	    d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
-	    (1 << conf->dst_info.data_width)) {
+	    conf->dst_info.data_width) {
 		/*
 		 * The DMAC hardware only supports
 		 * src (burst x width) == dst (burst x width)
@@ -2673,33 +2674,10 @@ static void d40_terminate_all(struct dma_chan *chan)
 static int
 dma40_config_to_halfchannel(struct d40_chan *d40c,
 			    struct stedma40_half_channel_info *info,
-			    enum dma_slave_buswidth width,
 			    u32 maxburst)
 {
-	enum stedma40_periph_data_width addr_width;
 	int psize;
 
-	switch (width) {
-	case DMA_SLAVE_BUSWIDTH_1_BYTE:
-		addr_width = STEDMA40_BYTE_WIDTH;
-		break;
-	case DMA_SLAVE_BUSWIDTH_2_BYTES:
-		addr_width = STEDMA40_HALFWORD_WIDTH;
-		break;
-	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		addr_width = STEDMA40_WORD_WIDTH;
-		break;
-	case DMA_SLAVE_BUSWIDTH_8_BYTES:
-		addr_width = STEDMA40_DOUBLEWORD_WIDTH;
-		break;
-	default:
-		dev_err(d40c->base->dev,
-			"illegal peripheral address width "
-			"requested (%d)\n",
-			width);
-		return -EINVAL;
-	}
-
 	if (chan_is_logical(d40c)) {
 		if (maxburst >= 16)
 			psize = STEDMA40_PSIZE_LOG_16;
@@ -2720,7 +2698,6 @@ dma40_config_to_halfchannel(struct d40_chan *d40c,
 			psize = STEDMA40_PSIZE_PHY_1;
 	}
 
-	info->data_width = addr_width;
 	info->psize = psize;
 	info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
 
@@ -2804,14 +2781,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
 		src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
 	}
 
+	/* Only valid widths are; 1, 2, 4 and 8. */
+	if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
+	    src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
+	    dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
+	    dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
+	    ((src_addr_width > 1) && (src_addr_width & 1)) ||
+	    ((dst_addr_width > 1) && (dst_addr_width & 1)))
+		return -EINVAL;
+
+	cfg->src_info.data_width = src_addr_width;
+	cfg->dst_info.data_width = dst_addr_width;
+
 	ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
-					  src_addr_width,
 					  src_maxburst);
 	if (ret)
 		return ret;
 
 	ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
-					  dst_addr_width,
 					  dst_maxburst);
 	if (ret)
 		return ret;
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 5ddd724..a035dfe 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -10,6 +10,18 @@
 
 #include "ste_dma40_ll.h"
 
+u8 d40_width_to_bits(enum dma_slave_buswidth width)
+{
+	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+		return STEDMA40_ESIZE_8_BIT;
+	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+		return STEDMA40_ESIZE_16_BIT;
+	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
+		return STEDMA40_ESIZE_64_BIT;
+	else
+		return STEDMA40_ESIZE_32_BIT;
+}
+
 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 		 u32 *lcsp1, u32 *lcsp3)
@@ -39,11 +51,13 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 
 	l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
 	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
-	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
+	l3 |= d40_width_to_bits(cfg->dst_info.data_width)
+		<< D40_MEM_LCSP3_DCFG_ESIZE_POS;
 
 	l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
 	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
-	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
+	l1 |= d40_width_to_bits(cfg->src_info.data_width)
+		<< D40_MEM_LCSP1_SCFG_ESIZE_POS;
 
 	*lcsp1 = l1;
 	*lcsp3 = l3;
@@ -95,8 +109,10 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
 	}
 
 	/* Element size */
-	src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
-	dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
+	src |= d40_width_to_bits(cfg->src_info.data_width)
+		<< D40_SREG_CFG_ESIZE_POS;
+	dst |= d40_width_to_bits(cfg->dst_info.data_width)
+		<< D40_SREG_CFG_ESIZE_POS;
 
 	/* Set the priority bit to high for the physical channel */
 	if (cfg->high_priority) {
@@ -133,23 +149,22 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 		num_elems = 2 << psize;
 
 	/* Must be aligned */
-	if (!IS_ALIGNED(data, 0x1 << data_width))
+	if (!IS_ALIGNED(data, data_width))
 		return -EINVAL;
 
 	/* Transfer size can't be smaller than (num_elms * elem_size) */
-	if (data_size < num_elems * (0x1 << data_width))
+	if (data_size < num_elems * data_width)
 		return -EINVAL;
 
 	/* The number of elements. IE now many chunks */
-	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
+	lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
 
 	/*
 	 * Distance to next element sized entry.
 	 * Usually the size of the element unless you want gaps.
 	 */
 	if (addr_inc)
-		lli->reg_elt |= (0x1 << data_width) <<
-			D40_SREG_ELEM_PHY_EIDX_POS;
+		lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
 
 	/* Where the data is */
 	lli->reg_ptr = data;
@@ -177,16 +192,16 @@ static int d40_seg_size(int size, int data_width1, int data_width2)
 {
 	u32 max_w = max(data_width1, data_width2);
 	u32 min_w = min(data_width1, data_width2);
-	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
 
 	if (seg_max > STEDMA40_MAX_SEG_SIZE)
-		seg_max -= (1 << max_w);
+		seg_max -= max_w;
 
 	if (size <= seg_max)
 		return size;
 
 	if (size <= 2 * seg_max)
-		return ALIGN(size / 2, 1 << max_w);
+		return ALIGN(size / 2, max_w);
 
 	return seg_max;
 }
@@ -352,10 +367,10 @@ static void d40_log_fill_lli(struct d40_log_lli *lli,
 	lli->lcsp13 = reg_cfg;
 
 	/* The number of elements to transfer */
-	lli->lcsp02 = ((data_size >> data_width) <<
+	lli->lcsp02 = ((data_size / data_width) <<
 		       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
 
-	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
+	BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
 
 	/* 16 LSBs address of the current element */
 	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 54ddca6..ceba6dc 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
 	STEDMA40_FLOW_CTRL,
 };
 
-enum stedma40_periph_data_width {
-	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
-	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
-	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
-	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
-};
-
 /**
  * struct stedma40_half_channel_info - dst/src channel configuration
  *
@@ -87,7 +80,7 @@ enum stedma40_periph_data_width {
  */
 struct stedma40_half_channel_info {
 	bool big_endian;
-	enum stedma40_periph_data_width data_width;
+	enum dma_slave_buswidth data_width;
 	int psize;
 	enum stedma40_flow_ctrl flow_ctrl;
 };
diff --git a/sound/soc/ux500/ux500_pcm.c b/sound/soc/ux500/ux500_pcm.c
index b6e5ae2..31f9bbc 100644
--- a/sound/soc/ux500/ux500_pcm.c
+++ b/sound/soc/ux500/ux500_pcm.c
@@ -76,20 +76,20 @@ static struct dma_chan *ux500_pcm_request_chan(struct snd_soc_pcm_runtime *rtd,
 	dma_params = snd_soc_dai_get_dma_data(dai, substream);
 	dma_cfg = dma_params->dma_cfg;
 
-	mem_data_width = STEDMA40_HALFWORD_WIDTH;
+	mem_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 
 	switch (dma_params->data_size) {
 	case 32:
-		per_data_width = STEDMA40_WORD_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	case 16:
-		per_data_width = STEDMA40_HALFWORD_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 		break;
 	case 8:
-		per_data_width = STEDMA40_BYTE_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 		break;
 	default:
-		per_data_width = STEDMA40_WORD_WIDTH;
+		per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	}
 
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:52:01 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:52:01 +0100
Subject: [PATCH 38/39] dmaengine: ste_dma40: Fetch the number of physical
 channels from DT
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-39-git-send-email-lee.jones@linaro.org>

Some platforms insist on obscure physical channel availability. This
information is currently passed though platform data in internal BSP
kernels. Once those platforms land, they'll need to configure them
appropriately, so we may as well add the infrastructure.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/dma/ste_dma40.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index ae462d3..4e528dd 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3482,7 +3482,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
-	int num_memcpy = 0;
+	int num_phy = 0, num_memcpy = 0;
 	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
@@ -3491,6 +3491,11 @@ static int __init d40_of_probe(struct platform_device *pdev,
 	if (!pdata)
 		return -ENOMEM;
 
+	/* If absent this value will be obtained from h/w. */
+	of_property_read_u32(np, "dma-channels", &num_phy);
+	if (num_phy > 0)
+		pdata->num_of_phy_chans = num_phy;
+
 	list = of_get_property(np, "memcpy-channels", &num_memcpy);
 	num_memcpy /= sizeof(*list);
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:52:02 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:52:02 +0100
Subject: [PATCH 39/39] dmaengine: ste_dma40: Fetch disabled channels from DT
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-40-git-send-email-lee.jones@linaro.org>

Some platforms have channels which are not available for normal use.
This information is currently passed though platform data in internal
BSP kernels. Once those platforms land, they'll need to configure them
appropriately, so we may as well add the infrastructure.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/dma/ste-dma40.txt |    2 ++
 drivers/dma/ste_dma40.c                             |   17 ++++++++++++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index aa272d8..bea5b73 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -11,6 +11,7 @@ Required properties:
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
 		the driver will attempt to obtain the information from H/W
+- disabled-channels: Channels which can not be used
 
 Example:
 
@@ -23,6 +24,7 @@ Example:
 
 		#dma-cells = <2>;
 		memcpy-channels  = <56 57 58 59 60>;
+		disabled-channels  = <12>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 4e528dd..ffac822 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3482,7 +3482,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
-	int num_phy = 0, num_memcpy = 0;
+	int num_phy = 0, num_memcpy = 0, num_disabled = 0;
 	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
@@ -3511,6 +3511,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 				   dma40_memcpy_channels,
 				   num_memcpy);
 
+	list = of_get_property(np, "disabled-channels", &num_disabled);
+	num_disabled /= sizeof(*list);
+
+	if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of disabled channels specified (%d)\n",
+			num_disabled);
+		return -EINVAL;
+	}
+
+	of_property_read_u32_array(np, "disabled-channels",
+				   pdata->disabled_channels,
+				   num_disabled);
+	pdata->disabled_channels[num_disabled] = -1;
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:51:59 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:51:59 +0100
Subject: [PATCH 36/39] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-37-git-send-email-lee.jones@linaro.org>

At this moment in time the memcpy channels which can be used by the D40
are fixed, as each supported platform in Mainline uses the same ones.
However, platforms do exist which don't follow this convention, so
these will need to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.

Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <djbw at fb.com>
Cc: Per Forlin <per.forlin at stericsson.com>
Cc: Rabin Vincent <rabin at rab.in>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/dma/ste-dma40.txt          |    2 +
 drivers/dma/ste_dma40.c                            |   40 ++++++++++++++++----
 include/linux/platform_data/dma-ste-dma40.h        |    2 +
 3 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 2679a87..aa272d8 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -6,6 +6,7 @@ Required properties:
 - reg-names: Names of the above areas to use during resource look-up
 - interrupt: Should contain the DMAC interrupt number
 - #dma-cells: must be <3>
+- memcpy-channels: Channels to be used for memcpy
 
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
@@ -21,6 +22,7 @@ Example:
 		interrupts = <0 25 0x4>;
 
 		#dma-cells = <2>;
+		memcpy-channels  = <56 57 58 59 60>;
 		dma-channels = <8>;
 	};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 76c255f..ae462d3 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,6 +58,8 @@
 #define D40_ALLOC_PHY		BIT(30)
 #define D40_ALLOC_LOG_FREE	0
 
+#define D40_MEMCPY_MAX_CHANS	8
+
 /* Reserved event lines for memcpy only. */
 #define DB8500_DMA_MEMCPY_EV_0	51
 #define DB8500_DMA_MEMCPY_EV_1	56
@@ -522,6 +524,8 @@ struct d40_gen_dmac {
  * @phy_start: Physical memory start of the DMA registers.
  * @phy_size: Size of the DMA register map.
  * @irq: The IRQ number.
+ * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
+ * transfers).
  * @num_phy_chans: The number of physical channels. Read from HW. This
  * is the number of available channels for this driver, not counting "Secure
  * mode" allocated physical channels.
@@ -565,6 +569,7 @@ struct d40_base {
 	phys_addr_t			  phy_start;
 	resource_size_t			  phy_size;
 	int				  irq;
+	int				  num_memcpy_chans;
 	int				  num_phy_chans;
 	int				  num_log_chans;
 	struct device_dma_parameters	  dma_parms;
@@ -2938,7 +2943,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 	}
 
 	d40_chan_init(base, &base->dma_memcpy, base->log_chans,
-		      base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
+		      base->num_log_chans, base->num_memcpy_chans);
 
 	dma_cap_zero(base->dma_memcpy.cap_mask);
 	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3139,6 +3144,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	struct d40_base *base = NULL;
 	int num_log_chans = 0;
 	int num_phy_chans;
+	int num_memcpy_chans;
 	int clk_ret = -EINVAL;
 	int i;
 	u32 pid;
@@ -3209,6 +3215,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 	else
 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
 
+	/* The number of channels used for memcpy */
+	if (plat_data->num_of_memcpy_chans)
+		num_memcpy_chans = plat_data->num_of_memcpy_chans;
+	else
+		num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
+
 	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
 
 	dev_info(&pdev->dev,
@@ -3216,7 +3228,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 		 rev, res->start, num_phy_chans, num_log_chans);
 
 	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
-		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
+		       (num_phy_chans + num_log_chans + num_memcpy_chans) *
 		       sizeof(struct d40_chan), GFP_KERNEL);
 
 	if (base == NULL) {
@@ -3226,6 +3238,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 
 	base->rev = rev;
 	base->clk = clk;
+	base->num_memcpy_chans = num_memcpy_chans;
 	base->num_phy_chans = num_phy_chans;
 	base->num_log_chans = num_log_chans;
 	base->phy_start = res->start;
@@ -3469,12 +3482,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
 			       struct device_node *np)
 {
 	struct stedma40_platform_data *pdata;
-
-	/*
-	 * FIXME: Fill in this routine as more support is added.
-	 * First platform enabled (u8500) doens't need any extra
-	 * properties to run, so this is fairly sparce currently.
-	 */
+	int num_memcpy = 0;
+	const const __be32 *list;
 
 	pdata = devm_kzalloc(&pdev->dev,
 			     sizeof(struct stedma40_platform_data),
@@ -3482,6 +3491,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
 	if (!pdata)
 		return -ENOMEM;
 
+	list = of_get_property(np, "memcpy-channels", &num_memcpy);
+	num_memcpy /= sizeof(*list);
+
+	if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
+		d40_err(&pdev->dev,
+			"Invalid number of memcpy channels specified (%d)\n",
+			num_memcpy);
+		return -EINVAL;
+	}
+	pdata->num_of_memcpy_chans = num_memcpy;
+
+	of_property_read_u32_array(np, "memcpy-channels",
+				   dma40_memcpy_channels,
+				   num_memcpy);
+
 	pdev->dev.platform_data = pdata;
 
 	return 0;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index ceba6dc..1bb9b18 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
  * @num_of_soft_lli_chans: The number of channels that needs to be configured
  * to use SoftLLI.
  * @use_esram_lcla: flag for mapping the lcla into esram region
+ * @num_of_memcpy_chans: The number of channels reserved for memcpy.
  * @num_of_phy_chans: The number of physical channels implemented in HW.
  * 0 means reading the number of channels from DMA HW but this is only valid
  * for 'multiple of 4' channels, like 8.
@@ -141,6 +142,7 @@ struct stedma40_platform_data {
 	int				*soft_lli_chans;
 	int				 num_of_soft_lli_chans;
 	bool				 use_esram_lcla;
+	int				 num_of_memcpy_chans;
 	int				 num_of_phy_chans;
 };
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 15 05:52:00 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 15 May 2013 10:52:00 +0100
Subject: [PATCH 37/39] ARM: ux500: Stop passing DMA platform data though
 AUXDATA
In-Reply-To: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368611522-9984-38-git-send-email-lee.jones@linaro.org>

The DMA platform data is now empty due to some recent refactoring,
so there is no longer a requirement to pass it though.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index b407601..3b77e36 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -259,8 +259,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
 		"ux500-msp-i2s.3", &msp3_platform_data),
 	/* Requires clock name bindings and channel address lookup table. */
-	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
-		       "dma40.0", &dma40_plat_data),
+	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
 	{},
 };
 
-- 
1.7.10.4



From nicolas.ferre at atmel.com  Wed May 15 06:08:20 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 12:08:20 +0200
Subject: [PATCH 1/1] ARM: at91: rm9200 fix time support
In-Reply-To: <20130505202025.GE24282@game.jcrosoft.org>
References: <20130505202025.GE24282@game.jcrosoft.org>
Message-ID: <51935E94.2020506@atmel.com>

On 05/05/2013 22:20, Jean-Christophe PLAGNIOL-VILLARD :
> since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488
> Author: Shawn Guo <shawn.guo at linaro.org>
> Date:   Sat Jan 12 11:50:05 2013 +0000
>
> ARM: use clockevents_config_and_register() where possible
>
> The timer is wrongly configured and result in since crash
> so revert it on rm9200 timer

What is strange is that this function is widely used now. So before 
reverting its use for rm9200, we may have to find why it is not working 
properly...

Best regards,

> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
> Hi Greg,
>
> 	if possible apply it to v3.8 and v3.9 stable
>
> 	I'll apply it for mainline
>
> Best Regards,
> J.
>   arch/arm/mach-at91/at91rm9200_time.c |    7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
> index 2acdff4..180b302 100644
> --- a/arch/arm/mach-at91/at91rm9200_time.c
> +++ b/arch/arm/mach-at91/at91rm9200_time.c
> @@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
>   static struct clock_event_device clkevt = {
>   	.name		= "at91_tick",
>   	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.shift		= 32,
>   	.rating		= 150,
>   	.set_next_event	= clkevt32k_next_event,
>   	.set_mode	= clkevt32k_mode,
> @@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void)
>   	at91_st_write(AT91_ST_RTMR, 1);
>
>   	/* Setup timer clockevent, with minimum of two ticks (important!!) */
> +	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
> +	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
> +	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
>   	clkevt.cpumask = cpumask_of(0);
> -	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
> -					2, AT91_ST_ALMV);
> +	clockevents_register_device(&clkevt);
>
>   	/* register clocksource */
>   	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
>


-- 
Nicolas Ferre


From plagnioj at jcrosoft.com  Wed May 15 06:12:33 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 12:12:33 +0200
Subject: [PATCH 1/1] ARM: at91: rm9200 fix time support
Message-ID: <1368612753-32565-1-git-send-email-plagnioj@jcrosoft.com>

since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488
Author: Shawn Guo <shawn.guo at linaro.org>
Date:   Sat Jan 12 11:50:05 2013 +0000

ARM: use clockevents_config_and_register() where possible

The timer is wrongly configured and result in a nice crash
so revert it on rm9200 timer

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: stable <stable at vger.kernel.org> # 3.8+
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/at91rm9200_time.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 2acdff4..180b302 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 static struct clock_event_device clkevt = {
 	.name		= "at91_tick",
 	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.shift		= 32,
 	.rating		= 150,
 	.set_next_event	= clkevt32k_next_event,
 	.set_mode	= clkevt32k_mode,
@@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void)
 	at91_st_write(AT91_ST_RTMR, 1);
 
 	/* Setup timer clockevent, with minimum of two ticks (important!!) */
+	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
+	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
+	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
 	clkevt.cpumask = cpumask_of(0);
-	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
-					2, AT91_ST_ALMV);
+	clockevents_register_device(&clkevt);
 
 	/* register clocksource */
 	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
-- 
1.7.10.4



From josephl at nvidia.com  Wed May 15 06:27:18 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:18 +0800
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
Message-ID: <1368613644-11863-1-git-send-email-josephl@nvidia.com>

Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
as CPU core and a enhanced flow controller for CPU power control. So
we need to skip some code that was for Contex-A9 and some other support
code that was for other Tegra SoC chips. Then adding the proper power up
and hot plug control for Tegra114.

Joseph Lo (6):
  ARM: tegra: add an assembly marco to check Tegra SoC ID
  ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
  ARM: tegra: make tegra_resume can work for Tegra114
  ARM: tegra114: add power up sequence for warm boot CPU
  clk: tegra114: implement wait_for_reset and disable_clock for
    tegra_cpu_car_ops
  ARM: tegra114: add CPU hotplug support

 arch/arm/mach-tegra/Makefile        |  1 +
 arch/arm/mach-tegra/flowctrl.h      |  1 +
 arch/arm/mach-tegra/fuse.h          | 22 +++++++++---------
 arch/arm/mach-tegra/hotplug.c       |  2 ++
 arch/arm/mach-tegra/platsmp.c       | 25 ++++++++++++++++++++-
 arch/arm/mach-tegra/reset-handler.S | 45 ++++++++++++++++++++-----------------
 arch/arm/mach-tegra/sleep-tegra30.S | 27 ++++++++++++++++++----
 arch/arm/mach-tegra/sleep.S         |  8 ++++---
 arch/arm/mach-tegra/sleep.h         | 35 ++++++++++++++++++++++++-----
 drivers/clk/tegra/clk-tegra114.c    | 23 ++++++++++++++++++-
 10 files changed, 143 insertions(+), 46 deletions(-)

-- 
1.8.2.2



From josephl at nvidia.com  Wed May 15 06:27:19 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:19 +0800
Subject: [PATCH 1/6] ARM: tegra: add an assembly marco to check Tegra SoC ID
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <1368613644-11863-2-git-send-email-josephl@nvidia.com>

There are some Tegra SoC ID checking code around the low level assembly
code. Adding a marco to replace them. For the single image to support all
the Tegra series, we may also need the marco in other common code. So we
make it become a marco for the usage.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/fuse.h          | 22 ++++++++++++----------
 arch/arm/mach-tegra/reset-handler.S | 24 +++++++-----------------
 arch/arm/mach-tegra/sleep.h         |  9 +++++++++
 3 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d..def7968 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
 #ifndef __MACH_TEGRA_FUSE_H
 #define __MACH_TEGRA_FUSE_H
 
-enum tegra_revision {
-	TEGRA_REVISION_UNKNOWN = 0,
-	TEGRA_REVISION_A01,
-	TEGRA_REVISION_A02,
-	TEGRA_REVISION_A03,
-	TEGRA_REVISION_A03p,
-	TEGRA_REVISION_A04,
-	TEGRA_REVISION_MAX,
-};
-
 #define SKU_ID_T20	8
 #define SKU_ID_T25SE	20
 #define SKU_ID_AP25	23
@@ -40,6 +30,17 @@ enum tegra_revision {
 #define TEGRA30		0x30
 #define TEGRA114	0x35
 
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+	TEGRA_REVISION_UNKNOWN = 0,
+	TEGRA_REVISION_A01,
+	TEGRA_REVISION_A02,
+	TEGRA_REVISION_A03,
+	TEGRA_REVISION_A03p,
+	TEGRA_REVISION_A04,
+	TEGRA_REVISION_MAX,
+};
+
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
 #else
 static inline void tegra114_init_speedo_data(void) {}
 #endif
+#endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a..525f1b9 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
 #include <asm/hardware/cache-l2x0.h>
 
 #include "flowctrl.h"
+#include "fuse.h"
 #include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
 
-#define APB_MISC_GP_HIDREV	0x804
 #define PMC_SCRATCH41	0x140
 
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
@@ -49,10 +49,7 @@ ENTRY(tegra_resume)
 
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 	/* Are we on Tegra20? */
-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r0, [r6, #APB_MISC_GP_HIDREV]
-	and	r0, r0, #0xff00
-	cmp	r0, #(0x20 << 8)
+	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r7
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
 	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
@@ -115,13 +112,9 @@ ENTRY(__tegra_cpu_reset_handler)
 
 	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
 
-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
-	and	r6, r6, #0xff00
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-t20_check:
-	cmp	r6, #(0x20 << 8)
+	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r5
 	bne	after_t20_check
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 t20_errata:
 	# Tegra20 is a Cortex-A9 r1p1
 	mrc	p15, 0, r0, c1, c0, 0   @ read system control register
@@ -132,8 +125,8 @@ t20_errata:
 	orr	r0, r0, #1 << 11        @ erratum 751472
 	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
 	b	after_errata
-after_t20_check:
 #endif
+after_t20_check:
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 t30_check:
 	cmp	r6, #(0x30 << 8)
@@ -163,7 +156,7 @@ after_errata:
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
-	cmp	r6, #(0x20 << 8)
+	cmp	r6, #(TEGRA20 << 8)
 	bne	1f
 	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
 	mov32	r5, TEGRA_PMC_BASE
@@ -210,10 +203,7 @@ __die:
 	mov32	r7, TEGRA_CLK_RESET_BASE
 
 	/* Are we on Tegra20? */
-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r0, [r6, #APB_MISC_GP_HIDREV]
-	and	r0, r0, #0xff00
-	cmp	r0, #(0x20 << 8)
+	cmp	r6, #(TEGRA20 << 8)
 	bne	1f
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb1..7e9c9fe 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -85,6 +85,15 @@
 	dsb
 .endm
 
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV	0x804
+.macro tegra_check_soc_id rev, base, tmp1, tmp2
+	mov32	\tmp2, \base
+	ldr	\tmp1, [\tmp2, #APB_MISC_GP_HIDREV]
+	and	\tmp1, \tmp1, #0xff00
+	cmp	\tmp1, #(\rev << 8)
+.endm
+
 /* Macro to resume & re-enable L2 cache */
 #ifndef L2X0_CTRL_EN
 #define L2X0_CTRL_EN	1
-- 
1.8.2.2



From josephl at nvidia.com  Wed May 15 06:27:20 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:20 +0800
Subject: [PATCH 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not
 Cortex-A9
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <1368613644-11863-3-git-send-email-josephl@nvidia.com>

For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/sleep.S |  8 +++++---
 arch/arm/mach-tegra/sleep.h | 24 ++++++++++++++++++------
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d845..9daaef2 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
 	isb
 #ifdef CONFIG_CACHE_L2X0
 	/* Disable L2 cache */
-	mov32	r4, TEGRA_ARM_PERIF_BASE + 0x3000
-	mov	r5, #0
-	str	r5, [r4, #L2X0_CTRL]
+	check_cpu_part_num 0xc09, r9, r10
+	movweq	r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+	movteq	r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+	moveq	r5, #0
+	streq	r5, [r4, #L2X0_CTRL]
 #endif
 	mov	pc, r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 7e9c9fe..c2cac9a 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -70,19 +70,31 @@
 	movt	\reg, #:upper16:\val
 .endm
 
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+	mrc	p15, 0, \tmp1, c0, c0, 0
+	ubfx	\tmp1, \tmp1, #4, #12
+	mov32	\tmp2, \part_num
+	cmp	\tmp1, \tmp2
+.endm
+
 /* Macro to exit SMP coherency. */
 .macro exit_smp, tmp1, tmp2
 	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
 	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
 	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
 	isb
-	cpu_id	\tmp1
-	mov	\tmp1, \tmp1, lsl #2
-	mov	\tmp2, #0xf
-	mov	\tmp2, \tmp2, lsl \tmp1
-	mov32	\tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
-	str	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+	check_cpu_part_num 0xc09, \tmp1, \tmp2
+	mrceq	p15, 0, \tmp1, c0, c0, 5
+	andeq	\tmp1, \tmp1, #0xF
+	moveq	\tmp1, \tmp1, lsl #2
+	moveq	\tmp2, #0xf
+	moveq	\tmp2, \tmp2, lsl \tmp1
+	ldreq	\tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+	streq	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
 	dsb
+#endif
 .endm
 
 /* Macro to check Tegra revision */
-- 
1.8.2.2



From josephl at nvidia.com  Wed May 15 06:27:21 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:21 +0800
Subject: [PATCH 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <1368613644-11863-4-git-send-email-josephl@nvidia.com>

Tegra114 is an ARM Cortex-A15 based SoC and some of the flow controller
hardware behavior and configurations are different with other Tegra series.
We fix the common resume function of tegra_resume to make it can work on
Tegra114 by checking SoC ID. And also checking CPU primary part number to
isolate the support code for Cortex A9 and A15.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/reset-handler.S | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 525f1b9..893f6b7 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -47,22 +47,25 @@ ENTRY(tegra_resume)
  THUMB(	it	ne )
 	bne	cpu_resume			@ no
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
 	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r7
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
-	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
-	ldr	r1, [r2]
+	cpu_to_csr_req r1, r0
+	mov32	r2, TEGRA_FLOW_CTRL_BASE
+	ldr	r1, [r2, r1]
 	/* Clear event & intr flag */
 	orr	r1, r1, \
 		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
+	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, & bitmaps
 	bic	r1, r1, r0
 	str	r1, [r2]
 1:
 #endif
 
+	check_cpu_part_num 0xc09, r8, r9
+	bne	not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
 	/* enable SCU */
 	mov32	r0, TEGRA_ARM_PERIF_BASE
@@ -73,6 +76,7 @@ ENTRY(tegra_resume)
 
 	/* L2 cache resume & re-enable */
 	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
 
 	b	cpu_resume
 ENDPROC(tegra_resume)
-- 
1.8.2.2



From josephl at nvidia.com  Wed May 15 06:27:22 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:22 +0800
Subject: [PATCH 4/6] ARM: tegra114: add power up sequence for warm boot CPU
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <1368613644-11863-5-git-send-email-josephl@nvidia.com>

For Tegra114, once the CPUs were powered up by PMC in cold boot flow. The
flow controller will maintain the power state and control power sequence
for each CPU by setting event trigger (e.g. CPU hotplug ,idle and
suspend power down/up).

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/flowctrl.h |  1 +
 arch/arm/mach-tegra/platsmp.c  | 25 ++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56..7a29bae 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
 #define FLOW_CTRL_WAITEVENT		(2 << 29)
 #define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
 #define FLOW_CTRL_JTAG_RESUME		(1 << 28)
+#define FLOW_CTRL_SCLK_RESUME		(1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
 #define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
 #define FLOW_CTRL_CPU0_CSR		0x8
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226..554aedc 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -140,8 +140,31 @@ remove_clamps:
 
 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+	int ret = 0;
+
 	cpu = cpu_logical_map(cpu);
-	return tegra_pmc_cpu_power_on(cpu);
+
+	if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+		/*
+		 * Warm boot flow
+		 * The flow controller in charge of the power state and
+		 * control for each CPU.
+		 */
+		/* set SCLK as event trigger for flow controller */
+		flowctrl_write_cpu_csr(cpu, 1);
+		flowctrl_write_cpu_halt(cpu,
+				FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+	} else {
+		/*
+		 * Cold boot flow
+		 * The CPU is powered up by toggling PMC directly. It will
+		 * also initial power state in flow controller. After that,
+		 * the CPU's power state is maintained by flow controller.
+		 */
+		ret = tegra_pmc_cpu_power_on(cpu);
+	}
+
+	return ret;
 }
 
 static int __cpuinit tegra_boot_secondary(unsigned int cpu,
-- 
1.8.2.2



From josephl at nvidia.com  Wed May 15 06:27:23 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:23 +0800
Subject: [PATCH 5/6] clk: tegra114: implement wait_for_reset and disable_clock
 for tegra_cpu_car_ops
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <1368613644-11863-6-git-send-email-josephl@nvidia.com>

The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.

Cc: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..40d939d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 #define CLK_SOURCE_EMC 0x19c
 
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 	}
 }
 
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+	/* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+	.wait_for_reset	= tegra114_wait_cpu_in_reset,
+	.disable_clock	= tegra114_disable_cpu_clock,
+};
 
 static const struct of_device_id pmc_match[] __initconst = {
 	{ .compatible = "nvidia,tegra114-pmc" },
-- 
1.8.2.2



From josephl at nvidia.com  Wed May 15 06:27:24 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 May 2013 18:27:24 +0800
Subject: [PATCH 6/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <1368613644-11863-7-git-send-email-josephl@nvidia.com>

The Tegra114 is a quad cores SoC. Each core can be hotplugged including
CPU0. The hotplug sequence can be controlled by setting event trigger in
flow controller. Then the flow controller will take care all the power
sequence that include CPU up and down.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/Makefile        |  1 +
 arch/arm/mach-tegra/hotplug.c       |  2 ++
 arch/arm/mach-tegra/reset-handler.S | 11 ++++++++++-
 arch/arm/mach-tegra/sleep-tegra30.S | 27 +++++++++++++++++++++++----
 arch/arm/mach-tegra/sleep.h         |  2 ++
 5 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0a..98b184e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= sleep-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a..d07f152 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -55,4 +55,6 @@ void __init tegra_hotplug_init(void)
 		tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
 		tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+	if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+		tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 893f6b7..5af3a7d 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -38,18 +38,24 @@
  *	  CPU boot vector when restarting the a CPU following
  *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
  *	  re-enabling sdram.
+ *
+ *	r6: SoC ID << 8
  */
 ENTRY(tegra_resume)
 	bl	v7_invalidate_l1
 
 	cpu_id	r0
+	tegra_check_soc_id TEGRA114, TEGRA_APB_MISC_BASE, r6, r7
+	beq	no_cpu0_chk
+
 	cmp	r0, #0				@ CPU0?
  THUMB(	it	ne )
 	bne	cpu_resume			@ no
+no_cpu0_chk:
 
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
-	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r7
+	cmp	r6, #(TEGRA20 << 8)
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
 	cpu_to_csr_req r1, r0
@@ -186,8 +192,11 @@ __is_not_lp2:
 	 * Can only be secondary boot (initial or hotplug) but CPU 0
 	 * cannot be here.
 	 */
+	cmp	r6, #(TEGRA114 <<8)
+	beq	__no_cpu0_chk
 	cmp	r10, #0
 	bleq	__die				@ CPU0 cannot be here
+__no_cpu0_chk:
 	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
 	cmp	lr, #0
 	bleq	__die				@ no secondary startup handler
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcc..ae36fbb 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 
+#include "fuse.h"
 #include "sleep.h"
 #include "flowctrl.h"
 
@@ -45,12 +46,17 @@ ENDPROC(tegra30_hotplug_shutdown)
  * and powergates it -- flags (in R0) indicate the request type.
  * Must never be called for CPU 0.
  *
- * corrupts r0-r4, r12
+ * r10 = SoC ID << 8
+ * corrupts r0-r4, r10-r12
  */
 ENTRY(tegra30_cpu_shutdown)
 	cpu_id	r3
+	tegra_check_soc_id TEGRA30, TEGRA_APB_MISC_VIRT, r10, r11
+	bne	_no_cpu0_chk	@ It's not Tegra30
+
 	cmp	r3, #0
 	moveq	pc, lr		@ Must never be called for CPU 0
+_no_cpu0_chk:
 
 	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
 	cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
 	movw	r12, \
 		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
 		FLOW_CTRL_CSR_ENABLE
-	mov	r4, #(1 << 4)
+	cmp	r10, #(TEGRA30 << 8)
+	moveq	r4, #(1 << 4)			@ wfe bitmap
+	movne	r4, #(1 << 8)			@ wfi bitmap
  ARM(	orr	r12, r12, r4, lsl r3	)
  THUMB(	lsl	r4, r4, r3		)
  THUMB(	orr	r12, r12, r4		)
@@ -79,9 +87,19 @@ delay_1:
 	cpsid	a				@ disable imprecise aborts.
 	ldr	r3, [r1]			@ read CSR
 	str	r3, [r1]			@ clear CSR
+
 	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	beq	flow_ctrl_setting_for_lp2
+
+	/* flow controller set up for hotplug */
+	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+	b	flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+	/* flow controller set up for LP2 */
+	cmp	r10, #(TEGRA30 << 8)
 	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
-	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+flow_ctrl_done:
+	cmp	r10, #(TEGRA30 << 8)
 	str	r3, [r2]
 	ldr	r0, [r2]
 	b	wfe_war
@@ -89,7 +107,8 @@ delay_1:
 __cpu_reset_again:
 	dsb
 	.align 5
-	wfe					@ CPU should be power gated here
+	wfeeq					@ CPU should be power gated here
+	wfine
 wfe_war:
 	b	__cpu_reset_again
 
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index c2cac9a..92a3f0c 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
 					+ IO_PPSB_VIRT)
 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+					+ IO_APB_VIRT)
 #define TEGRA_PMC_VIRT	(TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
 
 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
-- 
1.8.2.2



From nicolas.ferre at atmel.com  Wed May 15 06:36:02 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 12:36:02 +0200
Subject: [PATCH 1/1] ARM: at91: rm9200 fix time support
In-Reply-To: <1368612753-32565-1-git-send-email-plagnioj@jcrosoft.com>
References: <1368612753-32565-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <51936512.9020400@atmel.com>

On 15/05/2013 12:12, Jean-Christophe PLAGNIOL-VILLARD :
> since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488
> Author: Shawn Guo <shawn.guo at linaro.org>
> Date:   Sat Jan 12 11:50:05 2013 +0000
>
> ARM: use clockevents_config_and_register() where possible
>
> The timer is wrongly configured and result in a nice crash
> so revert it on rm9200 timer
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: stable <stable at vger.kernel.org> # 3.8+
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>

Ok, even if I said that it would have been better to understand the root 
cause of this, it is also true that we have to move forward in the 
meantime...

So, yes, I take it for at91-3.10-fixes:

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks,


> ---
>   arch/arm/mach-at91/at91rm9200_time.c |    7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
> index 2acdff4..180b302 100644
> --- a/arch/arm/mach-at91/at91rm9200_time.c
> +++ b/arch/arm/mach-at91/at91rm9200_time.c
> @@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
>   static struct clock_event_device clkevt = {
>   	.name		= "at91_tick",
>   	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.shift		= 32,
>   	.rating		= 150,
>   	.set_next_event	= clkevt32k_next_event,
>   	.set_mode	= clkevt32k_mode,
> @@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void)
>   	at91_st_write(AT91_ST_RTMR, 1);
>
>   	/* Setup timer clockevent, with minimum of two ticks (important!!) */
> +	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
> +	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
> +	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
>   	clkevt.cpumask = cpumask_of(0);
> -	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
> -					2, AT91_ST_ALMV);
> +	clockevents_register_device(&clkevt);
>
>   	/* register clocksource */
>   	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
>


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Wed May 15 06:45:47 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 15 May 2013 12:45:47 +0200
Subject: [GIT PULL] at91: fixes for 3.10 #1
Message-ID: <1368614747-1737-1-git-send-email-nicolas.ferre@atmel.com>

Arnd, Olof,

This is the first AT91 fixes pull-request for 3.10-rc.

Thanks, best regards,

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-fixes

for you to fetch changes up to b7a8ca5173ef9aa55fa039d7c216426ff0b25a12:

  ARM: at91: rm9200 fix time support (2013-05-15 12:37:45 +0200)

----------------------------------------------------------------
An important revert on at91rm9200 platform related
to timers that prevented the platform to boot properly.
Then one pinctrl adjustments for SPI CS and a couple of
trivial typos.

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (2):
      ARM: at91/trivial: fix model name for SAM9X25-EK
      ARM: at91: rm9200 fix time support

Ludovic Desroches (1):
      ARM: at91: dts: request only spi cs-gpios used on sama5d3x cpu module

Nicolas Ferre (1):
      ARM: at91/trivial: typo in GEM compatible string

 Documentation/devicetree/bindings/net/macb.txt |  2 +-
 arch/arm/boot/dts/at91sam9x25ek.dts            |  2 +-
 arch/arm/boot/dts/sama5d3.dtsi                 | 12 +-----------
 arch/arm/boot/dts/sama5d3xcm.dtsi              |  4 ++++
 arch/arm/mach-at91/at91rm9200_time.c           |  7 +++++--
 5 files changed, 12 insertions(+), 15 deletions(-)

-- 
Nicolas Ferre


From tomi.valkeinen at iki.fi  Wed May 15 06:53:58 2013
From: tomi.valkeinen at iki.fi (Tomi Valkeinen)
Date: Wed, 15 May 2013 13:53:58 +0300
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <1366697656-14315-1-git-send-email-kishon@ti.com>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
Message-ID: <51936946.3030507@iki.fi>

On 23/04/13 09:14, Kishon Vijay Abraham I wrote:
> After the device names are created using PLATFORM_DEVID_AUTO, the old
> device names given in usb_bind_phy are no longer valid causing the musb
> controller not to get the phy reference. Updated the usb_bind_phy with
> the new device names to get MUSB functional in omap4 panda.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
> Tested in OMAP4 PANDA.
>  arch/arm/mach-omap2/board-4430sdp.c    |    2 +-
>  arch/arm/mach-omap2/board-omap4panda.c |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
> index 00d7290..56a9a4f 100644
> --- a/arch/arm/mach-omap2/board-4430sdp.c
> +++ b/arch/arm/mach-omap2/board-4430sdp.c
> @@ -730,7 +730,7 @@ static void __init omap_4430sdp_init(void)
>  	omap4_sdp4430_wifi_init();
>  	omap4_twl6030_hsmmc_init(mmc);
>  
> -	usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
> +	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
>  	usb_musb_init(&musb_board_data);
>  
>  	status = omap_ethernet_init();

I'm seeing

[    2.190155] unable to find transceiver
[    2.190155] HS USB OTG: no transceiver configured
[    2.190155] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed
with status -517
[    2.207458] platform musb-hdrc.0.auto: Driver musb-hdrc requests
probe deferral

on 4430sdp with v3.10-rc1. Does that mean that the musb-hdrc.0.auto was
indeed correct, and the new value of musb-hdrc.2.auto is not?

The musb-hdrc id is wrong on overo also.

 Tomi



From jonas.jensen at gmail.com  Wed May 15 07:20:29 2013
From: jonas.jensen at gmail.com (Jonas Jensen)
Date: Wed, 15 May 2013 13:20:29 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <201303181503.49491.arnd@arndb.de>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201303151125.53999.arnd@arndb.de>
 <CACmBeS3aXs9vhc5ZYPbz5bjsYsSa6EzM12H4uPv706x0zU_5iw@mail.gmail.com>
 <201303181503.49491.arnd@arndb.de>
Message-ID: <CACmBeS1empYyoaKidgTrYwUFCw447OKndxZjT98TvYfKVWB00A@mail.gmail.com>

Hi,

.. it's been a while ..

This is now rebased for 3.10 and DT thanks to help from #armlinux on
Freenode. It should tick the boxes in the list from Arnd.

I'm only posting changes in arch/arm/* and will continue submitting
drivers separately as requested, this applies to next-20130515.

The full repository is available @
https://code.google.com/p/linux-3-9-rc3-moxart/source/list

Note: no boot without clocksource and irqchip drivers (I'll submit
these separately to the correct maintainers).

Also it won't boot without reverting the following commit:
e651eab0af88aa7a281fe9e8c36c0846552aa7fc - "ARM: 7677/1: LPAE: Fix
mapping in alloc_init_section for unaligned addresses"

Best regards,
Jonas


Signed-off-by: Jonas Jensen <jonas.jensen at gmail.com>
---
 arch/arm/Kconfig                           |    2 +
 arch/arm/Kconfig.debug                     |   10 +++
 arch/arm/Makefile                          |    1 +
 arch/arm/boot/dts/Makefile                 |    1 +
 arch/arm/boot/dts/moxart-uc7112lx.dts      |   90 ++++++++++++++++++++++
 arch/arm/boot/dts/moxart.dtsi              |   71 +++++++++++++++++
 arch/arm/configs/moxart_uc7112lx_defconfig |  113 ++++++++++++++++++++++++++++
 arch/arm/include/debug/moxart.S            |   14 ++++
 arch/arm/mach-moxart/Kconfig               |   34 ++++++++
 arch/arm/mach-moxart/Makefile              |   12 +++
 arch/arm/mach-moxart/Makefile.boot         |    3 +
 arch/arm/mach-moxart/idle.c                |   31 ++++++++
 arch/arm/mach-moxart/moxart.c              |   42 ++++++++++
 arch/arm/mach-moxart/moxart.h              |   11 +++
 14 files changed, 435 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7b7ab65..eba7935 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -938,6 +938,8 @@ source "arch/arm/mach-footbridge/Kconfig"

 source "arch/arm/mach-gemini/Kconfig"

+source "arch/arm/mach-moxart/Kconfig"
+
 source "arch/arm/mach-highbank/Kconfig"

 source "arch/arm/mach-integrator/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 29f7623..d534fce 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -429,6 +429,15 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on Allwinner A1X based platforms on the UART1.

+	config DEBUG_MOXART_UART0
+        bool "Kernel low-level debugging messages via MOXART UART0"
+        depends on ARCH_MOXART
+        help
+          Say Y here if you want kernel low-level debugging support
+          on MOXART based platforms on the UART0.
+          select this to make sure "putc" in arch/arm/boot/compressed/debug.S
+          uses arch/arm/include/debug/moxart.S:s "addruart" macro
+
 	config DEBUG_TEGRA_UART
 		depends on ARCH_TEGRA
 		bool "Use Tegra UART for low-level debug"
@@ -651,6 +660,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
 	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
 	default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
+	default "debug/moxart.S" if DEBUG_MOXART_UART0
 	default "debug/tegra.S" if DEBUG_TEGRA_UART
 	default "debug/ux500.S" if DEBUG_UX500_UART
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 3380c4f..2e964a9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -148,6 +148,7 @@ machine-$(CONFIG_ARCH_DOVE)		+= dove
 machine-$(CONFIG_ARCH_EBSA110)		+= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		+= gemini
+machine-$(CONFIG_ARCH_MOXART)       += moxart
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)	+= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		+= iop13xx
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 87e603c..8fbd32d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
 	wm8650-mid.dtb \
 	wm8850-w70v2.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
+dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb

 targets += dtbs
 targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts
b/arch/arm/boot/dts/moxart-uc7112lx.dts
new file mode 100644
index 0000000..44d4e33
--- /dev/null
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -0,0 +1,90 @@
+/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
+ *
+ * Copyright (C) 2013 Jonas Jensen <jonas.jensen at gmail.com>
+ *
+ * Licensed under GPLv2 or later. */
+
+/dts-v1/;
+/include/ "moxart.dtsi"
+
+/ {
+	model = "MOXA UC-7112-LX";
+	compatible = "moxart,moxart-uc-7112-lx";
+
+	memory {
+		reg = <0x00000000 0x02000000>;
+	};
+
+	flash at 80000000,0 {
+		/* JS28F128 J3D75 A9087684 - Numonyx? Embedded Flash Memory (J3 v. D) */
+		compatible = "numonyx,js28f128", "cfi-flash";
+		reg = <0x80000000 0x01000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition at 0 {
+			label = "bootloader";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition at 40000 {
+			label = "linux kernel";
+			reg = <0x00040000 0x001C0000>;
+		};
+		partition at 200000 {
+			label = "root filesystem";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition at a00000 {
+			label = "user filesystem";
+			reg = <0x00a00000 0x00600000>;
+		};
+	};
+
+	mmc at 98e00000 {
+		compatible = "moxart,moxart-mmc";
+		reg =	<0x98e00000 0x00001000>,
+				<0x98100000 0x1000>;		/* PMU */
+		interrupts = <5 0>;
+	};
+
+	mxser at 98200040 {
+		compatible = "moxart,moxart-mxser";
+		reg =	<0x98200040 0x00000080>,	/* UART "3" base */
+				<0x982000e4 0x00000080>,	/* UART mode base */
+				<0x982000c0 0x00000020>;	/* UART interrupt vector */
+		interrupts = <31 1>;
+	};
+
+	mac0: mac at 90900000 {
+		compatible = "moxart,moxart-mac0";
+		reg =   <0x90900000 0x1000>,
+				<0x80000000 0x01000000>;	/* MAC address stored on flash */
+		interrupts = <25 0>;
+		flash-offset = <0x50>;
+	};
+
+	mac1: mac at 92000000 {
+		compatible = "moxart,moxart-mac1";
+		reg =   <0x92000000 0x1000>,
+				<0x80000000 0x01000000>;	/* MAC address stored on flash */
+		interrupts = <27 0>;
+		flash-offset = <0x56>;
+	};
+
+	uart0: uart at 98200000 {
+		compatible = "ns16550a";
+		reg = <0x98200000 0x20>;
+		interrupts = <31 0>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		clock-frequency = <14745600>;
+		status = "okay";
+	};
+
+	chosen {
+		/* uncomment to use on board flash root
+		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw";
+		*/
+		bootargs = "console=ttyS0,115200n8 root=/dev/mmcblk0p1 rw rootwait";
+	};
+};
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
new file mode 100644
index 0000000..56743bc
--- /dev/null
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -0,0 +1,71 @@
+/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
+ *
+ * Copyright (C) 2013 Jonas Jensen <jonas.jensen at gmail.com>
+ *
+ * Licensed under GPLv2 or later. */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "faraday,fa526";
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x90000000 0x10000000>;
+		ranges;
+
+		intc: interrupt-controller at 98800000 {
+			compatible = "moxart,moxart-interrupt-controller";
+			reg = <0x98800000 0x38>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-mask = <0x00080000>;		/* single register vector,
interrupts 0-31, 1s signify edge */
+		};
+
+		timer0: timer at 98400000 {
+			compatible = "moxart,moxart-timer0";
+			reg = <0x98400000 0x10>;
+			interrupts = <19 1>;
+		};
+
+		gpio: gpio at 98700000 {
+			compatible = "moxart,moxart-gpio";
+			reg =	<0x98700000 0x1000>,
+					<0x98100000 0x1000>;		/* PMU */
+		};
+
+		rtc: rtc {
+			compatible = "moxart,moxart-rtc";
+		};
+
+		dma: dma at 90500000 {
+			compatible = "moxart,moxart-dma";
+			reg = <0x90500000 0x1000>;
+			interrupts = <24 0>;
+		};
+
+		watchdog: watchdog at 98500000 {
+			compatible = "moxart,moxart-watchdog";
+			reg = <0x98500000 0x1000>;
+		};
+	};
+};
diff --git a/arch/arm/configs/moxart_uc7112lx_defconfig
b/arch/arm/configs/moxart_uc7112lx_defconfig
new file mode 100644
index 0000000..7c40502
--- /dev/null
+++ b/arch/arm/configs/moxart_uc7112lx_defconfig
@@ -0,0 +1,113 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_MOXART=y
+CONFIG_MACH_UC7112LX=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ATAGS is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_ARM_MOXART_ETHER=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_MOXA_SMARTIO=y
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIO_MOXART=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_MOXART_WDT=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI_MOXART=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MOXART=y
+CONFIG_DMADEVICES=y
+CONFIG_MOXART_DMA=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT3_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_PROVE_LOCKING=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_KEYS=y
diff --git a/arch/arm/include/debug/moxart.S b/arch/arm/include/debug/moxart.S
new file mode 100644
index 0000000..01e2aee
--- /dev/null
+++ b/arch/arm/include/debug/moxart.S
@@ -0,0 +1,14 @@
+/* Copyright (C) 2013 Jonas Jensen <jonas.jensen at gmail.com>
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version. */
+
+#define MOXART_UART_DEBUG_PHYS_BASE		0x98200000
+
+.macro	addruart, rp, rv, tmp
+	ldr	\rp, =MOXART_UART_DEBUG_PHYS_BASE	@ physical
+.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
new file mode 100644
index 0000000..e19934c
--- /dev/null
+++ b/arch/arm/mach-moxart/Kconfig
@@ -0,0 +1,34 @@
+config ARCH_MOXART
+	bool "MOXA ART SoC" if (ARCH_MULTI_V4)
+	select ARCH_REQUIRE_GPIOLIB
+	select USE_OF
+	help
+	  Say Y here if you want to run your kernel on hardware
+	  with a MOXA ART SoC.
+	  These are DIN-rail / wall-mountable embedded PCs sold by MOXA.
+	  http://www.moxa.com/product/Embedded_Computers.htm
+
+config SOC_MOXART
+	bool "MOXART support"
+	depends on ARCH_MOXART
+	default y
+	select CPU_FA526
+	select ARM_DMA_MEM_BUFFERABLE
+	help
+	  Support for the MOXA ART SoC. This is a Faraday FA526 ARMv4 32-bit
192 MHz processor with MMU and 16KB/8KB D/I-cache (UC-7112-LX)
+	  This perticular SoC is used on models UC-7101, UC-7112/UC-7110,
IA240/IA241, IA3341.
+	  These are DIN-rail / wall-mountable embedded PCs sold by MOXA (
http://www.moxa.com/product/Embedded_Computers.htm ).
+
+if ARCH_MOXART
+
+menu "MOXA ART SoC Implementation"
+
+config MACH_UC7112LX
+	bool "MOXA UC-7112-LX"
+	depends on ARCH_MOXART && SOC_MOXART
+	help
+	  Say Y here if you intend to run this kernel on a MOXA UC-7112-LX
embedded computer.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-moxart/Makefile b/arch/arm/mach-moxart/Makefile
new file mode 100644
index 0000000..b4a1923
--- /dev/null
+++ b/arch/arm/mach-moxart/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for the linux kernel.
+#
+
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
+# Object file lists.
+
+obj-y          := idle.o
+
+obj-$(CONFIG_MACH_UC7112LX)	+= moxart.o
+
diff --git a/arch/arm/mach-moxart/Makefile.boot
b/arch/arm/mach-moxart/Makefile.boot
new file mode 100644
index 0000000..760a0ef
--- /dev/null
+++ b/arch/arm/mach-moxart/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y	+= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000
diff --git a/arch/arm/mach-moxart/idle.c b/arch/arm/mach-moxart/idle.c
new file mode 100644
index 0000000..5970c27
--- /dev/null
+++ b/arch/arm/mach-moxart/idle.c
@@ -0,0 +1,31 @@
+/* Copyright (C) 2013 Jonas Jensen <jonas.jensen at gmail.com>
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version. */
+
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/proc-fns.h>
+
+static void moxart_idle(void)
+{
+	/*
+	 * Because of broken hardware we have to enable interrupts or the CPU
+	 * will never wakeup... Acctualy it is not very good to enable
+	 * interrupts first since scheduler can miss a tick, but there is
+	 * no other way around this. Platforms that needs it for power saving
+	 * should call enable_hlt() in init code, since by default it is
+	 * disabled.
+	 */
+/*	local_irq_enable();
+	cpu_do_idle();*/
+}
+
+static int __init moxart_idle_init(void)
+{
+	arm_pm_idle = moxart_idle;
+	return 0;
+}
+
+arch_initcall(moxart_idle_init);
diff --git a/arch/arm/mach-moxart/moxart.c b/arch/arm/mach-moxart/moxart.c
new file mode 100644
index 0000000..4c89a21
--- /dev/null
+++ b/arch/arm/mach-moxart/moxart.c
@@ -0,0 +1,42 @@
+/* Copyright (C) 2013 Jonas Jensen <jonas.jensen at gmail.com>
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version. */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+
+#include "moxart.h"
+
+static void __init moxart_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+void moxart_restart(char mode, const char *cmd)
+{
+	writel(1, reg_wdt + 4);
+	writel(0x5ab9, reg_wdt + 8);
+	writel(0x03, reg_wdt + 12);
+}
+
+static const char * const moxart_board_dt_compat[] = {
+	"moxart,moxart-uc-7112-lx",
+	NULL,
+};
+
+DT_MACHINE_START(MOXART, "MOXA UC-7112-LX")
+	.init_irq		= moxart_init_irq,
+	.init_time		= moxart_timer_init,
+	.init_machine	= moxart_init,
+	.handle_irq		= moxart_handle_irq,
+	.restart        = moxart_restart,
+	.dt_compat		= moxart_board_dt_compat,
+	.nr_irqs		= 32,
+MACHINE_END
+
diff --git a/arch/arm/mach-moxart/moxart.h b/arch/arm/mach-moxart/moxart.h
new file mode 100644
index 0000000..255ad85
--- /dev/null
+++ b/arch/arm/mach-moxart/moxart.h
@@ -0,0 +1,11 @@
+/* Copyright (C) 2013 Jonas Jensen <jonas.jensen at gmail.com>
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version. */
+
+extern __iomem void *reg_wdt;
+extern void moxart_timer_init(void);
+extern void moxart_init_irq(void);
+extern void moxart_handle_irq(struct pt_regs *regs);
+


From linus.walleij at linaro.org  Wed May 15 07:27:25 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 13:27:25 +0200
Subject: [PATCH v2] pinctrl:sirf:re-arch and add support for new
 SiRFatlas6 SoC
In-Reply-To: <1368541078-6002-1-git-send-email-Baohua.Song@csr.com>
References: <1368541078-6002-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <CACRpkdZS36n=4fCjnSmo5UFKgMExA=iUt6565M1ZvM0Qym5XGA@mail.gmail.com>

On Tue, May 14, 2013 at 4:17 PM, Barry Song <21cnbao at gmail.com> wrote:

> atlas6 is a SoC very similar with primaII, the register layput of
> pinctrl is same, but the pads, groups and functions of atlas6 have
> different layout with prima2, this patch
> 1. pull the definition of pads, groups and functions out of the
> pinctrl-sirf driver,and put them into soc-specific files
> 2. add pads, groups and functions tables for atlas6
> 3. let pads, groups and functions tables become the config data of
>    the related dt compatible node, so the pinctrl-sirf can support
>    all SiRF SoCs with the config data as private data.
>
> In this patch,we create a sirf dir, and let
> the old drivers/pinctrl/pinctrl-sirf.c =
>         drivers/pinctrl/sirf/pinctrl-prima2.c +
>         drivers/pinctrl/sirf/pinctrl-sirf.c
>
> drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the
> pin layout of atlas6.
>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  -v2:
>  rebase to pinctrl/devel

Applied!

Thanks,
Linus Walleij


From pavel at ucw.cz  Wed May 15 07:47:37 2013
From: pavel at ucw.cz (Pavel Machek)
Date: Wed, 15 May 2013 13:47:37 +0200
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <20130515090103.GA12907@mudshark.cambridge.arm.com>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz>
 <5188B8B2.5030601@arm.com>
 <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
 <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>
 <alpine.LFD.2.03.1305141945160.31158@syhkavp.arg>
 <20130515090103.GA12907@mudshark.cambridge.arm.com>
Message-ID: <20130515114737.GA7900@amd.pavel.ucw.cz>

On Wed 2013-05-15 10:01:03, Will Deacon wrote:
> Hi Nico,
> 
> On Wed, May 15, 2013 at 12:56:51AM +0100, Nicolas Pitre wrote:
> > On Tue, 14 May 2013, Rob Herring wrote:
> > > On Tue, May 14, 2013 at 2:54 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > > > Waitaminute... Didn't you just claim this would be an ABI break?
> > > >
> > > > So if no application can be found, where is the ABI breakage?
> > > 
> > > lscpu
> > > 
> > > But that is already "broken" on ARM because x86 uses "bogomips" and
> > > ARM uses "BogoMIPS". 
> > 
> > So basically it won't be any more broken if the field disappears 
> > entirely, right?
> 
> It's not these sort of tools I was worried about. I was thinking about the
> possibility of badly written parsers which want some other field from
> cpuinfo, but use the bogomips line for context. Do these applications exist?
> No idea.

Yes, they do. bogomips is not nearly as bogus as you imply.

See

http://www.clifton.nl/index.html?bogomips.html

https://play.google.com/store/apps/details?id=com.securiteinfo.android.bogomips&hl=en

> My second (less stupid) version of the patch prints "not reported". I'd be
> happy to remove the line altogether if people get behind the decision though.
> In fact, I just tried it and at least my linaro filesystem seems happy
> enough.

Would it be too much work to simply put the field back with the right
value? We don't have to get it as precise as we used to, that should
make slowdown minimum.
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From dmurphy at ti.com  Wed May 15 07:56:26 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Wed, 15 May 2013 06:56:26 -0500
Subject: [PATCH v3] ARM:dts:omap4-panda:Update the LED support for the
 panda DTS
In-Reply-To: <20130515052916.GA15607@kahuna>
References: <1368541076-6854-1-git-send-email-dmurphy@ti.com>
 <20130515052916.GA15607@kahuna>
Message-ID: <519377EA.8070105@ti.com>

NM
On 05/15/2013 12:29 AM, Nishanth Menon wrote:
> $subject - add a space?
> s/ARM:dts:omap4-panda:Update/ARM: dts: omap4-panda: Update/ ?
Will fix.
> On 09:17-20130514, Dan Murphy wrote:
>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>> are different.
>>
>> A1-A3 = gpio_wk7
> Thanks for fixing this - this is a key fix else, GPIO_7 which controls
> VSEL for VDD_MPU on PandaBoard-ES will create all kind of ruckus (change
> voltage on heartbeat)!
>> ES = gpio_110
>>
>> There is no change to LED D2
>>
>> Abstract away the pinmux and the LED definitions for the two boards into
>> the respective DTS files.
>>
>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
>> ---
> [...]
>> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
>> index f1d8c21..8d1ba03 100644
>> --- a/arch/arm/boot/dts/omap4-panda-es.dts
>> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
>> @@ -34,3 +34,43 @@
>>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>>  		>;
>>  };
>> +
>> +&leds {
>> +	compatible = "gpio-leds";
>> +	heartbeat {
>> +		label = "pandaboard::status1";
>> +		gpios = <&gpio4 14 0>;
>> +		linux,default-trigger = "heartbeat";
>> +	};
>> +	mmc {
>> +		label = "pandaboard::status2";
>> +		gpios = <&gpio1 8 0>;
>> +		linux,default-trigger = "gpio";
> mmc0?
Good point why would I call it mmc and then set the trigger to gpio.

Will fix it.
>> +	};
>> +};
>> +
> Other that that,
> Tested-by: Nishanth Menon <nm at ti.com>


-- 
------------------
Dan Murphy



From prabhakar.csengg at gmail.com  Wed May 15 07:57:18 2013
From: prabhakar.csengg at gmail.com (Lad Prabhakar)
Date: Wed, 15 May 2013 17:27:18 +0530
Subject: [PATCH 2/6] ARM: davinci: dm365 evm: remove init_enable from ths7303
 pdata
In-Reply-To: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
References: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
Message-ID: <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>

From: Lad, Prabhakar <prabhakar.csengg at gmail.com>

remove init_enable from ths7303 pdata as it is no longer exists.

Signed-off-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Hans Verkuil <hans.verkuil at cisco.com>
Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
Cc: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
Cc: Sylwester Nawrocki <s.nawrocki at samsung.com>
Cc: Sakari Ailus <sakari.ailus at iki.fi>
Cc: linux-kernel at vger.kernel.org
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-davinci/board-dm365-evm.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 2a66743..4e02ae7 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -510,7 +510,6 @@ struct ths7303_platform_data ths7303_pdata = {
 	.ch_1 = 3,
 	.ch_2 = 3,
 	.ch_3 = 3,
-	.init_enable = 1,
 };
 
 static struct amp_config_info vpbe_amp = {
-- 
1.7.4.1



From laurent.pinchart at ideasonboard.com  Wed May 15 08:05:07 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 14:05:07 +0200
Subject: [PATCH 2/6] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>
References: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
 <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>
Message-ID: <1928313.pnnBGKgv0p@avalon>

Hi Prabhakar,

Thank you for the patch.

On Wednesday 15 May 2013 17:27:18 Lad Prabhakar wrote:
> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> 
> remove init_enable from ths7303 pdata as it is no longer exists.

You should move this before 1/6, otherwise you will break bisection.

> Signed-off-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Hans Verkuil <hans.verkuil at cisco.com>
> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
> Cc: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> Cc: Sylwester Nawrocki <s.nawrocki at samsung.com>
> Cc: Sakari Ailus <sakari.ailus at iki.fi>
> Cc: linux-kernel at vger.kernel.org
> Cc: davinci-linux-open-source at linux.davincidsp.com
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>  arch/arm/mach-davinci/board-dm365-evm.c |    1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c
> b/arch/arm/mach-davinci/board-dm365-evm.c index 2a66743..4e02ae7 100644
> --- a/arch/arm/mach-davinci/board-dm365-evm.c
> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
> @@ -510,7 +510,6 @@ struct ths7303_platform_data ths7303_pdata = {
>  	.ch_1 = 3,
>  	.ch_2 = 3,
>  	.ch_3 = 3,
> -	.init_enable = 1,
>  };
> 
>  static struct amp_config_info vpbe_amp = {
-- 
Regards,

Laurent Pinchart



From prabhakar.csengg at gmail.com  Wed May 15 08:11:51 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Wed, 15 May 2013 17:41:51 +0530
Subject: [PATCH 2/6] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <1928313.pnnBGKgv0p@avalon>
References: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
 <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>
 <1928313.pnnBGKgv0p@avalon>
Message-ID: <CA+V-a8uU6QkYcMg1b5BPHbA0gUGypZeXZNScE-WLa-GqK4_fQA@mail.gmail.com>

Hi Laurent,

Thanks for the review.

On Wed, May 15, 2013 at 5:35 PM, Laurent Pinchart
<laurent.pinchart at ideasonboard.com> wrote:
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Wednesday 15 May 2013 17:27:18 Lad Prabhakar wrote:
>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>>
>> remove init_enable from ths7303 pdata as it is no longer exists.
>
> You should move this before 1/6, otherwise you will break bisection.
>
OK I'll fix it in next version.

Regards,
--Prabhakar Lad


From nico at fluxnic.net  Wed May 15 08:34:51 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 15 May 2013 08:34:51 -0400 (EDT)
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <20130515114737.GA7900@amd.pavel.ucw.cz>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz> <5188B8B2.5030601@arm.com>
 <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
 <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>
 <alpine.LFD.2.03.1305141945160.31158@syhkavp.arg>
 <20130515090103.GA12907@mudshark.cambridge.arm.com>
 <20130515114737.GA7900@amd.pavel.ucw.cz>
Message-ID: <alpine.LFD.2.03.1305150830540.31158@syhkavp.arg>

On Wed, 15 May 2013, Pavel Machek wrote:

> On Wed 2013-05-15 10:01:03, Will Deacon wrote:
> > My second (less stupid) version of the patch prints "not reported".

Even then, you should tell the truth and say "not available" or "not 
applicable".

> > I'd be happy to remove the line altogether if people get behind the 
> > decision though.

You certainly have my ACK.

> > In fact, I just tried it and at least my linaro filesystem seems happy
> > enough.
> 
> Would it be too much work to simply put the field back with the right
> value? We don't have to get it as precise as we used to, that should
> make slowdown minimum.

There is simply no right value.  And whenever there is a value, people 
read too much into it.


Nicolas


From linux at roeck-us.net  Wed May 15 08:28:34 2013
From: linux at roeck-us.net (Guenter Roeck)
Date: Wed, 15 May 2013 05:28:34 -0700
Subject: [PATCH] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <51934896.3000506@free-electrons.com>
References: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>
 <51934896.3000506@free-electrons.com>
Message-ID: <20130515122834.GA26168@roeck-us.net>

On Wed, May 15, 2013 at 10:34:30AM +0200, Maxime Ripard wrote:
> Hi Carlo,
> 
> Le 12/05/2013 22:36, Carlo Caione a ?crit :
> > This patch adds the driver for the watchdog found in the Allwinner A10 and
> > A13 SoCs. It has DT-support and uses the new watchdog framework.
> > 
> > Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
> > ---
> >  drivers/watchdog/Kconfig     |  10 ++
> >  drivers/watchdog/Makefile    |   1 +
> >  drivers/watchdog/sunxi_wdt.c | 218 +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 229 insertions(+)
> >  create mode 100644 drivers/watchdog/sunxi_wdt.c
> > 
> > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> > index e89fc31..473e670 100644
> > --- a/drivers/watchdog/Kconfig
> > +++ b/drivers/watchdog/Kconfig
> > @@ -299,6 +299,16 @@ config ORION_WATCHDOG
> >  	  To compile this driver as a module, choose M here: the
> >  	  module will be called orion_wdt.
> >  
> > +config SUNXI_WATCHDOG
> > +	tristate "Sunxi watchdog"
> 
> Maybe mention what sunxi is? something like "Allwinner SoCs watchdog
> support"
> 
> > +	depends on ARCH_SUNXI
> > +	select WATCHDOG_CORE
> > +	help
> > +	  Say Y here to include support for the watchdog timer
> > +	  in Allwinner A10 and A13.
> 
> I'd be more generic here. As far as we know, this code is found in A10,
> A10s, A13, and can easily be adapted to support the A31 (and I suspect
> the A20 as well). Something like "Allwinner SoCs"
> 
> > +	  To compile this driver as a module, choose M here: the
> > +	  module will be called sunxi_wdt.
> > +
> >  config COH901327_WATCHDOG
> >  	bool "ST-Ericsson COH 901 327 watchdog"
> >  	depends on ARCH_U300
> > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> > index a300b94..5012d5f 100644
> > --- a/drivers/watchdog/Makefile
> > +++ b/drivers/watchdog/Makefile
> > @@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
> >  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
> >  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
> >  obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
> > +obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
> >  obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
> >  obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
> >  obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
> > diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
> > new file mode 100644
> > index 0000000..fe193b3
> > --- /dev/null
> > +++ b/drivers/watchdog/sunxi_wdt.c
> > @@ -0,0 +1,218 @@
> > +/*
> > + *      sunxi Watchdog Driver
> > + *
> > + *      Copyright (c) 2013 Carlo Caione
> > + *                    2012 Henrik Nordstrom
> > + *
> > + *      This program is free software; you can redistribute it and/or
> > + *      modify it under the terms of the GNU General Public License
> > + *      as published by the Free Software Foundation; either version
> > + *      2 of the License, or (at your option) any later version.
> > + *
> > + *      Based on xen_wdt.c
> > + *      (c) Copyright 2010 Novell, Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/moduleparam.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/types.h>
> > +#include <linux/watchdog.h>
> > +
> > +#define WDT_MAX_TIMEOUT         16
> > +#define WDT_MIN_TIMEOUT         1
> > +#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
> > +#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
> > +
> > +#define WDT_CTRL                0x00
> > +#define WDT_MODE                0x04
> > +
> > +#define WDT_MODE_RST_EN         (1 << 1)
> > +#define WDT_MODE_EN             (1 << 0)
> > +
> > +#define WDT_CTRL_RESTART        (1 << 0)
> 
> I'd prefer to see the bits values just behind the register they belong to.
> 
> > +#define WDT_CTRL_RESERVED       (0x0a57 << 1)
> > +#define DRV_NAME		"sunxi-wdt"
> > +#define DRV_VERSION		"1.0"
> > +
> > +static bool nowayout = WATCHDOG_NOWAYOUT;
> > +static int heartbeat = WDT_MAX_TIMEOUT;
> > +
> > +static const int wdt_timeout_map[] = {
> > +	[1] = 0b0001,
> > +	[2] = 0b0010,
> > +	[3] = 0b0011,
> > +	[4] = 0b0100,
> > +	[5] = 0b0101,
> > +	[6] = 0b0110,
> > +	[8] = 0b0111,
> > +	[10] = 0b1000,
> > +	[12] = 0b1001,
> > +	[14] = 0b1010,
> > +	[16] = 0b1011,
> > +};
> 
> It would be great to have a comment about what this map is here for and
> how you store the values.
> 
> You don't support the 0.5s timeout here as well. I know why, but some
> new comer might not, so I guess it would be great to add it to the
> comment as well.
> 
> Moreover, I'd really like this to be supported. Maybe, since obviously
> we can't put a value at the index 0.5, maybe saying that the 0 index is
> actually this 0.5ms timeout value?
> 
guess you mean 0.5s, not 0.5ms.

Since the watchdog infrastructure does not support it, how would you set it ?

Keep in mind that low timeout values are not really that useful, as you'll
have to guarantee that the watchdog gets pinged frequently enough. It would be
quite challenging to meet even a 1-second timeout requirement.

Guenter

> > +
> > +static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
> > +{
> > +	u32 reg;
> > +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> > +
> > +	reg = ioread32(wdt_base + WDT_CTRL);
> > +	reg |= (WDT_CTRL_RESTART | WDT_CTRL_RESERVED);
> 
> The RESERVED part is not needed, especially if you OR the values already
> there, it looks like it could trigger something nasty.
> 
> > +	iowrite32(reg, wdt_base + WDT_CTRL);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
> > +		unsigned int timeout)
> > +{
> > +	u32 reg;
> > +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> > +
> > +	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout]))
> > +		return -EINVAL;
> > +
> > +	sunxi_wdt_dev->timeout = timeout;
> > +
> > +	reg = ioread32(wdt_base + WDT_MODE);
> > +	reg &= ~(WDT_TIMEOUT_MASK);
> > +	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
> > +	iowrite32(reg, wdt_base + WDT_MODE);
> > +
> > +	sunxi_wdt_ping(sunxi_wdt_dev);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
> > +{
> > +	u32 reg;
> > +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> > +
> > +	reg = ioread32(wdt_base + WDT_MODE);
> > +	reg &= ~(WDT_MODE_RST_EN | WDT_MODE_EN);
> > +	iowrite32(reg, wdt_base + WDT_MODE);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
> > +{
> > +	u32 reg;
> > +	int ret;
> > +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> > +
> > +	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	reg = ioread32(wdt_base + WDT_MODE);
> > +	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
> > +	iowrite32(reg, wdt_base + WDT_MODE);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct watchdog_info sunxi_wdt_info = {
> > +	.identity	= DRV_NAME,
> > +	.options	= WDIOF_SETTIMEOUT |
> > +			  WDIOF_KEEPALIVEPING |
> > +			  WDIOF_MAGICCLOSE,
> > +};
> > +
> > +static const struct watchdog_ops sunxi_wdt_ops = {
> > +	.owner		= THIS_MODULE,
> > +	.start		= sunxi_wdt_start,
> > +	.stop		= sunxi_wdt_stop,
> > +	.ping		= sunxi_wdt_ping,
> > +	.set_timeout	= sunxi_wdt_set_timeout,
> > +};
> > +
> > +static struct watchdog_device sunxi_wdt_dev = {
> > +	.info		= &sunxi_wdt_info,
> > +	.ops		= &sunxi_wdt_ops,
> > +	.timeout	= WDT_MAX_TIMEOUT,
> > +	.max_timeout	= WDT_MAX_TIMEOUT,
> > +	.min_timeout	= WDT_MIN_TIMEOUT,
> > +};
> > +
> > +static int __init sunxi_wdt_probe(struct platform_device *pdev)
> > +{
> > +	int err;
> > +	void __iomem *wdt_base;
> > +
> > +	wdt_base = of_iomap(pdev->dev.of_node, 0);
> > +	if (unlikely(!wdt_base)) {
> > +		err = -ENOMEM;
> > +		goto error_mem_out;
> > +	}
> > +
> > +	sunxi_wdt_dev.parent = &pdev->dev;
> > +	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
> > +	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
> > +
> > +	err = watchdog_register_device(&sunxi_wdt_dev);
> > +	if (unlikely(err))
> > +		goto error_wdt;
> > +
> > +	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
> > +
> > +	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
> > +			sunxi_wdt_dev.timeout, nowayout);
> > +	return 0;
> > +
> > +error_wdt:
> > +	iounmap(wdt_base);
> > +error_mem_out:
> > +	return err;
> > +}
> > +
> > +static int __exit sunxi_wdt_remove(struct platform_device *pdev)
> > +{
> > +	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
> > +
> > +	sunxi_wdt_stop(&sunxi_wdt_dev);
> > +	watchdog_unregister_device(&sunxi_wdt_dev);
> > +	iounmap(wdt_base);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id sunxi_wdt_dt_ids[] = {
> > +	{ .compatible = "allwinner,sun4i-wdt" },
> > +	{ /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
> > +
> > +static struct platform_driver sunxi_wdt_driver = {
> > +	.probe		= sunxi_wdt_probe,
> > +	.remove		= sunxi_wdt_remove,
> > +	.driver		= {
> > +		.owner		= THIS_MODULE,
> > +		.name		= DRV_NAME,
> > +		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
> > +	},
> > +};
> > +
> > +module_platform_driver(sunxi_wdt_driver);
> > +
> > +module_param(heartbeat, int, 0);
> > +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
> > +
> > +module_param(nowayout, bool, 0);
> > +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
> > +		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> > +
> > +MODULE_LICENSE("GPL");
> > +MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
> > +MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
> > +MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
> > +MODULE_VERSION(DRV_VERSION);
> > 
> 
> 
> -- 
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
> --
> To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From pavel at ucw.cz  Wed May 15 08:36:40 2013
From: pavel at ucw.cz (Pavel Machek)
Date: Wed, 15 May 2013 14:36:40 +0200
Subject: v3.10-rc1: compile problem in arch/arm/common/mcpm_platsmp.c
Message-ID: <20130515123640.GA9066@amd.pavel.ucw.cz>

Hi!

I'm trying to switch to v3.10-rc1, and got following:

arch/arm/common/mcpm_platsmp.c: In function 'mcpm_secondary_init':
arch/arm/common/mcpm_platsmp.c:52:2: error: implicit declaration of
function 'gic_secondary_init' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[1]: *** [arch/arm/common/mcpm_platsmp.o] Error 1
make: *** [arch/arm/common] Error 2
make: *** Waiting for unfinished jobs....

I do have 

CONFIG_ARM_GIC=y

.
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From arnd at arndb.de  Tue May 14 16:23:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 14 May 2013 22:23:37 +0200
Subject: [PATCH] ASoC: remove saarb and tavorevb3 machine drivers
In-Reply-To: <1368544041.1350.111.camel@x61.thuisdomein>
References: <1368544041.1350.111.camel@x61.thuisdomein>
Message-ID: <2843869.zn4rrxyCrZ@wuerfel>

On Tuesday 14 May 2013 17:07:21 Paul Bolle wrote:
> Support for PXA95x was removed in v3.8. This means that the Kconfig
> symbols MACH_SAARB and MACH_TAVOREVB3 are no longer available. This
> leaves the SoC Audio support for Marvell Saarb and Marvell Tavor EVB3
> unbuildable. Remove these drivers too.
> 
> Signed-off-by: Paul Bolle <pebolle at tiscali.nl>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From emilio at elopez.com.ar  Wed May 15 08:36:41 2013
From: emilio at elopez.com.ar (=?UTF-8?q?Emilio=20L=C3=B3pez?=)
Date: Wed, 15 May 2013 09:36:41 -0300
Subject: [PATCH] ARM: ux500: select REGULATOR
Message-ID: <1368621401-18569-1-git-send-email-emilio@elopez.com.ar>

MACH_MOP500 selects REGULATOR_FIXED_VOLTAGE but not REGULATOR. This
patch makes it select the latter too.

Seen as:
    warning: (MACH_DOVE_DT && ARCH_KIRKWOOD_DT && MACH_AMS_DELTA &&
    MACH_MOP500 && TPS6105X) selects REGULATOR_FIXED_VOLTAGE which has
    unmet direct dependencies (REGULATOR)

Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
---
 arch/arm/mach-ux500/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 6a4387e..b19b072 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -51,6 +51,7 @@ config MACH_MOP500
 	bool "U8500 Development platform, MOP500 versions"
 	select I2C
 	select I2C_NOMADIK
+	select REGULATOR
 	select REGULATOR_FIXED_VOLTAGE
 	select SOC_BUS
 	select UX500_SOC_DB8500
-- 
1.8.2.3



From will.deacon at arm.com  Wed May 15 08:41:52 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 13:41:52 +0100
Subject: v3.10-rc1: compile problem in arch/arm/common/mcpm_platsmp.c
In-Reply-To: <20130515123640.GA9066@amd.pavel.ucw.cz>
References: <20130515123640.GA9066@amd.pavel.ucw.cz>
Message-ID: <20130515124152.GG23869@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 01:36:40PM +0100, Pavel Machek wrote:
> Hi!
> 
> I'm trying to switch to v3.10-rc1, and got following:
> 
> arch/arm/common/mcpm_platsmp.c: In function 'mcpm_secondary_init':
> arch/arm/common/mcpm_platsmp.c:52:2: error: implicit declaration of
> function 'gic_secondary_init' [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
> make[1]: *** [arch/arm/common/mcpm_platsmp.o] Error 1
> make: *** [arch/arm/common] Error 2
> make: *** Waiting for unfinished jobs....
> 
> I do have 
> 
> CONFIG_ARM_GIC=y

Please see 9e01573b5cf8 ("ARM: 7715/1: MCPM: adapt to GIC changes after
upstream merge") in rmk/fixes.

Will


From pavel at denx.de  Wed May 15 08:43:02 2013
From: pavel at denx.de (Pavel Machek)
Date: Wed, 15 May 2013 14:43:02 +0200
Subject: [PATCH 1/5] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
Message-ID: <20130515124302.GB9066@amd.pavel.ucw.cz>

On Tue 2013-05-14 17:52:31, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: <linux at arm.linux.org.uk>

Looks good.

Reviewed-by: Pavel Machek <pavel at denx.de>

...but, this patch is not enough to get ethernet to work with
3.10-rc1, right? I hoped that applying 1-3 of the series would get me
ethernet, but no :-(.

Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From tixy at linaro.org  Wed May 15 08:44:28 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Wed, 15 May 2013 13:44:28 +0100
Subject: v3.10-rc1: compile problem in arch/arm/common/mcpm_platsmp.c
In-Reply-To: <20130515123640.GA9066@amd.pavel.ucw.cz>
References: <20130515123640.GA9066@amd.pavel.ucw.cz>
Message-ID: <1368621868.5583.6.camel@computer5.home>

On Wed, 2013-05-15 at 14:36 +0200, Pavel Machek wrote:
> Hi!
> 
> I'm trying to switch to v3.10-rc1, and got following:
> 
> arch/arm/common/mcpm_platsmp.c: In function 'mcpm_secondary_init':
> arch/arm/common/mcpm_platsmp.c:52:2: error: implicit declaration of
> function 'gic_secondary_init' [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
> make[1]: *** [arch/arm/common/mcpm_platsmp.o] Error 1
> make: *** [arch/arm/common] Error 2
> make: *** Waiting for unfinished jobs....

This has already been hit by others and there is a patch in the
pipeline, see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/167586.html

-- 
Tixy



From nicolas.pitre at linaro.org  Wed May 15 08:48:45 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 15 May 2013 08:48:45 -0400 (EDT)
Subject: [PATCH] ARM: crypto: sha1-armv4-large.S: fix SP handling
In-Reply-To: <1368610020-29219-1-git-send-email-ard.biesheuvel@linaro.org>
References: <1368610020-29219-1-git-send-email-ard.biesheuvel@linaro.org>
Message-ID: <alpine.LFD.2.03.1305150845410.31158@syhkavp.arg>

On Wed, 15 May 2013, Ard Biesheuvel wrote:

> Make the SHA1 asm code ABI conformant by making sure all stack
> accesses occur above the stack pointer.
> 
> Origin:
> http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2
> 
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>

Acked-by: Nicolas Pitre <nico at linaro.org>

Please add

Cc: stable at vger.kernel.org

and send it to RMK's patch system.

>  arch/arm/crypto/sha1-armv4-large.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
> index 92c6eed..99207c4 100644
> --- a/arch/arm/crypto/sha1-armv4-large.S
> +++ b/arch/arm/crypto/sha1-armv4-large.S
> @@ -195,6 +195,7 @@ ENTRY(sha1_block_data_order)
>  	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
>  	cmp	r14,sp
>  	bne	.L_00_15		@ [((11+4)*5+2)*3]
> +	sub	sp,sp,#25*4
>  #if __ARM_ARCH__<7
>  	ldrb	r10,[r1,#2]
>  	ldrb	r9,[r1,#3]
> @@ -290,7 +291,6 @@ ENTRY(sha1_block_data_order)
>  	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
>  
>  	ldr	r8,.LK_20_39		@ [+15+16*4]
> -	sub	sp,sp,#25*4
>  	cmn	sp,#0			@ [+3], clear carry to denote 20_39
>  .L_20_39_or_60_79:
>  	ldr	r9,[r14,#15*4]
> -- 
> 1.8.1.2
> 


From arnd at arndb.de  Wed May 15 08:55:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 14:55:12 +0200
Subject: [PATCHv2 00/20] Cleanup irqchip_init calls
In-Reply-To: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <201305151455.12603.arnd@arndb.de>

On Tuesday 14 May 2013, Maxime Ripard wrote:
> This is a splitted up version of the patch I previously sent to
> remove the explicit declaration of irqchip_init as the init_irq callback in
> the machine descriptions.
> 
> Since it was a pretty tricky patch to merge, since it was touching a lot of
> different platforms, I splitted it for each platforms, and rebased it on top
> of 3.10-rc1.
> 
> The best way to merge it is probably that each one of us take into their tree
> the patches that are relevant for our architecture and send them to arm-soc
> later on.

Sounds good to me. I'm sure that some platform maintainers will fail to
apply this though. Could you send whatever remains as a separate branch
in a couple of weeks so we can directly apply it to next/cleanup?

	Arnd


From 21cnbao at gmail.com  Wed May 15 08:59:47 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 15 May 2013 20:59:47 +0800
Subject: [PATCH] spi: sirf: fix the issue while transferring more than 256
 words
In-Reply-To: <1363592828-6347-1-git-send-email-Barry.Song@csr.com>
References: <1363592828-6347-1-git-send-email-Barry.Song@csr.com>
Message-ID: <CAGsJ_4wamqzwLZkUz4h6ex=oVQZhzhw7S6r41wt9tTUoMR=aXw@mail.gmail.com>

ping Mark, Ping Grant.

2013/3/18 Barry Song <Barry.Song at csr.com>:
> From: Qipan Li <Qipan.Li at csr.com>
>
> currently, spi irq handler only does rx processing and  fetching data from rx
> fifo when "FRM_END" irq happens. FRM_END indicates one transfer completes. if
> rx size is less than 256, it works well.
> but the problem is that spi rx fifo size is only 256 bytes, then if data size
> of one frame is more than 256, before FRM_END comes, rx fifo will be filled with
> RXFIFO_OFLOW overflow interrupt, it will make us lose some data due to fifo
> overflow.
> Explicitly we need do fetch work from device rx fifo in irq handler not only in
> "FRM_END" irq but also in "THD_REACH" irq. THD_REACH means rx fifo has come to
> its threshold and will come to overflow if we don't take data from it in time.
>
> In this patch, we fix this issue. we take data from rx fifo when either FRM_END
> or RX_THD_REACH irq comes, we put data into tx fifo when either TX_FIFO_EMPTY
> or TX_THD_REACH irq comes.
>
> Signed-off-by: Qipan Li <Qipan.Li at csr.com>
> Signed-off-by: Zhiwu Song <Zhiwu.Song at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  drivers/spi/spi-sirf.c |   43 +++++++++++++------------------------------
>  1 files changed, 13 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
> index f59d417..d2bd1e5 100644
> --- a/drivers/spi/spi-sirf.c
> +++ b/drivers/spi/spi-sirf.c
> @@ -142,9 +142,6 @@ struct sirfsoc_spi {
>         unsigned int left_tx_cnt;
>         unsigned int left_rx_cnt;
>
> -       /* tasklet to push tx msg into FIFO */
> -       struct tasklet_struct tasklet_tx;
> -
>         int chipselect[0];
>  };
>
> @@ -236,17 +233,6 @@ static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
>         sspi->left_tx_cnt--;
>  }
>
> -static void spi_sirfsoc_tasklet_tx(unsigned long arg)
> -{
> -       struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
> -
> -       /* Fill Tx FIFO while there are left words to be transmitted */
> -       while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
> -                       SIRFSOC_SPI_FIFO_FULL)) &&
> -                       sspi->left_tx_cnt)
> -               sspi->tx_word(sspi);
> -}
> -
>  static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
>  {
>         struct sirfsoc_spi *sspi = dev_id;
> @@ -261,25 +247,25 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
>                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
>         }
>
> -       if (spi_stat & SIRFSOC_SPI_FRM_END) {
> +       if (spi_stat & (SIRFSOC_SPI_FRM_END
> +                       | SIRFSOC_SPI_RXFIFO_THD_REACH))
>                 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
>                                 & SIRFSOC_SPI_FIFO_EMPTY)) &&
>                                 sspi->left_rx_cnt)
>                         sspi->rx_word(sspi);
>
> -               /* Received all words */
> -               if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
> -                       complete(&sspi->done);
> -                       writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
> -               }
> -       }
> -
> -       if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH ||
> -               spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH ||
> -               spi_stat & SIRFSOC_SPI_RX_FIFO_FULL ||
> -               spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
> -               tasklet_schedule(&sspi->tasklet_tx);
> +       if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
> +                       | SIRFSOC_SPI_TXFIFO_THD_REACH))
> +               while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
> +                               & SIRFSOC_SPI_FIFO_FULL)) &&
> +                               sspi->left_tx_cnt)
> +                       sspi->tx_word(sspi);
>
> +       /* Received all words */
> +       if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
> +               complete(&sspi->done);
> +               writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
> +       }
>         return IRQ_HANDLED;
>  }
>
> @@ -573,9 +559,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
>
>         init_completion(&sspi->done);
>
> -       tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
> -                    (unsigned long)sspi);
> -
>         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
>         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
>         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
> --
> 1.7.5.4


From pavel at denx.de  Wed May 15 09:05:35 2013
From: pavel at denx.de (Pavel Machek)
Date: Wed, 15 May 2013 15:05:35 +0200
Subject: [PATCH 4/5] ARM: socfpga: dts: Add support for SD/MMC
In-Reply-To: <1368571955-6652-4-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-4-git-send-email-dinguyen@altera.com>
Message-ID: <20130515130535.GC9066@amd.pavel.ucw.cz>

Hi!

> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add bindings for SD/MMC for SOCFPGA.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: <linux at arm.linux.org.uk>

git says:

[pavel at pollux linux]$ cat /tmp/delme | git apply
<stdin>:136: space before tab in indent.
      	     	   altr,dw-mshc-sdr-timing = <0 3>;
<stdin>:143: new blank line at EOF.
+
warning: 2 lines add whitespace errors.
[pavel at pollux linux]$ 

Is this patch series expected to be enough to get MMC to work? I
applied all 5 patches, and it detects the controller, but mmcblkX
devices do not show up.

Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming
pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit
host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 400000Hz,
actual 400000HZ div = 125)
...
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "nfs" or unknown-block(2,0): error -6
Please append a correct "root=" boot option; here are the available
partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(2,0)

It should be configured in:

CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y

.

Otherwise, it looks good.

Reviewed-by: Pavel Machek <pavel at denx.de>

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From pavel at denx.de  Wed May 15 09:06:39 2013
From: pavel at denx.de (Pavel Machek)
Date: Wed, 15 May 2013 15:06:39 +0200
Subject: [PATCH 2/5] ARM: socfpga: dts: Add gate-clock bindings
In-Reply-To: <1368571955-6652-2-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-2-git-send-email-dinguyen@altera.com>
Message-ID: <20130515130639.GD9066@amd.pavel.ucw.cz>

Hi!

> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
> the peripherals.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>

Looks good to me.

Reviewed-by: Pavel Machek <pavel at denx.de>

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From arnd at arndb.de  Wed May 15 09:16:52 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 15:16:52 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <CACmBeS1empYyoaKidgTrYwUFCw447OKndxZjT98TvYfKVWB00A@mail.gmail.com>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201303181503.49491.arnd@arndb.de>
 <CACmBeS1empYyoaKidgTrYwUFCw447OKndxZjT98TvYfKVWB00A@mail.gmail.com>
Message-ID: <201305151516.52389.arnd@arndb.de>

On Wednesday 15 May 2013, Jonas Jensen wrote:
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 29f7623..d534fce 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -429,6 +429,15 @@ choice
>  		  Say Y here if you want kernel low-level debugging support
>  		  on Allwinner A1X based platforms on the UART1.
> 
> +	config DEBUG_MOXART_UART0
> +        bool "Kernel low-level debugging messages via MOXART UART0"
> +        depends on ARCH_MOXART
> +        help
> +          Say Y here if you want kernel low-level debugging support
> +          on MOXART based platforms on the UART0.
> +          select this to make sure "putc" in arch/arm/boot/compressed/debug.S
> +          uses arch/arm/include/debug/moxart.S:s "addruart" macro
> +
>  	config DEBUG_TEGRA_UART
>  		depends on ARCH_TEGRA
>  		bool "Use Tegra UART for low-level debug"
> @@ -651,6 +660,7 @@ config DEBUG_LL_INCLUDE
>  	default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
>  	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
>  	default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
> +	default "debug/moxart.S" if DEBUG_MOXART_UART0
>  	default "debug/tegra.S" if DEBUG_TEGRA_UART
>  	default "debug/ux500.S" if DEBUG_UX500_UART
>  	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \

Please split this patch into separate patches. All the debug stuff can go into
one patch that is fairly separate from the rest. You can probably find a few
other things that can be split out, just make sure that the order is so that
we don't have a broken source tree when only applying a few of them.

You can use git-format-patch and git-send-email to send out a series properly.
> +
> +		intc: interrupt-controller at 98800000 {
> +			compatible = "moxart,moxart-interrupt-controller";
> +			reg = <0x98800000 0x38>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupt-mask = <0x00080000>;		/* single register vector,
> interrupts 0-31, 1s signify edge */
> +		};

That will also take care of broken line wrapping as above. The current version can not
be applied.

> +		timer0: timer at 98400000 {
> +			compatible = "moxart,moxart-timer0";
> +			reg = <0x98400000 0x10>;
> +			interrupts = <19 1>;
> +		};

"moxart,moxart-timer0" is a strange identifier for a device. First of all, all your
compatible strings should probably start with "moxa," rather than "moxart,".

The part that I don't understand at all is the "timer0" part. Is that a string
from the data sheet?

> +		gpio: gpio at 98700000 {
> +			compatible = "moxart,moxart-gpio";
> +			reg =	<0x98700000 0x1000>,
> +					<0x98100000 0x1000>;		/* PMU */
> +		};

Can you provide some more detail why what PMU registers are used here? Is that
a "Performance Measurement Unit", "Power Management Unit" or something else?
Are you sure that those registers are only ever needed for GPIO?

> @@ -0,0 +1,34 @@
> +config ARCH_MOXART
> +	bool "MOXA ART SoC" if (ARCH_MULTI_V4)
> +	select ARCH_REQUIRE_GPIOLIB
> +	select USE_OF
> +	help
> +	  Say Y here if you want to run your kernel on hardware
> +	  with a MOXA ART SoC.
> +	  These are DIN-rail / wall-mountable embedded PCs sold by MOXA.
> +	  http://www.moxa.com/product/Embedded_Computers.htm
> +
> +config SOC_MOXART
> +	bool "MOXART support"
> +	depends on ARCH_MOXART
> +	default y
> +	select CPU_FA526
> +	select ARM_DMA_MEM_BUFFERABLE
> +	help
> +	  Support for the MOXA ART SoC. This is a Faraday FA526 ARMv4 32-bit
> 192 MHz processor with MMU and 16KB/8KB D/I-cache (UC-7112-LX)
> +	  This perticular SoC is used on models UC-7101, UC-7112/UC-7110,
> IA240/IA241, IA3341.
> +	  These are DIN-rail / wall-mountable embedded PCs sold by MOXA (
> http://www.moxa.com/product/Embedded_Computers.htm ).
> +
> +if ARCH_MOXART
> +
> +menu "MOXA ART SoC Implementation"
> +
> +config MACH_UC7112LX
> +	bool "MOXA UC-7112-LX"
> +	depends on ARCH_MOXART && SOC_MOXART
> +	help
> +	  Say Y here if you intend to run this kernel on a MOXA UC-7112-LX
> embedded computer.

There should be no need for three separate symbols here. Just fold it
all into ARCH_MOXART. Note that you messed up the line wrapping above,
so that should be fixed. Hopefully the UC-7112-LX specific portions
can remain small to nonexisting so we don't have a need to make that
a separate option.

> +
> +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include

Just leave this out and move all header files into the arch/arm/mach-moxart/
directory directly.

> diff --git a/arch/arm/mach-moxart/Makefile.boot
> b/arch/arm/mach-moxart/Makefile.boot
> new file mode 100644
> index 0000000..760a0ef
> --- /dev/null
> +++ b/arch/arm/mach-moxart/Makefile.boot
> @@ -0,0 +1,3 @@
> +   zreladdr-y	+= 0x00008000
> +params_phys-y	:= 0x00000100
> +initrd_phys-y	:= 0x00800000

Is this still used?

> diff --git a/arch/arm/mach-moxart/idle.c b/arch/arm/mach-moxart/idle.c
> new file mode 100644
> index 0000000..5970c27
> --- /dev/null
> +++ b/arch/arm/mach-moxart/idle.c

> +static void moxart_idle(void)
> +{
> +	/*
> +	 * Because of broken hardware we have to enable interrupts or the CPU
> +	 * will never wakeup... Acctualy it is not very good to enable
> +	 * interrupts first since scheduler can miss a tick, but there is
> +	 * no other way around this. Platforms that needs it for power saving
> +	 * should call enable_hlt() in init code, since by default it is
> +	 * disabled.
> +	 */
> +/*	local_irq_enable();
> +	cpu_do_idle();*/
> +}
> +
> +static int __init moxart_idle_init(void)
> +{
> +	arm_pm_idle = moxart_idle;
> +	return 0;
> +}
> +
> +arch_initcall(moxart_idle_init);

This does not seem to do anything at this point. Does the comment still
apply?

> +
> +static void __init moxart_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
> +
> +void moxart_restart(char mode, const char *cmd)
> +{
> +	writel(1, reg_wdt + 4);
> +	writel(0x5ab9, reg_wdt + 8);
> +	writel(0x03, reg_wdt + 12);
> +}
> +
> +static const char * const moxart_board_dt_compat[] = {
> +	"moxart,moxart-uc-7112-lx",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(MOXART, "MOXA UC-7112-LX")
> +	.init_irq		= moxart_init_irq,
> +	.init_time		= moxart_timer_init,
> +	.init_machine	= moxart_init,
> +	.handle_irq		= moxart_handle_irq,
> +	.restart        = moxart_restart,
> +	.dt_compat		= moxart_board_dt_compat,
> +	.nr_irqs		= 32,
> +MACHINE_END

You can leave out moxart_init() now, it's the default implementation.
moxart_init_irq, moxart_handle_irq and nr_irqs should be obsolete if
you did the irqchip driver correctly, same for moxart_timer_init and
the clocksource driver.

I think the only part remaining here is moxart_restart, but that is
broken as long as reg_wdt does not get initialized. I think you could
move that function into the watchdog driver and assign it to 
arm_pm_restart when you add that driver.

That would in fact make moxart the first platform that can run without
any platform specific code whatsoever.

	Arnd


From gregory.clement at free-electrons.com  Wed May 15 09:18:53 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 15 May 2013 15:18:53 +0200
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <1364235581-17900-4-git-send-email-will.deacon@arm.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
Message-ID: <51938B3D.2070508@free-electrons.com>

Hi Will,

On 03/25/2013 07:19 PM, Will Deacon wrote:
> Many ARMv7 cores have hardware page table walkers that can read the L1
> cache. This is discoverable from the ID_MMFR3 register, although this
> can be expensive to access from the low-level set_pte functions and is a
> pain to cache, particularly with multi-cluster systems.
> 
> A useful observation is that the multi-processing extensions for ARMv7
> require coherent table walks, meaning that we can make use of ALT_SMP
> patching in proc-v7-* to patch away the cache flush safely for these
> cores.

I encountered a regression with 3.10-rc1 on the Armada 370 based boards.
With the 3.10-rc1 they hang during auto testy of the xor engine which are
mainly DMA transfers. If I revert this patch, it no more hang. I found this
by using bisect, it was not obvious at all for me that this patch may have
cause this regression.
The issue appear in SMP and in UP. However I think that  the PJ4B-v7 used in
 the Armada 370 are not MP capable.

I made some investigation. And in UP if I remove the line:
	ALT_UP(W(nop))

at the begining of the cpu_v7_dcache_clean_are macro located in
arch/arm/mm/proc-v7.S

Then the kernel boot again. It is not surprising because in this case
we found the same generated code that before this patch was applied.

now I don't really understand why a W(nop) will cause this issue.

In SMP mode even with this line removed the kernel hang, but in this case
I am not sure of what happen exactly and how the .alt.smp.init section is
used.

I don't know if it is relevant but I tested with these 2 version of gcc:
gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5)
and
gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-1ubuntu1)

I hope you will find some explanation and solution to this bug, because currently
the only solution I have is to revert this patch.

Thanks,
Gregory
> 
> Reported-by: Albin Tonnerre <Albin.Tonnerre at arm.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/include/asm/tlbflush.h | 2 +-
>  arch/arm/mm/proc-v6.S           | 2 --
>  arch/arm/mm/proc-v7-2level.S    | 3 ++-
>  arch/arm/mm/proc-v7-3level.S    | 3 ++-
>  arch/arm/mm/proc-v7.S           | 4 ++--
>  5 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
> index c7cdb59..42d155e 100644
> --- a/arch/arm/include/asm/tlbflush.h
> +++ b/arch/arm/include/asm/tlbflush.h
> @@ -169,7 +169,7 @@
>  # define v6wbi_always_flags	(-1UL)
>  #endif
>  
> -#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
> +#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_BARRIER | \
>  				 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
>  				 TLB_V6_U_ASID | TLB_V6_BP | \
>  				 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
> diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
> index bcaaa8d..a286d47 100644
> --- a/arch/arm/mm/proc-v6.S
> +++ b/arch/arm/mm/proc-v6.S
> @@ -80,12 +80,10 @@ ENTRY(cpu_v6_do_idle)
>  	mov	pc, lr
>  
>  ENTRY(cpu_v6_dcache_clean_area)
> -#ifndef TLB_CAN_READ_FROM_L1_CACHE
>  1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
>  	add	r0, r0, #D_CACHE_LINE_SIZE
>  	subs	r1, r1, #D_CACHE_LINE_SIZE
>  	bhi	1b
> -#endif
>  	mov	pc, lr
>  
>  /*
> diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
> index 78f520b..9704097 100644
> --- a/arch/arm/mm/proc-v7-2level.S
> +++ b/arch/arm/mm/proc-v7-2level.S
> @@ -110,7 +110,8 @@ ENTRY(cpu_v7_set_pte_ext)
>   ARM(	str	r3, [r0, #2048]! )
>   THUMB(	add	r0, r0, #2048 )
>   THUMB(	str	r3, [r0] )
> -	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
> +	ALT_SMP(mov	pc,lr)
> +	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
>  #endif
>  	mov	pc, lr
>  ENDPROC(cpu_v7_set_pte_ext)
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 6ffd78c..363027e 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -73,7 +73,8 @@ ENTRY(cpu_v7_set_pte_ext)
>  	tst	r3, #1 << (55 - 32)		@ L_PTE_DIRTY
>  	orreq	r2, #L_PTE_RDONLY
>  1:	strd	r2, r3, [r0]
> -	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
> +	ALT_SMP(mov	pc, lr)
> +	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
>  #endif
>  	mov	pc, lr
>  ENDPROC(cpu_v7_set_pte_ext)
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 3a3c015..37716b0 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -75,14 +75,14 @@ ENTRY(cpu_v7_do_idle)
>  ENDPROC(cpu_v7_do_idle)
>  
>  ENTRY(cpu_v7_dcache_clean_area)
> -#ifndef TLB_CAN_READ_FROM_L1_CACHE
> +	ALT_SMP(mov	pc, lr)			@ MP extensions imply L1 PTW
> +	ALT_UP(W(nop))
>  	dcache_line_size r2, r3
>  1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
>  	add	r0, r0, r2
>  	subs	r1, r1, r2
>  	bhi	1b
>  	dsb
> -#endif
>  	mov	pc, lr
>  ENDPROC(cpu_v7_dcache_clean_area)
>  
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From arnd at arndb.de  Wed May 15 09:19:08 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 15:19:08 +0200
Subject: [PATCH 1/5] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
Message-ID: <201305151519.08598.arnd@arndb.de>

On Wednesday 15 May 2013, dinguyen at altera.com wrote:
>                 };
>  
> +               ethernet at ff700000 {
> +                       phy-mode = "gmii";
> +               };
> +
> +               ethernet at ff702000 {
> +                       status = "disabled";
> +               };

By convention, please mark the controllers as "disabled" in the main .dtsi file
and only enable them in the board specific files when used, rather than the
other way round.

	Arnd


From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:15 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:15 +0200
Subject: [PATCHv9 1/9] arm: mvebu: fix the 'ranges' property to handle PCIe
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-2-git-send-email-thomas.petazzoni@free-electrons.com>

Since 82a682676 ('ARM: dts: mvebu: Convert all the mvebu files to use
the range property') all the device nodes of Armada 370/XP are under a
common 'ranges' property that translates the device register addresses
into their absolute address, thanks to the base address of the
internal register space.

However, beyond just the register areas, there are also PCIe I/O and
memory regions, whose addresses should be properly translated. This
patch fixes the Armada 370 and XP ranges property to take PCIe into
account properly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Since the PCIe Device Tree description has been merged in 3.10-rc1,
this commit should go in 3.10-rc as well.
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    3 ++-
 arch/arm/boot/dts/armada-370.dtsi    |    3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..550eb77 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -33,7 +33,8 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&mpic>;
-		ranges = <0 0 0xd0000000 0x100000>;
+		ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
+			  0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
 
 		internal-regs {
 			compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index b2c1b5a..834c9be 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -29,7 +29,8 @@
 	};
 
 	soc {
-		ranges = <0 0xd0000000 0x100000>;
+		ranges = <0          0xd0000000 0x0100000 /* internal registers */
+			  0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
 		internal-regs {
 			system-controller at 18200 {
 				compatible = "marvell,armada-370-xp-system-controller";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:16 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:16 +0200
Subject: [PATCHv9 2/9] of/pci: Provide support for parsing PCI DT ranges
 property
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-3-git-send-email-thomas.petazzoni@free-electrons.com>

From: Andrew Murray <Andrew.Murray at arm.com>

This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to write archiecture independent host bridge
drivers and mitigate against further duplication of DT parsing code.

This patch can be used in the following way:

	struct of_pci_range_parser parser;
	struct of_pci_range range;

	if (of_pci_range_parser_init(&parser, np))
		; //no ranges property

	for_each_of_pci_range(&parser, &range) {

		/*
			directly access properties of the address range, e.g.:
			range.pci_space, range.pci_addr, range.cpu_addr,
			range.size, range.flags

			alternatively obtain a struct resource, e.g.:
			struct resource res;
			of_pci_range_to_resource(&range, np, &res);
		*/
	}

Additionally the implementation takes care of adjacent ranges and merges them
into a single range (as was the case with powerpc and microblaze).

Signed-off-by: Andrew Murray <Andrew.Murray at arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Reviewed-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Tested-by: Linus Walleij <linus.walleij at linaro.org>
Tested-by: Jingoo Han <jg1.han at samsung.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/of/address.c       |   67 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/of_address.h |   48 +++++++++++++++++++++++++++++++
 2 files changed, 115 insertions(+)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 04da786..fdd0636 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
 	return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
 }
 EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+
+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+				struct device_node *node)
+{
+	const int na = 3, ns = 2;
+	int rlen;
+
+	parser->node = node;
+	parser->pna = of_n_addr_cells(node);
+	parser->np = parser->pna + na + ns;
+
+	parser->range = of_get_property(node, "ranges", &rlen);
+	if (parser->range == NULL)
+		return -ENOENT;
+
+	parser->end = parser->range + rlen / sizeof(__be32);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
+
+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
+						struct of_pci_range *range)
+{
+	const int na = 3, ns = 2;
+
+	if (!range)
+		return NULL;
+
+	if (!parser->range || parser->range + parser->np > parser->end)
+		return NULL;
+
+	range->pci_space = parser->range[0];
+	range->flags = of_bus_pci_get_flags(parser->range);
+	range->pci_addr = of_read_number(parser->range + 1, ns);
+	range->cpu_addr = of_translate_address(parser->node,
+				parser->range + na);
+	range->size = of_read_number(parser->range + parser->pna + na, ns);
+
+	parser->range += parser->np;
+
+	/* Now consume following elements while they are contiguous */
+	while (parser->range + parser->np <= parser->end) {
+		u32 flags, pci_space;
+		u64 pci_addr, cpu_addr, size;
+
+		pci_space = be32_to_cpup(parser->range);
+		flags = of_bus_pci_get_flags(parser->range);
+		pci_addr = of_read_number(parser->range + 1, ns);
+		cpu_addr = of_translate_address(parser->node,
+				parser->range + na);
+		size = of_read_number(parser->range + parser->pna + na, ns);
+
+		if (flags != range->flags)
+			break;
+		if (pci_addr != range->pci_addr + range->size ||
+		    cpu_addr != range->cpu_addr + range->size)
+			break;
+
+		range->size += size;
+		parser->range += parser->np;
+	}
+
+	return range;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
+
 #endif /* CONFIG_PCI */
 
 /*
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index 0506eb5..4c2e6f2 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -4,6 +4,36 @@
 #include <linux/errno.h>
 #include <linux/of.h>
 
+struct of_pci_range_parser {
+	struct device_node *node;
+	const __be32 *range;
+	const __be32 *end;
+	int np;
+	int pna;
+};
+
+struct of_pci_range {
+	u32 pci_space;
+	u64 pci_addr;
+	u64 cpu_addr;
+	u64 size;
+	u32 flags;
+};
+
+#define for_each_of_pci_range(parser, range) \
+	for (; of_pci_range_parser_one(parser, range);)
+
+static inline void of_pci_range_to_resource(struct of_pci_range *range,
+					    struct device_node *np,
+					    struct resource *res)
+{
+	res->flags = range->flags;
+	res->start = range->cpu_addr;
+	res->end = range->cpu_addr + range->size - 1;
+	res->parent = res->child = res->sibling = NULL;
+	res->name = np->full_name;
+}
+
 #ifdef CONFIG_OF_ADDRESS
 extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
 extern bool of_can_translate_address(struct device_node *dev);
@@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
 #define pci_address_to_pio pci_address_to_pio
 #endif
 
+extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+			struct device_node *node);
+extern struct of_pci_range *of_pci_range_parser_one(
+					struct of_pci_range_parser *parser,
+					struct of_pci_range *range);
 #else /* CONFIG_OF_ADDRESS */
 #ifndef of_address_to_resource
 static inline int of_address_to_resource(struct device_node *dev, int index,
@@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
 {
 	return NULL;
 }
+
+static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+			struct device_node *node)
+{
+	return -1;
+}
+
+static inline struct of_pci_range *of_pci_range_parser_one(
+					struct of_pci_range_parser *parser,
+					struct of_pci_range *range)
+{
+	return NULL;
+}
 #endif /* CONFIG_OF_ADDRESS */
 
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:14 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:14 +0200
Subject: [PATCHv9 0/9] PCIe support for the Armada 370 and Armada XP SoCs
Message-ID: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

This series of patches introduces PCIe support for the Marvell Armada
370 and Armada XP. It has been rebased on top of 3.10-rc1, uses the
latest of/pci code from Andrew Murray, fixes the build failure that
was detected on powerpc64, and a regression that was introduced
between the v7 and the v8 of this patch set. See below for a detailed
changelog.

I'd like this code to be merged for 3.11.

For easier testing, the code has been pushed to:

  git://github.com/MISL-EBU-System-SW/mainline-public.git marvell-pcie-v9

This PATCHv9 follows:
 * PATCHv8, sent on April, 9th 2013
 * PATCHv7, sent on March, 27th 2013
 * PATCHv6, sent on March, 26st 2013
 * PATCHv5, sent on March, 21st 2013
 * PATCHv4, sent on March, 8th 2013
 * PATCHv3, sent on February, 12th 2013
 * PATCHv2, sent on January, 28th 2013
 * RFCv1, sent on December, 7th 2012

Changes between v8 and v9:

 * Rebased on top of 3.10-rc1. Since the PCIe Device Tree informations
   were merged in 3.10-rc1, it allowed to reduce quite significantly
   the size of this patch set.

 * A fix for the PCIe Device Tree information is added as the first
   patch, it adds a missing range entry to let the global PCIe
   memory/IO window addresses be correctly translated. It should be
   merged into the 3.10-rc cycle, to fix the hardware definition of
   the platform.

 * The patch set now integrates the latest version of Andrew Murray
   of/pci patch, that adds the PCI range parsing functions. The one
   I've integrated is:

   [PATCH v9 1/3] of/pci: Provide support for parsing PCI DT ranges property

 * I've fixed the PowerPC64 build problem, which was the reason why
   this driver was not taken for 3.10. In fact, the patch 'pci:
   infrastructure to add drivers in drivers/pci/host' was introducing
   a drivers/pci/host directory, with just an empty
   Makefile. Unfortunately, an empty Makefile doesn't trigger the
   generation of drivers/pci/host/built-in.o. So if you try to build
   the kernel with just this patch applied, and not the PCIe driver
   itself, the Makefile is empty, and the build breaks.

   To solve this, I've simply merged this patch with the PCIe driver
   patch itself. The PCIe driver patch adds the drivers/pci/host/
   directory and the related Kconfig/Makefile bits.

 * Fixed a regression in the driver introduced between the v7 and the
   v8. A #define <something> 1 was changed to #define <something>
   BIT(1), which obviously doesn't work. Changed to BIT(0), which is
   correct.

Changes between v7 and v8:

 * In the patch introducing the drivers/pci/host directory, add an
   empty drivers/pci/host/Makefile to ensure that the kernel still
   build. This Makefile will actually gets its first useful line when
   the Marvell PCIe driver gets added. Noted by Neil Greatorex.

 * Remove bogus (and useless) CFLAGS in drivers/pci/host/Makefile for
   the compilation of the Marvell PCIe driver. Noticed by Bjorn
   Helgaas.

 * Added missing parenthesis in the definition of the
   PCIE_BAR_CTRL_OFF macro. Noticed by Bjorn Helgaas.

 * Make mvebu_pcie_link_up() return 'bool' instead of 'int'. Suggested
   by Bjorn Helgaas.

 * Change mvebu_pcie_link_up(), mvebu_pcie_set_local_bus_nr(),
   mvebu_pcie_setup_wins(), mvebu_pcie_setup_hw(),
   mvebu_pcie_hw_rd_conf(), mvebu_pcie_hw_wr_conf() so that they take
   a 'struct mvebu_pcie_port *' instead of a 'void __iomem *' as first
   argument. The base address of the PCIe interface register are
   available using the 'base' field of 'struct
   mvebu_pcie_port'. Suggested by Bjorn Helgaas.

 * Fixed multi-line comments that should have been one line
   comments. Noticed by Bjorn Helgaas.

 * Fixed a for() loop in mvebu_pcie_setup_wins() to use the more
   conventional 'ii < 3' ending condition instead of 'i <=
   2'. Suggested by Bjorn Helgaas.

 * Add a #define instead of an hardcoded magic value when enabling
   interrupts A-D in mvebu_pcie_setup_hw(). Suggested by Bjorn
   Helgaas.

 * Add a PCIE_CONF_ADDR() to simplify the code in
   mvebu_pcie_hw_rd_conf() and mvebu_pcie_hw_wr_conf(). Suggested by
   Bjorn Helgaas.

 * Clarify the comments in mvebu_pcie_handle_iobase_change() and
   mvebu_pcie_handle_membase_change() so that it is clear we look at
   the new iobase/iolimit (respectively membase/memlimit)
   values. Suggested by Bjorn Helgaas.

 * Replace mvebu_pcie_find_port_by_bus() and
   mvebu_pcie_find_port_by_devfn() by a single mvebu_pcie_find_port()
   function, and simplify the mvebu_pcie_rd_conf() and
   mvebu_pcie_wr_conf() functions. Suggested by Bjorn Helgaas.

 * Fix the computation of the real I/O resource start and end
   addresses, according to the suggestions of Arnd Bergmann and Jason
   Gunthorpe.

 * Remove the MASK/OFFS definition, and use definitions more in the
   style of pci_regs.h. Suggested by Bjorn Helgaas.

 * Integrate the latest version of 'of/pci: Provide support for
   parsing PCI DT ranges property' from Andrew Murray, fixed according
   to the review of Rob Herring.

 * Added the Acked-by tags from Bjorn Helgaas on the PCI patches.

Changes between v6 and v7:

 * Use assigned-addresses in the DT subnodes for the MMIO PCIe
   registers, in order to align with what Thierry is doing on the
   Tegra PCIe driver.

 * Added empty 'ranges;' properties in the subnodes, as requested by
   Arnd. Note that due to this, it is not possible to remove the
   #address-cells and #size-cells properties from the subnodes, as
   Jason Gunthorpe requested, otherwise the DT compiler complains with:

     Warning (ranges_format): /soc/pcie-controller/pcie at 1,0 has empty
     "ranges" property but its #address-cells (2) differs from
     /soc/pcie-controller (3)

     Warning (ranges_format): /soc/pcie-controller/pcie at 1,0 has empty
     "ranges" property but its #size-cells (1) differs from
     /soc/pcie-controller (2)

 * Use the new RFCv3 patch from Andrew Murray for 'of/pci: Provide
   support for parsing PCI DT ranges property'.

 * Updated the DT binding documentation accordingly.

Changes between v5 and v6:

 * Use pci_create_root_bus() + pci_scan_child_bus() instead of
   pci_scan_root_bus(). This is needed to be able to add MSI support
   later on. Moreover Thierry Reding suggested that
   pci_scan_root_bus() "does a pci_bus_add_devices(), which is called
   again in pci_common_init() in the ARM code". Thanks Thierry for
   pointing out this issue.

Changes between v4 and v5:

 * Rebased on top of 3.9-rc2 + the new mvebu-mbus driver (v3).

 * Changed the names of the PCI DT sub-nodes to match the OF
   specifications: they should be named pcie at DD,FF where DD is the
   device number and FF the function number. Requested by Mitch
   Bradley.

 * Add the device_type = "pci" property at the pcie-controller
   level. Requested by Mitch Bradley.

 * Drop patch 'of/pci: Add of_pci_get_bus() function' because it
   wasn't actually used in the rest of the patch series.

 * Updated the patch 'of/pci: Provide support for parsing PCI DT
   ranges property' to use the latest version proposed by Andrew
   Murray on the devicetree-discuss@ mailing list.

Changes between v3 and v4:

 * Rebased on top of 3.9-rc1.

 * Drop patch "ARM: pci: Allow passing per-controller private data"
   because it was merged in 3.9.

 * Drop patch "lib: devres: don't enclose pcim_*() functions in
   CONFIG_HAS_IOPORT", because it was merged in 3.9.

 * Added CONFIG_PCI_MVEBU=y in mvebu_defconfig, so that the right PCI
   host controller driver is automatically enabled.

 * Instead of using the DT 'ranges' property to encode the PCIe
   register ranges, use a 'reg' property on the main PCIe controller
   DT node together with a 'reg-names' property. Suggested by Jason
   Gunthorpe.

 * Don't select PCI_SW_HOST_BRIDGE and PCI_SW_PCI_PCI_BRIDGE, they
   don't exist anymore. Reported by Bjorn Helgaas.

 * Added support for the Armada XP GP board.

 * Fix the 'ranges' property so that the memory range is an identity
   map between CPU addresses and bus addresses. Suggested by Arnd
   Bergmann.

 * Changed the 'ranges' property to have the I/O region after the
   memory region.

 * Use the new mvebu-mbus driver API to create/remove address decoding
   windows when needed. This remove the need to include
   <mach/addr-map.h>. Requested by Arnd Bergmann.

 * Include directly into the driver the few common PCIe functions we
   were using from arch/arm/plat-orion/pcie.c. This allows to remove
   the inclusion of <plat/pcie.h>. Requested by Arnd Bergmann.

 * Directly set up the address decoding windows when the memory
   base/limit and I/O base/limit are configured in the PCI-to-PCI
   bridge instead of relying on the memory and I/O accesses being
   enabled in the PCI_COMMAND register. Suggested by Bjorn Helgaas.

 * Added some comments on top of the calculations of the I/O
   base/limit and memory base/limit. Suggested by Arnd Bergmann.

 * Changed a bit the way the "realio" resource is created, from
   suggestions given by Arnd Bergmann.

 * Updated the Device Tree binding documentation. Reported by Jason
   Gunthorpe.

 * Instead of using "marvell,armada-370-xp-pcie" as the DT compatible
   string, use two separate compatible strings:
   "marvell,armada-370-pcie" and "marvell,armada-xp-pcie". For now,
   the driver does the same thing for both.

Changes between v2 and v3:

 * Use of_irq_map_pci() instead of of_irq_map_raw(), as suggested by
   Andrew Murray. In order to do this, we moved the interrupt-map and
   interrupt-map-mask DT properties from the main PCIe controller node
   to the DT subnodes representing each PCIe interface.

 * Remove the usage of the emulated host bridge.

 * Move the emulated PCI-to-PCI bridge code into the Marvell PCI
   driver itself, in order to allow a tighter integration. Suggested
   by Bjorn Helgaas and Jason Gunthorpe.

 * Make the allocation of address decoding windows dynamic: it's when
   memory accesses or I/O accesses are enabled at the PCI-to-PCI
   bridge level that we allocate and setup the corresponding address
   decoding window. Requested by Bjorn Helgaas.

 * Fixed the implementation of I/O accesses to use I/O addresses that
   fall within the normal IO_SPACE_LIMIT. This required using the
   "remap" functionality of address decoding windows, and therefore
   some changes in the address decoding window allocator. Follows a
   long discussion about I/O accesses.

 * Set up a correct bus number in the configuration of the PCIe
   interfaces so that we don't have to fake bus numbers
   anymore. Requested by Jason Gunthorpe.

 * Fix the of_pci_get_devfn() implementation according to Stephen
   Warren's comment.

 * Use CFLAGS_ instead of ccflags to add the mach-mvebu and plat-orion
   include paths when building the pci-mvebu driver. This ensures that
   the include paths are only added when building this specific
   driver. Requested by Stephen Warren.

 * Fix the ->resource_align() to only apply on bus 0 (the one on which
   the emulated PCI-to-PCI bridges sit), and to request an alignment
   on the size of the window (and not only 64 KB for I/O windows and 1
   MB for memory windows).

 * Clarified the commit log of "clk: mvebu: create parent-child
   relation for PCIe clocks on Armada 370"

Thanks,

Thomas

Andrew Murray (1):
  of/pci: Provide support for parsing PCI DT ranges property

Thierry Reding (2):
  of/pci: Add of_pci_get_devfn() function
  of/pci: Add of_pci_parse_bus_range() function

Thomas Petazzoni (6):
  arm: mvebu: fix the 'ranges' property to handle PCIe
  clk: mvebu: create parent-child relation for PCIe clocks on Armada
    370
  clk: mvebu: add more PCIe clocks for Armada XP
  pci: PCIe driver for Marvell Armada 370/XP systems
  arm: mvebu: PCIe support is now available on mvebu
  arm: mvebu: update defconfig with PCI and USB support

 .../devicetree/bindings/pci/mvebu-pci.txt          |  220 +++++
 arch/arm/boot/dts/armada-370-xp.dtsi               |    3 +-
 arch/arm/boot/dts/armada-370.dtsi                  |    3 +-
 arch/arm/configs/mvebu_defconfig                   |    3 +
 arch/arm/mach-mvebu/Kconfig                        |    2 +
 drivers/clk/mvebu/clk-gating-ctrl.c                |   18 +-
 drivers/of/address.c                               |   67 ++
 drivers/of/of_pci.c                                |   59 +-
 drivers/pci/Kconfig                                |    2 +
 drivers/pci/Makefile                               |    3 +
 drivers/pci/host/Kconfig                           |    8 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pci-mvebu.c                       |  879 ++++++++++++++++++++
 include/linux/of_address.h                         |   48 ++
 include/linux/of_pci.h                             |    2 +
 15 files changed, 1305 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
 create mode 100644 drivers/pci/host/Kconfig
 create mode 100644 drivers/pci/host/Makefile
 create mode 100644 drivers/pci/host/pci-mvebu.c

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:18 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:18 +0200
Subject: [PATCHv9 4/9] of/pci: Add of_pci_parse_bus_range() function
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-5-git-send-email-thomas.petazzoni@free-electrons.com>

From: Thierry Reding <thierry.reding at avionic-design.de>

This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 drivers/of/of_pci.c    |   25 +++++++++++++++++++++++++
 include/linux/of_pci.h |    1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 4dd7b9b..42c687a 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -64,3 +64,28 @@ int of_pci_get_devfn(struct device_node *np)
 	return (be32_to_cpup(reg) >> 8) & 0xff;
 }
 EXPORT_SYMBOL_GPL(of_pci_get_devfn);
+
+/**
+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
+ * @node: device node
+ * @res: address to a struct resource to return the bus-range
+ *
+ * Returns 0 on success or a negative error-code on failure.
+ */
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
+{
+	const __be32 *values;
+	int len;
+
+	values = of_get_property(node, "bus-range", &len);
+	if (!values || len < sizeof(*values) * 2)
+		return -EINVAL;
+
+	res->name = node->name;
+	res->start = be32_to_cpup(values++);
+	res->end = be32_to_cpup(values);
+	res->flags = IORESOURCE_BUS;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 91ec484..7a04826 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -11,5 +11,6 @@ struct device_node;
 struct device_node *of_pci_find_child_device(struct device_node *parent,
 					     unsigned int devfn);
 int of_pci_get_devfn(struct device_node *np);
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 
 #endif
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:17 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:17 +0200
Subject: [PATCHv9 3/9] of/pci: Add of_pci_get_devfn() function
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-4-git-send-email-thomas.petazzoni@free-electrons.com>

From: Thierry Reding <thierry.reding at avionic-design.de>

This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/of/of_pci.c    |   34 +++++++++++++++++++++++++++++-----
 include/linux/of_pci.h |    1 +
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 13e37e2..4dd7b9b 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -5,14 +5,15 @@
 #include <asm/prom.h>
 
 static inline int __of_pci_pci_compare(struct device_node *node,
-				       unsigned int devfn)
+				       unsigned int data)
 {
-	unsigned int size;
-	const __be32 *reg = of_get_property(node, "reg", &size);
+	int devfn;
 
-	if (!reg || size < 5 * sizeof(__be32))
+	devfn = of_pci_get_devfn(node);
+	if (devfn < 0)
 		return 0;
-	return ((be32_to_cpup(&reg[0]) >> 8) & 0xff) == devfn;
+
+	return devfn == data;
 }
 
 struct device_node *of_pci_find_child_device(struct device_node *parent,
@@ -40,3 +41,26 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(of_pci_find_child_device);
+
+/**
+ * of_pci_get_devfn() - Get device and function numbers for a device node
+ * @np: device node
+ *
+ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
+ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
+ * and function numbers respectively. On error a negative error code is
+ * returned.
+ */
+int of_pci_get_devfn(struct device_node *np)
+{
+	unsigned int size;
+	const __be32 *reg;
+
+	reg = of_get_property(np, "reg", &size);
+
+	if (!reg || size < 5 * sizeof(__be32))
+		return -EINVAL;
+
+	return (be32_to_cpup(reg) >> 8) & 0xff;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_devfn);
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index bb115de..91ec484 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -10,5 +10,6 @@ int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq);
 struct device_node;
 struct device_node *of_pci_find_child_device(struct device_node *parent,
 					     unsigned int devfn);
+int of_pci_get_devfn(struct device_node *np);
 
 #endif
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:19 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:19 +0200
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe
 clocks on Armada 370
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>

The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 drivers/clk/mvebu/clk-gating-ctrl.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index ebf141d..b35785a 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
 	{ "pex1_en", NULL,  2 },
 	{ "ge1", NULL, 3 },
 	{ "ge0", NULL, 4 },
-	{ "pex0", NULL, 5 },
-	{ "pex1", NULL, 9 },
+	{ "pex0", "pex0_en", 5 },
+	{ "pex1", "pex1_en", 9 },
 	{ "sata0", NULL, 15 },
 	{ "sdio", NULL, 17 },
 	{ "tdm", NULL, 25 },
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:22 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:22 +0200
Subject: [PATCHv9 8/9] arm: mvebu: PCIe support is now available on mvebu
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-9-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/Kconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb..381062d 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -15,6 +15,8 @@ config ARCH_MVEBU
 	select MVEBU_CLK_GATING
 	select MVEBU_MBUS
 	select ZONE_DMA if ARM_LPAE
+	select MIGHT_HAVE_PCI
+	select PCI_QUIRKS if PCI
 
 if ARCH_MVEBU
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:20 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:20 +0200
Subject: [PATCHv9 6/9] clk: mvebu: add more PCIe clocks for Armada XP
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-7-git-send-email-thomas.petazzoni@free-electrons.com>

The current revision of the datasheet only mentions the gatable clocks
for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
interfaces. After confirmation with Marvell engineers, this patch adds
the missing gatable clocks for those PCIe interfaces.

It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 drivers/clk/mvebu/clk-gating-ctrl.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index b35785a..2f03723 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
 	{ "ge2", NULL,  2 },
 	{ "ge1", NULL, 3 },
 	{ "ge0", NULL, 4 },
-	{ "pex0", NULL, 5 },
-	{ "pex1", NULL, 6 },
-	{ "pex2", NULL, 7 },
-	{ "pex3", NULL, 8 },
+	{ "pex00", NULL, 5 },
+	{ "pex01", NULL, 6 },
+	{ "pex02", NULL, 7 },
+	{ "pex03", NULL, 8 },
+	{ "pex10", NULL, 9 },
+	{ "pex11", NULL, 10 },
+	{ "pex12", NULL, 11 },
+	{ "pex13", NULL, 12 },
 	{ "bp", NULL, 13 },
 	{ "sata0lnk", NULL, 14 },
 	{ "sata0", "sata0lnk", 15 },
@@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
 	{ "xor0", NULL, 22 },
 	{ "crypto", NULL, 23 },
 	{ "tdm", NULL, 25 },
+	{ "pex20", NULL, 26 },
+	{ "pex30", NULL, 27 },
 	{ "xor1", NULL, 28 },
 	{ "sata1lnk", NULL, 29 },
 	{ "sata1", "sata1lnk", 30 },
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:23 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:23 +0200
Subject: [PATCHv9 9/9] arm: mvebu: update defconfig with PCI and USB support
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-10-git-send-email-thomas.petazzoni@free-electrons.com>

Now that we have the necessary drivers and Device Tree informations to
support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
option.

Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
connected on the PCIe bus, enable the corresponding options as well.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/configs/mvebu_defconfig |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae0..966281e 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
@@ -60,6 +62,7 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_MMC=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
-- 
1.7.9.5



From arnd at arndb.de  Wed May 15 09:25:49 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 15:25:49 +0200
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1368571955-6652-5-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-5-git-send-email-dinguyen@altera.com>
Message-ID: <201305151525.50005.arnd@arndb.de>

On Wednesday 15 May 2013, dinguyen at altera.com wrote:
> +
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> +
> +extern void __iomem *sys_manager_base_addr;

This is not acceptable, you cannot just reference external symbols
from one driver in another, without a proper interface.

Please explain what the functionality is that you need here, then
we can help you find the proper interface. My guess is that you
need either the functionality provided by drivers/reset/
or drivers/mfd/syscon.c.

> +       if (of_property_read_u32(dev->of_node, "pwr-en", &pwr_en)) {
> +               dev_info(dev, "couldn't determine pwr-en, assuming pwr-en = 0\n");
> +               pwr_en = 0;
> +       }
> +
> +       /* Set PWREN bit */
> +       mci_writel(host, PWREN, pwr_en);

If you add new properties, you have to document them in
Documentations/devicetree/bindings/*.

What is the requirement for this property? Is there no way to 
automatically power the card on/off using the normal
dw_mci_set_ios function?

The rest of this patch looks ok to me.

	Arnd


From thomas.petazzoni at free-electrons.com  Wed May 15 09:25:21 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:25:21 +0200
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>

This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.

The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.

Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.

In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas at google.com>
---
 .../devicetree/bindings/pci/mvebu-pci.txt          |  220 +++++
 drivers/pci/Kconfig                                |    2 +
 drivers/pci/Makefile                               |    3 +
 drivers/pci/host/Kconfig                           |    8 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pci-mvebu.c                       |  879 ++++++++++++++++++++
 6 files changed, 1113 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
 create mode 100644 drivers/pci/host/Kconfig
 create mode 100644 drivers/pci/host/Makefile
 create mode 100644 drivers/pci/host/pci-mvebu.c

diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
new file mode 100644
index 0000000..eb69d92
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -0,0 +1,220 @@
+* Marvell EBU PCIe interfaces
+
+Mandatory properties:
+- compatible: one of the following values:
+    marvell,armada-370-pcie
+    marvell,armada-xp-pcie
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- bus-range: PCI bus numbers covered
+- device_type, set to "pci"
+- ranges: ranges for the PCI memory and I/O regions, as well as the
+  MMIO registers to control the PCIe interfaces.
+
+In addition, the Device Tree node must have sub-nodes describing each
+PCIe interface, having the following mandatory properties:
+- reg: used only for interrupt mapping, so only the first four bytes
+  are used to refer to the correct bus number and device number.
+- assigned-addresses: reference to the MMIO registers used to control
+  this PCIe interface.
+- clocks: the clock associated to this PCIe interface
+- marvell,pcie-port: the physical PCIe port number
+- status: either "disabled" or "okay"
+- device_type, set to "pci"
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- ranges, empty property.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+
+and the following optional properties:
+- marvell,pcie-lane: the physical PCIe lane number, for ports having
+  multiple lanes. If this property is not found, we assume that the
+  value is 0.
+
+Example:
+
+pcie-controller {
+	compatible = "marvell,armada-xp-pcie";
+	status = "disabled";
+	device_type = "pci";
+
+	#address-cells = <3>;
+	#size-cells = <2>;
+
+	bus-range = <0x00 0xff>;
+
+	ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+		  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+		  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+		  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+		  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+		  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+		  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+		  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
+		  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
+		  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
+		  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+		  0x81000000 0 0	  0xe8000000 0 0x00100000>; /* downstream I/O */
+
+	pcie at 1,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+		reg = <0x0800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 58>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 5>;
+		status = "disabled";
+	};
+
+	pcie at 2,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+		reg = <0x1000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 59>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <1>;
+		clocks = <&gateclk 6>;
+		status = "disabled";
+	};
+
+	pcie at 3,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+		reg = <0x1800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 60>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <2>;
+		clocks = <&gateclk 7>;
+		status = "disabled";
+	};
+
+	pcie at 4,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+		reg = <0x2000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 61>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <3>;
+		clocks = <&gateclk 8>;
+		status = "disabled";
+	};
+
+	pcie at 5,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+		reg = <0x2800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 62>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 9>;
+		status = "disabled";
+	};
+
+	pcie at 6,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+		reg = <0x3000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 63>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <1>;
+		clocks = <&gateclk 10>;
+		status = "disabled";
+	};
+
+	pcie at 7,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+		reg = <0x3800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 64>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <2>;
+		clocks = <&gateclk 11>;
+		status = "disabled";
+	};
+
+	pcie at 8,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+		reg = <0x4000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 65>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <3>;
+		clocks = <&gateclk 12>;
+		status = "disabled";
+	};
+	pcie at 9,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+		reg = <0x4800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 99>;
+		marvell,pcie-port = <2>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 26>;
+		status = "disabled";
+	};
+
+	pcie at 10,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+		reg = <0x5000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 103>;
+		marvell,pcie-port = <3>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 27>;
+		status = "disabled";
+	};
+};
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6d51aa6..ac45398 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -119,3 +119,5 @@ config PCI_IOAPIC
 config PCI_LABEL
 	def_bool y if (DMI || ACPI)
 	select NLS
+
+source "drivers/pci/host/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 0c3efcf..6ebf5bf 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 obj-$(CONFIG_OF) += of.o
 
 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
+
+# PCI host controller drivers
+obj-y += host/
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
new file mode 100644
index 0000000..6918fbc
--- /dev/null
+++ b/drivers/pci/host/Kconfig
@@ -0,0 +1,8 @@
+menu "PCI host controller drivers"
+	depends on PCI
+
+config PCI_MVEBU
+	bool "Marvell EBU PCIe controller"
+	depends on ARCH_MVEBU
+
+endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
new file mode 100644
index 0000000..5ea2d8b
--- /dev/null
+++ b/drivers/pci/host/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
new file mode 100644
index 0000000..b0ee63b
--- /dev/null
+++ b/drivers/pci/host/pci-mvebu.c
@@ -0,0 +1,879 @@
+/*
+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mbus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF		0x0000
+#define PCIE_CMD_OFF		0x0004
+#define PCIE_DEV_REV_OFF	0x0008
+#define PCIE_BAR_LO_OFF(n)	(0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)	(0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF	0x0128
+#define PCIE_BAR_CTRL_OFF(n)	(0x1804 + (((n) - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)	(0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)	(0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n)	(0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF	0x1880
+#define PCIE_WIN5_BASE_OFF	0x1884
+#define PCIE_WIN5_REMAP_OFF	0x188c
+#define PCIE_CONF_ADDR_OFF	0x18f8
+#define  PCIE_CONF_ADDR_EN		0x80000000
+#define  PCIE_CONF_REG(r)		((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)		(((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)		(((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)		(((f) & 0x7) << 8)
+#define  PCIE_CONF_ADDR(bus, devfn, where) \
+	(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
+	 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
+	 PCIE_CONF_ADDR_EN)
+#define PCIE_CONF_DATA_OFF	0x18fc
+#define PCIE_MASK_OFF		0x1910
+#define  PCIE_MASK_ENABLE_INTS          0x0f000000
+#define PCIE_CTRL_OFF		0x1a00
+#define  PCIE_CTRL_X1_MODE		0x0001
+#define PCIE_STAT_OFF		0x1a04
+#define  PCIE_STAT_BUS                  0xff00
+#define  PCIE_STAT_LINK_DOWN		BIT(0)
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET		BIT(20)
+
+/*
+ * This product ID is registered by Marvell, and used when the Marvell
+ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
+ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
+ * bridge.
+ */
+#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
+
+/* PCI configuration space of a PCI-to-PCI bridge */
+struct mvebu_sw_pci_bridge {
+	u16 vendor;
+	u16 device;
+	u16 command;
+	u16 status;
+	u16 class;
+	u8 interface;
+	u8 revision;
+	u8 bist;
+	u8 header_type;
+	u8 latency_timer;
+	u8 cache_line_size;
+	u32 bar[2];
+	u8 primary_bus;
+	u8 secondary_bus;
+	u8 subordinate_bus;
+	u8 secondary_latency_timer;
+	u8 iobase;
+	u8 iolimit;
+	u16 secondary_status;
+	u16 membase;
+	u16 memlimit;
+	u16 prefmembase;
+	u16 prefmemlimit;
+	u32 prefbaseupper;
+	u32 preflimitupper;
+	u16 iobaseupper;
+	u16 iolimitupper;
+	u8 cappointer;
+	u8 reserved1;
+	u16 reserved2;
+	u32 romaddr;
+	u8 intline;
+	u8 intpin;
+	u16 bridgectrl;
+};
+
+struct mvebu_pcie_port;
+
+/* Structure representing all PCIe interfaces */
+struct mvebu_pcie {
+	struct platform_device *pdev;
+	struct mvebu_pcie_port *ports;
+	struct resource io;
+	struct resource realio;
+	struct resource mem;
+	struct resource busn;
+	int nports;
+};
+
+/* Structure representing one PCIe interface */
+struct mvebu_pcie_port {
+	char *name;
+	void __iomem *base;
+	spinlock_t conf_lock;
+	int haslink;
+	u32 port;
+	u32 lane;
+	int devfn;
+	struct clk *clk;
+	struct mvebu_sw_pci_bridge bridge;
+	struct device_node *dn;
+	struct mvebu_pcie *pcie;
+	phys_addr_t memwin_base;
+	size_t memwin_size;
+	phys_addr_t iowin_base;
+	size_t iowin_size;
+};
+
+static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
+{
+	return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
+{
+	u32 stat;
+
+	stat = readl(port->base + PCIE_STAT_OFF);
+	stat &= ~PCIE_STAT_BUS;
+	stat |= nr << 8;
+	writel(stat, port->base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
+{
+	const struct mbus_dram_target_info *dram;
+	u32 size;
+	int i;
+
+	dram = mv_mbus_dram_info();
+
+	/* First, disable and clear BARs and windows. */
+	for (i = 1; i < 3; i++) {
+		writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
+		writel(0, port->base + PCIE_BAR_LO_OFF(i));
+		writel(0, port->base + PCIE_BAR_HI_OFF(i));
+	}
+
+	for (i = 0; i < 5; i++) {
+		writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
+		writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
+		writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+	}
+
+	writel(0, port->base + PCIE_WIN5_CTRL_OFF);
+	writel(0, port->base + PCIE_WIN5_BASE_OFF);
+	writel(0, port->base + PCIE_WIN5_REMAP_OFF);
+
+	/* Setup windows for DDR banks.  Count total DDR size on the fly. */
+	size = 0;
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		writel(cs->base & 0xffff0000,
+		       port->base + PCIE_WIN04_BASE_OFF(i));
+		writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+		writel(((cs->size - 1) & 0xffff0000) |
+			(cs->mbus_attr << 8) |
+			(dram->mbus_dram_target_id << 4) | 1,
+		       port->base + PCIE_WIN04_CTRL_OFF(i));
+
+		size += cs->size;
+	}
+
+	/* Round up 'size' to the nearest power of two. */
+	if ((size & (size - 1)) != 0)
+		size = 1 << fls(size);
+
+	/* Setup BAR[1] to all DRAM banks. */
+	writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
+	writel(0, port->base + PCIE_BAR_HI_OFF(1));
+	writel(((size - 1) & 0xffff0000) | 1,
+	       port->base + PCIE_BAR_CTRL_OFF(1));
+}
+
+static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
+{
+	u16 cmd;
+	u32 mask;
+
+	/* Point PCIe unit MBUS decode windows to DRAM space. */
+	mvebu_pcie_setup_wins(port);
+
+	/* Master + slave enable. */
+	cmd = readw(port->base + PCIE_CMD_OFF);
+	cmd |= PCI_COMMAND_IO;
+	cmd |= PCI_COMMAND_MEMORY;
+	cmd |= PCI_COMMAND_MASTER;
+	writew(cmd, port->base + PCIE_CMD_OFF);
+
+	/* Enable interrupt lines A-D. */
+	mask = readl(port->base + PCIE_MASK_OFF);
+	mask |= PCIE_MASK_ENABLE_INTS;
+	writel(mask, port->base + PCIE_MASK_OFF);
+}
+
+static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
+				 struct pci_bus *bus,
+				 u32 devfn, int where, int size, u32 *val)
+{
+	writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+	       port->base + PCIE_CONF_ADDR_OFF);
+
+	*val = readl(port->base + PCIE_CONF_DATA_OFF);
+
+	if (size == 1)
+		*val = (*val >> (8 * (where & 3))) & 0xff;
+	else if (size == 2)
+		*val = (*val >> (8 * (where & 3))) & 0xffff;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
+				 struct pci_bus *bus,
+				 u32 devfn, int where, int size, u32 val)
+{
+	int ret = PCIBIOS_SUCCESSFUL;
+
+	writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+	       port->base + PCIE_CONF_ADDR_OFF);
+
+	if (size == 4)
+		writel(val, port->base + PCIE_CONF_DATA_OFF);
+	else if (size == 2)
+		writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+	else if (size == 1)
+		writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+	else
+		ret = PCIBIOS_BAD_REGISTER_NUMBER;
+
+	return ret;
+}
+
+static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
+{
+	phys_addr_t iobase;
+
+	/* Are the new iobase/iolimit values invalid? */
+	if (port->bridge.iolimit < port->bridge.iobase ||
+	    port->bridge.iolimitupper < port->bridge.iobaseupper) {
+
+		/* If a window was configured, remove it */
+		if (port->iowin_base) {
+			mvebu_mbus_del_window(port->iowin_base,
+					      port->iowin_size);
+			port->iowin_base = 0;
+			port->iowin_size = 0;
+		}
+
+		return;
+	}
+
+	/*
+	 * We read the PCI-to-PCI bridge emulated registers, and
+	 * calculate the base address and size of the address decoding
+	 * window to setup, according to the PCI-to-PCI bridge
+	 * specifications. iobase is the bus address, port->iowin_base
+	 * is the CPU address.
+	 */
+	iobase = ((port->bridge.iobase & 0xF0) << 8) |
+		(port->bridge.iobaseupper << 16);
+	port->iowin_base = port->pcie->io.start + iobase;
+	port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
+			    (port->bridge.iolimitupper << 16)) -
+			    iobase);
+
+	mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
+					  port->iowin_size,
+					  iobase,
+					  MVEBU_MBUS_PCI_IO);
+
+	pci_ioremap_io(iobase, port->iowin_base);
+}
+
+static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
+{
+	/* Are the new membase/memlimit values invalid? */
+	if (port->bridge.memlimit < port->bridge.membase) {
+
+		/* If a window was configured, remove it */
+		if (port->memwin_base) {
+			mvebu_mbus_del_window(port->memwin_base,
+					      port->memwin_size);
+			port->memwin_base = 0;
+			port->memwin_size = 0;
+		}
+
+		return;
+	}
+
+	/*
+	 * We read the PCI-to-PCI bridge emulated registers, and
+	 * calculate the base address and size of the address decoding
+	 * window to setup, according to the PCI-to-PCI bridge
+	 * specifications.
+	 */
+	port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);
+	port->memwin_size  =
+		(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
+		port->memwin_base;
+
+	mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
+					  port->memwin_size,
+					  MVEBU_MBUS_NO_REMAP,
+					  MVEBU_MBUS_PCI_MEM);
+}
+
+/*
+ * Initialize the configuration space of the PCI-to-PCI bridge
+ * associated with the given PCIe interface.
+ */
+static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
+{
+	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+	memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
+
+	bridge->status = PCI_STATUS_CAP_LIST;
+	bridge->class = PCI_CLASS_BRIDGE_PCI;
+	bridge->vendor = PCI_VENDOR_ID_MARVELL;
+	bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
+	bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
+	bridge->cache_line_size = 0x10;
+
+	/* We support 32 bits I/O addressing */
+	bridge->iobase = PCI_IO_RANGE_TYPE_32;
+	bridge->iolimit = PCI_IO_RANGE_TYPE_32;
+}
+
+/*
+ * Read the configuration space of the PCI-to-PCI bridge associated to
+ * the given PCIe interface.
+ */
+static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
+				  unsigned int where, int size, u32 *value)
+{
+	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+	switch (where & ~3) {
+	case PCI_VENDOR_ID:
+		*value = bridge->device << 16 | bridge->vendor;
+		break;
+
+	case PCI_COMMAND:
+		*value = bridge->status << 16 | bridge->command;
+		break;
+
+	case PCI_CLASS_REVISION:
+		*value = bridge->class << 16 | bridge->interface << 8 |
+			 bridge->revision;
+		break;
+
+	case PCI_CACHE_LINE_SIZE:
+		*value = bridge->bist << 24 | bridge->header_type << 16 |
+			 bridge->latency_timer << 8 | bridge->cache_line_size;
+		break;
+
+	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+		*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
+		break;
+
+	case PCI_PRIMARY_BUS:
+		*value = (bridge->secondary_latency_timer << 24 |
+			  bridge->subordinate_bus         << 16 |
+			  bridge->secondary_bus           <<  8 |
+			  bridge->primary_bus);
+		break;
+
+	case PCI_IO_BASE:
+		*value = (bridge->secondary_status << 16 |
+			  bridge->iolimit          <<  8 |
+			  bridge->iobase);
+		break;
+
+	case PCI_MEMORY_BASE:
+		*value = (bridge->memlimit << 16 | bridge->membase);
+		break;
+
+	case PCI_PREF_MEMORY_BASE:
+		*value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
+		break;
+
+	case PCI_PREF_BASE_UPPER32:
+		*value = bridge->prefbaseupper;
+		break;
+
+	case PCI_PREF_LIMIT_UPPER32:
+		*value = bridge->preflimitupper;
+		break;
+
+	case PCI_IO_BASE_UPPER16:
+		*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
+		break;
+
+	case PCI_ROM_ADDRESS1:
+		*value = 0;
+		break;
+
+	default:
+		*value = 0xffffffff;
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	if (size == 2)
+		*value = (*value >> (8 * (where & 3))) & 0xffff;
+	else if (size == 1)
+		*value = (*value >> (8 * (where & 3))) & 0xff;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/* Write to the PCI-to-PCI bridge configuration space */
+static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
+				     unsigned int where, int size, u32 value)
+{
+	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+	u32 mask, reg;
+	int err;
+
+	if (size == 4)
+		mask = 0x0;
+	else if (size == 2)
+		mask = ~(0xffff << ((where & 3) * 8));
+	else if (size == 1)
+		mask = ~(0xff << ((where & 3) * 8));
+	else
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
+	if (err)
+		return err;
+
+	value = (reg & mask) | value << ((where & 3) * 8);
+
+	switch (where & ~3) {
+	case PCI_COMMAND:
+		bridge->command = value & 0xffff;
+		bridge->status = value >> 16;
+		break;
+
+	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+		bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
+		break;
+
+	case PCI_IO_BASE:
+		/*
+		 * We also keep bit 1 set, it is a read-only bit that
+		 * indicates we support 32 bits addressing for the
+		 * I/O
+		 */
+		bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
+		bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
+		bridge->secondary_status = value >> 16;
+		mvebu_pcie_handle_iobase_change(port);
+		break;
+
+	case PCI_MEMORY_BASE:
+		bridge->membase = value & 0xffff;
+		bridge->memlimit = value >> 16;
+		mvebu_pcie_handle_membase_change(port);
+		break;
+
+	case PCI_PREF_MEMORY_BASE:
+		bridge->prefmembase = value & 0xffff;
+		bridge->prefmemlimit = value >> 16;
+		break;
+
+	case PCI_PREF_BASE_UPPER32:
+		bridge->prefbaseupper = value;
+		break;
+
+	case PCI_PREF_LIMIT_UPPER32:
+		bridge->preflimitupper = value;
+		break;
+
+	case PCI_IO_BASE_UPPER16:
+		bridge->iobaseupper = value & 0xffff;
+		bridge->iolimitupper = value >> 16;
+		mvebu_pcie_handle_iobase_change(port);
+		break;
+
+	case PCI_PRIMARY_BUS:
+		bridge->primary_bus             = value & 0xff;
+		bridge->secondary_bus           = (value >> 8) & 0xff;
+		bridge->subordinate_bus         = (value >> 16) & 0xff;
+		bridge->secondary_latency_timer = (value >> 24) & 0xff;
+		mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
+		break;
+
+	default:
+		break;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+	return sys->private_data;
+}
+
+static struct mvebu_pcie_port *
+mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
+		     int devfn)
+{
+	int i;
+
+	for (i = 0; i < pcie->nports; i++) {
+		struct mvebu_pcie_port *port = &pcie->ports[i];
+		if (bus->number == 0 && port->devfn == devfn)
+			return port;
+		if (bus->number != 0 &&
+		    port->bridge.secondary_bus == bus->number)
+			return port;
+	}
+
+	return NULL;
+}
+
+/* PCI configuration space write function */
+static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+			      int where, int size, u32 val)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+	struct mvebu_pcie_port *port;
+	unsigned long flags;
+	int ret;
+
+	port = mvebu_pcie_find_port(pcie, bus, devfn);
+	if (!port)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	/* Access the emulated PCI-to-PCI bridge */
+	if (bus->number == 0)
+		return mvebu_sw_pci_bridge_write(port, where, size, val);
+
+	if (!port->haslink || PCI_SLOT(devfn) != 0)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	/* Access the real PCIe interface */
+	spin_lock_irqsave(&port->conf_lock, flags);
+	ret = mvebu_pcie_hw_wr_conf(port, bus,
+				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+				    where, size, val);
+	spin_unlock_irqrestore(&port->conf_lock, flags);
+
+	return ret;
+}
+
+/* PCI configuration space read function */
+static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+			      int size, u32 *val)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+	struct mvebu_pcie_port *port;
+	unsigned long flags;
+	int ret;
+
+	port = mvebu_pcie_find_port(pcie, bus, devfn);
+	if (!port) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/* Access the emulated PCI-to-PCI bridge */
+	if (bus->number == 0)
+		return mvebu_sw_pci_bridge_read(port, where, size, val);
+
+	if (!port->haslink || PCI_SLOT(devfn) != 0) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/* Access the real PCIe interface */
+	spin_lock_irqsave(&port->conf_lock, flags);
+	ret = mvebu_pcie_hw_rd_conf(port, bus,
+				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+				    where, size, val);
+	spin_unlock_irqrestore(&port->conf_lock, flags);
+
+	return ret;
+}
+
+static struct pci_ops mvebu_pcie_ops = {
+	.read = mvebu_pcie_rd_conf,
+	.write = mvebu_pcie_wr_conf,
+};
+
+static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(sys);
+	int i;
+
+	pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
+	pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
+	pci_add_resource(&sys->resources, &pcie->busn);
+
+	for (i = 0; i < pcie->nports; i++) {
+		struct mvebu_pcie_port *port = &pcie->ports[i];
+		mvebu_pcie_setup_hw(port);
+	}
+
+	return 1;
+}
+
+static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct of_irq oirq;
+	int ret;
+
+	ret = of_irq_map_pci(dev, &oirq);
+	if (ret)
+		return ret;
+
+	return irq_create_of_mapping(oirq.controller, oirq.specifier,
+				     oirq.size);
+}
+
+static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(sys);
+	struct pci_bus *bus;
+
+	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
+				  &mvebu_pcie_ops, sys, &sys->resources);
+	if (!bus)
+		return NULL;
+
+	pci_scan_child_bus(bus);
+
+	return bus;
+}
+
+resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
+					  const struct resource *res,
+					  resource_size_t start,
+					  resource_size_t size,
+					  resource_size_t align)
+{
+	if (dev->bus->number != 0)
+		return start;
+
+	/*
+	 * On the PCI-to-PCI bridge side, the I/O windows must have at
+	 * least a 64 KB size and be aligned on their size, and the
+	 * memory windows must have at least a 1 MB size and be
+	 * aligned on their size
+	 */
+	if (res->flags & IORESOURCE_IO)
+		return round_up(start, max((resource_size_t)SZ_64K, size));
+	else if (res->flags & IORESOURCE_MEM)
+		return round_up(start, max((resource_size_t)SZ_1M, size));
+	else
+		return start;
+}
+
+static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
+{
+	struct hw_pci hw;
+
+	memset(&hw, 0, sizeof(hw));
+
+	hw.nr_controllers = 1;
+	hw.private_data   = (void **)&pcie;
+	hw.setup          = mvebu_pcie_setup;
+	hw.scan           = mvebu_pcie_scan_bus;
+	hw.map_irq        = mvebu_pcie_map_irq;
+	hw.ops            = &mvebu_pcie_ops;
+	hw.align_resource = mvebu_pcie_align_resource;
+
+	pci_common_init(&hw);
+}
+
+/*
+ * Looks up the list of register addresses encoded into the reg =
+ * <...> property for one that matches the given port/lane. Once
+ * found, maps it.
+ */
+static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
+					      struct device_node *np,
+					      struct mvebu_pcie_port *port)
+{
+	struct resource regs;
+	int ret = 0;
+
+	ret = of_address_to_resource(np, 0, &regs);
+	if (ret)
+		return NULL;
+
+	return devm_request_and_ioremap(&pdev->dev, &regs);
+}
+
+static int __init mvebu_pcie_probe(struct platform_device *pdev)
+{
+	struct mvebu_pcie *pcie;
+	struct device_node *np = pdev->dev.of_node;
+	struct of_pci_range range;
+	struct of_pci_range_parser parser;
+	struct device_node *child;
+	int i, ret;
+
+	pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
+			    GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pcie->pdev = pdev;
+
+	if (of_pci_range_parser_init(&parser, np))
+		return -EINVAL;
+
+	/* Get the I/O and memory ranges from DT */
+	for_each_of_pci_range(&parser, &range) {
+		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+		if (restype == IORESOURCE_IO) {
+			of_pci_range_to_resource(&range, np, &pcie->io);
+			of_pci_range_to_resource(&range, np, &pcie->realio);
+			pcie->io.name = "I/O";
+			pcie->realio.start = max_t(resource_size_t,
+						   PCIBIOS_MIN_IO,
+						   range.pci_addr);
+			pcie->realio.end = min_t(resource_size_t,
+						 IO_SPACE_LIMIT,
+						 range.pci_addr + range.size);
+		}
+		if (restype == IORESOURCE_MEM) {
+			of_pci_range_to_resource(&range, np, &pcie->mem);
+			pcie->mem.name = "MEM";
+		}
+	}
+
+	/* Get the bus range */
+	ret = of_pci_parse_bus_range(np, &pcie->busn);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
+			ret);
+		return ret;
+	}
+
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		if (!of_device_is_available(child))
+			continue;
+		pcie->nports++;
+	}
+
+	pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
+				   sizeof(struct mvebu_pcie_port),
+				   GFP_KERNEL);
+	if (!pcie->ports)
+		return -ENOMEM;
+
+	i = 0;
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		struct mvebu_pcie_port *port = &pcie->ports[i];
+
+		if (!of_device_is_available(child))
+			continue;
+
+		port->pcie = pcie;
+
+		if (of_property_read_u32(child, "marvell,pcie-port",
+					 &port->port)) {
+			dev_warn(&pdev->dev,
+				 "ignoring PCIe DT node, missing pcie-port property\n");
+			continue;
+		}
+
+		if (of_property_read_u32(child, "marvell,pcie-lane",
+					 &port->lane))
+			port->lane = 0;
+
+		port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
+				       port->port, port->lane);
+
+		port->devfn = of_pci_get_devfn(child);
+		if (port->devfn < 0)
+			continue;
+
+		port->base = mvebu_pcie_map_registers(pdev, child, port);
+		if (!port->base) {
+			dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
+				port->port, port->lane);
+			continue;
+		}
+
+		if (mvebu_pcie_link_up(port)) {
+			port->haslink = 1;
+			dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
+				 port->port, port->lane);
+		} else {
+			port->haslink = 0;
+			dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
+				 port->port, port->lane);
+		}
+
+		port->clk = of_clk_get_by_name(child, NULL);
+		if (!port->clk) {
+			dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
+			       port->port, port->lane);
+			iounmap(port->base);
+			port->haslink = 0;
+			continue;
+		}
+
+		port->dn = child;
+
+		clk_prepare_enable(port->clk);
+		spin_lock_init(&port->conf_lock);
+
+		mvebu_sw_pci_bridge_init(port);
+
+		i++;
+	}
+
+	mvebu_pcie_enable(pcie);
+
+	return 0;
+}
+
+static const struct of_device_id mvebu_pcie_of_match_table[] = {
+	{ .compatible = "marvell,armada-xp-pcie", },
+	{ .compatible = "marvell,armada-370-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
+
+static struct platform_driver mvebu_pcie_driver = {
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "mvebu-pcie",
+		.of_match_table =
+		   of_match_ptr(mvebu_pcie_of_match_table),
+	},
+};
+
+static int mvebu_pcie_init(void)
+{
+	return platform_driver_probe(&mvebu_pcie_driver,
+				     mvebu_pcie_probe);
+}
+
+subsys_initcall(mvebu_pcie_init);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni at free-electrons.com>");
+MODULE_DESCRIPTION("Marvell EBU PCIe driver");
+MODULE_LICENSE("GPLv2");
-- 
1.7.9.5



From linux at arm.linux.org.uk  Wed May 15 09:32:37 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 May 2013 14:32:37 +0100
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <201305151516.52389.arnd@arndb.de>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201303181503.49491.arnd@arndb.de>
 <CACmBeS1empYyoaKidgTrYwUFCw447OKndxZjT98TvYfKVWB00A@mail.gmail.com>
 <201305151516.52389.arnd@arndb.de>
Message-ID: <20130515133237.GK18614@n2100.arm.linux.org.uk>

On Wed, May 15, 2013 at 03:16:52PM +0200, Arnd Bergmann wrote:
> > +static void moxart_idle(void)
> > +{
> > +	/*
> > +	 * Because of broken hardware we have to enable interrupts or the CPU
> > +	 * will never wakeup... Acctualy it is not very good to enable
> > +	 * interrupts first since scheduler can miss a tick, but there is
> > +	 * no other way around this. Platforms that needs it for power saving
> > +	 * should call enable_hlt() in init code, since by default it is
> > +	 * disabled.
> > +	 */
> > +/*	local_irq_enable();
> > +	cpu_do_idle();*/
> > +}
> > +
> > +static int __init moxart_idle_init(void)
> > +{
> > +	arm_pm_idle = moxart_idle;
> > +	return 0;
> > +}
> > +
> > +arch_initcall(moxart_idle_init);
> 
> This does not seem to do anything at this point. Does the comment still
> apply?

Actually, that's probably the whole point of this - to do nothing.
This changes the behaviour of the idle loop from using the WFI to
just spinning instead with no wait-for-interrupt or anything else.
We just keep reading the need_resched flag.

That's much better than the commented out code which opens a mighty
big race condition which will then give bad scheduling behaviour,
allowing the idle task to sleep in WFI until the next interrupt while
the need_resched flag may be set.

Sure, there's better ways to do this, via the disable_hlt() stuff,
and whatever its replacement implementation is now called.  But
ultimately this workaround really is about "doing nothing" when
idle!


From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:54 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:54 +0200
Subject: [PATCHv4 1/9] pci: mvebu: enable driver usage on Kirkwood
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-2-git-send-email-thomas.petazzoni@free-electrons.com>

We allow the pci-mvebu driver to be compiled on the Kirkwood platform,
and add the 'marvell,kirkwood-pcie' as a compatible string supported
by the driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Tested-by: Andrew Lunn <andrew at lunn.ch>
---
 .../devicetree/bindings/pci/mvebu-pci.txt          |    1 +
 drivers/pci/host/Kconfig                           |    2 +-
 drivers/pci/host/pci-mvebu.c                       |    1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index eb69d92..f8d4058 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -4,6 +4,7 @@ Mandatory properties:
 - compatible: one of the following values:
     marvell,armada-370-pcie
     marvell,armada-xp-pcie
+    marvell,kirkwood-pcie
 - #address-cells, set to <3>
 - #size-cells, set to <2>
 - #interrupt-cells, set to <1>
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 6918fbc..1f1d67f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -3,6 +3,6 @@ menu "PCI host controller drivers"
 
 config PCI_MVEBU
 	bool "Marvell EBU PCIe controller"
-	depends on ARCH_MVEBU
+	depends on ARCH_MVEBU || ARCH_KIRKWOOD
 
 endmenu
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index b0ee63b..6fe8b90 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -853,6 +853,7 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
 static const struct of_device_id mvebu_pcie_of_match_table[] = {
 	{ .compatible = "marvell,armada-xp-pcie", },
 	{ .compatible = "marvell,armada-370-pcie", },
+	{ .compatible = "marvell,kirkwood-pcie", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:57 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:57 +0200
Subject: [PATCHv4 4/9] arm: kirkwood: convert Iomega Iconnect to use DT for
 the PCIe interface
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-5-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
of the legacy PCIe code, since it allows to describe the PCIe
interfaces in the Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-iconnect.dts |    8 ++++++++
 arch/arm/mach-kirkwood/board-iconnect.c |    8 --------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74..e591d5d 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -109,6 +109,14 @@
 				reg = <0x980000 0x1f400000>;
 			};
 		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
 	};
 
 	gpio-leds {
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4..98b5ad1 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -22,11 +22,3 @@ void __init iconnect_init(void)
 {
 	kirkwood_ge00_init(&iconnect_ge00_data);
 }
-
-static int __init iconnect_pci_init(void)
-{
-	if (of_machine_is_compatible("iom,iconnect"))
-		kirkwood_pcie_init(KW_PCIE0);
-	return 0;
-}
-subsys_initcall(iconnect_pci_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:55 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:55 +0200
Subject: [PATCHv4 2/9] arm: kirkwood: move PCIe window init to legacy driver
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-3-git-send-email-thomas.petazzoni@free-electrons.com>

Since we are going to enable the usage of the mvebu PCIe driver on
Kirkwood, we don't want the PCIe windows to be unconditionally created
by kirkwood_setup_wins(). Therefore, we move the PCIe window
initialization into the legacy PCIe driver
(arch/arm/mach-kirkwood/pcie.c).

The platforms using the legacy driver will see their windows
statically allocated by
arch/arm/mach-kirkwood/pcie.c:kirkwood_pcie_init(). The platforms
using the new driver in drivers/pci/ will see their windows
dynamically allocated directly by the driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Tested-by: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/mach-kirkwood/common.c |   24 ------------------------
 arch/arm/mach-kirkwood/pcie.c   |   22 ++++++++++++++++++++++
 2 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c2cae69..9b0b901 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -654,30 +654,6 @@ char * __init kirkwood_id(void)
 
 void __init kirkwood_setup_wins(void)
 {
-	/*
-	 * The PCIe windows will no longer be statically allocated
-	 * here once Kirkwood is migrated to the pci-mvebu driver.
-	 */
-	mvebu_mbus_add_window_remap_flags("pcie0.0",
-					  KIRKWOOD_PCIE_IO_PHYS_BASE,
-					  KIRKWOOD_PCIE_IO_SIZE,
-					  KIRKWOOD_PCIE_IO_BUS_BASE,
-					  MVEBU_MBUS_PCI_IO);
-	mvebu_mbus_add_window_remap_flags("pcie0.0",
-					  KIRKWOOD_PCIE_MEM_PHYS_BASE,
-					  KIRKWOOD_PCIE_MEM_SIZE,
-					  MVEBU_MBUS_NO_REMAP,
-					  MVEBU_MBUS_PCI_MEM);
-	mvebu_mbus_add_window_remap_flags("pcie1.0",
-					  KIRKWOOD_PCIE1_IO_PHYS_BASE,
-					  KIRKWOOD_PCIE1_IO_SIZE,
-					  KIRKWOOD_PCIE1_IO_BUS_BASE,
-					  MVEBU_MBUS_PCI_IO);
-	mvebu_mbus_add_window_remap_flags("pcie1.0",
-					  KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-					  KIRKWOOD_PCIE1_MEM_SIZE,
-					  MVEBU_MBUS_NO_REMAP,
-					  MVEBU_MBUS_PCI_MEM);
 	mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
 			      KIRKWOOD_NAND_MEM_SIZE);
 	mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 7f43e6c..ddcb09f 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -12,6 +12,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base)
 
 void __init kirkwood_pcie_init(unsigned int portmask)
 {
+	mvebu_mbus_add_window_remap_flags("pcie0.0",
+					  KIRKWOOD_PCIE_IO_PHYS_BASE,
+					  KIRKWOOD_PCIE_IO_SIZE,
+					  KIRKWOOD_PCIE_IO_BUS_BASE,
+					  MVEBU_MBUS_PCI_IO);
+	mvebu_mbus_add_window_remap_flags("pcie0.0",
+					  KIRKWOOD_PCIE_MEM_PHYS_BASE,
+					  KIRKWOOD_PCIE_MEM_SIZE,
+					  MVEBU_MBUS_NO_REMAP,
+					  MVEBU_MBUS_PCI_MEM);
+	mvebu_mbus_add_window_remap_flags("pcie1.0",
+					  KIRKWOOD_PCIE1_IO_PHYS_BASE,
+					  KIRKWOOD_PCIE1_IO_SIZE,
+					  KIRKWOOD_PCIE1_IO_BUS_BASE,
+					  MVEBU_MBUS_PCI_IO);
+	mvebu_mbus_add_window_remap_flags("pcie1.0",
+					  KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+					  KIRKWOOD_PCIE1_MEM_SIZE,
+					  MVEBU_MBUS_NO_REMAP,
+					  MVEBU_MBUS_PCI_MEM);
+
 	vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 
 	if (portmask & KW_PCIE0)
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:56 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:56 +0200
Subject: [PATCHv4 3/9] arm: kirkwood: add SoC-level Device Tree data for PCIe
 interfaces
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-4-git-send-email-thomas.petazzoni@free-electrons.com>

This commit adds Device Tree details to enable the PCIe interfaces on
Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe
interfaces.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Tested-by: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/boot/dts/kirkwood-6281.dtsi |   31 ++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-6282.dtsi |   48 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi      |    1 +
 3 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65..5137668 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,36 @@
 				marvell,function = "sdio";
 			};
 		};
+
+		pcie-controller {
+			compatible = "marvell,kirkwood-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			bus-range = <0x00 0xff>;
+
+			ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+				  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+			          0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+			pcie at 1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &intc 9>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gate_clk 2>;
+				status = "disabled";
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e4..66a751a 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -65,5 +65,53 @@
 			clocks = <&gate_clk 7>;
 			status = "disabled";
 		};
+
+		pcie-controller {
+			compatible = "marvell,kirkwood-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			bus-range = <0x00 0xff>;
+
+			ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+			          0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
+				  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+			          0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+			pcie at 1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &intc 9>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gate_clk 2>;
+				status = "disabled";
+			};
+
+			pcie at 2,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &intc 10>;
+				marvell,pcie-port = <1>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gate_clk 18>;
+				status = "disabled";
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..7eef88f 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -19,6 +19,7 @@
 	ocp at f1000000 {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0xf1000000 0x4000000
+		          0xe0000000 0xe0000000 0x8100000 /* PCIE */
 		          0xf5000000 0xf5000000 0x0000400>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:53 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:53 +0200
Subject: [PATCHv4 0/9] Use the mvebu PCIe driver on Kirkwood
Message-ID: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

Here is a set of patches that migrates adds support for Kirkwood
platforms to use the mvebu PCIe driver. All the Kirkwood platforms
that have already been converted to the Device Tree are converted to
use the new driver, and the DB-88F6281/DB-88F6282 evaluation board
from Marvell is also converted to the Device Tree and the usage of the
new PCIe driver.

Only non-DT platforms continue to use the legacy code in
arch/arm/mach-kirkwood/pcie.c.

This branch depends on the mvebu-pcie driver. I have pushed this
branch to the following Git repository for easier testing:

  https://github.com/MISL-EBU-System-SW/mainline-public/tree/kirkwood-pcie-dt-v4

# /usr/sbin/lspci
00:01.0 PCI bridge: Marvell Technology Group Ltd. Device 7846
00:02.0 PCI bridge: Marvell Technology Group Ltd. Device 7846
01:00.0 SCSI storage controller: Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port SATA-II (rev 02)
02:00.0 Ethernet controller: Intel Corporation 82572EI Gigabit Ethernet Controller (Copper) (rev 06)

I've tested both the e1000e NIC card and the SATA 4 ports card and
they work fine.

Changes between v3 and v4:

 * Rebase on top of 3.10-rc1.

 * Change the name of the file and Kconfig options related to the
   DB-88F6281/DB-88F6282 board to use DB-88F628x, since it handles in
   fact two different boards using two slightly different SoCs.

Changes between v2 and v3:

 * Integrate a replacement patch from Andrew Lunn for the QNAP changes
   after he tested on his platforms.

 * Add Andrew Lunn Tested-by tags on the appropriate patches.

Changes between v1 and v2:

 * Remove the 'needs_pcie_win' logic, and instead move the static
   initialization of PCIe windows into the legacy PCIe code, for the
   platforms that will still be using it. Platforms that will use the
   new PCIe driver benefit directly from dynamic allocation of PCIe
   windows.

 * Move the PCIe interface definitions from kirkwood.dtsi to
   kirkwood-6281.dtsi and kirkwood-6282.dtsi to take into account the
   fact that the 6281 has one PCIe interface, and the 6282 has two of
   them.

 * Convert all DT-platforms that were initializing PCIe using the
   legacy driver to use the DT to initialize the PCIe interface. This
   includes the Iomega Iconnect, the MPL CEC4, the ZyXEL NSA310and the
   QNAP TS219.

 * Fix the conversion to the Device Tree of the DB-88F6181/6282
   board. We now have two Device Trees, one for the 6281 variant of
   the board (one PCIe interface) and another for the 6282 variant of
   the board (two PCIe interfaces).

 * Update the defconfig with PCIe driver enabled and some board
   updates.

Best regards,

Thomas

Thomas Petazzoni (9):
  pci: mvebu: enable driver usage on Kirkwood
  arm: kirkwood: move PCIe window init to legacy driver
  arm: kirkwood: add SoC-level Device Tree data for PCIe interfaces
  arm: kirkwood: convert Iomega Iconnect to use DT for the PCIe
    interface
  arm: kirkwood: convert MPL CEC4 to use DT for the PCIe interface
  arm: kirkwood: convert ZyXEL NSA310 to use DT for the PCIe interface
  arm: kirkwood: convert QNAP TS219 to use DT for the PCIe interface
  arm: kirkwood: convert db-88f6281/db-88f6282 to the Device Tree
  arm: kirkwood: update defconfig with PCIe driver and board updates

 .../devicetree/bindings/pci/mvebu-pci.txt          |    1 +
 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/kirkwood-6281.dtsi               |   31 ++++++
 arch/arm/boot/dts/kirkwood-6282.dtsi               |   48 +++++++++
 arch/arm/boot/dts/kirkwood-db-88f6281.dts          |   30 ++++++
 arch/arm/boot/dts/kirkwood-db-88f6282.dts          |   34 ++++++
 arch/arm/boot/dts/kirkwood-db.dtsi                 |   89 ++++++++++++++++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |    8 ++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |    8 ++
 arch/arm/boot/dts/kirkwood-nsa310.dts              |    8 ++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    3 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    3 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |    9 +-
 arch/arm/boot/dts/kirkwood.dtsi                    |    1 +
 arch/arm/configs/kirkwood_defconfig                |    2 +
 arch/arm/mach-kirkwood/Kconfig                     |   21 ++--
 arch/arm/mach-kirkwood/Makefile                    |    3 +-
 arch/arm/mach-kirkwood/board-db88f628x-bp.c        |   24 +++++
 arch/arm/mach-kirkwood/board-dt.c                  |    6 ++
 arch/arm/mach-kirkwood/board-iconnect.c            |    8 --
 arch/arm/mach-kirkwood/board-mplcec4.c             |    1 -
 arch/arm/mach-kirkwood/board-nsa310.c              |   25 -----
 arch/arm/mach-kirkwood/board-ts219.c               |   10 --
 arch/arm/mach-kirkwood/common.c                    |   24 -----
 arch/arm/mach-kirkwood/common.h                    |    6 ++
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |  108 --------------------
 arch/arm/mach-kirkwood/pcie.c                      |   22 ++++
 drivers/pci/host/Kconfig                           |    2 +-
 drivers/pci/host/pci-mvebu.c                       |    1 +
 29 files changed, 341 insertions(+), 197 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6281.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6282.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-db.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-db88f628x-bp.c
 delete mode 100644 arch/arm/mach-kirkwood/board-nsa310.c
 delete mode 100644 arch/arm/mach-kirkwood/db88f6281-bp-setup.c

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:37:02 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:37:02 +0200
Subject: [PATCHv4 9/9] arm: kirkwood: update defconfig with PCIe driver and
 board updates
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-10-git-send-email-thomas.petazzoni@free-electrons.com>

This commit enables the mvebu PCIe driver in kirkwood_defconfig and
updates various options related to Kirkwood boards.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/configs/kirkwood_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252..452adec 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -31,6 +31,7 @@ CONFIG_MACH_T5325=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_CLOUDBOX_DT=y
+CONFIG_MACH_DB88F628X_BP_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
 CONFIG_MACH_DOCKSTAR_DT=y
 CONFIG_MACH_DREAMPLUG_DT=y
@@ -53,6 +54,7 @@ CONFIG_MACH_READYNAS_DT=y
 CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_PCI_MVEBU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:58 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:58 +0200
Subject: [PATCHv4 5/9] arm: kirkwood: convert MPL CEC4 to use DT for the PCIe
 interface
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-6-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
of the legacy PCIe code, since it allows to describe the PCIe
interfaces in the Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-mplcec4.dts |    8 ++++++++
 arch/arm/mach-kirkwood/board-mplcec4.c |    1 -
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..90501cf 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -139,6 +139,14 @@
 			cd-gpios = <&gpio1 15 0>;
 			/* No WP GPIO */
 		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
 	};
 
 	gpio-leds {
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc66..938712e 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -29,7 +29,6 @@ void __init mplcec4_init(void)
 	 */
 	kirkwood_ge00_init(&mplcec4_ge00_data);
 	kirkwood_ge01_init(&mplcec4_ge01_data);
-	kirkwood_pcie_init(KW_PCIE0);
 }
 
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:37:00 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:37:00 +0200
Subject: [PATCHv4 7/9] arm: kirkwood: convert QNAP TS219 to use DT for the
 PCIe interface
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-8-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
of the legacy PCIe code, since it allows to describe the PCIe
interfaces in the Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/boot/dts/kirkwood-ts219-6281.dts |    3 ++-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts |    3 ++-
 arch/arm/boot/dts/kirkwood-ts219.dtsi     |    9 +++++++--
 arch/arm/mach-kirkwood/board-ts219.c      |   10 ----------
 4 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c83..42648ab 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,7 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6281.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 
 / {
 	ocp at f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95d..95ceeb9 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,7 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6282.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 
 / {
 	ocp at f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..7c022fd 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -1,5 +1,3 @@
-/include/ "kirkwood.dtsi"
-
 / {
 	model = "QNAP TS219 family";
 	compatible = "qnap,ts219", "marvell,kirkwood";
@@ -74,5 +72,12 @@
 			status = "okay";
 			nr-ports = <2>;
 		};
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index acb0187..4695d5f 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -41,13 +41,3 @@ void __init qnap_dt_ts219_init(void)
 
 	pm_power_off = qnap_tsx1x_power_off;
 }
-
-/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */
-static int __init ts219_pci_init(void)
-{
-	if (machine_is_ts219())
-		kirkwood_pcie_init(KW_PCIE0);
-
-	return 0;
-}
-subsys_initcall(ts219_pci_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:36:59 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:36:59 +0200
Subject: [PATCHv4 6/9] arm: kirkwood: convert ZyXEL NSA310 to use DT for the
 PCIe interface
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-7-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
of the legacy PCIe code, since it allows to describe the PCIe
interfaces in the Device Tree.

Since it was the only device left that prevented this platform to use
the Device Tree only, we remove the board-nsa310.c file and the
related Kconfig/Makefile bits.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-nsa310.dts |    8 ++++++++
 arch/arm/mach-kirkwood/Kconfig        |    8 --------
 arch/arm/mach-kirkwood/Makefile       |    1 -
 arch/arm/mach-kirkwood/board-nsa310.c |   25 -------------------------
 4 files changed, 8 insertions(+), 34 deletions(-)
 delete mode 100644 arch/arm/mach-kirkwood/board-nsa310.c

diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index a7412b9..9ddf218 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -176,6 +176,14 @@
 				reg = <0x5040000 0x2fc0000>;
 			};
 		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
 	};
 
 	gpio_keys {
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..267ca95 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -272,14 +272,6 @@ config MACH_NETSPACE_V2_DT
 	  Say 'Y' here if you want your kernel to support the LaCie
 	  Network Space v2 NAS, using Flattened Device Tree.
 
-config MACH_NSA310_DT
-	bool "ZyXEL NSA-310 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	select ARM_ATAG_DTB_COMPAT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  ZyXEL NSA-310 board (Flattened Device Tree).
-
 config MACH_OPENBLOCKS_A6_DT
 	bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735..794366e 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NSA310_DT)		+= board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)	+= board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
 obj-$(CONFIG_MACH_TOPKICK_DT)		+= board-usi_topkick.o
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
deleted file mode 100644
index 55ade93..0000000
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/nsa-310-setup.c
- *
- * ZyXEL NSA-310 Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <mach/kirkwood.h>
-#include <linux/of.h>
-#include "common.h"
-
-static int __init nsa310_pci_init(void)
-{
-	if (of_machine_is_compatible("zyxel,nsa310"))
-		kirkwood_pcie_init(KW_PCIE0);
-
-	return 0;
-}
-
-subsys_initcall(nsa310_pci_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 15 09:37:01 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 15:37:01 +0200
Subject: [PATCHv4 8/9] arm: kirkwood: convert db-88f6281/db-88f6282 to the
 Device Tree
In-Reply-To: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368625022-25243-9-git-send-email-thomas.petazzoni@free-electrons.com>

This commit converts the Marvell DB-88F6281/DB-88F6282 board to the
Device Tree. In fact, the code was supporting two different boards:
one with the 6281 SoC variant, and one with the 6282 SoC variant. The
difference between the two being that the 6281 has one PCIe interface,
and the 6282 has two PCIe interfaces.

In order to handle that with the Device Tree, we create a
'kirkwood-db.dtsi' file that contains the definitions common to both
boards, and 'kirkwood-db-88f6281.dts' and 'kirkwood-db-88f6282.dts'
for the definitions specific to each board. This is similar to what is
done for the QNAP TS219 Kirkwood platform.

We have kept one single Kconfig option, just like it was before.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/Makefile                  |    2 +
 arch/arm/boot/dts/kirkwood-db-88f6281.dts   |   30 ++++++++
 arch/arm/boot/dts/kirkwood-db-88f6282.dts   |   34 +++++++++
 arch/arm/boot/dts/kirkwood-db.dtsi          |   89 ++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig              |   13 ++--
 arch/arm/mach-kirkwood/Makefile             |    2 +-
 arch/arm/mach-kirkwood/board-db88f628x-bp.c |   24 ++++++
 arch/arm/mach-kirkwood/board-dt.c           |    6 ++
 arch/arm/mach-kirkwood/common.h             |    6 ++
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c |  108 ---------------------------
 10 files changed, 199 insertions(+), 115 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6281.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6282.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-db.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-db88f628x-bp.c
 delete mode 100644 arch/arm/mach-kirkwood/db88f6281-bp-setup.c

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..cc53176 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
 	integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+	kirkwood-db-88f6281.dtb \
+	kirkwood-db-88f6282.dtb \
 	kirkwood-dns320.dtb \
 	kirkwood-dns325.dtb \
 	kirkwood-dockstar.dtb \
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
new file mode 100644
index 0000000..9d777ed
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -0,0 +1,30 @@
+/*
+ * Marvell DB-88F6281-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed at marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+	model = "Marvell DB-88F6281-BP Development Board";
+	compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	ocp at f1000000 {
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
new file mode 100644
index 0000000..f4c8528
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -0,0 +1,34 @@
+/*
+ * Marvell DB-88F6282-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed at marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6282.dtsi"
+
+/ {
+	model = "Marvell DB-88F6282-BP Development Board";
+	compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+	ocp at f1000000 {
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+
+			pcie at 2,0 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
new file mode 100644
index 0000000..c87cfb8
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed at marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the 6281
+ * and 6282 variants of the Marvell Kirkwood Development Board.
+ */
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		pinctrl at 10000 {
+			pmx_sdio_gpios: pmx-sdio-gpios {
+				marvell,pins = "mpp37", "mpp38";
+				marvell,function = "gpio";
+			};
+		};
+
+		serial at 12000 {
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			pinctrl-0 = <&pmx_nand>;
+			pinctrl-names = "default";
+			chip-delay = <25>;
+			status = "okay";
+
+			partition at 0 {
+				label = "uboot";
+				reg = <0x0 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x100000 0x400000>;
+			};
+
+			partition at 500000 {
+				label = "root";
+				reg = <0x500000 0x1fb00000>;
+			};
+		};
+
+		sata at 80000 {
+			nr-ports = <2>;
+			status = "okay";
+		};
+
+		ehci at 50000 {
+			status = "okay";
+		};
+
+		mvsdio at 90000 {
+			pinctrl-0 = <&pmx_sdio_gpios>;
+			pinctrl-names = "default";
+			wp-gpios = <&gpio1 5 0>;
+			cd-gpios = <&gpio1 6 0>;
+			status = "okay";
+		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 267ca95..b56bd3d 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -8,12 +8,6 @@ config MACH_D2NET_V2
 	  Say 'Y' here if you want your kernel to support the
 	  LaCie d2 Network v2 NAS.
 
-config MACH_DB88F6281_BP
-	bool "Marvell DB-88F6281-BP Development Board"
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Marvell DB-88F6281-BP Development Board.
-
 config MACH_DOCKSTAR
 	bool "Seagate FreeAgent DockStar"
 	help
@@ -153,6 +147,13 @@ config MACH_CLOUDBOX_DT
 	  Say 'Y' here if you want your kernel to support the LaCie
 	  CloudBox NAS, using Flattened Device Tree.
 
+config MACH_DB88F628X_BP_DT
+	bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the Marvell
+	  DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
+	  Device Tree).
+
 config MACH_DLINK_KIRKWOOD_DT
 	bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 794366e..2fdc3a7 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,7 +1,6 @@
 obj-y				+= common.o irq.o pcie.o mpp.o
 
 obj-$(CONFIG_MACH_D2NET_V2)		+= d2net_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_DB88F6281_BP)		+= db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_DOCKSTAR)		+= dockstar-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)	+= sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)		+= guruplug-setup.o
@@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_CLOUDBOX_DT)		+= board-ns2.o
+obj-$(CONFIG_MACH_DB88F628X_BP_DT)	+= board-db88f628x-bp.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)	+= board-dnskw.o
 obj-$(CONFIG_MACH_DOCKSTAR_DT)		+= board-dockstar.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
new file mode 100644
index 0000000..2f574bc
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
@@ -0,0 +1,24 @@
+/*
+ * Saeed Bishara <saeed at marvell.com>
+ *
+ * Marvell DB-88F628{1,2}-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
+};
+
+void __init db88f628x_init(void)
+{
+	kirkwood_ge00_init(&db88f628x_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..f5aed1f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -147,6 +147,10 @@ static void __init kirkwood_dt_init(void)
 	    of_machine_is_compatible("lacie,netspace_v2"))
 		ns2_init();
 
+	if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
+	    of_machine_is_compatible("marvell,db-88f6282-bp"))
+		db88f628x_init();
+
 	if (of_machine_is_compatible("mpl,cec4"))
 		mplcec4_init();
 
@@ -181,6 +185,8 @@ static const char * const kirkwood_dt_board_compat[] = {
 	"lacie,netspace_max_v2",
 	"lacie,netspace_mini_v2",
 	"lacie,netspace_v2",
+	"marvell,db-88f6281-bp",
+	"marvell,db-88f6282-bp",
 	"mpl,cec4",
 	"netgear,readynas-duo-v2",
 	"plathome,openblocks-a6",
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..cbbc0b8 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -119,6 +119,12 @@ void km_kirkwood_init(void);
 static inline void km_kirkwood_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DB88F628X_BP_DT
+void db88f628x_init(void);
+#else
+static inline void db88f628x_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_MPLCEC4_DT
 void mplcec4_init(void);
 #else
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
deleted file mode 100644
index 5a369fe..0000000
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
- *
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/sizes.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition db88f6281_nand_parts[] = {
-	{
-		.name = "u-boot",
-		.offset = 0,
-		.size = SZ_1M
-	}, {
-		.name = "uImage",
-		.offset = MTDPART_OFS_NXTBLK,
-		.size = SZ_4M
-	}, {
-		.name = "root",
-		.offset = MTDPART_OFS_NXTBLK,
-		.size = MTDPART_SIZ_FULL
-	},
-};
-
-static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data db88f6281_sata_data = {
-	.n_ports	= 2,
-};
-
-static struct mvsdio_platform_data db88f6281_mvsdio_data = {
-	.gpio_write_protect	= 37,
-	.gpio_card_detect	= 38,
-};
-
-static unsigned int db88f6281_mpp_config[] __initdata = {
-	MPP0_NF_IO2,
-	MPP1_NF_IO3,
-	MPP2_NF_IO4,
-	MPP3_NF_IO5,
-	MPP4_NF_IO6,
-	MPP5_NF_IO7,
-	MPP18_NF_IO0,
-	MPP19_NF_IO1,
-	MPP37_GPIO,
-	MPP38_GPIO,
-	0
-};
-
-static void __init db88f6281_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_init();
-	kirkwood_mpp_conf(db88f6281_mpp_config);
-
-	kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25);
-	kirkwood_ehci_init();
-	kirkwood_ge00_init(&db88f6281_ge00_data);
-	kirkwood_sata_init(&db88f6281_sata_data);
-	kirkwood_uart0_init();
-	kirkwood_sdio_init(&db88f6281_mvsdio_data);
-}
-
-static int __init db88f6281_pci_init(void)
-{
-	if (machine_is_db88f6281_bp()) {
-		u32 dev, rev;
-
-		kirkwood_pcie_id(&dev, &rev);
-		if (dev == MV88F6282_DEV_ID)
-			kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
-		else
-			kirkwood_pcie_init(KW_PCIE0);
-	}
-	return 0;
-}
-subsys_initcall(db88f6281_pci_init);
-
-MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
-	/* Maintainer: Saeed Bishara <saeed at marvell.com> */
-	.atag_offset	= 0x100,
-	.init_machine	= db88f6281_init,
-	.map_io		= kirkwood_map_io,
-	.init_early	= kirkwood_init_early,
-	.init_irq	= kirkwood_init_irq,
-	.init_time	= kirkwood_timer_init,
-	.restart	= kirkwood_restart,
-MACHINE_END
-- 
1.7.9.5



From will.deacon at arm.com  Wed May 15 09:41:17 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 14:41:17 +0100
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <51938B3D.2070508@free-electrons.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
Message-ID: <20130515134117.GH23869@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 02:18:53PM +0100, Gregory CLEMENT wrote:
> Hi Will,

Hi Gregory,

> On 03/25/2013 07:19 PM, Will Deacon wrote:
> > Many ARMv7 cores have hardware page table walkers that can read the L1
> > cache. This is discoverable from the ID_MMFR3 register, although this
> > can be expensive to access from the low-level set_pte functions and is a
> > pain to cache, particularly with multi-cluster systems.
> > 
> > A useful observation is that the multi-processing extensions for ARMv7
> > require coherent table walks, meaning that we can make use of ALT_SMP
> > patching in proc-v7-* to patch away the cache flush safely for these
> > cores.
> 
> I encountered a regression with 3.10-rc1 on the Armada 370 based boards.
> With the 3.10-rc1 they hang during auto testy of the xor engine which are
> mainly DMA transfers. If I revert this patch, it no more hang. I found this
> by using bisect, it was not obvious at all for me that this patch may have
> cause this regression.

Is this using dmatest.ko, or a different test program?

> The issue appear in SMP and in UP. However I think that  the PJ4B-v7 used in
>  the Armada 370 are not MP capable.

Ok, so the ALT_UP case should be emitted after patching, correct?

> I made some investigation. And in UP if I remove the line:
> 	ALT_UP(W(nop))

Did you remove the ALT_SMP case as well? You could also try making the
ALT_SMP case use W(nop) too and see if it changes anything.

> at the begining of the cpu_v7_dcache_clean_are macro located in
> arch/arm/mm/proc-v7.S
> 
> Then the kernel boot again. It is not surprising because in this case
> we found the same generated code that before this patch was applied.
> 
> now I don't really understand why a W(nop) will cause this issue.

No, that sounds weird. Can you inspect the functions using JTAG after the smp
patching code has executed?

> In SMP mode even with this line removed the kernel hang, but in this case
> I am not sure of what happen exactly and how the .alt.smp.init section is
> used.

If you don't have both of the alternatives, things will go wrong.

> I hope you will find some explanation and solution to this bug, because currently
> the only solution I have is to revert this patch.

Let's not jump to that just yet!

Cheers,

Will


From james.hogan at imgtec.com  Wed May 15 09:41:00 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Wed, 15 May 2013 14:41:00 +0100
Subject: [PATCH v3 1/4] clk: abstract parent cache
In-Reply-To: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368625263-23136-2-git-send-email-james.hogan@imgtec.com>

Abstract access to the clock parent cache by defining
clk_get_parent_by_index(clk, index). This allows access to parent
clocks from clock drivers.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v3:

* remove double underscore prefix from clk_get_parent_by_index()

 drivers/clk/clk.c            | 21 ++++++++++++++-------
 include/linux/clk-provider.h |  1 +
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 934cfd1..9bf4167 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -559,6 +559,19 @@ struct clk *__clk_get_parent(struct clk *clk)
 	return !clk ? NULL : clk->parent;
 }
 
+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
+{
+	if (!clk || index >= clk->num_parents)
+		return NULL;
+	else if (!clk->parents)
+		return __clk_lookup(clk->parent_names[index]);
+	else if (!clk->parents[index])
+		return clk->parents[index] =
+			__clk_lookup(clk->parent_names[index]);
+	else
+		return clk->parents[index];
+}
+
 unsigned int __clk_get_enable_count(struct clk *clk)
 {
 	return !clk ? 0 : clk->enable_count;
@@ -1315,13 +1328,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
 			kzalloc((sizeof(struct clk*) * clk->num_parents),
 					GFP_KERNEL);
 
-	if (!clk->parents)
-		ret = __clk_lookup(clk->parent_names[index]);
-	else if (!clk->parents[index])
-		ret = clk->parents[index] =
-			__clk_lookup(clk->parent_names[index]);
-	else
-		ret = clk->parents[index];
+	ret = clk_get_parent_by_index(clk, index);
 
 out:
 	return ret;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1186098..76b1667 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -403,6 +403,7 @@ const char *__clk_get_name(struct clk *clk);
 struct clk_hw *__clk_get_hw(struct clk *clk);
 u8 __clk_get_num_parents(struct clk *clk);
 struct clk *__clk_get_parent(struct clk *clk);
+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
-- 
1.8.1.2




From james.hogan at imgtec.com  Wed May 15 09:40:59 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Wed, 15 May 2013 14:40:59 +0100
Subject: [PATCH v3 0/4] clk: implement remuxing during set_rate
Message-ID: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>

This patchset adds support for automatic selection of the best parent
for a clock mux, i.e. the one which can provide the closest clock rate
to that requested. It can be disabled by a new CLK_SET_RATE_NO_REPARENT
flag (which is set for all uses of clk_register_mux().

This works by way of adding a new op, determine_rate, similar to
round_rate but with an extra parameter to allow the clock driver to
optionally select a different parent clock. This is used in
clk_calc_new_rates to decide whether to initiate a set_parent operation.

Changes in v3:

* rebased on v3.10-rc1
* remove double underscore prefix from clk_get_parent_by_index()
* store new_parent_index in struct clk too (calculated from
  clk_fetch_parent_index, and passed through __clk_set_parent_no_recalc
  to __clk_set_parent).
* allow determine_rate to satisfy recalc_rate check in __clk_init.
* rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
  to patch 3.
* patch 3: add CLK_SET_RATE_NO_REPARENT flag to all callers of
  clk_register_mux. If you don't mind your clocks being reparented in
  response to set_rate please let me know and I'll drop the relevant
  portion of the patch.

Changes in v2:

I've moved the mux determine_rate implementation into a core helper, but
I haven't pushed it fully into the core, as I think it just wouldn't
work correctly for more complex clocks, e.g. if you (theoretically) had
a combined mux and divide, you'd want to intercept the determine_rate
and ask for a larger rate from the parent clocks, then return the
divided rate. This should be possible by wrapping the mux determine_rate
helper.

Patch 1 still exports the __clk_get_parent_by_index as it seems like it
might be a useful thing for clock implementations to have access to if
they ever wanted to do something more fancy with changing clock parents.

I haven't made any attempt to implement the atomic set_parent+set_rate
as I don't have hardware that could take proper advantage of it, but it
shouldn't be too difficult for others to implement if they wanted since
they're fairly close to one another (in clk_change_rate()).

* switched to using new determine_rate op rather than adding an argument
  to round_rate.
* moved mux implementation into a single helper which should be usable
  from more complex clocks which can mux.
* rewrite main implementation so that no changes are made until after
  the PRE notifications have been sent, and in a way that should ensure
  correct notifications without duplicates, and I think should be safe
  in the event of a notification failing.
* various tidy ups and fixes.

James Hogan (4):
  clk: abstract parent cache
  clk: add support for clock reparent on set_rate
  clk: add CLK_SET_RATE_NO_REPARENT flag
  clk: clk-mux: implement remuxing on set_rate

 Documentation/clk.txt                |   4 +
 arch/arm/mach-imx/clk.h              |   5 +-
 drivers/clk/clk-mux.c                |   1 +
 drivers/clk/clk.c                    | 278 +++++++++++++++++++++++++----------
 drivers/clk/mmp/clk-mmp2.c           |  39 +++--
 drivers/clk/mmp/clk-pxa168.c         |  40 +++--
 drivers/clk/mmp/clk-pxa910.c         |  31 ++--
 drivers/clk/mxs/clk.h                |   4 +-
 drivers/clk/samsung/clk.h            |   2 +-
 drivers/clk/spear/spear1310_clock.c  | 179 +++++++++++-----------
 drivers/clk/spear/spear1340_clock.c  |  97 ++++++------
 drivers/clk/spear/spear3xx_clock.c   |  57 ++++---
 drivers/clk/spear/spear6xx_clock.c   |  35 +++--
 drivers/clk/sunxi/clk-sunxi.c        |   3 +-
 drivers/clk/tegra/clk-tegra114.c     |  36 +++--
 drivers/clk/tegra/clk-tegra20.c      |   6 +-
 drivers/clk/tegra/clk-tegra30.c      |  33 +++--
 drivers/clk/versatile/clk-vexpress.c |   4 +-
 include/linux/clk-private.h          |   3 +
 include/linux/clk-provider.h         |  12 ++
 20 files changed, 556 insertions(+), 313 deletions(-)

-- 
1.8.1.2




From james.hogan at imgtec.com  Wed May 15 09:41:03 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Wed, 15 May 2013 14:41:03 +0100
Subject: [PATCH v3 4/4] clk: clk-mux: implement remuxing on set_rate
In-Reply-To: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368625263-23136-5-git-send-email-james.hogan@imgtec.com>

Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't
set. This implements determine_rate for clk-mux to propagate to each
parent and to choose the best one (like clk-divider this chooses the
parent which provides the fastest rate <= the requested rate).

The determine_rate op is implemented as a core helper function so that
it can be easily used by more complex clocks which incorporate muxes.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v3:

* rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
  to patch 3.

 drivers/clk/clk-mux.c        |  1 +
 drivers/clk/clk.c            | 49 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h |  3 +++
 3 files changed, 53 insertions(+)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 25b1734..cecfa01 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -100,6 +100,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 const struct clk_ops clk_mux_ops = {
 	.get_parent = clk_mux_get_parent,
 	.set_parent = clk_mux_set_parent,
+	.determine_rate = __clk_mux_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index a04ca28..773092f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -695,6 +695,55 @@ struct clk *__clk_lookup(const char *name)
 	return NULL;
 }
 
+/*
+ * Helper for finding best parent to provide a given frequency. This can be used
+ * directly as a determine_rate callback (e.g. for a mux), or from a more
+ * complex clock that may combine a mux with other operations.
+ */
+long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *best_parent_rate,
+			      struct clk **best_parent_p)
+{
+	struct clk *clk = hw->clk, *parent, *best_parent = NULL;
+	int i, num_parents;
+	unsigned long parent_rate, best = 0;
+
+	/* if NO_REPARENT flag set, pass through to current parent */
+	if (clk->flags & CLK_SET_RATE_NO_REPARENT) {
+		parent = clk->parent;
+		if (clk->flags & CLK_SET_RATE_PARENT)
+			best = __clk_round_rate(parent, rate);
+		else if (parent)
+			best = __clk_get_rate(parent);
+		else
+			best = __clk_get_rate(clk);
+		goto out;
+	}
+
+	/* find the parent that can provide the fastest rate <= rate */
+	num_parents = clk->num_parents;
+	for (i = 0; i < num_parents; i++) {
+		parent = clk_get_parent_by_index(clk, i);
+		if (!parent)
+			continue;
+		if (clk->flags & CLK_SET_RATE_PARENT)
+			parent_rate = __clk_round_rate(parent, rate);
+		else
+			parent_rate = __clk_get_rate(parent);
+		if (parent_rate <= rate && parent_rate > best) {
+			best_parent = parent;
+			best = parent_rate;
+		}
+	}
+
+out:
+	if (best_parent_p && best_parent)
+		*best_parent_p = best_parent;
+	*best_parent_rate = best;
+
+	return best;
+}
+
 /***        clk api        ***/
 
 void __clk_unprepare(struct clk *clk)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index bb2d812..d6057eb 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -419,6 +419,9 @@ unsigned long __clk_get_flags(struct clk *clk);
 bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
+long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *best_parent_rate,
+			      struct clk **best_parent_p);
 
 /*
  * FIXME clock api without lock protection
-- 
1.8.1.2




From james.hogan at imgtec.com  Wed May 15 09:41:01 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Wed, 15 May 2013 14:41:01 +0100
Subject: [PATCH v3 2/4] clk: add support for clock reparent on set_rate
In-Reply-To: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>

Add core support to allow clock implementations to select the best
parent clock when rounding a rate, e.g. the one which can provide the
closest clock rate to that requested. This is by way of adding a new
clock op, determine_rate(), which is like round_rate() but has an extra
parameter to allow the clock implementation to optionally select a
different parent clock. The core then takes care of reparenting the
clock when setting the rate.

The parent change takes place with the help of two new private data
members. struct clk::new_parent specifies a clock's new parent (NULL
indicates no change), and struct clk::new_child specifies a clock's new
child (whose new_parent member points back to it). The purpose of these
are to allow correct walking of the future tree for notifications prior
to actually reparenting any clocks, specifically to skip child clocks
who are being reparented to another clock (they will be notified via the
new parent), and to include any new child clock. These pointers are set
by clk_calc_subtree(), and the new_child pointer gets cleared when a
child is actually reparented to avoid duplicate POST_RATE_CHANGE
notifications.

Each place where round_rate() is called, determine_rate is checked first
and called in preference, passing NULL to the new parent argument if not
needed (e.g. in __clk_round_rate). This restructures a few of the call
sites to simplify the logic into if/else blocks.

A new __clk_set_parent_no_recalc() is created similar to
clk_set_parent() but without calling __clk_recalc_rates(). This is for
clk_change_rate() to use, where rate recalculation and notifications are
already handled.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v3:

* rebased on v3.10-rc1
* store new_parent_index in struct clk too (calculated from
  clk_fetch_parent_index, and passed through __clk_set_parent_no_recalc
  to __clk_set_parent).
* allow determine_rate to satisfy recalc_rate check in __clk_init.

 Documentation/clk.txt        |   4 +
 drivers/clk/clk.c            | 208 +++++++++++++++++++++++++++++--------------
 include/linux/clk-private.h  |   3 +
 include/linux/clk-provider.h |   7 ++
 4 files changed, 154 insertions(+), 68 deletions(-)

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index b9911c2..3110ba4 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -70,6 +70,10 @@ the operations defined in clk.h:
 						unsigned long parent_rate);
 		long		(*round_rate)(struct clk_hw *hw, unsigned long,
 						unsigned long *);
+		long		(*determine_rate)(struct clk_hw *hw,
+						unsigned long rate,
+						unsigned long *best_parent_rate,
+						struct clk **best_parent_clk);
 		int		(*set_parent)(struct clk_hw *hw, u8 index);
 		u8		(*get_parent)(struct clk_hw *hw);
 		int		(*set_rate)(struct clk_hw *hw, unsigned long);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9bf4167..a04ca28 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -34,6 +34,9 @@ static HLIST_HEAD(clk_root_list);
 static HLIST_HEAD(clk_orphan_list);
 static LIST_HEAD(clk_notifier_list);
 
+static int __clk_set_parent_no_recalc(struct clk *clk, struct clk *parent,
+				      u8 p_index);
+
 /***           locking             ***/
 static void clk_prepare_lock(void)
 {
@@ -892,17 +895,20 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 	if (!clk)
 		return 0;
 
-	if (!clk->ops->round_rate) {
-		if (clk->flags & CLK_SET_RATE_PARENT)
-			return __clk_round_rate(clk->parent, rate);
-		else
-			return clk->rate;
-	}
 
 	if (clk->parent)
 		parent_rate = clk->parent->rate;
 
-	return clk->ops->round_rate(clk->hw, rate, &parent_rate);
+	if (clk->ops->determine_rate)
+		return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
+						NULL);
+	else if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk->hw, rate, &parent_rate);
+	else if (clk->flags & CLK_SET_RATE_PARENT)
+		return __clk_round_rate(clk->parent, rate);
+	else
+		return clk->rate;
+
 }
 
 /**
@@ -1027,6 +1033,32 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(clk_get_rate);
 
+static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
+{
+	u8 i;
+
+	if (!clk->parents)
+		clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
+								GFP_KERNEL);
+
+	/*
+	 * find index of new parent clock using cached parent ptrs,
+	 * or if not yet cached, use string name comparison and cache
+	 * them now to avoid future calls to __clk_lookup.
+	 */
+	for (i = 0; i < clk->num_parents; i++) {
+		if (clk->parents && clk->parents[i] == parent)
+			break;
+		else if (!strcmp(clk->parent_names[i], parent->name)) {
+			if (clk->parents)
+				clk->parents[i] = __clk_lookup(parent->name);
+			break;
+		}
+	}
+
+	return i;
+}
+
 /**
  * __clk_speculate_rates
  * @clk: first clk in the subtree
@@ -1071,18 +1103,24 @@ out:
 	return ret;
 }
 
-static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
+static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
+			     struct clk *new_parent, u8 p_index)
 {
 	struct clk *child;
 
 	clk->new_rate = new_rate;
+	clk->new_parent = new_parent;
+	clk->new_parent_index = p_index;
+	clk->new_child = NULL;
+	if (new_parent && new_parent != clk->parent)
+		new_parent->new_child = clk;
 
 	hlist_for_each_entry(child, &clk->children, child_node) {
 		if (child->ops->recalc_rate)
 			child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
 		else
 			child->new_rate = new_rate;
-		clk_calc_subtree(child, child->new_rate);
+		clk_calc_subtree(child, child->new_rate, NULL, 0);
 	}
 }
 
@@ -1093,50 +1131,63 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
 static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
 	struct clk *top = clk;
+	struct clk *old_parent, *parent;
 	unsigned long best_parent_rate = 0;
 	unsigned long new_rate;
+	u8 p_index = 0;
 
 	/* sanity */
 	if (IS_ERR_OR_NULL(clk))
 		return NULL;
 
 	/* save parent rate, if it exists */
-	if (clk->parent)
-		best_parent_rate = clk->parent->rate;
-
-	/* never propagate up to the parent */
-	if (!(clk->flags & CLK_SET_RATE_PARENT)) {
-		if (!clk->ops->round_rate) {
-			clk->new_rate = clk->rate;
-			return NULL;
-		}
-		new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
+	parent = old_parent = clk->parent;
+	if (parent)
+		best_parent_rate = parent->rate;
+
+	/* find the closest rate and parent clk/rate */
+	if (clk->ops->determine_rate) {
+		new_rate = clk->ops->determine_rate(clk->hw, rate,
+						    &best_parent_rate,
+						    &parent);
+	} else if (clk->ops->round_rate) {
+		new_rate = clk->ops->round_rate(clk->hw, rate,
+						&best_parent_rate);
+	} else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
+		/* pass-through clock without adjustable parent */
+		clk->new_rate = clk->rate;
+		return NULL;
+	} else {
+		/* pass-through clock with adjustable parent */
+		top = clk_calc_new_rates(parent, rate);
+		new_rate = parent->new_rate;
 		goto out;
 	}
 
-	/* need clk->parent from here on out */
-	if (!clk->parent) {
-		pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
+	/* some clocks must be gated to change parent */
+	if (parent != old_parent &&
+	    (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
+		pr_debug("%s: %s not gated but wants to reparent\n",
+			 __func__, clk->name);
 		return NULL;
 	}
 
-	if (!clk->ops->round_rate) {
-		top = clk_calc_new_rates(clk->parent, rate);
-		new_rate = clk->parent->new_rate;
-
-		goto out;
+	/* try finding the new parent index */
+	if (parent) {
+		p_index = clk_fetch_parent_index(clk, parent);
+		if (p_index == clk->num_parents) {
+			pr_debug("%s: clk %s can not be parent of clk %s\n",
+				 __func__, parent->name, clk->name);
+			return NULL;
+		}
 	}
 
-	new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
-
-	if (best_parent_rate != clk->parent->rate) {
-		top = clk_calc_new_rates(clk->parent, best_parent_rate);
-
-		goto out;
-	}
+	if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
+	    best_parent_rate != parent->rate)
+		top = clk_calc_new_rates(parent, best_parent_rate);
 
 out:
-	clk_calc_subtree(clk, new_rate);
+	clk_calc_subtree(clk, new_rate, parent, p_index);
 
 	return top;
 }
@@ -1148,7 +1199,7 @@ out:
  */
 static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
 {
-	struct clk *child, *fail_clk = NULL;
+	struct clk *child, *tmp_clk, *fail_clk = NULL;
 	int ret = NOTIFY_DONE;
 
 	if (clk->rate == clk->new_rate)
@@ -1161,9 +1212,19 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
 	}
 
 	hlist_for_each_entry(child, &clk->children, child_node) {
-		clk = clk_propagate_rate_change(child, event);
-		if (clk)
-			fail_clk = clk;
+		/* Skip children who will be reparented to another clock */
+		if (child->new_parent && child->new_parent != clk)
+			continue;
+		tmp_clk = clk_propagate_rate_change(child, event);
+		if (tmp_clk)
+			fail_clk = tmp_clk;
+	}
+
+	/* handle the new child who might not be in clk->children yet */
+	if (clk->new_child) {
+		tmp_clk = clk_propagate_rate_change(clk->new_child, event);
+		if (tmp_clk)
+			fail_clk = tmp_clk;
 	}
 
 	return fail_clk;
@@ -1181,6 +1242,11 @@ static void clk_change_rate(struct clk *clk)
 
 	old_rate = clk->rate;
 
+	/* set parent */
+	if (clk->new_parent && clk->new_parent != clk->parent)
+		__clk_set_parent_no_recalc(clk, clk->new_parent,
+					   clk->new_parent_index);
+
 	if (clk->parent)
 		best_parent_rate = clk->parent->rate;
 
@@ -1195,8 +1261,15 @@ static void clk_change_rate(struct clk *clk)
 	if (clk->notifier_count && old_rate != clk->rate)
 		__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
 
-	hlist_for_each_entry(child, &clk->children, child_node)
+	hlist_for_each_entry(child, &clk->children, child_node) {
+		/* Skip children who will be reparented to another clock */
+		if (child->new_parent && child->new_parent != clk)
+			continue;
 		clk_change_rate(child);
+	}
+
+	if (clk->new_child)
+		clk_change_rate(clk->new_child);
 }
 
 /**
@@ -1336,6 +1409,9 @@ out:
 
 static void clk_reparent(struct clk *clk, struct clk *new_parent)
 {
+	if (new_parent->new_child == clk)
+		new_parent->new_child = NULL;
+
 	hlist_del(&clk->child_node);
 
 	if (new_parent)
@@ -1353,32 +1429,6 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
 	__clk_recalc_rates(clk, POST_RATE_CHANGE);
 }
 
-static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
-{
-	u8 i;
-
-	if (!clk->parents)
-		clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
-								GFP_KERNEL);
-
-	/*
-	 * find index of new parent clock using cached parent ptrs,
-	 * or if not yet cached, use string name comparison and cache
-	 * them now to avoid future calls to __clk_lookup.
-	 */
-	for (i = 0; i < clk->num_parents; i++) {
-		if (clk->parents && clk->parents[i] == parent)
-			break;
-		else if (!strcmp(clk->parent_names[i], parent->name)) {
-			if (clk->parents)
-				clk->parents[i] = __clk_lookup(parent->name);
-			break;
-		}
-	}
-
-	return i;
-}
-
 static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
 {
 	unsigned long flags;
@@ -1451,6 +1501,27 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
 	return 0;
 }
 
+static int __clk_set_parent_no_recalc(struct clk *clk, struct clk *parent,
+				      u8 p_index)
+{
+	int ret = 0;
+
+	if (clk->parent == parent)
+		goto out;
+
+	/* only re-parent if the clock is not in use */
+	ret = __clk_set_parent(clk, parent, p_index);
+	if (ret)
+		goto out;
+
+	/* reparent, but don't propagate rate recalculation downstream */
+	clk_reparent(clk, parent);
+	clk_debug_reparent(clk, parent);
+
+out:
+	return ret;
+}
+
 /**
  * clk_set_parent - switch the parent of a mux clk
  * @clk: the mux clk whose input we are switching
@@ -1553,8 +1624,9 @@ int __clk_init(struct device *dev, struct clk *clk)
 
 	/* check that clk_ops are sane.  See Documentation/clk.txt */
 	if (clk->ops->set_rate &&
-			!(clk->ops->round_rate && clk->ops->recalc_rate)) {
-		pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
+	    !((clk->ops->round_rate || clk->ops->determine_rate) &&
+	      clk->ops->recalc_rate)) {
+		pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
 				__func__, clk->name);
 		ret = -EINVAL;
 		goto out;
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index dd7adff..8138c94 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -33,8 +33,11 @@ struct clk {
 	const char		**parent_names;
 	struct clk		**parents;
 	u8			num_parents;
+	u8			new_parent_index;
 	unsigned long		rate;
 	unsigned long		new_rate;
+	struct clk		*new_parent;
+	struct clk		*new_child;
 	unsigned long		flags;
 	unsigned int		enable_count;
 	unsigned int		prepare_count;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 76b1667..24cb2ee 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -79,6 +79,10 @@ struct clk_hw;
  * @round_rate:	Given a target rate as input, returns the closest rate actually
  * 		supported by the clock.
  *
+ * @determine_rate: Given a target rate as input, returns the closest rate
+ *		actually supported by the clock, and optionally the parent clock
+ *		that should be used to provide the clock rate.
+ *
  * @get_parent:	Queries the hardware to determine the parent of a clock.  The
  * 		return value is a u8 which specifies the index corresponding to
  * 		the parent clock.  This index can be applied to either the
@@ -126,6 +130,9 @@ struct clk_ops {
 					unsigned long parent_rate);
 	long		(*round_rate)(struct clk_hw *hw, unsigned long,
 					unsigned long *);
+	long		(*determine_rate)(struct clk_hw *hw, unsigned long rate,
+					unsigned long *best_parent_rate,
+					struct clk **best_parent_clk);
 	int		(*set_parent)(struct clk_hw *hw, u8 index);
 	u8		(*get_parent)(struct clk_hw *hw);
 	int		(*set_rate)(struct clk_hw *hw, unsigned long,
-- 
1.8.1.2




From james.hogan at imgtec.com  Wed May 15 09:41:02 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Wed, 15 May 2013 14:41:02 +0100
Subject: [PATCH v3 3/4] clk: add CLK_SET_RATE_NO_REPARENT flag
In-Reply-To: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1368625263-23136-4-git-send-email-james.hogan@imgtec.com>

Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Viresh Kumar <viresh.linux at gmail.com>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Chao Xie <xiechao.mail at gmail.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: "Emilio L?pez" <emilio at elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad at nvidia.com>
Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Joseph Lo <josephl at nvidia.com>
Cc: Peter De Schrijver <pdeschrijver at nvidia.com>
Cc: Pawel Moll <pawel.moll at arm.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: spear-devel at list.st.com
Cc: linux-tegra at vger.kernel.org
---
Changes in v3:

* rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
  to this new patch.
* patch 3: add CLK_SET_RATE_NO_REPARENT flag to all callers of
  clk_register_mux. If you don't mind your clocks being reparented in
  response to set_rate please let me know and I'll drop the relevant
  portion of the patch.

 arch/arm/mach-imx/clk.h              |   5 +-
 drivers/clk/mmp/clk-mmp2.c           |  39 +++++---
 drivers/clk/mmp/clk-pxa168.c         |  40 +++++---
 drivers/clk/mmp/clk-pxa910.c         |  31 +++---
 drivers/clk/mxs/clk.h                |   4 +-
 drivers/clk/samsung/clk.h            |   2 +-
 drivers/clk/spear/spear1310_clock.c  | 179 ++++++++++++++++++-----------------
 drivers/clk/spear/spear1340_clock.c  |  97 ++++++++++---------
 drivers/clk/spear/spear3xx_clock.c   |  57 +++++++----
 drivers/clk/spear/spear6xx_clock.c   |  35 +++----
 drivers/clk/sunxi/clk-sunxi.c        |   3 +-
 drivers/clk/tegra/clk-tegra114.c     |  36 ++++---
 drivers/clk/tegra/clk-tegra20.c      |   6 +-
 drivers/clk/tegra/clk-tegra30.c      |  33 ++++---
 drivers/clk/versatile/clk-vexpress.c |   4 +-
 include/linux/clk-provider.h         |   1 +
 16 files changed, 334 insertions(+), 238 deletions(-)

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c..244db2b 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -77,7 +77,8 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
+	return clk_register_mux(NULL, name, parents, num_parents,
+			CLK_SET_RATE_NO_REPARENT, reg, shift,
 			width, 0, &imx_ccm_lock);
 }
 
@@ -86,7 +87,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
 		int num_parents, unsigned long flags)
 {
 	return clk_register_mux(NULL, name, parents, num_parents,
-			flags, reg, shift, width, 0,
+			flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
 			&imx_ccm_lock);
 }
 
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index d1f1a19..b2721ca 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -248,7 +248,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
 
 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -258,7 +259,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 
 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -268,7 +270,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 
 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -278,7 +281,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 
 	clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.3", NULL);
@@ -288,7 +292,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
 
 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
 
@@ -297,7 +302,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 
 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
 
@@ -306,7 +312,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 
 	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.2", NULL);
 
@@ -315,7 +322,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 
 	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.3", NULL);
 
@@ -324,7 +332,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 
 	clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh_mux", NULL);
 
@@ -354,7 +363,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "usb_clk", NULL);
 
 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.0", NULL);
 
@@ -376,7 +386,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "disp_sphy.0", NULL);
 
 	clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.1", NULL);
 
@@ -394,7 +405,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "ccic_arbiter", NULL);
 
 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
 
@@ -421,7 +433,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
 
 	clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.1", NULL);
 
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 28b3b51..014396b 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -199,7 +199,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
 
 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -209,7 +210,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 
 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -219,7 +221,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 
 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -229,7 +232,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 
 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
 
@@ -238,7 +242,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 
 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
 
@@ -247,7 +252,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 
 	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.2", NULL);
 
@@ -256,7 +262,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 
 	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.3", NULL);
 
@@ -265,7 +272,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 
 	clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.4", NULL);
 
@@ -278,7 +286,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
 
 	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh0_mux", NULL);
 
@@ -287,7 +296,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
 
 	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh1_mux", NULL);
 
@@ -304,7 +314,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, "sph_clk", NULL);
 
 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.0", NULL);
 
@@ -317,7 +328,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, "hclk", "mmp-disp.0");
 
 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
 
@@ -327,8 +339,8 @@ void __init pxa168_clk_init(void)
 
 	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
 				ARRAY_SIZE(ccic_phy_parent),
-				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
-				7, 1, 0, &clk_lock);
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
 
 	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 6ec0569..9efc6a4 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -204,7 +204,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
 
 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -214,7 +215,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 
 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -224,7 +226,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 
 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -234,7 +237,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 
 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
 
@@ -243,7 +247,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 
 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
 
@@ -256,7 +261,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
 
 	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh0_mux", NULL);
 
@@ -265,7 +271,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
 
 	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh1_mux", NULL);
 
@@ -282,7 +289,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, "sph_clk", NULL);
 
 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.0", NULL);
 
@@ -291,7 +299,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-disp.0");
 
 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
 
@@ -301,8 +310,8 @@ void __init pxa910_clk_init(void)
 
 	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
 				ARRAY_SIZE(ccic_phy_parent),
-				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
-				7, 1, 0, &clk_lock);
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
 
 	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 81421e2..ef10ad9 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -52,8 +52,8 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parent_names, int num_parents)
 {
 	return clk_register_mux(NULL, name, parent_names, num_parents,
-				CLK_SET_RATE_PARENT, reg, shift, width,
-				0, &mxs_lock);
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+				reg, shift, width, 0, &mxs_lock);
 }
 
 static inline struct clk *mxs_clk_fixed_factor(const char *name,
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index e4ad6ea..eb672ba 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -127,7 +127,7 @@ struct samsung_mux_clock {
 		.name		= cname,			\
 		.parent_names	= pnames,			\
 		.num_parents	= ARRAY_SIZE(pnames),		\
-		.flags		= f,				\
+		.flags		= (f) | CLK_SET_RATE_NO_REPARENT, \
 		.offset		= o,				\
 		.shift		= s,				\
 		.width		= w,				\
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index aedbbe1..65894f7 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -416,9 +416,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	/* clock derived from 24 or 25 MHz osc clk */
 	/* vco-pll */
 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
-			SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
+			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco1_mclk", NULL);
 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
 			0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
@@ -427,9 +427,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "pll1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
-			SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
+			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco2_mclk", NULL);
 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
 			0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
@@ -438,9 +438,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "pll2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
-			SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
+			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco3_mclk", NULL);
 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
 			0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
@@ -515,9 +515,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* gpt clocks */
 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
@@ -525,9 +525,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
@@ -535,9 +535,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "gpt1");
 
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
@@ -545,9 +545,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "gpt2");
 
 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
@@ -562,7 +562,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
-			ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uart0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
 			SPEAR1310_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -602,7 +603,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
-			ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(c3_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
 			SPEAR1310_C3_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -614,8 +616,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* gmac */
 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
-			ARRAY_SIZE(gmac_phy_input_parents), 0,
-			SPEAR1310_GMAC_CLK_CFG,
+			ARRAY_SIZE(gmac_phy_input_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
 			SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 			SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -627,15 +629,16 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
-			ARRAY_SIZE(gmac_phy_parents), 0,
+			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 			SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
-			ARRAY_SIZE(clcd_synth_parents), 0,
-			SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
+			ARRAY_SIZE(clcd_synth_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
+			SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 			SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 
@@ -645,7 +648,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
-			ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(clcd_pixel_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 			SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -657,9 +661,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* i2s */
 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
-			ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
-			SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
+			SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 
 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
@@ -668,7 +672,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
-			ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(i2s_ref_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
 			SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -806,13 +811,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* RAS clks */
 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
-			ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
+			ARRAY_SIZE(gen_synth0_1_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
 			SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 			SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
-			ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
+			ARRAY_SIZE(gen_synth2_3_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
 			SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 			SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
@@ -929,8 +936,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
 			smii_rgmii_phy_parents,
-			ARRAY_SIZE(smii_rgmii_phy_parents), 0,
-			SPEAR1310_RAS_CTRL_REG1,
+			ARRAY_SIZE(smii_rgmii_phy_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
 			SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.1", NULL);
@@ -938,15 +945,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, "stmmacphy.4", NULL);
 
 	clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
-			ARRAY_SIZE(rmii_phy_parents), 0,
+			ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.3", NULL);
 
 	clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -955,9 +962,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5c800000.serial");
 
 	clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
@@ -966,9 +973,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5c900000.serial");
 
 	clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart3_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
@@ -977,9 +984,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5ca00000.serial");
 
 	clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart4_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
@@ -988,9 +995,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cb00000.serial");
 
 	clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart5_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
@@ -999,9 +1006,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cc00000.serial");
 
 	clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
@@ -1010,9 +1017,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cd00000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
@@ -1021,9 +1028,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5ce00000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c3_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
@@ -1032,9 +1039,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cf00000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c4_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
@@ -1043,9 +1050,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d000000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c5_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
@@ -1054,9 +1061,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d100000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c6_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
@@ -1065,9 +1072,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d200000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c7_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
@@ -1076,9 +1083,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d300000.i2c");
 
 	clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
-			ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
+			SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ssp1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
@@ -1087,9 +1094,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d400000.spi");
 
 	clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
-			ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
+			SPEAR1310_PCI_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "pci_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
@@ -1098,9 +1105,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "pci");
 
 	clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
-			ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
+			SPEAR1310_TDM_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "tdm1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
@@ -1109,9 +1116,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
 
 	clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
-			ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
+			SPEAR1310_TDM_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "tdm2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 9d0b394..fe835c1 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -473,9 +473,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	/* clock derived from 24 or 25 MHz osc clk */
 	/* vco-pll */
 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
-			SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
+			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco1_mclk", NULL);
 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
 			SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
@@ -484,9 +484,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "pll1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
-			SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
+			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco2_mclk", NULL);
 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
 			SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
@@ -495,9 +495,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "pll2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
-			SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
+			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco3_mclk", NULL);
 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
 			SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
@@ -561,8 +561,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "amba_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
-			ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
-			SPEAR1340_SCLK_SRC_SEL_SHIFT,
+			ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
 			SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "sys_mclk", NULL);
 
@@ -583,8 +583,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "smp_twd");
 
 	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
-			ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
-			SPEAR1340_HCLK_SRC_SEL_SHIFT,
+			ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
 			SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ahb_clk", NULL);
 
@@ -594,9 +594,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* gpt clocks */
 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
@@ -604,9 +604,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
@@ -614,9 +614,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "gpt1");
 
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
@@ -624,9 +624,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "gpt2");
 
 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
@@ -641,7 +641,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
-			ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uart0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
 			SPEAR1340_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -658,9 +659,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
-			ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
+			SPEAR1340_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -698,7 +699,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
-			ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(c3_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
 			SPEAR1340_C3_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -710,8 +712,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* gmac */
 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
-			ARRAY_SIZE(gmac_phy_input_parents), 0,
-			SPEAR1340_GMAC_CLK_CFG,
+			ARRAY_SIZE(gmac_phy_input_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
 			SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
 			SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -723,15 +725,16 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
-			ARRAY_SIZE(gmac_phy_parents), 0,
+			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
 			SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
-			ARRAY_SIZE(clcd_synth_parents), 0,
-			SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
+			ARRAY_SIZE(clcd_synth_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
+			SPEAR1340_CLCD_SYNT_CLK_SHIFT,
 			SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 
@@ -741,7 +744,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
-			ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(clcd_pixel_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
 			SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -753,9 +757,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* i2s */
 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
-			ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
-			SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
+			SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 
 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
@@ -765,7 +769,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
-			ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(i2s_ref_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
 			SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -891,13 +896,15 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* RAS clks */
 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
-			ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG,
+			ARRAY_SIZE(gen_synth0_1_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
 			SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
 
 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
-			ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG,
+			ARRAY_SIZE(gen_synth2_3_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
 			SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
@@ -938,7 +945,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "spear_cec.1");
 
 	clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
-			ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(spdif_out_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "spdif_out_mclk", NULL);
@@ -949,7 +957,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
 
 	clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
-			ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(spdif_in_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "spdif_in_mclk", NULL);
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index f9ec43f..4e3bb9e 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -294,7 +294,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
 	clk_register_clkdev(clk, NULL, "a9400000.i2s");
 
 	clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
-			ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(i2s_ref_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
 			I2S_REF_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_ref_clk", NULL);
@@ -313,57 +314,66 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
 	clk_register_clkdev(clk, "hclk", "ab000000.eth");
 
 	clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a9300000.serial");
 
 	clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
-			ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(sdhci_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "70000000.sdhci");
 
 	clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
-			ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
-			SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
+			ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
+			0, &_lock);
 	clk_register_clkdev(clk, NULL, "smii_pclk");
 
 	clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
 	clk_register_clkdev(clk, NULL, "smii");
 
 	clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "a3000000.serial");
 
 	clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a4000000.serial");
 
 	clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a9100000.serial");
 
 	clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a9200000.serial");
 
 	clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "60000000.serial");
 
 	clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "60100000.serial");
@@ -427,7 +437,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
-			ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uart0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
 			&_lock);
 	clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -444,7 +455,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
-			ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(firda_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
 			&_lock);
 	clk_register_clkdev(clk, "firda_mclk", NULL);
@@ -458,14 +470,16 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
 			ARRAY_SIZE(gpt_rtbl), &_lock);
 	clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
-			ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(gpt0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
 			ARRAY_SIZE(gpt_rtbl), &_lock);
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
-			ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(gpt1_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
@@ -476,7 +490,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
 			ARRAY_SIZE(gpt_rtbl), &_lock);
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
-			ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(gpt2_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
@@ -498,9 +513,9 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
-			ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
-			GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
+			CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
+			GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
 
 	clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
@@ -540,8 +555,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
-			ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
-			MCTR_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
+			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ddr_clk", NULL);
 
 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index 9406f24..4f649c9 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -169,8 +169,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
-			UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
+			&_lock);
 	clk_register_clkdev(clk, "uart_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
@@ -188,8 +189,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
-			ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
-			FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
+			&_lock);
 	clk_register_clkdev(clk, "firda_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
@@ -203,8 +205,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
-			ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
-			CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
+			&_lock);
 	clk_register_clkdev(clk, "clcd_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
@@ -217,13 +220,13 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
-			ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
-			GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
-			ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
-			GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
@@ -235,8 +238,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
-			ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
-			GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
@@ -248,8 +251,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
-			ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
-			GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
@@ -277,8 +280,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
-			ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
-			MCTR_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
+			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ddr_clk", NULL);
 
 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 8492ad1..390fe6f 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -261,7 +261,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
 	while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 		i++;
 
-	clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg,
+	clk = clk_register_mux(NULL, clk_name, parents, i,
+			       CLK_SET_RATE_NO_REPARENT, reg,
 			       data->shift, SUNXI_MUX_GATE_WIDTH,
 			       0, &clk_lock);
 
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..21aa7bb 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1435,7 +1435,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio0 */
 	clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
 			       NULL);
 	clks[audio0_mux] = clk;
@@ -1447,7 +1448,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio1 */
 	clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
 			       NULL);
 	clks[audio1_mux] = clk;
@@ -1459,7 +1461,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio2 */
 	clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
 			       NULL);
 	clks[audio2_mux] = clk;
@@ -1471,7 +1474,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio3 */
 	clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
 			       NULL);
 	clks[audio3_mux] = clk;
@@ -1483,7 +1487,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio4 */
 	clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
 			       NULL);
 	clks[audio4_mux] = clk;
@@ -1495,7 +1500,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* spdif */
 	clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
 			       NULL);
 	clks[spdif_mux] = clk;
@@ -1590,7 +1596,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_1 */
 	clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_1_mux] = clk;
@@ -1602,7 +1609,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_2 */
 	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_2_mux] = clk;
@@ -1614,7 +1622,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_3 */
 	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_3_mux] = clk;
@@ -1928,7 +1937,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 
 	/* dsia */
 	clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
-			       ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+			       ARRAY_SIZE(mux_plld_out0_plld2_out0),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
 	clks[dsia_mux] = clk;
 	clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
@@ -1938,7 +1948,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 
 	/* dsib */
 	clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
-			       ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+			       ARRAY_SIZE(mux_plld_out0_plld2_out0),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
 	clks[dsib_mux] = clk;
 	clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
@@ -1975,7 +1986,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm), 0,
+			       ARRAY_SIZE(mux_pllmcp_clkm),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       29, 3, 0, NULL);
 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 8292a00..48868deb 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -778,7 +778,8 @@ static void __init tegra20_audio_clk_init(void)
 
 	/* audio */
 	clk = clk_register_mux(NULL, "audio_mux", audio_parents,
-				ARRAY_SIZE(audio_parents), 0,
+				ARRAY_SIZE(audio_parents),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
 				clk_base + AUDIO_SYNC_CLK, 4,
@@ -933,7 +934,8 @@ static void __init tegra20_periph_clk_init(void)
 
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm), 0,
+			       ARRAY_SIZE(mux_pllmcp_clkm),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       30, 2, 0, NULL);
 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c6921f5..b4abfa5 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1008,7 +1008,8 @@ static void __init tegra30_pll_init(void)
 
 	/* PLLE */
 	clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
-			       ARRAY_SIZE(pll_e_parents), 0,
+			       ARRAY_SIZE(pll_e_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + PLLE_AUX, 2, 1, 0, NULL);
 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
 			     CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
@@ -1068,7 +1069,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio0 */
 	clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S0, 4,
@@ -1078,7 +1080,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio1 */
 	clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S1, 4,
@@ -1088,7 +1091,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio2 */
 	clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S2, 4,
@@ -1098,7 +1102,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio3 */
 	clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S3, 4,
@@ -1108,7 +1113,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio4 */
 	clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S4, 4,
@@ -1118,7 +1124,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* spdif */
 	clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
@@ -1211,7 +1218,8 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_1 */
 	clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_1_mux] = clk;
@@ -1223,7 +1231,8 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_2 */
 	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
 			       &clk_out_lock);
 	clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1234,7 +1243,8 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_3 */
 	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
 			       &clk_out_lock);
 	clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
@@ -1655,7 +1665,8 @@ static void __init tegra30_periph_clk_init(void)
 
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm), 0,
+			       ARRAY_SIZE(mux_pllmcp_clkm),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       30, 2, 0, NULL);
 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
index a4a728d..2d5e1b4 100644
--- a/drivers/clk/versatile/clk-vexpress.c
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -37,8 +37,8 @@ static void __init vexpress_sp810_init(void __iomem *base)
 		snprintf(name, ARRAY_SIZE(name), "timerclken%d", i);
 
 		vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name,
-				parents, 2, 0, base + SCCTRL,
-				SCCTRL_TIMERENnSEL_SHIFT(i), 1,
+				parents, 2, CLK_SET_RATE_NO_REPARENT,
+				base + SCCTRL, SCCTRL_TIMERENnSEL_SHIFT(i), 1,
 				0, &vexpress_sp810_lock);
 
 		if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i])))
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 24cb2ee..bb2d812 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -27,6 +27,7 @@
 #define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
 #define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
+#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
 
 struct clk_hw;
 
-- 
1.8.1.2




From gregory.clement at free-electrons.com  Wed May 15 09:54:14 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 15 May 2013 15:54:14 +0200
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <20130515134117.GH23869@mudshark.cambridge.arm.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
Message-ID: <51939386.7010709@free-electrons.com>

On 05/15/2013 03:41 PM, Will Deacon wrote:
> On Wed, May 15, 2013 at 02:18:53PM +0100, Gregory CLEMENT wrote:
>> Hi Will,
> 
> Hi Gregory,
> 
>> On 03/25/2013 07:19 PM, Will Deacon wrote:
>>> Many ARMv7 cores have hardware page table walkers that can read the L1
>>> cache. This is discoverable from the ID_MMFR3 register, although this
>>> can be expensive to access from the low-level set_pte functions and is a
>>> pain to cache, particularly with multi-cluster systems.
>>>
>>> A useful observation is that the multi-processing extensions for ARMv7
>>> require coherent table walks, meaning that we can make use of ALT_SMP
>>> patching in proc-v7-* to patch away the cache flush safely for these
>>> cores.
>>
>> I encountered a regression with 3.10-rc1 on the Armada 370 based boards.
>> With the 3.10-rc1 they hang during auto testy of the xor engine which are
>> mainly DMA transfers. If I revert this patch, it no more hang. I found this
>> by using bisect, it was not obvious at all for me that this patch may have
>> cause this regression.
> 
> Is this using dmatest.ko, or a different test program?

No they are self-test from the mv_xor driver

> 
>> The issue appear in SMP and in UP. However I think that  the PJ4B-v7 used in
>>  the Armada 370 are not MP capable.
> 
> Ok, so the ALT_UP case should be emitted after patching, correct?

Indeed it was I excepted but I didn't check (I don't know how to do)

> 
>> I made some investigation. And in UP if I remove the line:
>> 	ALT_UP(W(nop))
> 
> Did you remove the ALT_SMP case as well? You could also try making the
> ALT_SMP case use W(nop) too and see if it changes anything.

OK I will try it.

> 
>> at the begining of the cpu_v7_dcache_clean_are macro located in
>> arch/arm/mm/proc-v7.S
>>
>> Then the kernel boot again. It is not surprising because in this case
>> we found the same generated code that before this patch was applied.
>>
>> now I don't really understand why a W(nop) will cause this issue.
> 
> No, that sounds weird. Can you inspect the functions using JTAG after the smp
> patching code has executed?

No I can't: I don't have any JTAG :/

> 
>> In SMP mode even with this line removed the kernel hang, but in this case
>> I am not sure of what happen exactly and how the .alt.smp.init section is
>> used.
> 
> If you don't have both of the alternatives, things will go wrong.

For my own culture, how ALT_UP and ALT_SMP work in SMP case?
When I disassembled the proc-v7.o, I saw that the SMP variant of the code were
written. How the kernel switch to the UP version of the code?

> 
>> I hope you will find some explanation and solution to this bug, because currently
>> the only solution I have is to revert this patch.
> 
> Let's not jump to that just yet!

Sure I hope we will find a fix for that.
Thanks,

Gregory
-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linus.walleij at linaro.org  Wed May 15 09:54:55 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 15:54:55 +0200
Subject: [PATCH] ARM: ux500: select REGULATOR
In-Reply-To: <1368621401-18569-1-git-send-email-emilio@elopez.com.ar>
References: <1368621401-18569-1-git-send-email-emilio@elopez.com.ar>
Message-ID: <CACRpkdaDLJk5UE_10FQuFNishY4+bnKShJyeC0JOF33hUq2nqQ@mail.gmail.com>

On Wed, May 15, 2013 at 2:36 PM, Emilio L?pez <emilio at elopez.com.ar> wrote:

> MACH_MOP500 selects REGULATOR_FIXED_VOLTAGE but not REGULATOR. This
> patch makes it select the latter too.
>
> Seen as:
>     warning: (MACH_DOVE_DT && ARCH_KIRKWOOD_DT && MACH_AMS_DELTA &&
>     MACH_MOP500 && TPS6105X) selects REGULATOR_FIXED_VOLTAGE which has
>     unmet direct dependencies (REGULATOR)
>
> Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>

Applied for ux500 fixes.

Thanks!
Linus Walleij


From laurent.pinchart at ideasonboard.com  Wed May 15 09:55:45 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 15 May 2013 15:55:45 +0200
Subject: [RFC/PATCH] dma: of: Make of_dma_simple_xlate match on DMA device
 and channel ID
In-Reply-To: <51938FFD.2020300@metafoo.de>
References: <1368624449-29003-1-git-send-email-laurent.pinchart@ideasonboard.com>
 <51938FFD.2020300@metafoo.de>
Message-ID: <3106852.EdI2KVGSEm@avalon>

Hi Lars-Peter,

(CC'ing LAKML, I had forgotten to do so when I sent the patch)

On Wednesday 15 May 2013 15:39:09 Lars-Peter Clausen wrote:
> On 05/15/2013 03:27 PM, Laurent Pinchart wrote:
> > When translating a DT DMA channel specifier, the most common use case is
> > to match the DMA channel based on the channel DMA engine and channel ID.
> > Modify the of_dma_simple_xlate() function to do so, simplifying the API
> > for DMA engine drivers.
> > 
> > There is no need to check the DMA cells count in the filter function as
> > the check is already performed by the caller in of_dma_get_controller().
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> 
> Hi,
> 
> I've submitted a very similar patch some time ago, see
> https://lkml.org/lkml/2013/3/25/250

Thanks. So my patch makes at least some sense :-)

I had the impression that this is what omap-dma needs as well, hence the 
modification to the existing xlate function. I'm fine with a separate function 
as well if the current code covers different use cases.

> > ---
> > 
> >  drivers/dma/of-dma.c   | 39 +++++++++++++++++++++++++++++++--------
> >  drivers/dma/omap-dma.c |  8 +-------
> >  include/linux/of_dma.h |  5 -----
> >  3 files changed, 32 insertions(+), 20 deletions(-)
> > 
> > I've implemented this function while working on a DMA engine driver, and
> > realized that it wasn't specific to my driver at all. As I'm new to the
> > DMA engine API, I'd appreciate feedback on whether this change makes
> > sense, or if I should instead keep the existing of_dma_simple_xlate()
> > function and create a separate simple xlate helper.
> > 
> > diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
> > index 7aa0864..702a45d 100644
> > --- a/drivers/dma/of-dma.c
> > +++ b/drivers/dma/of-dma.c
> > @@ -202,6 +202,27 @@ struct dma_chan *of_dma_request_slave_channel(struct
> > device_node *np,
> >  	return NULL;
> >  }
> > 
> > +struct of_dma_filter_args {
> > +	struct dma_device *device;
> > +	unsigned int chan_id;
> > +};
> > +
> > +/**
> > + * of_dma_simple_xlate_filter - Channel filter function for
> > of_dma_simple_xlate + * @dma_chan:	pointer to candidate DMA channel
> > + * @param:	pointer to filter parameter
> > + *
> > + * Filter out candidate DMA channels that don't match the channel ID or
> > + * DMA engine device passed as arguments.
> > + */
> > +static bool of_dma_simple_xlate_filter(struct dma_chan *chan, void
> > *param)
> > +{
> > +	struct of_dma_filter_args *fargs = param;
> > +
> > +	return (chan->device == fargs->device) &&
> > +	       (chan->chan_id == fargs->chan_id);
> > +}
> > +
> >  /**
> >   * of_dma_simple_xlate - Simple DMA engine translation function
> >   * @dma_spec:	pointer to DMA specifier as found in the device tree
> > @@ -216,16 +237,18 @@ struct dma_chan *of_dma_request_slave_channel(struct
> > device_node *np,> 
> >  struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
> >  						struct of_dma *ofdma)
> >  {
> > -	int count = dma_spec->args_count;
> > -	struct of_dma_filter_info *info = ofdma->of_dma_data;
> > +	struct dma_device *dev = ofdma->of_dma_data;
> > +	struct of_dma_filter_args fargs;
> > +	dma_cap_mask_t cap;
> > 
> > -	if (!info || !info->filter_fn)
> > -		return NULL;
> > +	/* There's no need to specify matching caps as we're going to match a
> > +	 * specific DMA channel anyway.
> > +	 */
> > +	dma_cap_zero(cap);
> > 
> > -	if (count != 1)
> > -		return NULL;
> > +	fargs.device = dev;
> > +	fargs.chan_id = dma_spec->args[0];
> > 
> > -	return dma_request_channel(info->dma_cap, info->filter_fn,
> > -			&dma_spec->args[0]);
> > +	return dma_request_channel(cap, of_dma_simple_xlate_filter, &fargs);
> >  }
> >  EXPORT_SYMBOL_GPL(of_dma_simple_xlate);
> > diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> > index ec3fc4f..7e7ff06 100644
> > --- a/drivers/dma/omap-dma.c
> > +++ b/drivers/dma/omap-dma.c
> > @@ -69,10 +69,6 @@ static const unsigned es_bytes[] = {
> >  	[OMAP_DMA_DATA_TYPE_S32] = 4,
> >  };
> > 
> > -static struct of_dma_filter_info omap_dma_info = {
> > -	.filter_fn = omap_dma_filter_fn,
> > -};
> > -
> >  static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
> >  {
> >  	return container_of(d, struct omap_dmadev, ddev);
> > @@ -641,11 +637,9 @@ static int omap_dma_probe(struct platform_device
> > *pdev)> 
> >  	platform_set_drvdata(pdev, od);
> >  	if (pdev->dev.of_node) {
> > -		omap_dma_info.dma_cap = od->ddev.cap_mask;
> > -
> >  		/* Device-tree DMA controller registration */
> >  		rc = of_dma_controller_register(pdev->dev.of_node,
> > -				of_dma_simple_xlate, &omap_dma_info);
> > +				of_dma_simple_xlate, &od->ddev);
> >  		if (rc) {
> >  			pr_warn("OMAP-DMA: failed to register DMA controller\n");
> >  			dma_async_device_unregister(&od->ddev);
> > diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> > index 364dda7..3c0d9ac 100644
> > --- a/include/linux/of_dma.h
> > +++ b/include/linux/of_dma.h
> > @@ -27,11 +27,6 @@ struct of_dma {
> >  	void			*of_dma_data;
> >  };
> > 
> > -struct of_dma_filter_info {
> > -	dma_cap_mask_t	dma_cap;
> > -	dma_filter_fn	filter_fn;
> > -};
> > -
> > 
> >  #ifdef CONFIG_OF
> >  extern int of_dma_controller_register(struct device_node *np,
> >  		struct dma_chan *(*of_dma_xlate)
-- 
Regards,

Laurent Pinchart



From jagarwal at nvidia.com  Wed May 15 09:55:50 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 15 May 2013 19:25:50 +0530
Subject: [PATCH] Move PCIe node to correct place
Message-ID: <1368626150-25395-1-git-send-email-jagarwal@nvidia.com>

Moving PCIe controller node to correct place so
that it is sorted by register address in .dtsi file

Signed-off-by: Jay Agarwal <jagarwal at nvidia.com>
---
This patch is based on remotes/gitorious_thierryreding_linux/tegra/next
and should be applied on top of this.

 arch/arm/boot/dts/tegra30.dtsi |  132 ++++++++++++++++++++--------------------
 1 files changed, 66 insertions(+), 66 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5c1f7c0..a242b2e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -12,6 +12,72 @@
 		serial4 = &uarte;
 	};
 
+	pcie-controller {
+		compatible = "nvidia,tegra30-pcie";
+		device_type = "pci";
+		reg = <0x00003000 0x00000800   /* PADS registers */
+		       0x00003800 0x00000200   /* AFI registers */
+		       0x10000000 0x10000000>; /* configuration space */
+		reg-names = "pads", "afi", "cs";
+		interrupts = <0 98 0x04   /* controller interrupt */
+		              0 99 0x04>; /* MSI interrupt */
+
+		bus-range = <0x00 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
+			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
+			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
+			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
+			  0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
+			  0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
+
+		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
+			 <&tegra_car 118>, <&tegra_car 215>;
+		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		status = "disabled";
+
+		pci at 1,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
+			reg = <0x000800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+
+		pci at 2,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
+			reg = <0x001000 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+
+		pci at 3,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
+			reg = <0x001800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+	};
+
 	host1x {
 		compatible = "nvidia,tegra30-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
@@ -115,72 +181,6 @@
 		};
 	};
 
-	pcie-controller {
-		compatible = "nvidia,tegra30-pcie";
-		device_type = "pci";
-		reg = <0x00003000 0x00000800   /* PADS registers */
-		       0x00003800 0x00000200   /* AFI registers */
-		       0x10000000 0x10000000>; /* configuration space */
-		reg-names = "pads", "afi", "cs";
-		interrupts = <0 98 0x04   /* controller interrupt */
-		              0 99 0x04>; /* MSI interrupt */
-
-		bus-range = <0x00 0xff>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
-			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
-			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
-			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
-			  0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
-			  0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
-
-		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
-			 <&tegra_car 118>, <&tegra_car 215>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
-		status = "disabled";
-
-		pci at 1,0 {
-			device_type = "pci";
-			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
-			reg = <0x000800 0 0 0 0>;
-			status = "disabled";
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			nvidia,num-lanes = <2>;
-		};
-
-		pci at 2,0 {
-			device_type = "pci";
-			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
-			reg = <0x001000 0 0 0 0>;
-			status = "disabled";
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			nvidia,num-lanes = <2>;
-		};
-
-		pci at 3,0 {
-			device_type = "pci";
-			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
-			reg = <0x001800 0 0 0 0>;
-			status = "disabled";
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			nvidia,num-lanes = <2>;
-		};
-	};
-
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
-- 
1.7.0.4



From pavel at denx.de  Wed May 15 09:58:04 2013
From: pavel at denx.de (Pavel Machek)
Date: Wed, 15 May 2013 15:58:04 +0200
Subject: [PATCH 3/5] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1368571955-6652-3-git-send-email-dinguyen@altera.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-3-git-send-email-dinguyen@altera.com>
Message-ID: <20130515135804.GE9066@amd.pavel.ucw.cz>

Hi!

> Add support to gate the clocks that directly feed peripherals. For clocks
> with multiple parents, add the ability to determine the correct parent,
> and also set parents. Also add support to calculate and set the clocks'
> rate.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Mike Turquette <mturquette at linaro.org>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: <linux at arm.linux.org.uk>

> @@ -132,8 +147,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
>  
>  	socfpga_clk->hw.hw.init = &init;
>  
> -	if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
> -			strcmp(clk_name, "sdram_pll")) {
> +	if (strcmp(clk_name, "main_pll") == 0 ||
> +			strcmp(clk_name, "periph_pll") == 0 ||
> +			strcmp(clk_name, "sdram_pll") == 0) {
>  		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
>  		clk_pll_ops.enable = clk_gate_ops.enable;
>  		clk_pll_ops.disable = clk_gate_ops.disable;

Perhaps do

#define streq(a, b)   (strcmp((a), (b)) == 0)

and use that to simplify the conditions?

Actually, here are suggested cleanups. Note that there are two FIXMEs
-- I could not understand why the code is safe, and that the BUG_ON()s
are commented on. AFAICT I got them correct, but for some reason they
seem to trigger.

Thanks,
								Pavel

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index a0551f2..ddb340d 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,17 +24,17 @@
 #include <linux/of.h>
 
 /* Clock Manager offsets */
-#define CLKMGR_CTRL    0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL	0x0
+#define CLKMGR_BYPASS	0x4
 #define CLKMGR_L4SRC	0x70
 #define CLKMGR_PERPLL_SRC	0xAC
 
 /* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS		(1<<0)
+#define SDRAMPLL_BYPASS		(1<<1)
+#define SDRAMPLL_SRC_BYPASS	(1<<2)
+#define PERPLL_BYPASS		(1<<3)
+#define PERPLL_SRC_BYPASS	(1<<4)
 
 #define SOCFPGA_PLL_BG_PWRDWN		0
 #define SOCFPGA_PLL_EXT_ENA		1
@@ -45,14 +45,16 @@
 #define SOCFPGA_PLL_DIVQ_SHIFT	16
 #define SOCFGPA_MAX_PARENTS	3
 
-#define SOCFPGA_L4_MP_CLK			"l4_mp_clk"
-#define SOCFPGA_L4_SP_CLK			"l4_sp_clk"
+#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
 #define SOCFPGA_NAND_CLK		"nand_clk"
 #define SOCFPGA_NAND_X_CLK		"nand_x_clk"
 #define SOCFPGA_MMC_CLK			"mmc_clk"
 #define SOCFPGA_DB_CLK			"gpio_db_clk"
+#define SOCFPGA_QSPI_CLK		"qspi_clk"
 
 #define div_mask(width)	((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -62,8 +64,8 @@ struct socfpga_clk {
 	char *clk_name;
 	u32 fixed_div;
 	void __iomem *div_reg;
-	u32 width;
-	u32 shift;
+	u32 width;	/* only valid if div_reg != 0 */
+	u32 shift;	/* only valid if div_reg != 0 */
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -145,11 +147,12 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 
+	// FIXME: assigning automatic variable ptr into malloced structure?
 	socfpga_clk->hw.hw.init = &init;
 
-	if (strcmp(clk_name, "main_pll") == 0 ||
-			strcmp(clk_name, "periph_pll") == 0 ||
-			strcmp(clk_name, "sdram_pll") == 0) {
+	if (streq(clk_name, "main_pll") ||
+	    streq(clk_name, "periph_pll") ||
+	    streq(clk_name, "sdram_pll")) {
 		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
 		clk_pll_ops.enable = clk_gate_ops.enable;
 		clk_pll_ops.disable = clk_gate_ops.disable;
@@ -168,61 +171,57 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
 	u32 l4_src;
 	u32 perpll_src;
-	u8 parent;
 
-	if (strcmp(hwclk->init->name, SOCFPGA_L4_MP_CLK) == 0) {
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		l4_src &= 0x1;
-		parent = l4_src;
-	} else if (strcmp(hwclk->init->name, SOCFPGA_L4_SP_CLK) == 0) {
+		return l4_src & 1;
+	}
+	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		l4_src = ((l4_src & 0x2) >> 1);
-		parent = l4_src;
-	} else {
-		perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-		if (strcmp(hwclk->init->name, SOCFPGA_MMC_CLK) == 0)
-			perpll_src &= 0x3;
-		else if (strcmp(hwclk->init->name, SOCFPGA_NAND_CLK) == 0 ||
-			strcmp(hwclk->init->name, SOCFPGA_NAND_X_CLK) == 0)
-			perpll_src = ((perpll_src & 0xC) >> 2);
-		else /*QSPI clock */
-			perpll_src = ((perpll_src & 0x30) >> 4);
-		parent = perpll_src;
+		return !!(l4_src & 2);
 	}
+	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+		return perpll_src & 3;
+	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+	    streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+		return (perpll_src >> 2) & 3;
+
+	/* else QSPI clock */
+//	BUG_ON(!streq(hwclk->init->name, SOCFPGA_QSPI_CLK));
+	return (perpll_src >> 4) & 3;
+}
 
-	return parent;
+static int clrsetbits(u32 adr, u32 clr, u32 set)
+{
+	u32 reg;
+
+	reg = readl(adr);
+	reg &= ~clr;
+	reg |= set;
+	writel(reg, adr);
+	return 0;
 }
 
 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
 {
-	u32 src_reg;
-
-	if (strcmp(hwclk->init->name, SOCFPGA_L4_MP_CLK) == 0) {
-		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		src_reg &= ~0x1;
-		src_reg |= parent;
-		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
-	} else if (strcmp(hwclk->init->name, SOCFPGA_L4_SP_CLK) == 0) {
-		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		src_reg &= ~0x2;
-		src_reg |= (parent << 1);
-		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
-	} else {
-		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-		if (strcmp(hwclk->init->name, SOCFPGA_MMC_CLK) == 0) {
-			src_reg &= ~0x3;
-			src_reg |= parent;
-		} else if (strcmp(hwclk->init->name, SOCFPGA_NAND_CLK) == 0 ||
-			strcmp(hwclk->init->name, SOCFPGA_NAND_X_CLK) == 0) {
-			src_reg &= ~0xC;
-			src_reg |= (parent << 2);
-		} else {/*QSPI clock */
-			src_reg &= ~0x30;
-			src_reg |= (parent << 4);
-		}
-		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-	}
+//	BUG_ON(parent & ~3);
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK))
+		return clrsetbits(clk_mgr_base_addr + CLKMGR_L4SRC, 1, parent);
+	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK))
+		return clrsetbits(clk_mgr_base_addr + CLKMGR_L4SRC, 2, parent << 1);
 
+	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+		return clrsetbits(clk_mgr_base_addr + CLKMGR_PERPLL_SRC, 3, parent);
+	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+	    streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+		return clrsetbits(clk_mgr_base_addr + CLKMGR_PERPLL_SRC, 0xC, parent << 2);
+
+	/* else QSPI clock */
+//	BUG_ON(!streq(hwclk->init->name, SOCFPGA_QSPI_CLK));
+
+	clrsetbits(clk_mgr_base_addr + CLKMGR_PERPLL_SRC, 0x30, parent << 4);
 	return 0;
 }
 
@@ -237,7 +236,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 	else if (socfpgaclk->div_reg) {
 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
 		val &= div_mask(socfpgaclk->width);
-		if (strcmp(hwclk->init->name, SOCFPGA_DB_CLK) == 0)
+		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
 			div = val + 1;
 		else
 			div = (1 << val);
@@ -273,13 +272,6 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
 	if (rc)
 		clk_gate[0] = 0;
-
-	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
-	if (rc)
-		socfpga_clk->fixed_div = 0;
-	else
-		socfpga_clk->fixed_div = fixed_div;
-
 	if (clk_gate[0]) {
 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
 		socfpga_clk->hw.bit_idx = clk_gate[1];
@@ -288,6 +280,12 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
 		gateclk_ops.disable = clk_gate_ops.disable;
 	}
 
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		socfpga_clk->fixed_div = 0;
+	else
+		socfpga_clk->fixed_div = fixed_div;
+
 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
 	if (!rc) {
 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
@@ -302,12 +300,17 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
 	init.name = clk_name;
 	init.ops = ops;
 	init.flags = 0;
-	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
-			of_clk_get_parent_name(node, i)) != NULL)
+	while (i < SOCFGPA_MAX_PARENTS) {
+		char *name = of_clk_get_parent_name(node, i);
+		parent_name[i] = name;
+		if (name == NULL)
+			break;
 		i++;
+	}
 
 	init.parent_names = parent_name;
 	init.num_parents = i;
+	// FIXME: assigning automatic variable ptr into malloced structure?
 	socfpga_clk->hw.hw.init = &init;
 
 	clk = clk_register(NULL, &socfpga_clk->hw.hw);




-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From g.liakhovetski at gmx.de  Wed May 15 10:03:10 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 15 May 2013 16:03:10 +0200 (CEST)
Subject: [PATCH v3 01/20] sh-pfc: Add DT support
In-Reply-To: <1368577100-3530-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <Pine.LNX.4.64.1305151417300.10596@axis700.grange>

Hi Laurent

Thanks for your work on this! Sorry for jumping in so late in the game. 
Let's do it this way: I don't think my comments are serious enough to 
enforce a v4. If noone else complains, I'm fine with addressing them in an 
incremental patch. If you get more comments and have to do a v4, you can 
address mine too, otherwise I'm fine with this version going in and 
improving it slightly afterwards.

On Wed, 15 May 2013, Laurent Pinchart wrote:

> Support device instantiation through the device tree. The compatible
> property is used to select the SoC pinmux information.
> 
> Set the gpio_chip device field to the PFC device to enable automatic
> GPIO OF support.
> 
> Cc: devicetree-discuss at lists.ozlabs.org
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> ---
>  .../bindings/pinctrl/renesas,pfc-pinctrl.txt       | 143 ++++++++++++
>  drivers/pinctrl/sh-pfc/core.c                      |  66 +++++-
>  drivers/pinctrl/sh-pfc/pinctrl.c                   | 244 +++++++++++++++++++++
>  3 files changed, 451 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> new file mode 100644
> index 0000000..e7aae39
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> @@ -0,0 +1,143 @@
> +* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
> +
> +The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
> +SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
> +
> +
> +Pin Control
> +-----------
> +
> +Required Properties:
> +
> +  - compatible: should be one of the following.
> +    - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
> +    - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
> +    - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
> +    - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
> +    - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
> +    - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
> +    - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
> +
> +  - reg: Base address and length of each memory resource used by the pin
> +    controller hardware module.
> +
> +The PFC node also acts as a container for pin configuration nodes. Please refer
> +to pinctrl-bindings.txt in this directory for the definition of the term "pin
> +configuration node" and for the common pinctrl bindings used by client devices.
> +
> +Each pin configuration node represents a desired configuration for a pin, a
> +pin group, or a list of pins or pin groups. The configuration can include the
> +function to select on those pin(s) and pin configuration parameters (such as
> +pull-up and pull-down).
> +
> +Pin configuration nodes contain pin configuration properties, either directly
> +or grouped in child subnodes. Both pin muxing and configuration parameters can
> +be grouped in that way and referenced as a single pin configuration node by
> +client devices.
> +
> +A configuration node or subnode must reference at least one pin (through the
> +pins or pin groups properties) and contain at least a function or one
> +configuration parameter. When the function is present only pin groups can be
> +used to reference pins.
> +
> +All pin configuration nodes and subnodes names are ignored. All of those nodes
> +are parsed through phandles and processed purely based on their content.
> +
> +Pin Configuration Node Properties:
> +
> +- renesas,pins : An array of strings, each string containing the name of a pin.
> +- renesas,groups : An array of strings, each string containing the name of a pin
> +  group.
> +
> +- renesas,function: A string containing the name of the function to mux to the
> +  pin group(s) specified by the renesas,groups property
> +
> +  Valid values for pin, group and function names can be found in the group and
> +  function arrays of the PFC data file corresponding to the SoC
> +  (drivers/pinctrl/sh-pfc/pfc-*.c)
> +
> +- renesas,pull-up: An integer representing the pull-up strength to be applied
> +  to all pins specified by the renesas,pins and renesas-groups properties.
> +  0 disables the pull-up, 1 enables it. Other values should not be used.
> +- renesas,pull-down: An integer representing the pull-down strength to be
> +  applied to all pins specified by the renesas,pins and renesas-groups
> +  properties. 0 disables the pull-down, 1 enables it. Other values should not
> +  be used.
> +
> +
> +GPIO
> +----
> +
> +Required Properties:
> +
> +  - gpio-controller: Marks the device node as a gpio controller.
> +
> +  - #gpio-cells: Should be 2. The first cell is the pin number and the second
> +    cell is used to specify optional parameters as bit flags. Only the GPIO
> +    active low flag (bit 0) is currently supported.
> +
> +The syntax of the gpio specifier used by client nodes should be the following
> +with values derived from the SoC user manual.
> +
> +  <[phandle of the gpio controller node]
> +   [pin number within the gpio controller]
> +   [flags and pull up/down]>

How should pull up / down be specified? Above you say only "active low" is 
supported so far.

Actually, I'm a bit confused by how pinctrl and GPIO DT nodes should be 
implemented:

> +
> +
> +Examples
> +--------
> +
> +Example 1: SH73A0 (SH-Mobile AG5) pin controller node
> +
> +	pfc: pfc at e6050000 {
> +		compatible = "renesas,pfc-sh73a0";
> +		reg = <0xe6050000 0x8000>,
> +		      <0xe605801c 0x1c>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +	};

In this example you add one node, that implements both - a pinctrl and a 
GPIO controller. However, on some platforms you add two DT nodes: one for 
pinctrl and one for GPIO. While doing that your GPIO node has a compatible 
string like

		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";

Do I understand it right, that a separate DT node is used for a GPIO 
controller if the controllers are really well separated on the hardware, 
probably, don't share register address ranges? Is there a driver in the 
kernel, that actually probes those compatible strings? Or the driver for 
those GPIO controllers isn't DT based? Maybe at least a short explanation 
and an example with two DT nodes here, or a reference to another 
documentation would help.

[snip]

> diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
> index 3b2fd43..5fa1c6b 100644
> --- a/drivers/pinctrl/sh-pfc/core.c
> +++ b/drivers/pinctrl/sh-pfc/core.c
> @@ -18,6 +18,7 @@
>  #include <linux/ioport.h>
>  #include <linux/kernel.h>
>  #include <linux/module.h>
> +#include <linux/of_device.h>
>  #include <linux/pinctrl/machine.h>
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
> @@ -348,14 +349,74 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_OF

Not sure, is it really a good idea to use this #ifdef here? I think you 
could drop all 3 of them in this hunk:

[snip]

>  static int sh_pfc_probe(struct platform_device *pdev)
>  {
> +	const struct platform_device_id *platid = platform_get_device_id(pdev);
> +#ifdef CONFIG_OF

also here

> +	struct device_node *np = pdev->dev.of_node;
> +#endif
>  	const struct sh_pfc_soc_info *info;
>  	struct sh_pfc *pfc;
>  	int ret;
>  
> -	info = pdev->id_entry->driver_data
> -	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
> +	if (platid)
> +		info = (const void *)platid->driver_data;
> +#ifdef CONFIG_OF

and here.

> +	else if (np)
> +		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
> +#endif
> +	else
> +		info = pdev->dev.platform_data;
> +
>  	if (info == NULL)
>  		return -ENODEV;
>  

[snip]

> +static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
> +				 struct device_node *np,
> +				 struct pinctrl_map **map, unsigned *num_maps)
> +{
> +	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +	struct device *dev = pmx->pfc->dev;
> +	struct device_node *child;
> +	unsigned int index;
> +	int ret;
> +
> +	*map = NULL;
> +	*num_maps = 0;
> +	index = 0;
> +
> +	for_each_child_of_node(np, child) {
> +		ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
> +					       &index);
> +		if (ret < 0)
> +			goto done;
> +	}
> +
> +	/* If no mapping has been found in child nodes try the config node. */
> +	if (*num_maps == 0) {
> +		ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
> +		if (ret < 0)
> +			goto done;
> +	}
> +
> +	if (*num_maps == 0) {
> +		dev_err(dev, "no mapping found in node %s\n", np->full_name);
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +
> +	ret = 0;
> +
> +done:
> +	if (ret < 0)
> +		sh_pfc_dt_free_map(pctldev, *map, *num_maps);
> +
> +	return ret;
> +}

Maybe simpler

+	if (*num_maps)
+		return 0;
+
+	dev_err(dev, "no mapping found in node %s\n", np->full_name);
+	ret = -EINVAL;
+
+done:
+	sh_pfc_dt_free_map(pctldev, *map, *num_maps);
+
+	return ret;

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From thomas.petazzoni at free-electrons.com  Wed May 15 10:04:59 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 15 May 2013 16:04:59 +0200
Subject: [PATCH] arm: kirkwood: use the default of match table
Message-ID: <1368626700-29226-1-git-send-email-thomas.petazzoni@free-electrons.com>

mach-kirkwood/board-dt.c defines its own OF matching table, but in
fact, it is the same to the default of_default_bus_match_table[] which
is already used by mach-mvebu, mach-dove and mach-orion5x.

This patch therefore makes mach-kirkwood use the same default OF
matching table.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-kirkwood/board-dt.c |    7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..a8dae11 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -25,11 +25,6 @@
 #include <plat/common.h>
 #include "common.h"
 
-static struct of_device_id kirkwood_dt_match_table[] __initdata = {
-	{ .compatible = "simple-bus", },
-	{ }
-};
-
 /*
  * There are still devices that doesn't know about DT yet.  Get clock
  * gates here and add a clock lookup alias, so that old platform
@@ -159,7 +154,7 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("usi,topkick"))
 		usi_topkick_init();
 
-	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const kirkwood_dt_board_compat[] = {
-- 
1.7.9.5



From robdclark at gmail.com  Wed May 15 10:06:15 2013
From: robdclark at gmail.com (Rob Clark)
Date: Wed, 15 May 2013 10:06:15 -0400
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
Message-ID: <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>

On Wed, May 15, 2013 at 1:19 AM, Inki Dae <inki.dae at samsung.com> wrote:
>
>
>> -----Original Message-----
>> From: Rob Clark [mailto:robdclark at gmail.com]
>> Sent: Tuesday, May 14, 2013 10:39 PM
>> To: Inki Dae
>> Cc: linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham; YoungJun
>> Cho; linux-arm-kernel at lists.infradead.org; linux-media at vger.kernel.org
>> Subject: Re: Introduce a new helper framework for buffer synchronization
>>
>> On Mon, May 13, 2013 at 10:52 PM, Inki Dae <inki.dae at samsung.com> wrote:
>> >> well, for cache management, I think it is a better idea.. I didn't
>> >> really catch that this was the motivation from the initial patch, but
>> >> maybe I read it too quickly.  But cache can be decoupled from
>> >> synchronization, because CPU access is not asynchronous.  For
>> >> userspace/CPU access to buffer, you should:
>> >>
>> >>   1) wait for buffer
>> >>   2) prepare-access
>> >>   3)  ... do whatever cpu access to buffer ...
>> >>   4) finish-access
>> >>   5) submit buffer for new dma-operation
>> >>
>> >
>> >
>> > For data flow from CPU to DMA device,
>> > 1) wait for buffer
>> > 2) prepare-access (dma_buf_begin_cpu_access)
>> > 3) cpu access to buffer
>> >
>> >
>> > For data flow from DMA device to CPU
>> > 1) wait for buffer
>>
>> Right, but CPU access isn't asynchronous (from the point of view of
>> the CPU), so there isn't really any wait step at this point.  And if
>> you do want the CPU to be able to signal a fence from userspace for
>> some reason, you probably what something file/fd based so the
>> refcnting/cleanup when process dies doesn't leave some pending DMA
>> action wedged.  But I don't really see the point of that complexity
>> when the CPU access isn't asynchronous in the first place.
>>
>
> There was my missing comments, please see the below sequence.
>
> For data flow from CPU to DMA device and then from DMA device to CPU,
> 1) wait for buffer <- at user side - ioctl(fd, DMA_BUF_GET_FENCE, ...)
>         - including prepare-access (dma_buf_begin_cpu_access)
> 2) cpu access to buffer
> 3) wait for buffer <- at device driver
>         - but CPU is already accessing the buffer so blocked.
> 4) signal <- at user side - ioctl(fd, DMA_BUF_PUT_FENCE, ...)
> 5) the thread, blocked at 3), is waked up by 4).
>         - and then finish-access (dma_buf_end_cpu_access)

right, I understand you can have background threads, etc, in
userspace.  But there are already plenty of synchronization primitives
that can be used for cpu->cpu synchronization, either within the same
process or between multiple processes.  For cpu access, even if it is
handled by background threads/processes, I think it is better to use
the traditional pthreads or unix synchronization primitives.  They
have existed forever, they are well tested, and they work.

So while it seems nice and orthogonal/clean to couple cache and
synchronization and handle dma->cpu and cpu->cpu and cpu->dma in the
same generic way, but I think in practice we have to make things more
complex than they otherwise need to be to do this.  Otherwise I think
we'll be having problems with badly behaved or crashing userspace.

BR,
-R

> 6) dma access to buffer
> 7) wait for buffer <- at user side - ioctl(fd, DMA_BUF_GET_FENCE, ...)
>         - but DMA is already accessing the buffer so blocked.
> 8) signal <- at device driver
> 9) the thread, blocked at 7), is waked up by 8)
>         - and then prepare-access (dma_buf_begin_cpu_access)
> 10 cpu access to buffer
>
> Basically, 'wait for buffer' includes buffer synchronization, committing
> processing, and cache operation. The buffer synchronization means that a
> current thread should wait for other threads accessing a shared buffer until
> the completion of their access. And the committing processing means that a
> current thread possesses the shared buffer so any trying to access the
> shared buffer by another thread makes the thread to be blocked. However, as
> I already mentioned before, it seems that these user interfaces are so ugly
> yet. So we need better way.
>
> Give me more comments if there is my missing point :)
>
> Thanks,
> Inki Dae
>
>> BR,
>> -R
>>
>>
>> > 2) finish-access (dma_buf_end _cpu_access)
>> > 3) dma access to buffer
>> >
>> > 1) and 2) are coupled with one function: we have implemented
>> > fence_helper_commit_reserve() for it.
>> >
>> > Cache control(cache clean or cache invalidate) is performed properly
>> > checking previous access type and current access type.
>> > And the below is actual codes for it,
>


From will.deacon at arm.com  Wed May 15 10:06:07 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 15:06:07 +0100
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <51939386.7010709@free-electrons.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
Message-ID: <20130515140607.GI23869@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 02:54:14PM +0100, Gregory CLEMENT wrote:
> On 05/15/2013 03:41 PM, Will Deacon wrote:
> > Is this using dmatest.ko, or a different test program?
> 
> No they are self-test from the mv_xor driver

Ok. And the CPU locks up, rather than the DMA master?

> > Ok, so the ALT_UP case should be emitted after patching, correct?
> 
> Indeed it was I excepted but I didn't check (I don't know how to do)

If you don't have JTAG, that's trickier. Hopefully my other suggestion will
help.

> >> I made some investigation. And in UP if I remove the line:
> >> 	ALT_UP(W(nop))
> > 
> > Did you remove the ALT_SMP case as well? You could also try making the
> > ALT_SMP case use W(nop) too and see if it changes anything.
> 
> OK I will try it.

You could also try deleting both of the ALT_* lines and just putting a
W(nop) in there directly.

> > If you don't have both of the alternatives, things will go wrong.
> 
> For my own culture, how ALT_UP and ALT_SMP work in SMP case?
> When I disassembled the proc-v7.o, I saw that the SMP variant of the code were
> written. How the kernel switch to the UP version of the code?

Early in boot (head.S:__fixup_smp), we detect whether the CPU has the MP
extensions then, if we're actually UP but the kernel has CONFIG_SMP=y, we
walk over the .alt.smp.init section looking at each entry in there. The
ALT_UP macro spits out an (address, instruction) pair, so in
__do_fixup_smp_on_up, we store the instruction to the address for each pair,
replacing the SMP instruction which sat there in the compiled image.

It could be that the CPUID checks are failing on your Marvell part. Can you
tell me what you have in your mpidr (mrc p15, 0, Rd, c0, c0, 5) and also
your midr (mrc p15, 0, Rd, c0, c0) please?

Cheers,

Will


From plagnioj at jcrosoft.com  Wed May 15 10:03:03 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:03:03 +0200
Subject: [PATCH 3/5] ARM: at91: dt: add pinctrl pre-processor define
In-Reply-To: <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130515135821.GG22508@game.jcrosoft.org>
 <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368626585-24425-3-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 include/dt-bindings/pinctrl/at91.h |   35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/at91.h

diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
new file mode 100644
index 0000000..d7988b4
--- /dev/null
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -0,0 +1,35 @@
+/*
+ * This header provides constants for most at91 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
+#define __DT_BINDINGS_AT91_PINCTRL_H__
+
+#define AT91_PINCTRL_NONE		(0 << 0)
+#define AT91_PINCTRL_PULL_UP		(1 << 0)
+#define AT91_PINCTRL_MULTI_DRIVE	(1 << 1)
+#define AT91_PINCTRL_DEGLITCH		(1 << 2)
+#define AT91_PINCTRL_PULL_DOWN		(1 << 3)
+#define AT91_PINCTRL_DIS_SCHMIT		(1 << 4)
+#define AT91_PINCTRL_DEBOUNCE		(1 << 16)
+#define AT91_PINCTRL_DEBOUNCE_VA(x)	(x << 17)
+
+#define AT91_PINCTRL_PULL_UP_DEGLITCH	(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+
+#define AT91_PIOA	0
+#define AT91_PIOB	1
+#define AT91_PIOC	2
+#define AT91_PIOD	3
+#define AT91_PIOE	4
+
+#define AT91_PERIPH_GPIO	0
+#define AT91_PERIPH_A		1
+#define AT91_PERIPH_B		2
+#define AT91_PERIPH_C		3
+#define AT91_PERIPH_D		4
+
+#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Wed May 15 10:03:01 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:03:01 +0200
Subject: [PATCH 1/5] ARM: at91: dt: use #include for all device trees
In-Reply-To: <20130515135821.GG22508@game.jcrosoft.org>
References: <20130515135821.GG22508@game.jcrosoft.org>
Message-ID: <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>

to prepare the switch to the macro.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/aks-cdu.dts               |    2 +-
 arch/arm/boot/dts/animeo_ip.dts             |    2 +-
 arch/arm/boot/dts/at91-ariag25.dts          |    2 +-
 arch/arm/boot/dts/at91rm9200.dtsi           |    2 +-
 arch/arm/boot/dts/at91rm9200ek.dts          |    2 +-
 arch/arm/boot/dts/at91sam9260.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9263.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9263ek.dts         |    2 +-
 arch/arm/boot/dts/at91sam9g15.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g15ek.dts         |    4 ++--
 arch/arm/boot/dts/at91sam9g20.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g20ek.dts         |    2 +-
 arch/arm/boot/dts/at91sam9g20ek_2mmc.dts    |    2 +-
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    2 +-
 arch/arm/boot/dts/at91sam9g25.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g25ek.dts         |    4 ++--
 arch/arm/boot/dts/at91sam9g35.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g35ek.dts         |    4 ++--
 arch/arm/boot/dts/at91sam9g45.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |    2 +-
 arch/arm/boot/dts/at91sam9n12.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9n12ek.dts         |    2 +-
 arch/arm/boot/dts/at91sam9x25.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9x25ek.dts         |    4 ++--
 arch/arm/boot/dts/at91sam9x35.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9x35ek.dts         |    4 ++--
 arch/arm/boot/dts/at91sam9x5.dtsi           |    2 +-
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |    2 +-
 arch/arm/boot/dts/ethernut5.dts             |    2 +-
 arch/arm/boot/dts/evk-pro3.dts              |    4 ++--
 arch/arm/boot/dts/ge863-pro3.dtsi           |    2 +-
 arch/arm/boot/dts/kizbox.dts                |    4 ++--
 arch/arm/boot/dts/mpa1600.dts               |    2 +-
 arch/arm/boot/dts/pm9g45.dts                |    2 +-
 arch/arm/boot/dts/sama5d3.dtsi              |    2 +-
 arch/arm/boot/dts/sama5d31ek.dts            |    4 ++--
 arch/arm/boot/dts/sama5d33ek.dts            |    4 ++--
 arch/arm/boot/dts/sama5d34ek.dts            |    4 ++--
 arch/arm/boot/dts/sama5d35ek.dts            |    2 +-
 arch/arm/boot/dts/sama5d3xcm.dtsi           |    2 +-
 arch/arm/boot/dts/sama5d3xmb.dtsi           |    2 +-
 arch/arm/boot/dts/tny_a9260.dts             |    4 ++--
 arch/arm/boot/dts/tny_a9263.dts             |    2 +-
 arch/arm/boot/dts/tny_a9g20.dts             |    4 ++--
 arch/arm/boot/dts/usb_a9260.dts             |    4 ++--
 arch/arm/boot/dts/usb_a9263.dts             |    2 +-
 arch/arm/boot/dts/usb_a9g20.dts             |    4 ++--
 47 files changed, 61 insertions(+), 61 deletions(-)

diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
index 29b9f15..08b82a4 100644
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -9,7 +9,7 @@
 
 /dts-v1/;
 
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 5160210..b765892 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -7,7 +7,7 @@
  */
 
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
 	model = "Somfy Animeo IP";
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index c7aebba..09beeb4 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
+#include "at91sam9g25.dtsi"
 
 / {
 	model = "Acme Systems Aria G25";
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..6329679 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -10,7 +10,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel AT91RM9200 family SoC";
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index e586d85..5dffeb3 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 
 / {
 	model = "Atmel AT91RM9200 evaluation kit";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..b130b3e 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -8,7 +8,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel AT91SAM9260 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab..89f4e94 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel AT91SAM9263 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 3b82d91..6b646d4 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 
 / {
 	model = "Atmel at91sam9263ek";
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index 28467fd..cfd7044 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G15 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
index 5427b2d..26b0444 100644
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g15.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9g15.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G15-EK";
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 75ce6e7..b8e7946 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G20 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
index e5324bf..3f15a3f 100644
--- a/arch/arm/boot/dts/at91sam9g20ek.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20ek_common.dtsi"
+#include "at91sam9g20ek_common.dtsi"
 
 / {
 	model = "Atmel at91sam9g20ek";
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index 66467b1..942aa10 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20ek_common.dtsi"
+#include "at91sam9g20ek_common.dtsi"
 
 / {
 	model = "Atmel at91sam9g20ek 2 mmc";
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 6a92c5b..253960f 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -5,7 +5,7 @@
  *
  * Licensed under GPLv2.
  */
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
 
 / {
 
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 5fd32df..b4ec6fe 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index a1c511f..1e4c49c 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9g25.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G25-EK";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index d6fa8af..bebf9f5 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
index 6f58ab8..641a9bf 100644
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g35.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9g35.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G35-EK";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a73..18ea761 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -9,7 +9,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G45 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 51d9251b5..ba1205d 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g45.dtsi"
+#include "at91sam9g45.dtsi"
 
 / {
 	model = "Atmel AT91SAM9M10G45-EK";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3de8e6d..e848870 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel AT91SAM9N12 SoC";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d30e48b..b9e300e 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9n12.dtsi"
+#include "at91sam9n12.dtsi"
 
 / {
 	model = "Atmel AT91SAM9N12-EK";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 9ac2bc2..3f78d9b 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index 3b40d11..8ddbce0 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9x25.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x25.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G25-EK";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index ba67d83..1a3d525 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
index 6ad19a0..343d328 100644
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9x35.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x35.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X35-EK";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..69b386f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -9,7 +9,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel AT91SAM9x5 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 1fa48d2..24781f2 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -6,7 +6,7 @@
  *
  * Licensed under GPLv2 or later.
  */
-/include/ "at91sam9x5cm.dtsi"
+#include "at91sam9x5cm.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X5-EK";
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 1ea9d34..2067c66 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
 	model = "Ethernut 5";
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index 96e50f5..eae2cd7 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -9,7 +9,7 @@
 
 /dts-v1/;
 
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 
 / {
 	model = "Telit EVK-PRO3 for Telit GE863-PRO3";
@@ -50,4 +50,4 @@
 		status = "okay";
 	};
 
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 17136fc..230099b 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
 	clocks {
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index b4dc3ed..8328fed 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
 
 / {
 
@@ -137,4 +137,4 @@
 			gpio-key,wakeup;
 		};
 	};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index 3173008..f1b54a2 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 
 / {
 	model = "Phontech MPA 1600";
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 387fedb..639410b 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g45.dtsi"
+#include "at91sam9g45.dtsi"
 
 / {
 	model = "Ronetix pm9g45";
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..2293fa1 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -8,7 +8,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Atmel SAMA5D3 family SoC";
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index fa5d216..5bffd66 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
 
 / {
 	model = "Atmel SAMA5D31-EK";
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index c38c943..99bd0c8 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
 
 / {
 	model = "Atmel SAMA5D33-EK";
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index 6bebfcd..d88ff72 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
 
 / {
 	model = "Atmel SAMA5D34-EK";
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index a488fc4..3c364d2 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
+#include "sama5d3xmb.dtsi"
 
 / {
 	model = "Atmel SAMA5D35-EK";
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f8ed40..b552917 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -6,7 +6,7 @@
  *
  * Licensed under GPLv2 or later.
  */
-/include/ "sama5d3.dtsi"
+#include "sama5d3.dtsi"
 
 / {
 	compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 661d7ca..a5e7131 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -6,7 +6,7 @@
  *
  * Licensed under GPLv2 or later.
  */
-/include/ "sama5d3xcm.dtsi"
+#include "sama5d3xcm.dtsi"
 
 / {
 	compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
index 367a16d..dabe232 100644
--- a/arch/arm/boot/dts/tny_a9260.dts
+++ b/arch/arm/boot/dts/tny_a9260.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
-/include/ "tny_a9260_common.dtsi"
+#include "at91sam9260.dtsi"
+#include "tny_a9260_common.dtsi"
 
 / {
 	model = "Calao TNY A9260";
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index dee9c57..45f059b 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 
 / {
 	model = "Calao TNY A9263";
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
index e1ab64c..8456d70 100644
--- a/arch/arm/boot/dts/tny_a9g20.dts
+++ b/arch/arm/boot/dts/tny_a9g20.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
-/include/ "tny_a9260_common.dtsi"
+#include "at91sam9g20.dtsi"
+#include "tny_a9260_common.dtsi"
 
 / {
 	model = "Calao TNY A9G20";
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
index 2962160..a604107 100644
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
-/include/ "usb_a9260_common.dtsi"
+#include "at91sam9260.dtsi"
+#include "usb_a9260_common.dtsi"
 
 / {
 	model = "Calao USB A9260";
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 6fe05cc..82e204a 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 
 / {
 	model = "Calao USB A9263";
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 2dacb16c..c979c06 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
-/include/ "usb_a9260_common.dtsi"
+#include "at91sam9g20.dtsi"
+#include "usb_a9260_common.dtsi"
 
 / {
 	model = "Calao USB A9G20";
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Wed May 15 10:03:02 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:03:02 +0200
Subject: [PATCH 2/5] ARM: at91: dt: switch to standard GPIO flag defines.
In-Reply-To: <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130515135821.GG22508@game.jcrosoft.org>
 <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368626585-24425-2-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/aks-cdu.dts               |   10 ++++-----
 arch/arm/boot/dts/animeo_ip.dts             |   16 +++++++-------
 arch/arm/boot/dts/at91-ariag25.dts          |    4 ++--
 arch/arm/boot/dts/at91rm9200.dtsi           |    9 ++++----
 arch/arm/boot/dts/at91rm9200ek.dts          |    8 +++----
 arch/arm/boot/dts/at91sam9260.dtsi          |    9 ++++----
 arch/arm/boot/dts/at91sam9263.dtsi          |    9 ++++----
 arch/arm/boot/dts/at91sam9263ek.dts         |   18 ++++++++--------
 arch/arm/boot/dts/at91sam9g20ek.dts         |    4 ++--
 arch/arm/boot/dts/at91sam9g20ek_2mmc.dts    |    6 +++---
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    8 +++----
 arch/arm/boot/dts/at91sam9g45.dtsi          |    9 ++++----
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |   30 +++++++++++++--------------
 arch/arm/boot/dts/at91sam9n12.dtsi          |    9 ++++----
 arch/arm/boot/dts/at91sam9n12ek.dts         |   10 ++++-----
 arch/arm/boot/dts/at91sam9x5.dtsi           |   17 ++++++++-------
 arch/arm/boot/dts/at91sam9x5cm.dtsi         |    6 +++---
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |    8 +++----
 arch/arm/boot/dts/ethernut5.dts             |    4 ++--
 arch/arm/boot/dts/evk-pro3.dts              |    2 +-
 arch/arm/boot/dts/kizbox.dts                |   12 +++++------
 arch/arm/boot/dts/mpa1600.dts               |    2 +-
 arch/arm/boot/dts/pm9g45.dts                |   14 ++++++-------
 arch/arm/boot/dts/sama5d3.dtsi              |    1 +
 arch/arm/boot/dts/sama5d31ek.dts            |    2 +-
 arch/arm/boot/dts/sama5d34ek.dts            |    2 +-
 arch/arm/boot/dts/sama5d35ek.dts            |    2 +-
 arch/arm/boot/dts/sama5d3xcm.dtsi           |    2 +-
 arch/arm/boot/dts/sama5d3xmb.dtsi           |   12 +++++------
 arch/arm/boot/dts/tny_a9263.dts             |    2 +-
 arch/arm/boot/dts/usb_a9260_common.dtsi     |    6 +++---
 arch/arm/boot/dts/usb_a9263.dts             |    6 +++---
 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi    |   22 ++++++++++----------
 33 files changed, 144 insertions(+), 137 deletions(-)

diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
index 08b82a4..54cb5cf 100644
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -46,7 +46,7 @@
 			};
 
 			usb1: gadget at fffa4000 {
-				atmel,vbus-gpio = <&pioC 15 0>;
+				atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 		};
@@ -90,23 +90,23 @@
 		compatible = "gpio-leds";
 
 		red {
-			gpios = <&pioC 10 0>;
+			gpios = <&pioC 10 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "none";
 		};
 
 		green {
-			gpios = <&pioA 5 1>;
+			gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 			default-state = "on";
 		};
 
 		yellow {
-			gpios = <&pioB 20 1>;
+			gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 		};
 
 		blue {
-			gpios = <&pioB 21 1>;
+			gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 		};
 	};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index b765892..3a1de9e 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -123,7 +123,7 @@
 
 		usb0: ohci at 00500000 {
 			num-ports = <2>;
-			atmel,vbus-gpio = <&pioB 15 1>;
+			atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
 			status = "okay";
 		};
 	};
@@ -133,23 +133,23 @@
 
 		power_green {
 			label = "power_green";
-			gpios = <&pioC 17 0>;
+			gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		power_red {
 			label = "power_red";
-			gpios = <&pioA 2 0>;
+			gpios = <&pioA 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		tx_green {
 			label = "tx_green";
-			gpios = <&pioC 19 0>;
+			gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
 		};
 
 		tx_red {
 			label = "tx_red";
-			gpios = <&pioC 18 0>;
+			gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -160,21 +160,21 @@
 
 		keyswitch_in {
 			label = "keyswitch_in";
-			gpios = <&pioB 1 0>;
+			gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
 			linux,code = <28>;
 			gpio-key,wakeup;
 		};
 
 		error_in {
 			label = "error_in";
-			gpios = <&pioB 2 0>;
+			gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
 			linux,code = <29>;
 			gpio-key,wakeup;
 		};
 
 		btn {
 			label = "btn";
-			gpios = <&pioC 23 0>;
+			gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
 			linux,code = <31>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index 09beeb4..5ede767 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -156,7 +156,7 @@
 		/* little green LED in middle of Aria G25 module */
 		aria_led {
 			label = "aria_led";
-			gpios = <&pioB 8 0>; /* PB8 */
+			gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
 			linux,default-trigger = "heartbeat";
 		};
 
@@ -164,7 +164,7 @@
 
 	onewire at 0 {
 		compatible = "w1-gpio";
-		gpios = <&pioA 21 1>;
+		gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_w1_0>;
 	};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 6329679..7ebfe6c 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -11,6 +11,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel AT91RM9200 family SoC";
@@ -503,9 +504,9 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
 			nand-ecc-mode = "soft";
-			gpios = <&pioC 2 0
+			gpios = <&pioC 2 GPIO_ACTIVE_HIGH
 				 0
-				 &pioB 1 0
+				 &pioB 1 GPIO_ACTIVE_HIGH
 				>;
 			status = "disabled";
 		};
@@ -520,8 +521,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioA 25 0 /* sda */
-			 &pioA 26 0 /* scl */
+		gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 26 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 5dffeb3..1405812 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -50,7 +50,7 @@
 			};
 
 			usb1: gadget at fffb0000 {
-				atmel,vbus-gpio = <&pioD 4 0>;
+				atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 		};
@@ -66,19 +66,19 @@
 
 		ds2 {
 			label = "green";
-			gpios = <&pioB 0 0x1>;
+			gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "mmc0";
 		};
 
 		ds4 {
 			label = "yellow";
-			gpios = <&pioB 1 0x1>;
+			gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		ds6 {
 			label = "red";
-			gpios = <&pioB 2 0x1>;
+			gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index b130b3e..717625d 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel AT91SAM9260 family SoC";
@@ -567,8 +568,8 @@
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			gpios = <&pioC 13 0
-				 &pioC 14 0
+			gpios = <&pioC 13 GPIO_ACTIVE_HIGH
+				 &pioC 14 GPIO_ACTIVE_HIGH
 				 0
 				>;
 			status = "disabled";
@@ -584,8 +585,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioA 23 0 /* sda */
-			 &pioA 24 0 /* scl */
+		gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 24 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 89f4e94..5edfadf 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel AT91SAM9263 family SoC";
@@ -515,8 +516,8 @@
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			gpios = <&pioA 22 0
-				 &pioD 15 0
+			gpios = <&pioA 22 GPIO_ACTIVE_HIGH
+				 &pioD 15 GPIO_ACTIVE_HIGH
 				 0
 				>;
 			status = "disabled";
@@ -532,8 +533,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
+		gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
+			 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 6b646d4..e1942ec 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -51,7 +51,7 @@
 			};
 
 			usb1: gadget at fff78000 {
-				atmel,vbus-gpio = <&pioA 25 0>;
+				atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 
@@ -65,8 +65,8 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioE 18 0>;
-					wp-gpios = <&pioE 19 0>;
+					cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>;
+					wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -141,8 +141,8 @@
 		usb0: ohci at 00a00000 {
 			num-ports = <2>;
 			status = "okay";
-			atmel,vbus-gpio = <&pioA 24 0
-					   &pioA 21 0
+			atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH
+					   &pioA 21 GPIO_ACTIVE_HIGH
 					  >;
 		};
 	};
@@ -152,13 +152,13 @@
 
 		d3 {
 			label = "d3";
-			gpios = <&pioB 7 0>;
+			gpios = <&pioB 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		d2 {
 			label = "d2";
-			gpios = <&pioC 29 1>;
+			gpios = <&pioC 29 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "nand-disk";
 		};
 	};
@@ -168,14 +168,14 @@
 
 		left_click {
 			label = "left_click";
-			gpios = <&pioC 5 1>;
+			gpios = <&pioC 5 GPIO_ACTIVE_LOW>;
 			linux,code = <272>;
 			gpio-key,wakeup;
 		};
 
 		right_click {
 			label = "right_click";
-			gpios = <&pioC 4 1>;
+			gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
 			linux,code = <273>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
index 3f15a3f..bbfd753 100644
--- a/arch/arm/boot/dts/at91sam9g20ek.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -17,13 +17,13 @@
 
 		ds1 {
 			label = "ds1";
-			gpios = <&pioA 9 0>;
+			gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		ds5 {
 			label = "ds5";
-			gpios = <&pioA 6 1>;
+			gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index 942aa10..ec108b9 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -23,7 +23,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioC 2 0>;
+					cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -43,13 +43,13 @@
 
 		ds1 {
 			label = "ds1";
-			gpios = <&pioB 9 0>;
+			gpios = <&pioB 9 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		ds5 {
 			label = "ds5";
-			gpios = <&pioB 8 1>;
+			gpios = <&pioB 8 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 253960f..7933839 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -65,7 +65,7 @@
 			};
 
 			usb1: gadget at fffa4000 {
-				atmel,vbus-gpio = <&pioC 5 0>;
+				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 
@@ -79,7 +79,7 @@
 				slot at 1 {
 					reg = <1>;
 					bus-width = <4>;
-					cd-gpios = <&pioC 9 0>;
+					cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -180,14 +180,14 @@
 
 		btn3 {
 			label = "Button 3";
-			gpios = <&pioA 30 1>;
+			gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
 			linux,code = <0x103>;
 			gpio-key,wakeup;
 		};
 
 		btn4 {
 			label = "Button 4";
-			gpios = <&pioA 31 1>;
+			gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
 			linux,code = <0x104>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 18ea761..5d7c1f7 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel AT91SAM9G45 family SoC";
@@ -592,8 +593,8 @@
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			gpios = <&pioC 8 0
-				 &pioC 14 0
+			gpios = <&pioC 8 GPIO_ACTIVE_HIGH
+				 &pioC 14 GPIO_ACTIVE_HIGH
 				 0
 				>;
 			status = "disabled";
@@ -616,8 +617,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioA 20 0 /* sda */
-			 &pioA 21 0 /* scl */
+		gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index ba1205d..85e9c5e 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -68,7 +68,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 10 0>;
+					cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -81,8 +81,8 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 11 0>;
-					wp-gpios = <&pioD 29 0>;
+					cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
+					wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -139,8 +139,8 @@
 		usb0: ohci at 00700000 {
 			status = "okay";
 			num-ports = <2>;
-			atmel,vbus-gpio = <&pioD 1 1
-					   &pioD 3 1>;
+			atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
+					   &pioD 3 GPIO_ACTIVE_LOW>;
 		};
 
 		usb1: ehci at 00800000 {
@@ -153,19 +153,19 @@
 
 		d8 {
 			label = "d8";
-			gpios = <&pioD 30 0>;
+			gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		d6 {
 			label = "d6";
-			gpios = <&pioD 0 1>;
+			gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "nand-disk";
 		};
 
 		d7 {
 			label = "d7";
-			gpios = <&pioD 31 1>;
+			gpios = <&pioD 31 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "mmc0";
 		};
 	};
@@ -175,45 +175,45 @@
 
 		left_click {
 			label = "left_click";
-			gpios = <&pioB 6 1>;
+			gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
 			linux,code = <272>;
 			gpio-key,wakeup;
 		};
 
 		right_click {
 			label = "right_click";
-			gpios = <&pioB 7 1>;
+			gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
 			linux,code = <273>;
 			gpio-key,wakeup;
 		};
 
 		left {
 			label = "Joystick Left";
-			gpios = <&pioB 14 1>;
+			gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
 			linux,code = <105>;
 		};
 
 		right {
 			label = "Joystick Right";
-			gpios = <&pioB 15 1>;
+			gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
 			linux,code = <106>;
 		};
 
 		up {
 			label = "Joystick Up";
-			gpios = <&pioB 16 1>;
+			gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
 			linux,code = <103>;
 		};
 
 		down {
 			label = "Joystick Down";
-			gpios = <&pioB 17 1>;
+			gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
 			linux,code = <108>;
 		};
 
 		enter {
 			label = "Joystick Press";
-			gpios = <&pioB 18 1>;
+			gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
 			linux,code = <28>;
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e848870..5205403 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -8,6 +8,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel AT91SAM9N12 SoC";
@@ -438,8 +439,8 @@
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			gpios = <&pioD 5 0
-				 &pioD 4 0
+			gpios = <&pioD 5 GPIO_ACTIVE_HIGH
+				 &pioD 4 GPIO_ACTIVE_HIGH
 				 0
 				>;
 			status = "disabled";
@@ -455,8 +456,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
+		gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index b9e300e..8eece27 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -55,7 +55,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioA 7 0>;
+					cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -95,19 +95,19 @@
 
 		d8 {
 			label = "d8";
-			gpios = <&pioB 4 1>;
+			gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "mmc0";
 		};
 
 		d9 {
 			label = "d6";
-			gpios = <&pioB 5 1>;
+			gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "nand-disk";
 		};
 
 		d10 {
 			label = "d7";
-			gpios = <&pioB 6 0>;
+			gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
@@ -117,7 +117,7 @@
 
 		enter {
 			label = "Enter";
-			gpios = <&pioB 4 1>;
+			gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
 			linux,code = <28>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 69b386f..949b8ea 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel AT91SAM9x5 family SoC";
@@ -664,8 +665,8 @@
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			gpios = <&pioD 5 0
-				 &pioD 4 0
+			gpios = <&pioD 5 GPIO_ACTIVE_HIGH
+				 &pioD 4 GPIO_ACTIVE_HIGH
 				 0
 				>;
 			status = "disabled";
@@ -688,8 +689,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
+		gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
@@ -703,8 +704,8 @@
 
 	i2c at 1 {
 		compatible = "i2c-gpio";
-		gpios = <&pioC 0 0 /* sda */
-			 &pioC 1 0 /* scl */
+		gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
+			 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
@@ -718,8 +719,8 @@
 
 	i2c at 2 {
 		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
+		gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
+			 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 347a74a..94723c3 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -75,19 +75,19 @@
 
 		pb18 {
 			label = "pb18";
-			gpios = <&pioB 18 1>;
+			gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		pd21 {
 			label = "pd21";
-			gpios = <&pioD 21 0>;
+			gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	1wire_cm {
 		compatible = "w1-gpio";
-		gpios = <&pioB 18 0>;
+		gpios = <&pioB 18 GPIO_ACTIVE_HIGH>;
 		linux,open-drain;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_1wire_cm>;
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 24781f2..95f88c7 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -27,7 +27,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 15 0>;
+					cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -40,7 +40,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 14 0>;
+					cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -86,8 +86,8 @@
 		usb0: ohci at 00600000 {
 			status = "okay";
 			num-ports = <2>;
-			atmel,vbus-gpio = <&pioD 19 1
-					   &pioD 20 1
+			atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW
+					   &pioD 20 GPIO_ACTIVE_LOW
 					  >;
 		};
 
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 2067c66..143b6d2 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -40,7 +40,7 @@
 			};
 
 			usb1: gadget at fffa4000 {
-				atmel,vbus-gpio = <&pioC 5 0>;
+				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 		};
@@ -52,7 +52,7 @@
 			status = "okay";
 
 			gpios = <0
-				 &pioC 14 0
+				 &pioC 14 GPIO_ACTIVE_HIGH
 				 0
 				>;
 
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index eae2cd7..4d82968 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -31,7 +31,7 @@
 			};
 
 			usb1: gadget at fffa4000 {
-				atmel,vbus-gpio = <&pioC 5 0>;
+				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index 8328fed..02df191 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -94,26 +94,26 @@
 
 		led1g {
 			label = "led1:green";
-			gpios = <&pioB 0 1>;
+			gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 		};
 
 		led1r {
 			label = "led1:red";
-			gpios = <&pioB 1 1>;
+			gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 		};
 
 		led2g {
 			label = "led2:green";
-			gpios = <&pioB 2 1>;
+			gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 			default-state = "on";
 		};
 
 		led2r {
 			label = "led2:red";
-			gpios = <&pioB 3 1>;
+			gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "none";
 		};
 	};
@@ -125,14 +125,14 @@
 
 		reset {
 			label = "reset";
-			gpios = <&pioB 30 1>;
+			gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
 			linux,code = <0x100>;
 			gpio-key,wakeup;
 		};
 
 		mode {
 			label = "mode";
-			gpios = <&pioB 31 1>;
+			gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
 			linux,code = <0x101>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index f1b54a2..ccf9ea2 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -62,7 +62,7 @@
 
 		monitor_mute {
 			label = "Monitor mute";
-			gpios = <&pioC 1 1>;
+			gpios = <&pioC 1 GPIO_ACTIVE_LOW>;
 			linux,code = <113>;
 		};
 	};
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 639410b..315d927 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -64,7 +64,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 6 0>;
+					cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -81,8 +81,8 @@
 			nand-on-flash-bbt;
 			pinctrl-0 = <&pinctrl_board_nand>;
 
-			gpios = <&pioD 3 0
-				 &pioC 14 0
+			gpios = <&pioD 3 GPIO_ACTIVE_HIGH
+				 &pioC 14 GPIO_ACTIVE_HIGH
 				 0
 				>;
 
@@ -134,13 +134,13 @@
 
 		led0 {
 			label = "led0";
-			gpios = <&pioD 0 1>;
+			gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "nand-disk";
 		};
 
 		led1 {
 			label = "led1";
-			gpios = <&pioD 31 0>;
+			gpios = <&pioD 31 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
@@ -152,13 +152,13 @@
 
 		right {
 			label = "SW4";
-			gpios = <&pioE 7 1>;
+			gpios = <&pioE 7 GPIO_ACTIVE_LOW>;
 			linux,code = <106>;
 		};
 
 		up {
 			label = "SW3";
-			gpios = <&pioE 8 1>;
+			gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
 			linux,code = <103>;
 		};
 	};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2293fa1..0d65e3d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel SAMA5D3 family SoC";
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 5bffd66..027bac7 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -41,7 +41,7 @@
 	leds {
 		d3 {
 			label = "d3";
-			gpios = <&pioE 24 0>;
+			gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index d88ff72..fb8ee11 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -51,7 +51,7 @@
 	leds {
 		d3 {
 			label = "d3";
-			gpios = <&pioE 24 0>;
+			gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 3c364d2..509a53d 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -48,7 +48,7 @@
 
 		pb_user1 {
 			label = "pb_user1";
-			gpios = <&pioE 27 0>;
+			gpios = <&pioE 27 GPIO_ACTIVE_HIGH>;
 			linux,code = <0x100>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b552917..60637e4 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -85,7 +85,7 @@
 
 		d2 {
 			label = "d2";
-			gpios = <&pioE 25 1>;	/* PE25, conflicts with A25, RXD2 */
+			gpios = <&pioE 25 GPIO_ACTIVE_LOW>;	/* PE25, conflicts with A25, RXD2 */
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index a5e7131..205e64c 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -20,7 +20,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 17 0>;
+					cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -62,7 +62,7 @@
 				slot at 0 {
 					reg = <0>;
 					bus-width = <4>;
-					cd-gpios = <&pioD 18 0>;
+					cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>;
 				};
 			};
 
@@ -127,7 +127,7 @@
 		};
 
 		usb0: gadget at 00500000 {
-			atmel,vbus-gpio = <&pioD 29 0>;
+			atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usba_vbus>;
 			status = "okay";
@@ -135,9 +135,9 @@
 
 		usb1: ohci at 00600000 {
 			num-ports = <3>;
-			atmel,vbus-gpio = <&pioD 25 0
-					   &pioD 26 1
-					   &pioD 27 1
+			atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH
+					   &pioD 26 GPIO_ACTIVE_LOW
+					   &pioD 27 GPIO_ACTIVE_LOW
 					  >;
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 45f059b..0751a6a9 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -38,7 +38,7 @@
 			};
 
 			usb1: gadget at fff78000 {
-				atmel,vbus-gpio = <&pioB 11 0>;
+				atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 		};
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index e70d229..2859776 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -30,7 +30,7 @@
 			};
 
 			usb1: gadget at fffa4000 {
-				atmel,vbus-gpio = <&pioC 5 0>;
+				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 		};
@@ -93,7 +93,7 @@
 
 		user_led {
 			label = "user_led";
-			gpios = <&pioB 21 1>;
+			gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
@@ -105,7 +105,7 @@
 
 		user_pb {
 			label = "user_pb";
-			gpios = <&pioB 10 1>;
+			gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
 			linux,code = <28>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 82e204a..f8ec36c 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -43,7 +43,7 @@
 			};
 
 			usb1: gadget at fff78000 {
-				atmel,vbus-gpio = <&pioB 11 0>;
+				atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
 
@@ -107,7 +107,7 @@
 
 		user_led {
 			label = "user_led";
-			gpios = <&pioB 21 0>;
+			gpios = <&pioB 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
@@ -119,7 +119,7 @@
 
 		user_pb {
 			label = "user_pb";
-			gpios = <&pioB 10 1>;
+			gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
 			linux,code = <28>;
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
index ad3eca1..5b0ffc1 100644
--- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
+++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
@@ -28,39 +28,39 @@
 
 		user_led1 {
 			label = "user_led1";
-			gpios = <&pioB 20 1>;
+			gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
 		};
 
 /*
 * led already used by mother board but active as high
 *		user_led2 {
 *			label = "user_led2";
-*			gpios = <&pioB 21 1>;
+*			gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
 *		};
 */
 		user_led3 {
 			label = "user_led3";
-			gpios = <&pioB 22 1>;
+			gpios = <&pioB 22 GPIO_ACTIVE_LOW>;
 		};
 
 		user_led4 {
 			label = "user_led4";
-			gpios = <&pioB 23 1>;
+			gpios = <&pioB 23 GPIO_ACTIVE_LOW>;
 		};
 
 		red {
 			label = "red";
-			gpios = <&pioB 24 1>;
+			gpios = <&pioB 24 GPIO_ACTIVE_LOW>;
 		};
 
 		orange {
 			label = "orange";
-			gpios = <&pioB 30 1>;
+			gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
 		};
 
 		green {
 			label = "green";
-			gpios = <&pioB 31 1>;
+			gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
 		};
 	};
 
@@ -71,25 +71,25 @@
 
 		user_pb1 {
 			label = "user_pb1";
-			gpios = <&pioB 25 1>;
+			gpios = <&pioB 25 GPIO_ACTIVE_LOW>;
 			linux,code = <0x100>;
 		};
 
 		user_pb2 {
 			label = "user_pb2";
-			gpios = <&pioB 13 1>;
+			gpios = <&pioB 13 GPIO_ACTIVE_LOW>;
 			linux,code = <0x101>;
 		};
 
 		user_pb3 {
 			label = "user_pb3";
-			gpios = <&pioA 26 1>;
+			gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
 			linux,code = <0x102>;
 		};
 
 		user_pb4 {
 			label = "user_pb4";
-			gpios = <&pioC 9 1>;
+			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
 			linux,code = <0x103>;
 		};
 	};
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Wed May 15 10:03:05 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:03:05 +0200
Subject: [PATCH 5/5] ARM: at91: dt: switch to standard IRQ flag defines
In-Reply-To: <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130515135821.GG22508@game.jcrosoft.org>
 <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368626585-24425-5-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91rm9200.dtsi  |   45 +++++++++++---------
 arch/arm/boot/dts/at91sam9260.dtsi |   49 ++++++++++++----------
 arch/arm/boot/dts/at91sam9263.dtsi |   43 ++++++++++----------
 arch/arm/boot/dts/at91sam9g45.dtsi |   49 +++++++++++-----------
 arch/arm/boot/dts/at91sam9n12.dtsi |   41 ++++++++++---------
 arch/arm/boot/dts/at91sam9x5.dtsi  |   55 +++++++++++++------------
 arch/arm/boot/dts/sama5d3.dtsi     |   79 ++++++++++++++++++------------------
 7 files changed, 188 insertions(+), 173 deletions(-)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 361a957..4aad0d9 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -12,6 +12,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -79,25 +80,29 @@
 			st: timer at fffffd00 {
 				compatible = "atmel,at91rm9200-st";
 				reg = <0xfffffd00 0x100>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at fffa0000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffa0000 0x100>;
-				interrupts = <17 4 0 18 4 0 19 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+					      18 IRQ_TYPE_LEVEL_HIGH 0
+					      19 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at fffa4000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffa4000 0x100>;
-				interrupts = <20 4 0 21 4 0 22 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
+					      21 IRQ_TYPE_LEVEL_HIGH 0
+					      22 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			i2c0: i2c at fffb8000 {
 				compatible = "atmel,at91rm9200-i2c";
 				reg = <0xfffb8000 0x4000>;
-				interrupts = <12 4 6>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_twi>;
 				#address-cells = <1>;
@@ -108,7 +113,7 @@
 			mmc0: mmc at fffb4000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfffb4000 0x4000>;
-				interrupts = <10 4 0>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -117,7 +122,7 @@
 			ssc0: ssc at fffd0000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffd0000 0x4000>;
-				interrupts = <14 4 5>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disable";
@@ -126,7 +131,7 @@
 			ssc1: ssc at fffd4000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffd4000 0x4000>;
-				interrupts = <15 4 5>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disable";
@@ -135,7 +140,7 @@
 			ssc2: ssc at fffd8000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffd8000 0x4000>;
-				interrupts = <16 4 5>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
 				status = "disable";
@@ -144,7 +149,7 @@
 			macb0: ethernet at fffbc000 {
 				compatible = "cdns,at91rm9200-emac", "cdns,emac";
 				reg = <0xfffbc000 0x4000>;
-				interrupts = <24 4 3>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				phy-mode = "rmii";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
@@ -396,7 +401,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -406,7 +411,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -416,7 +421,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -426,7 +431,7 @@
 				pioD: gpio at fffffa00 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <5 4 1>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -437,7 +442,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -446,7 +451,7 @@
 			usart0: serial at fffc0000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffc0000 0x200>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -457,7 +462,7 @@
 			usart1: serial at fffc4000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffc4000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -468,7 +473,7 @@
 			usart2: serial at fffc8000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffc8000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -479,7 +484,7 @@
 			usart3: serial at fffcc000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffcc000 0x200>;
-				interrupts = <23 4 5>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -490,7 +495,7 @@
 			usb1: gadget at fffb0000 {
 				compatible = "atmel,at91rm9200-udc";
 				reg = <0xfffb0000 0x4000>;
-				interrupts = <11 4 2>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
 				status = "disabled";
 			};
 		};
@@ -515,7 +520,7 @@
 		usb0: ohci at 00300000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00300000 0x100000>;
-			interrupts = <23 4 2>;
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7edadf3..a776f50 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -10,6 +10,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -86,19 +87,23 @@
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at fffa0000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffa0000 0x100>;
-				interrupts = <17 4 0 18 4 0 19 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+					      18 IRQ_TYPE_LEVEL_HIGH 0
+					      19 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at fffdc000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffdc000 0x100>;
-				interrupts = <26 4 0 27 4 0 28 4 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+					      27 IRQ_TYPE_LEVEL_HIGH 0
+					      28 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			pinctrl at fffff400 {
@@ -345,7 +350,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -355,7 +360,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -365,7 +370,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -376,7 +381,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -385,7 +390,7 @@
 			usart0: serial at fffb0000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffb0000 0x200>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -396,7 +401,7 @@
 			usart1: serial at fffb4000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffb4000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -407,7 +412,7 @@
 			usart2: serial at fffb8000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffb8000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -418,7 +423,7 @@
 			usart3: serial at fffd0000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffd0000 0x200>;
-				interrupts = <23 4 5>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -429,7 +434,7 @@
 			uart0: serial at fffd4000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffd4000 0x200>;
-				interrupts = <24 4 5>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -440,7 +445,7 @@
 			uart1: serial at fffd8000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffd8000 0x200>;
-				interrupts = <25 4 5>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -451,7 +456,7 @@
 			macb0: ethernet at fffc4000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xfffc4000 0x100>;
-				interrupts = <21 4 3>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
 				status = "disabled";
@@ -460,14 +465,14 @@
 			usb1: gadget at fffa4000 {
 				compatible = "atmel,at91rm9200-udc";
 				reg = <0xfffa4000 0x4000>;
-				interrupts = <10 4 2>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
 				status = "disabled";
 			};
 
 			i2c0: i2c at fffac000 {
 				compatible = "atmel,at91sam9260-i2c";
 				reg = <0xfffac000 0x100>;
-				interrupts = <11 4 6>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -476,7 +481,7 @@
 			mmc0: mmc at fffa8000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfffa8000 0x600>;
-				interrupts = <9 4 0>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -485,7 +490,7 @@
 			ssc0: ssc at fffbc000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffbc000 0x4000>;
-				interrupts = <14 4 5>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -496,7 +501,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffc8000 0x200>;
-				interrupts = <12 4 3>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -507,7 +512,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffcc000 0x200>;
-				interrupts = <13 4 3>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -516,7 +521,7 @@
 			adc0: adc at fffe0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
-				interrupts = <5 4 0>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
 				atmel,adc-use-external-triggers;
 				atmel,adc-channels-used = <0xf>;
 				atmel,adc-vref = <3300>;
@@ -579,7 +584,7 @@
 		usb0: ohci at 00500000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00500000 0x100000>;
-			interrupts = <20 4 2>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index bb4d7ca..d9cf51a 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -8,6 +8,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -74,13 +75,13 @@
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at fff7c000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfff7c000 0x100>;
-				interrupts = <19 4 0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			rstc at fffffd00 {
@@ -326,7 +327,7 @@
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -336,7 +337,7 @@
 				pioB: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -346,7 +347,7 @@
 				pioC: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -356,7 +357,7 @@
 				pioD: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -366,7 +367,7 @@
 				pioE: gpio at fffffa00 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -377,7 +378,7 @@
 			dbgu: serial at ffffee00 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -386,7 +387,7 @@
 			usart0: serial at fff8c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff8c000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -397,7 +398,7 @@
 			usart1: serial at fff90000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff90000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -408,7 +409,7 @@
 			usart2: serial at fff94000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff94000 0x200>;
-				interrupts = <9 4 5>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -419,7 +420,7 @@
 			ssc0: ssc at fff98000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfff98000 0x4000>;
-				interrupts = <16 4 5>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -428,7 +429,7 @@
 			ssc1: ssc at fff9c000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfff9c000 0x4000>;
-				interrupts = <17 4 5>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disabled";
@@ -437,7 +438,7 @@
 			macb0: ethernet at fffbc000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xfffbc000 0x100>;
-				interrupts = <21 4 3>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
 				status = "disabled";
@@ -446,14 +447,14 @@
 			usb1: gadget at fff78000 {
 				compatible = "atmel,at91rm9200-udc";
 				reg = <0xfff78000 0x4000>;
-				interrupts = <24 4 2>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
 				status = "disabled";
 			};
 
 			i2c0: i2c at fff88000 {
 				compatible = "atmel,at91sam9263-i2c";
 				reg = <0xfff88000 0x100>;
-				interrupts = <13 4 6>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -462,7 +463,7 @@
 			mmc0: mmc at fff80000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfff80000 0x600>;
-				interrupts = <10 4 0>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -471,7 +472,7 @@
 			mmc1: mmc at fff84000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfff84000 0x600>;
-				interrupts = <11 4 0>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -488,7 +489,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa4000 0x200>;
-				interrupts = <14 4 3>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -499,7 +500,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa8000 0x200>;
-				interrupts = <15 4 3>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -527,7 +528,7 @@
 		usb0: ohci at 00a00000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00a00000 0x100000>;
-			interrupts = <29 4 2>;
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 8ba4c71..f0091af 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -11,6 +11,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -85,7 +86,7 @@
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 
@@ -97,19 +98,19 @@
 			tcb0: timer at fff7c000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfff7c000 0x100>;
-				interrupts = <18 4 0>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at fffd4000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffd4000 0x100>;
-				interrupts = <18 4 0>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
-				interrupts = <21 4 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -346,7 +347,7 @@
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -356,7 +357,7 @@
 				pioB: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -366,7 +367,7 @@
 				pioC: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -376,7 +377,7 @@
 				pioD: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <5 4 1>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -386,7 +387,7 @@
 				pioE: gpio at fffffa00 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <5 4 1>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -397,7 +398,7 @@
 			dbgu: serial at ffffee00 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -406,7 +407,7 @@
 			usart0: serial at fff8c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff8c000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -417,7 +418,7 @@
 			usart1: serial at fff90000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff90000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -428,7 +429,7 @@
 			usart2: serial at fff94000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff94000 0x200>;
-				interrupts = <9 4 5>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -439,7 +440,7 @@
 			usart3: serial at fff98000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff98000 0x200>;
-				interrupts = <10 4 5>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -450,7 +451,7 @@
 			macb0: ethernet at fffbc000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xfffbc000 0x100>;
-				interrupts = <25 4 3>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
 				status = "disabled";
@@ -459,7 +460,7 @@
 			i2c0: i2c at fff84000 {
 				compatible = "atmel,at91sam9g10-i2c";
 				reg = <0xfff84000 0x100>;
-				interrupts = <12 4 6>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -468,7 +469,7 @@
 			i2c1: i2c at fff88000 {
 				compatible = "atmel,at91sam9g10-i2c";
 				reg = <0xfff88000 0x100>;
-				interrupts = <13 4 6>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -477,7 +478,7 @@
 			ssc0: ssc at fff9c000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xfff9c000 0x4000>;
-				interrupts = <16 4 5>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -486,7 +487,7 @@
 			ssc1: ssc at fffa0000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xfffa0000 0x4000>;
-				interrupts = <17 4 5>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disabled";
@@ -495,7 +496,7 @@
 			adc0: adc at fffb0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffb0000 0x100>;
-				interrupts = <20 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
 				atmel,adc-use-external-triggers;
 				atmel,adc-channels-used = <0xff>;
 				atmel,adc-vref = <3300>;
@@ -535,7 +536,7 @@
 			mmc0: mmc at fff80000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfff80000 0x600>;
-				interrupts = <11 4 0>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -546,7 +547,7 @@
 			mmc1: mmc at fffd0000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfffd0000 0x600>;
-				interrupts = <29 4 0>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma 1 13>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -604,14 +605,14 @@
 		usb0: ohci at 00700000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00700000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
 		usb1: ehci at 00800000 {
 			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 			reg = <0x00800000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e166e0c..566af32 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -9,6 +9,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -79,7 +80,7 @@
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			shdwc at fffffe10 {
@@ -90,7 +91,7 @@
 			mmc0: mmc at f0008000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf0008000 0x600>;
-				interrupts = <12 4 0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -101,19 +102,19 @@
 			tcb0: timer at f8008000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf8008000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at f800c000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf800c000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
-				interrupts = <20 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -287,7 +288,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -297,7 +298,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -307,7 +308,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -317,7 +318,7 @@
 				pioD: gpio at fffffa00 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -328,7 +329,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -337,7 +338,7 @@
 			ssc0: ssc at f0010000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf0010000 0x4000>;
-				interrupts = <28 4 5>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -346,7 +347,7 @@
 			usart0: serial at f801c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf801c000 0x4000>;
-				interrupts = <5 4 5>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
 				status = "disabled";
@@ -355,7 +356,7 @@
 			usart1: serial at f8020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x4000>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
 				status = "disabled";
@@ -364,7 +365,7 @@
 			usart2: serial at f8024000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x4000>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
 				status = "disabled";
@@ -373,7 +374,7 @@
 			usart3: serial at f8028000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8028000 0x4000>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart3>;
 				status = "disabled";
@@ -382,7 +383,7 @@
 			i2c0: i2c at f8010000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;
-				interrupts = <9 4 6>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma 1 13>,
 				       <&dma 1 14>;
 				dma-names = "tx", "rx";
@@ -394,7 +395,7 @@
 			i2c1: i2c at f8014000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8014000 0x100>;
-				interrupts = <10 4 6>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma 1 15>,
 				       <&dma 1 16>;
 				dma-names = "tx", "rx";
@@ -408,7 +409,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
-				interrupts = <13 4 3>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -419,7 +420,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
-				interrupts = <14 4 3>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -450,7 +451,7 @@
 		usb0: ohci at 00500000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00500000 0x00100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index cfbf923..af91599 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -11,6 +11,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -87,32 +88,32 @@
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at f8008000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf8008000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at f800c000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf800c000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma0: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
-				interrupts = <20 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
 			dma1: dma-controller at ffffee00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffee00 0x200>;
-				interrupts = <21 4 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -416,7 +417,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -426,7 +427,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					#gpio-lines = <19>;
@@ -437,7 +438,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -447,7 +448,7 @@
 				pioD: gpio at fffffa00 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					#gpio-lines = <22>;
@@ -459,7 +460,7 @@
 			ssc0: ssc at f0010000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf0010000 0x4000>;
-				interrupts = <28 4 5>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -468,7 +469,7 @@
 			mmc0: mmc at f0008000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf0008000 0x600>;
-				interrupts = <12 4 0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma0 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -479,7 +480,7 @@
 			mmc1: mmc at f000c000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf000c000 0x600>;
-				interrupts = <26 4 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -490,7 +491,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -499,7 +500,7 @@
 			usart0: serial at f801c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf801c000 0x200>;
-				interrupts = <5 4 5>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
 				status = "disabled";
@@ -508,7 +509,7 @@
 			usart1: serial at f8020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x200>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
 				status = "disabled";
@@ -517,7 +518,7 @@
 			usart2: serial at f8024000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
 				status = "disabled";
@@ -526,7 +527,7 @@
 			macb0: ethernet at f802c000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
-				interrupts = <24 4 3>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb0_rmii>;
 				status = "disabled";
@@ -535,14 +536,14 @@
 			macb1: ethernet at f8030000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xf8030000 0x100>;
-				interrupts = <27 4 3>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
 				status = "disabled";
 			};
 
 			i2c0: i2c at f8010000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;
-				interrupts = <9 4 6>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 1 7>,
 				       <&dma0 1 8>;
 				dma-names = "tx", "rx";
@@ -556,7 +557,7 @@
 			i2c1: i2c at f8014000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8014000 0x100>;
-				interrupts = <10 4 6>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma1 1 5>,
 				       <&dma1 1 6>;
 				dma-names = "tx", "rx";
@@ -570,7 +571,7 @@
 			i2c2: i2c at f8018000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8018000 0x100>;
-				interrupts = <11 4 6>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 1 9>,
 				       <&dma0 1 10>;
 				dma-names = "tx", "rx";
@@ -584,7 +585,7 @@
 			adc0: adc at f804c000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf804c000 0x100>;
-				interrupts = <19 4 0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
 				atmel,adc-use-external;
 				atmel,adc-channels-used = <0xffff>;
 				atmel,adc-vref = <3300>;
@@ -627,7 +628,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
-				interrupts = <13 4 3>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -638,7 +639,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
-				interrupts = <14 4 3>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -647,7 +648,7 @@
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x40>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				status = "disabled";
 			};
 		};
@@ -676,14 +677,14 @@
 		usb0: ohci at 00600000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00600000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
 		usb1: ehci at 00700000 {
 			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 			reg = <0x00700000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 05a3380..c00e158 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -10,6 +10,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -61,7 +62,7 @@
 			mmc0: mmc at f0000000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf0000000 0x600>;
-				interrupts = <21 4 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma0 2 0>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
@@ -76,7 +77,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91sam9x5-spi";
 				reg = <0xf0004000 0x100>;
-				interrupts = <24 4 3>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				cs-gpios = <&pioD 13 0
 					    &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
 					    &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
@@ -90,7 +91,7 @@
 			ssc0: ssc at f0008000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf0008000 0x4000>;
-				interrupts = <38 4 4>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -99,7 +100,7 @@
 			can0: can at f000c000 {
 				compatible = "atmel,at91sam9x5-can";
 				reg = <0xf000c000 0x300>;
-				interrupts = <40 4 3>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_can0_rx_tx>;
 				status = "disabled";
@@ -108,13 +109,13 @@
 			tcb0: timer at f0010000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf0010000 0x100>;
-				interrupts = <26 4 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			i2c0: i2c at f0014000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf0014000 0x4000>;
-				interrupts = <18 4 6>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 2 7>,
 				       <&dma0 2 8>;
 				dma-names = "tx", "rx";
@@ -128,7 +129,7 @@
 			i2c1: i2c at f0018000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf0018000 0x4000>;
-				interrupts = <19 4 6>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 2 9>,
 				       <&dma0 2 10>;
 				dma-names = "tx", "rx";
@@ -142,7 +143,7 @@
 			usart0: serial at f001c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf001c000 0x100>;
-				interrupts = <12 4 5>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
 				status = "disabled";
@@ -151,7 +152,7 @@
 			usart1: serial at f0020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf0020000 0x100>;
-				interrupts = <13 4 5>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
 				status = "disabled";
@@ -160,7 +161,7 @@
 			macb0: ethernet at f0028000 {
 				compatible = "cnds,pc302-gem", "cdns,gem";
 				reg = <0xf0028000 0x100>;
-				interrupts = <34 4 3>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
 				status = "disabled";
@@ -169,14 +170,14 @@
 			isi: isi at f0034000 {
 				compatible = "atmel,at91sam9g45-isi";
 				reg = <0xf0034000 0x4000>;
-				interrupts = <37 4 5>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
 				status = "disabled";
 			};
 
 			mmc1: mmc at f8000000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf8000000 0x600>;
-				interrupts = <22 4 0>;
+				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 2 0>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
@@ -189,7 +190,7 @@
 			mmc2: mmc at f8004000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf8004000 0x600>;
-				interrupts = <23 4 0>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 2 1>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
@@ -204,7 +205,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91sam9x5-spi";
 				reg = <0xf8008000 0x100>;
-				interrupts = <25 4 3>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
 				cs-gpios = <&pioC 25 0
 					    &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
 					    &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
@@ -218,7 +219,7 @@
 			ssc1: ssc at f800c000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf800c000 0x4000>;
-				interrupts = <39 4 4>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disabled";
@@ -227,7 +228,7 @@
 			can1: can at f8010000 {
 				compatible = "atmel,at91sam9x5-can";
 				reg = <0xf8010000 0x300>;
-				interrupts = <41 4 3>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_can1_rx_tx>;
 			};
@@ -235,13 +236,13 @@
 			tcb1: timer at f8014000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf8014000 0x100>;
-				interrupts = <27 4 0>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			adc0: adc at f8018000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf8018000 0x100>;
-				interrupts = <29 4 5>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <
 					&pinctrl_adc0_adtrg
@@ -295,7 +296,7 @@
 			tsadcc: tsadcc at f8018000 {
 				compatible = "atmel,at91sam9x5-tsadcc";
 				reg = <0xf8018000 0x4000>;
-				interrupts = <29 4 5>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,tsadcc_clock = <300000>;
 				atmel,filtering_average = <0x03>;
 				atmel,pendet_debounce = <0x08>;
@@ -307,7 +308,7 @@
 			i2c2: i2c at f801c000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf801c000 0x4000>;
-				interrupts = <20 4 6>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma1 2 11>,
 				       <&dma1 2 12>;
 				dma-names = "tx", "rx";
@@ -319,7 +320,7 @@
 			usart2: serial at f8020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x100>;
-				interrupts = <14 4 5>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
 				status = "disabled";
@@ -328,7 +329,7 @@
 			usart3: serial at f8024000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x100>;
-				interrupts = <15 4 5>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart3>;
 				status = "disabled";
@@ -337,7 +338,7 @@
 			macb1: ethernet at f802c000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
-				interrupts = <35 4 3>;
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb1_rmii>;
 				status = "disabled";
@@ -346,7 +347,7 @@
 			sha at f8034000 {
 				compatible = "atmel,sam9g46-sha";
 				reg = <0xf8034000 0x100>;
-				interrupts = <42 4 0>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			aes at f8038000 {
@@ -358,20 +359,20 @@
 			tdes at f803c000 {
 				compatible = "atmel,sam9g46-tdes";
 				reg = <0xf803c000 0x100>;
-				interrupts = <44 4 0>;
+				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma0: dma-controller at ffffe600 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffe600 0x200>;
-				interrupts = <30 4 0>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
 			dma1: dma-controller at ffffe800 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffe800 0x200>;
-				interrupts = <31 4 0>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -383,7 +384,7 @@
 			dbgu: serial at ffffee00 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
-				interrupts = <2 4 7>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -817,7 +818,7 @@
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x100>;
-					interrupts = <6 4 1>;
+					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -827,7 +828,7 @@
 				pioB: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x100>;
-					interrupts = <7 4 1>;
+					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -837,7 +838,7 @@
 				pioC: gpio at fffff600 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x100>;
-					interrupts = <8 4 1>;
+					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -847,7 +848,7 @@
 				pioD: gpio at fffff800 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x100>;
-					interrupts = <9 4 1>;
+					interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -857,7 +858,7 @@
 				pioE: gpio at fffffa00 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x100>;
-					interrupts = <10 4 1>;
+					interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -878,7 +879,7 @@
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
-				interrupts = <3 4 5>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
 			};
 
 			watchdog at fffffe40 {
@@ -890,7 +891,7 @@
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x30>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 		};
 
@@ -900,7 +901,7 @@
 			compatible = "atmel,at91sam9rl-udc";
 			reg = <0x00500000 0x100000
 			       0xf8030000 0x4000>;
-			interrupts = <33 4 2>;
+			interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 
 			ep0 {
@@ -1012,14 +1013,14 @@
 		usb1: ohci at 00600000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00600000 0x100000>;
-			interrupts = <32 4 2>;
+			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
 		usb2: ehci at 00700000 {
 			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 			reg = <0x00700000 0x100000>;
-			interrupts = <32 4 2>;
+			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
@@ -1035,7 +1036,7 @@
 				0xffffc000 0x00000070	/* NFC HSMC regs */
 				0x00200000 0x00100000	/* NFC SRAM banks */
 				>;
-			interrupts = <5 4 6>;
+			interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
-- 
1.7.10.4



From arnd at arndb.de  Wed May 15 10:07:54 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 16:07:54 +0200
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <1368332581-94691-4-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-4-git-send-email-dt.tangr@gmail.com>
Message-ID: <201305151607.54442.arnd@arndb.de>

On Sunday 12 May 2013, Daniel Tang wrote:
> 
> Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
> ---
>  drivers/clk/Makefile     |   1 +
>  drivers/clk/clk-nspire.c | 141 +++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 142 insertions(+)
>  create mode 100644 drivers/clk/clk-nspire.c

You are missing a binding in Documentation/devicetree, same as for some of
the other drivers in this series.

> +static int nspire_clk_read(struct device_node *node,
> +		struct nspire_clk_info *clk)
> +{
> +	u32 val;
> +	int ret;
> +	void __iomem *io;
> +	const char *type = NULL;
> +
> +	ret = of_property_read_string(node, "io-type", &type);
> +	if (ret)
> +		return ret;

Using a string here feels clumsy. Why not use the "compatible" property
to distinguish the different models?

> +static void __init nspire_ahbdiv_setup(struct device_node *node)
> +{
> +	int ret;
> +	struct clk *clk;
> +	const char *clk_name = node->name;
> +	const char *parent_name;
> +	struct nspire_clk_info info;
> +
> +	ret = nspire_clk_read(node, &info);
> +	if (WARN_ON(ret))
> +		return;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);

It seems strange to assign the clk_name variable to node->name
first and then overriding it with the clock-output-names property.
Is that intentional? If so, please explain it in a comment.

> +
> +	pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n",
> +		info.base_clock / MHZ,
> +		info.base_clock / info.base_cpu_ratio / MHZ,
> +		info.base_clock / info.base_ahb_ratio / MHZ);
> +}
> +
> +CLK_OF_DECLARE(nspire_clk, "nspire-clock", nspire_clk_setup);
> +CLK_OF_DECLARE(nspire_ahbdiv, "nspire-ahb-divider", nspire_ahbdiv_setup);

I would put each of these lines directly under the function it references.

	Arnd


From jrudholm at gmail.com  Wed May 15 10:10:09 2013
From: jrudholm at gmail.com (Johan Rudholm)
Date: Wed, 15 May 2013 16:10:09 +0200
Subject: [PATCH 0/4] mmc: mmci: Add support for UHS cards
In-Reply-To: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
References: <1368610823-14113-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CA+20K0DP1xY1urAsxBFWcaN22AahJ3GVG2dxhACFArfwuZFDZw@mail.gmail.com>

Hi,

2013/5/15 Ulf Hansson <ulf.hansson at stericsson.com>:
> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> UHS cards in mode SDR12|25 operates at 1.8V I/O voltage. This patchset
> adds support to handle the corresponding voltage switch from the default
> 2.7-3.6 I/O voltage to 1.8V.
>
> The first patch, "Fixup regulator handling for vqmmc" has recently been
> sent as a separate patch, since it is a pure bugfix. Nevertheless this
> patchset depends on this patch, thus I decided to fold it here as well.
>
> Host capabilities for SDR12 and SDR25 needs to be set to enable support,
> but that will be handled outside this patchset.
>
> Ulf Hansson (4):
>   mmc: mmci: Fixup regulator handling for vqmmc
>   mmc: mmci: Support signal voltage switch for UHS cards
>   mmc: mmci: Cache MMCIDATACTRL register
>   mmc: mmci: Add card_busy function to improve UHS card support
>
>  drivers/mmc/host/mmci.c |   94 +++++++++++++++++++++++++++++++++++++++++++----
>  drivers/mmc/host/mmci.h |    4 ++
>  2 files changed, 90 insertions(+), 8 deletions(-)

Looks good! Please add my

Reviewed-by: Johan Rudholm <jrudholm at gmail.com>

to this patch set.

Kind regards, Johan


From arnd at arndb.de  Wed May 15 10:10:22 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 16:10:22 +0200
Subject: [RFC PATCHv3 2/6] arm: Add device trees for TI-Nspire
In-Reply-To: <1368332581-94691-3-git-send-email-dt.tangr@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-3-git-send-email-dt.tangr@gmail.com>
Message-ID: <201305151610.23145.arnd@arndb.de>

On Sunday 12 May 2013, Daniel Tang wrote:
> +
> +                       timer0: timer at 900C0000 {
> +                               reg = <0x900C0000 0x1000>;
> +
> +                               clocks = <&timer_clk>;
> +                               clock-names = "timer_clk";
> +                       };
> +
> +                       timer1: timer at 900D0000 {
> +                               reg = <0x900D0000 0x1000>;
> +                               interrupts = <19>;
> +
> +                               clocks = <&timer_clk>;
> +                               clock-names = "timer_clk";
> +                       };


> +                               clocks = <&apb_pclk>;
> +                               clock-names = "apb_pclk";
> +                       };

Why do you provide "clock-names" here? Do those devices have multiple
clock inputs? It's normally easier to just use the default clock
input.

	Arnd


From arnd at arndb.de  Wed May 15 10:15:39 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 16:15:39 +0200
Subject: [PATCHv2] arm: mm: Use phys_addr_t properly for ioremap functions
In-Reply-To: <1368560031-19367-1-git-send-email-lauraa@codeaurora.org>
References: <1368560031-19367-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <201305151615.39752.arnd@arndb.de>

On Tuesday 14 May 2013, Laura Abbott wrote:
> Several of the ioremap functions use unsigned long in places
> resulting in truncation if physical addresses greater than
> 4G are passed in. Change the types of the functions and the
> callers accordingly.

Looks good to me. I wonder a bit whether resource_size_t or phys_addr_t
is the right type here, but they are always defined to the same type
these days.

FWIW, x86 and tile use resource_size_t, while a couple of other architectures
use phys_addr_t.

	Arnd


From plagnioj at jcrosoft.com  Wed May 15 10:13:56 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:13:56 +0200
Subject: Fwd: Tegra 30 System hangs because of commit "pinctrl: move
 subsystem mutex to pinctrl_dev struct"
In-Reply-To: <5192A0E4.2070202@gmail.com>
References: <CACRpkdZdT8==cUtH4=Y3LC-eVu6ntO2ojFC4bSXNuxa4hMJ=ZA@mail.gmail.com>
 <20130505202236.GF24282@game.jcrosoft.org>
 <CACRpkda2EG0O-pfZQ5kLFX=cwSmUSVBJkR7Xvye3ROs3tstv9w@mail.gmail.com>
 <20130506194122.GG24282@game.jcrosoft.org>
 <20130506195403.GJ18614@n2100.arm.linux.org.uk>
 <CACRpkdZtPhzLFicYYZF0SZfp4dMJars+Z-7hTUZQ1JjPExXW3A@mail.gmail.com>
 <CACxGe6uo60OwRd7buPX4382_vE48MLWJYyB_ka+iS2FfVCa8mw@mail.gmail.com>
 <CAOesGMiqrXSPdEtUzGCuAuhdE4K7FVe65zMM962XuOrO555hnQ@mail.gmail.com>
 <CAGNsrLDw0_yX9nkLYDg0e8-551P7r43UxziTp1TXyyxdiKR5nA@mail.gmail.com>
 <5192A0E4.2070202@gmail.com>
Message-ID: <20130515141356.GH22508@game.jcrosoft.org>

On 15:39 Tue 14 May     , Rob Herring wrote:
> On 05/09/2013 12:51 PM, Fathi Boudra wrote:
> > On 9 May 2013 19:13, Olof Johansson <olof at lixom.net> wrote:
> >> On Thu, May 9, 2013 at 6:25 AM, Grant Likely <grant.likely at secretlab.ca> wrote:
> >>> On Mon, May 6, 2013 at 9:12 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> >>>> On Mon, May 6, 2013 at 9:54 PM, Russell King - ARM Linux
> >> Yes, a builder is quite useful. Several of us do our own builds as well.
> >>
> >> When it comes to boot coverage, I'm not sure how successful a central
> >> approach would be. It's something where I think Linaro could
> >> contribute a lot for their member platforms, but I haven't seen much
> >> engagement there yet.
> > 
> > My previous post was lost. Sorry to repost..
> > 
> > We've got a jenkins instance doing daily builds on various trees and
> > boot testing on the few boards we've got in the lab:
> > https://ci.linaro.org/jenkins/view/kernel-ci/
> > 
> > But it hasn't attracted much interest so far... It's been here since a year.
> 
> Perhaps because there is no useful information there that I can find.
> Where does it say what failed in the build? I see no artifacts or useful
> console output.
> 
> It seems it was designed with Linaro's needs in mind and not kernel
> maintainers' needs.

I was discussing with Fabo and Get in mind to create a Jenkins on kernel.org
for on our needs (maintainer's)

That will allow any one to add more hw for boot testing

Best Regards,
J.
> 
> Rob
> 
> > 
> >> Beyond there, I'd say the expectation is that each maintainer should
> >> keep an eye on their own platforms. They _should_ try building and
> >> booting linux-next on their platforms, to catch regressions early. And
> >> definitely around now, I'd like to see people boot mainline on their
> >> platforms to make sure we haven't added any severe regressions in the
> >> 3.10 merge window, etc. Some people are really good at this, others
> >> less so.
> >>
> >> What's the old saying, you can lead a horse to water but you can't
> >> make him drink? You can build a boot test cluster but you can't make
> >> anyone pay attention to it. :(
> >>
> >> -Olof
> > 
> > Cheers,
> > 
> > Fathi
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> 


From arnd at arndb.de  Wed May 15 10:20:56 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 16:20:56 +0200
Subject: [PATCH] arm: prima2: use of_platform_populate instead of
 of_platform_bus_probe
In-Reply-To: <1368523923-27137-1-git-send-email-Baohua.Song@csr.com>
References: <1368523923-27137-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <201305151620.56677.arnd@arndb.de>

On Tuesday 14 May 2013, Barry Song wrote:
> 
> use of_platform_populate to populate platform devices, it is suitable
> for creating devices which are children of the root node, then makes
> things like pcm work.
> 
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> Signed-off-by: Rongjun Ying <Rongjun.Ying at csr.com>

With 3.10-rc1 and above, you can just remove the sirfsoc_mach_init
function entirely for the same effect.

	Arnd


From plagnioj at jcrosoft.com  Wed May 15 10:19:06 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:19:06 +0200
Subject: [PATCH 0/5 v2] ARM: at91: dt: switch to pre-processor
Message-ID: <20130515141906.GI22508@game.jcrosoft.org>

HI,

	v2:
	 use common IRQ define
	 split patch
	 rebase on 3.10-rc1

        The follow patch series switch the at91 to DT pre-processor

        So we can use macro for AIC and Pinctrl instead of magic

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git j/for-3.11-dt

for you to fetch changes up to 3668ac6a70bc5af71a947ad7b531c57b8a787ea0:

  ARM: at91: dt: switch to standard IRQ flag defines (2013-05-15 21:56:18 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (5):
      ARM: at91: dt: use #include for all device trees
      ARM: at91: dt: switch to standard GPIO flag defines.
      ARM: at91: dt: add pinctrl pre-processor define
      ARM: at91: dt: switch to pinctrl to pre-processor
      ARM: at91: dt: switch to standard IRQ flag defines

 arch/arm/boot/dts/aks-cdu.dts               |   12 +--
 arch/arm/boot/dts/animeo_ip.dts             |   18 ++---
 arch/arm/boot/dts/at91-ariag25.dts          |    6 +-
 arch/arm/boot/dts/at91rm9200.dtsi           |  207 +++++++++++++++++++++++++------------------------
 arch/arm/boot/dts/at91rm9200ek.dts          |   10 +--
 arch/arm/boot/dts/at91sam9260.dtsi          |  215 ++++++++++++++++++++++++++-------------------------
 arch/arm/boot/dts/at91sam9263.dtsi          |  203 ++++++++++++++++++++++++------------------------
 arch/arm/boot/dts/at91sam9263ek.dts         |   24 +++---
 arch/arm/boot/dts/at91sam9g15.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g15ek.dts         |    4 +-
 arch/arm/boot/dts/at91sam9g20.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g20ek.dts         |    6 +-
 arch/arm/boot/dts/at91sam9g20ek_2mmc.dts    |   10 +--
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   28 ++++---
 arch/arm/boot/dts/at91sam9g25.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g25ek.dts         |    4 +-
 arch/arm/boot/dts/at91sam9g35.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9g35ek.dts         |    4 +-
 arch/arm/boot/dts/at91sam9g45.dtsi          |  213 +++++++++++++++++++++++++-------------------------
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |   38 ++++-----
 arch/arm/boot/dts/at91sam9n12.dtsi          |  141 +++++++++++++++++-----------------
 arch/arm/boot/dts/at91sam9n12ek.dts         |   14 ++--
 arch/arm/boot/dts/at91sam9x25.dtsi          |   22 +++---
 arch/arm/boot/dts/at91sam9x25ek.dts         |    4 +-
 arch/arm/boot/dts/at91sam9x35.dtsi          |    2 +-
 arch/arm/boot/dts/at91sam9x35ek.dts         |    4 +-
 arch/arm/boot/dts/at91sam9x5.dtsi           |  279 +++++++++++++++++++++++++++++++++---------------------------------
 arch/arm/boot/dts/at91sam9x5cm.dtsi         |    8 +-
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |   14 ++--
 arch/arm/boot/dts/ethernut5.dts             |    6 +-
 arch/arm/boot/dts/evk-pro3.dts              |    6 +-
 arch/arm/boot/dts/ge863-pro3.dtsi           |    2 +-
 arch/arm/boot/dts/kizbox.dts                |   16 ++--
 arch/arm/boot/dts/mpa1600.dts               |    4 +-
 arch/arm/boot/dts/pm9g45.dts                |   22 +++---
 arch/arm/boot/dts/sama5d3.dtsi              |  520 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------
 arch/arm/boot/dts/sama5d31ek.dts            |    6 +-
 arch/arm/boot/dts/sama5d33ek.dts            |    4 +-
 arch/arm/boot/dts/sama5d34ek.dts            |    6 +-
 arch/arm/boot/dts/sama5d35ek.dts            |    4 +-
 arch/arm/boot/dts/sama5d3xcm.dtsi           |    4 +-
 arch/arm/boot/dts/sama5d3xdm.dtsi           |    2 +-
 arch/arm/boot/dts/sama5d3xmb.dtsi           |   26 +++----
 arch/arm/boot/dts/tny_a9260.dts             |    4 +-
 arch/arm/boot/dts/tny_a9263.dts             |    4 +-
 arch/arm/boot/dts/tny_a9g20.dts             |    4 +-
 arch/arm/boot/dts/usb_a9260.dts             |    4 +-
 arch/arm/boot/dts/usb_a9260_common.dtsi     |    6 +-
 arch/arm/boot/dts/usb_a9263.dts             |    8 +-
 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi    |   22 +++---
 arch/arm/boot/dts/usb_a9g20.dts             |    4 +-
 include/dt-bindings/pinctrl/at91.h          |   35 +++++++++
 52 files changed, 1139 insertions(+), 1078 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/at91.h

Best Regards,
J.


From lorenzo.pieralisi at arm.com  Wed May 15 10:24:42 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Wed, 15 May 2013 15:24:42 +0100
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <alpine.LFD.2.03.1305141820280.31158@syhkavp.arg>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
 <20130514130005.GD29592@e102654-lin.cambridge.arm.com>
 <alpine.LFD.2.03.1305141820280.31158@syhkavp.arg>
Message-ID: <20130515142441.GA385@e102568-lin.cambridge.arm.com>

On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
> On Tue, 14 May 2013, Javi Merino wrote:
> 
> > On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> > 
> > > +static inline void init_cpu_port(struct cpu_port *port, u32 index, u32 mpidr)
> > 
> > The mpidr should be u64.
> 
> Why?

Since on arm64 MPIDR_EL1 size is 64 bits, we need the driver to work on
both arm and arm64.

Lorenzo



From balbi at ti.com  Wed May 15 10:35:25 2013
From: balbi at ti.com (Felipe Balbi)
Date: Wed, 15 May 2013 17:35:25 +0300
Subject: [V9 PATCH 00/12] mv-usb phy driver
In-Reply-To: <CADApbeg33WqVqG1o9Dp34t_Riia5HNg4xhz+Tk3MDPoVwxb3Mg@mail.gmail.com>
References: <1365330586-649-1-git-send-email-chao.xie@marvell.com>
 <CADApbeg4BSUubbTw8tC-fuQ06JrRtAW9+rOdg=3rP_0Dr=LwkQ@mail.gmail.com>
 <CADApbeg33WqVqG1o9Dp34t_Riia5HNg4xhz+Tk3MDPoVwxb3Mg@mail.gmail.com>
Message-ID: <20130515143525.GF26183@arwen.pp.htv.fi>

Hi,

On Wed, Apr 17, 2013 at 09:22:36AM +0800, Chao Xie wrote:
> On Wed, Apr 17, 2013 at 9:17 AM, Chao Xie <xiechao.mail at gmail.com> wrote:
> >
> > On Sun, Apr 7, 2013 at 6:29 PM, Chao Xie <chao.xie at marvell.com> wrote:
> >>
> >> The patches create the mv-usb phy driver
> >>
> >>
> >>   directly use devm_usb_get_phy_dev return value for error return.
> >>
> >> v9->v8
> >>   Remove u2o_xxx.
> >>   Add prefix for register definition
> >>   Move mutex to common PHY layer
> >>   Use module_platform_driver() to register driver
> >>   Use usleep_range to replace udelay
> >>
> >> Chao Xie (12):
> >>   usb: phy: protect phy init and shutdown for mutiple deivces
> >>   usb: phy: mv_usb2: add PHY driver for marvell usb2 controller
> >>   usb: gadget: mv_udc: use PHY driver for udc
> >>   usb: ehci: ehci-mv: use PHY driver for ehci
> >>   usb: phy: phy-mv-usb: use USB2 PHY driver for otg
> >>   usb: mv_u3d: usb phy drivers for phy operation
> >>   arm: mmp2: change the defintion of usb devices
> >>   arm: pxa910: change the defintion of usb devices
> >>   arm: ttc_dkb: modify usb support
> >>   arm: mmp: remove unused usb devices
> >>   arm: brownstone: add usb support for the board
> >>   usb: mv_usb: remove the phy callbacks in pdata
> >>
> >>  arch/arm/mach-mmp/brownstone.c          |   56 +++++
> >>  arch/arm/mach-mmp/include/mach/mmp2.h   |    4 +
> >>  arch/arm/mach-mmp/include/mach/pxa910.h |    7 +-
> >>  arch/arm/mach-mmp/mmp2.c                |    4 +
> >>  arch/arm/mach-mmp/pxa910.c              |    4 +
> >>  arch/arm/mach-mmp/ttc_dkb.c             |   39 +++-
> >>  drivers/usb/gadget/mv_u3d.h             |    3 +-
> >>  drivers/usb/gadget/mv_u3d_core.c        |   54 ++---
> >>  drivers/usb/gadget/mv_udc.h             |    2 +-
> >>  drivers/usb/gadget/mv_udc_core.c        |   50 ++---
> >>  drivers/usb/host/ehci-mv.c              |   49 ++---
> >>  drivers/usb/phy/Kconfig                 |    6 +
> >>  drivers/usb/phy/Makefile                |    1 +
> >>  drivers/usb/phy/phy-mv-usb.c            |   53 ++---
> >>  drivers/usb/phy/phy-mv-usb.h            |    2 +-
> >>  drivers/usb/phy/phy-mv-usb2.c           |  380
> >> +++++++++++++++++++++++++++++++
> >>  drivers/usb/phy/phy.c                   |    6 +
> >>  include/linux/platform_data/mv_usb.h    |    3 -
> >>  include/linux/usb/mv_usb2.h             |   29 +++
> >>  include/linux/usb/phy.h                 |   22 ++-
> >>  20 files changed, 624 insertions(+), 150 deletions(-)
> >>  create mode 100644 drivers/usb/phy/phy-mv-usb2.c
> >>  create mode 100644 include/linux/usb/mv_usb2.h
> >>
> >> --
> >> 1.7.4.1
> >>
> >>
> >
> hi, balbi
> You have given many valuable comments and suggestions for previous version.
> So i modified the driver based on your review feedback. Can you help to
> review the new version? Thanks.

sure, just give me a few more days and I'll get to these.

-- 
balbi
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From 21cnbao at gmail.com  Wed May 15 10:42:33 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 15 May 2013 22:42:33 +0800
Subject: [PATCH] arm: prima2: use of_platform_populate instead of
 of_platform_bus_probe
In-Reply-To: <201305151620.56677.arnd@arndb.de>
References: <1368523923-27137-1-git-send-email-Baohua.Song@csr.com>
 <201305151620.56677.arnd@arndb.de>
Message-ID: <CAGsJ_4znmN20pCe3yC57ysQve4V1L+euo_3X9Sbn6+z_Gx5tLQ@mail.gmail.com>

2013/5/15 Arnd Bergmann <arnd at arndb.de>:
> On Tuesday 14 May 2013, Barry Song wrote:
>>
>> use of_platform_populate to populate platform devices, it is suitable
>> for creating devices which are children of the root node, then makes
>> things like pcm work.
>>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>> Signed-off-by: Rongjun Ying <Rongjun.Ying at csr.com>
>
> With 3.10-rc1 and above, you can just remove the sirfsoc_mach_init
> function entirely for the same effect.

ok.  since kernel/setup.c does:

static int __init customize_machine(void)
{
        /*
         * customizes platform devices, or adds new ones
         * On DT based machines, we fall back to populating the
         * machine from the device tree, if no callback is provided,
         * otherwise we would always need an init_machine callback.
         */
        if (machine_desc->init_machine)
                machine_desc->init_machine();
#ifdef CONFIG_OF
        else
                of_platform_populate(NULL, of_default_bus_match_table,
                                        NULL, NULL);
#endif
        return 0;
}

>
>         Arnd

-barry


From gregory.clement at free-electrons.com  Wed May 15 10:46:20 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 15 May 2013 16:46:20 +0200
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <20130515140607.GI23869@mudshark.cambridge.arm.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
Message-ID: <51939FBC.3060705@free-electrons.com>

On 05/15/2013 04:06 PM, Will Deacon wrote:
> On Wed, May 15, 2013 at 02:54:14PM +0100, Gregory CLEMENT wrote:
>> On 05/15/2013 03:41 PM, Will Deacon wrote:
>>> Is this using dmatest.ko, or a different test program?
>>
>> No they are self-test from the mv_xor driver
> 
> Ok. And the CPU locks up, rather than the DMA master?
> 
>>> Ok, so the ALT_UP case should be emitted after patching, correct?
>>
>> Indeed it was I excepted but I didn't check (I don't know how to do)
> 
> If you don't have JTAG, that's trickier. Hopefully my other suggestion will
> help.
> 
>>>> I made some investigation. And in UP if I remove the line:
>>>> 	ALT_UP(W(nop))
>>>
>>> Did you remove the ALT_SMP case as well? You could also try making the
>>> ALT_SMP case use W(nop) too and see if it changes anything.
>>
>> OK I will try it.
> 
> You could also try deleting both of the ALT_* lines and just putting a
> W(nop) in there directly.

If I just delete the both of the ALT_* lines it no more hangs.
If I put a  W(nop) instead it hangs.

> 
>>> If you don't have both of the alternatives, things will go wrong.
>>
>> For my own culture, how ALT_UP and ALT_SMP work in SMP case?
>> When I disassembled the proc-v7.o, I saw that the SMP variant of the code were
>> written. How the kernel switch to the UP version of the code?
> 
> Early in boot (head.S:__fixup_smp), we detect whether the CPU has the MP
> extensions then, if we're actually UP but the kernel has CONFIG_SMP=y, we
> walk over the .alt.smp.init section looking at each entry in there. The
> ALT_UP macro spits out an (address, instruction) pair, so in
> __do_fixup_smp_on_up, we store the instruction to the address for each pair,
> replacing the SMP instruction which sat there in the compiled image.
> 
> It could be that the CPUID checks are failing on your Marvell part. Can you
> tell me what you have in your mpidr (mrc p15, 0, Rd, c0, c0, 5) and also
> your midr (mrc p15, 0, Rd, c0, c0) please?

mpidr= 0x0
midr= 0x561F5811

> 
> Cheers,
> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From rnayak at ti.com  Wed May 15 10:48:39 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:39 +0530
Subject: [PATCH v3 3/6] ARM: OMAP2+: hwmod-data: UART IP needs software
 control to manage sidle modes
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <1368629322-3170-4-git-send-email-rnayak@ti.com>

From: Santosh Shilimkar <santosh.shilimkar at ti.com>

OMAP UART IP needs software control for slave idle modes based on functional
state of the IP. i.e The IP slave idle settings should be set to 'noidle' when
being used and then put back to 'smart_idle' when unused. Currently this is
handled by the driver with function pointers implemented in platform code.
This however breaks in case of device tree because of missing idle handling
APIs.

Previous patches in this series added a flag HWMOD_SWSUP_SIDLE_ACTIVE which
takes care of the mentioned requirement. Hence add the flag for all UART IPs
to take advantage of feature supported by framework.

Subsequent patches removes the slave idle handling from driver code.

Tested-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    3 +++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |    6 ++++++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    4 ++++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 +++++-
 4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index c8c64b3..d05fc7b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -512,6 +512,7 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
 	.mpu_irqs	= omap2_uart1_mpu_irqs,
 	.sdma_reqs	= omap2_uart1_sdma_reqs,
 	.main_clk	= "uart1_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = CORE_MOD,
@@ -531,6 +532,7 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
 	.mpu_irqs	= omap2_uart2_mpu_irqs,
 	.sdma_reqs	= omap2_uart2_sdma_reqs,
 	.main_clk	= "uart2_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = CORE_MOD,
@@ -550,6 +552,7 @@ struct omap_hwmod omap2xxx_uart3_hwmod = {
 	.mpu_irqs	= omap2_uart3_mpu_irqs,
 	.sdma_reqs	= omap2_uart3_sdma_reqs,
 	.main_clk	= "uart3_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = CORE_MOD,
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 01d8f32..075f7cc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1995,6 +1995,7 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
 	.name		= "uart1",
 	.class		= &uart_class,
 	.clkdm_name	= "l4_wkup_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= am33xx_uart1_irqs,
 	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_wkupdm_ck",
@@ -2015,6 +2016,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
 	.name		= "uart2",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= am33xx_uart2_irqs,
 	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
@@ -2042,6 +2044,7 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
 	.name		= "uart3",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= am33xx_uart3_irqs,
 	.sdma_reqs	= uart3_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
@@ -2062,6 +2065,7 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
 	.name		= "uart4",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= am33xx_uart4_irqs,
 	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
@@ -2082,6 +2086,7 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
 	.name		= "uart5",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= am33xx_uart5_irqs,
 	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
@@ -2102,6 +2107,7 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
 	.name		= "uart6",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= am33xx_uart6_irqs,
 	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 4083606..31c7126 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -490,6 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
 	.mpu_irqs	= omap2_uart1_mpu_irqs,
 	.sdma_reqs	= omap2_uart1_sdma_reqs,
 	.main_clk	= "uart1_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = CORE_MOD,
@@ -508,6 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
 	.mpu_irqs	= omap2_uart2_mpu_irqs,
 	.sdma_reqs	= omap2_uart2_sdma_reqs,
 	.main_clk	= "uart2_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = CORE_MOD,
@@ -526,6 +528,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
 	.mpu_irqs	= omap2_uart3_mpu_irqs,
 	.sdma_reqs	= omap2_uart3_sdma_reqs,
 	.main_clk	= "uart3_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = OMAP3430_PER_MOD,
@@ -555,6 +558,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 	.mpu_irqs	= uart4_mpu_irqs,
 	.sdma_reqs	= uart4_sdma_reqs,
 	.main_clk	= "uart4_fck",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.prcm		= {
 		.omap2 = {
 			.module_offs = OMAP3430_PER_MOD,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index eaba9dc..848b6dc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3434,6 +3434,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
 	.name		= "uart1",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= omap44xx_uart1_irqs,
 	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
@@ -3462,6 +3463,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
 	.name		= "uart2",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= omap44xx_uart2_irqs,
 	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
@@ -3490,7 +3492,8 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
 	.name		= "uart3",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+				HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= omap44xx_uart3_irqs,
 	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
@@ -3519,6 +3522,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
 	.name		= "uart4",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE_ACT,
 	.mpu_irqs	= omap44xx_uart4_irqs,
 	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
-- 
1.7.9.5



From rnayak at ti.com  Wed May 15 10:48:42 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:42 +0530
Subject: [PATCH v3 6/6] ARM: OMAP2+: hwmod: Remove sysc slave idle and auto
 idle apis
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <1368629322-3170-7-git-send-email-rnayak@ti.com>

From: Santosh Shilimkar <santosh.shilimkar at ti.com>

With the OMAP serial driver sysc cleanup patches in this series, we can
now remove the hwmod external apis for sysc fiddling.

While at this, also remove unused sysc auto idle api from hwmod code.

Tested-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
Signed-off-by: Rajendra nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   68 --------------------------------------
 arch/arm/mach-omap2/omap_hwmod.h |    3 --
 2 files changed, 71 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5739429..0393142 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2255,42 +2255,6 @@ static int _idle(struct omap_hwmod *oh)
 }
 
 /**
- * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
- * @oh: struct omap_hwmod *
- * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
- *
- * Sets the IP block's OCP autoidle bit in hardware, and updates our
- * local copy. Intended to be used by drivers that require
- * direct manipulation of the AUTOIDLE bits.
- * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
- * along the return value from _set_module_autoidle().
- *
- * Any users of this function should be scrutinized carefully.
- */
-int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
-{
-	u32 v;
-	int retval = 0;
-	unsigned long flags;
-
-	if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
-		return -EINVAL;
-
-	spin_lock_irqsave(&oh->_lock, flags);
-
-	v = oh->_sysc_cache;
-
-	retval = _set_module_autoidle(oh, autoidle, &v);
-
-	if (!retval)
-		_write_sysconfig(v, oh);
-
-	spin_unlock_irqrestore(&oh->_lock, flags);
-
-	return retval;
-}
-
-/**
  * _shutdown - shutdown an omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -3189,38 +3153,6 @@ error:
 }
 
 /**
- * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
- * @oh: struct omap_hwmod *
- * @idlemode: SIDLEMODE field bits (shifted to bit 0)
- *
- * Sets the IP block's OCP slave idlemode in hardware, and updates our
- * local copy.  Intended to be used by drivers that have some erratum
- * that requires direct manipulation of the SIDLEMODE bits.  Returns
- * -EINVAL if @oh is null, or passes along the return value from
- * _set_slave_idlemode().
- *
- * XXX Does this function have any current users?  If not, we should
- * remove it; it is better to let the rest of the hwmod code handle this.
- * Any users of this function should be scrutinized carefully.
- */
-int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
-{
-	u32 v;
-	int retval = 0;
-
-	if (!oh)
-		return -EINVAL;
-
-	v = oh->_sysc_cache;
-
-	retval = _set_slave_idlemode(oh, idlemode, &v);
-	if (!retval)
-		_write_sysconfig(v, oh);
-
-	return retval;
-}
-
-/**
  * omap_hwmod_lookup - look up a registered omap_hwmod by name
  * @name: name of the omap_hwmod to look up
  *
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 8498774..0c898f5 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -645,9 +645,6 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
-int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
-int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
-
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
-- 
1.7.9.5



From rnayak at ti.com  Wed May 15 10:48:38 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:38 +0530
Subject: [PATCH v3 2/6] ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in
 SWSUP only in active
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <1368629322-3170-3-git-send-email-rnayak@ti.com>

Some IPs (like UART) need the sidle mode to be controlled in SW only
while they are active. Once they go inactive, they need the IP to be
put back in HW control so they are also wakeup capable.

The flag HWMOD_SWSUP_SIDLE takes care of IPs which need the sidle
mode to be *always* controlled in SWSUP. We now have a need to control
IPs sidle mode in SWSUP only while its active.

So define a new flag 'HWMOD_SWSUP_SIDLE_ACT' to help the framework
know about these new IP requirements.

Tested-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
 arch/arm/mach-omap2/omap_hwmod.h |    4 ++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c28552b..5739429 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1356,7 +1356,8 @@ static void _enable_sysc(struct omap_hwmod *oh)
 
 	clkdm = _get_clkdm(oh);
 	if (sf & SYSC_HAS_SIDLEMODE) {
-		if (oh->flags & HWMOD_SWSUP_SIDLE) {
+		if (oh->flags & HWMOD_SWSUP_SIDLE ||
+		    oh->flags & HWMOD_SWSUP_SIDLE_ACT) {
 			idlemode = HWMOD_IDLEMODE_NO;
 		} else {
 			if (sf & SYSC_HAS_ENAWAKEUP)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index fe59629..8498774 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -463,6 +463,9 @@ struct omap_hwmod_omap4_prcm {
  *     is kept in force-standby mode. Failing to do so causes PM problems
  *     with musb on OMAP3630 at least. Note that musb has a dedicated register
  *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
+ * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
+ *     out of idle, but rely on smart-idle to the put it back in idle,
+ *     so the wakeups are still functional (Only known case for now is UART)
  */
 #define HWMOD_SWSUP_SIDLE			(1 << 0)
 #define HWMOD_SWSUP_MSTANDBY			(1 << 1)
@@ -476,6 +479,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_EXT_OPT_MAIN_CLK			(1 << 9)
 #define HWMOD_BLOCK_WFI				(1 << 10)
 #define HWMOD_FORCE_MSTANDBY			(1 << 11)
+#define HWMOD_SWSUP_SIDLE_ACT			(1 << 12)
 
 /*
  * omap_hwmod._int_flags definitions
-- 
1.7.9.5



From rnayak at ti.com  Wed May 15 10:48:41 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:41 +0530
Subject: [PATCH v3 5/6] SERIAL: OMAP: Remove the slave idle handling from the
 driver
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <1368629322-3170-6-git-send-email-rnayak@ti.com>

From: Santosh Shilimkar <santosh.shilimkar at ti.com>

UART IP slave idle handling now taken care by runtime pm backend(hwmod layer)
so remove the hackery from the driver.

As discussed on the list, in future if dma mode needs to be brought
back to this driver, UART sysc handling needs to be updated in
framework such a way that no-idle/force idle profile can be supported.
Given the broken dma mode for OMAP uarts, its very unlikely.

Acked-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Tested-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
Signed-off-by: Rajendra nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/tty/serial/omap-serial.c          |   23 -----------------------
 include/linux/platform_data/serial-omap.h |    2 --
 2 files changed, 25 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 30d4f7a..f0b9f6b 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -202,26 +202,6 @@ static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 	return pdata->get_context_loss_count(up->dev);
 }
 
-static void serial_omap_set_forceidle(struct uart_omap_port *up)
-{
-	struct omap_uart_port_info *pdata = up->dev->platform_data;
-
-	if (!pdata || !pdata->set_forceidle)
-		return;
-
-	pdata->set_forceidle(up->dev);
-}
-
-static void serial_omap_set_noidle(struct uart_omap_port *up)
-{
-	struct omap_uart_port_info *pdata = up->dev->platform_data;
-
-	if (!pdata || !pdata->set_noidle)
-		return;
-
-	pdata->set_noidle(up->dev);
-}
-
 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 {
 	struct omap_uart_port_info *pdata = up->dev->platform_data;
@@ -298,8 +278,6 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	serial_omap_set_forceidle(up);
-
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
 }
@@ -364,7 +342,6 @@ static void serial_omap_start_tx(struct uart_port *port)
 
 	pm_runtime_get_sync(up->dev);
 	serial_omap_enable_ier_thri(up);
-	serial_omap_set_noidle(up);
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
 }
diff --git a/include/linux/platform_data/serial-omap.h b/include/linux/platform_data/serial-omap.h
index ff9b0aa..c860c1b 100644
--- a/include/linux/platform_data/serial-omap.h
+++ b/include/linux/platform_data/serial-omap.h
@@ -43,8 +43,6 @@ struct omap_uart_port_info {
 	int			DTR_present;
 
 	int (*get_context_loss_count)(struct device *);
-	void (*set_forceidle)(struct device *);
-	void (*set_noidle)(struct device *);
 	void (*enable_wakeup)(struct device *, bool);
 };
 
-- 
1.7.9.5



From rnayak at ti.com  Wed May 15 10:48:37 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:37 +0530
Subject: [PATCH v3 1/6] ARM: OMAP2+: hwmod: Fix sidle programming in
 _enable_sysc()/_idle_sysc()
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <1368629322-3170-2-git-send-email-rnayak@ti.com>

_enable_sysc() and _idle_sysc() handle the midle mode programming correctly
and program HWMOD_IDLEMODE_SMART or HWMOD_IDLEMODE_SMART_WKUP respectively
for supported IPs (The ones which support hardware controlled midle modes)

However the same programming logic is missing when it comes to sidle mode
programming. Here they seem to just set HWMOD_IDLEMODE_SMART (Again for the
ones which support hardware controlled sidle modes)

This problem was hidden due to the fact that a call to _enable_wakeup()
in those same functions would overwrite the idlemodes and program them
correctly (to HWMOD_IDLEMODE_SMART_WKUP in the supported cases)

So fix the sidlemode handling correctly in these functions and handle the
_enable_wakeup() for SIDLEMODE supported IPs same as the way its handled
for MIDLEMODE supported ones.

Tested-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   42 +++++++++++++++++++++++---------------
 1 file changed, 25 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d25a95f..c28552b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1356,13 +1356,26 @@ static void _enable_sysc(struct omap_hwmod *oh)
 
 	clkdm = _get_clkdm(oh);
 	if (sf & SYSC_HAS_SIDLEMODE) {
+		if (oh->flags & HWMOD_SWSUP_SIDLE) {
+			idlemode = HWMOD_IDLEMODE_NO;
+		} else {
+			if (sf & SYSC_HAS_ENAWAKEUP)
+				_enable_wakeup(oh, &v);
+			if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+				idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+			else
+				idlemode = HWMOD_IDLEMODE_SMART;
+		}
+
+		/*
+		 * This is special handling for some IPs like
+		 * 32k sync timer. Force them to idle!
+		 */
 		clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
 		if (clkdm_act && !(oh->class->sysc->idlemodes &
 				   (SIDLE_SMART | SIDLE_SMART_WKUP)))
 			idlemode = HWMOD_IDLEMODE_FORCE;
-		else
-			idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
-				HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+
 		_set_slave_idlemode(oh, idlemode, &v);
 	}
 
@@ -1391,10 +1404,6 @@ static void _enable_sysc(struct omap_hwmod *oh)
 	    (sf & SYSC_HAS_CLOCKACTIVITY))
 		_set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
-	/* If slave is in SMARTIDLE, also enable wakeup */
-	if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
-		_enable_wakeup(oh, &v);
-
 	_write_sysconfig(v, oh);
 
 	/*
@@ -1430,13 +1439,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
 	sf = oh->class->sysc->sysc_flags;
 
 	if (sf & SYSC_HAS_SIDLEMODE) {
-		/* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */
-		if (oh->flags & HWMOD_SWSUP_SIDLE ||
-		    !(oh->class->sysc->idlemodes &
-		      (SIDLE_SMART | SIDLE_SMART_WKUP)))
+		if (oh->flags & HWMOD_SWSUP_SIDLE) {
 			idlemode = HWMOD_IDLEMODE_FORCE;
-		else
-			idlemode = HWMOD_IDLEMODE_SMART;
+		} else {
+			if (sf & SYSC_HAS_ENAWAKEUP)
+				_enable_wakeup(oh, &v);
+			if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+				idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+			else
+				idlemode = HWMOD_IDLEMODE_SMART;
+		}
 		_set_slave_idlemode(oh, idlemode, &v);
 	}
 
@@ -1455,10 +1467,6 @@ static void _idle_sysc(struct omap_hwmod *oh)
 		_set_master_standbymode(oh, idlemode, &v);
 	}
 
-	/* If slave is in SMARTIDLE, also enable wakeup */
-	if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
-		_enable_wakeup(oh, &v);
-
 	_write_sysconfig(v, oh);
 }
 
-- 
1.7.9.5



From rnayak at ti.com  Wed May 15 10:48:36 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:36 +0530
Subject: [PATCH v3 0/6] ARM: OMAP2+: hwmod and SERIAL: Remove sysc handling
 from driver
Message-ID: <1368629322-3170-1-git-send-email-rnayak@ti.com>

changes in v3:
1. Fix the patch ordering issue (which otherwise broke git-bisect) as pointed
out by Kevin Hilman. I missed re-sending these out with the fix in time for
the 3.10 merge window. Thanks to Nishanth Menon for picking these up and doing
a rebase against 3.10-rc1.
Thanks also to Sourav and Vaibhav Bedia for running tests on 4430sdp and
beaglebone.

changes in v2:
---
1. Addressed the concerns from Paul Wamsley around cleanups in
_enable_wakeup()/_disable_wakeup(), and left them intact
2. Updates in changelogs in the serial patch about changes
needed when dma support is added back for serial
3. Dropped 1/8 from v1 since its already pulled in

The patches are based of 'fixes-non-critical' branch of
'git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap' tree
since patch 1/8 from v1 was pulled in here.

Patches can be found here:
git://github.com/rrnayak/linux.git sysc-cleanups
---

OMAP UART IP needs manual idle modes based on functional state of the
IP. Currently this is handled by the driver with function pointers
implemented in platform code.

This however breaks in case of device tree because of missing
idle handling. 

The series tries to address the issue and tries to remove complete
sysc handling from serial driver.

Patches has been tested on OMAP4430 SDP and OMAP5 EVM where the console
sluggishness was observed without idle mode handling. CPUIDLE and
suspend tested ok on these devices.

Thanks to Vaibhav Bedia for testing on Beaglebone(AM33XX) with suspend and
also the UART async wakeup from suspend.

Thanks to Sourav Poddar for Beagle XM(OMAP3630) devices testing with
retention and offmode in Idle and suspend for non-DT builds.

Serial driver platform code still has one more function pointer
left which is used to trigger io_ring(). This one needs some
discussion with pincontrol driver folks on how to implement
such a feature with generic pincontrol driver.

Rajendra Nayak (2):
  ARM: OMAP2+: hwmod: Fix sidle programming in
    _enable_sysc()/_idle_sysc()
  ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in
    active

Santosh Shilimkar (4):
  ARM: OMAP2+: hwmod-data: UART IP needs software control to manage
    sidle modes
  ARM: OMAP2+: serial: Remove the un-used slave idle hooks
  SERIAL: OMAP: Remove the slave idle handling from the driver
  ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis

 arch/arm/mach-omap2/omap_hwmod.c                   |  111 +++++---------------
 arch/arm/mach-omap2/omap_hwmod.h                   |    7 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    3 +
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |    6 ++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    4 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 +-
 arch/arm/mach-omap2/serial.c                       |   31 ------
 drivers/tty/serial/omap-serial.c                   |   23 ----
 include/linux/platform_data/serial-omap.h          |    2 -
 9 files changed, 48 insertions(+), 145 deletions(-)

-- 
1.7.9.5



From plagnioj at jcrosoft.com  Wed May 15 10:45:01 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:45:01 +0200
Subject: [PATCH 1/1] ARM: at91: dt: switch to standard IRQ flag defines
Message-ID: <1368629101-28251-1-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91rm9200.dtsi  |   45 +++++++++++---------
 arch/arm/boot/dts/at91sam9260.dtsi |   49 ++++++++++++----------
 arch/arm/boot/dts/at91sam9263.dtsi |   43 ++++++++++----------
 arch/arm/boot/dts/at91sam9g45.dtsi |   49 +++++++++++-----------
 arch/arm/boot/dts/at91sam9n12.dtsi |   41 ++++++++++---------
 arch/arm/boot/dts/at91sam9x5.dtsi  |   55 +++++++++++++------------
 arch/arm/boot/dts/sama5d3.dtsi     |   79 ++++++++++++++++++------------------
 7 files changed, 188 insertions(+), 173 deletions(-)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 361a957..4aad0d9 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -12,6 +12,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -79,25 +80,29 @@
 			st: timer at fffffd00 {
 				compatible = "atmel,at91rm9200-st";
 				reg = <0xfffffd00 0x100>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at fffa0000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffa0000 0x100>;
-				interrupts = <17 4 0 18 4 0 19 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+					      18 IRQ_TYPE_LEVEL_HIGH 0
+					      19 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at fffa4000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffa4000 0x100>;
-				interrupts = <20 4 0 21 4 0 22 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
+					      21 IRQ_TYPE_LEVEL_HIGH 0
+					      22 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			i2c0: i2c at fffb8000 {
 				compatible = "atmel,at91rm9200-i2c";
 				reg = <0xfffb8000 0x4000>;
-				interrupts = <12 4 6>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_twi>;
 				#address-cells = <1>;
@@ -108,7 +113,7 @@
 			mmc0: mmc at fffb4000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfffb4000 0x4000>;
-				interrupts = <10 4 0>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -117,7 +122,7 @@
 			ssc0: ssc at fffd0000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffd0000 0x4000>;
-				interrupts = <14 4 5>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disable";
@@ -126,7 +131,7 @@
 			ssc1: ssc at fffd4000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffd4000 0x4000>;
-				interrupts = <15 4 5>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disable";
@@ -135,7 +140,7 @@
 			ssc2: ssc at fffd8000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffd8000 0x4000>;
-				interrupts = <16 4 5>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
 				status = "disable";
@@ -144,7 +149,7 @@
 			macb0: ethernet at fffbc000 {
 				compatible = "cdns,at91rm9200-emac", "cdns,emac";
 				reg = <0xfffbc000 0x4000>;
-				interrupts = <24 4 3>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				phy-mode = "rmii";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
@@ -396,7 +401,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -406,7 +411,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -416,7 +421,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -426,7 +431,7 @@
 				pioD: gpio at fffffa00 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <5 4 1>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -437,7 +442,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -446,7 +451,7 @@
 			usart0: serial at fffc0000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffc0000 0x200>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -457,7 +462,7 @@
 			usart1: serial at fffc4000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffc4000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -468,7 +473,7 @@
 			usart2: serial at fffc8000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffc8000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -479,7 +484,7 @@
 			usart3: serial at fffcc000 {
 				compatible = "atmel,at91rm9200-usart";
 				reg = <0xfffcc000 0x200>;
-				interrupts = <23 4 5>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -490,7 +495,7 @@
 			usb1: gadget at fffb0000 {
 				compatible = "atmel,at91rm9200-udc";
 				reg = <0xfffb0000 0x4000>;
-				interrupts = <11 4 2>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
 				status = "disabled";
 			};
 		};
@@ -515,7 +520,7 @@
 		usb0: ohci at 00300000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00300000 0x100000>;
-			interrupts = <23 4 2>;
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7edadf3..a776f50 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -10,6 +10,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -86,19 +87,23 @@
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at fffa0000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffa0000 0x100>;
-				interrupts = <17 4 0 18 4 0 19 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+					      18 IRQ_TYPE_LEVEL_HIGH 0
+					      19 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at fffdc000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffdc000 0x100>;
-				interrupts = <26 4 0 27 4 0 28 4 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+					      27 IRQ_TYPE_LEVEL_HIGH 0
+					      28 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			pinctrl at fffff400 {
@@ -345,7 +350,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -355,7 +360,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -365,7 +370,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -376,7 +381,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -385,7 +390,7 @@
 			usart0: serial at fffb0000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffb0000 0x200>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -396,7 +401,7 @@
 			usart1: serial at fffb4000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffb4000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -407,7 +412,7 @@
 			usart2: serial at fffb8000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffb8000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -418,7 +423,7 @@
 			usart3: serial at fffd0000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffd0000 0x200>;
-				interrupts = <23 4 5>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -429,7 +434,7 @@
 			uart0: serial at fffd4000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffd4000 0x200>;
-				interrupts = <24 4 5>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -440,7 +445,7 @@
 			uart1: serial at fffd8000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffd8000 0x200>;
-				interrupts = <25 4 5>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -451,7 +456,7 @@
 			macb0: ethernet at fffc4000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xfffc4000 0x100>;
-				interrupts = <21 4 3>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
 				status = "disabled";
@@ -460,14 +465,14 @@
 			usb1: gadget at fffa4000 {
 				compatible = "atmel,at91rm9200-udc";
 				reg = <0xfffa4000 0x4000>;
-				interrupts = <10 4 2>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
 				status = "disabled";
 			};
 
 			i2c0: i2c at fffac000 {
 				compatible = "atmel,at91sam9260-i2c";
 				reg = <0xfffac000 0x100>;
-				interrupts = <11 4 6>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -476,7 +481,7 @@
 			mmc0: mmc at fffa8000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfffa8000 0x600>;
-				interrupts = <9 4 0>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -485,7 +490,7 @@
 			ssc0: ssc at fffbc000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfffbc000 0x4000>;
-				interrupts = <14 4 5>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -496,7 +501,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffc8000 0x200>;
-				interrupts = <12 4 3>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -507,7 +512,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffcc000 0x200>;
-				interrupts = <13 4 3>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -516,7 +521,7 @@
 			adc0: adc at fffe0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
-				interrupts = <5 4 0>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
 				atmel,adc-use-external-triggers;
 				atmel,adc-channels-used = <0xf>;
 				atmel,adc-vref = <3300>;
@@ -579,7 +584,7 @@
 		usb0: ohci at 00500000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00500000 0x100000>;
-			interrupts = <20 4 2>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index bb4d7ca..d9cf51a 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -8,6 +8,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -74,13 +75,13 @@
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at fff7c000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfff7c000 0x100>;
-				interrupts = <19 4 0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			rstc at fffffd00 {
@@ -326,7 +327,7 @@
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -336,7 +337,7 @@
 				pioB: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -346,7 +347,7 @@
 				pioC: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -356,7 +357,7 @@
 				pioD: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -366,7 +367,7 @@
 				pioE: gpio at fffffa00 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -377,7 +378,7 @@
 			dbgu: serial at ffffee00 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -386,7 +387,7 @@
 			usart0: serial at fff8c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff8c000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -397,7 +398,7 @@
 			usart1: serial at fff90000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff90000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -408,7 +409,7 @@
 			usart2: serial at fff94000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff94000 0x200>;
-				interrupts = <9 4 5>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -419,7 +420,7 @@
 			ssc0: ssc at fff98000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfff98000 0x4000>;
-				interrupts = <16 4 5>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -428,7 +429,7 @@
 			ssc1: ssc at fff9c000 {
 				compatible = "atmel,at91rm9200-ssc";
 				reg = <0xfff9c000 0x4000>;
-				interrupts = <17 4 5>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disabled";
@@ -437,7 +438,7 @@
 			macb0: ethernet at fffbc000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xfffbc000 0x100>;
-				interrupts = <21 4 3>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
 				status = "disabled";
@@ -446,14 +447,14 @@
 			usb1: gadget at fff78000 {
 				compatible = "atmel,at91rm9200-udc";
 				reg = <0xfff78000 0x4000>;
-				interrupts = <24 4 2>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
 				status = "disabled";
 			};
 
 			i2c0: i2c at fff88000 {
 				compatible = "atmel,at91sam9263-i2c";
 				reg = <0xfff88000 0x100>;
-				interrupts = <13 4 6>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -462,7 +463,7 @@
 			mmc0: mmc at fff80000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfff80000 0x600>;
-				interrupts = <10 4 0>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -471,7 +472,7 @@
 			mmc1: mmc at fff84000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfff84000 0x600>;
-				interrupts = <11 4 0>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -488,7 +489,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa4000 0x200>;
-				interrupts = <14 4 3>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -499,7 +500,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa8000 0x200>;
-				interrupts = <15 4 3>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -527,7 +528,7 @@
 		usb0: ohci at 00a00000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00a00000 0x100000>;
-			interrupts = <29 4 2>;
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 8ba4c71..f0091af 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -11,6 +11,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -85,7 +86,7 @@
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 
@@ -97,19 +98,19 @@
 			tcb0: timer at fff7c000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfff7c000 0x100>;
-				interrupts = <18 4 0>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at fffd4000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfffd4000 0x100>;
-				interrupts = <18 4 0>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
-				interrupts = <21 4 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -346,7 +347,7 @@
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -356,7 +357,7 @@
 				pioB: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -366,7 +367,7 @@
 				pioC: gpio at fffff600 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <4 4 1>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -376,7 +377,7 @@
 				pioD: gpio at fffff800 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <5 4 1>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -386,7 +387,7 @@
 				pioE: gpio at fffffa00 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <5 4 1>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -397,7 +398,7 @@
 			dbgu: serial at ffffee00 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -406,7 +407,7 @@
 			usart0: serial at fff8c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff8c000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -417,7 +418,7 @@
 			usart1: serial at fff90000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff90000 0x200>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -428,7 +429,7 @@
 			usart2: serial at fff94000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff94000 0x200>;
-				interrupts = <9 4 5>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -439,7 +440,7 @@
 			usart3: serial at fff98000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfff98000 0x200>;
-				interrupts = <10 4 5>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
@@ -450,7 +451,7 @@
 			macb0: ethernet at fffbc000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xfffbc000 0x100>;
-				interrupts = <25 4 3>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
 				status = "disabled";
@@ -459,7 +460,7 @@
 			i2c0: i2c at fff84000 {
 				compatible = "atmel,at91sam9g10-i2c";
 				reg = <0xfff84000 0x100>;
-				interrupts = <12 4 6>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -468,7 +469,7 @@
 			i2c1: i2c at fff88000 {
 				compatible = "atmel,at91sam9g10-i2c";
 				reg = <0xfff88000 0x100>;
-				interrupts = <13 4 6>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -477,7 +478,7 @@
 			ssc0: ssc at fff9c000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xfff9c000 0x4000>;
-				interrupts = <16 4 5>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -486,7 +487,7 @@
 			ssc1: ssc at fffa0000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xfffa0000 0x4000>;
-				interrupts = <17 4 5>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disabled";
@@ -495,7 +496,7 @@
 			adc0: adc at fffb0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffb0000 0x100>;
-				interrupts = <20 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
 				atmel,adc-use-external-triggers;
 				atmel,adc-channels-used = <0xff>;
 				atmel,adc-vref = <3300>;
@@ -535,7 +536,7 @@
 			mmc0: mmc at fff80000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfff80000 0x600>;
-				interrupts = <11 4 0>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -546,7 +547,7 @@
 			mmc1: mmc at fffd0000 {
 				compatible = "atmel,hsmci";
 				reg = <0xfffd0000 0x600>;
-				interrupts = <29 4 0>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma 1 13>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -604,14 +605,14 @@
 		usb0: ohci at 00700000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00700000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
 		usb1: ehci at 00800000 {
 			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 			reg = <0x00800000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e166e0c..566af32 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -9,6 +9,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -79,7 +80,7 @@
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			shdwc at fffffe10 {
@@ -90,7 +91,7 @@
 			mmc0: mmc at f0008000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf0008000 0x600>;
-				interrupts = <12 4 0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -101,19 +102,19 @@
 			tcb0: timer at f8008000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf8008000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at f800c000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf800c000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
-				interrupts = <20 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -287,7 +288,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -297,7 +298,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -307,7 +308,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -317,7 +318,7 @@
 				pioD: gpio at fffffa00 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -328,7 +329,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -337,7 +338,7 @@
 			ssc0: ssc at f0010000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf0010000 0x4000>;
-				interrupts = <28 4 5>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -346,7 +347,7 @@
 			usart0: serial at f801c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf801c000 0x4000>;
-				interrupts = <5 4 5>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
 				status = "disabled";
@@ -355,7 +356,7 @@
 			usart1: serial at f8020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x4000>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
 				status = "disabled";
@@ -364,7 +365,7 @@
 			usart2: serial at f8024000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x4000>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
 				status = "disabled";
@@ -373,7 +374,7 @@
 			usart3: serial at f8028000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8028000 0x4000>;
-				interrupts = <8 4 5>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart3>;
 				status = "disabled";
@@ -382,7 +383,7 @@
 			i2c0: i2c at f8010000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;
-				interrupts = <9 4 6>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma 1 13>,
 				       <&dma 1 14>;
 				dma-names = "tx", "rx";
@@ -394,7 +395,7 @@
 			i2c1: i2c at f8014000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8014000 0x100>;
-				interrupts = <10 4 6>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma 1 15>,
 				       <&dma 1 16>;
 				dma-names = "tx", "rx";
@@ -408,7 +409,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
-				interrupts = <13 4 3>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -419,7 +420,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
-				interrupts = <14 4 3>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -450,7 +451,7 @@
 		usb0: ohci at 00500000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00500000 0x00100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index cfbf923..af91599 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -11,6 +11,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -87,32 +88,32 @@
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 
 			tcb0: timer at f8008000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf8008000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			tcb1: timer at f800c000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf800c000 0x100>;
-				interrupts = <17 4 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma0: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
-				interrupts = <20 4 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
 			dma1: dma-controller at ffffee00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffee00 0x200>;
-				interrupts = <21 4 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -416,7 +417,7 @@
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -426,7 +427,7 @@
 				pioB: gpio at fffff600 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x200>;
-					interrupts = <2 4 1>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					#gpio-lines = <19>;
@@ -437,7 +438,7 @@
 				pioC: gpio at fffff800 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -447,7 +448,7 @@
 				pioD: gpio at fffffa00 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x200>;
-					interrupts = <3 4 1>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					#gpio-lines = <22>;
@@ -459,7 +460,7 @@
 			ssc0: ssc at f0010000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf0010000 0x4000>;
-				interrupts = <28 4 5>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -468,7 +469,7 @@
 			mmc0: mmc at f0008000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf0008000 0x600>;
-				interrupts = <12 4 0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma0 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -479,7 +480,7 @@
 			mmc1: mmc at f000c000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf000c000 0x600>;
-				interrupts = <26 4 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 1 0>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
@@ -490,7 +491,7 @@
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -499,7 +500,7 @@
 			usart0: serial at f801c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf801c000 0x200>;
-				interrupts = <5 4 5>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
 				status = "disabled";
@@ -508,7 +509,7 @@
 			usart1: serial at f8020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x200>;
-				interrupts = <6 4 5>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
 				status = "disabled";
@@ -517,7 +518,7 @@
 			usart2: serial at f8024000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x200>;
-				interrupts = <7 4 5>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
 				status = "disabled";
@@ -526,7 +527,7 @@
 			macb0: ethernet at f802c000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
-				interrupts = <24 4 3>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb0_rmii>;
 				status = "disabled";
@@ -535,14 +536,14 @@
 			macb1: ethernet at f8030000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xf8030000 0x100>;
-				interrupts = <27 4 3>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
 				status = "disabled";
 			};
 
 			i2c0: i2c at f8010000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;
-				interrupts = <9 4 6>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 1 7>,
 				       <&dma0 1 8>;
 				dma-names = "tx", "rx";
@@ -556,7 +557,7 @@
 			i2c1: i2c at f8014000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8014000 0x100>;
-				interrupts = <10 4 6>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma1 1 5>,
 				       <&dma1 1 6>;
 				dma-names = "tx", "rx";
@@ -570,7 +571,7 @@
 			i2c2: i2c at f8018000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8018000 0x100>;
-				interrupts = <11 4 6>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 1 9>,
 				       <&dma0 1 10>;
 				dma-names = "tx", "rx";
@@ -584,7 +585,7 @@
 			adc0: adc at f804c000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf804c000 0x100>;
-				interrupts = <19 4 0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
 				atmel,adc-use-external;
 				atmel,adc-channels-used = <0xffff>;
 				atmel,adc-vref = <3300>;
@@ -627,7 +628,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
-				interrupts = <13 4 3>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -638,7 +639,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
-				interrupts = <14 4 3>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
@@ -647,7 +648,7 @@
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x40>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				status = "disabled";
 			};
 		};
@@ -676,14 +677,14 @@
 		usb0: ohci at 00600000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00600000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
 		usb1: ehci at 00700000 {
 			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 			reg = <0x00700000 0x100000>;
-			interrupts = <22 4 2>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 05a3380..c00e158 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -10,6 +10,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -61,7 +62,7 @@
 			mmc0: mmc at f0000000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf0000000 0x600>;
-				interrupts = <21 4 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma0 2 0>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
@@ -76,7 +77,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91sam9x5-spi";
 				reg = <0xf0004000 0x100>;
-				interrupts = <24 4 3>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				cs-gpios = <&pioD 13 0
 					    &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
 					    &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
@@ -90,7 +91,7 @@
 			ssc0: ssc at f0008000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf0008000 0x4000>;
-				interrupts = <38 4 4>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 				status = "disabled";
@@ -99,7 +100,7 @@
 			can0: can at f000c000 {
 				compatible = "atmel,at91sam9x5-can";
 				reg = <0xf000c000 0x300>;
-				interrupts = <40 4 3>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_can0_rx_tx>;
 				status = "disabled";
@@ -108,13 +109,13 @@
 			tcb0: timer at f0010000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf0010000 0x100>;
-				interrupts = <26 4 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			i2c0: i2c at f0014000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf0014000 0x4000>;
-				interrupts = <18 4 6>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 2 7>,
 				       <&dma0 2 8>;
 				dma-names = "tx", "rx";
@@ -128,7 +129,7 @@
 			i2c1: i2c at f0018000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf0018000 0x4000>;
-				interrupts = <19 4 6>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma0 2 9>,
 				       <&dma0 2 10>;
 				dma-names = "tx", "rx";
@@ -142,7 +143,7 @@
 			usart0: serial at f001c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf001c000 0x100>;
-				interrupts = <12 4 5>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
 				status = "disabled";
@@ -151,7 +152,7 @@
 			usart1: serial at f0020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf0020000 0x100>;
-				interrupts = <13 4 5>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
 				status = "disabled";
@@ -160,7 +161,7 @@
 			macb0: ethernet at f0028000 {
 				compatible = "cnds,pc302-gem", "cdns,gem";
 				reg = <0xf0028000 0x100>;
-				interrupts = <34 4 3>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
 				status = "disabled";
@@ -169,14 +170,14 @@
 			isi: isi at f0034000 {
 				compatible = "atmel,at91sam9g45-isi";
 				reg = <0xf0034000 0x4000>;
-				interrupts = <37 4 5>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
 				status = "disabled";
 			};
 
 			mmc1: mmc at f8000000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf8000000 0x600>;
-				interrupts = <22 4 0>;
+				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 2 0>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
@@ -189,7 +190,7 @@
 			mmc2: mmc at f8004000 {
 				compatible = "atmel,hsmci";
 				reg = <0xf8004000 0x600>;
-				interrupts = <23 4 0>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 2 1>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
@@ -204,7 +205,7 @@
 				#size-cells = <0>;
 				compatible = "atmel,at91sam9x5-spi";
 				reg = <0xf8008000 0x100>;
-				interrupts = <25 4 3>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
 				cs-gpios = <&pioC 25 0
 					    &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
 					    &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
@@ -218,7 +219,7 @@
 			ssc1: ssc at f800c000 {
 				compatible = "atmel,at91sam9g45-ssc";
 				reg = <0xf800c000 0x4000>;
-				interrupts = <39 4 4>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
 				status = "disabled";
@@ -227,7 +228,7 @@
 			can1: can at f8010000 {
 				compatible = "atmel,at91sam9x5-can";
 				reg = <0xf8010000 0x300>;
-				interrupts = <41 4 3>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_can1_rx_tx>;
 			};
@@ -235,13 +236,13 @@
 			tcb1: timer at f8014000 {
 				compatible = "atmel,at91sam9x5-tcb";
 				reg = <0xf8014000 0x100>;
-				interrupts = <27 4 0>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			adc0: adc at f8018000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf8018000 0x100>;
-				interrupts = <29 4 5>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <
 					&pinctrl_adc0_adtrg
@@ -295,7 +296,7 @@
 			tsadcc: tsadcc at f8018000 {
 				compatible = "atmel,at91sam9x5-tsadcc";
 				reg = <0xf8018000 0x4000>;
-				interrupts = <29 4 5>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
 				atmel,tsadcc_clock = <300000>;
 				atmel,filtering_average = <0x03>;
 				atmel,pendet_debounce = <0x08>;
@@ -307,7 +308,7 @@
 			i2c2: i2c at f801c000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf801c000 0x4000>;
-				interrupts = <20 4 6>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
 				dmas = <&dma1 2 11>,
 				       <&dma1 2 12>;
 				dma-names = "tx", "rx";
@@ -319,7 +320,7 @@
 			usart2: serial at f8020000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x100>;
-				interrupts = <14 4 5>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
 				status = "disabled";
@@ -328,7 +329,7 @@
 			usart3: serial at f8024000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x100>;
-				interrupts = <15 4 5>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart3>;
 				status = "disabled";
@@ -337,7 +338,7 @@
 			macb1: ethernet at f802c000 {
 				compatible = "cdns,at32ap7000-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
-				interrupts = <35 4 3>;
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb1_rmii>;
 				status = "disabled";
@@ -346,7 +347,7 @@
 			sha at f8034000 {
 				compatible = "atmel,sam9g46-sha";
 				reg = <0xf8034000 0x100>;
-				interrupts = <42 4 0>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			aes at f8038000 {
@@ -358,20 +359,20 @@
 			tdes at f803c000 {
 				compatible = "atmel,sam9g46-tdes";
 				reg = <0xf803c000 0x100>;
-				interrupts = <44 4 0>;
+				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			dma0: dma-controller at ffffe600 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffe600 0x200>;
-				interrupts = <30 4 0>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
 			dma1: dma-controller at ffffe800 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffe800 0x200>;
-				interrupts = <31 4 0>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
 				#dma-cells = <2>;
 			};
 
@@ -383,7 +384,7 @@
 			dbgu: serial at ffffee00 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
-				interrupts = <2 4 7>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
@@ -817,7 +818,7 @@
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x100>;
-					interrupts = <6 4 1>;
+					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -827,7 +828,7 @@
 				pioB: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x100>;
-					interrupts = <7 4 1>;
+					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -837,7 +838,7 @@
 				pioC: gpio at fffff600 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff600 0x100>;
-					interrupts = <8 4 1>;
+					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -847,7 +848,7 @@
 				pioD: gpio at fffff800 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff800 0x100>;
-					interrupts = <9 4 1>;
+					interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -857,7 +858,7 @@
 				pioE: gpio at fffffa00 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffffa00 0x100>;
-					interrupts = <10 4 1>;
+					interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
@@ -878,7 +879,7 @@
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
-				interrupts = <3 4 5>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
 			};
 
 			watchdog at fffffe40 {
@@ -890,7 +891,7 @@
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x30>;
-				interrupts = <1 4 7>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 			};
 		};
 
@@ -900,7 +901,7 @@
 			compatible = "atmel,at91sam9rl-udc";
 			reg = <0x00500000 0x100000
 			       0xf8030000 0x4000>;
-			interrupts = <33 4 2>;
+			interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 
 			ep0 {
@@ -1012,14 +1013,14 @@
 		usb1: ohci at 00600000 {
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00600000 0x100000>;
-			interrupts = <32 4 2>;
+			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
 		usb2: ehci at 00700000 {
 			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 			reg = <0x00700000 0x100000>;
-			interrupts = <32 4 2>;
+			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
 			status = "disabled";
 		};
 
@@ -1035,7 +1036,7 @@
 				0xffffc000 0x00000070	/* NFC HSMC regs */
 				0x00200000 0x00100000	/* NFC SRAM banks */
 				>;
-			interrupts = <5 4 6>;
+			interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
-- 
1.7.10.4



From rnayak at ti.com  Wed May 15 10:48:40 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:18:40 +0530
Subject: [PATCH v3 4/6] ARM: OMAP2+: serial: Remove the un-used slave idle
 hooks
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <1368629322-3170-5-git-send-email-rnayak@ti.com>

From: Santosh Shilimkar <santosh.shilimkar at ti.com>

UART IP idle handling now taken care by runtime pm backend(hwmod) indirectly
and OMAP serial driver is also cleaned up accordingly.

So remove the un-used slave idle platforms hooks now.

Tested-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
Signed-off-by: Rajendra nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/serial.c |   31 -------------------------------
 1 file changed, 31 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 8396b5b..f660156 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -95,38 +95,9 @@ static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 		omap_hwmod_disable_wakeup(od->hwmods[0]);
 }
 
-/*
- * Errata i291: [UART]:Cannot Acknowledge Idle Requests
- * in Smartidle Mode When Configured for DMA Operations.
- * WA: configure uart in force idle mode.
- */
-static void omap_uart_set_noidle(struct device *dev)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct omap_device *od = to_omap_device(pdev);
-
-	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
-}
-
-static void omap_uart_set_smartidle(struct device *dev)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct omap_device *od = to_omap_device(pdev);
-	u8 idlemode;
-
-	if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
-		idlemode = HWMOD_IDLEMODE_SMART_WKUP;
-	else
-		idlemode = HWMOD_IDLEMODE_SMART;
-
-	omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
-}
-
 #else
 static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {}
-static void omap_uart_set_noidle(struct device *dev) {}
-static void omap_uart_set_smartidle(struct device *dev) {}
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_OMAP_MUX
@@ -299,8 +270,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
 	omap_up.flags = UPF_BOOT_AUTOCONF;
 	omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
-	omap_up.set_forceidle = omap_uart_set_smartidle;
-	omap_up.set_noidle = omap_uart_set_noidle;
 	omap_up.enable_wakeup = omap_uart_enable_wakeup;
 	omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
 	omap_up.dma_rx_timeout = info->dma_rx_timeout;
-- 
1.7.9.5



From nicolas.pitre at linaro.org  Wed May 15 10:51:43 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 15 May 2013 10:51:43 -0400 (EDT)
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <20130515142441.GA385@e102568-lin.cambridge.arm.com>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
 <20130514130005.GD29592@e102654-lin.cambridge.arm.com>
 <alpine.LFD.2.03.1305141820280.31158@syhkavp.arg>
 <20130515142441.GA385@e102568-lin.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305151037330.31158@syhkavp.arg>

On Wed, 15 May 2013, Lorenzo Pieralisi wrote:

> On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
> > On Tue, 14 May 2013, Javi Merino wrote:
> > 
> > > On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> > > 
> > > > +static inline void init_cpu_port(struct cpu_port *port, u32 index, u32 mpidr)
> > > 
> > > The mpidr should be u64.
> > 
> > Why?
> 
> Since on arm64 MPIDR_EL1 size is 64 bits, we need the driver to work on
> both arm and arm64.

OK.

Are you OK for me to carry this patch in the series for MCPM support 
on RTSM?  I would like to send it to arm-soc ASAP.


Nicolas


From lars at metafoo.de  Wed May 15 10:52:03 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Wed, 15 May 2013 16:52:03 +0200
Subject: [RFC/PATCH] dma: of: Make of_dma_simple_xlate match on DMA device
 and channel ID
In-Reply-To: <3106852.EdI2KVGSEm@avalon>
References: <1368624449-29003-1-git-send-email-laurent.pinchart@ideasonboard.com>
 <51938FFD.2020300@metafoo.de> <3106852.EdI2KVGSEm@avalon>
Message-ID: <5193A113.4050301@metafoo.de>

On 05/15/2013 03:55 PM, Laurent Pinchart wrote:
> Hi Lars-Peter,
> 
> (CC'ing LAKML, I had forgotten to do so when I sent the patch)
> 
> On Wednesday 15 May 2013 15:39:09 Lars-Peter Clausen wrote:
>> On 05/15/2013 03:27 PM, Laurent Pinchart wrote:
>>> When translating a DT DMA channel specifier, the most common use case is
>>> to match the DMA channel based on the channel DMA engine and channel ID.
>>> Modify the of_dma_simple_xlate() function to do so, simplifying the API
>>> for DMA engine drivers.
>>>
>>> There is no need to check the DMA cells count in the filter function as
>>> the check is already performed by the caller in of_dma_get_controller().
>>>
>>> Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
>>
>> Hi,
>>
>> I've submitted a very similar patch some time ago, see
>> https://lkml.org/lkml/2013/3/25/250
> 
> Thanks. So my patch makes at least some sense :-)

> 
> I had the impression that this is what omap-dma needs as well, hence the 
> modification to the existing xlate function. I'm fine with a separate function 
> as well if the current code covers different use cases.

My first attempt was to modify simple_xlate function, but I think it didn't
work for all users (some of which aren't applied yet), so I added a separate
function.

> 
>>> ---
>>>
>>>  drivers/dma/of-dma.c   | 39 +++++++++++++++++++++++++++++++--------
>>>  drivers/dma/omap-dma.c |  8 +-------
>>>  include/linux/of_dma.h |  5 -----
>>>  3 files changed, 32 insertions(+), 20 deletions(-)
>>>
>>> I've implemented this function while working on a DMA engine driver, and
>>> realized that it wasn't specific to my driver at all. As I'm new to the
>>> DMA engine API, I'd appreciate feedback on whether this change makes
>>> sense, or if I should instead keep the existing of_dma_simple_xlate()
>>> function and create a separate simple xlate helper.
>>>
>>> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
>>> index 7aa0864..702a45d 100644
>>> --- a/drivers/dma/of-dma.c
>>> +++ b/drivers/dma/of-dma.c
>>> @@ -202,6 +202,27 @@ struct dma_chan *of_dma_request_slave_channel(struct
>>> device_node *np,
>>>  	return NULL;
>>>  }
>>>
>>> +struct of_dma_filter_args {
>>> +	struct dma_device *device;
>>> +	unsigned int chan_id;
>>> +};
>>> +
>>> +/**
>>> + * of_dma_simple_xlate_filter - Channel filter function for
>>> of_dma_simple_xlate + * @dma_chan:	pointer to candidate DMA channel
>>> + * @param:	pointer to filter parameter
>>> + *
>>> + * Filter out candidate DMA channels that don't match the channel ID or
>>> + * DMA engine device passed as arguments.
>>> + */
>>> +static bool of_dma_simple_xlate_filter(struct dma_chan *chan, void
>>> *param)
>>> +{
>>> +	struct of_dma_filter_args *fargs = param;
>>> +
>>> +	return (chan->device == fargs->device) &&
>>> +	       (chan->chan_id == fargs->chan_id);
>>> +}
>>> +
>>>  /**
>>>   * of_dma_simple_xlate - Simple DMA engine translation function
>>>   * @dma_spec:	pointer to DMA specifier as found in the device tree
>>> @@ -216,16 +237,18 @@ struct dma_chan *of_dma_request_slave_channel(struct
>>> device_node *np,> 
>>>  struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
>>>  						struct of_dma *ofdma)
>>>  {
>>> -	int count = dma_spec->args_count;
>>> -	struct of_dma_filter_info *info = ofdma->of_dma_data;
>>> +	struct dma_device *dev = ofdma->of_dma_data;
>>> +	struct of_dma_filter_args fargs;
>>> +	dma_cap_mask_t cap;
>>>
>>> -	if (!info || !info->filter_fn)
>>> -		return NULL;
>>> +	/* There's no need to specify matching caps as we're going to match a
>>> +	 * specific DMA channel anyway.
>>> +	 */
>>> +	dma_cap_zero(cap);
>>>
>>> -	if (count != 1)
>>> -		return NULL;
>>> +	fargs.device = dev;
>>> +	fargs.chan_id = dma_spec->args[0];
>>>
>>> -	return dma_request_channel(info->dma_cap, info->filter_fn,
>>> -			&dma_spec->args[0]);
>>> +	return dma_request_channel(cap, of_dma_simple_xlate_filter, &fargs);
>>>  }
>>>  EXPORT_SYMBOL_GPL(of_dma_simple_xlate);
>>> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
>>> index ec3fc4f..7e7ff06 100644
>>> --- a/drivers/dma/omap-dma.c
>>> +++ b/drivers/dma/omap-dma.c
>>> @@ -69,10 +69,6 @@ static const unsigned es_bytes[] = {
>>>  	[OMAP_DMA_DATA_TYPE_S32] = 4,
>>>  };
>>>
>>> -static struct of_dma_filter_info omap_dma_info = {
>>> -	.filter_fn = omap_dma_filter_fn,
>>> -};
>>> -
>>>  static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
>>>  {
>>>  	return container_of(d, struct omap_dmadev, ddev);
>>> @@ -641,11 +637,9 @@ static int omap_dma_probe(struct platform_device
>>> *pdev)> 
>>>  	platform_set_drvdata(pdev, od);
>>>  	if (pdev->dev.of_node) {
>>> -		omap_dma_info.dma_cap = od->ddev.cap_mask;
>>> -
>>>  		/* Device-tree DMA controller registration */
>>>  		rc = of_dma_controller_register(pdev->dev.of_node,
>>> -				of_dma_simple_xlate, &omap_dma_info);
>>> +				of_dma_simple_xlate, &od->ddev);
>>>  		if (rc) {
>>>  			pr_warn("OMAP-DMA: failed to register DMA controller\n");
>>>  			dma_async_device_unregister(&od->ddev);
>>> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
>>> index 364dda7..3c0d9ac 100644
>>> --- a/include/linux/of_dma.h
>>> +++ b/include/linux/of_dma.h
>>> @@ -27,11 +27,6 @@ struct of_dma {
>>>  	void			*of_dma_data;
>>>  };
>>>
>>> -struct of_dma_filter_info {
>>> -	dma_cap_mask_t	dma_cap;
>>> -	dma_filter_fn	filter_fn;
>>> -};
>>> -
>>>
>>>  #ifdef CONFIG_OF
>>>  extern int of_dma_controller_register(struct device_node *np,
>>>  		struct dma_chan *(*of_dma_xlate)



From plagnioj at jcrosoft.com  Wed May 15 10:48:46 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 16:48:46 +0200
Subject: [PATCH 1/1] ARM: at91: udpate defconfigs
Message-ID: <1368629326-28711-1-git-send-email-plagnioj@jcrosoft.com>

merge 9g20 with 9260 and 9g10 with 9261 as those SoCs can run from the same
kernel even in non DT world

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/configs/at91_dt_defconfig                 |   55 ++---
 arch/arm/configs/at91rm9200_defconfig              |  218 +++-----------------
 ...am9g20_defconfig => at91sam9260_9g20_defconfig} |   67 ++++--
 arch/arm/configs/at91sam9260_defconfig             |   91 --------
 ...am9261_defconfig => at91sam9261_9g10_defconfig} |   19 +-
 arch/arm/configs/at91sam9263_defconfig             |   39 ++--
 arch/arm/configs/at91sam9g45_defconfig             |   94 +++------
 arch/arm/configs/sama5_defconfig                   |   35 +++-
 arch/arm/mach-at91/Kconfig.non_dt                  |  159 +++++++-------
 arch/arm/mach-at91/Makefile                        |    2 -
 arch/arm/mach-at91/at91rm9200_time.c               |    6 +-
 arch/arm/mach-at91/board-sam9261ek.c               |   28 +--
 12 files changed, 270 insertions(+), 543 deletions(-)
 rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
 delete mode 100644 arch/arm/configs/at91sam9260_defconfig
 rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 047f2a4..a8800d3 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -42,6 +39,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -51,7 +51,8 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
-CONFIG_EEPROM_93CX6=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
@@ -92,7 +91,23 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_DAVICOM_PHY=y
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_RTL8187=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 CONFIG_INPUT_POLLDEV=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
@@ -112,13 +127,11 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SSB=m
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
@@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y
 CONFIG_FONT_ACORN_8x8=y
 CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
@@ -146,14 +156,9 @@ CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_FTDI_SIO=y
 CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=m
-CONFIG_USB_ATMEL_USBA=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_AT91=y
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
@@ -168,16 +173,18 @@ CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
@@ -192,7 +199,7 @@ CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=m
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=m
 CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index 4ae57a3..8b09934 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -1,10 +1,12 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
@@ -35,49 +37,37 @@ CONFIG_AT91_TIMER_HZ=100
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_AT91_CF=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
+# CONFIG_COMPACTION is not set
 CONFIG_ZBOOT_ROM_TEXT=0x10000000
 CONFIG_ZBOOT_ROM_BSS=0x20040000
 CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=m
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_BT=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
@@ -94,55 +84,21 @@ CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_TUN=m
+CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
-CONFIG_PHYLIB=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_MICREL_PHY=y
-CONFIG_PPP=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOE=m
-CONFIG_PPP_ASYNC=y
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -151,38 +107,8 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_SPI_BITBANG=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_HWMON=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83L785TS=m
+# CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91RM9200_WATCHDOG=y
@@ -194,43 +120,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_KEYSPAN=y
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_MCT_U232=y
-CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
@@ -240,84 +137,27 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_REISERFS_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=y
-CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
 CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
+CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_PCBC=y
 CONFIG_CRYPTO_SHA1=y
+CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
similarity index 67%
rename from arch/arm/configs/at91sam9g20_defconfig
rename to arch/arm/configs/at91sam9260_9g20_defconfig
index 892e828..f50c404 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -11,7 +10,15 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
+CONFIG_ARCH_AT91SAM9260=y
+CONFIG_MACH_AT91SAM9260EK=y
+CONFIG_MACH_CAM60=y
+CONFIG_MACH_SAM9_L9260=y
+CONFIG_MACH_AFEB9260=y
+CONFIG_MACH_USB_A9260=y
+CONFIG_MACH_QIL_A9260=y
+CONFIG_MACH_CPU9260=y
+CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_AT91SAM9G20EK=y
 CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_MACH_CPU9G20=y
@@ -20,10 +27,10 @@ CONFIG_MACH_PORTUXG20=y
 CONFIG_MACH_STAMP9G20=y
 CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
-CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
@@ -33,12 +40,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
@@ -46,8 +55,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
@@ -56,6 +68,8 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -63,23 +77,36 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
-CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_SERIO is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -94,12 +121,11 @@ CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -109,15 +135,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -125,3 +148,9 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_AT91_DEBUG_LL_DBGU0=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
deleted file mode 100644
index 05618eb..0000000
--- a/arch/arm/configs/at91sam9260_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_ARCH_AT91SAM9260_SAM9XE=y
-CONFIG_MACH_AT91SAM9260EK=y
-CONFIG_MACH_CAM60=y
-CONFIG_MACH_SAM9_L9260=y
-CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_USB_A9260=y
-CONFIG_MACH_QIL_A9260=y
-CONFIG_MACH_CPU9260=y
-CONFIG_MACH_FLEXIBITY=y
-CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
similarity index 91%
rename from arch/arm/configs/at91sam9261_defconfig
rename to arch/arm/configs/at91sam9261_9g10_defconfig
index c87beb9..9d35cd8 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
+CONFIG_MACH_AT91SAM9G10EK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
@@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_CFG80211=y
-CONFIG_LIB80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
@@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_ZD1201=m
 CONFIG_RTL8187=m
 CONFIG_LIBERTAS=m
@@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y
 CONFIG_SND_USB_AUDIO=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
@@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-CONFIG_FTRACE=y
 CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 36fed66b..9d72ab6 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -1,6 +1,4 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
@@ -48,9 +46,11 @@ CONFIG_IP_PIMSM_V2=y
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_IPV6=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -65,7 +65,6 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
@@ -73,23 +72,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_USB_ZD1201=m
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -98,6 +92,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -107,9 +102,9 @@ CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -124,16 +119,12 @@ CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
 CONFIG_SND_USB_AUDIO=m
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=m
@@ -145,22 +136,18 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_FUSE_FS=m
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_FTRACE=y
+CONFIG_NLS_UTF8=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 18964cd..08166cd 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -36,6 +33,9 @@ CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -45,9 +45,6 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-CONFIG_CFG80211=y
-CONFIG_LIB80211=y
-CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 CONFIG_DAVICOM_PHY=y
-CONFIG_LIBERTAS_THINFIRM=m
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_AT76C50X_USB=m
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_ATH_COMMON=m
-CONFIG_ATH9K=m
-CONFIG_CARL9170=m
-CONFIG_B43=m
-CONFIG_B43_PHY_N=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-CONFIG_RT2X00=m
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RTL8192CU=m
-CONFIG_WL1251=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX_MENU=m
-CONFIG_WL12XX=m
-CONFIG_WL12XX_SDIO=m
-CONFIG_ZD1211RW=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_KEYBOARD_QT2160=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=m
 CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
-CONFIG_FB_UDL=m
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_ATMEL_LCDC=y
+CONFIG_BACKLIGHT_ATMEL_PWM=y
 # CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_ARM is not set
 CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB is not set
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_MULTI=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_MULTI=y
 CONFIG_USB_G_MULTI_CDC=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=y
-CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
@@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_DMATEST=m
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
@@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_USER_API_HASH=m
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4d0dc3c..f6e78f8 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -26,7 +26,9 @@ CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_KEXEC=y
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -39,6 +41,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
@@ -95,7 +102,19 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_RTL8187=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ATMELMCI=y
@@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
 CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 6c24985..1a2abd8 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,15 +14,11 @@ config ARCH_AT91RM9200
 	select SOC_AT91RM9200
 
 config ARCH_AT91SAM9260
-	bool "AT91SAM9260 or AT91SAM9XE"
+	bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
 	select SOC_AT91SAM9260
 
 config ARCH_AT91SAM9261
-	bool "AT91SAM9261"
-	select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9G10
-	bool "AT91SAM9G10"
+	bool "AT91SAM9261 or AT91SAM9G10"
 	select SOC_AT91SAM9261
 
 config ARCH_AT91SAM9263
@@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL
 	bool "AT91SAM9RL"
 	select SOC_AT91SAM9RL
 
-config ARCH_AT91SAM9G20
-	bool "AT91SAM9G20"
-	select SOC_AT91SAM9260
-
 config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
 	select SOC_AT91SAM9G45
@@ -50,6 +42,14 @@ config ARCH_AT91X40
 
 endchoice
 
+config ARCH_AT91SAM9G20
+	bool
+	select ARCH_AT91SAM9260
+
+config ARCH_AT91SAM9G10
+	bool
+	select ARCH_AT91SAM9261
+
 # ----------------------------------------------------------
 
 if ARCH_AT91RM9200
@@ -207,76 +207,6 @@ config MACH_FLEXIBITY
 	  Select this if you are using Flexibity Connect board
 	  <http://www.flexibity.com>
 
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9261
-
-comment "AT91SAM9261 Board Type"
-
-config MACH_AT91SAM9261EK
-	bool "Atmel AT91SAM9261-EK Evaluation Kit"
-	select HAVE_AT91_DATAFLASH_CARD
-	help
-	  Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G10
-
-comment "AT91SAM9G10 Board Type"
-
-config MACH_AT91SAM9G10EK
-	bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-	select HAVE_AT91_DATAFLASH_CARD
-	help
-	  Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9263
-
-comment "AT91SAM9263 Board Type"
-
-config MACH_AT91SAM9263EK
-	bool "Atmel AT91SAM9263-EK Evaluation Kit"
-	select HAVE_AT91_DATAFLASH_CARD
-	help
-	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-
-config MACH_USB_A9263
-	bool "CALAO USB-A9263"
-	help
-	  Select this if you are using a Calao Systems USB-A9263.
-	  <http://www.calao-systems.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9RL
-
-comment "AT91SAM9RL Board Type"
-
-config MACH_AT91SAM9RLEK
-	bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-	help
-	  Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G20
-
 comment "AT91SAM9G20 Board Type"
 
 config MACH_AT91SAM9G20EK
@@ -341,17 +271,70 @@ config MACH_USB_A9G20
 	  Select this if you are using a Calao Systems USB-A9G20.
 	  <http://www.calao-systems.com>
 
+config MACH_SNAPPER_9260
+	bool "Bluewater Systems Snapper 9260/9G20 module"
+	help
+	  Select this if you are using the Bluewater Systems Snapper 9260 or
+	  Snapper 9G20 modules.
+	  <http://www.bluewatersys.com/>
 endif
 
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
-comment "AT91SAM9260/AT91SAM9G20 boards"
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9261
+
+comment "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+	bool "Atmel AT91SAM9261-EK Evaluation Kit"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+	bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9263
+
+comment "AT91SAM9263 Board Type"
+
+config MACH_AT91SAM9263EK
+	bool "Atmel AT91SAM9263-EK Evaluation Kit"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+
+config MACH_USB_A9263
+	bool "CALAO USB-A9263"
+	help
+	  Select this if you are using a Calao Systems USB-A9263.
+	  <http://www.calao-systems.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9RL
+
+comment "AT91SAM9RL Board Type"
+
+config MACH_AT91SAM9RLEK
+	bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+	help
+	  Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
 
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
 endif
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562d..f4a5f79 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,10 +27,8 @@ obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o
 obj-$(CONFIG_ARCH_AT91RM9200)	+= at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)	+= at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9261)	+= at91sam9261_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G10)	+= at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)	+= at91sam9g45_devices.o
 obj-$(CONFIG_ARCH_AT91X40)	+= at91x40.o at91x40_time.o
 
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 180b302..43aeae0 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -265,11 +265,9 @@ void __init at91rm9200_timer_init(void)
 	at91_st_write(AT91_ST_RTMR, 1);
 
 	/* Setup timer clockevent, with minimum of two ticks (important!!) */
-	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
-	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
-	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
 	clkevt.cpumask = cpumask_of(0);
-	clockevents_register_device(&clkevt);
+	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
+					2, AT91_ST_ALMV);
 
 	/* register clocksource */
 	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 9a6618a..473546b 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {}
  */
 static struct at73c213_board_info at73c213_data = {
 	.ssc_id		= 1,
-#if defined(CONFIG_MACH_AT91SAM9261EK)
-	.shortname	= "AT91SAM9261-EK external DAC",
-#else
-	.shortname	= "AT91SAM9G10-EK external DAC",
-#endif
+	.shortname	= "AT91SAM9261/9G10-EK external DAC",
 };
 
 #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -412,9 +408,6 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
 	.default_monspecs		= &at91fb_default_stn_monspecs,
 	.atmel_lcdfb_power_control	= at91_lcdc_stn_power_control,
 	.guard_time			= 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 
 #else
@@ -468,9 +461,6 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
 	.default_monspecs		= &at91fb_default_tft_monspecs,
 	.atmel_lcdfb_power_control	= at91_lcdc_tft_power_control,
 	.guard_time			= 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 #endif
 
@@ -574,6 +564,10 @@ static void __init ek_board_init(void)
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 	at91_add_device_serial();
+
+	if (cpu_is_at91sam9g10())
+		ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
+
 	/* USB Host */
 	at91_add_device_usbh(&ek_usbh_data);
 	/* USB Device */
@@ -606,11 +600,17 @@ static void __init ek_board_init(void)
 	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
-#if defined(CONFIG_MACH_AT91SAM9261EK)
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
-#else
+	/* Maintainer: Atmel */
+	.init_time	= at91sam926x_pit_init,
+	.map_io		= at91_map_io,
+	.handle_irq	= at91_aic_handle_irq,
+	.init_early	= ek_init_early,
+	.init_irq	= at91_init_irq_default,
+	.init_machine	= ek_board_init,
+MACHINE_END
+
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
-#endif
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-- 
1.7.10.4



From lorenzo.pieralisi at arm.com  Wed May 15 10:55:57 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Wed, 15 May 2013 15:55:57 +0100
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <alpine.LFD.2.03.1305151037330.31158@syhkavp.arg>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
 <20130514130005.GD29592@e102654-lin.cambridge.arm.com>
 <alpine.LFD.2.03.1305141820280.31158@syhkavp.arg>
 <20130515142441.GA385@e102568-lin.cambridge.arm.com>
 <alpine.LFD.2.03.1305151037330.31158@syhkavp.arg>
Message-ID: <20130515145557.GB385@e102568-lin.cambridge.arm.com>

On Wed, May 15, 2013 at 03:51:43PM +0100, Nicolas Pitre wrote:
> On Wed, 15 May 2013, Lorenzo Pieralisi wrote:
> 
> > On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
> > > On Tue, 14 May 2013, Javi Merino wrote:
> > > 
> > > > On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> > > > 
> > > > > +static inline void init_cpu_port(struct cpu_port *port, u32 index, u32 mpidr)
> > > > 
> > > > The mpidr should be u64.
> > > 
> > > Why?
> > 
> > Since on arm64 MPIDR_EL1 size is 64 bits, we need the driver to work on
> > both arm and arm64.
> 
> OK.
> 
> Are you OK for me to carry this patch in the series for MCPM support 
> on RTSM?  I would like to send it to arm-soc ASAP.

Absolutely, I will apply the latest fixes and send the updated version
to you for arm-soc inclusion today.

Lorenzo



From eduardo.valentin at ti.com  Wed May 15 10:58:46 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 15 May 2013 10:58:46 -0400
Subject: [PATCHv2 1/3] arm: introduce config HAS_BANDGAP
In-Reply-To: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
Message-ID: <1368629928-6723-2-git-send-email-eduardo.valentin@ti.com>

Introduce HAS_BANDGAP config entry. This config is a
boolean value so that arch code can flag is they
feature a bandgap device.

This config entry follows the same idea behind
ARCH_HAS_CPUFREQ.

Cc: Russell King <linux at arm.linux.org.uk>
Cc: Tony Lindgren <tony at atomide.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-omap at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 arch/arm/Kconfig            | 3 +++
 arch/arm/mach-omap2/Kconfig | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..bcbdec9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -174,6 +174,9 @@ config ARCH_HAS_CPUFREQ
 	  and that the relevant menu configurations are displayed for
 	  it.
 
+config ARCH_HAS_BANDGAP
+	bool
+
 config GENERIC_HWEIGHT
 	bool
 	default y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..8620ab5 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -4,6 +4,7 @@ config ARCH_OMAP
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
 	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_BANDGAP
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select ARCH_OMAP
 	select ARCH_REQUIRE_GPIOLIB
-- 
1.8.2.1.342.gfa7285d



From eduardo.valentin at ti.com  Wed May 15 10:58:47 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 15 May 2013 10:58:47 -0400
Subject: [PATCHv2 2/3] arm: dts: add bandgap entry for OMAP443x devices
In-Reply-To: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
Message-ID: <1368629928-6723-3-git-send-email-eduardo.valentin@ti.com>

This patch add the bandgap entry for OMAP4430 devices.

Cc: "Beno?t Cousson" <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-omap at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 arch/arm/boot/dts/omap443x.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..8d6c968 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -24,4 +24,8 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+	bandgap {
+		reg = <0x4a002260 0x4 0x4a00232C 0x4>;
+		compatible = "ti,omap4430-bandgap";
+	};
 };
-- 
1.8.2.1.342.gfa7285d



From eduardo.valentin at ti.com  Wed May 15 10:58:48 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 15 May 2013 10:58:48 -0400
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
Message-ID: <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>

Include bandgap devices for OMAP4460 devices.

Cc: "Beno?t Cousson" <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-omap at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
---
 arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..e5bfbfe 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -29,4 +29,13 @@
 			     <0 55 0x4>;
 		ti,hwmods = "debugss";
 	};
+
+	bandgap {
+		reg = <0x4a002260 0x4
+			0x4a00232C 0x4
+			0x4a002378 0x18>;
+		compatible = "ti,omap4460-bandgap";
+		interrupts = <0 126 4>; /* talert */
+		ti,tshut-gpio = <86>;
+	};
 };
-- 
1.8.2.1.342.gfa7285d



From rnayak at ti.com  Wed May 15 11:00:52 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 15 May 2013 20:30:52 +0530
Subject: [PATCH v2 0/6] ARM; OMAP2+: hwmod and SERIAL: Remove sysc handling
 from driver
In-Reply-To: <20130510140200.GA11267@kahuna>
References: <1366973695-2088-1-git-send-email-rnayak@ti.com>
 <87ppxhxixu.fsf@linaro.org> <20130510140200.GA11267@kahuna>
Message-ID: <5193A324.8090703@ti.com>

On Friday 10 May 2013 07:32 PM, Nishanth Menon wrote:
> On 11:09-20130426, Kevin Hilman wrote:
>> Rajendra Nayak <rnayak at ti.com> writes:
>>
>> [...]
>>
>>> OMAP UART IP needs manual idle modes based on functional state of the
>>> IP. Currently this is handled by the driver with function pointers
>>> implemented in platform code.
>>>
>>> This however breaks in case of device tree because of missing
>>> idle handling. 
>>>
>>> The series tries to address the issue and tries to remove complete
>>> sysc handling from serial driver.
>>
>> Other than the minor nit about the order of the series for bisect, 
>>
>> Reviewed-by: Kevin Hilman <khilman at linaro.org>
>>
>> Also tested this on OMAP4/Panda where I was having the sluggish console
>> issues using DT boot, and and can confirm that this fixes the problem:
>>
>> Tested-by: Kevin Hilman <khilman at linaro.org>  # OMAP4/Panda
>>
> I saw the same let of console sluggishness on SDP4430, Panda, Panda-ES
> as well on latest linus master.
> 
> For reference, I have rebased the series to latest master and fixes the
> sequencing:
> https://github.com/nmenon/linux-2.6-playground/commits/push/uart-fixes-sidle-3.10
> based on:
> master 70eba42 Merge tag 'please-pull-pstore' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux
> 
> Rajendra,
> Would you be able to repost this series so that we can get this into
> 3.10-rc2+?

Tony/Paul,

I just posted the v3 of these out [1] based off 3.10-rc1. Can we pull these in into -rc since
these actually fix the console sluggishness introduced in this merge window (we always had issues
with UART sidle handling with DT but never saw issues in mainline because of some static deps which got
removed this merge window  I guess which would otherwise hide the issue).

regards,
Rajendra

[1] http://marc.info/?l=linux-omap&m=136862939928398&w=2

> 



From will.deacon at arm.com  Wed May 15 11:04:02 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 16:04:02 +0100
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <51939FBC.3060705@free-electrons.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
 <51939FBC.3060705@free-electrons.com>
Message-ID: <20130515150402.GK23869@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
> On 05/15/2013 04:06 PM, Will Deacon wrote:
> > You could also try deleting both of the ALT_* lines and just putting a
> > W(nop) in there directly.
> 
> If I just delete the both of the ALT_* lines it no more hangs.
> If I put a  W(nop) instead it hangs.

Wow. This doesn't sound good for your CPU and you might want to check with
the Marvell guys...

Extra things you could try:

	- Try adding a 16-bit nop instead (remove the W, build thumb-2 and
	  double check in your diasassembly)

	- Try adding the W(nop) to other places in the kernel and see if you
	  can tickle the lock-up elsewhere.

	- Can you reproduce on the Armada XP? (since I have access to one of
	  those)

> > Early in boot (head.S:__fixup_smp), we detect whether the CPU has the MP
> > extensions then, if we're actually UP but the kernel has CONFIG_SMP=y, we
> > walk over the .alt.smp.init section looking at each entry in there. The
> > ALT_UP macro spits out an (address, instruction) pair, so in
> > __do_fixup_smp_on_up, we store the instruction to the address for each pair,
> > replacing the SMP instruction which sat there in the compiled image.
> > 
> > It could be that the CPUID checks are failing on your Marvell part. Can you
> > tell me what you have in your mpidr (mrc p15, 0, Rd, c0, c0, 5) and also
> > your midr (mrc p15, 0, Rd, c0, c0) please?
> 
> mpidr= 0x0
> midr= 0x561F5811

Should be fine, but it doesn't look like the patching is the issue here.

Will


From linus.walleij at linaro.org  Wed May 15 11:07:20 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 17:07:20 +0200
Subject: [PATCH 3/5] ARM: at91: dt: add pinctrl pre-processor define
In-Reply-To: <1368626585-24425-3-git-send-email-plagnioj@jcrosoft.com>
References: <20130515135821.GG22508@game.jcrosoft.org>
 <1368626585-24425-1-git-send-email-plagnioj@jcrosoft.com>
 <1368626585-24425-3-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdbAvb0qfmwa9UxuBLgDV-ArHoHk3-Fb9tFcPkeYQ=PpFA@mail.gmail.com>

On Wed, May 15, 2013 at 4:03 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks, this makes the device trees much more readable.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From t.figa at samsung.com  Wed May 15 11:08:04 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 15 May 2013 17:08:04 +0200
Subject: [PATCH] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
Message-ID: <1368630484-29939-1-git-send-email-t.figa@samsung.com>

This patch extends exynos_init_time() function to handle Exynos4210 rev0
SoC, which differs in availability of system timers and needs different
clocksource initialization.

This makes it possible to use exynos_init_time() function as init_time
callback for all Exynos-based boards, including Universal_C210, which
originally had to use samsung_timer_init().

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig               |  3 ++-
 arch/arm/mach-exynos/common.c              | 30 +++++++++++++++++++++++++++++-
 arch/arm/mach-exynos/common.h              |  2 ++
 arch/arm/mach-exynos/mach-universal_c210.c |  5 ++---
 4 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d19edff..ff18fc2 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -250,6 +250,7 @@ config MACH_ARMLEX4210
 config MACH_UNIVERSAL_C210
 	bool "Mobile UNIVERSAL_C210 Board"
 	select CLKSRC_MMIO
+	select CLKSRC_SAMSUNG_PWM
 	select CPU_EXYNOS4210
 	select EXYNOS4_SETUP_FIMC
 	select EXYNOS4_SETUP_FIMD0
@@ -281,7 +282,6 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_TV
 	select S5P_GPIO_INT
 	select S5P_SETUP_MIPIPHY
-	select SAMSUNG_HRT
 	help
 	  Machine support for Samsung Mobile Universal S5PC210 Reference
 	  Board.
@@ -410,6 +410,7 @@ config MACH_EXYNOS4_DT
 	depends on ARCH_EXYNOS4
 	select ARM_AMBA
 	select CLKSRC_OF
+	select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
 	select CPU_EXYNOS4210
 	select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
 	select PINCTRL
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 745e304..a2d2012 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -10,12 +10,14 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/bitops.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/gpio.h>
+#include <clocksource/samsung_pwm.h>
 #include <linux/sched.h>
 #include <linux/serial_core.h>
 #include <linux/of.h>
@@ -302,6 +304,13 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
+static struct samsung_pwm_variant exynos4_pwm_variant = {
+	.bits		= 32,
+	.div_base	= 0,
+	.has_tint_cstat	= true,
+	.tclk_mask	= 0,
+};
+
 void exynos4_restart(char mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
@@ -442,8 +451,20 @@ static void __init exynos5440_map_io(void)
 	iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
+void __init exynos_set_timer_source(u8 channels)
+{
+	exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
+	exynos4_pwm_variant.output_mask &= ~channels;
+}
+
 void __init exynos_init_time(void)
 {
+	unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+		EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
+		EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
+		EXYNOS4_IRQ_TIMER4_VIC,
+	};
+
 	if (of_have_populated_dt()) {
 #ifdef CONFIG_OF
 		of_clk_init(NULL);
@@ -455,7 +476,14 @@ void __init exynos_init_time(void)
 		exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
 		exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
-		mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
+#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
+		if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+			samsung_pwm_clocksource_init(S3C_VA_TIMER,
+					timer_irqs, &exynos4_pwm_variant);
+		else
+#endif
+			mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
+					EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
 	}
 }
 
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 60dd35c..11fc1e2 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -32,6 +32,8 @@ void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
 
 void exynos_firmware_init(void);
 
+void exynos_set_timer_source(u8 channels);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 327d50d..74ddb2b 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,6 @@
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/fimc-core.h>
-#include <plat/samsung-time.h>
 #include <plat/camport.h>
 
 #include <mach/map.h>
@@ -1094,7 +1093,7 @@ static void __init universal_map_io(void)
 {
 	exynos_init_io(NULL, 0);
 	s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-	samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+	exynos_set_timer_source(BIT(2) | BIT(4));
 	xxti_f = 0;
 	xusbxti_f = 24000000;
 }
@@ -1154,7 +1153,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
 	.map_io		= universal_map_io,
 	.init_machine	= universal_machine_init,
 	.init_late	= exynos_init_late,
-	.init_time	= samsung_timer_init,
+	.init_time	= exynos_init_time,
 	.reserve        = &universal_reserve,
 	.restart	= exynos4_restart,
 MACHINE_END
-- 
1.8.2.1



From t.figa at samsung.com  Wed May 15 11:09:44 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 15 May 2013 17:09:44 +0200
Subject: [PATCH] ARM: SAMSUNG: devs: Add names to fimd0 IRQ resources
Message-ID: <1368630584-30147-1-git-send-email-t.figa@samsung.com>

Since commit 1977e6d8 (drm/exynos: change the method for getting the
interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
named. This patch fixes probe failure in non-DT cases by adding
appropriate resource names to fimd0 platform device.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/devs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 30c2fe2..0f9c3f4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
 #ifdef CONFIG_S5P_DEV_FIMD0
 static struct resource s5p_fimd0_resource[] = {
 	[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
-	[1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
-	[2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
-	[3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
+	[1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
+	[2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
+	[3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
 };
 
 struct platform_device s5p_device_fimd0 = {
-- 
1.8.2.1



From t.figa at samsung.com  Wed May 15 11:16:08 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 15 May 2013 17:16:08 +0200
Subject: [PATCH] rtc: max8998: Check for pdata presence before dereferencing
Message-ID: <1368630968-30460-1-git-send-email-t.figa@samsung.com>

Currently the driver can crash with a NULL pointer dereference if no pdata
is provided, despite of successful registration of MFD part. This patch
fixes the problem by adding a NULL check before dereferencing the pdata
pointer.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/rtc/rtc-max8998.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-max8998.c b/drivers/rtc/rtc-max8998.c
index 48b6612..d5af7ba 100644
--- a/drivers/rtc/rtc-max8998.c
+++ b/drivers/rtc/rtc-max8998.c
@@ -285,7 +285,7 @@ static int max8998_rtc_probe(struct platform_device *pdev)
 			info->irq, ret);
 
 	dev_info(&pdev->dev, "RTC CHIP NAME: %s\n", pdev->id_entry->name);
-	if (pdata->rtc_delay) {
+	if (pdata && pdata->rtc_delay) {
 		info->lp3974_bug_workaround = true;
 		dev_warn(&pdev->dev, "LP3974 with RTC REGERR option."
 				" RTC updates will be extremely slow.\n");
-- 
1.8.2.1



From plagnioj at jcrosoft.com  Wed May 15 11:19:21 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 17:19:21 +0200
Subject: [PATCH v2] ARM: at91: udpate defconfigs
Message-ID: <1368631161-31488-1-git-send-email-plagnioj@jcrosoft.com>

merge 9g20 with 9260 and 9g10 with 9261 as those SoCs can run from the same
kernel even in non DT world

fix the sam9261ek to allow 9g10 and sam9261 to compile together

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/configs/at91_dt_defconfig                 |   55 ++---
 arch/arm/configs/at91rm9200_defconfig              |  218 +++-----------------
 ...am9g20_defconfig => at91sam9260_9g20_defconfig} |   67 ++++--
 arch/arm/configs/at91sam9260_defconfig             |   91 --------
 ...am9261_defconfig => at91sam9261_9g10_defconfig} |   19 +-
 arch/arm/configs/at91sam9263_defconfig             |   39 ++--
 arch/arm/configs/at91sam9g45_defconfig             |   94 +++------
 arch/arm/configs/sama5_defconfig                   |   35 +++-
 arch/arm/mach-at91/Kconfig.non_dt                  |  159 +++++++-------
 arch/arm/mach-at91/Makefile                        |    2 -
 arch/arm/mach-at91/board-sam9261ek.c               |   28 +--
 11 files changed, 268 insertions(+), 539 deletions(-)
 rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
 delete mode 100644 arch/arm/configs/at91sam9260_defconfig
 rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 047f2a4..a8800d3 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -42,6 +39,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -51,7 +51,8 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
-CONFIG_EEPROM_93CX6=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
@@ -92,7 +91,23 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_DAVICOM_PHY=y
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_RTL8187=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 CONFIG_INPUT_POLLDEV=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
@@ -112,13 +127,11 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SSB=m
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
@@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y
 CONFIG_FONT_ACORN_8x8=y
 CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
@@ -146,14 +156,9 @@ CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_FTDI_SIO=y
 CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=m
-CONFIG_USB_ATMEL_USBA=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_AT91=y
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
@@ -168,16 +173,18 @@ CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
@@ -192,7 +199,7 @@ CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=m
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=m
 CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index 4ae57a3..8b09934 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -1,10 +1,12 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
@@ -35,49 +37,37 @@ CONFIG_AT91_TIMER_HZ=100
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_AT91_CF=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
+# CONFIG_COMPACTION is not set
 CONFIG_ZBOOT_ROM_TEXT=0x10000000
 CONFIG_ZBOOT_ROM_BSS=0x20040000
 CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=m
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_BT=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
@@ -94,55 +84,21 @@ CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_TUN=m
+CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
-CONFIG_PHYLIB=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_MICREL_PHY=y
-CONFIG_PPP=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOE=m
-CONFIG_PPP_ASYNC=y
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -151,38 +107,8 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_SPI_BITBANG=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_HWMON=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83L785TS=m
+# CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91RM9200_WATCHDOG=y
@@ -194,43 +120,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_KEYSPAN=y
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_MCT_U232=y
-CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
@@ -240,84 +137,27 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_REISERFS_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=y
-CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
 CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
+CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_PCBC=y
 CONFIG_CRYPTO_SHA1=y
+CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
similarity index 67%
rename from arch/arm/configs/at91sam9g20_defconfig
rename to arch/arm/configs/at91sam9260_9g20_defconfig
index 892e828..f50c404 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -11,7 +10,15 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
+CONFIG_ARCH_AT91SAM9260=y
+CONFIG_MACH_AT91SAM9260EK=y
+CONFIG_MACH_CAM60=y
+CONFIG_MACH_SAM9_L9260=y
+CONFIG_MACH_AFEB9260=y
+CONFIG_MACH_USB_A9260=y
+CONFIG_MACH_QIL_A9260=y
+CONFIG_MACH_CPU9260=y
+CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_AT91SAM9G20EK=y
 CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_MACH_CPU9G20=y
@@ -20,10 +27,10 @@ CONFIG_MACH_PORTUXG20=y
 CONFIG_MACH_STAMP9G20=y
 CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
-CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
@@ -33,12 +40,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
@@ -46,8 +55,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
@@ -56,6 +68,8 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -63,23 +77,36 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
-CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_SERIO is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -94,12 +121,11 @@ CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -109,15 +135,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -125,3 +148,9 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_AT91_DEBUG_LL_DBGU0=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
deleted file mode 100644
index 05618eb..0000000
--- a/arch/arm/configs/at91sam9260_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_ARCH_AT91SAM9260_SAM9XE=y
-CONFIG_MACH_AT91SAM9260EK=y
-CONFIG_MACH_CAM60=y
-CONFIG_MACH_SAM9_L9260=y
-CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_USB_A9260=y
-CONFIG_MACH_QIL_A9260=y
-CONFIG_MACH_CPU9260=y
-CONFIG_MACH_FLEXIBITY=y
-CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
similarity index 91%
rename from arch/arm/configs/at91sam9261_defconfig
rename to arch/arm/configs/at91sam9261_9g10_defconfig
index c87beb9..9d35cd8 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
+CONFIG_MACH_AT91SAM9G10EK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
@@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_CFG80211=y
-CONFIG_LIB80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
@@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_ZD1201=m
 CONFIG_RTL8187=m
 CONFIG_LIBERTAS=m
@@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y
 CONFIG_SND_USB_AUDIO=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
@@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-CONFIG_FTRACE=y
 CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 36fed66b..9d72ab6 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -1,6 +1,4 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
@@ -48,9 +46,11 @@ CONFIG_IP_PIMSM_V2=y
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_IPV6=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -65,7 +65,6 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
@@ -73,23 +72,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_USB_ZD1201=m
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -98,6 +92,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -107,9 +102,9 @@ CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -124,16 +119,12 @@ CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
 CONFIG_SND_USB_AUDIO=m
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=m
@@ -145,22 +136,18 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_FUSE_FS=m
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_FTRACE=y
+CONFIG_NLS_UTF8=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 18964cd..08166cd 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -36,6 +33,9 @@ CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -45,9 +45,6 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-CONFIG_CFG80211=y
-CONFIG_LIB80211=y
-CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 CONFIG_DAVICOM_PHY=y
-CONFIG_LIBERTAS_THINFIRM=m
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_AT76C50X_USB=m
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_ATH_COMMON=m
-CONFIG_ATH9K=m
-CONFIG_CARL9170=m
-CONFIG_B43=m
-CONFIG_B43_PHY_N=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-CONFIG_RT2X00=m
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RTL8192CU=m
-CONFIG_WL1251=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX_MENU=m
-CONFIG_WL12XX=m
-CONFIG_WL12XX_SDIO=m
-CONFIG_ZD1211RW=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_KEYBOARD_QT2160=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=m
 CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
-CONFIG_FB_UDL=m
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_ATMEL_LCDC=y
+CONFIG_BACKLIGHT_ATMEL_PWM=y
 # CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_ARM is not set
 CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB is not set
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_MULTI=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_MULTI=y
 CONFIG_USB_G_MULTI_CDC=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=y
-CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
@@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_DMATEST=m
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
@@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_USER_API_HASH=m
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4d0dc3c..f6e78f8 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -26,7 +26,9 @@ CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_KEXEC=y
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -39,6 +41,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
@@ -95,7 +102,19 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_RTL8187=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ATMELMCI=y
@@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
 CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 6c24985..1a2abd8 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,15 +14,11 @@ config ARCH_AT91RM9200
 	select SOC_AT91RM9200
 
 config ARCH_AT91SAM9260
-	bool "AT91SAM9260 or AT91SAM9XE"
+	bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
 	select SOC_AT91SAM9260
 
 config ARCH_AT91SAM9261
-	bool "AT91SAM9261"
-	select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9G10
-	bool "AT91SAM9G10"
+	bool "AT91SAM9261 or AT91SAM9G10"
 	select SOC_AT91SAM9261
 
 config ARCH_AT91SAM9263
@@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL
 	bool "AT91SAM9RL"
 	select SOC_AT91SAM9RL
 
-config ARCH_AT91SAM9G20
-	bool "AT91SAM9G20"
-	select SOC_AT91SAM9260
-
 config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
 	select SOC_AT91SAM9G45
@@ -50,6 +42,14 @@ config ARCH_AT91X40
 
 endchoice
 
+config ARCH_AT91SAM9G20
+	bool
+	select ARCH_AT91SAM9260
+
+config ARCH_AT91SAM9G10
+	bool
+	select ARCH_AT91SAM9261
+
 # ----------------------------------------------------------
 
 if ARCH_AT91RM9200
@@ -207,76 +207,6 @@ config MACH_FLEXIBITY
 	  Select this if you are using Flexibity Connect board
 	  <http://www.flexibity.com>
 
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9261
-
-comment "AT91SAM9261 Board Type"
-
-config MACH_AT91SAM9261EK
-	bool "Atmel AT91SAM9261-EK Evaluation Kit"
-	select HAVE_AT91_DATAFLASH_CARD
-	help
-	  Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G10
-
-comment "AT91SAM9G10 Board Type"
-
-config MACH_AT91SAM9G10EK
-	bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-	select HAVE_AT91_DATAFLASH_CARD
-	help
-	  Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9263
-
-comment "AT91SAM9263 Board Type"
-
-config MACH_AT91SAM9263EK
-	bool "Atmel AT91SAM9263-EK Evaluation Kit"
-	select HAVE_AT91_DATAFLASH_CARD
-	help
-	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-
-config MACH_USB_A9263
-	bool "CALAO USB-A9263"
-	help
-	  Select this if you are using a Calao Systems USB-A9263.
-	  <http://www.calao-systems.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9RL
-
-comment "AT91SAM9RL Board Type"
-
-config MACH_AT91SAM9RLEK
-	bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-	help
-	  Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G20
-
 comment "AT91SAM9G20 Board Type"
 
 config MACH_AT91SAM9G20EK
@@ -341,17 +271,70 @@ config MACH_USB_A9G20
 	  Select this if you are using a Calao Systems USB-A9G20.
 	  <http://www.calao-systems.com>
 
+config MACH_SNAPPER_9260
+	bool "Bluewater Systems Snapper 9260/9G20 module"
+	help
+	  Select this if you are using the Bluewater Systems Snapper 9260 or
+	  Snapper 9G20 modules.
+	  <http://www.bluewatersys.com/>
 endif
 
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
-comment "AT91SAM9260/AT91SAM9G20 boards"
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9261
+
+comment "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+	bool "Atmel AT91SAM9261-EK Evaluation Kit"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+	bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9263
+
+comment "AT91SAM9263 Board Type"
+
+config MACH_AT91SAM9263EK
+	bool "Atmel AT91SAM9263-EK Evaluation Kit"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+
+config MACH_USB_A9263
+	bool "CALAO USB-A9263"
+	help
+	  Select this if you are using a Calao Systems USB-A9263.
+	  <http://www.calao-systems.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9RL
+
+comment "AT91SAM9RL Board Type"
+
+config MACH_AT91SAM9RLEK
+	bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+	help
+	  Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
 
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
 endif
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562d..f4a5f79 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,10 +27,8 @@ obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o
 obj-$(CONFIG_ARCH_AT91RM9200)	+= at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)	+= at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9261)	+= at91sam9261_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G10)	+= at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)	+= at91sam9g45_devices.o
 obj-$(CONFIG_ARCH_AT91X40)	+= at91x40.o at91x40_time.o
 
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 9a6618a..473546b 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {}
  */
 static struct at73c213_board_info at73c213_data = {
 	.ssc_id		= 1,
-#if defined(CONFIG_MACH_AT91SAM9261EK)
-	.shortname	= "AT91SAM9261-EK external DAC",
-#else
-	.shortname	= "AT91SAM9G10-EK external DAC",
-#endif
+	.shortname	= "AT91SAM9261/9G10-EK external DAC",
 };
 
 #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -412,9 +408,6 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
 	.default_monspecs		= &at91fb_default_stn_monspecs,
 	.atmel_lcdfb_power_control	= at91_lcdc_stn_power_control,
 	.guard_time			= 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 
 #else
@@ -468,9 +461,6 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
 	.default_monspecs		= &at91fb_default_tft_monspecs,
 	.atmel_lcdfb_power_control	= at91_lcdc_tft_power_control,
 	.guard_time			= 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 #endif
 
@@ -574,6 +564,10 @@ static void __init ek_board_init(void)
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 	at91_add_device_serial();
+
+	if (cpu_is_at91sam9g10())
+		ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
+
 	/* USB Host */
 	at91_add_device_usbh(&ek_usbh_data);
 	/* USB Device */
@@ -606,11 +600,17 @@ static void __init ek_board_init(void)
 	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
-#if defined(CONFIG_MACH_AT91SAM9261EK)
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
-#else
+	/* Maintainer: Atmel */
+	.init_time	= at91sam926x_pit_init,
+	.map_io		= at91_map_io,
+	.handle_irq	= at91_aic_handle_irq,
+	.init_early	= ek_init_early,
+	.init_irq	= at91_init_irq_default,
+	.init_machine	= ek_board_init,
+MACHINE_END
+
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
-#endif
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-- 
1.7.10.4



From b-cousson at ti.com  Wed May 15 11:23:33 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 15 May 2013 17:23:33 +0200
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
Message-ID: <5193A875.1020000@ti.com>

Hi Eduardo,

On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
> Include bandgap devices for OMAP4460 devices.
> 
> Cc: "Beno?t Cousson" <b-cousson at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-omap at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
> ---
>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
> index 2cf227c..e5bfbfe 100644
> --- a/arch/arm/boot/dts/omap4460.dtsi
> +++ b/arch/arm/boot/dts/omap4460.dtsi
> @@ -29,4 +29,13 @@
>  			     <0 55 0x4>;
>  		ti,hwmods = "debugss";
>  	};
> +
> +	bandgap {
> +		reg = <0x4a002260 0x4
> +			0x4a00232C 0x4
> +			0x4a002378 0x18>;
> +		compatible = "ti,omap4460-bandgap";
> +		interrupts = <0 126 4>; /* talert */
> +		ti,tshut-gpio = <86>;

Why do you need a custom attribute for GPIO? Cannot you use the standard
one?

Where is the gpio controller phandle?

Usually it looks like this:

	gpios = <&gpio1 8 0>;


Regards,
Benoit



From mark.rutland at arm.com  Wed May 15 11:23:56 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Wed, 15 May 2013 16:23:56 +0100
Subject: [PATCHv2 0/5] arm: arch_timer cleanups and niceties
Message-ID: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>

The following patches clean up some (harmless) fallout from the changes
in 3.9, and make the driver always use the virtual counter, eliminating
problems relating to choosing which counters to use (racy
initialisation, branches in hot paths).

The patches can also be found in my public git tree:
git://linux-arm.org/git/linux-mr.git clocks/arch-timer-cleanups

Since v1 [1]:
* Rebased to v3.10-rc1
* Fix up mach-shmobile's selection of ARCH_ARM_TIMER

Thanks,
Mark.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-March/158604.html

Marc Zyngier (2):
  ARM: hyp: initialize CNTVOFF to zero
  ARM: arch_timer: stop virtual timer when booted in HYP mode

Mark Rutland (3):
  ARM: KVM: arch_timers: zero CNTVOFF upon return to host
  clocksource: arch_timer: use virtual counters
  arm: fix up ARM_ARCH_TIMER selects

 arch/arm/include/asm/arch_timer.h    |  9 ---------
 arch/arm/kernel/hyp-stub.S           |  7 +++++++
 arch/arm/kvm/interrupts_head.S       |  4 ++++
 arch/arm/mach-exynos/Kconfig         |  2 +-
 arch/arm/mach-shmobile/Kconfig       |  4 ++--
 arch/arm/mach-tegra/Kconfig          |  2 +-
 arch/arm/mach-virt/Kconfig           |  2 +-
 arch/arm64/include/asm/arch_timer.h  | 10 ----------
 drivers/clocksource/arm_arch_timer.c | 23 +++++------------------
 include/clocksource/arm_arch_timer.h |  2 +-
 10 files changed, 22 insertions(+), 43 deletions(-)

-- 
1.8.1.1



From mark.rutland at arm.com  Wed May 15 11:23:57 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Wed, 15 May 2013 16:23:57 +0100
Subject: [PATCHv2 1/5] ARM: hyp: initialize CNTVOFF to zero
In-Reply-To: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1368631441-28434-2-git-send-email-mark.rutland@arm.com>

From: Marc Zyngier <Marc.Zyngier at arm.com>

In order to be able to use the virtual counter in a safe way,
make sure it is initialized to zero before dropping to SVC.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/kernel/hyp-stub.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 1315c4c..dbe2110 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -153,6 +153,8 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
 	mrc	p15, 4, r7, c14, c1, 0	@ CNTHCTL
 	orr	r7, r7, #3		@ PL1PCEN | PL1PCTEN
 	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
+	mov	r7, #0
+	mcrr	p15, 4, r7, r7, c14	@ CNTVOFF
 1:
 #endif
 
-- 
1.8.1.1



From mark.rutland at arm.com  Wed May 15 11:23:58 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Wed, 15 May 2013 16:23:58 +0100
Subject: [PATCHv2 2/5] ARM: KVM: arch_timers: zero CNTVOFF upon return to host
In-Reply-To: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1368631441-28434-3-git-send-email-mark.rutland@arm.com>

To use the virtual counters from the host, we need to ensure that
CNTVOFF doesn't change unexpectedly. When we change to a guest, we
replace the host's CNTVOFF, but we don't restore it when returning to
the host.

As the host sets CNTVOFF to zero, and never changes it, we can simply
zero CNTVOFF when returning to the host. This patch adds said zeroing to
the return to host path.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Marc Zyngier <marc.zyngier at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Christoffer Dall <cdall at cs.columbia.edu>
---
 arch/arm/kvm/interrupts_head.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 3c8f2f0..d43cfb5 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -497,6 +497,10 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 	add	r5, vcpu, r4
 	strd	r2, r3, [r5]
 
+	@ Ensure host CNTVCT == CNTPCT
+	mov	r2, #0
+	mcrr	p15, 4, r2, r2, c14	@ CNTVOFF
+
 1:
 #endif
 	@ Allow physical timer/counter access for the host
-- 
1.8.1.1



From mark.rutland at arm.com  Wed May 15 11:24:00 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Wed, 15 May 2013 16:24:00 +0100
Subject: [PATCHv2 4/5] arm: fix up ARM_ARCH_TIMER selects
In-Reply-To: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1368631441-28434-5-git-send-email-mark.rutland@arm.com>

In 8a4da6e: "arm: arch_timer: move core to drivers/clocksource", the
selection of ARM_ARCH_TIMER was indirected via HAVE_ARM_ARCH_TIMER,
though mach-exynos's selection of ARM_ARCH_TIMER was missed, and since
then mach-shmobile, mach-tegra, and mach-virt have begun selecting
ARM_ARCH_TIMER. This can lead to architected timer support erroneously
appearing to not be selected in menuconfig.

This patch fixes up the Kconfigs for those platforms to select
HAVE_ARM_ARCH_TIMER.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Stephen Warren <swarren at nvidia.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Marc Zyngier <marc.zyngier at arm.com>
Cc: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-exynos/Kconfig   | 2 +-
 arch/arm/mach-shmobile/Kconfig | 4 ++--
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-virt/Kconfig     | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d19edff..3c3f36a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -76,7 +76,7 @@ config SOC_EXYNOS5440
 	default y
 	depends on ARCH_EXYNOS5
 	select ARCH_HAS_OPP
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select AUTO_ZRELADDR
 	select PINCTRL
 	select PINCTRL_EXYNOS5440
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2..767a6c3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,7 +23,7 @@ config ARCH_R8A73A4
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
 	select CPU_V7
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
 
@@ -56,7 +56,7 @@ config ARCH_R8A7790
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
 	select CPU_V7
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc..65c5ae6 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -60,7 +60,7 @@ config ARCH_TEGRA_3x_SOC
 
 config ARCH_TEGRA_114_SOC
 	bool "Enable support for Tegra114 family"
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select ARM_GIC
 	select ARM_L1_CACHE_SHIFT_6
 	select CPU_FREQ_TABLE if CPU_FREQ
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
index 8958f0d..081d469 100644
--- a/arch/arm/mach-virt/Kconfig
+++ b/arch/arm/mach-virt/Kconfig
@@ -2,7 +2,7 @@ config ARCH_VIRT
 	bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select ARM_PSCI
 	select HAVE_SMP
 	select CPU_V7
-- 
1.8.1.1



From mark.rutland at arm.com  Wed May 15 11:23:59 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Wed, 15 May 2013 16:23:59 +0100
Subject: [PATCHv2 3/5] clocksource: arch_timer: use virtual counters
In-Reply-To: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1368631441-28434-4-git-send-email-mark.rutland@arm.com>

Switching between reading the virtual or physical counters is
problematic, as some core code wants a view of time before we're fully
set up. Using a function pointer and switching the source after the
first read can make time appear to go backwards, and having a check in
the read function is an unfortunate block on what we want to be a fast
path.

Instead, this patch makes us always use the virtual counters. If we're a
guest, or don't have hyp mode, we'll use the virtual timers, and as such
don't care about CNTVOFF as long as it doesn't change in such a way as
to make time travel backwards. If we do have hyp mode, and might be a
KVM host, we have to use the physical timers, and require CNTVOFF to be
zero so as to have a consistent view of time between the physical timers
and virtual counters.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
Acked-by: Marc Zyngier <marc.zyngier at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/include/asm/arch_timer.h    |  9 ---------
 arch/arm64/include/asm/arch_timer.h  | 10 ----------
 drivers/clocksource/arm_arch_timer.c | 23 +++++------------------
 include/clocksource/arm_arch_timer.h |  2 +-
 4 files changed, 6 insertions(+), 38 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7c1bfc0..accefe0 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void)
 	return val;
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-	u64 cval;
-
-	isb();
-	asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-	return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
 	u64 cval;
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index bf6ab242..d56ed11 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -110,16 +110,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
 	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-	u64 cval;
-
-	isb();
-	asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
-
-	return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
 	u64 cval;
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index a2b2541..053d846 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -186,27 +186,19 @@ u32 arch_timer_get_rate(void)
 	return arch_timer_rate;
 }
 
-/*
- * Some external users of arch_timer_read_counter (e.g. sched_clock) may try to
- * call it before it has been initialised. Rather than incur a performance
- * penalty checking for initialisation, provide a default implementation that
- * won't lead to time appearing to jump backwards.
- */
-static u64 arch_timer_read_zero(void)
+u64 arch_timer_read_counter(void)
 {
-	return 0;
+	return arch_counter_get_cntvct();
 }
 
-u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero;
-
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
-	return arch_timer_read_counter();
+	return arch_counter_get_cntvct();
 }
 
 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
 {
-	return arch_timer_read_counter();
+	return arch_counter_get_cntvct();
 }
 
 static struct clocksource clocksource_counter = {
@@ -287,7 +279,7 @@ static int __init arch_timer_register(void)
 	cyclecounter.mult = clocksource_counter.mult;
 	cyclecounter.shift = clocksource_counter.shift;
 	timecounter_init(&timecounter, &cyclecounter,
-			 arch_counter_get_cntpct());
+			 arch_counter_get_cntvct());
 
 	if (arch_timer_use_virtual) {
 		ppi = arch_timer_ppi[VIRT_PPI];
@@ -376,11 +368,6 @@ static void __init arch_timer_init(struct device_node *np)
 		}
 	}
 
-	if (arch_timer_use_virtual)
-		arch_timer_read_counter = arch_counter_get_cntvct;
-	else
-		arch_timer_read_counter = arch_counter_get_cntpct;
-
 	arch_timer_register();
 	arch_timer_arch_init();
 }
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index e6c9c4c..c463ce9 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -32,7 +32,7 @@
 #ifdef CONFIG_ARM_ARCH_TIMER
 
 extern u32 arch_timer_get_rate(void);
-extern u64 (*arch_timer_read_counter)(void);
+extern u64 arch_timer_read_counter(void);
 extern struct timecounter *arch_timer_get_timecounter(void);
 
 #else
-- 
1.8.1.1



From mark.rutland at arm.com  Wed May 15 11:24:01 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Wed, 15 May 2013 16:24:01 +0100
Subject: [PATCHv2 5/5] ARM: arch_timer: stop virtual timer when booted in HYP
 mode
In-Reply-To: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1368631441-28434-6-git-send-email-mark.rutland@arm.com>

From: Marc Zyngier <Marc.Zyngier at arm.com>

When booting the kernel, a bootloader could have left the virtual
timer ticking away, potentially generating interrupts. This could
be troublesome if the user of the virtual timer is not careful
when enabling the interrupt.

In order to avoid any surprise, stop the virtual timer from
interrupting us when booted in HYP mode, as we'll use the physical
timer in this case.

Reported-by: Giridhar Maruthy <giridhar.m at samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/kernel/hyp-stub.S | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index dbe2110..4910232 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -155,6 +155,11 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
 	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
 	mov	r7, #0
 	mcrr	p15, 4, r7, r7, c14	@ CNTVOFF
+
+	@ Disable virtual timer in case it was counting
+	mrc	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
+	bic	r7, #1			@ Clear ENABLE
+	mcr	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
 1:
 #endif
 
-- 
1.8.1.1



From will.deacon at arm.com  Wed May 15 11:28:03 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 16:28:03 +0100
Subject: dmatest regression in 3.10-rc1
Message-ID: <20130515152803.GL23869@mudshark.cambridge.arm.com>

Hello,

I've been observing a regression in the dmatest module with 3.10-rc1. It
manifests as either:

 - a spurious timeout on one or more of the channel threads
 - a complete kernel lockup (loss of console)
 - a panic (see below, noting that the callback [dmatest_callback] is
   dereferencing a NULL pointer)

If I revert 77101ce578bb ("dmatest: cancel thread immediately when asked
for") then things are rosy again, but I'm not sure if this is hiding another
problem.

I'm using 8 iterations, 8 threads per channel and a 128k buffer size,
although I've reproduced it with 1 iteration, 1 thread, default buffer size
too.

Any ideas? Some of the changes to dmatest.c since 3.9 have some fishy
looking synchronisation variables without barriers/atomic accesses, but I'm
reproducing this on a software model so I wouldn't expect too much memory
re-ordering.

Any help appreciated,

Will

--->8

[   18.911813] dmatest: thread dma0chan0-copy1 exited with status 0
[   18.911916] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[   18.911974] pgd = c0003000
[   18.912020] [00000000] *pgd=80000080004003, *pmd=00000000
[   18.912097] Internal error: Oops: 207 [#1] PREEMPT SMP ARM
[   18.912144] Modules linked in: dmatest(-)
[   18.912230] CPU: 0 PID: 651 Comm: dma2chan0-copy3 Not tainted 3.10.0-rc1+ #15
[   18.912300] task: dfac8880 ti: df37a000 task.ti: df37a000
[   18.912378] PC is at _raw_spin_lock_irqsave+0x24/0x60
[   18.912448] LR is at __wake_up+0x20/0x50
[   18.912522] pc : [<c032ec60>]    lr : [<c0044054>]    psr: a0000193
[   18.912522] sp : df37bb78  ip : 00000000  fp : df37bb9c
[   18.912616] r10: df37a000  r9 : 00000000  r8 : 00000000
[   18.912679] r7 : 00000003  r6 : 00000000  r5 : df82c000  r4 : 00000000
[   18.912749] r3 : df37a000  r2 : 00000000  r1 : 40000103  r0 : a0000113
[   18.912818] Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[   18.912893] Control: 30c5387d  Table: 9f97ec80  DAC: fffffffd
[   18.912956] Process dma2chan0-copy3 (pid: 651, stack limit = 0xdf37a240)
[   18.913020] Stack: (0xdf37bb78 to 0xdf37c000)
[   18.913093] bb60:                                                       d28de712 00000001
[   18.913207] bb80: 0000006e df836878 df82c000 00000000 df82c040 df82c000 df37bbc4 c01e92d8
[   18.913322] bba0: 00000001 c0ce3a40 00000000 80000193 dfac88b8 00002e7b df82c04c 20000113
[   18.913438] bbc0: c0ce2e9c df836878 df836878 00000080 00000000 70b93fb1 8f46af61 df82c000
[   18.913551] bbe0: df82c004 00000000 c0556508 c0585d00 00000000 df37a000 00000006 c0025304
[   18.913665] bc00: 00000001 00000018 c055c09c df37a000 c055c080 40000102 00000018 c00256e0
[   18.913782] bc20: df80c950 df0850c0 e0802000 00000000 ffff90d1 00200040 df37bcec df37a000
[   18.913895] bc40: 00000060 00000000 e0802000 dfa00cc0 00000000 df0d5c00 df37bcec c0025ae8
[   18.914013] bc60: c0556e48 c000eb38 e080200c c0562820 df37bc90 c0008560 c00444b0 c032efe4
[   18.914130] bc80: 60000113 ffffffff df37bcc4 c000de80 c0ce3a40 dfac8880 df37a000 0000221b
[   18.914244] bca0: 00000000 c0ce3a40 dfacc840 00000002 dfa00cc0 00000000 df0d5c00 df37bcec
[   18.914362] bcc0: c0557a40 df37bcd8 c00444b0 c032efe4 60000113 ffffffff c0ce3a40 df37a000
[   18.914478] bce0: c0557a40 dfac8880 df37bd8c c032db74 00000001 c002bd68 c0586a54 c0586c54
[   18.914593] bd00: df37bd00 df37bd00 6475a018 00000004 00000004 c032e458 c0557a40 c0557a40
[   18.914706] bd20: 00000000 00000008 c055c08c c0025754 c05731c0 df81c840 c0ce6680 00000000
[   18.914821] bd40: ffff90cd 00200040 c01d4a84 df37a000 0000001b 00000000 e0802000 00007317
[   18.914936] bd60: c0556e48 0000001b 00000000 df37a000 80000113 ffffffff df37bdd4 c000dea0
[   18.915052] bd80: df37a000 0001beae df37bd9c c032e458 bf001fe0 bf001e70 00000000 c000deb8
[   18.915164] bda0: df15a200 dfb4ca40 0001beae 00020000 0001c8d5 00000000 0000000b 0000000c
[   18.915279] bdc0: 00007317 deea0000 0001beae 00000000 0001c8d4 df37bde8 bf001fe0 bf001e70
[   18.915393] bde0: 80000113 ffffffff 00020000 df15a200 00000000 00014b97 0000517d 00007317
[   18.915505] be00: dfb4ca40 0001beae 00000000 bf001fe0 0001beae 00000000 00000000 00000001
[   18.915618] be20: 00000080 00020000 0001beae bf002dfc dfb4c980 00000001 bf00262c 00000000
[   18.915731] be40: 00000000 00000001 00000080 ffffffff 000000c0 0000517d df37bf64 bf001cdc
[   18.915843] be60: 00014b97 00007317 dfb4ca40 00000001 0001beae 00000000 00000000 bf000e78
[   18.915954] be80: 9eea0000 00000000 df374000 00000002 9ee8517d 00000000 00000000 00000000
[   18.916066] bea0: df37401c 00000008 df37bf20 00000010 dfac8ab8 00000010 00000000 00000008
[   18.916181] bec0: df37be80 df82e014 df37be98 0000517d df37be80 df37be90 00000001 dfb4c980
[   18.916294] bee0: 00014b97 00000001 00000001 c0564504 c0591d00 00000000 00007317 df97e340
[   18.916408] bf00: 0000517d bf002dfc dfa0ac40 00000003 df37bf44 75b7c14f 00000001 df37bf20
[   18.916521] bf20: 00040004 df37bf24 df37bf24 00000007 00000007 00000000 df37bf38 df37bf38
[   18.916634] bf40: df37bf64 df161e98 00000000 df97e340 bf000b0c 00000000 00000000 00000000
[   18.916746] bf60: 00000000 c003c1a4 dfdfdfcf 00000000 dfdfdfcf df97e340 00000000 00000000
[   18.916861] bf80: df37bf80 df37bf80 00000000 00000000 df37bf90 df37bf90 df37bfac df161e98
[   18.916971] bfa0: c003c100 00000000 00000000 c000e318 00000000 00000000 00000000 00000000
[   18.917078] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[   18.917189] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 dfdfdfcf cfdfdfdf
[   18.917318] [<c032ec60>] (_raw_spin_lock_irqsave+0x24/0x60) from [<c0044054>] (__wake_up+0x20/0x50)
[   18.917453] [<c0044054>] (__wake_up+0x20/0x50) from [<c01e92d8>] (pl330_tasklet+0x4c8/0x580)
[   18.917593] [<c01e92d8>] (pl330_tasklet+0x4c8/0x580) from [<c0025304>] (tasklet_action+0x74/0x100)
[   18.917734] [<c0025304>] (tasklet_action+0x74/0x100) from [<c00256e0>] (__do_softirq+0xe0/0x1b8)
[   18.917858] [<c00256e0>] (__do_softirq+0xe0/0x1b8) from [<c0025ae8>] (irq_exit+0x90/0xc8)
[   18.917972] [<c0025ae8>] (irq_exit+0x90/0xc8) from [<c000eb38>] (handle_IRQ+0x3c/0x94)
[   18.918089] [<c000eb38>] (handle_IRQ+0x3c/0x94) from [<c0008560>] (gic_handle_irq+0x28/0x5c)
[   18.918204] [<c0008560>] (gic_handle_irq+0x28/0x5c) from [<c000de80>] (__irq_svc+0x40/0x70)
[   18.918273] Exception stack(0xdf37bc90 to 0xdf37bcd8)
[   18.918357] bc80:                                     c0ce3a40 dfac8880 df37a000 0000221b
[   18.918470] bca0: 00000000 c0ce3a40 dfacc840 00000002 dfa00cc0 00000000 df0d5c00 df37bcec
[   18.918572] bcc0: c0557a40 df37bcd8 c00444b0 c032efe4 60000113 ffffffff
[   18.918697] [<c000de80>] (__irq_svc+0x40/0x70) from [<c032efe4>] (_raw_spin_unlock_irq+0x1c/0x44)
[   18.918831] [<c032efe4>] (_raw_spin_unlock_irq+0x1c/0x44) from [<c00444b0>] (finish_task_switch+0x54/0xdc)
[   18.918965] [<c00444b0>] (finish_task_switch+0x54/0xdc) from [<c032db74>] (__schedule+0x208/0x66c)
[   18.919097] [<c032db74>] (__schedule+0x208/0x66c) from [<c032e458>] (preempt_schedule_irq+0x40/0x64)
[   18.919116] dma2chan0-copy7: #1: No errors with src_off=0x5000 dst_off=0x5028 len=0x8d77 (0)
[   18.919292] [<c032e458>] (preempt_schedule_irq+0x40/0x64) from [<c000deb8>] (svc_preempt+0x8/0x18)
[   18.919431] [<c000deb8>] (svc_preempt+0x8/0x18) from [<bf001e70>] (dmatest_verify.isra.9+0x14/0xb4 [dmatest])
[   18.919499] unwind: Index not found bf001e70
[   18.919582] Code: e3c3303f e5931004 e2811001 e5831004 (e1923f9f)
[   18.919644] ---[ end trace f24842049530d274 ]---
[   18.919699] Kernel panic - not syncing: Fatal exception in interrupt
[   18.919754] CPU4: stopping
[   18.919822] CPU: 4 PID: 655 Comm: dma2chan0-copy7 Tainted: G      D      3.10.0-rc1+ #15
[   18.919949] [<c0013b50>] (unwind_backtrace+0x0/0xf8) from [<c0011434>] (show_stack+0x10/0x14)
[   18.920073] [<c0011434>] (show_stack+0x10/0x14) from [<c0012918>] (handle_IPI+0xf8/0x11c)
[   18.920183] [<c0012918>] (handle_IPI+0xf8/0x11c) from [<c000858c>] (gic_handle_irq+0x54/0x5c)
[   18.920299] [<c000858c>] (gic_handle_irq+0x54/0x5c) from [<c000de80>] (__irq_svc+0x40/0x70)
[   18.920369] Exception stack(0xdef23e18 to 0xdef23e60)
[   18.920442] 3e00:                                                       dfb4ce40 000106d3
[   18.920555] 3e20: defa0000 000015d2 00020000 00012292 00008a83 00000080 ffffffff 000000c0
[   18.920671] 3e40: 00008a83 def23f64 ffffff8e def23e60 bf000fb4 bf000fe8 80000113 ffffffff
[   18.920808] [<c000de80>] (__irq_svc+0x40/0x70) from [<bf000fe8>] (dmatest_func+0x4dc/0x12ec [dmatest])
[   18.920944] [<bf000fe8>] (dmatest_func+0x4dc/0x12ec [dmatest]) from [<c003c1a4>] (kthread+0xa4/0xb0)
[   18.921066] [<c003c1a4>] (kthread+0xa4/0xb0) from [<c000e318>] (ret_from_fork+0x14/0x3c)



From gregory.clement at free-electrons.com  Wed May 15 11:36:43 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 15 May 2013 17:36:43 +0200
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <20130515150402.GK23869@mudshark.cambridge.arm.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
 <51939FBC.3060705@free-electrons.com>
 <20130515150402.GK23869@mudshark.cambridge.arm.com>
Message-ID: <5193AB8B.90100@free-electrons.com>

On 05/15/2013 05:04 PM, Will Deacon wrote:
> On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
>> On 05/15/2013 04:06 PM, Will Deacon wrote:
>>> You could also try deleting both of the ALT_* lines and just putting a
>>> W(nop) in there directly.
>>
>> If I just delete the both of the ALT_* lines it no more hangs.
>> If I put a  W(nop) instead it hangs.

It also hang with a simple nop by the way

> 
> Wow. This doesn't sound good for your CPU and you might want to check with
> the Marvell guys...
> 
> Extra things you could try:
> 
> 	- Try adding a 16-bit nop instead (remove the W, build thumb-2 and
> 	  double check in your diasassembly)
> 
> 	- Try adding the W(nop) to other places in the kernel and see if you
> 	  can tickle the lock-up elsewhere.

I managed to add  W(nop) elsewhere in the kernel without getting any lock-up.

Is the fact that this nop is the first instruction of the macro could have an
influence ?


> 
> 	- Can you reproduce on the Armada XP? (since I have access to one of
> 	  those)

No on Armada XP I don't have this kind of problem even on UP.

> 
>>> Early in boot (head.S:__fixup_smp), we detect whether the CPU has the MP
>>> extensions then, if we're actually UP but the kernel has CONFIG_SMP=y, we
>>> walk over the .alt.smp.init section looking at each entry in there. The
>>> ALT_UP macro spits out an (address, instruction) pair, so in
>>> __do_fixup_smp_on_up, we store the instruction to the address for each pair,
>>> replacing the SMP instruction which sat there in the compiled image.
>>>
>>> It could be that the CPUID checks are failing on your Marvell part. Can you
>>> tell me what you have in your mpidr (mrc p15, 0, Rd, c0, c0, 5) and also
>>> your midr (mrc p15, 0, Rd, c0, c0) please?
>>
>> mpidr= 0x0
>> midr= 0x561F5811
> 
> Should be fine, but it doesn't look like the patching is the issue here.
> 
> Will
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From will.deacon at arm.com  Wed May 15 11:41:13 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 16:41:13 +0100
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <5193AB8B.90100@free-electrons.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
 <51939FBC.3060705@free-electrons.com>
 <20130515150402.GK23869@mudshark.cambridge.arm.com>
 <5193AB8B.90100@free-electrons.com>
Message-ID: <20130515154113.GM23869@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 04:36:43PM +0100, Gregory CLEMENT wrote:
> On 05/15/2013 05:04 PM, Will Deacon wrote:
> > On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
> >> On 05/15/2013 04:06 PM, Will Deacon wrote:
> >>> You could also try deleting both of the ALT_* lines and just putting a
> >>> W(nop) in there directly.
> >>
> >> If I just delete the both of the ALT_* lines it no more hangs.
> >> If I put a  W(nop) instead it hangs.
> 
> It also hang with a simple nop by the way

Ok. Have you tried adding a different instruction (mov r0, r0, for example)?

> > 
> > Wow. This doesn't sound good for your CPU and you might want to check with
> > the Marvell guys...
> > 
> > Extra things you could try:
> > 
> > 	- Try adding a 16-bit nop instead (remove the W, build thumb-2 and
> > 	  double check in your diasassembly)
> > 
> > 	- Try adding the W(nop) to other places in the kernel and see if you
> > 	  can tickle the lock-up elsewhere.
> 
> I managed to add  W(nop) elsewhere in the kernel without getting any lock-up.
> 
> Is the fact that this nop is the first instruction of the macro could have an
> influence ?

I can't think why -- the macro is just expanded inline during assembly.

> 
> > 
> > 	- Can you reproduce on the Armada XP? (since I have access to one of
> > 	  those)
> 
> No on Armada XP I don't have this kind of problem even on UP.

Is that compiling with CONFIG_SMP=n?

Will


From sachin.kamat at linaro.org  Wed May 15 12:12:53 2013
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Wed, 15 May 2013 21:42:53 +0530
Subject: [PATCH] rtc: max8998: Check for pdata presence before
 dereferencing
In-Reply-To: <1368630968-30460-1-git-send-email-t.figa@samsung.com>
References: <1368630968-30460-1-git-send-email-t.figa@samsung.com>
Message-ID: <CAK9yfHxf6EMFWz0Xg4VzrDLVzKB6WO+PYjtW12Gc+=qHs817Ng@mail.gmail.com>

CCing Andrew Morton.

On 15 May 2013 20:46, Tomasz Figa <t.figa at samsung.com> wrote:
> Currently the driver can crash with a NULL pointer dereference if no pdata
> is provided, despite of successful registration of MFD part. This patch
> fixes the problem by adding a NULL check before dereferencing the pdata
> pointer.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/rtc/rtc-max8998.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/rtc/rtc-max8998.c b/drivers/rtc/rtc-max8998.c
> index 48b6612..d5af7ba 100644
> --- a/drivers/rtc/rtc-max8998.c
> +++ b/drivers/rtc/rtc-max8998.c
> @@ -285,7 +285,7 @@ static int max8998_rtc_probe(struct platform_device *pdev)
>                         info->irq, ret);
>
>         dev_info(&pdev->dev, "RTC CHIP NAME: %s\n", pdev->id_entry->name);
> -       if (pdata->rtc_delay) {
> +       if (pdata && pdata->rtc_delay) {
>                 info->lp3974_bug_workaround = true;
>                 dev_warn(&pdev->dev, "LP3974 with RTC REGERR option."
>                                 " RTC updates will be extremely slow.\n");
> --
> 1.8.2.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
With warm regards,
Sachin


From linus.walleij at linaro.org  Wed May 15 12:17:21 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:17:21 +0200
Subject: [GIT PULL] ux500 fixes for v3.10-rc1+
Message-ID: <CACRpkdY2Pd9o+PMmabKs5Zj56GRsGtva8eQENgu8w-VjZy2hHw@mail.gmail.com>

Hi ARM SoC folks,

please pull the following ux500 fixes for the v3.10-rc series.
Brief info in the signed tag.

Yours,
Linus Walleij

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-arm-soc-v3.10-fixes

for you to fetch changes up to 74ba4ec7a2036f9dbe5fcc85c7c737222005507f:

  ARM: ux500: select REGULATOR (2013-05-15 15:54:00 +0200)

----------------------------------------------------------------
Some ux500 fixes for the v3.10-rc series:
- Fixes up the debug UART
- Fix dangerous platform data double-assignment
- Fix auxdata for the ethernet device
- Select REGULATOR to satisfy Kconfig

----------------------------------------------------------------
Emilio L??pez (1):
      ARM: ux500: select REGULATOR

Lee Jones (3):
      ARM: ux500: Remove duplicated assignment of ab8500_platdata
      ARM: ux500: Fix incorrect DEBUG UART virtual addresses
      ARM: ux500: Provide device enumeration number suffix for SMSC911x

 arch/arm/include/debug/ux500.S     | 6 +++---
 arch/arm/mach-ux500/Kconfig        | 1 +
 arch/arm/mach-ux500/board-mop500.c | 6 +++---
 arch/arm/mach-ux500/cpu-db8500.c   | 6 ++----
 arch/arm/mach-ux500/setup.h        | 2 +-
 5 files changed, 10 insertions(+), 11 deletions(-)


From swarren at wwwdotorg.org  Wed May 15 12:21:54 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 10:21:54 -0600
Subject: [PATCH] Move PCIe node to correct place
In-Reply-To: <1368626150-25395-1-git-send-email-jagarwal@nvidia.com>
References: <1368626150-25395-1-git-send-email-jagarwal@nvidia.com>
Message-ID: <5193B622.9020503@wwwdotorg.org>

On 05/15/2013 07:55 AM, Jay Agarwal wrote:
> Moving PCIe controller node to correct place so
> that it is sorted by register address in .dtsi file

Reviewed-by: Stephen Warren <swarren at nvidia.com>


From dinh.linux at gmail.com  Wed May 15 12:27:05 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Wed, 15 May 2013 11:27:05 -0500
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <51930EE0.3010007@samsung.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-5-git-send-email-dinguyen@altera.com>
 <51930EE0.3010007@samsung.com>
Message-ID: <5193B759.50600@gmail.com>

Hi,

On 05/14/2013 11:28 PM, Jaehoon Chung wrote:
> On 05/15/2013 07:52 AM, dinguyen at altera.com wrote:
>> From: Dinh Nguyen <dinguyen at altera.com>
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>> can use this define.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
>> CC: Seungwon Jeon <tgih.jun at samsung.com>
>> CC: Jaehoon Chung <jh80.chung at samsung.com>
>> CC: Arnd Bergmann <arnd at arndb.de>
>> CC: Olof Johansson <olof at lixom.net>
>> CC: Pavel Machek <pavel at denx.de>
>> CC: linux-mmc at vger.kernel.org
>> ---
>>  drivers/mmc/host/Kconfig          |    8 +++
>>  drivers/mmc/host/Makefile         |    1 +
>>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>>  drivers/mmc/host/dw_mmc-socfpga.c |  141 +++++++++++++++++++++++++++++++++++++
>>  drivers/mmc/host/dw_mmc.h         |    1 +
>>  5 files changed, 151 insertions(+), 2 deletions(-)
>>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
>>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 9ab8f8d..1be2289 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>>  
>> +config MMC_DW_SOCFPGA
> SOCFPGA? I think good that should be changed more generic.

Not sure what you mean? SOCFPGA is the name of new ARM SOCs from Altera.

>> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
>> +	depends on MMC_DW
>> +	select MMC_DW_PLTFM
>> +	help
>> +	  This selects support for Altera SoCFPGA specific extensions to the
>> +	  Synopsys DesignWare Memory Card Interface driver.
>> +
>>  config MMC_DW_PCI
>>  	tristate "Synopsys Designware MCI support on PCI bus"
>>  	depends on MMC_DW && PCI
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index cd32280..67718c1 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
>> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index f013e7e..866edef 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -31,8 +31,6 @@
>>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
>>  
>> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
>> -
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
>>  
>> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
>> new file mode 100644
>> index 0000000..7eb3163
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> @@ -0,0 +1,141 @@
>> +/*
>> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
>> + *
>> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
>> + *  Copyright (C) 2013 Altera Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Taken from dw_mmc_exynos.c
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/mmc/host.h>
>> +#include <linux/mmc/dw_mmc.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "dw_mmc.h"
>> +#include "dw_mmc-pltfm.h"
>> +
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> Is it vendor specific register offset?
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
>> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> Change more readable. ((drvsel & 0x7) << 0 | (smplsel & 0x7) << 3)?
>> +
>> +extern void __iomem *sys_manager_base_addr;
>> +
>> +/* SOCFPGA implementation specific driver private data */
>> +struct dw_mci_socfpga_priv_data {
>> +	u8	ciu_div;
>> +	u32	hs_timing;
>> +};
>> +
>> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv;
>> +	struct device *dev = host->dev;
>> +	int pwr_en;
>> +
>> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> +	if (!priv) {
>> +		dev_err(host->dev, "mem alloc failed for private data\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	host->priv = priv;
>> +
>> +	if (of_property_read_u32(dev->of_node, "pwr-en", &pwr_en)) {
>> +		dev_info(dev, "couldn't determine pwr-en, assuming pwr-en = 0\n");
>> +		pwr_en = 0;
>> +	}
>> +
>> +	/* Set PWREN bit */
>> +	mci_writel(host, PWREN, pwr_en);
> What is this setting? In dw-mmc.c, PWREN register should be set.

Ah..it was there before 3.9...I will adjust accordingly.

>> +
>> +	return 0;
>> +}
>> +
>> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	clk_disable(host->ciu_clk);
>> +	writel(priv->hs_timing, sys_manager_base_addr +
>> +		SYSMGR_SDMMCGRP_CTRL_OFFSET);
>> +	clk_enable(host->ciu_clk);
> Why do you use the clk_disable/enable at this point?

Our implementation of the controller requires us to disable the clock
when we adjust the timing parameter.

>> +
>> +	host->bus_hz /= priv->ciu_div;
> Didn't consider the "divide by zero"?

Will fix..

Thanks alot for the review.

Dinh
>> +	return 0;
>> +}
>> +
>> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
>> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> +}
>> +
>> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +	struct device_node *np = host->dev->of_node;
>> +	u32 timing[2];
>> +	u32 div = 0;
>> +	int ret;
>> +
>> +	of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
>> +	priv->ciu_div = div;
>> +
>> +	ret = of_property_read_u32_array(np,
>> +			"altr,dw-mshc-sdr-timing", timing, 2);
>> +	if (ret)
>> +		return ret;
>> +
>> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
>> +	return 0;
>> +}
>> +
>> +static const struct dw_mci_drv_data socfpga_drv_data = {
>> +	.init			= dw_mci_socfpga_priv_init,
>> +	.setup_clock		= dw_mci_socfpga_setup_clock,
>> +	.prepare_command	= dw_mci_socfpga_prepare_command,
>> +	.parse_dt		= dw_mci_socfpga_parse_dt,
>> +};
>> +
>> +static const struct of_device_id dw_mci_socfpga_match[] = {
>> +	{ .compatible = "altr,socfpga-dw-mshc",
>> +			.data = &socfpga_drv_data, },
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
>> +
>> +int dw_mci_socfpga_probe(struct platform_device *pdev)
>> +{
>> +	const struct dw_mci_drv_data *drv_data;
>> +	const struct of_device_id *match;
>> +
>> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
>> +	drv_data = match->data;
>> +	return dw_mci_pltfm_register(pdev, drv_data);
>> +}
>> +
>> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
>> +	.probe		= dw_mci_socfpga_probe,
>> +	.remove		= __exit_p(dw_mci_pltfm_remove),
>> +	.driver		= {
>> +		.name		= "dwmmc_socfpga",
>> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
>> +		.pm		= &dw_mci_pltfm_pmops,
>> +	},
>> +};
>> +
>> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
>> +
>> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:dwmmc-socfpga");
>> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
>> index 0b74189..3700cb2 100644
>> --- a/drivers/mmc/host/dw_mmc.h
>> +++ b/drivers/mmc/host/dw_mmc.h
>> @@ -111,6 +111,7 @@
>>  #define SDMMC_INT_ERROR			0xbfc2
>>  /* Command register defines */
>>  #define SDMMC_CMD_START			BIT(31)
>> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>>  #define SDMMC_CMD_UPD_CLK		BIT(21)
>>
> 


From gregory.clement at free-electrons.com  Wed May 15 12:29:03 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 15 May 2013 18:29:03 +0200
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <20130515154113.GM23869@mudshark.cambridge.arm.com>
References: <1364235581-17900-1-git-send-email-will.deacon@arm.com>
 <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
 <51939FBC.3060705@free-electrons.com>
 <20130515150402.GK23869@mudshark.cambridge.arm.com>
 <5193AB8B.90100@free-electrons.com>
 <20130515154113.GM23869@mudshark.cambridge.arm.com>
Message-ID: <5193B7CF.2020208@free-electrons.com>

On 05/15/2013 05:41 PM, Will Deacon wrote:
> On Wed, May 15, 2013 at 04:36:43PM +0100, Gregory CLEMENT wrote:
>> On 05/15/2013 05:04 PM, Will Deacon wrote:
>>> On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
>>>> On 05/15/2013 04:06 PM, Will Deacon wrote:
>>>>> You could also try deleting both of the ALT_* lines and just putting a
>>>>> W(nop) in there directly.
>>>>
>>>> If I just delete the both of the ALT_* lines it no more hangs.
>>>> If I put a  W(nop) instead it hangs.
>>
>> It also hang with a simple nop by the way
> 
> Ok. Have you tried adding a different instruction (mov r0, r0, for example)?

it hanged again :(

I also try to boot a kernel in Thumb2, it doesn't hang in the same place but the kernel
crash latter

> 
>>>
>>> Wow. This doesn't sound good for your CPU and you might want to check with
>>> the Marvell guys...
>>>
>>> Extra things you could try:
>>>
>>> 	- Try adding a 16-bit nop instead (remove the W, build thumb-2 and
>>> 	  double check in your diasassembly)
>>>
>>> 	- Try adding the W(nop) to other places in the kernel and see if you
>>> 	  can tickle the lock-up elsewhere.
>>
>> I managed to add  W(nop) elsewhere in the kernel without getting any lock-up.
>>
>> Is the fact that this nop is the first instruction of the macro could have an
>> influence ?
> 
> I can't think why -- the macro is just expanded inline during assembly.

If I put anything before the "dcache_line_size r2, r3" line the kernel hang, but
just after it's ok.
> 
>>
>>>
>>> 	- Can you reproduce on the Armada XP? (since I have access to one of
>>> 	  those)
>>
>> No on Armada XP I don't have this kind of problem even on UP.
> 
> Is that compiling with CONFIG_SMP=n?
Yes

> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linus.walleij at linaro.org  Wed May 15 12:29:51 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:29:51 +0200
Subject: [PATCH 01/39] dmaengine: ste_dma40: Separate Logical Global
 Interrupt Mask (GIM) unmasking
In-Reply-To: <1368611522-9984-2-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZJp-WRGNgzwqERVBtb_WxQGybmMjnnLTAoX66qECNh7g@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> During the initial setup of a logical channel, it is necessary to unmask
> the GIM in order to receive generated terminal count and error interrupts.
> We're separating out this required code so it will be possible to move
> the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> into the runtime_config() routine.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied to my ux500-dma40 branch.

This lacks an ACK from Vinod...

I cannot get any of this stack of patches up to ARM SoC
before I have Vinod's ACK on all hitting drivers/dma/*

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed May 15 12:33:21 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:33:21 +0200
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbWPLvPmJz_oHxFVJ9w+8XRJsVVD5v=6LyoDzpYA+JRHA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> All configuration left in d40_phy_cfg() is runtime configurable and
> there is already a call into it from d40_runtime_config(), so let's
> rely on that.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

You forgot to update the commit message, but I saw that you
fixed what I asked for so I just went in and edited the commit message
and applied it.

Yours,
Linus Walleij


From eduardo.valentin at ti.com  Wed May 15 12:36:58 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 15 May 2013 12:36:58 -0400
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <5193A875.1020000@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com>
Message-ID: <5193B9AA.7020507@ti.com>

On 15-05-2013 11:23, Benoit Cousson wrote:
> Hi Eduardo,
> 
> On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
>> Include bandgap devices for OMAP4460 devices.
>>
>> Cc: "Beno?t Cousson" <b-cousson at ti.com>
>> Cc: Tony Lindgren <tony at atomide.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: linux-omap at vger.kernel.org
>> Cc: devicetree-discuss at lists.ozlabs.org
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: linux-kernel at vger.kernel.org
>> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
>> ---
>>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
>> index 2cf227c..e5bfbfe 100644
>> --- a/arch/arm/boot/dts/omap4460.dtsi
>> +++ b/arch/arm/boot/dts/omap4460.dtsi
>> @@ -29,4 +29,13 @@
>>  			     <0 55 0x4>;
>>  		ti,hwmods = "debugss";
>>  	};
>> +
>> +	bandgap {
>> +		reg = <0x4a002260 0x4
>> +			0x4a00232C 0x4
>> +			0x4a002378 0x18>;
>> +		compatible = "ti,omap4460-bandgap";
>> +		interrupts = <0 126 4>; /* talert */
>> +		ti,tshut-gpio = <86>;



> 
> Why do you need a custom attribute for GPIO? Cannot you use the standard
> one?

I believe it was by your suggestion :-), during the first attempts to
send this driver. But could not find the thread link :-( sorry.


I guess the reasoning to mark it as a ti specific is because it will be
used as IRQ line to treat thermal shutdown (in SW).

> 
> Where is the gpio controller phandle?
> 
> Usually it looks like this:
> 
> 	gpios = <&gpio1 8 0>;
> 
> 
> Regards,
> Benoit
> 
> 
> 


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From dinh.linux at gmail.com  Wed May 15 12:40:12 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Wed, 15 May 2013 11:40:12 -0500
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <201305151525.50005.arnd@arndb.de>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <1368571955-6652-5-git-send-email-dinguyen@altera.com>
 <201305151525.50005.arnd@arndb.de>
Message-ID: <5193BA6C.2050406@gmail.com>

Hi Arnd,

Thanks for the review.

On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013, dinguyen at altera.com wrote:
>> +
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
>> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
>> +
>> +extern void __iomem *sys_manager_base_addr;
> 
> This is not acceptable, you cannot just reference external symbols
> from one driver in another, without a proper interface.
> 
> Please explain what the functionality is that you need here, then
> we can help you find the proper interface. My guess is that you
> need either the functionality provided by drivers/reset/
> or drivers/mfd/syscon.c.

Our implementation has the timing controls for the SD/MMC controller in
another custom IP block(system manager). sys_manager_base_addr was
mapped in mach-socfpga/socfpga.c. I saw the same approach with
drivers/clk(clk_mgr_base_addr), so I thought it would be ok with this
driver. Please advise on another way to do this...

> 
>> +       if (of_property_read_u32(dev->of_node, "pwr-en", &pwr_en)) {
>> +               dev_info(dev, "couldn't determine pwr-en, assuming pwr-en = 0\n");
>> +               pwr_en = 0;
>> +       }
>> +
>> +       /* Set PWREN bit */
>> +       mci_writel(host, PWREN, pwr_en);
> 
> If you add new properties, you have to document them in
> Documentations/devicetree/bindings/*.
> 
> What is the requirement for this property? Is there no way to 
> automatically power the card on/off using the normal
> dw_mci_set_ios function?

Apologies...it wasn't there in 3.8. I will fix...

Thanks,
Dinh
> 
> The rest of this patch looks ok to me.
> 
> 	Arnd
> 


From dinh.linux at gmail.com  Wed May 15 12:44:08 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Wed, 15 May 2013 11:44:08 -0500
Subject: [PATCH 1/5] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
In-Reply-To: <20130515124302.GB9066@amd.pavel.ucw.cz>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <20130515124302.GB9066@amd.pavel.ucw.cz>
Message-ID: <5193BB58.2040109@gmail.com>

Hi Pavel,

Thanks for the review...

On 05/15/2013 07:43 AM, Pavel Machek wrote:
> On Tue 2013-05-14 17:52:31, dinguyen at altera.com wrote:
>> From: Dinh Nguyen <dinguyen at altera.com>
>>
>> Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
>> CC: Arnd Bergmann <arnd at arndb.de>
>> CC: Olof Johansson <olof at lixom.net>
>> CC: Pavel Machek <pavel at denx.de>
>> CC: <linux at arm.linux.org.uk>
> 
> Looks good.
> 
> Reviewed-by: Pavel Machek <pavel at denx.de>
> 
> ...but, this patch is not enough to get ethernet to work with
> 3.10-rc1, right? I hoped that applying 1-3 of the series would get me
> ethernet, but no :-(.

Yes, this fixes a build error for socfpga_defconfig in 3.10-rc1. I'll
send a patch to enable ethernet after these patches are accepted.

Dinh


> 
> Thanks,
> 									Pavel
> 


From linus.walleij at linaro.org  Wed May 15 12:44:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:44:26 +0200
Subject: [PATCH 03/39] dmaengine: ste_dma40: Don't configure runtime
 configurable setup during allocate
In-Reply-To: <1368611522-9984-4-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbvhB=7QScU1bCN8wXr7ZOuPX9XYoCjX_a8gFSMCkbm-w@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Using the dmaengine API, allocating and configuring a channel are two
> separate actions. Here we're removing logical channel configuration from
> the channel allocating routines.

This commit message is also incorrect, but I amended it.

Besides, when I amend commit messages I make sure I really
understand what is going on so no big deal...

> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I still need Vinod's ACK on this before I send it anywhere.

Patch applied!

Yours,
Linus Walleij


From dinh.linux at gmail.com  Wed May 15 12:44:47 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Wed, 15 May 2013 11:44:47 -0500
Subject: [PATCH 1/5] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
In-Reply-To: <201305151519.08598.arnd@arndb.de>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <201305151519.08598.arnd@arndb.de>
Message-ID: <5193BB7F.8030404@gmail.com>

Hi Arnd,

On 05/15/2013 08:19 AM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013, dinguyen at altera.com wrote:
>>                 };
>>  
>> +               ethernet at ff700000 {
>> +                       phy-mode = "gmii";
>> +               };
>> +
>> +               ethernet at ff702000 {
>> +                       status = "disabled";
>> +               };
> 
> By convention, please mark the controllers as "disabled" in the main .dtsi file
> and only enable them in the board specific files when used, rather than the
> other way round.

Thanks for the review. Will fix.

Dinh
> 
> 	Arnd
> 


From dmurphy at ti.com  Wed May 15 12:46:26 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Wed, 15 May 2013 11:46:26 -0500
Subject: [PATCH v4] ARM:dts:omap4-panda: Update the LED support for the panda
 DTS
Message-ID: <1368636386-17138-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   40 +++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..2b516af 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,7 +16,7 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "pandaboard::status1";
@@ -137,6 +137,20 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_wkgpio_pins
+	>;
+
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..e6f696d 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,43 @@
 		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
 		>;
 };
+
+&leds {
+	compatible = "gpio-leds";
+	heartbeat {
+		label = "pandaboard::status1";
+		gpios = <&gpio4 14 0>;
+		linux,default-trigger = "heartbeat";
+	};
+	mmc {
+		label = "pandaboard::status2";
+		gpios = <&gpio1 8 0>;
+		linux,default-trigger = "mmc0";
+	};
+};
+
+&omap4_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_gpio_pins
+	>;
+
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
+&omap4_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_wkgpio_pins
+	>;
+
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
-- 
1.7.5.4



From linus.walleij at linaro.org  Wed May 15 12:48:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:48:12 +0200
Subject: [PATCH 04/39] ARM: ux500: Stop passing UART's platform data for
 Device Tree boots
In-Reply-To: <1368611522-9984-5-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbMVQWQpgiG+PcMUY789i+OgRObtH-toDYKdkbn9VtQ5g@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> It was required to pass DMA channel configuration information to the
> UART driver before the new DMA API was in place. Now that it is, and
> is fully compatible with Device Tree we can stop doing that.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/cpu-db8500.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
> index 38ebf2b..9b26fe2 100644
> --- a/arch/arm/mach-ux500/cpu-db8500.c
> +++ b/arch/arm/mach-ux500/cpu-db8500.c
> @@ -230,9 +230,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
>         /* Requires call-back bindings. */
>         OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
>         /* Requires DMA bindings. */
> -       OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
> -       OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
> -       OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
> +       OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
> +       OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
> +       OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
>         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
>         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
>         OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),

OK dma_request_slave_channel() is upstream in the PL011 driver,
so applied!

Yours,
Linus Walleij


From will.deacon at arm.com  Wed May 15 12:48:43 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 May 2013 17:48:43 +0100
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and
 use ALT_SMP instead
In-Reply-To: <5193B7CF.2020208@free-electrons.com>
References: <1364235581-17900-4-git-send-email-will.deacon@arm.com>
 <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
 <51939FBC.3060705@free-electrons.com>
 <20130515150402.GK23869@mudshark.cambridge.arm.com>
 <5193AB8B.90100@free-electrons.com>
 <20130515154113.GM23869@mudshark.cambridge.arm.com>
 <5193B7CF.2020208@free-electrons.com>
Message-ID: <20130515164843.GN23869@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 05:29:03PM +0100, Gregory CLEMENT wrote:
> On 05/15/2013 05:41 PM, Will Deacon wrote:
> > On Wed, May 15, 2013 at 04:36:43PM +0100, Gregory CLEMENT wrote:
> >> On 05/15/2013 05:04 PM, Will Deacon wrote:
> >>> On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
> >>>> On 05/15/2013 04:06 PM, Will Deacon wrote:
> >>>>> You could also try deleting both of the ALT_* lines and just putting a
> >>>>> W(nop) in there directly.
> >>>>
> >>>> If I just delete the both of the ALT_* lines it no more hangs.
> >>>> If I put a  W(nop) instead it hangs.
> >>
> >> It also hang with a simple nop by the way
> > 
> > Ok. Have you tried adding a different instruction (mov r0, r0, for example)?
> 
> it hanged again :(
> 
> I also try to boot a kernel in Thumb2, it doesn't hang in the same place but the kernel
> crash latter

Crikey, that's not much fun. My last idea is to try sticking an isb
instruction in there. Does that make any difference?

Can you get access to another 370 board and see if the problem reproduces
there? Is there any possibility of getting JTAG (again, perhaps on a
different board)?

Failing that, I think you need to pester the CPU guys and/or the board guys
to help you debug this.

Will


From linux at arm.linux.org.uk  Wed May 15 12:48:54 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 May 2013 17:48:54 +0100
Subject: [PATCHv2] arm: mm: Use phys_addr_t properly for ioremap functions
In-Reply-To: <201305151615.39752.arnd@arndb.de>
References: <1368560031-19367-1-git-send-email-lauraa@codeaurora.org>
 <201305151615.39752.arnd@arndb.de>
Message-ID: <20130515164854.GM18614@n2100.arm.linux.org.uk>

On Wed, May 15, 2013 at 04:15:39PM +0200, Arnd Bergmann wrote:
> On Tuesday 14 May 2013, Laura Abbott wrote:
> > Several of the ioremap functions use unsigned long in places
> > resulting in truncation if physical addresses greater than
> > 4G are passed in. Change the types of the functions and the
> > callers accordingly.
> 
> Looks good to me. I wonder a bit whether resource_size_t or phys_addr_t
> is the right type here, but they are always defined to the same type
> these days.
> 
> FWIW, x86 and tile use resource_size_t, while a couple of other architectures
> use phys_addr_t.

Maybe there's a project there for someone to remove phys_addr_t or
resource_size_t then - but I suspect Linus won't like the churn
caused by that...

So, let's just go by the one which takes less typing and save our
fingers.  phys_addr_t.


From linus.walleij at linaro.org  Wed May 15 12:50:47 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:50:47 +0200
Subject: [PATCH 05/39] ARM: ux500: Stop passing MMC's platform data for
 Device Tree boots
In-Reply-To: <1368611522-9984-6-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbOxzhgR=ugXLrSBJ_Y1rw=0mcrvtuRi=-c5v039xsPWA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> It was required to pass DMA channel configuration information to the
> MMC driver before the new DMA API was in place. Now that it is, and
> is fully compatible with Device Tree we can stop doing that.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

So since the use of dma_request_slave_channel() is not upstream,
I guess this will break DMA use (i.e slow down transfers!) on all
device tree boots?

I'd be happy to apply it once the MMCI patch is in linux-next
indicating there may just be a window in the merge period
where it falls back to IRQ mode, but I don't want to disable
DMA on DT boots for an entire kernel cycle just like that.

Not applied as of yet.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed May 15 12:54:18 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:54:18 +0200
Subject: [PATCH 07/39] dmaengine: ste_dma40: Only use addresses passed as
 configuration information
In-Reply-To: <1368611522-9984-8-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY97uS_ckSqy=Ta0SDrXrGmtDB4eL28_ZZPN5j--emr5A@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Addresses are passed in from the client's driver via the invocation of
> dmaengine_slave_config(), so there's no need to fetch them from platform
> data too, hardwired or otherwise. This is a great step forward, as it
> elevates a large burden from platform data in the way of a look-up
> table.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This should be the case even without patch 5 & 6 so patch tentatively
applied.

Waiting for Vinod's ACK on this though.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed May 15 12:56:05 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:56:05 +0200
Subject: [PATCH 08/39] dmaengine: ste_dma40: Remove redundant address
 fetching function
In-Reply-To: <1368611522-9984-9-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-9-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZpx3=8dhGaZ9xW7vXTmvhi=OVE5vFCAW66-AnwV_i=rQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Addresses are now stored in local data structures and are easy to
> obtain, thus a specialist function used to fetch them is now surplus
> to requirement.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch tentatively applied, waiting for Vinod's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed May 15 12:51:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 18:51:38 +0200
Subject: [PATCH 06/39] ARM: ux500: Move SDI (MMC) and UART devices under
 more descriptive heading
In-Reply-To: <1368611522-9984-7-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ=NJR3VRNJE2pSTJ8t1VCMq+wjH_s0NOi4AHko3no_KA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
> should be possible to remove them from the auxdata structure. However,
> after doing so the drivers fail. Common clk is still reliant on the
> dev_name() call to do device name matching, which will fail due to the
> fact that Device Tree naming differs somewhat do the more traditional
> conventions.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Cannot be applied due to dependency on 5/39.

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Wed May 15 12:57:26 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 15 May 2013 18:57:26 +0200
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <5193B9AA.7020507@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com>
Message-ID: <20130515165726.GK22508@game.jcrosoft.org>

On 12:36 Wed 15 May     , Eduardo Valentin wrote:
> On 15-05-2013 11:23, Benoit Cousson wrote:
> > Hi Eduardo,
> > 
> > On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
> >> Include bandgap devices for OMAP4460 devices.
> >>
> >> Cc: "Beno?t Cousson" <b-cousson at ti.com>
> >> Cc: Tony Lindgren <tony at atomide.com>
> >> Cc: Russell King <linux at arm.linux.org.uk>
> >> Cc: linux-omap at vger.kernel.org
> >> Cc: devicetree-discuss at lists.ozlabs.org
> >> Cc: linux-arm-kernel at lists.infradead.org
> >> Cc: linux-kernel at vger.kernel.org
> >> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
> >> ---
> >>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
> >>  1 file changed, 9 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
> >> index 2cf227c..e5bfbfe 100644
> >> --- a/arch/arm/boot/dts/omap4460.dtsi
> >> +++ b/arch/arm/boot/dts/omap4460.dtsi
> >> @@ -29,4 +29,13 @@
> >>  			     <0 55 0x4>;
> >>  		ti,hwmods = "debugss";
> >>  	};
> >> +
> >> +	bandgap {
> >> +		reg = <0x4a002260 0x4
> >> +			0x4a00232C 0x4
> >> +			0x4a002378 0x18>;
> >> +		compatible = "ti,omap4460-bandgap";
> >> +		interrupts = <0 126 4>; /* talert */
> >> +		ti,tshut-gpio = <86>;
> 
> 
> 
> > 
> > Why do you need a custom attribute for GPIO? Cannot you use the standard
> > one?
> 
> I believe it was by your suggestion :-), during the first attempts to
> send this driver. But could not find the thread link :-( sorry.
> 
> 
> I guess the reasoning to mark it as a ti specific is because it will be
> used as IRQ line to treat thermal shutdown (in SW).
so use interrup-parent
> 
> > 
> > Where is the gpio controller phandle?
> > 
> > Usually it looks like this:
> > 
> > 	gpios = <&gpio1 8 0>;
> > 
> > 
> > Regards,
> > Benoit
> > 
> > 
> > 
> 
> 



> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From linus.walleij at linaro.org  Wed May 15 13:03:10 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:03:10 +0200
Subject: [PATCH 09/39] ARM: ux500: Remove DMA address look-up table
In-Reply-To: <1368611522-9984-10-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-10-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdasU0a_T5rwvRah0VpddrOGardLQkNCMRngUdxOUnSH7A@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA addresses are now passed as part of the dmaengine API by invoking
> dmaengine_slave_config(). So there's no requirement for the DMA40
> driver to look them up in a table provided by platform data. This
> method does not fit in well using Device Tree either.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Good riddance. Patch tentatively applied.
Awaiting Vinod's ACK for include/platform_data/*.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed May 15 13:04:27 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:04:27 +0200
Subject: [PATCH 10/39] dmaengine: ste_dma40: Correct copy/paste error
In-Reply-To: <1368611522-9984-11-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-11-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbQaB9adaCb6FR3XAMMK2AtDdzKfNb0WZZ8Gm5yQBiuVw@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> 'struct stedma40_half_channel_info's header comment says that it's
> called 'struct stedma40_chan_cfg'. Let's straighten that out.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch tentatively applied waiting for Vinod's ACK.

Yours,
Linus Walleij


From nm at ti.com  Wed May 15 13:05:16 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 15 May 2013 12:05:16 -0500
Subject: [PATCH v4] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <1368636386-17138-1-git-send-email-dmurphy@ti.com>
References: <1368636386-17138-1-git-send-email-dmurphy@ti.com>
Message-ID: <20130515170516.GA6135@kahuna>

On 11:46-20130515, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
> 
> A1-A3 = gpio_wk7
> ES = gpio_110
> 
> There is no change to LED D2
> 
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
> 
> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> ---
nit: Giving patch history is a nice practise.
>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++-
>  arch/arm/boot/dts/omap4-panda-es.dts      |   40 +++++++++++++++++++++++++++++
>  2 files changed, 55 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 03bd60d..2b516af 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -16,7 +16,7 @@
>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>  	};
>  
> -	leds {
> +	leds: leds {
>  		compatible = "gpio-leds";
>  		heartbeat {
>  			label = "pandaboard::status1";
> @@ -137,6 +137,20 @@
I missed noticing this previously, Apologies on the same.
Considering that drivers/leds/leds-gpio.c has ability to handle pinctrl,
One better option might be to provide pinctrl phandle with leds -
Couple of reasons why this might be good:
a) one gets the following warning at boot:
"leds-gpio leds.8: pins are not configured from the driver"
b) you donot need to setup the pins by default at boot - it is not
mandatory for the system functionality, instead we do it *if* the driver
is enabled.
Further, optionally, all you'd have to do in panda-es.dts is the following
&led_wkgpio_pins {
		pinctrl-single,pins = <
			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
		>;
}
Similarly for gpios override for panda-es.

>  	};
>  };
>  
> +&omap4_pmx_wkup {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <
> +		&led_wkgpio_pins
> +	>;
> +
> +	led_wkgpio_pins: pinmux_leds_wkpins {
> +		pinctrl-single,pins = <
> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
>  &i2c1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&i2c1_pins>;
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..e6f696d 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,43 @@
>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>  		>;
>  };
> +
> +&leds {
> +	compatible = "gpio-leds";
> +	heartbeat {
> +		label = "pandaboard::status1";
> +		gpios = <&gpio4 14 0>;
> +		linux,default-trigger = "heartbeat";
> +	};
> +	mmc {
> +		label = "pandaboard::status2";
> +		gpios = <&gpio1 8 0>;
> +		linux,default-trigger = "mmc0";
> +	};
> +};
> +
> +&omap4_pmx_core {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <
> +		&led_gpio_pins
> +	>;
> +
> +	led_gpio_pins: gpio_led_pmx {
> +		pinctrl-single,pins = <
> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
> +&omap4_pmx_wkup {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <
> +		&led_wkgpio_pins
> +	>;
> +
> +	led_wkgpio_pins: pinmux_leds_wkpins {
> +		pinctrl-single,pins = <
> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> -- 
> 1.7.5.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Regards,
Nishanth Menon


From tony at atomide.com  Wed May 15 13:07:35 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 15 May 2013 10:07:35 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130515015212.GB3268@animalcreek.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
Message-ID: <20130515170734.GI5600@atomide.com>

* Mark A. Greer <mgreer at animalcreek.com> [130514 18:57]:
> On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
> > Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> > changed PM to not access IVA registers on omaps that don't have
> > them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
> > will stay on and block deeper idle states.
> > 
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > 
> > ---
> > 
> > Paul & Kevin, do you have better ideas for fixing this?
> > 
> > --- a/arch/arm/mach-omap2/pm34xx.c
> > +++ b/arch/arm/mach-omap2/pm34xx.c
> > @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
> >  	/* Clear any pending PRCM interrupts */
> >  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> >  
> > -	if (omap3_has_iva())
> > -		omap3_iva_idle();
> > +	/*
> > +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> > +	 */
> > +	omap3_iva_idle();
> >  
> >  	omap3_d2d_idle();
> >  }
> 
> [Kevin, Paul, some background: Tony discovered that the am3703 needs
> to have omap3_iva_idle() called even though its not supposed to have
> an IVA.]
> 
> This is potentially bad for other SoC's that don't have an IVA so I don't
> think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
> flag for the am3703 only since its the one with the bug.  Maybe something
> in id.c:omap3xxx_check_features() but I don't see any existing way to check
> for an am3703 vs. other am37xx SoCs.  Any ideas?
> 
> Another option, I suppose, is a dts entry but I don't like that at all.

It seems that iva2_pwrdm is there for all omap3 even if OMAP3_HAS_IVA
flag is unset. And if that's the case, iva2 clocks still need to be idled
in all cases.

It's possible that not all steps in omap3_iva_idle() are needed though.
I can debug further to see which part of the omap3_iva_idle() are needed.

Mark, do you have some omap3 with no iva (other than am3703) to test the
idle states with?

Regards,

Tony


From linus.walleij at linaro.org  Wed May 15 13:07:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:07:58 +0200
Subject: [PATCH 12/39] crypto: ux500/hash - Prepare clock before enabling
 it
In-Reply-To: <1368611522-9984-13-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-13-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYdf1j+V516CigFeGKv1B+Mf4mZk8g3ZwYAwa=rDP=7vg@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> If we fail to prepare the ux500-hash clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This patch seems to be totally independent of the other stuff
in the patch series, and it even seems like an -rc fix to me
(I don't think the crypto device works without this).

This should go into the crypto tree?

Else please convince Herbert to give his ACK on this
before I apply it.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed May 15 13:09:57 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:09:57 +0200
Subject: [PATCH 13/39] crypto: ux500/hash - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1368611522-9984-14-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-14-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ+XExToF8DaC+iiMrpf-s01Hc6W5q40n=WnfJ4qtKStw@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I think I need to stop applying here and wait for an ACK from
Herbert on everything hitting drivers/crypto.

If I get Vinod's ACK for the previous patches I can send an
initial pull request on that and then follow up with the rest.

Yours,
Linus Walleij


From arnd at arndb.de  Wed May 15 13:11:23 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 May 2013 19:11:23 +0200
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <5193BA6C.2050406@gmail.com>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <201305151525.50005.arnd@arndb.de> <5193BA6C.2050406@gmail.com>
Message-ID: <5336483.qTzEF54m2z@wuerfel>

On Wednesday 15 May 2013 11:40:12 Dinh Nguyen wrote:
> On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
> > On Wednesday 15 May 2013, dinguyen at altera.com wrote:
> >> +
> >> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET         0x108
> >> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK        0x7
> >> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)              \
> >> +    ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> >> +
> >> +extern void __iomem *sys_manager_base_addr;
> > 
> > This is not acceptable, you cannot just reference external symbols
> > from one driver in another, without a proper interface.
> > 
> > Please explain what the functionality is that you need here, then
> > we can help you find the proper interface. My guess is that you
> > need either the functionality provided by drivers/reset/
> > or drivers/mfd/syscon.c.
> 
> Our implementation has the timing controls for the SD/MMC controller in
> another custom IP block(system manager). sys_manager_base_addr was
> mapped in mach-socfpga/socfpga.c. I saw the same approach with
> drivers/clk(clk_mgr_base_addr), so I thought it would be ok with this
> driver. Please advise on another way to do this...

The clock code is tied more more closely to the platform code, so I
was turning a blind eye on that one, under the assumption that it
was only used there.

	Arnd


From linus.walleij at linaro.org  Wed May 15 13:11:46 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:11:46 +0200
Subject: [PATCH 15/39] crypto: ux500/cryp - Prepare clock before enabling
 it
In-Reply-To: <1368611522-9984-16-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-16-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY_9=OO_E9pFLuihVmE4YvLmydk_b+jsGr_R0sELt0UvA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This patch also looks like -rc series stuff for the crypto tree.

BTW: these two clk_prepare_enable() patches are
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From davidb at codeaurora.org  Wed May 15 13:12:06 2013
From: davidb at codeaurora.org (David Brown)
Date: Wed, 15 May 2013 10:12:06 -0700
Subject: [PATCH 14/20] ARM: msm: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-15-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-15-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130515171206.GA3799@codeaurora.org>

On Tue, May 14, 2013 at 05:38:47PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for msm as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/mach-msm/board-dt-8660.c | 2 --
>  arch/arm/mach-msm/board-dt-8960.c | 2 --
>  2 files changed, 4 deletions(-)

I've replaced the patch in my msm-cleanup tree with this one.  I'll
push this out once the support goes into the arm soc tree.

David

-- 
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From linus.walleij at linaro.org  Wed May 15 13:05:44 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:05:44 +0200
Subject: [PATCH 11/39] ARM: ux500: Remove unnecessary attributes from DMA
 channel request pdata
In-Reply-To: <1368611522-9984-12-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-12-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYLwywT0R7zyd2d=1bH+FajV=yopHrvTMpYRYF+4zkQDQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA data width and packet size information is only required at channel
> configuration time. Any information passed from platform data is passed
> directly to the DMA40 driver to use during channel allocation, but these
> pieces of information are subsequently ignored by the driver, so we may
> as well remove them.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied.

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Wed May 15 13:16:11 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 May 2013 18:16:11 +0100
Subject: [PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE
 and use ALT_SMP instead
In-Reply-To: <20130515164843.GN23869@mudshark.cambridge.arm.com>
References: <51938B3D.2070508@free-electrons.com>
 <20130515134117.GH23869@mudshark.cambridge.arm.com>
 <51939386.7010709@free-electrons.com>
 <20130515140607.GI23869@mudshark.cambridge.arm.com>
 <51939FBC.3060705@free-electrons.com>
 <20130515150402.GK23869@mudshark.cambridge.arm.com>
 <5193AB8B.90100@free-electrons.com>
 <20130515154113.GM23869@mudshark.cambridge.arm.com>
 <5193B7CF.2020208@free-electrons.com>
 <20130515164843.GN23869@mudshark.cambridge.arm.com>
Message-ID: <20130515171611.GN18614@n2100.arm.linux.org.uk>

On Wed, May 15, 2013 at 05:48:43PM +0100, Will Deacon wrote:
> On Wed, May 15, 2013 at 05:29:03PM +0100, Gregory CLEMENT wrote:
> > On 05/15/2013 05:41 PM, Will Deacon wrote:
> > > On Wed, May 15, 2013 at 04:36:43PM +0100, Gregory CLEMENT wrote:
> > >> On 05/15/2013 05:04 PM, Will Deacon wrote:
> > >>> On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
> > >>>> On 05/15/2013 04:06 PM, Will Deacon wrote:
> > >>>>> You could also try deleting both of the ALT_* lines and just putting a
> > >>>>> W(nop) in there directly.
> > >>>>
> > >>>> If I just delete the both of the ALT_* lines it no more hangs.
> > >>>> If I put a  W(nop) instead it hangs.
> > >>
> > >> It also hang with a simple nop by the way
> > > 
> > > Ok. Have you tried adding a different instruction (mov r0, r0, for example)?
> > 
> > it hanged again :(
> > 
> > I also try to boot a kernel in Thumb2, it doesn't hang in the same place but the kernel
> > crash latter
> 
> Crikey, that's not much fun. My last idea is to try sticking an isb
> instruction in there. Does that make any difference?
> 
> Can you get access to another 370 board and see if the problem reproduces
> there? Is there any possibility of getting JTAG (again, perhaps on a
> different board)?
> 
> Failing that, I think you need to pester the CPU guys and/or the board guys
> to help you debug this.

I've just tried it on the cubox (Dove, Armada 510) which has the xor
engines enabled in the config.  I see in the boot messages:

mv_xor mv_xor.0: Marvell XOR driver
mv_xor mv_xor.0: Marvell XOR: ( xor cpy )
mv_xor mv_xor.0: Marvell XOR: ( xor fill cpy )
mv_xor mv_xor.1: Marvell XOR driver
mv_xor mv_xor.1: Marvell XOR: ( xor cpy )
mv_xor mv_xor.1: Marvell XOR: ( xor fill cpy )

and /proc/interrupts shows that the interrupts have fired:

 39:          2  orion_irq  mv_xor.0
 40:          2  orion_irq  mv_xor.0
 42:          2  orion_irq  mv_xor.1
 43:          2  orion_irq  mv_xor.1

on each boot.  So I assume that they're doing this self-test.

Anyway, I've added the 'nop' to cpu_v7_dcache_clean_area, and it boots
just fine.  The CPU is:

CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c53c7d


From linus.walleij at linaro.org  Wed May 15 13:18:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 19:18:01 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I guess this stuff is dependent on the stuff Fabio has recently sent to
Felipe for the ux500 musb DMA so these musb patches should
primarily go through his tree.

It seems like the later changes to the platform code
(arch/arm/mach-ux500) may be sufficiently orthogonal
so it can be done out-of-order?

I can't merge any of this without Felipes ACKs in any
case.

Yours,
Linus Walleij


From jagarwal at nvidia.com  Wed May 15 13:28:22 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 15 May 2013 22:58:22 +0530
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <518A8596.7070702@wwwdotorg.org>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
Message-ID: <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>


> On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> > - Enable PCIe controller on Cardhu
> > - Only port 2 is connected on this board
> > - Add regulators required for Tegra30
> > - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> > - and should be applied on top of this.
> 
> > diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
> > b/arch/arm/boot/dts/tegra30-cardhu.dtsi
> 
> > +	pcie-controller {
> > +		status = "okay";
> > +		pex-clk-supply = <&pex_hvdd_3v3_reg>;
> > +		vdd-supply = <&ldo1_reg>;
> > +		avdd-supply = <&ldo2_reg>;
> > +
> > +		pci at 3,0 {
> > +			status = "okay";
> > +		};
> > +	};
> 
> So, if I apply this series, I do see the PCIe bridge and Ethernet device get
> enumerated, but I don't see the USB3 controller get enumerated. I believe
> that is a PCIe device behind the same bridge on the same Tegra PCIe port.
> Shouldn't this device show up?
[>]  I have also reproduced this problem. I see somehow no non-prefetchable memory is assigned to any of pcie devices.
Probably that is the reason for USB3 (pci 0000:04:00.0) not getting enumerated since it uses only non-prefetchable memory.


From linus.walleij at linaro.org  Wed May 15 14:38:05 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 20:38:05 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305141551.24375.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
 <CACRpkda-wQyo8aYxbW9RJNcR3Kwe2w5AhaAuUHfaxBksa_Pm2A@mail.gmail.com>
 <201305141551.24375.heiko@sntech.de>
Message-ID: <CACRpkdY1s7u9Xjzkb+AdFY1xEO1PQOp1ZFPf4r5qPL-=WPkvNQ@mail.gmail.com>

On Tue, May 14, 2013 at 3:51 PM, Heiko St?bner <heiko at sntech.de> wrote:
> Am Dienstag, 14. Mai 2013, 14:47:19 schrieb Linus Walleij:
>> On Sat, May 11, 2013 at 1:31 PM, Heiko St?bner <heiko at sntech.de> wrote:
>> > Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
>> > with numerous virtual channels being mapped to a lot less physical ones.
>> > The driver therefore borrows a lot from the amba-pl08x driver in this
>> > regard. Functionality-wise the driver gains a memcpy ability in addition
>> > to the slave_sg one.
>> >
>> > The driver currently only supports the "newer" SoCs which can use any
>> > physical channel for any dma slave. Support for the older SoCs where
>> > each channel only supports a subset of possible dma slaves will have to
>> > be added later.
>> >
>> > Tested on a s3c2416-based board, memcpy using the dmatest module and
>> > slave_sg partially using the spi-s3c64xx driver.
>> >
>> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
>>
>> So have I understood correctly if I assume that *some* S3C
>> variants, i.e. this: arch/arm/mach-s3c64xx/dma.c
>> have a vanilla, unmodified, or just slightly modified
>> PL08x block, while this DMAC is something probably based on
>> the PL08x where some ASIC engineer has had a good time hacking
>> around in the VHDL code to meet some feature requirements.
>> Correct? Or plausible guess?
>
> You're guess is at good as mine :-) . The public s3c64xx (ARM11 based)
> documentation says that it is using s PL080 as dma controller while the
> s3c24xx (ARM9 based) SoCs have this one, which doesn't come with any label in
> the manuals.
> Similar to the s3c64xx using a vic, while the s3c24xx uses something
> homegrown.
>
> The relationship description was more based on the concepts used, i.e. the
> virtual channel concept and general handling of dma transfers feel somehow
> similar - as I said these are my first steps into this, so I still need to
> understand a lot.

OK then, a separate driver seems required, will look a bit closer at
the patch as such.

Yours,
Linus Walleij


From linux at prisktech.co.nz  Wed May 15 14:52:03 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 16 May 2013 06:52:03 +1200
Subject: [PATCH 20/20] ARM: vt8500: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-21-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-21-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <5193D953.5040202@prisktech.co.nz>

On 15/05/13 03:38, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for vt8500 as well.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>   arch/arm/mach-vt8500/vt8500.c | 2 --
>   1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
> index 1dd281e..70a5ac9 100644
> --- a/arch/arm/mach-vt8500/vt8500.c
> +++ b/arch/arm/mach-vt8500/vt8500.c
> @@ -20,7 +20,6 @@
>   
>   #include <linux/clocksource.h>
>   #include <linux/io.h>
> -#include <linux/irqchip.h>
>   #include <linux/pm.h>
>   
>   #include <asm/mach-types.h>
> @@ -178,7 +177,6 @@ static const char * const vt8500_dt_compat[] = {
>   DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
>   	.dt_compat	= vt8500_dt_compat,
>   	.map_io		= vt8500_map_io,
> -	.init_irq	= irqchip_init,
>   	.init_machine	= vt8500_init,
>   	.init_time	= clocksource_of_init,
>   	.restart	= vt8500_restart,
I don't have any plans to touch this driver, so please send direct to 
arm-soc as Arnd
requested.

Acked-by: Tony Prisk <linux at prisktech.co.nz>

Regards
Tony Prisk


From linus.walleij at linaro.org  Wed May 15 14:53:32 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 20:53:32 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305111331.25405.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
Message-ID: <CACRpkdaT195McX9NeccJYpmWbuYK-AZUTHr9AXKHnJdkf+Qzuw@mail.gmail.com>

On Sat, May 11, 2013 at 1:31 PM, Heiko St?bner <heiko at sntech.de> wrote:

> This adds a new driver to support the s3c24xx dma using the dmaengine
> and make the old one in mach-s3c24xx obsolete in the long run.
>
> Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> with numerous virtual channels being mapped to a lot less physical ones.
> The driver therefore borrows a lot from the amba-pl08x driver in this
> regard. Functionality-wise the driver gains a memcpy ability in addition
> to the slave_sg one.
>
> The driver currently only supports the "newer" SoCs which can use any
> physical channel for any dma slave. Support for the older SoCs where
> each channel only supports a subset of possible dma slaves will have to
> be added later.
>
> Tested on a s3c2416-based board, memcpy using the dmatest module and
> slave_sg partially using the spi-s3c64xx driver.
>
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
(...)
> +static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan *s3cchan)
> +{
> +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> +       struct s3c24xx_txd *txd = s3cchan->at;
> +       u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
> +
> +       switch (txd->dcon & DCON_DSZ_MASK) {
> +       case DCON_DSZ_BYTE:
> +               return tc;
> +       case DCON_DSZ_HALFWORD:
> +               return tc * 2;
> +       case DCON_DSZ_WORD:
> +               return tc * 4;
> +       default:
> +               break;
> +       }
> +
> +       BUG();

Isn't that a bit nasty. This macro should be used with care and we
should recover if possible. dev_err()?

> +/*
> + * Set the initial DMA register values.
> + * Put them into the hardware and start the transfer.
> + */
> +static void s3c24xx_dma_start_next_txd(struct s3c24xx_dma_chan *s3cchan)
> +{
> +       struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
> +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> +       struct virt_dma_desc *vd = vchan_next_desc(&s3cchan->vc);
> +       struct s3c24xx_txd *txd = to_s3c24xx_txd(&vd->tx);
> +       u32 dcon = txd->dcon;
> +       u32 val;
> +
> +       list_del(&txd->vd.node);
> +
> +       s3cchan->at = txd;
> +
> +       /* Wait for channel inactive */
> +       while (s3c24xx_dma_phy_busy(phy))
> +               cpu_relax();
> +
> +       /* transfer-size and -count from len and width */
> +       switch (txd->width) {
> +       case 1:
> +               dcon |= DCON_DSZ_BYTE | txd->len;
> +               break;
> +       case 2:
> +               dcon |= DCON_DSZ_HALFWORD | (txd->len / 2);
> +               break;
> +       case 4:
> +               dcon |= DCON_DSZ_WORD | (txd->len / 4);
> +               break;
> +       }
> +
> +       if (s3cchan->slave) {
> +               if (s3cdma->sdata->has_reqsel) {
> +                       int reqsel = s3cdma->pdata->reqsel_map[s3cchan->id];
> +                       writel((reqsel << 1) | DMAREQSEL_HW,
> +                              phy->base + DMAREQSEL);
> +               } else {
> +                       dev_err(&s3cdma->pdev->dev, "non-reqsel unsupported\n");
> +                       return;
> +                       dcon |= DCON_HWTRIG;
> +               }
> +       } else {
> +               if (s3cdma->sdata->has_reqsel) {
> +                       writel(0, phy->base + DMAREQSEL);
> +               } else {
> +                       dev_err(&s3cdma->pdev->dev, "non-reqsel unsupported\n");
> +                       return;
> +               }
> +       }
> +
> +       writel(txd->src_addr, phy->base + DISRC);
> +       writel(txd->disrcc, phy->base + DISRCC);
> +       writel(txd->dst_addr, phy->base + DIDST);
> +       writel(txd->didstc, phy->base + DIDSTC);
> +
> +       writel(dcon, phy->base + DCON);
> +
> +       val = readl(phy->base + DMASKTRIG);
> +       val &= ~DMASKTRIG_STOP;
> +       val |= DMASKTRIG_ON;
> +       writel(val, phy->base + DMASKTRIG);
> +
> +       /* trigger the dma operation for memcpy transfers */
> +       if (!s3cchan->slave) {
> +               val = readl(phy->base + DMASKTRIG);
> +               val |= DMASKTRIG_SWTRIG;
> +               writel(val, phy->base + DMASKTRIG);
> +       }
> +}

Since you have a few readl() and writel() in potentially
time-critical code, consider using readl_relaxed() and
writel_relaxed().

> +static irqreturn_t s3c24xx_dma_irq(int irq, void *data)
> +{
> +       struct s3c24xx_dma_phy *phy = data;
> +       struct s3c24xx_dma_chan *s3cchan = phy->serving;
> +       struct s3c24xx_txd *txd;
> +
> +       dev_dbg(&phy->host->pdev->dev, "interrupt on channel %d\n", phy->id);
> +
> +       if (!s3cchan) {
> +               dev_err(&phy->host->pdev->dev, "interrupt on unused channel %d\n",
> +                       phy->id);
> +               return IRQ_NONE;
> +       }
> +
> +       spin_lock(&s3cchan->vc.lock);
> +       txd = s3cchan->at;
> +       if (txd) {
> +               s3cchan->at = NULL;
> +               vchan_cookie_complete(&txd->vd);
> +
> +               /*
> +                * And start the next descriptor (if any),
> +                * otherwise free this channel.
> +                */
> +               if (vchan_next_desc(&s3cchan->vc))
> +                       s3c24xx_dma_start_next_txd(s3cchan);
> +               else
> +                       s3c24xx_dma_phy_free(s3cchan);
> +       }
> +       spin_unlock(&s3cchan->vc.lock);
> +
> +       return IRQ_HANDLED;
> +}

OK so one IRQ per channel. Is there really no status
register to check or flag to clear on these IRQs?

Apart from these smallish things it looks good to me:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From dinh.linux at gmail.com  Wed May 15 15:18:51 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Wed, 15 May 2013 14:18:51 -0500
Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <5336483.qTzEF54m2z@wuerfel>
References: <1368571955-6652-1-git-send-email-dinguyen@altera.com>
 <201305151525.50005.arnd@arndb.de> <5193BA6C.2050406@gmail.com>
 <5336483.qTzEF54m2z@wuerfel>
Message-ID: <5193DF9B.8030504@gmail.com>

Hi Arnd,

On 05/15/2013 12:11 PM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013 11:40:12 Dinh Nguyen wrote:
>> On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
>>> On Wednesday 15 May 2013, dinguyen at altera.com wrote:
>>>> +
>>>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET         0x108
>>>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK        0x7
>>>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)              \
>>>> +    ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
>>>> +
>>>> +extern void __iomem *sys_manager_base_addr;
>>>
>>> This is not acceptable, you cannot just reference external symbols
>>> from one driver in another, without a proper interface.
>>>
>>> Please explain what the functionality is that you need here, then
>>> we can help you find the proper interface. My guess is that you
>>> need either the functionality provided by drivers/reset/
>>> or drivers/mfd/syscon.c.
>>
>> Our implementation has the timing controls for the SD/MMC controller in
>> another custom IP block(system manager). sys_manager_base_addr was
>> mapped in mach-socfpga/socfpga.c. I saw the same approach with
>> drivers/clk(clk_mgr_base_addr), so I thought it would be ok with this
>> driver. Please advise on another way to do this...
> 
> The clock code is tied more more closely to the platform code, so I
> was turning a blind eye on that one, under the assumption that it
> was only used there.

I think I can use the syscon interface for this. Thanks for the pointer.
I kinda thought that these dw_mmc-<platform> is platform specific
enough, but I will go the syscon route.

Dinh
> 
> 	Arnd
> 


From ulf.hansson at linaro.org  Wed May 15 15:24:48 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 15 May 2013 21:24:48 +0200
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
Message-ID: <CAPDyKFpZ6-O-zSyBVgGGFL4W+d=-k-qaXimUS12fgC=9TkUNVA@mail.gmail.com>

On 1 May 2013 06:42, Saravana Kannan <skannan at codeaurora.org> wrote:
> Without this patch, the following race conditions are possible.
>
> Race condition 1:
> * clk-A has two parents - clk-X and clk-Y.
> * All three are disabled and clk-X is current parent.
> * Thread A: clk_set_parent(clk-A, clk-Y).
> * Thread A: <snip execution flow>
> * Thread A: Grabs enable lock.
> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
> * Thread A: Updates clk-A SW parent to clk-Y
> * Thread A: Releases enable lock.
> * Thread B: clk_enable(clk-A).
> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.
>
> clk-A is now enabled in software, but not clocking in hardware since the
> hardware parent is still clk-X.
>
> The only way to avoid race conditions between clk_set_parent() and
> clk_enable/disable() is to ensure that clk_enable/disable() calls don't
> require changes to hardware enable state between changes to software clock
> topology and hardware clock topology.
>
> There are options to achieve the above:
> 1. Grab the enable lock before changing software/hardware topology and
>    release it afterwards.
> 2. Keep the clock enabled for the duration of software/hardware topology
>    change so that any additional enable/disable calls don't try to change
>    the hardware state. Once the topology change is complete, the clock can
>    be put back in its original enable state.
>
> Option (1) is not an acceptable solution since the set_parent() ops might
> need to sleep.
>
> Therefore, this patch implements option (2).
>
> This patch doesn't violate any API semantics. clk_disable() doesn't
> guarantee that the clock is actually disabled. So, no clients of a clock
> can assume that a clock is disabled after their last call to clk_disable().
> So, enabling the clock during a parent change is not a violation of any API
> semantics.
>
> This also has the nice side effect of simplifying the error handling code.
>
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> ---
> It's been a while since I submitted a patch. So, apologies if I'm cc'ing
> people who no longer care about the state of the common clock framework.
>
>  drivers/clk/clk.c |   72 +++++++++++++++++++++++-----------------------------
>  1 files changed, 32 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 934cfd1..fe4055f 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1377,67 +1377,59 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
>         unsigned long flags;
>         int ret = 0;
>         struct clk *old_parent = clk->parent;
> -       bool migrated_enable = false;
>
> -       /* migrate prepare */
> -       if (clk->prepare_count)
> +       /*
> +        * Migrate prepare state between parents and prevent race with
> +        * clk_enable().
> +        *
> +        * If the clock is not prepared, then a race with
> +        * clk_enable/disable() is impossible since we already have the
> +        * prepare lock (future calls to clk_enable() need to be preceded by
> +        * a clk_prepare()).
> +        *
> +        * If the clock is prepared, migrate the prepared state to the new
> +        * parent and also protect against a race with clk_enable() by
> +        * forcing the clock and the new parent on.  This ensures that all
> +        * future calls to clk_enable() are practically NOPs with respect to
> +        * hardware and software states.
> +        */

Maybe an additional note about that since CLK_SET_PARENT_GATE is a
prerequisite for doing migration of "prepare", we also interpreted
this flags as it is acceptable to enable the clock(s) in this context.

> +       if (clk->prepare_count) {
>                 __clk_prepare(parent);
> -
> -       flags = clk_enable_lock();
> -
> -       /* migrate enable */
> -       if (clk->enable_count) {
> -               __clk_enable(parent);
> -               migrated_enable = true;
> +               clk_enable(parent);
> +               clk_enable(clk);
>         }
>
>         /* update the clk tree topology */
> +       flags = clk_enable_lock();
>         clk_reparent(clk, parent);
> -
>         clk_enable_unlock(flags);
>
>         /* change clock input source */
>         if (parent && clk->ops->set_parent)
>                 ret = clk->ops->set_parent(clk->hw, p_index);
> -
>         if (ret) {
> -               /*
> -                * The error handling is tricky due to that we need to release
> -                * the spinlock while issuing the .set_parent callback. This
> -                * means the new parent might have been enabled/disabled in
> -                * between, which must be considered when doing rollback.
> -                */
> -               flags = clk_enable_lock();
>
> +               flags = clk_enable_lock();
>                 clk_reparent(clk, old_parent);
> -
> -               if (migrated_enable && clk->enable_count) {
> -                       __clk_disable(parent);
> -               } else if (migrated_enable && (clk->enable_count == 0)) {
> -                       __clk_disable(old_parent);
> -               } else if (!migrated_enable && clk->enable_count) {
> -                       __clk_disable(parent);
> -                       __clk_enable(old_parent);
> -               }
> -

Really good, that we can remove this awkward error handling!

>                 clk_enable_unlock(flags);
>
> -               if (clk->prepare_count)
> +               if (clk->prepare_count) {
> +                       clk_disable(clk);
> +                       clk_disable(parent);
>                         __clk_unprepare(parent);
> -
> +               }
>                 return ret;
>         }
>
> -       /* clean up enable for old parent if migration was done */
> -       if (migrated_enable) {
> -               flags = clk_enable_lock();
> -               __clk_disable(old_parent);
> -               clk_enable_unlock(flags);
> -       }
> -
> -       /* clean up prepare for old parent if migration was done */
> -       if (clk->prepare_count)
> +       /*
> +        * Finish the migration of prepare state and undo the changes done
> +        * for preventing a race with clk_enable().
> +        */
> +       if (clk->prepare_count) {
> +               clk_disable(clk);
> +               clk_disable(old_parent);
>                 __clk_unprepare(old_parent);
> +       }
>
>         /* update debugfs with new clk tree topology */
>         clk_debug_reparent(clk, parent);
> --
> 1.7.8.3
>
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation

Looks good! Thanks for having another round to fixup this kind of
tricky code. :-)

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From linus.walleij at linaro.org  Wed May 15 15:35:17 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 21:35:17 +0200
Subject: [PATCH] ARM: ux500: update MSP1 pinctrl defintions
In-Reply-To: <1368004193-21213-1-git-send-email-fabio.baltieri@linaro.org>
References: <1368004193-21213-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <CACRpkdZj6r3=fo=72PDshHbL7oHxb6H6uGeGvRyb2+uMjoAvUg@mail.gmail.com>

On Wed, May 8, 2013 at 11:09 AM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:

> Update MSP1 pinctrl definitions in mop500_family_pinmap by removing
> sleep state and setting default ones as pin hogs, as those are used by
> both ux500-msp-i2s.1 and ux500-msp-i2s.3.
>
> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>

Applied to my ux500-pinctrl branch.

I need to refresh the entire pinctrl setup anyway, so will make
big changes in this file, and need to keep it in my tree.

Yours,
Linus Walleij


From sboyd at codeaurora.org  Wed May 15 15:38:12 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 15 May 2013 12:38:12 -0700
Subject: [PATCH] ARM: avoid mis-detecting some V7 cores in the decompressor
In-Reply-To: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
References: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <5193E424.9090605@codeaurora.org>

On 05/08/13 14:47, Stephen Boyd wrote:
> From: Brian Swetland <swetland at google.com>
>
> Currently v7 CPUs with an MIDR that has no bits set in the range
> [16:12] will be detected as old ARM CPUs with no caches and so
> the cache will never be turned on during decompression. ARM's
> Cortex chips have an 0xC in the range [16:12] so they never match
> this entry, but Qualcomm's Scorpion and Krait processors never
> set these bits to anything besides 0 so they always match.
>
> Skip this entry if we've compiled in support for v7 CPUs. This
> allows kernel decompression to happen nearly instantly instead of
> taking over 20 seconds.
>
> Signed-off-by: Brian Swetland <swetland at google.com>
> [sboyd: Clarified and extended commit text]
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---

Ping?

>  arch/arm/boot/compressed/head.S | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index fe4d9c3..a236190 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -805,6 +805,8 @@ call_cache_fn:	adr	r12, proc_types
>  		.align	2
>  		.type	proc_types,#object
>  proc_types:
> +#if !defined(CONFIG_CPU_V7)
> +		/* This collides with some V7 IDs, preventing correct detection */
>  		.word	0x00000000		@ old ARM ID
>  		.word	0x0000f000
>  		mov	pc, lr
> @@ -813,6 +815,7 @@ proc_types:
>   THUMB(		nop				)
>  		mov	pc, lr
>   THUMB(		nop				)
> +#endif
>  
>  		.word	0x41007000		@ ARM7/710
>  		.word	0xfff8fe00


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From gmbnomis at gmail.com  Wed May 15 15:42:29 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Wed, 15 May 2013 21:42:29 +0200
Subject: [PATCH V2 00/10] mmc_of_parse() adaptations, DT support for
 Sheevaplugs
In-Reply-To: <20130514162652.GA13801@schnuecks.de>
References: <1368479941-10084-1-git-send-email-gmbnomis@gmail.com>
 <Pine.LNX.4.64.1305140819520.32151@axis700.grange>
 <20130514162652.GA13801@schnuecks.de>
Message-ID: <20130515194229.GA27459@schnuecks.de>

On Tue, May 14, 2013 at 06:26:52PM +0200, Simon Baatz wrote:
> On Tue, May 14, 2013 at 08:37:47AM +0200, Guennadi Liakhovetski wrote:
> > On Mon, 13 May 2013, Simon Baatz wrote:
> > 
> > > While adding DT support for the Sheevaplugs by Globalscale Technologies
> > > (Kirkwood), it turned out that the DT binding of mvsdio lacked features to
> > > properly support the hardware (active high/low of CD and WP pins could not
> > > be described in DT).
> > > 
> > > This is standard functionality provided by the mmc_of_parse() helper
> > > function.  However, mmc_of_parse() may allocate GPIO lines.  If the
> > > allocation fails, it outputs an error, but does not return an error to its
> > > caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.
> > 
> > Thanks for the patches. In principle I'm fine either way. It is a policy 
> > decision IMHO. E.g. consider a situation. You have a DT with an SD-card 
> > slot, where card-detection is performed by a GPIO. OTOH the same pin is 
> > used on some other (optional) interface on the same board. If that other 
> > competing interface is unused, the driver isn't loaded, you can use the 
> > GPIO for card-detection. However, if that other interface is used, your 
> > attempt to get the card-detect pin will fail, but you still can use the 
> > interface in polling mode. No, I don't think this is a good example of 
> > hardware design :) User experience would depend on driver probing order, 
> > but in principle it is imaginable. So, with the current mmc_of_parse() 
> > you're more tolerant. You get a warning in the log, but the interface 
> > might still be usable. And if you're surprised why your write protection 
> > status hasn't been properly detected - just look in the log.
> 
> Yes, there is value in both ways. As should be clear by now, I prefer
> being more strict here :-).  But in the end, it is a policy decision
> as you say.

I realized that I missed one use case: There are platforms on which a
driver may load earlier than the GPIO driver.  In this case,
EPROBE_DEFER can be used to retry the probe later.  Actually, mmci.c
is an example of such a driver.

Thus, when calling of_get_named_gpio_flags() in mmc_of_parse(), we
need to check for EPROBE_DEFER and return that to the caller. I will
update the patch accordingly.

- Simon


From linus.walleij at linaro.org  Wed May 15 15:41:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 May 2013 21:41:01 +0200
Subject: [RFC 6/8] ARM:stih41x: Add STiH416 SOC support
In-Reply-To: <1368022318-2380-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <1368022318-2380-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <CACRpkdZ6pdjJe5e7FdZPS-nCgRY3MGh3aewB36KJM7z76O-NQQ@mail.gmail.com>

On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
<srinivas.kandagatla at st.com> wrote:

> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>
> The STiH416 is advanced HD AVC processor with 3D graphics acceleration
> and 1.2-GHz ARM Cortex-A9 SMP CPU.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> CC: Stephen Gallimore <stephen.gallimore at st.com>
> CC: Stuart Menefy <stuart.menefy at st.com>

(...)

This stuff is looking really good.

> +++ b/arch/arm/boot/dts/stih416.dtsi
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (C) 2012 STMicroelectronics Limited.
> + * Author: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
> + */
> +#include "stih41x.dtsi"
> +#include "stih416-clock.dtsi"
> +#include "stih416-pinctrl.dtsi"

Nice layering here!

> diff --git a/arch/arm/boot/dts/stih416.h b/arch/arm/boot/dts/stih416.h
> new file mode 100644
> index 0000000..2e27792
> --- /dev/null
> +++ b/arch/arm/boot/dts/stih416.h

I've seen that people start to put these into:
include/dt-bindings/

With one include per driver subsystem. I suggest you follow
this pattern.

Yours,
Linus Walleij


From fabio.baltieri at linaro.org  Wed May 15 16:14:39 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Wed, 15 May 2013 22:14:39 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
Message-ID: <20130515201439.GA10141@balto.lan>

Hello Linus,

On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > For all ux500 based platforms the maximum number of end-points are used.
> > Move this knowledge into the driver so we can relinquish the burden from
> > platform data. This also removes quite a bit of complexity from the driver
> > and will aid us when we come to enable the driver for Device Tree.
> >
> > Cc: Felipe Balbi <balbi at ti.com>
> > Cc: linux-usb at vger.kernel.org
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> I guess this stuff is dependent on the stuff Fabio has recently sent to
> Felipe for the ux500 musb DMA so these musb patches should
> primarily go through his tree.

Not really, I only sent some coding style fix for the dma driver, as
almost all of my work was in the usb phy files.  I also checked my
latest series against Lee's tree and the two seems to merge without any
conflict, so as far as I'm concerned it's really up to you and Felipe.

Fabio

> It seems like the later changes to the platform code
> (arch/arm/mach-ux500) may be sufficiently orthogonal
> so it can be done out-of-order?
> 
> I can't merge any of this without Felipes ACKs in any
> case.
> 
> Yours,
> Linus Walleij
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

-- 
Fabio Baltieri


From sboyd at codeaurora.org  Wed May 15 16:25:23 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 15 May 2013 13:25:23 -0700
Subject: [PATCH v3 1/4] clk: abstract parent cache
In-Reply-To: <1368625263-23136-2-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
 <1368625263-23136-2-git-send-email-james.hogan@imgtec.com>
Message-ID: <5193EF33.9000903@codeaurora.org>

On 05/15/13 06:41, James Hogan wrote:
> Abstract access to the clock parent cache by defining
> clk_get_parent_by_index(clk, index). This allows access to parent
> clocks from clock drivers.
>
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org

Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Wed May 15 16:25:24 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 15 May 2013 13:25:24 -0700
Subject: [PATCH v3 2/4] clk: add support for clock reparent on set_rate
In-Reply-To: <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
 <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>
Message-ID: <5193EF34.7070800@codeaurora.org>

On 05/15/13 06:41, James Hogan wrote:
> Add core support to allow clock implementations to select the best
> parent clock when rounding a rate, e.g. the one which can provide the
> closest clock rate to that requested. This is by way of adding a new
> clock op, determine_rate(), which is like round_rate() but has an extra
> parameter to allow the clock implementation to optionally select a
> different parent clock. The core then takes care of reparenting the
> clock when setting the rate.
>
> The parent change takes place with the help of two new private data
> members. struct clk::new_parent specifies a clock's new parent (NULL
> indicates no change), and struct clk::new_child specifies a clock's new
> child (whose new_parent member points back to it). The purpose of these
> are to allow correct walking of the future tree for notifications prior
> to actually reparenting any clocks, specifically to skip child clocks
> who are being reparented to another clock (they will be notified via the
> new parent), and to include any new child clock. These pointers are set
> by clk_calc_subtree(), and the new_child pointer gets cleared when a
> child is actually reparented to avoid duplicate POST_RATE_CHANGE
> notifications.
>
> Each place where round_rate() is called, determine_rate is checked first
> and called in preference, passing NULL to the new parent argument if not
> needed (e.g. in __clk_round_rate).

That's annoying. Even if we don't care about the pointer in
clk_round_rate(), this requires the ops to check for NULL before
assigning the pointer. Why not just pass an unused pointer that the ops
can assign all the time?

>  This restructures a few of the call
> sites to simplify the logic into if/else blocks.
>
> A new __clk_set_parent_no_recalc() is created similar to
> clk_set_parent() but without calling __clk_recalc_rates(). This is for
> clk_change_rate() to use, where rate recalculation and notifications are
> already handled.
>
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org

With the above change you can add

Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From robherring2 at gmail.com  Wed May 15 16:30:44 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 15 May 2013 15:30:44 -0500
Subject: ux500 breaking multi-platform kernels
Message-ID: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>

Lee, Linus,

There are some initcalls on ux500 that are not properly
conditionalized. The first is in ux500_l2x0_init and here is a fix:

diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index f58615b..e066d32 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -39,10 +39,10 @@ static int __init ux500_l2x0_init(void)
 {
        u32 aux_val = 0x3e000000;

-       if (cpu_is_u8500_family() || cpu_is_ux540_family())
-               l2x0_base = __io_address(U8500_L2CC_BASE);
-       else
-               ux500_unknown_soc();
+       if (!(cpu_is_u8500_family() || cpu_is_ux540_family()))
+               return -ENODEV;
+
+       l2x0_base = __io_address(U8500_L2CC_BASE);

        /* Unlock before init */
        ux500_l2x0_unlock();


Here is the second problem with cpuidle driver:

[    4.514645] Unable to handle kernel NULL pointer dereference at
virtual address 000000fc
[    4.522729] pgd = c0004000
[    4.525429] [000000fc] *pgd=00000000
[    4.529009] Internal error: Oops: 5 [#1] SMP ARM
[    4.533620] Modules linked in:
[    4.536679] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W
3.10.0-rc1-00013-g5d170cd-dirty #527
[    4.545893] task: ed888000 ti: ed884000 task.ti: ed884000
[    4.551297] PC is at config_wakeups+0x6c/0x14c
[    4.555740] LR is at db8500_prcmu_enable_wakeups+0x64/0x7c
[    4.561223] pc : [<c06f4948>]    lr : [<c06f64f4>]    psr: 20000193
[    4.561223] sp : ed885ec8  ip : ed885ef8  fp : ed885ef4
[    4.572693] r10: c2d69494  r9 : 00000000  r8 : c31d92bc
[    4.577911] r7 : 00028881  r6 : 00000000  r5 : c31d92bc  r4 : 00000000
[    4.584431] r3 : 00000000  r2 : 00000000  r1 : 00000000  r0 : 60000113
[    4.590954] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[    4.598342] Control: 10c53c7d  Table: 0000404a  DAC: 00000017
[    4.604082] Process swapper/0 (pid: 1, stack limit = 0xed884240)
[    4.610083] Stack: (0xed885ec8 to 0xed886000)
[    4.614436] 5ec0:                   00000000 04019494 c31d92bc
00020081 60000113 c3137440
[    4.622611] 5ee0: 00000000 c2d69494 ed885f14 ed885ef8 c06f64f4
c06f48e8 ed884000 00000006
[    4.630786] 5f00: c2d69488 c2c9abdc ed885f24 ed885f18 c2c9abf0
c06f649c ed885f5c ed885f28
[    4.638960] 5f20: c0008a78 c2c9abe8 00000be1 c2a527f4 ed885f5c
00000006 c2d69484 00000006
[    4.647134] 5f40: c2d69488 c2df9efc c3137440 00000be1 ed885f94
ed885f60 c2c71a98 c00089bc
[    4.655307] 5f60: 00000006 00000006 c2c711ac c010ed98 00000000
c1c95000 00000000 00000000
[    4.663479] 5f80: 00000000 00000000 ed885fac ed885f98 c1c95018
c2c718f8 00000000 00000000
[    4.671651] 5fa0: 00000000 ed885fb0 c000ed98 c1c9500c 00000000
00000000 00000000 00000000
[    4.679824] 5fc0: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[    4.687997] 5fe0: 00000000 00000000 00000000 00000000 00000013
00000000 00000000 00000000
[    4.696183] [<c06f4948>] (config_wakeups+0x6c/0x14c) from
[<c06f64f4>] (db8500_prcmu_enable_wakeups+0x64/0x7c)
[    4.706189] [<c06f64f4>] (db8500_prcmu_enable_wakeups+0x64/0x7c)
from [<c2c9abf0>] (ux500_idle_init+0x14/0x2c)
[    4.716195] [<c2c9abf0>] (ux500_idle_init+0x14/0x2c) from
[<c0008a78>] (do_one_initcall+0xc8/0x184)
[    4.725247] [<c0008a78>] (do_one_initcall+0xc8/0x184) from
[<c2c71a98>] (kernel_init_freeable+0x1ac/0x284)
[    4.734906] [<c2c71a98>] (kernel_init_freeable+0x1ac/0x284) from
[<c1c95018>] (kernel_init+0x18/0xf4)
[    4.744128] [<c1c95018>] (kernel_init+0x18/0xf4) from [<c000ed98>]
(ret_from_fork+0x14/0x20)
[    4.752565] Code: ea000001 e59f50dc e1a08005 e5953054 (e59320fc)
[    4.758656] ---[ end trace 47a577e4e96d6f0b ]---
[    4.763269] Kernel panic - not syncing: Fatal exception


From heiko at sntech.de  Wed May 15 16:31:52 2013
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Wed, 15 May 2013 22:31:52 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <CACRpkdaT195McX9NeccJYpmWbuYK-AZUTHr9AXKHnJdkf+Qzuw@mail.gmail.com>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
 <CACRpkdaT195McX9NeccJYpmWbuYK-AZUTHr9AXKHnJdkf+Qzuw@mail.gmail.com>
Message-ID: <201305152231.52423.heiko@sntech.de>

Am Mittwoch, 15. Mai 2013, 20:53:32 schrieb Linus Walleij:
> On Sat, May 11, 2013 at 1:31 PM, Heiko St?bner <heiko at sntech.de> wrote:
> > This adds a new driver to support the s3c24xx dma using the dmaengine
> > and make the old one in mach-s3c24xx obsolete in the long run.
> > 
> > Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> > with numerous virtual channels being mapped to a lot less physical ones.
> > The driver therefore borrows a lot from the amba-pl08x driver in this
> > regard. Functionality-wise the driver gains a memcpy ability in addition
> > to the slave_sg one.
> > 
> > The driver currently only supports the "newer" SoCs which can use any
> > physical channel for any dma slave. Support for the older SoCs where
> > each channel only supports a subset of possible dma slaves will have to
> > be added later.
> > 
> > Tested on a s3c2416-based board, memcpy using the dmatest module and
> > slave_sg partially using the spi-s3c64xx driver.
> > 
> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> 
> (...)
> 
> > +static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan *s3cchan)
> > +{
> > +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> > +       struct s3c24xx_txd *txd = s3cchan->at;
> > +       u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
> > +
> > +       switch (txd->dcon & DCON_DSZ_MASK) {
> > +       case DCON_DSZ_BYTE:
> > +               return tc;
> > +       case DCON_DSZ_HALFWORD:
> > +               return tc * 2;
> > +       case DCON_DSZ_WORD:
> > +               return tc * 4;
> > +       default:
> > +               break;
> > +       }
> > +
> > +       BUG();
> 
> Isn't that a bit nasty. This macro should be used with care and we
> should recover if possible. dev_err()?

runtime_config already denies any settings not in the 1,2 or 4bytes range - 
the default-part should therefore never be reached. So if any other value 
magically appears in the register and triggers the default-part, something is 
seriously wrong. So my guess is, the BUG might be appropriate.

On the other hand the whole default+BUG part could also simply go away, for 
the same reasons.


> > +/*
> > + * Set the initial DMA register values.
> > + * Put them into the hardware and start the transfer.
> > + */
> > +static void s3c24xx_dma_start_next_txd(struct s3c24xx_dma_chan *s3cchan)
> > +{
> > +       struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
> > +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> > +       struct virt_dma_desc *vd = vchan_next_desc(&s3cchan->vc);
> > +       struct s3c24xx_txd *txd = to_s3c24xx_txd(&vd->tx);
> > +       u32 dcon = txd->dcon;
> > +       u32 val;
> > +
> > +       list_del(&txd->vd.node);
> > +
> > +       s3cchan->at = txd;
> > +
> > +       /* Wait for channel inactive */
> > +       while (s3c24xx_dma_phy_busy(phy))
> > +               cpu_relax();
> > +
> > +       /* transfer-size and -count from len and width */
> > +       switch (txd->width) {
> > +       case 1:
> > +               dcon |= DCON_DSZ_BYTE | txd->len;
> > +               break;
> > +       case 2:
> > +               dcon |= DCON_DSZ_HALFWORD | (txd->len / 2);
> > +               break;
> > +       case 4:
> > +               dcon |= DCON_DSZ_WORD | (txd->len / 4);
> > +               break;
> > +       }
> > +
> > +       if (s3cchan->slave) {
> > +               if (s3cdma->sdata->has_reqsel) {
> > +                       int reqsel =
> > s3cdma->pdata->reqsel_map[s3cchan->id]; +                      
> > writel((reqsel << 1) | DMAREQSEL_HW,
> > +                              phy->base + DMAREQSEL);
> > +               } else {
> > +                       dev_err(&s3cdma->pdev->dev, "non-reqsel
> > unsupported\n"); +                       return;
> > +                       dcon |= DCON_HWTRIG;
> > +               }
> > +       } else {
> > +               if (s3cdma->sdata->has_reqsel) {
> > +                       writel(0, phy->base + DMAREQSEL);
> > +               } else {
> > +                       dev_err(&s3cdma->pdev->dev, "non-reqsel
> > unsupported\n"); +                       return;
> > +               }
> > +       }
> > +
> > +       writel(txd->src_addr, phy->base + DISRC);
> > +       writel(txd->disrcc, phy->base + DISRCC);
> > +       writel(txd->dst_addr, phy->base + DIDST);
> > +       writel(txd->didstc, phy->base + DIDSTC);
> > +
> > +       writel(dcon, phy->base + DCON);
> > +
> > +       val = readl(phy->base + DMASKTRIG);
> > +       val &= ~DMASKTRIG_STOP;
> > +       val |= DMASKTRIG_ON;
> > +       writel(val, phy->base + DMASKTRIG);
> > +
> > +       /* trigger the dma operation for memcpy transfers */
> > +       if (!s3cchan->slave) {
> > +               val = readl(phy->base + DMASKTRIG);
> > +               val |= DMASKTRIG_SWTRIG;
> > +               writel(val, phy->base + DMASKTRIG);
> > +       }
> > +}
> 
> Since you have a few readl() and writel() in potentially
> time-critical code, consider using readl_relaxed() and
> writel_relaxed().

You're right of course.

If I understand the writel semantics and the thread from you from 2011 [0] 
correctly, only the writel to DMASKTRIG mustn't be relaxed to make sure the 
settings registers are written to before, so like:

       writel_relaxed(txd->src_addr, phy->base + DISRC);
       writel_relaxed(txd->disrcc, phy->base + DISRCC);
       writel_relaxed(txd->dst_addr, phy->base + DIDST);
       writel_relaxed(txd->didstc, phy->base + DIDSTC);
       writel_relaxed(dcon, phy->base + DCON);

       val = readl_relaxed(phy->base + DMASKTRIG);
       val &= ~DMASKTRIG_STOP;
       val |= DMASKTRIG_ON;
       writel(val, phy->base + DMASKTRIG);


And note to self: check if the memcpy-speciality can move into the first 
DMASKTRIG write.

> > +static irqreturn_t s3c24xx_dma_irq(int irq, void *data)
> > +{
> > +       struct s3c24xx_dma_phy *phy = data;
> > +       struct s3c24xx_dma_chan *s3cchan = phy->serving;
> > +       struct s3c24xx_txd *txd;
> > +
> > +       dev_dbg(&phy->host->pdev->dev, "interrupt on channel %d\n",
> > phy->id); +
> > +       if (!s3cchan) {
> > +               dev_err(&phy->host->pdev->dev, "interrupt on unused
> > channel %d\n", +                       phy->id);
> > +               return IRQ_NONE;
> > +       }
> > +
> > +       spin_lock(&s3cchan->vc.lock);
> > +       txd = s3cchan->at;
> > +       if (txd) {
> > +               s3cchan->at = NULL;
> > +               vchan_cookie_complete(&txd->vd);
> > +
> > +               /*
> > +                * And start the next descriptor (if any),
> > +                * otherwise free this channel.
> > +                */
> > +               if (vchan_next_desc(&s3cchan->vc))
> > +                       s3c24xx_dma_start_next_txd(s3cchan);
> > +               else
> > +                       s3c24xx_dma_phy_free(s3cchan);
> > +       }
> > +       spin_unlock(&s3cchan->vc.lock);
> > +
> > +       return IRQ_HANDLED;
> > +}
> 
> OK so one IRQ per channel. Is there really no status
> register to check or flag to clear on these IRQs?

Nope there are none. The only status you get from the controller is busy/non-
busy and remaining transfers for the transaction - the DSTAT register in the 
code. And not listed in the code the current memory addresses (source and 
destination) in use. There are no other registers at all.

And the irq itself only triggers when all transfers of the transaction are 
done (transfer_count is 0).


> Apart from these smallish things it looks good to me:
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

really? Cool.
Part of me was expecting tomatoes or other vegetables to be thrown ;-) .


Thanks for looking thru the driver.
Heiko


[0] http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626


From ocean_ieee at yahoo.it  Wed May 15 17:01:55 2013
From: ocean_ieee at yahoo.it (ocean)
Date: Wed, 15 May 2013 23:01:55 +0200
Subject: SIGSEGV changing pc register (help for my master thesis on
 ARM/linux kernel)
In-Reply-To: <51928313.4010902@yahoo.it>
References: <51928313.4010902@yahoo.it>
Message-ID: <5193F7C3.6080209@yahoo.it>

for those who could be interested in solved, i was missing this
fundamental piece of information:

http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/

best regards,
ocean


From sylvester.nawrocki at gmail.com  Wed May 15 17:20:08 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Wed, 15 May 2013 23:20:08 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305152231.52423.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
 <CACRpkdaT195McX9NeccJYpmWbuYK-AZUTHr9AXKHnJdkf+Qzuw@mail.gmail.com>
 <201305152231.52423.heiko@sntech.de>
Message-ID: <5193FC08.5040002@gmail.com>

On 05/15/2013 10:31 PM, Heiko St?bner wrote:
>>> +       BUG();
>> >
>> >  Isn't that a bit nasty. This macro should be used with care and we
>> >  should recover if possible. dev_err()?
>
> runtime_config already denies any settings not in the 1,2 or 4bytes range -
> the default-part should therefore never be reached. So if any other value
> magically appears in the register and triggers the default-part, something is
> seriously wrong. So my guess is, the BUG might be appropriate.
>
> On the other hand the whole default+BUG part could also simply go away, for
> the same reasons.

IMHO BUG() is not needed at all. As Linus suggested dev_err() is such case
or WARN_ON() would be more appropriate. This has been discussed in the past
extensively, not sure if you are aware of the other Linus' opinion on
BUG()/BUG_ON() proliferation: https://lkml.org/lkml/2012/9/27/461

Regards,
Sylwester


From mturquette at linaro.org  Wed May 15 17:41:54 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 15 May 2013 14:41:54 -0700
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe
 clocks on Armada 370
In-Reply-To: <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130515214154.12127.73539@quantum>

Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> The Armada 370 has two gatable clocks for each PCIe interface, and we
> want both of them to be enabled. We therefore make one of the two
> clocks a child of the other, as we did for the sataX and sataXlnk
> clocks on Armada XP.
> 

Ack for patches #5 and #6.  Do you want me to take them?

Regards,
Mike

> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> ---
>  drivers/clk/mvebu/clk-gating-ctrl.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
> index ebf141d..b35785a 100644
> --- a/drivers/clk/mvebu/clk-gating-ctrl.c
> +++ b/drivers/clk/mvebu/clk-gating-ctrl.c
> @@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
>         { "pex1_en", NULL,  2 },
>         { "ge1", NULL, 3 },
>         { "ge0", NULL, 4 },
> -       { "pex0", NULL, 5 },
> -       { "pex1", NULL, 9 },
> +       { "pex0", "pex0_en", 5 },
> +       { "pex1", "pex1_en", 9 },
>         { "sata0", NULL, 15 },
>         { "sdio", NULL, 17 },
>         { "tdm", NULL, 25 },
> -- 
> 1.7.9.5


From heiko at sntech.de  Wed May 15 17:48:31 2013
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Wed, 15 May 2013 23:48:31 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <5193FC08.5040002@gmail.com>
References: <201305111330.05046.heiko@sntech.de>
 <201305152231.52423.heiko@sntech.de> <5193FC08.5040002@gmail.com>
Message-ID: <201305152348.32171.heiko@sntech.de>

Am Mittwoch, 15. Mai 2013, 23:20:08 schrieb Sylwester Nawrocki:
> On 05/15/2013 10:31 PM, Heiko St?bner wrote:
> >>> +       BUG();
> >>> 
> >> >  Isn't that a bit nasty. This macro should be used with care and we
> >> >  should recover if possible. dev_err()?
> > 
> > runtime_config already denies any settings not in the 1,2 or 4bytes range
> > - the default-part should therefore never be reached. So if any other
> > value magically appears in the register and triggers the default-part,
> > something is seriously wrong. So my guess is, the BUG might be
> > appropriate.
> > 
> > On the other hand the whole default+BUG part could also simply go away,
> > for the same reasons.
> 
> IMHO BUG() is not needed at all. As Linus suggested dev_err() is such case
> or WARN_ON() would be more appropriate. This has been discussed in the past
> extensively, not sure if you are aware of the other Linus' opinion on
> BUG()/BUG_ON() proliferation: https://lkml.org/lkml/2012/9/27/461

Very interesting read and I'll keep this in mind in the future. What about the 
other option ... i.e. simply getting rid of the whole "error handling", as the 
other code paths should already make sure that only valid values get written 
into the register.

Can the value change in the register somehow on its own without kernel 
intervention, or does this not happen?


Thanks
Heiko


From mgreer at animalcreek.com  Wed May 15 17:50:28 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Wed, 15 May 2013 14:50:28 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130515170734.GI5600@atomide.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
Message-ID: <20130515215028.GA11883@animalcreek.com>

On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
> * Mark A. Greer <mgreer at animalcreek.com> [130514 18:57]:
> > On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
> > > Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> > > changed PM to not access IVA registers on omaps that don't have
> > > them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
> > > will stay on and block deeper idle states.
> > > 
> > > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > > 
> > > ---
> > > 
> > > Paul & Kevin, do you have better ideas for fixing this?
> > > 
> > > --- a/arch/arm/mach-omap2/pm34xx.c
> > > +++ b/arch/arm/mach-omap2/pm34xx.c
> > > @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
> > >  	/* Clear any pending PRCM interrupts */
> > >  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> > >  
> > > -	if (omap3_has_iva())
> > > -		omap3_iva_idle();
> > > +	/*
> > > +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> > > +	 */
> > > +	omap3_iva_idle();
> > >  
> > >  	omap3_d2d_idle();
> > >  }
> > 
> > [Kevin, Paul, some background: Tony discovered that the am3703 needs
> > to have omap3_iva_idle() called even though its not supposed to have
> > an IVA.]
> > 
> > This is potentially bad for other SoC's that don't have an IVA so I don't
> > think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
> > flag for the am3703 only since its the one with the bug.  Maybe something
> > in id.c:omap3xxx_check_features() but I don't see any existing way to check
> > for an am3703 vs. other am37xx SoCs.  Any ideas?
> > 
> > Another option, I suppose, is a dts entry but I don't like that at all.
> 
> It seems that iva2_pwrdm is there for all omap3 even if OMAP3_HAS_IVA
> flag is unset. And if that's the case, iva2 clocks still need to be idled
> in all cases.

Ahh, this takes us to the "Great TI Docs Mystery" :) -- its basically
impossible to tell because despite what their docs may say, the hardware
can be quite different.  I'm not sure how to proceed other than trial &
error with as many different SoCs as we can find.

> It's possible that not all steps in omap3_iva_idle() are needed though.
> I can debug further to see which part of the omap3_iva_idle() are needed.
> 
> Mark, do you have some omap3 with no iva (other than am3703) to test the
> idle states with?

I have an am35xx which isn't supposed to have an IVA so I can test with it
(although, I'm not sure how well the kernel works on the am35xx these days).

I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
comes up, see what I can figure out.

Mark
--


From sergei.shtylyov at cogentembedded.com  Wed May 15 17:58:07 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 01:58:07 +0400
Subject: [PATCH v4 2/3] ARM: shmobile: Marzen: add VIN and ADV7180 support
In-Reply-To: <201305160153.29827.sergei.shtylyov@cogentembedded.com>
References: <201305160153.29827.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305160158.08239.sergei.shtylyov@cogentembedded.com>

From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

Add ADV7180 platform devices on the Marzen board, configure VIN1/3 pins, and
register VIN1/3 devices with the ADV7180 specific platform data.

Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
[Sergei: removed superfluous tabulation and inserted empty lines in the  macro
definition, updated the copyrights, annotated VIN platform data as '__initdata']
Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
Changes since version 3:
- changed the VIN platform device names to be R8A7779 specific;

Changes since version 2:
- annotated 'vin_platform_data' as '__initdata' since they're kmemdup()'ed while
  registering the platform devices anyway.

Changes since the original posting:
- used a macro to define the camera platform devices;
- updated the copyrights;
- refreshed the patch.

 arch/arm/mach-shmobile/board-marzen.c |   44 +++++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

Index: renesas/arch/arm/mach-shmobile/board-marzen.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/board-marzen.c
+++ renesas/arch/arm/mach-shmobile/board-marzen.c
@@ -1,8 +1,9 @@
 /*
  * marzen board support
  *
- * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013  Renesas Solutions Corp.
  * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -37,6 +38,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+#include <media/soc_camera.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -178,12 +180,40 @@ static struct platform_device leds_devic
 	},
 };
 
+static struct rcar_vin_platform_data vin_platform_data __initdata = {
+	.flags	= RCAR_VIN_BT656,
+};
+
+#define MARZEN_CAMERA(idx)					\
+static struct i2c_board_info camera##idx##_info = {		\
+	I2C_BOARD_INFO("adv7180", 0x20 + (idx)),		\
+};								\
+								\
+static struct soc_camera_link iclink##idx##_adv7180 = {		\
+	.bus_id		= 1 + 2 * (idx),			\
+	.i2c_adapter_id	= 0,					\
+	.board_info	= &camera##idx##_info,			\
+};								\
+								\
+static struct platform_device camera##idx##_device = {		\
+	.name	= "soc-camera-pdrv",				\
+	.id	= idx,						\
+	.dev	= {						\
+		.platform_data	= &iclink##idx##_adv7180,	\
+	},							\
+};
+
+MARZEN_CAMERA(0);
+MARZEN_CAMERA(1);
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
 	&sdhi0_device,
 	&thermal_device,
 	&hspi_device,
 	&leds_device,
+	&camera0_device,
+	&camera1_device,
 };
 
 static const struct pinctrl_map marzen_pinctrl_map[] = {
@@ -219,6 +249,16 @@ static const struct pinctrl_map marzen_p
 	/* USB2 */
 	PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
 				  "usb2", "usb2"),
+	/* VIN1 */
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779",
+				  "vin1_clk", "vin1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779",
+				  "vin1_data8", "vin1"),
+	/* VIN3 */
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779",
+				  "vin3_clk", "vin3"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779",
+				  "vin3_data8", "vin3"),
 };
 
 static void __init marzen_init(void)
@@ -235,6 +275,8 @@ static void __init marzen_init(void)
 
 	r8a7779_add_standard_devices();
 	r8a7779_add_usb_phy_device(&usb_phy_platform_data);
+	r8a7779_add_vin_device(1, &vin_platform_data);
+	r8a7779_add_vin_device(3, &vin_platform_data);
 	platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
 


From sergei.shtylyov at cogentembedded.com  Wed May 15 17:53:29 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 01:53:29 +0400
Subject: [PATCH v4 0/3] R8A7779/Marzen R-Car VIN driver support
Message-ID: <201305160153.29827.sergei.shtylyov@cogentembedded.com>

Hello.

   Here's the set of 3 patches against the Simon Horman's 'renesas.git' repo,
'renesas-next-20130515v2' tag and my recent yet unapplied USB/I2C patches.
Here we add the VIN driver platform code for the R8A7779/Marzen with ADV7180
I2C video decoder.

[1/3] ARM: shmobile: r8a7779: add VIN support
[2/3] ARM: shmobile: Marzen: add VIN and ADV7180 support
[3/3] ARM: shmobile: Marzen: enable VIN and ADV7180 in defconfig

   The VIN driver itself has been excluded from the series as it will be developed
against Mauro's 'media_tree.git' plus some yet unapplied patches in the future...

WBR, Sergei


From sergei.shtylyov at cogentembedded.com  Wed May 15 17:59:54 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 01:59:54 +0400
Subject: [PATCH v4 3/3] ARM: shmobile: Marzen: enable VIN and ADV7180 in
 defconfig
In-Reply-To: <201305160153.29827.sergei.shtylyov@cogentembedded.com>
References: <201305160153.29827.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305160159.55056.sergei.shtylyov@cogentembedded.com>

From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

Add the VIN and ADV7180 drivers to 'marzen_defconfig'.

Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
 arch/arm/configs/marzen_defconfig |    7 +++++++
 1 file changed, 7 insertions(+)

Index: renesas/arch/arm/configs/marzen_defconfig
===================================================================
--- renesas.orig/arch/arm/configs/marzen_defconfig
+++ renesas/arch/arm/configs/marzen_defconfig
@@ -84,6 +84,13 @@ CONFIG_GPIO_RCAR=y
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_VIDEO_RCAR_VIN=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_VIDEO_ADV7180=y
 CONFIG_USB=y
 CONFIG_USB_RCAR_PHY=y
 CONFIG_MMC=y


From tomasz.figa at gmail.com  Wed May 15 18:02:40 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Thu, 16 May 2013 00:02:40 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305152348.32171.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de> <5193FC08.5040002@gmail.com>
 <201305152348.32171.heiko@sntech.de>
Message-ID: <45625193.0y3McEvmiD@flatron>

On Wednesday 15 of May 2013 23:48:31 Heiko St?bner wrote:
> Am Mittwoch, 15. Mai 2013, 23:20:08 schrieb Sylwester Nawrocki:
> > On 05/15/2013 10:31 PM, Heiko St?bner wrote:
> > >>> +       BUG();
> > >>> 
> > >> >  Isn't that a bit nasty. This macro should be used with care and
> > >> >  we
> > >> >  should recover if possible. dev_err()?
> > > 
> > > runtime_config already denies any settings not in the 1,2 or 4bytes
> > > range - the default-part should therefore never be reached. So if
> > > any other value magically appears in the register and triggers the
> > > default-part, something is seriously wrong. So my guess is, the BUG
> > > might be appropriate.
> > > 
> > > On the other hand the whole default+BUG part could also simply go
> > > away,
> > > for the same reasons.
> > 
> > IMHO BUG() is not needed at all. As Linus suggested dev_err() is such
> > case or WARN_ON() would be more appropriate. This has been discussed
> > in the past extensively, not sure if you are aware of the other
> > Linus' opinion on BUG()/BUG_ON() proliferation:
> > https://lkml.org/lkml/2012/9/27/461
> Very interesting read and I'll keep this in mind in the future. What
> about the other option ... i.e. simply getting rid of the whole "error
> handling", as the other code paths should already make sure that only
> valid values get written into the register.
> 
> Can the value change in the register somehow on its own without kernel
> intervention, or does this not happen?

Hmm, it depends on hardware, I guess. Not sure how it works on this 
particular IP.

Still, the mentioned BUG() was about a value in a driver-filled struct, 
wasn't it?

/* Quoting the the code for reference */

> +static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan *s3cchan)
> +{
> +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> +       struct s3c24xx_txd *txd = s3cchan->at;
> +       u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
> +
> +       switch (txd->dcon & DCON_DSZ_MASK) {
> +       case DCON_DSZ_BYTE:
> +               return tc;
> +       case DCON_DSZ_HALFWORD:
> +               return tc * 2;
> +       case DCON_DSZ_WORD:
> +               return tc * 4;
> +       default:
> +               break;
> +       }
> +
> +       BUG();

(Btw. I don't see anything setting the DCON_DSZ bits in this field. Am I 
missing something?)

Best regards,
Tomasz



From sergei.shtylyov at cogentembedded.com  Wed May 15 17:56:14 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 01:56:14 +0400
Subject: [PATCH v4 1/3] ARM: shmobile: r8a7779: add VIN support
In-Reply-To: <201305160153.29827.sergei.shtylyov@cogentembedded.com>
References: <201305160153.29827.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305160156.15596.sergei.shtylyov@cogentembedded.com>

From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

Add VIN clocks and platform devices for R8A7779 SoC; add function to register
the VIN platform devices.

Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
[Sergei: added 'id' parameter check to r8a7779_add_vin_device(), used '*pdata'
in *sizeof* operator there, renamed some variables, annotated vin[0-3]_resources
[] and 'vin[0-3]_info' as '__initdata'.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
Changes since version 3:
- changed the VIN platform device name to be R8A7779 specific; 
- used '*pdata' in *sizeof* operator in r8a7779_add_vin_device();
- resolved reject in <mach/r8a7779.h> due to USB patch rework.

Changes since version 2:
- annotated vin[0-3]_resources[] and 'vin[0-3]_info' as '__initdata' since they
  are kmemdup()'ed while registering the platform devices anyway;

Changes since the original posting:
- added 'id' parameter check to r8a7779_add_vin_device().

 arch/arm/mach-shmobile/clock-r8a7779.c        |   10 +++++++
 arch/arm/mach-shmobile/include/mach/r8a7779.h |    3 ++
 arch/arm/mach-shmobile/setup-r8a7779.c        |   37 ++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

Index: renesas/arch/arm/mach-shmobile/clock-r8a7779.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/clock-r8a7779.c
+++ renesas/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,9 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
+	MSTP120,
 	MSTP116, MSTP115, MSTP114,
+	MSTP110, MSTP109, MSTP108,
 	MSTP103, MSTP101, MSTP100,
 	MSTP030,
 	MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,9 +127,13 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+	[MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */
 	[MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
 	[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
 	[MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
+	[MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */
+	[MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  9, 0), /* VIN1 */
+	[MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  8, 0), /* VIN2 */
 	[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
 	[MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  1, 0), /* USB2 */
 	[MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  0, 0), /* USB0/1 */
@@ -162,10 +168,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("peripheral_clk",	&clkp_clk),
 
 	/* MSTP32 clocks */
+	CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */
 	CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
 	CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
 	CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
 	CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
+	CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
+	CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
+	CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */
 	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
 	CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
 	CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
Index: renesas/arch/arm/mach-shmobile/include/mach/r8a7779.h
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ renesas/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -5,6 +5,7 @@
 #include <linux/pm_domain.h>
 #include <linux/sh_eth.h>
 #include <linux/platform_data/usb-rcar-phy.h>
+#include <linux/platform_data/camera-rcar.h>
 
 struct platform_device;
 
@@ -35,6 +36,8 @@ extern void r8a7779_add_standard_devices
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
 extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7779_add_vin_device(int idx,
+				   struct rcar_vin_platform_data *pdata);
 extern void r8a7779_init_late(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
Index: renesas/arch/arm/mach-shmobile/setup-r8a7779.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/setup-r8a7779.c
+++ renesas/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -559,6 +559,33 @@ static struct resource ether_resources[]
 	},
 };
 
+#define R8A7779_VIN(idx) \
+static struct resource vin##idx##_resources[] __initdata = {		\
+	DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000),		\
+	DEFINE_RES_IRQ(gic_iid(0x5f + (idx))),				\
+};									\
+									\
+static struct platform_device_info vin##idx##_info __initdata = {	\
+	.parent		= &platform_bus,				\
+	.name		= "r8a7779-vin",				\
+	.id		= idx,						\
+	.res		= vin##idx##_resources,				\
+	.num_res	= ARRAY_SIZE(vin##idx##_resources),		\
+	.dma_mask	= DMA_BIT_MASK(32),				\
+}
+
+R8A7779_VIN(0);
+R8A7779_VIN(1);
+R8A7779_VIN(2);
+R8A7779_VIN(3);
+
+static struct platform_device_info *vin_info_table[] __initdata = {
+	&vin0_info,
+	&vin1_info,
+	&vin2_info,
+	&vin3_info,
+};
+
 static struct platform_device *r8a7779_devices_dt[] __initdata = {
 	&scif0_device,
 	&scif1_device,
@@ -610,6 +637,16 @@ void __init r8a7779_add_usb_phy_device(s
 					  pdata, sizeof(*pdata));
 }
 
+void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
+{
+	BUG_ON(id < 0 || id > 3);
+
+	vin_info_table[id]->data = pdata;
+	vin_info_table[id]->size_data = sizeof(*pdata);
+
+	platform_device_register_full(vin_info_table[id]);
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak r8a7779_register_twd(void) { }
 


From swarren at wwwdotorg.org  Wed May 15 18:28:50 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 16:28:50 -0600
Subject: Naming convention DSI + device tree
In-Reply-To: <20130514181745.GA2762@mail.o2s.ch>
References: <20130514181745.GA2762@mail.o2s.ch>
Message-ID: <51940C22.4050802@wwwdotorg.org>

On 05/14/2013 12:17 PM, David Lanzend?rfer wrote:
> Hello
> I have the following issue:
> In order to make the DSI controller react at all,

Hmm. In the upstream kernel, we don't even have a DSI driver at all for
Tegra, so control over the panel itself is likely the least of your
worries for now.

> I need to pass him a certain combination of pin states.
> Until now within the code of the original android kernel which was using board files this has just been
> done by doing bit banging.
> 
> namely:
> 	gpio_set_value(tf201_lvds_shutdown, 1);
...
> Now with a device tree comes the question: Where should I put this?

Likely, you will need to create a DT binding that represents the
particular panel model that you have, and make the Tegra display
controller node refer to that panel node. The panel node would need
properties to describe the various GPIOs used to control the panel.
Then, you'd want to write a panel-specific driver that handles that
device tree node.

All of this will likely need to be integrated with the upcoming Common
Display Framework.


From sboyd at codeaurora.org  Wed May 15 18:31:11 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 15 May 2013 15:31:11 -0700
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <51940CAF.6010808@codeaurora.org>

On 05/10/13 08:02, James Hogan wrote:
> This adds a metag architecture specific clk-gate and clk-mux which
> extends the generic ones to use global lock2 to protect the register
> fields. It is common with metag to have an RTOS running on a different
> thread or core with access to different bits in the same register (which
> contain clock gate/switch bits for other clocks). Access to such
> registers must be serialised with a global lock such as the one provided
> by the metag architecture port in <asm/global_lock.h>
>
> RFC because despite extending the generic clocks there's still a bit of
> duplicated code necessary. One alternative is to add special cases to
> the generic clock components for when a global or callback function
> based lock is desired instead of a spinlock, but I wasn't sure if that
> sort of hack would really be appreciated in the generic drivers.
>
> Comments?

Can you please Cc the devicetree mailing list when proposing new bindings?

Your patchset brings up a question I've had which is if we should be
putting the bits and register width information in devicetree at all. On
the one hand it's nice to not have anything in C code, just iterate over
nodes and register clocks. On the other hand, it's the first time I've
seen anyone put the register interface into devicetree. From what I can
tell, the regulator bindings have put at most the register base and
physical properties like enable-time, max voltage, etc., but not what
bits are needed to enable/disable a regulator. Also I thought I read
somewhere that reg properties shouldn't overlap each other, so if you
ever have two clocks living in the same register we're going to violate
that.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From arnd at arndb.de  Wed May 15 18:40:54 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 May 2013 00:40:54 +0200
Subject: [PATCH 0/4] ARM: Remove boilerplate debug_ll_io_init code
In-Reply-To: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <201305160040.54399.arnd@arndb.de>

On Monday 13 May 2013, Maxime Ripard wrote:
> The recent introduction of debug_ll_io_init made possible to not rely
> anymore on a custom map_io function but on debug_ll_io_init for the
> early mapping and then on the various drivers to do the needed mappings for
> the kernel to boot.
> 
> Some architectures begin to use only this function as the map_io callback in
> the machine description.
> 
> In order to remove some boilerplate code, make the ARM mm code call
> debug_ll_io_init by itself when no .map_io callback is defined.
> 
> This has been tested on the sunxi platform.

Great stuff!

I didn't notice the addition of debug_ll_io_init, so this is a nice surprise
for me.

Acked-by: Arnd Bergmann <arnd at arndb.de>


From swarren at wwwdotorg.org  Wed May 15 18:43:48 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 16:43:48 -0600
Subject: [PATCH 1/6] ARM: tegra: add an assembly marco to check Tegra
 SoC ID
In-Reply-To: <1368613644-11863-2-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-2-git-send-email-josephl@nvidia.com>
Message-ID: <51940FA4.6050609@wwwdotorg.org>

On 05/15/2013 04:27 AM, Joseph Lo wrote:
> There are some Tegra SoC ID checking code around the low level assembly
> code. Adding a marco to replace them. For the single image to support all
> the Tegra series, we may also need the marco in other common code. So we
> make it become a marco for the usage.

I'm not sure this patch doesn't obfuscate the code too much. The big
issue I see is:

> @@ -115,13 +112,9 @@ ENTRY(__tegra_cpu_reset_handler)
>  
>  	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
>  
> -	mov32	r6, TEGRA_APB_MISC_BASE
> -	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
> -	and	r6, r6, #0xff00
> -#ifdef CONFIG_ARCH_TEGRA_2x_SOC
> -t20_check:
> -	cmp	r6, #(0x20 << 8)
> +	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r5

Here, we replace all the code with the new macro, ...

>  #ifdef CONFIG_ARCH_TEGRA_2x_SOC
>  	/* Are we on Tegra20? */
> -	cmp	r6, #(0x20 << 8)
> +	cmp	r6, #(TEGRA20 << 8)

But here we still have to write out the cmp instructions.

It may be reasonable to create a macro to read/mask/shift the SoC ID,
similar to the existing cpu_id macro, i.e. roughly:

/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV	0x804
+.macro tegra_soc_id base, tmp1, tmp2
+	mov32	\tmp2, \base
+	ldr	\tmp1, [\tmp2, #APB_MISC_GP_HIDREV]
+	and	\tmp1, \tmp1, #0xff00
+.endm

Also, I wonder:

(a) why the need to pass TEGRA_APB_MISC_BASE into the macro; can't the
macro just hard-code that value since it's always the same?

(b) Why need two registers passed to the macro. At least one of the code
segments you've replaced with the macro uses a single register instead:

-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
-	and	r6, r6, #0xff00

Wouldn't that be a better implementation of the macro? I don't think
relying on \tmp2 containing "base" after the macro invocation would be a
good idea, since that's rather like looking inside the black box.


From heiko at sntech.de  Wed May 15 18:45:03 2013
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Thu, 16 May 2013 00:45:03 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <45625193.0y3McEvmiD@flatron>
References: <201305111330.05046.heiko@sntech.de>
 <201305152348.32171.heiko@sntech.de> <45625193.0y3McEvmiD@flatron>
Message-ID: <201305160045.03934.heiko@sntech.de>

Am Donnerstag, 16. Mai 2013, 00:02:40 schrieb Tomasz Figa:
> On Wednesday 15 of May 2013 23:48:31 Heiko St?bner wrote:
> > Am Mittwoch, 15. Mai 2013, 23:20:08 schrieb Sylwester Nawrocki:
> > > On 05/15/2013 10:31 PM, Heiko St?bner wrote:
> > > >>> +       BUG();
> > > >>> 
> > > >> >  Isn't that a bit nasty. This macro should be used with care and
> > > >> >  we
> > > >> >  should recover if possible. dev_err()?
> > > > 
> > > > runtime_config already denies any settings not in the 1,2 or 4bytes
> > > > range - the default-part should therefore never be reached. So if
> > > > any other value magically appears in the register and triggers the
> > > > default-part, something is seriously wrong. So my guess is, the BUG
> > > > might be appropriate.
> > > > 
> > > > On the other hand the whole default+BUG part could also simply go
> > > > away,
> > > > for the same reasons.
> > > 
> > > IMHO BUG() is not needed at all. As Linus suggested dev_err() is such
> > > case or WARN_ON() would be more appropriate. This has been discussed
> > > in the past extensively, not sure if you are aware of the other
> > > Linus' opinion on BUG()/BUG_ON() proliferation:
> > > https://lkml.org/lkml/2012/9/27/461
> > 
> > Very interesting read and I'll keep this in mind in the future. What
> > about the other option ... i.e. simply getting rid of the whole "error
> > handling", as the other code paths should already make sure that only
> > valid values get written into the register.
> > 
> > Can the value change in the register somehow on its own without kernel
> > intervention, or does this not happen?
> 
> Hmm, it depends on hardware, I guess. Not sure how it works on this
> particular IP.
> 
> Still, the mentioned BUG() was about a value in a driver-filled struct,
> wasn't it?
> 
> /* Quoting the the code for reference */
> 
> > +static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan *s3cchan)
> > +{
> > +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> > +       struct s3c24xx_txd *txd = s3cchan->at;
> > +       u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
> > +
> > +       switch (txd->dcon & DCON_DSZ_MASK) {
> > +       case DCON_DSZ_BYTE:
> > +               return tc;
> > +       case DCON_DSZ_HALFWORD:
> > +               return tc * 2;
> > +       case DCON_DSZ_WORD:
> > +               return tc * 4;
> > +       default:
> > +               break;
> > +       }
> > +
> > +       BUG();
> 
> (Btw. I don't see anything setting the DCON_DSZ bits in this field. Am I
> missing something?)

this is for calculating the remaining bytes of the transaction. which is used 
in s3c24xx_dma_tx_status. 

And when looking at it again, I can't really fathom why I did it this way with 
decoding the DSZ from the dcon value of the s3c24xx_txd again instead of 
simply using the width value of the same struct .... 

So it can be much simpler as
	(...)
     u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
	return tc * txd->width;

getting rid of this stuff alltogether


still puzzled how I came up with this strangeness in the first place
Heiko


From swarren at wwwdotorg.org  Wed May 15 18:48:55 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 16:48:55 -0600
Subject: [PATCH 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not
 Cortex-A9
In-Reply-To: <1368613644-11863-3-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-3-git-send-email-josephl@nvidia.com>
Message-ID: <519410D7.9060201@wwwdotorg.org>

On 05/15/2013 04:27 AM, Joseph Lo wrote:
> For supporting single image on all Tegra series, we need to skip some HW
> support code for Cortex-A9 only.

> diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S

> +	check_cpu_part_num 0xc09, r9, r10
> +	movweq	r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
> +	movteq	r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
> +	moveq	r5, #0
> +	streq	r5, [r4, #L2X0_CTRL]

Do those conditional instructions need a Thumb iteq wrapped around them
in order to compile in Thumb2 mode? Same comment for the other change,
although IIRC iteq only supports 4 instructions at a time, so maybe a
branch would be better there. Using branches might also reduce the size
of the diff, and make the change more obvious.


From arnd at arndb.de  Wed May 15 18:54:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 May 2013 00:54:20 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <20130515133237.GK18614@n2100.arm.linux.org.uk>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201305151516.52389.arnd@arndb.de>
 <20130515133237.GK18614@n2100.arm.linux.org.uk>
Message-ID: <201305160054.21064.arnd@arndb.de>

On Wednesday 15 May 2013, Russell King - ARM Linux wrote:
> Actually, that's probably the whole point of this - to do nothing.
> This changes the behaviour of the idle loop from using the WFI to
> just spinning instead with no wait-for-interrupt or anything else.
> We just keep reading the need_resched flag.
> 
> That's much better than the commented out code which opens a mighty
> big race condition which will then give bad scheduling behaviour,
> allowing the idle task to sleep in WFI until the next interrupt while
> the need_resched flag may be set.
> 
> Sure, there's better ways to do this, via the disable_hlt() stuff,
> and whatever its replacement implementation is now called.  But
> ultimately this workaround really is about "doing nothing" when
> idle!

Ah, I see. I also read the mach-gemini version of the idle code,
which is apparently the same thing as the code that was commented
out here, so that has the wakeup race.

Since it seems that WFI is broken on all fa526 cores, or at least
all the ones we want to support in Linux, maybe it's better to
not call WFI at all there?

	Arnd


From swarren at wwwdotorg.org  Wed May 15 18:57:45 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 16:57:45 -0600
Subject: [PATCH 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <1368613644-11863-4-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-4-git-send-email-josephl@nvidia.com>
Message-ID: <519412E9.2080905@wwwdotorg.org>

On 05/15/2013 04:27 AM, Joseph Lo wrote:
> Tegra114 is an ARM Cortex-A15 based SoC and some of the flow controller

I don't think the CPU type is the issue here. The issue is simply that
Tegra114's flow controller is different. Mentioning the CPU type seems
misleading.

> hardware behavior and configurations are different with other Tegra series.
> We fix the common resume function of tegra_resume to make it can work on
> Tegra114 by checking SoC ID. And also checking CPU primary part number to
> isolate the support code for Cortex A9 and A15.

> diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S

> -#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> +#ifndef CONFIG_ARCH_TEGRA_2x_SOC
>  	/* Are we on Tegra20? */
>  	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r7
>  	beq	1f				@ Yes
>  	/* Clear the flow controller flags for this CPU. */
> -	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
> -	ldr	r1, [r2]
> +	cpu_to_csr_req r1, r0

Where is cpu_to_csr_req defined? grep can't find it in next-20130513,
and I don't see it added in this series.

This presumably changes behaviour on Tegra30; will this cause problems?

> +	mov32	r2, TEGRA_FLOW_CTRL_BASE
> +	ldr	r1, [r2, r1]
>  	/* Clear event & intr flag */
>  	orr	r1, r1, \
>  		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
> -	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
> +	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, & bitmaps

What does this change do; does the commend need updating to describe the
new bits that are set?


From swarren at wwwdotorg.org  Wed May 15 19:02:33 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 17:02:33 -0600
Subject: [PATCH 5/6] clk: tegra114: implement wait_for_reset and
 disable_clock for tegra_cpu_car_ops
In-Reply-To: <1368613644-11863-6-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-6-git-send-email-josephl@nvidia.com>
Message-ID: <51941409.3030909@wwwdotorg.org>

On 05/15/2013 04:27 AM, Joseph Lo wrote:
> The conventional CPU hotplug sequence on the other Tegra chips, we will also
> clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
> Tegra114, the flow controller will clock gate the CPU after the power down
> sequence. But we still need to implement a empty function for disable_clock
> to avoid kernel warning message.

I assume I need to apply this patch in the Tegra tree along with all the
other patches in this series? i.e. Mike can't apply it on its own to the
clk tree?

If so, I'll wait for an ack from Mike.


From swarren at wwwdotorg.org  Wed May 15 19:11:41 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 17:11:41 -0600
Subject: [PATCH 6/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1368613644-11863-7-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-7-git-send-email-josephl@nvidia.com>
Message-ID: <5194162D.7010007@wwwdotorg.org>

On 05/15/2013 04:27 AM, Joseph Lo wrote:
> The Tegra114 is a quad cores SoC. Each core can be hotplugged including
> CPU0. The hotplug sequence can be controlled by setting event trigger in
> flow controller. Then the flow controller will take care all the power
> sequence that include CPU up and down.

> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile

> +obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= sleep-tegra30.o

CONFIG_ARCH_TEGRA_3x_SOC also adds that to obj-y. Will including it
twice cause problems?

> diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S

>   *	  CPU boot vector when restarting the a CPU following
>   *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
>   *	  re-enabling sdram.
> + *
> + *	r6: SoC ID << 8

I meant to ask in patch 1: Perhaps the macro could do a >>8 so that code
can compare directly against the SoC IDs instead of having to compare
against shifted values.

> +	tegra_check_soc_id TEGRA114, TEGRA_APB_MISC_BASE, r6, r7
> +	beq	no_cpu0_chk

Does that need a THUMB(it ...) added? Same elsewhere.

> +	cmp	r6, #(TEGRA114 <<8)

Needs a space after <<.

> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S

> @@ -45,12 +46,17 @@ ENDPROC(tegra30_hotplug_shutdown)
>   * and powergates it -- flags (in R0) indicate the request type.
>   * Must never be called for CPU 0.

That comment is wrong now, I think.

>  	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
> +	beq	flow_ctrl_setting_for_lp2
> +
> +	/* flow controller set up for hotplug */
> +	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
> +	b	flow_ctrl_done
> +flow_ctrl_setting_for_lp2:
> +	/* flow controller set up for LP2 */
> +	cmp	r10, #(TEGRA30 << 8)
>  	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2

Do you need e.g. "movne r3, #0" or similar here? Otherwise, I think r3
ends up not being initialized.

> -	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
> +flow_ctrl_done:
> +	cmp	r10, #(TEGRA30 << 8)
>  	str	r3, [r2]

I wonder whether creating a separate tegra114_cpu_shutdown() wouldn't be
better, to avoid all the runtime conditional code.


From tomasz.figa at gmail.com  Wed May 15 19:26:08 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Thu, 16 May 2013 01:26:08 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305160045.03934.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de> <45625193.0y3McEvmiD@flatron>
 <201305160045.03934.heiko@sntech.de>
Message-ID: <2010181.yFyln8lrI2@flatron>

On Thursday 16 of May 2013 00:45:03 Heiko St?bner wrote:
> Am Donnerstag, 16. Mai 2013, 00:02:40 schrieb Tomasz Figa:
> > On Wednesday 15 of May 2013 23:48:31 Heiko St?bner wrote:
> > > Am Mittwoch, 15. Mai 2013, 23:20:08 schrieb Sylwester Nawrocki:
> > > > On 05/15/2013 10:31 PM, Heiko St?bner wrote:
> > > > >>> +       BUG();
> > > > >>> 
> > > > >> >  Isn't that a bit nasty. This macro should be used with care
> > > > >> >  and
> > > > >> >  we
> > > > >> >  should recover if possible. dev_err()?
> > > > > 
> > > > > runtime_config already denies any settings not in the 1,2 or
> > > > > 4bytes
> > > > > range - the default-part should therefore never be reached. So
> > > > > if
> > > > > any other value magically appears in the register and triggers
> > > > > the
> > > > > default-part, something is seriously wrong. So my guess is, the
> > > > > BUG
> > > > > might be appropriate.
> > > > > 
> > > > > On the other hand the whole default+BUG part could also simply
> > > > > go
> > > > > away,
> > > > > for the same reasons.
> > > > 
> > > > IMHO BUG() is not needed at all. As Linus suggested dev_err() is
> > > > such
> > > > case or WARN_ON() would be more appropriate. This has been
> > > > discussed
> > > > in the past extensively, not sure if you are aware of the other
> > > > Linus' opinion on BUG()/BUG_ON() proliferation:
> > > > https://lkml.org/lkml/2012/9/27/461
> > > 
> > > Very interesting read and I'll keep this in mind in the future. What
> > > about the other option ... i.e. simply getting rid of the whole
> > > "error
> > > handling", as the other code paths should already make sure that
> > > only
> > > valid values get written into the register.
> > > 
> > > Can the value change in the register somehow on its own without
> > > kernel
> > > intervention, or does this not happen?
> > 
> > Hmm, it depends on hardware, I guess. Not sure how it works on this
> > particular IP.
> > 
> > Still, the mentioned BUG() was about a value in a driver-filled
> > struct,
> > wasn't it?
> > 
> > /* Quoting the the code for reference */
> > 
> > > +static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan
> > > *s3cchan)
> > > +{
> > > +       struct s3c24xx_dma_phy *phy = s3cchan->phy;
> > > +       struct s3c24xx_txd *txd = s3cchan->at;
> > > +       u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
> > > +
> > > +       switch (txd->dcon & DCON_DSZ_MASK) {
> > > +       case DCON_DSZ_BYTE:
> > > +               return tc;
> > > +       case DCON_DSZ_HALFWORD:
> > > +               return tc * 2;
> > > +       case DCON_DSZ_WORD:
> > > +               return tc * 4;
> > > +       default:
> > > +               break;
> > > +       }
> > > +
> > > +       BUG();
> > 
> > (Btw. I don't see anything setting the DCON_DSZ bits in this field. Am
> > I missing something?)
> 
> this is for calculating the remaining bytes of the transaction. which is
> used in s3c24xx_dma_tx_status.
> 
> And when looking at it again, I can't really fathom why I did it this
> way with decoding the DSZ from the dcon value of the s3c24xx_txd again
> instead of simply using the width value of the same struct ....
> 
> So it can be much simpler as
> 	(...)
>      u32 tc = readl(phy->base + DSTAT) & DSTAT_CURRTC_MASK;
> 	return tc * txd->width;
> 
> getting rid of this stuff alltogether
> 
> 
> still puzzled how I came up with this strangeness in the first place

Hehe, happens.

I'm still yet to review the whole series, but I'm failing to find enough 
time. Hopefully will get to do it soon.

Best regards,
Tomasz



From khilman at linaro.org  Wed May 15 19:29:03 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 15 May 2013 16:29:03 -0700
Subject: u8500_defconfig: build failure in linux-next
Message-ID: <CAGa+x85Q8i9DCdTprbVX1opB9UdeD4uxAQpZ-CsqPYt86dLVFA@mail.gmail.com>

Lee, Linus,

In building all the ARM defconfigs in linux-next, I noticed
u8500_defconfig not building:

  [...]
  CC      drivers/mfd/ab8500-debugfs.o
/work/kernel/next/drivers/mfd/ab8500-debugfs.c:95:23: fatal error:
mach/irqs.h: No such file or directory

Same build error on v3.10-rc1 and Linus' master branch (but is fine on v3.9)

Kevin


From tony at atomide.com  Wed May 15 19:33:36 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 15 May 2013 16:33:36 -0700
Subject: [PATCH v2 1/3] ARM: allow platforms to use generic headers
 without ARCH_MULTIPLATFORM
In-Reply-To: <5192532B.1070705@gmail.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
 <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>
 <5192532B.1070705@gmail.com>
Message-ID: <20130515233335.GO5600@atomide.com>

* Rob Herring <robherring2 at gmail.com> [130514 08:12]:
> On 05/14/2013 06:27 AM, Jonathan Austin wrote:
> > Currently the use of generic mach headers is only is controlled by the same
> > config option as selection of a multiplatform kernel (i.e.
> > ARCH_MULTIPLATFORM). However, there are cases where it is valid to use the
> > generic headers but still build a single platform kernel.
> > 
> > One such example is when using the vexpress platform with a core that does
> > not have an MMU; a multiplatform kernel does not make sense, but use of the
> > generic headers is required by the vexpress platform since 617276307cd4c
> > ("ARM: vexpress: convert to multi-platform").
> > 
> > This patch untangles these two options by introducing a new
> > ARM_GENERIC_HEADERS config option that ARCH_MULTIPLATFORM selects. Other
> > platforms can now select ARM_GENERIC_HEADERS independently.
> 
> I find this name confusing. It is no headers you are selecting and
> generic is a bit overused IMHO. So how about something like
> NEED_NO_MACH_HEADERS to somewhat align to the other header related
> config options (e.g. NEED_MACH_GPIO_H).

Hmm it _looks_ like this won't allow the drivers again to
#include <plat/*.h> and <mach/*.h>. Have you checked that?

It might be worth checking as we really don't want to go back there
again.. Currently arch/arm/Makefile has:

ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
ifeq ($(KBUILD_SRC),)
KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
else
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
endif
endif

So you may need to do something there to prevent drivers from again
including machdirs and platdirs.

Regards,

Tony


From swarren at wwwdotorg.org  Wed May 15 19:38:00 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 May 2013 17:38:00 -0600
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
Message-ID: <51941C58.9060002@wwwdotorg.org>

On 05/15/2013 04:27 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.

This series mostly works OK, but I see one problem: I can't hotunplug
CPU0, which the commit descriptions and code changes imply I should be
able to do:

root at localhost:~# echo 0 > /sys/devices/system/cpu/cpu0/online
-bash: echo: write error: Operation not permitted


From horms at verge.net.au  Wed May 15 19:56:43 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 16 May 2013 08:56:43 +0900
Subject: [PATCH v2 3/4] ARM: shmobile: marzen-reference: Initialise irqpin
In-Reply-To: <1482970.xQCySsLs8z@avalon>
References: <1368586650-26263-1-git-send-email-horms+renesas@verge.net.au>
 <1368586650-26263-4-git-send-email-horms+renesas@verge.net.au>
 <1482970.xQCySsLs8z@avalon>
Message-ID: <20130515235640.GA27876@verge.net.au>

On Wed, May 15, 2013 at 11:28:15AM +0200, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thanks for the patch.
> 
> On Wednesday 15 May 2013 11:57:29 Simon Horman wrote:
> > Empirically it appears to be necessary to call r8a7779_init_irq_extpin(1)
> > in order to initialise irqpin for use with IRQ1. This is already done in
> > the marzen board code. This adds the call to the marzen-reference board
> > code.
> > 
> > The motivation for this is to allow use of SMSC LAN, which uses IRQ1, with
> > marzen-reference.
> 
> This is an acceptable workaround for now, but in the not-so-long term we want 
> to move that code to the irqpin driver.

Yes, I agree that this not a long term solution.

> I've had a brief look at the irq-renesas-intc-irqpin driver, and it definitely 
> looks like some love is needed there. I don't have any free time for that at 
> the moment, but I could provide pointers if anyone wants to work on moving 
> irqpin-related arch code to the driver.
> 
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > ---
> >  arch/arm/mach-shmobile/board-marzen-reference.c | 8 +++++++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> > b/arch/arm/mach-shmobile/board-marzen-reference.c index 5332e89..f83b6d1
> > 100644
> > --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> > +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> > @@ -63,12 +63,18 @@ static const char *marzen_boards_compat_dt[] __initdata
> > = { NULL,
> >  };
> > 
> > +void __init marzen_init_irq(void)
> > +{
> > +	r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
> > +	r8a7779_init_irq_dt();
> > +}
> > +
> >  DT_MACHINE_START(MARZEN, "marzen")
> >  	.smp		= smp_ops(r8a7779_smp_ops),
> >  	.map_io		= r8a7779_map_io,
> >  	.init_early	= r8a7779_init_delay,
> >  	.nr_irqs	= NR_IRQS_LEGACY,
> > -	.init_irq	= r8a7779_init_irq_dt,
> > +	.init_irq	= marzen_init_irq,
> >  	.init_machine	= marzen_init,
> >  	.init_time	= shmobile_timer_init,
> >  	.dt_compat	= marzen_boards_compat_dt,
> -- 
> Regards,
> 
> Laurent Pinchart
> 


From horms at verge.net.au  Wed May 15 20:07:04 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 16 May 2013 09:07:04 +0900
Subject: [PATCHv2 4/5] arm: fix up ARM_ARCH_TIMER selects
In-Reply-To: <1368631441-28434-5-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
 <1368631441-28434-5-git-send-email-mark.rutland@arm.com>
Message-ID: <20130516000704.GF27876@verge.net.au>

On Wed, May 15, 2013 at 04:24:00PM +0100, Mark Rutland wrote:
> In 8a4da6e: "arm: arch_timer: move core to drivers/clocksource", the
> selection of ARM_ARCH_TIMER was indirected via HAVE_ARM_ARCH_TIMER,
> though mach-exynos's selection of ARM_ARCH_TIMER was missed, and since
> then mach-shmobile, mach-tegra, and mach-virt have begun selecting
> ARM_ARCH_TIMER. This can lead to architected timer support erroneously
> appearing to not be selected in menuconfig.
> 
> This patch fixes up the Kconfigs for those platforms to select
> HAVE_ARM_ARCH_TIMER.
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Acked-by: Stephen Warren <swarren at nvidia.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Cc: Simon Horman <horms at verge.net.au>
> ---
>  arch/arm/mach-exynos/Kconfig   | 2 +-
>  arch/arm/mach-shmobile/Kconfig | 4 ++--
>  arch/arm/mach-tegra/Kconfig    | 2 +-
>  arch/arm/mach-virt/Kconfig     | 2 +-
>  4 files changed, 5 insertions(+), 5 deletions(-)

arch/arm/mach-shmobile/Kconfig portion:

Acked-by: Simon Horman <horms+renesas at verge.net.au>

> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index d19edff..3c3f36a 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -76,7 +76,7 @@ config SOC_EXYNOS5440
>  	default y
>  	depends on ARCH_EXYNOS5
>  	select ARCH_HAS_OPP
> -	select ARM_ARCH_TIMER
> +	select HAVE_ARM_ARCH_TIMER
>  	select AUTO_ZRELADDR
>  	select PINCTRL
>  	select PINCTRL_EXYNOS5440
> diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
> index 1a517e2..767a6c3 100644
> --- a/arch/arm/mach-shmobile/Kconfig
> +++ b/arch/arm/mach-shmobile/Kconfig
> @@ -23,7 +23,7 @@ config ARCH_R8A73A4
>  	select ARCH_WANT_OPTIONAL_GPIOLIB
>  	select ARM_GIC
>  	select CPU_V7
> -	select ARM_ARCH_TIMER
> +	select HAVE_ARM_ARCH_TIMER
>  	select SH_CLK_CPG
>  	select RENESAS_IRQC
>  
> @@ -56,7 +56,7 @@ config ARCH_R8A7790
>  	select ARCH_WANT_OPTIONAL_GPIOLIB
>  	select ARM_GIC
>  	select CPU_V7
> -	select ARM_ARCH_TIMER
> +	select HAVE_ARM_ARCH_TIMER
>  	select SH_CLK_CPG
>  	select RENESAS_IRQC
>  
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 84d72fc..65c5ae6 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -60,7 +60,7 @@ config ARCH_TEGRA_3x_SOC
>  
>  config ARCH_TEGRA_114_SOC
>  	bool "Enable support for Tegra114 family"
> -	select ARM_ARCH_TIMER
> +	select HAVE_ARM_ARCH_TIMER
>  	select ARM_GIC
>  	select ARM_L1_CACHE_SHIFT_6
>  	select CPU_FREQ_TABLE if CPU_FREQ
> diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
> index 8958f0d..081d469 100644
> --- a/arch/arm/mach-virt/Kconfig
> +++ b/arch/arm/mach-virt/Kconfig
> @@ -2,7 +2,7 @@ config ARCH_VIRT
>  	bool "Dummy Virtual Machine" if ARCH_MULTI_V7
>  	select ARCH_WANT_OPTIONAL_GPIOLIB
>  	select ARM_GIC
> -	select ARM_ARCH_TIMER
> +	select HAVE_ARM_ARCH_TIMER
>  	select ARM_PSCI
>  	select HAVE_SMP
>  	select CPU_V7
> -- 
> 1.8.1.1
> 


From kuninori.morimoto.gx at renesas.com  Wed May 15 21:10:29 2013
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Wed, 15 May 2013 18:10:29 -0700 (PDT)
Subject: [PATCH v3 1/1] ARM: shmobile: r8a7778: add I2C support
In-Reply-To: <201304232015.59697.sergei.shtylyov@cogentembedded.com>
References: <201304232012.57619.sergei.shtylyov@cogentembedded.com>
 <201304232015.59697.sergei.shtylyov@cogentembedded.com>
Message-ID: <87txm3wwzh.wl%kuninori.morimoto.gx@renesas.com>


Hi Sergei

Basically, this patch is good for me.
But I have some comment.

Sergei Shtylyov wrote:
> 
> From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
> 
> Add I2C clocks and platform devices for R8A7778 SoC.
> Don't forget to also add the peripheral clock which the I2C driver uses.
> 
> Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
> [Sergei: changed the registration function to platform_device_register_simple(),
> annotated I2C resources as '__initdata', regrouped MSTPxxx *enum* members, added
> the copyright.]
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
(snip)
> -	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
> +	MSTP030, MSTP029,
> +	MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,

It should be

	MSTP30,
	MSPT029, MSPT028, MSPT027...

> +/* I2C */
> +static struct resource i2c0_resources[] __initdata = {
> +	DEFINE_RES_MEM(0xffc70000, 0x1000),
> +	DEFINE_RES_IRQ(gic_iid(0x63)),
> +};
> +
> +static struct resource i2c1_resources[] __initdata = {
> +	DEFINE_RES_MEM(0xffc71000, 0x1000),
> +	DEFINE_RES_IRQ(gic_iid(0x6e)),
> +};
> +
> +static struct resource i2c2_resources[] __initdata = {
> +	DEFINE_RES_MEM(0xffc72000, 0x1000),
> +	DEFINE_RES_IRQ(gic_iid(0x6c)),
> +};
> +
> +static struct resource i2c3_resources[] __initdata = {
> +	DEFINE_RES_MEM(0xffc73000, 0x1000),
> +	DEFINE_RES_IRQ(gic_iid(0x6d)),
> +};
> +
> +#define r8a7778_register_i2c(idx)			\
> +	platform_device_register_simple(		\
> +		"i2c-rcar", idx,			\
> +		i2c##idx##_resources,			\
> +		ARRAY_SIZE(i2c##idx##_resources))
> +
>  /* USB PHY */
>  static struct resource usb_phy_resources[] __initdata = {
>  	DEFINE_RES_MEM(0xffe70800, 0x100),
> @@ -294,6 +321,11 @@ void __init r8a7778_add_standard_devices
>  
>  	r8a7778_register_tmu(0);
>  	r8a7778_register_tmu(1);
> +
> +	r8a7778_register_i2c(0);
> +	r8a7778_register_i2c(1);
> +	r8a7778_register_i2c(2);
> +	r8a7778_register_i2c(3);
>  }

i2c1 - i2c3 pins are pin-multi.
I guess using r8a7778_add_i2c_devices(idx) from board code is better method


Best regards
---
Kuninori Morimoto


From Baohua.Song at csr.com  Wed May 15 22:50:07 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Thu, 16 May 2013 10:50:07 +0800
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
Message-ID: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>

From: Xiaomeng Hou <Xiaomeng.Hou at csr.com>

if we initilize i2c bus by module_init, there are some devices which want
initialization earlier than i2c and could not do that in time, so move i2c
driver initilization to subsys_initcall and make i2c ready before devices
init.

Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/i2c/busses/i2c-sirf.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c
index 5a7ad24..e438f48 100644
--- a/drivers/i2c/busses/i2c-sirf.c
+++ b/drivers/i2c/busses/i2c-sirf.c
@@ -454,7 +454,19 @@ static struct platform_driver i2c_sirfsoc_driver = {
 	.probe = i2c_sirfsoc_probe,
 	.remove = i2c_sirfsoc_remove,
 };
-module_platform_driver(i2c_sirfsoc_driver);
+
+static __init int i2c_sirfsoc_init(void)
+{
+	return platform_driver_register(&i2c_sirfsoc_driver);
+}
+
+static void __exit i2c_sirfsoc_exit(void)
+{
+	platform_driver_unregister(&i2c_sirfsoc_driver);
+}
+
+subsys_initcall(i2c_sirfsoc_init);
+module_exit(i2c_sirfsoc_exit);
 
 MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song at csr.com>, "
-- 
1.8.2.3



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Baohua.Song at csr.com  Wed May 15 23:17:09 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Thu, 16 May 2013 11:17:09 +0800
Subject: [PATCH] pinctrl: sirf: save the status in suspend and restore after
 resuming
Message-ID: <1368674229-11813-1-git-send-email-Baohua.Song@csr.com>

this patch saves the status of pinctrl registers and restore them while
resuming. this makes all drivers have coherent status for pinmux after
suspending and resuming.

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/pinctrl/sirf/pinctrl-sirf.c | 56 +++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index b4727db..0677e19 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -390,11 +390,67 @@ out_no_rsc_remap:
 	return ret;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
+{
+	int i, j;
+	struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
+
+	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+		for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
+			spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
+				SIRFSOC_GPIO_CTRL(i, j));
+		}
+		spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
+			SIRFSOC_GPIO_INT_STATUS(i));
+		spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
+			SIRFSOC_GPIO_PAD_EN(i));
+	}
+	spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
+
+	for (i = 0; i < 3; i++)
+		spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
+
+	return 0;
+}
+
+static int sirfsoc_pinmux_resume_noirq(struct device *dev)
+{
+	int i, j;
+	struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
+
+	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+		for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
+			writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
+				SIRFSOC_GPIO_CTRL(i, j));
+		}
+		writel(spmx->ints_regs[i], spmx->gpio_virtbase +
+			SIRFSOC_GPIO_INT_STATUS(i));
+		writel(spmx->paden_regs[i], spmx->gpio_virtbase +
+			SIRFSOC_GPIO_PAD_EN(i));
+	}
+	writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
+
+	for (i = 0; i < 3; i++)
+		writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
+
+	return 0;
+}
+
+static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
+	.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
+	.resume_noirq = sirfsoc_pinmux_resume_noirq,
+};
+#endif
+
 static struct platform_driver sirfsoc_pinmux_driver = {
 	.driver = {
 		.name = DRIVER_NAME,
 		.owner = THIS_MODULE,
 		.of_match_table = pinmux_ids,
+#ifdef CONFIG_PM_SLEEP
+		.pm = &sirfsoc_pinmux_pm_ops,
+#endif
 	},
 	.probe = sirfsoc_pinmux_probe,
 };
-- 
1.8.2.3



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From sfr at canb.auug.org.au  Wed May 15 23:22:53 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 16 May 2013 13:22:53 +1000
Subject: linux-next: manual merge of the renesas tree with Linus' tree
Message-ID: <20130516132253.8865ca7b6503bd6fe9e6b05a@canb.auug.org.au>

Hi Simon,

Today's linux-next merge of the renesas tree got a conflict in
arch/arm/mach-shmobile/board-lager.c between commit 65be2de17aae ("ARM:
shmobile: use r8a7790 timer setup code on Lager") from Linus' tree and
commit 993340a1390d ("ARM: shmobile: use r8a7790 timer setup code on
Lager") from the renesas tree.

These are the same patch but different commits :-( and there are further
commits touching this file in the renesas tree.  Please clean up your
tree and remove anything that has already gone upstream as different
patches.  I used the renesas tree version of this file.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From Baohua.Song at csr.com  Wed May 15 23:26:10 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Thu, 16 May 2013 11:26:10 +0800
Subject: [PATCH v2] arm: prima2: use of_platform_populate instead of
 of_platform_bus_probe
Message-ID: <1368674770-18845-1-git-send-email-Baohua.Song@csr.com>

use of_platform_populate to populate platform devices, it is suitable
for creating devices which are children of the root node, then makes
things like pcm work.

this patch removes sirfsoc_mach_init() function and lets arm core do
of_platform_populate:

    static int __init customize_machine(void)
    {
            /*
             * customizes platform devices, or adds new ones
             * On DT based machines, we fall back to populating the
             * machine from the device tree, if no callback is provided,
             * otherwise we would always need an init_machine callback.
             */
            if (machine_desc->init_machine)
                    machine_desc->init_machine();
            else
                    of_platform_populate(NULL, of_default_bus_match_table,
                                            NULL, NULL);
            return 0;
    }

Signed-off-by: Barry Song <Baohua.Song at csr.com>
Signed-off-by: Rongjun Ying <Rongjun.Ying at csr.com>
---
 -v2: removes sirfsoc_mach_init() function as Arnd's comments

 arch/arm/mach-prima2/common.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd8..5ae029f 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -17,16 +17,6 @@
 #include <linux/of_platform.h>
 #include "common.h"
 
-static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
-	{ .compatible = "simple-bus", },
-	{},
-};
-
-void __init sirfsoc_mach_init(void)
-{
-	of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
-}
-
 void __init sirfsoc_init_late(void)
 {
 	sirfsoc_pm_init();
@@ -57,7 +47,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	.map_io         = sirfsoc_map_io,
 	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
-	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = atlas6_dt_match,
 	.restart	= sirfsoc_restart,
@@ -77,7 +66,6 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
 	.dma_zone_size	= SZ_256M,
-	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = prima2_dt_match,
 	.restart	= sirfsoc_restart,
@@ -96,7 +84,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
 	.map_io         = sirfsoc_map_io,
 	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_init_time,
-	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = marco_dt_match,
 	.restart	= sirfsoc_restart,
-- 
1.8.2.3



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From skannan at codeaurora.org  Thu May 16 00:07:24 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 15 May 2013 21:07:24 -0700
Subject: [PATCH v2] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1368677244-7279-1-git-send-email-skannan@codeaurora.org>

Without this patch, the following race condition is possible.
* clk-A has two parents - clk-X and clk-Y.
* All three are disabled and clk-X is current parent.
* Thread A: clk_set_parent(clk-A, clk-Y).
* Thread A: <snip execution flow>
* Thread A: Grabs enable lock.
* Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
* Thread A: Updates clk-A SW parent to clk-Y
* Thread A: Releases enable lock.
* Thread B: clk_enable(clk-A).
* Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.

clk-A is now enabled in software, but not clocking in hardware since the
hardware parent is still clk-X.

The only way to avoid race conditions between clk_set_parent() and
clk_enable/disable() is to ensure that clk_enable/disable() calls don't
require changes to hardware enable state between changes to software clock
topology and hardware clock topology.

The options to achieve the above are:
1. Grab the enable lock before changing software/hardware topology and
   release it afterwards.
2. Keep the clock enabled for the duration of software/hardware topology
   change so that any additional enable/disable calls don't try to change
   the hardware state. Once the topology change is complete, the clock can
   be put back in its original enable state.

Option (1) is not an acceptable solution since the set_parent() ops might
need to sleep.

Therefore, this patch implements option (2).

This patch doesn't violate any API semantics. clk_disable() doesn't
guarantee that the clock is actually disabled. So, no clients of a clock
can assume that a clock is disabled after their last call to clk_disable().
So, enabling the clock during a parent change is not a violation of any API
semantics.

This also has the nice side effect of simplifying the error handling code.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
---
 drivers/clk/clk.c |   91 ++++++++++++++++++++++++++---------------------------
 1 files changed, 45 insertions(+), 46 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 934cfd1..b4dbb8c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1377,67 +1377,61 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
 	unsigned long flags;
 	int ret = 0;
 	struct clk *old_parent = clk->parent;
-	bool migrated_enable = false;
 
-	/* migrate prepare */
-	if (clk->prepare_count)
+	/*
+	 * Migrate prepare state between parents and prevent race with
+	 * clk_enable().
+	 *
+	 * If the clock is not prepared, then a race with
+	 * clk_enable/disable() is impossible since we already have the
+	 * prepare lock (future calls to clk_enable() need to be preceded by
+	 * a clk_prepare()).
+	 *
+	 * If the clock is prepared, migrate the prepared state to the new
+	 * parent and also protect against a race with clk_enable() by
+	 * forcing the clock and the new parent on.  This ensures that all
+	 * future calls to clk_enable() are practically NOPs with respect to
+	 * hardware and software states.
+	 *
+	 * See also: Comment for clk_set_parent() below.
+	 */
+	if (clk->prepare_count) {
 		__clk_prepare(parent);
-
-	flags = clk_enable_lock();
-
-	/* migrate enable */
-	if (clk->enable_count) {
-		__clk_enable(parent);
-		migrated_enable = true;
+		clk_enable(parent);
+		clk_enable(clk);
 	}
 
 	/* update the clk tree topology */
+	flags = clk_enable_lock();
 	clk_reparent(clk, parent);
-
 	clk_enable_unlock(flags);
 
 	/* change clock input source */
 	if (parent && clk->ops->set_parent)
 		ret = clk->ops->set_parent(clk->hw, p_index);
-
 	if (ret) {
-		/*
-		 * The error handling is tricky due to that we need to release
-		 * the spinlock while issuing the .set_parent callback. This
-		 * means the new parent might have been enabled/disabled in
-		 * between, which must be considered when doing rollback.
-		 */
-		flags = clk_enable_lock();
 
+		flags = clk_enable_lock();
 		clk_reparent(clk, old_parent);
-
-		if (migrated_enable && clk->enable_count) {
-			__clk_disable(parent);
-		} else if (migrated_enable && (clk->enable_count == 0)) {
-			__clk_disable(old_parent);
-		} else if (!migrated_enable && clk->enable_count) {
-			__clk_disable(parent);
-			__clk_enable(old_parent);
-		}
-
 		clk_enable_unlock(flags);
 
-		if (clk->prepare_count)
+		if (clk->prepare_count) {
+			clk_disable(clk);
+			clk_disable(parent);
 			__clk_unprepare(parent);
-
+		}
 		return ret;
 	}
 
-	/* clean up enable for old parent if migration was done */
-	if (migrated_enable) {
-		flags = clk_enable_lock();
-		__clk_disable(old_parent);
-		clk_enable_unlock(flags);
-	}
-
-	/* clean up prepare for old parent if migration was done */
-	if (clk->prepare_count)
+	/*
+	 * Finish the migration of prepare state and undo the changes done
+	 * for preventing a race with clk_enable().
+	 */
+	if (clk->prepare_count) {
+		clk_disable(clk);
+		clk_disable(old_parent);
 		__clk_unprepare(old_parent);
+	}
 
 	/* update debugfs with new clk tree topology */
 	clk_debug_reparent(clk, parent);
@@ -1449,12 +1443,17 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
  * @clk: the mux clk whose input we are switching
  * @parent: the new input to clk
  *
- * Re-parent clk to use parent as it's new input source.  If clk has the
- * CLK_SET_PARENT_GATE flag set then clk must be gated for this
- * operation to succeed.  After successfully changing clk's parent
- * clk_set_parent will update the clk topology, sysfs topology and
- * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
- * success, -EERROR otherwise.
+ * Re-parent clk to use parent as its new input source.  If clk is in
+ * prepared state, the clk will get enabled for the duration of this call. If
+ * that's not acceptable for a specific clk (Eg: the consumer can't handle
+ * that, the reparenting is glitchy in hardware, etc), use the
+ * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
+ *
+ * After successfully changing clk's parent clk_set_parent will update the
+ * clk topology, sysfs topology and propagate rate recalculation via
+ * __clk_recalc_rates.
+ *
+ * Returns 0 on success, -EERROR otherwise.
  */
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
-- 
1.7.8.3

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May 16 00:11:43 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 15 May 2013 21:11:43 -0700
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <51945C7F.2030605@codeaurora.org>

On 04/19/2013 09:28 AM, James Hogan wrote:
> This patchset adds support for automatic selection of the best parent
> for a clock mux, i.e. the one which can provide the closest clock rate
> to that requested. It can be controlled by a new CLK_SET_RATE_REMUX flag
> so that it doesn't happen unless explicitly allowed.
>
> This works by way of adding a new op, determine_rate, similar to
> round_rate but with an extra parameter to allow the clock driver to
> optionally select a different parent clock. This is used in
> clk_calc_new_rates to decide whether to initiate a set_parent operation.
>
> Changes in v2:
>
> I've moved the mux determine_rate implementation into a core helper, but
> I haven't pushed it fully into the core, as I think it just wouldn't
> work correctly for more complex clocks, e.g. if you (theoretically) had
> a combined mux and divide, you'd want to intercept the determine_rate
> and ask for a larger rate from the parent clocks, then return the
> divided rate. This should be possible by wrapping the mux determine_rate
> helper.
>
> Patch 1 still exports the __clk_get_parent_by_index as it seems like it
> might be a useful thing for clock implementations to have access to if
> they ever wanted to do something more fancy with changing clock parents.
>
> I haven't made any attempt to implement the atomic set_parent+set_rate
> as I don't have hardware that could take proper advantage of it, but it
> shouldn't be too difficult for others to implement if they wanted since
> they're fairly close to one another (in clk_change_rate()).
>
> * switched to using new determine_rate op rather than adding an argument
>    to round_rate.
> * moved mux implementation into a single helper which should be usable
>    from more complex clocks which can mux.
> * rewrite main implementation so that no changes are made until after
>    the PRE notifications have been sent, and in a way that should ensure
>    correct notifications without duplicates, and I think should be safe
>    in the event of a notification failing.
> * various tidy ups and fixes.
>
> James Hogan (3):
>    clk: abstract parent cache
>    clk: add support for clock reparent on set_rate
>    clk: clk-mux: implement remuxing on set_rate
>
>   Documentation/clk.txt        |   4 +
>   drivers/clk/clk-mux.c        |   1 +
>   drivers/clk/clk.c            | 216 +++++++++++++++++++++++++++++++++----------
>   include/linux/clk-private.h  |   2 +
>   include/linux/clk-provider.h |  12 +++
>   5 files changed, 185 insertions(+), 50 deletions(-)
>

I really want to review this because I solved the same problem in our 
internal clock framework and want to make sure upstream doesn't go 
through the same mistakes. But haven't had the time. Hopefully, I'll go 
it before this gets accepted by Mike. I'll try to do it this week/weekend.

Thanks,
Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May 16 00:17:03 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 15 May 2013 21:17:03 -0700
Subject: [PATCH] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <CAPDyKFpZ6-O-zSyBVgGGFL4W+d=-k-qaXimUS12fgC=9TkUNVA@mail.gmail.com>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <CAPDyKFpZ6-O-zSyBVgGGFL4W+d=-k-qaXimUS12fgC=9TkUNVA@mail.gmail.com>
Message-ID: <51945DBF.60308@codeaurora.org>

On 05/15/2013 12:24 PM, Ulf Hansson wrote:
> On 1 May 2013 06:42, Saravana Kannan <skannan at codeaurora.org> wrote:

<snip>

>> -       /* migrate prepare */
>> -       if (clk->prepare_count)
>> +       /*
>> +        * Migrate prepare state between parents and prevent race with
>> +        * clk_enable().
>> +        *
>> +        * If the clock is not prepared, then a race with
>> +        * clk_enable/disable() is impossible since we already have the
>> +        * prepare lock (future calls to clk_enable() need to be preceded by
>> +        * a clk_prepare()).
>> +        *
>> +        * If the clock is prepared, migrate the prepared state to the new
>> +        * parent and also protect against a race with clk_enable() by
>> +        * forcing the clock and the new parent on.  This ensures that all
>> +        * future calls to clk_enable() are practically NOPs with respect to
>> +        * hardware and software states.
>> +        */
>
> Maybe an additional note about that since CLK_SET_PARENT_GATE is a
> prerequisite for doing migration of "prepare", we also interpreted
> this flags as it is acceptable to enable the clock(s) in this context.

Done. Sent v2 patch.

<snip>

>
> Looks good! Thanks for having another round to fixup this kind of
> tricky code. :-)

Thanks :-)

> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
>

Thanks again.

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May 16 00:23:03 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 15 May 2013 21:23:03 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130511142132.GA3200@sirena.org.uk>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
 <518D7C45.2090602@codeaurora.org> <20130511142132.GA3200@sirena.org.uk>
Message-ID: <51945F27.7010003@codeaurora.org>

On 05/11/2013 07:21 AM, Mark Brown wrote:
> On Fri, May 10, 2013 at 04:01:25PM -0700, Saravana Kannan wrote:
>> On 05/10/2013 03:18 PM, Mike Turquette wrote:
>
> Guys please delete irrelevant context from replies...
>
>>> One way to do it is to introduce a new config option,
>>> CONFIG_COMMON_CLK_DEBUG_CONTROL that would expose the controls for
>>> every clock in the existing debugfs infrastructure.  The downside to
>>> this approach is that it would get abused and ship in millions of
>>> Android products using horrible userspace hacks to control clocks.
>>> Maybe that's not our problem to solve, maybe it is.
>
>> We already have this for MSM. But I seem to have managed to keep our
>> userspace guys away from abusing it. YMMV.
>
> It's much harder when it's in the standard kernel and there's no contact
> with some of the users.  I've pushed back pretty strongly on some of
> your equivalent stuff for regulators for this reason.

Agreed. I don't really keep up with what's going on with the MSM regulators.

But at some point, I'll start requesting for this for debugfs. It's 
terribly handy to debug power issues, run unit tests and for debug 
sessions (debugfs. So, clearly!).

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May 16 00:28:50 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 15 May 2013 21:28:50 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130515044604.GA24524@sirena.org.uk>
References: <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum> <51927DEB.7090001@balister.org>
 <20130515044604.GA24524@sirena.org.uk>
Message-ID: <51946082.1000606@codeaurora.org>

On 05/14/2013 09:46 PM, Mark Brown wrote:
> On Tue, May 14, 2013 at 02:09:47PM -0400, Philip Balister wrote:
>
>> First of all, the driver that loads the bitstream into the fpga
>> fabric does not know ANYTHING about what the bitstream does. So it
>> cannot do any setup based on the contents of the file that is
>> loaded. (And this can also be loaded during the SoC bootup,
>> bypassing this driver completely)
>
> This is a problem that is going to need to be fixed - there will be some
> things going on the FPGAs that do need drivers and so there needs to be
> some way to instantiate a driver for a FPGA image.  Things like adding
> extra DT blobs along with the FPGA image have been talked about
>
>> Second, there are four clocks that feed the FPGA fabric. We will
>> want to set these clocks from user space somehow. It is perfectly
>> valid to use a uio driver to interface with logic in the fpga. If we
>> take the approach of using such general purpose techniques to
>> interface with fpga logic, we must have ways for the user to control
>> the fpga clocks.
>
> Right, and if the specific device is being controlled by UIO then having
> UIO create some clocks makes sense but then that should be integrated
> into the UIO instantiation rather than done as a separate thing.

Agreed. I was about to reply with exactly the same point. I haven't done 
any UIO coding, but that device file will eventually have to be opened. 
Turn on the clocks in the open and turn them off at close.

Rate to request can be a DT property.

-Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From skannan at codeaurora.org  Thu May 16 00:34:03 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 15 May 2013 21:34:03 -0700
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing
 is done
In-Reply-To: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
References: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
Message-ID: <519461BB.3010209@codeaurora.org>

On 05/09/2013 11:35 AM, Saravana Kannan wrote:
> With deferred probing, late_initcall() is too soon to declare a clock as
> unused. Wait for deferred probing to finish before declaring a clock as
> unused. Since deferred probing is done in late_initcall(), do the unused
> check to late_initcall_sync.
>
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> ---
>   drivers/clk/clk.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index fe4055f..5ecb64c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -534,7 +534,7 @@ static int clk_disable_unused(void)
>
>   	return 0;
>   }
> -late_initcall(clk_disable_unused);
> +late_initcall_sync(clk_disable_unused);
>
>   /***    helper functions   ***/

Mike,

Thoughts? Picking it up? Removing the existing auto-disable code (I 
think they are still useful)?

-Saravana


-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From horms+renesas at verge.net.au  Thu May 16 00:48:01 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Thu, 16 May 2013 13:48:01 +0900
Subject: [PATCH] ARM: shmobile: marzen: Use error values in usb_power_*
Message-ID: <1368679681-10779-1-git-send-email-horms+renesas@verge.net.au>

This patch updates the marzen board code as if USB PHY isn't enabled
they phy will have a value set by ERR_PTR() rather than be NULL.

Without this patch a NULL pointer dereference  and kernel panic
occurs on initialisation of USB on marzen.

This resolves a regression introduced in 3.10-rc1 by
b7fa5c2aec5be083eb2719b405089703608e9bc6
("usb: phy: return -ENXIO when PHY layer isn't enabled").

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 9105285..b9594e9 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -212,8 +212,8 @@ static struct platform_device *marzen_devices[] __initdata = {
 static struct usb_phy *phy;
 static int usb_power_on(struct platform_device *pdev)
 {
-	if (!phy)
-		return -EIO;
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
 
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_get_sync(&pdev->dev);
@@ -225,7 +225,7 @@ static int usb_power_on(struct platform_device *pdev)
 
 static void usb_power_off(struct platform_device *pdev)
 {
-	if (!phy)
+	if (IS_ERR(phy))
 		return;
 
 	usb_phy_shutdown(phy);
-- 
1.8.2.1



From horms at verge.net.au  Thu May 16 01:04:53 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 16 May 2013 14:04:53 +0900
Subject: linux-next: manual merge of the renesas tree with Linus' tree
In-Reply-To: <20130516132253.8865ca7b6503bd6fe9e6b05a@canb.auug.org.au>
References: <20130516132253.8865ca7b6503bd6fe9e6b05a@canb.auug.org.au>
Message-ID: <20130516050450.GA13842@verge.net.au>

On Thu, May 16, 2013 at 01:22:53PM +1000, Stephen Rothwell wrote:
> Hi Simon,
> 
> Today's linux-next merge of the renesas tree got a conflict in
> arch/arm/mach-shmobile/board-lager.c between commit 65be2de17aae ("ARM:
> shmobile: use r8a7790 timer setup code on Lager") from Linus' tree and
> commit 993340a1390d ("ARM: shmobile: use r8a7790 timer setup code on
> Lager") from the renesas tree.
> 
> These are the same patch but different commits :-( and there are further
> commits touching this file in the renesas tree.  Please clean up your
> tree and remove anything that has already gone upstream as different
> patches.  I used the renesas tree version of this file.


Sorry about that. I am working on re-basing my branches on
top of v3.10-rc1 and I have confirmed that in my current local
branches the problem you describe is no longer present.
I plan to push the refreshed branches, including a new next branch
for linux-next, once a few bug-fix patches have been reviewed.



From vinod.koul at intel.com  Thu May 16 01:05:49 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 10:35:49 +0530
Subject: [PATCH 36/39] dmaengine: ste_dma40: Allow memcpy channels to
 be configured from DT
In-Reply-To: <1368611522-9984-37-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-37-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516050549.GE27639@intel.com>

On Wed, May 15, 2013 at 10:51:59AM +0100, Lee Jones wrote:
> At this moment in time the memcpy channels which can be used by the D40
> are fixed, as each supported platform in Mainline uses the same ones.
> However, platforms do exist which don't follow this convention, so
> these will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
Acked-by: Vinod Koul <vinod.koul at intel.com>

> ---
>  .../devicetree/bindings/dma/ste-dma40.txt          |    2 +
>  drivers/dma/ste_dma40.c                            |   40 ++++++++++++++++----
>  include/linux/platform_data/dma-ste-dma40.h        |    2 +
>  3 files changed, 36 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> index 2679a87..aa272d8 100644
> --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
> +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> @@ -6,6 +6,7 @@ Required properties:
>  - reg-names: Names of the above areas to use during resource look-up
>  - interrupt: Should contain the DMAC interrupt number
>  - #dma-cells: must be <3>
> +- memcpy-channels: Channels to be used for memcpy
>  
>  Optional properties:
>  - dma-channels: Number of channels supported by hardware - if not present
> @@ -21,6 +22,7 @@ Example:
>  		interrupts = <0 25 0x4>;
>  
>  		#dma-cells = <2>;
> +		memcpy-channels  = <56 57 58 59 60>;
>  		dma-channels = <8>;
>  	};
>  
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 76c255f..ae462d3 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -58,6 +58,8 @@
>  #define D40_ALLOC_PHY		BIT(30)
>  #define D40_ALLOC_LOG_FREE	0
>  
> +#define D40_MEMCPY_MAX_CHANS	8
> +
>  /* Reserved event lines for memcpy only. */
>  #define DB8500_DMA_MEMCPY_EV_0	51
>  #define DB8500_DMA_MEMCPY_EV_1	56
> @@ -522,6 +524,8 @@ struct d40_gen_dmac {
>   * @phy_start: Physical memory start of the DMA registers.
>   * @phy_size: Size of the DMA register map.
>   * @irq: The IRQ number.
> + * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
> + * transfers).
>   * @num_phy_chans: The number of physical channels. Read from HW. This
>   * is the number of available channels for this driver, not counting "Secure
>   * mode" allocated physical channels.
> @@ -565,6 +569,7 @@ struct d40_base {
>  	phys_addr_t			  phy_start;
>  	resource_size_t			  phy_size;
>  	int				  irq;
> +	int				  num_memcpy_chans;
>  	int				  num_phy_chans;
>  	int				  num_log_chans;
>  	struct device_dma_parameters	  dma_parms;
> @@ -2938,7 +2943,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
>  	}
>  
>  	d40_chan_init(base, &base->dma_memcpy, base->log_chans,
> -		      base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
> +		      base->num_log_chans, base->num_memcpy_chans);
>  
>  	dma_cap_zero(base->dma_memcpy.cap_mask);
>  	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
> @@ -3139,6 +3144,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
>  	struct d40_base *base = NULL;
>  	int num_log_chans = 0;
>  	int num_phy_chans;
> +	int num_memcpy_chans;
>  	int clk_ret = -EINVAL;
>  	int i;
>  	u32 pid;
> @@ -3209,6 +3215,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
>  	else
>  		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
>  
> +	/* The number of channels used for memcpy */
> +	if (plat_data->num_of_memcpy_chans)
> +		num_memcpy_chans = plat_data->num_of_memcpy_chans;
> +	else
> +		num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
> +
>  	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
>  
>  	dev_info(&pdev->dev,
> @@ -3216,7 +3228,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
>  		 rev, res->start, num_phy_chans, num_log_chans);
>  
>  	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
> -		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
> +		       (num_phy_chans + num_log_chans + num_memcpy_chans) *
>  		       sizeof(struct d40_chan), GFP_KERNEL);
>  
>  	if (base == NULL) {
> @@ -3226,6 +3238,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
>  
>  	base->rev = rev;
>  	base->clk = clk;
> +	base->num_memcpy_chans = num_memcpy_chans;
>  	base->num_phy_chans = num_phy_chans;
>  	base->num_log_chans = num_log_chans;
>  	base->phy_start = res->start;
> @@ -3469,12 +3482,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
>  			       struct device_node *np)
>  {
>  	struct stedma40_platform_data *pdata;
> -
> -	/*
> -	 * FIXME: Fill in this routine as more support is added.
> -	 * First platform enabled (u8500) doens't need any extra
> -	 * properties to run, so this is fairly sparce currently.
> -	 */
> +	int num_memcpy = 0;
> +	const const __be32 *list;
>  
>  	pdata = devm_kzalloc(&pdev->dev,
>  			     sizeof(struct stedma40_platform_data),
> @@ -3482,6 +3491,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
>  	if (!pdata)
>  		return -ENOMEM;
>  
> +	list = of_get_property(np, "memcpy-channels", &num_memcpy);
> +	num_memcpy /= sizeof(*list);
> +
> +	if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
> +		d40_err(&pdev->dev,
> +			"Invalid number of memcpy channels specified (%d)\n",
> +			num_memcpy);
> +		return -EINVAL;
> +	}
> +	pdata->num_of_memcpy_chans = num_memcpy;
> +
> +	of_property_read_u32_array(np, "memcpy-channels",
> +				   dma40_memcpy_channels,
> +				   num_memcpy);
> +
>  	pdev->dev.platform_data = pdata;
>  
>  	return 0;
> diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
> index ceba6dc..1bb9b18 100644
> --- a/include/linux/platform_data/dma-ste-dma40.h
> +++ b/include/linux/platform_data/dma-ste-dma40.h
> @@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
>   * @num_of_soft_lli_chans: The number of channels that needs to be configured
>   * to use SoftLLI.
>   * @use_esram_lcla: flag for mapping the lcla into esram region
> + * @num_of_memcpy_chans: The number of channels reserved for memcpy.
>   * @num_of_phy_chans: The number of physical channels implemented in HW.
>   * 0 means reading the number of channels from DMA HW but this is only valid
>   * for 'multiple of 4' channels, like 8.
> @@ -141,6 +142,7 @@ struct stedma40_platform_data {
>  	int				*soft_lli_chans;
>  	int				 num_of_soft_lli_chans;
>  	bool				 use_esram_lcla;
> +	int				 num_of_memcpy_chans;
>  	int				 num_of_phy_chans;
>  };
>  
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 01:13:57 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 10:43:57 +0530
Subject: [PATCH 33/39] dmaengine: ste_dma40_ll: Use the BIT macro to
 replace ugly '(1 << x)'s
In-Reply-To: <1368611522-9984-34-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-34-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516051357.GF27639@intel.com>

On Wed, May 15, 2013 at 10:51:56AM +0100, Lee Jones wrote:
> The aim is to make the code that little more readable.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
Acked-by: Vinod Koul <vinod.koul at intel.com>

Hopefully all the BIT conversion in the driver are done in this

--
~Vinod
> ---
>  drivers/dma/ste_dma40_ll.c |   44 ++++++++++++++++++++++----------------------
>  1 file changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index 121c0ce..5ddd724 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -20,28 +20,28 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
>  	/* src is mem? -> increase address pos */
>  	if (cfg->dir ==  DMA_MEM_TO_DEV ||
>  	    cfg->dir ==  DMA_MEM_TO_MEM)
> -		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
> +		l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
>  
>  	/* dst is mem? -> increase address pos */
>  	if (cfg->dir ==  DMA_DEV_TO_MEM ||
>  	    cfg->dir ==  DMA_MEM_TO_MEM)
> -		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
> +		l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
>  
>  	/* src is hw? -> master port 1 */
>  	if (cfg->dir ==  DMA_DEV_TO_MEM ||
>  	    cfg->dir ==  DMA_DEV_TO_DEV)
> -		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
> +		l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
>  
>  	/* dst is hw? -> master port 1 */
>  	if (cfg->dir ==  DMA_MEM_TO_DEV ||
>  	    cfg->dir ==  DMA_DEV_TO_DEV)
> -		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
> +		l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
>  
> -	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
> +	l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
>  	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
>  	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
>  
> -	l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
> +	l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
>  	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
>  	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
>  
> @@ -58,39 +58,39 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
>  	if ((cfg->dir == DMA_DEV_TO_MEM) ||
>  	    (cfg->dir == DMA_DEV_TO_DEV)) {
>  		/* Set master port to 1 */
> -		src |= 1 << D40_SREG_CFG_MST_POS;
> +		src |= BIT(D40_SREG_CFG_MST_POS);
>  		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
>  
>  		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> -			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
> +			src |= BIT(D40_SREG_CFG_PHY_TM_POS);
>  		else
>  			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
>  	}
>  	if ((cfg->dir == DMA_MEM_TO_DEV) ||
>  	    (cfg->dir == DMA_DEV_TO_DEV)) {
>  		/* Set master port to 1 */
> -		dst |= 1 << D40_SREG_CFG_MST_POS;
> +		dst |= BIT(D40_SREG_CFG_MST_POS);
>  		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
>  
>  		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> -			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
> +			dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
>  		else
>  			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
>  	}
>  	/* Interrupt on end of transfer for destination */
> -	dst |= 1 << D40_SREG_CFG_TIM_POS;
> +	dst |= BIT(D40_SREG_CFG_TIM_POS);
>  
>  	/* Generate interrupt on error */
> -	src |= 1 << D40_SREG_CFG_EIM_POS;
> -	dst |= 1 << D40_SREG_CFG_EIM_POS;
> +	src |= BIT(D40_SREG_CFG_EIM_POS);
> +	dst |= BIT(D40_SREG_CFG_EIM_POS);
>  
>  	/* PSIZE */
>  	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
> -		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> +		src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
>  		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
>  	}
>  	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
> -		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> +		dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
>  		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
>  	}
>  
> @@ -100,14 +100,14 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
>  
>  	/* Set the priority bit to high for the physical channel */
>  	if (cfg->high_priority) {
> -		src |= 1 << D40_SREG_CFG_PRI_POS;
> -		dst |= 1 << D40_SREG_CFG_PRI_POS;
> +		src |= BIT(D40_SREG_CFG_PRI_POS);
> +		dst |= BIT(D40_SREG_CFG_PRI_POS);
>  	}
>  
>  	if (cfg->src_info.big_endian)
> -		src |= 1 << D40_SREG_CFG_LBE_POS;
> +		src |= BIT(D40_SREG_CFG_LBE_POS);
>  	if (cfg->dst_info.big_endian)
> -		dst |= 1 << D40_SREG_CFG_LBE_POS;
> +		dst |= BIT(D40_SREG_CFG_LBE_POS);
>  
>  	*src_cfg = src;
>  	*dst_cfg = dst;
> @@ -157,15 +157,15 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
>  
>  	/* If this scatter list entry is the last one, no next link */
>  	if (next_lli == 0)
> -		lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
> +		lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
>  	else
>  		lli->reg_lnk = next_lli;
>  
>  	/* Set/clear interrupt generation on this link item.*/
>  	if (term_int)
> -		lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
> +		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
>  	else
> -		lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
> +		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
>  
>  	/* Post link */
>  	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 01:17:01 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 10:47:01 +0530
Subject: [PATCH 31/39] dmaengine: ste_dma40: Replace ST-E's home-brew
 DMA direction defs with generic ones
In-Reply-To: <1368611522-9984-32-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-32-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516051701.GG27639@intel.com>

On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
Nice :)

1) I dont see the STE macro getting removed, why do we need it
2) last i checked the direction values had a bit idfference b/w what you are
using and what dmaengine defines, so hopefully that is taken care of..

--
~Vinod
> ---
>  drivers/dma/ste_dma40.c    |   56 ++++++++++++++++++++++----------------------
>  drivers/dma/ste_dma40_ll.c |   24 +++++++++----------
>  2 files changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 08bc58a..483da16 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -78,7 +78,7 @@ static int dma40_memcpy_channels[] = {
>  /* Default configuration for physcial memcpy */
>  struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
>  	.mode = STEDMA40_MODE_PHYSICAL,
> -	.dir = STEDMA40_MEM_TO_MEM,
> +	.dir = DMA_MEM_TO_MEM,
>  
>  	.src_info.data_width = STEDMA40_BYTE_WIDTH,
>  	.src_info.psize = STEDMA40_PSIZE_PHY_1,
> @@ -92,7 +92,7 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
>  /* Default configuration for logical memcpy */
>  struct stedma40_chan_cfg dma40_memcpy_conf_log = {
>  	.mode = STEDMA40_MODE_LOGICAL,
> -	.dir = STEDMA40_MEM_TO_MEM,
> +	.dir = DMA_MEM_TO_MEM,
>  
>  	.src_info.data_width = STEDMA40_BYTE_WIDTH,
>  	.src_info.psize = STEDMA40_PSIZE_LOG_1,
> @@ -843,7 +843,7 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
>  		 * that uses linked lists.
>  		 */
>  		if (!(chan->phy_chan->use_soft_lli &&
> -			chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM))
> +			chan->dma_cfg.dir == DMA_DEV_TO_MEM))
>  			curr_lcla = d40_lcla_alloc_one(chan, desc);
>  
>  		first_lcla = curr_lcla;
> @@ -1311,12 +1311,12 @@ static void d40_config_set_event(struct d40_chan *d40c,
>  	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
>  
>  	/* Enable event line connected to device (or memcpy) */
> -	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
> -	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
> +	if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
> +	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
>  		__d40_config_set_event(d40c, event_type, event,
>  				       D40_CHAN_REG_SSLNK);
>  
> -	if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM)
> +	if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
>  		__d40_config_set_event(d40c, event_type, event,
>  				       D40_CHAN_REG_SDLNK);
>  }
> @@ -1774,7 +1774,7 @@ static int d40_validate_conf(struct d40_chan *d40c,
>  		res = -EINVAL;
>  	}
>  
> -	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
> +	if (conf->dir == DMA_DEV_TO_DEV) {
>  		/*
>  		 * DMAC HW supports it. Will be added to this driver,
>  		 * in case any dma client requires it.
> @@ -1905,11 +1905,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
>  	phys = d40c->base->phy_res;
>  	num_phy_chans = d40c->base->num_phy_chans;
>  
> -	if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
> +	if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
>  		log_num = 2 * dev_type;
>  		is_src = true;
> -	} else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
> -		   d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
> +	} else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
> +		   d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
>  		/* dst event lines are used for logical memcpy */
>  		log_num = 2 * dev_type + 1;
>  		is_src = false;
> @@ -1920,7 +1920,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
>  	event_line = D40_TYPE_TO_EVENT(dev_type);
>  
>  	if (!is_log) {
> -		if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
> +		if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
>  			/* Find physical half channel */
>  			if (d40c->dma_cfg.use_fixed_channel) {
>  				i = d40c->dma_cfg.phy_channel;
> @@ -2068,10 +2068,10 @@ static int d40_free_dma(struct d40_chan *d40c)
>  		return -EINVAL;
>  	}
>  
> -	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
> -	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
> +	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
> +	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
>  		is_src = false;
> -	else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
> +	else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
>  		is_src = true;
>  	else {
>  		chan_err(d40c, "Unknown direction\n");
> @@ -2133,10 +2133,10 @@ static bool d40_is_paused(struct d40_chan *d40c)
>  		goto _exit;
>  	}
>  
> -	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
> -	    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
> +	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
> +	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
>  		status = readl(chanbase + D40_CHAN_REG_SDLNK);
> -	} else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
> +	} else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
>  		status = readl(chanbase + D40_CHAN_REG_SSLNK);
>  	} else {
>  		chan_err(d40c, "Unknown direction\n");
> @@ -2387,12 +2387,12 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
>  	if (d40c->base->rev < 3)
>  		return;
>  
> -	if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
> -	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
> +	if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
> +	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
>  		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
>  
> -	if ((d40c->dma_cfg.dir ==  STEDMA40_MEM_TO_PERIPH) ||
> -	    (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
> +	if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
> +	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
>  		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
>  }
>  
> @@ -2423,11 +2423,11 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
>  
>  	switch (D40_DT_FLAGS_DIR(flags)) {
>  	case 0:
> -		cfg.dir = STEDMA40_MEM_TO_PERIPH;
> +		cfg.dir = DMA_MEM_TO_DEV;
>  		cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
>  		break;
>  	case 1:
> -		cfg.dir = STEDMA40_PERIPH_TO_MEM;
> +		cfg.dir = DMA_DEV_TO_MEM;
>  		cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
>  		break;
>  	}
> @@ -2473,7 +2473,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
>  	d40_set_prio_realtime(d40c);
>  
>  	if (chan_is_logical(d40c)) {
> -		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
> +		if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
>  			d40c->lcpa = d40c->base->lcpa_base +
>  				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
>  		else
> @@ -2746,12 +2746,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  	if (config->direction == DMA_DEV_TO_MEM) {
>  		config_addr = config->src_addr;
>  
> -		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
> +		if (cfg->dir != DMA_DEV_TO_MEM)
>  			dev_dbg(d40c->base->dev,
>  				"channel was not configured for peripheral "
>  				"to memory transfer (%d) overriding\n",
>  				cfg->dir);
> -		cfg->dir = STEDMA40_PERIPH_TO_MEM;
> +		cfg->dir = DMA_DEV_TO_MEM;
>  
>  		/* Configure the memory side */
>  		if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
> @@ -2762,12 +2762,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  	} else if (config->direction == DMA_MEM_TO_DEV) {
>  		config_addr = config->dst_addr;
>  
> -		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
> +		if (cfg->dir != DMA_MEM_TO_DEV)
>  			dev_dbg(d40c->base->dev,
>  				"channel was not configured for memory "
>  				"to peripheral transfer (%d) overriding\n",
>  				cfg->dir);
> -		cfg->dir = STEDMA40_MEM_TO_PERIPH;
> +		cfg->dir = DMA_MEM_TO_DEV;
>  
>  		/* Configure the memory side */
>  		if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index ab5a2a7..121c0ce 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -18,23 +18,23 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
>  	u32 l1 = 0; /* src */
>  
>  	/* src is mem? -> increase address pos */
> -	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
> -	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
> +	if (cfg->dir ==  DMA_MEM_TO_DEV ||
> +	    cfg->dir ==  DMA_MEM_TO_MEM)
>  		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
>  
>  	/* dst is mem? -> increase address pos */
> -	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
> -	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
> +	if (cfg->dir ==  DMA_DEV_TO_MEM ||
> +	    cfg->dir ==  DMA_MEM_TO_MEM)
>  		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
>  
>  	/* src is hw? -> master port 1 */
> -	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
> -	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
> +	if (cfg->dir ==  DMA_DEV_TO_MEM ||
> +	    cfg->dir ==  DMA_DEV_TO_DEV)
>  		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
>  
>  	/* dst is hw? -> master port 1 */
> -	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
> -	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
> +	if (cfg->dir ==  DMA_MEM_TO_DEV ||
> +	    cfg->dir ==  DMA_DEV_TO_DEV)
>  		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
>  
>  	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
> @@ -55,8 +55,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
>  	u32 src = 0;
>  	u32 dst = 0;
>  
> -	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
> -	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> +	if ((cfg->dir == DMA_DEV_TO_MEM) ||
> +	    (cfg->dir == DMA_DEV_TO_DEV)) {
>  		/* Set master port to 1 */
>  		src |= 1 << D40_SREG_CFG_MST_POS;
>  		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
> @@ -66,8 +66,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
>  		else
>  			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
>  	}
> -	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
> -	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> +	if ((cfg->dir == DMA_MEM_TO_DEV) ||
> +	    (cfg->dir == DMA_DEV_TO_DEV)) {
>  		/* Set master port to 1 */
>  		dst |= 1 << D40_SREG_CFG_MST_POS;
>  		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 01:18:20 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 10:48:20 +0530
Subject: [PATCH 35/39] dmaengine: ste_dma40_ll: Replace meaningless
 register set with comment
In-Reply-To: <1368611522-9984-36-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-36-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516051820.GH27639@intel.com>

On Wed, May 15, 2013 at 10:51:58AM +0100, Lee Jones wrote:
> Unsure of the author's intentions, rather than just removing the nop,
> we're replacing it with a comment containing the possible intention
> of the statement OR:ing with 0.
Would be worthwhile to check w/ Linus W on this (or check whom to blame)

--
~Vinod
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/dma/ste_dma40_ll.c |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index a035dfe..27b818d 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -182,8 +182,10 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
>  	else
>  		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
>  
> -	/* Post link */
> -	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
> +	/*
> +	 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
> +	 * Relink happens after transfer completion.
> +	 */
>  
>  	return 0;
>  }
> -- 
> 1.7.10.4
> 


From 21cnbao at gmail.com  Thu May 16 02:08:07 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 16 May 2013 14:08:07 +0800
Subject: [PATCH] ASoC: omap-hdmi-codec: make the driver common for other SoCs
Message-ID: <1368684487-8890-1-git-send-email-Baohua.Song@csr.com>

to support HDMI on CSR SiRFprimaII and atlasVI, we need one more HDMI pseudo
codec, rather than add a new driver, we can make omap HDMI codec common for
other SoCs as well. then the omap-hdmi codec becomes a generic HDMI pseudo-
codec as HDMI audio features depend on HDMI specification not on SoCs.

Cc: Ricardo Neri <ricardo.neri at ti.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 sound/soc/codecs/Kconfig                 |  4 ++--
 sound/soc/codecs/Makefile                |  4 ++--
 sound/soc/codecs/{omap-hdmi.c => hdmi.c} | 26 +++++++++++++-------------
 sound/soc/omap/omap-hdmi-card.c          |  2 +-
 4 files changed, 18 insertions(+), 18 deletions(-)
 rename sound/soc/codecs/{omap-hdmi.c => hdmi.c} (69%)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 2f45f00..d8c4f3d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -53,7 +53,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_MAX9877 if I2C
 	select SND_SOC_MC13783 if MFD_MC13XXX
 	select SND_SOC_ML26124 if I2C
-	select SND_SOC_OMAP_HDMI_CODEC if OMAP4_DSS_HDMI
+	select SND_SOC_HDMI_CODEC
 	select SND_SOC_PCM3008
 	select SND_SOC_RT5631 if I2C
 	select SND_SOC_SGTL5000 if I2C
@@ -287,7 +287,7 @@ config SND_SOC_MAX98095
 config SND_SOC_MAX9850
 	tristate
 
-config SND_SOC_OMAP_HDMI_CODEC
+config SND_SOC_HDMI_CODEC
        tristate
 
 config SND_SOC_PCM3008
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index b9e41c9..49ff127 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -41,7 +41,7 @@ snd-soc-max98095-objs := max98095.o
 snd-soc-max9850-objs := max9850.o
 snd-soc-mc13783-objs := mc13783.o
 snd-soc-ml26124-objs := ml26124.o
-snd-soc-omap-hdmi-codec-objs := omap-hdmi.o
+snd-soc-hdmi-codec-objs := hdmi.o
 snd-soc-pcm3008-objs := pcm3008.o
 snd-soc-rt5631-objs := rt5631.o
 snd-soc-sgtl5000-objs := sgtl5000.o
@@ -168,7 +168,7 @@ obj-$(CONFIG_SND_SOC_MAX98095)	+= snd-soc-max98095.o
 obj-$(CONFIG_SND_SOC_MAX9850)	+= snd-soc-max9850.o
 obj-$(CONFIG_SND_SOC_MC13783)	+= snd-soc-mc13783.o
 obj-$(CONFIG_SND_SOC_ML26124)	+= snd-soc-ml26124.o
-obj-$(CONFIG_SND_SOC_OMAP_HDMI_CODEC) += snd-soc-omap-hdmi-codec.o
+obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o
 obj-$(CONFIG_SND_SOC_PCM3008)	+= snd-soc-pcm3008.o
 obj-$(CONFIG_SND_SOC_RT5631)	+= snd-soc-rt5631.o
 obj-$(CONFIG_SND_SOC_SGTL5000)  += snd-soc-sgtl5000.o
diff --git a/sound/soc/codecs/omap-hdmi.c b/sound/soc/codecs/hdmi.c
similarity index 69%
rename from sound/soc/codecs/omap-hdmi.c
rename to sound/soc/codecs/hdmi.c
index 529d064..2bcae2b 100644
--- a/sound/soc/codecs/omap-hdmi.c
+++ b/sound/soc/codecs/hdmi.c
@@ -1,5 +1,5 @@
 /*
- * ALSA SoC codec driver for HDMI audio on OMAP processors.
+ * ALSA SoC codec driver for HDMI audio codecs.
  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  * Author: Ricardo Neri <ricardo.neri at ti.com>
  *
@@ -23,10 +23,10 @@
 
 #define DRV_NAME "hdmi-audio-codec"
 
-static struct snd_soc_codec_driver omap_hdmi_codec;
+static struct snd_soc_codec_driver hdmi_codec;
 
-static struct snd_soc_dai_driver omap_hdmi_codec_dai = {
-	.name = "omap-hdmi-hifi",
+static struct snd_soc_dai_driver hdmi_codec_dai = {
+	.name = "hdmi-hifi",
 	.playback = {
 		.channels_min = 2,
 		.channels_max = 8,
@@ -39,31 +39,31 @@ static struct snd_soc_dai_driver omap_hdmi_codec_dai = {
 	},
 };
 
-static int omap_hdmi_codec_probe(struct platform_device *pdev)
+static int hdmi_codec_probe(struct platform_device *pdev)
 {
-	return snd_soc_register_codec(&pdev->dev, &omap_hdmi_codec,
-			&omap_hdmi_codec_dai, 1);
+	return snd_soc_register_codec(&pdev->dev, &hdmi_codec,
+			&hdmi_codec_dai, 1);
 }
 
-static int omap_hdmi_codec_remove(struct platform_device *pdev)
+static int hdmi_codec_remove(struct platform_device *pdev)
 {
 	snd_soc_unregister_codec(&pdev->dev);
 	return 0;
 }
 
-static struct platform_driver omap_hdmi_codec_driver = {
+static struct platform_driver hdmi_codec_driver = {
 	.driver		= {
 		.name	= DRV_NAME,
 		.owner	= THIS_MODULE,
 	},
 
-	.probe		= omap_hdmi_codec_probe,
-	.remove		= omap_hdmi_codec_remove,
+	.probe		= hdmi_codec_probe,
+	.remove		= hdmi_codec_remove,
 };
 
-module_platform_driver(omap_hdmi_codec_driver);
+module_platform_driver(hdmi_codec_driver);
 
 MODULE_AUTHOR("Ricardo Neri <ricardo.neri at ti.com>");
-MODULE_DESCRIPTION("ASoC OMAP HDMI codec driver");
+MODULE_DESCRIPTION("ASoC generic HDMI codec driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/omap/omap-hdmi-card.c b/sound/soc/omap/omap-hdmi-card.c
index d4eaa92..7e66e9c 100644
--- a/sound/soc/omap/omap-hdmi-card.c
+++ b/sound/soc/omap/omap-hdmi-card.c
@@ -35,7 +35,7 @@ static struct snd_soc_dai_link omap_hdmi_dai = {
 	.cpu_dai_name = "omap-hdmi-audio-dai",
 	.platform_name = "omap-pcm-audio",
 	.codec_name = "hdmi-audio-codec",
-	.codec_dai_name = "omap-hdmi-hifi",
+	.codec_dai_name = "hdmi-hifi",
 };
 
 static struct snd_soc_card snd_soc_omap_hdmi = {
-- 
1.8.2.3



From sfr at canb.auug.org.au  Thu May 16 02:12:19 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 16 May 2013 16:12:19 +1000
Subject: linux-next: manual merge of the renesas tree with Linus' tree
In-Reply-To: <20130516050450.GA13842@verge.net.au>
References: <20130516132253.8865ca7b6503bd6fe9e6b05a@canb.auug.org.au>
 <20130516050450.GA13842@verge.net.au>
Message-ID: <20130516161219.cc475a1a7a5c3051672e11bd@canb.auug.org.au>

Hi Simon,

On Thu, 16 May 2013 14:04:53 +0900 Simon Horman <horms at verge.net.au> wrote:
>
> Sorry about that. I am working on re-basing my branches on
> top of v3.10-rc1 and I have confirmed that in my current local
> branches the problem you describe is no longer present.
> I plan to push the refreshed branches, including a new next branch
> for linux-next, once a few bug-fix patches have been reviewed.

Excellent, thanks.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From vinod.koul at intel.com  Thu May 16 02:08:50 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 11:38:50 +0530
Subject: [PATCH 39/39] dmaengine: ste_dma40: Fetch disabled channels
 from DT
In-Reply-To: <1368611522-9984-40-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-40-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516060850.GI27639@intel.com>

On Wed, May 15, 2013 at 10:52:02AM +0100, Lee Jones wrote:
> Some platforms have channels which are not available for normal use.
> This information is currently passed though platform data in internal
> BSP kernels. Once those platforms land, they'll need to configure them
> appropriately, so we may as well add the infrastructure.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
Acked-by: Vinod Koul <vinod.koul at intel.com>

> ---
>  Documentation/devicetree/bindings/dma/ste-dma40.txt |    2 ++
>  drivers/dma/ste_dma40.c                             |   17 ++++++++++++++++-
>  2 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> index aa272d8..bea5b73 100644
> --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
> +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> @@ -11,6 +11,7 @@ Required properties:
>  Optional properties:
>  - dma-channels: Number of channels supported by hardware - if not present
>  		the driver will attempt to obtain the information from H/W
> +- disabled-channels: Channels which can not be used
>  
>  Example:
>  
> @@ -23,6 +24,7 @@ Example:
>  
>  		#dma-cells = <2>;
>  		memcpy-channels  = <56 57 58 59 60>;
> +		disabled-channels  = <12>;
>  		dma-channels = <8>;
>  	};
>  
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 4e528dd..ffac822 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -3482,7 +3482,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
>  			       struct device_node *np)
>  {
>  	struct stedma40_platform_data *pdata;
> -	int num_phy = 0, num_memcpy = 0;
> +	int num_phy = 0, num_memcpy = 0, num_disabled = 0;
>  	const const __be32 *list;
>  
>  	pdata = devm_kzalloc(&pdev->dev,
> @@ -3511,6 +3511,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
>  				   dma40_memcpy_channels,
>  				   num_memcpy);
>  
> +	list = of_get_property(np, "disabled-channels", &num_disabled);
> +	num_disabled /= sizeof(*list);
> +
> +	if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
> +		d40_err(&pdev->dev,
> +			"Invalid number of disabled channels specified (%d)\n",
> +			num_disabled);
> +		return -EINVAL;
> +	}
> +
> +	of_property_read_u32_array(np, "disabled-channels",
> +				   pdata->disabled_channels,
> +				   num_disabled);
> +	pdata->disabled_channels[num_disabled] = -1;
> +
>  	pdev->dev.platform_data = pdata;
>  
>  	return 0;
> -- 
> 1.7.10.4
> 


From dirk.behme at de.bosch.com  Thu May 16 02:51:34 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Thu, 16 May 2013 08:51:34 +0200
Subject: [PATCH] i.MX6: Documentation: update from fsl,
 card-wired to non-removable
Message-ID: <1368687094-11385-1-git-send-email-dirk.behme@de.bosch.com>

With the commit 7f217794f (mmc: dt: Consolidate DT bindings),
the device tree properties used by various device drivers
for SD/MMC host controllers were standardized.  One of the changes
was that the property "fsl,card-wired", previously used by the
Freescale driver, was replaced with "non-removable". Fix the example
documentation regarding this.

Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>
---
 Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
index bcfdab5..3a7caf7 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding:
 
 Examples:
 usdhc at 0219c000 { /* uSDHC4 */
-	fsl,card-wired;
+	non-removable;
 	vmmc-supply = <&reg_3p3v>;
 	status = "okay";
 	pinctrl-names = "default";
-- 
1.8.2



From b35083 at freescale.com  Thu May 16 02:10:44 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:10:44 +0800
Subject: [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support
Message-ID: <1368684648-20826-1-git-send-email-b35083@freescale.com>

Vybird MVF600 is a heterogeneous dual-core eMPU using ARM Cortex-A5 and
Cortex-M4 cores. The kernel are implemented on the Cortex-A5 core.
The core is different with current I.MX serial. However, This SOC
still shares some IPs with I.MX serials, such as FEC, ESDHC, WATCHDOG,
I2C, ASRC and ESAI, This SOC also shares some IPs with ColdFire platform,
such as eDMA and DSPI. And this SOC still have its own IPs such as PIT,
SAI, UART, QuadSPI and DCU.

Jingchang Lu (4):
  ARM: imx: add MVF600 clock support
  ARM: imx: add initial support for MVF600
  ARM: dts: add SoC level device tree source for MVF600
  ARM: dts: add initial MVF600 Tower board dts support

 Documentation/devicetree/bindings/clock/mvf600-clock.txt |  26 ++
 arch/arm/boot/dts/Makefile                               |   3 +-
 arch/arm/boot/dts/mvf600-pinfunc.h                       | 810 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mvf600-twr.dts                         | 108 +++++
 arch/arm/boot/dts/mvf600.dtsi                            | 475 ++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                                |  15 +
 arch/arm/mach-imx/Makefile                               |   2 +
 arch/arm/mach-imx/clk-mvf600.c                           | 322 ++++++++++++++
 arch/arm/mach-imx/common.h                               |   1 +
 arch/arm/mach-imx/mach-mvf600.c                          |  70 +++
 include/dt-bindings/clock/mvf600-clock.h                 | 163 +++++++
 11 files changed, 1994 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
 create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
 create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
 create mode 100644 arch/arm/boot/dts/mvf600.dtsi
 create mode 100644 arch/arm/mach-imx/clk-mvf600.c
 create mode 100644 arch/arm/mach-imx/mach-mvf600.c
 create mode 100644 include/dt-bindings/clock/mvf600-clock.h




From lee.jones at linaro.org  Thu May 16 02:53:55 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 07:53:55 +0100
Subject: [PATCH 12/39] crypto: ux500/hash - Prepare clock before enabling
 it
In-Reply-To: <CACRpkdYdf1j+V516CigFeGKv1B+Mf4mZk8g3ZwYAwa=rDP=7vg@mail.gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-13-git-send-email-lee.jones@linaro.org>
 <CACRpkdYdf1j+V516CigFeGKv1B+Mf4mZk8g3ZwYAwa=rDP=7vg@mail.gmail.com>
Message-ID: <20130516065355.GA3269@gmail.com>

On Wed, 15 May 2013, Linus Walleij wrote:

> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > If we fail to prepare the ux500-hash clock before enabling it the
> > platform will fail to boot. Here we insure this happens.
> >
> > Cc: Herbert Xu <herbert at gondor.apana.org.au>
> > Cc: David S. Miller <davem at davemloft.net>
> > Cc: Andreas Westin <andreas.westin at stericsson.com>
> > Cc: linux-crypto at vger.kernel.org
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This patch seems to be totally independent of the other stuff
> in the patch series, and it even seems like an -rc fix to me
> (I don't think the crypto device works without this).
> 
> This should go into the crypto tree?

I agree. 

> Else please convince Herbert to give his ACK on this
> before I apply it.

Pleeeeaasseee Herbert, take this patch! :)

How's that?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From b35083 at freescale.com  Thu May 16 02:10:45 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:10:45 +0800
Subject: [PATCH v3 1/4] ARM: imx: add MVF600 clock support
In-Reply-To: <1368684648-20826-1-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
Message-ID: <1368684648-20826-2-git-send-email-b35083@freescale.com>

Add clock support for Vybrid MVF600. It uses dtc macro support to
define all clock IDs in mvf600-clock.h to keep clock IDs coherence
between kernel and DT.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  use DTC macro support to define these clock IDs.
  remove unused #include header lines.
  name clocks close to reference manual.

 .../devicetree/bindings/clock/mvf600-clock.txt     |  26 ++
 arch/arm/mach-imx/clk-mvf600.c                     | 322 +++++++++++++++++++++
 include/dt-bindings/clock/mvf600-clock.h           | 163 +++++++++++
 3 files changed, 511 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
 create mode 100644 arch/arm/mach-imx/clk-mvf600.c
 create mode 100644 include/dt-bindings/clock/mvf600-clock.h

diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
new file mode 100644
index 0000000..34c0abb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt
@@ -0,0 +1,26 @@
+* Clock bindings for Freescale Vybrid MVF600 SOC
+
+Required properties:
+- compatible: Should be "fsl,mvf600-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/mvf600-clock.h
+for the full list of MVF600 clock IDs.
+
+Examples:
+
+clks: ccm at 4006b000 {
+	compatible = "fsl,mvf600-ccm";
+	reg = <0x4006b000 0x1000>;
+	#clock-cells = <1>;
+};
+
+uart1: serial at 40028000 {
+	compatible = "fsl,mvf600-uart";
+	reg = <0x40028000 0x1000>;
+	interrupts = <0 62 0x04>;
+	clocks = <&clks MVF600_CLK_UART1>;
+	clock-names = "ipg";
+};
diff --git a/arch/arm/mach-imx/clk-mvf600.c b/arch/arm/mach-imx/clk-mvf600.c
new file mode 100644
index 0000000..58c0065
--- /dev/null
+++ b/arch/arm/mach-imx/clk-mvf600.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <dt-bindings/clock/mvf600-clock.h>
+
+#include "clk.h"
+
+#define CCM_CCR			(ccm_base + 0x00)
+#define CCM_CSR			(ccm_base + 0x04)
+#define CCM_CCSR		(ccm_base + 0x08)
+#define CCM_CACRR		(ccm_base + 0x0c)
+#define CCM_CSCMR1		(ccm_base + 0x10)
+#define CCM_CSCDR1		(ccm_base + 0x14)
+#define CCM_CSCDR2		(ccm_base + 0x18)
+#define CCM_CSCDR3		(ccm_base + 0x1c)
+#define CCM_CSCMR2		(ccm_base + 0x20)
+#define CCM_CSCDR4		(ccm_base + 0x24)
+#define CCM_CLPCR		(ccm_base + 0x2c)
+#define CCM_CISR		(ccm_base + 0x30)
+#define CCM_CIMR		(ccm_base + 0x34)
+#define CCM_CGPR		(ccm_base + 0x3c)
+#define CCM_CCGR0		(ccm_base + 0x40)
+#define CCM_CCGR1		(ccm_base + 0x44)
+#define CCM_CCGR2		(ccm_base + 0x48)
+#define CCM_CCGR3		(ccm_base + 0x4c)
+#define CCM_CCGR4		(ccm_base + 0x50)
+#define CCM_CCGR5		(ccm_base + 0x54)
+#define CCM_CCGR6		(ccm_base + 0x58)
+#define CCM_CCGR7		(ccm_base + 0x5c)
+#define CCM_CCGR8		(ccm_base + 0x60)
+#define CCM_CCGR9		(ccm_base + 0x64)
+#define CCM_CCGR10		(ccm_base + 0x68)
+#define CCM_CCGR11		(ccm_base + 0x6c)
+#define CCM_CMEOR0		(ccm_base + 0x70)
+#define CCM_CMEOR1		(ccm_base + 0x74)
+#define CCM_CMEOR2		(ccm_base + 0x78)
+#define CCM_CMEOR3		(ccm_base + 0x7c)
+#define CCM_CMEOR4		(ccm_base + 0x80)
+#define CCM_CMEOR5		(ccm_base + 0x84)
+#define CCM_CPPDSR		(ccm_base + 0x88)
+#define CCM_CCOWR		(ccm_base + 0x8c)
+#define CCM_CCPGR0		(ccm_base + 0x90)
+#define CCM_CCPGR1		(ccm_base + 0x94)
+#define CCM_CCPGR2		(ccm_base + 0x98)
+#define CCM_CCPGR3		(ccm_base + 0x9c)
+
+#define CCM_CCGRx_CGn(n)	((n) * 2)
+
+#define PFD_PLL1_BASE		(anatop_base + 0x2b0)
+#define PFD_PLL2_BASE		(anatop_base + 0x100)
+#define PFD_PLL3_BASE		(anatop_base + 0xf0)
+
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+
+/* sources for multiplexer clocks, this is used multiple times */
+static const char const *fast_sels[]	= { "firc", "fxosc", };
+static const char const *slow_sels[]	= { "sirc_32k", "sxosc", };
+static const char const *pll1_sels[]	= { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char const *pll2_sels[]	= { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char const *sys_sels[]	= { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char const *ddr_sels[]	= { "pll2_pfd2", "sys_sel", };
+static const char const *rmii_sels[]	= { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char const *enet_ts_sels[]	= { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char const *esai_sels[]	= { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *sai_sels[]	= { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *nfc_sels[]	= { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char const *qspi_sels[]	= { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char const *esdhc_sels[]	= { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char const *dcu_sels[]	= { "pll1_pfd2", "pll3_main", };
+static const char const *gpu_sels[]	= { "pll2_pfd2", "pll3_pfd2", };
+static const char const *vadc_sels[]	= { "pll6_main_div", "pll3_main_div", "pll3_main", };
+/* FTM counter clock source, not module clock */
+static const char const *ftm_ext_sels[]	= {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char const *ftm_fix_sels[]	= { "sxosc", "ipg_bus", };
+
+static struct clk_div_table pll4_main_div_table[] = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 6 },
+	{ .val = 3, .div = 8 },
+	{ .val = 4, .div = 10 },
+	{ .val = 5, .div = 12 },
+	{ .val = 6, .div = 14 },
+	{ .val = 7, .div = 16 },
+	{ }
+};
+
+static struct clk *clk[MVF600_CLK_END];
+static struct clk_onecell_data clk_data;
+
+int __init mvf600_clocks_init(void)
+{
+	struct device_node *np;
+
+	of_clk_init(NULL);
+
+	clk[MVF600_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+	clk[MVF600_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
+	clk[MVF600_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
+	clk[MVF600_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
+
+	clk[MVF600_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
+	clk[MVF600_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
+	clk[MVF600_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
+	clk[MVF600_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+
+	clk[MVF600_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-anatop");
+	anatop_base = of_iomap(np, 0);
+	WARN_ON(!anatop_base);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-ccm");
+	ccm_base = of_iomap(np, 0);
+	WARN_ON(!ccm_base);
+
+	clk[MVF600_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
+	clk[MVF600_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
+
+	clk[MVF600_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
+	clk[MVF600_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
+	clk[MVF600_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
+	clk[MVF600_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
+	clk[MVF600_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
+
+	clk[MVF600_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
+	clk[MVF600_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
+	clk[MVF600_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
+	clk[MVF600_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
+	clk[MVF600_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
+
+	clk[MVF600_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
+	clk[MVF600_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
+	clk[MVF600_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
+	clk[MVF600_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
+	clk[MVF600_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
+
+	clk[MVF600_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
+	/* Enet pll: fixed 50Mhz */
+	clk[MVF600_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
+	/* pll6: default 960Mhz */
+	clk[MVF600_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+	clk[MVF600_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
+	clk[MVF600_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
+	clk[MVF600_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
+	clk[MVF600_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
+	clk[MVF600_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
+	clk[MVF600_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
+	clk[MVF600_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
+
+	clk[MVF600_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
+	clk[MVF600_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
+	clk[MVF600_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+
+	clk[MVF600_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
+	clk[MVF600_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+
+	clk[MVF600_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
+	clk[MVF600_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
+	clk[MVF600_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
+	clk[MVF600_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
+	clk[MVF600_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
+	clk[MVF600_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
+
+	clk[MVF600_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
+	clk[MVF600_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
+	clk[MVF600_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
+	clk[MVF600_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
+	clk[MVF600_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
+	clk[MVF600_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
+
+	clk[MVF600_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
+	clk[MVF600_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+	clk[MVF600_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
+	clk[MVF600_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
+	clk[MVF600_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
+	clk[MVF600_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
+
+	clk[MVF600_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
+
+	clk[MVF600_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
+	clk[MVF600_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
+	clk[MVF600_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
+	clk[MVF600_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
+
+	clk[MVF600_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
+	clk[MVF600_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
+
+	clk[MVF600_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
+	clk[MVF600_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
+	clk[MVF600_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
+	clk[MVF600_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
+
+	clk[MVF600_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
+
+	clk[MVF600_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
+	clk[MVF600_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
+	clk[MVF600_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
+	clk[MVF600_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
+
+	clk[MVF600_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
+	clk[MVF600_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
+	clk[MVF600_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
+	clk[MVF600_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
+
+	/*
+	 * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
+	 * selectable clock sources, both use a common enable bit
+	 * in CCM_CSCDR1, selecting "dummy" clock as parent of
+	 * "ftm0_ext_fix" make it serve only for enable/disable.
+	 */
+	clk[MVF600_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
+	clk[MVF600_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
+	clk[MVF600_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
+	clk[MVF600_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
+	clk[MVF600_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
+	clk[MVF600_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
+	clk[MVF600_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
+	clk[MVF600_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
+	clk[MVF600_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
+	clk[MVF600_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
+	clk[MVF600_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
+	clk[MVF600_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
+
+	/* ftm(n)_clk are FTM module operation clock */
+	clk[MVF600_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
+	clk[MVF600_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
+	clk[MVF600_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
+	clk[MVF600_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
+
+	clk[MVF600_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
+	clk[MVF600_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
+	clk[MVF600_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
+	clk[MVF600_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+	clk[MVF600_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
+	clk[MVF600_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
+	clk[MVF600_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
+	clk[MVF600_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+
+	clk[MVF600_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
+	clk[MVF600_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
+	clk[MVF600_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
+	clk[MVF600_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
+
+	clk[MVF600_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
+	clk[MVF600_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
+	clk[MVF600_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
+	clk[MVF600_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
+
+	clk[MVF600_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
+	clk[MVF600_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
+	clk[MVF600_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
+	clk[MVF600_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
+
+	clk[MVF600_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
+	clk[MVF600_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
+	clk[MVF600_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
+	clk[MVF600_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
+
+	clk[MVF600_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
+	clk[MVF600_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
+	clk[MVF600_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
+	clk[MVF600_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
+
+	clk[MVF600_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
+	clk[MVF600_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
+	clk[MVF600_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
+	clk[MVF600_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
+	clk[MVF600_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
+
+	clk[MVF600_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
+	clk[MVF600_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
+	clk[MVF600_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
+
+	clk[MVF600_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
+	clk[MVF600_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
+	clk[MVF600_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
+	clk[MVF600_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
+	clk[MVF600_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
+
+	clk[MVF600_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
+	clk[MVF600_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
+	clk[MVF600_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
+	clk[MVF600_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
+
+	clk[MVF600_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
+
+	clk[MVF600_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
+	clk[MVF600_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+
+	clk_set_parent(clk[MVF600_CLK_QSPI0_SEL], clk[MVF600_CLK_PLL1_PFD4]);
+	clk_set_rate(clk[MVF600_CLK_QSPI0_X4_DIV], clk_get_rate(clk[MVF600_CLK_QSPI0_SEL]) / 2);
+	clk_set_rate(clk[MVF600_CLK_QSPI0_X2_DIV], clk_get_rate(clk[MVF600_CLK_QSPI0_X4_DIV]) / 2);
+	clk_set_rate(clk[MVF600_CLK_QSPI0_X1_DIV], clk_get_rate(clk[MVF600_CLK_QSPI0_X2_DIV]) / 2);
+
+	clk_set_parent(clk[MVF600_CLK_QSPI1_SEL], clk[MVF600_CLK_PLL1_PFD4]);
+	clk_set_rate(clk[MVF600_CLK_QSPI1_X4_DIV], clk_get_rate(clk[MVF600_CLK_QSPI1_SEL]) / 2);
+	clk_set_rate(clk[MVF600_CLK_QSPI1_X2_DIV], clk_get_rate(clk[MVF600_CLK_QSPI1_X4_DIV]) / 2);
+	clk_set_rate(clk[MVF600_CLK_QSPI1_X1_DIV], clk_get_rate(clk[MVF600_CLK_QSPI1_X2_DIV]) / 2);
+
+	clk_set_parent(clk[MVF600_CLK_SAI0_EN], clk[MVF600_CLK_AUDIO_EXT]);
+	clk_set_parent(clk[MVF600_CLK_SAI1_EN], clk[MVF600_CLK_AUDIO_EXT]);
+	clk_set_parent(clk[MVF600_CLK_SAI2_EN], clk[MVF600_CLK_AUDIO_EXT]);
+	clk_set_parent(clk[MVF600_CLK_SAI3_EN], clk[MVF600_CLK_AUDIO_EXT]);
+
+	/* Add the clocks to provider list */
+	clk_data.clks = clk;
+	clk_data.clk_num = ARRAY_SIZE(clk);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	return 0;
+}
diff --git a/include/dt-bindings/clock/mvf600-clock.h b/include/dt-bindings/clock/mvf600-clock.h
new file mode 100644
index 0000000..7c43c8a
--- /dev/null
+++ b/include/dt-bindings/clock/mvf600-clock.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_MVF600_H
+#define __DT_BINDINGS_CLOCK_MVF600_H
+
+#define MVF600_CLK_DUMMY		0
+#define MVF600_CLK_SIRC_128K		1
+#define MVF600_CLK_SIRC_32K		2
+#define MVF600_CLK_FIRC			3
+#define MVF600_CLK_SXOSC		4
+#define MVF600_CLK_FXOSC		5
+#define MVF600_CLK_FXOSC_HALF		6
+#define MVF600_CLK_SLOW_CLK_SEL		7
+#define MVF600_CLK_FASK_CLK_SEL		8
+#define MVF600_CLK_AUDIO_EXT		9
+#define MVF600_CLK_ENET_EXT		10
+#define MVF600_CLK_PLL1_MAIN		11
+#define MVF600_CLK_PLL1_PFD1		12
+#define MVF600_CLK_PLL1_PFD2		13
+#define MVF600_CLK_PLL1_PFD3		14
+#define MVF600_CLK_PLL1_PFD4		15
+#define MVF600_CLK_PLL2_MAIN		16
+#define MVF600_CLK_PLL2_PFD1		17
+#define MVF600_CLK_PLL2_PFD2		18
+#define MVF600_CLK_PLL2_PFD3		19
+#define MVF600_CLK_PLL2_PFD4		20
+#define MVF600_CLK_PLL3_MAIN		21
+#define MVF600_CLK_PLL3_PFD1		22
+#define MVF600_CLK_PLL3_PFD2		23
+#define MVF600_CLK_PLL3_PFD3		24
+#define MVF600_CLK_PLL3_PFD4		25
+#define MVF600_CLK_PLL4_MAIN		26
+#define MVF600_CLK_PLL5_MAIN		27
+#define MVF600_CLK_PLL6_MAIN		28
+#define MVF600_CLK_PLL3_MAIN_DIV	29
+#define MVF600_CLK_PLL4_MAIN_DIV	30
+#define MVF600_CLK_PLL6_MAIN_DIV	31
+#define MVF600_CLK_PLL1_PFD_SEL		32
+#define MVF600_CLK_PLL2_PFD_SEL		33
+#define MVF600_CLK_SYS_SEL		34
+#define MVF600_CLK_DDR_SEL		35
+#define MVF600_CLK_SYS_BUS		36
+#define MVF600_CLK_PLATFORM_BUS		37
+#define MVF600_CLK_IPG_BUS		38
+#define MVF600_CLK_UART0		39
+#define MVF600_CLK_UART1		40
+#define MVF600_CLK_UART2		41
+#define MVF600_CLK_UART3		42
+#define MVF600_CLK_UART4		43
+#define MVF600_CLK_UART5		44
+#define MVF600_CLK_PIT			45
+#define MVF600_CLK_I2C0			46
+#define MVF600_CLK_I2C1			47
+#define MVF600_CLK_I2C2			48
+#define MVF600_CLK_I2C3			49
+#define MVF600_CLK_FTM0_EXT_SEL		50
+#define MVF600_CLK_FTM0_FIX_SEL		51
+#define MVF600_CLK_FTM0_EXT_FIX_EN	52
+#define MVF600_CLK_FTM1_EXT_SEL		53
+#define MVF600_CLK_FTM1_FIX_SEL		54
+#define MVF600_CLK_FTM1_EXT_FIX_EN	55
+#define MVF600_CLK_FTM2_EXT_SEL		56
+#define MVF600_CLK_FTM2_FIX_SEL		57
+#define MVF600_CLK_FTM2_EXT_FIX_EN	58
+#define MVF600_CLK_FTM3_EXT_SEL		59
+#define MVF600_CLK_FTM3_FIX_SEL		60
+#define MVF600_CLK_FTM3_EXT_FIX_EN	61
+#define MVF600_CLK_FTM0			62
+#define MVF600_CLK_FTM1			63
+#define MVF600_CLK_FTM2			64
+#define MVF600_CLK_FTM3			65
+#define MVF600_CLK_ENET_50M		66
+#define MVF600_CLK_ENET_25M		67
+#define MVF600_CLK_ENET_SEL		68
+#define MVF600_CLK_ENET			69
+#define MVF600_CLK_ENET_TS_SEL		70
+#define MVF600_CLK_ENET_TS		71
+#define MVF600_CLK_DSPI0		72
+#define MVF600_CLK_DSPI1		73
+#define MVF600_CLK_DSPI2		74
+#define MVF600_CLK_DSPI3		75
+#define MVF600_CLK_WDT			76
+#define MVF600_CLK_ESDHC0_SEL		77
+#define MVF600_CLK_ESDHC0_EN		78
+#define MVF600_CLK_ESDHC0_DIV		79
+#define MVF600_CLK_ESDHC0		80
+#define MVF600_CLK_ESDHC1_SEL		81
+#define MVF600_CLK_ESDHC1_EN		82
+#define MVF600_CLK_ESDHC1_DIV		83
+#define MVF600_CLK_ESDHC1		84
+#define MVF600_CLK_DCU0_SEL		85
+#define MVF600_CLK_DCU0_EN		86
+#define MVF600_CLK_DCU0_DIV		87
+#define MVF600_CLK_DCU0			88
+#define MVF600_CLK_DCU1_SEL		89
+#define MVF600_CLK_DCU1_EN		90
+#define MVF600_CLK_DCU1_DIV		91
+#define MVF600_CLK_DCU1			92
+#define MVF600_CLK_ESAI_SEL		93
+#define MVF600_CLK_ESAI_EN		94
+#define MVF600_CLK_ESAI_DIV		95
+#define MVF600_CLK_ESAI			96
+#define MVF600_CLK_SAI0_SEL		97
+#define MVF600_CLK_SAI0_EN		98
+#define MVF600_CLK_SAI0_DIV		99
+#define MVF600_CLK_SAI0			100
+#define MVF600_CLK_SAI1_SEL		101
+#define MVF600_CLK_SAI1_EN		102
+#define MVF600_CLK_SAI1_DIV		103
+#define MVF600_CLK_SAI1			104
+#define MVF600_CLK_SAI2_SEL		105
+#define MVF600_CLK_SAI2_EN		106
+#define MVF600_CLK_SAI2_DIV		107
+#define MVF600_CLK_SAI2			108
+#define MVF600_CLK_SAI3_SEL		109
+#define MVF600_CLK_SAI3_EN		110
+#define MVF600_CLK_SAI3_DIV		111
+#define MVF600_CLK_SAI3			112
+#define MVF600_CLK_USBC0		113
+#define MVF600_CLK_USBC1		114
+#define MVF600_CLK_QSPI0_SEL		115
+#define MVF600_CLK_QSPI0_EN		116
+#define MVF600_CLK_QSPI0_X4_DIV		117
+#define MVF600_CLK_QSPI0_X2_DIV		118
+#define MVF600_CLK_QSPI0_X1_DIV		119
+#define MVF600_CLK_QSPI1_SEL		120
+#define MVF600_CLK_QSPI1_EN		121
+#define MVF600_CLK_QSPI1_X4_DIV		122
+#define MVF600_CLK_QSPI1_X2_DIV		123
+#define MVF600_CLK_QSPI1_X1_DIV		124
+#define MVF600_CLK_QSPI0		125
+#define MVF600_CLK_QSPI1		126
+#define MVF600_CLK_NFC_SEL		127
+#define MVF600_CLK_NFC_EN		128
+#define MVF600_CLK_NFC_PRE_DIV		129
+#define MVF600_CLK_NFC_FRAC_DIV		130
+#define MVF600_CLK_NFC_INV		131
+#define MVF600_CLK_NFC			132
+#define MVF600_CLK_VADC_SEL		133
+#define MVF600_CLK_VADC_EN		134
+#define MVF600_CLK_VADC_DIV		135
+#define MVF600_CLK_VADC_DIV_HALF	136
+#define MVF600_CLK_VADC			137
+#define MVF600_CLK_ADC0			138
+#define MVF600_CLK_ADC1			139
+#define MVF600_CLK_DAC0			140
+#define MVF600_CLK_DAC1			141
+#define MVF600_CLK_FLEXCAN0		142
+#define MVF600_CLK_FLEXCAN1		143
+#define MVF600_CLK_ASRC			144
+#define MVF600_CLK_GPU_SEL		145
+#define MVF600_CLK_GPU_EN		146
+#define MVF600_CLK_GPU2D		147
+#define MVF600_CLK_END			148
+
+#endif /* __DT_BINDINGS_CLOCK_MVF600_H */
-- 
1.8.0




From b35083 at freescale.com  Thu May 16 02:10:48 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:10:48 +0800
Subject: [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support
In-Reply-To: <1368684648-20826-1-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
Message-ID: <1368684648-20826-5-git-send-email-b35083@freescale.com>

Add initial MVF600 Tower board  support with uart, fec,
i2c, qspi, and sai enabled.

Signed-off-by: Xiaochun Li <b41219 at freescale.com>
Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  split DTS support to SoC and board patches.
  sort node by alphabet order of labels.

 arch/arm/boot/dts/Makefile       |   3 +-
 arch/arm/boot/dts/mvf600-twr.dts | 108 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/mvf600-twr.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 87e603c..968164b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -122,7 +122,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
 	imx6q-sbc6x.dtb \
-	imx6sl-evk.dtb
+	imx6sl-evk.dtb \
+	mvf600-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx23-olinuxino.dtb \
 	imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts
new file mode 100644
index 0000000..fe2e0e6
--- /dev/null
+++ b/arch/arm/boot/dts/mvf600-twr.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "mvf600.dtsi"
+
+/ {
+	model = "MVF600 Tower Board";
+	compatible = "fsl,mvf600-twr", "fsl,mvf600";
+
+	chosen {
+		bootargs = "console=ttyLP1,115200";
+	};
+
+	memory {
+		reg = <0x80000000 0x8000000>;
+	};
+
+	clocks {
+		audio_ext {
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
+		enet_ext {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
+	sound {
+		compatible = "fsl,mvf600-audio-sgtl5000";
+		model = "mvf600-sgtl5000";
+		sai-controller = <&sai2>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+	};
+
+};
+
+&fec0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec0_1>;
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1_1>;
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_1>;
+
+	codec: sgtl5000 at 0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&clks MVF600_CLK_SAI2>;
+	};
+};
+
+&qspi0 { /* QuadSPI0 */
+	fsl,spi-num-chipselects = <1>;
+	fsl,spi-flash-chipselects = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi0_1>;
+	status = "okay";
+
+	flash: s25fl128s at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl128s";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		linux,modalias = "m25p80";
+		modal = "s25fl128s";
+		partition at 0 {
+			label = "s25fl128s";
+			reg = <0x0 0x1000000>;
+		};
+	};
+};
+
+&sai2 {
+	fsl,mode = "i2s-slave";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2_1>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
-- 
1.8.0




From b35083 at freescale.com  Thu May 16 02:10:46 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:10:46 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <1368684648-20826-1-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
Message-ID: <1368684648-20826-3-git-send-email-b35083@freescale.com>

Add initial support for Vybrid MVF600 SoC.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  remove unused #include header lines.
  use common mxc restart function.

 arch/arm/mach-imx/Kconfig       | 15 +++++++++
 arch/arm/mach-imx/Makefile      |  2 ++
 arch/arm/mach-imx/common.h      |  1 +
 arch/arm/mach-imx/mach-mvf600.c | 70 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 88 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-mvf600.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a402248..b9c01a1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -835,6 +835,21 @@ config SOC_IMX6SL
 	help
 	  This enables support for Freescale i.MX6 SoloLite processor.
 
+config SOC_MVF600
+	bool "Vybrid Family MVF600 support"
+	select CPU_V7
+	select ARM_GIC
+	select CLKSRC_OF
+	select PINCTRL
+	select PINCTRL_MVF600
+	select MVF600_PIT_TIMER
+	select PL310_ERRATA_588369 if CACHE_PL310
+	select PL310_ERRATA_727915 if CACHE_PL310
+	select PL310_ERRATA_769419 if CACHE_PL310
+
+	help
+	  This enable support for Freescale Vybrid MVF600 processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 2a4754d..28d8b4c 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -112,4 +112,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
+obj-$(CONFIG_SOC_MVF600) += clk-mvf600.o mach-mvf600.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 208e76f..55cdba0 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -70,6 +70,7 @@ extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
 extern int imx6sl_clocks_init(void);
+extern int mvf600_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
diff --git a/arch/arm/mach-imx/mach-mvf600.c b/arch/arm/mach-imx/mach-mvf600.c
new file mode 100644
index 0000000..deffe74
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mvf600.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/system_misc.h>
+
+#include "common.h"
+
+static void __init mvf600_init_machine(void)
+{
+	mxc_arch_reset_init_dt();
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init mvf600_init_irq(void)
+{
+	struct device_node *np;
+	void __iomem *mscm_base;
+	int i;
+
+	l2x0_of_init(0, ~0UL);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm");
+	mscm_base = of_iomap(np, 0);
+	if (!mscm_base)
+		return;
+
+	/* route all shared peripheral interrupts to CP0 */
+	for (i = 0; i < 111; i++)
+		__raw_writew(1, mscm_base + 0x880 + 2 * i);
+
+	iounmap(mscm_base);
+
+	irqchip_init();
+}
+
+static void __init mvf600_init_time(void)
+{
+	mvf600_clocks_init();
+	clocksource_of_init();
+}
+
+static const char *mvf600_dt_compat[] __initdata = {
+	"fsl,mvf600",
+	NULL,
+};
+
+DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)")
+	.init_irq	= mvf600_init_irq,
+	.init_time	= mvf600_init_time,
+	.init_machine   = mvf600_init_machine,
+	.dt_compat	= mvf600_dt_compat,
+	.restart	= mxc_restart,
+MACHINE_END
-- 
1.8.0




From b35083 at freescale.com  Thu May 16 02:10:47 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:10:47 +0800
Subject: [PATCH v3 3/4] ARM: dts: add SoC level device tree source for MVF600
In-Reply-To: <1368684648-20826-1-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
Message-ID: <1368684648-20826-4-git-send-email-b35083@freescale.com>

Add SoC level device tree source for Freescale Vybrid MVF600.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  define mvf600 pinfunc ID as <mux_reg input_reg mux_mode input_val>.
  clean up code.

 arch/arm/boot/dts/mvf600-pinfunc.h | 810 +++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mvf600.dtsi      | 475 ++++++++++++++++++++++
 2 files changed, 1285 insertions(+)
 create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
 create mode 100644 arch/arm/boot/dts/mvf600.dtsi

diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h
new file mode 100644
index 0000000..355c580
--- /dev/null
+++ b/arch/arm/boot/dts/mvf600-pinfunc.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_MVF600_PINFUNC_H
+#define __DTS_MVF600_PINFUNC_H
+
+/*
+ * The pin function ID for MVF600 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+
+#define ALT0	0x0
+#define ALT1	0x1
+#define ALT2	0x2
+#define ALT3	0x3
+#define ALT4	0x4
+#define ALT5	0x5
+#define ALT6	0x6
+#define ALT7	0x7
+
+
+#define MVF600_PAD_PTA6__GPIO_0			0x000 0x000 ALT0 0x0
+#define MVF600_PAD_PTA6__RMII_CLKOUT		0x000 0x000 ALT1 0x0
+#define MVF600_PAD_PTA6__RMII_CLKIN		0x000 0x2F0 ALT2 0x0
+#define MVF600_PAD_PTA6__DCU1_TCON11		0x000 0x000 ALT4 0x0
+#define MVF600_PAD_PTA6__DCU1_R2		0x000 0x000 ALT7 0x0
+#define MVF600_PAD_PTA8__GPIO_1			0x004 0x000 ALT0 0x0
+#define MVF600_PAD_PTA8__TCLK			0x004 0x000 ALT1 0x0
+#define MVF600_PAD_PTA8__DCU0_R0		0x004 0x000 ALT4 0x0
+#define MVF600_PAD_PTA8__MLB_CLK		0x004 0x354 ALT7 0x0
+#define MVF600_PAD_PTA9__GPIO_2			0x008 0x000 ALT0 0x0
+#define MVF600_PAD_PTA9__TDI			0x008 0x000 ALT1 0x0
+#define MVF600_PAD_PTA9__RMII_CLKOUT		0x008 0x000 ALT2 0x0
+#define MVF600_PAD_PTA9__RMII_CLKIN		0x008 0x2F0 ALT3 0x1
+#define MVF600_PAD_PTA9__DCU0_R1		0x008 0x000 ALT4 0x0
+#define MVF600_PAD_PTA9__WDOG_B			0x008 0x000 ALT6 0x0
+#define MVF600_PAD_PTA10__GPIO_3		0x00C 0x000 ALT0 0x0
+#define MVF600_PAD_PTA10__TDO			0x00C 0x000 ALT1 0x0
+#define MVF600_PAD_PTA10__EXT_AUDIO_MCLK	0x00C 0x2EC ALT2 0x0
+#define MVF600_PAD_PTA10__DCU0_G0		0x00C 0x000 ALT4 0x0
+#define MVF600_PAD_PTA10__ENET_TS_CLKIN		0x00C 0x2F4 ALT6 0x0
+#define MVF600_PAD_PTA10__MLB_SIGNAL		0x00C 0x35C ALT7 0x0
+#define MVF600_PAD_PTA11__GPIO_4		0x010 0x000 ALT0 0x0
+#define MVF600_PAD_PTA11__TMS			0x010 0x000 ALT1 0x0
+#define MVF600_PAD_PTA11__DCU0_G1		0x010 0x000 ALT4 0x0
+#define MVF600_PAD_PTA11__MLB_DATA		0x010 0x358 ALT7 0x0
+#define MVF600_PAD_PTA12__GPIO_5		0x014 0x000 ALT0 0x0
+#define MVF600_PAD_PTA12__TRACECK		0x014 0x000 ALT1 0x0
+#define MVF600_PAD_PTA12__EXT_AUDIO_MCLK	0x014 0x2EC ALT2 0x1
+#define MVF600_PAD_PTA12__VIU_DATA13		0x014 0x000 ALT6 0x0
+#define MVF600_PAD_PTA12__I2C0_SCL		0x014 0x33C ALT7 0x0
+#define MVF600_PAD_PTA16__GPIO_6		0x018 0x000 ALT0 0x0
+#define MVF600_PAD_PTA16__TRACED0		0x018 0x000 ALT1 0x0
+#define MVF600_PAD_PTA16__USB0_VBUS_EN		0x018 0x000 ALT2 0x0
+#define MVF600_PAD_PTA16__ADC1_SE0		0x018 0x000 ALT3 0x0
+#define MVF600_PAD_PTA16__LCD29			0x018 0x000 ALT4 0x0
+#define MVF600_PAD_PTA16__SAI2_TX_BCLK		0x018 0x370 ALT5 0x0
+#define MVF600_PAD_PTA16__VIU_DATA14		0x018 0x000 ALT6 0x0
+#define MVF600_PAD_PTA16__I2C0_SDA		0x018 0x340 ALT7 0x0
+#define MVF600_PAD_PTA17__GPIO_7		0x01C 0x000 ALT0 0x0
+#define MVF600_PAD_PTA17__TRACED1		0x01C 0x000 ALT1 0x0
+#define MVF600_PAD_PTA17__USB0_VBUS_OC		0x01C 0x000 ALT2 0x0
+#define MVF600_PAD_PTA17__ADC1_SE1		0x01C 0x000 ALT3 0x0
+#define MVF600_PAD_PTA17__LCD30			0x01C 0x000 ALT4 0x0
+#define MVF600_PAD_PTA17__USB0_SOF_PULSE	0x01C 0x000 ALT5 0x0
+#define MVF600_PAD_PTA17__VIU_DATA15		0x01C 0x000 ALT6 0x0
+#define MVF600_PAD_PTA17__I2C1_SCL		0x01C 0x344 ALT7 0x0
+#define MVF600_PAD_PTA18__GPIO_8		0x020 0x000 ALT0 0x0
+#define MVF600_PAD_PTA18__TRACED2		0x020 0x000 ALT1 0x0
+#define MVF600_PAD_PTA18__ADC0_SE0		0x020 0x000 ALT2 0x0
+#define MVF600_PAD_PTA18__FTM1_QD_PHA		0x020 0x334 ALT3 0x0
+#define MVF600_PAD_PTA18__LCD31			0x020 0x000 ALT4 0x0
+#define MVF600_PAD_PTA18__SAI2_TX_DATA		0x020 0x000 ALT5 0x0
+#define MVF600_PAD_PTA18__VIU_DATA16		0x020 0x000 ALT6 0x0
+#define MVF600_PAD_PTA18__I2C1_SDA		0x020 0x348 ALT7 0x0
+#define MVF600_PAD_PTA19__GPIO_9		0x024 0x000 ALT0 0x0
+#define MVF600_PAD_PTA19__TRACED3		0x024 0x000 ALT1 0x0
+#define MVF600_PAD_PTA19__ADC0_SE1		0x024 0x000 ALT2 0x0
+#define MVF600_PAD_PTA19__FTM1_QD_PHB		0x024 0x338 ALT3 0x0
+#define MVF600_PAD_PTA19__LCD32			0x024 0x000 ALT4 0x0
+#define MVF600_PAD_PTA19__SAI2_TX_SYNC		0x024 0x000 ALT5 0x0
+#define MVF600_PAD_PTA19__VIU_DATA17		0x024 0x000 ALT6 0x0
+#define MVF600_PAD_PTA19__QSPI1_A_QSCK		0x024 0x374 ALT7 0x0
+#define MVF600_PAD_PTA20__GPIO_10		0x028 0x000 ALT0 0x0
+#define MVF600_PAD_PTA20__TRACED4		0x028 0x000 ALT1 0x0
+#define MVF600_PAD_PTA20__LCD33			0x028 0x000 ALT4 0x0
+#define MVF600_PAD_PTA20__UART3_TX		0x028 0x394 ALT6 0x0
+#define MVF600_PAD_PTA20__DCU1_HSYNC		0x028 0x000 ALT7 0x0
+#define MVF600_PAD_PTA21__GPIO_11		0x02C 0x000 ALT0 0x0
+#define MVF600_PAD_PTA21__TRACED5		0x02C 0x000 ALT1 0x0
+#define MVF600_PAD_PTA21__SAI2_RX_BCLK		0x02C 0x364 ALT5 0x0
+#define MVF600_PAD_PTA21__UART3_RX		0x02C 0x390 ALT6 0x0
+#define MVF600_PAD_PTA21__DCU1_VSYNC		0x02C 0x000 ALT7 0x0
+#define MVF600_PAD_PTA22__GPIO_12		0x030 0x000 ALT0 0x0
+#define MVF600_PAD_PTA22__TRACED6		0x030 0x000 ALT1 0x0
+#define MVF600_PAD_PTA22__SAI2_RX_DATA		0x030 0x368 ALT5 0x0
+#define MVF600_PAD_PTA22__I2C2_SCL		0x030 0x34C ALT6 0x0
+#define MVF600_PAD_PTA22__DCU1_TAG		0x030 0x000 ALT7 0x0
+#define MVF600_PAD_PTA23__GPIO_13		0x034 0x000 ALT0 0x0
+#define MVF600_PAD_PTA23__TRACED7		0x034 0x000 ALT1 0x0
+#define MVF600_PAD_PTA23__SAI2_RX_SYNC		0x034 0x36C ALT5 0x0
+#define MVF600_PAD_PTA23__I2C2_SDA		0x034 0x350 ALT6 0x0
+#define MVF600_PAD_PTA23__DCU1_DE		0x034 0x000 ALT7 0x0
+#define MVF600_PAD_PTA24__GPIO_14		0x038 0x000 ALT0 0x0
+#define MVF600_PAD_PTA24__TRACED8		0x038 0x000 ALT1 0x0
+#define MVF600_PAD_PTA24__USB1_VBUS_EN		0x038 0x000 ALT2 0x0
+#define MVF600_PAD_PTA24__ESDHC1_CLK		0x038 0x000 ALT5 0x0
+#define MVF600_PAD_PTA24__DCU1_TCON4		0x038 0x000 ALT6 0x0
+#define MVF600_PAD_PTA24__DDR_TEST_PAD_CTRL	0x038 0x000 ALT7 0x0
+#define MVF600_PAD_PTA25__GPIO_15		0x03C 0x000 ALT0 0x0
+#define MVF600_PAD_PTA25__TRACED9		0x03C 0x000 ALT1 0x0
+#define MVF600_PAD_PTA25__USB1_VBUS_OC		0x03C 0x000 ALT2 0x0
+#define MVF600_PAD_PTA25__ESDHC1_CMD		0x03C 0x000 ALT5 0x0
+#define MVF600_PAD_PTA25__DCU1_TCON5		0x03C 0x000 ALT6 0x0
+#define MVF600_PAD_PTA26__GPIO_16		0x040 0x000 ALT0 0x0
+#define MVF600_PAD_PTA26__TRACED10		0x040 0x000 ALT1 0x0
+#define MVF600_PAD_PTA26__SAI3_TX_BCLK		0x040 0x000 ALT2 0x0
+#define MVF600_PAD_PTA26__ESDHC1_DAT0		0x040 0x000 ALT5 0x0
+#define MVF600_PAD_PTA26__DCU1_TCON6		0x040 0x000 ALT6 0x0
+#define MVF600_PAD_PTA27__GPIO_17		0x044 0x000 ALT0 0x0
+#define MVF600_PAD_PTA27__TRACED11		0x044 0x000 ALT1 0x0
+#define MVF600_PAD_PTA27__SAI3_RX_BCLK		0x044 0x000 ALT2 0x0
+#define MVF600_PAD_PTA27__ESDHC1_DAT1		0x044 0x000 ALT5 0x0
+#define MVF600_PAD_PTA27__DCU1_TCON7		0x044 0x000 ALT6 0x0
+#define MVF600_PAD_PTA28__GPIO_18		0x048 0x000 ALT0 0x0
+#define MVF600_PAD_PTA28__TRACED12		0x048 0x000 ALT1 0x0
+#define MVF600_PAD_PTA28__SAI3_RX_DATA		0x048 0x000 ALT2 0x0
+#define MVF600_PAD_PTA28__ENET1_1588_TMR0	0x048 0x000 ALT3 0x0
+#define MVF600_PAD_PTA28__UART4_TX		0x048 0x000 ALT4 0x0
+#define MVF600_PAD_PTA28__ESDHC1_DATA2		0x048 0x000 ALT5 0x0
+#define MVF600_PAD_PTA28__DCU1_TCON8		0x048 0x000 ALT6 0x0
+#define MVF600_PAD_PTA29__GPIO_19		0x04C 0x000 ALT0 0x0
+#define MVF600_PAD_PTA29__TRACED13		0x04C 0x000 ALT1 0x0
+#define MVF600_PAD_PTA29__SAI3_TX_DATA		0x04C 0x000 ALT2 0x0
+#define MVF600_PAD_PTA29__ENET1_1588_TMR1	0x04C 0x000 ALT3 0x0
+#define MVF600_PAD_PTA29__UART4_RX		0x04C 0x000 ALT4 0x0
+#define MVF600_PAD_PTA29__ESDHC1_DAT3		0x04C 0x000 ALT5 0x0
+#define MVF600_PAD_PTA29__DCU1_TCON9		0x04C 0x000 ALT6 0x0
+#define MVF600_PAD_PTA30__GPIO_20		0x050 0x000 ALT0 0x0
+#define MVF600_PAD_PTA30__TRACED14		0x050 0x000 ALT1 0x0
+#define MVF600_PAD_PTA30__SAI3_RX_SYNC		0x050 0x000 ALT2 0x0
+#define MVF600_PAD_PTA30__ENET1_1588_TMR2	0x050 0x000 ALT3 0x0
+#define MVF600_PAD_PTA30__UART4_RTS		0x050 0x000 ALT4 0x0
+#define MVF600_PAD_PTA30__I2C3_SCL		0x050 0x000 ALT5 0x0
+#define MVF600_PAD_PTA30__UART3_TX		0x050 0x394 ALT7 0x1
+#define MVF600_PAD_PTA31__GPIO_21		0x054 0x000 ALT0 0x0
+#define MVF600_PAD_PTA31__TRACED15		0x054 0x000 ALT1 0x0
+#define MVF600_PAD_PTA31__SAI3_TX_SYNC		0x054 0x000 ALT2 0x0
+#define MVF600_PAD_PTA31__ENET1_1588_TMR3	0x054 0x000 ALT3 0x0
+#define MVF600_PAD_PTA31__UART4_CTS		0x054 0x000 ALT4 0x0
+#define MVF600_PAD_PTA31__I2C3_SDA		0x054 0x000 ALT5 0x0
+#define MVF600_PAD_PTA31__UART3_RX		0x054 0x390 ALT7 0x1
+#define MVF600_PAD_PTB0__GPIO_22		0x058 0x000 ALT0 0x0
+#define MVF600_PAD_PTB0__FTM0_CH0		0x058 0x000 ALT1 0x0
+#define MVF600_PAD_PTB0__ADC0_SE2		0x058 0x000 ALT2 0x0
+#define MVF600_PAD_PTB0__TRACE_CTL		0x058 0x000 ALT3 0x0
+#define MVF600_PAD_PTB0__LCD34			0x058 0x000 ALT4 0x0
+#define MVF600_PAD_PTB0__SAI2_RX_BCLK		0x058 0x364 ALT5 0x1
+#define MVF600_PAD_PTB0__VIU_DATA18		0x058 0x000 ALT6 0x0
+#define MVF600_PAD_PTB0__QSPI1_A_QPCS0		0x058 0x000 ALT7 0x0
+#define MVF600_PAD_PTB1__GPIO_23		0x05C 0x000 ALT0 0x0
+#define MVF600_PAD_PTB1__FTM0_CH1		0x05C 0x000 ALT1 0x0
+#define MVF600_PAD_PTB1__ADC0_SE3		0x05C 0x000 ALT2 0x0
+#define MVF600_PAD_PTB1__SRC_RCON30		0x05C 0x000 ALT3 0x0
+#define MVF600_PAD_PTB1__LCD35			0x05C 0x000 ALT4 0x0
+#define MVF600_PAD_PTB1__SAI2_RX_DATA		0x05C 0x368 ALT5 0x1
+#define MVF600_PAD_PTB1__VIU_DATA19		0x05C 0x000 ALT6 0x0
+#define MVF600_PAD_PTB1__QSPI1_A_DATA3		0x05C 0x000 ALT7 0x0
+#define MVF600_PAD_PTB2__GPIO_24		0x060 0x000 ALT0 0x0
+#define MVF600_PAD_PTB2__FTM0_CH2		0x060 0x000 ALT1 0x0
+#define MVF600_PAD_PTB2__ADC1_SE2		0x060 0x000 ALT2 0x0
+#define MVF600_PAD_PTB2__SRC_RCON31		0x060 0x000 ALT3 0x0
+#define MVF600_PAD_PTB2__LCD36			0x060 0x000 ALT4 0x0
+#define MVF600_PAD_PTB2__SAI2_RX_SYNC		0x060 0x36C ALT5 0x1
+#define MVF600_PAD_PTB2__VIDEO_IN0_DATA20	0x060 0x000 ALT6 0x0
+#define MVF600_PAD_PTB2__QSPI1_A_DATA2		0x060 0x000 ALT7 0x0
+#define MVF600_PAD_PTB3__GPIO_25		0x064 0x000 ALT0 0x0
+#define MVF600_PAD_PTB3__FTM0_CH3		0x064 0x000 ALT1 0x0
+#define MVF600_PAD_PTB3__ADC1_SE3		0x064 0x000 ALT2 0x0
+#define MVF600_PAD_PTB3__PDB_EXTRIG		0x064 0x000 ALT3 0x0
+#define MVF600_PAD_PTB3__LCD37			0x064 0x000 ALT4 0x0
+#define MVF600_PAD_PTB3__VIU_DATA21		0x064 0x000 ALT6 0x0
+#define MVF600_PAD_PTB3__QSPI1_A_DATA1		0x064 0x000 ALT7 0x0
+#define MVF600_PAD_PTB4__GPIO_26		0x068 0x000 ALT0 0x0
+#define MVF600_PAD_PTB4__FTM0_CH4		0x068 0x000 ALT1 0x0
+#define MVF600_PAD_PTB4__UART1_TX		0x068 0x380 ALT2 0x0
+#define MVF600_PAD_PTB4__ADC0_SE4		0x068 0x000 ALT3 0x0
+#define MVF600_PAD_PTB4__LCD38			0x068 0x000 ALT4 0x0
+#define MVF600_PAD_PTB4__VIU_FID		0x068 0x3A8 ALT5 0x0
+#define MVF600_PAD_PTB4__VIU_DATA22		0x068 0x000 ALT6 0x0
+#define MVF600_PAD_PTB4__QSPI1_A_DATA0		0x068 0x000 ALT7 0x0
+#define MVF600_PAD_PTB5__GPIO_27		0x06C 0x000 ALT0 0x0
+#define MVF600_PAD_PTB5__FTM0_CH5		0x06C 0x000 ALT1 0x0
+#define MVF600_PAD_PTB5__UART1_RX		0x06C 0x37C ALT2 0x0
+#define MVF600_PAD_PTB5__ADC1_SE4		0x06C 0x000 ALT3 0x0
+#define MVF600_PAD_PTB5__LCD39			0x06C 0x000 ALT4 0x0
+#define MVF600_PAD_PTB5__VIU_DE			0x06C 0x3A4 ALT5 0x0
+#define MVF600_PAD_PTB5__QSPI1_A_DQS		0x06C 0x000 ALT7 0x0
+#define MVF600_PAD_PTB6__GPIO_28		0x070 0x000 ALT0 0x0
+#define MVF600_PAD_PTB6__FTM0_CH6		0x070 0x000 ALT1 0x0
+#define MVF600_PAD_PTB6__UART1_RTS		0x070 0x000 ALT2 0x0
+#define MVF600_PAD_PTB6__QSPI0_QPCS1_A		0x070 0x000 ALT3 0x0
+#define MVF600_PAD_PTB6__LCD_LCD40		0x070 0x000 ALT4 0x0
+#define MVF600_PAD_PTB6__FB_CLKOUT		0x070 0x000 ALT5 0x0
+#define MVF600_PAD_PTB6__VIU_HSYNC		0x070 0x000 ALT6 0x0
+#define MVF600_PAD_PTB6__UART2_TX		0x070 0x38C ALT7 0x0
+#define MVF600_PAD_PTB7__GPIO_29		0x074 0x000 ALT0 0x0
+#define MVF600_PAD_PTB7__FTM0_CH7		0x074 0x000 ALT1 0x0
+#define MVF600_PAD_PTB7__UART1_CTS		0x074 0x378 ALT2 0x0
+#define MVF600_PAD_PTB7__QSPI0_B_QPCS1		0x074 0x000 ALT3 0x0
+#define MVF600_PAD_PTB7__LCD41			0x074 0x000 ALT4 0x0
+#define MVF600_PAD_PTB7__VIU_VSYNC		0x074 0x000 ALT6 0x0
+#define MVF600_PAD_PTB7__UART2_RX		0x074 0x388 ALT7 0x0
+#define MVF600_PAD_PTB8__GPIO_30		0x078 0x000 ALT0 0x0
+#define MVF600_PAD_PTB8__FTM1_CH0		0x078 0x32C ALT1 0x0
+#define MVF600_PAD_PTB8__FTM1_QD_PHA		0x078 0x334 ALT3 0x1
+#define MVF600_PAD_PTB8__VIU_DE			0x078 0x3A4 ALT5 0x1
+#define MVF600_PAD_PTB8__DCU1_R6		0x078 0x000 ALT7 0x0
+#define MVF600_PAD_PTB9__GPIO_31		0x07C 0x000 ALT0 0x0
+#define MVF600_PAD_PTB9__FTM1_CH1		0x07C 0x330 ALT1 0x0
+#define MVF600_PAD_PTB9__FTM1_QD_PHB		0x07C 0x338 ALT3 0x1
+#define MVF600_PAD_PTB9__DCU1_R7		0x07C 0x000 ALT7 0x0
+#define MVF600_PAD_PTB10__GPIO_32		0x080 0x000 ALT0 0x0
+#define MVF600_PAD_PTB10__UART0_TX		0x080 0x000 ALT1 0x0
+#define MVF600_PAD_PTB10__DCU0_TCON4		0x080 0x000 ALT4 0x0
+#define MVF600_PAD_PTB10__VIU_DE		0x080 0x3A4 ALT5 0x2
+#define MVF600_PAD_PTB10__CKO1			0x080 0x000 ALT6 0x0
+#define MVF600_PAD_PTB10__ENET_TS_CLKIN		0x080 0x2F4 ALT7 0x1
+#define MVF600_PAD_PTB11__GPIO_33		0x084 0x000 ALT0 0x0
+#define MVF600_PAD_PTB11__UART0_RX		0x084 0x000 ALT1 0x0
+#define MVF600_PAD_PTB11__DCU0_TCON5		0x084 0x000 ALT4 0x0
+#define MVF600_PAD_PTB11__SNVS_ALARM_OUT_B	0x084 0x000 ALT5 0x0
+#define MVF600_PAD_PTB11__CKO2			0x084 0x000 ALT6 0x0
+#define MVF600_PAD_PTB11_ENET0_1588_TMR0	0x084 0x304 ALT7 0x0
+#define MVF600_PAD_PTB12__GPIO_34		0x088 0x000 ALT0 0x0
+#define MVF600_PAD_PTB12__UART0_RTS		0x088 0x000 ALT1 0x0
+#define MVF600_PAD_PTB12__DSPI0_CS5		0x088 0x000 ALT3 0x0
+#define MVF600_PAD_PTB12__DCU0_TCON6		0x088 0x000 ALT4 0x0
+#define MVF600_PAD_PTB12__FB_AD1		0x088 0x000 ALT5 0x0
+#define MVF600_PAD_PTB12__NMI			0x088 0x000 ALT6 0x0
+#define MVF600_PAD_PTB12__ENET0_1588_TMR1	0x088 0x308 ALT7 0x0
+#define MVF600_PAD_PTB13__GPIO_35		0x08C 0x000 ALT0 0x0
+#define MVF600_PAD_PTB13__UART0_CTS		0x08C 0x000 ALT1 0x0
+#define MVF600_PAD_PTB13__DSPI0_CS4		0x08C 0x000 ALT3 0x0
+#define MVF600_PAD_PTB13__DCU0_TCON7		0x08C 0x000 ALT4 0x0
+#define MVF600_PAD_PTB13__FB_AD0		0x08C 0x000 ALT5 0x0
+#define MVF600_PAD_PTB13__TRACE_CTL		0x08C 0x000 ALT6 0x0
+#define MVF600_PAD_PTB14__GPIO_36		0x090 0x000 ALT0 0x0
+#define MVF600_PAD_PTB14__CAN0_RX		0x090 0x000 ALT1 0x0
+#define MVF600_PAD_PTB14__I2C0_SCL		0x090 0x33C ALT2 0x1
+#define MVF600_PAD_PTB14__DCU0_TCON8		0x090 0x000 ALT4 0x0
+#define MVF600_PAD_PTB14__DCU1_PCLK		0x090 0x000 ALT7 0x0
+#define MVF600_PAD_PTB15__GPIO_37		0x094 0x000 ALT0 0x0
+#define MVF600_PAD_PTB15__CAN0_TX		0x094 0x000 ALT1 0x0
+#define MVF600_PAD_PTB15__I2C0_SDA		0x094 0x340 ALT2 0x1
+#define MVF600_PAD_PTB15__DCU0_TCON9		0x094 0x000 ALT4 0x0
+#define MVF600_PAD_PTB15__VIU_PIX_CLK		0x094 0x3AC ALT7 0x0
+#define MVF600_PAD_PTB16__GPIO_38		0x098 0x000 ALT0 0x0
+#define MVF600_PAD_PTB16__CAN1_RX		0x098 0x000 ALT1 0x0
+#define MVF600_PAD_PTB16__I2C1_SCL		0x098 0x344 ALT2 0x1
+#define MVF600_PAD_PTB16__DCU0_TCON10		0x098 0x000 ALT4 0x0
+#define MVF600_PAD_PTB17__GPIO_39		0x09C 0x000 ALT0 0x0
+#define MVF600_PAD_PTB17__CAN1_TX		0x09C 0x000 ALT1 0x0
+#define MVF600_PAD_PTB17__I2C1_SDA		0x09C 0x348 ALT2 0x1
+#define MVF600_PAD_PTB17__DCU0_TCON11		0x09C 0x000 ALT4 0x0
+#define MVF600_PAD_PTB18__GPIO_40		0x0A0 0x000 ALT0 0x0
+#define MVF600_PAD_PTB18__DSPI0_CS1		0x0A0 0x000 ALT1 0x0
+#define MVF600_PAD_PTB18__EXT_AUDIO_MCLK	0x0A0 0x2EC ALT2 0x2
+#define MVF600_PAD_PTB18__VIU_DATA9		0x0A0 0x000 ALT6 0x0
+#define MVF600_PAD_PTB19__GPIO_41		0x0A4 0x000 ALT0 0x0
+#define MVF600_PAD_PTB19__DSPI0_CS0		0x0A4 0x000 ALT1 0x0
+#define MVF600_PAD_PTB19__VIU_DATA10		0x0A4 0x000 ALT6 0x0
+#define MVF600_PAD_PTB20__GPIO_42		0x0A8 0x000 ALT0 0x0
+#define MVF600_PAD_PTB20__DSPI0_SIN		0x0A8 0x000 ALT1 0x0
+#define MVF600_PAD_PTB20__LCD42			0x0A8 0x000 ALT4 0x0
+#define MVF600_PAD_PTB20__VIU_DATA11		0x0A8 0x000 ALT6 0x0
+#define MVF600_PAD_PTB21__GPIO_43		0x0AC 0x000 ALT0 0x0
+#define MVF600_PAD_PTB21__DSPI0_SOUT		0x0AC 0x000 ALT1 0x0
+#define MVF600_PAD_PTB21__LCD43			0x0AC 0x000 ALT4 0x0
+#define MVF600_PAD_PTB21__VIU_DATA12		0x0AC 0x000 ALT6 0x0
+#define MVF600_PAD_PTB21__DCU1_PCLK		0x0AC 0x000 ALT7 0x0
+#define MVF600_PAD_PTB22__GPIO_44		0x0B0 0x000 ALT0 0x0
+#define MVF600_PAD_PTB22__DSPI0_SCK		0x0B0 0x000 ALT1 0x0
+#define MVF600_PAD_PTB22__VLCD			0x0B0 0x000 ALT4 0x0
+#define MVF600_PAD_PTB22__VIU_FID		0x0B0 0x3A8 ALT5 0x1
+#define MVF600_PAD_PTC0__GPIO_45		0x0B4 0x000 ALT0 0x0
+#define MVF600_PAD_PTC0__ENET_RMII0_MDC		0x0B4 0x000 ALT1 0x0
+#define MVF600_PAD_PTC0__FTM1_CH0		0x0B4 0x32C ALT2 0x1
+#define MVF600_PAD_PTC0__DSPI0_CS3		0x0B4 0x000 ALT3 0x0
+#define MVF600_PAD_PTC0__ESAI_SCKT		0x0B4 0x310 ALT4 0x0
+#define MVF600_PAD_PTC0__ESDHC0_CLK		0x0B4 0x000 ALT5 0x0
+#define MVF600_PAD_PTC0__VIU_DATA0		0x0B4 0x000 ALT6 0x0
+#define MVF600_PAD_PTC0__SRC_RCON18		0x0B4 0x398 ALT7 0x0
+#define MVF600_PAD_PTC1__GPIO_46		0x0B8 0x000 ALT0 0x0
+#define MVF600_PAD_PTC1__ENET_RMII0_MDIO	0x0B8 0x000 ALT1 0x0
+#define MVF600_PAD_PTC1__FTM1_CH1		0x0B8 0x330 ALT2 0x1
+#define MVF600_PAD_PTC1__DSPI0_CS2		0x0B8 0x000 ALT3 0x0
+#define MVF600_PAD_PTC1__ESAI_FST		0x0B8 0x30C ALT4 0x0
+#define MVF600_PAD_PTC1__ESDHC0_CMD		0x0B8 0x000 ALT5 0x0
+#define MVF600_PAD_PTC1__VIU_DATA1		0x0B8 0x000 ALT6 0x0
+#define MVF600_PAD_PTC1__SRC_RCON19		0x0B8 0x39C ALT7 0x0
+#define MVF600_PAD_PTC2__GPIO_47		0x0BC 0x000 ALT0 0x0
+#define MVF600_PAD_PTC2__ENET_RMII0_CRS		0x0BC 0x000 ALT1 0x0
+#define MVF600_PAD_PTC2__UART1_TX		0x0BC 0x380 ALT2 0x1
+#define MVF600_PAD_PTC2__ESAI_SDO0		0x0BC 0x314 ALT4 0x0
+#define MVF600_PAD_PTC2__ESDHC0_DAT0		0x0BC 0x000 ALT5 0x0
+#define MVF600_PAD_PTC2__VIU_DATA2		0x0BC 0x000 ALT6 0x0
+#define MVF600_PAD_PTC2__SRC_RCON20		0x0BC 0x3A0 ALT7 0x0
+#define MVF600_PAD_PTC3__GPIO_48		0x0C0 0x000 ALT0 0x0
+#define MVF600_PAD_PTC3__ENET_RMII0_RXD1	0x0C0 0x000 ALT1 0x0
+#define MVF600_PAD_PTC3__UART1_RX		0x0C0 0x37C ALT2 0x1
+#define MVF600_PAD_PTC3__ESAI_SDO1		0x0C0 0x318 ALT4 0x0
+#define MVF600_PAD_PTC3__ESDHC0_DAT1		0x0C0 0x000 ALT5 0x0
+#define MVF600_PAD_PTC3__VIU_DATA3		0x0C0 0x000 ALT6 0x0
+#define MVF600_PAD_PTC3__DCU0_R0		0x0C0 0x000 ALT7 0x0
+#define MVF600_PAD_PTC4__GPIO_49		0x0C4 0x000 ALT0 0x0
+#define MVF600_PAD_PTC4__ENET_RMII0_RXD0	0x0C4 0x000 ALT1 0x0
+#define MVF600_PAD_PTC4__UART1_RTS		0x0C4 0x000 ALT2 0x0
+#define MVF600_PAD_PTC4__DSPI1_CS1		0x0C4 0x000 ALT3 0x0
+#define MVF600_PAD_PTC4__ESAI_SDO2		0x0C4 0x31C ALT4 0x0
+#define MVF600_PAD_PTC4__ESDHC0_DAT2		0x0C4 0x000 ALT5 0x0
+#define MVF600_PAD_PTC4__VIU_DATA4		0x0C4 0x000 ALT6 0x0
+#define MVF600_PAD_PTC4__DCU0_R1		0x0C4 0x000 ALT7 0x0
+#define MVF600_PAD_PTC5__GPIO_50		0x0C8 0x000 ALT0 0x0
+#define MVF600_PAD_PTC5__ENET_RMII0_RXER	0x0C8 0x000 ALT1 0x0
+#define MVF600_PAD_PTC5__UART1_CTS		0x0C8 0x378 ALT2 0x1
+#define MVF600_PAD_PTC5__DSPI1_CS0		0x0C8 0x300 ALT3 0x0
+#define MVF600_PAD_PTC5__ESAI_SDO3		0x0C8 0x320 ALT4 0x0
+#define MVF600_PAD_PTC5__ESDHC0_DAT3		0x0C8 0x000 ALT5 0x0
+#define MVF600_PAD_PTC5__VIU_DATA5		0x0C8 0x000 ALT6 0x0
+#define MVF600_PAD_PTC5__DCU0_G0		0x0C8 0x000 ALT7 0x0
+#define MVF600_PAD_PTC6__GPIO_51		0x0CC 0x000 ALT0 0x0
+#define MVF600_PAD_PTC6__ENET_RMII0_TXD1	0x0CC 0x000 ALT1 0x0
+#define MVF600_PAD_PTC6__DSPI1_SIN		0x0CC 0x2FC ALT3 0x0
+#define MVF600_PAD_PTC6__ESAI_SDI0		0x0CC 0x328 ALT4 0x0
+#define MVF600_PAD_PTC6__ESDHC0_WP		0x0CC 0x000 ALT5 0x0
+#define MVF600_PAD_PTC6__VIU_DATA6		0x0CC 0x000 ALT6 0x0
+#define MVF600_PAD_PTC6__DCU0_G1		0x0CC 0x000 ALT7 0x0
+#define MVF600_PAD_PTC7__GPIO_52		0x0D0 0x000 ALT0 0x0
+#define MVF600_PAD_PTC7__ENET_RMII0_TXD0	0x0D0 0x000 ALT1 0x0
+#define MVF600_PAD_PTC7__DSPI1_SOUT		0x0D0 0x000 ALT3 0x0
+#define MVF600_PAD_PTC7__ESAI_SDI1		0x0D0 0x324 ALT4 0x0
+#define MVF600_PAD_PTC7__VIU_DATA7		0x0D0 0x000 ALT6 0x0
+#define MVF600_PAD_PTC7__DCU0_B0		0x0D0 0x000 ALT7 0x0
+#define MVF600_PAD_PTC8__GPIO_53		0x0D4 0x000 ALT0 0x0
+#define MVF600_PAD_PTC8__ENET_RMII0_TXEN	0x0D4 0x000 ALT1 0x0
+#define MVF600_PAD_PTC8__DSPI1_SCK		0x0D4 0x2F8 ALT3 0x0
+#define MVF600_PAD_PTC8__VIU_DATA8		0x0D4 0x000 ALT6 0x0
+#define MVF600_PAD_PTC8__DCU0_B1		0x0D4 0x000 ALT7 0x0
+#define MVF600_PAD_PTC9__GPIO_54		0x0D8 0x000 ALT0 0x0
+#define MVF600_PAD_PTC9__ENET_RMII1_MDC		0x0D8 0x000 ALT1 0x0
+#define MVF600_PAD_PTC9__ESAI_SCKT		0x0D8 0x310 ALT3 0x1
+#define MVF600_PAD_PTC9__MLB_CLK		0x0D8 0x354 ALT6 0x1
+#define MVF600_PAD_PTC9__DEBUG_OUT0		0x0D8 0x000 ALT7 0x0
+#define MVF600_PAD_PTC10__GPIO_55		0x0DC 0x000 ALT0 0x0
+#define MVF600_PAD_PTC10__ENET_RMII1_MDIO	0x0DC 0x000 ALT1 0x0
+#define MVF600_PAD_PTC10__ESAI_FST		0x0DC 0x30C ALT3 0x1
+#define MVF600_PAD_PTC10__MLB_SIGNAL		0x0DC 0x35C ALT6 0x1
+#define MVF600_PAD_PTC10__DEBUG_OUT1		0x0DC 0x000 ALT7 0x0
+#define MVF600_PAD_PTC11__GPIO_56		0x0E0 0x000 ALT0 0x0
+#define MVF600_PAD_PTC11__ENET_RMII1_CRS	0x0E0 0x000 ALT1 0x0
+#define MVF600_PAD_PTC11__ESAI_SDO0		0x0E0 0x314 ALT3 0x1
+#define MVF600_PAD_PTC11__MLB_DATA		0x0E0 0x358 ALT6 0x1
+#define MVF600_PAD_PTC11__DEBUG_OUT		0x0E0 0x000 ALT7 0x0
+#define MVF600_PAD_PTC12__GPIO_57		0x0E4 0x000 ALT0 0x0
+#define MVF600_PAD_PTC12__ENET_RMII_RXD1	0x0E4 0x000 ALT1 0x0
+#define MVF600_PAD_PTC12__ESAI_SDO1		0x0E4 0x318 ALT3 0x1
+#define MVF600_PAD_PTC12__SAI2_TX_BCLK		0x0E4 0x370 ALT5 0x1
+#define MVF600_PAD_PTC12__DEBUG_OUT3		0x0E4 0x000 ALT7 0x0
+#define MVF600_PAD_PTC13__GPIO_58		0x0E8 0x000 ALT0 0x0
+#define MVF600_PAD_PTC13__ENET_RMII1_RXD0	0x0E8 0x000 ALT1 0x0
+#define MVF600_PAD_PTC13__ESAI_SDO2		0x0E8 0x31C ALT3 0x1
+#define MVF600_PAD_PTC13__SAI2_RX_BCLK		0x0E8 0x364 ALT5 0x2
+#define MVF600_PAD_PTC13__DEBUG_OUT4		0x0E8 0x000 ALT7 0x0
+#define MVF600_PAD_PTC14__GPIO_59		0x0EC 0x000 ALT0 0x0
+#define MVF600_PAD_PTC14__ENET_RMII1_RXER	0x0EC 0x000 ALT1 0x0
+#define MVF600_PAD_PTC14__ESAI_SDO3		0x0EC 0x320 ALT3 0x1
+#define MVF600_PAD_PTC14__UART5_TX		0x0EC 0x000 ALT4 0x0
+#define MVF600_PAD_PTC14__SAI2_RX_DATA		0x0EC 0x368 ALT5 0x2
+#define MVF600_PAD_PTC14__ADC0_SE6		0x0EC 0x000 ALT6 0x0
+#define MVF600_PAD_PTC14__DEBUG_OUT5		0x0EC 0x000 ALT7 0x0
+#define MVF600_PAD_PTC15__GPIO_60		0x0F0 0x000 ALT0 0x0
+#define MVF600_PAD_PTC15__ENET_RMII1_TXD1	0x0F0 0x000 ALT1 0x0
+#define MVF600_PAD_PTC15__ESAI_SDI0		0x0F0 0x328 ALT3 0x1
+#define MVF600_PAD_PTC15__UART5_RX		0x0F0 0x000 ALT4 0x0
+#define MVF600_PAD_PTC15__SAI2_TX_DATA		0x0F0 0x000 ALT5 0x0
+#define MVF600_PAD_PTC15__ADC0_SE7		0x0F0 0x000 ALT6 0x0
+#define MVF600_PAD_PTC15__DEBUG_OUT6		0x0F0 0x000 ALT7 0x0
+#define MVF600_PAD_PTC16__GPIO_61		0x0F4 0x000 ALT0 0x0
+#define MVF600_PAD_PTC16__ENET_RMII1_TXD0	0x0F4 0x000 ALT1 0x0
+#define MVF600_PAD_PTC16__ESAI_SDI1		0x0F4 0x324 ALT3 0x1
+#define MVF600_PAD_PTC16__UART5_RTS		0x0F4 0x000 ALT4 0x0
+#define MVF600_PAD_PTC16__SAI2_RX_SYNC		0x0F4 0x36C ALT5 0x2
+#define MVF600_PAD_PTC16__ADC1_SE6		0x0F4 0x000 ALT6 0x0
+#define MVF600_PAD_PTC16__DEBUG_OUT7		0x0F4 0x000 ALT7 0x0
+#define MVF600_PAD_PTC17__GPIO_62		0x0F8 0x000 ALT0 0x0
+#define MVF600_PAD_PTC17__ENET_RMII1_TXEN	0x0F8 0x000 ALT1 0x0
+#define MVF600_PAD_PTC17__ADC1_SE7		0x0F8 0x000 ALT3 0x0
+#define MVF600_PAD_PTC17__UART5_CTS		0x0F8 0x000 ALT4 0x0
+#define MVF600_PAD_PTC17__SAI2_TX_SYNC		0x0F8 0x374 ALT5 0x1
+#define MVF600_PAD_PTC17__USB1_SOF_PULSE	0x0F8 0x000 ALT6 0x0
+#define MVF600_PAD_PTC17__DEBUG_OUT8		0x0F8 0x000 ALT7 0x0
+#define MVF600_PAD_PTD31__GPIO_63		0x0FC 0x000 ALT0 0x0
+#define MVF600_PAD_PTD31__FB_AD31		0x0FC 0x000 ALT1 0x0
+#define MVF600_PAD_PTD31__NF_IO15		0x0FC 0x000 ALT2 0x0
+#define MVF600_PAD_PTD31__FTM3_CH0		0x0FC 0x000 ALT4 0x0
+#define MVF600_PAD_PTD31__DSPI2_CS1		0x0FC 0x000 ALT5 0x0
+#define MVF600_PAD_PTD31__DEBUG_OUT9		0x0FC 0x000 ALT7 0x0
+#define MVF600_PAD_PTD30__GPIO_64		0x100 0x000 ALT0 0x0
+#define MVF600_PAD_PTD30__FB_AD30		0x100 0x000 ALT1 0x0
+#define MVF600_PAD_PTD30__NF_IO14		0x100 0x000 ALT2 0x0
+#define MVF600_PAD_PTD30__FTM3_CH1		0x100 0x000 ALT4 0x0
+#define MVF600_PAD_PTD30__DSPI2_CS0		0x100 0x000 ALT5 0x0
+#define MVF600_PAD_PTD30__DEBUG_OUT10		0x100 0x000 ALT7 0x0
+#define MVF600_PAD_PTD29__GPIO_65		0x104 0x000 ALT0 0x0
+#define MVF600_PAD_PTD29__FB_AD29		0x104 0x000 ALT1 0x0
+#define MVF600_PAD_PTD29__NF_IO13		0x104 0x000 ALT2 0x0
+#define MVF600_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
+#define MVF600_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
+#define MVF600_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
+#define MVF600_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define MVF600_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
+#define MVF600_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
+#define MVF600_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1
+#define MVF600_PAD_PTD28__FTM3_CH3		0x108 0x000 ALT4 0x0
+#define MVF600_PAD_PTD28__DSPI2_SOUT		0x108 0x000 ALT5 0x0
+#define MVF600_PAD_PTD28__DEBUG_OUT12		0x108 0x000 ALT7 0x0
+#define MVF600_PAD_PTD27__GPIO_67		0x10C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD27__FB_AD27		0x10C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD27__NF_IO11		0x10C 0x000 ALT2 0x0
+#define MVF600_PAD_PTD27__I2C2_SDA		0x10C 0x350 ALT3 0x1
+#define MVF600_PAD_PTD27__FTM3_CH4		0x10C 0x000 ALT4 0x0
+#define MVF600_PAD_PTD27__DSPI2_SCK		0x10C 0x000 ALT5 0x0
+#define MVF600_PAD_PTD27__DEBUG_OUT13		0x10C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD26__GPIO_68		0x110 0x000 ALT0 0x0
+#define MVF600_PAD_PTD26__FB_AD26		0x110 0x000 ALT1 0x0
+#define MVF600_PAD_PTD26__NF_IO10		0x110 0x000 ALT2 0x0
+#define MVF600_PAD_PTD26__FTM3_CH5		0x110 0x000 ALT4 0x0
+#define MVF600_PAD_PTD26__ESDHC1_WP		0x110 0x000 ALT5 0x0
+#define MVF600_PAD_PTD26__DEBUG_OUT14		0x110 0x000 ALT7 0x0
+#define MVF600_PAD_PTD25__GPIO_69		0x114 0x000 ALT0 0x0
+#define MVF600_PAD_PTD25__FB_AD25		0x114 0x000 ALT1 0x0
+#define MVF600_PAD_PTD25__NF_IO9		0x114 0x000 ALT2 0x0
+#define MVF600_PAD_PTD25__FTM3_CH6		0x114 0x000 ALT4 0x0
+#define MVF600_PAD_PTD25__DEBUG_OUT15		0x114 0x000 ALT7 0x0
+#define MVF600_PAD_PTD24__GPIO_70		0x118 0x000 ALT0 0x0
+#define MVF600_PAD_PTD24__FB_AD24		0x118 0x000 ALT1 0x0
+#define MVF600_PAD_PTD24__NF_IO8		0x118 0x000 ALT2 0x0
+#define MVF600_PAD_PTD24__FTM3_CH7		0x118 0x000 ALT4 0x0
+#define MVF600_PAD_PTD24__DEBUG_OUT16		0x118 0x000 ALT7 0x0
+#define MVF600_PAD_PTD23__GPIO_71		0x11C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD23__FB_AD23		0x11C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD23__NF_IO7		0x11C 0x000 ALT2 0x0
+#define MVF600_PAD_PTD23__FTM2_CH0		0x11C 0x000 ALT3 0x0
+#define MVF600_PAD_PTD23__ENET0_1588_TMR0	0x11C 0x304 ALT4 0x1
+#define MVF600_PAD_PTD23__ESDHC0_DAT4		0x11C 0x000 ALT5 0x0
+#define MVF600_PAD_PTD23__UART2_TX		0x11C 0x38C ALT6 0x1
+#define MVF600_PAD_PTD23__DCU1_R3		0x11C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD22__GPIO_72		0x120 0x000 ALT0 0x0
+#define MVF600_PAD_PTD22__FB_AD22		0x120 0x000 ALT1 0x0
+#define MVF600_PAD_PTD22__NF_IO6		0x120 0x000 ALT2 0x0
+#define MVF600_PAD_PTD22__FTM2_CH1		0x120 0x000 ALT3 0x0
+#define MVF600_PAD_PTD22__ENET0_1588_TMR1	0x120 0x308 ALT4 0x1
+#define MVF600_PAD_PTD22__ESDHC0_DAT5		0x120 0x000 ALT5 0x0
+#define MVF600_PAD_PTD22__UART2_RX		0x120 0x388 ALT6 0x1
+#define MVF600_PAD_PTD22__DCU1_R4		0x120 0x000 ALT7 0x0
+#define MVF600_PAD_PTD21__GPIO_73		0x124 0x000 ALT0 0x0
+#define MVF600_PAD_PTD21__FB_AD21		0x124 0x000 ALT1 0x0
+#define MVF600_PAD_PTD21__NF_IO5		0x124 0x000 ALT2 0x0
+#define MVF600_PAD_PTD21__ENET0_1588_TMR2	0x124 0x000 ALT4 0x0
+#define MVF600_PAD_PTD21__ESDHC0_DAT6		0x124 0x000 ALT5 0x0
+#define MVF600_PAD_PTD21__UART2_RTS		0x124 0x000 ALT6 0x0
+#define MVF600_PAD_PTD21__DCU1_R5		0x124 0x000 ALT7 0x0
+#define MVF600_PAD_PTD20__GPIO_74		0x128 0x000 ALT0 0x0
+#define MVF600_PAD_PTD20__FB_AD20		0x128 0x000 ALT1 0x0
+#define MVF600_PAD_PTD20__NF_IO4		0x128 0x000 ALT2 0x0
+#define MVF600_PAD_PTD20__ENET0_1588_TMR3	0x128 0x000 ALT4 0x0
+#define MVF600_PAD_PTD20__ESDHC0_DAT7		0x128 0x000 ALT5 0x0
+#define MVF600_PAD_PTD20__UART2_CTS		0x128 0x384 ALT6 0x0
+#define MVF600_PAD_PTD20__DCU1_R0		0x128 0x000 ALT7 0x0
+#define MVF600_PAD_PTD19__GPIO_75		0x12C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD19__FB_AD19		0x12C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD19__NF_IO3		0x12C 0x000 ALT2 0x0
+#define MVF600_PAD_PTD19__ESAI_SCKR		0x12C 0x000 ALT3 0x0
+#define MVF600_PAD_PTD19__I2C0_SCL		0x12C 0x33C ALT4 0x2
+#define MVF600_PAD_PTD19__FTM2_QD_PHA		0x12C 0x000 ALT5 0x0
+#define MVF600_PAD_PTD19__DCU1_R1		0x12C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD18__GPIO_76		0x130 0x000 ALT0 0x0
+#define MVF600_PAD_PTD18__FB_AD18		0x130 0x000 ALT1 0x0
+#define MVF600_PAD_PTD18__NF_IO2		0x130 0x000 ALT2 0x0
+#define MVF600_PAD_PTD18__ESAI_FSR		0x130 0x000 ALT3 0x0
+#define MVF600_PAD_PTD18__I2C0_SDA		0x130 0x340 ALT4 0x2
+#define MVF600_PAD_PTD18__FTM2_QD_PHB		0x130 0x000 ALT5 0x0
+#define MVF600_PAD_PTD18__DCU1_G0		0x130 0x000 ALT7 0x0
+#define MVF600_PAD_PTD17__GPIO_77		0x134 0x000 ALT0 0x0
+#define MVF600_PAD_PTD17__FB_AD17		0x134 0x000 ALT1 0x0
+#define MVF600_PAD_PTD17__NF_IO1		0x134 0x000 ALT2 0x0
+#define MVF600_PAD_PTD17__ESAI_HCKR		0x134 0x000 ALT3 0x0
+#define MVF600_PAD_PTD17__I2C1_SCL		0x134 0x344 ALT4 0x2
+#define MVF600_PAD_PTD17__DCU1_G1		0x134 0x000 ALT7 0x0
+#define MVF600_PAD_PTD16__GPIO_78		0x138 0x000 ALT0 0x0
+#define MVF600_PAD_PTD16__FB_AD16		0x138 0x000 ALT1 0x0
+#define MVF600_PAD_PTD16__NF_IO0		0x138 0x000 ALT2 0x0
+#define MVF600_PAD_PTD16__ESAI_HCKT		0x138 0x000 ALT3 0x0
+#define MVF600_PAD_PTD16__I2C1_SDA		0x138 0x348 ALT4 0x2
+#define MVF600_PAD_PTD16__DCU1_G2		0x138 0x000 ALT7 0x0
+#define MVF600_PAD_PTD0__GPIO_79		0x13C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD0__QSPI0_A_QSCK		0x13C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD0__UART2_TX		0x13C 0x38C ALT2 0x2
+#define MVF600_PAD_PTD0__FB_AD15		0x13C 0x000 ALT4 0x0
+#define MVF600_PAD_PTD0__SPDIF_EXTCLK		0x13C 0x000 ALT5 0x0
+#define MVF600_PAD_PTD0__DEBUG_OUT17		0x13C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD1__GPIO_80		0x140 0x000 ALT0 0x0
+#define MVF600_PAD_PTD1__QSPI0_A_CS0		0x140 0x000 ALT1 0x0
+#define MVF600_PAD_PTD1__UART2_RX		0x140 0x388 ALT2 0x2
+#define MVF600_PAD_PTD1__FB_AD14		0x140 0x000 ALT4 0x0
+#define MVF600_PAD_PTD1__SPDIF_IN1		0x140 0x000 ALT5 0x0
+#define MVF600_PAD_PTD1__DEBUG_OUT18		0x140 0x000 ALT7 0x0
+#define MVF600_PAD_PTD2__GPIO_81		0x144 0x000 ALT0 0x0
+#define MVF600_PAD_PTD2__QSPI0_A_DATA3		0x144 0x000 ALT1 0x0
+#define MVF600_PAD_PTD2__UART2_RTS		0x144 0x000 ALT2 0x0
+#define MVF600_PAD_PTD2__DSPI1_CS3		0x144 0x000 ALT3 0x0
+#define MVF600_PAD_PTD2__FB_AD13		0x144 0x000 ALT4 0x0
+#define MVF600_PAD_PTD2__SPDIF_OUT1		0x144 0x000 ALT5 0x0
+#define MVF600_PAD_PTD2__DEBUG_OUT19		0x144 0x000 ALT7 0x0
+#define MVF600_PAD_PTD3__GPIO_82		0x148 0x000 ALT0 0x0
+#define MVF600_PAD_PTD3__QSPI0_A_DATA2		0x148 0x000 ALT1 0x0
+#define MVF600_PAD_PTD3__UART2_CTS		0x148 0x384 ALT2 0x1
+#define MVF600_PAD_PTD3__DSPI1_CS2		0x148 0x000 ALT3 0x0
+#define MVF600_PAD_PTD3__FB_AD12		0x148 0x000 ALT4 0x0
+#define MVF600_PAD_PTD3__SPDIF_PLOCK		0x148 0x000 ALT5 0x0
+#define MVF600_PAD_PTD3__DEBUG_OUT20		0x148 0x000 ALT7 0x0
+#define MVF600_PAD_PTD4__GPIO_83		0x14C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD4__QSPI0_A_DATA1		0x14C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD4__DSPI1_CS1		0x14C 0x000 ALT3 0x0
+#define MVF600_PAD_PTD4__FB_AD11		0x14C 0x000 ALT4 0x0
+#define MVF600_PAD_PTD4__SPDIF_SRCLK		0x14C 0x000 ALT5 0x0
+#define MVF600_PAD_PTD4__DEBUG_OUT21		0x14C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD5__GPIO_84		0x150 0x000 ALT0 0x0
+#define MVF600_PAD_PTD5__QSPI0_A_DATA0		0x150 0x000 ALT1 0x0
+#define MVF600_PAD_PTD5__DSPI1_CS0		0x150 0x300 ALT3 0x1
+#define MVF600_PAD_PTD5__FB_AD10		0x150 0x000 ALT4 0x0
+#define MVF600_PAD_PTD5__DEBUG_OUT22		0x150 0x000 ALT7 0x0
+#define MVF600_PAD_PTD6__GPIO_85		0x154 0x000 ALT0 0x0
+#define MVF600_PAD_PTD6__QSPI1_A_DQS		0x154 0x000 ALT1 0x0
+#define MVF600_PAD_PTD6__DSPI1_SIN		0x154 0x2FC ALT3 0x1
+#define MVF600_PAD_PTD6__FB_AD9			0x154 0x000 ALT4 0x0
+#define MVF600_PAD_PTD6__DEBUG_OUT23		0x154 0x000 ALT7 0x0
+#define MVF600_PAD_PTD7__GPIO_86		0x158 0x000 ALT0 0x0
+#define MVF600_PAD_PTD7__QSPI0_B_QSCK		0x158 0x000 ALT1 0x0
+#define MVF600_PAD_PTD7__DSPI1_SOUT		0x158 0x000 ALT3 0x0
+#define MVF600_PAD_PTD7__FB_AD8			0x158 0x000 ALT4 0x0
+#define MVF600_PAD_PTD7__DEBUG_OUT24		0x158 0x000 ALT7 0x0
+#define MVF600_PAD_PTD8__GPIO_87		0x15C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD8__QSPI0_B_CS0		0x15C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD8__FB_CLKOUT		0x15C 0x000 ALT2 0x0
+#define MVF600_PAD_PTD8__DSPI1_SCK		0x15C 0x2F8 ALT3 0x1
+#define MVF600_PAD_PTD8__FB_AD7			0x15C 0x000 ALT4 0x0
+#define MVF600_PAD_PTD8__DEBUG_OUT25		0x15C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD9__GPIO_88		0x160 0x000 ALT0 0x0
+#define MVF600_PAD_PTD9__QSPI0_B_DATA3		0x160 0x000 ALT1 0x0
+#define MVF600_PAD_PTD9__DSPI3_CS1		0x160 0x000 ALT2 0x0
+#define MVF600_PAD_PTD9__FB_AD6			0x160 0x000 ALT4 0x0
+#define MVF600_PAD_PTD9__SAI1_TX_SYNC		0x160 0x360 ALT6 0x0
+#define MVF600_PAD_PTD9__DCU1_B0		0x160 0x000 ALT7 0x0
+#define MVF600_PAD_PTD10__GPIO_89		0x164 0x000 ALT0 0x0
+#define MVF600_PAD_PTD10__QSPI0_B_DATA2		0x164 0x000 ALT1 0x0
+#define MVF600_PAD_PTD10__DSPI3_CS0		0x164 0x000 ALT2 0x0
+#define MVF600_PAD_PTD10__FB_AD5		0x164 0x000 ALT4 0x0
+#define MVF600_PAD_PTD10__DCU1_B1		0x164 0x000 ALT7 0x0
+#define MVF600_PAD_PTD11__GPIO_90		0x168 0x000 ALT0 0x0
+#define MVF600_PAD_PTD11__QSPI0_B_DATA1		0x168 0x000 ALT1 0x0
+#define MVF600_PAD_PTD11__DSPI3_SIN		0x168 0x000 ALT2 0x0
+#define MVF600_PAD_PTD11__FB_AD4		0x168 0x000 ALT4 0x0
+#define MVF600_PAD_PTD11__DEBUG_OUT26		0x168 0x000 ALT7 0x0
+#define MVF600_PAD_PTD12__GPIO_91		0x16C 0x000 ALT0 0x0
+#define MVF600_PAD_PTD12__QSPI0_B_DATA0		0x16C 0x000 ALT1 0x0
+#define MVF600_PAD_PTD12__DSPI3_SOUT		0x16C 0x000 ALT2 0x0
+#define MVF600_PAD_PTD12__FB_AD3		0x16C 0x000 ALT4 0x0
+#define MVF600_PAD_PTD12__DEBUG_OUT27		0x16C 0x000 ALT7 0x0
+#define MVF600_PAD_PTD13__GPIO_92		0x170 0x000 ALT0 0x0
+#define MVF600_PAD_PTD13__QSPI0_B_DQS		0x170 0x000 ALT1 0x0
+#define MVF600_PAD_PTD13__DSPI3_SCK		0x170 0x000 ALT2 0x0
+#define MVF600_PAD_PTD13__FB_AD2		0x170 0x000 ALT4 0x0
+#define MVF600_PAD_PTD13__DEBUG_OUT28		0x170 0x000 ALT7 0x0
+#define MVF600_PAD_PTB23__GPIO_93		0x174 0x000 ALT0 0x0
+#define MVF600_PAD_PTB23__SAI0_TX_BCLK		0x174 0x000 ALT1 0x0
+#define MVF600_PAD_PTB23__UART1_TX		0x174 0x380 ALT2 0x2
+#define MVF600_PAD_PTB23__SRC_RCON18		0x174 0x398 ALT3 0x1
+#define MVF600_PAD_PTB23__FB_MUXED_ALE		0x174 0x000 ALT4 0x0
+#define MVF600_PAD_PTB23__FB_TS_B		0x174 0x000 ALT5 0x0
+#define MVF600_PAD_PTB23__UART3_RTS		0x174 0x000 ALT6 0x0
+#define MVF600_PAD_PTB23__DCU1_G3		0x174 0x000 ALT7 0x0
+#define MVF600_PAD_PTB24__GPIO_94		0x178 0x000 ALT0 0x0
+#define MVF600_PAD_PTB24__SAI0_RX_BCLK		0x178 0x000 ALT1 0x0
+#define MVF600_PAD_PTB24__UART1_RX		0x178 0x37C ALT2 0x2
+#define MVF600_PAD_PTB24__SRC_RCON19		0x178 0x39C ALT3 0x1
+#define MVF600_PAD_PTB24__FB_MUXED_TSIZ0	0x178 0x000 ALT4 0x0
+#define MVF600_PAD_PTB24__NF_WE_B		0x178 0x000 ALT5 0x0
+#define MVF600_PAD_PTB24__UART3_CTS		0x178 0x000 ALT6 0x0
+#define MVF600_PAD_PTB24__DCU1_G4		0x178 0x000 ALT7 0x0
+#define MVF600_PAD_PTB25__GPIO_95		0x17C 0x000 ALT0 0x0
+#define MVF600_PAD_PTB25__SAI0_RX_DATA		0x17C 0x000 ALT1 0x0
+#define MVF600_PAD_PTB25__UART1_RTS		0x17C 0x000 ALT2 0x0
+#define MVF600_PAD_PTB25__SRC_RCON20		0x17C 0x3A0 ALT3 0x1
+#define MVF600_PAD_PTB25__FB_CS1_B		0x17C 0x000 ALT4 0x0
+#define MVF600_PAD_PTB25__NF_CE0_B		0x17C 0x000 ALT5 0x0
+#define MVF600_PAD_PTB25__DCU1_G5		0x17C 0x000 ALT7 0x0
+#define MVF600_PAD_PTB26__GPIO_96		0x180 0x000 ALT0 0x0
+#define MVF600_PAD_PTB26__SAI0_TX_DATA		0x180 0x000 ALT1 0x0
+#define MVF600_PAD_PTB26__UART1_CTS		0x180 0x378 ALT2 0x2
+#define MVF600_PAD_PTB26__SRC_RCON21		0x180 0x000 ALT3 0x0
+#define MVF600_PAD_PTB26__FB_CS0_B		0x180 0x000 ALT4 0x0
+#define MVF600_PAD_PTB26__NF_CE1_B		0x180 0x000 ALT5 0x0
+#define MVF600_PAD_PTB26__DCU1_G6		0x180 0x000 ALT7 0x0
+#define MVF600_PAD_PTB27__GPIO_97		0x184 0x000 ALT0 0x0
+#define MVF600_PAD_PTB27__SAI0_RX_SYNC		0x184 0x000 ALT1 0x0
+#define MVF600_PAD_PTB27__SRC_RCON22		0x184 0x000 ALT3 0x0
+#define MVF600_PAD_PTB27__FB_OE_B		0x184 0x000 ALT4 0x0
+#define MVF600_PAD_PTB27__FB_MUXED_TBST_B	0x184 0x000 ALT5 0x0
+#define MVF600_PAD_PTB27__NF_RE_B		0x184 0x000 ALT6 0x0
+#define MVF600_PAD_PTB27__DCU1_G7		0x184 0x000 ALT7 0x0
+#define MVF600_PAD_PTB28__GPIO_98		0x188 0x000 ALT0 0x0
+#define MVF600_PAD_PTB28__SAI0_TX_SYNC		0x188 0x000 ALT1 0x0
+#define MVF600_PAD_PTB28__SRC_RCON23		0x188 0x000 ALT3 0x0
+#define MVF600_PAD_PTB28__FB_RW_B		0x188 0x000 ALT4 0x0
+#define MVF600_PAD_PTB28__DCU1_B6		0x188 0x000 ALT7 0x0
+#define MVF600_PAD_PTC26__GPIO_99		0x18C 0x000 ALT0 0x0
+#define MVF600_PAD_PTC26__SAI1_TX_BCLK		0x18C 0x000 ALT1 0x0
+#define MVF600_PAD_PTC26__DSPI0_CS5		0x18C 0x000 ALT2 0x0
+#define MVF600_PAD_PTC26__SRC_RCON24		0x18C 0x000 ALT3 0x0
+#define MVF600_PAD_PTC26__FB_TA_B		0x18C 0x000 ALT4 0x0
+#define MVF600_PAD_PTC26__NF_RB_B		0x18C 0x000 ALT5 0x0
+#define MVF600_PAD_PTC26__DCU1_B7		0x18C 0x000 ALT7 0x0
+#define MVF600_PAD_PTC27__GPIO_100		0x190 0x000 ALT0 0x0
+#define MVF600_PAD_PTC27__SAI1_RX_BCLK		0x190 0x000 ALT1 0x0
+#define MVF600_PAD_PTC27__DSPI0_CS4		0x190 0x000 ALT2 0x0
+#define MVF600_PAD_PTC27__SRC_RCON25		0x190 0x000 ALT3 0x0
+#define MVF600_PAD_PTC27__FB_BE3_B		0x190 0x000 ALT4 0x0
+#define MVF600_PAD_PTC27__FB_CS3_B		0x190 0x000 ALT5 0x0
+#define MVF600_PAD_PTC27__NF_ALE		0x190 0x000 ALT6 0x0
+#define MVF600_PAD_PTC27__DCU1_B2		0x190 0x000 ALT7 0x0
+#define MVF600_PAD_PTC28__GPIO_101		0x194 0x000 ALT0 0x0
+#define MVF600_PAD_PTC28__SAI1_RX_DATA		0x194 0x000 ALT1 0x0
+#define MVF600_PAD_PTC28__DSPI0_CS3		0x194 0x000 ALT2 0x0
+#define MVF600_PAD_PTC28__SRC_RCON26		0x194 0x000 ALT3 0x0
+#define MVF600_PAD_PTC28__FB_BE2_B		0x194 0x000 ALT4 0x0
+#define MVF600_PAD_PTC28__FB_CS2_B		0x194 0x000 ALT5 0x0
+#define MVF600_PAD_PTC28__NF_CLE		0x194 0x000 ALT6 0x0
+#define MVF600_PAD_PTC28__DCU1_B3		0x194 0x000 ALT7 0x0
+#define MVF600_PAD_PTC29__GPIO_102		0x198 0x000 ALT0 0x0
+#define MVF600_PAD_PTC29__SAI1_TX_DATA		0x198 0x000 ALT1 0x0
+#define MVF600_PAD_PTC29__DSPI0_CS2		0x198 0x000 ALT2 0x0
+#define MVF600_PAD_PTC29__SRC_RCON27		0x198 0x000 ALT3 0x0
+#define MVF600_PAD_PTC29__FB_BE1_B		0x198 0x000 ALT4 0x0
+#define MVF600_PAD_PTC29__FB_MUXED_TSIZE1	0x198 0x000 ALT5 0x0
+#define MVF600_PAD_PTC29__DCU1_B4		0x198 0x000 ALT7 0x0
+#define MVF600_PAD_PTC30__GPIO_103		0x19C 0x000 ALT0 0x0
+#define MVF600_PAD_PTC30__SAI1_RX_SYNC		0x19C 0x000 ALT1 0x0
+#define MVF600_PAD_PTC30__DSPI1_CS2		0x19C 0x000 ALT2 0x0
+#define MVF600_PAD_PTC30__SRC_RCON28		0x19C 0x000 ALT3 0x0
+#define MVF600_PAD_PTC30__FB_MUXED_BE0_B	0x19C 0x000 ALT4 0x0
+#define MVF600_PAD_PTC30__FB_TSIZ0		0x19C 0x000 ALT5 0x0
+#define MVF600_PAD_PTC30__ADC0_SE5		0x19C 0x000 ALT6 0x0
+#define MVF600_PAD_PTC30__DCU1_B5		0x19C 0x000 ALT7 0x0
+#define MVF600_PAD_PTC31__GPIO_104		0x1A0 0x000 ALT0 0x0
+#define MVF600_PAD_PTC31__SAI1_TX_SYNC		0x1A0 0x360 ALT1 0x1
+#define MVF600_PAD_PTC31__SRC_RCON29		0x1A0 0x000 ALT3 0x0
+#define MVF600_PAD_PTC31__ADC1_SE5		0x1A0 0x000 ALT6 0x0
+#define MVF600_PAD_PTC31__DCU1_B6		0x1A0 0x000 ALT7 0x0
+#define MVF600_PAD_PTE0__GPIO_105		0x1A4 0x000 ALT0 0x0
+#define MVF600_PAD_PTE0__DCU0_HSYNC		0x1A4 0x000 ALT1 0x0
+#define MVF600_PAD_PTE0__SRC_BMODE1		0x1A4 0x000 ALT2 0x0
+#define MVF600_PAD_PTE0__LCD0			0x1A4 0x000 ALT4 0x0
+#define MVF600_PAD_PTE0__DEBUG_OUT29		0x1A4 0x000 ALT7 0x0
+#define MVF600_PAD_PTE1__GPIO_106		0x1A8 0x000 ALT0 0x0
+#define MVF600_PAD_PTE1__DCU0_VSYNC		0x1A8 0x000 ALT1 0x0
+#define MVF600_PAD_PTE1__SRC_BMODE0		0x1A8 0x000 ALT2 0x0
+#define MVF600_PAD_PTE1__LCD1			0x1A8 0x000 ALT4 0x0
+#define MVF600_PAD_PTE1__DEBUG_OUT30		0x1A8 0x000 ALT7 0x0
+#define MVF600_PAD_PTE2__GPIO_107		0x1AC 0x000 ALT0 0x0
+#define MVF600_PAD_PTE2__DCU0_PCLK		0x1AC 0x000 ALT1 0x0
+#define MVF600_PAD_PTE2__LCD2			0x1AC 0x000 ALT4 0x0
+#define MVF600_PAD_PTE2__DEBUG_OUT31		0x1AC 0x000 ALT7 0x0
+#define MVF600_PAD_PTE3__GPIO_108		0x1B0 0x000 ALT0 0x0
+#define MVF600_PAD_PTE3__DCU0_TAG		0x1B0 0x000 ALT1 0x0
+#define MVF600_PAD_PTE3__LCD3			0x1B0 0x000 ALT4 0x0
+#define MVF600_PAD_PTE3__DEBUG_OUT32		0x1B0 0x000 ALT7 0x0
+#define MVF600_PAD_PTE4__GPIO_109		0x1B4 0x000 ALT0 0x0
+#define MVF600_PAD_PTE4__DCU0_DE		0x1B4 0x000 ALT1 0x0
+#define MVF600_PAD_PTE4__LCD4			0x1B4 0x000 ALT4 0x0
+#define MVF600_PAD_PTE4__DEBUG_OUT33		0x1B4 0x000 ALT7 0x0
+#define MVF600_PAD_PTE5__GPIO_110		0x1B8 0x000 ALT0 0x0
+#define MVF600_PAD_PTE5__DCU0_R0		0x1B8 0x000 ALT1 0x0
+#define MVF600_PAD_PTE5__LCD5			0x1B8 0x000 ALT4 0x0
+#define MVF600_PAD_PTE5__DEBUG_OUT34		0x1B8 0x000 ALT7 0x0
+#define MVF600_PAD_PTE6__GPIO_111		0x1BC 0x000 ALT0 0x0
+#define MVF600_PAD_PTE6__DCU0_R1		0x1BC 0x000 ALT1 0x0
+#define MVF600_PAD_PTE6__LCD6			0x1BC 0x000 ALT4 0x0
+#define MVF600_PAD_PTE6__DEBUG_OUT35		0x1BC 0x000 ALT7 0x0
+#define MVF600_PAD_PTE7__GPIO_112		0x1C0 0x000 ALT0 0x0
+#define MVF600_PAD_PTE7__DCU0_R2		0x1C0 0x000 ALT1 0x0
+#define MVF600_PAD_PTE7__SRC_RCON0		0x1C0 0x000 ALT3 0x0
+#define MVF600_PAD_PTE7__LCD7			0x1C0 0x000 ALT4 0x0
+#define MVF600_PAD_PTE7__DEBUG_OUT36		0x1C0 0x000 ALT7 0x0
+#define MVF600_PAD_PTE8__GPIO_113		0x1C4 0x000 ALT0 0x0
+#define MVF600_PAD_PTE8__DCU0_R3		0x1C4 0x000 ALT1 0x0
+#define MVF600_PAD_PTE8__SRC_RCON1		0x1C4 0x000 ALT3 0x0
+#define MVF600_PAD_PTE8__LCD8			0x1C4 0x000 ALT4 0x0
+#define MVF600_PAD_PTE8__DEBUG_OUT37		0x1C4 0x000 ALT7 0x0
+#define MVF600_PAD_PTE9__GPIO_114		0x1C8 0x000 ALT0 0x0
+#define MVF600_PAD_PTE9__DCU0_R4		0x1C8 0x000 ALT1 0x0
+#define MVF600_PAD_PTE9__SRC_RCON2		0x1C8 0x000 ALT3 0x0
+#define MVF600_PAD_PTE9__LCD9			0x1C8 0x000 ALT4 0x0
+#define MVF600_PAD_PTE9__DEBUG_OUT38		0x1C8 0x000 ALT7 0x0
+#define MVF600_PAD_PTE10__GPIO_115		0x1CC 0x000 ALT0 0x0
+#define MVF600_PAD_PTE10__DCU0_R5		0x1CC 0x000 ALT1 0x0
+#define MVF600_PAD_PTE10__SRC_RCON3		0x1CC 0x000 ALT3 0x0
+#define MVF600_PAD_PTE10__LCD10			0x1CC 0x000 ALT4 0x0
+#define MVF600_PAD_PTE10__DEBUG_OUT39		0x1CC 0x000 ALT7 0x0
+#define MVF600_PAD_PTE11__GPIO_116		0x1D0 0x000 ALT0 0x0
+#define MVF600_PAD_PTE11__DCU0_R6		0x1D0 0x000 ALT1 0x0
+#define MVF600_PAD_PTE11__SRC_RCON4		0x1D0 0x000 ALT3 0x0
+#define MVF600_PAD_PTE11__LCD11			0x1D0 0x000 ALT4 0x0
+#define MVF600_PAD_PTE11__DEBUG_OUT40		0x1D0 0x000 ALT7 0x0
+#define MVF600_PAD_PTE12__GPIO_117		0x1D4 0x000 ALT0 0x0
+#define MVF600_PAD_PTE12__DCU0_R7		0x1D4 0x000 ALT1 0x0
+#define MVF600_PAD_PTE12__DSPI1_CS3		0x1D4 0x000 ALT2 0x0
+#define MVF600_PAD_PTE12__SRC_RCON5		0x1D4 0x000 ALT3 0x0
+#define MVF600_PAD_PTE12__LCD12			0x1D4 0x000 ALT4 0x0
+#define MVF600_PAD_PTE12__LPT_ALT0		0x1D4 0x000 ALT7 0x0
+#define MVF600_PAD_PTE13__GPIO_118		0x1D8 0x000 ALT0 0x0
+#define MVF600_PAD_PTE13__DCU0_G0		0x1D8 0x000 ALT1 0x0
+#define MVF600_PAD_PTE13__LCD13			0x1D8 0x000 ALT4 0x0
+#define MVF600_PAD_PTE13__DEBUG_OUT41		0x1D8 0x000 ALT7 0x0
+#define MVF600_PAD_PTE14__GPIO_119		0x1DC 0x000 ALT0 0x0
+#define MVF600_PAD_PTE14__DCU0_G1		0x1DC 0x000 ALT1 0x0
+#define MVF600_PAD_PTE14__LCD14			0x1DC 0x000 ALT4 0x0
+#define MVF600_PAD_PTE14__DEBUG_OUT42		0x1DC 0x000 ALT7 0x0
+#define MVF600_PAD_PTE15__GPIO_120		0x1E0 0x000 ALT0 0x0
+#define MVF600_PAD_PTE15__DCU0_G2		0x1E0 0x000 ALT1 0x0
+#define MVF600_PAD_PTE15__SRC_RCON6		0x1E0 0x000 ALT3 0x0
+#define MVF600_PAD_PTE15__LCD15			0x1E0 0x000 ALT4 0x0
+#define MVF600_PAD_PTE15__DEBUG_OUT43		0x1E0 0x000 ALT7 0x0
+#define MVF600_PAD_PTE16__GPIO_121		0x1E4 0x000 ALT0 0x0
+#define MVF600_PAD_PTE16__DCU0_G3		0x1E4 0x000 ALT1 0x0
+#define MVF600_PAD_PTE16__SRC_RCON7		0x1E4 0x000 ALT3 0x0
+#define MVF600_PAD_PTE16__LCD16			0x1E4 0x000 ALT4 0x0
+#define MVF600_PAD_PTE17__GPIO_122		0x1E8 0x000 ALT0 0x0
+#define MVF600_PAD_PTE17__DCU0_G4		0x1E8 0x000 ALT1 0x0
+#define MVF600_PAD_PTE17__SRC_RCON8		0x1E8 0x000 ALT3 0x0
+#define MVF600_PAD_PTE17__LCD17			0x1E8 0x000 ALT4 0x0
+#define MVF600_PAD_PTE18__GPIO_123		0x1EC 0x000 ALT0 0x0
+#define MVF600_PAD_PTE18__DCU0_G5		0x1EC 0x000 ALT1 0x0
+#define MVF600_PAD_PTE18__SRC_RCON9		0x1EC 0x000 ALT3 0x0
+#define MVF600_PAD_PTE18__LCD18			0x1EC 0x000 ALT4 0x0
+#define MVF600_PAD_PTE19__GPIO_124		0x1F0 0x000 ALT0 0x0
+#define MVF600_PAD_PTE19__DCU0_G6		0x1F0 0x000 ALT1 0x0
+#define MVF600_PAD_PTE19__SRC_RCON10		0x1F0 0x000 ALT3 0x0
+#define MVF600_PAD_PTE19__LCD19			0x1F0 0x000 ALT4 0x0
+#define MVF600_PAD_PTE19__I2C0_SCL		0x1F0 0x33C ALT5 0x3
+#define MVF600_PAD_PTE20__GPIO_125		0x1F4 0x000 ALT0 0x0
+#define MVF600_PAD_PTE20__DCU0_G7		0x1F4 0x000 ALT1 0x0
+#define MVF600_PAD_PTE20__SRC_RCON11		0x1F4 0x000 ALT3 0x0
+#define MVF600_PAD_PTE20__LCD20			0x1F4 0x000 ALT4 0x0
+#define MVF600_PAD_PTE20__I2C0_SDA		0x1F4 0x340 ALT5 0x3
+#define MVF600_PAD_PTE20__EWM_IN		0x1F4 0x000 ALT7 0x0
+#define MVF600_PAD_PTE21__GPIO_126		0x1F8 0x000 ALT0 0x0
+#define MVF600_PAD_PTE21__DCU0_B0		0x1F8 0x000 ALT1 0x0
+#define MVF600_PAD_PTE21__LCD21			0x1F8 0x000 ALT4 0x0
+#define MVF600_PAD_PTE22__GPIO_127		0x1FC 0x000 ALT0 0x0
+#define MVF600_PAD_PTE22__DCU0_B1		0x1FC 0x000 ALT1 0x0
+#define MVF600_PAD_PTE22__LCD22			0x1FC 0x000 ALT4 0x0
+#define MVF600_PAD_PTE23__GPIO_128		0x200 0x000 ALT0 0x0
+#define MVF600_PAD_PTE23__DCU0_B2		0x200 0x000 ALT1 0x0
+#define MVF600_PAD_PTE23__SRC_RCON12		0x200 0x000 ALT3 0x0
+#define MVF600_PAD_PTE23__LCD23			0x200 0x000 ALT4 0x0
+#define MVF600_PAD_PTE24__GPIO_129		0x204 0x000 ALT0 0x0
+#define MVF600_PAD_PTE24__DCU0_B3		0x204 0x000 ALT1 0x0
+#define MVF600_PAD_PTE24__SRC_RCON13		0x204 0x000 ALT3 0x0
+#define MVF600_PAD_PTE24__LCD24			0x204 0x000 ALT4 0x0
+#define MVF600_PAD_PTE25__GPIO_130		0x208 0x000 ALT0 0x0
+#define MVF600_PAD_PTE25__DCU0_B4		0x208 0x000 ALT1 0x0
+#define MVF600_PAD_PTE25__SRC_RCON14		0x208 0x000 ALT3 0x0
+#define MVF600_PAD_PTE25__LCD25			0x208 0x000 ALT4 0x0
+#define MVF600_PAD_PTE26__GPIO_131		0x20C 0x000 ALT0 0x0
+#define MVF600_PAD_PTE26__DCU0_B5		0x20C 0x000 ALT1 0x0
+#define MVF600_PAD_PTE26__SRC_RCON15		0x20C 0x000 ALT3 0x0
+#define MVF600_PAD_PTE26__LCD26			0x20C 0x000 ALT4 0x0
+#define MVF600_PAD_PTE27__GPIO_132		0x210 0x000 ALT0 0x0
+#define MVF600_PAD_PTE27__DCU0_B6		0x210 0x000 ALT1 0x0
+#define MVF600_PAD_PTE27__SRC_RCON16		0x210 0x000 ALT3 0x0
+#define MVF600_PAD_PTE27__LCD27			0x210 0x000 ALT4 0x0
+#define MVF600_PAD_PTE27__I2C1_SCL		0x210 0x344 ALT5 0x3
+#define MVF600_PAD_PTE28__GPIO_133		0x214 0x000 ALT0 0x0
+#define MVF600_PAD_PTE28__DCU0_B7		0x214 0x000 ALT1 0x0
+#define MVF600_PAD_PTE28__SRC_RCON17		0x214 0x000 ALT3 0x0
+#define MVF600_PAD_PTE28__LCD28			0x214 0x000 ALT4 0x0
+#define MVF600_PAD_PTE28__I2C1_SDA		0x214 0x348 ALT5 0x3
+#define MVF600_PAD_PTE28__EWM_OUT		0x214 0x000 ALT7 0x0
+#define MVF600_PAD_PTA7__GPIO_134		0x218 0x000 ALT0 0x0
+#define MVF600_PAD_PTA7__VIU_PIX_CLK		0x218 0x3AC ALT1 0x1
+
+#endif
diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi
new file mode 100644
index 0000000..a3c3353
--- /dev/null
+++ b/arch/arm/boot/dts/mvf600.dtsi
@@ -0,0 +1,475 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton.dtsi"
+#include "mvf600-pinfunc.h"
+#include <dt-bindings/clock/mvf600-clock.h>
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a5";
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sxosc {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		fxosc {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		aips0: aips-bus at 40000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-parent = <&intc>;
+			reg = <0x40000000 0x70000>;
+			ranges;
+
+			mscm: mscm at 40001000 {
+				compatible = "fsl,mvf600-mscm";
+				reg = <0x40001000 0x1000>;
+			};
+
+			intc: interrupt-controller at 40002000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				reg = <0x40003000 0x1000>,
+				      <0x40002100 0x100>;
+			};
+
+			L2: l2-cache at 40006000 {
+				compatible = "arm,pl310-cache";
+				reg = <0x40006000 0x1000>;
+				cache-unified;
+				cache-level = <2>;
+				arm,data-latency = <1 1 1>;
+				arm,tag-latency = <2 2 2>;
+			};
+
+			uart0: serial at 40027000 {
+				compatible = "fsl,mvf600-uart","fsl,lpuart";
+				reg = <0x40027000 0x1000>;
+				interrupts = <0 61 0x00>;
+				clocks = <&clks MVF600_CLK_UART0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart1: serial at 40028000 {
+				compatible = "fsl,mvf600-uart","fsl,lpuart";
+				reg = <0x40028000 0x1000>;
+				interrupts = <0 62 0x04>;
+				clocks = <&clks MVF600_CLK_UART1>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart2: serial at 40029000 {
+				compatible = "fsl,mvf600-uart","fsl,lpuart";
+				reg = <0x40029000 0x1000>;
+				interrupts = <0 63 0x04>;
+				clocks = <&clks MVF600_CLK_UART2>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart3: serial at 4002a000 {
+				compatible = "fsl,mvf600-uart","fsl,lpuart";
+				reg = <0x4002a000 0x1000>;
+				interrupts = <0 64 0x04>;
+				clocks = <&clks MVF600_CLK_UART3>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			sai2: sai at 40031000 {
+				compatible = "fsl,mvf600-sai";
+				reg = <0x40031000 0x1000>;
+				interrupts = <0 86 0x04>;
+				clocks = <&clks MVF600_CLK_SAI2>;
+				clock-names = "sai";
+				status = "disabled";
+			};
+
+			pit:pit at 40037000 {
+				compatible = "fsl,mvf600-pit";
+				reg = <0x40037000 0x1000>;
+				interrupts = <0 39 0x04>;
+				clock-names = "pit";
+				clocks = <&clks MVF600_CLK_PIT>;
+			};
+
+			wdog at 4003e000 {
+				compatible = "fsl,mvf600-wdt","fsl,imx21-wdt";
+				reg = <0x4003e000 0x1000>;
+				clock-names = "wdog";
+				clocks = <&clks MVF600_CLK_WDT>;
+			};
+
+			qspi0: quadspi at 40044000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,mvf600-qspi";
+				reg = <0x40044000 0x1000>;
+				interrupts = <0 24 0x04>;
+				clocks = <&clks MVF600_CLK_QSPI0_EN>,
+					<&clks MVF600_CLK_QSPI0>;
+				clock-names = "qspi0_en", "qspi0";
+				status = "disabled";
+			};
+
+			iomuxc: iomuxc at 40048000 {
+				compatible = "fsl,mvf600-iomuxc";
+				reg = <0x40048000 0x1000>;
+				#gpio-range-cells = <2>;
+
+				/* functions and groups pins */
+
+				dcu0 {
+					pinctrl_dcu0_1: dcu0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB8__GPIO_30	0x42
+						MVF600_PAD_PTE0__DCU0_HSYNC	0x42
+						MVF600_PAD_PTE1__DCU0_VSYNC	0x42
+						MVF600_PAD_PTE2__DCU0_PCLK	0x42
+						MVF600_PAD_PTE4__DCU0_DE	0x42
+						MVF600_PAD_PTE5__DCU0_R0	0x42
+						MVF600_PAD_PTE6__DCU0_R1	0x42
+						MVF600_PAD_PTE7__DCU0_R2	0x42
+						MVF600_PAD_PTE8__DCU0_R3	0x42
+						MVF600_PAD_PTE9__DCU0_R4	0x42
+						MVF600_PAD_PTE10__DCU0_R5	0x42
+						MVF600_PAD_PTE11__DCU0_R6	0x42
+						MVF600_PAD_PTE12__DCU0_R7	0x42
+						MVF600_PAD_PTE13__DCU0_G0	0x42
+						MVF600_PAD_PTE14__DCU0_G1	0x42
+						MVF600_PAD_PTE15__DCU0_G2	0x42
+						MVF600_PAD_PTE16__DCU0_G3	0x42
+						MVF600_PAD_PTE17__DCU0_G4	0x42
+						MVF600_PAD_PTE18__DCU0_G5	0x42
+						MVF600_PAD_PTE19__DCU0_G6	0x42
+						MVF600_PAD_PTE20__DCU0_G7	0x42
+						MVF600_PAD_PTE21__DCU0_B0	0x42
+						MVF600_PAD_PTE22__DCU0_B1	0x42
+						MVF600_PAD_PTE23__DCU0_B2	0x42
+						MVF600_PAD_PTE24__DCU0_B3	0x42
+						MVF600_PAD_PTE25__DCU0_B4	0x42
+						MVF600_PAD_PTE26__DCU0_B5	0x42
+						MVF600_PAD_PTE27__DCU0_B6	0x42
+						MVF600_PAD_PTE28__DCU0_B7	0x42
+						>;
+					};
+				};
+
+				dspi0 {
+					pinctrl_dspi0_1: dspi0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB19__DSPI0_CS0	0x1182
+						MVF600_PAD_PTB20__DSPI0_SIN	0x1181
+						MVF600_PAD_PTB21__DSPI0_SOUT	0x1182
+						MVF600_PAD_PTB22__DSPI0_SCK	0x1182
+						>;
+					};
+				};
+
+				esdhc1 {
+					pinctrl_esdhc1_1: esdhc1grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA24__ESDHC1_CLK	0x31ef
+						MVF600_PAD_PTA25__ESDHC1_CMD	0x31ef
+						MVF600_PAD_PTA26__ESDHC1_DAT0	0x31ef
+						MVF600_PAD_PTA27__ESDHC1_DAT1	0x31ef
+						MVF600_PAD_PTA28__ESDHC1_DATA2	0x31ef
+						MVF600_PAD_PTA29__ESDHC1_DAT3	0x31ef
+						MVF600_PAD_PTA7__GPIO_134	0x219d
+						>;
+					};
+				};
+
+				fec0 {
+					pinctrl_fec0_1: fec0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA6__RMII_CLKIN		0x30d1
+						MVF600_PAD_PTC0__ENET_RMII0_MDC		0x30d3
+						MVF600_PAD_PTC1__ENET_RMII0_MDIO	0x30d1
+						MVF600_PAD_PTC2__ENET_RMII0_CRS		0x30d1
+						MVF600_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
+						MVF600_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
+						MVF600_PAD_PTC5__ENET_RMII0_RXER	0x30d1
+						MVF600_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
+						MVF600_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
+						MVF600_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
+						>;
+					};
+				};
+
+				fec1 {
+					pinctrl_fec1_1: fec1grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTC9__ENET_RMII1_MDC		0x30d2
+						MVF600_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
+						MVF600_PAD_PTC11__ENET_RMII1_CRS	0x30d1
+						MVF600_PAD_PTC12__ENET_RMII_RXD1	0x30d1
+						MVF600_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
+						MVF600_PAD_PTC14__ENET_RMII1_RXER	0x30d1
+						MVF600_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
+						MVF600_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
+						MVF600_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
+						>;
+					};
+				};
+
+				i2c0 {
+					pinctrl_i2c0_1: i2c0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB14__I2C0_SCL	0x30d3
+						MVF600_PAD_PTB15__I2C0_SDA	0x30d3
+						>;
+					};
+				};
+
+				pwm0 {
+					pinctrl_pwm0_1: pwm0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB0__FTM0_CH0	0x1582
+						MVF600_PAD_PTB1__FTM0_CH1	0x1582
+						MVF600_PAD_PTB2__FTM0_CH2	0x1582
+						MVF600_PAD_PTB3__FTM0_CH3	0x1582
+						MVF600_PAD_PTB6__FTM0_CH6	0x1582
+						MVF600_PAD_PTB7__FTM0_CH7	0x1582
+						>;
+					};
+				};
+
+				qspi0 {
+					pinctrl_qspi0_1: qspi0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTD0__QSPI0_A_QSCK	0x307b
+						MVF600_PAD_PTD1__QSPI0_A_CS0	0x307f
+						MVF600_PAD_PTD2__QSPI0_A_DATA3	0x3073
+						MVF600_PAD_PTD3__QSPI0_A_DATA2	0x3073
+						MVF600_PAD_PTD4__QSPI0_A_DATA1	0x3073
+						MVF600_PAD_PTD5__QSPI0_A_DATA0	0x307b
+						MVF600_PAD_PTD7__QSPI0_B_QSCK	0x307b
+						MVF600_PAD_PTD8__QSPI0_B_CS0	0x307f
+						MVF600_PAD_PTD9__QSPI0_B_DATA3	0x3073
+						MVF600_PAD_PTD10__QSPI0_B_DATA2	0x3073
+						MVF600_PAD_PTD11__QSPI0_B_DATA1	0x3073
+						MVF600_PAD_PTD12__QSPI0_B_DATA0	0x307b
+						>;
+					};
+				};
+
+				sai2 {
+					pinctrl_sai2_1: sai2grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA16__SAI2_TX_BCLK		0x02ed
+						MVF600_PAD_PTA18__SAI2_TX_DATA		0x02ee
+						MVF600_PAD_PTA19__SAI2_TX_SYNC		0x02ed
+						MVF600_PAD_PTA21__SAI2_RX_BCLK		0x02ed
+						MVF600_PAD_PTA22__SAI2_RX_DATA		0x02ed
+						MVF600_PAD_PTA23__SAI2_RX_SYNC		0x02ed
+						MVF600_PAD_PTB18__EXT_AUDIO_MCLK	0x02ed
+						>;
+					};
+				};
+
+				touchscreen0 {
+					pinctrl_ts0_1: ts0grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA31__GPIO_21	0x219d
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTB4__UART1_TX(0x21a2)
+						MVF600_PAD_PTB5__UART1_RX(0x21a1)
+						>;
+					};
+				};
+
+				usbvbus {
+					pinctrl_usbvbus_1: usbvbusgrp_1 {
+						fsl,pins = <
+						MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c)
+						MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c)
+						>;
+					};
+				};
+
+			};
+
+			gpio1: gpio at 40049000 {
+				compatible = "fsl,mvf600-gpio";
+				reg = <0x40049000 0x1000 0x400ff000 0x40>;
+				interrupts = <0 107 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 32>;
+			};
+
+			gpio2: gpio at 4004a000 {
+				compatible = "fsl,mvf600-gpio";
+				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+				interrupts = <0 108 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 32 32>;
+			};
+
+			gpio3: gpio at 4004b000 {
+				compatible = "fsl,mvf600-gpio";
+				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+				interrupts = <0 109 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 64 32>;
+			};
+
+			gpio4: gpio at 4004c000 {
+				compatible = "fsl,mvf600-gpio";
+				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+				interrupts = <0 110 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 96 32>;
+			};
+
+			gpio5: gpio at 4004d000 {
+				compatible = "fsl,mvf600-gpio";
+				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+				interrupts = <0 111 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 128 7>;
+			};
+
+			anatop at 40050000 {
+				compatible = "fsl,mvf600-anatop";
+				reg = <0x40050000 0x1000>;
+			};
+
+			i2c0: i2c at 40066000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,mvf600-i2c";
+				reg = <0x40066000 0x1000>;
+				interrupts =<0 71 0x04>;
+				clocks = <&clks MVF600_CLK_I2C0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			clks: ccm at 4006b000 {
+				compatible = "fsl,mvf600-ccm";
+				reg = <0x4006b000 0x1000>;
+				#clock-cells = <1>;
+			};
+		};
+
+		aips1: aips-bus at 40080000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40080000 0x80000>;
+			ranges;
+
+			uart4: serial at 400a9000 {
+				compatible = "fsl,mvf600-uart","fsl,lpuart";
+				reg = <0x400a9000 0x1000>;
+				interrupts = <0 65 0x04>;
+				clocks = <&clks MVF600_CLK_UART4>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart5: serial at 400aa000 {
+				compatible = "fsl,mvf600-uart","fsl,lpuart";
+				reg = <0x400aa000 0x1000>;
+				interrupts = <0 66 0x04>;
+				clocks = <&clks MVF600_CLK_UART5>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			fec0: ethernet at 400d0000 {
+				compatible = "fsl,mvf600-fec","fsl,mvf-fec";
+				reg = <0x400d0000 0x1000>;
+				interrupts = <0 78 0x04>;
+				clocks = <&clks MVF600_CLK_ENET>,
+					<&clks MVF600_CLK_ENET>,
+					<&clks MVF600_CLK_ENET>;
+				clock-names = "ipg", "ahb", "ptp";
+			};
+
+			fec1: ethernet at 400d1000 {
+				compatible = "fsl,mvf600-fec","fsl,mvf-fec";
+				reg = <0x400d1000 0x1000>;
+				interrupts = <0 79 0x04>;
+				clocks = <&clks MVF600_CLK_ENET>,
+					<&clks MVF600_CLK_ENET>,
+					<&clks MVF600_CLK_ENET>;
+				clock-names = "ipg", "ahb", "ptp";
+			};
+		};
+	};
+};
-- 
1.8.0




From Baohua.Song at csr.com  Thu May 16 02:53:04 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Thu, 16 May 2013 14:53:04 +0800
Subject: [PATCH] ASoC: dfbmcs320: make the driver common for other BT modules
Message-ID: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>

DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
we don't want everyone to have a seperate codec driver. anyway, the
feature of Bluetooth handsfree is same on all platforms, so this patch
makes the DFBM-CS320 driver become a common BT handsfree driver.

Cc: Graeme Gregory <graeme at openmoko.org>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 sound/soc/codecs/Kconfig                         |  4 ++--
 sound/soc/codecs/Makefile                        |  4 ++--
 sound/soc/codecs/{dfbmcs320.c => bt-handsfree.c} | 28 ++++++++++++------------
 sound/soc/samsung/neo1973_wm8753.c               |  6 ++---
 4 files changed, 21 insertions(+), 21 deletions(-)
 rename sound/soc/codecs/{dfbmcs320.c => bt-handsfree.c} (57%)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index d8c4f3d..618928a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -40,7 +40,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_DA7213 if I2C
 	select SND_SOC_DA732X if I2C
 	select SND_SOC_DA9055 if I2C
-	select SND_SOC_DFBMCS320
+	select SND_SOC_BT_HANDSFREE
 	select SND_SOC_ISABELLE if I2C
 	select SND_SOC_JZ4740_CODEC
 	select SND_SOC_LM4857 if I2C
@@ -263,7 +263,7 @@ config SND_SOC_DA732X
 config SND_SOC_DA9055
 	tristate
 
-config SND_SOC_DFBMCS320
+config SND_SOC_BT_HANDSFREE
 	tristate
 
 config SND_SOC_DMIC
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 49ff127..23a8c06 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -27,7 +27,7 @@ snd-soc-da7210-objs := da7210.o
 snd-soc-da7213-objs := da7213.o
 snd-soc-da732x-objs := da732x.o
 snd-soc-da9055-objs := da9055.o
-snd-soc-dfbmcs320-objs := dfbmcs320.o
+snd-soc-bt-handsfree-objs := bt-handsfree.o
 snd-soc-dmic-objs := dmic.o
 snd-soc-isabelle-objs := isabelle.o
 snd-soc-jz4740-codec-objs := jz4740.o
@@ -154,7 +154,7 @@ obj-$(CONFIG_SND_SOC_DA7210)	+= snd-soc-da7210.o
 obj-$(CONFIG_SND_SOC_DA7213)	+= snd-soc-da7213.o
 obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
 obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
-obj-$(CONFIG_SND_SOC_DFBMCS320)	+= snd-soc-dfbmcs320.o
+obj-$(CONFIG_SND_SOC_BT_HANDSFREE)	+= snd-soc-bt-handsfree.o
 obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
 obj-$(CONFIG_SND_SOC_ISABELLE)	+= snd-soc-isabelle.o
 obj-$(CONFIG_SND_SOC_JZ4740_CODEC)	+= snd-soc-jz4740-codec.o
diff --git a/sound/soc/codecs/dfbmcs320.c b/sound/soc/codecs/bt-handsfree.c
similarity index 57%
rename from sound/soc/codecs/dfbmcs320.c
rename to sound/soc/codecs/bt-handsfree.c
index 4f4f7f4..99291e0 100644
--- a/sound/soc/codecs/dfbmcs320.c
+++ b/sound/soc/codecs/bt-handsfree.c
@@ -1,5 +1,5 @@
 /*
- * Driver for the DFBM-CS320 bluetooth module
+ * Driver for generic Bluetooth Handsfree
  * Copyright 2011 Lars-Peter Clausen <lars at metafoo.de>
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -15,8 +15,8 @@
 
 #include <sound/soc.h>
 
-static struct snd_soc_dai_driver dfbmcs320_dai = {
-	.name = "dfbmcs320-pcm",
+static struct snd_soc_dai_driver bt_handsfree_dai = {
+	.name = "bt-handsfree-pcm",
 	.playback = {
 		.channels_min = 1,
 		.channels_max = 1,
@@ -31,32 +31,32 @@ static struct snd_soc_dai_driver dfbmcs320_dai = {
 	},
 };
 
-static struct snd_soc_codec_driver soc_codec_dev_dfbmcs320;
+static struct snd_soc_codec_driver soc_codec_dev_bt_handsfree;
 
-static int dfbmcs320_probe(struct platform_device *pdev)
+static int bt_handsfree_probe(struct platform_device *pdev)
 {
-	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_dfbmcs320,
-			&dfbmcs320_dai, 1);
+	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_bt_handsfree,
+			&bt_handsfree_dai, 1);
 }
 
-static int dfbmcs320_remove(struct platform_device *pdev)
+static int bt_handsfree_remove(struct platform_device *pdev)
 {
 	snd_soc_unregister_codec(&pdev->dev);
 
 	return 0;
 }
 
-static struct platform_driver dfmcs320_driver = {
+static struct platform_driver bt_handsfree_driver = {
 	.driver = {
-		.name = "dfbmcs320",
+		.name = "bt-handsfree",
 		.owner = THIS_MODULE,
 	},
-	.probe = dfbmcs320_probe,
-	.remove = dfbmcs320_remove,
+	.probe = bt_handsfree_probe,
+	.remove = bt_handsfree_remove,
 };
 
-module_platform_driver(dfmcs320_driver);
+module_platform_driver(bt_handsfree_driver);
 
 MODULE_AUTHOR("Lars-Peter Clausen <lars at metafoo.de>");
-MODULE_DESCRIPTION("ASoC DFBM-CS320 bluethooth module driver");
+MODULE_DESCRIPTION("ASoC generic bluethooth handsfree driver");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/neo1973_wm8753.c b/sound/soc/samsung/neo1973_wm8753.c
index e591c38..bae5144 100644
--- a/sound/soc/samsung/neo1973_wm8753.c
+++ b/sound/soc/samsung/neo1973_wm8753.c
@@ -373,7 +373,7 @@ static struct snd_soc_dai_link neo1973_dai[] = {
 { /* Voice via BT */
 	.name = "Bluetooth",
 	.stream_name = "Voice",
-	.cpu_dai_name = "dfbmcs320-pcm",
+	.cpu_dai_name = "bt-handsfree-pcm",
 	.codec_dai_name = "wm8753-voice",
 	.codec_name = "wm8753.0-001a",
 	.ops = &neo1973_voice_ops,
@@ -382,8 +382,8 @@ static struct snd_soc_dai_link neo1973_dai[] = {
 
 static struct snd_soc_aux_dev neo1973_aux_devs[] = {
 	{
-		.name = "dfbmcs320",
-		.codec_name = "dfbmcs320.0",
+		.name = "bt_handsfree",
+		.codec_name = "bt_handsfree.0",
 	},
 };
 
-- 
1.8.2.3



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From lee.jones at linaro.org  Thu May 16 02:58:03 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 07:58:03 +0100
Subject: [PATCH 35/39] dmaengine: ste_dma40_ll: Replace meaningless
 register set with comment
In-Reply-To: <20130516051820.GH27639@intel.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-36-git-send-email-lee.jones@linaro.org>
 <20130516051820.GH27639@intel.com>
Message-ID: <20130516065803.GB3269@gmail.com>

> > Unsure of the author's intentions, rather than just removing the nop,
> > we're replacing it with a comment containing the possible intention
> > of the statement OR:ing with 0.
> Would be worthwhile to check w/ Linus W on this (or check whom to blame)

I did already. It was his idea to place the comment in.

The original author will on parental leave for the foreseeable future.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From prabhakar.csengg at gmail.com  Thu May 16 02:58:22 2013
From: prabhakar.csengg at gmail.com (Lad Prabhakar)
Date: Thu, 16 May 2013 12:28:22 +0530
Subject: [PATCH] ARM: davinci: dma: Convert to devm_* api
Message-ID: <1368687502-15551-1-git-send-email-prabhakar.csengg@gmail.com>

From: Lad, Prabhakar <prabhakar.csengg at gmail.com>

Use devm_ioremap_resource instead of reques_mem_region()/ioremap() and
devm_request_irq() instead of request_irq().

This ensures more consistent error values and simplifies error paths.

Signed-off-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
---
 NOte:- Boot tested on Logic-PD OMAP-L138 EVM

 arch/arm/mach-davinci/dma.c |   63 ++++++++++++++++--------------------------
 1 files changed, 24 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 45b7c71..aeda496 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1402,7 +1402,6 @@ static int __init edma_probe(struct platform_device *pdev)
 	int			irq[EDMA_MAX_CC] = {0, 0};
 	int			err_irq[EDMA_MAX_CC] = {0, 0};
 	struct resource		*r[EDMA_MAX_CC] = {NULL};
-	resource_size_t		len[EDMA_MAX_CC];
 	char			res_name[10];
 	char			irq_name[10];
 
@@ -1422,25 +1421,16 @@ static int __init edma_probe(struct platform_device *pdev)
 			found = 1;
 		}
 
-		len[j] = resource_size(r[j]);
-
-		r[j] = request_mem_region(r[j]->start, len[j],
-			dev_name(&pdev->dev));
-		if (!r[j]) {
-			status = -EBUSY;
-			goto fail1;
-		}
-
-		edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
-		if (!edmacc_regs_base[j]) {
+		edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
+		if (IS_ERR(edmacc_regs_base[j])) {
 			status = -EBUSY;
-			goto fail1;
+			goto fail;
 		}
 
 		edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
 		if (!edma_cc[j]) {
 			status = -ENOMEM;
-			goto fail1;
+			goto fail;
 		}
 
 		edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
@@ -1491,10 +1481,12 @@ static int __init edma_probe(struct platform_device *pdev)
 		sprintf(irq_name, "edma%d", j);
 		irq[j] = platform_get_irq_byname(pdev, irq_name);
 		edma_cc[j]->irq_res_start = irq[j];
-		status = request_irq(irq[j], dma_irq_handler, 0, "edma",
-					&pdev->dev);
+		status = devm_request_irq(&pdev->dev, irq[j],
+					  dma_irq_handler, 0, "edma",
+					  &pdev->dev);
 		if (status < 0) {
-			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+			dev_dbg(&pdev->dev,
+				"devm_request_irq %d failed --> %d\n",
 				irq[j], status);
 			goto fail;
 		}
@@ -1502,10 +1494,12 @@ static int __init edma_probe(struct platform_device *pdev)
 		sprintf(irq_name, "edma%d_err", j);
 		err_irq[j] = platform_get_irq_byname(pdev, irq_name);
 		edma_cc[j]->irq_res_end = err_irq[j];
-		status = request_irq(err_irq[j], dma_ccerr_handler, 0,
-					"edma_error", &pdev->dev);
+		status = devm_request_irq(&pdev->dev, err_irq[j],
+					  dma_ccerr_handler, 0,
+					  "edma_error", &pdev->dev);
 		if (status < 0) {
-			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+			dev_dbg(&pdev->dev,
+				"devm_request_irq %d failed --> %d\n",
 				err_irq[j], status);
 			goto fail;
 		}
@@ -1542,17 +1536,20 @@ static int __init edma_probe(struct platform_device *pdev)
 	}
 
 	if (tc_errs_handled) {
-		status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
-					"edma_tc0", &pdev->dev);
+		status = devm_request_irq(&pdev->dev, IRQ_TCERRINT0,
+					  dma_tc0err_handler, 0,
+					  "edma_tc0", &pdev->dev);
 		if (status < 0) {
-			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+			dev_dbg(&pdev->dev,
+				"devm_request_irq %d failed --> %d\n",
 				IRQ_TCERRINT0, status);
 			return status;
 		}
-		status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
-					"edma_tc1", &pdev->dev);
+		status = devm_request_irq(&pdev->dev, IRQ_TCERRINT,
+					  dma_tc1err_handler, 0,
+					  "edma_tc1", &pdev->dev);
 		if (status < 0) {
-			dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
+			dev_dbg(&pdev->dev, "devm_request_irq %d --> %d\n",
 				IRQ_TCERRINT, status);
 			return status;
 		}
@@ -1561,20 +1558,8 @@ static int __init edma_probe(struct platform_device *pdev)
 	return 0;
 
 fail:
-	for (i = 0; i < EDMA_MAX_CC; i++) {
-		if (err_irq[i])
-			free_irq(err_irq[i], &pdev->dev);
-		if (irq[i])
-			free_irq(irq[i], &pdev->dev);
-	}
-fail1:
-	for (i = 0; i < EDMA_MAX_CC; i++) {
-		if (r[i])
-			release_mem_region(r[i]->start, len[i]);
-		if (edmacc_regs_base[i])
-			iounmap(edmacc_regs_base[i]);
+	for (i = 0; i < EDMA_MAX_CC; i++)
 		kfree(edma_cc[i]);
-	}
 	return status;
 }
 
-- 
1.7.4.1



From b35083 at freescale.com  Thu May 16 02:15:24 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:15:24 +0800
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
Message-ID: <1368684924-1560-1-git-send-email-b35083@freescale.com>

Add Freescale Vybrid MVF600 period interrupt timer support.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  move the pit driver to drivers/clocksource.

 drivers/clocksource/Kconfig            |   5 +
 drivers/clocksource/Makefile           |   1 +
 drivers/clocksource/mvf600_pit_timer.c | 224 +++++++++++++++++++++++++++++++++
 3 files changed, 230 insertions(+)
 create mode 100644 drivers/clocksource/mvf600_pit_timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f151c6c..2808a76 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
 	  Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
 	  for all devicetree enabled platforms. This driver will be
 	  needed only on systems that do not have the Exynos MCT available.
+
+config MVF600_PIT_TIMER
+	bool
+	help
+	  Support for Period Interrupt Timer on Freescale Vybrid MVF600 SoC.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c7..f471ca3 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
 obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
+obj-$(CONFIG_MVF600_PIT_TIMER)	+= mvf600_pit_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
diff --git a/drivers/clocksource/mvf600_pit_timer.c b/drivers/clocksource/mvf600_pit_timer.c
new file mode 100644
index 0000000..74f7963
--- /dev/null
+++ b/drivers/clocksource/mvf600_pit_timer.c
@@ -0,0 +1,224 @@
+/*
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/sched_clock.h>
+
+/*
+ * 8 timers: pit0 - pit7,
+ * Each takes 0x10 Bytes register sapce
+ */
+#define PITMCR		0x00
+#define PIT0_OFFSET	0x100
+#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
+#define PITLDVAL	0x00
+#define PITCVAL		0x04
+#define PITTCTRL	0x08
+#define PITTFLG		0x0c
+
+#define PITTCTRL_TEN		(0x1 << 0)
+#define PITTCTRL_TIE		(0x1 << 1)
+#define	PITCTRL_CHN		(0x1 << 2)
+
+#define PITTFLG_TIF		0x1
+
+static struct clock_event_device clockevent_pit;
+static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+static void __iomem *clksrc_base;
+static void __iomem *clkevt_base;
+static void __iomem *sched_clock_reg;
+static unsigned long pit_cycle_per_jiffy;
+
+static inline void pit_timer_enable(void)
+{
+	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_timer_disable(void)
+{
+	__raw_writel(0, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_disable(void)
+{
+	unsigned long val;
+
+	val = __raw_readl(clkevt_base + PITTCTRL);
+	val &= ~PITTCTRL_TIE;
+	__raw_writel(val, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_enable(void)
+{
+	unsigned long val;
+
+	val = __raw_readl(clkevt_base + PITTCTRL);
+	val |= PITTCTRL_TIE;
+	__raw_writel(val, clkevt_base + PITTCTRL);
+}
+
+static void pit_irq_acknowledge(void)
+{
+	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+}
+
+static unsigned int pit_read_sched_clock(void)
+{
+	return __raw_readl(sched_clock_reg);
+}
+
+
+static int __init pit_clocksource_init(struct clk *pit_clk)
+{
+	unsigned int c = clk_get_rate(pit_clk);
+
+	sched_clock_reg = clksrc_base + PITCVAL;
+
+	setup_sched_clock(pit_read_sched_clock, 32, c);
+	return clocksource_mmio_init(clksrc_base + PITCVAL, "mvf600-pit", c,
+			300, 32, clocksource_mmio_readl_down);
+}
+
+/* set clock event */
+static int pit_set_next_event(unsigned long delta,
+				struct clock_event_device *unused)
+{
+	pit_timer_disable();
+	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
+	pit_irq_acknowledge();
+	pit_timer_enable();
+
+	return 0;
+}
+
+static void pit_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	pit_timer_disable();
+	pit_irq_acknowledge();
+
+	/* Remember timer mode */
+	clockevent_mode = mode;
+	local_irq_restore(flags);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+
+		__raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
+		pit_timer_enable();
+
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+
+		break;
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_RESUME:
+
+		break;
+	default:
+		WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
+		break;
+	}
+}
+
+static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = &clockevent_pit;
+
+	pit_irq_acknowledge();
+
+	if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT)
+		pit_timer_disable();
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction pit_timer_irq = {
+	.name		= "MVF600 pit timer",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= pit_timer_interrupt,
+};
+
+static struct clock_event_device clockevent_pit = {
+	.name		= "MVF600 pit timer",
+	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode	= pit_set_mode,
+	.set_next_event	= pit_set_next_event,
+	.rating		= 300,
+};
+
+static int __init pit_clockevent_init(struct clk *pit_clk)
+{
+	unsigned int c = clk_get_rate(pit_clk);
+
+	clockevent_pit.cpumask = cpumask_of(0);
+	clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00);
+
+	return 0;
+}
+
+static void __init pit_timer_init(struct device_node *np)
+{
+	struct clk *pit_clk;
+	void __iomem *timer_base;
+	int irq;
+
+	if (!np) {
+		pr_err("Failed to find MVF600 pit DT node\n");
+		BUG();
+	}
+
+	timer_base = of_iomap(np, 0);
+	WARN_ON(!timer_base);
+
+	/* choose PIT2 as clocksource, PIT3 as clockevent dev */
+	clksrc_base = timer_base + PITn_OFFSET(2);
+	clkevt_base = timer_base + PITn_OFFSET(3);
+
+	irq = irq_of_parse_and_map(np, 0);
+
+	pit_clk = of_clk_get(np, 0);
+	if (IS_ERR(pit_clk)) {
+		pr_err("Vybrid MVF600 pit timer: unable to get clk\n");
+		return;
+	}
+
+	clk_prepare_enable(pit_clk);
+
+	pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
+
+	__raw_writel(0x0, timer_base + PITMCR);
+
+	__raw_writel(0, clkevt_base + PITTCTRL);
+	__raw_writel(0xffffffff, clkevt_base + PITLDVAL);
+
+	__raw_writel(0, clksrc_base + PITTCTRL);
+	__raw_writel(0xffffffff, clksrc_base + PITLDVAL);
+	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
+
+	pit_clocksource_init(pit_clk);
+
+	setup_irq(irq, &pit_timer_irq);
+
+	pit_clockevent_init(pit_clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf600-pit", pit_timer_init);
-- 
1.8.0




From herbert at gondor.apana.org.au  Thu May 16 03:00:03 2013
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Thu, 16 May 2013 15:00:03 +0800
Subject: [PATCH 12/39] crypto: ux500/hash - Prepare clock before
 enabling it
In-Reply-To: <20130516065355.GA3269@gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-13-git-send-email-lee.jones@linaro.org>
 <CACRpkdYdf1j+V516CigFeGKv1B+Mf4mZk8g3ZwYAwa=rDP=7vg@mail.gmail.com>
 <20130516065355.GA3269@gmail.com>
Message-ID: <20130516070003.GA6634@gondor.apana.org.au>

On Thu, May 16, 2013 at 07:53:55AM +0100, Lee Jones wrote:
> On Wed, 15 May 2013, Linus Walleij wrote:
> 
> > On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> > 
> > > If we fail to prepare the ux500-hash clock before enabling it the
> > > platform will fail to boot. Here we insure this happens.
> > >
> > > Cc: Herbert Xu <herbert at gondor.apana.org.au>
> > > Cc: David S. Miller <davem at davemloft.net>
> > > Cc: Andreas Westin <andreas.westin at stericsson.com>
> > > Cc: linux-crypto at vger.kernel.org
> > > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > > Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > 
> > This patch seems to be totally independent of the other stuff
> > in the patch series, and it even seems like an -rc fix to me
> > (I don't think the crypto device works without this).
> > 
> > This should go into the crypto tree?
> 
> I agree. 
> 
> > Else please convince Herbert to give his ACK on this
> > before I apply it.
> 
> Pleeeeaasseee Herbert, take this patch! :)

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>

Thanks,
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From herbert at gondor.apana.org.au  Thu May 16 03:01:33 2013
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Thu, 16 May 2013 15:01:33 +0800
Subject: [PATCH 13/39] crypto: ux500/hash - Set DMA configuration
 though dma_slave_config()
In-Reply-To: <1368611522-9984-14-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-14-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516070132.GA6721@gondor.apana.org.au>

On Wed, May 15, 2013 at 10:51:36AM +0100, Lee Jones wrote:
> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
> 
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From b35083 at freescale.com  Thu May 16 02:18:15 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:18:15 +0800
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
Message-ID: <1368685096-13177-1-git-send-email-b35083@freescale.com>

Add Freescale lpuart driver support. The lpuart device
can be founded on Vybrid MVF600 and Layerscape LS-1 SoCs.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  change the uart driver name from mvf to lpuart for further share between SoCs.
  add bind doc in Documentation/devicetree/bindings/tty/serial.
  remove unused #include header lines.
  clean up code.

 .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
 drivers/tty/serial/Kconfig                         |  14 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/fsl_lpuart.c                    | 916 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 5 files changed, 948 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
 create mode 100644 drivers/tty/serial/fsl_lpuart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
new file mode 100644
index 0000000..46ffdb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
@@ -0,0 +1,14 @@
+* Freescale Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
+
+Required properties:
+- compatible : Should be "fsl,lpuart"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain uart interrupt
+
+Example:
+
+uart0: serial at 40027000 {
+	       compatible = "fsl,lpuart";
+	       reg = <0x40027000 0x1000>;
+	       interrupts = <0 61 0x00>;
+       };
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..2cea1a0 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1484,6 +1484,20 @@ config SERIAL_RP2_NR_UARTS
 	  If multiple cards are present, the default limit of 32 ports may
 	  need to be increased.
 
+config SERIAL_FSL_LPUART
+	bool "Freescale Lpuart serial port support"
+	select SERIAL_CORE
+	help
+	  Support for the on-chip LPUARTs on some Freescal SOCs.
+
+config SERIAL_FSL_LPUART_CONSOLE
+	bool "Console on Vybrid serial port"
+	depends on SERIAL_FSL_LPUART
+	select SERIAL_CORE_CONSOLE
+	help
+	  If you have enabled the lpuart serial port on the Freescale SoCs,
+	  you can make it the console by answering Y to this option.
+
 endmenu
 
 endif # TTY
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index eedfec4..cf650f0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
 obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
 obj-$(CONFIG_SERIAL_ARC)	+= arc_uart.o
 obj-$(CONFIG_SERIAL_RP2)	+= rp2.o
+obj-$(CONFIG_SERIAL_FSL_LPUART)	+= fsl_lpuart.o
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
new file mode 100644
index 0000000..8753bc2
--- /dev/null
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -0,0 +1,916 @@
+/*
+ *  Freescale lpuart ports driver
+ *
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/of_device.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/pinctrl/consumer.h>
+
+/* All registers are 8-bit width */
+#define UARTBDH			0x00
+#define UARTBDL			0x01
+#define UARTCR1			0x02
+#define UARTCR2			0x03
+#define UARTSR1			0x04
+#define UARTCR3			0x06
+#define UARTDR			0x07
+#define UARTCR4			0x0a
+#define UARTCR5			0x0b
+#define UARTMODEM		0x0d
+#define UARTPFIFO		0x10
+#define UARTCFIFO		0x11
+#define UARTSFIFO		0x12
+#define UARTTWFIFO		0x13
+#define UARTTCFIFO		0x14
+#define UARTRWFIFO		0x15
+
+#define UARTBDH_LBKDIE		0x80
+#define UARTBDH_RXEDGIE		0x40
+#define UARTBDH_SBR_MASK	0x1f
+
+#define UARTCR1_LOOPS		0x80
+#define UARTCR1_RSRC		0x20
+#define UARTCR1_M		0x10
+#define UARTCR1_WAKE		0x08
+#define UARTCR1_ILT		0x04
+#define UARTCR1_PE		0x02
+#define UARTCR1_PT		0x01
+
+#define UARTCR2_TIE		0x80
+#define UARTCR2_TCIE		0x40
+#define UARTCR2_RIE		0x20
+#define UARTCR2_ILIE		0x10
+#define UARTCR2_TE		0x08
+#define UARTCR2_RE		0x04
+#define UARTCR2_RWU		0x02
+#define UARTCR2_SBK		0x01
+
+#define UARTSR1_TDRE		0x80
+#define UARTSR1_TC		0x40
+#define UARTSR1_RDRF		0x20
+#define UARTSR1_IDLE		0x10
+#define UARTSR1_OR		0x08
+#define UARTSR1_NF		0x04
+#define UARTSR1_FE		0x02
+#define UARTSR1_PE		0x01
+
+#define UARTCR3_R8		0x80
+#define UARTCR3_T8		0x40
+#define UARTCR3_TXDIR		0x20
+#define UARTCR3_TXINV		0x10
+#define UARTCR3_ORIE		0x08
+#define UARTCR3_NEIE		0x04
+#define UARTCR3_FEIE		0x02
+#define UARTCR3_PEIE		0x01
+
+#define UARTCR4_MAEN1		0x80
+#define UARTCR4_MAEN2		0x40
+#define UARTCR4_M10		0x20
+#define UARTCR4_BRFA_MASK	0x1f
+#define UARTCR4_BRFA_OFF	0
+
+#define UARTCR5_TDMAS		0x80
+#define UARTCR5_RDMAS		0x20
+
+#define UARTMODEM_RXRTSE	0x08
+#define UARTMODEM_TXRTSPOL	0x04
+#define UARTMODEM_TXRTSE	0x02
+#define UARTMODEM_TXCTSE	0x01
+
+#define UARTPFIFO_TXFE		0x80
+#define UARTPFIFO_FIFOSIZE_MASK	0x7
+#define UARTPFIFO_TXSIZE_OFF	4
+#define UARTPFIFO_RXFE		0x08
+#define UARTPFIFO_RXSIZE_OFF	0
+
+#define UARTCFIFO_TXFLUSH	0x80
+#define UARTCFIFO_RXFLUSH	0x40
+#define UARTCFIFO_RXOFE		0x04
+#define UARTCFIFO_TXOFE		0x02
+#define UARTCFIFO_RXUFE		0x01
+
+#define UARTSFIFO_TXEMPT	0x80
+#define UARTSFIFO_RXEMPT	0x40
+#define UARTSFIFO_RXOF		0x04
+#define UARTSFIFO_TXOF		0x02
+#define UARTSFIFO_RXUF		0x01
+
+#define DRIVER_NAME	"LP-uart"
+#define DEV_NAME	"ttyLP"
+#define UART_NR		6
+
+struct lpuart_port {
+	struct uart_port	port;
+	struct clk		*clk;
+	unsigned int		tx_fifo_size;
+	unsigned int		rx_fifo_size;
+};
+
+static struct of_device_id lpuart_uart_dt_ids[] = {
+	{
+		.compatible = "fsl,lpuart",
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lpuart_uart_dt_ids);
+
+static void lpuart_stop_tx(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + UARTCR2);
+	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
+	writeb(temp, sport->port.membase + UARTCR2);
+}
+
+static void lpuart_stop_rx(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + UARTCR2);
+	writeb(temp & ~UARTCR2_RE, sport->port.membase + UARTCR2);
+}
+
+static void lpuart_enable_ms(struct uart_port *port)
+{
+}
+
+static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
+{
+	struct circ_buf *xmit = &sport->port.state->xmit;
+
+	while (!uart_circ_empty(xmit) &&
+	(readb(sport->port.membase + UARTTCFIFO) < sport->tx_fifo_size)) {
+		writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		sport->port.icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+	if (uart_circ_empty(xmit))
+		lpuart_stop_tx(&sport->port);
+}
+
+static void lpuart_start_tx(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + UARTCR2);
+	writeb(temp | UARTCR2_TIE,
+			sport->port.membase + UARTCR2);
+
+	if (readb(sport->port.membase + UARTSR1) & UARTSR1_TDRE)
+		lpuart_transmit_buffer(sport);
+}
+
+static irqreturn_t lpuart_txint(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	struct circ_buf *xmit = &sport->port.state->xmit;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+	if (sport->port.x_char) {
+		writeb(sport->port.x_char, sport->port.membase + UARTDR);
+		goto out;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
+		lpuart_stop_tx(&sport->port);
+		goto out;
+	}
+
+	lpuart_transmit_buffer(sport);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_rxint(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	unsigned int flg, ignored = 0;
+	struct tty_port *port = &sport->port.state->port;
+	unsigned long flags;
+	unsigned char r8, rx, sr;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	while (!(readb(sport->port.membase + UARTSFIFO) &
+				UARTSFIFO_RXEMPT)) {
+		flg = TTY_NORMAL;
+		sport->port.icount.rx++;
+
+		/*  To clear the FE, OR, NF, FE, PE flags when set,
+		 *  read SR1 then read DR
+		 */
+		sr = readb(sport->port.membase + UARTSR1);
+
+		r8 = readb(sport->port.membase + UARTCR3) & UARTCR3_R8;
+		rx = readb(sport->port.membase + UARTDR);
+
+		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
+			continue;
+		if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
+			if (sr & UARTSR1_PE)
+				sport->port.icount.parity++;
+			else if (sr & UARTSR1_FE)
+				sport->port.icount.frame++;
+			if (sr & UARTSR1_OR)
+				sport->port.icount.overrun++;
+
+			if (sr & sport->port.ignore_status_mask) {
+				if (++ignored > 100)
+					goto out;
+				continue;
+			}
+
+			sr &= sport->port.read_status_mask;
+
+			if (sr & UARTSR1_PE)
+				flg = TTY_PARITY;
+			else if (sr & UARTSR1_FE)
+				flg = TTY_FRAME;
+			if (sr & UARTSR1_OR)
+				flg = TTY_OVERRUN;
+
+#ifdef SUPPORT_SYSRQ
+			sport->port.sysrq = 0;
+#endif
+		}
+
+		tty_insert_flip_char(port, rx, flg);
+	}
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+
+	tty_flip_buffer_push(port);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_int(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	unsigned int sts;
+
+	sts = readb(sport->port.membase + UARTSR1);
+
+	if (sts & UARTSR1_RDRF)
+		lpuart_rxint(irq, dev_id);
+
+	if (sts & UARTSR1_TDRE &&
+		!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
+		lpuart_txint(irq, dev_id);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Return TIOCSER_TEMT when transmitter is not busy.
+ */
+static unsigned int lpuart_tx_empty(struct uart_port *port)
+{
+
+	return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
+		TIOCSER_TEMT : 0;
+}
+
+static unsigned int lpuart_get_mctrl(struct uart_port *port)
+{
+	unsigned int tmp = 0;
+	unsigned char reg;
+
+	reg = readb(port->membase + UARTMODEM);
+	if (reg & UARTMODEM_TXCTSE)
+		tmp |= TIOCM_CTS;
+
+	if (reg & UARTMODEM_RXRTSE)
+		tmp |= TIOCM_RTS;
+
+	return tmp;
+}
+
+static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	unsigned long temp;
+
+	temp = readb(port->membase + UARTMODEM) &
+			~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+	if (mctrl & TIOCM_RTS)
+		temp |= UARTMODEM_RXRTSE;
+	if (mctrl & TIOCM_CTS)
+		temp |= UARTMODEM_TXCTSE;
+
+	writeb(temp, port->membase + UARTMODEM);
+}
+
+static void lpuart_break_ctl(struct uart_port *port, int break_state)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
+
+	if (break_state != 0)
+		temp |= UARTCR2_SBK;
+
+	writeb(temp, port->membase + UARTCR2);
+
+}
+
+static void lpuart_setup_watermark(struct lpuart_port *sport)
+{
+	unsigned char val, old_cr2, cr2;
+
+	/* set receiver/transmitter trigger level. */
+	old_cr2 = cr2 = readb(sport->port.membase + UARTCR2);
+	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
+			UARTCR2_RIE | UARTCR2_RE);
+	writeb(cr2, sport->port.membase + UARTCR2);
+
+	writeb(2, sport->port.membase + UARTTWFIFO);
+	writeb(1, sport->port.membase + UARTRWFIFO);
+
+	/* determine FIFO size and enable */
+	val = readb(sport->port.membase + UARTPFIFO);
+
+	sport->tx_fifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
+		UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	sport->rx_fifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
+		UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
+			sport->port.membase + UARTPFIFO);
+
+	/* Flush the Tx and Rx FIFO to a known state */
+	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
+			sport->port.membase + UARTCFIFO);
+
+	/* restore CR2 */
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+
+}
+
+static int lpuart_startup(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	int retval;
+	unsigned long flags, temp;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	lpuart_setup_watermark(sport);
+
+	temp = readb(sport->port.membase + UARTCR2);
+	writeb(temp & ~UARTCR2_RIE, sport->port.membase + UARTCR2);
+
+	/* clear and enable interrupts */
+	temp = readb(sport->port.membase + UARTCR2);
+	temp |= UARTCR2_RIE | UARTCR2_TIE;
+	writeb(temp, sport->port.membase + UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	/*
+	 * request the IRQ
+	 */
+	retval = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
+				DRIVER_NAME, sport);
+	if (retval)
+		return retval;
+
+	return 0;
+}
+
+static void lpuart_shutdown(struct uart_port *port)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned char temp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	temp = readb(port->membase + UARTCR2);
+	temp &= ~(UARTCR2_TE | UARTCR2_RE);
+	writeb(temp, port->membase + UARTCR2);
+	/*
+	 * Disable all interrupts
+	 */
+	temp = readb(port->membase + UARTCR2);
+	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+	writeb(temp, port->membase + UARTCR2);
+	spin_unlock_irqrestore(&port->lock, flags);
+	/*
+	 * Free the irq
+	 */
+	devm_free_irq(port->dev, port->irq, sport);
+}
+
+static void
+lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
+		   struct ktermios *old)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned long flags;
+	unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+	unsigned int  baud;
+	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+	unsigned int sbr, brfa;
+
+	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
+	old_cr2 = readb(sport->port.membase + UARTCR2);
+	cr4 = readb(sport->port.membase + UARTCR4);
+	bdh = readb(sport->port.membase + UARTBDH);
+	modem = readb(sport->port.membase + UARTMODEM);
+
+	/*
+	 * We only support CS8 and CS7, and for CS7 must enable PE.
+	 * supported mode:
+	 *  - (7,e/o,1)
+	 *  - (8,n,1)
+	 *  - (8,m/s,1)
+	 *  - (8,e/o,1)
+	 */
+	while ((termios->c_cflag & CSIZE) != CS8 &&
+		(termios->c_cflag & CSIZE) != CS7) {
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= old_csize;
+		old_csize = CS8;
+	}
+
+	if ((termios->c_cflag & CSIZE) == CS8 ||
+		(termios->c_cflag & CSIZE) == CS7)
+		cr1 = old_cr1 & ~UARTCR1_M;
+
+	if (termios->c_cflag & CMSPAR) {
+		if ((termios->c_cflag & CSIZE) != CS8) {
+			termios->c_cflag &= ~CSIZE;
+			termios->c_cflag |= CS8;
+		}
+		cr1 |= UARTCR1_M;
+	}
+
+	if (termios->c_cflag & CRTSCTS) {
+		modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+	} else {
+		termios->c_cflag &= ~CRTSCTS;
+		modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		termios->c_cflag &= ~CSTOPB;
+
+	/* parity must enable when CS7 to match 8-bits format */
+	if ((termios->c_cflag & CSIZE) == CS7)
+		termios->c_cflag |= PARENB;
+
+	if ((termios->c_cflag & PARENB)) {
+		if (termios->c_cflag & CMSPAR) {
+			cr1 &= ~UARTCR1_PE;
+			cr1 |= UARTCR1_M;
+		} else {
+			cr1 |= UARTCR1_PE;
+			if ((termios->c_cflag & CSIZE) == CS8)
+				cr1 |= UARTCR1_M;
+			if (termios->c_cflag & PARODD)
+				cr1 |= UARTCR1_PT;
+			else
+				cr1 &= ~UARTCR1_PT;
+		}
+	}
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	sport->port.read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		sport->port.read_status_mask |=
+					(UARTSR1_FE | UARTSR1_PE);
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		sport->port.read_status_mask |= UARTSR1_FE;
+
+	/*
+	 * Characters to ignore
+	 */
+	sport->port.ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		sport->port.ignore_status_mask |= UARTSR1_PE;
+	if (termios->c_iflag & IGNBRK) {
+		sport->port.ignore_status_mask |= UARTSR1_FE;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			sport->port.ignore_status_mask |= UARTSR1_OR;
+	}
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/* wait transmit engin complete */
+	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+		barrier();
+
+	writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
+			sport->port.membase + UARTCR2);
+
+	/* disable transmit and receive */
+	sbr = sport->port.uartclk / (16 * baud);
+	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
+
+	bdh &= ~UARTBDH_SBR_MASK;
+	bdh |= (sbr >> 8) & 0x1F;
+
+	cr4 &= ~UARTCR4_BRFA_MASK;
+	brfa &= UARTCR4_BRFA_MASK;
+	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
+	writeb(bdh, sport->port.membase + UARTBDH);
+	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
+	writeb(cr1, sport->port.membase + UARTCR1);
+	writeb(modem, sport->port.membase + UARTMODEM);
+
+	/* restore control register */
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
+static const char *lpuart_type(struct uart_port *port)
+{
+	return "FSL_LPUART";
+}
+
+static void lpuart_release_port(struct uart_port *port)
+{
+	/* Nothing to do */
+}
+
+static int lpuart_request_port(struct uart_port *port)
+{
+	return  0;
+}
+/*
+ * Configure/autoconfigure the port.
+ */
+static void lpuart_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE)
+		port->type = PORT_LPUART;
+}
+
+static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
+		ret = -EINVAL;
+	if (port->irq != ser->irq)
+		ret = -EINVAL;
+	if (ser->io_type != UPIO_MEM)
+		ret = -EINVAL;
+	if (port->uartclk / 16 != ser->baud_base)
+		ret = -EINVAL;
+	if (port->iobase != ser->port)
+		ret = -EINVAL;
+	if (ser->hub6 != 0)
+		ret = -EINVAL;
+	return ret;
+}
+
+static struct uart_ops lpuart_pops = {
+	.tx_empty	= lpuart_tx_empty,
+	.set_mctrl	= lpuart_set_mctrl,
+	.get_mctrl	= lpuart_get_mctrl,
+	.stop_tx	= lpuart_stop_tx,
+	.start_tx	= lpuart_start_tx,
+	.stop_rx	= lpuart_stop_rx,
+	.enable_ms	= lpuart_enable_ms,
+	.break_ctl	= lpuart_break_ctl,
+	.startup	= lpuart_startup,
+	.shutdown	= lpuart_shutdown,
+	.set_termios	= lpuart_set_termios,
+	.type		= lpuart_type,
+	.request_port	= lpuart_request_port,
+	.release_port	= lpuart_release_port,
+	.config_port	= lpuart_config_port,
+	.verify_port	= lpuart_verify_port,
+};
+
+static struct lpuart_port *lpuart_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
+static void lpuart_console_putchar(struct uart_port *port, int ch)
+{
+	while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
+		barrier();
+
+	writeb(ch, port->membase + UARTDR);
+}
+
+static void
+lpuart_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct lpuart_port *sport = lpuart_ports[co->index];
+	unsigned int  old_cr2, cr2;
+
+	/*
+	 * First, save CR2 and then disable interrupts
+	 */
+	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
+
+	cr2 |= (UARTCR2_TE |  UARTCR2_RE);
+	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+
+	writeb(cr2, sport->port.membase + UARTCR2);
+
+	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
+
+	/*
+	 * wait for transmitter finish complete and restore CR2
+	 */
+	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+		barrier();
+
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+}
+
+/*
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+lpuart_console_get_options(struct lpuart_port *sport, int *baud,
+			   int *parity, int *bits)
+{
+	unsigned char cr, bdh, bdl, brfa;
+	unsigned int sbr, uartclk;
+	unsigned int baud_raw;
+
+	cr = readb(sport->port.membase + UARTCR2);
+	cr &= UARTCR2_TE | UARTCR2_RE;
+	if (!cr)
+		return;
+
+	/* ok, the port was enabled */
+
+	cr = readb(sport->port.membase + UARTCR1);
+
+	*parity = 'n';
+	if (cr & UARTCR1_PE) {
+		if (cr & UARTCR1_PT)
+			*parity = 'o';
+		else
+			*parity = 'e';
+	}
+
+	if (cr & UARTCR1_M)
+		*bits = 9;
+	else
+		*bits = 8;
+
+	bdh = readb(sport->port.membase + UARTBDH);
+	bdh &= UARTBDH_SBR_MASK;
+	bdl = readb(sport->port.membase + UARTBDL);
+	sbr = bdh;
+	sbr <<= 8;
+	sbr |= bdl;
+	brfa = readb(sport->port.membase + UARTCR4);
+	brfa &= UARTCR4_BRFA_MASK;
+
+	uartclk = clk_get_rate(sport->clk);
+	/*
+	 * Baud = mod_clk/(16*(sbr[13]+(brfa)/32)
+	 */
+	baud_raw = uartclk / (16 * (sbr + brfa / 32));
+
+	if (*baud != baud_raw)
+		printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+				"from %d to %d\n", baud_raw, *baud);
+}
+
+static int __init lpuart_console_setup(struct console *co, char *options)
+{
+	struct lpuart_port *sport;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
+		co->index = 0;
+	sport = lpuart_ports[co->index];
+
+	if (sport == NULL)
+		return -ENODEV;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		lpuart_console_get_options(sport, &baud, &parity, &bits);
+
+	lpuart_setup_watermark(sport);
+
+	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver lpuart_reg;
+static struct console lpuart_console = {
+	.name		= DEV_NAME,
+	.write		= lpuart_console_write,
+	.device		= uart_console_device,
+	.setup		= lpuart_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &lpuart_reg,
+};
+
+#define LPUART_CONSOLE	(&lpuart_console)
+#else
+#define LPUART_CONSOLE	NULL
+#endif
+
+static struct uart_driver lpuart_reg = {
+	.owner		= THIS_MODULE,
+	.driver_name	= DRIVER_NAME,
+	.dev_name	= DEV_NAME,
+	.nr		= ARRAY_SIZE(lpuart_ports),
+	.cons		= LPUART_CONSOLE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int lpuart_uart_suspend(struct device *dev)
+{
+	struct lpuart_port *sport = dev_get_drvdata(dev);
+
+	uart_suspend_port(&lpuart_reg, &sport->port);
+
+	return 0;
+}
+
+static int lpuart_uart_resume(struct device *dev)
+{
+	struct lpuart_port *sport = dev_get_drvdata(dev);
+
+	uart_resume_port(&lpuart_reg, &sport->port);
+
+	return 0;
+}
+#endif
+
+static int lpuart_uart_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct lpuart_port *sport;
+	void __iomem *base;
+	struct resource *res;
+	int ret;
+
+	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+	if (!sport)
+		return -ENOMEM;
+
+	pdev->dev.coherent_dma_mask = 0;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!base)
+		return -ENOMEM;
+
+	sport->port.dev = &pdev->dev;
+	sport->port.mapbase = res->start;
+	sport->port.membase = base;
+	sport->port.type = PORT_LPUART;
+	sport->port.iotype = UPIO_MEM;
+	sport->port.irq = platform_get_irq(pdev, 0);
+	sport->port.ops = &lpuart_pops;
+	sport->port.flags = UPF_BOOT_AUTOCONF;
+
+	sport->clk = devm_clk_get(&pdev->dev, "ipg");
+	if (IS_ERR(sport->clk)) {
+		ret = PTR_ERR(sport->clk);
+		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+		return ret;
+	}
+
+	clk_prepare_enable(sport->clk);
+
+	sport->port.uartclk = clk_get_rate(sport->clk);
+
+	lpuart_ports[sport->port.line] = sport;
+
+	platform_set_drvdata(pdev, &sport->port);
+
+	ret = uart_add_one_port(&lpuart_reg, &sport->port);
+
+	if (ret) {
+		clk_disable_unprepare(sport->clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int lpuart_uart_remove(struct platform_device *pdev)
+{
+	struct lpuart_port *sport = platform_get_drvdata(pdev);
+
+	uart_remove_one_port(&lpuart_reg, &sport->port);
+
+	clk_disable_unprepare(sport->clk);
+
+	return 0;
+}
+
+static const struct dev_pm_ops lpuart_uart_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(lpuart_uart_suspend, lpuart_uart_resume)
+};
+
+static struct platform_driver lpuart_uart_driver = {
+	.probe		= lpuart_uart_probe,
+	.remove		= lpuart_uart_remove,
+	.driver		= {
+		.name	= "lpuart-uart",
+		.owner	= THIS_MODULE,
+		.of_match_table = lpuart_uart_dt_ids,
+		.pm	= &lpuart_uart_pm_ops,
+	},
+};
+
+static int __init lpuart_serial_init(void)
+{
+	int ret;
+
+	pr_info("serial: Freescale lpuart driver\n");
+
+	ret = uart_register_driver(&lpuart_reg);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&lpuart_uart_driver);
+	if (ret)
+		uart_unregister_driver(&lpuart_reg);
+
+	return 0;
+}
+
+static void __exit lpuart_serial_exit(void)
+{
+	platform_driver_unregister(&lpuart_uart_driver);
+	uart_unregister_driver(&lpuart_reg);
+}
+
+module_init(lpuart_serial_init);
+module_exit(lpuart_serial_exit);
+
+MODULE_DESCRIPTION("Freescale LPUART serial driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 74c2bf7..df84fa2 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -226,4 +226,7 @@
 /* Rocketport EXPRESS/INFINITY */
 #define PORT_RP2	102
 
+/* Freescale lp-uart */
+#define PORT_LPUART	103
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
1.8.0




From herbert at gondor.apana.org.au  Thu May 16 03:01:44 2013
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Thu, 16 May 2013 15:01:44 +0800
Subject: [PATCH 15/39] crypto: ux500/cryp - Prepare clock before
 enabling it
In-Reply-To: <1368611522-9984-16-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-16-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516070144.GB6721@gondor.apana.org.au>

On Wed, May 15, 2013 at 10:51:38AM +0100, Lee Jones wrote:
> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
> 
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From herbert at gondor.apana.org.au  Thu May 16 03:01:57 2013
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Thu, 16 May 2013 15:01:57 +0800
Subject: [PATCH 16/39] crypto: ux500/cryp - Set DMA configuration
 though dma_slave_config()
In-Reply-To: <1368611522-9984-17-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-17-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516070157.GC6721@gondor.apana.org.au>

On Wed, May 15, 2013 at 10:51:39AM +0100, Lee Jones wrote:
> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
> 
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From herbert at gondor.apana.org.au  Thu May 16 03:02:17 2013
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Thu, 16 May 2013 15:02:17 +0800
Subject: [PATCH 18/39] crypto: ux500/[cryp|hash] - Show successful
 start-up in the bootlog
In-Reply-To: <1368611522-9984-19-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-19-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516070217.GD6721@gondor.apana.org.au>

On Wed, May 15, 2013 at 10:51:41AM +0100, Lee Jones wrote:
> The Cryp driver is currently silent and the Hash driver prints the
> name of its probe function unnecessarily. Let's just put a nice
> descriptive one-liner there instead.
> 
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From b35083 at freescale.com  Thu May 16 02:20:24 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:20:24 +0800
Subject: [PATCH v3 2/2] pinctrl: imx: add MVF600 support to imx pinctrl
 framework
In-Reply-To: <1368685224-17915-1-git-send-email-b35083@freescale.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
Message-ID: <1368685224-17915-2-git-send-email-b35083@freescale.com>

On some platforms such as MVF600, offset of mux and pad ctrl register
may be zero, and the mux_mode and config_val are in one 32-bit register.
This patch adds support to imx core pinctrl framework to handle these
cases.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  add ZERO_OFFSET_VALID flag to handle register offset from zero on mvf600.
  add SHARE_MUX_CONF_REG flag to handle mux mode and config value in one 32-bit
register in mvf600.

 drivers/pinctrl/pinctrl-imx.c | 53 ++++++++++++++++++++++++++++++++++---------
 drivers/pinctrl/pinctrl-imx.h |  4 ++++
 2 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4fcfff92..57a4eb0 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -221,13 +221,21 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 		pin_id = pins[i];
 		pin_reg = &info->pin_regs[pin_id];
 
-		if (!pin_reg->mux_reg) {
+		if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
 			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
 				info->pins[pin_id].name);
 			return -EINVAL;
 		}
 
-		writel(mux[i], ipctl->base + pin_reg->mux_reg);
+		if (info->flags & SHARE_MUX_CONF_REG) {
+			u32 reg;
+			reg = readl(ipctl->base + pin_reg->mux_reg);
+			reg &= ~(0x7 << 20);
+			reg |= (mux[i] << 20);
+			writel(reg, ipctl->base + pin_reg->mux_reg);
+		} else {
+			writel(mux[i], ipctl->base + pin_reg->mux_reg);
+		}
 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 			pin_reg->mux_reg, mux[i]);
 
@@ -287,7 +295,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 
-	if (!pin_reg->conf_reg) {
+	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
 		dev_err(info->dev, "Pin(%s) does not support config function\n",
 			info->pins[pin_id].name);
 		return -EINVAL;
@@ -295,6 +303,9 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
+	if (info->flags & SHARE_MUX_CONF_REG)
+		*config &= 0xffff;
+
 	return 0;
 }
 
@@ -305,7 +316,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 
-	if (!pin_reg->conf_reg) {
+	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
 		dev_err(info->dev, "Pin(%s) does not support config function\n",
 			info->pins[pin_id].name);
 		return -EINVAL;
@@ -314,7 +325,15 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 		info->pins[pin_id].name);
 
-	writel(config, ipctl->base + pin_reg->conf_reg);
+	if (info->flags & SHARE_MUX_CONF_REG) {
+		u32 reg;
+		reg = readl(ipctl->base + pin_reg->conf_reg);
+		reg &= ~0xffff;
+		reg |= config;
+		writel(reg, ipctl->base + pin_reg->conf_reg);
+	} else {
+		writel(config, ipctl->base + pin_reg->conf_reg);
+	}
 	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 		pin_reg->conf_reg, config);
 
@@ -381,19 +400,24 @@ static struct pinctrl_desc imx_pinctrl_desc = {
  * 1 u32 CONFIG, so 24 types in total for each pin.
  */
 #define FSL_PIN_SIZE 24
+#define SHARE_FSL_PIN_SIZE 20
 
 static int imx_pinctrl_parse_groups(struct device_node *np,
 				    struct imx_pin_group *grp,
 				    struct imx_pinctrl_soc_info *info,
 				    u32 index)
 {
-	int size;
+	int size, pin_size;
 	const __be32 *list;
 	int i;
 	u32 config;
 
 	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 
+	if (info->flags & SHARE_MUX_CONF_REG)
+		pin_size = SHARE_FSL_PIN_SIZE;
+	else
+		pin_size = FSL_PIN_SIZE;
 	/* Initialise group */
 	grp->name = np->name;
 
@@ -403,12 +427,12 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 	 */
 	list = of_get_property(np, "fsl,pins", &size);
 	/* we do not check return since it's safe node passed down */
-	if (!size || size % FSL_PIN_SIZE) {
+	if (!size || size % pin_size) {
 		dev_err(info->dev, "Invalid fsl,pins property\n");
 		return -EINVAL;
 	}
 
-	grp->npins = size / FSL_PIN_SIZE;
+	grp->npins = size / pin_size;
 	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 				GFP_KERNEL);
 	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
@@ -421,10 +445,17 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 				GFP_KERNEL);
 	for (i = 0; i < grp->npins; i++) {
 		u32 mux_reg = be32_to_cpu(*list++);
-		u32 conf_reg = be32_to_cpu(*list++);
-		unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
-		struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+		u32 conf_reg;
+		unsigned int pin_id;
+		struct imx_pin_reg *pin_reg;
 
+		if (info->flags & SHARE_MUX_CONF_REG)
+			conf_reg = mux_reg;
+		else
+			conf_reg = be32_to_cpu(*list++);
+
+		pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+		pin_reg = &info->pin_regs[pin_id];
 		grp->pins[i] = pin_id;
 		pin_reg->mux_reg = mux_reg;
 		pin_reg->conf_reg = conf_reg;
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
index 607ef54..bcedd99 100644
--- a/drivers/pinctrl/pinctrl-imx.h
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -74,8 +74,12 @@ struct imx_pinctrl_soc_info {
 	unsigned int ngroups;
 	struct imx_pmx_func *functions;
 	unsigned int nfunctions;
+	unsigned int flags;
 };
 
+#define ZERO_OFFSET_VALID	0x1
+#define SHARE_MUX_CONF_REG	0x2
+
 #define NO_MUX		0x0
 #define NO_PAD		0x0
 
-- 
1.8.0




From b35083 at freescale.com  Thu May 16 02:20:23 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 16 May 2013 14:20:23 +0800
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
Message-ID: <1368685224-17915-1-git-send-email-b35083@freescale.com>

Adds Freescale Vybrid Family MVF600 pin controller
driver to IMX iomuxc common driver framework.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  clean up code.
  update binding document according recommendation.

 .../bindings/pinctrl/fsl,mvf600-pinctrl.txt        |  41 +++
 drivers/pinctrl/Kconfig                            |   8 +
 drivers/pinctrl/Makefile                           |   1 +
 drivers/pinctrl/pinctrl-mvf600.c                   | 338 +++++++++++++++++++++
 4 files changed, 388 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvf600.c

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt
new file mode 100644
index 0000000..a4d04d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt
@@ -0,0 +1,41 @@
+Freescale Vybrid IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,mvf600-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = < PIN_FUNC_ID >, PIN_FUNC_ID is a pin
+  working on a specific function, CONFIG is the pad setting value such as
+  pull-up, speed, ode for this pin. Please refer to Vybrid MVF600 datasheet
+  for the valid pad config settings.
+
+CONFIG bits definition:
+PAD_CTL_SPEED_LOW		(1 << 12)
+PAD_CTL_SPEED_MED		(2 << 12)
+PAD_CTL_SPEED_HIGH		(3 << 12)
+PAD_CTL_SRE_FAST		(1 << 11)
+PAD_CTL_SRE_SLOW		(0 << 11)
+PAD_CTL_ODE			(1 << 10)
+PAD_CTL_HYS			(1 << 9)
+PAD_CTL_DSE_DISABLE		(0 << 6)
+PAD_CTL_DSE_150ohm		(1 << 6)
+PAD_CTL_DSE_75ohm		(2 << 6)
+PAD_CTL_DSE_50ohm		(3 << 6)
+PAD_CTL_DSE_37ohm		(4 << 6)
+PAD_CTL_DSE_30ohm		(5 << 6)
+PAD_CTL_DSE_25ohm		(6 << 6)
+PAD_CTL_DSE_20ohm		(7 << 6)
+PAD_CTL_PUS_100K_DOWN		(0 << 4)
+PAD_CTL_PUS_47K_UP		(1 << 4)
+PAD_CTL_PUS_100K_UP		(2 << 4)
+PAD_CTL_PUS_22K_UP		(3 << 4)
+PAD_CTL_PKE			(1 << 3)
+PAD_CTL_PUE			(1 << 2)
+PAD_CTL_OBE_ENABLE		(1 << 1)
+PAD_CTL_IBE_ENABLE		(1 << 0)
+PAD_CTL_OBE_IBE_ENABLE		(3 << 0)
+
+Please refer to mvf600-pinfunc.h in device tree source folder
+for all available PIN_FUNC_ID for Vybrid.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f66924..5cb3987 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -108,6 +108,14 @@ config PINCTRL_IMX6SL
 	help
 	  Say Y here to enable the imx6sl pinctrl driver
 
+config PINCTRL_MVF600
+	bool "Freescale Vybrid MVF600 pinctrl driver"
+	depends on OF
+	depends on SOC_MVF600
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the Freescale Vybrid MVF600 pinctrl driver
+
 config PINCTRL_LANTIQ
 	bool
 	depends on LANTIQ
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 34c4ae6..dfec292 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
 obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
+obj-$(CONFIG_PINCTRL_MVF600)	+= pinctrl-mvf600.o
 
 obj-$(CONFIG_PLAT_ORION)        += mvebu/
 obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
diff --git a/drivers/pinctrl/pinctrl-mvf600.c b/drivers/pinctrl/pinctrl-mvf600.c
new file mode 100644
index 0000000..6e2bcc0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvf600.c
@@ -0,0 +1,338 @@
+/*
+ * MVF600 pinctrl driver based on imx pinmux and pinconf core
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum mvf600_pads {
+	MVF600_PAD_PTA6 = 0,
+	MVF600_PAD_PTA8 = 1,
+	MVF600_PAD_PTA9 = 2,
+	MVF600_PAD_PTA10 = 3,
+	MVF600_PAD_PTA11 = 4,
+	MVF600_PAD_PTA12 = 5,
+	MVF600_PAD_PTA16 = 6,
+	MVF600_PAD_PTA17 = 7,
+	MVF600_PAD_PTA18 = 8,
+	MVF600_PAD_PTA19 = 9,
+	MVF600_PAD_PTA20 = 10,
+	MVF600_PAD_PTA21 = 11,
+	MVF600_PAD_PTA22 = 12,
+	MVF600_PAD_PTA23 = 13,
+	MVF600_PAD_PTA24 = 14,
+	MVF600_PAD_PTA25 = 15,
+	MVF600_PAD_PTA26 = 16,
+	MVF600_PAD_PTA27 = 17,
+	MVF600_PAD_PTA28 = 18,
+	MVF600_PAD_PTA29 = 19,
+	MVF600_PAD_PTA30 = 20,
+	MVF600_PAD_PTA31 = 21,
+	MVF600_PAD_PTB0 = 22,
+	MVF600_PAD_PTB1 = 23,
+	MVF600_PAD_PTB2 = 24,
+	MVF600_PAD_PTB3 = 25,
+	MVF600_PAD_PTB4 = 26,
+	MVF600_PAD_PTB5 = 27,
+	MVF600_PAD_PTB6 = 28,
+	MVF600_PAD_PTB7 = 29,
+	MVF600_PAD_PTB8 = 30,
+	MVF600_PAD_PTB9 = 31,
+	MVF600_PAD_PTB10 = 32,
+	MVF600_PAD_PTB11 = 33,
+	MVF600_PAD_PTB12 = 34,
+	MVF600_PAD_PTB13 = 35,
+	MVF600_PAD_PTB14 = 36,
+	MVF600_PAD_PTB15 = 37,
+	MVF600_PAD_PTB16 = 38,
+	MVF600_PAD_PTB17 = 39,
+	MVF600_PAD_PTB18 = 40,
+	MVF600_PAD_PTB19 = 41,
+	MVF600_PAD_PTB20 = 42,
+	MVF600_PAD_PTB21 = 43,
+	MVF600_PAD_PTB22 = 44,
+	MVF600_PAD_PTC0 = 45,
+	MVF600_PAD_PTC1 = 46,
+	MVF600_PAD_PTC2 = 47,
+	MVF600_PAD_PTC3 = 48,
+	MVF600_PAD_PTC4 = 49,
+	MVF600_PAD_PTC5 = 50,
+	MVF600_PAD_PTC6 = 51,
+	MVF600_PAD_PTC7 = 52,
+	MVF600_PAD_PTC8 = 53,
+	MVF600_PAD_PTC9 = 54,
+	MVF600_PAD_PTC10 = 55,
+	MVF600_PAD_PTC11 = 56,
+	MVF600_PAD_PTC12 = 57,
+	MVF600_PAD_PTC13 = 58,
+	MVF600_PAD_PTC14 = 59,
+	MVF600_PAD_PTC15 = 60,
+	MVF600_PAD_PTC16 = 61,
+	MVF600_PAD_PTC17 = 62,
+	MVF600_PAD_PTD31 = 63,
+	MVF600_PAD_PTD30 = 64,
+	MVF600_PAD_PTD29 = 65,
+	MVF600_PAD_PTD28 = 66,
+	MVF600_PAD_PTD27 = 67,
+	MVF600_PAD_PTD26 = 68,
+	MVF600_PAD_PTD25 = 69,
+	MVF600_PAD_PTD24 = 70,
+	MVF600_PAD_PTD23 = 71,
+	MVF600_PAD_PTD22 = 72,
+	MVF600_PAD_PTD21 = 73,
+	MVF600_PAD_PTD20 = 74,
+	MVF600_PAD_PTD19 = 75,
+	MVF600_PAD_PTD18 = 76,
+	MVF600_PAD_PTD17 = 77,
+	MVF600_PAD_PTD16 = 78,
+	MVF600_PAD_PTD0 = 79,
+	MVF600_PAD_PTD1 = 80,
+	MVF600_PAD_PTD2 = 81,
+	MVF600_PAD_PTD3 = 82,
+	MVF600_PAD_PTD4 = 83,
+	MVF600_PAD_PTD5 = 84,
+	MVF600_PAD_PTD6 = 85,
+	MVF600_PAD_PTD7 = 86,
+	MVF600_PAD_PTD8 = 87,
+	MVF600_PAD_PTD9 = 88,
+	MVF600_PAD_PTD10 = 89,
+	MVF600_PAD_PTD11 = 90,
+	MVF600_PAD_PTD12 = 91,
+	MVF600_PAD_PTD13 = 92,
+	MVF600_PAD_PTB23 = 93,
+	MVF600_PAD_PTB24 = 94,
+	MVF600_PAD_PTB25 = 95,
+	MVF600_PAD_PTB26 = 96,
+	MVF600_PAD_PTB27 = 97,
+	MVF600_PAD_PTB28 = 98,
+	MVF600_PAD_PTC26 = 99,
+	MVF600_PAD_PTC27 = 100,
+	MVF600_PAD_PTC28 = 101,
+	MVF600_PAD_PTC29 = 102,
+	MVF600_PAD_PTC30 = 103,
+	MVF600_PAD_PTC31 = 104,
+	MVF600_PAD_PTE0 = 105,
+	MVF600_PAD_PTE1 = 106,
+	MVF600_PAD_PTE2 = 107,
+	MVF600_PAD_PTE3 = 108,
+	MVF600_PAD_PTE4 = 109,
+	MVF600_PAD_PTE5 = 110,
+	MVF600_PAD_PTE6 = 111,
+	MVF600_PAD_PTE7 = 112,
+	MVF600_PAD_PTE8 = 113,
+	MVF600_PAD_PTE9 = 114,
+	MVF600_PAD_PTE10 = 115,
+	MVF600_PAD_PTE11 = 116,
+	MVF600_PAD_PTE12 = 117,
+	MVF600_PAD_PTE13 = 118,
+	MVF600_PAD_PTE14 = 119,
+	MVF600_PAD_PTE15 = 120,
+	MVF600_PAD_PTE16 = 121,
+	MVF600_PAD_PTE17 = 122,
+	MVF600_PAD_PTE18 = 123,
+	MVF600_PAD_PTE19 = 124,
+	MVF600_PAD_PTE20 = 125,
+	MVF600_PAD_PTE21 = 126,
+	MVF600_PAD_PTE22 = 127,
+	MVF600_PAD_PTE23 = 128,
+	MVF600_PAD_PTE24 = 129,
+	MVF600_PAD_PTE25 = 130,
+	MVF600_PAD_PTE26 = 131,
+	MVF600_PAD_PTE27 = 132,
+	MVF600_PAD_PTE28 = 133,
+	MVF600_PAD_PTA7 = 134,
+	};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc mvf600_pinctrl_pads[] = {
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA29),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA30),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA31),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB14),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB15),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC14),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC15),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD31),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD30),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD29),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTD13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTB28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC29),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC30),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTC31),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE0),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE1),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE2),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE3),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE4),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE5),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE6),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE7),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE8),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE9),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE10),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE11),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE12),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE13),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE14),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE15),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE16),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE17),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE18),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE19),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE20),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE21),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE22),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE23),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE24),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE25),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE26),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE27),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTE28),
+	IMX_PINCTRL_PIN(MVF600_PAD_PTA7),
+};
+
+static struct imx_pinctrl_soc_info mvf600_pinctrl_info = {
+	.pins = mvf600_pinctrl_pads,
+	.npins = ARRAY_SIZE(mvf600_pinctrl_pads),
+	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
+};
+
+static struct of_device_id mvf600_pinctrl_of_match[] = {
+	{ .compatible = "fsl,mvf600-iomuxc", },
+	{ /* sentinel */ }
+};
+
+static int mvf600_pinctrl_probe(struct platform_device *pdev)
+{
+	return imx_pinctrl_probe(pdev, &mvf600_pinctrl_info);
+}
+
+static struct platform_driver mvf600_pinctrl_driver = {
+	.driver = {
+		.name = "mvf600-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(mvf600_pinctrl_of_match),
+	},
+	.probe = mvf600_pinctrl_probe,
+	.remove = imx_pinctrl_remove,
+};
+
+static int __init mvf600_pinctrl_init(void)
+{
+	return platform_driver_register(&mvf600_pinctrl_driver);
+}
+arch_initcall(mvf600_pinctrl_init);
+
+static void __exit mvf600_pinctrl_exit(void)
+{
+	platform_driver_unregister(&mvf600_pinctrl_driver);
+}
+module_exit(mvf600_pinctrl_exit);
+
+MODULE_DESCRIPTION("Freescale MVF600 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.0




From lee.jones at linaro.org  Thu May 16 03:06:38 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 08:06:38 +0100
Subject: [PATCH 31/39] dmaengine: ste_dma40: Replace ST-E's home-brew DMA
 direction defs with generic ones
In-Reply-To: <20130516051701.GG27639@intel.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-32-git-send-email-lee.jones@linaro.org>
 <20130516051701.GG27639@intel.com>
Message-ID: <20130516070638.GC3269@gmail.com>

On Thu, 16 May 2013, Vinod Koul wrote:

> On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > duplicating such things.
> > 
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> Nice :)

:)

> 1) I dont see the STE macro getting removed, why do we need it

They are removed later in the set, once their use has been removed
from platform code and all the other drivers.

> 2) last i checked the direction values had a bit idfference b/w what you are
> using and what dmaengine defines, so hopefully that is taken care of..

Yes, no problem.

<place Ack here> ;)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From vinod.koul at intel.com  Thu May 16 02:32:44 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:02:44 +0530
Subject: [PATCH 34/39] dmaengine: ste_dma40: Convert data_width from
 register bit format to value
In-Reply-To: <1368611522-9984-35-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-35-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516063244.GA14863@intel.com>

On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> When a DMA client requests and configures a DMA channel, it requests
> data_width in Bytes. The DMA40 driver then swiftly converts it over to
> the necessary register bit value. Unfortunately, for any subsequent
> calculations we have to shift '1' by the bit pattern (1 << data_width)
> times to make any sense of it.
> 
> This patch flips the semantics on its head and only converts the value
> to its respective register bit pattern when writing to registers. This
> way we can use the true data_width (in Bytes) value.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
  
> @@ -2804,14 +2781,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  		src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
>  	}
>  
> +	/* Only valid widths are; 1, 2, 4 and 8. */
> +	if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> +	    src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
> +	    dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> +	    dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
> +	    ((src_addr_width > 1) && (src_addr_width & 1)) ||
> +	    ((dst_addr_width > 1) && (dst_addr_width & 1)))
> +		return -EINVAL;
how about a simple macro to check above..

> +
> +	cfg->src_info.data_width = src_addr_width;
> +	cfg->dst_info.data_width = dst_addr_width;
> +
>  	ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
> -					  src_addr_width,
>  					  src_maxburst);
>  	if (ret)
>  		return ret;
>  
>  	ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
> -					  dst_addr_width,
>  					  dst_maxburst);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index 5ddd724..a035dfe 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -10,6 +10,18 @@
>  
>  #include "ste_dma40_ll.h"
>  
> +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> +{
> +	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> +		return STEDMA40_ESIZE_8_BIT;
> +	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> +		return STEDMA40_ESIZE_16_BIT;
> +	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> +		return STEDMA40_ESIZE_64_BIT;
> +	else
> +		return STEDMA40_ESIZE_32_BIT;
> +}
> +
Switch looks better for this and how about
	return fls(width);

as your defines are 0...3 and dmaengine define 1,2,..8 for same thing
then you can also get rid of STEDMA40_XXX_WIDTH macros!


> @@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
>  	STEDMA40_FLOW_CTRL,
>  };
>  
> -enum stedma40_periph_data_width {
> -	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
> -	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
> -	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
> -	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
> -};
nice

--
~Vinod


From vinod.koul at intel.com  Thu May 16 02:34:14 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:04:14 +0530
Subject: [PATCH 38/39] dmaengine: ste_dma40: Fetch the number of
 physical channels from DT
In-Reply-To: <1368611522-9984-39-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-39-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516063414.GB14863@intel.com>

On Wed, May 15, 2013 at 10:52:01AM +0100, Lee Jones wrote:
> Some platforms insist on obscure physical channel availability. This
> information is currently passed though platform data in internal BSP
> kernels. Once those platforms land, they'll need to configure them
> appropriately, so we may as well add the infrastructure.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
Acked-by: Vinod Koul <vinod.koul at intel.com>

>  drivers/dma/ste_dma40.c |    7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index ae462d3..4e528dd 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -3482,7 +3482,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
>  			       struct device_node *np)
>  {
>  	struct stedma40_platform_data *pdata;
> -	int num_memcpy = 0;
> +	int num_phy = 0, num_memcpy = 0;
>  	const const __be32 *list;
>  
>  	pdata = devm_kzalloc(&pdev->dev,
> @@ -3491,6 +3491,11 @@ static int __init d40_of_probe(struct platform_device *pdev,
>  	if (!pdata)
>  		return -ENOMEM;
>  
> +	/* If absent this value will be obtained from h/w. */
> +	of_property_read_u32(np, "dma-channels", &num_phy);
> +	if (num_phy > 0)
> +		pdata->num_of_phy_chans = num_phy;
> +
>  	list = of_get_property(np, "memcpy-channels", &num_memcpy);
>  	num_memcpy /= sizeof(*list);
>  
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 02:35:13 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:05:13 +0530
Subject: [PATCH 01/39] dmaengine: ste_dma40: Separate Logical Global
 Interrupt Mask (GIM) unmasking
In-Reply-To: <CACRpkdZJp-WRGNgzwqERVBtb_WxQGybmMjnnLTAoX66qECNh7g@mail.gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-2-git-send-email-lee.jones@linaro.org>
 <CACRpkdZJp-WRGNgzwqERVBtb_WxQGybmMjnnLTAoX66qECNh7g@mail.gmail.com>
Message-ID: <20130516063513.GC14863@intel.com>

On Wed, May 15, 2013 at 06:29:51PM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > During the initial setup of a logical channel, it is necessary to unmask
> > the GIM in order to receive generated terminal count and error interrupts.
> > We're separating out this required code so it will be possible to move
> > the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> > into the runtime_config() routine.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Tentatively applied to my ux500-dma40 branch.
> 
> This lacks an ACK from Vinod...
Acked-by: Vinod Koul <vinod.koul at intel.com>
> 
> I cannot get any of this stack of patches up to ARM SoC
> before I have Vinod's ACK on all hitting drivers/dma/*
Wip ... :)

> 
> Yours,
> Linus Walleij


From vinod.koul at intel.com  Thu May 16 02:35:46 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:05:46 +0530
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516063546.GD14863@intel.com>

On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
> All configuration left in d40_phy_cfg() is runtime configurable and
> there is already a call into it from d40_runtime_config(), so let's
> rely on that.
> 
> Acked-by: Vinod Koul <vnod.koul at intel.com>
That needs up update!

> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/dma/ste_dma40.c    |   14 +++---
>  drivers/dma/ste_dma40_ll.c |  101 +++++++++++++++++++++-----------------------
>  drivers/dma/ste_dma40_ll.h |    3 +-
>  3 files changed, 58 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 759293e..b7fe46b 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -2043,6 +2043,14 @@ static int d40_config_memcpy(struct d40_chan *d40c)
>  	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
>  		   dma_has_cap(DMA_SLAVE, cap)) {
>  		d40c->dma_cfg = dma40_memcpy_conf_phy;
> +
> +		/* Generate interrrupt at end of transfer or relink. */
> +		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
> +
> +		/* Generate interrupt on error. */
> +		d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> +		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> +
>  	} else {
>  		chan_err(d40c, "No memcpy\n");
>  		return -EINVAL;
> @@ -2496,9 +2504,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
>  	}
>  
>  	pm_runtime_get_sync(d40c->base->dev);
> -	/* Fill in basic CFG register values */
> -	d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
> -		    &d40c->dst_def_cfg, chan_is_logical(d40c));
>  
>  	d40_set_prio_realtime(d40c);
>  
> @@ -2862,8 +2867,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  	if (chan_is_logical(d40c))
>  		d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
>  	else
> -		d40_phy_cfg(cfg, &d40c->src_def_cfg,
> -			    &d40c->dst_def_cfg, false);
> +		d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
>  
>  	/* These settings will take precedence later */
>  	d40c->runtime_addr = config_addr;
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index 435a223..ab5a2a7 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -50,63 +50,58 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
>  
>  }
>  
> -/* Sets up SRC and DST CFG register for both logical and physical channels */
> -void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
> -		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
> +void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
>  {
>  	u32 src = 0;
>  	u32 dst = 0;
>  
> -	if (!is_log) {
> -		/* Physical channel */
> -		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
> -		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> -			/* Set master port to 1 */
> -			src |= 1 << D40_SREG_CFG_MST_POS;
> -			src |= D40_TYPE_TO_EVENT(cfg->dev_type);
> -
> -			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> -				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
> -			else
> -				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
> -		}
> -		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
> -		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> -			/* Set master port to 1 */
> -			dst |= 1 << D40_SREG_CFG_MST_POS;
> -			dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
> -
> -			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> -				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
> -			else
> -				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
> -		}
> -		/* Interrupt on end of transfer for destination */
> -		dst |= 1 << D40_SREG_CFG_TIM_POS;
> -
> -		/* Generate interrupt on error */
> -		src |= 1 << D40_SREG_CFG_EIM_POS;
> -		dst |= 1 << D40_SREG_CFG_EIM_POS;
> -
> -		/* PSIZE */
> -		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
> -			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> -			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
> -		}
> -		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
> -			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> -			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
> -		}
> -
> -		/* Element size */
> -		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
> -		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
> -
> -		/* Set the priority bit to high for the physical channel */
> -		if (cfg->high_priority) {
> -			src |= 1 << D40_SREG_CFG_PRI_POS;
> -			dst |= 1 << D40_SREG_CFG_PRI_POS;
> -		}
> +	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
> +	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> +		/* Set master port to 1 */
> +		src |= 1 << D40_SREG_CFG_MST_POS;
> +		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
> +
> +		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> +			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
> +		else
> +			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
> +	}
> +	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
> +	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> +		/* Set master port to 1 */
> +		dst |= 1 << D40_SREG_CFG_MST_POS;
> +		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
> +
> +		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> +			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
> +		else
> +			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
> +	}
> +	/* Interrupt on end of transfer for destination */
> +	dst |= 1 << D40_SREG_CFG_TIM_POS;
> +
> +	/* Generate interrupt on error */
> +	src |= 1 << D40_SREG_CFG_EIM_POS;
> +	dst |= 1 << D40_SREG_CFG_EIM_POS;
> +
> +	/* PSIZE */
> +	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
> +		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> +		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
> +	}
> +	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
> +		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> +		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
> +	}
> +
> +	/* Element size */
> +	src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
> +	dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
> +
> +	/* Set the priority bit to high for the physical channel */
> +	if (cfg->high_priority) {
> +		src |= 1 << D40_SREG_CFG_PRI_POS;
> +		dst |= 1 << D40_SREG_CFG_PRI_POS;
>  	}
>  
>  	if (cfg->src_info.big_endian)
> diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
> index fdde8ef..1b47312 100644
> --- a/drivers/dma/ste_dma40_ll.h
> +++ b/drivers/dma/ste_dma40_ll.h
> @@ -432,8 +432,7 @@ enum d40_lli_flags {
>  
>  void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
>  		 u32 *src_cfg,
> -		 u32 *dst_cfg,
> -		 bool is_log);
> +		 u32 *dst_cfg);
>  
>  void d40_log_cfg(struct stedma40_chan_cfg *cfg,
>  		 u32 *lcsp1,
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 02:36:40 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:06:40 +0530
Subject: [PATCH 03/39] dmaengine: ste_dma40: Don't configure runtime
 configurable setup during allocate
In-Reply-To: <1368611522-9984-4-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-4-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516063640.GE14863@intel.com>

On Wed, May 15, 2013 at 10:51:26AM +0100, Lee Jones wrote:
> Using the dmaengine API, allocating and configuring a channel are two
> separate actions. Here we're removing logical channel configuration from
> the channel allocating routines.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
>  drivers/dma/ste_dma40.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index b7fe46b..ba84df8 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -2040,6 +2040,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
>  		d40c->dma_cfg = dma40_memcpy_conf_log;
>  		d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
>  
> +		d40_log_cfg(&d40c->dma_cfg,
> +			    &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> +
>  	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
>  		   dma_has_cap(DMA_SLAVE, cap)) {
>  		d40c->dma_cfg = dma40_memcpy_conf_phy;
> @@ -2508,9 +2511,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
>  	d40_set_prio_realtime(d40c);
>  
>  	if (chan_is_logical(d40c)) {
> -		d40_log_cfg(&d40c->dma_cfg,
> -			    &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> -
>  		if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
>  			d40c->lcpa = d40c->base->lcpa_base +
>  				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
> -- 
> 1.7.10.4
> 


From david.lanzendoerfer at o2s.ch  Thu May 16 03:15:37 2013
From: david.lanzendoerfer at o2s.ch (David =?iso-8859-1?Q?Lanzend=F6rfer?=)
Date: Thu, 16 May 2013 09:15:37 +0200
Subject: Naming convention DSI + device tree
In-Reply-To: <51940C22.4050802@wwwdotorg.org>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org>
Message-ID: <20130516071537.GA13573@mail.o2s.ch>

On Wed, May 15, 2013 at 04:28:50PM -0600, Stephen Warren wrote:
> On 05/14/2013 12:17 PM, David Lanzend?rfer wrote:
> > Hello
> > I have the following issue:
> > In order to make the DSI controller react at all,
> Hmm. In the upstream kernel, we don't even have a DSI driver at all for
> Tegra, so control over the panel itself is likely the least of your
> worries for now.
Is there a patch set pending for merge into upstream which will provide
this support? And if yes, where can I find these pending patches?
I'd like to build up my code based on already existing work which is
expected to be in upstream at some later point of time.

> > I need to pass him a certain combination of pin states.
> > Until now within the code of the original android kernel which was using board files this has just been
> > done by doing bit banging.
> > 
> > namely:
> > 	gpio_set_value(tf201_lvds_shutdown, 1);
> > ...
> > Now with a device tree comes the question: Where should I put this?
> Likely, you will need to create a DT binding that represents the
> particular panel model that you have, and make the Tegra display
> controller node refer to that panel node. The panel node would need
> properties to describe the various GPIOs used to control the panel.
> Then, you'd want to write a panel-specific driver that handles that
> device tree node.
That was my thought too.
Where should I put this panel-specific driver?

> All of this will likely need to be integrated with the upcoming Common
> Display Framework.
Is this upcoming CDF included within your "linux-next_common" branch?

best regards
David
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From vinod.koul at intel.com  Thu May 16 02:40:37 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:10:37 +0530
Subject: [PATCH 07/39] dmaengine: ste_dma40: Only use addresses passed
 as configuration information
In-Reply-To: <1368611522-9984-8-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-8-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516064036.GF14863@intel.com>

On Wed, May 15, 2013 at 10:51:30AM +0100, Lee Jones wrote:
> Addresses are passed in from the client's driver via the invocation of
> dmaengine_slave_config(), so there's no need to fetch them from platform
> data too, hardwired or otherwise. This is a great step forward, as it
> elevates a large burden from platform data in the way of a look-up
> table.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
Good code size reduction, always a good template for code improvements

Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
>  drivers/dma/ste_dma40.c |   51 ++++++++++-------------------------------------
>  1 file changed, 11 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index ba84df8..57a127e 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -1774,22 +1774,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
>  		res = -EINVAL;
>  	}
>  
> -	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
> -	    d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
> -	    d40c->runtime_addr == 0) {
> -		chan_err(d40c, "Invalid TX channel address (%d)\n",
> -			 conf->dev_type);
> -		res = -EINVAL;
> -	}
> -
> -	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
> -	    d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
> -	    d40c->runtime_addr == 0) {
> -		chan_err(d40c, "Invalid RX channel address (%d)\n",
> -			 conf->dev_type);
> -		res = -EINVAL;
> -	}
> -
>  	if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
>  		/*
>  		 * DMAC HW supports it. Will be added to this driver,
> @@ -2327,14 +2311,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
>  	if (sg_next(&sg_src[sg_len - 1]) == sg_src)
>  		desc->cyclic = true;
>  
> -	if (direction != DMA_TRANS_NONE) {
> -		dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
> -
> -		if (direction == DMA_DEV_TO_MEM)
> -			src_dev_addr = dev_addr;
> -		else if (direction == DMA_MEM_TO_DEV)
> -			dst_dev_addr = dev_addr;
> -	}
> +	if (direction == DMA_DEV_TO_MEM)
> +		src_dev_addr = chan->runtime_addr;
> +	else if (direction == DMA_MEM_TO_DEV)
> +		dst_dev_addr = chan->runtime_addr;
>  
>  	if (chan_is_logical(chan))
>  		ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
> @@ -2782,15 +2762,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  	dst_maxburst = config->dst_maxburst;
>  
>  	if (config->direction == DMA_DEV_TO_MEM) {
> -		dma_addr_t dev_addr_rx =
> -			d40c->base->plat_data->dev_rx[cfg->dev_type];
> -
>  		config_addr = config->src_addr;
> -		if (dev_addr_rx)
> -			dev_dbg(d40c->base->dev,
> -				"channel has a pre-wired RX address %08x "
> -				"overriding with %08x\n",
> -				dev_addr_rx, config_addr);
> +
>  		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
>  			dev_dbg(d40c->base->dev,
>  				"channel was not configured for peripheral "
> @@ -2805,15 +2778,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  			dst_maxburst = src_maxburst;
>  
>  	} else if (config->direction == DMA_MEM_TO_DEV) {
> -		dma_addr_t dev_addr_tx =
> -			d40c->base->plat_data->dev_tx[cfg->dev_type];
> -
>  		config_addr = config->dst_addr;
> -		if (dev_addr_tx)
> -			dev_dbg(d40c->base->dev,
> -				"channel has a pre-wired TX address %08x "
> -				"overriding with %08x\n",
> -				dev_addr_tx, config_addr);
> +
>  		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
>  			dev_dbg(d40c->base->dev,
>  				"channel was not configured for memory "
> @@ -2833,6 +2799,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
>  		return -EINVAL;
>  	}
>  
> +	if (config_addr <= 0) {
> +		dev_err(d40c->base->dev, "no address supplied\n");
> +		return -EINVAL;
> +	}
> +
>  	if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
>  		dev_err(d40c->base->dev,
>  			"src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 02:41:09 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:11:09 +0530
Subject: [PATCH 08/39] dmaengine: ste_dma40: Remove redundant address
 fetching function
In-Reply-To: <1368611522-9984-9-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-9-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516064109.GG14863@intel.com>

On Wed, May 15, 2013 at 10:51:31AM +0100, Lee Jones wrote:
> Addresses are now stored in local data structures and are easy to
> obtain, thus a specialist function used to fetch them is now surplus
> to requirement.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
>  drivers/dma/ste_dma40.c |   18 ------------------
>  1 file changed, 18 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 57a127e..6ed7757 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -2267,24 +2267,6 @@ err:
>  	return NULL;
>  }
>  
> -static dma_addr_t
> -d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
> -{
> -	struct stedma40_platform_data *plat = chan->base->plat_data;
> -	struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
> -	dma_addr_t addr = 0;
> -
> -	if (chan->runtime_addr)
> -		return chan->runtime_addr;
> -
> -	if (direction == DMA_DEV_TO_MEM)
> -		addr = plat->dev_rx[cfg->dev_type];
> -	else if (direction == DMA_MEM_TO_DEV)
> -		addr = plat->dev_tx[cfg->dev_type];
> -
> -	return addr;
> -}
> -
>  static struct dma_async_tx_descriptor *
>  d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
>  	    struct scatterlist *sg_dst, unsigned int sg_len,
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 02:42:17 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:12:17 +0530
Subject: [PATCH 10/39] dmaengine: ste_dma40: Correct copy/paste error
In-Reply-To: <1368611522-9984-11-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-11-git-send-email-lee.jones@linaro.org>
Message-ID: <20130516064217.GH14863@intel.com>

On Wed, May 15, 2013 at 10:51:33AM +0100, Lee Jones wrote:
> 'struct stedma40_half_channel_info's header comment says that it's
> called 'struct stedma40_chan_cfg'. Let's straighten that out.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
>  include/linux/platform_data/dma-ste-dma40.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
> index af0064e..288dc24 100644
> --- a/include/linux/platform_data/dma-ste-dma40.h
> +++ b/include/linux/platform_data/dma-ste-dma40.h
> @@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
>  
>  
>  /**
> - * struct stedma40_chan_cfg - dst/src channel configuration
> + * struct stedma40_half_channel_info - dst/src channel configuration
>   *
>   * @big_endian: true if the src/dst should be read as big endian
>   * @data_width: Data width of the src/dst hardware
> -- 
> 1.7.10.4
> 


From vinod.koul at intel.com  Thu May 16 02:43:42 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 12:13:42 +0530
Subject: [PATCH 31/39] dmaengine: ste_dma40: Replace ST-E's home-brew
 DMA direction defs with generic ones
In-Reply-To: <20130516070638.GC3269@gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-32-git-send-email-lee.jones@linaro.org>
 <20130516051701.GG27639@intel.com>
 <20130516070638.GC3269@gmail.com>
Message-ID: <20130516064342.GI14863@intel.com>

On Thu, May 16, 2013 at 08:06:38AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
> 
> > On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> > > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > > duplicating such things.
> > > 
> > > Cc: Vinod Koul <vinod.koul at intel.com>
> > > Cc: Dan Williams <djbw at fb.com>
> > > Cc: Per Forlin <per.forlin at stericsson.com>
> > > Cc: Rabin Vincent <rabin at rab.in>
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > Nice :)
> 
> :)
> 
> > 1) I dont see the STE macro getting removed, why do we need it
> 
> They are removed later in the set, once their use has been removed
> from platform code and all the other drivers.
> 
> > 2) last i checked the direction values had a bit idfference b/w what you are
> > using and what dmaengine defines, so hopefully that is taken care of..
> 
> Yes, no problem.
> 
> <place Ack here> ;)
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
> 
> -- 
> Lee Jones
> Linaro ST-Ericsson Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog


From b-cousson at ti.com  Thu May 16 03:20:51 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Thu, 16 May 2013 09:20:51 +0200
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <5193B9AA.7020507@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com>
Message-ID: <519488D3.5070003@ti.com>

Hi Eduardo,

On 05/15/2013 06:36 PM, Eduardo Valentin wrote:
> On 15-05-2013 11:23, Benoit Cousson wrote:
>> Hi Eduardo,
>>
>> On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
>>> Include bandgap devices for OMAP4460 devices.
>>>
>>> Cc: "Beno?t Cousson" <b-cousson at ti.com>
>>> Cc: Tony Lindgren <tony at atomide.com>
>>> Cc: Russell King <linux at arm.linux.org.uk>
>>> Cc: linux-omap at vger.kernel.org
>>> Cc: devicetree-discuss at lists.ozlabs.org
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: linux-kernel at vger.kernel.org
>>> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
>>> ---
>>>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
>>>  1 file changed, 9 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
>>> index 2cf227c..e5bfbfe 100644
>>> --- a/arch/arm/boot/dts/omap4460.dtsi
>>> +++ b/arch/arm/boot/dts/omap4460.dtsi
>>> @@ -29,4 +29,13 @@
>>>  			     <0 55 0x4>;
>>>  		ti,hwmods = "debugss";
>>>  	};
>>> +
>>> +	bandgap {
>>> +		reg = <0x4a002260 0x4
>>> +			0x4a00232C 0x4
>>> +			0x4a002378 0x18>;
>>> +		compatible = "ti,omap4460-bandgap";
>>> +		interrupts = <0 126 4>; /* talert */
>>> +		ti,tshut-gpio = <86>;
> 
> 
> 
>>
>> Why do you need a custom attribute for GPIO? Cannot you use the standard
>> one?
> 
> I believe it was by your suggestion :-), during the first attempts to
> send this driver. But could not find the thread link :-( sorry.

Ooops :-) I do not remember that... maybe it was long time ago, before
we had any decent binding available for GPIO and IRQ...

> I guess the reasoning to mark it as a ti specific is because it will be
> used as IRQ line to treat thermal shutdown (in SW).

Mmm, ok, so in that case, it is not even a gpio, but an interrupt entry
that is needed like that:

	interrupt-parent = <&gpio3>;
	interrupts = <22>; /* gpio line 86 */

Except that we already have an IRQ line connected to GIC for the
Talert... I'm not sure we can have 2 different IRQ controllers for one
device :-(

We need to check.

Regards,
Benoit


>> Where is the gpio controller phandle?
>>
>> Usually it looks like this:
>>
>> 	gpios = <&gpio1 8 0>;
>>
>>
>> Regards,
>> Benoit
>>
>>
>>
> 
> 



From lee.jones at linaro.org  Thu May 16 03:25:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 08:25:57 +0100
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <20130516063546.GD14863@intel.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
 <20130516063546.GD14863@intel.com>
Message-ID: <20130516072557.GD3269@gmail.com>

On Thu, 16 May 2013, Vinod Koul wrote:

> On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
> > All configuration left in d40_phy_cfg() is runtime configurable and
> > there is already a call into it from d40_runtime_config(), so let's
> > rely on that.
> > 
> > Acked-by: Vinod Koul <vnod.koul at intel.com>
> That needs up update!

Ah, where did I get that from that?

Was that my mistake, or was this in the MAINTAINERS file?

> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  drivers/dma/ste_dma40.c    |   14 +++---
> >  drivers/dma/ste_dma40_ll.c |  101 +++++++++++++++++++++-----------------------
> >  drivers/dma/ste_dma40_ll.h |    3 +-
> >  3 files changed, 58 insertions(+), 60 deletions(-)
> > 
> > diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> > index 759293e..b7fe46b 100644
> > --- a/drivers/dma/ste_dma40.c
> > +++ b/drivers/dma/ste_dma40.c
> > @@ -2043,6 +2043,14 @@ static int d40_config_memcpy(struct d40_chan *d40c)
> >  	} else if (dma_has_cap(DMA_MEMCPY, cap) &&
> >  		   dma_has_cap(DMA_SLAVE, cap)) {
> >  		d40c->dma_cfg = dma40_memcpy_conf_phy;
> > +
> > +		/* Generate interrrupt at end of transfer or relink. */
> > +		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
> > +
> > +		/* Generate interrupt on error. */
> > +		d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> > +		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
> > +
> >  	} else {
> >  		chan_err(d40c, "No memcpy\n");
> >  		return -EINVAL;
> > @@ -2496,9 +2504,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
> >  	}
> >  
> >  	pm_runtime_get_sync(d40c->base->dev);
> > -	/* Fill in basic CFG register values */
> > -	d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
> > -		    &d40c->dst_def_cfg, chan_is_logical(d40c));
> >  
> >  	d40_set_prio_realtime(d40c);
> >  
> > @@ -2862,8 +2867,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> >  	if (chan_is_logical(d40c))
> >  		d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> >  	else
> > -		d40_phy_cfg(cfg, &d40c->src_def_cfg,
> > -			    &d40c->dst_def_cfg, false);
> > +		d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
> >  
> >  	/* These settings will take precedence later */
> >  	d40c->runtime_addr = config_addr;
> > diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> > index 435a223..ab5a2a7 100644
> > --- a/drivers/dma/ste_dma40_ll.c
> > +++ b/drivers/dma/ste_dma40_ll.c
> > @@ -50,63 +50,58 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
> >  
> >  }
> >  
> > -/* Sets up SRC and DST CFG register for both logical and physical channels */
> > -void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
> > -		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
> > +void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
> >  {
> >  	u32 src = 0;
> >  	u32 dst = 0;
> >  
> > -	if (!is_log) {
> > -		/* Physical channel */
> > -		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
> > -		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> > -			/* Set master port to 1 */
> > -			src |= 1 << D40_SREG_CFG_MST_POS;
> > -			src |= D40_TYPE_TO_EVENT(cfg->dev_type);
> > -
> > -			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> > -				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
> > -			else
> > -				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
> > -		}
> > -		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
> > -		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> > -			/* Set master port to 1 */
> > -			dst |= 1 << D40_SREG_CFG_MST_POS;
> > -			dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
> > -
> > -			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> > -				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
> > -			else
> > -				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
> > -		}
> > -		/* Interrupt on end of transfer for destination */
> > -		dst |= 1 << D40_SREG_CFG_TIM_POS;
> > -
> > -		/* Generate interrupt on error */
> > -		src |= 1 << D40_SREG_CFG_EIM_POS;
> > -		dst |= 1 << D40_SREG_CFG_EIM_POS;
> > -
> > -		/* PSIZE */
> > -		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
> > -			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> > -			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
> > -		}
> > -		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
> > -			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> > -			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
> > -		}
> > -
> > -		/* Element size */
> > -		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
> > -		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
> > -
> > -		/* Set the priority bit to high for the physical channel */
> > -		if (cfg->high_priority) {
> > -			src |= 1 << D40_SREG_CFG_PRI_POS;
> > -			dst |= 1 << D40_SREG_CFG_PRI_POS;
> > -		}
> > +	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
> > +	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> > +		/* Set master port to 1 */
> > +		src |= 1 << D40_SREG_CFG_MST_POS;
> > +		src |= D40_TYPE_TO_EVENT(cfg->dev_type);
> > +
> > +		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> > +			src |= 1 << D40_SREG_CFG_PHY_TM_POS;
> > +		else
> > +			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
> > +	}
> > +	if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
> > +	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> > +		/* Set master port to 1 */
> > +		dst |= 1 << D40_SREG_CFG_MST_POS;
> > +		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
> > +
> > +		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> > +			dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
> > +		else
> > +			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
> > +	}
> > +	/* Interrupt on end of transfer for destination */
> > +	dst |= 1 << D40_SREG_CFG_TIM_POS;
> > +
> > +	/* Generate interrupt on error */
> > +	src |= 1 << D40_SREG_CFG_EIM_POS;
> > +	dst |= 1 << D40_SREG_CFG_EIM_POS;
> > +
> > +	/* PSIZE */
> > +	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
> > +		src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> > +		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
> > +	}
> > +	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
> > +		dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> > +		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
> > +	}
> > +
> > +	/* Element size */
> > +	src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
> > +	dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
> > +
> > +	/* Set the priority bit to high for the physical channel */
> > +	if (cfg->high_priority) {
> > +		src |= 1 << D40_SREG_CFG_PRI_POS;
> > +		dst |= 1 << D40_SREG_CFG_PRI_POS;
> >  	}
> >  
> >  	if (cfg->src_info.big_endian)
> > diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
> > index fdde8ef..1b47312 100644
> > --- a/drivers/dma/ste_dma40_ll.h
> > +++ b/drivers/dma/ste_dma40_ll.h
> > @@ -432,8 +432,7 @@ enum d40_lli_flags {
> >  
> >  void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
> >  		 u32 *src_cfg,
> > -		 u32 *dst_cfg,
> > -		 bool is_log);
> > +		 u32 *dst_cfg);
> >  
> >  void d40_log_cfg(struct stedma40_chan_cfg *cfg,
> >  		 u32 *lcsp1,

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Thu May 16 03:26:34 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 08:26:34 +0100
Subject: [PATCH 01/39] dmaengine: ste_dma40: Separate Logical Global
 Interrupt Mask (GIM) unmasking
In-Reply-To: <20130516063513.GC14863@intel.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-2-git-send-email-lee.jones@linaro.org>
 <CACRpkdZJp-WRGNgzwqERVBtb_WxQGybmMjnnLTAoX66qECNh7g@mail.gmail.com>
 <20130516063513.GC14863@intel.com>
Message-ID: <20130516072634.GE3269@gmail.com>

On Thu, 16 May 2013, Vinod Koul wrote:

> On Wed, May 15, 2013 at 06:29:51PM +0200, Linus Walleij wrote:
> > On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> > 
> > > During the initial setup of a logical channel, it is necessary to unmask
> > > the GIM in order to receive generated terminal count and error interrupts.
> > > We're separating out this required code so it will be possible to move
> > > the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> > > into the runtime_config() routine.
> > >
> > > Cc: Vinod Koul <vinod.koul at intel.com>
> > > Cc: Dan Williams <djbw at fb.com>
> > > Cc: Per Forlin <per.forlin at stericsson.com>
> > > Cc: Rabin Vincent <rabin at rab.in>
> > > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > 
> > Tentatively applied to my ux500-dma40 branch.
> > 
> > This lacks an ACK from Vinod...
> Acked-by: Vinod Koul <vinod.koul at intel.com>
> > 
> > I cannot get any of this stack of patches up to ARM SoC
> > before I have Vinod's ACK on all hitting drivers/dma/*
> Wip ... :)

Nice! :)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Thu May 16 03:35:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 08:35:53 +0100
Subject: [PATCH 34/39] dmaengine: ste_dma40: Convert data_width from
 register bit format to value
In-Reply-To: <20130516063244.GA14863@intel.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-35-git-send-email-lee.jones@linaro.org>
 <20130516063244.GA14863@intel.com>
Message-ID: <20130516073553.GF3269@gmail.com>

On Thu, 16 May 2013, Vinod Koul wrote:

> On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> > When a DMA client requests and configures a DMA channel, it requests
> > data_width in Bytes. The DMA40 driver then swiftly converts it over to
> > the necessary register bit value. Unfortunately, for any subsequent
> > calculations we have to shift '1' by the bit pattern (1 << data_width)
> > times to make any sense of it.
> > 
> > This patch flips the semantics on its head and only converts the value
> > to its respective register bit pattern when writing to registers. This
> > way we can use the true data_width (in Bytes) value.
> > 
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
>   
> > @@ -2804,14 +2781,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> >  		src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
> >  	}
> >  
> > +	/* Only valid widths are; 1, 2, 4 and 8. */
> > +	if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> > +	    src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
> > +	    dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> > +	    dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
> > +	    ((src_addr_width > 1) && (src_addr_width & 1)) ||
> > +	    ((dst_addr_width > 1) && (dst_addr_width & 1)))
> > +		return -EINVAL;
> how about a simple macro to check above..

I thought about it, but as this code appears only once, I considered
it to be unnecessary abstraction.

> > +
> > +	cfg->src_info.data_width = src_addr_width;
> > +	cfg->dst_info.data_width = dst_addr_width;
> > +
> >  	ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
> > -					  src_addr_width,
> >  					  src_maxburst);
> >  	if (ret)
> >  		return ret;
> >  
> >  	ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
> > -					  dst_addr_width,
> >  					  dst_maxburst);
> >  	if (ret)
> >  		return ret;
> > diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> > index 5ddd724..a035dfe 100644
> > --- a/drivers/dma/ste_dma40_ll.c
> > +++ b/drivers/dma/ste_dma40_ll.c
> > @@ -10,6 +10,18 @@
> >  
> >  #include "ste_dma40_ll.h"
> >  
> > +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> > +{
> > +	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> > +		return STEDMA40_ESIZE_8_BIT;
> > +	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> > +		return STEDMA40_ESIZE_16_BIT;
> > +	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> > +		return STEDMA40_ESIZE_64_BIT;
> > +	else
> > +		return STEDMA40_ESIZE_32_BIT;
> > +}
> > +
> Switch looks better for this and how about
> 	return fls(width);
> 
> as your defines are 0...3 and dmaengine define 1,2,..8 for same thing
> then you can also get rid of STEDMA40_XXX_WIDTH macros!

I like it.

Will you let me do it as a follow-up patch?

> > @@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
> >  	STEDMA40_FLOW_CTRL,
> >  };
> >  
> > -enum stedma40_periph_data_width {
> > -	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
> > -	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
> > -	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
> > -	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
> > -};
> nice
> 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Thu May 16 03:43:15 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 08:43:15 +0100
Subject: ux500 breaking multi-platform kernels
In-Reply-To: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
References: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
Message-ID: <20130516074315.GG3269@gmail.com>

On Wed, 15 May 2013, Rob Herring wrote:

> Lee, Linus,
> 
> There are some initcalls on ux500 that are not properly
> conditionalized. The first is in ux500_l2x0_init and here is a fix:
> 
> diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
> index f58615b..e066d32 100644
> --- a/arch/arm/mach-ux500/cache-l2x0.c
> +++ b/arch/arm/mach-ux500/cache-l2x0.c
> @@ -39,10 +39,10 @@ static int __init ux500_l2x0_init(void)
>  {
>         u32 aux_val = 0x3e000000;
> 
> -       if (cpu_is_u8500_family() || cpu_is_ux540_family())
> -               l2x0_base = __io_address(U8500_L2CC_BASE);
> -       else
> -               ux500_unknown_soc();
> +       if (!(cpu_is_u8500_family() || cpu_is_ux540_family()))
> +               return -ENODEV;
> +
> +       l2x0_base = __io_address(U8500_L2CC_BASE);
> 
>         /* Unlock before init */
>         ux500_l2x0_unlock();

Ah, I see. Nice solution.

Are you going to forward this as a patch? Do you require an Ack?

> Here is the second problem with cpuidle driver:

Can you re-run this and send me your vmlinux file and this output for
'that run' please? I'll endeavour to fix.

> [    4.514645] Unable to handle kernel NULL pointer dereference at
> virtual address 000000fc
> [    4.522729] pgd = c0004000
> [    4.525429] [000000fc] *pgd=00000000
> [    4.529009] Internal error: Oops: 5 [#1] SMP ARM
> [    4.533620] Modules linked in:
> [    4.536679] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W
> 3.10.0-rc1-00013-g5d170cd-dirty #527
> [    4.545893] task: ed888000 ti: ed884000 task.ti: ed884000
> [    4.551297] PC is at config_wakeups+0x6c/0x14c
> [    4.555740] LR is at db8500_prcmu_enable_wakeups+0x64/0x7c
> [    4.561223] pc : [<c06f4948>]    lr : [<c06f64f4>]    psr: 20000193
> [    4.561223] sp : ed885ec8  ip : ed885ef8  fp : ed885ef4
> [    4.572693] r10: c2d69494  r9 : 00000000  r8 : c31d92bc
> [    4.577911] r7 : 00028881  r6 : 00000000  r5 : c31d92bc  r4 : 00000000
> [    4.584431] r3 : 00000000  r2 : 00000000  r1 : 00000000  r0 : 60000113
> [    4.590954] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
> Segment kernel
> [    4.598342] Control: 10c53c7d  Table: 0000404a  DAC: 00000017
> [    4.604082] Process swapper/0 (pid: 1, stack limit = 0xed884240)
> [    4.610083] Stack: (0xed885ec8 to 0xed886000)
> [    4.614436] 5ec0:                   00000000 04019494 c31d92bc
> 00020081 60000113 c3137440
> [    4.622611] 5ee0: 00000000 c2d69494 ed885f14 ed885ef8 c06f64f4
> c06f48e8 ed884000 00000006
> [    4.630786] 5f00: c2d69488 c2c9abdc ed885f24 ed885f18 c2c9abf0
> c06f649c ed885f5c ed885f28
> [    4.638960] 5f20: c0008a78 c2c9abe8 00000be1 c2a527f4 ed885f5c
> 00000006 c2d69484 00000006
> [    4.647134] 5f40: c2d69488 c2df9efc c3137440 00000be1 ed885f94
> ed885f60 c2c71a98 c00089bc
> [    4.655307] 5f60: 00000006 00000006 c2c711ac c010ed98 00000000
> c1c95000 00000000 00000000
> [    4.663479] 5f80: 00000000 00000000 ed885fac ed885f98 c1c95018
> c2c718f8 00000000 00000000
> [    4.671651] 5fa0: 00000000 ed885fb0 c000ed98 c1c9500c 00000000
> 00000000 00000000 00000000
> [    4.679824] 5fc0: 00000000 00000000 00000000 00000000 00000000
> 00000000 00000000 00000000
> [    4.687997] 5fe0: 00000000 00000000 00000000 00000000 00000013
> 00000000 00000000 00000000
> [    4.696183] [<c06f4948>] (config_wakeups+0x6c/0x14c) from
> [<c06f64f4>] (db8500_prcmu_enable_wakeups+0x64/0x7c)
> [    4.706189] [<c06f64f4>] (db8500_prcmu_enable_wakeups+0x64/0x7c)
> from [<c2c9abf0>] (ux500_idle_init+0x14/0x2c)
> [    4.716195] [<c2c9abf0>] (ux500_idle_init+0x14/0x2c) from
> [<c0008a78>] (do_one_initcall+0xc8/0x184)
> [    4.725247] [<c0008a78>] (do_one_initcall+0xc8/0x184) from
> [<c2c71a98>] (kernel_init_freeable+0x1ac/0x284)
> [    4.734906] [<c2c71a98>] (kernel_init_freeable+0x1ac/0x284) from
> [<c1c95018>] (kernel_init+0x18/0xf4)
> [    4.744128] [<c1c95018>] (kernel_init+0x18/0xf4) from [<c000ed98>]
> (ret_from_fork+0x14/0x20)
> [    4.752565] Code: ea000001 e59f50dc e1a08005 e5953054 (e59320fc)
> [    4.758656] ---[ end trace 47a577e4e96d6f0b ]---
> [    4.763269] Kernel panic - not syncing: Fatal exception

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From thomas.petazzoni at free-electrons.com  Thu May 16 03:44:17 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 09:44:17 +0200
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe
 clocks on Armada 370
In-Reply-To: <20130515214154.12127.73539@quantum>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130515214154.12127.73539@quantum>
Message-ID: <20130516094417.24b1ca0d@skate>

Dear Mike Turquette,

On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> > The Armada 370 has two gatable clocks for each PCIe interface, and we
> > want both of them to be enabled. We therefore make one of the two
> > clocks a child of the other, as we did for the sataX and sataXlnk
> > clocks on Armada XP.
> 
> Ack for patches #5 and #6.  Do you want me to take them?

I don't know, I guess with your Ack, it would be easier to carry them
through the Marvell maintainers and then the arm-soc tree, so that we
can test arm-soc and have all the pieces needed in here.

That said, Sebastian Hesselbarth has submitted a big rework of the
mvebu clock drivers, which would conflict with this patch, and
Sebastian's rework would most likely go through your tree. If that's
the case, I guess it would be better to let you take #5 and #6 in this
patch series.

That's something to be discussed with the Marvell maintainers (Jason
Cooper, Andrew Lunn, Gregory Clement).

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From lee.jones at linaro.org  Thu May 16 03:48:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 08:48:31 +0100
Subject: ux500 breaking multi-platform kernels
In-Reply-To: <20130516074315.GG3269@gmail.com>
References: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
 <20130516074315.GG3269@gmail.com>
Message-ID: <20130516074831.GH3269@gmail.com>

> > Here is the second problem with cpuidle driver:
> 
> Can you re-run this and send me your vmlinux file and this output for
> 'that run' please? I'll endeavour to fix.

Scrap that. I see what's happening. I'll fix.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at stericsson.com  Thu May 16 03:48:45 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 16 May 2013 09:48:45 +0200
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
Message-ID: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The pinctrldev_list_mutex is sinked into the functions that
actually traverse the list and lock it there. The code makes
much more sense in this way. All the callers are in
non-performance critical paths and the code is way more
readable this way.

Also refactor the function get_pinctrl_dev_from_devname() to
follow the design pattern of get_pinctrl_dev_from_of_node()
which is slightly simpler.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/core.c | 34 +++++++++++++---------------------
 1 file changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 5327f35..1f9608b 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -101,20 +101,23 @@ EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata);
 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname)
 {
 	struct pinctrl_dev *pctldev = NULL;
-	bool found = false;
 
 	if (!devname)
 		return NULL;
 
+	mutex_lock(&pinctrldev_list_mutex);
+
 	list_for_each_entry(pctldev, &pinctrldev_list, node) {
 		if (!strcmp(dev_name(pctldev->dev), devname)) {
 			/* Matched on device name */
-			found = true;
-			break;
+			mutex_unlock(&pinctrldev_list_mutex);
+			return pctldev;
 		}
 	}
 
-	return found ? pctldev : NULL;
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	return NULL;
 }
 
 struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np)
@@ -326,6 +329,8 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
 	struct pinctrl_gpio_range *range = NULL;
 	struct gpio_chip *chip = gpio_to_chip(gpio);
 
+	mutex_lock(&pinctrldev_list_mutex);
+
 	/* Loop over the pin controllers */
 	list_for_each_entry(pctldev, &pinctrldev_list, node) {
 		/* Loop over the ranges */
@@ -334,9 +339,13 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
 			if (range->base + range->npins - 1 < chip->base ||
 			    range->base > chip->base + chip->ngpio - 1)
 				continue;
+			mutex_unlock(&pinctrldev_list_mutex);
 			return true;
 		}
 	}
+
+	mutex_unlock(&pinctrldev_list_mutex);
+
 	return false;
 }
 #else
@@ -408,8 +417,6 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
 {
 	struct pinctrl_dev *pctldev;
 
-	mutex_lock(&pinctrldev_list_mutex);
-
 	pctldev = get_pinctrl_dev_from_devname(devname);
 
 	/*
@@ -418,13 +425,10 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
 	 * range need to defer probing.
 	 */
 	if (!pctldev) {
-		mutex_unlock(&pinctrldev_list_mutex);
 		return ERR_PTR(-EPROBE_DEFER);
 	}
 	pinctrl_add_gpio_range(pctldev, range);
 
-	mutex_unlock(&pinctrldev_list_mutex);
-
 	return pctldev;
 }
 EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range);
@@ -517,13 +521,10 @@ int pinctrl_request_gpio(unsigned gpio)
 	int ret;
 	int pin;
 
-	mutex_lock(&pinctrldev_list_mutex);
-
 	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
 	if (ret) {
 		if (pinctrl_ready_for_gpio_range(gpio))
 			ret = 0;
-		mutex_unlock(&pinctrldev_list_mutex);
 		return ret;
 	}
 
@@ -532,7 +533,6 @@ int pinctrl_request_gpio(unsigned gpio)
 
 	ret = pinmux_request_gpio(pctldev, range, pin, gpio);
 
-	mutex_unlock(&pinctrldev_list_mutex);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pinctrl_request_gpio);
@@ -552,11 +552,8 @@ void pinctrl_free_gpio(unsigned gpio)
 	int ret;
 	int pin;
 
-	mutex_lock(&pinctrldev_list_mutex);
-
 	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
 	if (ret) {
-		mutex_unlock(&pinctrldev_list_mutex);
 		return;
 	}
 	mutex_lock(&pctldev->mutex);
@@ -567,7 +564,6 @@ void pinctrl_free_gpio(unsigned gpio)
 	pinmux_free_gpio(pctldev, pin, range);
 
 	mutex_unlock(&pctldev->mutex);
-	mutex_unlock(&pinctrldev_list_mutex);
 }
 EXPORT_SYMBOL_GPL(pinctrl_free_gpio);
 
@@ -578,11 +574,8 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input)
 	int ret;
 	int pin;
 
-	mutex_lock(&pinctrldev_list_mutex);
-
 	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
 	if (ret) {
-		mutex_unlock(&pinctrldev_list_mutex);
 		return ret;
 	}
 
@@ -593,7 +586,6 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input)
 	ret = pinmux_gpio_direction(pctldev, range, pin, input);
 
 	mutex_unlock(&pctldev->mutex);
-	mutex_unlock(&pinctrldev_list_mutex);
 
 	return ret;
 }
-- 
1.7.11.3



From marek.belisko at streamunlimited.com  Thu May 16 03:53:26 2013
From: marek.belisko at streamunlimited.com (Marek Belisko)
Date: Thu, 16 May 2013 09:53:26 +0200
Subject: [PATCH v2 1/2] clk: si5351: Fix clkout rate computation.
In-Reply-To: <20130514191650.10068.92925@quantum>
References: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
 <20130514191650.10068.92925@quantum>
Message-ID: <51949076.9040008@streamunlimited.com>

On 05/14/2013 09:16 PM, Mike Turquette wrote:
> Quoting Marek Belisko (2013-05-02 22:53:22)
>> Rate was incorrectly computed because we read from wrong divider register.
>>
>> Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
>> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
>
> Do either of these patches need to go into clk-fixes?  If so please be
> explicit about it in the changelog, the section under the three dashes.
Yes I believe they should go to clk-fixes (probably also to linux-stable).
>
> Regards,
> Mike
>
>> ---
>>   drivers/clk/clk-si5351.c |    2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
>> index 8927284..cf39e53 100644
>> --- a/drivers/clk/clk-si5351.c
>> +++ b/drivers/clk/clk-si5351.c
>> @@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
>>          unsigned char reg;
>>          unsigned char rdiv;
>>
>> -       if (hwdata->num > 5)
>> +       if (hwdata->num <= 5)
>>                  reg = si5351_msynth_params_address(hwdata->num) + 2;
>>          else
>>                  reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
>> --
>> 1.7.9.5
>

Regards,

Marek
-- 
Marek Belisko

Software Developer
StreamUnlimited Engineering GmbH
Gutheil Schodergasse 8-12
A-1100 Vienna, Austria

Office: +421 267200087

e-mail: marek.belisko at streamunlimited.com
http://www.streamunlimited.com

Meet us at:

IFA - Berlin, 6-11 September
CEDIA - Denver, 25-28 September


From g.liakhovetski at gmx.de  Thu May 16 03:57:20 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 16 May 2013 09:57:20 +0200 (CEST)
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <Pine.LNX.4.64.1305160951040.21125@axis700.grange>

Hi Laurent

On Wed, 15 May 2013, Laurent Pinchart wrote:

> Add GPIO controller nodes to the r8a7790 core device tree.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> ---
>  arch/arm/boot/dts/r8a7790.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index ee21061..b5fe51da 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -44,6 +44,60 @@
>  		};
>  	};
>  
> +	gpio0: gpio at ffc40000 {
> +		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
> +		reg = <0xffc40000 0x2c>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 4 0x4>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +	};

I'm testing your patches on Lager and GPIOs don't seem to get registered:

/ # ls /sys/class/gpio/
export    unexport
/ #

And this is easy to trace back: sh_pfc_probe() calls 
sh_pfc_register_gpiochip(), where a check

	if (pfc->info->data_regs == NULL)
		return 0;

successfully fails GPIO initialisation :) Is this known and there are 
still some pieces missing, or you weren't aware of this?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From maxime.ripard at free-electrons.com  Thu May 16 04:18:14 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 16 May 2013 10:18:14 +0200
Subject: [PATCHv2 00/20] Cleanup irqchip_init calls
In-Reply-To: <201305151455.12603.arnd@arndb.de>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <201305151455.12603.arnd@arndb.de>
Message-ID: <51949646.4000107@free-electrons.com>

Hi Arnd,

Le 15/05/2013 14:55, Arnd Bergmann a ?crit :
> On Tuesday 14 May 2013, Maxime Ripard wrote:
>> This is a splitted up version of the patch I previously sent to
>> remove the explicit declaration of irqchip_init as the init_irq callback in
>> the machine descriptions.
>>
>> Since it was a pretty tricky patch to merge, since it was touching a lot of
>> different platforms, I splitted it for each platforms, and rebased it on top
>> of 3.10-rc1.
>>
>> The best way to merge it is probably that each one of us take into their tree
>> the patches that are relevant for our architecture and send them to arm-soc
>> later on.
> 
> Sounds good to me. I'm sure that some platform maintainers will fail to
> apply this though. Could you send whatever remains as a separate branch
> in a couple of weeks so we can directly apply it to next/cleanup?

Ok, I will.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Thu May 16 04:18:57 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 16 May 2013 10:18:57 +0200
Subject: [PATCH 20/20] ARM: vt8500: Remove init_irq declaration in machine
 description
In-Reply-To: <5193D953.5040202@prisktech.co.nz>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-21-git-send-email-maxime.ripard@free-electrons.com>
 <5193D953.5040202@prisktech.co.nz>
Message-ID: <51949671.1070907@free-electrons.com>

Hi Tony,

Le 15/05/2013 20:52, Tony Prisk a ?crit :
> I don't have any plans to touch this driver, so please send direct to
> arm-soc as Arnd
> requested.
> 
> Acked-by: Tony Prisk <linux at prisktech.co.nz>

Thanks!

I will send it then.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Thu May 16 04:19:56 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 16 May 2013 10:19:56 +0200
Subject: [PATCH 04/20] ARM: picoxcell: Remove init_irq declaration in
 machine description
In-Reply-To: <20130514162046.GA16346@page>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-5-git-send-email-maxime.ripard@free-electrons.com>
 <20130514162046.GA16346@page>
Message-ID: <519496AC.1070809@free-electrons.com>

Hi Jamie,

Le 14/05/2013 18:20, Jamie Iles a ?crit :
> Hi Maxime,
> 
> Thanks for this, I'll add it to my tree.  I've modified it slightly to 
> kill off the other irq includes, hopefully that's okay with you.

Yes, I was pretty conservative since I was not familiar with most of the
code, but yes, I'm fine with the changes.

Thank you,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From sebastian.hesselbarth at gmail.com  Thu May 16 04:26:24 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 16 May 2013 10:26:24 +0200
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe
 clocks on Armada 370
In-Reply-To: <20130516094417.24b1ca0d@skate>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130515214154.12127.73539@quantum> <20130516094417.24b1ca0d@skate>
Message-ID: <51949830.70306@gmail.com>

On 05/16/2013 09:44 AM, Thomas Petazzoni wrote:
> Dear Mike Turquette,
>
> On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
>> Quoting Thomas Petazzoni (2013-05-15 06:25:19)
>>> The Armada 370 has two gatable clocks for each PCIe interface, and we
>>> want both of them to be enabled. We therefore make one of the two
>>> clocks a child of the other, as we did for the sataX and sataXlnk
>>> clocks on Armada XP.
>>
>> Ack for patches #5 and #6.  Do you want me to take them?
>
> I don't know, I guess with your Ack, it would be easier to carry them
> through the Marvell maintainers and then the arm-soc tree, so that we
> can test arm-soc and have all the pieces needed in here.
>
> That said, Sebastian Hesselbarth has submitted a big rework of the
> mvebu clock drivers, which would conflict with this patch, and
> Sebastian's rework would most likely go through your tree. If that's
> the case, I guess it would be better to let you take #5 and #6 in this
> patch series.

I also requested to take the restructure patches through ARM tree. They
are only touching files in drivers/clk/mvebu and by taking them through
ARM, we can update PCIe clock patches easily. The dependency between
Thomas' and my patches basically is that I renamed files that Thomas
now commits to. (I switched clk/mvebu from per-function files to per-soc
files).

> That's something to be discussed with the Marvell maintainers (Jason
> Cooper, Andrew Lunn, Gregory Clement).

Sebastian


From dt.tangr at gmail.com  Thu May 16 04:31:38 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Thu, 16 May 2013 18:31:38 +1000
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <201305151607.54442.arnd@arndb.de>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-4-git-send-email-dt.tangr@gmail.com>
 <201305151607.54442.arnd@arndb.de>
Message-ID: <15FD6543-D04A-4953-A56A-40B27F0026E4@gmail.com>


On 16/05/2013, at 12:07 AM, Arnd Bergmann <arnd at arndb.de> wrote:

> You are missing a binding in Documentation/devicetree, same as for some of
> the other drivers in this series.

Should we be adding a vendor prefix to it too? If so, we're not sure whether to use "ti," or not since this isn't an official port by TI.

> It seems strange to assign the clk_name variable to node->name
> first and then overriding it with the clock-output-names property.
> Is that intentional? If so, please explain it in a comment.
> 

I copied that bit of boilerplate from drivers/clk/clk-fixed-rate.c but I'm guessing it's to use the node name as the clock name unless there is a property called "clock-output-names"

Cheers,
Daniel Tang

From linux at arm.linux.org.uk  Thu May 16 04:57:11 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 May 2013 09:57:11 +0100
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <201305160054.21064.arnd@arndb.de>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201305151516.52389.arnd@arndb.de>
 <20130515133237.GK18614@n2100.arm.linux.org.uk>
 <201305160054.21064.arnd@arndb.de>
Message-ID: <20130516085711.GP18614@n2100.arm.linux.org.uk>

On Thu, May 16, 2013 at 12:54:20AM +0200, Arnd Bergmann wrote:
> Ah, I see. I also read the mach-gemini version of the idle code,
> which is apparently the same thing as the code that was commented
> out here, so that has the wakeup race.
> 
> Since it seems that WFI is broken on all fa526 cores, or at least
> all the ones we want to support in Linux, maybe it's better to
> not call WFI at all there?

Well, if its a CPU core thing, then it's even easier - the proc-*.S
file can handle it just fine (because that's where the WFI code is.)
Just delete the contents of the processor specific idle function, IOW:

/*
 * cpu_fa526_do_idle()
 */
        .align  4
ENTRY(cpu_fa526_do_idle)
        mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
        mov     pc, lr

remove the WFI from there.


From james.hogan at imgtec.com  Thu May 16 05:25:44 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Thu, 16 May 2013 10:25:44 +0100
Subject: [PATCH v2 0/3] clk: implement remuxing during set_rate
In-Reply-To: <51945C7F.2030605@codeaurora.org>
References: <1366388904-13903-1-git-send-email-james.hogan@imgtec.com>
 <51945C7F.2030605@codeaurora.org>
Message-ID: <5194A618.3040900@imgtec.com>

On 16/05/13 05:11, Saravana Kannan wrote:
> I really want to review this because I solved the same problem in our
> internal clock framework and want to make sure upstream doesn't go
> through the same mistakes. But haven't had the time. Hopefully, I'll go
> it before this gets accepted by Mike. I'll try to do it this week/weekend.

Great! FYI I submitted a v3 yesterday, but screwed up and forgot to CC
LKML :-(

It can be found on linux-arm-kernel archives here (or if it's a real
PITA I can resubmit cc'ing LKML):

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168485.html

Cheers
James



From dedekind1 at gmail.com  Thu May 16 05:32:28 2013
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 16 May 2013 12:32:28 +0300
Subject: [PATCH 0/4] mtd: atmel_nand: enable Nand Flash Controller (NFC)
 support
In-Reply-To: <1366712997-17639-1-git-send-email-josh.wu@atmel.com>
References: <1366712997-17639-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368696748.15764.184.camel@sauron.fi.intel.com>

On Tue, 2013-04-23 at 18:29 +0800, Josh Wu wrote:
> This patch series enable NFC support for SAMA5 soc. It can send command,
> address cycles automaticly. Also when enable NFC sram, NFC will transfer
> data to sram. Which can save lots of cpu time.
> 
> Josh Wu (4):
>   mtd: atmel_nand: replace pmecc enable code with one function.
>   mtd: atmel_nand: add Nand Flash Controller (NFC) support
>   mtd: atmel_nand: enable Nand Flash Controller (NFC) read data
>     via sram
>   mtd: atmel_nand: enable Nand Flash Controller (NFC) write via
>     sram

Please, re-base against the latest l2-mtd.git tree. The patches do not
compile:

--------------------------------------------------------------------------------
Failed to build the following commit for configuration "arm-at91cap9_defconfig" (architecture arm)":

2bd4bff mtd: atmel_nand: enable Nand Flash Controller (NFC) write via sram

drivers/mtd/nand/atmel_nand.c: In function 'nfc_nand_command':
drivers/mtd/nand/atmel_nand.c:1848: error: 'NAND_CMD_DEPLETE1' undeclared (first use in this function)
drivers/mtd/nand/atmel_nand.c:1848: error: (Each undeclared identifier is reported only once
drivers/mtd/nand/atmel_nand.c:1848: error: for each function it appears in.)
drivers/mtd/nand/atmel_nand.c:1854: error: 'NAND_CMD_STATUS_ERROR' undeclared (first use in this function)
drivers/mtd/nand/atmel_nand.c:1855: error: 'NAND_CMD_STATUS_ERROR0' undeclared (first use in this function)
drivers/mtd/nand/atmel_nand.c:1856: error: 'NAND_CMD_STATUS_ERROR1' undeclared (first use in this function)
drivers/mtd/nand/atmel_nand.c:1857: error: 'NAND_CMD_STATUS_ERROR2' undeclared (first use in this function)
drivers/mtd/nand/atmel_nand.c:1858: error: 'NAND_CMD_STATUS_ERROR3' undeclared (first use in this function)
drivers/mtd/nand/atmel_nand.c: In function 'nfc_sram_init':
drivers/mtd/nand/atmel_nand.c:1979: warning: assignment from incompatible pointer type
make[4]: *** [drivers/mtd/nand/atmel_nand.o] Error 1

-- 
Best Regards,
Artem Bityutskiy



From ezequiel.garcia at free-electrons.com  Thu May 16 05:33:14 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Thu, 16 May 2013 06:33:14 -0300
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130516093312.GB2459@localhost>

On Wed, May 15, 2013 at 03:25:21PM +0200, Thomas Petazzoni wrote:
[..]
> +
> +static int __init mvebu_pcie_probe(struct platform_device *pdev)
> +{
> +	struct mvebu_pcie *pcie;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct of_pci_range range;
> +	struct of_pci_range_parser parser;
> +	struct device_node *child;
> +	int i, ret;
> +
> +	pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
> +			    GFP_KERNEL);
> +	if (!pcie)
> +		return -ENOMEM;
> +
> +	pcie->pdev = pdev;
> +
> +	if (of_pci_range_parser_init(&parser, np))
> +		return -EINVAL;
> +
> +	/* Get the I/O and memory ranges from DT */
> +	for_each_of_pci_range(&parser, &range) {
> +		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
> +		if (restype == IORESOURCE_IO) {
> +			of_pci_range_to_resource(&range, np, &pcie->io);
> +			of_pci_range_to_resource(&range, np, &pcie->realio);
> +			pcie->io.name = "I/O";
> +			pcie->realio.start = max_t(resource_size_t,
> +						   PCIBIOS_MIN_IO,
> +						   range.pci_addr);
> +			pcie->realio.end = min_t(resource_size_t,
> +						 IO_SPACE_LIMIT,
> +						 range.pci_addr + range.size);
> +		}
> +		if (restype == IORESOURCE_MEM) {
> +			of_pci_range_to_resource(&range, np, &pcie->mem);
> +			pcie->mem.name = "MEM";
> +		}
> +	}
> +
> +	/* Get the bus range */
> +	ret = of_pci_parse_bus_range(np, &pcie->busn);
> +	if (ret) {
> +		dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
> +			ret);
> +		return ret;
> +	}
> +
> +	for_each_child_of_node(pdev->dev.of_node, child) {
> +		if (!of_device_is_available(child))
> +			continue;
> +		pcie->nports++;
> +	}
> +
> +	pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
> +				   sizeof(struct mvebu_pcie_port),
> +				   GFP_KERNEL);
> +	if (!pcie->ports)
> +		return -ENOMEM;
> +
> +	i = 0;
> +	for_each_child_of_node(pdev->dev.of_node, child) {
> +		struct mvebu_pcie_port *port = &pcie->ports[i];
> +
> +		if (!of_device_is_available(child))
> +			continue;
> +
> +		port->pcie = pcie;
> +
> +		if (of_property_read_u32(child, "marvell,pcie-port",
> +					 &port->port)) {
> +			dev_warn(&pdev->dev,
> +				 "ignoring PCIe DT node, missing pcie-port property\n");
> +			continue;
> +		}
> +
> +		if (of_property_read_u32(child, "marvell,pcie-lane",
> +					 &port->lane))
> +			port->lane = 0;
> +
> +		port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
> +				       port->port, port->lane);
> +
> +		port->devfn = of_pci_get_devfn(child);
> +		if (port->devfn < 0)
> +			continue;
> +
> +		port->base = mvebu_pcie_map_registers(pdev, child, port);
> +		if (!port->base) {
> +			dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
> +				port->port, port->lane);
> +			continue;
> +		}
> +
> +		if (mvebu_pcie_link_up(port)) {
> +			port->haslink = 1;
> +			dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
> +				 port->port, port->lane);
> +		} else {
> +			port->haslink = 0;
> +			dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
> +				 port->port, port->lane);
> +		}
> +
> +		port->clk = of_clk_get_by_name(child, NULL);
> +		if (!port->clk) {
> +			dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
> +			       port->port, port->lane);
> +			iounmap(port->base);
> +			port->haslink = 0;
> +			continue;
> +		}
> +
> +		port->dn = child;
> +
> +		clk_prepare_enable(port->clk);
> +		spin_lock_init(&port->conf_lock);
> +
> +		mvebu_sw_pci_bridge_init(port);
> +
> +		i++;
> +	}
> +
> +	mvebu_pcie_enable(pcie);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id mvebu_pcie_of_match_table[] = {
> +	{ .compatible = "marvell,armada-xp-pcie", },
> +	{ .compatible = "marvell,armada-370-pcie", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
> +
> +static struct platform_driver mvebu_pcie_driver = {
> +	.driver = {
> +		.owner = THIS_MODULE,
> +		.name = "mvebu-pcie",
> +		.of_match_table =
> +		   of_match_ptr(mvebu_pcie_of_match_table),
> +	},
> +};
> +
> +static int mvebu_pcie_init(void)

Building this showed a warning here. It seems you forgot
to mark this one as __init.

-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com


From james.hogan at imgtec.com  Thu May 16 05:35:39 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Thu, 16 May 2013 10:35:39 +0100
Subject: [PATCH v3 2/4] clk: add support for clock reparent on set_rate
In-Reply-To: <5193EF34.7070800@codeaurora.org>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
 <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>
 <5193EF34.7070800@codeaurora.org>
Message-ID: <5194A86B.6000207@imgtec.com>

On 15/05/13 21:25, Stephen Boyd wrote:
> On 05/15/13 06:41, James Hogan wrote:
>> Each place where round_rate() is called, determine_rate is checked first
>> and called in preference, passing NULL to the new parent argument if not
>> needed (e.g. in __clk_round_rate).
> 
> That's annoying. Even if we don't care about the pointer in
> clk_round_rate(), this requires the ops to check for NULL before
> assigning the pointer. Why not just pass an unused pointer that the ops
> can assign all the time?

True, I'll fix that.

> With the above change you can add
> 
> Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>

Thanks for taking the time to review it.

Cheers
James



From wsa at the-dreams.de  Thu May 16 05:38:49 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Thu, 16 May 2013 11:38:49 +0200
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
References: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130516093846.GA2927@katana>

On Thu, May 16, 2013 at 10:50:07AM +0800, Barry Song wrote:
> From: Xiaomeng Hou <Xiaomeng.Hou at csr.com>
> 
> if we initilize i2c bus by module_init, there are some devices which want
> initialization earlier than i2c and could not do that in time, so move i2c
> driver initilization to subsys_initcall and make i2c ready before devices
> init.
> 
> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

What about deferred probing?



From lars at metafoo.de  Thu May 16 05:51:56 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 16 May 2013 11:51:56 +0200
Subject: [PATCH] ASoC: dfbmcs320: make the driver common for other BT
 modules
In-Reply-To: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>
References: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <5194AC3C.4080206@metafoo.de>

On 05/16/2013 08:53 AM, Barry Song wrote:
> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
> we don't want everyone to have a seperate codec driver. anyway, the
> feature of Bluetooth handsfree is same on all platforms, so this patch
> makes the DFBM-CS320 driver become a common BT handsfree driver.
[...]
> -static struct platform_driver dfmcs320_driver = {
> +static struct platform_driver bt_handsfree_driver = {
>  	.driver = {
> -		.name = "dfbmcs320",
> +		.name = "bt-handsfree",
>  		.owner = THIS_MODULE,

In my opinion it's a good idea to keep a platform_id list of all the
supported devices.

>  	},
> -	.probe = dfbmcs320_probe,
> -	.remove = dfbmcs320_remove,
> +	.probe = bt_handsfree_probe,
> +	.remove = bt_handsfree_remove,
>  };
>  
> -module_platform_driver(dfmcs320_driver);
> +module_platform_driver(bt_handsfree_driver);



From josephl at nvidia.com  Thu May 16 05:53:39 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 May 2013 17:53:39 +0800
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <51941C58.9060002@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <51941C58.9060002@wwwdotorg.org>
Message-ID: <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>

On Thu, 2013-05-16 at 07:38 +0800, Stephen Warren wrote:
> On 05/15/2013 04:27 AM, Joseph Lo wrote:
> > Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> > as CPU core and a enhanced flow controller for CPU power control. So
> > we need to skip some code that was for Contex-A9 and some other support
> > code that was for other Tegra SoC chips. Then adding the proper power up
> > and hot plug control for Tegra114.
> 
> This series mostly works OK, but I see one problem: I can't hotunplug
> CPU0, which the commit descriptions and code changes imply I should be
> able to do:
> 
> root at localhost:~# echo 0 > /sys/devices/system/cpu/cpu0/online
> -bash: echo: write error: Operation not permitted

I want to provide this function originally. But I found the
tegra_cpu_disable() was removed recently. It was replaced by the common
cpu_disable() function that didn't allow CPU0 to be un-plugged.

But I had verified the CPU0 is OK to be un-plugged on the older
linux-next branch that tegra_cpu_disable() watn't removed yet.

Do you want me to add them back to support this function for Tegra114?

Thanks,
Joseph



From t.figa at samsung.com  Thu May 16 05:57:05 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:05 +0200
Subject: [PATCH v2 0/6] Samsung USB PHY SoC support cleanup
Message-ID: <1368698231-24268-1-git-send-email-t.figa@samsung.com>

This patch series intends to improve handling of SoC-specific differences
in Samsung USB PHY drivers, by reducing the need to explicitly check
SoC type using if and switch statements.

In addition, last patch adds support for Exynos 4x12, as this is simply
a matter of adding appropriate driver data and additional case in two switches.

Tested on Exynos4210-based Trats board and Exynos4412-based internal
Samsung board.

Changes since v1:
 - rebased to latest usb-next

Tomasz Figa (6):
  usb: phy: samsung: Select common driver part implicitly
  usb: phy: samsung: Use clk_get to get reference clock
  usb: phy: samsung: Consolidate reference clock rate handling
  usb: phy: samsung: Pass set_isolation callback through driver data
  usb: phy: samsung: Pass enable/disable callbacks through driver data
  usb: phy: samsung: Add support for USB 2.0 PHY on Exynos 4x12

 drivers/usb/phy/Kconfig            |   2 +-
 drivers/usb/phy/phy-samsung-usb.c  | 154 ++++++++++++++++++-------------------
 drivers/usb/phy/phy-samsung-usb.h  |  14 +++-
 drivers/usb/phy/phy-samsung-usb2.c |  53 +++++++++----
 drivers/usb/phy/phy-samsung-usb3.c |  23 ++++--
 5 files changed, 146 insertions(+), 100 deletions(-)

-- 
1.8.2.1



From t.figa at samsung.com  Thu May 16 05:57:06 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:06 +0200
Subject: [PATCH v2 1/6] usb: phy: samsung: Select common driver part implicitly
In-Reply-To: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
References: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368698231-24268-2-git-send-email-t.figa@samsung.com>

Since phy-samsung-usb library can be used only by phy-samsung-usb2 and
phy-samsung-usb3 drivers, there is no need to give explicit control over
its Kconfig symbol.

This patch makes CONFIG_SAMSUNG_USBPHY symbol hidden and selected
implicitly by CONFIG_SAMSUNG_USB2PHY and CONFIG_SAMSUNG_USB3PHY.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/usb/phy/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 371d0e7..a2b9e18 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -86,7 +86,7 @@ config OMAP_USB3
 	  on/off the PHY.
 
 config SAMSUNG_USBPHY
-	tristate "Samsung USB PHY Driver"
+	tristate
 	help
 	  Enable this to support Samsung USB phy helper driver for Samsung SoCs.
 	  This driver provides common interface to interact, for Samsung USB 2.0 PHY
-- 
1.8.2.1



From t.figa at samsung.com  Thu May 16 05:57:07 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:07 +0200
Subject: [PATCH v2 2/6] usb: phy: samsung: Use clk_get to get reference clock
In-Reply-To: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
References: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368698231-24268-3-git-send-email-t.figa@samsung.com>

There is no need to use devm_clk_get to get a clock that is being put
at the end of the function.

This patch changes the code getting reference clock to use clk_get
instead of useless in this case devm_clk_get.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/usb/phy/phy-samsung-usb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/phy/phy-samsung-usb.c b/drivers/usb/phy/phy-samsung-usb.c
index 7b118ee5..62cdb7e 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -175,9 +175,9 @@ int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
 	 * external crystal clock XXTI
 	 */
 	if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
-		ref_clk = devm_clk_get(sphy->dev, "ext_xtal");
+		ref_clk = clk_get(sphy->dev, "ext_xtal");
 	else
-		ref_clk = devm_clk_get(sphy->dev, "xusbxti");
+		ref_clk = clk_get(sphy->dev, "xusbxti");
 	if (IS_ERR(ref_clk)) {
 		dev_err(sphy->dev, "Failed to get reference clock\n");
 		return PTR_ERR(ref_clk);
-- 
1.8.2.1



From t.figa at samsung.com  Thu May 16 05:57:08 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:08 +0200
Subject: [PATCH v2 3/6] usb: phy: samsung: Consolidate reference clock rate
 handling
In-Reply-To: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
References: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368698231-24268-4-git-send-email-t.figa@samsung.com>

This patch cleans up handling of reference clock rate in Samsung USB PHY
drivers. It is mostly a cosmetic change but improves error handling in
case of failing to get reference clock or invalid clock rate.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/usb/phy/phy-samsung-usb.c  | 114 ++++++++++++++++++++++---------------
 drivers/usb/phy/phy-samsung-usb.h  |   7 +++
 drivers/usb/phy/phy-samsung-usb2.c |   8 ++-
 drivers/usb/phy/phy-samsung-usb3.c |   6 +-
 4 files changed, 86 insertions(+), 49 deletions(-)

diff --git a/drivers/usb/phy/phy-samsung-usb.c b/drivers/usb/phy/phy-samsung-usb.c
index 62cdb7e..c40ea32 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -162,13 +162,76 @@ int samsung_usbphy_set_type(struct usb_phy *phy,
 }
 EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
 
+int samsung_usbphy_rate_to_clksel_64xx(struct samsung_usbphy *sphy,
+							unsigned long rate)
+{
+	unsigned int clksel;
+
+	switch (rate) {
+	case 12 * MHZ:
+		clksel = PHYCLK_CLKSEL_12M;
+		break;
+	case 24 * MHZ:
+		clksel = PHYCLK_CLKSEL_24M;
+		break;
+	case 48 * MHZ:
+		clksel = PHYCLK_CLKSEL_48M;
+		break;
+	default:
+		dev_err(sphy->dev,
+			"Invalid reference clock frequency: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	return clksel;
+}
+EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_64xx);
+
+int samsung_usbphy_rate_to_clksel_4x12(struct samsung_usbphy *sphy,
+							unsigned long rate)
+{
+	unsigned int clksel;
+
+	switch (rate) {
+	case 9600 * KHZ:
+		clksel = FSEL_CLKSEL_9600K;
+		break;
+	case 10 * MHZ:
+		clksel = FSEL_CLKSEL_10M;
+		break;
+	case 12 * MHZ:
+		clksel = FSEL_CLKSEL_12M;
+		break;
+	case 19200 * KHZ:
+		clksel = FSEL_CLKSEL_19200K;
+		break;
+	case 20 * MHZ:
+		clksel = FSEL_CLKSEL_20M;
+		break;
+	case 24 * MHZ:
+		clksel = FSEL_CLKSEL_24M;
+		break;
+	case 50 * MHZ:
+		clksel = FSEL_CLKSEL_50M;
+		break;
+	default:
+		dev_err(sphy->dev,
+			"Invalid reference clock frequency: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	return clksel;
+}
+EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_4x12);
+
 /*
  * Returns reference clock frequency selection value
  */
 int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
 {
 	struct clk *ref_clk;
-	int refclk_freq = 0;
+	unsigned long rate;
+	int refclk_freq;
 
 	/*
 	 * In exynos5250 USB host and device PHY use
@@ -183,52 +246,9 @@ int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
 		return PTR_ERR(ref_clk);
 	}
 
-	if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) {
-		/* set clock frequency for PLL */
-		switch (clk_get_rate(ref_clk)) {
-		case 9600 * KHZ:
-			refclk_freq = FSEL_CLKSEL_9600K;
-			break;
-		case 10 * MHZ:
-			refclk_freq = FSEL_CLKSEL_10M;
-			break;
-		case 12 * MHZ:
-			refclk_freq = FSEL_CLKSEL_12M;
-			break;
-		case 19200 * KHZ:
-			refclk_freq = FSEL_CLKSEL_19200K;
-			break;
-		case 20 * MHZ:
-			refclk_freq = FSEL_CLKSEL_20M;
-			break;
-		case 50 * MHZ:
-			refclk_freq = FSEL_CLKSEL_50M;
-			break;
-		case 24 * MHZ:
-		default:
-			/* default reference clock */
-			refclk_freq = FSEL_CLKSEL_24M;
-			break;
-		}
-	} else {
-		switch (clk_get_rate(ref_clk)) {
-		case 12 * MHZ:
-			refclk_freq = PHYCLK_CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			refclk_freq = PHYCLK_CLKSEL_24M;
-			break;
-		case 48 * MHZ:
-			refclk_freq = PHYCLK_CLKSEL_48M;
-			break;
-		default:
-			if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
-				refclk_freq = PHYCLK_CLKSEL_48M;
-			else
-				refclk_freq = PHYCLK_CLKSEL_24M;
-			break;
-		}
-	}
+	rate = clk_get_rate(ref_clk);
+	refclk_freq = sphy->drv_data->rate_to_clksel(sphy, rate);
+
 	clk_put(ref_clk);
 
 	return refclk_freq;
diff --git a/drivers/usb/phy/phy-samsung-usb.h b/drivers/usb/phy/phy-samsung-usb.h
index 70a9cae..0336f6b 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -244,6 +244,8 @@ enum samsung_cpu_type {
 	TYPE_EXYNOS5250,
 };
 
+struct samsung_usbphy;
+
 /*
  * struct samsung_usbphy_drvdata - driver data for various SoC variants
  * @cpu_type: machine identifier
@@ -268,6 +270,7 @@ struct samsung_usbphy_drvdata {
 	int hostphy_en_mask;
 	u32 devphy_reg_offset;
 	u32 hostphy_reg_offset;
+	int (*rate_to_clksel)(struct samsung_usbphy *, unsigned long);
 };
 
 /*
@@ -325,3 +328,7 @@ extern void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy);
 extern int samsung_usbphy_set_type(struct usb_phy *phy,
 					enum samsung_usb_phy_type phy_type);
 extern int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy);
+extern int samsung_usbphy_rate_to_clksel_64xx(struct samsung_usbphy *sphy,
+							unsigned long rate);
+extern int samsung_usbphy_rate_to_clksel_4x12(struct samsung_usbphy *sphy,
+							unsigned long rate);
diff --git a/drivers/usb/phy/phy-samsung-usb2.c b/drivers/usb/phy/phy-samsung-usb2.c
index 45ffe03..802e738 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -413,7 +413,10 @@ static int samsung_usb2phy_probe(struct platform_device *pdev)
 	sphy->phy.label		= "samsung-usb2phy";
 	sphy->phy.init		= samsung_usb2phy_init;
 	sphy->phy.shutdown	= samsung_usb2phy_shutdown;
-	sphy->ref_clk_freq	= samsung_usbphy_get_refclk_freq(sphy);
+
+	sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
+	if (sphy->ref_clk_freq < 0)
+		return -EINVAL;
 
 	sphy->phy.otg		= otg;
 	sphy->phy.otg->phy	= &sphy->phy;
@@ -443,18 +446,21 @@ static int samsung_usb2phy_remove(struct platform_device *pdev)
 static const struct samsung_usbphy_drvdata usb2phy_s3c64xx = {
 	.cpu_type		= TYPE_S3C64XX,
 	.devphy_en_mask		= S3C64XX_USBPHY_ENABLE,
+	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_64xx,
 };
 
 static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
 	.cpu_type		= TYPE_EXYNOS4210,
 	.devphy_en_mask		= EXYNOS_USBPHY_ENABLE,
 	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
+	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_64xx,
 };
 
 static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
 	.cpu_type		= TYPE_EXYNOS5250,
 	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
 	.hostphy_reg_offset	= EXYNOS_USBHOST_PHY_CTRL_OFFSET,
+	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
 };
 
 #ifdef CONFIG_OF
diff --git a/drivers/usb/phy/phy-samsung-usb3.c b/drivers/usb/phy/phy-samsung-usb3.c
index 133f3d0..c07bc32 100644
--- a/drivers/usb/phy/phy-samsung-usb3.c
+++ b/drivers/usb/phy/phy-samsung-usb3.c
@@ -279,7 +279,10 @@ static int samsung_usb3phy_probe(struct platform_device *pdev)
 	sphy->phy.init		= samsung_usb3phy_init;
 	sphy->phy.shutdown	= samsung_usb3phy_shutdown;
 	sphy->drv_data		= samsung_usbphy_get_driver_data(pdev);
-	sphy->ref_clk_freq	= samsung_usbphy_get_refclk_freq(sphy);
+
+	sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
+	if (sphy->ref_clk_freq < 0)
+		return -EINVAL;
 
 	spin_lock_init(&sphy->lock);
 
@@ -305,6 +308,7 @@ static int samsung_usb3phy_remove(struct platform_device *pdev)
 static struct samsung_usbphy_drvdata usb3phy_exynos5 = {
 	.cpu_type		= TYPE_EXYNOS5250,
 	.devphy_en_mask		= EXYNOS_USBPHY_ENABLE,
+	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
 };
 
 #ifdef CONFIG_OF
-- 
1.8.2.1



From t.figa at samsung.com  Thu May 16 05:57:09 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:09 +0200
Subject: [PATCH v2 4/6] usb: phy: samsung: Pass set_isolation callback through
 driver data
In-Reply-To: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
References: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368698231-24268-5-git-send-email-t.figa@samsung.com>

This patch extends driver data structure with set_isolation callback,
which allows to remove the need for checking for SoC type in a switch
statement.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/usb/phy/phy-samsung-usb.c  | 36 ++++++++----------------------------
 drivers/usb/phy/phy-samsung-usb.h  |  4 +++-
 drivers/usb/phy/phy-samsung-usb2.c | 11 +++++++----
 drivers/usb/phy/phy-samsung-usb3.c |  7 +++++--
 4 files changed, 23 insertions(+), 35 deletions(-)

diff --git a/drivers/usb/phy/phy-samsung-usb.c b/drivers/usb/phy/phy-samsung-usb.c
index c40ea32..7a1ed90 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -73,7 +73,7 @@ EXPORT_SYMBOL_GPL(samsung_usbphy_parse_dt);
  * Here 'on = true' would mean USB PHY block is isolated, hence
  * de-activated and vice-versa.
  */
-void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
+void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy, bool on)
 {
 	void __iomem *reg = NULL;
 	u32 reg_val;
@@ -84,32 +84,12 @@ void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
 		return;
 	}
 
-	switch (sphy->drv_data->cpu_type) {
-	case TYPE_S3C64XX:
-		/*
-		 * Do nothing: We will add here once S3C64xx goes for DT support
-		 */
-		break;
-	case TYPE_EXYNOS4210:
-		/*
-		 * Fall through since exynos4210 and exynos5250 have similar
-		 * register architecture: two separate registers for host and
-		 * device phy control with enable bit at position 0.
-		 */
-	case TYPE_EXYNOS5250:
-		if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
-			reg = sphy->pmuregs +
-				sphy->drv_data->devphy_reg_offset;
-			en_mask = sphy->drv_data->devphy_en_mask;
-		} else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
-			reg = sphy->pmuregs +
-				sphy->drv_data->hostphy_reg_offset;
-			en_mask = sphy->drv_data->hostphy_en_mask;
-		}
-		break;
-	default:
-		dev_err(sphy->dev, "Invalid SoC type\n");
-		return;
+	if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
+		reg = sphy->pmuregs + sphy->drv_data->devphy_reg_offset;
+		en_mask = sphy->drv_data->devphy_en_mask;
+	} else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
+		reg = sphy->pmuregs + sphy->drv_data->hostphy_reg_offset;
+		en_mask = sphy->drv_data->hostphy_en_mask;
 	}
 
 	reg_val = readl(reg);
@@ -121,7 +101,7 @@ void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
 
 	writel(reg_val, reg);
 }
-EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation);
+EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);
 
 /*
  * Configure the mode of working of usb-phy here: HOST/DEVICE.
diff --git a/drivers/usb/phy/phy-samsung-usb.h b/drivers/usb/phy/phy-samsung-usb.h
index 0336f6b..5203784 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -271,6 +271,7 @@ struct samsung_usbphy_drvdata {
 	u32 devphy_reg_offset;
 	u32 hostphy_reg_offset;
 	int (*rate_to_clksel)(struct samsung_usbphy *, unsigned long);
+	void (*set_isolation)(struct samsung_usbphy *, bool);
 };
 
 /*
@@ -323,7 +324,8 @@ static inline const struct samsung_usbphy_drvdata
 }
 
 extern int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy);
-extern void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on);
+extern void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy,
+								bool on);
 extern void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy);
 extern int samsung_usbphy_set_type(struct usb_phy *phy,
 					enum samsung_usb_phy_type phy_type);
diff --git a/drivers/usb/phy/phy-samsung-usb2.c b/drivers/usb/phy/phy-samsung-usb2.c
index 802e738..ae6da68 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -284,8 +284,8 @@ static int samsung_usb2phy_init(struct usb_phy *phy)
 	/* Disable phy isolation */
 	if (sphy->plat && sphy->plat->pmu_isolation)
 		sphy->plat->pmu_isolation(false);
-	else
-		samsung_usbphy_set_isolation(sphy, false);
+	else if (sphy->drv_data->set_isolation)
+		sphy->drv_data->set_isolation(sphy, false);
 
 	/* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
 	samsung_usbphy_cfg_sel(sphy);
@@ -342,8 +342,8 @@ static void samsung_usb2phy_shutdown(struct usb_phy *phy)
 	/* Enable phy isolation */
 	if (sphy->plat && sphy->plat->pmu_isolation)
 		sphy->plat->pmu_isolation(true);
-	else
-		samsung_usbphy_set_isolation(sphy, true);
+	else if (sphy->drv_data->set_isolation)
+		sphy->drv_data->set_isolation(sphy, true);
 
 	spin_unlock_irqrestore(&sphy->lock, flags);
 
@@ -447,6 +447,7 @@ static const struct samsung_usbphy_drvdata usb2phy_s3c64xx = {
 	.cpu_type		= TYPE_S3C64XX,
 	.devphy_en_mask		= S3C64XX_USBPHY_ENABLE,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_64xx,
+	.set_isolation		= NULL, /* TODO */
 };
 
 static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
@@ -454,6 +455,7 @@ static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
 	.devphy_en_mask		= EXYNOS_USBPHY_ENABLE,
 	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_64xx,
+	.set_isolation		= samsung_usbphy_set_isolation_4210,
 };
 
 static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
@@ -461,6 +463,7 @@ static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
 	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
 	.hostphy_reg_offset	= EXYNOS_USBHOST_PHY_CTRL_OFFSET,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
+	.set_isolation		= samsung_usbphy_set_isolation_4210,
 };
 
 #ifdef CONFIG_OF
diff --git a/drivers/usb/phy/phy-samsung-usb3.c b/drivers/usb/phy/phy-samsung-usb3.c
index c07bc32..ae232ad 100644
--- a/drivers/usb/phy/phy-samsung-usb3.c
+++ b/drivers/usb/phy/phy-samsung-usb3.c
@@ -184,7 +184,8 @@ static int samsung_usb3phy_init(struct usb_phy *phy)
 	samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
 
 	/* Disable phy isolation */
-	samsung_usbphy_set_isolation(sphy, false);
+	if (sphy->drv_data->set_isolation)
+		sphy->drv_data->set_isolation(sphy, false);
 
 	/* Initialize usb phy registers */
 	samsung_exynos5_usb3phy_enable(sphy);
@@ -221,7 +222,8 @@ static void samsung_usb3phy_shutdown(struct usb_phy *phy)
 	samsung_exynos5_usb3phy_disable(sphy);
 
 	/* Enable phy isolation */
-	samsung_usbphy_set_isolation(sphy, true);
+	if (sphy->drv_data->set_isolation)
+		sphy->drv_data->set_isolation(sphy, true);
 
 	spin_unlock_irqrestore(&sphy->lock, flags);
 
@@ -309,6 +311,7 @@ static struct samsung_usbphy_drvdata usb3phy_exynos5 = {
 	.cpu_type		= TYPE_EXYNOS5250,
 	.devphy_en_mask		= EXYNOS_USBPHY_ENABLE,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
+	.set_isolation		= samsung_usbphy_set_isolation_4210,
 };
 
 #ifdef CONFIG_OF
-- 
1.8.2.1



From t.figa at samsung.com  Thu May 16 05:57:10 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:10 +0200
Subject: [PATCH v2 5/6] usb: phy: samsung: Pass enable/disable callbacks
 through driver data
In-Reply-To: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
References: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368698231-24268-6-git-send-email-t.figa@samsung.com>

To remove unnecessary if statements, this patch introduces phy_enable
and phy_disable callbacks in driver data structure that implement
SoC-specific PHY initialization and deinitialization.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/usb/phy/phy-samsung-usb.h  |  2 ++
 drivers/usb/phy/phy-samsung-usb2.c | 16 ++++++++--------
 drivers/usb/phy/phy-samsung-usb3.c | 10 +++++-----
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/usb/phy/phy-samsung-usb.h b/drivers/usb/phy/phy-samsung-usb.h
index 5203784..31e2ec3 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -272,6 +272,8 @@ struct samsung_usbphy_drvdata {
 	u32 hostphy_reg_offset;
 	int (*rate_to_clksel)(struct samsung_usbphy *, unsigned long);
 	void (*set_isolation)(struct samsung_usbphy *, bool);
+	void (*phy_enable)(struct samsung_usbphy *);
+	void (*phy_disable)(struct samsung_usbphy *);
 };
 
 /*
diff --git a/drivers/usb/phy/phy-samsung-usb2.c b/drivers/usb/phy/phy-samsung-usb2.c
index ae6da68..b81347b 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -291,10 +291,7 @@ static int samsung_usb2phy_init(struct usb_phy *phy)
 	samsung_usbphy_cfg_sel(sphy);
 
 	/* Initialize usb phy registers */
-	if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
-		samsung_exynos5_usb2phy_enable(sphy);
-	else
-		samsung_usb2phy_enable(sphy);
+	sphy->drv_data->phy_enable(sphy);
 
 	spin_unlock_irqrestore(&sphy->lock, flags);
 
@@ -334,10 +331,7 @@ static void samsung_usb2phy_shutdown(struct usb_phy *phy)
 	}
 
 	/* De-initialize usb phy registers */
-	if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
-		samsung_exynos5_usb2phy_disable(sphy);
-	else
-		samsung_usb2phy_disable(sphy);
+	sphy->drv_data->phy_disable(sphy);
 
 	/* Enable phy isolation */
 	if (sphy->plat && sphy->plat->pmu_isolation)
@@ -448,6 +442,8 @@ static const struct samsung_usbphy_drvdata usb2phy_s3c64xx = {
 	.devphy_en_mask		= S3C64XX_USBPHY_ENABLE,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_64xx,
 	.set_isolation		= NULL, /* TODO */
+	.phy_enable		= samsung_usb2phy_enable,
+	.phy_disable		= samsung_usb2phy_disable,
 };
 
 static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
@@ -456,6 +452,8 @@ static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
 	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_64xx,
 	.set_isolation		= samsung_usbphy_set_isolation_4210,
+	.phy_enable		= samsung_usb2phy_enable,
+	.phy_disable		= samsung_usb2phy_disable,
 };
 
 static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
@@ -464,6 +462,8 @@ static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
 	.hostphy_reg_offset	= EXYNOS_USBHOST_PHY_CTRL_OFFSET,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
 	.set_isolation		= samsung_usbphy_set_isolation_4210,
+	.phy_enable		= samsung_exynos5_usb2phy_enable,
+	.phy_disable		= samsung_exynos5_usb2phy_disable,
 };
 
 #ifdef CONFIG_OF
diff --git a/drivers/usb/phy/phy-samsung-usb3.c b/drivers/usb/phy/phy-samsung-usb3.c
index ae232ad..b663353 100644
--- a/drivers/usb/phy/phy-samsung-usb3.c
+++ b/drivers/usb/phy/phy-samsung-usb3.c
@@ -65,7 +65,7 @@ static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy)
 	return reg;
 }
 
-static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
+static void samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
 {
 	void __iomem *regs = sphy->regs;
 	u32 phyparam0;
@@ -133,8 +133,6 @@ static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
 
 	phyclkrst &= ~(PHYCLKRST_PORTRESET);
 	writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
-
-	return 0;
 }
 
 static void samsung_exynos5_usb3phy_disable(struct samsung_usbphy *sphy)
@@ -188,7 +186,7 @@ static int samsung_usb3phy_init(struct usb_phy *phy)
 		sphy->drv_data->set_isolation(sphy, false);
 
 	/* Initialize usb phy registers */
-	samsung_exynos5_usb3phy_enable(sphy);
+	sphy->drv_data->phy_enable(sphy);
 
 	spin_unlock_irqrestore(&sphy->lock, flags);
 
@@ -219,7 +217,7 @@ static void samsung_usb3phy_shutdown(struct usb_phy *phy)
 	samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
 
 	/* De-initialize usb phy registers */
-	samsung_exynos5_usb3phy_disable(sphy);
+	sphy->drv_data->phy_disable(sphy);
 
 	/* Enable phy isolation */
 	if (sphy->drv_data->set_isolation)
@@ -312,6 +310,8 @@ static struct samsung_usbphy_drvdata usb3phy_exynos5 = {
 	.devphy_en_mask		= EXYNOS_USBPHY_ENABLE,
 	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
 	.set_isolation		= samsung_usbphy_set_isolation_4210,
+	.phy_enable		= samsung_exynos5_usb3phy_enable,
+	.phy_disable		= samsung_exynos5_usb3phy_disable,
 };
 
 #ifdef CONFIG_OF
-- 
1.8.2.1



From t.figa at samsung.com  Thu May 16 05:57:11 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 16 May 2013 11:57:11 +0200
Subject: [PATCH v2 6/6] usb: phy: samsung: Add support for USB 2.0 PHY on
 Exynos 4x12
In-Reply-To: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
References: <1368698231-24268-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368698231-24268-7-git-send-email-t.figa@samsung.com>

This patch adds driver data for Exynos 4x12 USB 2.0 PHY.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/usb/phy/phy-samsung-usb.h  |  1 +
 drivers/usb/phy/phy-samsung-usb2.c | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/usb/phy/phy-samsung-usb.h b/drivers/usb/phy/phy-samsung-usb.h
index 31e2ec3..585d12f 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -241,6 +241,7 @@
 enum samsung_cpu_type {
 	TYPE_S3C64XX,
 	TYPE_EXYNOS4210,
+	TYPE_EXYNOS4X12,
 	TYPE_EXYNOS5250,
 };
 
diff --git a/drivers/usb/phy/phy-samsung-usb2.c b/drivers/usb/phy/phy-samsung-usb2.c
index b81347b..381f8d4 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -177,6 +177,7 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
 		rstcon |= RSTCON_SWRST;
 		break;
 	case TYPE_EXYNOS4210:
+	case TYPE_EXYNOS4X12:
 		phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
 		rstcon |= RSTCON_SWRST;
 	default:
@@ -240,6 +241,7 @@ static void samsung_usb2phy_disable(struct samsung_usbphy *sphy)
 		phypwr |= PHYPWR_NORMAL_MASK;
 		break;
 	case TYPE_EXYNOS4210:
+	case TYPE_EXYNOS4X12:
 		phypwr |= PHYPWR_NORMAL_MASK_PHY0;
 	default:
 		break;
@@ -456,6 +458,16 @@ static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
 	.phy_disable		= samsung_usb2phy_disable,
 };
 
+static const struct samsung_usbphy_drvdata usb2phy_exynos4x12 = {
+	.cpu_type		= TYPE_EXYNOS4X12,
+	.devphy_en_mask		= EXYNOS_USBPHY_ENABLE,
+	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
+	.rate_to_clksel		= samsung_usbphy_rate_to_clksel_4x12,
+	.set_isolation		= samsung_usbphy_set_isolation_4210,
+	.phy_enable		= samsung_usb2phy_enable,
+	.phy_disable		= samsung_usb2phy_disable,
+};
+
 static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
 	.cpu_type		= TYPE_EXYNOS5250,
 	.hostphy_en_mask	= EXYNOS_USBPHY_ENABLE,
@@ -475,6 +487,9 @@ static const struct of_device_id samsung_usbphy_dt_match[] = {
 		.compatible = "samsung,exynos4210-usb2phy",
 		.data = &usb2phy_exynos4,
 	}, {
+		.compatible = "samsung,exynos4x12-usb2phy",
+		.data = &usb2phy_exynos4x12,
+	}, {
 		.compatible = "samsung,exynos5250-usb2phy",
 		.data = &usb2phy_exynos5
 	},
@@ -491,6 +506,9 @@ static struct platform_device_id samsung_usbphy_driver_ids[] = {
 		.name		= "exynos4210-usb2phy",
 		.driver_data	= (unsigned long)&usb2phy_exynos4,
 	}, {
+		.name		= "exynos4x12-usb2phy",
+		.driver_data	= (unsigned long)&usb2phy_exynos4x12,
+	}, {
 		.name		= "exynos5250-usb2phy",
 		.driver_data	= (unsigned long)&usb2phy_exynos5,
 	},
-- 
1.8.2.1



From james.hogan at imgtec.com  Thu May 16 05:56:51 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Thu, 16 May 2013 10:56:51 +0100
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <51940CAF.6010808@codeaurora.org>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
 <51940CAF.6010808@codeaurora.org>
Message-ID: <5194AD63.9020804@imgtec.com>

On 15/05/13 23:31, Stephen Boyd wrote:
> On 05/10/13 08:02, James Hogan wrote:
>> This adds a metag architecture specific clk-gate and clk-mux which
>> extends the generic ones to use global lock2 to protect the register
>> fields. It is common with metag to have an RTOS running on a different
>> thread or core with access to different bits in the same register (which
>> contain clock gate/switch bits for other clocks). Access to such
>> registers must be serialised with a global lock such as the one provided
>> by the metag architecture port in <asm/global_lock.h>
>>
>> RFC because despite extending the generic clocks there's still a bit of
>> duplicated code necessary. One alternative is to add special cases to
>> the generic clock components for when a global or callback function
>> based lock is desired instead of a spinlock, but I wasn't sure if that
>> sort of hack would really be appreciated in the generic drivers.
>>
>> Comments?
> 
> Can you please Cc the devicetree mailing list when proposing new bindings?

Erm, I think it was on Cc (devicetree-discuss at lists.ozlabs.org yeh?)

> Your patchset brings up a question I've had which is if we should be
> putting the bits and register width information in devicetree at all. On
> the one hand it's nice to not have anything in C code, just iterate over
> nodes and register clocks. On the other hand, it's the first time I've
> seen anyone put the register interface into devicetree. From what I can
> tell, the regulator bindings have put at most the register base and
> physical properties like enable-time, max voltage, etc., but not what
> bits are needed to enable/disable a regulator. Also I thought I read
> somewhere that reg properties shouldn't overlap each other, so if you
> ever have two clocks living in the same register we're going to violate
> that.

Oh, I wasn't aware of that limitation.

The SoC I'm working with has some registers full of clock enable bits (I
guess one could have a gate array component with up to 32 clock inputs
and outputs) and some registers full of clock mux switch bits (that
would get really messy to define as a block since each bit switches
between 2 parents, and some of the parents are other clock muxes in the
same block). Some registers contain a bunch of low power related bits
together, including clock enable bits in the same register as various
pinconf settings which is used by a separate pinctrl driver.

Cheers
James



From josephl at nvidia.com  Thu May 16 06:09:48 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 May 2013 18:09:48 +0800
Subject: [PATCH 1/6] ARM: tegra: add an assembly marco to check Tegra
 SoC ID
In-Reply-To: <51940FA4.6050609@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-2-git-send-email-josephl@nvidia.com>
 <51940FA4.6050609@wwwdotorg.org>
Message-ID: <1368698988.7403.25.camel@jlo-ubuntu-64.nvidia.com>

On Thu, 2013-05-16 at 06:43 +0800, Stephen Warren wrote:
> On 05/15/2013 04:27 AM, Joseph Lo wrote:
> > There are some Tegra SoC ID checking code around the low level assembly
> > code. Adding a marco to replace them. For the single image to support all
> > the Tegra series, we may also need the marco in other common code. So we
> > make it become a marco for the usage.
> 
> I'm not sure this patch doesn't obfuscate the code too much. The big
> issue I see is:
> 
> > @@ -115,13 +112,9 @@ ENTRY(__tegra_cpu_reset_handler)
> >  
> >  	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
> >  
> > -	mov32	r6, TEGRA_APB_MISC_BASE
> > -	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
> > -	and	r6, r6, #0xff00
> > -#ifdef CONFIG_ARCH_TEGRA_2x_SOC
> > -t20_check:
> > -	cmp	r6, #(0x20 << 8)
> > +	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r5
> 
> Here, we replace all the code with the new macro, ...
> 
> >  #ifdef CONFIG_ARCH_TEGRA_2x_SOC
> >  	/* Are we on Tegra20? */
> > -	cmp	r6, #(0x20 << 8)
> > +	cmp	r6, #(TEGRA20 << 8)
> 
> But here we still have to write out the cmp instructions.
> 
The marco did "cmp" once and move the soc_id into r6. But the flags may
be changed after running some other codes, we need to "cmp" again to get
the correct flag.

> It may be reasonable to create a macro to read/mask/shift the SoC ID,
> similar to the existing cpu_id macro, i.e. roughly:
> 
> /* Macro to check Tegra revision */
> +#define APB_MISC_GP_HIDREV	0x804
> +.macro tegra_soc_id base, tmp1, tmp2
> +	mov32	\tmp2, \base
> +	ldr	\tmp1, [\tmp2, #APB_MISC_GP_HIDREV]
> +	and	\tmp1, \tmp1, #0xff00
> +.endm
> 
> Also, I wonder:
> 
> (a) why the need to pass TEGRA_APB_MISC_BASE into the macro; can't the
> macro just hard-code that value since it's always the same?
> 
Because this marco will be used in virtual address space too, I need to
pass different base addr here.

> (b) Why need two registers passed to the macro. At least one of the code
> segments you've replaced with the macro uses a single register instead:
> 
> -	mov32	r6, TEGRA_APB_MISC_BASE
> -	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
> -	and	r6, r6, #0xff00
> 
> Wouldn't that be a better implementation of the macro? I don't think
> relying on \tmp2 containing "base" after the macro invocation would be a
> good idea, since that's rather like looking inside the black box.

OK. I can remove one tmp register here.




From josephl at nvidia.com  Thu May 16 06:13:17 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 May 2013 18:13:17 +0800
Subject: [PATCH 2/6] ARM: tegra: skip SCU and PL310 code when CPU is
 not Cortex-A9
In-Reply-To: <519410D7.9060201@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-3-git-send-email-josephl@nvidia.com>
 <519410D7.9060201@wwwdotorg.org>
Message-ID: <1368699197.7403.28.camel@jlo-ubuntu-64.nvidia.com>

On Thu, 2013-05-16 at 06:48 +0800, Stephen Warren wrote:
> On 05/15/2013 04:27 AM, Joseph Lo wrote:
> > For supporting single image on all Tegra series, we need to skip some HW
> > support code for Cortex-A9 only.
> 
> > diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
> 
> > +	check_cpu_part_num 0xc09, r9, r10
> > +	movweq	r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
> > +	movteq	r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
> > +	moveq	r5, #0
> > +	streq	r5, [r4, #L2X0_CTRL]
> 
> Do those conditional instructions need a Thumb iteq wrapped around them
> in order to compile in Thumb2 mode? Same comment for the other change,
> although IIRC iteq only supports 4 instructions at a time, so maybe a
> branch would be better there. Using branches might also reduce the size
> of the diff, and make the change more obvious.

IIRC, I had tested this patch series with THUMB2_KERNEL enabled. It's
OK. I can double confirm again later.

Thanks,
Joseph



From vinod.koul at intel.com  Thu May 16 05:40:14 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 15:10:14 +0530
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <20130516072557.GD3269@gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
 <20130516063546.GD14863@intel.com>
 <20130516072557.GD3269@gmail.com>
Message-ID: <20130516094014.GJ14863@intel.com>

On Thu, May 16, 2013 at 08:25:57AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
> 
> > On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
> > > All configuration left in d40_phy_cfg() is runtime configurable and
> > > there is already a call into it from d40_runtime_config(), so let's
> > > rely on that.
> > > 
> > > Acked-by: Vinod Koul <vnod.koul at intel.com>
> > That needs up update!
> 
> Ah, where did I get that from that?
> 
> Was that my mistake, or was this in the MAINTAINERS file?
Certainly not in MAINTAINERS file :)

--
~Vinod


From vinod.koul at intel.com  Thu May 16 05:41:57 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 16 May 2013 15:11:57 +0530
Subject: [PATCH 34/39] dmaengine: ste_dma40: Convert data_width from
 register bit format to value
In-Reply-To: <20130516073553.GF3269@gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-35-git-send-email-lee.jones@linaro.org>
 <20130516063244.GA14863@intel.com>
 <20130516073553.GF3269@gmail.com>
Message-ID: <20130516094157.GK14863@intel.com>

On Thu, May 16, 2013 at 08:35:53AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
> 
> > On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> > > +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> > > +{
> > > +	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> > > +		return STEDMA40_ESIZE_8_BIT;
> > > +	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> > > +		return STEDMA40_ESIZE_16_BIT;
> > > +	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> > > +		return STEDMA40_ESIZE_64_BIT;
> > > +	else
> > > +		return STEDMA40_ESIZE_32_BIT;
> > > +}
> > > +
> > Switch looks better for this and how about
> > 	return fls(width);
> > 
> > as your defines are 0...3 and dmaengine define 1,2,..8 for same thing
> > then you can also get rid of STEDMA40_XXX_WIDTH macros!
> 
> I like it.
> 
> Will you let me do it as a follow-up patch?
Okay...

--
~Vinod


From 21cnbao at gmail.com  Thu May 16 06:25:39 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 16 May 2013 18:25:39 +0800
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <20130516093846.GA2927@katana>
References: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
 <20130516093846.GA2927@katana>
Message-ID: <CAGsJ_4zVOF8-g=emEGgP3atxkWdxMaQQiVZrZkht_WueTriSnw@mail.gmail.com>

2013/5/16 Wolfram Sang <wsa at the-dreams.de>:
> On Thu, May 16, 2013 at 10:50:07AM +0800, Barry Song wrote:
>> From: Xiaomeng Hou <Xiaomeng.Hou at csr.com>
>>
>> if we initilize i2c bus by module_init, there are some devices which want
>> initialization earlier than i2c and could not do that in time, so move i2c
>> driver initilization to subsys_initcall and make i2c ready before devices
>> init.
>>
>> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou at csr.com>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>
> What about deferred probing?

deferred probing could work but could not work for automative.
what we really want is that devices begin to work as early as
possible. we want i2c clients like lcd, camera begin to show images as
early as possible as an automative requirement.

-barry


From arnd at arndb.de  Thu May 16 06:29:28 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 May 2013 12:29:28 +0200
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <1368684648-20826-3-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-3-git-send-email-b35083@freescale.com>
Message-ID: <5396520.ZTuSn9S4Vd@wuerfel>

On Thursday 16 May 2013 14:10:46 Jingchang Lu wrote:

> index a402248..b9c01a1 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -835,6 +835,21 @@ config SOC_IMX6SL
>  	help
>  	  This enables support for Freescale i.MX6 SoloLite processor.
>  
> +config SOC_MVF600
> +	bool "Vybrid Family MVF600 support"
> +	select CPU_V7
> +	select ARM_GIC
> +	select CLKSRC_OF
> +	select PINCTRL
> +	select PINCTRL_MVF600
> +	select MVF600_PIT_TIMER
> +	select PL310_ERRATA_588369 if CACHE_PL310
> +	select PL310_ERRATA_727915 if CACHE_PL310
> +	select PL310_ERRATA_769419 if CACHE_PL310
> +
> +	help
> +	  This enable support for Freescale Vybrid MVF600 processor.
> +
>  endif

Shouldn't that 'depends on ARCH_MULTI_V7'?

Can you describe how much Vybrid is actually like MXC? Do you actually
use most of the mach-imx code?

> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index 208e76f..55cdba0 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -70,6 +70,7 @@ extern int mx51_clocks_init_dt(void);
>  extern int mx53_clocks_init_dt(void);
>  extern int mx6q_clocks_init(void);
>  extern int imx6sl_clocks_init(void);
> +extern int mvf600_clocks_init(void);
>  extern struct platform_device *mxc_register_gpio(char *name, int id,
>  	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
>  extern void mxc_set_cpu_type(unsigned int type);

This hunk belongs into the first patch, right?

Actually I think you should move that driver to drivers/clk and use
of_clk_init(NULL) to initialize it.

> +static void __init mvf600_init_machine(void)
> +{
> +	mxc_arch_reset_init_dt();

I don't see the mxc_arch_reset_init_dt function in 3.10-rc1. Where does it
get introduced?

It would be nice if we could integrate that into the watchdog driver,
so that driver just registers a pm_restart function when it gets loaded.
It is a rather small driver, so it would not hurt to always load it.

> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}

It would be nicer if you could just use the default init_machine.

> +static void __init mvf600_init_irq(void)
> +{
> +	struct device_node *np;
> +	void __iomem *mscm_base;
> +	int i;
> +
> +	l2x0_of_init(0, ~0UL);
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm");
> +	mscm_base = of_iomap(np, 0);
> +	if (!mscm_base)
> +		return;
> +
> +	/* route all shared peripheral interrupts to CP0 */
> +	for (i = 0; i < 111; i++)
> +		__raw_writew(1, mscm_base + 0x880 + 2 * i);
> +
> +	iounmap(mscm_base);
> +
> +	irqchip_init();
> +}

What is the mscm? Shouldn't the boot loader have set this up correctly?
If you can remove that code from the kernel, you can use the default
irqchip_init call.

> +static void __init mvf600_init_time(void)
> +{
> +	mvf600_clocks_init();
> +	clocksource_of_init();
> +}

I would like to call of_clk_init(NULL) unconditionally on all machines
in 3.11, so this function could also go away.

> +static const char *mvf600_dt_compat[] __initdata = {
> +	"fsl,mvf600",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)")
> +	.init_irq	= mvf600_init_irq,
> +	.init_time	= mvf600_init_time,
> +	.init_machine   = mvf600_init_machine,
> +	.dt_compat	= mvf600_dt_compat,
> +	.restart	= mxc_restart,
> +MACHINE_END

If we can do all of the above, we can actually remove the entire machine
descriptor here, since all its members are NULL.

	Arnd


From 21cnbao at gmail.com  Thu May 16 06:31:12 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 16 May 2013 18:31:12 +0800
Subject: [alsa-devel] [PATCH] ASoC: dfbmcs320: make the driver common for
 other BT modules
In-Reply-To: <5194AC3C.4080206@metafoo.de>
References: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>
 <5194AC3C.4080206@metafoo.de>
Message-ID: <CAGsJ_4yoXj+e7A20SM5+ctLvE2QRTp0bzDeKfCZSUHTO8BPq5A@mail.gmail.com>

2013/5/16 Lars-Peter Clausen <lars at metafoo.de>:
> On 05/16/2013 08:53 AM, Barry Song wrote:
>> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
>> we don't want everyone to have a seperate codec driver. anyway, the
>> feature of Bluetooth handsfree is same on all platforms, so this patch
>> makes the DFBM-CS320 driver become a common BT handsfree driver.
> [...]
>> -static struct platform_driver dfmcs320_driver = {
>> +static struct platform_driver bt_handsfree_driver = {
>>       .driver = {
>> -             .name = "dfbmcs320",
>> +             .name = "bt-handsfree",
>>               .owner = THIS_MODULE,
>
> In my opinion it's a good idea to keep a platform_id list of all the
> supported devices.

i have no idea how many bluetooth handsfree module exist in the world.
there must be many. actually the driver works for almost all BT
handsfree.
so my basic idea is making the codes as common as possible.

and i also want to add dt compatible in this driver, a generic
compatible string can be "bluetooth, handsfree", but users can add
specific string in its board dts like:

compatible = "delta, dfbmcs320", "bluetooth, handsfree";

so the driver will still work for  "delta, dfbmcs320".

>
>>       },
>> -     .probe = dfbmcs320_probe,
>> -     .remove = dfbmcs320_remove,
>> +     .probe = bt_handsfree_probe,
>> +     .remove = bt_handsfree_remove,
>>  };
>>
>> -module_platform_driver(dfmcs320_driver);
>> +module_platform_driver(bt_handsfree_driver);

-barry


From josephl at nvidia.com  Thu May 16 06:35:33 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 May 2013 18:35:33 +0800
Subject: [PATCH 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <519412E9.2080905@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-4-git-send-email-josephl@nvidia.com>
 <519412E9.2080905@wwwdotorg.org>
Message-ID: <1368700533.7403.47.camel@jlo-ubuntu-64.nvidia.com>

On Thu, 2013-05-16 at 06:57 +0800, Stephen Warren wrote:
> On 05/15/2013 04:27 AM, Joseph Lo wrote:
> > Tegra114 is an ARM Cortex-A15 based SoC and some of the flow controller
> 
> I don't think the CPU type is the issue here. The issue is simply that
> Tegra114's flow controller is different. Mentioning the CPU type seems
> misleading.
> 
> > hardware behavior and configurations are different with other Tegra series.
> > We fix the common resume function of tegra_resume to make it can work on
> > Tegra114 by checking SoC ID. And also checking CPU primary part number to
> > isolate the support code for Cortex A9 and A15.
> 
> > diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
> 
> > -#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> > +#ifndef CONFIG_ARCH_TEGRA_2x_SOC
> >  	/* Are we on Tegra20? */
> >  	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r7
> >  	beq	1f				@ Yes
> >  	/* Clear the flow controller flags for this CPU. */
> > -	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
> > -	ldr	r1, [r2]
> > +	cpu_to_csr_req r1, r0
> 
> Where is cpu_to_csr_req defined? grep can't find it in next-20130513,
> and I don't see it added in this series.
> 
The cpu_to_csr_reg macro was defined in "sleep.h". I was used to
translate the bit offset of CPU number in CSR register. The code here
was used for CPU0 on Tegra30 only before. Because the Tegra114 had more
advance CPU power control. Each Core need run through here when power
gate resume.

> This presumably changes behaviour on Tegra30; will this cause problems?
> 
No, I had verified on Tegra20, Tegra30 and Tegra114 of this series.

> > +	mov32	r2, TEGRA_FLOW_CTRL_BASE
> > +	ldr	r1, [r2, r1]
> >  	/* Clear event & intr flag */
> >  	orr	r1, r1, \
> >  		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
> > -	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
> > +	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, & bitmaps
> 
> What does this change do; does the commend need updating to describe the
> new bits that are set?
It clear the some extensions for CPU power control on Tegra114.





From gleb at redhat.com  Thu May 16 06:42:45 2013
From: gleb at redhat.com (Gleb Natapov)
Date: Thu, 16 May 2013 13:42:45 +0300
Subject: [PATCH v3 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <1368538262-25546-3-git-send-email-marc.zyngier@arm.com>
References: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
 <1368538262-25546-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130516104245.GR26453@redhat.com>

On Tue, May 14, 2013 at 02:31:02PM +0100, Marc Zyngier wrote:
> As requested by the KVM maintainers, remove the addprefix used to
> refer to the main KVM code from the arch code, and replace it with
> a KVM variable that does the same thing.
> 
Thanks, I will wait till next week for arch maintainers to comment and apply.

> Cc: Paolo Bonzini <pbonzini at redhat.com>
> Cc: Gleb Natapov <gleb at redhat.com>
> Cc: Christoffer Dall <cdall at cs.columbia.edu>
> Acked-by: Xiantao Zhang <xiantao.zhang at intel.com>
> Cc: Tony Luck <tony.luck at intel.com>
> Cc: Fenghua Yu <fenghua.yu at intel.com>
> Cc: Alexander Graf <agraf at suse.de>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: Christian Borntraeger <borntraeger at de.ibm.com>
> Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/kvm/Makefile     |  2 +-
>  arch/ia64/kvm/Makefile    |  7 ++++---
>  arch/powerpc/kvm/Makefile | 13 +++++++------
>  arch/s390/kvm/Makefile    |  3 ++-
>  arch/x86/kvm/Makefile     | 13 +++++++------
>  5 files changed, 21 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
> index 9184a49..d99bee4 100644
> --- a/arch/arm/kvm/Makefile
> +++ b/arch/arm/kvm/Makefile
> @@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
>  AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
>  
>  KVM := ../../../virt/kvm
> -kvm-arm-y = $(addprefix $(KVM)/, kvm_main.o coalesced_mmio.o)
> +kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
>  
>  obj-y += kvm-arm.o init.o interrupts.o
>  obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
> diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
> index 1a40537..18e45ec 100644
> --- a/arch/ia64/kvm/Makefile
> +++ b/arch/ia64/kvm/Makefile
> @@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
>  
>  ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
>  asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
> +KVM := ../../../virt/kvm
>  
> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
> -		coalesced_mmio.o irq_comm.o)
> +common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
> +		$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
>  
>  ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
> -common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
> +common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
>  endif
>  
>  kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
> diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
> index 422de3f..008cd85 100644
> --- a/arch/powerpc/kvm/Makefile
> +++ b/arch/powerpc/kvm/Makefile
> @@ -5,9 +5,10 @@
>  subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
>  
>  ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
> +KVM := ../../../virt/kvm
>  
> -common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
> -						eventfd.o)
> +common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
> +		$(KVM)/eventfd.o
>  
>  CFLAGS_44x_tlb.o  := -I.
>  CFLAGS_e500_mmu.o := -I.
> @@ -53,7 +54,7 @@ kvm-e500mc-objs := \
>  kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
>  
>  kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
> -	../../../virt/kvm/coalesced_mmio.o \
> +	$(KVM)/coalesced_mmio.o \
>  	fpu.o \
>  	book3s_paired_singles.o \
>  	book3s_pr.o \
> @@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
>  	book3s_xics.o
>  
>  kvm-book3s_64-module-objs := \
> -	../../../virt/kvm/kvm_main.o \
> -	../../../virt/kvm/eventfd.o \
> +	$(KVM)/kvm_main.o \
> +	$(KVM)/eventfd.o \
>  	powerpc.o \
>  	emulate.o \
>  	book3s.o \
> @@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
>  kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
>  
>  kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
> -kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
> +kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
>  
>  kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
>  
> diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
> index 8fe9d65..40b4c64 100644
> --- a/arch/s390/kvm/Makefile
> +++ b/arch/s390/kvm/Makefile
> @@ -6,7 +6,8 @@
>  # it under the terms of the GNU General Public License (version 2 only)
>  # as published by the Free Software Foundation.
>  
> -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
> +KVM := ../../../virt/kvm
> +common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
>  
>  ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
>  
> diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
> index d609e1d..bf4fb04 100644
> --- a/arch/x86/kvm/Makefile
> +++ b/arch/x86/kvm/Makefile
> @@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
>  CFLAGS_svm.o := -I.
>  CFLAGS_vmx.o := -I.
>  
> -kvm-y			+= $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
> -				coalesced_mmio.o irq_comm.o eventfd.o \
> -				irqchip.o)
> -kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(addprefix ../../../virt/kvm/, \
> -				assigned-dev.o iommu.o)
> -kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(addprefix ../../../virt/kvm/, async_pf.o)
> +KVM := ../../../virt/kvm
> +
> +kvm-y			+= $(KVM)/kvm_main.o $(KVM)/ioapic.o \
> +				$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o \
> +				$(KVM)/eventfd.o $(KVM)/irqchip.o
> +kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)	+= $(KVM)/assigned-dev.o $(KVM)/iommu.o
> +kvm-$(CONFIG_KVM_ASYNC_PF)	+= $(KVM)/async_pf.o
>  
>  kvm-y			+= x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
>  			   i8254.o cpuid.o pmu.o
> -- 
> 1.8.2.3
> 

--
			Gleb.


From laurent.pinchart at ideasonboard.com  Thu May 16 06:55:00 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 16 May 2013 12:55 +0200
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <Pine.LNX.4.64.1305160951040.21125@axis700.grange>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <Pine.LNX.4.64.1305160951040.21125@axis700.grange>
Message-ID: <1483674.dsLuiHpOf9@avalon>

Hi Guennadi,

On Thursday 16 May 2013 09:57:20 Guennadi Liakhovetski wrote:
> On Wed, 15 May 2013, Laurent Pinchart wrote:
> > Add GPIO controller nodes to the r8a7790 core device tree.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> > ---
> > 
> >  arch/arm/boot/dts/r8a7790.dtsi | 54 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi
> > b/arch/arm/boot/dts/r8a7790.dtsi index ee21061..b5fe51da 100644
> > --- a/arch/arm/boot/dts/r8a7790.dtsi
> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
> > @@ -44,6 +44,60 @@
> >  		};
> >  	};
> > 
> > +	gpio0: gpio at ffc40000 {
> > +		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
> > +		reg = <0xffc40000 0x2c>;
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <0 4 0x4>;
> > +		#gpio-cells = <2>;
> > +		gpio-controller;
> > +	};
> 
> I'm testing your patches on Lager and GPIOs don't seem to get registered:
> 
> / # ls /sys/class/gpio/
> export    unexport
> / #
> 
> And this is easy to trace back: sh_pfc_probe() calls
> sh_pfc_register_gpiochip(), where a check
> 
> 	if (pfc->info->data_regs == NULL)
> 		return 0;
> 
> successfully fails GPIO initialisation :) Is this known and there are
> still some pieces missing, or you weren't aware of this?

GPIOs are handled by the gpio-rcar driver on R8A7790, not by the sh-pfc 
driver.

-- 
Regards,

Laurent Pinchart



From lee.jones at linaro.org  Thu May 16 06:59:59 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 11:59:59 +0100
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <20130516094014.GJ14863@intel.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
 <20130516063546.GD14863@intel.com>
 <20130516072557.GD3269@gmail.com>
 <20130516094014.GJ14863@intel.com>
Message-ID: <20130516105959.GI3269@gmail.com>

On Thu, 16 May 2013, Vinod Koul wrote:

> On Thu, May 16, 2013 at 08:25:57AM +0100, Lee Jones wrote:
> > On Thu, 16 May 2013, Vinod Koul wrote:
> > 
> > > On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
> > > > All configuration left in d40_phy_cfg() is runtime configurable and
> > > > there is already a call into it from d40_runtime_config(), so let's
> > > > rely on that.
> > > > 
> > > > Acked-by: Vinod Koul <vnod.koul at intel.com>
> > > That needs up update!
> > 
> > Ah, where did I get that from that?
> > 
> > Was that my mistake, or was this in the MAINTAINERS file?
> Certainly not in MAINTAINERS file :)

My bad then, sorry.

Linus,

Would you be kind enough to fix it please, as it's in your tree now.
-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From borntraeger at de.ibm.com  Thu May 16 07:00:21 2013
From: borntraeger at de.ibm.com (Christian Borntraeger)
Date: Thu, 16 May 2013 13:00:21 +0200
Subject: [PATCH v3 2/2] KVM: get rid of $(addprefix ../../../virt/kvm/,
 ...) in Makefiles
In-Reply-To: <1368538262-25546-3-git-send-email-marc.zyngier@arm.com>
References: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
 <1368538262-25546-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <5194BC45.6070103@de.ibm.com>

On 14/05/13 15:31, Marc Zyngier wrote:
> As requested by the KVM maintainers, remove the addprefix used to
> refer to the main KVM code from the arch code, and replace it with
> a KVM variable that does the same thing.
> 
> Cc: Paolo Bonzini <pbonzini at redhat.com>
> Cc: Gleb Natapov <gleb at redhat.com>
> Cc: Christoffer Dall <cdall at cs.columbia.edu>
> Acked-by: Xiantao Zhang <xiantao.zhang at intel.com>
> Cc: Tony Luck <tony.luck at intel.com>
> Cc: Fenghua Yu <fenghua.yu at intel.com>
> Cc: Alexander Graf <agraf at suse.de>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: Christian Borntraeger <borntraeger at de.ibm.com>

s390 part:
Tested-by: Christian Borntraeger <borntraeger at de.ibm.com>

> Cc: Cornelia Huck <cornelia.huck at de.ibm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/kvm/Makefile     |  2 +-
>  arch/ia64/kvm/Makefile    |  7 ++++---
>  arch/powerpc/kvm/Makefile | 13 +++++++------
>  arch/s390/kvm/Makefile    |  3 ++-
>  arch/x86/kvm/Makefile     | 13 +++++++------
>  5 files changed, 21 insertions(+), 17 deletions(-)



From steve.capper at linaro.org  Thu May 16 07:06:34 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 16 May 2013 12:06:34 +0100
Subject: [PATCH] ARM: remove the .vm_mm value from gate_vma.
Message-ID: <1368702394-1737-1-git-send-email-steve.capper@linaro.org>

If one reads /proc/$PID/smaps, the mmap_sem belonging to the
address space of the task being examined is locked for reading.
All the pages of the vmas belonging to the task's address space
are then walked with this lock held.

If a gate_vma is present in the architecture, it too is examined
by the fs/proc/task_mmu.c code. As gate_vma doesn't belong to the
address space of the task though, its pages are not walked.

A recent cleanup (commit f6604efe) of the gate_vma initialisation
code set the vm_mm value to &init_mm. Unfortunately a non-NULL
vm_mm value in the gate_vma will cause the task_mmu code to attempt
to walk the pages of the gate_vma (with no mmap-sem lock held). If
one enables Transparent Huge Page support and vm debugging, this
will then cause OOPses as pmd_trans_huge_lock is called without
mmap_sem being locked.

This patch removes the .vm_mm value from gate_vma, restoring the
original behaviour of the task_mmu code.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm/kernel/process.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..282de48 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -411,7 +411,6 @@ static struct vm_area_struct gate_vma = {
 	.vm_start	= 0xffff0000,
 	.vm_end		= 0xffff0000 + PAGE_SIZE,
 	.vm_flags	= VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
-	.vm_mm		= &init_mm,
 };
 
 static int __init gate_vma_init(void)
-- 
1.8.1.4



From mst at redhat.com  Thu May 16 07:07:33 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:07:33 +0300
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
Message-ID: <cover.1368702323.git.mst@redhat.com>

This improves the might_fault annotations used
by uaccess routines:

1. The only reason uaccess routines might sleep
   is if they fault. Make this explicit for
   all architectures.
2. Accesses (e.g through socket ops) to kernel memory
   with KERNEL_DS like net/sunrpc does will never sleep.
   Remove an unconditinal might_sleep in the inline
   might_fault in kernel.h
   (used when PROVE_LOCKING is not set).
3. Accesses with pagefault_disable return EFAULT
   but won't cause caller to sleep.
   Check for that and avoid might_sleep when
   PROVE_LOCKING is set.

I'd like these changes to go in for the benefit of
the vhost driver where we want to call socket ops
under a spinlock, and fall back on slower thread handler
on error.

Please review, and consider for 3.11.


If the changes look good, what's the best way to merge them?
Maybe core/locking makes sense?

Note on arch code updates:
I tested x86_64 code.
Other architectures were build-tested.
I don't have cross-build environment for arm64, tile, microblaze and
mn10300 architectures. The changes look safe enough
but would appreciate review/acks from arch maintainers.

Version 1 of this change was titled
	x86: uaccess s/might_sleep/might_fault/


Changes from v1:
	add more architectures
	fix might_fault() scheduling differently depending
	on CONFIG_PROVE_LOCKING, as suggested by Ingo


Michael S. Tsirkin (10):
  asm-generic: uaccess s/might_sleep/might_fault/
  arm64: uaccess s/might_sleep/might_fault/
  frv: uaccess s/might_sleep/might_fault/
  m32r: uaccess s/might_sleep/might_fault/
  microblaze: uaccess s/might_sleep/might_fault/
  mn10300: uaccess s/might_sleep/might_fault/
  powerpc: uaccess s/might_sleep/might_fault/
  tile: uaccess s/might_sleep/might_fault/
  x86: uaccess s/might_sleep/might_fault/
  kernel: might_fault does not imply might_sleep

 arch/arm64/include/asm/uaccess.h      |  4 ++--
 arch/frv/include/asm/uaccess.h        |  4 ++--
 arch/m32r/include/asm/uaccess.h       | 12 ++++++------
 arch/microblaze/include/asm/uaccess.h |  6 +++---
 arch/mn10300/include/asm/uaccess.h    |  4 ++--
 arch/powerpc/include/asm/uaccess.h    | 16 ++++++++--------
 arch/tile/include/asm/uaccess.h       |  2 +-
 arch/x86/include/asm/uaccess_64.h     |  2 +-
 include/asm-generic/uaccess.h         | 10 +++++-----
 include/linux/kernel.h                |  1 -
 mm/memory.c                           | 14 +++++++++-----
 11 files changed, 39 insertions(+), 36 deletions(-)

Thanks,

-- 
MST


From mst at redhat.com  Thu May 16 07:10:14 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:10:14 +0300
Subject: [PATCH v2 02/10] arm64: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <90a2283bb84b6ce77c9966d76dbceb5c7edffd18.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/arm64/include/asm/uaccess.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 008f848..edb3d5c 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -166,7 +166,7 @@ do {									\
 
 #define get_user(x, ptr)						\
 ({									\
-	might_sleep();							\
+	might_fault();							\
 	access_ok(VERIFY_READ, (ptr), sizeof(*(ptr))) ?			\
 		__get_user((x), (ptr)) :				\
 		((x) = 0, -EFAULT);					\
@@ -227,7 +227,7 @@ do {									\
 
 #define put_user(x, ptr)						\
 ({									\
-	might_sleep();							\
+	might_fault();							\
 	access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) ?		\
 		__put_user((x), (ptr)) :				\
 		-EFAULT;						\
-- 
MST



From moinejf at free.fr  Thu May 16 07:12:33 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Thu, 16 May 2013 13:12:33 +0200
Subject: [PATCH] ARM: dove: declare all device IDs for module loading
Message-ID: <20130516131233.30145f82@armhf>

When the si5351 driver is a kernel module, it is loaded into memory
from its i2c device IDs, but not from its DT compatible properties.

This patch declares the i2c device IDs of all chip variants.

Signed-off-by: Jean-Francois Moine <moinejf at free.fr>
--- 
 drivers/clk/clk-si5351.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 8927284..9ebdddd 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1490,7 +1490,10 @@ static int si5351_i2c_probe(struct i2c_client *client,
 }
 
 static const struct i2c_device_id si5351_i2c_ids[] = {
-	{ "silabs,si5351", 0 },
+	{ "si5351a", 0 },
+	{ "si5351a-msop", 0 },
+	{ "si5351b", 0 },
+	{ "si5351c", 0 },
 	{ }
 };
 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);


-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From mst at redhat.com  Thu May 16 07:10:48 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:10:48 +0300
Subject: [PATCH v2 03/10] frv: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <89d860b7fb23b35e6a15beda9df6ebccf820a2f6.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/frv/include/asm/uaccess.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/frv/include/asm/uaccess.h b/arch/frv/include/asm/uaccess.h
index 0b67ec5..3ac9a59 100644
--- a/arch/frv/include/asm/uaccess.h
+++ b/arch/frv/include/asm/uaccess.h
@@ -280,14 +280,14 @@ extern long __memcpy_user(void *dst, const void *src, unsigned long count);
 static inline unsigned long __must_check
 __copy_to_user(void __user *to, const void *from, unsigned long n)
 {
-       might_sleep();
+       might_fault();
        return __copy_to_user_inatomic(to, from, n);
 }
 
 static inline unsigned long
 __copy_from_user(void *to, const void __user *from, unsigned long n)
 {
-       might_sleep();
+       might_fault();
        return __copy_from_user_inatomic(to, from, n);
 }
 
-- 
MST



From mst at redhat.com  Thu May 16 07:11:04 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:11:04 +0300
Subject: [PATCH v2 04/10] m32r: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <8b99c8a5fb9dc4ee9a39f96ecb3b9c02c97a8ba2.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/m32r/include/asm/uaccess.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/m32r/include/asm/uaccess.h b/arch/m32r/include/asm/uaccess.h
index 1c7047b..84fe7ba 100644
--- a/arch/m32r/include/asm/uaccess.h
+++ b/arch/m32r/include/asm/uaccess.h
@@ -216,7 +216,7 @@ extern int fixup_exception(struct pt_regs *regs);
 ({									\
 	long __gu_err = 0;						\
 	unsigned long __gu_val;						\
-	might_sleep();							\
+	might_fault();							\
 	__get_user_size(__gu_val,(ptr),(size),__gu_err);		\
 	(x) = (__typeof__(*(ptr)))__gu_val;				\
 	__gu_err;							\
@@ -227,7 +227,7 @@ extern int fixup_exception(struct pt_regs *regs);
 	long __gu_err = -EFAULT;					\
 	unsigned long __gu_val = 0;					\
 	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);		\
-	might_sleep();							\
+	might_fault();							\
 	if (access_ok(VERIFY_READ,__gu_addr,size))			\
 		__get_user_size(__gu_val,__gu_addr,(size),__gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;				\
@@ -295,7 +295,7 @@ do {									\
 #define __put_user_nocheck(x,ptr,size)					\
 ({									\
 	long __pu_err;							\
-	might_sleep();							\
+	might_fault();							\
 	__put_user_size((x),(ptr),(size),__pu_err);			\
 	__pu_err;							\
 })
@@ -305,7 +305,7 @@ do {									\
 ({									\
 	long __pu_err = -EFAULT;					\
 	__typeof__(*(ptr)) __user *__pu_addr = (ptr);			\
-	might_sleep();							\
+	might_fault();							\
 	if (access_ok(VERIFY_WRITE,__pu_addr,size))			\
 		__put_user_size((x),__pu_addr,(size),__pu_err);		\
 	__pu_err;							\
@@ -597,7 +597,7 @@ unsigned long __generic_copy_from_user(void *, const void __user *, unsigned lon
  */
 #define copy_to_user(to,from,n)				\
 ({							\
-	might_sleep();					\
+	might_fault();					\
 	__generic_copy_to_user((to),(from),(n));	\
 })
 
@@ -638,7 +638,7 @@ unsigned long __generic_copy_from_user(void *, const void __user *, unsigned lon
  */
 #define copy_from_user(to,from,n)			\
 ({							\
-	might_sleep();					\
+	might_fault();					\
 	__generic_copy_from_user((to),(from),(n));	\
 })
 
-- 
MST



From mst at redhat.com  Thu May 16 07:11:19 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:11:19 +0300
Subject: [PATCH v2 05/10] microblaze: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <b6ae099df81bf07ad812189a0fe83ae3ebde9306.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/microblaze/include/asm/uaccess.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index efe59d8..2fc8bf7 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -145,7 +145,7 @@ static inline unsigned long __must_check __clear_user(void __user *to,
 static inline unsigned long __must_check clear_user(void __user *to,
 							unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	if (unlikely(!access_ok(VERIFY_WRITE, to, n)))
 		return n;
 
@@ -371,7 +371,7 @@ extern long __user_bad(void);
 static inline long copy_from_user(void *to,
 		const void __user *from, unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	if (access_ok(VERIFY_READ, from, n))
 		return __copy_from_user(to, from, n);
 	return n;
@@ -385,7 +385,7 @@ static inline long copy_from_user(void *to,
 static inline long copy_to_user(void __user *to,
 		const void *from, unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	if (access_ok(VERIFY_WRITE, to, n))
 		return __copy_to_user(to, from, n);
 	return n;
-- 
MST



From mst at redhat.com  Thu May 16 07:12:35 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:12:35 +0300
Subject: [PATCH v2 06/10] mn10300: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <affedb5f30410296ad0bb43a69158b38e32378ea.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/mn10300/include/asm/uaccess.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mn10300/include/asm/uaccess.h b/arch/mn10300/include/asm/uaccess.h
index 780560b..107508a 100644
--- a/arch/mn10300/include/asm/uaccess.h
+++ b/arch/mn10300/include/asm/uaccess.h
@@ -471,13 +471,13 @@ extern unsigned long __generic_copy_from_user(void *, const void __user *,
 
 #define __copy_to_user(to, from, n)			\
 ({							\
-	might_sleep();					\
+	might_fault();					\
 	__copy_to_user_inatomic((to), (from), (n));	\
 })
 
 #define __copy_from_user(to, from, n)			\
 ({							\
-	might_sleep();					\
+	might_fault();					\
 	__copy_from_user_inatomic((to), (from), (n));	\
 })
 
-- 
MST



From josephl at nvidia.com  Thu May 16 07:14:22 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 May 2013 19:14:22 +0800
Subject: [PATCH 6/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <5194162D.7010007@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-7-git-send-email-josephl@nvidia.com>
 <5194162D.7010007@wwwdotorg.org>
Message-ID: <1368702862.7403.86.camel@jlo-ubuntu-64.nvidia.com>

On Thu, 2013-05-16 at 07:11 +0800, Stephen Warren wrote:
> On 05/15/2013 04:27 AM, Joseph Lo wrote:
> > The Tegra114 is a quad cores SoC. Each core can be hotplugged including
> > CPU0. The hotplug sequence can be controlled by setting event trigger in
> > flow controller. Then the flow controller will take care all the power
> > sequence that include CPU up and down.
> 
> > diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> 
> > +obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= sleep-tegra30.o
> 
> CONFIG_ARCH_TEGRA_3x_SOC also adds that to obj-y. Will including it
> twice cause problems?
> 
Looks the compiler can take care of this. I didn't see any problem here.

> > diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
> 
> >   *	  CPU boot vector when restarting the a CPU following
> >   *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
> >   *	  re-enabling sdram.
> > + *
> > + *	r6: SoC ID << 8
> 
> I meant to ask in patch 1: Perhaps the macro could do a >>8 so that code
> can compare directly against the SoC IDs instead of having to compare
> against shifted values.
> 
That's more easy to read the code indeed. Will do.

> > +	tegra_check_soc_id TEGRA114, TEGRA_APB_MISC_BASE, r6, r7
> > +	beq	no_cpu0_chk
> 
> Does that need a THUMB(it ...) added? Same elsewhere.
> 
Will double confirm again later.

> > +	cmp	r6, #(TEGRA114 <<8)
> 
> Needs a space after <<.
> 
> > diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
> 
> > @@ -45,12 +46,17 @@ ENDPROC(tegra30_hotplug_shutdown)
> >   * and powergates it -- flags (in R0) indicate the request type.
> >   * Must never be called for CPU 0.
> 
> That comment is wrong now, I think.
Only true for Tegra30 now. Will fix.

> 
> >  	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
> > +	beq	flow_ctrl_setting_for_lp2
> > +
> > +	/* flow controller set up for hotplug */
> > +	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
> > +	b	flow_ctrl_done
> > +flow_ctrl_setting_for_lp2:
> > +	/* flow controller set up for LP2 */
> > +	cmp	r10, #(TEGRA30 << 8)
> >  	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
> 
> Do you need e.g. "movne r3, #0" or similar here? Otherwise, I think r3
> ends up not being initialized.

Yes, I will add the code when I add LP2 support for Tegra114 later.
Currently the LP2 code flow only for Tegra30, so it's OK.

> 
> > -	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
> > +flow_ctrl_done:
> > +	cmp	r10, #(TEGRA30 << 8)
> >  	str	r3, [r2]
> 
> I wonder whether creating a separate tegra114_cpu_shutdown() wouldn't be
> better, to avoid all the runtime conditional code.

I personally think the conditional code is OK. And the ARM CPU also had
hardware for branch detection also.

I had finished some further features for both Tegra30 and Tegra114. And
most of the code here can be shared each other at least until now I
could see. Once I see if there is a significant difference, then I would
prepare maintain the code separately too.



From wsa at the-dreams.de  Thu May 16 07:15:36 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Thu, 16 May 2013 13:15:36 +0200
Subject: [PATCH 08/33] drivers/i2c/busses: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
Message-ID: <1368702961-4325-9-git-send-email-wsa@the-dreams.de>

devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
---
 drivers/i2c/busses/i2c-s3c2410.c |    5 -----
 drivers/i2c/busses/i2c-sirf.c    |    6 ------
 drivers/i2c/busses/i2c-tegra.c   |    5 -----
 3 files changed, 16 deletions(-)

diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 6e8ee92..cab1c91 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -1082,11 +1082,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
 	/* map the registers */
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res == NULL) {
-		dev_err(&pdev->dev, "cannot find IO resource\n");
-		return -ENOENT;
-	}
-
 	i2c->regs = devm_ioremap_resource(&pdev->dev, res);
 
 	if (IS_ERR(i2c->regs))
diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c
index 5a7ad24..a63c7d5 100644
--- a/drivers/i2c/busses/i2c-sirf.c
+++ b/drivers/i2c/busses/i2c-sirf.c
@@ -303,12 +303,6 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
 	adap->class = I2C_CLASS_HWMON;
 
 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (mem_res == NULL) {
-		dev_err(&pdev->dev, "Unable to get MEM resource\n");
-		err = -EINVAL;
-		goto out;
-	}
-
 	siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
 	if (IS_ERR(siic->base)) {
 		err = PTR_ERR(siic->base);
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index b60ff90..9aa1b60 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -714,11 +714,6 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 	int ret = 0;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "no mem resource\n");
-		return -EINVAL;
-	}
-
 	base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(base))
 		return PTR_ERR(base);
-- 
1.7.10.4



From wsa at the-dreams.de  Thu May 16 07:15:43 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Thu, 16 May 2013 13:15:43 +0200
Subject: [PATCH 15/33] drivers/pwm: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
Message-ID: <1368702961-4325-16-git-send-email-wsa@the-dreams.de>

devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
---
 drivers/pwm/pwm-imx.c      |    5 -----
 drivers/pwm/pwm-puv3.c     |    5 -----
 drivers/pwm/pwm-pxa.c      |    5 -----
 drivers/pwm/pwm-tegra.c    |    5 -----
 drivers/pwm/pwm-tiecap.c   |    5 -----
 drivers/pwm/pwm-tiehrpwm.c |    5 -----
 drivers/pwm/pwm-tipwmss.c  |    5 -----
 drivers/pwm/pwm-vt8500.c   |    5 -----
 8 files changed, 40 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index ec28798..c938bae 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -265,11 +265,6 @@ static int imx_pwm_probe(struct platform_device *pdev)
 	imx->chip.npwm = 1;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(imx->mmio_base))
 		return PTR_ERR(imx->mmio_base);
diff --git a/drivers/pwm/pwm-puv3.c b/drivers/pwm/pwm-puv3.c
index d1eb499..ed6007b 100644
--- a/drivers/pwm/pwm-puv3.c
+++ b/drivers/pwm/pwm-puv3.c
@@ -117,11 +117,6 @@ static int pwm_probe(struct platform_device *pdev)
 		return PTR_ERR(puv3->clk);
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	puv3->base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(puv3->base))
 		return PTR_ERR(puv3->base);
diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index dee6ab55..dc97175 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -147,11 +147,6 @@ static int pwm_probe(struct platform_device *pdev)
 	pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(pwm->mmio_base))
 		return PTR_ERR(pwm->mmio_base);
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 3d75f4a..a540293 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -181,11 +181,6 @@ static int tegra_pwm_probe(struct platform_device *pdev)
 	pwm->dev = &pdev->dev;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!r) {
-		dev_err(&pdev->dev, "no memory resources defined\n");
-		return -ENODEV;
-	}
-
 	pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(pwm->mmio_base))
 		return PTR_ERR(pwm->mmio_base);
diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
index 0d65fb2..72ca42d 100644
--- a/drivers/pwm/pwm-tiecap.c
+++ b/drivers/pwm/pwm-tiecap.c
@@ -240,11 +240,6 @@ static int ecap_pwm_probe(struct platform_device *pdev)
 	pc->chip.npwm = 1;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!r) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(pc->mmio_base))
 		return PTR_ERR(pc->mmio_base);
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 6a21759..48a485c 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -471,11 +471,6 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
 	pc->chip.npwm = NUM_PWM_CHANNEL;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!r) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(pc->mmio_base))
 		return PTR_ERR(pc->mmio_base);
diff --git a/drivers/pwm/pwm-tipwmss.c b/drivers/pwm/pwm-tipwmss.c
index c9c3d3a..3b119bc 100644
--- a/drivers/pwm/pwm-tipwmss.c
+++ b/drivers/pwm/pwm-tipwmss.c
@@ -70,11 +70,6 @@ static int pwmss_probe(struct platform_device *pdev)
 	mutex_init(&info->pwmss_lock);
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!r) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(info->mmio_base))
 		return PTR_ERR(info->mmio_base);
diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c
index 69effd1..323125a 100644
--- a/drivers/pwm/pwm-vt8500.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -230,11 +230,6 @@ static int vt8500_pwm_probe(struct platform_device *pdev)
 	}
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		return -ENODEV;
-	}
-
 	chip->base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(chip->base))
 		return PTR_ERR(chip->base);
-- 
1.7.10.4



From wsa at the-dreams.de  Thu May 16 07:15:44 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Thu, 16 May 2013 13:15:44 +0200
Subject: [PATCH 16/33] drivers/rtc: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
Message-ID: <1368702961-4325-17-git-send-email-wsa@the-dreams.de>

devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
---
 drivers/rtc/rtc-nuc900.c |    5 -----
 drivers/rtc/rtc-omap.c   |    5 -----
 drivers/rtc/rtc-s3c.c    |    5 -----
 drivers/rtc/rtc-tegra.c  |    6 ------
 4 files changed, 21 deletions(-)

diff --git a/drivers/rtc/rtc-nuc900.c b/drivers/rtc/rtc-nuc900.c
index f5dfb6e..d592e2f 100644
--- a/drivers/rtc/rtc-nuc900.c
+++ b/drivers/rtc/rtc-nuc900.c
@@ -234,11 +234,6 @@ static int __init nuc900_rtc_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "platform_get_resource failed\n");
-		return -ENXIO;
-	}
-
 	nuc900_rtc->rtc_reg = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(nuc900_rtc->rtc_reg))
 		return PTR_ERR(nuc900_rtc->rtc_reg);
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 4e1bdb8..b0ba3fc 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -347,11 +347,6 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		pr_debug("%s: RTC resource data missing\n", pdev->name);
-		return -ENOENT;
-	}
-
 	rtc_base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(rtc_base))
 		return PTR_ERR(rtc_base);
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 14040b2..0b495e8 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -477,11 +477,6 @@ static int s3c_rtc_probe(struct platform_device *pdev)
 	/* get the memory region */
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res == NULL) {
-		dev_err(&pdev->dev, "failed to get memory region resource\n");
-		return -ENOENT;
-	}
-
 	s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(s3c_rtc_base))
 		return PTR_ERR(s3c_rtc_base);
diff --git a/drivers/rtc/rtc-tegra.c b/drivers/rtc/rtc-tegra.c
index a34315d..76af92a 100644
--- a/drivers/rtc/rtc-tegra.c
+++ b/drivers/rtc/rtc-tegra.c
@@ -322,12 +322,6 @@ static int __init tegra_rtc_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(&pdev->dev,
-			"Unable to allocate resources for device.\n");
-		return -EBUSY;
-	}
-
 	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(info->rtc_base))
 		return PTR_ERR(info->rtc_base);
-- 
1.7.10.4



From wsa at the-dreams.de  Thu May 16 07:15:57 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Thu, 16 May 2013 13:15:57 +0200
Subject: [PATCH 29/33] arch/arm/mach-tegra: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
Message-ID: <1368702961-4325-30-git-send-email-wsa@the-dreams.de>

devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
---
 arch/arm/mach-tegra/tegra2_emc.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 9e8bdfa..31e69a0 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -307,11 +307,6 @@ static int tegra_emc_probe(struct platform_device *pdev)
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "missing register base\n");
-		return -ENOMEM;
-	}
-
 	emc_regbase = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(emc_regbase))
 		return PTR_ERR(emc_regbase);
-- 
1.7.10.4



From wsa at the-dreams.de  Thu May 16 07:15:58 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Thu, 16 May 2013 13:15:58 +0200
Subject: [PATCH 30/33] arch/arm/plat-samsung: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
Message-ID: <1368702961-4325-31-git-send-email-wsa@the-dreams.de>

devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa at the-dreams.de>
---
 arch/arm/plat-samsung/adc.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index ca07cb1..79690f2 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -381,11 +381,6 @@ static int s3c_adc_probe(struct platform_device *pdev)
 	}
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!regs) {
-		dev_err(dev, "failed to find registers\n");
-		return -ENXIO;
-	}
-
 	adc->regs = devm_ioremap_resource(dev, regs);
 	if (IS_ERR(adc->regs))
 		return PTR_ERR(adc->regs);
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May 16 07:15:35 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:15:35 +0100
Subject: [PATCH] ARM: ux500: Only configure wake-up reasons on ux500 based
 platforms
Message-ID: <1368702935-25599-1-git-send-email-lee.jones@linaro.org>

Multiplatform calls all enabled platforms' initcalls. In the
ux500_idle_init() initcall we call into the DBx500-PRCMU which in turn
executes some ux500 specific register reads/writes. When running on
some !ux500 platforms this ends up causing a kernel Oops. This patch
ensures the PRCMU call is only invoked when running on ux500 based
platforms.

Reported-by: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpuidle.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
index 317a2be..a45dd09 100644
--- a/arch/arm/mach-ux500/cpuidle.c
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -21,6 +21,7 @@
 #include <asm/proc-fns.h>
 
 #include "db8500-regs.h"
+#include "id.h"
 
 static atomic_t master = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(master_lock);
@@ -114,6 +115,9 @@ static struct cpuidle_driver ux500_idle_driver = {
 
 int __init ux500_idle_init(void)
 {
+	if (!(cpu_is_u8500_family() || cpu_is_ux540_family()))
+		return -ENODEV;
+
 	/* Configure wake up reasons */
 	prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
 			     PRCMU_WAKEUP(ABB));
-- 
1.7.10.4



From mst at redhat.com  Thu May 16 07:10:03 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:10:03 +0300
Subject: [PATCH v2 01/10] asm-generic: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <0138f31b9c0f1764a0d6bbed2ee9aa3aedea6815.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 include/asm-generic/uaccess.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/asm-generic/uaccess.h b/include/asm-generic/uaccess.h
index c184aa8..dc1269c 100644
--- a/include/asm-generic/uaccess.h
+++ b/include/asm-generic/uaccess.h
@@ -163,7 +163,7 @@ static inline __must_check long __copy_to_user(void __user *to,
 
 #define put_user(x, ptr)					\
 ({								\
-	might_sleep();						\
+	might_fault();						\
 	access_ok(VERIFY_WRITE, ptr, sizeof(*ptr)) ?		\
 		__put_user(x, ptr) :				\
 		-EFAULT;					\
@@ -225,7 +225,7 @@ extern int __put_user_bad(void) __attribute__((noreturn));
 
 #define get_user(x, ptr)					\
 ({								\
-	might_sleep();						\
+	might_fault();						\
 	access_ok(VERIFY_READ, ptr, sizeof(*ptr)) ?		\
 		__get_user(x, ptr) :				\
 		-EFAULT;					\
@@ -255,7 +255,7 @@ extern int __get_user_bad(void) __attribute__((noreturn));
 static inline long copy_from_user(void *to,
 		const void __user * from, unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	if (access_ok(VERIFY_READ, from, n))
 		return __copy_from_user(to, from, n);
 	else
@@ -265,7 +265,7 @@ static inline long copy_from_user(void *to,
 static inline long copy_to_user(void __user *to,
 		const void *from, unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	if (access_ok(VERIFY_WRITE, to, n))
 		return __copy_to_user(to, from, n);
 	else
@@ -336,7 +336,7 @@ __clear_user(void __user *to, unsigned long n)
 static inline __must_check unsigned long
 clear_user(void __user *to, unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	if (!access_ok(VERIFY_WRITE, to, n))
 		return n;
 
-- 
MST



From mst at redhat.com  Thu May 16 07:15:36 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:15:36 +0300
Subject: [PATCH v2 07/10] powerpc: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <2aa6c3da21a28120126732b5e0b4ecd6cba8ca3b.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/powerpc/include/asm/uaccess.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
index 4db4959..9485b43 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -178,7 +178,7 @@ do {								\
 	long __pu_err;						\
 	__typeof__(*(ptr)) __user *__pu_addr = (ptr);		\
 	if (!is_kernel_addr((unsigned long)__pu_addr))		\
-		might_sleep();					\
+		might_fault();					\
 	__chk_user_ptr(ptr);					\
 	__put_user_size((x), __pu_addr, (size), __pu_err);	\
 	__pu_err;						\
@@ -188,7 +188,7 @@ do {								\
 ({									\
 	long __pu_err = -EFAULT;					\
 	__typeof__(*(ptr)) __user *__pu_addr = (ptr);			\
-	might_sleep();							\
+	might_fault();							\
 	if (access_ok(VERIFY_WRITE, __pu_addr, size))			\
 		__put_user_size((x), __pu_addr, (size), __pu_err);	\
 	__pu_err;							\
@@ -268,7 +268,7 @@ do {								\
 	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);	\
 	__chk_user_ptr(ptr);					\
 	if (!is_kernel_addr((unsigned long)__gu_addr))		\
-		might_sleep();					\
+		might_fault();					\
 	__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;			\
 	__gu_err;						\
@@ -282,7 +282,7 @@ do {								\
 	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);	\
 	__chk_user_ptr(ptr);					\
 	if (!is_kernel_addr((unsigned long)__gu_addr))		\
-		might_sleep();					\
+		might_fault();					\
 	__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;			\
 	__gu_err;						\
@@ -294,7 +294,7 @@ do {								\
 	long __gu_err = -EFAULT;					\
 	unsigned long  __gu_val = 0;					\
 	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);		\
-	might_sleep();							\
+	might_fault();							\
 	if (access_ok(VERIFY_READ, __gu_addr, (size)))			\
 		__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;				\
@@ -419,14 +419,14 @@ static inline unsigned long __copy_to_user_inatomic(void __user *to,
 static inline unsigned long __copy_from_user(void *to,
 		const void __user *from, unsigned long size)
 {
-	might_sleep();
+	might_fault();
 	return __copy_from_user_inatomic(to, from, size);
 }
 
 static inline unsigned long __copy_to_user(void __user *to,
 		const void *from, unsigned long size)
 {
-	might_sleep();
+	might_fault();
 	return __copy_to_user_inatomic(to, from, size);
 }
 
@@ -434,7 +434,7 @@ extern unsigned long __clear_user(void __user *addr, unsigned long size);
 
 static inline unsigned long clear_user(void __user *addr, unsigned long size)
 {
-	might_sleep();
+	might_fault();
 	if (likely(access_ok(VERIFY_WRITE, addr, size)))
 		return __clear_user(addr, size);
 	if ((unsigned long)addr < TASK_SIZE) {
-- 
MST



From mst at redhat.com  Thu May 16 07:15:48 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:15:48 +0300
Subject: [PATCH v2 08/10] tile: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <018bba1e097552bc4054e6d90e3f03e7c9a632bb.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 arch/tile/include/asm/uaccess.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/tile/include/asm/uaccess.h b/arch/tile/include/asm/uaccess.h
index 8a082bc..e4d44bd 100644
--- a/arch/tile/include/asm/uaccess.h
+++ b/arch/tile/include/asm/uaccess.h
@@ -442,7 +442,7 @@ extern unsigned long __copy_in_user_inatomic(
 static inline unsigned long __must_check
 __copy_in_user(void __user *to, const void __user *from, unsigned long n)
 {
-	might_sleep();
+	might_fault();
 	return __copy_in_user_inatomic(to, from, n);
 }
 
-- 
MST



From mst at redhat.com  Thu May 16 07:15:58 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:15:58 +0300
Subject: [PATCH v2 09/10] x86: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <4fe705ad6d48e166bfe77c1401140008eac8f6f6.1368702323.git.mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
Acked-by: Ingo Molnar <mingo at kernel.org>
---
 arch/x86/include/asm/uaccess_64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h
index 142810c..4f7923d 100644
--- a/arch/x86/include/asm/uaccess_64.h
+++ b/arch/x86/include/asm/uaccess_64.h
@@ -235,7 +235,7 @@ extern long __copy_user_nocache(void *dst, const void __user *src,
 static inline int
 __copy_from_user_nocache(void *dst, const void __user *src, unsigned size)
 {
-	might_sleep();
+	might_fault();
 	return __copy_user_nocache(dst, src, size, 1);
 }
 
-- 
MST



From mst at redhat.com  Thu May 16 07:16:10 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Thu, 16 May 2013 14:16:10 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>

There are several ways to make sure might_fault
calling function does not sleep.
One is to use it on kernel or otherwise locked memory - apparently
nfs/sunrpc does this. As noted by Ingo, this is handled by the
migh_fault() implementation in mm/memory.c but not the one in
linux/kernel.h so in the current code might_fault() schedules
differently depending on CONFIG_PROVE_LOCKING, which is an undesired
semantical side effect.

Another is to call pagefault_disable: in this case the page fault
handler will go to fixups processing and we get an error instead of
sleeping, so the might_sleep annotation is a false positive.
vhost driver wants to do this now in order to reuse socket ops
under a spinlock (and fall back on slower thread handler
on error).

Address both issues by:
	- dropping the unconditional call to might_sleep
	  from the fast might_fault code in linux/kernel.h
	- checking for pagefault_disable() in the
	  CONFIG_PROVE_LOCKING implementation

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
 include/linux/kernel.h |  1 -
 mm/memory.c            | 14 +++++++++-----
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index e96329c..322b065 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -198,7 +198,6 @@ void might_fault(void);
 #else
 static inline void might_fault(void)
 {
-	might_sleep();
 }
 #endif
 
diff --git a/mm/memory.c b/mm/memory.c
index 6dc1882..1b8327b 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -4222,13 +4222,17 @@ void might_fault(void)
 	if (segment_eq(get_fs(), KERNEL_DS))
 		return;
 
-	might_sleep();
 	/*
-	 * it would be nicer only to annotate paths which are not under
-	 * pagefault_disable, however that requires a larger audit and
-	 * providing helpers like get_user_atomic.
+	 * It would be nicer to annotate paths which are under preempt_disable
+	 * but not under pagefault_disable, however that requires a new flag
+	 * for differentiating between the two.
 	 */
-	if (!in_atomic() && current->mm)
+	if (in_atomic())
+		return;
+
+	might_sleep();
+
+	if (current->mm)
 		might_lock_read(&current->mm->mmap_sem);
 }
 EXPORT_SYMBOL(might_fault);
-- 
MST


From moinejf at free.fr  Thu May 16 07:28:22 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Thu, 16 May 2013 13:28:22 +0200
Subject: [PATCH] ARM: dove: add a kms/drm driver
Message-ID: <20130516132822.09b883cf@armhf>

This patch adds a KMS/DRM video driver for the LCD and display
controllers of the Marvell's Dove SoC.

Signed-off-by: Jean-Francois Moine <moinejf at free.fr>
---
 drivers/gpu/drm/Kconfig          |    2 +
 drivers/gpu/drm/Makefile         |    1 +
 drivers/gpu/drm/dove/Kconfig     |   10 +
 drivers/gpu/drm/dove/Makefile    |    6 +
 drivers/gpu/drm/dove/dove_crtc.c | 1378 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/dove/dove_dcon.h |   64 +++
 drivers/gpu/drm/dove/dove_drv.c  |  380 +++++++++++++
 drivers/gpu/drm/dove/dove_drv.h  |   93 ++++
 drivers/gpu/drm/dove/dove_ec.c   |  570 ++++++++++++++++++++
 drivers/gpu/drm/dove/dove_lcd.h  |  519 ++++++++++++++++++
 10 files changed, 3023 insertions(+)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index b16c50e..c6e4f4f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -220,3 +220,5 @@ source "drivers/gpu/drm/omapdrm/Kconfig"
 source "drivers/gpu/drm/tilcdc/Kconfig"
 
 source "drivers/gpu/drm/qxl/Kconfig"
+
+source "drivers/gpu/drm/dove/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 1c9f243..6428683 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -52,4 +52,5 @@ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
 obj-$(CONFIG_DRM_OMAP)	+= omapdrm/
 obj-$(CONFIG_DRM_TILCDC)	+= tilcdc/
 obj-$(CONFIG_DRM_QXL) += qxl/
+obj-$(CONFIG_DRM_DOVE)	+= dove/
 obj-y			+= i2c/
diff --git a/drivers/gpu/drm/dove/Kconfig b/drivers/gpu/drm/dove/Kconfig
new file mode 100644
index 0000000..465dc4d
--- /dev/null
+++ b/drivers/gpu/drm/dove/Kconfig
@@ -0,0 +1,10 @@
+config DRM_DOVE
+	tristate "DRM Support for Marvell Dove"
+	depends on DRM && ARCH_DOVE
+	depends on OF
+	select DRM_KMS_HELPER
+	select DRM_KMS_CMA_HELPER
+	select DRM_GEM_CMA_HELPER
+	help
+	  Choose this option if you have a Marvell Dove chipset.
+	  If M is selected the module will be called dove-drm.
diff --git a/drivers/gpu/drm/dove/Makefile b/drivers/gpu/drm/dove/Makefile
new file mode 100644
index 0000000..3758a19
--- /dev/null
+++ b/drivers/gpu/drm/dove/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for Marvell Dove's DRM device driver
+#
+
+dove-drm-objs := dove_drv.o dove_crtc.o dove_ec.o
+obj-$(CONFIG_DRM_DOVE) += dove-drm.o
diff --git a/drivers/gpu/drm/dove/dove_crtc.c b/drivers/gpu/drm/dove/dove_crtc.c
new file mode 100644
index 0000000..9e397e7
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_crtc.c
@@ -0,0 +1,1378 @@
+/*
+ * Marvell Dove DRM driver - CRTC
+ *
+ * Copyright (C) 2013
+ *   Jean-Francois Moine <moinejf at free.fr>
+ *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/of_irq.h>
+
+#include "dove_drv.h"
+#include "dove_lcd.h"
+
+#define DOVE_LCD_REG_BASE_MASK	0xfffff
+#define DOVE_LCD0_REG_BASE	0x20000
+#define DOVE_LCD1_REG_BASE	0x10000
+
+#define to_dove_lcd(x) container_of(x, struct dove_lcd, crtc)
+
+static inline void dove_write(struct dove_lcd *dove_lcd, u32 reg, u32 data)
+{
+	writel(data, dove_lcd->mmio + reg);
+}
+static inline u32 dove_read(struct dove_lcd *dove_lcd, u32 reg)
+{
+	return readl(dove_lcd->mmio + reg);
+}
+static inline void dove_set(struct dove_lcd *dove_lcd, u32 reg, u32 mask)
+{
+	dove_write(dove_lcd, reg, dove_read(dove_lcd, reg) | mask);
+}
+static inline void dove_clear(struct dove_lcd *dove_lcd, u32 reg, u32 mask)
+{
+	dove_write(dove_lcd, reg, dove_read(dove_lcd, reg) & ~mask);
+}
+
+/*
+ * vertical blank functions
+ */
+u32 dove_vblank_count(struct drm_device *dev, int crtc)
+{
+	struct dove_lcd *dove_lcd = dove_drm.lcds[crtc];
+
+	return STA_GRA_FRAME_COUNT(dove_read(dove_lcd, SPU_IRQ_ISR));
+}
+
+int dove_enable_vblank(struct drm_device *dev, int crtc)
+{
+	struct dove_lcd *dove_lcd = dove_drm.lcds[crtc];
+
+#ifdef HANDLE_INTERLACE
+	dove_lcd->vblank_enabled = 1;
+#endif
+	dove_set(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
+	return 0;
+}
+
+void dove_disable_vblank(struct drm_device *dev, int crtc)
+{
+	struct dove_lcd *dove_lcd = dove_drm.lcds[crtc];
+
+#ifdef HANDLE_INTERLACE
+	dove_lcd->vblank_enabled = 0;
+	if (!dove_lcd->v_sync0)
+#endif
+	dove_clear(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int dove_lcd_regs_show(struct seq_file *m,
+			struct dove_lcd *dove_lcd)
+{
+	u32 x, shl, shh, total_v, total_h, active_h, active_v;
+	u32 orig_buff_x, orig_buff_y, zoomed_x, zoomed_y;
+	unsigned i;
+
+	seq_printf(m, "\t\t*** LCD %d ***\n", dove_lcd->num);
+
+	/* Get resolution */
+	x = dove_read(dove_lcd, LCD_SPU_V_H_ACTIVE);
+	active_h = H_LCD(x);
+	active_v = V_LCD(x);
+
+	/* Get total line */
+	x = dove_read(dove_lcd, LCD_SPUT_V_H_TOTAL);
+	total_h = H_LCD(x);
+	total_v = V_LCD(x);
+	seq_printf(m, "----total-------------------------<%4dx%4d>"
+					"-------------------------\n"
+			"----active--------------|", total_h, total_v);
+
+	/* Get H Timings */
+	x = dove_read(dove_lcd, LCD_SPU_H_PORCH);
+	shl = F_LCD(x);
+	shh = B_LCD(x);
+	seq_printf(m, "->front porch(%d)->hsync(%d)->back porch(%d)\n",
+		shl, total_h - shl -shh - active_h, shh);
+
+	seq_printf(m,	"|\t\t\t|\n"
+			"|\t\t\t|\n"
+			"|\t<%4dx%4d>\t|\n"
+			"|\t\t\t|\n"
+			"|\t\t\t|\n"
+			"------------------------|\n", active_h, active_v);
+
+	/* Get V Timings */
+	x = dove_read(dove_lcd, LCD_SPU_V_PORCH);
+	shl = F_LCD(x);
+	shh = B_LCD(x);
+	seq_printf(m, "|\n|front porch(%d)\n|vsync(%d)\n|back porch(%d)\n",
+		shl, total_v - shl - shh - active_v, shh);
+	seq_printf(m, "----------------------------------"
+			"-----------------------------------\n");
+
+	/* Get Line Pitch */
+	x = dove_read(dove_lcd, LCD_CFG_GRA_PITCH);
+	shl = x & 0x0000ffff;
+	seq_printf(m, "gfx line pitch in memory is <%d>\n",
+			shl);
+
+	/* Get scaling info */
+	x = dove_read(dove_lcd, LCD_SPU_GRA_HPXL_VLN);
+	orig_buff_x = H_LCD(x);
+	orig_buff_y = V_LCD(x);
+	x = dove_read(dove_lcd, LCD_SPU_GZM_HPXL_VLN);
+	zoomed_x = H_LCD(x);
+	zoomed_y = V_LCD(x);
+	seq_printf(m, "Scaled from <%dx%d> to <%dx%d>\n",
+			orig_buff_x, orig_buff_y, zoomed_x, zoomed_y);
+
+	seq_printf(m, "======================================\n");
+
+	for (i = 0x0080; i <= 0x01c4; i += 4) {
+		x = dove_read(dove_lcd, i);
+		seq_printf(m, "0x%04x 0x%08x\n", i, x);
+	}
+	return 0;
+}
+
+static int dove_regs_show(struct seq_file *m, void *arg)
+{
+	struct dove_lcd *dove_lcd;
+	unsigned i;
+
+	for (i = 0; i < MAX_DOVE_LCD; i++) {
+		dove_lcd = dove_drm.lcds[i];
+		if (dove_lcd)
+			dove_lcd_regs_show(m, dove_lcd);
+	}
+	return 0;
+}
+
+static struct drm_info_list dove_debugfs_list[] = {
+	{ "lcd", dove_regs_show, 0 },
+	{ "fb",   drm_fb_cma_debugfs_show, 0 },
+};
+
+int dove_debugfs_init(struct drm_minor *minor)
+{
+	struct drm_device *dev = minor->dev;
+	int ret;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	ret = drm_debugfs_create_files(dove_debugfs_list,
+			ARRAY_SIZE(dove_debugfs_list),
+			minor->debugfs_root, minor);
+	if (ret)
+		dev_err(dev->dev, "could not install dove_debugfs_list\n");
+
+	return ret;
+}
+
+void dove_debugfs_cleanup(struct drm_minor *minor)
+{
+	drm_debugfs_remove_files(dove_debugfs_list,
+			ARRAY_SIZE(dove_debugfs_list), minor);
+}
+#endif
+
+static void dove_update_base(struct dove_lcd *dove_lcd)
+{
+	struct drm_crtc *crtc = &dove_lcd->crtc;
+	struct drm_framebuffer *fb = crtc->fb;
+	struct drm_gem_cma_object *gem;
+	unsigned int depth, bpp;
+	dma_addr_t start;
+
+	drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
+	gem = drm_fb_cma_get_gem_obj(fb, 0);
+	start = gem->paddr + fb->offsets[0] +
+			crtc->y * fb->pitches[0] +
+			crtc->x * bpp / 8;
+
+	dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR0, start);
+#ifdef HANDLE_INTERLACE
+	if (dove_lcd->crtc.mode.mode->flags & DRM_MODE_FLAG_INTERLACE) {
+		dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR1,
+					start + fb->pitches[0]);
+		dove_write(dove_lcd, LCD_CFG_GRA_PITCH, fb->pitches[0] * 2);
+		return;
+	}
+#endif
+	dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR1, start);
+	dove_write(dove_lcd, LCD_CFG_GRA_PITCH, fb->pitches[0]);
+}
+
+static void set_frame_timings(struct dove_lcd *dove_lcd)
+{
+	struct drm_crtc *crtc = &dove_lcd->crtc;
+	const struct drm_display_mode *mode = &crtc->mode;
+	u32 h_active, v_active, h_orig, v_orig, h_zoom, v_zoom;
+	u32 hfp, hbp, vfp, vbp, hs, vs, v_total;
+	u32 x;
+
+	/*
+	 * Calc active size, zoomed size, porch.
+	 */
+	h_active = h_zoom = mode->hdisplay;
+	v_active = v_zoom = mode->vdisplay;
+	hfp = mode->hsync_start - mode->hdisplay;
+	hbp = mode->htotal - mode->hsync_end;
+	vfp = mode->vsync_start - mode->vdisplay;
+	vbp = mode->vtotal - mode->vsync_end;
+	hs = mode->hsync_end - mode->hsync_start;
+	vs = mode->vsync_end - mode->vsync_start;
+
+	/*
+	 * Calc original size.
+	 */
+	h_orig = h_active;
+	v_orig = v_active;
+
+#ifdef HANDLE_INTERLACE
+	/* interlaced workaround */
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+		v_active /= 2;
+		v_zoom /= 2;
+		v_orig /= 2;
+	}
+#endif
+
+	/* calc total width and height */
+	v_total = v_active + vfp + vs + vbp;
+
+	/* apply setting to registers */
+	dove_write(dove_lcd, LCD_SPU_V_H_ACTIVE, LCD_H_V(h_active, v_active));
+	dove_write(dove_lcd, LCD_SPU_GRA_HPXL_VLN, LCD_H_V(h_orig, v_orig));
+	dove_write(dove_lcd, LCD_SPU_GZM_HPXL_VLN, LCD_H_V(h_zoom, v_zoom));
+	dove_write(dove_lcd, LCD_SPU_H_PORCH, LCD_F_B(hfp, hbp));
+	dove_write(dove_lcd, LCD_SPU_V_PORCH, LCD_F_B(vfp, vbp));
+	dove_write(dove_lcd, LCD_SPUT_V_H_TOTAL,
+					LCD_H_V(mode->htotal, v_total));
+
+	/* configure vsync adjust logic */
+	x = dove_read(dove_lcd, LCD_TV_CONTROL1);
+	x &= ~(VSYNC_L_OFFSET_MASK | VSYNC_H_OFFSET_MASK);
+	x |= VSYNC_OFFSET_EN |			/* VSYNC adjust enable */
+		VSYNC_L_OFFSET(h_active + hfp) |
+		VSYNC_H_OFFSET(h_active + hfp);
+#ifdef HANDLE_INTERLACE
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+		dove_lcd->v_sync0 = VSYNC_L_OFFSET(h_active + hfp) |
+				VSYNC_H_OFFSET(h_active + hfp);
+		dove_lcd->v_sync1 = VSYNC_L_OFFSET(h_active / 2 + hfp) |
+				VSYNC_H_OFFSET(h_active / 2 + hfp);
+	} else {
+		dove_lcd->v_sync0 = 0;
+	}
+#endif
+	dove_write(dove_lcd, LCD_TV_CONTROL1, x);
+}
+
+static int dove_set_clock(struct dove_lcd *dove_lcd)
+{
+	struct drm_crtc *crtc = &dove_lcd->crtc;
+	const struct drm_display_mode *mode = &crtc->mode;
+	struct clk *clk;
+	u32 x, needed_pixclk, ref_clk, div, fract;
+	int clk_src;
+
+	fract = 0;
+	needed_pixclk = mode->clock * 1000;
+#ifdef HANDLE_INTERLACE
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+		needed_pixclk /= 2;
+#endif
+
+	/* first check if pixclk is multiple of current clock */
+	clk_src = dove_lcd->clk_src;
+	clk = dove_lcd->clk[clk_src];
+	ref_clk = clk_get_rate(clk);
+
+	DRM_DEBUG_DRIVER("clk src %d rate %u needed %u div %u mod %u\n",
+			clk_src, ref_clk, needed_pixclk,
+			ref_clk / needed_pixclk, ref_clk % needed_pixclk);
+
+	if (ref_clk % needed_pixclk == 0) {
+		div = ref_clk / needed_pixclk;
+		goto set_clock;
+	}
+
+	/* try to set current clock to requested pixclk */
+	clk_set_rate(clk, needed_pixclk);
+	ref_clk = clk_get_rate(clk);
+	if (ref_clk == needed_pixclk) {
+		div = 1;
+		goto set_clock;
+	}
+
+	/* check if any other clock can set pixclk directly */
+	for (clk_src = 0; clk_src < MAX_CLK; clk_src++) {
+		clk = dove_lcd->clk[clk_src];
+		if (!clk)
+			continue;
+
+		/* try to set clock to requested pixclk */
+		clk_set_rate(clk, needed_pixclk);
+		ref_clk = clk_get_rate(clk);
+
+		if (ref_clk % needed_pixclk == 0) {
+			div = ref_clk / needed_pixclk;
+			goto set_clock;
+		}
+	}
+
+	/* fall back to default fix clock source LCD or AXI */
+	if (dove_lcd->clk[SCLK_SRC_PLLDIV])
+		clk_src = SCLK_SRC_PLLDIV;
+	else
+		clk_src = SCLK_SRC_AXI;
+	clk = dove_lcd->clk[clk_src];
+
+	clk_set_rate(clk, needed_pixclk);
+	ref_clk = clk_get_rate(clk);
+		
+	/* use internal divider */
+	if (false) {
+/*fixme: does not work*/
+		ref_clk /= 1000;
+		needed_pixclk /= 1000;
+		x = (ref_clk * 0x1000 + needed_pixclk - 1) / needed_pixclk;
+		div = x >> 12;
+		if (div < 1)
+			div = 1;
+		else
+			fract = x & 0xfff;
+	} else {
+		div = (ref_clk + needed_pixclk - 1) / needed_pixclk;
+		if (div < 1)
+			div = 1;
+	}
+
+set_clock:
+	dove_lcd->clk_src = clk_src;
+	DRM_DEBUG_DRIVER("set clk src %d ref %u div %u fract %u needed %u\n",
+			clk_src, ref_clk, div, fract, needed_pixclk);
+	x = SET_SCLK(clk_src, div, fract);
+	dove_write(dove_lcd, LCD_CFG_SCLK_DIV, x);
+	return 0;
+}
+
+static void set_dma_control(struct dove_lcd *dove_lcd)
+{
+	const struct drm_display_mode *mode = &dove_lcd->crtc.mode;
+	u32 x;
+	int fmt, rbswap;
+
+	rbswap = 1;				/* default */
+	switch (dove_lcd->crtc.fb->pixel_format) {
+	case DRM_FORMAT_BGR888:
+		rbswap = 0;
+	case DRM_FORMAT_RGB888:
+		fmt = GMODE_RGB888PACKED;
+		break;
+	case DRM_FORMAT_XBGR8888:
+		rbswap = 0;
+	case DRM_FORMAT_XRGB8888:		/* depth 24 */
+		fmt = GMODE_RGBA888;
+		break;
+	case DRM_FORMAT_ABGR8888:
+		rbswap = 0;
+	case DRM_FORMAT_ARGB8888:		/* depth 32 */
+		fmt = GMODE_RGB888UNPACKED;
+		break;
+	case DRM_FORMAT_YVYU:
+		rbswap = 0;
+	case DRM_FORMAT_YUYV:
+		fmt = GMODE_YUV422PACKED;
+		break;
+	case DRM_FORMAT_YVU422:
+		rbswap = 0;
+	case DRM_FORMAT_YUV422:
+		fmt = GMODE_YUV422PLANAR;
+		break;
+	case DRM_FORMAT_YVU420:
+		rbswap = 0;
+	default:
+/*	case DRM_FORMAT_YUV420: */
+		fmt = GMODE_YUV420PLANAR;
+		break;
+	}
+
+	x = dove_read(dove_lcd, LCD_SPU_DMA_CTRL0);
+	x &= ~(CFG_PALETTE_ENA |		/* true color */
+		CFG_GRAFORMAT_MASK |
+		CFG_GRA_SWAPRB |
+		CFG_GRA_FTOGGLE);
+	x |= CFG_GRA_ENA |			/* graphic enable */
+		CFG_GRA_HSMOOTH;		/* horiz. smooth scaling */
+	x |= CFG_GRAFORMAT(fmt);
+
+	if (!rbswap)
+		x |= CFG_GRA_SWAPRB;
+#ifdef HANDLE_INTERLACE
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+		x |= CFG_GRA_FTOGGLE;
+#endif
+	dove_write(dove_lcd, LCD_SPU_DMA_CTRL0, x);
+
+	/*
+	 * trigger DMA on the falling edge of vsync if vsync is
+	 * active low, or on the rising edge if vsync is active high
+	 */
+	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
+		dove_set(dove_lcd, LCD_SPU_DMA_CTRL1, CFG_VSYNC_INV);
+}
+
+/* this function is called on mode DRM_MODE_DPMS_ON
+ * and also at loading time with gpio_only set */
+static void set_dumb_panel_control(struct dove_lcd *dove_lcd,
+				int gpio_only)
+{
+	const struct drm_display_mode *mode = &dove_lcd->crtc.mode;
+	u32 x;
+
+	x = 0;
+	if (dove_lcd->dpms == DRM_MODE_DPMS_ON)
+		x = CFG_DUMB_ENA;
+	if (!gpio_only) {
+		if (dove_lcd->dpms == DRM_MODE_DPMS_ON)
+			/*
+			 * When dumb interface isn't under 24bit
+			 * It might be under SPI or GPIO. If set
+			 * to 0x7 will force LCD_D[23:0] output
+			 * blank color and damage GPIO and SPI
+			 * behavior.
+			 */
+			x |= CFG_DUMBMODE(DUMB24_RGB888_0);
+		else
+			x |= CFG_DUMBMODE(7);
+/*fixme
+		if (mode->flags & FB_SYNC_COMP_HIGH_ACT)
+			x |= CFG_INV_COMPSYNC;
+*/
+		if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
+			x |= CFG_INV_VSYNC;
+
+		/* Following is a weired workaround. This bit shouldn't be set
+		 * For now, if it's 1080p or 720 then don't set HOR_HIGH_ACT */
+		if ((mode->hdisplay == 1920 && mode->vdisplay == 1080) ||
+		    (mode->hdisplay == 1280 && mode->vdisplay == 720))
+			/* Do nothing */
+			;
+		else
+			if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
+				x |= CFG_INV_HSYNC;
+	}
+
+	dove_write(dove_lcd, LCD_SPU_DUMB_CTRL, x);
+}
+
+void dove_crtc_start(struct dove_lcd *dove_lcd)
+{
+	struct drm_crtc *crtc = &dove_lcd->crtc;
+	struct drm_display_mode *mode = &crtc->mode;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	if (mode->clock == 0) {
+		dev_err(dove_lcd->dev, "crtc_start: no clock!\n");
+		dove_lcd->dpms = DRM_MODE_DPMS_OFF;
+		return;
+	}
+
+	set_frame_timings(dove_lcd);
+	if (dove_set_clock(dove_lcd) < 0)
+		return;
+	set_dma_control(dove_lcd);
+	dove_update_base(dove_lcd);
+	set_dumb_panel_control(dove_lcd, 0);
+
+#ifdef HANDLE_INTERLACE
+	if (dove_lcd->v_sync0) {		/* interlace mode on */
+		dove_set(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
+	} else {				/* interlace mode off */
+		if (!dove_lcd->vblank_enabled)
+			dove_clear(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
+	}
+#endif
+
+	DRM_DEBUG_DRIVER("start %s@%d\n",
+			crtc->mode.name, crtc->mode.vrefresh);
+}
+
+void dove_crtc_stop(struct dove_lcd *dove_lcd)
+{
+	DRM_DEBUG_DRIVER("\n");
+
+	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_GRA_ENA);
+	dove_clear(dove_lcd, LCD_SPU_DUMB_CTRL, CFG_DUMB_ENA);
+#ifdef HANDLE_INTERLACE
+	if (dove_lcd->v_sync0
+	 && !dove_lcd->vblank_enabled)
+		dove_clear(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
+#endif
+}
+
+/* -----------------------------------------------------------------------------
+ * cursor
+ */
+
+/* load the hardware cursor */
+static int load_cursor(struct dove_lcd *dove_lcd,
+			struct drm_file *file_priv,
+			uint32_t handle,
+			int data_len)
+{
+	struct drm_gem_object *obj;
+	struct drm_gem_cma_object *cma_obj;
+	u8 *p_pixel;
+	u32 u, val;
+	u32 ram, color;
+	int i, j, ret;
+
+	obj = drm_gem_object_lookup(dove_drm.drm, file_priv, handle);
+	if (!obj)
+		return -ENOENT;
+
+	if (!obj->map_list.map) {
+		dev_warn(dove_lcd->dev, "cursor not mapped\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (data_len != obj->size) {
+		dev_warn(dove_lcd->dev, "bad cursor size\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	cma_obj = to_drm_gem_cma_obj(obj);
+	p_pixel = cma_obj->vaddr;
+
+	u = CFG_SRAM_INIT_WR_RD(SRAMID_INIT_WRITE) |
+			CFG_SRAM_ADDR_LCDID(SRAMID_HWC);
+	ram = CFG_SRAM_INIT_WR_RD(SRAMID_INIT_WRITE);
+
+	/* load the RGBA cursor to SRAM */
+	for (i = 0; i < data_len / 4 / 4; i++) {
+		color = (p_pixel[3 * 4 + 0] << 24) |	/* red */
+			(p_pixel[2 * 4 + 0] << 16) |
+			(p_pixel[1 * 4 + 0] << 8) |
+			p_pixel[0];
+		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, color);
+		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL,
+				ram | CFG_SRAM_ADDR_LCDID(SRAMID_HWC32_RAM1));
+		color = (p_pixel[3 * 4 + 1] << 24) |	/* green */
+			(p_pixel[2 * 4 + 1] << 16) |
+			(p_pixel[1 * 4 + 1] << 8) |
+			p_pixel[1];
+		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, color);
+		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL,
+				ram | CFG_SRAM_ADDR_LCDID(SRAMID_HWC32_RAM2));
+		color = (p_pixel[3 * 4 + 2] << 24) |	/* blue */
+			(p_pixel[2 * 4 + 2] << 16) |
+			(p_pixel[1 * 4 + 2] << 8) |
+			p_pixel[2];
+		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, color);
+		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL,
+				ram | CFG_SRAM_ADDR_LCDID(SRAMID_HWC32_RAM3));
+		p_pixel += 4 * 4;
+		if ((++ram & 0xff) == 0) {
+			ram -= 0x100;			/* I[7:0] */
+			ram += 1 << 12;			/* J[1:0] */
+		}
+	}
+
+	/* set the transparency */
+	p_pixel = cma_obj->vaddr;
+	for (i = 0; i < data_len / 16 / 4; i++) {
+		val = 0;
+		for (j = 16 * 4 - 4; j >= 0 ; j -= 4) {
+			val <<= 2;
+			if (p_pixel[j + 3])	/* alpha */
+				val |= 1;	/* not transparent */
+		}
+		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, val);
+		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL, u++);
+		p_pixel += 16 * 4;
+	}
+	ret = 0;
+out:
+	drm_gem_object_unreference_unlocked(obj);
+	return ret;
+}
+
+static int dove_cursor_set(struct drm_crtc *crtc,
+			struct drm_file *file_priv,
+			uint32_t handle,
+			uint32_t width,
+			uint32_t height)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+	int ret;
+
+	DRM_DEBUG_DRIVER("%dx%d handle %d\n", width, height, handle);
+
+	/* disable cursor */
+	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
+
+	if (!handle)
+		return 0;		/* cursor off */
+
+	if (width != 64 || height != 64) {
+		dev_err(dove_lcd->dev, "bad cursor size\n");
+		return -EINVAL;
+	}
+
+	/* load the cursor */
+	ret = load_cursor(dove_lcd, file_priv, handle, width * height * 4);
+	if (ret < 0)
+		return ret;
+
+	/* set cursor size */
+	dove_write(dove_lcd, LCD_SPU_HWC_HPXL_VLN, LCD_H_V(width, height));
+
+	/* enable cursor */
+	dove_set(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
+
+	return 0;
+}
+
+static int dove_cursor_move(struct drm_crtc *crtc,
+				int x, int y)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+
+	if (x < 0)
+		x = 0;
+	if (y < 0)
+		y = 0;
+	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
+	dove_write(dove_lcd, LCD_SPU_HWC_OVSA_HPXL_VLN, LCD_H_V(x, y));
+	dove_set(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
+	return 0;
+}
+
+static void dove_crtc_destroy(struct drm_crtc *crtc)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+
+	DRM_DEBUG_DRIVER("\n");
+
+	WARN_ON(dove_lcd->dpms == DRM_MODE_DPMS_ON);
+
+	drm_crtc_cleanup(crtc);
+}
+
+static int dove_crtc_page_flip(struct drm_crtc *crtc,
+			struct drm_framebuffer *fb,
+			struct drm_pending_vblank_event *event)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+	struct drm_device *drm = dove_drm.drm;
+	unsigned long flags;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	spin_lock_irqsave(&drm->event_lock, flags);
+	if (dove_lcd->event) {
+		spin_unlock_irqrestore(&drm->event_lock, flags);
+		dev_err(drm->dev, "already pending page flip!\n");
+		return -EBUSY;
+	}
+	spin_unlock_irqrestore(&drm->event_lock, flags);
+
+	crtc->fb = fb;
+	dove_update_base(dove_lcd);
+
+	if (event) {
+		event->pipe = 0;
+		spin_lock_irqsave(&drm->event_lock, flags);
+		dove_lcd->event = event;
+		spin_unlock_irqrestore(&drm->event_lock, flags);
+		drm_vblank_get(drm, dove_lcd->num);
+	}
+
+	return 0;
+}
+
+static void dove_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+
+	/* we really only care about on or off */
+	if (mode != DRM_MODE_DPMS_ON)
+		mode = DRM_MODE_DPMS_OFF;
+
+	DRM_DEBUG_DRIVER("dpms %s\n", mode == DRM_MODE_DPMS_ON ? "on" : "off");
+
+	if (dove_lcd->dpms == mode)
+		return;
+
+	dove_lcd->dpms = mode;
+
+	if (mode == DRM_MODE_DPMS_ON)
+		dove_crtc_start(dove_lcd);
+	else
+		dove_crtc_stop(dove_lcd);
+}
+
+static bool dove_crtc_mode_fixup(struct drm_crtc *crtc,
+				const struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode)
+{
+	DRM_DEBUG_DRIVER("\n");
+	if (adjusted_mode->vrefresh == 0) {
+/*		drm_mode_set_name(adjusted_mode); */
+		adjusted_mode->vrefresh = drm_mode_vrefresh(adjusted_mode);
+		DRM_DEBUG_DRIVER("%s@%d\n",
+				adjusted_mode->name, adjusted_mode->vrefresh);
+	}
+	return true;
+}
+
+static void dove_crtc_prepare(struct drm_crtc *crtc)
+{
+	DRM_DEBUG_DRIVER("\n");
+	dove_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+}
+
+static void dove_crtc_commit(struct drm_crtc *crtc)
+{
+	DRM_DEBUG_DRIVER("\n");
+/*	dove_crtc_dpms(crtc, DRM_MODE_DPMS_ON); */
+}
+
+static int dove_crtc_mode_set(struct drm_crtc *crtc,
+			struct drm_display_mode *mode,
+			struct drm_display_mode *adjusted_mode,
+			int x, int y,
+			struct drm_framebuffer *old_fb)
+{
+	unsigned int bandwidth;
+	DRM_DEBUG_DRIVER("\n");
+
+	if (mode->hdisplay > 2048)
+		return MODE_VIRTUAL_X;
+
+	/* width must be multiple of 16 */
+	if (mode->hdisplay & 0xf)
+		return MODE_VIRTUAL_X;
+
+	if (mode->vdisplay > 2048)
+		return MODE_VIRTUAL_Y;
+
+	/* filter out modes that would require too much memory bandwidth: */
+	bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode);
+	if (bandwidth > 1920 * 1080 * 60)
+		return MODE_BAD;
+
+/*fixme: is this useful? */
+	mode = &crtc->mode;
+	if (mode->vrefresh == 0) {
+		drm_mode_set_name(mode);
+		mode->vrefresh = drm_mode_vrefresh(mode);
+		DRM_DEBUG_DRIVER("%s@%d\n", mode->name, mode->vrefresh);
+	}
+	return MODE_OK;
+}
+
+static int dove_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
+				struct drm_framebuffer *old_fb)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+
+	DRM_DEBUG_DRIVER("\n");
+	dove_update_base(dove_lcd);
+	return 0;
+}
+
+/* mandatory drm function */
+static void dove_crtc_load_lut(struct drm_crtc *crtc)
+{
+	DRM_DEBUG_DRIVER("\n");
+}
+
+static const struct drm_crtc_funcs dove_crtc_funcs = {
+	.cursor_set	= dove_cursor_set,
+	.cursor_move	= dove_cursor_move,
+	.destroy        = dove_crtc_destroy,
+	.set_config     = drm_crtc_helper_set_config,
+	.page_flip      = dove_crtc_page_flip,
+};
+
+static const struct drm_crtc_helper_funcs dove_crtc_helper_funcs = {
+	.dpms           = dove_crtc_dpms,
+	.mode_fixup     = dove_crtc_mode_fixup,
+	.prepare        = dove_crtc_prepare,
+	.commit         = dove_crtc_commit,
+	.mode_set       = dove_crtc_mode_set,
+	.mode_set_base  = dove_crtc_mode_set_base,
+	.load_lut       = dove_crtc_load_lut,
+};
+
+void dove_crtc_cancel_page_flip(struct dove_lcd *dove_lcd,
+				struct drm_file *file)
+{
+	struct drm_pending_vblank_event *event;
+	struct drm_device *drm = dove_drm.drm;
+	unsigned long flags;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	/*
+	 * Destroy the pending vertical blanking event associated with the
+	 * pending page flip, if any, and disable vertical blanking interrupts.
+	 */
+	spin_lock_irqsave(&drm->event_lock, flags);
+	event = dove_lcd->event;
+	if (event && event->base.file_priv == file) {
+		dove_lcd->event = NULL;
+		event->base.destroy(&event->base);
+		drm_vblank_put(drm, dove_lcd->num);
+	}
+	spin_unlock_irqrestore(&drm->event_lock, flags);
+}
+
+/* configure default register values */
+static void dove_set_defaults(struct dove_lcd *dove_lcd)
+{
+	u32 x;
+
+	/* set the default clock */
+	if (dove_lcd->clk[SCLK_SRC_PLLDIV])
+		dove_lcd->clk_src = SCLK_SRC_PLLDIV;
+	else
+		dove_lcd->clk_src = SCLK_SRC_AXI;
+	DRM_DEBUG_DRIVER("default clock %d\n", dove_lcd->clk_src);
+
+	x = SET_SCLK(dove_lcd->clk_src, 1, 0);
+	dove_write(dove_lcd, LCD_CFG_SCLK_DIV, x);
+	dove_write(dove_lcd, LCD_SPU_BLANKCOLOR, 0);
+
+	dove_write(dove_lcd, SPU_IOPAD_CONTROL, IOPAD_DUMB24);
+	dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR1, 0);
+	dove_write(dove_lcd, LCD_SPU_GRA_OVSA_HPXL_VLN, 0);
+	dove_write(dove_lcd, LCD_SPU_SRAM_PARA0, 0);
+	dove_write(dove_lcd, LCD_SPU_SRAM_PARA1, CFG_CSB_256x32 |
+						CFG_CSB_256x24 |
+						CFG_CSB_256x8);
+	dove_write(dove_lcd, LCD_SPU_DMA_CTRL1, CFG_VSYNC_TRIG(2) |
+						CFG_GATED_ENA |
+						CFG_PWRDN_ENA |
+						CFG_ALPHA_MODE(2) |
+						CFG_ALPHA(0xff) |
+						CFG_PXLCMD(0x81));
+
+	/*
+	 * Fix me: to avoid jiggling issue for high resolution in
+	 * dual display, we set watermark to affect LCD AXI read
+	 * from MC (default 0x80). Lower watermark means LCD will
+	 * do DMA read more often.
+	 */
+	x = dove_read(dove_lcd, LCD_CFG_RDREG4F);
+	x &= ~DMA_WATERMARK_MASK;
+	x |= DMA_WATERMARK(0x20);
+
+	/*
+	 * Disable LCD SRAM Read Wait State to resolve HWC32 make
+	 * system hang while use external clock.
+	 */
+	x &= ~LCD_SRAM_WAIT;
+	dove_write(dove_lcd, LCD_CFG_RDREG4F, x);
+
+	/* prepare the hwc32 */
+	dove_set(dove_lcd, LCD_TV_CONTROL1, HWC32_ENABLE);
+
+	/* set hwc32 with 100% static alpha blending factor */
+	dove_write(dove_lcd, LCD_SPU_ALPHA_COLOR1,
+				HWC32_CFG_ALPHA(0xff));
+}
+
+static irqreturn_t dove_lcd_irq(int irq, void *dev_id)
+{
+	struct dove_lcd *dove_lcd = (struct dove_lcd *) dev_id;
+	struct drm_pending_vblank_event *event;
+	struct drm_device *drm = dove_drm.drm;
+	u32 isr;
+	unsigned long flags;
+
+	isr = dove_read(dove_lcd, SPU_IRQ_ISR);
+	dove_write(dove_lcd, SPU_IRQ_ISR, 0);
+
+	DRM_DEBUG_DRIVER("\n");
+
+	if (isr & IRQ_GRA_FRAME_DONE) {
+#ifdef HANDLE_INTERLACE
+		if (dove_lcd->v_sync0) {
+			u32 x;
+
+			x = dove_read(dove_lcd, LCD_TV_CONTROL1);
+			x &= ~(VSYNC_L_OFFSET_MASK | VSYNC_H_OFFSET_MASK);
+			if (isr & IRQ_GRA_FRAME0)
+				x |= dove_lcd->v_sync0;
+			else
+				x |= dove_lcd->v_sync1;
+			dove_write(dove_lcd, LCD_TV_CONTROL1, x);
+		}
+		if (dove_lcd->vblank_enabled)
+#endif
+		drm_handle_vblank(drm, dove_lcd->num); 
+		spin_lock_irqsave(&drm->event_lock, flags);
+		event = dove_lcd->event;
+		dove_lcd->event = NULL;
+		if (event)
+			drm_send_vblank_event(drm, dove_lcd->num, event);
+		spin_unlock_irqrestore(&drm->event_lock, flags);
+		if (event)
+			drm_vblank_put(drm, dove_lcd->num);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/* initialize a lcd */
+static int dove_crtc_init(struct dove_lcd *dove_lcd)
+{
+	struct drm_crtc *crtc = &dove_lcd->crtc;
+	int ret;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	dove_lcd->dpms = DRM_MODE_DPMS_OFF;
+
+	ret = drm_crtc_init(dove_drm.drm, crtc, &dove_crtc_funcs);
+	if (ret < 0)
+		goto fail;
+
+	dove_write(dove_lcd, SPU_IRQ_ENA, 0);	/* disable interrupts */
+	ret = devm_request_irq(dove_lcd->dev, dove_lcd->irq, dove_lcd_irq, 0,
+			dove_lcd->name, dove_lcd);
+	if (ret < 0) {
+		dev_err(dove_lcd->dev, "unable to request irq %d\n",
+				dove_lcd->irq);
+		goto fail;
+	}
+
+	if (ret < 0) {
+		dev_err(dove_lcd->dev, "failed to install IRQ handler\n");
+		goto fail;
+	}
+
+	dove_set_defaults(dove_lcd);
+	set_dumb_panel_control(dove_lcd, 1);
+
+	drm_crtc_helper_add(crtc, &dove_crtc_helper_funcs);
+
+	return 0;
+
+fail:
+	dove_crtc_destroy(crtc);
+	return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * Overlay plane
+ */
+
+static void plane_update_base(struct dove_lcd *dove_lcd,
+				int plane_num,
+				struct drm_framebuffer *fb,
+				int fmt,
+				int x, int y,
+				int w, int h)
+{
+	struct drm_gem_cma_object *gem;
+	unsigned int addr;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	gem = drm_fb_cma_get_gem_obj(fb, plane_num);
+
+	addr = gem->paddr + fb->offsets[0] + y * fb->pitches[0] + x;
+	dove_write(dove_lcd, LCD_SPU_DMA_START_ADDR_Y0, addr);
+
+	switch (fmt) {
+	case VMODE_YUV422PLANAR:
+	case VMODE_YUV420PLANAR:
+		addr += w * h / 2;	/* planar */
+		break;
+	}
+	dove_write(dove_lcd, LCD_SPU_DMA_START_ADDR_U0, addr);
+
+	switch (fmt) {
+	case VMODE_YUV422PLANAR:
+		addr += w * h / 2;
+		break;
+	case VMODE_YUV420PLANAR:
+		addr += w * h / 4;
+		break;
+	}
+	dove_write(dove_lcd, LCD_SPU_DMA_START_ADDR_V0, addr);
+
+	switch (fb->pixel_format) {
+	case VMODE_YUV422PACKED:
+		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_YC,
+						LCD_Y_C(w * 2, 0));
+		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_UV, LCD_U_V(w, w));
+		break;
+	default:
+/*	case VMODE_YUV422PLANAR: */
+/*	case VMODE_YUV420PLANAR: */
+		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_YC, LCD_Y_C(w, 0));
+		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_UV,
+						LCD_U_V(w / 2, w / 2));
+		break;
+	}
+}
+
+static int dove_plane_update(struct drm_plane *plane,
+			struct drm_crtc *crtc,
+			struct drm_framebuffer *fb,
+			int crtc_x, int crtc_y,
+			unsigned int crtc_w, unsigned int crtc_h,
+			uint32_t src_x, uint32_t src_y,
+			uint32_t src_w, uint32_t src_h)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
+	u32 x, x_bk;
+	int fmt, rbswap;
+
+	DRM_DEBUG_DRIVER("%d\n", plane == &dove_lcd->planes[PLANE_VID]);
+
+	if (plane != &dove_lcd->planes[PLANE_VID])
+		return 0;
+	rbswap = 1;				/* default */
+	switch (fb->pixel_format) {
+	case DRM_FORMAT_YVYU:
+		rbswap = 0;
+	case DRM_FORMAT_YUYV:
+	case DRM_FORMAT_UYVY:
+		fmt = VMODE_YUV422PACKED;
+		break;
+	case DRM_FORMAT_YVU422:
+		rbswap = 0;
+	case DRM_FORMAT_YUV422:
+		fmt = VMODE_YUV422PLANAR;
+		break;
+	case DRM_FORMAT_YVU420:
+		rbswap = 0;
+	default:
+/*	case DRM_FORMAT_YUV420: */
+		fmt = VMODE_YUV420PLANAR;
+		break;
+	}
+
+	x_bk = x = dove_read(dove_lcd, LCD_SPU_DMA_CTRL0);
+					/* clear video layer's field */
+	x &= ~(CFG_YUV2RGB_DMA | CFG_DMA_SWAP_MASK |
+		CFG_DMA_TSTMODE | CFG_DMA_HSMOOTH | CFG_DMA_FTOGGLE |
+		CFG_DMAFORMAT_MASK | CFG_PALETTE_ENA);
+	x |= CFG_DMA_HSMOOTH;		/* enable horizontal smooth scaling */
+	x |= CFG_DMAFORMAT(fmt);	/* configure hardware pixel format */
+/*fixme: no RGB */
+	if (fb->pixel_format == DRM_FORMAT_UYVY) {
+		x |= CFG_YUV2RGB_DMA;
+	} else if (fmt == VMODE_YUV422PACKED) {
+		x |= CFG_YUV2RGB_DMA |
+			CFG_DMA_SWAPYU |
+			CFG_DMA_SWAPRB;
+		if (rbswap)
+			x |= CFG_DMA_SWAPUV;
+	} else {				/* planar */
+		x |= CFG_YUV2RGB_DMA |
+			CFG_DMA_SWAPRB;
+		if (!rbswap)
+			x |= CFG_DMA_SWAPUV;
+	}
+	if (x != x_bk)
+		dove_write(dove_lcd, LCD_SPU_DMA_CTRL0, x);
+
+	/* set the dma addresses */
+	plane_update_base(dove_lcd, PLANE_VID,
+			fb, fmt, src_x, src_y, src_w, src_h);
+
+	/* original size */
+	dove_write(dove_lcd, LCD_SPU_DMA_HPXL_VLN,
+				LCD_H_V(src_w, src_h));
+
+	/* scaled size */
+	dove_write(dove_lcd, LCD_SPU_DZM_HPXL_VLN,
+				LCD_H_V(crtc_w, crtc_h));
+
+	/* update video position offset */
+	dove_write(dove_lcd, LCD_SPUT_DMA_OVSA_HPXL_VLN,
+				LCD_H_V(crtc_x, crtc_y));
+	return 0;
+}
+
+static int dove_plane_disable(struct drm_plane *plane)
+{
+	struct dove_lcd *dove_lcd = to_dove_lcd(plane->crtc);
+
+	DRM_DEBUG_DRIVER("%d\n",
+			plane == &dove_lcd->planes[PLANE_VID]);
+
+	if (plane != &dove_lcd->planes[PLANE_VID])
+		return 0;
+
+	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_DMA_ENA);
+	return 0;
+}
+
+static void dove_plane_destroy(struct drm_plane *plane)
+{
+	dove_plane_disable(plane);
+	drm_plane_cleanup(plane);
+}
+
+static const struct drm_plane_funcs plane_funcs = {
+	.update_plane = dove_plane_update,
+	.disable_plane = dove_plane_disable,
+	.destroy = dove_plane_destroy,
+};
+static const uint32_t gfx_formats[] = {
+	DRM_FORMAT_BGR888,
+	DRM_FORMAT_RGB888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVU422,
+	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU420,
+	DRM_FORMAT_YUV420,
+};
+static const uint32_t vid_formats[] = {
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVU422,
+	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU420,
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_UYVY,
+};
+
+static int dove_planes_init(struct dove_lcd *dove_lcd)
+{
+	struct drm_device *drm = dove_drm.drm;
+	struct drm_plane *plane;
+	int ret;
+
+	if (false) {
+		plane = &dove_lcd->planes[PLANE_VID];
+		ret = drm_plane_init(drm, plane, 1 << dove_lcd->num,
+				&plane_funcs,
+				gfx_formats, ARRAY_SIZE(gfx_formats), true);
+		if (ret < 0)
+			return ret;
+		plane->crtc = &dove_lcd->crtc;
+	}
+	plane = &dove_lcd->planes[PLANE_VID];
+	ret = drm_plane_init(drm, plane, 1 << dove_lcd->num,
+				&plane_funcs,
+				vid_formats, ARRAY_SIZE(vid_formats), false);
+	if (ret < 0)
+		return ret;
+	plane->crtc = &dove_lcd->crtc;
+	return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+int dove_lcd_init(struct dove_lcd *dove_lcd)
+{
+	int ret;
+
+	ret = dove_crtc_init(dove_lcd);
+	if (ret < 0)
+		return ret;
+	ret = dove_planes_init(dove_lcd);
+	if (ret < 0)
+		dev_err(dove_lcd->dev, "failed to create the planes\n");
+
+	return ret;
+}
+
+/* at probe time, get the possible LCD clocks */
+static int get_lcd_clocks(struct dove_lcd *dove_lcd)
+{
+	struct device *dev = dove_lcd->dev;
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args clkspec;
+	struct clk *clk;
+	int i, no_clock, ret;
+
+	no_clock = 1;
+	for (i = 0; i < MAX_CLK; i++) {
+
+		/* check first if there is a phandle to the clock */
+		ret = of_parse_phandle_with_args(np,
+					"clocks", "#clock-cells", i,
+					&clkspec);
+		if (ret)
+			continue;		/* no defined clock here */
+		of_node_put(clkspec.np);
+
+		/* if no clock driver, ignore this clock */
+		clk = of_clk_get(np, i);
+		if (IS_ERR(clk)) {
+			if (!dove_drm.probe_defer) {
+				dove_drm.probe_defer = 1;
+				return -EPROBE_DEFER;
+			}
+			dev_err(dev, "no driver for clock %i\n", i);
+			continue;
+		}
+		DRM_DEBUG_DRIVER("clock %d ok\n", i);
+		clk_prepare_enable(clk);
+		dove_lcd->clk[i] = clk;
+		no_clock = 0;
+	}
+	if (no_clock) {
+		dev_err(dev, "no available clock\n");
+		return -EINVAL;
+	}
+	if (!dove_lcd->clk[SCLK_SRC_PLLDIV] && !dove_lcd->clk[SCLK_SRC_AXI]) {
+		dev_err(dev, "no fixed clock\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int dove_lcd_remove(struct platform_device *pdev)
+{
+	struct dove_lcd *dove_lcd = platform_get_drvdata(pdev);
+	struct clk *clk;
+	int i;
+
+	dove_write(dove_lcd, SPU_IRQ_ENA, 0);	/* disable interrupts */
+
+	if (dove_drm.lcds[dove_lcd->num] == dove_lcd)
+		dove_drm.lcds[dove_lcd->num] = NULL;
+
+	for (i = 0; i < MAX_CLK; i++) {
+		clk = dove_lcd->clk[i];
+		if (clk) {
+			clk_disable_unprepare(clk);
+			clk_put(clk);
+		}
+	}
+	
+	kfree(dove_lcd);
+	return 0;
+}
+
+static int dove_lcd_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct dove_lcd *dove_lcd;
+	struct resource *res;
+	int ret;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	/* bail out early if no DT data */
+	if (!np) {
+		dev_err(dev, "no device-tree\n");
+		return -ENXIO;
+	}
+
+	dove_lcd = kzalloc(sizeof *dove_lcd, GFP_KERNEL);
+	if (!dove_lcd) {
+		dev_err(dev, "failed to allocate private data\n");
+		return -ENOMEM;
+	}
+	platform_set_drvdata(pdev, dove_lcd);
+	dove_lcd->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "failed to get memory resource\n");
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	dove_lcd->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dove_lcd->mmio)) {
+		dev_err(dev, "failed map registers\n");
+		ret = PTR_ERR(dove_lcd->mmio);
+		dove_lcd->mmio = NULL;
+		goto fail;
+	}
+
+	switch (((u32) dove_lcd->mmio) & DOVE_LCD_REG_BASE_MASK) {
+	case DOVE_LCD0_REG_BASE:
+/*		dove_lcd->num = 0; */
+		break;
+	case DOVE_LCD1_REG_BASE:
+		dove_lcd->num = 1;
+		break;
+	default:
+		dev_err(dev, "unknown lcd reg base %08x\n",
+					(u32) dove_lcd->mmio);
+		ret = -EINVAL;
+		goto fail;
+	}
+	snprintf(dove_lcd->name, sizeof dove_lcd->name, "dove-lcd%d",
+			dove_lcd->num);
+	dove_drm.lcds[dove_lcd->num] = dove_lcd;
+
+	dove_lcd->irq = irq_of_parse_and_map(np, 0);
+	if (dove_lcd->irq < 0 || dove_lcd->irq == NO_IRQ) {
+		dev_err(dev, "unable to get irq lcd %d\n", dove_lcd->num);
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	ret = get_lcd_clocks(dove_lcd);
+	if (ret < 0)
+		goto fail;
+
+	/* check the presence of a possible external slave encoder */
+	ret = dove_ec_probe(dove_lcd);
+	if (ret < 0)
+		goto fail;
+
+	/* init done, try to initialize the drm driver */
+	return dove_probed();
+
+fail:
+	dove_lcd_remove(pdev);
+	return ret;
+}
+
+static struct of_device_id dove_lcd_of_match[] = {
+	{ .compatible = "marvell,dove-lcd" },
+	{ },
+};
+struct platform_driver dove_lcd_platform_driver = {
+	.driver     = {
+		.owner  = THIS_MODULE,
+		.name   = "dove-lcd",
+		.of_match_table = dove_lcd_of_match,
+	},
+	.probe      = dove_lcd_probe,
+	.remove     = dove_lcd_remove,
+};
diff --git a/drivers/gpu/drm/dove/dove_dcon.h b/drivers/gpu/drm/dove/dove_dcon.h
new file mode 100644
index 0000000..da2b99c
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_dcon.h
@@ -0,0 +1,64 @@
+/*
+ * Display controller registers of Marvell DOVE
+ *
+ * Copyright (C) 2013
+ *   Jean-Francois Moine <moinejf at free.fr>
+ *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DOVE_DCON_H_
+#define	_DOVE_DCON_H_
+
+/* ------------< DCON register >------------ */
+
+#define DCON_CTL0		0x0000
+#define   VGA_CLK_DISABLE		BIT(25)
+#define   DCON_CLK_DISABLE		BIT(24)
+#define   DCON_RST			BIT(23)
+#define   LCD_Disable			BIT(17)
+#define   Reverse_Scan			BIT(10)
+#define   LCD_Port_B_Select_MASK	0x00000300
+#define		Port_B_Select_LCD1	0x00000000
+#define		Port_B_Select_LCD0	0x00000100
+#define		Port_B_Select_A_copy	0x00000300
+#define   LCD_Port_A_Select_MASK	0x000000c0
+#define		Port_A_Select_LCD	0x00000000
+#define		Port_A_Select_OLPC	0x00000040
+#define		Port_A_Select_Dual	0x00000080
+#define		Port_A_Select_ext	0x000000c0
+#define   LBUF_EN			BIT(5)
+#define DCON_IRQ_CTL		0x0008
+#define   IRQ_Control_MASK		0x00ff0000
+#define DITHER_REG_R		0x0050
+#define DITHER_REG_G		0x0054
+#define DITHER_REG_B		0x0058
+#define DCON_DITHER_PAT_RL	0x0060
+#define DCON_DITHER_PAT_RH	0x0064
+#define DCON_DITHER_PAT_GL	0x0068
+#define DCON_DITHER_PAT_GH	0x006c
+#define DCON_DITHER_PAT_BL	0x0070
+#define DCON_DITHER_PAT_BH	0x0074
+#define VGA_Global		0x0080
+#define VGA_CHA			0x0084
+#define VGA_CHB			0x0088
+#define VGA_CHC			0x008c
+#define VGA_CHA_STA		0x0090
+#define VGA_CHB_STA		0x0094
+#define VGA_CHC_STA		0x0098
+#define CT_LUT_INDEX		0x00a4
+#define CT_LUT_DATA		0x00a8
+#define FTDLL_CTL		0x00c0
+
+#endif /* _DOVE_DCON_H_ */
diff --git a/drivers/gpu/drm/dove/dove_drv.c b/drivers/gpu/drm/dove/dove_drv.c
new file mode 100644
index 0000000..e9e77ad
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_drv.c
@@ -0,0 +1,380 @@
+/*
+ * Marvell Dove DRM driver - main
+ *
+ * Copyright (C) 2013
+ *   Jean-Francois Moine <moinejf at free.fr>
+ *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+
+#include "dove_drv.h"
+
+#define DRIVER_NAME	"dove-drm"
+#define DRIVER_DESC	"Marvell Dove DRM"
+#define DRIVER_DATE	"20130516"
+#define DRIVER_MAJOR	1
+#define DRIVER_MINOR	0
+
+struct dove_drm dove_drm;
+static struct platform_device *g_pdev;
+static atomic_t probed;
+
+static struct drm_framebuffer *dove_fb_create(struct drm_device *drm,
+					struct drm_file *file_priv,
+					struct drm_mode_fb_cmd2 *mode_cmd)
+{
+	DRM_DEBUG_DRIVER("fmt %.4s\n", (char *) &mode_cmd->pixel_format);
+
+	switch (mode_cmd->pixel_format) {
+	case DRM_FORMAT_BGR888:
+	case DRM_FORMAT_RGB888:
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_ABGR8888:
+	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_YVYU:
+	case DRM_FORMAT_YUYV:
+	case DRM_FORMAT_YVU422:
+	case DRM_FORMAT_YUV422:
+	case DRM_FORMAT_YVU420:
+	case DRM_FORMAT_YUV420:
+		break;
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+	return drm_fb_cma_create(drm, file_priv, mode_cmd);
+}
+
+static void dove_fb_output_poll_changed(struct drm_device *drm)
+{
+	DRM_DEBUG_DRIVER("fb:%d\n", dove_drm.fbdev != NULL);
+	if (dove_drm.fbdev)
+		drm_fbdev_cma_hotplug_event(dove_drm.fbdev);
+}
+
+static const struct drm_mode_config_funcs mode_config_funcs = {
+	.fb_create = dove_fb_create,
+	.output_poll_changed = dove_fb_output_poll_changed,
+};
+
+/*
+ * DRM operations:
+ */
+static int dove_unload(struct drm_device *drm)
+{
+	struct dove_lcd *dove_lcd;
+	int i;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	for (i = 0; i < MAX_DOVE_LCD; i++) {
+		dove_lcd = dove_drm.lcds[i];
+		if (dove_lcd) {
+			if (dove_lcd->planes[PLANE_VID].dev)
+				drm_plane_cleanup(&dove_lcd->planes[PLANE_VID]);
+			if (dove_lcd->planes[PLANE_GFX].dev)
+				drm_plane_cleanup(&dove_lcd->planes[PLANE_GFX]);
+		}
+	}
+	drm_kms_helper_poll_fini(drm);
+	drm_mode_config_cleanup(drm);
+	drm_vblank_cleanup(drm);
+
+	return 0;
+}
+
+/* this function is called when all LCDs and dcon have been probed */
+static int dove_load(struct drm_device *drm, unsigned long flags)
+{
+	struct platform_device *pdev = drm->platformdev;
+	struct dove_lcd *dove_lcd;
+	int i, ret;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	dove_drm.drm = drm;
+	platform_set_drvdata(pdev, &dove_drm);
+	drm->dev_private = &dove_drm;
+
+	drm_mode_config_init(drm);
+
+/*	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); */
+
+	for (i = 0; i < MAX_DOVE_LCD; i++) {
+		dove_lcd = dove_drm.lcds[i];
+		if (dove_lcd) {
+			ret = dove_lcd_init(dove_lcd);
+			if (ret < 0)
+				goto fail;
+			ret = dove_ec_init(dove_lcd);
+			if (ret < 0)
+				goto fail;
+		}
+	}
+
+	drm->mode_config.min_width = 0;
+	drm->mode_config.min_height = 0;
+	drm->mode_config.max_width = 2048;
+	drm->mode_config.max_height = 2048;
+	drm->mode_config.funcs = &mode_config_funcs;
+
+	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+	if (ret < 0) {
+		dev_err(drm->dev, "failed to initialize vblank\n");
+		goto fail;
+	}
+
+	dove_drm.fbdev = drm_fbdev_cma_init(drm,
+					32,	/* bpp */
+					drm->mode_config.num_crtc,
+					drm->mode_config.num_connector);
+
+	drm_kms_helper_poll_init(drm);
+	return 0;
+fail:
+	dove_unload(drm);
+	return ret;
+}
+
+static void dove_preclose(struct drm_device *drm, struct drm_file *file)
+{
+	struct dove_lcd *dove_lcd;
+	int i;
+
+	for (i = 0; i < MAX_DOVE_LCD; i++) {
+		dove_lcd = dove_drm.lcds[i];
+		if (dove_lcd)
+			dove_crtc_cancel_page_flip(dove_lcd, file);
+	}
+}
+
+static void dove_lastclose(struct drm_device *drm)
+{
+	drm_fbdev_cma_restore_mode(dove_drm.fbdev);
+}
+
+static int dove_gem_cma_dumb_create(struct drm_file *file_priv,
+				struct drm_device *dev,
+				struct drm_mode_create_dumb *args)
+{
+	if (args->height * args->width * args->bpp == 0) {
+		dev_err(dev->dev, "dumb_create %dx%d bpp %d!\n",
+			args->height, args->width, args->bpp);
+		return -ENOMEM;
+	}
+	return drm_gem_cma_dumb_create(file_priv, dev, args);
+}
+
+static const struct file_operations fops = {
+	.owner		= THIS_MODULE,
+	.open		= drm_open,
+	.release	= drm_release,
+	.unlocked_ioctl	= drm_ioctl,
+	.poll		= drm_poll,
+	.read		= drm_read,
+	.fasync		= drm_fasync,
+	.llseek		= no_llseek,
+	.mmap		= drm_gem_cma_mmap,
+};
+
+static struct drm_driver dove_driver = {
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET,
+	.load			= dove_load,
+	.unload			= dove_unload,
+	.preclose		= dove_preclose,
+	.lastclose		= dove_lastclose,
+	.get_vblank_counter	= dove_vblank_count,
+	.enable_vblank		= dove_enable_vblank,
+	.disable_vblank		= dove_disable_vblank,
+	.gem_free_object	= drm_gem_cma_free_object,
+	.gem_vm_ops		= &drm_gem_cma_vm_ops,
+	.dumb_create		= dove_gem_cma_dumb_create,
+	.dumb_map_offset	= drm_gem_cma_dumb_map_offset,
+	.dumb_destroy		= drm_gem_cma_dumb_destroy,
+#ifdef CONFIG_DEBUG_FS
+	.debugfs_init		= dove_debugfs_init,
+	.debugfs_cleanup	= dove_debugfs_cleanup,
+#endif
+	.fops			= &fops,
+
+	.name			= DRIVER_NAME,
+	.desc			= DRIVER_DESC,
+	.date			= DRIVER_DATE,
+	.major			= DRIVER_MAJOR,
+	.minor			= DRIVER_MINOR,
+};
+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * Power management
+ */
+static int dove_pm_suspend(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct dove_lcd *dove_lcd;
+	int i;
+
+	drm_kms_helper_poll_disable(drm);
+	for (i = 0; i < MAX_DOVE_LCD; i++) {
+		dove_lcd = dove_drm.lcds[i];
+		if (dove_lcd)
+			dove_crtc_stop(dove_lcd);
+	}
+	return 0;
+}
+
+static int dove_pm_resume(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct dove_lcd *dove_lcd;
+	int i;
+
+	for (i = 0; i < MAX_DOVE_LCD; i++) {
+		dove_lcd = dove_drm.lcds[i];
+		if (dove_lcd
+		 && dove_lcd->dpms == DRM_MODE_DPMS_ON)
+			dove_crtc_start(dove_lcd);
+	}
+	drm_kms_helper_poll_enable(drm);
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops dove_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(dove_pm_suspend, dove_pm_resume)
+};
+
+/*
+ * Platform driver
+ */
+
+/* count the number of awaited sub devices */
+static int dove_subdev_cnt(void)
+{
+	struct device_node *np;
+	unsigned int n;
+	static struct of_device_id dove_of_subdev[] = {
+		{ .compatible = "marvell,dove-lcd" },
+		{ .compatible = "marvell,dove-dcon" },
+		{ },
+	};
+
+	n = 0;
+	np = NULL;
+	for (;;) {
+		np = of_find_matching_node_and_match(np,
+						dove_of_subdev, NULL);
+		if (!np)
+			break;
+		if (of_device_is_available(np))
+			n++;
+	}
+	return n;
+}
+
+int dove_probed(void)
+{
+	if (atomic_add_return(1, &probed) == 0)
+		return drm_platform_init(&dove_driver, g_pdev);
+	return 0;
+}
+
+static int dove_pdev_probe(struct platform_device *pdev)
+{
+	int awaited;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	g_pdev = pdev;
+
+	awaited = dove_subdev_cnt();
+	if (awaited == 0) {
+		dev_err(&pdev->dev, "no lcd nor dcon devices\n");
+		return -ENXIO;
+	}
+	if (atomic_sub_return(awaited, &probed) == 0)
+		return drm_platform_init(&dove_driver, pdev);
+	return 0;
+}
+
+static int dove_pdev_remove(struct platform_device *pdev)
+{
+	drm_platform_exit(&dove_driver, pdev);
+	return 0;
+}
+
+static struct of_device_id dove_of_match[] = {
+	{ .compatible = "marvell,dove-video" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, dove_of_match);
+
+static struct platform_driver dove_platform_driver = {
+	.probe      = dove_pdev_probe,
+	.remove     = dove_pdev_remove,
+	.driver     = {
+		.owner  = THIS_MODULE,
+		.name   = "dove-drm",
+		.pm     = &dove_pm_ops,
+		.of_match_table = dove_of_match,
+	},
+};
+
+static int __init dove_drm_init(void)
+{
+	int ret;
+
+	/* wait for other drivers to be loaded (si5351, tda998x..) */
+	msleep(200);
+
+/* uncomment to activate the drm trace at startup time */
+/*	drm_debug = DRM_UT_CORE | DRM_UT_DRIVER | DRM_UT_KMS; */
+
+	DRM_DEBUG_DRIVER("\n");
+
+	ret = platform_driver_register(&dove_lcd_platform_driver);
+	if (ret < 0)
+		return ret;
+	ret = platform_driver_register(&dove_dcon_platform_driver);
+	if (ret < 0)
+		goto out1;
+	ret = platform_driver_register(&dove_platform_driver);
+	if (ret < 0)
+		goto out2;
+	return 0;
+
+out2:
+	platform_driver_unregister(&dove_dcon_platform_driver);
+out1:
+	platform_driver_unregister(&dove_lcd_platform_driver);
+	return ret;
+}
+static void __exit dove_drm_fini(void)
+{
+	platform_driver_unregister(&dove_platform_driver);
+	platform_driver_unregister(&dove_dcon_platform_driver);
+	platform_driver_unregister(&dove_lcd_platform_driver);
+}
+module_init(dove_drm_init);
+module_exit(dove_drm_fini);
+
+MODULE_AUTHOR("Jean-Francois Moine <moinejf at free.fr>");
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
+MODULE_DESCRIPTION("Marvell Dove DRM Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/dove/dove_drv.h b/drivers/gpu/drm/dove/dove_drv.h
new file mode 100644
index 0000000..7488c7e
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_drv.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2013 Jean-Fran?ois Moine
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DOVE_DRV_H__
+#define __DOVE_DRV_H__
+
+#include <linux/clk.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_encoder_slave.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+
+/* (not tested) */
+/*#define HANDLE_INTERLACE 1*/
+
+#define MAX_DOVE_LCD 2		/* max number of dove lcd devices */
+#define MAX_CLK 4		/* max number of clocks per crtc */
+
+#define PLANE_GFX 0
+#define PLANE_VID 1
+#define NPLANES 2
+
+struct dove_lcd {
+	void __iomem *mmio;
+	struct device *dev;
+	struct drm_crtc crtc;
+
+	u8 num;			/* index in dove_drm */
+	u8 dpms;
+
+#ifdef HANDLE_INTERLACE
+	u8 vblank_enabled;
+	u32 v_sync0;
+	u32 v_sync1;
+#endif
+
+	short clk_src;		/* current clock source */
+	struct clk *clk[MAX_CLK];
+
+	int irq;
+	char name[16];
+
+	struct drm_pending_vblank_event *event;
+
+	struct drm_plane planes[NPLANES];
+
+	struct drm_connector connector;
+	struct drm_encoder_slave encoder_slave;
+};
+
+struct dove_drm {
+	struct drm_device *drm;
+	struct dove_lcd *lcds[MAX_DOVE_LCD];
+
+	struct drm_fbdev_cma *fbdev;
+	int probe_defer;
+};
+
+extern struct dove_drm dove_drm;
+int dove_probed(void);
+
+u32 dove_vblank_count(struct drm_device *dev, int crtc);
+int dove_enable_vblank(struct drm_device *dev, int crtc);
+void dove_disable_vblank(struct drm_device *dev, int crtc);
+int dove_lcd_init(struct dove_lcd *dove_lcd);
+void dove_crtc_cancel_page_flip(struct dove_lcd *dove_lcd,
+				struct drm_file *file);
+void dove_crtc_start(struct dove_lcd *dove_lcd);
+void dove_crtc_stop(struct dove_lcd *dove_lcd);
+#ifdef CONFIG_DEBUG_FS
+int dove_debugfs_init(struct drm_minor *minor);
+void dove_debugfs_cleanup(struct drm_minor *minor);
+#endif
+extern struct platform_driver dove_lcd_platform_driver;
+
+int dove_ec_probe(struct dove_lcd *dove_lcd);
+int dove_ec_init(struct dove_lcd *dove_lcd);
+extern struct platform_driver dove_dcon_platform_driver;
+#endif /* __DOVE_DRV_H__ */
diff --git a/drivers/gpu/drm/dove/dove_ec.c b/drivers/gpu/drm/dove/dove_ec.c
new file mode 100644
index 0000000..003b031
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_ec.c
@@ -0,0 +1,570 @@
+/*
+ * Marvell Dove DRM driver - encoder / connector and display controller
+ *
+ * Copyright (C) 2013
+ *   Jean-Francois Moine <moinejf at free.fr>
+ *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/i2c.h>
+#include <linux/of_i2c.h>
+#include <linux/module.h>
+
+#include "dove_drv.h"
+#include "dove_dcon.h"
+
+struct dove_dcon {
+	void __iomem *mmio;
+	struct device *dev;
+};
+static struct dove_dcon dove_dcon;
+
+/* -----------------------------------------------------------------------------
+ * Encoder
+ */
+/* LVDS and VGA/DAC functions */
+static void dove_encoder_dpms(struct drm_encoder *encoder, int mode)
+{
+}
+static bool dove_encoder_mode_fixup(struct drm_encoder *encoder,
+				const struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+static void dove_encoder_prepare(struct drm_encoder *encoder)
+{
+}
+static void dove_encoder_commit(struct drm_encoder *encoder)
+{
+}
+static void dove_encoder_mode_set(struct drm_encoder *encoder,
+				struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode)
+{
+}
+
+static const struct drm_encoder_helper_funcs lvds_encoder_helper_funcs = {
+	.dpms = dove_encoder_dpms,
+	.mode_fixup = dove_encoder_mode_fixup,
+	.prepare = dove_encoder_prepare,
+	.commit = dove_encoder_commit,
+	.mode_set = dove_encoder_mode_set,
+};
+
+/* HDMI (i2c) functions */
+static const struct drm_encoder_helper_funcs hdmi_encoder_helper_funcs = {
+	.dpms = drm_i2c_encoder_dpms,
+	.mode_fixup = drm_i2c_encoder_mode_fixup,
+	.prepare = drm_i2c_encoder_prepare,
+	.commit = drm_i2c_encoder_commit,
+	.mode_set = drm_i2c_encoder_mode_set,
+};
+
+static void dove_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	struct drm_encoder_slave *encoder_slave = to_encoder_slave(encoder);
+	struct i2c_client *i2c_client;
+	struct module *module;
+
+	if (encoder_slave->slave_funcs)
+		encoder_slave->slave_funcs->destroy(encoder);
+	i2c_client = encoder_slave->bus_priv;
+	if (i2c_client) {
+		module = i2c_client->driver->driver.owner;
+		module_put(module);
+	}
+	if (encoder->dev)
+		drm_encoder_cleanup(encoder);
+}
+
+static const struct drm_encoder_funcs encoder_funcs = {
+	.destroy = dove_drm_encoder_destroy,
+};
+
+static int dove_encoder_get_hdmi(struct dove_lcd *dove_lcd)
+{
+	struct device *dev = dove_lcd->dev;
+	struct drm_device *drm = dove_drm.drm;
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+	struct drm_encoder *encoder = &encoder_slave->base;
+	struct drm_connector *connector = &dove_lcd->connector;
+	struct i2c_client *i2c_client;
+	struct module *module;
+	struct drm_i2c_encoder_driver *encoder_drv;
+	int ret;
+
+	i2c_client = encoder_slave->bus_priv;
+	if (!i2c_client) {
+		dev_err(dev, "no external-encoder for hdmi\n");
+		return -EINVAL;
+	}
+
+	encoder_drv = to_drm_i2c_encoder_driver(i2c_client->driver);
+	if (!encoder_drv || !encoder_drv->encoder_init) {
+		dev_err(dev, "no external encoder init\n");
+		return -EINVAL;
+	}
+
+	/* lock the external encoder module */
+	module = i2c_client->driver->driver.owner;
+	if (!module || !try_module_get(module)) {
+		dev_err(dev, "cannot get module %s\n", module->name);
+		return -EINVAL;
+	}
+
+	ret = encoder_drv->encoder_init(i2c_client, drm, encoder_slave);
+	if (ret < 0) {
+		dev_err(dev, "slave encoder init failed\n");
+		return ret;
+	}
+	encoder_slave->slave_funcs->create_resources(encoder, connector);
+	return ret;
+}
+
+static int dove_encoder_init(struct dove_lcd *dove_lcd,
+				int mode_encoder)
+{
+	struct drm_device *drm = dove_drm.drm;
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+	struct drm_encoder *encoder = &encoder_slave->base;
+	int ret;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	/* do early init in case of error */
+	ret = drm_encoder_init(drm, encoder, &encoder_funcs, mode_encoder);
+	if (ret < 0) {
+		dev_err(dove_lcd->dev, "drm encoder init failed\n");
+		return ret;
+	}
+
+	encoder->possible_crtcs = 1 << dove_lcd->num;
+
+	/*
+	 * If the display controller is present,
+	 * - the port A cannot be VGA/DAC,
+	 * - the port B can be only VGA/DAC and may receive the lcd 0 output.
+	 */
+	if (dove_dcon.mmio) {
+		if (dove_lcd->num == 0) {
+			if (mode_encoder == DRM_MODE_ENCODER_DAC) {
+				dev_err(dove_lcd->dev,
+						"bad lcd 0 port-type\n");
+				return -EINVAL;
+			}
+		} else {
+			if (mode_encoder != DRM_MODE_ENCODER_DAC) {
+				dev_err(dove_lcd->dev,
+						"bad lcd 1 port-type\n");
+				return -EINVAL;
+			}
+			encoder->possible_crtcs |= 1;
+
+			/* the port B may receive the LCD 0 output */
+			encoder->possible_clones = 1;
+		}
+	}
+
+	switch (mode_encoder) {
+	case DRM_MODE_ENCODER_DAC:
+/*fixme: to do */
+	case DRM_MODE_ENCODER_LVDS:
+		drm_encoder_helper_add(encoder, &lvds_encoder_helper_funcs);
+		ret = 0;
+		break;
+	case DRM_MODE_ENCODER_TMDS:
+		drm_encoder_helper_add(encoder, &hdmi_encoder_helper_funcs);
+		ret = dove_encoder_get_hdmi(dove_lcd);
+		break;
+	}
+	return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * Connector
+ */
+
+static int dove_lvds_get_modes(struct dove_lcd *dove_lcd)
+{
+	struct device *dev = dove_lcd->dev;
+	struct device_node *np = dev->of_node;
+	struct drm_connector *connector = &dove_lcd->connector;
+	struct drm_display_mode *mode;
+	int clock, hdisplay, vdisplay, hfp, hbp, vfp, vbp, hs, vs;
+	int w_mm, h_mm;
+	int ret;
+
+	/* same as of_videomode, but simpler! */
+	np = of_find_node_by_name(np, "display-timings");
+	if (!np) {
+		dev_err(dev, "no display-timings\n");
+		return -EINVAL;
+	}
+	np = of_get_next_child(np, NULL);
+	if (!np) {
+		dev_err(dev, "no 'mode' subnode in DT\n");
+		return -EINVAL;
+	}
+
+	ret = 0;
+	ret |= of_property_read_u32(np, "hactive", &hdisplay);
+	ret |= of_property_read_u32(np, "vactive", &vdisplay);
+	ret |= of_property_read_u32(np, "hfront-porch", &hfp);
+	ret |= of_property_read_u32(np, "hsync-len", &hs);
+	ret |= of_property_read_u32(np, "hback-porch", &hbp);
+	ret |= of_property_read_u32(np, "vfront-porch", &vfp);
+	ret |= of_property_read_u32(np, "vsync-len", &vs);
+	ret |= of_property_read_u32(np, "vback-porch", &vbp);
+	ret |= of_property_read_u32(np, "clock", &clock);
+	if (ret) {
+		dev_err(dev, "bad display-timings\n");
+		return -EINVAL;
+	}
+	if (clock < 15000 || clock > 150000) {
+		dev_err(dev, "bad clock\n");
+		return -EINVAL;
+	}
+
+	mode = drm_mode_create(dove_drm.drm);
+	if (!mode) {
+		ret = -ENOMEM;
+		return ret;
+	}
+
+	mode->clock = clock;
+	mode->hdisplay = hdisplay;
+	mode->hsync_start = hdisplay + hfp;
+	mode->hsync_end = mode->hsync_start + hs;
+	mode->htotal = mode->hsync_end + hbp;
+	mode->vdisplay = vdisplay;
+	mode->vsync_start = vdisplay + vfp;
+	mode->vsync_end = mode->vsync_start + vs;
+	mode->vtotal = mode->vsync_end + vbp;
+
+	drm_mode_set_name(mode);
+	mode->vrefresh = drm_mode_vrefresh(mode);
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(connector, mode);
+
+	/* optional display dimension */
+	ret = of_property_read_u32(np, "width-mm", &w_mm);
+	ret |= of_property_read_u32(np, "height-mm", &h_mm);
+	if (ret >= 0) {
+		connector->display_info.width_mm = w_mm;
+		connector->display_info.height_mm = h_mm;
+	}
+	return 1;
+}
+
+static int dove_drm_connector_get_modes(struct drm_connector *connector)
+{
+	struct dove_lcd *dove_lcd = 
+		container_of(connector, struct dove_lcd, connector);
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+	int ret;
+
+	switch (connector->connector_type) {
+	case DRM_MODE_CONNECTOR_VGA:
+/*fixme:to do */
+	case DRM_MODE_CONNECTOR_LVDS:
+		ret = dove_lvds_get_modes(dove_lcd);
+		break;
+	default:
+/*	case DRM_MODE_CONNECTOR_HDMIA: */
+/*	case DRM_MODE_CONNECTOR_HDMIB: */
+		ret = encoder_slave->slave_funcs->get_modes(&encoder_slave->base,
+							connector);
+		break;
+	}
+	DRM_DEBUG_DRIVER("-> %d\n", ret);
+	return ret;
+}
+
+static int dove_drm_connector_mode_valid(struct drm_connector *connector,
+					  struct drm_display_mode *mode)
+{
+	struct dove_lcd *dove_lcd = 
+		container_of(connector, struct dove_lcd, connector);
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+
+	if (!encoder_slave->slave_funcs)
+		return MODE_OK;
+	return encoder_slave->slave_funcs->mode_valid(&encoder_slave->base,
+							mode);
+}
+
+static struct drm_encoder *
+dove_drm_connector_best_encoder(struct drm_connector *connector)
+{
+	struct dove_lcd *dove_lcd = 
+		container_of(connector, struct dove_lcd, connector);
+
+	return &dove_lcd->encoder_slave.base;
+}
+
+static const struct drm_connector_helper_funcs connector_helper_funcs = {
+	.get_modes = dove_drm_connector_get_modes,
+	.mode_valid = dove_drm_connector_mode_valid,
+	.best_encoder = dove_drm_connector_best_encoder,
+};
+
+static void dove_drm_connector_destroy(struct drm_connector *connector)
+{
+	if (!connector->dev)
+		return;
+	drm_sysfs_connector_remove(connector);
+	drm_connector_cleanup(connector);
+}
+
+static enum drm_connector_status
+dove_drm_connector_detect(struct drm_connector *connector, bool force)
+{
+	struct dove_lcd *dove_lcd = 
+		container_of(connector, struct dove_lcd, connector);
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+
+	DRM_DEBUG_DRIVER("\n");
+	if (encoder_slave->slave_funcs)
+		return encoder_slave->slave_funcs->detect(&encoder_slave->base,
+							connector);
+/*fixme: KO with VGA*/
+	return connector_status_connected;
+}
+
+static void dove_drm_connector_dpms(struct drm_connector *connector,
+				int mode)
+{
+	struct dove_lcd *dove_lcd =
+		container_of(connector, struct dove_lcd, connector);
+	struct drm_encoder *encoder = connector->encoder;
+	struct drm_encoder_slave *encoder_slave = to_encoder_slave(encoder);
+	struct dove_lcd *dove_lcd2 =
+		container_of(encoder_slave, struct dove_lcd, encoder_slave);
+	int modeA, modeB;
+	u32 reg;
+
+	if (mode == dove_lcd->connector.dpms)
+		return;
+
+	/* adjust the port B input */
+	if (dove_dcon.mmio) {
+		reg = readl(dove_dcon.mmio + DCON_CTL0);
+		reg &= ~LCD_Port_B_Select_MASK;
+		if (dove_lcd2 != dove_lcd) {
+			if (dove_lcd->num == 0) {
+				modeA = mode;
+				modeB = dove_lcd2->connector.dpms;
+			} else {
+				modeA = dove_lcd->connector.dpms;
+				modeB = mode;
+			}
+
+			if (modeB == DRM_MODE_DPMS_ON) {
+				if (modeA == DRM_MODE_DPMS_ON)
+					reg |= Port_B_Select_A_copy;
+				else
+					reg |= Port_B_Select_LCD0;
+			}
+		}
+		writel(reg, dove_dcon.mmio + DCON_CTL0);
+		DRM_DEBUG_DRIVER("port B select %08x\n", reg);
+	}
+
+	drm_helper_connector_dpms(connector, mode);
+}
+
+static int dove_connector_set_property(struct drm_connector *connector,
+				struct drm_property *property,
+				uint64_t value)
+{
+	struct dove_lcd *dove_lcd = 
+		container_of(connector, struct dove_lcd, connector);
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+
+	DRM_DEBUG_DRIVER("\n");
+	if (!encoder_slave->slave_funcs)
+		return 0;
+	return encoder_slave->slave_funcs->set_property(&encoder_slave->base,
+							connector,
+							property,
+							value);
+}
+
+static const struct drm_connector_funcs connector_funcs = {
+	.destroy = dove_drm_connector_destroy,
+	.dpms = dove_drm_connector_dpms,
+	.detect = dove_drm_connector_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.set_property = dove_connector_set_property,
+};
+
+/* initialize the couple connector-encoder of a LCD */
+int dove_ec_init(struct dove_lcd *dove_lcd)
+{
+	struct device *dev = dove_lcd->dev;
+	struct device_node *np = dev->of_node;
+	struct drm_device *drm = dove_drm.drm;
+	struct drm_connector *connector = &dove_lcd->connector;
+	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
+	struct drm_encoder *encoder = &encoder_slave->base;
+	u32 port_type;
+	int mode_encoder, ret;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	/* get the port (connector) type */
+	if (of_property_read_u32(np, "marvell,port-type", &port_type)) {
+		dev_err(dev, "no port-type\n");
+		return -EINVAL;
+	}
+	switch (port_type) {
+	case DRM_MODE_CONNECTOR_VGA:		/* 1 */
+		mode_encoder = DRM_MODE_ENCODER_DAC;
+		break;
+	case DRM_MODE_CONNECTOR_LVDS:		/* 7 */
+		mode_encoder = DRM_MODE_ENCODER_LVDS;
+		break;
+	case DRM_MODE_CONNECTOR_HDMIA:		/* 11 */
+	case DRM_MODE_CONNECTOR_HDMIB:		/* 12 */
+		mode_encoder = DRM_MODE_ENCODER_TMDS;
+		break;
+	default:
+		dev_err(dev, "bad port type %d\n", port_type);
+		return -EINVAL;
+	}
+
+	ret = drm_connector_init(drm, connector, &connector_funcs, port_type);
+	if (ret < 0)
+		return ret;
+
+	drm_connector_helper_add(connector, &connector_helper_funcs);
+
+#ifdef HANDLE_INTERLACE
+	connector->interlace_allowed = true;
+#endif
+
+	ret = dove_encoder_init(dove_lcd, mode_encoder);
+	if (ret < 0)
+		goto err;
+
+	ret = drm_mode_connector_attach_encoder(connector, encoder);
+	if (ret < 0)
+		goto err;
+
+	connector->encoder = encoder;
+
+	ret = drm_sysfs_connector_add(connector);
+	if (ret < 0)
+		goto err;
+
+	drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+	ret = drm_object_property_set_value(&connector->base,
+					drm->mode_config.dpms_property,
+					DRM_MODE_DPMS_OFF);
+	if (ret < 0)
+		goto err;
+	return 0;
+
+err:
+	dev_err(dev, "dove_ec_init err %d\n", ret);
+	dove_drm_encoder_destroy(&encoder_slave->base);
+	drm_connector_cleanup(connector);
+	return ret;
+}
+
+/* at probe time, check the presence of a possible external slave encoder */
+int dove_ec_probe(struct dove_lcd *dove_lcd)
+{
+	struct device *dev = dove_lcd->dev;
+	struct device_node *np = dev->of_node;
+	struct device_node *i2c_node;
+	struct i2c_client *i2c_client;
+
+	/* get the optional external encoder */
+	i2c_node = of_parse_phandle(np, "marvell,external-encoder", 0);
+	if (!i2c_node)
+		return 0;
+
+	i2c_client = of_find_i2c_device_by_node(i2c_node);
+	of_node_put(i2c_node);
+	if (!i2c_client) {
+		dev_err(dev, "bad external-encoder\n");
+		return -EINVAL;
+	}
+
+	/* check if the slave-encoder module is initialized */
+	if (!i2c_client->driver) {
+		if (dove_drm.probe_defer) {
+			dev_err(dev, "cannot get the external-encoder\n");
+			return -EINVAL;
+		}
+		dove_drm.probe_defer = 1;
+		return -EPROBE_DEFER;
+	}
+
+	dove_lcd->encoder_slave.bus_priv = i2c_client;
+	return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Display controller
+ */
+
+static int dove_dcon_remove(struct platform_device *pdev)
+{
+	dove_dcon.mmio = NULL;
+	return 0;
+}
+
+static int dove_dcon_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	void __iomem *mmio;
+
+	DRM_DEBUG_DRIVER("\n");
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get dcon resource\n");
+		return -EINVAL;
+	}
+
+	mmio = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mmio)) {
+		dev_err(&pdev->dev, "failed map dcon registers\n");
+		return PTR_ERR(mmio);
+	}
+
+	dove_dcon.mmio = mmio;
+	dove_dcon.dev = &pdev->dev;
+
+	/* init done, try to initialize the drm driver */
+	return dove_probed();
+}
+
+static struct of_device_id dove_dcon_of_match[] = {
+	{ .compatible = "marvell,dove-dcon" },
+	{ },
+};
+struct platform_driver dove_dcon_platform_driver = {
+	.driver     = {
+		.owner  = THIS_MODULE,
+		.name   = "dove-dcon",
+		.of_match_table = dove_dcon_of_match,
+	},
+	.probe      = dove_dcon_probe,
+	.remove     = dove_dcon_remove,
+};
diff --git a/drivers/gpu/drm/dove/dove_lcd.h b/drivers/gpu/drm/dove/dove_lcd.h
new file mode 100644
index 0000000..03b198b
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_lcd.h
@@ -0,0 +1,519 @@
+/*
+ * LCD controller registers of Marvell DOVE
+ *
+ * Copyright (C) 2013
+ *   Jean-Francois Moine <moinejf at free.fr>
+ *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DOVE_LCD_H_
+#define	_DOVE_LCD_H_
+
+/* ------------< LCD register >------------ */
+
+/* Video Frame 0&1 start address registers */
+#define	LCD_TV_CONTROL1			0x0084
+#define   VSYNC_L_OFFSET(o)			((o) << 20)
+#define   VSYNC_L_OFFSET_MASK			(0xfff << 20)
+#define   HWC32_ENABLE				BIT(13)
+#define   VSYNC_OFFSET_EN			BIT(12)
+#define   VSYNC_H_OFFSET(o)			(o)
+#define   VSYNC_H_OFFSET_MASK			0xfff
+
+/* Video Frame 0&1 start address registers */
+#define	LCD_SPU_DMA_START_ADDR_Y0	0x00c0
+#define	LCD_SPU_DMA_START_ADDR_U0	0x00c4
+#define	LCD_SPU_DMA_START_ADDR_V0	0x00c8
+#define LCD_CFG_DMA_START_ADDR_0	0x00cc /* Cmd address */
+#define	LCD_SPU_DMA_START_ADDR_Y1	0x00d0
+#define	LCD_SPU_DMA_START_ADDR_U1	0x00d4
+#define	LCD_SPU_DMA_START_ADDR_V1	0x00d8
+#define LCD_CFG_DMA_START_ADDR_1	0x00dc /* Cmd address */
+
+/* YC & UV Pitch */
+#define LCD_SPU_DMA_PITCH_YC		0x00e0
+#define   LCD_Y_C(y, c)				(((c) << 16) | (y))
+#define LCD_SPU_DMA_PITCH_UV		0x00e4
+#define   LCD_U_V(u, v)				(((v) << 16) | (u))
+
+/* Video Starting Point on Screen Register */
+#define LCD_SPUT_DMA_OVSA_HPXL_VLN	0x00e8
+
+/* Video Size Register */
+#define LCD_SPU_DMA_HPXL_VLN		0x00ec
+
+/* Video Size After zooming Register */
+#define LCD_SPU_DZM_HPXL_VLN		0x00f0
+
+/* Graphic Frame 0&1 Starting Address Register */
+#define LCD_CFG_GRA_START_ADDR0		0x00f4
+#define LCD_CFG_GRA_START_ADDR1		0x00f8
+
+/* Graphic Frame Pitch */
+#define LCD_CFG_GRA_PITCH		0x00fc
+
+/* Graphic Starting Point on Screen Register */
+#define LCD_SPU_GRA_OVSA_HPXL_VLN	0x0100
+
+/* Graphic Size Register */
+#define LCD_SPU_GRA_HPXL_VLN		0x0104
+
+/* Graphic Size after Zooming Register */
+#define LCD_SPU_GZM_HPXL_VLN		0x0108
+
+/* HW Cursor Starting Point on Screen Register */
+#define LCD_SPU_HWC_OVSA_HPXL_VLN	0x010c
+
+/* HW Cursor Size */
+#define LCD_SPU_HWC_HPXL_VLN		0x0110
+
+/* Total Screen Size Register */
+#define LCD_SPUT_V_H_TOTAL		0x0114
+
+/* Total Screen Active Size Register */
+#define LCD_SPU_V_H_ACTIVE		0x0118
+#define   LCD_H_V(h, v)				(((v) << 16) | (h))
+#define   H_LCD(x)				((x) & 0xffff)
+#define   V_LCD(x)				(((x) >> 16) & 0xffff)
+
+/* Screen H&V Porch Register */
+#define LCD_SPU_H_PORCH			0x011c
+#define LCD_SPU_V_PORCH			0x0120
+#define   LCD_F_B(f, b)				(((b) << 16) | (f))
+#define   F_LCD(x)				((x) & 0xffff)
+#define   B_LCD(x)				(((x) >> 16) & 0xffff)
+
+/* Screen Blank Color Register */
+#define LCD_SPU_BLANKCOLOR		0x0124
+
+/* HW Cursor Color 1&2 Register */
+#define LCD_SPU_ALPHA_COLOR1		0x0128
+#define   HWC32_CFG_ALPHA(alpha)		((alpha) << 24)
+#define LCD_SPU_ALPHA_COLOR2		0x012c
+#define   COLOR_MASK				0x00ffffff
+#define   COLOR_RGB(r, g, b) (((b) << 16) | ((g) << 8) | (r))
+
+/* Video YUV Color Key Control */
+#define LCD_SPU_COLORKEY_Y		0x0130
+#define   CFG_CKEY_Y2(y2)			((y2) << 24)
+#define   CFG_CKEY_Y2_MASK			0xff000000
+#define   CFG_CKEY_Y1(y1)			((y1) << 16)
+#define   CFG_CKEY_Y1_MASK			0x00ff0000
+#define   CFG_CKEY_Y(y)				((y) << 8)
+#define   CFG_CKEY_Y_MASK			0x0000ff00
+#define   CFG_ALPHA_Y(y)			(y)
+#define   CFG_ALPHA_Y_MASK			0x000000ff
+#define LCD_SPU_COLORKEY_U		0x0134
+#define   CFG_CKEY_U2(u2)			((u2) << 24)
+#define   CFG_CKEY_U2_MASK			0xff000000
+#define   CFG_CKEY_U1(u1)			((u1) << 16)
+#define   CFG_CKEY_U1_MASK			0x00ff0000
+#define   CFG_CKEY_U(u)				((u) << 8)
+#define   CFG_CKEY_U_MASK			0x0000ff00
+#define   CFG_ALPHA_U(u)			(u)
+#define   CFG_ALPHA_U_MASK			0x000000ff
+#define LCD_SPU_COLORKEY_V		0x0138
+#define   CFG_CKEY_V2(v2)			((v2) << 24)
+#define   CFG_CKEY_V2_MASK			0xff000000
+#define   CFG_CKEY_V1(v1)			((v1) << 16)
+#define   CFG_CKEY_V1_MASK			0x00ff0000
+#define   CFG_CKEY_V(v)				((v) << 8)
+#define   CFG_CKEY_V_MASK			0x0000ff00
+#define   CFG_ALPHA_V(v)			(v)
+#define   CFG_ALPHA_V_MASK			0x000000ff
+
+/* LCD General Configuration Register */
+#define LCD_CFG_RDREG4F			0x013c
+#define   LCD_SRAM_WAIT				BIT(11)
+#define   DMA_WATERMARK_MASK			0xff
+#define   DMA_WATERMARK(m)			(m)
+
+/* SPI Read Data Register */
+#define LCD_SPU_SPI_RXDATA		0x0140
+
+/* Smart Panel Read Data Register */
+#define LCD_SPU_ISA_RSDATA		0x0144
+#define   ISA_RXDATA_16BIT_1_DATA_MASK		0x000000ff
+#define   ISA_RXDATA_16BIT_2_DATA_MASK		0x0000ff00
+#define   ISA_RXDATA_16BIT_3_DATA_MASK		0x00ff0000
+#define   ISA_RXDATA_16BIT_4_DATA_MASK		0xff000000
+#define   ISA_RXDATA_32BIT_1_DATA_MASK		0x00ffffff
+
+/* HWC SRAM Read Data Register */
+#define LCD_SPU_HWC_RDDAT		0x0158
+
+/* Gamma Table SRAM Read Data Register */
+#define LCD_SPU_GAMMA_RDDAT		0x015c
+#define   GAMMA_RDDAT_MASK			0x000000ff
+
+/* Palette Table SRAM Read Data Register */
+#define LCD_SPU_PALETTE_RDDAT		0x0160
+#define   PALETTE_RDDAT_MASK			0x00ffffff
+
+/* I/O Pads Input Read Only Register */
+#define LCD_SPU_IOPAD_IN		0x0178
+#define   IOPAD_IN_MASK				0x0fffffff
+
+/* Reserved Read Only Registers */
+#define LCD_CFG_RDREG5F			0x017c
+#define   IRE_FRAME_CNT_MASK			0x000000c0
+#define   IPE_FRAME_CNT_MASK			0x00000030
+#define   GRA_FRAME_CNT_MASK			0x0000000c	/* Graphic */
+#define   DMA_FRAME_CNT_MASK			0x00000003	/* Video */
+
+/* SPI Control Register. */
+#define LCD_SPU_SPI_CTRL		0x0180
+#define   CFG_SCLKCNT(div)			((div) << 24)
+#define   CFG_SCLKCNT_MASK			0xff000000
+#define   CFG_RXBITS(rx)			((rx) << 16)
+#define   CFG_RXBITS_MASK			0x00ff0000
+#define   CFG_TXBITS(tx)			((tx) << 8)
+#define   CFG_TXBITS_MASK			0x0000ff00
+#define   CFG_CLKINV				BIT(7)
+#define   CFG_KEEPXFER				BIT(6)
+#define   CFG_RXBITSTO0				BIT(5)
+#define   CFG_TXBITSTO0				BIT(4)
+#define   CFG_SPI_ENA				BIT(3)
+#define   CFG_SPI_SEL				BIT(2)
+#define   CFG_SPI_3W4WB				BIT(1)
+#define   CFG_SPI_START				BIT(0)
+
+/* SPI Tx Data Register */
+#define LCD_SPU_SPI_TXDATA		0x0184
+
+/*
+ *  1. Smart Pannel 8-bit Bus Control Register.
+ *  2. AHB Slave Path Data Port Register
+ */
+#define LCD_SPU_SMPN_CTRL		0x0188
+
+/* DMA Control 0 Register */
+#define LCD_SPU_DMA_CTRL0		0x0190
+#define   CFG_NOBLENDING			BIT(31)
+#define   CFG_GAMMA_ENA				BIT(30)
+#define   CFG_CBSH_ENA				BIT(29)
+#define   CFG_PALETTE_ENA			BIT(28)
+#define   CFG_ARBFAST_ENA			BIT(27)
+#define   CFG_HWC_1BITMOD			BIT(26)
+#define   CFG_HWC_1BITENA			BIT(25)
+#define   CFG_HWC_ENA				BIT(24)
+#define   CFG_DMAFORMAT(dmaformat)		((dmaformat) << 20)
+#define   CFG_DMAFORMAT_MASK			0x00f00000
+#define   CFG_GRAFORMAT(graformat)		((graformat) << 16)
+#define   CFG_GRAFORMAT_MASK			0x000f0000
+/* for graphic part */
+#define   CFG_GRA_FTOGGLE			BIT(15)
+#define   CFG_GRA_HSMOOTH			BIT(14)
+#define   CFG_GRA_TSTMODE			BIT(13)
+#define   CFG_GRA_SWAPRB			BIT(12)
+#define   CFG_GRA_SWAPUV			BIT(11)
+#define   CFG_GRA_SWAPYU			BIT(10)
+#define   CFG_YUV2RGB_GRA			BIT(9)
+#define   CFG_GRA_ENA				BIT(8)
+/* for video part */
+#define   CFG_DMA_FTOGGLE			BIT(7)
+#define   CFG_DMA_HSMOOTH			BIT(6)
+#define   CFG_DMA_TSTMODE			BIT(5)
+#define   CFG_DMA_SWAPRB			BIT(4)
+#define   CFG_DMA_SWAPUV			BIT(3)
+#define   CFG_DMA_SWAPYU			BIT(2)
+#define   CFG_DMA_SWAP_MASK			0x0000001c
+#define   CFG_YUV2RGB_DMA			BIT(1)
+#define   CFG_DMA_ENA				BIT(0)
+
+/* DMA Control 1 Register */
+#define LCD_SPU_DMA_CTRL1		0x0194
+#define   CFG_FRAME_TRIG			BIT(31)
+#define   CFG_VSYNC_TRIG(trig)			((trig) << 28)
+#define   CFG_VSYNC_TRIG_MASK			0x70000000
+#define   CFG_VSYNC_INV				BIT(27)
+#define   CFG_COLOR_KEY_MODE(cmode)		((cmode) << 24)
+#define   CFG_COLOR_KEY_MASK			0x07000000
+#define   CFG_CARRY				BIT(23)
+#define   CFG_GATED_ENA				BIT(21)
+#define   CFG_PWRDN_ENA				BIT(20)
+#define   CFG_DSCALE(dscale)			((dscale) << 18)
+#define   CFG_DSCALE_MASK			0x000c0000
+#define   CFG_ALPHA_MODE(amode)			((amode) << 16)
+#define   CFG_ALPHA_MODE_MASK			0x00030000
+#define   CFG_ALPHA(alpha)			((alpha) << 8)
+#define   CFG_ALPHA_MASK			0x0000ff00
+#define   CFG_PXLCMD(pxlcmd)			(pxlcmd)
+#define   CFG_PXLCMD_MASK			0x000000ff
+
+/* SRAM Control Register */
+#define LCD_SPU_SRAM_CTRL		0x0198
+#define   CFG_SRAM_INIT_WR_RD(mode)		((mode) << 14)
+#define   CFG_SRAM_INIT_WR_RD_MASK		0x0000c000
+#define   CFG_SRAM_ADDR_LCDID(id)		((id) << 8)
+#define   CFG_SRAM_ADDR_LCDID_MASK		0x00000f00
+#define   CFG_SRAM_ADDR(addr)			(addr)
+#define   CFG_SRAM_ADDR_MASK			0x000000ff
+
+/* SRAM Write Data Register */
+#define LCD_SPU_SRAM_WRDAT		0x019c
+
+/* SRAM RTC/WTC Control Register */
+#define LCD_SPU_SRAM_PARA0		0x01a0
+
+/* SRAM Power Down Control Register */
+#define LCD_SPU_SRAM_PARA1		0x01a4
+#define   CFG_CSB_256x32			BIT(15)		/* HWC */
+#define   CFG_CSB_256x24			BIT(14)		/* Palette */
+#define   CFG_CSB_256x8				BIT(13)		/* Gamma */
+#define   CFG_PDWN256x32			BIT(7)		/* HWC */
+#define   CFG_PDWN256x24			BIT(6)		/* Palette */
+#define   CFG_PDWN256x8				BIT(5)		/* Gamma */
+#define   CFG_PDWN32x32				BIT(3)
+#define   CFG_PDWN16x66				BIT(2)
+#define   CFG_PDWN32x66				BIT(1)
+#define   CFG_PDWN64x66				BIT(0)
+
+/* Smart or Dumb Panel Clock Divider */
+#define LCD_CFG_SCLK_DIV		0x01a8
+#define   SET_SCLK(src, div, frac) (((src) << 30) | ((frac) << 16 ) | (div))
+
+/* Video Contrast Register */
+#define LCD_SPU_CONTRAST		0x01ac
+#define   CFG_BRIGHTNESS(bright)		((bright) << 16)
+#define   CFG_BRIGHTNESS_MASK			0xffff0000
+#define   CFG_CONTRAST(contrast)		(contrast)
+#define   CFG_CONTRAST_MASK			0x0000ffff
+
+/* Video Saturation Register */
+#define LCD_SPU_SATURATION		0x01b0
+#define   CFG_C_MULTS(mult)			((mult) << 16)
+#define   CFG_C_MULTS_MASK			0xffff0000
+#define   CFG_SATURATION(sat)			(sat)
+#define   CFG_SATURATION_MASK			0x0000ffff
+
+/* Video Hue Adjust Register */
+#define LCD_SPU_CBSH_HUE		0x01b4
+#define   CFG_SIN0(sin0)			((sin0) << 16)
+#define   CFG_SIN0_MASK				0xffff0000
+#define   CFG_COS0(con0)			(con0)
+#define   CFG_COS0_MASK				0x0000ffff
+
+/* Dump LCD Panel Control Register */
+#define LCD_SPU_DUMB_CTRL		0x01b8
+#define   CFG_DUMBMODE(mode)			((mode) << 28)
+#define   CFG_DUMBMODE_MASK			0xf0000000
+#define   CFG_LCDGPIO_O(data)			((data) << 20)
+#define   CFG_LCDGPIO_O_MASK			0x0ff00000
+#define   CFG_LCDGPIO_ENA(gpio)			((gpio) << 12)
+#define   CFG_LCDGPIO_ENA_MASK			0x000ff000
+#define   CFG_BIAS_OUT				BIT(8)
+#define   CFG_REVERSE_RGB			BIT(7)
+#define   CFG_INV_COMPBLANK			BIT(6)
+#define   CFG_INV_COMPSYNC			BIT(5)
+#define   CFG_INV_HENA				BIT(4)
+#define   CFG_INV_VSYNC				BIT(3)
+#define   CFG_INV_HSYNC				BIT(2)
+#define   CFG_INV_PCLK				BIT(1)
+#define   CFG_DUMB_ENA				BIT(0)
+
+/* LCD I/O Pads Control Register */
+#define SPU_IOPAD_CONTROL		0x01bc
+#define   CFG_VSC_LINEAR(vm)			((vm) << 18)	/* gfx */
+#define   CFG_VSC_LINEAR_MASK			0x000c0000
+#define   CFG_GRA_VM_ENA			BIT(15)		/* gfx */
+#define   CFG_DMA_VM_ENA			BIT(14)		/* video */
+#define   CFG_CMD_VM_ENA			BIT(13)
+#define   CFG_CSC(csc)				((csc) << 8)
+#define   CFG_CSC_MASK				0x00000300
+#define   CFG_AXICTRL(axi)			((axi) << 4)
+#define   CFG_AXICTRL_MASK			0x000000f0
+#define   CFG_IOPADMODE(iopad)			(iopad)
+#define   CFG_IOPADMODE_MASK			0x0000000f
+
+/* LCD Interrupt Control Register */
+#define SPU_IRQ_ENA			0x1c0
+/* LCD Interrupt Status Register */
+#define SPU_IRQ_ISR			0x1c4
+#define   IRQ_DMA_FRAME0			BIT(31)
+#define   IRQ_DMA_FRAME1			BIT(30)
+#define   IRQ_DMA_FIFO_UNDERFLOW		BIT(29)
+#define   IRQ_GRA_FRAME0			BIT(27)
+#define   IRQ_GRA_FRAME1			BIT(26)
+#define   IRQ_GRA_FIFO_UNDERFLOW		BIT(25)
+#define   IRQ_SMART_VSYNC			BIT(23)
+#define   IRQ_DUMB_FRAME_DONE			BIT(22)
+#define   IRQ_SMART_FRAME_DONE			BIT(21)
+#define   IRQ_HWCURSOR_FRAME_DONE		BIT(20)
+#define   IRQ_AHB_CMD_EMPTY			BIT(19)
+#define   IRQ_SPI_TRANSFER_DONE			BIT(18)
+#define   IRQ_POWERDOWN				BIT(17)
+#define   IRQ_AXI_ERROR				BIT(16)
+/* read only status */
+#define   STA_DMA_FRAME0			BIT(15)
+#define   STA_DMA_FRAME1			BIT(14)
+#define   STA_DMA_FRAME_COUNT(x) (((x) & (BIT(13) | BIT(12))) >> 12)
+#define   STA_GRA_FRAME0			BIT(11)
+#define   STA_GRA_FRAME1			BIT(10)
+#define   STA_GRA_FRAME_COUNT(x) (((x) & (BIT(9) | BIT(8))) >> 8)
+#define   STA_SMART_VSYNC			BIT(7)
+#define   STA_DUMB_FRAME_DONE			BIT(6)
+#define   STA_SMART_FRAME_DONE			BIT(5)
+#define   STA_HWCURSOR_FRAME_DONE		BIT(4)
+#define   STA_AHB_CMD_EMPTY			BIT(3)
+#define   STA_DMA_FIFO_EMPTY			BIT(2)
+#define   STA_GRA_FIFO_EMPTY			BIT(1)
+#define   STA_POWERDOWN				BIT(0)
+
+#define IRQ_DMA_FRAME_DONE			(IRQ_DMA_FRAME0 | IRQ_DMA_FRAME1)
+#define IRQ_GRA_FRAME_DONE \
+			(IRQ_GRA_FRAME0 | IRQ_GRA_FRAME1 | IRQ_SMART_VSYNC)
+
+/*
+ * defined Video Memory Color format for DMA control 0 register
+ * DMA0 bit[23:20]
+ */
+#define VMODE_RGB565		0x0
+#define VMODE_RGB1555		0x1
+#define VMODE_RGB888PACKED	0x2
+#define VMODE_RGB888UNPACKED	0x3
+#define VMODE_RGBA888		0x4
+#define VMODE_YUV422PACKED	0x5
+#define VMODE_YUV422PLANAR	0x6
+#define VMODE_YUV420PLANAR	0x7
+#define VMODE_SMPNCMD		0x8
+#define VMODE_PALETTE4BIT	0x9
+#define VMODE_PALETTE8BIT	0xa
+#define VMODE_RESERVED		0xb
+
+/*
+ * defined Graphic Memory Color format for DMA control 0 register
+ * DMA0 bit[19:16]
+ */
+#define GMODE_RGB565		0x0
+#define GMODE_RGB1555		0x1
+#define GMODE_RGB888PACKED	0x2
+#define GMODE_RGB888UNPACKED	0x3
+#define GMODE_RGBA888		0x4
+#define GMODE_YUV422PACKED	0x5
+#define GMODE_YUV422PLANAR	0x6
+#define GMODE_YUV420PLANAR	0x7
+#define GMODE_SMPNCMD		0x8
+#define GMODE_PALETTE4BIT	0x9
+#define GMODE_PALETTE8BIT	0xa
+#define GMODE_RESERVED		0xb
+
+/*
+ * define for DMA control 1 register
+ */
+#define DMA1_FRAME_TRIG		31	/* bit location */
+#define DMA1_VSYNC_MODE		28
+#define DMA1_VSYNC_INV		27
+#define DMA1_CKEY		24
+#define DMA1_CARRY		23
+#define DMA1_LNBUF_ENA		22
+#define DMA1_GATED_ENA		21
+#define DMA1_PWRDN_ENA		20
+#define DMA1_DSCALE		18
+#define DMA1_ALPHA_MODE		16
+#define DMA1_ALPHA		 8
+#define DMA1_PXLCMD		 0
+
+/*
+ * defined for Configure Dumb Mode
+ * DUMB LCD Panel bit[31:28]
+ */
+#define DUMB16_RGB565_0		0x0
+#define DUMB16_RGB565_1		0x1
+#define DUMB18_RGB666_0		0x2
+#define DUMB18_RGB666_1		0x3
+#define DUMB12_RGB444_0		0x4
+#define DUMB12_RGB444_1		0x5
+#define DUMB24_RGB888_0		0x6
+#define DUMB_BLANK		0x7
+
+/*
+ * defined for Configure I/O Pin Allocation Mode
+ * LCD LCD I/O Pads control register bit[3:0]
+ */
+#define IOPAD_DUMB24		0x0
+#define IOPAD_DUMB18SPI		0x1
+#define IOPAD_DUMB18GPIO	0x2
+#define IOPAD_DUMB16SPI		0x3
+#define IOPAD_DUMB16GPIO	0x4
+#define IOPAD_DUMB12		0x5
+#define IOPAD_SMART18SPI	0x6
+#define IOPAD_SMART16SPI	0x7
+#define IOPAD_SMART8BOTH	0x8
+
+/*
+ * clock source SCLK_Source bit[31:30]
+ */
+#define SCLK_SRC_AXI 0
+#define SCLK_SRC_EXTCLK0 1
+#define SCLK_SRC_PLLDIV 2
+#define SCLK_SRC_EXTCLK1 3
+
+/*
+ * defined Dumb Panel Clock Divider register
+ * SCLK_Source bit[31]
+ */
+#define AXI_BUS_SEL		0x80000000	/* 0: PLL clock select*/
+#define CCD_CLK_SEL		0x40000000
+#define DCON_CLK_SEL		0x20000000
+#define IDLE_CLK_INT_DIV	0x1		/* idle Integer Divider */
+#define DIS_CLK_INT_DIV		0x0		/* Disable Integer Divider */
+
+/* SRAM ID */
+#define SRAMID_GAMMA_YR		0x0
+#define SRAMID_GAMMA_UG		0x1
+#define SRAMID_GAMMA_VB		0x2
+#define SRAMID_PALETTE		0x3
+#define SRAMID_HWC32_RAM1	0xc
+#define SRAMID_HWC32_RAM2	0xd
+#define SRAMID_HWC32_RAM3	0xe
+#define SRAMID_HWC		0xf
+
+/* SRAM INIT Read/Write */
+#define SRAMID_INIT_READ	0x0
+#define SRAMID_INIT_WRITE	0x2
+#define SRAMID_INIT_DEFAULT	0x3
+
+/*
+ * defined VSYNC selection mode for DMA control 1 register
+ * DMA1 bit[30:28]
+ */
+#define VMODE_SMPN		0x0
+#define VMODE_SMPNIRQ		0x1
+#define VMODE_DUMB		0x2
+#define VMODE_IPE		0x3
+#define VMODE_IRE		0x4
+
+/*
+ * defined Configure Alpha and Alpha mode for DMA control 1 register
+ * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode)
+ */
+/* ALPHA mode */
+#define MODE_ALPHA_DMA		0xa0
+#define MODE_ALPHA_GRA		0x1
+#define MODE_ALPHA_CFG		0x2
+
+/* alpha value */
+#define ALPHA_NOGRAPHIC		0xff	/* all video, no graphic */
+#define ALPHA_NOVIDEO		0x00	/* all graphic, no video */
+#define ALPHA_GRAPHnVIDEO	0x0f	/* Selects graphic & video */
+
+/*
+ * defined Pixel Command for DMA control 1 register
+ * DMA1 bit[07:00]
+ */
+#define PIXEL_CMD		0x81
+
+#endif /* _DOVE_LCD_H_ */


-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From lee.jones at linaro.org  Thu May 16 07:27:20 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:20 +0100
Subject: [PATCH 0/6] crypto: ux500/[cryp|hash] - Enable Device Tree
Message-ID: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>

This patch-set simply allows ux500-[cryp|hash] drivers to be probed
when Snowball is running with Device Tree enabled.

Linus,

Feel free to split the DTS changes out into your ux500-devicetree branch.

 arch/arm/boot/dts/dbx5x0.dtsi         |   17 +++++++++++++++++
 arch/arm/boot/dts/snowball.dts        |    8 ++++++++
 arch/arm/mach-ux500/cpu-db8500.c      |    2 ++
 drivers/crypto/ux500/cryp/cryp_core.c |    6 ++++++
 drivers/crypto/ux500/hash/hash_core.c |    6 ++++++
 5 files changed, 39 insertions(+)



From lee.jones at linaro.org  Thu May 16 07:27:21 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:21 +0100
Subject: [PATCH 1/6] ARM: ux500: Add Device Tree nodes for the ux500 Crypt
 device
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368703646-26418-2-git-send-email-lee.jones@linaro.org>

This patch provides information required to setup ux500-crypt when
booting with DT on the Snowball low-cost development platform.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi  |    9 +++++++++
 arch/arm/boot/dts/snowball.dts |    4 ++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index fd5794a..92fd4b74 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -755,5 +755,14 @@
 
 			status = "disabled";
 		};
+
+		cryp at a03cb000 {
+			compatible = "stericsson,ux500-cryp";
+			reg = <0xa03cb000 0x1000>;
+			interrupts = <0 15 0x4>;
+
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index db5db24..de585fd 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -350,5 +350,9 @@
 				};
 			};
 		};
+
+		cryp at a03cb000 {
+			status = "okay";
+		};
 	};
 };
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May 16 07:27:22 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:22 +0100
Subject: [PATCH 2/6] ARM: ux500: Add Device Tree nodes for the ux500 Hash
 device
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368703646-26418-3-git-send-email-lee.jones@linaro.org>

This patch provides information required to setup ux500-hash when
booting with DT on the Snowball low-cost development platform.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi  |    8 ++++++++
 arch/arm/boot/dts/snowball.dts |    4 ++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 92fd4b74..6c25fbe 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -764,5 +764,13 @@
 			v-ape-supply = <&db8500_vape_reg>;
 			status = "disabled";
 		};
+
+		hash at a03c2000 {
+			compatible = "stericsson,ux500-hash";
+			reg = <0xa03c2000 0x1000>;
+
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index de585fd..3cadb5b 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -354,5 +354,9 @@
 		cryp at a03cb000 {
 			status = "okay";
 		};
+
+		hash at a03c2000 {
+			status = "okay";
+		};
 	};
 };
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May 16 07:27:23 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:23 +0100
Subject: [PATCH 3/6] ARM: ux500: Provide an AUXDATA entry for ux500-cyrpt
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368703646-26418-4-git-send-email-lee.jones@linaro.org>

This provides a device name which is required by the common clk API.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 3b77e36..4d118d8 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -246,6 +246,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
 	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
+	OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May 16 07:27:25 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:25 +0100
Subject: [PATCH 5/6] crypto: ux500/cryp - Enable DT probing of the driver
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368703646-26418-6-git-send-email-lee.jones@linaro.org>

By providing an OF match table with a suitable compatible string, we
can ensure the ux500-crypt driver is probed by supplying an associated
DT node in a given platform's Device Tree.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: linux-crypto at vger.kernel.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/cryp/cryp_core.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 4f8b11a..d3940b7 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1772,6 +1772,11 @@ static int ux500_cryp_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(ux500_cryp_pm, ux500_cryp_suspend, ux500_cryp_resume);
 
+static const struct of_device_id ux500_cryp_match[] = {
+        { .compatible = "stericsson,ux500-cryp" },
+        { },
+};
+
 static struct platform_driver cryp_driver = {
 	.probe  = ux500_cryp_probe,
 	.remove = ux500_cryp_remove,
@@ -1779,6 +1784,7 @@ static struct platform_driver cryp_driver = {
 	.driver = {
 		.owner = THIS_MODULE,
 		.name  = "cryp1",
+		.of_match_table = ux500_cryp_match,
 		.pm    = &ux500_cryp_pm,
 	}
 };
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May 16 07:27:24 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:24 +0100
Subject: [PATCH 4/6] ARM: ux500: Provide an AUXDATA entry for ux500-hash
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368703646-26418-5-git-send-email-lee.jones@linaro.org>

This provides a device name which is required by the common clk API.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 4d118d8..8305bad 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -247,6 +247,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 			&db8500_prcmu_pdata),
 	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
 	OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
+	OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Thu May 16 07:27:26 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 16 May 2013 12:27:26 +0100
Subject: [PATCH 6/6] crypto: ux500/hash - Enable DT probing of the driver
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1368703646-26418-7-git-send-email-lee.jones@linaro.org>

By providing an OF match table with a suitable compatible string, we
can ensure the ux500-hasht driver is probed by supplying an associated
DT node in a given platform's Device Tree.

Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: linux-crypto at vger.kernel.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/crypto/ux500/hash/hash_core.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 9ca6fbb..f89fe8a 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1981,6 +1981,11 @@ static int ux500_hash_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
 
+static const struct of_device_id ux500_hash_match[] = {
+        { .compatible = "stericsson,ux500-hash" },
+        { },
+};
+
 static struct platform_driver hash_driver = {
 	.probe  = ux500_hash_probe,
 	.remove = ux500_hash_remove,
@@ -1988,6 +1993,7 @@ static struct platform_driver hash_driver = {
 	.driver = {
 		.owner = THIS_MODULE,
 		.name  = "hash1",
+		.of_match_table = ux500_hash_match,
 		.pm    = &ux500_hash_pm,
 	}
 };
-- 
1.7.10.4



From laurent.pinchart at ideasonboard.com  Thu May 16 07:30:25 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 16 May 2013 13:30:25 +0200
Subject: [RFC/PATCH] dma: of: Make of_dma_simple_xlate match on DMA device
 and channel ID
In-Reply-To: <5193A113.4050301@metafoo.de>
References: <1368624449-29003-1-git-send-email-laurent.pinchart@ideasonboard.com>
 <3106852.EdI2KVGSEm@avalon> <5193A113.4050301@metafoo.de>
Message-ID: <16693906.m6Wa34B7F1@avalon>

Hi Lars-Peter,

On Wednesday 15 May 2013 16:52:03 Lars-Peter Clausen wrote:
> On 05/15/2013 03:55 PM, Laurent Pinchart wrote:
> > On Wednesday 15 May 2013 15:39:09 Lars-Peter Clausen wrote:
> >> On 05/15/2013 03:27 PM, Laurent Pinchart wrote:
> >>> When translating a DT DMA channel specifier, the most common use case is
> >>> to match the DMA channel based on the channel DMA engine and channel ID.
> >>> Modify the of_dma_simple_xlate() function to do so, simplifying the API
> >>> for DMA engine drivers.
> >>> 
> >>> There is no need to check the DMA cells count in the filter function as
> >>> the check is already performed by the caller in of_dma_get_controller().
> >>> 
> >>> Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> >> 
> >> Hi,
> >> 
> >> I've submitted a very similar patch some time ago, see
> >> https://lkml.org/lkml/2013/3/25/250
> > 
> > Thanks. So my patch makes at least some sense :-)
> > 
> > I had the impression that this is what omap-dma needs as well, hence the
> > modification to the existing xlate function. I'm fine with a separate
> > function as well if the current code covers different use cases.
> 
> My first attempt was to modify simple_xlate function, but I think it didn't
> work for all users (some of which aren't applied yet), so I added a separate
> function.

OK. Do you plan to push your patch to mainline ? You can add my

Tested-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

> >>> ---
> >>> 
> >>>  drivers/dma/of-dma.c   | 39 +++++++++++++++++++++++++++++++--------
> >>>  drivers/dma/omap-dma.c |  8 +-------
> >>>  include/linux/of_dma.h |  5 -----
> >>>  3 files changed, 32 insertions(+), 20 deletions(-)
> >>> 
> >>> I've implemented this function while working on a DMA engine driver, and
> >>> realized that it wasn't specific to my driver at all. As I'm new to the
> >>> DMA engine API, I'd appreciate feedback on whether this change makes
> >>> sense, or if I should instead keep the existing of_dma_simple_xlate()
> >>> function and create a separate simple xlate helper.
> >>> 
> >>> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
> >>> index 7aa0864..702a45d 100644
> >>> --- a/drivers/dma/of-dma.c
> >>> +++ b/drivers/dma/of-dma.c
> >>> @@ -202,6 +202,27 @@ struct dma_chan
> >>> *of_dma_request_slave_channel(struct
> >>> device_node *np,
> >>> 
> >>>  	return NULL;
> >>>  
> >>>  }
> >>> 
> >>> +struct of_dma_filter_args {
> >>> +	struct dma_device *device;
> >>> +	unsigned int chan_id;
> >>> +};
> >>> +
> >>> +/**
> >>> + * of_dma_simple_xlate_filter - Channel filter function for
> >>> of_dma_simple_xlate + * @dma_chan:	pointer to candidate DMA channel
> >>> + * @param:	pointer to filter parameter
> >>> + *
> >>> + * Filter out candidate DMA channels that don't match the channel ID or
> >>> + * DMA engine device passed as arguments.
> >>> + */
> >>> +static bool of_dma_simple_xlate_filter(struct dma_chan *chan, void
> >>> *param)
> >>> +{
> >>> +	struct of_dma_filter_args *fargs = param;
> >>> +
> >>> +	return (chan->device == fargs->device) &&
> >>> +	       (chan->chan_id == fargs->chan_id);
> >>> +}
> >>> +
> >>> 
> >>>  /**
> >>>  
> >>>   * of_dma_simple_xlate - Simple DMA engine translation function
> >>>   * @dma_spec:	pointer to DMA specifier as found in the device tree
> >>> 
> >>> @@ -216,16 +237,18 @@ struct dma_chan
> >>> *of_dma_request_slave_channel(struct
> >>> device_node *np,>
> >>> 
> >>>  struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
> >>>  
> >>>  						struct of_dma *ofdma)
> >>>  
> >>>  {
> >>> 
> >>> -	int count = dma_spec->args_count;
> >>> -	struct of_dma_filter_info *info = ofdma->of_dma_data;
> >>> +	struct dma_device *dev = ofdma->of_dma_data;
> >>> +	struct of_dma_filter_args fargs;
> >>> +	dma_cap_mask_t cap;
> >>> 
> >>> -	if (!info || !info->filter_fn)
> >>> -		return NULL;
> >>> +	/* There's no need to specify matching caps as we're going to match a
> >>> +	 * specific DMA channel anyway.
> >>> +	 */
> >>> +	dma_cap_zero(cap);
> >>> 
> >>> -	if (count != 1)
> >>> -		return NULL;
> >>> +	fargs.device = dev;
> >>> +	fargs.chan_id = dma_spec->args[0];
> >>> 
> >>> -	return dma_request_channel(info->dma_cap, info->filter_fn,
> >>> -			&dma_spec->args[0]);
> >>> +	return dma_request_channel(cap, of_dma_simple_xlate_filter, &fargs);
> >>> 
> >>>  }
> >>>  EXPORT_SYMBOL_GPL(of_dma_simple_xlate);
> >>> 
> >>> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> >>> index ec3fc4f..7e7ff06 100644
> >>> --- a/drivers/dma/omap-dma.c
> >>> +++ b/drivers/dma/omap-dma.c
> >>> @@ -69,10 +69,6 @@ static const unsigned es_bytes[] = {
> >>> 
> >>>  	[OMAP_DMA_DATA_TYPE_S32] = 4,
> >>>  
> >>>  };
> >>> 
> >>> -static struct of_dma_filter_info omap_dma_info = {
> >>> -	.filter_fn = omap_dma_filter_fn,
> >>> -};
> >>> -
> >>> 
> >>>  static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
> >>>  {
> >>>  
> >>>  	return container_of(d, struct omap_dmadev, ddev);
> >>> 
> >>> @@ -641,11 +637,9 @@ static int omap_dma_probe(struct platform_device
> >>> *pdev)>
> >>> 
> >>>  	platform_set_drvdata(pdev, od);
> >>>  	if (pdev->dev.of_node) {
> >>> 
> >>> -		omap_dma_info.dma_cap = od->ddev.cap_mask;
> >>> -
> >>> 
> >>>  		/* Device-tree DMA controller registration */
> >>>  		rc = of_dma_controller_register(pdev->dev.of_node,
> >>> 
> >>> -				of_dma_simple_xlate, &omap_dma_info);
> >>> +				of_dma_simple_xlate, &od->ddev);
> >>> 
> >>>  		if (rc) {
> >>>  		
> >>>  			pr_warn("OMAP-DMA: failed to register DMA controller\n");
> >>>  			dma_async_device_unregister(&od->ddev);
> >>> 
> >>> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> >>> index 364dda7..3c0d9ac 100644
> >>> --- a/include/linux/of_dma.h
> >>> +++ b/include/linux/of_dma.h
> >>> @@ -27,11 +27,6 @@ struct of_dma {
> >>> 
> >>>  	void			*of_dma_data;
> >>>  
> >>>  };
> >>> 
> >>> -struct of_dma_filter_info {
> >>> -	dma_cap_mask_t	dma_cap;
> >>> -	dma_filter_fn	filter_fn;
> >>> -};
> >>> -
> >>> 
> >>>  #ifdef CONFIG_OF
> >>>  extern int of_dma_controller_register(struct device_node *np,
> >>>  
> >>>  		struct dma_chan *(*of_dma_xlate)
-- 
Regards,

Laurent Pinchart



From lars at metafoo.de  Thu May 16 07:29:00 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 16 May 2013 13:29:00 +0200
Subject: [alsa-devel] [PATCH] ASoC: dfbmcs320: make the driver common
 for other BT modules
In-Reply-To: <CAGsJ_4yoXj+e7A20SM5+ctLvE2QRTp0bzDeKfCZSUHTO8BPq5A@mail.gmail.com>
References: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>
 <5194AC3C.4080206@metafoo.de>
 <CAGsJ_4yoXj+e7A20SM5+ctLvE2QRTp0bzDeKfCZSUHTO8BPq5A@mail.gmail.com>
Message-ID: <5194C2FC.70804@metafoo.de>

On 05/16/2013 12:31 PM, Barry Song wrote:
> 2013/5/16 Lars-Peter Clausen <lars at metafoo.de>:
>> On 05/16/2013 08:53 AM, Barry Song wrote:
>>> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
>>> we don't want everyone to have a seperate codec driver. anyway, the
>>> feature of Bluetooth handsfree is same on all platforms, so this patch
>>> makes the DFBM-CS320 driver become a common BT handsfree driver.
>> [...]
>>> -static struct platform_driver dfmcs320_driver = {
>>> +static struct platform_driver bt_handsfree_driver = {
>>>       .driver = {
>>> -             .name = "dfbmcs320",
>>> +             .name = "bt-handsfree",
>>>               .owner = THIS_MODULE,
>>
>> In my opinion it's a good idea to keep a platform_id list of all the
>> supported devices.
> 
> i have no idea how many bluetooth handsfree module exist in the world.
> there must be many. actually the driver works for almost all BT
> handsfree.
> so my basic idea is making the codes as common as possible.

you don't have to know all the device names, but I'd prefer to keep at least
dfbmcs320 in the device id list.

- Lars


From lars at metafoo.de  Thu May 16 07:38:52 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 16 May 2013 13:38:52 +0200
Subject: [RFC/PATCH] dma: of: Make of_dma_simple_xlate match on DMA device
 and channel ID
In-Reply-To: <16693906.m6Wa34B7F1@avalon>
References: <1368624449-29003-1-git-send-email-laurent.pinchart@ideasonboard.com>
 <3106852.EdI2KVGSEm@avalon> <5193A113.4050301@metafoo.de>
 <16693906.m6Wa34B7F1@avalon>
Message-ID: <5194C54C.10300@metafoo.de>

On 05/16/2013 01:30 PM, Laurent Pinchart wrote:
> Hi Lars-Peter,
> 
> On Wednesday 15 May 2013 16:52:03 Lars-Peter Clausen wrote:
>> On 05/15/2013 03:55 PM, Laurent Pinchart wrote:
>>> On Wednesday 15 May 2013 15:39:09 Lars-Peter Clausen wrote:
>>>> On 05/15/2013 03:27 PM, Laurent Pinchart wrote:
>>>>> When translating a DT DMA channel specifier, the most common use case is
>>>>> to match the DMA channel based on the channel DMA engine and channel ID.
>>>>> Modify the of_dma_simple_xlate() function to do so, simplifying the API
>>>>> for DMA engine drivers.
>>>>>
>>>>> There is no need to check the DMA cells count in the filter function as
>>>>> the check is already performed by the caller in of_dma_get_controller().
>>>>>
>>>>> Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
>>>>
>>>> Hi,
>>>>
>>>> I've submitted a very similar patch some time ago, see
>>>> https://lkml.org/lkml/2013/3/25/250
>>>
>>> Thanks. So my patch makes at least some sense :-)
>>>
>>> I had the impression that this is what omap-dma needs as well, hence the
>>> modification to the existing xlate function. I'm fine with a separate
>>> function as well if the current code covers different use cases.
>>
>> My first attempt was to modify simple_xlate function, but I think it didn't
>> work for all users (some of which aren't applied yet), so I added a separate
>> function.
> 
> OK. Do you plan to push your patch to mainline ? You can add my
> 

Yes, I already submitted it for mainline inclusion. Waiting for Vinod to
either apply or comment on it.

> Tested-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>



From prabhakar.csengg at gmail.com  Thu May 16 07:48:00 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Thu, 16 May 2013 17:18:00 +0530
Subject: [PATCH 2/6] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <CA+V-a8uU6QkYcMg1b5BPHbA0gUGypZeXZNScE-WLa-GqK4_fQA@mail.gmail.com>
References: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
 <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>
 <1928313.pnnBGKgv0p@avalon>
 <CA+V-a8uU6QkYcMg1b5BPHbA0gUGypZeXZNScE-WLa-GqK4_fQA@mail.gmail.com>
Message-ID: <CA+V-a8txWU=ohuJfmtKk5fQ_rh_qsp8wA72vUXWEDBZU1TJR-g@mail.gmail.com>

Hi Laurent,

On Wed, May 15, 2013 at 5:41 PM, Prabhakar Lad
<prabhakar.csengg at gmail.com> wrote:
> Hi Laurent,
>
> Thanks for the review.
>
> On Wed, May 15, 2013 at 5:35 PM, Laurent Pinchart
> <laurent.pinchart at ideasonboard.com> wrote:
>> Hi Prabhakar,
>>
>> Thank you for the patch.
>>
>> On Wednesday 15 May 2013 17:27:18 Lad Prabhakar wrote:
>>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>>>
>>> remove init_enable from ths7303 pdata as it is no longer exists.
>>
>> You should move this before 1/6, otherwise you will break bisection.
>>
How about I just reshuffles while issuing a pull rather than resending
the whole series ?

Regards,
--Prabhakar Lad


From laurent.pinchart at ideasonboard.com  Thu May 16 07:53:25 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 16 May 2013 13:53:25 +0200
Subject: [PATCH v3 01/20] sh-pfc: Add DT support
In-Reply-To: <Pine.LNX.4.64.1305151417300.10596@axis700.grange>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <Pine.LNX.4.64.1305151417300.10596@axis700.grange>
Message-ID: <1711141.qqk6hopDLW@avalon>

Hi Guennadi,

On Wednesday 15 May 2013 16:03:10 Guennadi Liakhovetski wrote:
> Hi Laurent
> 
> Thanks for your work on this! Sorry for jumping in so late in the game.

No worries.

> Let's do it this way: I don't think my comments are serious enough to
> enforce a v4. If noone else complains, I'm fine with addressing them in an
> incremental patch. If you get more comments and have to do a v4, you can
> address mine too, otherwise I'm fine with this version going in and
> improving it slightly afterwards.

I don't mind submitting a v4.

> On Wed, 15 May 2013, Laurent Pinchart wrote:
> > Support device instantiation through the device tree. The compatible
> > property is used to select the SoC pinmux information.
> > 
> > Set the gpio_chip device field to the PFC device to enable automatic
> > GPIO OF support.
> > 
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> > ---
> > 
> >  .../bindings/pinctrl/renesas,pfc-pinctrl.txt       | 143 ++++++++++++
> >  drivers/pinctrl/sh-pfc/core.c                      |  66 +++++-
> >  drivers/pinctrl/sh-pfc/pinctrl.c                   | 244 ++++++++++++++++
> >  3 files changed, 451 insertions(+), 2 deletions(-)
> >  create mode 100644
> >  Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt> 
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> > b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt new
> > file mode 100644
> > index 0000000..e7aae39
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> > @@ -0,0 +1,143 @@
> > +* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
> > +
> > +The Pin Function Controller (PFC) is a Pin Mux/Config controller. On
> > SH7372, +SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
> > +
> > +
> > +Pin Control
> > +-----------
> > +
> > +Required Properties:
> > +
> > +  - compatible: should be one of the following.
> > +    - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible
> > pin-controller.
> > +    - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-
> > controller.
> > +    - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-
> > controller.
> > +    - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-
> > controller.
> > +    - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-
> > controller.
> > +    - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible
> > pin-controller.
> > +    - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-
> > controller.
> > +
> > +  - reg: Base address and length of each memory resource used by the pin
> > +    controller hardware module.
> > +
> > +The PFC node also acts as a container for pin configuration nodes. Please
> > +refer to pinctrl-bindings.txt in this directory for the definition of the
> > +term "pin configuration node" and for the common pinctrl bindings used by
> > +client devices.
> > +
> > +Each pin configuration node represents a desired configuration for a pin,
> > +a pin group, or a list of pins or pin groups. The configuration can
> > +include the function to select on those pin(s) and pin configuration
> > +parameters (such as +pull-up and pull-down).
> > +
> > +Pin configuration nodes contain pin configuration properties, either
> > +directly or grouped in child subnodes. Both pin muxing and configuration
> > +parameters can be grouped in that way and referenced as a single pin
> > +configuration node by client devices.
> > +
> > +A configuration node or subnode must reference at least one pin (through
> > +the pins or pin groups properties) and contain at least a function or one
> > +configuration parameter. When the function is present only pin groups can
> > +be used to reference pins.
> > +
> > +All pin configuration nodes and subnodes names are ignored. All of those
> > +nodes are parsed through phandles and processed purely based on their
> > +content.
> > +
> > +Pin Configuration Node Properties:
> > +
> > +- renesas,pins : An array of strings, each string containing the name of
> > +  a pin.
> > +- renesas,groups : An array of strings, each string containing the name
> > +  of a pin group.
> > +
> > +- renesas,function: A string containing the name of the function to mux
> > +  to the pin group(s) specified by the renesas,groups property
> > +
> > +  Valid values for pin, group and function names can be found in the
> > +  group and function arrays of the PFC data file corresponding to the SoC
> > +  (drivers/pinctrl/sh-pfc/pfc-*.c)
> > +
> > +- renesas,pull-up: An integer representing the pull-up strength to be
> > +  applied to all pins specified by the renesas,pins and renesas-groups
> > +  properties. 0 disables the pull-up, 1 enables it. Other values should
> > +  not be used.
> > +- renesas,pull-down: An integer representing the pull-down strength to be
> > +  applied to all pins specified by the renesas,pins and renesas-groups
> > +  properties. 0 disables the pull-down, 1 enables it. Other values should
> > +  not be used.
> > +
> > +
> > +GPIO
> > +----
> > +
> > +Required Properties:
> > +
> > +  - gpio-controller: Marks the device node as a gpio controller.
> > +
> > +  - #gpio-cells: Should be 2. The first cell is the pin number and the
> > +    second cell is used to specify optional parameters as bit flags.
> > +    Only the GPIO active low flag (bit 0) is currently supported.
> > +
> > +The syntax of the gpio specifier used by client nodes should be the
> > +following with values derived from the SoC user manual.
> > +
> > +  <[phandle of the gpio controller node]
> > +   [pin number within the gpio controller]
> > +   [flags and pull up/down]>
> 
> How should pull up / down be specified? Above you say only "active low" is
> supported so far.

My bad. It should be [flags] only. Pull-up and pull-down configuration should 
go through the renesas,pull-up and renesas,pull-down properties in pin 
configuration nodes.
 
> Actually, I'm a bit confused by how pinctrl and GPIO DT nodes should be
> implemented:
>
> > +
> > +
> > +Examples
> > +--------
> > +
> > +Example 1: SH73A0 (SH-Mobile AG5) pin controller node
> > +
> > +	pfc: pfc at e6050000 {
> > +		compatible = "renesas,pfc-sh73a0";
> > +		reg = <0xe6050000 0x8000>,
> > +		      <0xe605801c 0x1c>;
> > +		gpio-controller;
> > +		#gpio-cells = <2>;
> > +	};
> 
> In this example you add one node, that implements both - a pinctrl and a
> GPIO controller. However, on some platforms you add two DT nodes: one for
> pinctrl and one for GPIO. While doing that your GPIO node has a compatible
> string like
> 
> 		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
> 
> Do I understand it right, that a separate DT node is used for a GPIO
> controller if the controllers are really well separated on the hardware,
> probably, don't share register address ranges? Is there a driver in the
> kernel, that actually probes those compatible strings? Or the driver for
> those GPIO controllers isn't DT based?

On platforms where the GPIO controller hardware is separate from the PFC 
hardware, GPIOs are handled by the gpio-rcar driver. I've added DT support to 
gpio-rcar, the patches have been posted to the linux-sh mailing list and are 
in my tree at git://linuxtv.org/pinchartl/fbdev.git pinmux/3.9/dt.

> Maybe at least a short explanation and an example with two DT nodes here, or
> a reference to another documentation would help.

What about

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index e7aae39..ce2584c 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -68,6 +68,9 @@ Pin Configuration Node Properties:
 GPIO
 ----
 
+On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
+node.
+
 Required Properties:
 
   - gpio-controller: Marks the device node as a gpio controller.
@@ -81,7 +84,11 @@ with values derived from the SoC user manual.
 
   <[phandle of the gpio controller node]
    [pin number within the gpio controller]
    [flags and pull up/down]>
+
+On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
+Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+for documentation of the GPIO device tree bindings on those platforms.

> [snip]
> 
> > diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
> > index 3b2fd43..5fa1c6b 100644
> > --- a/drivers/pinctrl/sh-pfc/core.c
> > +++ b/drivers/pinctrl/sh-pfc/core.c
> > @@ -18,6 +18,7 @@
> >  #include <linux/ioport.h>
> >  #include <linux/kernel.h>
> >  #include <linux/module.h>
> > +#include <linux/of_device.h>
> >  #include <linux/pinctrl/machine.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/slab.h>
> > @@ -348,14 +349,74 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned
> > mark, int pinmux_type)> 
> >  	return 0;
> >  
> >  }
> > 
> > +#ifdef CONFIG_OF
> 
> Not sure, is it really a good idea to use this #ifdef here?

I think there's no point in making the driver larger if CONFIG_OF isn't 
defined, especially for SH platforms.

> I think you could drop all 3 of them in this hunk:

I've dropped the other two.

> [snip]
> 
> >  static int sh_pfc_probe(struct platform_device *pdev)
> >  {
> > 
> > +	const struct platform_device_id *platid = 
platform_get_device_id(pdev);
> > +#ifdef CONFIG_OF
> 
> also here

Dropped.

> > +	struct device_node *np = pdev->dev.of_node;
> > +#endif
> > 
> >  	const struct sh_pfc_soc_info *info;
> >  	struct sh_pfc *pfc;
> >  	int ret;
> > 
> > -	info = pdev->id_entry->driver_data
> > -	      ? (void *)pdev->id_entry->driver_data : pdev-
>dev.platform_data;
> > +	if (platid)
> > +		info = (const void *)platid->driver_data;
> > +#ifdef CONFIG_OF
> 
> and here.

Dropped.

> > +	else if (np)
> > +		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
> > +#endif
> > +	else
> > +		info = pdev->dev.platform_data;

I will also add a new patch that removes support for pdev->dev.platform_data, 
as we don't use it anymore.

> > +
> > 
> >  	if (info == NULL)
> >  	
> >  		return -ENODEV;
> 
> [snip]
> 
> > +static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
> > +				 struct device_node *np,
> > +				 struct pinctrl_map **map, unsigned *num_maps)
> > +{
> > +	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +	struct device *dev = pmx->pfc->dev;
> > +	struct device_node *child;
> > +	unsigned int index;
> > +	int ret;
> > +
> > +	*map = NULL;
> > +	*num_maps = 0;
> > +	index = 0;
> > +
> > +	for_each_child_of_node(np, child) {
> > +		ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
> > +					       &index);
> > +		if (ret < 0)
> > +			goto done;
> > +	}
> > +
> > +	/* If no mapping has been found in child nodes try the config node. 
*/
> > +	if (*num_maps == 0) {
> > +		ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
> > +		if (ret < 0)
> > +			goto done;
> > +	}
> > +
> > +	if (*num_maps == 0) {
> > +		dev_err(dev, "no mapping found in node %s\n", np->full_name);
> > +		ret = -EINVAL;
> > +		goto done;
> > +	}
> > +
> > +	ret = 0;
> > +
> > +done:
> > +	if (ret < 0)
> > +		sh_pfc_dt_free_map(pctldev, *map, *num_maps);
> > +
> > +	return ret;
> > +}
> 
> Maybe simpler
> 
> +	if (*num_maps)
> +		return 0;
> +
> +	dev_err(dev, "no mapping found in node %s\n", np->full_name);
> +	ret = -EINVAL;
> +
> +done:
> +	sh_pfc_dt_free_map(pctldev, *map, *num_maps);
> +
> +	return ret;

OK I'll change that.

-- 
Regards,

Laurent Pinchart



From laurent.pinchart at ideasonboard.com  Thu May 16 07:54:08 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 16 May 2013 13:54:08 +0200
Subject: [PATCH 2/6] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <CA+V-a8txWU=ohuJfmtKk5fQ_rh_qsp8wA72vUXWEDBZU1TJR-g@mail.gmail.com>
References: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
 <CA+V-a8uU6QkYcMg1b5BPHbA0gUGypZeXZNScE-WLa-GqK4_fQA@mail.gmail.com>
 <CA+V-a8txWU=ohuJfmtKk5fQ_rh_qsp8wA72vUXWEDBZU1TJR-g@mail.gmail.com>
Message-ID: <8665087.XDPi8z3vzr@avalon>

Hi Prabhakar,

On Thursday 16 May 2013 17:18:00 Prabhakar Lad wrote:
> On Wed, May 15, 2013 at 5:41 PM, Prabhakar Lad wrote:
> > On Wed, May 15, 2013 at 5:35 PM, Laurent Pinchart wrote:
> >> On Wednesday 15 May 2013 17:27:18 Lad Prabhakar wrote:
> >>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> >>> 
> >>> remove init_enable from ths7303 pdata as it is no longer exists.
> >> 
> >> You should move this before 1/6, otherwise you will break bisection.
> 
> How about I just reshuffles while issuing a pull rather than resending
> the whole series ?

As long as you don't forget to do so, sure :-)

-- 
Regards,

Laurent Pinchart



From linux at arm.linux.org.uk  Thu May 16 07:59:07 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 May 2013 12:59:07 +0100
Subject: [PATCH] ARM: dove: add a kms/drm driver
In-Reply-To: <20130516132822.09b883cf@armhf>
References: <20130516132822.09b883cf@armhf>
Message-ID: <20130516115907.GQ18614@n2100.arm.linux.org.uk>

On Thu, May 16, 2013 at 01:28:22PM +0200, Jean-Francois Moine wrote:
> This patch adds a KMS/DRM video driver for the LCD and display
> controllers of the Marvell's Dove SoC.
> 
> Signed-off-by: Jean-Francois Moine <moinejf at free.fr>

I want to review this as I have a competing driver which offers full
support for the Dove cubox including a fully accelerated X server,
and overlay support, page flipping and so forth.


From 21cnbao at gmail.com  Thu May 16 08:00:17 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 16 May 2013 20:00:17 +0800
Subject: [alsa-devel] [PATCH] ASoC: dfbmcs320: make the driver common for
 other BT modules
In-Reply-To: <5194C2FC.70804@metafoo.de>
References: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>
 <5194AC3C.4080206@metafoo.de>
 <CAGsJ_4yoXj+e7A20SM5+ctLvE2QRTp0bzDeKfCZSUHTO8BPq5A@mail.gmail.com>
 <5194C2FC.70804@metafoo.de>
Message-ID: <CAGsJ_4yn2uodRKrFKYrX85XA7A=hQs2w0cyGoEEHsYgCJHD7eQ@mail.gmail.com>

2013/5/16 Lars-Peter Clausen <lars at metafoo.de>:
> On 05/16/2013 12:31 PM, Barry Song wrote:
>> 2013/5/16 Lars-Peter Clausen <lars at metafoo.de>:
>>> On 05/16/2013 08:53 AM, Barry Song wrote:
>>>> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
>>>> we don't want everyone to have a seperate codec driver. anyway, the
>>>> feature of Bluetooth handsfree is same on all platforms, so this patch
>>>> makes the DFBM-CS320 driver become a common BT handsfree driver.
>>> [...]
>>>> -static struct platform_driver dfmcs320_driver = {
>>>> +static struct platform_driver bt_handsfree_driver = {
>>>>       .driver = {
>>>> -             .name = "dfbmcs320",
>>>> +             .name = "bt-handsfree",
>>>>               .owner = THIS_MODULE,
>>>
>>> In my opinion it's a good idea to keep a platform_id list of all the
>>> supported devices.
>>
>> i have no idea how many bluetooth handsfree module exist in the world.
>> there must be many. actually the driver works for almost all BT
>> handsfree.
>> so my basic idea is making the codes as common as possible.
>
> you don't have to know all the device names, but I'd prefer to keep at least
> dfbmcs320 in the device id list.

i did think it is a good idea to have device id list while i sent the
last mail. and it matches with the generic device driver engineering
sense. the problem is i don't how long the list will be.
if you like to keep dfbmcs320 at least for the moment, i would agree.

>
> - Lars

-barry


From yegor_sub1 at visionsystems.de  Thu May 16 06:19:20 2013
From: yegor_sub1 at visionsystems.de (Yegor Yefremov)
Date: Thu, 16 May 2013 12:19:20 +0200
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130515215028.GA11883@animalcreek.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com> <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
Message-ID: <5194B2A8.8020608@visionsystems.de>

On 15.05.2013 23:50, Mark A. Greer wrote:
> On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
>> * Mark A. Greer <mgreer at animalcreek.com> [130514 18:57]:
>>> On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
>>>> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
>>>> changed PM to not access IVA registers on omaps that don't have
>>>> them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
>>>> will stay on and block deeper idle states.
>>>>
>>>> Signed-off-by: Tony Lindgren <tony at atomide.com>
>>>>
>>>> ---
>>>>
>>>> Paul & Kevin, do you have better ideas for fixing this?
>>>>
>>>> --- a/arch/arm/mach-omap2/pm34xx.c
>>>> +++ b/arch/arm/mach-omap2/pm34xx.c
>>>> @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
>>>>  	/* Clear any pending PRCM interrupts */
>>>>  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
>>>>  
>>>> -	if (omap3_has_iva())
>>>> -		omap3_iva_idle();
>>>> +	/*
>>>> +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
>>>> +	 */
>>>> +	omap3_iva_idle();
>>>>  
>>>>  	omap3_d2d_idle();
>>>>  }
>>>
>>> [Kevin, Paul, some background: Tony discovered that the am3703 needs
>>> to have omap3_iva_idle() called even though its not supposed to have
>>> an IVA.]
>>>
>>> This is potentially bad for other SoC's that don't have an IVA so I don't
>>> think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
>>> flag for the am3703 only since its the one with the bug.  Maybe something
>>> in id.c:omap3xxx_check_features() but I don't see any existing way to check
>>> for an am3703 vs. other am37xx SoCs.  Any ideas?
>>>
>>> Another option, I suppose, is a dts entry but I don't like that at all.
>>
>> It seems that iva2_pwrdm is there for all omap3 even if OMAP3_HAS_IVA
>> flag is unset. And if that's the case, iva2 clocks still need to be idled
>> in all cases.
> 
> Ahh, this takes us to the "Great TI Docs Mystery" :) -- its basically
> impossible to tell because despite what their docs may say, the hardware
> can be quite different.  I'm not sure how to proceed other than trial &
> error with as many different SoCs as we can find.
> 
>> It's possible that not all steps in omap3_iva_idle() are needed though.
>> I can debug further to see which part of the omap3_iva_idle() are needed.
>>
>> Mark, do you have some omap3 with no iva (other than am3703) to test the
>> idle states with?
> 
> I have an am35xx which isn't supposed to have an IVA so I can test with it
> (although, I'm not sure how well the kernel works on the am35xx these days).
> 
> I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
> comes up, see what I can figure out.

I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html

I have such a system running, so if you have any other patches/ideas to test, I would do it.

Yegor



From arnd at arndb.de  Thu May 16 08:17:27 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 May 2013 14:17:27 +0200
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <15FD6543-D04A-4953-A56A-40B27F0026E4@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <201305151607.54442.arnd@arndb.de>
 <15FD6543-D04A-4953-A56A-40B27F0026E4@gmail.com>
Message-ID: <201305161417.28133.arnd@arndb.de>

On Thursday 16 May 2013, Daniel Tang wrote:
> 
> On 16/05/2013, at 12:07 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> 
> > You are missing a binding in Documentation/devicetree, same as for some of
> > the other drivers in this series.
> 
> Should we be adding a vendor prefix to it too? If so, we're not sure whether
> to use "ti," or not since this isn't an official port by TI.

The binding describes the hardware, it should not matter who does the port.
However, any part of the tree that is not actually from TI should have a
vendor prefix indicating who made that part. IIRC, the SoC used in there
is from TI, so you should use something else for the on-soc components.
 
> > It seems strange to assign the clk_name variable to node->name
> > first and then overriding it with the clock-output-names property.
> > Is that intentional? If so, please explain it in a comment.
> > 
> 
> I copied that bit of boilerplate from drivers/clk/clk-fixed-rate.c but
> I'm guessing it's to use the node name as the clock name unless there
> is a property called "clock-output-names"

Ah, I see. It seems you forgot to add the clock maintainer to Cc in the
mail. Mike is the one who will have to take you patch anyway, so I assume
he will comment on this if you did it wrong.

	Arnd


From gwenhael.goavec-merou at armadeus.com  Thu May 16 06:25:31 2013
From: gwenhael.goavec-merou at armadeus.com (Gwenhael Goavec-Merou)
Date: Thu, 16 May 2013 12:25:31 +0200
Subject: [PATCH] ARM: imx: apf51: add nfc support
Message-ID: <1368699931-9977-1-git-send-email-gwenhael.goavec-merou@armadeus.com>


Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>
---
 arch/arm/boot/dts/imx51-apf51.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 2bcf698..8f7f9ac 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -45,6 +45,13 @@
 	status = "okay";
 };
 
+&nfc {
+	nand-bus-width = <8>;
+	nand-ecc-mode = "hw";
+	nand-on-flash-bbt;
+	status = "okay";
+};
+
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3_2>;
-- 
1.8.1.5



From 21cnbao at gmail.com  Thu May 16 08:22:19 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 16 May 2013 20:22:19 +0800
Subject: [PATCH 08/33] drivers/i2c/busses: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-9-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
 <1368702961-4325-9-git-send-email-wsa@the-dreams.de>
Message-ID: <CAGsJ_4zAJpqxjg_rcO1WxS=GLii7YooPnsCgt40frf_5afiY6g@mail.gmail.com>

2013/5/16 Wolfram Sang <wsa at the-dreams.de>:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang <wsa at the-dreams.de>

Acked-by: Barry Song <Baohua.Song at csr.com>

-barry


From eduardo.valentin at ti.com  Thu May 16 08:27:27 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 16 May 2013 08:27:27 -0400
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <519488D3.5070003@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com> <519488D3.5070003@ti.com>
Message-ID: <5194D0AF.3010407@ti.com>

On 16-05-2013 03:20, Benoit Cousson wrote:
> Hi Eduardo,
> 
> On 05/15/2013 06:36 PM, Eduardo Valentin wrote:
>> On 15-05-2013 11:23, Benoit Cousson wrote:
>>> Hi Eduardo,
>>>
>>> On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
>>>> Include bandgap devices for OMAP4460 devices.
>>>>
>>>> Cc: "Beno?t Cousson" <b-cousson at ti.com>
>>>> Cc: Tony Lindgren <tony at atomide.com>
>>>> Cc: Russell King <linux at arm.linux.org.uk>
>>>> Cc: linux-omap at vger.kernel.org
>>>> Cc: devicetree-discuss at lists.ozlabs.org
>>>> Cc: linux-arm-kernel at lists.infradead.org
>>>> Cc: linux-kernel at vger.kernel.org
>>>> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
>>>> ---
>>>>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
>>>>  1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
>>>> index 2cf227c..e5bfbfe 100644
>>>> --- a/arch/arm/boot/dts/omap4460.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4460.dtsi
>>>> @@ -29,4 +29,13 @@
>>>>  			     <0 55 0x4>;
>>>>  		ti,hwmods = "debugss";
>>>>  	};
>>>> +
>>>> +	bandgap {
>>>> +		reg = <0x4a002260 0x4
>>>> +			0x4a00232C 0x4
>>>> +			0x4a002378 0x18>;
>>>> +		compatible = "ti,omap4460-bandgap";
>>>> +		interrupts = <0 126 4>; /* talert */
>>>> +		ti,tshut-gpio = <86>;
>>
>>
>>
>>>
>>> Why do you need a custom attribute for GPIO? Cannot you use the standard
>>> one?
>>
>> I believe it was by your suggestion :-), during the first attempts to
>> send this driver. But could not find the thread link :-( sorry.
> 
> Ooops :-) I do not remember that... maybe it was long time ago, before
> we had any decent binding available for GPIO and IRQ...
> 


Probably it was because by that time we didnt have GPIO binding ready, yeah.

>> I guess the reasoning to mark it as a ti specific is because it will be
>> used as IRQ line to treat thermal shutdown (in SW).
> 
> Mmm, ok, so in that case, it is not even a gpio, but an interrupt entry
> that is needed like that:
> 
> 	interrupt-parent = <&gpio3>;
> 	interrupts = <22>; /* gpio line 86 */
> 
> Except that we already have an IRQ line connected to GIC for the
> Talert... I'm not sure we can have 2 different IRQ controllers for one
> device :-(
> 
> We need to check.
> 


Yeah, I also dont think this will work, because we will reparent the
interrupt, setting to a different controller. That will break the TALERT
signal already defined at GIC (check original patch).

I propose keeping the way I sent. Unless there is a way to set two
different controllers to same device.

> Regards,
> Benoit
> 
> 
>>> Where is the gpio controller phandle?
>>>
>>> Usually it looks like this:
>>>
>>> 	gpios = <&gpio1 8 0>;
>>>
>>>
>>> Regards,
>>> Benoit
>>>
>>>
>>>
>>
>>
> 
> 
> 


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From eduardo.valentin at ti.com  Thu May 16 08:29:23 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Thu, 16 May 2013 08:29:23 -0400
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <20130515165726.GK22508@game.jcrosoft.org>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com>
 <20130515165726.GK22508@game.jcrosoft.org>
Message-ID: <5194D123.4060403@ti.com>

On 15-05-2013 12:57, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 12:36 Wed 15 May     , Eduardo Valentin wrote:
>> On 15-05-2013 11:23, Benoit Cousson wrote:
>>> Hi Eduardo,
>>>
>>> On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
>>>> Include bandgap devices for OMAP4460 devices.
>>>>
>>>> Cc: "Beno?t Cousson" <b-cousson at ti.com>
>>>> Cc: Tony Lindgren <tony at atomide.com>
>>>> Cc: Russell King <linux at arm.linux.org.uk>
>>>> Cc: linux-omap at vger.kernel.org
>>>> Cc: devicetree-discuss at lists.ozlabs.org
>>>> Cc: linux-arm-kernel at lists.infradead.org
>>>> Cc: linux-kernel at vger.kernel.org
>>>> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
>>>> ---
>>>>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
>>>>  1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
>>>> index 2cf227c..e5bfbfe 100644
>>>> --- a/arch/arm/boot/dts/omap4460.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4460.dtsi
>>>> @@ -29,4 +29,13 @@
>>>>  			     <0 55 0x4>;
>>>>  		ti,hwmods = "debugss";
>>>>  	};
>>>> +
>>>> +	bandgap {
>>>> +		reg = <0x4a002260 0x4
>>>> +			0x4a00232C 0x4
>>>> +			0x4a002378 0x18>;
>>>> +		compatible = "ti,omap4460-bandgap";
>>>> +		interrupts = <0 126 4>; /* talert */
>>>> +		ti,tshut-gpio = <86>;
>>
>>
>>
>>>
>>> Why do you need a custom attribute for GPIO? Cannot you use the standard
>>> one?
>>
>> I believe it was by your suggestion :-), during the first attempts to
>> send this driver. But could not find the thread link :-( sorry.
>>
>>
>> I guess the reasoning to mark it as a ti specific is because it will be
>> used as IRQ line to treat thermal shutdown (in SW).
> so use interrup-parent


Jean-Christophe,

That will change the controller and break the configuration for the
other IRQ line, coming from GIC.

>>
>>>
>>> Where is the gpio controller phandle?
>>>
>>> Usually it looks like this:
>>>
>>> 	gpios = <&gpio1 8 0>;
>>>
>>>
>>> Regards,
>>> Benoit
>>>
>>>
>>>
>>
>>
> 
> 
> 
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> 
> 


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From amit.shah at redhat.com  Thu May 16 08:37:46 2013
From: amit.shah at redhat.com (Amit Shah)
Date: Thu, 16 May 2013 18:07:46 +0530
Subject: [PATCH V2 1/3] virtio: console: Add emergency writeonly register
 to config space
In-Reply-To: <1367842791-30285-2-git-send-email-pranavkumar@linaro.org>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-2-git-send-email-pranavkumar@linaro.org>
Message-ID: <20130516123746.GA4744@amit.redhat.com>

On (Mon) 06 May 2013 [17:49:49], Pranavkumar Sawargaonkar wrote:
> This patch adds an emerg_wr register (writeonly) in config space
> of virtio console device which can be used for debugging.
> 
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
> Signed-off-by: Anup Patel <anup.patel at linaro.org>
> Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>

OK, this change by itself looks harmless.

Acked-by: Amit Shah <amit.shah at redhat.com>

		Amit


From ulf.hansson at linaro.org  Thu May 16 08:55:46 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Thu, 16 May 2013 14:55:46 +0200
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing
 is done
In-Reply-To: <519461BB.3010209@codeaurora.org>
References: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
 <519461BB.3010209@codeaurora.org>
Message-ID: <CAPDyKFqyvfuttH=rGLxBCemgRMq4N3fVktom+RB2wm72NruaDA@mail.gmail.com>

On 16 May 2013 06:34, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 05/09/2013 11:35 AM, Saravana Kannan wrote:
>>
>> With deferred probing, late_initcall() is too soon to declare a clock as
>> unused. Wait for deferred probing to finish before declaring a clock as
>> unused. Since deferred probing is done in late_initcall(), do the unused
>> check to late_initcall_sync.
>>
>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>> ---
>>   drivers/clk/clk.c |    2 +-
>>   1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>> index fe4055f..5ecb64c 100644
>> --- a/drivers/clk/clk.c
>> +++ b/drivers/clk/clk.c
>> @@ -534,7 +534,7 @@ static int clk_disable_unused(void)
>>
>>         return 0;
>>   }
>> -late_initcall(clk_disable_unused);
>> +late_initcall_sync(clk_disable_unused);

Without giving this too much thinking... Will boot time be affected
with this change?

Kind regards
Ulf Hansson

>>
>>   /***    helper functions   ***/
>
>
> Mike,
>
> Thoughts? Picking it up? Removing the existing auto-disable code (I think
> they are still useful)?
>
> -Saravana
>
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


From sergei.shtylyov at cogentembedded.com  Thu May 16 09:17:30 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 17:17:30 +0400
Subject: [PATCH] ARM: davinci: dma: Convert to devm_* api
In-Reply-To: <1368687502-15551-1-git-send-email-prabhakar.csengg@gmail.com>
References: <1368687502-15551-1-git-send-email-prabhakar.csengg@gmail.com>
Message-ID: <5194DC6A.8080609@cogentembedded.com>

Hello.

On 16-05-2013 10:58, Lad Prabhakar wrote:

> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>

> Use devm_ioremap_resource instead of reques_mem_region()/ioremap() and
> devm_request_irq() instead of request_irq().

> This ensures more consistent error values and simplifies error paths.

> Signed-off-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> ---
>   NOte:- Boot tested on Logic-PD OMAP-L138 EVM

>   arch/arm/mach-davinci/dma.c |   63 ++++++++++++++++--------------------------
>   1 files changed, 24 insertions(+), 39 deletions(-)

> diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> index 45b7c71..aeda496 100644
> --- a/arch/arm/mach-davinci/dma.c
> +++ b/arch/arm/mach-davinci/dma.c
[...]
> @@ -1422,25 +1421,16 @@ static int __init edma_probe(struct platform_device *pdev)
>   			found = 1;
>   		}
>
> -		len[j] = resource_size(r[j]);
> -
> -		r[j] = request_mem_region(r[j]->start, len[j],
> -			dev_name(&pdev->dev));
> -		if (!r[j]) {
> -			status = -EBUSY;
> -			goto fail1;
> -		}
> -
> -		edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
> -		if (!edmacc_regs_base[j]) {
> +		edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
> +		if (IS_ERR(edmacc_regs_base[j])) {
>   			status = -EBUSY;

    And you call that "more consistent error values"? Why not:

			status = PTR_ERR(edmacc_regs_base[j]);

>  		edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);

    Maybe it's worth using devm_kzalloc() too?

WBR, Sergei



From neidhard.kim at lge.com  Thu May 16 09:26:41 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Thu, 16 May 2013 22:26:41 +0900
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <5193164E.6050400@wwwdotorg.org>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org> <022d01ce5107$8bc668e0$a3533aa0$@lge.com>
 <5193164E.6050400@wwwdotorg.org>
Message-ID: <02e901ce5239$013b2570$03b17050$@lge.com>

Stephen Warren <swarren at wwwdotorg.org> :
>> All r1p5 have 32-byte FIFO depth and it's not configurable. From the
PL011
>> TRM:
>> 
>> r1p4-r1p5	Contains the following differences in functionality:
>> 		* The receive and transmit FIFOs are increased to a depth of
32.
>> 		* The Revision field in the UARTPeriphID2 Register on page
3-24
>> 		  bits [7:4] now reads back as 0x3.
>
> Well, that certainly isn't true in practice. I think we should revert
> this commit until we can determine what the problem is.

I asked to the ARM support about this. Waiting for reply..



From robherring2 at gmail.com  Thu May 16 09:29:10 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 May 2013 08:29:10 -0500
Subject: [PATCH] ARM: omap2: remove CONFIG_ARCH_OMAP2PLUS_TYPICAL
Message-ID: <1368710950-2306-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

CONFIG_ARCH_OMAP2PLUS_TYPICAL is selecting user defined features, not h/w
required options. This does not play well with multi-platform kernels and
belongs in a defconfig.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: linux-omap at vger.kernel.org
---
 arch/arm/mach-omap2/Kconfig | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..9d4b5f7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -26,23 +26,6 @@ if ARCH_OMAP2PLUS
 
 menu "TI OMAP2/3/4 Specific Features"
 
-config ARCH_OMAP2PLUS_TYPICAL
-	bool "Typical OMAP configuration"
-	default y
-	select AEABI
-	select HIGHMEM
-	select I2C
-	select I2C_OMAP
-	select MENELAUS if ARCH_OMAP2
-	select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
-	select PM_RUNTIME
-	select REGULATOR
-	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
-	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
-	select VFP
-	help
-	  Compile a kernel suitable for booting most boards
-
 config SOC_HAS_OMAP2_SDRC
 	bool "OMAP2 SDRAM Controller support"
 
-- 
1.8.1.2



From catalin.marinas at arm.com  Thu May 16 09:29:01 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 May 2013 14:29:01 +0100
Subject: [PATCH v2 02/10] arm64: uaccess s/might_sleep/might_fault/
In-Reply-To: <90a2283bb84b6ce77c9966d76dbceb5c7edffd18.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <90a2283bb84b6ce77c9966d76dbceb5c7edffd18.1368702323.git.mst@redhat.com>
Message-ID: <CAHkRjk5bHV3WDSnfQLr1MPTXGXXKP+XKRbqL2fn_bPmXt_7=cw@mail.gmail.com>

On 16 May 2013 12:10, Michael S. Tsirkin <mst at redhat.com> wrote:
> The only reason uaccess routines might sleep
> is if they fault. Make this explicit.
>
> Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
> ---
>  arch/arm64/include/asm/uaccess.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

For arm64:

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From cmetcalf at tilera.com  Thu May 16 09:33:21 2013
From: cmetcalf at tilera.com (Chris Metcalf)
Date: Thu, 16 May 2013 09:33:21 -0400
Subject: [PATCH v2 08/10] tile: uaccess s/might_sleep/might_fault/
In-Reply-To: <018bba1e097552bc4054e6d90e3f03e7c9a632bb.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <018bba1e097552bc4054e6d90e3f03e7c9a632bb.1368702323.git.mst@redhat.com>
Message-ID: <5194E021.8080906@tilera.com>

On 5/16/2013 7:15 AM, Michael S. Tsirkin wrote:
> The only reason uaccess routines might sleep
> is if they fault. Make this explicit.
>
> Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
> ---
>  arch/tile/include/asm/uaccess.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Acked-by: Chris Metcalf <cmetcalf at tilera.com>

-- 
Chris Metcalf, Tilera Corp.
http://www.tilera.com



From arnd at arndb.de  Thu May 16 09:35:03 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 May 2013 15:35:03 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <20130516085711.GP18614@n2100.arm.linux.org.uk>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201305160054.21064.arnd@arndb.de>
 <20130516085711.GP18614@n2100.arm.linux.org.uk>
Message-ID: <201305161535.03742.arnd@arndb.de>

On Thursday 16 May 2013, Russell King - ARM Linux wrote:
> Well, if its a CPU core thing, then it's even easier - the proc-*.S
> file can handle it just fine (because that's where the WFI code is.)
> Just delete the contents of the processor specific idle function, IOW:
> 
> /*
>  * cpu_fa526_do_idle()
>  */
>         .align  4
> ENTRY(cpu_fa526_do_idle)
>         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
>         mov     pc, lr
> 
> remove the WFI from there.

Yes, that was what I meant.

	Arnd


From jonas.jensen at gmail.com  Thu May 16 09:37:16 2013
From: jonas.jensen at gmail.com (Jonas Jensen)
Date: Thu, 16 May 2013 15:37:16 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <201305151516.52389.arnd@arndb.de>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201303181503.49491.arnd@arndb.de>
 <CACmBeS1empYyoaKidgTrYwUFCw447OKndxZjT98TvYfKVWB00A@mail.gmail.com>
 <201305151516.52389.arnd@arndb.de>
Message-ID: <CACmBeS3JZ8bm6jJbmrKTfmZqshezN6QKdmyPCKdQ2HUwzY7ggA@mail.gmail.com>

On 15 May 2013 15:16, Arnd Bergmann <arnd at arndb.de> wrote:
> The part that I don't understand at all is the "timer0" part. Is that a string
> from the data sheet?

I have next to no data sheets or documentation on the SoC itself. What
I know is from looking at old sources, which suggest there are more
than one timer (the rest were never implemented).

It only needs one for timer_tick? Does it make sense to just call it "timer"?

> Can you provide some more detail why what PMU registers are used here? Is that
> a "Performance Measurement Unit", "Power Management Unit" or something else?
> Are you sure that those registers are only ever needed for GPIO?

It's "Power Management Unit". The MMC driver uses it to read system
clock and write it to clock control, but I suspect it can be removed.
It's code under #ifdef MSD_SUPPORT_GET_CLOCK but I think the else is
perfectly acceptable.
GPIO uses it only to enable or disable pins.

>> diff --git a/arch/arm/mach-moxart/Makefile.boot
>> b/arch/arm/mach-moxart/Makefile.boot
>> new file mode 100644
>> index 0000000..760a0ef
>> --- /dev/null
>> +++ b/arch/arm/mach-moxart/Makefile.boot
>> @@ -0,0 +1,3 @@
>> +   zreladdr-y        += 0x00008000
>> +params_phys-y        := 0x00000100
>> +initrd_phys-y        := 0x00800000
>
> Is this still used?

Looks like this is no longer needed. Boots without it. Removed.

> You can leave out moxart_init() now, it's the default implementation.
> moxart_init_irq, moxart_handle_irq and nr_irqs should be obsolete if
> you did the irqchip driver correctly, same for moxart_timer_init and
> the clocksource driver.
>
> I think the only part remaining here is moxart_restart, but that is
> broken as long as reg_wdt does not get initialized. I think you could
> move that function into the watchdog driver and assign it to
> arm_pm_restart when you add that driver.

All removed. It boots after some additions to clocksource and irqchip.
arm_pm_restart is set in watchdog.


What I haven't commented on should already be fixed @
https://code.google.com/p/linux-3-10-rc1-moxart/

I'll send new patches.

Best regards,
Jonas


From mkl at pengutronix.de  Thu May 16 09:42:36 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Thu, 16 May 2013 15:42:36 +0200
Subject: [PATCH] can: flexcan: allow compilation on arm and powerpc
Message-ID: <1368711756-22324-1-git-send-email-mkl@pengutronix.de>

This patch removes the Kconfig symbols HAVE_CAN_FLEXCAN and
IMX_HAVE_PLATFORM_FLEXCAN from arch/{arm,powerpc} and allowing compilation on
all arm and powerpc platforms.

This brings a bigger compile time coverage and removes the following dependency
warning found by Arnd Bergmann:

    warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 && IMX_HAVE_PLATFORM_FLEXCAN &&
        SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
    which has unmet direct dependencies (NET && CAN && CAN_DEV)

Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Kumar Gala <galak at kernel.crashing.org>
Cc: U Bhaskar-B22300 <B22300 at freescale.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
---
Hello,

if the arm and powerpc people are okay with this, I'm taking this patch (and
then will go upstream via David Miller's net-next).

regards,
Marc

 arch/arm/mach-imx/Kconfig         | 8 --------
 arch/arm/mach-imx/devices/Kconfig | 4 ----
 arch/arm/mach-mxs/Kconfig         | 1 -
 arch/powerpc/Kconfig              | 1 -
 drivers/net/can/Kconfig           | 5 +----
 5 files changed, 1 insertion(+), 18 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328..239d084 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -111,7 +111,6 @@ config SOC_IMX25
 	select ARCH_MXC_IOMUX_V3
 	select COMMON_CLK
 	select CPU_ARM926T
-	select HAVE_CAN_FLEXCAN if CAN
 	select MXC_AVIC
 
 config SOC_IMX27
@@ -137,7 +136,6 @@ config SOC_IMX35
 	select ARCH_MXC_IOMUX_V3
 	select COMMON_CLK
 	select CPU_V6K
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_EPIT
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
@@ -208,7 +206,6 @@ comment "MX25 platforms:"
 
 config MACH_MX25_3DS
 	bool "Support MX25PDK (3DS) Platform"
-	select IMX_HAVE_PLATFORM_FLEXCAN
 	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMXDI_RTC
@@ -223,7 +220,6 @@ config MACH_MX25_3DS
 
 config MACH_EUKREA_CPUIMX25SD
 	bool "Support Eukrea CPUIMX25 Platform"
-	select IMX_HAVE_PLATFORM_FLEXCAN
 	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMXDI_RTC
@@ -629,7 +625,6 @@ comment "MX35 platforms:"
 
 config MACH_PCM043
 	bool "Support Phytec pcm043 (i.MX35) platforms"
-	select IMX_HAVE_PLATFORM_FLEXCAN
 	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMX_I2C
@@ -665,7 +660,6 @@ config MACH_MX35_3DS
 
 config MACH_EUKREA_CPUIMX35SD
 	bool "Support Eukrea CPUIMX35 Platform"
-	select IMX_HAVE_PLATFORM_FLEXCAN
 	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMX_I2C
@@ -776,7 +770,6 @@ comment "Device tree only"
 
 config	SOC_IMX53
 	bool "i.MX53 support"
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_IMX_SRC
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select PINCTRL
@@ -799,7 +792,6 @@ config SOC_IMX6Q
 	select CPU_V7
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if LOCAL_TIMERS
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_IMX_ANATOP
 	select HAVE_IMX_GPC
 	select HAVE_IMX_MMDC
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 3dd2b1b..b0a629d 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -2,10 +2,6 @@ config IMX_HAVE_PLATFORM_FEC
 	bool
 	default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
 
-config IMX_HAVE_PLATFORM_FLEXCAN
-	bool
-	select HAVE_CAN_FLEXCAN if CAN
-
 config IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	bool
 
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4dc2fbb..ce6e7d6 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -11,7 +11,6 @@ config SOC_IMX28
 	select ARM_AMBA
 	select ARM_CPU_SUSPEND if PM
 	select CPU_ARM926T
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_PWM
 	select PINCTRL_IMX28
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c33e3ad..7754c6b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -674,7 +674,6 @@ config SBUS
 
 config FSL_SOC
 	bool
-	select HAVE_CAN_FLEXCAN if NET && CAN
 
 config FSL_PCI
  	bool
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index e456b70..3c06947 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -102,12 +102,9 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config HAVE_CAN_FLEXCAN
-	bool
-
 config CAN_FLEXCAN
 	tristate "Support for Freescale FLEXCAN based chips"
-	depends on HAVE_CAN_FLEXCAN
+	depends on ARM || PPC
 	---help---
 	  Say Y here if you want to support for Freescale FlexCAN.
 
-- 
1.8.2.rc2



From jonas.jensen at gmail.com  Thu May 16 09:50:22 2013
From: jonas.jensen at gmail.com (Jonas Jensen)
Date: Thu, 16 May 2013 15:50:22 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <201305160054.21064.arnd@arndb.de>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201305151516.52389.arnd@arndb.de>
 <20130515133237.GK18614@n2100.arm.linux.org.uk>
 <201305160054.21064.arnd@arndb.de>
Message-ID: <CACmBeS2B7TCeqF2rRRVqPw94SpJHQmmbV33SaMO_R_=5Y1DrjQ@mail.gmail.com>

On 16 May 2013 00:54, Arnd Bergmann <arnd at arndb.de> wrote:
> Ah, I see. I also read the mach-gemini version of the idle code,
> which is apparently the same thing as the code that was commented
> out here, so that has the wakeup race.

The empty moxart_idle is the only way I get a successful boot to init.
It stalls half way using code from gemini or if left out (arm_pm_idle
not set).

"INFO: rcu_preempt detected stalls on CPUs/tasks" is printed in a loop
with the code from gemini though.

logs:

default idle (arm_pm_idle not set):

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.10.0-rc1-next-20130515+ (i at Ildjarn)
(gcc version 4.6.3 (crosstool-NG 1.16.0) ) #130 PREEMPT Thu May 16
09:25:22 CEST 2013
[    0.000000] CPU: FA526 [66015261] revision 1 (ARMv4), cr=0000397f
[    0.000000] CPU: VIVT data cache, VIVT instruction cache
[    0.000000] Machine: MOXA UC-7112-LX, model: MOXA UC-7112-LX
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] On node 0 totalpages: 8192
[    0.000000] free_area_init_node: node 0, pgdat c02d58c4,
node_mem_map c07f8000
[    0.000000]   Normal zone: 64 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 8192 pages, LIFO batch:0
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 8128
[    0.000000] Kernel command line: initcall_debug debug loglevel=9
console=ttyS0,115200n8 root=/dev/mmcblk0p1 rw rootwait
[    0.000000] PID hash table entries: 128 (order: -3, 512 bytes)
[    0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Memory: 32MB = 32MB total
[    0.000000] Memory: 24284k/24284k available, 8484k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc2800000 - 0xff000000   ( 968 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc2000000   (  32 MB)
[    0.000000]       .text : 0xc0008000 - 0xc02a19bc   (2663 kB)
[    0.000000]       .init : 0xc02a2000 - 0xc02b8638   (  90 kB)
[    0.000000]       .data : 0xc02ba000 - 0xc02d60c0   ( 113 kB)
[    0.000000]        .bss : 0xc02d60c0 - 0xc07f5f14   (5248 kB)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] NR_IRQS:16 nr_irqs:32 32
[    0.000000] /soc/interrupt-controller at 98800000: moxart_of_init finished
[    0.000000] /soc/timer at 98400000: count/load (APB_CLK=48000000/HZ=100) IRQ=19
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns,
wraps every 4294967286ms
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat,
Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.010000] Calibrating delay loop... 144.79 BogoMIPS (lpj=723968)
[    0.080000] pid_max: default: 4096 minimum: 301
[    0.080000] Mount-cache hash table entries: 512
[    0.110000] CPU: Testing write buffer coherency: ok
[    0.110000] calling  init_static_idmap+0x0/0xd4 @ 1
[    0.120000] Setting up static identity map for 0xc0219820 - 0xc0219868
[    0.120000] initcall init_static_idmap+0x0/0xd4 returned 0 after 0 usecs
[    0.120000] calling  spawn_ksoftirqd+0x0/0x1c @ 1
[    0.120000] initcall spawn_ksoftirqd+0x0/0x1c returned 0 after 0 usecs
[    0.120000] calling  init_workqueues+0x0/0x2c0 @ 1
[    0.130000] initcall init_workqueues+0x0/0x2c0 returned 0 after 9765 usecs
[    0.130000] calling  check_cpu_stall_init+0x0/0x20 @ 1
[    0.130000] initcall check_cpu_stall_init+0x0/0x20 returned 0 after 0 usecs
[    0.130000] calling  rcu_scheduler_really_started+0x0/0x18 @ 1
[    0.130000] initcall rcu_scheduler_really_started+0x0/0x18 returned
0 after 0 usecs
[    0.130000] calling  rcu_spawn_gp_kthread+0x0/0x7c @ 1
[    0.140000] initcall rcu_spawn_gp_kthread+0x0/0x7c returned 0 after
9765 usecs
[    0.150000] devtmpfs: initialized
[    0.160000] calling  ipc_ns_init+0x0/0x18 @ 1
[    0.160000] initcall ipc_ns_init+0x0/0x18 returned 0 after 0 usecs
[    0.160000] calling  init_mmap_min_addr+0x0/0x20 @ 1
[    0.160000] initcall init_mmap_min_addr+0x0/0x20 returned 0 after 0 usecs
[    0.160000] calling  net_ns_init+0x0/0x1d4 @ 1
[    0.160000] initcall net_ns_init+0x0/0x1d4 returned 0 after 0 usecs
[    0.160000] calling  ptrace_break_init+0x0/0x2c @ 1
[    0.160000] initcall ptrace_break_init+0x0/0x2c returned 0 after 0 usecs
[    0.160000] calling  wq_sysfs_init+0x0/0x10 @ 1
[    0.170000] initcall wq_sysfs_init+0x0/0x10 returned 0 after 9765 usecs
[    0.170000] calling  ksysfs_init+0x0/0x98 @ 1
[    0.170000] initcall ksysfs_init+0x0/0x98 returned 0 after 0 usecs
[    0.170000] calling  init_jiffies_clocksource+0x0/0xc @ 1
[    0.170000] initcall init_jiffies_clocksource+0x0/0xc returned 0
after 0 usecs
[    0.170000] calling  init_zero_pfn+0x0/0x44 @ 1
[    0.180000] initcall init_zero_pfn+0x0/0x44 returned 0 after 0 usecs
[    0.180000] calling  fsnotify_init+0x0/0x34 @ 1
[    0.180000] initcall fsnotify_init+0x0/0x34 returned 0 after 0 usecs
[    0.180000] calling  filelock_init+0x0/0x40 @ 1
[    0.180000] initcall filelock_init+0x0/0x40 returned 0 after 0 usecs
[    0.180000] calling  init_script_binfmt+0x0/0x1c @ 1
[    0.180000] initcall init_script_binfmt+0x0/0x1c returned 0 after 0 usecs
[    0.180000] calling  init_elf_binfmt+0x0/0x1c @ 1
[    0.180000] initcall init_elf_binfmt+0x0/0x1c returned 0 after 0 usecs
[    0.180000] calling  prandom_init+0x0/0x88 @ 1
[    0.180000] initcall prandom_init+0x0/0x88 returned 0 after 0 usecs
[    0.180000] calling  sock_init+0x0/0x90 @ 1
[    0.180000] initcall sock_init+0x0/0x90 returned 0 after 0 usecs
[    0.180000] calling  netlink_proto_init+0x0/0x22c @ 1
[    0.190000] NET: Registered protocol family 16
[    0.190000] initcall netlink_proto_init+0x0/0x22c returned 0 after 9765 usecs
[    0.190000] calling  atomic_pool_init+0x0/0x124 @ 1
[    0.200000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.200000] initcall atomic_pool_init+0x0/0x124 returned 0 after 9765 usecs
[    0.200000] calling  bdi_class_init+0x0/0x44 @ 1
[    0.200000] initcall bdi_class_init+0x0/0x44 returned 0 after 0 usecs
[    0.200000] calling  kobject_uevent_init+0x0/0xc @ 1
[    0.200000] initcall kobject_uevent_init+0x0/0xc returned 0 after 0 usecs
[    0.200000] calling  moxart_gpio_init+0x0/0xc @ 1
[    0.210000] initcall moxart_gpio_init+0x0/0xc returned 0 after 9765 usecs
[    0.210000] calling  tty_class_init+0x0/0x44 @ 1
[    0.210000] initcall tty_class_init+0x0/0x44 returned 0 after 0 usecs
[    0.210000] calling  gate_vma_init+0x0/0x24 @ 1
[    0.210000] initcall gate_vma_init+0x0/0x24 returned 0 after 0 usecs
[    0.210000] calling  customize_machine+0x0/0x44 @ 1
[    0.240000] moxart-gpio 98700000.gpio: finished moxart_gpio_probe
gpio_base=c284a000 pmu_base=c284c000
[    0.290000] initcall customize_machine+0x0/0x44 returned 0 after 78125 usecs
[    0.290000] calling  exceptions_init+0x0/0x90 @ 1
[    0.290000] initcall exceptions_init+0x0/0x90 returned 0 after 0 usecs
[    0.290000] calling  dma_bus_init+0x0/0x14 @ 1
[    0.290000] initcall dma_bus_init+0x0/0x14 returned 0 after 0 usecs
[    0.290000] calling  dma_channel_table_init+0x0/0x11c @ 1
[    0.290000] initcall dma_channel_table_init+0x0/0x11c returned 0
after 0 usecs
[    0.290000] calling  topology_init+0x0/0x28 @ 1
[    0.300000] initcall topology_init+0x0/0x28 returned 0 after 9765 usecs
[    0.300000] calling  param_sysfs_init+0x0/0x2d0 @ 1
[    0.480000] initcall param_sysfs_init+0x0/0x2d0 returned 0 after 175781 usecs
[    0.480000] calling  pm_sysrq_init+0x0/0x1c @ 1
[    0.480000] initcall pm_sysrq_init+0x0/0x1c returned 0 after 0 usecs
[    0.480000] calling  default_bdi_init+0x0/0x7c @ 1
[    0.490000] initcall default_bdi_init+0x0/0x7c returned 0 after 9765 usecs
[    0.490000] calling  init_bio+0x0/0xfc @ 1
[    0.490000] bio: create slab <bio-0> at 0
[    0.490000] initcall init_bio+0x0/0xfc returned 0 after 0 usecs
[    0.490000] calling  fsnotify_notification_init+0x0/0x98 @ 1
[    0.500000] initcall fsnotify_notification_init+0x0/0x98 returned 0
after 0 usecs
[    0.500000] calling  blk_settings_init+0x0/0x34 @ 1
[    0.500000] initcall blk_settings_init+0x0/0x34 returned 0 after 0 usecs
[    0.500000] calling  blk_ioc_init+0x0/0x40 @ 1
[    0.500000] initcall blk_ioc_init+0x0/0x40 returned 0 after 0 usecs
[    0.500000] calling  blk_softirq_init+0x0/0x2c @ 1
[    0.500000] initcall blk_softirq_init+0x0/0x2c returned 0 after 0 usecs
[    0.500000] calling  blk_iopoll_setup+0x0/0x2c @ 1
[    0.500000] initcall blk_iopoll_setup+0x0/0x2c returned 0 after 0 usecs
[    0.500000] calling  genhd_device_init+0x0/0x80 @ 1
[    0.500000] initcall genhd_device_init+0x0/0x80 returned 0 after 0 usecs
[    0.500000] calling  moxart_init+0x0/0xc @ 1
[    0.530000] moxart-dma-engine 90500000.dma: finished moxart_probe IRQ=24
[    0.530000] initcall moxart_init+0x0/0xc returned 0 after 19531 usecs
[    0.530000] calling  misc_init+0x0/0xc0 @ 1
[    0.540000] initcall misc_init+0x0/0xc0 returned 0 after 9765 usecs
[    0.540000] calling  rtc_init+0x0/0x60 @ 1
[    0.540000] initcall rtc_init+0x0/0x60 returned 0 after 0 usecs
[    0.540000] calling  mmc_init+0x0/0x84 @ 1
[    0.550000] initcall mmc_init+0x0/0x84 returned 0 after 9765 usecs
[    0.550000] calling  proto_init+0x0/0xc @ 1
[    0.550000] initcall proto_init+0x0/0xc returned 0 after 0 usecs
[    0.550000] calling  net_dev_init+0x0/0x180 @ 1
[    0.580000] initcall net_dev_init+0x0/0x180 returned 0 after 29296 usecs
[    0.580000] calling  neigh_init+0x0/0xa4 @ 1
[    0.580000] initcall neigh_init+0x0/0xa4 returned 0 after 0 usecs
[    0.580000] calling  genl_init+0x0/0x80 @ 1
[    0.580000] initcall genl_init+0x0/0x80 returned 0 after 0 usecs
[    0.580000] calling  proc_cpu_init+0x0/0x24 @ 1
[    0.580000] initcall proc_cpu_init+0x0/0x24 returned 0 after 0 usecs
[    0.580000] calling  dma_debug_do_init+0x0/0x8 @ 1
[    0.580000] initcall dma_debug_do_init+0x0/0x8 returned 0 after 0 usecs
[    0.580000] calling  alignment_init+0x0/0xf4 @ 1
[    0.580000] initcall alignment_init+0x0/0xf4 returned 0 after 0 usecs
[    0.580000] calling  clocksource_done_booting+0x0/0x58 @ 1
[    0.580000] initcall clocksource_done_booting+0x0/0x58 returned 0
after 0 usecs
[    0.580000] calling  init_pipe_fs+0x0/0x4c @ 1
[    0.580000] initcall init_pipe_fs+0x0/0x4c returned 0 after 0 usecs
[    0.580000] calling  eventpoll_init+0x0/0xac @ 1
[    0.590000] initcall eventpoll_init+0x0/0xac returned 0 after 9765 usecs
[    0.590000] calling  anon_inode_init+0x0/0x64 @ 1
[    0.590000] initcall anon_inode_init+0x0/0x64 returned 0 after 0 usecs
[    0.590000] calling  blk_scsi_ioctl_init+0x0/0xdc @ 1
[    0.590000] initcall blk_scsi_ioctl_init+0x0/0xdc returned 0 after 0 usecs
[    0.590000] calling  chr_dev_init+0x0/0xd4 @ 1
[    0.640000] initcall chr_dev_init+0x0/0xd4 returned 0 after 48828 usecs
[    0.640000] calling  sysctl_core_init+0x0/0x30 @ 1
[    0.640000] initcall sysctl_core_init+0x0/0x30 returned 0 after 0 usecs
[    0.640000] calling  inet_init+0x0/0x250 @ 1
[    0.650000] NET: Registered protocol family 2
[    0.660000] TCP established hash table entries: 512 (order: 0, 4096 bytes)
[    0.660000] TCP bind hash table entries: 512 (order: 2, 18432 bytes)
[    0.660000] TCP: Hash tables configured (established 512 bind 512)
[    0.660000] TCP: reno registered
[    0.660000] UDP hash table entries: 128 (order: 1, 10240 bytes)
[    0.660000] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes)
[    0.680000] initcall inet_init+0x0/0x250 returned 0 after 39062 usecs
[    0.680000] calling  ipv4_offload_init+0x0/0x64 @ 1
[    0.680000] initcall ipv4_offload_init+0x0/0x64 returned 0 after 0 usecs
[    0.680000] calling  af_unix_init+0x0/0x54 @ 1
[    0.680000] NET: Registered protocol family 1
[    0.680000] initcall af_unix_init+0x0/0x54 returned 0 after 0 usecs
[    0.680000] calling  ipv6_offload_init+0x0/0x64 @ 1
[    0.680000] initcall ipv6_offload_init+0x0/0x64 returned 0 after 0 usecs
[    0.680000] calling  default_rootfs+0x0/0x70 @ 1
[    0.680000] initcall default_rootfs+0x0/0x70 returned 0 after 0 usecs
[    0.680000] calling  sched_clock_syscore_init+0x0/0x18 @ 1
[    0.680000] initcall sched_clock_syscore_init+0x0/0x18 returned 0
after 0 usecs
[    0.680000] calling  proc_execdomains_init+0x0/0x38 @ 1
[    0.680000] initcall proc_execdomains_init+0x0/0x38 returned 0 after 0 usecs
[    0.680000] calling  ioresources_init+0x0/0x58 @ 1
[    0.680000] initcall ioresources_init+0x0/0x58 returned 0 after 0 usecs
[    0.680000] calling  uid_cache_init+0x0/0x98 @ 1
[    0.680000] initcall uid_cache_init+0x0/0x98 returned 0 after 0 usecs
[    0.680000] calling  init_posix_timers+0x0/0x208 @ 1
[    0.680000] initcall init_posix_timers+0x0/0x208 returned 0 after 0 usecs
[    0.680000] calling  init_posix_cpu_timers+0x0/0xe4 @ 1
[    0.680000] initcall init_posix_cpu_timers+0x0/0xe4 returned 0 after 0 usecs
[    0.680000] calling  timekeeping_init_ops+0x0/0x18 @ 1
[    0.680000] initcall timekeeping_init_ops+0x0/0x18 returned 0 after 0 usecs
[    0.680000] calling  init_clocksource_sysfs+0x0/0x54 @ 1
[    0.690000] initcall init_clocksource_sysfs+0x0/0x54 returned 0
after 9765 usecs
[    0.690000] calling  init_timer_list_procfs+0x0/0x40 @ 1
[    0.690000] initcall init_timer_list_procfs+0x0/0x40 returned 0 after 0 usecs
[    0.690000] calling  alarmtimer_init+0x0/0x1a4 @ 1
[    0.700000] initcall alarmtimer_init+0x0/0x1a4 returned 0 after 9765 usecs
[    0.700000] calling  lockdep_proc_init+0x0/0x74 @ 1
[    0.700000] initcall lockdep_proc_init+0x0/0x74 returned 0 after 0 usecs
[    0.700000] calling  futex_init+0x0/0x84 @ 1
[    0.700000] initcall futex_init+0x0/0x84 returned 0 after 0 usecs
[    0.700000] calling  kallsyms_init+0x0/0x38 @ 1
[    0.700000] initcall kallsyms_init+0x0/0x38 returned 0 after 0 usecs
[    0.700000] calling  ikconfig_init+0x0/0x58 @ 1
[    0.700000] initcall ikconfig_init+0x0/0x58 returned 0 after 0 usecs
[    0.700000] calling  hung_task_init+0x0/0x54 @ 1
[    0.700000] initcall hung_task_init+0x0/0x54 returned 0 after 0 usecs
[    0.710000] calling  utsname_sysctl_init+0x0/0x18 @ 1
[    0.710000] initcall utsname_sysctl_init+0x0/0x18 returned 0 after 0 usecs
[    0.710000] calling  init_per_zone_wmark_min+0x0/0x88 @ 1
[    0.710000] initcall init_per_zone_wmark_min+0x0/0x88 returned 0
after 0 usecs
[    0.710000] calling  kswapd_init+0x0/0x18 @ 1
[    0.710000] initcall kswapd_init+0x0/0x18 returned 0 after 0 usecs
[    0.710000] calling  setup_vmstat+0x0/0x90 @ 1
[    0.710000] initcall setup_vmstat+0x0/0x90 returned 0 after 0 usecs
[    0.710000] calling  mm_sysfs_init+0x0/0x38 @ 1
[    0.710000] initcall mm_sysfs_init+0x0/0x38 returned 0 after 0 usecs
[    0.710000] calling  init_reserve_notifier+0x0/0x8 @ 1
[    0.710000] initcall init_reserve_notifier+0x0/0x8 returned 0 after 0 usecs
[    0.710000] calling  init_admin_reserve+0x0/0x30 @ 1
[    0.710000] initcall init_admin_reserve+0x0/0x30 returned 0 after 0 usecs
[    0.710000] calling  init_user_reserve+0x0/0x30 @ 1
[    0.710000] initcall init_user_reserve+0x0/0x30 returned 0 after 0 usecs
[    0.710000] calling  proc_vmalloc_init+0x0/0x38 @ 1
[    0.710000] initcall proc_vmalloc_init+0x0/0x38 returned 0 after 0 usecs
[    0.710000] calling  slab_sysfs_init+0x0/0x108 @ 1
[    0.940000] initcall slab_sysfs_init+0x0/0x108 returned 0 after 224609 usecs
[    0.940000] calling  fcntl_init+0x0/0x40 @ 1
[    0.950000] initcall fcntl_init+0x0/0x40 returned 0 after 9765 usecs
[    0.950000] calling  proc_filesystems_init+0x0/0x38 @ 1
[    0.950000] initcall proc_filesystems_init+0x0/0x38 returned 0 after 0 usecs
[    0.950000] calling  dio_init+0x0/0x40 @ 1
[    0.960000] initcall dio_init+0x0/0x40 returned 0 after 9765 usecs
[    0.960000] calling  fsnotify_mark_init+0x0/0x40 @ 1
[    0.960000] initcall fsnotify_mark_init+0x0/0x40 returned 0 after 0 usecs
[    0.960000] calling  dnotify_init+0x0/0x80 @ 1
[    0.960000] initcall dnotify_init+0x0/0x80 returned 0 after 0 usecs
[    0.960000] calling  inotify_user_setup+0x0/0x78 @ 1
[    0.960000] initcall inotify_user_setup+0x0/0x78 returned 0 after 0 usecs
[    0.960000] calling  proc_locks_init+0x0/0x38 @ 1
[    0.960000] initcall proc_locks_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  init_mbcache+0x0/0x18 @ 1
[    0.960000] initcall init_mbcache+0x0/0x18 returned 0 after 0 usecs
[    0.960000] calling  proc_cmdline_init+0x0/0x38 @ 1
[    0.960000] initcall proc_cmdline_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_consoles_init+0x0/0x38 @ 1
[    0.960000] initcall proc_consoles_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_cpuinfo_init+0x0/0x38 @ 1
[    0.960000] initcall proc_cpuinfo_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_devices_init+0x0/0x38 @ 1
[    0.960000] initcall proc_devices_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_interrupts_init+0x0/0x38 @ 1
[    0.960000] initcall proc_interrupts_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_loadavg_init+0x0/0x38 @ 1
[    0.960000] initcall proc_loadavg_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_meminfo_init+0x0/0x38 @ 1
[    0.960000] initcall proc_meminfo_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_stat_init+0x0/0x38 @ 1
[    0.960000] initcall proc_stat_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_uptime_init+0x0/0x38 @ 1
[    0.960000] initcall proc_uptime_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_version_init+0x0/0x38 @ 1
[    0.960000] initcall proc_version_init+0x0/0x38 returned 0 after 0 usecs
[    0.970000] calling  proc_softirqs_init+0x0/0x38 @ 1
[    0.970000] initcall proc_softirqs_init+0x0/0x38 returned 0 after 0 usecs
[    0.970000] calling  proc_kmsg_init+0x0/0x38 @ 1
[    0.970000] initcall proc_kmsg_init+0x0/0x38 returned 0 after 0 usecs
[    0.970000] calling  proc_page_init+0x0/0x58 @ 1
[    0.970000] initcall proc_page_init+0x0/0x58 returned 0 after 0 usecs
[    0.970000] calling  init_devpts_fs+0x0/0x68 @ 1
[    0.970000] initcall init_devpts_fs+0x0/0x68 returned 0 after 0 usecs
[    0.970000] calling  init_ext3_fs+0x0/0x8c @ 1
[    0.980000] initcall init_ext3_fs+0x0/0x8c returned 0 after 9765 usecs
[    0.980000] calling  journal_init+0x0/0xb4 @ 1
[    1.000000] initcall journal_init+0x0/0xb4 returned 0 after 19531 usecs
[    1.000000] calling  init_ramfs_fs+0x0/0xc @ 1
[    1.000000] initcall init_ramfs_fs+0x0/0xc returned 0 after 0 usecs
[    1.000000] calling  init_jffs2_fs+0x0/0xd8 @ 1
[    1.000000] jffs2: version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
[    1.010000] initcall init_jffs2_fs+0x0/0xd8 returned 0 after 9765 usecs
[    1.010000] calling  ipc_init+0x0/0x24 @ 1
[    1.010000] msgmni has been set to 47
[    1.010000] initcall ipc_init+0x0/0x24 returned 0 after 0 usecs
[    1.010000] calling  ipc_sysctl_init+0x0/0x18 @ 1
[    1.010000] initcall ipc_sysctl_init+0x0/0x18 returned 0 after 0 usecs
[    1.010000] calling  key_proc_init+0x0/0x48 @ 1
[    1.010000] initcall key_proc_init+0x0/0x48 returned 0 after 0 usecs
[    1.010000] calling  crypto_algapi_init+0x0/0x10 @ 1
[    1.010000] initcall crypto_algapi_init+0x0/0x10 returned 0 after 0 usecs
[    1.010000] calling  aes_init+0x0/0xc @ 1
[    1.020000] initcall aes_init+0x0/0xc returned 0 after 9765 usecs
[    1.020000] calling  krng_mod_init+0x0/0xc @ 1
[    1.020000] initcall krng_mod_init+0x0/0xc returned 0 after 0 usecs
[    1.020000] calling  prng_mod_init+0x0/0x10 @ 1
[    1.020000] initcall prng_mod_init+0x0/0x10 returned 0 after 0 usecs
[    1.020000] calling  proc_genhd_init+0x0/0x58 @ 1
[    1.020000] initcall proc_genhd_init+0x0/0x58 returned 0 after 0 usecs
[    1.020000] calling  noop_init+0x0/0xc @ 1
[    1.020000] io scheduler noop registered
[    1.020000] initcall noop_init+0x0/0xc returned 0 after 0 usecs
[    1.020000] calling  cfq_init+0x0/0x94 @ 1
[    1.020000] io scheduler cfq registered (default)
[    1.020000] initcall cfq_init+0x0/0x94 returned 0 after 0 usecs
[    1.020000] calling  pty_init+0x0/0x230 @ 1
[    1.020000] initcall pty_init+0x0/0x230 returned 0 after 0 usecs
[    1.030000] calling  sysrq_init+0x0/0x48 @ 1
[    1.030000] initcall sysrq_init+0x0/0x48 returned 0 after 0 usecs
[    1.030000] calling  serial8250_init+0x0/0x158 @ 1
[    1.030000] Serial: 8250/16550 driver, 1 ports, IRQ sharing enabled
[    1.040000] initcall serial8250_init+0x0/0x158 returned 0 after 9765 usecs
[    1.040000] calling  of_platform_serial_driver_init+0x0/0xc @ 1
[    1.070000] 98200000.uart: ttyS0 at MMIO 0x98200000 (irq = 31) is a 16550A
[    2.960000] console [ttyS0] enabled
[    2.970000] initcall of_platform_serial_driver_init+0x0/0xc
returned 0 after 1884765 usecs
[    2.980000] calling  mxser_module_init+0x0/0x49c @ 1
[    2.990000] MOXA Smartio/Industio family driver version 2.0.5
[    3.000000] mxser: found MOXA UC-7112-LX board (CAP=0x0)
[    3.000000] mxser: mxser_initbrd success IRQ=31 max baud=921600 bps
[    3.020000] initcall mxser_module_init+0x0/0x49c returned 0 after 29296 usecs
[    3.030000] calling  rand_initialize+0x0/0x2c @ 1
[    3.030000] initcall rand_initialize+0x0/0x2c returned 0 after 0 usecs
[    3.040000] calling  topology_sysfs_init+0x0/0x20 @ 1
[    3.050000] initcall topology_sysfs_init+0x0/0x20 returned 0 after 0 usecs
[    3.060000] calling  init_mtd+0x0/0xf8 @ 1
[    3.070000] initcall init_mtd+0x0/0xf8 returned 0 after 9765 usecs
[    3.080000] calling  ofpart_parser_init+0x0/0x38 @ 1
[    3.090000] initcall ofpart_parser_init+0x0/0x38 returned 0 after 0 usecs
[    3.100000] calling  init_mtdblock+0x0/0xc @ 1
[    3.100000] initcall init_mtdblock+0x0/0xc returned 0 after 0 usecs
[    3.110000] calling  cfi_probe_init+0x0/0x18 @ 1
[    3.120000] initcall cfi_probe_init+0x0/0x18 returned 0 after 0 usecs
[    3.120000] calling  physmap_init+0x0/0xc @ 1
[    3.130000] initcall physmap_init+0x0/0xc returned 0 after 0 usecs
[    3.140000] calling  of_flash_driver_init+0x0/0xc @ 1
[    3.170000] 80000000.flash: Found 1 x16 devices at 0x0 in 16-bit
bank. Manufacturer ID 0x000089 Chip ID 0x000018
[    3.180000] Intel/Sharp Extended Query Table at 0x0031
[    3.190000] Intel/Sharp Extended Query Table at 0x0031
[    3.190000] Using buffer write method
[    3.200000] cfi_cmdset_0001: Erase suspend on write enabled
[    3.200000] erase region 0: offset=0x0,size=0x20000,blocks=128
[    3.210000] 4 ofpart partitions found on MTD device 80000000.flash
[    3.220000] Creating 4 MTD partitions on "80000000.flash":
[    3.220000] 0x000000000000-0x000000040000 : "bootloader"
[    3.260000] 0x000000040000-0x000000200000 : "linux kernel"
[    3.300000] 0x000000200000-0x000000a00000 : "root filesystem"
[    3.330000] 0x000000a00000-0x000001000000 : "user filesystem"
[    3.370000] initcall of_flash_driver_init+0x0/0xc returned 0 after
224609 usecs
[    3.370000] calling  net_olddevs_init+0x0/0x68 @ 1
[    3.380000] initcall net_olddevs_init+0x0/0x68 returned 0 after 0 usecs
[    3.390000] calling  moxart_mac_init+0x0/0xc @ 1
[    3.440000] moxart-ethernet 90900000.mac eth0: moxart_mac_probe:
IRQ=25 address=00:90:e8:1b:e2:a5
[    3.500000] moxart-ethernet 92000000.mac eth1: moxart_mac_probe:
IRQ=27 address=00:90:e8:1b:e2:a6
[    3.520000] initcall moxart_mac_init+0x0/0xc returned 0 after 126953 usecs
[    3.520000] calling  moxart_rtc_init+0x0/0xc @ 1
[    3.540000] moxart-rtc rtc.0: rtc core: registered rtc.0 as rtc0
[    3.550000] moxart-rtc rtc.0: finished moxart_rtc_probe
[    3.560000] initcall moxart_rtc_init+0x0/0xc returned 0 after 29296 usecs
[    3.570000] calling  moxart_wdt_init+0x0/0xc @ 1
[    3.580000] moxart-watchdog 98500000.watchdog: finished
moxart_wdt_probe base=c2920000
[    3.600000] initcall moxart_wdt_init+0x0/0xc returned 0 after 29296 usecs
[    3.600000] calling  mmc_blk_init+0x0/0x74 @ 1
[    3.610000] initcall mmc_blk_init+0x0/0x74 returned 0 after 0 usecs
[    3.620000] calling  moxart_init+0x0/0xc @ 1


gemini idle:

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.10.0-rc1-next-20130515+ (i at Ildjarn)
(gcc version 4.6.3 (crosstool-NG 1.16.0) ) #129 PREEMPT Thu May 16
09:20:50 CEST 2013
[    0.000000] CPU: FA526 [66015261] revision 1 (ARMv4), cr=0000397f
[    0.000000] CPU: VIVT data cache, VIVT instruction cache
[    0.000000] Machine: MOXA UC-7112-LX, model: MOXA UC-7112-LX
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] On node 0 totalpages: 8192
[    0.000000] free_area_init_node: node 0, pgdat c02d58c4,
node_mem_map c07f8000
[    0.000000]   Normal zone: 64 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 8192 pages, LIFO batch:0
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 8128
[    0.000000] Kernel command line: initcall_debug debug loglevel=9
console=ttyS0,115200n8 root=/dev/mmcblk0p1 rw rootwait
[    0.000000] PID hash table entries: 128 (order: -3, 512 bytes)
[    0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Memory: 32MB = 32MB total
[    0.000000] Memory: 24284k/24284k available, 8484k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc2800000 - 0xff000000   ( 968 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc2000000   (  32 MB)
[    0.000000]       .text : 0xc0008000 - 0xc02a19d0   (2663 kB)
[    0.000000]       .init : 0xc02a2000 - 0xc02b865c   (  90 kB)
[    0.000000]       .data : 0xc02ba000 - 0xc02d60c0   ( 113 kB)
[    0.000000]        .bss : 0xc02d60c0 - 0xc07f5f14   (5248 kB)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] NR_IRQS:16 nr_irqs:32 32
[    0.000000] /soc/interrupt-controller at 98800000: moxart_of_init finished
[    0.000000] /soc/timer at 98400000: count/load (APB_CLK=48000000/HZ=100) IRQ=19
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns,
wraps every 4294967286ms
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat,
Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.010000] Calibrating delay loop... 144.79 BogoMIPS (lpj=723968)
[    0.080000] pid_max: default: 4096 minimum: 301
[    0.080000] Mount-cache hash table entries: 512
[    0.110000] CPU: Testing write buffer coherency: ok
[    0.120000] calling  init_static_idmap+0x0/0xd4 @ 1
[    0.120000] Setting up static identity map for 0xc0219820 - 0xc0219868
[    0.120000] initcall init_static_idmap+0x0/0xd4 returned 0 after 0 usecs
[    0.120000] calling  spawn_ksoftirqd+0x0/0x1c @ 1
[    0.120000] initcall spawn_ksoftirqd+0x0/0x1c returned 0 after 0 usecs
[    0.120000] calling  init_workqueues+0x0/0x2c0 @ 1
[    0.130000] initcall init_workqueues+0x0/0x2c0 returned 0 after 9765 usecs
[    0.130000] calling  check_cpu_stall_init+0x0/0x20 @ 1
[    0.130000] initcall check_cpu_stall_init+0x0/0x20 returned 0 after 0 usecs
[    0.130000] calling  rcu_scheduler_really_started+0x0/0x18 @ 1
[    0.130000] initcall rcu_scheduler_really_started+0x0/0x18 returned
0 after 0 usecs
[    0.130000] calling  rcu_spawn_gp_kthread+0x0/0x7c @ 1
[    0.140000] initcall rcu_spawn_gp_kthread+0x0/0x7c returned 0 after
9765 usecs
[    0.150000] devtmpfs: initialized
[    0.160000] calling  ipc_ns_init+0x0/0x18 @ 1
[    0.160000] initcall ipc_ns_init+0x0/0x18 returned 0 after 0 usecs
[    0.160000] calling  init_mmap_min_addr+0x0/0x20 @ 1
[    0.160000] initcall init_mmap_min_addr+0x0/0x20 returned 0 after 0 usecs
[    0.160000] calling  net_ns_init+0x0/0x1d4 @ 1
[    0.160000] initcall net_ns_init+0x0/0x1d4 returned 0 after 0 usecs
[    0.160000] calling  ptrace_break_init+0x0/0x2c @ 1
[    0.160000] initcall ptrace_break_init+0x0/0x2c returned 0 after 0 usecs
[    0.160000] calling  wq_sysfs_init+0x0/0x10 @ 1
[    0.170000] initcall wq_sysfs_init+0x0/0x10 returned 0 after 9765 usecs
[    0.170000] calling  ksysfs_init+0x0/0x98 @ 1
[    0.170000] initcall ksysfs_init+0x0/0x98 returned 0 after 0 usecs
[    0.170000] calling  init_jiffies_clocksource+0x0/0xc @ 1
[    0.170000] initcall init_jiffies_clocksource+0x0/0xc returned 0
after 0 usecs
[    0.180000] calling  init_zero_pfn+0x0/0x44 @ 1
[    0.180000] initcall init_zero_pfn+0x0/0x44 returned 0 after 0 usecs
[    0.180000] calling  fsnotify_init+0x0/0x34 @ 1
[    0.180000] initcall fsnotify_init+0x0/0x34 returned 0 after 0 usecs
[    0.180000] calling  filelock_init+0x0/0x40 @ 1
[    0.180000] initcall filelock_init+0x0/0x40 returned 0 after 0 usecs
[    0.180000] calling  init_script_binfmt+0x0/0x1c @ 1
[    0.180000] initcall init_script_binfmt+0x0/0x1c returned 0 after 0 usecs
[    0.180000] calling  init_elf_binfmt+0x0/0x1c @ 1
[    0.180000] initcall init_elf_binfmt+0x0/0x1c returned 0 after 0 usecs
[    0.180000] calling  prandom_init+0x0/0x88 @ 1
[    0.180000] initcall prandom_init+0x0/0x88 returned 0 after 0 usecs
[    0.180000] calling  sock_init+0x0/0x90 @ 1
[    0.180000] initcall sock_init+0x0/0x90 returned 0 after 0 usecs
[    0.180000] calling  netlink_proto_init+0x0/0x22c @ 1
[    0.190000] NET: Registered protocol family 16
[    0.190000] initcall netlink_proto_init+0x0/0x22c returned 0 after 9765 usecs
[    0.190000] calling  atomic_pool_init+0x0/0x124 @ 1
[    0.200000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.200000] initcall atomic_pool_init+0x0/0x124 returned 0 after 9765 usecs
[    0.200000] calling  bdi_class_init+0x0/0x44 @ 1
[    0.200000] initcall bdi_class_init+0x0/0x44 returned 0 after 0 usecs
[    0.200000] calling  kobject_uevent_init+0x0/0xc @ 1
[    0.200000] initcall kobject_uevent_init+0x0/0xc returned 0 after 0 usecs
[    0.200000] calling  moxart_gpio_init+0x0/0xc @ 1
[    0.210000] initcall moxart_gpio_init+0x0/0xc returned 0 after 9765 usecs
[    0.210000] calling  tty_class_init+0x0/0x44 @ 1
[    0.210000] initcall tty_class_init+0x0/0x44 returned 0 after 0 usecs
[    0.210000] calling  gate_vma_init+0x0/0x24 @ 1
[    0.210000] initcall gate_vma_init+0x0/0x24 returned 0 after 0 usecs
[    0.210000] calling  customize_machine+0x0/0x44 @ 1
[    0.240000] moxart-gpio 98700000.gpio: finished moxart_gpio_probe
gpio_base=c284a000 pmu_base=c284c000
[    0.280000] initcall customize_machine+0x0/0x44 returned 0 after 68359 usecs
[    0.290000] calling  exceptions_init+0x0/0x90 @ 1
[    0.290000] initcall exceptions_init+0x0/0x90 returned 0 after 0 usecs
[    0.290000] calling  moxart_idle_init+0x0/0x1c @ 1
[    0.290000] initcall moxart_idle_init+0x0/0x1c returned 0 after 0 usecs
[    0.290000] calling  dma_bus_init+0x0/0x14 @ 1
[    0.290000] initcall dma_bus_init+0x0/0x14 returned 0 after 0 usecs
[    0.290000] calling  dma_channel_table_init+0x0/0x11c @ 1
[    0.290000] initcall dma_channel_table_init+0x0/0x11c returned 0
after 0 usecs
[    0.290000] calling  topology_init+0x0/0x28 @ 1
[    0.290000] initcall topology_init+0x0/0x28 returned 0 after 0 usecs
[    0.300000] calling  param_sysfs_init+0x0/0x2d0 @ 1
[    0.480000] initcall param_sysfs_init+0x0/0x2d0 returned 0 after 175781 usecs
[    0.480000] calling  pm_sysrq_init+0x0/0x1c @ 1
[    0.480000] initcall pm_sysrq_init+0x0/0x1c returned 0 after 0 usecs
[    0.480000] calling  default_bdi_init+0x0/0x7c @ 1
[    0.490000] initcall default_bdi_init+0x0/0x7c returned 0 after 9765 usecs
[    0.490000] calling  init_bio+0x0/0xfc @ 1
[    0.490000] bio: create slab <bio-0> at 0
[    0.490000] initcall init_bio+0x0/0xfc returned 0 after 0 usecs
[    0.490000] calling  fsnotify_notification_init+0x0/0x98 @ 1
[    0.490000] initcall fsnotify_notification_init+0x0/0x98 returned 0
after 0 usecs
[    0.490000] calling  blk_settings_init+0x0/0x34 @ 1
[    0.490000] initcall blk_settings_init+0x0/0x34 returned 0 after 0 usecs
[    0.490000] calling  blk_ioc_init+0x0/0x40 @ 1
[    0.490000] initcall blk_ioc_init+0x0/0x40 returned 0 after 0 usecs
[    0.490000] calling  blk_softirq_init+0x0/0x2c @ 1
[    0.490000] initcall blk_softirq_init+0x0/0x2c returned 0 after 0 usecs
[    0.490000] calling  blk_iopoll_setup+0x0/0x2c @ 1
[    0.490000] initcall blk_iopoll_setup+0x0/0x2c returned 0 after 0 usecs
[    0.490000] calling  genhd_device_init+0x0/0x80 @ 1
[    0.500000] initcall genhd_device_init+0x0/0x80 returned 0 after 9765 usecs
[    0.500000] calling  moxart_init+0x0/0xc @ 1
[    0.520000] moxart-dma-engine 90500000.dma: finished moxart_probe IRQ=24
[    0.530000] initcall moxart_init+0x0/0xc returned 0 after 29296 usecs
[    0.530000] calling  misc_init+0x0/0xc0 @ 1
[    0.530000] initcall misc_init+0x0/0xc0 returned 0 after 0 usecs
[    0.530000] calling  rtc_init+0x0/0x60 @ 1
[    0.540000] initcall rtc_init+0x0/0x60 returned 0 after 0 usecs
[    0.540000] calling  mmc_init+0x0/0x84 @ 1
[    0.550000] initcall mmc_init+0x0/0x84 returned 0 after 9765 usecs
[    0.550000] calling  proto_init+0x0/0xc @ 1
[    0.550000] initcall proto_init+0x0/0xc returned 0 after 0 usecs
[    0.550000] calling  net_dev_init+0x0/0x180 @ 1
[    0.570000] initcall net_dev_init+0x0/0x180 returned 0 after 19531 usecs
[    0.570000] calling  neigh_init+0x0/0xa4 @ 1
[    0.570000] initcall neigh_init+0x0/0xa4 returned 0 after 0 usecs
[    0.570000] calling  genl_init+0x0/0x80 @ 1
[    0.580000] initcall genl_init+0x0/0x80 returned 0 after 9765 usecs
[    0.580000] calling  proc_cpu_init+0x0/0x24 @ 1
[    0.580000] initcall proc_cpu_init+0x0/0x24 returned 0 after 0 usecs
[    0.580000] calling  dma_debug_do_init+0x0/0x8 @ 1
[    0.580000] initcall dma_debug_do_init+0x0/0x8 returned 0 after 0 usecs
[    0.580000] calling  alignment_init+0x0/0xf4 @ 1
[    0.580000] initcall alignment_init+0x0/0xf4 returned 0 after 0 usecs
[    0.580000] calling  clocksource_done_booting+0x0/0x58 @ 1
[    0.580000] initcall clocksource_done_booting+0x0/0x58 returned 0
after 0 usecs
[    0.580000] calling  init_pipe_fs+0x0/0x4c @ 1
[    0.580000] initcall init_pipe_fs+0x0/0x4c returned 0 after 0 usecs
[    0.580000] calling  eventpoll_init+0x0/0xac @ 1
[    0.580000] initcall eventpoll_init+0x0/0xac returned 0 after 0 usecs
[    0.580000] calling  anon_inode_init+0x0/0x64 @ 1
[    0.580000] initcall anon_inode_init+0x0/0x64 returned 0 after 0 usecs
[    0.590000] calling  blk_scsi_ioctl_init+0x0/0xdc @ 1
[    0.590000] initcall blk_scsi_ioctl_init+0x0/0xdc returned 0 after 0 usecs
[    0.590000] calling  chr_dev_init+0x0/0xd4 @ 1
[    0.640000] initcall chr_dev_init+0x0/0xd4 returned 0 after 48828 usecs
[    0.640000] calling  sysctl_core_init+0x0/0x30 @ 1
[    0.640000] initcall sysctl_core_init+0x0/0x30 returned 0 after 0 usecs
[    0.640000] calling  inet_init+0x0/0x250 @ 1
[    0.640000] NET: Registered protocol family 2
[    0.650000] TCP established hash table entries: 512 (order: 0, 4096 bytes)
[    0.660000] TCP bind hash table entries: 512 (order: 2, 18432 bytes)
[    0.660000] TCP: Hash tables configured (established 512 bind 512)
[    0.660000] TCP: reno registered
[    0.660000] UDP hash table entries: 128 (order: 1, 10240 bytes)
[    0.660000] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes)
[    0.670000] initcall inet_init+0x0/0x250 returned 0 after 29296 usecs
[    0.670000] calling  ipv4_offload_init+0x0/0x64 @ 1
[    0.670000] initcall ipv4_offload_init+0x0/0x64 returned 0 after 0 usecs
[    0.670000] calling  af_unix_init+0x0/0x54 @ 1
[    0.670000] NET: Registered protocol family 1
[    0.670000] initcall af_unix_init+0x0/0x54 returned 0 after 0 usecs
[    0.670000] calling  ipv6_offload_init+0x0/0x64 @ 1
[    0.670000] initcall ipv6_offload_init+0x0/0x64 returned 0 after 0 usecs
[    0.670000] calling  default_rootfs+0x0/0x70 @ 1
[    0.670000] initcall default_rootfs+0x0/0x70 returned 0 after 0 usecs
[    0.680000] calling  sched_clock_syscore_init+0x0/0x18 @ 1
[    0.680000] initcall sched_clock_syscore_init+0x0/0x18 returned 0
after 0 usecs
[    0.680000] calling  proc_execdomains_init+0x0/0x38 @ 1
[    0.680000] initcall proc_execdomains_init+0x0/0x38 returned 0 after 0 usecs
[    0.680000] calling  ioresources_init+0x0/0x58 @ 1
[    0.680000] initcall ioresources_init+0x0/0x58 returned 0 after 0 usecs
[    0.680000] calling  uid_cache_init+0x0/0x98 @ 1
[    0.680000] initcall uid_cache_init+0x0/0x98 returned 0 after 0 usecs
[    0.680000] calling  init_posix_timers+0x0/0x208 @ 1
[    0.680000] initcall init_posix_timers+0x0/0x208 returned 0 after 0 usecs
[    0.680000] calling  init_posix_cpu_timers+0x0/0xe4 @ 1
[    0.680000] initcall init_posix_cpu_timers+0x0/0xe4 returned 0 after 0 usecs
[    0.680000] calling  timekeeping_init_ops+0x0/0x18 @ 1
[    0.680000] initcall timekeeping_init_ops+0x0/0x18 returned 0 after 0 usecs
[    0.680000] calling  init_clocksource_sysfs+0x0/0x54 @ 1
[    0.690000] initcall init_clocksource_sysfs+0x0/0x54 returned 0
after 9765 usecs
[    0.690000] calling  init_timer_list_procfs+0x0/0x40 @ 1
[    0.690000] initcall init_timer_list_procfs+0x0/0x40 returned 0 after 0 usecs
[    0.690000] calling  alarmtimer_init+0x0/0x1a4 @ 1
[    0.700000] initcall alarmtimer_init+0x0/0x1a4 returned 0 after 9765 usecs
[    0.700000] calling  lockdep_proc_init+0x0/0x74 @ 1
[    0.700000] initcall lockdep_proc_init+0x0/0x74 returned 0 after 0 usecs
[    0.700000] calling  futex_init+0x0/0x84 @ 1
[    0.700000] initcall futex_init+0x0/0x84 returned 0 after 0 usecs
[    0.700000] calling  kallsyms_init+0x0/0x38 @ 1
[    0.700000] initcall kallsyms_init+0x0/0x38 returned 0 after 0 usecs
[    0.700000] calling  ikconfig_init+0x0/0x58 @ 1
[    0.700000] initcall ikconfig_init+0x0/0x58 returned 0 after 0 usecs
[    0.700000] calling  hung_task_init+0x0/0x54 @ 1
[    0.700000] initcall hung_task_init+0x0/0x54 returned 0 after 0 usecs
[    0.700000] calling  utsname_sysctl_init+0x0/0x18 @ 1
[    0.700000] initcall utsname_sysctl_init+0x0/0x18 returned 0 after 0 usecs
[    0.700000] calling  init_per_zone_wmark_min+0x0/0x88 @ 1
[    0.700000] initcall init_per_zone_wmark_min+0x0/0x88 returned 0
after 0 usecs
[    0.700000] calling  kswapd_init+0x0/0x18 @ 1
[    0.700000] initcall kswapd_init+0x0/0x18 returned 0 after 0 usecs
[    0.700000] calling  setup_vmstat+0x0/0x90 @ 1
[    0.700000] initcall setup_vmstat+0x0/0x90 returned 0 after 0 usecs
[    0.700000] calling  mm_sysfs_init+0x0/0x38 @ 1
[    0.700000] initcall mm_sysfs_init+0x0/0x38 returned 0 after 0 usecs
[    0.710000] calling  init_reserve_notifier+0x0/0x8 @ 1
[    0.710000] initcall init_reserve_notifier+0x0/0x8 returned 0 after 0 usecs
[    0.710000] calling  init_admin_reserve+0x0/0x30 @ 1
[    0.710000] initcall init_admin_reserve+0x0/0x30 returned 0 after 0 usecs
[    0.710000] calling  init_user_reserve+0x0/0x30 @ 1
[    0.710000] initcall init_user_reserve+0x0/0x30 returned 0 after 0 usecs
[    0.710000] calling  proc_vmalloc_init+0x0/0x38 @ 1
[    0.710000] initcall proc_vmalloc_init+0x0/0x38 returned 0 after 0 usecs
[    0.710000] calling  slab_sysfs_init+0x0/0x108 @ 1
[    0.940000] initcall slab_sysfs_init+0x0/0x108 returned 0 after 224609 usecs
[    0.940000] calling  fcntl_init+0x0/0x40 @ 1
[    0.940000] initcall fcntl_init+0x0/0x40 returned 0 after 0 usecs
[    0.940000] calling  proc_filesystems_init+0x0/0x38 @ 1
[    0.940000] initcall proc_filesystems_init+0x0/0x38 returned 0 after 0 usecs
[    0.940000] calling  dio_init+0x0/0x40 @ 1
[    0.950000] initcall dio_init+0x0/0x40 returned 0 after 9765 usecs
[    0.950000] calling  fsnotify_mark_init+0x0/0x40 @ 1
[    0.950000] initcall fsnotify_mark_init+0x0/0x40 returned 0 after 0 usecs
[    0.950000] calling  dnotify_init+0x0/0x80 @ 1
[    0.950000] initcall dnotify_init+0x0/0x80 returned 0 after 0 usecs
[    0.950000] calling  inotify_user_setup+0x0/0x78 @ 1
[    0.950000] initcall inotify_user_setup+0x0/0x78 returned 0 after 0 usecs
[    0.950000] calling  proc_locks_init+0x0/0x38 @ 1
[    0.950000] initcall proc_locks_init+0x0/0x38 returned 0 after 0 usecs
[    0.950000] calling  init_mbcache+0x0/0x18 @ 1
[    0.950000] initcall init_mbcache+0x0/0x18 returned 0 after 0 usecs
[    0.950000] calling  proc_cmdline_init+0x0/0x38 @ 1
[    0.950000] initcall proc_cmdline_init+0x0/0x38 returned 0 after 0 usecs
[    0.950000] calling  proc_consoles_init+0x0/0x38 @ 1
[    0.950000] initcall proc_consoles_init+0x0/0x38 returned 0 after 0 usecs
[    0.950000] calling  proc_cpuinfo_init+0x0/0x38 @ 1
[    0.950000] initcall proc_cpuinfo_init+0x0/0x38 returned 0 after 0 usecs
[    0.950000] calling  proc_devices_init+0x0/0x38 @ 1
[    0.950000] initcall proc_devices_init+0x0/0x38 returned 0 after 0 usecs
[    0.950000] calling  proc_interrupts_init+0x0/0x38 @ 1
[    0.960000] initcall proc_interrupts_init+0x0/0x38 returned 0 after
9765 usecs
[    0.960000] calling  proc_loadavg_init+0x0/0x38 @ 1
[    0.960000] initcall proc_loadavg_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_meminfo_init+0x0/0x38 @ 1
[    0.960000] initcall proc_meminfo_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_stat_init+0x0/0x38 @ 1
[    0.960000] initcall proc_stat_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_uptime_init+0x0/0x38 @ 1
[    0.960000] initcall proc_uptime_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_version_init+0x0/0x38 @ 1
[    0.960000] initcall proc_version_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_softirqs_init+0x0/0x38 @ 1
[    0.960000] initcall proc_softirqs_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_kmsg_init+0x0/0x38 @ 1
[    0.960000] initcall proc_kmsg_init+0x0/0x38 returned 0 after 0 usecs
[    0.960000] calling  proc_page_init+0x0/0x58 @ 1
[    0.960000] initcall proc_page_init+0x0/0x58 returned 0 after 0 usecs
[    0.960000] calling  init_devpts_fs+0x0/0x68 @ 1
[    0.960000] initcall init_devpts_fs+0x0/0x68 returned 0 after 0 usecs
[    0.960000] calling  init_ext3_fs+0x0/0x8c @ 1
[    0.970000] initcall init_ext3_fs+0x0/0x8c returned 0 after 9765 usecs
[    0.970000] calling  journal_init+0x0/0xb4 @ 1
[    0.990000] initcall journal_init+0x0/0xb4 returned 0 after 19531 usecs
[    0.990000] calling  init_ramfs_fs+0x0/0xc @ 1
[    0.990000] initcall init_ramfs_fs+0x0/0xc returned 0 after 0 usecs
[    0.990000] calling  init_jffs2_fs+0x0/0xd8 @ 1
[    0.990000] jffs2: version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
[    1.000000] initcall init_jffs2_fs+0x0/0xd8 returned 0 after 9765 usecs
[    1.000000] calling  ipc_init+0x0/0x24 @ 1
[    1.000000] msgmni has been set to 47
[    1.000000] initcall ipc_init+0x0/0x24 returned 0 after 0 usecs
[    1.000000] calling  ipc_sysctl_init+0x0/0x18 @ 1
[    1.000000] initcall ipc_sysctl_init+0x0/0x18 returned 0 after 0 usecs
[    1.000000] calling  key_proc_init+0x0/0x48 @ 1
[    1.000000] initcall key_proc_init+0x0/0x48 returned 0 after 0 usecs
[    1.000000] calling  crypto_algapi_init+0x0/0x10 @ 1
[    1.000000] initcall crypto_algapi_init+0x0/0x10 returned 0 after 0 usecs
[    1.000000] calling  aes_init+0x0/0xc @ 1
[    1.010000] initcall aes_init+0x0/0xc returned 0 after 9765 usecs
[    1.010000] calling  krng_mod_init+0x0/0xc @ 1
[    1.010000] initcall krng_mod_init+0x0/0xc returned 0 after 0 usecs
[    1.010000] calling  prng_mod_init+0x0/0x10 @ 1
[    1.010000] initcall prng_mod_init+0x0/0x10 returned 0 after 0 usecs
[    1.010000] calling  proc_genhd_init+0x0/0x58 @ 1
[    1.010000] initcall proc_genhd_init+0x0/0x58 returned 0 after 0 usecs
[    1.010000] calling  noop_init+0x0/0xc @ 1
[    1.010000] io scheduler noop registered
[    1.010000] initcall noop_init+0x0/0xc returned 0 after 0 usecs
[    1.010000] calling  cfq_init+0x0/0x94 @ 1
[    1.010000] io scheduler cfq registered (default)
[    1.010000] initcall cfq_init+0x0/0x94 returned 0 after 0 usecs
[    1.010000] calling  pty_init+0x0/0x230 @ 1
[    1.020000] initcall pty_init+0x0/0x230 returned 0 after 9765 usecs
[    1.020000] calling  sysrq_init+0x0/0x48 @ 1
[    1.020000] initcall sysrq_init+0x0/0x48 returned 0 after 0 usecs
[    1.020000] calling  serial8250_init+0x0/0x158 @ 1
[    1.020000] Serial: 8250/16550 driver, 1 ports, IRQ sharing enabled
[    1.030000] initcall serial8250_init+0x0/0x158 returned 0 after 9765 usecs
[    1.040000] calling  of_platform_serial_driver_init+0x0/0xc @ 1
[    1.060000] 98200000.uart: ttyS0 at MMIO 0x98200000 (irq = 31) is a 16550A
[    2.960000] console [ttyS0] enabled
[    2.970000] initcall of_platform_serial_driver_init+0x0/0xc
returned 0 after 1884765 usecs
[    2.980000] calling  mxser_module_init+0x0/0x49c @ 1
[    2.990000] MOXA Smartio/Industio family driver version 2.0.5
[    3.000000] mxser: found MOXA UC-7112-LX board (CAP=0x0)
[    3.000000] mxser: mxser_initbrd success IRQ=31 max baud=921600 bps
[    3.020000] initcall mxser_module_init+0x0/0x49c returned 0 after 29296 usecs
[    3.030000] calling  rand_initialize+0x0/0x2c @ 1
[    3.040000] initcall rand_initialize+0x0/0x2c returned 0 after 0 usecs
[    3.040000] calling  topology_sysfs_init+0x0/0x20 @ 1
[    3.050000] initcall topology_sysfs_init+0x0/0x20 returned 0 after 0 usecs
[    3.060000] calling  init_mtd+0x0/0xf8 @ 1
[    3.080000] initcall init_mtd+0x0/0xf8 returned 0 after 19531 usecs
[    3.090000] calling  ofpart_parser_init+0x0/0x38 @ 1
[    3.090000] initcall ofpart_parser_init+0x0/0x38 returned 0 after 0 usecs
[    3.100000] calling  init_mtdblock+0x0/0xc @ 1
[    3.110000] initcall init_mtdblock+0x0/0xc returned 0 after 0 usecs
[    3.110000] calling  cfi_probe_init+0x0/0x18 @ 1
[    3.120000] initcall cfi_probe_init+0x0/0x18 returned 0 after 0 usecs
[    3.130000] calling  physmap_init+0x0/0xc @ 1
[    3.130000] initcall physmap_init+0x0/0xc returned 0 after 0 usecs
[    3.140000] calling  of_flash_driver_init+0x0/0xc @ 1
[    3.170000] 80000000.flash: Found 1 x16 devices at 0x0 in 16-bit
bank. Manufacturer ID 0x000089 Chip ID 0x000018
[    3.180000] Intel/Sharp Extended Query Table at 0x0031
[    3.190000] Intel/Sharp Extended Query Table at 0x0031
[    3.200000] Using buffer write method
[    3.200000] cfi_cmdset_0001: Erase suspend on write enabled
[    3.210000] erase region 0: offset=0x0,size=0x20000,blocks=128
[    3.210000] 4 ofpart partitions found on MTD device 80000000.flash
[    3.220000] Creating 4 MTD partitions on "80000000.flash":
[    3.220000] 0x000000000000-0x000000040000 : "bootloader"
[    3.270000] 0x000000040000-0x000000200000 : "linux kernel"
[    3.300000] 0x000000200000-0x000000a00000 : "root filesystem"
[    3.330000] 0x000000a00000-0x000001000000 : "user filesystem"
[    3.370000] initcall of_flash_driver_init+0x0/0xc returned 0 after
214843 usecs
[    3.380000] calling  net_olddevs_init+0x0/0x68 @ 1
[    3.380000] initcall net_olddevs_init+0x0/0x68 returned 0 after 0 usecs
[    3.390000] calling  moxart_mac_init+0x0/0xc @ 1
[    3.440000] moxart-ethernet 90900000.mac eth0: moxart_mac_probe:
IRQ=25 address=00:90:e8:1b:e2:a5
[    3.500000] moxart-ethernet 92000000.mac eth1: moxart_mac_probe:
IRQ=27 address=00:90:e8:1b:e2:a6
[    3.520000] initcall moxart_mac_init+0x0/0xc returned 0 after 126953 usecs
[    3.520000] calling  moxart_rtc_init+0x0/0xc @ 1
[    3.540000] moxart-rtc rtc.0: rtc core: registered rtc.0 as rtc0
[    3.550000] moxart-rtc rtc.0: finished moxart_rtc_probe
[    3.560000] initcall moxart_rtc_init+0x0/0xc returned 0 after 29296 usecs
[    3.570000] calling  moxart_wdt_init+0x0/0xc @ 1
[    3.580000] moxart-watchdog 98500000.watchdog: finished
moxart_wdt_probe base=c2920000
[    3.600000] initcall moxart_wdt_init+0x0/0xc returned 0 after 29296 usecs
[    3.600000] calling  mmc_blk_init+0x0/0x74 @ 1
[    3.610000] initcall mmc_blk_init+0x0/0x74 returned 0 after 0 usecs
[    3.620000] calling  moxart_init+0x0/0xc @ 1
[   24.650000] INFO: rcu_preempt detected stalls on CPUs/tasks: {}
(detected by 0, t=2102 jiffies, g=4294967164, c=4294967163, q=9)
[   24.650000] INFO: Stall ended before state dump start
[   87.700000] INFO: rcu_preempt detected stalls on CPUs/tasks: {}
(detected by 0, t=8407 jiffies, g=4294967164, c=4294967163, q=9)
[   87.700000] INFO: Stall ended before state dump start
[  150.750000] INFO: rcu_preempt detected stalls on CPUs/tasks: {}
(detected by 0, t=14712 jiffies, g=4294967164, c=4294967163, q=9)
[  150.750000] INFO: Stall ended before state dump start


From khilman at linaro.org  Thu May 16 10:02:35 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Thu, 16 May 2013 07:02:35 -0700
Subject: [GIT PULL] OMAP PM cleanups for v3.10
In-Reply-To: <20130423175934.GA6728@quad.lixom.net> (Olof Johansson's message
 of "Tue, 23 Apr 2013 10:59:34 -0700")
References: <87ehej1ena.fsf@linaro.org> <20130410181452.GG10155@atomide.com>
 <20130423175934.GA6728@quad.lixom.net>
Message-ID: <87ppwrt43o.fsf@linaro.org>

Olof Johansson <olof at lixom.net> writes:

> On Wed, Apr 10, 2013 at 11:14:52AM -0700, Tony Lindgren wrote:
>> Hi,
>> 
>> Added Olof to cc, I suggest Olof pull this directly as we're starting
>> to run out of time.
>
> Hi,
>
> I'm terribly sorry for dropping this one on the floor, in spite of repeated
> pings from Tony. :(
>
> If it wasn't for the fact that we're pushing back on some of the other
> late submissions I'd be open to taking this, but to be fair it makes
> more sense to merge it right after -rc1. The changes don't look like
> they're truly critical for 3.10, and you should still be able to use
> this as a base for your 3.11 changes, so hopefully this doesn't cause
> too much trouble.
>
> So, please resend right after the merge window closes.

Pull request below.  It is unchanged and merges cleanly with v3.10-rc1.

Kevin

The following changes since commit c309f7f46167e85d1aae2fd31f23e7d2b5cdfbe0:

  Merge branch 'for_3.10/omap_generic_cleanup_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux into omap-for-v3.10/cleanup-v2 (2013-03-28 14:45:31 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git tags/omap-pm-v3.10/cleanup/pm

for you to fetch changes up to 705814b5ea6ff69d4da8ad581c3da5d26d1eae83:

  ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5 (2013-04-09 10:53:06 -0700)

----------------------------------------------------------------
OMAP PM cleanups for v3.10

----------------------------------------------------------------
Santosh Shilimkar (4):
      ARM: OMAP4: PM: Avoid expensive cpu_suspend() path for all CPU power states except off
      ARM: OMAP4+: PM: Consolidate MPU subsystem PM code for re-use
      ARM: OMAP4+: Make secondary_startup function name more consistent
      ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5

 arch/arm/mach-omap2/common.h              |  4 +-
 arch/arm/mach-omap2/omap-headsmp.S        |  8 ++--
 arch/arm/mach-omap2/omap-mpuss-lowpower.c | 69 +++++++++++++++++++++++++------
 arch/arm/mach-omap2/omap-smp.c            |  6 +--
 arch/arm/mach-omap2/pm44xx.c              | 58 +++++++++++++++++++++-----
 5 files changed, 113 insertions(+), 32 deletions(-)


From rpimentel.silva at gmail.com  Thu May 16 10:02:54 2013
From: rpimentel.silva at gmail.com (Rogerio Pimentel)
Date: Thu, 16 May 2013 11:02:54 -0300
Subject: parallel-display driver for i.MX53
Message-ID: <CAOkaPuX7RjwrMiZUCGwXTovgsFf=onRkrGa2U+qUv-tU3t4WWg@mail.gmail.com>

Hi,

I'm trying to add the parallel display on i.MX53QSB but it's not
working on current linux next. It was working prior to 3.10-rc1.

Does anybody know about any significant change that made this driver
break? Or maybe something else I need to do on imx53-qsb.dtb?

Thanks,
Rogerio


From tglx at linutronix.de  Thu May 16 10:04:56 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Thu, 16 May 2013 16:04:56 +0200 (CEST)
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
In-Reply-To: <1368684924-1560-1-git-send-email-b35083@freescale.com>
References: <1368684924-1560-1-git-send-email-b35083@freescale.com>
Message-ID: <alpine.LFD.2.02.1305161214570.1388@ionos>

On Thu, 16 May 2013, Jingchang Lu wrote:
> +/*
> + * 8 timers: pit0 - pit7,
> + * Each takes 0x10 Bytes register sapce
> + */
> +#define PITMCR		0x00
> +#define PIT0_OFFSET	0x100
> +#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
> +#define PITLDVAL	0x00
> +#define PITCVAL		0x04
> +#define PITTCTRL	0x08
> +#define PITTFLG		0x0c
> +
> +#define PITTCTRL_TEN		(0x1 << 0)
> +#define PITTCTRL_TIE		(0x1 << 1)
> +#define	PITCTRL_CHN		(0x1 << 2)
> +
> +#define PITTFLG_TIF		0x1
> +
> +static struct clock_event_device clockevent_pit;
> +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;

What the heck is this? The clock event device itself tracks the
mode. So why do you need a separate status variable?

> +
> +static void __iomem *clksrc_base;
> +static void __iomem *clkevt_base;
> +static void __iomem *sched_clock_reg;
> +static unsigned long pit_cycle_per_jiffy;
> +
> +static inline void pit_timer_enable(void)
> +{
> +	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_timer_disable(void)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_disable(void)

Unused function

> +{
> +	unsigned long val;
> +
> +	val = __raw_readl(clkevt_base + PITTCTRL);
> +	val &= ~PITTCTRL_TIE;
> +	__raw_writel(val, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_enable(void)

Ditto

> +{
> +	unsigned long val;
> +
> +	val = __raw_readl(clkevt_base + PITTCTRL);
> +	val |= PITTCTRL_TIE;
> +	__raw_writel(val, clkevt_base + PITTCTRL);
> +}
> +
> +static void pit_irq_acknowledge(void)

inline

> +{
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +}
> +
> +static unsigned int pit_read_sched_clock(void)
> +{
> +	return __raw_readl(sched_clock_reg);
> +}
> +
> +
> +static int __init pit_clocksource_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	sched_clock_reg = clksrc_base + PITCVAL;
> +
> +	setup_sched_clock(pit_read_sched_clock, 32, c);
> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "mvf600-pit", c,
> +			300, 32, clocksource_mmio_readl_down);
> +}
> +
> +/* set clock event */

This is the most useless comment ever.

> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_irq_acknowledge();
> +	pit_timer_enable();

It would be much more interesting to comment, why you need to
acknowlegde the timer here.

> +	return 0;
> +}
> +
> +static void pit_set_mode(enum clock_event_mode mode,
> +				struct clock_event_device *evt)
> +{
> +	unsigned long flags;
> +
> +	local_irq_save(flags);

All clockevent functions are called with interrupts disabled.

> +	pit_timer_disable();
> +	pit_irq_acknowledge();
> +
> +	/* Remember timer mode */
> +	clockevent_mode = mode;

Groan.

> +	local_irq_restore(flags);
> +
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +
> +		__raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
> +		pit_timer_enable();
> +
> +		break;
> +	case CLOCK_EVT_MODE_ONESHOT:

Whats so special that this needs a separate break?

> +		break;
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_RESUME:
> +
> +		break;
> +	default:
> +		WARN(1, "%s: unhandled event mode %d\n", __func__, mode);

What the heck? Either you have a default catching everything you do
not handle or you remove the default and let the compiler warn you
when the CLOCK_EVT_MODE enum got a new value added.

> +		break;
> +	}
> +}
> +
> +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = &clockevent_pit;
> +
> +	pit_irq_acknowledge();
> +
> +	if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT)
> +		pit_timer_disable();

So in oneshot mode you do:

     pit_irq_ack()
     pit_timer_disable()
     ....
	set_next_event()
  	  pit_timer_disable()
	  write_new_value()
	  pit_irq_ack()
	  pit_timer_enable()

Not really the most efficient way in the interrupt fast path, right?

> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction pit_timer_irq = {
> +	.name		= "MVF600 pit timer",
> +	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,

Please look up what IRQF_DISABLED does and why you shouldn't use it.

> +	.handler	= pit_timer_interrupt,
> +};
> +
> +static struct clock_event_device clockevent_pit = {
> +	.name		= "MVF600 pit timer",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= pit_set_mode,
> +	.set_next_event	= pit_set_next_event,
> +	.rating		= 300,
> +};
> +
> +static int __init pit_clockevent_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	clockevent_pit.cpumask = cpumask_of(0);
> +	clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00);

0x100 and 0xffffff00 ?? Random numbers pulled out of what?

> +	return 0;
> +}
> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	int irq;
> +
> +	if (!np) {

So how gets that called without a valid node pointer?

> +		pr_err("Failed to find MVF600 pit DT node\n");
> +		BUG();
> +	}
> +
> +	timer_base = of_iomap(np, 0);
> +	WARN_ON(!timer_base);

Great, timer_base is NULL and you just emit a warning and then
proceed? So instead of either bailing out or crashing the machine
right away you let it randomly die with the first access.

> +
> +	/* choose PIT2 as clocksource, PIT3 as clockevent dev */
> +	clksrc_base = timer_base + PITn_OFFSET(2);
> +	clkevt_base = timer_base + PITn_OFFSET(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +
> +	pit_clk = of_clk_get(np, 0);
> +	if (IS_ERR(pit_clk)) {
> +		pr_err("Vybrid MVF600 pit timer: unable to get clk\n");

Can you please make your pr_*() format consistent?

> +		pr_err("Failed to find MVF600 pit DT node\n");
> +		pr_err("Vybrid MVF600 pit timer: unable to get clk\n");

> +		return;
> +	}
> +
> +	clk_prepare_enable(pit_clk);

And while you're worried about the core code sending you random crap,
you assume that this call always succeeds.

> +	pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
> +
> +	__raw_writel(0x0, timer_base + PITMCR);
> +
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +	__raw_writel(0xffffffff, clkevt_base + PITLDVAL);

What's the point of this? 

> +	__raw_writel(0, clksrc_base + PITTCTRL);
> +	__raw_writel(0xffffffff, clksrc_base + PITLDVAL);

And of this? Why isn't the setup done in the relevant init functions?

> +	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
> +
> +	pit_clocksource_init(pit_clk);
> +
> +	setup_irq(irq, &pit_timer_irq);
> +
> +	pit_clockevent_init(pit_clk);
> +}

Thanks,

	tglx


From fabio.estevam at freescale.com  Thu May 16 10:13:59 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Thu, 16 May 2013 11:13:59 -0300
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <1368713639-21485-2-git-send-email-fabio.estevam@freescale.com>

Commit e5aba13 (i2c: i2c-mxs: move to use generic DMA helper) changed
i2c-mxs.txt and drivers/i2c/busses/i2c-mxs.c to only use one I2C interrupt.

Adapt the dtsi bindings with such change.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx28.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 33389b8..2e1ba4b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -878,7 +878,7 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx28-i2c";
 				reg = <0x80058000 0x2000>;
-				interrupts = <111 68>;
+				interrupts = <111>;
 				clock-frequency = <100000>;
 				dmas = <&dma_apbx 6>;
 				dma-names = "rx-tx";
@@ -891,7 +891,7 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx28-i2c";
 				reg = <0x8005a000 0x2000>;
-				interrupts = <110 69>;
+				interrupts = <110>;
 				clock-frequency = <100000>;
 				dmas = <&dma_apbx 7>;
 				dma-names = "rx-tx";
-- 
1.8.1.2




From fabio.estevam at freescale.com  Thu May 16 10:13:58 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Thu, 16 May 2013 11:13:58 -0300
Subject: [PATCH 1/2] ARM: dts: imx: Remove custom dma-channel bindings
Message-ID: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>

Commit f30fb03 (ARM: dts: add generic DMA device tree binding for mxs-dma) added
the generic DMA dt bindings, but missed to remove the old ones.

Remove the the old dma bindings.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx23.dtsi   | 3 ---
 arch/arm/boot/dts/imx28.dtsi   | 5 -----
 arch/arm/boot/dts/imx6qdl.dtsi | 1 -
 3 files changed, 9 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0..be93494 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -78,7 +78,6 @@
 				clock-names = "gpmi_io";
 				dmas = <&dma_apbh 4>;
 				dma-names = "rx-tx";
-				fsl,gpmi-dma-channel = <4>;
 				status = "disabled";
 			};
 
@@ -88,7 +87,6 @@
 				clocks = <&clks 33>;
 				dmas = <&dma_apbh 1>;
 				dma-names = "rx-tx";
-				fsl,ssp-dma-channel = <1>;
 				status = "disabled";
 			};
 
@@ -366,7 +364,6 @@
 				clocks = <&clks 33>;
 				dmas = <&dma_apbh 2>;
 				dma-names = "rx-tx";
-				fsl,ssp-dma-channel = <2>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e401dee..33389b8 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -100,7 +100,6 @@
 				clock-names = "gpmi_io";
 				dmas = <&dma_apbh 4>;
 				dma-names = "rx-tx";
-				fsl,gpmi-dma-channel = <4>;
 				status = "disabled";
 			};
 
@@ -112,7 +111,6 @@
 				clocks = <&clks 46>;
 				dmas = <&dma_apbh 0>;
 				dma-names = "rx-tx";
-				fsl,ssp-dma-channel = <0>;
 				status = "disabled";
 			};
 
@@ -124,7 +122,6 @@
 				clocks = <&clks 47>;
 				dmas = <&dma_apbh 1>;
 				dma-names = "rx-tx";
-				fsl,ssp-dma-channel = <1>;
 				status = "disabled";
 			};
 
@@ -136,7 +133,6 @@
 				clocks = <&clks 48>;
 				dmas = <&dma_apbh 2>;
 				dma-names = "rx-tx";
-				fsl,ssp-dma-channel = <2>;
 				status = "disabled";
 			};
 
@@ -148,7 +144,6 @@
 				clocks = <&clks 49>;
 				dmas = <&dma_apbh 3>;
 				dma-names = "rx-tx";
-				fsl,ssp-dma-channel = <3>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461c..5cc2855 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -89,7 +89,6 @@
 				      "gpmi_bch_apb", "per1_bch";
 			dmas = <&dma_apbh 0>;
 			dma-names = "rx-tx";
-			fsl,gpmi-dma-channel = <0>;
 			status = "disabled";
 		};
 
-- 
1.8.1.2




From sergei.shtylyov at cogentembedded.com  Thu May 16 10:25:13 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 18:25:13 +0400
Subject: [PATCH v3 1/1] ARM: shmobile: r8a7778: add I2C support
In-Reply-To: <87txm3wwzh.wl%kuninori.morimoto.gx@renesas.com>
References: <201304232012.57619.sergei.shtylyov@cogentembedded.com>
 <201304232015.59697.sergei.shtylyov@cogentembedded.com>
 <87txm3wwzh.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <5194EC49.9000508@cogentembedded.com>

Hello.

On 16-05-2013 5:10, Kuninori Morimoto wrote:

> Basically, this patch is good for me.
> But I have some comment.

> Sergei Shtylyov wrote:

>> From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

>> Add I2C clocks and platform devices for R8A7778 SoC.
>> Don't forget to also add the peripheral clock which the I2C driver uses.

>> Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
>> [Sergei: changed the registration function to platform_device_register_simple(),
>> annotated I2C resources as '__initdata', regrouped MSTPxxx *enum* members, added
>> the copyright.]
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> (snip)
>> -	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
>> +	MSTP030, MSTP029,
>> +	MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
>
> It should be

> 	MSTP30,
> 	MSPT029, MSPT028, MSPT027...

    This will cause a warning from checkpatch.pl for the violation of 
80-column line limit, I think.

>> +/* I2C */
>> +static struct resource i2c0_resources[] __initdata = {
>> +	DEFINE_RES_MEM(0xffc70000, 0x1000),
>> +	DEFINE_RES_IRQ(gic_iid(0x63)),
>> +};
>> +
>> +static struct resource i2c1_resources[] __initdata = {
>> +	DEFINE_RES_MEM(0xffc71000, 0x1000),
>> +	DEFINE_RES_IRQ(gic_iid(0x6e)),
>> +};
>> +
>> +static struct resource i2c2_resources[] __initdata = {
>> +	DEFINE_RES_MEM(0xffc72000, 0x1000),
>> +	DEFINE_RES_IRQ(gic_iid(0x6c)),
>> +};
>> +
>> +static struct resource i2c3_resources[] __initdata = {
>> +	DEFINE_RES_MEM(0xffc73000, 0x1000),
>> +	DEFINE_RES_IRQ(gic_iid(0x6d)),
>> +};
>> +
>> +#define r8a7778_register_i2c(idx)			\
>> +	platform_device_register_simple(		\
>> +		"i2c-rcar", idx,			\
>> +		i2c##idx##_resources,			\
>> +		ARRAY_SIZE(i2c##idx##_resources))
>> +
>>   /* USB PHY */
>>   static struct resource usb_phy_resources[] __initdata = {
>>   	DEFINE_RES_MEM(0xffe70800, 0x100),
>> @@ -294,6 +321,11 @@ void __init r8a7778_add_standard_devices
>>
>>   	r8a7778_register_tmu(0);
>>   	r8a7778_register_tmu(1);
>> +
>> +	r8a7778_register_i2c(0);
>> +	r8a7778_register_i2c(1);
>> +	r8a7778_register_i2c(2);
>> +	r8a7778_register_i2c(3);
>>   }
>
> i2c1 - i2c3 pins are pin-multi.

    Ah, you mean there should be I2C related entries in the pinmux table
in the BOCK-W code?

> I guess using r8a7778_add_i2c_devices(idx) from board code is better method

    Why? Not at all, I think, since we don't have the platform data.

> Best regards
> ---
> Kuninori Morimoto

WBR, Sergei




From sergei.shtylyov at cogentembedded.com  Thu May 16 10:30:13 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 16 May 2013 18:30:13 +0400
Subject: [PATCH v3 1/1] ARM: shmobile: r8a7778: add I2C support
In-Reply-To: <5194EC49.9000508@cogentembedded.com>
References: <201304232012.57619.sergei.shtylyov@cogentembedded.com>
 <201304232015.59697.sergei.shtylyov@cogentembedded.com>
 <87txm3wwzh.wl%kuninori.morimoto.gx@renesas.com>
 <5194EC49.9000508@cogentembedded.com>
Message-ID: <5194ED75.5000908@cogentembedded.com>

On 16-05-2013 18:25, I wrote:

>> Basically, this patch is good for me.
>> But I have some comment.

>>> From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

>>> Add I2C clocks and platform devices for R8A7778 SoC.
>>> Don't forget to also add the peripheral clock which the I2C driver uses.

>>> Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
>>> [Sergei: changed the registration function to
>>> platform_device_register_simple(),
>>> annotated I2C resources as '__initdata', regrouped MSTPxxx *enum*
>>> members, added
>>> the copyright.]
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
>> (snip)
[...]

>>> +/* I2C */
>>> +static struct resource i2c0_resources[] __initdata = {
>>> +    DEFINE_RES_MEM(0xffc70000, 0x1000),
>>> +    DEFINE_RES_IRQ(gic_iid(0x63)),
>>> +};
>>> +
>>> +static struct resource i2c1_resources[] __initdata = {
>>> +    DEFINE_RES_MEM(0xffc71000, 0x1000),
>>> +    DEFINE_RES_IRQ(gic_iid(0x6e)),
>>> +};
>>> +
>>> +static struct resource i2c2_resources[] __initdata = {
>>> +    DEFINE_RES_MEM(0xffc72000, 0x1000),
>>> +    DEFINE_RES_IRQ(gic_iid(0x6c)),
>>> +};
>>> +
>>> +static struct resource i2c3_resources[] __initdata = {
>>> +    DEFINE_RES_MEM(0xffc73000, 0x1000),
>>> +    DEFINE_RES_IRQ(gic_iid(0x6d)),
>>> +};
>>> +
>>> +#define r8a7778_register_i2c(idx)            \
>>> +    platform_device_register_simple(        \
>>> +        "i2c-rcar", idx,            \
>>> +        i2c##idx##_resources,            \
>>> +        ARRAY_SIZE(i2c##idx##_resources))
>>> +
>>>   /* USB PHY */
>>>   static struct resource usb_phy_resources[] __initdata = {
>>>       DEFINE_RES_MEM(0xffe70800, 0x100),
>>> @@ -294,6 +321,11 @@ void __init r8a7778_add_standard_devices
>>>
>>>       r8a7778_register_tmu(0);
>>>       r8a7778_register_tmu(1);
>>> +
>>> +    r8a7778_register_i2c(0);
>>> +    r8a7778_register_i2c(1);
>>> +    r8a7778_register_i2c(2);
>>> +    r8a7778_register_i2c(3);
>>>   }

>> i2c1 - i2c3 pins are pin-multi.

>     Ah, you mean there should be I2C related entries in the pinmux table
> in the BOCK-W code?

    On the other hand, we only use I2C0 on BOCK-W which as you say is 
not pin-multiplexed.

>> I guess using r8a7778_add_i2c_devices(idx) from board code is better
>> method

>     Why? Not at all, I think, since we don't have the platform data.

    Hm, you may be right here...

>> Best regards
>> ---
>> Kuninori Morimoto

WBR, Sergei




From linux at arm.linux.org.uk  Thu May 16 10:36:38 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 May 2013 15:36:38 +0100
Subject: [PATCH] ARM: remove the .vm_mm value from gate_vma.
In-Reply-To: <1368702394-1737-1-git-send-email-steve.capper@linaro.org>
References: <1368702394-1737-1-git-send-email-steve.capper@linaro.org>
Message-ID: <20130516143638.GR18614@n2100.arm.linux.org.uk>

On Thu, May 16, 2013 at 12:06:34PM +0100, Steve Capper wrote:
> If one reads /proc/$PID/smaps, the mmap_sem belonging to the
> address space of the task being examined is locked for reading.
> All the pages of the vmas belonging to the task's address space
> are then walked with this lock held.
> 
> If a gate_vma is present in the architecture, it too is examined
> by the fs/proc/task_mmu.c code. As gate_vma doesn't belong to the
> address space of the task though, its pages are not walked.
> 
> A recent cleanup (commit f6604efe) of the gate_vma initialisation
> code set the vm_mm value to &init_mm. Unfortunately a non-NULL
> vm_mm value in the gate_vma will cause the task_mmu code to attempt
> to walk the pages of the gate_vma (with no mmap-sem lock held). If
> one enables Transparent Huge Page support and vm debugging, this
> will then cause OOPses as pmd_trans_huge_lock is called without
> mmap_sem being locked.
> 
> This patch removes the .vm_mm value from gate_vma, restoring the
> original behaviour of the task_mmu code.

This looks fine - x86 also sets .vm_mm to NULL here.  So please put
it in my patch system.  Does this need to be applied to stable
kernels as well?  If so, please mark it with Cc: <stable at vger.kernel.org>
(but do not send it to that address).  Also, it'd be worth checking
which stable kernels it needs to be applied to.

Thanks.


From philip at balister.org  Thu May 16 10:44:16 2013
From: philip at balister.org (Philip Balister)
Date: Thu, 16 May 2013 10:44:16 -0400
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <51946082.1000606@codeaurora.org>
References: <20130512143344.GC3200@sirena.org.uk>
 <9e55c552-ce34-4663-9a57-bf2c626d7d58@TX2EHSMHS008.ehs.local>
 <20130513052135.GD6836@sirena.org.uk>
 <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum> <51927DEB.7090001@balister.org>
 <20130515044604.GA24524@sirena.org.uk> <51946082.1000606@codeaurora.org>
Message-ID: <5194F0C0.9020609@balister.org>

On 05/16/2013 12:28 AM, Saravana Kannan wrote:
> On 05/14/2013 09:46 PM, Mark Brown wrote:
>> On Tue, May 14, 2013 at 02:09:47PM -0400, Philip Balister wrote:
>>
>>> First of all, the driver that loads the bitstream into the fpga
>>> fabric does not know ANYTHING about what the bitstream does. So it
>>> cannot do any setup based on the contents of the file that is
>>> loaded. (And this can also be loaded during the SoC bootup,
>>> bypassing this driver completely)
>>
>> This is a problem that is going to need to be fixed - there will be some
>> things going on the FPGAs that do need drivers and so there needs to be
>> some way to instantiate a driver for a FPGA image.  Things like adding
>> extra DT blobs along with the FPGA image have been talked about
>>
>>> Second, there are four clocks that feed the FPGA fabric. We will
>>> want to set these clocks from user space somehow. It is perfectly
>>> valid to use a uio driver to interface with logic in the fpga. If we
>>> take the approach of using such general purpose techniques to
>>> interface with fpga logic, we must have ways for the user to control
>>> the fpga clocks.
>>
>> Right, and if the specific device is being controlled by UIO then having
>> UIO create some clocks makes sense but then that should be integrated
>> into the UIO instantiation rather than done as a separate thing.
> 
> Agreed. I was about to reply with exactly the same point. I haven't done
> any UIO coding, but that device file will eventually have to be opened.
> Turn on the clocks in the open and turn them off at close.
> 
> Rate to request can be a DT property.

But you are assuming each device implemented in the fpga uses one clock.
This assumption is clearly not valid since devices will ahve to share
clocks.

Philip


From arnd at arndb.de  Thu May 16 10:52:55 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 May 2013 16:52:55 +0200
Subject: [PATCH] ARM: mach-moxart: platform port for MOXA ART SoC
In-Reply-To: <CACmBeS3JZ8bm6jJbmrKTfmZqshezN6QKdmyPCKdQ2HUwzY7ggA@mail.gmail.com>
References: <CACmBeS1NLFUYHBOVL28aCCzRrgXYGPZF9t3qj6AdcgaMkrPGoQ@mail.gmail.com>
 <201305151516.52389.arnd@arndb.de>
 <CACmBeS3JZ8bm6jJbmrKTfmZqshezN6QKdmyPCKdQ2HUwzY7ggA@mail.gmail.com>
Message-ID: <4406410.DRdDEViWVK@wuerfel>

On Thursday 16 May 2013 15:37:16 Jonas Jensen wrote:
> On 15 May 2013 15:16, Arnd Bergmann <arnd at arndb.de> wrote:
> > The part that I don't understand at all is the "timer0" part. Is that a string
> > from the data sheet?
> 
> I have next to no data sheets or documentation on the SoC itself. What
> I know is from looking at old sources, which suggest there are more
> than one timer (the rest were never implemented).
> 
> It only needs one for timer_tick? Does it make sense to just call it "timer"?

Yes, I think just "moxa,moxart-timer" is fine. Chances are that if you have
more of them, they are actually compatible with one another. If they are not
and you need more than one, you can always pick a different name
if you need another one.

> > Can you provide some more detail why what PMU registers are used here? Is that
> > a "Performance Measurement Unit", "Power Management Unit" or something else?
> > Are you sure that those registers are only ever needed for GPIO?
> 
> It's "Power Management Unit". The MMC driver uses it to read system
> clock and write it to clock control, but I suspect it can be removed.
> It's code under #ifdef MSD_SUPPORT_GET_CLOCK but I think the else is
> perfectly acceptable.
> GPIO uses it only to enable or disable pins.

It sounds like this is used for what should be separate drivers/clk and
drivers/pinctrl drivers:

A pinctrl driver is often the superset of a gpio driver and can control
more aspects of a pin than the gpio interface can.

The clk driver is supposed to give an abstraction of the clock tree
to be used with interfaces like clk_get() and clk_set_rate(). It
can probably be really simple in case of moxart. Is the mmc driver
the only one that needs access to clocks?

Are the pinctrl and clk registers in different parts of the PMU, or are
they intermixed? In the former case, you can just turn it into separate
devices that have their own distinct "reg" properties, in the second
case, the best solution is likely to mark the pmu 'compatible="syscon"'
and use the drivers/mfd/syscon.c driver to get a regmap that is used
by the clock and pinctrl drivers, respectively.

	Arnd


From catalin.marinas at arm.com  Thu May 16 09:52:34 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 May 2013 14:52:34 +0100
Subject: [RFC PATCH v2 06/11] ARM64: mm: Restore memblock limit when
 map_mem finished.
In-Reply-To: <1368006763-30774-7-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-7-git-send-email-steve.capper@linaro.org>
Message-ID: <20130516135233.GB18308@arm.com>

On Wed, May 08, 2013 at 10:52:38AM +0100, Steve Capper wrote:
> In paging_init the memblock limit is set to restrict any addresses
> returned by early_alloc to fit within the initial direct kernel
> mapping in swapper_pg_dir. This allows map_mem to allocate puds,
> pmds and ptes from the initial direct kernel mapping.
> 
> The limit stays low after paging_init() though, meaning any
> bootmem allocations will be from a restricted subset of memory.
> Gigabyte huge pages, for instance, are normally allocated from
> bootmem as their order (18) is too large for the default buddy
> allocator (MAX_ORDER = 11).
> 
> This patch restores the memblock limit when map_mem has finished,
> allowing gigabyte huge pages (and other objects) to be allocated
> from all of bootmem.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Thu May 16 10:59:27 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 May 2013 15:59:27 +0100
Subject: [RFC PATCH v2 10/11] ARM64: mm: Raise MAX_ORDER for 64KB pages
 and THP.
In-Reply-To: <1368006763-30774-11-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-11-git-send-email-steve.capper@linaro.org>
Message-ID: <20130516145927.GF18308@arm.com>

On Wed, May 08, 2013 at 10:52:42AM +0100, Steve Capper wrote:
> The buddy allocator has a default MAX_ORDER of 11, which is too
> low to allocate enough memory for 512MB Transparent HugePages if
> our base page size is 64KB.
> 
> This patch introduces MAX_ZONE_ORDER and sets it to 14 when 64KB
> pages are used in conjuction with THP, otherwise the default value
> of 11 is used.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From jason at lakedaemon.net  Thu May 16 11:06:16 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 11:06:16 -0400
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for
 PCIe clocks on Armada 370
In-Reply-To: <51949830.70306@gmail.com>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130515214154.12127.73539@quantum>
 <20130516094417.24b1ca0d@skate> <51949830.70306@gmail.com>
Message-ID: <20130516150616.GD6563@titan.lakedaemon.net>

Mike, Sebastian,

On Thu, May 16, 2013 at 10:26:24AM +0200, Sebastian Hesselbarth wrote:
> On 05/16/2013 09:44 AM, Thomas Petazzoni wrote:
> >Dear Mike Turquette,
> >
> >On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> >>Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> >>>The Armada 370 has two gatable clocks for each PCIe interface, and we
> >>>want both of them to be enabled. We therefore make one of the two
> >>>clocks a child of the other, as we did for the sataX and sataXlnk
> >>>clocks on Armada XP.
> >>
> >>Ack for patches #5 and #6.  Do you want me to take them?

Thanks for the Ack!

> >I don't know, I guess with your Ack, it would be easier to carry them
> >through the Marvell maintainers and then the arm-soc tree, so that we
> >can test arm-soc and have all the pieces needed in here.
> >
> >That said, Sebastian Hesselbarth has submitted a big rework of the
> >mvebu clock drivers, which would conflict with this patch, and
> >Sebastian's rework would most likely go through your tree. If that's
> >the case, I guess it would be better to let you take #5 and #6 in this
> >patch series.
> 
> I also requested to take the restructure patches through ARM tree. They
> are only touching files in drivers/clk/mvebu and by taking them through
> ARM, we can update PCIe clock patches easily. The dependency between
> Thomas' and my patches basically is that I renamed files that Thomas
> now commits to. (I switched clk/mvebu from per-function files to per-soc
> files).

I agree.  My heart jumped into my throat a little there :)  Mike, if
it's ok with you, I'd prefer to take these through arm-soc.  Any merge
conflicts should be minimal.  And at any rate, resolving the conflicts
are *much* easier to handle than having arm-soc depend on an outside
tree (then Linus has to take care in the order he merges them, no
rebasing for clk tree, dogs and cats living together, etc ;-) )

thx,

Jason.


From tony at atomide.com  Thu May 16 11:11:27 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 08:11:27 -0700
Subject: [PATCH] ARM: omap2: remove CONFIG_ARCH_OMAP2PLUS_TYPICAL
In-Reply-To: <1368710950-2306-1-git-send-email-robherring2@gmail.com>
References: <1368710950-2306-1-git-send-email-robherring2@gmail.com>
Message-ID: <20130516151126.GP5600@atomide.com>

* Rob Herring <robherring2 at gmail.com> [130516 06:34]:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> CONFIG_ARCH_OMAP2PLUS_TYPICAL is selecting user defined features, not h/w
> required options. This does not play well with multi-platform kernels and
> belongs in a defconfig.

Yes we can remove this. But let's update omap2plus_defconfig with these
options where needed. I can update this patch for that and queue it
if that works for you.

Regards,

Tony


> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: linux-omap at vger.kernel.org
> ---
>  arch/arm/mach-omap2/Kconfig | 17 -----------------
>  1 file changed, 17 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f49cd51..9d4b5f7 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -26,23 +26,6 @@ if ARCH_OMAP2PLUS
>  
>  menu "TI OMAP2/3/4 Specific Features"
>  
> -config ARCH_OMAP2PLUS_TYPICAL
> -	bool "Typical OMAP configuration"
> -	default y
> -	select AEABI
> -	select HIGHMEM
> -	select I2C
> -	select I2C_OMAP
> -	select MENELAUS if ARCH_OMAP2
> -	select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
> -	select PM_RUNTIME
> -	select REGULATOR
> -	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
> -	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
> -	select VFP
> -	help
> -	  Compile a kernel suitable for booting most boards
> -
>  config SOC_HAS_OMAP2_SDRC
>  	bool "OMAP2 SDRAM Controller support"
>  
> -- 
> 1.8.1.2
> 


From robherring2 at gmail.com  Thu May 16 11:19:49 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 May 2013 10:19:49 -0500
Subject: [PATCH] ARM: omap2: remove CONFIG_ARCH_OMAP2PLUS_TYPICAL
In-Reply-To: <20130516151126.GP5600@atomide.com>
References: <1368710950-2306-1-git-send-email-robherring2@gmail.com>
 <20130516151126.GP5600@atomide.com>
Message-ID: <CAL_JsqJgc39YO3-L=-kgJ=wmXhe-dAP5nHngaCLbxfheAEvduA@mail.gmail.com>

On Thu, May 16, 2013 at 10:11 AM, Tony Lindgren <tony at atomide.com> wrote:
> * Rob Herring <robherring2 at gmail.com> [130516 06:34]:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> CONFIG_ARCH_OMAP2PLUS_TYPICAL is selecting user defined features, not h/w
>> required options. This does not play well with multi-platform kernels and
>> belongs in a defconfig.
>
> Yes we can remove this. But let's update omap2plus_defconfig with these
> options where needed. I can update this patch for that and queue it
> if that works for you.
>

Yes, that's fine. You might also want to enable the h/w related
features to multi_v7_defconfig as well.

Rob


From maxime.ripard at free-electrons.com  Thu May 16 11:20:36 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 16 May 2013 17:20:36 +0200
Subject: [PATCH 0/4] ARM: Remove boilerplate debug_ll_io_init code
In-Reply-To: <201305160040.54399.arnd@arndb.de>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
 <201305160040.54399.arnd@arndb.de>
Message-ID: <5194F944.2040803@free-electrons.com>

Hi Arnd,

Le 16/05/2013 00:40, Arnd Bergmann a ?crit :
> On Monday 13 May 2013, Maxime Ripard wrote:
>> The recent introduction of debug_ll_io_init made possible to not rely
>> anymore on a custom map_io function but on debug_ll_io_init for the
>> early mapping and then on the various drivers to do the needed mappings for
>> the kernel to boot.
>>
>> Some architectures begin to use only this function as the map_io callback in
>> the machine description.
>>
>> In order to remove some boilerplate code, make the ARM mm code call
>> debug_ll_io_init by itself when no .map_io callback is defined.
>>
>> This has been tested on the sunxi platform.
> 
> Great stuff!
> 
> I didn't notice the addition of debug_ll_io_init, so this is a nice surprise
> for me.

Well, you can thank Rob for that, I wasn't involved in it in the first
place :)

> Acked-by: Arnd Bergmann <arnd at arndb.de>

Thanks,

How will we merge this? The first patch would be merged by Russel and
the 3 others by their respective maintainers?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From tony at atomide.com  Thu May 16 11:23:41 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 08:23:41 -0700
Subject: [PATCH] ARM: omap2: remove CONFIG_ARCH_OMAP2PLUS_TYPICAL
In-Reply-To: <CAL_JsqJgc39YO3-L=-kgJ=wmXhe-dAP5nHngaCLbxfheAEvduA@mail.gmail.com>
References: <1368710950-2306-1-git-send-email-robherring2@gmail.com>
 <20130516151126.GP5600@atomide.com>
 <CAL_JsqJgc39YO3-L=-kgJ=wmXhe-dAP5nHngaCLbxfheAEvduA@mail.gmail.com>
Message-ID: <20130516152338.GQ5600@atomide.com>

* Rob Herring <robherring2 at gmail.com> [130516 08:25]:
> On Thu, May 16, 2013 at 10:11 AM, Tony Lindgren <tony at atomide.com> wrote:
> > * Rob Herring <robherring2 at gmail.com> [130516 06:34]:
> >> From: Rob Herring <rob.herring at calxeda.com>
> >>
> >> CONFIG_ARCH_OMAP2PLUS_TYPICAL is selecting user defined features, not h/w
> >> required options. This does not play well with multi-platform kernels and
> >> belongs in a defconfig.
> >
> > Yes we can remove this. But let's update omap2plus_defconfig with these
> > options where needed. I can update this patch for that and queue it
> > if that works for you.
> >
> 
> Yes, that's fine. You might also want to enable the h/w related
> features to multi_v7_defconfig as well.

Yes will do. BTW, getting rid of CONFIG_ARCH_OMAP2PLUS_TYPICAL was the
reason I did not update multi_v7_defconfig yet.

I'll also update Arnd's randconfig fix patch and post it, then
will stick all three patches into one branch.

Regards,

Tony


From jason at lakedaemon.net  Thu May 16 11:28:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 11:28:27 -0400
Subject: [PATCH] ARM: dove: declare all device IDs for module loading
In-Reply-To: <20130516131233.30145f82@armhf>
References: <20130516131233.30145f82@armhf>
Message-ID: <20130516152827.GE6563@titan.lakedaemon.net>

Jean-Francois,

Thanks for the patch, but you may want to change the subject "clk:
si5351: ..."  Other than that,

On Thu, May 16, 2013 at 01:12:33PM +0200, Jean-Francois Moine wrote:
> When the si5351 driver is a kernel module, it is loaded into memory
> from its i2c device IDs, but not from its DT compatible properties.
> 
> This patch declares the i2c device IDs of all chip variants.
> 
> Signed-off-by: Jean-Francois Moine <moinejf at free.fr>
> --- 
>  drivers/clk/clk-si5351.c |    5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)

Acked-by: Jason Cooper <jason at lakedaemon.net>


From tony at atomide.com  Thu May 16 11:30:23 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 08:30:23 -0700
Subject: [GIT PULL] OMAP PM cleanups for v3.10
In-Reply-To: <87ppwrt43o.fsf@linaro.org>
References: <87ehej1ena.fsf@linaro.org> <20130410181452.GG10155@atomide.com>
 <20130423175934.GA6728@quad.lixom.net> <87ppwrt43o.fsf@linaro.org>
Message-ID: <20130516153023.GR5600@atomide.com>

* Kevin Hilman <khilman at linaro.org> [130516 07:08]:
> Olof Johansson <olof at lixom.net> writes:
> 
> > On Wed, Apr 10, 2013 at 11:14:52AM -0700, Tony Lindgren wrote:
> >> Hi,
> >> 
> >> Added Olof to cc, I suggest Olof pull this directly as we're starting
> >> to run out of time.
> >
> > Hi,
> >
> > I'm terribly sorry for dropping this one on the floor, in spite of repeated
> > pings from Tony. :(
> >
> > If it wasn't for the fact that we're pushing back on some of the other
> > late submissions I'd be open to taking this, but to be fair it makes
> > more sense to merge it right after -rc1. The changes don't look like
> > they're truly critical for 3.10, and you should still be able to use
> > this as a base for your 3.11 changes, so hopefully this doesn't cause
> > too much trouble.
> >
> > So, please resend right after the merge window closes.
> 
> Pull request below.  It is unchanged and merges cleanly with v3.10-rc1.

I've pulled this into omap-for-v3.11/pm. Olof, you can also pull Kevin's
branch now or later on along with other omap pull requests whichever you
prefer.

Regards,

Tony
 
> The following changes since commit c309f7f46167e85d1aae2fd31f23e7d2b5cdfbe0:
> 
>   Merge branch 'for_3.10/omap_generic_cleanup_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux into omap-for-v3.10/cleanup-v2 (2013-03-28 14:45:31 -0700)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git tags/omap-pm-v3.10/cleanup/pm
> 
> for you to fetch changes up to 705814b5ea6ff69d4da8ad581c3da5d26d1eae83:
> 
>   ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5 (2013-04-09 10:53:06 -0700)
> 
> ----------------------------------------------------------------
> OMAP PM cleanups for v3.10
> 
> ----------------------------------------------------------------
> Santosh Shilimkar (4):
>       ARM: OMAP4: PM: Avoid expensive cpu_suspend() path for all CPU power states except off
>       ARM: OMAP4+: PM: Consolidate MPU subsystem PM code for re-use
>       ARM: OMAP4+: Make secondary_startup function name more consistent
>       ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5
> 
>  arch/arm/mach-omap2/common.h              |  4 +-
>  arch/arm/mach-omap2/omap-headsmp.S        |  8 ++--
>  arch/arm/mach-omap2/omap-mpuss-lowpower.c | 69 +++++++++++++++++++++++++------
>  arch/arm/mach-omap2/omap-smp.c            |  6 +--
>  arch/arm/mach-omap2/pm44xx.c              | 58 +++++++++++++++++++++-----
>  5 files changed, 113 insertions(+), 32 deletions(-)


From maxime.ripard at free-electrons.com  Thu May 16 11:33:07 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 16 May 2013 17:33:07 +0200
Subject: [PATCH] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <20130515122834.GA26168@roeck-us.net>
References: <1368390994-27161-1-git-send-email-carlo.caione@gmail.com>
 <51934896.3000506@free-electrons.com> <20130515122834.GA26168@roeck-us.net>
Message-ID: <5194FC33.8090303@free-electrons.com>

Hi,

Le 15/05/2013 14:28, Guenter Roeck a ?crit :
> On Wed, May 15, 2013 at 10:34:30AM +0200, Maxime Ripard wrote:
>> Hi Carlo,
>>
>> Le 12/05/2013 22:36, Carlo Caione a ?crit :
>>> This patch adds the driver for the watchdog found in the Allwinner A10 and
>>> A13 SoCs. It has DT-support and uses the new watchdog framework.
>>>
>>> Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
>>> ---
>>>  drivers/watchdog/Kconfig     |  10 ++
>>>  drivers/watchdog/Makefile    |   1 +
>>>  drivers/watchdog/sunxi_wdt.c | 218 +++++++++++++++++++++++++++++++++++++++++++
>>>  3 files changed, 229 insertions(+)
>>>  create mode 100644 drivers/watchdog/sunxi_wdt.c
>>>
>>> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
>>> index e89fc31..473e670 100644
>>> --- a/drivers/watchdog/Kconfig
>>> +++ b/drivers/watchdog/Kconfig
>>> @@ -299,6 +299,16 @@ config ORION_WATCHDOG
>>>  	  To compile this driver as a module, choose M here: the
>>>  	  module will be called orion_wdt.
>>>  
>>> +config SUNXI_WATCHDOG
>>> +	tristate "Sunxi watchdog"
>>
>> Maybe mention what sunxi is? something like "Allwinner SoCs watchdog
>> support"
>>
>>> +	depends on ARCH_SUNXI
>>> +	select WATCHDOG_CORE
>>> +	help
>>> +	  Say Y here to include support for the watchdog timer
>>> +	  in Allwinner A10 and A13.
>>
>> I'd be more generic here. As far as we know, this code is found in A10,
>> A10s, A13, and can easily be adapted to support the A31 (and I suspect
>> the A20 as well). Something like "Allwinner SoCs"
>>
>>> +	  To compile this driver as a module, choose M here: the
>>> +	  module will be called sunxi_wdt.
>>> +
>>>  config COH901327_WATCHDOG
>>>  	bool "ST-Ericsson COH 901 327 watchdog"
>>>  	depends on ARCH_U300
>>> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
>>> index a300b94..5012d5f 100644
>>> --- a/drivers/watchdog/Makefile
>>> +++ b/drivers/watchdog/Makefile
>>> @@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
>>>  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
>>>  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
>>>  obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
>>> +obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
>>>  obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
>>>  obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
>>>  obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
>>> diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
>>> new file mode 100644
>>> index 0000000..fe193b3
>>> --- /dev/null
>>> +++ b/drivers/watchdog/sunxi_wdt.c
>>> @@ -0,0 +1,218 @@
>>> +/*
>>> + *      sunxi Watchdog Driver
>>> + *
>>> + *      Copyright (c) 2013 Carlo Caione
>>> + *                    2012 Henrik Nordstrom
>>> + *
>>> + *      This program is free software; you can redistribute it and/or
>>> + *      modify it under the terms of the GNU General Public License
>>> + *      as published by the Free Software Foundation; either version
>>> + *      2 of the License, or (at your option) any later version.
>>> + *
>>> + *      Based on xen_wdt.c
>>> + *      (c) Copyright 2010 Novell, Inc.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/err.h>
>>> +#include <linux/init.h>
>>> +#include <linux/io.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/moduleparam.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/types.h>
>>> +#include <linux/watchdog.h>
>>> +
>>> +#define WDT_MAX_TIMEOUT         16
>>> +#define WDT_MIN_TIMEOUT         1
>>> +#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
>>> +#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
>>> +
>>> +#define WDT_CTRL                0x00
>>> +#define WDT_MODE                0x04
>>> +
>>> +#define WDT_MODE_RST_EN         (1 << 1)
>>> +#define WDT_MODE_EN             (1 << 0)
>>> +
>>> +#define WDT_CTRL_RESTART        (1 << 0)
>>
>> I'd prefer to see the bits values just behind the register they belong to.
>>
>>> +#define WDT_CTRL_RESERVED       (0x0a57 << 1)
>>> +#define DRV_NAME		"sunxi-wdt"
>>> +#define DRV_VERSION		"1.0"
>>> +
>>> +static bool nowayout = WATCHDOG_NOWAYOUT;
>>> +static int heartbeat = WDT_MAX_TIMEOUT;
>>> +
>>> +static const int wdt_timeout_map[] = {
>>> +	[1] = 0b0001,
>>> +	[2] = 0b0010,
>>> +	[3] = 0b0011,
>>> +	[4] = 0b0100,
>>> +	[5] = 0b0101,
>>> +	[6] = 0b0110,
>>> +	[8] = 0b0111,
>>> +	[10] = 0b1000,
>>> +	[12] = 0b1001,
>>> +	[14] = 0b1010,
>>> +	[16] = 0b1011,
>>> +};
>>
>> It would be great to have a comment about what this map is here for and
>> how you store the values.
>>
>> You don't support the 0.5s timeout here as well. I know why, but some
>> new comer might not, so I guess it would be great to add it to the
>> comment as well.
>>
>> Moreover, I'd really like this to be supported. Maybe, since obviously
>> we can't put a value at the index 0.5, maybe saying that the 0 index is
>> actually this 0.5ms timeout value?
>>
> guess you mean 0.5s, not 0.5ms.
> 
> Since the watchdog infrastructure does not support it, how would you set it ?

Ah, I wasn't aware of such limitation in the watchdog infrastructure.

Ok, You can ignore my comment about this then. But I'd still like some
comments before that structure.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From dmurphy at ti.com  Thu May 16 11:35:57 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Thu, 16 May 2013 10:35:57 -0500
Subject: [PATCH v4] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <20130515170516.GA6135@kahuna>
References: <1368636386-17138-1-git-send-email-dmurphy@ti.com>
 <20130515170516.GA6135@kahuna>
Message-ID: <5194FCDD.8080209@ti.com>

On 05/15/2013 12:05 PM, Nishanth Menon wrote:
> On 11:46-20130515, Dan Murphy wrote:
>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>> are different.
>>
>> A1-A3 = gpio_wk7
>> ES = gpio_110
>>
>> There is no change to LED D2
>>
>> Abstract away the pinmux and the LED definitions for the two boards into
>> the respective DTS files.
>>
>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
>> ---
> nit: Giving patch history is a nice practise.
>>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++-
>>  arch/arm/boot/dts/omap4-panda-es.dts      |   40 +++++++++++++++++++++++++++++
>>  2 files changed, 55 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> index 03bd60d..2b516af 100644
>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> @@ -16,7 +16,7 @@
>>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>>  	};
>>  
>> -	leds {
>> +	leds: leds {
>>  		compatible = "gpio-leds";
>>  		heartbeat {
>>  			label = "pandaboard::status1";
>> @@ -137,6 +137,20 @@
> I missed noticing this previously, Apologies on the same.
> Considering that drivers/leds/leds-gpio.c has ability to handle pinctrl,
> One better option might be to provide pinctrl phandle with leds -
> Couple of reasons why this might be good:
> a) one gets the following warning at boot:
> "leds-gpio leds.8: pins are not configured from the driver"
> b) you donot need to setup the pins by default at boot - it is not
> mandatory for the system functionality, instead we do it *if* the driver
> is enabled.
> Further, optionally, all you'd have to do in panda-es.dts is the following
> &led_wkgpio_pins {
> 		pinctrl-single,pins = <
> 			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> 		>;
> }
> Similarly for gpios override for panda-es.
I am not sure you really want to do this.
If I make the pinctrl part of the led structure then the only way the gpio_wk7 on a1-a3 to be configured is when
the CONFIG_LEDS_GPIO flag is set.

Do you really want that dependency?  You did say it was a key fix
At least this way the pins are configured regardless of that flag.
>>  	};
>>  };
>>  
>> +&omap4_pmx_wkup {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <
>> +		&led_wkgpio_pins
>> +	>;
>> +
>> +	led_wkgpio_pins: pinmux_leds_wkpins {
>> +		pinctrl-single,pins = <
>> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
>> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>> +		>;
>> +	};
>> +};
>> +
>>  &i2c1 {
>>  	pinctrl-names = "default";
>>  	pinctrl-0 = <&i2c1_pins>;
>> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
>> index f1d8c21..e6f696d 100644
>> --- a/arch/arm/boot/dts/omap4-panda-es.dts
>> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
>> @@ -34,3 +34,43 @@
>>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>>  		>;
>>  };
>> +
>> +&leds {
>> +	compatible = "gpio-leds";
>> +	heartbeat {
>> +		label = "pandaboard::status1";
>> +		gpios = <&gpio4 14 0>;
>> +		linux,default-trigger = "heartbeat";
>> +	};
>> +	mmc {
>> +		label = "pandaboard::status2";
>> +		gpios = <&gpio1 8 0>;
>> +		linux,default-trigger = "mmc0";
>> +	};
>> +};
>> +
>> +&omap4_pmx_core {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <
>> +		&led_gpio_pins
>> +	>;
>> +
>> +	led_gpio_pins: gpio_led_pmx {
>> +		pinctrl-single,pins = <
>> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
>> +		>;
>> +	};
>> +};
>> +
>> +&omap4_pmx_wkup {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <
>> +		&led_wkgpio_pins
>> +	>;
>> +
>> +	led_wkgpio_pins: pinmux_leds_wkpins {
>> +		pinctrl-single,pins = <
>> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>> +		>;
>> +	};
>> +};
>> -- 
>> 1.7.5.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
------------------
Dan Murphy



From maxime.ripard at free-electrons.com  Thu May 16 11:37:44 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 16 May 2013 17:37:44 +0200
Subject: [PATCH] gpio: mxs: Use set and clear capabilities of the gpio
 controller
In-Reply-To: <20130502024443.GE3442@S2101-09.ap.freescale.net>
References: <1367244438-5322-1-git-send-email-maxime.ripard@free-electrons.com>
 <20130502024443.GE3442@S2101-09.ap.freescale.net>
Message-ID: <5194FD48.3010106@free-electrons.com>

Hi Linus,

Le 02/05/2013 04:44, Shawn Guo a ?crit :
> On Mon, Apr 29, 2013 at 04:07:18PM +0200, Maxime Ripard wrote:
>> The current driver doesn't use the set and clear registers found on the
>> mxs gpio controller.
>>
>> This leads the generic gpio controller to be using some internal value
>> to avoid looking up the value stored in the registers, making it behave
>> pretty much like a cache.
>>
>> This raises some coherency problem when a gpio is not modified by the
>> gpio controller, while it can easily be fixed by using the set and clear
>> registers.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> 
> Acked-by: Shawn Guo <shawn.guo at linaro.org>

Would you consider merging this patch?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From jason at lakedaemon.net  Thu May 16 11:40:31 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 11:40:31 -0400
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <20130516093312.GB2459@localhost>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130516093312.GB2459@localhost>
Message-ID: <20130516154031.GF6563@titan.lakedaemon.net>

On Thu, May 16, 2013 at 06:33:14AM -0300, Ezequiel Garcia wrote:
> On Wed, May 15, 2013 at 03:25:21PM +0200, Thomas Petazzoni wrote:
> [..]
> > +
> > +static int __init mvebu_pcie_probe(struct platform_device *pdev)
> > +{
> > +	struct mvebu_pcie *pcie;
> > +	struct device_node *np = pdev->dev.of_node;
> > +	struct of_pci_range range;
> > +	struct of_pci_range_parser parser;
> > +	struct device_node *child;
> > +	int i, ret;
> > +
> > +	pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
> > +			    GFP_KERNEL);
> > +	if (!pcie)
> > +		return -ENOMEM;
> > +
> > +	pcie->pdev = pdev;
> > +
> > +	if (of_pci_range_parser_init(&parser, np))
> > +		return -EINVAL;
> > +
> > +	/* Get the I/O and memory ranges from DT */
> > +	for_each_of_pci_range(&parser, &range) {
> > +		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
> > +		if (restype == IORESOURCE_IO) {
> > +			of_pci_range_to_resource(&range, np, &pcie->io);
> > +			of_pci_range_to_resource(&range, np, &pcie->realio);
> > +			pcie->io.name = "I/O";
> > +			pcie->realio.start = max_t(resource_size_t,
> > +						   PCIBIOS_MIN_IO,
> > +						   range.pci_addr);
> > +			pcie->realio.end = min_t(resource_size_t,
> > +						 IO_SPACE_LIMIT,
> > +						 range.pci_addr + range.size);
> > +		}
> > +		if (restype == IORESOURCE_MEM) {
> > +			of_pci_range_to_resource(&range, np, &pcie->mem);
> > +			pcie->mem.name = "MEM";
> > +		}
> > +	}
> > +
> > +	/* Get the bus range */
> > +	ret = of_pci_parse_bus_range(np, &pcie->busn);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
> > +			ret);
> > +		return ret;
> > +	}
> > +
> > +	for_each_child_of_node(pdev->dev.of_node, child) {
> > +		if (!of_device_is_available(child))
> > +			continue;
> > +		pcie->nports++;
> > +	}
> > +
> > +	pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
> > +				   sizeof(struct mvebu_pcie_port),
> > +				   GFP_KERNEL);
> > +	if (!pcie->ports)
> > +		return -ENOMEM;
> > +
> > +	i = 0;
> > +	for_each_child_of_node(pdev->dev.of_node, child) {
> > +		struct mvebu_pcie_port *port = &pcie->ports[i];
> > +
> > +		if (!of_device_is_available(child))
> > +			continue;
> > +
> > +		port->pcie = pcie;
> > +
> > +		if (of_property_read_u32(child, "marvell,pcie-port",
> > +					 &port->port)) {
> > +			dev_warn(&pdev->dev,
> > +				 "ignoring PCIe DT node, missing pcie-port property\n");
> > +			continue;
> > +		}
> > +
> > +		if (of_property_read_u32(child, "marvell,pcie-lane",
> > +					 &port->lane))
> > +			port->lane = 0;
> > +
> > +		port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
> > +				       port->port, port->lane);
> > +
> > +		port->devfn = of_pci_get_devfn(child);
> > +		if (port->devfn < 0)
> > +			continue;
> > +
> > +		port->base = mvebu_pcie_map_registers(pdev, child, port);
> > +		if (!port->base) {
> > +			dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
> > +				port->port, port->lane);
> > +			continue;
> > +		}
> > +
> > +		if (mvebu_pcie_link_up(port)) {
> > +			port->haslink = 1;
> > +			dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
> > +				 port->port, port->lane);
> > +		} else {
> > +			port->haslink = 0;
> > +			dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
> > +				 port->port, port->lane);
> > +		}
> > +
> > +		port->clk = of_clk_get_by_name(child, NULL);
> > +		if (!port->clk) {
> > +			dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
> > +			       port->port, port->lane);
> > +			iounmap(port->base);
> > +			port->haslink = 0;
> > +			continue;
> > +		}
> > +
> > +		port->dn = child;
> > +
> > +		clk_prepare_enable(port->clk);
> > +		spin_lock_init(&port->conf_lock);
> > +
> > +		mvebu_sw_pci_bridge_init(port);
> > +
> > +		i++;
> > +	}
> > +
> > +	mvebu_pcie_enable(pcie);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id mvebu_pcie_of_match_table[] = {
> > +	{ .compatible = "marvell,armada-xp-pcie", },
> > +	{ .compatible = "marvell,armada-370-pcie", },
> > +	{},
> > +};
> > +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
> > +
> > +static struct platform_driver mvebu_pcie_driver = {
> > +	.driver = {
> > +		.owner = THIS_MODULE,
> > +		.name = "mvebu-pcie",
> > +		.of_match_table =
> > +		   of_match_ptr(mvebu_pcie_of_match_table),
> > +	},
> > +};
> > +
> > +static int mvebu_pcie_init(void)
> 
> Building this showed a warning here. It seems you forgot
> to mark this one as __init.

Thomas, I'll fix this up when I pull this in, no need to resend. :)

thx,

Jason.


From rpimentel.silva at gmail.com  Thu May 16 11:45:13 2013
From: rpimentel.silva at gmail.com (Rogerio Pimentel)
Date: Thu, 16 May 2013 12:45:13 -0300
Subject: parallel-display driver for i.MX53
In-Reply-To: <CAOkaPuX7RjwrMiZUCGwXTovgsFf=onRkrGa2U+qUv-tU3t4WWg@mail.gmail.com>
References: <CAOkaPuX7RjwrMiZUCGwXTovgsFf=onRkrGa2U+qUv-tU3t4WWg@mail.gmail.com>
Message-ID: <CAOkaPuUdugB8+qTakh8-N0bsxfobQymbYtCQ67FfX8CuttPb0A@mail.gmail.com>

Hi Philipp,

I see that reverting patch

2ea42608ba977bd05ce7b2d8a1f65efacfc84352
staging: drm/imx: Add support for VGA via TVE on i.MX53

The display on LCD/i.MX53QSB shows for about 1 second and turn off.
Have you noticed any kind of problem on parallel displays after your
recent patches?
Could you please confirm that imx-parallel display is functional after
your tve patches are applied?

Rgds
Rogerio Pimentel

On Thu, May 16, 2013 at 11:02 AM, Rogerio Pimentel
<rpimentel.silva at gmail.com> wrote:
> Hi,
>
> I'm trying to add the parallel display on i.MX53QSB but it's not
> working on current linux next. It was working prior to 3.10-rc1.
>
> Does anybody know about any significant change that made this driver
> break? Or maybe something else I need to do on imx53-qsb.dtb?
>
> Thanks,
> Rogerio


From jason at lakedaemon.net  Thu May 16 11:45:43 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 11:45:43 -0400
Subject: [PATCH] ARM: dove: add a kms/drm driver
In-Reply-To: <20130516132822.09b883cf@armhf>
References: <20130516132822.09b883cf@armhf>
Message-ID: <20130516154543.GG6563@titan.lakedaemon.net>

Jean-Fran?ois,

Please run ./scripts/get_maintainer.pl on your patches before
submitting.  In this case:

$ ./scripts/get_maintainer.pl -f drivers/gpu/drm/
David Airlie <airlied at linux.ie> (maintainer:DRM DRIVERS)
dri-devel at lists.freedesktop.org (open list:DRM DRIVERS)
linux-kernel at vger.kernel.org (open list)

I've added them to the CC:

thx,

Jason.


On Thu, May 16, 2013 at 01:28:22PM +0200, Jean-Francois Moine wrote:
> This patch adds a KMS/DRM video driver for the LCD and display
> controllers of the Marvell's Dove SoC.
> 
> Signed-off-by: Jean-Francois Moine <moinejf at free.fr>
> ---
>  drivers/gpu/drm/Kconfig          |    2 +
>  drivers/gpu/drm/Makefile         |    1 +
>  drivers/gpu/drm/dove/Kconfig     |   10 +
>  drivers/gpu/drm/dove/Makefile    |    6 +
>  drivers/gpu/drm/dove/dove_crtc.c | 1378 ++++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/dove/dove_dcon.h |   64 +++
>  drivers/gpu/drm/dove/dove_drv.c  |  380 +++++++++++++
>  drivers/gpu/drm/dove/dove_drv.h  |   93 ++++
>  drivers/gpu/drm/dove/dove_ec.c   |  570 ++++++++++++++++++++
>  drivers/gpu/drm/dove/dove_lcd.h  |  519 ++++++++++++++++++
>  10 files changed, 3023 insertions(+)
> 
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index b16c50e..c6e4f4f 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -220,3 +220,5 @@ source "drivers/gpu/drm/omapdrm/Kconfig"
>  source "drivers/gpu/drm/tilcdc/Kconfig"
>  
>  source "drivers/gpu/drm/qxl/Kconfig"
> +
> +source "drivers/gpu/drm/dove/Kconfig"
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 1c9f243..6428683 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -52,4 +52,5 @@ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
>  obj-$(CONFIG_DRM_OMAP)	+= omapdrm/
>  obj-$(CONFIG_DRM_TILCDC)	+= tilcdc/
>  obj-$(CONFIG_DRM_QXL) += qxl/
> +obj-$(CONFIG_DRM_DOVE)	+= dove/
>  obj-y			+= i2c/
> diff --git a/drivers/gpu/drm/dove/Kconfig b/drivers/gpu/drm/dove/Kconfig
> new file mode 100644
> index 0000000..465dc4d
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/Kconfig
> @@ -0,0 +1,10 @@
> +config DRM_DOVE
> +	tristate "DRM Support for Marvell Dove"
> +	depends on DRM && ARCH_DOVE
> +	depends on OF
> +	select DRM_KMS_HELPER
> +	select DRM_KMS_CMA_HELPER
> +	select DRM_GEM_CMA_HELPER
> +	help
> +	  Choose this option if you have a Marvell Dove chipset.
> +	  If M is selected the module will be called dove-drm.
> diff --git a/drivers/gpu/drm/dove/Makefile b/drivers/gpu/drm/dove/Makefile
> new file mode 100644
> index 0000000..3758a19
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/Makefile
> @@ -0,0 +1,6 @@
> +#
> +# Makefile for Marvell Dove's DRM device driver
> +#
> +
> +dove-drm-objs := dove_drv.o dove_crtc.o dove_ec.o
> +obj-$(CONFIG_DRM_DOVE) += dove-drm.o
> diff --git a/drivers/gpu/drm/dove/dove_crtc.c b/drivers/gpu/drm/dove/dove_crtc.c
> new file mode 100644
> index 0000000..9e397e7
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_crtc.c
> @@ -0,0 +1,1378 @@
> +/*
> + * Marvell Dove DRM driver - CRTC
> + *
> + * Copyright (C) 2013
> + *   Jean-Francois Moine <moinejf at free.fr>
> + *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_irq.h>
> +
> +#include "dove_drv.h"
> +#include "dove_lcd.h"
> +
> +#define DOVE_LCD_REG_BASE_MASK	0xfffff
> +#define DOVE_LCD0_REG_BASE	0x20000
> +#define DOVE_LCD1_REG_BASE	0x10000
> +
> +#define to_dove_lcd(x) container_of(x, struct dove_lcd, crtc)
> +
> +static inline void dove_write(struct dove_lcd *dove_lcd, u32 reg, u32 data)
> +{
> +	writel(data, dove_lcd->mmio + reg);
> +}
> +static inline u32 dove_read(struct dove_lcd *dove_lcd, u32 reg)
> +{
> +	return readl(dove_lcd->mmio + reg);
> +}
> +static inline void dove_set(struct dove_lcd *dove_lcd, u32 reg, u32 mask)
> +{
> +	dove_write(dove_lcd, reg, dove_read(dove_lcd, reg) | mask);
> +}
> +static inline void dove_clear(struct dove_lcd *dove_lcd, u32 reg, u32 mask)
> +{
> +	dove_write(dove_lcd, reg, dove_read(dove_lcd, reg) & ~mask);
> +}
> +
> +/*
> + * vertical blank functions
> + */
> +u32 dove_vblank_count(struct drm_device *dev, int crtc)
> +{
> +	struct dove_lcd *dove_lcd = dove_drm.lcds[crtc];
> +
> +	return STA_GRA_FRAME_COUNT(dove_read(dove_lcd, SPU_IRQ_ISR));
> +}
> +
> +int dove_enable_vblank(struct drm_device *dev, int crtc)
> +{
> +	struct dove_lcd *dove_lcd = dove_drm.lcds[crtc];
> +
> +#ifdef HANDLE_INTERLACE
> +	dove_lcd->vblank_enabled = 1;
> +#endif
> +	dove_set(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
> +	return 0;
> +}
> +
> +void dove_disable_vblank(struct drm_device *dev, int crtc)
> +{
> +	struct dove_lcd *dove_lcd = dove_drm.lcds[crtc];
> +
> +#ifdef HANDLE_INTERLACE
> +	dove_lcd->vblank_enabled = 0;
> +	if (!dove_lcd->v_sync0)
> +#endif
> +	dove_clear(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
> +}
> +
> +#ifdef CONFIG_DEBUG_FS
> +static int dove_lcd_regs_show(struct seq_file *m,
> +			struct dove_lcd *dove_lcd)
> +{
> +	u32 x, shl, shh, total_v, total_h, active_h, active_v;
> +	u32 orig_buff_x, orig_buff_y, zoomed_x, zoomed_y;
> +	unsigned i;
> +
> +	seq_printf(m, "\t\t*** LCD %d ***\n", dove_lcd->num);
> +
> +	/* Get resolution */
> +	x = dove_read(dove_lcd, LCD_SPU_V_H_ACTIVE);
> +	active_h = H_LCD(x);
> +	active_v = V_LCD(x);
> +
> +	/* Get total line */
> +	x = dove_read(dove_lcd, LCD_SPUT_V_H_TOTAL);
> +	total_h = H_LCD(x);
> +	total_v = V_LCD(x);
> +	seq_printf(m, "----total-------------------------<%4dx%4d>"
> +					"-------------------------\n"
> +			"----active--------------|", total_h, total_v);
> +
> +	/* Get H Timings */
> +	x = dove_read(dove_lcd, LCD_SPU_H_PORCH);
> +	shl = F_LCD(x);
> +	shh = B_LCD(x);
> +	seq_printf(m, "->front porch(%d)->hsync(%d)->back porch(%d)\n",
> +		shl, total_h - shl -shh - active_h, shh);
> +
> +	seq_printf(m,	"|\t\t\t|\n"
> +			"|\t\t\t|\n"
> +			"|\t<%4dx%4d>\t|\n"
> +			"|\t\t\t|\n"
> +			"|\t\t\t|\n"
> +			"------------------------|\n", active_h, active_v);
> +
> +	/* Get V Timings */
> +	x = dove_read(dove_lcd, LCD_SPU_V_PORCH);
> +	shl = F_LCD(x);
> +	shh = B_LCD(x);
> +	seq_printf(m, "|\n|front porch(%d)\n|vsync(%d)\n|back porch(%d)\n",
> +		shl, total_v - shl - shh - active_v, shh);
> +	seq_printf(m, "----------------------------------"
> +			"-----------------------------------\n");
> +
> +	/* Get Line Pitch */
> +	x = dove_read(dove_lcd, LCD_CFG_GRA_PITCH);
> +	shl = x & 0x0000ffff;
> +	seq_printf(m, "gfx line pitch in memory is <%d>\n",
> +			shl);
> +
> +	/* Get scaling info */
> +	x = dove_read(dove_lcd, LCD_SPU_GRA_HPXL_VLN);
> +	orig_buff_x = H_LCD(x);
> +	orig_buff_y = V_LCD(x);
> +	x = dove_read(dove_lcd, LCD_SPU_GZM_HPXL_VLN);
> +	zoomed_x = H_LCD(x);
> +	zoomed_y = V_LCD(x);
> +	seq_printf(m, "Scaled from <%dx%d> to <%dx%d>\n",
> +			orig_buff_x, orig_buff_y, zoomed_x, zoomed_y);
> +
> +	seq_printf(m, "======================================\n");
> +
> +	for (i = 0x0080; i <= 0x01c4; i += 4) {
> +		x = dove_read(dove_lcd, i);
> +		seq_printf(m, "0x%04x 0x%08x\n", i, x);
> +	}
> +	return 0;
> +}
> +
> +static int dove_regs_show(struct seq_file *m, void *arg)
> +{
> +	struct dove_lcd *dove_lcd;
> +	unsigned i;
> +
> +	for (i = 0; i < MAX_DOVE_LCD; i++) {
> +		dove_lcd = dove_drm.lcds[i];
> +		if (dove_lcd)
> +			dove_lcd_regs_show(m, dove_lcd);
> +	}
> +	return 0;
> +}
> +
> +static struct drm_info_list dove_debugfs_list[] = {
> +	{ "lcd", dove_regs_show, 0 },
> +	{ "fb",   drm_fb_cma_debugfs_show, 0 },
> +};
> +
> +int dove_debugfs_init(struct drm_minor *minor)
> +{
> +	struct drm_device *dev = minor->dev;
> +	int ret;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	ret = drm_debugfs_create_files(dove_debugfs_list,
> +			ARRAY_SIZE(dove_debugfs_list),
> +			minor->debugfs_root, minor);
> +	if (ret)
> +		dev_err(dev->dev, "could not install dove_debugfs_list\n");
> +
> +	return ret;
> +}
> +
> +void dove_debugfs_cleanup(struct drm_minor *minor)
> +{
> +	drm_debugfs_remove_files(dove_debugfs_list,
> +			ARRAY_SIZE(dove_debugfs_list), minor);
> +}
> +#endif
> +
> +static void dove_update_base(struct dove_lcd *dove_lcd)
> +{
> +	struct drm_crtc *crtc = &dove_lcd->crtc;
> +	struct drm_framebuffer *fb = crtc->fb;
> +	struct drm_gem_cma_object *gem;
> +	unsigned int depth, bpp;
> +	dma_addr_t start;
> +
> +	drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
> +	gem = drm_fb_cma_get_gem_obj(fb, 0);
> +	start = gem->paddr + fb->offsets[0] +
> +			crtc->y * fb->pitches[0] +
> +			crtc->x * bpp / 8;
> +
> +	dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR0, start);
> +#ifdef HANDLE_INTERLACE
> +	if (dove_lcd->crtc.mode.mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR1,
> +					start + fb->pitches[0]);
> +		dove_write(dove_lcd, LCD_CFG_GRA_PITCH, fb->pitches[0] * 2);
> +		return;
> +	}
> +#endif
> +	dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR1, start);
> +	dove_write(dove_lcd, LCD_CFG_GRA_PITCH, fb->pitches[0]);
> +}
> +
> +static void set_frame_timings(struct dove_lcd *dove_lcd)
> +{
> +	struct drm_crtc *crtc = &dove_lcd->crtc;
> +	const struct drm_display_mode *mode = &crtc->mode;
> +	u32 h_active, v_active, h_orig, v_orig, h_zoom, v_zoom;
> +	u32 hfp, hbp, vfp, vbp, hs, vs, v_total;
> +	u32 x;
> +
> +	/*
> +	 * Calc active size, zoomed size, porch.
> +	 */
> +	h_active = h_zoom = mode->hdisplay;
> +	v_active = v_zoom = mode->vdisplay;
> +	hfp = mode->hsync_start - mode->hdisplay;
> +	hbp = mode->htotal - mode->hsync_end;
> +	vfp = mode->vsync_start - mode->vdisplay;
> +	vbp = mode->vtotal - mode->vsync_end;
> +	hs = mode->hsync_end - mode->hsync_start;
> +	vs = mode->vsync_end - mode->vsync_start;
> +
> +	/*
> +	 * Calc original size.
> +	 */
> +	h_orig = h_active;
> +	v_orig = v_active;
> +
> +#ifdef HANDLE_INTERLACE
> +	/* interlaced workaround */
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		v_active /= 2;
> +		v_zoom /= 2;
> +		v_orig /= 2;
> +	}
> +#endif
> +
> +	/* calc total width and height */
> +	v_total = v_active + vfp + vs + vbp;
> +
> +	/* apply setting to registers */
> +	dove_write(dove_lcd, LCD_SPU_V_H_ACTIVE, LCD_H_V(h_active, v_active));
> +	dove_write(dove_lcd, LCD_SPU_GRA_HPXL_VLN, LCD_H_V(h_orig, v_orig));
> +	dove_write(dove_lcd, LCD_SPU_GZM_HPXL_VLN, LCD_H_V(h_zoom, v_zoom));
> +	dove_write(dove_lcd, LCD_SPU_H_PORCH, LCD_F_B(hfp, hbp));
> +	dove_write(dove_lcd, LCD_SPU_V_PORCH, LCD_F_B(vfp, vbp));
> +	dove_write(dove_lcd, LCD_SPUT_V_H_TOTAL,
> +					LCD_H_V(mode->htotal, v_total));
> +
> +	/* configure vsync adjust logic */
> +	x = dove_read(dove_lcd, LCD_TV_CONTROL1);
> +	x &= ~(VSYNC_L_OFFSET_MASK | VSYNC_H_OFFSET_MASK);
> +	x |= VSYNC_OFFSET_EN |			/* VSYNC adjust enable */
> +		VSYNC_L_OFFSET(h_active + hfp) |
> +		VSYNC_H_OFFSET(h_active + hfp);
> +#ifdef HANDLE_INTERLACE
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		dove_lcd->v_sync0 = VSYNC_L_OFFSET(h_active + hfp) |
> +				VSYNC_H_OFFSET(h_active + hfp);
> +		dove_lcd->v_sync1 = VSYNC_L_OFFSET(h_active / 2 + hfp) |
> +				VSYNC_H_OFFSET(h_active / 2 + hfp);
> +	} else {
> +		dove_lcd->v_sync0 = 0;
> +	}
> +#endif
> +	dove_write(dove_lcd, LCD_TV_CONTROL1, x);
> +}
> +
> +static int dove_set_clock(struct dove_lcd *dove_lcd)
> +{
> +	struct drm_crtc *crtc = &dove_lcd->crtc;
> +	const struct drm_display_mode *mode = &crtc->mode;
> +	struct clk *clk;
> +	u32 x, needed_pixclk, ref_clk, div, fract;
> +	int clk_src;
> +
> +	fract = 0;
> +	needed_pixclk = mode->clock * 1000;
> +#ifdef HANDLE_INTERLACE
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> +		needed_pixclk /= 2;
> +#endif
> +
> +	/* first check if pixclk is multiple of current clock */
> +	clk_src = dove_lcd->clk_src;
> +	clk = dove_lcd->clk[clk_src];
> +	ref_clk = clk_get_rate(clk);
> +
> +	DRM_DEBUG_DRIVER("clk src %d rate %u needed %u div %u mod %u\n",
> +			clk_src, ref_clk, needed_pixclk,
> +			ref_clk / needed_pixclk, ref_clk % needed_pixclk);
> +
> +	if (ref_clk % needed_pixclk == 0) {
> +		div = ref_clk / needed_pixclk;
> +		goto set_clock;
> +	}
> +
> +	/* try to set current clock to requested pixclk */
> +	clk_set_rate(clk, needed_pixclk);
> +	ref_clk = clk_get_rate(clk);
> +	if (ref_clk == needed_pixclk) {
> +		div = 1;
> +		goto set_clock;
> +	}
> +
> +	/* check if any other clock can set pixclk directly */
> +	for (clk_src = 0; clk_src < MAX_CLK; clk_src++) {
> +		clk = dove_lcd->clk[clk_src];
> +		if (!clk)
> +			continue;
> +
> +		/* try to set clock to requested pixclk */
> +		clk_set_rate(clk, needed_pixclk);
> +		ref_clk = clk_get_rate(clk);
> +
> +		if (ref_clk % needed_pixclk == 0) {
> +			div = ref_clk / needed_pixclk;
> +			goto set_clock;
> +		}
> +	}
> +
> +	/* fall back to default fix clock source LCD or AXI */
> +	if (dove_lcd->clk[SCLK_SRC_PLLDIV])
> +		clk_src = SCLK_SRC_PLLDIV;
> +	else
> +		clk_src = SCLK_SRC_AXI;
> +	clk = dove_lcd->clk[clk_src];
> +
> +	clk_set_rate(clk, needed_pixclk);
> +	ref_clk = clk_get_rate(clk);
> +		
> +	/* use internal divider */
> +	if (false) {
> +/*fixme: does not work*/
> +		ref_clk /= 1000;
> +		needed_pixclk /= 1000;
> +		x = (ref_clk * 0x1000 + needed_pixclk - 1) / needed_pixclk;
> +		div = x >> 12;
> +		if (div < 1)
> +			div = 1;
> +		else
> +			fract = x & 0xfff;
> +	} else {
> +		div = (ref_clk + needed_pixclk - 1) / needed_pixclk;
> +		if (div < 1)
> +			div = 1;
> +	}
> +
> +set_clock:
> +	dove_lcd->clk_src = clk_src;
> +	DRM_DEBUG_DRIVER("set clk src %d ref %u div %u fract %u needed %u\n",
> +			clk_src, ref_clk, div, fract, needed_pixclk);
> +	x = SET_SCLK(clk_src, div, fract);
> +	dove_write(dove_lcd, LCD_CFG_SCLK_DIV, x);
> +	return 0;
> +}
> +
> +static void set_dma_control(struct dove_lcd *dove_lcd)
> +{
> +	const struct drm_display_mode *mode = &dove_lcd->crtc.mode;
> +	u32 x;
> +	int fmt, rbswap;
> +
> +	rbswap = 1;				/* default */
> +	switch (dove_lcd->crtc.fb->pixel_format) {
> +	case DRM_FORMAT_BGR888:
> +		rbswap = 0;
> +	case DRM_FORMAT_RGB888:
> +		fmt = GMODE_RGB888PACKED;
> +		break;
> +	case DRM_FORMAT_XBGR8888:
> +		rbswap = 0;
> +	case DRM_FORMAT_XRGB8888:		/* depth 24 */
> +		fmt = GMODE_RGBA888;
> +		break;
> +	case DRM_FORMAT_ABGR8888:
> +		rbswap = 0;
> +	case DRM_FORMAT_ARGB8888:		/* depth 32 */
> +		fmt = GMODE_RGB888UNPACKED;
> +		break;
> +	case DRM_FORMAT_YVYU:
> +		rbswap = 0;
> +	case DRM_FORMAT_YUYV:
> +		fmt = GMODE_YUV422PACKED;
> +		break;
> +	case DRM_FORMAT_YVU422:
> +		rbswap = 0;
> +	case DRM_FORMAT_YUV422:
> +		fmt = GMODE_YUV422PLANAR;
> +		break;
> +	case DRM_FORMAT_YVU420:
> +		rbswap = 0;
> +	default:
> +/*	case DRM_FORMAT_YUV420: */
> +		fmt = GMODE_YUV420PLANAR;
> +		break;
> +	}
> +
> +	x = dove_read(dove_lcd, LCD_SPU_DMA_CTRL0);
> +	x &= ~(CFG_PALETTE_ENA |		/* true color */
> +		CFG_GRAFORMAT_MASK |
> +		CFG_GRA_SWAPRB |
> +		CFG_GRA_FTOGGLE);
> +	x |= CFG_GRA_ENA |			/* graphic enable */
> +		CFG_GRA_HSMOOTH;		/* horiz. smooth scaling */
> +	x |= CFG_GRAFORMAT(fmt);
> +
> +	if (!rbswap)
> +		x |= CFG_GRA_SWAPRB;
> +#ifdef HANDLE_INTERLACE
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> +		x |= CFG_GRA_FTOGGLE;
> +#endif
> +	dove_write(dove_lcd, LCD_SPU_DMA_CTRL0, x);
> +
> +	/*
> +	 * trigger DMA on the falling edge of vsync if vsync is
> +	 * active low, or on the rising edge if vsync is active high
> +	 */
> +	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
> +		dove_set(dove_lcd, LCD_SPU_DMA_CTRL1, CFG_VSYNC_INV);
> +}
> +
> +/* this function is called on mode DRM_MODE_DPMS_ON
> + * and also at loading time with gpio_only set */
> +static void set_dumb_panel_control(struct dove_lcd *dove_lcd,
> +				int gpio_only)
> +{
> +	const struct drm_display_mode *mode = &dove_lcd->crtc.mode;
> +	u32 x;
> +
> +	x = 0;
> +	if (dove_lcd->dpms == DRM_MODE_DPMS_ON)
> +		x = CFG_DUMB_ENA;
> +	if (!gpio_only) {
> +		if (dove_lcd->dpms == DRM_MODE_DPMS_ON)
> +			/*
> +			 * When dumb interface isn't under 24bit
> +			 * It might be under SPI or GPIO. If set
> +			 * to 0x7 will force LCD_D[23:0] output
> +			 * blank color and damage GPIO and SPI
> +			 * behavior.
> +			 */
> +			x |= CFG_DUMBMODE(DUMB24_RGB888_0);
> +		else
> +			x |= CFG_DUMBMODE(7);
> +/*fixme
> +		if (mode->flags & FB_SYNC_COMP_HIGH_ACT)
> +			x |= CFG_INV_COMPSYNC;
> +*/
> +		if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
> +			x |= CFG_INV_VSYNC;
> +
> +		/* Following is a weired workaround. This bit shouldn't be set
> +		 * For now, if it's 1080p or 720 then don't set HOR_HIGH_ACT */
> +		if ((mode->hdisplay == 1920 && mode->vdisplay == 1080) ||
> +		    (mode->hdisplay == 1280 && mode->vdisplay == 720))
> +			/* Do nothing */
> +			;
> +		else
> +			if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
> +				x |= CFG_INV_HSYNC;
> +	}
> +
> +	dove_write(dove_lcd, LCD_SPU_DUMB_CTRL, x);
> +}
> +
> +void dove_crtc_start(struct dove_lcd *dove_lcd)
> +{
> +	struct drm_crtc *crtc = &dove_lcd->crtc;
> +	struct drm_display_mode *mode = &crtc->mode;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	if (mode->clock == 0) {
> +		dev_err(dove_lcd->dev, "crtc_start: no clock!\n");
> +		dove_lcd->dpms = DRM_MODE_DPMS_OFF;
> +		return;
> +	}
> +
> +	set_frame_timings(dove_lcd);
> +	if (dove_set_clock(dove_lcd) < 0)
> +		return;
> +	set_dma_control(dove_lcd);
> +	dove_update_base(dove_lcd);
> +	set_dumb_panel_control(dove_lcd, 0);
> +
> +#ifdef HANDLE_INTERLACE
> +	if (dove_lcd->v_sync0) {		/* interlace mode on */
> +		dove_set(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
> +	} else {				/* interlace mode off */
> +		if (!dove_lcd->vblank_enabled)
> +			dove_clear(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
> +	}
> +#endif
> +
> +	DRM_DEBUG_DRIVER("start %s@%d\n",
> +			crtc->mode.name, crtc->mode.vrefresh);
> +}
> +
> +void dove_crtc_stop(struct dove_lcd *dove_lcd)
> +{
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_GRA_ENA);
> +	dove_clear(dove_lcd, LCD_SPU_DUMB_CTRL, CFG_DUMB_ENA);
> +#ifdef HANDLE_INTERLACE
> +	if (dove_lcd->v_sync0
> +	 && !dove_lcd->vblank_enabled)
> +		dove_clear(dove_lcd, SPU_IRQ_ENA, IRQ_GRA_FRAME_DONE);
> +#endif
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * cursor
> + */
> +
> +/* load the hardware cursor */
> +static int load_cursor(struct dove_lcd *dove_lcd,
> +			struct drm_file *file_priv,
> +			uint32_t handle,
> +			int data_len)
> +{
> +	struct drm_gem_object *obj;
> +	struct drm_gem_cma_object *cma_obj;
> +	u8 *p_pixel;
> +	u32 u, val;
> +	u32 ram, color;
> +	int i, j, ret;
> +
> +	obj = drm_gem_object_lookup(dove_drm.drm, file_priv, handle);
> +	if (!obj)
> +		return -ENOENT;
> +
> +	if (!obj->map_list.map) {
> +		dev_warn(dove_lcd->dev, "cursor not mapped\n");
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	if (data_len != obj->size) {
> +		dev_warn(dove_lcd->dev, "bad cursor size\n");
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	cma_obj = to_drm_gem_cma_obj(obj);
> +	p_pixel = cma_obj->vaddr;
> +
> +	u = CFG_SRAM_INIT_WR_RD(SRAMID_INIT_WRITE) |
> +			CFG_SRAM_ADDR_LCDID(SRAMID_HWC);
> +	ram = CFG_SRAM_INIT_WR_RD(SRAMID_INIT_WRITE);
> +
> +	/* load the RGBA cursor to SRAM */
> +	for (i = 0; i < data_len / 4 / 4; i++) {
> +		color = (p_pixel[3 * 4 + 0] << 24) |	/* red */
> +			(p_pixel[2 * 4 + 0] << 16) |
> +			(p_pixel[1 * 4 + 0] << 8) |
> +			p_pixel[0];
> +		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, color);
> +		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL,
> +				ram | CFG_SRAM_ADDR_LCDID(SRAMID_HWC32_RAM1));
> +		color = (p_pixel[3 * 4 + 1] << 24) |	/* green */
> +			(p_pixel[2 * 4 + 1] << 16) |
> +			(p_pixel[1 * 4 + 1] << 8) |
> +			p_pixel[1];
> +		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, color);
> +		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL,
> +				ram | CFG_SRAM_ADDR_LCDID(SRAMID_HWC32_RAM2));
> +		color = (p_pixel[3 * 4 + 2] << 24) |	/* blue */
> +			(p_pixel[2 * 4 + 2] << 16) |
> +			(p_pixel[1 * 4 + 2] << 8) |
> +			p_pixel[2];
> +		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, color);
> +		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL,
> +				ram | CFG_SRAM_ADDR_LCDID(SRAMID_HWC32_RAM3));
> +		p_pixel += 4 * 4;
> +		if ((++ram & 0xff) == 0) {
> +			ram -= 0x100;			/* I[7:0] */
> +			ram += 1 << 12;			/* J[1:0] */
> +		}
> +	}
> +
> +	/* set the transparency */
> +	p_pixel = cma_obj->vaddr;
> +	for (i = 0; i < data_len / 16 / 4; i++) {
> +		val = 0;
> +		for (j = 16 * 4 - 4; j >= 0 ; j -= 4) {
> +			val <<= 2;
> +			if (p_pixel[j + 3])	/* alpha */
> +				val |= 1;	/* not transparent */
> +		}
> +		dove_write(dove_lcd, LCD_SPU_SRAM_WRDAT, val);
> +		dove_write(dove_lcd, LCD_SPU_SRAM_CTRL, u++);
> +		p_pixel += 16 * 4;
> +	}
> +	ret = 0;
> +out:
> +	drm_gem_object_unreference_unlocked(obj);
> +	return ret;
> +}
> +
> +static int dove_cursor_set(struct drm_crtc *crtc,
> +			struct drm_file *file_priv,
> +			uint32_t handle,
> +			uint32_t width,
> +			uint32_t height)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +	int ret;
> +
> +	DRM_DEBUG_DRIVER("%dx%d handle %d\n", width, height, handle);
> +
> +	/* disable cursor */
> +	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
> +
> +	if (!handle)
> +		return 0;		/* cursor off */
> +
> +	if (width != 64 || height != 64) {
> +		dev_err(dove_lcd->dev, "bad cursor size\n");
> +		return -EINVAL;
> +	}
> +
> +	/* load the cursor */
> +	ret = load_cursor(dove_lcd, file_priv, handle, width * height * 4);
> +	if (ret < 0)
> +		return ret;
> +
> +	/* set cursor size */
> +	dove_write(dove_lcd, LCD_SPU_HWC_HPXL_VLN, LCD_H_V(width, height));
> +
> +	/* enable cursor */
> +	dove_set(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
> +
> +	return 0;
> +}
> +
> +static int dove_cursor_move(struct drm_crtc *crtc,
> +				int x, int y)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +
> +	if (x < 0)
> +		x = 0;
> +	if (y < 0)
> +		y = 0;
> +	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
> +	dove_write(dove_lcd, LCD_SPU_HWC_OVSA_HPXL_VLN, LCD_H_V(x, y));
> +	dove_set(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_HWC_ENA);
> +	return 0;
> +}
> +
> +static void dove_crtc_destroy(struct drm_crtc *crtc)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	WARN_ON(dove_lcd->dpms == DRM_MODE_DPMS_ON);
> +
> +	drm_crtc_cleanup(crtc);
> +}
> +
> +static int dove_crtc_page_flip(struct drm_crtc *crtc,
> +			struct drm_framebuffer *fb,
> +			struct drm_pending_vblank_event *event)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +	struct drm_device *drm = dove_drm.drm;
> +	unsigned long flags;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	spin_lock_irqsave(&drm->event_lock, flags);
> +	if (dove_lcd->event) {
> +		spin_unlock_irqrestore(&drm->event_lock, flags);
> +		dev_err(drm->dev, "already pending page flip!\n");
> +		return -EBUSY;
> +	}
> +	spin_unlock_irqrestore(&drm->event_lock, flags);
> +
> +	crtc->fb = fb;
> +	dove_update_base(dove_lcd);
> +
> +	if (event) {
> +		event->pipe = 0;
> +		spin_lock_irqsave(&drm->event_lock, flags);
> +		dove_lcd->event = event;
> +		spin_unlock_irqrestore(&drm->event_lock, flags);
> +		drm_vblank_get(drm, dove_lcd->num);
> +	}
> +
> +	return 0;
> +}
> +
> +static void dove_crtc_dpms(struct drm_crtc *crtc, int mode)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +
> +	/* we really only care about on or off */
> +	if (mode != DRM_MODE_DPMS_ON)
> +		mode = DRM_MODE_DPMS_OFF;
> +
> +	DRM_DEBUG_DRIVER("dpms %s\n", mode == DRM_MODE_DPMS_ON ? "on" : "off");
> +
> +	if (dove_lcd->dpms == mode)
> +		return;
> +
> +	dove_lcd->dpms = mode;
> +
> +	if (mode == DRM_MODE_DPMS_ON)
> +		dove_crtc_start(dove_lcd);
> +	else
> +		dove_crtc_stop(dove_lcd);
> +}
> +
> +static bool dove_crtc_mode_fixup(struct drm_crtc *crtc,
> +				const struct drm_display_mode *mode,
> +				struct drm_display_mode *adjusted_mode)
> +{
> +	DRM_DEBUG_DRIVER("\n");
> +	if (adjusted_mode->vrefresh == 0) {
> +/*		drm_mode_set_name(adjusted_mode); */
> +		adjusted_mode->vrefresh = drm_mode_vrefresh(adjusted_mode);
> +		DRM_DEBUG_DRIVER("%s@%d\n",
> +				adjusted_mode->name, adjusted_mode->vrefresh);
> +	}
> +	return true;
> +}
> +
> +static void dove_crtc_prepare(struct drm_crtc *crtc)
> +{
> +	DRM_DEBUG_DRIVER("\n");
> +	dove_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
> +}
> +
> +static void dove_crtc_commit(struct drm_crtc *crtc)
> +{
> +	DRM_DEBUG_DRIVER("\n");
> +/*	dove_crtc_dpms(crtc, DRM_MODE_DPMS_ON); */
> +}
> +
> +static int dove_crtc_mode_set(struct drm_crtc *crtc,
> +			struct drm_display_mode *mode,
> +			struct drm_display_mode *adjusted_mode,
> +			int x, int y,
> +			struct drm_framebuffer *old_fb)
> +{
> +	unsigned int bandwidth;
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	if (mode->hdisplay > 2048)
> +		return MODE_VIRTUAL_X;
> +
> +	/* width must be multiple of 16 */
> +	if (mode->hdisplay & 0xf)
> +		return MODE_VIRTUAL_X;
> +
> +	if (mode->vdisplay > 2048)
> +		return MODE_VIRTUAL_Y;
> +
> +	/* filter out modes that would require too much memory bandwidth: */
> +	bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode);
> +	if (bandwidth > 1920 * 1080 * 60)
> +		return MODE_BAD;
> +
> +/*fixme: is this useful? */
> +	mode = &crtc->mode;
> +	if (mode->vrefresh == 0) {
> +		drm_mode_set_name(mode);
> +		mode->vrefresh = drm_mode_vrefresh(mode);
> +		DRM_DEBUG_DRIVER("%s@%d\n", mode->name, mode->vrefresh);
> +	}
> +	return MODE_OK;
> +}
> +
> +static int dove_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
> +				struct drm_framebuffer *old_fb)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +
> +	DRM_DEBUG_DRIVER("\n");
> +	dove_update_base(dove_lcd);
> +	return 0;
> +}
> +
> +/* mandatory drm function */
> +static void dove_crtc_load_lut(struct drm_crtc *crtc)
> +{
> +	DRM_DEBUG_DRIVER("\n");
> +}
> +
> +static const struct drm_crtc_funcs dove_crtc_funcs = {
> +	.cursor_set	= dove_cursor_set,
> +	.cursor_move	= dove_cursor_move,
> +	.destroy        = dove_crtc_destroy,
> +	.set_config     = drm_crtc_helper_set_config,
> +	.page_flip      = dove_crtc_page_flip,
> +};
> +
> +static const struct drm_crtc_helper_funcs dove_crtc_helper_funcs = {
> +	.dpms           = dove_crtc_dpms,
> +	.mode_fixup     = dove_crtc_mode_fixup,
> +	.prepare        = dove_crtc_prepare,
> +	.commit         = dove_crtc_commit,
> +	.mode_set       = dove_crtc_mode_set,
> +	.mode_set_base  = dove_crtc_mode_set_base,
> +	.load_lut       = dove_crtc_load_lut,
> +};
> +
> +void dove_crtc_cancel_page_flip(struct dove_lcd *dove_lcd,
> +				struct drm_file *file)
> +{
> +	struct drm_pending_vblank_event *event;
> +	struct drm_device *drm = dove_drm.drm;
> +	unsigned long flags;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	/*
> +	 * Destroy the pending vertical blanking event associated with the
> +	 * pending page flip, if any, and disable vertical blanking interrupts.
> +	 */
> +	spin_lock_irqsave(&drm->event_lock, flags);
> +	event = dove_lcd->event;
> +	if (event && event->base.file_priv == file) {
> +		dove_lcd->event = NULL;
> +		event->base.destroy(&event->base);
> +		drm_vblank_put(drm, dove_lcd->num);
> +	}
> +	spin_unlock_irqrestore(&drm->event_lock, flags);
> +}
> +
> +/* configure default register values */
> +static void dove_set_defaults(struct dove_lcd *dove_lcd)
> +{
> +	u32 x;
> +
> +	/* set the default clock */
> +	if (dove_lcd->clk[SCLK_SRC_PLLDIV])
> +		dove_lcd->clk_src = SCLK_SRC_PLLDIV;
> +	else
> +		dove_lcd->clk_src = SCLK_SRC_AXI;
> +	DRM_DEBUG_DRIVER("default clock %d\n", dove_lcd->clk_src);
> +
> +	x = SET_SCLK(dove_lcd->clk_src, 1, 0);
> +	dove_write(dove_lcd, LCD_CFG_SCLK_DIV, x);
> +	dove_write(dove_lcd, LCD_SPU_BLANKCOLOR, 0);
> +
> +	dove_write(dove_lcd, SPU_IOPAD_CONTROL, IOPAD_DUMB24);
> +	dove_write(dove_lcd, LCD_CFG_GRA_START_ADDR1, 0);
> +	dove_write(dove_lcd, LCD_SPU_GRA_OVSA_HPXL_VLN, 0);
> +	dove_write(dove_lcd, LCD_SPU_SRAM_PARA0, 0);
> +	dove_write(dove_lcd, LCD_SPU_SRAM_PARA1, CFG_CSB_256x32 |
> +						CFG_CSB_256x24 |
> +						CFG_CSB_256x8);
> +	dove_write(dove_lcd, LCD_SPU_DMA_CTRL1, CFG_VSYNC_TRIG(2) |
> +						CFG_GATED_ENA |
> +						CFG_PWRDN_ENA |
> +						CFG_ALPHA_MODE(2) |
> +						CFG_ALPHA(0xff) |
> +						CFG_PXLCMD(0x81));
> +
> +	/*
> +	 * Fix me: to avoid jiggling issue for high resolution in
> +	 * dual display, we set watermark to affect LCD AXI read
> +	 * from MC (default 0x80). Lower watermark means LCD will
> +	 * do DMA read more often.
> +	 */
> +	x = dove_read(dove_lcd, LCD_CFG_RDREG4F);
> +	x &= ~DMA_WATERMARK_MASK;
> +	x |= DMA_WATERMARK(0x20);
> +
> +	/*
> +	 * Disable LCD SRAM Read Wait State to resolve HWC32 make
> +	 * system hang while use external clock.
> +	 */
> +	x &= ~LCD_SRAM_WAIT;
> +	dove_write(dove_lcd, LCD_CFG_RDREG4F, x);
> +
> +	/* prepare the hwc32 */
> +	dove_set(dove_lcd, LCD_TV_CONTROL1, HWC32_ENABLE);
> +
> +	/* set hwc32 with 100% static alpha blending factor */
> +	dove_write(dove_lcd, LCD_SPU_ALPHA_COLOR1,
> +				HWC32_CFG_ALPHA(0xff));
> +}
> +
> +static irqreturn_t dove_lcd_irq(int irq, void *dev_id)
> +{
> +	struct dove_lcd *dove_lcd = (struct dove_lcd *) dev_id;
> +	struct drm_pending_vblank_event *event;
> +	struct drm_device *drm = dove_drm.drm;
> +	u32 isr;
> +	unsigned long flags;
> +
> +	isr = dove_read(dove_lcd, SPU_IRQ_ISR);
> +	dove_write(dove_lcd, SPU_IRQ_ISR, 0);
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	if (isr & IRQ_GRA_FRAME_DONE) {
> +#ifdef HANDLE_INTERLACE
> +		if (dove_lcd->v_sync0) {
> +			u32 x;
> +
> +			x = dove_read(dove_lcd, LCD_TV_CONTROL1);
> +			x &= ~(VSYNC_L_OFFSET_MASK | VSYNC_H_OFFSET_MASK);
> +			if (isr & IRQ_GRA_FRAME0)
> +				x |= dove_lcd->v_sync0;
> +			else
> +				x |= dove_lcd->v_sync1;
> +			dove_write(dove_lcd, LCD_TV_CONTROL1, x);
> +		}
> +		if (dove_lcd->vblank_enabled)
> +#endif
> +		drm_handle_vblank(drm, dove_lcd->num); 
> +		spin_lock_irqsave(&drm->event_lock, flags);
> +		event = dove_lcd->event;
> +		dove_lcd->event = NULL;
> +		if (event)
> +			drm_send_vblank_event(drm, dove_lcd->num, event);
> +		spin_unlock_irqrestore(&drm->event_lock, flags);
> +		if (event)
> +			drm_vblank_put(drm, dove_lcd->num);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/* initialize a lcd */
> +static int dove_crtc_init(struct dove_lcd *dove_lcd)
> +{
> +	struct drm_crtc *crtc = &dove_lcd->crtc;
> +	int ret;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	dove_lcd->dpms = DRM_MODE_DPMS_OFF;
> +
> +	ret = drm_crtc_init(dove_drm.drm, crtc, &dove_crtc_funcs);
> +	if (ret < 0)
> +		goto fail;
> +
> +	dove_write(dove_lcd, SPU_IRQ_ENA, 0);	/* disable interrupts */
> +	ret = devm_request_irq(dove_lcd->dev, dove_lcd->irq, dove_lcd_irq, 0,
> +			dove_lcd->name, dove_lcd);
> +	if (ret < 0) {
> +		dev_err(dove_lcd->dev, "unable to request irq %d\n",
> +				dove_lcd->irq);
> +		goto fail;
> +	}
> +
> +	if (ret < 0) {
> +		dev_err(dove_lcd->dev, "failed to install IRQ handler\n");
> +		goto fail;
> +	}
> +
> +	dove_set_defaults(dove_lcd);
> +	set_dumb_panel_control(dove_lcd, 1);
> +
> +	drm_crtc_helper_add(crtc, &dove_crtc_helper_funcs);
> +
> +	return 0;
> +
> +fail:
> +	dove_crtc_destroy(crtc);
> +	return ret;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Overlay plane
> + */
> +
> +static void plane_update_base(struct dove_lcd *dove_lcd,
> +				int plane_num,
> +				struct drm_framebuffer *fb,
> +				int fmt,
> +				int x, int y,
> +				int w, int h)
> +{
> +	struct drm_gem_cma_object *gem;
> +	unsigned int addr;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	gem = drm_fb_cma_get_gem_obj(fb, plane_num);
> +
> +	addr = gem->paddr + fb->offsets[0] + y * fb->pitches[0] + x;
> +	dove_write(dove_lcd, LCD_SPU_DMA_START_ADDR_Y0, addr);
> +
> +	switch (fmt) {
> +	case VMODE_YUV422PLANAR:
> +	case VMODE_YUV420PLANAR:
> +		addr += w * h / 2;	/* planar */
> +		break;
> +	}
> +	dove_write(dove_lcd, LCD_SPU_DMA_START_ADDR_U0, addr);
> +
> +	switch (fmt) {
> +	case VMODE_YUV422PLANAR:
> +		addr += w * h / 2;
> +		break;
> +	case VMODE_YUV420PLANAR:
> +		addr += w * h / 4;
> +		break;
> +	}
> +	dove_write(dove_lcd, LCD_SPU_DMA_START_ADDR_V0, addr);
> +
> +	switch (fb->pixel_format) {
> +	case VMODE_YUV422PACKED:
> +		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_YC,
> +						LCD_Y_C(w * 2, 0));
> +		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_UV, LCD_U_V(w, w));
> +		break;
> +	default:
> +/*	case VMODE_YUV422PLANAR: */
> +/*	case VMODE_YUV420PLANAR: */
> +		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_YC, LCD_Y_C(w, 0));
> +		dove_write(dove_lcd, LCD_SPU_DMA_PITCH_UV,
> +						LCD_U_V(w / 2, w / 2));
> +		break;
> +	}
> +}
> +
> +static int dove_plane_update(struct drm_plane *plane,
> +			struct drm_crtc *crtc,
> +			struct drm_framebuffer *fb,
> +			int crtc_x, int crtc_y,
> +			unsigned int crtc_w, unsigned int crtc_h,
> +			uint32_t src_x, uint32_t src_y,
> +			uint32_t src_w, uint32_t src_h)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(crtc);
> +	u32 x, x_bk;
> +	int fmt, rbswap;
> +
> +	DRM_DEBUG_DRIVER("%d\n", plane == &dove_lcd->planes[PLANE_VID]);
> +
> +	if (plane != &dove_lcd->planes[PLANE_VID])
> +		return 0;
> +	rbswap = 1;				/* default */
> +	switch (fb->pixel_format) {
> +	case DRM_FORMAT_YVYU:
> +		rbswap = 0;
> +	case DRM_FORMAT_YUYV:
> +	case DRM_FORMAT_UYVY:
> +		fmt = VMODE_YUV422PACKED;
> +		break;
> +	case DRM_FORMAT_YVU422:
> +		rbswap = 0;
> +	case DRM_FORMAT_YUV422:
> +		fmt = VMODE_YUV422PLANAR;
> +		break;
> +	case DRM_FORMAT_YVU420:
> +		rbswap = 0;
> +	default:
> +/*	case DRM_FORMAT_YUV420: */
> +		fmt = VMODE_YUV420PLANAR;
> +		break;
> +	}
> +
> +	x_bk = x = dove_read(dove_lcd, LCD_SPU_DMA_CTRL0);
> +					/* clear video layer's field */
> +	x &= ~(CFG_YUV2RGB_DMA | CFG_DMA_SWAP_MASK |
> +		CFG_DMA_TSTMODE | CFG_DMA_HSMOOTH | CFG_DMA_FTOGGLE |
> +		CFG_DMAFORMAT_MASK | CFG_PALETTE_ENA);
> +	x |= CFG_DMA_HSMOOTH;		/* enable horizontal smooth scaling */
> +	x |= CFG_DMAFORMAT(fmt);	/* configure hardware pixel format */
> +/*fixme: no RGB */
> +	if (fb->pixel_format == DRM_FORMAT_UYVY) {
> +		x |= CFG_YUV2RGB_DMA;
> +	} else if (fmt == VMODE_YUV422PACKED) {
> +		x |= CFG_YUV2RGB_DMA |
> +			CFG_DMA_SWAPYU |
> +			CFG_DMA_SWAPRB;
> +		if (rbswap)
> +			x |= CFG_DMA_SWAPUV;
> +	} else {				/* planar */
> +		x |= CFG_YUV2RGB_DMA |
> +			CFG_DMA_SWAPRB;
> +		if (!rbswap)
> +			x |= CFG_DMA_SWAPUV;
> +	}
> +	if (x != x_bk)
> +		dove_write(dove_lcd, LCD_SPU_DMA_CTRL0, x);
> +
> +	/* set the dma addresses */
> +	plane_update_base(dove_lcd, PLANE_VID,
> +			fb, fmt, src_x, src_y, src_w, src_h);
> +
> +	/* original size */
> +	dove_write(dove_lcd, LCD_SPU_DMA_HPXL_VLN,
> +				LCD_H_V(src_w, src_h));
> +
> +	/* scaled size */
> +	dove_write(dove_lcd, LCD_SPU_DZM_HPXL_VLN,
> +				LCD_H_V(crtc_w, crtc_h));
> +
> +	/* update video position offset */
> +	dove_write(dove_lcd, LCD_SPUT_DMA_OVSA_HPXL_VLN,
> +				LCD_H_V(crtc_x, crtc_y));
> +	return 0;
> +}
> +
> +static int dove_plane_disable(struct drm_plane *plane)
> +{
> +	struct dove_lcd *dove_lcd = to_dove_lcd(plane->crtc);
> +
> +	DRM_DEBUG_DRIVER("%d\n",
> +			plane == &dove_lcd->planes[PLANE_VID]);
> +
> +	if (plane != &dove_lcd->planes[PLANE_VID])
> +		return 0;
> +
> +	dove_clear(dove_lcd, LCD_SPU_DMA_CTRL0, CFG_DMA_ENA);
> +	return 0;
> +}
> +
> +static void dove_plane_destroy(struct drm_plane *plane)
> +{
> +	dove_plane_disable(plane);
> +	drm_plane_cleanup(plane);
> +}
> +
> +static const struct drm_plane_funcs plane_funcs = {
> +	.update_plane = dove_plane_update,
> +	.disable_plane = dove_plane_disable,
> +	.destroy = dove_plane_destroy,
> +};
> +static const uint32_t gfx_formats[] = {
> +	DRM_FORMAT_BGR888,
> +	DRM_FORMAT_RGB888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVU422,
> +	DRM_FORMAT_YUV422,
> +	DRM_FORMAT_YVU420,
> +	DRM_FORMAT_YUV420,
> +};
> +static const uint32_t vid_formats[] = {
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVU422,
> +	DRM_FORMAT_YUV422,
> +	DRM_FORMAT_YVU420,
> +	DRM_FORMAT_YUV420,
> +	DRM_FORMAT_UYVY,
> +};
> +
> +static int dove_planes_init(struct dove_lcd *dove_lcd)
> +{
> +	struct drm_device *drm = dove_drm.drm;
> +	struct drm_plane *plane;
> +	int ret;
> +
> +	if (false) {
> +		plane = &dove_lcd->planes[PLANE_VID];
> +		ret = drm_plane_init(drm, plane, 1 << dove_lcd->num,
> +				&plane_funcs,
> +				gfx_formats, ARRAY_SIZE(gfx_formats), true);
> +		if (ret < 0)
> +			return ret;
> +		plane->crtc = &dove_lcd->crtc;
> +	}
> +	plane = &dove_lcd->planes[PLANE_VID];
> +	ret = drm_plane_init(drm, plane, 1 << dove_lcd->num,
> +				&plane_funcs,
> +				vid_formats, ARRAY_SIZE(vid_formats), false);
> +	if (ret < 0)
> +		return ret;
> +	plane->crtc = &dove_lcd->crtc;
> +	return ret;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Initialization
> + */
> +
> +int dove_lcd_init(struct dove_lcd *dove_lcd)
> +{
> +	int ret;
> +
> +	ret = dove_crtc_init(dove_lcd);
> +	if (ret < 0)
> +		return ret;
> +	ret = dove_planes_init(dove_lcd);
> +	if (ret < 0)
> +		dev_err(dove_lcd->dev, "failed to create the planes\n");
> +
> +	return ret;
> +}
> +
> +/* at probe time, get the possible LCD clocks */
> +static int get_lcd_clocks(struct dove_lcd *dove_lcd)
> +{
> +	struct device *dev = dove_lcd->dev;
> +	struct device_node *np = dev->of_node;
> +	struct of_phandle_args clkspec;
> +	struct clk *clk;
> +	int i, no_clock, ret;
> +
> +	no_clock = 1;
> +	for (i = 0; i < MAX_CLK; i++) {
> +
> +		/* check first if there is a phandle to the clock */
> +		ret = of_parse_phandle_with_args(np,
> +					"clocks", "#clock-cells", i,
> +					&clkspec);
> +		if (ret)
> +			continue;		/* no defined clock here */
> +		of_node_put(clkspec.np);
> +
> +		/* if no clock driver, ignore this clock */
> +		clk = of_clk_get(np, i);
> +		if (IS_ERR(clk)) {
> +			if (!dove_drm.probe_defer) {
> +				dove_drm.probe_defer = 1;
> +				return -EPROBE_DEFER;
> +			}
> +			dev_err(dev, "no driver for clock %i\n", i);
> +			continue;
> +		}
> +		DRM_DEBUG_DRIVER("clock %d ok\n", i);
> +		clk_prepare_enable(clk);
> +		dove_lcd->clk[i] = clk;
> +		no_clock = 0;
> +	}
> +	if (no_clock) {
> +		dev_err(dev, "no available clock\n");
> +		return -EINVAL;
> +	}
> +	if (!dove_lcd->clk[SCLK_SRC_PLLDIV] && !dove_lcd->clk[SCLK_SRC_AXI]) {
> +		dev_err(dev, "no fixed clock\n");
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> +
> +static int dove_lcd_remove(struct platform_device *pdev)
> +{
> +	struct dove_lcd *dove_lcd = platform_get_drvdata(pdev);
> +	struct clk *clk;
> +	int i;
> +
> +	dove_write(dove_lcd, SPU_IRQ_ENA, 0);	/* disable interrupts */
> +
> +	if (dove_drm.lcds[dove_lcd->num] == dove_lcd)
> +		dove_drm.lcds[dove_lcd->num] = NULL;
> +
> +	for (i = 0; i < MAX_CLK; i++) {
> +		clk = dove_lcd->clk[i];
> +		if (clk) {
> +			clk_disable_unprepare(clk);
> +			clk_put(clk);
> +		}
> +	}
> +	
> +	kfree(dove_lcd);
> +	return 0;
> +}
> +
> +static int dove_lcd_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct dove_lcd *dove_lcd;
> +	struct resource *res;
> +	int ret;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	/* bail out early if no DT data */
> +	if (!np) {
> +		dev_err(dev, "no device-tree\n");
> +		return -ENXIO;
> +	}
> +
> +	dove_lcd = kzalloc(sizeof *dove_lcd, GFP_KERNEL);
> +	if (!dove_lcd) {
> +		dev_err(dev, "failed to allocate private data\n");
> +		return -ENOMEM;
> +	}
> +	platform_set_drvdata(pdev, dove_lcd);
> +	dove_lcd->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(dev, "failed to get memory resource\n");
> +		ret = -EINVAL;
> +		goto fail;
> +	}
> +
> +	dove_lcd->mmio = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(dove_lcd->mmio)) {
> +		dev_err(dev, "failed map registers\n");
> +		ret = PTR_ERR(dove_lcd->mmio);
> +		dove_lcd->mmio = NULL;
> +		goto fail;
> +	}
> +
> +	switch (((u32) dove_lcd->mmio) & DOVE_LCD_REG_BASE_MASK) {
> +	case DOVE_LCD0_REG_BASE:
> +/*		dove_lcd->num = 0; */
> +		break;
> +	case DOVE_LCD1_REG_BASE:
> +		dove_lcd->num = 1;
> +		break;
> +	default:
> +		dev_err(dev, "unknown lcd reg base %08x\n",
> +					(u32) dove_lcd->mmio);
> +		ret = -EINVAL;
> +		goto fail;
> +	}
> +	snprintf(dove_lcd->name, sizeof dove_lcd->name, "dove-lcd%d",
> +			dove_lcd->num);
> +	dove_drm.lcds[dove_lcd->num] = dove_lcd;
> +
> +	dove_lcd->irq = irq_of_parse_and_map(np, 0);
> +	if (dove_lcd->irq < 0 || dove_lcd->irq == NO_IRQ) {
> +		dev_err(dev, "unable to get irq lcd %d\n", dove_lcd->num);
> +		ret = -EINVAL;
> +		goto fail;
> +	}
> +
> +	ret = get_lcd_clocks(dove_lcd);
> +	if (ret < 0)
> +		goto fail;
> +
> +	/* check the presence of a possible external slave encoder */
> +	ret = dove_ec_probe(dove_lcd);
> +	if (ret < 0)
> +		goto fail;
> +
> +	/* init done, try to initialize the drm driver */
> +	return dove_probed();
> +
> +fail:
> +	dove_lcd_remove(pdev);
> +	return ret;
> +}
> +
> +static struct of_device_id dove_lcd_of_match[] = {
> +	{ .compatible = "marvell,dove-lcd" },
> +	{ },
> +};
> +struct platform_driver dove_lcd_platform_driver = {
> +	.driver     = {
> +		.owner  = THIS_MODULE,
> +		.name   = "dove-lcd",
> +		.of_match_table = dove_lcd_of_match,
> +	},
> +	.probe      = dove_lcd_probe,
> +	.remove     = dove_lcd_remove,
> +};
> diff --git a/drivers/gpu/drm/dove/dove_dcon.h b/drivers/gpu/drm/dove/dove_dcon.h
> new file mode 100644
> index 0000000..da2b99c
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_dcon.h
> @@ -0,0 +1,64 @@
> +/*
> + * Display controller registers of Marvell DOVE
> + *
> + * Copyright (C) 2013
> + *   Jean-Francois Moine <moinejf at free.fr>
> + *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef _DOVE_DCON_H_
> +#define	_DOVE_DCON_H_
> +
> +/* ------------< DCON register >------------ */
> +
> +#define DCON_CTL0		0x0000
> +#define   VGA_CLK_DISABLE		BIT(25)
> +#define   DCON_CLK_DISABLE		BIT(24)
> +#define   DCON_RST			BIT(23)
> +#define   LCD_Disable			BIT(17)
> +#define   Reverse_Scan			BIT(10)
> +#define   LCD_Port_B_Select_MASK	0x00000300
> +#define		Port_B_Select_LCD1	0x00000000
> +#define		Port_B_Select_LCD0	0x00000100
> +#define		Port_B_Select_A_copy	0x00000300
> +#define   LCD_Port_A_Select_MASK	0x000000c0
> +#define		Port_A_Select_LCD	0x00000000
> +#define		Port_A_Select_OLPC	0x00000040
> +#define		Port_A_Select_Dual	0x00000080
> +#define		Port_A_Select_ext	0x000000c0
> +#define   LBUF_EN			BIT(5)
> +#define DCON_IRQ_CTL		0x0008
> +#define   IRQ_Control_MASK		0x00ff0000
> +#define DITHER_REG_R		0x0050
> +#define DITHER_REG_G		0x0054
> +#define DITHER_REG_B		0x0058
> +#define DCON_DITHER_PAT_RL	0x0060
> +#define DCON_DITHER_PAT_RH	0x0064
> +#define DCON_DITHER_PAT_GL	0x0068
> +#define DCON_DITHER_PAT_GH	0x006c
> +#define DCON_DITHER_PAT_BL	0x0070
> +#define DCON_DITHER_PAT_BH	0x0074
> +#define VGA_Global		0x0080
> +#define VGA_CHA			0x0084
> +#define VGA_CHB			0x0088
> +#define VGA_CHC			0x008c
> +#define VGA_CHA_STA		0x0090
> +#define VGA_CHB_STA		0x0094
> +#define VGA_CHC_STA		0x0098
> +#define CT_LUT_INDEX		0x00a4
> +#define CT_LUT_DATA		0x00a8
> +#define FTDLL_CTL		0x00c0
> +
> +#endif /* _DOVE_DCON_H_ */
> diff --git a/drivers/gpu/drm/dove/dove_drv.c b/drivers/gpu/drm/dove/dove_drv.c
> new file mode 100644
> index 0000000..e9e77ad
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_drv.c
> @@ -0,0 +1,380 @@
> +/*
> + * Marvell Dove DRM driver - main
> + *
> + * Copyright (C) 2013
> + *   Jean-Francois Moine <moinejf at free.fr>
> + *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of.h>
> +
> +#include "dove_drv.h"
> +
> +#define DRIVER_NAME	"dove-drm"
> +#define DRIVER_DESC	"Marvell Dove DRM"
> +#define DRIVER_DATE	"20130516"
> +#define DRIVER_MAJOR	1
> +#define DRIVER_MINOR	0
> +
> +struct dove_drm dove_drm;
> +static struct platform_device *g_pdev;
> +static atomic_t probed;
> +
> +static struct drm_framebuffer *dove_fb_create(struct drm_device *drm,
> +					struct drm_file *file_priv,
> +					struct drm_mode_fb_cmd2 *mode_cmd)
> +{
> +	DRM_DEBUG_DRIVER("fmt %.4s\n", (char *) &mode_cmd->pixel_format);
> +
> +	switch (mode_cmd->pixel_format) {
> +	case DRM_FORMAT_BGR888:
> +	case DRM_FORMAT_RGB888:
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_ABGR8888:
> +	case DRM_FORMAT_ARGB8888:
> +	case DRM_FORMAT_YVYU:
> +	case DRM_FORMAT_YUYV:
> +	case DRM_FORMAT_YVU422:
> +	case DRM_FORMAT_YUV422:
> +	case DRM_FORMAT_YVU420:
> +	case DRM_FORMAT_YUV420:
> +		break;
> +	default:
> +		return ERR_PTR(-EINVAL);
> +	}
> +	return drm_fb_cma_create(drm, file_priv, mode_cmd);
> +}
> +
> +static void dove_fb_output_poll_changed(struct drm_device *drm)
> +{
> +	DRM_DEBUG_DRIVER("fb:%d\n", dove_drm.fbdev != NULL);
> +	if (dove_drm.fbdev)
> +		drm_fbdev_cma_hotplug_event(dove_drm.fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs mode_config_funcs = {
> +	.fb_create = dove_fb_create,
> +	.output_poll_changed = dove_fb_output_poll_changed,
> +};
> +
> +/*
> + * DRM operations:
> + */
> +static int dove_unload(struct drm_device *drm)
> +{
> +	struct dove_lcd *dove_lcd;
> +	int i;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	for (i = 0; i < MAX_DOVE_LCD; i++) {
> +		dove_lcd = dove_drm.lcds[i];
> +		if (dove_lcd) {
> +			if (dove_lcd->planes[PLANE_VID].dev)
> +				drm_plane_cleanup(&dove_lcd->planes[PLANE_VID]);
> +			if (dove_lcd->planes[PLANE_GFX].dev)
> +				drm_plane_cleanup(&dove_lcd->planes[PLANE_GFX]);
> +		}
> +	}
> +	drm_kms_helper_poll_fini(drm);
> +	drm_mode_config_cleanup(drm);
> +	drm_vblank_cleanup(drm);
> +
> +	return 0;
> +}
> +
> +/* this function is called when all LCDs and dcon have been probed */
> +static int dove_load(struct drm_device *drm, unsigned long flags)
> +{
> +	struct platform_device *pdev = drm->platformdev;
> +	struct dove_lcd *dove_lcd;
> +	int i, ret;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	dove_drm.drm = drm;
> +	platform_set_drvdata(pdev, &dove_drm);
> +	drm->dev_private = &dove_drm;
> +
> +	drm_mode_config_init(drm);
> +
> +/*	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); */
> +
> +	for (i = 0; i < MAX_DOVE_LCD; i++) {
> +		dove_lcd = dove_drm.lcds[i];
> +		if (dove_lcd) {
> +			ret = dove_lcd_init(dove_lcd);
> +			if (ret < 0)
> +				goto fail;
> +			ret = dove_ec_init(dove_lcd);
> +			if (ret < 0)
> +				goto fail;
> +		}
> +	}
> +
> +	drm->mode_config.min_width = 0;
> +	drm->mode_config.min_height = 0;
> +	drm->mode_config.max_width = 2048;
> +	drm->mode_config.max_height = 2048;
> +	drm->mode_config.funcs = &mode_config_funcs;
> +
> +	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
> +	if (ret < 0) {
> +		dev_err(drm->dev, "failed to initialize vblank\n");
> +		goto fail;
> +	}
> +
> +	dove_drm.fbdev = drm_fbdev_cma_init(drm,
> +					32,	/* bpp */
> +					drm->mode_config.num_crtc,
> +					drm->mode_config.num_connector);
> +
> +	drm_kms_helper_poll_init(drm);
> +	return 0;
> +fail:
> +	dove_unload(drm);
> +	return ret;
> +}
> +
> +static void dove_preclose(struct drm_device *drm, struct drm_file *file)
> +{
> +	struct dove_lcd *dove_lcd;
> +	int i;
> +
> +	for (i = 0; i < MAX_DOVE_LCD; i++) {
> +		dove_lcd = dove_drm.lcds[i];
> +		if (dove_lcd)
> +			dove_crtc_cancel_page_flip(dove_lcd, file);
> +	}
> +}
> +
> +static void dove_lastclose(struct drm_device *drm)
> +{
> +	drm_fbdev_cma_restore_mode(dove_drm.fbdev);
> +}
> +
> +static int dove_gem_cma_dumb_create(struct drm_file *file_priv,
> +				struct drm_device *dev,
> +				struct drm_mode_create_dumb *args)
> +{
> +	if (args->height * args->width * args->bpp == 0) {
> +		dev_err(dev->dev, "dumb_create %dx%d bpp %d!\n",
> +			args->height, args->width, args->bpp);
> +		return -ENOMEM;
> +	}
> +	return drm_gem_cma_dumb_create(file_priv, dev, args);
> +}
> +
> +static const struct file_operations fops = {
> +	.owner		= THIS_MODULE,
> +	.open		= drm_open,
> +	.release	= drm_release,
> +	.unlocked_ioctl	= drm_ioctl,
> +	.poll		= drm_poll,
> +	.read		= drm_read,
> +	.fasync		= drm_fasync,
> +	.llseek		= no_llseek,
> +	.mmap		= drm_gem_cma_mmap,
> +};
> +
> +static struct drm_driver dove_driver = {
> +	.driver_features	= DRIVER_GEM | DRIVER_MODESET,
> +	.load			= dove_load,
> +	.unload			= dove_unload,
> +	.preclose		= dove_preclose,
> +	.lastclose		= dove_lastclose,
> +	.get_vblank_counter	= dove_vblank_count,
> +	.enable_vblank		= dove_enable_vblank,
> +	.disable_vblank		= dove_disable_vblank,
> +	.gem_free_object	= drm_gem_cma_free_object,
> +	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> +	.dumb_create		= dove_gem_cma_dumb_create,
> +	.dumb_map_offset	= drm_gem_cma_dumb_map_offset,
> +	.dumb_destroy		= drm_gem_cma_dumb_destroy,
> +#ifdef CONFIG_DEBUG_FS
> +	.debugfs_init		= dove_debugfs_init,
> +	.debugfs_cleanup	= dove_debugfs_cleanup,
> +#endif
> +	.fops			= &fops,
> +
> +	.name			= DRIVER_NAME,
> +	.desc			= DRIVER_DESC,
> +	.date			= DRIVER_DATE,
> +	.major			= DRIVER_MAJOR,
> +	.minor			= DRIVER_MINOR,
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +/*
> + * Power management
> + */
> +static int dove_pm_suspend(struct device *dev)
> +{
> +	struct drm_device *drm = dev_get_drvdata(dev);
> +	struct dove_lcd *dove_lcd;
> +	int i;
> +
> +	drm_kms_helper_poll_disable(drm);
> +	for (i = 0; i < MAX_DOVE_LCD; i++) {
> +		dove_lcd = dove_drm.lcds[i];
> +		if (dove_lcd)
> +			dove_crtc_stop(dove_lcd);
> +	}
> +	return 0;
> +}
> +
> +static int dove_pm_resume(struct device *dev)
> +{
> +	struct drm_device *drm = dev_get_drvdata(dev);
> +	struct dove_lcd *dove_lcd;
> +	int i;
> +
> +	for (i = 0; i < MAX_DOVE_LCD; i++) {
> +		dove_lcd = dove_drm.lcds[i];
> +		if (dove_lcd
> +		 && dove_lcd->dpms == DRM_MODE_DPMS_ON)
> +			dove_crtc_start(dove_lcd);
> +	}
> +	drm_kms_helper_poll_enable(drm);
> +	return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops dove_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(dove_pm_suspend, dove_pm_resume)
> +};
> +
> +/*
> + * Platform driver
> + */
> +
> +/* count the number of awaited sub devices */
> +static int dove_subdev_cnt(void)
> +{
> +	struct device_node *np;
> +	unsigned int n;
> +	static struct of_device_id dove_of_subdev[] = {
> +		{ .compatible = "marvell,dove-lcd" },
> +		{ .compatible = "marvell,dove-dcon" },
> +		{ },
> +	};
> +
> +	n = 0;
> +	np = NULL;
> +	for (;;) {
> +		np = of_find_matching_node_and_match(np,
> +						dove_of_subdev, NULL);
> +		if (!np)
> +			break;
> +		if (of_device_is_available(np))
> +			n++;
> +	}
> +	return n;
> +}
> +
> +int dove_probed(void)
> +{
> +	if (atomic_add_return(1, &probed) == 0)
> +		return drm_platform_init(&dove_driver, g_pdev);
> +	return 0;
> +}
> +
> +static int dove_pdev_probe(struct platform_device *pdev)
> +{
> +	int awaited;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	g_pdev = pdev;
> +
> +	awaited = dove_subdev_cnt();
> +	if (awaited == 0) {
> +		dev_err(&pdev->dev, "no lcd nor dcon devices\n");
> +		return -ENXIO;
> +	}
> +	if (atomic_sub_return(awaited, &probed) == 0)
> +		return drm_platform_init(&dove_driver, pdev);
> +	return 0;
> +}
> +
> +static int dove_pdev_remove(struct platform_device *pdev)
> +{
> +	drm_platform_exit(&dove_driver, pdev);
> +	return 0;
> +}
> +
> +static struct of_device_id dove_of_match[] = {
> +	{ .compatible = "marvell,dove-video" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, dove_of_match);
> +
> +static struct platform_driver dove_platform_driver = {
> +	.probe      = dove_pdev_probe,
> +	.remove     = dove_pdev_remove,
> +	.driver     = {
> +		.owner  = THIS_MODULE,
> +		.name   = "dove-drm",
> +		.pm     = &dove_pm_ops,
> +		.of_match_table = dove_of_match,
> +	},
> +};
> +
> +static int __init dove_drm_init(void)
> +{
> +	int ret;
> +
> +	/* wait for other drivers to be loaded (si5351, tda998x..) */
> +	msleep(200);
> +
> +/* uncomment to activate the drm trace at startup time */
> +/*	drm_debug = DRM_UT_CORE | DRM_UT_DRIVER | DRM_UT_KMS; */
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	ret = platform_driver_register(&dove_lcd_platform_driver);
> +	if (ret < 0)
> +		return ret;
> +	ret = platform_driver_register(&dove_dcon_platform_driver);
> +	if (ret < 0)
> +		goto out1;
> +	ret = platform_driver_register(&dove_platform_driver);
> +	if (ret < 0)
> +		goto out2;
> +	return 0;
> +
> +out2:
> +	platform_driver_unregister(&dove_dcon_platform_driver);
> +out1:
> +	platform_driver_unregister(&dove_lcd_platform_driver);
> +	return ret;
> +}
> +static void __exit dove_drm_fini(void)
> +{
> +	platform_driver_unregister(&dove_platform_driver);
> +	platform_driver_unregister(&dove_dcon_platform_driver);
> +	platform_driver_unregister(&dove_lcd_platform_driver);
> +}
> +module_init(dove_drm_init);
> +module_exit(dove_drm_fini);
> +
> +MODULE_AUTHOR("Jean-Francois Moine <moinejf at free.fr>");
> +MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
> +MODULE_DESCRIPTION("Marvell Dove DRM Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/gpu/drm/dove/dove_drv.h b/drivers/gpu/drm/dove/dove_drv.h
> new file mode 100644
> index 0000000..7488c7e
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_drv.h
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright (C) 2013 Jean-Fran?ois Moine
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __DOVE_DRV_H__
> +#define __DOVE_DRV_H__
> +
> +#include <linux/clk.h>
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_encoder_slave.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +
> +/* (not tested) */
> +/*#define HANDLE_INTERLACE 1*/
> +
> +#define MAX_DOVE_LCD 2		/* max number of dove lcd devices */
> +#define MAX_CLK 4		/* max number of clocks per crtc */
> +
> +#define PLANE_GFX 0
> +#define PLANE_VID 1
> +#define NPLANES 2
> +
> +struct dove_lcd {
> +	void __iomem *mmio;
> +	struct device *dev;
> +	struct drm_crtc crtc;
> +
> +	u8 num;			/* index in dove_drm */
> +	u8 dpms;
> +
> +#ifdef HANDLE_INTERLACE
> +	u8 vblank_enabled;
> +	u32 v_sync0;
> +	u32 v_sync1;
> +#endif
> +
> +	short clk_src;		/* current clock source */
> +	struct clk *clk[MAX_CLK];
> +
> +	int irq;
> +	char name[16];
> +
> +	struct drm_pending_vblank_event *event;
> +
> +	struct drm_plane planes[NPLANES];
> +
> +	struct drm_connector connector;
> +	struct drm_encoder_slave encoder_slave;
> +};
> +
> +struct dove_drm {
> +	struct drm_device *drm;
> +	struct dove_lcd *lcds[MAX_DOVE_LCD];
> +
> +	struct drm_fbdev_cma *fbdev;
> +	int probe_defer;
> +};
> +
> +extern struct dove_drm dove_drm;
> +int dove_probed(void);
> +
> +u32 dove_vblank_count(struct drm_device *dev, int crtc);
> +int dove_enable_vblank(struct drm_device *dev, int crtc);
> +void dove_disable_vblank(struct drm_device *dev, int crtc);
> +int dove_lcd_init(struct dove_lcd *dove_lcd);
> +void dove_crtc_cancel_page_flip(struct dove_lcd *dove_lcd,
> +				struct drm_file *file);
> +void dove_crtc_start(struct dove_lcd *dove_lcd);
> +void dove_crtc_stop(struct dove_lcd *dove_lcd);
> +#ifdef CONFIG_DEBUG_FS
> +int dove_debugfs_init(struct drm_minor *minor);
> +void dove_debugfs_cleanup(struct drm_minor *minor);
> +#endif
> +extern struct platform_driver dove_lcd_platform_driver;
> +
> +int dove_ec_probe(struct dove_lcd *dove_lcd);
> +int dove_ec_init(struct dove_lcd *dove_lcd);
> +extern struct platform_driver dove_dcon_platform_driver;
> +#endif /* __DOVE_DRV_H__ */
> diff --git a/drivers/gpu/drm/dove/dove_ec.c b/drivers/gpu/drm/dove/dove_ec.c
> new file mode 100644
> index 0000000..003b031
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_ec.c
> @@ -0,0 +1,570 @@
> +/*
> + * Marvell Dove DRM driver - encoder / connector and display controller
> + *
> + * Copyright (C) 2013
> + *   Jean-Francois Moine <moinejf at free.fr>
> + *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/i2c.h>
> +#include <linux/of_i2c.h>
> +#include <linux/module.h>
> +
> +#include "dove_drv.h"
> +#include "dove_dcon.h"
> +
> +struct dove_dcon {
> +	void __iomem *mmio;
> +	struct device *dev;
> +};
> +static struct dove_dcon dove_dcon;
> +
> +/* -----------------------------------------------------------------------------
> + * Encoder
> + */
> +/* LVDS and VGA/DAC functions */
> +static void dove_encoder_dpms(struct drm_encoder *encoder, int mode)
> +{
> +}
> +static bool dove_encoder_mode_fixup(struct drm_encoder *encoder,
> +				const struct drm_display_mode *mode,
> +				struct drm_display_mode *adjusted_mode)
> +{
> +	return true;
> +}
> +static void dove_encoder_prepare(struct drm_encoder *encoder)
> +{
> +}
> +static void dove_encoder_commit(struct drm_encoder *encoder)
> +{
> +}
> +static void dove_encoder_mode_set(struct drm_encoder *encoder,
> +				struct drm_display_mode *mode,
> +				struct drm_display_mode *adjusted_mode)
> +{
> +}
> +
> +static const struct drm_encoder_helper_funcs lvds_encoder_helper_funcs = {
> +	.dpms = dove_encoder_dpms,
> +	.mode_fixup = dove_encoder_mode_fixup,
> +	.prepare = dove_encoder_prepare,
> +	.commit = dove_encoder_commit,
> +	.mode_set = dove_encoder_mode_set,
> +};
> +
> +/* HDMI (i2c) functions */
> +static const struct drm_encoder_helper_funcs hdmi_encoder_helper_funcs = {
> +	.dpms = drm_i2c_encoder_dpms,
> +	.mode_fixup = drm_i2c_encoder_mode_fixup,
> +	.prepare = drm_i2c_encoder_prepare,
> +	.commit = drm_i2c_encoder_commit,
> +	.mode_set = drm_i2c_encoder_mode_set,
> +};
> +
> +static void dove_drm_encoder_destroy(struct drm_encoder *encoder)
> +{
> +	struct drm_encoder_slave *encoder_slave = to_encoder_slave(encoder);
> +	struct i2c_client *i2c_client;
> +	struct module *module;
> +
> +	if (encoder_slave->slave_funcs)
> +		encoder_slave->slave_funcs->destroy(encoder);
> +	i2c_client = encoder_slave->bus_priv;
> +	if (i2c_client) {
> +		module = i2c_client->driver->driver.owner;
> +		module_put(module);
> +	}
> +	if (encoder->dev)
> +		drm_encoder_cleanup(encoder);
> +}
> +
> +static const struct drm_encoder_funcs encoder_funcs = {
> +	.destroy = dove_drm_encoder_destroy,
> +};
> +
> +static int dove_encoder_get_hdmi(struct dove_lcd *dove_lcd)
> +{
> +	struct device *dev = dove_lcd->dev;
> +	struct drm_device *drm = dove_drm.drm;
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +	struct drm_encoder *encoder = &encoder_slave->base;
> +	struct drm_connector *connector = &dove_lcd->connector;
> +	struct i2c_client *i2c_client;
> +	struct module *module;
> +	struct drm_i2c_encoder_driver *encoder_drv;
> +	int ret;
> +
> +	i2c_client = encoder_slave->bus_priv;
> +	if (!i2c_client) {
> +		dev_err(dev, "no external-encoder for hdmi\n");
> +		return -EINVAL;
> +	}
> +
> +	encoder_drv = to_drm_i2c_encoder_driver(i2c_client->driver);
> +	if (!encoder_drv || !encoder_drv->encoder_init) {
> +		dev_err(dev, "no external encoder init\n");
> +		return -EINVAL;
> +	}
> +
> +	/* lock the external encoder module */
> +	module = i2c_client->driver->driver.owner;
> +	if (!module || !try_module_get(module)) {
> +		dev_err(dev, "cannot get module %s\n", module->name);
> +		return -EINVAL;
> +	}
> +
> +	ret = encoder_drv->encoder_init(i2c_client, drm, encoder_slave);
> +	if (ret < 0) {
> +		dev_err(dev, "slave encoder init failed\n");
> +		return ret;
> +	}
> +	encoder_slave->slave_funcs->create_resources(encoder, connector);
> +	return ret;
> +}
> +
> +static int dove_encoder_init(struct dove_lcd *dove_lcd,
> +				int mode_encoder)
> +{
> +	struct drm_device *drm = dove_drm.drm;
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +	struct drm_encoder *encoder = &encoder_slave->base;
> +	int ret;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	/* do early init in case of error */
> +	ret = drm_encoder_init(drm, encoder, &encoder_funcs, mode_encoder);
> +	if (ret < 0) {
> +		dev_err(dove_lcd->dev, "drm encoder init failed\n");
> +		return ret;
> +	}
> +
> +	encoder->possible_crtcs = 1 << dove_lcd->num;
> +
> +	/*
> +	 * If the display controller is present,
> +	 * - the port A cannot be VGA/DAC,
> +	 * - the port B can be only VGA/DAC and may receive the lcd 0 output.
> +	 */
> +	if (dove_dcon.mmio) {
> +		if (dove_lcd->num == 0) {
> +			if (mode_encoder == DRM_MODE_ENCODER_DAC) {
> +				dev_err(dove_lcd->dev,
> +						"bad lcd 0 port-type\n");
> +				return -EINVAL;
> +			}
> +		} else {
> +			if (mode_encoder != DRM_MODE_ENCODER_DAC) {
> +				dev_err(dove_lcd->dev,
> +						"bad lcd 1 port-type\n");
> +				return -EINVAL;
> +			}
> +			encoder->possible_crtcs |= 1;
> +
> +			/* the port B may receive the LCD 0 output */
> +			encoder->possible_clones = 1;
> +		}
> +	}
> +
> +	switch (mode_encoder) {
> +	case DRM_MODE_ENCODER_DAC:
> +/*fixme: to do */
> +	case DRM_MODE_ENCODER_LVDS:
> +		drm_encoder_helper_add(encoder, &lvds_encoder_helper_funcs);
> +		ret = 0;
> +		break;
> +	case DRM_MODE_ENCODER_TMDS:
> +		drm_encoder_helper_add(encoder, &hdmi_encoder_helper_funcs);
> +		ret = dove_encoder_get_hdmi(dove_lcd);
> +		break;
> +	}
> +	return ret;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Connector
> + */
> +
> +static int dove_lvds_get_modes(struct dove_lcd *dove_lcd)
> +{
> +	struct device *dev = dove_lcd->dev;
> +	struct device_node *np = dev->of_node;
> +	struct drm_connector *connector = &dove_lcd->connector;
> +	struct drm_display_mode *mode;
> +	int clock, hdisplay, vdisplay, hfp, hbp, vfp, vbp, hs, vs;
> +	int w_mm, h_mm;
> +	int ret;
> +
> +	/* same as of_videomode, but simpler! */
> +	np = of_find_node_by_name(np, "display-timings");
> +	if (!np) {
> +		dev_err(dev, "no display-timings\n");
> +		return -EINVAL;
> +	}
> +	np = of_get_next_child(np, NULL);
> +	if (!np) {
> +		dev_err(dev, "no 'mode' subnode in DT\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = 0;
> +	ret |= of_property_read_u32(np, "hactive", &hdisplay);
> +	ret |= of_property_read_u32(np, "vactive", &vdisplay);
> +	ret |= of_property_read_u32(np, "hfront-porch", &hfp);
> +	ret |= of_property_read_u32(np, "hsync-len", &hs);
> +	ret |= of_property_read_u32(np, "hback-porch", &hbp);
> +	ret |= of_property_read_u32(np, "vfront-porch", &vfp);
> +	ret |= of_property_read_u32(np, "vsync-len", &vs);
> +	ret |= of_property_read_u32(np, "vback-porch", &vbp);
> +	ret |= of_property_read_u32(np, "clock", &clock);
> +	if (ret) {
> +		dev_err(dev, "bad display-timings\n");
> +		return -EINVAL;
> +	}
> +	if (clock < 15000 || clock > 150000) {
> +		dev_err(dev, "bad clock\n");
> +		return -EINVAL;
> +	}
> +
> +	mode = drm_mode_create(dove_drm.drm);
> +	if (!mode) {
> +		ret = -ENOMEM;
> +		return ret;
> +	}
> +
> +	mode->clock = clock;
> +	mode->hdisplay = hdisplay;
> +	mode->hsync_start = hdisplay + hfp;
> +	mode->hsync_end = mode->hsync_start + hs;
> +	mode->htotal = mode->hsync_end + hbp;
> +	mode->vdisplay = vdisplay;
> +	mode->vsync_start = vdisplay + vfp;
> +	mode->vsync_end = mode->vsync_start + vs;
> +	mode->vtotal = mode->vsync_end + vbp;
> +
> +	drm_mode_set_name(mode);
> +	mode->vrefresh = drm_mode_vrefresh(mode);
> +	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
> +	drm_mode_probed_add(connector, mode);
> +
> +	/* optional display dimension */
> +	ret = of_property_read_u32(np, "width-mm", &w_mm);
> +	ret |= of_property_read_u32(np, "height-mm", &h_mm);
> +	if (ret >= 0) {
> +		connector->display_info.width_mm = w_mm;
> +		connector->display_info.height_mm = h_mm;
> +	}
> +	return 1;
> +}
> +
> +static int dove_drm_connector_get_modes(struct drm_connector *connector)
> +{
> +	struct dove_lcd *dove_lcd = 
> +		container_of(connector, struct dove_lcd, connector);
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +	int ret;
> +
> +	switch (connector->connector_type) {
> +	case DRM_MODE_CONNECTOR_VGA:
> +/*fixme:to do */
> +	case DRM_MODE_CONNECTOR_LVDS:
> +		ret = dove_lvds_get_modes(dove_lcd);
> +		break;
> +	default:
> +/*	case DRM_MODE_CONNECTOR_HDMIA: */
> +/*	case DRM_MODE_CONNECTOR_HDMIB: */
> +		ret = encoder_slave->slave_funcs->get_modes(&encoder_slave->base,
> +							connector);
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("-> %d\n", ret);
> +	return ret;
> +}
> +
> +static int dove_drm_connector_mode_valid(struct drm_connector *connector,
> +					  struct drm_display_mode *mode)
> +{
> +	struct dove_lcd *dove_lcd = 
> +		container_of(connector, struct dove_lcd, connector);
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +
> +	if (!encoder_slave->slave_funcs)
> +		return MODE_OK;
> +	return encoder_slave->slave_funcs->mode_valid(&encoder_slave->base,
> +							mode);
> +}
> +
> +static struct drm_encoder *
> +dove_drm_connector_best_encoder(struct drm_connector *connector)
> +{
> +	struct dove_lcd *dove_lcd = 
> +		container_of(connector, struct dove_lcd, connector);
> +
> +	return &dove_lcd->encoder_slave.base;
> +}
> +
> +static const struct drm_connector_helper_funcs connector_helper_funcs = {
> +	.get_modes = dove_drm_connector_get_modes,
> +	.mode_valid = dove_drm_connector_mode_valid,
> +	.best_encoder = dove_drm_connector_best_encoder,
> +};
> +
> +static void dove_drm_connector_destroy(struct drm_connector *connector)
> +{
> +	if (!connector->dev)
> +		return;
> +	drm_sysfs_connector_remove(connector);
> +	drm_connector_cleanup(connector);
> +}
> +
> +static enum drm_connector_status
> +dove_drm_connector_detect(struct drm_connector *connector, bool force)
> +{
> +	struct dove_lcd *dove_lcd = 
> +		container_of(connector, struct dove_lcd, connector);
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +	if (encoder_slave->slave_funcs)
> +		return encoder_slave->slave_funcs->detect(&encoder_slave->base,
> +							connector);
> +/*fixme: KO with VGA*/
> +	return connector_status_connected;
> +}
> +
> +static void dove_drm_connector_dpms(struct drm_connector *connector,
> +				int mode)
> +{
> +	struct dove_lcd *dove_lcd =
> +		container_of(connector, struct dove_lcd, connector);
> +	struct drm_encoder *encoder = connector->encoder;
> +	struct drm_encoder_slave *encoder_slave = to_encoder_slave(encoder);
> +	struct dove_lcd *dove_lcd2 =
> +		container_of(encoder_slave, struct dove_lcd, encoder_slave);
> +	int modeA, modeB;
> +	u32 reg;
> +
> +	if (mode == dove_lcd->connector.dpms)
> +		return;
> +
> +	/* adjust the port B input */
> +	if (dove_dcon.mmio) {
> +		reg = readl(dove_dcon.mmio + DCON_CTL0);
> +		reg &= ~LCD_Port_B_Select_MASK;
> +		if (dove_lcd2 != dove_lcd) {
> +			if (dove_lcd->num == 0) {
> +				modeA = mode;
> +				modeB = dove_lcd2->connector.dpms;
> +			} else {
> +				modeA = dove_lcd->connector.dpms;
> +				modeB = mode;
> +			}
> +
> +			if (modeB == DRM_MODE_DPMS_ON) {
> +				if (modeA == DRM_MODE_DPMS_ON)
> +					reg |= Port_B_Select_A_copy;
> +				else
> +					reg |= Port_B_Select_LCD0;
> +			}
> +		}
> +		writel(reg, dove_dcon.mmio + DCON_CTL0);
> +		DRM_DEBUG_DRIVER("port B select %08x\n", reg);
> +	}
> +
> +	drm_helper_connector_dpms(connector, mode);
> +}
> +
> +static int dove_connector_set_property(struct drm_connector *connector,
> +				struct drm_property *property,
> +				uint64_t value)
> +{
> +	struct dove_lcd *dove_lcd = 
> +		container_of(connector, struct dove_lcd, connector);
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +	if (!encoder_slave->slave_funcs)
> +		return 0;
> +	return encoder_slave->slave_funcs->set_property(&encoder_slave->base,
> +							connector,
> +							property,
> +							value);
> +}
> +
> +static const struct drm_connector_funcs connector_funcs = {
> +	.destroy = dove_drm_connector_destroy,
> +	.dpms = dove_drm_connector_dpms,
> +	.detect = dove_drm_connector_detect,
> +	.fill_modes = drm_helper_probe_single_connector_modes,
> +	.set_property = dove_connector_set_property,
> +};
> +
> +/* initialize the couple connector-encoder of a LCD */
> +int dove_ec_init(struct dove_lcd *dove_lcd)
> +{
> +	struct device *dev = dove_lcd->dev;
> +	struct device_node *np = dev->of_node;
> +	struct drm_device *drm = dove_drm.drm;
> +	struct drm_connector *connector = &dove_lcd->connector;
> +	struct drm_encoder_slave *encoder_slave = &dove_lcd->encoder_slave;
> +	struct drm_encoder *encoder = &encoder_slave->base;
> +	u32 port_type;
> +	int mode_encoder, ret;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	/* get the port (connector) type */
> +	if (of_property_read_u32(np, "marvell,port-type", &port_type)) {
> +		dev_err(dev, "no port-type\n");
> +		return -EINVAL;
> +	}
> +	switch (port_type) {
> +	case DRM_MODE_CONNECTOR_VGA:		/* 1 */
> +		mode_encoder = DRM_MODE_ENCODER_DAC;
> +		break;
> +	case DRM_MODE_CONNECTOR_LVDS:		/* 7 */
> +		mode_encoder = DRM_MODE_ENCODER_LVDS;
> +		break;
> +	case DRM_MODE_CONNECTOR_HDMIA:		/* 11 */
> +	case DRM_MODE_CONNECTOR_HDMIB:		/* 12 */
> +		mode_encoder = DRM_MODE_ENCODER_TMDS;
> +		break;
> +	default:
> +		dev_err(dev, "bad port type %d\n", port_type);
> +		return -EINVAL;
> +	}
> +
> +	ret = drm_connector_init(drm, connector, &connector_funcs, port_type);
> +	if (ret < 0)
> +		return ret;
> +
> +	drm_connector_helper_add(connector, &connector_helper_funcs);
> +
> +#ifdef HANDLE_INTERLACE
> +	connector->interlace_allowed = true;
> +#endif
> +
> +	ret = dove_encoder_init(dove_lcd, mode_encoder);
> +	if (ret < 0)
> +		goto err;
> +
> +	ret = drm_mode_connector_attach_encoder(connector, encoder);
> +	if (ret < 0)
> +		goto err;
> +
> +	connector->encoder = encoder;
> +
> +	ret = drm_sysfs_connector_add(connector);
> +	if (ret < 0)
> +		goto err;
> +
> +	drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
> +	ret = drm_object_property_set_value(&connector->base,
> +					drm->mode_config.dpms_property,
> +					DRM_MODE_DPMS_OFF);
> +	if (ret < 0)
> +		goto err;
> +	return 0;
> +
> +err:
> +	dev_err(dev, "dove_ec_init err %d\n", ret);
> +	dove_drm_encoder_destroy(&encoder_slave->base);
> +	drm_connector_cleanup(connector);
> +	return ret;
> +}
> +
> +/* at probe time, check the presence of a possible external slave encoder */
> +int dove_ec_probe(struct dove_lcd *dove_lcd)
> +{
> +	struct device *dev = dove_lcd->dev;
> +	struct device_node *np = dev->of_node;
> +	struct device_node *i2c_node;
> +	struct i2c_client *i2c_client;
> +
> +	/* get the optional external encoder */
> +	i2c_node = of_parse_phandle(np, "marvell,external-encoder", 0);
> +	if (!i2c_node)
> +		return 0;
> +
> +	i2c_client = of_find_i2c_device_by_node(i2c_node);
> +	of_node_put(i2c_node);
> +	if (!i2c_client) {
> +		dev_err(dev, "bad external-encoder\n");
> +		return -EINVAL;
> +	}
> +
> +	/* check if the slave-encoder module is initialized */
> +	if (!i2c_client->driver) {
> +		if (dove_drm.probe_defer) {
> +			dev_err(dev, "cannot get the external-encoder\n");
> +			return -EINVAL;
> +		}
> +		dove_drm.probe_defer = 1;
> +		return -EPROBE_DEFER;
> +	}
> +
> +	dove_lcd->encoder_slave.bus_priv = i2c_client;
> +	return 0;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Display controller
> + */
> +
> +static int dove_dcon_remove(struct platform_device *pdev)
> +{
> +	dove_dcon.mmio = NULL;
> +	return 0;
> +}
> +
> +static int dove_dcon_probe(struct platform_device *pdev)
> +{
> +	struct resource *res;
> +	void __iomem *mmio;
> +
> +	DRM_DEBUG_DRIVER("\n");
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(&pdev->dev, "failed to get dcon resource\n");
> +		return -EINVAL;
> +	}
> +
> +	mmio = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(mmio)) {
> +		dev_err(&pdev->dev, "failed map dcon registers\n");
> +		return PTR_ERR(mmio);
> +	}
> +
> +	dove_dcon.mmio = mmio;
> +	dove_dcon.dev = &pdev->dev;
> +
> +	/* init done, try to initialize the drm driver */
> +	return dove_probed();
> +}
> +
> +static struct of_device_id dove_dcon_of_match[] = {
> +	{ .compatible = "marvell,dove-dcon" },
> +	{ },
> +};
> +struct platform_driver dove_dcon_platform_driver = {
> +	.driver     = {
> +		.owner  = THIS_MODULE,
> +		.name   = "dove-dcon",
> +		.of_match_table = dove_dcon_of_match,
> +	},
> +	.probe      = dove_dcon_probe,
> +	.remove     = dove_dcon_remove,
> +};
> diff --git a/drivers/gpu/drm/dove/dove_lcd.h b/drivers/gpu/drm/dove/dove_lcd.h
> new file mode 100644
> index 0000000..03b198b
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_lcd.h
> @@ -0,0 +1,519 @@
> +/*
> + * LCD controller registers of Marvell DOVE
> + *
> + * Copyright (C) 2013
> + *   Jean-Francois Moine <moinejf at free.fr>
> + *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef _DOVE_LCD_H_
> +#define	_DOVE_LCD_H_
> +
> +/* ------------< LCD register >------------ */
> +
> +/* Video Frame 0&1 start address registers */
> +#define	LCD_TV_CONTROL1			0x0084
> +#define   VSYNC_L_OFFSET(o)			((o) << 20)
> +#define   VSYNC_L_OFFSET_MASK			(0xfff << 20)
> +#define   HWC32_ENABLE				BIT(13)
> +#define   VSYNC_OFFSET_EN			BIT(12)
> +#define   VSYNC_H_OFFSET(o)			(o)
> +#define   VSYNC_H_OFFSET_MASK			0xfff
> +
> +/* Video Frame 0&1 start address registers */
> +#define	LCD_SPU_DMA_START_ADDR_Y0	0x00c0
> +#define	LCD_SPU_DMA_START_ADDR_U0	0x00c4
> +#define	LCD_SPU_DMA_START_ADDR_V0	0x00c8
> +#define LCD_CFG_DMA_START_ADDR_0	0x00cc /* Cmd address */
> +#define	LCD_SPU_DMA_START_ADDR_Y1	0x00d0
> +#define	LCD_SPU_DMA_START_ADDR_U1	0x00d4
> +#define	LCD_SPU_DMA_START_ADDR_V1	0x00d8
> +#define LCD_CFG_DMA_START_ADDR_1	0x00dc /* Cmd address */
> +
> +/* YC & UV Pitch */
> +#define LCD_SPU_DMA_PITCH_YC		0x00e0
> +#define   LCD_Y_C(y, c)				(((c) << 16) | (y))
> +#define LCD_SPU_DMA_PITCH_UV		0x00e4
> +#define   LCD_U_V(u, v)				(((v) << 16) | (u))
> +
> +/* Video Starting Point on Screen Register */
> +#define LCD_SPUT_DMA_OVSA_HPXL_VLN	0x00e8
> +
> +/* Video Size Register */
> +#define LCD_SPU_DMA_HPXL_VLN		0x00ec
> +
> +/* Video Size After zooming Register */
> +#define LCD_SPU_DZM_HPXL_VLN		0x00f0
> +
> +/* Graphic Frame 0&1 Starting Address Register */
> +#define LCD_CFG_GRA_START_ADDR0		0x00f4
> +#define LCD_CFG_GRA_START_ADDR1		0x00f8
> +
> +/* Graphic Frame Pitch */
> +#define LCD_CFG_GRA_PITCH		0x00fc
> +
> +/* Graphic Starting Point on Screen Register */
> +#define LCD_SPU_GRA_OVSA_HPXL_VLN	0x0100
> +
> +/* Graphic Size Register */
> +#define LCD_SPU_GRA_HPXL_VLN		0x0104
> +
> +/* Graphic Size after Zooming Register */
> +#define LCD_SPU_GZM_HPXL_VLN		0x0108
> +
> +/* HW Cursor Starting Point on Screen Register */
> +#define LCD_SPU_HWC_OVSA_HPXL_VLN	0x010c
> +
> +/* HW Cursor Size */
> +#define LCD_SPU_HWC_HPXL_VLN		0x0110
> +
> +/* Total Screen Size Register */
> +#define LCD_SPUT_V_H_TOTAL		0x0114
> +
> +/* Total Screen Active Size Register */
> +#define LCD_SPU_V_H_ACTIVE		0x0118
> +#define   LCD_H_V(h, v)				(((v) << 16) | (h))
> +#define   H_LCD(x)				((x) & 0xffff)
> +#define   V_LCD(x)				(((x) >> 16) & 0xffff)
> +
> +/* Screen H&V Porch Register */
> +#define LCD_SPU_H_PORCH			0x011c
> +#define LCD_SPU_V_PORCH			0x0120
> +#define   LCD_F_B(f, b)				(((b) << 16) | (f))
> +#define   F_LCD(x)				((x) & 0xffff)
> +#define   B_LCD(x)				(((x) >> 16) & 0xffff)
> +
> +/* Screen Blank Color Register */
> +#define LCD_SPU_BLANKCOLOR		0x0124
> +
> +/* HW Cursor Color 1&2 Register */
> +#define LCD_SPU_ALPHA_COLOR1		0x0128
> +#define   HWC32_CFG_ALPHA(alpha)		((alpha) << 24)
> +#define LCD_SPU_ALPHA_COLOR2		0x012c
> +#define   COLOR_MASK				0x00ffffff
> +#define   COLOR_RGB(r, g, b) (((b) << 16) | ((g) << 8) | (r))
> +
> +/* Video YUV Color Key Control */
> +#define LCD_SPU_COLORKEY_Y		0x0130
> +#define   CFG_CKEY_Y2(y2)			((y2) << 24)
> +#define   CFG_CKEY_Y2_MASK			0xff000000
> +#define   CFG_CKEY_Y1(y1)			((y1) << 16)
> +#define   CFG_CKEY_Y1_MASK			0x00ff0000
> +#define   CFG_CKEY_Y(y)				((y) << 8)
> +#define   CFG_CKEY_Y_MASK			0x0000ff00
> +#define   CFG_ALPHA_Y(y)			(y)
> +#define   CFG_ALPHA_Y_MASK			0x000000ff
> +#define LCD_SPU_COLORKEY_U		0x0134
> +#define   CFG_CKEY_U2(u2)			((u2) << 24)
> +#define   CFG_CKEY_U2_MASK			0xff000000
> +#define   CFG_CKEY_U1(u1)			((u1) << 16)
> +#define   CFG_CKEY_U1_MASK			0x00ff0000
> +#define   CFG_CKEY_U(u)				((u) << 8)
> +#define   CFG_CKEY_U_MASK			0x0000ff00
> +#define   CFG_ALPHA_U(u)			(u)
> +#define   CFG_ALPHA_U_MASK			0x000000ff
> +#define LCD_SPU_COLORKEY_V		0x0138
> +#define   CFG_CKEY_V2(v2)			((v2) << 24)
> +#define   CFG_CKEY_V2_MASK			0xff000000
> +#define   CFG_CKEY_V1(v1)			((v1) << 16)
> +#define   CFG_CKEY_V1_MASK			0x00ff0000
> +#define   CFG_CKEY_V(v)				((v) << 8)
> +#define   CFG_CKEY_V_MASK			0x0000ff00
> +#define   CFG_ALPHA_V(v)			(v)
> +#define   CFG_ALPHA_V_MASK			0x000000ff
> +
> +/* LCD General Configuration Register */
> +#define LCD_CFG_RDREG4F			0x013c
> +#define   LCD_SRAM_WAIT				BIT(11)
> +#define   DMA_WATERMARK_MASK			0xff
> +#define   DMA_WATERMARK(m)			(m)
> +
> +/* SPI Read Data Register */
> +#define LCD_SPU_SPI_RXDATA		0x0140
> +
> +/* Smart Panel Read Data Register */
> +#define LCD_SPU_ISA_RSDATA		0x0144
> +#define   ISA_RXDATA_16BIT_1_DATA_MASK		0x000000ff
> +#define   ISA_RXDATA_16BIT_2_DATA_MASK		0x0000ff00
> +#define   ISA_RXDATA_16BIT_3_DATA_MASK		0x00ff0000
> +#define   ISA_RXDATA_16BIT_4_DATA_MASK		0xff000000
> +#define   ISA_RXDATA_32BIT_1_DATA_MASK		0x00ffffff
> +
> +/* HWC SRAM Read Data Register */
> +#define LCD_SPU_HWC_RDDAT		0x0158
> +
> +/* Gamma Table SRAM Read Data Register */
> +#define LCD_SPU_GAMMA_RDDAT		0x015c
> +#define   GAMMA_RDDAT_MASK			0x000000ff
> +
> +/* Palette Table SRAM Read Data Register */
> +#define LCD_SPU_PALETTE_RDDAT		0x0160
> +#define   PALETTE_RDDAT_MASK			0x00ffffff
> +
> +/* I/O Pads Input Read Only Register */
> +#define LCD_SPU_IOPAD_IN		0x0178
> +#define   IOPAD_IN_MASK				0x0fffffff
> +
> +/* Reserved Read Only Registers */
> +#define LCD_CFG_RDREG5F			0x017c
> +#define   IRE_FRAME_CNT_MASK			0x000000c0
> +#define   IPE_FRAME_CNT_MASK			0x00000030
> +#define   GRA_FRAME_CNT_MASK			0x0000000c	/* Graphic */
> +#define   DMA_FRAME_CNT_MASK			0x00000003	/* Video */
> +
> +/* SPI Control Register. */
> +#define LCD_SPU_SPI_CTRL		0x0180
> +#define   CFG_SCLKCNT(div)			((div) << 24)
> +#define   CFG_SCLKCNT_MASK			0xff000000
> +#define   CFG_RXBITS(rx)			((rx) << 16)
> +#define   CFG_RXBITS_MASK			0x00ff0000
> +#define   CFG_TXBITS(tx)			((tx) << 8)
> +#define   CFG_TXBITS_MASK			0x0000ff00
> +#define   CFG_CLKINV				BIT(7)
> +#define   CFG_KEEPXFER				BIT(6)
> +#define   CFG_RXBITSTO0				BIT(5)
> +#define   CFG_TXBITSTO0				BIT(4)
> +#define   CFG_SPI_ENA				BIT(3)
> +#define   CFG_SPI_SEL				BIT(2)
> +#define   CFG_SPI_3W4WB				BIT(1)
> +#define   CFG_SPI_START				BIT(0)
> +
> +/* SPI Tx Data Register */
> +#define LCD_SPU_SPI_TXDATA		0x0184
> +
> +/*
> + *  1. Smart Pannel 8-bit Bus Control Register.
> + *  2. AHB Slave Path Data Port Register
> + */
> +#define LCD_SPU_SMPN_CTRL		0x0188
> +
> +/* DMA Control 0 Register */
> +#define LCD_SPU_DMA_CTRL0		0x0190
> +#define   CFG_NOBLENDING			BIT(31)
> +#define   CFG_GAMMA_ENA				BIT(30)
> +#define   CFG_CBSH_ENA				BIT(29)
> +#define   CFG_PALETTE_ENA			BIT(28)
> +#define   CFG_ARBFAST_ENA			BIT(27)
> +#define   CFG_HWC_1BITMOD			BIT(26)
> +#define   CFG_HWC_1BITENA			BIT(25)
> +#define   CFG_HWC_ENA				BIT(24)
> +#define   CFG_DMAFORMAT(dmaformat)		((dmaformat) << 20)
> +#define   CFG_DMAFORMAT_MASK			0x00f00000
> +#define   CFG_GRAFORMAT(graformat)		((graformat) << 16)
> +#define   CFG_GRAFORMAT_MASK			0x000f0000
> +/* for graphic part */
> +#define   CFG_GRA_FTOGGLE			BIT(15)
> +#define   CFG_GRA_HSMOOTH			BIT(14)
> +#define   CFG_GRA_TSTMODE			BIT(13)
> +#define   CFG_GRA_SWAPRB			BIT(12)
> +#define   CFG_GRA_SWAPUV			BIT(11)
> +#define   CFG_GRA_SWAPYU			BIT(10)
> +#define   CFG_YUV2RGB_GRA			BIT(9)
> +#define   CFG_GRA_ENA				BIT(8)
> +/* for video part */
> +#define   CFG_DMA_FTOGGLE			BIT(7)
> +#define   CFG_DMA_HSMOOTH			BIT(6)
> +#define   CFG_DMA_TSTMODE			BIT(5)
> +#define   CFG_DMA_SWAPRB			BIT(4)
> +#define   CFG_DMA_SWAPUV			BIT(3)
> +#define   CFG_DMA_SWAPYU			BIT(2)
> +#define   CFG_DMA_SWAP_MASK			0x0000001c
> +#define   CFG_YUV2RGB_DMA			BIT(1)
> +#define   CFG_DMA_ENA				BIT(0)
> +
> +/* DMA Control 1 Register */
> +#define LCD_SPU_DMA_CTRL1		0x0194
> +#define   CFG_FRAME_TRIG			BIT(31)
> +#define   CFG_VSYNC_TRIG(trig)			((trig) << 28)
> +#define   CFG_VSYNC_TRIG_MASK			0x70000000
> +#define   CFG_VSYNC_INV				BIT(27)
> +#define   CFG_COLOR_KEY_MODE(cmode)		((cmode) << 24)
> +#define   CFG_COLOR_KEY_MASK			0x07000000
> +#define   CFG_CARRY				BIT(23)
> +#define   CFG_GATED_ENA				BIT(21)
> +#define   CFG_PWRDN_ENA				BIT(20)
> +#define   CFG_DSCALE(dscale)			((dscale) << 18)
> +#define   CFG_DSCALE_MASK			0x000c0000
> +#define   CFG_ALPHA_MODE(amode)			((amode) << 16)
> +#define   CFG_ALPHA_MODE_MASK			0x00030000
> +#define   CFG_ALPHA(alpha)			((alpha) << 8)
> +#define   CFG_ALPHA_MASK			0x0000ff00
> +#define   CFG_PXLCMD(pxlcmd)			(pxlcmd)
> +#define   CFG_PXLCMD_MASK			0x000000ff
> +
> +/* SRAM Control Register */
> +#define LCD_SPU_SRAM_CTRL		0x0198
> +#define   CFG_SRAM_INIT_WR_RD(mode)		((mode) << 14)
> +#define   CFG_SRAM_INIT_WR_RD_MASK		0x0000c000
> +#define   CFG_SRAM_ADDR_LCDID(id)		((id) << 8)
> +#define   CFG_SRAM_ADDR_LCDID_MASK		0x00000f00
> +#define   CFG_SRAM_ADDR(addr)			(addr)
> +#define   CFG_SRAM_ADDR_MASK			0x000000ff
> +
> +/* SRAM Write Data Register */
> +#define LCD_SPU_SRAM_WRDAT		0x019c
> +
> +/* SRAM RTC/WTC Control Register */
> +#define LCD_SPU_SRAM_PARA0		0x01a0
> +
> +/* SRAM Power Down Control Register */
> +#define LCD_SPU_SRAM_PARA1		0x01a4
> +#define   CFG_CSB_256x32			BIT(15)		/* HWC */
> +#define   CFG_CSB_256x24			BIT(14)		/* Palette */
> +#define   CFG_CSB_256x8				BIT(13)		/* Gamma */
> +#define   CFG_PDWN256x32			BIT(7)		/* HWC */
> +#define   CFG_PDWN256x24			BIT(6)		/* Palette */
> +#define   CFG_PDWN256x8				BIT(5)		/* Gamma */
> +#define   CFG_PDWN32x32				BIT(3)
> +#define   CFG_PDWN16x66				BIT(2)
> +#define   CFG_PDWN32x66				BIT(1)
> +#define   CFG_PDWN64x66				BIT(0)
> +
> +/* Smart or Dumb Panel Clock Divider */
> +#define LCD_CFG_SCLK_DIV		0x01a8
> +#define   SET_SCLK(src, div, frac) (((src) << 30) | ((frac) << 16 ) | (div))
> +
> +/* Video Contrast Register */
> +#define LCD_SPU_CONTRAST		0x01ac
> +#define   CFG_BRIGHTNESS(bright)		((bright) << 16)
> +#define   CFG_BRIGHTNESS_MASK			0xffff0000
> +#define   CFG_CONTRAST(contrast)		(contrast)
> +#define   CFG_CONTRAST_MASK			0x0000ffff
> +
> +/* Video Saturation Register */
> +#define LCD_SPU_SATURATION		0x01b0
> +#define   CFG_C_MULTS(mult)			((mult) << 16)
> +#define   CFG_C_MULTS_MASK			0xffff0000
> +#define   CFG_SATURATION(sat)			(sat)
> +#define   CFG_SATURATION_MASK			0x0000ffff
> +
> +/* Video Hue Adjust Register */
> +#define LCD_SPU_CBSH_HUE		0x01b4
> +#define   CFG_SIN0(sin0)			((sin0) << 16)
> +#define   CFG_SIN0_MASK				0xffff0000
> +#define   CFG_COS0(con0)			(con0)
> +#define   CFG_COS0_MASK				0x0000ffff
> +
> +/* Dump LCD Panel Control Register */
> +#define LCD_SPU_DUMB_CTRL		0x01b8
> +#define   CFG_DUMBMODE(mode)			((mode) << 28)
> +#define   CFG_DUMBMODE_MASK			0xf0000000
> +#define   CFG_LCDGPIO_O(data)			((data) << 20)
> +#define   CFG_LCDGPIO_O_MASK			0x0ff00000
> +#define   CFG_LCDGPIO_ENA(gpio)			((gpio) << 12)
> +#define   CFG_LCDGPIO_ENA_MASK			0x000ff000
> +#define   CFG_BIAS_OUT				BIT(8)
> +#define   CFG_REVERSE_RGB			BIT(7)
> +#define   CFG_INV_COMPBLANK			BIT(6)
> +#define   CFG_INV_COMPSYNC			BIT(5)
> +#define   CFG_INV_HENA				BIT(4)
> +#define   CFG_INV_VSYNC				BIT(3)
> +#define   CFG_INV_HSYNC				BIT(2)
> +#define   CFG_INV_PCLK				BIT(1)
> +#define   CFG_DUMB_ENA				BIT(0)
> +
> +/* LCD I/O Pads Control Register */
> +#define SPU_IOPAD_CONTROL		0x01bc
> +#define   CFG_VSC_LINEAR(vm)			((vm) << 18)	/* gfx */
> +#define   CFG_VSC_LINEAR_MASK			0x000c0000
> +#define   CFG_GRA_VM_ENA			BIT(15)		/* gfx */
> +#define   CFG_DMA_VM_ENA			BIT(14)		/* video */
> +#define   CFG_CMD_VM_ENA			BIT(13)
> +#define   CFG_CSC(csc)				((csc) << 8)
> +#define   CFG_CSC_MASK				0x00000300
> +#define   CFG_AXICTRL(axi)			((axi) << 4)
> +#define   CFG_AXICTRL_MASK			0x000000f0
> +#define   CFG_IOPADMODE(iopad)			(iopad)
> +#define   CFG_IOPADMODE_MASK			0x0000000f
> +
> +/* LCD Interrupt Control Register */
> +#define SPU_IRQ_ENA			0x1c0
> +/* LCD Interrupt Status Register */
> +#define SPU_IRQ_ISR			0x1c4
> +#define   IRQ_DMA_FRAME0			BIT(31)
> +#define   IRQ_DMA_FRAME1			BIT(30)
> +#define   IRQ_DMA_FIFO_UNDERFLOW		BIT(29)
> +#define   IRQ_GRA_FRAME0			BIT(27)
> +#define   IRQ_GRA_FRAME1			BIT(26)
> +#define   IRQ_GRA_FIFO_UNDERFLOW		BIT(25)
> +#define   IRQ_SMART_VSYNC			BIT(23)
> +#define   IRQ_DUMB_FRAME_DONE			BIT(22)
> +#define   IRQ_SMART_FRAME_DONE			BIT(21)
> +#define   IRQ_HWCURSOR_FRAME_DONE		BIT(20)
> +#define   IRQ_AHB_CMD_EMPTY			BIT(19)
> +#define   IRQ_SPI_TRANSFER_DONE			BIT(18)
> +#define   IRQ_POWERDOWN				BIT(17)
> +#define   IRQ_AXI_ERROR				BIT(16)
> +/* read only status */
> +#define   STA_DMA_FRAME0			BIT(15)
> +#define   STA_DMA_FRAME1			BIT(14)
> +#define   STA_DMA_FRAME_COUNT(x) (((x) & (BIT(13) | BIT(12))) >> 12)
> +#define   STA_GRA_FRAME0			BIT(11)
> +#define   STA_GRA_FRAME1			BIT(10)
> +#define   STA_GRA_FRAME_COUNT(x) (((x) & (BIT(9) | BIT(8))) >> 8)
> +#define   STA_SMART_VSYNC			BIT(7)
> +#define   STA_DUMB_FRAME_DONE			BIT(6)
> +#define   STA_SMART_FRAME_DONE			BIT(5)
> +#define   STA_HWCURSOR_FRAME_DONE		BIT(4)
> +#define   STA_AHB_CMD_EMPTY			BIT(3)
> +#define   STA_DMA_FIFO_EMPTY			BIT(2)
> +#define   STA_GRA_FIFO_EMPTY			BIT(1)
> +#define   STA_POWERDOWN				BIT(0)
> +
> +#define IRQ_DMA_FRAME_DONE			(IRQ_DMA_FRAME0 | IRQ_DMA_FRAME1)
> +#define IRQ_GRA_FRAME_DONE \
> +			(IRQ_GRA_FRAME0 | IRQ_GRA_FRAME1 | IRQ_SMART_VSYNC)
> +
> +/*
> + * defined Video Memory Color format for DMA control 0 register
> + * DMA0 bit[23:20]
> + */
> +#define VMODE_RGB565		0x0
> +#define VMODE_RGB1555		0x1
> +#define VMODE_RGB888PACKED	0x2
> +#define VMODE_RGB888UNPACKED	0x3
> +#define VMODE_RGBA888		0x4
> +#define VMODE_YUV422PACKED	0x5
> +#define VMODE_YUV422PLANAR	0x6
> +#define VMODE_YUV420PLANAR	0x7
> +#define VMODE_SMPNCMD		0x8
> +#define VMODE_PALETTE4BIT	0x9
> +#define VMODE_PALETTE8BIT	0xa
> +#define VMODE_RESERVED		0xb
> +
> +/*
> + * defined Graphic Memory Color format for DMA control 0 register
> + * DMA0 bit[19:16]
> + */
> +#define GMODE_RGB565		0x0
> +#define GMODE_RGB1555		0x1
> +#define GMODE_RGB888PACKED	0x2
> +#define GMODE_RGB888UNPACKED	0x3
> +#define GMODE_RGBA888		0x4
> +#define GMODE_YUV422PACKED	0x5
> +#define GMODE_YUV422PLANAR	0x6
> +#define GMODE_YUV420PLANAR	0x7
> +#define GMODE_SMPNCMD		0x8
> +#define GMODE_PALETTE4BIT	0x9
> +#define GMODE_PALETTE8BIT	0xa
> +#define GMODE_RESERVED		0xb
> +
> +/*
> + * define for DMA control 1 register
> + */
> +#define DMA1_FRAME_TRIG		31	/* bit location */
> +#define DMA1_VSYNC_MODE		28
> +#define DMA1_VSYNC_INV		27
> +#define DMA1_CKEY		24
> +#define DMA1_CARRY		23
> +#define DMA1_LNBUF_ENA		22
> +#define DMA1_GATED_ENA		21
> +#define DMA1_PWRDN_ENA		20
> +#define DMA1_DSCALE		18
> +#define DMA1_ALPHA_MODE		16
> +#define DMA1_ALPHA		 8
> +#define DMA1_PXLCMD		 0
> +
> +/*
> + * defined for Configure Dumb Mode
> + * DUMB LCD Panel bit[31:28]
> + */
> +#define DUMB16_RGB565_0		0x0
> +#define DUMB16_RGB565_1		0x1
> +#define DUMB18_RGB666_0		0x2
> +#define DUMB18_RGB666_1		0x3
> +#define DUMB12_RGB444_0		0x4
> +#define DUMB12_RGB444_1		0x5
> +#define DUMB24_RGB888_0		0x6
> +#define DUMB_BLANK		0x7
> +
> +/*
> + * defined for Configure I/O Pin Allocation Mode
> + * LCD LCD I/O Pads control register bit[3:0]
> + */
> +#define IOPAD_DUMB24		0x0
> +#define IOPAD_DUMB18SPI		0x1
> +#define IOPAD_DUMB18GPIO	0x2
> +#define IOPAD_DUMB16SPI		0x3
> +#define IOPAD_DUMB16GPIO	0x4
> +#define IOPAD_DUMB12		0x5
> +#define IOPAD_SMART18SPI	0x6
> +#define IOPAD_SMART16SPI	0x7
> +#define IOPAD_SMART8BOTH	0x8
> +
> +/*
> + * clock source SCLK_Source bit[31:30]
> + */
> +#define SCLK_SRC_AXI 0
> +#define SCLK_SRC_EXTCLK0 1
> +#define SCLK_SRC_PLLDIV 2
> +#define SCLK_SRC_EXTCLK1 3
> +
> +/*
> + * defined Dumb Panel Clock Divider register
> + * SCLK_Source bit[31]
> + */
> +#define AXI_BUS_SEL		0x80000000	/* 0: PLL clock select*/
> +#define CCD_CLK_SEL		0x40000000
> +#define DCON_CLK_SEL		0x20000000
> +#define IDLE_CLK_INT_DIV	0x1		/* idle Integer Divider */
> +#define DIS_CLK_INT_DIV		0x0		/* Disable Integer Divider */
> +
> +/* SRAM ID */
> +#define SRAMID_GAMMA_YR		0x0
> +#define SRAMID_GAMMA_UG		0x1
> +#define SRAMID_GAMMA_VB		0x2
> +#define SRAMID_PALETTE		0x3
> +#define SRAMID_HWC32_RAM1	0xc
> +#define SRAMID_HWC32_RAM2	0xd
> +#define SRAMID_HWC32_RAM3	0xe
> +#define SRAMID_HWC		0xf
> +
> +/* SRAM INIT Read/Write */
> +#define SRAMID_INIT_READ	0x0
> +#define SRAMID_INIT_WRITE	0x2
> +#define SRAMID_INIT_DEFAULT	0x3
> +
> +/*
> + * defined VSYNC selection mode for DMA control 1 register
> + * DMA1 bit[30:28]
> + */
> +#define VMODE_SMPN		0x0
> +#define VMODE_SMPNIRQ		0x1
> +#define VMODE_DUMB		0x2
> +#define VMODE_IPE		0x3
> +#define VMODE_IRE		0x4
> +
> +/*
> + * defined Configure Alpha and Alpha mode for DMA control 1 register
> + * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode)
> + */
> +/* ALPHA mode */
> +#define MODE_ALPHA_DMA		0xa0
> +#define MODE_ALPHA_GRA		0x1
> +#define MODE_ALPHA_CFG		0x2
> +
> +/* alpha value */
> +#define ALPHA_NOGRAPHIC		0xff	/* all video, no graphic */
> +#define ALPHA_NOVIDEO		0x00	/* all graphic, no video */
> +#define ALPHA_GRAPHnVIDEO	0x0f	/* Selects graphic & video */
> +
> +/*
> + * defined Pixel Command for DMA control 1 register
> + * DMA1 bit[07:00]
> + */
> +#define PIXEL_CMD		0x81
> +
> +#endif /* _DOVE_LCD_H_ */
> 
> 
> -- 
> Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
> Jef		|		http://moinejf.free.fr/
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From moinejf at free.fr  Thu May 16 11:49:16 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Thu, 16 May 2013 17:49:16 +0200
Subject: [PATCH v2] clk: si5351: declare all device IDs for module loading
Message-ID: <20130516174916.2daa49b6@armhf>

When the si5351 driver is a kernel module, it is loaded into memory
from its i2c device IDs, but not from its DT compatible properties.

This patch declares the i2c device IDs of all chip variants.

Signed-off-by: Jean-Francois Moine <moinejf at free.fr>
---
v2: subject change - was "ARM: dove: ..."
--- 
 drivers/clk/clk-si5351.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 8927284..9ebdddd 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1490,7 +1490,10 @@ static int si5351_i2c_probe(struct i2c_client *client,
 }
 
 static const struct i2c_device_id si5351_i2c_ids[] = {
-	{ "silabs,si5351", 0 },
+	{ "si5351a", 0 },
+	{ "si5351a-msop", 0 },
+	{ "si5351b", 0 },
+	{ "si5351c", 0 },
 	{ }
 };
 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);


-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From thomas.petazzoni at free-electrons.com  Thu May 16 11:49:03 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:49:03 +0200
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <20130516154031.GF6563@titan.lakedaemon.net>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130516093312.GB2459@localhost>
 <20130516154031.GF6563@titan.lakedaemon.net>
Message-ID: <20130516174903.3a7a07ef@skate>

Dear Jason Cooper,

On Thu, 16 May 2013 11:40:31 -0400, Jason Cooper wrote:

> > > +static int mvebu_pcie_init(void)
> > 
> > Building this showed a warning here. It seems you forgot
> > to mark this one as __init.
> 
> Thomas, I'll fix this up when I pull this in, no need to resend. :)

I'll resend, because beyond this function pointed by Ezequiel, there
are two other functions that can be marked __init. The one pointed by
Ezequiel is important because it causes a section mismatch
when !CONFIG_MODULES, because in this case platform_driver_probe() is
__init (and this explains what I wasn't seeing the warning, since I'm
building CONFIG_MODULES=y). The two other functions are more cosmetic,
but good to have as well.

It would already been sent if git hadn't decided to do a 'git gc' right
after my rebase. It's been gc-ing for quite some time now...

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From tony at atomide.com  Thu May 16 11:49:52 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 08:49:52 -0700
Subject: [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values
In-Reply-To: <1366388981.3928.158.camel@mars>
References: <5170738F.8050305@ti.com> <1366325282.4232.6.camel@lovely>
 <51708097.6070102@ti.com> <51708131.2040208@ti.com>
 <1366362081.3928.18.camel@mars> <1366372957.3928.104.camel@mars>
 <51714E0D.7020304@ti.com> <1366383208.3928.144.camel@mars>
 <5171647B.9070108@ti.com> <1366388981.3928.158.camel@mars>
Message-ID: <20130516154952.GT5600@atomide.com>

* Christoph Fritz <chf.fritz at googlemail.com> [130419 09:34]:
> This patch removes omap2_nand_gpmc_retime() which was used to quirk
> some timing values before gpmc_cs_set_timings(). Due to recent changes,
> gpmc_cs_set_timings() has evolved so that there is no more need for a
> retime function.
> 
> To keep the gpmc configuration consistent for legacy board files, this
> patch also adds oe_on and we_on to nand_default_timings[] as they
> would be by the retime function.
> 
> Signed-off-by: Christoph Fritz <chf.fritz at googlemail.com>

Thanks looks safe to me so applying into omap-for-v3.11/gpmc.

Regards,

Tony

> ---
>  arch/arm/mach-omap2/board-flash.c |    3 +++
>  arch/arm/mach-omap2/gpmc-nand.c   |   40 +------------------------------------
>  2 files changed, 4 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
> index c33adea..fc20a61 100644
> --- a/arch/arm/mach-omap2/board-flash.c
> +++ b/arch/arm/mach-omap2/board-flash.c
> @@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = {
>  		.cs_rd_off = 36,
>  		.cs_wr_off = 36,
>  
> +		.we_on = 6,
> +		.oe_on = 6,
> +
>  		.adv_on = 6,
>  		.adv_rd_off = 24,
>  		.adv_wr_off = 36,
> diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
> index d9c2719..c8044b0 100644
> --- a/arch/arm/mach-omap2/gpmc-nand.c
> +++ b/arch/arm/mach-omap2/gpmc-nand.c
> @@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
>  	.resource	= gpmc_nand_resource,
>  };
>  
> -static int omap2_nand_gpmc_retime(
> -				struct omap_nand_platform_data *gpmc_nand_data,
> -				struct gpmc_timings *gpmc_t)
> -{
> -	struct gpmc_timings t;
> -	int err;
> -
> -	memset(&t, 0, sizeof(t));
> -	t.sync_clk = gpmc_t->sync_clk;
> -	t.cs_on = gpmc_t->cs_on;
> -	t.adv_on = gpmc_t->adv_on;
> -
> -	/* Read */
> -	t.adv_rd_off = gpmc_t->adv_rd_off;
> -	t.oe_on  = t.adv_on;
> -	t.access = gpmc_t->access;
> -	t.oe_off = gpmc_t->oe_off;
> -	t.cs_rd_off = gpmc_t->cs_rd_off;
> -	t.rd_cycle = gpmc_t->rd_cycle;
> -
> -	/* Write */
> -	t.adv_wr_off = gpmc_t->adv_wr_off;
> -	t.we_on  = t.oe_on;
> -	if (cpu_is_omap34xx()) {
> -		t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
> -		t.wr_access = gpmc_t->wr_access;
> -	}
> -	t.we_off = gpmc_t->we_off;
> -	t.cs_wr_off = gpmc_t->cs_wr_off;
> -	t.wr_cycle = gpmc_t->wr_cycle;
> -
> -	err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
> -	if (err)
> -		return err;
> -
> -	return 0;
> -}
> -
>  static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
>  {
>  	/* support only OMAP3 class */
> @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
>  				gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
>  
>  	if (gpmc_t) {
> -		err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
> +		err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
>  		if (err < 0) {
>  			dev_err(dev, "Unable to set gpmc timings: %d\n", err);
>  			return err;
> -- 
> 1.7.10.4
> 
> 
> 


From festevam at gmail.com  Thu May 16 11:50:31 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 16 May 2013 12:50:31 -0300
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <1368713639-21485-2-git-send-email-fabio.estevam@freescale.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <1368713639-21485-2-git-send-email-fabio.estevam@freescale.com>
Message-ID: <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>

On Thu, May 16, 2013 at 11:13 AM, Fabio Estevam
<fabio.estevam at freescale.com> wrote:
> Commit e5aba13 (i2c: i2c-mxs: move to use generic DMA helper) changed
> i2c-mxs.txt and drivers/i2c/busses/i2c-mxs.c to only use one I2C interrupt.
>
> Adapt the dtsi bindings with such change.
>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx28.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 33389b8..2e1ba4b 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -878,7 +878,7 @@
>                                 #size-cells = <0>;
>                                 compatible = "fsl,imx28-i2c";
>                                 reg = <0x80058000 0x2000>;
> -                               interrupts = <111 68>;
> +                               interrupts = <111>;
>                                 clock-frequency = <100000>;
>                                 dmas = <&dma_apbx 6>;
>                                 dma-names = "rx-tx";
> @@ -891,7 +891,7 @@
>                                 #size-cells = <0>;
>                                 compatible = "fsl,imx28-i2c";
>                                 reg = <0x8005a000 0x2000>;
> -                               interrupts = <110 69>;
> +                               interrupts = <110>;
>                                 clock-frequency = <100000>;
>                                 dmas = <&dma_apbx 7>;
>                                 dma-names = "rx-tx";

Actually the correct is:

--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -878,7 +878,7 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx28-i2c";
 				reg = <0x80058000 0x2000>;
-				interrupts = <111 68>;
+				interrupts = <68>;
 				clock-frequency = <100000>;
 				dmas = <&dma_apbx 6>;
 				dma-names = "rx-tx";
@@ -891,7 +891,7 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx28-i2c";
 				reg = <0x8005a000 0x2000>;
-				interrupts = <110 69>;
+				interrupts = <69>;
 				clock-frequency = <100000>;
 				dmas = <&dma_apbx 7>;
 				dma-names = "rx-tx";

,but then i2c fails to probe.

Has anyone tried mxs i2c dma recently?

Here is what I do on linux-next-20130516:

- Revert  b871f1ad3c8a1ac2 (will send this later to alsa-devel)
- Booting mx28evk will show:

[    6.378298]  mmcblk0: p1 p2 p3
[   29.547791] sgtl5000 0-000a: Failed to get supply 'VDDD': -19
[   29.556308] 0-000a: 1200 mV normal
[   29.562225] sgtl5000 0-000a: Using internal LDO instead of VDDD
[   29.573156] sgtl5000 0-000a: sgtl5000 revision 0x11

,ie, i2c is too slow as it takes 13 seconds to read the sgtl5000 codec
registers. Looks like i2c dma is disabled

Then I apply

--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -878,7 +878,7 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx28-i2c";
 				reg = <0x80058000 0x2000>;
-				interrupts = <111 68>;
+				interrupts = <68>;
 				clock-frequency = <100000>;
 				dmas = <&dma_apbx 6>;
 				dma-names = "rx-tx";
@@ -891,7 +891,7 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx28-i2c";
 				reg = <0x8005a000 0x2000>;
-				interrupts = <110 69>;
+				interrupts = <69>;
 				clock-frequency = <100000>;
 				dmas = <&dma_apbx 7>;
 				dma-names = "rx-tx";

and the sgtl5000 probe fails.


From robherring2 at gmail.com  Thu May 16 11:50:37 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 May 2013 10:50:37 -0500
Subject: [PATCH] ARM: prima2: return rather than panic on missing DT nodes
Message-ID: <1368719437-28287-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Missing nodes is a normal condition in multi-platform kernels when we boot
on other platforms. So remove the panic and just return if we don't find
a DT node.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Barry Song <baohua.song at csr.com>
---
 arch/arm/mach-prima2/pm.c   | 2 +-
 arch/arm/mach-prima2/rstc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 9936c18..a8003e2 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -102,7 +102,7 @@ static int __init sirfsoc_of_pwrc_init(void)
 
 	np = of_find_matching_node(NULL, pwrc_ids);
 	if (!np)
-		panic("unable to find compatible pwrc node in dtb\n");
+		return -ENODEV;
 
 	/*
 	 * pwrc behind rtciobrg is not located in memory space
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..6d7d9db 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -29,7 +29,7 @@ static int __init sirfsoc_of_rstc_init(void)
 
 	np = of_find_matching_node(NULL, rstc_ids);
 	if (!np)
-		panic("unable to find compatible rstc node in dtb\n");
+		return -ENODEV;
 
 	sirfsoc_rstc_base = of_iomap(np, 0);
 	if (!sirfsoc_rstc_base)
-- 
1.8.1.2



From marex at denx.de  Thu May 16 11:51:17 2013
From: marex at denx.de (Marek Vasut)
Date: Thu, 16 May 2013 17:51:17 +0200
Subject: parallel-display driver for i.MX53
In-Reply-To: <CAOkaPuUdugB8+qTakh8-N0bsxfobQymbYtCQ67FfX8CuttPb0A@mail.gmail.com>
References: <CAOkaPuX7RjwrMiZUCGwXTovgsFf=onRkrGa2U+qUv-tU3t4WWg@mail.gmail.com>
 <CAOkaPuUdugB8+qTakh8-N0bsxfobQymbYtCQ67FfX8CuttPb0A@mail.gmail.com>
Message-ID: <201305161751.17405.marex@denx.de>

Dear Rogerio Pimentel,

> Hi Philipp,
> 
> I see that reverting patch
> 
> 2ea42608ba977bd05ce7b2d8a1f65efacfc84352
> staging: drm/imx: Add support for VGA via TVE on i.MX53
> 
> The display on LCD/i.MX53QSB shows for about 1 second and turn off.
> Have you noticed any kind of problem on parallel displays after your
> recent patches?
> Could you please confirm that imx-parallel display is functional after
> your tve patches are applied?

You should not do this top-posting ;-)

> On Thu, May 16, 2013 at 11:02 AM, Rogerio Pimentel
> 
> <rpimentel.silva at gmail.com> wrote:
> > Hi,
> > 
> > I'm trying to add the parallel display on i.MX53QSB but it's not
> > working on current linux next. It was working prior to 3.10-rc1.
> > 
> > Does anybody know about any significant change that made this driver
> > break? Or maybe something else I need to do on imx53-qsb.dtb?
> > 
> > Thanks,
> > Rogerio

Best regards,
Marek Vasut


From jason at lakedaemon.net  Thu May 16 11:56:17 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 11:56:17 -0400
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <20130516174903.3a7a07ef@skate>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130516093312.GB2459@localhost>
 <20130516154031.GF6563@titan.lakedaemon.net>
 <20130516174903.3a7a07ef@skate>
Message-ID: <20130516155617.GH6563@titan.lakedaemon.net>

On Thu, May 16, 2013 at 05:49:03PM +0200, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Thu, 16 May 2013 11:40:31 -0400, Jason Cooper wrote:
> 
> > > > +static int mvebu_pcie_init(void)
> > > 
> > > Building this showed a warning here. It seems you forgot
> > > to mark this one as __init.
> > 
> > Thomas, I'll fix this up when I pull this in, no need to resend. :)
> 
> I'll resend, because beyond this function pointed by Ezequiel, there
> are two other functions that can be marked __init. The one pointed by
> Ezequiel is important because it causes a section mismatch
> when !CONFIG_MODULES, because in this case platform_driver_probe() is
> __init (and this explains what I wasn't seeing the warning, since I'm
> building CONFIG_MODULES=y). The two other functions are more cosmetic,
> but good to have as well.
> 
> It would already been sent if git hadn't decided to do a 'git gc' right
> after my rebase. It's been gc-ing for quite some time now...

Dear boss,

I am in desperate need of a 500GB SSD on which to do my kernel work.

Thanks,

Kranky Kernel Developer

hehehe...


I'll pull in once you send.

thx,

Jason.


From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:16 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:16 +0200
Subject: [PATCHv10 1/9] arm: mvebu: fix the 'ranges' property to handle PCIe
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-2-git-send-email-thomas.petazzoni@free-electrons.com>

Since 82a682676 ('ARM: dts: mvebu: Convert all the mvebu files to use
the range property') all the device nodes of Armada 370/XP are under a
common 'ranges' property that translates the device register addresses
into their absolute address, thanks to the base address of the
internal register space.

However, beyond just the register areas, there are also PCIe I/O and
memory regions, whose addresses should be properly translated. This
patch fixes the Armada 370 and XP ranges property to take PCIe into
account properly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Since the PCIe Device Tree description has been merged in 3.10-rc1,
this commit should go in 3.10-rc as well.
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    3 ++-
 arch/arm/boot/dts/armada-370.dtsi    |    3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..550eb77 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -33,7 +33,8 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&mpic>;
-		ranges = <0 0 0xd0000000 0x100000>;
+		ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
+			  0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
 
 		internal-regs {
 			compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index b2c1b5a..834c9be 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -29,7 +29,8 @@
 	};
 
 	soc {
-		ranges = <0 0xd0000000 0x100000>;
+		ranges = <0          0xd0000000 0x0100000 /* internal registers */
+			  0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
 		internal-regs {
 			system-controller at 18200 {
 				compatible = "marvell,armada-370-xp-system-controller";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:17 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:17 +0200
Subject: [PATCHv10 2/9] of/pci: Provide support for parsing PCI DT ranges
 property
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-3-git-send-email-thomas.petazzoni@free-electrons.com>

From: Andrew Murray <Andrew.Murray at arm.com>

This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to write archiecture independent host bridge
drivers and mitigate against further duplication of DT parsing code.

This patch can be used in the following way:

	struct of_pci_range_parser parser;
	struct of_pci_range range;

	if (of_pci_range_parser_init(&parser, np))
		; //no ranges property

	for_each_of_pci_range(&parser, &range) {

		/*
			directly access properties of the address range, e.g.:
			range.pci_space, range.pci_addr, range.cpu_addr,
			range.size, range.flags

			alternatively obtain a struct resource, e.g.:
			struct resource res;
			of_pci_range_to_resource(&range, np, &res);
		*/
	}

Additionally the implementation takes care of adjacent ranges and merges them
into a single range (as was the case with powerpc and microblaze).

Signed-off-by: Andrew Murray <Andrew.Murray at arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Reviewed-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Tested-by: Linus Walleij <linus.walleij at linaro.org>
Tested-by: Jingoo Han <jg1.han at samsung.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/of/address.c       |   67 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/of_address.h |   48 +++++++++++++++++++++++++++++++
 2 files changed, 115 insertions(+)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 04da786..fdd0636 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
 	return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
 }
 EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+
+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+				struct device_node *node)
+{
+	const int na = 3, ns = 2;
+	int rlen;
+
+	parser->node = node;
+	parser->pna = of_n_addr_cells(node);
+	parser->np = parser->pna + na + ns;
+
+	parser->range = of_get_property(node, "ranges", &rlen);
+	if (parser->range == NULL)
+		return -ENOENT;
+
+	parser->end = parser->range + rlen / sizeof(__be32);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
+
+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
+						struct of_pci_range *range)
+{
+	const int na = 3, ns = 2;
+
+	if (!range)
+		return NULL;
+
+	if (!parser->range || parser->range + parser->np > parser->end)
+		return NULL;
+
+	range->pci_space = parser->range[0];
+	range->flags = of_bus_pci_get_flags(parser->range);
+	range->pci_addr = of_read_number(parser->range + 1, ns);
+	range->cpu_addr = of_translate_address(parser->node,
+				parser->range + na);
+	range->size = of_read_number(parser->range + parser->pna + na, ns);
+
+	parser->range += parser->np;
+
+	/* Now consume following elements while they are contiguous */
+	while (parser->range + parser->np <= parser->end) {
+		u32 flags, pci_space;
+		u64 pci_addr, cpu_addr, size;
+
+		pci_space = be32_to_cpup(parser->range);
+		flags = of_bus_pci_get_flags(parser->range);
+		pci_addr = of_read_number(parser->range + 1, ns);
+		cpu_addr = of_translate_address(parser->node,
+				parser->range + na);
+		size = of_read_number(parser->range + parser->pna + na, ns);
+
+		if (flags != range->flags)
+			break;
+		if (pci_addr != range->pci_addr + range->size ||
+		    cpu_addr != range->cpu_addr + range->size)
+			break;
+
+		range->size += size;
+		parser->range += parser->np;
+	}
+
+	return range;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
+
 #endif /* CONFIG_PCI */
 
 /*
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index 0506eb5..4c2e6f2 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -4,6 +4,36 @@
 #include <linux/errno.h>
 #include <linux/of.h>
 
+struct of_pci_range_parser {
+	struct device_node *node;
+	const __be32 *range;
+	const __be32 *end;
+	int np;
+	int pna;
+};
+
+struct of_pci_range {
+	u32 pci_space;
+	u64 pci_addr;
+	u64 cpu_addr;
+	u64 size;
+	u32 flags;
+};
+
+#define for_each_of_pci_range(parser, range) \
+	for (; of_pci_range_parser_one(parser, range);)
+
+static inline void of_pci_range_to_resource(struct of_pci_range *range,
+					    struct device_node *np,
+					    struct resource *res)
+{
+	res->flags = range->flags;
+	res->start = range->cpu_addr;
+	res->end = range->cpu_addr + range->size - 1;
+	res->parent = res->child = res->sibling = NULL;
+	res->name = np->full_name;
+}
+
 #ifdef CONFIG_OF_ADDRESS
 extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
 extern bool of_can_translate_address(struct device_node *dev);
@@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
 #define pci_address_to_pio pci_address_to_pio
 #endif
 
+extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+			struct device_node *node);
+extern struct of_pci_range *of_pci_range_parser_one(
+					struct of_pci_range_parser *parser,
+					struct of_pci_range *range);
 #else /* CONFIG_OF_ADDRESS */
 #ifndef of_address_to_resource
 static inline int of_address_to_resource(struct device_node *dev, int index,
@@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
 {
 	return NULL;
 }
+
+static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+			struct device_node *node)
+{
+	return -1;
+}
+
+static inline struct of_pci_range *of_pci_range_parser_one(
+					struct of_pci_range_parser *parser,
+					struct of_pci_range *range)
+{
+	return NULL;
+}
 #endif /* CONFIG_OF_ADDRESS */
 
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:15 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:15 +0200
Subject: [PATCHv10 0/9] PCIe support for the Armada 370 and Armada XP SoCs
Message-ID: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

This series of patches introduces PCIe support for the Marvell Armada
370 and Armada XP.

I'd like this code to be merged for 3.11.

For easier testing, the code has been pushed to:

  git://github.com/MISL-EBU-System-SW/mainline-public.git marvell-pcie-v10

This PATCHv10 follows:
 * PATCHv9, sent on May, 16th 2013
 * PATCHv8, sent on April, 9th 2013
 * PATCHv7, sent on March, 27th 2013
 * PATCHv6, sent on March, 26st 2013
 * PATCHv5, sent on March, 21st 2013
 * PATCHv4, sent on March, 8th 2013
 * PATCHv3, sent on February, 12th 2013
 * PATCHv2, sent on January, 28th 2013
 * RFCv1, sent on December, 7th 2012

Changes between v9 and v10:

 * Mark mvebu_pcie_init() as __init, as reported by Ezequiel
   Garcia. platform_driver_probe() is __init_or_module, so when
   !CONFIG_MODULES is used, platform_driver_probe() belongs to the
   __init section.

 * Mark two other small functions as __init, just because they are
   only used during the initialization (mvebu_pcie_enable and
   mvebu_pcie_map_registers). Suggested by Ezequiel Garcia.

Changes between v8 and v9:

 * Rebased on top of 3.10-rc1. Since the PCIe Device Tree informations
   were merged in 3.10-rc1, it allowed to reduce quite significantly
   the size of this patch set.

 * A fix for the PCIe Device Tree information is added as the first
   patch, it adds a missing range entry to let the global PCIe
   memory/IO window addresses be correctly translated. It should be
   merged into the 3.10-rc cycle, to fix the hardware definition of
   the platform.

 * The patch set now integrates the latest version of Andrew Murray
   of/pci patch, that adds the PCI range parsing functions. The one
   I've integrated is:

   [PATCH v9 1/3] of/pci: Provide support for parsing PCI DT ranges property

 * I've fixed the PowerPC64 build problem, which was the reason why
   this driver was not taken for 3.10. In fact, the patch 'pci:
   infrastructure to add drivers in drivers/pci/host' was introducing
   a drivers/pci/host directory, with just an empty
   Makefile. Unfortunately, an empty Makefile doesn't trigger the
   generation of drivers/pci/host/built-in.o. So if you try to build
   the kernel with just this patch applied, and not the PCIe driver
   itself, the Makefile is empty, and the build breaks.

   To solve this, I've simply merged this patch with the PCIe driver
   patch itself. The PCIe driver patch adds the drivers/pci/host/
   directory and the related Kconfig/Makefile bits.

 * Fixed a regression in the driver introduced between the v7 and the
   v8. A #define <something> 1 was changed to #define <something>
   BIT(1), which obviously doesn't work. Changed to BIT(0), which is
   correct.

Changes between v7 and v8:

 * In the patch introducing the drivers/pci/host directory, add an
   empty drivers/pci/host/Makefile to ensure that the kernel still
   build. This Makefile will actually gets its first useful line when
   the Marvell PCIe driver gets added. Noted by Neil Greatorex.

 * Remove bogus (and useless) CFLAGS in drivers/pci/host/Makefile for
   the compilation of the Marvell PCIe driver. Noticed by Bjorn
   Helgaas.

 * Added missing parenthesis in the definition of the
   PCIE_BAR_CTRL_OFF macro. Noticed by Bjorn Helgaas.

 * Make mvebu_pcie_link_up() return 'bool' instead of 'int'. Suggested
   by Bjorn Helgaas.

 * Change mvebu_pcie_link_up(), mvebu_pcie_set_local_bus_nr(),
   mvebu_pcie_setup_wins(), mvebu_pcie_setup_hw(),
   mvebu_pcie_hw_rd_conf(), mvebu_pcie_hw_wr_conf() so that they take
   a 'struct mvebu_pcie_port *' instead of a 'void __iomem *' as first
   argument. The base address of the PCIe interface register are
   available using the 'base' field of 'struct
   mvebu_pcie_port'. Suggested by Bjorn Helgaas.

 * Fixed multi-line comments that should have been one line
   comments. Noticed by Bjorn Helgaas.

 * Fixed a for() loop in mvebu_pcie_setup_wins() to use the more
   conventional 'ii < 3' ending condition instead of 'i <=
   2'. Suggested by Bjorn Helgaas.

 * Add a #define instead of an hardcoded magic value when enabling
   interrupts A-D in mvebu_pcie_setup_hw(). Suggested by Bjorn
   Helgaas.

 * Add a PCIE_CONF_ADDR() to simplify the code in
   mvebu_pcie_hw_rd_conf() and mvebu_pcie_hw_wr_conf(). Suggested by
   Bjorn Helgaas.

 * Clarify the comments in mvebu_pcie_handle_iobase_change() and
   mvebu_pcie_handle_membase_change() so that it is clear we look at
   the new iobase/iolimit (respectively membase/memlimit)
   values. Suggested by Bjorn Helgaas.

 * Replace mvebu_pcie_find_port_by_bus() and
   mvebu_pcie_find_port_by_devfn() by a single mvebu_pcie_find_port()
   function, and simplify the mvebu_pcie_rd_conf() and
   mvebu_pcie_wr_conf() functions. Suggested by Bjorn Helgaas.

 * Fix the computation of the real I/O resource start and end
   addresses, according to the suggestions of Arnd Bergmann and Jason
   Gunthorpe.

 * Remove the MASK/OFFS definition, and use definitions more in the
   style of pci_regs.h. Suggested by Bjorn Helgaas.

 * Integrate the latest version of 'of/pci: Provide support for
   parsing PCI DT ranges property' from Andrew Murray, fixed according
   to the review of Rob Herring.

 * Added the Acked-by tags from Bjorn Helgaas on the PCI patches.

Changes between v6 and v7:

 * Use assigned-addresses in the DT subnodes for the MMIO PCIe
   registers, in order to align with what Thierry is doing on the
   Tegra PCIe driver.

 * Added empty 'ranges;' properties in the subnodes, as requested by
   Arnd. Note that due to this, it is not possible to remove the
   #address-cells and #size-cells properties from the subnodes, as
   Jason Gunthorpe requested, otherwise the DT compiler complains with:

     Warning (ranges_format): /soc/pcie-controller/pcie at 1,0 has empty
     "ranges" property but its #address-cells (2) differs from
     /soc/pcie-controller (3)

     Warning (ranges_format): /soc/pcie-controller/pcie at 1,0 has empty
     "ranges" property but its #size-cells (1) differs from
     /soc/pcie-controller (2)

 * Use the new RFCv3 patch from Andrew Murray for 'of/pci: Provide
   support for parsing PCI DT ranges property'.

 * Updated the DT binding documentation accordingly.

Changes between v5 and v6:

 * Use pci_create_root_bus() + pci_scan_child_bus() instead of
   pci_scan_root_bus(). This is needed to be able to add MSI support
   later on. Moreover Thierry Reding suggested that
   pci_scan_root_bus() "does a pci_bus_add_devices(), which is called
   again in pci_common_init() in the ARM code". Thanks Thierry for
   pointing out this issue.

Changes between v4 and v5:

 * Rebased on top of 3.9-rc2 + the new mvebu-mbus driver (v3).

 * Changed the names of the PCI DT sub-nodes to match the OF
   specifications: they should be named pcie at DD,FF where DD is the
   device number and FF the function number. Requested by Mitch
   Bradley.

 * Add the device_type = "pci" property at the pcie-controller
   level. Requested by Mitch Bradley.

 * Drop patch 'of/pci: Add of_pci_get_bus() function' because it
   wasn't actually used in the rest of the patch series.

 * Updated the patch 'of/pci: Provide support for parsing PCI DT
   ranges property' to use the latest version proposed by Andrew
   Murray on the devicetree-discuss@ mailing list.

Changes between v3 and v4:

 * Rebased on top of 3.9-rc1.

 * Drop patch "ARM: pci: Allow passing per-controller private data"
   because it was merged in 3.9.

 * Drop patch "lib: devres: don't enclose pcim_*() functions in
   CONFIG_HAS_IOPORT", because it was merged in 3.9.

 * Added CONFIG_PCI_MVEBU=y in mvebu_defconfig, so that the right PCI
   host controller driver is automatically enabled.

 * Instead of using the DT 'ranges' property to encode the PCIe
   register ranges, use a 'reg' property on the main PCIe controller
   DT node together with a 'reg-names' property. Suggested by Jason
   Gunthorpe.

 * Don't select PCI_SW_HOST_BRIDGE and PCI_SW_PCI_PCI_BRIDGE, they
   don't exist anymore. Reported by Bjorn Helgaas.

 * Added support for the Armada XP GP board.

 * Fix the 'ranges' property so that the memory range is an identity
   map between CPU addresses and bus addresses. Suggested by Arnd
   Bergmann.

 * Changed the 'ranges' property to have the I/O region after the
   memory region.

 * Use the new mvebu-mbus driver API to create/remove address decoding
   windows when needed. This remove the need to include
   <mach/addr-map.h>. Requested by Arnd Bergmann.

 * Include directly into the driver the few common PCIe functions we
   were using from arch/arm/plat-orion/pcie.c. This allows to remove
   the inclusion of <plat/pcie.h>. Requested by Arnd Bergmann.

 * Directly set up the address decoding windows when the memory
   base/limit and I/O base/limit are configured in the PCI-to-PCI
   bridge instead of relying on the memory and I/O accesses being
   enabled in the PCI_COMMAND register. Suggested by Bjorn Helgaas.

 * Added some comments on top of the calculations of the I/O
   base/limit and memory base/limit. Suggested by Arnd Bergmann.

 * Changed a bit the way the "realio" resource is created, from
   suggestions given by Arnd Bergmann.

 * Updated the Device Tree binding documentation. Reported by Jason
   Gunthorpe.

 * Instead of using "marvell,armada-370-xp-pcie" as the DT compatible
   string, use two separate compatible strings:
   "marvell,armada-370-pcie" and "marvell,armada-xp-pcie". For now,
   the driver does the same thing for both.

Changes between v2 and v3:

 * Use of_irq_map_pci() instead of of_irq_map_raw(), as suggested by
   Andrew Murray. In order to do this, we moved the interrupt-map and
   interrupt-map-mask DT properties from the main PCIe controller node
   to the DT subnodes representing each PCIe interface.

 * Remove the usage of the emulated host bridge.

 * Move the emulated PCI-to-PCI bridge code into the Marvell PCI
   driver itself, in order to allow a tighter integration. Suggested
   by Bjorn Helgaas and Jason Gunthorpe.

 * Make the allocation of address decoding windows dynamic: it's when
   memory accesses or I/O accesses are enabled at the PCI-to-PCI
   bridge level that we allocate and setup the corresponding address
   decoding window. Requested by Bjorn Helgaas.

 * Fixed the implementation of I/O accesses to use I/O addresses that
   fall within the normal IO_SPACE_LIMIT. This required using the
   "remap" functionality of address decoding windows, and therefore
   some changes in the address decoding window allocator. Follows a
   long discussion about I/O accesses.

 * Set up a correct bus number in the configuration of the PCIe
   interfaces so that we don't have to fake bus numbers
   anymore. Requested by Jason Gunthorpe.

 * Fix the of_pci_get_devfn() implementation according to Stephen
   Warren's comment.

 * Use CFLAGS_ instead of ccflags to add the mach-mvebu and plat-orion
   include paths when building the pci-mvebu driver. This ensures that
   the include paths are only added when building this specific
   driver. Requested by Stephen Warren.

 * Fix the ->resource_align() to only apply on bus 0 (the one on which
   the emulated PCI-to-PCI bridges sit), and to request an alignment
   on the size of the window (and not only 64 KB for I/O windows and 1
   MB for memory windows).

 * Clarified the commit log of "clk: mvebu: create parent-child
   relation for PCIe clocks on Armada 370"

Thanks,

Thomas

Andrew Murray (1):
  of/pci: Provide support for parsing PCI DT ranges property

Thierry Reding (2):
  of/pci: Add of_pci_get_devfn() function
  of/pci: Add of_pci_parse_bus_range() function

Thomas Petazzoni (6):
  arm: mvebu: fix the 'ranges' property to handle PCIe
  clk: mvebu: create parent-child relation for PCIe clocks on Armada
    370
  clk: mvebu: add more PCIe clocks for Armada XP
  pci: PCIe driver for Marvell Armada 370/XP systems
  arm: mvebu: PCIe support is now available on mvebu
  arm: mvebu: update defconfig with PCI and USB support

 .../devicetree/bindings/pci/mvebu-pci.txt          |  220 +++++
 arch/arm/boot/dts/armada-370-xp.dtsi               |    3 +-
 arch/arm/boot/dts/armada-370.dtsi                  |    3 +-
 arch/arm/configs/mvebu_defconfig                   |    3 +
 arch/arm/mach-mvebu/Kconfig                        |    2 +
 drivers/clk/mvebu/clk-gating-ctrl.c                |   18 +-
 drivers/of/address.c                               |   67 ++
 drivers/of/of_pci.c                                |   59 +-
 drivers/pci/Kconfig                                |    2 +
 drivers/pci/Makefile                               |    3 +
 drivers/pci/host/Kconfig                           |    8 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pci-mvebu.c                       |  880 ++++++++++++++++++++
 include/linux/of_address.h                         |   48 ++
 include/linux/of_pci.h                             |    2 +
 15 files changed, 1306 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
 create mode 100644 drivers/pci/host/Kconfig
 create mode 100644 drivers/pci/host/Makefile
 create mode 100644 drivers/pci/host/pci-mvebu.c

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:18 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:18 +0200
Subject: [PATCHv10 3/9] of/pci: Add of_pci_get_devfn() function
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-4-git-send-email-thomas.petazzoni@free-electrons.com>

From: Thierry Reding <thierry.reding at avionic-design.de>

This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/of/of_pci.c    |   34 +++++++++++++++++++++++++++++-----
 include/linux/of_pci.h |    1 +
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 13e37e2..4dd7b9b 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -5,14 +5,15 @@
 #include <asm/prom.h>
 
 static inline int __of_pci_pci_compare(struct device_node *node,
-				       unsigned int devfn)
+				       unsigned int data)
 {
-	unsigned int size;
-	const __be32 *reg = of_get_property(node, "reg", &size);
+	int devfn;
 
-	if (!reg || size < 5 * sizeof(__be32))
+	devfn = of_pci_get_devfn(node);
+	if (devfn < 0)
 		return 0;
-	return ((be32_to_cpup(&reg[0]) >> 8) & 0xff) == devfn;
+
+	return devfn == data;
 }
 
 struct device_node *of_pci_find_child_device(struct device_node *parent,
@@ -40,3 +41,26 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(of_pci_find_child_device);
+
+/**
+ * of_pci_get_devfn() - Get device and function numbers for a device node
+ * @np: device node
+ *
+ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
+ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
+ * and function numbers respectively. On error a negative error code is
+ * returned.
+ */
+int of_pci_get_devfn(struct device_node *np)
+{
+	unsigned int size;
+	const __be32 *reg;
+
+	reg = of_get_property(np, "reg", &size);
+
+	if (!reg || size < 5 * sizeof(__be32))
+		return -EINVAL;
+
+	return (be32_to_cpup(reg) >> 8) & 0xff;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_devfn);
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index bb115de..91ec484 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -10,5 +10,6 @@ int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq);
 struct device_node;
 struct device_node *of_pci_find_child_device(struct device_node *parent,
 					     unsigned int devfn);
+int of_pci_get_devfn(struct device_node *np);
 
 #endif
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:19 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:19 +0200
Subject: [PATCHv10 4/9] of/pci: Add of_pci_parse_bus_range() function
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-5-git-send-email-thomas.petazzoni@free-electrons.com>

From: Thierry Reding <thierry.reding at avionic-design.de>

This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 drivers/of/of_pci.c    |   25 +++++++++++++++++++++++++
 include/linux/of_pci.h |    1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 4dd7b9b..42c687a 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -64,3 +64,28 @@ int of_pci_get_devfn(struct device_node *np)
 	return (be32_to_cpup(reg) >> 8) & 0xff;
 }
 EXPORT_SYMBOL_GPL(of_pci_get_devfn);
+
+/**
+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
+ * @node: device node
+ * @res: address to a struct resource to return the bus-range
+ *
+ * Returns 0 on success or a negative error-code on failure.
+ */
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
+{
+	const __be32 *values;
+	int len;
+
+	values = of_get_property(node, "bus-range", &len);
+	if (!values || len < sizeof(*values) * 2)
+		return -EINVAL;
+
+	res->name = node->name;
+	res->start = be32_to_cpup(values++);
+	res->end = be32_to_cpup(values);
+	res->flags = IORESOURCE_BUS;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 91ec484..7a04826 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -11,5 +11,6 @@ struct device_node;
 struct device_node *of_pci_find_child_device(struct device_node *parent,
 					     unsigned int devfn);
 int of_pci_get_devfn(struct device_node *np);
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 
 #endif
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:23 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:23 +0200
Subject: [PATCHv10 8/9] arm: mvebu: PCIe support is now available on mvebu
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-9-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/Kconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb..381062d 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -15,6 +15,8 @@ config ARCH_MVEBU
 	select MVEBU_CLK_GATING
 	select MVEBU_MBUS
 	select ZONE_DMA if ARM_LPAE
+	select MIGHT_HAVE_PCI
+	select PCI_QUIRKS if PCI
 
 if ARCH_MVEBU
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:20 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:20 +0200
Subject: [PATCHv10 5/9] clk: mvebu: create parent-child relation for PCIe
 clocks on Armada 370
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-6-git-send-email-thomas.petazzoni@free-electrons.com>

The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 drivers/clk/mvebu/clk-gating-ctrl.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index ebf141d..b35785a 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
 	{ "pex1_en", NULL,  2 },
 	{ "ge1", NULL, 3 },
 	{ "ge0", NULL, 4 },
-	{ "pex0", NULL, 5 },
-	{ "pex1", NULL, 9 },
+	{ "pex0", "pex0_en", 5 },
+	{ "pex1", "pex1_en", 9 },
 	{ "sata0", NULL, 15 },
 	{ "sdio", NULL, 17 },
 	{ "tdm", NULL, 25 },
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:21 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:21 +0200
Subject: [PATCHv10 6/9] clk: mvebu: add more PCIe clocks for Armada XP
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-7-git-send-email-thomas.petazzoni@free-electrons.com>

The current revision of the datasheet only mentions the gatable clocks
for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
interfaces. After confirmation with Marvell engineers, this patch adds
the missing gatable clocks for those PCIe interfaces.

It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 drivers/clk/mvebu/clk-gating-ctrl.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index b35785a..2f03723 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
 	{ "ge2", NULL,  2 },
 	{ "ge1", NULL, 3 },
 	{ "ge0", NULL, 4 },
-	{ "pex0", NULL, 5 },
-	{ "pex1", NULL, 6 },
-	{ "pex2", NULL, 7 },
-	{ "pex3", NULL, 8 },
+	{ "pex00", NULL, 5 },
+	{ "pex01", NULL, 6 },
+	{ "pex02", NULL, 7 },
+	{ "pex03", NULL, 8 },
+	{ "pex10", NULL, 9 },
+	{ "pex11", NULL, 10 },
+	{ "pex12", NULL, 11 },
+	{ "pex13", NULL, 12 },
 	{ "bp", NULL, 13 },
 	{ "sata0lnk", NULL, 14 },
 	{ "sata0", "sata0lnk", 15 },
@@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
 	{ "xor0", NULL, 22 },
 	{ "crypto", NULL, 23 },
 	{ "tdm", NULL, 25 },
+	{ "pex20", NULL, 26 },
+	{ "pex30", NULL, 27 },
 	{ "xor1", NULL, 28 },
 	{ "sata1lnk", NULL, 29 },
 	{ "sata1", "sata1lnk", 30 },
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:24 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:24 +0200
Subject: [PATCHv10 9/9] arm: mvebu: update defconfig with PCI and USB support
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-10-git-send-email-thomas.petazzoni@free-electrons.com>

Now that we have the necessary drivers and Device Tree informations to
support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
option.

Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
connected on the PCIe bus, enable the corresponding options as well.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/configs/mvebu_defconfig |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae0..966281e 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
@@ -60,6 +62,7 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_MMC=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 11:55:22 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 17:55:22 +0200
Subject: [PATCHv10 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1368719725-21265-8-git-send-email-thomas.petazzoni@free-electrons.com>

This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.

The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.

Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.

In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas at google.com>
---
 .../devicetree/bindings/pci/mvebu-pci.txt          |  220 +++++
 drivers/pci/Kconfig                                |    2 +
 drivers/pci/Makefile                               |    3 +
 drivers/pci/host/Kconfig                           |    8 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pci-mvebu.c                       |  880 ++++++++++++++++++++
 6 files changed, 1114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
 create mode 100644 drivers/pci/host/Kconfig
 create mode 100644 drivers/pci/host/Makefile
 create mode 100644 drivers/pci/host/pci-mvebu.c

diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
new file mode 100644
index 0000000..eb69d92
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -0,0 +1,220 @@
+* Marvell EBU PCIe interfaces
+
+Mandatory properties:
+- compatible: one of the following values:
+    marvell,armada-370-pcie
+    marvell,armada-xp-pcie
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- bus-range: PCI bus numbers covered
+- device_type, set to "pci"
+- ranges: ranges for the PCI memory and I/O regions, as well as the
+  MMIO registers to control the PCIe interfaces.
+
+In addition, the Device Tree node must have sub-nodes describing each
+PCIe interface, having the following mandatory properties:
+- reg: used only for interrupt mapping, so only the first four bytes
+  are used to refer to the correct bus number and device number.
+- assigned-addresses: reference to the MMIO registers used to control
+  this PCIe interface.
+- clocks: the clock associated to this PCIe interface
+- marvell,pcie-port: the physical PCIe port number
+- status: either "disabled" or "okay"
+- device_type, set to "pci"
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- ranges, empty property.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+
+and the following optional properties:
+- marvell,pcie-lane: the physical PCIe lane number, for ports having
+  multiple lanes. If this property is not found, we assume that the
+  value is 0.
+
+Example:
+
+pcie-controller {
+	compatible = "marvell,armada-xp-pcie";
+	status = "disabled";
+	device_type = "pci";
+
+	#address-cells = <3>;
+	#size-cells = <2>;
+
+	bus-range = <0x00 0xff>;
+
+	ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+		  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+		  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+		  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+		  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+		  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+		  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+		  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
+		  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
+		  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
+		  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+		  0x81000000 0 0	  0xe8000000 0 0x00100000>; /* downstream I/O */
+
+	pcie at 1,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+		reg = <0x0800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 58>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 5>;
+		status = "disabled";
+	};
+
+	pcie at 2,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+		reg = <0x1000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 59>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <1>;
+		clocks = <&gateclk 6>;
+		status = "disabled";
+	};
+
+	pcie at 3,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+		reg = <0x1800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 60>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <2>;
+		clocks = <&gateclk 7>;
+		status = "disabled";
+	};
+
+	pcie at 4,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+		reg = <0x2000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 61>;
+		marvell,pcie-port = <0>;
+		marvell,pcie-lane = <3>;
+		clocks = <&gateclk 8>;
+		status = "disabled";
+	};
+
+	pcie at 5,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+		reg = <0x2800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 62>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 9>;
+		status = "disabled";
+	};
+
+	pcie at 6,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+		reg = <0x3000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 63>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <1>;
+		clocks = <&gateclk 10>;
+		status = "disabled";
+	};
+
+	pcie at 7,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+		reg = <0x3800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 64>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <2>;
+		clocks = <&gateclk 11>;
+		status = "disabled";
+	};
+
+	pcie at 8,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+		reg = <0x4000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 65>;
+		marvell,pcie-port = <1>;
+		marvell,pcie-lane = <3>;
+		clocks = <&gateclk 12>;
+		status = "disabled";
+	};
+	pcie at 9,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+		reg = <0x4800 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 99>;
+		marvell,pcie-port = <2>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 26>;
+		status = "disabled";
+	};
+
+	pcie at 10,0 {
+		device_type = "pci";
+		assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+		reg = <0x5000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &mpic 103>;
+		marvell,pcie-port = <3>;
+		marvell,pcie-lane = <0>;
+		clocks = <&gateclk 27>;
+		status = "disabled";
+	};
+};
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6d51aa6..ac45398 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -119,3 +119,5 @@ config PCI_IOAPIC
 config PCI_LABEL
 	def_bool y if (DMI || ACPI)
 	select NLS
+
+source "drivers/pci/host/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 0c3efcf..6ebf5bf 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 obj-$(CONFIG_OF) += of.o
 
 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
+
+# PCI host controller drivers
+obj-y += host/
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
new file mode 100644
index 0000000..6918fbc
--- /dev/null
+++ b/drivers/pci/host/Kconfig
@@ -0,0 +1,8 @@
+menu "PCI host controller drivers"
+	depends on PCI
+
+config PCI_MVEBU
+	bool "Marvell EBU PCIe controller"
+	depends on ARCH_MVEBU
+
+endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
new file mode 100644
index 0000000..5ea2d8b
--- /dev/null
+++ b/drivers/pci/host/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
new file mode 100644
index 0000000..ad1c46b
--- /dev/null
+++ b/drivers/pci/host/pci-mvebu.c
@@ -0,0 +1,880 @@
+/*
+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mbus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF		0x0000
+#define PCIE_CMD_OFF		0x0004
+#define PCIE_DEV_REV_OFF	0x0008
+#define PCIE_BAR_LO_OFF(n)	(0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)	(0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF	0x0128
+#define PCIE_BAR_CTRL_OFF(n)	(0x1804 + (((n) - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)	(0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)	(0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n)	(0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF	0x1880
+#define PCIE_WIN5_BASE_OFF	0x1884
+#define PCIE_WIN5_REMAP_OFF	0x188c
+#define PCIE_CONF_ADDR_OFF	0x18f8
+#define  PCIE_CONF_ADDR_EN		0x80000000
+#define  PCIE_CONF_REG(r)		((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)		(((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)		(((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)		(((f) & 0x7) << 8)
+#define  PCIE_CONF_ADDR(bus, devfn, where) \
+	(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
+	 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
+	 PCIE_CONF_ADDR_EN)
+#define PCIE_CONF_DATA_OFF	0x18fc
+#define PCIE_MASK_OFF		0x1910
+#define  PCIE_MASK_ENABLE_INTS          0x0f000000
+#define PCIE_CTRL_OFF		0x1a00
+#define  PCIE_CTRL_X1_MODE		0x0001
+#define PCIE_STAT_OFF		0x1a04
+#define  PCIE_STAT_BUS                  0xff00
+#define  PCIE_STAT_LINK_DOWN		BIT(0)
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET		BIT(20)
+
+/*
+ * This product ID is registered by Marvell, and used when the Marvell
+ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
+ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
+ * bridge.
+ */
+#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
+
+/* PCI configuration space of a PCI-to-PCI bridge */
+struct mvebu_sw_pci_bridge {
+	u16 vendor;
+	u16 device;
+	u16 command;
+	u16 status;
+	u16 class;
+	u8 interface;
+	u8 revision;
+	u8 bist;
+	u8 header_type;
+	u8 latency_timer;
+	u8 cache_line_size;
+	u32 bar[2];
+	u8 primary_bus;
+	u8 secondary_bus;
+	u8 subordinate_bus;
+	u8 secondary_latency_timer;
+	u8 iobase;
+	u8 iolimit;
+	u16 secondary_status;
+	u16 membase;
+	u16 memlimit;
+	u16 prefmembase;
+	u16 prefmemlimit;
+	u32 prefbaseupper;
+	u32 preflimitupper;
+	u16 iobaseupper;
+	u16 iolimitupper;
+	u8 cappointer;
+	u8 reserved1;
+	u16 reserved2;
+	u32 romaddr;
+	u8 intline;
+	u8 intpin;
+	u16 bridgectrl;
+};
+
+struct mvebu_pcie_port;
+
+/* Structure representing all PCIe interfaces */
+struct mvebu_pcie {
+	struct platform_device *pdev;
+	struct mvebu_pcie_port *ports;
+	struct resource io;
+	struct resource realio;
+	struct resource mem;
+	struct resource busn;
+	int nports;
+};
+
+/* Structure representing one PCIe interface */
+struct mvebu_pcie_port {
+	char *name;
+	void __iomem *base;
+	spinlock_t conf_lock;
+	int haslink;
+	u32 port;
+	u32 lane;
+	int devfn;
+	struct clk *clk;
+	struct mvebu_sw_pci_bridge bridge;
+	struct device_node *dn;
+	struct mvebu_pcie *pcie;
+	phys_addr_t memwin_base;
+	size_t memwin_size;
+	phys_addr_t iowin_base;
+	size_t iowin_size;
+};
+
+static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
+{
+	return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
+{
+	u32 stat;
+
+	stat = readl(port->base + PCIE_STAT_OFF);
+	stat &= ~PCIE_STAT_BUS;
+	stat |= nr << 8;
+	writel(stat, port->base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
+{
+	const struct mbus_dram_target_info *dram;
+	u32 size;
+	int i;
+
+	dram = mv_mbus_dram_info();
+
+	/* First, disable and clear BARs and windows. */
+	for (i = 1; i < 3; i++) {
+		writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
+		writel(0, port->base + PCIE_BAR_LO_OFF(i));
+		writel(0, port->base + PCIE_BAR_HI_OFF(i));
+	}
+
+	for (i = 0; i < 5; i++) {
+		writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
+		writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
+		writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+	}
+
+	writel(0, port->base + PCIE_WIN5_CTRL_OFF);
+	writel(0, port->base + PCIE_WIN5_BASE_OFF);
+	writel(0, port->base + PCIE_WIN5_REMAP_OFF);
+
+	/* Setup windows for DDR banks.  Count total DDR size on the fly. */
+	size = 0;
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		writel(cs->base & 0xffff0000,
+		       port->base + PCIE_WIN04_BASE_OFF(i));
+		writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+		writel(((cs->size - 1) & 0xffff0000) |
+			(cs->mbus_attr << 8) |
+			(dram->mbus_dram_target_id << 4) | 1,
+		       port->base + PCIE_WIN04_CTRL_OFF(i));
+
+		size += cs->size;
+	}
+
+	/* Round up 'size' to the nearest power of two. */
+	if ((size & (size - 1)) != 0)
+		size = 1 << fls(size);
+
+	/* Setup BAR[1] to all DRAM banks. */
+	writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
+	writel(0, port->base + PCIE_BAR_HI_OFF(1));
+	writel(((size - 1) & 0xffff0000) | 1,
+	       port->base + PCIE_BAR_CTRL_OFF(1));
+}
+
+static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
+{
+	u16 cmd;
+	u32 mask;
+
+	/* Point PCIe unit MBUS decode windows to DRAM space. */
+	mvebu_pcie_setup_wins(port);
+
+	/* Master + slave enable. */
+	cmd = readw(port->base + PCIE_CMD_OFF);
+	cmd |= PCI_COMMAND_IO;
+	cmd |= PCI_COMMAND_MEMORY;
+	cmd |= PCI_COMMAND_MASTER;
+	writew(cmd, port->base + PCIE_CMD_OFF);
+
+	/* Enable interrupt lines A-D. */
+	mask = readl(port->base + PCIE_MASK_OFF);
+	mask |= PCIE_MASK_ENABLE_INTS;
+	writel(mask, port->base + PCIE_MASK_OFF);
+}
+
+static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
+				 struct pci_bus *bus,
+				 u32 devfn, int where, int size, u32 *val)
+{
+	writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+	       port->base + PCIE_CONF_ADDR_OFF);
+
+	*val = readl(port->base + PCIE_CONF_DATA_OFF);
+
+	if (size == 1)
+		*val = (*val >> (8 * (where & 3))) & 0xff;
+	else if (size == 2)
+		*val = (*val >> (8 * (where & 3))) & 0xffff;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
+				 struct pci_bus *bus,
+				 u32 devfn, int where, int size, u32 val)
+{
+	int ret = PCIBIOS_SUCCESSFUL;
+
+	writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+	       port->base + PCIE_CONF_ADDR_OFF);
+
+	if (size == 4)
+		writel(val, port->base + PCIE_CONF_DATA_OFF);
+	else if (size == 2)
+		writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+	else if (size == 1)
+		writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+	else
+		ret = PCIBIOS_BAD_REGISTER_NUMBER;
+
+	return ret;
+}
+
+static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
+{
+	phys_addr_t iobase;
+
+	/* Are the new iobase/iolimit values invalid? */
+	if (port->bridge.iolimit < port->bridge.iobase ||
+	    port->bridge.iolimitupper < port->bridge.iobaseupper) {
+
+		/* If a window was configured, remove it */
+		if (port->iowin_base) {
+			mvebu_mbus_del_window(port->iowin_base,
+					      port->iowin_size);
+			port->iowin_base = 0;
+			port->iowin_size = 0;
+		}
+
+		return;
+	}
+
+	/*
+	 * We read the PCI-to-PCI bridge emulated registers, and
+	 * calculate the base address and size of the address decoding
+	 * window to setup, according to the PCI-to-PCI bridge
+	 * specifications. iobase is the bus address, port->iowin_base
+	 * is the CPU address.
+	 */
+	iobase = ((port->bridge.iobase & 0xF0) << 8) |
+		(port->bridge.iobaseupper << 16);
+	port->iowin_base = port->pcie->io.start + iobase;
+	port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
+			    (port->bridge.iolimitupper << 16)) -
+			    iobase);
+
+	mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
+					  port->iowin_size,
+					  iobase,
+					  MVEBU_MBUS_PCI_IO);
+
+	pci_ioremap_io(iobase, port->iowin_base);
+}
+
+static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
+{
+	/* Are the new membase/memlimit values invalid? */
+	if (port->bridge.memlimit < port->bridge.membase) {
+
+		/* If a window was configured, remove it */
+		if (port->memwin_base) {
+			mvebu_mbus_del_window(port->memwin_base,
+					      port->memwin_size);
+			port->memwin_base = 0;
+			port->memwin_size = 0;
+		}
+
+		return;
+	}
+
+	/*
+	 * We read the PCI-to-PCI bridge emulated registers, and
+	 * calculate the base address and size of the address decoding
+	 * window to setup, according to the PCI-to-PCI bridge
+	 * specifications.
+	 */
+	port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);
+	port->memwin_size  =
+		(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
+		port->memwin_base;
+
+	mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
+					  port->memwin_size,
+					  MVEBU_MBUS_NO_REMAP,
+					  MVEBU_MBUS_PCI_MEM);
+}
+
+/*
+ * Initialize the configuration space of the PCI-to-PCI bridge
+ * associated with the given PCIe interface.
+ */
+static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
+{
+	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+	memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
+
+	bridge->status = PCI_STATUS_CAP_LIST;
+	bridge->class = PCI_CLASS_BRIDGE_PCI;
+	bridge->vendor = PCI_VENDOR_ID_MARVELL;
+	bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
+	bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
+	bridge->cache_line_size = 0x10;
+
+	/* We support 32 bits I/O addressing */
+	bridge->iobase = PCI_IO_RANGE_TYPE_32;
+	bridge->iolimit = PCI_IO_RANGE_TYPE_32;
+}
+
+/*
+ * Read the configuration space of the PCI-to-PCI bridge associated to
+ * the given PCIe interface.
+ */
+static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
+				  unsigned int where, int size, u32 *value)
+{
+	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+	switch (where & ~3) {
+	case PCI_VENDOR_ID:
+		*value = bridge->device << 16 | bridge->vendor;
+		break;
+
+	case PCI_COMMAND:
+		*value = bridge->status << 16 | bridge->command;
+		break;
+
+	case PCI_CLASS_REVISION:
+		*value = bridge->class << 16 | bridge->interface << 8 |
+			 bridge->revision;
+		break;
+
+	case PCI_CACHE_LINE_SIZE:
+		*value = bridge->bist << 24 | bridge->header_type << 16 |
+			 bridge->latency_timer << 8 | bridge->cache_line_size;
+		break;
+
+	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+		*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
+		break;
+
+	case PCI_PRIMARY_BUS:
+		*value = (bridge->secondary_latency_timer << 24 |
+			  bridge->subordinate_bus         << 16 |
+			  bridge->secondary_bus           <<  8 |
+			  bridge->primary_bus);
+		break;
+
+	case PCI_IO_BASE:
+		*value = (bridge->secondary_status << 16 |
+			  bridge->iolimit          <<  8 |
+			  bridge->iobase);
+		break;
+
+	case PCI_MEMORY_BASE:
+		*value = (bridge->memlimit << 16 | bridge->membase);
+		break;
+
+	case PCI_PREF_MEMORY_BASE:
+		*value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
+		break;
+
+	case PCI_PREF_BASE_UPPER32:
+		*value = bridge->prefbaseupper;
+		break;
+
+	case PCI_PREF_LIMIT_UPPER32:
+		*value = bridge->preflimitupper;
+		break;
+
+	case PCI_IO_BASE_UPPER16:
+		*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
+		break;
+
+	case PCI_ROM_ADDRESS1:
+		*value = 0;
+		break;
+
+	default:
+		*value = 0xffffffff;
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	if (size == 2)
+		*value = (*value >> (8 * (where & 3))) & 0xffff;
+	else if (size == 1)
+		*value = (*value >> (8 * (where & 3))) & 0xff;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/* Write to the PCI-to-PCI bridge configuration space */
+static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
+				     unsigned int where, int size, u32 value)
+{
+	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+	u32 mask, reg;
+	int err;
+
+	if (size == 4)
+		mask = 0x0;
+	else if (size == 2)
+		mask = ~(0xffff << ((where & 3) * 8));
+	else if (size == 1)
+		mask = ~(0xff << ((where & 3) * 8));
+	else
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
+	if (err)
+		return err;
+
+	value = (reg & mask) | value << ((where & 3) * 8);
+
+	switch (where & ~3) {
+	case PCI_COMMAND:
+		bridge->command = value & 0xffff;
+		bridge->status = value >> 16;
+		break;
+
+	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+		bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
+		break;
+
+	case PCI_IO_BASE:
+		/*
+		 * We also keep bit 1 set, it is a read-only bit that
+		 * indicates we support 32 bits addressing for the
+		 * I/O
+		 */
+		bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
+		bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
+		bridge->secondary_status = value >> 16;
+		mvebu_pcie_handle_iobase_change(port);
+		break;
+
+	case PCI_MEMORY_BASE:
+		bridge->membase = value & 0xffff;
+		bridge->memlimit = value >> 16;
+		mvebu_pcie_handle_membase_change(port);
+		break;
+
+	case PCI_PREF_MEMORY_BASE:
+		bridge->prefmembase = value & 0xffff;
+		bridge->prefmemlimit = value >> 16;
+		break;
+
+	case PCI_PREF_BASE_UPPER32:
+		bridge->prefbaseupper = value;
+		break;
+
+	case PCI_PREF_LIMIT_UPPER32:
+		bridge->preflimitupper = value;
+		break;
+
+	case PCI_IO_BASE_UPPER16:
+		bridge->iobaseupper = value & 0xffff;
+		bridge->iolimitupper = value >> 16;
+		mvebu_pcie_handle_iobase_change(port);
+		break;
+
+	case PCI_PRIMARY_BUS:
+		bridge->primary_bus             = value & 0xff;
+		bridge->secondary_bus           = (value >> 8) & 0xff;
+		bridge->subordinate_bus         = (value >> 16) & 0xff;
+		bridge->secondary_latency_timer = (value >> 24) & 0xff;
+		mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
+		break;
+
+	default:
+		break;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+	return sys->private_data;
+}
+
+static struct mvebu_pcie_port *
+mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
+		     int devfn)
+{
+	int i;
+
+	for (i = 0; i < pcie->nports; i++) {
+		struct mvebu_pcie_port *port = &pcie->ports[i];
+		if (bus->number == 0 && port->devfn == devfn)
+			return port;
+		if (bus->number != 0 &&
+		    port->bridge.secondary_bus == bus->number)
+			return port;
+	}
+
+	return NULL;
+}
+
+/* PCI configuration space write function */
+static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+			      int where, int size, u32 val)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+	struct mvebu_pcie_port *port;
+	unsigned long flags;
+	int ret;
+
+	port = mvebu_pcie_find_port(pcie, bus, devfn);
+	if (!port)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	/* Access the emulated PCI-to-PCI bridge */
+	if (bus->number == 0)
+		return mvebu_sw_pci_bridge_write(port, where, size, val);
+
+	if (!port->haslink || PCI_SLOT(devfn) != 0)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	/* Access the real PCIe interface */
+	spin_lock_irqsave(&port->conf_lock, flags);
+	ret = mvebu_pcie_hw_wr_conf(port, bus,
+				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+				    where, size, val);
+	spin_unlock_irqrestore(&port->conf_lock, flags);
+
+	return ret;
+}
+
+/* PCI configuration space read function */
+static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+			      int size, u32 *val)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+	struct mvebu_pcie_port *port;
+	unsigned long flags;
+	int ret;
+
+	port = mvebu_pcie_find_port(pcie, bus, devfn);
+	if (!port) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/* Access the emulated PCI-to-PCI bridge */
+	if (bus->number == 0)
+		return mvebu_sw_pci_bridge_read(port, where, size, val);
+
+	if (!port->haslink || PCI_SLOT(devfn) != 0) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/* Access the real PCIe interface */
+	spin_lock_irqsave(&port->conf_lock, flags);
+	ret = mvebu_pcie_hw_rd_conf(port, bus,
+				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+				    where, size, val);
+	spin_unlock_irqrestore(&port->conf_lock, flags);
+
+	return ret;
+}
+
+static struct pci_ops mvebu_pcie_ops = {
+	.read = mvebu_pcie_rd_conf,
+	.write = mvebu_pcie_wr_conf,
+};
+
+static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(sys);
+	int i;
+
+	pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
+	pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
+	pci_add_resource(&sys->resources, &pcie->busn);
+
+	for (i = 0; i < pcie->nports; i++) {
+		struct mvebu_pcie_port *port = &pcie->ports[i];
+		mvebu_pcie_setup_hw(port);
+	}
+
+	return 1;
+}
+
+static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct of_irq oirq;
+	int ret;
+
+	ret = of_irq_map_pci(dev, &oirq);
+	if (ret)
+		return ret;
+
+	return irq_create_of_mapping(oirq.controller, oirq.specifier,
+				     oirq.size);
+}
+
+static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(sys);
+	struct pci_bus *bus;
+
+	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
+				  &mvebu_pcie_ops, sys, &sys->resources);
+	if (!bus)
+		return NULL;
+
+	pci_scan_child_bus(bus);
+
+	return bus;
+}
+
+resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
+					  const struct resource *res,
+					  resource_size_t start,
+					  resource_size_t size,
+					  resource_size_t align)
+{
+	if (dev->bus->number != 0)
+		return start;
+
+	/*
+	 * On the PCI-to-PCI bridge side, the I/O windows must have at
+	 * least a 64 KB size and be aligned on their size, and the
+	 * memory windows must have at least a 1 MB size and be
+	 * aligned on their size
+	 */
+	if (res->flags & IORESOURCE_IO)
+		return round_up(start, max((resource_size_t)SZ_64K, size));
+	else if (res->flags & IORESOURCE_MEM)
+		return round_up(start, max((resource_size_t)SZ_1M, size));
+	else
+		return start;
+}
+
+static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
+{
+	struct hw_pci hw;
+
+	memset(&hw, 0, sizeof(hw));
+
+	hw.nr_controllers = 1;
+	hw.private_data   = (void **)&pcie;
+	hw.setup          = mvebu_pcie_setup;
+	hw.scan           = mvebu_pcie_scan_bus;
+	hw.map_irq        = mvebu_pcie_map_irq;
+	hw.ops            = &mvebu_pcie_ops;
+	hw.align_resource = mvebu_pcie_align_resource;
+
+	pci_common_init(&hw);
+}
+
+/*
+ * Looks up the list of register addresses encoded into the reg =
+ * <...> property for one that matches the given port/lane. Once
+ * found, maps it.
+ */
+static void __iomem * __init
+mvebu_pcie_map_registers(struct platform_device *pdev,
+			 struct device_node *np,
+			 struct mvebu_pcie_port *port)
+{
+	struct resource regs;
+	int ret = 0;
+
+	ret = of_address_to_resource(np, 0, &regs);
+	if (ret)
+		return NULL;
+
+	return devm_request_and_ioremap(&pdev->dev, &regs);
+}
+
+static int __init mvebu_pcie_probe(struct platform_device *pdev)
+{
+	struct mvebu_pcie *pcie;
+	struct device_node *np = pdev->dev.of_node;
+	struct of_pci_range range;
+	struct of_pci_range_parser parser;
+	struct device_node *child;
+	int i, ret;
+
+	pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
+			    GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pcie->pdev = pdev;
+
+	if (of_pci_range_parser_init(&parser, np))
+		return -EINVAL;
+
+	/* Get the I/O and memory ranges from DT */
+	for_each_of_pci_range(&parser, &range) {
+		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+		if (restype == IORESOURCE_IO) {
+			of_pci_range_to_resource(&range, np, &pcie->io);
+			of_pci_range_to_resource(&range, np, &pcie->realio);
+			pcie->io.name = "I/O";
+			pcie->realio.start = max_t(resource_size_t,
+						   PCIBIOS_MIN_IO,
+						   range.pci_addr);
+			pcie->realio.end = min_t(resource_size_t,
+						 IO_SPACE_LIMIT,
+						 range.pci_addr + range.size);
+		}
+		if (restype == IORESOURCE_MEM) {
+			of_pci_range_to_resource(&range, np, &pcie->mem);
+			pcie->mem.name = "MEM";
+		}
+	}
+
+	/* Get the bus range */
+	ret = of_pci_parse_bus_range(np, &pcie->busn);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
+			ret);
+		return ret;
+	}
+
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		if (!of_device_is_available(child))
+			continue;
+		pcie->nports++;
+	}
+
+	pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
+				   sizeof(struct mvebu_pcie_port),
+				   GFP_KERNEL);
+	if (!pcie->ports)
+		return -ENOMEM;
+
+	i = 0;
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		struct mvebu_pcie_port *port = &pcie->ports[i];
+
+		if (!of_device_is_available(child))
+			continue;
+
+		port->pcie = pcie;
+
+		if (of_property_read_u32(child, "marvell,pcie-port",
+					 &port->port)) {
+			dev_warn(&pdev->dev,
+				 "ignoring PCIe DT node, missing pcie-port property\n");
+			continue;
+		}
+
+		if (of_property_read_u32(child, "marvell,pcie-lane",
+					 &port->lane))
+			port->lane = 0;
+
+		port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
+				       port->port, port->lane);
+
+		port->devfn = of_pci_get_devfn(child);
+		if (port->devfn < 0)
+			continue;
+
+		port->base = mvebu_pcie_map_registers(pdev, child, port);
+		if (!port->base) {
+			dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
+				port->port, port->lane);
+			continue;
+		}
+
+		if (mvebu_pcie_link_up(port)) {
+			port->haslink = 1;
+			dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
+				 port->port, port->lane);
+		} else {
+			port->haslink = 0;
+			dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
+				 port->port, port->lane);
+		}
+
+		port->clk = of_clk_get_by_name(child, NULL);
+		if (!port->clk) {
+			dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
+			       port->port, port->lane);
+			iounmap(port->base);
+			port->haslink = 0;
+			continue;
+		}
+
+		port->dn = child;
+
+		clk_prepare_enable(port->clk);
+		spin_lock_init(&port->conf_lock);
+
+		mvebu_sw_pci_bridge_init(port);
+
+		i++;
+	}
+
+	mvebu_pcie_enable(pcie);
+
+	return 0;
+}
+
+static const struct of_device_id mvebu_pcie_of_match_table[] = {
+	{ .compatible = "marvell,armada-xp-pcie", },
+	{ .compatible = "marvell,armada-370-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
+
+static struct platform_driver mvebu_pcie_driver = {
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "mvebu-pcie",
+		.of_match_table =
+		   of_match_ptr(mvebu_pcie_of_match_table),
+	},
+};
+
+static int __init mvebu_pcie_init(void)
+{
+	return platform_driver_probe(&mvebu_pcie_driver,
+				     mvebu_pcie_probe);
+}
+
+subsys_initcall(mvebu_pcie_init);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni at free-electrons.com>");
+MODULE_DESCRIPTION("Marvell EBU PCIe driver");
+MODULE_LICENSE("GPLv2");
-- 
1.7.9.5



From tony at atomide.com  Thu May 16 11:58:57 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 08:58:57 -0700
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <51936946.3030507@iki.fi>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
 <51936946.3030507@iki.fi>
Message-ID: <20130516155857.GV5600@atomide.com>

* Tomi Valkeinen <tomi.valkeinen at iki.fi> [130515 03:59]:
> On 23/04/13 09:14, Kishon Vijay Abraham I wrote:
> > After the device names are created using PLATFORM_DEVID_AUTO, the old
> > device names given in usb_bind_phy are no longer valid causing the musb
> > controller not to get the phy reference. Updated the usb_bind_phy with
> > the new device names to get MUSB functional in omap4 panda.
> > 
> > Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> > ---
> > Tested in OMAP4 PANDA.
> >  arch/arm/mach-omap2/board-4430sdp.c    |    2 +-
> >  arch/arm/mach-omap2/board-omap4panda.c |    2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
> > index 00d7290..56a9a4f 100644
> > --- a/arch/arm/mach-omap2/board-4430sdp.c
> > +++ b/arch/arm/mach-omap2/board-4430sdp.c
> > @@ -730,7 +730,7 @@ static void __init omap_4430sdp_init(void)
> >  	omap4_sdp4430_wifi_init();
> >  	omap4_twl6030_hsmmc_init(mmc);
> >  
> > -	usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
> > +	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
> >  	usb_musb_init(&musb_board_data);
> >  
> >  	status = omap_ethernet_init();
> 
> I'm seeing
> 
> [    2.190155] unable to find transceiver
> [    2.190155] HS USB OTG: no transceiver configured
> [    2.190155] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed
> with status -517
> [    2.207458] platform musb-hdrc.0.auto: Driver musb-hdrc requests
> probe deferral
> 
> on 4430sdp with v3.10-rc1. Does that mean that the musb-hdrc.0.auto was
> indeed correct, and the new value of musb-hdrc.2.auto is not?

Just checking.. Do you have CONFIG_OMAP_OCP2SCP=y in your .config? Sounds
like the some transceivers should depend on that for omap4.
 
> The musb-hdrc id is wrong on overo also.

Hmm has there been a fix posted for that?

Regards,

Tony


From lorenzo.pieralisi at arm.com  Thu May 16 11:34:05 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 16 May 2013 16:34:05 +0100
Subject: [PATCH 1/3] ARM: DT: kernel: move temporary cpu map stack array to
 static data
In-Reply-To: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368718447-19209-2-git-send-email-lorenzo.pieralisi@arm.com>

As the number of CPUs increase, the temporary array allocated on the
stack in arm_dt_init_cpu_maps() can become too big and trigger stack
issues.
This patch moves the allocated memory to static __initdata so that stack
data is not used anymore to allocate the temporary array.
Memory is marked as __initdata since it need not be persistent after boot.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/kernel/devtree.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..3d652e4f 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -78,11 +78,12 @@ void __init arm_dt_init_cpu_maps(void)
 	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
 	 * read as 0.
 	 */
+	static u32 tmp_map[NR_CPUS] __initdata = {
+				[0 ... NR_CPUS-1] = UINT_MAX };
 	struct device_node *cpu, *cpus;
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 
-- 
1.8.2.2



From thomas.petazzoni at free-electrons.com  Thu May 16 12:07:24 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 18:07:24 +0200
Subject: [PATCH] arm: mvebu: enable the third USB interface on OpenBlocks AX3
Message-ID: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>

Besides the two "classic" USB interfaces with normal USB ports on the
front side, the PlatHome OpenBlocks AX3 uses the third USB interface
of the Marvell SoC in the mini-PCIe connector. This allows certain
mini-PCIe cards to expose parts of their functionality as a USB
peripheral.

This commit enables this third USB interface in the OpenBlocks AX3
Device Tree, and also adds comments on top of the two other USB
interfaces so that the Device Tree makes it clear which USB interface
at the SoC level matches which USB interface visible on the board.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index f14d36c..60a79e7 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -134,13 +134,22 @@
 				nr-ports = <2>;
 				status = "okay";
 			};
+
+			/* Front side USB 0 */
 			usb at 50000 {
 				status = "okay";
 			};
+
+			/* Front side USB 1 */
 			usb at 51000 {
 				status = "okay";
 			};
 
+			/* USB interface in the mini-PCIe connector */
+			usb at 52000 {
+				status = "okay";
+			};
+
 			devbus-bootcs at 10400 {
 				status = "okay";
 				ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 16 12:08:50 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 18:08:50 +0200
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <20130516155617.GH6563@titan.lakedaemon.net>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130516093312.GB2459@localhost>
 <20130516154031.GF6563@titan.lakedaemon.net>
 <20130516174903.3a7a07ef@skate>
 <20130516155617.GH6563@titan.lakedaemon.net>
Message-ID: <20130516180850.3622e1a8@skate>

Dear Jason Cooper,

On Thu, 16 May 2013 11:56:17 -0400, Jason Cooper wrote:

> > > > Building this showed a warning here. It seems you forgot
> > > > to mark this one as __init.
> > > 
> > > Thomas, I'll fix this up when I pull this in, no need to resend. :)
> > 
> > I'll resend, because beyond this function pointed by Ezequiel, there
> > are two other functions that can be marked __init. The one pointed by
> > Ezequiel is important because it causes a section mismatch
> > when !CONFIG_MODULES, because in this case platform_driver_probe() is
> > __init (and this explains what I wasn't seeing the warning, since I'm
> > building CONFIG_MODULES=y). The two other functions are more cosmetic,
> > but good to have as well.
> > 
> > It would already been sent if git hadn't decided to do a 'git gc' right
> > after my rebase. It's been gc-ing for quite some time now...
> 
> Dear boss,
> 
> I am in desperate need of a 500GB SSD on which to do my kernel work.
> 
> Thanks,
> 
> Kranky Kernel Developer
> 
> hehehe...

Adding boss in the Cc list :-)

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jason at lakedaemon.net  Thu May 16 12:12:02 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 12:12:02 -0400
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <20130516180850.3622e1a8@skate>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130516093312.GB2459@localhost>
 <20130516154031.GF6563@titan.lakedaemon.net>
 <20130516174903.3a7a07ef@skate>
 <20130516155617.GH6563@titan.lakedaemon.net>
 <20130516180850.3622e1a8@skate>
Message-ID: <20130516161201.GI6563@titan.lakedaemon.net>

On Thu, May 16, 2013 at 06:08:50PM +0200, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Thu, 16 May 2013 11:56:17 -0400, Jason Cooper wrote:
> 
> > > > > Building this showed a warning here. It seems you forgot
> > > > > to mark this one as __init.
> > > > 
> > > > Thomas, I'll fix this up when I pull this in, no need to resend. :)
> > > 
> > > I'll resend, because beyond this function pointed by Ezequiel, there
> > > are two other functions that can be marked __init. The one pointed by
> > > Ezequiel is important because it causes a section mismatch
> > > when !CONFIG_MODULES, because in this case platform_driver_probe() is
> > > __init (and this explains what I wasn't seeing the warning, since I'm
> > > building CONFIG_MODULES=y). The two other functions are more cosmetic,
> > > but good to have as well.
> > > 
> > > It would already been sent if git hadn't decided to do a 'git gc' right
> > > after my rebase. It's been gc-ing for quite some time now...
> > 
> > Dear boss,
> > 
> > I am in desperate need of a 500GB SSD on which to do my kernel work.
> > 
> > Thanks,
> > 
> > Kranky Kernel Developer
> > 
> > hehehe...
> 
> Adding boss in the Cc list :-)

Hey, whatever works for you.  Good luck!

thx,

Jason.


From tomi.valkeinen at iki.fi  Thu May 16 12:05:46 2013
From: tomi.valkeinen at iki.fi (Tomi Valkeinen)
Date: Thu, 16 May 2013 19:05:46 +0300
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <20130516155857.GV5600@atomide.com>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
 <51936946.3030507@iki.fi> <20130516155857.GV5600@atomide.com>
Message-ID: <519503DA.5070303@iki.fi>

On 16/05/13 18:58, Tony Lindgren wrote:
> * Tomi Valkeinen <tomi.valkeinen at iki.fi> [130515 03:59]:
>> On 23/04/13 09:14, Kishon Vijay Abraham I wrote:
>>> After the device names are created using PLATFORM_DEVID_AUTO, the old
>>> device names given in usb_bind_phy are no longer valid causing the musb
>>> controller not to get the phy reference. Updated the usb_bind_phy with
>>> the new device names to get MUSB functional in omap4 panda.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>>> ---
>>> Tested in OMAP4 PANDA.
>>>  arch/arm/mach-omap2/board-4430sdp.c    |    2 +-
>>>  arch/arm/mach-omap2/board-omap4panda.c |    2 +-
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
>>> index 00d7290..56a9a4f 100644
>>> --- a/arch/arm/mach-omap2/board-4430sdp.c
>>> +++ b/arch/arm/mach-omap2/board-4430sdp.c
>>> @@ -730,7 +730,7 @@ static void __init omap_4430sdp_init(void)
>>>  	omap4_sdp4430_wifi_init();
>>>  	omap4_twl6030_hsmmc_init(mmc);
>>>  
>>> -	usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
>>> +	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
>>>  	usb_musb_init(&musb_board_data);
>>>  
>>>  	status = omap_ethernet_init();
>>
>> I'm seeing
>>
>> [    2.190155] unable to find transceiver
>> [    2.190155] HS USB OTG: no transceiver configured
>> [    2.190155] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed
>> with status -517
>> [    2.207458] platform musb-hdrc.0.auto: Driver musb-hdrc requests
>> probe deferral
>>
>> on 4430sdp with v3.10-rc1. Does that mean that the musb-hdrc.0.auto was
>> indeed correct, and the new value of musb-hdrc.2.auto is not?
> 
> Just checking.. Do you have CONFIG_OMAP_OCP2SCP=y in your .config? Sounds
> like the some transceivers should depend on that for omap4.

Yes, I have OCP2SCP=y.

>> The musb-hdrc id is wrong on overo also.
> 
> Hmm has there been a fix posted for that?

I couldn't find with a quick look. We debugged and discussed this on an irc
channel with Kishon, who said he'll send a patch. Changing the musb-hdrc ID
on overo fixed the issue, and it looks very similar to the error on 4430sdp.
The overo fix was just:

diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4ca6b68..a496774 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -472,7 +472,7 @@ static void __init overo_init(void)
                                  mt46h32m32lf6_sdrc_params);
        board_nand_init(overo_nand_partitions,
                        ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
-       usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
+       usb_bind_phy("musb-hdrc.1.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
 
        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));


Is that ID "randomly" chosen? Doesn't that mean that it'll just get broken
every now and then?

 Tomi



From holt at sgi.com  Thu May 16 12:14:42 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:42 -0500
Subject: [PATCH -v11 resend 03/11] Remove -stable friendly PF_THREAD_BOUND
 define
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-4-git-send-email-holt@sgi.com>

Remove the prior patch's #define for easier backporting to the stable
releases.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
---
 kernel/sys.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index 2bbd9a7..17bb8d3 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,11 +362,6 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
-/* Add backwards compatibility for stable trees. */
-#ifndef PF_NO_SETAFFINITY
-#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
-#endif
-
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:40 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:40 -0500
Subject: [PATCH -v11 resend 01/11] CPU hotplug: Provide a generic helper to
 disable/enable CPU hotplug
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-2-git-send-email-holt@sgi.com>

From: "Srivatsa S. Bhat" <srivatsa.bhat at linux.vnet.ibm.com>

There are instances in the kernel where we would like to disable
CPU hotplug (from sysfs) during some important operation. Today
the freezer code depends on this and the code to do it was kinda
tailor-made for that.

Restructure the code and make it generic enough to be useful for
other usecases too.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat at linux.vnet.ibm.com>
Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>
---
 include/linux/cpu.h |  4 ++++
 kernel/cpu.c        | 55 ++++++++++++++++++++++-------------------------------
 2 files changed, 27 insertions(+), 32 deletions(-)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e08..9f3c7e8 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
 
 extern void get_online_cpus(void);
 extern void put_online_cpus(void);
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
@@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
 
 #define get_online_cpus()	do { } while (0)
 #define put_online_cpus()	do { } while (0)
+#define cpu_hotplug_disable()	do { } while (0)
+#define cpu_hotplug_enable()	do { } while (0)
 #define hotcpu_notifier(fn, pri)	do { (void)(fn); } while (0)
 /* These aren't inline functions due to a GCC bug. */
 #define register_hotcpu_notifier(nb)	({ (void)(nb); 0; })
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2..198a388 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
 	mutex_unlock(&cpu_hotplug.lock);
 }
 
+/*
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
+ */
+void cpu_hotplug_disable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 1;
+	cpu_maps_update_done();
+}
+
+void cpu_hotplug_enable(void)
+{
+	cpu_maps_update_begin();
+	cpu_hotplug_disabled = 0;
+	cpu_maps_update_done();
+}
+
 #else /* #if CONFIG_HOTPLUG_CPU */
 static void cpu_hotplug_begin(void) {}
 static void cpu_hotplug_done(void) {}
@@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
- */
-void cpu_hotplug_disable_before_freeze(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 1;
-	cpu_maps_update_done();
-}
-
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
-{
-	cpu_maps_update_begin();
-	cpu_hotplug_disabled = 0;
-	cpu_maps_update_done();
-}
-
-/*
  * When callbacks for CPU hotplug notifications are being executed, we must
  * ensure that the state of the system with respect to the tasks being frozen
  * or not, as reported by the notification, remains unchanged *throughout the
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
 	case PM_SUSPEND_PREPARE:
 	case PM_HIBERNATION_PREPARE:
-		cpu_hotplug_disable_before_freeze();
+		cpu_hotplug_disable();
 		break;
 
 	case PM_POST_SUSPEND:
 	case PM_POST_HIBERNATION:
-		cpu_hotplug_enable_after_thaw();
+		cpu_hotplug_enable();
 		break;
 
 	default:
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:44 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:44 -0500
Subject: [PATCH -v11 resend 05/11] checkpatch.pl the new kernel/reboot.c file.
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-6-git-send-email-holt@sgi.com>

Get the new file to pass scripts/checkpatch.pl

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since v6:
 - Removed last remaining line length warning.
---
 include/linux/reboot.h |  2 +-
 kernel/reboot.c        | 28 +++++++++++++---------------
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 23b3630..c6eba21 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -26,7 +26,7 @@ extern void machine_shutdown(void);
 struct pt_regs;
 extern void machine_crash_shutdown(struct pt_regs *);
 
-/* 
+/*
  * Architecture independent implemenations of sys_reboot commands.
  */
 
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 0616483..abb6a04 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -4,6 +4,8 @@
  *  Copyright (C) 2013  Linus Torvalds
  */
 
+#define pr_fmt(fmt)	"reboot: " fmt
+
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -114,9 +116,9 @@ void kernel_restart(char *cmd)
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
+		pr_emerg("Restarting system\n");
 	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+		pr_emerg("Restarting system with command '%s'\n", cmd);
 	kmsg_dump(KMSG_DUMP_RESTART);
 	machine_restart(cmd);
 }
@@ -125,7 +127,7 @@ EXPORT_SYMBOL_GPL(kernel_restart);
 static void kernel_shutdown_prepare(enum system_states state)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
 	usermodehelper_disable();
 	device_shutdown();
@@ -140,11 +142,10 @@ void kernel_halt(void)
 	kernel_shutdown_prepare(SYSTEM_HALT);
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
+	pr_emerg("System halted\n");
 	kmsg_dump(KMSG_DUMP_HALT);
 	machine_halt();
 }
-
 EXPORT_SYMBOL_GPL(kernel_halt);
 
 /**
@@ -159,7 +160,7 @@ void kernel_power_off(void)
 		pm_power_off_prepare();
 	migrate_to_reboot_cpu();
 	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
+	pr_emerg("Power down\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
 	machine_power_off();
 }
@@ -188,10 +189,10 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 
 	/* For safety, we require "magic" arguments. */
 	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			(magic2 != LINUX_REBOOT_MAGIC2 &&
+			magic2 != LINUX_REBOOT_MAGIC2A &&
 			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
+			magic2 != LINUX_REBOOT_MAGIC2C))
 		return -EINVAL;
 
 	/*
@@ -234,7 +235,8 @@ SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
 		break;
 
 	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+		ret = strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1);
+		if (ret < 0) {
 			ret = -EFAULT;
 			break;
 		}
@@ -282,7 +284,6 @@ void ctrl_alt_del(void)
 	else
 		kill_cad_pid(SIGINT, 1);
 }
-	
 
 char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
 
@@ -301,14 +302,11 @@ static int __orderly_poweroff(bool force)
 		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
 		argv_free(argv);
 	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
 		ret = -ENOMEM;
 	}
 
 	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
+		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 		/*
 		 * I guess this should try to kick off some daemon to sync and
 		 * poweroff asap.  Or not even bother syncing if we're doing an
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:39 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:39 -0500
Subject: [PATCH -v11 resend 00/11] Shutdown from reboot_cpuid without stopping
 other cpus.
Message-ID: <1368720890-57711-1-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
reboot_cpu and then continuing with shutdown/reboot.

The patch set is broken into eleven parts.  The first two are planned for
the stable release.  The others move the halt/shutdown/reboot related
functions to their own kernel/reboot.c file and then move the handling
of the kernel reboot= kernel parameter to generic kernel code.

Changes since -v10
 - Added Russell's Acked-by for arm.

 - Fixed an accidentally commented out line in an arm header file.

Changes since -v9
 - Added Ingo's Acked-by for x86.

 - Added Guan's Acked-by for unicore32.

 - Replaced first patch with updated patch from Srivatsa S. Bhat.
   This compiles for alpha allmodconfig, all arm defconfigs, and a few
   test x86_64 defconfigs.  I have not tried more.

Changes since -v8
 - Changes reboot_cpu on stack to cpu to fix bug noticed by Russell King.

 - Switched unicore32 and arm from using REBOOT_WARM/COLD to HARD/SOFT.

 - Fixed case statement bug.

 - Went to using simple_strtoul for parsing reboot_cpu=smp###.

 - Made parsing of reboot= not use any #ifdef'd code.

Changes since -v7.
 - Fixed authorship for first patch.

 - Rebased to Linus' current tree (51a26ae7a).

Changes since -v6.
 - Cross compiled all arm architectures (using v3.9 kernel.  Fails with
   current).

 - Added a #define for non-hotplug case.

 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.

 - Fixup s/reboot_cpu_id/reboot_cpu/

 - Add include of linux/uaccess.h to allow building on arm.

 - Removed last remaining checkpatch.pl line length warning on
   kernel/reboot.c.

 - Fixed the duplicate handling or the reboot= kernel parameter.

Changes since -v5.
 - Moved the arch/x86 reboot= up to the generic kernel code.

Changes since -v4.
 - Integrated Srivatsa S. Bhat creating cpu_hotplug_disable()
   function

 - Integrated comments by Srivatsa S. Bhat.

 - Made one more comment consistent with others in function.

Changes since -v3.
 - Added a tested-by for the original reporter.

 - Fix compile failure found by Joe Perches.

 - Integrated comments by Joe Perches.


To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>


From holt at sgi.com  Thu May 16 12:14:41 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:41 -0500
Subject: [PATCH -v11 resend 02/11] Migrate shutdown/reboot to boot cpu.
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-3-git-send-email-holt@sgi.com>

We recently noticed that reboot of a 1024 cpu machine takes approx 16
minutes of just stopping the cpus.  The slowdown was tracked to commit
f96972f.

The current implementation does all the work of hot removing the cpus
before halting the system.  We are switching to just migrating to the
boot cpu and then continuing with shutdown/reboot.

This also has the effect of not breaking x86's command line parameter for
specifying the reboot cpu.  Note, this code was shamelessly copied from
arch/x86/kernel/reboot.c with bits removed pertaining to the reboot_cpu
command line parameter.

Signed-off-by: Robin Holt <holt at sgi.com>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Cc: <stable at vger.kernel.org>

---

Changes since -v8
 - Change stack parameter to make future patches cleaner.

Changes since -v6:
 - Add #define for PF_THREAD_BOUND as compatibility to make stable easier.
 - Fixup s/reboot_cpu_id/reboot_cpu/
---
 kernel/sys.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c7..2bbd9a7 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY		PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
 /**
  *	kernel_restart - reboot the system
  *	@cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
 	kernel_restart_prepare(cmd);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	if (!cmd)
 		printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
 	kernel_shutdown_prepare(SYSTEM_HALT);
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
 	if (pm_power_off_prepare)
 		pm_power_off_prepare();
-	disable_nonboot_cpus();
+	migrate_to_reboot_cpu();
 	syscore_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	kmsg_dump(KMSG_DUMP_POWEROFF);
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:46 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:46 -0500
Subject: [PATCH -v11 resend 07/11] unicore32,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-8-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>
---

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/unicore32/kernel/process.c | 10 +++++-----
 arch/unicore32/kernel/setup.h   |  2 +-
 arch/unicore32/mm/mmu.c         |  2 +-
 include/linux/reboot.h          |  2 ++
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index c944769..93dd035 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,14 +51,14 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static char reboot_mode = 'h';
+static enum reboot_mode reboot_mode = REBOOT_HARD;
 
 int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
@@ -88,7 +88,7 @@ void machine_restart(char *cmd)
 	 * we may need it to insert some 1:1 mappings so that
 	 * soft boot works.
 	 */
-	setup_mm_for_reboot(reboot_mode);
+	setup_mm_for_reboot();
 
 	/* Clean and invalidate caches */
 	flush_cache_all();
@@ -102,7 +102,7 @@ void machine_restart(char *cmd)
 	/*
 	 * Now handle reboot code.
 	 */
-	if (reboot_mode == 's') {
+	if (reboot_mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index 30f749d..f5c51b8 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -22,7 +22,7 @@ extern void puv3_ps2_init(void);
 extern void pci_puv3_preinit(void);
 extern void __init puv3_init_gpio(void);
 
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 
 extern char __stubs_start[], __stubs_end[];
 extern char __vectors_start[], __vectors_end[];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index 43c20b4..4f5a532 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -445,7 +445,7 @@ void __init paging_init(void)
  * the user-mode pages.  This will then ensure that we have predictable
  * results when turning the mmu off
  */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 	unsigned long base_pmdval;
 	pgd_t *pgd;
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 37d56c3..ca29a6f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -13,6 +13,8 @@
 enum reboot_mode {
 	REBOOT_COLD = 0,
 	REBOOT_WARM,
+	REBOOT_HARD,
+	REBOOT_SOFT,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:45 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:45 -0500
Subject: [PATCH -v11 resend 06/11] x86,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-7-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Miguel Boton <mboton.lkml at gmail.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Ingo Molnar <mingo at kernel.org>
---
 arch/x86/kernel/reboot.c | 12 +++++++-----
 include/linux/reboot.h   |  5 +++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 76fa1e9..f770340 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,7 +36,7 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static int reboot_mode;
+static enum reboot_mode reboot_mode;
 enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
@@ -88,11 +88,11 @@ static int __init reboot_setup(char *str)
 
 		switch (*str) {
 		case 'w':
-			reboot_mode = 0x1234;
+			reboot_mode = REBOOT_WARM;
 			break;
 
 		case 'c':
-			reboot_mode = 0;
+			reboot_mode = REBOOT_COLD;
 			break;
 
 #ifdef CONFIG_SMP
@@ -536,6 +536,7 @@ static void native_machine_emergency_restart(void)
 	int i;
 	int attempt = 0;
 	int orig_reboot_type = reboot_type;
+	unsigned short mode;
 
 	if (reboot_emergency)
 		emergency_vmx_disable_all();
@@ -543,7 +544,8 @@ static void native_machine_emergency_restart(void)
 	tboot_shutdown(TB_SHUTDOWN_REBOOT);
 
 	/* Tell the BIOS if we want cold or warm reboot */
-	*((unsigned short *)__va(0x472)) = reboot_mode;
+	mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
+	*((unsigned short *)__va(0x472)) = mode;
 
 	for (;;) {
 		/* Could also try the reset bit in the Hammer NB */
@@ -585,7 +587,7 @@ static void native_machine_emergency_restart(void)
 
 		case BOOT_EFI:
 			if (efi_enabled(EFI_RUNTIME_SERVICES))
-				efi.reset_system(reboot_mode ?
+				efi.reset_system(reboot_mode == REBOOT_WARM ?
 						 EFI_RESET_WARM :
 						 EFI_RESET_COLD,
 						 EFI_SUCCESS, 0, NULL);
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index c6eba21..37d56c3 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -10,6 +10,11 @@
 #define SYS_HALT	0x0002	/* Notify of system halt */
 #define SYS_POWER_OFF	0x0003	/* Notify of system power off */
 
+enum reboot_mode {
+	REBOOT_COLD = 0,
+	REBOOT_WARM,
+};
+
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
 
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:47 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:47 -0500
Subject: [PATCH -v11 resend 08/11] arm,
 Remove unused restart_mode fields from some arm subarchs
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-9-git-send-email-holt@sgi.com>

These restart_mode fields are not used at all.  Remove them to make
moving the reboot= cmdline options to the general kernel easier.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/mach-ebsa110/core.c | 1 -
 arch/arm/mach-pxa/mioa701.c  | 1 -
 arch/arm/mach-pxa/spitz.c    | 3 ---
 arch/arm/mach-pxa/tosa.c     | 1 -
 4 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74..69a9d5d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
 	.atag_offset	= 0x400,
 	.reserve_lp0	= 1,
 	.reserve_lp2	= 1,
-	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
 	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b9..dbea67a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -756,7 +756,6 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
 	.map_io		= &pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
 	.init_irq	= &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..c3c0042 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,7 +979,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -993,7 +992,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
@@ -1007,7 +1005,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-	.restart_mode	= 'g',
 	.fixup		= spitz_fixup,
 	.map_io		= pxa27x_map_io,
 	.nr_irqs	= PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e..a41992f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -969,7 +969,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-	.restart_mode	= 'g',
 	.fixup          = fixup_tosa,
 	.map_io         = pxa25x_map_io,
 	.nr_irqs	= TOSA_NR_IRQS,
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:43 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:43 -0500
Subject: [PATCH -v11 resend 04/11] Move shutdown/reboot related functions to
 kernel/reboot.c
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-5-git-send-email-holt@sgi.com>

This patch is preparatory.  It moves reboot related syscall, etc
functions from kernel/sys.c to kernel/reboot.c.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>

---

Changes since -v6:
 - Add include of linux/uaccess.h to allow building on arm.
---
 kernel/Makefile |   2 +-
 kernel/reboot.c | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/sys.c    | 331 -----------------------------------------------------
 3 files changed, 348 insertions(+), 332 deletions(-)
 create mode 100644 kernel/reboot.c

diff --git a/kernel/Makefile b/kernel/Makefile
index 271fd31..470839d 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y     = fork.o exec_domain.o panic.o printk.o \
 	    rcupdate.o extable.o params.o posix-timers.o \
 	    kthread.o wait.o sys_ni.o posix-cpu-timers.o mutex.o \
 	    hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-	    notifier.o ksysfs.o cred.o \
+	    notifier.o ksysfs.o cred.o reboot.o \
 	    async.o range.o groups.o lglock.o smpboot.o
 
 ifdef CONFIG_FUNCTION_TRACER
diff --git a/kernel/reboot.c b/kernel/reboot.c
new file mode 100644
index 0000000..0616483
--- /dev/null
+++ b/kernel/reboot.c
@@ -0,0 +1,347 @@
+/*
+ *  linux/kernel/reboot.c
+ *
+ *  Copyright (C) 2013  Linus Torvalds
+ */
+
+#include <linux/export.h>
+#include <linux/kexec.h>
+#include <linux/kmod.h>
+#include <linux/kmsg_dump.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h>
+#include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
+
+/*
+ * this indicates whether you can reboot with ctrl-alt-del: the default is yes
+ */
+
+int C_A_D = 1;
+struct pid *cad_pid;
+EXPORT_SYMBOL(cad_pid);
+
+/*
+ * If set, this is used for preparing the system to power off.
+ */
+
+void (*pm_power_off_prepare)(void);
+
+/**
+ *	emergency_restart - reboot the system
+ *
+ *	Without shutting down any hardware or taking any locks
+ *	reboot the system.  This is called when we know we are in
+ *	trouble so this is our best effort to reboot.  This is
+ *	safe to call in interrupt context.
+ */
+void emergency_restart(void)
+{
+	kmsg_dump(KMSG_DUMP_EMERG);
+	machine_emergency_restart();
+}
+EXPORT_SYMBOL_GPL(emergency_restart);
+
+void kernel_restart_prepare(char *cmd)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
+	system_state = SYSTEM_RESTART;
+	usermodehelper_disable();
+	device_shutdown();
+}
+
+/**
+ *	register_reboot_notifier - Register function to be called at reboot time
+ *	@nb: Info about notifier function to be called
+ *
+ *	Registers a function with the list of functions
+ *	to be called at reboot time.
+ *
+ *	Currently always returns zero, as blocking_notifier_chain_register()
+ *	always returns zero.
+ */
+int register_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(register_reboot_notifier);
+
+/**
+ *	unregister_reboot_notifier - Unregister previously registered reboot notifier
+ *	@nb: Hook to be unregistered
+ *
+ *	Unregisters a previously registered reboot
+ *	notifier function.
+ *
+ *	Returns zero on success, or %-ENOENT on failure.
+ */
+int unregister_reboot_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
+}
+EXPORT_SYMBOL(unregister_reboot_notifier);
+
+static void migrate_to_reboot_cpu(void)
+{
+	/* The boot cpu is always logical cpu 0 */
+	int cpu = 0;
+
+	cpu_hotplug_disable();
+
+	/* Make certain the cpu I'm about to reboot on is online */
+	if (!cpu_online(cpu))
+		cpu = cpumask_first(cpu_online_mask);
+
+	/* Prevent races with other tasks migrating this task */
+	current->flags |= PF_NO_SETAFFINITY;
+
+	/* Make certain I only run on the appropriate processor */
+	set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
+/**
+ *	kernel_restart - reboot the system
+ *	@cmd: pointer to buffer containing command to execute for restart
+ *		or %NULL
+ *
+ *	Shutdown everything and perform a clean reboot.
+ *	This is not safe to call in interrupt context.
+ */
+void kernel_restart(char *cmd)
+{
+	kernel_restart_prepare(cmd);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	if (!cmd)
+		printk(KERN_EMERG "Restarting system.\n");
+	else
+		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
+	kmsg_dump(KMSG_DUMP_RESTART);
+	machine_restart(cmd);
+}
+EXPORT_SYMBOL_GPL(kernel_restart);
+
+static void kernel_shutdown_prepare(enum system_states state)
+{
+	blocking_notifier_call_chain(&reboot_notifier_list,
+		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
+	system_state = state;
+	usermodehelper_disable();
+	device_shutdown();
+}
+/**
+ *	kernel_halt - halt the system
+ *
+ *	Shutdown everything and perform a clean system halt.
+ */
+void kernel_halt(void)
+{
+	kernel_shutdown_prepare(SYSTEM_HALT);
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "System halted.\n");
+	kmsg_dump(KMSG_DUMP_HALT);
+	machine_halt();
+}
+
+EXPORT_SYMBOL_GPL(kernel_halt);
+
+/**
+ *	kernel_power_off - power_off the system
+ *
+ *	Shutdown everything and perform a clean system power_off.
+ */
+void kernel_power_off(void)
+{
+	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
+	if (pm_power_off_prepare)
+		pm_power_off_prepare();
+	migrate_to_reboot_cpu();
+	syscore_shutdown();
+	printk(KERN_EMERG "Power down.\n");
+	kmsg_dump(KMSG_DUMP_POWEROFF);
+	machine_power_off();
+}
+EXPORT_SYMBOL_GPL(kernel_power_off);
+
+static DEFINE_MUTEX(reboot_mutex);
+
+/*
+ * Reboot system call: for obvious reasons only root may call it,
+ * and even root needs to set up some magic numbers in the registers
+ * so that some mistake won't make this reboot the whole machine.
+ * You can also set the meaning of the ctrl-alt-del-key here.
+ *
+ * reboot doesn't sync: do that yourself before calling this.
+ */
+SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
+		void __user *, arg)
+{
+	struct pid_namespace *pid_ns = task_active_pid_ns(current);
+	char buffer[256];
+	int ret = 0;
+
+	/* We only trust the superuser with rebooting the system. */
+	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
+		return -EPERM;
+
+	/* For safety, we require "magic" arguments. */
+	if (magic1 != LINUX_REBOOT_MAGIC1 ||
+	    (magic2 != LINUX_REBOOT_MAGIC2 &&
+	                magic2 != LINUX_REBOOT_MAGIC2A &&
+			magic2 != LINUX_REBOOT_MAGIC2B &&
+	                magic2 != LINUX_REBOOT_MAGIC2C))
+		return -EINVAL;
+
+	/*
+	 * If pid namespaces are enabled and the current task is in a child
+	 * pid_namespace, the command is handled by reboot_pid_ns() which will
+	 * call do_exit().
+	 */
+	ret = reboot_pid_ns(pid_ns, cmd);
+	if (ret)
+		return ret;
+
+	/* Instead of trying to make the power_off code look like
+	 * halt when pm_power_off is not set do it the easy way.
+	 */
+	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
+		cmd = LINUX_REBOOT_CMD_HALT;
+
+	mutex_lock(&reboot_mutex);
+	switch (cmd) {
+	case LINUX_REBOOT_CMD_RESTART:
+		kernel_restart(NULL);
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_ON:
+		C_A_D = 1;
+		break;
+
+	case LINUX_REBOOT_CMD_CAD_OFF:
+		C_A_D = 0;
+		break;
+
+	case LINUX_REBOOT_CMD_HALT:
+		kernel_halt();
+		do_exit(0);
+		panic("cannot halt");
+
+	case LINUX_REBOOT_CMD_POWER_OFF:
+		kernel_power_off();
+		do_exit(0);
+		break;
+
+	case LINUX_REBOOT_CMD_RESTART2:
+		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
+			ret = -EFAULT;
+			break;
+		}
+		buffer[sizeof(buffer) - 1] = '\0';
+
+		kernel_restart(buffer);
+		break;
+
+#ifdef CONFIG_KEXEC
+	case LINUX_REBOOT_CMD_KEXEC:
+		ret = kernel_kexec();
+		break;
+#endif
+
+#ifdef CONFIG_HIBERNATION
+	case LINUX_REBOOT_CMD_SW_SUSPEND:
+		ret = hibernate();
+		break;
+#endif
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&reboot_mutex);
+	return ret;
+}
+
+static void deferred_cad(struct work_struct *dummy)
+{
+	kernel_restart(NULL);
+}
+
+/*
+ * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
+ * As it's called within an interrupt, it may NOT sync: the only choice
+ * is whether to reboot at once, or just ignore the ctrl-alt-del.
+ */
+void ctrl_alt_del(void)
+{
+	static DECLARE_WORK(cad_work, deferred_cad);
+
+	if (C_A_D)
+		schedule_work(&cad_work);
+	else
+		kill_cad_pid(SIGINT, 1);
+}
+	
+
+char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
+
+static int __orderly_poweroff(bool force)
+{
+	char **argv;
+	static char *envp[] = {
+		"HOME=/",
+		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
+		NULL
+	};
+	int ret;
+
+	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
+	if (argv) {
+		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
+		argv_free(argv);
+	} else {
+		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
+					 __func__, poweroff_cmd);
+		ret = -ENOMEM;
+	}
+
+	if (ret && force) {
+		printk(KERN_WARNING "Failed to start orderly shutdown: "
+					"forcing the issue\n");
+		/*
+		 * I guess this should try to kick off some daemon to sync and
+		 * poweroff asap.  Or not even bother syncing if we're doing an
+		 * emergency shutdown?
+		 */
+		emergency_sync();
+		kernel_power_off();
+	}
+
+	return ret;
+}
+
+static bool poweroff_force;
+
+static void poweroff_work_func(struct work_struct *work)
+{
+	__orderly_poweroff(poweroff_force);
+}
+
+static DECLARE_WORK(poweroff_work, poweroff_work_func);
+
+/**
+ * orderly_poweroff - Trigger an orderly system poweroff
+ * @force: force poweroff if command execution fails
+ *
+ * This may be called from any context to trigger a system shutdown.
+ * If the orderly shutdown fails, it will force an immediate shutdown.
+ */
+int orderly_poweroff(bool force)
+{
+	if (force) /* do not override the pending "true" */
+		poweroff_force = true;
+	schedule_work(&poweroff_work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(orderly_poweroff);
diff --git a/kernel/sys.c b/kernel/sys.c
index 17bb8d3..467a18f 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -116,20 +116,6 @@ EXPORT_SYMBOL(fs_overflowuid);
 EXPORT_SYMBOL(fs_overflowgid);
 
 /*
- * this indicates whether you can reboot with ctrl-alt-del: the default is yes
- */
-
-int C_A_D = 1;
-struct pid *cad_pid;
-EXPORT_SYMBOL(cad_pid);
-
-/*
- * If set, this is used for preparing the system to power off.
- */
-
-void (*pm_power_off_prepare)(void);
-
-/*
  * Returns true if current's euid is same as p's uid or euid,
  * or has CAP_SYS_NICE to p's user_ns.
  *
@@ -308,261 +294,6 @@ out_unlock:
 	return retval;
 }
 
-/**
- *	emergency_restart - reboot the system
- *
- *	Without shutting down any hardware or taking any locks
- *	reboot the system.  This is called when we know we are in
- *	trouble so this is our best effort to reboot.  This is
- *	safe to call in interrupt context.
- */
-void emergency_restart(void)
-{
-	kmsg_dump(KMSG_DUMP_EMERG);
-	machine_emergency_restart();
-}
-EXPORT_SYMBOL_GPL(emergency_restart);
-
-void kernel_restart_prepare(char *cmd)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
-	system_state = SYSTEM_RESTART;
-	usermodehelper_disable();
-	device_shutdown();
-}
-
-/**
- *	register_reboot_notifier - Register function to be called at reboot time
- *	@nb: Info about notifier function to be called
- *
- *	Registers a function with the list of functions
- *	to be called at reboot time.
- *
- *	Currently always returns zero, as blocking_notifier_chain_register()
- *	always returns zero.
- */
-int register_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_register(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(register_reboot_notifier);
-
-/**
- *	unregister_reboot_notifier - Unregister previously registered reboot notifier
- *	@nb: Hook to be unregistered
- *
- *	Unregisters a previously registered reboot
- *	notifier function.
- *
- *	Returns zero on success, or %-ENOENT on failure.
- */
-int unregister_reboot_notifier(struct notifier_block *nb)
-{
-	return blocking_notifier_chain_unregister(&reboot_notifier_list, nb);
-}
-EXPORT_SYMBOL(unregister_reboot_notifier);
-
-static void migrate_to_reboot_cpu(void)
-{
-	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
-
-	cpu_hotplug_disable();
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(cpu))
-		cpu = cpumask_first(cpu_online_mask);
-
-	/* Prevent races with other tasks migrating this task */
-	current->flags |= PF_NO_SETAFFINITY;
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(cpu));
-}
-
-/**
- *	kernel_restart - reboot the system
- *	@cmd: pointer to buffer containing command to execute for restart
- *		or %NULL
- *
- *	Shutdown everything and perform a clean reboot.
- *	This is not safe to call in interrupt context.
- */
-void kernel_restart(char *cmd)
-{
-	kernel_restart_prepare(cmd);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	if (!cmd)
-		printk(KERN_EMERG "Restarting system.\n");
-	else
-		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
-	kmsg_dump(KMSG_DUMP_RESTART);
-	machine_restart(cmd);
-}
-EXPORT_SYMBOL_GPL(kernel_restart);
-
-static void kernel_shutdown_prepare(enum system_states state)
-{
-	blocking_notifier_call_chain(&reboot_notifier_list,
-		(state == SYSTEM_HALT)?SYS_HALT:SYS_POWER_OFF, NULL);
-	system_state = state;
-	usermodehelper_disable();
-	device_shutdown();
-}
-/**
- *	kernel_halt - halt the system
- *
- *	Shutdown everything and perform a clean system halt.
- */
-void kernel_halt(void)
-{
-	kernel_shutdown_prepare(SYSTEM_HALT);
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "System halted.\n");
-	kmsg_dump(KMSG_DUMP_HALT);
-	machine_halt();
-}
-
-EXPORT_SYMBOL_GPL(kernel_halt);
-
-/**
- *	kernel_power_off - power_off the system
- *
- *	Shutdown everything and perform a clean system power_off.
- */
-void kernel_power_off(void)
-{
-	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
-	if (pm_power_off_prepare)
-		pm_power_off_prepare();
-	migrate_to_reboot_cpu();
-	syscore_shutdown();
-	printk(KERN_EMERG "Power down.\n");
-	kmsg_dump(KMSG_DUMP_POWEROFF);
-	machine_power_off();
-}
-EXPORT_SYMBOL_GPL(kernel_power_off);
-
-static DEFINE_MUTEX(reboot_mutex);
-
-/*
- * Reboot system call: for obvious reasons only root may call it,
- * and even root needs to set up some magic numbers in the registers
- * so that some mistake won't make this reboot the whole machine.
- * You can also set the meaning of the ctrl-alt-del-key here.
- *
- * reboot doesn't sync: do that yourself before calling this.
- */
-SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
-		void __user *, arg)
-{
-	struct pid_namespace *pid_ns = task_active_pid_ns(current);
-	char buffer[256];
-	int ret = 0;
-
-	/* We only trust the superuser with rebooting the system. */
-	if (!ns_capable(pid_ns->user_ns, CAP_SYS_BOOT))
-		return -EPERM;
-
-	/* For safety, we require "magic" arguments. */
-	if (magic1 != LINUX_REBOOT_MAGIC1 ||
-	    (magic2 != LINUX_REBOOT_MAGIC2 &&
-	                magic2 != LINUX_REBOOT_MAGIC2A &&
-			magic2 != LINUX_REBOOT_MAGIC2B &&
-	                magic2 != LINUX_REBOOT_MAGIC2C))
-		return -EINVAL;
-
-	/*
-	 * If pid namespaces are enabled and the current task is in a child
-	 * pid_namespace, the command is handled by reboot_pid_ns() which will
-	 * call do_exit().
-	 */
-	ret = reboot_pid_ns(pid_ns, cmd);
-	if (ret)
-		return ret;
-
-	/* Instead of trying to make the power_off code look like
-	 * halt when pm_power_off is not set do it the easy way.
-	 */
-	if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
-		cmd = LINUX_REBOOT_CMD_HALT;
-
-	mutex_lock(&reboot_mutex);
-	switch (cmd) {
-	case LINUX_REBOOT_CMD_RESTART:
-		kernel_restart(NULL);
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_ON:
-		C_A_D = 1;
-		break;
-
-	case LINUX_REBOOT_CMD_CAD_OFF:
-		C_A_D = 0;
-		break;
-
-	case LINUX_REBOOT_CMD_HALT:
-		kernel_halt();
-		do_exit(0);
-		panic("cannot halt");
-
-	case LINUX_REBOOT_CMD_POWER_OFF:
-		kernel_power_off();
-		do_exit(0);
-		break;
-
-	case LINUX_REBOOT_CMD_RESTART2:
-		if (strncpy_from_user(&buffer[0], arg, sizeof(buffer) - 1) < 0) {
-			ret = -EFAULT;
-			break;
-		}
-		buffer[sizeof(buffer) - 1] = '\0';
-
-		kernel_restart(buffer);
-		break;
-
-#ifdef CONFIG_KEXEC
-	case LINUX_REBOOT_CMD_KEXEC:
-		ret = kernel_kexec();
-		break;
-#endif
-
-#ifdef CONFIG_HIBERNATION
-	case LINUX_REBOOT_CMD_SW_SUSPEND:
-		ret = hibernate();
-		break;
-#endif
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	mutex_unlock(&reboot_mutex);
-	return ret;
-}
-
-static void deferred_cad(struct work_struct *dummy)
-{
-	kernel_restart(NULL);
-}
-
-/*
- * This function gets called by ctrl-alt-del - ie the keyboard interrupt.
- * As it's called within an interrupt, it may NOT sync: the only choice
- * is whether to reboot at once, or just ignore the ctrl-alt-del.
- */
-void ctrl_alt_del(void)
-{
-	static DECLARE_WORK(cad_work, deferred_cad);
-
-	if (C_A_D)
-		schedule_work(&cad_work);
-	else
-		kill_cad_pid(SIGINT, 1);
-}
-	
 /*
  * Unprivileged users may change the real gid to the effective gid
  * or vice versa.  (BSD-style)
@@ -2276,68 +2007,6 @@ SYSCALL_DEFINE3(getcpu, unsigned __user *, cpup, unsigned __user *, nodep,
 	return err ? -EFAULT : 0;
 }
 
-char poweroff_cmd[POWEROFF_CMD_PATH_LEN] = "/sbin/poweroff";
-
-static int __orderly_poweroff(bool force)
-{
-	char **argv;
-	static char *envp[] = {
-		"HOME=/",
-		"PATH=/sbin:/bin:/usr/sbin:/usr/bin",
-		NULL
-	};
-	int ret;
-
-	argv = argv_split(GFP_KERNEL, poweroff_cmd, NULL);
-	if (argv) {
-		ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_EXEC);
-		argv_free(argv);
-	} else {
-		printk(KERN_WARNING "%s failed to allocate memory for \"%s\"\n",
-					 __func__, poweroff_cmd);
-		ret = -ENOMEM;
-	}
-
-	if (ret && force) {
-		printk(KERN_WARNING "Failed to start orderly shutdown: "
-					"forcing the issue\n");
-		/*
-		 * I guess this should try to kick off some daemon to sync and
-		 * poweroff asap.  Or not even bother syncing if we're doing an
-		 * emergency shutdown?
-		 */
-		emergency_sync();
-		kernel_power_off();
-	}
-
-	return ret;
-}
-
-static bool poweroff_force;
-
-static void poweroff_work_func(struct work_struct *work)
-{
-	__orderly_poweroff(poweroff_force);
-}
-
-static DECLARE_WORK(poweroff_work, poweroff_work_func);
-
-/**
- * orderly_poweroff - Trigger an orderly system poweroff
- * @force: force poweroff if command execution fails
- *
- * This may be called from any context to trigger a system shutdown.
- * If the orderly shutdown fails, it will force an immediate shutdown.
- */
-int orderly_poweroff(bool force)
-{
-	if (force) /* do not override the pending "true" */
-		poweroff_force = true;
-	schedule_work(&poweroff_work);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(orderly_poweroff);
-
 /**
  * do_sysinfo - fill in sysinfo struct
  * @info: pointer to buffer to fill
-- 
1.8.2.1



From robherring2 at gmail.com  Thu May 16 12:15:16 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 May 2013 11:15:16 -0500
Subject: [PATCH 2/4] ARM: highbank: remove the .map_io declaration
In-Reply-To: <1368440169-29088-3-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368440169-29088-3-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CAL_Jsq+R_3K4PyYsvq4qo11wEmQkHB2Q+dZm68jqcKn9rDmqLw@mail.gmail.com>

On Mon, May 13, 2013 at 5:16 AM, Maxime Ripard
<maxime.ripard at free-electrons.com> wrote:
> Now that the ARM core code calls debug_ll_io_init, we can remove it from
> the machine_desc declaration.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Acked-by: Rob Herring <rob.herring at calxeda.com>

> ---
>  arch/arm/mach-highbank/highbank.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
> index e7df2dd..dc5d6be 100644
> --- a/arch/arm/mach-highbank/highbank.c
> +++ b/arch/arm/mach-highbank/highbank.c
> @@ -176,7 +176,6 @@ static const char *highbank_match[] __initconst = {
>
>  DT_MACHINE_START(HIGHBANK, "Highbank")
>         .smp            = smp_ops(highbank_smp_ops),
> -       .map_io         = debug_ll_io_init,
>         .init_irq       = highbank_init_irq,
>         .init_time      = highbank_timer_init,
>         .init_machine   = highbank_init,
> --
> 1.8.1.2
>


From holt at sgi.com  Thu May 16 12:14:50 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:50 -0500
Subject: [PATCH -v11 resend 11/11] Move arch/x86 reboot= handling to generic
 kernel.
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-12-git-send-email-holt@sgi.com>

Merge together the unicore32, arm, and x86 reboot= command line
parameter handling.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Ingo Molnar <mingo at kernel.org>
Acked-by: Guan Xuetao <gxt at mprc.pku.edu.cn>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>

---
Changes since -v8
 - Add missing break statements.

 - Change parsing so #ifdef's are no longer needed.

 - Switch to using simple_strtoul to make parsing cleaner.

 - Add handling of REBOOT_HARD/SOFT
---
 Documentation/kernel-parameters.txt      |  14 +++-
 arch/arm/kernel/process.c                |  10 ---
 arch/unicore32/kernel/process.c          |  10 ---
 arch/x86/include/asm/emergency-restart.h |  12 ----
 arch/x86/kernel/apic/x2apic_uv_x.c       |   2 +-
 arch/x86/kernel/reboot.c                 | 111 +------------------------------
 include/linux/reboot.h                   |  17 +++++
 kernel/reboot.c                          |  76 ++++++++++++++++++++-
 8 files changed, 107 insertions(+), 145 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c3bfacb..b2945ce 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2677,9 +2677,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Run specified binary instead of /init from the ramdisk,
 			used for early userspace startup. See initrd.
 
-	reboot=		[BUGS=X86-32,BUGS=ARM,BUGS=IA-64] Rebooting mode
-			Format: <reboot_mode>[,<reboot_mode2>[,...]]
-			See arch/*/kernel/reboot.c or arch/*/kernel/process.c
+	reboot=		[KNL]
+			Format (x86 or x86_64):
+				[w[arm] | c[old] | h[ard] | s[oft] | g[pio]] \
+				[[,]s[mp]#### \
+				[[,]b[ios] | a[cpi] | k[bd] | t[riple] | e[fi] | p[ci]] \
+				[[,]f[orce]
+			Where reboot_mode is one of warm (soft) or cold (hard) or gpio,
+			      reboot_type is one of bios, acpi, kbd, triple, efi, or pci,
+			      reboot_force is either force or not specified,
+			      reboot_cpu is s[mp]#### with #### being the processor
+					to be used for rebooting.
 
 	relax_domain_level=
 			[KNL, SMP] Set scheduler's default relax_domain_level.
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 42856fc..304b102 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -175,16 +175,6 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-enum reboot_mode reboot_mode = REBOOT_HARD;
-
-static int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 93dd035..778ebba 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -51,16 +51,6 @@ void arch_cpu_idle(void)
 	local_irq_enable();
 }
 
-static enum reboot_mode reboot_mode = REBOOT_HARD;
-
-int __init reboot_setup(char *str)
-{
-	if ('s' == str[0])
-		reboot_mode = REBOOT_SOFT;
-	return 1;
-}
-__setup("reboot=", reboot_setup);
-
 void machine_halt(void)
 {
 	gpio_set_value(GPO_SOFT_OFF, 0);
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f4..77a99ac 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -1,18 +1,6 @@
 #ifndef _ASM_X86_EMERGENCY_RESTART_H
 #define _ASM_X86_EMERGENCY_RESTART_H
 
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-	BOOT_BIOS = 'b',
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e',
-	BOOT_CF9 = 'p',
-	BOOT_CF9_COND = 'q',
-};
-
-extern enum reboot_type reboot_type;
-
 extern void machine_emergency_restart(void);
 
 #endif /* _ASM_X86_EMERGENCY_RESTART_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb..958e3e4 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -25,6 +25,7 @@
 #include <linux/kdebug.h>
 #include <linux/delay.h>
 #include <linux/crash_dump.h>
+#include <linux/reboot.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -36,7 +37,6 @@
 #include <asm/ipi.h>
 #include <asm/smp.h>
 #include <asm/x86_init.h>
-#include <asm/emergency-restart.h>
 #include <asm/nmi.h>
 
 /* BMC sets a bit this MMR non-zero before sending an NMI */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index f770340..563ed91 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -36,22 +36,6 @@ void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
-static enum reboot_mode reboot_mode;
-enum reboot_type reboot_type = BOOT_ACPI;
-int reboot_force;
-
-/*
- * This variable is used privately to keep track of whether or not
- * reboot_type is still set to its default value (i.e., reboot= hasn't
- * been set on the command line).  This is needed so that we can
- * suppress DMI scanning for reboot quirks.  Without it, it's
- * impossible to override a faulty reboot quirk without recompiling.
- */
-static int reboot_default = 1;
-
-#ifdef CONFIG_SMP
-static int reboot_cpu = -1;
-#endif
 
 /*
  * This is set if we need to go through the 'emergency' path.
@@ -64,79 +48,6 @@ static int reboot_emergency;
 bool port_cf9_safe = false;
 
 /*
- * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
- * warm   Don't set the cold reboot flag
- * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS
- * smp    Reboot by executing reset on BSP or other CPU
- * triple Force a triple fault (init)
- * kbd    Use the keyboard controller. cold reset (default)
- * acpi   Use the RESET_REG in the FADT
- * efi    Use efi reset_system runtime service
- * pci    Use the so-called "PCI reset register", CF9
- * force  Avoid anything that could hang.
- */
-static int __init reboot_setup(char *str)
-{
-	for (;;) {
-		/*
-		 * Having anything passed on the command line via
-		 * reboot= will cause us to disable DMI checking
-		 * below.
-		 */
-		reboot_default = 0;
-
-		switch (*str) {
-		case 'w':
-			reboot_mode = REBOOT_WARM;
-			break;
-
-		case 'c':
-			reboot_mode = REBOOT_COLD;
-			break;
-
-#ifdef CONFIG_SMP
-		case 's':
-			if (isdigit(*(str+1))) {
-				reboot_cpu = (int) (*(str+1) - '0');
-				if (isdigit(*(str+2)))
-					reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0');
-			}
-			/*
-			 * We will leave sorting out the final value
-			 * when we are ready to reboot, since we might not
-			 * have detected BSP APIC ID or smp_num_cpu
-			 */
-			break;
-#endif /* CONFIG_SMP */
-
-		case 'b':
-		case 'a':
-		case 'k':
-		case 't':
-		case 'e':
-		case 'p':
-			reboot_type = *str;
-			break;
-
-		case 'f':
-			reboot_force = 1;
-			break;
-		}
-
-		str = strchr(str, ',');
-		if (str)
-			str++;
-		else
-			break;
-	}
-	return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
-
-/*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
  */
@@ -616,26 +527,10 @@ void native_machine_shutdown(void)
 {
 	/* Stop the cpus and apics */
 #ifdef CONFIG_SMP
-
-	/* The boot cpu is always logical cpu 0 */
-	int reboot_cpu_id = 0;
-
-	/* See if there has been given a command line override */
-	if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
-		cpu_online(reboot_cpu))
-		reboot_cpu_id = reboot_cpu;
-
-	/* Make certain the cpu I'm about to reboot on is online */
-	if (!cpu_online(reboot_cpu_id))
-		reboot_cpu_id = smp_processor_id();
-
-	/* Make certain I only run on the appropriate processor */
-	set_cpus_allowed_ptr(current, cpumask_of(reboot_cpu_id));
-
 	/*
-	 * O.K Now that I'm on the appropriate processor, stop all of the
-	 * others. Also disable the local irq to not receive the per-cpu
-	 * timer interrupt which may trigger scheduler's load balance.
+	 * Stop all of the others. Also disable the local irq to
+	 * not receive the per-cpu timer interrupt which may trigger
+	 * scheduler's load balance.
 	 */
 	local_irq_disable();
 	stop_other_cpus();
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index 5a5d7f7..8e00f9f 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -17,6 +17,23 @@ enum reboot_mode {
 	REBOOT_SOFT,
 	REBOOT_GPIO,
 };
+extern enum reboot_mode reboot_mode;
+
+enum reboot_type {
+	BOOT_TRIPLE = 't',
+	BOOT_KBD = 'k',
+	BOOT_BIOS = 'b',
+	BOOT_ACPI = 'a',
+	BOOT_EFI = 'e',
+	BOOT_CF9 = 'p',
+	BOOT_CF9_COND = 'q',
+};
+extern enum reboot_type reboot_type;
+
+extern int reboot_default;
+extern int reboot_cpu;
+extern int reboot_force;
+
 
 extern int register_reboot_notifier(struct notifier_block *);
 extern int unregister_reboot_notifier(struct notifier_block *);
diff --git a/kernel/reboot.c b/kernel/reboot.c
index abb6a04..269ed93 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -6,6 +6,7 @@
 
 #define pr_fmt(fmt)	"reboot: " fmt
 
+#include <linux/ctype.h>
 #include <linux/export.h>
 #include <linux/kexec.h>
 #include <linux/kmod.h>
@@ -24,6 +25,18 @@ int C_A_D = 1;
 struct pid *cad_pid;
 EXPORT_SYMBOL(cad_pid);
 
+#if defined(CONFIG_ARM) || defined(CONFIG_UNICORE32)
+#define DEFAULT_REBOOT_MODE		= REBOOT_HARD
+#else
+#define DEFAULT_REBOOT_MODE
+#endif
+enum reboot_mode reboot_mode DEFAULT_REBOOT_MODE;
+
+int reboot_default;
+int reboot_cpu;
+enum reboot_type reboot_type = BOOT_ACPI;
+int reboot_force;
+
 /*
  * If set, this is used for preparing the system to power off.
  */
@@ -87,7 +100,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 static void migrate_to_reboot_cpu(void)
 {
 	/* The boot cpu is always logical cpu 0 */
-	int cpu = 0;
+	int cpu = reboot_cpu;
 
 	cpu_hotplug_disable();
 
@@ -343,3 +356,64 @@ int orderly_poweroff(bool force)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(orderly_poweroff);
+
+static int __init reboot_setup(char *str)
+{
+	for (;;) {
+		/*
+		 * Having anything passed on the command line via
+		 * reboot= will cause us to disable DMI checking
+		 * below.
+		 */
+		reboot_default = 0;
+
+		switch (*str) {
+		case 'w':
+			reboot_mode = REBOOT_WARM;
+			break;
+
+		case 'c':
+			reboot_mode = REBOOT_COLD;
+			break;
+
+		case 'h':
+			reboot_mode = REBOOT_HARD;
+			break;
+
+		case 's':
+			if (isdigit(*(str+1)))
+				reboot_cpu = simple_strtoul(str+1, NULL, 0);
+			else if (str[1] == 'm' && str[2] == 'p' &&
+							isdigit(*(str+3)))
+				reboot_cpu = simple_strtoul(str+3, NULL, 0);
+			else
+				reboot_mode = REBOOT_SOFT;
+			break;
+
+		case 'g':
+			reboot_mode = REBOOT_GPIO;
+			break;
+
+		case 'b':
+		case 'a':
+		case 'k':
+		case 't':
+		case 'e':
+		case 'p':
+			reboot_type = *str;
+			break;
+
+		case 'f':
+			reboot_force = 1;
+			break;
+		}
+
+		str = strchr(str, ',');
+		if (str)
+			str++;
+		else
+			break;
+	}
+	return 1;
+}
+__setup("reboot=", reboot_setup);
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:48 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:48 -0500
Subject: [PATCH -v11 resend 09/11] arm,
 prepare reboot_mode for moving to generic kernel code.
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-10-git-send-email-holt@sgi.com>

This patch prepares for the moving the parsing of reboot= to the generic
kernel code by making reboot_mode into a more generic form.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>

---

Changes since -v10
 - Uncommented an accidentally commented out line.

Changes since -v8
 - Switched from using REBOOT_WARM/COLD to HARD/SOFT.
---
 arch/arm/include/asm/mach/arch.h   | 3 ++-
 arch/arm/kernel/process.c          | 8 ++++----
 arch/arm/kernel/setup.c            | 6 +++---
 arch/arm/mach-footbridge/cats-hw.c | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..e2b551e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -9,6 +9,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 
 struct tag;
 struct meminfo;
@@ -39,7 +40,7 @@ struct machine_desc {
 	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-	char			restart_mode;	/* default restart mode	*/
+	enum reboot_mode	reboot_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..92b47df 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -174,14 +174,14 @@ void arch_cpu_idle(void)
 		default_idle();
 }
 
-static char reboot_mode = 'h';
+enum reboot_mode reboot_mode = REBOOT_HARD;
 
-int __init reboot_setup(char *str)
+static int __init reboot_setup(char *str)
 {
-	reboot_mode = str[0];
+	if ('s' == str[0])
+		reboot_mode = REBOOT_SOFT;
 	return 1;
 }
-
 __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7a..e05df42 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -73,7 +73,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -769,8 +769,8 @@ void __init setup_arch(char **cmdline_p)
 
 	setup_dma_zone(mdesc);
 
-	if (mdesc->restart_mode)
-		reboot_setup(&mdesc->restart_mode);
+	if (mdesc->reboot_mode != REBOOT_HARD)
+		reboot_mode = mdesc->reboot_mode;
 
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09..9669cc0 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
 	/* Maintainer: Philip Blundell */
 	.atag_offset	= 0x100,
-	.restart_mode	= 's',
+	.reboot_mode	= REBOOT_SOFT,
 	.fixup		= fixup_cats,
 	.map_io		= footbridge_map_io,
 	.init_irq	= footbridge_init_irq,
-- 
1.8.2.1



From holt at sgi.com  Thu May 16 12:14:49 2013
From: holt at sgi.com (Robin Holt)
Date: Thu, 16 May 2013 11:14:49 -0500
Subject: [PATCH -v11 resend 10/11] arm,
 change reboot_mode to use enum reboot_mode
In-Reply-To: <1368720890-57711-1-git-send-email-holt@sgi.com>
References: <1368720890-57711-1-git-send-email-holt@sgi.com>
Message-ID: <1368720890-57711-11-git-send-email-holt@sgi.com>

Preparing to move the parsing of reboot= to generic kernel code
forces the change in reboot_mode handling to use the enum.

Signed-off-by: Robin Holt <holt at sgi.com>
To: Andrew Morton <akpm at linux-foundation.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Russ Anderson <rja at sgi.com>
Cc: Robin Holt <holt at sgi.com>
Cc: H. Peter Anvin <hpa at zytor.com>
Cc: Guan Xuetao <gxt at mprc.pku.edu.cn>
Cc: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
Cc: the arch/x86 maintainers <x86 at kernel.org>
Cc: Arm Mailing List <linux-arm-kernel at lists.infradead.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/include/asm/hardware/iop3xx.h         |  3 ++-
 arch/arm/include/asm/mach/arch.h               |  2 +-
 arch/arm/include/asm/system_misc.h             |  3 ++-
 arch/arm/kernel/process.c                      |  5 +++--
 arch/arm/mach-at91/at91rm9200.c                |  3 ++-
 arch/arm/mach-at91/generic.h                   |  5 +++--
 arch/arm/mach-bcm2835/bcm2835.c                |  4 ++--
 arch/arm/mach-clps711x/common.c                |  2 +-
 arch/arm/mach-clps711x/common.h                |  4 +++-
 arch/arm/mach-cns3xxx/core.h                   |  4 +++-
 arch/arm/mach-cns3xxx/pm.c                     |  2 +-
 arch/arm/mach-davinci/devices-da8xx.c          |  3 ++-
 arch/arm/mach-davinci/devices.c                |  3 ++-
 arch/arm/mach-davinci/include/mach/common.h    |  3 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h     |  3 ++-
 arch/arm/mach-davinci/include/mach/tnetv107x.h |  3 ++-
 arch/arm/mach-davinci/tnetv107x.c              |  3 ++-
 arch/arm/mach-dove/common.c                    |  2 +-
 arch/arm/mach-dove/common.h                    |  4 +++-
 arch/arm/mach-ebsa110/core.c                   |  2 +-
 arch/arm/mach-ep93xx/core.c                    |  3 ++-
 arch/arm/mach-ep93xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-exynos/common.c                  |  4 ++--
 arch/arm/mach-exynos/common.h                  |  5 +++--
 arch/arm/mach-footbridge/common.c              |  4 ++--
 arch/arm/mach-footbridge/common.h              |  3 ++-
 arch/arm/mach-footbridge/netwinder-hw.c        |  4 ++--
 arch/arm/mach-highbank/core.h                  |  4 +++-
 arch/arm/mach-highbank/system.c                |  5 +++--
 arch/arm/mach-imx/common.h                     |  4 +++-
 arch/arm/mach-imx/mach-imx6q.c                 |  3 ++-
 arch/arm/mach-imx/system.c                     |  2 +-
 arch/arm/mach-integrator/common.h              |  3 ++-
 arch/arm/mach-integrator/core.c                |  2 +-
 arch/arm/mach-iop13xx/include/mach/iop13xx.h   |  5 ++++-
 arch/arm/mach-iop13xx/setup.c                  |  2 +-
 arch/arm/mach-iop32x/n2100.c                   |  2 +-
 arch/arm/mach-ixp4xx/common.c                  |  4 ++--
 arch/arm/mach-ixp4xx/dsmg600-setup.c           |  1 +
 arch/arm/mach-ixp4xx/include/mach/platform.h   |  4 +++-
 arch/arm/mach-kirkwood/board-lsxl.c            |  2 +-
 arch/arm/mach-kirkwood/common.c                |  3 ++-
 arch/arm/mach-kirkwood/common.h                |  4 +++-
 arch/arm/mach-ks8695/generic.h                 |  2 +-
 arch/arm/mach-ks8695/time.c                    |  4 ++--
 arch/arm/mach-lpc32xx/common.c                 |  6 +++---
 arch/arm/mach-lpc32xx/common.h                 |  3 ++-
 arch/arm/mach-mmp/common.c                     |  2 +-
 arch/arm/mach-mmp/common.h                     |  3 ++-
 arch/arm/mach-mmp/include/mach/pxa168.h        |  4 +++-
 arch/arm/mach-mmp/pxa168.c                     |  2 +-
 arch/arm/mach-mv78xx0/common.c                 |  2 +-
 arch/arm/mach-mv78xx0/common.h                 |  4 +++-
 arch/arm/mach-mvebu/common.h                   |  4 +++-
 arch/arm/mach-mvebu/system-controller.c        |  3 ++-
 arch/arm/mach-mxs/mach-mxs.c                   |  4 +++-
 arch/arm/mach-netx/generic.c                   |  3 ++-
 arch/arm/mach-netx/generic.h                   |  4 +++-
 arch/arm/mach-nomadik/cpu-8815.c               |  2 +-
 arch/arm/mach-omap1/board-voiceblue.c          |  3 ++-
 arch/arm/mach-omap1/common.h                   |  3 ++-
 arch/arm/mach-omap1/reset.c                    |  3 ++-
 arch/arm/mach-omap2/am33xx-restart.c           |  3 ++-
 arch/arm/mach-omap2/common.h                   | 17 +++++++++--------
 arch/arm/mach-omap2/omap2-restart.c            |  2 +-
 arch/arm/mach-omap2/omap3-restart.c            |  3 ++-
 arch/arm/mach-omap2/omap4-common.c             |  3 ++-
 arch/arm/mach-orion5x/common.c                 |  2 +-
 arch/arm/mach-orion5x/common.h                 |  4 +++-
 arch/arm/mach-orion5x/ls-chl-setup.c           |  2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c           |  2 +-
 arch/arm/mach-orion5x/lsmini-setup.c           |  2 +-
 arch/arm/mach-picoxcell/common.c               |  3 ++-
 arch/arm/mach-prima2/common.h                  |  4 +++-
 arch/arm/mach-prima2/rstc.c                    |  3 ++-
 arch/arm/mach-pxa/corgi.c                      |  6 +++---
 arch/arm/mach-pxa/generic.h                    |  4 +++-
 arch/arm/mach-pxa/mioa701.c                    |  7 ++++---
 arch/arm/mach-pxa/poodle.c                     |  2 +-
 arch/arm/mach-pxa/reset.c                      |  8 ++++----
 arch/arm/mach-pxa/spitz.c                      |  5 +++--
 arch/arm/mach-pxa/tosa.c                       |  5 +++--
 arch/arm/mach-realview/realview_eb.c           |  3 ++-
 arch/arm/mach-realview/realview_pb1176.c       |  3 ++-
 arch/arm/mach-realview/realview_pb11mp.c       |  3 ++-
 arch/arm/mach-realview/realview_pba8.c         |  3 ++-
 arch/arm/mach-realview/realview_pbx.c          |  3 ++-
 arch/arm/mach-rpc/riscpc.c                     |  3 ++-
 arch/arm/mach-s3c24xx/common.h                 | 12 +++++++-----
 arch/arm/mach-s3c24xx/s3c2410.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2412.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2416.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c2443.c                |  5 +++--
 arch/arm/mach-s3c24xx/s3c244x.c                |  5 +++--
 arch/arm/mach-s3c64xx/common.c                 |  5 +++--
 arch/arm/mach-s3c64xx/common.h                 |  4 +++-
 arch/arm/mach-s5p64x0/common.c                 |  5 +++--
 arch/arm/mach-s5p64x0/common.h                 |  4 +++-
 arch/arm/mach-s5pc100/common.c                 |  5 +++--
 arch/arm/mach-s5pc100/common.h                 |  4 +++-
 arch/arm/mach-s5pv210/common.c                 |  2 +-
 arch/arm/mach-s5pv210/common.h                 |  4 +++-
 arch/arm/mach-sa1100/generic.c                 |  5 +++--
 arch/arm/mach-sa1100/generic.h                 |  3 ++-
 arch/arm/mach-shark/core.c                     |  3 ++-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  3 ++-
 arch/arm/mach-shmobile/board-kzm9g.c           |  3 ++-
 arch/arm/mach-socfpga/socfpga.c                |  3 ++-
 arch/arm/mach-spear/generic.h                  |  4 +++-
 arch/arm/mach-spear/restart.c                  |  5 +++--
 arch/arm/mach-sunxi/sunxi.c                    |  3 ++-
 arch/arm/mach-tegra/board.h                    |  3 ++-
 arch/arm/mach-tegra/common.c                   |  3 ++-
 arch/arm/mach-u300/core.c                      |  6 +++---
 arch/arm/mach-versatile/core.c                 |  3 ++-
 arch/arm/mach-versatile/core.h                 |  3 ++-
 arch/arm/mach-vt8500/vt8500.c                  |  3 ++-
 arch/arm/mach-w90x900/cpu.c                    |  4 ++--
 arch/arm/mach-w90x900/nuc9xx.h                 |  5 ++++-
 arch/arm/plat-iop/gpio.c                       |  1 +
 arch/arm/plat-iop/restart.c                    |  2 +-
 drivers/power/reset/restart-poweroff.c         |  3 ++-
 drivers/power/reset/vexpress-poweroff.c        |  2 +-
 include/linux/reboot.h                         |  1 +
 include/linux/vexpress.h                       |  1 +
 125 files changed, 282 insertions(+), 166 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a..423744b 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e2b551e..2353bc3 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -54,7 +54,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	void			(*handle_irq)(struct pt_regs *);
 #endif
-	void			(*restart)(char, const char *);
+	void			(*restart)(enum reboot_mode, const char *);
 };
 
 /*
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e3..a3d61ad 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED	(1 << 0)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 92b47df..42856fc 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -112,7 +113,7 @@ void soft_restart(unsigned long addr)
 	BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +123,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..f70c239 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -304,7 +305,7 @@ static void at91rm9200_idle(void)
 	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	/*
 	 * Perform a hardware reset with the use of the Watchdog timer.
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..0723ed6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 740fa9e..40686d7 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -53,7 +53,7 @@ static void bcm2835_setup_restart(void)
 	WARN(!wdt_regs, "failed to remap watchdog regs");
 }
 
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 val;
 
@@ -91,7 +91,7 @@ static void bcm2835_power_off(void)
 	writel_relaxed(val, wdt_regs + PM_RSTS);
 
 	/* Continue with normal reset mechanism */
-	bcm2835_restart(0, "");
+	bcm2835_restart(REBOOT_HARD, "");
 }
 
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f..54f6a8d 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -345,7 +345,7 @@ void __init clps711x_timer_init(void)
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a729..2da0ff5 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
  * Common bits.
  */
 
+#include <linux/reboot.h>
+
 #define CLPS711X_NR_IRQS	(33)
 #define CLPS711X_NR_GPIO	(4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit)	((prt) * 8 + (bit))
@@ -12,4 +14,4 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b..5218b61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
+#include <linux/reboot.h>
+
 extern void cns3xxx_timer_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 79e3d47..fb38c72 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..c80e189 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
 	.resource	= da8xx_watchdog_resources,
 };
 
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device *dev;
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3..5364f70 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
@@ -303,7 +304,7 @@ struct platform_device davinci_wdt_device = {
 	.resource	= wdt_resources,
 };
 
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
 	davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..cce316b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 
 extern void davinci_timer_init(void);
 
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..95b76a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,6 +17,7 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
@@ -106,7 +107,7 @@ int __init da850_register_vpif_display
 			(struct vpif_display_config *display_config);
 int __init da850_register_vpif_capture
 			(struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..bc9479d 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -54,7 +55,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d..4545667 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/map.h>
 
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
 	__raw_writel(1, &regs->kick);
 }
 
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
 	tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..cbdb88b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -382,7 +382,7 @@ void __init dove_init(void)
 	dove_xor1_init();
 }
 
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index e863479..1d72522 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 
 #endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 69a9d5d..62b928b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 
 arch_initcall(ebsa110_init);
 
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0x80000000);
 }
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3d..df8612f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
 	gpio_led_register_device(-1, &ep93xx_led_data);
 }
 
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b3..e256e0b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 745e304..e3a2802 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -302,12 +302,12 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
 	},
 };
 
-void exynos4_restart(char mode, const char *cmd)
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	u32 val;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 60dd35c..da1130b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,6 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/reboot.h>
 #include <linux/of.h>
 
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
@@ -22,8 +23,8 @@ struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369..2739ca2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
 	}
 }
 
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50..56607b3 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23f..1fd2cf0 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
 
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into the ROM */
 		soft_restart(0x41000000);
 	} else {
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206..aea1ec5 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
 
+#include <linux/reboot.h>
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384..2df5870 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
  */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 
 #include "core.h"
 #include "sysregs.h"
 
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 'h')
+	if (mode == REBOOT_HARD)
 		highbank_set_pwr_hard_reset();
 	else
 		highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f..5740795 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct platform_device;
 struct pt_regs;
 struct clk;
@@ -72,7 +74,7 @@ extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..6fdb478 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -26,6 +26,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -66,7 +67,7 @@ static void __init imx6q_init_revision(void)
 	mxc_set_cpu_type(rev >> 16 & 0xff);
 }
 
-static void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d7..d7ec547 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -34,7 +34,7 @@ static void __iomem *wdog_base;
 /*
  * Reset the system. It is called by machine_restart().
  */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
 	unsigned int wcr_enable;
 
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658b..ad0ac55 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d2..4cdfd73 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
  * To reset, we hit the on-board reset register in the system FPGA
  */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
 	cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58..17b4027 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 
 #ifndef __ASSEMBLY__
+
+#include <linux/reboot.h>
+
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61..97a4906 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -597,7 +597,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a..0691443 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
 		;
 }
 
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
 	gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
 	gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff..33e4630 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
 					0xf, 0xfffffffe);
 }
 
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if ( 1 && mode == 's') {
+	if ( 1 && mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8..686ef34 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb6..4c4c6a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/reboot.h>
+
 #include <asm/types.h>
 
 #ifndef	__ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..c44f8b2 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -35,7 +35,7 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
  */
 static void lsxl_power_off(void)
 {
-	kirkwood_restart('h', NULL);
+	kirkwood_restart(REBOOT_HARD, NULL);
 }
 
 void __init lsxl_init(void)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c2cae69..f54fdf9 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -729,7 +730,7 @@ void __init kirkwood_init(void)
 #endif
 }
 
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..2a109df 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,7 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 			    int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce4..43253f8 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a386..426c976 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
 	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
 
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	unsigned int reg;
 
-	if (mode == 's')
+	if (reboot_mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c..d7aa54c 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
 	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
 
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 		lpc32xx_watchdog_reset();
 		break;
 
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b2606..1cd8853 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 /*
  * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 
 
 /*
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..c03b4ab 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..991d7e9 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..459c2d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
 
+#include <linux/reboot.h>
+
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3..144e997 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 	return platform_device_register(&pxa168_device_usb_host);
 }
 
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 749a7f8..75062ef 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -413,7 +413,7 @@ void __init mv78xx0_init(void)
 	clk_init();
 }
 
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6889af2 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
 
+#include <linux/reboot.h>
+
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 
 extern void mv78xx0_timer_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..f7ad45e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,9 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-void mvebu_restart(char mode, const char *cmd);
+#include <linux/reboot.h>
+
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df..f875124 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 static void __iomem *system_controller_base;
 
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
 	{ /* end of list */ },
 };
 
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!system_controller_base) {
 		pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..79ddcaf 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -26,6 +26,8 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -390,7 +392,7 @@ static void __init mxs_machine_init(void)
 /*
  * Reset the system. It is called by machine_restart().
  */
-static void mxs_restart(char mode, const char *cmd)
+static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
 	struct device_node *np;
 	void __iomem *reset_addr;
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68..db25b0c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 
 subsys_initcall(netx_init);
 
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
 	       NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26b..bb2ce47 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/reboot.h>
+
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..8aec5af 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -148,7 +148,7 @@ static void __init cpu8815_map_io(void)
 	iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
 
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1..4677a9c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
 	gpio_set_value(0, wdt_gpio_state);
 }
 
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e99..abec019 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <plat/i2c.h>
 
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e..72bf4bf 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
 
 
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8..1eae962 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..be9b930 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 
 #include <asm/proc-fns.h>
 
@@ -118,33 +119,33 @@ static inline void omap_soc_device_init(void)
 #endif
 
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716..68423e2 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
  * Set the DPLL to bypass so that reboot completes successfully.  No
  * return value.
  */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 rate;
 
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582..5de2a0c 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 	omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ff..14c7bad 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -348,7 +349,7 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  * Resets the SoC.  For @cmd, see the 'reboot' syscall in
  * kernel/sys.c.  No return value.
  */
-void omap44xx_restart(char mode, const char *cmd)
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* XXX Should save 'cmd' into scratchpad for use after reboot */
 	omap4_prminst_global_warm_sw_reset(); /* never returns */
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b97fd67..98dd90c 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -354,7 +354,7 @@ void __init orion5x_init(void)
 	orion5x_wdt_init();
 }
 
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index cdaa01f..a909afb 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+#include <linux/reboot.h>
+
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -29,7 +31,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 24f4e14..6234977 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 
 static void lschl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fc653bb..fe04c4b 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 
 static void ls_hgl_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 18e66e6..ca4dbe9 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-	orion5x_restart('h', NULL);
+	orion5x_restart(REBOOT_HARD, NULL);
 }
 
 
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441a..d298ed0 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,6 +15,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
@@ -70,7 +71,7 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
 	/*
 	 * Configure the watchdog to reset with the shortest possible timeout
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd..a630485 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..bdf57d4 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -82,7 +83,7 @@ int sirfsoc_reset_device(struct device *dev)
 
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
 	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fea..f162f1b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
 		/* Green LED off tells the bootloader to halt */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!machine_is_corgi())
 		/* Green LED on tells the bootloader to reboot */
 		gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-	pxa_restart('h', cmd);
+	pxa_restart(REBOOT_HARD, cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39..8963984 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/reboot.h>
+
 struct irq_data;
 
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
 
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dbea67a..76f5e46 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -691,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', NULL);
+	pxa_restart(REBOOT_SOFT, NULL);
 }
 
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
 	mioa701_machine_exit();
-	pxa_restart('s', cmd);
+	pxa_restart(REBOOT_SOFT, cmd);
 }
 
 static struct gpio global_gpios[] = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..711d37e 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -422,7 +422,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 
 static void poodle_poweroff(void)
 {
-	pxa_restart('h', NULL);
+	pxa_restart(REBOOT_HARD, NULL);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583..0d5dd64 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
 	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
 	local_irq_disable();
 	local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
 	clear_reset_status(RESET_STATUS_ALL);
 
 	switch (mode) {
-	case 's':
+	case REBOOT_SOFT:
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 		break;
-	case 'g':
+	case REBOOT_GPIO:
 		do_gpio_reset();
 		break;
-	case 'h':
+	case REBOOT_HARD:
 	default:
 		do_hw_reset();
 		break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c3c0042..2125df0 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -924,10 +925,10 @@ static inline void spitz_i2c_init(void) {}
  ******************************************************************************/
 static void spitz_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 	/* Bootloader magic for a reboot */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a41992f..0206b91 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-	pxa_restart('g', NULL);
+	pxa_restart(REBOOT_GPIO, NULL);
 }
 
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
 	uint32_t msc0 = __raw_readl(MSC0);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bf..c85ddb2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
 	realview_eb_twd_init();
 }
 
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1..c5eade7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe21..f4b0962 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
 	realview_pb11mp_twd_init();
 }
 
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a..10a3e1d 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185..9d75493 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
 
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5..09d602b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 
 arch_initcall(rpc_init);
 
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
 	iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 307c371..84b2806 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
+#include <linux/reboot.h>
+
 struct s3c2410_uartcfg;
 
 #ifdef CONFIG_CPU_S3C2410
@@ -20,7 +22,7 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -36,7 +38,7 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -51,7 +53,7 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -66,7 +68,7 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c244x_init_clocks(int xtal);
-extern void s3c244x_restart(char mode, const char *cmd);
+extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
@@ -96,7 +98,7 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5..f68ccf0 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
@@ -195,9 +196,9 @@ int __init s3c2410a_init(void)
 	return s3c2410_init();
 }
 
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		soft_restart(0);
 	}
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0f864d4..0251650 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,9 +130,9 @@ static void s3c2412_idle(void)
 	cpu_do_idle();
 }
 
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	/* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index b9c5d38..9ef3ccf 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -79,9 +80,9 @@ static struct device s3c2416_dev = {
 	.bus		= &s3c2416_subsys,
 };
 
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 8328cd6..b6c7191 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,9 +60,9 @@ static struct device s3c2443_dev = {
 	.bus		= &s3c2443_subsys,
 };
 
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb..de88598 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -197,9 +198,9 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
 	.resume		= s3c244x_resume,
 };
 
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's')
+	if (mode == REBOOT_SOFT)
 		soft_restart(0);
 
 	arch_wdt_reset();
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..c13d90d 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,9 +376,9 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
 
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..e8f990b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
 
+#include <linux/reboot.h>
+
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
 
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..5f515e1 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -437,9 +438,9 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
 
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fd..f3a9b43 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 
 #ifdef CONFIG_CPU_S5P6440
 
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..e6cc829 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -216,9 +217,9 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode != 's')
+	if (mode != REBOOT_SOFT)
 		arch_wdt_reset();
 
 	soft_restart(0);
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index c41f912..08d782d 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
 
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e..023f1a7 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 	}
 };
 
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 0a1cc0ae..fe1beb5 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
+#include <linux/reboot.h>
+
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
 
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98..f25b611 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 
 #include <video/sa1100fb.h>
 
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
 	PMCR = PMCR_SF;
 }
 
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1..9a33695 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
  *
  * Author: Nicolas Pitre
  */
+#include <linux/reboot.h>
 
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 1535557..1d32c5e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
         short temp;
         /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b288..fde2e4f 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -1277,7 +1278,7 @@ static void __init eva_add_early_devices(void)
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* Do soft power on reset */
 	writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a..2f223f0 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -33,6 +33,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -806,7 +807,7 @@ static void __init kzm_init(void)
 	sh73a0_pm_init();
 }
 
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
 	/* Do soft power on reset */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a0513..0fde6c0 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -90,7 +91,7 @@ static void __init socfpga_init_irq(void)
 	socfpga_sysmgr_init();
 }
 
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
 	u32 temp;
 
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index a9fd453..904f2c9 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -16,6 +16,8 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/pl08x.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
+
 #include <asm/mach/time.h>
 
 extern void spear13xx_timer_init(void);
@@ -32,7 +34,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
 
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 2b44500..ce5e098 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -12,14 +12,15 @@
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* software reset, Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35..f71923b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 
 #include <linux/clk/sunxi.h>
 
@@ -36,7 +37,7 @@
 
 static void __iomem *wdt_base;
 
-static void sun4i_restart(char mode, const char *cmd)
+static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (!wdt_base)
 		return;
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1787327..9a6659f 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 
 #include <linux/types.h>
+#include <linux/reboot.h>
 
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 
 void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..2572e73 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip.h>
 #include <linux/clk/tegra.h>
+#include <linux/reboot.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -67,7 +68,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
 
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
 	u32 reg;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..3e7af05 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -671,11 +671,11 @@ static void __init u300_init_machine(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-static void u300_restart(char mode, const char *cmd)
+static void u300_restart(enum reboot_mode mode, const char *cmd)
 {
 	switch (mode) {
-	case 's':
-	case 'h':
+	case REBOOT_SOFT:
+	case REBOOT_HARD:
 #ifdef CONFIG_COH901327_WATCHDOG
 		coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 54bb80b..3b0572f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif	/* CONFIG_LEDS */
 
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
 	void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 	u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d..f06d576 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..de2b7eb 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +48,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
 	if (pmc_base)
 		writel(1, pmc_base + VT8500_PMSR_REG);
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b..b1eabaa 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define	WTE	(1 << 7)
 #define	WTRE	(1 << 1)
 
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-	if (mode == 's') {
+	if (mode == REBOOT_SOFT) {
 		/* Jump into ROM at address 0 */
 		soft_restart(0);
 	} else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b2..e3ab1e1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
  * published by the Free Software Foundation.
  *
  */
+
+#include <linux/reboot.h>
+
 struct map_desc;
 
 /* core initialisation functions */
 
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be..697de6d 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699..3a4d5e5 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
 
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	*IOP3XX_PCSR = 0x30;
 
diff --git a/drivers/power/reset/restart-poweroff.c b/drivers/power/reset/restart-poweroff.c
index 059cd15..5758033 100644
--- a/drivers/power/reset/restart-poweroff.c
+++ b/drivers/power/reset/restart-poweroff.c
@@ -15,11 +15,12 @@
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 
 static void restart_poweroff_do_poweroff(void)
 {
-	arm_pm_restart('h', NULL);
+	arm_pm_restart(REBOOT_HARD, NULL);
 }
 
 static int restart_poweroff_probe(struct platform_device *pdev)
diff --git a/drivers/power/reset/vexpress-poweroff.c b/drivers/power/reset/vexpress-poweroff.c
index 469e696..476aa49 100644
--- a/drivers/power/reset/vexpress-poweroff.c
+++ b/drivers/power/reset/vexpress-poweroff.c
@@ -48,7 +48,7 @@ static void vexpress_power_off(void)
 
 static struct device *vexpress_restart_device;
 
-static void vexpress_restart(char str, const char *cmd)
+static void vexpress_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 	vexpress_reset_do(vexpress_restart_device, "restart");
 }
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index ca29a6f..5a5d7f7 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -15,6 +15,7 @@ enum reboot_mode {
 	REBOOT_WARM,
 	REBOOT_HARD,
 	REBOOT_SOFT,
+	REBOOT_GPIO,
 };
 
 extern int register_reboot_notifier(struct notifier_block *);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index ea7168a..617c01b 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/reboot.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
-- 
1.8.2.1



From robherring2 at gmail.com  Thu May 16 12:16:48 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 May 2013 11:16:48 -0500
Subject: [PATCH 1/4] ARM: mmu: Call debug_ll_io_init if no map_io function
 is specified
In-Reply-To: <1368440169-29088-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368440169-29088-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CAL_Jsq+LuNBUyzc++i6RKJ67La1LKyC5d6hPvXuj1Kr_R0EmMQ@mail.gmail.com>

On Mon, May 13, 2013 at 5:16 AM, Maxime Ripard
<maxime.ripard at free-electrons.com> wrote:
> More and more sub-architectures are using only the debug_ll_io_init
> function as the map_io function. Make the core code call this function
> if no function is specified in the machine description to remove some
> boilerplate code.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Acked-by: Rob Herring <rob.herring at calxeda.com>

> ---
>  arch/arm/mm/mmu.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index e0d8565..faa36d7 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -1232,6 +1232,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
>          */
>         if (mdesc->map_io)
>                 mdesc->map_io();
> +       else
> +               debug_ll_io_init();
>         fill_pmd_gaps();
>
>         /* Reserve fixed i/o space in VMALLOC region */
> --
> 1.8.1.2
>


From tony at atomide.com  Thu May 16 12:20:35 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 09:20:35 -0700
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <519503DA.5070303@iki.fi>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
 <51936946.3030507@iki.fi> <20130516155857.GV5600@atomide.com>
 <519503DA.5070303@iki.fi>
Message-ID: <20130516162034.GX5600@atomide.com>

* Tomi Valkeinen <tomi.valkeinen at iki.fi> [130516 09:11]:
> On 16/05/13 18:58, Tony Lindgren wrote:
> > * Tomi Valkeinen <tomi.valkeinen at iki.fi> [130515 03:59]:
> > 
> > Just checking.. Do you have CONFIG_OMAP_OCP2SCP=y in your .config? Sounds
> > like the some transceivers should depend on that for omap4.
> 
> Yes, I have OCP2SCP=y.

Hmm well no idea beyond that then. Sounds like Kishon should check it.
 
> >> The musb-hdrc id is wrong on overo also.
> > 
> > Hmm has there been a fix posted for that?
> 
> I couldn't find with a quick look. We debugged and discussed this on an irc
> channel with Kishon, who said he'll send a patch. Changing the musb-hdrc ID
> on overo fixed the issue, and it looks very similar to the error on 4430sdp.
> The overo fix was just:
> 
> diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
> index 4ca6b68..a496774 100644
> --- a/arch/arm/mach-omap2/board-overo.c
> +++ b/arch/arm/mach-omap2/board-overo.c
> @@ -472,7 +472,7 @@ static void __init overo_init(void)
>                                   mt46h32m32lf6_sdrc_params);
>         board_nand_init(overo_nand_partitions,
>                         ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
> -       usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
> +       usb_bind_phy("musb-hdrc.1.auto", 0, "twl4030_usb");
>         usb_musb_init(NULL);
>  
>         usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
> 
> 
> Is that ID "randomly" chosen? Doesn't that mean that it'll just get broken
> every now and then?

Yes if so it's not a good solution. For omap4 we'll be flipping over to
be device tree only for v3.11, but that still leaves earlier omaps to
worry about.

I'll wait for a proper patch for the above for the -rc series after we
hear from Kishon.

Regards,

Tony


From tony at atomide.com  Thu May 16 12:21:45 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 09:21:45 -0700
Subject: [PATCH] ARM: dts: OMAP2+: Simplify NAND support
In-Reply-To: <1367331082-27944-1-git-send-email-jon-hunter@ti.com>
References: <1367331082-27944-1-git-send-email-jon-hunter@ti.com>
Message-ID: <20130516162144.GY5600@atomide.com>

* Jon Hunter <jon-hunter at ti.com> [130430 07:16]:
> Commit 8c8a777 (ARM: OMAP2+: Add function to read GPMC settings from
> device-tree) added a device-tree property "gpmc,device-nand" to indicate
> is the GPMC child device is NAND. This commit should have updated the
> GPMC NAND documentation (Documentation/devicetree/bindings/mtd/gpmc-nand.txt)
> to list the property "gpmc,device-nand" as a required property and also
> updated the example. However, this property is redundant and not needed
> because the GPMC child device node for NAND is called "nand". Therefore,
> remove this property.
> 
> Signed-off-by: Jon Hunter <jon-hunter at ti.com>

Thanks applying into omap-for-v3.11/gpmc.

Regards,

Tony


From steve.capper at linaro.org  Thu May 16 12:22:58 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 16 May 2013 17:22:58 +0100
Subject: [PATCH] ARM: remove the .vm_mm value from gate_vma.
In-Reply-To: <20130516143638.GR18614@n2100.arm.linux.org.uk>
References: <1368702394-1737-1-git-send-email-steve.capper@linaro.org>
 <20130516143638.GR18614@n2100.arm.linux.org.uk>
Message-ID: <20130516162257.GA7521@linaro.org>

On Thu, May 16, 2013 at 03:36:38PM +0100, Russell King - ARM Linux wrote:
> On Thu, May 16, 2013 at 12:06:34PM +0100, Steve Capper wrote:

[ ... ]

> 
> This looks fine - x86 also sets .vm_mm to NULL here.  So please put
> it in my patch system.  Does this need to be applied to stable
> kernels as well?  If so, please mark it with Cc: <stable at vger.kernel.org>
> (but do not send it to that address).  Also, it'd be worth checking
> which stable kernels it needs to be applied to.
> 
> Thanks.

Thank you Russell,
I couldn't see any branches in linux-stable that need this patch.
The patch is now in your system with id 7727/1.

Cheers,
-- 
Steve


From will.deacon at arm.com  Thu May 16 11:50:38 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 May 2013 16:50:38 +0100
Subject: [PATCH 3/3] ARM: kernel: fix __cpu_logical_map default
 initialization
In-Reply-To: <1368718447-19209-4-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368718447-19209-4-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <20130516155038.GK11706@mudshark.cambridge.arm.com>

On Thu, May 16, 2013 at 04:34:07PM +0100, Lorenzo Pieralisi wrote:
> For legacy reasons, the __cpu_logical_map array is initialized to 0.
> On old pre-DT ARM platforms, smp_setup_processor_id() generates
> __cpu_logical_map entries at boot before the number of possible CPUs is
> set-up, with values that can be considered valid MPIDRs even if they are
> not present in the system booting; this implies that the __cpu_logical_map[]
> might end up containing MPIDR values that can be considered valid at logical
> indexes corresponding to CPUs that are not marked as possible.
> 
> To prevent issues with the current implementation, this patch defines an
> MPIDR_INVALID value, statically initializes the __cpu_logical_map[] array to it
> and allows DT parsing code to overwrite values in the __cpu_logical_map array
> that were erroneously set-up in smp_setup_processor_id().

What issues have you actually hit with this?

> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> CC: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/include/asm/cputype.h  |  2 ++
>  arch/arm/include/asm/smp_plat.h |  2 +-
>  arch/arm/kernel/devtree.c       | 10 ++++++----
>  arch/arm/kernel/setup.c         |  2 +-
>  4 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 7652712..dba62cb 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -32,6 +32,8 @@
>  
>  #define MPIDR_HWID_BITMASK 0xFFFFFF
>  
> +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
> +
>  #define MPIDR_LEVEL_BITS 8
>  #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
>  
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index aaa61b6..e789832 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
>  /*
>   * Logical CPU mapping.
>   */
> -extern int __cpu_logical_map[];
> +extern u32 __cpu_logical_map[];
>  #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
>  /*
>   * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index d2293c0..08f012e 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -79,12 +79,12 @@ void __init arm_dt_init_cpu_maps(void)
>  	 * read as 0.
>  	 */
>  	static u32 tmp_map[NR_CPUS] __initdata = {
> -				[0 ... NR_CPUS-1] = UINT_MAX };
> +				[0 ... NR_CPUS-1] = MPIDR_INVALID };
>  	struct device_node *cpu, *cpus;
>  	u32 i, j, cpuidx = 1;
>  	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
> -
>  	bool bootcpu_valid = false;
> +

Random whitespace change.

Will


From linux at arm.linux.org.uk  Thu May 16 12:39:16 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 May 2013 17:39:16 +0100
Subject: [RFC] ARM: Allow user selection HZ values
Message-ID: <20130516163916.GU18614@n2100.arm.linux.org.uk>

Allow users to configure the Hz rate on implementations which do not have
a fixed clock rate.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
Whenever HZ_FIXED is not set through one of its "default" settings, the
user is allowed to select a tick rate from 100, 200, 250, 300, 500Hz
and 1kHz.  This is slightly more choice than with the generic HZ
selection in kernel/Kconfig.hz (which only does 100, 250, 300Hz and
1kHz).  The reason for including 200Hz is that a greater number of
other platforms want that via the fixed rate, and 500Hz just seemed
to be a better middle value than 300Hz (which is of course stupidly
close to 250.)

 arch/arm/Kconfig |   40 ++++++++++++++++++++++++++++++++++++++--
 1 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67874b8..dcd16ff 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1646,14 +1646,50 @@ config ARCH_NR_GPIO
 
 source kernel/Kconfig.preempt
 
-config HZ
+config HZ_FIXED
 	int
 	default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
 		ARCH_S5PV210 || ARCH_EXYNOS4
 	default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
 	default AT91_TIMER_HZ if ARCH_AT91
 	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
-	default 100
+
+choice
+	depends on !HZ_FIXED
+	prompt "Timer frequency"
+
+config HZ_100
+	bool "100 Hz"
+
+config HZ_200
+	bool "200 Hz"
+
+config HZ_250
+	bool "250 Hz"
+
+config HZ_300
+	bool "300 Hz"
+
+config HZ_500
+	bool "500 Hz"
+
+config HZ_1000
+	bool "1000 Hz"
+
+endchoice
+
+config HZ
+	int
+	default HZ_FIXED if HZ_FIXED
+	default 100 if HZ_100
+	default 200 if HZ_200
+	default 250 if HZ_250
+	default 300 if HZ_300
+	default 500 if HZ_500
+	default 1000
+
+config SCHED_HRTICK
+	def_bool HIGH_RES_TIMERS
 
 config THUMB2_KERNEL
 	bool "Compile the kernel in Thumb-2 mode"
-- 
1.7.4.4



From will.deacon at arm.com  Thu May 16 11:35:53 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 May 2013 16:35:53 +0100
Subject: dmatest regression in 3.10-rc1
In-Reply-To: <20130515152803.GL23869@mudshark.cambridge.arm.com>
References: <20130515152803.GL23869@mudshark.cambridge.arm.com>
Message-ID: <20130516153553.GI11706@mudshark.cambridge.arm.com>

On Wed, May 15, 2013 at 04:28:03PM +0100, Will Deacon wrote:
> I've been observing a regression in the dmatest module with 3.10-rc1. It
> manifests as either:
> 
>  - a spurious timeout on one or more of the channel threads
>  - a complete kernel lockup (loss of console)
>  - a panic (see below, noting that the callback [dmatest_callback] is
>    dereferencing a NULL pointer)
> 
> If I revert 77101ce578bb ("dmatest: cancel thread immediately when asked
> for") then things are rosy again, but I'm not sure if this is hiding another
> problem.

Right, so I think I understand what's causing this, but I'll leave it to
Andriy to suggest a fix. The problem comes about because the dmatest
module is now driven from debugfs, making it possible to unload the module
whilst a test run is in progress. In this case:

	- The DMA threads will return from wait_event_freezable_timeout(...)
	  due to kthread_should_stop() returning true, and subsequently
	  report failure because done.done is false.

	- The DMA engines may not be idle, so the asynchronous callback can
	  be invoked after we've started cleaning up, explaining the NULL
	  dereference I'm seeing.

The solutions are either fixing the module exit code to cope with concurrent
DMA transfers or to revert 77101ce578bb and not allow the channel threads to
return mid-transfer.

Will


From thomas.petazzoni at free-electrons.com  Thu May 16 12:46:58 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 16 May 2013 18:46:58 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130516184658.0650f838@skate>

Sebastian, Jason, Andrew, Gregory,

On Sat, 11 May 2013 03:08:00 +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
> 
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
> 
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
> 
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> 
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> 
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
> 
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
> 
> Sebastian Hesselbarth (10):
>   clk: mvebu: introduce per-clock-gate flags
>   clk: mvebu: add common clock functions for core clk and clk gating
>   clk: mvebu: add Dove SoC-centric clock init
>   clk: mvebu: add Kirkwood SoC-centric clock init
>   clk: mvebu: add Armada 370 SoC-centric clock init
>   clk: mvebu: add Armada XP SoC-centric clock init
>   ARM: dove: move DT boards to SoC-centric clock init
>   ARM: kirkwood: move DT boards to SoC-centric clock init
>   ARM: mvebu: move DT boards to SoC-centric clock init
>   clk: mvebu: desintegrate obsolete file

Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

I've tested on Armada 370 DB (after reverting the ARM core patch that
prevents this platform from booting) and the Armada XP DB. Both boards
boot fine, and detect PCIe devices as they should.

There is some conflict between this set of commits and the two commits
that modify the PCIe clocks in my PCIe series. I've pushed a branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
which has the mvebu PCIe stuff + Sebastian patches on top of it, with
the conflicts resolved. The tricky thing is that since Sebastian is
adding new clock files, and then removing the old ones, it's pretty
easy to "loose" the changes the two PCIe clock patches are doing. The
branch above works on Armada 370/XP, so you can compare the clock files
if needed.

Of course, I'm willing to do another final test once you've done the
merged to confirm that everything is alright.

I haven't done a detailed review of the patches, but I definitely agree
with the principle, and I trust Sebastian for having done the right
thing in here.

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From srinivas.kandagatla at st.com  Thu May 16 13:00:20 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Thu, 16 May 2013 18:00:20 +0100
Subject: [PATCH] ARM: prima2: return rather than panic on missing DT nodes
In-Reply-To: <1368719437-28287-1-git-send-email-robherring2@gmail.com>
References: <1368719437-28287-1-git-send-email-robherring2@gmail.com>
Message-ID: <519510A4.8090904@st.com>

Hi Rob,

I was just testing multi_v7_defconfig and noticed that the code is still
doing early_initcall and postcore_initcalls. Which IMO is NOK for
multiplatforms.

I was just about to send my patch and just noticed your patch.


On 16/05/13 16:50, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Missing nodes is a normal condition in multi-platform kernels when we boot
> on other platforms. So remove the panic and just return if we don't find
> a DT node.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Barry Song <baohua.song at csr.com>
> ---
>  arch/arm/mach-prima2/pm.c   | 2 +-
>  arch/arm/mach-prima2/rstc.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
> index 9936c18..a8003e2 100644
> --- a/arch/arm/mach-prima2/pm.c
> +++ b/arch/arm/mach-prima2/pm.c
> @@ -102,7 +102,7 @@ static int __init sirfsoc_of_pwrc_init(void)
>  
First thing is the mach code should not even attempt to run this
function in first place.

I think the correct fix for this is to move all the postcore_initcalls
and early_initcalls to callbacks in MACHINE.


Thanks,
srini

>  	np = of_find_matching_node(NULL, pwrc_ids);
>  	if (!np)
> -		panic("unable to find compatible pwrc node in dtb\n");
> +		return -ENODEV;
>  
>  	/*
>  	 * pwrc behind rtciobrg is not located in memory space
> diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
> index 435019c..6d7d9db 100644
> --- a/arch/arm/mach-prima2/rstc.c
> +++ b/arch/arm/mach-prima2/rstc.c
> @@ -29,7 +29,7 @@ static int __init sirfsoc_of_rstc_init(void)
>  
>  	np = of_find_matching_node(NULL, rstc_ids);
>  	if (!np)
> -		panic("unable to find compatible rstc node in dtb\n");
> +		return -ENODEV;
>  
>  	sirfsoc_rstc_base = of_iomap(np, 0);
>  	if (!sirfsoc_rstc_base)
> 



From lorenzo.pieralisi at arm.com  Thu May 16 11:34:07 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 16 May 2013 16:34:07 +0100
Subject: [PATCH 3/3] ARM: kernel: fix __cpu_logical_map default initialization
In-Reply-To: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368718447-19209-4-git-send-email-lorenzo.pieralisi@arm.com>

For legacy reasons, the __cpu_logical_map array is initialized to 0.
On old pre-DT ARM platforms, smp_setup_processor_id() generates
__cpu_logical_map entries at boot before the number of possible CPUs is
set-up, with values that can be considered valid MPIDRs even if they are
not present in the system booting; this implies that the __cpu_logical_map[]
might end up containing MPIDR values that can be considered valid at logical
indexes corresponding to CPUs that are not marked as possible.

To prevent issues with the current implementation, this patch defines an
MPIDR_INVALID value, statically initializes the __cpu_logical_map[] array to it
and allows DT parsing code to overwrite values in the __cpu_logical_map array
that were erroneously set-up in smp_setup_processor_id().

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
CC: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/cputype.h  |  2 ++
 arch/arm/include/asm/smp_plat.h |  2 +-
 arch/arm/kernel/devtree.c       | 10 ++++++----
 arch/arm/kernel/setup.c         |  2 +-
 4 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712..dba62cb 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -32,6 +32,8 @@
 
 #define MPIDR_HWID_BITMASK 0xFFFFFF
 
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6..e789832 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
 /*
  * Logical CPU mapping.
  */
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
 #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
 /*
  * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index d2293c0..08f012e 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -79,12 +79,12 @@ void __init arm_dt_init_cpu_maps(void)
 	 * read as 0.
 	 */
 	static u32 tmp_map[NR_CPUS] __initdata = {
-				[0 ... NR_CPUS-1] = UINT_MAX };
+				[0 ... NR_CPUS-1] = MPIDR_INVALID };
 	struct device_node *cpu, *cpus;
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
-
 	bool bootcpu_valid = false;
+
 	cpus = of_find_node_by_path("/cpus");
 
 	if (!cpus)
@@ -160,11 +160,13 @@ void __init arm_dt_init_cpu_maps(void)
 	/*
 	 * Since the boot CPU node contains proper data, and all nodes have
 	 * a reg property, the DT CPU list can be considered valid and the
-	 * logical map created in smp_setup_processor_id() can be overridden
+	 * logical map created in smp_setup_processor_id() can be overridden,
+	 * inclusive of entries that must contain invalid MPIDRs
 	 */
+	memcpy(__cpu_logical_map, tmp_map,
+			nr_cpu_ids * sizeof(tmp_map[0]));
 	for (i = 0; i < cpuidx; i++) {
 		set_cpu_possible(i, true);
-		cpu_logical_map(i) = tmp_map[i];
 		pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
 	}
 }
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6ae71b7..eeac924 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -457,7 +457,7 @@ void notrace cpu_init(void)
 	    : "r14");
 }
 
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 
 void __init smp_setup_processor_id(void)
 {
-- 
1.8.2.2



From festevam at gmail.com  Thu May 16 13:25:08 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 16 May 2013 14:25:08 -0300
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <1368713639-21485-2-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>
Message-ID: <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>

On Thu, May 16, 2013 at 12:50 PM, Fabio Estevam <festevam at gmail.com> wrote:

> Actually the correct is:
>
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -878,7 +878,7 @@
>                                 #size-cells = <0>;
>                                 compatible = "fsl,imx28-i2c";
>                                 reg = <0x80058000 0x2000>;
> -                               interrupts = <111 68>;
> +                               interrupts = <68>;
>                                 clock-frequency = <100000>;
>                                 dmas = <&dma_apbx 6>;
>                                 dma-names = "rx-tx";
> @@ -891,7 +891,7 @@
>                                 #size-cells = <0>;
>                                 compatible = "fsl,imx28-i2c";
>                                 reg = <0x8005a000 0x2000>;
> -                               interrupts = <110 69>;
> +                               interrupts = <69>;
>                                 clock-frequency = <100000>;
>                                 dmas = <&dma_apbx 7>;
>                                 dma-names = "rx-tx";

Sorry, the original patch is correct.

i2c slowness is a different issue.


From broonie at kernel.org  Thu May 16 13:23:58 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 16 May 2013 18:23:58 +0100
Subject: [PATCH] spi: sirf: fix the issue while transferring more than
 256 words
In-Reply-To: <CAGsJ_4wamqzwLZkUz4h6ex=oVQZhzhw7S6r41wt9tTUoMR=aXw@mail.gmail.com>
References: <1363592828-6347-1-git-send-email-Barry.Song@csr.com>
 <CAGsJ_4wamqzwLZkUz4h6ex=oVQZhzhw7S6r41wt9tTUoMR=aXw@mail.gmail.com>
Message-ID: <20130516172358.GA1627@sirena.org.uk>

On Wed, May 15, 2013 at 08:59:47PM +0800, Barry Song wrote:
> ping Mark, Ping Grant.

Don't top post, don't send contentless pings.  At a guess you didn't CC
me...
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From broonie at kernel.org  Thu May 16 13:26:05 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 16 May 2013 18:26:05 +0100
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <5194F0C0.9020609@balister.org>
References: <0bf5a185-86f7-4a93-a90f-42caefb06a1d@TX2EHSMHS009.ehs.local>
 <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum>
 <51927DEB.7090001@balister.org>
 <20130515044604.GA24524@sirena.org.uk>
 <51946082.1000606@codeaurora.org> <5194F0C0.9020609@balister.org>
Message-ID: <20130516172605.GB1627@sirena.org.uk>

On Thu, May 16, 2013 at 10:44:16AM -0400, Philip Balister wrote:
> On 05/16/2013 12:28 AM, Saravana Kannan wrote:

> > Agreed. I was about to reply with exactly the same point. I haven't done
> > any UIO coding, but that device file will eventually have to be opened.
> > Turn on the clocks in the open and turn them off at close.

> > Rate to request can be a DT property.

> But you are assuming each device implemented in the fpga uses one clock.
> This assumption is clearly not valid since devices will ahve to share
> clocks.

The binding should obviously be defined as a set of clocks rather than a
single clock - something like how we specify regulators on PMICs
probably makes sense.  Each clock can have its own properties.
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From catalin.marinas at arm.com  Thu May 16 10:58:48 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 May 2013 15:58:48 +0100
Subject: [RFC PATCH v2 08/11] ARM64: mm: Swap PTE_FILE and
 PTE_PROT_NONE bits.
In-Reply-To: <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-9-git-send-email-steve.capper@linaro.org>
Message-ID: <20130516145848.GE18308@arm.com>

On Wed, May 08, 2013 at 10:52:40AM +0100, Steve Capper wrote:
> Under ARM64, PTEs can be broadly categorised as follows:
>    - Present and valid: Bit #0 is set. The PTE is valid and memory
>      access to the region may fault.
> 
>    - Present and invalid: Bit #0 is clear and bit #1 is set.
>      Represents present memory with PROT_NONE protection. The PTE
>      is an invalid entry, and the user fault handler will raise a
>      SIGSEGV.
> 
>    - Not present (file): Bits #0 and #1 are clear, bit #2 is set.
>      Memory represented has been paged out. The PTE is an invalid
>      entry, and the fault handler will try and re-populate the
>      memory where necessary.
> 
> Huge PTEs are block descriptors that have bit #1 clear. If we wish
> to represent PROT_NONE huge PTEs we then run into a problem as
> there is no way to distinguish between regular and huge PTEs if we
> set bit #1.
> 
> As huge PTEs are always present, the meaning of bits #1 and #2 can
> be swapped for invalid PTEs. This patch swaps the PTE_FILE and
> PTE_PROT_NONE constants, allowing us to represent PROT_NONE huge
> PTEs.

I guess we'll never get a huge_(pte|pmd)_file() (but we can shift the
file bits up anyway).

> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Apart from the comments you already got:

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Thu May 16 10:32:36 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 May 2013 15:32:36 +0100
Subject: [RFC PATCH v2 09/11] ARM64: mm: HugeTLB support.
In-Reply-To: <1368006763-30774-10-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-10-git-send-email-steve.capper@linaro.org>
Message-ID: <20130516143236.GD18308@arm.com>

On Wed, May 08, 2013 at 10:52:41AM +0100, Steve Capper wrote:
> --- /dev/null
> +++ b/arch/arm64/include/asm/hugetlb.h
...
> +static inline int pud_large(pud_t pud)
> +{
> +	return !(pud_val(pud) & PUD_TABLE_BIT);
> +}

I already commented on this - do we really need pud_large() which is
the same as pud_huge()? It's only defined on x86 and can be safely
replaced with pud_huge().

> --- /dev/null
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -0,0 +1,70 @@
...
> +int pmd_huge(pmd_t pmd)
> +{
> +	return !(pmd_val(pmd) & PMD_TABLE_BIT);
> +}
> +
> +int pud_huge(pud_t pud)
> +{
> +	return !(pud_val(pud) & PUD_TABLE_BIT);
> +}

You could even go further and make pud/pmd_huge static inline functions
for slightly better efficiency (needs changing in the linux/hugetlb.h
header).

-- 
Catalin


From broonie at kernel.org  Thu May 16 13:35:59 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 16 May 2013 18:35:59 +0100
Subject: [alsa-devel] [PATCH] ASoC: dfbmcs320: make the driver common for
 other BT modules
In-Reply-To: <CAGsJ_4yn2uodRKrFKYrX85XA7A=hQs2w0cyGoEEHsYgCJHD7eQ@mail.gmail.com>
References: <1368687184-12169-1-git-send-email-Baohua.Song@csr.com>
 <5194AC3C.4080206@metafoo.de>
 <CAGsJ_4yoXj+e7A20SM5+ctLvE2QRTp0bzDeKfCZSUHTO8BPq5A@mail.gmail.com>
 <5194C2FC.70804@metafoo.de>
 <CAGsJ_4yn2uodRKrFKYrX85XA7A=hQs2w0cyGoEEHsYgCJHD7eQ@mail.gmail.com>
Message-ID: <20130516173559.GD1627@sirena.org.uk>

On Thu, May 16, 2013 at 08:00:17PM +0800, Barry Song wrote:

> i did think it is a good idea to have device id list while i sent the
> last mail. and it matches with the generic device driver engineering
> sense. the problem is i don't how long the list will be.
> if you like to keep dfbmcs320 at least for the moment, i would agree.

I'd prefer to see the ID list; we shouldn't be throwing away
information.  Probably we can go a long way towards cutting down the
length of the list if it gets silly with use of wildcards in the device
names listed.
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From tony at atomide.com  Thu May 16 13:43:56 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 10:43:56 -0700
Subject: [PATCH V5 1/6] clk: OMAP: introduce device tree binding to
 kernel clock data
In-Reply-To: <20130513235119.10068.47040@quantum>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
 <1368039976-29648-2-git-send-email-nm@ti.com>
 <20130513235119.10068.47040@quantum>
Message-ID: <20130516174355.GB5600@atomide.com>

* Mike Turquette <mturquette at linaro.org> [130513 16:56]:
> Quoting Nishanth Menon (2013-05-08 12:06:11)
> <snip>
> > Overall strategy introduced here is simple: a clock node described in
> > device tree blob is used to identify the exact clock provided in the
> > SoC specific data. This is then linked back using of_clk_add_provider
> > to the device node to be accessible by of_clk_get.
> > 
> 
> FYI, I'm working on moving the OMAP clocks over to DT which is a better
> alternative than this patch.  I'll share what I have on the list,
> hopefully next week.

That's good news! What's your plan on using the indexing the clocks?

I'd rather avoid indexing as that's basically same as the old IRQ
numbering and GPIO numbering schemes that don't work well in the long
term.

We already have quite a few sets of clocks for omaps, so the indexing
is already an issue. My thinking is that indexing should only be used
if the same physical clock has multiple outputs.

Regards,

Tony


From tony at atomide.com  Thu May 16 13:46:08 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 10:46:08 -0700
Subject: [PATCH] ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards
In-Reply-To: <5193296D.5040001@ti.com>
References: <20130511023557.GB28602@atomide.com>
 <5193296D.5040001@ti.com>
Message-ID: <20130516174608.GC5600@atomide.com>

* Kishon Vijay Abraham I <kishon at ti.com> [130514 23:27]:
> On Saturday 11 May 2013 08:05 AM, Tony Lindgren wrote:
> >Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to
> >OMAP3+ boards) added support for MUSB on omap3 for device tree,
> >but added the interrupts the wrong way probably as they were
> >copied from the omap4.dtsi file. On omap3 we have TI specific
> >interrupt controller, not GIC.
> >
> >Fix this by specifying the interrupt following the TI INTC
> >binding.
> >
> >Without this fix MUSB won't work as it is trying to use
> >irq0 instead of irq92.
> >
> >Signed-off-by: Tony Lindgren <tony at atomide.com>
> Tested in beagleboard-xm
> 
> Tested-by: Kishon Vijay Abraham I <kishon at ti.com>

Oops thanks, sorry I already pushed it out into omap-for-v3.10/dt-fixes
before noticing your tested-by.

Regards,

Tony

> >--- a/arch/arm/boot/dts/omap3.dtsi
> >+++ b/arch/arm/boot/dts/omap3.dtsi
> >@@ -516,7 +516,7 @@
> >  		usb_otg_hs: usb_otg_hs at 480ab000 {
> >  			compatible = "ti,omap3-musb";
> >  			reg = <0x480ab000 0x1000>;
> >-			interrupts = <0 92 0x4>, <0 93 0x4>;
> >+			interrupts = <92>, <93>;
> >  			interrupt-names = "mc", "dma";
> >  			ti,hwmods = "usb_otg_hs";
> >  			multipoint = <1>;
> >
> 


From tony at atomide.com  Thu May 16 13:48:47 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 10:48:47 -0700
Subject: [PATCH] ARM: OMAP: fix error return code in
 omap1_system_dma_init()
In-Reply-To: <CAPgLHd8iPa4efHsYsCmGE-j-GzZw7DtWdSaQqpEuF60-BRtmbg@mail.gmail.com>
References: <CAPgLHd8iPa4efHsYsCmGE-j-GzZw7DtWdSaQqpEuF60-BRtmbg@mail.gmail.com>
Message-ID: <20130516174847.GD5600@atomide.com>

* Wei Yongjun <weiyj.lk at gmail.com> [130512 21:30]:
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> 
> Fix to return -ENOMEM in the d->chan alloc error handling
> case instead of 0, as done elsewhere in this function.
> 
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Thanks, applying into omap-for-v3.10/fixes.

Regards,

Tony

> ---
>  arch/arm/mach-omap1/dma.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 68ab858..a94b3a7 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -345,6 +345,7 @@ static int __init omap1_system_dma_init(void)
>  		dev_err(&pdev->dev,
>  			"%s: Memory allocation failed for d->chan!\n",
>  			__func__);
> +		ret = -ENOMEM;
>  		goto exit_release_d;
>  	}
>  
> 


From lorenzo.pieralisi at arm.com  Thu May 16 12:23:33 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 16 May 2013 17:23:33 +0100
Subject: [PATCH 3/3] ARM: kernel: fix __cpu_logical_map default
 initialization
In-Reply-To: <20130516155038.GK11706@mudshark.cambridge.arm.com>
References: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368718447-19209-4-git-send-email-lorenzo.pieralisi@arm.com>
 <20130516155038.GK11706@mudshark.cambridge.arm.com>
Message-ID: <20130516162332.GA19375@e102568-lin.cambridge.arm.com>

On Thu, May 16, 2013 at 04:50:38PM +0100, Will Deacon wrote:
> On Thu, May 16, 2013 at 04:34:07PM +0100, Lorenzo Pieralisi wrote:
> > For legacy reasons, the __cpu_logical_map array is initialized to 0.
> > On old pre-DT ARM platforms, smp_setup_processor_id() generates
> > __cpu_logical_map entries at boot before the number of possible CPUs is
> > set-up, with values that can be considered valid MPIDRs even if they are
> > not present in the system booting; this implies that the __cpu_logical_map[]
> > might end up containing MPIDR values that can be considered valid at logical
> > indexes corresponding to CPUs that are not marked as possible.
> > 
> > To prevent issues with the current implementation, this patch defines an
> > MPIDR_INVALID value, statically initializes the __cpu_logical_map[] array to it
> > and allows DT parsing code to overwrite values in the __cpu_logical_map array
> > that were erroneously set-up in smp_setup_processor_id().
> 
> What issues have you actually hit with this?

I have not hit any, I just thought it would be proper to have the
cpu_logical_map filled with only valid (ie present in HW) MPIDRs (and
by default initialized with MPIDR_INVALID, not 0s which are valid MPIDRs).

I wrote the patch while coding the MPIDR to logical CPU reverse look-up
for the CCI driver and noticed that, if for any reason we do not
constrain the look-up to possible cpus, we might get a logical index
for a CPU that does not exist since smp_setup_processor_id() initializes
the cpu_logical_map up to nr_cpu_ids, with values that might well be
real MPIDRs (but not present in HW).

If we pass an mpidr value to get_logical_index(), that function must not
return a logical index for an MPIDR that does not exist in HW. This can
happen with current code (but I do not think anyone will ever call
get_logical_index() with a mpidr value that has not been read from a CPU
coprocessor, so what I am saying is purely hypothetical).
True, we might check the return value is actually a CPU marked as possible,
provided that check is safe to carry out in low-level PM code where it is
likely to be used.

Overall it can be overkill, granted, it was just meant to clean-up the code,
no more than that.

> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> > CC: Will Deacon <will.deacon at arm.com>
> > ---
> >  arch/arm/include/asm/cputype.h  |  2 ++
> >  arch/arm/include/asm/smp_plat.h |  2 +-
> >  arch/arm/kernel/devtree.c       | 10 ++++++----
> >  arch/arm/kernel/setup.c         |  2 +-
> >  4 files changed, 10 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> > index 7652712..dba62cb 100644
> > --- a/arch/arm/include/asm/cputype.h
> > +++ b/arch/arm/include/asm/cputype.h
> > @@ -32,6 +32,8 @@
> >  
> >  #define MPIDR_HWID_BITMASK 0xFFFFFF
> >  
> > +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
> > +
> >  #define MPIDR_LEVEL_BITS 8
> >  #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
> >  
> > diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> > index aaa61b6..e789832 100644
> > --- a/arch/arm/include/asm/smp_plat.h
> > +++ b/arch/arm/include/asm/smp_plat.h
> > @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
> >  /*
> >   * Logical CPU mapping.
> >   */
> > -extern int __cpu_logical_map[];
> > +extern u32 __cpu_logical_map[];
> >  #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
> >  /*
> >   * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
> > diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> > index d2293c0..08f012e 100644
> > --- a/arch/arm/kernel/devtree.c
> > +++ b/arch/arm/kernel/devtree.c
> > @@ -79,12 +79,12 @@ void __init arm_dt_init_cpu_maps(void)
> >  	 * read as 0.
> >  	 */
> >  	static u32 tmp_map[NR_CPUS] __initdata = {
> > -				[0 ... NR_CPUS-1] = UINT_MAX };
> > +				[0 ... NR_CPUS-1] = MPIDR_INVALID };
> >  	struct device_node *cpu, *cpus;
> >  	u32 i, j, cpuidx = 1;
> >  	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
> > -
> >  	bool bootcpu_valid = false;
> > +
> 
> Random whitespace change.

Gah, sorry.

Thanks for having a look,
Lorenzo


From tony at atomide.com  Thu May 16 14:04:25 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 11:04:25 -0700
Subject: [PATCH] ARM: OMAP: fix __init section mismatch for
 _enable_preprogram
In-Reply-To: <CAGGh5h1_-zbe=gw+YtMeddGxGkVzos=siavOv9nbSOVZqk1nVw@mail.gmail.com>
References: <CAGGh5h1_-zbe=gw+YtMeddGxGkVzos=siavOv9nbSOVZqk1nVw@mail.gmail.com>
Message-ID: <20130516180425.GE5600@atomide.com>

* jean-philippe francois <jp.francois at cynove.com> [130513 02:34]:
> Hi,
> 
> _enable_preprogram is marked as __init, but is called from _enable
> which is not. Without this patch, the board oopses after init. Tested
> on custom hardware and on beagle board xM.
> 
> Signed-off-by: Jean-Philippe Fran?ois <jp.francois at cynove.com>

Thanks applying into omap-for-v3.10/fixes.

Regards,

Tony


From lorenzo.pieralisi at arm.com  Thu May 16 11:34:06 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 16 May 2013 16:34:06 +0100
Subject: [PATCH 2/3] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu
 nodes
In-Reply-To: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368718447-19209-3-git-send-email-lorenzo.pieralisi@arm.com>

The introduction of the cpu-map topology node in the cpus node implies
that cpus node might have children that are not cpu nodes. The DT
parsing code needs updating otherwise it would check for cpu nodes
properties in nodes that are not required to contain them, resulting
in warnings that have no bearing on bindings defined in the dts source file.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/kernel/devtree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 3d652e4f..d2293c0 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -93,6 +93,9 @@ void __init arm_dt_init_cpu_maps(void)
 	for_each_child_of_node(cpus, cpu) {
 		u32 hwid;
 
+		if (of_node_cmp(cpu->type, "cpu"))
+			continue;
+
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
 		 * A device tree containing CPU nodes with missing "reg"
-- 
1.8.2.2



From tony at atomide.com  Thu May 16 14:06:50 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 11:06:50 -0700
Subject: [PATCH] ARM: defconfigs: OMAP: omap2plus_defconfig missing
 CONFIG_ARCH_MULTI_V6=y
In-Reply-To: <alpine.DEB.2.00.1305131703271.7156@utopia.booyaka.com>
References: <alpine.DEB.2.00.1305131701270.7156@utopia.booyaka.com>
 <alpine.DEB.2.00.1305131703271.7156@utopia.booyaka.com>
Message-ID: <20130516180650.GF5600@atomide.com>

* Paul Walmsley <paul at pwsan.com> [130513 10:09]:
> On Mon, 13 May 2013, Paul Walmsley wrote:
> 
> > Fix by setting CONFIG_ARCH_MULTI_V7.
> 
> Well, obvious typo here.  Here's the updated version.

Thanks applying into omap-for-v3.10/fixes.

Regards,

Tony


From catalin.marinas at arm.com  Thu May 16 11:01:56 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 May 2013 16:01:56 +0100
Subject: [RFC PATCH v2 11/11] ARM64: mm: THP support.
In-Reply-To: <1368006763-30774-12-git-send-email-steve.capper@linaro.org>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-12-git-send-email-steve.capper@linaro.org>
Message-ID: <20130516150155.GG18308@arm.com>

On Wed, May 08, 2013 at 10:52:43AM +0100, Steve Capper wrote:
> Bring Transparent HugePage support to ARM. The size of a
> transparent huge page depends on the normal page size. A
> transparent huge page is always represented as a pmd.
> 
> If PAGE_SIZE is 4KB, THPs are 2MB.
> If PAGE_SIZE is 64KB, THPs are 512MB.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From tony at atomide.com  Thu May 16 14:09:34 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 11:09:34 -0700
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
Message-ID: <20130516180933.GG5600@atomide.com>

* Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> Hi,
> 
> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> 
> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> 
> The error is coming from regmap code. According to git bisect, it is
> caused by:
> 
> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> 	Author: Jon Hunter <jon-hunter at ti.com>
> 	Date:   Fri Mar 1 11:22:47 2013 -0600
> 
> 	    gpio/omap: convert gpio irq domain to linear mapping
> 
> The commit does not anymore revert cleanly, and I haven't yet tried
> crafting a manual revert, so any fix proposals/ideas are welcome...

Hmm this might be a bit trickier to fix. Obviously the real solution
is to convert omap1 to SPARSE_IRQ like we did for omap2+.

For the -rc cycle, it might be possible to fix this by adding a
different irq_to_gpio() and gpio_to_irq() functions for omap1.

Regards,

Tony


From tony at atomide.com  Thu May 16 14:15:36 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 11:15:36 -0700
Subject: [PATCH] ARM : omap : remove __init for _enable_preprogram
In-Reply-To: <8738tpxwmj.fsf@linaro.org>
References: <1368547621-8570-1-git-send-email-jp.francois@cynove.com>
 <8738tpxwmj.fsf@linaro.org>
Message-ID: <20130516181536.GI5600@atomide.com>

* Kevin Hilman <khilman at linaro.org> [130514 11:13]:
> jp.francois at cynove.com writes:
> 
> > _enable_preprogram is marked as __init, but is called from _enable which is not.
> > This results in oops once init is freed.
> > Fix this by removing the __init marker.
> >
> > Signed-off-by: Jean-Philippe Fran?ois <jp.francois at cynove.com>
> 
> Acked-by: Kevin Hilman <khilman at linaro.org>
> 
> Tony, this should probably be queued for v3.10-rc, and tagged for stable.

Yes just applied the earlier version of this and added your
ack with cc: stable.

Regards,

Tony


From swarren at wwwdotorg.org  Thu May 16 14:17:37 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 12:17:37 -0600
Subject: Naming convention DSI + device tree
In-Reply-To: <20130516071537.GA13573@mail.o2s.ch>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org> <20130516071537.GA13573@mail.o2s.ch>
Message-ID: <519522C1.5010107@wwwdotorg.org>

On 05/16/2013 01:15 AM, David Lanzend?rfer wrote:
> On Wed, May 15, 2013 at 04:28:50PM -0600, Stephen Warren wrote:
>> On 05/14/2013 12:17 PM, David Lanzend?rfer wrote:
>>> Hello I have the following issue: In order to make the DSI
>>> controller react at all,
>> 
>> Hmm. In the upstream kernel, we don't even have a DSI driver at
>> all for Tegra, so control over the panel itself is likely the
>> least of your worries for now.
> 
> Is there a patch set pending for merge into upstream which will
> provide this support? And if yes, where can I find these pending
> patches? I'd like to build up my code based on already existing
> work which is expected to be in upstream at some later point of
> time.

No, we haven't yet posted DSI support upstream.

>>> I need to pass him a certain combination of pin states. Until
>>> now within the code of the original android kernel which was
>>> using board files this has just been done by doing bit
>>> banging.
>>> 
>>> namely: gpio_set_value(tf201_lvds_shutdown, 1); ... Now with a
>>> device tree comes the question: Where should I put this?
>> 
>> Likely, you will need to create a DT binding that represents the 
>> particular panel model that you have, and make the Tegra display 
>> controller node refer to that panel node. The panel node would
>> need properties to describe the various GPIOs used to control the
>> panel. Then, you'd want to write a panel-specific driver that
>> handles that device tree node.
> 
> That was my thought too. Where should I put this panel-specific
> driver?

Honestly, I'm not sure. I assume (and it is just an assumption) that
if you look at the CDF patches, you should find some examples of panel
drivers that use it, although perhaps there aren't any yet...

>> All of this will likely need to be integrated with the upcoming
>> Common Display Framework.
> 
> Is this upcoming CDF included within your "linux-next_common"
> branch?

No. That branch of mine is basd on linux-next, so whatever is in
linux-next is in my branch, and I certainly haven't applied the CDF
locally.

I believe the CDF has been posted to various mailing lists a few
times, but it isn't checked in yet since there isn't a final version.
I CC'd Alex; he might know the status better than me.


From nm at ti.com  Thu May 16 14:18:10 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 16 May 2013 13:18:10 -0500
Subject: [PATCH v4] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <5194FCDD.8080209@ti.com>
References: <1368636386-17138-1-git-send-email-dmurphy@ti.com>
 <20130515170516.GA6135@kahuna> <5194FCDD.8080209@ti.com>
Message-ID: <CAGo_u6pX+DdVNWqdPXDChzMr27YAXL_Zvt7DxWBijOCW0rXpkA@mail.gmail.com>

On Thu, May 16, 2013 at 10:35 AM, Dan Murphy <dmurphy at ti.com> wrote:
> I am not sure you really want to do this.
> If I make the pinctrl part of the led structure then the only way the gpio_wk7 on a1-a3 to be configured is when
> the CONFIG_LEDS_GPIO flag is set.
>
> Do you really want that dependency?  You did say it was a key fix
> At least this way the pins are configured regardless of that flag.

That is better as the system will be left in the pinmux configuration
handed over from bootloader.

The point being, muxing up pins even when not needed(config switched
off) has no real benefit - in this case albeit, the default mux was
causing a bug.
pinctrl IMHO should be considered as any other resource, if it is not
mandatory for boot, and needed only for a device functionality when
probed, it should done there only.

just my 2 cents.


From swarren at wwwdotorg.org  Thu May 16 14:19:48 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 12:19:48 -0600
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <51941C58.9060002@wwwdotorg.org>
 <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <51952344.1090003@wwwdotorg.org>

On 05/16/2013 03:53 AM, Joseph Lo wrote:
> On Thu, 2013-05-16 at 07:38 +0800, Stephen Warren wrote:
>> On 05/15/2013 04:27 AM, Joseph Lo wrote:
>>> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
>>> as CPU core and a enhanced flow controller for CPU power control. So
>>> we need to skip some code that was for Contex-A9 and some other support
>>> code that was for other Tegra SoC chips. Then adding the proper power up
>>> and hot plug control for Tegra114.
>>
>> This series mostly works OK, but I see one problem: I can't hotunplug
>> CPU0, which the commit descriptions and code changes imply I should be
>> able to do:
>>
>> root at localhost:~# echo 0 > /sys/devices/system/cpu/cpu0/online
>> -bash: echo: write error: Operation not permitted
> 
> I want to provide this function originally. But I found the
> tegra_cpu_disable() was removed recently. It was replaced by the common
> cpu_disable() function that didn't allow CPU0 to be un-plugged.

Is there a specific reason for that; is there some problem in the core
ARM code that implies CPU0 should never be disabled?

> But I had verified the CPU0 is OK to be un-plugged on the older
> linux-next branch that tegra_cpu_disable() watn't removed yet.
> 
> Do you want me to add them back to support this function for Tegra114?

If there is a problem removing CPU0 in the core code, the functionality
of this series is OK, although it's probably worth removing the parts
that attempt to make CPU0 hot-unpluggable to reduce the diff size.

If there's no problem removing CPU0, it'd be good to make it work,
although that could be done in followon patches.


From swarren at wwwdotorg.org  Thu May 16 14:21:19 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 12:21:19 -0600
Subject: [PATCH 1/6] ARM: tegra: add an assembly marco to check Tegra
 SoC ID
In-Reply-To: <1368698988.7403.25.camel@jlo-ubuntu-64.nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-2-git-send-email-josephl@nvidia.com>
 <51940FA4.6050609@wwwdotorg.org>
 <1368698988.7403.25.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <5195239F.5030602@wwwdotorg.org>

On 05/16/2013 04:09 AM, Joseph Lo wrote:
> On Thu, 2013-05-16 at 06:43 +0800, Stephen Warren wrote:
>> On 05/15/2013 04:27 AM, Joseph Lo wrote:
>>> There are some Tegra SoC ID checking code around the low level assembly
>>> code. Adding a marco to replace them. For the single image to support all
>>> the Tegra series, we may also need the marco in other common code. So we
>>> make it become a marco for the usage.
>>
>> I'm not sure this patch doesn't obfuscate the code too much. The big
>> issue I see is:
>>
>>> @@ -115,13 +112,9 @@ ENTRY(__tegra_cpu_reset_handler)
>>>  
>>>  	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
>>>  
>>> -	mov32	r6, TEGRA_APB_MISC_BASE
>>> -	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
>>> -	and	r6, r6, #0xff00
>>> -#ifdef CONFIG_ARCH_TEGRA_2x_SOC
>>> -t20_check:
>>> -	cmp	r6, #(0x20 << 8)
>>> +	tegra_check_soc_id TEGRA20, TEGRA_APB_MISC_BASE, r6, r5
>>
>> Here, we replace all the code with the new macro, ...
>>
>>>  #ifdef CONFIG_ARCH_TEGRA_2x_SOC
>>>  	/* Are we on Tegra20? */
>>> -	cmp	r6, #(0x20 << 8)
>>> +	cmp	r6, #(TEGRA20 << 8)
>>
>> But here we still have to write out the cmp instructions.
>>
> The marco did "cmp" once and move the soc_id into r6. But the flags may
> be changed after running some other codes, we need to "cmp" again to get
> the correct flag.

Yes, I understand that. The issue is that writing the macro didn't
remove all the code, so it seems like it'd be best if the macro only
included the common code, and anything that needs to be repeated at each
test site not be part of the macro.


From broonie at kernel.org  Thu May 16 14:21:22 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 16 May 2013 19:21:22 +0100
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <51945F27.7010003@codeaurora.org>
References: <1368207091-32538-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368207091-32538-2-git-send-email-soren.brinkmann@xilinx.com>
 <518D320C.4010707@elopez.com.ar>
 <fe9e603e-a432-4a29-a195-fd393b875a7e@TX2EHSMHS006.ehs.local>
 <518D411D.9070209@elopez.com.ar>
 <CAPtuhTgsP4gvMAFoQb3icXAZw3ucSg4dfrAdJMho-VxNmNTvwg@mail.gmail.com>
 <518D7C45.2090602@codeaurora.org>
 <20130511142132.GA3200@sirena.org.uk>
 <51945F27.7010003@codeaurora.org>
Message-ID: <20130516182122.GG1627@sirena.org.uk>

On Wed, May 15, 2013 at 09:23:03PM -0700, Saravana Kannan wrote:
> On 05/11/2013 07:21 AM, Mark Brown wrote:

> >It's much harder when it's in the standard kernel and there's no contact
> >with some of the users.  I've pushed back pretty strongly on some of
> >your equivalent stuff for regulators for this reason.

> Agreed. I don't really keep up with what's going on with the MSM regulators.

> But at some point, I'll start requesting for this for debugfs. It's
> terribly handy to debug power issues, run unit tests and for debug
> sessions (debugfs. So, clearly!).

Sure, it's handy for debugging - but it's also far too handy for writing
silly things in userspace which isn't something we want to encourage.
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From swarren at wwwdotorg.org  Thu May 16 14:24:23 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 12:24:23 -0600
Subject: [PATCH 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <1368700533.7403.47.camel@jlo-ubuntu-64.nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-4-git-send-email-josephl@nvidia.com>
 <519412E9.2080905@wwwdotorg.org>
 <1368700533.7403.47.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <51952457.4050108@wwwdotorg.org>

On 05/16/2013 04:35 AM, Joseph Lo wrote:
> On Thu, 2013-05-16 at 06:57 +0800, Stephen Warren wrote:
>> On 05/15/2013 04:27 AM, Joseph Lo wrote:

>>> diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S

>>> +	cpu_to_csr_req r1, r0
>>
>> Where is cpu_to_csr_req defined? grep can't find it in next-20130513,
>> and I don't see it added in this series.
>
> The cpu_to_csr_reg macro was defined in "sleep.h".

So it is. I fail at grep.

> I was used to
> translate the bit offset of CPU number in CSR register. The code here
> was used for CPU0 on Tegra30 only before.
...
>> This presumably changes behaviour on Tegra30; will this cause problems?

Ah, OK.

>>> +	mov32	r2, TEGRA_FLOW_CTRL_BASE
>>> +	ldr	r1, [r2, r1]
>>>  	/* Clear event & intr flag */
>>>  	orr	r1, r1, \
>>>  		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
>>> -	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
>>> +	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, & bitmaps
>>
>> What does this change do; does the commend need updating to describe the
>> new bits that are set?
>
> It clear the some extensions for CPU power control on Tegra114.

OK; I was implying that perhaps the comment needs updating?



From swarren at wwwdotorg.org  Thu May 16 14:26:49 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 12:26:49 -0600
Subject: [PATCH 6/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1368702862.7403.86.camel@jlo-ubuntu-64.nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-7-git-send-email-josephl@nvidia.com>
 <5194162D.7010007@wwwdotorg.org>
 <1368702862.7403.86.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <519524E9.8000401@wwwdotorg.org>

On 05/16/2013 05:14 AM, Joseph Lo wrote:
> On Thu, 2013-05-16 at 07:11 +0800, Stephen Warren wrote:
>> On 05/15/2013 04:27 AM, Joseph Lo wrote:
>>> The Tegra114 is a quad cores SoC. Each core can be hotplugged including
>>> CPU0. The hotplug sequence can be controlled by setting event trigger in
>>> flow controller. Then the flow controller will take care all the power
>>> sequence that include CPU up and down.

>>>  	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
>>> +	beq	flow_ctrl_setting_for_lp2
>>> +
>>> +	/* flow controller set up for hotplug */
>>> +	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
>>> +	b	flow_ctrl_done
>>> +flow_ctrl_setting_for_lp2:
>>> +	/* flow controller set up for LP2 */
>>> +	cmp	r10, #(TEGRA30 << 8)
>>>  	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
>>
>> Do you need e.g. "movne r3, #0" or similar here? Otherwise, I think r3
>> ends up not being initialized.
> 
> Yes, I will add the code when I add LP2 support for Tegra114 later.
> Currently the LP2 code flow only for Tegra30, so it's OK.

Ah, I see. Can we add the extra move to make sure the register is always
initialized now even though the path won't be used. That way, nobody
will be confused by this.

>>> -	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
>>> +flow_ctrl_done:
>>> +	cmp	r10, #(TEGRA30 << 8)
>>>  	str	r3, [r2]
>>
>> I wonder whether creating a separate tegra114_cpu_shutdown() wouldn't be
>> better, to avoid all the runtime conditional code.
> 
> I personally think the conditional code is OK. And the ARM CPU also had
> hardware for branch detection also.
> 
> I had finished some further features for both Tegra30 and Tegra114. And
> most of the code here can be shared each other at least until now I
> could see. Once I see if there is a significant difference, then I would
> prepare maintain the code separately too.

OK, if the function gets larger with more shared, I guess it's fine.
Right now, the conditional-to-non-conditional code ratio is pretty high.


From paul at pwsan.com  Thu May 16 14:32:43 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 16 May 2013 18:32:43 +0000 (UTC)
Subject: [PATCH v3 0/6] ARM: OMAP2+: hwmod and SERIAL: Remove sysc handling
 from driver
In-Reply-To: <1368629322-3170-1-git-send-email-rnayak@ti.com>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
Message-ID: <alpine.DEB.2.00.1305161831390.21357@utopia.booyaka.com>

On Wed, 15 May 2013, Rajendra Nayak wrote:

> OMAP UART IP needs manual idle modes based on functional state of the
> IP. Currently this is handled by the driver with function pointers
> implemented in platform code.
> 
> This however breaks in case of device tree because of missing
> idle handling. 
> 
> The series tries to address the issue and tries to remove complete
> sysc handling from serial driver.

These look good to me.  Will queue them for v3.10-rc once they pass local 
testing here.


- Paul


From paul at pwsan.com  Thu May 16 14:33:28 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 16 May 2013 18:33:28 +0000 (UTC)
Subject: OMAP baseline test results for v3.9
In-Reply-To: <20130514225221.GD5600@atomide.com>
References: <alpine.DEB.2.00.1305081933270.19747@utopia.booyaka.com>
 <20130514211328.GC5600@atomide.com>
 <alpine.DEB.2.00.1305142116001.4368@utopia.booyaka.com>
 <20130514225221.GD5600@atomide.com>
Message-ID: <alpine.DEB.2.00.1305161832520.21357@utopia.booyaka.com>

On Tue, 14 May 2013, Tony Lindgren wrote:

> Thanks that explains. BTW, the "PM off" naming might make some
> people think that CONFIG_PM is not set :)

That's a good point.  Will rename that and probably split the 3730 Beagle 
XM into its own testing category.


- Paul


From tony at atomide.com  Thu May 16 14:35:16 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 11:35:16 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <5194B2A8.8020608@visionsystems.de>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
Message-ID: <20130516183516.GJ5600@atomide.com>

* Yegor Yefremov <yegor_sub1 at visionsystems.de> [130516 05:13]:
> On 15.05.2013 23:50, Mark A. Greer wrote:
> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
> >> * Mark A. Greer <mgreer at animalcreek.com> [130514 18:57]:
> >>> On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
> >>>> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> >>>> changed PM to not access IVA registers on omaps that don't have
> >>>> them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
> >>>> will stay on and block deeper idle states.
> >>>>
> >>>> Signed-off-by: Tony Lindgren <tony at atomide.com>
> >>>>
> >>>> ---
> >>>>
> >>>> Paul & Kevin, do you have better ideas for fixing this?
> >>>>
> >>>> --- a/arch/arm/mach-omap2/pm34xx.c
> >>>> +++ b/arch/arm/mach-omap2/pm34xx.c
> >>>> @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
> >>>>  	/* Clear any pending PRCM interrupts */
> >>>>  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> >>>>  
> >>>> -	if (omap3_has_iva())
> >>>> -		omap3_iva_idle();
> >>>> +	/*
> >>>> +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> >>>> +	 */
> >>>> +	omap3_iva_idle();
> >>>>  
> >>>>  	omap3_d2d_idle();
> >>>>  }
> >>>
> >>> [Kevin, Paul, some background: Tony discovered that the am3703 needs
> >>> to have omap3_iva_idle() called even though its not supposed to have
> >>> an IVA.]
> >>>
> >>> This is potentially bad for other SoC's that don't have an IVA so I don't
> >>> think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
> >>> flag for the am3703 only since its the one with the bug.  Maybe something
> >>> in id.c:omap3xxx_check_features() but I don't see any existing way to check
> >>> for an am3703 vs. other am37xx SoCs.  Any ideas?
> >>>
> >>> Another option, I suppose, is a dts entry but I don't like that at all.
> >>
> >> It seems that iva2_pwrdm is there for all omap3 even if OMAP3_HAS_IVA
> >> flag is unset. And if that's the case, iva2 clocks still need to be idled
> >> in all cases.
> > 
> > Ahh, this takes us to the "Great TI Docs Mystery" :) -- its basically
> > impossible to tell because despite what their docs may say, the hardware
> > can be quite different.  I'm not sure how to proceed other than trial &
> > error with as many different SoCs as we can find.
> > 
> >> It's possible that not all steps in omap3_iva_idle() are needed though.
> >> I can debug further to see which part of the omap3_iva_idle() are needed.
> >>
> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
> >> idle states with?
> > 
> > I have an am35xx which isn't supposed to have an IVA so I can test with it
> > (although, I'm not sure how well the kernel works on the am35xx these days).
> > 
> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
> > comes up, see what I can figure out.
> 
> I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html

OK sounds like Mark's patch as http://www.spinics.net/lists/arm-kernel/msg168865.html
is needed as a fix.
 
> I have such a system running, so if you have any other patches/ideas to test, I would do it.

Well I think my patch does not matter for am3517 as that one has iva2
while am3703 does not.

Regards,

Tony


From peterz at infradead.org  Thu May 16 14:40:41 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Thu, 16 May 2013 20:40:41 +0200
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
Message-ID: <20130516184041.GP19669@dyad.programming.kicks-ass.net>

On Thu, May 16, 2013 at 02:16:10PM +0300, Michael S. Tsirkin wrote:
> There are several ways to make sure might_fault
> calling function does not sleep.
> One is to use it on kernel or otherwise locked memory - apparently
> nfs/sunrpc does this. As noted by Ingo, this is handled by the
> migh_fault() implementation in mm/memory.c but not the one in
> linux/kernel.h so in the current code might_fault() schedules
> differently depending on CONFIG_PROVE_LOCKING, which is an undesired
> semantical side effect.
> 
> Another is to call pagefault_disable: in this case the page fault
> handler will go to fixups processing and we get an error instead of
> sleeping, so the might_sleep annotation is a false positive.
> vhost driver wants to do this now in order to reuse socket ops
> under a spinlock (and fall back on slower thread handler
> on error).

Are you using the assumption that spin_lock() implies preempt_disable() implies
pagefault_disable()? Note that this assumption isn't valid for -rt where the
spinlock becomes preemptible but we'll not disable pagefaults.

> Address both issues by:
> 	- dropping the unconditional call to might_sleep
> 	  from the fast might_fault code in linux/kernel.h
> 	- checking for pagefault_disable() in the
> 	  CONFIG_PROVE_LOCKING implementation
> 
> Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
> ---
>  include/linux/kernel.h |  1 -
>  mm/memory.c            | 14 +++++++++-----
>  2 files changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/include/linux/kernel.h b/include/linux/kernel.h
> index e96329c..322b065 100644
> --- a/include/linux/kernel.h
> +++ b/include/linux/kernel.h
> @@ -198,7 +198,6 @@ void might_fault(void);
>  #else
>  static inline void might_fault(void)
>  {
> -	might_sleep();

This removes potential resched points for PREEMPT_VOLUNTARY -- was that
intentional?

>  }
>  #endif
>  
> diff --git a/mm/memory.c b/mm/memory.c
> index 6dc1882..1b8327b 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -4222,13 +4222,17 @@ void might_fault(void)
>  	if (segment_eq(get_fs(), KERNEL_DS))
>  		return;
>  
> -	might_sleep();
>  	/*
> -	 * it would be nicer only to annotate paths which are not under
> -	 * pagefault_disable, however that requires a larger audit and
> -	 * providing helpers like get_user_atomic.
> +	 * It would be nicer to annotate paths which are under preempt_disable
> +	 * but not under pagefault_disable, however that requires a new flag
> +	 * for differentiating between the two.

-rt has this, pagefault_disable() doesn't change the preempt count but pokes
at task_struct::pagefault_disable.

>  	 */
> -	if (!in_atomic() && current->mm)
> +	if (in_atomic())
> +		return;
> +
> +	might_sleep();
> +
> +	if (current->mm)
>  		might_lock_read(&current->mm->mmap_sem);
>  }
>  EXPORT_SYMBOL(might_fault);
> -- 
> MST


From tony at atomide.com  Thu May 16 14:54:44 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 11:54:44 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130516183516.GJ5600@atomide.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
 <20130516183516.GJ5600@atomide.com>
Message-ID: <20130516185444.GK5600@atomide.com>

* Tony Lindgren <tony at atomide.com> [130516 11:40]:
> * Yegor Yefremov <yegor_sub1 at visionsystems.de> [130516 05:13]:
> > 
> > I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
> > I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
> 
> OK sounds like Mark's patch as http://www.spinics.net/lists/arm-kernel/msg168865.html
> is needed as a fix.

Yegor, thinking about your boot issue more, I'm thinking that you
have your board .init_time = omap3_secure_sync32k_timer_init, or
some non-waking gpt timer. And that means the system won't wake to
timer events.

The system should still wake to timer events even if you have no
wake-up events configred, so Mark's patch probably does not fix
the right issue for you.

Regards,

Tony


From soren.brinkmann at xilinx.com  Thu May 16 14:55:45 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Thu, 16 May 2013 11:55:45 -0700
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <20130516172605.GB1627@sirena.org.uk>
References: <519112F9.2010102@gmail.com>
 <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum>
 <51927DEB.7090001@balister.org>
 <20130515044604.GA24524@sirena.org.uk>
 <51946082.1000606@codeaurora.org> <5194F0C0.9020609@balister.org>
 <20130516172605.GB1627@sirena.org.uk>
Message-ID: <1b69c011-cab5-4fde-a61d-7e2536208920@CH1EHSMHS003.ehs.local>

On Thu, May 16, 2013 at 06:26:05PM +0100, Mark Brown wrote:
> On Thu, May 16, 2013 at 10:44:16AM -0400, Philip Balister wrote:
> > On 05/16/2013 12:28 AM, Saravana Kannan wrote:
> 
> > > Agreed. I was about to reply with exactly the same point. I haven't done
> > > any UIO coding, but that device file will eventually have to be opened.
> > > Turn on the clocks in the open and turn them off at close.
> 
> > > Rate to request can be a DT property.
> 
> > But you are assuming each device implemented in the fpga uses one clock.
> > This assumption is clearly not valid since devices will ahve to share
> > clocks.
> 
> The binding should obviously be defined as a set of clocks rather than a
> single clock - something like how we specify regulators on PMICs
> probably makes sense.  Each clock can have its own properties.
For a device driver as clock consumer, the bindings etc. are well
defined. Just add the 'clocks' and 'clock-names' props and use the CCF.

	S?ren




From lorenzo.pieralisi at arm.com  Thu May 16 11:34:04 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 16 May 2013 16:34:04 +0100
Subject: [PATCH 0/3] ARM: kernel: cpu_logical_map misc fixes
Message-ID: <1368718447-19209-1-git-send-email-lorenzo.pieralisi@arm.com>

Hi Russell, Rob,

this series contains simple fixes/improvements related to the DT
cpu_logical_map initialization code. I would like to get these patches
in in order to have a stable base on top of which I can send the DT topology
bindings and cpu_logical_map bindings/parsing code updates for arm and arm64.

Thank you very much,
Lorenzo

Lorenzo Pieralisi (3):
  ARM: DT: kernel: move temporary cpu map stack array to static data
  ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
  ARM: kernel: fix __cpu_logical_map default initialization

 arch/arm/include/asm/cputype.h  |  2 ++
 arch/arm/include/asm/smp_plat.h |  2 +-
 arch/arm/kernel/devtree.c       | 14 ++++++++++----
 arch/arm/kernel/setup.c         |  2 +-
 4 files changed, 14 insertions(+), 6 deletions(-)

-- 
1.8.2.2



From dinguyen at altera.com  Thu May 16 15:05:15 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 16 May 2013 14:05:15 -0500
Subject: [PATCHv2 4/6] ARM: socfpga: Add syscon to be part of socfpga
In-Reply-To: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368731117-4749-4-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

SOCFPGA has a system manager register block can be accessed by using
the syscon driver.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Cc: <linux at arm.linux.org.uk>
---
 arch/arm/mach-socfpga/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 566e804..07dff6f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -13,5 +13,6 @@ config ARCH_SOCFPGA
 	select GPIO_PL061 if GPIOLIB
 	select HAVE_ARM_SCU
 	select HAVE_SMP
+	select MFD_SYSCON
 	select SPARSE_IRQ
 	select USE_OF
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 16 15:05:14 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 16 May 2013 14:05:14 -0500
Subject: [PATCHv2 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368731117-4749-3-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Mike Turquette <mturquette at linaro.org>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Fix space/indent errors
- Add streq for strcmp == 0
---
 drivers/clk/socfpga/clk.c |  197 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 188 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315..1ca1791 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,15 +24,17 @@
 #include <linux/of.h>
 
 /* Clock Manager offsets */
-#define CLKMGR_CTRL    0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL	0x0
+#define CLKMGR_BYPASS	0x4
+#define CLKMGR_L4SRC	0x70
+#define CLKMGR_PERPLL_SRC	0xAC
 
 /* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS		(1<<0)
+#define SDRAMPLL_BYPASS		(1<<1)
+#define SDRAMPLL_SRC_BYPASS	(1<<2)
+#define PERPLL_BYPASS		(1<<3)
+#define PERPLL_SRC_BYPASS	(1<<4)
 
 #define SOCFPGA_PLL_BG_PWRDWN		0
 #define SOCFPGA_PLL_EXT_ENA		1
@@ -41,6 +43,17 @@
 #define SOCFPGA_PLL_DIVF_SHIFT	3
 #define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT	16
+#define SOCFGPA_MAX_PARENTS	3
+
+#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
+#define SOCFPGA_NAND_CLK		"nand_clk"
+#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
+#define SOCFPGA_MMC_CLK			"mmc_clk"
+#define SOCFPGA_DB_CLK			"gpio_db_clk"
+
+#define div_mask(width)	((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -49,6 +62,9 @@ struct socfpga_clk {
 	char *parent_name;
 	char *clk_name;
 	u32 fixed_div;
+	void __iomem *div_reg;
+	u32 width;	/* only valid if div_reg != 0 */
+	u32 shift;	/* only valid if div_reg != 0 */
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 
 	socfpga_clk->hw.hw.init = &init;
 
-	if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
-			strcmp(clk_name, "sdram_pll")) {
+	if (streq(clk_name, "main_pll") ||
+		streq(clk_name, "periph_pll") ||
+		streq(clk_name, "sdram_pll")) {
 		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
 		clk_pll_ops.enable = clk_gate_ops.enable;
 		clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +165,162 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 	return clk;
 }
 
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+	u32 l4_src;
+	u32 perpll_src;
+	u8 parent;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		l4_src &= 0x1;
+		parent = l4_src;
+	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		l4_src = ((l4_src & 0x2) >> 1);
+		parent = l4_src;
+	} else {
+		perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+			perpll_src &= 0x3;
+		else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+			perpll_src = ((perpll_src & 0xC) >> 2);
+		else /*QSPI clock */
+			perpll_src = ((perpll_src & 0x30) >> 4);
+		parent = perpll_src;
+	}
+
+	return parent;
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+	u32 src_reg;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x1;
+		src_reg |= parent;
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x2;
+		src_reg |= (parent << 1);
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+			src_reg &= ~0x3;
+			src_reg |= parent;
+		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+			src_reg &= ~0xC;
+			src_reg |= (parent << 2);
+		} else {/*QSPI clock */
+			src_reg &= ~0x30;
+			src_reg |= (parent << 4);
+		}
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	}
+
+	return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+	u32 div = 1, val;
+
+	if (socfpgaclk->fixed_div)
+		div = socfpgaclk->fixed_div;
+	else if (socfpgaclk->div_reg) {
+		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+		val &= div_mask(socfpgaclk->width);
+		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+			div = val + 1;
+		else
+			div = (1 << val);
+	}
+
+	return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+	.recalc_rate = socfpga_clk_recalc_rate,
+	.get_parent = socfpga_clk_get_parent,
+	.set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 clk_gate[2];
+	u32 div_reg[3];
+	u32 fixed_div;
+	struct clk *clk;
+	struct socfpga_clk *socfpga_clk;
+	const char *clk_name = node->name;
+	const char *parent_name[SOCFGPA_MAX_PARENTS];
+	struct clk_init_data init;
+	int rc;
+	int i = 0;
+
+	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+	if (WARN_ON(!socfpga_clk))
+		return;
+
+	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+	if (rc)
+		clk_gate[0] = 0;
+
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		socfpga_clk->fixed_div = 0;
+	else
+		socfpga_clk->fixed_div = fixed_div;
+
+	if (clk_gate[0]) {
+		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+		socfpga_clk->hw.bit_idx = clk_gate[1];
+
+		gateclk_ops.enable = clk_gate_ops.enable;
+		gateclk_ops.disable = clk_gate_ops.disable;
+	}
+
+	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+	if (!rc) {
+		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+		socfpga_clk->shift = div_reg[1];
+		socfpga_clk->width = div_reg[2];
+	} else {
+		socfpga_clk->div_reg = 0;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+			of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	init.parent_names = parent_name;
+	init.num_parents = i;
+	socfpga_clk->hw.hw.init = &init;
+
+	clk = clk_register(NULL, &socfpga_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(socfpga_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(rc))
+		return;
+}
+
 static void __init socfpga_pll_init(struct device_node *node)
 {
 	socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +333,12 @@ static void __init socfpga_periph_init(struct device_node *node)
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
 
+static void __init socfpga_gate_init(struct device_node *node)
+{
+	socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
 void __init socfpga_init_clocks(void)
 {
 	struct clk *clk;
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 16 15:05:13 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 16 May 2013 14:05:13 -0500
Subject: [PATCHv2 2/6] ARM: socfpga: dts: Add gate-clock bindings
In-Reply-To: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368731117-4749-2-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
the peripherals.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 .../devicetree/bindings/clock/altr_socfpga.txt     |    7 +
 arch/arm/boot/dts/socfpga.dtsi                     |  199 ++++++++++++++++++++
 2 files changed, 206 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index bd0c841..0045433 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -9,6 +9,9 @@ Required properties:
 	"altr,socfpga-pll-clock" - for a PLL clock
 	"altr,socfpga-perip-clock" - The peripheral clock divided from the
 		PLL clock.
+	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
 	either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+        and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+        and width.
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 02bb425..bee62a2 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -95,6 +95,12 @@
 						compatible = "fixed-clock";
 					};
 
+					f2s_periph_ref_clk: f2s_periph_ref_clk {
+						#clock-cells = <0>;
+						compatible = "fixed-clock";
+						clock-frequency = <10000000>;
+					};
+
 					main_pll: main_pll {
 						#address-cells = <1>;
 						#size-cells = <0>;
@@ -236,6 +242,199 @@
 							reg = <0xD4>;
 						};
 					};
+
+				mpu_periph_clk: mpu_periph_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <4>;
+					};
+
+				mpu_l2_ram_clk: mpu_l2_ram_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <2>;
+					};
+
+				l4_main_clk: l4_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					clk-gate = <0x60 0>;
+					};
+
+				l3_main_clk: l3_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					};
+
+				l3_mp_clk: l3_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 0 2>;
+					clk-gate = <0x60 1>;
+					};
+
+				l3_sp_clk: l3_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 2 2>;
+				};
+
+				l4_mp_clk: l4_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 4 3>;
+					clk-gate = <0x60 2>;
+					};
+
+				l4_sp_clk: l4_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 7 3>;
+					clk-gate = <0x60 3>;
+					};
+
+				dbg_at_clk: dbg_at_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 0 2>;
+					clk-gate = <0x60 4>;
+					};
+
+				dbg_clk: dbg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 2 2>;
+					clk-gate = <0x60 5>;
+					};
+
+				dbg_trace_clk: dbg_trace_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x6C 0 3>;
+					clk-gate = <0x60 6>;
+					};
+
+				dbg_timer_clk: dbg_timer_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					clk-gate = <0x60 7>;
+					};
+
+				cfg_clk: cfg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 8>;
+					};
+
+				s2f_user0_clk: s2f_user0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 9>;
+					};
+
+				emac_0_clk: emac_0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac0_clk>;
+					clk-gate = <0xa0 0>;
+					};
+
+				emac_1_clk: emac_1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac1_clk>;
+					clk-gate = <0xa0 1>;
+					};
+
+				usb_mp_clk: usb_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 2>;
+					div-reg = <0xa4 0 3>;
+					};
+
+				spi_m_clk: spi_m_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 3>;
+					div-reg = <0xa4 3 3>;
+					};
+
+				can0_clk: can0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 4>;
+					div-reg = <0xa4 6 3>;
+					};
+
+				can1_clk: can1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 5>;
+					div-reg = <0xa4 9 3>;
+					};
+
+				gpio_db_clk: gpio_db_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 6>;
+					div-reg = <0xa8 0 24>;
+					};
+
+				s2f_user1_clk: s2f_user1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&s2f_usr1_clk>;
+					clk-gate = <0xa0 7>;
+					};
+
+				sdmmc_clk: sdmmc_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 8>;
+					};
+
+				nand_x_clk: nand_x_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 9>;
+					};
+
+				nand_clk: nand_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 10>;
+					fixed-divider = <4>;
+					};
+
+				qspi_clk: qspi_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+					clk-gate = <0xa0 11>;
+					};
 				};
 			};
 
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 16 15:05:16 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 16 May 2013 14:05:16 -0500
Subject: [PATCHv2 5/6] ARM: socfpga: dts: Add support for SD/MMC
In-Reply-To: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368731117-4749-5-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for SD/MMC for SOCFPGA.
Add "syscon" to the "altr,sys-mgr" binding.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Add "syscon" to "altr,sys-mgr"
- Remove pwr-en field
---
 .../devicetree/bindings/mmc/socfpga-dw-mshc.txt    |   60 ++++++++++++++++++++
 arch/arm/boot/dts/socfpga.dtsi                     |   13 ++++-
 arch/arm/boot/dts/socfpga_cyclone5.dts             |   13 +++++
 arch/arm/boot/dts/socfpga_vt.dts                   |   12 ++++
 4 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
new file mode 100644
index 0000000..9d7062c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
@@ -0,0 +1,60 @@
+* Altera SOCFPGA specific extensions to the Synopsis Designware Mobile
+  Storage Host Controller
+
+Required Properties:
+
+* compatible: should be
+	- "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA
+	  specific extentions.
+
+* altr,dw-mshc-ciu-div: Specifies the divider value for the card interface
+  unit (ciu) clock. The value should be (n-1). For Altera's SOCFPGA, the divider
+  value is fixed at 3, which mean parent_clock/4.
+
+* altr,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
+  in transmit mode and CIU clock phase shift value in receive mode for single
+  data rate mode operation. Refer notes below for the order of the cells and the
+  valid values.
+
+  Notes for the sdr-timing values:
+
+    The order of the cells should be
+      - First Cell: CIU clock phase shift value for RX mode, smplsel bits in
+	the system manager SDMMC control group.
+      - Second Cell: CIU clock phase shift value for TX mode, drvsel bits in
+	the system manager SDMMC control group.
+
+    Valid values for SDR CIU clock timing for SOCFPGA:
+      - valid value for tx phase shift and rx phase shift is 0 to 7.
+
+Required properties for a slot:
+
+* bus-width: Data width for card slot. 4-bit or 8-bit data.
+
+Example:
+
+  The MSHC controller node can be split into two portions, SoC specific and
+  board specific portions as listed below.
+
+	dwmmc0 at ff704000 {
+		compatible = "altr,socfpga-dw-mshc";
+		reg = <0xff704000 0x1000>;
+		interrupts = <0 139 4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc0 at ff704000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x400>;
+		altr,dw-mshc-ciu-div = <3>;
+      		altr,dw-mshc-sdr-timing = <0 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+		};
+	};
+
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index bee62a2..dbf7f22 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -468,6 +468,17 @@
 			cache-level = <2>;
 		};
 
+		mmc: dwmmc0 at ff704000 {
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0xff704000 0x1000>;
+			interrupts = <0 139 4>;
+			fifo-depth = <0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+			clock-names = "biu", "ciu";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
@@ -521,7 +532,7 @@
 			};
 
 		sysmgr at ffd08000 {
-				compatible = "altr,sys-mgr";
+				compatible = "altr,sys-mgr", "syscon";
 				reg = <0xffd08000 0x4000>;
 			};
 	};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 973999d..1853cb1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -54,6 +54,19 @@
 			status = "okay";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <3>;
+			altr,dw-mshc-sdr-timing = <0 3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0ca..d93deb0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -46,6 +46,18 @@
 			status = "okay";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 16 15:05:12 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 16 May 2013 14:05:12 -0500
Subject: [PATCHv2 1/6] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Message-ID: <1368731117-4749-1-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Moved "disabled" status to dtsi file
---
 arch/arm/boot/dts/socfpga.dtsi         |   18 ++++++++++++++++--
 arch/arm/boot/dts/socfpga_cyclone5.dts |   13 +++++++++++++
 arch/arm/boot/dts/socfpga_vt.dts       |    5 +++++
 3 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13..02bb425 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
 
 	aliases {
 		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		timer0 = &timer0;
@@ -238,13 +239,26 @@
 				};
 			};
 
-		gmac0: stmmac at ff700000 {
+		gmac0: ethernet at ff700000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff700000 0x2000>;
 			interrupts = <0 115 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			phy-mode = "gmii";
+			clocks = <&emac0_clk>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+		};
+
+		gmac1: ethernet at ff702000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+			reg = <0xff702000 0x2000>;
+			interrupts = <0 120 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+			clocks = <&emac1_clk>;
+			clock-names = "stmmaceth";
+			status = "disabled";
 		};
 
 		L2: l2-cache at fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958..973999d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
 	soc {
 		clkmgr at ffd04000 {
 			clocks {
@@ -41,6 +48,12 @@
 			};
 		};
 
+		ethernet at ff702000 {
+			phy-mode = "rgmii";
+			phy-addr = <0xffffffff>; /* probe for phy addr */
+			status = "okay";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d..d1ec0ca 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,11 @@
 			};
 		};
 
+		ethernet at ff700000 {
+			phy-mode = "gmii";
+			status = "okay";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 16 15:05:17 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 16 May 2013 14:05:17 -0500
Subject: [PATCHv2 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
Message-ID: <1368731117-4749-6-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add platform specific functionality for the DW SD/MMC driver for
SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
can use this define.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Seungwon Jeon <tgih.jun at samsung.com>
CC: Jaehoon Chung <jh80.chung at samsung.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: linux-mmc at vger.kernel.org

v2:
- Use syscon and regmap
- Avoid divide by zero
- Remove the need to set PWR_EN
---
 drivers/mmc/host/Kconfig          |    8 +++
 drivers/mmc/host/Makefile         |    1 +
 drivers/mmc/host/dw_mmc-exynos.c  |    2 -
 drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h         |    1 +
 5 files changed, 149 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9ab8f8d..1be2289 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Exynos4 and Exynos5 SoC's.
 
+config MMC_DW_SOCFPGA
+	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
+	depends on MMC_DW
+	select MMC_DW_PLTFM
+	help
+	  This selects support for Altera SoCFPGA specific extensions to the
+	  Synopsys DesignWare Memory Card Interface driver.
+
 config MMC_DW_PCI
 	tristate "Synopsys Designware MCI support on PCI bus"
 	depends on MMC_DW && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cd32280..67718c1 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
 obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
 obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
 obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
+obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
 obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
 obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..866edef 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -31,8 +31,6 @@
 					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
 					SDMMC_CLKSEL_CCLK_DIVIDER(z))
 
-#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
-
 #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
 
diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
new file mode 100644
index 0000000..af89685
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -0,0 +1,139 @@
+/*
+ * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
+ *
+ *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Taken from dw_mmc_exynos.c
+ */
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
+#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
+	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+extern void __iomem *sys_manager_base_addr;
+
+/* SOCFPGA implementation specific driver private data */
+struct dw_mci_socfpga_priv_data {
+	u8	ciu_div;
+	u32	hs_timing;
+	struct regmap   *sysreg;
+};
+
+static int dw_mci_socfpga_priv_init(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv;
+	struct device *dev = host->dev;
+
+	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(host->dev, "mem alloc failed for private data\n");
+		return -ENOMEM;
+	}
+
+	host->priv = priv;
+	return 0;
+}
+
+static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	clk_disable(host->ciu_clk);
+	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
+	clk_enable(host->ciu_clk);
+
+	host->bus_hz /= (priv->ciu_div + 1);
+	return 0;
+}
+
+static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
+		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+	struct device_node *np = host->dev->of_node;
+	u32 timing[2];
+	u32 div = 0;
+	int ret;
+
+	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+	if (IS_ERR(priv->sysreg)) {
+		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+		return PTR_ERR(priv->sysreg);
+	}
+
+	of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
+	priv->ciu_div = div;
+
+	ret = of_property_read_u32_array(np,
+			"altr,dw-mshc-sdr-timing", timing, 2);
+	if (ret)
+		return ret;
+
+	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+	return 0;
+}
+
+static const struct dw_mci_drv_data socfpga_drv_data = {
+	.init			= dw_mci_socfpga_priv_init,
+	.setup_clock		= dw_mci_socfpga_setup_clock,
+	.prepare_command	= dw_mci_socfpga_prepare_command,
+	.parse_dt		= dw_mci_socfpga_parse_dt,
+};
+
+static const struct of_device_id dw_mci_socfpga_match[] = {
+	{ .compatible = "altr,socfpga-dw-mshc",
+			.data = &socfpga_drv_data, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
+
+int dw_mci_socfpga_probe(struct platform_device *pdev)
+{
+	const struct dw_mci_drv_data *drv_data;
+	const struct of_device_id *match;
+
+	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
+	drv_data = match->data;
+	return dw_mci_pltfm_register(pdev, drv_data);
+}
+
+static struct platform_driver dw_mci_socfpga_pltfm_driver = {
+	.probe		= dw_mci_socfpga_probe,
+	.remove		= __exit_p(dw_mci_pltfm_remove),
+	.driver		= {
+		.name		= "dwmmc_socfpga",
+		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
+		.pm		= &dw_mci_pltfm_pmops,
+	},
+};
+
+module_platform_driver(dw_mci_socfpga_pltfm_driver);
+
+MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:dwmmc-socfpga");
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0b74189..3700cb2 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
-- 
1.7.9.5




From mturquette at linaro.org  Thu May 16 15:17:23 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 16 May 2013 12:17:23 -0700
Subject: [PATCH 5/6] clk: tegra114: implement wait_for_reset and
 disable_clock for tegra_cpu_car_ops
In-Reply-To: <1368613644-11863-6-git-send-email-josephl@nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <1368613644-11863-6-git-send-email-josephl@nvidia.com>
Message-ID: <20130516191723.12127.40116@quantum>

Quoting Joseph Lo (2013-05-15 03:27:23)
> The conventional CPU hotplug sequence on the other Tegra chips, we will also
> clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
> Tegra114, the flow controller will clock gate the CPU after the power down
> sequence. But we still need to implement a empty function for disable_clock
> to avoid kernel warning message.
> 
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Joseph Lo <josephl at nvidia.com>

Acked-by: Mike Turquette <mturquette at linaro.org>

> ---
>  drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index d78e16e..40d939d 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -250,6 +250,9 @@
>  #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
>  #define CLK_SOURCE_EMC 0x19c
>  
> +/* Tegra CPU clock and reset control regs */
> +#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS    0x470
> +
>  static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
>  
>  static void __iomem *clk_base;
> @@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
>         }
>  }
>  
> -static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
> +/* Tegra114 CPU clock and reset control functions */
> +static void tegra114_wait_cpu_in_reset(u32 cpu)
> +{
> +       unsigned int reg;
> +
> +       do {
> +               reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
> +               cpu_relax();
> +       } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
> +}
> +static void tegra114_disable_cpu_clock(u32 cpu)
> +{
> +       /* flow controller would take care in the power sequence. */
> +}
> +
> +static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
> +       .wait_for_reset = tegra114_wait_cpu_in_reset,
> +       .disable_clock  = tegra114_disable_cpu_clock,
> +};
>  
>  static const struct of_device_id pmc_match[] __initconst = {
>         { .compatible = "nvidia,tegra114-pmc" },
> -- 
> 1.8.2.2


From skannan at codeaurora.org  Thu May 16 15:23:12 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Thu, 16 May 2013 12:23:12 -0700
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing
 is done
In-Reply-To: <CAPDyKFqyvfuttH=rGLxBCemgRMq4N3fVktom+RB2wm72NruaDA@mail.gmail.com>
References: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
 <519461BB.3010209@codeaurora.org>
 <CAPDyKFqyvfuttH=rGLxBCemgRMq4N3fVktom+RB2wm72NruaDA@mail.gmail.com>
Message-ID: <51953220.6060207@codeaurora.org>

On 05/16/2013 05:55 AM, Ulf Hansson wrote:
> On 16 May 2013 06:34, Saravana Kannan <skannan at codeaurora.org> wrote:
>> On 05/09/2013 11:35 AM, Saravana Kannan wrote:
>>>
>>> With deferred probing, late_initcall() is too soon to declare a clock as
>>> unused. Wait for deferred probing to finish before declaring a clock as
>>> unused. Since deferred probing is done in late_initcall(), do the unused
>>> check to late_initcall_sync.
>>>
>>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>>> ---
>>>    drivers/clk/clk.c |    2 +-
>>>    1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>>> index fe4055f..5ecb64c 100644
>>> --- a/drivers/clk/clk.c
>>> +++ b/drivers/clk/clk.c
>>> @@ -534,7 +534,7 @@ static int clk_disable_unused(void)
>>>
>>>          return 0;
>>>    }
>>> -late_initcall(clk_disable_unused);
>>> +late_initcall_sync(clk_disable_unused);
>
> Without giving this too much thinking... Will boot time be affected
> with this change?
>

No, we are just reordering the steps.

-Saravana


-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From linux at arm.linux.org.uk  Thu May 16 15:25:10 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 May 2013 20:25:10 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
Message-ID: <20130516192510.GV18614@n2100.arm.linux.org.uk>

What follows is my DRM driver for Dove, which I've been working on with
the Solid-run Cubox, which only offers HDMI output via the TDA19988
chip.

Not everything is finished off perfectly in this driver; there's quite
a number of ragged edges (particularly with page flipping, which is
completely untested.)

I have most of the Xorg driver complete - none of the DRI interfaces
checked yet (partly because that involves quite an amount of work with
Mesa).

However, graphics, video overlay, interlacing, accelerated GPU via the
original vivante support all works through this driver, with this driver
providing the X pixmaps.


From alexandre.belloni at free-electrons.com  Thu May 16 15:33:57 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Thu, 16 May 2013 21:33:57 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <1368713639-21485-2-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>
 <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
Message-ID: <519534A5.2070209@free-electrons.com>

Hi Fabio,

On 16/05/2013 19:25, Fabio Estevam wrote:
> Sorry, the original patch is correct.
>
> i2c slowness is a different issue.

Would that be related to the timeouts I'm observing ?

http://www.spinics.net/lists/linux-i2c/msg11985.html

I didn't have the time to have a look at it yet. I was planning to hook
up a logic analyzer someday in june to debug it. It seems that there is
a 1 second timeout with each i2c message that are sent.

Don't hesitate to contact me if you need more info.

Regards,

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From robert.jarzmik at free.fr  Thu May 16 15:39:00 2013
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Thu, 16 May 2013 21:39:00 +0200
Subject: GPIO sysfs : set a wake source
In-Reply-To: <51926177.1050600@wwwdotorg.org> (Stephen Warren's message of
 "Tue, 14 May 2013 10:08:23 -0600")
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
 <51926177.1050600@wwwdotorg.org>
Message-ID: <87ip2ig1ez.fsf@free.fr>

Stephen Warren <swarren at wwwdotorg.org> writes:

> On 05/14/2013 03:29 AM, Linus Walleij wrote:
>> On Thu, May 9, 2013 at 2:59 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
>> 
>>> I was thinking on how to remove all "gpio_request()" from my board code
>>> (arch/arm/mach-pxa/mioa701.c).
>>>
>>> I have a small difficulty with the functionality provided by gpiolib in
>>> userspace. This is what I need :
>>>  - define a gpio as an input
>>>  - define this gpio to be an interrupt source
>>>  - define this interrupt to be a wake-up source
>> 
>> This sounds like trying to remove board code by moving it to userspace
>> and basically starting to implement stuff that belongs in the kernel
>> in userspace just because someone says we should get rid of board
>> files :-)
No, really, even it's true that it comes from someone asking me, now I have
though it a bit more through.

>> Don't go down this path, let the kernel handle this kind of stuff.
Oh really, where ?

Let me show you why it can't be a module.
In my case, I have a 2G modem connected to the soc :
 - the modem and 1 SoC UART are connected (TX, RX, CTS, ...)
 - the modem and SoC are connected through several gpios
   - one or two control to power up and reset the modem
   - one connected to the modem "ring" signal (the one I want a wakeup for).

So I have no module to handle my modem :
 - UART is handled by pxa-uart
 - control/reset by gpiolib
 - ring ... by nobody

So my point is that this ring *should* be handled by gpiolib, just as any casual
input gpio. Moreover, the "wake-up" ability should be activable/deactivable on
wish by userspace.

>> Instead figure out how to make the subsystems we have and the
>> device trees express what you want to do.
As I said above, I don't think it's the way to go. I have *no* subsystem to
address.
Devicetree can't help in the toggle to "activate" or "deactivate" the wakeup
upon this GPIO, can it ?

>> 
>> In another thread I suggested that we add a GPIO "hogging"
>> mechanism to gpiolib, so that the gpio subsystem can by itself
>> "hog" (get) some GPIOs and set them up in certain modes.
>> This closely matches what the pin control subsystem will do
>> with some such things.
>> 
>> What do you think about this idea?
I don't yet know. Let me think this more over. I'd like some literature if you
can provide (especially on LAKML).

> There's some merit to discussing the use of "GPIO hogging" for the
> purpose of solving interactions between the IRQ and GPIO subsystems
>
> However, the discussion above sounds like simply a list of GPIOs to
> initialize at boot for the sole purpose of GPIO initialization. I
> thought that had been discussed before and nak'd?
Now I have described a bit more the problem, I think this sentence would need to
be amended :)

Cheers.

-- 
Robert


From mturquette at linaro.org  Thu May 16 15:46:32 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 16 May 2013 12:46:32 -0700
Subject: [PATCH V5 1/6] clk: OMAP: introduce device tree binding to kernel
 clock data
In-Reply-To: <20130516174355.GB5600@atomide.com>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
 <1368039976-29648-2-git-send-email-nm@ti.com>
 <20130513235119.10068.47040@quantum> <20130516174355.GB5600@atomide.com>
Message-ID: <20130516194632.12127.59935@quantum>

Quoting Tony Lindgren (2013-05-16 10:43:56)
> * Mike Turquette <mturquette at linaro.org> [130513 16:56]:
> > Quoting Nishanth Menon (2013-05-08 12:06:11)
> > <snip>
> > > Overall strategy introduced here is simple: a clock node described in
> > > device tree blob is used to identify the exact clock provided in the
> > > SoC specific data. This is then linked back using of_clk_add_provider
> > > to the device node to be accessible by of_clk_get.
> > > 
> > 
> > FYI, I'm working on moving the OMAP clocks over to DT which is a better
> > alternative than this patch.  I'll share what I have on the list,
> > hopefully next week.
> 
> That's good news! What's your plan on using the indexing the clocks?
> 
> I'd rather avoid indexing as that's basically same as the old IRQ
> numbering and GPIO numbering schemes that don't work well in the long
> term.
> 
> We already have quite a few sets of clocks for omaps, so the indexing
> is already an issue. My thinking is that indexing should only be used
> if the same physical clock has multiple outputs.
> 

At present I am actually describing the clock hardware in DT.  Each
clock is a node (not a device) using the established clock binding in
Documentation/devicetree/bindings/clocks/clock-bindings.txt.

To do this I am introducing new bindings for the common types: gate, mux
& divider.  These are the ones I am migrating to DT first.  Eventually
I'll create bindings for the OMAP-specifc clocks after this.

I currently have this DT approach co-existing with the static data.  As
a start I have used the fixed-clock and mux-clock bindings to put all of
the root clocks and sys_clk into arch/arm/boot/dts/omap4-clocks.dtsi.
This file is included by arch/arm/boot/dts/omap4.dtsi.

The DT clocks are parsed prior to the static clock registration:

diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a4..7cc4cae 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -27,6 +27,7 @@
 #include <linux/clk-private.h>
 #include <linux/clkdev.h>
 #include <linux/io.h>
+#include <linux/clk/omap.h>
 
 #include "soc.h"
 #include "iomap.h"
@@ -1442,27 +1443,11 @@ static struct omap_clk omap443x_clks[] = {
  * clocks common to omap44xx
  */
 static struct omap_clk omap44xx_clks[] = {
-	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
 	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
 	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
-	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
-	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
 	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
 	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
 	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
-	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
-	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
-	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
-	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
-	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
-	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
-	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
-	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
-	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
-	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
-	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
-	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
-	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
 	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
 	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
 	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
@@ -1690,6 +1675,9 @@ int __init omap4xxx_clk_init(void)
 {
 	int rc;
 
+	/* FIXME register clocks from DT first */
+	dt_omap_clk_init();
+
 	if (cpu_is_omap443x()) {
 		cpu_mask = RATE_IN_4430;
 		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));


Ideally dt_omap_clk_init() will go away and instead by replaced by the
probe from drivers/clk/omap/clk.c (new omap clock driver).  However I
still need to register the root clocks before the PLLs and other
dividers for now to avoid many issues (divide by zero errors, failed
reparent operations, etc).  And furthermore I don't think the hwmod code
will work if the clock tree is not populated before module_init.  So for
now the omap clock driver does not properly probe or call module_init,
but some day that might be fixed.

I know that putting all of the data into DT is not a popular idea with
everybody.  I also know that I am not a DT expert, so I'm sure there are
some better approaches to the some of the decisions I'm making.  I'll
post an RFC to the list next week with cleaned-up patches and then we
can all take it from there.

Regards,
Mike

> Regards,
> 
> Tony


From swarren at wwwdotorg.org  Thu May 16 15:49:20 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 13:49:20 -0600
Subject: GPIO sysfs : set a wake source
In-Reply-To: <87ip2ig1ez.fsf@free.fr>
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
 <51926177.1050600@wwwdotorg.org> <87ip2ig1ez.fsf@free.fr>
Message-ID: <51953840.9050106@wwwdotorg.org>

On 05/16/2013 01:39 PM, Robert Jarzmik wrote:
> Stephen Warren <swarren at wwwdotorg.org> writes:
> 
>> On 05/14/2013 03:29 AM, Linus Walleij wrote:
>>> On Thu, May 9, 2013 at 2:59 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
>>>
>>>> I was thinking on how to remove all "gpio_request()" from my board code
>>>> (arch/arm/mach-pxa/mioa701.c).
>>>>
>>>> I have a small difficulty with the functionality provided by gpiolib in
>>>> userspace. This is what I need :
>>>>  - define a gpio as an input
>>>>  - define this gpio to be an interrupt source
>>>>  - define this interrupt to be a wake-up source
>>>
>>> This sounds like trying to remove board code by moving it to userspace
>>> and basically starting to implement stuff that belongs in the kernel
>>> in userspace just because someone says we should get rid of board
>>> files :-)
> No, really, even it's true that it comes from someone asking me, now I have
> though it a bit more through.
> 
>>> Don't go down this path, let the kernel handle this kind of stuff.
> Oh really, where ?
> 
> Let me show you why it can't be a module.
> In my case, I have a 2G modem connected to the soc :
>  - the modem and 1 SoC UART are connected (TX, RX, CTS, ...)
>  - the modem and SoC are connected through several gpios
>    - one or two control to power up and reset the modem
>    - one connected to the modem "ring" signal (the one I want a wakeup for).
> 
> So I have no module to handle my modem :
>  - UART is handled by pxa-uart
>  - control/reset by gpiolib
>  - ring ... by nobody
> 
> So my point is that this ring *should* be handled by gpiolib, just as any casual
> input gpio. Moreover, the "wake-up" ability should be activable/deactivable on
> wish by userspace.
> 
>>> Instead figure out how to make the subsystems we have and the
>>> device trees express what you want to do.
>
> As I said above, I don't think it's the way to go. I have *no* subsystem to
> address.
> Devicetree can't help in the toggle to "activate" or "deactivate" the wakeup
> upon this GPIO, can it ?

This sounds very similar to WiFi rfkill, although it's a MODEM not WiFi.



From david.lanzendoerfer at o2s.ch  Thu May 16 15:50:49 2013
From: david.lanzendoerfer at o2s.ch (David =?iso-8859-1?Q?Lanzend=F6rfer?=)
Date: Thu, 16 May 2013 21:50:49 +0200
Subject: Naming convention DSI + device tree
In-Reply-To: <519522C1.5010107@wwwdotorg.org>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org>
 <20130516071537.GA13573@mail.o2s.ch>
 <519522C1.5010107@wwwdotorg.org>
Message-ID: <20130516195049.GA17092@mail.o2s.ch>

> No, we haven't yet posted DSI support upstream.
Ok.

> Honestly, I'm not sure. I assume (and it is just an assumption) that
> if you look at the CDF patches, you should find some examples of panel
> drivers that use it, although perhaps there aren't any yet...
Ok. If there's an API already flying around somewhere, which will
be posted to upstream at some point of time, and won't change drastically
anymore I can work with it. 

> No. That branch of mine is basd on linux-next, so whatever is in
> linux-next is in my branch, and I certainly haven't applied the CDF
> locally.
Ok.

> I believe the CDF has been posted to various mailing lists a few
> times, but it isn't checked in yet since there isn't a final version.
> I CC'd Alex; he might know the status better than me.
Ok. Thank you very much!
The best would be a patchset for CDF against linux-next (which will most
likely be the case anyway) in order to track the changes and post my own
changes upstream as soon as CDF is in next.
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From tony at atomide.com  Thu May 16 16:02:38 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 13:02:38 -0700
Subject: [PATCH V5 1/6] clk: OMAP: introduce device tree binding to
 kernel clock data
In-Reply-To: <20130516194632.12127.59935@quantum>
References: <1368039976-29648-1-git-send-email-nm@ti.com>
 <1368039976-29648-2-git-send-email-nm@ti.com>
 <20130513235119.10068.47040@quantum>
 <20130516174355.GB5600@atomide.com>
 <20130516194632.12127.59935@quantum>
Message-ID: <20130516200237.GL5600@atomide.com>

* Mike Turquette <mturquette at linaro.org> [130516 12:52]:
> Quoting Tony Lindgren (2013-05-16 10:43:56)
> > * Mike Turquette <mturquette at linaro.org> [130513 16:56]:
> > > Quoting Nishanth Menon (2013-05-08 12:06:11)
> > > <snip>
> > > > Overall strategy introduced here is simple: a clock node described in
> > > > device tree blob is used to identify the exact clock provided in the
> > > > SoC specific data. This is then linked back using of_clk_add_provider
> > > > to the device node to be accessible by of_clk_get.
> > > > 
> > > 
> > > FYI, I'm working on moving the OMAP clocks over to DT which is a better
> > > alternative than this patch.  I'll share what I have on the list,
> > > hopefully next week.
> > 
> > That's good news! What's your plan on using the indexing the clocks?
> > 
> > I'd rather avoid indexing as that's basically same as the old IRQ
> > numbering and GPIO numbering schemes that don't work well in the long
> > term.
> > 
> > We already have quite a few sets of clocks for omaps, so the indexing
> > is already an issue. My thinking is that indexing should only be used
> > if the same physical clock has multiple outputs.
> > 
> 
> At present I am actually describing the clock hardware in DT.  Each
> clock is a node (not a device) using the established clock binding in
> Documentation/devicetree/bindings/clocks/clock-bindings.txt.
> 
> To do this I am introducing new bindings for the common types: gate, mux
> & divider.  These are the ones I am migrating to DT first.  Eventually
> I'll create bindings for the OMAP-specifc clocks after this.

Great, that's the way to go.
 
> I currently have this DT approach co-existing with the static data.  As
> a start I have used the fixed-clock and mux-clock bindings to put all of
> the root clocks and sys_clk into arch/arm/boot/dts/omap4-clocks.dtsi.
> This file is included by arch/arm/boot/dts/omap4.dtsi.

OK.

> The DT clocks are parsed prior to the static clock registration:
> 
> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> index 88e37a4..7cc4cae 100644
> --- a/arch/arm/mach-omap2/cclock44xx_data.c
> +++ b/arch/arm/mach-omap2/cclock44xx_data.c
> @@ -27,6 +27,7 @@
>  #include <linux/clk-private.h>
>  #include <linux/clkdev.h>
>  #include <linux/io.h>
> +#include <linux/clk/omap.h>
>  
>  #include "soc.h"
>  #include "iomap.h"
> @@ -1442,27 +1443,11 @@ static struct omap_clk omap443x_clks[] = {
>   * clocks common to omap44xx
>   */
>  static struct omap_clk omap44xx_clks[] = {
> -	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
>  	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
>  	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
> -	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
> -	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
>  	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
>  	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
>  	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
> -	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
> -	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
> -	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
> -	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
> -	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
> -	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
> -	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
> -	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
> -	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
> -	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
> -	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
> -	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
> -	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
>  	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
>  	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
>  	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
> @@ -1690,6 +1675,9 @@ int __init omap4xxx_clk_init(void)
>  {
>  	int rc;
>  
> +	/* FIXME register clocks from DT first */
> +	dt_omap_clk_init();
> +
>  	if (cpu_is_omap443x()) {
>  		cpu_mask = RATE_IN_4430;
>  		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
> 
> 
> Ideally dt_omap_clk_init() will go away and instead by replaced by the
> probe from drivers/clk/omap/clk.c (new omap clock driver).  However I
> still need to register the root clocks before the PLLs and other
> dividers for now to avoid many issues (divide by zero errors, failed
> reparent operations, etc).  And furthermore I don't think the hwmod code
> will work if the clock tree is not populated before module_init.  So for
> now the omap clock driver does not properly probe or call module_init,
> but some day that might be fixed.

Yes, I'm sure there are some dependencies to untangle there..
 
> I know that putting all of the data into DT is not a popular idea with
> everybody.  I also know that I am not a DT expert, so I'm sure there are
> some better approaches to the some of the decisions I'm making.  I'll
> post an RFC to the list next week with cleaned-up patches and then we
> can all take it from there.

The DT related bloat issues can be avoided with the following:

1. Allow defining all clocks as needed in the .dtsi files

   This way we have the clocks available for timer, uart, mmc and
   whatever people might need.

2. Optionally allow loading the complete clock set from /lib/firmware

   This way we can avoid large amount of data in the .dtsi files
   to make booting faster. Naturally this is optional, and not needed
   if all the clocks are already defined in .dtsi files. And this can
   of course done later on if needed as long as we just keep that
   option open.

Regards,

Tony


From mturquette at linaro.org  Thu May 16 16:13:35 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 16 May 2013 13:13:35 -0700
Subject: [PATCH v2] clk: si5351: declare all device IDs for module loading
In-Reply-To: <20130516174916.2daa49b6@armhf>
References: <20130516174916.2daa49b6@armhf>
Message-ID: <20130516201335.12127.99310@quantum>

Quoting Jean-Francois Moine (2013-05-16 08:49:16)
> When the si5351 driver is a kernel module, it is loaded into memory
> from its i2c device IDs, but not from its DT compatible properties.
> 
> This patch declares the i2c device IDs of all chip variants.
> 
> Signed-off-by: Jean-Francois Moine <moinejf at free.fr>

Taken into clk-next.

Thanks,
Mike

> ---
> v2: subject change - was "ARM: dove: ..."
> --- 
>  drivers/clk/clk-si5351.c |    5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index 8927284..9ebdddd 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -1490,7 +1490,10 @@ static int si5351_i2c_probe(struct i2c_client *client,
>  }
>  
>  static const struct i2c_device_id si5351_i2c_ids[] = {
> -       { "silabs,si5351", 0 },
> +       { "si5351a", 0 },
> +       { "si5351a-msop", 0 },
> +       { "si5351b", 0 },
> +       { "si5351c", 0 },
>         { }
>  };
>  MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
> 
> 
> -- 
> Ken ar c'henta? |             ** Breizh ha Linux atav! **
> Jef             |               http://moinejf.free.fr/
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From jason at lakedaemon.net  Thu May 16 16:18:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 May 2013 16:18:27 -0400
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
In-Reply-To: <20130516161201.GI6563@titan.lakedaemon.net>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-8-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130516093312.GB2459@localhost>
 <20130516154031.GF6563@titan.lakedaemon.net>
 <20130516174903.3a7a07ef@skate>
 <20130516155617.GH6563@titan.lakedaemon.net>
 <20130516180850.3622e1a8@skate>
 <20130516161201.GI6563@titan.lakedaemon.net>
Message-ID: <20130516201827.GA11137@titan.lakedaemon.net>

On Thu, May 16, 2013 at 12:12:02PM -0400, Jason Cooper wrote:
> On Thu, May 16, 2013 at 06:08:50PM +0200, Thomas Petazzoni wrote:
> > Dear Jason Cooper,
> > 
> > On Thu, 16 May 2013 11:56:17 -0400, Jason Cooper wrote:
> > 
> > > > > > Building this showed a warning here. It seems you forgot
> > > > > > to mark this one as __init.
> > > > > 
> > > > > Thomas, I'll fix this up when I pull this in, no need to resend. :)
> > > > 
> > > > I'll resend, because beyond this function pointed by Ezequiel, there
> > > > are two other functions that can be marked __init. The one pointed by
> > > > Ezequiel is important because it causes a section mismatch
> > > > when !CONFIG_MODULES, because in this case platform_driver_probe() is
> > > > __init (and this explains what I wasn't seeing the warning, since I'm
> > > > building CONFIG_MODULES=y). The two other functions are more cosmetic,
> > > > but good to have as well.
> > > > 
> > > > It would already been sent if git hadn't decided to do a 'git gc' right
> > > > after my rebase. It's been gc-ing for quite some time now...
> > > 
> > > Dear boss,
> > > 
> > > I am in desperate need of a 500GB SSD on which to do my kernel work.
> > > 
> > > Thanks,
> > > 
> > > Kranky Kernel Developer
> > > 
> > > hehehe...
> > 
> > Adding boss in the Cc list :-)
> 
> Hey, whatever works for you.  Good luck!

Ok, you motivated me, I just ordered this one:

http://www.amazon.com/Crucial-512GB-2-5-Inch-9-5mm-CT512M4SSD2/dp/B004W2JL3Y

I'd've gone with Intel, but it ships in 2 to 5 weeks, and it costs 20%
more with comparable capacity.

thx,

Jason.


From robherring2 at gmail.com  Thu May 16 16:18:53 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 May 2013 15:18:53 -0500
Subject: [PATCH] ARM: prima2: return rather than panic on missing DT nodes
In-Reply-To: <519510A4.8090904@st.com>
References: <1368719437-28287-1-git-send-email-robherring2@gmail.com>
 <519510A4.8090904@st.com>
Message-ID: <CAL_JsqL_z99EfT=3E32c0AS6fbwqOyTb7n+AzySmzJNyMCab3w@mail.gmail.com>

On Thu, May 16, 2013 at 12:00 PM, Srinivas KANDAGATLA
<srinivas.kandagatla at st.com> wrote:
> Hi Rob,
>
> I was just testing multi_v7_defconfig and noticed that the code is still
> doing early_initcall and postcore_initcalls. Which IMO is NOK for
> multiplatforms.
>
> I was just about to send my patch and just noticed your patch.
>
>
> On 16/05/13 16:50, Rob Herring wrote:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> Missing nodes is a normal condition in multi-platform kernels when we boot
>> on other platforms. So remove the panic and just return if we don't find
>> a DT node.
>>
>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>> Cc: Barry Song <baohua.song at csr.com>
>> ---
>>  arch/arm/mach-prima2/pm.c   | 2 +-
>>  arch/arm/mach-prima2/rstc.c | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
>> index 9936c18..a8003e2 100644
>> --- a/arch/arm/mach-prima2/pm.c
>> +++ b/arch/arm/mach-prima2/pm.c
>> @@ -102,7 +102,7 @@ static int __init sirfsoc_of_pwrc_init(void)
>>
> First thing is the mach code should not even attempt to run this
> function in first place.
>
> I think the correct fix for this is to move all the postcore_initcalls
> and early_initcalls to callbacks in MACHINE.

Agreed, but that may cause some init ordering issues. So I'll leave
that to someone that knows this platform and can test it.

Rob


From dmurphy at ti.com  Thu May 16 16:22:51 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Thu, 16 May 2013 15:22:51 -0500
Subject: [PATCH v4] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <CAGo_u6pX+DdVNWqdPXDChzMr27YAXL_Zvt7DxWBijOCW0rXpkA@mail.gmail.com>
References: <1368636386-17138-1-git-send-email-dmurphy@ti.com>
 <20130515170516.GA6135@kahuna> <5194FCDD.8080209@ti.com>
 <CAGo_u6pX+DdVNWqdPXDChzMr27YAXL_Zvt7DxWBijOCW0rXpkA@mail.gmail.com>
Message-ID: <5195401B.5070209@ti.com>

On 05/16/2013 01:18 PM, Nishanth Menon wrote:
> On Thu, May 16, 2013 at 10:35 AM, Dan Murphy <dmurphy at ti.com> wrote:
>> I am not sure you really want to do this.
>> If I make the pinctrl part of the led structure then the only way the gpio_wk7 on a1-a3 to be configured is when
>> the CONFIG_LEDS_GPIO flag is set.
>>
>> Do you really want that dependency?  You did say it was a key fix
>> At least this way the pins are configured regardless of that flag.
> That is better as the system will be left in the pinmux configuration
> handed over from bootloader.
So you want to depend on a boot loader to configure pins correctly for the kernel?
Hmmm seems risky to me.
> The point being, muxing up pins even when not needed(config switched
> off) has no real benefit - in this case albeit, the default mux was
> causing a bug.
> pinctrl IMHO should be considered as any other resource, if it is not
> mandatory for boot, and needed only for a device functionality when
> probed, it should done there only.
>
> just my 2 cents.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
------------------
Dan Murphy



From linux at arm.linux.org.uk  Thu May 16 16:29:21 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 May 2013 21:29:21 +0100
Subject: [PATCH 0/9] Fix Marvell mv63xxx I2C driver
Message-ID: <20130516202921.GW18614@n2100.arm.linux.org.uk>

This patch series fixes a whole chunk of problems with this driver,
discovered with the Marvell Armada 510 chip on the Solid-run cubox.

Most notable of these is the I2C driver aborting a transaction
because a signal is pending - which might be SIGPIPE or SIGALRM
for the process.  Meanwhile, the calling driver may be in the
middle of a critical read-modify-write cycle on a device register,
causing it to fail.

Other problems are race conditions in the handling of multi-part
messages, where we end up sending multiple start conditions -
sometimes more times than we have i2c_msg's to send.

Lastly is the rather poor probe error handling, which ranges from
non-existent to lacking propagating the provided error code.


From rmk+kernel at arm.linux.org.uk  Thu May 16 16:30:59 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:30:59 +0100
Subject: [PATCH 1/9] I2C: mv64xxx: work around signals causing I2C
 transactions to be aborted
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>

Do not use interruptible waits in an I2C driver; if a process uses
signals (eg, Xorg uses SIGALRM and SIGPIPE) then these signals can
cause the I2C driver to abort a transaction in progress by another
driver, which can cause that driver to fail.  I2C drivers are not
expected to abort transactions on signals.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 8b20ef8..8d4c0a0 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -252,7 +252,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 		writel(drv_data->cntl_bits,
 			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
 		drv_data->block = 0;
-		wake_up_interruptible(&drv_data->waitq);
+		wake_up(&drv_data->waitq);
 		break;
 
 	case MV64XXX_I2C_ACTION_CONTINUE:
@@ -300,7 +300,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
 		drv_data->block = 0;
-		wake_up_interruptible(&drv_data->waitq);
+		wake_up(&drv_data->waitq);
 		break;
 
 	case MV64XXX_I2C_ACTION_INVALID:
@@ -315,7 +315,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
 		drv_data->block = 0;
-		wake_up_interruptible(&drv_data->waitq);
+		wake_up(&drv_data->waitq);
 		break;
 	}
 }
@@ -381,7 +381,7 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
 	unsigned long	flags;
 	char		abort = 0;
 
-	time_left = wait_event_interruptible_timeout(drv_data->waitq,
+	time_left = wait_event_timeout(drv_data->waitq,
 		!drv_data->block, drv_data->adapter.timeout);
 
 	spin_lock_irqsave(&drv_data->lock, flags);
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:32:08 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:32:08 +0100
Subject: [PATCH 2/9] I2C: mv64xxx: use return value from mv64xxx_i2c_map_regs()
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4qO-0004JW-U7@rmk-PC.arm.linux.org.uk>

mv64xxx_i2c_map_regs() already returns an error code, so lets
propagate that to mv64xxx_i2c_probe()'s caller.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 8d4c0a0..0339cd8 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -619,10 +619,9 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 	if (!drv_data)
 		return -ENOMEM;
 
-	if (mv64xxx_i2c_map_regs(pd, drv_data)) {
-		rc = -ENODEV;
+	rc = mv64xxx_i2c_map_regs(pd, drv_data);
+	if (rc)
 		goto exit_kfree;
-	}
 
 	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
 		sizeof(drv_data->adapter.name));
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:33:09 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:33:09 +0100
Subject: [PATCH 3/9] I2C: mv64xxx: use devm_ioremap_resource()
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4rN-0004Jc-CL@rmk-PC.arm.linux.org.uk>

Eliminate reg_base_p and reg_size, mv64xxx_i2c_unmap_regs() and an
unchecked ioremap() return from this driver by using the devm_*
API for requesting and ioremapping resources.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |   46 +++++---------------------------------
 1 files changed, 6 insertions(+), 40 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 0339cd8..19cc9bf 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -92,8 +92,6 @@ struct mv64xxx_i2c_data {
 	u32			aborting;
 	u32			cntl_bits;
 	void __iomem		*reg_base;
-	u32			reg_base_p;
-	u32			reg_size;
 	u32			addr1;
 	u32			addr2;
 	u32			bytes_left;
@@ -495,40 +493,6 @@ static const struct i2c_algorithm mv64xxx_i2c_algo = {
  *
  *****************************************************************************
  */
-static int
-mv64xxx_i2c_map_regs(struct platform_device *pd,
-	struct mv64xxx_i2c_data *drv_data)
-{
-	int size;
-	struct resource	*r = platform_get_resource(pd, IORESOURCE_MEM, 0);
-
-	if (!r)
-		return -ENODEV;
-
-	size = resource_size(r);
-
-	if (!request_mem_region(r->start, size, drv_data->adapter.name))
-		return -EBUSY;
-
-	drv_data->reg_base = ioremap(r->start, size);
-	drv_data->reg_base_p = r->start;
-	drv_data->reg_size = size;
-
-	return 0;
-}
-
-static void
-mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
-{
-	if (drv_data->reg_base) {
-		iounmap(drv_data->reg_base);
-		release_mem_region(drv_data->reg_base_p, drv_data->reg_size);
-	}
-
-	drv_data->reg_base = NULL;
-	drv_data->reg_base_p = 0;
-}
-
 #ifdef CONFIG_OF
 static int
 mv64xxx_calc_freq(const int tclk, const int n, const int m)
@@ -610,6 +574,7 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 {
 	struct mv64xxx_i2c_data		*drv_data;
 	struct mv64xxx_i2c_pdata	*pdata = pd->dev.platform_data;
+	struct resource	*r;
 	int	rc;
 
 	if ((!pdata && !pd->dev.of_node))
@@ -619,9 +584,12 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 	if (!drv_data)
 		return -ENOMEM;
 
-	rc = mv64xxx_i2c_map_regs(pd, drv_data);
-	if (rc)
+	r = platform_get_resource(pd, IORESOURCE_MEM, 0);
+	drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
+	if (IS_ERR(drv_data->reg_base)) {
+		rc = PTR_ERR(drv_data->reg_base);
 		goto exit_kfree;
+	}
 
 	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
 		sizeof(drv_data->adapter.name));
@@ -690,7 +658,6 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 		clk_unprepare(drv_data->clk);
 	}
 #endif
-		mv64xxx_i2c_unmap_regs(drv_data);
 	exit_kfree:
 		kfree(drv_data);
 	return rc;
@@ -704,7 +671,6 @@ mv64xxx_i2c_remove(struct platform_device *dev)
 
 	rc = i2c_del_adapter(&drv_data->adapter);
 	free_irq(drv_data->irq, drv_data);
-	mv64xxx_i2c_unmap_regs(drv_data);
 #if defined(CONFIG_HAVE_CLK)
 	/* Not all platforms have a clk */
 	if (!IS_ERR(drv_data->clk)) {
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:34:10 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:34:10 +0100
Subject: [PATCH 4/9] I2C: mv64xxx: use devm_clk_get() to avoid missing
 clk_put()
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4sM-0004Ji-3h@rmk-PC.arm.linux.org.uk>

This driver forgets to use clk_put().  Rather than adding clk_put(),
lets instead use devm_clk_get() to obtain this clock so that it's
automatically handled on cleanup.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 19cc9bf..0b4da77 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -599,7 +599,7 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 
 #if defined(CONFIG_HAVE_CLK)
 	/* Not all platforms have a clk */
-	drv_data->clk = clk_get(&pd->dev, NULL);
+	drv_data->clk = devm_clk_get(&pd->dev, NULL);
 	if (!IS_ERR(drv_data->clk)) {
 		clk_prepare(drv_data->clk);
 		clk_enable(drv_data->clk);
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:35:10 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:35:10 +0100
Subject: [PATCH 5/9] I2C: mv64xxx: use devm_kzalloc()
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4tK-0004Jo-Ik@rmk-PC.arm.linux.org.uk>

As we're changing to using devm_* APIs to fix various problems
in this driver, lets also do devm_kzalloc() while we're here too.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |   24 ++++++++++--------------
 1 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 0b4da77..841792f 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -580,16 +580,15 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 	if ((!pdata && !pd->dev.of_node))
 		return -ENODEV;
 
-	drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
+	drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
+				GFP_KERNEL);
 	if (!drv_data)
 		return -ENOMEM;
 
 	r = platform_get_resource(pd, IORESOURCE_MEM, 0);
 	drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
-	if (IS_ERR(drv_data->reg_base)) {
-		rc = PTR_ERR(drv_data->reg_base);
-		goto exit_kfree;
-	}
+	if (IS_ERR(drv_data->reg_base))
+		return PTR_ERR(drv_data->reg_base);
 
 	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
 		sizeof(drv_data->adapter.name));
@@ -613,11 +612,11 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 	} else if (pd->dev.of_node) {
 		rc = mv64xxx_of_config(drv_data, pd->dev.of_node);
 		if (rc)
-			goto exit_unmap_regs;
+			goto exit_clk;
 	}
 	if (drv_data->irq < 0) {
 		rc = -ENXIO;
-		goto exit_unmap_regs;
+		goto exit_clk;
 	}
 
 	drv_data->adapter.dev.parent = &pd->dev;
@@ -637,7 +636,7 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 			"mv64xxx: Can't register intr handler irq: %d\n",
 			drv_data->irq);
 		rc = -EINVAL;
-		goto exit_unmap_regs;
+		goto exit_clk;
 	} else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
 		dev_err(&drv_data->adapter.dev,
 			"mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
@@ -648,9 +647,9 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 
 	return 0;
 
-	exit_free_irq:
-		free_irq(drv_data->irq, drv_data);
-	exit_unmap_regs:
+exit_free_irq:
+	free_irq(drv_data->irq, drv_data);
+exit_clk:
 #if defined(CONFIG_HAVE_CLK)
 	/* Not all platforms have a clk */
 	if (!IS_ERR(drv_data->clk)) {
@@ -658,8 +657,6 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 		clk_unprepare(drv_data->clk);
 	}
 #endif
-	exit_kfree:
-		kfree(drv_data);
 	return rc;
 }
 
@@ -678,7 +675,6 @@ mv64xxx_i2c_remove(struct platform_device *dev)
 		clk_unprepare(drv_data->clk);
 	}
 #endif
-	kfree(drv_data);
 
 	return rc;
 }
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:36:11 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:36:11 +0100
Subject: [PATCH 6/9] I2C: mv64xxx: fix error handling for request_irq()
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4uJ-0004Jt-0s@rmk-PC.arm.linux.org.uk>

Propagate the error code from request_irq() rather than ignoring it
entirely.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 841792f..a82ab25 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -630,12 +630,12 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 
 	mv64xxx_i2c_hw_init(drv_data);
 
-	if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
-			MV64XXX_I2C_CTLR_NAME, drv_data)) {
+	rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
+			 MV64XXX_I2C_CTLR_NAME, drv_data);
+	if (rc) {
 		dev_err(&drv_data->adapter.dev,
-			"mv64xxx: Can't register intr handler irq: %d\n",
-			drv_data->irq);
-		rc = -EINVAL;
+			"mv64xxx: Can't register intr handler irq%d: %d\n",
+			drv_data->irq, rc);
 		goto exit_clk;
 	} else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
 		dev_err(&drv_data->adapter.dev,
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:37:11 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:37:11 +0100
Subject: [PATCH 7/9] I2C: mv64xxx: remove I2C_M_NOSTART code
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4vH-0004Jz-F6@rmk-PC.arm.linux.org.uk>

As this driver does not advertise protocol mangling support
(I2C_FUNC_PROTOCOL_MANGLING is not set), having code to act on
I2C_M_NOSTART is illogical, and in any case isn't supportable on
anything but the first message - which makes no sense.  Remove
the I2C_M_NOSTART code.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |   26 +++++---------------------
 1 files changed, 5 insertions(+), 21 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index a82ab25..d160f8c 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -419,28 +419,12 @@ mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
 	spin_lock_irqsave(&drv_data->lock, flags);
 	mv64xxx_i2c_prepare_for_io(drv_data, msg);
 
-	if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
-		if (drv_data->msg->flags & I2C_M_RD) {
-			/* No action to do, wait for slave to send a byte */
-			drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
-			drv_data->state =
-				MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
-		} else {
-			drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
-			drv_data->state =
-				MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
-			drv_data->bytes_left--;
-		}
+	if (is_first) {
+		drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
+		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
 	} else {
-		if (is_first) {
-			drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
-			drv_data->state =
-				MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
-		} else {
-			drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
-			drv_data->state =
-				MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
-		}
+		drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
+		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
 	}
 
 	drv_data->send_stop = is_last;
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:38:11 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:38:11 +0100
Subject: [PATCH 8/9] I2C: mv64xxx: move mv64xxx_i2c_prepare_for_io()
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4wF-0004K5-U1@rmk-PC.arm.linux.org.uk>

Move mv64xxx_i2c_prepare_for_io() higher up in the driver to avoid a
future forward declaration for this function.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |   52 +++++++++++++++++++-------------------
 1 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index d160f8c..7457ef5 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -110,6 +110,32 @@ struct mv64xxx_i2c_data {
 	struct i2c_adapter	adapter;
 };
 
+static void
+mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
+	struct i2c_msg *msg)
+{
+	u32	dir = 0;
+
+	drv_data->msg = msg;
+	drv_data->byte_posn = 0;
+	drv_data->bytes_left = msg->len;
+	drv_data->aborting = 0;
+	drv_data->rc = 0;
+	drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
+		MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
+
+	if (msg->flags & I2C_M_RD)
+		dir = 1;
+
+	if (msg->flags & I2C_M_TEN) {
+		drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
+		drv_data->addr2 = (u32)msg->addr & 0xff;
+	} else {
+		drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
+		drv_data->addr2 = 0;
+	}
+}
+
 /*
  *****************************************************************************
  *
@@ -347,32 +373,6 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
  *****************************************************************************
  */
 static void
-mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
-	struct i2c_msg *msg)
-{
-	u32	dir = 0;
-
-	drv_data->msg = msg;
-	drv_data->byte_posn = 0;
-	drv_data->bytes_left = msg->len;
-	drv_data->aborting = 0;
-	drv_data->rc = 0;
-	drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
-		MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
-
-	if (msg->flags & I2C_M_RD)
-		dir = 1;
-
-	if (msg->flags & I2C_M_TEN) {
-		drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
-		drv_data->addr2 = (u32)msg->addr & 0xff;
-	} else {
-		drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
-		drv_data->addr2 = 0;
-	}
-}
-
-static void
 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
 {
 	long		time_left;
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 16:39:12 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 21:39:12 +0100
Subject: [PATCH 9/9] I2C: mv64xxx: fix race between FSM/interrupt and process
 context
In-Reply-To: <20130516202921.GW18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud4xE-0004KB-2T@rmk-PC.arm.linux.org.uk>

Asking for a multi-part message to be handled by this driver is racy; it
has been observed that the following sequence is possible with this
driver:

	- send start
	- send address + write
	- send data
	- send (repeated) start
	- send address + write
	- send (repeated) start
	- send address + read
	- unrecoverable bus hang (except by system reset)

The problem is that the interrupt handling sees the next event after the
first repeated start is sent - the IFLG bit is set in the register even
though INTEN is disabled.

Let's fix this by moving all of the message processing into interrupt
context, rather than having it partly in IRQ and partly in process
context.  This allows us to move immediately to the next message in the
interrupt handler and get on with the transfer, rather than incuring a
couple of scheduling switches to get the next message.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/i2c/busses/i2c-mv64xxx.c |   54 ++++++++++++++++++++++++--------------
 1 files changed, 34 insertions(+), 20 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 7457ef5..a2e4633 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -86,6 +86,8 @@ enum {
 };
 
 struct mv64xxx_i2c_data {
+	struct i2c_msg		*msgs;
+	int			num_msgs;
 	int			irq;
 	u32			state;
 	u32			action;
@@ -194,7 +196,7 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
 		if ((drv_data->bytes_left == 0)
 				|| (drv_data->aborting
 					&& (drv_data->byte_posn != 0))) {
-			if (drv_data->send_stop) {
+			if (drv_data->send_stop || drv_data->aborting) {
 				drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 				drv_data->state = MV64XXX_I2C_STATE_IDLE;
 			} else {
@@ -271,12 +273,25 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 {
 	switch(drv_data->action) {
 	case MV64XXX_I2C_ACTION_SEND_RESTART:
+		/* We should only get here if we have further messages */
+		BUG_ON(drv_data->num_msgs == 0);
+
 		drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
-		drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 		writel(drv_data->cntl_bits,
 			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
-		drv_data->block = 0;
-		wake_up(&drv_data->waitq);
+
+		drv_data->msgs++;
+		drv_data->num_msgs--;
+
+		/* Setup for the next message */
+		mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
+
+		/*
+		 * We're never at the start of the message here, and by this
+		 * time it's already too late to do any protocol mangling.
+		 * Thankfully, do not advertise support for that feature.
+		 */
+		drv_data->send_stop = drv_data->num_msgs == 1;
 		break;
 
 	case MV64XXX_I2C_ACTION_CONTINUE:
@@ -412,20 +427,15 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
 
 static int
 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
-				int is_first, int is_last)
+				int is_last)
 {
 	unsigned long	flags;
 
 	spin_lock_irqsave(&drv_data->lock, flags);
 	mv64xxx_i2c_prepare_for_io(drv_data, msg);
 
-	if (is_first) {
-		drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
-		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
-	} else {
-		drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
-		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
-	}
+	drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
+	drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
 
 	drv_data->send_stop = is_last;
 	drv_data->block = 1;
@@ -453,16 +463,20 @@ static int
 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 {
 	struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
-	int	i, rc;
+	int rc, ret = num;
 
-	for (i = 0; i < num; i++) {
-		rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
-						i == 0, i + 1 == num);
-		if (rc < 0)
-			return rc;
-	}
+	BUG_ON(drv_data->msgs != NULL);
+	drv_data->msgs = msgs;
+	drv_data->num_msgs = num;
+
+	rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
+	if (rc < 0)
+		ret = rc;
+
+	drv_data->num_msgs = 0;
+	drv_data->msgs = NULL;
 
-	return num;
+	return ret;
 }
 
 static const struct i2c_algorithm mv64xxx_i2c_algo = {
-- 
1.7.4.4



From nm at ti.com  Thu May 16 16:42:39 2013
From: nm at ti.com (Nishanth Menon)
Date: Thu, 16 May 2013 15:42:39 -0500
Subject: [PATCH v4] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <5195401B.5070209@ti.com>
References: <1368636386-17138-1-git-send-email-dmurphy@ti.com>
 <20130515170516.GA6135@kahuna> <5194FCDD.8080209@ti.com>
 <CAGo_u6pX+DdVNWqdPXDChzMr27YAXL_Zvt7DxWBijOCW0rXpkA@mail.gmail.com>
 <5195401B.5070209@ti.com>
Message-ID: <CAGo_u6oQP6eGkCQe=uTBmUsKQqFbS9_xXYt24_HRtjEr561O=g@mail.gmail.com>

On Thu, May 16, 2013 at 3:22 PM, Dan Murphy <dmurphy at ti.com> wrote:
> On 05/16/2013 01:18 PM, Nishanth Menon wrote:
>> On Thu, May 16, 2013 at 10:35 AM, Dan Murphy <dmurphy at ti.com> wrote:
>>> I am not sure you really want to do this.
>>> If I make the pinctrl part of the led structure then the only way the gpio_wk7 on a1-a3 to be configured is when
>>> the CONFIG_LEDS_GPIO flag is set.
>>>
>>> Do you really want that dependency?  You did say it was a key fix
>>> At least this way the pins are configured regardless of that flag.
>> That is better as the system will be left in the pinmux configuration
>> handed over from bootloader.
> So you want to depend on a boot loader to configure pins correctly for the kernel?
> Hmmm seems risky to me.

Not really! if it is a critical pinmux, pinmux defaults are great,
else belongs definitely to device->pinctrl :) depending on bootloader
pinmux implies NOT having pinmux even for device - NO. that is
definitely not what I stated.
Regards,
NM


From mturquette at linaro.org  Thu May 16 16:44:55 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 16 May 2013 13:44:55 -0700
Subject: [PATCH v2] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <1368677244-7279-1-git-send-email-skannan@codeaurora.org>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <1368677244-7279-1-git-send-email-skannan@codeaurora.org>
Message-ID: <20130516204455.12127.75296@quantum>

Quoting Saravana Kannan (2013-05-15 21:07:24)
> Without this patch, the following race condition is possible.
> * clk-A has two parents - clk-X and clk-Y.
> * All three are disabled and clk-X is current parent.
> * Thread A: clk_set_parent(clk-A, clk-Y).
> * Thread A: <snip execution flow>
> * Thread A: Grabs enable lock.
> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
> * Thread A: Updates clk-A SW parent to clk-Y
> * Thread A: Releases enable lock.
> * Thread B: clk_enable(clk-A).
> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.
> 
> clk-A is now enabled in software, but not clocking in hardware since the
> hardware parent is still clk-X.
> 
> The only way to avoid race conditions between clk_set_parent() and
> clk_enable/disable() is to ensure that clk_enable/disable() calls don't
> require changes to hardware enable state between changes to software clock
> topology and hardware clock topology.
> 
> The options to achieve the above are:
> 1. Grab the enable lock before changing software/hardware topology and
>    release it afterwards.
> 2. Keep the clock enabled for the duration of software/hardware topology
>    change so that any additional enable/disable calls don't try to change
>    the hardware state. Once the topology change is complete, the clock can
>    be put back in its original enable state.
> 
> Option (1) is not an acceptable solution since the set_parent() ops might
> need to sleep.
> 
> Therefore, this patch implements option (2).
> 
> This patch doesn't violate any API semantics. clk_disable() doesn't
> guarantee that the clock is actually disabled. So, no clients of a clock
> can assume that a clock is disabled after their last call to clk_disable().
> So, enabling the clock during a parent change is not a violation of any API
> semantics.
> 
> This also has the nice side effect of simplifying the error handling code.
> 
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>

Updated to this version in clk-next.

Thanks,
Mike

> ---
>  drivers/clk/clk.c |   91 ++++++++++++++++++++++++++---------------------------
>  1 files changed, 45 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 934cfd1..b4dbb8c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1377,67 +1377,61 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
>         unsigned long flags;
>         int ret = 0;
>         struct clk *old_parent = clk->parent;
> -       bool migrated_enable = false;
>  
> -       /* migrate prepare */
> -       if (clk->prepare_count)
> +       /*
> +        * Migrate prepare state between parents and prevent race with
> +        * clk_enable().
> +        *
> +        * If the clock is not prepared, then a race with
> +        * clk_enable/disable() is impossible since we already have the
> +        * prepare lock (future calls to clk_enable() need to be preceded by
> +        * a clk_prepare()).
> +        *
> +        * If the clock is prepared, migrate the prepared state to the new
> +        * parent and also protect against a race with clk_enable() by
> +        * forcing the clock and the new parent on.  This ensures that all
> +        * future calls to clk_enable() are practically NOPs with respect to
> +        * hardware and software states.
> +        *
> +        * See also: Comment for clk_set_parent() below.
> +        */
> +       if (clk->prepare_count) {
>                 __clk_prepare(parent);
> -
> -       flags = clk_enable_lock();
> -
> -       /* migrate enable */
> -       if (clk->enable_count) {
> -               __clk_enable(parent);
> -               migrated_enable = true;
> +               clk_enable(parent);
> +               clk_enable(clk);
>         }
>  
>         /* update the clk tree topology */
> +       flags = clk_enable_lock();
>         clk_reparent(clk, parent);
> -
>         clk_enable_unlock(flags);
>  
>         /* change clock input source */
>         if (parent && clk->ops->set_parent)
>                 ret = clk->ops->set_parent(clk->hw, p_index);
> -
>         if (ret) {
> -               /*
> -                * The error handling is tricky due to that we need to release
> -                * the spinlock while issuing the .set_parent callback. This
> -                * means the new parent might have been enabled/disabled in
> -                * between, which must be considered when doing rollback.
> -                */
> -               flags = clk_enable_lock();
>  
> +               flags = clk_enable_lock();
>                 clk_reparent(clk, old_parent);
> -
> -               if (migrated_enable && clk->enable_count) {
> -                       __clk_disable(parent);
> -               } else if (migrated_enable && (clk->enable_count == 0)) {
> -                       __clk_disable(old_parent);
> -               } else if (!migrated_enable && clk->enable_count) {
> -                       __clk_disable(parent);
> -                       __clk_enable(old_parent);
> -               }
> -
>                 clk_enable_unlock(flags);
>  
> -               if (clk->prepare_count)
> +               if (clk->prepare_count) {
> +                       clk_disable(clk);
> +                       clk_disable(parent);
>                         __clk_unprepare(parent);
> -
> +               }
>                 return ret;
>         }
>  
> -       /* clean up enable for old parent if migration was done */
> -       if (migrated_enable) {
> -               flags = clk_enable_lock();
> -               __clk_disable(old_parent);
> -               clk_enable_unlock(flags);
> -       }
> -
> -       /* clean up prepare for old parent if migration was done */
> -       if (clk->prepare_count)
> +       /*
> +        * Finish the migration of prepare state and undo the changes done
> +        * for preventing a race with clk_enable().
> +        */
> +       if (clk->prepare_count) {
> +               clk_disable(clk);
> +               clk_disable(old_parent);
>                 __clk_unprepare(old_parent);
> +       }
>  
>         /* update debugfs with new clk tree topology */
>         clk_debug_reparent(clk, parent);
> @@ -1449,12 +1443,17 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
>   * @clk: the mux clk whose input we are switching
>   * @parent: the new input to clk
>   *
> - * Re-parent clk to use parent as it's new input source.  If clk has the
> - * CLK_SET_PARENT_GATE flag set then clk must be gated for this
> - * operation to succeed.  After successfully changing clk's parent
> - * clk_set_parent will update the clk topology, sysfs topology and
> - * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
> - * success, -EERROR otherwise.
> + * Re-parent clk to use parent as its new input source.  If clk is in
> + * prepared state, the clk will get enabled for the duration of this call. If
> + * that's not acceptable for a specific clk (Eg: the consumer can't handle
> + * that, the reparenting is glitchy in hardware, etc), use the
> + * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
> + *
> + * After successfully changing clk's parent clk_set_parent will update the
> + * clk topology, sysfs topology and propagate rate recalculation via
> + * __clk_recalc_rates.
> + *
> + * Returns 0 on success, -EERROR otherwise.
>   */
>  int clk_set_parent(struct clk *clk, struct clk *parent)
>  {
> -- 
> 1.7.8.3
> 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation


From rmk+kernel at arm.linux.org.uk  Thu May 16 15:26:58 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:26:58 +0100
Subject: [RFC 5/8] drm/i2c: nxp-tda998x: prepare for video input configuration
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3pK-0001qv-D7@rmk-PC.arm.linux.org.uk>

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |   16 ++++++++++------
 1 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index da2917b..d6afd02 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -32,6 +32,9 @@ struct tda998x_priv {
 	uint16_t rev;
 	uint8_t current_page;
 	int dpms;
+	u8 vip_cntrl_0;
+	u8 vip_cntrl_1;
+	u8 vip_cntrl_2;
 };
 
 #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
@@ -447,12 +450,9 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 		reg_write(encoder, REG_ENA_VP_1, 0xff);
 		reg_write(encoder, REG_ENA_VP_2, 0xff);
 		/* set muxing after enabling ports: */
-		reg_write(encoder, REG_VIP_CNTRL_0,
-				VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
-		reg_write(encoder, REG_VIP_CNTRL_1,
-				VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1));
-		reg_write(encoder, REG_VIP_CNTRL_2,
-				VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5));
+		reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
+		reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
+		reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 		break;
 	case DRM_MODE_DPMS_OFF:
 		/* disable audio and video ports */
@@ -822,6 +822,10 @@ tda998x_encoder_init(struct i2c_client *client,
 	if (!priv)
 		return -ENOMEM;
 
+	priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
+	priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
+	priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
+
 	priv->current_page = 0;
 	priv->cec = i2c_new_dummy(client->adapter, 0x34);
 	priv->dpms = DRM_MODE_DPMS_OFF;
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:27:38 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:27:38 +0100
Subject: [RFC 7/8] DRM: Dove: add support for drm tda19988 driver
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3py-0001r4-Lm@rmk-PC.arm.linux.org.uk>

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/dove/Kconfig         |    9 ++
 drivers/gpu/drm/dove/Makefile        |    2 +
 drivers/gpu/drm/dove/dove_drm.h      |    1 +
 drivers/gpu/drm/dove/dove_drv.c      |    4 +
 drivers/gpu/drm/dove/dove_tda19988.c |  249 ++++++++++++++++++++++++++++++++++
 5 files changed, 265 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpu/drm/dove/dove_tda19988.c

diff --git a/drivers/gpu/drm/dove/Kconfig b/drivers/gpu/drm/dove/Kconfig
index 24844b6..718d3c5 100644
--- a/drivers/gpu/drm/dove/Kconfig
+++ b/drivers/gpu/drm/dove/Kconfig
@@ -16,6 +16,15 @@ config DRM_DOVE
 
 if DRM_DOVE != n
 
+config DRM_DOVE_TDA1998X
+	bool "Support TDA1998X HDMI output"
+	depends on I2C
+	depends on DRM_I2C_NXP_TDA998X = y
+	default y
+	help
+	  Support the TDA1998x HDMI output device found on the Solid-Run
+	  CuBox.
+
 config DRM_DOVE_CURSOR
 	bool "Enable Dove DRM hardware cursor support"
 
diff --git a/drivers/gpu/drm/dove/Makefile b/drivers/gpu/drm/dove/Makefile
index a2326c4..65c701e 100644
--- a/drivers/gpu/drm/dove/Makefile
+++ b/drivers/gpu/drm/dove/Makefile
@@ -4,4 +4,6 @@ dove-y			:= dove_crtc.o dove_drv.o dove_fb.o dove_fbdev.o \
 			   dove_gem.o dove_output.o dove_overlay.o
 dove-$(CONFIG_DEBUG_FS) += dove_debugfs.o
 
+dove-$(CONFIG_DRM_DOVE_TDA1998X) += dove_tda19988.o
+
 obj-$(CONFIG_DRM_DOVE) := dove.o
diff --git a/drivers/gpu/drm/dove/dove_drm.h b/drivers/gpu/drm/dove/dove_drm.h
index d00a9d6..825c553 100644
--- a/drivers/gpu/drm/dove/dove_drm.h
+++ b/drivers/gpu/drm/dove/dove_drm.h
@@ -57,6 +57,7 @@ void dove_overlay_destroy(struct drm_device *);
 void dove_drm_overlay_off(struct drm_device *, struct dove_overlay *);
 
 struct drm_connector *dove_drm_tda19988_create(struct drm_device *dev);
+struct drm_connector *dove_drm_tda19988_nxp_create(struct drm_device *dev);
 
 int dove_drm_debugfs_init(struct drm_minor *);
 void dove_drm_debugfs_cleanup(struct drm_minor *);
diff --git a/drivers/gpu/drm/dove/dove_drv.c b/drivers/gpu/drm/dove/dove_drv.c
index 98cb25f..1792f00 100644
--- a/drivers/gpu/drm/dove/dove_drv.c
+++ b/drivers/gpu/drm/dove/dove_drv.c
@@ -88,6 +88,10 @@ static int dove_drm_load(struct drm_device *dev, unsigned long flags)
 		}
 	}
 
+#ifdef CONFIG_DRM_DOVE_TDA1998X
+	dove_drm_tda19988_create(dev);
+#endif
+
 	ret = drm_vblank_init(dev, n);
 	if (ret)
 		goto err_kms;
diff --git a/drivers/gpu/drm/dove/dove_tda19988.c b/drivers/gpu/drm/dove/dove_tda19988.c
new file mode 100644
index 0000000..26ef2a2
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_tda19988.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  Rewritten from the dovefb driver, and Armada510 manuals.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "drmP.h"
+#include "drm_edid.h"
+#include "drm_crtc_helper.h"
+#include "dove_output.h"
+#include "dove_drm.h"
+#include <drm/drm_encoder_slave.h>
+#include <drm/i2c/tda998x.h>
+
+struct dove_drm_tda19988_encoder {
+	struct drm_encoder_slave slave;
+	struct drm_encoder_helper_funcs encoder_helpers;
+};
+#define to_tda19988_encoder(enc) container_of(to_encoder_slave(enc), struct dove_drm_tda19988_encoder, slave)
+
+static int dove_drm_connector_tda19988_mode_valid(struct drm_connector *conn,
+	struct drm_display_mode *mode)
+{
+	struct drm_encoder *enc = conn->encoder;
+	struct dove_drm_tda19988_encoder *tenc = to_tda19988_encoder(enc);
+
+	return tenc->slave.slave_funcs->mode_valid(enc, mode);
+}
+
+static int dove_drm_connector_tda19988_get_modes(struct drm_connector *conn)
+{
+	struct drm_display_mode *mode;
+	struct drm_encoder *enc = conn->encoder;
+	struct dove_drm_tda19988_encoder *tenc = to_tda19988_encoder(enc);
+	int count = tenc->slave.slave_funcs->get_modes(enc, conn);
+
+	if (count)
+		return count;
+
+	mode = drm_mode_create(conn->dev);
+	mode->type = DRM_MODE_TYPE_DRIVER;
+	mode->clock = 74250;
+	mode->vrefresh = 60;
+	mode->hdisplay = 1280;
+	mode->hsync_start = mode->hdisplay + 110;
+	mode->hsync_end = mode->hsync_start + 40;
+	mode->htotal = mode->hsync_end + 220;
+	mode->vdisplay = 720;
+	mode->vsync_start = mode->vdisplay + 5;
+	mode->vsync_end = mode->vsync_start + 5;
+	mode->vtotal = mode->vsync_end + 20;
+	mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
+
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(conn, mode);
+
+	return 1;
+}
+
+static bool dove_drm_tda19988_enc_mode_fixup(struct drm_encoder *encoder,
+	const struct drm_display_mode *mode, struct drm_display_mode *adjusted)
+{
+	adjusted->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
+			     DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
+			     DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC);
+
+	/* The TDA19988 always requires negative VSYNC? */
+	adjusted->flags |= DRM_MODE_FLAG_NVSYNC;
+
+	/* The TDA19988 requires positive HSYNC on 1080p or 720p */
+	if ((adjusted->hdisplay == 1920 && adjusted->vdisplay == 1080) ||
+	    (adjusted->hdisplay == 1280 && adjusted->vdisplay == 720))
+		adjusted->flags |= DRM_MODE_FLAG_PHSYNC;
+	else
+		adjusted->flags |= DRM_MODE_FLAG_NHSYNC;
+
+	return true;
+}
+
+static void dove_drm_tda19988_enc_destroy(struct drm_encoder *enc)
+{
+	struct dove_drm_tda19988_encoder *tenc = to_tda19988_encoder(enc);
+
+	if (tenc->slave.slave_funcs)
+		tenc->slave.slave_funcs->destroy(enc);
+
+	drm_encoder_cleanup(&tenc->slave.base);
+	kfree(tenc);
+}
+
+static const struct drm_encoder_funcs dove_drm_tda19988_enc_funcs = {
+	.destroy	= dove_drm_tda19988_enc_destroy,
+};
+
+static const struct drm_connector_helper_funcs dove_drm_conn_tda19988_helper_funcs = {
+	.get_modes	= dove_drm_connector_tda19988_get_modes,
+	.mode_valid	= dove_drm_connector_tda19988_mode_valid,
+	.best_encoder	= dove_drm_connector_best_encoder,
+};
+
+static enum drm_connector_status dove_drm_conn_tda19988_detect(
+	struct drm_connector *conn, bool force)
+{
+	struct drm_encoder *enc = conn->encoder;
+	struct drm_encoder_helper_funcs *funcs = enc->helper_private;
+	enum drm_connector_status status = funcs->detect(enc, conn);
+
+	/*
+	 * Treat all disconnected status as unknown, otherwise we fail
+	 * to initialize when we have no "connected" output devices.
+	 */
+	if (status == connector_status_disconnected)
+		status = connector_status_unknown;
+
+	return status;
+}
+
+static struct i2c_board_info info[] = {
+	{
+		.type = "tda998x",
+		.addr = 0x70,
+	},
+	{ }
+};
+
+static struct tda998x_encoder_params params = {
+#if 0
+	/* This is with a post mux value of 0x12, which is what the nxp driver uses
+	    VIP_MUX_G_B | VIP_MUX_B_R | VIP_MUX_R_G = 0x00 | 0x02 | 0x10
+	LCD out	Pins	VIP	Int VP
+	R:7:0	VPC7:0	23:16	7:0[R]
+	G:15:8	VPB7:0	15:8	23:16[G]
+	B:23:16	VPA7:0	7:0	15:8[B]
+	*/
+	.swap_a = 0,
+	.swap_b = 1,
+	.swap_c = 2,
+	.swap_d = 3,
+	.swap_e = 4,
+	.swap_f = 5,
+#else
+	/* With 0x24, there is no translation between vp_out and int_vp
+	FB	LCD out	Pins	VIP 	Int Vp
+	R:23:16	R:7:0	VPC7:0	7:0	7:0[R]
+	G:15:8	G:15:8	VPB7:0	23:16	23:16[G]
+	B:7:0	B:23:16	VPA7:0	15:8	15:8[B]
+	*/
+	.swap_a = 2,
+	.swap_b = 3,
+	.swap_c = 4,
+	.swap_d = 5,
+	.swap_e = 0,
+	.swap_f = 1,
+#endif
+	.audio_cfg = BIT(2),
+	.audio_frame[1] = 1,
+	.audio_format = AFMT_SPDIF,
+	.audio_sample_rate = 44100,
+};
+
+static int dove_drm_conn_tda19988_create(struct drm_connector *conn,
+	struct drm_encoder **enc_ret)
+{
+	struct dove_drm_tda19988_encoder *tenc;
+	struct drm_encoder_slave_funcs *sfuncs;
+	struct i2c_adapter *adap;
+	int ret;
+
+	drm_connector_helper_add(conn, &dove_drm_conn_tda19988_helper_funcs);
+
+	tenc = kzalloc(sizeof(*tenc), GFP_KERNEL);
+	if (!tenc)
+		return -ENOMEM;
+
+	tenc->slave.base.possible_crtcs = 1 << 0;
+
+	adap = i2c_get_adapter(0);
+	if (!adap) {
+		kfree(tenc);
+		return -EPROBE_DEFER;
+	}
+
+	ret = drm_encoder_init(conn->dev, &tenc->slave.base,
+			       &dove_drm_tda19988_enc_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("unable to init encoder\n");
+		i2c_put_adapter(adap);
+		kfree(tenc);
+		return ret;
+	}
+
+	ret = drm_i2c_encoder_init(conn->dev, &tenc->slave, adap, info);
+	i2c_put_adapter(adap);
+	if (ret) {
+		DRM_ERROR("unable to init encoder slave\n");
+		dove_drm_tda19988_enc_destroy(&tenc->slave.base);
+		return ret;
+	}
+
+	sfuncs = tenc->slave.slave_funcs;
+	tenc->encoder_helpers.dpms = sfuncs->dpms;
+	tenc->encoder_helpers.save = sfuncs->save;
+	tenc->encoder_helpers.restore = sfuncs->restore;
+	tenc->encoder_helpers.mode_fixup = dove_drm_tda19988_enc_mode_fixup;
+	tenc->encoder_helpers.prepare = dove_drm_encoder_prepare;
+	tenc->encoder_helpers.commit = dove_drm_encoder_commit;
+	tenc->encoder_helpers.mode_set = sfuncs->mode_set;
+	tenc->encoder_helpers.detect = sfuncs->detect;
+
+	drm_encoder_helper_add(&tenc->slave.base, &tenc->encoder_helpers);
+	ret = sfuncs->create_resources(&tenc->slave.base, conn);
+	if (ret) {
+		dove_drm_tda19988_enc_destroy(&tenc->slave.base);
+		return ret;
+	}
+
+	sfuncs->set_config(&tenc->slave.base, &params);
+
+	conn->encoder = &tenc->slave.base;
+	*enc_ret = &tenc->slave.base;
+
+	return ret;
+}
+
+static int dove_drm_conn_tda19988_set_property(struct drm_connector *conn,
+	struct drm_property *property, uint64_t value)
+{
+	struct dove_drm_tda19988_encoder *tenc =
+		to_tda19988_encoder(conn->encoder);
+	struct drm_encoder_slave_funcs *sfuncs = tenc->slave.slave_funcs;
+
+	return sfuncs->set_property(&tenc->slave.base, conn, property, value);
+}
+
+static const struct dove_output_type dove_drm_conn_tda19988 = {
+	.connector_type	= DRM_MODE_CONNECTOR_HDMIA,
+	.polled		= DRM_CONNECTOR_POLL_HPD,
+	.detect		= dove_drm_conn_tda19988_detect,
+	.create		= dove_drm_conn_tda19988_create,
+	.set_property	= dove_drm_conn_tda19988_set_property,
+};
+
+struct drm_connector *dove_drm_tda19988_create(struct drm_device *dev)
+{
+	return dove_output_create(dev, &dove_drm_conn_tda19988);
+}
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:26:18 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:26:18 +0100
Subject: [RFC 3/8] drm/i2c: nxp-tda998x: ensure VIP output mux is properly set
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3og-0001qm-52@rmk-PC.arm.linux.org.uk>

When switching between various drivers for this device, it's possible
that some critical registers are left containing values which affect
the device operation.  One such case encountered is the VIP output
mux register.  This defaults to 0x24 on powerup, but other drivers may
set this to 0x12.  This results in incorrect colours.

Fix this by ensuring that the register is always set to the power on
default setting.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index d71c408..4b4db95 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -110,6 +110,7 @@ struct tda998x_priv {
 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
+#define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 # define MAT_CONTRL_MAT_BP        (1 << 2)
@@ -438,6 +439,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
+		/* Write the default value MUX register */
+		reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
 		/* enable audio and video ports */
 		reg_write(encoder, REG_ENA_AP, 0xff);
 		reg_write(encoder, REG_ENA_VP_0, 0xff);
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:26:38 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:26:38 +0100
Subject: [RFC 4/8] drm/i2c: nxp-tda998x: fix npix/nline programming
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3p0-0001qq-8v@rmk-PC.arm.linux.org.uk>

The npix/nline registers are supposed to be programmed with the total
number of pixels/lines, not the displayed pixels/lines, and not minus
one either.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index 4b4db95..da2917b 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -586,8 +586,8 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
 		reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
 
 	reg_write(encoder, REG_VIDFORMAT, 0x00);
-	reg_write16(encoder, REG_NPIX_MSB, mode->hdisplay - 1);
-	reg_write16(encoder, REG_NLINE_MSB, mode->vdisplay - 1);
+	reg_write16(encoder, REG_NPIX_MSB, mode->htotal);
+	reg_write16(encoder, REG_NLINE_MSB, mode->vtotal);
 	reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start);
 	reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end);
 	reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start);
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:25:58 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:25:58 +0100
Subject: [RFC 2/8] drm/i2c: nxp-tda998x: fix EDID reading on TDA19988 devices
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3oM-0001qg-0c@rmk-PC.arm.linux.org.uk>

TDA19988 devices need their RAM enabled in order to read EDID
information.  Add support for this.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index e68b58a..d71c408 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -229,6 +229,8 @@ struct tda998x_priv {
 
 /* Page 12h: HDCP and OTP */
 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
+#define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
+# define TX4_PD_RAM               (1 << 1)
 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 # define TX33_HDMI                (1 << 1)
 
@@ -673,6 +675,7 @@ read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
 static uint8_t *
 do_get_edid(struct drm_encoder *encoder)
 {
+	struct tda998x_priv *priv = to_tda998x_priv(encoder);
 	int j = 0, valid_extensions = 0;
 	uint8_t *block, *new;
 	bool print_bad_edid = drm_debug & DRM_UT_KMS;
@@ -680,6 +683,9 @@ do_get_edid(struct drm_encoder *encoder)
 	if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
 		return NULL;
 
+	if (priv->rev == TDA19988)
+		reg_clear(encoder, REG_TX4, TX4_PD_RAM);
+
 	/* base block fetch */
 	if (read_edid_block(encoder, block, 0))
 		goto fail;
@@ -689,7 +695,7 @@ do_get_edid(struct drm_encoder *encoder)
 
 	/* if there's no extensions, we're done */
 	if (block[0x7e] == 0)
-		return block;
+		goto done;
 
 	new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
 	if (!new)
@@ -716,9 +722,15 @@ do_get_edid(struct drm_encoder *encoder)
 		block = new;
 	}
 
+done:
+	if (priv->rev == TDA19988)
+		reg_set(encoder, REG_TX4, TX4_PD_RAM);
+
 	return block;
 
 fail:
+	if (priv->rev == TDA19988)
+		reg_set(encoder, REG_TX4, TX4_PD_RAM);
 	dev_warn(encoder->dev->dev, "failed to read EDID\n");
 	kfree(block);
 	return NULL;
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:25:37 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:25:37 +0100
Subject: [RFC 1/8] DRM: Add Dove DRM driver
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3o1-0001qc-RH@rmk-PC.arm.linux.org.uk>

This patch adds support for the pair of LCD controllers on the Marvell
Armada 510 (aka Dove) SoCs.  This driver supports:
- multiple contiguous scanout buffers for video and graphics
- shm backed cacheable buffer objects for X pixmaps for Vivante GPU
  acceleration
- dual lcd0 and lcd1 crt operation
- video overlay on each LCD crt
- page flipping of the main scanout buffers

Included in this commit is the core driver with no output support; output
support is platform and encoder driver dependent.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/Kconfig             |    2 +
 drivers/gpu/drm/Makefile            |    1 +
 drivers/gpu/drm/dove/Kconfig        |   22 +
 drivers/gpu/drm/dove/Makefile       |    7 +
 drivers/gpu/drm/dove/dove_crtc.c    |  917 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/dove/dove_crtc.h    |   87 ++++
 drivers/gpu/drm/dove/dove_debugfs.c |  186 +++++++
 drivers/gpu/drm/dove/dove_drm.h     |   64 +++
 drivers/gpu/drm/dove/dove_drv.c     |  323 ++++++++++++
 drivers/gpu/drm/dove/dove_fb.c      |  156 ++++++
 drivers/gpu/drm/dove/dove_fb.h      |   21 +
 drivers/gpu/drm/dove/dove_fbdev.c   |  210 ++++++++
 drivers/gpu/drm/dove/dove_gem.c     |  420 ++++++++++++++++
 drivers/gpu/drm/dove/dove_gem.h     |   41 ++
 drivers/gpu/drm/dove/dove_hw.h      |  283 +++++++++++
 drivers/gpu/drm/dove/dove_ioctl.h   |  128 +++++
 drivers/gpu/drm/dove/dove_ioctlP.h  |   22 +
 drivers/gpu/drm/dove/dove_output.c  |  124 +++++
 drivers/gpu/drm/dove/dove_output.h  |   26 +
 drivers/gpu/drm/dove/dove_overlay.c |  514 ++++++++++++++++++++
 drivers/gpu/drm/dove/drm_helper.h   |   31 ++
 21 files changed, 3585 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpu/drm/dove/Kconfig
 create mode 100644 drivers/gpu/drm/dove/Makefile
 create mode 100644 drivers/gpu/drm/dove/dove_crtc.c
 create mode 100644 drivers/gpu/drm/dove/dove_crtc.h
 create mode 100644 drivers/gpu/drm/dove/dove_debugfs.c
 create mode 100644 drivers/gpu/drm/dove/dove_drm.h
 create mode 100644 drivers/gpu/drm/dove/dove_drv.c
 create mode 100644 drivers/gpu/drm/dove/dove_fb.c
 create mode 100644 drivers/gpu/drm/dove/dove_fb.h
 create mode 100644 drivers/gpu/drm/dove/dove_fbdev.c
 create mode 100644 drivers/gpu/drm/dove/dove_gem.c
 create mode 100644 drivers/gpu/drm/dove/dove_gem.h
 create mode 100644 drivers/gpu/drm/dove/dove_hw.h
 create mode 100644 drivers/gpu/drm/dove/dove_ioctl.h
 create mode 100644 drivers/gpu/drm/dove/dove_ioctlP.h
 create mode 100644 drivers/gpu/drm/dove/dove_output.c
 create mode 100644 drivers/gpu/drm/dove/dove_output.h
 create mode 100644 drivers/gpu/drm/dove/dove_overlay.c
 create mode 100644 drivers/gpu/drm/dove/drm_helper.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 1e82882..db0a607 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -213,6 +213,8 @@ source "drivers/gpu/drm/mgag200/Kconfig"
 
 source "drivers/gpu/drm/cirrus/Kconfig"
 
+source "drivers/gpu/drm/dove/Kconfig"
+
 source "drivers/gpu/drm/shmobile/Kconfig"
 
 source "drivers/gpu/drm/tegra/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 0d59b24..2d2e593 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_DRM_EXYNOS) +=exynos/
 obj-$(CONFIG_DRM_GMA500) += gma500/
 obj-$(CONFIG_DRM_UDL) += udl/
 obj-$(CONFIG_DRM_AST) += ast/
+obj-$(CONFIG_DRM_DOVE) += dove/
 obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_OMAP)	+= omapdrm/
diff --git a/drivers/gpu/drm/dove/Kconfig b/drivers/gpu/drm/dove/Kconfig
new file mode 100644
index 0000000..24844b6
--- /dev/null
+++ b/drivers/gpu/drm/dove/Kconfig
@@ -0,0 +1,22 @@
+config DRM_DOVE
+	tristate "DRM support for Marvell Dove"
+	depends on DRM && HAVE_CLK
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	select DRM_KMS_HELPER
+	help
+	  Support the "LCD" controllers found on the Marvell Armada 510
+	  Dove devices.  There are two controllers on the device, each
+	  controller supports graphics and video overlays.
+
+	  This driver provides no built-in acceleration; acceleration is
+	  performed by other IP found on the SoC.  This driver provides
+	  kernel mode setting and buffer management to userspace.
+
+if DRM_DOVE != n
+
+config DRM_DOVE_CURSOR
+	bool "Enable Dove DRM hardware cursor support"
+
+endif
diff --git a/drivers/gpu/drm/dove/Makefile b/drivers/gpu/drm/dove/Makefile
new file mode 100644
index 0000000..a2326c4
--- /dev/null
+++ b/drivers/gpu/drm/dove/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -Iinclude/drm
+
+dove-y			:= dove_crtc.o dove_drv.o dove_fb.o dove_fbdev.o \
+			   dove_gem.o dove_output.o dove_overlay.o
+dove-$(CONFIG_DEBUG_FS) += dove_debugfs.o
+
+obj-$(CONFIG_DRM_DOVE) := dove.o
diff --git a/drivers/gpu/drm/dove/dove_crtc.c b/drivers/gpu/drm/dove/dove_crtc.c
new file mode 100644
index 0000000..4c590d5
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_crtc.c
@@ -0,0 +1,917 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  Rewritten from the dovefb driver, and Armada510 manuals.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "dove_crtc.h"
+#include "dove_drm.h"
+#include "dove_fb.h"
+#include "dove_gem.h"
+#include "dove_hw.h"
+
+/*
+ * A note about interlacing.  Let's consider HDMI 1920x1080i.
+ * The timing parameters we have from X are:
+ *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
+ *  1920 2448 2492 2640  1080 1084 1094 1125
+ * Which get translated to:
+ *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
+ *  1920 2448 2492 2640   540  542  547  562
+ *
+ * This is how it is defined by CEA-861-D - line and pixel numbers are
+ * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
+ * line: 2640.  The odd frame, the first active line is at line 21, and
+ * the even frame, the first active line is 584.
+ *
+ * LN:    560     561     562     563             567     568    569
+ * DE:    ~~~|____________________________//__________________________
+ * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
+ * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
+ *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
+ *
+ * LN:    1123   1124    1125      1               5       6      7
+ * DE:    ~~~|____________________________//__________________________
+ * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
+ * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
+ *  23 blanking lines
+ *
+ * The Dove LCD Controller line and pixel numbers are, like X timings,
+ * referenced to the top left of the active frame.
+ *
+ * So, translating these to our LCD controller:
+ *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
+ *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
+ * Note: Vsync front porch remains constant!
+ *
+ * if (odd_frame) {
+ *   vtotal = mode->crtc_vtotal + 1;
+ *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
+ *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
+ * } else {
+ *   vtotal = mode->crtc_vtotal;
+ *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
+ *   vhorizpos = mode->crtc_hsync_start;
+ * }
+ * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
+ *
+ * So, we need to reprogram these registers on each vsync event:
+ *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
+ *
+ * Note: we do not use the frame done interrupts because these appear
+ * to happen too early, and lead to jitter on the display (presumably
+ * they occur at the end of the last active line, before the vsync back
+ * porch, which we're reprogramming.)
+ */
+
+static void dove_updatel(uint32_t val, uint32_t mask, void __iomem *ptr)
+{
+	uint32_t ov, v;
+
+	ov = v = readl_relaxed(ptr);
+	v = (v & ~mask) | val;
+	if (ov != v)
+		writel_relaxed(v, ptr);
+}
+
+void dove_drm_crtc_update_regs(struct dove_crtc *dcrtc, struct dove_regs *regs)
+{
+	while (regs->offset != ~0) {
+		void __iomem *reg = dcrtc->base + regs->offset;
+		uint32_t val;
+
+		val = regs->mask;
+		if (val != 0)
+			val &= readl_relaxed(reg);
+		writel_relaxed(val | regs->val, reg);
+		++regs;
+	}
+}
+
+#define dpms_blanked(dpms)	((dpms) != DRM_MODE_DPMS_ON)
+
+static void dove_drm_crtc_update(struct dove_crtc *dcrtc)
+{
+	uint32_t dumb_ctrl;
+
+	dumb_ctrl = dcrtc->cfg_dumb_ctrl;
+
+	if (!dpms_blanked(dcrtc->dpms))
+		dumb_ctrl |= CFG_DUMB_ENA;
+
+	/*
+	 * When a dumb interface isn't under 24bit, it might be
+	 * under SPI or GPIO.  If set to 7, this will force
+	 * LCD_D[23:0] to output blank color and damage GPIO
+	 * and SPI behaviour.  So leave it as-is unless in
+	 * DUMB24_RGB888_0 mode.
+	 */
+	if (dpms_blanked(dcrtc->dpms) &&
+	    (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
+		dumb_ctrl &= ~DUMB_MASK;
+		dumb_ctrl |= DUMB_BLANK;
+	}
+
+	/*
+	 * The spec is unclear about the polarities of the syncs.
+	 * We assume their non-inverted state is active high.
+	 */
+	if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
+		dumb_ctrl |= CFG_INV_CSYNC;
+	if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
+		dumb_ctrl |= CFG_INV_HSYNC;
+	if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
+		dumb_ctrl |= CFG_INV_VSYNC;
+
+	if (dcrtc->dumb_ctrl != dumb_ctrl) {
+		dcrtc->dumb_ctrl = dumb_ctrl;
+		writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
+	}
+}
+
+static unsigned dove_drm_crtc_calc_fb(struct drm_framebuffer *fb, int x, int y,
+	struct dove_regs *regs, bool interlaced)
+{
+	struct dove_gem_object *obj = drm_fb_obj(fb);
+	unsigned pitch = fb->pitches[0];
+	unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
+	uint32_t addr_odd, addr_even;
+	unsigned i = 0;
+
+	DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
+		pitch, x, y, fb->bits_per_pixel);
+
+	addr_odd = addr_even = obj->dev_addr + offset;
+
+	if (interlaced) {
+		addr_even += pitch;
+		pitch *= 2;
+	}
+
+	/* write offset, base, and pitch */
+	dove_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
+	dove_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
+	dove_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
+
+	return i;
+}
+
+static void dove_drm_crtc_finish_fb(struct dove_crtc *dcrtc,
+	struct drm_framebuffer *fb, bool force)
+{
+	struct dove_gem_object *obj;
+
+	if (!fb)
+		return;
+
+	obj = drm_fb_obj(fb);
+//	if (force || dpms_blanked(dcrtc->dpms)) {
+		/* Display is disabled, so just drop the old fb */
+		drm_gem_object_unreference_unlocked(&obj->obj);
+//	} else {
+//fixme		dcrtc->old_fb_obj = obj;
+//	}
+}
+
+static void dove_drm_crtc_complete_flip(struct dove_crtc *dcrtc,
+	struct timeval *now)
+{
+	struct drm_device *dev = dcrtc->crtc.dev;
+	struct dove_page_flip *flip = dcrtc->flip;
+	struct drm_pending_vblank_event *e = flip->event;
+	struct timeval tvbl;
+	unsigned seq;
+
+	dcrtc->flip = NULL;
+
+	drm_vblank_put(dev, dcrtc->num);
+	dove_drm_crtc_update_regs(dcrtc, flip->regs);
+	kfree(flip);
+
+	if (!e)
+		return;
+
+	seq = drm_vblank_count_and_time(dev, dcrtc->num, &tvbl);
+
+	/* Just like the i915 driver */
+	if (now) {
+		s64 ns_vbl, ns_now;
+
+		ns_vbl = timeval_to_ns(&tvbl);
+		ns_now = timeval_to_ns(now);
+
+		if (10 * (ns_now - ns_vbl) > 9 * dcrtc->crtc.framedur_ns) {
+			seq++;
+			tvbl = ns_to_timeval(ns_vbl + dcrtc->crtc.framedur_ns);
+		}
+	}
+
+	e->event.sequence = seq;
+	e->event.tv_sec = tvbl.tv_sec;
+	e->event.tv_usec = tvbl.tv_usec;
+
+	list_add_tail(&e->base.link, &e->base.file_priv->event_list);
+	wake_up_interruptible(&e->base.file_priv->event_wait);
+}
+
+static void dove_drm_vblank_off(struct dove_crtc *dcrtc)
+{
+	struct drm_device *dev = dcrtc->crtc.dev;
+
+	/*
+	 * Tell the DRM core that vblank IRQs aren't going to happen for
+	 * a while.  This cleans up any pending vblank events for us.
+	 */
+	drm_vblank_off(dev, dcrtc->num);
+
+	/* Handle any pending flip event. */
+	spin_lock_irq(&dev->event_lock);
+	if (dcrtc->flip)
+		dove_drm_crtc_complete_flip(dcrtc, NULL);
+	spin_unlock_irq(&dev->event_lock);
+}
+
+void dove_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b, int idx)
+{
+}
+
+void dove_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, int idx)
+{
+}
+
+/* The mode_config.mutex will be held for this call */
+static void dove_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+
+	if (dcrtc->dpms != dpms) {
+		dcrtc->dpms = dpms;
+		dove_drm_crtc_update(dcrtc);
+		if (dpms_blanked(dpms))
+			dove_drm_vblank_off(dcrtc);
+	}
+}
+
+/*
+ * Prepare for a mode set.  Turn off overlay to ensure that we don't end
+ * up with the overlay size being bigger than the active screen size.
+ * We rely upon X refreshing this state after the mode set has completed.
+ *
+ * The mode_config.mutex will be held for this call
+ */
+static void dove_drm_crtc_prepare(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+
+	mutex_lock(&dev->struct_mutex);
+	if (dcrtc->doverlay)
+		dove_drm_overlay_off(dev, dcrtc->doverlay);
+	mutex_unlock(&dev->struct_mutex);
+}
+
+/* The mode_config.mutex will be held for this call */
+static void dove_drm_crtc_commit(struct drm_crtc *crtc)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+
+	if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
+		dcrtc->dpms = DRM_MODE_DPMS_ON;
+		dove_drm_crtc_update(dcrtc);
+	}
+}
+
+/* The mode_config.mutex will be held for this call */
+static bool dove_drm_crtc_mode_fixup(struct drm_crtc *crtc,
+	const struct drm_display_mode *mode, struct drm_display_mode *adj)
+{
+	return true;
+}
+
+void dove_drm_crtc_irq(struct dove_crtc *dcrtc, u32 stat)
+{
+	struct dove_vbl_event *e, *n;
+	struct timeval now;
+
+	do_gettimeofday(&now);
+
+	if (stat & DMA_FF_UNDERFLOW)
+		DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
+	if (stat & GRA_FF_UNDERFLOW)
+		DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
+
+	drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
+
+	spin_lock(&dcrtc->irq_lock);
+
+	list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
+		list_del_init(&e->node);
+		drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
+		e->fn(dcrtc, e->data);
+	}
+
+	if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
+		void __iomem *base = dcrtc->base;
+		int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
+		uint32_t val;
+
+		writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
+		writel_relaxed(dcrtc->v[i].spu_v_h_total, base + LCD_SPUT_V_H_TOTAL);
+
+		val = readl_relaxed(base + LCD_SPU_ADV_REG);
+		val &= ~(0xfff << 20 | 0xfff);
+		val |= dcrtc->v[i].spu_adv_reg;
+		writel_relaxed(val, dcrtc->base + LCD_SPU_ADV_REG);
+	}
+	spin_unlock(&dcrtc->irq_lock);
+
+	/* Only on frame 0 IRQs (start of progressive / odd frame) */
+	if (stat & GRA_FRAME_IRQ0) {
+		struct drm_device *dev = dcrtc->crtc.dev;
+
+		spin_lock(&dev->event_lock);
+		if (dcrtc->flip)
+			dove_drm_crtc_complete_flip(dcrtc, &now);
+
+//		if (dcrtc->old_fb_obj) {
+//		}
+		spin_unlock(&dev->event_lock);
+
+		wake_up(&dcrtc->frame_wait);
+	}
+
+}
+
+/* These are locked by dev->vbl_lock */
+void dove_drm_crtc_disable_irq(struct dove_crtc *dcrtc, u32 mask)
+{
+	if (dcrtc->irq_ena & mask) {
+		dcrtc->irq_ena &= ~mask;
+		writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
+	}
+}
+
+void dove_drm_crtc_enable_irq(struct dove_crtc *dcrtc, u32 mask)
+{
+	if ((dcrtc->irq_ena & mask) != mask) {
+		dcrtc->irq_ena |= mask;
+		writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
+		if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
+			writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
+	}
+}
+
+/* The mode_config.mutex will be held for this call */
+static int dove_drm_crtc_mode_set(struct drm_crtc *crtc,
+	struct drm_display_mode *mode, struct drm_display_mode *adj,
+	int x, int y, struct drm_framebuffer *old_fb)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+	struct dove_regs regs[16];
+	uint32_t lm, rm, tm, bm, val, rate, ref, div;
+	unsigned long flags;
+	unsigned i;
+	bool interlaced;
+
+	drm_gem_object_reference(&drm_fb_obj(crtc->fb)->obj);
+
+	interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
+
+	i = dove_drm_crtc_calc_fb(dcrtc->crtc.fb, x, y, regs, interlaced);
+
+	rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
+	lm = adj->crtc_htotal - adj->crtc_hsync_end;
+	bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
+	tm = adj->crtc_vtotal - adj->crtc_vsync_end;
+
+	DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
+		adj->crtc_hdisplay,
+		adj->crtc_hsync_start,
+		adj->crtc_hsync_end,
+		adj->crtc_htotal, lm, rm);
+	DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
+		adj->crtc_vdisplay,
+		adj->crtc_vsync_start,
+		adj->crtc_vsync_end,
+		adj->crtc_vtotal, tm, bm);
+
+	/* Wait for pending flips to complete */
+	wait_event(dcrtc->frame_wait, !dcrtc->flip);
+
+	drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
+
+	crtc->mode = *adj;
+
+	val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
+	if (val != dcrtc->dumb_ctrl) {
+		dcrtc->dumb_ctrl = val;
+		writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
+	}
+
+	rate = adj->clock * 1000;
+	clk_set_rate(dcrtc->clk, rate);
+	ref = clk_get_rate(dcrtc->clk);
+	div = DIV_ROUND_UP(ref, rate);
+	if (div < 1)
+		div = 1;
+	dove_reg_queue_set(regs, i, div | dcrtc->cfg_sclk, LCD_CFG_SCLK_DIV);
+
+	if (interlaced ^ dcrtc->interlaced) {
+		if (adj->flags & DRM_MODE_FLAG_INTERLACE)
+			drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
+		else
+			drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
+		dcrtc->interlaced = interlaced;
+	}
+
+	spin_lock_irqsave(&dcrtc->irq_lock, flags);
+
+	/* Even interlaced/progressive frame */
+	dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
+				    adj->crtc_htotal;
+	dcrtc->v[1].spu_v_porch = tm << 16 | bm;
+	val = adj->crtc_hsync_start;
+	dcrtc->v[1].spu_adv_reg = val << 20 | val;
+
+	if (interlaced) {
+		/* Odd interlaced frame */
+		dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
+						(1 << 16);
+		dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
+		val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
+		dcrtc->v[0].spu_adv_reg = val << 20 | val;
+	} else {
+		dcrtc->v[0] = dcrtc->v[1];
+	}
+
+	val = (adj->crtc_vdisplay << 16) | adj->crtc_hdisplay;
+
+	dove_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
+	dove_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
+	dove_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
+	dove_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
+	dove_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
+	dove_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
+			   LCD_SPUT_V_H_TOTAL);
+	dove_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg | ADV_VSYNCOFFEN,
+			   (0xfff << 20 | 0xfff), LCD_SPU_ADV_REG);
+
+	val = dcrtc->cfg_dma_ctrl0;
+
+	switch (crtc->fb->pixel_format) {
+	case DRM_FORMAT_XRGB1555:
+	case DRM_FORMAT_ARGB1555:
+		val ^= CFG_GRA_SWAPRB;
+	case DRM_FORMAT_XBGR1555:
+	case DRM_FORMAT_ABGR1555:
+		val |= CFG_GRA_1555;
+		break;
+	case DRM_FORMAT_RGB565:
+		val ^= CFG_GRA_SWAPRB;
+	case DRM_FORMAT_BGR565:
+		val |= CFG_GRA_565;
+		break;
+	case DRM_FORMAT_RGB888:
+		val ^= CFG_GRA_SWAPRB;
+	case DRM_FORMAT_BGR888:
+		val |= CFG_GRA_888PACK;
+		break;
+	case DRM_FORMAT_XRGB8888:
+		val ^= CFG_GRA_SWAPRB;
+	case DRM_FORMAT_XBGR8888:
+		val |= CFG_GRA_X888;
+		break;
+	case DRM_FORMAT_ARGB8888:
+		val ^= CFG_GRA_SWAPRB;
+	case DRM_FORMAT_ABGR8888:
+		val |= CFG_GRA_8888;
+		break;
+	case DRM_FORMAT_C8:
+		val |= CFG_GRA_PSEUDO8 | CFG_PALETTE_ENA;
+		break;
+	}
+	if (interlaced)
+		val |= CFG_GRA_FTOGGLE;
+	dove_reg_queue_mod(regs, i, val, CFG_GRAFORMAT | CFG_GRA_SWAPRB |
+			   CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
+			   LCD_SPU_DMA_CTRL0);
+
+	val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
+	dove_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
+
+	/*
+	 * Set the colorimetry, based upon the HDMI spec.
+	 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others
+	 * use ITU601.  In any case, we select professional.
+	 */
+	if ((adj->hdisplay == 1280 && adj->vdisplay == 720 && !interlaced) ||
+	    (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
+		val = CFG_CSC_PROF | CFG_CSC_CCIR709;
+	} else {
+		val = CFG_CSC_PROF;
+	}
+	dove_reg_queue_mod(regs, i, val, CFG_CSC_MASK, LCD_SPU_IOPAD_CONTROL);
+	dove_reg_queue_end(regs, i);
+
+	dove_drm_crtc_update_regs(dcrtc, regs);
+	spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
+
+	dove_drm_crtc_update(dcrtc);
+
+	drm_vblank_post_modeset(crtc->dev, dcrtc->num);
+	dove_drm_crtc_finish_fb(dcrtc, old_fb, false);
+
+	return 0;
+}
+
+/* The mode_config.mutex will be held for this call */
+static int dove_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
+	struct drm_framebuffer *old_fb)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+	struct dove_regs regs[4];
+	unsigned i;
+
+	i = dove_drm_crtc_calc_fb(crtc->fb, crtc->x, crtc->y, regs, dcrtc->interlaced);
+	dove_reg_queue_end(regs, i);
+
+	/* Wait for pending flips to complete */
+	wait_event(dcrtc->frame_wait, !dcrtc->flip);
+
+	drm_gem_object_reference(&drm_fb_obj(crtc->fb)->obj);
+	dove_drm_crtc_update_regs(dcrtc, regs);
+	dove_drm_crtc_finish_fb(dcrtc, old_fb, false);
+
+	return 0;
+}
+
+static void dove_drm_crtc_load_lut(struct drm_crtc *crtc)
+{
+}
+
+/* The mode_config.mutex will be held for this call */
+static void dove_drm_crtc_disable(struct drm_crtc *crtc)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+
+	if (dcrtc->dpms != DRM_MODE_DPMS_OFF) {
+		dcrtc->dpms = DRM_MODE_DPMS_OFF;
+		dove_drm_crtc_update(dcrtc);
+	}
+	dove_drm_vblank_off(dcrtc);
+	dove_drm_crtc_finish_fb(dcrtc, crtc->fb, true);
+}
+
+static const struct drm_crtc_helper_funcs dove_crtc_helper_funcs = {
+	.dpms		= dove_drm_crtc_dpms,
+	.prepare	= dove_drm_crtc_prepare,
+	.commit		= dove_drm_crtc_commit,
+	.mode_fixup	= dove_drm_crtc_mode_fixup,
+	.mode_set	= dove_drm_crtc_mode_set,
+	.mode_set_base	= dove_drm_crtc_mode_set_base,
+	.load_lut	= dove_drm_crtc_load_lut,
+	.disable	= dove_drm_crtc_disable,
+};
+
+#ifdef CONFIG_DRM_DOVE_CURSOR
+static int dove_drm_crtc_cursor_update(struct dove_crtc *dcrtc, bool reload)
+{
+	uint32_t xoff, xscr, w = dcrtc->cursor_w, s = w;
+	uint32_t yoff, yscr, h = dcrtc->cursor_h;
+
+	/*
+	 * Calculate the visible width and height of the cursor,
+	 * screen position, and the position in the cursor bitmap.
+	 */
+	if (dcrtc->cursor_x < 0) {
+		xoff = -dcrtc->cursor_x;
+		xscr = 0;
+		w -= min(xoff, w);
+	} else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
+		xoff = 0;
+		xscr = dcrtc->cursor_x;
+		w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
+	} else {
+		xoff = 0;
+		xscr = dcrtc->cursor_x;
+	}
+
+	if (dcrtc->cursor_y < 0) {
+		yoff = -dcrtc->cursor_y;
+		yscr = 0;
+		h -= min(yoff, h);
+	} else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
+		yoff = 0;
+		yscr = dcrtc->cursor_y;
+		h = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_y, 0);
+	} else {
+		yoff = 0;
+		yscr = dcrtc->cursor_y;
+	}
+
+	if (dcrtc->interlaced) {
+		s *= 2;
+		yscr /= 2;
+		h /= 2;
+	}
+
+	if (!dcrtc->cursor_obj || !h || !w) {
+		spin_lock_irq(&dcrtc->irq_lock);
+		dove_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
+		spin_unlock_irq(&dcrtc->irq_lock);
+		return 0;
+	}
+
+	dove_updatel(CFG_CSB_256x32, CFG_PDWN256x32,
+		     dcrtc->base + LCD_SPU_SRAM_PARA1);
+
+	if (dcrtc->cursor_lw != w || dcrtc->cursor_lh != h || reload) {
+		struct dove_gem_object *obj = dcrtc->cursor_obj;
+		uint32_t *pix, *p, col2 = 0, col3 = 0;
+		unsigned x, y, d, n, a;
+
+		dcrtc->cursor_lw = w;
+		dcrtc->cursor_lh = h;
+
+		pix = phys_to_virt(obj->phys_addr);
+
+		/* Set the top-left corner of the cursor image */
+		pix += yoff * s + xoff;
+
+		a = 2 << 14 | 15 << 8;
+		for (d = n = y = 0; y < h; y++) {
+			for (x = 0, p = &pix[y * s]; x < w; x++, p++) {
+				uint32_t v = *p;
+				unsigned b;
+
+				if ((v & 0xff000000) != 0xff000000) {
+					b = 0;	/* transparent */
+				} else if (col2 == v) {
+					b = 2;	/* color 2 */
+				} else if (col3 == v) {
+					b = 3;	/* color 3 */
+				} else if (col2 == 0) {
+					col2 = v;
+					b = 2;	/* alloc color 2 */
+				} else if (col3 == 0) {
+					col3 = v;
+					b = 3;	/* alloc color 3 */
+				} else {
+					/* fail */
+					b = 1;	/* inverse (!) */
+				}
+
+				d |= b << n;
+				n += 2;
+
+				if (n == 32) {
+					writel_relaxed(d, dcrtc->base + LCD_SPU_SRAM_WRDAT);
+					writel_relaxed(a, dcrtc->base + LCD_SPU_SRAM_CTRL);
+					a++;
+					d = n = 0;
+				}
+			}
+		}
+
+		if (n) {
+			writel_relaxed(d, dcrtc->base + LCD_SPU_SRAM_WRDAT);
+			writel_relaxed(a, dcrtc->base + LCD_SPU_SRAM_CTRL);
+		}
+
+		writel_relaxed(col2, dcrtc->base + LCD_SPU_ALPHA_COLOR1);
+		writel_relaxed(col3, dcrtc->base + LCD_SPU_ALPHA_COLOR2);
+		writel_relaxed(h << 16 | w, dcrtc->base + LCD_SPU_HWC_HPXL_VLN);
+	}
+
+	writel_relaxed(yscr << 16 | xscr, dcrtc->base + LCD_SPU_HWC_OVSA_HPXL_VLN);
+
+	spin_lock_irq(&dcrtc->irq_lock);
+	dove_updatel(CFG_HWC_ENA,
+		     CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
+		     dcrtc->base + LCD_SPU_DMA_CTRL0);
+	spin_unlock_irq(&dcrtc->irq_lock);
+
+	return 0;
+}
+
+static void cursor_update(void *data)
+{
+	dove_drm_crtc_cursor_update(data, true);
+}
+
+static int dove_drm_crtc_cursor_set(struct drm_crtc *crtc,
+	struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
+{
+	struct drm_device *dev = crtc->dev;
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+	struct dove_gem_object *obj = NULL;
+	int ret;
+
+	if (handle && w > 0 && h > 0) {
+		/* maximum size is 64x64 */
+		if (w > 64 || h > 64)
+			return -ENOMEM;
+
+		obj = dove_gem_object_lookup(dev, file, handle);
+		if (!obj)
+			return -ENOENT;
+
+		/* Don't allow cursor to be in drm linear memory */
+		if (obj->linear) {
+			drm_gem_object_unreference_unlocked(&obj->obj);
+			return -EINVAL;
+		}
+
+		if (obj->obj.size < w * h * 4) {
+			DRM_ERROR("buffer is too small\n");
+			drm_gem_object_unreference_unlocked(&obj->obj);
+			return -ENOMEM;
+		}
+	}
+
+	mutex_lock(&dev->struct_mutex);
+	if (dcrtc->cursor_obj) {
+		dcrtc->cursor_obj->update = NULL;
+		dcrtc->cursor_obj->update_data = NULL;
+		drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
+	}
+	dcrtc->cursor_obj = obj;
+	dcrtc->cursor_w = w;
+	dcrtc->cursor_h = h;
+	ret = dove_drm_crtc_cursor_update(dcrtc, true);
+	if (obj) {
+		obj->update_data = dcrtc;
+		obj->update = cursor_update;
+	}
+	mutex_unlock(&dev->struct_mutex);
+
+	return ret;
+}
+
+static int dove_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+{
+	struct drm_device *dev = crtc->dev;
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+	int ret;
+
+	mutex_lock(&dev->struct_mutex);
+	dcrtc->cursor_x = x;
+	dcrtc->cursor_y = y;
+	ret = dove_drm_crtc_cursor_update(dcrtc, false);
+	mutex_unlock(&dev->struct_mutex);
+
+	return ret;
+}
+#else
+#define dove_drm_crtc_cursor_set NULL
+#define dove_drm_crtc_cursor_move NULL
+#endif
+
+static void dove_drm_crtc_destroy(struct drm_crtc *crtc)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+	struct dove_private *priv = crtc->dev->dev_private;
+
+	if (dcrtc->cursor_obj)
+		drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
+
+	priv->dcrtc[dcrtc->num] = NULL;
+	drm_crtc_cleanup(&dcrtc->crtc);
+	clk_disable_unprepare(dcrtc->clk);
+	clk_put(dcrtc->clk);
+	kfree(dcrtc);
+}
+
+/*
+ * The mode_config lock is held here, to prevent races between this
+ * and a mode_set.
+ */
+static int dove_drm_crtc_page_flip(struct drm_crtc *crtc,
+	struct drm_framebuffer *fb, struct drm_pending_vblank_event *event)
+{
+	struct dove_crtc *dcrtc = drm_to_dove_crtc(crtc);
+	struct dove_page_flip *flip;
+	struct drm_device *dev = crtc->dev;
+	struct drm_framebuffer *old_fb;
+	unsigned long flags;
+	unsigned i;
+	int ret;
+
+	/* We don't support changing the pixel format */
+	if (fb->pixel_format != crtc->fb->pixel_format)
+		return -EINVAL;
+
+	flip = kmalloc(sizeof(*flip), GFP_KERNEL);
+	if (!flip)
+		return -ENOMEM;
+
+	flip->event = event;
+	i = dove_drm_crtc_calc_fb(fb, crtc->x, crtc->y, flip->regs, dcrtc->interlaced);
+	dove_reg_queue_end(flip->regs, i);
+
+	ret = drm_vblank_get(dev, dcrtc->num);
+	if (ret) {
+		DRM_ERROR("failed to acquire vblank counter\n");
+		kfree(flip);
+		return ret;
+	}
+
+	drm_gem_object_reference(&drm_fb_obj(fb)->obj);
+
+	old_fb = dcrtc->crtc.fb;
+	dcrtc->crtc.fb = fb;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	if (!dcrtc->flip) {
+		dcrtc->flip = flip;
+	} else {
+		ret = -EBUSY;
+	}
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	if (ret) {
+		dcrtc->crtc.fb = old_fb;
+		drm_gem_object_unreference_unlocked(&drm_fb_obj(fb)->obj);
+		drm_vblank_put(dev, dcrtc->num);
+		kfree(flip);
+	} else {
+		dove_drm_crtc_finish_fb(dcrtc, old_fb, false);
+	}
+
+	return 0;
+}
+
+static struct drm_crtc_funcs dove_crtc_funcs = {
+	.cursor_set	= dove_drm_crtc_cursor_set,
+	.cursor_move	= dove_drm_crtc_cursor_move,
+	.destroy	= dove_drm_crtc_destroy,
+	.page_flip	= dove_drm_crtc_page_flip,
+	.set_config	= drm_crtc_helper_set_config,
+};
+
+int dove_drm_crtc_create(struct drm_device *dev, unsigned num,
+	struct resource *res, struct clk *clk)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct dove_crtc *dcrtc;
+	void __iomem *base;
+	int ret;
+
+	ret = clk_prepare_enable(clk);
+	if (ret) {
+		DRM_ERROR("clk would not prepare and enable\n");
+		return ret;
+	}
+
+	base = devm_request_and_ioremap(dev->dev, res);
+	if (!base) {
+		DRM_ERROR("failed to ioremap register\n");
+		clk_disable_unprepare(clk);
+		return -ENOMEM;
+	}
+
+	dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
+	if (!dcrtc) {
+		DRM_ERROR("failed to allocate dove crtc\n");
+		clk_disable_unprepare(clk);
+		return -ENOMEM;
+	}
+
+	dcrtc->base = base;
+	dcrtc->num = num;
+	dcrtc->clk = clk;
+	dcrtc->cfg_sclk = 0xc0000000;
+	dcrtc->cfg_dma_ctrl0 = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
+	dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
+	spin_lock_init(&dcrtc->irq_lock);
+	dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
+	INIT_LIST_HEAD(&dcrtc->vbl_list);
+	init_waitqueue_head(&dcrtc->frame_wait);
+
+	/* Initialize some registers which we don't otherwise set */
+	writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
+	writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
+	writel_relaxed(CFG_IOPAD_DUMB24, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
+	writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
+	writel_relaxed(0x0000e000, dcrtc->base + LCD_SPU_SRAM_PARA1);
+	writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
+	writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
+
+	/* Lower the watermark so to eliminate jitter at higher bandwidths */
+	dove_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
+
+	/* Ensure AXI pipeline is enabled */
+	dove_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
+
+	priv->dcrtc[dcrtc->num] = dcrtc;
+
+	drm_crtc_init(dev, &dcrtc->crtc, &dove_crtc_funcs);
+	drm_crtc_helper_add(&dcrtc->crtc, &dove_crtc_helper_funcs);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/dove/dove_crtc.h b/drivers/gpu/drm/dove/dove_crtc.h
new file mode 100644
index 0000000..766e7ea
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_crtc.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_CRTC_H
+#define DOVE_CRTC_H
+
+struct dove_overlay;
+struct dove_gem_object;
+
+struct dove_regs {
+	uint32_t offset;
+	uint32_t mask;
+	uint32_t val;
+};
+
+#define dove_reg_queue_mod(_r, _i, _v, _m, _o)	\
+	do {					\
+		struct dove_regs *__reg = _r;	\
+		__reg[_i].offset = _o;		\
+		__reg[_i].mask = ~(_m);		\
+		__reg[_i].val = _v;		\
+		_i++;				\
+	} while (0)
+
+#define dove_reg_queue_set(_r, _i, _v, _o)	\
+	dove_reg_queue_mod(_r, _i, _v, ~0, _o)
+
+#define dove_reg_queue_end(_r, _i)		\
+	dove_reg_queue_mod(_r, _i, 0, 0, ~0)
+
+struct dove_page_flip {
+	struct drm_pending_vblank_event *event;
+	struct dove_regs		regs[4];
+};
+
+struct dove_crtc {
+	struct drm_crtc		crtc;
+	unsigned		num;
+	void __iomem		*base;
+	struct clk		*clk;
+	struct {
+		uint32_t	spu_v_h_total;
+		uint32_t	spu_v_porch;
+		uint32_t	spu_adv_reg;
+	} v[2];
+	bool			interlaced;
+
+	struct dove_overlay	*doverlay;
+
+	struct dove_gem_object	*cursor_obj;
+	int			cursor_x;
+	int			cursor_y;
+	uint32_t		cursor_w;
+	uint32_t		cursor_h;
+	uint32_t		cursor_lw;
+	uint32_t		cursor_lh;
+
+	int			dpms;
+	uint32_t		cfg_sclk;
+	uint32_t		cfg_dma_ctrl0;
+	uint32_t		cfg_dumb_ctrl;
+	uint32_t		dumb_ctrl;
+
+	wait_queue_head_t	frame_wait;
+	struct dove_page_flip	*flip;
+	struct dove_page_flip	flip_pending;
+
+	spinlock_t		irq_lock;
+	uint32_t		irq_ena;
+	struct list_head	vbl_list;
+};
+#define drm_to_dove_crtc(c) container_of(c, struct dove_crtc, crtc)
+
+int dove_drm_crtc_create(struct drm_device *, unsigned, struct resource *,
+	struct clk *);
+void dove_drm_crtc_gamma_set(struct drm_crtc *, u16, u16, u16, int);
+void dove_drm_crtc_gamma_get(struct drm_crtc *, u16 *, u16 *, u16 *, int);
+void dove_drm_crtc_irq(struct dove_crtc *, u32);
+void dove_drm_crtc_disable_irq(struct dove_crtc *, u32);
+void dove_drm_crtc_enable_irq(struct dove_crtc *, u32);
+void dove_drm_crtc_update_regs(struct dove_crtc *, struct dove_regs *);
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_debugfs.c b/drivers/gpu/drm/dove/dove_debugfs.c
new file mode 100644
index 0000000..6cb1b1d
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_debugfs.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  Rewritten from the dovefb driver, and Armada510 manuals.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/ctype.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "dove_crtc.h"
+#include "dove_drm.h"
+
+static int dove_debugfs_gem_offs_show(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_gem_mm *mm = dev->mm_private;
+
+	return drm_mm_dump_table(m, &mm->offset_manager);
+}
+
+static int dove_debugfs_gem_linear_show(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = m->private;
+	struct dove_private *priv = node->minor->dev->dev_private;
+
+	return drm_mm_dump_table(m, &priv->linear);
+}
+
+static int dove_debugfs_reg_show(struct seq_file *m, void *data)
+{
+	struct drm_device *dev = m->private;
+	struct dove_private *priv = dev->dev_private;
+	int n, i;
+
+	if (priv) {
+		for (n = 0; n < ARRAY_SIZE(priv->dcrtc); n++) {
+			struct dove_crtc *dcrtc = priv->dcrtc[n];
+			if (!dcrtc)
+				continue;
+
+			for (i = 0x84; i <= 0x1c4; i += 4) {
+				uint32_t v = readl_relaxed(dcrtc->base + i);
+				seq_printf(m, "%u: 0x%04x: 0x%08x\n", n, i, v);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int dove_debugfs_reg_r_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dove_debugfs_reg_show, inode->i_private);
+}
+
+static const struct file_operations fops_reg_r = {
+	.owner = THIS_MODULE,
+	.open = dove_debugfs_reg_r_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int dove_debugfs_write(struct file *file, const char __user *ptr,
+	size_t len, loff_t *off)
+{
+	struct drm_device *dev = file->private_data;
+	struct dove_private *priv = dev->dev_private;
+	struct dove_crtc *dcrtc = priv->dcrtc[0];
+	char buf[32], *p;
+	uint32_t reg, val;
+	int ret;
+
+	if (*off != 0)
+		return 0;
+
+	if (len > sizeof(buf) - 1)
+		len = sizeof(buf) - 1;
+
+	ret = strncpy_from_user(buf, ptr, len);
+	if (ret < 0)
+		return ret;
+	buf[len] = '\0';
+
+	reg = simple_strtoul(buf, &p, 16);
+	if (!isspace(*p))
+		return -EINVAL;
+	val = simple_strtoul(p + 1, NULL, 16);
+
+	if (reg >= 0x84 && reg <= 0x1c4)
+		writel(val, dcrtc->base + reg);
+
+	return len;
+}
+
+static int dove_debugfs_reg_w_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations fops_reg_w = {
+	.owner = THIS_MODULE,
+	.open = dove_debugfs_reg_w_open,
+	.write = dove_debugfs_write,
+	.llseek = noop_llseek,
+};
+
+static struct drm_info_list dove_debugfs_list[] = {
+	{ "gem_linear", dove_debugfs_gem_linear_show, 0 },
+	{ "gem_offset", dove_debugfs_gem_offs_show, 0 },
+};
+#define DOVE_DEBUGFS_ENTRIES ARRAY_SIZE(dove_debugfs_list)
+
+static int drm_add_fake_info_node(struct drm_minor *minor, struct dentry *ent,
+	const void *key)
+{
+	struct drm_info_node *node;
+
+	node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
+	if (node == NULL) {
+		debugfs_remove(ent);
+		return -ENOMEM;
+	}
+
+	node->minor = minor;
+	node->dent = ent;
+	node->info_ent = (void *) key;
+
+	mutex_lock(&minor->debugfs_lock);
+	list_add(&node->list, &minor->debugfs_list);
+	mutex_unlock(&minor->debugfs_lock);
+
+	return 0;
+}
+
+static int dove_debugfs_create(struct dentry *root, struct drm_minor *minor,
+	const char *name, umode_t mode, const struct file_operations *fops)
+{
+	struct dentry *de;
+
+	de = debugfs_create_file(name, mode, root, minor->dev, fops);
+
+	return drm_add_fake_info_node(minor, de, fops);
+}
+
+int dove_drm_debugfs_init(struct drm_minor *minor)
+{
+	int ret;
+
+	ret = drm_debugfs_create_files(dove_debugfs_list, DOVE_DEBUGFS_ENTRIES,
+				       minor->debugfs_root, minor);
+	if (ret)
+		return ret;
+
+	ret = dove_debugfs_create(minor->debugfs_root, minor,
+				   "reg", S_IFREG | S_IRUSR, &fops_reg_r);
+	if (ret)
+		goto err_1;
+
+	ret = dove_debugfs_create(minor->debugfs_root, minor,
+				"reg_wr", S_IFREG | S_IWUSR, &fops_reg_w);
+	if (ret)
+		goto err_2;
+	return ret;
+
+ err_2:
+	drm_debugfs_remove_files((struct drm_info_list *) &fops_reg_r, 1, minor);
+ err_1:
+	drm_debugfs_remove_files(dove_debugfs_list, DOVE_DEBUGFS_ENTRIES,
+				 minor);
+	return ret;
+}
+
+void dove_drm_debugfs_cleanup(struct drm_minor *minor)
+{
+	drm_debugfs_remove_files((struct drm_info_list *) &fops_reg_w, 1, minor);
+	drm_debugfs_remove_files((struct drm_info_list *) &fops_reg_r, 1, minor);
+	drm_debugfs_remove_files(dove_debugfs_list, DOVE_DEBUGFS_ENTRIES,
+				 minor);
+}
diff --git a/drivers/gpu/drm/dove/dove_drm.h b/drivers/gpu/drm/dove/dove_drm.h
new file mode 100644
index 0000000..d00a9d6
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_drm.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_DRM_H
+#define DOVE_DRM_H
+
+struct dove_crtc;
+struct dove_gem_object;
+struct dove_overlay;
+struct clk;
+
+static inline uint32_t dove_pitch(uint32_t width, uint32_t bpp)
+{
+	uint32_t pitch = bpp != 4 ? width * ((bpp + 7) / 8) : width / 2;
+
+	/* 88AP510 spec recommends pitch be a multiple of 128 */
+	return ALIGN(pitch, 128);
+}
+
+struct dove_vbl_event {
+	struct list_head	node;
+	void			*data;
+	void			(*fn)(struct dove_crtc *, void *);
+};
+void dove_drm_vbl_event_add(struct dove_crtc *, struct dove_vbl_event *);
+void dove_drm_vbl_event_remove(struct dove_crtc *, struct dove_vbl_event *);
+void dove_drm_vbl_event_remove_unlocked(struct dove_crtc *, struct dove_vbl_event *);
+#define dove_drm_vbl_event_init(_e,_f,_d) do {	\
+	struct dove_vbl_event *__e = _e;	\
+	INIT_LIST_HEAD(&__e->node);		\
+	__e->data = _d;				\
+	__e->fn = _f;				\
+} while (0)
+
+
+struct dove_private {
+	struct drm_fb_helper	*fbdev;
+	struct dove_crtc	*dcrtc[2];
+	struct dove_overlay	*doverlay;
+	struct drm_mm		linear;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry		*de;
+#endif
+};
+
+extern const struct drm_mode_config_funcs dove_drm_mode_config_funcs;
+
+int dove_fbdev_init(struct drm_device *);
+void dove_fbdev_fini(struct drm_device *);
+
+int dove_overlay_create(struct drm_device *);
+void dove_overlay_destroy(struct drm_device *);
+void dove_drm_overlay_off(struct drm_device *, struct dove_overlay *);
+
+struct drm_connector *dove_drm_tda19988_create(struct drm_device *dev);
+
+int dove_drm_debugfs_init(struct drm_minor *);
+void dove_drm_debugfs_cleanup(struct drm_minor *);
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_drv.c b/drivers/gpu/drm/dove/dove_drv.c
new file mode 100644
index 0000000..98cb25f
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_drv.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/module.h>
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "dove_crtc.h"
+#include "dove_drm.h"
+#include "dove_gem.h"
+#include "dove_hw.h"
+#include "dove_ioctl.h"
+#include "dove_ioctlP.h"
+
+static int dove_drm_load(struct drm_device *dev, unsigned long flags)
+{
+	struct dove_private *priv;
+	struct resource *res[ARRAY_SIZE(priv->dcrtc)];
+	struct resource *mem = NULL;
+	int ret, n, i;
+
+	memset(res, 0, sizeof(res));
+
+	for (n = i = 0; ; n++) {
+		struct resource *r = platform_get_resource(dev->platformdev,
+							   IORESOURCE_MEM, n);
+		if (!r)
+			break;
+
+		if (resource_size(r) > SZ_4K)
+			mem = r;
+		else if (i < ARRAY_SIZE(priv->dcrtc))
+			res[i++] = r;
+		else
+			return -EINVAL;
+	}
+
+	if (!res[0] || !mem)
+		return -ENXIO;
+
+	if (!devm_request_mem_region(dev->dev, mem->start,
+			resource_size(mem), "dove-drm"))
+		return -EBUSY;
+
+	priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		DRM_ERROR("failed to allocate private\n");
+		ret = -ENOMEM;
+		goto err_buf;
+	}
+
+	dev->dev_private = priv;
+
+	/* Mode setting support */
+	drm_mode_config_init(dev);
+	dev->mode_config.min_width = 0;
+	dev->mode_config.min_height = 0;
+	dev->mode_config.max_width = 2048;
+	dev->mode_config.max_height = 2048;
+	dev->mode_config.preferred_depth = 24;
+	dev->mode_config.funcs = &dove_drm_mode_config_funcs;
+	drm_mm_init(&priv->linear, mem->start, resource_size(mem));
+
+	/* Create all LCD controllers */
+	for (n = 0; n < ARRAY_SIZE(priv->dcrtc); n++) {
+		struct clk *clk;
+
+		if (!res[n])
+			break;
+
+		clk = clk_get_sys("dovefb.0", "extclk");
+		if (IS_ERR(clk)) {
+			DRM_ERROR("failed to get clock\n");
+			ret = PTR_ERR(clk);
+			if (ret == -ENOENT)
+				ret = -EPROBE_DEFER;
+			goto err_kms;
+		}
+
+		ret = dove_drm_crtc_create(dev, n, res[n], clk);
+		if (ret) {
+			clk_put(clk);
+			goto err_kms;
+		}
+	}
+
+	ret = drm_vblank_init(dev, n);
+	if (ret)
+		goto err_kms;
+
+	ret = drm_irq_install(dev);
+	if (ret)
+		goto err_kms;
+
+	dev->vblank_disable_allowed = 1;
+
+	ret = dove_fbdev_init(dev);
+	if (ret)
+		goto err_irq;
+
+	ret = dove_overlay_create(dev);
+	if (ret)
+		goto err_irq;
+
+	drm_kms_helper_poll_init(dev);
+
+	return 0;
+
+ err_irq:
+	drm_irq_uninstall(dev);
+ err_kms:
+	drm_mode_config_cleanup(dev);
+	drm_mm_takedown(&priv->linear);
+ err_buf:
+
+	return ret;
+}
+
+static int dove_drm_unload(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+
+	drm_kms_helper_poll_fini(dev);
+	dove_overlay_destroy(dev);
+	dove_fbdev_fini(dev);
+	drm_irq_uninstall(dev);
+	drm_mode_config_cleanup(dev);
+	drm_mm_takedown(&priv->linear);
+	dev->dev_private = NULL;
+
+	return 0;
+}
+
+void dove_drm_vbl_event_add(struct dove_crtc *dcrtc, struct dove_vbl_event *evt)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dcrtc->irq_lock, flags);
+	if (list_empty(&evt->node)) {
+		list_add_tail(&evt->node, &dcrtc->vbl_list);
+
+		drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
+	}
+	spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
+}
+
+void dove_drm_vbl_event_remove(struct dove_crtc *dcrtc,
+	struct dove_vbl_event *evt)
+{
+	if (!list_empty(&evt->node)) {
+		list_del_init(&evt->node);
+		drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
+	}
+}
+
+void dove_drm_vbl_event_remove_unlocked(struct dove_crtc *dcrtc, struct dove_vbl_event *evt)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dcrtc->irq_lock, flags);
+	dove_drm_vbl_event_remove(dcrtc, evt);
+	spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
+}
+
+/* These are called under the vbl_lock. */
+static int dove_drm_enable_vblank(struct drm_device *dev, int crtc)
+{
+	struct dove_private *priv = dev->dev_private;
+	dove_drm_crtc_enable_irq(priv->dcrtc[crtc], VSYNC_IRQ_ENA);
+	return 0;
+}
+
+static void dove_drm_disable_vblank(struct drm_device *dev, int crtc)
+{
+	struct dove_private *priv = dev->dev_private;
+	dove_drm_crtc_disable_irq(priv->dcrtc[crtc], VSYNC_IRQ_ENA);
+}
+
+static irqreturn_t dove_drm_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = arg;
+	struct dove_private *priv = dev->dev_private;
+	struct dove_crtc *dcrtc = priv->dcrtc[0];
+	uint32_t v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
+
+	/*
+	 * This is rediculous - rather than writing bits to clear, we
+	 * have to set the actual status register value.  This is racy.
+	 */
+	writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
+
+	/* Mask out those interrupts we haven't enabled */
+	v = stat & dcrtc->irq_ena;
+
+	if (v & VSYNC_IRQ)
+		dove_drm_crtc_irq(dcrtc, stat);
+
+	return (stat & VSYNC_IRQ) ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static int dove_drm_irq_postinstall(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct dove_crtc *dcrtc = priv->dcrtc[0];
+
+	spin_lock_irq(&dev->vbl_lock);
+	writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
+	writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
+	spin_unlock_irq(&dev->vbl_lock);
+
+	return 0;
+}
+
+static void dove_drm_irq_uninstall(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct dove_crtc *dcrtc = priv->dcrtc[0];
+
+	writel(0, dcrtc->base + LCD_SPU_IRQ_ENA);
+}
+
+static struct drm_ioctl_desc dove_ioctls[] = {
+	DRM_IOCTL_DEF_DRV(DOVE_GEM_CREATE, dove_gem_create_ioctl, DRM_UNLOCKED),
+	DRM_IOCTL_DEF_DRV(DOVE_GEM_CREATE_PHYS, dove_gem_create_phys_ioctl, DRM_UNLOCKED),
+	DRM_IOCTL_DEF_DRV(DOVE_GEM_MMAP, dove_gem_mmap_ioctl, DRM_UNLOCKED),
+	DRM_IOCTL_DEF_DRV(DOVE_GEM_PROP, dove_gem_prop_ioctl, DRM_UNLOCKED),
+	DRM_IOCTL_DEF_DRV(DOVE_GEM_PWRITE, dove_gem_pwrite_ioctl, DRM_UNLOCKED),
+	DRM_IOCTL_DEF_DRV(DOVE_OVERLAY_PUT_IMAGE, dove_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+	DRM_IOCTL_DEF_DRV(DOVE_OVERLAY_ATTRS, dove_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+};
+
+static const struct file_operations dove_drm_fops = {
+	.owner			= THIS_MODULE,
+	.llseek			= no_llseek,
+	.read			= drm_read,
+	.poll			= drm_poll,
+	.unlocked_ioctl		= drm_ioctl,
+	.mmap			= drm_gem_mmap,
+	.open			= drm_open,
+	.release		= drm_release,
+	.fasync			= drm_fasync,
+};
+
+extern const struct vm_operations_struct dove_gem_vm_ops;
+
+static struct drm_driver dove_drm_driver = {
+	.load			= dove_drm_load,
+	.open			= NULL,
+	.preclose		= NULL,
+	.postclose		= NULL,
+	.lastclose		= NULL,
+	.unload			= dove_drm_unload,
+	.get_vblank_counter	= drm_vblank_count,
+	.enable_vblank		= dove_drm_enable_vblank,
+	.disable_vblank		= dove_drm_disable_vblank,
+	.irq_handler		= dove_drm_irq_handler,
+	.irq_postinstall	= dove_drm_irq_postinstall,
+	.irq_uninstall		= dove_drm_irq_uninstall,
+#ifdef CONFIG_DEBUG_FS
+	.debugfs_init		= dove_drm_debugfs_init,
+	.debugfs_cleanup	= dove_drm_debugfs_cleanup,
+#endif
+	.gem_init_object	= NULL,
+	.gem_free_object	= dove_gem_free_object,
+	.prime_handle_to_fd	= NULL,
+	.prime_fd_to_handle	= NULL,
+	.gem_prime_export	= NULL,
+	.gem_prime_import	= NULL,
+	.dumb_create		= dove_gem_dumb_create,
+	.dumb_map_offset	= dove_gem_dumb_map_offset,
+	.dumb_destroy		= dove_gem_dumb_destroy,
+	.gem_vm_ops		= &dove_gem_vm_ops,
+	.major			= 1,
+	.minor			= 0,
+	.name			= "dove-drm",
+	.desc			= "Dove SoC DRM",
+	.date			= "20120730",
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_HAVE_IRQ,
+	.ioctls			= dove_ioctls,
+	.fops			= &dove_drm_fops,
+};
+
+static int dove_drm_probe(struct platform_device *pdev)
+{
+	return drm_platform_init(&dove_drm_driver, pdev);
+}
+
+static int dove_drm_remove(struct platform_device *pdev)
+{
+	drm_platform_exit(&dove_drm_driver, pdev);
+	return 0;
+}
+
+static struct platform_driver dove_drm_platform_driver = {
+	.probe	= dove_drm_probe,
+	.remove	= dove_drm_remove,
+	.driver	= {
+		.owner	= THIS_MODULE,
+		.name	= "dove-drm",
+	},
+};
+
+static int __init dove_drm_init(void)
+{
+	dove_drm_driver.num_ioctls = DRM_ARRAY_SIZE(dove_ioctls);
+	return platform_driver_register(&dove_drm_platform_driver);
+}
+module_init(dove_drm_init);
+
+static void __exit dove_drm_exit(void)
+{
+	platform_driver_unregister(&dove_drm_platform_driver);
+}
+module_exit(dove_drm_exit);
+
+MODULE_AUTHOR("Russell King <rmk+kernel at arm.linux.org.uk>");
+MODULE_DESCRIPTION("Dove DRM Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dove-drm");
diff --git a/drivers/gpu/drm/dove/dove_fb.c b/drivers/gpu/drm/dove/dove_fb.c
new file mode 100644
index 0000000..1286b4b
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_fb.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "drm_fb_helper.h"
+#include "dove_drm.h"
+#include "dove_fb.h"
+#include "dove_gem.h"
+
+static void dove_fb_destroy(struct drm_framebuffer *fb)
+{
+	struct dove_framebuffer *dfb = drm_fb_to_dove_fb(fb);
+
+	drm_framebuffer_cleanup(&dfb->fb);
+	if (dfb->obj)
+		drm_gem_object_unreference_unlocked(&dfb->obj->obj);
+	kfree(dfb);
+}
+
+static int dove_fb_create_handle(struct drm_framebuffer *fb,
+	struct drm_file *dfile, unsigned int *handle)
+{
+	struct dove_framebuffer *dfb = drm_fb_to_dove_fb(fb);
+	return drm_gem_handle_create(dfile, &dfb->obj->obj, handle);
+}
+
+static const struct drm_framebuffer_funcs dove_fb_funcs = {
+	.destroy	= dove_fb_destroy,
+	.create_handle	= dove_fb_create_handle,
+};
+
+/*
+ * Supported pixel formats:
+ *		T	R	G	B	BPP
+ * RGB565 		[15:11] [10:5]	[4:0]	16	DRM_FORMAT_RGB565
+ * BGR565		[4:0]	[10:5]	[15:11]	16	DRM_FORMAT_BGR565
+ * RGB1555	15	[14:10]	[9:5]	[4:0]	16	DRM_FORMAT_ARGB1555
+ * BGR1555	15	[4:0]	[9:5]	[14:10]	16	DRM_FORMAT_ABGR1555
+ * RGB888PACK		[23:16]	[15:8]	[7:0]	24	DRM_FORMAT_RGB888
+ * BGR888PACK		[7:0]	[15:8]	[23:16]	24	DRM_FORMAT_BGR888
+ * RGB888UNPACK		[23:16]	[15:8]	[7:0]	32	DRM_FORMAT_XRGB8888
+ * BGR888UNPACK		[7:0]	[15:8]	[23:16]	32	DRM_FORMAT_XBGR8888
+ * RGBA888	[31:24]	[23:16]	[15:8]	[7:0]	32	DRM_FORMAT_ARGB8888
+ * BGRA888	[31:24]	[7:0]	[15:8]	[23:16]	32	DRM_FORMAT_ABGR8888
+ *
+ * We don't currently support (note that the YUV pixel fields
+ * are incorrect, coming from the dovefb driver):
+ *			Y	U	V	BPP
+ * YUV422PACK		[15:8]	[7:4]	[3:0]	16
+ * YVU422PACK		[7:0]	[11:8]	[15:12]	16
+ * YUV422PLANAR		[15:8]	[7:4]	[3:0]	16
+ * YVU422PLANAR		[7:0]	[11:8]	[15:12]	16
+ * YUV420PLANAR		[11:4]	[3:2]	[1:0]	12
+ * YVU420PLANAR		[7:0]	[9:8]	[11:10]	12
+ * PSEUDOCOLOR					8
+ * UYVY422PACK		[11:4]	[15:12]	[3:0]	16
+ */
+int dove_framebuffer_create(struct drm_device *dev,
+	struct dove_framebuffer **dfbp, struct drm_mode_fb_cmd2 *mode,
+	struct dove_gem_object *obj)
+{
+	struct dove_framebuffer *dfb;
+	int ret;
+
+	switch (mode->pixel_format) {
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_BGR565:
+	case DRM_FORMAT_ARGB1555:
+	case DRM_FORMAT_ABGR1555:
+	case DRM_FORMAT_RGB888:
+	case DRM_FORMAT_BGR888:
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_ABGR8888:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	dfb = kzalloc(sizeof(*dfb), GFP_KERNEL);
+	if (!dfb) {
+		DRM_ERROR("failed to allocate dove fb object\n");
+		return -ENOMEM;
+	}
+
+	ret = drm_framebuffer_init(dev, &dfb->fb, &dove_fb_funcs);
+	if (ret) {
+		kfree(dfb);
+		return ret;
+	}
+
+	drm_helper_mode_fill_fb_struct(&dfb->fb, mode);
+
+	/*
+	 * Take a reference on our object - the caller is expected
+	 * to drop their reference to it.
+	 */
+	drm_gem_object_reference(&obj->obj);
+	dfb->obj = obj;
+	*dfbp = dfb;
+
+	return 0;
+}
+
+static struct drm_framebuffer *dove_fb_create(struct drm_device *dev,
+	struct drm_file *dfile, struct drm_mode_fb_cmd2 *mode)
+{
+	struct dove_gem_object *obj;
+	struct dove_framebuffer *dfb;
+	int ret;
+
+	DRM_DEBUG_DRIVER("w%u h%u pf%08x f%u p%u,%u,%u\n",
+		mode->width, mode->height, mode->pixel_format,
+		mode->flags, mode->pitches[0], mode->pitches[1],
+		mode->pitches[2]);
+
+	/* We can only handle a single plane at the moment */
+	if (drm_format_num_planes(mode->pixel_format) > 1)
+		return ERR_PTR(-EINVAL);
+
+	obj = dove_gem_object_lookup(dev, dfile, mode->handles[0]);
+	if (!obj) {
+		DRM_ERROR("failed to lookup gem object\n");
+		return ERR_PTR(-ENOENT);
+	}
+
+	ret = dove_framebuffer_create(dev, &dfb, mode, obj);
+	drm_gem_object_unreference_unlocked(&obj->obj);
+
+	if (ret) {
+		DRM_ERROR("failed to initialize framebuffer\n");
+		return ERR_PTR(ret);
+	}
+
+	return &dfb->fb;
+}
+
+static void dove_output_poll_changed(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct drm_fb_helper *fbh = priv->fbdev;
+
+	if (fbh)
+		drm_fb_helper_hotplug_event(fbh);
+}
+
+const struct drm_mode_config_funcs dove_drm_mode_config_funcs = {
+	.fb_create		= dove_fb_create,
+	.output_poll_changed	= dove_output_poll_changed,
+};
diff --git a/drivers/gpu/drm/dove/dove_fb.h b/drivers/gpu/drm/dove/dove_fb.h
new file mode 100644
index 0000000..69eb274
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_fb.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_FB_H
+#define DOVE_FB_H
+
+struct dove_framebuffer {
+	struct drm_framebuffer	fb;
+	struct dove_gem_object	*obj;
+};
+#define drm_fb_to_dove_fb(dfb) container_of(dfb, struct dove_framebuffer, fb)
+#define drm_fb_obj(fb) drm_fb_to_dove_fb(fb)->obj
+
+int dove_framebuffer_create(struct drm_device *, struct dove_framebuffer **,
+	struct drm_mode_fb_cmd2 *, struct dove_gem_object *);
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_fbdev.c b/drivers/gpu/drm/dove/dove_fbdev.c
new file mode 100644
index 0000000..35b676c
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_fbdev.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  Written from the i915 driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "drmP.h"
+#include "drm_fb_helper.h"
+#include "dove_crtc.h"
+#include "dove_drm.h"
+#include "dove_fb.h"
+#include "dove_gem.h"
+
+static /*const*/ struct fb_ops dove_fb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_check_var	= drm_fb_helper_check_var,
+	.fb_set_par	= drm_fb_helper_set_par,
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+	.fb_pan_display	= drm_fb_helper_pan_display,
+	.fb_blank	= drm_fb_helper_blank,
+	.fb_setcmap	= drm_fb_helper_setcmap,
+	.fb_debug_enter	= drm_fb_helper_debug_enter,
+	.fb_debug_leave	= drm_fb_helper_debug_leave,
+};
+
+static int dove_fb_create(struct drm_fb_helper *fbh,
+	struct drm_fb_helper_surface_size *sizes)
+{
+	struct drm_device *dev = fbh->dev;
+	struct drm_mode_fb_cmd2 mode;
+	struct dove_framebuffer *dfb;
+	struct dove_gem_object *obj;
+	struct fb_info *info;
+	int size, ret;
+
+	memset(&mode, 0, sizeof(mode));
+	mode.width = sizes->surface_width;
+	mode.height = sizes->surface_height;
+	mode.pitches[0] = dove_pitch(mode.width, sizes->surface_bpp);
+	mode.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
+					sizes->surface_depth);
+
+	size = ALIGN(mode.pitches[0] * mode.height, PAGE_SIZE);
+	obj = dove_gem_alloc_private_object(dev, size);
+	if (!obj) {
+		DRM_ERROR("failed to allocate fb memory\n");
+		return -ENOMEM;
+	}
+
+	ret = dove_gem_linear_back(dev, obj);
+	if (ret) {
+		drm_gem_object_unreference_unlocked(&obj->obj);
+		return ret;
+	}
+
+	ret = dove_framebuffer_create(dev, &dfb, &mode, obj);
+	if (ret)
+		goto err_fbcreate;
+
+	mutex_lock(&dev->struct_mutex);
+
+	info = framebuffer_alloc(0, dev->dev);
+	if (!info) {
+		ret = -ENOMEM;
+		goto err_fballoc;
+	}
+
+	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+	if (ret) {
+		ret = -ENOMEM;
+		goto err_fbcmap;
+	}
+
+	strlcpy(info->fix.id, "dove-drmfb", sizeof(info->fix.id));
+	info->par = fbh;
+	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
+	info->fbops = &dove_fb_ops;
+	info->fix.smem_start = obj->phys_addr;
+	info->fix.smem_len = size;
+	info->screen_size = size;
+	info->screen_base = ioremap_wc(info->fix.smem_start, size);
+	if (!info->screen_base) {
+		ret = -ENOMEM;
+		goto err_ioremap;
+	}
+
+	fbh->fb = &dfb->fb;
+	fbh->fbdev = info;
+	drm_fb_helper_fill_fix(info, dfb->fb.pitches[0], dfb->fb.depth);
+	drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height);
+
+	DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08x\n",
+		dfb->fb.width, dfb->fb.height,
+		dfb->fb.bits_per_pixel, obj->phys_addr);
+
+	drm_gem_object_unreference(&obj->obj);
+	mutex_unlock(&dev->struct_mutex);
+
+	return 0;
+
+ err_ioremap:
+	fb_dealloc_cmap(&info->cmap);
+ err_fbcmap:
+	framebuffer_release(info);
+ err_fballoc:
+	mutex_unlock(&dev->struct_mutex);
+	dfb->fb.funcs->destroy(&dfb->fb);
+ err_fbcreate:
+	drm_gem_object_unreference_unlocked(&obj->obj);
+	return ret;
+}
+
+static void dove_fb_destroy(struct drm_fb_helper *fbh)
+{
+	struct fb_info *info = fbh->fbdev;
+
+	if (info) {
+		unregister_framebuffer(info);
+		iounmap(info->screen_base);
+		if (info->cmap.len)
+			fb_dealloc_cmap(&info->cmap);
+		framebuffer_release(info);
+	}
+
+	if (fbh->fb)
+		fbh->fb->funcs->destroy(fbh->fb);
+
+	drm_fb_helper_fini(fbh);
+}
+
+static int dove_fb_probe(struct drm_fb_helper *fbh,
+	struct drm_fb_helper_surface_size *sizes)
+{
+	int ret = 0;
+
+	if (!fbh->fb) {
+		ret = dove_fb_create(fbh, sizes);
+		if (ret == 0)
+			ret = 1;
+	}
+	return ret;
+}
+
+static struct drm_fb_helper_funcs dove_fb_helper_funcs = {
+	.gamma_set	= dove_drm_crtc_gamma_set,
+	.gamma_get	= dove_drm_crtc_gamma_get,
+	.fb_probe	= dove_fb_probe,
+};
+
+int dove_fbdev_init(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct drm_fb_helper *fbh;
+	int ret;
+
+	fbh = kzalloc(sizeof(*fbh), GFP_KERNEL);
+	if (!fbh)
+		return -ENOMEM;
+
+	priv->fbdev = fbh;
+
+	fbh->funcs = &dove_fb_helper_funcs;
+
+	ret = drm_fb_helper_init(dev, fbh, 1, 1);
+	if (ret) {
+		DRM_ERROR("failed to initialize drm fb helper\n");
+		goto err_fb_helper;
+	}
+
+	ret = drm_fb_helper_single_add_all_connectors(fbh);
+	if (ret) {
+		DRM_ERROR("failed to add fb connectors\n");
+		goto err_fb_setup;
+	}
+
+	ret = drm_fb_helper_initial_config(fbh, 32);
+	if (ret) {
+		DRM_ERROR("failed to set initial config\n");
+		goto err_fb_setup;
+	}
+
+	return 0;
+ err_fb_setup:
+	drm_fb_helper_fini(fbh);
+ err_fb_helper:
+	kfree(fbh);
+	priv->fbdev = NULL;
+	return ret;
+}
+
+void dove_fbdev_fini(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct drm_fb_helper *fbh = priv->fbdev;
+
+	if (fbh) {
+		dove_fb_destroy(fbh);
+		kfree(fbh);
+		priv->fbdev = NULL;
+	}
+}
diff --git a/drivers/gpu/drm/dove/dove_gem.c b/drivers/gpu/drm/dove/dove_gem.c
new file mode 100644
index 0000000..2aee511
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_gem.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/shmem_fs.h>
+#include "drmP.h"
+#include "dove_drm.h"
+#include "dove_gem.h"
+#include "dove_ioctl.h"
+#include "dove_ioctlP.h"
+
+static int dove_gem_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+	struct dove_gem_object *obj = drm_to_dove_gem(vma->vm_private_data);
+	unsigned long addr = (unsigned long)vmf->virtual_address;
+	unsigned long pfn = obj->phys_addr >> PAGE_SHIFT;
+	int ret;
+
+	pfn += (addr - vma->vm_start) >> PAGE_SHIFT;
+	ret = vm_insert_pfn(vma, addr, pfn);
+
+	switch (ret) {
+	case -EIO:
+	case -EAGAIN:
+		set_need_resched();
+	case 0:
+	case -ERESTARTSYS:
+	case -EINTR:
+		return VM_FAULT_NOPAGE;
+	case -ENOMEM:
+		return VM_FAULT_OOM;
+	default:
+		return VM_FAULT_SIGBUS;
+	}
+}
+
+const struct vm_operations_struct dove_gem_vm_ops = {
+	.fault	= dove_gem_vm_fault,
+	.open	= drm_gem_vm_open,
+	.close	= drm_gem_vm_close,
+};
+
+static size_t roundup_gem_size(size_t size)
+{
+	return roundup(size, PAGE_SIZE);
+}
+
+void dove_gem_free_object(struct drm_gem_object *obj)
+{
+	struct dove_gem_object *dobj = drm_to_dove_gem(obj);
+
+	DRM_DEBUG_DRIVER("release obj %p\n", dobj);
+
+	if (dobj->linear)
+		drm_mm_put_block(dobj->linear);
+
+	if (dobj->obj.map_list.map)
+		drm_gem_free_mmap_offset(&dobj->obj);
+
+	if (dobj->page) {
+		unsigned int order = get_order(dobj->obj.size);
+		__free_pages(dobj->page, order);
+	}
+
+	drm_gem_object_release(&dobj->obj);
+
+	kfree(dobj);
+}
+
+int dove_gem_linear_back(struct drm_device *dev, struct dove_gem_object *obj)
+{
+	struct dove_private *priv = dev->dev_private;
+	size_t size = obj->obj.size;
+
+	if (obj->page || obj->linear)
+		return 0;
+
+	/* If it is a small allocation, try to get it from the system */
+	if (size < 1048576) {
+		unsigned int order = get_order(size);
+		struct page *p = alloc_pages(GFP_KERNEL, order);
+
+		if (p) {
+			unsigned sz = (size + 31) & ~31;
+			uintptr_t ptr;
+
+			obj->phys_addr = page_to_phys(p);
+			obj->dev_addr = obj->phys_addr;
+
+			/* FIXME: Hack around dirty cache */
+			ptr = (uintptr_t)phys_to_virt(obj->phys_addr);
+			memset((void *)ptr, 0, PAGE_ALIGN(size));
+			while (sz) {
+				asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (ptr));
+				ptr += 32;
+				sz -= 32;
+			}
+			dsb();
+
+			obj->page = p;
+		}
+	}
+
+	/* Otherwise, grab it from our linear allocation */
+	if (!obj->page) {
+		struct drm_mm_node *free;
+		unsigned align = min_t(unsigned, size, SZ_2M);
+		void __iomem *ptr;
+
+		free = drm_mm_search_free(&priv->linear, size, align, 0);
+		if (free)
+			obj->linear = drm_mm_get_block(free, size, align);
+		if (!obj->linear)
+			return -ENOSPC;
+
+		/* Ensure that the memory we're returning is cleared. */
+		ptr = ioremap_wc(obj->linear->start, size);
+		if (!ptr) {
+			drm_mm_put_block(obj->linear);
+			obj->linear = NULL;
+			return -ENOMEM;
+		}
+
+		memset_io(ptr, 0, size);
+		iounmap(ptr);
+
+		obj->phys_addr = obj->linear->start;
+		obj->dev_addr = obj->linear->start;
+	}
+
+	DRM_DEBUG_DRIVER("obj %p phys %#x dev %#x\n",
+			 obj, obj->phys_addr, obj->dev_addr);
+
+	return 0;
+}
+
+struct dove_gem_object *dove_gem_alloc_private_object(struct drm_device *dev,
+	size_t size)
+{
+	struct dove_gem_object *obj;
+
+	size = roundup_gem_size(size);
+
+	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+	if (!obj)
+		return NULL;
+
+	if (drm_gem_private_object_init(dev, &obj->obj, size)) {
+		kfree(obj);
+		return NULL;
+	}
+
+	DRM_DEBUG_DRIVER("alloc private obj %p size %zu\n", obj, size);
+
+	return obj;
+}
+
+struct dove_gem_object *dove_gem_alloc_object(struct drm_device *dev,
+	size_t size)
+{
+	struct dove_gem_object *obj;
+	struct address_space *mapping;
+
+	size = roundup_gem_size(size);
+
+	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+	if (!obj)
+		return NULL;
+
+	if (drm_gem_object_init(dev, &obj->obj, size)) {
+		kfree(obj);
+		return NULL;
+	}
+
+	mapping = obj->obj.filp->f_path.dentry->d_inode->i_mapping;
+	mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
+
+	DRM_DEBUG_DRIVER("alloc obj %p size %zu\n", obj, size);
+
+	return obj;
+}
+
+/* Dumb alloc support */
+int dove_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
+	struct drm_mode_create_dumb *args)
+{
+	struct dove_gem_object *dobj;
+	u32 handle;
+	size_t size;
+	int ret;
+
+	args->pitch = dove_pitch(args->width, args->bpp);
+	args->size = size = args->pitch * args->height;
+
+	dobj = dove_gem_alloc_private_object(dev, size);
+	if (dobj == NULL)
+		return -ENOMEM;
+
+	ret = dove_gem_linear_back(dev, dobj);
+	if (ret)
+		goto err;
+
+	ret = drm_gem_handle_create(file, &dobj->obj, &handle);
+	if (ret)
+		goto err;
+
+	args->handle = handle;
+
+	/* drop reference from allocate - handle holds it now */
+	DRM_DEBUG_DRIVER("obj %p size %zu handle %#x\n", dobj, size, handle);
+ err:
+	drm_gem_object_unreference_unlocked(&dobj->obj);
+	return ret;
+}
+
+int dove_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
+	uint32_t handle, uint64_t *offset)
+{
+	struct dove_gem_object *obj;
+	int ret = 0;
+
+	mutex_lock(&dev->struct_mutex);
+	obj = dove_gem_object_lookup(dev, file, handle);
+	if (!obj) {
+		DRM_ERROR("failed to lookup gem object\n");
+		ret = -EINVAL;
+		goto err_unlock;
+	}
+
+	if (!obj->obj.map_list.map)
+		ret = drm_gem_create_mmap_offset(&obj->obj);
+
+	if (ret == 0) {
+		*offset = (u64)obj->obj.map_list.hash.key << PAGE_SHIFT;
+		DRM_DEBUG_DRIVER("handle %#x offset %llx\n", handle, *offset);
+	}
+
+	drm_gem_object_unreference(&obj->obj);
+ err_unlock:
+	mutex_unlock(&dev->struct_mutex);
+
+	return ret;
+}
+
+int dove_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
+	uint32_t handle)
+{
+	return drm_gem_handle_delete(file, handle);
+}
+
+/* Private driver gem ioctls */
+int dove_gem_create_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_gem_create *args = data;
+	struct dove_gem_object *dobj;
+	size_t size;
+	u32 handle;
+	int ret;
+
+	if (args->size == 0) {
+		args->pitch = dove_pitch(args->width, args->bpp);
+		args->size = size = args->pitch * args->height;
+	} else {
+		size = args->size;
+	}
+
+	dobj = dove_gem_alloc_object(dev, size);
+	if (dobj == NULL)
+		return -ENOMEM;
+
+	ret = drm_gem_handle_create(file, &dobj->obj, &handle);
+	if (ret)
+		goto err;
+
+	args->handle = handle;
+
+	/* drop reference from allocate - handle holds it now */
+	DRM_DEBUG_DRIVER("obj %p size %zu handle %#x\n", dobj, size, handle);
+ err:
+	drm_gem_object_unreference_unlocked(&dobj->obj);
+	return ret;
+}
+
+int dove_gem_create_phys_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_gem_create_phys *arg = data;
+	struct dove_gem_object *dobj;
+	u32 handle;
+	int ret;
+
+	dobj = dove_gem_alloc_private_object(dev, arg->size);
+	if (dobj) {
+		dobj->phys_addr = arg->phys;
+		dobj->dev_addr = arg->phys;
+	}
+
+	ret = drm_gem_handle_create(file, &dobj->obj, &handle);
+	if (ret) {
+		drm_gem_object_release(&dobj->obj);
+		return ret;
+	}
+
+	/* drop reference from allocate - handle holds it now */
+	drm_gem_object_unreference(&dobj->obj);
+
+	arg->handle = handle;
+
+	return 0;
+}
+
+/* Map a shmem-backed object into process memory space */
+int dove_gem_mmap_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_gem_mmap *args = data;
+	struct dove_gem_object *dobj;
+	unsigned long addr;
+
+	dobj = dove_gem_object_lookup(dev, file, args->handle);
+	if (dobj == NULL)
+		return -ENOENT;
+
+	if (!dobj->obj.filp) {
+		drm_gem_object_unreference(&dobj->obj);
+		return -EINVAL;
+	}
+
+	addr = vm_mmap(dobj->obj.filp, 0, args->size, PROT_READ | PROT_WRITE,
+	               MAP_SHARED, args->offset);
+	drm_gem_object_unreference(&dobj->obj);
+	if (IS_ERR_VALUE(addr))
+		return addr;
+
+	args->addr = addr;
+
+	return 0;
+}
+
+int dove_gem_prop_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_gem_prop *arg = data;
+	struct dove_gem_object *dobj;
+	int ret;
+
+	ret = mutex_lock_interruptible(&dev->struct_mutex);
+	if (ret)
+		return ret;
+
+	dobj = dove_gem_object_lookup(dev, file, arg->handle);
+	if (dobj == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+
+	arg->phys = dobj->phys_addr;
+	ret = 0;
+	drm_gem_object_unreference(&dobj->obj);
+
+ unlock:
+	mutex_unlock(&dev->struct_mutex);
+
+	return ret;
+}
+
+int dove_gem_pwrite_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_gem_pwrite *args = data;
+	struct dove_gem_object *dobj;
+	char __user *ptr;
+	int ret;
+
+	DRM_DEBUG_DRIVER("handle %u off %u size %u ptr 0x%llx\n",
+		args->handle, args->offset, args->size, args->ptr);
+
+	if (args->size == 0)
+		return 0;
+
+	ptr = (char __user *)(uintptr_t)args->ptr;
+
+	if (!access_ok(VERIFY_READ, ptr, args->size))
+		return -EFAULT;
+
+	ret = fault_in_multipages_readable(ptr, args->size);
+	if (ret)
+		return ret;
+
+	dobj = dove_gem_object_lookup(dev, file, args->handle);
+	if (dobj == NULL)
+		return -ENOENT;
+
+	/* Don't allow pwrite to drm linear backed objects */
+	if (dobj->linear)
+		return -EINVAL;
+
+	if (args->offset > dobj->obj.size ||
+	    args->size > dobj->obj.size - args->offset) {
+		DRM_ERROR("invalid size: object size %u\n", dobj->obj.size);
+		ret = -EINVAL;
+		goto unref;
+	}
+
+	{
+		void *data = phys_to_virt(dobj->phys_addr) + args->offset;
+		ret = copy_from_user(data, ptr, args->size) ? -EFAULT : 0;
+
+		if (ret == 0 && dobj->update)
+			dobj->update(dobj->update_data);
+	}
+
+  unref:
+	drm_gem_object_unreference_unlocked(&dobj->obj);
+	return ret;
+}
diff --git a/drivers/gpu/drm/dove/dove_gem.h b/drivers/gpu/drm/dove/dove_gem.h
new file mode 100644
index 0000000..324f23d
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_gem.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_GEM_H
+#define DOVE_GEM_H
+
+/* GEM */
+struct dove_gem_object {
+	struct drm_gem_object	obj;
+	struct drm_mm_node	*linear;
+	phys_addr_t		phys_addr;
+	resource_size_t		dev_addr;
+	struct page		*page;
+	void			(*update)(void *);
+	void			*update_data;
+};
+
+#define drm_to_dove_gem(o) container_of(o, struct dove_gem_object, obj)
+
+void dove_gem_free_object(struct drm_gem_object *);
+int dove_gem_linear_back(struct drm_device *, struct dove_gem_object *);
+struct dove_gem_object *dove_gem_alloc_private_object(struct drm_device *, size_t);
+int dove_gem_dumb_create(struct drm_file *, struct drm_device *,
+	struct drm_mode_create_dumb *);
+int dove_gem_dumb_map_offset(struct drm_file *, struct drm_device *,
+	uint32_t, uint64_t *);
+int dove_gem_dumb_destroy(struct drm_file *, struct drm_device *,
+	uint32_t);
+
+static inline struct dove_gem_object *dove_gem_object_lookup(
+	struct drm_device *dev, struct drm_file *dfile, unsigned handle)
+{
+	struct drm_gem_object *obj = drm_gem_object_lookup(dev, dfile, handle);
+
+	return obj ? drm_to_dove_gem(obj) : NULL;
+}
+#endif
diff --git a/drivers/gpu/drm/dove/dove_hw.h b/drivers/gpu/drm/dove/dove_hw.h
new file mode 100644
index 0000000..91e022f
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_hw.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  Rewritten from the dovefb driver, and Armada510 manuals.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_HW_H
+#define DOVE_HW_H
+
+/*
+ * Note: the following registers are written from IRQ context:
+ *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
+ *  LCD_SPU_DMA_START_ADDR_[YUV][01], LCD_SPU_DMA_PITCH_YC,
+ *  LCD_SPU_DMA_PITCH_UV, LCD_SPU_DMA_OVSA_HPXL_VLN,
+ *  LCD_SPU_DMA_HPXL_VLN, LCD_SPU_DZM_HPXL_VLN, LCD_SPU_DMA_CTRL0
+ */
+enum {
+	LCD_SPU_ADV_REG			= 0x0084,
+	LCD_SPU_DMA_START_ADDR_Y0	= 0x00c0,
+	LCD_SPU_DMA_START_ADDR_U0	= 0x00c4,
+	LCD_SPU_DMA_START_ADDR_V0	= 0x00c8,
+	LCD_CFG_DMA_START_ADDR_0	= 0x00cc,
+	LCD_SPU_DMA_START_ADDR_Y1	= 0x00d0,
+	LCD_SPU_DMA_START_ADDR_U1	= 0x00d4,
+	LCD_SPU_DMA_START_ADDR_V1	= 0x00d8,
+	LCD_CFG_DMA_START_ADDR_1	= 0x00dc,
+	LCD_SPU_DMA_PITCH_YC		= 0x00e0,
+	LCD_SPU_DMA_PITCH_UV		= 0x00e4,
+	LCD_SPU_DMA_OVSA_HPXL_VLN	= 0x00e8,
+	LCD_SPU_DMA_HPXL_VLN		= 0x00ec,
+	LCD_SPU_DZM_HPXL_VLN		= 0x00f0,
+	LCD_CFG_GRA_START_ADDR0		= 0x00f4,
+	LCD_CFG_GRA_START_ADDR1		= 0x00f8,
+	LCD_CFG_GRA_PITCH		= 0x00fc,
+	LCD_SPU_GRA_OVSA_HPXL_VLN	= 0x0100,
+	LCD_SPU_GRA_HPXL_VLN		= 0x0104,
+	LCD_SPU_GZM_HPXL_VLN		= 0x0108,
+	LCD_SPU_HWC_OVSA_HPXL_VLN	= 0x010c,
+	LCD_SPU_HWC_HPXL_VLN		= 0x0110,
+	LCD_SPUT_V_H_TOTAL		= 0x0114,
+	LCD_SPU_V_H_ACTIVE		= 0x0118,
+	LCD_SPU_H_PORCH			= 0x011c,
+	LCD_SPU_V_PORCH			= 0x0120,
+	LCD_SPU_BLANKCOLOR		= 0x0124,
+	LCD_SPU_ALPHA_COLOR1		= 0x0128,
+	LCD_SPU_ALPHA_COLOR2		= 0x012c,
+	LCD_SPU_COLORKEY_Y		= 0x0130,
+	LCD_SPU_COLORKEY_U		= 0x0134,
+	LCD_SPU_COLORKEY_V		= 0x0138,
+	LCD_CFG_RDREG4F			= 0x013c,
+	LCD_SPU_SPI_RXDATA		= 0x0140,
+	LCD_SPU_ISA_RSDATA		= 0x0144,
+	LCD_SPU_HWC_RDDAT		= 0x0158,
+	LCD_SPU_GAMMA_RDDAT		= 0x015c,
+	LCD_SPU_PALETTE_RDDAT		= 0x0160,
+	LCD_SPU_IOPAD_IN		= 0x0178,
+	LCD_CFG_RDREG5F			= 0x017c,
+	LCD_SPU_SPI_CTRL		= 0x0180,
+	LCD_SPU_SPI_TXDATA		= 0x0184,
+	LCD_SPU_SMPN_CTRL		= 0x0188,
+	LCD_SPU_DMA_CTRL0		= 0x0190,
+	LCD_SPU_DMA_CTRL1		= 0x0194,
+	LCD_SPU_SRAM_CTRL		= 0x0198,
+	LCD_SPU_SRAM_WRDAT		= 0x019c,
+	LCD_SPU_SRAM_PARA0		= 0x01a0,
+	LCD_SPU_SRAM_PARA1		= 0x01a4,
+	LCD_CFG_SCLK_DIV		= 0x01a8,
+	LCD_SPU_CONTRAST		= 0x01ac,
+	LCD_SPU_SATURATION		= 0x01b0,
+	LCD_SPU_CBSH_HUE		= 0x01b4,
+	LCD_SPU_DUMB_CTRL		= 0x01b8,
+	LCD_SPU_IOPAD_CONTROL		= 0x01bc,
+	LCD_SPU_IRQ_ENA			= 0x01c0,
+	LCD_SPU_IRQ_ISR			= 0x01c4,
+};
+
+/* For LCD_SPU_ADV_REG */
+enum {
+	ADV_VSYNC_L_OFF	= 0xfff << 20,
+	ADV_GRACOLORKEY	= 1 << 19,
+	ADV_VIDCOLORKEY	= 1 << 18,
+	ADV_HWC32BLEND	= 1 << 15,
+	ADV_HWC32ARGB	= 1 << 14,
+	ADV_HWC32ENABLE	= 1 << 13,
+	ADV_VSYNCOFFEN	= 1 << 12,
+	ADV_VSYNC_H_OFF	= 0xfff << 0,
+};
+
+/* For LCD_SPU_DMA_CTRL0 */
+enum {
+	CFG_NOBLENDING	= 1 << 31,
+	CFG_GAMMA_ENA	= 1 << 30,
+	CFG_CBSH_ENA	= 1 << 29,
+	CFG_PALETTE_ENA	= 1 << 28,
+	CFG_ARBFAST_ENA	= 1 << 27,
+	CFG_HWC_1BITMOD	= 1 << 26,
+	CFG_HWC_1BITENA	= 1 << 25,
+	CFG_HWC_ENA	= 1 << 24,
+	CFG_DMAFORMAT	= 0xf << 20,
+	CFG_DMA_565	= 0x0 << 20,
+	CFG_DMA_1555	= 0x1 << 20,
+	CFG_DMA_888PACK	= 0x2 << 20,
+	CFG_DMA_X888	= 0x3 << 20,
+	CFG_DMA_8888	= 0x4 << 20,
+	CFG_DMA_422PACK	= 0x5 << 20,
+	CFG_DMA_422	= 0x6 << 20,
+	CFG_DMA_420	= 0x7 << 20,
+	CFG_DMA_PSEUDO4	= 0x9 << 20,
+	CFG_DMA_PSEUDO8	= 0xa << 20,
+	CFG_GRAFORMAT	= 0xf << 16,
+	CFG_GRA_565	= 0x0 << 16,
+	CFG_GRA_1555	= 0x1 << 16,
+	CFG_GRA_888PACK	= 0x2 << 16,
+	CFG_GRA_X888	= 0x3 << 16,
+	CFG_GRA_8888	= 0x4 << 16,
+	CFG_GRA_422PACK	= 0x5 << 16,
+	CFG_GRA_422	= 0x6 << 16,
+	CFG_GRA_420	= 0x7 << 16,
+	CFG_GRA_PSEUDO4	= 0x9 << 16,
+	CFG_GRA_PSEUDO8	= 0xa << 16,
+	CFG_GRA_FTOGGLE	= 1 << 15,
+	CFG_GRA_HSMOOTH	= 1 << 14,
+	CFG_GRA_TSTMODE	= 1 << 13,
+	CFG_GRA_SWAPRB	= 1 << 12,
+	CFG_GRA_SWAPUV	= 1 << 11,
+	CFG_GRA_SWAPYU	= 1 << 10,
+	CFG_YUV2RGB_GRA	= 1 << 9,
+	CFG_GRA_ENA	= 1 << 8,
+	CFG_DMA_FTOGGLE	= 1 << 7,
+	CFG_DMA_HSMOOTH	= 1 << 6,
+	CFG_DMA_TSTMODE	= 1 << 5,
+	CFG_DMA_SWAPRB	= 1 << 4,
+	CFG_DMA_SWAPUV	= 1 << 3,
+	CFG_DMA_SWAPYU	= 1 << 2,
+	CFG_YUV2RGB_DMA	= 1 << 1,
+	CFG_DMA_ENA	= 1 << 0,
+};
+
+/* For LCD_SPU_DMA_CTRL1 */
+enum {
+	CFG_FRAME_TRIG	= 1 << 31,
+	CFG_VSYNC_INV	= 1 << 27,
+	CFG_CKMODE_MASK	= 0x7 << 24,
+	CFG_CKMODE_DIS	= 0x0 << 24,
+	CFG_CKMODE_Y	= 0x1 << 24,
+	CFG_CKMODE_U	= 0x2 << 24,
+	CFG_CKMODE_RGB	= 0x3 << 24,
+	CFG_CKMODE_V	= 0x4 << 24,
+	CFG_CKMODE_R	= 0x5 << 24,
+	CFG_CKMODE_G	= 0x6 << 24,
+	CFG_CKMODE_B	= 0x7 << 24,
+	CFG_CARRY	= 1 << 23,
+	CFG_GATED_CLK	= 1 << 21,
+	CFG_PWRDN_ENA	= 1 << 20,
+	CFG_DSCALE_MASK	= 0x3 << 18,
+	CFG_DSCALE_NONE	= 0x0 << 18,
+	CFG_DSCALE_HALF	= 0x1 << 18,
+	CFG_DSCALE_QUAR = 0x2 << 18,
+	CFG_ALPHAM_MASK	= 0x3 << 16,
+	CFG_ALPHAM_VIDEO= 0x0 << 16,
+	CFG_ALPHAM_GRA	= 0x1 << 16,
+	CFG_ALPHAM_CFG	= 0x2 << 16,
+	CFG_ALPHA_MASK	= 0xff << 8,
+	CFG_PIXCMD_MASK	= 0xff,
+};
+
+/* For LCD_SPU_SRAM_PARA1 */
+enum {
+	CFG_CSB_256x32	= 1 << 15,
+	CFG_CSB_256x24	= 1 << 14,
+	CFG_CSB_256x8	= 1 << 13,
+	CFG_PDWN256x32	= 1 << 7,
+	CFG_PDWN256x24	= 1 << 6,
+	CFG_PDWN256x8	= 1 << 5,
+	CFG_PDWN32x32	= 1 << 3,
+	CFG_PDWN16x66	= 1 << 2,
+	CFG_PDWN32x66	= 1 << 1,
+	CFG_PDWN64x66	= 1 << 0,
+};
+
+/* For LCD_SPU_DUMB_CTRL */
+enum {
+	DUMB16_RGB565_0	= 0x0 << 28,
+	DUMB16_RGB565_1	= 0x1 << 28,
+	DUMB18_RGB666_0	= 0x2 << 28,
+	DUMB18_RGB666_1	= 0x3 << 28,
+	DUMB12_RGB444_0	= 0x4 << 28,
+	DUMB12_RGB444_1	= 0x5 << 28,
+	DUMB24_RGB888_0	= 0x6 << 28,
+	DUMB_BLANK	= 0x7 << 28,
+	DUMB_MASK	= 0xf << 28,
+	CFG_BIAS_OUT	= 1 << 8,
+	CFG_REV_RGB	= 1 << 7,
+	CFG_INV_CBLANK	= 1 << 6,
+	CFG_INV_CSYNC	= 1 << 5,
+	CFG_INV_HENA	= 1 << 4,
+	CFG_INV_VSYNC	= 1 << 3,
+	CFG_INV_HSYNC	= 1 << 2,
+	CFG_INV_PCLK	= 1 << 1,
+	CFG_DUMB_ENA	= 1 << 0,
+};
+
+/* For LCD_SPU_IOPAD_CONTROL */
+enum {
+	CFG_VSCALE_LN_EN	= 3 << 18,
+	CFG_GRA_VM_ENA		= 1 << 15,
+	CFG_DMA_VM_ENA		= 1 << 13,
+	CFG_CMD_VM_ENA		= 1 << 11,
+	CFG_CSC_MASK		= 3 << 8,
+	CFG_CSC_CCIR709		= 1 << 9,
+	CFG_CSC_PROF		= 1 << 8,
+	CFG_IOPAD_MASK		= 0xf << 0,
+	CFG_IOPAD_DUMB24	= 0x0 << 0,
+	CFG_IOPAD_DUMB18SPI	= 0x1 << 0,
+	CFG_IOPAD_DUMB18GPIO	= 0x2 << 0,
+	CFG_IOPAD_DUMB16SPI	= 0x3 << 0,
+	CFG_IOPAD_DUMB16GPIO	= 0x4 << 0,
+	CFG_IOPAD_DUMB12GPIO	= 0x5 << 0,
+	CFG_IOPAD_SMART18	= 0x6 << 0,
+	CFG_IOPAD_SMART16	= 0x7 << 0,
+	CFG_IOPAD_SMART8	= 0x8 << 0,
+};
+
+#define IOPAD_DUMB24                0x0
+
+/* For LCD_SPU_IRQ_ENA */
+enum {
+	DMA_FRAME_IRQ0_ENA	= 1 << 31,
+	DMA_FRAME_IRQ1_ENA	= 1 << 30,
+	DMA_FRAME_IRQ_ENA	= DMA_FRAME_IRQ0_ENA | DMA_FRAME_IRQ1_ENA,
+	DMA_FF_UNDERFLOW_ENA	= 1 << 29,
+	GRA_FRAME_IRQ0_ENA	= 1 << 27,
+	GRA_FRAME_IRQ1_ENA	= 1 << 26,
+	GRA_FRAME_IRQ_ENA	= GRA_FRAME_IRQ0_ENA | GRA_FRAME_IRQ1_ENA,
+	GRA_FF_UNDERFLOW_ENA	= 1 << 25,
+	VSYNC_IRQ_ENA		= 1 << 23,
+	DUMB_FRAMEDONE_ENA	= 1 << 22,
+	TWC_FRAMEDONE_ENA	= 1 << 21,
+	HWC_FRAMEDONE_ENA	= 1 << 20,
+	SLV_IRQ_ENA		= 1 << 19,
+	SPI_IRQ_ENA		= 1 << 18,
+	PWRDN_IRQ_ENA		= 1 << 17,
+	ERR_IRQ_ENA		= 1 << 16,
+	CLEAN_SPU_IRQ_ISR	= 0xffff,
+};
+
+/* For LCD_SPU_IRQ_ISR */
+enum {
+	DMA_FRAME_IRQ0		= 1 << 31,
+	DMA_FRAME_IRQ1		= 1 << 30,
+	DMA_FRAME_IRQ		= DMA_FRAME_IRQ0 | DMA_FRAME_IRQ1,
+	DMA_FF_UNDERFLOW	= 1 << 29,
+	GRA_FRAME_IRQ0		= 1 << 27,
+	GRA_FRAME_IRQ1		= 1 << 26,
+	GRA_FRAME_IRQ		= GRA_FRAME_IRQ0 | GRA_FRAME_IRQ1,
+	GRA_FF_UNDERFLOW	= 1 << 25,
+	VSYNC_IRQ		= 1 << 23,
+	DUMB_FRAMEDONE		= 1 << 22,
+	TWC_FRAMEDONE		= 1 << 21,
+	HWC_FRAMEDONE		= 1 << 20,
+	SLV_IRQ			= 1 << 19,
+	SPI_IRQ			= 1 << 18,
+	PWRDN_IRQ		= 1 << 17,
+	ERR_IRQ			= 1 << 16,
+	DMA_FRAME_IRQ0_LEVEL	= 1 << 15,
+	DMA_FRAME_IRQ1_LEVEL	= 1 << 14,
+	DMA_FRAME_CNT_ISR	= 3 << 12,
+	GRA_FRAME_IRQ0_LEVEL	= 1 << 11,
+	GRA_FRAME_IRQ1_LEVEL	= 1 << 10,
+	GRA_FRAME_CNT_ISR	= 3 << 8,
+	VSYNC_IRQ_LEVEL		= 1 << 7,
+	DUMB_FRAMEDONE_LEVEL	= 1 << 6,
+	TWC_FRAMEDONE_LEVEL	= 1 << 5,
+	HWC_FRAMEDONE_LEVEL	= 1 << 4,
+	SLV_FF_EMPTY		= 1 << 3,
+	DMA_FF_ALLEMPTY		= 1 << 2,
+	GRA_FF_ALLEMPTY		= 1 << 1,
+	PWRDN_IRQ_LEVEL		= 1 << 0,
+};
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_ioctl.h b/drivers/gpu/drm/dove/dove_ioctl.h
new file mode 100644
index 0000000..c1dcbaa
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_ioctl.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  With inspiration from the i915 driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DRM_DOVE_IOCTL_H
+#define DRM_DOVE_IOCTL_H
+
+#define DRM_DOVE_GEM_CREATE		0x00
+#define DRM_DOVE_GEM_CREATE_PHYS	0x01
+#define DRM_DOVE_GEM_MMAP		0x02
+#define DRM_DOVE_GEM_PWRITE		0x03
+#define DRM_DOVE_GEM_PROP		0x04
+#define DRM_DOVE_OVERLAY_PUT_IMAGE	0x06
+#define DRM_DOVE_OVERLAY_ATTRS		0x07
+
+#define DOVE_IOCTL(dir,name,str) \
+	DRM_##dir(DRM_COMMAND_BASE + DRM_DOVE_##name, struct drm_dove_##str)
+
+struct drm_dove_gem_create {
+	uint32_t height;
+	uint32_t width;
+	uint32_t bpp;
+	uint32_t handle;
+	uint32_t pitch;
+	uint32_t size;
+};
+#define DRM_IOCTL_DOVE_GEM_CREATE \
+	DOVE_IOCTL(IOWR, GEM_CREATE, gem_create)
+
+struct drm_dove_gem_create_phys {
+	uint32_t size;
+	uint32_t handle;
+	uint64_t phys;
+};
+#define DRM_IOCTL_DOVE_GEM_CREATE_PHYS \
+	DOVE_IOCTL(IOWR, GEM_CREATE_PHYS, gem_create_phys)
+
+struct drm_dove_gem_mmap {
+	uint32_t handle;
+	uint32_t pad;
+	uint64_t offset;
+	uint64_t size;
+	uint64_t addr;
+};
+#define DRM_IOCTL_DOVE_GEM_MMAP \
+	DOVE_IOCTL(IOWR, GEM_MMAP, gem_mmap)
+
+struct drm_dove_gem_pwrite {
+	uint32_t handle;
+	uint32_t offset;
+	uint32_t size;
+	uint64_t ptr;
+};
+#define DRM_IOCTL_DOVE_GEM_PWRITE \
+	DOVE_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
+
+struct drm_dove_gem_prop {
+	uint64_t phys;
+	uint32_t handle;
+};
+#define DRM_IOCTL_DOVE_GEM_PROP \
+	DOVE_IOCTL(IOWR, GEM_PROP, gem_prop)
+
+/* Same as Intel I915 */
+struct drm_dove_overlay_put_image {
+	uint32_t flags;
+#define DOVE_OVERLAY_TYPE_MASK          0x000000ff
+#define DOVE_OVERLAY_YUV_PLANAR         0x00000001
+#define DOVE_OVERLAY_YUV_PACKED         0x00000002
+#define DOVE_OVERLAY_RGB                0x00000003
+#define DOVE_OVERLAY_DEPTH_MASK		0x0000ff00
+#define DOVE_OVERLAY_RGB24		0x00001000
+#define DOVE_OVERLAY_RGB16		0x00002000
+#define DOVE_OVERLAY_RGB15		0x00003000
+#define DOVE_OVERLAY_YUV422		0x00000100
+#define DOVE_OVERLAY_YUV411		0x00000200
+#define DOVE_OVERLAY_YUV420		0x00000300
+#define DOVE_OVERLAY_YUV410		0x00000400
+#define DOVE_OVERLAY_SWAP_MASK		0x00ff0000
+#define DOVE_OVERLAY_NO_SWAP		0x00000000
+#define DOVE_OVERLAY_UV_SWAP		0x00010000
+#define DOVE_OVERLAY_Y_SWAP		0x00020000
+#define DOVE_OVERLAY_Y_AND_UV_SWAP	0x00030000
+#define DOVE_OVERLAY_FLAGS_MASK		0xff000000
+#define DOVE_OVERLAY_ENABLE		0x01000000
+	uint32_t bo_handle;
+	uint16_t stride_Y;
+	uint16_t stride_UV;
+	uint32_t offset_Y;
+	uint32_t offset_U;
+	uint32_t offset_V;
+	uint16_t src_width;
+	uint16_t src_height;
+	uint16_t src_scan_width;
+	uint16_t src_scan_height;
+	uint32_t crtc_id;
+	uint16_t dst_x;
+	uint16_t dst_y;
+	uint16_t dst_width;
+	uint16_t dst_height;
+};
+#define DRM_IOCTL_DOVE_OVERLAY_PUT_IMAGE \
+	DOVE_IOCTL(IOW, OVERLAY_PUT_IMAGE, overlay_put_image)
+
+/* Same as Intel I915 */
+struct drm_dove_overlay_attrs {
+	uint32_t flags;
+#define DOVE_OVERLAY_UPDATE_ATTRS	(1<<0)
+#define DOVE_OVERLAY_UPDATE_GAMMA	(1<<1)
+	uint32_t color_key;
+	int32_t brightness;
+	uint32_t contrast;
+	uint32_t saturation;
+	uint32_t gamma0;
+	uint32_t gamma1;
+	uint32_t gamma2;
+	uint32_t gamma3;
+	uint32_t gamma4;
+	uint32_t gamma5;
+};
+#define DRM_IOCTL_DOVE_OVERLAY_ATTRS \
+	DOVE_IOCTL(IOWR, OVERLAY_ATTRS, overlay_attrs)
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_ioctlP.h b/drivers/gpu/drm/dove/dove_ioctlP.h
new file mode 100644
index 0000000..7791b55
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_ioctlP.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_IOCTLP_H
+#define DOVE_IOCTLP_H
+
+#define DOVE_IOCTL_PROTO(name)\
+extern int dove_##name##_ioctl(struct drm_device *, void *, struct drm_file *)
+
+DOVE_IOCTL_PROTO(gem_create);
+DOVE_IOCTL_PROTO(gem_create_phys);
+DOVE_IOCTL_PROTO(gem_mmap);
+DOVE_IOCTL_PROTO(gem_prop);
+DOVE_IOCTL_PROTO(gem_pwrite);
+DOVE_IOCTL_PROTO(overlay_put_image);
+DOVE_IOCTL_PROTO(overlay_attrs);
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_output.c b/drivers/gpu/drm/dove/dove_output.c
new file mode 100644
index 0000000..7cd7d35
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_output.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "drm_edid.h"
+#include "drm_helper.h"
+#include "dove_output.h"
+#include "dove_drm.h"
+
+struct dove_connector {
+	struct drm_connector conn;
+	const struct dove_output_type *type;
+};
+
+#define drm_to_dove_conn(c) container_of(c, struct dove_connector, conn)
+
+struct drm_encoder *dove_drm_connector_best_encoder(struct drm_connector *conn)
+{
+	uint32_t id = conn->encoder_ids[0];
+
+	return id ? drm_encoder_find(conn->dev, id) : NULL;
+}
+
+static enum drm_connector_status dove_drm_connector_detect(
+	struct drm_connector *conn, bool force)
+{
+	struct dove_connector *dconn = drm_to_dove_conn(conn);
+
+	return dconn->type->detect(conn, force);
+}
+
+static void dove_drm_connector_destroy(struct drm_connector *conn)
+{
+	struct dove_connector *dconn = drm_to_dove_conn(conn);
+
+	drm_sysfs_connector_remove(conn);
+	drm_connector_cleanup(conn);
+	kfree(dconn);
+}
+
+static int dove_drm_connector_set_property(struct drm_connector *conn,
+	struct drm_property *property, uint64_t value)
+{
+	struct dove_connector *dconn = drm_to_dove_conn(conn);
+
+	if (!dconn->type->set_property)
+		return -EINVAL;
+
+	return dconn->type->set_property(conn, property, value);
+}
+
+static const struct drm_connector_funcs dove_drm_conn_funcs = {
+	.dpms		= drm_helper_connector_dpms,
+	.fill_modes	= drm_helper_probe_single_connector_modes,
+	.detect		= dove_drm_connector_detect,
+	.destroy	= dove_drm_connector_destroy,
+	.set_property	= dove_drm_connector_set_property,
+};
+
+void dove_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct drm_encoder_helper_funcs *funcs = encoder->helper_private;
+
+	funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+void dove_drm_encoder_commit(struct drm_encoder *encoder)
+{
+	struct drm_encoder_helper_funcs *funcs = encoder->helper_private;
+
+	funcs->dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+struct drm_connector *dove_output_create(struct drm_device *dev,
+	const struct dove_output_type *type)
+{
+	struct dove_connector *dconn;
+	struct drm_encoder *enc;
+	int ret;
+
+	dconn = kzalloc(sizeof(*dconn), GFP_KERNEL);
+	if (!dconn)
+		return NULL;
+
+	dconn->conn.interlace_allowed = true;
+	dconn->conn.polled = type->polled;
+	dconn->type = type;
+
+	ret = drm_connector_init(dev, &dconn->conn, &dove_drm_conn_funcs,
+				 type->connector_type);
+	if (ret) {
+		DRM_ERROR("unable to init connector\n");
+		goto err_destroy_dconn;
+	}
+
+	ret = type->create(&dconn->conn, &enc);
+	if (ret)
+		goto err_conn;
+
+	ret = drm_sysfs_connector_add(&dconn->conn);
+	if (ret)
+		goto err_sysfs;
+
+	ret = drm_mode_connector_attach_encoder(&dconn->conn, enc);
+	if (ret)
+		goto err_attach;
+
+	return &dconn->conn;
+
+ err_attach:
+	drm_sysfs_connector_remove(&dconn->conn);
+ err_sysfs:
+	enc->funcs->destroy(enc);
+ err_conn:
+	drm_connector_cleanup(&dconn->conn);
+ err_destroy_dconn:
+	kfree(dconn);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/dove/dove_output.h b/drivers/gpu/drm/dove/dove_output.h
new file mode 100644
index 0000000..1b12890
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_output.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DOVE_CONNETOR_H
+#define DOVE_CONNETOR_H
+
+struct dove_output_type {
+	int connector_type;
+	int polled;
+	enum drm_connector_status (*detect)(struct drm_connector *, bool);
+	int (*create)(struct drm_connector *, struct drm_encoder **);
+	int (*set_property)(struct drm_connector *, struct drm_property *, uint64_t);
+};
+
+struct drm_encoder *dove_drm_connector_best_encoder(struct drm_connector *conn);
+void dove_drm_encoder_prepare(struct drm_encoder *encoder);
+void dove_drm_encoder_commit(struct drm_encoder *encoder);
+
+struct drm_connector *dove_output_create(struct drm_device *dev,
+	const struct dove_output_type *);
+
+#endif
diff --git a/drivers/gpu/drm/dove/dove_overlay.c b/drivers/gpu/drm/dove/dove_overlay.c
new file mode 100644
index 0000000..39c081b
--- /dev/null
+++ b/drivers/gpu/drm/dove/dove_overlay.c
@@ -0,0 +1,514 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  Rewritten from the dovefb driver, and Armada510 manuals.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "drmP.h"
+#include "drm_helper.h"
+#include "dove_crtc.h"
+#include "dove_drm.h"
+#include "dove_gem.h"
+#include "dove_hw.h"
+#include "dove_ioctl.h"
+#include "dove_ioctlP.h"
+
+struct dove_overlay {
+	struct dove_gem_object *obj;
+	struct dove_gem_object *old_obj;
+	struct dove_crtc *dcrtc;
+	uint32_t crtc_id;
+	uint32_t cached_flags;
+	uint32_t cached_cfg;
+
+	uint32_t stride_yc;
+	uint32_t stride_uv;
+	uint32_t dst_yx;
+	uint32_t src_hw;
+	uint32_t dst_hw;
+	uint32_t cfg;
+
+	uint32_t color_key;
+	int32_t brightness;
+	uint32_t contrast;
+	uint32_t saturation;
+
+	struct dove_vbl_event vbl_update;
+
+	struct dove_regs update[13];
+
+	wait_queue_head_t vbl_wait;
+};
+
+static void dove_updatel(uint32_t val, uint32_t mask, void __iomem *ptr)
+{
+	uint32_t ov, v;
+
+	ov = v = readl_relaxed(ptr);
+	v = (v & ~mask) | val;
+	if (ov != v)
+		writel_relaxed(v, ptr);
+}
+
+static void dove_ovl_update(struct dove_crtc *dcrtc, void *data)
+{
+	struct dove_overlay *ovl = container_of(data, struct dove_overlay, update);
+	dove_drm_crtc_update_regs(dcrtc, data);
+	wake_up(&ovl->vbl_wait);
+}
+
+static void dove_ovl_update_attr(struct dove_overlay *ovl)
+{
+	struct dove_crtc *dcrtc = ovl->dcrtc;
+	uint32_t key = ovl->color_key;
+        uint32_t r, g, b;
+
+        r = (key & 0x0000ff);
+        g = (key & 0x00ff00) >> 8;
+        b = (key & 0xff0000) >> 16;
+
+	writel_relaxed(r << 8 | r << 16 | r << 24, dcrtc->base + LCD_SPU_COLORKEY_Y);
+	writel_relaxed(g << 8 | g << 16 | g << 24, dcrtc->base + LCD_SPU_COLORKEY_U);
+	writel_relaxed(b << 8 | b << 16 | b << 24, dcrtc->base + LCD_SPU_COLORKEY_V);
+
+	writel_relaxed(0x00004000, dcrtc->base + LCD_SPU_CONTRAST);
+	writel_relaxed(0x40000000, dcrtc->base + LCD_SPU_SATURATION);
+	writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
+
+	spin_lock_irq(&dcrtc->irq_lock);
+	dove_updatel(CFG_CKMODE_RGB | CFG_ALPHAM_GRA,
+		     CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
+		     dcrtc->base + LCD_SPU_DMA_CTRL1);
+
+	dove_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
+	spin_unlock_irq(&dcrtc->irq_lock);
+}
+
+static int dove_check_planar(struct drm_dove_overlay_put_image *args,
+	struct dove_gem_object *obj)
+{
+	uint32_t tmp;
+
+	DRM_DEBUG_DRIVER("stride Y%#x UV%#x offset Y%#x U%#x V%#x obj %#x\n",
+		args->stride_Y, args->stride_UV,
+		args->offset_Y, args->offset_U, args->offset_V,
+		obj->obj.size);
+
+	if (args->src_scan_width     > args->stride_Y ||
+	    args->src_scan_width / 2 > args->stride_UV)
+		return -EINVAL;
+
+	tmp = args->stride_Y * args->src_height;
+	if (tmp > obj->obj.size ||
+	    args->offset_Y > obj->obj.size - tmp)
+		return -EINVAL;
+
+	tmp = args->stride_UV * args->src_height;
+	if (tmp > obj->obj.size ||
+	    args->offset_U > obj->obj.size - tmp ||
+	    args->offset_V > obj->obj.size - tmp)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int dove_check_packed(struct drm_dove_overlay_put_image *args,
+	struct dove_gem_object *obj)
+{
+	uint32_t tmp = args->stride_Y * args->src_height;
+
+	if (args->src_scan_width * 2 > args->stride_Y ||
+	    tmp > obj->obj.size ||
+	    args->offset_Y > obj->obj.size - tmp)
+		return -EINVAL;
+
+	return 0;
+}
+
+static struct dove_crtc *dove_crtc_lookup(struct drm_device *dev, uint32_t id)
+{
+	struct drm_crtc *crtc = drm_crtc_find(dev, id);
+	return crtc ? drm_to_dove_crtc(crtc) : NULL;
+}
+
+static void dove_ovl_release_old(struct dove_overlay *ovl)
+{
+	if (ovl->old_obj) {
+		drm_gem_object_unreference(&ovl->old_obj->obj);
+		ovl->old_obj = NULL;
+	}
+}
+
+/*
+ * This should be called with both dev->struct_mutex and
+ * the mode_config mutexes held.
+ */
+void dove_drm_overlay_off(struct drm_device *dev, struct dove_overlay *ovl)
+{
+	struct dove_crtc *dcrtc = ovl->dcrtc;
+
+	ovl->cfg = 0;
+
+	if (dcrtc) {
+		/* Disable overlay */
+		dove_drm_vbl_event_remove_unlocked(dcrtc, &ovl->vbl_update);
+
+		spin_lock_irq(&dcrtc->irq_lock);
+		dove_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
+		spin_unlock_irq(&dcrtc->irq_lock);
+
+		ovl->dcrtc->doverlay = NULL;
+		ovl->dcrtc = NULL;
+		ovl->crtc_id = ~0;
+	}
+
+	dove_ovl_release_old(ovl);
+
+	if (ovl->obj) {
+		drm_gem_object_unreference(&ovl->obj->obj);
+		ovl->obj = NULL;
+	}
+}
+
+static int dove_ovl_check_dst(const struct drm_dove_overlay_put_image *args,
+	const struct drm_display_mode *mode)
+{
+	if (args->dst_x < mode->hdisplay &&
+	    args->dst_width <= mode->hdisplay - args->dst_x &&
+	    args->dst_y < mode->vdisplay &&
+	    args->dst_height <= mode->vdisplay - args->dst_y)
+		return 0;
+	return -EINVAL;
+}
+
+static int dove_ovl_compute_cfg(struct dove_overlay *ovl, uint32_t flags)
+{
+	uint32_t cfg = CFG_DMA_HSMOOTH | CFG_CBSH_ENA;
+
+	switch (flags & DOVE_OVERLAY_TYPE_MASK) {
+	case DOVE_OVERLAY_YUV_PLANAR:
+		switch (flags & DOVE_OVERLAY_DEPTH_MASK) {
+		case DOVE_OVERLAY_YUV422:	/* Planar YUV422 */
+			cfg |= CFG_DMA_422;
+			break;
+		case DOVE_OVERLAY_YUV420:	/* Planar YUV420 */
+			cfg |= CFG_DMA_420;
+			break;
+		default:
+			DRM_ERROR("bad planar depth\n");
+			return -EINVAL;
+		}
+		/* Planar formats have no swaps */
+		if (flags & DOVE_OVERLAY_SWAP_MASK) {
+			DRM_ERROR("planar and requested swap\n");
+			return -EINVAL;
+		}
+		cfg |= CFG_YUV2RGB_DMA;
+		break;
+
+	case DOVE_OVERLAY_YUV_PACKED:
+		switch (flags & DOVE_OVERLAY_DEPTH_MASK) {
+		case DOVE_OVERLAY_YUV422:
+			cfg |= CFG_DMA_422PACK;
+			break;
+		default:
+			DRM_ERROR("bad packed depth\n");
+			return -EINVAL;
+		}
+		if (flags & (DOVE_OVERLAY_SWAP_MASK & ~DOVE_OVERLAY_Y_AND_UV_SWAP)) {
+			DRM_ERROR("bad overlay swap\n");
+			return -EINVAL;
+		}
+		/*
+		 *                            [0:7] [8:15] [16:23] [24:31]
+		 * 0:			YUY2:   Y     U       Y       V
+		 * UV_SWAP:		YVYU:   Y     V       Y       U
+		 * Y_SWAP:		UYVY:   U     Y       V       Y
+		 * Y_SWAP | UV_SWAP:	VYUY:   V     Y       U       Y
+		 *
+		 * Default ordering in memory:  U     Y0      V       Y1
+		 *
+		 * Image fourcc 59565955 UYVY flags 01020102 -> correct
+		 * Image fourcc 32595559 YUY2 flags 01000102 -> wrong U/V swapped
+		 */
+		if (flags & DOVE_OVERLAY_UV_SWAP)
+			cfg |= CFG_DMA_SWAPUV;
+		if (!(flags & DOVE_OVERLAY_Y_SWAP))
+			cfg ^= CFG_DMA_SWAPYU | CFG_DMA_SWAPUV;
+		cfg |= CFG_YUV2RGB_DMA;
+		break;
+
+	case DOVE_OVERLAY_RGB:
+		switch (flags & DOVE_OVERLAY_DEPTH_MASK) {
+		case DOVE_OVERLAY_RGB24:	/* 3 byte RGB */
+			cfg |= CFG_DMA_888PACK;
+			break;
+		case DOVE_OVERLAY_RGB16:        /* 2 byte RGB */
+			cfg |= CFG_DMA_565;
+			break;
+		case DOVE_OVERLAY_RGB15:        /* 2 byte RGB */
+			cfg |= CFG_DMA_1555;
+			break;
+		default:
+			DRM_ERROR("bad RGB depth\n");
+			return -EINVAL;
+		}
+		/* Planar formats have no swaps */
+		if (flags & DOVE_OVERLAY_SWAP_MASK) {
+			DRM_ERROR("RGB and requested swap\n");
+			return -EINVAL;
+		}
+		break;
+
+	default:
+		DRM_ERROR("bad overlay type\n");
+		return -EINVAL;
+	}
+
+	cfg |= CFG_DMA_ENA;
+
+	ovl->cached_flags = flags;
+	ovl->cached_cfg = cfg;
+	return 0;
+}
+
+int dove_overlay_put_image_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_overlay_put_image *args = data;
+	struct dove_private *priv = dev->dev_private;
+	struct dove_overlay *ovl = priv->doverlay;
+	struct dove_gem_object *obj;
+	struct dove_crtc *dcrtc;
+	uint32_t stride_uv, stride_yc, src_hw, dst_hw, dst_yx;
+	bool planar = false;
+	int ret, idx;
+
+	if (!ovl) {
+		DRM_DEBUG_DRIVER("no overlay");
+		return -ENODEV;
+	}
+
+	if (!(args->flags & DOVE_OVERLAY_ENABLE)) {
+		mutex_lock(&dev->mode_config.mutex);
+		mutex_lock(&dev->struct_mutex);
+
+		dove_drm_overlay_off(dev, ovl);
+
+		mutex_unlock(&dev->struct_mutex);
+		mutex_unlock(&dev->mode_config.mutex);
+
+		return 0;
+	}
+
+//	DRM_DEBUG_DRIVER("flags %x handle %x src %dx%d dst %dx%d+%d+%d\n",
+//		args->flags, args->bo_handle, args->src_scan_width, args->src_scan_height,
+//		args->dst_width, args->dst_height, args->dst_x, args->dst_y);
+
+	if (!ovl->dcrtc || ovl->crtc_id != args->crtc_id) {
+		dcrtc = dove_crtc_lookup(dev, args->crtc_id);
+		if (!dcrtc)
+			return -ENOENT;
+	} else {
+		dcrtc = ovl->dcrtc;
+	}
+
+	if (args->flags != ovl->cached_flags) {
+		ret = dove_ovl_compute_cfg(ovl, args->flags);
+		if (ret)
+			return ret;
+	}
+
+	obj = dove_gem_object_lookup(dev, file, args->bo_handle);
+	if (!obj)
+		return -ENOENT;
+
+	ret = wait_event_timeout(ovl->vbl_wait, list_empty(&ovl->vbl_update.node), HZ/25);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&dev->mode_config.mutex);
+	mutex_lock(&dev->struct_mutex);
+
+	/* Prevent updates */
+	if (ovl->dcrtc)
+		dove_drm_vbl_event_remove_unlocked(ovl->dcrtc, &ovl->vbl_update);
+
+	if (ovl->dcrtc != dcrtc) {
+		dove_drm_overlay_off(dev, ovl);
+
+		ovl->crtc_id = args->crtc_id;
+		ovl->dcrtc = dcrtc;
+		dcrtc->doverlay = ovl;
+
+		dove_ovl_update_attr(ovl);
+	}
+
+	ret = dove_ovl_check_dst(args, &ovl->dcrtc->crtc.mode);
+	if (ret)
+		goto err_unref;
+
+	planar = (args->flags & DOVE_OVERLAY_TYPE_MASK) == DOVE_OVERLAY_YUV_PLANAR;
+	if (planar)
+		ret = dove_check_planar(args, obj);
+	else
+		ret = dove_check_packed(args, obj);
+	if (ret)
+		goto err_unref;
+
+	if (ovl->dcrtc->interlaced) {
+		args->dst_y /= 2;
+		args->dst_height /= 2;
+	}
+
+	idx = 0;
+	if (ovl->obj != obj) {
+		uint32_t start_y, start_u, start_v;
+
+		/* switch to new object */
+		dove_ovl_release_old(ovl);
+		ovl->old_obj = ovl->obj;
+		ovl->obj = obj;
+
+		start_y = obj->dev_addr + args->offset_Y;
+		if (planar) {
+			start_u = obj->dev_addr + args->offset_U;
+			start_v = obj->dev_addr + args->offset_V;
+		} else {
+			start_u = start_y;
+			start_v = start_y;
+		}
+
+		dove_reg_queue_set(ovl->update, idx, start_y, LCD_SPU_DMA_START_ADDR_Y0);
+		dove_reg_queue_set(ovl->update, idx, start_u, LCD_SPU_DMA_START_ADDR_U0);
+		dove_reg_queue_set(ovl->update, idx, start_v, LCD_SPU_DMA_START_ADDR_V0);
+		dove_reg_queue_set(ovl->update, idx, start_y, LCD_SPU_DMA_START_ADDR_Y1);
+		dove_reg_queue_set(ovl->update, idx, start_u, LCD_SPU_DMA_START_ADDR_U1);
+		dove_reg_queue_set(ovl->update, idx, start_v, LCD_SPU_DMA_START_ADDR_V1);
+	} else {
+		drm_gem_object_unreference(&obj->obj);
+	}
+
+	stride_yc = args->stride_Y << 16 | args->stride_Y;
+	stride_uv = args->stride_UV << 16 | args->stride_UV;
+
+	if (ovl->stride_yc != stride_yc || ovl->stride_uv != stride_uv) {
+		ovl->stride_yc = stride_yc;
+		ovl->stride_uv = stride_uv;
+		dove_reg_queue_set(ovl->update, idx, stride_yc, LCD_SPU_DMA_PITCH_YC);
+		dove_reg_queue_set(ovl->update, idx, stride_uv, LCD_SPU_DMA_PITCH_UV);
+	}
+
+	src_hw = args->src_scan_height << 16 | args->src_scan_width;
+	dst_hw = args->dst_height << 16 | args->dst_width;
+	if (ovl->src_hw != src_hw || ovl->dst_hw != dst_hw) {
+		ovl->src_hw = src_hw;
+		ovl->dst_hw = dst_hw;
+
+		dove_reg_queue_set(ovl->update, idx, dst_hw, LCD_SPU_DZM_HPXL_VLN);
+		dove_reg_queue_set(ovl->update, idx, src_hw, LCD_SPU_DMA_HPXL_VLN);
+	}
+
+	dst_yx = args->dst_y << 16 | args->dst_x;
+	if (ovl->dst_yx != dst_yx) {
+		ovl->dst_yx = dst_yx;
+		dove_reg_queue_set(ovl->update, idx, dst_yx, LCD_SPU_DMA_OVSA_HPXL_VLN);
+	}
+
+	/* Update overlay DMA settings */
+	if (ovl->cfg != ovl->cached_cfg) {
+		ovl->cfg = ovl->cached_cfg;
+		dove_reg_queue_mod(ovl->update, idx, ovl->cached_cfg,
+			CFG_DMAFORMAT | CFG_DMA_FTOGGLE | CFG_DMA_HSMOOTH |
+			CFG_DMA_TSTMODE | CFG_DMA_SWAPRB | CFG_DMA_SWAPUV |
+			CFG_DMA_SWAPYU | CFG_YUV2RGB_DMA | CFG_DMA_ENA,
+			LCD_SPU_DMA_CTRL0);
+	}
+	if (idx) {
+		dove_reg_queue_end(ovl->update, idx);
+		dove_drm_vbl_event_add(dcrtc, &ovl->vbl_update);
+	}
+
+ err_unref:
+	if (ret)
+		drm_gem_object_unreference(&obj->obj);
+	mutex_unlock(&dev->struct_mutex);
+	mutex_unlock(&dev->mode_config.mutex);
+
+	return ret;
+}
+
+int dove_overlay_attrs_ioctl(struct drm_device *dev, void *data,
+	struct drm_file *file)
+{
+	struct drm_dove_overlay_attrs *args = data;
+        struct dove_private *priv = dev->dev_private;
+	struct dove_overlay *ovl = priv->doverlay;
+
+	if (!ovl) {
+		DRM_DEBUG_DRIVER("no overlay");
+		return -ENODEV;
+	}
+
+	if (args->flags & DOVE_OVERLAY_UPDATE_ATTRS) {
+		if (args->brightness < -128 || args->brightness > 127 ||
+		    args->contrast > 255 || args->saturation > 1023)
+			return -EINVAL;
+
+		ovl->color_key = args->color_key;
+		ovl->brightness = args->brightness;
+		ovl->contrast = args->contrast;
+		ovl->saturation = args->saturation;
+
+		mutex_lock(&dev->mode_config.mutex);
+		if (ovl->dcrtc)
+			dove_ovl_update_attr(ovl);
+		mutex_unlock(&dev->mode_config.mutex);
+	} else {
+		args->color_key = ovl->color_key;
+		args->brightness = ovl->brightness;
+		args->contrast = ovl->contrast;
+		args->saturation = ovl->saturation;
+	}
+
+	if (args->flags & DOVE_OVERLAY_UPDATE_GAMMA) {
+		/* args->gamma0..5 */
+	}
+
+	return 0;
+}
+
+int dove_overlay_create(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct dove_overlay *ovl;
+
+	ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
+	if (!ovl)
+		return -ENOMEM;
+
+	priv->doverlay = ovl;
+
+	init_waitqueue_head(&ovl->vbl_wait);
+	dove_drm_vbl_event_init(&ovl->vbl_update, dove_ovl_update, ovl->update);
+
+	ovl->color_key = 0x0101fe;
+	ovl->brightness = -19;
+	ovl->contrast = 75;
+	ovl->saturation = 146;
+
+	return 0;
+}
+
+void dove_overlay_destroy(struct drm_device *dev)
+{
+	struct dove_private *priv = dev->dev_private;
+	struct dove_overlay *ovl = priv->doverlay;
+
+	if (ovl->dcrtc)
+		dove_drm_vbl_event_remove_unlocked(ovl->dcrtc, &ovl->vbl_update);
+
+	kfree(ovl);
+}
diff --git a/drivers/gpu/drm/dove/drm_helper.h b/drivers/gpu/drm/dove/drm_helper.h
new file mode 100644
index 0000000..0753b3f
--- /dev/null
+++ b/drivers/gpu/drm/dove/drm_helper.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DRM_HELPER_H
+#define DRM_HELPER_H
+
+/* Useful helpers I wish the DRM core would provide */
+
+#include "drmP.h"
+
+static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
+	uint32_t id)
+{
+	struct drm_mode_object *mo;
+	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CRTC);
+	return mo ? obj_to_crtc(mo) : NULL;
+}
+
+static inline struct drm_encoder *drm_encoder_find(struct drm_device *dev,
+	uint32_t id)
+{
+	struct drm_mode_object *mo;
+	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_ENCODER);
+	return mo ? obj_to_encoder(mo) : NULL;
+}
+
+#endif
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:27:18 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:27:18 +0100
Subject: [RFC 6/8] drm/i2c: nxp-tda998x: add video and audio input
 configuration
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3pe-0001r0-HU@rmk-PC.arm.linux.org.uk>

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |  308 ++++++++++++++++++++++++++++++++++++-
 1 files changed, 301 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index d6afd02..8ffb844 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -23,7 +23,7 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_encoder_slave.h>
 #include <drm/drm_edid.h>
-
+#include <drm/i2c/tda998x.h>
 
 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 
@@ -32,9 +32,11 @@ struct tda998x_priv {
 	uint16_t rev;
 	uint8_t current_page;
 	int dpms;
+	bool is_hdmi_sink;
 	u8 vip_cntrl_0;
 	u8 vip_cntrl_1;
 	u8 vip_cntrl_2;
+	struct tda998x_encoder_params params;
 };
 
 #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
@@ -71,10 +73,13 @@ struct tda998x_priv {
 # define I2C_MASTER_DIS_MM        (1 << 0)
 # define I2C_MASTER_DIS_FILT      (1 << 1)
 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
+#define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
+# define FEAT_POWERDOWN_SPDIF     (1 << 3)
 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
+#define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
@@ -113,6 +118,7 @@ struct tda998x_priv {
 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
+#define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
@@ -175,6 +181,12 @@ struct tda998x_priv {
 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
+#define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
+# define I2S_FORMAT(x)            (((x) & 3) << 0)
+#define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
+# define AIP_CLKSEL_FS(x)         (((x) & 3) << 0)
+# define AIP_CLKSEL_CLK_POL(x)    (((x) & 1) << 2)
+# define AIP_CLKSEL_AIP(x)        (((x) & 7) << 3)
 
 
 /* Page 02h: PLL settings */
@@ -216,6 +228,11 @@ struct tda998x_priv {
 
 
 /* Page 10h: information frames and packets */
+#define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
+#define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
+#define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
+#define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
+#define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 
 
 /* Page 11h: audio settings and content info packets */
@@ -225,10 +242,33 @@ struct tda998x_priv {
 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
+#define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
+# define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
+# define CA_I2S_HBR_CHSTAT        (1 << 6)
+#define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
+#define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
+#define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
+#define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
+#define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
+#define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
+#define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
+#define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
+# define CTS_N_K(x)               (((x) & 7) << 0)
+# define CTS_N_M(x)               (((x) & 3) << 4)
 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 # define ENC_CNTRL_RST_ENC        (1 << 0)
 # define ENC_CNTRL_RST_SEL        (1 << 1)
 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
+#define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
+# define DIP_FLAGS_ACR            (1 << 0)
+# define DIP_FLAGS_GC             (1 << 1)
+#define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
+# define DIP_IF_FLAGS_IF1         (1 << 1)
+# define DIP_IF_FLAGS_IF2         (1 << 2)
+# define DIP_IF_FLAGS_IF3         (1 << 3)
+# define DIP_IF_FLAGS_IF4         (1 << 4)
+# define DIP_IF_FLAGS_IF5         (1 << 5)
+#define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 
 
 /* Page 12h: HDCP and OTP */
@@ -344,6 +384,23 @@ reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt)
 	return ret;
 }
 
+static void
+reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt)
+{
+	struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
+	uint8_t buf[cnt+1];
+	int ret;
+
+	buf[0] = REG2ADDR(reg);
+	memcpy(&buf[1], p, cnt);
+
+	set_page(encoder, reg);
+
+	ret = i2c_master_send(client, buf, cnt + 1);
+	if (ret < 0)
+		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
+}
+
 static uint8_t
 reg_read(struct drm_encoder *encoder, uint16_t reg)
 {
@@ -421,11 +478,192 @@ tda998x_reset(struct drm_encoder *encoder)
 	reg_write(encoder, REG_PLL_SCG2,     0x10);
 }
 
+static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
+{
+	uint8_t sum = 0;
+
+	while (bytes--)
+		sum += *buf++;
+	return (255 - sum) + 1;
+}
+
+#define HB(x) (x)
+#define PB(x) (HB(2) + 1 + (x))
+
+static void
+tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr,
+		 uint8_t *buf, size_t size)
+{
+	buf[PB(0)] = tda998x_cksum(buf, size);
+
+	reg_clear(encoder, REG_DIP_IF_FLAGS, bit);
+	reg_write_range(encoder, addr, buf, size);
+	reg_set(encoder, REG_DIP_IF_FLAGS, bit);
+}
+
+static void
+tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p)
+{
+	uint8_t buf[PB(5) + 1];
+
+	buf[HB(0)] = 0x84;
+	buf[HB(1)] = 0x01;
+	buf[HB(2)] = 10;
+	buf[PB(0)] = 0;
+	buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
+	buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
+	buf[PB(4)] = p->audio_frame[4];
+	buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
+
+	tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
+			 sizeof(buf));
+}
+
+static void
+tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode)
+{
+	uint8_t buf[PB(13) + 1];
+
+	memset(buf, 0, sizeof(buf));
+	buf[HB(0)] = 0x82;
+	buf[HB(1)] = 0x02;
+	buf[HB(2)] = 13;
+	buf[PB(4)] = drm_match_cea_mode(mode);
+
+	tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
+			 sizeof(buf));
+}
+
+static void tda998x_audio_mute(struct drm_encoder *encoder, bool on)
+{
+	if (on) {
+		reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO);
+		reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO);
+		reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
+	} else {
+		reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
+	}
+}
+
+static void
+tda998x_configure_audio(struct drm_encoder *encoder, struct tda998x_encoder_params *p)
+{
+	uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n;
+	uint32_t n;
+
+	/* SetAudioPortConfig */
+	reg_write(encoder, REG_ENA_AP, p->audio_cfg);
+	/* SetAudioClockPortConfig */
+	reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg);
+
+	/*
+	 * layout = channelAllocation ? 1 : 0;
+	 * AudioInSetConfig(format, i2sFormat, channelAllocation,
+	 *   HDMITX_CHAN_NO_CHANGE, HDMITX_CLKPOLDSD_NO_CHANGE,
+	 *   HDMITX_SWAPDSD_NO_CHANGE, layout, HDMITX_LATENCY_CURRENT,
+	 *   dstRate)
+	 */
+	switch (p->audio_format) {
+	case AFMT_SPDIF:
+		reg_write(encoder, REG_MUX_AP, 0x40);
+		clksel_aip = AIP_CLKSEL_AIP(0);
+		/* FS64SPDIF */
+		clksel_fs = AIP_CLKSEL_FS(2);
+		cts_n = CTS_N_M(3) | CTS_N_K(3);
+		ca_i2s = 0;
+		break;
+
+	case AFMT_I2S:
+		reg_write(encoder, REG_MUX_AP, 0x64);
+		clksel_aip = AIP_CLKSEL_AIP(1);
+		/* ACLK */
+		clksel_fs = AIP_CLKSEL_FS(0);
+		cts_n = CTS_N_M(3) | CTS_N_K(3);
+		ca_i2s = CA_I2S_CA_I2S(0 /* channel allocation */);
+		break;
+	}
+
+	reg_write(encoder, REG_AIP_CLKSEL, clksel_aip);
+//	reg_write(encoder, REG_CA_I2S, ca_i2s);
+//	reg_write(encoder, REG_I2S_FORMAT, I2S_FORMAT(0 /* i2s format */));
+	reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT);
+	/* latency? */
+
+	/* get video format */
+
+	/*
+	 * ctsRef = HDMITX_CTSREF_FS64SPDIF, uCtsX = HDMITX_CTSX_64
+	 * AudioInSetCts(ctsRef, rate, VidFmt, vOutFreq,
+	 *   HDMITX_CTS_AUTO, uCtsX, HDMITX_CTSK_USE_CTSX,
+	 *   HDMITX_CTSMTS_USE_CTSX, dstRate)
+	 */
+	/* Auto CTS */
+	reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN);
+	reg_write(encoder, REG_CTS_N, cts_n);
+	reg_write(encoder, REG_AUDIO_DIV, 3);
+
+	/*
+	 * This is the approximate value of N, which happens to be
+	 * the recommended values for non-coherent clocks.
+	 */
+	n = 128 * p->audio_sample_rate / 1000;
+
+	/* Write the CTS and N values */
+	buf[0] = 0x44;
+	buf[1] = 0x42;
+	buf[2] = 0x01;
+	buf[3] = n;
+	buf[4] = n >> 8;
+	buf[5] = n >> 16;
+	reg_write_range(encoder, REG_ACR_CTS_0, buf, 6);
+
+	/* Set CTS clock reference */
+	reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
+
+	/* Reset CTS generator */
+	reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
+	reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
+
+	/* Write the channel status */
+	buf[0] = 0x04;
+	buf[1] = 0x00;
+	buf[2] = 0x00;
+	buf[3] = 0xf1;
+	reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4);
+
+	tda998x_audio_mute(encoder, true);
+	mdelay(20);
+	tda998x_audio_mute(encoder, false);
+
+	/* Write the audio information packet */
+	tda998x_write_aif(encoder, p);
+}
+
 /* DRM encoder functions */
 
 static void
 tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
 {
+	struct tda998x_priv *priv = to_tda998x_priv(encoder);
+	struct tda998x_encoder_params *p = params;
+
+	priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
+			    (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
+			    VIP_CNTRL_0_SWAP_B(p->swap_b) |
+			    (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
+	priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
+			    (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
+			    VIP_CNTRL_1_SWAP_D(p->swap_d) |
+			    (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
+	priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
+			    (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
+			    VIP_CNTRL_2_SWAP_F(p->swap_f) |
+			    (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
+
+	priv->params = *p;
+
+	if (p->audio_cfg)
+		tda998x_configure_audio(encoder, p);
 }
 
 static void
@@ -445,7 +683,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 		/* Write the default value MUX register */
 		reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
 		/* enable audio and video ports */
-		reg_write(encoder, REG_ENA_AP, 0xff);
+//		reg_write(encoder, REG_ENA_AP, priv->ena_ap);
+//		reg_write(encoder, REG_ENA_ACLK, priv->ena_aclk);
 		reg_write(encoder, REG_ENA_VP_0, 0xff);
 		reg_write(encoder, REG_ENA_VP_1, 0xff);
 		reg_write(encoder, REG_ENA_VP_2, 0xff);
@@ -456,7 +695,7 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 		break;
 	case DRM_MODE_DPMS_OFF:
 		/* disable audio and video ports */
-		reg_write(encoder, REG_ENA_AP, 0x00);
+//		reg_write(encoder, REG_ENA_AP, 0x00);
 		reg_write(encoder, REG_ENA_VP_0, 0x00);
 		reg_write(encoder, REG_ENA_VP_1, 0x00);
 		reg_write(encoder, REG_ENA_VP_2, 0x00);
@@ -607,17 +846,31 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
 	reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
 	reg_write16(encoder, REG_REFLINE_MSB, ref_line);
 
-	reg = TBG_CNTRL_1_VHX_EXT_DE |
-			TBG_CNTRL_1_VHX_EXT_HS |
-			TBG_CNTRL_1_VHX_EXT_VS |
-			TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
+	reg = TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
 			TBG_CNTRL_1_VH_TGL_2;
+	/*
+	 * It is questionable whether this is correct - the nxp driver
+	 * does not set VH_TGL_2 and the below for all display modes.
+	 */
 	if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC))
 		reg |= TBG_CNTRL_1_VH_TGL_0;
 	reg_set(encoder, REG_TBG_CNTRL_1, reg);
 
 	/* must be last register set: */
 	reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
+
+	/* Only setup the info frames if the sink is HDMI */
+	if (priv->is_hdmi_sink) {
+		/* We need to turn HDMI HDCP stuff on to get audio through */
+		reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
+		reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
+		reg_set(encoder, REG_TX33, TX33_HDMI);
+
+		tda998x_write_avi(encoder, adjusted_mode);
+
+		if (priv->params.audio_cfg)
+			tda998x_configure_audio(encoder, &priv->params);
+	}
 }
 
 static enum drm_connector_status
@@ -743,12 +996,14 @@ static int
 tda998x_encoder_get_modes(struct drm_encoder *encoder,
 			 struct drm_connector *connector)
 {
+	struct tda998x_priv *priv = to_tda998x_priv(encoder);
 	struct edid *edid = (struct edid *)do_get_edid(encoder);
 	int n = 0;
 
 	if (edid) {
 		drm_mode_connector_update_edid_property(connector, edid);
 		n = drm_add_edid_modes(connector, edid);
+		priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
 		kfree(edid);
 	}
 
@@ -810,6 +1065,40 @@ tda998x_remove(struct i2c_client *client)
 	return 0;
 }
 
+static ssize_t i2c_read_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct drm_encoder *encoder = dev_get_drvdata(dev);
+	unsigned int page, addr;
+	unsigned char val;
+
+	sscanf(buf, "%x %x", &page, &addr);
+
+	val = reg_read(encoder, REG(page, addr));
+
+	printk("i2c read %02x @ page:%02x address:%02x\n", val, page, addr);
+	return size;
+}
+
+static ssize_t i2c_write_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct drm_encoder *encoder = dev_get_drvdata(dev);
+	unsigned int page, addr, mask, val;
+	unsigned char rval;
+
+	sscanf(buf, "%x %x %x %x", &page, &addr, &mask, &val);
+
+	rval = reg_read(encoder, REG(page, addr));
+	rval &= ~mask;
+	rval |= val & mask;
+	reg_write(encoder, REG(page, addr), rval);
+
+	printk("i2c write %02x @ page:%02x address:%02x\n", rval, page, addr);
+	return size;
+}
+
+static DEVICE_ATTR(i2c_read, S_IWUSR, NULL, i2c_read_store);
+static DEVICE_ATTR(i2c_write, S_IWUSR, NULL, i2c_write_store);
+
 static int
 tda998x_encoder_init(struct i2c_client *client,
 		    struct drm_device *dev,
@@ -817,6 +1106,11 @@ tda998x_encoder_init(struct i2c_client *client,
 {
 	struct drm_encoder *encoder = &encoder_slave->base;
 	struct tda998x_priv *priv;
+/* debug */
+	device_create_file(&client->dev, &dev_attr_i2c_read);
+	device_create_file(&client->dev, &dev_attr_i2c_write);
+	dev_set_drvdata(&client->dev, encoder);
+/* debug end */
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu May 16 15:27:59 2013
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 16 May 2013 20:27:59 +0100
Subject: [RFC 8/8] DRM: dove: provide a couple of generic slave encoder helpers
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <E1Ud3qJ-0001rA-3q@rmk-PC.arm.linux.org.uk>

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/gpu/drm/dove/dove_output.c   |   20 ++++++++++++++++++++
 drivers/gpu/drm/dove/dove_output.h   |    6 ++++++
 drivers/gpu/drm/dove/dove_tda19988.c |   23 ++---------------------
 3 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/dove/dove_output.c b/drivers/gpu/drm/dove/dove_output.c
index 7cd7d35..470ce80 100644
--- a/drivers/gpu/drm/dove/dove_output.c
+++ b/drivers/gpu/drm/dove/dove_output.c
@@ -9,6 +9,7 @@
 #include "drm_crtc_helper.h"
 #include "drm_edid.h"
 #include "drm_helper.h"
+#include "drm_encoder_slave.h"
 #include "dove_output.h"
 #include "dove_drm.h"
 
@@ -76,6 +77,25 @@ void dove_drm_encoder_commit(struct drm_encoder *encoder)
 	funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 }
 
+/* Shouldn't this be a generic helper function? */
+int dove_drm_slave_encoder_mode_valid(struct drm_connector *conn,
+	struct drm_display_mode *mode)
+{
+	struct drm_encoder *encoder = conn->encoder;
+	struct drm_encoder_slave *slave = to_encoder_slave(encoder);
+
+	return slave->slave_funcs->mode_valid(encoder, mode);
+}
+
+int dove_drm_slave_encoder_set_property(struct drm_connector *conn,
+	struct drm_property *property, uint64_t value)
+{
+	struct drm_encoder *encoder = conn->encoder;
+	struct drm_encoder_slave *slave = to_encoder_slave(encoder);
+
+	return slave->slave_funcs->set_property(encoder, conn, property, value);
+}
+
 struct drm_connector *dove_output_create(struct drm_device *dev,
 	const struct dove_output_type *type)
 {
diff --git a/drivers/gpu/drm/dove/dove_output.h b/drivers/gpu/drm/dove/dove_output.h
index 1b12890..d504ef0 100644
--- a/drivers/gpu/drm/dove/dove_output.h
+++ b/drivers/gpu/drm/dove/dove_output.h
@@ -20,6 +20,12 @@ struct drm_encoder *dove_drm_connector_best_encoder(struct drm_connector *conn);
 void dove_drm_encoder_prepare(struct drm_encoder *encoder);
 void dove_drm_encoder_commit(struct drm_encoder *encoder);
 
+int dove_drm_slave_encoder_mode_valid(struct drm_connector *conn,
+	struct drm_display_mode *mode);
+
+int dove_drm_slave_encoder_set_property(struct drm_connector *conn,
+	struct drm_property *property, uint64_t value);
+
 struct drm_connector *dove_output_create(struct drm_device *dev,
 	const struct dove_output_type *);
 
diff --git a/drivers/gpu/drm/dove/dove_tda19988.c b/drivers/gpu/drm/dove/dove_tda19988.c
index 26ef2a2..0b179d7 100644
--- a/drivers/gpu/drm/dove/dove_tda19988.c
+++ b/drivers/gpu/drm/dove/dove_tda19988.c
@@ -20,15 +20,6 @@ struct dove_drm_tda19988_encoder {
 };
 #define to_tda19988_encoder(enc) container_of(to_encoder_slave(enc), struct dove_drm_tda19988_encoder, slave)
 
-static int dove_drm_connector_tda19988_mode_valid(struct drm_connector *conn,
-	struct drm_display_mode *mode)
-{
-	struct drm_encoder *enc = conn->encoder;
-	struct dove_drm_tda19988_encoder *tenc = to_tda19988_encoder(enc);
-
-	return tenc->slave.slave_funcs->mode_valid(enc, mode);
-}
-
 static int dove_drm_connector_tda19988_get_modes(struct drm_connector *conn)
 {
 	struct drm_display_mode *mode;
@@ -96,7 +87,7 @@ static const struct drm_encoder_funcs dove_drm_tda19988_enc_funcs = {
 
 static const struct drm_connector_helper_funcs dove_drm_conn_tda19988_helper_funcs = {
 	.get_modes	= dove_drm_connector_tda19988_get_modes,
-	.mode_valid	= dove_drm_connector_tda19988_mode_valid,
+	.mode_valid	= dove_drm_slave_encoder_mode_valid,
 	.best_encoder	= dove_drm_connector_best_encoder,
 };
 
@@ -225,22 +216,12 @@ static int dove_drm_conn_tda19988_create(struct drm_connector *conn,
 	return ret;
 }
 
-static int dove_drm_conn_tda19988_set_property(struct drm_connector *conn,
-	struct drm_property *property, uint64_t value)
-{
-	struct dove_drm_tda19988_encoder *tenc =
-		to_tda19988_encoder(conn->encoder);
-	struct drm_encoder_slave_funcs *sfuncs = tenc->slave.slave_funcs;
-
-	return sfuncs->set_property(&tenc->slave.base, conn, property, value);
-}
-
 static const struct dove_output_type dove_drm_conn_tda19988 = {
 	.connector_type	= DRM_MODE_CONNECTOR_HDMIA,
 	.polled		= DRM_CONNECTOR_POLL_HPD,
 	.detect		= dove_drm_conn_tda19988_detect,
 	.create		= dove_drm_conn_tda19988_create,
-	.set_property	= dove_drm_conn_tda19988_set_property,
+	.set_property	= dove_drm_slave_encoder_set_property,
 };
 
 struct drm_connector *dove_drm_tda19988_create(struct drm_device *dev)
-- 
1.7.4.4



From aaro.koskinen at iki.fi  Thu May 16 17:00:06 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Fri, 17 May 2013 00:00:06 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130516180933.GG5600@atomide.com>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
Message-ID: <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>

On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> > I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> > 
> > [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> > [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> > [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> > 
> > The error is coming from regmap code. According to git bisect, it is
> > caused by:
> > 
> > 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> > 	Author: Jon Hunter <jon-hunter at ti.com>
> > 	Date:   Fri Mar 1 11:22:47 2013 -0600
> > 
> > 	    gpio/omap: convert gpio irq domain to linear mapping
> > 
> > The commit does not anymore revert cleanly, and I haven't yet tried
> > crafting a manual revert, so any fix proposals/ideas are welcome...
> 
> Hmm this might be a bit trickier to fix. Obviously the real solution
> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> 
> For the -rc cycle, it might be possible to fix this by adding a
> different irq_to_gpio() and gpio_to_irq() functions for omap1.

The commit reverts cleanly if we also revert
3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
service routine), which seems to be just some minor optimization. The
result is below, and with it 770 works again.

A.

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 2050891..a9b5813 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -52,6 +52,7 @@ struct gpio_bank {
 	struct list_head node;
 	void __iomem *base;
 	u16 irq;
+	int irq_base;
 	struct irq_domain *domain;
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
@@ -87,14 +88,7 @@ struct gpio_bank {
 
 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
 {
-	return bank->chip.base + gpio_irq;
-}
-
-static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
-
-	return irq_find_mapping(bank->domain, offset);
+	return gpio_irq - bank->irq_base + bank->chip.base;
 }
 
 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
@@ -435,7 +429,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
 #endif
 
 	if (!gpio)
-		gpio = irq_to_gpio(bank, d->hwirq);
+		gpio = irq_to_gpio(bank, d->irq);
 
 	if (type & ~IRQ_TYPE_SENSE_MASK)
 		return -EINVAL;
@@ -588,7 +582,7 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio)
 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
+	unsigned int gpio = irq_to_gpio(bank, d->irq);
 
 	return _set_gpio_wakeup(bank, gpio, enable);
 }
@@ -688,7 +682,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
 	void __iomem *isr_reg = NULL;
 	u32 isr;
-	unsigned int bit;
+	unsigned int gpio_irq, gpio_index;
 	struct gpio_bank *bank;
 	int unmasked = 0;
 	struct irq_chip *chip = irq_desc_get_chip(desc);
@@ -729,9 +723,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 		if (!isr)
 			break;
 
-		while (isr) {
-			bit = __ffs(isr);
-			isr &= ~(1 << bit);
+		gpio_irq = bank->irq_base;
+		for (; isr != 0; isr >>= 1, gpio_irq++) {
+			int gpio = irq_to_gpio(bank, gpio_irq);
+
+			if (!(isr & 1))
+				continue;
+
+			gpio_index = GPIO_INDEX(bank, gpio);
 
 			/*
 			 * Some chips can't respond to both rising and falling
@@ -740,10 +739,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 			 * to respond to the IRQ for the opposite direction.
 			 * This will be indicated in the bank toggle_mask.
 			 */
-			if (bank->toggle_mask & (1 << bit))
-				_toggle_gpio_edge_triggering(bank, bit);
+			if (bank->toggle_mask & (1 << gpio_index))
+				_toggle_gpio_edge_triggering(bank, gpio_index);
 
-			generic_handle_irq(irq_find_mapping(bank->domain, bit));
+			generic_handle_irq(gpio_irq);
 		}
 	}
 	/* if bank has any level sensitive GPIO pin interrupt
@@ -759,7 +758,7 @@ exit:
 static void gpio_irq_shutdown(struct irq_data *d)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
+	unsigned int gpio = irq_to_gpio(bank, d->irq);
 	unsigned long flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
@@ -770,7 +769,7 @@ static void gpio_irq_shutdown(struct irq_data *d)
 static void gpio_ack_irq(struct irq_data *d)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
+	unsigned int gpio = irq_to_gpio(bank, d->irq);
 
 	_clear_gpio_irqstatus(bank, gpio);
 }
@@ -778,7 +777,7 @@ static void gpio_ack_irq(struct irq_data *d)
 static void gpio_mask_irq(struct irq_data *d)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
+	unsigned int gpio = irq_to_gpio(bank, d->irq);
 	unsigned long flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
@@ -790,7 +789,7 @@ static void gpio_mask_irq(struct irq_data *d)
 static void gpio_unmask_irq(struct irq_data *d)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
+	unsigned int gpio = irq_to_gpio(bank, d->irq);
 	unsigned int irq_mask = GPIO_BIT(bank, gpio);
 	u32 trigger = irqd_get_trigger_type(d);
 	unsigned long flags;
@@ -956,6 +955,14 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 	spin_unlock_irqrestore(&bank->lock, flags);
 }
 
+static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
+{
+	struct gpio_bank *bank;
+
+	bank = container_of(chip, struct gpio_bank, chip);
+	return bank->irq_base + offset;
+}
+
 /*---------------------------------------------------------------------*/
 
 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
@@ -1052,7 +1059,7 @@ static void omap_gpio_chip_init(struct gpio_bank *bank)
 	bank->chip.direction_output = gpio_output;
 	bank->chip.set_debounce = gpio_debounce;
 	bank->chip.set = gpio_set;
-	bank->chip.to_irq = omap_gpio_to_irq;
+	bank->chip.to_irq = gpio_2irq;
 	if (bank->is_mpuio) {
 		bank->chip.label = "mpuio";
 		if (bank->regs->wkup_en)
@@ -1067,16 +1074,15 @@ static void omap_gpio_chip_init(struct gpio_bank *bank)
 
 	gpiochip_add(&bank->chip);
 
-	for (j = 0; j < bank->width; j++) {
-		int irq = irq_create_mapping(bank->domain, j);
-		irq_set_lockdep_class(irq, &gpio_lock_class);
-		irq_set_chip_data(irq, bank);
+	for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
+		irq_set_lockdep_class(j, &gpio_lock_class);
+		irq_set_chip_data(j, bank);
 		if (bank->is_mpuio) {
-			omap_mpuio_alloc_gc(bank, irq, bank->width);
+			omap_mpuio_alloc_gc(bank, j, bank->width);
 		} else {
-			irq_set_chip_and_handler(irq, &gpio_irq_chip,
-						 handle_simple_irq);
-			set_irq_flags(irq, IRQF_VALID);
+			irq_set_chip(j, &gpio_irq_chip);
+			irq_set_handler(j, handle_simple_irq);
+			set_irq_flags(j, IRQF_VALID);
 		}
 	}
 	irq_set_chained_handler(bank->irq, gpio_irq_handler);
@@ -1131,10 +1137,14 @@ static int omap_gpio_probe(struct platform_device *pdev)
 	}
 
 
-	bank->domain = irq_domain_add_linear(node, bank->width,
-					     &irq_domain_simple_ops, NULL);
-	if (!bank->domain)
+	bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
+	if (bank->irq_base < 0) {
+		dev_err(dev, "Couldn't allocate IRQ numbers\n");
 		return -ENODEV;
+	}
+
+	bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
+					     0, &irq_domain_simple_ops, NULL);
 
 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
 		bank->set_dataout = _set_gpio_dataout_reg;


From sergei.shtylyov at cogentembedded.com  Thu May 16 17:22:33 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 17 May 2013 01:22:33 +0400
Subject: [PATCH v4 0/3] R8A7778/BOCK-W R-Car VIN driver support
Message-ID: <201305170122.33996.sergei.shtylyov@cogentembedded.com>

Hello.

   Here's the set of 3 patches against the Simon Horman's 'renesas.git' repo,
'renesas-next-20130515v2' tag and my recent yet unapplied patches. Here we
add the VIN platform code working on
the R8A7778/BOCK-W with ML86V7667. The driver patch also applies (with offsets)
to Mauro's 'media_tree.git'...

[1/3] ARM: shmobile: r8a7778: add VIN support
[2/3] ARM: shmobile: BOCK-W: add VIN and ML86V7667 support
[3/3] ARM: shmobile: BOCK-W: enable VIN and ML86V7667 in defconfig

   The patch containing OKI ML86V7667 video decoder driver has been removed
from the series as it should be applied to the 'media_tree.git' repo. The patch
containing the VIN PFC support has been also removed from the series and has
now been merged.

WBR, Sergei


From sergei.shtylyov at cogentembedded.com  Thu May 16 17:28:02 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 17 May 2013 01:28:02 +0400
Subject: [PATCH v4 1/3] ARM: shmobile: r8a7778: add VIN support
In-Reply-To: <201305170122.33996.sergei.shtylyov@cogentembedded.com>
References: <201305170122.33996.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305170128.03074.sergei.shtylyov@cogentembedded.com>

From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

Add VIN clocks and platform devices on R8A7778 SoC; add function to register
the VIN platform devices.

Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
[Sergei: added 'id' parameter check to r8a7779_add_vin_device(), used '*pdata'
in *sizeof* operator there, renamed some variables, annotated 'vin[01]_info' and
vin[01]_resources[] as '__initdata'.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
Changes since version 3:
- changed the VIN platform device names to be R8A7778 specific; 
- resolved reject in <mach/r8a7778.h>  due to USB patch rework.

Changes from version 2:
- annotated 'vin[01]_info' and vin[01]_resources[] as '__initdata' since they're
  kmemdup()'ed while registering the platform devices anyway;
- refreshed the patch.

 arch/arm/mach-shmobile/clock-r8a7778.c        |    5 +++
 arch/arm/mach-shmobile/include/mach/r8a7778.h |    3 ++
 arch/arm/mach-shmobile/setup-r8a7778.c        |   33 ++++++++++++++++++++++++++
 3 files changed, 41 insertions(+)

Index: renesas/arch/arm/mach-shmobile/clock-r8a7778.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/clock-r8a7778.c
+++ renesas/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -106,6 +106,7 @@ static struct clk *main_clks[] = {
 enum {
 	MSTP323, MSTP322, MSTP321,
 	MSTP114,
+	MSTP110, MSTP109,
 	MSTP100,
 	MSTP030, MSTP029,
 	MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -117,6 +118,8 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+	[MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
+	[MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1,  9, 0), /* VIN1 */
 	[MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1,  0, 0), /* USB0/1 */
 	[MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
 	[MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
@@ -140,6 +143,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
 	CLKDEV_DEV_ID("sh-eth",	&mstp_clks[MSTP114]), /* Ether */
+	CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
+	CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
 	CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
 	CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
 	CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
Index: renesas/arch/arm/mach-shmobile/include/mach/r8a7778.h
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ renesas/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -21,11 +21,14 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
 #include <linux/platform_data/usb-rcar-phy.h>
+#include <linux/platform_data/camera-rcar.h>
 
 extern void r8a7778_add_standard_devices(void);
 extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
 extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7778_add_vin_device(int id,
+				   struct rcar_vin_platform_data *pdata);
 extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq(void);
Index: renesas/arch/arm/mach-shmobile/setup-r8a7778.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/setup-r8a7778.c
+++ renesas/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -299,6 +299,39 @@ void __init r8a7778_sdhi_init(int id,
 		info, sizeof(*info));
 }
 
+/* VIN */
+#define R8A7778_VIN(idx)						\
+static struct resource vin##idx##_resources[] __initdata = {		\
+	DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000),		\
+	DEFINE_RES_IRQ(gic_iid(0x5a)),					\
+};									\
+									\
+static struct platform_device_info vin##idx##_info __initdata = {	\
+	.parent		= &platform_bus,				\
+	.name		= "r8a7778-vin",				\
+	.id		= idx,						\
+	.res		= vin##idx##_resources,				\
+	.num_res	= ARRAY_SIZE(vin##idx##_resources),		\
+	.dma_mask	= DMA_BIT_MASK(32),				\
+}
+
+R8A7778_VIN(0);
+R8A7778_VIN(1);
+
+static struct platform_device_info *vin_info_table[] __initdata = {
+	&vin0_info,
+	&vin1_info,
+};
+
+void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
+{
+	BUG_ON(id < 0 || id > 1);
+
+	vin_info_table[id]->data = pdata;
+	vin_info_table[id]->size_data = sizeof(*pdata);
+	platform_device_register_full(vin_info_table[id]);
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
 	int i;


From sergei.shtylyov at cogentembedded.com  Thu May 16 17:30:40 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 17 May 2013 01:30:40 +0400
Subject: [PATCH v4 2/3] ARM: shmobile: BOCK-W: add VIN and ML86V7667 support
In-Reply-To: <201305170122.33996.sergei.shtylyov@cogentembedded.com>
References: <201305170122.33996.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305170130.40830.sergei.shtylyov@cogentembedded.com>

From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and
register VIN0/1 devices with the ML86V7667 specific platform data.

Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
[Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate
#include, annotated all platform data as '__initdata'.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
Changes since version 3:
- changed the VIN platform device names to be R8A7778 specific; 
- resolved reject due to USB patch rework, refreshed the patch.

Changes since version 2:
- removed duplicate #include <linux/pinctrl/machine.h>;
- annotated all platform data as '__initdata' since they're kmemdup()'ed while
  registering the platform devices anyway;
- resolved rejects, refreshed the patch.

 arch/arm/mach-shmobile/board-bockw.c |   39 +++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

Index: renesas/arch/arm/mach-shmobile/board-bockw.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/board-bockw.c
+++ renesas/arch/arm/mach-shmobile/board-bockw.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +26,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <media/soc_camera.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
@@ -65,6 +67,25 @@ static struct sh_mobile_sdhi_info sdhi0_
 
 static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
 
+static struct rcar_vin_platform_data vin_platform_data __initdata = {
+	.flags	= RCAR_VIN_BT656,
+};
+
+/* In the default configuration both decoders reside on I2C bus 0 */
+#define BOCKW_CAMERA(idx)						\
+static struct i2c_board_info camera##idx##_info = {			\
+	I2C_BOARD_INFO("ml86v7667", 0x41 + 2 * (idx)),			\
+};									\
+									\
+static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = {	\
+	.bus_id		= idx,						\
+	.i2c_adapter_id	= 0,						\
+	.board_info	= &camera##idx##_info,				\
+};
+
+BOCKW_CAMERA(0);
+BOCKW_CAMERA(1);
+
 static const struct pinctrl_map bockw_pinctrl_map[] = {
 	/* SCIF0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
@@ -84,6 +105,16 @@ static const struct pinctrl_map bockw_pi
 				  "usb0", "usb0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
 				  "usb1", "usb1"),
+	/* VIN0 */
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778",
+				  "vin0_clk", "vin0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778",
+				  "vin0_data8", "vin0"),
+	/* VIN1 */
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778",
+				  "vin1_clk", "vin1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778",
+				  "vin1_data8", "vin1"),
 };
 
 #define FPGA	0x18200000
@@ -98,6 +129,14 @@ static void __init bockw_init(void)
 	r8a7778_init_irq_extpin(1);
 	r8a7778_add_standard_devices();
 	r8a7778_add_usb_phy_device(&usb_phy_platform_data);
+	r8a7778_add_vin_device(0, &vin_platform_data);
+	r8a7778_add_vin_device(1, &vin_platform_data);
+	platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0,
+				      &iclink0_ml86v7667,
+				      sizeof(iclink0_ml86v7667));
+	platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
+				      &iclink1_ml86v7667,
+				      sizeof(iclink1_ml86v7667));
 
 	pinctrl_register_mappings(bockw_pinctrl_map,
 				  ARRAY_SIZE(bockw_pinctrl_map));


From skannan at codeaurora.org  Thu May 16 17:31:23 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Thu, 16 May 2013 14:31:23 -0700
Subject: [PATCH v2] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <20130516204455.12127.75296@quantum>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <1368677244-7279-1-git-send-email-skannan@codeaurora.org>
 <20130516204455.12127.75296@quantum>
Message-ID: <5195502B.3070003@codeaurora.org>

On 05/16/2013 01:44 PM, Mike Turquette wrote:
> Quoting Saravana Kannan (2013-05-15 21:07:24)
>> Without this patch, the following race condition is possible.
>> * clk-A has two parents - clk-X and clk-Y.
>> * All three are disabled and clk-X is current parent.
>> * Thread A: clk_set_parent(clk-A, clk-Y).
>> * Thread A: <snip execution flow>
>> * Thread A: Grabs enable lock.
>> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
>> * Thread A: Updates clk-A SW parent to clk-Y
>> * Thread A: Releases enable lock.
>> * Thread B: clk_enable(clk-A).
>> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.
>>
>> clk-A is now enabled in software, but not clocking in hardware since the
>> hardware parent is still clk-X.
>>
>> The only way to avoid race conditions between clk_set_parent() and
>> clk_enable/disable() is to ensure that clk_enable/disable() calls don't
>> require changes to hardware enable state between changes to software clock
>> topology and hardware clock topology.
>>
>> The options to achieve the above are:
>> 1. Grab the enable lock before changing software/hardware topology and
>>     release it afterwards.
>> 2. Keep the clock enabled for the duration of software/hardware topology
>>     change so that any additional enable/disable calls don't try to change
>>     the hardware state. Once the topology change is complete, the clock can
>>     be put back in its original enable state.
>>
>> Option (1) is not an acceptable solution since the set_parent() ops might
>> need to sleep.
>>
>> Therefore, this patch implements option (2).
>>
>> This patch doesn't violate any API semantics. clk_disable() doesn't
>> guarantee that the clock is actually disabled. So, no clients of a clock
>> can assume that a clock is disabled after their last call to clk_disable().
>> So, enabling the clock during a parent change is not a violation of any API
>> semantics.
>>
>> This also has the nice side effect of simplifying the error handling code.
>>
>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>
> Updated to this version in clk-next.
>

Thanks Mike. I forgot to add the Ack by Ulf. Would be nice if you can 
put that in.

Btw, I did send this email to the list. But looks like this mail is 
wedged in the series of tubes in the arm mailing list.

-Saravana


-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From sergei.shtylyov at cogentembedded.com  Thu May 16 17:34:04 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 17 May 2013 01:34:04 +0400
Subject: [PATCH v4 3/3] ARM: shmobile: BOCK-W: enable VIN and ML86V7667 in
 defconfig
In-Reply-To: <201305170122.33996.sergei.shtylyov@cogentembedded.com>
References: <201305170122.33996.sergei.shtylyov@cogentembedded.com>
Message-ID: <201305170134.05547.sergei.shtylyov@cogentembedded.com>

From: Vladimir Barinov <vladimir.barinov at cogentembedded.com>

Add the VIN and ML86V7667 drivers to 'bockw_defconfig'.

Signed-off-by: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
 arch/arm/configs/bockw_defconfig |    7 +++++++
 1 file changed, 7 insertions(+)

Index: renesas/arch/arm/configs/bockw_defconfig
===================================================================
--- renesas.orig/arch/arm/configs/bockw_defconfig
+++ renesas/arch/arm/configs/bockw_defconfig
@@ -76,6 +76,13 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HWMON is not set
 CONFIG_I2C=y
 CONFIG_I2C_RCAR=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_VIDEO_RCAR_VIN=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_VIDEO_ML86V7667=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_EHCI_HCD=y


From sergei.shtylyov at cogentembedded.com  Thu May 16 17:41:59 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 17 May 2013 01:41:59 +0400
Subject: [PATCH v2] ARM: shmobile: BOCK-W: add Ether support
Message-ID: <201305170141.59791.sergei.shtylyov@cogentembedded.com>

Register Ether device from bockw_init(), passing the platform data to it, adding
only the RMII pin group to bockw_pinctrl_map[].  Although the LINK signal exists
on the board, it's connected to the link/activity LED  output of the PHY, thus
the link disappears and reappears after each packet. We'd be better off ignoring
such signal and getting the link state from the PHY indirectly.

Also, Ether has pin conflict with VIN1, so the latter is not registered when the
'sh_eth' driver is enabled now.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

---
The patch is atop of Simon's 'renesas.git' repo, 'renesas-next-20130515v2' tag
and my recent yet unapplied patches.

Note that it's compile and run time dependent on the current Linus' tree. 

Changes from the original posting:
- refreshed the patch.

 arch/arm/mach-shmobile/board-bockw.c |   22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

Index: renesas/arch/arm/mach-shmobile/board-bockw.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/board-bockw.c
+++ renesas/arch/arm/mach-shmobile/board-bockw.c
@@ -67,6 +67,20 @@ static struct sh_mobile_sdhi_info sdhi0_
 
 static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
 
+static struct sh_eth_plat_data ether_platform_data __initdata = {
+	.phy		= 0x01,
+	.edmac_endian	= EDMAC_LITTLE_ENDIAN,
+	.register_type	= SH_ETH_REG_FAST_RCAR,
+	.phy_interface	= PHY_INTERFACE_MODE_RMII,
+	/*
+	 * Although the LINK signal is available on the board, it's connected to
+	 * the link/activity LED output of the PHY, thus the link disappears and
+	 * reappears after each packet.  We'd be better off ignoring such signal
+	 * and getting the link state from the PHY indirectly.
+	 */
+	.no_ether_link	= 1,
+};
+
 static struct rcar_vin_platform_data vin_platform_data __initdata = {
 	.flags	= RCAR_VIN_BT656,
 };
@@ -87,6 +101,9 @@ BOCKW_CAMERA(0);
 BOCKW_CAMERA(1);
 
 static const struct pinctrl_map bockw_pinctrl_map[] = {
+	/* Ether */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778",
+				  "ether_rmii", "ether"),
 	/* SCIF0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 				  "scif0_data_a", "scif0"),
@@ -129,8 +146,11 @@ static void __init bockw_init(void)
 	r8a7778_init_irq_extpin(1);
 	r8a7778_add_standard_devices();
 	r8a7778_add_usb_phy_device(&usb_phy_platform_data);
+	r8a7778_add_ether_device(&ether_platform_data);
 	r8a7778_add_vin_device(0, &vin_platform_data);
-	r8a7778_add_vin_device(1, &vin_platform_data);
+	/* VIN1 has a pin conflict with Ether */
+	if (!IS_ENABLED(CONFIG_SH_ETH))
+		r8a7778_add_vin_device(1, &vin_platform_data);
 	platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0,
 				      &iclink0_ml86v7667,
 				      sizeof(iclink0_ml86v7667));


From tony at atomide.com  Thu May 16 17:44:31 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 May 2013 14:44:31 -0700
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
Message-ID: <20130516214430.GN5600@atomide.com>

* Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> > * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> > > I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> > > 
> > > [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> > > [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> > > [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> > > 
> > > The error is coming from regmap code. According to git bisect, it is
> > > caused by:
> > > 
> > > 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> > > 	Author: Jon Hunter <jon-hunter at ti.com>
> > > 	Date:   Fri Mar 1 11:22:47 2013 -0600
> > > 
> > > 	    gpio/omap: convert gpio irq domain to linear mapping
> > > 
> > > The commit does not anymore revert cleanly, and I haven't yet tried
> > > crafting a manual revert, so any fix proposals/ideas are welcome...
> > 
> > Hmm this might be a bit trickier to fix. Obviously the real solution
> > is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> > 
> > For the -rc cycle, it might be possible to fix this by adding a
> > different irq_to_gpio() and gpio_to_irq() functions for omap1.
> 
> The commit reverts cleanly if we also revert
> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
> service routine), which seems to be just some minor optimization. The
> result is below, and with it 770 works again.

Hmm in this case it seems that we should just fix it rather than go back
to the old code, so let's take a look at that first.

Regards,

Tony


From arnd at arndb.de  Thu May 16 18:09:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 00:09:46 +0200
Subject: [PATCH V2 1/2] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1368200883-15668-1-git-send-email-csd@broadcom.com>
References: <1368200883-15668-1-git-send-email-csd@broadcom.com>
Message-ID: <201305170009.46244.arnd@arndb.de>

On Friday 10 May 2013, Christian Daudt wrote:
> +
> +struct sdhci_bcm_kona_cfg {
> +	unsigned int	max_freq;
> +	int		is_8bit;
> +	int		irq;
> +	int		cd_gpio;
> +	int		wp_gpio;
> +	int		non_removable;
> +};

I see no use for this structure to be separate: a lot of the fields are
duplicated in the sdhci_host, or should just get merged into
sdhci_bcm_kona_dev.

> +struct sdhci_bcm_kona_dev {
> +	struct sdhci_bcm_kona_cfg *cfg;
> +	struct device *dev;
> +	struct sdhci_host *host;
> +	struct clk *peri_clk;
> +	struct clk *sleep_clk;
> +};

The *dev and *host members in this structure are redundant, just
allocate it together with sdhci_host and use use container_of()
to get from the sdhci_host back it it.

> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
> +{
> +	unsigned int val;
> +
> +	/* enable the interrupt from the IP core */
> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
> +	val |= KONA_SDHOST_IP;
> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
> +
> +	/* Enable the AHB clock gating module to the host */
> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> +	val |= KONA_SDHOST_EN;
> +
> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	mdelay(1);
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> +}

Why not use msleep() instead of mdelay() here?

> +static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
> +{
> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
> +	u32 val;
> +	unsigned long flags;
> +
> +	/* this function can be called from various contexts including ISR */
> +	spin_lock_irqsave(&host->lock, flags);
> +	/* Ensure SD bus scanning to detect media change */
> +	host->mmc->rescan_disable = 0;
> +
> +	/*
> +	 * Back-to-Back register write needs a delay of min 10uS.
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 * We keep 20uS
> +	 */
> +	udelay(20);
> +	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);

Does the delay have to be done with interrupts disabled? That is not particularly
nice.

I hope the hardware designers have been appropriately punished for the creating
such crap.
> +static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
> +				u8 power_mode)
> +{
> +	if (power_mode == MMC_POWER_OFF)
> +		return;
> +	else
> +		mdelay(10);
> +}

This requires at the minimum a comment about why the mdelay is needed.
Maybe we can change the set_ios function so we never need to call it
in atomic context.

> +static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
> +			struct platform_device *pdev)
> +{
> +	struct sdhci_bcm_kona_cfg *cfg;
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 temp;

fold this function into probe()

> +	if (!np)
> +		return NULL;

impossible

> +	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
> +	if (!cfg) {
> +		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
> +		return NULL;
> +	}

Not needed

> +static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
> +{
> +	const struct of_device_id *match;

constant, so not needed.

> +	struct sdhci_bcm_kona_cfg *kona_cfg = NULL;

No need to initialize this.

> +	const struct sdhci_pltfm_data *plat_data;

make it global.

> +	struct sdhci_bcm_kona_dev *kona_dev = NULL;

No need to initialize this.

> +	kona_dev = devm_kzalloc(dev, sizeof(*kona_dev), GFP_KERNEL);
> +	if (!kona_dev) {
> +		dev_err(dev, "Can't allocate kona_dev\n");
> +		ret = -ENOMEM;
> +		goto err_pltfm_free;
> +	}

It is rather silly to have the base sdhci code allocate extra
memory for the platform drivers but then require an extra allocation.
Better change the sdhci_pltfm_init function to let you pass the extra
allocation size.

> +MODULE_AUTHOR("Broadcom");

No person?

	Arnd


From ezequiel.garcia at free-electrons.com  Thu May 16 18:15:31 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Thu, 16 May 2013 19:15:31 -0300
Subject: [PATCH] drivers: memory: Introduce Marvell EBU Device Bus driver
In-Reply-To: <20130513201234.GB31290@titan.lakedaemon.net>
References: <1366744886-3019-1-git-send-email-elezegarcia@gmail.com>
 <20130423194822.GA7214@kroah.com> <20130423195556.GA3335@localhost>
 <20130513201234.GB31290@titan.lakedaemon.net>
Message-ID: <20130516221530.GA15738@localhost>

Hi Greg,

On Mon, May 13, 2013 at 04:12:34PM -0400, Jason Cooper wrote:
> On Tue, Apr 23, 2013 at 04:55:58PM -0300, Ezequiel Garcia wrote:
> > On Tue, Apr 23, 2013 at 12:48:22PM -0700, Greg KH wrote:
> > > On Tue, Apr 23, 2013 at 04:21:26PM -0300, Ezequiel Garcia wrote:
[...]
> > > It's way too late for new drivers for 3.10, sorry.  I'll hold on to this
> > > and merge it to my trees after 3.10-rc1 is out for inclusion in 3.11.
> > > 
> > 
> > That's fine, no problem.
> 
> I'm dropping this from my tree as Greg has said he would take it.
> 

Do you plan to take this through your trees? Which tree should I be
monitoring? If at all possible, I'd love to see this in linux-next
somewhat soon, to avoid future problems.

Thanks!
-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com


From sboyd at codeaurora.org  Thu May 16 18:22:36 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 16 May 2013 15:22:36 -0700
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <5194AD63.9020804@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
 <51940CAF.6010808@codeaurora.org> <5194AD63.9020804@imgtec.com>
Message-ID: <51955C2C.5060705@codeaurora.org>

On 05/16/13 02:56, James Hogan wrote:
> On 15/05/13 23:31, Stephen Boyd wrote:
>> On 05/10/13 08:02, James Hogan wrote:
>>> This adds a metag architecture specific clk-gate and clk-mux which
>>> extends the generic ones to use global lock2 to protect the register
>>> fields. It is common with metag to have an RTOS running on a different
>>> thread or core with access to different bits in the same register (which
>>> contain clock gate/switch bits for other clocks). Access to such
>>> registers must be serialised with a global lock such as the one provided
>>> by the metag architecture port in <asm/global_lock.h>
>>>
>>> RFC because despite extending the generic clocks there's still a bit of
>>> duplicated code necessary. One alternative is to add special cases to
>>> the generic clock components for when a global or callback function
>>> based lock is desired instead of a spinlock, but I wasn't sure if that
>>> sort of hack would really be appreciated in the generic drivers.
>>>
>>> Comments?
>> Can you please Cc the devicetree mailing list when proposing new bindings?
> Erm, I think it was on Cc (devicetree-discuss at lists.ozlabs.org yeh?)

I added them in my reply.

>
>> Your patchset brings up a question I've had which is if we should be
>> putting the bits and register width information in devicetree at all. On
>> the one hand it's nice to not have anything in C code, just iterate over
>> nodes and register clocks. On the other hand, it's the first time I've
>> seen anyone put the register interface into devicetree. From what I can
>> tell, the regulator bindings have put at most the register base and
>> physical properties like enable-time, max voltage, etc., but not what
>> bits are needed to enable/disable a regulator. Also I thought I read
>> somewhere that reg properties shouldn't overlap each other, so if you
>> ever have two clocks living in the same register we're going to violate
>> that.
> Oh, I wasn't aware of that limitation.
>
> The SoC I'm working with has some registers full of clock enable bits (I
> guess one could have a gate array component with up to 32 clock inputs
> and outputs) and some registers full of clock mux switch bits (that
> would get really messy to define as a block since each bit switches
> between 2 parents, and some of the parents are other clock muxes in the
> same block). Some registers contain a bunch of low power related bits
> together, including clock enable bits in the same register as various
> pinconf settings which is used by a separate pinctrl driver.
>

I have similar hardware and so I would like to hear what the devicetree
knowledgeable people think about it. Hopefully Rob or Grant can shed
some light here.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From mturquette at linaro.org  Thu May 16 18:29:57 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 16 May 2013 15:29:57 -0700
Subject: [PATCH v2] clk: Fix race condition between clk_set_parent and
 clk_enable()
In-Reply-To: <5195502B.3070003@codeaurora.org>
References: <1367383328-25700-1-git-send-email-skannan@codeaurora.org>
 <1368677244-7279-1-git-send-email-skannan@codeaurora.org>
 <20130516204455.12127.75296@quantum> <5195502B.3070003@codeaurora.org>
Message-ID: <20130516222957.12127.25336@quantum>

Quoting Saravana Kannan (2013-05-16 14:31:23)
> On 05/16/2013 01:44 PM, Mike Turquette wrote:
> > Quoting Saravana Kannan (2013-05-15 21:07:24)
> >> Without this patch, the following race condition is possible.
> >> * clk-A has two parents - clk-X and clk-Y.
> >> * All three are disabled and clk-X is current parent.
> >> * Thread A: clk_set_parent(clk-A, clk-Y).
> >> * Thread A: <snip execution flow>
> >> * Thread A: Grabs enable lock.
> >> * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y.
> >> * Thread A: Updates clk-A SW parent to clk-Y
> >> * Thread A: Releases enable lock.
> >> * Thread B: clk_enable(clk-A).
> >> * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns.
> >>
> >> clk-A is now enabled in software, but not clocking in hardware since the
> >> hardware parent is still clk-X.
> >>
> >> The only way to avoid race conditions between clk_set_parent() and
> >> clk_enable/disable() is to ensure that clk_enable/disable() calls don't
> >> require changes to hardware enable state between changes to software clock
> >> topology and hardware clock topology.
> >>
> >> The options to achieve the above are:
> >> 1. Grab the enable lock before changing software/hardware topology and
> >>     release it afterwards.
> >> 2. Keep the clock enabled for the duration of software/hardware topology
> >>     change so that any additional enable/disable calls don't try to change
> >>     the hardware state. Once the topology change is complete, the clock can
> >>     be put back in its original enable state.
> >>
> >> Option (1) is not an acceptable solution since the set_parent() ops might
> >> need to sleep.
> >>
> >> Therefore, this patch implements option (2).
> >>
> >> This patch doesn't violate any API semantics. clk_disable() doesn't
> >> guarantee that the clock is actually disabled. So, no clients of a clock
> >> can assume that a clock is disabled after their last call to clk_disable().
> >> So, enabling the clock during a parent change is not a violation of any API
> >> semantics.
> >>
> >> This also has the nice side effect of simplifying the error handling code.
> >>
> >> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> >
> > Updated to this version in clk-next.
> >
> 
> Thanks Mike. I forgot to add the Ack by Ulf. Would be nice if you can 
> put that in.
> 

Yes I picked up the Ack.

Regards,
Mike

> Btw, I did send this email to the list. But looks like this mail is 
> wedged in the series of tubes in the arm mailing list.
> 
> -Saravana
> 
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation


From sameo at linux.intel.com  Thu May 16 18:43:37 2013
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 17 May 2013 00:43:37 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130515090449.GA3494@gmail.com>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
Message-ID: <20130516224337.GZ22822@zurbaran>

Hi Lee,

On Wed, May 15, 2013 at 10:04:49AM +0100, Lee Jones wrote:
> Hi Sam,
> 
> Since v1 of my MFD -fixes pull-request, I have applied a few more
> patches which really should be entered into the -rc:s. As it appears
> that you have not yet pulled v1, I figured sending a v2 in its place
> would be appropriate, so here it is.
This almost looks good, I just have one comment:

> Fabio Baltieri (5):
>       mfd: abx500-core: Fix sparse warning
>       mfd: ab8500-sysctrl: Fix sparse warning
>       mfd: ab8500-sysctrl: Set sysctrl_dev during probe
>       mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
Unless I'm missing something here, this one is not really rcN material, so
I'd appreciate if you could queue it to your for-mfd branch instead.

The rest is pulled and applied, thanks again.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From festevam at gmail.com  Thu May 16 20:10:52 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 16 May 2013 21:10:52 -0300
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <519534A5.2070209@free-electrons.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <1368713639-21485-2-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>
 <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
 <519534A5.2070209@free-electrons.com>
Message-ID: <CAOMZO5B_8TPJK9MLWyF5SiE=afKdfmg-ff6qEJOcq_R5VqhAjg@mail.gmail.com>

Hi Alexandre,

On Thu, May 16, 2013 at 4:33 PM, Alexandre Belloni
<alexandre.belloni at free-electrons.com> wrote:

> Would that be related to the timeouts I'm observing ?
>
> http://www.spinics.net/lists/linux-i2c/msg11985.html
>
> I didn't have the time to have a look at it yet. I was planning to hook
> up a logic analyzer someday in june to debug it. It seems that there is
> a 1 second timeout with each i2c message that are sent.

Yes, I see the same one second timeout for each i2c transaction here.

Regards,

Fabio Estevam


From 21cnbao at gmail.com  Thu May 16 20:30:15 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 17 May 2013 08:30:15 +0800
Subject: [PATCH] ARM: prima2: return rather than panic on missing DT nodes
In-Reply-To: <CAL_JsqL_z99EfT=3E32c0AS6fbwqOyTb7n+AzySmzJNyMCab3w@mail.gmail.com>
References: <1368719437-28287-1-git-send-email-robherring2@gmail.com>
 <519510A4.8090904@st.com>
 <CAL_JsqL_z99EfT=3E32c0AS6fbwqOyTb7n+AzySmzJNyMCab3w@mail.gmail.com>
Message-ID: <CAGsJ_4w_a=vXMeh-vbRKwD+KGqRNthx-zne=DR3iR7B-WqiUPw@mail.gmail.com>

2013/5/17 Rob Herring <robherring2 at gmail.com>:
> On Thu, May 16, 2013 at 12:00 PM, Srinivas KANDAGATLA
> <srinivas.kandagatla at st.com> wrote:
>> Hi Rob,
>>
>> I was just testing multi_v7_defconfig and noticed that the code is still
>> doing early_initcall and postcore_initcalls. Which IMO is NOK for
>> multiplatforms.
>>
>> I was just about to send my patch and just noticed your patch.
>>
>>
>> On 16/05/13 16:50, Rob Herring wrote:
>>> From: Rob Herring <rob.herring at calxeda.com>
>>>
>>> Missing nodes is a normal condition in multi-platform kernels when we boot
>>> on other platforms. So remove the panic and just return if we don't find
>>> a DT node.
>>>
>>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>>> Cc: Barry Song <baohua.song at csr.com>
>>> ---
>>>  arch/arm/mach-prima2/pm.c   | 2 +-
>>>  arch/arm/mach-prima2/rstc.c | 2 +-
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
>>> index 9936c18..a8003e2 100644
>>> --- a/arch/arm/mach-prima2/pm.c
>>> +++ b/arch/arm/mach-prima2/pm.c
>>> @@ -102,7 +102,7 @@ static int __init sirfsoc_of_pwrc_init(void)
>>>
>> First thing is the mach code should not even attempt to run this
>> function in first place.
>>
>> I think the correct fix for this is to move all the postcore_initcalls
>> and early_initcalls to callbacks in MACHINE.
>
> Agreed, but that may cause some init ordering issues. So I'll leave
> that to someone that knows this platform and can test it.

what if i really want the system to panic early when these is no pwrc
node?  then we can check the machine , if it is sirf, we panic the
kernel. that results in ugly source codes.

        np = of_find_matching_node(NULL, pwrc_ids);
        if (!np)
-               panic("unable to find compatible pwrc node in dtb\n");
+               return -ENODEV;

then it turns out that moving the codes to callbacks of machine is the
right way. i will take care the init ordering issues.

>
> Rob
>

-barry


From 21cnbao at gmail.com  Thu May 16 20:31:24 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 17 May 2013 08:31:24 +0800
Subject: [PATCH] ARM: prima2: return rather than panic on missing DT nodes
In-Reply-To: <CAL_JsqL_z99EfT=3E32c0AS6fbwqOyTb7n+AzySmzJNyMCab3w@mail.gmail.com>
References: <1368719437-28287-1-git-send-email-robherring2@gmail.com>
 <519510A4.8090904@st.com>
 <CAL_JsqL_z99EfT=3E32c0AS6fbwqOyTb7n+AzySmzJNyMCab3w@mail.gmail.com>
Message-ID: <CAGsJ_4xyLqVRoOa7btKuvPn01KjJF=rXvMEu5XYzPX+UH1S2Wg@mail.gmail.com>

2013/5/17 Rob Herring <robherring2 at gmail.com>:
> On Thu, May 16, 2013 at 12:00 PM, Srinivas KANDAGATLA
> <srinivas.kandagatla at st.com> wrote:
>> Hi Rob,
>>
>> I was just testing multi_v7_defconfig and noticed that the code is still
>> doing early_initcall and postcore_initcalls. Which IMO is NOK for
>> multiplatforms.
>>
>> I was just about to send my patch and just noticed your patch.

will you send? i can test.

>>
>>
>> On 16/05/13 16:50, Rob Herring wrote:
>>> From: Rob Herring <rob.herring at calxeda.com>
>>>
>>> Missing nodes is a normal condition in multi-platform kernels when we boot
>>> on other platforms. So remove the panic and just return if we don't find
>>> a DT node.
>>>
>>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>>> Cc: Barry Song <baohua.song at csr.com>
>>> ---
>>>  arch/arm/mach-prima2/pm.c   | 2 +-
>>>  arch/arm/mach-prima2/rstc.c | 2 +-
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
>>> index 9936c18..a8003e2 100644
>>> --- a/arch/arm/mach-prima2/pm.c
>>> +++ b/arch/arm/mach-prima2/pm.c
>>> @@ -102,7 +102,7 @@ static int __init sirfsoc_of_pwrc_init(void)
>>>
>> First thing is the mach code should not even attempt to run this
>> function in first place.
>>
>> I think the correct fix for this is to move all the postcore_initcalls
>> and early_initcalls to callbacks in MACHINE.
>
> Agreed, but that may cause some init ordering issues. So I'll leave
> that to someone that knows this platform and can test it.

what if we want the system to keep the behavior of panic when these is
no pwrc node?  then we can check the machine , if it is sirf, we panic
the kernel. that results in ugly source codes.

        np = of_find_matching_node(NULL, pwrc_ids);
        if (!np)  {
               if (sirf platform)
                              panic("unable to find compatible pwrc
node in dtb\n");
               else
                              return -ENODEV;
      }

it turns out that moving the codes to callbacks of machine is the
right way. i will take care the init ordering issues.

>
> Rob
>

-barry


From rusty at rustcorp.com.au  Thu May 16 19:52:58 2013
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 17 May 2013 09:22:58 +0930
Subject: [PATCH V2 1/3] virtio: console: Add emergency writeonly register
 to config space
In-Reply-To: <20130516123746.GA4744@amit.redhat.com>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-2-git-send-email-pranavkumar@linaro.org>
 <20130516123746.GA4744@amit.redhat.com>
Message-ID: <871u96a3dx.fsf@rustcorp.com.au>

Amit Shah <amit.shah at redhat.com> writes:
> On (Mon) 06 May 2013 [17:49:49], Pranavkumar Sawargaonkar wrote:
>> This patch adds an emerg_wr register (writeonly) in config space
>> of virtio console device which can be used for debugging.
>> 
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>> Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
>
> OK, this change by itself looks harmless.
>
> Acked-by: Amit Shah <amit.shah at redhat.com>
>
> 		Amit

Thanks.  This is queued for *next* merge window.

Cheers,
Rusty.


From shawn.guo at linaro.org  Thu May 16 21:53:57 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 09:53:57 +0800
Subject: [PATCH 16/20] ARM: mxs: Remove init_irq declaration in machine
 description
In-Reply-To: <1368545933-7430-17-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-17-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130517015355.GB3893@S2101-09.ap.freescale.net>

On Tue, May 14, 2013 at 05:38:49PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for mxs as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Applied, thanks.



From 21cnbao at gmail.com  Thu May 16 21:58:24 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 17 May 2013 09:58:24 +0800
Subject: [PATCH] spi: sirf: fix the issue while transferring more than 256
 words
In-Reply-To: <20130516172358.GA1627@sirena.org.uk>
References: <1363592828-6347-1-git-send-email-Barry.Song@csr.com>
 <CAGsJ_4wamqzwLZkUz4h6ex=oVQZhzhw7S6r41wt9tTUoMR=aXw@mail.gmail.com>
 <20130516172358.GA1627@sirena.org.uk>
Message-ID: <CAGsJ_4z9=2RYkwntnCD4X-JVsZoYEgzwdWO_uryp3RpbEHu7fA@mail.gmail.com>

2013/5/17 Mark Brown <broonie at kernel.org>:
> On Wed, May 15, 2013 at 08:59:47PM +0800, Barry Song wrote:
>> ping Mark, Ping Grant.
>
> Don't top post, don't send contentless pings.  At a guess you didn't CC
> me...

yes. i missed you in CC. sorry for that, Mark. so do you want me to resend it?

-barry


From shawn.guo at linaro.org  Thu May 16 21:58:44 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 09:58:44 +0800
Subject: [PATCH] ARM: imx: apf51: add nfc support
In-Reply-To: <1368699931-9977-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
References: <1368699931-9977-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
Message-ID: <20130517015842.GD3893@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 12:25:31PM +0200, Gwenhael Goavec-Merou wrote:
> 
> Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>

Applied, thanks.

> ---
>  arch/arm/boot/dts/imx51-apf51.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
> index 2bcf698..8f7f9ac 100644
> --- a/arch/arm/boot/dts/imx51-apf51.dts
> +++ b/arch/arm/boot/dts/imx51-apf51.dts
> @@ -45,6 +45,13 @@
>  	status = "okay";
>  };
>  
> +&nfc {
> +	nand-bus-width = <8>;
> +	nand-ecc-mode = "hw";
> +	nand-on-flash-bbt;
> +	status = "okay";
> +};
> +
>  &uart3 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_uart3_2>;
> -- 
> 1.8.1.5
> 



From shawn.guo at linaro.org  Thu May 16 21:58:27 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 09:58:27 +0800
Subject: [PATCH] i.MX6: Documentation: update from fsl,card-wired to
 non-removable
In-Reply-To: <1368687094-11385-1-git-send-email-dirk.behme@de.bosch.com>
References: <1368687094-11385-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <20130517015825.GC3893@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 08:51:34AM +0200, Dirk Behme wrote:
> With the commit 7f217794f (mmc: dt: Consolidate DT bindings),
> the device tree properties used by various device drivers
> for SD/MMC host controllers were standardized.  One of the changes
> was that the property "fsl,card-wired", previously used by the
> Freescale driver, was replaced with "non-removable". Fix the example
> documentation regarding this.
> 
> Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>

Applied, thanks.



From shawn.guo at linaro.org  Thu May 16 22:03:52 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 10:03:52 +0800
Subject: [PATCH] can: flexcan: allow compilation on arm and powerpc
In-Reply-To: <1368711756-22324-1-git-send-email-mkl@pengutronix.de>
References: <1368711756-22324-1-git-send-email-mkl@pengutronix.de>
Message-ID: <20130517020351.GE3893@S2101-09.ap.freescale.net>

Hi Marc,

On Thu, May 16, 2013 at 03:42:36PM +0200, Marc Kleine-Budde wrote:
> This patch removes the Kconfig symbols HAVE_CAN_FLEXCAN and
> IMX_HAVE_PLATFORM_FLEXCAN from arch/{arm,powerpc} and allowing compilation on
> all arm and powerpc platforms.

I'm generally fine with the approach.  But with Kconfig symbol
IMX_HAVE_PLATFORM_FLEXCAN removed, how does the build of
platform-flexcan.o work?

arch/arm/mach-imx/devices/Makefile:obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o

Shawn



From ming.lei at canonical.com  Thu May 16 22:16:40 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 17 May 2013 10:16:40 +0800
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
Message-ID: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>

Hi,

The commit a43cb95d5(dump_stack: unify debug information printed by show_regs())
caused ARM perf regression, then 'perf top' outputs mistakenly, see
[1].  The correct
output should be [2], which can be got after reverting the commit or
doing it partly
by the one line change below:

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..89bc3a4 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -225,7 +225,7 @@ void __show_regs(struct pt_regs *regs)
        unsigned long flags;
        char buf[64];

-       show_regs_print_info(KERN_DEFAULT);
+       //show_regs_print_info(KERN_DEFAULT);


Looks a bit weird, anyone can give a hint?


Thanks,
--
Ming Lei

[1], 'perf top' mistaken output
Samples: 17K of event 'cpu-clock', Event count (approx.): 3516532661
 97.51%  [smsc95xx]            [k] 0x013645b8
  0.21%  libc-2.15.so          [.] strstr
  0.14%  libc-2.15.so          [.] strchr
  0.12%  libc-2.15.so          [.] strcmp
  0.12%  perf                  [.] perf_evsel__parse_sample
  0.09%  perf                  [.] symbols__insert
  0.09%  perf                  [.] dso__load_sym
  0.08%  perf                  [.] perf_top__mmap_read_idx
  0.08%  perf                  [.] symbol_filter
  0.07%  libc-2.15.so          [.] memchr
  0.07%  libc-2.15.so          [.] memset
  0.07%  perf                  [.] internal_cplus_demangle
  0.06%  perf                  [.] sort__dso_cmp
  0.06%  libc-2.15.so          [.] strncmp
  0.06%  perf                  [.] add_hist_entry.isra.2
  0.06%  perf                  [.] dso__find_symbol
  0.06%  libc-2.15.so          [.] _int_malloc
  0.05%  perf                  [.] 0x00010d60
  0.04%  libc-2.15.so          [.] memcpy
  0.04%  perf                  [.] map__find_symbol
  0.04%  perf                  [.] rb_next
  0.04%  libelf-0.154.so       [.] gelf_getsym


[2], 'perf top' correct output
Samples: 46K of event 'cpu-clock', Event count (approx.): 937128704
 96.44%  [kernel]            [k] cpuidle_enter_state
  0.19%  libc-2.15.so        [.] strstr
  0.16%  [kernel]            [k] kallsyms_expand_symbol.clone.0
  0.13%  [kernel]            [k] _raw_spin_unlock_irq
  0.13%  [kernel]            [k] _raw_spin_unlock_irqrestore
  0.10%  [kernel]            [k] format_decode
  0.10%  perf                [.] perf_top__mmap_read_idx
  0.10%  perf                [.] rb_next
  0.09%  perf                [.] dso__find_symbol
  0.08%  [kernel]            [k] vsnprintf
  0.08%  perf                [.] add_hist_entry.isra.2
  0.08%  libc-2.15.so        [.] strcmp
  0.08%  libc-2.15.so        [.] memchr
  0.07%  perf                [.] sort__dso_cmp
  0.07%  libc-2.15.so        [.] strchr
  0.07%  [kernel]            [k] number.clone.1
  0.07%  perf                [.] map__process_kallsym_symbol
  0.06%  [kernel]            [k] memcpy
  0.05%  perf                [.] perf_evsel__parse_sample
  0.05%  libc-2.15.so        [.] _int_malloc
  0.05%  libc-2.15.so        [.] memcpy
  0.05%  perf                [.] perf_event__preprocess_sample


From Baohua.Song at csr.com  Thu May 16 22:19:37 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Fri, 17 May 2013 10:19:37 +0800
Subject: [PATCH v2] ASoC: dfbmcs320: make the driver common for other BT
 modules
Message-ID: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>

DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
we don't want everyone to have a seperate codec driver. anyway, the
feature of Bluetooth handsfree is same on all platforms, so this patch
makes the DFBM-CS320 driver become a common BT handsfree driver.

Cc: Graeme Gregory <graeme at openmoko.org>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2: keep the device id list

 sound/soc/codecs/Kconfig                         |  4 +--
 sound/soc/codecs/Makefile                        |  4 +--
 sound/soc/codecs/{dfbmcs320.c => bt-handsfree.c} | 37 +++++++++++++++---------
 sound/soc/samsung/neo1973_wm8753.c               |  2 +-
 4 files changed, 28 insertions(+), 19 deletions(-)
 rename sound/soc/codecs/{dfbmcs320.c => bt-handsfree.c} (51%)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index d8c4f3d..618928a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -40,7 +40,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_DA7213 if I2C
 	select SND_SOC_DA732X if I2C
 	select SND_SOC_DA9055 if I2C
-	select SND_SOC_DFBMCS320
+	select SND_SOC_BT_HANDSFREE
 	select SND_SOC_ISABELLE if I2C
 	select SND_SOC_JZ4740_CODEC
 	select SND_SOC_LM4857 if I2C
@@ -263,7 +263,7 @@ config SND_SOC_DA732X
 config SND_SOC_DA9055
 	tristate
 
-config SND_SOC_DFBMCS320
+config SND_SOC_BT_HANDSFREE
 	tristate
 
 config SND_SOC_DMIC
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 49ff127..23a8c06 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -27,7 +27,7 @@ snd-soc-da7210-objs := da7210.o
 snd-soc-da7213-objs := da7213.o
 snd-soc-da732x-objs := da732x.o
 snd-soc-da9055-objs := da9055.o
-snd-soc-dfbmcs320-objs := dfbmcs320.o
+snd-soc-bt-handsfree-objs := bt-handsfree.o
 snd-soc-dmic-objs := dmic.o
 snd-soc-isabelle-objs := isabelle.o
 snd-soc-jz4740-codec-objs := jz4740.o
@@ -154,7 +154,7 @@ obj-$(CONFIG_SND_SOC_DA7210)	+= snd-soc-da7210.o
 obj-$(CONFIG_SND_SOC_DA7213)	+= snd-soc-da7213.o
 obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
 obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
-obj-$(CONFIG_SND_SOC_DFBMCS320)	+= snd-soc-dfbmcs320.o
+obj-$(CONFIG_SND_SOC_BT_HANDSFREE)	+= snd-soc-bt-handsfree.o
 obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
 obj-$(CONFIG_SND_SOC_ISABELLE)	+= snd-soc-isabelle.o
 obj-$(CONFIG_SND_SOC_JZ4740_CODEC)	+= snd-soc-jz4740-codec.o
diff --git a/sound/soc/codecs/dfbmcs320.c b/sound/soc/codecs/bt-handsfree.c
similarity index 51%
rename from sound/soc/codecs/dfbmcs320.c
rename to sound/soc/codecs/bt-handsfree.c
index 4f4f7f4..7ec784a 100644
--- a/sound/soc/codecs/dfbmcs320.c
+++ b/sound/soc/codecs/bt-handsfree.c
@@ -1,5 +1,5 @@
 /*
- * Driver for the DFBM-CS320 bluetooth module
+ * Driver for generic Bluetooth Handsfree
  * Copyright 2011 Lars-Peter Clausen <lars at metafoo.de>
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -15,8 +15,8 @@
 
 #include <sound/soc.h>
 
-static struct snd_soc_dai_driver dfbmcs320_dai = {
-	.name = "dfbmcs320-pcm",
+static struct snd_soc_dai_driver bt_handsfree_dai = {
+	.name = "bt-handsfree-pcm",
 	.playback = {
 		.channels_min = 1,
 		.channels_max = 1,
@@ -31,32 +31,41 @@ static struct snd_soc_dai_driver dfbmcs320_dai = {
 	},
 };
 
-static struct snd_soc_codec_driver soc_codec_dev_dfbmcs320;
+static struct snd_soc_codec_driver soc_codec_dev_bt_handsfree;
 
-static int dfbmcs320_probe(struct platform_device *pdev)
+static int bt_handsfree_probe(struct platform_device *pdev)
 {
-	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_dfbmcs320,
-			&dfbmcs320_dai, 1);
+	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_bt_handsfree,
+			&bt_handsfree_dai, 1);
 }
 
-static int dfbmcs320_remove(struct platform_device *pdev)
+static int bt_handsfree_remove(struct platform_device *pdev)
 {
 	snd_soc_unregister_codec(&pdev->dev);
 
 	return 0;
 }
 
-static struct platform_driver dfmcs320_driver = {
+static struct platform_device_id bt_handsfree_driver_ids[] = {
+	{
+		.name		= "dfbmcs320",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(platform, bt_handsfree_driver_ids);
+
+static struct platform_driver bt_handsfree_driver = {
 	.driver = {
-		.name = "dfbmcs320",
+		.name = "bt-handsfree",
 		.owner = THIS_MODULE,
 	},
-	.probe = dfbmcs320_probe,
-	.remove = dfbmcs320_remove,
+	.probe = bt_handsfree_probe,
+	.remove = bt_handsfree_remove,
+	.id_table = bt_handsfree_driver_ids,
 };
 
-module_platform_driver(dfmcs320_driver);
+module_platform_driver(bt_handsfree_driver);
 
 MODULE_AUTHOR("Lars-Peter Clausen <lars at metafoo.de>");
-MODULE_DESCRIPTION("ASoC DFBM-CS320 bluethooth module driver");
+MODULE_DESCRIPTION("ASoC generic bluethooth handsfree driver");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/neo1973_wm8753.c b/sound/soc/samsung/neo1973_wm8753.c
index e591c38..3aefea4 100644
--- a/sound/soc/samsung/neo1973_wm8753.c
+++ b/sound/soc/samsung/neo1973_wm8753.c
@@ -373,7 +373,7 @@ static struct snd_soc_dai_link neo1973_dai[] = {
 { /* Voice via BT */
 	.name = "Bluetooth",
 	.stream_name = "Voice",
-	.cpu_dai_name = "dfbmcs320-pcm",
+	.cpu_dai_name = "bt-handsfree-pcm",
 	.codec_dai_name = "wm8753-voice",
 	.codec_name = "wm8753.0-001a",
 	.ops = &neo1973_voice_ops,
-- 
1.8.2.3



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From shawn.guo at linaro.org  Thu May 16 22:25:31 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 10:25:31 +0800
Subject: [PATCH 1/2] ARM: dts: imx: Remove custom dma-channel bindings
In-Reply-To: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20130517022529.GA8607@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 11:13:58AM -0300, Fabio Estevam wrote:
> Commit f30fb03 (ARM: dts: add generic DMA device tree binding for mxs-dma) added
> the generic DMA dt bindings, but missed to remove the old ones.
> 
> Remove the the old dma bindings.

I already had a patch [1] to remove those old DMA binding data (both
channel and interrupt number) from client device nodes.  And I'm waiting
for mxs-saif/pcm to be converted to generic DMA binding helper to apply
the patch.  Mark has queued mxs-saif conversion for 3.11, and I have to
wait for 3.11-rc1 to apply the dts cleanup.

Shawn

[1] http://thread.gmane.org/gmane.linux.alsa.devel/106027/focus=220815



From ming.lei at canonical.com  Thu May 16 22:28:23 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 17 May 2013 10:28:23 +0800
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
Message-ID: <CACVXFVPYsF3z6GajSeTSq6r0jbLrPWeGf9=0ckqC+uprF7wOiw@mail.gmail.com>

On Fri, May 17, 2013 at 10:16 AM, Ming Lei <ming.lei at canonical.com> wrote:
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index f219703..89bc3a4 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -225,7 +225,7 @@ void __show_regs(struct pt_regs *regs)
>         unsigned long flags;
>         char buf[64];
>
> -       show_regs_print_info(KERN_DEFAULT);
> +       //show_regs_print_info(KERN_DEFAULT);

Forget to mention, __show_regs() isn't run under both cases.

Thanks,
--
Ming Lei


From yamagata at plathome.co.jp  Thu May 16 22:18:10 2013
From: yamagata at plathome.co.jp (yamagata at plathome.co.jp)
Date: Fri, 17 May 2013 11:18:10 +0900 (JST)
Subject: [PATCH] arm: mvebu: enable the third USB interface on
 OpenBlocks AX3
In-Reply-To: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130517.111810.02327269.yamagata@plathome.co.jp>

Dear Mr. Petazzoni

> Besides the two "classic" USB interfaces with normal USB ports on the
> front side, the PlatHome OpenBlocks AX3 uses the third USB interface
> of the Marvell SoC in the mini-PCIe connector. This allows certain
> mini-PCIe cards to expose parts of their functionality as a USB
> peripheral.
> 
> This commit enables this third USB interface in the OpenBlocks AX3
> Device Tree, and also adds comments on top of the two other USB
> interfaces so that the Device Tree makes it clear which USB interface
> at the SoC level matches which USB interface visible on the board.

I see the following messages by dmesg with your patch for
linux-3.10-rc1 and 3.9.2.

...
usb 3-1: New USB device found, idVendor=0a5c, idProduct=219c
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 3-1: Product: Broadcom BCM2070 Bluetooth Device
usb 3-1: Manufacturer: Broadcom Corp
usb 3-1: SerialNumber: B4749F63C1B6
...
Bluetooth: Core ver 2.16
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
usbcore: registered new interface driver btusb
...

Best regards

Atsushi Yamagata
--- Atsushi Yamagata


From swarren at wwwdotorg.org  Thu May 16 22:49:28 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 20:49:28 -0600
Subject: [PATCH] ARM: bcm2835: enable CONFIG_LEDS_GPIO
Message-ID: <1368758969-26339-1-git-send-email-swarren@wwwdotorg.org>

Enable CONFIG_LEDS_GPIO and all options required to enable it, or make
the option useful.

This patch also regenerated bcm2835_defconfig, which removes two HW_RANDOM
entries, since they're enabled by default.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
 arch/arm/configs/bcm2835_defconfig |   14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index ce98721..898c030 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -61,8 +61,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_BCM2835=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BCM2835=y
@@ -75,6 +73,18 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
-- 
1.7.10.4



From swarren at wwwdotorg.org  Thu May 16 22:50:11 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 May 2013 20:50:11 -0600
Subject: [PATCH] ARM: bcm2835: enable CONFIG_LEDS_GPIO
In-Reply-To: <1368758969-26339-1-git-send-email-swarren@wwwdotorg.org>
References: <1368758969-26339-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <51959AE3.3020300@wwwdotorg.org>

On 05/16/2013 08:49 PM, Stephen Warren wrote:
> Enable CONFIG_LEDS_GPIO and all options required to enable it, or make
> the option useful.
> 
> This patch also regenerated bcm2835_defconfig, which removes two HW_RANDOM
> entries, since they're enabled by default.

I have applied this to bcm2835's for-3.11/defconfig branch.



From robert.jarzmik at free.fr  Thu May 16 23:18:33 2013
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Fri, 17 May 2013 05:18:33 +0200
Subject: GPIO sysfs : set a wake source
In-Reply-To: <51953840.9050106@wwwdotorg.org> (Stephen Warren's message of
 "Thu, 16 May 2013 13:49:20 -0600")
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
 <51926177.1050600@wwwdotorg.org> <87ip2ig1ez.fsf@free.fr>
 <51953840.9050106@wwwdotorg.org>
Message-ID: <87ehd6fg52.fsf@free.fr>

Stephen Warren <swarren at wwwdotorg.org> writes:

>>>> Instead figure out how to make the subsystems we have and the
>>>> device trees express what you want to do.
>>
>> As I said above, I don't think it's the way to go. I have *no* subsystem to
>> address.
>> Devicetree can't help in the toggle to "activate" or "deactivate" the wakeup
>> upon this GPIO, can it ?
>
> This sounds very similar to WiFi rfkill, although it's a MODEM not WiFi.
Mmmm yes, similar. But with one big difference : RFKill is control of wireless
chip "up state", while the toggle I'm speaking of will purely say if the "input
GPIO" will trigger a wake-up from S3 or not.

If RFKill interface had a toggle to say "hardware rfkill button toggle can
wake-up the kernel out of S3" then it would be very similar.

Cheers.

-- 
Robert


From daniel at ffwll.ch  Fri May 17 00:19:53 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Fri, 17 May 2013 06:19:53 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
References: <CAAQKjZNNw4qddo6bE5OY_CahrqDtqkxdO7Pm9RCguXyj9F4cMQ@mail.gmail.com>
 <51909DB4.2060208@canonical.com>
 <025201ce4fbb$363d0390$a2b70ab0$%dae@samsung.com>
 <5190B7D8.3010803@canonical.com>
 <027a01ce4fcc$5e7c7320$1b755960$%dae@samsung.com>
 <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
Message-ID: <CAKMK7uHRER_wmBcEN1JRqtkLxA_0SHBp16Z1Z_GqVbYw-YAZSA@mail.gmail.com>

On Wed, May 15, 2013 at 4:06 PM, Rob Clark <robdclark at gmail.com> wrote:
> So while it seems nice and orthogonal/clean to couple cache and
> synchronization and handle dma->cpu and cpu->cpu and cpu->dma in the
> same generic way, but I think in practice we have to make things more
> complex than they otherwise need to be to do this.  Otherwise I think
> we'll be having problems with badly behaved or crashing userspace.

I haven't read through the entire thread careful but imo this is very
important. If we add a fence interface which allows userspace to block
dma this is a no-go. The only thing we need is to sync up with all
outstanding dma operations and flush caches for cpu access. If broken
userspace starts to issue new dma (or multiple thread stomp onto each
another) that's not a problem dma fences/syncpoints should try to
solve. This way we can concentrate on solving the (already
challenging) device-to-device sync issues without additional
complexities which cpu->cpu sync would impose.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From prabhakar.csengg at gmail.com  Fri May 17 00:58:52 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 17 May 2013 10:28:52 +0530
Subject: [PATCH] ARM: davinci: dma: Convert to devm_* api
In-Reply-To: <5194DC6A.8080609@cogentembedded.com>
References: <1368687502-15551-1-git-send-email-prabhakar.csengg@gmail.com>
 <5194DC6A.8080609@cogentembedded.com>
Message-ID: <CA+V-a8v89gGuGuZB75-LnYNP7G765RnaY9uwviNwPmY-vQzPVA@mail.gmail.com>

Hi Sergei,

Thanks for the review.

On Thu, May 16, 2013 at 6:47 PM, Sergei Shtylyov
<sergei.shtylyov at cogentembedded.com> wrote:
> Hello.
>
>
> On 16-05-2013 10:58, Lad Prabhakar wrote:
>
>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>
>
>> Use devm_ioremap_resource instead of reques_mem_region()/ioremap() and
>> devm_request_irq() instead of request_irq().
>
>
>> This ensures more consistent error values and simplifies error paths.
>
>
>> Signed-off-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>> ---
>>   NOte:- Boot tested on Logic-PD OMAP-L138 EVM
>
>
>>   arch/arm/mach-davinci/dma.c |   63
>> ++++++++++++++++--------------------------
>>   1 files changed, 24 insertions(+), 39 deletions(-)
>
>
>> diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
>> index 45b7c71..aeda496 100644
>> --- a/arch/arm/mach-davinci/dma.c
>> +++ b/arch/arm/mach-davinci/dma.c
>
> [...]
>
>> @@ -1422,25 +1421,16 @@ static int __init edma_probe(struct
>> platform_device *pdev)
>>                         found = 1;
>>                 }
>>
>> -               len[j] = resource_size(r[j]);
>> -
>> -               r[j] = request_mem_region(r[j]->start, len[j],
>> -                       dev_name(&pdev->dev));
>> -               if (!r[j]) {
>> -                       status = -EBUSY;
>> -                       goto fail1;
>> -               }
>> -
>> -               edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
>> -               if (!edmacc_regs_base[j]) {
>> +               edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev,
>> r[j]);
>> +               if (IS_ERR(edmacc_regs_base[j])) {
>>                         status = -EBUSY;
>
>
>    And you call that "more consistent error values"? Why not:
>
>                         status = PTR_ERR(edmacc_regs_base[j]);
>
Yes missed it will fix it in v2.

>
>>                 edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
>
>
>    Maybe it's worth using devm_kzalloc() too?
>
OK

Regards,
--Prabhakar Lad


From linux at prisktech.co.nz  Fri May 17 01:21:15 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 17 May 2013 17:21:15 +1200
Subject: [PATCHv6 0/3] Add support for velocity network driver on platform
 devices
Message-ID: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>

v6 changes:
Remove more bus specific code from velocity_probe()
Make velocity_(suspend/resume) accept a struct device *
Simplify PM code to use velocity_(suspend/resume) - remove the individual
pci and platform functions.
Add a struct pci_dev variable to velocity_get_pci_info() to reduce churn

v5 changes:
Remove velocity_info union. Change velocity_info->pdev back to struct pci_dev.
Remove more 'if (pci)' sections.
Remove 'void *pdev' function parameters.
Pass correct variable to velocity_choose_state()

v4 changes:
Code tidyup as requested by Francois Romieu
Removed '#ifdef PCI' around PCI code. Compile tested on (!)PCI and (!)PM.

v3 changes:
Rebased against net-next.
Fix errors in pm code.

v2 changes:
Drop patch #1 as requested by David Miller.
Correct the PHYID_ICPLUS_IP101A MII bits - should be ON, rather than OFF.
Read the platform rev_id from the correct register [regs->rev_id]. It's possible
this would work for the PCI version as well and would remove the need for the
'if (pci)' test to set vptr->rev_id.

v1:
The first three patches are general tidyup.

[DROPPED] Patch ## just alphabetizes the #includes to make it easier to read.

Patch #1 replaces vptr->dev with vptr->netdev, in preparation of adding a
struct device *dev in Patch #2

Patch #2 replaces the pci dma functions with the generic versions.

I have build tested these patches but don't have a PCI velocity to run-test it.
I can't see that they should introduce any problems as it is all renames and
function swapping.

Patch #3 adds support for the velocity driver on devicetree platform devices.
Binding document included. This patch is compile-tested for PCI, and boot
tested on a VIA APC8750.

I think it would be pertinent to get some tested-by's for PCI users.

Regards
Tony Prisk


Tony Prisk (3):
  net: velocity: Rename vptr->dev to vptr->netdev
  net: velocity: Convert to generic dma functions
  net: velocity: Add platform device support to VIA velocity driver

 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  497 +++++++++++++-------
 drivers/net/ethernet/via/via-velocity.h            |   35 +-
 4 files changed, 377 insertions(+), 178 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 01:21:16 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 17 May 2013 17:21:16 +1200
Subject: [PATCHv6 1/3] net: velocity: Rename vptr->dev to vptr->netdev
In-Reply-To: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
References: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368768078-16121-2-git-send-email-linux@prisktech.co.nz>

Improve the clarity of the code in preparation for converting the
dma functions to generic versions, which require a struct device *.

This makes it possible to store a 'struct device *dev' in the
velocity_info structure.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   66 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    4 +-
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index fb62489..187eef3 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -998,9 +998,9 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 {
 
 	if (vptr->mii_status & VELOCITY_LINK_FAIL) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
 	} else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
 
 		if (vptr->mii_status & VELOCITY_SPEED_1000)
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
@@ -1014,7 +1014,7 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 		else
 			VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
 	} else {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
 		switch (vptr->options.spd_dpx) {
 		case SPD_DPX_1000_FULL:
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
@@ -1319,7 +1319,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 	case VELOCITY_INIT_RESET:
 	case VELOCITY_INIT_WOL:
 
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/*
 		 *	Reset RX to prevent RX pointer not on the 4X location
@@ -1332,7 +1332,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1354,7 +1354,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 
 		mac_eeprom_reload(regs);
 		for (i = 0; i < 6; i++)
-			writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -1377,7 +1377,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		/*
 		 *	Set packet filter: Receive directed and broadcast address
 		 */
-		velocity_set_multi(vptr->dev);
+		velocity_set_multi(vptr->netdev);
 
 		/*
 		 *	Enable MII auto-polling
@@ -1404,14 +1404,14 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
 
 		mii_status = velocity_get_opt_media_mode(vptr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		mii_init(vptr, mii_status);
 
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1474,7 +1474,7 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 				    rx_ring_size, &pool_dma);
 	if (!pool) {
 		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
-			vptr->dev->name);
+			vptr->netdev->name);
 		return -ENOMEM;
 	}
 
@@ -1514,7 +1514,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 
-	rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx.buf_sz + 64);
+	rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
 	if (rd_info->skb == NULL)
 		return -ENOMEM;
 
@@ -1620,7 +1620,7 @@ static int velocity_init_rd_ring(struct velocity_info *vptr)
 
 	if (velocity_rx_refill(vptr) != vptr->options.numrx) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
-			"%s: failed to allocate RX buffer.\n", vptr->dev->name);
+			"%s: failed to allocate RX buffer.\n", vptr->netdev->name);
 		velocity_free_rd_ring(vptr);
 		goto out;
 	}
@@ -1809,7 +1809,7 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
 		BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
 		writew(TRDCSR_RUN, &regs->TDCSRClr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/* FIXME: port over the pci_device_failed code and use it
 		   here */
@@ -1850,10 +1850,10 @@ static void velocity_error(struct velocity_info *vptr, int status)
 
 		if (linked) {
 			vptr->mii_status &= ~VELOCITY_LINK_FAIL;
-			netif_carrier_on(vptr->dev);
+			netif_carrier_on(vptr->netdev);
 		} else {
 			vptr->mii_status |= VELOCITY_LINK_FAIL;
-			netif_carrier_off(vptr->dev);
+			netif_carrier_off(vptr->netdev);
 		}
 
 		velocity_print_link_status(vptr);
@@ -1867,9 +1867,9 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		enable_mii_autopoll(regs);
 
 		if (vptr->mii_status & VELOCITY_LINK_FAIL)
-			netif_stop_queue(vptr->dev);
+			netif_stop_queue(vptr->netdev);
 		else
-			netif_wake_queue(vptr->dev);
+			netif_wake_queue(vptr->netdev);
 
 	}
 	if (status & ISR_MIBFI)
@@ -1894,7 +1894,7 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	int idx;
 	int works = 0;
 	struct velocity_td_info *tdinfo;
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 
 	for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
 		for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
@@ -1939,9 +1939,9 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	 *	Look to see if we should kick the transmit network
 	 *	layer for more work.
 	 */
-	if (netif_queue_stopped(vptr->dev) && (full == 0) &&
+	if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
 	    (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
-		netif_wake_queue(vptr->dev);
+		netif_wake_queue(vptr->netdev);
 	}
 	return works;
 }
@@ -1989,7 +1989,7 @@ static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
 	if (pkt_size < rx_copybreak) {
 		struct sk_buff *new_skb;
 
-		new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
+		new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
 		if (new_skb) {
 			new_skb->ip_summed = rx_skb[0]->ip_summed;
 			skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
@@ -2030,14 +2030,14 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
 	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
 	struct sk_buff *skb;
 
 	if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
-		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->netdev->name);
 		stats->rx_length_errors++;
 		return -EINVAL;
 	}
@@ -2075,7 +2075,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		   PCI_DMA_FROMDEVICE);
 
 	skb_put(skb, pkt_len - 4);
-	skb->protocol = eth_type_trans(skb, vptr->dev);
+	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
 	if (rd->rdesc0.RSR & RSR_DETAG) {
 		u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
@@ -2100,7 +2100,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
  */
 static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
 {
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	int rd_curr = vptr->rx.curr;
 	int works = 0;
 
@@ -2292,7 +2292,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 	if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
-				vptr->dev->name);
+				vptr->netdev->name);
 		ret = -EINVAL;
 		goto out_0;
 	}
@@ -2314,7 +2314,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 			goto out_0;
 		}
 
-		tmp_vptr->dev = dev;
+		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
@@ -2692,7 +2692,7 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
  */
 static void velocity_print_info(struct velocity_info *vptr)
 {
-	struct net_device *dev = vptr->dev;
+	struct net_device *dev = vptr->netdev;
 
 	printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
 	printk(KERN_INFO "%s: Ethernet Address: %pM\n",
@@ -2755,7 +2755,7 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	velocity_init_info(pdev, vptr, info);
 
-	vptr->dev = dev;
+	vptr->netdev = dev;
 
 	ret = pci_enable_device(pdev);
 	if (ret < 0)
@@ -3010,10 +3010,10 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	struct velocity_info *vptr = netdev_priv(dev);
 	unsigned long flags;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
-	netif_device_detach(vptr->dev);
+	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
 	pci_save_state(pdev);
@@ -3078,7 +3078,7 @@ static int velocity_resume(struct pci_dev *pdev)
 	unsigned long flags;
 	int i;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
 	pci_set_power_state(pdev, PCI_D0);
@@ -3101,7 +3101,7 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	mac_enable_int(vptr->mac_regs);
 	spin_unlock_irqrestore(&vptr->lock, flags);
-	netif_device_attach(vptr->dev);
+	netif_device_attach(vptr->netdev);
 
 	return 0;
 }
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index 4cb9f13..ff8d7828 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1435,7 +1435,7 @@ struct velocity_opt {
 
 struct velocity_info {
 	struct pci_dev *pdev;
-	struct net_device *dev;
+	struct net_device *netdev;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
@@ -1514,7 +1514,7 @@ static inline int velocity_get_ip(struct velocity_info *vptr)
 	int res = -ENOENT;
 
 	rcu_read_lock();
-	in_dev = __in_dev_get_rcu(vptr->dev);
+	in_dev = __in_dev_get_rcu(vptr->netdev);
 	if (in_dev != NULL) {
 		ifa = (struct in_ifaddr *) in_dev->ifa_list;
 		if (ifa != NULL) {
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 01:21:18 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 17 May 2013 17:21:18 +1200
Subject: [PATCHv6 3/3] net: velocity: Add platform device support to VIA
 velocity driver
In-Reply-To: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
References: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368768078-16121-4-git-send-email-linux@prisktech.co.nz>

Add support for the VIA Velocity network driver to be bound to a
OF created platform device.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  388 ++++++++++++++------
 drivers/net/ethernet/via/via-velocity.h            |   32 +-
 4 files changed, 321 insertions(+), 122 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

diff --git a/Documentation/devicetree/bindings/net/via-velocity.txt b/Documentation/devicetree/bindings/net/via-velocity.txt
new file mode 100644
index 0000000..b3db469
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/via-velocity.txt
@@ -0,0 +1,20 @@
+* VIA Velocity 10/100/1000 Network Controller
+
+Required properties:
+- compatible : Should be "via,velocity-vt6110"
+- reg : Address and length of the io space
+- interrupts : Should contain the controller interrupt line
+
+Optional properties:
+- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
+	devices quite often set this data in uboot and do not provide an eeprom.
+	Specify this option if you have no external eeprom.
+
+Examples:
+
+eth0 at d8004000 {
+	compatible = "via,velocity-vt6110";
+	reg = <0xd8004000 0x400>;
+	interrupts = <10>;
+	no-eeprom;
+};
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
index 68a9ba6..6a87097 100644
--- a/drivers/net/ethernet/via/Kconfig
+++ b/drivers/net/ethernet/via/Kconfig
@@ -5,7 +5,6 @@
 config NET_VENDOR_VIA
 	bool "VIA devices"
 	default y
-	depends on PCI
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y
 	  and read the Ethernet-HOWTO, available from
@@ -45,7 +44,7 @@ config VIA_RHINE_MMIO
 
 config VIA_VELOCITY
 	tristate "VIA Velocity support"
-	depends on PCI
+	depends on (PCI || USE_OF)
 	select CRC32
 	select CRC_CCITT
 	select NET_CORE
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 5996cee..b30ab62 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -65,7 +65,11 @@
 #include <linux/if.h>
 #include <linux/uaccess.h>
 #include <linux/proc_fs.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
 #include <linux/inetdevice.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/ethtool.h>
 #include <linux/mii.h>
@@ -84,6 +88,16 @@
 static int velocity_nics;
 static int msglevel = MSG_LEVEL_INFO;
 
+static void velocity_set_power_state(struct velocity_info *vptr, char state)
+{
+	void *addr = vptr->mac_regs;
+
+	if (vptr->bustype == BUS_PCI)
+		pci_set_power_state(vptr->pdev, state);
+	else
+		writeb(state, addr + 0x154);
+}
+
 /**
  *	mac_get_cam_mask	-	Read a CAM mask
  *	@regs: register block for this velocity
@@ -362,12 +376,23 @@ static struct velocity_info_tbl chip_info_table[] = {
  *	Describe the PCI device identifiers that we support in this
  *	device driver. Used for hotplug autoloading.
  */
-static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
+
+static DEFINE_PCI_DEVICE_TABLE(velocity_pci_id_table) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
 	{ }
 };
 
-MODULE_DEVICE_TABLE(pci, velocity_id_table);
+MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
+
+/**
+ *	Describe the OF device identifiers that we support in this
+ *	device driver. Used for devicetree nodes.
+ */
+static struct of_device_id velocity_of_ids[] = {
+	{ .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, velocity_of_ids);
 
 /**
  *	get_chip_name	- 	identifier to name
@@ -386,29 +411,6 @@ static const char *get_chip_name(enum chip_type chip_id)
 }
 
 /**
- *	velocity_remove1	-	device unplug
- *	@pdev: PCI device being removed
- *
- *	Device unload callback. Called on an unplug or on module
- *	unload for each active device that is present. Disconnects
- *	the device from the network layer and frees all the resources
- */
-static void velocity_remove1(struct pci_dev *pdev)
-{
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
-
-	unregister_netdev(dev);
-	iounmap(vptr->mac_regs);
-	pci_release_regions(pdev);
-	pci_disable_device(pdev);
-	pci_set_drvdata(pdev, NULL);
-	free_netdev(dev);
-
-	velocity_nics--;
-}
-
-/**
  *	velocity_set_int_opt	-	parser for integer options
  *	@opt: pointer to option value
  *	@val: value the user requested (or -1 for default)
@@ -1181,6 +1183,17 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
 	u16 BMCR;
 
 	switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
+	case PHYID_ICPLUS_IP101A:
+		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
+						MII_ADVERTISE, vptr->mac_regs);
+		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		else
+			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
+		break;
 	case PHYID_CICADA_CS8201:
 		/*
 		 *	Reset to hardware default
@@ -1353,9 +1366,12 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		velocity_soft_reset(vptr);
 		mdelay(5);
 
-		mac_eeprom_reload(regs);
-		for (i = 0; i < 6; i++)
-			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
+		if (!vptr->no_eeprom) {
+			mac_eeprom_reload(regs);
+			for (i = 0; i < 6; i++)
+				writeb(vptr->netdev->dev_addr[i],
+							&(regs->PAR[i]));
+		}
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -2233,15 +2249,15 @@ static int velocity_open(struct net_device *dev)
 		goto out;
 
 	/* Ensure chip is running */
-	pci_set_power_state(vptr->pdev, PCI_D0);
+	velocity_set_power_state(vptr, PCI_D0);
 
 	velocity_init_registers(vptr, VELOCITY_INIT_COLD);
 
-	ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
+	ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
 			  dev->name, dev);
 	if (ret < 0) {
 		/* Power down the chip */
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 		velocity_free_rings(vptr);
 		goto out;
 	}
@@ -2314,6 +2330,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
+		tmp_vptr->dev = vptr->dev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
 
@@ -2413,7 +2430,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	   saving then we need to bring the device back up to talk to it */
 
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 
 	switch (cmd) {
 	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
@@ -2426,7 +2443,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 		ret = -EOPNOTSUPP;
 	}
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 
 
 	return ret;
@@ -2492,7 +2509,7 @@ static int velocity_close(struct net_device *dev)
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
 		velocity_get_ip(vptr);
 
-	free_irq(vptr->pdev->irq, dev);
+	free_irq(dev->irq, dev);
 
 	velocity_free_rings(vptr);
 
@@ -2631,13 +2648,9 @@ static const struct net_device_ops velocity_netdev_ops = {
  *	Set up the initial velocity_info struct for the device that has been
  *	discovered.
  */
-static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
-			       const struct velocity_info_tbl *info)
+static void velocity_init_info(struct velocity_info *vptr,
+				const struct velocity_info_tbl *info)
 {
-	memset(vptr, 0, sizeof(struct velocity_info));
-
-	vptr->dev = &pdev->dev;
-	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
 	vptr->multicast_limit = MCAM_SIZE;
@@ -2652,10 +2665,9 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
  *	Retrieve the PCI configuration space data that interests us from
  *	the kernel PCI layer
  */
-static int velocity_get_pci_info(struct velocity_info *vptr,
-				 struct pci_dev *pdev)
+static int velocity_get_pci_info(struct velocity_info *vptr)
 {
-	vptr->rev_id = pdev->revision;
+	struct pci_dev *pdev = vptr->pdev;
 
 	pci_set_master(pdev);
 
@@ -2678,7 +2690,37 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
 		dev_err(&pdev->dev, "region #1 is too small.\n");
 		return -EINVAL;
 	}
-	vptr->pdev = pdev;
+
+	return 0;
+}
+
+/**
+ *	velocity_get_platform_info - retrieve platform info for device
+ *	@vptr: velocity device
+ *	@pdev: platform device it matches
+ *
+ *	Retrieve the Platform configuration data that interests us
+ */
+static int velocity_get_platform_info(struct velocity_info *vptr)
+{
+	struct resource res;
+	int ret;
+
+	if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
+		vptr->no_eeprom = 1;
+
+	ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
+	if (ret) {
+		dev_err(vptr->dev, "unable to find memory address\n");
+		return ret;
+	}
+
+	vptr->memaddr = res.start;
+
+	if (resource_size(&res) < VELOCITY_IO_SIZE) {
+		dev_err(vptr->dev, "memory region is too small.\n");
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -2707,21 +2749,22 @@ static u32 velocity_get_link(struct net_device *dev)
 }
 
 /**
- *	velocity_found1		-	set up discovered velocity card
+ *	velocity_probe - set up discovered velocity device
  *	@pdev: PCI device
  *	@ent: PCI device table entry that matched
+ *	@bustype: bus that device is connected to
  *
  *	Configure a discovered adapter from scratch. Return a negative
  *	errno error code on failure paths.
  */
-static int velocity_found1(struct pci_dev *pdev,
-			   const struct pci_device_id *ent)
+static int velocity_probe(struct device *dev, int irq,
+			   const struct velocity_info_tbl *info,
+			   enum velocity_bus_type bustype)
 {
 	static int first = 1;
-	struct net_device *dev;
+	struct net_device *netdev;
 	int i;
 	const char *drv_string;
-	const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
 	struct velocity_info *vptr;
 	struct mac_regs __iomem *regs;
 	int ret = -ENOMEM;
@@ -2730,19 +2773,19 @@ static int velocity_found1(struct pci_dev *pdev,
 	 * can support more than MAX_UNITS.
 	 */
 	if (velocity_nics >= MAX_UNITS) {
-		dev_notice(&pdev->dev, "already found %d NICs.\n",
-			   velocity_nics);
+		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
 		return -ENODEV;
 	}
 
-	dev = alloc_etherdev(sizeof(struct velocity_info));
-	if (!dev)
+	netdev = alloc_etherdev(sizeof(struct velocity_info));
+	if (!netdev)
 		goto out;
 
 	/* Chain it all together */
 
-	SET_NETDEV_DEV(dev, &pdev->dev);
-	vptr = netdev_priv(dev);
+	SET_NETDEV_DEV(netdev, dev);
+	vptr = netdev_priv(netdev);
+	memset(vptr, 0, sizeof(struct velocity_info));
 
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
@@ -2752,41 +2795,41 @@ static int velocity_found1(struct pci_dev *pdev,
 		first = 0;
 	}
 
-	velocity_init_info(pdev, vptr, info);
-
-	vptr->netdev = dev;
+	netdev->irq = irq;
+	vptr->bustype = bustype;
+	vptr->netdev = netdev;
+	vptr->dev = dev;
 
-	ret = pci_enable_device(pdev);
-	if (ret < 0)
-		goto err_free_dev;
+	velocity_init_info(vptr, info);
 
-	ret = velocity_get_pci_info(vptr, pdev);
-	if (ret < 0) {
-		/* error message already printed */
-		goto err_disable;
-	}
+	if (vptr->bustype == BUS_PCI) {
+		vptr->pdev = to_pci_dev(dev);
 
-	ret = pci_request_regions(pdev, VELOCITY_NAME);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "No PCI resources.\n");
-		goto err_disable;
+		ret = velocity_get_pci_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
+	} else {
+		ret = velocity_get_platform_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
 	}
 
 	regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
 	if (regs == NULL) {
 		ret = -EIO;
-		goto err_release_res;
+		goto err_free_dev;
 	}
 
 	vptr->mac_regs = regs;
+	vptr->rev_id = readb(&regs->rev_id);
 
 	mac_wol_reset(regs);
 
 	for (i = 0; i < 6; i++)
-		dev->dev_addr[i] = readb(&regs->PAR[i]);
+		netdev->dev_addr[i] = readb(&regs->PAR[i]);
 
 
-	drv_string = dev_driver_string(&pdev->dev);
+	drv_string = dev_driver_string(dev);
 
 	velocity_get_options(&vptr->options, velocity_nics, drv_string);
 
@@ -2807,46 +2850,125 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
 
-	dev->netdev_ops = &velocity_netdev_ops;
-	dev->ethtool_ops = &velocity_ethtool_ops;
-	netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
+	netdev->netdev_ops = &velocity_netdev_ops;
+	netdev->ethtool_ops = &velocity_ethtool_ops;
+	netif_napi_add(netdev, &vptr->napi, velocity_poll,
+							VELOCITY_NAPI_WEIGHT);
 
-	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
+	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
 			   NETIF_F_HW_VLAN_CTAG_TX;
-	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_FILTER |
-			 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_IP_CSUM;
+	netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
+			NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
+			NETIF_F_IP_CSUM;
 
-	ret = register_netdev(dev);
+	ret = register_netdev(netdev);
 	if (ret < 0)
 		goto err_iounmap;
 
-	if (!velocity_get_link(dev)) {
-		netif_carrier_off(dev);
+	if (!velocity_get_link(netdev)) {
+		netif_carrier_off(netdev);
 		vptr->mii_status |= VELOCITY_LINK_FAIL;
 	}
 
 	velocity_print_info(vptr);
-	pci_set_drvdata(pdev, dev);
+	dev_set_drvdata(vptr->dev, netdev);
 
 	/* and leave the chip powered down */
 
-	pci_set_power_state(pdev, PCI_D3hot);
+	velocity_set_power_state(vptr, PCI_D3hot);
 	velocity_nics++;
 out:
 	return ret;
 
 err_iounmap:
 	iounmap(regs);
-err_release_res:
-	pci_release_regions(pdev);
-err_disable:
-	pci_disable_device(pdev);
 err_free_dev:
-	free_netdev(dev);
+	free_netdev(netdev);
 	goto out;
 }
 
-#ifdef CONFIG_PM
+/**
+ *	velocity_remove	- device unplug
+ *	@dev: device being removed
+ *
+ *	Device unload callback. Called on an unplug or on module
+ *	unload for each active device that is present. Disconnects
+ *	the device from the network layer and frees all the resources
+ */
+static int velocity_remove(struct device *dev)
+{
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
+
+	unregister_netdev(netdev);
+	iounmap(vptr->mac_regs);
+	free_netdev(netdev);
+	velocity_nics--;
+
+	return 0;
+}
+
+static int velocity_pci_probe(struct pci_dev *pdev,
+			   const struct pci_device_id *ent)
+{
+	int ret;
+	const struct velocity_info_tbl *info =
+					&chip_info_table[ent->driver_data];
+
+	ret = pci_enable_device(pdev);
+	if (ret < 0)
+		return ret;
+
+	ret = pci_request_regions(pdev, VELOCITY_NAME);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "No PCI resources.\n");
+		pci_disable_device(pdev);
+		return ret;
+	}
+
+	ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
+	if (ret < 0) {
+		pci_release_regions(pdev);
+		pci_disable_device(pdev);
+	}
+
+	return ret;
+}
+
+static void velocity_pci_remove(struct pci_dev *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+}
+
+static int velocity_platform_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	const struct velocity_info_tbl *info;
+	int irq;
+
+	of_id = of_match_device(velocity_of_ids, &pdev->dev);
+	if (!of_id)
+		return -EINVAL;
+	info = of_id->data;
+
+	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+	if (!irq)
+		return -EINVAL;
+
+	return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
+}
+
+static int velocity_platform_remove(struct platform_device *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
 /**
  *	wol_calc_crc		-	WOL CRC
  *	@pattern: data pattern
@@ -3003,10 +3125,10 @@ static void velocity_save_context(struct velocity_info *vptr, struct velocity_co
 
 }
 
-static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
+static int velocity_suspend(struct device *dev, pm_message_t state)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 
 	if (!netif_running(vptr->netdev))
@@ -3015,20 +3137,24 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
-	pci_save_state(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_save_state(vptr->pdev);
 
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
 		velocity_get_ip(vptr);
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
 		velocity_set_wol(vptr);
-		pci_enable_wake(pdev, PCI_D3hot, 1);
-		pci_set_power_state(pdev, PCI_D3hot);
+		if (vptr->bustype == BUS_PCI)
+			pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	} else {
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
-		pci_disable_device(pdev);
-		pci_set_power_state(pdev, pci_choose_state(pdev, state));
+		if (vptr->bustype == BUS_PCI)
+			pci_disable_device(vptr->pdev);
+		velocity_set_power_state(vptr,
+				velocity_choose_state(vptr->dev, state));
 	}
 
 	spin_unlock_irqrestore(&vptr->lock, flags);
@@ -3070,19 +3196,22 @@ static void velocity_restore_context(struct velocity_info *vptr, struct velocity
 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
 }
 
-static int velocity_resume(struct pci_dev *pdev)
+static int velocity_resume(struct device *dev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 	int i;
 
 	if (!netif_running(vptr->netdev))
 		return 0;
 
-	pci_set_power_state(pdev, PCI_D0);
-	pci_enable_wake(pdev, 0, 0);
-	pci_restore_state(pdev);
+	velocity_set_power_state(vptr, PCI_D0);
+
+	if (vptr->bustype == BUS_PCI) {
+		pci_enable_wake(vptr->pdev, 0, 0);
+		pci_restore_state(vptr->pdev);
+	}
 
 	mac_wol_reset(vptr->mac_regs);
 
@@ -3104,23 +3233,34 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	return 0;
 }
-#endif
+#endif	/* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
 
 /*
  *	Definition for our device driver. The PCI layer interface
  *	uses this to handle all our card discover and plugging
  */
-static struct pci_driver velocity_driver = {
+static struct pci_driver velocity_pci_driver = {
 	.name		= VELOCITY_NAME,
-	.id_table	= velocity_id_table,
-	.probe		= velocity_found1,
-	.remove		= velocity_remove1,
-#ifdef CONFIG_PM
-	.suspend	= velocity_suspend,
-	.resume		= velocity_resume,
-#endif
+	.id_table	= velocity_pci_id_table,
+	.probe		= velocity_pci_probe,
+	.remove		= velocity_pci_remove,
+	.driver = {
+		.pm = &velocity_pm_ops,
+	},
 };
 
+static struct platform_driver velocity_platform_driver = {
+	.probe		= velocity_platform_probe,
+	.remove		= velocity_platform_remove,
+	.driver = {
+		.name = "via-velocity",
+		.owner = THIS_MODULE,
+		.of_match_table = velocity_of_ids,
+		.pm = &velocity_pm_ops,
+	},
+};
 
 /**
  *	velocity_ethtool_up	-	pre hook for ethtool
@@ -3133,7 +3273,7 @@ static int velocity_ethtool_up(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 	return 0;
 }
 
@@ -3148,7 +3288,7 @@ static void velocity_ethtool_down(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 }
 
 static int velocity_get_settings(struct net_device *dev,
@@ -3270,7 +3410,11 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
 	struct velocity_info *vptr = netdev_priv(dev);
 	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
 	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
-	strlcpy(info->bus_info, pci_name(vptr->pdev), sizeof(info->bus_info));
+	if (vptr->bustype == BUS_PCI)
+		strlcpy(info->bus_info, pci_name(vptr->pdev),
+						sizeof(info->bus_info));
+	else
+		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
 }
 
 static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -3563,9 +3707,15 @@ static int __init velocity_init_module(void)
 	int ret;
 
 	velocity_register_notifier();
-	ret = pci_register_driver(&velocity_driver);
+
+	ret = pci_register_driver(&velocity_pci_driver);
+	if (ret < 0)
+		velocity_unregister_notifier();
+
+	ret = platform_driver_register(&velocity_platform_driver);
 	if (ret < 0)
 		velocity_unregister_notifier();
+
 	return ret;
 }
 
@@ -3580,7 +3730,9 @@ static int __init velocity_init_module(void)
 static void __exit velocity_cleanup_module(void)
 {
 	velocity_unregister_notifier();
-	pci_unregister_driver(&velocity_driver);
+
+	pci_unregister_driver(&velocity_pci_driver);
+	platform_driver_unregister(&velocity_platform_driver);
 }
 
 module_init(velocity_init_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index c38bbae..6be7e46 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1265,7 +1265,7 @@ struct velocity_context {
 #define PHYID_VT3216_64BIT  0x000FC600UL
 #define PHYID_MARVELL_1000  0x01410C50UL
 #define PHYID_MARVELL_1000S 0x01410C40UL
-
+#define PHYID_ICPLUS_IP101A 0x02430C54UL
 #define PHYID_REV_ID_MASK   0x0000000FUL
 
 #define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
@@ -1433,10 +1433,38 @@ struct velocity_opt {
 
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
+static inline char velocity_choose_state(struct device *dev,
+					   pm_message_t state)
+
+{
+	switch (state.event) {
+	case PM_EVENT_ON:
+		return PCI_D0;
+	case PM_EVENT_FREEZE:
+	case PM_EVENT_PRETHAW:
+		/* REVISIT both freeze and pre-thaw "should" use D0 */
+	case PM_EVENT_SUSPEND:
+	case PM_EVENT_HIBERNATE:
+		return PCI_D3hot;
+	default:
+		dev_info(dev, "unrecognized suspend event %d\n", state.event);
+		BUG();
+	}
+
+	return PCI_D0;
+}
+
+enum velocity_bus_type {
+	BUS_PCI,
+	BUS_PLATFORM,
+};
+
 struct velocity_info {
-	struct device *dev;
 	struct pci_dev *pdev;
+	struct device *dev;
 	struct net_device *netdev;
+	enum velocity_bus_type bustype;
+	int no_eeprom;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 01:21:17 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 17 May 2013 17:21:17 +1200
Subject: [PATCHv6 2/3] net: velocity: Convert to generic dma functions
In-Reply-To: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
References: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368768078-16121-3-git-send-email-linux@prisktech.co.nz>

Remove the pci_* dma functions and replace with the more generic
versions.

In preparation of adding platform support, a new struct device *dev
is added to struct velocity_info which can be used by both the pci
and platform code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   51 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    1 +
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 187eef3..5996cee 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -46,6 +46,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 #include <linux/init.h>
+#include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
@@ -1459,7 +1460,6 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	struct velocity_opt *opt = &vptr->options;
 	const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
 	const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
-	struct pci_dev *pdev = vptr->pdev;
 	dma_addr_t pool_dma;
 	void *pool;
 	unsigned int i;
@@ -1467,13 +1467,13 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	/*
 	 * Allocate all RD/TD rings a single pool.
 	 *
-	 * pci_alloc_consistent() fulfills the requirement for 64 bytes
+	 * dma_alloc_coherent() fulfills the requirement for 64 bytes
 	 * alignment
 	 */
-	pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
-				    rx_ring_size, &pool_dma);
+	pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
+				    rx_ring_size, &pool_dma, GFP_ATOMIC);
 	if (!pool) {
-		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
+		dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
 			vptr->netdev->name);
 		return -ENOMEM;
 	}
@@ -1524,8 +1524,8 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	 */
 	skb_reserve(rd_info->skb,
 			64 - ((unsigned long) rd_info->skb->data & 63));
-	rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
-					vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
+					vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Fill in the descriptor to match
@@ -1588,8 +1588,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr)
 
 		if (!rd_info->skb)
 			continue;
-		pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-				 PCI_DMA_FROMDEVICE);
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
 		rd_info->skb_dma = 0;
 
 		dev_kfree_skb(rd_info->skb);
@@ -1670,7 +1670,7 @@ static void velocity_free_dma_rings(struct velocity_info *vptr)
 	const int size = vptr->options.numrx * sizeof(struct rx_desc) +
 		vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
 
-	pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
+	dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
 }
 
 static int velocity_init_rings(struct velocity_info *vptr, int mtu)
@@ -1727,8 +1727,8 @@ static void velocity_free_tx_buf(struct velocity_info *vptr,
 				pktlen = max_t(size_t, pktlen,
 						td->td_buf[i].size & ~TD_QUEUE);
 
-			pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
-					le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
+			dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
+					le16_to_cpu(pktlen), DMA_TO_DEVICE);
 		}
 	}
 	dev_kfree_skb_irq(skb);
@@ -1750,8 +1750,8 @@ static void velocity_free_td_ring_entry(struct velocity_info *vptr,
 	if (td_info->skb) {
 		for (i = 0; i < td_info->nskb_dma; i++) {
 			if (td_info->skb_dma[i]) {
-				pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
-					td_info->skb->len, PCI_DMA_TODEVICE);
+				dma_unmap_single(vptr->dev, td_info->skb_dma[i],
+					td_info->skb->len, DMA_TO_DEVICE);
 				td_info->skb_dma[i] = 0;
 			}
 		}
@@ -2029,7 +2029,6 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
  */
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
-	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
 	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
@@ -2047,8 +2046,8 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 
 	skb = rd_info->skb;
 
-	pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
-				    vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
+				    vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Drop frame not meeting IEEE 802.3
@@ -2061,19 +2060,18 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		}
 	}
 
-	pci_action = pci_dma_sync_single_for_device;
-
 	velocity_rx_csum(rd, skb);
 
 	if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
 		velocity_iph_realign(vptr, skb, pkt_len);
-		pci_action = pci_unmap_single;
 		rd_info->skb = NULL;
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
+	} else {
+		dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
+					   vptr->rx.buf_sz, DMA_FROM_DEVICE);
 	}
 
-	pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-		   PCI_DMA_FROMDEVICE);
-
 	skb_put(skb, pkt_len - 4);
 	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
@@ -2550,7 +2548,8 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	 *	add it to the transmit ring.
 	 */
 	tdinfo->skb = skb;
-	tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+	tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
+								DMA_TO_DEVICE);
 	td_ptr->tdesc0.len = cpu_to_le16(pktlen);
 	td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
 	td_ptr->td_buf[0].pa_high = 0;
@@ -2560,7 +2559,7 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
-		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(&vptr->pdev->dev,
+		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
 							  frag, 0,
 							  skb_frag_size(frag),
 							  DMA_TO_DEVICE);
@@ -2637,6 +2636,7 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
 {
 	memset(vptr, 0, sizeof(struct velocity_info));
 
+	vptr->dev = &pdev->dev;
 	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
@@ -2744,7 +2744,6 @@ static int velocity_found1(struct pci_dev *pdev,
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	vptr = netdev_priv(dev);
 
-
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
 			VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index ff8d7828..c38bbae 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1434,6 +1434,7 @@ struct velocity_opt {
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
 struct velocity_info {
+	struct device *dev;
 	struct pci_dev *pdev;
 	struct net_device *netdev;
 
-- 
1.7.9.5



From acourbot at nvidia.com  Fri May 17 01:36:34 2013
From: acourbot at nvidia.com (Alex Courbot)
Date: Fri, 17 May 2013 14:36:34 +0900
Subject: Naming convention DSI + device tree
In-Reply-To: <519522C1.5010107@wwwdotorg.org>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org> <20130516071537.GA13573@mail.o2s.ch>
 <519522C1.5010107@wwwdotorg.org>
Message-ID: <5195C1E2.4020009@nvidia.com>

On 05/17/2013 03:17 AM, Stephen Warren wrote:
>> Is this upcoming CDF included within your "linux-next_common"
>> branch?
>
> No. That branch of mine is basd on linux-next, so whatever is in
> linux-next is in my branch, and I certainly haven't applied the CDF
> locally.
>
> I believe the CDF has been posted to various mailing lists a few
> times, but it isn't checked in yet since there isn't a final version.
> I CC'd Alex; he might know the status better than me.

Current version is RFC v2 - I know Laurent is working on a v3, but it is 
taking some time. It will probably differ considerably from v2, so be 
warned if you use it.

Still, if you want to play around with the CDF, you can have a look at 
the tegra-cdf branch of my github repo: 
https://github.com/Gnurou/linux/commits/tegra-cdf

It was kind of old so I rebased it on top of 3.10rc1. It includes the 
CDF v2 patch, adds CDF support to the tegra-drm driver, and also 
implements a driver for the Tegra 2-based Ventana panel. It's pretty 
straightforward to read so I guess you can use that as a guide.

I checked whether the rebase worked and it does - you just need to 
enable host1x/tegradrm support on top of the default settings (Stephen, 
why aren't these enabled by default?)

So long story short, CDF works well and is small enough to be easy to 
maintain out-of-tree. A proper panel framework is desperately needed in 
the kernel, so I hope it will move forward soon.

Hope this helps,
Alex.



From kishon at ti.com  Fri May 17 01:39:24 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Fri, 17 May 2013 11:09:24 +0530
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <20130516162034.GX5600@atomide.com>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
 <51936946.3030507@iki.fi> <20130516155857.GV5600@atomide.com>
 <519503DA.5070303@iki.fi> <20130516162034.GX5600@atomide.com>
Message-ID: <5195C28C.40300@ti.com>

Hi,

On Thursday 16 May 2013 09:50 PM, Tony Lindgren wrote:
> * Tomi Valkeinen <tomi.valkeinen at iki.fi> [130516 09:11]:
>> On 16/05/13 18:58, Tony Lindgren wrote:
>>> * Tomi Valkeinen <tomi.valkeinen at iki.fi> [130515 03:59]:
>>>
>>> Just checking.. Do you have CONFIG_OMAP_OCP2SCP=y in your .config? Sounds
>>> like the some transceivers should depend on that for omap4.
>>
>> Yes, I have OCP2SCP=y.
>
> Hmm well no idea beyond that then. Sounds like Kishon should check it.
>
>>>> The musb-hdrc id is wrong on overo also.
>>>
>>> Hmm has there been a fix posted for that?
>>
>> I couldn't find with a quick look. We debugged and discussed this on an irc
>> channel with Kishon, who said he'll send a patch. Changing the musb-hdrc ID
>> on overo fixed the issue, and it looks very similar to the error on 4430sdp.
>> The overo fix was just:

hmm.. I think using device name to bind the controller and the phy can 
no longer be used reliably. I think it's better to have something like 
what Grant suggested in my other patch series.. to have the phy 
reference into the host controllers platform_data structure. And for the 
phy reference I'll have label and id.

Does this makes sense to you?

Thanks
Kishon


From pranavkumar at linaro.org  Fri May 17 02:00:38 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Fri, 17 May 2013 11:30:38 +0530
Subject: [PATCH V2 1/3] virtio: console: Add emergency writeonly register
 to config space
In-Reply-To: <871u96a3dx.fsf@rustcorp.com.au>
References: <1367842791-30285-1-git-send-email-pranavkumar@linaro.org>
 <1367842791-30285-2-git-send-email-pranavkumar@linaro.org>
 <20130516123746.GA4744@amit.redhat.com>
 <871u96a3dx.fsf@rustcorp.com.au>
Message-ID: <CAAHg+HhrvF6XxogiAA-8fzuT6byiwFUkpvr__qwTgKTxXDNdJw@mail.gmail.com>

On 17 May 2013 05:22, Rusty Russell <rusty at rustcorp.com.au> wrote:
> Amit Shah <amit.shah at redhat.com> writes:
>> On (Mon) 06 May 2013 [17:49:49], Pranavkumar Sawargaonkar wrote:
>>> This patch adds an emerg_wr register (writeonly) in config space
>>> of virtio console device which can be used for debugging.
>>>
>>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
>>> Signed-off-by: Anup Patel <anup.patel at linaro.org>
>>> Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
>>
>> OK, this change by itself looks harmless.
>>
>> Acked-by: Amit Shah <amit.shah at redhat.com>
>>
>>               Amit
>
> Thanks.  This is queued for *next* merge window.
>

Thanks amit and rusty.

> Cheers,
> Rusty.

Regards,
Pranav


From linus.walleij at linaro.org  Fri May 17 02:24:35 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 08:24:35 +0200
Subject: GPIO sysfs : set a wake source
In-Reply-To: <87ip2ig1ez.fsf@free.fr>
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
 <51926177.1050600@wwwdotorg.org> <87ip2ig1ez.fsf@free.fr>
Message-ID: <CACRpkdbiZFutP_+u=ciuC6r-8N5FpkEnGVLH9LGDQ7pvdo3_-Q@mail.gmail.com>

On Thu, May 16, 2013 at 9:39 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:

>>> Don't go down this path, let the kernel handle this kind of stuff.

> Oh really, where ?
>
> Let me show you why it can't be a module.

I'm not following. I haven't been talking about modules ...
(I think?)

Do you mean you want to show why it can't be in the kernel?

> In my case, I have a 2G modem connected to the soc :
>  - the modem and 1 SoC UART are connected (TX, RX, CTS, ...)
>  - the modem and SoC are connected through several gpios
>    - one or two control to power up and reset the modem
>    - one connected to the modem "ring" signal (the one I want a wakeup for).
>
> So I have no module to handle my modem :
>  - UART is handled by pxa-uart
>  - control/reset by gpiolib

Do you mean control/reset is handled by the userspace sysfs
interface to GPIOlib? This is not necessarily a good idea
in that case.

>  - ring ... by nobody
>
> So my point is that this ring *should* be handled by gpiolib, just as any casual
> input gpio. Moreover, the "wake-up" ability should be activable/deactivable on
> wish by userspace.

(...)

>>> Instead figure out how to make the subsystems we have and the
>>> device trees express what you want to do.
> As I said above, I don't think it's the way to go. I have *no* subsystem to
> address.

We have several cases of out-of-tree code due to missing subsystems.

One such subsystem is the in-kernel modem subsystem which Arun
has been trying to get going:
http://marc.info/?l=linux-kernel&m=134881988212794&w=2

> Devicetree can't help in the toggle to "activate" or "deactivate" the wakeup
> upon this GPIO, can it ?

No, I'm just saying the connection between the device and the
GPIO tree shall be modeled in the device tree, especially since
this is obviously deeply embedded, soldered-on stuff and the
hardware set-up should be encoded in the device tree.

I am starting so suspect that the real issue here, which has
not been expressed so far, is that you think of this embedded
modem as a US Robotics 28K8 modem connected to a serial
port, and as something that should be handled by userspace.

Is there a silent assumption that "modem drivers must be in
userspace"?

This assumption is not necessarily true when the modem start
to connect wires like GPIO to work. There are modems using
other things than UART, such as HSI, for datapath. And modems
using in-kernel protocols like CAIF or Phonet for control.

I think you need to think about how we join this modem closer
with the kernel instead of trying to paper it over using userspace
GPIO.

>>> What do you think about this idea? [GPIO hogs]
> I don't yet know. Let me think this more over. I'd like some literature if you
> can provide (especially on LAKML).

It doesn't toggle any pins so it's not what you want anyway.

I think you want part of your driver in the kernel.

I think the dilemma faced by embedded modems need to
be considered thoroughly here.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 17 02:29:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 08:29:01 +0200
Subject: ux500 breaking multi-platform kernels
In-Reply-To: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
References: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
Message-ID: <CACRpkdbJosO7Ea8=BUdgVSf5fZwddWZb79ONaz3r+DqseAaF7Q@mail.gmail.com>

On Wed, May 15, 2013 at 10:30 PM, Rob Herring <robherring2 at gmail.com> wrote:

> There are some initcalls on ux500 that are not properly
> conditionalized.

Oh wow you actually compiled it in and tried to boot it on something
else :-D

Highbank I suppose?

> The first is in ux500_l2x0_init and here is a fix:

I guess this is all -rc material. Can you send a proper patch (set)?

Unfortunately I don't have any other ARMv7 system than ux500 so
I cannot test multiplatform on any other machine myself.
(I have several ARMv5:s...)

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 17 02:31:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 08:31:31 +0200
Subject: u8500_defconfig: build failure in linux-next
In-Reply-To: <CAGa+x85Q8i9DCdTprbVX1opB9UdeD4uxAQpZ-CsqPYt86dLVFA@mail.gmail.com>
References: <CAGa+x85Q8i9DCdTprbVX1opB9UdeD4uxAQpZ-CsqPYt86dLVFA@mail.gmail.com>
Message-ID: <CACRpkdYLskC67vXQsVq470yo5J+E6eLtPz5-em4Qd_Pe0pwJiA@mail.gmail.com>

On Thu, May 16, 2013 at 1:29 AM, Kevin Hilman <khilman at linaro.org> wrote:

> Lee, Linus,
>
> In building all the ARM defconfigs in linux-next, I noticed
> u8500_defconfig not building:
>
>   [...]
>   CC      drivers/mfd/ab8500-debugfs.o
> /work/kernel/next/drivers/mfd/ab8500-debugfs.c:95:23: fatal error:
> mach/irqs.h: No such file or directory
>
> Same build error on v3.10-rc1 and Linus' master branch (but is fine on v3.9)

Yes, I sent this patch:
http://marc.info/?l=linux-kernel&m=136601206705342&w=2

Sam's been a bit overloaded that is why it's taking time to reach
Torvalds tree. Recently Lee started to help out queueing patches
for MFD so hopefully the bottleneck will be solved this way.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 17 02:35:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 08:35:04 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <20130515201439.GA10141@balto.lan>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
 <20130515201439.GA10141@balto.lan>
Message-ID: <CACRpkdaJ7_p=ggax2gE86ea75Da7p9xB6A6Kte36j2LZq6_TVQ@mail.gmail.com>

On Wed, May 15, 2013 at 10:14 PM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:
> On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
>> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > For all ux500 based platforms the maximum number of end-points are used.
>> > Move this knowledge into the driver so we can relinquish the burden from
>> > platform data. This also removes quite a bit of complexity from the driver
>> > and will aid us when we come to enable the driver for Device Tree.
>> >
>> > Cc: Felipe Balbi <balbi at ti.com>
>> > Cc: linux-usb at vger.kernel.org
>> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
>> > Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> I guess this stuff is dependent on the stuff Fabio has recently sent to
>> Felipe for the ux500 musb DMA so these musb patches should
>> primarily go through his tree.
>
> Not really, I only sent some coding style fix for the dma driver, as
> almost all of my work was in the usb phy files.  I also checked my
> latest series against Lee's tree and the two seems to merge without any
> conflict, so as far as I'm concerned it's really up to you and Felipe.

OK so Felipe can merge these smallish patches to musb, fine...

The other (DMA) stuff needs to be merged together with the rest
of the DMA40 series, so here basically Felipe needs an indication
if he can ACK it so I merge it through ARM SoC without colissions
and it sounds like we can make the assumption that this will work.

Yours,
Linus Walleij


From moinejf at free.fr  Fri May 17 02:37:43 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Fri, 17 May 2013 08:37:43 +0200
Subject: [PATCH 1/9] I2C: mv64xxx: work around signals causing I2C
 transactions to be aborted
In-Reply-To: <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>
Message-ID: <20130517083743.31af4eb0@armhf>

On Thu, 16 May 2013 21:30:59 +0100
Russell King <rmk+kernel at arm.linux.org.uk> wrote:

> Do not use interruptible waits in an I2C driver; if a process uses
> signals (eg, Xorg uses SIGALRM and SIGPIPE) then these signals can
> cause the I2C driver to abort a transaction in progress by another
> driver, which can cause that driver to fail.  I2C drivers are not
> expected to abort transactions on signals.

Hi Russell,

I had the same problem with my dove drm driver, but I don't fully agree
with your solution.

Using wait_event_timeout() stops the system, and reading the EDID from
an external screen may take some time.

Instead, as the problem occurs with the X server on HDMI exchanges,
I acted on the tda998x driver, simply masking the SIGALRM and SIGPIPE
signals on each drm driver request.

This mechanism works fine for me. Patch follows.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From moinejf at free.fr  Fri May 17 02:38:03 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Fri, 17 May 2013 08:38:03 +0200
Subject: [PATCH] drm/i2c: nxp-tda998x: fix abort of some i2c exchanges
Message-ID: <20130517083803.5f34816e@armhf>

The signals SIGALRM (most often) and SIGPOLL (sometimes) may be raised
after irq or some parameter change and this aborts the i2c exchanges.

The problem is solved by masking these signals.

Signed-off-by: Jean-Francois Moine <moinejf at free.fr>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |   40 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index e68b58a..672d045 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -262,6 +262,28 @@ struct tda998x_priv {
 #define TDA19989N2                0x0202
 #define TDA19988                  0x0301
 
+/*
+ * the signals SIGALRM (most often) and SIGPOLL (sometimes)
+ *	may be raised after irq or some parameter change
+ *	and this aborts the i2c exchanges
+ * the problem is solved by masking these signals
+ */
+static void savesig(sigset_t *p_oldset)
+{
+	sigset_t newset;
+
+	sigemptyset(&newset);
+	sigaddset(&newset, SIGALRM);
+	sigaddset(&newset, SIGPOLL);
+
+	sigprocmask(SIG_BLOCK, &newset, p_oldset);
+
+}
+static void restoresig(sigset_t *p_oldset)
+{
+	sigprocmask(SIG_SETMASK, p_oldset, NULL);
+}
+
 static void
 cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val)
 {
@@ -426,6 +448,7 @@ static void
 tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct tda998x_priv *priv = to_tda998x_priv(encoder);
+	sigset_t oldset;
 
 	/* we only care about on or off: */
 	if (mode != DRM_MODE_DPMS_ON)
@@ -434,6 +457,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 	if (mode == priv->dpms)
 		return;
 
+	savesig(&oldset);
+
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		/* enable audio and video ports */
@@ -458,6 +483,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
 		break;
 	}
 
+	restoresig(&oldset);
+
 	priv->dpms = mode;
 }
 
@@ -494,11 +521,14 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
 			struct drm_display_mode *adjusted_mode)
 {
 	struct tda998x_priv *priv = to_tda998x_priv(encoder);
+	sigset_t oldset;
 	uint16_t hs_start, hs_end, line_start, line_end;
 	uint16_t vwin_start, vwin_end, de_start, de_end;
 	uint16_t ref_pix, ref_line, pix_start2;
 	uint8_t reg, div, rep;
 
+	savesig(&oldset);
+
 	hs_start   = mode->hsync_start - mode->hdisplay;
 	hs_end     = mode->hsync_end - mode->hdisplay;
 	line_start = 1;
@@ -613,6 +643,8 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
 
 	/* must be last register set: */
 	reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
+
+	restoresig(&oldset);
 }
 
 static enum drm_connector_status
@@ -728,15 +760,21 @@ static int
 tda998x_encoder_get_modes(struct drm_encoder *encoder,
 			 struct drm_connector *connector)
 {
-	struct edid *edid = (struct edid *)do_get_edid(encoder);
+	struct edid *edid;
+	sigset_t oldset;
 	int n = 0;
 
+	savesig(&oldset);
+
+	edid = (struct edid *) do_get_edid(encoder);
 	if (edid) {
 		drm_mode_connector_update_edid_property(connector, edid);
 		n = drm_add_edid_modes(connector, edid);
 		kfree(edid);
 	}
 
+	restoresig(&oldset);
+
 	return n;
 }
 


-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From srinivas.kandagatla at st.com  Fri May 17 02:35:31 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 17 May 2013 07:35:31 +0100
Subject: [PATCH] ARM: prima2: return rather than panic on missing DT nodes
In-Reply-To: <CAGsJ_4w_a=vXMeh-vbRKwD+KGqRNthx-zne=DR3iR7B-WqiUPw@mail.gmail.com>
References: <1368719437-28287-1-git-send-email-robherring2@gmail.com>
 <519510A4.8090904@st.com>
 <CAL_JsqL_z99EfT=3E32c0AS6fbwqOyTb7n+AzySmzJNyMCab3w@mail.gmail.com>
 <CAGsJ_4w_a=vXMeh-vbRKwD+KGqRNthx-zne=DR3iR7B-WqiUPw@mail.gmail.com>
Message-ID: <5195CFB3.4090905@st.com>

On 17/05/13 01:30, Barry Song wrote:
> then it turns out that moving the codes to callbacks of machine is the
> right way. i will take care the init ordering issues.

Not sure if this helps but, I have done a patch for this yesterday to
fix few more issues when booting with multi_v7_defconfig then the one
pointed out by Rob .

--srini
-------------- next part --------------
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From gwenhael.goavec-merou at armadeus.com  Fri May 17 01:13:41 2013
From: gwenhael.goavec-merou at armadeus.com (Gwenhael Goavec-Merou)
Date: Fri, 17 May 2013 07:13:41 +0200
Subject: [PATCH] ARM: dts: apf28dev: Add touchscreen support for APF28dev
Message-ID: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>


Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>
---
 arch/arm/boot/dts/imx28-apf28dev.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 3d905d1..b602494 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -103,6 +103,7 @@
 
 		apbx at 80040000 {
 			lradc at 80050000 {
+				fsl,lradc-touchscreen-wires = <4>;
 				status = "okay";
 			};
 
-- 
1.8.1.5



From gwenhael.goavec-merou at armadeus.com  Fri May 17 01:13:42 2013
From: gwenhael.goavec-merou at armadeus.com (Gwenhael Goavec-Merou)
Date: Fri, 17 May 2013 07:13:42 +0200
Subject: [PATCH] ARM: imx: apf51: add nfc support
In-Reply-To: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
References: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
Message-ID: <1368767622-12968-2-git-send-email-gwenhael.goavec-merou@armadeus.com>


Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>
---
 arch/arm/boot/dts/imx51-apf51.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 2bcf698..8f7f9ac 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -45,6 +45,13 @@
 	status = "okay";
 };
 
+&nfc {
+	nand-bus-width = <8>;
+	nand-ecc-mode = "hw";
+	nand-on-flash-bbt;
+	status = "okay";
+};
+
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3_2>;
-- 
1.8.1.5



From mturquette at linaro.org  Fri May 17 03:08:26 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 17 May 2013 00:08:26 -0700
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe
 clocks on Armada 370
In-Reply-To: <20130516150616.GD6563@titan.lakedaemon.net>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130515214154.12127.73539@quantum> <20130516094417.24b1ca0d@skate>
 <51949830.70306@gmail.com> <20130516150616.GD6563@titan.lakedaemon.net>
Message-ID: <20130517070826.12127.41382@quantum>

Quoting Jason Cooper (2013-05-16 08:06:16)
> Mike, Sebastian,
> 
> On Thu, May 16, 2013 at 10:26:24AM +0200, Sebastian Hesselbarth wrote:
> > On 05/16/2013 09:44 AM, Thomas Petazzoni wrote:
> > >Dear Mike Turquette,
> > >
> > >On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> > >>Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> > >>>The Armada 370 has two gatable clocks for each PCIe interface, and we
> > >>>want both of them to be enabled. We therefore make one of the two
> > >>>clocks a child of the other, as we did for the sataX and sataXlnk
> > >>>clocks on Armada XP.
> > >>
> > >>Ack for patches #5 and #6.  Do you want me to take them?
> 
> Thanks for the Ack!
> 
> > >I don't know, I guess with your Ack, it would be easier to carry them
> > >through the Marvell maintainers and then the arm-soc tree, so that we
> > >can test arm-soc and have all the pieces needed in here.
> > >
> > >That said, Sebastian Hesselbarth has submitted a big rework of the
> > >mvebu clock drivers, which would conflict with this patch, and
> > >Sebastian's rework would most likely go through your tree. If that's
> > >the case, I guess it would be better to let you take #5 and #6 in this
> > >patch series.
> > 
> > I also requested to take the restructure patches through ARM tree. They
> > are only touching files in drivers/clk/mvebu and by taking them through
> > ARM, we can update PCIe clock patches easily. The dependency between
> > Thomas' and my patches basically is that I renamed files that Thomas
> > now commits to. (I switched clk/mvebu from per-function files to per-soc
> > files).
> 
> I agree.  My heart jumped into my throat a little there :)  Mike, if
> it's ok with you, I'd prefer to take these through arm-soc.  Any merge
> conflicts should be minimal.  And at any rate, resolving the conflicts
> are *much* easier to handle than having arm-soc depend on an outside
> tree (then Linus has to take care in the order he merges them, no
> rebasing for clk tree, dogs and cats living together, etc ;-) )
> 

Yeah that all sounds good to me.  I'll review the restructure patches
shortly.

Regards,
Mike

> thx,
> 
> Jason.


From srinivas.kandagatla at st.com  Fri May 17 03:44:17 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 17 May 2013 08:44:17 +0100
Subject: [PATCH] ARM: vt8500: Add missing NULL terminator in dt_compat
Message-ID: <1368776657-23035-1-git-send-email-srinivas.kandagatla@st.com>

From: Srinivas Kandagatla <srinivas.kandagatla at st.com>

When I tried booting a stih415 Dual core A9 with multi_v7_defconfig, it
failed to boot. The issues seems to be changing by enabling or disabling
VT8550 platform. Having a quick look at dt_compat list, it seems to miss
a NULL terminator, which means of_flat_dt_match will compat check will
cross the boundary of dt_compat and fault at some point , which is what
was happening in my case.

Without this patch if we try to boot multi_v7_defconfig you might notice
that some of the platforms might fault if they fall after vt8500 in
machine-desc list. Other platforms which fall before vt8500 in mdesc list
will not fault.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
---
 arch/arm/mach-vt8500/vt8500.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 1dd281e..f5c33df 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -173,6 +173,7 @@ static const char * const vt8500_dt_compat[] = {
 	"wm,wm8505",
 	"wm,wm8750",
 	"wm,wm8850",
+	NULL
 };
 
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
-- 
1.7.6.5



From fabio.baltieri at linaro.org  Fri May 17 03:51:40 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Fri, 17 May 2013 09:51:40 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130516224337.GZ22822@zurbaran>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
 <20130516224337.GZ22822@zurbaran>
Message-ID: <20130517075140.GA25077@balto.lan>

Hello Samuel,

On Fri, May 17, 2013 at 12:43:37AM +0200, Samuel Ortiz wrote:
> > Fabio Baltieri (5):
> >       mfd: abx500-core: Fix sparse warning
> >       mfd: ab8500-sysctrl: Fix sparse warning
> >       mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> >       mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> Unless I'm missing something here, this one is not really rcN material, so
> I'd appreciate if you could queue it to your for-mfd branch instead.

The last two:

  mfd: ab8500-sysctrl: Set sysctrl_dev during probe
  mfd: ab8500-sysctrl: Let sysctrl driver work without pdata

are actually fixes for bugs introduced in this merge window that
inhibited the ab8500-sysctl driver as a consequence.  Would you
reconsider pulling just those?

Thanks,
Fabio

-- 
Fabio Baltieri


From santosh.shilimkar at ti.com  Fri May 17 04:00:00 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 17 May 2013 13:30:00 +0530
Subject: [GIT PULL] ARM: OMAP5: hwmod, prm/cm data files and updates for
 3.10
In-Reply-To: <515F00B8.3000501@ti.com>
References: <1363768852-18125-1-git-send-email-santosh.shilimkar@ti.com>
 <20130401170539.GK10155@atomide.com> <515BA76D.3000302@ti.com>
 <alpine.DEB.2.00.1304031146230.2616@utopia.booyaka.com>
 <515D6020.2030103@ti.com> <20130404165208.GI10155@atomide.com>
 <515DB110.9000503@ti.com> <515F00B8.3000501@ti.com>
Message-ID: <5195E380.4040103@ti.com>

Paul, Tony,

On Friday 05 April 2013 10:20 PM, Santosh Shilimkar wrote:
> On Thursday 04 April 2013 10:27 PM, Santosh Shilimkar wrote:
>> On Thursday 04 April 2013 10:22 PM, Tony Lindgren wrote:
>>> * Santosh Shilimkar <santosh.shilimkar at ti.com> [130404 04:15]:
> [..]
> 
>>> Can't we already trim the am33xx hwmod data after your patches for
>>> v3.10 as am33xx is already DT only? Unfortunately we cannot create
>>> negative diffstat in other ways for v3.10 merge window as we cannot
>>> make omap4 DT only just quite yet.
>>>
>> Yes we can and I can take a stab it tomorrow. The only thing is I
>> might need some support for testing but thats manageable. Will
>> take a stab at it tomorrow and if everything goes well, post a
>> patch for smae.
>>
> Patch for the AM33XX to trim is end of the email. Thanks to
> Sricharan and Pekon for patch and testing. Looping both
> Vaibhav's if they have any objection on the patch.
> 
> Regards,
> Santosh
> 
> From b95dd33fe59b8e77727eb3b1717d763bbf9a2893 Mon Sep 17 00:00:00 2001
> From: Sricharan R <r.sricharan at ti.com>
> Date: Fri, 5 Apr 2013 20:39:12 +0530
> Subject: [PATCH] ARM: AM33XX: hwmod data: Clean up the data file
> 
For whatever reason, we again missed the merge window for the subject
series, I would like to know your plan on the subject series for
at least 3.11. Asking *well in advance* to avoid late merge related
discussions.

Thanks to Vaibhav, AM33XX patch is tested and validated with some
updates considering upcoming PM support for AM33XX. So that
patch will be included in the series.

Rajendra will follow up the patchset if there is some re-basing is
needed since I will away for few weeks because of travel. 

OMAP5 data is the *only* thing which is gating the device to boot
from mainline.

Thanks in advance.

Regards,
Santosh






From lee.jones at linaro.org  Fri May 17 04:00:08 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 17 May 2013 09:00:08 +0100
Subject: ux500 breaking multi-platform kernels
In-Reply-To: <CACRpkdbJosO7Ea8=BUdgVSf5fZwddWZb79ONaz3r+DqseAaF7Q@mail.gmail.com>
References: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
 <CACRpkdbJosO7Ea8=BUdgVSf5fZwddWZb79ONaz3r+DqseAaF7Q@mail.gmail.com>
Message-ID: <20130517080008.GJ3269@gmail.com>

On Fri, 17 May 2013, Linus Walleij wrote:

> On Wed, May 15, 2013 at 10:30 PM, Rob Herring <robherring2 at gmail.com> wrote:
> 
> > There are some initcalls on ux500 that are not properly
> > conditionalized.
> 
> Oh wow you actually compiled it in and tried to boot it on something
> else :-D
> 
> Highbank I suppose?
> 
> > The first is in ux500_l2x0_init and here is a fix:
> 
> I guess this is all -rc material. Can you send a proper patch (set)?

Feel free to add my fix for cpuidle to this set if it works for you.

If it doesn't I'll re-work.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From fabio.baltieri at linaro.org  Fri May 17 04:02:39 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Fri, 17 May 2013 10:02:39 +0200
Subject: [PATCH] ARM: ux500: update MSP1 pinctrl defintions
In-Reply-To: <CACRpkdZj6r3=fo=72PDshHbL7oHxb6H6uGeGvRyb2+uMjoAvUg@mail.gmail.com>
References: <1368004193-21213-1-git-send-email-fabio.baltieri@linaro.org>
 <CACRpkdZj6r3=fo=72PDshHbL7oHxb6H6uGeGvRyb2+uMjoAvUg@mail.gmail.com>
Message-ID: <20130517080239.GA26583@balto.lan>

On Wed, May 15, 2013 at 09:35:17PM +0200, Linus Walleij wrote:
> On Wed, May 8, 2013 at 11:09 AM, Fabio Baltieri
> <fabio.baltieri at linaro.org> wrote:
> 
> > Update MSP1 pinctrl definitions in mop500_family_pinmap by removing
> > sleep state and setting default ones as pin hogs, as those are used by
> > both ux500-msp-i2s.1 and ux500-msp-i2s.3.
> >
> > Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> 
> Applied to my ux500-pinctrl branch.

Thanks Linus,

This one was actually sort-of related to the ASoC patch to drop sleep
pin state control from the ux500 ASoC driver.  Would you be able to
check that one too?

The subject is:
  [PATCH 3/6] ASoC: ux500: Drop pinctrl sleep support

There are no dependency issues by applying this and the other in
different trees, but I'd like to close the discussion on the other one.

Thanks,
Fabio

-- 
Fabio Baltieri


From shawn.guo at linaro.org  Fri May 17 04:03:14 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 16:03:14 +0800
Subject: [PATCH] ARM: imx: apf51: add nfc support
In-Reply-To: <1368767622-12968-2-git-send-email-gwenhael.goavec-merou@armadeus.com>
References: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
 <1368767622-12968-2-git-send-email-gwenhael.goavec-merou@armadeus.com>
Message-ID: <20130517080312.GE8607@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 07:13:42AM +0200, Gwenhael Goavec-Merou wrote:
> 
> Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>

I already applied the patch [1], so this one can be ignored? 

Shawn

http://thread.gmane.org/gmane.linux.ports.arm.kernel/236989/

> ---
>  arch/arm/boot/dts/imx51-apf51.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
> index 2bcf698..8f7f9ac 100644
> --- a/arch/arm/boot/dts/imx51-apf51.dts
> +++ b/arch/arm/boot/dts/imx51-apf51.dts
> @@ -45,6 +45,13 @@
>  	status = "okay";
>  };
>  
> +&nfc {
> +	nand-bus-width = <8>;
> +	nand-ecc-mode = "hw";
> +	nand-on-flash-bbt;
> +	status = "okay";
> +};
> +
>  &uart3 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_uart3_2>;
> -- 
> 1.8.1.5
> 



From shawn.guo at linaro.org  Fri May 17 04:10:43 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 16:10:43 +0800
Subject: [PATCH] ARM: imx23-olinuxino: Add i2c support
In-Reply-To: <1368766213-16487-1-git-send-email-f.koliqi@gmail.com>
References: <1368766213-16487-1-git-send-email-f.koliqi@gmail.com>
Message-ID: <20130517081042.GF8607@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 12:50:13AM -0400, Fadil Berisha wrote:
> -			i2c at 80058000 {
> +			i2c: i2c at 80058000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx28-i2c";
>  				reg = <0x80058000 0x2000>;
>  				dmas = <&dma_apbx 3>;
>  				dma-names = "rx-tx";
> +				interrupts = <27 26>;
> +				clock-frequency = <100000>;
> +				fsl,i2c-dma-channel = <3>;

As we have adopted generic DMA bindings, this custom property shouldn't
be needed now.

Shawn

>  				status = "disabled";
>  			};
>  
> -- 
> 1.7.10
> 



From james.hogan at imgtec.com  Fri May 17 04:18:50 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 17 May 2013 09:18:50 +0100
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <51955C2C.5060705@codeaurora.org>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
 <51940CAF.6010808@codeaurora.org> <5194AD63.9020804@imgtec.com>
 <51955C2C.5060705@codeaurora.org>
Message-ID: <5195E7EA.3020703@imgtec.com>

On 16/05/13 23:22, Stephen Boyd wrote:
> On 05/16/13 02:56, James Hogan wrote:
>> On 15/05/13 23:31, Stephen Boyd wrote:
>>> Can you please Cc the devicetree mailing list when proposing new bindings?
>> Erm, I think it was on Cc (devicetree-discuss at lists.ozlabs.org yeh?)
> 
> I added them in my reply.

Ah yes, sorry, my mistake.

Cheers
James



From linus.walleij at linaro.org  Fri May 17 04:25:10 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 10:25:10 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130517075140.GA25077@balto.lan>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
 <20130516224337.GZ22822@zurbaran>
 <20130517075140.GA25077@balto.lan>
Message-ID: <CACRpkdYpEreHKdUyfcANA9kTRAjVbLbpJkBJCq1Q_pAeOKcdxw@mail.gmail.com>

On Fri, May 17, 2013 at 9:51 AM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:
> Hello Samuel,
(...)
> The last two:
>
>   mfd: ab8500-sysctrl: Set sysctrl_dev during probe
>   mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
>
> are actually fixes for bugs introduced in this merge window that
> inhibited the ab8500-sysctl driver as a consequence.  Would you
> reconsider pulling just those?

A good way to make sure that patches fixing regressions are applied
to the -rc series is to indicate in the commit message or even the
heading that it fixes a regression.

I usually try to begin such commits with the text:

  this patch fixes a regression caused by change 018745435
  "foo: fix bar"...

Then copying in some crash dump text never hurts :-)

It makes it very easy for us as subsystem maintainers to pick
regression fixes.

Yours,
Linus Walleij


From weiyj.lk at gmail.com  Fri May 17 04:26:00 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Fri, 17 May 2013 16:26:00 +0800
Subject: [PATCH] ARM: etm: add missing misc_deregister() on probe error and
 remove
Message-ID: <CAPgLHd_ScFPt5iYoFv++Bn-0cbwBXRX4YXJWqyyNzhQQkTsHXQ@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Add the missing misc_deregister() on probe error and remove.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 arch/arm/kernel/etm.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 8ff0ecd..d0b7426 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -365,7 +365,8 @@ static int etb_probe(struct amba_device *dev, const struct amba_id *id)
 	t->emu_clk = clk_get(&dev->dev, "emu_src_ck");
 	if (IS_ERR(t->emu_clk)) {
 		dev_dbg(&dev->dev, "Failed to obtain emu_src_ck.\n");
-		return -EFAULT;
+		ret = PTR_ERR(t->emu_clk);
+		goto out_dereg;
 	}
 
 	clk_enable(t->emu_clk);
@@ -384,6 +385,8 @@ static int etb_probe(struct amba_device *dev, const struct amba_id *id)
 out:
 	return ret;
 
+out_dereg:
+	misc_deregister(&etb_miscdev);
 out_unmap:
 	amba_set_drvdata(dev, NULL);
 	iounmap(t->etb_regs);
@@ -398,6 +401,7 @@ static int etb_remove(struct amba_device *dev)
 {
 	struct tracectx *t = amba_get_drvdata(dev);
 
+	misc_deregister(&etb_miscdev);
 	amba_set_drvdata(dev, NULL);
 
 	iounmap(t->etb_regs);



From linux at arm.linux.org.uk  Fri May 17 04:28:16 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 09:28:16 +0100
Subject: [PATCH] drm/i2c: nxp-tda998x: fix abort of some i2c exchanges
In-Reply-To: <20130517083803.5f34816e@armhf>
References: <20130517083803.5f34816e@armhf>
Message-ID: <20130517082816.GY18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 08:38:03AM +0200, Jean-Francois Moine wrote:
> The signals SIGALRM (most often) and SIGPOLL (sometimes) may be raised
> after irq or some parameter change and this aborts the i2c exchanges.
> 
> The problem is solved by masking these signals.

NAK.  The real problem is in the I2C driver, which actually suffers from
multiple problems.  See the set of I2C patches I posted yesterday.


From linux at prisktech.co.nz  Fri May 17 04:28:36 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 17 May 2013 20:28:36 +1200
Subject: [PATCH] ARM: vt8500: Add missing NULL terminator in dt_compat
In-Reply-To: <1368776657-23035-1-git-send-email-srinivas.kandagatla@st.com>
References: <1368776657-23035-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <5195EA34.7000409@prisktech.co.nz>

On 17/05/13 19:44, Srinivas KANDAGATLA wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>
> When I tried booting a stih415 Dual core A9 with multi_v7_defconfig, it
> failed to boot. The issues seems to be changing by enabling or disabling
> VT8550 platform. Having a quick look at dt_compat list, it seems to miss
> a NULL terminator, which means of_flat_dt_match will compat check will
> cross the boundary of dt_compat and fault at some point , which is what
> was happening in my case.
>
> Without this patch if we try to boot multi_v7_defconfig you might notice
> that some of the platforms might fault if they fall after vt8500 in
> machine-desc list. Other platforms which fall before vt8500 in mdesc list
> will not fault.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> ---
>   arch/arm/mach-vt8500/vt8500.c |    1 +
>   1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
> index 1dd281e..f5c33df 100644
> --- a/arch/arm/mach-vt8500/vt8500.c
> +++ b/arch/arm/mach-vt8500/vt8500.c
> @@ -173,6 +173,7 @@ static const char * const vt8500_dt_compat[] = {
>   	"wm,wm8505",
>   	"wm,wm8750",
>   	"wm,wm8850",
> +	NULL
>   };
>   
>   DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
My bad. Thanks for the fix.

Acked-by: Tony Prisk <linux at prisktech.co.nz>

Arnd, Olof: Can you apply this directly please.

Regards
Tony Prisk


From nicolas.ferre at atmel.com  Fri May 17 04:28:35 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 17 May 2013 10:28:35 +0200
Subject: [PATCH 0/5 v2] ARM: at91: dt: switch to pre-processor
In-Reply-To: <20130515141906.GI22508@game.jcrosoft.org>
References: <20130515141906.GI22508@game.jcrosoft.org>
Message-ID: <5195EA33.4010400@atmel.com>

On 15/05/2013 16:19, Jean-Christophe PLAGNIOL-VILLARD :
> HI,
>
> 	v2:
> 	 use common IRQ define
> 	 split patch
> 	 rebase on 3.10-rc1
>
>          The follow patch series switch the at91 to DT pre-processor
>
>          So we can use macro for AIC and Pinctrl instead of magic

Hi, this is very good for me: nice to use the common GPIO and IRQ 
defines. It increases readability a lot!

So, it seems natural to push this series through arm-soc. It would be 
integrated early in a "cleanup" branch for 3.11.
We also would like to make it a prerequisite for all AT91 material that 
are touching the changed files, targeted for 3.11.

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks, best regards.

> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
>
>    Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
>
> are available in the git repository at:
>
>    git://github.com/at91linux/linux-at91.git j/for-3.11-dt
>
> for you to fetch changes up to 3668ac6a70bc5af71a947ad7b531c57b8a787ea0:
>
>    ARM: at91: dt: switch to standard IRQ flag defines (2013-05-15 21:56:18 +0800)
>
> ----------------------------------------------------------------
> Jean-Christophe PLAGNIOL-VILLARD (5):
>        ARM: at91: dt: use #include for all device trees
>        ARM: at91: dt: switch to standard GPIO flag defines.
>        ARM: at91: dt: add pinctrl pre-processor define
>        ARM: at91: dt: switch to pinctrl to pre-processor
>        ARM: at91: dt: switch to standard IRQ flag defines
>
>   arch/arm/boot/dts/aks-cdu.dts               |   12 +--
>   arch/arm/boot/dts/animeo_ip.dts             |   18 ++---
>   arch/arm/boot/dts/at91-ariag25.dts          |    6 +-
>   arch/arm/boot/dts/at91rm9200.dtsi           |  207 +++++++++++++++++++++++++------------------------
>   arch/arm/boot/dts/at91rm9200ek.dts          |   10 +--
>   arch/arm/boot/dts/at91sam9260.dtsi          |  215 ++++++++++++++++++++++++++-------------------------
>   arch/arm/boot/dts/at91sam9263.dtsi          |  203 ++++++++++++++++++++++++------------------------
>   arch/arm/boot/dts/at91sam9263ek.dts         |   24 +++---
>   arch/arm/boot/dts/at91sam9g15.dtsi          |    2 +-
>   arch/arm/boot/dts/at91sam9g15ek.dts         |    4 +-
>   arch/arm/boot/dts/at91sam9g20.dtsi          |    2 +-
>   arch/arm/boot/dts/at91sam9g20ek.dts         |    6 +-
>   arch/arm/boot/dts/at91sam9g20ek_2mmc.dts    |   10 +--
>   arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   28 ++++---
>   arch/arm/boot/dts/at91sam9g25.dtsi          |    2 +-
>   arch/arm/boot/dts/at91sam9g25ek.dts         |    4 +-
>   arch/arm/boot/dts/at91sam9g35.dtsi          |    2 +-
>   arch/arm/boot/dts/at91sam9g35ek.dts         |    4 +-
>   arch/arm/boot/dts/at91sam9g45.dtsi          |  213 +++++++++++++++++++++++++-------------------------
>   arch/arm/boot/dts/at91sam9m10g45ek.dts      |   38 ++++-----
>   arch/arm/boot/dts/at91sam9n12.dtsi          |  141 +++++++++++++++++-----------------
>   arch/arm/boot/dts/at91sam9n12ek.dts         |   14 ++--
>   arch/arm/boot/dts/at91sam9x25.dtsi          |   22 +++---
>   arch/arm/boot/dts/at91sam9x25ek.dts         |    4 +-
>   arch/arm/boot/dts/at91sam9x35.dtsi          |    2 +-
>   arch/arm/boot/dts/at91sam9x35ek.dts         |    4 +-
>   arch/arm/boot/dts/at91sam9x5.dtsi           |  279 +++++++++++++++++++++++++++++++++---------------------------------
>   arch/arm/boot/dts/at91sam9x5cm.dtsi         |    8 +-
>   arch/arm/boot/dts/at91sam9x5ek.dtsi         |   14 ++--
>   arch/arm/boot/dts/ethernut5.dts             |    6 +-
>   arch/arm/boot/dts/evk-pro3.dts              |    6 +-
>   arch/arm/boot/dts/ge863-pro3.dtsi           |    2 +-
>   arch/arm/boot/dts/kizbox.dts                |   16 ++--
>   arch/arm/boot/dts/mpa1600.dts               |    4 +-
>   arch/arm/boot/dts/pm9g45.dts                |   22 +++---
>   arch/arm/boot/dts/sama5d3.dtsi              |  520 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------
>   arch/arm/boot/dts/sama5d31ek.dts            |    6 +-
>   arch/arm/boot/dts/sama5d33ek.dts            |    4 +-
>   arch/arm/boot/dts/sama5d34ek.dts            |    6 +-
>   arch/arm/boot/dts/sama5d35ek.dts            |    4 +-
>   arch/arm/boot/dts/sama5d3xcm.dtsi           |    4 +-
>   arch/arm/boot/dts/sama5d3xdm.dtsi           |    2 +-
>   arch/arm/boot/dts/sama5d3xmb.dtsi           |   26 +++----
>   arch/arm/boot/dts/tny_a9260.dts             |    4 +-
>   arch/arm/boot/dts/tny_a9263.dts             |    4 +-
>   arch/arm/boot/dts/tny_a9g20.dts             |    4 +-
>   arch/arm/boot/dts/usb_a9260.dts             |    4 +-
>   arch/arm/boot/dts/usb_a9260_common.dtsi     |    6 +-
>   arch/arm/boot/dts/usb_a9263.dts             |    8 +-
>   arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi    |   22 +++---
>   arch/arm/boot/dts/usb_a9g20.dts             |    4 +-
>   include/dt-bindings/pinctrl/at91.h          |   35 +++++++++
>   52 files changed, 1139 insertions(+), 1078 deletions(-)
>   create mode 100644 include/dt-bindings/pinctrl/at91.h
>
> Best Regards,
> J.
>
>


-- 
Nicolas Ferre


From linux at arm.linux.org.uk  Fri May 17 04:31:13 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 09:31:13 +0100
Subject: [PATCH 1/9] I2C: mv64xxx: work around signals causing I2C
 transactions to be aborted
In-Reply-To: <20130517083743.31af4eb0@armhf>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk> <20130517083743.31af4eb0@armhf>
Message-ID: <20130517083113.GZ18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 08:37:43AM +0200, Jean-Francois Moine wrote:
> On Thu, 16 May 2013 21:30:59 +0100
> Russell King <rmk+kernel at arm.linux.org.uk> wrote:
> 
> > Do not use interruptible waits in an I2C driver; if a process uses
> > signals (eg, Xorg uses SIGALRM and SIGPIPE) then these signals can
> > cause the I2C driver to abort a transaction in progress by another
> > driver, which can cause that driver to fail.  I2C drivers are not
> > expected to abort transactions on signals.
> 
> Hi Russell,
> 
> I had the same problem with my dove drm driver, but I don't fully agree
> with your solution.
> 
> Using wait_event_timeout() stops the system, and reading the EDID from
> an external screen may take some time.

It doesn't stop the system.  It stops the process until that has completed.
Using the DRM TDA19988 driver, things are nice and quick while reading
the EDID, because it does reads an entire EDID block using one message.

Blocking the signals like you do has exactly the same effect - you
prevent the I2C driver being interrupted by signals.


From fabio.baltieri at linaro.org  Fri May 17 04:33:54 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Fri, 17 May 2013 10:33:54 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <CACRpkdYpEreHKdUyfcANA9kTRAjVbLbpJkBJCq1Q_pAeOKcdxw@mail.gmail.com>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
 <20130516224337.GZ22822@zurbaran>
 <20130517075140.GA25077@balto.lan>
 <CACRpkdYpEreHKdUyfcANA9kTRAjVbLbpJkBJCq1Q_pAeOKcdxw@mail.gmail.com>
Message-ID: <20130517083354.GA32133@balto.lan>

On Fri, May 17, 2013 at 10:25:10AM +0200, Linus Walleij wrote:
> On Fri, May 17, 2013 at 9:51 AM, Fabio Baltieri
> <fabio.baltieri at linaro.org> wrote:
> > Hello Samuel,
> (...)
> > The last two:
> >
> >   mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> >   mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> >
> > are actually fixes for bugs introduced in this merge window that
> > inhibited the ab8500-sysctl driver as a consequence.  Would you
> > reconsider pulling just those?
> 
> A good way to make sure that patches fixing regressions are applied
> to the -rc series is to indicate in the commit message or even the
> heading that it fixes a regression.
> 
> I usually try to begin such commits with the text:
> 
>   this patch fixes a regression caused by change 018745435
>   "foo: fix bar"...
> 
> Then copying in some crash dump text never hurts :-)
> 
> It makes it very easy for us as subsystem maintainers to pick
> regression fixes.

Right, I actually pointed to the culprit commit (applied during the
merge window) in the message, but I'll try to be more direct next time.
I also agree on the crash dump, but unfortunately this one was failing
silently. :-)

Thanks for the tip!
Fabio

-- 
Fabio Baltieri


From jiada_wang at mentor.com  Fri May 17 04:40:45 2013
From: jiada_wang at mentor.com (Jiada Wang)
Date: Fri, 17 May 2013 17:40:45 +0900
Subject: [PATCH 2/2] ARM: imx: remove MLB PLL from pllv3
In-Reply-To: <1368780045-6481-1-git-send-email-jiada_wang@mentor.com>
References: <1368780045-6481-1-git-send-email-jiada_wang@mentor.com>
Message-ID: <1368780045-6481-3-git-send-email-jiada_wang@mentor.com>

MLB PLL should be handled internally in MLB driver,
so remove it from pllv3.

Signed-off-by: Jiada Wang <jiada_wang at mentor.com>
CC: Shawn Guo <shawn.guo at linaro.org>
CC: Dirk Behme <dirk.behme at de.bosch.com>
---
 arch/arm/mach-imx/clk-pllv3.c | 10 ----------
 arch/arm/mach-imx/clk.h       |  1 -
 2 files changed, 11 deletions(-)

diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index d09bc3d..a9fad5f 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
 	.recalc_rate	= clk_pllv3_enet_recalc_rate,
 };
 
-static const struct clk_ops clk_pllv3_mlb_ops = {
-	.prepare	= clk_pllv3_prepare,
-	.unprepare	= clk_pllv3_unprepare,
-	.enable		= clk_pllv3_enable,
-	.disable	= clk_pllv3_disable,
-};
-
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 			  const char *parent_name, void __iomem *base,
 			  u32 div_mask)
@@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 	case IMX_PLLV3_ENET:
 		ops = &clk_pllv3_enet_ops;
 		break;
-	case IMX_PLLV3_MLB:
-		ops = &clk_pllv3_mlb_ops;
-		break;
 	default:
 		ops = &clk_pllv3_ops;
 	}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c..bcaafe9 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -18,7 +18,6 @@ enum imx_pllv3_type {
 	IMX_PLLV3_USB,
 	IMX_PLLV3_AV,
 	IMX_PLLV3_ENET,
-	IMX_PLLV3_MLB,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-- 
1.8.1.1



From jiada_wang at mentor.com  Fri May 17 04:40:44 2013
From: jiada_wang at mentor.com (Jiada Wang)
Date: Fri, 17 May 2013 17:40:44 +0900
Subject: [PATCH 1/2] ARM: imx: disable pll8_mlb in mx6q_clks
In-Reply-To: <1368780045-6481-1-git-send-email-jiada_wang@mentor.com>
References: <1368780045-6481-1-git-send-email-jiada_wang@mentor.com>
Message-ID: <1368780045-6481-2-git-send-email-jiada_wang@mentor.com>

The MLB PLL clock's operation doesn't fit for clock framework and
it should be handled internally in MLB driver.
Remove initialization of pll8_mlb clock device but leave its
declaration in mx6q_clks to avoid affecting imx6q clock numbering.

Signed-off-by: Jiada Wang <jiada_wang at mentor.com>
CC: Shawn Guo <shawn.guo at linaro.org>
CC: Dirk Behme <dirk.behme at de.bosch.com>
---
 arch/arm/mach-imx/clk-imx6q.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1512590..795e718 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -311,7 +311,6 @@ int __init mx6q_clocks_init(void)
 	clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,	"pll5_video",	"osc", base + 0xa0, 0x7f);
 	clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,	"pll6_enet",	"osc", base + 0xe0, 0x3);
 	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);
-	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x0);
 
 	/*
 	 * Bit 20 is the reserved and read-only bit, we do this only for:
-- 
1.8.1.1



From jiada_wang at mentor.com  Fri May 17 04:40:43 2013
From: jiada_wang at mentor.com (Jiada Wang)
Date: Fri, 17 May 2013 17:40:43 +0900
Subject: [PATCH 0/2] remove MLB PLL clock device
Message-ID: <1368780045-6481-1-git-send-email-jiada_wang@mentor.com>

As MLB PLL is not suitable to be handled outside MLB driver.
This patch series removes MLB PLL (pll8_mlb) from clk-imx6q
and pllv3.

Jiada Wang (2):
  ARM: imx: disable pll8_mlb in mx6q_clks
  ARM: imx: remove MLB PLL from pllv3

 arch/arm/mach-imx/clk-imx6q.c |  1 -
 arch/arm/mach-imx/clk-pllv3.c | 10 ----------
 arch/arm/mach-imx/clk.h       |  1 -
 3 files changed, 12 deletions(-)

-- 
1.8.1.1



From steve.capper at linaro.org  Fri May 17 04:41:25 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Fri, 17 May 2013 09:41:25 +0100
Subject: [RFC PATCH v2 09/11] ARM64: mm: HugeTLB support.
In-Reply-To: <20130516143236.GD18308@arm.com>
References: <1368006763-30774-1-git-send-email-steve.capper@linaro.org>
 <1368006763-30774-10-git-send-email-steve.capper@linaro.org>
 <20130516143236.GD18308@arm.com>
Message-ID: <20130517084124.GA22241@linaro.org>

On Thu, May 16, 2013 at 03:32:36PM +0100, Catalin Marinas wrote:
> On Wed, May 08, 2013 at 10:52:41AM +0100, Steve Capper wrote:
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/hugetlb.h
> ...
> > +static inline int pud_large(pud_t pud)
> > +{
> > +	return !(pud_val(pud) & PUD_TABLE_BIT);
> > +}
> 
> I already commented on this - do we really need pud_large() which is
> the same as pud_huge()? It's only defined on x86 and can be safely
> replaced with pud_huge().
> 

Thanks, yes, sorry this one slipped through the cracks.
I'll update this to use pud_huge.

> > --- /dev/null
> > +++ b/arch/arm64/mm/hugetlbpage.c
> > @@ -0,0 +1,70 @@
> ...
> > +int pmd_huge(pmd_t pmd)
> > +{
> > +	return !(pmd_val(pmd) & PMD_TABLE_BIT);
> > +}
> > +
> > +int pud_huge(pud_t pud)
> > +{
> > +	return !(pud_val(pud) & PUD_TABLE_BIT);
> > +}
> 
> You could even go further and make pud/pmd_huge static inline functions
> for slightly better efficiency (needs changing in the linux/hugetlb.h
> header).

I'll have to have a think about this and a tinker :-). 

Cheers,
-- 
Steve


From will.deacon at arm.com  Fri May 17 04:45:42 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 09:45:42 +0100
Subject: [PATCH] ARM: remove the .vm_mm value from gate_vma.
In-Reply-To: <1368702394-1737-1-git-send-email-steve.capper@linaro.org>
References: <1368702394-1737-1-git-send-email-steve.capper@linaro.org>
Message-ID: <20130517084542.GA22992@mudshark.cambridge.arm.com>

On Thu, May 16, 2013 at 12:06:34PM +0100, Steve Capper wrote:
> If one reads /proc/$PID/smaps, the mmap_sem belonging to the
> address space of the task being examined is locked for reading.
> All the pages of the vmas belonging to the task's address space
> are then walked with this lock held.
> 
> If a gate_vma is present in the architecture, it too is examined
> by the fs/proc/task_mmu.c code. As gate_vma doesn't belong to the
> address space of the task though, its pages are not walked.
> 
> A recent cleanup (commit f6604efe) of the gate_vma initialisation
> code set the vm_mm value to &init_mm. Unfortunately a non-NULL
> vm_mm value in the gate_vma will cause the task_mmu code to attempt
> to walk the pages of the gate_vma (with no mmap-sem lock held). If
> one enables Transparent Huge Page support and vm debugging, this
> will then cause OOPses as pmd_trans_huge_lock is called without
> mmap_sem being locked.
> 
> This patch removes the .vm_mm value from gate_vma, restoring the
> original behaviour of the task_mmu code.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> ---
>  arch/arm/kernel/process.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index f219703..282de48 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -411,7 +411,6 @@ static struct vm_area_struct gate_vma = {
>  	.vm_start	= 0xffff0000,
>  	.vm_end		= 0xffff0000 + PAGE_SIZE,
>  	.vm_flags	= VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
> -	.vm_mm		= &init_mm,
>  };
>  
>  static int __init gate_vma_init(void)

Thanks to the wonders of Mimecrap, which decided to sit on most of my email
yesterday, I only just received this patch.

I see it's in the patch system, but for the record:

  Acked-by: Will Deacon <will.deacon at arm.com>

Cheers,

Will


From mkl at pengutronix.de  Fri May 17 04:51:00 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Fri, 17 May 2013 10:51:00 +0200
Subject: [PATCH] can: flexcan: allow compilation on arm and powerpc
In-Reply-To: <20130517020351.GE3893@S2101-09.ap.freescale.net>
References: <1368711756-22324-1-git-send-email-mkl@pengutronix.de>
 <20130517020351.GE3893@S2101-09.ap.freescale.net>
Message-ID: <5195EF74.8070005@pengutronix.de>

On 05/17/2013 04:03 AM, Shawn Guo wrote:
> Hi Marc,
> 
> On Thu, May 16, 2013 at 03:42:36PM +0200, Marc Kleine-Budde wrote:
>> This patch removes the Kconfig symbols HAVE_CAN_FLEXCAN and
>> IMX_HAVE_PLATFORM_FLEXCAN from arch/{arm,powerpc} and allowing compilation on
>> all arm and powerpc platforms.
> 
> I'm generally fine with the approach.  But with Kconfig symbol
> IMX_HAVE_PLATFORM_FLEXCAN removed, how does the build of
> platform-flexcan.o work?
> 
> arch/arm/mach-imx/devices/Makefile:obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o

Doh! - I've removed too much, will change.

Tnx,
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From will.deacon at arm.com  Fri May 17 04:55:31 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 09:55:31 +0100
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
Message-ID: <20130517085530.GB22992@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 03:16:40AM +0100, Ming Lei wrote:
> Hi,

Hello,

> The commit a43cb95d5(dump_stack: unify debug information printed by show_regs())
> caused ARM perf regression, then 'perf top' outputs mistakenly, see
> [1].  The correct
> output should be [2], which can be got after reverting the commit or
> doing it partly
> by the one line change below:
> 
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index f219703..89bc3a4 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -225,7 +225,7 @@ void __show_regs(struct pt_regs *regs)
>         unsigned long flags;
>         char buf[64];
> 
> -       show_regs_print_info(KERN_DEFAULT);
> +       //show_regs_print_info(KERN_DEFAULT);
> 
> 
> Looks a bit weird, anyone can give a hint?

So it's still the morning and I haven't had my coffee yet, but I'm really
struggling to see what you're getting at. Why does this have anything to do
with perf?

> [1], 'perf top' mistaken output
> Samples: 17K of event 'cpu-clock', Event count (approx.): 3516532661
>  97.51%  [smsc95xx]            [k] 0x013645b8
>   0.21%  libc-2.15.so          [.] strstr
>   0.14%  libc-2.15.so          [.] strchr
>   0.12%  libc-2.15.so          [.] strcmp

[...]

> [2], 'perf top' correct output
> Samples: 46K of event 'cpu-clock', Event count (approx.): 937128704
>  96.44%  [kernel]            [k] cpuidle_enter_state
>   0.19%  libc-2.15.so        [.] strstr
>   0.16%  [kernel]            [k] kallsyms_expand_symbol.clone.0
>   0.13%  [kernel]            [k] _raw_spin_unlock_irq

[...]

Are you saying that the profile you're seeing is radically different,
rather than there being some formatting error that I can't spot? If so, that
sounds really strange and I can't see how the patch you mention is to
blame...

If we want to persue this, I guess other obvious questions are: which kernel
are you running? Does this affect multiple architectures (your diff only
changes ARM)? What's the workload which you are profiling?

Will


From shawn.guo at linaro.org  Fri May 17 04:57:15 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 16:57:15 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <5396520.ZTuSn9S4Vd@wuerfel>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-3-git-send-email-b35083@freescale.com>
 <5396520.ZTuSn9S4Vd@wuerfel>
Message-ID: <20130517085714.GG8607@S2101-09.ap.freescale.net>

Arnd,

Allow me help respond a little bit.

On Thu, May 16, 2013 at 12:29:28PM +0200, Arnd Bergmann wrote:
> On Thursday 16 May 2013 14:10:46 Jingchang Lu wrote:
> 
> > index a402248..b9c01a1 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -835,6 +835,21 @@ config SOC_IMX6SL
> >  	help
> >  	  This enables support for Freescale i.MX6 SoloLite processor.
> >  
> > +config SOC_MVF600
> > +	bool "Vybrid Family MVF600 support"
> > +	select CPU_V7
> > +	select ARM_GIC
> > +	select CLKSRC_OF
> > +	select PINCTRL
> > +	select PINCTRL_MVF600
> > +	select MVF600_PIT_TIMER
> > +	select PL310_ERRATA_588369 if CACHE_PL310
> > +	select PL310_ERRATA_727915 if CACHE_PL310
> > +	select PL310_ERRATA_769419 if CACHE_PL310
> > +
> > +	help
> > +	  This enable support for Freescale Vybrid MVF600 processor.
> > +
> >  endif
> 
> Shouldn't that 'depends on ARCH_MULTI_V7'?
> 
SOC_MVF600 is added as a sub-item of ARCH_MXC which already handles the
ARCH_MULTI_* dependency.

> Can you describe how much Vybrid is actually like MXC? Do you actually
> use most of the mach-imx code?
> 
Jingchang mentioned some IP blocks shared between IMX and Vybrid.  Right
now, mvf600 reuses mxc_restart() and some amount of clk code
clk-pllv3.c, clk-gate2.c clk.c etc. in arch/arm/mach-imx.

> > diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> > index 208e76f..55cdba0 100644
> > --- a/arch/arm/mach-imx/common.h
> > +++ b/arch/arm/mach-imx/common.h
> > @@ -70,6 +70,7 @@ extern int mx51_clocks_init_dt(void);
> >  extern int mx53_clocks_init_dt(void);
> >  extern int mx6q_clocks_init(void);
> >  extern int imx6sl_clocks_init(void);
> > +extern int mvf600_clocks_init(void);
> >  extern struct platform_device *mxc_register_gpio(char *name, int id,
> >  	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
> >  extern void mxc_set_cpu_type(unsigned int type);
> 
> This hunk belongs into the first patch, right?
> 
The declaration is only used in this patch by mach-mvf600.c.

> Actually I think you should move that driver to drivers/clk and use
> of_clk_init(NULL) to initialize it.
> 
The mvf600 clock driver uses a lot of base clk support from mach-imx,
and can not be moved into drivers/clk as a single driver.  Right now, in
IMX clock drivers, we call of_clk_init() to only register fixed rate
clocks, since all the other clocks are not represented in device tree.

> > +static void __init mvf600_init_machine(void)
> > +{
> > +	mxc_arch_reset_init_dt();
> 
> I don't see the mxc_arch_reset_init_dt function in 3.10-rc1. Where does it
> get introduced?
> 
It gets introduced by my series below.  And I guess Jiangchang is basing
his series on my imx/soc branch.

http://thread.gmane.org/gmane.linux.ports.arm.kernel/235986/focus=236091

> It would be nice if we could integrate that into the watchdog driver,
> so that driver just registers a pm_restart function when it gets loaded.
> It is a rather small driver, so it would not hurt to always load it.
> 
Sound like a good idea.  We will consider it as another cleanup task for
mach-imx.

> > +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> > +}
> 
> It would be nicer if you could just use the default init_machine.
> 
> > +static void __init mvf600_init_irq(void)
> > +{
> > +	struct device_node *np;
> > +	void __iomem *mscm_base;
> > +	int i;
> > +
> > +	l2x0_of_init(0, ~0UL);
> > +
> > +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm");
> > +	mscm_base = of_iomap(np, 0);
> > +	if (!mscm_base)
> > +		return;
> > +
> > +	/* route all shared peripheral interrupts to CP0 */
> > +	for (i = 0; i < 111; i++)
> > +		__raw_writew(1, mscm_base + 0x880 + 2 * i);
> > +
> > +	iounmap(mscm_base);
> > +
> > +	irqchip_init();
> > +}
> 
> What is the mscm? Shouldn't the boot loader have set this up correctly?
> If you can remove that code from the kernel, you can use the default
> irqchip_init call.
> 
Yeah, and if we find another way for l2x0_of_init() call.

> > +static void __init mvf600_init_time(void)
> > +{
> > +	mvf600_clocks_init();
> > +	clocksource_of_init();
> > +}
> 
> I would like to call of_clk_init(NULL) unconditionally on all machines
> in 3.11, so this function could also go away.
> 
of_clk_init() has been called in mvf600_clocks_init(), but as explained
as above, it only registers fixed rate clocks and can not save
mvf600_clocks_init() call right now where most of mvf600 clocks gets
registered.

> > +static const char *mvf600_dt_compat[] __initdata = {
> > +	"fsl,mvf600",
> > +	NULL,
> > +};
> > +
> > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)")
> > +	.init_irq	= mvf600_init_irq,
> > +	.init_time	= mvf600_init_time,
> > +	.init_machine   = mvf600_init_machine,
> > +	.dt_compat	= mvf600_dt_compat,
> > +	.restart	= mxc_restart,
> > +MACHINE_END
> 
> If we can do all of the above, we can actually remove the entire machine
> descriptor here, since all its members are NULL.
> 
Yeah, we understand the goal, and this will be the goal of mach-imx
cleanup.

Shawn



From mkl at pengutronix.de  Fri May 17 04:59:17 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Fri, 17 May 2013 10:59:17 +0200
Subject: [PATCH v2] can: flexcan: remove HAVE_CAN_FLEXCAN Kconfig symbol
Message-ID: <1368781157-4646-1-git-send-email-mkl@pengutronix.de>

This patch removes the Kconfig symbol HAVE_CAN_FLEXCAN from arch/{arm,powerpc}
and allowing compilation unconditionally on all arm and powerpc platforms.

This brings a bigger compile time coverage and removes the following dependency
warning found by Arnd Bergmann:

    warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 && IMX_HAVE_PLATFORM_FLEXCAN &&
        SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
    which has unmet direct dependencies (NET && CAN && CAN_DEV)

Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Kumar Gala <galak at kernel.crashing.org>
Cc: U Bhaskar-B22300 <B22300 at freescale.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
---
Changes since v1:
- don't remove IMX_HAVE_PLATFORM_FLEXCAN, which breaks non DT imx platforms
  tnx Shawn

 arch/arm/mach-imx/Kconfig         | 4 ----
 arch/arm/mach-imx/devices/Kconfig | 1 -
 arch/arm/mach-mxs/Kconfig         | 1 -
 arch/powerpc/Kconfig              | 1 -
 drivers/net/can/Kconfig           | 5 +----
 5 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328..af8e109 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -111,7 +111,6 @@ config SOC_IMX25
 	select ARCH_MXC_IOMUX_V3
 	select COMMON_CLK
 	select CPU_ARM926T
-	select HAVE_CAN_FLEXCAN if CAN
 	select MXC_AVIC
 
 config SOC_IMX27
@@ -137,7 +136,6 @@ config SOC_IMX35
 	select ARCH_MXC_IOMUX_V3
 	select COMMON_CLK
 	select CPU_V6K
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_EPIT
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
@@ -776,7 +774,6 @@ comment "Device tree only"
 
 config	SOC_IMX53
 	bool "i.MX53 support"
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_IMX_SRC
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select PINCTRL
@@ -799,7 +796,6 @@ config SOC_IMX6Q
 	select CPU_V7
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if LOCAL_TIMERS
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_IMX_ANATOP
 	select HAVE_IMX_GPC
 	select HAVE_IMX_MMDC
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 3dd2b1b..68c74fb 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -4,7 +4,6 @@ config IMX_HAVE_PLATFORM_FEC
 
 config IMX_HAVE_PLATFORM_FLEXCAN
 	bool
-	select HAVE_CAN_FLEXCAN if CAN
 
 config IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	bool
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4dc2fbb..ce6e7d6 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -11,7 +11,6 @@ config SOC_IMX28
 	select ARM_AMBA
 	select ARM_CPU_SUSPEND if PM
 	select CPU_ARM926T
-	select HAVE_CAN_FLEXCAN if CAN
 	select HAVE_PWM
 	select PINCTRL_IMX28
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c33e3ad..7754c6b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -674,7 +674,6 @@ config SBUS
 
 config FSL_SOC
 	bool
-	select HAVE_CAN_FLEXCAN if NET && CAN
 
 config FSL_PCI
  	bool
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index e456b70..3c06947 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -102,12 +102,9 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config HAVE_CAN_FLEXCAN
-	bool
-
 config CAN_FLEXCAN
 	tristate "Support for Freescale FLEXCAN based chips"
-	depends on HAVE_CAN_FLEXCAN
+	depends on ARM || PPC
 	---help---
 	  Say Y here if you want to support for Freescale FlexCAN.
 
-- 
1.8.2.rc2



From srinivas.kandagatla at st.com  Fri May 17 04:57:07 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 17 May 2013 09:57:07 +0100
Subject: ux500 breaking multi-platform kernels
In-Reply-To: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
References: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
Message-ID: <5195F0E3.6020402@st.com>

On 15/05/13 21:30, Rob Herring wrote:
> @@ -39,10 +39,10 @@ static int __init ux500_l2x0_init(void)
>  {
>         u32 aux_val = 0x3e000000;
> 
> -       if (cpu_is_u8500_family() || cpu_is_ux540_family())
> -               l2x0_base = __io_address(U8500_L2CC_BASE);
> -       else
> -               ux500_unknown_soc();
> +       if (!(cpu_is_u8500_family() || cpu_is_ux540_family()))
> +               return -ENODEV;
> +
> +       l2x0_base = __io_address(U8500_L2CC_BASE);

I think moving
early_initcall(ux500_l2x0_init);

to
MACHINE
.init_early = ux500_l2x0_init

should solve this issue neatly.


--srini





From gwenhael.goavec-merou at armadeus.com  Fri May 17 05:06:14 2013
From: gwenhael.goavec-merou at armadeus.com (gwenhael.goavec)
Date: Fri, 17 May 2013 11:06:14 +0200
Subject: [PATCH] ARM: imx: apf51: add nfc support
In-Reply-To: <20130517080312.GE8607@S2101-09.ap.freescale.net>
References: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
 <1368767622-12968-2-git-send-email-gwenhael.goavec-merou@armadeus.com>
 <20130517080312.GE8607@S2101-09.ap.freescale.net>
Message-ID: <20130517110614.553b1c6d@x230>

On Fri, 17 May 2013 16:03:14 +0800
Shawn Guo <shawn.guo at linaro.org> wrote:

> On Fri, May 17, 2013 at 07:13:42AM +0200, Gwenhael Goavec-Merou wrote:
> > 
> > Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>
> 
> I already applied the patch [1], so this one can be ignored? 
> 
Yes,
It's a wrong manip.

Sorry.

Gwen


From shawn.guo at linaro.org  Fri May 17 05:08:17 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 17:08:17 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <1368684648-20826-3-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-3-git-send-email-b35083@freescale.com>
Message-ID: <20130517090815.GH8607@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:10:46PM +0800, Jingchang Lu wrote:
> Add initial support for Vybrid MVF600 SoC.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   remove unused #include header lines.

There are more ...

> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/clk.h>
> +#include <linux/clocksource.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqchip/arm-gic.h>
> +#include <asm/mach/arch.h>
> +#include <asm/hardware/cache-l2x0.h>
> +#include <asm/system_misc.h>

#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/system_misc.h>

I do not see how these 4 headers are needed.

Shawn



From shawn.guo at linaro.org  Fri May 17 05:09:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 17:09:51 +0800
Subject: [PATCH v2] can: flexcan: remove HAVE_CAN_FLEXCAN Kconfig symbol
In-Reply-To: <1368781157-4646-1-git-send-email-mkl@pengutronix.de>
References: <1368781157-4646-1-git-send-email-mkl@pengutronix.de>
Message-ID: <20130517090949.GI8607@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 10:59:17AM +0200, Marc Kleine-Budde wrote:
> This patch removes the Kconfig symbol HAVE_CAN_FLEXCAN from arch/{arm,powerpc}
> and allowing compilation unconditionally on all arm and powerpc platforms.
> 
> This brings a bigger compile time coverage and removes the following dependency
> warning found by Arnd Bergmann:
> 
>     warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 && IMX_HAVE_PLATFORM_FLEXCAN &&
>         SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
>     which has unmet direct dependencies (NET && CAN && CAN_DEV)
> 
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Kumar Gala <galak at kernel.crashing.org>
> Cc: U Bhaskar-B22300 <B22300 at freescale.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linuxppc-dev at lists.ozlabs.org
> Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>



From list-09_linuc_arm at tqsc.de  Fri May 17 05:19:51 2013
From: list-09_linuc_arm at tqsc.de (Markus Niebel)
Date: Fri, 17 May 2013 11:19:51 +0200
Subject: [PATCH 1/3] staging: drm/imx: set correct sync pins for parallel
 display
In-Reply-To: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368782393-9660-2-git-send-email-list-09_linuc_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

Have to call imx_drm_crtc_panel_format_pins with the correct pins instead of (0, 0)
This enables configuration of correct waveforms for vsync / hsync

TODO: configure pins via device tree

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
---
 drivers/staging/imx-drm/parallel-display.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index e7fba62..e49a906 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -114,8 +114,8 @@ static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
 
-	imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_NONE,
-			imxpd->interface_pix_fmt);
+	imx_drm_crtc_panel_format_pins(encoder->crtc, DRM_MODE_ENCODER_NONE,
+			imxpd->interface_pix_fmt, 2, 3);
 }
 
 static void imx_pd_encoder_commit(struct drm_encoder *encoder)
-- 
1.7.9.5



From list-09_linuc_arm at tqsc.de  Fri May 17 05:19:50 2013
From: list-09_linuc_arm at tqsc.de (Markus Niebel)
Date: Fri, 17 May 2013 11:19:50 +0200
Subject: [PATCH 0/3] staging: fix parallel display regressions
Message-ID: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

Support for VGA via TVE on iMX53 causes  regression, which prevents
parallel display from working. This series brings the parallel display
functionality back.

Tested on a modified v3.9 with TQMa53 module and compile tested with
v3.10-rc1.

Markus Niebel (3):
  staging: drm/imx: set correct sync pins for parallel display
  staging: drm/imx: fix spelling error for vsync flag config
  staging: drm/imx: revert vsync_cnt for di->id 1

 drivers/staging/imx-drm/ipu-v3/ipu-di.c    |   13 +++++++++----
 drivers/staging/imx-drm/parallel-display.c |    4 ++--
 2 files changed, 11 insertions(+), 6 deletions(-)

-- 
1.7.9.5



From list-09_linuc_arm at tqsc.de  Fri May 17 05:19:52 2013
From: list-09_linuc_arm at tqsc.de (Markus Niebel)
Date: Fri, 17 May 2013 11:19:52 +0200
Subject: [PATCH 2/3] staging: drm/imx: fix spelling error for vsync flag config
In-Reply-To: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368782393-9660-3-git-send-email-list-09_linuc_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

Have to check for vsync_pin instead of hsync_pin to set Vsync_pol.

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
---
 drivers/staging/imx-drm/ipu-v3/ipu-di.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index 19d777e..e7b9c98 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
@@ -614,11 +614,11 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 				di_gen |= DI_GEN_POLARITY_7;
 		}
 		if (sig->Vsync_pol) {
-			if (sig->hsync_pin == 3)
+			if (sig->vsync_pin == 3)
 				di_gen |= DI_GEN_POLARITY_3;
-			else if (sig->hsync_pin == 6)
+			else if (sig->vsync_pin == 6)
 				di_gen |= DI_GEN_POLARITY_6;
-			else if (sig->hsync_pin == 8)
+			else if (sig->vsync_pin == 8)
 				di_gen |= DI_GEN_POLARITY_8;
 		}
 	}
-- 
1.7.9.5



From list-09_linuc_arm at tqsc.de  Fri May 17 05:19:53 2013
From: list-09_linuc_arm at tqsc.de (Markus Niebel)
Date: Fri, 17 May 2013 11:19:53 +0200
Subject: [PATCH 3/3] staging: drm/imx: revert vsync_cnt for di->id 1
In-Reply-To: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368782393-9660-4-git-send-email-list-09_linuc_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

parallel display support / DVI needs the original setting to work

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
---
 drivers/staging/imx-drm/ipu-v3/ipu-di.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index e7b9c98..0b6806e 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
@@ -603,7 +603,12 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 		vsync_cnt = 3;
 		if (di->id == 1)
-			vsync_cnt = 6;
+			/*
+			 * TODO: change only for TVEv2, parallel display
+			 * uses pin 2 / 3
+			 */
+			if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
+				vsync_cnt = 6;
 
 		if (sig->Hsync_pol) {
 			if (sig->hsync_pin == 2)
-- 
1.7.9.5



From moinejf at free.fr  Fri May 17 05:23:16 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Fri, 17 May 2013 11:23:16 +0200
Subject: [PATCH 3/9] I2C: mv64xxx: use devm_ioremap_resource()
In-Reply-To: <E1Ud4rN-0004Jc-CL@rmk-PC.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4rN-0004Jc-CL@rmk-PC.arm.linux.org.uk>
Message-ID: <20130517112316.12a3ddc3@armhf>

On Thu, 16 May 2013 21:33:09 +0100
Russell King <rmk+kernel at arm.linux.org.uk> wrote:

> Eliminate reg_base_p and reg_size, mv64xxx_i2c_unmap_regs() and an
> unchecked ioremap() return from this driver by using the devm_*
> API for requesting and ioremapping resources.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  drivers/i2c/busses/i2c-mv64xxx.c |   46 +++++---------------------------------
>  1 files changed, 6 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
> index 0339cd8..19cc9bf 100644
> --- a/drivers/i2c/busses/i2c-mv64xxx.c
> +++ b/drivers/i2c/busses/i2c-mv64xxx.c
	[snip]
> @@ -704,7 +671,6 @@ mv64xxx_i2c_remove(struct platform_device *dev)
>  
>  	rc = i2c_del_adapter(&drv_data->adapter);
>  	free_irq(drv_data->irq, drv_data);
> -	mv64xxx_i2c_unmap_regs(drv_data);
>  #if defined(CONFIG_HAVE_CLK)
>  	/* Not all platforms have a clk */
>  	if (!IS_ERR(drv_data->clk)) {

The patch does not apply: it seems it lacks:

+	int rc;

-	i2c_del_adapter(&drv_data->adapter);
+	rc = i2c_del_adapter(&drv_data->adapter);

-	return 0;
+	return rc;

BTW, is this return code useful?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From ming.lei at canonical.com  Fri May 17 05:27:05 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 17 May 2013 17:27:05 +0800
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <20130517085530.GB22992@mudshark.cambridge.arm.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>

On Fri, May 17, 2013 at 4:55 PM, Will Deacon <will.deacon at arm.com> wrote:
>
> So it's still the morning and I haven't had my coffee yet, but I'm really
> struggling to see what you're getting at. Why does this have anything to do
> with perf?

I don't know, and I just report it out, :-)

I found the problem days ago, and until yesterday I had one more hours to
git-bisect it, but the result is very frustrated.

>
>> [1], 'perf top' mistaken output
>> Samples: 17K of event 'cpu-clock', Event count (approx.): 3516532661
>>  97.51%  [smsc95xx]            [k] 0x013645b8
>>   0.21%  libc-2.15.so          [.] strstr
>>   0.14%  libc-2.15.so          [.] strchr
>>   0.12%  libc-2.15.so          [.] strcmp
>
> [...]
>
>> [2], 'perf top' correct output
>> Samples: 46K of event 'cpu-clock', Event count (approx.): 937128704
>>  96.44%  [kernel]            [k] cpuidle_enter_state
>>   0.19%  libc-2.15.so        [.] strstr
>>   0.16%  [kernel]            [k] kallsyms_expand_symbol.clone.0
>>   0.13%  [kernel]            [k] _raw_spin_unlock_irq
>
> [...]
>
> Are you saying that the profile you're seeing is radically different,
> rather than there being some formatting error that I can't spot? If so, that

Yes.

> sounds really strange and I can't see how the patch you mention is to
> blame...
>
> If we want to persue this, I guess other obvious questions are: which kernel
> are you running? Does this affect multiple architectures (your diff only

Either 3.10-rc1 or today's -next tree(3.10.0-rc1-next-20130516).

> changes ARM)? What's the workload which you are profiling?

I only tested it on Pandaboard, and no real workload, so you can see
cpuidle_enter_state is the top frequent symbol.

Or could anyone else try to verify the problem on their own environment?

Thanks,
--
Ming Lei


From b32955 at freescale.com  Fri May 17 05:15:23 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 17 May 2013 17:15:23 +0800
Subject: [PATCH] ARM: imx6q: clk: add the eim_slow clock
Message-ID: <1368782123-15523-1-git-send-email-b32955@freescale.com>

Add the eim_slow clock, since the weim needs it.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 .../devicetree/bindings/clock/imx6q-clock.txt      |    1 +
 arch/arm/mach-imx/clk-imx6q.c                      |    3 ++-
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 6deb6fd..a0e104f 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -208,6 +208,7 @@ clocks and IDs.
 	pll4_post_div		193
 	pll5_post_div		194
 	pll5_video_div		195
+	eim_slow      		196
 
 Examples:
 
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 50095dd..441a22d 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -238,7 +238,7 @@ enum mx6q_clks {
 	pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
 	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
 	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
+	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -535,6 +535,7 @@ int __init mx6q_clocks_init(void)
 	clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
 	clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
 	clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+	clk[eim_slow]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
 	clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
 	clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
 	clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
-- 
1.7.1




From jp.francois at cynove.com  Fri May 17 05:32:05 2013
From: jp.francois at cynove.com (jean-philippe francois)
Date: Fri, 17 May 2013 11:32:05 +0200
Subject: 3.9 regression : CAM_XCLKA wrong frequency setting.
Message-ID: <CAGGh5h2RB7OEOpGOe52eE8+LgdSmvDK5rPLueMzQMfVfOCuYHg@mail.gmail.com>

Hi,

Laurent, you are on the recipient list because the symptom is visible
throug your driver. I found the other name looking in the clock
related files. Please apologize if you are not concerned by this mail.

Symptom :
External clock CAM_XCLKA frequency is wrong with 3.9, it was ok until
3.6. Everything else is working fine, except the fps are higher, and
the image quality sucks because the input clock is out of spec.
Oscilloscope measured freq is around 30 MHz instead of the 24 MHz the
sensor is asking for.

Hardware :
dm3730, with 19.2 MHz crystal, running at OPP100

The register frequency settings seems to be ok, and they are the same
as in 3.6.11 :
CM_CLKSEL2_PLL : 0x04816807
        19, 2 * 360 / 8 = 864 MHz
         this value is already set when I look at it in u-boot

CM_CLKSEL_CAM : 0x5
        864 / 5 = 172,8 MHz
        this value is set through the clock framework by the omap3isp
driver code

ISP.TCTRL_CTRL : 0x7
        172,8 / 7 = 24,685... MHz
         this value is set by the omap3isp driver code

However, as stated before, the actual output frequency is NOT 24 MHz
but around 30.

If dpll4 frequency is wrong, what other clock would be affected ?
What can I do to debug this ?
Laurent, I believe you have a camera add-on board for the beagle xm,
could you test and report wether you can reproduce this bug ?

Attached is the boot log with 3.9, with some debugging messages activated.

Thank you for your help,
Regards,

Jean-Philippe Fran?ois
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From will.deacon at arm.com  Fri May 17 05:36:16 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 10:36:16 +0100
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
 <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
Message-ID: <20130517093616.GC23112@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 10:27:05AM +0100, Ming Lei wrote:
> On Fri, May 17, 2013 at 4:55 PM, Will Deacon <will.deacon at arm.com> wrote:
> >
> > So it's still the morning and I haven't had my coffee yet, but I'm really
> > struggling to see what you're getting at. Why does this have anything to do
> > with perf?
> 
> I don't know, and I just report it out, :-)
> 
> I found the problem days ago, and until yesterday I had one more hours to
> git-bisect it, but the result is very frustrated.
> 
> >
> >> [1], 'perf top' mistaken output
> >> Samples: 17K of event 'cpu-clock', Event count (approx.): 3516532661
> >>  97.51%  [smsc95xx]            [k] 0x013645b8
> >>   0.21%  libc-2.15.so          [.] strstr
> >>   0.14%  libc-2.15.so          [.] strchr
> >>   0.12%  libc-2.15.so          [.] strcmp
> >
> > [...]
> >
> >> [2], 'perf top' correct output
> >> Samples: 46K of event 'cpu-clock', Event count (approx.): 937128704
> >>  96.44%  [kernel]            [k] cpuidle_enter_state
> >>   0.19%  libc-2.15.so        [.] strstr
> >>   0.16%  [kernel]            [k] kallsyms_expand_symbol.clone.0
> >>   0.13%  [kernel]            [k] _raw_spin_unlock_irq
> >
> > [...]
> >
> > Are you saying that the profile you're seeing is radically different,
> > rather than there being some formatting error that I can't spot? If so, that
> 
> Yes.
> 
> > sounds really strange and I can't see how the patch you mention is to
> > blame...
> >
> > If we want to persue this, I guess other obvious questions are: which kernel
> > are you running? Does this affect multiple architectures (your diff only
> 
> Either 3.10-rc1 or today's -next tree(3.10.0-rc1-next-20130516).
> 
> > changes ARM)? What's the workload which you are profiling?
> 
> I only tested it on Pandaboard, and no real workload, so you can see
> cpuidle_enter_state is the top frequent symbol.

It's probably easier if you choose a workload, otherwise it's difficult to
see what is `correct' and what is broken. For example, your broken output
seems to be in the smsc95xx driver, so assumedly there's a bunch of
networking going on whereas your other output is in cpuidle_enter_state.

We need an apples-for-apples comparison if you think there's a bug in the
kernel. Can you try profiling hackbench or something?

> Or could anyone else try to verify the problem on their own environment?

How are you running perf top?

Will


From linux at arm.linux.org.uk  Fri May 17 05:34:49 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 10:34:49 +0100
Subject: [PATCH 3/9] I2C: mv64xxx: use devm_ioremap_resource()
In-Reply-To: <20130517112316.12a3ddc3@armhf>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4rN-0004Jc-CL@rmk-PC.arm.linux.org.uk> <20130517112316.12a3ddc3@armhf>
Message-ID: <20130517093449.GA18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 11:23:16AM +0200, Jean-Francois Moine wrote:
> On Thu, 16 May 2013 21:33:09 +0100
> Russell King <rmk+kernel at arm.linux.org.uk> wrote:
> 
> > Eliminate reg_base_p and reg_size, mv64xxx_i2c_unmap_regs() and an
> > unchecked ioremap() return from this driver by using the devm_*
> > API for requesting and ioremapping resources.
> > 
> > Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> > ---
> >  drivers/i2c/busses/i2c-mv64xxx.c |   46 +++++---------------------------------
> >  1 files changed, 6 insertions(+), 40 deletions(-)
> > 
> > diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
> > index 0339cd8..19cc9bf 100644
> > --- a/drivers/i2c/busses/i2c-mv64xxx.c
> > +++ b/drivers/i2c/busses/i2c-mv64xxx.c
> 	[snip]
> > @@ -704,7 +671,6 @@ mv64xxx_i2c_remove(struct platform_device *dev)
> >  
> >  	rc = i2c_del_adapter(&drv_data->adapter);
> >  	free_irq(drv_data->irq, drv_data);
> > -	mv64xxx_i2c_unmap_regs(drv_data);
> >  #if defined(CONFIG_HAVE_CLK)
> >  	/* Not all platforms have a clk */
> >  	if (!IS_ERR(drv_data->clk)) {
> 
> The patch does not apply: it seems it lacks:

I should've mentioned that the patches are against v3.9, not v3.10-rc1.

> +	int rc;
> 
> -	i2c_del_adapter(&drv_data->adapter);
> +	rc = i2c_del_adapter(&drv_data->adapter);
> 
> -	return 0;
> +	return rc;
> 
> BTW, is this return code useful?

No it isn't.  Removals *can't* fail.  Once the remove function is called,
the device _will_ be unbound no matter what the return value of that
function is.  The module will also be unloaded (if that's why it's being
unbound) whether or not you return an error.

So, removals must always succeed.  Why their return type hasn't been void
from the start I've no idea - but that's a question for Patrick Mochel
who implemented the original driver model design.


From ming.lei at canonical.com  Fri May 17 05:48:23 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 17 May 2013 17:48:23 +0800
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <20130517093616.GC23112@mudshark.cambridge.arm.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
 <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
 <20130517093616.GC23112@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVP56EJb0BZ+w6hVAukQ-mN0e0Jn_GLw3XqXQqMwVGfNdA@mail.gmail.com>

On Fri, May 17, 2013 at 5:36 PM, Will Deacon <will.deacon at arm.com> wrote:
>
> It's probably easier if you choose a workload, otherwise it's difficult to
> see what is `correct' and what is broken. For example, your broken output
> seems to be in the smsc95xx driver, so assumedly there's a bunch of
> networking going on whereas your other output is in cpuidle_enter_state.

If all modules are removed, the result will become OK. And if I only insert one
module, the top sample will fall inside the only module, but I am sure
nothing is working on the symbols of the module.

>
> We need an apples-for-apples comparison if you think there's a bug in the
> kernel. Can you try profiling hackbench or something?
>
>> Or could anyone else try to verify the problem on their own environment?
>
> How are you running perf top?

sudo perf top

Thanks
--
Ming Lei


From wsa at the-dreams.de  Fri May 17 05:51:51 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Fri, 17 May 2013 11:51:51 +0200
Subject: [PATCH 9/9] I2C: mv64xxx: fix race between FSM/interrupt and
 process context
In-Reply-To: <E1Ud4xE-0004KB-2T@rmk-PC.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4xE-0004KB-2T@rmk-PC.arm.linux.org.uk>
Message-ID: <20130517095149.GI17056@katana>


> @@ -271,12 +273,25 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
>  {
>  	switch(drv_data->action) {
>  	case MV64XXX_I2C_ACTION_SEND_RESTART:
> +		/* We should only get here if we have further messages */
> +		BUG_ON(drv_data->num_msgs == 0);
> +

...

> @@ -453,16 +463,20 @@ static int
>  mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  {
>  	struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
> -	int	i, rc;
> +	int rc, ret = num;
>  
> -	for (i = 0; i < num; i++) {
> -		rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
> -						i == 0, i + 1 == num);
> -		if (rc < 0)
> -			return rc;
> -	}
> +	BUG_ON(drv_data->msgs != NULL);

Can't we handle this more gracefully than to halt the kernel? Like
WARN_ON and resetting the controller or disabling the bus or...



From josh.wu at atmel.com  Fri May 17 05:51:44 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 17 May 2013 17:51:44 +0800
Subject: [PATCH v2 0/4] mtd: atmel_nand: enable Nand Flash Controller (NFC)
 support
Message-ID: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>

This patch series enable NFC support for SAMA5 soc. It can send command,
address cycles automaticly. Also when enable NFC sram, NFC will transfer
data to sram. Which can save lots of cpu time.

v1 --> v2:
 1) rebase it with latest l2-mtd git tree: 
    - remove useless nand commands (NAND_CMD_DEPLETE1, NAND_CMD_STATUS_ERRORx).
    - adopt to the new nand write function's parameters. Add error message when
      handle subpage write via nfc sram.
 2) rewrite pmecc_enable function. Now I use exist NAND_ECC_READ/WRITE const
    instead of using a new enum definition.

Josh Wu (4):
  mtd: atmel_nand: replace pmecc enable code with one function.
  mtd: atmel_nand: add Nand Flash Controller (NFC) support
  mtd: atmel_nand: enable Nand Flash Controller (NFC) read data via
    sram
  mtd: atmel_nand: enable Nand Flash Controller (NFC) write via sram

 .../devicetree/bindings/mtd/atmel-nand.txt         |    4 +
 drivers/mtd/nand/atmel_nand.c                      |  657 ++++++++++++++++++--
 drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++
 3 files changed, 718 insertions(+), 49 deletions(-)
 create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h

-- 
1.7.9.5



From josh.wu at atmel.com  Fri May 17 05:51:45 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 17 May 2013 17:51:45 +0800
Subject: [PATCH v2 1/4] mtd: atmel_nand: replace pmecc enable code with one
 function.
In-Reply-To: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368784308-7600-2-git-send-email-josh.wu@atmel.com>

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
v1 --> v2:
 use the exist constants (NAND_ECC_READ/WRITE) instead of define new enums.

 drivers/mtd/nand/atmel_nand.c |   40 +++++++++++++++++++++++++---------------
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 2d23d29..f747791 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -763,6 +763,29 @@ normal_check:
 	return total_err;
 }
 
+static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
+{
+	u32 val;
+	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
+	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
+	val = pmecc_readl_relaxed(host->ecc, CFG);
+
+	if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
+		dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
+		return;
+	}
+
+	if (ecc_op == NAND_ECC_READ)
+		pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
+			| PMECC_CFG_AUTO_ENABLE);
+	else
+		pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
+			& ~PMECC_CFG_AUTO_ENABLE);
+
+	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
+	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
+}
+
 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
@@ -774,13 +797,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	unsigned long end_time;
 	int bitflips = 0;
 
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
-	pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
-		& ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
-
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
+	pmecc_enable(host, NAND_ECC_READ);
 
 	chip->read_buf(mtd, buf, eccsize);
 	chip->read_buf(mtd, oob, mtd->oobsize);
@@ -813,14 +830,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 	int i, j;
 	unsigned long end_time;
 
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
-
-	pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
-		PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
-
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
+	pmecc_enable(host, NAND_ECC_WRITE);
 
 	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 
-- 
1.7.9.5



From will.deacon at arm.com  Fri May 17 05:54:23 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 10:54:23 +0100
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <CACVXFVP56EJb0BZ+w6hVAukQ-mN0e0Jn_GLw3XqXQqMwVGfNdA@mail.gmail.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
 <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
 <20130517093616.GC23112@mudshark.cambridge.arm.com>
 <CACVXFVP56EJb0BZ+w6hVAukQ-mN0e0Jn_GLw3XqXQqMwVGfNdA@mail.gmail.com>
Message-ID: <20130517095423.GD23112@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 10:48:23AM +0100, Ming Lei wrote:
> On Fri, May 17, 2013 at 5:36 PM, Will Deacon <will.deacon at arm.com> wrote:
> >
> > It's probably easier if you choose a workload, otherwise it's difficult to
> > see what is `correct' and what is broken. For example, your broken output
> > seems to be in the smsc95xx driver, so assumedly there's a bunch of
> > networking going on whereas your other output is in cpuidle_enter_state.
> 
> If all modules are removed, the result will become OK. And if I only insert one
> module, the top sample will fall inside the only module, but I am sure
> nothing is working on the symbols of the module.

Can you check your dmesg please? I suppose the smsc95xx driver might be
screaming about something and somehow the changes to the reg printing have
made it get stuck.

> >
> > We need an apples-for-apples comparison if you think there's a bug in the
> > kernel. Can you try profiling hackbench or something?
> >
> >> Or could anyone else try to verify the problem on their own environment?
> >
> > How are you running perf top?
> 
> sudo perf top

... and did hackbench make any difference (i.e. is the profile more stable)?

Will


From josh.wu at atmel.com  Fri May 17 05:51:46 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 17 May 2013 17:51:46 +0800
Subject: =?UTF-8?q?=5BPATCH=20v2=202/4=5D=20mtd=3A=20atmel=5Fnand=3A=20add=20Nand=20Flash=20Controller=20=28NFC=29=20support?=
In-Reply-To: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368784308-7600-3-git-send-email-josh.wu@atmel.com>

Nand Flash Controller (NFC) can handle automatic transfers, sending the
commands and address cycles to the NAND Flash.

To use NFC in this driver, the user needs to set the address and size of
NFC command registers, NFC registers (embedded in HSMC) and NFC SRAM in dts.
Also user need to set up the HSMC irq, which use to check whether nfc
command is finish or not.

This driver has been tested on SAMA5D3X-EK board with JFFS2, YAFFS,
UBIFS and mtd-utils.

I put the part of the mtd_speedtest result here for your information.
>From the mtd_speedtest, we can see the NFC will reduce the %50 of cpu load
when writing nand flash. No change when reading.
In the meantime, the speed will be slow about %8.

- commands use to test:
    #insmod /mnt/mtd_speedtest.ko dev=2 &
    #top -n 30 -d 1 | grep speedtest

- test result:

Before the patch:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
  515   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  99% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock write speed is 5768 KiB/s
mtd_speedtest: testing eraseblock read speed
  515   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock read speed is 5932 KiB/s
mtd_speedtest: testing page write speed
  515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page write speed is 5770 KiB/s
mtd_speedtest: testing page read speed
  515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
  515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page read speed is 5910 KiB/s

After the patch:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
mtd_speedtest: testing eraseblock write speed
  509   495 root     D     1164   0%  49% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock write speed is 5370 KiB/s
mtd_speedtest: testing eraseblock read speed
  509   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     R     1164   0%  95% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock read speed is 5715 KiB/s
mtd_speedtest: testing page write speed
  509   495 root     D     1164   0%  48% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page write speed is 5224 KiB/s
mtd_speedtest: testing page read speed
  509   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page read speed is 5641 KiB/s

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
v1 --> v2:
  remove the useless nand commands: NAND_CMD_STATUS_ERRORx, NAND_CMD_DEPLETE1.

 .../devicetree/bindings/mtd/atmel-nand.txt         |    3 +
 drivers/mtd/nand/atmel_nand.c                      |  373 ++++++++++++++++++--
 drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++++
 3 files changed, 454 insertions(+), 28 deletions(-)
 create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index d555421..88e3313 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -6,6 +6,8 @@ Required properties:
 	and hardware ECC controller if available.
 	If the hardware ECC is PMECC, it should contain address and size for
 	PMECC, PMECC Error Location controller and ROM which has lookup tables.
+	If hardware supports Nand Flash Controller, it should contain address and
+	size for NFC command registers, NFC registers and NFC Sram.
 - atmel,nand-addr-offset : offset for the address latch.
 - atmel,nand-cmd-offset : offset for the command latch.
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
@@ -29,6 +31,7 @@ Optional properties:
   sector size 1024.
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- atmel,has-nfc: boolean to enable Nand Flash Controller(NFC).
 
 Examples:
 nand0: nand at 40000000,0 {
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index f747791..48d7ee6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -18,6 +18,9 @@
  *  Add Programmable Multibit ECC support for various AT91 SoC
  *     ? Copyright 2012 ATMEL, Hong Xu
  *
+ *  Add Nand Flash Controller support for SAMA5 SoC
+ *     ? Copyright 2013 ATMEL, Josh Wu (josh.wu at atmel.com)
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -37,9 +40,11 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
+#include <linux/delay.h>
 #include <linux/dmaengine.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
+#include <linux/interrupt.h>
 #include <linux/platform_data/atmel.h>
 #include <linux/pinctrl/consumer.h>
 
@@ -58,6 +63,7 @@ module_param(on_flash_bbt, int, 0);
 	__raw_writel((value), add + ATMEL_ECC_##reg)
 
 #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
+#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
 
 /* oob layout for large page size
  * bad block info is on bytes 0 and 1
@@ -85,6 +91,13 @@ static struct nand_ecclayout atmel_oobinfo_small = {
 	},
 };
 
+struct atmel_nfc {
+	void __iomem		*base_cmd_regs;
+	void __iomem		*hsmc_regs;
+	void __iomem		*sram_bank0;
+	dma_addr_t		sram_bank0_phys;
+};
+
 struct atmel_nand_host {
 	struct nand_chip	nand_chip;
 	struct mtd_info		mtd;
@@ -93,10 +106,15 @@ struct atmel_nand_host {
 	struct atmel_nand_data	board;
 	struct device		*dev;
 	void __iomem		*ecc;
+	int			irq;
 
 	struct completion	comp;
 	struct dma_chan		*dma_chan;
 
+	bool			has_nfc;
+	struct atmel_nfc	nfc;
+	struct completion	comp_nfc;
+
 	bool			has_pmecc;
 	u8			pmecc_corr_cap;
 	u16			pmecc_sector_size;
@@ -1357,6 +1375,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	board->det_pin = of_get_gpio(np, 2);
 
 	host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
+	host->has_nfc = of_property_read_bool(np, "atmel,has-nfc");
 
 	if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
 		return 0;	/* Not using PMECC */
@@ -1469,6 +1488,275 @@ static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
 	return 0;
 }
 
+/* SMC interrupt service routine */
+static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
+{
+	struct atmel_nand_host *host = dev_id;
+	u32 status, mask, pending;
+	irqreturn_t ret = IRQ_NONE;
+
+	status = nfc_readl(host->nfc.hsmc_regs, SR);
+	mask = nfc_readl(host->nfc.hsmc_regs, IMR);
+	pending = status & mask;
+
+	if (pending & ATMEL_HSMC_NFC_XFR_DONE) {
+		complete(&host->comp_nfc);
+		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_XFR_DONE);
+		ret = IRQ_HANDLED;
+	} else if (pending & ATMEL_HSMC_NFC_RB_EDGE) {
+		complete(&host->comp_nfc);
+		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_RB_EDGE);
+		ret = IRQ_HANDLED;
+	} else if (pending & ATMEL_HSMC_NFC_CMD_DONE) {
+		complete(&host->comp_nfc);
+		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_CMD_DONE);
+		ret = IRQ_HANDLED;
+	}
+
+	return ret;
+}
+
+/* NFC(Nand Flash Controller) related functions */
+static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
+{
+	unsigned long timeout;
+	init_completion(&host->comp_nfc);
+
+	/* Enable interrupt that need to wait for */
+	nfc_writel(host->nfc.hsmc_regs, IER, flag);
+
+	timeout = wait_for_completion_timeout(&host->comp_nfc,
+			msecs_to_jiffies(NFC_TIME_OUT_MS));
+	if (timeout)
+		return 0;
+
+	/* Time out to wait for the interrupt */
+	dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
+	return -ETIMEDOUT;
+}
+
+static int nfc_send_command(struct atmel_nand_host *host,
+	unsigned int cmd, unsigned int addr, unsigned char cycle0)
+{
+	unsigned long timeout;
+	dev_dbg(host->dev,
+		"nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
+		cmd, addr, cycle0);
+
+	timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
+	while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc.base_cmd_regs)
+			& NFCADDR_CMD_NFCBUSY) {
+		if (time_after(jiffies, timeout)) {
+			dev_err(host->dev,
+				"Time out to wait CMD_NFCBUSY ready!\n");
+			break;
+		}
+	}
+	nfc_writel(host->nfc.hsmc_regs, CYCLE0, cycle0);
+	nfc_cmd_addr1234_writel(cmd, addr, host->nfc.base_cmd_regs);
+	return nfc_wait_interrupt(host, ATMEL_HSMC_NFC_CMD_DONE);
+}
+
+static int nfc_device_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct atmel_nand_host *host = nand_chip->priv;
+	if (!nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE))
+		return 1;
+	return 0;
+}
+
+static void nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct atmel_nand_host *host = nand_chip->priv;
+
+	if (chip == -1)
+		nfc_writel(host->nfc.hsmc_regs, CTRL, ATMEL_HSMC_NFC_DISABLE);
+	else
+		nfc_writel(host->nfc.hsmc_regs, CTRL, ATMEL_HSMC_NFC_ENABLE);
+}
+
+static int nfc_init(struct platform_device *pdev, struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct atmel_nand_host *host = nand_chip->priv;
+	struct atmel_nfc *nfc = &host->nfc;
+	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
+
+	nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 4);
+	if (!nfc_cmd_regs)
+		return -EINVAL;
+
+	nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 5);
+	if (!nfc_hsmc_regs)
+		return -EINVAL;
+
+	nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 6);
+	if (!nfc_sram)
+		return -EINVAL;
+
+	nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
+	if (IS_ERR(nfc->base_cmd_regs))
+		return PTR_ERR(nfc->base_cmd_regs);
+
+	nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
+	if (IS_ERR(nfc->hsmc_regs))
+		return PTR_ERR(nfc->hsmc_regs);
+
+	nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
+	if (IS_ERR(nfc->sram_bank0))
+		return PTR_ERR(nfc->sram_bank0);
+
+	nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
+
+	dev_info(host->dev, "Using NFC\n");
+	return 0;
+}
+
+static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
+		unsigned int *addr1234, unsigned int *cycle0)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	int acycle = 0;
+	unsigned char addr_bytes[8];
+	int index = 0, bit_shift;
+
+	BUG_ON(addr1234 == NULL || cycle0 == NULL);
+
+	*cycle0 = 0;
+	*addr1234 = 0;
+
+	if (column != -1) {
+		if (chip->options & NAND_BUSWIDTH_16)
+			column >>= 1;
+		addr_bytes[acycle++] = column & 0xff;
+		if (mtd->writesize > 512)
+			addr_bytes[acycle++] = (column >> 8) & 0xff;
+	}
+
+	if (page_addr != -1) {
+		addr_bytes[acycle++] = page_addr & 0xff;
+		addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
+		if (chip->chipsize > (128 << 20))
+			addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
+	}
+
+	if (acycle > 4)
+		*cycle0 = addr_bytes[index++];
+
+	for (bit_shift = 0; index < acycle; bit_shift += 8)
+		*addr1234 += addr_bytes[index++] << bit_shift;
+
+	return acycle << 19;	/* return acycle in cmd register */
+}
+
+static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
+				int column, int page_addr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct atmel_nand_host *host = chip->priv;
+	unsigned long timeout;
+	unsigned int nfc_addr_cmd = 0;
+
+	unsigned int cmd1 = command << 2;
+
+	/* Set default settings: no cmd2, no addr cycle. read from nand */
+	unsigned int cmd2 = 0;
+	unsigned int vcmd2 = 0;
+	int acycle = NFCADDR_CMD_ACYCLE_NONE;
+	int csid = NFCADDR_CMD_CSID_3;
+	int dataen = NFCADDR_CMD_DATADIS;
+	int nfcwr = NFCADDR_CMD_NFCRD;
+	unsigned int addr1234 = 0;
+	unsigned int cycle0 = 0;
+	bool do_addr = true;
+
+	dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
+	     __func__, command, column, page_addr);
+
+	switch (command) {
+	case NAND_CMD_RESET:
+		nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
+		nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
+		udelay(chip->chip_delay);
+
+		nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
+		timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
+		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
+			if (time_after(jiffies, timeout)) {
+				dev_err(host->dev,
+					"Time out to wait status ready!\n");
+				break;
+			}
+		}
+		return;
+	case NAND_CMD_STATUS:
+		do_addr = false;
+		break;
+	case NAND_CMD_PARAM:
+	case NAND_CMD_READID:
+		do_addr = false;
+		acycle = NFCADDR_CMD_ACYCLE_1;
+		if (column != -1)
+			addr1234 = column;
+		break;
+	case NAND_CMD_RNDOUT:
+		cmd2 = NAND_CMD_RNDOUTSTART << 10;
+		vcmd2 = NFCADDR_CMD_VCMD2;
+		break;
+	case NAND_CMD_READ0:
+	case NAND_CMD_READOOB:
+		if (command == NAND_CMD_READOOB) {
+			column += mtd->writesize;
+			command = NAND_CMD_READ0; /* only READ0 is valid */
+			cmd1 = command << 2;
+		}
+
+		cmd2 = NAND_CMD_READSTART << 10;
+		vcmd2 = NFCADDR_CMD_VCMD2;
+		break;
+	/* For prgramming command, the cmd need set to write enable */
+	case NAND_CMD_PAGEPROG:
+	case NAND_CMD_SEQIN:
+	case NAND_CMD_RNDIN:
+		nfcwr = NFCADDR_CMD_NFCWR;
+		break;
+	default:
+		break;
+	}
+
+	if (do_addr)
+		acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
+				&cycle0);
+
+	nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
+	nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
+
+	/*
+	 * Program and erase have their own busy handlers status, sequential
+	 * in, and deplete1 need no delay.
+	 */
+	switch (command) {
+	case NAND_CMD_CACHEDPROG:
+	case NAND_CMD_PAGEPROG:
+	case NAND_CMD_ERASE1:
+	case NAND_CMD_ERASE2:
+	case NAND_CMD_RNDIN:
+	case NAND_CMD_STATUS:
+	case NAND_CMD_RNDOUT:
+	case NAND_CMD_SEQIN:
+	case NAND_CMD_READID:
+		return;
+
+	case NAND_CMD_READ0:
+		/* fall through */
+	default:
+		nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE);
+	}
+}
+
 /*
  * Probe for the NAND device.
  */
@@ -1479,7 +1767,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	struct nand_chip *nand_chip;
 	struct resource *mem;
 	struct mtd_part_parser_data ppdata = {};
-	int res;
+	int res, irq;
 	struct pinctrl *pinctrl;
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1523,7 +1811,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	/* Set address of NAND IO lines */
 	nand_chip->IO_ADDR_R = host->io_base;
 	nand_chip->IO_ADDR_W = host->io_base;
-	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
 
 	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 	if (IS_ERR(pinctrl)) {
@@ -1532,41 +1819,69 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 		goto err_ecc_ioremap;
 	}
 
-	if (gpio_is_valid(host->board.rdy_pin)) {
-		res = gpio_request(host->board.rdy_pin, "nand_rdy");
-		if (res < 0) {
-			dev_err(&pdev->dev,
-				"can't request rdy gpio %d\n",
-				host->board.rdy_pin);
+	if (host->has_nfc) {
+		res = nfc_init(pdev, mtd);
+		if (res)
+			goto err_ecc_ioremap;
+		nand_chip->select_chip = nfc_select_chip;
+		nand_chip->dev_ready = nfc_device_ready;
+		nand_chip->cmdfunc = nfc_nand_command;
+
+		/* Initialize the interrupt for NFC */
+		irq = platform_get_irq(pdev, 0);
+		if (irq < 0) {
+			dev_err(host->dev, "Cannot get HSMC irq!\n");
 			goto err_ecc_ioremap;
 		}
 
-		res = gpio_direction_input(host->board.rdy_pin);
-		if (res < 0) {
-			dev_err(&pdev->dev,
-				"can't request input direction rdy gpio %d\n",
-				host->board.rdy_pin);
+		res = request_irq(irq, hsmc_interrupt, 0, "hsmc", host);
+		if (res) {
+			dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
+				irq);
 			goto err_ecc_ioremap;
 		}
 
-		nand_chip->dev_ready = atmel_nand_device_ready;
-	}
+		host->irq = irq;
+	} else {
+		nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
+
+		if (gpio_is_valid(host->board.rdy_pin)) {
+			res = gpio_request(host->board.rdy_pin, "nand_rdy");
+			if (res < 0) {
+				dev_err(&pdev->dev,
+					"can't request rdy gpio %d\n",
+					host->board.rdy_pin);
+				goto err_ecc_ioremap;
+			}
 
-	if (gpio_is_valid(host->board.enable_pin)) {
-		res = gpio_request(host->board.enable_pin, "nand_enable");
-		if (res < 0) {
-			dev_err(&pdev->dev,
-				"can't request enable gpio %d\n",
-				host->board.enable_pin);
-			goto err_ecc_ioremap;
+			res = gpio_direction_input(host->board.rdy_pin);
+			if (res < 0) {
+				dev_err(&pdev->dev,
+					"can't request input direction rdy gpio %d\n",
+					host->board.rdy_pin);
+				goto err_ecc_ioremap;
+			}
+
+			nand_chip->dev_ready = atmel_nand_device_ready;
 		}
 
-		res = gpio_direction_output(host->board.enable_pin, 1);
-		if (res < 0) {
-			dev_err(&pdev->dev,
-				"can't request output direction enable gpio %d\n",
-				host->board.enable_pin);
-			goto err_ecc_ioremap;
+		if (gpio_is_valid(host->board.enable_pin)) {
+			res = gpio_request(host->board.enable_pin,
+				"nand_enable");
+			if (res < 0) {
+				dev_err(&pdev->dev,
+					"can't request enable gpio %d\n",
+					host->board.enable_pin);
+				goto err_ecc_ioremap;
+			}
+
+			res = gpio_direction_output(host->board.enable_pin, 1);
+			if (res < 0) {
+				dev_err(&pdev->dev,
+					"can't request output direction enable gpio %d\n",
+					host->board.enable_pin);
+				goto err_ecc_ioremap;
+			}
 		}
 	}
 
@@ -1682,6 +1997,8 @@ err_ecc_ioremap:
 	iounmap(host->io_base);
 err_nand_ioremap:
 	kfree(host);
+	if (host->irq)
+		free_irq(host->irq, host);
 	return res;
 }
 
diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
new file mode 100644
index 0000000..ca124de
--- /dev/null
+++ b/drivers/mtd/nand/atmel_nand_nfc.h
@@ -0,0 +1,106 @@
+/*
+ * Atmel Nand Flash Controller (NFC) - System peripherals regsters.
+ * Based on SAMA5D3 datasheet.
+ *
+ * ? Copyright 2013 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef ATMEL_NAND_NFC_H
+#define ATMEL_NAND_NFC_H
+
+/*
+ * HSMC NFC registers
+ */
+#define ATMEL_HSMC_NFC_CFG		0x00	/* NFC Configuration Register */
+#define		ATMEL_HSMC_PAGESIZE_512		(0)
+#define		ATMEL_HSMC_PAGESIZE_1024	(1)
+#define		ATMEL_HSMC_PAGESIZE_2048	(2)
+#define		ATMEL_HSMC_PAGESIZE_4096	(3)
+#define		ATMEL_HSMC_PAGESIZE_8192	(4)
+#define		ATMEL_HSMC_WSPARE		(1 << 8)
+#define		ATMEL_HSMC_RSPARE		(1 << 9)
+#define		ATMEL_HSMC_EDGE_CTRL_RISING	(0 << 12)
+#define		ATMEL_HSMC_EDGE_CTRL_FALLING	(1 << 12)
+#define		ATMEL_HSMC_RBEDGE		(1 << 13)
+#define		ATMEL_HSMC_NFC_DTOCYC		(0xf << 16)
+#define		ATMEL_HSMC_NFC_DTOMUL		(0x7 << 20)
+#define		ATMEL_HSMC_NFC_SPARESIZE	(0x7f << 24)
+
+#define ATMEL_HSMC_NFC_CTRL		0x04	/* NFC Control Register */
+#define		ATMEL_HSMC_NFC_ENABLE		(1 << 0)
+#define		ATMEL_HSMC_NFC_DISABLE		(1 << 1)
+
+#define ATMEL_HSMC_NFC_SR		0x08	/* NFC Status Register */
+#define		ATMEL_HSMC_NFC_STATUS		(1 << 0)
+#define		ATMEL_HSMC_NFC_RB_RISE		(1 << 4)
+#define		ATMEL_HSMC_NFC_RB_FALL		(1 << 5)
+#define		ATMEL_HSMC_NFC_BUSY		(1 << 8)
+#define		ATMEL_HSMC_NFC_WR		(1 << 11)
+#define		ATMEL_HSMC_NFC_CSID		(7 << 12)
+#define		ATMEL_HSMC_NFC_XFR_DONE		(1 << 16)
+#define		ATMEL_HSMC_NFC_CMD_DONE		(1 << 17)
+#define		ATMEL_HSMC_NFC_DTOE		(1 << 20)
+#define		ATMEL_HSMC_NFC_UNDEF		(1 << 21)
+#define		ATMEL_HSMC_NFC_AWB		(1 << 22)
+#define		ATMEL_HSMC_NFC_ASE		(1 << 23)
+#define		ATMEL_HSMC_NFC_RB_EDGE		(1 << 24)
+
+#define ATMEL_HSMC_NFC_IER		0x0c
+#define ATMEL_HSMC_NFC_IDR		0x10
+#define ATMEL_HSMC_NFC_IMR		0x14
+#define ATMEL_HSMC_NFC_CYCLE0		0x18	/* NFC Address Cycle Zero */
+#define		ATMEL_HSMC_NFC_ADDR_CYCLE0	(0xff)
+
+#define ATMEL_HSMC_NFC_BANK		0x1c	/* NFC Bank Register */
+#define		ATMEL_HSMC_NFC_BANK0	(0 << 0)
+#define		ATMEL_HSMC_NFC_BANK1	(1 << 0)
+#define		NFC_SRAM_BANK_OFFSET	(0x1200)
+
+#define nfc_writel(addr, reg, value) \
+	writel((value), (addr) + ATMEL_HSMC_NFC_##reg)
+
+#define nfc_readl(addr, reg) \
+	readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
+
+/*
+ * NFC Address Command definitions
+ */
+#define NFCADDR_CMD_CMD1	(0xff << 2)	/* Command for Cycle 1 */
+#define NFCADDR_CMD_CMD2	(0xff << 10)	/* Command for Cycle 2 */
+#define NFCADDR_CMD_VCMD2	(0x1 << 18)	/* Valid Cycle 2 Command */
+#define NFCADDR_CMD_ACYCLE	(0x7 << 19)	/* Number of Address required */
+#define   NFCADDR_CMD_ACYCLE_NONE	(0x0 << 19)
+#define   NFCADDR_CMD_ACYCLE_1		(0x1 << 19)
+#define   NFCADDR_CMD_ACYCLE_2		(0x2 << 19)
+#define   NFCADDR_CMD_ACYCLE_3		(0x3 << 19)
+#define   NFCADDR_CMD_ACYCLE_4		(0x4 << 19)
+#define   NFCADDR_CMD_ACYCLE_5		(0x5 << 19)
+#define NFCADDR_CMD_CSID	(0x7 << 22)	/* Chip Select Identifier */
+#define   NFCADDR_CMD_CSID_0		(0x0 << 22)
+#define   NFCADDR_CMD_CSID_1		(0x1 << 22)
+#define   NFCADDR_CMD_CSID_2		(0x2 << 22)
+#define   NFCADDR_CMD_CSID_3		(0x3 << 22)
+#define   NFCADDR_CMD_CSID_4		(0x4 << 22)
+#define   NFCADDR_CMD_CSID_5		(0x5 << 22)
+#define   NFCADDR_CMD_CSID_6		(0x6 << 22)
+#define   NFCADDR_CMD_CSID_7		(0x7 << 22)
+#define NFCADDR_CMD_DATAEN	(0x1 << 25)	/* Data Transfer Enable */
+#define NFCADDR_CMD_DATADIS	(0x0 << 25)	/* Data Transfer Disable */
+#define NFCADDR_CMD_NFCRD	(0x0 << 26)	/* NFC Read Enable */
+#define NFCADDR_CMD_NFCWR	(0x1 << 26)	/* NFC Write Enable */
+#define NFCADDR_CMD_NFCBUSY	(0x1 << 27)	/* NFC Busy */
+
+#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \
+	writel((addr1234), (cmd) + nfc_base)
+
+#define nfc_cmd_readl(bitstatus, nfc_base) \
+	readl_relaxed((bitstatus) + nfc_base)
+
+#define NFC_TIME_OUT_MS		100
+
+#endif
-- 
1.7.9.5



From josh.wu at atmel.com  Fri May 17 05:51:47 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 17 May 2013 17:51:47 +0800
Subject: [PATCH v2 3/4] mtd: atmel_nand: enable Nand Flash Controller (NFC)
 read data via sram
In-Reply-To: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368784308-7600-4-git-send-email-josh.wu@atmel.com>

NFC has embedded sram which can use to transfer data. This patch enable reading
nand flash via NFC SRAM. It will minimize the CPU overhead.

This driver has been tested on SAMA5D3X-EK with JFFS2, YAFFS2, UBIFS and
mtd-utils.

Here puts the part of mtd_speedtest (read test) result as following:
Compare with non-NFC mtd_speedtest result, reading will reduce %45 cpu load
with increase %80 speed.

- commands use to test:
  # insmod /mnt/mtd_speedtest.ko dev=2 &
  # top -n 30 -d 1 | grep speedtest

- test result:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
mtd_speedtest: testing eraseblock read speed
  509   495 root     D     1164   0%  28% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  25% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  26% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock read speed is 9403 KiB/s
mtd_speedtest: testing page read speed
  509   495 root     R     1164   0%  31% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  57% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  53% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  71% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page read speed is 9258 KiB/s

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
v1 --> v2:
  use NAND_ECC_READ instead of use new definition pass to pmecc_enable().

 .../devicetree/bindings/mtd/atmel-nand.txt         |    1 +
 drivers/mtd/nand/atmel_nand.c                      |  154 +++++++++++++++++++-
 2 files changed, 151 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 88e3313..40bf3fd 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -32,6 +32,7 @@ Optional properties:
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 - atmel,has-nfc: boolean to enable Nand Flash Controller(NFC).
+- atmel,use-nfc-sram: boolean to enable NFC transfer data via sram.
 
 Examples:
 nand0: nand at 40000000,0 {
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 48d7ee6..c10cd71 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -96,6 +96,9 @@ struct atmel_nfc {
 	void __iomem		*hsmc_regs;
 	void __iomem		*sram_bank0;
 	dma_addr_t		sram_bank0_phys;
+
+	/* Point to the sram bank which include readed data via NFC */
+	void __iomem		*data_in_sram;
 };
 
 struct atmel_nand_host {
@@ -112,6 +115,7 @@ struct atmel_nand_host {
 	struct dma_chan		*dma_chan;
 
 	bool			has_nfc;
+	bool			use_nfc_sram;
 	struct atmel_nfc	nfc;
 	struct completion	comp_nfc;
 
@@ -204,21 +208,43 @@ static int atmel_nand_device_ready(struct mtd_info *mtd)
                 !!host->board.rdy_pin_active_low;
 }
 
+static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
+{
+	int i;
+	u32 *t = trg;
+	const __iomem u32 *s = src;
+
+	for (i = 0; i < (size >> 2); i++)
+		*t++ = readl_relaxed(s++);
+}
+
 /*
  * Minimal-overhead PIO for data access.
  */
 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
 {
 	struct nand_chip	*nand_chip = mtd->priv;
+	struct atmel_nand_host *host = nand_chip->priv;
 
-	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
+	if (host->use_nfc_sram && host->nfc.data_in_sram) {
+		memcpy32_fromio(buf, host->nfc.data_in_sram, len);
+		host->nfc.data_in_sram += len;
+	} else {
+		__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
+	}
 }
 
 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
 {
 	struct nand_chip	*nand_chip = mtd->priv;
+	struct atmel_nand_host *host = nand_chip->priv;
 
-	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
+	if (host->use_nfc_sram && host->nfc.data_in_sram) {
+		memcpy32_fromio(buf, host->nfc.data_in_sram, len);
+		host->nfc.data_in_sram += len;
+	} else {
+		__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
+	}
 }
 
 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
@@ -240,6 +266,40 @@ static void dma_complete_func(void *completion)
 	complete(completion);
 }
 
+static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
+{
+	/* NFC only has two banks. Must be 0 or 1 */
+	if (bank > 1)
+		return -EINVAL;
+
+	if (bank) {
+		/* Only for a 2k-page or lower flash, NFC can handle 2 banks */
+		if (host->mtd.writesize > 2048)
+			return -EINVAL;
+		nfc_writel(host->nfc.hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
+	} else {
+		nfc_writel(host->nfc.hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
+	}
+
+	return 0;
+}
+
+static uint nfc_get_sram_off(struct atmel_nand_host *host)
+{
+	if (nfc_readl(host->nfc.hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
+		return NFC_SRAM_BANK_OFFSET;
+	else
+		return 0;
+}
+
+static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
+{
+	if (nfc_readl(host->nfc.hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
+		return host->nfc.sram_bank0_phys + NFC_SRAM_BANK_OFFSET;
+	else
+		return host->nfc.sram_bank0_phys;
+}
+
 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 			       int is_read)
 {
@@ -253,6 +313,7 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 	void *p = buf;
 	int err = -EIO;
 	enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+	struct atmel_nfc *nfc = &host->nfc;
 
 	if (buf >= high_memory)
 		goto err_buf;
@@ -269,7 +330,12 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 	}
 
 	if (is_read) {
-		dma_src_addr = host->io_phys;
+		if (nfc->data_in_sram)
+			dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
+				- (nfc->sram_bank0 + nfc_get_sram_off(host)));
+		else
+			dma_src_addr = host->io_phys;
+
 		dma_dst_addr = phys_addr;
 	} else {
 		dma_src_addr = phys_addr;
@@ -296,6 +362,10 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 	dma_async_issue_pending(host->dma_chan);
 	wait_for_completion(&host->comp);
 
+	if (is_read && host->nfc.data_in_sram)
+		/* After read data from SRAM, need to increase the position */
+		host->nfc.data_in_sram += len;
+
 	err = 0;
 
 err_dma:
@@ -815,7 +885,8 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	unsigned long end_time;
 	int bitflips = 0;
 
-	pmecc_enable(host, NAND_ECC_READ);
+	if (!host->use_nfc_sram)
+		pmecc_enable(host, NAND_ECC_READ);
 
 	chip->read_buf(mtd, buf, eccsize);
 	chip->read_buf(mtd, oob, mtd->oobsize);
@@ -1376,6 +1447,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 
 	host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
 	host->has_nfc = of_property_read_bool(np, "atmel,has-nfc");
+	host->use_nfc_sram = of_property_read_bool(np, "atmel,use-nfc-sram");
 
 	if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
 		return 0;	/* Not using PMECC */
@@ -1672,6 +1744,7 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 	unsigned int addr1234 = 0;
 	unsigned int cycle0 = 0;
 	bool do_addr = true;
+	host->nfc.data_in_sram = NULL;
 
 	dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
 	     __func__, command, column, page_addr);
@@ -1713,6 +1786,16 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 			command = NAND_CMD_READ0; /* only READ0 is valid */
 			cmd1 = command << 2;
 		}
+		if (host->use_nfc_sram) {
+			/* Enable Data transfer to sram */
+			dataen = NFCADDR_CMD_DATAEN;
+
+			/* Need enable PMECC now, since NFC will transfer
+			 * data in bus after sending nfc read command.
+			 */
+			if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
+				pmecc_enable(host, NAND_ECC_READ);
+		}
 
 		cmd2 = NAND_CMD_READSTART << 10;
 		vcmd2 = NFCADDR_CMD_VCMD2;
@@ -1734,6 +1817,10 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 	nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
 	nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
 
+	if (dataen == NFCADDR_CMD_DATAEN)
+		if (nfc_wait_interrupt(host, ATMEL_HSMC_NFC_XFR_DONE))
+			dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
+
 	/*
 	 * Program and erase have their own busy handlers status, sequential
 	 * in, and deplete1 need no delay.
@@ -1751,12 +1838,62 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 		return;
 
 	case NAND_CMD_READ0:
+		if (dataen == NFCADDR_CMD_DATAEN) {
+			host->nfc.data_in_sram = host->nfc.sram_bank0 +
+				nfc_get_sram_off(host);
+			return;
+		}
 		/* fall through */
 	default:
 		nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE);
 	}
 }
 
+static int nfc_sram_init(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct atmel_nand_host *host = chip->priv;
+	int res = 0;
+
+	/* Initialize the NFC CFG register */
+	unsigned int cfg_nfc = 0;
+
+	/* set page size and oob layout */
+	switch (mtd->writesize) {
+	case 512:
+		cfg_nfc = ATMEL_HSMC_PAGESIZE_512;
+		break;
+	case 1024:
+		cfg_nfc = ATMEL_HSMC_PAGESIZE_1024;
+		break;
+	case 2048:
+		cfg_nfc = ATMEL_HSMC_PAGESIZE_2048;
+		break;
+	case 4096:
+		cfg_nfc = ATMEL_HSMC_PAGESIZE_4096;
+		break;
+	case 8192:
+		cfg_nfc = ATMEL_HSMC_PAGESIZE_8192;
+		break;
+	default:
+		dev_err(host->dev, "Unsupported page size for NFC.\n");
+		res = -ENXIO;
+		return res;
+	}
+
+	cfg_nfc |= ((mtd->oobsize / 4) - 1) << 24;
+	cfg_nfc |= ATMEL_HSMC_RSPARE |
+			ATMEL_HSMC_NFC_DTOCYC | ATMEL_HSMC_NFC_DTOMUL;
+
+	nfc_writel(host->nfc.hsmc_regs, CFG, cfg_nfc);
+
+	nfc_set_sram_bank(host, 0);
+
+	dev_info(host->dev, "Using NFC Sram\n");
+
+	return 0;
+}
+
 /*
  * Probe for the NAND device.
  */
@@ -1962,6 +2099,15 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 			goto err_hw_ecc;
 	}
 
+	/* initialize the nfc configuration register */
+	if (host->has_nfc && host->use_nfc_sram) {
+		res = nfc_sram_init(mtd);
+		if (res) {
+			host->use_nfc_sram = false;
+			dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
+		}
+	}
+
 	/* second phase scan */
 	if (nand_scan_tail(mtd)) {
 		res = -ENXIO;
-- 
1.7.9.5



From josh.wu at atmel.com  Fri May 17 05:51:48 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 17 May 2013 17:51:48 +0800
Subject: [PATCH v2 4/4] mtd: atmel_nand: enable Nand Flash Controller (NFC)
 write via sram
In-Reply-To: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1368784308-7600-5-git-send-email-josh.wu@atmel.com>

This patch enable writing nand flash via NFC SRAM. It will minimize the CPU
overhead. The SRAM write only support ECC_NONE and ECC_HW with PMECC.

This driver has been tested on SAMA5D3X-EK with JFFS2, YAFFS2, UBIFS and
mtd-utils.

Here is part of mtd_speedtest (writing test) result, compare with non-NFC
writing, it reduces %65 cpu load with loss %12 speed.

- commands use to test:
  # insmod /mnt/mtd_speedtest.ko dev=2 &
  # top -n 30 -d 1 | grep speedtest

- test result:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
mtd_speedtest: testing eraseblock write speed
  509   495 root     D     1164   0%   7% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%   8% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     R     1164   0%   5% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock write speed is 5194 KiB/s
mtd_speedtest: testing page write speed
  509   495 root     D     1164   0%  32% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  27% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  25% insmod /mnt/mtd_speedtest.ko dev=2
  509   495 root     D     1164   0%  30% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page write speed is 5024 KiB/s

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
v1 --> v2:
  use NAND_ECC_WRITE instead of use new defined pass to pmecc_enable().
  report a error if use a partial page write via nfc sram.

 drivers/mtd/nand/atmel_nand.c |   94 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 90 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index c10cd71..4490bd6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -99,6 +99,7 @@ struct atmel_nfc {
 
 	/* Point to the sram bank which include readed data via NFC */
 	void __iomem		*data_in_sram;
+	bool			will_write_sram;
 };
 
 struct atmel_nand_host {
@@ -218,6 +219,16 @@ static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 		*t++ = readl_relaxed(s++);
 }
 
+static void memcpy32_toio(void __iomem *trg, const void *src, int size)
+{
+	int i;
+	u32 __iomem *t = trg;
+	const u32 *s = src;
+
+	for (i = 0; i < (size >> 2); i++)
+		writel_relaxed(*s++, t++);
+}
+
 /*
  * Minimal-overhead PIO for data access.
  */
@@ -339,7 +350,11 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 		dma_dst_addr = phys_addr;
 	} else {
 		dma_src_addr = phys_addr;
-		dma_dst_addr = host->io_phys;
+
+		if (host->use_nfc_sram)
+			dma_dst_addr = nfc_sram_phys(host);
+		else
+			dma_dst_addr = host->io_phys;
 	}
 
 	tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
@@ -919,9 +934,10 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 	int i, j;
 	unsigned long end_time;
 
-	pmecc_enable(host, NAND_ECC_WRITE);
-
-	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
+	if (!host->use_nfc_sram) {
+		pmecc_enable(host, NAND_ECC_WRITE);
+		chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
+	}
 
 	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
@@ -1805,6 +1821,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 	case NAND_CMD_SEQIN:
 	case NAND_CMD_RNDIN:
 		nfcwr = NFCADDR_CMD_NFCWR;
+		if (host->nfc.will_write_sram && command == NAND_CMD_SEQIN)
+			dataen = NFCADDR_CMD_DATAEN;
 		break;
 	default:
 		break;
@@ -1849,6 +1867,68 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 	}
 }
 
+static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t offset, int data_len, const uint8_t *buf,
+			int oob_required, int page, int cached, int raw)
+{
+	int cfg, len;
+	int status = 0;
+	struct atmel_nand_host *host = chip->priv;
+	void __iomem *sram = host->nfc.sram_bank0 + nfc_get_sram_off(host);
+
+	/* Subpage write is not supported */
+	if (offset || (data_len < mtd->writesize))
+		return -EINVAL;
+
+	cfg = nfc_readl(host->nfc.hsmc_regs, CFG);
+	len = mtd->writesize;
+
+	if (unlikely(raw)) {
+		len += mtd->oobsize;
+		nfc_writel(host->nfc.hsmc_regs, CFG, cfg | ATMEL_HSMC_WSPARE);
+	} else
+		nfc_writel(host->nfc.hsmc_regs, CFG, cfg & ~ATMEL_HSMC_WSPARE);
+
+	/* Copy page data to sram that will write to nand via NFC */
+	if (use_dma) {
+		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
+			/* Fall back to use cpu copy */
+			memcpy32_toio(sram, buf, len);
+	} else {
+		memcpy32_toio(sram, buf, len);
+	}
+
+	if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
+		/*
+		 * When use NFC sram, need set up PMECC before send
+		 * NAND_CMD_SEQIN command. Since when the nand command
+		 * is sent, nfc will do transfer from sram and nand.
+		 */
+		pmecc_enable(host, NAND_ECC_WRITE);
+
+	host->nfc.will_write_sram = true;
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+	host->nfc.will_write_sram = false;
+
+	if (likely(!raw))
+		/* Need to write ecc into oob */
+		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+
+	if (status < 0)
+		return status;
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	if ((status & NAND_STATUS_FAIL) && (chip->errstat))
+		status = chip->errstat(mtd, chip, FL_WRITING, status, page);
+
+	if (status & NAND_STATUS_FAIL)
+		return -EIO;
+
+	return 0;
+}
+
 static int nfc_sram_init(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
@@ -1887,10 +1967,16 @@ static int nfc_sram_init(struct mtd_info *mtd)
 
 	nfc_writel(host->nfc.hsmc_regs, CFG, cfg_nfc);
 
+	host->nfc.will_write_sram = false;
 	nfc_set_sram_bank(host, 0);
 
 	dev_info(host->dev, "Using NFC Sram\n");
 
+	/* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
+	if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
+			chip->ecc.mode == NAND_ECC_NONE)
+		chip->write_page = nfc_sram_write_page;
+
 	return 0;
 }
 
-- 
1.7.9.5



From B45370 at freescale.com  Fri May 17 05:56:22 2013
From: B45370 at freescale.com (Sharma Bhupesh-B45370)
Date: Fri, 17 May 2013 09:56:22 +0000
Subject: ARM Cortex-A7 support in Linux
Message-ID: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>

Hi Catalin, list

I am trying to locate support for Cortex-A7 soc (in Linux) and it's primary features like:
- SMMU 400 (Virtualization)
- CCI 400 
- LPAE
- GIC 400

We wish to use this core in one of our SoCs and will like to reuse most of the code.
I can see some support added for:
- Cortex-A7 dts by Pawel for Versatile board
	http://linux-arm.org/git?p=arm-dts.git;a=commitdiff;h=81195261a984e8c734f319eda80f86ba82b37d27

- LPAE support by Catalin
	http://lxr.linux.no/linux+v3.9.2/arch/arm/mm/Kconfig#L589

- CCI 400 RFC patches from Lorenzo
	https://patchwork.kernel.org/patch/2508121/

- Basic dts support for GIC virtualization support is already present here:
	http://lxr.linux.no/linux+v3.9.2/Documentation/devicetree/bindings/arm/gic.txt#L64

But I am not sure about the following:
- Does the current GIC driver support GIC-400 features as well?

- I don't see many of these features supported in u-boot. Any idea if any work is going on for the same? 

Thanks for your help.
Regards,
Bhupesh



From josh.wu at atmel.com  Fri May 17 05:58:48 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 17 May 2013 17:58:48 +0800
Subject: [PATCH 0/4] mtd: atmel_nand: enable Nand Flash Controller (NFC)
 support
In-Reply-To: <1368696748.15764.184.camel@sauron.fi.intel.com>
References: <1366712997-17639-1-git-send-email-josh.wu@atmel.com>
 <1368696748.15764.184.camel@sauron.fi.intel.com>
Message-ID: <5195FF58.4070909@atmel.com>

Hi, Artem

On 5/16/2013 5:32 PM, Artem Bityutskiy wrote:
> On Tue, 2013-04-23 at 18:29 +0800, Josh Wu wrote:
>> This patch series enable NFC support for SAMA5 soc. It can send command,
>> address cycles automaticly. Also when enable NFC sram, NFC will transfer
>> data to sram. Which can save lots of cpu time.
>>
>> Josh Wu (4):
>>    mtd: atmel_nand: replace pmecc enable code with one function.
>>    mtd: atmel_nand: add Nand Flash Controller (NFC) support
>>    mtd: atmel_nand: enable Nand Flash Controller (NFC) read data
>>      via sram
>>    mtd: atmel_nand: enable Nand Flash Controller (NFC) write via
>>      sram
> Please, re-base against the latest l2-mtd.git tree. The patches do not
> compile:

I've sent out the v2 version which is rebased on the latest l2-mtd.git 
tree. It fixed the compiler error and imcompatible parameters of the 
write_page().
Thanks for point out.

Best Regards,
Josh Wu

> --------------------------------------------------------------------------------
> Failed to build the following commit for configuration "arm-at91cap9_defconfig" (architecture arm)":
>
> 2bd4bff mtd: atmel_nand: enable Nand Flash Controller (NFC) write via sram
>
> drivers/mtd/nand/atmel_nand.c: In function 'nfc_nand_command':
> drivers/mtd/nand/atmel_nand.c:1848: error: 'NAND_CMD_DEPLETE1' undeclared (first use in this function)
> drivers/mtd/nand/atmel_nand.c:1848: error: (Each undeclared identifier is reported only once
> drivers/mtd/nand/atmel_nand.c:1848: error: for each function it appears in.)
> drivers/mtd/nand/atmel_nand.c:1854: error: 'NAND_CMD_STATUS_ERROR' undeclared (first use in this function)
> drivers/mtd/nand/atmel_nand.c:1855: error: 'NAND_CMD_STATUS_ERROR0' undeclared (first use in this function)
> drivers/mtd/nand/atmel_nand.c:1856: error: 'NAND_CMD_STATUS_ERROR1' undeclared (first use in this function)
> drivers/mtd/nand/atmel_nand.c:1857: error: 'NAND_CMD_STATUS_ERROR2' undeclared (first use in this function)
> drivers/mtd/nand/atmel_nand.c:1858: error: 'NAND_CMD_STATUS_ERROR3' undeclared (first use in this function)
> drivers/mtd/nand/atmel_nand.c: In function 'nfc_sram_init':
> drivers/mtd/nand/atmel_nand.c:1979: warning: assignment from incompatible pointer type
> make[4]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
>



From linux at arm.linux.org.uk  Fri May 17 06:00:16 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 11:00:16 +0100
Subject: [PATCH 9/9] I2C: mv64xxx: fix race between FSM/interrupt and
 process context
In-Reply-To: <20130517095149.GI17056@katana>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4xE-0004KB-2T@rmk-PC.arm.linux.org.uk> <20130517095149.GI17056@katana>
Message-ID: <20130517100016.GB18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 11:51:51AM +0200, Wolfram Sang wrote:
> >  {
> >  	switch(drv_data->action) {
> >  	case MV64XXX_I2C_ACTION_SEND_RESTART:
> > +		/* We should only get here if we have further messages */
> > +		BUG_ON(drv_data->num_msgs == 0);
> > +
> 
> ...
> 
> > @@ -453,16 +463,20 @@ static int
> >  mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
> >  {
> >  	struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
> > -	int	i, rc;
> > +	int rc, ret = num;
> >  
> > -	for (i = 0; i < num; i++) {
> > -		rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
> > -						i == 0, i + 1 == num);
> > -		if (rc < 0)
> > -			return rc;
> > -	}
> > +	BUG_ON(drv_data->msgs != NULL);
> 
> Can't we handle this more gracefully than to halt the kernel? Like
> WARN_ON and resetting the controller or disabling the bus or...

Well, the latter really is something which should never ever happen,
and if it does happen it can only really be because something's
screwed up in the locking in the I2C layer.

The former is more probable, and I thought about that, but I don't
have any good alternative solution.  Given the problems I've seen,
I don't think resetting the controller is really an option, because
that'll likely cause the bus to lock (that's the original problem
which I'm trying to solve in this patch.)  The thing really does
have to work according to the I2C protocol otherwise stuff goes
irrecoverably wrong to the point of needing an entire system reset.


From ming.lei at canonical.com  Fri May 17 06:07:37 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 17 May 2013 18:07:37 +0800
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <20130517095423.GD23112@mudshark.cambridge.arm.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
 <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
 <20130517093616.GC23112@mudshark.cambridge.arm.com>
 <CACVXFVP56EJb0BZ+w6hVAukQ-mN0e0Jn_GLw3XqXQqMwVGfNdA@mail.gmail.com>
 <20130517095423.GD23112@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVPJyKrOBk+JjsfCi+aQ8snQ7PsEJVuOnuTkrWBYEnvDtA@mail.gmail.com>

On Fri, May 17, 2013 at 5:54 PM, Will Deacon <will.deacon at arm.com> wrote:
> On Fri, May 17, 2013 at 10:48:23AM +0100, Ming Lei wrote:
>> On Fri, May 17, 2013 at 5:36 PM, Will Deacon <will.deacon at arm.com> wrote:
>> >
>> > It's probably easier if you choose a workload, otherwise it's difficult to
>> > see what is `correct' and what is broken. For example, your broken output
>> > seems to be in the smsc95xx driver, so assumedly there's a bunch of
>> > networking going on whereas your other output is in cpuidle_enter_state.
>>
>> If all modules are removed, the result will become OK. And if I only insert one
>> module, the top sample will fall inside the only module, but I am sure
>> nothing is working on the symbols of the module.
>
> Can you check your dmesg please? I suppose the smsc95xx driver might be
> screaming about something and somehow the changes to the reg printing have
> made it get stuck.

If I insert only one useless module(such as, spi-altera.ko) on Pandaboard,
the top sample will fall inside the module of spi-altera, so it is nothing to
do with smsc95xx, also you can see the sampled top IP is an invalid address.

>
>> >
>> > We need an apples-for-apples comparison if you think there's a bug in the
>> > kernel. Can you try profiling hackbench or something?
>> >
>> >> Or could anyone else try to verify the problem on their own environment?
>> >
>> > How are you running perf top?
>>
>> sudo perf top
>
> ... and did hackbench make any difference (i.e. is the profile more stable)?

When hackbench is started, there is no much change compared with idle,
only another sample( 2.49%  [unknown]            [.] 0xb6f618a0) comes and
becomes top 2.

Thanks,
--
Ming Lei


From hvaibhav at ti.com  Fri May 17 06:13:41 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 17 May 2013 15:43:41 +0530
Subject: [PATCH-V2] ARM: OMAP3+: am33xx id: Add new am33xx specific function
 to check dev_feature
Message-ID: <1368785621-31591-1-git-send-email-hvaibhav@ti.com>

Layout of DEV_FEATURE register (offset = 0x604) is different
between TI81xx and AM33xx device, so create separate function
which will check for features available on specific AM33xx SoC
and set the flags accordingly.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Reviewed-by: Kevin Hilman <khilman at linaro.org>
---
Changes from V1:
	- Removed SHIFT value, as it never gets used in code
	- Used BIT() macro for MASK definition

 arch/arm/mach-omap2/control.h |    4 ++++
 arch/arm/mach-omap2/id.c      |   13 +++++++++++++
 arch/arm/mach-omap2/io.c      |    2 +-
 arch/arm/mach-omap2/soc.h     |    1 +
 4 files changed, 19 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c3281..174eb41 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,10 @@
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)

+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE		0x604
+#define AM33XX_SGX_MASK			BIT(29)
+
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS	0x044c

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41..44be835 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -302,6 +302,19 @@ void __init ti81xx_check_features(void)
 	omap3_cpuinfo();
 }

+void __init am33xx_check_features(void)
+{
+	u32 status;
+
+	omap_features = OMAP3_HAS_NEON;
+
+	status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+	if (status & AM33XX_SGX_MASK)
+		omap_features |= OMAP3_HAS_SGX;
+
+	omap3_cpuinfo();
+}
+
 void __init omap3xxx_check_revision(void)
 {
 	const char *cpu_rev;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..06a8946 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -576,7 +576,7 @@ void __init am33xx_init_early(void)
 	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
 	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
 	omap3xxx_check_revision();
-	ti81xx_check_features();
+	am33xx_check_features();
 	am33xx_voltagedomains_init();
 	am33xx_powerdomains_init();
 	am33xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16..fd4507b 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -424,6 +424,7 @@ void omap4xxx_check_revision(void);
 void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
+void am33xx_check_features(void);
 void omap4xxx_check_features(void);

 /*
--
1.7.0.4



From hvaibhav at ti.com  Fri May 17 06:15:09 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 May 2013 10:15:09 +0000
Subject: [PATCH] ARM: OMAP3+: am33xx id: Add new am33xx specific
 function to check dev_feature
In-Reply-To: <87bo8e1r8o.fsf@linaro.org>
References: <1367996313-6676-1-git-send-email-hvaibhav@ti.com>
 <87bo8e1r8o.fsf@linaro.org>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8BF4F@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Kevin Hilman [mailto:khilman at linaro.org]
> Sent: Tuesday, May 14, 2013 3:23 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH] ARM: OMAP3+: am33xx id: Add new am33xx specific
> function to check dev_feature
> 
> Vaibhav Hiremath <hvaibhav at ti.com> writes:
> 
> > Layout of DEV_FEATURE register (offset = 0x604) is different
> > between TI81xx and AM33xx device, so create separate function
> > which will check for features available on specific AM33xx SoC
> > and set the flags accordingly.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> 
> Minor nit below, otherwise...
> 
> Reviewed-by: Kevin Hilman <khilman at linaro.org>
> 
> > ---
> >  arch/arm/mach-omap2/control.h |    5 +++++
> >  arch/arm/mach-omap2/id.c      |   13 +++++++++++++
> >  arch/arm/mach-omap2/io.c      |    2 +-
> >  arch/arm/mach-omap2/soc.h     |    1 +
> >  4 files changed, 20 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-
> omap2/control.h
> > index e6c3281..4acdfc5 100644
> > --- a/arch/arm/mach-omap2/control.h
> > +++ b/arch/arm/mach-omap2/control.h
> > @@ -358,6 +358,11 @@
> >  #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
> >  #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)
> >
> > +/* DEV Feature register to identify AM33XX features */
> > +#define AM33XX_DEV_FEATURE		0x604
> > +#define AM33XX_SGX_SHIFT		29
> 
> You don't need the shift value anywhere in the code, so...
> 
> > +#define AM33XX_SGX_MASK			(1 << AM33XX_SGX_SHIFT)
> 
> #define AM33XX_SGX_MASK		BIT(29)
> 
> instead?
> 
> Otherwise, rest of patch looks fine.
> 
Thanks for the review Kevin.
I just sent out V2 version of the patch with your reviewed-by
With changes you mentioned.

Thanks,
Vaibhav


From josephl at nvidia.com  Fri May 17 06:15:59 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 17 May 2013 18:15:59 +0800
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <51952344.1090003@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <51941C58.9060002@wwwdotorg.org>
 <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>
 <51952344.1090003@wwwdotorg.org>
Message-ID: <1368785759.3174.8.camel@jlo-ubuntu-64.nvidia.com>

On Fri, 2013-05-17 at 02:19 +0800, Stephen Warren wrote:
> On 05/16/2013 03:53 AM, Joseph Lo wrote:
> > On Thu, 2013-05-16 at 07:38 +0800, Stephen Warren wrote:
> >> On 05/15/2013 04:27 AM, Joseph Lo wrote:
> >>> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> >>> as CPU core and a enhanced flow controller for CPU power control. So
> >>> we need to skip some code that was for Contex-A9 and some other support
> >>> code that was for other Tegra SoC chips. Then adding the proper power up
> >>> and hot plug control for Tegra114.
> >>
> >> This series mostly works OK, but I see one problem: I can't hotunplug
> >> CPU0, which the commit descriptions and code changes imply I should be
> >> able to do:
> >>
> >> root at localhost:~# echo 0 > /sys/devices/system/cpu/cpu0/online
> >> -bash: echo: write error: Operation not permitted
> > 
> > I want to provide this function originally. But I found the
> > tegra_cpu_disable() was removed recently. It was replaced by the common
> > cpu_disable() function that didn't allow CPU0 to be un-plugged.
> 
> Is there a specific reason for that; is there some problem in the core
> ARM code that implies CPU0 should never be disabled?
> 
I think the CPU0 is the boot CPU for most of the case. We always need at
least one CPU online. That assumes to be the boot CPU.

> > But I had verified the CPU0 is OK to be un-plugged on the older
> > linux-next branch that tegra_cpu_disable() watn't removed yet.
> > 
> > Do you want me to add them back to support this function for Tegra114?
> 
> If there is a problem removing CPU0 in the core code, the functionality
> of this series is OK, although it's probably worth removing the parts
> that attempt to make CPU0 hot-unpluggable to reduce the diff size.
> 
> If there's no problem removing CPU0, it'd be good to make it work,
> although that could be done in followon patches.

OK. Thanks.




From linux at arm.linux.org.uk  Fri May 17 06:23:45 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 11:23:45 +0100
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <51941C58.9060002@wwwdotorg.org>
 <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <20130517102345.GC18614@n2100.arm.linux.org.uk>

On Thu, May 16, 2013 at 05:53:39PM +0800, Joseph Lo wrote:
> On Thu, 2013-05-16 at 07:38 +0800, Stephen Warren wrote:
> > This series mostly works OK, but I see one problem: I can't hotunplug
> > CPU0, which the commit descriptions and code changes imply I should be
> > able to do:
> > 
> > root at localhost:~# echo 0 > /sys/devices/system/cpu/cpu0/online
> > -bash: echo: write error: Operation not permitted
> 
> I want to provide this function originally. But I found the
> tegra_cpu_disable() was removed recently. It was replaced by the common
> cpu_disable() function that didn't allow CPU0 to be un-plugged.

It got removed for the simple reason that the implementation of that
function was exactly the same as the default path in cpu_disable().
If you have a need to do something else other than the default, then
provide the function (and *only* provide it if you need to do something
different.)

However, if the default suffices, do not provide extra code even if you
later intend to change the function.  Only add the function when you
need to do something else.

I see too much of this "I'll add this function just becase, and maybe
I'll change it later" crap getting into the kernel; this needs to stop.
Things like providing an empty function for every single method in a
struct even through the behaviour would be to do nothing had that
function not been provided.  So whenever I see this, I remove the
offending functions if I'm touching that code.


From linux at arm.linux.org.uk  Fri May 17 06:27:00 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 11:27:00 +0100
Subject: [PATCH 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <51952344.1090003@wwwdotorg.org>
References: <1368613644-11863-1-git-send-email-josephl@nvidia.com>
 <51941C58.9060002@wwwdotorg.org>
 <1368698019.7403.10.camel@jlo-ubuntu-64.nvidia.com>
 <51952344.1090003@wwwdotorg.org>
Message-ID: <20130517102700.GD18614@n2100.arm.linux.org.uk>

On Thu, May 16, 2013 at 12:19:48PM -0600, Stephen Warren wrote:
> Is there a specific reason for that; is there some problem in the core
> ARM code that implies CPU0 should never be disabled?

No.  This is the code I removed:

-int tegra_cpu_disable(unsigned int cpu)
-{
-       /*
-        * we don't allow CPU 0 to be shutdown (it is still too special
-        * e.g. clock tick interrupts)
-        */
-       return cpu == 0 ? -EPERM : 0;
-}

This gets called from here:

static int platform_cpu_disable(unsigned int cpu)
{
        if (smp_ops.cpu_disable)
                return smp_ops.cpu_disable(cpu);

        /*
         * By default, allow disabling all CPUs except the first one,
         * since this is special on a lot of platforms, e.g. because
         * of clock tick interrupts.
         */
        return cpu == 0 ? -EPERM : 0;
}

Notice the useless utterly nature of tegra_cpu_disable() given that it's
doing _precisely_ the same thing as the common code.  It might as well
not even exist - and it doesn't for that very reason.  Never provide
implementations for methods which are copies of the default action if
no method is provided.


From hvaibhav at ti.com  Fri May 17 06:30:54 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 May 2013 10:30:54 +0000
Subject: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
 clkdiv32k_ick clock
In-Reply-To: <alpine.DEB.2.00.1303271744510.17356@utopia.booyaka.com>
References: <1364378666-23641-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1303271744510.17356@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8BFA7@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Wednesday, March 27, 2013 11:15 PM
> To: Tony Lindgren; Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Nayak, Rajendra
> Subject: Re: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
> clkdiv32k_ick clock
> 
> On Wed, 27 Mar 2013, Vaibhav Hiremath wrote:
> 
> > It is required to enable respective clock-domain before
> > enabling any clock/module inside that clock-domain.
> >
> > During common-clock migration, .clkdm_name field got missed
> > for "clkdiv32k_ick" clock, which leaves "clk_24mhz_clkdm"
> > unused; so it will be disabled even if childs of this clock-domain
> > is enabled, which keeps child modules in idle mode.
> >
> > This fixes the kernel crash observed on AM335xEVM-SK platform,
> > where clkdiv32_ick clock is being used as a gpio debounce clock
> > and since clkdiv32k_ick is in idle mode it leads to below crash -
> >
> > Crash Log:
> > ==========
> > [    2.598347] Unhandled fault: external abort on non-linefetch
> (0x1028) at
> > 0xfa1ac150
> > [    2.606434] Internal error: : 1028 [#1] SMP ARM
> > [    2.611207] Modules linked in:
> > [    2.614449] CPU: 0    Not tainted  (3.8.4-01382-g1f449cd-dirty #4)
> > [    2.620973] PC is at _set_gpio_debounce+0x60/0x104
> > [    2.626025] LR is at clk_enable+0x30/0x3c
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Paul Walmsley <paul at pwsan.com>
> > Cc: Rajendra Nayak <rnayak at ti.com>
> 
> Acked-by: Paul Walmsley <paul at pwsan.com>
> 
> Tony, if it isn't too late, could this one be added to your 3.9-rc
> fixes
> series?
> 
> 

Looks like we missed this so far.

Tony, can you merge this patch for v3.10-rc ?

Thanks,
Vaibhav


From marc.zyngier at arm.com  Fri May 17 06:47:45 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 17 May 2013 12:47:45 +0200
Subject: ARM Cortex-A7 support in Linux
In-Reply-To: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
References: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
Message-ID: <f6c9d2b0d52d63efa95f780b172690ef@localhost>

On Fri, 17 May 2013 09:56:22 +0000, Sharma Bhupesh-B45370
<B45370 at freescale.com> wrote:

> But I am not sure about the following:
> - Does the current GIC driver support GIC-400 features as well?

It depends which feature you're after. Linux supports the GIC
virtualization extensions with KVM, for example. But we don't make any use
of other things like priorities, split deactivation/priority drop...

         M.
-- 
Fast, cheap, reliable. Pick two.


From p.zabel at pengutronix.de  Fri May 17 06:50:39 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 17 May 2013 12:50:39 +0200
Subject: [PATCH 0/3] staging: fix parallel display regressions
In-Reply-To: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368787839.4011.4.camel@pizza.hi.pengutronix.de>

Hi Markus,

Am Freitag, den 17.05.2013, 11:19 +0200 schrieb Markus Niebel:
> From: Markus Niebel <Markus.Niebel at tqs.de>
> 
> Support for VGA via TVE on iMX53 causes  regression, which prevents
> parallel display from working. This series brings the parallel display
> functionality back.
> 
> Tested on a modified v3.9 with TQMa53 module and compile tested with
> v3.10-rc1.
> 
> Markus Niebel (3):
>   staging: drm/imx: set correct sync pins for parallel display
>   staging: drm/imx: fix spelling error for vsync flag config
>   staging: drm/imx: revert vsync_cnt for di->id 1
> 
>  drivers/staging/imx-drm/ipu-v3/ipu-di.c    |   13 +++++++++----
>  drivers/staging/imx-drm/parallel-display.c |    4 ++--
>  2 files changed, 11 insertions(+), 6 deletions(-)

thank you for posting the patches! I can confirm that they fix the
issues of incorrect signal generation on IPU display interface 1,
caused by my TVE patch series.

Tested-by: Philipp Zabel <p.zabel at pengutronix.de>

regards
Philipp



From p.zabel at pengutronix.de  Fri May 17 06:50:55 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 17 May 2013 12:50:55 +0200
Subject: [PATCH 1/3] staging: drm/imx: set correct sync pins for
 parallel display
In-Reply-To: <1368782393-9660-2-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
 <1368782393-9660-2-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368787855.4011.6.camel@pizza.hi.pengutronix.de>

Am Freitag, den 17.05.2013, 11:19 +0200 schrieb Markus Niebel:
> From: Markus Niebel <Markus.Niebel at tqs.de>
> 
> partial fix of changes from
> "staging: drm/imx: Add support for VGA via TVE on i.MX53"
> 
> Have to call imx_drm_crtc_panel_format_pins with the correct pins instead of (0, 0)
> This enables configuration of correct waveforms for vsync / hsync
> 
> TODO: configure pins via device tree
> 
> Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
> ---
>  drivers/staging/imx-drm/parallel-display.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
> index e7fba62..e49a906 100644
> --- a/drivers/staging/imx-drm/parallel-display.c
> +++ b/drivers/staging/imx-drm/parallel-display.c
> @@ -114,8 +114,8 @@ static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
>  {
>  	struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
>  
> -	imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_NONE,
> -			imxpd->interface_pix_fmt);
> +	imx_drm_crtc_panel_format_pins(encoder->crtc, DRM_MODE_ENCODER_NONE,
> +			imxpd->interface_pix_fmt, 2, 3);
>  }
>  
>  static void imx_pd_encoder_commit(struct drm_encoder *encoder)

Rather than putting this here, as long as it is not configurable from
device tree, I'd prefer to use this patch instead:

--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -144,7 +144,7 @@ int imx_drm_crtc_panel_format(struct drm_crtc *crtc, u32 encoder_type,
                u32 interface_pix_fmt)
 {
        return imx_drm_crtc_panel_format_pins(crtc, encoder_type,
-                                             interface_pix_fmt, 0, 0);
+                                             interface_pix_fmt, 2, 3);
 }
 EXPORT_SYMBOL_GPL(imx_drm_crtc_panel_format);
 
Because this will fix the same issue also for LDB, HDMI, and MIPI/DSI drivers.

regards
Philipp



From p.zabel at pengutronix.de  Fri May 17 06:51:17 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 17 May 2013 12:51:17 +0200
Subject: [PATCH 2/3] staging: drm/imx: fix spelling error for vsync flag
 config
In-Reply-To: <1368782393-9660-3-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
 <1368782393-9660-3-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368787877.4011.7.camel@pizza.hi.pengutronix.de>

Am Freitag, den 17.05.2013, 11:19 +0200 schrieb Markus Niebel:
> From: Markus Niebel <Markus.Niebel at tqs.de>
> 
> partial fix of changes from
> "staging: drm/imx: Add support for VGA via TVE on i.MX53"
> 
> Have to check for vsync_pin instead of hsync_pin to set Vsync_pol.
> 
> Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
> ---
>  drivers/staging/imx-drm/ipu-v3/ipu-di.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
> index 19d777e..e7b9c98 100644
> --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
> +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
> @@ -614,11 +614,11 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
>  				di_gen |= DI_GEN_POLARITY_7;
>  		}
>  		if (sig->Vsync_pol) {
> -			if (sig->hsync_pin == 3)
> +			if (sig->vsync_pin == 3)
>  				di_gen |= DI_GEN_POLARITY_3;
> -			else if (sig->hsync_pin == 6)
> +			else if (sig->vsync_pin == 6)
>  				di_gen |= DI_GEN_POLARITY_6;
> -			else if (sig->hsync_pin == 8)
> +			else if (sig->vsync_pin == 8)
>  				di_gen |= DI_GEN_POLARITY_8;
>  		}
>  	}

Acked-by: Philipp Zabel <p.zabel at pengutronix.de>



From p.zabel at pengutronix.de  Fri May 17 06:52:12 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 17 May 2013 12:52:12 +0200
Subject: [PATCH 3/3] staging: drm/imx: revert vsync_cnt for di->id 1
In-Reply-To: <1368782393-9660-4-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
 <1368782393-9660-4-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <1368787932.4011.8.camel@pizza.hi.pengutronix.de>

Am Freitag, den 17.05.2013, 11:19 +0200 schrieb Markus Niebel:
> From: Markus Niebel <Markus.Niebel at tqs.de>
> 
> partial fix of changes from
> "staging: drm/imx: Add support for VGA via TVE on i.MX53"
> 
> parallel display support / DVI needs the original setting to work
> 
> Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
> ---
>  drivers/staging/imx-drm/ipu-v3/ipu-di.c |    7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
> index e7b9c98..0b6806e 100644
> --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
> +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
> @@ -603,7 +603,12 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
>  
>  		vsync_cnt = 3;
>  		if (di->id == 1)
> -			vsync_cnt = 6;
> +			/*
> +			 * TODO: change only for TVEv2, parallel display
> +			 * uses pin 2 / 3
> +			 */
> +			if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
> +				vsync_cnt = 6;
>  
>  		if (sig->Hsync_pol) {
>  			if (sig->hsync_pin == 2)

Acked-by: Philipp Zabel <p.zabel at pengutronix.de>

regards
Philipp



From linux at arm.linux.org.uk  Fri May 17 06:55:00 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 11:55:00 +0100
Subject: ARM Cortex-A7 support in Linux
In-Reply-To: <f6c9d2b0d52d63efa95f780b172690ef@localhost>
References: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
 <f6c9d2b0d52d63efa95f780b172690ef@localhost>
Message-ID: <20130517105500.GE18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
> It depends which feature you're after. Linux supports the GIC
> virtualization extensions with KVM, for example. But we don't make any use
> of other things like priorities, split deactivation/priority drop...

Not that we could make use of priorities anymore as all interrupt handlers
are now run with IRQs disabled; an IRQ handler can't be interrupted by a
higher priority IRQ coming in.

Part of the solution to that is to go back to the original philosophy of
IRQ handling in Linux - do the least possible amount of work in the IRQ
and move the heavier stuff off into soft-IRQ context.  Unfortunately,
many drivers are no longer written like that, and just do a great amount
of time consuming work in their IRQ handler.


From B35083 at freescale.com  Fri May 17 07:01:08 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Fri, 17 May 2013 11:01:08 +0000
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
In-Reply-To: <alpine.LFD.2.02.1305161214570.1388@ionos>
References: <1368684924-1560-1-git-send-email-b35083@freescale.com>
 <alpine.LFD.2.02.1305161214570.1388@ionos>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851C9FBB@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Thomas Gleixner [mailto:tglx at linutronix.de]
>Sent: Thursday, May 16, 2013 10:05 PM
>To: Lu Jingchang-B35083
>Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
>john.stultz at linaro.org; shawn.guo at linaro.org; s.hauer at pengutronix.de
>Subject: Re: [PATCH v3] clocksource: add MVF600 pit timer support
>
>> +static int pit_set_next_event(unsigned long delta,
>> +				struct clock_event_device *unused) {
>> +	pit_timer_disable();
>> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
>> +	pit_irq_acknowledge();
>> +	pit_timer_enable();
>
>It would be much more interesting to comment, why you need to acknowlegde
>the timer here.
[Lu Jingchang-B35083] 
 The pit is a period load and count timer, ack here is to make sure the int flag is clear,
I will check if the ack here is needed and remove the redundant code. Thanks!
>
>> +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) {
>> +	struct clock_event_device *evt = &clockevent_pit;
>> +
>> +	pit_irq_acknowledge();
>> +
>> +	if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT)
>> +		pit_timer_disable();
>
>So in oneshot mode you do:
>
>     pit_irq_ack()
>     pit_timer_disable()
>     ....
>	set_next_event()
>  	  pit_timer_disable()
>	  write_new_value()
>	  pit_irq_ack()
>	  pit_timer_enable()
>
>Not really the most efficient way in the interrupt fast path, right?
[Lu Jingchang-B35083] 
 The pit hardware doesn't support oneshot timer. So for oneshot mode event,
software need to disable and enable the timer each time.
 The timers generate interrupt at periodic intervals, when enabled. The timers load the start
values as specified in their LDVAL registers, count down to 0, generate an INT and then reload the respective
start value again. Each time a timer reaches 0, it will set the interrupt flag.
I will remove the redundant irq_ack.
Thanks!
>
>> +	evt->event_handler(evt);
>> +
>> +	clockevents_config_and_register(&clockevent_pit, c, 0x100,
>> +0xffffff00);
>
>0x100 and 0xffffff00 ?? Random numbers pulled out of what?
[Lu Jingchang-B35083] 
It seems too small delta is not reasonable, and the max delta value is not sensible.
So refer to some other platforms, I set it to 0x100-0xffffff00. I'm OK to set it to 0x2~0xffffffff.
Thanks!
>
>> +
>> +	timer_base = of_iomap(np, 0);
>> +	WARN_ON(!timer_base);
>
>Great, timer_base is NULL and you just emit a warning and then proceed? So
>instead of either bailing out or crashing the machine right away you let
>it randomly die with the first access.
[Lu Jingchang-B35083] 
I will use BUG_ON() instead of WARN_ON(). Thanks!
>
>> +
>> +	clk_prepare_enable(pit_clk);
>
>And while you're worried about the core code sending you random crap, you
>assume that this call always succeeds.
[Lu Jingchang-B35083] 
I will check the return value for that call. Thanks!

>> +	__raw_writel(0, clksrc_base + PITTCTRL);
>> +	__raw_writel(0xffffffff, clksrc_base + PITLDVAL);
>
>And of this? Why isn't the setup done in the relevant init functions?
[Lu Jingchang-B35083] 
I will move these to relevant init functions. Thanks!





From broonie at kernel.org  Fri May 17 07:02:41 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 17 May 2013 12:02:41 +0100
Subject: [PATCH RFC] clk: Introduce userspace clock driver
In-Reply-To: <1b69c011-cab5-4fde-a61d-7e2536208920@CH1EHSMHS003.ehs.local>
References: <7c5e7537-6ed5-4622-a7a9-bf46820ef695@VA3EHSMHS033.ehs.local>
 <519124D3.2040403@gmail.com>
 <af51c63e-7ff1-4e73-9305-08309217ab38@TX2EHSMHS037.ehs.local>
 <20130514164611.10068.46384@quantum>
 <51927DEB.7090001@balister.org>
 <20130515044604.GA24524@sirena.org.uk>
 <51946082.1000606@codeaurora.org> <5194F0C0.9020609@balister.org>
 <20130516172605.GB1627@sirena.org.uk>
 <1b69c011-cab5-4fde-a61d-7e2536208920@CH1EHSMHS003.ehs.local>
Message-ID: <20130517110241.GI1627@sirena.org.uk>

On Thu, May 16, 2013 at 11:55:45AM -0700, S?ren Brinkmann wrote:
> On Thu, May 16, 2013 at 06:26:05PM +0100, Mark Brown wrote:

> > The binding should obviously be defined as a set of clocks rather than a
> > single clock - something like how we specify regulators on PMICs
> > probably makes sense.  Each clock can have its own properties.

> For a device driver as clock consumer, the bindings etc. are well
> defined. Just add the 'clocks' and 'clock-names' props and use the CCF.

That's not really intended to be used for enumeration by the child,
though - you'd at least need to define that the child looks through
the same binding to figure out what clocks to request.
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From broonie at kernel.org  Fri May 17 07:03:30 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 17 May 2013 12:03:30 +0100
Subject: [PATCH] spi: sirf: fix the issue while transferring more than
 256 words
In-Reply-To: <CAGsJ_4z9=2RYkwntnCD4X-JVsZoYEgzwdWO_uryp3RpbEHu7fA@mail.gmail.com>
References: <1363592828-6347-1-git-send-email-Barry.Song@csr.com>
 <CAGsJ_4wamqzwLZkUz4h6ex=oVQZhzhw7S6r41wt9tTUoMR=aXw@mail.gmail.com>
 <20130516172358.GA1627@sirena.org.uk>
 <CAGsJ_4z9=2RYkwntnCD4X-JVsZoYEgzwdWO_uryp3RpbEHu7fA@mail.gmail.com>
Message-ID: <20130517110330.GJ1627@sirena.org.uk>

On Fri, May 17, 2013 at 09:58:24AM +0800, Barry Song wrote:
> 2013/5/17 Mark Brown <broonie at kernel.org>:

> > Don't top post, don't send contentless pings.  At a guess you didn't CC
> > me...

> yes. i missed you in CC. sorry for that, Mark. so do you want me to resend it?

Yes, please.
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From hvaibhav at ti.com  Fri May 17 07:07:38 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 May 2013 11:07:38 +0000
Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output
 on SoC pad
In-Reply-To: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8C081@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Tuesday, May 07, 2013 3:10 PM
> To: linux-omap at vger.kernel.org
> Cc: tony at atomide.com; Cousson, Benoit; paul at pwsan.com; linux-arm-
> kernel at lists.infradead.org; Hiremath, Vaibhav
> Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2
> output on SoC pad
> 
> 'clkout2' comes out on the device pad and is being used by various
> external on-board peripherals like, Audio codecs, Wilink and stuff.
> So enable the clkout2 by default during init sequence itself
> along with right pinmux configuration clkout2 output.
> 
> Also, add the missing entry of "clkout2_ck" to the AM33xx clock table.
> 
> As far as enabling of clkout2 during init is concerned,
> we can argue that it can be handled using DT property and enable
> the clock only when specified; but not until OMAP clock-tree
> migration to DT.
> 
> Vaibhav Hiremath (2):
>   ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init
>   ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output
> 
>  arch/arm/boot/dts/am335x-bone.dts     |    8 +++++++-
>  arch/arm/boot/dts/am335x-evm.dts      |    8 +++++++-
>  arch/arm/boot/dts/am335x-evmsk.dts    |    8 +++++++-
>  arch/arm/mach-omap2/cclock33xx_data.c |    2 ++
>  4 files changed, 23 insertions(+), 3 deletions(-)

Tony, Paul and Benoit,

Any update on this series?

Thanks,
Vaibhav



From hvaibhav at ti.com  Fri May 17 07:08:27 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 May 2013 11:08:27 +0000
Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to
 GFX hwmod
In-Reply-To: <1367693284-7870-1-git-send-email-hvaibhav@ti.com>
References: <1367693284-7870-1-git-send-email-hvaibhav@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8C092@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Sunday, May 05, 2013 12:18 AM
> To: linux-omap at vger.kernel.org
> Cc: tony at atomide.com; linux-arm-kernel at lists.infradead.org; Hiremath,
> Vaibhav; Paul Walmsley
> Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to
> GFX hwmod
> 
> GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
> so update the GFX hwmod data with .rstst_off and .st_shift
> information.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index d1cf3ab..38c7b04 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -329,7 +329,7 @@ static struct omap_hwmod_class
> am33xx_gfx_hwmod_class = {
>  };
> 
>  static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
> -	{ .name = "gfx", .rst_shift = 0 },
> +	{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
>  };
> 
>  static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
> @@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
>  		.omap4	= {
>  			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
>  			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
> +			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
>  			.modulemode	= MODULEMODE_SWCTRL,
>  		},
>  	},
> --

Tony and Paul,

Any Update on this one as well?

Thanks,
Vaibhav


From pavel at denx.de  Fri May 17 07:09:40 2013
From: pavel at denx.de (Pavel Machek)
Date: Fri, 17 May 2013 13:09:40 +0200
Subject: [PATCHv2 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1368731117-4749-3-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
 <1368731117-4749-3-git-send-email-dinguyen@altera.com>
Message-ID: <20130517110940.GA3466@amd.pavel.ucw.cz>

Hi!

> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add support to gate the clocks that directly feed peripherals. For clocks
> with multiple parents, add the ability to determine the correct parent,
> and also set parents. Also add support to calculate and set the clocks'
> rate.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> Reviewed-by: Pavel Machek <pavel at denx.de>
> CC: Mike Turquette <mturquette at linaro.org>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> Cc: Pavel Machek <pavel at denx.de>
> CC: <linux at arm.linux.org.uk>
> 
> v2:
> - Fix space/indent errors
> - Add streq for strcmp == 0
> ---

> +static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
> +{
> +	u32 l4_src;
> +	u32 perpll_src;
> +	u8 parent;
> +
> +	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
> +		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> +		l4_src &= 0x1;
> +		parent = l4_src;
> +	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
> +		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> +		l4_src = ((l4_src & 0x2) >> 1);
> +		parent = l4_src;
> +	} else {
> +		perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> +		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
> +			perpll_src &= 0x3;
> +		else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
> +			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
> +			perpll_src = ((perpll_src & 0xC) >> 2);
> +		else /*QSPI clock */
> +			perpll_src = ((perpll_src & 0x30) >> 4);
> +		parent = perpll_src;

I really don't like the "else" here. If some new clock name appears in
hwclk->init->name or if there's problem somewhere, it will just
silently operate wrong clock. WARN_ON(!streq(...))?

(I tried to append patch to previous email, with suggested
cleanups....)

> +		} else {/*QSPI clock */
> +			src_reg &= ~0x30;
> +			src_reg |= (parent << 4);
> +		}

Same here. (And there should be space after /* ).

> +	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
> +	if (WARN_ON(!socfpga_clk))
> +		return;
> +
> +	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
> +	if (rc)
> +		clk_gate[0] = 0;
> +
> +	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
> +	if (rc)
> +		socfpga_clk->fixed_div = 0;
> +	else
> +		socfpga_clk->fixed_div = fixed_div;
> +
> +	if (clk_gate[0]) {
> +		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
> +		socfpga_clk->hw.bit_idx = clk_gate[1];
> +
> +		gateclk_ops.enable = clk_gate_ops.enable;
> +		gateclk_ops.disable = clk_gate_ops.disable;
> +	}
> +

Could if (clk_gate[]) be moved one block above? It uses
partially-initialized array, so it would be nice to have code as clear
as possible.


> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	init.name = clk_name;
> +	init.ops = ops;
> +	init.flags = 0;
> +	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
> +			of_clk_get_parent_name(node, i)) != NULL)
> +		i++;

I'd suggest explicit loop, like

+       while (i < SOCFGPA_MAX_PARENTS) {
+               char *name = of_clk_get_parent_name(node, i);
+               parent_name[i] = name;
+               if (name == NULL)
+                       break;
                i++;
+       }

This is a bit too subtle.

> +	init.parent_names = parent_name;
> +	init.num_parents = i;
> +	socfpga_clk->hw.hw.init = &init;
> +
> +	clk = clk_register(NULL, &socfpga_clk->hw.hw);

init is local variable, yet pointer passed to it is in globally
alocated structure. What is going on there? Are there some comments
needed?

Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From ezequiel.garcia at free-electrons.com  Fri May 17 07:09:57 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Fri, 17 May 2013 08:09:57 -0300
Subject: [PATCH 1/2] ARM: mvebu: Fix ranges entry on XP GP board
Message-ID: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>

With the latest device tree reorganization which introduced the
'internal-reg' node, now the only region translated is the internal register's.
This makes the description of the hardware incomplete, for it lacks the
Device Bus childs address space.

In order to fix this, it's required to add a 'ranges' entry with a suitable
address space to map Device Bus childs, on a per-board basis.
This patch fixes the ranges property on the Armada XP GP board.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
---
This should be included in v3.10.

 arch/arm/boot/dts/armada-xp-gp.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 26ad06f..3ee63d1 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,6 +39,9 @@
 	};
 
 	soc {
+		ranges = <0          0 0xd0000000 0x100000
+			  0xf0000000 0 0xf0000000 0x1000000>;
+
 		internal-regs {
 			serial at 12000 {
 				clock-frequency = <250000000>;
-- 
1.8.1.5



From ezequiel.garcia at free-electrons.com  Fri May 17 07:09:58 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Fri, 17 May 2013 08:09:58 -0300
Subject: [PATCH 2/2] ARM: mvebu: Add support for NOR flash device on Armada
 XP-DB board
In-Reply-To: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
Message-ID: <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>

The Armada XP Development Board (DB-78460-BP) has a NOR flash device
connected to the Device Bus. This commit adds the device tree node
to support this device.

This SoC supports a flexible and dynamic decoding window allocation
scheme; but since this feature is still not implemented we need
to specify the window base address in the device tree node itself.

This base address has been selected in a completely arbitrary fashion.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-xp-db.dts | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index d6cc8bf..864831a 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,6 +30,9 @@
 	};
 
 	soc {
+		ranges = <0          0 0xd0000000 0x100000	/* Internal registers 1MiB */
+			  0xf0000000 0 0xf0000000 0x1000000>;	/* Device Bus, NOR 16MiB   */
+
 		internal-regs {
 			serial at 12000 {
 				clock-frequency = <250000000>;
@@ -155,6 +158,35 @@
 					status = "okay";
 				};
 			};
+
+			devbus-bootcs at 10400 {
+				status = "okay";
+				ranges = <0 0xf0000000 0x1000000>;
+
+				/* Device Bus parameters are required */
+
+				/* Read parameters */
+				devbus,bus-width    = <8>;
+				devbus,turn-off-ps  = <60000>;
+				devbus,badr-skew-ps = <0>;
+				devbus,acc-first-ps = <124000>;
+				devbus,acc-next-ps  = <248000>;
+				devbus,rd-setup-ps  = <0>;
+				devbus,rd-hold-ps   = <0>;
+
+				/* Write parameters */
+				devbus,sync-enable = <0>;
+				devbus,wr-high-ps  = <60000>;
+				devbus,wr-low-ps   = <60000>;
+				devbus,ale-wr-ps   = <60000>;
+
+				/* NOR 16 MiB */
+				nor at 0 {
+					compatible = "cfi-flash";
+					reg = <0 0x1000000>;
+					bank-width = <2>;
+				};
+			};
 		};
 	};
 };
-- 
1.8.1.5



From broonie at kernel.org  Fri May 17 07:15:23 2013
From: broonie at kernel.org (Mark Brown)
Date: Fri, 17 May 2013 12:15:23 +0100
Subject: [PATCH v2] ASoC: dfbmcs320: make the driver common for other BT
 modules
In-Reply-To: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>
References: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130517111523.GM1627@sirena.org.uk>

On Fri, May 17, 2013 at 10:19:37AM +0800, Barry Song wrote:
> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
> we don't want everyone to have a seperate codec driver. anyway, the
> feature of Bluetooth handsfree is same on all platforms, so this patch
> makes the DFBM-CS320 driver become a common BT handsfree driver.

Sorry, should have thought of this before but why are we calling this
"handsfree"?  It's just a generic bluetooth link as far as the host
system is concerned, "bt-sco" might be more appropriate?

Otherwise this looks OK for ASoC though I'd expect to see a change to
registration of the OpenMoko BT device (perhaps I missed it though).
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From jp.francois at cynove.com  Fri May 17 07:20:20 2013
From: jp.francois at cynove.com (jean-philippe francois)
Date: Fri, 17 May 2013 13:20:20 +0200
Subject: 3.9 regression : CAM_XCLKA wrong frequency setting.
In-Reply-To: <CAGGh5h2RB7OEOpGOe52eE8+LgdSmvDK5rPLueMzQMfVfOCuYHg@mail.gmail.com>
References: <CAGGh5h2RB7OEOpGOe52eE8+LgdSmvDK5rPLueMzQMfVfOCuYHg@mail.gmail.com>
Message-ID: <CAGGh5h3BNV7fE3jC0KSmA+2K6zKwVyHdeo8AW0gvmhgQsy8ZEg@mail.gmail.com>

2013/5/17 jean-philippe francois <jp.francois at cynove.com>:
> Hi,
>
> Laurent, you are on the recipient list because the symptom is visible
> throug your driver. I found the other name looking in the clock
> related files. Please apologize if you are not concerned by this mail.
>
> Symptom :
> External clock CAM_XCLKA frequency is wrong with 3.9, it was ok until
> 3.6. Everything else is working fine, except the fps are higher, and
> the image quality sucks because the input clock is out of spec.
> Oscilloscope measured freq is around 30 MHz instead of the 24 MHz the
> sensor is asking for.
>
> Hardware :
> dm3730, with 19.2 MHz crystal, running at OPP100
>
> The register frequency settings seems to be ok, and they are the same
> as in 3.6.11 :
> CM_CLKSEL2_PLL : 0x04816807
>         19, 2 * 360 / 8 = 864 MHz
>          this value is already set when I look at it in u-boot
>
> CM_CLKSEL_CAM : 0x5
>         864 / 5 = 172,8 MHz
>         this value is set through the clock framework by the omap3isp
> driver code
>
> ISP.TCTRL_CTRL : 0x7
>         172,8 / 7 = 24,685... MHz
>          this value is set by the omap3isp driver code
>
> However, as stated before, the actual output frequency is NOT 24 MHz
> but around 30.
>
> If dpll4 frequency is wrong, what other clock would be affected ?

As usual, writing a mail brings up new idea. Sorry to use the lists
as rubber duck debug partner, but I still need your help.

Obviously, dpll4 frequency is correct, because it sources the 96 and
48 MHz clock.
I can check it measuring bit time on uart3tx : 8.6usec for 115200 => Ok

30 MHz is 1.25 * 24 MHz
CM_CLKSEL_CAM reset value is 4, programmed value is 5,
So I did the following, while looking at CAM_XCLKA on scope :

# devmem 0x48004f40
0x00000005
# devmem 0x48004f40 32 5  -> freq = 30 MHz
# devmem 0x48004f40 32 4  -> freq = 30 MHz
# devmem 0x48004f40 32 5  -> freq = 24 MHz

So there is something nasty in the setup sequence of cam_mclk and dpll4_m5ckx2
that prevents the new divisor value to be used by the hardware.
I will dive into the code to see where things went wrong, but I am a
bit lost here.

> What can I do to debug this ?
> Laurent, I believe you have a camera add-on board for the beagle xm,
> could you test and report wether you can reproduce this bug ?
>
> Attached is the boot log with 3.9, with some debugging messages activated.
>
> Thank you for your help,
> Regards,
>
> Jean-Philippe Fran?ois


From moinejf at free.fr  Fri May 17 07:33:45 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Fri, 17 May 2013 13:33:45 +0200
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130516192510.GV18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
Message-ID: <20130517133345.7c1368f5@armhf>

On Thu, 16 May 2013 20:25:10 +0100
Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> What follows is my DRM driver for Dove, which I've been working on with
> the Solid-run Cubox, which only offers HDMI output via the TDA19988
> chip.
> 
> Not everything is finished off perfectly in this driver; there's quite
> a number of ragged edges (particularly with page flipping, which is
> completely untested.)
> 
> I have most of the Xorg driver complete - none of the DRI interfaces
> checked yet (partly because that involves quite an amount of work with
> Mesa).
> 
> However, graphics, video overlay, interlacing, accelerated GPU via the
> original vivante support all works through this driver, with this driver
> providing the X pixmaps.

Hi Russell,

I quickly compared your dove drm driver and ours (Sebastian and me):

- CMA helper

  You don't use DRM_KMS_CMA_HELPER and DRM_GEM_CMA_HELPER which would
  simplify some code.

- device tree

  Our driver depends on the DT and, by this way, it may be used for
  various boards (Cubox, DB-MV88AP510 Development Board, CompuLab
  CM-A510 Board..). Especially, in the Cubox, only a HDMI screen may be
  connected, while the display controller permits connection of a smart
  panel (port A) and a VGA screen (port B). 
  Also, the driver could be used for different chips as the Armada 160
  which has quite the same LCD controller (but one LCD only and no
  display controller - Sebastian's idea).

- module loading (si5351, tda998x)

  As our driver is loaded by the Cubox DT, and as the auxilliary drivers
  (external clock, HDMI transmitter) may also be modules, a
  synchronization mechanism (inspired by the tegra drm driver) permits
  the driver to start when all the other drivers are also started.

- display controller

  I implemented output port cloning (LCD 0 to port B) but it is not
  tested (I just have a Cubox and I think that Sebastian did not have
  time enough yet to do it).     

- LCD handling

  With our driver, the description of a smart panel (port A) may be
  done by the DT.

- hardware cursor

  Our driver always proposes the HWC 32 (RGBA 64x64).

- LCD clocks

  Each LCD may use one clock amongst 4 (AXI, LCD PLL and 2 external
  clocks). In our driver, the choice of the clock is done on each video
  mode change (Sebastian's idea).

- interlaced modes

  While the code is there, I did not test the interlaced modes.
  Your code may be better.

- video overlay

  Same as above: the code is in our driver (overlay plane), but it is
  not tested.

- private ioctls

  It should be easy to add them in our driver and have an API
  compatible with your X server module. 

- screen rotation (IRE)

  This feature is needed when the Dove SoC is used in a tablet and does
  not exist in both drivers.

- VGA DAC

  This feature is needed to get the VGA screen parameters (mode,
  dimensions) and does not exist in both drivers too.

Otherwise, there are some small differences in, for example,
programming the LCD modes, or treating the vblank events.

What do you think about merging?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From will.deacon at arm.com  Fri May 17 07:36:22 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 12:36:22 +0100
Subject: ARM Cortex-A7 support in Linux
In-Reply-To: <20130517105500.GE18614@n2100.arm.linux.org.uk>
References: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
 <f6c9d2b0d52d63efa95f780b172690ef@localhost>
 <20130517105500.GE18614@n2100.arm.linux.org.uk>
Message-ID: <20130517113622.GH23112@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
> > It depends which feature you're after. Linux supports the GIC
> > virtualization extensions with KVM, for example. But we don't make any use
> > of other things like priorities, split deactivation/priority drop...
> 
> Not that we could make use of priorities anymore as all interrupt handlers
> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
> higher priority IRQ coming in.
> 
> Part of the solution to that is to go back to the original philosophy of
> IRQ handling in Linux - do the least possible amount of work in the IRQ
> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
> many drivers are no longer written like that, and just do a great amount
> of time consuming work in their IRQ handler.

We could also consider using interrupt priorities to have a fake NMI (I
think PPC does this for some cores), which is useful for profiling and
watchdogs, especially now that FIQ is often stolen by the secure world.

I remember dismissing this in the past because I thought it would increase
our GIC distributor accesses, but I don't remember why.

Will


From marc.zyngier at arm.com  Fri May 17 07:42:11 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 17 May 2013 12:42:11 +0100
Subject: ARM Cortex-A7 support in Linux
In-Reply-To: <20130517113622.GH23112@mudshark.cambridge.arm.com>
References: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
 <f6c9d2b0d52d63efa95f780b172690ef@localhost>
 <20130517105500.GE18614@n2100.arm.linux.org.uk>
 <20130517113622.GH23112@mudshark.cambridge.arm.com>
Message-ID: <51961793.1000107@arm.com>

On 17/05/13 12:36, Will Deacon wrote:
> On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
>> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
>>> It depends which feature you're after. Linux supports the GIC
>>> virtualization extensions with KVM, for example. But we don't make any use
>>> of other things like priorities, split deactivation/priority drop...
>>
>> Not that we could make use of priorities anymore as all interrupt handlers
>> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
>> higher priority IRQ coming in.
>>
>> Part of the solution to that is to go back to the original philosophy of
>> IRQ handling in Linux - do the least possible amount of work in the IRQ
>> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
>> many drivers are no longer written like that, and just do a great amount
>> of time consuming work in their IRQ handler.
> 
> We could also consider using interrupt priorities to have a fake NMI (I
> think PPC does this for some cores), which is useful for profiling and
> watchdogs, especially now that FIQ is often stolen by the secure world.
> 
> I remember dismissing this in the past because I thought it would increase
> our GIC distributor accesses, but I don't remember why.

I think it would rather require to write to the interrupt priority mask
register (GIC_PMR) in the CPU interface. The cost is probably the same,
actually (probably quite high, given how often we enable/disable
interrupts).

	M.
-- 
Jazz is not dead. It just smells funny...



From pavel at denx.de  Fri May 17 07:46:07 2013
From: pavel at denx.de (Pavel Machek)
Date: Fri, 17 May 2013 13:46:07 +0200
Subject: [PATCHv2 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1368731117-4749-6-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
 <1368731117-4749-6-git-send-email-dinguyen@altera.com>
Message-ID: <20130517114607.GB3466@amd.pavel.ucw.cz>

Hi!

> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.

> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> @@ -0,0 +1,139 @@
> +/*
> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
> + *
> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> + *  Copyright (C) 2013 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Taken from dw_mmc_exynos.c

Actually it is   dw_mmc-exynos.c

> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))

Should SYSMGR stuff go to shared header file somewhere?

> +extern void __iomem *sys_manager_base_addr;

This is unused.

> +/* SOCFPGA implementation specific driver private data */
> +struct dw_mci_socfpga_priv_data {
> +	u8	ciu_div;

comment would be nice, something like
/* card interface unit divisor */ ?

> +	u32	hs_timing;

/* card interface unit phase shift for RX/TX mode */
?

> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	clk_disable(host->ciu_clk);
> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
> +	clk_enable(host->ciu_clk);
> +
> +	host->bus_hz /= (priv->ciu_div + 1);

Previous version said:

+       host->bus_hz /= priv->ciu_div;

I see you want to avoid division by zero, but this will introduce
significant error for low divisors, right? Is divisor of 0 valid?

Otherwise it looks good. Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From will.deacon at arm.com  Fri May 17 07:48:27 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 12:48:27 +0100
Subject: ARM Cortex-A7 support in Linux
In-Reply-To: <51961793.1000107@arm.com>
References: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
 <f6c9d2b0d52d63efa95f780b172690ef@localhost>
 <20130517105500.GE18614@n2100.arm.linux.org.uk>
 <20130517113622.GH23112@mudshark.cambridge.arm.com>
 <51961793.1000107@arm.com>
Message-ID: <20130517114827.GI23112@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 12:42:11PM +0100, Marc Zyngier wrote:
> On 17/05/13 12:36, Will Deacon wrote:
> > On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
> >> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
> >>> It depends which feature you're after. Linux supports the GIC
> >>> virtualization extensions with KVM, for example. But we don't make any use
> >>> of other things like priorities, split deactivation/priority drop...
> >>
> >> Not that we could make use of priorities anymore as all interrupt handlers
> >> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
> >> higher priority IRQ coming in.
> >>
> >> Part of the solution to that is to go back to the original philosophy of
> >> IRQ handling in Linux - do the least possible amount of work in the IRQ
> >> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
> >> many drivers are no longer written like that, and just do a great amount
> >> of time consuming work in their IRQ handler.
> > 
> > We could also consider using interrupt priorities to have a fake NMI (I
> > think PPC does this for some cores), which is useful for profiling and
> > watchdogs, especially now that FIQ is often stolen by the secure world.
> > 
> > I remember dismissing this in the past because I thought it would increase
> > our GIC distributor accesses, but I don't remember why.
> 
> I think it would rather require to write to the interrupt priority mask
> register (GIC_PMR) in the CPU interface. The cost is probably the same,
> actually (probably quite high, given how often we enable/disable
> interrupts).

In terms of the hardware, maybe, but the distributor requires a lock and
will also trap to the hypervisor if accessed from a guest.

However, since the GIC_PMR is in the CPU interface then that should be fine.

Will


From marc.zyngier at arm.com  Fri May 17 07:50:33 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 17 May 2013 12:50:33 +0100
Subject: ARM Cortex-A7 support in Linux
In-Reply-To: <20130517114827.GI23112@mudshark.cambridge.arm.com>
References: <A1A6EA40F8503D48BB002B42BD65974E295341@039-SN2MPN1-012.039d.mgd.msft.net>
 <f6c9d2b0d52d63efa95f780b172690ef@localhost>
 <20130517105500.GE18614@n2100.arm.linux.org.uk>
 <20130517113622.GH23112@mudshark.cambridge.arm.com>
 <51961793.1000107@arm.com>
 <20130517114827.GI23112@mudshark.cambridge.arm.com>
Message-ID: <51961989.7020409@arm.com>

On 17/05/13 12:48, Will Deacon wrote:
> On Fri, May 17, 2013 at 12:42:11PM +0100, Marc Zyngier wrote:
>> On 17/05/13 12:36, Will Deacon wrote:
>>> On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
>>>> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
>>>>> It depends which feature you're after. Linux supports the GIC
>>>>> virtualization extensions with KVM, for example. But we don't make any use
>>>>> of other things like priorities, split deactivation/priority drop...
>>>>
>>>> Not that we could make use of priorities anymore as all interrupt handlers
>>>> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
>>>> higher priority IRQ coming in.
>>>>
>>>> Part of the solution to that is to go back to the original philosophy of
>>>> IRQ handling in Linux - do the least possible amount of work in the IRQ
>>>> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
>>>> many drivers are no longer written like that, and just do a great amount
>>>> of time consuming work in their IRQ handler.
>>>
>>> We could also consider using interrupt priorities to have a fake NMI (I
>>> think PPC does this for some cores), which is useful for profiling and
>>> watchdogs, especially now that FIQ is often stolen by the secure world.
>>>
>>> I remember dismissing this in the past because I thought it would increase
>>> our GIC distributor accesses, but I don't remember why.
>>
>> I think it would rather require to write to the interrupt priority mask
>> register (GIC_PMR) in the CPU interface. The cost is probably the same,
>> actually (probably quite high, given how often we enable/disable
>> interrupts).
> 
> In terms of the hardware, maybe, but the distributor requires a lock and
> will also trap to the hypervisor if accessed from a guest.
> 
> However, since the GIC_PMR is in the CPU interface then that should be fine.

Absolutely. I was just thinking of the respective costs of a device
write vs setting the I bit in CPSR.

	M.
-- 
Jazz is not dead. It just smells funny...



From sebastian.hesselbarth at gmail.com  Fri May 17 07:58:34 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 17 May 2013 13:58:34 +0200
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517133345.7c1368f5@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
Message-ID: <51961B6A.6020704@gmail.com>

On 05/17/13 13:33, Jean-Francois Moine wrote:
> On Thu, 16 May 2013 20:25:10 +0100
> Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
>> What follows is my DRM driver for Dove, which I've been working on with
>> the Solid-run Cubox, which only offers HDMI output via the TDA19988
>> chip.
...
> - device tree
>
>    Our driver depends on the DT and, by this way, it may be used for
>    various boards (Cubox, DB-MV88AP510 Development Board, CompuLab
>    CM-A510 Board..). Especially, in the Cubox, only a HDMI screen may be
>    connected, while the display controller permits connection of a smart
>    panel (port A) and a VGA screen (port B).
>    Also, the driver could be used for different chips as the Armada 160
>    which has quite the same LCD controller (but one LCD only and no
>    display controller - Sebastian's idea).

Jean-Francois,

as Russell already mentioned, he is not on DT yet. It's not a big deal
to add the binding parsing to his driver though. Basically, there is 
only one thing that bothers me with Russell's driver: integrating TDA
HDMI in the driver. But from what I have seen, it's almost equal to
our drm_slave_encoder stuff, so rebranding some functions should be
enough to allow any external encoder on lcdc.

> - module loading (si5351, tda998x)
>
>    As our driver is loaded by the Cubox DT, and as the auxilliary drivers
>    (external clock, HDMI transmitter) may also be modules, a
>    synchronization mechanism (inspired by the tegra drm driver) permits
>    the driver to start when all the other drivers are also started.

I agree on HDMI (when enabled through DT), but disagree on clock.
There is some clocks internally that should be exploited even if there
is no external clock available. This is actually something more general
with common clock as it does not handle dynamic clocks yet.

> - display controller
>
>    I implemented output port cloning (LCD 0 to port B) but it is not
>    tested (I just have a Cubox and I think that Sebastian did not have
>    time enough yet to do it).

Lack of time, sorry.
Would have to test on D2Plug which has both HDMI (also TDA) and VGA.

> - LCD handling
>
>    With our driver, the description of a smart panel (port A) may be
>    done by the DT.

In priciple, DT should support describing all possible panel modes. But
of course, let's start with what we can test. SmartPanel and VGA in
Jean-Francois and mine driver are just place holders. To mainline a
common driver, I suggest to take Russell's driver as a start and add
DT and stuff Russell agrees to.

> - LCD clocks
>
>    Each LCD may use one clock amongst 4 (AXI, LCD PLL and 2 external
>    clocks). In our driver, the choice of the clock is done on each video
>    mode change (Sebastian's idea).

This is because of the dynamic clock restriction above. Reprobing clocks
on each mode change will behave like dynamic clocks and should be
removed if common clock framework supports it someday.

Then there is a heuristic, that tries to find the best matching clock
starting with the current clock as lcdc itself can do integer division.

For Cubox with si5351 clock driver, it should be sufficient to rely on
si5351 providing the clock. That will allow all HD modes, except
1600x1200 at 60 and above which exceed 160MHz max output frequency
restriction of si5351.

> - screen rotation (IRE)
>
>    This feature is needed when the Dove SoC is used in a tablet and does
>    not exist in both drivers.

Again, let's implement what we can test - or is there anybody using
secretary mode on his TV? BTW, IRE is only available on Dove, while lcdc
controller can be reused on some PXAs.. try not to put too much Dove
dependency into lcdc if possible.

> - VGA DAC
>
>    This feature is needed to get the VGA screen parameters (mode,
>    dimensions) and does not exist in both drivers too.

Do I still have a VGA monitor to test? ;)

> What do you think about merging?

As said above, I'd prefer to take Russell's driver as a start and merge
ours (actually yours, as I just added stuff that slowed you down :P)

Sebastian


From linux at arm.linux.org.uk  Fri May 17 08:01:15 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 13:01:15 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517133345.7c1368f5@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
Message-ID: <20130517120115.GF18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 01:33:45PM +0200, Jean-Francois Moine wrote:
> Hi Russell,
> 
> I quickly compared your dove drm driver and ours (Sebastian and me):

I already said - I don't support DT.  I don't run any DT based ARM
devices, so I have no experience with DT.  What I care more about
is a working cubox platform, which afaik DT still can't offer yet.

> - CMA helper
> 
>   You don't use DRM_KMS_CMA_HELPER and DRM_GEM_CMA_HELPER which would
>   simplify some code.

Possibly, but the biggest win for me is having cacheable gem objects.
CMA will be a retrograde step for those.

> - device tree
> 
>   Our driver depends on the DT and, by this way, it may be used for
>   various boards (Cubox, DB-MV88AP510 Development Board, CompuLab
>   CM-A510 Board..). Especially, in the Cubox, only a HDMI screen may be
>   connected, while the display controller permits connection of a smart
>   panel (port A) and a VGA screen (port B). 

I only have a Cubox, so I can't test anything but HDMI.

Given that there's big questions about the polarity of signals coming
out of the Armada 510 (with the invert bits 0, are the syncs positive
or negative?) I wouldn't like to lead anyone up the path of thinking
that this driver supports anything but the tested HDMI scenario yet.

As that information is not in any of the Armada 510 TRMs, and can only
be discovered by physically probing the signals with a scope... that's
on my todo list when I feel like dismantling the Cubox and getting the
soldering iron out to separate the two boards so I can get access to
the signals.

I've already tried to explain this to Sebastian on IRC, and kept getting
nonsense back from him.  "You need to program the whole chain".  Yes,
but that makes no sense to the question I was asking.

The reason is this:
+-----------------------------+      +------------------------+
| Armada510                   |      |   TDA19988             |
| LCD controller ---> switch ---------> switch --> processing |
|   VSYNC/HSYNC               |      |                        |
+-----------------------------+      +------------------------+

The issue is that each 'switch' point is capable of inverting the sync
signal.  If you program both identically then you end up with inversion
following another inversion.  Which means no inversion.  That's why
I've found Sebastian's answers to be much less than helpful on this
point.

What I have found with the NXP TDA19988 driver is that you need to get
the input syncs to the TDA19988 set to the correct polarity for the
TDA19988, which _isn't_ what is advertised in the EDID.  The TDA19988
then has its own processing internally which places the appropriate
sync codes onto the output data stream.

In some cases, getting this wrong shifts the displayed image by a few
pixels/lines.  In other cases you get no output or invalid output which
isn't recognised by the connected device.

>   Also, the driver could be used for different chips as the Armada 160
>   which has quite the same LCD controller (but one LCD only and no
>   display controller - Sebastian's idea).

That's no problem - you just provide my driver with only one IO space
for the LCD controller, and it will only use one.  If you have more
than two, it will cope as well.

> - module loading (si5351, tda998x)
> 
>   As our driver is loaded by the Cubox DT, and as the auxilliary drivers
>   (external clock, HDMI transmitter) may also be modules, a
>   synchronization mechanism (inspired by the tegra drm driver) permits
>   the driver to start when all the other drivers are also started.

The lack of Si5351 already gets tested on every cubox boot I do.  That
causes probe deferal, which allows the driver to properly start when
it becomes ready.

Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 7) is a 16550A
console [ttyS0] enabled
serial8250.1: ttyS1 at MMIO 0xf1012100 (irq = 8) is a 16550A
[drm] Initialized drm 1.1.0 20060810
[drm:dove_drm_load] *ERROR* failed to get clock
platform dove-drm: Driver dove-drm requests probe deferral
...
si5351 0-0060: registered si5351 i2c client
si5351 0-0060: external clock setup : clkdev = d827f820
cubox_extclk_setup : add alias 'extclk/dovefb.0' to clkout0 w 0
external clock setup done
...
dove-drm dove-drm: found TDA19988
[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[drm] No driver support for vblank timestamp query.
dove-drm dove-drm: failed to read EDID
Console: switching to colour frame buffer device 160x45
dove-drm dove-drm: fb0: dove-drmfb frame buffer device
dove-drm dove-drm: registered panic notifier
[drm] Initialized dove-drm 1.0.0 20120730 on minor 0

TDA998x is a different matter - I do need to propagate that error code,
and then make a decision in the tda19988 connector whether to return
-EPROBEDEFER.

(The failure to read EDID is caused by my HDMI switch, which at boot
doesn't have the cubox selected, and so doesn't provide EDID until
the cubox is selected.)

> - display controller
> 
>   I implemented output port cloning (LCD 0 to port B) but it is not
>   tested (I just have a Cubox and I think that Sebastian did not have
>   time enough yet to do it).

I didn't bother with this because - again - no access to port B on my
hardware.

> - LCD handling
> 
>   With our driver, the description of a smart panel (port A) may be
>   done by the DT.

That's simple enough to add - just another 'connector' even though it's
the same physical connection out of the Armada 510.

> - hardware cursor
> 
>   Our driver always proposes the HWC 32 (RGBA 64x64).

Hardware cursor support is pretty useless.

In RGBA mode, it's not 64x64 but you get the choice of either 64x32 or
32x64.  This is useless for Xorg's purposes, where it really wants a
64x64 cursor.  And the XF86 Xorg backend really wants RGBA for hardware
cursor, not 2bpp.  So my conclusion is that hardware cursor is not worth
any effort and I've a good mind to strip that out from my driver (which
will simplify a few places.)

I've played with the idea of reducing a RGBA cursor down to 2bpp mode
where we can fit the required size in, but that doesn't work very well.

Just because the hardware does something doesn't mean you should write
code for it! :)

> - LCD clocks
> 
>   Each LCD may use one clock amongst 4 (AXI, LCD PLL and 2 external
>   clocks). In our driver, the choice of the clock is done on each video
>   mode change (Sebastian's idea).

Yes, this could be added to mine, probably fairly simply too, but for
the purposes of the cubox...

> - interlaced modes
> 
>   While the code is there, I did not test the interlaced modes.
>   Your code may be better.

I know mine works... I've run it at 1080i with the NXP TDA19988 driver.

> - video overlay
> 
>   Same as above: the code is in our driver (overlay plane), but it is
>   not tested.

We as a family, have watched many hours of video on mine. :)

> - private ioctls
> 
>   It should be easy to add them in our driver and have an API
>   compatible with your X server module. 
> 
> - screen rotation (IRE)
> 
>   This feature is needed when the Dove SoC is used in a tablet and does
>   not exist in both drivers.
> 
> - VGA DAC
> 
>   This feature is needed to get the VGA screen parameters (mode,
>   dimensions) and does not exist in both drivers too.
> 
> Otherwise, there are some small differences in, for example,
> programming the LCD modes, or treating the vblank events.
> 
> What do you think about merging?

Yes, I think merging the two together would probably be sane. :)


From monstr at monstr.eu  Fri May 17 08:09:38 2013
From: monstr at monstr.eu (Michal Simek)
Date: Fri, 17 May 2013 14:09:38 +0200
Subject: [PATCH v2 1/5] tty: xuartps: Remove suspend/resume functions
In-Reply-To: <1368467199-8702-2-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368467199-8702-2-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <51961E02.9020501@monstr.eu>

Hi Greg,

can you please add this patch to your tree?
It is unrelated to clk changes which Soren sent.

Thanks,
Michal

On 05/13/2013 07:46 PM, Soren Brinkmann wrote:
> Currently Zynq does not support suspend/resume.
> The driver callbacks are never used or tested, broken and using the old
> PM interface.
> 
> Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: Jiri Slaby <jslaby at suse.cz>
> Cc: linux-serial at vger.kernel.org
> ---
>  drivers/tty/serial/xilinx_uartps.c | 30 ------------------------------
>  1 file changed, 30 deletions(-)
> 
> diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
> index 4e5c778..b5f655d 100644
> --- a/drivers/tty/serial/xilinx_uartps.c
> +++ b/drivers/tty/serial/xilinx_uartps.c
> @@ -1006,34 +1006,6 @@ static int xuartps_remove(struct platform_device *pdev)
>  	return rc;
>  }
>  
> -/**
> - * xuartps_suspend - suspend event
> - * @pdev: Pointer to the platform device structure
> - * @state: State of the device
> - *
> - * Returns 0
> - **/
> -static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
> -{
> -	/* Call the API provided in serial_core.c file which handles
> -	 * the suspend.
> -	 */
> -	uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
> -	return 0;
> -}
> -
> -/**
> - * xuartps_resume - Resume after a previous suspend
> - * @pdev: Pointer to the platform device structure
> - *
> - * Returns 0
> - **/
> -static int xuartps_resume(struct platform_device *pdev)
> -{
> -	uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
> -	return 0;
> -}
> -
>  /* Match table for of_platform binding */
>  static struct of_device_id xuartps_of_match[] = {
>  	{ .compatible = "xlnx,xuartps", },
> @@ -1044,8 +1016,6 @@ MODULE_DEVICE_TABLE(of, xuartps_of_match);
>  static struct platform_driver xuartps_platform_driver = {
>  	.probe   = xuartps_probe,		/* Probe method */
>  	.remove  = xuartps_remove,		/* Detach method */
> -	.suspend = xuartps_suspend,		/* Suspend */
> -	.resume  = xuartps_resume,		/* Resume after a suspend */
>  	.driver  = {
>  		.owner = THIS_MODULE,
>  		.name = XUARTPS_NAME,		/* Driver name */
> 


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From wsa at the-dreams.de  Fri May 17 08:15:53 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Fri, 17 May 2013 14:15:53 +0200
Subject: [PATCH 9/9] I2C: mv64xxx: fix race between FSM/interrupt and
 process context
In-Reply-To: <20130517100016.GB18614@n2100.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4xE-0004KB-2T@rmk-PC.arm.linux.org.uk>
 <20130517095149.GI17056@katana>
 <20130517100016.GB18614@n2100.arm.linux.org.uk>
Message-ID: <20130517121550.GB2939@katana>

On Fri, May 17, 2013 at 11:00:16AM +0100, Russell King - ARM Linux wrote:
> On Fri, May 17, 2013 at 11:51:51AM +0200, Wolfram Sang wrote:
> > >  {
> > >  	switch(drv_data->action) {
> > >  	case MV64XXX_I2C_ACTION_SEND_RESTART:
> > > +		/* We should only get here if we have further messages */
> > > +		BUG_ON(drv_data->num_msgs == 0);
> > > +
> > 
> > ...
> > 
> > > @@ -453,16 +463,20 @@ static int
> > >  mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
> > >  {
> > >  	struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
> > > -	int	i, rc;
> > > +	int rc, ret = num;
> > >  
> > > -	for (i = 0; i < num; i++) {
> > > -		rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
> > > -						i == 0, i + 1 == num);
> > > -		if (rc < 0)
> > > -			return rc;
> > > -	}
> > > +	BUG_ON(drv_data->msgs != NULL);
> > 
> > Can't we handle this more gracefully than to halt the kernel? Like
> > WARN_ON and resetting the controller or disabling the bus or...
> 
> Well, the latter really is something which should never ever happen,
> and if it does happen it can only really be because something's
> screwed up in the locking in the I2C layer.

I'd think we should trust the layer here.

> The former is more probable, and I thought about that, but I don't
> have any good alternative solution.  Given the problems I've seen,
> I don't think resetting the controller is really an option, because
> that'll likely cause the bus to lock (that's the original problem
> which I'm trying to solve in this patch.)  The thing really does
> have to work according to the I2C protocol otherwise stuff goes
> irrecoverably wrong to the point of needing an entire system reset.

Fine with me for now. If somebody later has a setup where I2C slaves can
be reset (e.g. via GPIO), so a complete bus reset is possible, we might
need another solution, then.

Thanks,

   Wolfram


From monstr at monstr.eu  Fri May 17 08:14:47 2013
From: monstr at monstr.eu (Michal Simek)
Date: Fri, 17 May 2013 14:14:47 +0200
Subject: [PATCH v2 0/5] Zynq: revised CCF code
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <51961F37.3030202@monstr.eu>

Hi Mike,

I have sent email to Greg to take this patch from this series
though his serial tree because it is unrelated to this clock stuff.

Can you please give me your ACK for these patches or add them
to your CLK tree?

I just need to move this to be able to start to push other drivers
which are related to this.

Thanks,
Michal


On 05/13/2013 07:46 PM, Soren Brinkmann wrote:
> I rebased this series on v3.10-rc1 eliminating all dependencies and incorporated
> Greg's feedback.
> I'll push this also to my github repository.
> https://github.com/sorenb-xlnx/linux-xlnx/tree/zynq/clkc
> 
> v2:
>  - dropped the 'sort #includes' patches
> 
> 	S?ren
> 
> 
> Soren Brinkmann (5):
>   tty: xuartps: Remove suspend/resume functions
>   clk: zynq: Factor out PLL driver
>   clk: zynq: Add clock controller driver
>   arm: zynq: Migrate platform to clock controller
>   clk: zynq: Remove deprecated clock code
> 
>  .../devicetree/bindings/clock/zynq-7000.txt        | 127 +++--
>  arch/arm/boot/dts/zynq-7000.dtsi                   |  71 +--
>  arch/arm/boot/dts/zynq-zc702.dts                   |   4 -
>  arch/arm/mach-zynq/slcr.c                          |   2 +-
>  drivers/clk/Makefile                               |   2 +-
>  drivers/clk/clk-zynq.c                             | 378 ---------------
>  drivers/clk/zynq/Makefile                          |   3 +
>  drivers/clk/zynq/clkc.c                            | 533 +++++++++++++++++++++
>  drivers/clk/zynq/pll.c                             | 235 +++++++++
>  drivers/clocksource/cadence_ttc_timer.c            |  23 +-
>  drivers/tty/serial/xilinx_uartps.c                 | 115 +++--
>  include/linux/clk/zynq.h                           |   8 +-
>  12 files changed, 974 insertions(+), 527 deletions(-)
>  delete mode 100644 drivers/clk/clk-zynq.c
>  create mode 100644 drivers/clk/zynq/Makefile
>  create mode 100644 drivers/clk/zynq/clkc.c
>  create mode 100644 drivers/clk/zynq/pll.c
> 


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From wsa at the-dreams.de  Fri May 17 08:17:56 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Fri, 17 May 2013 14:17:56 +0200
Subject: [PATCH 1/9] I2C: mv64xxx: work around signals causing I2C
 transactions to be aborted
In-Reply-To: <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>
Message-ID: <20130517121752.GC2939@katana>

On Thu, May 16, 2013 at 09:30:59PM +0100, Russell King wrote:
> Do not use interruptible waits in an I2C driver; if a process uses
> signals (eg, Xorg uses SIGALRM and SIGPIPE) then these signals can
> cause the I2C driver to abort a transaction in progress by another
> driver, which can cause that driver to fail.  I2C drivers are not
> expected to abort transactions on signals.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>

Applied to for-current, thanks!

Rest will be reviewed later...


From linus.walleij at linaro.org  Fri May 17 08:20:49 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 14:20:49 +0200
Subject: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
In-Reply-To: <201305152231.52423.heiko@sntech.de>
References: <201305111330.05046.heiko@sntech.de>
 <201305111331.25405.heiko@sntech.de>
 <CACRpkdaT195McX9NeccJYpmWbuYK-AZUTHr9AXKHnJdkf+Qzuw@mail.gmail.com>
 <201305152231.52423.heiko@sntech.de>
Message-ID: <CACRpkdaGBjUfhfT2zCEeNmMh3KhouOMjKSB7H6_cu_uDM6cm=w@mail.gmail.com>

On Wed, May 15, 2013 at 10:31 PM, Heiko St?bner <heiko at sntech.de> wrote:

> If I understand the writel semantics and the thread from you from 2011 [0]
> correctly, only the writel to DMASKTRIG mustn't be relaxed to make sure the
> settings registers are written to before, so like:
>
>        writel_relaxed(txd->src_addr, phy->base + DISRC);
>        writel_relaxed(txd->disrcc, phy->base + DISRCC);
>        writel_relaxed(txd->dst_addr, phy->base + DIDST);
>        writel_relaxed(txd->didstc, phy->base + DIDSTC);
>        writel_relaxed(dcon, phy->base + DCON);
>
>        val = readl_relaxed(phy->base + DMASKTRIG);
>        val &= ~DMASKTRIG_STOP;
>        val |= DMASKTRIG_ON;
>        writel(val, phy->base + DMASKTRIG);

Yep. That will drain write buffers etc and make sure all outstanding writes hit
the hardware.

Yours,
Linus Walleij


From gregory.clement at free-electrons.com  Fri May 17 08:25:02 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 17 May 2013 14:25:02 +0200
Subject: [PATCH] [for 3.10-rc] ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for
 mvebu platform
Message-ID: <1368793503-8883-1-git-send-email-gregory.clement@free-electrons.com>

Hello,

The following fix a regression which appear in 3.10-rc1: the GPIOLIB
is nor more selected for mvebu. I found this while I was trying to
test the GPIO buttons on the OpenBlocks AX3, but it impacts all the
mvebu platform.

It was the conjunction of a lot of
elements which lead to this bug, see the commit log for the
details. The patch by itself is very simple.

Regards,

Gregory CLEMENT (1):
  ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform

 arch/arm/mach-mvebu/Kconfig | 1 +
 1 file changed, 1 insertion(+)

-- 
1.8.1.2



From gregory.clement at free-electrons.com  Fri May 17 08:25:03 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 17 May 2013 14:25:03 +0200
Subject: [PATCH] ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform
In-Reply-To: <1368793503-8883-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368793503-8883-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368793503-8883-2-git-send-email-gregory.clement@free-electrons.com>

Initially ARCH_REQUIRE_GPIOLIB was part of Thomas Petazzoni series
when he introduced the gpiolib support for mvebu:
93a59cf arm: mvebu: use GPIO support now that a driver is available

This commit was written to be applied for the ARCH_MVEBU which was
located in arch/arm/KConfig and was merged in 3.7.

In the same time Rob Herring moved the ARCH_MVEBU block to
arch/arm/mach-mvebu/Kconfig with this commit and also merged in 3.7:
387798b ARM: initial multiplatform support

Unfortunately the ARCH_REQUIRE_GPIOLIB have been lost during this
migration. This was not noticed until the v3.10-rc1, because mvebu as
part of ARCH_MULTIPLATFORM was always selected with ARCH_VEXPRESS, and
this architect selected ARCH_REQUIRE_GPIOLIB.

Since the following commit from Arnd: "883a106 ARM: default machine
descriptor for multiplatform", ARCH_VEXPRESS was then no more selected
by default with ARCH_MVEBU and it made appeared the lack of
ARCH_REQUIRE_GPIOLIB for mvebu. This commit added back the selection
of ARCH_REQUIRE_GPIOLIB for ARCH_MVEBU.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mvebu/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb..80a8bca 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -15,6 +15,7 @@ config ARCH_MVEBU
 	select MVEBU_CLK_GATING
 	select MVEBU_MBUS
 	select ZONE_DMA if ARM_LPAE
+	select ARCH_REQUIRE_GPIOLIB
 
 if ARCH_MVEBU
 
-- 
1.8.1.2



From g.liakhovetski at gmx.de  Fri May 17 08:26:48 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 17 May 2013 14:26:48 +0200 (CEST)
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <Pine.LNX.4.64.1305171423270.31481@axis700.grange>

Hi Laurent

On Wed, 15 May 2013, Laurent Pinchart wrote:

> Add GPIO controller nodes to the r8a7790 core device tree.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> ---
>  arch/arm/boot/dts/r8a7790.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)

Also here a couple of things are missing (presumably, for other SoCs you 
need the same):

diff --git a/arch/arm/boot/dts/r8a7790.dtsi 
b/arch/arm/boot/dts/r8a7790.dtsi
index 674ee39..cd1a04f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -51,6 +51,7 @@
 		interrupts = <0 4 0x4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-ranges = <&pfc 0 0 32>;
 	};
 
 	gpio1: gpio at ffc41000 {
@@ -60,6 +61,7 @@
 		interrupts = <0 5 0x4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-ranges = <&pfc 0 32 32>;
 	};
 
 	gpio2: gpio at ffc42000 {
@@ -69,6 +71,7 @@
 		interrupts = <0 6 0x4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-ranges = <&pfc 0 64 32>;
 	};
 
 	gpio3: gpio at ffc43000 {
@@ -78,6 +81,7 @@
 		interrupts = <0 7 0x4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-ranges = <&pfc 0 96 32>;
 	};
 
 	gpio4: gpio at ffc44000 {
@@ -87,6 +91,7 @@
 		interrupts = <0 8 0x4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-ranges = <&pfc 0 128 32>;
 	};
 
 	gpio5: gpio at ffc45000 {
@@ -96,6 +101,7 @@
 		interrupts = <0 9 0x4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-ranges = <&pfc 0 160 32>;
 	};
 
 	timer {
@@ -118,6 +124,7 @@
 	pfc: pfc at e6060000 {
 		compatible = "renesas,pfc-r8a7790";
 		reg = <0 0xe6060000 0 0x250>;
+		#gpio-range-cells = <3>;
 	};
 
 	/* No MMC_CAP_UHS_DDR50 (dual data rate) capability on r8a7790! */

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From arnd at arndb.de  Fri May 17 08:29:52 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 14:29:52 +0200
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <20130517085714.GG8607@S2101-09.ap.freescale.net>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <5396520.ZTuSn9S4Vd@wuerfel>
 <20130517085714.GG8607@S2101-09.ap.freescale.net>
Message-ID: <201305171429.52646.arnd@arndb.de>

On Friday 17 May 2013, Shawn Guo wrote:
> On Thu, May 16, 2013 at 12:29:28PM +0200, Arnd Bergmann wrote:
> > On Thursday 16 May 2013 14:10:46 Jingchang Lu wrote:
> > > +config SOC_MVF600
> > 
> > Shouldn't that 'depends on ARCH_MULTI_V7'?
> > 
> SOC_MVF600 is added as a sub-item of ARCH_MXC which already handles the
> ARCH_MULTI_* dependency.

Ah, makes sense.

> > Can you describe how much Vybrid is actually like MXC? Do you actually
> > use most of the mach-imx code?
> > 
> Jingchang mentioned some IP blocks shared between IMX and Vybrid.  Right
> now, mvf600 reuses mxc_restart() and some amount of clk code
> clk-pllv3.c, clk-gate2.c clk.c etc. in arch/arm/mach-imx.

Ok.

> > Actually I think you should move that driver to drivers/clk and use
> > of_clk_init(NULL) to initialize it.
> > 
> The mvf600 clock driver uses a lot of base clk support from mach-imx,
> and can not be moved into drivers/clk as a single driver.  Right now, in
> IMX clock drivers, we call of_clk_init() to only register fixed rate
> clocks, since all the other clocks are not represented in device tree.

What are your plans for this in the long run?

> > It would be nice if we could integrate that into the watchdog driver,
> > so that driver just registers a pm_restart function when it gets loaded.
> > It is a rather small driver, so it would not hurt to always load it.
> > 
> Sound like a good idea.  We will consider it as another cleanup task for
> mach-imx.

Ok
 
> > What is the mscm? Shouldn't the boot loader have set this up correctly?
> > If you can remove that code from the kernel, you can use the default
> > irqchip_init call.
> > 
> Yeah, and if we find another way for l2x0_of_init() call.

Good point. That is something we need to do anyway.

> > > +static const char *mvf600_dt_compat[] __initdata = {
> > > +	"fsl,mvf600",
> > > +	NULL,
> > > +};
> > > +
> > > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)")
> > > +	.init_irq	= mvf600_init_irq,
> > > +	.init_time	= mvf600_init_time,
> > > +	.init_machine   = mvf600_init_machine,
> > > +	.dt_compat	= mvf600_dt_compat,
> > > +	.restart	= mxc_restart,
> > > +MACHINE_END
> > 
> > If we can do all of the above, we can actually remove the entire machine
> > descriptor here, since all its members are NULL.
> > 
> Yeah, we understand the goal, and this will be the goal of mach-imx
> cleanup.

Ok. I guess we just won't be there for 3.11 then.

	Arnd



From yegorslists at googlemail.com  Fri May 17 08:30:34 2013
From: yegorslists at googlemail.com (yegorslists at googlemail.com)
Date: Fri, 17 May 2013 14:30:34 +0200
Subject: [PATCH] usb: musb: fix clock naming
In-Reply-To: <1368793834-31627-1-git-send-email-yegorslists@googlemail.com>
References: <1368793834-31627-1-git-send-email-yegorslists@googlemail.com>
Message-ID: <1368793834-31627-2-git-send-email-yegorslists@googlemail.com>

From: Yegor Yefremov <yegorslists at googlemail.com>

'ick' was changed to 'hsotgusb_ick'
'fck' was changed to 'hsotgusb_fck'

Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
---
 drivers/usb/musb/am35x.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index 2231850..92b5b23 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -477,14 +477,14 @@ static int am35x_probe(struct platform_device *pdev)
 		goto err1;
 	}
 
-	phy_clk = clk_get(&pdev->dev, "fck");
+	phy_clk = clk_get(&pdev->dev, "hsotgusb_ick");
 	if (IS_ERR(phy_clk)) {
 		dev_err(&pdev->dev, "failed to get PHY clock\n");
 		ret = PTR_ERR(phy_clk);
 		goto err3;
 	}
 
-	clk = clk_get(&pdev->dev, "ick");
+	clk = clk_get(&pdev->dev, "hsotgusb_fck");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
 		ret = PTR_ERR(clk);
-- 
1.7.7



From arnd at arndb.de  Fri May 17 08:31:15 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 14:31:15 +0200
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <201305171429.52646.arnd@arndb.de>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <20130517085714.GG8607@S2101-09.ap.freescale.net>
 <201305171429.52646.arnd@arndb.de>
Message-ID: <201305171431.15701.arnd@arndb.de>

On Friday 17 May 2013, Arnd Bergmann wrote:
> > > > +static const char *mvf600_dt_compat[] __initdata = {
> > > > + "fsl,mvf600",
> > > > + NULL,
> > > > +};
> > > > +
> > > > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)")
> > > > + .init_irq       = mvf600_init_irq,
> > > > + .init_time      = mvf600_init_time,
> > > > + .init_machine   = mvf600_init_machine,
> > > > + .dt_compat      = mvf600_dt_compat,
> > > > + .restart        = mxc_restart,
> > > > +MACHINE_END
> > > 
> > > If we can do all of the above, we can actually remove the entire machine
> > > descriptor here, since all its members are NULL.
> > > 
> > Yeah, we understand the goal, and this will be the goal of mach-imx
> > cleanup.
> 
> Ok. I guess we just won't be there for 3.11 then.

To clarify: what I mean is we should try to remove all the callbacks 
we can here, but merge the MVF600 port anyway, even if we still need a
couple of them.

	Arnd


From yegorslists at googlemail.com  Fri May 17 08:30:33 2013
From: yegorslists at googlemail.com (yegorslists at googlemail.com)
Date: Fri, 17 May 2013 14:30:33 +0200
Subject: [PATCH] broken musb on am35xx
Message-ID: <1368793834-31627-1-git-send-email-yegorslists@googlemail.com>


The ick and fck clock names nave been changed. This patch updates these names. Please see this discussion for reference:

https://patchwork.kernel.org/patch/1231671/

Yegor


From plagnioj at jcrosoft.com  Fri May 17 08:38:07 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 14:38:07 +0200
Subject: [PATCH 0/5 v2] ARM: at91: dt: switch to pre-processor
In-Reply-To: <5195EA33.4010400@atmel.com>
References: <20130515141906.GI22508@game.jcrosoft.org>
 <5195EA33.4010400@atmel.com>
Message-ID: <20130517123807.GA16804@game.jcrosoft.org>

On 10:28 Fri 17 May     , Nicolas Ferre wrote:
> On 15/05/2013 16:19, Jean-Christophe PLAGNIOL-VILLARD :
> >HI,
> >
> >	v2:
> >	 use common IRQ define
> >	 split patch
> >	 rebase on 3.10-rc1
> >
> >         The follow patch series switch the at91 to DT pre-processor
> >
> >         So we can use macro for AIC and Pinctrl instead of magic
> 
> Hi, this is very good for me: nice to use the common GPIO and IRQ
> defines. It increases readability a lot!
and avoid typo when adding pinctrl
> 
> So, it seems natural to push this series through arm-soc. It would
> be integrated early in a "cleanup" branch for 3.11.
> We also would like to make it a prerequisite for all AT91 material
> that are touching the changed files, targeted for 3.11.

agreed
> 
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Best Regards,
J.
> 
> Thanks, best regards.
> 
> >The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> >
> >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> >
> >are available in the git repository at:
> >
> >   git://github.com/at91linux/linux-at91.git j/for-3.11-dt
> >
> >for you to fetch changes up to 3668ac6a70bc5af71a947ad7b531c57b8a787ea0:
> >
> >   ARM: at91: dt: switch to standard IRQ flag defines (2013-05-15 21:56:18 +0800)
> >
> >----------------------------------------------------------------
> >Jean-Christophe PLAGNIOL-VILLARD (5):
> >       ARM: at91: dt: use #include for all device trees
> >       ARM: at91: dt: switch to standard GPIO flag defines.
> >       ARM: at91: dt: add pinctrl pre-processor define
> >       ARM: at91: dt: switch to pinctrl to pre-processor
> >       ARM: at91: dt: switch to standard IRQ flag defines
> >
> >  arch/arm/boot/dts/aks-cdu.dts               |   12 +--
> >  arch/arm/boot/dts/animeo_ip.dts             |   18 ++---
> >  arch/arm/boot/dts/at91-ariag25.dts          |    6 +-
> >  arch/arm/boot/dts/at91rm9200.dtsi           |  207 +++++++++++++++++++++++++------------------------
> >  arch/arm/boot/dts/at91rm9200ek.dts          |   10 +--
> >  arch/arm/boot/dts/at91sam9260.dtsi          |  215 ++++++++++++++++++++++++++-------------------------
> >  arch/arm/boot/dts/at91sam9263.dtsi          |  203 ++++++++++++++++++++++++------------------------
> >  arch/arm/boot/dts/at91sam9263ek.dts         |   24 +++---
> >  arch/arm/boot/dts/at91sam9g15.dtsi          |    2 +-
> >  arch/arm/boot/dts/at91sam9g15ek.dts         |    4 +-
> >  arch/arm/boot/dts/at91sam9g20.dtsi          |    2 +-
> >  arch/arm/boot/dts/at91sam9g20ek.dts         |    6 +-
> >  arch/arm/boot/dts/at91sam9g20ek_2mmc.dts    |   10 +--
> >  arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   28 ++++---
> >  arch/arm/boot/dts/at91sam9g25.dtsi          |    2 +-
> >  arch/arm/boot/dts/at91sam9g25ek.dts         |    4 +-
> >  arch/arm/boot/dts/at91sam9g35.dtsi          |    2 +-
> >  arch/arm/boot/dts/at91sam9g35ek.dts         |    4 +-
> >  arch/arm/boot/dts/at91sam9g45.dtsi          |  213 +++++++++++++++++++++++++-------------------------
> >  arch/arm/boot/dts/at91sam9m10g45ek.dts      |   38 ++++-----
> >  arch/arm/boot/dts/at91sam9n12.dtsi          |  141 +++++++++++++++++-----------------
> >  arch/arm/boot/dts/at91sam9n12ek.dts         |   14 ++--
> >  arch/arm/boot/dts/at91sam9x25.dtsi          |   22 +++---
> >  arch/arm/boot/dts/at91sam9x25ek.dts         |    4 +-
> >  arch/arm/boot/dts/at91sam9x35.dtsi          |    2 +-
> >  arch/arm/boot/dts/at91sam9x35ek.dts         |    4 +-
> >  arch/arm/boot/dts/at91sam9x5.dtsi           |  279 +++++++++++++++++++++++++++++++++---------------------------------
> >  arch/arm/boot/dts/at91sam9x5cm.dtsi         |    8 +-
> >  arch/arm/boot/dts/at91sam9x5ek.dtsi         |   14 ++--
> >  arch/arm/boot/dts/ethernut5.dts             |    6 +-
> >  arch/arm/boot/dts/evk-pro3.dts              |    6 +-
> >  arch/arm/boot/dts/ge863-pro3.dtsi           |    2 +-
> >  arch/arm/boot/dts/kizbox.dts                |   16 ++--
> >  arch/arm/boot/dts/mpa1600.dts               |    4 +-
> >  arch/arm/boot/dts/pm9g45.dts                |   22 +++---
> >  arch/arm/boot/dts/sama5d3.dtsi              |  520 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------
> >  arch/arm/boot/dts/sama5d31ek.dts            |    6 +-
> >  arch/arm/boot/dts/sama5d33ek.dts            |    4 +-
> >  arch/arm/boot/dts/sama5d34ek.dts            |    6 +-
> >  arch/arm/boot/dts/sama5d35ek.dts            |    4 +-
> >  arch/arm/boot/dts/sama5d3xcm.dtsi           |    4 +-
> >  arch/arm/boot/dts/sama5d3xdm.dtsi           |    2 +-
> >  arch/arm/boot/dts/sama5d3xmb.dtsi           |   26 +++----
> >  arch/arm/boot/dts/tny_a9260.dts             |    4 +-
> >  arch/arm/boot/dts/tny_a9263.dts             |    4 +-
> >  arch/arm/boot/dts/tny_a9g20.dts             |    4 +-
> >  arch/arm/boot/dts/usb_a9260.dts             |    4 +-
> >  arch/arm/boot/dts/usb_a9260_common.dtsi     |    6 +-
> >  arch/arm/boot/dts/usb_a9263.dts             |    8 +-
> >  arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi    |   22 +++---
> >  arch/arm/boot/dts/usb_a9g20.dts             |    4 +-
> >  include/dt-bindings/pinctrl/at91.h          |   35 +++++++++
> >  52 files changed, 1139 insertions(+), 1078 deletions(-)
> >  create mode 100644 include/dt-bindings/pinctrl/at91.h
> >
> >Best Regards,
> >J.
> >
> >
> 
> 
> -- 
> Nicolas Ferre


From jason at lakedaemon.net  Fri May 17 08:55:13 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 17 May 2013 08:55:13 -0400
Subject: [PATCHv9 5/9] clk: mvebu: create parent-child relation for
 PCIe clocks on Armada 370
In-Reply-To: <20130517070826.12127.41382@quantum>
References: <1368624323-24311-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368624323-24311-6-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130515214154.12127.73539@quantum>
 <20130516094417.24b1ca0d@skate> <51949830.70306@gmail.com>
 <20130516150616.GD6563@titan.lakedaemon.net>
 <20130517070826.12127.41382@quantum>
Message-ID: <20130517125513.GC11137@titan.lakedaemon.net>

On Fri, May 17, 2013 at 12:08:26AM -0700, Mike Turquette wrote:
> Quoting Jason Cooper (2013-05-16 08:06:16)
> > Mike, Sebastian,
> > 
> > On Thu, May 16, 2013 at 10:26:24AM +0200, Sebastian Hesselbarth wrote:
> > > On 05/16/2013 09:44 AM, Thomas Petazzoni wrote:
> > > >Dear Mike Turquette,
> > > >
> > > >On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> > > >>Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> > > >>>The Armada 370 has two gatable clocks for each PCIe interface, and we
> > > >>>want both of them to be enabled. We therefore make one of the two
> > > >>>clocks a child of the other, as we did for the sataX and sataXlnk
> > > >>>clocks on Armada XP.
> > > >>
> > > >>Ack for patches #5 and #6.  Do you want me to take them?
> > 
> > Thanks for the Ack!
> > 
> > > >I don't know, I guess with your Ack, it would be easier to carry them
> > > >through the Marvell maintainers and then the arm-soc tree, so that we
> > > >can test arm-soc and have all the pieces needed in here.
> > > >
> > > >That said, Sebastian Hesselbarth has submitted a big rework of the
> > > >mvebu clock drivers, which would conflict with this patch, and
> > > >Sebastian's rework would most likely go through your tree. If that's
> > > >the case, I guess it would be better to let you take #5 and #6 in this
> > > >patch series.
> > > 
> > > I also requested to take the restructure patches through ARM tree. They
> > > are only touching files in drivers/clk/mvebu and by taking them through
> > > ARM, we can update PCIe clock patches easily. The dependency between
> > > Thomas' and my patches basically is that I renamed files that Thomas
> > > now commits to. (I switched clk/mvebu from per-function files to per-soc
> > > files).
> > 
> > I agree.  My heart jumped into my throat a little there :)  Mike, if
> > it's ok with you, I'd prefer to take these through arm-soc.  Any merge
> > conflicts should be minimal.  And at any rate, resolving the conflicts
> > are *much* easier to handle than having arm-soc depend on an outside
> > tree (then Linus has to take care in the order he merges them, no
> > rebasing for clk tree, dogs and cats living together, etc ;-) )
> > 
> 
> Yeah that all sounds good to me.  I'll review the restructure patches
> shortly.

Awesome, thanks.

Jason.


From g.liakhovetski at gmx.de  Fri May 17 09:00:23 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 17 May 2013 15:00:23 +0200 (CEST)
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
Message-ID: <Pine.LNX.4.64.1305171458550.31481@axis700.grange>

Hi Simon, Magnus

On Wed, 3 Apr 2013, Simon Horman wrote:

> From: Magnus Damm <damm at opensource.se>
> 
> Add LAN9220 support to the APE6EVM board using C and DT.
> At this point the PFC driver lacks DT bindings so to
> configure the PFC we use PINCTRL in C board code.
> 
> Signed-off-by: Magnus Damm <damm at opensource.se>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/boot/dts/r8a73a4-ape6evm.dts  |   23 ++++++++++++++++++-
>  arch/arm/mach-shmobile/board-ape6evm.c |   38 ++++++++++++++++++++++++++++++++
>  2 files changed, 60 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> index 833f703..f603c69 100644
> --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> @@ -16,7 +16,7 @@
>  	compatible = "renesas,ape6evm", "renesas,r8a73a4";
>  
>  	chosen {
> -		bootargs = "console=ttySC0,115200 ignore_loglevel";
> +		bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
>  	};
>  
>  	memory at 40000000 {
> @@ -24,8 +24,29 @@
>  		reg = <0 0x40000000 0 0x40000000>;
>  	};
>  
> +	ape6evm_fixed_3v3: fixedregulator at 0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "3V3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +
>  	lbsc {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> +
> +		ethernet at 8000000 {
> +			compatible = "smsc,lan9118", "smsc,lan9115";
> +			reg = <0x08000000 0x1000>;
> +			interrupt-parent = <&irqc1>;
> +			interrupts = <8 0x4>;
> +			phy-mode = "mii";
> +			reg-io-width = <4>;
> +			smsc,irq-active-high;
> +			smsc,irq-push-pull;
> +			vdd33a-supply = <&ape6evm_fixed_3v3>;
> +			vddvario-supply = <&ape6evm_fixed_3v3>;
> +		};
>  	};
>  };

The above didn't work in my tests without this:

diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index f603c69..4fb0102 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -33,8 +33,10 @@
 	};
 
 	lbsc {
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
+		ranges = <0 0 0 0x80000000>;
 
 		ethernet at 8000000 {
 			compatible = "smsc,lan9118", "smsc,lan9115";

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From nicolas.ferre at atmel.com  Fri May 17 09:03:50 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 17 May 2013 15:03:50 +0200
Subject: [PATCH v2] ARM: at91: udpate defconfigs
In-Reply-To: <1368631161-31488-1-git-send-email-plagnioj@jcrosoft.com>
References: <1368631161-31488-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <51962AB6.1080807@atmel.com>

On 15/05/2013 17:19, Jean-Christophe PLAGNIOL-VILLARD :
> merge 9g20 with 9260 and 9g10 with 9261 as those SoCs can run from the same
> kernel even in non DT world
>
> fix the sam9261ek to allow 9g10 and sam9261 to compile together
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

stacked on at91-3.11-cleanup branch.

Bye,

> ---
>   arch/arm/configs/at91_dt_defconfig                 |   55 ++---
>   arch/arm/configs/at91rm9200_defconfig              |  218 +++-----------------
>   ...am9g20_defconfig => at91sam9260_9g20_defconfig} |   67 ++++--
>   arch/arm/configs/at91sam9260_defconfig             |   91 --------
>   ...am9261_defconfig => at91sam9261_9g10_defconfig} |   19 +-
>   arch/arm/configs/at91sam9263_defconfig             |   39 ++--
>   arch/arm/configs/at91sam9g45_defconfig             |   94 +++------
>   arch/arm/configs/sama5_defconfig                   |   35 +++-
>   arch/arm/mach-at91/Kconfig.non_dt                  |  159 +++++++-------
>   arch/arm/mach-at91/Makefile                        |    2 -
>   arch/arm/mach-at91/board-sam9261ek.c               |   28 +--
>   11 files changed, 268 insertions(+), 539 deletions(-)
>   rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
>   delete mode 100644 arch/arm/configs/at91sam9260_defconfig
>   rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)
>
> diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
> index 047f2a4..a8800d3 100644
> --- a/arch/arm/configs/at91_dt_defconfig
> +++ b/arch/arm/configs/at91_dt_defconfig
> @@ -1,4 +1,3 @@
> -CONFIG_EXPERIMENTAL=y
>   # CONFIG_LOCALVERSION_AUTO is not set
>   # CONFIG_SWAP is not set
>   CONFIG_SYSVIPC=y
> @@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
>   CONFIG_AT91_TIMER_HZ=128
>   CONFIG_AEABI=y
>   # CONFIG_OABI_COMPAT is not set
> -CONFIG_LEDS=y
> -CONFIG_LEDS_CPU=y
>   CONFIG_UACCESS_WITH_MEMCPY=y
>   CONFIG_ZBOOT_ROM_TEXT=0x0
>   CONFIG_ZBOOT_ROM_BSS=0x0
> @@ -42,6 +39,9 @@ CONFIG_UNIX=y
>   CONFIG_INET=y
>   CONFIG_IP_MULTICAST=y
>   CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +CONFIG_IP_PNP_RARP=y
>   # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
>   # CONFIG_INET_XFRM_MODE_TUNNEL is not set
>   # CONFIG_INET_XFRM_MODE_BEET is not set
> @@ -51,7 +51,8 @@ CONFIG_IPV6=y
>   # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
>   # CONFIG_INET6_XFRM_MODE_BEET is not set
>   CONFIG_IPV6_SIT_6RD=y
> -# CONFIG_WIRELESS is not set
> +CONFIG_CFG80211=y
> +CONFIG_MAC80211=y
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
>   CONFIG_DEVTMPFS=y
>   CONFIG_DEVTMPFS_MOUNT=y
> @@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
>   CONFIG_BLK_DEV_RAM_SIZE=8192
>   CONFIG_ATMEL_PWM=y
>   CONFIG_ATMEL_TCLIB=y
> -CONFIG_EEPROM_93CX6=m
>   CONFIG_SCSI=y
>   CONFIG_BLK_DEV_SD=y
>   CONFIG_SCSI_MULTI_LUN=y
> @@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y
>   CONFIG_MII=y
>   CONFIG_MACB=y
>   # CONFIG_NET_VENDOR_BROADCOM is not set
> -# CONFIG_NET_VENDOR_CHELSIO is not set
>   # CONFIG_NET_VENDOR_FARADAY is not set
>   # CONFIG_NET_VENDOR_INTEL is not set
>   # CONFIG_NET_VENDOR_MARVELL is not set
> @@ -92,7 +91,23 @@ CONFIG_MACB=y
>   # CONFIG_NET_VENDOR_STMICRO is not set
>   CONFIG_DAVICOM_PHY=y
>   CONFIG_MICREL_PHY=y
> -# CONFIG_WLAN is not set
> +CONFIG_RTL8187=m
> +CONFIG_LIBERTAS=m
> +CONFIG_LIBERTAS_SDIO=m
> +CONFIG_LIBERTAS_SPI=m
> +CONFIG_RT2X00=m
> +CONFIG_RT2500USB=m
> +CONFIG_RT73USB=m
> +CONFIG_RT2800USB=m
> +CONFIG_RT2800USB_RT53XX=y
> +CONFIG_RT2800USB_RT55XX=y
> +CONFIG_RT2800USB_UNKNOWN=y
> +CONFIG_RTLWIFI=m
> +# CONFIG_RTLWIFI_DEBUG is not set
> +CONFIG_RTL8192CU=m
> +CONFIG_MWIFIEX=m
> +CONFIG_MWIFIEX_SDIO=m
> +CONFIG_MWIFIEX_USB=m
>   CONFIG_INPUT_POLLDEV=y
>   # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
>   CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
> @@ -112,13 +127,11 @@ CONFIG_I2C=y
>   CONFIG_I2C_GPIO=y
>   CONFIG_SPI=y
>   CONFIG_SPI_ATMEL=y
> -CONFIG_PINCTRL_AT91=y
>   # CONFIG_HWMON is not set
>   CONFIG_WATCHDOG=y
>   CONFIG_AT91SAM9X_WATCHDOG=y
>   CONFIG_SSB=m
>   CONFIG_FB=y
> -CONFIG_FB_MODE_HELPERS=y
>   CONFIG_FB_ATMEL=y
>   CONFIG_BACKLIGHT_LCD_SUPPORT=y
>   # CONFIG_LCD_CLASS_DEVICE is not set
> @@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y
>   CONFIG_FONT_ACORN_8x8=y
>   CONFIG_FONT_MINI_4x6=y
>   CONFIG_LOGO=y
> -# CONFIG_HID_SUPPORT is not set
>   CONFIG_USB=y
>   CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_OHCI_HCD=y
>   CONFIG_USB_ACM=y
> @@ -146,14 +156,9 @@ CONFIG_USB_SERIAL_GENERIC=y
>   CONFIG_USB_SERIAL_FTDI_SIO=y
>   CONFIG_USB_SERIAL_PL2303=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_AT91=m
> -CONFIG_USB_ATMEL_USBA=m
> -CONFIG_USB_ETH=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_CDC_COMPOSITE=m
> -CONFIG_USB_G_ACM_MS=m
> -CONFIG_USB_G_MULTI=m
> -CONFIG_USB_G_MULTI_CDC=y
> +CONFIG_USB_AT91=y
> +CONFIG_USB_ATMEL_USBA=y
> +CONFIG_USB_G_SERIAL=y
>   CONFIG_MMC=y
>   CONFIG_MMC_ATMELMCI=y
>   CONFIG_NEW_LEDS=y
> @@ -168,16 +173,18 @@ CONFIG_RTC_DRV_AT91RM9200=y
>   CONFIG_RTC_DRV_AT91SAM9=y
>   CONFIG_DMADEVICES=y
>   # CONFIG_IOMMU_SUPPORT is not set
> -CONFIG_EXT2_FS=y
> +CONFIG_EXT4_FS=y
>   CONFIG_FANOTIFY=y
>   CONFIG_VFAT_FS=y
>   CONFIG_TMPFS=y
> +CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
>   CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
>   CONFIG_ROOT_NFS=y
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_CODEPAGE_850=y
>   CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_UTF8=y
>   CONFIG_STRIP_ASM_SYMS=y
>   CONFIG_DEBUG_FS=y
>   # CONFIG_SCHED_DEBUG is not set
> @@ -192,7 +199,7 @@ CONFIG_CRYPTO_ARC4=y
>   CONFIG_CRYPTO_USER_API_HASH=m
>   CONFIG_CRYPTO_USER_API_SKCIPHER=m
>   # CONFIG_CRYPTO_HW is not set
> -CONFIG_CRC_CCITT=m
> -CONFIG_CRC_ITU_T=m
> +CONFIG_CRC_CCITT=y
> +CONFIG_CRC_ITU_T=y
>   CONFIG_CRC7=m
>   CONFIG_AVERAGE=y
> diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
> index 4ae57a3..8b09934 100644
> --- a/arch/arm/configs/at91rm9200_defconfig
> +++ b/arch/arm/configs/at91rm9200_defconfig
> @@ -1,10 +1,12 @@
> -CONFIG_EXPERIMENTAL=y
>   # CONFIG_LOCALVERSION_AUTO is not set
>   # CONFIG_SWAP is not set
>   CONFIG_SYSVIPC=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
>   CONFIG_IKCONFIG=y
>   CONFIG_IKCONFIG_PROC=y
>   CONFIG_LOG_BUF_SHIFT=14
> +CONFIG_USER_NS=y
>   CONFIG_BLK_DEV_INITRD=y
>   CONFIG_MODULES=y
>   CONFIG_MODULE_FORCE_LOAD=y
> @@ -35,49 +37,37 @@ CONFIG_AT91_TIMER_HZ=100
>   # CONFIG_ARM_THUMB is not set
>   CONFIG_PCCARD=y
>   CONFIG_AT91_CF=y
> -CONFIG_NO_HZ=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_PREEMPT=y
>   CONFIG_AEABI=y
> -CONFIG_LEDS=y
> -CONFIG_LEDS_CPU=y
> +# CONFIG_COMPACTION is not set
>   CONFIG_ZBOOT_ROM_TEXT=0x10000000
>   CONFIG_ZBOOT_ROM_BSS=0x20040000
>   CONFIG_KEXEC=y
> +CONFIG_AUTO_ZRELADDR=y
>   CONFIG_FPE_NWFPE=y
>   CONFIG_BINFMT_MISC=y
>   CONFIG_NET=y
>   CONFIG_PACKET=y
>   CONFIG_UNIX=y
> -CONFIG_XFRM_USER=m
>   CONFIG_INET=y
>   CONFIG_IP_MULTICAST=y
>   CONFIG_IP_PNP=y
>   CONFIG_IP_PNP_DHCP=y
>   CONFIG_IP_PNP_BOOTP=y
> -CONFIG_NET_IPIP=m
> -CONFIG_INET_AH=m
> -CONFIG_INET_ESP=m
> -CONFIG_INET_IPCOMP=m
> -CONFIG_INET_XFRM_MODE_TRANSPORT=m
> -CONFIG_INET_XFRM_MODE_TUNNEL=m
> -CONFIG_INET_XFRM_MODE_BEET=m
> +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_DIAG is not set
> +CONFIG_IPV6=y
>   CONFIG_IPV6_PRIVACY=y
>   CONFIG_IPV6_ROUTER_PREF=y
>   CONFIG_IPV6_ROUTE_INFO=y
> -CONFIG_INET6_AH=m
> -CONFIG_INET6_ESP=m
> -CONFIG_INET6_IPCOMP=m
> -CONFIG_IPV6_MIP6=m
> -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
> -CONFIG_IPV6_TUNNEL=m
> -CONFIG_BRIDGE=m
> -CONFIG_VLAN_8021Q=m
> -CONFIG_BT=m
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +# CONFIG_STANDALONE is not set
> +# CONFIG_PREVENT_FIRMWARE_BUILD is not set
>   CONFIG_MTD=y
>   CONFIG_MTD_CMDLINE_PARTS=y
> -CONFIG_MTD_AFS_PARTS=y
>   CONFIG_MTD_CHAR=y
>   CONFIG_MTD_BLOCK=y
>   CONFIG_MTD_CFI=y
> @@ -94,55 +84,21 @@ CONFIG_MTD_NAND_PLATFORM=y
>   CONFIG_MTD_UBI=y
>   CONFIG_MTD_UBI_GLUEBI=y
>   CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_NBD=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_SCSI=y
> -CONFIG_BLK_DEV_SD=y
> -CONFIG_BLK_DEV_SR=m
> -CONFIG_BLK_DEV_SR_VENDOR=y
> -CONFIG_CHR_DEV_SG=m
> -CONFIG_SCSI_MULTI_LUN=y
> -# CONFIG_SCSI_LOWLEVEL is not set
>   CONFIG_NETDEVICES=y
> -CONFIG_TUN=m
> +CONFIG_MII=y
>   CONFIG_ARM_AT91_ETHER=y
> -CONFIG_PHYLIB=y
>   CONFIG_DAVICOM_PHY=y
>   CONFIG_SMSC_PHY=y
>   CONFIG_MICREL_PHY=y
> -CONFIG_PPP=y
> -CONFIG_PPP_BSDCOMP=y
> -CONFIG_PPP_DEFLATE=y
> -CONFIG_PPP_FILTER=y
> -CONFIG_PPP_MPPE=m
> -CONFIG_PPP_MULTILINK=y
> -CONFIG_PPPOE=m
> -CONFIG_PPP_ASYNC=y
> -CONFIG_SLIP=m
> -CONFIG_SLIP_COMPRESSED=y
> -CONFIG_SLIP_SMART=y
> -CONFIG_SLIP_MODE_SLIP6=y
> -CONFIG_USB_CATC=m
> -CONFIG_USB_KAWETH=m
> -CONFIG_USB_PEGASUS=m
> -CONFIG_USB_RTL8150=m
> -CONFIG_USB_USBNET=m
> -CONFIG_USB_NET_DM9601=m
> -CONFIG_USB_NET_GL620A=m
> -CONFIG_USB_NET_PLUSB=m
> -CONFIG_USB_NET_RNDIS_HOST=m
> -CONFIG_USB_ALI_M5632=y
> -CONFIG_USB_AN2720=y
> -CONFIG_USB_EPSON2888=y
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
> +# CONFIG_WLAN is not set
> +# CONFIG_INPUT_MOUSEDEV is not set
>   CONFIG_INPUT_EVDEV=y
>   CONFIG_KEYBOARD_GPIO=y
>   # CONFIG_INPUT_MOUSE is not set
>   CONFIG_INPUT_TOUCHSCREEN=y
> -CONFIG_LEGACY_PTY_COUNT=32
> +# CONFIG_LEGACY_PTYS is not set
>   CONFIG_SERIAL_ATMEL=y
>   CONFIG_SERIAL_ATMEL_CONSOLE=y
>   CONFIG_HW_RANDOM=y
> @@ -151,38 +107,8 @@ CONFIG_I2C_CHARDEV=y
>   CONFIG_I2C_GPIO=y
>   CONFIG_SPI=y
>   CONFIG_SPI_ATMEL=y
> -CONFIG_SPI_BITBANG=y
>   CONFIG_GPIO_SYSFS=y
> -CONFIG_HWMON=m
> -CONFIG_SENSORS_ADM1021=m
> -CONFIG_SENSORS_ADM1025=m
> -CONFIG_SENSORS_ADM1026=m
> -CONFIG_SENSORS_ADM1029=m
> -CONFIG_SENSORS_ADM1031=m
> -CONFIG_SENSORS_ADM9240=m
> -CONFIG_SENSORS_DS1621=m
> -CONFIG_SENSORS_GL518SM=m
> -CONFIG_SENSORS_GL520SM=m
> -CONFIG_SENSORS_IT87=m
> -CONFIG_SENSORS_LM63=m
> -CONFIG_SENSORS_LM73=m
> -CONFIG_SENSORS_LM75=m
> -CONFIG_SENSORS_LM77=m
> -CONFIG_SENSORS_LM78=m
> -CONFIG_SENSORS_LM80=m
> -CONFIG_SENSORS_LM83=m
> -CONFIG_SENSORS_LM85=m
> -CONFIG_SENSORS_LM87=m
> -CONFIG_SENSORS_LM90=m
> -CONFIG_SENSORS_LM92=m
> -CONFIG_SENSORS_MAX1619=m
> -CONFIG_SENSORS_PCF8591=m
> -CONFIG_SENSORS_SMSC47B397=m
> -CONFIG_SENSORS_W83781D=m
> -CONFIG_SENSORS_W83791D=m
> -CONFIG_SENSORS_W83792D=m
> -CONFIG_SENSORS_W83793=m
> -CONFIG_SENSORS_W83L785TS=m
> +# CONFIG_HWMON is not set
>   CONFIG_WATCHDOG=y
>   CONFIG_WATCHDOG_NOWAYOUT=y
>   CONFIG_AT91RM9200_WATCHDOG=y
> @@ -194,43 +120,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
>   CONFIG_LCD_CLASS_DEVICE=y
>   CONFIG_BACKLIGHT_CLASS_DEVICE=y
>   # CONFIG_BACKLIGHT_GENERIC is not set
> -CONFIG_DISPLAY_SUPPORT=y
>   CONFIG_FRAMEBUFFER_CONSOLE=y
>   CONFIG_FONTS=y
> -CONFIG_FONT_MINI_4x6=y
>   CONFIG_LOGO=y
> -# CONFIG_LOGO_LINUX_MONO is not set
> -# CONFIG_LOGO_LINUX_VGA16 is not set
>   CONFIG_USB=y
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
> -CONFIG_USB_MON=y
>   CONFIG_USB_OHCI_HCD=y
> -CONFIG_USB_ACM=m
> -CONFIG_USB_PRINTER=m
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_SERIAL=y
> -CONFIG_USB_SERIAL_CONSOLE=y
> -CONFIG_USB_SERIAL_GENERIC=y
> -CONFIG_USB_SERIAL_FTDI_SIO=y
> -CONFIG_USB_SERIAL_KEYSPAN=y
> -CONFIG_USB_SERIAL_KEYSPAN_MPR=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA28=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA19=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
> -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
> -CONFIG_USB_SERIAL_MCT_U232=y
> -CONFIG_USB_SERIAL_PL2303=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_ETH=m
> -CONFIG_USB_MASS_STORAGE=m
> +CONFIG_USB_AT91=y
> +CONFIG_USB_G_SERIAL=y
>   CONFIG_MMC=y
>   CONFIG_MMC_ATMELMCI=y
>   CONFIG_NEW_LEDS=y
> @@ -240,84 +137,27 @@ CONFIG_LEDS_TRIGGERS=y
>   CONFIG_LEDS_TRIGGER_TIMER=y
>   CONFIG_LEDS_TRIGGER_HEARTBEAT=y
>   CONFIG_LEDS_TRIGGER_GPIO=y
> -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
>   CONFIG_RTC_CLASS=y
> -# CONFIG_RTC_HCTOSYS is not set
> -CONFIG_RTC_DRV_DS1307=y
> -CONFIG_RTC_DRV_PCF8563=y
>   CONFIG_RTC_DRV_AT91RM9200=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT2_FS_XATTR=y
> -CONFIG_EXT3_FS=y
> -# CONFIG_EXT3_FS_XATTR is not set
> -CONFIG_REISERFS_FS=y
> +CONFIG_EXT4_FS=y
>   CONFIG_AUTOFS4_FS=y
> -CONFIG_ISO9660_FS=y
> -CONFIG_JOLIET=y
> -CONFIG_ZISOFS=y
> -CONFIG_UDF_FS=y
> -CONFIG_MSDOS_FS=y
>   CONFIG_VFAT_FS=y
> -CONFIG_NTFS_FS=m
>   CONFIG_TMPFS=y
> -CONFIG_CONFIGFS_FS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_SUMMARY=y
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_LZO=y
> -CONFIG_JFFS2_RUBIN=y
> -CONFIG_CRAMFS=y
> -CONFIG_MINIX_FS=y
> +CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
>   CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -CONFIG_NFS_V3_ACL=y
> -CONFIG_NFS_V4=y
>   CONFIG_ROOT_NFS=y
> -CONFIG_NFSD=y
> -CONFIG_CIFS=m
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_MAC_PARTITION=y
>   CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_CODEPAGE_737=m
> -CONFIG_NLS_CODEPAGE_775=m
> -CONFIG_NLS_CODEPAGE_850=m
> -CONFIG_NLS_CODEPAGE_852=m
> -CONFIG_NLS_CODEPAGE_855=m
> -CONFIG_NLS_CODEPAGE_857=m
> -CONFIG_NLS_CODEPAGE_860=m
> -CONFIG_NLS_CODEPAGE_861=m
> -CONFIG_NLS_CODEPAGE_862=m
> -CONFIG_NLS_CODEPAGE_863=m
> -CONFIG_NLS_CODEPAGE_864=m
> -CONFIG_NLS_CODEPAGE_865=m
> -CONFIG_NLS_CODEPAGE_866=m
> -CONFIG_NLS_CODEPAGE_869=m
> -CONFIG_NLS_CODEPAGE_936=m
> -CONFIG_NLS_CODEPAGE_950=m
> -CONFIG_NLS_CODEPAGE_932=m
> -CONFIG_NLS_CODEPAGE_949=m
> -CONFIG_NLS_CODEPAGE_874=m
> -CONFIG_NLS_ISO8859_8=m
> -CONFIG_NLS_CODEPAGE_1250=m
> -CONFIG_NLS_CODEPAGE_1251=m
> -CONFIG_NLS_ASCII=m
> +CONFIG_NLS_CODEPAGE_850=y
>   CONFIG_NLS_ISO8859_1=y
> -CONFIG_NLS_ISO8859_2=m
> -CONFIG_NLS_ISO8859_3=m
> -CONFIG_NLS_ISO8859_4=m
> -CONFIG_NLS_ISO8859_5=m
> -CONFIG_NLS_ISO8859_6=m
> -CONFIG_NLS_ISO8859_7=m
> -CONFIG_NLS_ISO8859_9=m
> -CONFIG_NLS_ISO8859_13=m
> -CONFIG_NLS_ISO8859_14=m
> -CONFIG_NLS_ISO8859_15=m
> -CONFIG_NLS_KOI8_R=m
> -CONFIG_NLS_KOI8_U=m
>   CONFIG_NLS_UTF8=y
>   CONFIG_MAGIC_SYSRQ=y
>   CONFIG_DEBUG_FS=y
>   CONFIG_DEBUG_KERNEL=y
>   # CONFIG_FTRACE is not set
> +CONFIG_DEBUG_USER=y
> +CONFIG_DEBUG_LL=y
> +CONFIG_EARLY_PRINTK=y
>   CONFIG_CRYPTO_PCBC=y
>   CONFIG_CRYPTO_SHA1=y
> +CONFIG_XZ_DEC_ARMTHUMB=y
> diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
> similarity index 67%
> rename from arch/arm/configs/at91sam9g20_defconfig
> rename to arch/arm/configs/at91sam9260_9g20_defconfig
> index 892e828..f50c404 100644
> --- a/arch/arm/configs/at91sam9g20_defconfig
> +++ b/arch/arm/configs/at91sam9260_9g20_defconfig
> @@ -1,4 +1,3 @@
> -CONFIG_EXPERIMENTAL=y
>   # CONFIG_LOCALVERSION_AUTO is not set
>   # CONFIG_SWAP is not set
>   CONFIG_SYSVIPC=y
> @@ -11,7 +10,15 @@ CONFIG_MODULE_UNLOAD=y
>   # CONFIG_IOSCHED_DEADLINE is not set
>   # CONFIG_IOSCHED_CFQ is not set
>   CONFIG_ARCH_AT91=y
> -CONFIG_ARCH_AT91SAM9G20=y
> +CONFIG_ARCH_AT91SAM9260=y
> +CONFIG_MACH_AT91SAM9260EK=y
> +CONFIG_MACH_CAM60=y
> +CONFIG_MACH_SAM9_L9260=y
> +CONFIG_MACH_AFEB9260=y
> +CONFIG_MACH_USB_A9260=y
> +CONFIG_MACH_QIL_A9260=y
> +CONFIG_MACH_CPU9260=y
> +CONFIG_MACH_FLEXIBITY=y
>   CONFIG_MACH_AT91SAM9G20EK=y
>   CONFIG_MACH_AT91SAM9G20EK_2MMC=y
>   CONFIG_MACH_CPU9G20=y
> @@ -20,10 +27,10 @@ CONFIG_MACH_PORTUXG20=y
>   CONFIG_MACH_STAMP9G20=y
>   CONFIG_MACH_PCONTROL_G20=y
>   CONFIG_MACH_GSIA18S=y
> -CONFIG_MACH_USB_A9G20=y
>   CONFIG_MACH_SNAPPER_9260=y
>   CONFIG_MACH_AT91SAM9_DT=y
>   CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
> +CONFIG_AT91_SLOW_CLOCK=y
>   # CONFIG_ARM_THUMB is not set
>   CONFIG_AEABI=y
>   CONFIG_LEDS=y
> @@ -33,12 +40,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0
>   CONFIG_ARM_APPENDED_DTB=y
>   CONFIG_ARM_ATAG_DTB_COMPAT=y
>   CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
> +CONFIG_AUTO_ZRELADDR=y
>   CONFIG_FPE_NWFPE=y
>   CONFIG_NET=y
>   CONFIG_PACKET=y
>   CONFIG_UNIX=y
>   CONFIG_INET=y
>   CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
>   CONFIG_IP_PNP_BOOTP=y
>   # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
>   # CONFIG_INET_XFRM_MODE_TUNNEL is not set
> @@ -46,8 +55,11 @@ CONFIG_IP_PNP_BOOTP=y
>   # CONFIG_INET_LRO is not set
>   # CONFIG_IPV6 is not set
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
>   CONFIG_MTD=y
>   CONFIG_MTD_CMDLINE_PARTS=y
> +CONFIG_MTD_OF_PARTS=y
>   CONFIG_MTD_CHAR=y
>   CONFIG_MTD_BLOCK=y
>   CONFIG_MTD_DATAFLASH=y
> @@ -56,6 +68,8 @@ CONFIG_MTD_NAND_ATMEL=y
>   CONFIG_BLK_DEV_LOOP=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_SIZE=8192
> +CONFIG_MISC_DEVICES=y
> +CONFIG_EEPROM_AT25=y
>   CONFIG_SCSI=y
>   CONFIG_BLK_DEV_SD=y
>   CONFIG_SCSI_MULTI_LUN=y
> @@ -63,23 +77,36 @@ CONFIG_SCSI_MULTI_LUN=y
>   CONFIG_NETDEVICES=y
>   CONFIG_MII=y
>   CONFIG_MACB=y
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_CHELSIO is not set
> +# CONFIG_NET_VENDOR_FARADAY is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_MICROCHIP is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +# CONFIG_NET_VENDOR_STMICRO is not set
> +CONFIG_SMSC_PHY=y
>   # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_KEYBOARD_ATKBD is not set
>   CONFIG_KEYBOARD_GPIO=y
>   # CONFIG_INPUT_MOUSE is not set
> -CONFIG_LEGACY_PTY_COUNT=16
> +# CONFIG_SERIO is not set
>   CONFIG_SERIAL_ATMEL=y
>   CONFIG_SERIAL_ATMEL_CONSOLE=y
>   CONFIG_HW_RANDOM=y
>   CONFIG_I2C=y
> +CONFIG_I2C_CHARDEV=y
>   CONFIG_I2C_GPIO=y
>   CONFIG_SPI=y
>   CONFIG_SPI_ATMEL=y
>   CONFIG_SPI_SPIDEV=y
> +CONFIG_GPIO_SYSFS=y
>   # CONFIG_HWMON is not set
> +CONFIG_WATCHDOG=y
> +CONFIG_WATCHDOG_NOWAYOUT=y
> +CONFIG_AT91SAM9X_WATCHDOG=y
>   CONFIG_SOUND=y
>   CONFIG_SND=y
>   CONFIG_SND_SEQUENCER=y
> @@ -94,12 +121,11 @@ CONFIG_USB_MON=y
>   CONFIG_USB_OHCI_HCD=y
>   CONFIG_USB_STORAGE=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
> +CONFIG_USB_AT91=y
> +CONFIG_USB_G_SERIAL=y
>   CONFIG_MMC=y
> -CONFIG_MMC_ATMELMCI=m
> +CONFIG_MMC_ATMELMCI=y
> +CONFIG_MMC_SPI=y
>   CONFIG_NEW_LEDS=y
>   CONFIG_LEDS_CLASS=y
>   CONFIG_LEDS_GPIO=y
> @@ -109,15 +135,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
>   CONFIG_RTC_CLASS=y
>   CONFIG_RTC_DRV_RV3029C2=y
>   CONFIG_RTC_DRV_AT91SAM9=y
> -CONFIG_EXT2_FS=y
> -CONFIG_MSDOS_FS=y
> +CONFIG_EXT4_FS=y
>   CONFIG_VFAT_FS=y
>   CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_SUMMARY=y
> -CONFIG_CRAMFS=y
> +CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
>   CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
>   CONFIG_ROOT_NFS=y
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_CODEPAGE_850=y
> @@ -125,3 +148,9 @@ CONFIG_NLS_ISO8859_1=y
>   CONFIG_NLS_ISO8859_15=y
>   CONFIG_NLS_UTF8=y
>   # CONFIG_ENABLE_WARN_DEPRECATED is not set
> +CONFIG_DEBUG_KERNEL=y
> +CONFIG_DEBUG_INFO=y
> +# CONFIG_FTRACE is not set
> +CONFIG_DEBUG_LL=y
> +CONFIG_AT91_DEBUG_LL_DBGU0=y
> +CONFIG_EARLY_PRINTK=y
> diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
> deleted file mode 100644
> index 05618eb..0000000
> --- a/arch/arm/configs/at91sam9260_defconfig
> +++ /dev/null
> @@ -1,91 +0,0 @@
> -CONFIG_EXPERIMENTAL=y
> -# CONFIG_LOCALVERSION_AUTO is not set
> -# CONFIG_SWAP is not set
> -CONFIG_SYSVIPC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_SLAB=y
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_IOSCHED_DEADLINE is not set
> -# CONFIG_IOSCHED_CFQ is not set
> -CONFIG_ARCH_AT91=y
> -CONFIG_ARCH_AT91SAM9260=y
> -CONFIG_ARCH_AT91SAM9260_SAM9XE=y
> -CONFIG_MACH_AT91SAM9260EK=y
> -CONFIG_MACH_CAM60=y
> -CONFIG_MACH_SAM9_L9260=y
> -CONFIG_MACH_AFEB9260=y
> -CONFIG_MACH_USB_A9260=y
> -CONFIG_MACH_QIL_A9260=y
> -CONFIG_MACH_CPU9260=y
> -CONFIG_MACH_FLEXIBITY=y
> -CONFIG_MACH_SNAPPER_9260=y
> -CONFIG_MACH_AT91SAM9_DT=y
> -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
> -# CONFIG_ARM_THUMB is not set
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_ARM_APPENDED_DTB=y
> -CONFIG_ARM_ATAG_DTB_COMPAT=y
> -CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
> -CONFIG_FPE_NWFPE=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_INET=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_IPV6 is not set
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_SCSI=y
> -CONFIG_BLK_DEV_SD=y
> -CONFIG_SCSI_MULTI_LUN=y
> -CONFIG_NETDEVICES=y
> -CONFIG_MII=y
> -CONFIG_MACB=y
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -CONFIG_SERIAL_ATMEL=y
> -CONFIG_SERIAL_ATMEL_CONSOLE=y
> -# CONFIG_HW_RANDOM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_GPIO=y
> -# CONFIG_HWMON is not set
> -CONFIG_WATCHDOG=y
> -CONFIG_WATCHDOG_NOWAYOUT=y
> -CONFIG_AT91SAM9X_WATCHDOG=y
> -# CONFIG_USB_HID is not set
> -CONFIG_USB=y
> -CONFIG_USB_DEVICEFS=y
> -CONFIG_USB_MON=y
> -CONFIG_USB_OHCI_HCD=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_STORAGE_DEBUG=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_AT91SAM9=y
> -CONFIG_EXT2_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_CRAMFS=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_CODEPAGE_850=y
> -CONFIG_NLS_ISO8859_1=y
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_LL=y
> diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
> similarity index 91%
> rename from arch/arm/configs/at91sam9261_defconfig
> rename to arch/arm/configs/at91sam9261_9g10_defconfig
> index c87beb9..9d35cd8 100644
> --- a/arch/arm/configs/at91sam9261_defconfig
> +++ b/arch/arm/configs/at91sam9261_9g10_defconfig
> @@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
>   CONFIG_ARCH_AT91=y
>   CONFIG_ARCH_AT91SAM9261=y
>   CONFIG_MACH_AT91SAM9261EK=y
> +CONFIG_MACH_AT91SAM9G10EK=y
>   CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
>   # CONFIG_ARM_THUMB is not set
>   CONFIG_AEABI=y
> @@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y
>   # CONFIG_INET_LRO is not set
>   # CONFIG_IPV6 is not set
>   CONFIG_CFG80211=y
> -CONFIG_LIB80211=y
>   CONFIG_MAC80211=y
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
>   CONFIG_MTD=y
> -CONFIG_MTD_PARTITIONS=y
>   CONFIG_MTD_CMDLINE_PARTS=y
>   CONFIG_MTD_BLOCK=y
>   CONFIG_MTD_NAND=y
> @@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y
>   CONFIG_MTD_UBI_GLUEBI=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_MISC_DEVICES=y
>   CONFIG_ATMEL_TCLIB=y
>   CONFIG_ATMEL_SSC=y
>   CONFIG_SCSI=y
>   CONFIG_BLK_DEV_SD=y
>   CONFIG_SCSI_MULTI_LUN=y
>   CONFIG_NETDEVICES=y
> -CONFIG_NET_ETHERNET=y
>   CONFIG_DM9000=y
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
>   CONFIG_USB_ZD1201=m
>   CONFIG_RTL8187=m
>   CONFIG_LIBERTAS=m
> @@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y
>   CONFIG_SND_USB_AUDIO=m
>   # CONFIG_USB_HID is not set
>   CONFIG_USB=y
> -CONFIG_USB_DEVICEFS=y
>   CONFIG_USB_OHCI_HCD=y
>   CONFIG_USB_STORAGE=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_ETH=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
> +CONFIG_USB_AT91=y
> +CONFIG_USB_G_SERIAL=y
>   CONFIG_MMC=y
>   CONFIG_MMC_ATMELMCI=m
>   CONFIG_NEW_LEDS=y
> @@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y
>   CONFIG_SQUASHFS_LZO=y
>   CONFIG_SQUASHFS_XZ=y
>   CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
>   CONFIG_ROOT_NFS=y
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_CODEPAGE_850=y
>   CONFIG_NLS_ISO8859_1=y
>   CONFIG_NLS_ISO8859_15=y
>   CONFIG_NLS_UTF8=y
> -CONFIG_FTRACE=y
>   CONFIG_CRC_CCITT=m
> diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
> index 36fed66b..9d72ab6 100644
> --- a/arch/arm/configs/at91sam9263_defconfig
> +++ b/arch/arm/configs/at91sam9263_defconfig
> @@ -1,6 +1,4 @@
> -CONFIG_EXPERIMENTAL=y
>   # CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_KERNEL_LZMA=y
>   # CONFIG_SWAP is not set
>   CONFIG_SYSVIPC=y
>   CONFIG_IKCONFIG=y
> @@ -48,9 +46,11 @@ CONFIG_IP_PIMSM_V2=y
>   # CONFIG_INET_LRO is not set
>   # CONFIG_INET_DIAG is not set
>   CONFIG_IPV6=y
> +# CONFIG_WIRELESS is not set
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
>   CONFIG_MTD=y
> -CONFIG_MTD_PARTITIONS=y
>   CONFIG_MTD_CMDLINE_PARTS=y
>   CONFIG_MTD_CHAR=y
>   CONFIG_MTD_BLOCK=y
> @@ -65,7 +65,6 @@ CONFIG_MTD_UBI_GLUEBI=y
>   CONFIG_BLK_DEV_LOOP=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_MISC_DEVICES=y
>   CONFIG_ATMEL_PWM=y
>   CONFIG_ATMEL_TCLIB=y
>   CONFIG_SCSI=y
> @@ -73,23 +72,18 @@ CONFIG_BLK_DEV_SD=y
>   CONFIG_SCSI_MULTI_LUN=y
>   CONFIG_NETDEVICES=y
>   CONFIG_MII=y
> -CONFIG_SMSC_PHY=y
> -CONFIG_NET_ETHERNET=y
>   CONFIG_MACB=y
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -CONFIG_USB_ZD1201=m
> +CONFIG_SMSC_PHY=y
> +# CONFIG_WLAN is not set
>   CONFIG_INPUT_POLLDEV=m
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
> +# CONFIG_INPUT_MOUSEDEV is not set
>   CONFIG_INPUT_EVDEV=y
>   # CONFIG_KEYBOARD_ATKBD is not set
>   CONFIG_KEYBOARD_GPIO=y
>   # CONFIG_INPUT_MOUSE is not set
>   CONFIG_INPUT_TOUCHSCREEN=y
>   CONFIG_TOUCHSCREEN_ADS7846=y
> -CONFIG_LEGACY_PTY_COUNT=4
> +# CONFIG_LEGACY_PTYS is not set
>   CONFIG_SERIAL_ATMEL=y
>   CONFIG_SERIAL_ATMEL_CONSOLE=y
>   CONFIG_HW_RANDOM=y
> @@ -98,6 +92,7 @@ CONFIG_I2C_CHARDEV=y
>   CONFIG_I2C_GPIO=y
>   CONFIG_SPI=y
>   CONFIG_SPI_ATMEL=y
> +CONFIG_GPIO_SYSFS=y
>   # CONFIG_HWMON is not set
>   CONFIG_WATCHDOG=y
>   CONFIG_WATCHDOG_NOWAYOUT=y
> @@ -107,9 +102,9 @@ CONFIG_FB_ATMEL=y
>   CONFIG_BACKLIGHT_LCD_SUPPORT=y
>   CONFIG_LCD_CLASS_DEVICE=y
>   CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -CONFIG_BACKLIGHT_ATMEL_LCDC=y
>   CONFIG_FRAMEBUFFER_CONSOLE=y
>   CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
> +CONFIG_FONTS=y
>   CONFIG_LOGO=y
>   CONFIG_SOUND=y
>   CONFIG_SND=y
> @@ -124,16 +119,12 @@ CONFIG_SND_ATMEL_AC97C=y
>   # CONFIG_SND_SPI is not set
>   CONFIG_SND_USB_AUDIO=m
>   CONFIG_USB=y
> -CONFIG_USB_DEVICEFS=y
>   CONFIG_USB_MON=y
>   CONFIG_USB_OHCI_HCD=y
>   CONFIG_USB_STORAGE=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_ETH=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
> +CONFIG_USB_ATMEL_USBA=y
> +CONFIG_USB_G_SERIAL=y
>   CONFIG_MMC=y
>   CONFIG_SDIO_UART=m
>   CONFIG_MMC_ATMELMCI=m
> @@ -145,22 +136,18 @@ CONFIG_LEDS_TRIGGERS=y
>   CONFIG_LEDS_TRIGGER_HEARTBEAT=y
>   CONFIG_RTC_CLASS=y
>   CONFIG_RTC_DRV_AT91SAM9=y
> -CONFIG_EXT2_FS=y
> -CONFIG_FUSE_FS=m
> +CONFIG_EXT4_FS=y
>   CONFIG_VFAT_FS=y
>   CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
>   CONFIG_UBIFS_FS=y
>   CONFIG_UBIFS_FS_ADVANCED_COMPR=y
> -CONFIG_CRAMFS=y
>   CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
>   CONFIG_NFS_V3_ACL=y
>   CONFIG_NFS_V4=y
>   CONFIG_ROOT_NFS=y
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_CODEPAGE_850=y
>   CONFIG_NLS_ISO8859_1=y
> -CONFIG_FTRACE=y
> +CONFIG_NLS_UTF8=y
>   CONFIG_DEBUG_USER=y
>   CONFIG_XZ_DEC=y
> diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
> index 18964cd..08166cd 100644
> --- a/arch/arm/configs/at91sam9g45_defconfig
> +++ b/arch/arm/configs/at91sam9g45_defconfig
> @@ -1,4 +1,3 @@
> -CONFIG_EXPERIMENTAL=y
>   # CONFIG_LOCALVERSION_AUTO is not set
>   # CONFIG_SWAP is not set
>   CONFIG_SYSVIPC=y
> @@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
>   CONFIG_AT91_SLOW_CLOCK=y
>   CONFIG_AEABI=y
>   # CONFIG_OABI_COMPAT is not set
> -CONFIG_LEDS=y
> -CONFIG_LEDS_CPU=y
>   CONFIG_UACCESS_WITH_MEMCPY=y
>   CONFIG_ZBOOT_ROM_TEXT=0x0
>   CONFIG_ZBOOT_ROM_BSS=0x0
> @@ -36,6 +33,9 @@ CONFIG_PACKET=y
>   CONFIG_UNIX=y
>   CONFIG_INET=y
>   CONFIG_IP_MULTICAST=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
>   # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
>   # CONFIG_INET_XFRM_MODE_TUNNEL is not set
>   # CONFIG_INET_XFRM_MODE_BEET is not set
> @@ -45,9 +45,6 @@ CONFIG_IPV6=y
>   # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
>   # CONFIG_INET6_XFRM_MODE_BEET is not set
>   CONFIG_IPV6_SIT_6RD=y
> -CONFIG_CFG80211=y
> -CONFIG_LIB80211=y
> -CONFIG_MAC80211=y
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
>   CONFIG_DEVTMPFS=y
>   CONFIG_DEVTMPFS_MOUNT=y
> @@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y
>   CONFIG_MTD_NAND=y
>   CONFIG_MTD_NAND_ATMEL=y
>   CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_GLUEBI=y
>   CONFIG_BLK_DEV_LOOP=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_COUNT=4
>   CONFIG_BLK_DEV_RAM_SIZE=8192
> -CONFIG_MISC_DEVICES=y
>   CONFIG_ATMEL_PWM=y
>   CONFIG_ATMEL_TCLIB=y
> +CONFIG_ATMEL_SSC=y
>   CONFIG_SCSI=y
>   CONFIG_BLK_DEV_SD=y
>   CONFIG_SCSI_MULTI_LUN=y
> @@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y
>   CONFIG_MII=y
>   CONFIG_MACB=y
>   CONFIG_DAVICOM_PHY=y
> -CONFIG_LIBERTAS_THINFIRM=m
> -CONFIG_LIBERTAS_THINFIRM_USB=m
> -CONFIG_AT76C50X_USB=m
> -CONFIG_USB_ZD1201=m
> -CONFIG_RTL8187=m
> -CONFIG_ATH_COMMON=m
> -CONFIG_ATH9K=m
> -CONFIG_CARL9170=m
> -CONFIG_B43=m
> -CONFIG_B43_PHY_N=y
> -CONFIG_LIBERTAS=m
> -CONFIG_LIBERTAS_USB=m
> -CONFIG_LIBERTAS_SDIO=m
> -CONFIG_LIBERTAS_SPI=m
> -CONFIG_RT2X00=m
> -CONFIG_RT2500USB=m
> -CONFIG_RT73USB=m
> -CONFIG_RT2800USB=m
> -CONFIG_RT2800USB_RT53XX=y
> -CONFIG_RT2800USB_UNKNOWN=y
> -CONFIG_RTL8192CU=m
> -CONFIG_WL1251=m
> -CONFIG_WL1251_SDIO=m
> -CONFIG_WL12XX_MENU=m
> -CONFIG_WL12XX=m
> -CONFIG_WL12XX_SDIO=m
> -CONFIG_ZD1211RW=m
> -CONFIG_MWIFIEX=m
> -CONFIG_MWIFIEX_SDIO=m
> -CONFIG_INPUT_POLLDEV=m
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
> +# CONFIG_INPUT_MOUSEDEV is not set
>   CONFIG_INPUT_JOYDEV=y
>   CONFIG_INPUT_EVDEV=y
>   # CONFIG_KEYBOARD_ATKBD is not set
> -CONFIG_KEYBOARD_QT1070=m
> -CONFIG_KEYBOARD_QT2160=m
> +CONFIG_KEYBOARD_QT1070=y
> +CONFIG_KEYBOARD_QT2160=y
>   CONFIG_KEYBOARD_GPIO=y
>   # CONFIG_INPUT_MOUSE is not set
>   CONFIG_INPUT_TOUCHSCREEN=y
>   CONFIG_TOUCHSCREEN_ATMEL_MXT=m
>   CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
>   # CONFIG_SERIO is not set
> -CONFIG_LEGACY_PTY_COUNT=4
> +# CONFIG_LEGACY_PTYS is not set
>   CONFIG_SERIAL_ATMEL=y
>   CONFIG_SERIAL_ATMEL_CONSOLE=y
>   CONFIG_HW_RANDOM=y
>   CONFIG_I2C=y
> +CONFIG_I2C_CHARDEV=y
>   CONFIG_I2C_GPIO=y
>   CONFIG_SPI=y
>   CONFIG_SPI_ATMEL=y
>   # CONFIG_HWMON is not set
>   CONFIG_FB=y
>   CONFIG_FB_ATMEL=y
> -CONFIG_FB_UDL=m
>   CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -# CONFIG_LCD_CLASS_DEVICE is not set
> +CONFIG_LCD_CLASS_DEVICE=y
>   CONFIG_BACKLIGHT_CLASS_DEVICE=y
>   CONFIG_BACKLIGHT_ATMEL_LCDC=y
> +CONFIG_BACKLIGHT_ATMEL_PWM=y
>   # CONFIG_BACKLIGHT_GENERIC is not set
> +CONFIG_FRAMEBUFFER_CONSOLE=y
> +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
> +CONFIG_FONTS=y
> +CONFIG_LOGO=y
>   CONFIG_SOUND=y
>   CONFIG_SND=y
>   CONFIG_SND_SEQUENCER=y
> @@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y
>   # CONFIG_SND_ARM is not set
>   CONFIG_SND_ATMEL_AC97C=y
>   # CONFIG_SND_SPI is not set
> -CONFIG_SND_USB_AUDIO=m
> +# CONFIG_SND_USB is not set
>   # CONFIG_USB_HID is not set
>   CONFIG_USB=y
>   CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_OHCI_HCD=y
>   CONFIG_USB_ACM=y
>   CONFIG_USB_STORAGE=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_ATMEL_USBA=m
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_AUDIO=m
> -CONFIG_USB_ETH=m
> -CONFIG_USB_ETH_EEM=y
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
> -CONFIG_USB_CDC_COMPOSITE=m
> -CONFIG_USB_G_MULTI=m
> +CONFIG_USB_ATMEL_USBA=y
> +CONFIG_USB_G_MULTI=y
>   CONFIG_USB_G_MULTI_CDC=y
>   CONFIG_MMC=y
>   # CONFIG_MMC_BLOCK_BOUNCE is not set
> -CONFIG_SDIO_UART=m
>   CONFIG_MMC_ATMELMCI=y
> -CONFIG_LEDS_ATMEL_PWM=y
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=y
>   CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_TRIGGERS=y
>   CONFIG_LEDS_TRIGGER_TIMER=y
>   CONFIG_LEDS_TRIGGER_HEARTBEAT=y
>   CONFIG_LEDS_TRIGGER_GPIO=y
> @@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y
>   CONFIG_AT_HDMAC=y
>   CONFIG_DMATEST=m
>   # CONFIG_IOMMU_SUPPORT is not set
> -CONFIG_EXT2_FS=y
> +CONFIG_EXT4_FS=y
>   CONFIG_FANOTIFY=y
>   CONFIG_VFAT_FS=y
>   CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_SUMMARY=y
> -CONFIG_CRAMFS=m
> -CONFIG_SQUASHFS=m
> -CONFIG_SQUASHFS_EMBEDDED=y
> +CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
>   CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> +CONFIG_ROOT_NFS=y
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_CODEPAGE_850=y
>   CONFIG_NLS_ISO8859_1=y
> @@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y
>   CONFIG_DEBUG_MEMORY_INIT=y
>   # CONFIG_FTRACE is not set
>   CONFIG_DEBUG_USER=y
> +CONFIG_DEBUG_LL=y
> +CONFIG_EARLY_PRINTK=y
>   CONFIG_CRYPTO_ECB=y
>   # CONFIG_CRYPTO_ANSI_CPRNG is not set
>   CONFIG_CRYPTO_USER_API_HASH=m
> diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
> index 4d0dc3c..f6e78f8 100644
> --- a/arch/arm/configs/sama5_defconfig
> +++ b/arch/arm/configs/sama5_defconfig
> @@ -26,7 +26,9 @@ CONFIG_AEABI=y
>   CONFIG_UACCESS_WITH_MEMCPY=y
>   CONFIG_ZBOOT_ROM_TEXT=0x0
>   CONFIG_ZBOOT_ROM_BSS=0x0
> +CONFIG_ARM_APPENDED_DTB=y
>   CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
> +CONFIG_KEXEC=y
>   CONFIG_AUTO_ZRELADDR=y
>   CONFIG_VFP=y
>   # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> @@ -39,6 +41,9 @@ CONFIG_UNIX=y
>   CONFIG_INET=y
>   CONFIG_IP_MULTICAST=y
>   CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +CONFIG_IP_PNP_RARP=y
>   # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
>   # CONFIG_INET_XFRM_MODE_TUNNEL is not set
>   # CONFIG_INET_XFRM_MODE_BEET is not set
> @@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y
>   CONFIG_MTD_NAND=y
>   CONFIG_MTD_NAND_ATMEL=y
>   CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_GLUEBI=y
> +CONFIG_PROC_DEVICETREE=y
>   CONFIG_BLK_DEV_LOOP=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_COUNT=4
> @@ -95,7 +102,19 @@ CONFIG_MACB=y
>   # CONFIG_NET_VENDOR_STMICRO is not set
>   # CONFIG_NET_VENDOR_WIZNET is not set
>   CONFIG_MICREL_PHY=y
> -# CONFIG_WLAN is not set
> +CONFIG_LIBERTAS_THINFIRM=m
> +CONFIG_LIBERTAS_THINFIRM_USB=m
> +CONFIG_RTL8187=m
> +CONFIG_RT2X00=m
> +CONFIG_RT2500USB=m
> +CONFIG_RT73USB=m
> +CONFIG_RT2800USB=m
> +CONFIG_RT2800USB_RT53XX=y
> +CONFIG_RT2800USB_RT55XX=y
> +CONFIG_RT2800USB_UNKNOWN=y
> +CONFIG_MWIFIEX=m
> +CONFIG_MWIFIEX_SDIO=m
> +CONFIG_MWIFIEX_USB=m
>   # CONFIG_INPUT_MOUSEDEV is not set
>   CONFIG_INPUT_EVDEV=y
>   # CONFIG_KEYBOARD_ATKBD is not set
> @@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_OHCI_HCD=y
>   CONFIG_USB_ACM=y
>   CONFIG_USB_STORAGE=y
> +CONFIG_USB_SERIAL=y
> +CONFIG_USB_SERIAL_GENERIC=y
> +CONFIG_USB_SERIAL_FTDI_SIO=y
> +CONFIG_USB_SERIAL_PL2303=y
>   CONFIG_USB_GADGET=y
> -CONFIG_USB_AT91=y
> -CONFIG_USB_MASS_STORAGE=m
> +CONFIG_USB_ATMEL_USBA=y
> +CONFIG_USB_G_SERIAL=y
>   CONFIG_MMC=y
>   # CONFIG_MMC_BLOCK_BOUNCE is not set
>   CONFIG_MMC_ATMELMCI=y
> @@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y
>   # CONFIG_IOMMU_SUPPORT is not set
>   CONFIG_IIO=y
>   CONFIG_AT91_ADC=y
> -CONFIG_EXT2_FS=y
> +CONFIG_EXT4_FS=y
>   CONFIG_FANOTIFY=y
>   CONFIG_VFAT_FS=y
>   CONFIG_TMPFS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_SUMMARY=y
>   CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
>   CONFIG_NFS_FS=y
>   CONFIG_ROOT_NFS=y
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_CODEPAGE_850=y
>   CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_UTF8=y
>   CONFIG_STRIP_ASM_SYMS=y
>   CONFIG_DEBUG_FS=y
>   # CONFIG_SCHED_DEBUG is not set
> diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
> index 6c24985..1a2abd8 100644
> --- a/arch/arm/mach-at91/Kconfig.non_dt
> +++ b/arch/arm/mach-at91/Kconfig.non_dt
> @@ -14,15 +14,11 @@ config ARCH_AT91RM9200
>   	select SOC_AT91RM9200
>
>   config ARCH_AT91SAM9260
> -	bool "AT91SAM9260 or AT91SAM9XE"
> +	bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
>   	select SOC_AT91SAM9260
>
>   config ARCH_AT91SAM9261
> -	bool "AT91SAM9261"
> -	select SOC_AT91SAM9261
> -
> -config ARCH_AT91SAM9G10
> -	bool "AT91SAM9G10"
> +	bool "AT91SAM9261 or AT91SAM9G10"
>   	select SOC_AT91SAM9261
>
>   config ARCH_AT91SAM9263
> @@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL
>   	bool "AT91SAM9RL"
>   	select SOC_AT91SAM9RL
>
> -config ARCH_AT91SAM9G20
> -	bool "AT91SAM9G20"
> -	select SOC_AT91SAM9260
> -
>   config ARCH_AT91SAM9G45
>   	bool "AT91SAM9G45"
>   	select SOC_AT91SAM9G45
> @@ -50,6 +42,14 @@ config ARCH_AT91X40
>
>   endchoice
>
> +config ARCH_AT91SAM9G20
> +	bool
> +	select ARCH_AT91SAM9260
> +
> +config ARCH_AT91SAM9G10
> +	bool
> +	select ARCH_AT91SAM9261
> +
>   # ----------------------------------------------------------
>
>   if ARCH_AT91RM9200
> @@ -207,76 +207,6 @@ config MACH_FLEXIBITY
>   	  Select this if you are using Flexibity Connect board
>   	  <http://www.flexibity.com>
>
> -endif
> -
> -# ----------------------------------------------------------
> -
> -if ARCH_AT91SAM9261
> -
> -comment "AT91SAM9261 Board Type"
> -
> -config MACH_AT91SAM9261EK
> -	bool "Atmel AT91SAM9261-EK Evaluation Kit"
> -	select HAVE_AT91_DATAFLASH_CARD
> -	help
> -	  Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
> -	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
> -
> -endif
> -
> -# ----------------------------------------------------------
> -
> -if ARCH_AT91SAM9G10
> -
> -comment "AT91SAM9G10 Board Type"
> -
> -config MACH_AT91SAM9G10EK
> -	bool "Atmel AT91SAM9G10-EK Evaluation Kit"
> -	select HAVE_AT91_DATAFLASH_CARD
> -	help
> -	  Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
> -	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
> -
> -endif
> -
> -# ----------------------------------------------------------
> -
> -if ARCH_AT91SAM9263
> -
> -comment "AT91SAM9263 Board Type"
> -
> -config MACH_AT91SAM9263EK
> -	bool "Atmel AT91SAM9263-EK Evaluation Kit"
> -	select HAVE_AT91_DATAFLASH_CARD
> -	help
> -	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
> -	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
> -
> -config MACH_USB_A9263
> -	bool "CALAO USB-A9263"
> -	help
> -	  Select this if you are using a Calao Systems USB-A9263.
> -	  <http://www.calao-systems.com>
> -
> -endif
> -
> -# ----------------------------------------------------------
> -
> -if ARCH_AT91SAM9RL
> -
> -comment "AT91SAM9RL Board Type"
> -
> -config MACH_AT91SAM9RLEK
> -	bool "Atmel AT91SAM9RL-EK Evaluation Kit"
> -	help
> -	  Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
> -
> -endif
> -
> -# ----------------------------------------------------------
> -
> -if ARCH_AT91SAM9G20
> -
>   comment "AT91SAM9G20 Board Type"
>
>   config MACH_AT91SAM9G20EK
> @@ -341,17 +271,70 @@ config MACH_USB_A9G20
>   	  Select this if you are using a Calao Systems USB-A9G20.
>   	  <http://www.calao-systems.com>
>
> +config MACH_SNAPPER_9260
> +	bool "Bluewater Systems Snapper 9260/9G20 module"
> +	help
> +	  Select this if you are using the Bluewater Systems Snapper 9260 or
> +	  Snapper 9G20 modules.
> +	  <http://www.bluewatersys.com/>
>   endif
>
> -if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
> -comment "AT91SAM9260/AT91SAM9G20 boards"
> +# ----------------------------------------------------------
> +
> +if ARCH_AT91SAM9261
> +
> +comment "AT91SAM9261 Board Type"
> +
> +config MACH_AT91SAM9261EK
> +	bool "Atmel AT91SAM9261-EK Evaluation Kit"
> +	select HAVE_AT91_DATAFLASH_CARD
> +	help
> +	  Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
> +	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
> +
> +comment "AT91SAM9G10 Board Type"
> +
> +config MACH_AT91SAM9G10EK
> +	bool "Atmel AT91SAM9G10-EK Evaluation Kit"
> +	select HAVE_AT91_DATAFLASH_CARD
> +	help
> +	  Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
> +	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
> +
> +endif
> +
> +# ----------------------------------------------------------
> +
> +if ARCH_AT91SAM9263
> +
> +comment "AT91SAM9263 Board Type"
> +
> +config MACH_AT91SAM9263EK
> +	bool "Atmel AT91SAM9263-EK Evaluation Kit"
> +	select HAVE_AT91_DATAFLASH_CARD
> +	help
> +	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
> +	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
> +
> +config MACH_USB_A9263
> +	bool "CALAO USB-A9263"
> +	help
> +	  Select this if you are using a Calao Systems USB-A9263.
> +	  <http://www.calao-systems.com>
> +
> +endif
> +
> +# ----------------------------------------------------------
> +
> +if ARCH_AT91SAM9RL
> +
> +comment "AT91SAM9RL Board Type"
> +
> +config MACH_AT91SAM9RLEK
> +	bool "Atmel AT91SAM9RL-EK Evaluation Kit"
> +	help
> +	  Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
>
> -config MACH_SNAPPER_9260
> -        bool "Bluewater Systems Snapper 9260/9G20 module"
> -        help
> -          Select this if you are using the Bluewater Systems Snapper 9260 or
> -          Snapper 9G20 modules.
> -          <http://www.bluewatersys.com/>
>   endif
>
>   # ----------------------------------------------------------
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 788562d..f4a5f79 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -27,10 +27,8 @@ obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o
>   obj-$(CONFIG_ARCH_AT91RM9200)	+= at91rm9200_devices.o
>   obj-$(CONFIG_ARCH_AT91SAM9260)	+= at91sam9260_devices.o
>   obj-$(CONFIG_ARCH_AT91SAM9261)	+= at91sam9261_devices.o
> -obj-$(CONFIG_ARCH_AT91SAM9G10)	+= at91sam9261_devices.o
>   obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263_devices.o
>   obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl_devices.o
> -obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260_devices.o
>   obj-$(CONFIG_ARCH_AT91SAM9G45)	+= at91sam9g45_devices.o
>   obj-$(CONFIG_ARCH_AT91X40)	+= at91x40.o at91x40_time.o
>
> diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
> index 9a6618a..473546b 100644
> --- a/arch/arm/mach-at91/board-sam9261ek.c
> +++ b/arch/arm/mach-at91/board-sam9261ek.c
> @@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {}
>    */
>   static struct at73c213_board_info at73c213_data = {
>   	.ssc_id		= 1,
> -#if defined(CONFIG_MACH_AT91SAM9261EK)
> -	.shortname	= "AT91SAM9261-EK external DAC",
> -#else
> -	.shortname	= "AT91SAM9G10-EK external DAC",
> -#endif
> +	.shortname	= "AT91SAM9261/9G10-EK external DAC",
>   };
>
>   #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
> @@ -412,9 +408,6 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
>   	.default_monspecs		= &at91fb_default_stn_monspecs,
>   	.atmel_lcdfb_power_control	= at91_lcdc_stn_power_control,
>   	.guard_time			= 1,
> -#if defined(CONFIG_MACH_AT91SAM9G10EK)
> -	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
> -#endif
>   };
>
>   #else
> @@ -468,9 +461,6 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
>   	.default_monspecs		= &at91fb_default_tft_monspecs,
>   	.atmel_lcdfb_power_control	= at91_lcdc_tft_power_control,
>   	.guard_time			= 1,
> -#if defined(CONFIG_MACH_AT91SAM9G10EK)
> -	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
> -#endif
>   };
>   #endif
>
> @@ -574,6 +564,10 @@ static void __init ek_board_init(void)
>   	/* DBGU on ttyS0. (Rx & Tx only) */
>   	at91_register_uart(0, 0, 0);
>   	at91_add_device_serial();
> +
> +	if (cpu_is_at91sam9g10())
> +		ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
> +
>   	/* USB Host */
>   	at91_add_device_usbh(&ek_usbh_data);
>   	/* USB Device */
> @@ -606,11 +600,17 @@ static void __init ek_board_init(void)
>   	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
>   }
>
> -#if defined(CONFIG_MACH_AT91SAM9261EK)
>   MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
> -#else
> +	/* Maintainer: Atmel */
> +	.init_time	= at91sam926x_pit_init,
> +	.map_io		= at91_map_io,
> +	.handle_irq	= at91_aic_handle_irq,
> +	.init_early	= ek_init_early,
> +	.init_irq	= at91_init_irq_default,
> +	.init_machine	= ek_board_init,
> +MACHINE_END
> +
>   MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
> -#endif
>   	/* Maintainer: Atmel */
>   	.init_time	= at91sam926x_pit_init,
>   	.map_io		= at91_map_io,
>


-- 
Nicolas Ferre


From shawn.guo at linaro.org  Fri May 17 09:06:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 21:06:05 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <201305171429.52646.arnd@arndb.de>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <5396520.ZTuSn9S4Vd@wuerfel>
 <20130517085714.GG8607@S2101-09.ap.freescale.net>
 <201305171429.52646.arnd@arndb.de>
Message-ID: <20130517130603.GJ8607@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 02:29:52PM +0200, Arnd Bergmann wrote:
> > > Actually I think you should move that driver to drivers/clk and use
> > > of_clk_init(NULL) to initialize it.
> > > 
> > The mvf600 clock driver uses a lot of base clk support from mach-imx,
> > and can not be moved into drivers/clk as a single driver.  Right now, in
> > IMX clock drivers, we call of_clk_init() to only register fixed rate
> > clocks, since all the other clocks are not represented in device tree.
> 
> What are your plans for this in the long run?
> 
We can move all the IMX clock drivers into drivers/clk at some point
when necessary.  But I do not have a plan to register all the clocks
by merely calling of_clk_init(), because doing that would mean we have
to represent all these clocks in device tree.  For imx6q example, it's
about 200 ~ 300 nodes addition to DTB.  Device tree maintainers are
against to the idea.  They are perfectly fine with having clock driver
in kernel to represent/register these SoC internal clocks to clk
framework.

Shawn



From vinod.koul at intel.com  Fri May 17 08:34:23 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Fri, 17 May 2013 18:04:23 +0530
Subject: dmatest regression in 3.10-rc1
In-Reply-To: <20130516153553.GI11706@mudshark.cambridge.arm.com>
References: <20130515152803.GL23869@mudshark.cambridge.arm.com>
 <20130516153553.GI11706@mudshark.cambridge.arm.com>
Message-ID: <20130517123423.GR14863@intel.com>

On Thu, May 16, 2013 at 04:35:53PM +0100, Will Deacon wrote:
> On Wed, May 15, 2013 at 04:28:03PM +0100, Will Deacon wrote:
> > I've been observing a regression in the dmatest module with 3.10-rc1. It
> > manifests as either:
> > 
> >  - a spurious timeout on one or more of the channel threads
> >  - a complete kernel lockup (loss of console)
> >  - a panic (see below, noting that the callback [dmatest_callback] is
> >    dereferencing a NULL pointer)
> > 
> > If I revert 77101ce578bb ("dmatest: cancel thread immediately when asked
> > for") then things are rosy again, but I'm not sure if this is hiding another
> > problem.
> 
> Right, so I think I understand what's causing this, but I'll leave it to
> Andriy to suggest a fix. The problem comes about because the dmatest
> module is now driven from debugfs, making it possible to unload the module
> whilst a test run is in progress. In this case:
> 
> 	- The DMA threads will return from wait_event_freezable_timeout(...)
> 	  due to kthread_should_stop() returning true, and subsequently
> 	  report failure because done.done is false.
> 
> 	- The DMA engines may not be idle, so the asynchronous callback can
> 	  be invoked after we've started cleaning up, explaining the NULL
> 	  dereference I'm seeing.
> 
> The solutions are either fixing the module exit code to cope with concurrent
> DMA transfers or to revert 77101ce578bb and not allow the channel threads to
> return mid-transfer.
We need to properly abort the channels on removal. This is already handled in
the code but the kthread_stop is called after the transactions are aborted. It
should be the other way round. Can you try with below patch

---

diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index d8ce4ec..4e8d581 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -822,6 +822,9 @@ static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
 	struct dmatest_thread	*_thread;
 	int			ret;
 
+	/* terminate all transfers on specified channels */
+	dmaengine_terminate_all(dtc->chan);
+
 	list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
 		ret = kthread_stop(thread->task);
 		pr_debug("dmatest: thread %s exited with status %d\n",
@@ -830,9 +833,6 @@ static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
 		kfree(thread);
 	}
 
-	/* terminate all transfers on specified channels */
-	dmaengine_terminate_all(dtc->chan);
-
 	kfree(dtc);
 }

--
~Vinod 


From arnd at arndb.de  Fri May 17 09:17:31 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 15:17:31 +0200
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <20130517130603.GJ8607@S2101-09.ap.freescale.net>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <201305171429.52646.arnd@arndb.de>
 <20130517130603.GJ8607@S2101-09.ap.freescale.net>
Message-ID: <4003326.AbobOukrYT@wuerfel>

On Friday 17 May 2013 21:06:05 Shawn Guo wrote:
> On Fri, May 17, 2013 at 02:29:52PM +0200, Arnd Bergmann wrote:
> > > > Actually I think you should move that driver to drivers/clk and use
> > > > of_clk_init(NULL) to initialize it.
> > > > 
> > > The mvf600 clock driver uses a lot of base clk support from mach-imx,
> > > and can not be moved into drivers/clk as a single driver.  Right now, in
> > > IMX clock drivers, we call of_clk_init() to only register fixed rate
> > > clocks, since all the other clocks are not represented in device tree.
> > 
> > What are your plans for this in the long run?
> > 
> We can move all the IMX clock drivers into drivers/clk at some point
> when necessary.  But I do not have a plan to register all the clocks
> by merely calling of_clk_init(), because doing that would mean we have
> to represent all these clocks in device tree.  For imx6q example, it's
> about 200 ~ 300 nodes addition to DTB.  Device tree maintainers are
> against to the idea.  They are perfectly fine with having clock driver
> in kernel to represent/register these SoC internal clocks to clk
> framework.

Can't we move the driver to drivers/clk and have it initialized through
of_clk_init() without representing all clocks in the DT?

For all I can tell, CLK_OF_DECLARE() requires only the clock provider
to be described in DT, but not the actual clocks.

	Arnd


From linus.walleij at linaro.org  Fri May 17 09:17:39 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 15:17:39 +0200
Subject: [RFC PATCHv3 4/6] clocksource: Add TI-Nspire timer drivers
In-Reply-To: <26FBB324-AAA9-4C10-8978-C2EC1C26672E@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>
 <CACRpkdZBFbOnQ9rCehO0yKDN7fH9VR3VYCa_NkOGJz7KN+02FQ@mail.gmail.com>
 <26FBB324-AAA9-4C10-8978-C2EC1C26672E@gmail.com>
Message-ID: <CACRpkdaO7ieSdo5+Yq0+CLDfP==+DBOWn8+v0ap5iMOJy0Vf=Q@mail.gmail.com>

On Tue, May 14, 2013 at 1:51 PM, Daniel Tang <dt.tangr at gmail.com> wrote:
> On 14/05/2013, at 6:03 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
>
>>> +
>>> +       timer->interrupt_regs = of_iomap(node, 1);
>>
>> Check for errors.
>>
>>> +       timer->irqnr = irq_of_parse_and_map(node, 0);
>>
>> Check for errors.
>>> +       if (timer->interrupt_regs && timer->irqnr) {
>>>
>
> The idea with this is to make these properties optional. Each timer has two sub-timers
> but only one can generate interrupts.

I see now. Sorry, I was just being dumb, don't worry!

> Should I comment it in the code to make it apparent what's happening or is there a
> better way to express this?

Maybe. Maybe it's obvious to everyone else but me :-/

>>> +               writel(0x3F, timer->interrupt_regs + IO_INTR_ACK);
>>
>> Hm magic number, I guess it's clearing all IRQ lines?
>
> It's a bitmask of bits 0-5.

Yeah I figured so much... So 6 IRQ lines that get cleared.

>> If this timer is really just 16 bits, it's a *pretty* good idea to use
>> the prescaler (I guess this is what IO_DIVIDER is) beacuse else you
>> will get short sleep times with CONFIG_NO_HZ_IDLE on this system,
>> and wake up unnecessarily often.
>>
>> The same goes for the clock event.
>
> The clock frequency is 32768Hz. Should I be scaling it down at that frequency?

No. But that was *pretty* slow.

The thing is that the driver is getting "some clockfrequency" from
the clk subsystem and does not know what it is.

Usually (and I've seen this hardware design pattern a lot) when you
have a clock like this, and go talk to the clk implementation specialist
s/he will say "oh, yeah, I can mux in this 34 MHz clock to the timer
as well", and if that is possible then that is often what you want,
because it's good for things like HRtimers, and then it's useful to have
a prescaler och the clocksource/clockevent.

You can use that 32768 Hz for clock events and clocksource (but I
suspect that HRtimers will never be useful on this platform due to this).

Yours,
Linus Walleij


From dmurphy at ti.com  Fri May 17 09:21:23 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 17 May 2013 08:21:23 -0500
Subject: [PATCH v5] ARM:dts:omap4-panda: Update the LED support for the panda
 DTS
Message-ID: <1368796883-5501-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---

v5 - Provide pincrtl phandle to the gpio-led driver

 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 ++++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   34 +++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..5fd59b3 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <
+			&led_wkgpio_pins
+		>;
+
 		heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 0>;
@@ -137,6 +142,15 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..08d2e38 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,37 @@
 		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
 		>;
 };
+
+&omap4_pmx_core {
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
+&led_wkgpio_pins {
+	pinctrl-single,pins = <
+		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+	>;
+};
+
+&leds {
+	compatible = "gpio-leds";
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&led_gpio_pins
+		&led_wkgpio_pins
+	>;
+
+	heartbeat {
+		label = "pandaboard::status1";
+		gpios = <&gpio4 14 0>;
+		linux,default-trigger = "heartbeat";
+	};
+	mmc {
+		label = "pandaboard::status2";
+		gpios = <&gpio1 8 0>;
+		linux,default-trigger = "mmc0";
+	};
+};
-- 
1.7.5.4



From kishon at ti.com  Fri May 17 09:22:34 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Fri, 17 May 2013 18:52:34 +0530
Subject: [RFC PATCH 4/4] arm: omap: remove using usb_bind_phy for binding musb
 and phy
In-Reply-To: <1368796954-3499-1-git-send-email-kishon@ti.com>
References: <1368796954-3499-1-git-send-email-kishon@ti.com>
Message-ID: <1368796954-3499-4-git-send-email-kishon@ti.com>

Now that MUSB for OMAP started using devm_usb_get_phy_by_name
which does not require PHY library to already have the binding
information, removed usb_bind_phy calls that binds the MUSB controller
with the PHY from the board files.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c          |    1 -
 arch/arm/mach-omap2/board-3430sdp.c          |    1 -
 arch/arm/mach-omap2/board-4430sdp.c          |    1 -
 arch/arm/mach-omap2/board-cm-t35.c           |    1 -
 arch/arm/mach-omap2/board-devkit8000.c       |    1 -
 arch/arm/mach-omap2/board-igep0020.c         |    1 -
 arch/arm/mach-omap2/board-ldp.c              |    1 -
 arch/arm/mach-omap2/board-omap3beagle.c      |    1 -
 arch/arm/mach-omap2/board-omap3evm.c         |    1 -
 arch/arm/mach-omap2/board-omap3logic.c       |    1 -
 arch/arm/mach-omap2/board-omap3pandora.c     |    1 -
 arch/arm/mach-omap2/board-omap3stalker.c     |    1 -
 arch/arm/mach-omap2/board-omap3touchbook.c   |    1 -
 arch/arm/mach-omap2/board-omap4panda.c       |    1 -
 arch/arm/mach-omap2/board-overo.c            |    1 -
 arch/arm/mach-omap2/board-rm680.c            |    1 -
 arch/arm/mach-omap2/board-rx51.c             |    1 -
 arch/arm/mach-omap2/board-zoom-peripherals.c |    1 -
 18 files changed, 18 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 244d8a5..30d81f2 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -233,7 +233,6 @@ static void __init omap_2430sdp_init(void)
 	omap_hsmmc_init(mmc);
 
 	omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	board_smc91x_init();
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 23b004a..7f431b4 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -590,7 +590,6 @@ static void __init omap_3430sdp_init(void)
 	omap_ads7846_init(1, gpio_pendown, 310, NULL);
 	omap_serial_init();
 	omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	board_smc91x_init();
 	board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 56a9a4f..5a05b5a 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -730,7 +730,6 @@ static void __init omap_4430sdp_init(void)
 	omap4_sdp4430_wifi_init();
 	omap4_twl6030_hsmmc_init(mmc);
 
-	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
 	usb_musb_init(&musb_board_data);
 
 	status = omap_ethernet_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ee6218c..f9b4241 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -690,7 +690,6 @@ static void __init cm_t3x_common_init(void)
 	cm_t35_init_display();
 	omap_twl4030_audio_init("cm-t3x", NULL);
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	cm_t35_init_usbh();
 	cm_t35_init_camera();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 5764205..8d24aab 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -593,7 +593,6 @@ static void __init devkit8000_init(void)
 
 	omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
 	board_nand_init(devkit8000_nand_partitions,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index b54562d..5451c9c 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -628,7 +628,6 @@ static void __init igep_init(void)
 	omap_serial_init();
 	omap_sdrc_init(m65kxxxxam_sdrc_params,
 				  m65kxxxxam_sdrc_params);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	igep_flash_init();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d0d17bc..07423f2 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -376,7 +376,6 @@ static void __init omap_ldp_init(void)
 	omap_ads7846_init(1, 54, 310, NULL);
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
 			ZOOM_NAND_CS, 0, nand_default_timings);
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 04c1165..47d7dd7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -551,7 +551,6 @@ static void __init omap3_beagle_init(void)
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
 				  mt46h32m32lf6_sdrc_params);
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	usbhs_init(&usbhs_bdata);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d0de..87ec1bf 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -704,7 +704,6 @@ static void __init omap3_evm_init(void)
 		omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
 		phy_data[0].reset_gpio = 135;
 	}
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(&musb_board_data);
 
 	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index bab51e6..16e4e2a 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -216,7 +216,6 @@ static void __init omap3logic_init(void)
 	board_mmc_init();
 	board_smsc911x_init();
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 28133d5..6f730df 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -610,7 +610,6 @@ static void __init omap3pandora_init(void)
 	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
 	usbhs_init(&usbhs_bdata);
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	gpmc_nand_init(&pandora_nand_data, NULL);
 
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index d37e6b1..6f6fc92 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -394,7 +394,6 @@ static void __init omap3_stalker_init(void)
 
 	omap_serial_init();
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 7da48bc..bbff6de 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -367,7 +367,6 @@ static void __init omap3_touchbook_init(void)
 
 	/* Touchscreen and accelerometer */
 	omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1e2c75e..7eca390 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -435,7 +435,6 @@ static void __init omap4_panda_init(void)
 	omap_sdrc_init(NULL, NULL);
 	omap4_twl6030_hsmmc_init(mmc);
 	omap4_ehci_init();
-	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
 	usb_musb_init(&musb_board_data);
 	omap4_panda_display_init();
 }
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4ca6b68..d67ad70 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -472,7 +472,6 @@ static void __init overo_init(void)
 				  mt46h32m32lf6_sdrc_params);
 	board_nand_init(overo_nand_partitions,
 			ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 
 	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 345e8c4..cadeb5c 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -135,7 +135,6 @@ static void __init rm680_init(void)
 	sdrc_params = nokia_get_sdram_timings();
 	omap_sdrc_init(sdrc_params, sdrc_params);
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	rm680_peripherals_init();
 }
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index d2ea68e..0d16d37 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -99,7 +99,6 @@ static void __init rx51_init(void)
 	sdrc_params = nokia_get_sdram_timings();
 	omap_sdrc_init(sdrc_params, sdrc_params);
 
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(&musb_board_data);
 	rx51_peripherals_init();
 
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index a90375d..d05db2d 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -353,7 +353,6 @@ void __init zoom_peripherals_init(void)
 	omap_i2c_init();
 	pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup));
 	platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
-	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
 	usb_musb_init(NULL);
 	enable_board_wakeup_source();
 	omap_serial_init();
-- 
1.7.10.4



From kishon at ti.com  Fri May 17 09:22:31 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Fri, 17 May 2013 18:52:31 +0530
Subject: [RFC PATCH 1/4] arm: omap: Add phy binding info for musb in plat data
Message-ID: <1368796954-3499-1-git-send-email-kishon@ti.com>

In order for controllers to get PHY in case of non dt boot, the phy
binding information (phy label) should be added in the platform
data of the controller.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/mach-omap2/usb-musb.c |    6 +++++-
 include/linux/usb/musb.h       |    3 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3242a55..5ddbe39 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,8 +85,12 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
 	musb_plat.mode = board_data->mode;
 	musb_plat.extvbus = board_data->extvbus;
 
-	if (cpu_is_omap44xx())
+	if (cpu_is_omap44xx()) {
 		musb_plat.has_mailbox = true;
+		musb_plat.phy_name = "omap-usb2";
+	} else if (cpu_is_omap34xx()) {
+		musb_plat.phy_name = "twl4030";
+	}
 
 	if (soc_is_am35xx()) {
 		oh_name = "am35x_otg_hs";
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 053c268..c05d46d 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -104,6 +104,9 @@ struct musb_hdrc_platform_data {
 	/* for clk_get() */
 	const char	*clock;
 
+	/* phy device label */
+	const char	*phy_name;
+
 	/* (HOST or OTG) switch VBUS on/off */
 	int		(*set_vbus)(struct device *dev, int is_on);
 
-- 
1.7.10.4



From kishon at ti.com  Fri May 17 09:22:33 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Fri, 17 May 2013 18:52:33 +0530
Subject: [RFC PATCH 3/4] usb: musb: omap: use the new API to get PHY reference
 by label
In-Reply-To: <1368796954-3499-1-git-send-email-kishon@ti.com>
References: <1368796954-3499-1-git-send-email-kishon@ti.com>
Message-ID: <1368796954-3499-3-git-send-email-kishon@ti.com>

After the devices are created using PLATFORM_DEVID_AUTO,
devm_usb_get_phy_dev and usb_get_phy_dev can't be used reliably
as it relies on the device_names passed in usb_bind_phy. So used the
new API devm_usb_get_phy_by_name to get the PHY reference.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 drivers/usb/musb/musb_core.c |    1 +
 drivers/usb/musb/musb_core.h |    1 +
 drivers/usb/musb/omap2430.c  |    2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 37a261a..00fbaf4 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -1864,6 +1864,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
 	musb->board_set_power = plat->set_power;
 	musb->min_power = plat->min_power;
 	musb->ops = plat->platform_ops;
+	musb->phy_name = plat->phy_name;
 
 	/* The musb_platform_init() call:
 	 *   - adjusts musb->mregs
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 7fb4819..e9a9339 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -434,6 +434,7 @@ struct musb {
 	unsigned                double_buffer_not_ok:1;
 
 	struct musb_hdrc_config	*config;
+	const char		*phy_name;
 
 #ifdef MUSB_CONFIG_PROC_FS
 	struct proc_dir_entry *proc_entry;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 3551f1a..be29aa7 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -352,7 +352,7 @@ static int omap2430_musb_init(struct musb *musb)
 		musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent,
 		    "usb-phy", 0);
 	else
-		musb->xceiv = devm_usb_get_phy_dev(dev, 0);
+		musb->xceiv = devm_usb_get_phy_by_name(dev, musb->phy_name);
 
 	if (IS_ERR(musb->xceiv)) {
 		status = PTR_ERR(musb->xceiv);
-- 
1.7.10.4



From kishon at ti.com  Fri May 17 09:22:32 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Fri, 17 May 2013 18:52:32 +0530
Subject: [RFC PATCH 2/4] usb: phy: add a new API to get PHY ref by label
In-Reply-To: <1368796954-3499-1-git-send-email-kishon@ti.com>
References: <1368796954-3499-1-git-send-email-kishon@ti.com>
Message-ID: <1368796954-3499-2-git-send-email-kishon@ti.com>

After the devices are created using PLATFORM_DEVID_AUTO,
devm_usb_get_phy_dev and usb_get_phy_dev can't be used reliably
as it relies on the device_names passed in usb_bind_phy. So
added a new API to get the PHY reference by PHY label (PHY label
should be filled which creating the PHY).

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 drivers/usb/phy/phy.c   |   78 +++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/phy.h |   16 ++++++++++
 2 files changed, 94 insertions(+)

diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
index a9984c7..0dfdc38 100644
--- a/drivers/usb/phy/phy.c
+++ b/drivers/usb/phy/phy.c
@@ -55,6 +55,21 @@ static struct usb_phy *__usb_find_phy_dev(struct device *dev,
 	return ERR_PTR(-ENODEV);
 }
 
+static struct usb_phy *__usb_find_phy_by_name(struct device *dev,
+	struct list_head *list, const char *name)
+{
+	struct usb_phy	*phy = NULL;
+
+	list_for_each_entry(phy, list, head) {
+		if (strcmp(name, phy->label))
+			continue;
+
+		return phy;
+	}
+
+	return ERR_PTR(-ENODEV);
+}
+
 static struct usb_phy *__of_usb_find_phy(struct device_node *node)
 {
 	struct usb_phy  *phy;
@@ -272,6 +287,69 @@ struct usb_phy *devm_usb_get_phy_dev(struct device *dev, u8 index)
 EXPORT_SYMBOL_GPL(devm_usb_get_phy_dev);
 
 /**
+ * usb_get_phy_by_name - find the USB PHY using device ptr and phy label
+ * @dev - device that requests this phy
+ * @name - the name of the phy
+ *
+ * Returns the phy driver, after getting a refcount to it; or
+ * -ENODEV if there is no such phy.  The caller is responsible for
+ * calling usb_put_phy() to release that count.
+ *
+ * For use by USB host and peripheral drivers.
+ */
+struct usb_phy *usb_get_phy_by_name(struct device *dev, const char *name)
+{
+	struct usb_phy	*phy = NULL;
+	unsigned long	flags;
+
+	spin_lock_irqsave(&phy_lock, flags);
+
+	phy = __usb_find_phy_by_name(dev, &phy_list, name);
+	if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
+		pr_err("unable to find transceiver\n");
+		goto err0;
+	}
+
+	get_device(phy->dev);
+
+err0:
+	spin_unlock_irqrestore(&phy_lock, flags);
+
+	return phy;
+}
+EXPORT_SYMBOL_GPL(usb_get_phy_by_name);
+
+/**
+ * devm_usb_get_phy_by_name - find the USB PHY using device ptr and phy label
+ * @dev - device that requests this phy
+ * @name - the label of the phy
+ *
+ * Gets the phy using usb_get_phy_by_name(), and associates a device with it
+ * using devres. On driver detach, release function is invoked on the devres
+ * data, then, devres data is freed.
+ *
+ * For use by USB host and peripheral drivers.
+ */
+struct usb_phy *devm_usb_get_phy_by_name(struct device *dev, const char *name)
+{
+	struct usb_phy **ptr, *phy;
+
+	ptr = devres_alloc(devm_usb_phy_release, sizeof(*ptr), GFP_KERNEL);
+	if (!ptr)
+		return NULL;
+
+	phy = usb_get_phy_by_name(dev, name);
+	if (!IS_ERR(phy)) {
+		*ptr = phy;
+		devres_add(dev, ptr);
+	} else
+		devres_free(ptr);
+
+	return phy;
+}
+EXPORT_SYMBOL_GPL(devm_usb_get_phy_by_name);
+
+/**
  * devm_usb_put_phy - release the USB PHY
  * @dev - device that wants to release this phy
  * @phy - the phy returned by devm_usb_get_phy()
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index 6b5978f..12fa4b1 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -188,6 +188,10 @@ extern struct usb_phy *devm_usb_get_phy(struct device *dev,
 	enum usb_phy_type type);
 extern struct usb_phy *usb_get_phy_dev(struct device *dev, u8 index);
 extern struct usb_phy *devm_usb_get_phy_dev(struct device *dev, u8 index);
+extern struct usb_phy *usb_get_phy_by_name(struct device *dev,
+	const char *name);
+extern struct usb_phy *devm_usb_get_phy_by_name(struct device *dev,
+	const char *name);
 extern struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
 	const char *phandle, u8 index);
 extern void usb_put_phy(struct usb_phy *);
@@ -216,6 +220,18 @@ static inline struct usb_phy *devm_usb_get_phy_dev(struct device *dev, u8 index)
 	return ERR_PTR(-ENXIO);
 }
 
+static inline struct usb_phy *usb_get_phy_by_name(struct device *dev,
+	const char *name)
+{
+	return ERR_PTR(-ENXIO);
+}
+
+static inline struct usb_phy *devm_usb_get_phy_by_name(struct device *dev,
+	const char *name)
+{
+	return ERR_PTR(-ENXIO);
+}
+
 static inline struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
 	const char *phandle, u8 index)
 {
-- 
1.7.10.4



From linus.walleij at linaro.org  Fri May 17 09:25:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 May 2013 15:25:12 +0200
Subject: [GIT PULL] Nomadik clocks from device tree
Message-ID: <CACRpkdY8xqi04cf-SJ69QvHr8qB6itqvgxMyNk+=Xrtz2FGVaA@mail.gmail.com>

Hi ARM SoC folks,

please pull this patch set for Nomadik clocks from the device
tree into ARM SoC for v3.11 at your convenience. All patches
are reviewed and drivers/clk changes are ACKed by the clk
maintainer.

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
tags/nomadik-clk-dt-for-arm-soc

for you to fetch changes up to 7690fbb293df83025cffb608f9c2e81414c468a8:

  ARM: nomadik: register clocksource from device tree (2013-05-12
21:49:56 +0200)

----------------------------------------------------------------
This patch set moves the Nomadik clock tree to the device
tree, and adds device tree support to the Nomadik MTU
timer.

----------------------------------------------------------------
Linus Walleij (2):
      ARM: nomadik: convert all clocks except timer to dt
      ARM: nomadik: register clocksource from device tree

Rabin Vincent (1):
      clocksource: nomadik-mtu: support of probe

 .../devicetree/bindings/arm/ste-nomadik.txt        |  5 ++
 arch/arm/boot/dts/ste-nomadik-stn8815.dtsi         | 63 ++++++++++++++++++-
 arch/arm/mach-nomadik/Kconfig                      |  1 +
 arch/arm/mach-nomadik/cpu-8815.c                   | 26 ++------
 drivers/clk/clk-nomadik.c                          | 41 +++----------
 drivers/clocksource/nomadik-mtu.c                  | 70 ++++++++++++++++++----
 6 files changed, 137 insertions(+), 69 deletions(-)


From arnd at arndb.de  Fri May 17 09:31:16 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 15:31:16 +0200
Subject: [PATCH 0/4] ARM: Remove boilerplate debug_ll_io_init code
In-Reply-To: <5194F944.2040803@free-electrons.com>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
 <201305160040.54399.arnd@arndb.de> <5194F944.2040803@free-electrons.com>
Message-ID: <201305171531.16240.arnd@arndb.de>

On Thursday 16 May 2013, Maxime Ripard wrote:

> 
> How will we merge this? The first patch would be merged by Russel and
> the 3 others by their respective maintainers?

I think since it's mostly platform code and all trivial, we can merge
it into the next/cleanup branch in arm-soc directly.

	Arnd


From nm at ti.com  Fri May 17 09:34:18 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 17 May 2013 08:34:18 -0500
Subject: [PATCH v5] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <1368796883-5501-1-git-send-email-dmurphy@ti.com>
References: <1368796883-5501-1-git-send-email-dmurphy@ti.com>
Message-ID: <20130517133418.GA5068@kahuna>

On 08:21-20130517, Dan Murphy wrote:
[...]
May be others with better DT experience can help here..
but here is a trick to reduce dts file changes:
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..08d2e38 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,37 @@
>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>  		>;
>  };
> +
> +&omap4_pmx_core {
> +	led_gpio_pins: gpio_led_pmx {
> +		pinctrl-single,pins = <
> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
> +&led_wkgpio_pins {
> +	pinctrl-single,pins = <
> +		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +	>;
> +};
> +
> +&leds {
> +	compatible = "gpio-leds";
> +	pinctrl-names = "default";
Normally, override  will either add (if new param) OR replace (if same param)
	So the above two are superfluous.
> +	pinctrl-0 = <
> +		&led_gpio_pins
> +		&led_wkgpio_pins
> +	>;
These are needed
> +
> +	heartbeat {
> +		label = "pandaboard::status1";
can drop this
> +		gpios = <&gpio4 14 0>;
needed
> +		linux,default-trigger = "heartbeat";
can be dropped
> +	};
> +	mmc {
> +		label = "pandaboard::status2";
could be dropped
> +		gpios = <&gpio1 8 0>;
needed
> +		linux,default-trigger = "mmc0";
could be dropped.

-- 
Regards,
Nishanth Menon


From oliver+list at schinagl.nl  Fri May 17 09:35:44 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Fri, 17 May 2013 15:35:44 +0200
Subject: [PATCH 2/2] Add sunxi-sid to dts for sun4i and sun5i
In-Reply-To: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
Message-ID: <1368797744-13737-3-git-send-email-oliver+list@schinagl.nl>

From: Oliver Schinagl <oliver at schinagl.nl>

This should add support for the sunxi-sid driver to the device table for sun4i and sun5i

Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++
 arch/arm/boot/dts/sun5i-a13.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..1043db2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -163,6 +163,11 @@
 		reg = <0x01c20000 0x300000>;
 		ranges;
 
+		sid: eeprom at 01c23800 {
+			compatible = "allwinner,sun4i-sid";
+			reg = <0x01c23800 0x10>;
+		};
+
 		intc: interrupt-controller at 01c20400 {
 			compatible = "allwinner,sun4i-ic";
 			reg = <0x01c20400 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..f715132 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -153,6 +153,11 @@
 		reg = <0x01c20000 0x300000>;
 		ranges;
 
+		sid: eeprom at 01c23800 {
+			compatible = "allwinner,sun4i-sid";
+			reg = <0x01c23800 0x10>;
+		};
+
 		intc: interrupt-controller at 01c20400 {
 			compatible = "allwinner,sun4i-ic";
 			reg = <0x01c20400 0x400>;
-- 
1.8.1.5



From oliver+list at schinagl.nl  Fri May 17 09:35:42 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Fri, 17 May 2013 15:35:42 +0200
Subject: [PATCH 0/2] Driver for Allwinner sunxi Security ID
Message-ID: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>

The Allwinner A-series of SoC's have efuses exposed via registers to read the
factory programmed e-fuses. These should in theory be programmable but this is
still to be confirmed. It does appear that these fuses are unique enough to be
used as serial numbers, RSA keys, generate MAC addresses from etc. If it turns
out to be user programmable, the use obviously increases. Allwinner did use the
fuses initially to determine the chip-type.

This driver supports all currently known chips based on datasheets and 'dumped'
drivers that we have so far, the dts is only implemented for known chips.

This is my very first driver so please try to be gentle ;)

Oliver Schinagl (2):
  Initial support for Allwinner's Security ID fuses
  Add sunxi-sid to dts for sun4i and sun5i

 arch/arm/boot/dts/sun4i-a10.dtsi |   5 +
 arch/arm/boot/dts/sun5i-a13.dtsi |   5 +
 drivers/misc/eeprom/Kconfig      |  19 ++++
 drivers/misc/eeprom/Makefile     |   1 +
 drivers/misc/eeprom/sunxi_sid.c  | 218 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 248 insertions(+)
 create mode 100644 drivers/misc/eeprom/sunxi_sid.c

-- 
1.8.1.5



From oliver+list at schinagl.nl  Fri May 17 09:35:43 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Fri, 17 May 2013 15:35:43 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
Message-ID: <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>

From: Oliver Schinagl <oliver at schinagl.nl>

Allwinner has electric fuses (efuse) on their line of chips. This driver
reads those fuses and exports them as a sysfs node. Also a symbol is exported
for in-kernel useage.

While initially these fuses are used to somewhat determin the chipID, these
appear to be writeable by the user and thus can be used for other purpouses.
For example storing a 128 bit root key, a unique serial number, which could
then even be used as a MAC address.

Because writing to e-fuses can be potentially dangerous, and are certainly
not as often writable (if at all) as flash memory, these shouldn't be easily
changeable, hence only a read-only mode. An offline tool to write the fuses
is in the works.

Currently supported are the following known chips:
Allwinner sun4i (A10)
Allwinner sun5i (A10s A13)
Allwinner sun6i (A31, A31s)
Allwinner sun7i (A20)

Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
---
 drivers/misc/eeprom/Kconfig     |  19 ++++
 drivers/misc/eeprom/Makefile    |   1 +
 drivers/misc/eeprom/sunxi_sid.c | 218 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/misc/eeprom/sunxi_sid.c

diff --git a/drivers/misc/eeprom/Kconfig b/drivers/misc/eeprom/Kconfig
index 04f2e1f..c9ddda5 100644
--- a/drivers/misc/eeprom/Kconfig
+++ b/drivers/misc/eeprom/Kconfig
@@ -96,4 +96,23 @@ config EEPROM_DIGSY_MTC_CFG
 
 	  If unsure, say N.
 
+config EEPROM_SUNXI_SID
+	tristate "Allwinner sunxi security ID support"
+	depends on ARCH_SUNXI && SYSFS
+	help
+	  This is a driver for the 'security ID' available on various Allwinner
+	  devices. Currently supported are:
+		sun4i (A10)
+		sun5i (A10s, A12, A13)
+		sun6i (A31)
+		sun7i (A20)
+
+	  Due to the potential risks involved with changing e-fuses,
+	  this driver is read-only
+
+	  For more information visit http://linux-sunxi.org/SID
+
+	  This driver can also be built as a module. If so, the module
+	  will be called sunxi_sid.
+
 endmenu
diff --git a/drivers/misc/eeprom/Makefile b/drivers/misc/eeprom/Makefile
index fc1e81d..9507aec 100644
--- a/drivers/misc/eeprom/Makefile
+++ b/drivers/misc/eeprom/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_EEPROM_LEGACY)	+= eeprom.o
 obj-$(CONFIG_EEPROM_MAX6875)	+= max6875.o
 obj-$(CONFIG_EEPROM_93CX6)	+= eeprom_93cx6.o
 obj-$(CONFIG_EEPROM_93XX46)	+= eeprom_93xx46.o
+obj-$(CONFIG_EEPROM_SUNXI_SID)	+= sunxi_sid.o
 obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o
diff --git a/drivers/misc/eeprom/sunxi_sid.c b/drivers/misc/eeprom/sunxi_sid.c
new file mode 100644
index 0000000..953f137
--- /dev/null
+++ b/drivers/misc/eeprom/sunxi_sid.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2013 Oliver Schinagl
+ * http://www.linux-sunxi.org
+ *
+ * Oliver Schinagl <oliver at schinagl.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This driver exposes the Allwinner security ID, a 128 bit eeprom, in chunks
+ * of 8 bytes.
+ */
+
+#include <linux/compiler.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kobject.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/stat.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+
+
+#define DRV_NAME "sunxi-sid"
+#define DRV_VERSION "1.0"
+
+/* Register offsets */
+#define SUNXI_SID_KEY0 0x00
+#define SUNXI_SID_KEY1 0x04
+#define SUNXI_SID_KEY2 0x08
+#define SUNXI_SID_KEY3 0x0c
+
+/* There are 4 32-bit keys */
+#define SUNXI_SID_KEYS 4
+/* and 4 32-bit keys per 32-bit key */
+#define SUNXI_SID_SIZE (SUNXI_SID_KEYS * 4)
+
+#if (SUNXI_SID_SIZE > PAGE_SIZE)
+#error "SUNXI_SID_SIZE is larger then the target's PAGE_SIZE, ENOMEM."
+#endif
+
+static u8 keys_lut[] = {
+	SUNXI_SID_KEY0,
+	SUNXI_SID_KEY1,
+	SUNXI_SID_KEY2,
+	SUNXI_SID_KEY3,
+};
+
+struct sid_priv {
+	void __iomem *sid_base;
+};
+
+struct sid_priv *p;
+
+
+/* We read the entire key, using a look up table. Returned is only the
+ * requested byte. This is of course slower then it could be and uses 4 times
+ * more reads as needed but keeps code a little simpler.
+ */
+u8 sunxi_sid_read_byte(const int key)
+{
+	u32 sid_key;
+	u8 ret;
+
+	ret = 0;
+	if (likely((key <= SUNXI_SID_SIZE))) {
+		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
+		switch (key % 4) {
+		case 0:
+			ret = (sid_key >> 24) & 0xff;
+			break;
+		case 1:
+			ret = (sid_key >> 16) & 0xff;
+			break;
+		case 2:
+			ret = (sid_key >> 8) & 0xff;
+			break;
+		case 3:
+			ret = sid_key & 0xff;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static ssize_t sid_read(struct file *fd, struct kobject *kobj,
+			struct bin_attribute *attr, char *buf,
+			loff_t pos, size_t size)
+{
+	ssize_t ret;
+	struct device *dev;
+	struct sid_priv *priv;
+	int i;
+
+	ret = -EPERM;
+	dev = kobj_to_dev(kobj);
+	priv = dev_get_drvdata(dev);
+
+	if ((likely(size > 0)) && ((size + pos) <= SUNXI_SID_SIZE)) {
+		for (i = 0; i < size; i++) {
+			buf[i] = sunxi_sid_read_byte(pos + i);
+		}
+		if (i < PAGE_SIZE) {
+			buf[i] = '\0';
+			ret = (ssize_t)size;
+		} else {
+			ret = -ENOMEM;
+		}
+	} else {
+		buf[0] = '\0';
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static struct of_device_id sid_of_match[] = {
+	{
+		.compatible = "allwinner,sun4i-sid",
+	},
+	{/* sentinel */}
+};
+MODULE_DEVICE_TABLE(of, sid_of_match);
+
+static struct bin_attribute sid_bin_attr = {
+	.attr = {
+		.name = "key",
+		.mode = S_IRUGO,
+	},
+	.size = SUNXI_SID_SIZE,
+	.read = sid_read,
+};
+
+static int sid_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct sid_priv *priv;
+
+	priv = dev_get_drvdata(dev);
+	device_remove_bin_file(dev, &sid_bin_attr);
+	iounmap(priv->sid_base);
+	devm_kfree(dev, priv);
+	return 0;
+}
+
+static int __init sid_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct device *dev = &pdev->dev;
+	struct sid_priv *priv;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	p = priv;
+
+	dev_set_drvdata(dev, priv);
+
+	if (!priv) {
+		dev_err(dev, "Unable to allocate device private data\n");
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+	priv->sid_base = of_iomap(dev->of_node, 0);
+	if (!priv->sid_base) {
+		dev_err(dev, "Unable to map memory region\n");
+		ret = -ENOMEM;
+		goto exit_free;
+	}
+
+	ret = device_create_bin_file(dev, &sid_bin_attr);
+	if (ret) {
+		dev_err(dev, "Unable to create sysfs bin entry\n");
+		goto exit_unmap;
+	}
+
+	dev_info(dev, "Sunxi security ID driver loaded successfully.\n");
+
+	return 0;
+
+
+exit_unmap:
+	iounmap(priv->sid_base);
+exit_free:
+	devm_kfree(dev, priv);
+exit:
+	return ret;
+}
+
+static struct platform_driver sid_driver = {
+	.probe = sid_probe,
+	.remove = sid_remove,
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+		.of_match_table = sid_of_match,
+	},
+};
+module_platform_driver(sid_driver);
+
+
+MODULE_AUTHOR("Oliver Schinagl <oliver at schinagl.nl>");
+MODULE_DESCRIPTION("Allwinner sunxi security id driver");
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL");
-- 
1.8.1.5



From arnd at arndb.de  Fri May 17 09:45:09 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 15:45:09 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
Message-ID: <4144514.S8gIuIKLrJ@wuerfel>

On Friday 17 May 2013 15:35:43 Oliver Schinagl wrote:
> +static struct bin_attribute sid_bin_attr = {
> +       .attr = {
> +               .name = "key",
> +               .mode = S_IRUGO,
> +       },
> +       .size = SUNXI_SID_SIZE,
> +       .read = sid_read,
> +};

I believe all the other drivers in drivers/misc/eeprom use "eeprom"
as the name for the attribute, so using "key" here is a bit inconsistent.

Can you change that?

	Arnd


From emilio at elopez.com.ar  Fri May 17 09:43:20 2013
From: emilio at elopez.com.ar (=?UTF-8?q?Emilio=20L=C3=B3pez?=)
Date: Fri, 17 May 2013 10:43:20 -0300
Subject: [PATCH] clk: sunxi: "cpu_data" is defined in header files of some
 architectures
In-Reply-To: <5195D615.70608@cateee.net>
References: <5195D615.70608@cateee.net>
Message-ID: <1368798200-7063-1-git-send-email-emilio@elopez.com.ar>

From: "Giacomo A. Catenazzi" <cate at cateee.net>

In some architectures, the #define cpu_data is not a "macro-function",
so the compiler will substitute the identifier with probably something
wrong.

Signed-off-by: Giacomo A. Catenazzi <cate at cateee.net>
Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
[emilio at elopez.com.ar: use cpu_mux_data instead of this_cpu_data]
---

Hi Giacomo,

I have taken your patch and resent it to linux-arm-kernel and Mike 
Turquette this time, but please try to use git send-email on your next 
patch.

Here is a video from Greg that explains how to use it as well as other 
things (checkpatch.pl, get_maintainer.pl, etc)

http://www.youtube.com/watch?v=LLBrBBImJt4

Thanks! :)

Emilio

 drivers/clk/sunxi/clk-sunxi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 930d36f..412912b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -239,7 +239,7 @@ struct mux_data {
 	u8 shift;
 };
 
-static const __initconst struct mux_data cpu_data = {
+static const __initconst struct mux_data cpu_mux_data = {
 	.shift = 16,
 };
 
@@ -433,7 +433,7 @@ static const __initconst struct of_device_id clk_div_match[] = {
 
 /* Matches for mux clocks */
 static const __initconst struct of_device_id clk_mux_match[] = {
-	{.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_data,},
+	{.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,},
 	{.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
 	{}
 };
-- 
1.8.2.3



From gregory.clement at free-electrons.com  Fri May 17 09:47:37 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 17 May 2013 15:47:37 +0200
Subject: [PATCH] arm: mvebu: enable the third USB interface on OpenBlocks
 AX3
In-Reply-To: <20130517.111810.02327269.yamagata@plathome.co.jp>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
Message-ID: <519634F9.7060700@free-electrons.com>

Hi Thomas,
On 05/17/2013 04:18 AM, yamagata at plathome.co.jp wrote:
> Dear Mr. Petazzoni
> 
>> Besides the two "classic" USB interfaces with normal USB ports on the
>> front side, the PlatHome OpenBlocks AX3 uses the third USB interface
>> of the Marvell SoC in the mini-PCIe connector. This allows certain
>> mini-PCIe cards to expose parts of their functionality as a USB
>> peripheral.
>>
>> This commit enables this third USB interface in the OpenBlocks AX3
>> Device Tree, and also adds comments on top of the two other USB
>> interfaces so that the Device Tree makes it clear which USB interface
>> at the SoC level matches which USB interface visible on the board.
> 
> I see the following messages by dmesg with your patch for
> linux-3.10-rc1 and 3.9.2.
> 
> ...
> usb 3-1: New USB device found, idVendor=0a5c, idProduct=219c
> usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
> usb 3-1: Product: Broadcom BCM2070 Bluetooth Device
> usb 3-1: Manufacturer: Broadcom Corp
> usb 3-1: SerialNumber: B4749F63C1B6
> ...
> Bluetooth: Core ver 2.16
> NET: Registered protocol family 31
> Bluetooth: HCI device and connection manager initialized
> Bluetooth: HCI socket layer initialized
> Bluetooth: L2CAP socket layer initialized
> Bluetooth: SCO socket layer initialized
> usbcore: registered new interface driver btusb

This patch is nice and adds useful information.

I applied and tested on my OpenBlocks AX3 and get the 3rd USB
interface detected. As I don't have any mini-PCIe card which use USB,
I didn't tested it furthermore, but as Atsushi Yamagata managed to
detect an USB device on this interface, we can be pretty confident
with this patch:

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

Thanks,

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From p.zabel at pengutronix.de  Fri May 17 09:49:02 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 17 May 2013 15:49:02 +0200
Subject: [PATCH 1/2] ARM i.MX53: Add SATA clock
Message-ID: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 +
 arch/arm/mach-imx/clk-imx51-imx53.c                    | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index d71b4b2..b66cf36 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -184,6 +184,7 @@ clocks and IDs.
 	cko2			170
 	srtc_gate		171
 	pata_gate		172
+	sata_gate		173
 
 Examples (for mx53):
 
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6fc486b..fbc15f2 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -110,7 +110,7 @@ enum imx5_clks {
 	owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
 	cko1_sel, cko1_podf, cko1,
 	cko2_sel, cko2_podf, cko2,
-	srtc_gate, pata_gate,
+	srtc_gate, pata_gate, sata_gate,
 	clk_max
 };
 
@@ -485,6 +485,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
 	clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
 	clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+	clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
 
 	clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
 				mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
-- 
1.8.2.rc2



From p.zabel at pengutronix.de  Fri May 17 09:49:03 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 17 May 2013 15:49:03 +0200
Subject: [PATCH 2/2] ARM i.MX5: Add S/PDIF clocks
In-Reply-To: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>
References: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1368798543-23285-2-git-send-email-p.zabel@pengutronix.de>

This patch adds the S/PDIF clocks for i.MX51 and i.MX53. Tested on i.MX53.
The i.MX51 has a second set of spdif_root clock dividers, and on i.MX53
there is an additional input to the spdif_xtal mux.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 .../devicetree/bindings/clock/imx5-clock.txt       | 12 ++++++++++
 arch/arm/mach-imx/clk-imx51-imx53.c                | 28 +++++++++++++++++++++-
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index b66cf36..f46f562 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -185,6 +185,18 @@ clocks and IDs.
 	srtc_gate		171
 	pata_gate		172
 	sata_gate		173
+	spdif_xtal_sel		174
+	spdif0_sel		175
+	spdif1_sel		176
+	spdif0_pred		177
+	spdif0_podf		178
+	spdif1_pred		179
+	spdif1_podf		180
+	spdif0_com_sel		181
+	spdif1_com_sel		182
+	spdif0_gate		183
+	spdif1_gate		184
+	spdif_ipg_gate		185
 
 Examples (for mx53):
 
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fbc15f2..6ac38de 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = {
 	"tve_sel", "lp_apm",
 	"uart_root", "dummy"/* spdif0_clk_root */,
 	"dummy", "dummy", };
+static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
+static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
+static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
+static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
+static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
+
 
 enum imx5_clks {
 	dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -110,7 +116,9 @@ enum imx5_clks {
 	owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
 	cko1_sel, cko1_podf, cko1,
 	cko2_sel, cko2_podf, cko2,
-	srtc_gate, pata_gate, sata_gate,
+	srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
+	spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
+	spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
 	clk_max
 };
 
@@ -267,6 +275,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
 	clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
 	clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
+	clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
+	clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
+	clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
+	clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
+				spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
+	clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
+	clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
 
 	for (i = 0; i < ARRAY_SIZE(clk); i++)
 		if (IS_ERR(clk[i]))
@@ -378,6 +393,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
 	clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
 	clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+	clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+				mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
+	clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
+				spdif_sel, ARRAY_SIZE(spdif_sel));
+	clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+	clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
+	clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
+				mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
+	clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 
 	for (i = 0; i < ARRAY_SIZE(clk); i++)
 		if (IS_ERR(clk[i]))
@@ -496,6 +520,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 				mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
 	clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
 	clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+	clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+				mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 
 	for (i = 0; i < ARRAY_SIZE(clk); i++)
 		if (IS_ERR(clk[i]))
-- 
1.8.2.rc2



From shawn.guo at linaro.org  Fri May 17 09:54:46 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 May 2013 21:54:46 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <4003326.AbobOukrYT@wuerfel>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <201305171429.52646.arnd@arndb.de>
 <20130517130603.GJ8607@S2101-09.ap.freescale.net>
 <4003326.AbobOukrYT@wuerfel>
Message-ID: <20130517135444.GK8607@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 03:17:31PM +0200, Arnd Bergmann wrote:
> Can't we move the driver to drivers/clk and have it initialized through
> of_clk_init() without representing all clocks in the DT?
> 
> For all I can tell, CLK_OF_DECLARE() requires only the clock provider
> to be described in DT, but not the actual clocks.

Clock provider is actually a "clk".  For fixed rate clock example,
of_fixed_factor_clk_setup() firstly parses DT to get all the
necessary data and then calls clk_register_fixed_factor() to register
the clk to framework, lastly calls of_clk_add_provider() to register the
clk as a provider.

Shawn



From khilman at linaro.org  Fri May 17 10:01:26 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 17 May 2013 07:01:26 -0700
Subject: u8500_defconfig: build failure in linux-next
In-Reply-To: <CACRpkdYLskC67vXQsVq470yo5J+E6eLtPz5-em4Qd_Pe0pwJiA@mail.gmail.com>
 (Linus Walleij's message of "Fri, 17 May 2013 08:31:31 +0200")
References: <CAGa+x85Q8i9DCdTprbVX1opB9UdeD4uxAQpZ-CsqPYt86dLVFA@mail.gmail.com>
 <CACRpkdYLskC67vXQsVq470yo5J+E6eLtPz5-em4Qd_Pe0pwJiA@mail.gmail.com>
Message-ID: <87bo89u2mh.fsf@linaro.org>

Linus Walleij <linus.walleij at linaro.org> writes:

> On Thu, May 16, 2013 at 1:29 AM, Kevin Hilman <khilman at linaro.org> wrote:
>
>> Lee, Linus,
>>
>> In building all the ARM defconfigs in linux-next, I noticed
>> u8500_defconfig not building:
>>
>>   [...]
>>   CC      drivers/mfd/ab8500-debugfs.o
>> /work/kernel/next/drivers/mfd/ab8500-debugfs.c:95:23: fatal error:
>> mach/irqs.h: No such file or directory
>>
>> Same build error on v3.10-rc1 and Linus' master branch (but is fine on v3.9)
>
> Yes, I sent this patch:
> http://marc.info/?l=linux-kernel&m=136601206705342&w=2

Great.

> Sam's been a bit overloaded that is why it's taking time to reach
> Torvalds tree. Recently Lee started to help out queueing patches
> for MFD so hopefully the bottleneck will be solved this way.

Looks like this hit linux-next today, so u8500_defconfig is back to
building cleanly in linux-next.

Thanks,

Kevin


From nicolas.ferre at atmel.com  Fri May 17 10:02:16 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 17 May 2013 16:02:16 +0200
Subject: [GIT PULL] at91: cleanup (pinctrl macros, defconfigs) for 3.11 #1
Message-ID: <1368799336-25226-1-git-send-email-nicolas.ferre@atmel.com>

Arnd, Olof,

Here is the first AT91 cleanup pull-request for 3.11. I is dominated by a big
update of DT files because of the move to macros in pinctrl. As we plan to 
make this "cleanup" series the base of all our work on AT91 for 3.11, we would
like to see it appearing early in arm-soc and linux-next: this is why we send
it to you right now.

We have colected the Acked-by from Linus Walleij and we all think that it makes
sense to merge this material through arm-soc tree:
- is touches nearly nothing of pinctrl actual code (a header file)
- all dtsi/dts modifications for 3.11 will need this as a codebase for avoiding
  merging nightmare

I hope that it is okay with you.

Thanks, best regards,

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-cleanup

for you to fetch changes up to b3f442b0eedbc20b5ce3f4a96530588d14901199:

  ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)

----------------------------------------------------------------
Big update with pinctrl by use of macros and
header files. Increases readability and avoid
typos.
Update of AT91 defconfigs and merge of defconfigs for
SoC look-alike:
sam9260/9g20 and sam9261/9g10.

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (6):
      ARM: at91: dt: use #include for all device trees
      ARM: at91: dt: switch to standard GPIO flag defines.
      ARM: at91: dt: add pinctrl pre-processor define
      ARM: at91: dt: switch to pinctrl to pre-processor
      ARM: at91: dt: switch to standard IRQ flag defines
      ARM: at91: udpate defconfigs

 arch/arm/boot/dts/aks-cdu.dts                      |  12 +-
 arch/arm/boot/dts/animeo_ip.dts                    |  18 +-
 arch/arm/boot/dts/at91-ariag25.dts                 |   6 +-
 arch/arm/boot/dts/at91rm9200.dtsi                  | 207 ++++----
 arch/arm/boot/dts/at91rm9200ek.dts                 |  10 +-
 arch/arm/boot/dts/at91sam9260.dtsi                 | 215 ++++-----
 arch/arm/boot/dts/at91sam9263.dtsi                 | 203 ++++----
 arch/arm/boot/dts/at91sam9263ek.dts                |  24 +-
 arch/arm/boot/dts/at91sam9g15.dtsi                 |   2 +-
 arch/arm/boot/dts/at91sam9g15ek.dts                |   4 +-
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   2 +-
 arch/arm/boot/dts/at91sam9g20ek.dts                |   6 +-
 arch/arm/boot/dts/at91sam9g20ek_2mmc.dts           |  10 +-
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi        |  28 +-
 arch/arm/boot/dts/at91sam9g25.dtsi                 |   2 +-
 arch/arm/boot/dts/at91sam9g25ek.dts                |   4 +-
 arch/arm/boot/dts/at91sam9g35.dtsi                 |   2 +-
 arch/arm/boot/dts/at91sam9g35ek.dts                |   4 +-
 arch/arm/boot/dts/at91sam9g45.dtsi                 | 213 ++++-----
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |  38 +-
 arch/arm/boot/dts/at91sam9n12.dtsi                 | 141 +++---
 arch/arm/boot/dts/at91sam9n12ek.dts                |  14 +-
 arch/arm/boot/dts/at91sam9x25.dtsi                 |  22 +-
 arch/arm/boot/dts/at91sam9x25ek.dts                |   4 +-
 arch/arm/boot/dts/at91sam9x35.dtsi                 |   2 +-
 arch/arm/boot/dts/at91sam9x35ek.dts                |   4 +-
 arch/arm/boot/dts/at91sam9x5.dtsi                  | 279 +++++------
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   8 +-
 arch/arm/boot/dts/at91sam9x5ek.dtsi                |  14 +-
 arch/arm/boot/dts/ethernut5.dts                    |   6 +-
 arch/arm/boot/dts/evk-pro3.dts                     |   6 +-
 arch/arm/boot/dts/ge863-pro3.dtsi                  |   2 +-
 arch/arm/boot/dts/kizbox.dts                       |  16 +-
 arch/arm/boot/dts/mpa1600.dts                      |   4 +-
 arch/arm/boot/dts/pm9g45.dts                       |  22 +-
 arch/arm/boot/dts/sama5d3.dtsi                     | 520 +++++++++++----------
 arch/arm/boot/dts/sama5d31ek.dts                   |   6 +-
 arch/arm/boot/dts/sama5d33ek.dts                   |   4 +-
 arch/arm/boot/dts/sama5d34ek.dts                   |   6 +-
 arch/arm/boot/dts/sama5d35ek.dts                   |   4 +-
 arch/arm/boot/dts/sama5d3xcm.dtsi                  |   4 +-
 arch/arm/boot/dts/sama5d3xdm.dtsi                  |   2 +-
 arch/arm/boot/dts/sama5d3xmb.dtsi                  |  26 +-
 arch/arm/boot/dts/tny_a9260.dts                    |   4 +-
 arch/arm/boot/dts/tny_a9263.dts                    |   4 +-
 arch/arm/boot/dts/tny_a9g20.dts                    |   4 +-
 arch/arm/boot/dts/usb_a9260.dts                    |   4 +-
 arch/arm/boot/dts/usb_a9260_common.dtsi            |   6 +-
 arch/arm/boot/dts/usb_a9263.dts                    |   8 +-
 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi           |  22 +-
 arch/arm/boot/dts/usb_a9g20.dts                    |   4 +-
 arch/arm/configs/at91_dt_defconfig                 |  55 ++-
 arch/arm/configs/at91rm9200_defconfig              | 218 ++-------
 ...am9g20_defconfig => at91sam9260_9g20_defconfig} |  67 ++-
 arch/arm/configs/at91sam9260_defconfig             |  91 ----
 ...am9261_defconfig => at91sam9261_9g10_defconfig} |  19 +-
 arch/arm/configs/at91sam9263_defconfig             |  39 +-
 arch/arm/configs/at91sam9g45_defconfig             |  94 ++--
 arch/arm/configs/sama5_defconfig                   |  35 +-
 arch/arm/mach-at91/Kconfig.non_dt                  | 159 +++----
 arch/arm/mach-at91/Makefile                        |   2 -
 arch/arm/mach-at91/board-sam9261ek.c               |  28 +-
 include/dt-bindings/pinctrl/at91.h                 |  35 ++
 63 files changed, 1407 insertions(+), 1617 deletions(-)
 rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
 delete mode 100644 arch/arm/configs/at91sam9260_defconfig
 rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)
 create mode 100644 include/dt-bindings/pinctrl/at91.h

-- 
Nicolas Ferre


From plagnioj at jcrosoft.com  Fri May 17 10:14:43 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 16:14:43 +0200
Subject: [PATCH 0/5 v3] ARM: at91: dt: add USBA support
Message-ID: <20130517141443.GB16804@game.jcrosoft.org>

HI,

	v3:
	rebase againt 3.10-rc1 + dt macro cleanup

	This patch serie finish to add the usb device support to dt for at91
	with the usba support present on the last at91 generation since sam9g45

The following changes since commit b3f442b0eedbc20b5ce3f4a96530588d14901199:

  ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git j/for-3.11-usba

for you to fetch changes up to f24c9792c29803420a7bf7204223ef028191d449:

  ARM: at91: sam9m10g45ek add udc DT support (2013-05-17 22:05:46 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (5):
      usb: add Atmel USBA UDC DT support
      ARM: at91: sam9x5 add udc DT support
      ARM: at91: sam9x5ek add udc DT support
      ARM: at91: sam9g45 add udc DT support
      ARM: at91: sam9m10g45ek add udc DT support

 Documentation/devicetree/bindings/usb/atmel-usb.txt |   82 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi                  |   62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts              |    5 +++++
 arch/arm/boot/dts/at91sam9x5.dtsi                   |   62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi                 |    5 +++++
 arch/arm/mach-at91/at91sam9g45.c                    |    2 ++
 arch/arm/mach-at91/at91sam9x5.c                     |    2 ++
 drivers/usb/gadget/Kconfig                          |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                 |  214 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------
 drivers/usb/gadget/atmel_usba_udc.h                 |    1 +
 10 files changed, 382 insertions(+), 55 deletions(-)

Best Regards,
J.


From will.deacon at arm.com  Fri May 17 10:18:57 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 15:18:57 +0100
Subject: dmatest regression in 3.10-rc1
In-Reply-To: <20130517123423.GR14863@intel.com>
References: <20130515152803.GL23869@mudshark.cambridge.arm.com>
 <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <20130517123423.GR14863@intel.com>
Message-ID: <20130517141857.GM23112@mudshark.cambridge.arm.com>

Hi Vinod,

Thanks for the reply.

On Fri, May 17, 2013 at 01:34:23PM +0100, Vinod Koul wrote:
> On Thu, May 16, 2013 at 04:35:53PM +0100, Will Deacon wrote:
> > Right, so I think I understand what's causing this, but I'll leave it to
> > Andriy to suggest a fix. The problem comes about because the dmatest
> > module is now driven from debugfs, making it possible to unload the module
> > whilst a test run is in progress. In this case:
> > 
> > 	- The DMA threads will return from wait_event_freezable_timeout(...)
> > 	  due to kthread_should_stop() returning true, and subsequently
> > 	  report failure because done.done is false.
> > 
> > 	- The DMA engines may not be idle, so the asynchronous callback can
> > 	  be invoked after we've started cleaning up, explaining the NULL
> > 	  dereference I'm seeing.
> > 
> > The solutions are either fixing the module exit code to cope with concurrent
> > DMA transfers or to revert 77101ce578bb and not allow the channel threads to
> > return mid-transfer.
> We need to properly abort the channels on removal. This is already handled in
> the code but the kthread_stop is called after the transactions are aborted. It
> should be the other way round. Can you try with below patch

Unfortunately, I can trigger the exact same panic with this patch applied.

Isn't there a race between terminating the dmaengine transfers
(dmaengine_terminate_all) and killing the test threads (kthread_stop) where
a new transfer could be kicked off by dmatest_func?

Will


From khilman at linaro.org  Fri May 17 10:29:04 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 17 May 2013 07:29:04 -0700
Subject: [PATCH v3 0/6] ARM: OMAP2+: hwmod and SERIAL: Remove sysc
 handling from driver
In-Reply-To: <alpine.DEB.2.00.1305161831390.21357@utopia.booyaka.com> (Paul
 Walmsley's message of "Thu, 16 May 2013 18:32:43 +0000 (UTC)")
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
 <alpine.DEB.2.00.1305161831390.21357@utopia.booyaka.com>
Message-ID: <87txm1smrz.fsf@linaro.org>

Hi Paul,

Paul Walmsley <paul at pwsan.com> writes:

> On Wed, 15 May 2013, Rajendra Nayak wrote:
>
>> OMAP UART IP needs manual idle modes based on functional state of the
>> IP. Currently this is handled by the driver with function pointers
>> implemented in platform code.
>> 
>> This however breaks in case of device tree because of missing
>> idle handling. 
>> 
>> The series tries to address the issue and tries to remove complete
>> sysc handling from serial driver.
>
> These look good to me.  Will queue them for v3.10-rc once they pass local 
> testing here.

I reviewed and tested v2 of this (Rajendra forgot to add the tags in
v3) and also just sanity tested v3 of this on 4430/panda DT boot to
verify the console issue is resolved.  Feel free to add:

Reviewed-by: Kevin Hilman <khilman at linaro.org>
Tested-by: Kevin Hilman <khilman at linaro.org>  # OMAP4/Panda

Kevin


From arnd at arndb.de  Fri May 17 10:36:49 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 May 2013 16:36:49 +0200
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <518B77C1.70107@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305082148.10933.arnd@arndb.de> <518B77C1.70107@st.com>
Message-ID: <201305171636.49627.arnd@arndb.de>

On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
> On 08/05/13 20:48, Arnd Bergmann wrote:
> I agree, my initial approach was having a dedicated driver specific to
> ST syscon, however syscon seems to do things very much similar to what
> we want, so I have integrated those 3 functions in syscon.
> Am happy to go back with my first approach of adding ST specific syscon
> driver if no one is actually going to benefit with such a change to
> syscon driver.

That would at least be less controversial.

> > Can you describe how your syscon registers are laid out?
> On STiH416 SOC we have 9 SYSCONF(aka System Configuration
> Registers)named banks/groups, each bank has its own memory map.
> Each sysconf bank has number of 32 bit registers which vary from bank to
> bank, like sysconf bank "sbc" has range from SYSTEM_CONFIG0 to
> SYSTEM_CONFIG999 where as  sysconf bank "front" has range of
> SYSTEM_CONFIG1000 to SYSTEM_CONFIG1999 and so on.
> 
> Each register is assigned with a unique SYCONF number, example:
> SYSTEM_CONFIG100, SYSTEM_CONFIG101 , .. and so on.
> Each sysconf contains bits of the IP configurations wired-up to the
> sysconf register bits.

Ok.

> As example:
> 
> - Each pinctrl entry for set of 8 pins uses around 8-10 sysconfig
> register to control pinconf and pin functions.
> - IPs like Ethernet have few bit like Ethernet-Mode selection external
> or internal phyclk wired up to bits in sysconf registers,
> - Few clocks are controlled by sysconf registers.
> - Reset to IPs are wired up to bits of sysconf same registers.
> - ARM core soft reset is wired up to the sysconf registers...
> And most of the IPs have similar requirements ......
> 
> Total layout of the sysconf changes per SOC, and the bit arrangements
> aswell, however the core IP(pinctrl, etherenet ...) and logic to drive
> those bits remains exactly same.

It sounds like you really need a driver with high-level interfaces
for the bits that change by each core and are needed by otherwise
identical drivers, like the Ethernet driver you mention.

I would not go as far as you did describing the individual bits in
the device node using these however. That driver can be layered on
top of the existing syscon driver, but hardcode the bits for each
SoC it knows of.

For drivers that are essentially just wrappers around sysconf,
I would make them one driver per SoC and use a low-level interface
but still hardcode the offsets in the driver instead of using DT
to find the registers.

The pinctrl and reset drivers are examples of this.

> In general the requirements of the sysconf support to the SOC/driver
> support is.
> 1> It should be able to read/write a sysconf register bits without
> having to "if" each SOC in the code. So that code is totally abstracted.
> Which is currently achieved by passing the information from the device
> trees and the driver just uses the property to get it.

The goal sounds fine, just the method is a bit more complex than necessary
here I think.

> 2> The infrastructure should protect the claimed registers from
> over-writing by other drivers. We do this by claim-read/write-release
> style API.

I don't understand this part. Is it about atomicity of accesses to
32-bit registers when you only want to change a bit? That is something
the regmap interface handles already.

If this is about drivers touching registers they should not touch
in the first place, I think it should not be needed at all, because
that would be a driver bug, and you can't really protect yourself
from broken drivers anyway.

> 3> The driver should be able to set a group of sysconf registers bits to
> a particular values before initialises the IP. I was thinking of doing
> this in a same way as pinctrl state.

That does not fit well with the model we use for other subsystems. If possible,
try to use the existing abstractions for clock, regulator, pinctrl, reset,
etc. and call generic interfaces from the driver. When that does not work,
create a high-level function call from your sysconf driver to do a particular
thing (e.g. stih_sysconf_ethernet_set_phy_mode()) rather than set up random
bits from the driver.

	Arnd


From plagnioj at jcrosoft.com  Fri May 17 10:42:08 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 16:42:08 +0200
Subject: [PATCH 3/5] ARM: at91: sam9x5ek add udc DT support
In-Reply-To: <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368801730-31383-3-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5ek.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 19c8ebb..5e10027 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -52,6 +52,11 @@
 				status = "okay";
 			};
 
+			usb2: gadget at f803c000 {
+				atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
+
 			i2c0: i2c at f8010000 {
 				status = "okay";
 			};
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri May 17 10:42:07 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 16:42:07 +0200
Subject: [PATCH 2/5] ARM: at91: sam9x5 add udc DT support
In-Reply-To: <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368801730-31383-2-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   62 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9x5.c   |    2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599..01a815d 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -645,6 +645,68 @@
 				status = "disabled";
 			};
 
+			usb2: gadget at f803c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00500000 0x80000
+				       0xf803c000 0x400>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+			};
+
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x40>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec..2abee66 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 
 /*
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri May 17 10:42:10 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 16:42:10 +0200
Subject: [PATCH 5/5] ARM: at91: sam9m10g45ek add udc DT support
In-Reply-To: <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368801730-31383-5-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 89c50d1..17665ef 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -112,6 +112,11 @@
 					reg = <0>;
 				};
 			};
+
+			usb2: gadget at fff78000 {
+				atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri May 17 10:42:09 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 16:42:09 +0200
Subject: [PATCH 4/5] ARM: at91: sam9g45 add udc DT support
In-Reply-To: <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1368801730-31383-4-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g45.dtsi |   62 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9g45.c   |    2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index f0091af..fccc488 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -582,6 +582,68 @@
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
+
+			usb2: gadget at fff78000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00600000 0x80000
+				       0xfff78000 0x400>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..95a418a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+	CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri May 17 10:42:06 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 17 May 2013 16:42:06 +0200
Subject: [PATCH 1/5] usb: add Atmel USBA UDC DT support
In-Reply-To: <20130517141443.GB16804@game.jcrosoft.org>
References: <20130517141443.GB16804@game.jcrosoft.org>
Message-ID: <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>

Allow to compile the driver all the time if AT91 enabled.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 .../devicetree/bindings/usb/atmel-usb.txt          |   82 ++++++++
 drivers/usb/gadget/Kconfig                         |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                |  214 +++++++++++++++-----
 drivers/usb/gadget/atmel_usba_udc.h                |    1 +
 4 files changed, 244 insertions(+), 55 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 60bd215..878556b2 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -47,3 +47,85 @@ usb1: gadget at fffa4000 {
 	interrupts = <10 4>;
 	atmel,vbus-gpio = <&pioC 5 0>;
 };
+
+Atmel High-Speed USB device controller
+
+Required properties:
+ - compatible: Should be "atmel,at91sam9rl-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain macb interrupt
+ - ep childnode: To specifiy the number of endpoints and their properties.
+
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+Required child node properties:
+ - name: Name of the endpoint.
+ - reg: Num of the endpoint.
+ - atmel,fifo-size: Size of the fifo.
+ - atmel,nb-banks: Number of banks.
+ - atmel,can-dma: Boolean to specify if the endpoint support DMA.
+ - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
+
+usb2: gadget at fff78000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "atmel,at91sam9rl-udc";
+	reg = <0x00600000 0x80000
+	       0xfff78000 0x400>;
+	interrupts = <27 4>;
+	atmel,vbus-gpio = <&pioB 19 0>;
+
+	ep0 {
+		reg = <0>;
+		atmel,fifo-size = <64>;
+		atmel,nb-banks = <1>;
+	};
+
+	ep1 {
+		reg = <1>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep2 {
+		reg = <2>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep3 {
+		reg = <3>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+	};
+
+	ep4 {
+		reg = <4>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+	};
+
+	ep5 {
+		reg = <5>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep6 {
+		reg = <6>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 83300d9..5e47d50 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_LPC32XX
 
 config USB_ATMEL_USBA
 	tristate "Atmel USBA"
-	depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on AVR32 || ARCH_AT91
 	help
 	  USBA is the integrated high-speed USB Device controller on
 	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f2a970f..b3084b9 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -22,6 +22,8 @@
 #include <linux/usb/atmel_usba_udc.h>
 #include <linux/delay.h>
 #include <linux/platform_data/atmel.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 
 #include <asm/gpio.h>
 
@@ -1835,9 +1837,143 @@ static int atmel_usba_stop(struct usb_gadget *gadget,
 	return 0;
 }
 
-static int __init usba_udc_probe(struct platform_device *pdev)
+#ifdef CONFIG_OF
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	u32 val;
+	const char *name;
+	enum of_gpio_flags flags;
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *pp;
+	int i, ret;
+	struct usba_ep *eps, *ep;
+
+	udc->num_ep = 0;
+
+	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
+						&flags);
+	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+	pp = NULL;
+	while ((pp = of_get_next_child(np, pp)))
+		udc->num_ep++;
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	pp = NULL;
+	i = 0;
+	while ((pp = of_get_next_child(np, pp))) {
+		ep = &eps[i];
+
+		ret = of_property_read_u32(pp, "reg", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
+			goto err;
+		}
+		ep->index = val;
+
+		ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
+			goto err;
+		}
+		ep->fifo_size = val;
+
+		ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
+			goto err;
+		}
+		ep->nr_banks = val;
+
+		ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
+		ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
+
+		ret = of_property_read_string(pp, "name", &name);
+		ep->ep.name = name;
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.maxpacket = ep->fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+
+		i++;
+	}
+
+	return eps;
+err:
+	return ERR_PTR(ret);
+}
+#else
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	return ERR_PTR(-ENOSYS);
+}
+#endif
+
+static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
+						 struct usba_udc *udc)
 {
 	struct usba_platform_data *pdata = pdev->dev.platform_data;
+	struct usba_ep *eps;
+	int i;
+
+	if (!pdata)
+		return ERR_PTR(-ENXIO);
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	udc->vbus_pin = pdata->vbus_pin;
+	udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
+	udc->num_ep = pdata->num_ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	for (i = 0; i < pdata->num_ep; i++) {
+		struct usba_ep *ep = &eps[i];
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.name = pdata->ep[i].name;
+		ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+		ep->nr_banks = pdata->ep[i].nr_banks;
+		ep->index = pdata->ep[i].index;
+		ep->can_dma = pdata->ep[i].can_dma;
+		ep->can_isoc = pdata->ep[i].can_isoc;
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	}
+
+	return eps;
+}
+
+static int __init usba_udc_probe(struct platform_device *pdev)
+{
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
 	struct usba_udc *udc = &the_udc;
@@ -1845,7 +1981,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
 	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
-	if (!regs || !fifo || !pdata)
+	if (!regs || !fifo)
 		return -ENXIO;
 
 	irq = platform_get_irq(pdev, 0);
@@ -1891,46 +2027,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
 	clk_disable(pclk);
 
-	usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
-			  GFP_KERNEL);
-	if (!usba_ep)
-		goto err_alloc_ep;
-
-	the_udc.gadget.ep0 = &usba_ep[0].ep;
-
-	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
-	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
-	usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
-	usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
-	usba_ep[0].ep.ops = &usba_ep_ops;
-	usba_ep[0].ep.name = pdata->ep[0].name;
-	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
-	usba_ep[0].udc = &the_udc;
-	INIT_LIST_HEAD(&usba_ep[0].queue);
-	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
-	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
-	usba_ep[0].index = pdata->ep[0].index;
-	usba_ep[0].can_dma = pdata->ep[0].can_dma;
-	usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
-
-	for (i = 1; i < pdata->num_ep; i++) {
-		struct usba_ep *ep = &usba_ep[i];
-
-		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
-		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
-		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
-		ep->ep.ops = &usba_ep_ops;
-		ep->ep.name = pdata->ep[i].name;
-		ep->ep.maxpacket = pdata->ep[i].fifo_size;
-		ep->udc = &the_udc;
-		INIT_LIST_HEAD(&ep->queue);
-		ep->fifo_size = pdata->ep[i].fifo_size;
-		ep->nr_banks = pdata->ep[i].nr_banks;
-		ep->index = pdata->ep[i].index;
-		ep->can_dma = pdata->ep[i].can_dma;
-		ep->can_isoc = pdata->ep[i].can_isoc;
+	if (pdev->dev.of_node)
+		usba_ep = atmel_udc_of_init(pdev, udc);
+	else
+		usba_ep = usba_udc_pdata(pdev, udc);
 
-		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	if (IS_ERR(usba_ep)) {
+		ret = PTR_ERR(usba_ep);
+		goto err_alloc_ep;
 	}
 
 	ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
@@ -1941,16 +2045,12 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	}
 	udc->irq = irq;
 
-	if (gpio_is_valid(pdata->vbus_pin)) {
-		if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
-			udc->vbus_pin = pdata->vbus_pin;
-			udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
-
+	if (gpio_is_valid(udc->vbus_pin)) {
+		if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
 			ret = request_irq(gpio_to_irq(udc->vbus_pin),
 					usba_vbus_irq, 0,
 					"atmel_usba_udc", udc);
 			if (ret) {
-				gpio_free(udc->vbus_pin);
 				udc->vbus_pin = -ENODEV;
 				dev_warn(&udc->pdev->dev,
 					 "failed to request vbus irq; "
@@ -1969,16 +2069,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_add_udc;
 
 	usba_init_debugfs(udc);
-	for (i = 1; i < pdata->num_ep; i++)
+	for (i = 1; i < udc->num_ep; i++)
 		usba_ep_init_debugfs(udc, &usba_ep[i]);
 
 	return 0;
 
 err_add_udc:
-	if (gpio_is_valid(pdata->vbus_pin)) {
+	if (gpio_is_valid(udc->vbus_pin))
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
-		gpio_free(udc->vbus_pin);
-	}
 
 	free_irq(irq, udc);
 err_request_irq:
@@ -2001,19 +2099,17 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 {
 	struct usba_udc *udc;
 	int i;
-	struct usba_platform_data *pdata = pdev->dev.platform_data;
 
 	udc = platform_get_drvdata(pdev);
 
 	usb_del_gadget_udc(&udc->gadget);
 
-	for (i = 1; i < pdata->num_ep; i++)
+	for (i = 1; i < udc->num_ep; i++)
 		usba_ep_cleanup_debugfs(&usba_ep[i]);
 	usba_cleanup_debugfs(udc);
 
 	if (gpio_is_valid(udc->vbus_pin)) {
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
-		gpio_free(udc->vbus_pin);
 	}
 
 	free_irq(udc->irq, udc);
@@ -2026,11 +2122,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_udc_dt_ids[] = {
+	{ .compatible = "atmel,at91sam9rl-udc" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
+#endif
+
 static struct platform_driver udc_driver = {
 	.remove		= __exit_p(usba_udc_remove),
 	.driver		= {
 		.name		= "atmel_usba_udc",
 		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_udc_dt_ids),
 	},
 };
 
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index d65a618..6999a26 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -317,6 +317,7 @@ struct usba_udc {
 	int irq;
 	int vbus_pin;
 	int vbus_pin_inverted;
+	int num_ep;
 	struct clk *pclk;
 	struct clk *hclk;
 
-- 
1.7.10.4



From u.kleine-koenig at pengutronix.de  Fri May 17 11:17:01 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 17 May 2013 17:17:01 +0200
Subject: [PULL] add support for ARM-v7M
Message-ID: <20130517151701.GA8215@pengutronix.de>

Hello Russell,

The following changes since commit 73a09d212ec65b7068a283e6034fa05649d3d075:

  Merge branch 'for-next' of git://git.pengutronix.de/git/ukl/linux into devel-stable (2013-03-09 15:49:32 +0000)

are available in the git repository at:

  git://git.pengutronix.de/git/ukl/linux.git for-next

for you to fetch changes up to 6fae9cdafc92ae9958a3a45dd68205f72e3ad900:

  ARM: ARMv7-M: implement read_cpuid_ext (2013-05-17 11:44:40 +0200)

All but the last patch were in next since next-20130418 without issues.
The last patch fixes a problem in combination with 

	8164f7a (ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register)

which triggers a WARN_ON without an implemented read_cpuid_ext.

The branch merges fine into v3.10-rc1 and I'd be happy if you pulled it
for 3.11-rc1. The only missing piece to be able to run a Cortex-M3 is
the irqchip driver that will go in via Thomas Gleixner and platform
specific stuff.

Best regards
Uwe
----------------------------------------------------------------
Catalin Marinas (1):
      ARM: Add base support for ARMv7-M

Uwe Kleine-K?nig (3):
      ARM: ARMv7-M: Add support for exception handling
      ARM: ARMv7-M: Allow the building of new kernel port
      ARM: ARMv7-M: implement read_cpuid_ext

 arch/arm/Kconfig                   |   4 +-
 arch/arm/Kconfig-nommu             |   2 +-
 arch/arm/Makefile                  |   1 +
 arch/arm/include/asm/assembler.h   |  17 +++-
 arch/arm/include/asm/cputype.h     |  44 ++++++++++-
 arch/arm/include/asm/glue-cache.h  |  27 +++++++
 arch/arm/include/asm/glue-df.h     |   8 ++
 arch/arm/include/asm/glue-proc.h   |   9 +++
 arch/arm/include/asm/irqflags.h    |  22 ++++--
 arch/arm/include/asm/ptrace.h      |   4 +
 arch/arm/include/asm/system_info.h |   1 +
 arch/arm/include/asm/v7m.h         |  44 +++++++++++
 arch/arm/include/uapi/asm/ptrace.h |  35 +++++++--
 arch/arm/kernel/Makefile           |   8 +-
 arch/arm/kernel/entry-common.S     |   4 +
 arch/arm/kernel/entry-header.S     | 124 +++++++++++++++++++++++++++++
 arch/arm/kernel/entry-v7m.S        | 143 +++++++++++++++++++++++++++++++++
 arch/arm/kernel/head-nommu.S       |  10 ++-
 arch/arm/kernel/setup.c            |  17 +++-
 arch/arm/kernel/traps.c            |   8 ++
 arch/arm/mm/Kconfig                |  21 ++++-
 arch/arm/mm/Makefile               |   2 +
 arch/arm/mm/cache-nop.S            |  50 ++++++++++++
 arch/arm/mm/nommu.c                |   7 ++
 arch/arm/mm/proc-v7m.S             | 157 +++++++++++++++++++++++++++++++++++++
 25 files changed, 742 insertions(+), 27 deletions(-)
 create mode 100644 arch/arm/include/asm/v7m.h
 create mode 100644 arch/arm/kernel/entry-v7m.S
 create mode 100644 arch/arm/mm/cache-nop.S
 create mode 100644 arch/arm/mm/proc-v7m.S

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From lorenzo.pieralisi at arm.com  Fri May 17 11:20:43 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:43 +0100
Subject: [RFC PATCH v4 00/18] ARM: DT cpu bindings updates
Message-ID: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>

This patchset is an update of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165219.html

v4 changes:

- Replaced WARN* with pr_warn
- Removed tmp_map in arm_dt_init_cpu_maps()
- Rebased against 3.10-rc1
- Patched additional atmel and sunxi dts files
- Removed BUG_ON on !bootcpu_valid, now flagged up as an error
- Added code to reset invalid entries in cpu_logical_map after DT parsing

v3 changes:

- More dts fixes of in-kernel dts
- Defined ARM v8 behaviour with different cpus node #address-cells
- Added pre ARM11 processors suffixes in the cpu node compatible list
- Reordered series
- Reworded #address-cells definition
- Added ARM v8 - cores running on AArch32 bindings example
- Moved WARN* calls on one line to prevent grepping issues

v2 changes:

- Reworded DT cpu bindings
- Split the set, with per-mach specific dts updates
- Updated cpu node compatible string list
- Defined behaviour of OS running on v8 in AArch32

The introduction of DT cpus/cpu bindings for ARM requires well established
rules to enforce the reg property definition for 32-bit and 64-bit ARM
processors, inclusive of legacy and current uniprocessor/SMP systems.

ARM 64 bit architecture also requires dtb compiled for 64-bit configurations
to be reused for kernels running in 32 bit mode, so the cpus/cpu bindings
specification must be made compliant to cope with this configuration.

Patch #1-#2 of this series are fixes and are included to have a clean patch
series and should get reviewed and merged separately.

Patch #3-18, along with some kernel fixes related to DT parsing function,
update the cpu node bindings and in kernel dts files to cope with legacy,
current and upcoming ARM systems.

In-kernel device tree source files are updated to comply with the latest
specification, so thorough testing is required in order to validate all
changes on all affected ARM systems, in particular systems with exotic
MPIDR configurations that are likely to break with the changes provided.

Code relying on the reg property size to be 4-bytes must be updated so that
dtbs compiled for 64-bit kernels can also be used to boot a 32-bit system.

Lorenzo Pieralisi (18):
  ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
  ARM: kernel: fix __cpu_logical_map default initialization
  Documentation: devicetree: arm: cpus/cpu nodes bindings updates
  ARM: dts: am33xx: cpus/cpu nodes dts updates
  ARM: dts: armada-370-xp: cpus/cpu node dts updates
  ARM: dts: at91: cpus/cpu node dts updates
  ARM: dts: exynos5440: cpus/cpu nodes dts updates
  ARM: dts: imx: cpus/cpu nodes dts updates
  ARM: dts: lpc32xx: cpus/cpu nodes dts updates
  ARM: dts: omap: cpus/cpu nodes dts updates
  ARM: dts: picoxcell: cpus/cpu nodes dts updates
  ARM: dts: prima2: cpus/cpu node dts updates
  ARM: dts: pxa2xx: cpus/cpu nodes dts updates
  ARM: dts: r8a7740: cpus/cpu nodes dts updates
  ARM: dts: sh7372: cpus/cpu nodes dts updates
  ARM: dts: spear: cpus/cpu nodes dts updates
  ARM: dts: sunxi: cpus/cpu nodes dts updates
  ARM: DT: kernel: DT cpus/cpu node bindings update

 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 arch/arm/boot/dts/am33xx.dtsi                  |   4 +
 arch/arm/boot/dts/armada-370-xp.dtsi           |   4 +
 arch/arm/boot/dts/at91rm9200.dtsi              |   6 +-
 arch/arm/boot/dts/at91sam9260.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9263.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9g45.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9n12.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9x5.dtsi              |   8 +-
 arch/arm/boot/dts/exynos5440.dtsi              |   4 +
 arch/arm/boot/dts/imx23.dtsi                   |   8 +-
 arch/arm/boot/dts/imx28.dtsi                   |   8 +-
 arch/arm/boot/dts/imx6dl.dtsi                  |   2 +
 arch/arm/boot/dts/imx6q.dtsi                   |   4 +
 arch/arm/boot/dts/lpc32xx.dtsi                 |   8 +-
 arch/arm/boot/dts/omap2.dtsi                   |   6 +-
 arch/arm/boot/dts/omap3.dtsi                   |   5 +
 arch/arm/boot/dts/omap4.dtsi                   |   7 +
 arch/arm/boot/dts/omap5.dtsi                   |   7 +
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi         |   8 +-
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi         |   8 +-
 arch/arm/boot/dts/prima2.dtsi                  |   2 +
 arch/arm/boot/dts/pxa2xx.dtsi                  |   7 +-
 arch/arm/boot/dts/r8a7740.dtsi                 |   4 +
 arch/arm/boot/dts/sama5d3.dtsi                 |   2 +
 arch/arm/boot/dts/sh7372.dtsi                  |   5 +
 arch/arm/boot/dts/spear13xx.dtsi               |   2 +
 arch/arm/boot/dts/spear3xx.dtsi                |   8 +-
 arch/arm/boot/dts/spear600.dtsi                |   8 +-
 arch/arm/boot/dts/sun4i-a10.dtsi               |   2 +
 arch/arm/boot/dts/sun5i-a13.dtsi               |   2 +
 arch/arm/include/asm/cputype.h                 |   2 +
 arch/arm/include/asm/smp_plat.h                |   2 +-
 arch/arm/kernel/devtree.c                      | 149 ++++----
 arch/arm/kernel/setup.c                        |   2 +-
 35 files changed, 646 insertions(+), 139 deletions(-)

-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:46 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:46 +0100
Subject: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes
 bindings updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-4-git-send-email-lorenzo.pieralisi@arm.com>

In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.

Main changes:
    - adds 64-bit bindings
    - define usage of #address-cells
    - define 32/64 dts compatibility settings
    - defines behaviour on pre and post v7 uniprocessor systems
    - adds ARM 11MPcore specific reg property definition

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..3fc0c11 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -1,77 +1,442 @@
-* ARM CPUs binding description
+=================
+ARM CPUs bindings
+=================
 
 The device tree allows to describe the layout of CPUs in a system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type:	must be "cpu"
-- reg:		property matching the CPU MPIDR[23:0] register bits
-		reg[31:24] bits must be set to 0
-- compatible:	should be one of:
-		"arm,arm1020"
-		"arm,arm1020e"
-		"arm,arm1022"
-		"arm,arm1026"
-		"arm,arm720"
-		"arm,arm740"
-		"arm,arm7tdmi"
-		"arm,arm920"
-		"arm,arm922"
-		"arm,arm925"
-		"arm,arm926"
-		"arm,arm940"
-		"arm,arm946"
-		"arm,arm9tdmi"
-		"arm,cortex-a5"
-		"arm,cortex-a7"
-		"arm,cortex-a8"
-		"arm,cortex-a9"
-		"arm,cortex-a15"
-		"arm,arm1136"
-		"arm,arm1156"
-		"arm,arm1176"
-		"arm,arm11mpcore"
-		"faraday,fa526"
-		"intel,sa110"
-		"intel,sa1100"
-		"marvell,feroceon"
-		"marvell,mohawk"
-		"marvell,xsc3"
-		"marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+================================
+Convention used in this document
+================================
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+  the reg property contained in bits 7 down to 0
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+	Description: Container of cpu nodes
+
+	The node name must be "cpus".
+
+	A cpus node must define the following properties:
+
+	- #address-cells
+		Usage: required
+		Value type: <u32>
+
+		Definition depends on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  value must be 0.
+			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
+			  value must be 1.
+			# On ARM v8 64-bit systems value must be set to 1
+			  or 2. Refer to the cpu node's reg property
+			  description for allowed configurations.
+
+	- #size-cells
+		Usage: required
+		Value type: <u32>
+		Definition: must be set to 0
+
+- cpu node
+
+	Description: Describes a CPU in an ARM based system
+
+	PROPERTIES
+
+	- device_type
+		Usage: required
+		Value type: <string>
+		Definition: must be "cpu"
+	- reg
+		Usage and definition depend on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  this property is optional since they do not define
+			  any register that provides a CPU identifier.
+			  Any value set in the reg property for these CPUs
+			  should be ignored.
+
+			# On ARM 11 MPcore based systems this property is
+			  required and matches the CPUID[11:0] register bits.
+
+			  Bits [11:0] in the reg cell must be set to
+			  bits [11:0] in CPU ID register.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On 32-bit ARM v7 or later systems this property is
+			  required and matches the CPU MPIDR[23:0] register
+			  bits.
+
+			  Bits [23:0] in the reg cell must be set to
+			  bits [23:0] in MPIDR.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On ARM v8 64-bit systems, where the reg property
+			  size can be 1 or 2 cells (as defined by cpus node's
+			  #address-cells property), this property is
+			  required and matches:
+
+			  - On systems running the OS in AArch32:
+
+			    * If the cpus node's #address-cells value is 2:
+
+			      The first reg cell must be set to 0.
+
+			      The second reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cells must be set to 0.
+
+			    * If the cpus node's #address-cells value is 1:
+
+			      Bits [23:0] in the reg cell must be set to
+			      bits [23:0] in MPIDR_EL1.
+
+			      All other bits in the reg cell must be 0.
+
+			  - On systems running the OS in AArch64:
+
+			    * If the cpus node's #address-cells value is 2:
+
+			      The first reg cell bits [7:0] must be set to
+			      bits [39:32] of MPIDR_EL1.
+
+			      The second reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cells must be set to 0.
+
+			    * If the cpus node's #address-cells value is 1:
+
+			      MPIDR_EL1[63:32] is 0 on all processors in the
+			      system.
+
+			      The reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cell must be set to 0.
+
+	- compatible:
+		Usage: required
+		Value type: <string>
+		Definition: should be one of:
+			    "arm,arm710t"
+			    "arm,arm720t"
+			    "arm,arm740t"
+			    "arm,arm7ej-s"
+			    "arm,arm7tdmi"
+			    "arm,arm7tdmi-s"
+			    "arm,arm9es"
+			    "arm,arm9ej-s"
+			    "arm,arm920t"
+			    "arm,arm922t"
+			    "arm,arm925"
+			    "arm,arm926e-s"
+			    "arm,arm926ej-s"
+			    "arm,arm940t"
+			    "arm,arm946e-s"
+			    "arm,arm966e-s"
+			    "arm,arm968e-s"
+			    "arm,arm9tdmi"
+			    "arm,arm1020e"
+			    "arm,arm1020t"
+			    "arm,arm1022e"
+			    "arm,arm1026ej-s"
+			    "arm,arm1136j-s"
+			    "arm,arm1136jf-s"
+			    "arm,arm1156t2-s"
+			    "arm,arm1156t2f-s"
+			    "arm,arm1176jzf"
+			    "arm,arm1176jz-s"
+			    "arm,arm1176jzf-s"
+			    "arm,arm11mpcore"
+			    "arm,cortex-a5"
+			    "arm,cortex-a7"
+			    "arm,cortex-a8"
+			    "arm,cortex-a9"
+			    "arm,cortex-a15"
+			    "arm,cortex-a53"
+			    "arm,cortex-a57"
+			    "arm,cortex-m0"
+			    "arm,cortex-m0+"
+			    "arm,cortex-m1"
+			    "arm,cortex-m3"
+			    "arm,cortex-m4"
+			    "arm,cortex-r4"
+			    "arm,cortex-r5"
+			    "arm,cortex-r7"
+			    "faraday,fa526"
+			    "intel,sa110"
+			    "intel,sa1100"
+			    "marvell,feroceon"
+			    "marvell,mohawk"
+			    "marvell,pj4"
+			    "marvell,sheeva-v7"
+			    "marvell,xsc3"
+			    "marvell,xscale"
+			    "qcom,krait"
+			    "qcom,scorpion"
+	- enable-method
+		Value type: <stringlist>
+		Usage and definition depend on ARM architecture version and
+		configuration:
+			# On ARM v8 64-bit systems running the OS in AArch64,
+			  this property is required and must be one of:
+			     "spin-table"
+			     "psci"
+			# On ARM 32-bit systems or ARM v8 systems running
+			  the OS in AArch32 this property is prohibited.
+
+	- cpu-release-addr
+		Usage: required for systems that have an "enable-method"
+		       property value of "spin-table".
+		Value type: <prop-encoded-array>
+		Definition:
+			# On ARM v8 64-bit systems must be a two cell
+			  property identifying a 64-bit zero-initialised
+			  memory location.
+
+Example 1 (dual-cluster big.LITTLE system 32-bit):
 
 	cpus {
 		#size-cells = <0>;
 		#address-cells = <1>;
 
-		CPU0: cpu at 0 {
+		cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 		};
 
-		CPU1: cpu at 1 {
+		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 		};
 
-		CPU2: cpu at 100 {
+		cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 		};
 
-		CPU3: cpu at 101 {
+		cpu at 101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 		};
 	};
+
+Example 2 (Cortex-A8 uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0x0>;
+		};
+	};
+
+Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <0>;
+
+		cpu {
+			device_type = "cpu";
+			compatible = "arm,arm926ej-s";
+		};
+	};
+
+Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+};
+
+Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+	};
+
+	cpu at 1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+	};
+
+	cpu at 100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+	};
+
+	cpu at 101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+	};
+};
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:50 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:50 +0100
Subject: [RFC PATCH v4 07/18] ARM: dts: exynos5440: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-8-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/exynos5440.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..646677e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -38,18 +38,22 @@
 		#size-cells = <0>;
 
 		cpu at 0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 		};
 		cpu at 1 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 		};
 		cpu at 2 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 		};
 		cpu at 3 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 		};
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:48 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:48 +0100
Subject: [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts
 updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-6-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..2407903 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -23,8 +23,12 @@
 	compatible = "marvell,armada-370-xp";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu at 0 {
 			compatible = "marvell,sheeva-v7";
+			device_type = "cpu";
+			reg = <0>;
 		};
 	};
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:47 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:47 +0100
Subject: [RFC PATCH v4 04/18] ARM: dts: am33xx: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-5-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/am33xx.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b..6827853 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -26,8 +26,12 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu at 0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0>;
 
 			/*
 			 * To consider voltage drop between PMIC and SoC,
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:44 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:44 +0100
Subject: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip
 non-cpu nodes
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-2-git-send-email-lorenzo.pieralisi@arm.com>

The introduction of the cpu-map topology node in the cpus node implies
that cpus node might have children that are not cpu nodes. The DT
parsing code needs updating otherwise it would check for cpu nodes
properties in nodes that are not required to contain them, resulting
in warnings that have no bearing on bindings defined in the dts source file.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/kernel/devtree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..904cad5 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
 	for_each_child_of_node(cpus, cpu) {
 		u32 hwid;
 
+		if (of_node_cmp(cpu->type, "cpu"))
+			continue;
+
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
 		 * A device tree containing CPU nodes with missing "reg"
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:56 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:56 +0100
Subject: [RFC PATCH v4 13/18] ARM: dts: pxa2xx: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-14-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/pxa2xx.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad3..a5e90f0 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
 	};
 
 	cpus {
-		cpu at 0 {
-			compatible = "arm,xscale";
+		#address-cells = <0>;
+		#size-cells = <0>;
+		cpu {
+			compatible = "marvell,xscale";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:45 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:45 +0100
Subject: [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default
 initialization
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-3-git-send-email-lorenzo.pieralisi@arm.com>

The __cpu_logical_map array is statically initialized to 0, which is a valid
MPIDR value. To prevent issues with the current implementation, this patch
defines an MPIDR_INVALID value, and statically initializes the
__cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
tmp_map array used to stash DT reg properties while parsing DT are initialized
with the MPIDR_INVALID value as well for consistency.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
CC: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/cputype.h  | 2 ++
 arch/arm/include/asm/smp_plat.h | 2 +-
 arch/arm/kernel/devtree.c       | 2 +-
 arch/arm/kernel/setup.c         | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712..dba62cb 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -32,6 +32,8 @@
 
 #define MPIDR_HWID_BITMASK 0xFFFFFF
 
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6..e789832 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
 /*
  * Logical CPU mapping.
  */
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
 #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
 /*
  * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 904cad5..0905502 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6ae71b7..eeac924 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -457,7 +457,7 @@ void notrace cpu_init(void)
 	    : "r14");
 }
 
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 
 void __init smp_setup_processor_id(void)
 {
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:57 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:57 +0100
Subject: [RFC PATCH v4 14/18] ARM: dts: r8a7740: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-15-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/r8a7740.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35..8a831e9 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,12 @@
 	compatible = "renesas,r8a7740";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu at 0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 };
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:21:00 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:21:00 +0100
Subject: [RFC PATCH v4 17/18] ARM: dts: sunxi: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-18-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
 arch/arm/boot/dts/sun5i-a13.dtsi | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..39a8f61 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,7 +17,9 @@
 
 	cpus {
 		cpu at 0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a8";
+			reg = <0x0>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f..00a2637 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -18,7 +18,9 @@
 
 	cpus {
 		cpu at 0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a8";
+			reg = <0x0>;
 		};
 	};
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:21:01 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:21:01 +0100
Subject: [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-19-git-send-email-lorenzo.pieralisi@arm.com>

DT cpu map parsing code must be made compliant with the latest cpus/cpu
nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
function with checks and additional parsing rules.

Uniprocessor systems predating v7 do not parse the cpus node at all
since the reg property is meaningless on those systems.

Device trees for 64-bit systems can be taken as device tree input also
for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
are zeroed as required in the respective fields and detects automatically
the cpus node #address-cells value so that device tree written for
64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
be taken as input. The correct device tree entries are to be set up by the
boot loader, kernel code just checks that device tree entries in the cpus
node are as expected for a 32-bit CPU (reg[63:24] == 0).

cpu node entries with invalid reg property or containing duplicates are
ignored and the device tree parsing is not stopped anymore when such
entries are encountered, the device tree cpu node entry is just skipped.

A device tree with cpu nodes missing the boot CPU MPIDR is considered
an error and the kernel flags this up as such to trigger firmware updates.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 58 deletions(-)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 0905502..80d6cf24 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -23,6 +23,7 @@
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/smp_plat.h>
+#include <asm/system_info.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
  */
 void __init arm_dt_init_cpu_maps(void)
 {
-	/*
-	 * Temp logical map is initialized with UINT_MAX values that are
-	 * considered invalid logical map entries since the logical map must
-	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
-	 * read as 0.
-	 */
 	struct device_node *cpu, *cpus;
-	u32 i, j, cpuidx = 1;
+	u32 i, ac, cpuidx = 1;
+	int len;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 
-	if (!cpus)
+	if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
 		return;
 
+	if (of_property_read_u32(cpus, "#address-cells", &ac)) {
+		pr_warn("%s invalid #address-cells\n", cpus->full_name);
+		ac = of_n_addr_cells(cpus);
+	}
+	/*
+	 * The boot CPU knows its MPIDR and initialize it
+	 * to allow DT boot CPU detection.
+	 */
+	cpu_logical_map(0) = mpidr;
+
 	for_each_child_of_node(cpus, cpu) {
-		u32 hwid;
+		u64 hwid64;
+		u32 hwid32;
+		const __be32 *prop;
 
 		if (of_node_cmp(cpu->type, "cpu"))
 			continue;
 
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
-		 * A device tree containing CPU nodes with missing "reg"
-		 * properties is considered invalid to build the
-		 * cpu_logical_map.
+		 * A CPU node with missing or wrong "reg" property is
+		 * considered invalid to build a cpu_logical_map entry.
 		 */
-		if (of_property_read_u32(cpu, "reg", &hwid)) {
-			pr_debug(" * %s missing reg property\n",
-				     cpu->full_name);
-			return;
+		prop = of_get_property(cpu, "reg", &len);
+		if (!prop || len < (ac * sizeof(*prop))) {
+			pr_warn(" * %s node missing/wrong reg property, skipped\n",
+				cpu->full_name);
+				goto next;
 		}
 
 		/*
-		 * 8 MSBs must be set to 0 in the DT since the reg property
-		 * defines the MPIDR[23:0].
+		 * Always read reg as u64 value.
+		 * For dts with #address-cells == 1 hwid64[63:32]
+		 * will be set to 0 by of_read_number.
+		 * Toss away the top 32 bits and store value in hwid32.
 		 */
-		if (hwid & ~MPIDR_HWID_BITMASK)
-			return;
-
+		hwid32 = hwid64 = of_read_number(prop, ac);
+		/*
+		 * hwid64[63:24] must be always be 0 since the reg
+		 * property defines the MPIDR[23:0] bits regardless
+		 * of the cpus node #address-cells value.
+		 */
+		if (hwid64 & ~MPIDR_HWID_BITMASK) {
+			pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
+				cpu->full_name, hwid64);
+			goto next;
+		}
 		/*
 		 * Duplicate MPIDRs are a recipe for disaster.
 		 * Scan all initialized entries and check for
-		 * duplicates. If any is found just bail out.
-		 * temp values were initialized to UINT_MAX
-		 * to avoid matching valid MPIDR[23:0] values.
+		 * duplicates. If any is found just ignore the CPU.
+		 * Boot CPU at logical index 0 is not checked to
+		 * allow self contained boot CPU detection logic.
 		 */
-		for (j = 0; j < cpuidx; j++)
-			if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
-						     "properties in the DT\n"))
-				return;
+		for (i = 1; i < cpuidx; i++)
+			if (cpu_logical_map(i) == hwid32) {
+				pr_warn(" * %s node duplicate cpu reg property, skipped\n",
+					cpu->full_name);
+				goto next;
+			}
 
 		/*
-		 * Build a stashed array of MPIDR values. Numbering scheme
-		 * requires that if detected the boot CPU must be assigned
-		 * logical id 0. Other CPUs get sequential indexes starting
-		 * from 1. If a CPU node with a reg property matching the
-		 * boot CPU MPIDR is detected, this is recorded so that the
-		 * logical map built from DT is validated and can be used
-		 * to override the map created in smp_setup_processor_id().
+		 * If a CPU node with a reg property matching the
+		 * cpu_logical_map(0) is detected, this is recorded so
+		 * that the bootcpu_valid condition can be checked when
+		 * DT scanning is completed. Duplicate boot cpu entries
+		 * are flagged up if detected.
 		 */
-		if (hwid == mpidr) {
-			i = 0;
-			bootcpu_valid = true;
-		} else {
-			i = cpuidx++;
+		if (hwid32 == cpu_logical_map(0)) {
+			if (bootcpu_valid) {
+				pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
+					cpu->full_name);
+			} else {
+				bootcpu_valid = true;
+			}
+			goto next;
 		}
+		/*
+		 * Build cpu_logical_map array. Numbering scheme
+		 * requires that boot CPU is assigned logical id 0.
+		 * Other CPUs get sequential indexes starting from 1.
+		 */
+		i = cpuidx++;
 
-		if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
-					       "max cores %u, capping them\n",
-					       cpuidx, nr_cpu_ids)) {
+		if (cpuidx > nr_cpu_ids) {
+			pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
+				cpuidx, nr_cpu_ids);
 			cpuidx = nr_cpu_ids;
-			break;
+			goto next;
 		}
 
-		tmp_map[i] = hwid;
+		cpu_logical_map(i) = hwid32;
+		set_cpu_possible(i, true);
+		pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
+next:	;
 	}
-
-	if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
-				 "fall back to default cpu_logical_map\n"))
-		return;
+	/*
+	 * A DT missing the boot CPU MPIDR is a really bad omen
+	 * Flag it up as such.
+	 */
+	if (!bootcpu_valid)
+		pr_warn("DT missing boot cpu node\n");
 
 	/*
-	 * Since the boot CPU node contains proper data, and all nodes have
-	 * a reg property, the DT CPU list can be considered valid and the
-	 * logical map created in smp_setup_processor_id() can be overridden
+	 * Since the DT might contain fewer entries than NR_CPUS,
+	 * cpu_logical_map entries initialized in smp_setup_processor_id()
+	 * but not found in the DT must be overriden with MPIDR_INVALID
+	 * values to make sure the cpu_logical_map does not contain stale
+	 * MPIDR values.
 	 */
-	for (i = 0; i < cpuidx; i++) {
-		set_cpu_possible(i, true);
-		cpu_logical_map(i) = tmp_map[i];
-		pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
-	}
+	for (i = cpuidx; i < nr_cpu_ids; i++)
+		cpu_logical_map(i) = MPIDR_INVALID;
 }
 
 /**
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:58 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:58 +0100
Subject: [RFC PATCH v4 15/18] ARM: dts: sh7372: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-16-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/sh7372.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..7bf020e 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
 	compatible = "renesas,sh7372";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu at 0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 };
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:55 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:55 +0100
Subject: [RFC PATCH v4 12/18] ARM: dts: prima2: cpus/cpu node dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-13-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/boot/dts/prima2.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..02edd89 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
 		#size-cells = <0>;
 
 		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0x0>;
 			d-cache-line-size = <32>;
 			i-cache-line-size = <32>;
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:51 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:51 +0100
Subject: [RFC PATCH v4 08/18] ARM: dts: imx: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-9-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx23.dtsi  | 8 ++++++--
 arch/arm/boot/dts/imx28.dtsi  | 8 ++++++--
 arch/arm/boot/dts/imx6dl.dtsi | 2 ++
 arch/arm/boot/dts/imx6q.dtsi  | 4 ++++
 4 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0..587ceef 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
 	};
 
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb..4c10a19 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
 	};
 
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a..62dc781 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
 
 		cpu at 0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu at 1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e6758..dc54a72 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
 
 		cpu at 0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 			operating-points = <
@@ -39,18 +40,21 @@
 
 		cpu at 1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu at 2 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <2>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu at 3 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <3>;
 			next-level-cache = <&L2>;
 		};
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:54 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:54 +0100
Subject: [RFC PATCH v4 11/18] ARM: dts: picoxcell: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-12-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 ++++----
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c20..533919e 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
 	#size-cells = <1>;
 
 	cpus {
-		#address-cells = <1>;
+		#address-cells = <0>;
 		#size-cells = <0>;
 
-		cpu at 0 {
-			compatible = "arm,1176jz-s";
+		cpu {
+			compatible = "arm,arm1176jz-s";
+			device_type = "cpu";
 			clock-frequency = <400000000>;
-			reg = <0>;
 			d-cache-line-size = <32>;
 			d-cache-size = <32768>;
 			i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d..ab3e800 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
 	#size-cells = <1>;
 
 	cpus {
-		#address-cells = <1>;
+		#address-cells = <0>;
 		#size-cells = <0>;
 
-		cpu at 0 {
-			compatible = "arm,1176jz-s";
+		cpu {
+			compatible = "arm,arm1176jz-s";
+			device_type = "cpu";
 			cpu-clock = <&arm_clk>, "cpu";
-			reg = <0>;
 			d-cache-line-size = <32>;
 			d-cache-size = <32768>;
 			i-cache-line-size = <32>;
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:59 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:59 +0100
Subject: [RFC PATCH v4 16/18] ARM: dts: spear: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-17-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Viresh Kumar <viresh.kumar at linaro.org>
---
 arch/arm/boot/dts/spear13xx.dtsi | 2 ++
 arch/arm/boot/dts/spear3xx.dtsi  | 8 ++++++--
 arch/arm/boot/dts/spear600.dtsi  | 8 ++++++--
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd..4382547 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
 
 		cpu at 0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu at 1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d..f0e3fcf 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
 	interrupt-parent = <&vic>;
 
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc..9f60a7b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
 	compatible = "st,spear600";
 
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:49 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:49 +0100
Subject: [RFC PATCH v4 06/18] ARM: dts: at91: cpus/cpu node dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-7-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
 arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
 arch/arm/boot/dts/sama5d3.dtsi     | 2 ++
 7 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..0af879a 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -35,8 +35,12 @@
 		ssc2 = &ssc2;
 	};
 	cpus {
-		cpu at 0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
 			compatible = "arm,arm920t";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..e1ba7ea 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -32,8 +32,12 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab..fcd38f8 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -29,8 +29,12 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a73..479a062 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -35,8 +35,12 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3de8e6d..01df681 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -31,8 +31,12 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..6d8bd671 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -33,8 +33,12 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..5325371 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -36,7 +36,9 @@
 	};
 	cpus {
 		cpu at 0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a5";
+			reg = <0x0>;
 		};
 	};
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:53 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:53 +0100
Subject: [RFC PATCH v4 10/18] ARM: dts: omap: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-11-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/omap2.dtsi | 6 +++++-
 arch/arm/boot/dts/omap3.dtsi | 5 +++++
 arch/arm/boot/dts/omap4.dtsi | 7 +++++++
 arch/arm/boot/dts/omap5.dtsi | 7 +++++++
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..4aac404 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
 	};
 
 	cpus {
-		cpu at 0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
 			compatible = "arm,arm1136jf-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..ba05d7f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu at 0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..33a9450 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu at 0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			next-level-cache = <&L2>;
+			reg = <0x0>;
 		};
 		cpu at 1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			next-level-cache = <&L2>;
+			reg = <0x1>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..35a6536 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -34,11 +34,18 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu at 0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
+			reg = <0x0>;
 		};
 		cpu at 1 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
+			reg = <0x1>;
 		};
 	};
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 17 11:20:52 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 16:20:52 +0100
Subject: [RFC PATCH v4 09/18] ARM: dts: lpc32xx: cpus/cpu nodes dts updates
In-Reply-To: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1368804061-4421-10-git-send-email-lorenzo.pieralisi@arm.com>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f48..3abebb7 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
 	interrupt-parent = <&mic>;
 
 	cpus {
-		cpu at 0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.8.2.2




From liuj97 at gmail.com  Fri May 17 11:45:03 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Fri, 17 May 2013 23:45:03 +0800
Subject: [PATCH v7,
 part3 01/16] mm: change signature of free_reserved_area() to fix
 building warnings
In-Reply-To: <1368805518-2634-1-git-send-email-jiang.liu@huawei.com>
References: <1368805518-2634-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368805518-2634-2-git-send-email-jiang.liu@huawei.com>

Change signature of free_reserved_area() according to Russell King's
suggestion to fix following build warnings:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
  free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
  ^
In file included from include/linux/mman.h:4:0,
                 from arch/arm/mm/init.c:15:
include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
 extern unsigned long free_reserved_area(unsigned long start, unsigned long end,

   mm/page_alloc.c: In function 'free_reserved_area':
>> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
   In file included from arch/mips/include/asm/page.h:49:0,
                    from include/linux/mmzone.h:20,
                    from include/linux/gfp.h:4,
                    from include/linux/mm.h:8,
                    from mm/page_alloc.c:18:
   arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
   mm/page_alloc.c: In function 'free_area_init_nodes':
   mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Reported-by: Arnd Bergmann <arnd at arndb.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-mm at kvack.org
---
 arch/alpha/kernel/sys_nautilus.c |  4 ++--
 arch/alpha/mm/init.c             |  2 +-
 arch/arc/mm/init.c               |  2 +-
 arch/arm/mm/init.c               |  2 +-
 arch/arm64/mm/init.c             |  2 +-
 arch/avr32/mm/init.c             |  2 +-
 arch/blackfin/mm/init.c          |  2 +-
 arch/c6x/mm/init.c               |  2 +-
 arch/frv/mm/init.c               |  2 +-
 arch/h8300/mm/init.c             |  2 +-
 arch/ia64/mm/init.c              |  3 +--
 arch/m32r/mm/init.c              |  2 +-
 arch/m68k/mm/init.c              |  2 +-
 arch/metag/mm/init.c             |  3 ++-
 arch/microblaze/mm/init.c        |  2 +-
 arch/mips/mm/init.c              |  3 ++-
 arch/mn10300/mm/init.c           |  3 ++-
 arch/openrisc/mm/init.c          |  2 +-
 arch/parisc/mm/init.c            |  3 ++-
 arch/powerpc/kernel/kvm.c        |  2 +-
 arch/powerpc/mm/mem.c            |  2 +-
 arch/s390/mm/init.c              |  3 ++-
 arch/score/mm/init.c             |  3 ++-
 arch/sh/mm/init.c                |  2 +-
 arch/sparc/mm/init_32.c          |  4 ++--
 arch/sparc/mm/init_64.c          |  4 ++--
 arch/um/kernel/mem.c             |  2 +-
 arch/unicore32/mm/init.c         |  2 +-
 arch/xtensa/mm/init.c            |  2 +-
 include/linux/mm.h               |  5 ++---
 mm/page_alloc.c                  | 16 ++++++++--------
 31 files changed, 48 insertions(+), 44 deletions(-)

diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 1d4aabf..891bd27 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -238,8 +238,8 @@ nautilus_init_pci(void)
 	if (pci_mem < memtop)
 		memtop = pci_mem;
 	if (memtop > alpha_mv.min_mem_address) {
-		free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
-				   (unsigned long)__va(memtop), 0, NULL);
+		free_reserved_area(__va(alpha_mv.min_mem_address),
+				   __va(memtop), 0, NULL);
 		printk("nautilus_init_pci: %ldk freed\n",
 			(memtop - alpha_mv.min_mem_address) >> 10);
 	}
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 0ba85ee..d54848d 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -326,6 +326,6 @@ free_initmem(void)
 void
 free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 4a17736..dce02e4 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -152,7 +152,7 @@ void __init_refok free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc0..59d6f76 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -744,7 +744,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index f497ca7..6041e40 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -398,7 +398,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index e66e840..5a79fa0 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -154,6 +154,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 82d01a7..8e9eab2 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -133,7 +133,7 @@ void __init mem_init(void)
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
 #ifndef CONFIG_MPU
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 #endif
 }
 #endif
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
index a9fcd89..97914e5 100644
--- a/arch/c6x/mm/init.c
+++ b/arch/c6x/mm/init.c
@@ -77,7 +77,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index dee354f..a67f3a5 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -173,6 +173,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 } /* end free_initrd_mem() */
 #endif
diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c
index ff349d7..57e03c5 100644
--- a/arch/h8300/mm/init.c
+++ b/arch/h8300/mm/init.c
@@ -161,7 +161,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index d1fe4b4..da568c2 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -154,8 +154,7 @@ ia64_init_addr_space (void)
 void
 free_initmem (void)
 {
-	free_reserved_area((unsigned long)ia64_imva(__init_begin),
-			   (unsigned long)ia64_imva(__init_end),
+	free_reserved_area(ia64_imva(__init_begin), ia64_imva(__init_end),
 			   0, "unused kernel");
 }
 
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index ab4cbce..d80412d 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -191,6 +191,6 @@ void free_initmem(void)
  *======================================================================*/
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 1af2ca3..95de725 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -202,6 +202,6 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index d05b845..5e2238d 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -414,7 +414,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index b38ae3a..d7b8ada 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -235,7 +235,7 @@ void __init setup_memory(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 9b973e0..268f2a9 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -440,7 +440,8 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 5a8ace6..e19049d 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -152,6 +152,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index b3cbc67..ab11332 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -261,7 +261,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index ce939ac..59cec60 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -1101,6 +1101,7 @@ void flush_tlb_all(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, 0, "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end, 0,
+					    "initrd");
 }
 #endif
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 6782221..5e4830a 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -756,7 +756,7 @@ static __init void kvm_free_tmp(void)
 	end = (ulong)&kvm_tmp[ARRAY_SIZE(kvm_tmp)] & PAGE_MASK;
 
 	/* Free the tmp space we don't need */
-	free_reserved_area(start, end, 0, NULL);
+	free_reserved_area((void *)start, (void *)end, 0, NULL);
 }
 
 static int __init kvm_guest_init(void)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 0988a26..347c5b1 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -407,7 +407,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 89ebae4..0878c89 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -172,7 +172,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index d8f988a..3d79ecb 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -110,7 +110,8 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 20f9ead..b892a9b 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -505,7 +505,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index af472cf..d5f9c02 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -372,8 +372,8 @@ void free_initmem (void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index a717199..a54cdcd 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2124,8 +2124,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 9df292b..2aa7a24 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -244,7 +244,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 63df12d..220755c 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -486,7 +486,7 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index bba125b..4d658ef 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -214,7 +214,7 @@ extern int initrd_is_mapped;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (initrd_is_mapped)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e0c8528..771769f 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1307,7 +1307,7 @@ extern void free_initmem(void);
  * "poison" if it's non-zero.
  * Return pages freed into the buddy system.
  */
-extern unsigned long free_reserved_area(unsigned long start, unsigned long end,
+extern unsigned long free_reserved_area(void *start, void *end,
 					int poison, char *s);
 #ifdef	CONFIG_HIGHMEM
 /*
@@ -1351,8 +1351,7 @@ static inline unsigned long free_initmem_default(int poison)
 {
 	extern char __init_begin[], __init_end[];
 
-	return free_reserved_area(PAGE_ALIGN((unsigned long)&__init_begin) ,
-				  ((unsigned long)&__init_end) & PAGE_MASK,
+	return free_reserved_area(&__init_begin, &__init_end,
 				  poison, "unused kernel");
 }
 
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 34d42dc..9fe3061 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5188,21 +5188,21 @@ early_param("movablecore", cmdline_parse_movablecore);
 
 #endif /* CONFIG_HAVE_MEMBLOCK_NODE_MAP */
 
-unsigned long free_reserved_area(unsigned long start, unsigned long end,
-				 int poison, char *s)
+unsigned long free_reserved_area(void *start, void *end, int poison, char *s)
 {
-	unsigned long pages, pos;
+	void *pos;
+	unsigned long pages = 0;
 
-	pos = start = PAGE_ALIGN(start);
-	end &= PAGE_MASK;
-	for (pages = 0; pos < end; pos += PAGE_SIZE, pages++) {
+	start = (void *)PAGE_ALIGN((unsigned long)start);
+	end = (void *)((unsigned long)end & PAGE_MASK);
+	for (pos = start; pos < end; pos += PAGE_SIZE, pages++) {
 		if (poison)
-			memset((void *)pos, poison, PAGE_SIZE);
+			memset(pos, poison, PAGE_SIZE);
 		free_reserved_page(virt_to_page(pos));
 	}
 
 	if (pages && s)
-		pr_info("Freeing %s memory: %ldK (%lx - %lx)\n",
+		pr_info("Freeing %s memory: %ldK (%p - %p)\n",
 			s, pages << (PAGE_SHIFT - 10), start, end);
 
 	return pages;
-- 
1.8.1.2



From liuj97 at gmail.com  Fri May 17 11:45:05 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Fri, 17 May 2013 23:45:05 +0800
Subject: [PATCH v7, part3 03/16] mm/ARM64: kill poison_init_mem()
In-Reply-To: <1368805518-2634-1-git-send-email-jiang.liu@huawei.com>
References: <1368805518-2634-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1368805518-2634-4-git-send-email-jiang.liu@huawei.com>

Use free_reserved_area() to poison initmem memory pages and kill
poison_init_mem() on ARM64.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm64/mm/init.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 997c634..a398eb9 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -197,14 +197,6 @@ void __init bootmem_init(void)
 	max_pfn = max_low_pfn = max;
 }
 
-/*
- * Poison init memory with an undefined instruction (0x0).
- */
-static inline void poison_init_mem(void *s, size_t count)
-{
-	memset(s, 0, count);
-}
-
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
 static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -386,8 +378,7 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-	poison_init_mem(__init_begin, __init_end - __init_begin);
-	free_initmem_default(-1);
+	free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -396,10 +387,8 @@ static int keep_initrd;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	if (!keep_initrd) {
-		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area((void *)start, (void *)end, -1, "initrd");
-	}
+	if (!keep_initrd)
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 17 11:46:38 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 17 May 2013 11:46:38 -0400 (EDT)
Subject: [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default
 initialization
In-Reply-To: <1368804061-4421-3-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-3-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <alpine.LFD.2.03.1305171146100.31158@syhkavp.arg>

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> The __cpu_logical_map array is statically initialized to 0, which is a valid
> MPIDR value. To prevent issues with the current implementation, this patch
> defines an MPIDR_INVALID value, and statically initializes the
> __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
> tmp_map array used to stash DT reg properties while parsing DT are initialized
> with the MPIDR_INVALID value as well for consistency.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> CC: Will Deacon <will.deacon at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/include/asm/cputype.h  | 2 ++
>  arch/arm/include/asm/smp_plat.h | 2 +-
>  arch/arm/kernel/devtree.c       | 2 +-
>  arch/arm/kernel/setup.c         | 2 +-
>  4 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 7652712..dba62cb 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -32,6 +32,8 @@
>  
>  #define MPIDR_HWID_BITMASK 0xFFFFFF
>  
> +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
> +
>  #define MPIDR_LEVEL_BITS 8
>  #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
>  
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index aaa61b6..e789832 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
>  /*
>   * Logical CPU mapping.
>   */
> -extern int __cpu_logical_map[];
> +extern u32 __cpu_logical_map[];
>  #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
>  /*
>   * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 904cad5..0905502 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
>  	u32 i, j, cpuidx = 1;
>  	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>  
> -	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
> +	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>  	bool bootcpu_valid = false;
>  	cpus = of_find_node_by_path("/cpus");
>  
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 6ae71b7..eeac924 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -457,7 +457,7 @@ void notrace cpu_init(void)
>  	    : "r14");
>  }
>  
> -int __cpu_logical_map[NR_CPUS];
> +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>  
>  void __init smp_setup_processor_id(void)
>  {
> -- 
> 1.8.2.2
> 
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 


From nicolas.pitre at linaro.org  Fri May 17 11:49:19 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 17 May 2013 11:49:19 -0400 (EDT)
Subject: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to
 skip non-cpu nodes
In-Reply-To: <1368804061-4421-2-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-2-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <alpine.LFD.2.03.1305171148460.31158@syhkavp.arg>

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>



> ---
>  arch/arm/kernel/devtree.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
>  	for_each_child_of_node(cpus, cpu) {
>  		u32 hwid;
>  
> +		if (of_node_cmp(cpu->type, "cpu"))
> +			continue;
> +
>  		pr_debug(" * %s...\n", cpu->full_name);
>  		/*
>  		 * A device tree containing CPU nodes with missing "reg"
> -- 
> 1.8.2.2
> 
> 


From jp.francois at cynove.com  Fri May 17 11:51:26 2013
From: jp.francois at cynove.com (Jean-Philippe Francois)
Date: Fri, 17 May 2013 17:51:26 +0200
Subject: [PATCH] ARM : omap3 : fix wrong container_of in clock36xx.c
In-Reply-To: <CAGGh5h3BNV7fE3jC0KSmA+2K6zKwVyHdeo8AW0gvmhgQsy8ZEg@mail.gmail.com>
References: <CAGGh5h3BNV7fE3jC0KSmA+2K6zKwVyHdeo8AW0gvmhgQsy8ZEg@mail.gmail.com>
Message-ID: <1368805886-26085-1-git-send-email-jp.francois@cynove.com>

omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
have parent defined as clk_divider.
Fix the function to use clk_divider. 
Tested with  3.9 on dm3730.

Signed-off-by: Jean-Philippe Fran??ois <jp.francois at cynove.com>

Index: b/arch/arm/mach-omap2/clock36xx.c
===================================================================
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include "clock.h"
 #include "clock36xx.h"
-
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 /**
  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-	struct clk_hw_omap *parent;
+	struct clk_divider *parent;
 	struct clk_hw *parent_hw;
-	u32 dummy_v, orig_v, clksel_shift;
+	u32 dummy_v, orig_v;
 	int ret;
 
 	/* Clear PWRDN bit of HSDIVIDER */
 	ret = omap2_dflt_clk_enable(clk);
 
 	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-	parent = to_clk_hw_omap(parent_hw);
+	parent = to_clk_divider(parent_hw);
 
 	/* Restore the dividers */
 	if (!ret) {
-		clksel_shift = __ffs(parent->clksel_mask);
-		orig_v = __raw_readl(parent->clksel_reg);
+		orig_v = __raw_readl(parent->reg);
 		dummy_v = orig_v;
 
 		/* Write any other value different from the Read value */
-		dummy_v ^= (1 << clksel_shift);
-		__raw_writel(dummy_v, parent->clksel_reg);
+		dummy_v ^= (1 << parent->shift);
+		__raw_writel(dummy_v, parent->reg);
 
 		/* Write the original divider */
-		__raw_writel(orig_v, parent->clksel_reg);
+		__raw_writel(orig_v, parent->reg);
 	}
 
 	return ret;


From will.deacon at arm.com  Fri May 17 11:59:36 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 16:59:36 +0100
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <CACVXFVPJyKrOBk+JjsfCi+aQ8snQ7PsEJVuOnuTkrWBYEnvDtA@mail.gmail.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
 <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
 <20130517093616.GC23112@mudshark.cambridge.arm.com>
 <CACVXFVP56EJb0BZ+w6hVAukQ-mN0e0Jn_GLw3XqXQqMwVGfNdA@mail.gmail.com>
 <20130517095423.GD23112@mudshark.cambridge.arm.com>
 <CACVXFVPJyKrOBk+JjsfCi+aQ8snQ7PsEJVuOnuTkrWBYEnvDtA@mail.gmail.com>
Message-ID: <20130517155936.GQ23112@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 11:07:37AM +0100, Ming Lei wrote:
> On Fri, May 17, 2013 at 5:54 PM, Will Deacon <will.deacon at arm.com> wrote:
> > On Fri, May 17, 2013 at 10:48:23AM +0100, Ming Lei wrote:
> >> On Fri, May 17, 2013 at 5:36 PM, Will Deacon <will.deacon at arm.com> wrote:
> >> >
> >> > It's probably easier if you choose a workload, otherwise it's difficult to
> >> > see what is `correct' and what is broken. For example, your broken output
> >> > seems to be in the smsc95xx driver, so assumedly there's a bunch of
> >> > networking going on whereas your other output is in cpuidle_enter_state.
> >>
> >> If all modules are removed, the result will become OK. And if I only insert one
> >> module, the top sample will fall inside the only module, but I am sure
> >> nothing is working on the symbols of the module.

Ok, I tried to reproduce this on my TC2 with 3.10-rc1 and perf top looks
fine. I also tried loading your spi-altera module and it made no difference.

I'm using a fairly old perf tool (reports its version as 3.5.5).

Will


From dmurphy at ti.com  Fri May 17 12:02:32 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 17 May 2013 11:02:32 -0500
Subject: [PATCH v6] ARM:dts:omap4-panda: Update the LED support for the panda
 DTS
Message-ID: <1368806552-8851-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
Changes in this version:
	- review comments incorporated.
Previous version of this patch was discussed in:
	https://patchwork.kernel.org/patch/2582771/

 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..5fd59b3 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <
+			&led_wkgpio_pins
+		>;
+
 		heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 0>;
@@ -137,6 +142,15 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c968a3b 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
 		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
 		>;
 };
+
+&omap4_pmx_core {
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
+&led_wkgpio_pins {
+	pinctrl-single,pins = <
+		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+	>;
+};
+
+&leds {
+	pinctrl-0 = <
+		&led_gpio_pins
+		&led_wkgpio_pins
+	>;
+
+	heartbeat {
+		gpios = <&gpio4 14 0>;
+	};
+	mmc {
+		gpios = <&gpio1 8 0>;
+	};
+};
-- 
1.7.5.4



From nicolas.pitre at linaro.org  Fri May 17 12:07:05 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 17 May 2013 12:07:05 -0400 (EDT)
Subject: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu
 nodes bindings updates
In-Reply-To: <1368804061-4421-4-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-4-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <alpine.LFD.2.03.1305171206350.31158@syhkavp.arg>

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
> 
> Main changes:
>     - adds 64-bit bindings
>     - define usage of #address-cells
>     - define 32/64 dts compatibility settings
>     - defines behaviour on pre and post v7 uniprocessor systems
>     - adds ARM 11MPcore specific reg property definition
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
>  1 file changed, 412 insertions(+), 47 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index f32494d..3fc0c11 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -1,77 +1,442 @@
> -* ARM CPUs binding description
> +=================
> +ARM CPUs bindings
> +=================
>  
>  The device tree allows to describe the layout of CPUs in a system through
>  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>  defining properties for every cpu.
>  
> -Bindings for CPU nodes follow the ePAPR standard, available from:
> -
> -http://devicetree.org
> -
> -For the ARM architecture every CPU node must contain the following properties:
> -
> -- device_type:	must be "cpu"
> -- reg:		property matching the CPU MPIDR[23:0] register bits
> -		reg[31:24] bits must be set to 0
> -- compatible:	should be one of:
> -		"arm,arm1020"
> -		"arm,arm1020e"
> -		"arm,arm1022"
> -		"arm,arm1026"
> -		"arm,arm720"
> -		"arm,arm740"
> -		"arm,arm7tdmi"
> -		"arm,arm920"
> -		"arm,arm922"
> -		"arm,arm925"
> -		"arm,arm926"
> -		"arm,arm940"
> -		"arm,arm946"
> -		"arm,arm9tdmi"
> -		"arm,cortex-a5"
> -		"arm,cortex-a7"
> -		"arm,cortex-a8"
> -		"arm,cortex-a9"
> -		"arm,cortex-a15"
> -		"arm,arm1136"
> -		"arm,arm1156"
> -		"arm,arm1176"
> -		"arm,arm11mpcore"
> -		"faraday,fa526"
> -		"intel,sa110"
> -		"intel,sa1100"
> -		"marvell,feroceon"
> -		"marvell,mohawk"
> -		"marvell,xsc3"
> -		"marvell,xscale"
> -
> -Example:
> +Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
> +
> +https://www.power.org/documentation/epapr-version-1-1/
> +
> +with updates for 32-bit and 64-bit ARM systems provided in this document.
> +
> +================================
> +Convention used in this document
> +================================
> +
> +This document follows the conventions described in the ePAPR v1.1, with
> +the addition:
> +
> +- square brackets define bitfields, eg reg[7:0] value of the bitfield in
> +  the reg property contained in bits 7 down to 0
> +
> +=====================================
> +cpus and cpu node bindings definition
> +=====================================
> +
> +The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
> +nodes to be present and contain the properties described below.
> +
> +- cpus node
> +
> +	Description: Container of cpu nodes
> +
> +	The node name must be "cpus".
> +
> +	A cpus node must define the following properties:
> +
> +	- #address-cells
> +		Usage: required
> +		Value type: <u32>
> +
> +		Definition depends on ARM architecture version and
> +		configuration:
> +
> +			# On uniprocessor ARM architectures previous to v7
> +			  value must be 0.
> +			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
> +			  value must be 1.
> +			# On ARM v8 64-bit systems value must be set to 1
> +			  or 2. Refer to the cpu node's reg property
> +			  description for allowed configurations.
> +
> +	- #size-cells
> +		Usage: required
> +		Value type: <u32>
> +		Definition: must be set to 0
> +
> +- cpu node
> +
> +	Description: Describes a CPU in an ARM based system
> +
> +	PROPERTIES
> +
> +	- device_type
> +		Usage: required
> +		Value type: <string>
> +		Definition: must be "cpu"
> +	- reg
> +		Usage and definition depend on ARM architecture version and
> +		configuration:
> +
> +			# On uniprocessor ARM architectures previous to v7
> +			  this property is optional since they do not define
> +			  any register that provides a CPU identifier.
> +			  Any value set in the reg property for these CPUs
> +			  should be ignored.
> +
> +			# On ARM 11 MPcore based systems this property is
> +			  required and matches the CPUID[11:0] register bits.
> +
> +			  Bits [11:0] in the reg cell must be set to
> +			  bits [11:0] in CPU ID register.
> +
> +			  All other bits in the reg cell must be set to 0.
> +
> +			# On 32-bit ARM v7 or later systems this property is
> +			  required and matches the CPU MPIDR[23:0] register
> +			  bits.
> +
> +			  Bits [23:0] in the reg cell must be set to
> +			  bits [23:0] in MPIDR.
> +
> +			  All other bits in the reg cell must be set to 0.
> +
> +			# On ARM v8 64-bit systems, where the reg property
> +			  size can be 1 or 2 cells (as defined by cpus node's
> +			  #address-cells property), this property is
> +			  required and matches:
> +
> +			  - On systems running the OS in AArch32:
> +
> +			    * If the cpus node's #address-cells value is 2:
> +
> +			      The first reg cell must be set to 0.
> +
> +			      The second reg cell bits [23:0] must be set to
> +			      bits [23:0] of MPIDR_EL1.
> +
> +			      All other bits in the reg cells must be set to 0.
> +
> +			    * If the cpus node's #address-cells value is 1:
> +
> +			      Bits [23:0] in the reg cell must be set to
> +			      bits [23:0] in MPIDR_EL1.
> +
> +			      All other bits in the reg cell must be 0.
> +
> +			  - On systems running the OS in AArch64:
> +
> +			    * If the cpus node's #address-cells value is 2:
> +
> +			      The first reg cell bits [7:0] must be set to
> +			      bits [39:32] of MPIDR_EL1.
> +
> +			      The second reg cell bits [23:0] must be set to
> +			      bits [23:0] of MPIDR_EL1.
> +
> +			      All other bits in the reg cells must be set to 0.
> +
> +			    * If the cpus node's #address-cells value is 1:
> +
> +			      MPIDR_EL1[63:32] is 0 on all processors in the
> +			      system.
> +
> +			      The reg cell bits [23:0] must be set to
> +			      bits [23:0] of MPIDR_EL1.
> +
> +			      All other bits in the reg cell must be set to 0.
> +
> +	- compatible:
> +		Usage: required
> +		Value type: <string>
> +		Definition: should be one of:
> +			    "arm,arm710t"
> +			    "arm,arm720t"
> +			    "arm,arm740t"
> +			    "arm,arm7ej-s"
> +			    "arm,arm7tdmi"
> +			    "arm,arm7tdmi-s"
> +			    "arm,arm9es"
> +			    "arm,arm9ej-s"
> +			    "arm,arm920t"
> +			    "arm,arm922t"
> +			    "arm,arm925"
> +			    "arm,arm926e-s"
> +			    "arm,arm926ej-s"
> +			    "arm,arm940t"
> +			    "arm,arm946e-s"
> +			    "arm,arm966e-s"
> +			    "arm,arm968e-s"
> +			    "arm,arm9tdmi"
> +			    "arm,arm1020e"
> +			    "arm,arm1020t"
> +			    "arm,arm1022e"
> +			    "arm,arm1026ej-s"
> +			    "arm,arm1136j-s"
> +			    "arm,arm1136jf-s"
> +			    "arm,arm1156t2-s"
> +			    "arm,arm1156t2f-s"
> +			    "arm,arm1176jzf"
> +			    "arm,arm1176jz-s"
> +			    "arm,arm1176jzf-s"
> +			    "arm,arm11mpcore"
> +			    "arm,cortex-a5"
> +			    "arm,cortex-a7"
> +			    "arm,cortex-a8"
> +			    "arm,cortex-a9"
> +			    "arm,cortex-a15"
> +			    "arm,cortex-a53"
> +			    "arm,cortex-a57"
> +			    "arm,cortex-m0"
> +			    "arm,cortex-m0+"
> +			    "arm,cortex-m1"
> +			    "arm,cortex-m3"
> +			    "arm,cortex-m4"
> +			    "arm,cortex-r4"
> +			    "arm,cortex-r5"
> +			    "arm,cortex-r7"
> +			    "faraday,fa526"
> +			    "intel,sa110"
> +			    "intel,sa1100"
> +			    "marvell,feroceon"
> +			    "marvell,mohawk"
> +			    "marvell,pj4"
> +			    "marvell,sheeva-v7"
> +			    "marvell,xsc3"
> +			    "marvell,xscale"
> +			    "qcom,krait"
> +			    "qcom,scorpion"
> +	- enable-method
> +		Value type: <stringlist>
> +		Usage and definition depend on ARM architecture version and
> +		configuration:
> +			# On ARM v8 64-bit systems running the OS in AArch64,
> +			  this property is required and must be one of:
> +			     "spin-table"
> +			     "psci"
> +			# On ARM 32-bit systems or ARM v8 systems running
> +			  the OS in AArch32 this property is prohibited.
> +
> +	- cpu-release-addr
> +		Usage: required for systems that have an "enable-method"
> +		       property value of "spin-table".
> +		Value type: <prop-encoded-array>
> +		Definition:
> +			# On ARM v8 64-bit systems must be a two cell
> +			  property identifying a 64-bit zero-initialised
> +			  memory location.
> +
> +Example 1 (dual-cluster big.LITTLE system 32-bit):
>  
>  	cpus {
>  		#size-cells = <0>;
>  		#address-cells = <1>;
>  
> -		CPU0: cpu at 0 {
> +		cpu at 0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0x0>;
>  		};
>  
> -		CPU1: cpu at 1 {
> +		cpu at 1 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0x1>;
>  		};
>  
> -		CPU2: cpu at 100 {
> +		cpu at 100 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x100>;
>  		};
>  
> -		CPU3: cpu at 101 {
> +		cpu at 101 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x101>;
>  		};
>  	};
> +
> +Example 2 (Cortex-A8 uniprocessor 32-bit system):
> +
> +	cpus {
> +		#size-cells = <0>;
> +		#address-cells = <1>;
> +
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a8";
> +			reg = <0x0>;
> +		};
> +	};
> +
> +Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
> +
> +	cpus {
> +		#size-cells = <0>;
> +		#address-cells = <0>;
> +
> +		cpu {
> +			device_type = "cpu";
> +			compatible = "arm,arm926ej-s";
> +		};
> +	};
> +
> +Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
> +
> +cpus {
> +	#size-cells = <0>;
> +	#address-cells = <2>;
> +
> +	cpu at 0 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x0>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 1 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x1>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 10000 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10000>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 10001 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10001>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 10100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 10101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100000000 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x0>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100000001 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x1>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100000100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100000101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100010000 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10000>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100010001 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10001>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100010100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu at 100010101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +};
> +
> +Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
> +
> +cpus {
> +	#size-cells = <0>;
> +	#address-cells = <2>;
> +
> +	cpu at 0 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x0>;
> +	};
> +
> +	cpu at 1 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x1>;
> +	};
> +
> +	cpu at 100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x100>;
> +	};
> +
> +	cpu at 101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x101>;
> +	};
> +};
> -- 
> 1.8.2.2
> 
> 


From lorenzo.pieralisi at arm.com  Fri May 17 12:11:43 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 17:11:43 +0100
Subject: [GIT PULL] ARM DT topology bindings
Message-ID: <20130517161143.GA4855@e102568-lin.cambridge.arm.com>

Hi Grant, Rob,

since it looks like we reached agreement on DT topology bindings for ARM
please pull the bindings documentation so that code relying on the
topology to be published and set in stone can be released and can stabilize.

The topology documentation relies on updates to the cpus/cpu nodes bindings
that I have just posted:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/169083.html

I do not know if you prefer to merge both documents at once or we can merge
this document first waiting for the other patchset to get merged, please
let me know.

Thank you very much indeed,
Lorenzo

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://linux-arm.org/linux-2.6-lp.git dt-topology

for you to fetch changes up to 9cb1b6c8d59f09e51c87ac812b83d0350151ed3b:

  Documentation: DT: arm: define CPU topology bindings (2013-05-17 16:40:12 +0100)

----------------------------------------------------------------
Lorenzo Pieralisi (1):
      Documentation: DT: arm: define CPU topology bindings

 Documentation/devicetree/bindings/arm/topology.txt | 492 +++++++++++++++++++++
 1 file changed, 492 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/topology.txt



From nm at ti.com  Fri May 17 12:15:25 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 17 May 2013 11:15:25 -0500
Subject: [PATCH v6] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <1368806552-8851-1-git-send-email-dmurphy@ti.com>
References: <1368806552-8851-1-git-send-email-dmurphy@ti.com>
Message-ID: <20130517161525.GA30014@kahuna>

On 11:02-20130517, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
> 
> A1-A3 = gpio_wk7
> ES = gpio_110
> 
> There is no change to LED D2
> 
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
> 
> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> ---
> Changes in this version:
> 	- review comments incorporated.
> Previous version of this patch was discussed in:
> 	https://patchwork.kernel.org/patch/2582771/
one minor nit,
$subject could do with space after the ':'
otherwise, it looks fine to me. Will suggest waiting for further
reviewers if they have an opinion prior to a new rev.

> 
>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>  arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>  2 files changed, 43 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 03bd60d..5fd59b3 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -16,8 +16,13 @@
>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>  	};
>  
> -	leds {
> +	leds: leds {
>  		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <
> +			&led_wkgpio_pins
> +		>;
> +
>  		heartbeat {
>  			label = "pandaboard::status1";
>  			gpios = <&gpio1 7 0>;
> @@ -137,6 +142,15 @@
>  	};
>  };
>  
> +&omap4_pmx_wkup {
> +	led_wkgpio_pins: pinmux_leds_wkpins {
> +		pinctrl-single,pins = <
> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
>  &i2c1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&i2c1_pins>;
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..c968a3b 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,31 @@
>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>  		>;
>  };
> +
> +&omap4_pmx_core {
> +	led_gpio_pins: gpio_led_pmx {
> +		pinctrl-single,pins = <
> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
> +&led_wkgpio_pins {
> +	pinctrl-single,pins = <
> +		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +	>;
> +};
> +
> +&leds {
> +	pinctrl-0 = <
> +		&led_gpio_pins
> +		&led_wkgpio_pins
> +	>;
> +
> +	heartbeat {
> +		gpios = <&gpio4 14 0>;
> +	};
> +	mmc {
> +		gpios = <&gpio1 8 0>;
> +	};
> +};

-- 
Regards,
Nishanth Menon


From dmurphy at ti.com  Fri May 17 12:17:17 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 17 May 2013 11:17:17 -0500
Subject: [PATCH v6] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <20130517161525.GA30014@kahuna>
References: <1368806552-8851-1-git-send-email-dmurphy@ti.com>
 <20130517161525.GA30014@kahuna>
Message-ID: <5196580D.1070209@ti.com>

On 05/17/2013 11:15 AM, Nishanth Menon wrote:
> On 11:02-20130517, Dan Murphy wrote:
>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>> are different.
>>
>> A1-A3 = gpio_wk7
>> ES = gpio_110
>>
>> There is no change to LED D2
>>
>> Abstract away the pinmux and the LED definitions for the two boards into
>> the respective DTS files.
>>
>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
>> ---
>> Changes in this version:
>> 	- review comments incorporated.
>> Previous version of this patch was discussed in:
>> 	https://patchwork.kernel.org/patch/2582771/
> one minor nit,
> $subject could do with space after the ':'
> otherwise, it looks fine to me. Will suggest waiting for further
> reviewers if they have an opinion prior to a new rev.
Thanks NM I will queue up this change locally and await further review prior to sending v7.

>>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>>  arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>>  2 files changed, 43 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> index 03bd60d..5fd59b3 100644
>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> @@ -16,8 +16,13 @@
>>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>>  	};
>>  
>> -	leds {
>> +	leds: leds {
>>  		compatible = "gpio-leds";
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <
>> +			&led_wkgpio_pins
>> +		>;
>> +
>>  		heartbeat {
>>  			label = "pandaboard::status1";
>>  			gpios = <&gpio1 7 0>;
>> @@ -137,6 +142,15 @@
>>  	};
>>  };
>>  
>> +&omap4_pmx_wkup {
>> +	led_wkgpio_pins: pinmux_leds_wkpins {
>> +		pinctrl-single,pins = <
>> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
>> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>> +		>;
>> +	};
>> +};
>> +
>>  &i2c1 {
>>  	pinctrl-names = "default";
>>  	pinctrl-0 = <&i2c1_pins>;
>> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
>> index f1d8c21..c968a3b 100644
>> --- a/arch/arm/boot/dts/omap4-panda-es.dts
>> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
>> @@ -34,3 +34,31 @@
>>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>>  		>;
>>  };
>> +
>> +&omap4_pmx_core {
>> +	led_gpio_pins: gpio_led_pmx {
>> +		pinctrl-single,pins = <
>> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
>> +		>;
>> +	};
>> +};
>> +
>> +&led_wkgpio_pins {
>> +	pinctrl-single,pins = <
>> +		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>> +	>;
>> +};
>> +
>> +&leds {
>> +	pinctrl-0 = <
>> +		&led_gpio_pins
>> +		&led_wkgpio_pins
>> +	>;
>> +
>> +	heartbeat {
>> +		gpios = <&gpio4 14 0>;
>> +	};
>> +	mmc {
>> +		gpios = <&gpio1 8 0>;
>> +	};
>> +};


-- 
------------------
Dan Murphy



From nicolas.pitre at linaro.org  Fri May 17 12:22:33 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 17 May 2013 12:22:33 -0400 (EDT)
Subject: [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings
 update
In-Reply-To: <1368804061-4421-19-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-19-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <alpine.LFD.2.03.1305171222020.31158@syhkavp.arg>

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> DT cpu map parsing code must be made compliant with the latest cpus/cpu
> nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
> function with checks and additional parsing rules.
> 
> Uniprocessor systems predating v7 do not parse the cpus node at all
> since the reg property is meaningless on those systems.
> 
> Device trees for 64-bit systems can be taken as device tree input also
> for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
> are zeroed as required in the respective fields and detects automatically
> the cpus node #address-cells value so that device tree written for
> 64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
> be taken as input. The correct device tree entries are to be set up by the
> boot loader, kernel code just checks that device tree entries in the cpus
> node are as expected for a 32-bit CPU (reg[63:24] == 0).
> 
> cpu node entries with invalid reg property or containing duplicates are
> ignored and the device tree parsing is not stopped anymore when such
> entries are encountered, the device tree cpu node entry is just skipped.
> 
> A device tree with cpu nodes missing the boot CPU MPIDR is considered
> an error and the kernel flags this up as such to trigger firmware updates.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
>  1 file changed, 88 insertions(+), 58 deletions(-)
> 
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 0905502..80d6cf24 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -23,6 +23,7 @@
>  #include <asm/setup.h>
>  #include <asm/page.h>
>  #include <asm/smp_plat.h>
> +#include <asm/system_info.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach-types.h>
>  
> @@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
>   */
>  void __init arm_dt_init_cpu_maps(void)
>  {
> -	/*
> -	 * Temp logical map is initialized with UINT_MAX values that are
> -	 * considered invalid logical map entries since the logical map must
> -	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
> -	 * read as 0.
> -	 */
>  	struct device_node *cpu, *cpus;
> -	u32 i, j, cpuidx = 1;
> +	u32 i, ac, cpuidx = 1;
> +	int len;
>  	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>  
> -	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>  	bool bootcpu_valid = false;
>  	cpus = of_find_node_by_path("/cpus");
>  
> -	if (!cpus)
> +	if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
>  		return;
>  
> +	if (of_property_read_u32(cpus, "#address-cells", &ac)) {
> +		pr_warn("%s invalid #address-cells\n", cpus->full_name);
> +		ac = of_n_addr_cells(cpus);
> +	}
> +	/*
> +	 * The boot CPU knows its MPIDR and initialize it
> +	 * to allow DT boot CPU detection.
> +	 */
> +	cpu_logical_map(0) = mpidr;
> +
>  	for_each_child_of_node(cpus, cpu) {
> -		u32 hwid;
> +		u64 hwid64;
> +		u32 hwid32;
> +		const __be32 *prop;
>  
>  		if (of_node_cmp(cpu->type, "cpu"))
>  			continue;
>  
>  		pr_debug(" * %s...\n", cpu->full_name);
>  		/*
> -		 * A device tree containing CPU nodes with missing "reg"
> -		 * properties is considered invalid to build the
> -		 * cpu_logical_map.
> +		 * A CPU node with missing or wrong "reg" property is
> +		 * considered invalid to build a cpu_logical_map entry.
>  		 */
> -		if (of_property_read_u32(cpu, "reg", &hwid)) {
> -			pr_debug(" * %s missing reg property\n",
> -				     cpu->full_name);
> -			return;
> +		prop = of_get_property(cpu, "reg", &len);
> +		if (!prop || len < (ac * sizeof(*prop))) {
> +			pr_warn(" * %s node missing/wrong reg property, skipped\n",
> +				cpu->full_name);
> +				goto next;
>  		}
>  
>  		/*
> -		 * 8 MSBs must be set to 0 in the DT since the reg property
> -		 * defines the MPIDR[23:0].
> +		 * Always read reg as u64 value.
> +		 * For dts with #address-cells == 1 hwid64[63:32]
> +		 * will be set to 0 by of_read_number.
> +		 * Toss away the top 32 bits and store value in hwid32.
>  		 */
> -		if (hwid & ~MPIDR_HWID_BITMASK)
> -			return;
> -
> +		hwid32 = hwid64 = of_read_number(prop, ac);
> +		/*
> +		 * hwid64[63:24] must be always be 0 since the reg
> +		 * property defines the MPIDR[23:0] bits regardless
> +		 * of the cpus node #address-cells value.
> +		 */
> +		if (hwid64 & ~MPIDR_HWID_BITMASK) {
> +			pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
> +				cpu->full_name, hwid64);
> +			goto next;
> +		}
>  		/*
>  		 * Duplicate MPIDRs are a recipe for disaster.
>  		 * Scan all initialized entries and check for
> -		 * duplicates. If any is found just bail out.
> -		 * temp values were initialized to UINT_MAX
> -		 * to avoid matching valid MPIDR[23:0] values.
> +		 * duplicates. If any is found just ignore the CPU.
> +		 * Boot CPU at logical index 0 is not checked to
> +		 * allow self contained boot CPU detection logic.
>  		 */
> -		for (j = 0; j < cpuidx; j++)
> -			if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
> -						     "properties in the DT\n"))
> -				return;
> +		for (i = 1; i < cpuidx; i++)
> +			if (cpu_logical_map(i) == hwid32) {
> +				pr_warn(" * %s node duplicate cpu reg property, skipped\n",
> +					cpu->full_name);
> +				goto next;
> +			}
>  
>  		/*
> -		 * Build a stashed array of MPIDR values. Numbering scheme
> -		 * requires that if detected the boot CPU must be assigned
> -		 * logical id 0. Other CPUs get sequential indexes starting
> -		 * from 1. If a CPU node with a reg property matching the
> -		 * boot CPU MPIDR is detected, this is recorded so that the
> -		 * logical map built from DT is validated and can be used
> -		 * to override the map created in smp_setup_processor_id().
> +		 * If a CPU node with a reg property matching the
> +		 * cpu_logical_map(0) is detected, this is recorded so
> +		 * that the bootcpu_valid condition can be checked when
> +		 * DT scanning is completed. Duplicate boot cpu entries
> +		 * are flagged up if detected.
>  		 */
> -		if (hwid == mpidr) {
> -			i = 0;
> -			bootcpu_valid = true;
> -		} else {
> -			i = cpuidx++;
> +		if (hwid32 == cpu_logical_map(0)) {
> +			if (bootcpu_valid) {
> +				pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
> +					cpu->full_name);
> +			} else {
> +				bootcpu_valid = true;
> +			}
> +			goto next;
>  		}
> +		/*
> +		 * Build cpu_logical_map array. Numbering scheme
> +		 * requires that boot CPU is assigned logical id 0.
> +		 * Other CPUs get sequential indexes starting from 1.
> +		 */
> +		i = cpuidx++;
>  
> -		if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
> -					       "max cores %u, capping them\n",
> -					       cpuidx, nr_cpu_ids)) {
> +		if (cpuidx > nr_cpu_ids) {
> +			pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
> +				cpuidx, nr_cpu_ids);
>  			cpuidx = nr_cpu_ids;
> -			break;
> +			goto next;
>  		}
>  
> -		tmp_map[i] = hwid;
> +		cpu_logical_map(i) = hwid32;
> +		set_cpu_possible(i, true);
> +		pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
> +next:	;
>  	}
> -
> -	if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
> -				 "fall back to default cpu_logical_map\n"))
> -		return;
> +	/*
> +	 * A DT missing the boot CPU MPIDR is a really bad omen
> +	 * Flag it up as such.
> +	 */
> +	if (!bootcpu_valid)
> +		pr_warn("DT missing boot cpu node\n");
>  
>  	/*
> -	 * Since the boot CPU node contains proper data, and all nodes have
> -	 * a reg property, the DT CPU list can be considered valid and the
> -	 * logical map created in smp_setup_processor_id() can be overridden
> +	 * Since the DT might contain fewer entries than NR_CPUS,
> +	 * cpu_logical_map entries initialized in smp_setup_processor_id()
> +	 * but not found in the DT must be overriden with MPIDR_INVALID
> +	 * values to make sure the cpu_logical_map does not contain stale
> +	 * MPIDR values.
>  	 */
> -	for (i = 0; i < cpuidx; i++) {
> -		set_cpu_possible(i, true);
> -		cpu_logical_map(i) = tmp_map[i];
> -		pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
> -	}
> +	for (i = cpuidx; i < nr_cpu_ids; i++)
> +		cpu_logical_map(i) = MPIDR_INVALID;
>  }
>  
>  /**
> -- 
> 1.8.2.2
> 
> 


From t.figa at samsung.com  Fri May 17 12:24:28 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:28 +0200
Subject: [PATCH 2/6] ARM: EXYNOS: Fix EINT wake-up mask configuration when
 pinctrl is used
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368807872-2601-3-git-send-email-t.figa@samsung.com>

On DT-enabled systems pinctrl-exynos driver is responsible for handling
of wake-up EINT interrupts. This patch adjusts wake-up mask
configuration code to take wake-up mask value from pinctrl-exynos driver
on DT-enabled systems.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 7dbbfec..296090e 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -18,8 +18,15 @@
 #ifndef __ASM_ARCH_PM_CORE_H
 #define __ASM_ARCH_PM_CORE_H __FILE__
 
+#include <linux/of.h>
 #include <mach/regs-pmu.h>
 
+#ifdef CONFIG_PINCTRL_EXYNOS
+extern u32 exynos_get_eint_wake_mask(void);
+#else
+static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
+#endif
+
 static inline void s3c_pm_debug_init_uart(void)
 {
 	/* nothing here yet */
@@ -27,7 +34,12 @@ static inline void s3c_pm_debug_init_uart(void)
 
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
-	__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+	u32 eintmask = s3c_irqwake_eintmask;
+
+	if (of_have_populated_dt())
+		eintmask = exynos_get_eint_wake_mask();
+
+	__raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
 	__raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 }
 
-- 
1.8.2.1



From t.figa at samsung.com  Fri May 17 12:24:26 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:26 +0200
Subject: [PATCH 0/6] Fix suspend/resume issues created by pinmux on exynos,
 part 2
Message-ID: <1368807872-2601-1-git-send-email-t.figa@samsung.com>

This series aims at fixing problems with suspend/resume on Exynos SoCs
introduced by migration of GPIO and EINT support to pin control driver
on DT-enabled platforms.

The patches fix following issues:
 - missing support for IRQ wake of pinctrl-exynos driver
 - legacy GPIO and EINT save/restore handling in platform PM code
   inappropriate on pinctrl-enabled platforms
 - several EINT-related registers must be saved as well
 
The series is based on a patch by Doug Anderson that adds suspend/restore
of pinctrl registers to pinctrl-samsung driver:
[PATCH v3] pinctrl: samsung: fix suspend/resume functionality
http://www.spinics.net/lists/kernel/msg1534119.html

On Exynos4210-based Trats board:
Tested-by: Tomasz Figa <t.figa at samsung.com>

Tomasz Figa (6):
  pinctrl: exynos: Add support for set_irq_wake of wake-up EINTs
  ARM: EXYNOS: Fix EINT wake-up mask configuration when pinctrl is used
  ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled platforms
  pinctrl: samsung: Add support for SoC-specific suspend/resume
    callbacks
  pinctrl: samsung: Allow per-bank SoC-specific private data
  pinctrl: exynos: Handle suspend/resume of GPIO EINT registers

 arch/arm/mach-exynos/include/mach/pm-core.h |  14 +++-
 arch/arm/plat-samsung/pm.c                  |  17 +++--
 drivers/pinctrl/pinctrl-exynos.c            | 106 ++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-exynos.h            |   1 +
 drivers/pinctrl/pinctrl-samsung.c           |   6 ++
 drivers/pinctrl/pinctrl-samsung.h           |   4 ++
 6 files changed, 142 insertions(+), 6 deletions(-)

-- 
1.8.2.1



From t.figa at samsung.com  Fri May 17 12:24:27 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:27 +0200
Subject: [PATCH 1/6] pinctrl: exynos: Add support for set_irq_wake of wake-up
 EINTs
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368807872-2601-2-git-send-email-t.figa@samsung.com>

This patch adds support of IRQ wake-up ability configuration for
wake-up EINTs on Exynos SoCs.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/pinctrl/pinctrl-exynos.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index ac74281..4f868e5 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -326,6 +326,28 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
 	return 0;
 }
 
+static u32 exynos_eint_wake_mask = 0xffffffff;
+
+u32 exynos_get_eint_wake_mask(void)
+{
+	return exynos_eint_wake_mask;
+}
+
+static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
+{
+	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+	unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
+
+	pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
+
+	if (!on)
+		exynos_eint_wake_mask |= bit;
+	else
+		exynos_eint_wake_mask &= ~bit;
+
+	return 0;
+}
+
 /*
  * irq_chip for wakeup interrupts
  */
@@ -335,6 +357,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
 	.irq_mask	= exynos_wkup_irq_mask,
 	.irq_ack	= exynos_wkup_irq_ack,
 	.irq_set_type	= exynos_wkup_irq_set_type,
+	.irq_set_wake	= exynos_wkup_irq_set_wake,
 };
 
 /* interrupt handler for wakeup interrupts 0..15 */
-- 
1.8.2.1



From t.figa at samsung.com  Fri May 17 12:24:30 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:30 +0200
Subject: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific
 suspend/resume callbacks
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368807872-2601-5-git-send-email-t.figa@samsung.com>

SoC-specific driver might require additional save and restore of
registers. This patch adds pair of SoC-specific callbacks per pinctrl
device to account for this.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/pinctrl/pinctrl-samsung.c | 6 ++++++
 drivers/pinctrl/pinctrl-samsung.h | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 15db258..63ac22e 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1010,6 +1010,9 @@ static void samsung_pinctrl_suspend_dev(
 				 reg, bank->pm_save[PINCFG_TYPE_FUNC]);
 		}
 	}
+
+	if (ctrl->suspend)
+		ctrl->suspend(drvdata);
 }
 
 /**
@@ -1026,6 +1029,9 @@ static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
 	void __iomem *virt_base = drvdata->virt_base;
 	int i;
 
+	if (ctrl->resume)
+		ctrl->resume(drvdata);
+
 	for (i = 0; i < ctrl->nr_banks; i++) {
 		struct samsung_pin_bank *bank = &ctrl->pin_banks[i];
 		void __iomem *reg = virt_base + bank->pctl_offset;
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 9f5cc81..b316d9f 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -187,6 +187,9 @@ struct samsung_pin_ctrl {
 
 	int		(*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
 	int		(*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
+	void		(*suspend)(struct samsung_pinctrl_drv_data *);
+	void		(*resume)(struct samsung_pinctrl_drv_data *);
+
 	char		*label;
 };
 
-- 
1.8.2.1



From t.figa at samsung.com  Fri May 17 12:24:29 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:29 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368807872-2601-4-git-send-email-t.figa@samsung.com>

This patch makes legacy code on suspend/resume path being executed
conditionally, on non-DT platforms only, to fix suspend/resume of
DT-enabled systems, for which the code is inappropriate.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/pm.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 53210ec..8ac2b2d 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -261,7 +261,8 @@ static int s3c_pm_enter(suspend_state_t state)
 	 * require a full power-cycle)
 	*/
 
-	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+	if (!of_have_populated_dt() &&
+	    !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
 	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
 		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
 		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
@@ -270,8 +271,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	/* save all necessary core registers not covered by the drivers */
 
-	samsung_pm_save_gpios();
-	samsung_pm_saved_gpios();
+	if (!of_have_populated_dt()) {
+		samsung_pm_save_gpios();
+		samsung_pm_saved_gpios();
+	}
+
 	s3c_pm_save_uarts();
 	s3c_pm_save_core();
 
@@ -310,8 +314,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	s3c_pm_restore_core();
 	s3c_pm_restore_uarts();
-	samsung_pm_restore_gpios();
-	s3c_pm_restored_gpios();
+
+	if (!of_have_populated_dt()) {
+		samsung_pm_restore_gpios();
+		s3c_pm_restored_gpios();
+	}
 
 	s3c_pm_debug_init();
 
-- 
1.8.2.1



From t.figa at samsung.com  Fri May 17 12:24:31 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:31 +0200
Subject: [PATCH 5/6] pinctrl: samsung: Allow per-bank SoC-specific private data
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368807872-2601-6-git-send-email-t.figa@samsung.com>

This patch extends pin bank descriptor structure with SoC-specific
private data field that allows SoC-specific drivers to store their own
private data.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/pinctrl/pinctrl-samsung.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index b316d9f..26d3519 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -139,6 +139,7 @@ struct samsung_pin_bank {
 	u32		eint_mask;
 	u32		eint_offset;
 	char		*name;
+	void		*soc_priv;
 	struct device_node *of_node;
 	struct samsung_pinctrl_drv_data *drvdata;
 	struct irq_domain *irq_domain;
-- 
1.8.2.1



From t.figa at samsung.com  Fri May 17 12:24:32 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 17 May 2013 18:24:32 +0200
Subject: [PATCH 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <1368807872-2601-7-git-send-email-t.figa@samsung.com>

Some GPIO EINT control registers needs to be preserved across
suspend/resume cycle. This patch extends the driver to take care of
this.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/pinctrl/pinctrl-exynos.c | 83 ++++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-exynos.h |  1 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 4f868e5..908d24a 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -196,6 +196,12 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+struct exynos_eint_gpio_save {
+	u32 eint_con;
+	u32 eint_fltcon0;
+	u32 eint_fltcon1;
+};
+
 /*
  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
  * @d: driver data of samsung pinctrl driver.
@@ -229,6 +235,11 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 			dev_err(dev, "gpio irq domain add failed\n");
 			return -ENXIO;
 		}
+
+		bank->soc_priv = devm_kzalloc(d->dev,
+			sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
+		if (!bank->soc_priv)
+			return -ENOMEM;
 	}
 
 	return 0;
@@ -528,6 +539,58 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 	return 0;
 }
 
+static void exynos_pinctrl_suspend_bank(
+				struct samsung_pinctrl_drv_data *drvdata,
+				struct samsung_pin_bank *bank)
+{
+	struct exynos_eint_gpio_save *save = bank->soc_priv;
+	void __iomem *regs = drvdata->virt_base;
+
+	save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+						+ bank->eint_offset);
+	save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset);
+	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset + 4);
+}
+
+static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+		if (bank->eint_type == EINT_TYPE_GPIO)
+			exynos_pinctrl_suspend_bank(drvdata, bank);
+}
+
+static void exynos_pinctrl_resume_bank(
+				struct samsung_pinctrl_drv_data *drvdata,
+				struct samsung_pin_bank *bank)
+{
+	struct exynos_eint_gpio_save *save = bank->soc_priv;
+	void __iomem *regs = drvdata->virt_base;
+
+	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+						+ bank->eint_offset);
+	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset);
+	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset + 4);
+}
+
+static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+		if (bank->eint_type == EINT_TYPE_GPIO)
+			exynos_pinctrl_resume_bank(drvdata, bank);
+}
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -591,6 +654,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4210-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -605,6 +670,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4210-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -686,6 +753,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -700,6 +769,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -710,6 +781,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl2",
 	}, {
 		/* pin-controller instance 3 data */
@@ -720,6 +793,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl3",
 	},
 };
@@ -798,6 +873,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -808,6 +885,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -818,6 +897,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl2",
 	}, {
 		/* pin-controller instance 3 data */
@@ -828,6 +909,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl3",
 	},
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 9b1f77a..3c91c35 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -19,6 +19,7 @@
 
 /* External GPIO and wakeup interrupt related definitions */
 #define EXYNOS_GPIO_ECON_OFFSET		0x700
+#define EXYNOS_GPIO_EFLTCON_OFFSET	0x800
 #define EXYNOS_GPIO_EMASK_OFFSET	0x900
 #define EXYNOS_GPIO_EPEND_OFFSET	0xA00
 #define EXYNOS_WKUP_ECON_OFFSET		0xE00
-- 
1.8.2.1



From robherring2 at gmail.com  Fri May 17 12:31:18 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 17 May 2013 11:31:18 -0500
Subject: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to
 skip non-cpu nodes
In-Reply-To: <1368804061-4421-2-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-2-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <CAL_JsqLdbbsBeEaUT5BcxjZnbjEiu=qsPsynxCXdgi1J=ejzTg@mail.gmail.com>

On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
<lorenzo.pieralisi at arm.com> wrote:
> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.

Great, so a new DT with cpu-map entries may not work with old kernels.
Please check the behavior. This should go to stable kernels.

Rob

>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> ---
>  arch/arm/kernel/devtree.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
>         for_each_child_of_node(cpus, cpu) {
>                 u32 hwid;
>
> +               if (of_node_cmp(cpu->type, "cpu"))
> +                       continue;
> +
>                 pr_debug(" * %s...\n", cpu->full_name);
>                 /*
>                  * A device tree containing CPU nodes with missing "reg"
> --
> 1.8.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From will.deacon at arm.com  Fri May 17 12:43:41 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 17:43:41 +0100
Subject: [PATCH] arm64: extable: sort the exception table at build time
Message-ID: <1368809021-25130-1-git-send-email-will.deacon@arm.com>

As is done for other architectures, sort the exception table at
build-time rather than during boot.

Since sortextable appears to be a standalone C program relying on the
host elf.h to provide EM_AARCH64, I've had to add a conditional check in
order to allow cross-compilation on machines that aren't running a
bleeding-edge libc-dev.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm64/Kconfig              |  1 +
 arch/arm64/kernel/vmlinux.lds.S | 15 +++++++--------
 scripts/sortextable.c           |  5 +++++
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 48347dc..fb8fd90 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -7,6 +7,7 @@ config ARM64
 	select ARM_AMBA
 	select ARM_ARCH_TIMER
 	select ARM_GIC
+	select BUILDTIME_EXTABLE_SORT
 	select CLONE_BACKWARDS
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 3fae2be..3d527726 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -57,6 +57,13 @@ SECTIONS
 
 	RO_DATA(PAGE_SIZE)
 
+	. = ALIGN(8);
+	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
+		__start___ex_table = .;
+		*(__ex_table)
+		__stop___ex_table = .;
+	}
+
 	_etext = .;			/* End of text and rodata section */
 
 	. = ALIGN(PAGE_SIZE);
@@ -99,14 +106,6 @@ SECTIONS
 		READ_MOSTLY_DATA(64)
 
 		/*
-		 * The exception fixup table (might need resorting at runtime)
-		 */
-		. = ALIGN(32);
-		__start___ex_table = .;
-		*(__ex_table)
-		__stop___ex_table = .;
-
-		/*
 		 * and the usual data section
 		 */
 		DATA_DATA
diff --git a/scripts/sortextable.c b/scripts/sortextable.c
index 1f10e89..f9ce116 100644
--- a/scripts/sortextable.c
+++ b/scripts/sortextable.c
@@ -31,6 +31,10 @@
 #include <tools/be_byteshift.h>
 #include <tools/le_byteshift.h>
 
+#ifndef EM_AARCH64
+#define EM_AARCH64	183
+#endif
+
 static int fd_map;	/* File descriptor for file being modified. */
 static int mmap_failed; /* Boolean flag. */
 static void *ehdr_curr; /* current ElfXX_Ehdr *  for resource cleanup */
@@ -249,6 +253,7 @@ do_file(char const *const fname)
 		custom_sort = sort_relative_table;
 		break;
 	case EM_ARM:
+	case EM_AARCH64:
 	case EM_MIPS:
 		break;
 	}  /* end switch */
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 12:54:38 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 17:54:38 +0100
Subject: [PATCH 2/2] ARM: tlb: don't perform inner-shareable invalidation for
 local BP ops
In-Reply-To: <1368809678-25818-1-git-send-email-will.deacon@arm.com>
References: <1368809678-25818-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368809678-25818-2-git-send-email-will.deacon@arm.com>

Now that the ASID allocator doesn't require inner-shareable maintenance,
we can convert the local_bp_flush_all function to perform only
non-shareable flushing, in a similar manner to the TLB invalidation
routines.

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/tlbflush.h | 16 +++++++++++++---
 arch/arm/kernel/smp_tlb.c       |  2 +-
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 55b5e18..8630db6 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -168,7 +168,7 @@
 
 #define v7wbi_tlb_flags_smp	(TLB_WB | TLB_BARRIER | \
 				 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
-				 TLB_V6_U_ASID | \
+				 TLB_V6_U_ASID | TLB_V6_BP | \
 				 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
 				 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
 #define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
@@ -488,14 +488,24 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr)
 	}
 }
 
-static inline void local_flush_bp_all(void)
+static inline void __flush_bp_all(void)
 {
 	const int zero = 0;
 	const unsigned int __tlb_flag = __cpu_tlb_flags;
 
 	if (tlb_flag(TLB_V7_UIS_BP))
 		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
-	else if (tlb_flag(TLB_V6_BP))
+
+	if (tlb_flag(TLB_BARRIER))
+		isb();
+}
+
+static inline void local_flush_bp_all(void)
+{
+	const int zero = 0;
+	const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+	if (tlb_flag(TLB_V6_BP))
 		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
 
 	if (tlb_flag(TLB_BARRIER))
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index cc299b5..5cb5500 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -204,5 +204,5 @@ void flush_bp_all(void)
 	if (tlb_ops_need_broadcast())
 		on_each_cpu(ipi_flush_bp_all, NULL, 1);
 	else
-		local_flush_bp_all();
+		__flush_bp_all();
 }
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 12:54:37 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 17:54:37 +0100
Subject: [PATCH 1/2] ARM: tlb: don't perform inner-shareable invalidation for
 local TLB ops
Message-ID: <1368809678-25818-1-git-send-email-will.deacon@arm.com>

Inner-shareable TLB invalidation is typically more expensive than local
(non-shareable) invalidation, so performing the broadcasting for
local_flush_tlb_* operations is a waste of cycles and needlessly
clobbers entries in the TLBs of other CPUs.

This patch introduces __flush_tlb_* versions for many of the TLB
invalidation functions, which only respect inner-shareable variants of
the invalidation instructions. This allows us to modify the v7 SMP TLB
flags to include *both* inner-shareable and non-shareable operations and
then check the relevant flags depending on whether the operation is
local or not.

This gains us around 0.5% in hackbench scores for a dual-core A15, but I
would expect this to improve as more cores (and clusters) are added to
the equation.

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Albin Tonnerre <Albin.Tonnerre at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/tlbflush.h | 67 ++++++++++++++++++++++++++++++++++++++---
 arch/arm/kernel/smp_tlb.c       |  8 ++---
 arch/arm/mm/context.c           |  6 +---
 3 files changed, 68 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d1..55b5e18 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -167,6 +167,8 @@
 #endif
 
 #define v7wbi_tlb_flags_smp	(TLB_WB | TLB_BARRIER | \
+				 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
+				 TLB_V6_U_ASID | \
 				 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
 				 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
 #define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
@@ -330,6 +332,21 @@ static inline void local_flush_tlb_all(void)
 	tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
 	tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
 	tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
+
+	if (tlb_flag(TLB_BARRIER)) {
+		dsb();
+		isb();
+	}
+}
+
+static inline void __flush_tlb_all(void)
+{
+	const int zero = 0;
+	const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+	if (tlb_flag(TLB_WB))
+		dsb();
+
 	tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
 
 	if (tlb_flag(TLB_BARRIER)) {
@@ -348,21 +365,32 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
 		dsb();
 
 	if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
-		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
+		if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
 			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
 			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
 			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
 		}
-		put_cpu();
 	}
 
 	tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
 	tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
 	tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
+
+	if (tlb_flag(TLB_BARRIER))
+		dsb();
+}
+
+static inline void __flush_tlb_mm(struct mm_struct *mm)
+{
+	const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+	if (tlb_flag(TLB_WB))
+		dsb();
+
 #ifdef CONFIG_ARM_ERRATA_720789
-	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
+	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", 0);
 #else
-	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
+	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm));
 #endif
 
 	if (tlb_flag(TLB_BARRIER))
@@ -392,6 +420,21 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
 	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
 	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
+
+	if (tlb_flag(TLB_BARRIER))
+		dsb();
+}
+
+static inline void
+__flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+{
+	const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+	uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
+
+	if (tlb_flag(TLB_WB))
+		dsb();
+
 #ifdef CONFIG_ARM_ERRATA_720789
 	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
 #else
@@ -421,6 +464,22 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
 	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
 	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
 	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
+
+	if (tlb_flag(TLB_BARRIER)) {
+		dsb();
+		isb();
+	}
+}
+
+static inline void __flush_tlb_kernel_page(unsigned long kaddr)
+{
+	const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+	kaddr &= PAGE_MASK;
+
+	if (tlb_flag(TLB_WB))
+		dsb();
+
 	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
 
 	if (tlb_flag(TLB_BARRIER)) {
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 9a52a07..cc299b5 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -135,7 +135,7 @@ void flush_tlb_all(void)
 	if (tlb_ops_need_broadcast())
 		on_each_cpu(ipi_flush_tlb_all, NULL, 1);
 	else
-		local_flush_tlb_all();
+		__flush_tlb_all();
 	broadcast_tlb_a15_erratum();
 }
 
@@ -144,7 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
 	if (tlb_ops_need_broadcast())
 		on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
 	else
-		local_flush_tlb_mm(mm);
+		__flush_tlb_mm(mm);
 	broadcast_tlb_mm_a15_erratum(mm);
 }
 
@@ -157,7 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 		on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page,
 					&ta, 1);
 	} else
-		local_flush_tlb_page(vma, uaddr);
+		__flush_tlb_page(vma, uaddr);
 	broadcast_tlb_mm_a15_erratum(vma->vm_mm);
 }
 
@@ -168,7 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
 		ta.ta_start = kaddr;
 		on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
 	} else
-		local_flush_tlb_kernel_page(kaddr);
+		__flush_tlb_kernel_page(kaddr);
 	broadcast_tlb_a15_erratum();
 }
 
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2ac3737..62c1ec5 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -134,10 +134,7 @@ static void flush_context(unsigned int cpu)
 	}
 
 	/* Queue a TLB invalidate and flush the I-cache if necessary. */
-	if (!tlb_ops_need_broadcast())
-		cpumask_set_cpu(cpu, &tlb_flush_pending);
-	else
-		cpumask_setall(&tlb_flush_pending);
+	cpumask_setall(&tlb_flush_pending);
 
 	if (icache_is_vivt_asid_tagged())
 		__flush_icache_all();
@@ -215,7 +212,6 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
 	if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
 		local_flush_bp_all();
 		local_flush_tlb_all();
-		dummy_flush_tlb_a15_erratum();
 	}
 
 	atomic64_set(&per_cpu(active_asids, cpu), asid);
-- 
1.8.2.2



From jason at lakedaemon.net  Fri May 17 12:55:40 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 17 May 2013 12:55:40 -0400
Subject: [PATCH 1/2] ARM: mvebu: Fix ranges entry on XP GP board
In-Reply-To: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
Message-ID: <20130517165540.GD11137@titan.lakedaemon.net>

On Fri, May 17, 2013 at 08:09:57AM -0300, Ezequiel Garcia wrote:
> With the latest device tree reorganization which introduced the
> 'internal-reg' node, now the only region translated is the internal register's.
> This makes the description of the hardware incomplete, for it lacks the
> Device Bus childs address space.
> 
> In order to fix this, it's required to add a 'ranges' entry with a suitable
> address space to map Device Bus childs, on a per-board basis.
> This patch fixes the ranges property on the Armada XP GP board.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> ---
> This should be included in v3.10.
> 
>  arch/arm/boot/dts/armada-xp-gp.dts | 3 +++
>  1 file changed, 3 insertions(+)

Applied to mvebu/fixes

thx,

Jason.


From jagarwal at nvidia.com  Fri May 17 12:51:38 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Fri, 17 May 2013 22:21:38 +0530
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
Message-ID: <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>

> > On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> > > - Enable PCIe controller on Cardhu
> > > - Only port 2 is connected on this board
> > > - Add regulators required for Tegra30
> > > - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> > > - and should be applied on top of this.
> >
> > > diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
> > > b/arch/arm/boot/dts/tegra30-cardhu.dtsi
> >
> > > +	pcie-controller {
> > > +		status = "okay";
> > > +		pex-clk-supply = <&pex_hvdd_3v3_reg>;
> > > +		vdd-supply = <&ldo1_reg>;
> > > +		avdd-supply = <&ldo2_reg>;
> > > +
> > > +		pci at 3,0 {
> > > +			status = "okay";
> > > +		};
> > > +	};
> >
> > So, if I apply this series, I do see the PCIe bridge and Ethernet
> > device get enumerated, but I don't see the USB3 controller get
> > enumerated. I believe that is a PCIe device behind the same bridge on the
> same Tegra PCIe port.
> > Shouldn't this device show up?
> I have also reproduced this problem. I see somehow no non-
> prefetchable memory is assigned to any of pcie devices.
> Probably that is the reason for USB3 (pci 0000:04:00.0) not getting
> enumerated since it uses only non-prefetchable memory.

1. Bus4(on which usb3 device resides) always return 0xffffffff from it's config space. which means device is not present?
2. That's why it is not assigned any resources and hence no usb3 probe happens.
3. But same bus does return valid info like vendor/device id etc from it's config space in downstream kernel and hence usb3 probe does happen.

Thierry, Stephen,
4. Any idea why bus4 should return 0xffffffff values in upstream kernel? Anything missing?
5. Also, how config space of all pcie devices are mapped? I mean if I change the config space offset in dts file, then also I find correct vendor/device id etc for bus0/device0/fun0.
    So how this mapping happens that even after changing the config space offset in PCIe address space, it always finds correct vendor/device id.



From jason at lakedaemon.net  Fri May 17 12:56:56 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 17 May 2013 12:56:56 -0400
Subject: [PATCH 2/2] ARM: mvebu: Add support for NOR flash device on
 Armada XP-DB board
In-Reply-To: <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
 <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>
Message-ID: <20130517165656.GE11137@titan.lakedaemon.net>

On Fri, May 17, 2013 at 08:09:58AM -0300, Ezequiel Garcia wrote:
> The Armada XP Development Board (DB-78460-BP) has a NOR flash device
> connected to the Device Bus. This commit adds the device tree node
> to support this device.
> 
> This SoC supports a flexible and dynamic decoding window allocation
> scheme; but since this feature is still not implemented we need
> to specify the window base address in the device tree node itself.
> 
> This base address has been selected in a completely arbitrary fashion.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-xp-db.dts | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Fri May 17 13:01:49 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 17 May 2013 13:01:49 -0400
Subject: [PATCH] ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform
In-Reply-To: <1368793503-8883-2-git-send-email-gregory.clement@free-electrons.com>
References: <1368793503-8883-1-git-send-email-gregory.clement@free-electrons.com>
 <1368793503-8883-2-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130517170149.GF11137@titan.lakedaemon.net>

On Fri, May 17, 2013 at 02:25:03PM +0200, Gregory CLEMENT wrote:
> Initially ARCH_REQUIRE_GPIOLIB was part of Thomas Petazzoni series
> when he introduced the gpiolib support for mvebu:
> 93a59cf arm: mvebu: use GPIO support now that a driver is available
> 
> This commit was written to be applied for the ARCH_MVEBU which was
> located in arch/arm/KConfig and was merged in 3.7.
> 
> In the same time Rob Herring moved the ARCH_MVEBU block to
> arch/arm/mach-mvebu/Kconfig with this commit and also merged in 3.7:
> 387798b ARM: initial multiplatform support
> 
> Unfortunately the ARCH_REQUIRE_GPIOLIB have been lost during this
> migration. This was not noticed until the v3.10-rc1, because mvebu as
> part of ARCH_MULTIPLATFORM was always selected with ARCH_VEXPRESS, and
> this architect selected ARCH_REQUIRE_GPIOLIB.
> 
> Since the following commit from Arnd: "883a106 ARM: default machine
> descriptor for multiplatform", ARCH_VEXPRESS was then no more selected
> by default with ARCH_MVEBU and it made appeared the lack of
> ARCH_REQUIRE_GPIOLIB for mvebu. This commit added back the selection
> of ARCH_REQUIRE_GPIOLIB for ARCH_MVEBU.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/mach-mvebu/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

Applied to mvebu/fixes

thx,

Jason.


From linux at arm.linux.org.uk  Fri May 17 13:04:11 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 18:04:11 +0100
Subject: [PATCH 1/2] ARM: tlb: don't perform inner-shareable
 invalidation for local TLB ops
In-Reply-To: <1368809678-25818-1-git-send-email-will.deacon@arm.com>
References: <1368809678-25818-1-git-send-email-will.deacon@arm.com>
Message-ID: <20130517170411.GJ18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 05:54:37PM +0100, Will Deacon wrote:
>  	if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
> -		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
> +		if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
>  			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
>  			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
>  			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
>  		}
> -		put_cpu();

NAK.  You may wish to read daaeb6c93829806221b2ac533330c64f338ebb89
which changed this from smp_processor_id() _to_ using get_cpu()/put_cpu().


From lorenzo.pieralisi at arm.com  Fri May 17 13:04:23 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 17 May 2013 18:04:23 +0100
Subject: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to
 skip non-cpu nodes
In-Reply-To: <CAL_JsqLdbbsBeEaUT5BcxjZnbjEiu=qsPsynxCXdgi1J=ejzTg@mail.gmail.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-2-git-send-email-lorenzo.pieralisi@arm.com>
 <CAL_JsqLdbbsBeEaUT5BcxjZnbjEiu=qsPsynxCXdgi1J=ejzTg@mail.gmail.com>
Message-ID: <20130517170422.GF27589@e102568-lin.cambridge.arm.com>

On Fri, May 17, 2013 at 05:31:18PM +0100, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi at arm.com> wrote:
> > The introduction of the cpu-map topology node in the cpus node implies
> > that cpus node might have children that are not cpu nodes. The DT
> > parsing code needs updating otherwise it would check for cpu nodes
> > properties in nodes that are not required to contain them, resulting
> > in warnings that have no bearing on bindings defined in the dts source file.
> 
> Great, so a new DT with cpu-map entries may not work with old kernels.
> Please check the behavior. This should go to stable kernels.

You are right, and I do not see any other solution if we want the
cpu-map node to live in the cpus node; at the time we added the cpus/cpu
bindings we thought that the cpus node's children would be restricted to cpu
nodes, and well, we are changing that, this is one of the consequences.

Yes, this patch should go to stable kernels, I will do that.

Lorenzo

> Rob
> 
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> > ---
> >  arch/arm/kernel/devtree.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> > index 5af04f6..904cad5 100644
> > --- a/arch/arm/kernel/devtree.c
> > +++ b/arch/arm/kernel/devtree.c
> > @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> >         for_each_child_of_node(cpus, cpu) {
> >                 u32 hwid;
> >
> > +               if (of_node_cmp(cpu->type, "cpu"))
> > +                       continue;
> > +
> >                 pr_debug(" * %s...\n", cpu->full_name);
> >                 /*
> >                  * A device tree containing CPU nodes with missing "reg"
> > --
> > 1.8.2.2
> >
> >
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss at lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
> 



From mgreer at animalcreek.com  Fri May 17 13:06:48 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Fri, 17 May 2013 10:06:48 -0700
Subject: [PATCH 1/9] I2C: mv64xxx: work around signals causing I2C
 transactions to be aborted
In-Reply-To: <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4pH-0004JQ-Jq@rmk-PC.arm.linux.org.uk>
Message-ID: <20130517170648.GD28484@animalcreek.com>

On Thu, May 16, 2013 at 09:30:59PM +0100, Russell King wrote:
> Do not use interruptible waits in an I2C driver; if a process uses
> signals (eg, Xorg uses SIGALRM and SIGPIPE) then these signals can
> cause the I2C driver to abort a transaction in progress by another
> driver, which can cause that driver to fail.  I2C drivers are not
> expected to abort transactions on signals.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

I don't have hardware to test but I have no issues with these patches so,
FWIW:

Acked-by: Mark A. Greer <mgreer at animalcreek.com>

for the entire series.


From tony at atomide.com  Fri May 17 13:10:17 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 10:10:17 -0700
Subject: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
 clkdiv32k_ick clock
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EC8BFA7@DBDE04.ent.ti.com>
References: <1364378666-23641-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1303271744510.17356@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EC8BFA7@DBDE04.ent.ti.com>
Message-ID: <20130517171016.GV5600@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [130517 03:36]:
> 
> > -----Original Message-----
> > From: Paul Walmsley [mailto:paul at pwsan.com]
> > Sent: Wednesday, March 27, 2013 11:15 PM
> > To: Tony Lindgren; Hiremath, Vaibhav
> > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> > Nayak, Rajendra
> > Subject: Re: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
> > clkdiv32k_ick clock
> > 
> > On Wed, 27 Mar 2013, Vaibhav Hiremath wrote:
> > 
> > > It is required to enable respective clock-domain before
> > > enabling any clock/module inside that clock-domain.
> > >
> > > During common-clock migration, .clkdm_name field got missed
> > > for "clkdiv32k_ick" clock, which leaves "clk_24mhz_clkdm"
> > > unused; so it will be disabled even if childs of this clock-domain
> > > is enabled, which keeps child modules in idle mode.
> > >
> > > This fixes the kernel crash observed on AM335xEVM-SK platform,
> > > where clkdiv32_ick clock is being used as a gpio debounce clock
> > > and since clkdiv32k_ick is in idle mode it leads to below crash -
> > >
> > > Crash Log:
> > > ==========
> > > [    2.598347] Unhandled fault: external abort on non-linefetch
> > (0x1028) at
> > > 0xfa1ac150
> > > [    2.606434] Internal error: : 1028 [#1] SMP ARM
> > > [    2.611207] Modules linked in:
> > > [    2.614449] CPU: 0    Not tainted  (3.8.4-01382-g1f449cd-dirty #4)
> > > [    2.620973] PC is at _set_gpio_debounce+0x60/0x104
> > > [    2.626025] LR is at clk_enable+0x30/0x3c
> > >
> > > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > > Cc: Tony Lindgren <tony at atomide.com>
> > > Cc: Paul Walmsley <paul at pwsan.com>
> > > Cc: Rajendra Nayak <rnayak at ti.com>
> > 
> > Acked-by: Paul Walmsley <paul at pwsan.com>
> > 
> > Tony, if it isn't too late, could this one be added to your 3.9-rc
> > fixes
> > series?
> > 
> > 
> 
> Looks like we missed this so far.
> 
> Tony, can you merge this patch for v3.10-rc ?

Oops, sorry somehow this did not make it. I'll apply it to omap-for-v3.10/fixes
with cc: stable flag.

Regards,

Tony


From will.deacon at arm.com  Fri May 17 13:13:20 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:13:20 +0100
Subject: [PATCH 1/2] ARM: tlb: don't perform inner-shareable invalidation
 for local TLB ops
In-Reply-To: <20130517170411.GJ18614@n2100.arm.linux.org.uk>
References: <1368809678-25818-1-git-send-email-will.deacon@arm.com>
 <20130517170411.GJ18614@n2100.arm.linux.org.uk>
Message-ID: <20130517171320.GV23112@mudshark.cambridge.arm.com>

Hi Russell,

On Fri, May 17, 2013 at 06:04:11PM +0100, Russell King - ARM Linux wrote:
> On Fri, May 17, 2013 at 05:54:37PM +0100, Will Deacon wrote:
> >  	if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
> > -		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
> > +		if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
> >  			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
> >  			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
> >  			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
> >  		}
> > -		put_cpu();
> 
> NAK.  You may wish to read daaeb6c93829806221b2ac533330c64f338ebb89
> which changed this from smp_processor_id() _to_ using get_cpu()/put_cpu().

With these changes, it would be a bug to call a local_* operation from
preemptible context, so the issue described in the commit above will never
trigger from properly written code. Since the flush_* operations are moved
to non-local variants, that shouldn't affect any existing users.

Will


From will.deacon at arm.com  Fri May 17 13:07:50 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:50 +0100
Subject: [PATCH 11/14] ARM: mm: cleanup checks for membank overlap with
 vmalloc area
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-12-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

On Keystone platforms, physical memory is entirely outside the 32-bit
addressible range.  Therefore, the (bank->start > ULONG_MAX) check below marks
the entire system memory as highmem, and this causes unpleasentness all over.

This patch eliminates the extra bank start check (against ULONG_MAX) by
checking bank->start against the physical address corresponding to vmalloc_min
instead.

In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/mmu.c | 19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index fc6ff1a..ae249d1 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -994,15 +994,12 @@ void __init sanity_check_meminfo(void)
 		struct membank *bank = &meminfo.bank[j];
 		*bank = meminfo.bank[i];
 
-		if (bank->start > ULONG_MAX)
-			highmem = 1;
-
-#ifdef CONFIG_HIGHMEM
 		if (bank->start >= vmalloc_limit)
 			highmem = 1;
 
 		bank->highmem = highmem;
 
+#ifdef CONFIG_HIGHMEM
 		/*
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
@@ -1025,8 +1022,6 @@ void __init sanity_check_meminfo(void)
 			bank->size = vmalloc_limit - bank->start;
 		}
 #else
-		bank->highmem = highmem;
-
 		/*
 		 * Highmem banks not allowed with !CONFIG_HIGHMEM.
 		 */
@@ -1039,18 +1034,6 @@ void __init sanity_check_meminfo(void)
 		}
 
 		/*
-		 * Check whether this memory bank would entirely overlap
-		 * the vmalloc area.
-		 */
-		if (bank->start >= vmalloc_limit) {
-			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-			       "(vmalloc region overlap).\n",
-			       (unsigned long long)bank->start,
-			       (unsigned long long)bank->start + bank->size - 1);
-			continue;
-		}
-
-		/*
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:39 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:39 +0100
Subject: [PATCH 00/14] Random LPAE-related patches
Message-ID: <1368810473-26070-1-git-send-email-will.deacon@arm.com>

Hello,

This is a collection of LPAE-related patches (mostly fixes) that have
been kicking around for a while and I've been collecting in one place.
There were some extra patches for bootmem, but they produced lots of
warnings and need more thought, so they've not been included here.

All comments welcome,

Will

Cyril Chemparathy (9):
  ARM: LPAE: use signed arithmetic for mask definitions
  ARM: LPAE: use phys_addr_t in switch_mm()
  ARM: LPAE: use 64-bit accessors for TTBR registers
  ARM: LPAE: factor out T1SZ and TTBR1 computations
  ARM: LPAE: accomodate >32-bit addresses for page table base
  ARM: mm: use physical addresses in highmem sanity checks
  ARM: fix type of PHYS_PFN_OFFSET to unsigned long
  ARM: mm: cleanup checks for membank overlap with vmalloc area
  ARM: mm: clean up membank size limit checks

Vitaly Andrianov (3):
  ARM: LPAE: use phys_addr_t in alloc_init_pud()
  ARM: LPAE: use phys_addr_t in free_memmap()
  ARM: LPAE: use phys_addr_t for initrd location

Will Deacon (2):
  ARM: lpae: fix definition of PTE_HWTABLE_PTRS
  ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions

 arch/arm/include/asm/memory.h               | 18 +++++++++-
 arch/arm/include/asm/page.h                 |  2 +-
 arch/arm/include/asm/pgtable-3level-hwdef.h | 20 +++++++++++
 arch/arm/include/asm/pgtable-3level.h       |  8 ++---
 arch/arm/include/asm/proc-fns.h             | 26 ++++++++++----
 arch/arm/include/uapi/asm/hwcap.h           |  2 +-
 arch/arm/kernel/head.S                      | 10 +++---
 arch/arm/kernel/setup.c                     |  8 ++++-
 arch/arm/kernel/smp.c                       | 11 ++++--
 arch/arm/mm/context.c                       |  9 ++---
 arch/arm/mm/init.c                          | 19 ++++++-----
 arch/arm/mm/mmu.c                           | 49 +++++++++-----------------
 arch/arm/mm/proc-v7-3level.S                | 53 +++++++++++++++--------------
 13 files changed, 139 insertions(+), 96 deletions(-)

-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:41 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:41 +0100
Subject: [PATCH 02/14] ARM: LPAE: use phys_addr_t in alloc_init_pud()
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-3-git-send-email-will.deacon@arm.com>

From: Vitaly Andrianov <vitalya at ti.com>

This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
unsigned long when passing in the phys argument.

This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a (ARM:
pgtable: use phys_addr_t for physical addresses), which applied similar changes
elsewhere in the ARM memory management code.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/mmu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e0d8565..b7ce65a8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -673,7 +673,8 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-	unsigned long end, unsigned long phys, const struct mem_type *type)
+				  unsigned long end, phys_addr_t phys,
+				  const struct mem_type *type)
 {
 	pud_t *pud = pud_offset(pgd, addr);
 	unsigned long next;
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:43 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:43 +0100
Subject: [PATCH 04/14] ARM: LPAE: use phys_addr_t for initrd location
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-5-git-send-email-will.deacon@arm.com>

From: Vitaly Andrianov <vitalya at ti.com>

This patch fixes the initrd setup code to use phys_addr_t instead of assuming
32-bit addressing.  Without this we cannot boot on systems where initrd is
located above the 4G physical address limit.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/init.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 68c914e..2ffee02 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,12 +36,13 @@
 
 #include "mm.h"
 
-static unsigned long phys_initrd_start __initdata = 0;
+static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
 static int __init early_initrd(char *p)
 {
-	unsigned long start, size;
+	phys_addr_t start;
+	unsigned long size;
 	char *endp;
 
 	start = memparse(p, &endp);
@@ -350,14 +351,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (phys_initrd_size &&
 	    !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
-		pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
-		       phys_initrd_start, phys_initrd_size);
+		pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
+		       (u64)phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size &&
 	    memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
-		pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-		       phys_initrd_start, phys_initrd_size);
+		pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
+		       (u64)phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size) {
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:49 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:49 +0100
Subject: [PATCH 10/14] ARM: fix type of PHYS_PFN_OFFSET to unsigned long
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-11-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

On LPAE machines, PHYS_OFFSET evaluates to a phys_addr_t and this type is
inherited by the PHYS_PFN_OFFSET definition as well.  Consequently, the kernel
build emits warnings of the form:

init/main.c: In function 'start_kernel':
init/main.c:588:7: warning: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'phys_addr_t' [-Wformat]

This patch fixes this warning by pinning down the PFN type to unsigned long.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/memory.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e506088..584786f 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -223,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
  * direct-mapped view.  We assume this is the first page
  * of RAM in the mem_map as well.
  */
-#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
+#define PHYS_PFN_OFFSET	((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 
 /*
  * These are *only* valid on the kernel direct mapped RAM memory.
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:42 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:42 +0100
Subject: [PATCH 03/14] ARM: LPAE: use phys_addr_t in free_memmap()
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-4-git-send-email-will.deacon@arm.com>

From: Vitaly Andrianov <vitalya at ti.com>

The free_memmap() was mistakenly using unsigned long type to represent
physical addresses.  This breaks on PAE systems where memory could be placed
above the 32-bit addressible limit.

This patch fixes this function to properly use phys_addr_t instead.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc0..68c914e 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -442,7 +442,7 @@ static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
 	struct page *start_pg, *end_pg;
-	unsigned long pg, pgend;
+	phys_addr_t pg, pgend;
 
 	/*
 	 * Convert start_pfn/end_pfn to a struct page pointer.
@@ -454,8 +454,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 	 * Convert to physical addresses, and
 	 * round start upwards and end downwards.
 	 */
-	pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
-	pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+	pg = PAGE_ALIGN(__pa(start_pg));
+	pgend = __pa(end_pg) & PAGE_MASK;
 
 	/*
 	 * If there are free pages between these,
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:44 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:44 +0100
Subject: [PATCH 05/14] ARM: LPAE: use phys_addr_t in switch_mm()
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-6-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
[will: fixed up conflict in 3-level switch_mm with big-endian changes]
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/proc-fns.h |  4 ++--
 arch/arm/mm/proc-v7-3level.S    | 16 ++++++++++++----
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb..75b5f14 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
 	/*
 	 * Set the page table
 	 */
-	void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+	void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
 	/*
 	 * Set a possibly extended PTE.  Non-extended PTEs should
 	 * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
 extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
-extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
 #ifdef CONFIG_ARM_LPAE
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
 #else
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 363027e..995857d 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -39,6 +39,14 @@
 #define TTB_FLAGS_SMP	(TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
 #define PMD_FLAGS_SMP	(PMD_SECT_WBWA|PMD_SECT_S)
 
+#ifndef __ARMEB__
+#  define rpgdl	r0
+#  define rpgdh	r1
+#else
+#  define rpgdl	r1
+#  define rpgdh	r0
+#endif
+
 /*
  * cpu_v7_switch_mm(pgd_phys, tsk)
  *
@@ -47,10 +55,10 @@
  */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-	mmid	r1, r1				@ get mm->context.id
-	asid	r3, r1
-	mov	r3, r3, lsl #(48 - 32)		@ ASID
-	mcrr	p15, 0, r0, r3, c2		@ set TTB 0
+	mmid	r2, r2
+	asid	r2, r2
+	orr	rpgdh, rpgdh, r2, lsl #(48 - 32)	@ upper 32-bits of pgd
+	mcrr	p15, 0, rpgdl, rpgdh, c2		@ set TTB 0
 	isb
 #endif
 	mov	pc, lr
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:52 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:52 +0100
Subject: [PATCH 13/14] ARM: lpae: fix definition of PTE_HWTABLE_PTRS
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-14-git-send-email-will.deacon@arm.com>

For 2-level page tables, PTE_HWTABLE_PTRS describes the offset between
Linux PTEs and hardware PTEs. On LPAE, there is no distinction (since
we have 64-bit descriptors with plenty of space) so PTE_HWTABLE_PTRS
should be 0. Unfortunately, it is wrongly defined as PTRS_PER_PTE,
meaning that current pte table flushing is off by a page. Luckily,
all current LPAE implementations are SMP, so the hardware walker can
snoop L1.

This patch fixes the broken definition.

Acked-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/pgtable-3level.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 5b85b21..d03c589 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -33,7 +33,7 @@
 #define PTRS_PER_PMD		512
 #define PTRS_PER_PGD		4
 
-#define PTE_HWTABLE_PTRS	(PTRS_PER_PTE)
+#define PTE_HWTABLE_PTRS	(0)
 #define PTE_HWTABLE_OFF		(0)
 #define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u64))
 
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:40 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:40 +0100
Subject: [PATCH 01/14] ARM: LPAE: use signed arithmetic for mask definitions
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-2-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch applies to PAGE_MASK, PMD_MASK, and PGDIR_MASK, where forcing
unsigned long math truncates the mask at the 32-bits.  This clearly does bad
things on PAE systems.

This patch fixes this problem by defining these masks as signed quantities.
We then rely on sign extension to do the right thing.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/page.h           | 2 +-
 arch/arm/include/asm/pgtable-3level.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 812a494..6363f3d 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT		12
 #define PAGE_SIZE		(_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK		(~(PAGE_SIZE-1))
+#define PAGE_MASK		(~((1 << PAGE_SHIFT) - 1))
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 86b8fe3..5b85b21 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -48,16 +48,16 @@
 #define PMD_SHIFT		21
 
 #define PMD_SIZE		(1UL << PMD_SHIFT)
-#define PMD_MASK		(~(PMD_SIZE-1))
+#define PMD_MASK		(~((1 << PMD_SHIFT) - 1))
 #define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK		(~(PGDIR_SIZE-1))
+#define PGDIR_MASK		(~((1 << PGDIR_SHIFT) - 1))
 
 /*
  * section address mask and size definitions.
  */
 #define SECTION_SHIFT		21
 #define SECTION_SIZE		(1UL << SECTION_SHIFT)
-#define SECTION_MASK		(~(SECTION_SIZE-1))
+#define SECTION_MASK		(~((1 << SECTION_SHIFT) - 1))
 
 #define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)
 
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:45 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:45 +0100
Subject: [PATCH 06/14] ARM: LPAE: use 64-bit accessors for TTBR registers
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-7-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
the LPAE version of cpu_set_reserved_ttbr0() to use these instead.

In the process, we also fix these functions to correctly handle cases
where the physical address lies beyond the 4G limit of 32-bit addressing.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/proc-fns.h | 22 +++++++++++++++++-----
 arch/arm/mm/context.c           |  9 ++-------
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 75b5f14..1c3cf94 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
 #ifdef CONFIG_ARM_LPAE
+
+#define cpu_get_ttbr(nr)					\
+	({							\
+		u64 ttbr;					\
+		__asm__("mrrc	p15, " #nr ", %Q0, %R0, c2"	\
+			: "=r" (ttbr));				\
+		ttbr;						\
+	})
+
+#define cpu_set_ttbr(nr, val)					\
+	do {							\
+		u64 ttbr = val;					\
+		__asm__("mcrr	p15, " #nr ", %Q0, %R0, c2"	\
+			: : "r" (ttbr));			\
+	} while (0)
+
 #define cpu_get_pgd()	\
 	({						\
-		unsigned long pg, pg2;			\
-		__asm__("mrrc	p15, 0, %0, %1, c2"	\
-			: "=r" (pg), "=r" (pg2)		\
-			:				\
-			: "cc");			\
+		u64 pg = cpu_get_ttbr(0);		\
 		pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);	\
 		(pgd_t *)phys_to_virt(pg);		\
 	})
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2ac3737..3675e31 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 
 /*
  * On ARMv6, we have the following structure in the Context ID:
@@ -55,17 +56,11 @@ static cpumask_t tlb_flush_pending;
 #ifdef CONFIG_ARM_LPAE
 static void cpu_set_reserved_ttbr0(void)
 {
-	unsigned long ttbl = __pa(swapper_pg_dir);
-	unsigned long ttbh = 0;
-
 	/*
 	 * Set TTBR0 to swapper_pg_dir which contains only global entries. The
 	 * ASID is set to 0.
 	 */
-	asm volatile(
-	"	mcrr	p15, 0, %0, %1, c2		@ set TTBR0\n"
-	:
-	: "r" (ttbl), "r" (ttbh));
+	cpu_set_ttbr(0, __pa(swapper_pg_dir));
 	isb();
 }
 #else
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:53 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:53 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-15-git-send-email-will.deacon@arm.com>

CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
userspace software can avoid having to use the exclusive variants of
these instructions if they wish.

This patch advertises the atomicity of these instructions via the
hwcaps, so userspace can detect this CPU feature.

Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h | 2 +-
 arch/arm/kernel/setup.c           | 8 +++++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 3688fd1..6d34d08 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -25,6 +25,6 @@
 #define HWCAP_IDIVT	(1 << 18)
 #define HWCAP_VFPD32	(1 << 19)	/* set if VFP has 32 regs (not 16) */
 #define HWCAP_IDIV	(HWCAP_IDIVA | HWCAP_IDIVT)
-
+#define HWCAP_LPAE	(1 << 20)
 
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7a..bdcd4dd 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -355,7 +355,7 @@ void __init early_print(const char *str, ...)
 
 static void __init cpuid_init_hwcaps(void)
 {
-	unsigned int divide_instrs;
+	unsigned int divide_instrs, vmsa;
 
 	if (cpu_architecture() < CPU_ARCH_ARMv7)
 		return;
@@ -368,6 +368,11 @@ static void __init cpuid_init_hwcaps(void)
 	case 1:
 		elf_hwcap |= HWCAP_IDIVT;
 	}
+
+	/* LPAE implies atomic ldrd/strd instructions */
+	vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
+	if (vmsa >= 5)
+		elf_hwcap |= HWCAP_LPAE;
 }
 
 static void __init feat_v6_fixup(void)
@@ -872,6 +877,7 @@ static const char *hwcap_str[] = {
 	"vfpv4",
 	"idiva",
 	"idivt",
+	"lpae",
 	NULL
 };
 
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:46 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:46 +0100
Subject: [PATCH 07/14] ARM: LPAE: factor out T1SZ and TTBR1 computations
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-8-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code.  This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/pgtable-3level-hwdef.h | 20 ++++++++++++++++++++
 arch/arm/mm/proc-v7-3level.S                | 29 ++++++++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef..c6c6e6d 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -79,4 +79,24 @@
 #define PHYS_MASK_SHIFT		(40)
 #define PHYS_MASK		((1ULL << PHYS_MASK_SHIFT) - 1)
 
+/*
+ * TTBR0/TTBR1 split (PAGE_OFFSET):
+ *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+ *   0x80000000: T0SZ = 0, T1SZ = 1
+ *   0xc0000000: T0SZ = 0, T1SZ = 2
+ *
+ * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
+ * booting secondary CPUs would end up using TTBR1 for the identity
+ * mapping set up in TTBR0.
+ */
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET	16			/* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET	(4096 * (1 + 3))	/* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET	0
+#endif
+
+#define TTBR1_SIZE	(((PAGE_OFFSET >> 30) - 1) << 16)
+
 #endif
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 995857d..58ab747 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -114,7 +114,7 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
-	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET? (branch below)
+	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?
 	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
 	orr	\tmp, \tmp, #TTB_EAE
 	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP)
@@ -122,27 +122,14 @@ ENDPROC(cpu_v7_set_pte_ext)
 	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP << 16)
 	ALT_UP(orr	\tmp, \tmp, #TTB_FLAGS_UP << 16)
 	/*
-	 * TTBR0/TTBR1 split (PAGE_OFFSET):
-	 *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
-	 *   0x80000000: T0SZ = 0, T1SZ = 1
-	 *   0xc0000000: T0SZ = 0, T1SZ = 2
-	 *
-	 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
-	 * booting secondary CPUs would end up using TTBR1 for the identity
-	 * mapping set up in TTBR0.
+	 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
+	 * otherwise booting secondary CPUs would end up using TTBR1 for the
+	 * identity mapping set up in TTBR0.
 	 */
-	bhi	9001f				@ PHYS_OFFSET > PAGE_OFFSET?
-	orr	\tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
-	/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
-	add	\ttbr1, \ttbr1, #1 << 4		@ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
-	/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
-	add	\ttbr1, \ttbr1, #4096 * (1 + 3)	@ only L2 used, skip pgd+3*pmd
-#endif
-	/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001:	mcr	p15, 0, \tmp, c2, c0, 2		@ TTB control register
-	mcrr	p15, 1, \ttbr1, \zero, c2	@ load TTBR1
+	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
+	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
+	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
 	.endm
 
 	__CPUINIT
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:48 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:48 +0100
Subject: [PATCH 09/14] ARM: mm: use physical addresses in highmem sanity checks
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-10-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch modifies the highmem sanity checking code to use physical addresses
instead.  This change eliminates the wrap-around problems associated with the
original virtual address based checks, and this simplifies the code a bit.

The one constraint imposed here is that low physical memory must be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x < y must => pa(x) < pa(y).

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/mmu.c | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b7ce65a8..fc6ff1a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -988,6 +988,7 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
 	int i, j, highmem = 0;
+	phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
@@ -997,8 +998,7 @@ void __init sanity_check_meminfo(void)
 			highmem = 1;
 
 #ifdef CONFIG_HIGHMEM
-		if (__va(bank->start) >= vmalloc_min ||
-		    __va(bank->start) < (void *)PAGE_OFFSET)
+		if (bank->start >= vmalloc_limit)
 			highmem = 1;
 
 		bank->highmem = highmem;
@@ -1007,8 +1007,8 @@ void __init sanity_check_meminfo(void)
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
 		 */
-		if (!highmem && __va(bank->start) < vmalloc_min &&
-		    bank->size > vmalloc_min - __va(bank->start)) {
+		if (!highmem && bank->start < vmalloc_limit &&
+		    bank->size > vmalloc_limit - bank->start) {
 			if (meminfo.nr_banks >= NR_BANKS) {
 				printk(KERN_CRIT "NR_BANKS too low, "
 						 "ignoring high memory\n");
@@ -1017,12 +1017,12 @@ void __init sanity_check_meminfo(void)
 					(meminfo.nr_banks - i) * sizeof(*bank));
 				meminfo.nr_banks++;
 				i++;
-				bank[1].size -= vmalloc_min - __va(bank->start);
-				bank[1].start = __pa(vmalloc_min - 1) + 1;
+				bank[1].size -= vmalloc_limit - bank->start;
+				bank[1].start = vmalloc_limit;
 				bank[1].highmem = highmem = 1;
 				j++;
 			}
-			bank->size = vmalloc_min - __va(bank->start);
+			bank->size = vmalloc_limit - bank->start;
 		}
 #else
 		bank->highmem = highmem;
@@ -1042,8 +1042,7 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would entirely overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start) >= vmalloc_min ||
-		    __va(bank->start) < (void *)PAGE_OFFSET) {
+		if (bank->start >= vmalloc_limit) {
 			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 			       "(vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
@@ -1055,9 +1054,8 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
-		    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
-			unsigned long newsize = vmalloc_min - __va(bank->start);
+		if (bank->start + bank->size > vmalloc_limit)
+			unsigned long newsize = vmalloc_limit - bank->start;
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:51 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:51 +0100
Subject: [PATCH 12/14] ARM: mm: clean up membank size limit checks
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-13-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch cleans up the highmem sanity check code by simplifying the range
checks with a pre-calculated size_limit.  This patch should otherwise have no
functional impact on behavior.

This patch also removes a redundant (bank->start < vmalloc_limit) check, since
this is already covered by the !highmem condition.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/mmu.c | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ae249d1..280f91d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -992,10 +992,15 @@ void __init sanity_check_meminfo(void)
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
+		phys_addr_t size_limit;
+
 		*bank = meminfo.bank[i];
+		size_limit = bank->size;
 
 		if (bank->start >= vmalloc_limit)
 			highmem = 1;
+		else
+			size_limit = vmalloc_limit - bank->start;
 
 		bank->highmem = highmem;
 
@@ -1004,8 +1009,7 @@ void __init sanity_check_meminfo(void)
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
 		 */
-		if (!highmem && bank->start < vmalloc_limit &&
-		    bank->size > vmalloc_limit - bank->start) {
+		if (!highmem && bank->size > size_limit) {
 			if (meminfo.nr_banks >= NR_BANKS) {
 				printk(KERN_CRIT "NR_BANKS too low, "
 						 "ignoring high memory\n");
@@ -1014,12 +1018,12 @@ void __init sanity_check_meminfo(void)
 					(meminfo.nr_banks - i) * sizeof(*bank));
 				meminfo.nr_banks++;
 				i++;
-				bank[1].size -= vmalloc_limit - bank->start;
+				bank[1].size -= size_limit;
 				bank[1].start = vmalloc_limit;
 				bank[1].highmem = highmem = 1;
 				j++;
 			}
-			bank->size = vmalloc_limit - bank->start;
+			bank->size = size_limit;
 		}
 #else
 		/*
@@ -1037,14 +1041,13 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (bank->start + bank->size > vmalloc_limit)
-			unsigned long newsize = vmalloc_limit - bank->start;
+		if (bank->size > size_limit) {
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
 			       (unsigned long long)bank->start + bank->size - 1,
-			       (unsigned long long)bank->start + newsize - 1);
-			bank->size = newsize;
+			       (unsigned long long)bank->start + size_limit - 1);
+			bank->size = size_limit;
 		}
 #endif
 		if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 17 13:07:47 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 17 May 2013 18:07:47 +0100
Subject: [PATCH 08/14] ARM: LPAE: accomodate >32-bit addresses for page table
 base
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <1368810473-26070-9-git-send-email-will.deacon@arm.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems.  This allows for up to
38-bit physical addresses.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/memory.h | 16 ++++++++++++++++
 arch/arm/kernel/head.S        | 10 ++++------
 arch/arm/kernel/smp.c         | 11 +++++++++--
 arch/arm/mm/proc-v7-3level.S  |  8 ++++++++
 4 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 57870ab..e506088 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
 
+#include <asm/cache.h>
+
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
 #endif
@@ -141,6 +143,20 @@
 #define page_to_phys(page)	(__pfn_to_phys(page_to_pfn(page)))
 #define phys_to_page(phys)	(pfn_to_page(__phys_to_pfn(phys)))
 
+/*
+ * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
+ * around in head.S and proc-*.S are shifted by this amount, in order to
+ * leave spare high bits for systems with physical address extension.  This
+ * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
+ * gives us about 38-bits or so.
+ */
+#ifdef CONFIG_ARM_LPAE
+#define ARCH_PGD_SHIFT		L1_CACHE_SHIFT
+#else
+#define ARCH_PGD_SHIFT		0
+#endif
+#define ARCH_PGD_MASK		((1 << ARCH_PGD_SHIFT) - 1)
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 8bac553..45e8935 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -156,7 +156,7 @@ ENDPROC(stext)
  *
  * Returns:
  *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  */
 __create_page_tables:
 	pgtbl	r4, r8				@ page table address
@@ -331,6 +331,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
 	sub	r4, r4, #0x1000		@ point to the PGD table
+	mov	r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
 	mov	pc, lr
 ENDPROC(__create_page_tables)
@@ -408,7 +409,7 @@ __secondary_data:
  *  r0  = cp#15 control register
  *  r1  = machine ID
  *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  */
@@ -427,10 +428,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
 	bic	r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
-	mov	r5, #0
-	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
-#else
+#ifndef CONFIG_ARM_LPAE
 	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 47ab905..c9c3f3ad 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -78,6 +78,13 @@ void __init smp_set_ops(struct smp_operations *ops)
 		smp_ops = *ops;
 };
 
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+	phys_addr_t pgdir = virt_to_phys(pgd);
+	BUG_ON(pgdir & ARCH_PGD_MASK);
+	return pgdir >> ARCH_PGD_SHIFT;
+}
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
 	int ret;
@@ -87,8 +94,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 	 * its stack and the page tables.
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-	secondary_data.pgdir = virt_to_phys(idmap_pgd);
-	secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+	secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+	secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
 	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
 	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 58ab747..5ffe195 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -114,6 +114,7 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
+	mov	\tmp, \tmp, lsr #ARCH_PGD_SHIFT
 	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?
 	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
 	orr	\tmp, \tmp, #TTB_EAE
@@ -128,8 +129,15 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
 	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
+	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits
 	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
 	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
+	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
+	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits
+	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
+	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
+	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
 	.endm
 
 	__CPUINIT
-- 
1.8.2.2



From gregory.clement at free-electrons.com  Fri May 17 13:16:36 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 17 May 2013 19:16:36 +0200
Subject: [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts
 updates
In-Reply-To: <1368804061-4421-6-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368804061-4421-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368804061-4421-6-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <519665F4.8090707@free-electrons.com>

On 05/17/2013 05:20 PM, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 272bbc6..2407903 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -23,8 +23,12 @@
>  	compatible = "marvell,armada-370-xp";
>  
>  	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
>  		cpu at 0 {
>  			compatible = "marvell,sheeva-v7";
> +			device_type = "cpu";
> +			reg = <0>;
>  		};
>  	};
>  
> 

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From tony at atomide.com  Fri May 17 13:22:31 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 10:22:31 -0700
Subject: [GIT PULL] ARM: OMAP5: hwmod, prm/cm data files and updates
 for 3.10
In-Reply-To: <5195E380.4040103@ti.com>
References: <1363768852-18125-1-git-send-email-santosh.shilimkar@ti.com>
 <20130401170539.GK10155@atomide.com> <515BA76D.3000302@ti.com>
 <alpine.DEB.2.00.1304031146230.2616@utopia.booyaka.com>
 <515D6020.2030103@ti.com> <20130404165208.GI10155@atomide.com>
 <515DB110.9000503@ti.com> <515F00B8.3000501@ti.com>
 <5195E380.4040103@ti.com>
Message-ID: <20130517172231.GW5600@atomide.com>

* Santosh Shilimkar <santosh.shilimkar at ti.com> [130517 01:02]:
> Paul, Tony,
> 
> On Friday 05 April 2013 10:20 PM, Santosh Shilimkar wrote:
> > On Thursday 04 April 2013 10:27 PM, Santosh Shilimkar wrote:
> >> On Thursday 04 April 2013 10:22 PM, Tony Lindgren wrote:
> >>> * Santosh Shilimkar <santosh.shilimkar at ti.com> [130404 04:15]:
> > [..]
> > 
> >>> Can't we already trim the am33xx hwmod data after your patches for
> >>> v3.10 as am33xx is already DT only? Unfortunately we cannot create
> >>> negative diffstat in other ways for v3.10 merge window as we cannot
> >>> make omap4 DT only just quite yet.
> >>>
> >> Yes we can and I can take a stab it tomorrow. The only thing is I
> >> might need some support for testing but thats manageable. Will
> >> take a stab at it tomorrow and if everything goes well, post a
> >> patch for smae.
> >>
> > Patch for the AM33XX to trim is end of the email. Thanks to
> > Sricharan and Pekon for patch and testing. Looping both
> > Vaibhav's if they have any objection on the patch.
> > 
> > Regards,
> > Santosh
> > 
> > From b95dd33fe59b8e77727eb3b1717d763bbf9a2893 Mon Sep 17 00:00:00 2001
> > From: Sricharan R <r.sricharan at ti.com>
> > Date: Fri, 5 Apr 2013 20:39:12 +0530
> > Subject: [PATCH] ARM: AM33XX: hwmod data: Clean up the data file
> > 
> For whatever reason, we again missed the merge window for the subject
> series, I would like to know your plan on the subject series for
> at least 3.11. Asking *well in advance* to avoid late merge related
> discussions.

Yes, I think we should have now a omap5 hwmod data sized hole coming
up with conversion of omap4 to be DT only. I'll post those patches
today for the board file and legacy mux removal for omap4:

12 files changed, 52 insertions(+), 3260 deletions(-)

Those coupled with your am33xx hwmod cleanup patch and your omap4
hwmod cleanup patch should allow us having the omap5 hwmod data
without making the diffstats look too bad.
 
> Thanks to Vaibhav, AM33XX patch is tested and validated with some
> updates considering upcoming PM support for AM33XX. So that
> patch will be included in the series.
> 
> Rajendra will follow up the patchset if there is some re-basing is
> needed since I will away for few weeks because of travel. 

OK, well the omap4 hwmod clean-up patch depends on first dropping
the above mentioned omap4 legacy files.
 
> OMAP5 data is the *only* thing which is gating the device to boot
> from mainline.

That's great!

Regards,

Tony


From tony at atomide.com  Fri May 17 13:23:35 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 10:23:35 -0700
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <5195C28C.40300@ti.com>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
 <51936946.3030507@iki.fi> <20130516155857.GV5600@atomide.com>
 <519503DA.5070303@iki.fi> <20130516162034.GX5600@atomide.com>
 <5195C28C.40300@ti.com>
Message-ID: <20130517172335.GX5600@atomide.com>

* Kishon Vijay Abraham I <kishon at ti.com> [130516 22:45]:
> Hi,
> 
> On Thursday 16 May 2013 09:50 PM, Tony Lindgren wrote:
> >* Tomi Valkeinen <tomi.valkeinen at iki.fi> [130516 09:11]:
> >>On 16/05/13 18:58, Tony Lindgren wrote:
> >>>* Tomi Valkeinen <tomi.valkeinen at iki.fi> [130515 03:59]:
> >>>
> >>>Just checking.. Do you have CONFIG_OMAP_OCP2SCP=y in your .config? Sounds
> >>>like the some transceivers should depend on that for omap4.
> >>
> >>Yes, I have OCP2SCP=y.
> >
> >Hmm well no idea beyond that then. Sounds like Kishon should check it.
> >
> >>>>The musb-hdrc id is wrong on overo also.
> >>>
> >>>Hmm has there been a fix posted for that?
> >>
> >>I couldn't find with a quick look. We debugged and discussed this on an irc
> >>channel with Kishon, who said he'll send a patch. Changing the musb-hdrc ID
> >>on overo fixed the issue, and it looks very similar to the error on 4430sdp.
> >>The overo fix was just:
> 
> hmm.. I think using device name to bind the controller and the phy
> can no longer be used reliably. I think it's better to have
> something like what Grant suggested in my other patch series.. to
> have the phy reference into the host controllers platform_data
> structure. And for the phy reference I'll have label and id.
> 
> Does this makes sense to you?

Sounds OK to me, but I guess that would be for v3.11. I think we
still need a fix for at least overo for v3.10?

Regards,

Tony


From tony at atomide.com  Fri May 17 13:24:52 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 10:24:52 -0700
Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to
 GFX hwmod
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EC8C092@DBDE04.ent.ti.com>
References: <1367693284-7870-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83EC8C092@DBDE04.ent.ti.com>
Message-ID: <20130517172451.GY5600@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [130517 04:13]:
> 
> > -----Original Message-----
> > From: Hiremath, Vaibhav
> > Sent: Sunday, May 05, 2013 12:18 AM
> > To: linux-omap at vger.kernel.org
> > Cc: tony at atomide.com; linux-arm-kernel at lists.infradead.org; Hiremath,
> > Vaibhav; Paul Walmsley
> > Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to
> > GFX hwmod
> > 
> > GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
> > so update the GFX hwmod data with .rstst_off and .st_shift
> > information.
> > 
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > Cc: Paul Walmsley <paul at pwsan.com>
> > ---
> >  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    3 ++-
> >  1 files changed, 2 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > index d1cf3ab..38c7b04 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > @@ -329,7 +329,7 @@ static struct omap_hwmod_class
> > am33xx_gfx_hwmod_class = {
> >  };
> > 
> >  static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
> > -	{ .name = "gfx", .rst_shift = 0 },
> > +	{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
> >  };
> > 
> >  static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
> > @@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
> >  		.omap4	= {
> >  			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
> >  			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
> > +			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
> >  			.modulemode	= MODULEMODE_SWCTRL,
> >  		},
> >  	},
> > --
> 
> Tony and Paul,
> 
> Any Update on this one as well?

Is this needed for v3.10 as a fix? If so, it should describe the
regression or error.

Regards,

Tony


From Catalin.Marinas at arm.com  Fri May 17 13:32:05 2013
From: Catalin.Marinas at arm.com (Catalin Marinas)
Date: Fri, 17 May 2013 18:32:05 +0100
Subject: [GIT PULL] arm64 fixes for 3.10-rc2
Message-ID: <20130517173205.GA14326@arm.com>

Hi Linus,

Please pull the arm64 patches below. Thanks.

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git tags/arm64-fixes

for you to fetch changes up to 3126976be64bfb4c87297cb022ca815212079aec:

  arm64: debug: fix mdscr.ss check when enabling debug exceptions (2013-05-17 18:24:19 +0100)

----------------------------------------------------------------
Fixes for duplicate definition of early_console, kernel/time/Kconfig
include, __flush_dcache_all() set/way computing, debug (locking, bit
testing). The of_platform_populate() was moved to an arch_init_call() to
allow subsys_init_call() drivers to probe the DT.

----------------------------------------------------------------
Catalin Marinas (2):
      arm64: Invoke the of_platform_populate() at arch_initcall() level
      arm64: Do not source kernel/time/Kconfig explicitly

Chen Gang (1):
      arm64: Fix duplicate definition of early_console

Sukanto Ghosh (1):
      arm64: mm: Fix operands of clz in __flush_dcache_all

Will Deacon (2):
      arm64: debug: clear mdscr_el1 instead of taking the OS lock
      arm64: debug: fix mdscr.ss check when enabling debug exceptions

 arch/arm64/Kconfig                 |  2 --
 arch/arm64/include/asm/assembler.h |  2 +-
 arch/arm64/kernel/debug-monitors.c |  2 --
 arch/arm64/kernel/early_printk.c   |  5 +++--
 arch/arm64/kernel/setup.c          | 12 +++---------
 arch/arm64/mm/cache.S              |  2 +-
 arch/arm64/mm/proc.S               |  3 +--
 7 files changed, 9 insertions(+), 19 deletions(-)


From moinejf at free.fr  Fri May 17 13:40:23 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Fri, 17 May 2013 19:40:23 +0200
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517120115.GF18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
Message-ID: <20130517194023.0c385ea0@armhf>

On Fri, 17 May 2013 13:01:15 +0100
Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> I already said - I don't support DT.  I don't run any DT based ARM
> devices, so I have no experience with DT.  What I care more about
> is a working cubox platform, which afaik DT still can't offer yet.

I like the DT concept. All the job I did on the Cubox is based on DT,
even when I was still using the aweful Marvell and NXP drivers. I have
nothing which is Cubox specific in my kernel, but the driver modules.

> > - CMA helper
> > 
> >   You don't use DRM_KMS_CMA_HELPER and DRM_GEM_CMA_HELPER which would
> >   simplify some code.  
> 
> Possibly, but the biggest win for me is having cacheable gem objects.
> CMA will be a retrograde step for those.

I did not think yet about the possible problems which could be raised
when the output of the video decoding engine, vMeta, will be the LCD
overlay plane.

> > - device tree
> > 
> >   Our driver depends on the DT and, by this way, it may be used for
> >   various boards (Cubox, DB-MV88AP510 Development Board, CompuLab
> >   CM-A510 Board..). Especially, in the Cubox, only a HDMI screen may be
> >   connected, while the display controller permits connection of a smart
> >   panel (port A) and a VGA screen (port B).   
> 
> I only have a Cubox, so I can't test anything but HDMI.

Sebastian has other Dove based machine(s).

> Given that there's big questions about the polarity of signals coming
> out of the Armada 510 (with the invert bits 0, are the syncs positive
> or negative?) I wouldn't like to lead anyone up the path of thinking
> that this driver supports anything but the tested HDMI scenario yet.
> 
> As that information is not in any of the Armada 510 TRMs, and can only
> be discovered by physically probing the signals with a scope... that's
> on my todo list when I feel like dismantling the Cubox and getting the
> soldering iron out to separate the two boards so I can get access to
> the signals.

Yes, from the beginning, Solidrun did not give us any information about
their hardware..., nor about their software! It seems Rabeeh is only
interested by a closed XBMC.

> I've already tried to explain this to Sebastian on IRC, and kept getting
> nonsense back from him.  "You need to program the whole chain".  Yes,
> but that makes no sense to the question I was asking.
> 
> The reason is this:
> +-----------------------------+      +------------------------+
> | Armada510                   |      |   TDA19988             |
> | LCD controller ---> switch ---------> switch --> processing |
> |   VSYNC/HSYNC               |      |                        |
> +-----------------------------+      +------------------------+
> 
> The issue is that each 'switch' point is capable of inverting the sync
> signal.  If you program both identically then you end up with inversion
> following another inversion.  Which means no inversion.  That's why
> I've found Sebastian's answers to be much less than helpful on this
> point.
> 
> What I have found with the NXP TDA19988 driver is that you need to get
> the input syncs to the TDA19988 set to the correct polarity for the
> TDA19988, which _isn't_ what is advertised in the EDID.  The TDA19988
> then has its own processing internally which places the appropriate
> sync codes onto the output data stream.
> 
> In some cases, getting this wrong shifts the displayed image by a few
> pixels/lines.  In other cases you get no output or invalid output which
> isn't recognised by the connected device.

Right. But I found that using Rob's tda988x driver gives me a full
image on my TV set while with NXP's driver, I had more than 20 pixels
lost on each side (left, right, top and bottom).

	[snip]
> > - module loading (si5351, tda998x)
> > 
> >   As our driver is loaded by the Cubox DT, and as the auxilliary drivers
> >   (external clock, HDMI transmitter) may also be modules, a
> >   synchronization mechanism (inspired by the tegra drm driver) permits
> >   the driver to start when all the other drivers are also started.  
> 
> The lack of Si5351 already gets tested on every cubox boot I do.  That
> causes probe deferal, which allows the driver to properly start when
> it becomes ready.
	[snip]

That's what we have. I added an escape mechanism in case the si5351 is
not present (I was waiting for the driver to be in the kernel). In this
case, after a first -EPROBEDEFER, the LCD works with either AXI or the
LCD PLL (both work fine with my TV set at 1920x1080p).

	[snip]
> > - hardware cursor
> > 
> >   Our driver always proposes the HWC 32 (RGBA 64x64).  
> 
> Hardware cursor support is pretty useless.
> 
> In RGBA mode, it's not 64x64 but you get the choice of either 64x32 or
> 32x64.  This is useless for Xorg's purposes, where it really wants a
> 64x64 cursor.  And the XF86 Xorg backend really wants RGBA for hardware
> cursor, not 2bpp.  So my conclusion is that hardware cursor is not worth
> any effort and I've a good mind to strip that out from my driver (which
> will simplify a few places.)
> 
> I've played with the idea of reducing a RGBA cursor down to 2bpp mode
> where we can fit the required size in, but that doesn't work very well.
> 
> Just because the hardware does something doesn't mean you should write
> code for it! :)

Maybe I did not explain correctly: the colored cursor maybe RGB888 +
transparency (64x64) or full ARGB (64x32 or 32x64). I coded the first
case. And, yes, I better like a hardware cursor: it asks for less
computation, and I get it immediately at graphic starting time!

	[snip]
> > - video overlay
> > 
> >   Same as above: the code is in our driver (overlay plane), but it is
> >   not tested.  
> 
> We as a family, have watched many hours of video on mine. :)

I wrote the drm driver because there was no easy way to use the video
decoding engine with vlc and the Marvell's drivers. Now that the driver
runs, the next step was to extend the 'modesetting' X server module to
handle the overlay planes (I wonder why nobody did it yet). But, if you
already have something running, I'd be glad to get it...

	[snip]
> > What do you think about merging?  
> 
> Yes, I think merging the two together would probably be sane. :)

OK.

The first step is "DT or not DT"? For me, the DT is more flexible
(one or two LCDs, smart panel definition, display controller or not..)
and permits easy inclusion of out of tree drivers as the private VPU
and GPU ones.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From linux at arm.linux.org.uk  Fri May 17 14:00:29 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 19:00:29 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517194023.0c385ea0@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
Message-ID: <20130517180028.GK18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 07:40:23PM +0200, Jean-Francois Moine wrote:
> On Fri, 17 May 2013 13:01:15 +0100
> Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> > > - CMA helper
> > > 
> > >   You don't use DRM_KMS_CMA_HELPER and DRM_GEM_CMA_HELPER which would
> > >   simplify some code.  
> > 
> > Possibly, but the biggest win for me is having cacheable gem objects.
> > CMA will be a retrograde step for those.
> 
> I did not think yet about the possible problems which could be raised
> when the output of the video decoding engine, vMeta, will be the LCD
> overlay plane.

Not talking about vMeta here, but the vivante GPU.  vMeta has entirely
different requirements because vMeta does not have any IOMMU, whereas
the GPU has a built-in MMU.  That alone allows us to deal with SHM-backed
buffer objects in a sensible way.

> > I've already tried to explain this to Sebastian on IRC, and kept getting
> > nonsense back from him.  "You need to program the whole chain".  Yes,
> > but that makes no sense to the question I was asking.
> > 
> > The reason is this:
> > +-----------------------------+      +------------------------+
> > | Armada510                   |      |   TDA19988             |
> > | LCD controller ---> switch ---------> switch --> processing |
> > |   VSYNC/HSYNC               |      |                        |
> > +-----------------------------+      +------------------------+
> > 
> > The issue is that each 'switch' point is capable of inverting the sync
> > signal.  If you program both identically then you end up with inversion
> > following another inversion.  Which means no inversion.  That's why
> > I've found Sebastian's answers to be much less than helpful on this
> > point.
> > 
> > What I have found with the NXP TDA19988 driver is that you need to get
> > the input syncs to the TDA19988 set to the correct polarity for the
> > TDA19988, which _isn't_ what is advertised in the EDID.  The TDA19988
> > then has its own processing internally which places the appropriate
> > sync codes onto the output data stream.
> > 
> > In some cases, getting this wrong shifts the displayed image by a few
> > pixels/lines.  In other cases you get no output or invalid output which
> > isn't recognised by the connected device.
> 
> Right. But I found that using Rob's tda988x driver gives me a full
> image on my TV set while with NXP's driver, I had more than 20 pixels
> lost on each side (left, right, top and bottom).

At the moment, Rob's driver has many problems, one of them is that it
mis-programs the NPIX and NLINE registers in such a way that it causes
my TV to complain about the input.  Basically, the driver as it stands
in mainline is totally unusable for me.  The TV doesn't recognise any
output.

Yet, program the device with the CEA mode (where it uses its own internal
settings) and lo and behold, picture.  I tracked that down to NPIX and
NLINE being completely wrong.

What you're actually seeing is what's called "overscan" which is something
that TVs do with broadcast images.  The left and right pixels, top and
bottom lines are always "off screen".  However, our computer displays,
we expect the display to be "underscanned" where the top left and bottom
right most pixels correspond with the corners of the display.

There are bits in the HDMI data stream which tell the TV whether the
display should be overscanned or underscanned.  Unfortunately, many
TVs choose to ignore this data (they're permitted to do this by the
standards), and instead decide that if it's a computer resolution, they
will underscan, otherwise if it's a broadcast resolution, they will
overscan.

That's not a bug in the transmission.  That's a bug in the display device.

> > > - hardware cursor
> > > 
> > >   Our driver always proposes the HWC 32 (RGBA 64x64).  
> > 
> > Hardware cursor support is pretty useless.
> > 
> > In RGBA mode, it's not 64x64 but you get the choice of either 64x32 or
> > 32x64.  This is useless for Xorg's purposes, where it really wants a
> > 64x64 cursor.  And the XF86 Xorg backend really wants RGBA for hardware
> > cursor, not 2bpp.  So my conclusion is that hardware cursor is not worth
> > any effort and I've a good mind to strip that out from my driver (which
> > will simplify a few places.)
> > 
> > I've played with the idea of reducing a RGBA cursor down to 2bpp mode
> > where we can fit the required size in, but that doesn't work very well.
> > 
> > Just because the hardware does something doesn't mean you should write
> > code for it! :)
> 
> Maybe I did not explain correctly: the colored cursor maybe RGB888 +
> transparency (64x64) or full ARGB (64x32 or 32x64). I coded the first
> case. And, yes, I better like a hardware cursor: it asks for less
> computation, and I get it immediately at graphic starting time!

Interesting.  Where did you find the documentation for the transparency?
The FS lists HWC32_TRANS_CNTL but omits to specify where that gets used.

> 	[snip]
> > > - video overlay
> > > 
> > >   Same as above: the code is in our driver (overlay plane), but it is
> > >   not tested.  
> > 
> > We as a family, have watched many hours of video on mine. :)
> 
> I wrote the drm driver because there was no easy way to use the video
> decoding engine with vlc and the Marvell's drivers. Now that the driver
> runs, the next step was to extend the 'modesetting' X server module to
> handle the overlay planes (I wonder why nobody did it yet). But, if you
> already have something running, I'd be glad to get it...

Ahem.  You're duplicating all my work.  I've had working vlc for mpeg2
and mpeg4 (not h264) since August/September last year!

> 	[snip]
> > > What do you think about merging?  
> > 
> > Yes, I think merging the two together would probably be sane. :)
> 
> OK.
> 
> The first step is "DT or not DT"? For me, the DT is more flexible
> (one or two LCDs, smart panel definition, display controller or not..)
> and permits easy inclusion of out of tree drivers as the private VPU
> and GPU ones.

I'd argue supporting both. :)


From linux at arm.linux.org.uk  Fri May 17 14:05:55 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 May 2013 19:05:55 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517180028.GK18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
 <20130517180028.GK18614@n2100.arm.linux.org.uk>
Message-ID: <20130517180555.GL18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 07:00:29PM +0100, Russell King - ARM Linux wrote:
> On Fri, May 17, 2013 at 07:40:23PM +0200, Jean-Francois Moine wrote:
> > Maybe I did not explain correctly: the colored cursor maybe RGB888 +
> > transparency (64x64) or full ARGB (64x32 or 32x64). I coded the first
> > case. And, yes, I better like a hardware cursor: it asks for less
> > computation, and I get it immediately at graphic starting time!
> 
> Interesting.  Where did you find the documentation for the transparency?
> The FS lists HWC32_TRANS_CNTL but omits to specify where that gets used.

Ignore that, I just found the reference (unfortunately wrapped so evince
couldn't find it with a search.)


From santosh.shilimkar at ti.com  Fri May 17 14:23:56 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 17 May 2013 23:53:56 +0530
Subject: [PATCH 00/14] Random LPAE-related patches
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <519675BC.8010800@ti.com>

On Friday 17 May 2013 10:37 PM, Will Deacon wrote:
> Hello,
> 
> This is a collection of LPAE-related patches (mostly fixes) that have
> been kicking around for a while and I've been collecting in one place.
> There were some extra patches for bootmem, but they produced lots of
> warnings and need more thought, so they've not been included here.
> 
> All comments welcome,
> 
> Will
> 
> Cyril Chemparathy (9):
>   ARM: LPAE: use signed arithmetic for mask definitions
>   ARM: LPAE: use phys_addr_t in switch_mm()
>   ARM: LPAE: use 64-bit accessors for TTBR registers
>   ARM: LPAE: factor out T1SZ and TTBR1 computations
>   ARM: LPAE: accomodate >32-bit addresses for page table base
>   ARM: mm: use physical addresses in highmem sanity checks
>   ARM: fix type of PHYS_PFN_OFFSET to unsigned long
>   ARM: mm: cleanup checks for membank overlap with vmalloc area
>   ARM: mm: clean up membank size limit checks
> 
> Vitaly Andrianov (3):
>   ARM: LPAE: use phys_addr_t in alloc_init_pud()
>   ARM: LPAE: use phys_addr_t in free_memmap()
>   ARM: LPAE: use phys_addr_t for initrd location
> 
> Will Deacon (2):
>   ARM: lpae: fix definition of PTE_HWTABLE_PTRS
>   ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions
> 
Thanks for picking up the patches. As off-list discussed, I have
tested these patches along with remainder bootmem related patches.

Feel free to use,
Tested-by: Santosh Shilimkar <santosh.shilimkar at ti.com>



From ddaney.cavm at gmail.com  Fri May 17 14:33:53 2013
From: ddaney.cavm at gmail.com (David Daney)
Date: Fri, 17 May 2013 11:33:53 -0700
Subject: [PATCH] arm64: extable: sort the exception table at build time
In-Reply-To: <1368809021-25130-1-git-send-email-will.deacon@arm.com>
References: <1368809021-25130-1-git-send-email-will.deacon@arm.com>
Message-ID: <51967811.7090709@gmail.com>

On 05/17/2013 09:43 AM, Will Deacon wrote:
> As is done for other architectures, sort the exception table at
> build-time rather than during boot.
>
> Since sortextable appears to be a standalone C program relying on the
> host elf.h to provide EM_AARCH64, I've had to add a conditional check in
> order to allow cross-compilation on machines that aren't running a
> bleeding-edge libc-dev.
>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>   arch/arm64/Kconfig              |  1 +
>   arch/arm64/kernel/vmlinux.lds.S | 15 +++++++--------
>   scripts/sortextable.c           |  5 +++++
>   3 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 48347dc..fb8fd90 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -7,6 +7,7 @@ config ARM64
>   	select ARM_AMBA
>   	select ARM_ARCH_TIMER
>   	select ARM_GIC
> +	select BUILDTIME_EXTABLE_SORT
>   	select CLONE_BACKWARDS
>   	select COMMON_CLK
>   	select GENERIC_CLOCKEVENTS
> diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> index 3fae2be..3d527726 100644
> --- a/arch/arm64/kernel/vmlinux.lds.S
> +++ b/arch/arm64/kernel/vmlinux.lds.S
> @@ -57,6 +57,13 @@ SECTIONS
>
>   	RO_DATA(PAGE_SIZE)
>
> +	. = ALIGN(8);
> +	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
> +		__start___ex_table = .;
> +		*(__ex_table)
> +		__stop___ex_table = .;
> +	}
> +
>   	_etext = .;			/* End of text and rodata section */


You have moved this to rodata.

o Will the runtime sort still work like this?

o Do we care?  Maybe not.

David Daney


>
>   	. = ALIGN(PAGE_SIZE);
> @@ -99,14 +106,6 @@ SECTIONS
>   		READ_MOSTLY_DATA(64)
>
>   		/*
> -		 * The exception fixup table (might need resorting at runtime)
> -		 */
> -		. = ALIGN(32);
> -		__start___ex_table = .;
> -		*(__ex_table)
> -		__stop___ex_table = .;
> -
> -		/*
>   		 * and the usual data section
>   		 */
>   		DATA_DATA
> diff --git a/scripts/sortextable.c b/scripts/sortextable.c
> index 1f10e89..f9ce116 100644
> --- a/scripts/sortextable.c
> +++ b/scripts/sortextable.c
> @@ -31,6 +31,10 @@
>   #include <tools/be_byteshift.h>
>   #include <tools/le_byteshift.h>
>
> +#ifndef EM_AARCH64
> +#define EM_AARCH64	183
> +#endif
> +
>   static int fd_map;	/* File descriptor for file being modified. */
>   static int mmap_failed; /* Boolean flag. */
>   static void *ehdr_curr; /* current ElfXX_Ehdr *  for resource cleanup */
> @@ -249,6 +253,7 @@ do_file(char const *const fname)
>   		custom_sort = sort_relative_table;
>   		break;
>   	case EM_ARM:
> +	case EM_AARCH64:
>   	case EM_MIPS:
>   		break;
>   	}  /* end switch */
>



From mgreer at animalcreek.com  Fri May 17 14:47:13 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Fri, 17 May 2013 11:47:13 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130516183516.GJ5600@atomide.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
 <20130516183516.GJ5600@atomide.com>
Message-ID: <20130517184713.GE28484@animalcreek.com>

On Thu, May 16, 2013 at 11:35:16AM -0700, Tony Lindgren wrote:
> * Yegor Yefremov <yegor_sub1 at visionsystems.de> [130516 05:13]:
> > On 15.05.2013 23:50, Mark A. Greer wrote:
> > > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
> > >> * Mark A. Greer <mgreer at animalcreek.com> [130514 18:57]:
> > >>> On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
> > >>>> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> > >>>> changed PM to not access IVA registers on omaps that don't have
> > >>>> them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
> > >>>> will stay on and block deeper idle states.
> > >>>>
> > >>>> Signed-off-by: Tony Lindgren <tony at atomide.com>
> > >>>>
> > >>>> ---
> > >>>>
> > >>>> Paul & Kevin, do you have better ideas for fixing this?
> > >>>>
> > >>>> --- a/arch/arm/mach-omap2/pm34xx.c
> > >>>> +++ b/arch/arm/mach-omap2/pm34xx.c
> > >>>> @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
> > >>>>  	/* Clear any pending PRCM interrupts */
> > >>>>  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> > >>>>  
> > >>>> -	if (omap3_has_iva())
> > >>>> -		omap3_iva_idle();
> > >>>> +	/*
> > >>>> +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> > >>>> +	 */
> > >>>> +	omap3_iva_idle();
> > >>>>  
> > >>>>  	omap3_d2d_idle();
> > >>>>  }
> > >>>
> > >>> [Kevin, Paul, some background: Tony discovered that the am3703 needs
> > >>> to have omap3_iva_idle() called even though its not supposed to have
> > >>> an IVA.]
> > >>>
> > >>> This is potentially bad for other SoC's that don't have an IVA so I don't
> > >>> think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
> > >>> flag for the am3703 only since its the one with the bug.  Maybe something
> > >>> in id.c:omap3xxx_check_features() but I don't see any existing way to check
> > >>> for an am3703 vs. other am37xx SoCs.  Any ideas?
> > >>>
> > >>> Another option, I suppose, is a dts entry but I don't like that at all.
> > >>
> > >> It seems that iva2_pwrdm is there for all omap3 even if OMAP3_HAS_IVA
> > >> flag is unset. And if that's the case, iva2 clocks still need to be idled
> > >> in all cases.
> > > 
> > > Ahh, this takes us to the "Great TI Docs Mystery" :) -- its basically
> > > impossible to tell because despite what their docs may say, the hardware
> > > can be quite different.  I'm not sure how to proceed other than trial &
> > > error with as many different SoCs as we can find.
> > > 
> > >> It's possible that not all steps in omap3_iva_idle() are needed though.
> > >> I can debug further to see which part of the omap3_iva_idle() are needed.
> > >>
> > >> Mark, do you have some omap3 with no iva (other than am3703) to test the
> > >> idle states with?
> > > 
> > > I have an am35xx which isn't supposed to have an IVA so I can test with it
> > > (although, I'm not sure how well the kernel works on the am35xx these days).
> > > 
> > > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
> > > comes up, see what I can figure out.
> > 
> > I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
> > I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
> 
> OK sounds like Mark's patch as http://www.spinics.net/lists/arm-kernel/msg168865.html
> is needed as a fix.

FYI, that patch works (until recently, anyway) but is an unacceptable approach.

> > I have such a system running, so if you have any other patches/ideas to test, I would do it.
> 
> Well I think my patch does not matter for am3517 as that one has iva2
> while am3703 does not.

To make sure there is no confusion, the am3517 does NOT have an iva2.

Tony was misled by a boot log from an older kernel that didn't have the
patch that unsets the IVA feature flag.

Aside: I have so far been unable to get my am3517evm to come up.

Mark
--


From sam at ravnborg.org  Fri May 17 14:49:50 2013
From: sam at ravnborg.org (Sam Ravnborg)
Date: Fri, 17 May 2013 20:49:50 +0200
Subject: [PATCH] arm64: extable: sort the exception table at build time
In-Reply-To: <1368809021-25130-1-git-send-email-will.deacon@arm.com>
References: <1368809021-25130-1-git-send-email-will.deacon@arm.com>
Message-ID: <20130517184950.GA22304@merkur.ravnborg.org>

On Fri, May 17, 2013 at 05:43:41PM +0100, Will Deacon wrote:
> As is done for other architectures, sort the exception table at
> build-time rather than during boot.
> 
> Since sortextable appears to be a standalone C program relying on the
> host elf.h to provide EM_AARCH64, I've had to add a conditional check in
> order to allow cross-compilation on machines that aren't running a
> bleeding-edge libc-dev.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm64/Kconfig              |  1 +
>  arch/arm64/kernel/vmlinux.lds.S | 15 +++++++--------
>  scripts/sortextable.c           |  5 +++++
>  3 files changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 48347dc..fb8fd90 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -7,6 +7,7 @@ config ARM64
>  	select ARM_AMBA
>  	select ARM_ARCH_TIMER
>  	select ARM_GIC
> +	select BUILDTIME_EXTABLE_SORT
>  	select CLONE_BACKWARDS
>  	select COMMON_CLK
>  	select GENERIC_CLOCKEVENTS
> diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> index 3fae2be..3d527726 100644
> --- a/arch/arm64/kernel/vmlinux.lds.S
> +++ b/arch/arm64/kernel/vmlinux.lds.S
> @@ -57,6 +57,13 @@ SECTIONS
>  
>  	RO_DATA(PAGE_SIZE)
>  
> +	. = ALIGN(8);
> +	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
> +		__start___ex_table = .;
> +		*(__ex_table)
> +		__stop___ex_table = .;
> +	}

Here you could use:
     EXCEPTION_TABLE(align)

(From include/asm-generic/vmlinux.lds.h)

	Sam


From oliver+list at schinagl.nl  Fri May 17 14:54:45 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Fri, 17 May 2013 20:54:45 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <4144514.S8gIuIKLrJ@wuerfel>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <4144514.S8gIuIKLrJ@wuerfel>
Message-ID: <51967CF5.7060806@schinagl.nl>

On 05/17/13 15:45, Arnd Bergmann wrote:
> On Friday 17 May 2013 15:35:43 Oliver Schinagl wrote:
>> +static struct bin_attribute sid_bin_attr = {
>> +       .attr = {
>> +               .name = "key",
>> +               .mode = S_IRUGO,
>> +       },
>> +       .size = SUNXI_SID_SIZE,
>> +       .read = sid_read,
>> +};
>
> I believe all the other drivers in drivers/misc/eeprom use "eeprom"
> as the name for the attribute, so using "key" here is a bit inconsistent.
>
> Can you change that?
Changed, will wait for more feedback and then use that in the final version.

Should there also be a symlink elsewhere in /sys? Just curious is all.
>
> 	Arnd
>



From moinejf at free.fr  Fri May 17 14:57:17 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Fri, 17 May 2013 20:57:17 +0200
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517180028.GK18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
 <20130517180028.GK18614@n2100.arm.linux.org.uk>
Message-ID: <20130517205717.4d7e5ef9@armhf>

On Fri, 17 May 2013 19:00:29 +0100
Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> > Maybe I did not explain correctly: the colored cursor maybe RGB888 +
> > transparency (64x64) or full ARGB (64x32 or 32x64). I coded the first
> > case. And, yes, I better like a hardware cursor: it asks for less
> > computation, and I get it immediately at graphic starting time!  
> 
> Interesting.  Where did you find the documentation for the transparency?
> The FS lists HWC32_TRANS_CNTL but omits to specify where that gets used.

Simply in the ? 11.3.2.1. The HWC32_TRANS_CNTL SRAM is loaded like the
HWC 2bpp, but with 00 transparent / 01 RGB.

> > The first step is "DT or not DT"? For me, the DT is more flexible
> > (one or two LCDs, smart panel definition, display controller or not..)
> > and permits easy inclusion of out of tree drivers as the private VPU
> > and GPU ones.  
> 
> I'd argue supporting both. :)

Not easy!

If you have not yet looked at our driver, here is how it starts:

- in '/', the DT contains

	video {
		compatible = "marvell,dove-video";
	};

  which loads the dove-drm module.

- its module init function registers the lcd driver, the dcon driver
  and the drm driver.

- the lcd probe function tries to get all the resources for the
  specific LCD from the DT, including the clocks and the HDMI
  transmitter.
  If some resource is lacking, it deferes.
  When all resources are there, it says "present" to the drm driver (see
  below).

  The resources of a LCD are declared in the DT by something like:

  &lcd0 {					/* the iomem and irq are declared
						 * in the Dove global DT */
	status = "okay";			/* this LCD is present and usable */
	clocks = <&core_clk 3>, <0>, <&lcdclk>, <&si5351 0>;
							/* 3 usable clocks */
	marvell,port-type = <11>;			/* HDMIA */
	marvell,external-encoder = <&tda998x>;		/* HDMI slave encoder */
  };

- the dcon probe function gets its resources and says "present" to the
  drm driver.
  Its DT declaration is just:

  &dcon { status = "okay"; };			/* iomem and irq in the Dove DT */

- the drm probe function scans all the DT, counting its usuable devices,
  (i.e. the LCDs and the dcon), and decrement the "present" variable
  accordingly.

- when the "present" variable is null, the active devices have all
  their resources, and, then, the drm driver is activated by a call to
  drm_platform_init().

I don't see clearly how to do that with a static initialization, and I
don't want to write a "cubox-setup.c". A kernel CONFIG_CUBOX ?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From mgreer at animalcreek.com  Fri May 17 14:56:20 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Fri, 17 May 2013 11:56:20 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <5194B2A8.8020608@visionsystems.de>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
Message-ID: <20130517185620.GF28484@animalcreek.com>

On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
> On 15.05.2013 23:50, Mark A. Greer wrote:
> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:

> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
> >> idle states with?
> > 
> > I have an am35xx which isn't supposed to have an IVA so I can test with it
> > (although, I'm not sure how well the kernel works on the am35xx these days).
> > 
> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
> > comes up, see what I can figure out.
> 
> I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
> 
> I have such a system running, so if you have any other patches/ideas to test, I would do it.

Yegor, since I've so far been unable to get my am3517evm to fire up, can
you play around with the 3517 to see if there appears to be iva registers
that can be read/written to safely?  In particular, can the code that idles
the iva be run safely on an am3517?

Thanks,

Mark
--


From dianders at chromium.org  Fri May 17 15:17:02 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 12:17:02 -0700
Subject: [PATCH 1/6] pinctrl: exynos: Add support for set_irq_wake of
 wake-up EINTs
In-Reply-To: <1368807872-2601-2-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-2-git-send-email-t.figa@samsung.com>
Message-ID: <CAD=FV=V-GfvVi++6Mrz2d=idRkj3q5O0NQQmCGE=0vi1=sD5cA@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> This patch adds support of IRQ wake-up ability configuration for
> wake-up EINTs on Exynos SoCs.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/pinctrl/pinctrl-exynos.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)

On exynos5250-snow (pinmux backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>


From tony at atomide.com  Fri May 17 15:17:46 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:17:46 -0700
Subject: [PATCH 0/6] Drop legacy booting for omap4 for v3.11,
 boot with device tree only
Message-ID: <20130517191304.468.73487.stgit@localhost>

Hi all,

Here are patches against v3.10-rc1 to drop omap4 legacy booting as
things are now working well enough for booting omap4 with device
tree.

We already have am33xx and omap5 booting with device tree only,
and converting omap4 is relatively easy with just two board-*.c
files merged as we have not accepted any new board-*.c files for
quite some time now.

By working "well enough" I mean that I can use my omap4 panda-es
with device tree with a Motorola LapDock with HDMI, DVI, HID, USB
and WLAN using v3.10-rc1 and the patches in this series plus some
extra patches that are driver related.

Of course some things will need more work, like PM. But that
has not yet been fully working for omap4 anyways, and that
work can now be combined with omap5 PM work to some extent.

Regards,

Tony


FYI, the extra patches I'm using in addition to these are:

1. GPIO regression fix (needed at least for SDP nfsroot)

   ab6ec0fb (gpio/omap: ensure gpio context is initialised)

2. HSMMC DT pbias fix

  [PATCH] mmc: omap_hsmmc: Fix the DT pbias workaround for MMC controllers 2 to 5

3. WL12XX support patches

   [PATCH 0/3] WLAN support for omap4 when booted with devicetree

4. USB host support for panda dts changes

   ARM: dts: omap4-panda: Add USB Host support

5. Fix for LapDock enumeration

   usb: musb: Fix LapDock enumeration on omap for boot and slow cable insertion

---

Tony Lindgren (6):
      ARM: OMAP2+: Remove board-4430sdp.c
      ARM: OMAP2+: Remove board-omap4panda.c
      ARM: OMAP2+: Remove legacy mux data for omap4
      ARM: OMAP2+: Remove omap4 pdata from hsmmc.c
      ARM: OMAP2+: Remove omap4 pdata for USB
      ARM: OMAP2+: Remove omap4 ocp2scp pdata


 arch/arm/mach-omap2/Kconfig                |   22 
 arch/arm/mach-omap2/Makefile               |    3 
 arch/arm/mach-omap2/board-4430sdp.c        |  765 ----------------
 arch/arm/mach-omap2/board-omap4panda.c     |  455 ---------
 arch/arm/mach-omap2/devices.c              |  123 ---
 arch/arm/mach-omap2/hsmmc.c                |  103 --
 arch/arm/mach-omap2/mux.h                  |    3 
 arch/arm/mach-omap2/mux44xx.c              | 1356 ----------------------------
 arch/arm/mach-omap2/mux44xx.h              |  298 ------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   21 
 arch/arm/mach-omap2/usb-host.c             |  194 ----
 arch/arm/mach-omap2/usb-musb.c             |    3 
 drivers/bus/omap-ocp2scp.c                 |   60 -
 include/linux/platform_data/omap_ocp2scp.h |   31 -
 14 files changed, 10 insertions(+), 3427 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/board-4430sdp.c
 delete mode 100644 arch/arm/mach-omap2/board-omap4panda.c
 delete mode 100644 arch/arm/mach-omap2/mux44xx.c
 delete mode 100644 arch/arm/mach-omap2/mux44xx.h
 delete mode 100644 include/linux/platform_data/omap_ocp2scp.h

-- 
Signature


From tony at atomide.com  Fri May 17 15:17:51 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:17:51 -0700
Subject: [PATCH 1/6] ARM: OMAP2+: Remove board-4430sdp.c
In-Reply-To: <20130517191304.468.73487.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
Message-ID: <20130517191751.468.89202.stgit@localhost>

We can now boot with device tree. If you don't want to update u-boot,
you can boot with appended DTB with the following instructions:

1. Make sure you have the appended DTB support in .config

   CONFIG_ARM_APPENDED_DTB=y
   CONFIG_ARM_ATAG_DTB_COMPAT=y
   CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y

2. Build the zImage

   $ ARCH=arm CROSS_COMPILE=... make zImage

3. Build the device tree blobs

   $ ARCH=arm CROSS_COMPILE=... make dtbs

4. Append the dtb to zImage

   $ cat arch/arm/boot/zImage arch/arm/boot/dts/omap4-sdp.dtb > /tmp/appended

5. Use mkimage to produce the appended device tree uImage

   $ mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 \
     -n "Linux" -d /tmp/appended /tmp/uImage

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig         |    8 
 arch/arm/mach-omap2/Makefile        |    1 
 arch/arm/mach-omap2/board-4430sdp.c |  765 -----------------------------------
 3 files changed, 774 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/board-4430sdp.c

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..465edd1 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -378,14 +378,6 @@ config MACH_TI8148EVM
 	depends on SOC_TI81XX
 	default y
 
-config MACH_OMAP_4430SDP
-	bool "OMAP 4430 SDP board"
-	default y
-	depends on ARCH_OMAP4
-	select OMAP_PACKAGE_CBL
-	select OMAP_PACKAGE_CBS
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-
 config MACH_OMAP4_PANDA
 	bool "OMAP4 Panda Board"
 	default y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..875d61d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -251,7 +251,6 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)		+= board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)		+= board-igep0020.o
 obj-$(CONFIG_MACH_TOUCHBOOK)		+= board-omap3touchbook.o
-obj-$(CONFIG_MACH_OMAP_4430SDP)		+= board-4430sdp.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)		+= board-omap4panda.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
deleted file mode 100644
index 56a9a4f..0000000
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/*
- * Board support file for OMAP4430 SDP.
- *
- * Copyright (C) 2009 Texas Instruments
- *
- * Author: Santosh Shilimkar <santosh.shilimkar at ti.com>
- *
- * Based on mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
-#include <linux/gpio_keys.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/pwm.h>
-#include <linux/leds.h>
-#include <linux/leds_pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/omap4-keypad.h>
-#include <linux/usb/musb.h>
-#include <linux/usb/phy.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "omap4-keypad.h"
-#include <linux/wl12xx.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
-
-#include "soc.h"
-#include "mux.h"
-#include "mmc.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "common-board-devices.h"
-#include "dss-common.h"
-
-#define ETH_KS8851_IRQ			34
-#define ETH_KS8851_POWER_ON		48
-#define ETH_KS8851_QUART		138
-#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO	184
-#define OMAP4_SFH7741_ENABLE_GPIO		188
-
-#define GPIO_WIFI_PMENA		54
-#define GPIO_WIFI_IRQ		53
-
-static const int sdp4430_keymap[] = {
-	KEY(0, 0, KEY_E),
-	KEY(0, 1, KEY_R),
-	KEY(0, 2, KEY_T),
-	KEY(0, 3, KEY_HOME),
-	KEY(0, 4, KEY_F5),
-	KEY(0, 5, KEY_UNKNOWN),
-	KEY(0, 6, KEY_I),
-	KEY(0, 7, KEY_LEFTSHIFT),
-
-	KEY(1, 0, KEY_D),
-	KEY(1, 1, KEY_F),
-	KEY(1, 2, KEY_G),
-	KEY(1, 3, KEY_SEND),
-	KEY(1, 4, KEY_F6),
-	KEY(1, 5, KEY_UNKNOWN),
-	KEY(1, 6, KEY_K),
-	KEY(1, 7, KEY_ENTER),
-
-	KEY(2, 0, KEY_X),
-	KEY(2, 1, KEY_C),
-	KEY(2, 2, KEY_V),
-	KEY(2, 3, KEY_END),
-	KEY(2, 4, KEY_F7),
-	KEY(2, 5, KEY_UNKNOWN),
-	KEY(2, 6, KEY_DOT),
-	KEY(2, 7, KEY_CAPSLOCK),
-
-	KEY(3, 0, KEY_Z),
-	KEY(3, 1, KEY_KPPLUS),
-	KEY(3, 2, KEY_B),
-	KEY(3, 3, KEY_F1),
-	KEY(3, 4, KEY_F8),
-	KEY(3, 5, KEY_UNKNOWN),
-	KEY(3, 6, KEY_O),
-	KEY(3, 7, KEY_SPACE),
-
-	KEY(4, 0, KEY_W),
-	KEY(4, 1, KEY_Y),
-	KEY(4, 2, KEY_U),
-	KEY(4, 3, KEY_F2),
-	KEY(4, 4, KEY_VOLUMEUP),
-	KEY(4, 5, KEY_UNKNOWN),
-	KEY(4, 6, KEY_L),
-	KEY(4, 7, KEY_LEFT),
-
-	KEY(5, 0, KEY_S),
-	KEY(5, 1, KEY_H),
-	KEY(5, 2, KEY_J),
-	KEY(5, 3, KEY_F3),
-	KEY(5, 4, KEY_F9),
-	KEY(5, 5, KEY_VOLUMEDOWN),
-	KEY(5, 6, KEY_M),
-	KEY(5, 7, KEY_RIGHT),
-
-	KEY(6, 0, KEY_Q),
-	KEY(6, 1, KEY_A),
-	KEY(6, 2, KEY_N),
-	KEY(6, 3, KEY_BACK),
-	KEY(6, 4, KEY_BACKSPACE),
-	KEY(6, 5, KEY_UNKNOWN),
-	KEY(6, 6, KEY_P),
-	KEY(6, 7, KEY_UP),
-
-	KEY(7, 0, KEY_PROG1),
-	KEY(7, 1, KEY_PROG2),
-	KEY(7, 2, KEY_PROG3),
-	KEY(7, 3, KEY_PROG4),
-	KEY(7, 4, KEY_F4),
-	KEY(7, 5, KEY_UNKNOWN),
-	KEY(7, 6, KEY_OK),
-	KEY(7, 7, KEY_DOWN),
-};
-static struct omap_device_pad keypad_pads[] = {
-	{	.name   = "kpd_col1.kpd_col1",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "kpd_col1.kpd_col1",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "kpd_col2.kpd_col2",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "kpd_col3.kpd_col3",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "kpd_col4.kpd_col4",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "kpd_col5.kpd_col5",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "gpmc_a23.kpd_col7",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "gpmc_a22.kpd_col6",
-		.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-	},
-	{	.name   = "kpd_row0.kpd_row0",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "kpd_row1.kpd_row1",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "kpd_row2.kpd_row2",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "kpd_row3.kpd_row3",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "kpd_row4.kpd_row4",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "kpd_row5.kpd_row5",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "gpmc_a18.kpd_row6",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-	{	.name   = "gpmc_a19.kpd_row7",
-		.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-			OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-	},
-};
-
-static struct matrix_keymap_data sdp4430_keymap_data = {
-	.keymap			= sdp4430_keymap,
-	.keymap_size		= ARRAY_SIZE(sdp4430_keymap),
-};
-
-static struct omap4_keypad_platform_data sdp4430_keypad_data = {
-	.keymap_data		= &sdp4430_keymap_data,
-	.rows			= 8,
-	.cols			= 8,
-};
-
-static struct omap_board_data keypad_data = {
-	.id	    		= 1,
-	.pads	 		= keypad_pads,
-	.pads_cnt       	= ARRAY_SIZE(keypad_pads),
-};
-
-static struct gpio_led sdp4430_gpio_leds[] = {
-	{
-		.name	= "omap4:green:debug0",
-		.gpio	= 61,
-	},
-	{
-		.name	= "omap4:green:debug1",
-		.gpio	= 30,
-	},
-	{
-		.name	= "omap4:green:debug2",
-		.gpio	= 7,
-	},
-	{
-		.name	= "omap4:green:debug3",
-		.gpio	= 8,
-	},
-	{
-		.name	= "omap4:green:debug4",
-		.gpio	= 50,
-	},
-	{
-		.name	= "omap4:blue:user",
-		.gpio	= 169,
-	},
-	{
-		.name	= "omap4:red:user",
-		.gpio	= 170,
-	},
-	{
-		.name	= "omap4:green:user",
-		.gpio	= 139,
-	},
-
-};
-
-static struct gpio_keys_button sdp4430_gpio_keys[] = {
-	{
-		.desc			= "Proximity Sensor",
-		.type			= EV_SW,
-		.code			= SW_FRONT_PROXIMITY,
-		.gpio			= OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
-		.active_low		= 0,
-	}
-};
-
-static struct gpio_led_platform_data sdp4430_led_data = {
-	.leds	= sdp4430_gpio_leds,
-	.num_leds	= ARRAY_SIZE(sdp4430_gpio_leds),
-};
-
-static struct pwm_lookup sdp4430_pwm_lookup[] = {
-	PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"),
-	PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL),
-	PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"),
-};
-
-static struct led_pwm sdp4430_pwm_leds[] = {
-	{
-		.name		= "omap4::keypad",
-		.max_brightness	= 127,
-		.pwm_period_ns	= 7812500,
-	},
-	{
-		.name		= "omap4:green:chrg",
-		.max_brightness	= 255,
-		.pwm_period_ns	= 7812500,
-	},
-};
-
-static struct led_pwm_platform_data sdp4430_pwm_data = {
-	.num_leds	= ARRAY_SIZE(sdp4430_pwm_leds),
-	.leds		= sdp4430_pwm_leds,
-};
-
-static struct platform_device sdp4430_leds_pwm = {
-	.name	= "leds_pwm",
-	.id	= -1,
-	.dev	= {
-		.platform_data = &sdp4430_pwm_data,
-	},
-};
-
-/* Dummy regulator for pwm-backlight driver */
-static struct regulator_consumer_supply backlight_supply =
-	REGULATOR_SUPPLY("enable", "pwm-backlight");
-
-static struct platform_pwm_backlight_data sdp4430_backlight_data = {
-	.max_brightness = 127,
-	.dft_brightness = 127,
-	.pwm_period_ns = 7812500,
-};
-
-static struct platform_device sdp4430_backlight_pwm = {
-	.name   = "pwm-backlight",
-	.id     = -1,
-	.dev    = {
-		.platform_data = &sdp4430_backlight_data,
-	},
-};
-
-static int omap_prox_activate(struct device *dev)
-{
-	gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
-	return 0;
-}
-
-static void omap_prox_deactivate(struct device *dev)
-{
-	gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
-}
-
-static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
-	.buttons	= sdp4430_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(sdp4430_gpio_keys),
-	.enable		= omap_prox_activate,
-	.disable	= omap_prox_deactivate,
-};
-
-static struct platform_device sdp4430_gpio_keys_device = {
-	.name	= "gpio-keys",
-	.id	= -1,
-	.dev	= {
-		.platform_data	= &sdp4430_gpio_keys_data,
-	},
-};
-
-static struct platform_device sdp4430_leds_gpio = {
-	.name	= "leds-gpio",
-	.id	= -1,
-	.dev	= {
-		.platform_data = &sdp4430_led_data,
-	},
-};
-static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
-	{
-		.modalias               = "ks8851",
-		.bus_num                = 1,
-		.chip_select            = 0,
-		.max_speed_hz           = 24000000,
-		/*
-		 * .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
-		 * in omap_4430sdp_init
-		 */
-	},
-};
-
-static struct gpio sdp4430_eth_gpios[] __initdata = {
-	{ ETH_KS8851_POWER_ON,	GPIOF_OUT_INIT_HIGH,	"eth_power"	},
-	{ ETH_KS8851_QUART,	GPIOF_OUT_INIT_HIGH,	"quart"		},
-	{ ETH_KS8851_IRQ,	GPIOF_IN,		"eth_irq"	},
-};
-
-static int __init omap_ethernet_init(void)
-{
-	int status;
-
-	/* Request of GPIO lines */
-	status = gpio_request_array(sdp4430_eth_gpios,
-				    ARRAY_SIZE(sdp4430_eth_gpios));
-	if (status)
-		pr_err("Cannot request ETH GPIOs\n");
-
-	return status;
-}
-
-static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
-	REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
-	REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
-};
-
-static struct regulator_init_data sdp4430_vbat_data = {
-	.constraints = {
-		.always_on	= 1,
-	},
-	.num_consumer_supplies	= ARRAY_SIZE(sdp4430_vbat_supply),
-	.consumer_supplies	= sdp4430_vbat_supply,
-};
-
-static struct fixed_voltage_config sdp4430_vbat_pdata = {
-	.supply_name	= "VBAT",
-	.microvolts	= 3750000,
-	.init_data	= &sdp4430_vbat_data,
-	.gpio		= -EINVAL,
-};
-
-static struct platform_device sdp4430_vbat = {
-	.name		= "reg-fixed-voltage",
-	.id		= -1,
-	.dev = {
-		.platform_data = &sdp4430_vbat_pdata,
-	},
-};
-
-static struct platform_device sdp4430_dmic_codec = {
-	.name	= "dmic-codec",
-	.id	= -1,
-};
-
-static struct platform_device sdp4430_hdmi_audio_codec = {
-	.name	= "hdmi-audio-codec",
-	.id	= -1,
-};
-
-static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
-	.card_name = "SDP4430",
-	.has_hs		= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	.has_hf		= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	.has_ep		= 1,
-	.has_aux	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	.has_vibra	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-
-	.has_dmic	= 1,
-	.has_hsmic	= 1,
-	.has_mainmic	= 1,
-	.has_submic	= 1,
-	.has_afm	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-
-	.jack_detection = 1,
-	/* MCLK input is 38.4MHz */
-	.mclk_freq	= 38400000,
-};
-
-static struct platform_device sdp4430_abe_audio = {
-	.name		= "omap-abe-twl6040",
-	.id		= -1,
-	.dev = {
-		.platform_data = &sdp4430_abe_audio_data,
-	},
-};
-
-static struct platform_device *sdp4430_devices[] __initdata = {
-	&sdp4430_gpio_keys_device,
-	&sdp4430_leds_gpio,
-	&sdp4430_leds_pwm,
-	&sdp4430_backlight_pwm,
-	&sdp4430_vbat,
-	&sdp4430_dmic_codec,
-	&sdp4430_abe_audio,
-	&sdp4430_hdmi_audio_codec,
-};
-
-static struct omap_musb_board_data musb_board_data = {
-	.interface_type		= MUSB_INTERFACE_UTMI,
-	.mode			= MUSB_OTG,
-	.power			= 100,
-};
-
-static struct omap2_hsmmc_info mmc[] = {
-	{
-		.mmc		= 2,
-		.caps		=  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-		.gpio_cd	= -EINVAL,
-		.gpio_wp	= -EINVAL,
-		.nonremovable   = true,
-		.ocr_mask	= MMC_VDD_29_30,
-		.no_off_init	= true,
-	},
-	{
-		.mmc		= 1,
-		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-		.gpio_cd	= -EINVAL,
-		.gpio_wp	= -EINVAL,
-	},
-	{
-		.mmc		= 5,
-		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-		.pm_caps	= MMC_PM_KEEP_POWER,
-		.gpio_cd	= -EINVAL,
-		.gpio_wp	= -EINVAL,
-		.ocr_mask	= MMC_VDD_165_195,
-		.nonremovable	= true,
-	},
-	{}	/* Terminator */
-};
-
-static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
-	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
-};
-
-static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = {
-	.supply = "vmmc",
-	.dev_name = "omap_hsmmc.4",
-};
-
-static struct regulator_init_data sdp4430_vmmc5 = {
-	.constraints = {
-		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-	},
-	.num_consumer_supplies = 1,
-	.consumer_supplies = &omap4_sdp4430_vmmc5_supply,
-};
-
-static struct fixed_voltage_config sdp4430_vwlan = {
-	.supply_name		= "vwl1271",
-	.microvolts		= 1800000, /* 1.8V */
-	.gpio			= GPIO_WIFI_PMENA,
-	.startup_delay		= 70000, /* 70msec */
-	.enable_high		= 1,
-	.enabled_at_boot	= 0,
-	.init_data		= &sdp4430_vmmc5,
-};
-
-static struct platform_device omap_vwlan_device = {
-	.name		= "reg-fixed-voltage",
-	.id		= 1,
-	.dev = {
-		.platform_data = &sdp4430_vwlan,
-	},
-};
-
-static struct regulator_init_data sdp4430_vaux1 = {
-	.constraints = {
-		.min_uV			= 1000000,
-		.max_uV			= 3000000,
-		.apply_uV		= true,
-		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-					| REGULATOR_MODE_STANDBY,
-		.valid_ops_mask	 = REGULATOR_CHANGE_VOLTAGE
-					| REGULATOR_CHANGE_MODE
-					| REGULATOR_CHANGE_STATUS,
-	},
-	.num_consumer_supplies  = ARRAY_SIZE(sdp4430_vaux_supply),
-	.consumer_supplies      = sdp4430_vaux_supply,
-};
-
-static struct regulator_init_data sdp4430_vusim = {
-	.constraints = {
-		.min_uV			= 1200000,
-		.max_uV			= 2900000,
-		.apply_uV		= true,
-		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-					| REGULATOR_MODE_STANDBY,
-		.valid_ops_mask	 = REGULATOR_CHANGE_VOLTAGE
-					| REGULATOR_CHANGE_MODE
-					| REGULATOR_CHANGE_STATUS,
-	},
-};
-
-static struct twl6040_codec_data twl6040_codec = {
-	/* single-step ramp for headset and handsfree */
-	.hs_left_step	= 0x0f,
-	.hs_right_step	= 0x0f,
-	.hf_left_step	= 0x1d,
-	.hf_right_step	= 0x1d,
-};
-
-static struct twl6040_vibra_data twl6040_vibra = {
-	.vibldrv_res = 8,
-	.vibrdrv_res = 3,
-	.viblmotor_res = 10,
-	.vibrmotor_res = 10,
-	.vddvibl_uV = 0,	/* fixed volt supply - VBAT */
-	.vddvibr_uV = 0,	/* fixed volt supply - VBAT */
-};
-
-static struct twl6040_platform_data twl6040_data = {
-	.codec		= &twl6040_codec,
-	.vibra		= &twl6040_vibra,
-	.audpwron_gpio	= 127,
-};
-
-static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
-	{
-		I2C_BOARD_INFO("twl6040", 0x4b),
-		.irq = 119 + OMAP44XX_IRQ_GIC_START,
-		.platform_data = &twl6040_data,
-	},
-};
-
-static struct twl4030_platform_data sdp4430_twldata = {
-	/* Regulators */
-	.vusim		= &sdp4430_vusim,
-	.vaux1		= &sdp4430_vaux1,
-};
-
-static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
-	{
-		I2C_BOARD_INFO("tmp105", 0x48),
-	},
-	{
-		I2C_BOARD_INFO("bh1780", 0x29),
-	},
-};
-static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
-	{
-		I2C_BOARD_INFO("hmc5843", 0x1e),
-	},
-};
-static int __init omap4_i2c_init(void)
-{
-	omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
-			TWL_COMMON_REGULATOR_VDAC |
-			TWL_COMMON_REGULATOR_VAUX2 |
-			TWL_COMMON_REGULATOR_VAUX3 |
-			TWL_COMMON_REGULATOR_VMMC |
-			TWL_COMMON_REGULATOR_VPP |
-			TWL_COMMON_REGULATOR_VANA |
-			TWL_COMMON_REGULATOR_VCXIO |
-			TWL_COMMON_REGULATOR_VUSB |
-			TWL_COMMON_REGULATOR_CLK32KG |
-			TWL_COMMON_REGULATOR_V1V8 |
-			TWL_COMMON_REGULATOR_V2V1);
-	omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
-			ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
-	omap_register_i2c_bus(2, 400, NULL, 0);
-	omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
-				ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
-	omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
-				ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
-	return 0;
-}
-
-static void __init omap_sfh7741prox_init(void)
-{
-	int error;
-
-	error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
-				 GPIOF_OUT_INIT_LOW, "sfh7741");
-	if (error < 0)
-		pr_err("%s:failed to request GPIO %d, error %d\n",
-			__func__, OMAP4_SFH7741_ENABLE_GPIO, error);
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-	OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-	/* NIRQ2 for twl6040 */
-	OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
-		  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-	/* GPIO_127 for twl6040 */
-	OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-	/* McPDM */
-	OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	/* DMIC */
-	OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-	OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	/* McBSP1 */
-	OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-		  OMAP_PULL_ENA),
-	OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	/* McBSP2 */
-	OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-		  OMAP_PULL_ENA),
-	OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-#else
-#define board_mux	NULL
- #endif
-
-static void __init omap4_sdp4430_wifi_mux_init(void)
-{
-	omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
-				OMAP_PIN_OFF_WAKEUPENABLE);
-	omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT);
-
-	omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd",
-				OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-	omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk",
-				OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-	omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0",
-				OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-	omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1",
-				OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-	omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2",
-				OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-	omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3",
-				OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-
-}
-
-static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-	.board_ref_clock = WL12XX_REFCLOCK_26,
-	.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
-};
-
-static void __init omap4_sdp4430_wifi_init(void)
-{
-	int ret;
-
-	omap4_sdp4430_wifi_mux_init();
-	omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
-	ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
-	if (ret)
-		pr_err("Error setting wl12xx data: %d\n", ret);
-	ret = platform_device_register(&omap_vwlan_device);
-	if (ret)
-		pr_err("Error registering wl12xx device: %d\n", ret);
-}
-
-static void __init omap_4430sdp_init(void)
-{
-	int status;
-	int package = OMAP_PACKAGE_CBS;
-
-	if (omap_rev() == OMAP4430_REV_ES1_0)
-		package = OMAP_PACKAGE_CBL;
-	omap4_mux_init(board_mux, NULL, package);
-
-	omap4_i2c_init();
-	omap_sfh7741prox_init();
-	regulator_register_always_on(0, "backlight-enable",
-				     &backlight_supply, 1, 0);
-	platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-	omap_serial_init();
-	omap_sdrc_init(NULL, NULL);
-	omap4_sdp4430_wifi_init();
-	omap4_twl6030_hsmmc_init(mmc);
-
-	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
-	usb_musb_init(&musb_board_data);
-
-	status = omap_ethernet_init();
-	if (status) {
-		pr_err("Ethernet initialization failed: %d\n", status);
-	} else {
-		sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
-		spi_register_board_info(sdp4430_spi_board_info,
-				ARRAY_SIZE(sdp4430_spi_board_info));
-	}
-
-	pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup));
-	status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
-	if (status)
-		pr_err("Keypad initialization failed: %d\n", status);
-
-	omap_4430sdp_display_init();
-}
-
-MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
-	/* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
-	.atag_offset	= 0x100,
-	.smp		= smp_ops(omap4_smp_ops),
-	.reserve	= omap_reserve,
-	.map_io		= omap4_map_io,
-	.init_early	= omap4430_init_early,
-	.init_irq	= gic_init_irq,
-	.init_machine	= omap_4430sdp_init,
-	.init_late	= omap4430_init_late,
-	.init_time	= omap4_local_timer_init,
-	.restart	= omap44xx_restart,
-MACHINE_END



From tony at atomide.com  Fri May 17 15:17:59 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:17:59 -0700
Subject: [PATCH 4/6] ARM: OMAP2+: Remove omap4 pdata from hsmmc.c
In-Reply-To: <20130517191304.468.73487.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
Message-ID: <20130517191759.468.9983.stgit@localhost>

This is no longer needed as omap4 is now booted using
device tree.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/hsmmc.c |  103 ++++---------------------------------------
 1 file changed, 10 insertions(+), 93 deletions(-)

diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 2ef1f87..07d4c7b 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -29,7 +29,6 @@
 
 static u16 control_pbias_offset;
 static u16 control_devconf1_offset;
-static u16 control_mmc1;
 
 #define HSMMC_NAME_LEN	9
 
@@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
 	}
 }
 
-static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
-				  int power_on, int vdd)
-{
-	u32 reg;
-
-	/*
-	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
-	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
-	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
-	 */
-	reg = omap4_ctrl_pad_readl(control_pbias_offset);
-	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
-		OMAP4_MMC1_PWRDNZ_MASK |
-		OMAP4_MMC1_PBIASLITE_VMODE_MASK);
-	omap4_ctrl_pad_writel(reg, control_pbias_offset);
-}
-
-static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
-				 int power_on, int vdd)
-{
-	u32 reg;
-	unsigned long timeout;
-
-	if (power_on) {
-		reg = omap4_ctrl_pad_readl(control_pbias_offset);
-		reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
-		if ((1 << vdd) <= MMC_VDD_165_195)
-			reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
-		else
-			reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
-		reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
-			OMAP4_MMC1_PWRDNZ_MASK);
-		omap4_ctrl_pad_writel(reg, control_pbias_offset);
-
-		timeout = jiffies + msecs_to_jiffies(5);
-		do {
-			reg = omap4_ctrl_pad_readl(control_pbias_offset);
-			if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
-				break;
-			usleep_range(100, 200);
-		} while (!time_after(jiffies, timeout));
-
-		if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
-			pr_err("Pbias Voltage is not same as LDO\n");
-			/* Caution : On VMODE_ERROR Power Down MMC IO */
-			reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
-			omap4_ctrl_pad_writel(reg, control_pbias_offset);
-		}
-	}
-}
-
 static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
 {
 	u32 reg;
@@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 	mmc->slots[0].pm_caps = c->pm_caps;
 	mmc->slots[0].internal_clock = !c->ext_clock;
 	mmc->max_freq = c->max_freq;
-	if (cpu_is_omap44xx())
-		mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
-	else
-		mmc->reg_offset = 0;
-
+	mmc->reg_offset = 0;
 	mmc->get_context_loss_count = hsmmc_get_context_loss;
 
 	mmc->slots[0].switch_pin = c->gpio_cd;
@@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 	if (!soc_is_am35xx())
 		mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
-	if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
-		mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
-
 	switch (c->mmc) {
 	case 1:
 		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 			/* on-chip level shifting via PBIAS0/PBIAS1 */
-			if (cpu_is_omap44xx()) {
-				mmc->slots[0].before_set_reg =
-						omap4_hsmmc1_before_set_reg;
-				mmc->slots[0].after_set_reg =
-						omap4_hsmmc1_after_set_reg;
-			} else {
-				mmc->slots[0].before_set_reg =
-						omap_hsmmc1_before_set_reg;
-				mmc->slots[0].after_set_reg =
-						omap_hsmmc1_after_set_reg;
-			}
+			mmc->slots[0].before_set_reg =
+					omap_hsmmc1_before_set_reg;
+			mmc->slots[0].after_set_reg =
+					omap_hsmmc1_after_set_reg;
 		}
 
 		if (soc_is_am35xx())
@@ -563,34 +497,17 @@ free_mmc:
 
 void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
-	u32 reg;
-
 	if (omap_hsmmc_done)
 		return;
 
 	omap_hsmmc_done = 1;
 
-	if (!cpu_is_omap44xx()) {
-		if (cpu_is_omap2430()) {
-			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
-			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-		} else {
-			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
-		}
+	if (cpu_is_omap2430()) {
+		control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
+		control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 	} else {
-		control_pbias_offset =
-			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
-		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
-		reg = omap4_ctrl_pad_readl(control_mmc1);
-		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
-			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
-		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
-			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
-		reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
-			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
-			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
-		omap4_ctrl_pad_writel(reg, control_mmc1);
+		control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+		control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 	}
 
 	for (; controllers->mmc; controllers++)



From tony at atomide.com  Fri May 17 15:18:01 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:18:01 -0700
Subject: [PATCH 5/6] ARM: OMAP2+: Remove omap4 pdata for USB
In-Reply-To: <20130517191304.468.73487.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
Message-ID: <20130517191801.468.56731.stgit@localhost>

This is no longer needed as omap4 is now booted
using device tree.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/devices.c  |   45 ---------
 arch/arm/mach-omap2/usb-host.c |  194 ----------------------------------------
 arch/arm/mach-omap2/usb-musb.c |    3 -
 3 files changed, 242 deletions(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4269fc1..0fd3834 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -20,7 +20,6 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
 #include <linux/platform_data/omap_ocp2scp.h>
-#include <linux/usb/omap_control_usb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -253,49 +252,6 @@ static inline void omap_init_camera(void)
 #endif
 }
 
-#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
-static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
-	.type = 1,
-};
-
-struct resource omap4_control_usb_res[] = {
-	{
-		.name	= "control_dev_conf",
-		.start	= 0x4a002300,
-		.end	= 0x4a002303,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.name	= "otghs_control",
-		.start	= 0x4a00233c,
-		.end	= 0x4a00233f,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap4_control_usb = {
-	.name = "omap-control-usb",
-	.id = -1,
-	.dev = {
-		.platform_data = &omap4_control_usb_pdata,
-	},
-	.num_resources = 2,
-	.resource = omap4_control_usb_res,
-};
-
-static inline void __init omap_init_control_usb(void)
-{
-	if (!cpu_is_omap44xx())
-		return;
-
-	if (platform_device_register(&omap4_control_usb))
-		pr_err("Error registering omap_control_usb device\n");
-}
-
-#else
-static inline void omap_init_control_usb(void) { }
-#endif /* CONFIG_OMAP_CONTROL_USB */
-
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
 			*sdp4430_keypad_data, struct omap_board_data *bdata)
 {
@@ -651,7 +607,6 @@ static int __init omap2_init_devices(void)
 	omap_init_mbox();
 	/* If dtb is there, the devices will be created dynamically */
 	if (!of_have_populated_dt()) {
-		omap_init_control_usb();
 		omap_init_dmic();
 		omap_init_mcpdm();
 		omap_init_mcspi();
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f..544c92b 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -188,125 +188,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 	return;
 }
 
-static
-void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
-{
-	switch (port_mode[0]) {
-	case OMAP_EHCI_PORT_MODE_PHY:
-		omap_mux_init_signal("usbb1_ulpiphy_stp",
-			OMAP_PIN_OUTPUT);
-		omap_mux_init_signal("usbb1_ulpiphy_clk",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dir",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_nxt",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat0",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat1",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat2",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat3",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat4",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat5",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat6",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpiphy_dat7",
-			OMAP_PIN_INPUT_PULLDOWN);
-			break;
-	case OMAP_EHCI_PORT_MODE_TLL:
-		omap_mux_init_signal("usbb1_ulpitll_stp",
-			OMAP_PIN_INPUT_PULLUP);
-		omap_mux_init_signal("usbb1_ulpitll_clk",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dir",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_nxt",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat0",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat1",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat2",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat3",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat4",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat5",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat6",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_ulpitll_dat7",
-			OMAP_PIN_INPUT_PULLDOWN);
-			break;
-	case OMAP_USBHS_PORT_MODE_UNUSED:
-	default:
-			break;
-	}
-	switch (port_mode[1]) {
-	case OMAP_EHCI_PORT_MODE_PHY:
-		omap_mux_init_signal("usbb2_ulpiphy_stp",
-			OMAP_PIN_OUTPUT);
-		omap_mux_init_signal("usbb2_ulpiphy_clk",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dir",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_nxt",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat0",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat1",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat2",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat3",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat4",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat5",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat6",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpiphy_dat7",
-			OMAP_PIN_INPUT_PULLDOWN);
-			break;
-	case OMAP_EHCI_PORT_MODE_TLL:
-		omap_mux_init_signal("usbb2_ulpitll_stp",
-			OMAP_PIN_INPUT_PULLUP);
-		omap_mux_init_signal("usbb2_ulpitll_clk",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dir",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_nxt",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat0",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat1",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat2",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat3",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat4",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat5",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat6",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_ulpitll_dat7",
-			OMAP_PIN_INPUT_PULLDOWN);
-			break;
-	case OMAP_USBHS_PORT_MODE_UNUSED:
-	default:
-			break;
-	}
-}
-
 static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
 	switch (port_mode[0]) {
@@ -404,78 +285,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 	}
 }
 
-static
-void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
-{
-	switch (port_mode[0]) {
-	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-		omap_mux_init_signal("usbb1_mm_rxdp",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_mm_rxdm",
-			OMAP_PIN_INPUT_PULLDOWN);
-
-	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-		omap_mux_init_signal("usbb1_mm_rxrcv",
-			OMAP_PIN_INPUT_PULLDOWN);
-
-	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-		omap_mux_init_signal("usbb1_mm_txen",
-			OMAP_PIN_INPUT_PULLDOWN);
-
-
-	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-		omap_mux_init_signal("usbb1_mm_txdat",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb1_mm_txse0",
-			OMAP_PIN_INPUT_PULLDOWN);
-		break;
-
-	case OMAP_USBHS_PORT_MODE_UNUSED:
-	default:
-		break;
-	}
-
-	switch (port_mode[1]) {
-	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-		omap_mux_init_signal("usbb2_mm_rxdp",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_mm_rxdm",
-			OMAP_PIN_INPUT_PULLDOWN);
-
-	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-		omap_mux_init_signal("usbb2_mm_rxrcv",
-			OMAP_PIN_INPUT_PULLDOWN);
-
-	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-		omap_mux_init_signal("usbb2_mm_txen",
-			OMAP_PIN_INPUT_PULLDOWN);
-
-
-	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-		omap_mux_init_signal("usbb2_mm_txdat",
-			OMAP_PIN_INPUT_PULLDOWN);
-		omap_mux_init_signal("usbb2_mm_txse0",
-			OMAP_PIN_INPUT_PULLDOWN);
-		break;
-
-	case OMAP_USBHS_PORT_MODE_UNUSED:
-	default:
-		break;
-	}
-}
-
 void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 {
 	struct omap_hwmod	*uhh_hwm, *tll_hwm;
@@ -489,9 +298,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 		if (omap_rev() <= OMAP3430_REV_ES2_1)
 			pdata->single_ulpi_bypass = true;
 
-	} else if (cpu_is_omap44xx()) {
-		setup_4430ehci_io_mux(pdata->port_mode);
-		setup_4430ohci_io_mux(pdata->port_mode);
 	}
 
 	uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3242a55..8c4de270 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
 	musb_plat.mode = board_data->mode;
 	musb_plat.extvbus = board_data->extvbus;
 
-	if (cpu_is_omap44xx())
-		musb_plat.has_mailbox = true;
-
 	if (soc_is_am35xx()) {
 		oh_name = "am35x_otg_hs";
 		name = "musb-am35x";



From tony at atomide.com  Fri May 17 15:17:53 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:17:53 -0700
Subject: [PATCH 2/6] ARM: OMAP2+: Remove board-omap4panda.c
In-Reply-To: <20130517191304.468.73487.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
Message-ID: <20130517191753.468.1734.stgit@localhost>

We can now boot with device tree. If you don't want to update u-boot,
you can boot with appended DTB with the following instructions:

1. Make sure you have the appended DTB support in .config

   CONFIG_ARM_APPENDED_DTB=y
   CONFIG_ARM_ATAG_DTB_COMPAT=y
   CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y

2. Build the zImage

   $ ARCH=arm CROSS_COMPILE=... make zImage

3. Build the device tree blobs

   $ ARCH=arm CROSS_COMPILE=... make dtbs

4. Append the correct panda dtb to zImage

   Depending on your hardware it's omap4-panda.dtb, omap4-panda-a4.dtb
   or omap4-panda-es.dtb.

   $ cat arch/arm/boot/zImage arch/arm/boot/dts/omap4-panda-es.dtb > /tmp/appended

5. Use mkimage to produce the appended device tree uImage

   $ mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 \
     -n "Linux" -d /tmp/appended /tmp/uImage

Signed-off-by: Tony Lindgren <tony at atomide.com
---
 arch/arm/mach-omap2/Kconfig            |    8 -
 arch/arm/mach-omap2/Makefile           |    1 
 arch/arm/mach-omap2/board-omap4panda.c |  455 --------------------------------
 3 files changed, 464 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/board-omap4panda.c

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 465edd1..1f941c4 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -378,14 +378,6 @@ config MACH_TI8148EVM
 	depends on SOC_TI81XX
 	default y
 
-config MACH_OMAP4_PANDA
-	bool "OMAP4 Panda Board"
-	default y
-	depends on ARCH_OMAP4
-	select OMAP_PACKAGE_CBL
-	select OMAP_PACKAGE_CBS
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-
 config OMAP3_EMU
 	bool "OMAP3 debugging peripherals"
 	depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 875d61d..2cbf3ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -251,7 +251,6 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)		+= board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)		+= board-igep0020.o
 obj-$(CONFIG_MACH_TOUCHBOOK)		+= board-omap3touchbook.o
-obj-$(CONFIG_MACH_OMAP4_PANDA)		+= board-omap4panda.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
deleted file mode 100644
index 1e2c75e..0000000
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- * Board support file for OMAP4430 based PandaBoard.
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * Author: David Anders <x0132446 at ti.com>
- *
- * Based on mach-omap2/board-4430sdp.c
- *
- * Author: Santosh Shilimkar <santosh.shilimkar at ti.com>
- *
- * Based on mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/ti_wilink_st.h>
-#include <linux/usb/musb.h>
-#include <linux/usb/phy.h>
-#include <linux/usb/nop-usb-xceiv.h>
-#include <linux/wl12xx.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "soc.h"
-#include "mmc.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "mux.h"
-#include "common-board-devices.h"
-#include "dss-common.h"
-
-#define GPIO_HUB_POWER		1
-#define GPIO_HUB_NRESET		62
-#define GPIO_WIFI_PMENA		43
-#define GPIO_WIFI_IRQ		53
-
-/* wl127x BT, FM, GPS connectivity chip */
-static struct ti_st_plat_data wilink_platform_data = {
-	.nshutdown_gpio	= 46,
-	.dev_name	= "/dev/ttyO1",
-	.flow_cntrl	= 1,
-	.baud_rate	= 3000000,
-	.chip_enable	= NULL,
-	.suspend	= NULL,
-	.resume		= NULL,
-};
-
-static struct platform_device wl1271_device = {
-	.name	= "kim",
-	.id	= -1,
-	.dev	= {
-		.platform_data	= &wilink_platform_data,
-	},
-};
-
-static struct gpio_led gpio_leds[] = {
-	{
-		.name			= "pandaboard::status1",
-		.default_trigger	= "heartbeat",
-		.gpio			= 7,
-	},
-	{
-		.name			= "pandaboard::status2",
-		.default_trigger	= "mmc0",
-		.gpio			= 8,
-	},
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
-	.leds		= gpio_leds,
-	.num_leds	= ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
-	.name	= "leds-gpio",
-	.id	= -1,
-	.dev	= {
-		.platform_data	= &gpio_led_info,
-	},
-};
-
-static struct omap_abe_twl6040_data panda_abe_audio_data = {
-	/* Audio out */
-	.has_hs		= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	/* HandsFree through expansion connector */
-	.has_hf		= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	/* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
-	.has_aux	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	/* PandaBoard: FM RX, PandaBoardES: audio in */
-	.has_afm	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-	/* No jack detection. */
-	.jack_detection	= 0,
-	/* MCLK input is 38.4MHz */
-	.mclk_freq	= 38400000,
-
-};
-
-static struct platform_device panda_abe_audio = {
-	.name		= "omap-abe-twl6040",
-	.id		= -1,
-	.dev = {
-		.platform_data = &panda_abe_audio_data,
-	},
-};
-
-static struct platform_device panda_hdmi_audio_codec = {
-	.name	= "hdmi-audio-codec",
-	.id	= -1,
-};
-
-static struct platform_device btwilink_device = {
-	.name	= "btwilink",
-	.id	= -1,
-};
-
-/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
-static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
-	/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-	.clk_rate = 19200000,
-};
-
-static struct usbhs_phy_data phy_data[] __initdata = {
-	{
-		.port = 1,
-		.reset_gpio = GPIO_HUB_NRESET,
-		.vcc_gpio = GPIO_HUB_POWER,
-		.vcc_polarity = 1,
-		.platform_data = &hsusb1_phy_data,
-	},
-};
-
-static struct platform_device *panda_devices[] __initdata = {
-	&leds_gpio,
-	&wl1271_device,
-	&panda_abe_audio,
-	&panda_hdmi_audio_codec,
-	&btwilink_device,
-};
-
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-};
-
-static void __init omap4_ehci_init(void)
-{
-	int ret;
-
-	/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-	ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
-	if (ret)
-		pr_err("Failed to add main_clk alias to auxclk3_ck\n");
-
-	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
-	usbhs_init(&usbhs_bdata);
-}
-
-static struct omap_musb_board_data musb_board_data = {
-	.interface_type		= MUSB_INTERFACE_UTMI,
-	.mode			= MUSB_OTG,
-	.power			= 100,
-};
-
-static struct omap2_hsmmc_info mmc[] = {
-	{
-		.mmc		= 1,
-		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-		.gpio_wp	= -EINVAL,
-		.gpio_cd	= -EINVAL,
-	},
-	{
-		.name		= "wl1271",
-		.mmc		= 5,
-		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-		.gpio_wp	= -EINVAL,
-		.gpio_cd	= -EINVAL,
-		.ocr_mask	= MMC_VDD_165_195,
-		.nonremovable	= true,
-	},
-	{}	/* Terminator */
-};
-
-static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
-	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
-};
-
-static struct regulator_init_data panda_vmmc5 = {
-	.constraints = {
-		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
-	.consumer_supplies = omap4_panda_vmmc5_supply,
-};
-
-static struct fixed_voltage_config panda_vwlan = {
-	.supply_name = "vwl1271",
-	.microvolts = 1800000, /* 1.8V */
-	.gpio = GPIO_WIFI_PMENA,
-	.startup_delay = 70000, /* 70msec */
-	.enable_high = 1,
-	.enabled_at_boot = 0,
-	.init_data = &panda_vmmc5,
-};
-
-static struct platform_device omap_vwlan_device = {
-	.name		= "reg-fixed-voltage",
-	.id		= 1,
-	.dev = {
-		.platform_data = &panda_vwlan,
-	},
-};
-
-static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
-};
-
-static struct twl6040_codec_data twl6040_codec = {
-	/* single-step ramp for headset and handsfree */
-	.hs_left_step	= 0x0f,
-	.hs_right_step	= 0x0f,
-	.hf_left_step	= 0x1d,
-	.hf_right_step	= 0x1d,
-};
-
-static struct twl6040_platform_data twl6040_data = {
-	.codec		= &twl6040_codec,
-	.audpwron_gpio	= 127,
-};
-
-static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
-	{
-		I2C_BOARD_INFO("twl6040", 0x4b),
-		.irq = 119 + OMAP44XX_IRQ_GIC_START,
-		.platform_data = &twl6040_data,
-	},
-};
-
-/* Panda board uses the common PMIC configuration */
-static struct twl4030_platform_data omap4_panda_twldata;
-
-/*
- * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
- * is connected as I2C slave device, and can be accessed at address 0x50
- */
-static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
-	{
-		I2C_BOARD_INFO("eeprom", 0x50),
-	},
-};
-
-static int __init omap4_panda_i2c_init(void)
-{
-	omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
-			TWL_COMMON_REGULATOR_VDAC |
-			TWL_COMMON_REGULATOR_VAUX2 |
-			TWL_COMMON_REGULATOR_VAUX3 |
-			TWL_COMMON_REGULATOR_VMMC |
-			TWL_COMMON_REGULATOR_VPP |
-			TWL_COMMON_REGULATOR_VANA |
-			TWL_COMMON_REGULATOR_VCXIO |
-			TWL_COMMON_REGULATOR_VUSB |
-			TWL_COMMON_REGULATOR_CLK32KG |
-			TWL_COMMON_REGULATOR_V1V8 |
-			TWL_COMMON_REGULATOR_V2V1);
-	omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
-			ARRAY_SIZE(panda_i2c_1_boardinfo));
-	omap_register_i2c_bus(2, 400, NULL, 0);
-	/*
-	 * Bus 3 is attached to the DVI port where devices like the pico DLP
-	 * projector don't work reliably with 400kHz
-	 */
-	omap_register_i2c_bus(3, 100, panda_i2c_eeprom,
-					ARRAY_SIZE(panda_i2c_eeprom));
-	omap_register_i2c_bus(4, 400, NULL, 0);
-	return 0;
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-	/* WLAN IRQ - GPIO 53 */
-	OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-	/* WLAN POWER ENABLE - GPIO 43 */
-	OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-	/* WLAN SDIO: MMC5 CMD */
-	OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	/* WLAN SDIO: MMC5 CLK */
-	OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	/* WLAN SDIO: MMC5 DAT[0-3] */
-	OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	/* gpio 0 - TFP410 PD */
-	OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
-	/* dispc2_data23 */
-	OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data22 */
-	OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data21 */
-	OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data20 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data19 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data18 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data15 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data14 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data13 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data12 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data11 */
-	OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data10 */
-	OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data9 */
-	OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data16 */
-	OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data17 */
-	OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_hsync */
-	OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_pclk */
-	OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_vsync */
-	OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_de */
-	OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data8 */
-	OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data7 */
-	OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data6 */
-	OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data5 */
-	OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data4 */
-	OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data3 */
-	OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data2 */
-	OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data1 */
-	OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* dispc2_data0 */
-	OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-	/* NIRQ2 for twl6040 */
-	OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
-		  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-	/* GPIO_127 for twl6040 */
-	OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-	/* McPDM */
-	OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-	OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	/* McBSP1 */
-	OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-	OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-	OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-		  OMAP_PULL_ENA),
-	OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-
-	/* UART2 - BT/FM/GPS shared transport */
-	OMAP4_MUX(UART2_CTS,	OMAP_PIN_INPUT	| OMAP_MUX_MODE0),
-	OMAP4_MUX(UART2_RTS,	OMAP_PIN_OUTPUT	| OMAP_MUX_MODE0),
-	OMAP4_MUX(UART2_RX,	OMAP_PIN_INPUT	| OMAP_MUX_MODE0),
-	OMAP4_MUX(UART2_TX,	OMAP_PIN_OUTPUT	| OMAP_MUX_MODE0),
-
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-#else
-#define board_mux	NULL
-#endif
-
-
-static void omap4_panda_init_rev(void)
-{
-	if (cpu_is_omap443x()) {
-		/* PandaBoard 4430 */
-		/* ASoC audio configuration */
-		panda_abe_audio_data.card_name = "PandaBoard";
-		panda_abe_audio_data.has_hsmic = 1;
-	} else {
-		/* PandaBoard ES */
-		/* ASoC audio configuration */
-		panda_abe_audio_data.card_name = "PandaBoardES";
-	}
-}
-
-static void __init omap4_panda_init(void)
-{
-	int package = OMAP_PACKAGE_CBS;
-	int ret;
-
-	if (omap_rev() == OMAP4430_REV_ES1_0)
-		package = OMAP_PACKAGE_CBL;
-	omap4_mux_init(board_mux, NULL, package);
-
-	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
-	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
-	if (ret)
-		pr_err("error setting wl12xx data: %d\n", ret);
-
-	omap4_panda_init_rev();
-	omap4_panda_i2c_init();
-	platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
-	platform_device_register(&omap_vwlan_device);
-	omap_serial_init();
-	omap_sdrc_init(NULL, NULL);
-	omap4_twl6030_hsmmc_init(mmc);
-	omap4_ehci_init();
-	usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
-	usb_musb_init(&musb_board_data);
-	omap4_panda_display_init();
-}
-
-MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
-	/* Maintainer: David Anders - Texas Instruments Inc */
-	.atag_offset	= 0x100,
-	.smp		= smp_ops(omap4_smp_ops),
-	.reserve	= omap_reserve,
-	.map_io		= omap4_map_io,
-	.init_early	= omap4430_init_early,
-	.init_irq	= gic_init_irq,
-	.init_machine	= omap4_panda_init,
-	.init_late	= omap4430_init_late,
-	.init_time	= omap4_local_timer_init,
-	.restart	= omap44xx_restart,
-MACHINE_END



From tony at atomide.com  Fri May 17 15:18:03 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:18:03 -0700
Subject: [PATCH 6/6] ARM: OMAP2+: Remove omap4 ocp2scp pdata
In-Reply-To: <20130517191304.468.73487.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
Message-ID: <20130517191803.468.32800.stgit@localhost>

This is omap4+ only and no longer needed as omap4+ can be booted
using device tree.

Also remove the related pdata handling from the driver and the
now unneeded platform_data/omap_ocp2scp.h.

Cc: Kishon Vijay Abraham I <kishon at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/devices.c              |   78 ----------------------------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   21 --------
 drivers/bus/omap-ocp2scp.c                 |   60 ----------------------
 include/linux/platform_data/omap_ocp2scp.h |   31 -----------
 4 files changed, 190 deletions(-)
 delete mode 100644 include/linux/platform_data/omap_ocp2scp.h

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 0fd3834..3f2c85a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,7 +19,6 @@
 #include <linux/of.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
-#include <linux/platform_data/omap_ocp2scp.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -513,82 +512,6 @@ static void omap_init_vout(void)
 static inline void omap_init_vout(void) {}
 #endif
 
-#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE)
-static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
-{
-	int cnt	= 0;
-
-	while (ocp2scp_dev->drv_name != NULL) {
-		cnt++;
-		ocp2scp_dev++;
-	}
-
-	return cnt;
-}
-
-static void __init omap_init_ocp2scp(void)
-{
-	struct omap_hwmod	*oh;
-	struct platform_device	*pdev;
-	int			bus_id = -1, dev_cnt = 0, i;
-	struct omap_ocp2scp_dev	*ocp2scp_dev;
-	const char		*oh_name, *name;
-	struct omap_ocp2scp_platform_data *pdata;
-
-	if (!cpu_is_omap44xx())
-		return;
-
-	oh_name = "ocp2scp_usb_phy";
-	name	= "omap-ocp2scp";
-
-	oh = omap_hwmod_lookup(oh_name);
-	if (!oh) {
-		pr_err("%s: could not find omap_hwmod for %s\n", __func__,
-								oh_name);
-		return;
-	}
-
-	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-	if (!pdata) {
-		pr_err("%s: No memory for ocp2scp pdata\n", __func__);
-		return;
-	}
-
-	ocp2scp_dev = oh->dev_attr;
-	dev_cnt = count_ocp2scp_devices(ocp2scp_dev);
-
-	if (!dev_cnt) {
-		pr_err("%s: No devices connected to ocp2scp\n", __func__);
-		kfree(pdata);
-		return;
-	}
-
-	pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *)
-					* dev_cnt, GFP_KERNEL);
-	if (!pdata->devices) {
-		pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
-		kfree(pdata);
-		return;
-	}
-
-	for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
-		pdata->devices[i] = ocp2scp_dev;
-
-	pdata->dev_cnt	= dev_cnt;
-
-	pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
-	if (IS_ERR(pdev)) {
-		pr_err("Could not build omap_device for %s %s\n",
-						name, oh_name);
-		kfree(pdata->devices);
-		kfree(pdata);
-		return;
-	}
-}
-#else
-static inline void omap_init_ocp2scp(void) { }
-#endif
-
 /*-------------------------------------------------------------------------*/
 
 static int __init omap2_init_devices(void)
@@ -616,7 +539,6 @@ static int __init omap2_init_devices(void)
 	omap_init_sti();
 	omap_init_rng();
 	omap_init_vout();
-	omap_init_ocp2scp();
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index eaba9dc..8b60678 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
-#include <linux/platform_data/omap_ocp2scp.h>
 #include <linux/i2c-omap.h>
 
 #include <linux/omap-dma.h>
@@ -2695,25 +2694,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
 	.sysc	= &omap44xx_ocp2scp_sysc,
 };
 
-/* ocp2scp dev_attr */
-static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
-	{
-		.name		= "usb_phy",
-		.start		= 0x4a0ad080,
-		.end		= 0x4a0ae000,
-		.flags		= IORESOURCE_MEM,
-	},
-	{ }
-};
-
-static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
-	{
-		.drv_name       = "omap-usb2",
-		.res		= omap44xx_usb_phy_and_pll_addrs,
-	},
-	{ }
-};
-
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
 	.name		= "ocp2scp_usb_phy",
@@ -2737,7 +2717,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
 			.modulemode   = MODULEMODE_HWCTRL,
 		},
 	},
-	.dev_attr	= ocp2scp_dev_attr,
 };
 
 /*
diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
index fe71916..5511f98 100644
--- a/drivers/bus/omap-ocp2scp.c
+++ b/drivers/bus/omap-ocp2scp.c
@@ -22,26 +22,6 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
-#include <linux/platform_data/omap_ocp2scp.h>
-
-/**
- * _count_resources - count for the number of resources
- * @res: struct resource *
- *
- * Count and return the number of resources populated for the device that is
- * connected to ocp2scp.
- */
-static unsigned _count_resources(struct resource *res)
-{
-	int cnt	= 0;
-
-	while (res->start != res->end) {
-		cnt++;
-		res++;
-	}
-
-	return cnt;
-}
 
 static int ocp2scp_remove_devices(struct device *dev, void *c)
 {
@@ -55,11 +35,7 @@ static int ocp2scp_remove_devices(struct device *dev, void *c)
 static int omap_ocp2scp_probe(struct platform_device *pdev)
 {
 	int ret;
-	unsigned res_cnt, i;
 	struct device_node *np = pdev->dev.of_node;
-	struct platform_device *pdev_child;
-	struct omap_ocp2scp_platform_data *pdata = pdev->dev.platform_data;
-	struct omap_ocp2scp_dev *dev;
 
 	if (np) {
 		ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
@@ -68,48 +44,12 @@ static int omap_ocp2scp_probe(struct platform_device *pdev)
 			    "failed to add resources for ocp2scp child\n");
 			goto err0;
 		}
-	} else if (pdata) {
-		for (i = 0, dev = *pdata->devices; i < pdata->dev_cnt; i++,
-		    dev++) {
-			res_cnt = _count_resources(dev->res);
-
-			pdev_child = platform_device_alloc(dev->drv_name,
-			    PLATFORM_DEVID_AUTO);
-			if (!pdev_child) {
-				dev_err(&pdev->dev,
-				  "failed to allocate mem for ocp2scp child\n");
-				goto err0;
-			}
-
-			ret = platform_device_add_resources(pdev_child,
-			    dev->res, res_cnt);
-			if (ret) {
-				dev_err(&pdev->dev,
-				 "failed to add resources for ocp2scp child\n");
-				goto err1;
-			}
-
-			pdev_child->dev.parent	= &pdev->dev;
-
-			ret = platform_device_add(pdev_child);
-			if (ret) {
-				dev_err(&pdev->dev,
-				   "failed to register ocp2scp child device\n");
-				goto err1;
-			}
-		}
-	} else {
-		dev_err(&pdev->dev, "OCP2SCP initialized without plat data\n");
-		return -EINVAL;
 	}
 
 	pm_runtime_enable(&pdev->dev);
 
 	return 0;
 
-err1:
-	platform_device_put(pdev_child);
-
 err0:
 	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
 
diff --git a/include/linux/platform_data/omap_ocp2scp.h b/include/linux/platform_data/omap_ocp2scp.h
deleted file mode 100644
index 5c6c393..0000000
--- a/include/linux/platform_data/omap_ocp2scp.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * omap_ocp2scp.h -- ocp2scp header file
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Author: Kishon Vijay Abraham I <kishon at ti.com>
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __DRIVERS_OMAP_OCP2SCP_H
-#define __DRIVERS_OMAP_OCP2SCP_H
-
-struct omap_ocp2scp_dev {
-	const char			*drv_name;
-	struct resource			*res;
-};
-
-struct omap_ocp2scp_platform_data {
-	int				dev_cnt;
-	struct omap_ocp2scp_dev		**devices;
-};
-#endif /* __DRIVERS_OMAP_OCP2SCP_H */



From tony at atomide.com  Fri May 17 15:17:57 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:17:57 -0700
Subject: [PATCH 3/6] ARM: OMAP2+: Remove legacy mux data for omap4
In-Reply-To: <20130517191304.468.73487.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
Message-ID: <20130517191757.468.99664.stgit@localhost>

We can now boot with devicetree and muxing can be done
with pinctrl-single.c.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig   |    6 
 arch/arm/mach-omap2/Makefile  |    1 
 arch/arm/mach-omap2/mux.h     |    3 
 arch/arm/mach-omap2/mux44xx.c | 1356 -----------------------------------------
 arch/arm/mach-omap2/mux44xx.h |  298 ---------
 5 files changed, 1664 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/mux44xx.c
 delete mode 100644 arch/arm/mach-omap2/mux44xx.h

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1f941c4..6903d47 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -167,12 +167,6 @@ config OMAP_PACKAGE_CUS
 config OMAP_PACKAGE_CBP
        bool
 
-config OMAP_PACKAGE_CBL
-       bool
-
-config OMAP_PACKAGE_CBS
-       bool
-
 comment "OMAP Board Type"
 	depends on ARCH_OMAP2PLUS
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 2cbf3ef..13302a5 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -63,7 +63,6 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap3-restart.o
 obj-$(CONFIG_SOC_OMAP2420)		+= mux2420.o
 obj-$(CONFIG_SOC_OMAP2430)		+= mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)		+= mux34xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index fdb22f1..5d2080e 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,7 +10,6 @@
 #include "mux2420.h"
 #include "mux2430.h"
 #include "mux34xx.h"
-#include "mux44xx.h"
 
 #define OMAP_MUX_TERMINATOR	0xffff
 
@@ -64,8 +63,6 @@
 
 /* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK		0xffff
-#define OMAP_PACKAGE_CBS		8		/* 547-pin 0.40 0.40 */
-#define OMAP_PACKAGE_CBL		7		/* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBP		6		/* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CUS		5		/* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB		4		/* 515-pin 0.40 0.50 */
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
deleted file mode 100644
index f5a74da..0000000
--- a/arch/arm/mach-omap2/mux44xx.c
+++ /dev/null
@@ -1,1356 +0,0 @@
-/*
- * OMAP44xx ES1.0 pin mux definition
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson at ti.com)
- *
- * - Based on mux34xx.c done by Tony Lindgren <tony at atomide.com>
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap at vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "mux.h"
-
-#ifdef CONFIG_OMAP_MUX
-
-#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)	\
-{									\
-	.reg_offset	= (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),	\
-	.gpio		= (g),						\
-	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
-}
-
-#else
-
-#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)	\
-{									\
-	.reg_offset	= (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),	\
-	.gpio		= (g),						\
-}
-
-#endif
-
-#define _OMAP4_BALLENTRY(M0, bb, bt)				\
-{									\
-	.reg_offset	= (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),	\
-	.balls		= { bb, bt },					\
-}
-
-/*
- * Superset of all mux modes for omap4 ES1.0
- */
-static struct omap_mux __initdata omap4_core_muxmodes[] = {
-	_OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
-			"sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
-			"sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
-			"sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
-			"sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
-			"gpio_32", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
-			"gpio_33", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
-			"gpio_34", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
-			"gpio_35", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
-			"gpio_36", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
-			"gpio_37", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
-			"gpio_38", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
-			"gpio_39", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
-			"gpio_40", "venc_656_data0", NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
-			"gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
-			"gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
-			"gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
-			"gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
-			"gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
-			"gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
-			"gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
-			"gpio_48", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
-			"gpio_49", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
-			"sys_ndmareq0", NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
-			"gpio_51", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
-			"gpio_52", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
-			"c2c_dataout4", "gpio_53", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
-			"sys_ndmareq1", NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
-			"sys_ndmareq2", NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
-			"gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
-			"gpio_59", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
-			"gpio_60", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
-			"gpio_61", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
-			"gpio_62", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
-			"c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
-			"c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
-			"c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
-			"c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
-			"c2c_dataout1", "gpio_104", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
-			"gpio_65", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
-			"gpio_66", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
-			"gpio_83", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
-			"hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
-			NULL, "hw_dbg20", "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
-			"hsi1_cadata", "mcbsp4_clkr", "gpio_85",
-			"usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
-			"hsi1_caflag", "mcbsp4_fsr", "gpio_86",
-			"usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
-			"hsi1_acready", "mcbsp4_fsx", "gpio_87",
-			"usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
-			"hsi1_acwake", "mcbsp4_clkx", "gpio_88",
-			"usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
-			"hsi1_acdata", "mcbsp4_dx", "gpio_89",
-			"usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
-			"hsi1_acflag", "mcbsp4_dr", "gpio_90",
-			"usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
-			"hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
-			"usbb1_mm_txen", "hw_dbg27", "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
-			"dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
-			"usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
-			"dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
-			"usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
-			"dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
-			"usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
-			"dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
-			"usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
-			"gpio_96", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
-			NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
-			"gpio_98", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
-			"gpio_99", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
-			"gpio_100", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
-			"gpio_101", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
-			"gpio_102", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
-			"gpio_103", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
-			"gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
-			"gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
-			"gpio_106", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
-			"gpio_107", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
-			"gpio_108", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
-			"gpio_109", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
-			"abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
-			"abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
-			"abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
-			"abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
-			"abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
-			"abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
-			"abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
-			"abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
-			"abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
-			"abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
-			NULL, NULL, NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
-			NULL, NULL, NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
-			"gpio_119", "usbb2_mm_txse0", NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
-			"gpio_120", "usbb2_mm_txdat", NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
-			NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
-			"abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
-			"gpio_123", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
-			"gpio_124", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
-			"gpio_125", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
-			"gpio_126", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
-			"gpio_127", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	_OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	_OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
-			"gpio_128", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
-			"gpio_129", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
-			"gpio_135", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
-			"gpio_136", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
-			"gpio_138", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
-			"slimbus2_clock", "gpio_139", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
-			"slimbus2_data", "gpio_140", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
-			NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
-			"gpio_142", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
-			"dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
-			"dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
-			"usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
-			"usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
-			"usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
-			"usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
-			"gpio_149", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
-			"gpio_150", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
-			"gpio_151", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
-			"gpio_152", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
-			"gpio_153", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
-			"gpio_154", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
-			"gpio_155", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
-			"gpio_156", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
-			"usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
-			"hsi2_cawake", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
-			"usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
-			"hsi2_cadata", "dispc2_data23", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
-			"usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
-			"hsi2_caflag", "dispc2_data22", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
-			"usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
-			"hsi2_acready", "dispc2_data21", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
-			"usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
-			"hsi2_acwake", "dispc2_data20", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
-			"usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
-			"hsi2_acdata", "dispc2_data19", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
-			"usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
-			"hsi2_acflag", "dispc2_data18", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
-			"usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
-			"hsi2_caready", "dispc2_data15", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
-			"usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
-			"mcspi3_somi", "dispc2_data14", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
-			"usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
-			"mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
-			"usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
-			"mcspi3_simo", "dispc2_data12", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
-			"usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
-			"mcspi3_clk", "dispc2_data11", NULL, "reserved"),
-	_OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
-			"gpio_169", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
-			NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
-			"gpio_171", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
-			"gpio_172", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
-			"gpio_173", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
-			"gpio_174", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
-			"gpio_0", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
-			"gpio_1", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
-			"gpi_175", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
-			"gpi_176", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
-			"gpi_177", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
-			"gpi_178", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
-			"gpi_2", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
-			"gpi_3", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
-			"uart2_rx", "gpio_179", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
-			"uart2_tx", "gpio_180", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
-			"gpio_181", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
-			"gpio_182", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
-			NULL, "hw_dbg0", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
-			NULL, "hw_dbg1", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
-			"gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
-			"gpio_14", NULL, "dispc2_data10", "hw_dbg3",
-			"reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
-			"gpio_15", NULL, "dispc2_data9", "hw_dbg4",
-			"reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
-			"gpio_16", "rfbi_te_vsync0", "dispc2_data16",
-			"hw_dbg5", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
-			"uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
-			"dispc2_data17", "hw_dbg6", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
-			"uart3_rx_irrx", "gpio_18", "rfbi_cs0",
-			"dispc2_hsync", "hw_dbg7", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
-			"uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
-			"hw_dbg8", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
-			"uart3_cts_rctx", "gpio_20", "rfbi_we",
-			"dispc2_vsync", "hw_dbg9", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
-			NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
-			"reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
-			NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
-			"hw_dbg11", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
-			NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
-			"hw_dbg12", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
-			NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
-			"hw_dbg13", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
-			"uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
-			"hw_dbg14", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
-			NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
-			"hw_dbg15", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
-			"dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
-			"hw_dbg16", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
-			"dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
-			"hw_dbg17", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
-			"dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
-			"hw_dbg18", "reserved"),
-	_OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
-			"dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
-			"hw_dbg19", "reserved"),
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 44XX CBL package
- * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *				  0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)		\
-		&& defined(CONFIG_OMAP_PACKAGE_CBL)
-static struct omap_ball __initdata omap4_core_cbl_ball[] = {
-	_OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
-	_OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
-	_OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
-	_OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
-	_OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
-	_OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
-	_OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
-	_OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
-	_OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
-	_OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
-	_OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
-	_OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
-	_OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
-	_OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
-	_OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
-	_OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
-	_OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
-	_OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
-	_OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
-	_OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
-	_OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
-	_OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
-	_OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
-	_OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
-	_OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
-	_OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
-	_OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
-	_OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
-	_OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
-	_OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
-	_OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
-	_OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
-	_OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
-	_OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
-	_OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
-	_OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
-	_OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
-	_OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
-	_OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
-	_OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
-	_OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
-	_OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
-	_OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
-	_OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
-	_OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
-	_OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
-	_OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
-	_OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
-	_OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
-	_OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
-	_OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
-	_OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
-	_OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
-	_OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
-	_OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
-	_OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
-	_OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
-	_OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
-	_OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
-	_OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
-	_OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
-	_OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
-	_OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
-	_OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
-	_OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
-	_OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
-	_OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
-	_OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_core_cbl_ball  NULL
-#endif
-
-/*
- * Signals different on ES2.0 compared to superset
- */
-static struct omap_mux __initdata omap4_es2_core_subset[] = {
-	_OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
-			"gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
-			"gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
-			"gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
-			"gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
-			"gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
-			"gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
-			"gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
-			"gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
-			"gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
-			"gpio_48", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
-			"c2c_dataout7", "gpio_52", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
-			"sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
-			"gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
-	_OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
-			"c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
-			"gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
-			"gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
-			"c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
-			"c2c_dataout1", "gpio_104", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
-			"hsi1_acwake", "mcbsp4_clkx", "gpio_88",
-			"usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
-			"hsi1_acdata", "mcbsp4_dx", "gpio_89",
-			"usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
-			"hsi1_acflag", "mcbsp4_dr", "gpio_90",
-			"usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
-			"hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
-			"usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
-			"gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
-			"gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
-			"abe_mcasp_axr", "gpio_121", NULL,
-			"dmtimer11_pwm_evt", NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
-			"abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
-			"usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
-			"usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
-			"usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
-			"usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
-			"gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
-			"gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
-			"kpd_col6", "gpio_151", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
-			"kpd_col7", "gpio_152", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
-			"kpd_row6", "gpio_153", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
-			"kpd_row7", "gpio_154", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
-			"gpio_155", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
-			"gpio_156", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
-			"usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
-			"hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
-			"usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
-			"hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
-			"usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
-			"hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
-			"usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
-			"hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
-			"usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
-			"hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
-			"usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
-			"hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
-			"usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
-			"hsi2_caready", "dispc2_data15", "rfbi_data15",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
-			"usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
-			"mcspi3_somi", "dispc2_data14", "rfbi_data14",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
-			"usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
-			"mcspi3_cs0", "dispc2_data13", "rfbi_data13",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
-			"usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
-			"mcspi3_simo", "dispc2_data12", "rfbi_data12",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
-			"usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
-			"mcspi3_clk", "dispc2_data11", "rfbi_data11",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
-			"gpio_171", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
-			"gpio_172", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
-			"gpio_173", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
-			"gpio_174", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
-			"gpio_175", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
-			"gpio_176", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
-			"gpio_177", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
-			"gpio_178", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
-			"uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
-			"uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
-			"gpio_13", NULL, "dispc2_fid", "hw_dbg2",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
-			"gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
-			"gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
-			"gpio_16", "rfbi_te_vsync0", "dispc2_data16",
-			"hw_dbg5", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
-			"uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
-			"dispc2_data17", "hw_dbg6", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
-			"uart3_rx_irrx", "gpio_18", "rfbi_cs0",
-			"dispc2_hsync", "hw_dbg7", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
-			"uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
-			"hw_dbg8", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
-			"uart3_cts_rctx", "gpio_20", "rfbi_we",
-			"dispc2_vsync", "hw_dbg9", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
-			NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
-			"safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
-			NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
-			"hw_dbg11", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
-			NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
-			"hw_dbg12", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
-			NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
-			"hw_dbg13", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
-			"uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
-			"hw_dbg14", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
-			NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
-			"hw_dbg15", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
-			"dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
-			"hw_dbg16", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
-			"dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
-			"hw_dbg17", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
-			"dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
-			"hw_dbg18", "safe_mode"),
-	_OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
-			"dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
-			"hw_dbg19", "safe_mode"),
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 44XX CBS package
- * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *				  0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)		\
-		&& defined(CONFIG_OMAP_PACKAGE_CBS)
-static struct omap_ball __initdata omap4_core_cbs_ball[] = {
-	_OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
-	_OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
-	_OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
-	_OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
-	_OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
-	_OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
-	_OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
-	_OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
-	_OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
-	_OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
-	_OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
-	_OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
-	_OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
-	_OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
-	_OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
-	_OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
-	_OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
-	_OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
-	_OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
-	_OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
-	_OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
-	_OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
-	_OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
-	_OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
-	_OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
-	_OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
-	_OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
-	_OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
-	_OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
-	_OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
-	_OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
-	_OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
-	_OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
-	_OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
-	_OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
-	_OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
-	_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
-	_OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
-	_OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
-	_OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
-	_OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
-	_OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
-	_OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
-	_OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
-	_OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
-	_OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
-	_OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
-	_OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
-	_OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
-	_OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
-	_OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
-	_OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
-	_OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
-	_OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
-	_OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
-	_OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
-	_OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
-	_OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
-	_OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
-	_OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
-	_OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
-	_OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
-	_OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
-	_OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
-	_OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
-	_OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
-	_OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
-	_OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
-	_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
-	_OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
-	_OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
-	_OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
-	_OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
-	_OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
-	_OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
-	_OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
-	_OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
-	_OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
-	_OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
-	_OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
-	_OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
-	_OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
-	_OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
-	_OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
-	_OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
-	_OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
-	_OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
-	_OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
-	_OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_core_cbs_ball  NULL
-#endif
-
-/*
- * Superset of all mux modes for omap4
- */
-static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
-	_OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	_OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	_OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
-			"c2c_wakereqin", NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
-			"gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
-			"sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
-			"sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
-			"sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
-			NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
-			NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
-			"gpio_wk8", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	_OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
-			NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
-			NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
-			NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
-			"gpio_wk9", "c2c_wakereqout", NULL, NULL,
-			"safe_mode"),
-	_OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
-			"gpio_wk10", NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
-			NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
-			NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
-			NULL, NULL, NULL),
-	_OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
-			NULL, NULL, NULL, "safe_mode"),
-	_OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	_OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
-			NULL, NULL),
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 44XX CBL & CBS package - wakeup partition
- * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *				  0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)		\
-		&& defined(CONFIG_OMAP_PACKAGE_CBL)
-static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
-	_OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
-	_OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
-	_OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
-	_OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
-	_OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
-	_OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
-	_OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
-	_OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
-	_OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
-	_OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
-	_OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
-	_OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
-	_OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
-	_OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
-	_OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
-	_OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
-	_OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
-	_OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
-	_OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
-	_OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
-	_OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
-	_OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
-	{ .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_wkup_cbl_cbs_ball  NULL
-#endif
-
-int __init omap4_mux_init(struct omap_board_mux *board_subset,
-	struct omap_board_mux *board_wkup_subset, int flags)
-{
-	struct omap_ball *package_balls_core;
-	struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
-	struct omap_mux *core_muxmodes;
-	struct omap_mux *core_subset = NULL;
-	int ret;
-
-	switch (flags & OMAP_PACKAGE_MASK) {
-	case OMAP_PACKAGE_CBL:
-		pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
-		package_balls_core = omap4_core_cbl_ball;
-		core_muxmodes = omap4_core_muxmodes;
-		break;
-	case OMAP_PACKAGE_CBS:
-		pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
-		package_balls_core = omap4_core_cbs_ball;
-		core_muxmodes = omap4_core_muxmodes;
-		core_subset = omap4_es2_core_subset;
-		break;
-	default:
-		pr_err("%s: Unknown omap package, mux disabled\n", __func__);
-		return -EINVAL;
-	}
-
-	ret = omap_mux_init("core",
-			    OMAP_MUX_GPIO_IN_MODE3,
-			    OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
-			    OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
-			    core_muxmodes, core_subset, board_subset,
-			    package_balls_core);
-	if (ret)
-		return ret;
-
-	ret = omap_mux_init("wkup",
-			    OMAP_MUX_GPIO_IN_MODE3,
-			    OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
-			    OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
-			    omap4_wkup_muxmodes, NULL, board_wkup_subset,
-			    package_balls_wkup);
-
-	return ret;
-}
-
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
deleted file mode 100644
index c635026..0000000
--- a/arch/arm/mach-omap2/mux44xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * OMAP44xx MUX registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson at ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap at vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
-
-#define OMAP4_MUX(M0, mux_value)					\
-{									\
-	.reg_offset	= (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),	\
-	.value		= (mux_value),					\
-}
-
-/* ctrl_module_pad_core base address */
-#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE			0x4a100000
-
-/* ctrl_module_pad_core registers offset */
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET			0x0040
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET			0x0042
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET			0x0044
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET			0x0046
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET			0x0048
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET			0x004a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET			0x004c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET			0x004e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET			0x0050
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET			0x0052
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET			0x0054
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET			0x0056
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET			0x0058
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET			0x005a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET			0x005c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET			0x005e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET			0x0060
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET			0x0062
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET			0x0064
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET			0x0066
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET			0x0068
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET			0x006a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET			0x006c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET			0x006e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET			0x0070
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET			0x0072
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET			0x0074
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET			0x0076
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET			0x0078
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET			0x007a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET			0x007c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET			0x007e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET		0x0080
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET			0x0082
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET			0x0084
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET		0x0086
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET			0x0088
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET			0x008a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET			0x008c
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET			0x008e
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET			0x0090
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET			0x0092
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET			0x0094
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET			0x0096
-#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET			0x0098
-#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET			0x009a
-#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET		0x009c
-#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET		0x009e
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET			0x00a0
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET			0x00a2
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET			0x00a4
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET			0x00a6
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET			0x00a8
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET			0x00aa
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET			0x00ac
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET			0x00ae
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET			0x00b0
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET			0x00b2
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET			0x00b4
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET			0x00b6
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET			0x00b8
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET			0x00ba
-#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET		0x00bc
-#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET			0x00be
-#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET		0x00c0
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET		0x00c2
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET		0x00c4
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET		0x00c6
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET		0x00c8
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET		0x00ca
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET		0x00cc
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET		0x00ce
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET		0x00d0
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET		0x00d2
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET		0x00d4
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET		0x00d6
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET		0x00d8
-#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET		0x00da
-#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET		0x00dc
-#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET		0x00de
-#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET		0x00e0
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET			0x00e2
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET			0x00e4
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET		0x00e6
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET		0x00e8
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET		0x00ea
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET		0x00ec
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET		0x00ee
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET		0x00f0
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET		0x00f2
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET		0x00f4
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET		0x00f6
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET		0x00f8
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET		0x00fa
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET		0x00fc
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET		0x00fe
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET		0x0100
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET		0x0102
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET		0x0104
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET		0x0106
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET		0x0108
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET		0x010a
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET		0x010c
-#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET			0x010e
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET		0x0110
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET		0x0112
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET		0x0114
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET		0x0116
-#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET			0x0118
-#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET			0x011a
-#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET			0x011c
-#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET			0x011e
-#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET			0x0120
-#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET			0x0122
-#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET			0x0124
-#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET			0x0126
-#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET			0x0128
-#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET			0x012a
-#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET			0x012c
-#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET			0x012e
-#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET			0x0130
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET			0x0132
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET		0x0134
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET		0x0136
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET			0x0138
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET			0x013a
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET			0x013c
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET			0x013e
-#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET		0x0140
-#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET		0x0142
-#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET		0x0144
-#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET		0x0146
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET			0x0148
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET			0x014a
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET		0x014c
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET		0x014e
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET		0x0150
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET		0x0152
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET			0x0154
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET		0x0156
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET		0x0158
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET			0x015a
-#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET			0x015c
-#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET			0x015e
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET		0x0160
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET		0x0162
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET		0x0164
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET		0x0166
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET		0x0168
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET		0x016a
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET		0x016c
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET		0x016e
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET		0x0170
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET		0x0172
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET		0x0174
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET		0x0176
-#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET		0x0178
-#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET		0x017a
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET			0x017c
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET			0x017e
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET			0x0180
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET			0x0182
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET			0x0184
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET			0x0186
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET			0x0188
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET			0x018a
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET			0x018c
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET			0x018e
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET			0x0190
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET			0x0192
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET		0x0194
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET		0x0196
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET		0x0198
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET		0x019a
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET		0x019c
-#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET			0x019e
-#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET			0x01a0
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET			0x01a2
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET			0x01a4
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET			0x01a6
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET			0x01a8
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET			0x01aa
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET			0x01ac
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET			0x01ae
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET			0x01b0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET			0x01b2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET			0x01b4
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET			0x01b6
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET			0x01b8
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET			0x01ba
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET			0x01bc
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET			0x01be
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET			0x01c0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET			0x01c2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET			0x01c4
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET			0x01c6
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET			0x01c8
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET			0x01ca
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET			0x01cc
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET			0x01ce
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET			0x01d0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET			0x01d2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET			0x01d4
-
-/* ES2.0 only */
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET			0x008e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET			0x0090
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET			0x0092
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET			0x0094
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET			0x0096
-
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET			0x017c
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET			0x017e
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET			0x0180
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET			0x0182
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET			0x0184
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET			0x0186
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET			0x0188
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET			0x018a
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET			0x018c
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET			0x018e
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET			0x0190
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET			0x0192
-
-
-#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE			\
-		(OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET		\
-		 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
-
-/* ctrl_module_pad_wkup base address */
-#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE			0x4a31e000
-
-/* ctrl_module_pad_wkup registers offset */
-#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET			0x0040
-#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET			0x0042
-#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET			0x0044
-#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET			0x0046
-#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET		0x0048
-#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET			0x004a
-#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET			0x004c
-#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET		0x004e
-#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET		0x0050
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET		0x0052
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET		0x0054
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET		0x0056
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET		0x0058
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET		0x005a
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET		0x005c
-#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET			0x005e
-#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET		0x0060
-#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET		0x0062
-#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET		0x0064
-#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET	0x0066
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET			0x0068
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET			0x006a
-#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET			0x006c
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET			0x006e
-#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET			0x0070
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET		0x0072
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET			0x0074
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET			0x0076
-
-#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE			\
-		(OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET		\
-		 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
-
-#endif



From dianders at chromium.org  Fri May 17 15:22:36 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 12:22:36 -0700
Subject: [PATCH 2/6] ARM: EXYNOS: Fix EINT wake-up mask configuration when
 pinctrl is used
In-Reply-To: <1368807872-2601-3-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-3-git-send-email-t.figa@samsung.com>
Message-ID: <CAD=FV=UUzB=FwHfzTwRMDDGn3+FkuZPbXG9QL_h07qZgRMkZrw@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> On DT-enabled systems pinctrl-exynos driver is responsible for handling
> of wake-up EINT interrupts. This patch adjusts wake-up mask
> configuration code to take wake-up mask value from pinctrl-exynos driver
> on DT-enabled systems.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)

A little ugly because of the need to support old non-device tree
boards, but seems reasonable.  Means that if you have a device tree
you'd better be using pincontrol.  Assuming that's true now someone
needs to go through and remove all of the device tree support (and
bindings Documentation) for gpio-samsung.  Maybe someone has already
started?


On exynos5250-snow (pinmux backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> On DT-enabled systems pinctrl-exynos driver is responsible for handling
> of wake-up EINT interrupts. This patch adjusts wake-up mask
> configuration code to take wake-up mask value from pinctrl-exynos driver
> on DT-enabled systems.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
> index 7dbbfec..296090e 100644
> --- a/arch/arm/mach-exynos/include/mach/pm-core.h
> +++ b/arch/arm/mach-exynos/include/mach/pm-core.h
> @@ -18,8 +18,15 @@
>  #ifndef __ASM_ARCH_PM_CORE_H
>  #define __ASM_ARCH_PM_CORE_H __FILE__
>
> +#include <linux/of.h>
>  #include <mach/regs-pmu.h>
>
> +#ifdef CONFIG_PINCTRL_EXYNOS
> +extern u32 exynos_get_eint_wake_mask(void);
> +#else
> +static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
> +#endif
> +
>  static inline void s3c_pm_debug_init_uart(void)
>  {
>         /* nothing here yet */
> @@ -27,7 +34,12 @@ static inline void s3c_pm_debug_init_uart(void)
>
>  static inline void s3c_pm_arch_prepare_irqs(void)
>  {
> -       __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
> +       u32 eintmask = s3c_irqwake_eintmask;
> +
> +       if (of_have_populated_dt())
> +               eintmask = exynos_get_eint_wake_mask();
> +
> +       __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
>         __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
>  }
>
> --
> 1.8.2.1
>


From robherring2 at gmail.com  Fri May 17 15:23:34 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 17 May 2013 14:23:34 -0500
Subject: ux500 breaking multi-platform kernels
In-Reply-To: <CACRpkdbJosO7Ea8=BUdgVSf5fZwddWZb79ONaz3r+DqseAaF7Q@mail.gmail.com>
References: <CAL_JsqJzf8Aj6+K_qEYo3JbAoeJn36EerBfaGYT9EQj-zPaHUw@mail.gmail.com>
 <CACRpkdbJosO7Ea8=BUdgVSf5fZwddWZb79ONaz3r+DqseAaF7Q@mail.gmail.com>
Message-ID: <CAL_JsqLRXh9AW9fPy9YkAufzY5cV8=FmRU_O346EQixb=YAW3Q@mail.gmail.com>

On Fri, May 17, 2013 at 1:29 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, May 15, 2013 at 10:30 PM, Rob Herring <robherring2 at gmail.com> wrote:
>
>> There are some initcalls on ux500 that are not properly
>> conditionalized.
>
> Oh wow you actually compiled it in and tried to boot it on something
> else :-D
>
> Highbank I suppose?
>
>> The first is in ux500_l2x0_init and here is a fix:
>
> I guess this is all -rc material. Can you send a proper patch (set)?

It is. I don't really think this is the ideal fix. It would be better
if you could make this not be an unconditional initcall.

Rob


From dianders at chromium.org  Fri May 17 15:24:04 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 12:24:04 -0700
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <1368807872-2601-4-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-4-git-send-email-t.figa@samsung.com>
Message-ID: <CAD=FV=XJ=_o+hVbD=pPqXxXo=1PZdeRWyn-xyfS+Jf5LYfe2dg@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> This patch makes legacy code on suspend/resume path being executed
> conditionally, on non-DT platforms only, to fix suspend/resume of
> DT-enabled systems, for which the code is inappropriate.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/plat-samsung/pm.c | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
> index 53210ec..8ac2b2d 100644
> --- a/arch/arm/plat-samsung/pm.c
> +++ b/arch/arm/plat-samsung/pm.c
> @@ -261,7 +261,8 @@ static int s3c_pm_enter(suspend_state_t state)
>          * require a full power-cycle)
>         */
>
> -       if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
> +       if (!of_have_populated_dt() &&
> +           !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&

I'd rather see you modify patch set #2 to provide some function to
retrieve just the eint mask and then use it here.  Your patch removes
this test and doesn't replace it with anything.  If you moved this
test to pinctrl directly you'd lose the test against intallow.

...or do you think this test is no longer useful for some reason?


>             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
>                 printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
>                 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
> @@ -270,8 +271,11 @@ static int s3c_pm_enter(suspend_state_t state)
>
>         /* save all necessary core registers not covered by the drivers */
>
> -       samsung_pm_save_gpios();
> -       samsung_pm_saved_gpios();
> +       if (!of_have_populated_dt()) {
> +               samsung_pm_save_gpios();
> +               samsung_pm_saved_gpios();
> +       }
> +

Ah, the important part here is the "saved", not the "save"!  The
"save" should get a NULL chip for all GPIOs and effectively be a
no-op.

Skipping the "saved" is important of s3c64xx and s5p64x0 where the
"saved" seems to transition things over to powerdown mode.  Hopefully
a future patch of yours adds that back for those platforms in the
pinmux world.  ...same for restore.


Summary: I've tested this on exynos5250-snow and it's reasonable but
I'd love a response about the missing test before adding Reviewed-by.

-Doug


From dianders at chromium.org  Fri May 17 15:24:29 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 12:24:29 -0700
Subject: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific
 suspend/resume callbacks
In-Reply-To: <1368807872-2601-5-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-5-git-send-email-t.figa@samsung.com>
Message-ID: <CAD=FV=Xy2Poti6Wz594DpN1ZbB3FQJ1Dkt+PND1Z0fqf2pJvaw@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> +       if (ctrl->resume)
> +               ctrl->resume(drvdata);
> +

Having this resume at the beginning of the function seems right for
restoring eint settings like you do in patch #6.

...but if you need to try to handle the old s3c64xx and s5p64x0
concept of "restored" to actually take GPIOs out of powerdown mode
then you'll also need a callback at the end.

Does it make sense to add a second callback at the end of this function?


...since it's unclear how we'll handle s3c64xx/s5p64x0 (or even if I'm
misunderstanding and they're already handled somehow), I don't see any
problems with this patch, so...


On exynos5250-snow (pinmux backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>


From dianders at chromium.org  Fri May 17 15:24:41 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 12:24:41 -0700
Subject: [PATCH 5/6] pinctrl: samsung: Allow per-bank SoC-specific private
 data
In-Reply-To: <1368807872-2601-6-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-6-git-send-email-t.figa@samsung.com>
Message-ID: <CAD=FV=VPoBEQ6fGscPYBnVyThKbMdOgXznrMoA97HHaTp0coGA@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> This patch extends pin bank descriptor structure with SoC-specific
> private data field that allows SoC-specific drivers to store their own
> private data.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/pinctrl/pinctrl-samsung.h | 1 +
>  1 file changed, 1 insertion(+)

Sure.  Seems like it could be squashed into the next patch, but I
think it looks fine separate too.

On exynos5250-snow (pinmux backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>


From dianders at chromium.org  Fri May 17 15:25:02 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 12:25:02 -0700
Subject: [PATCH 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <1368807872-2601-7-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-7-git-send-email-t.figa@samsung.com>
Message-ID: <CAD=FV=WKCeW=3BFnmnyXB70VCjXHGrzarXbj8cBfq4-ENA-Y2w@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> Some GPIO EINT control registers needs to be preserved across
> suspend/resume cycle. This patch extends the driver to take care of
> this.

I was confused why we didn't seem to need this on exynos5250-snow but
figured it out.  We only use interrupts on GPX lines which don't need
this code.  ...but on any exynos5250 boards that use one of the other
banks for interrupts you'd need it.  I tested by setting one of the
registers related to GPA0 and found that this code is indeed needed on
exynos5250.  :)

Just nits / optional comments below, so on exynos5250-snow (pinmux
backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>


> @@ -229,6 +235,11 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
>                         dev_err(dev, "gpio irq domain add failed\n");
>                         return -ENXIO;
>                 }
> +
> +               bank->soc_priv = devm_kzalloc(d->dev,
> +                       sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
> +               if (!bank->soc_priv)
> +                       return -ENOMEM;

Slight nit to add this before the call to irq_domain_add_linear().
demv() will handle freeing your memory but nothing will handle undoing
the irq_domain_add_linear() if you return an error.

>         }
>
>         return 0;
> @@ -528,6 +539,58 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
>         return 0;
>  }
>
> +static void exynos_pinctrl_suspend_bank(
> +                               struct samsung_pinctrl_drv_data *drvdata,
> +                               struct samsung_pin_bank *bank)
> +{
> +       struct exynos_eint_gpio_save *save = bank->soc_priv;
> +       void __iomem *regs = drvdata->virt_base;
> +
> +       save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
> +                                               + bank->eint_offset);
> +       save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> +                                               + 2 * bank->eint_offset);
> +       save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> +                                               + 2 * bank->eint_offset + 4);

Optional: I wish there were debug statements to help debug, like:

pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);


> +}
> +
> +static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> +{
> +       struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
> +       struct samsung_pin_bank *bank = ctrl->pin_banks;
> +       int i;
> +
> +       for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
> +               if (bank->eint_type == EINT_TYPE_GPIO)
> +                       exynos_pinctrl_suspend_bank(drvdata, bank);
> +}
> +
> +static void exynos_pinctrl_resume_bank(
> +                               struct samsung_pinctrl_drv_data *drvdata,
> +                               struct samsung_pin_bank *bank)
> +{
> +       struct exynos_eint_gpio_save *save = bank->soc_priv;
> +       void __iomem *regs = drvdata->virt_base;
> +

Optional: debug statements:

pr_debug("%s:     con %#010x => %#010x\n", bank->name,
  readl(regs + EXYNOS_GPIO_ECON_OFFSET + bank->eint_offset),
  save->eint_con);
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
  readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset),
  save->eint_fltcon0);
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
  readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4),
  save->eint_fltcon1);

-Doug


From tony at atomide.com  Fri May 17 15:25:16 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 12:25:16 -0700
Subject: [GIT PULL] omap fixes for v3.10-rc1
Message-ID: <20130517192515.GC5600@atomide.com>

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10-rc1/fixes

for you to fetch changes up to a6d25f4c951b8b28f2eaec6f891ff834622532f2:

  ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock (2013-05-17 10:07:45 -0700)

----------------------------------------------------------------
Fixes for omaps:

- a section mismatch fix for hwmod
- boot fix for omap2plus_defconfig for omap2
- musb interrupt fix when using device tree
- am33xx clock fix that I missed earlier somehow
- omap1 dma return code error fix

----------------------------------------------------------------
Paul Walmsley (1):
      ARM: OMAP2+: Add missing CONFIG_ARCH_MULTI_V6=y to omap2plus_defconfig

Tony Lindgren (1):
      ARM: dts: Fix musb interrupt for device tree booting

Vaibhav Hiremath (1):
      ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock

Wei Yongjun (1):
      ARM: OMAP: fix error return code in omap1_system_dma_init()

jean-philippe francois (1):
      ARM: OMAP: fix __init section mismatch for _enable_preprogram

 arch/arm/boot/dts/omap3.dtsi          |  2 +-
 arch/arm/configs/omap2plus_defconfig  |  1 +
 arch/arm/mach-omap1/dma.c             |  1 +
 arch/arm/mach-omap2/cclock33xx_data.c | 26 +++++++++++++++++++++++---
 arch/arm/mach-omap2/omap_hwmod.c      |  2 +-
 5 files changed, 27 insertions(+), 5 deletions(-)


From robherring2 at gmail.com  Fri May 17 15:36:28 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 17 May 2013 14:36:28 -0500
Subject: spurious bL cpufreq driver messages
Message-ID: <519686BC.3090101@gmail.com>

The bL cpufreq driver appears to collide with the cpufreq-cpu0 driver.
There doesn't appear to be a functional problem, but just spurious
prints which indicate it is trying to do something. I think it needs
better checking whether the chip is actually multi-cluster. This is what
I get when I hotplug cpus:

[  909.372319] CPU1: Booted secondary processor
[  909.372616] cpu cpu1: get_cluster_clk_and_freq_table: init_opp_table
failed, cpu: 1, err: -61
[  909.385411] cpu cpu1: get_cluster_clk_and_freq_table: Failed to get
data for cluster: 9
[  909.394161] CPU2: shutdown
[  909.400957] CPU2: Booted secondary processor
[  909.401253] cpu cpu2: get_cluster_clk_and_freq_table: init_opp_table
failed, cpu: 2, err: -61
[  909.414044] cpu cpu2: get_cluster_clk_and_freq_table: Failed to get
data for cluster: 9

Rob


From swarren at wwwdotorg.org  Fri May 17 15:39:00 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 13:39:00 -0600
Subject: Naming convention DSI + device tree
In-Reply-To: <5195C1E2.4020009@nvidia.com>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org> <20130516071537.GA13573@mail.o2s.ch>
 <519522C1.5010107@wwwdotorg.org> <5195C1E2.4020009@nvidia.com>
Message-ID: <51968754.6050509@wwwdotorg.org>

On 05/16/2013 11:36 PM, Alex Courbot wrote:
...
> I checked whether the rebase worked and it does - you just need to
> enable host1x/tegradrm support on top of the default settings (Stephen,
> why aren't these enabled by default?)

I guess it just got overlooked. I see CONFIG_DRM is on though; perhaps
the default for the Tegra DRM driver changed in Kconfig. Feel free to
send a patch to tegra_defconfig.


From swarren at wwwdotorg.org  Fri May 17 15:48:36 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 13:48:36 -0600
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
Message-ID: <51968994.5030408@wwwdotorg.org>

On 05/17/2013 10:51 AM, Jay Agarwal wrote:
>>> On 05/08/2013 04:57 AM, Jay Agarwal wrote:
>>>> - Enable PCIe controller on Cardhu
>>>> - Only port 2 is connected on this board
>>>> - Add regulators required for Tegra30
>>>> - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
>>>> - and should be applied on top of this.
...
>>> So, if I apply this series, I do see the PCIe bridge and Ethernet
>>> device get enumerated, but I don't see the USB3 controller get
>>> enumerated. I believe that is a PCIe device behind the same bridge on the
>>> same Tegra PCIe port.
>>> Shouldn't this device show up?
>>
>> I have also reproduced this problem. I see somehow no non-
>> prefetchable memory is assigned to any of pcie devices.
>> Probably that is the reason for USB3 (pci 0000:04:00.0) not getting
>> enumerated since it uses only non-prefetchable memory.
> 
> 1. Bus4(on which usb3 device resides) always return 0xffffffff from it's config space. which means device is not present?
> 2. That's why it is not assigned any resources and hence no usb3 probe happens.
> 3. But same bus does return valid info like vendor/device id etc from it's config space in downstream kernel and hence usb3 probe does happen.
> 
> Thierry, Stephen,
> 4. Any idea why bus4 should return 0xffffffff values in upstream kernel? Anything missing?

Is there some reset/enable GPIO or regulator that needs to be programmed
to enable the PCIe USB3 controller? Take a look at the schematic. If you
can make it work by tweaking those GPIOs/... manually, then we can
ignore this issue and fix it up later, since it's not directly related
to the PCIe controller driver patches. It's more important to get this
Ethernet working than USB, I think.

> 5. Also, how config space of all pcie devices are mapped? I mean if I change the config space offset in dts file, then also I find correct vendor/device id etc for bus0/device0/fun0.
>     So how this mapping happens that even after changing the config space offset in PCIe address space, it always finds correct vendor/device id.

Can you please word-wrap your email less than 80 columns? It's quite
hard to read.

I don't quite understand your question. The PCIe driver implements the
functions that access config space. I don't recall that being influenced
by anything much in the device tree, except for the 3rd entry in the
top-level PCIe controller's reg property:

        pcie-controller {
                compatible = "nvidia,tegra30-pcie";
                device_type = "pci";
                reg = <0x00003000 0x00000800   /* PADS registers */
                       0x00003800 0x00000200   /* AFI registers */
                       0x10000000 0x10000000>; /* configuration space */



From tomasz.figa at gmail.com  Fri May 17 15:49:13 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 May 2013 21:49:13 +0200
Subject: [PATCH 2/6] ARM: EXYNOS: Fix EINT wake-up mask configuration when
 pinctrl is used
In-Reply-To: <CAD=FV=UUzB=FwHfzTwRMDDGn3+FkuZPbXG9QL_h07qZgRMkZrw@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-3-git-send-email-t.figa@samsung.com>
 <CAD=FV=UUzB=FwHfzTwRMDDGn3+FkuZPbXG9QL_h07qZgRMkZrw@mail.gmail.com>
Message-ID: <13970900.6bfa7bMWJL@flatron>

Hi Doug,

On Friday 17 of May 2013 12:22:36 Doug Anderson wrote:
> Tomasz,
> 
> On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> > On DT-enabled systems pinctrl-exynos driver is responsible for
> > handling
> > of wake-up EINT interrupts. This patch adjusts wake-up mask
> > configuration code to take wake-up mask value from pinctrl-exynos
> > driver on DT-enabled systems.
> > 
> > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> > 
> >  arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++-
> >  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> A little ugly

Hehe. I thought exactly the same, but I don't see any better solution at 
the moment, except persuading the whole suspend/resume support in plat-
samsung to be a friend of multiplatform, which will have to be done 
eventually, but at the moment I don't have time to work on it.

> because of the need to support old non-device tree
> boards, but seems reasonable.  Means that if you have a device tree
> you'd better be using pincontrol.  Assuming that's true now someone
> needs to go through and remove all of the device tree support (and
> bindings Documentation) for gpio-samsung.  Maybe someone has already
> started?

If I remember correctly Sylwester Nawrocki had some patches to remove 
that. He's on a leave right now, so he won't send them for a while, but I 
guess it's nothing urgent.

> On exynos5250-snow (pinmux backported to 3.8):
> 
> Tested-by: Doug Anderson <dianders at chromium.org>
> 
> Reviewed-by: Doug Anderson <dianders at chromium.org>

Thanks.

Best regards,
Tomasz

> On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> > On DT-enabled systems pinctrl-exynos driver is responsible for
> > handling
> > of wake-up EINT interrupts. This patch adjusts wake-up mask
> > configuration code to take wake-up mask value from pinctrl-exynos
> > driver on DT-enabled systems.
> > 
> > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> > 
> >  arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++-
> >  1 file changed, 13 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h
> > b/arch/arm/mach-exynos/include/mach/pm-core.h index 7dbbfec..296090e
> > 100644
> > --- a/arch/arm/mach-exynos/include/mach/pm-core.h
> > +++ b/arch/arm/mach-exynos/include/mach/pm-core.h
> > @@ -18,8 +18,15 @@
> > 
> >  #ifndef __ASM_ARCH_PM_CORE_H
> >  #define __ASM_ARCH_PM_CORE_H __FILE__
> > 
> > +#include <linux/of.h>
> > 
> >  #include <mach/regs-pmu.h>
> > 
> > +#ifdef CONFIG_PINCTRL_EXYNOS
> > +extern u32 exynos_get_eint_wake_mask(void);
> > +#else
> > +static inline u32 exynos_get_eint_wake_mask(void) { return
> > 0xffffffff; } +#endif
> > +
> > 
> >  static inline void s3c_pm_debug_init_uart(void)
> >  {
> >  
> >         /* nothing here yet */
> > 
> > @@ -27,7 +34,12 @@ static inline void s3c_pm_debug_init_uart(void)
> > 
> >  static inline void s3c_pm_arch_prepare_irqs(void)
> >  {
> > 
> > -       __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
> > +       u32 eintmask = s3c_irqwake_eintmask;
> > +
> > +       if (of_have_populated_dt())
> > +               eintmask = exynos_get_eint_wake_mask();
> > +
> > +       __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
> > 
> >         __raw_writel(s3c_irqwake_intmask & ~(1 << 31),
> >         S5P_WAKEUP_MASK);
> >  
> >  }
> > 
> > --
> > 1.8.2.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe
> linux-samsung-soc" in the body of a message to
> majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From balbi at ti.com  Fri May 17 16:05:31 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 17 May 2013 23:05:31 +0300
Subject: [PATCH 6/6] ARM: OMAP2+: Remove omap4 ocp2scp pdata
In-Reply-To: <20130517191803.468.32800.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
 <20130517191803.468.32800.stgit@localhost>
Message-ID: <20130517200531.GA17851@arwen.pp.htv.fi>

On Fri, May 17, 2013 at 12:18:03PM -0700, Tony Lindgren wrote:
> This is omap4+ only and no longer needed as omap4+ can be booted
> using device tree.
> 
> Also remove the related pdata handling from the driver and the
> now unneeded platform_data/omap_ocp2scp.h.
> 
> Cc: Kishon Vijay Abraham I <kishon at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Olof Johansson <olof at lixom.net>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

fine by me :-)

Acked-by: Felipe Balbi <balbi at ti.com>

-- 
balbi
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From andreas.herrmann at calxeda.com  Fri May 17 16:16:39 2013
From: andreas.herrmann at calxeda.com (Andreas Herrmann)
Date: Fri, 17 May 2013 22:16:39 +0200
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130513104147.GF10369@alberich>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
 <20130513095846.GC29814@mudshark.cambridge.arm.com>
 <20130513104147.GF10369@alberich>
Message-ID: <20130517201639.GL10369@alberich>

On Mon, May 13, 2013 at 12:41:47PM +0200, Andreas Herrmann wrote:
> On Mon, May 13, 2013 at 05:58:46AM -0400, Will Deacon wrote:
> > On Mon, May 13, 2013 at 10:50:20AM +0100, Andreas Herrmann wrote:

[snip]

> > > I also think that it is more useful to move the stream-id property to
> > > the device node of a master device. (It's a characteristic of the
> > > master device not of the SMMU.) Currently with multiple stream IDs per
> > > master device you have repeated entries in the mmu-master property.
> > 
> > The problem with that approach is how to handle StreamID remastering. This
> > can and will happen, so the StreamID for a device is actually a property of
> > both the device *and* a particular point in the bus topology. Putting this
> > information in the device nodes will drag topology information all over the
> > place and I don't think it will make things clearer to read or easier to parse.
> 
> Ok, good point, didn't think about that.
> And agreed, adding remastered StreamIDs as a property to a device node is odd.
> 
> > > But all that is needed is to point (once) to each mmu-master in the
> > > SMMU device node. Then you should be able to look up the corresponding
> > > stream IDs in the device node for each mmu-master.
> > 
> > Again, you also need to tie in topology information if you go down this
> > route.

I still don't like the approach of having two independend lists that
must be in sync to associate a master with its stream-ids.

Why? Say you have 8 masters for an SMMU with 1 or 2 stream-ids each:

     	 smmu {
		...
                mmu-masters = <&dma0>, <&dma0>, <&dma1>, <&dma1>,
			      <&dma2>, <&dma2>, <&dma4>, <&dma4>,
			      <&dma5>, <&dma6>, <&dma7>, <&dma8>;
                stream-ids =	<0>, <1>, <2>, <3>,
				<4>, <5>, <6>, <7>,
		                <8>, <9>, <0xa>, <0xb>;
	}

Couldn't we use of_phandle_args for this purpose? So your example

+        smmu {
		 ...
+                mmu-masters = <&dma0>,
+                              <&dma0>,
+                              <&dma1>;
+                stream-ids  = <0xd01d>,
+                              <0xd01e>,
+                              <0xd11c>;
+        };

would look like

	dma0 {
		...
		#stream-id-cells = <2>
		...
	}

	dma1 {
		...
		#stream-id-cells = <1>
		...
	}

        smmu {
		...
		mmu-masters = <&dma0 0xd01d 0xd01e
			       &dma1 0xd11c>,
       };

and my example would be converted to

	smmu {
		...
                mmu-masters = <&dma0 0 1 &dma1 2 3 &dma2 4 5
			       &dma4 6 7 &dma5 8 &dma6 9
			       &dma7 0xa &dma8 0xb>
		...
	}

where each master has #stream-id-cells property with value 1 or 2.
And if dma4 has #stream-id-cells = <1>, the parsing code quickly
notifies us about an error whereas such an error can't be noticed
right from the beginning with the two-list-approach. In this example
stream-id 6 belongs to dma3 which was completely ommitted in both
descriptions.

Of course usage of of_phandle_args would restrict the number of
stream-ids per master to 8 (which is currently used as
MAX_PHANDLE_ARGS). But I don't think that this is a restriction in
practice or do you expect to have more than 8 stream-ids per master
(ie. per struct device in Linux)?


Andreas


From tomasz.figa at gmail.com  Fri May 17 16:23:07 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 May 2013 22:23:07 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <CAD=FV=XJ=_o+hVbD=pPqXxXo=1PZdeRWyn-xyfS+Jf5LYfe2dg@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-4-git-send-email-t.figa@samsung.com>
 <CAD=FV=XJ=_o+hVbD=pPqXxXo=1PZdeRWyn-xyfS+Jf5LYfe2dg@mail.gmail.com>
Message-ID: <4241187.TFCdy2kUT6@flatron>

On Friday 17 of May 2013 12:24:04 Doug Anderson wrote:
> Tomasz,
> 
> On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> > This patch makes legacy code on suspend/resume path being executed
> > conditionally, on non-DT platforms only, to fix suspend/resume of
> > DT-enabled systems, for which the code is inappropriate.
> > 
> > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> > 
> >  arch/arm/plat-samsung/pm.c | 17 ++++++++++++-----
> >  1 file changed, 12 insertions(+), 5 deletions(-)
> > 
> > diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
> > index 53210ec..8ac2b2d 100644
> > --- a/arch/arm/plat-samsung/pm.c
> > +++ b/arch/arm/plat-samsung/pm.c
> > @@ -261,7 +261,8 @@ static int s3c_pm_enter(suspend_state_t state)
> > 
> >          * require a full power-cycle)
> >         
> >         */
> > 
> > -       if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
> > +       if (!of_have_populated_dt() &&
> > +           !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
> 
> I'd rather see you modify patch set #2 to provide some function to
> retrieve just the eint mask and then use it here.  Your patch removes
> this test and doesn't replace it with anything.  If you moved this
> test to pinctrl directly you'd lose the test against intallow.

Well, looking from the perspective of status before my patch, it just 
bypasses a test that is incorrect on DT-enabled platforms.

I agree that this test is rather reasonable to have, but it would require 
defining a new interface and moving all platforms to it, which for now 
would be a bit of overkill.

IMHO a separate series that sanitizes the whole PM handling in plat-
samsung, including a rework of this check to make it cover all platforms 
in a generic and multiplatform-friendly way. What do you think?

> ...or do you think this test is no longer useful for some reason?
> 
> >             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow))
> >             {
> >             
> >                 printk(KERN_ERR "%s: No wake-up sources!\n",
> >                 __func__);
> >                 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
> > 
> > @@ -270,8 +271,11 @@ static int s3c_pm_enter(suspend_state_t state)
> > 
> >         /* save all necessary core registers not covered by the
> >         drivers */
> > 
> > -       samsung_pm_save_gpios();
> > -       samsung_pm_saved_gpios();
> > +       if (!of_have_populated_dt()) {
> > +               samsung_pm_save_gpios();
> > +               samsung_pm_saved_gpios();
> > +       }
> > +
> 
> Ah, the important part here is the "saved", not the "save"!  The
> "save" should get a NULL chip for all GPIOs and effectively be a
> no-op.
> 
> Skipping the "saved" is important of s3c64xx and s5p64x0 where the
> "saved" seems to transition things over to powerdown mode.  Hopefully
> a future patch of yours adds that back for those platforms in the
> pinmux world.  ...same for restore.

S3C64xx can be switched to power down pin configuration manually, but if 
you don't do it, it will activate it automatically after entering sleep 
mode.

> Summary: I've tested this on exynos5250-snow and it's reasonable but
> I'd love a response about the missing test before adding Reviewed-by.

Thanks.

Best regards,
Tomasz



From tomasz.figa at gmail.com  Fri May 17 16:34:21 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 May 2013 22:34:21 +0200
Subject: [PATCH 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <CAD=FV=WKCeW=3BFnmnyXB70VCjXHGrzarXbj8cBfq4-ENA-Y2w@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-7-git-send-email-t.figa@samsung.com>
 <CAD=FV=WKCeW=3BFnmnyXB70VCjXHGrzarXbj8cBfq4-ENA-Y2w@mail.gmail.com>
Message-ID: <18754346.1REWN52J0K@flatron>

On Friday 17 of May 2013 12:25:02 Doug Anderson wrote:
> Tomasz,
> 
> On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> > Some GPIO EINT control registers needs to be preserved across
> > suspend/resume cycle. This patch extends the driver to take care of
> > this.
> 
> I was confused why we didn't seem to need this on exynos5250-snow but
> figured it out.  We only use interrupts on GPX lines which don't need
> this code.  ...but on any exynos5250 boards that use one of the other
> banks for interrupts you'd need it.  I tested by setting one of the
> registers related to GPA0 and found that this code is indeed needed on
> exynos5250.  :)
> 
> Just nits / optional comments below, so on exynos5250-snow (pinmux
> backported to 3.8):
> 
> Tested-by: Doug Anderson <dianders at chromium.org>
> 
> Reviewed-by: Doug Anderson <dianders at chromium.org>
> 
> > @@ -229,6 +235,11 @@ static int exynos_eint_gpio_init(struct
> > samsung_pinctrl_drv_data *d)> 
> >                         dev_err(dev, "gpio irq domain add failed\n");
> >                         return -ENXIO;
> >                 
> >                 }
> > 
> > +
> > +               bank->soc_priv = devm_kzalloc(d->dev,
> > +                       sizeof(struct exynos_eint_gpio_save),
> > GFP_KERNEL); +               if (!bank->soc_priv)
> > +                       return -ENOMEM;
> 
> Slight nit to add this before the call to irq_domain_add_linear().
> demv() will handle freeing your memory but nothing will handle undoing
> the irq_domain_add_linear() if you return an error.

I'm a bit sceptical when it is about error handling in such cases. 
Basically if interrupt initialization fails, something is seriously wrong, 
either with your kernel config or with some code.

Since such case has been already unhandled in the driver (with nr_banks > 
1 = always), so I didn't bother to add any undoing here.

> >         }
> >         
> >         return 0;
> > 
> > @@ -528,6 +539,58 @@ static int exynos_eint_wkup_init(struct
> > samsung_pinctrl_drv_data *d)> 
> >         return 0;
> >  
> >  }
> > 
> > +static void exynos_pinctrl_suspend_bank(
> > +                               struct samsung_pinctrl_drv_data
> > *drvdata, +                               struct samsung_pin_bank
> > *bank) +{
> > +       struct exynos_eint_gpio_save *save = bank->soc_priv;
> > +       void __iomem *regs = drvdata->virt_base;
> > +
> > +       save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
> > +                                               + bank->eint_offset);
> > +       save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > +                                               + 2 *
> > bank->eint_offset); +       save->eint_fltcon1 = readl(regs +
> > EXYNOS_GPIO_EFLTCON_OFFSET +                                         
> >      + 2 * bank->eint_offset + 4);
> Optional: I wish there were debug statements to help debug, like:
> 
> pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
> pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
> pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
> 

Right, seems reasonable.

> > +}
> > +
> > +static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data
> > *drvdata) +{
> > +       struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
> > +       struct samsung_pin_bank *bank = ctrl->pin_banks;
> > +       int i;
> > +
> > +       for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
> > +               if (bank->eint_type == EINT_TYPE_GPIO)
> > +                       exynos_pinctrl_suspend_bank(drvdata, bank);
> > +}
> > +
> > +static void exynos_pinctrl_resume_bank(
> > +                               struct samsung_pinctrl_drv_data
> > *drvdata, +                               struct samsung_pin_bank
> > *bank) +{
> > +       struct exynos_eint_gpio_save *save = bank->soc_priv;
> > +       void __iomem *regs = drvdata->virt_base;
> > +
> 
> Optional: debug statements:
> 
> pr_debug("%s:     con %#010x => %#010x\n", bank->name,
>   readl(regs + EXYNOS_GPIO_ECON_OFFSET + bank->eint_offset),
>   save->eint_con);
> pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
>   readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset),
>   save->eint_fltcon0);
> pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
>   readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4),
>   save->eint_fltcon1);

OK. I wonder if this could be added in a separate patch or I should rather 
send v2 on Monday?

Best regards,
Tomasz



From tomasz.figa at gmail.com  Fri May 17 16:51:04 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 May 2013 22:51:04 +0200
Subject: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific
 suspend/resume callbacks
In-Reply-To: <CAD=FV=Xy2Poti6Wz594DpN1ZbB3FQJ1Dkt+PND1Z0fqf2pJvaw@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-5-git-send-email-t.figa@samsung.com>
 <CAD=FV=Xy2Poti6Wz594DpN1ZbB3FQJ1Dkt+PND1Z0fqf2pJvaw@mail.gmail.com>
Message-ID: <31112981.QqbfMZZPSN@flatron>

On Friday 17 of May 2013 12:24:29 Doug Anderson wrote:
> Tomasz,
> 
> On Fri, May 17, 2013 at 9:24 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> > +       if (ctrl->resume)
> > +               ctrl->resume(drvdata);
> > +
> 
> Having this resume at the beginning of the function seems right for
> restoring eint settings like you do in patch #6.
> 
> ...but if you need to try to handle the old s3c64xx and s5p64x0
> concept of "restored" to actually take GPIOs out of powerdown mode
> then you'll also need a callback at the end.
> 
> Does it make sense to add a second callback at the end of this function?

Right. I haven't thought of this. It might make sense to add .resumed() 
callback as well to handle this.

I guess it could be added as a part of patches for S3C64xx-specific 
pinctrl suspend/resume, that I will post some day.

> ...since it's unclear how we'll handle s3c64xx/s5p64x0 (or even if I'm
> misunderstanding and they're already handled somehow), I don't see any
> problems with this patch, so...
> 
> 
> On exynos5250-snow (pinmux backported to 3.8):
> 
> Tested-by: Doug Anderson <dianders at chromium.org>
> 
> Reviewed-by: Doug Anderson <dianders at chromium.org>

Thanks.

Best regards,
Tomasz



From dianders at chromium.org  Fri May 17 16:56:39 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 13:56:39 -0700
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <4241187.TFCdy2kUT6@flatron>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-4-git-send-email-t.figa@samsung.com>
 <CAD=FV=XJ=_o+hVbD=pPqXxXo=1PZdeRWyn-xyfS+Jf5LYfe2dg@mail.gmail.com>
 <4241187.TFCdy2kUT6@flatron>
Message-ID: <CAD=FV=XcmzogZc9mWQ+FSr9dg9jML-ACUJY2M2-s+_rBw9gMzQ@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 1:23 PM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>> I'd rather see you modify patch set #2 to provide some function to
>> retrieve just the eint mask and then use it here.  Your patch removes
>> this test and doesn't replace it with anything.  If you moved this
>> test to pinctrl directly you'd lose the test against intallow.
>
> Well, looking from the perspective of status before my patch, it just
> bypasses a test that is incorrect on DT-enabled platforms.

True.  What was there before was broken and this avoids the broken code.


> I agree that this test is rather reasonable to have, but it would require
> defining a new interface and moving all platforms to it, which for now
> would be a bit of overkill.

It seems like you could use the same type of solution as patch set #2?

...oh, but that's only for exynos!  I guess we would need something
similar for other platforms.  ...and until we do those other platforms
(including S3C64xx, I think) are still using the old
s3c_irqwake_eintmask, right?

...so overall your patch series only fully fixes exynos, though it
does make other platforms less broken which is a plus.  :)


> IMHO a separate series that sanitizes the whole PM handling in plat-
> samsung, including a rework of this check to make it cover all platforms
> in a generic and multiplatform-friendly way. What do you think?

Sure, I think that would be OK.


>> Ah, the important part here is the "saved", not the "save"!  The
>> "save" should get a NULL chip for all GPIOs and effectively be a
>> no-op.
>>
>> Skipping the "saved" is important of s3c64xx and s5p64x0 where the
>> "saved" seems to transition things over to powerdown mode.  Hopefully
>> a future patch of yours adds that back for those platforms in the
>> pinmux world.  ...same for restore.
>
> S3C64xx can be switched to power down pin configuration manually, but if
> you don't do it, it will activate it automatically after entering sleep
> mode.

How would restore work in that case?  I'd imagine that it would
automatically switch out of the powerdown config at wakeup before
running software?  That doesn't seem like a great idea.

I think that to make S3C64xx work properly we'd need to solve.


I wouldn't be opposed to a re-spin to address some of the above, but I
also won't object to this landing and remaining issues being addressed
in future patches.  This patch definitely does make things better and
no worse.  :)

On exynos5250-snow (pinmux backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>


From tony at atomide.com  Fri May 17 17:03:17 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 May 2013 14:03:17 -0700
Subject: [PATCH] ARM: OMAP2+: Fix multiple randconfig errors if no SoC is
 selected, take3
Message-ID: <20130517210317.GB10378@atomide.com>

If no SoC is selected, we should not build any of the SoC support
code for omap2+. Otherwise we can get multiple errors with make
randconfig.

Based on the mailing list discussions we came to the conclusion that
this is best fixed with a combination of Makefile and Kconfig changes.

Some issues are best fixed by selecting objects in Makefile based on
a combination of features and SoC as suggested by Arnd Bergman and
done in commit 572b16db7 (ARM: OMAP: build SMP code only for OMAP4/5).

For the SoC related code, we should not build any of the dependant
features though. This is best done by making the SoC dependant
features depend on at least one SoC being selected as done in
this patch.

The minimal fix is to select the existing config ARCH_OMAP only if a SoC
is selected, and then build the SoC dependant objects only if config
ARCH_OMAP is selected. While at it, we can also change ARCH_OMAP2
to a menuconfig which allows us to drop the now unnecessary menu entry.

For reference, the build errors without this patch are something like:

arch/arm/mach-omap2/built-in.o: In function `_add_initiator_dep':
arch/arm/mach-omap2/omap_hwmod.c:691: undefined reference to `clkdm_add_sleepdep'
arch/arm/mach-omap2/built-in.o: In function `_deassert_hardreset':
arch/arm/mach-omap2/omap_hwmod.c:1677: undefined reference to `clkdm_in_hwsup'
arch/arm/mach-omap2/omap_hwmod.c:1678: undefined reference to `clkdm_hwmod_enable'
arch/arm/mach-omap2/omap_hwmod.c:1705: undefined reference to `clkdm_allow_idle'
arch/arm/mach-omap2/omap_hwmod.c:1708: undefined reference to `clkdm_hwmod_disable'
arch/arm/mach-omap2/built-in.o: In function `_enable':
arch/arm/mach-omap2/omap_hwmod.c:2145: undefined reference to `clkdm_in_hwsup'
arch/arm/mach-omap2/omap_hwmod.c:2147: undefined reference to `clkdm_hwmod_enable'
arch/arm/mach-omap2/omap_hwmod.c:2145: undefined reference to `clkdm_missing_idle_reporting'
arch/arm/mach-omap2/omap_hwmod.c:2191: undefined reference to `clkdm_hwmod_disable'
arch/arm/mach-omap2/omap_hwmod.c:2172: undefined reference to `clkdm_allow_idle'
arch/arm/mach-omap2/built-in.o: In function `_del_initiator_dep':
arch/arm/mach-omap2/omap_hwmod.c:720: undefined reference to `clkdm_del_sleepdep'
arch/arm/mach-omap2/built-in.o: In function `_idle':
arch/arm/mach-omap2/omap_hwmod.c:2235: undefined reference to `clkdm_hwmod_disable'
arch/arm/mach-omap2/built-in.o: In function `_shutdown':
arch/arm/mach-omap2/omap_hwmod.c:2338: undefined reference to `clkdm_hwmod_disable'
arch/arm/mach-omap2/built-in.o: In function `omap_hwmod_get_context_loss_count':
arch/arm/mach-omap2/omap_hwmod.c:4071: undefined reference to `pwrdm_get_context_loss_count'
arch/arm/mach-omap2/built-in.o: In function `pm_dbg_show_timers':
arch/arm/mach-omap2/pm-debug.c:155: undefined reference to `pwrdm_for_each'
arch/arm/mach-omap2/built-in.o: In function `pwrdm_dbg_show_timer':
arch/arm/mach-omap2/pm-debug.c:132: undefined reference to `pwrdm_state_switch'
arch/arm/mach-omap2/built-in.o: In function `pm_dbg_show_counters':
arch/arm/mach-omap2/pm-debug.c:147: undefined reference to `pwrdm_for_each'
arch/arm/mach-omap2/pm-debug.c:148: undefined reference to `clkdm_for_each'
arch/arm/mach-omap2/built-in.o: In function `pwrdm_dbg_show_counter':
arch/arm/mach-omap2/pm-debug.c:102: undefined reference to `pwrdm_read_pwrst'
arch/arm/mach-omap2/pm-debug.c:103: undefined reference to `pwrdm_read_pwrst'
arch/arm/mach-omap2/built-in.o: In function `omap2_common_pm_late_init':
arch/arm/mach-omap2/pm.c:294: undefined reference to `omap_voltage_late_init'
arch/arm/mach-omap2/built-in.o: In function `omap_pm_clkdms_setup':
arch/arm/mach-omap2/pm.c:117: undefined reference to `clkdm_sleep'
arch/arm/mach-omap2/pm.c:114: undefined reference to `clkdm_allow_idle'
arch/arm/mach-omap2/built-in.o: In function `omap2_gpio_dev_init':
arch/arm/mach-omap2/gpio.c:133: undefined reference to `pwrdm_can_ever_lose_context'
arch/arm/mach-omap2/built-in.o: In function `pm_dbg_init':
arch/arm/mach-omap2/pm-debug.c:272: undefined reference to `pwrdm_for_each'

Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>
Signed-off-by: Tony Lindgren <tony at atomide.com>

---

Here's a combined Kconfig + Makefile fix for this. I've tried to keep it
as minimal as possible as I'd like to get this fix merged as a fix.
That is unless you guys think it's too intrusive for the -rc series.


diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..b6eb91d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,11 +1,10 @@
 config ARCH_OMAP
 	bool
 
-config ARCH_OMAP2PLUS
+menuconfig ARCH_OMAP2PLUS
 	bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_HOLES_MEMORYMODEL
-	select ARCH_OMAP
 	select ARCH_REQUIRE_GPIOLIB
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
@@ -24,8 +23,6 @@ config ARCH_OMAP2PLUS
 
 if ARCH_OMAP2PLUS
 
-menu "TI OMAP2/3/4 Specific Features"
-
 config ARCH_OMAP2PLUS_TYPICAL
 	bool "Typical OMAP configuration"
 	default y
@@ -45,6 +42,7 @@ config ARCH_OMAP2PLUS_TYPICAL
 
 config SOC_HAS_OMAP2_SDRC
 	bool "OMAP2 SDRAM Controller support"
+	depends on ARCH_OMAP
 
 config SOC_HAS_REALTIME_COUNTER
 	bool "Real time free running counter"
@@ -57,6 +55,7 @@ config ARCH_OMAP2
 	depends on ARCH_MULTI_V6
 	default y
 	select CPU_V6
+	select ARCH_OMAP
 	select MULTI_IRQ_HANDLER
 	select SOC_HAS_OMAP2_SDRC
 	select COMMON_CLK
@@ -69,6 +68,7 @@ config ARCH_OMAP3
 	select ARCH_HAS_OPP
 	select ARM_CPU_SUSPEND if PM
 	select CPU_V7
+	select ARCH_OMAP
 	select MULTI_IRQ_HANDLER
 	select OMAP_INTERCONNECT
 	select PM_OPP if PM
@@ -89,6 +89,7 @@ config ARCH_OMAP4
 	select ARM_GIC
 	select CACHE_L2X0
 	select CPU_V7
+	select ARCH_OMAP
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if LOCAL_TIMERS
 	select HAVE_SMP
@@ -109,6 +110,7 @@ config SOC_OMAP5
 	select ARM_CPU_SUSPEND if PM
 	select ARM_GIC
 	select CPU_V7
+	select ARCH_OMAP
 	select HAVE_SMP
 	select COMMON_CLK
 	select HAVE_ARM_ARCH_TIMER
@@ -146,6 +148,7 @@ config SOC_AM33XX
 	default y
 	select ARM_CPU_SUSPEND if PM
 	select CPU_V7
+	select ARCH_OMAP
 	select MULTI_IRQ_HANDLER
 	select COMMON_CLK
 
@@ -435,6 +438,5 @@ config OMAP4_ERRATA_I688
 	  In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
 	  IO barrier ensure that there is no synchronisation loss on initiators
 	  operating on both interconnect port simultaneously.
-endmenu
 
 endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..a0e0251 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 	-I$(srctree)/arch/arm/plat-omap/include
 
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
+soc-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
 	 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
 	 omap_device.o sram.o
 
@@ -85,7 +85,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o
 obj-$(CONFIG_SOC_OMAP5)			+= omap-mpuss-lowpower.o
-obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
+pm-$(CONFIG_ARCH_OMAP)			+= pm-debug.o
+obj-$(CONFIG_PM_DEBUG)			+= $(pm-y)
 
 obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o
 obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
@@ -201,7 +202,8 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)			+= emu.o
-obj-$(CONFIG_HW_PERF_EVENTS)		+= pmu.o
+pmu-$(CONFIG_ARCH_OMAP)			+= pmu.o
+obj-$(CONFIG_HW_PERF_EVENTS)		+= $(pmu-y)
 
 obj-$(CONFIG_OMAP_MBOX_FWK)		+= mailbox_mach.o
 mailbox_mach-objs			:= mailbox.o
@@ -266,28 +268,28 @@ obj-$(CONFIG_MACH_TI8148EVM)		+= board-ti8168evm.o
 
 omap-flash-$(CONFIG_MTD_NAND_OMAP2)	:= board-flash.o
 omap-flash-$(CONFIG_MTD_ONENAND_OMAP2)	:= board-flash.o
-obj-y					+= $(omap-flash-y) $(omap-flash-m)
+soc-y					+= $(omap-flash-y) $(omap-flash-m)
 
 omap-hsmmc-$(CONFIG_MMC_OMAP_HS)	:= hsmmc.o
 obj-y					+= $(omap-hsmmc-m) $(omap-hsmmc-y)
 
-obj-y					+= usb-musb.o
-obj-y					+= omap_phy_internal.o
+soc-y					+= usb-musb.o
+soc-y					+= omap_phy_internal.o
 
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
-obj-y					+= usb-host.o
+soc-y					+= usb-host.o
 
 onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
-obj-y					+= $(onenand-m) $(onenand-y)
+soc-y					+= $(onenand-m) $(onenand-y)
 
 nand-$(CONFIG_MTD_NAND_OMAP2)		:= gpmc-nand.o
-obj-y					+= $(nand-m) $(nand-y)
+soc-y					+= $(nand-m) $(nand-y)
 
 smc91x-$(CONFIG_SMC91X)			:= gpmc-smc91x.o
-obj-y					+= $(smc91x-m) $(smc91x-y)
+soc-y					+= $(smc91x-m) $(smc91x-y)
 
 smsc911x-$(CONFIG_SMSC911X)		:= gpmc-smsc911x.o
-obj-y					+= $(smsc911x-m) $(smsc911x-y)
+soc-y					+= $(smsc911x-m) $(smsc911x-y)
 ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
 obj-y					+= hwspinlock.o
 endif
@@ -295,4 +297,7 @@ endif
 emac-$(CONFIG_TI_DAVINCI_EMAC)		:= am35xx-emac.o
 obj-y					+= $(emac-m) $(emac-y)
 
-obj-y					+= common-board-devices.o twl-common.o dss-common.o
+soc-y					+= common-board-devices.o twl-common.o dss-common.o
+
+# SoC dependant objects
+obj-$(CONFIG_ARCH_OMAP)			+= $(soc-y)


From mgreer at animalcreek.com  Fri May 17 17:05:50 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Fri, 17 May 2013 14:05:50 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130515015212.GB3268@animalcreek.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
Message-ID: <20130517210550.GH28484@animalcreek.com>

On Tue, May 14, 2013 at 06:52:12PM -0700, Mark A. Greer wrote:
> On Tue, May 14, 2013 at 05:25:37PM -0700, Tony Lindgren wrote:
> > Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> > changed PM to not access IVA registers on omaps that don't have
> > them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm
> > will stay on and block deeper idle states.
> > 
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > 
> > ---
> > 
> > Paul & Kevin, do you have better ideas for fixing this?
> > 
> > --- a/arch/arm/mach-omap2/pm34xx.c
> > +++ b/arch/arm/mach-omap2/pm34xx.c
> > @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
> >  	/* Clear any pending PRCM interrupts */
> >  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> >  
> > -	if (omap3_has_iva())
> > -		omap3_iva_idle();
> > +	/*
> > +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> > +	 */
> > +	omap3_iva_idle();
> >  
> >  	omap3_d2d_idle();
> >  }

> This is potentially bad for other SoC's that don't have an IVA so I don't
> think its the way to go.  My preference would be to set the OMAP3_HAS_IVA
> flag for the am3703 only since its the one with the bug.  Maybe something
> in id.c:omap3xxx_check_features() but I don't see any existing way to check
> for an am3703 vs. other am37xx SoCs.  Any ideas?

As I think about it more, I may have been overly dramatic here.

Before the check that's being removed existed, omap3_iva_idle() was always
called and nobody complained (including am3517).  So, I'd still like to hear
what Yegor can figure out but I have to believe that this patch is safe.

Mark
--


From tomasz.figa at gmail.com  Fri May 17 17:07:11 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 May 2013 23:07:11 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <CAD=FV=XcmzogZc9mWQ+FSr9dg9jML-ACUJY2M2-s+_rBw9gMzQ@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <4241187.TFCdy2kUT6@flatron>
 <CAD=FV=XcmzogZc9mWQ+FSr9dg9jML-ACUJY2M2-s+_rBw9gMzQ@mail.gmail.com>
Message-ID: <1666561.1GujhmlVbA@flatron>

On Friday 17 of May 2013 13:56:39 Doug Anderson wrote:
> Tomasz,
> 
> On Fri, May 17, 2013 at 1:23 PM, Tomasz Figa <tomasz.figa at gmail.com> 
wrote:
> >> I'd rather see you modify patch set #2 to provide some function to
> >> retrieve just the eint mask and then use it here.  Your patch removes
> >> this test and doesn't replace it with anything.  If you moved this
> >> test to pinctrl directly you'd lose the test against intallow.
> > 
> > Well, looking from the perspective of status before my patch, it just
> > bypasses a test that is incorrect on DT-enabled platforms.
> 
> True.  What was there before was broken and this avoids the broken code.
> > I agree that this test is rather reasonable to have, but it would
> > require defining a new interface and moving all platforms to it,
> > which for now would be a bit of overkill.
> 
> It seems like you could use the same type of solution as patch set #2?
> 
> ...oh, but that's only for exynos!  I guess we would need something
> similar for other platforms.  ...and until we do those other platforms
> (including S3C64xx, I think) are still using the old
> s3c_irqwake_eintmask, right?

Correct.

Also as an extra side note, intallow is used here as a mask of valid 
eintmask bits on given platform. On Exynos SoCs there are 32 EINTs, so 
this extra mask is not needed.

> ...so overall your patch series only fully fixes exynos, though it
> does make other platforms less broken which is a plus.  :)
> 
> > IMHO a separate series that sanitizes the whole PM handling in plat-
> > samsung, including a rework of this check to make it cover all
> > platforms in a generic and multiplatform-friendly way. What do you
> > think?
> Sure, I think that would be OK.
> 
> >> Ah, the important part here is the "saved", not the "save"!  The
> >> "save" should get a NULL chip for all GPIOs and effectively be a
> >> no-op.
> >> 
> >> Skipping the "saved" is important of s3c64xx and s5p64x0 where the
> >> "saved" seems to transition things over to powerdown mode.  Hopefully
> >> a future patch of yours adds that back for those platforms in the
> >> pinmux world.  ...same for restore.
> > 
> > S3C64xx can be switched to power down pin configuration manually, but
> > if you don't do it, it will activate it automatically after entering
> > sleep mode.
> 
> How would restore work in that case?  I'd imagine that it would
> automatically switch out of the powerdown config at wakeup before
> running software?  That doesn't seem like a great idea.

This is configurable. There is a bit that determines whether it should 
switch back to normal config automatically or not. What's interesting is 
that AFAIR current code uses automatic switch, which even with the glitch 
prevention in resume can glitch things, due to the period of time between 
wake-up and resume when pins are misconfigured.

I think we should just configure this bit for manual switch back and 
trigger the switch from .resumed() callback of the pin controller in 
pinctrl-s3c64xx driver. I will post a patch for this some day.

> I think that to make S3C64xx work properly we'd need to solve.
> 
> 
> I wouldn't be opposed to a re-spin to address some of the above, but I
> also won't object to this landing and remaining issues being addressed
> in future patches.  This patch definitely does make things better and
> no worse.  :)

Let's see. If nobody takes this until Monday, which is very likely, I will 
send new version.

> On exynos5250-snow (pinmux backported to 3.8):
> 
> Tested-by: Doug Anderson <dianders at chromium.org>
> 
> Reviewed-by: Doug Anderson <dianders at chromium.org>

Thanks.

Best regards,
Tomasz



From maxime.ripard at free-electrons.com  Fri May 17 17:18:33 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 17 May 2013 23:18:33 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
Message-ID: <51969EA9.1060602@free-electrons.com>

Hi Oliver,

Le 17/05/2013 15:35, Oliver Schinagl a ?crit :
> From: Oliver Schinagl <oliver at schinagl.nl>
> 
> Allwinner has electric fuses (efuse) on their line of chips. This driver
> reads those fuses and exports them as a sysfs node. Also a symbol is exported
> for in-kernel useage.
> 
> While initially these fuses are used to somewhat determin the chipID, these
> appear to be writeable by the user and thus can be used for other purpouses.
> For example storing a 128 bit root key, a unique serial number, which could
> then even be used as a MAC address.
> 
> Because writing to e-fuses can be potentially dangerous, and are certainly
> not as often writable (if at all) as flash memory, these shouldn't be easily
> changeable, hence only a read-only mode. An offline tool to write the fuses
> is in the works.
> 
> Currently supported are the following known chips:
> Allwinner sun4i (A10)
> Allwinner sun5i (A10s A13)
> Allwinner sun6i (A31, A31s)
> Allwinner sun7i (A20)

Since I don't think those patches have been tested on sun6i/sun7i, and
that there's not even kernel support for those, maybe it's not worth
mentionning them?

> 
> Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
> ---
>  drivers/misc/eeprom/Kconfig     |  19 ++++
>  drivers/misc/eeprom/Makefile    |   1 +
>  drivers/misc/eeprom/sunxi_sid.c | 218 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 238 insertions(+)
>  create mode 100644 drivers/misc/eeprom/sunxi_sid.c
> 
> diff --git a/drivers/misc/eeprom/Kconfig b/drivers/misc/eeprom/Kconfig
> index 04f2e1f..c9ddda5 100644
> --- a/drivers/misc/eeprom/Kconfig
> +++ b/drivers/misc/eeprom/Kconfig
> @@ -96,4 +96,23 @@ config EEPROM_DIGSY_MTC_CFG
>  
>  	  If unsure, say N.
>  
> +config EEPROM_SUNXI_SID
> +	tristate "Allwinner sunxi security ID support"
> +	depends on ARCH_SUNXI && SYSFS
> +	help
> +	  This is a driver for the 'security ID' available on various Allwinner
> +	  devices. Currently supported are:
> +		sun4i (A10)
> +		sun5i (A10s, A12, A13)
> +		sun6i (A31)
> +		sun7i (A20)

Same things here.

> +
> +	  Due to the potential risks involved with changing e-fuses,
> +	  this driver is read-only
> +
> +	  For more information visit http://linux-sunxi.org/SID
> +
> +	  This driver can also be built as a module. If so, the module
> +	  will be called sunxi_sid.
> +
>  endmenu
> diff --git a/drivers/misc/eeprom/Makefile b/drivers/misc/eeprom/Makefile
> index fc1e81d..9507aec 100644
> --- a/drivers/misc/eeprom/Makefile
> +++ b/drivers/misc/eeprom/Makefile
> @@ -4,4 +4,5 @@ obj-$(CONFIG_EEPROM_LEGACY)	+= eeprom.o
>  obj-$(CONFIG_EEPROM_MAX6875)	+= max6875.o
>  obj-$(CONFIG_EEPROM_93CX6)	+= eeprom_93cx6.o
>  obj-$(CONFIG_EEPROM_93XX46)	+= eeprom_93xx46.o
> +obj-$(CONFIG_EEPROM_SUNXI_SID)	+= sunxi_sid.o
>  obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o
> diff --git a/drivers/misc/eeprom/sunxi_sid.c b/drivers/misc/eeprom/sunxi_sid.c
> new file mode 100644
> index 0000000..953f137
> --- /dev/null
> +++ b/drivers/misc/eeprom/sunxi_sid.c
> @@ -0,0 +1,218 @@
> +/*
> + * Copyright (c) 2013 Oliver Schinagl
> + * http://www.linux-sunxi.org
> + *
> + * Oliver Schinagl <oliver at schinagl.nl>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * This driver exposes the Allwinner security ID, a 128 bit eeprom, in chunks
> + * of 8 bytes.

16 bytes or 8 bits? because 8 bytes != 128 bits.

> + */
> +
> +#include <linux/compiler.h>
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/fs.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kobject.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/stat.h>
> +#include <linux/sysfs.h>
> +#include <linux/types.h>
> +
> +
> +#define DRV_NAME "sunxi-sid"
> +#define DRV_VERSION "1.0"
> +
> +/* Register offsets */
> +#define SUNXI_SID_KEY0 0x00
> +#define SUNXI_SID_KEY1 0x04
> +#define SUNXI_SID_KEY2 0x08
> +#define SUNXI_SID_KEY3 0x0c
> +
> +/* There are 4 32-bit keys */
> +#define SUNXI_SID_KEYS 4
> +/* and 4 32-bit keys per 32-bit key */

The comment is wrong here.

> +#define SUNXI_SID_SIZE (SUNXI_SID_KEYS * 4)
> +
> +#if (SUNXI_SID_SIZE > PAGE_SIZE)
> +#error "SUNXI_SID_SIZE is larger then the target's PAGE_SIZE, ENOMEM."
> +#endif

Hmmmm, I don't follow you here, what's the relation between your driver
and PAGE_SIZE?

> +
> +static u8 keys_lut[] = {
> +	SUNXI_SID_KEY0,
> +	SUNXI_SID_KEY1,
> +	SUNXI_SID_KEY2,
> +	SUNXI_SID_KEY3,
> +};
> +
> +struct sid_priv {
> +	void __iomem *sid_base;
> +};
> +
> +struct sid_priv *p;

What's the point of having a structure here? And why putting a global
value, !static, with a generic name, while you could have an
instance-specific one?

struct file has a private_data field, use it.

> +
> +
> +/* We read the entire key, using a look up table. Returned is only the
> + * requested byte. This is of course slower then it could be and uses 4 times
> + * more reads as needed but keeps code a little simpler.
> + */
> +u8 sunxi_sid_read_byte(const int key)
> +{
> +	u32 sid_key;
> +	u8 ret;
> +
> +	ret = 0;
> +	if (likely((key <= SUNXI_SID_SIZE))) {
> +		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
> +		switch (key % 4) {
> +		case 0:
> +			ret = (sid_key >> 24) & 0xff;
> +			break;
> +		case 1:
> +			ret = (sid_key >> 16) & 0xff;
> +			break;
> +		case 2:
> +			ret = (sid_key >> 8) & 0xff;
> +			break;
> +		case 3:
> +			ret = sid_key & 0xff;
> +			break;
> +		}
> +	}

Come on, you can do better. This lookup table is useless.

Also, why the first key is the one with the MSBs?
I'd expect that the key 0 is the one holding the LSBs.

> +
> +	return ret;
> +}
> +
> +static ssize_t sid_read(struct file *fd, struct kobject *kobj,
> +			struct bin_attribute *attr, char *buf,
> +			loff_t pos, size_t size)
> +{
> +	ssize_t ret;
> +	struct device *dev;
> +	struct sid_priv *priv;
> +	int i;
> +
> +	ret = -EPERM;
> +	dev = kobj_to_dev(kobj);
> +	priv = dev_get_drvdata(dev);
> +
> +	if ((likely(size > 0)) && ((size + pos) <= SUNXI_SID_SIZE)) {
> +		for (i = 0; i < size; i++) {
> +			buf[i] = sunxi_sid_read_byte(pos + i);
> +		}
> +		if (i < PAGE_SIZE) {
> +			buf[i] = '\0';
> +			ret = (ssize_t)size;
> +		} else {
> +			ret = -ENOMEM;
> +		}

Hmmmm, what? Why returning \0 here? It's not a string, it's binary data.
What's the relation with PAGE_SIZE again?

Just return the number of bytes read, that's it.

> +	} else {
> +		buf[0] = '\0';
> +		ret = 0;
> +	}
> +
> +	return ret;
> +}
> +
> +static struct of_device_id sid_of_match[] = {
> +	{
> +		.compatible = "allwinner,sun4i-sid",
> +	},
> +	{/* sentinel */}
> +};
> +MODULE_DEVICE_TABLE(of, sid_of_match);
> +
> +static struct bin_attribute sid_bin_attr = {
> +	.attr = {
> +		.name = "key",
> +		.mode = S_IRUGO,
> +	},
> +	.size = SUNXI_SID_SIZE,
> +	.read = sid_read,
> +};
> +
> +static int sid_remove(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct sid_priv *priv;
> +
> +	priv = dev_get_drvdata(dev);
> +	device_remove_bin_file(dev, &sid_bin_attr);
> +	iounmap(priv->sid_base);
> +	devm_kfree(dev, priv);
> +	return 0;
> +}
> +
> +static int __init sid_probe(struct platform_device *pdev)
> +{
> +	int ret;
> +	struct device *dev = &pdev->dev;
> +	struct sid_priv *priv;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	p = priv;
> +
> +	dev_set_drvdata(dev, priv);
> +
> +	if (!priv) {
> +		dev_err(dev, "Unable to allocate device private data\n");
> +		ret = -ENOMEM;
> +		goto exit;
> +	}

Isn't it a bit weird to check for the memory allocation after using the
variable. Also, you don't really need the dev_err, since if the kernel
fails to allocate some memory, it will tell you anyway.

> +	priv->sid_base = of_iomap(dev->of_node, 0);
> +	if (!priv->sid_base) {
> +		dev_err(dev, "Unable to map memory region\n");
> +		ret = -ENOMEM;
> +		goto exit_free;
> +	}
> +
> +	ret = device_create_bin_file(dev, &sid_bin_attr);
> +	if (ret) {
> +		dev_err(dev, "Unable to create sysfs bin entry\n");
> +		goto exit_unmap;
> +	}

Hmmm, maybe it's not worth all these gotos just for an iounmap, I'd
probably return right away, but that's your call.

> +	dev_info(dev, "Sunxi security ID driver loaded successfully.\n");
> +
> +	return 0;
> +
> +
> +exit_unmap:
> +	iounmap(priv->sid_base);
> +exit_free:
> +	devm_kfree(dev, priv);
> +exit:
> +	return ret;
> +}
> +
> +static struct platform_driver sid_driver = {
> +	.probe = sid_probe,
> +	.remove = sid_remove,
> +	.driver = {
> +		.name = DRV_NAME,
> +		.owner = THIS_MODULE,
> +		.of_match_table = sid_of_match,
> +	},
> +};
> +module_platform_driver(sid_driver);
> +
> +
> +MODULE_AUTHOR("Oliver Schinagl <oliver at schinagl.nl>");
> +MODULE_DESCRIPTION("Allwinner sunxi security id driver");
> +MODULE_VERSION(DRV_VERSION);
> +MODULE_LICENSE("GPL");
> 

Thanks for this driver!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From dianders at chromium.org  Fri May 17 17:18:39 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 17 May 2013 14:18:39 -0700
Subject: [PATCH 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <18754346.1REWN52J0K@flatron>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-7-git-send-email-t.figa@samsung.com>
 <CAD=FV=WKCeW=3BFnmnyXB70VCjXHGrzarXbj8cBfq4-ENA-Y2w@mail.gmail.com>
 <18754346.1REWN52J0K@flatron>
Message-ID: <CAD=FV=XiWET3Xptfk2CVWMw=xVCE4zUJhJtgXHbhiND12rJGnQ@mail.gmail.com>

Tomasz,

On Fri, May 17, 2013 at 1:34 PM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>> Slight nit to add this before the call to irq_domain_add_linear().
>> demv() will handle freeing your memory but nothing will handle undoing
>> the irq_domain_add_linear() if you return an error.
>
> I'm a bit sceptical when it is about error handling in such cases.
> Basically if interrupt initialization fails, something is seriously wrong,
> either with your kernel config or with some code.
>
> Since such case has been already unhandled in the driver (with nr_banks >
> 1 = always), so I didn't bother to add any undoing here.

Yeah, not all drivers handle it well.  I'm always surprised by the
number of drivers that seem have it right, though.  Certainly it seems
awfully unlikely that allocating a small number of bytes in a probe
function would fail.

...but changing the order doesn't hurt anything and would make it more
correct, even if it's not fully correct.


>> Optional: debug statements:
>>
>> pr_debug("%s:     con %#010x => %#010x\n", bank->name,
>>   readl(regs + EXYNOS_GPIO_ECON_OFFSET + bank->eint_offset),
>>   save->eint_con);
>> pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
>>   readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset),
>>   save->eint_fltcon0);
>> pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
>>   readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4),
>>   save->eint_fltcon1);
>
> OK. I wonder if this could be added in a separate patch or I should rather
> send v2 on Monday?

Definitely optional to add these, so up to you whether to spin the
patch, ignore my suggestion, or do a separate patch.  :)


Thanks for sending all of these up, by the way!  If things look good
next week I'll probably revert my local version of this (the V2 of my
original series) and pull in your series to keep us on the same page.
:)


-Doug


From linux at prisktech.co.nz  Fri May 17 17:18:51 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 09:18:51 +1200
Subject: [PATCH 3/4] clk: vt8500: Remove unnecessary divisor adjustment in
 vtwm_dclk_set_rate()
In-Reply-To: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368825532-30917-4-git-send-email-linux@prisktech.co.nz>

The divisor adjustment code to ensure that a divisor is not rounded down,
thereby giving a rate higher than requested, is unnecessary and in some
instances results in the actual rate being much lower than requested due to
rounding errors.

The test is already performed in vtwm_dclk_round_rate(), which is always
called when clk_set_rate is called. Due to rounding errors in the line:
divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up
adjusting the divisor twice - first in round_rate and then again in set_rate.

This patch removes the test/adjustment in vtwm_dclk_set_rate.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/clk/clk-vt8500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index ce401cf..82306f5 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -157,10 +157,6 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	divisor =  parent_rate / rate;
 
-	/* If prate / rate would be decimal, incr the divisor */
-	if (rate * divisor < parent_rate)
-		divisor++;
-
 	if (divisor == cdev->div_mask + 1)
 		divisor = 0;
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 17:18:49 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 09:18:49 +1200
Subject: [PATCH 1/4] clk: vt8500: Fix unbalanced spinlock in
 vt8500_dclk_set_rate()
In-Reply-To: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368825532-30917-2-git-send-email-linux@prisktech.co.nz>

With the addition of a DVO clock, a bug is now evident in the vt8500
clock code:
[    0.290000] WARNING: at init/main.c:698 do_one_initcall+0x158/0x18c()
[    0.300000] initcall wm8505fb_driver_init+0x0/0xc returned with disabled int

This is caused by an unbalanced spinlock in vt8500_dclk_set_rate().
Replace the second call to spin_lock_irqsave() with spin_unlock_irqrestore().

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/clk/clk-vt8500.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index debf688..553ac35 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 	writel(divisor, cdev->div_reg);
 	vt8500_pmc_wait_busy();
 
-	spin_lock_irqsave(cdev->lock, flags);
+	spin_unlock_irqrestore(cdev->lock, flags);
 
 	return 0;
 }
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 17:18:48 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 09:18:48 +1200
Subject: [PATCH 0/4] VT8500 clock for 3.10/3.11
Message-ID: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>

Hi Mike,

Patch #1 is a fix for 3.10 please - Due to an unbalanced spinlock in
vt8500_dclk_set_rate() we get kernel dumps on bootup.

Patch #2 adds support for the PLL clocks on WM8850 - originally it was thought
these were the same as WM8750, but with the release of vendor source it's now
confirmed to be different.

Patch #3 removes a check (which is also done in vt8500_dclk_round_rate) to
ensure the divisor is correct. Due to rounding errors, this usually results in
a lower than requested clock rate. Because round_rate is always called on all
our clocks, this test is actually redundant so I have dropped it.

Patch #4 is to add clk-vt8500.c to MAINTAINERS

Regards
Tony Prisk

Tony Prisk (4):
  clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()
  clk: vt8500: Add support for clocks on the WM8850 SoCs
  clk: vt8500: Remove unnecessary divisor adjustment in
    vtwm_dclk_set_rate()
  MAINTAINERS: vt8500: Add clk-vt8500.c to MAINTAINERS file

 Documentation/devicetree/bindings/clock/vt8500.txt |    2 +
 MAINTAINERS                                        |    1 +
 drivers/clk/clk-vt8500.c                           |   77 ++++++++++++++++++--
 3 files changed, 75 insertions(+), 5 deletions(-)

-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 17:18:52 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 09:18:52 +1200
Subject: [PATCH 4/4] MAINTAINERS: vt8500: Add clk-vt8500.c to MAINTAINERS file
In-Reply-To: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368825532-30917-5-git-send-email-linux@prisktech.co.nz>

This file has missed being added under ARM/VT8500 ARM ARCHITECTURE,
and is maintained along with the rest of the vt8500 arch code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 MAINTAINERS |    1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7782b..5ab8ccb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1283,6 +1283,7 @@ M:	Tony Prisk <linux at prisktech.co.nz>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-vt8500/
+F:	drivers/clk/vt8500-vt8500.c
 F:	drivers/clocksource/vt8500_timer.c
 F:	drivers/gpio/gpio-vt8500.c
 F:	drivers/mmc/host/wmt-sdmmc.c
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 17:18:50 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 09:18:50 +1200
Subject: [PATCH 2/4] clk: vt8500: Add support for clocks on the WM8850 SoCs
In-Reply-To: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368825532-30917-3-git-send-email-linux@prisktech.co.nz>

The WM8850 has a different PLL clock to the previous versions. This
patch adds support for the WM8850-style PLL clocks.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 Documentation/devicetree/bindings/clock/vt8500.txt |    2 +
 drivers/clk/clk-vt8500.c                           |   71 ++++++++++++++++++++
 2 files changed, 73 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
index a880c70..91d71cc 100644
--- a/Documentation/devicetree/bindings/clock/vt8500.txt
+++ b/Documentation/devicetree/bindings/clock/vt8500.txt
@@ -8,6 +8,8 @@ Required properties:
 - compatible : shall be one of the following:
 	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
 	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
+	"wm,wm8750-pll-clock" - for a WM8750 PLL clock
+	"wm,wm8850-pll-clock" - for a WM8850 PLL clock
 	"via,vt8500-device-clock" - for a VT/WM device clock
 
 Required properties for PLL clocks:
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 553ac35..ce401cf 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -42,6 +42,7 @@ struct clk_device {
 #define PLL_TYPE_VT8500		0
 #define PLL_TYPE_WM8650		1
 #define PLL_TYPE_WM8750		2
+#define PLL_TYPE_WM8850		3
 
 struct clk_pll {
 	struct clk_hw	hw;
@@ -327,6 +328,15 @@ CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
 #define WM8750_BITS_TO_VAL(f, m, d1, d2)				\
 		((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
 
+/* Helper macros for PLL_WM8850 */
+#define WM8850_PLL_MUL(x)	((((x >> 16) & 0x7F) + 1) * 2)
+#define WM8850_PLL_DIV(x)	((((x >> 8) & 1) + 1) * (1 << (x & 3)))
+
+#define WM8850_BITS_TO_FREQ(r, m, d1, d2)				\
+				(r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
+
+#define WM8850_BITS_TO_VAL(m, d1, d2)					\
+		((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
 
 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 				u32 *multiplier, u32 *prediv)
@@ -466,6 +476,49 @@ static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	*divisor2 = best_div2;
 }
 
+static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+				u32 *multiplier, u32 *divisor1, u32 *divisor2)
+{
+	u32 mul, div1, div2;
+	u32 best_mul, best_div1, best_div2;
+	unsigned long tclk, rate_err, best_err;
+
+	best_err = (unsigned long)-1;
+
+	/* Find the closest match (lower or equal to requested) */
+	for (div1 = 1; div1 >= 0; div1--)
+		for (div2 = 3; div2 >= 0; div2--)
+			for (mul = 0; mul <= 127; mul++) {
+				tclk = parent_rate * ((mul + 1) * 2) /
+						((div1 + 1) * (1 << div2));
+				if (tclk > rate)
+					continue;
+				/* error will always be +ve */
+				rate_err = rate - tclk;
+				if (rate_err == 0) {
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
+					return;
+				}
+
+				if (rate_err < best_err) {
+					best_err = rate_err;
+					best_mul = mul;
+					best_div1 = div1;
+					best_div2 = div2;
+				}
+			}
+
+	/* if we got here, it wasn't an exact match */
+	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
+							rate - best_err);
+
+	*multiplier = best_mul;
+	*divisor1 = best_div1;
+	*divisor2 = best_div2;
+}
+
 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 				unsigned long parent_rate)
 {
@@ -489,6 +542,10 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 		wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
 		pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
 		break;
+	case PLL_TYPE_WM8850:
+		wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
+		pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
+		break;
 	default:
 		pr_err("%s: invalid pll type\n", __func__);
 		return 0;
@@ -525,6 +582,10 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 		wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
 		round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
 		break;
+	case PLL_TYPE_WM8850:
+		wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
+		round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
+		break;
 	default:
 		round_rate = 0;
 	}
@@ -552,6 +613,10 @@ static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
 		pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
 		pll_freq /= WM8750_PLL_DIV(pll_val);
 		break;
+	case PLL_TYPE_WM8850:
+		pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
+		pll_freq /= WM8850_PLL_DIV(pll_val);
+		break;
 	default:
 		pll_freq = 0;
 	}
@@ -628,6 +693,12 @@ static void __init wm8750_pll_init(struct device_node *node)
 }
 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
 
+static void __init wm8850_pll_init(struct device_node *node)
+{
+	vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
+}
+CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
+
 void __init vtwm_clk_init(void __iomem *base)
 {
 	if (!base)
-- 
1.7.9.5



From davem at davemloft.net  Fri May 17 17:19:38 2013
From: davem at davemloft.net (David Miller)
Date: Fri, 17 May 2013 14:19:38 -0700 (PDT)
Subject: [PATCHv6 0/3] Add support for velocity network driver on
 platform devices
In-Reply-To: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
References: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <20130517.141938.2120801813213703422.davem@davemloft.net>


Series applied, thanks.


From maxime.ripard at free-electrons.com  Fri May 17 17:21:42 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 17 May 2013 23:21:42 +0200
Subject: [PATCH 2/2] Add sunxi-sid to dts for sun4i and sun5i
In-Reply-To: <1368797744-13737-3-git-send-email-oliver+list@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-3-git-send-email-oliver+list@schinagl.nl>
Message-ID: <51969F66.7080205@free-electrons.com>

Hi Oliver,

Le 17/05/2013 15:35, Oliver Schinagl a ?crit :
> From: Oliver Schinagl <oliver at schinagl.nl>
> 
> This should add support for the sunxi-sid driver to the device table for sun4i and sun5i

And it actually does :)

> 
> Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
> ---
>  arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++
>  arch/arm/boot/dts/sun5i-a13.dtsi | 5 +++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index e7ef619..1043db2 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -163,6 +163,11 @@
>  		reg = <0x01c20000 0x300000>;
>  		ranges;
>  
> +		sid: eeprom at 01c23800 {
> +			compatible = "allwinner,sun4i-sid";
> +			reg = <0x01c23800 0x10>;
> +		};
> +

I'd prefer to have the nodes sorted by base addresses.
Also, the reserved address space for this IP is 1kB, please make it as
such in the dt.

>  		intc: interrupt-controller at 01c20400 {
>  			compatible = "allwinner,sun4i-ic";
>  			reg = <0x01c20400 0x400>;
> diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
> index 8ba65c1..f715132 100644
> --- a/arch/arm/boot/dts/sun5i-a13.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
> @@ -153,6 +153,11 @@
>  		reg = <0x01c20000 0x300000>;
>  		ranges;
>  
> +		sid: eeprom at 01c23800 {
> +			compatible = "allwinner,sun4i-sid";
> +			reg = <0x01c23800 0x10>;
> +		};

Ditto,

> +
>  		intc: interrupt-controller at 01c20400 {
>  			compatible = "allwinner,sun4i-ic";
>  			reg = <0x01c20400 0x400>;
> 

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From yegorslists at googlemail.com  Fri May 17 17:28:53 2013
From: yegorslists at googlemail.com (Yegor Yefremov)
Date: Fri, 17 May 2013 23:28:53 +0200
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130517185620.GF28484@animalcreek.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com> <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de> <20130517185620.GF28484@animalcreek.com>
Message-ID: <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>

On Fri, May 17, 2013 at 8:56 PM, Mark A. Greer <mgreer at animalcreek.com> wrote:
> On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
>> On 15.05.2013 23:50, Mark A. Greer wrote:
>> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
>
>> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
>> >> idle states with?
>> >
>> > I have an am35xx which isn't supposed to have an IVA so I can test with it
>> > (although, I'm not sure how well the kernel works on the am35xx these days).
>> >
>> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
>> > comes up, see what I can figure out.
>>
>> I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
>> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
>>
>> I have such a system running, so if you have any other patches/ideas to test, I would do it.
>
> Yegor, since I've so far been unable to get my am3517evm to fire up, can
> you play around with the 3517 to see if there appears to be iva registers
> that can be read/written to safely?  In particular, can the code that idles
> the iva be run safely on an am3517?

I'll look into this next week. am3517 and IVA seems to be a really big
mystery. In the TI forum will be stated, there is no IVA:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/150961.aspx, but TRM
has various appearances of IVA2 registers, but no real
description/explanation of what is IVA and how to eat it.

Yegor


From sergei.shtylyov at cogentembedded.com  Fri May 17 18:23:37 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Sat, 18 May 2013 02:23:37 +0400
Subject: [PATCH v2 2/3] ARM: shmobile: lager: enable Ether
In-Reply-To: <519235D7.1050706@cogentembedded.com>
References: <1368499171-22427-1-git-send-email-horms+renesas@verge.net.au>
 <1368499171-22427-3-git-send-email-horms+renesas@verge.net.au>
 <9708378.xkqng7A9dx@avalon> <519235D7.1050706@cogentembedded.com>
Message-ID: <5196ADE9.2080308@cogentembedded.com>

Hello.

On 05/14/2013 05:02 PM, Sergei Shtylyov wrote:

>
>>> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
>>> Cc: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>
>> Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
>
>> Is there any ongoing work on DT bindings for sh-eth ?
>
>    At least there was -- by Nobuhiro Iwamatsu. I don't think 
> converting platform data to DT properties makes sense since sh_eth 
> have some procedural platform data. I also don't think working on DT 
> makes sense until the driver is cleaned up of all its #ifdef'ery (that 
> work is partly being done by Nobuhiro and I'm planning to start the 
> big #ifdef cleanup this week).

     Alas, not this week apparently as my management has shifted 
priorities thrice this week. So maybe late next week now...

WBR, Sergei



From swarren at wwwdotorg.org  Fri May 17 18:50:45 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 16:50:45 -0600
Subject: [GIT PULL] ARM: tegra: DT-related fixes needed by the USB tree
Message-ID: <1368831045-19105-1-git-send-email-swarren@wwwdotorg.org>

Felipe, (and Alan, Greg),

These are the changes from the Tegra tree that need to be merged
before the Tegra USB driver patches 4-8 from Venu can be applied. Recall
that we had previously agreed on this approach for v3.9, but Venu's
patches didn't end up being ready until now, unfortunately. I note
that Venu's patches affect both the Tegra USB and PHY drivers.

Following this, I will soon send some patches that fix up some ARM multi-
platform issues in the Tegra EHCI driver. Those won't affect the Tegra
USB PHY driver, but I do expect I'll want to rebase them on top of Venu's
series, since they will probably interact a bit with Venu's patches.

I also soon hope to see patches to:
* Convert the Tegra USB and PHY drivers from the vbus-gpios DT property
  to the new vbus-supply regulator. This will affect both drivers, and
  I really hope will happen soon.
* Add support for Tegra30 and Tegra114 SoCs. I expect this would touch
  both the USB and PHY drivers. This may or may not happen in 3.11.

As such, there will be quite a lot of interaction between the Tegra USB
and PHY drivers in 3.10. I'll let you decide if it's better for them to
go through the main USB tree or the USB PHY tree, and hence who should
pull in this pull request.

----------------------------------------------------------------

Tag description:

The Tegra USB bindings were in bad shape. The patches in this branch
fix the binding definitions, and make all the necessary additions to
the DT files. Stale nodes/properties will be removed early in 3.12
once the USB driver has been updated for the new binding.

These changes are needed in both the USB tree, to allow the driver to
be updated to handle them, and the Tegra tree, so that various tree-
wide DT changes (e.g. conversion of IRQ/GPIO/clock constants to defines)
can be applied on top of them.

----------------------------------------------------------------

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tegra-for-3.11-deps-for-usb

for you to fetch changes up to 4c94c8b5b3cc38b0d0b1ec79642f5710e19a3e01:

  ARM: tegra: update device trees for USB binding rework

----------------------------------------------------------------

Venu Byravarasu (3):
      ARM: tegra: finalize USB EHCI and PHY bindings
      ARM: tegra: modify ULPI reset GPIO properties
      ARM: tegra: update device trees for USB binding rework

 .../bindings/usb/nvidia,tegra20-ehci.txt        |   27 ++--------
 .../bindings/usb/nvidia,tegra20-usb-phy.txt     |   41 +++++++++++++--
 arch/arm/boot/dts/tegra20-colibri-512.dtsi      |    6 ++-
 arch/arm/boot/dts/tegra20-harmony.dts           |   15 ++++--
 arch/arm/boot/dts/tegra20-iris-512.dts          |    9 +++-
 arch/arm/boot/dts/tegra20-paz00.dts             |   15 ++++--
 arch/arm/boot/dts/tegra20-seaboard.dts          |   26 ++++++++--
 arch/arm/boot/dts/tegra20-tamonten.dtsi         |    4 ++
 arch/arm/boot/dts/tegra20-trimslice.dts         |   25 +++++++--
 arch/arm/boot/dts/tegra20-ventana.dts           |   15 ++++--
 arch/arm/boot/dts/tegra20-whistler.dts          |   28 ++++++++++
 arch/arm/boot/dts/tegra20.dtsi                  |   49 +++++++++++++-----
 12 files changed, 206 insertions(+), 54 deletions(-)


From swarren at wwwdotorg.org  Fri May 17 18:54:49 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 16:54:49 -0600
Subject: [PATCH] clk: tegra: Use common of_clk_init() function
In-Reply-To: <1365066351-2395-1-git-send-email-pgaikwad@nvidia.com>
References: <1365066351-2395-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <5196B539.4040708@wwwdotorg.org>

On 04/04/2013 03:05 AM, Prashant Gaikwad wrote:
> Use common of_clk_init() function for clocks initialization.

Prashant, can you please resend this to Mike for inclusion in 3.11; now
that we have moved the Tegra clock driver out of arch/arm/mach-tegra, we
should send all clock driver changes through Mike if possible. Thanks.

Just one question though:

> diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c

> -#include <linux/clk/tegra.h>
> +#include <linux/clk-provider.h>

Is clk-provider.h the right header? This code isn't a clock provider?


From swarren at wwwdotorg.org  Fri May 17 19:52:29 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:52:29 -0600
Subject: [PATCH 1/1] ARM: DT: tegra: Add gpio-leds to Tegra30 Beaver
In-Reply-To: <1368232829-25716-1-git-send-email-ebrower@nvidia.com>
References: <1368232829-25716-1-git-send-email-ebrower@nvidia.com>
Message-ID: <5196C2BD.4040709@wwwdotorg.org>

On 05/10/2013 06:40 PM, Eric Brower wrote:
> Add support for general-purpose LEDs present on Beaver

I've applied this to Tegra's for-3.11/dt branch. When applying, I moved
the newly added node to maintain the node sort order.


From swarren at wwwdotorg.org  Fri May 17 19:53:45 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:53:45 -0600
Subject: [PATCH] ARM: tegra: add various LED triggers to defconfig
In-Reply-To: <1368834690-1174-1-git-send-email-swarren@wwwdotorg.org>
References: <1368834690-1174-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <5196C309.5000903@wwwdotorg.org>

On 05/17/2013 05:51 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> A couple of Tegra boards have gpio-leds present. Enable various trigger
> options to make those useful. This sets all the trigger options to their
> "if you don't know, say X" value.

I have applied this to (squashed it into) Tegra's for-3.11/defconfig branch.


From swarren at wwwdotorg.org  Fri May 17 19:54:40 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:54:40 -0600
Subject: [PATCH 2/2] ARM: tegra: dts: dalmore: enable spi4
In-Reply-To: <1365594483-20651-2-git-send-email-ldewangan@nvidia.com>
References: <1365594483-20651-1-git-send-email-ldewangan@nvidia.com>
 <1365594483-20651-2-git-send-email-ldewangan@nvidia.com>
Message-ID: <5196C340.2080706@wwwdotorg.org>

On 04/10/2013 05:48 AM, Laxman Dewangan wrote:
> Enable SPI4 and add Winbond SPI flash W25Q32DW device
> on CS0 line.

I have applied this to Tegra's for-3.11/dt branch.


From swarren at wwwdotorg.org  Fri May 17 19:54:50 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:54:50 -0600
Subject: [PATCH 1/2] ARM: config: tegra: enable T114 SPI
In-Reply-To: <1365594483-20651-1-git-send-email-ldewangan@nvidia.com>
References: <1365594483-20651-1-git-send-email-ldewangan@nvidia.com>
Message-ID: <5196C34A.9000303@wwwdotorg.org>

On 04/10/2013 05:48 AM, Laxman Dewangan wrote:
> Nvidia Tegra114 has the new spi controller whose driver
> is not compatible with older SoCs. The new driver is added
> for Tegra114 spi controller.

I have applied this to (squashed it into) Tegra's for-3.11/defconfig branch.


From swarren at wwwdotorg.org  Fri May 17 19:55:24 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:55:24 -0600
Subject: [PATCH] ARM: tegra: fix memory size on Beaver
In-Reply-To: <1368474451-11176-1-git-send-email-swarren@wwwdotorg.org>
References: <1368474451-11176-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <5196C36C.8020103@wwwdotorg.org>

On 05/13/2013 01:47 PM, Stephen Warren wrote:
> Tegra30's boot ROM masks the top 1MiB of RAM. Fix the memory node in
> Beaver's DT file to reflect this.

I have applied this to Tegra's for-3.11/dt branch.


From swarren at wwwdotorg.org  Fri May 17 19:57:38 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:57:38 -0600
Subject: [PATCH] ARM: tegra: Add charger subnode to tps65090 node
In-Reply-To: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
References: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
Message-ID: <5196C3F2.8070204@wwwdotorg.org>

On 04/10/2013 01:51 PM, Rhyland Klein wrote:
> The charger is now represented by a distinct subnode of the tps65090
> device. Add this node and enable low current charging with it.

What's the status of the TPS60590 bindings; are they agreed upon by
NVIDIA, TI, and SlimLogic yet? In other words, is this patch still
something I should apply for 3.11, or does it need to be reworked?


From swarren at wwwdotorg.org  Fri May 17 19:51:30 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 May 2013 17:51:30 -0600
Subject: [PATCH] ARM: tegra: add various LED triggers to defconfig
Message-ID: <1368834690-1174-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

A couple of Tegra boards have gpio-leds present. Enable various trigger
options to make those useful. This sets all the trigger options to their
"if you don't know, say X" value.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/configs/tegra_defconfig |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8a50fc8..ea2869c 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -190,7 +190,13 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
-- 
1.7.10.4



From davem at davemloft.net  Fri May 17 20:36:44 2013
From: davem at davemloft.net (David Miller)
Date: Fri, 17 May 2013 17:36:44 -0700 (PDT)
Subject: [PATCHv6 0/3] Add support for velocity network driver on
 platform devices
In-Reply-To: <20130517.141938.2120801813213703422.davem@davemloft.net>
References: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
 <20130517.141938.2120801813213703422.davem@davemloft.net>
Message-ID: <20130517.173644.1877140985770026320.davem@davemloft.net>

From: David Miller <davem at davemloft.net>
Date: Fri, 17 May 2013 14:19:38 -0700 (PDT)

> 
> Series applied, thanks.

I'm reverting this, you're not using the correct types for the PM
functions you're hooking up.

drivers/net/ethernet/via/via-velocity.c:3238:8: warning: initialization from incompatible pointer type [enabled by default]
drivers/net/ethernet/via/via-velocity.c:3238:8: warning: (near initialization for ?velocity_pm_ops.suspend?) [enabled by default]
drivers/net/ethernet/via/via-velocity.c:3238:8: warning: initialization from incompatible pointer type [enabled by default]
drivers/net/ethernet/via/via-velocity.c:3238:8: warning: (near initialization for ?velocity_pm_ops.freeze?) [enabled by default]
drivers/net/ethernet/via/via-velocity.c:3238:8: warning: initialization from incompatible pointer type [enabled by default]
drivers/net/ethernet/via/via-velocity.c:3238:8: warning: (near initialization for ?velocity_pm_ops.poweroff?) [enabled by default]

From anton at enomsg.org  Fri May 17 19:55:53 2013
From: anton at enomsg.org (Anton Vorontsov)
Date: Fri, 17 May 2013 16:55:53 -0700
Subject: [PATCH 3/3] ARM: versatile: Make able to use UART ports for KGDB
 FIQ debugger
In-Reply-To: <20130510161710.45b18866@skate>
References: <1368144651-11250-1-git-send-email-john.stultz@linaro.org>
 <1368144651-11250-4-git-send-email-john.stultz@linaro.org>
 <20130510161710.45b18866@skate>
Message-ID: <20130517235553.GA6137@teo>

Thanks a lot for the review, Thomas!

On Fri, May 10, 2013 at 04:17:10PM +0200, Thomas Petazzoni wrote:
[...]
> > +{
> > +	return readl(kgdb_irq_base + VIC_FIQ_STATUS) & (1 << kgdb_irq);
> > +}
> > +
> > +static int __init kgdb_fiq_init(void)
> > +{
> > +	kgdb_irq_base = __io_address(VERSATILE_VIC_BASE);
> > +	kgdb_irq += INT_UARTINT0;
> > +	WARN_ON(kgdb_irq > INT_UARTINT2);
> > +
> > +	return kgdb_register_fiq(kgdb_fiq_select, kgdb_is_fiq_rised);
> > +}
> > +console_initcall(kgdb_fiq_init);
> 
> Also, this code that uses hardcoded addresses and IRQ numbers doesn't
> seem to play really well with the DT. I was considering toying around
> with this thing on the mach-mvebu platform, but don't have those
> hardcoded addresses and IRQs, and the register offsets of the IRQ
> controller driver are not exposed in an header file. Shouldn't IRQ
> controller driver be exposing a the fiq_select() functionality instead?
> Like a new flag for irq_chip->irq_set_type(), or a completely new hook
> irq_chip->irq_set_mode() or something like that?

FIQs are very specific to the platform, and I doubt that anyone will be
happy in exposing this kind of knowledge to the generic subsystem.

Moreover, Russell King once said that we should better detach IRQ stuff
from FIQs altogether. Thing is, FIQs are not going through the generic IRQ
code flow, so there is actually very little point in managing them thru
the generic IRQ subsystem.

What seems more plausible is making a "FIQ subsystem", and register each
IRQ controller that can redirect its sources to FIQ with that new
subsystem. But the "subsystem" isn't there, and even doing some cleanups
in this core stuff takes forever to review/make decision. :) Plus, writing
it for this small thing seems like a bit of overhead.

And if you take a closer look at this patch, it actually does not use IRQ
numbers with the IRQ subsystem. Instead, it bypasses the whole thing and
writes to the VIC registers directly.

So, for your case (if you want to use FIQ debugger on your board), I would
suggest doing the same. At least until we figure out how to do these ten
lines of board-specific code better (ideas/hints are welcome! :)

Thanks!

Anton


From shawn.guo at linaro.org  Fri May 17 21:07:09 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 18 May 2013 09:07:09 +0800
Subject: [PATCH] ARM: dts: apf28dev: Add touchscreen support for APF28dev
In-Reply-To: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
References: <1368767622-12968-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
Message-ID: <20130518010707.GA18471@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 07:13:41AM +0200, Gwenhael Goavec-Merou wrote:
> 
> Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>

Applied, thanks.

> ---
>  arch/arm/boot/dts/imx28-apf28dev.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
> index 3d905d1..b602494 100644
> --- a/arch/arm/boot/dts/imx28-apf28dev.dts
> +++ b/arch/arm/boot/dts/imx28-apf28dev.dts
> @@ -103,6 +103,7 @@
>  
>  		apbx at 80040000 {
>  			lradc at 80050000 {
> +				fsl,lradc-touchscreen-wires = <4>;
>  				status = "okay";
>  			};
>  
> -- 
> 1.8.1.5
> 



From shawn.guo at linaro.org  Fri May 17 21:27:28 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 18 May 2013 09:27:28 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <1368684648-20826-3-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-3-git-send-email-b35083@freescale.com>
Message-ID: <20130518012726.GA18553@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:10:46PM +0800, Jingchang Lu wrote:
> +static void __init mvf600_init_irq(void)
> +{
> +	struct device_node *np;
> +	void __iomem *mscm_base;
> +	int i;
> +
> +	l2x0_of_init(0, ~0UL);
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm");
> +	mscm_base = of_iomap(np, 0);
> +	if (!mscm_base)
> +		return;
> +
> +	/* route all shared peripheral interrupts to CP0 */
> +	for (i = 0; i < 111; i++)
> +		__raw_writew(1, mscm_base + 0x880 + 2 * i);

I second Arnd's comment on this.  Can we have this setup done in
bootloader?

Shawn

> +
> +	iounmap(mscm_base);
> +
> +	irqchip_init();
> +}



From viresh.kumar at linaro.org  Fri May 17 22:03:48 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sat, 18 May 2013 07:33:48 +0530
Subject: spurious bL cpufreq driver messages
In-Reply-To: <519686BC.3090101@gmail.com>
References: <519686BC.3090101@gmail.com>
Message-ID: <CAKohpom0cGfWvsCf-jaMyu0cQJi2hVk9_0wskEDH2X7MaeHDLw@mail.gmail.com>

On 18 May 2013 01:06, Rob Herring <robherring2 at gmail.com> wrote:
> The bL cpufreq driver appears to collide with the cpufreq-cpu0 driver.
> There doesn't appear to be a functional problem, but just spurious
> prints which indicate it is trying to do something. I think it needs
> better checking whether the chip is actually multi-cluster. This is what
> I get when I hotplug cpus:
>
> [  909.372319] CPU1: Booted secondary processor
> [  909.372616] cpu cpu1: get_cluster_clk_and_freq_table: init_opp_table
> failed, cpu: 1, err: -61
> [  909.385411] cpu cpu1: get_cluster_clk_and_freq_table: Failed to get
> data for cluster: 9
> [  909.394161] CPU2: shutdown
> [  909.400957] CPU2: Booted secondary processor
> [  909.401253] cpu cpu2: get_cluster_clk_and_freq_table: init_opp_table
> failed, cpu: 2, err: -61
> [  909.414044] cpu cpu2: get_cluster_clk_and_freq_table: Failed to get
> data for cluster: 9

See if this fixes your issue.

https://groups.google.com/forum/?fromgroups#!topic/linux.kernel/XJF-82rad4o

Attached too.
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From linux at prisktech.co.nz  Fri May 17 22:22:57 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 14:22:57 +1200
Subject: [PATCHv6 0/3] Add support for velocity network driver on platform
 devices
In-Reply-To: <20130517.173644.1877140985770026320.davem@davemloft.net>
References: <1368768078-16121-1-git-send-email-linux@prisktech.co.nz>
 <20130517.141938.2120801813213703422.davem@davemloft.net>
 <20130517.173644.1877140985770026320.davem@davemloft.net>
Message-ID: <5196E601.10202@prisktech.co.nz>

On 18/05/13 12:36, David Miller wrote:
> From: David Miller <davem at davemloft.net>
> Date: Fri, 17 May 2013 14:19:38 -0700 (PDT)
>
>> Series applied, thanks.
> I'm reverting this, you're not using the correct types for the PM
> functions you're hooking up.
>
> drivers/net/ethernet/via/via-velocity.c:3238:8: warning: initialization from incompatible pointer type [enabled by default]
> drivers/net/ethernet/via/via-velocity.c:3238:8: warning: (near initialization for ?velocity_pm_ops.suspend?) [enabled by default]
> drivers/net/ethernet/via/via-velocity.c:3238:8: warning: initialization from incompatible pointer type [enabled by default]
> drivers/net/ethernet/via/via-velocity.c:3238:8: warning: (near initialization for ?velocity_pm_ops.freeze?) [enabled by default]
> drivers/net/ethernet/via/via-velocity.c:3238:8: warning: initialization from incompatible pointer type [enabled by default]
> drivers/net/ethernet/via/via-velocity.c:3238:8: warning: (near initialization for ?velocity_pm_ops.poweroff?) [enabled by default]
Argh.. sorry Dave.
I forgot to merge the fixup for this before sending. Fixed version to 
follow.

Regards
Tony P


From linux at prisktech.co.nz  Fri May 17 22:23:42 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 14:23:42 +1200
Subject: [PATCHv7 0/3] Add support for velocity network driver on platform
 devices
Message-ID: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>

v7 changes:
Forgot to merge a patch to fix an error with the pm ops changes. Apologies Dave.

v6 changes:
Remove more bus specific code from velocity_probe()
Make velocity_(suspend/resume) accept a struct device *
Simplify PM code to use velocity_(suspend/resume) - remove the individual
pci and platform functions.
Add a struct pci_dev variable to velocity_get_pci_info() to reduce churn

v5 changes:
Remove velocity_info union. Change velocity_info->pdev back to struct pci_dev.
Remove more 'if (pci)' sections.
Remove 'void *pdev' function parameters.
Pass correct variable to velocity_choose_state()

v4 changes:
Code tidyup as requested by Francois Romieu
Removed '#ifdef PCI' around PCI code. Compile tested on (!)PCI and (!)PM.

v3 changes:
Rebased against net-next.
Fix errors in pm code.

v2 changes:
Drop patch #1 as requested by David Miller.
Correct the PHYID_ICPLUS_IP101A MII bits - should be ON, rather than OFF.
Read the platform rev_id from the correct register [regs->rev_id]. It's possible
this would work for the PCI version as well and would remove the need for the
'if (pci)' test to set vptr->rev_id.

v1:
The first three patches are general tidyup.

[DROPPED] Patch ## just alphabetizes the #includes to make it easier to read.

Patch #1 replaces vptr->dev with vptr->netdev, in preparation of adding a
struct device *dev in Patch #2

Patch #2 replaces the pci dma functions with the generic versions.

I have build tested these patches but don't have a PCI velocity to run-test it.
I can't see that they should introduce any problems as it is all renames and
function swapping.

Patch #3 adds support for the velocity driver on devicetree platform devices.
Binding document included. This patch is compile-tested for PCI, and boot
tested on a VIA APC8750.

I think it would be pertinent to get some tested-by's for PCI users.

Regards
Tony Prisk


Tony Prisk (3):
  net: velocity: Rename vptr->dev to vptr->netdev
  net: velocity: Convert to generic dma functions
  net: velocity: Add platform device support to VIA velocity driver

 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  496 +++++++++++++-------
 drivers/net/ethernet/via/via-velocity.h            |   35 +-
 4 files changed, 376 insertions(+), 178 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 22:23:44 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 14:23:44 +1200
Subject: [PATCHv7 2/3] net: velocity: Convert to generic dma functions
In-Reply-To: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
References: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368843825-14813-3-git-send-email-linux@prisktech.co.nz>

Remove the pci_* dma functions and replace with the more generic
versions.

In preparation of adding platform support, a new struct device *dev
is added to struct velocity_info which can be used by both the pci
and platform code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   51 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    1 +
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 187eef3..5996cee 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -46,6 +46,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 #include <linux/init.h>
+#include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
@@ -1459,7 +1460,6 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	struct velocity_opt *opt = &vptr->options;
 	const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
 	const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
-	struct pci_dev *pdev = vptr->pdev;
 	dma_addr_t pool_dma;
 	void *pool;
 	unsigned int i;
@@ -1467,13 +1467,13 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	/*
 	 * Allocate all RD/TD rings a single pool.
 	 *
-	 * pci_alloc_consistent() fulfills the requirement for 64 bytes
+	 * dma_alloc_coherent() fulfills the requirement for 64 bytes
 	 * alignment
 	 */
-	pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
-				    rx_ring_size, &pool_dma);
+	pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
+				    rx_ring_size, &pool_dma, GFP_ATOMIC);
 	if (!pool) {
-		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
+		dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
 			vptr->netdev->name);
 		return -ENOMEM;
 	}
@@ -1524,8 +1524,8 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	 */
 	skb_reserve(rd_info->skb,
 			64 - ((unsigned long) rd_info->skb->data & 63));
-	rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
-					vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
+					vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Fill in the descriptor to match
@@ -1588,8 +1588,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr)
 
 		if (!rd_info->skb)
 			continue;
-		pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-				 PCI_DMA_FROMDEVICE);
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
 		rd_info->skb_dma = 0;
 
 		dev_kfree_skb(rd_info->skb);
@@ -1670,7 +1670,7 @@ static void velocity_free_dma_rings(struct velocity_info *vptr)
 	const int size = vptr->options.numrx * sizeof(struct rx_desc) +
 		vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
 
-	pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
+	dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
 }
 
 static int velocity_init_rings(struct velocity_info *vptr, int mtu)
@@ -1727,8 +1727,8 @@ static void velocity_free_tx_buf(struct velocity_info *vptr,
 				pktlen = max_t(size_t, pktlen,
 						td->td_buf[i].size & ~TD_QUEUE);
 
-			pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
-					le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
+			dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
+					le16_to_cpu(pktlen), DMA_TO_DEVICE);
 		}
 	}
 	dev_kfree_skb_irq(skb);
@@ -1750,8 +1750,8 @@ static void velocity_free_td_ring_entry(struct velocity_info *vptr,
 	if (td_info->skb) {
 		for (i = 0; i < td_info->nskb_dma; i++) {
 			if (td_info->skb_dma[i]) {
-				pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
-					td_info->skb->len, PCI_DMA_TODEVICE);
+				dma_unmap_single(vptr->dev, td_info->skb_dma[i],
+					td_info->skb->len, DMA_TO_DEVICE);
 				td_info->skb_dma[i] = 0;
 			}
 		}
@@ -2029,7 +2029,6 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
  */
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
-	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
 	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
@@ -2047,8 +2046,8 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 
 	skb = rd_info->skb;
 
-	pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
-				    vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
+				    vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Drop frame not meeting IEEE 802.3
@@ -2061,19 +2060,18 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		}
 	}
 
-	pci_action = pci_dma_sync_single_for_device;
-
 	velocity_rx_csum(rd, skb);
 
 	if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
 		velocity_iph_realign(vptr, skb, pkt_len);
-		pci_action = pci_unmap_single;
 		rd_info->skb = NULL;
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
+	} else {
+		dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
+					   vptr->rx.buf_sz, DMA_FROM_DEVICE);
 	}
 
-	pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-		   PCI_DMA_FROMDEVICE);
-
 	skb_put(skb, pkt_len - 4);
 	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
@@ -2550,7 +2548,8 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	 *	add it to the transmit ring.
 	 */
 	tdinfo->skb = skb;
-	tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+	tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
+								DMA_TO_DEVICE);
 	td_ptr->tdesc0.len = cpu_to_le16(pktlen);
 	td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
 	td_ptr->td_buf[0].pa_high = 0;
@@ -2560,7 +2559,7 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
-		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(&vptr->pdev->dev,
+		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
 							  frag, 0,
 							  skb_frag_size(frag),
 							  DMA_TO_DEVICE);
@@ -2637,6 +2636,7 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
 {
 	memset(vptr, 0, sizeof(struct velocity_info));
 
+	vptr->dev = &pdev->dev;
 	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
@@ -2744,7 +2744,6 @@ static int velocity_found1(struct pci_dev *pdev,
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	vptr = netdev_priv(dev);
 
-
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
 			VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index ff8d7828..c38bbae 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1434,6 +1434,7 @@ struct velocity_opt {
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
 struct velocity_info {
+	struct device *dev;
 	struct pci_dev *pdev;
 	struct net_device *netdev;
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 22:23:43 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 14:23:43 +1200
Subject: [PATCHv7 1/3] net: velocity: Rename vptr->dev to vptr->netdev
In-Reply-To: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
References: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368843825-14813-2-git-send-email-linux@prisktech.co.nz>

Improve the clarity of the code in preparation for converting the
dma functions to generic versions, which require a struct device *.

This makes it possible to store a 'struct device *dev' in the
velocity_info structure.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   66 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    4 +-
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index fb62489..187eef3 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -998,9 +998,9 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 {
 
 	if (vptr->mii_status & VELOCITY_LINK_FAIL) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
 	} else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
 
 		if (vptr->mii_status & VELOCITY_SPEED_1000)
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
@@ -1014,7 +1014,7 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 		else
 			VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
 	} else {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
 		switch (vptr->options.spd_dpx) {
 		case SPD_DPX_1000_FULL:
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
@@ -1319,7 +1319,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 	case VELOCITY_INIT_RESET:
 	case VELOCITY_INIT_WOL:
 
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/*
 		 *	Reset RX to prevent RX pointer not on the 4X location
@@ -1332,7 +1332,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1354,7 +1354,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 
 		mac_eeprom_reload(regs);
 		for (i = 0; i < 6; i++)
-			writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -1377,7 +1377,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		/*
 		 *	Set packet filter: Receive directed and broadcast address
 		 */
-		velocity_set_multi(vptr->dev);
+		velocity_set_multi(vptr->netdev);
 
 		/*
 		 *	Enable MII auto-polling
@@ -1404,14 +1404,14 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
 
 		mii_status = velocity_get_opt_media_mode(vptr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		mii_init(vptr, mii_status);
 
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1474,7 +1474,7 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 				    rx_ring_size, &pool_dma);
 	if (!pool) {
 		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
-			vptr->dev->name);
+			vptr->netdev->name);
 		return -ENOMEM;
 	}
 
@@ -1514,7 +1514,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 
-	rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx.buf_sz + 64);
+	rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
 	if (rd_info->skb == NULL)
 		return -ENOMEM;
 
@@ -1620,7 +1620,7 @@ static int velocity_init_rd_ring(struct velocity_info *vptr)
 
 	if (velocity_rx_refill(vptr) != vptr->options.numrx) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
-			"%s: failed to allocate RX buffer.\n", vptr->dev->name);
+			"%s: failed to allocate RX buffer.\n", vptr->netdev->name);
 		velocity_free_rd_ring(vptr);
 		goto out;
 	}
@@ -1809,7 +1809,7 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
 		BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
 		writew(TRDCSR_RUN, &regs->TDCSRClr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/* FIXME: port over the pci_device_failed code and use it
 		   here */
@@ -1850,10 +1850,10 @@ static void velocity_error(struct velocity_info *vptr, int status)
 
 		if (linked) {
 			vptr->mii_status &= ~VELOCITY_LINK_FAIL;
-			netif_carrier_on(vptr->dev);
+			netif_carrier_on(vptr->netdev);
 		} else {
 			vptr->mii_status |= VELOCITY_LINK_FAIL;
-			netif_carrier_off(vptr->dev);
+			netif_carrier_off(vptr->netdev);
 		}
 
 		velocity_print_link_status(vptr);
@@ -1867,9 +1867,9 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		enable_mii_autopoll(regs);
 
 		if (vptr->mii_status & VELOCITY_LINK_FAIL)
-			netif_stop_queue(vptr->dev);
+			netif_stop_queue(vptr->netdev);
 		else
-			netif_wake_queue(vptr->dev);
+			netif_wake_queue(vptr->netdev);
 
 	}
 	if (status & ISR_MIBFI)
@@ -1894,7 +1894,7 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	int idx;
 	int works = 0;
 	struct velocity_td_info *tdinfo;
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 
 	for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
 		for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
@@ -1939,9 +1939,9 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	 *	Look to see if we should kick the transmit network
 	 *	layer for more work.
 	 */
-	if (netif_queue_stopped(vptr->dev) && (full == 0) &&
+	if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
 	    (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
-		netif_wake_queue(vptr->dev);
+		netif_wake_queue(vptr->netdev);
 	}
 	return works;
 }
@@ -1989,7 +1989,7 @@ static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
 	if (pkt_size < rx_copybreak) {
 		struct sk_buff *new_skb;
 
-		new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
+		new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
 		if (new_skb) {
 			new_skb->ip_summed = rx_skb[0]->ip_summed;
 			skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
@@ -2030,14 +2030,14 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
 	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
 	struct sk_buff *skb;
 
 	if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
-		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->netdev->name);
 		stats->rx_length_errors++;
 		return -EINVAL;
 	}
@@ -2075,7 +2075,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		   PCI_DMA_FROMDEVICE);
 
 	skb_put(skb, pkt_len - 4);
-	skb->protocol = eth_type_trans(skb, vptr->dev);
+	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
 	if (rd->rdesc0.RSR & RSR_DETAG) {
 		u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
@@ -2100,7 +2100,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
  */
 static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
 {
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	int rd_curr = vptr->rx.curr;
 	int works = 0;
 
@@ -2292,7 +2292,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 	if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
-				vptr->dev->name);
+				vptr->netdev->name);
 		ret = -EINVAL;
 		goto out_0;
 	}
@@ -2314,7 +2314,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 			goto out_0;
 		}
 
-		tmp_vptr->dev = dev;
+		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
@@ -2692,7 +2692,7 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
  */
 static void velocity_print_info(struct velocity_info *vptr)
 {
-	struct net_device *dev = vptr->dev;
+	struct net_device *dev = vptr->netdev;
 
 	printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
 	printk(KERN_INFO "%s: Ethernet Address: %pM\n",
@@ -2755,7 +2755,7 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	velocity_init_info(pdev, vptr, info);
 
-	vptr->dev = dev;
+	vptr->netdev = dev;
 
 	ret = pci_enable_device(pdev);
 	if (ret < 0)
@@ -3010,10 +3010,10 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	struct velocity_info *vptr = netdev_priv(dev);
 	unsigned long flags;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
-	netif_device_detach(vptr->dev);
+	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
 	pci_save_state(pdev);
@@ -3078,7 +3078,7 @@ static int velocity_resume(struct pci_dev *pdev)
 	unsigned long flags;
 	int i;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
 	pci_set_power_state(pdev, PCI_D0);
@@ -3101,7 +3101,7 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	mac_enable_int(vptr->mac_regs);
 	spin_unlock_irqrestore(&vptr->lock, flags);
-	netif_device_attach(vptr->dev);
+	netif_device_attach(vptr->netdev);
 
 	return 0;
 }
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index 4cb9f13..ff8d7828 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1435,7 +1435,7 @@ struct velocity_opt {
 
 struct velocity_info {
 	struct pci_dev *pdev;
-	struct net_device *dev;
+	struct net_device *netdev;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
@@ -1514,7 +1514,7 @@ static inline int velocity_get_ip(struct velocity_info *vptr)
 	int res = -ENOENT;
 
 	rcu_read_lock();
-	in_dev = __in_dev_get_rcu(vptr->dev);
+	in_dev = __in_dev_get_rcu(vptr->netdev);
 	if (in_dev != NULL) {
 		ifa = (struct in_ifaddr *) in_dev->ifa_list;
 		if (ifa != NULL) {
-- 
1.7.9.5



From linux at prisktech.co.nz  Fri May 17 22:23:45 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 14:23:45 +1200
Subject: [PATCHv7 3/3] net: velocity: Add platform device support to VIA
 velocity driver
In-Reply-To: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
References: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368843825-14813-4-git-send-email-linux@prisktech.co.nz>

Add support for the VIA Velocity network driver to be bound to a
OF created platform device.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  387 ++++++++++++++------
 drivers/net/ethernet/via/via-velocity.h            |   32 +-
 4 files changed, 320 insertions(+), 122 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

diff --git a/Documentation/devicetree/bindings/net/via-velocity.txt b/Documentation/devicetree/bindings/net/via-velocity.txt
new file mode 100644
index 0000000..b3db469
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/via-velocity.txt
@@ -0,0 +1,20 @@
+* VIA Velocity 10/100/1000 Network Controller
+
+Required properties:
+- compatible : Should be "via,velocity-vt6110"
+- reg : Address and length of the io space
+- interrupts : Should contain the controller interrupt line
+
+Optional properties:
+- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
+	devices quite often set this data in uboot and do not provide an eeprom.
+	Specify this option if you have no external eeprom.
+
+Examples:
+
+eth0 at d8004000 {
+	compatible = "via,velocity-vt6110";
+	reg = <0xd8004000 0x400>;
+	interrupts = <10>;
+	no-eeprom;
+};
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
index 68a9ba6..6a87097 100644
--- a/drivers/net/ethernet/via/Kconfig
+++ b/drivers/net/ethernet/via/Kconfig
@@ -5,7 +5,6 @@
 config NET_VENDOR_VIA
 	bool "VIA devices"
 	default y
-	depends on PCI
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y
 	  and read the Ethernet-HOWTO, available from
@@ -45,7 +44,7 @@ config VIA_RHINE_MMIO
 
 config VIA_VELOCITY
 	tristate "VIA Velocity support"
-	depends on PCI
+	depends on (PCI || USE_OF)
 	select CRC32
 	select CRC_CCITT
 	select NET_CORE
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 5996cee..d8d5bc5 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -65,7 +65,11 @@
 #include <linux/if.h>
 #include <linux/uaccess.h>
 #include <linux/proc_fs.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
 #include <linux/inetdevice.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/ethtool.h>
 #include <linux/mii.h>
@@ -84,6 +88,16 @@
 static int velocity_nics;
 static int msglevel = MSG_LEVEL_INFO;
 
+static void velocity_set_power_state(struct velocity_info *vptr, char state)
+{
+	void *addr = vptr->mac_regs;
+
+	if (vptr->bustype == BUS_PCI)
+		pci_set_power_state(vptr->pdev, state);
+	else
+		writeb(state, addr + 0x154);
+}
+
 /**
  *	mac_get_cam_mask	-	Read a CAM mask
  *	@regs: register block for this velocity
@@ -362,12 +376,23 @@ static struct velocity_info_tbl chip_info_table[] = {
  *	Describe the PCI device identifiers that we support in this
  *	device driver. Used for hotplug autoloading.
  */
-static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
+
+static DEFINE_PCI_DEVICE_TABLE(velocity_pci_id_table) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
 	{ }
 };
 
-MODULE_DEVICE_TABLE(pci, velocity_id_table);
+MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
+
+/**
+ *	Describe the OF device identifiers that we support in this
+ *	device driver. Used for devicetree nodes.
+ */
+static struct of_device_id velocity_of_ids[] = {
+	{ .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, velocity_of_ids);
 
 /**
  *	get_chip_name	- 	identifier to name
@@ -386,29 +411,6 @@ static const char *get_chip_name(enum chip_type chip_id)
 }
 
 /**
- *	velocity_remove1	-	device unplug
- *	@pdev: PCI device being removed
- *
- *	Device unload callback. Called on an unplug or on module
- *	unload for each active device that is present. Disconnects
- *	the device from the network layer and frees all the resources
- */
-static void velocity_remove1(struct pci_dev *pdev)
-{
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
-
-	unregister_netdev(dev);
-	iounmap(vptr->mac_regs);
-	pci_release_regions(pdev);
-	pci_disable_device(pdev);
-	pci_set_drvdata(pdev, NULL);
-	free_netdev(dev);
-
-	velocity_nics--;
-}
-
-/**
  *	velocity_set_int_opt	-	parser for integer options
  *	@opt: pointer to option value
  *	@val: value the user requested (or -1 for default)
@@ -1181,6 +1183,17 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
 	u16 BMCR;
 
 	switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
+	case PHYID_ICPLUS_IP101A:
+		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
+						MII_ADVERTISE, vptr->mac_regs);
+		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		else
+			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
+		break;
 	case PHYID_CICADA_CS8201:
 		/*
 		 *	Reset to hardware default
@@ -1353,9 +1366,12 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		velocity_soft_reset(vptr);
 		mdelay(5);
 
-		mac_eeprom_reload(regs);
-		for (i = 0; i < 6; i++)
-			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
+		if (!vptr->no_eeprom) {
+			mac_eeprom_reload(regs);
+			for (i = 0; i < 6; i++)
+				writeb(vptr->netdev->dev_addr[i],
+							&(regs->PAR[i]));
+		}
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -2233,15 +2249,15 @@ static int velocity_open(struct net_device *dev)
 		goto out;
 
 	/* Ensure chip is running */
-	pci_set_power_state(vptr->pdev, PCI_D0);
+	velocity_set_power_state(vptr, PCI_D0);
 
 	velocity_init_registers(vptr, VELOCITY_INIT_COLD);
 
-	ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
+	ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
 			  dev->name, dev);
 	if (ret < 0) {
 		/* Power down the chip */
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 		velocity_free_rings(vptr);
 		goto out;
 	}
@@ -2314,6 +2330,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
+		tmp_vptr->dev = vptr->dev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
 
@@ -2413,7 +2430,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	   saving then we need to bring the device back up to talk to it */
 
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 
 	switch (cmd) {
 	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
@@ -2426,7 +2443,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 		ret = -EOPNOTSUPP;
 	}
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 
 
 	return ret;
@@ -2492,7 +2509,7 @@ static int velocity_close(struct net_device *dev)
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
 		velocity_get_ip(vptr);
 
-	free_irq(vptr->pdev->irq, dev);
+	free_irq(dev->irq, dev);
 
 	velocity_free_rings(vptr);
 
@@ -2631,13 +2648,9 @@ static const struct net_device_ops velocity_netdev_ops = {
  *	Set up the initial velocity_info struct for the device that has been
  *	discovered.
  */
-static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
-			       const struct velocity_info_tbl *info)
+static void velocity_init_info(struct velocity_info *vptr,
+				const struct velocity_info_tbl *info)
 {
-	memset(vptr, 0, sizeof(struct velocity_info));
-
-	vptr->dev = &pdev->dev;
-	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
 	vptr->multicast_limit = MCAM_SIZE;
@@ -2652,10 +2665,9 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
  *	Retrieve the PCI configuration space data that interests us from
  *	the kernel PCI layer
  */
-static int velocity_get_pci_info(struct velocity_info *vptr,
-				 struct pci_dev *pdev)
+static int velocity_get_pci_info(struct velocity_info *vptr)
 {
-	vptr->rev_id = pdev->revision;
+	struct pci_dev *pdev = vptr->pdev;
 
 	pci_set_master(pdev);
 
@@ -2678,7 +2690,37 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
 		dev_err(&pdev->dev, "region #1 is too small.\n");
 		return -EINVAL;
 	}
-	vptr->pdev = pdev;
+
+	return 0;
+}
+
+/**
+ *	velocity_get_platform_info - retrieve platform info for device
+ *	@vptr: velocity device
+ *	@pdev: platform device it matches
+ *
+ *	Retrieve the Platform configuration data that interests us
+ */
+static int velocity_get_platform_info(struct velocity_info *vptr)
+{
+	struct resource res;
+	int ret;
+
+	if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
+		vptr->no_eeprom = 1;
+
+	ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
+	if (ret) {
+		dev_err(vptr->dev, "unable to find memory address\n");
+		return ret;
+	}
+
+	vptr->memaddr = res.start;
+
+	if (resource_size(&res) < VELOCITY_IO_SIZE) {
+		dev_err(vptr->dev, "memory region is too small.\n");
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -2707,21 +2749,22 @@ static u32 velocity_get_link(struct net_device *dev)
 }
 
 /**
- *	velocity_found1		-	set up discovered velocity card
+ *	velocity_probe - set up discovered velocity device
  *	@pdev: PCI device
  *	@ent: PCI device table entry that matched
+ *	@bustype: bus that device is connected to
  *
  *	Configure a discovered adapter from scratch. Return a negative
  *	errno error code on failure paths.
  */
-static int velocity_found1(struct pci_dev *pdev,
-			   const struct pci_device_id *ent)
+static int velocity_probe(struct device *dev, int irq,
+			   const struct velocity_info_tbl *info,
+			   enum velocity_bus_type bustype)
 {
 	static int first = 1;
-	struct net_device *dev;
+	struct net_device *netdev;
 	int i;
 	const char *drv_string;
-	const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
 	struct velocity_info *vptr;
 	struct mac_regs __iomem *regs;
 	int ret = -ENOMEM;
@@ -2730,19 +2773,19 @@ static int velocity_found1(struct pci_dev *pdev,
 	 * can support more than MAX_UNITS.
 	 */
 	if (velocity_nics >= MAX_UNITS) {
-		dev_notice(&pdev->dev, "already found %d NICs.\n",
-			   velocity_nics);
+		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
 		return -ENODEV;
 	}
 
-	dev = alloc_etherdev(sizeof(struct velocity_info));
-	if (!dev)
+	netdev = alloc_etherdev(sizeof(struct velocity_info));
+	if (!netdev)
 		goto out;
 
 	/* Chain it all together */
 
-	SET_NETDEV_DEV(dev, &pdev->dev);
-	vptr = netdev_priv(dev);
+	SET_NETDEV_DEV(netdev, dev);
+	vptr = netdev_priv(netdev);
+	memset(vptr, 0, sizeof(struct velocity_info));
 
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
@@ -2752,41 +2795,41 @@ static int velocity_found1(struct pci_dev *pdev,
 		first = 0;
 	}
 
-	velocity_init_info(pdev, vptr, info);
-
-	vptr->netdev = dev;
+	netdev->irq = irq;
+	vptr->bustype = bustype;
+	vptr->netdev = netdev;
+	vptr->dev = dev;
 
-	ret = pci_enable_device(pdev);
-	if (ret < 0)
-		goto err_free_dev;
+	velocity_init_info(vptr, info);
 
-	ret = velocity_get_pci_info(vptr, pdev);
-	if (ret < 0) {
-		/* error message already printed */
-		goto err_disable;
-	}
+	if (vptr->bustype == BUS_PCI) {
+		vptr->pdev = to_pci_dev(dev);
 
-	ret = pci_request_regions(pdev, VELOCITY_NAME);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "No PCI resources.\n");
-		goto err_disable;
+		ret = velocity_get_pci_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
+	} else {
+		ret = velocity_get_platform_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
 	}
 
 	regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
 	if (regs == NULL) {
 		ret = -EIO;
-		goto err_release_res;
+		goto err_free_dev;
 	}
 
 	vptr->mac_regs = regs;
+	vptr->rev_id = readb(&regs->rev_id);
 
 	mac_wol_reset(regs);
 
 	for (i = 0; i < 6; i++)
-		dev->dev_addr[i] = readb(&regs->PAR[i]);
+		netdev->dev_addr[i] = readb(&regs->PAR[i]);
 
 
-	drv_string = dev_driver_string(&pdev->dev);
+	drv_string = dev_driver_string(dev);
 
 	velocity_get_options(&vptr->options, velocity_nics, drv_string);
 
@@ -2807,46 +2850,125 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
 
-	dev->netdev_ops = &velocity_netdev_ops;
-	dev->ethtool_ops = &velocity_ethtool_ops;
-	netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
+	netdev->netdev_ops = &velocity_netdev_ops;
+	netdev->ethtool_ops = &velocity_ethtool_ops;
+	netif_napi_add(netdev, &vptr->napi, velocity_poll,
+							VELOCITY_NAPI_WEIGHT);
 
-	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
+	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
 			   NETIF_F_HW_VLAN_CTAG_TX;
-	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_FILTER |
-			 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_IP_CSUM;
+	netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
+			NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
+			NETIF_F_IP_CSUM;
 
-	ret = register_netdev(dev);
+	ret = register_netdev(netdev);
 	if (ret < 0)
 		goto err_iounmap;
 
-	if (!velocity_get_link(dev)) {
-		netif_carrier_off(dev);
+	if (!velocity_get_link(netdev)) {
+		netif_carrier_off(netdev);
 		vptr->mii_status |= VELOCITY_LINK_FAIL;
 	}
 
 	velocity_print_info(vptr);
-	pci_set_drvdata(pdev, dev);
+	dev_set_drvdata(vptr->dev, netdev);
 
 	/* and leave the chip powered down */
 
-	pci_set_power_state(pdev, PCI_D3hot);
+	velocity_set_power_state(vptr, PCI_D3hot);
 	velocity_nics++;
 out:
 	return ret;
 
 err_iounmap:
 	iounmap(regs);
-err_release_res:
-	pci_release_regions(pdev);
-err_disable:
-	pci_disable_device(pdev);
 err_free_dev:
-	free_netdev(dev);
+	free_netdev(netdev);
 	goto out;
 }
 
-#ifdef CONFIG_PM
+/**
+ *	velocity_remove	- device unplug
+ *	@dev: device being removed
+ *
+ *	Device unload callback. Called on an unplug or on module
+ *	unload for each active device that is present. Disconnects
+ *	the device from the network layer and frees all the resources
+ */
+static int velocity_remove(struct device *dev)
+{
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
+
+	unregister_netdev(netdev);
+	iounmap(vptr->mac_regs);
+	free_netdev(netdev);
+	velocity_nics--;
+
+	return 0;
+}
+
+static int velocity_pci_probe(struct pci_dev *pdev,
+			   const struct pci_device_id *ent)
+{
+	int ret;
+	const struct velocity_info_tbl *info =
+					&chip_info_table[ent->driver_data];
+
+	ret = pci_enable_device(pdev);
+	if (ret < 0)
+		return ret;
+
+	ret = pci_request_regions(pdev, VELOCITY_NAME);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "No PCI resources.\n");
+		pci_disable_device(pdev);
+		return ret;
+	}
+
+	ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
+	if (ret < 0) {
+		pci_release_regions(pdev);
+		pci_disable_device(pdev);
+	}
+
+	return ret;
+}
+
+static void velocity_pci_remove(struct pci_dev *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+}
+
+static int velocity_platform_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	const struct velocity_info_tbl *info;
+	int irq;
+
+	of_id = of_match_device(velocity_of_ids, &pdev->dev);
+	if (!of_id)
+		return -EINVAL;
+	info = of_id->data;
+
+	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+	if (!irq)
+		return -EINVAL;
+
+	return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
+}
+
+static int velocity_platform_remove(struct platform_device *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
 /**
  *	wol_calc_crc		-	WOL CRC
  *	@pattern: data pattern
@@ -3003,10 +3125,10 @@ static void velocity_save_context(struct velocity_info *vptr, struct velocity_co
 
 }
 
-static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
+static int velocity_suspend(struct device *dev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 
 	if (!netif_running(vptr->netdev))
@@ -3015,20 +3137,23 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
-	pci_save_state(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_save_state(vptr->pdev);
 
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
 		velocity_get_ip(vptr);
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
 		velocity_set_wol(vptr);
-		pci_enable_wake(pdev, PCI_D3hot, 1);
-		pci_set_power_state(pdev, PCI_D3hot);
+		if (vptr->bustype == BUS_PCI)
+			pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	} else {
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
-		pci_disable_device(pdev);
-		pci_set_power_state(pdev, pci_choose_state(pdev, state));
+		if (vptr->bustype == BUS_PCI)
+			pci_disable_device(vptr->pdev);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	}
 
 	spin_unlock_irqrestore(&vptr->lock, flags);
@@ -3070,19 +3195,22 @@ static void velocity_restore_context(struct velocity_info *vptr, struct velocity
 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
 }
 
-static int velocity_resume(struct pci_dev *pdev)
+static int velocity_resume(struct device *dev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 	int i;
 
 	if (!netif_running(vptr->netdev))
 		return 0;
 
-	pci_set_power_state(pdev, PCI_D0);
-	pci_enable_wake(pdev, 0, 0);
-	pci_restore_state(pdev);
+	velocity_set_power_state(vptr, PCI_D0);
+
+	if (vptr->bustype == BUS_PCI) {
+		pci_enable_wake(vptr->pdev, 0, 0);
+		pci_restore_state(vptr->pdev);
+	}
 
 	mac_wol_reset(vptr->mac_regs);
 
@@ -3104,23 +3232,34 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	return 0;
 }
-#endif
+#endif	/* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
 
 /*
  *	Definition for our device driver. The PCI layer interface
  *	uses this to handle all our card discover and plugging
  */
-static struct pci_driver velocity_driver = {
+static struct pci_driver velocity_pci_driver = {
 	.name		= VELOCITY_NAME,
-	.id_table	= velocity_id_table,
-	.probe		= velocity_found1,
-	.remove		= velocity_remove1,
-#ifdef CONFIG_PM
-	.suspend	= velocity_suspend,
-	.resume		= velocity_resume,
-#endif
+	.id_table	= velocity_pci_id_table,
+	.probe		= velocity_pci_probe,
+	.remove		= velocity_pci_remove,
+	.driver = {
+		.pm = &velocity_pm_ops,
+	},
 };
 
+static struct platform_driver velocity_platform_driver = {
+	.probe		= velocity_platform_probe,
+	.remove		= velocity_platform_remove,
+	.driver = {
+		.name = "via-velocity",
+		.owner = THIS_MODULE,
+		.of_match_table = velocity_of_ids,
+		.pm = &velocity_pm_ops,
+	},
+};
 
 /**
  *	velocity_ethtool_up	-	pre hook for ethtool
@@ -3133,7 +3272,7 @@ static int velocity_ethtool_up(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 	return 0;
 }
 
@@ -3148,7 +3287,7 @@ static void velocity_ethtool_down(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 }
 
 static int velocity_get_settings(struct net_device *dev,
@@ -3270,7 +3409,11 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
 	struct velocity_info *vptr = netdev_priv(dev);
 	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
 	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
-	strlcpy(info->bus_info, pci_name(vptr->pdev), sizeof(info->bus_info));
+	if (vptr->bustype == BUS_PCI)
+		strlcpy(info->bus_info, pci_name(vptr->pdev),
+						sizeof(info->bus_info));
+	else
+		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
 }
 
 static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -3563,9 +3706,15 @@ static int __init velocity_init_module(void)
 	int ret;
 
 	velocity_register_notifier();
-	ret = pci_register_driver(&velocity_driver);
+
+	ret = pci_register_driver(&velocity_pci_driver);
+	if (ret < 0)
+		velocity_unregister_notifier();
+
+	ret = platform_driver_register(&velocity_platform_driver);
 	if (ret < 0)
 		velocity_unregister_notifier();
+
 	return ret;
 }
 
@@ -3580,7 +3729,9 @@ static int __init velocity_init_module(void)
 static void __exit velocity_cleanup_module(void)
 {
 	velocity_unregister_notifier();
-	pci_unregister_driver(&velocity_driver);
+
+	pci_unregister_driver(&velocity_pci_driver);
+	platform_driver_unregister(&velocity_platform_driver);
 }
 
 module_init(velocity_init_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index c38bbae..6be7e46 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1265,7 +1265,7 @@ struct velocity_context {
 #define PHYID_VT3216_64BIT  0x000FC600UL
 #define PHYID_MARVELL_1000  0x01410C50UL
 #define PHYID_MARVELL_1000S 0x01410C40UL
-
+#define PHYID_ICPLUS_IP101A 0x02430C54UL
 #define PHYID_REV_ID_MASK   0x0000000FUL
 
 #define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
@@ -1433,10 +1433,38 @@ struct velocity_opt {
 
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
+static inline char velocity_choose_state(struct device *dev,
+					   pm_message_t state)
+
+{
+	switch (state.event) {
+	case PM_EVENT_ON:
+		return PCI_D0;
+	case PM_EVENT_FREEZE:
+	case PM_EVENT_PRETHAW:
+		/* REVISIT both freeze and pre-thaw "should" use D0 */
+	case PM_EVENT_SUSPEND:
+	case PM_EVENT_HIBERNATE:
+		return PCI_D3hot;
+	default:
+		dev_info(dev, "unrecognized suspend event %d\n", state.event);
+		BUG();
+	}
+
+	return PCI_D0;
+}
+
+enum velocity_bus_type {
+	BUS_PCI,
+	BUS_PLATFORM,
+};
+
 struct velocity_info {
-	struct device *dev;
 	struct pci_dev *pdev;
+	struct device *dev;
 	struct net_device *netdev;
+	enum velocity_bus_type bustype;
+	int no_eeprom;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 00:55:09 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 16:55:09 +1200
Subject: [PATCHv7 0/3] Add support for velocity network driver on platform
 devices
In-Reply-To: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
References: <1368843825-14813-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <519709AD.8010206@prisktech.co.nz>

On 18/05/13 14:23, Tony Prisk wrote:
> v7 changes:
> Forgot to merge a patch to fix an error with the pm ops changes. Apologies Dave.
>
> v6 changes:
> Remove more bus specific code from velocity_probe()
> Make velocity_(suspend/resume) accept a struct device *
> Simplify PM code to use velocity_(suspend/resume) - remove the individual
> pci and platform functions.
> Add a struct pci_dev variable to velocity_get_pci_info() to reduce churn
>
> v5 changes:
> Remove velocity_info union. Change velocity_info->pdev back to struct pci_dev.
> Remove more 'if (pci)' sections.
> Remove 'void *pdev' function parameters.
> Pass correct variable to velocity_choose_state()
>
> v4 changes:
> Code tidyup as requested by Francois Romieu
> Removed '#ifdef PCI' around PCI code. Compile tested on (!)PCI and (!)PM.
>
> v3 changes:
> Rebased against net-next.
> Fix errors in pm code.
>
> v2 changes:
> Drop patch #1 as requested by David Miller.
> Correct the PHYID_ICPLUS_IP101A MII bits - should be ON, rather than OFF.
> Read the platform rev_id from the correct register [regs->rev_id]. It's possible
> this would work for the PCI version as well and would remove the need for the
> 'if (pci)' test to set vptr->rev_id.
>
> v1:
> The first three patches are general tidyup.
>
> [DROPPED] Patch ## just alphabetizes the #includes to make it easier to read.
>
> Patch #1 replaces vptr->dev with vptr->netdev, in preparation of adding a
> struct device *dev in Patch #2
>
> Patch #2 replaces the pci dma functions with the generic versions.
>
> I have build tested these patches but don't have a PCI velocity to run-test it.
> I can't see that they should introduce any problems as it is all renames and
> function swapping.
>
> Patch #3 adds support for the velocity driver on devicetree platform devices.
> Binding document included. This patch is compile-tested for PCI, and boot
> tested on a VIA APC8750.
>
> I think it would be pertinent to get some tested-by's for PCI users.
>
> Regards
> Tony Prisk
>
>
> Tony Prisk (3):
>    net: velocity: Rename vptr->dev to vptr->netdev
>    net: velocity: Convert to generic dma functions
>    net: velocity: Add platform device support to VIA velocity driver
>
>   .../devicetree/bindings/net/via-velocity.txt       |   20 +
>   drivers/net/ethernet/via/Kconfig                   |    3 +-
>   drivers/net/ethernet/via/via-velocity.c            |  496 +++++++++++++-------
>   drivers/net/ethernet/via/via-velocity.h            |   35 +-
>   4 files changed, 376 insertions(+), 178 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt
>

Please don't apply this version either Dave.
I noticed that velocity_choose_state is defined in via-velocity.h but is 
never used.

Will resend v8.


From linux at prisktech.co.nz  Sat May 18 00:59:44 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 16:59:44 +1200
Subject: [PATCHv8 0/3] Add support for velocity network driver on platform
 devices
Message-ID: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>

v8 changes:
Remove velocity_choose_state from via-velocity.h: unused function.

v7 changes:
Forgot to merge a patch to fix an error with the pm ops changes. Apologies Dave.

v6 changes:
Remove more bus specific code from velocity_probe()
Make velocity_(suspend/resume) accept a struct device *
Simplify PM code to use velocity_(suspend/resume) - remove the individual
pci and platform functions.
Add a struct pci_dev variable to velocity_get_pci_info() to reduce churn

v5 changes:
Remove velocity_info union. Change velocity_info->pdev back to struct pci_dev.
Remove more 'if (pci)' sections.
Remove 'void *pdev' function parameters.
Pass correct variable to velocity_choose_state()

v4 changes:
Code tidyup as requested by Francois Romieu
Removed '#ifdef PCI' around PCI code. Compile tested on (!)PCI and (!)PM.

v3 changes:
Rebased against net-next.
Fix errors in pm code.

v2 changes:
Drop patch #1 as requested by David Miller.
Correct the PHYID_ICPLUS_IP101A MII bits - should be ON, rather than OFF.
Read the platform rev_id from the correct register [regs->rev_id]. It's possible
this would work for the PCI version as well and would remove the need for the
'if (pci)' test to set vptr->rev_id.

v1:
The first three patches are general tidyup.

[DROPPED] Patch ## just alphabetizes the #includes to make it easier to read.

Patch #1 replaces vptr->dev with vptr->netdev, in preparation of adding a
struct device *dev in Patch #2

Patch #2 replaces the pci dma functions with the generic versions.

I have build tested these patches but don't have a PCI velocity to run-test it.
I can't see that they should introduce any problems as it is all renames and
function swapping.

Patch #3 adds support for the velocity driver on devicetree platform devices.
Binding document included. This patch is compile-tested for PCI, and boot
tested on a VIA APC8750.

I think it would be pertinent to get some tested-by's for PCI users.

Regards
Tony Prisk

Tony Prisk (3):
  net: velocity: Rename vptr->dev to vptr->netdev
  net: velocity: Convert to generic dma functions
  net: velocity: Add platform device support to VIA velocity driver

 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  496 +++++++++++++-------
 drivers/net/ethernet/via/via-velocity.h            |   14 +-
 4 files changed, 355 insertions(+), 178 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 00:59:46 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 16:59:46 +1200
Subject: [PATCHv8 2/3] net: velocity: Convert to generic dma functions
In-Reply-To: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
References: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368853187-17823-3-git-send-email-linux@prisktech.co.nz>

Remove the pci_* dma functions and replace with the more generic
versions.

In preparation of adding platform support, a new struct device *dev
is added to struct velocity_info which can be used by both the pci
and platform code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   51 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    1 +
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 187eef3..5996cee 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -46,6 +46,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 #include <linux/init.h>
+#include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
@@ -1459,7 +1460,6 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	struct velocity_opt *opt = &vptr->options;
 	const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
 	const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
-	struct pci_dev *pdev = vptr->pdev;
 	dma_addr_t pool_dma;
 	void *pool;
 	unsigned int i;
@@ -1467,13 +1467,13 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 	/*
 	 * Allocate all RD/TD rings a single pool.
 	 *
-	 * pci_alloc_consistent() fulfills the requirement for 64 bytes
+	 * dma_alloc_coherent() fulfills the requirement for 64 bytes
 	 * alignment
 	 */
-	pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
-				    rx_ring_size, &pool_dma);
+	pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
+				    rx_ring_size, &pool_dma, GFP_ATOMIC);
 	if (!pool) {
-		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
+		dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
 			vptr->netdev->name);
 		return -ENOMEM;
 	}
@@ -1524,8 +1524,8 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	 */
 	skb_reserve(rd_info->skb,
 			64 - ((unsigned long) rd_info->skb->data & 63));
-	rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
-					vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
+					vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Fill in the descriptor to match
@@ -1588,8 +1588,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr)
 
 		if (!rd_info->skb)
 			continue;
-		pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-				 PCI_DMA_FROMDEVICE);
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
 		rd_info->skb_dma = 0;
 
 		dev_kfree_skb(rd_info->skb);
@@ -1670,7 +1670,7 @@ static void velocity_free_dma_rings(struct velocity_info *vptr)
 	const int size = vptr->options.numrx * sizeof(struct rx_desc) +
 		vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
 
-	pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
+	dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
 }
 
 static int velocity_init_rings(struct velocity_info *vptr, int mtu)
@@ -1727,8 +1727,8 @@ static void velocity_free_tx_buf(struct velocity_info *vptr,
 				pktlen = max_t(size_t, pktlen,
 						td->td_buf[i].size & ~TD_QUEUE);
 
-			pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
-					le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
+			dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
+					le16_to_cpu(pktlen), DMA_TO_DEVICE);
 		}
 	}
 	dev_kfree_skb_irq(skb);
@@ -1750,8 +1750,8 @@ static void velocity_free_td_ring_entry(struct velocity_info *vptr,
 	if (td_info->skb) {
 		for (i = 0; i < td_info->nskb_dma; i++) {
 			if (td_info->skb_dma[i]) {
-				pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
-					td_info->skb->len, PCI_DMA_TODEVICE);
+				dma_unmap_single(vptr->dev, td_info->skb_dma[i],
+					td_info->skb->len, DMA_TO_DEVICE);
 				td_info->skb_dma[i] = 0;
 			}
 		}
@@ -2029,7 +2029,6 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
  */
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
-	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
 	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
@@ -2047,8 +2046,8 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 
 	skb = rd_info->skb;
 
-	pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
-				    vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+	dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
+				    vptr->rx.buf_sz, DMA_FROM_DEVICE);
 
 	/*
 	 *	Drop frame not meeting IEEE 802.3
@@ -2061,19 +2060,18 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		}
 	}
 
-	pci_action = pci_dma_sync_single_for_device;
-
 	velocity_rx_csum(rd, skb);
 
 	if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
 		velocity_iph_realign(vptr, skb, pkt_len);
-		pci_action = pci_unmap_single;
 		rd_info->skb = NULL;
+		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
+				 DMA_FROM_DEVICE);
+	} else {
+		dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
+					   vptr->rx.buf_sz, DMA_FROM_DEVICE);
 	}
 
-	pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-		   PCI_DMA_FROMDEVICE);
-
 	skb_put(skb, pkt_len - 4);
 	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
@@ -2550,7 +2548,8 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	 *	add it to the transmit ring.
 	 */
 	tdinfo->skb = skb;
-	tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+	tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
+								DMA_TO_DEVICE);
 	td_ptr->tdesc0.len = cpu_to_le16(pktlen);
 	td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
 	td_ptr->td_buf[0].pa_high = 0;
@@ -2560,7 +2559,7 @@ static netdev_tx_t velocity_xmit(struct sk_buff *skb,
 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
-		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(&vptr->pdev->dev,
+		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
 							  frag, 0,
 							  skb_frag_size(frag),
 							  DMA_TO_DEVICE);
@@ -2637,6 +2636,7 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
 {
 	memset(vptr, 0, sizeof(struct velocity_info));
 
+	vptr->dev = &pdev->dev;
 	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
@@ -2744,7 +2744,6 @@ static int velocity_found1(struct pci_dev *pdev,
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	vptr = netdev_priv(dev);
 
-
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
 			VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index ff8d7828..c38bbae 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1434,6 +1434,7 @@ struct velocity_opt {
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
 struct velocity_info {
+	struct device *dev;
 	struct pci_dev *pdev;
 	struct net_device *netdev;
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 00:59:45 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 16:59:45 +1200
Subject: [PATCHv8 1/3] net: velocity: Rename vptr->dev to vptr->netdev
In-Reply-To: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
References: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368853187-17823-2-git-send-email-linux@prisktech.co.nz>

Improve the clarity of the code in preparation for converting the
dma functions to generic versions, which require a struct device *.

This makes it possible to store a 'struct device *dev' in the
velocity_info structure.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/net/ethernet/via/via-velocity.c |   66 +++++++++++++++----------------
 drivers/net/ethernet/via/via-velocity.h |    4 +-
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index fb62489..187eef3 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -998,9 +998,9 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 {
 
 	if (vptr->mii_status & VELOCITY_LINK_FAIL) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
 	} else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
 
 		if (vptr->mii_status & VELOCITY_SPEED_1000)
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
@@ -1014,7 +1014,7 @@ static void velocity_print_link_status(struct velocity_info *vptr)
 		else
 			VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
 	} else {
-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
 		switch (vptr->options.spd_dpx) {
 		case SPD_DPX_1000_FULL:
 			VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
@@ -1319,7 +1319,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 	case VELOCITY_INIT_RESET:
 	case VELOCITY_INIT_WOL:
 
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/*
 		 *	Reset RX to prevent RX pointer not on the 4X location
@@ -1332,7 +1332,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1354,7 +1354,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 
 		mac_eeprom_reload(regs);
 		for (i = 0; i < 6; i++)
-			writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -1377,7 +1377,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		/*
 		 *	Set packet filter: Receive directed and broadcast address
 		 */
-		velocity_set_multi(vptr->dev);
+		velocity_set_multi(vptr->netdev);
 
 		/*
 		 *	Enable MII auto-polling
@@ -1404,14 +1404,14 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
 
 		mii_status = velocity_get_opt_media_mode(vptr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		mii_init(vptr, mii_status);
 
 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
 			velocity_print_link_status(vptr);
 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-				netif_wake_queue(vptr->dev);
+				netif_wake_queue(vptr->netdev);
 		}
 
 		enable_flow_control_ability(vptr);
@@ -1474,7 +1474,7 @@ static int velocity_init_dma_rings(struct velocity_info *vptr)
 				    rx_ring_size, &pool_dma);
 	if (!pool) {
 		dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
-			vptr->dev->name);
+			vptr->netdev->name);
 		return -ENOMEM;
 	}
 
@@ -1514,7 +1514,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 
-	rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx.buf_sz + 64);
+	rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
 	if (rd_info->skb == NULL)
 		return -ENOMEM;
 
@@ -1620,7 +1620,7 @@ static int velocity_init_rd_ring(struct velocity_info *vptr)
 
 	if (velocity_rx_refill(vptr) != vptr->options.numrx) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
-			"%s: failed to allocate RX buffer.\n", vptr->dev->name);
+			"%s: failed to allocate RX buffer.\n", vptr->netdev->name);
 		velocity_free_rd_ring(vptr);
 		goto out;
 	}
@@ -1809,7 +1809,7 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
 		BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
 		writew(TRDCSR_RUN, &regs->TDCSRClr);
-		netif_stop_queue(vptr->dev);
+		netif_stop_queue(vptr->netdev);
 
 		/* FIXME: port over the pci_device_failed code and use it
 		   here */
@@ -1850,10 +1850,10 @@ static void velocity_error(struct velocity_info *vptr, int status)
 
 		if (linked) {
 			vptr->mii_status &= ~VELOCITY_LINK_FAIL;
-			netif_carrier_on(vptr->dev);
+			netif_carrier_on(vptr->netdev);
 		} else {
 			vptr->mii_status |= VELOCITY_LINK_FAIL;
-			netif_carrier_off(vptr->dev);
+			netif_carrier_off(vptr->netdev);
 		}
 
 		velocity_print_link_status(vptr);
@@ -1867,9 +1867,9 @@ static void velocity_error(struct velocity_info *vptr, int status)
 		enable_mii_autopoll(regs);
 
 		if (vptr->mii_status & VELOCITY_LINK_FAIL)
-			netif_stop_queue(vptr->dev);
+			netif_stop_queue(vptr->netdev);
 		else
-			netif_wake_queue(vptr->dev);
+			netif_wake_queue(vptr->netdev);
 
 	}
 	if (status & ISR_MIBFI)
@@ -1894,7 +1894,7 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	int idx;
 	int works = 0;
 	struct velocity_td_info *tdinfo;
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 
 	for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
 		for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
@@ -1939,9 +1939,9 @@ static int velocity_tx_srv(struct velocity_info *vptr)
 	 *	Look to see if we should kick the transmit network
 	 *	layer for more work.
 	 */
-	if (netif_queue_stopped(vptr->dev) && (full == 0) &&
+	if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
 	    (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
-		netif_wake_queue(vptr->dev);
+		netif_wake_queue(vptr->netdev);
 	}
 	return works;
 }
@@ -1989,7 +1989,7 @@ static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
 	if (pkt_size < rx_copybreak) {
 		struct sk_buff *new_skb;
 
-		new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
+		new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
 		if (new_skb) {
 			new_skb->ip_summed = rx_skb[0]->ip_summed;
 			skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
@@ -2030,14 +2030,14 @@ static inline void velocity_iph_realign(struct velocity_info *vptr,
 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 {
 	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
 	int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
 	struct sk_buff *skb;
 
 	if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
-		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->netdev->name);
 		stats->rx_length_errors++;
 		return -EINVAL;
 	}
@@ -2075,7 +2075,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
 		   PCI_DMA_FROMDEVICE);
 
 	skb_put(skb, pkt_len - 4);
-	skb->protocol = eth_type_trans(skb, vptr->dev);
+	skb->protocol = eth_type_trans(skb, vptr->netdev);
 
 	if (rd->rdesc0.RSR & RSR_DETAG) {
 		u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
@@ -2100,7 +2100,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
  */
 static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
 {
-	struct net_device_stats *stats = &vptr->dev->stats;
+	struct net_device_stats *stats = &vptr->netdev->stats;
 	int rd_curr = vptr->rx.curr;
 	int works = 0;
 
@@ -2292,7 +2292,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 	if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
 		VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
-				vptr->dev->name);
+				vptr->netdev->name);
 		ret = -EINVAL;
 		goto out_0;
 	}
@@ -2314,7 +2314,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 			goto out_0;
 		}
 
-		tmp_vptr->dev = dev;
+		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
@@ -2692,7 +2692,7 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
  */
 static void velocity_print_info(struct velocity_info *vptr)
 {
-	struct net_device *dev = vptr->dev;
+	struct net_device *dev = vptr->netdev;
 
 	printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
 	printk(KERN_INFO "%s: Ethernet Address: %pM\n",
@@ -2755,7 +2755,7 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	velocity_init_info(pdev, vptr, info);
 
-	vptr->dev = dev;
+	vptr->netdev = dev;
 
 	ret = pci_enable_device(pdev);
 	if (ret < 0)
@@ -3010,10 +3010,10 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	struct velocity_info *vptr = netdev_priv(dev);
 	unsigned long flags;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
-	netif_device_detach(vptr->dev);
+	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
 	pci_save_state(pdev);
@@ -3078,7 +3078,7 @@ static int velocity_resume(struct pci_dev *pdev)
 	unsigned long flags;
 	int i;
 
-	if (!netif_running(vptr->dev))
+	if (!netif_running(vptr->netdev))
 		return 0;
 
 	pci_set_power_state(pdev, PCI_D0);
@@ -3101,7 +3101,7 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	mac_enable_int(vptr->mac_regs);
 	spin_unlock_irqrestore(&vptr->lock, flags);
-	netif_device_attach(vptr->dev);
+	netif_device_attach(vptr->netdev);
 
 	return 0;
 }
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index 4cb9f13..ff8d7828 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1435,7 +1435,7 @@ struct velocity_opt {
 
 struct velocity_info {
 	struct pci_dev *pdev;
-	struct net_device *dev;
+	struct net_device *netdev;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
@@ -1514,7 +1514,7 @@ static inline int velocity_get_ip(struct velocity_info *vptr)
 	int res = -ENOENT;
 
 	rcu_read_lock();
-	in_dev = __in_dev_get_rcu(vptr->dev);
+	in_dev = __in_dev_get_rcu(vptr->netdev);
 	if (in_dev != NULL) {
 		ifa = (struct in_ifaddr *) in_dev->ifa_list;
 		if (ifa != NULL) {
-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 00:59:47 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 16:59:47 +1200
Subject: [PATCHv8 3/3] net: velocity: Add platform device support to VIA
 velocity driver
In-Reply-To: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
References: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368853187-17823-4-git-send-email-linux@prisktech.co.nz>

Add support for the VIA Velocity network driver to be bound to a
OF created platform device.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/net/via-velocity.txt       |   20 +
 drivers/net/ethernet/via/Kconfig                   |    3 +-
 drivers/net/ethernet/via/via-velocity.c            |  387 ++++++++++++++------
 drivers/net/ethernet/via/via-velocity.h            |   11 +-
 4 files changed, 299 insertions(+), 122 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/via-velocity.txt

diff --git a/Documentation/devicetree/bindings/net/via-velocity.txt b/Documentation/devicetree/bindings/net/via-velocity.txt
new file mode 100644
index 0000000..b3db469
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/via-velocity.txt
@@ -0,0 +1,20 @@
+* VIA Velocity 10/100/1000 Network Controller
+
+Required properties:
+- compatible : Should be "via,velocity-vt6110"
+- reg : Address and length of the io space
+- interrupts : Should contain the controller interrupt line
+
+Optional properties:
+- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
+	devices quite often set this data in uboot and do not provide an eeprom.
+	Specify this option if you have no external eeprom.
+
+Examples:
+
+eth0 at d8004000 {
+	compatible = "via,velocity-vt6110";
+	reg = <0xd8004000 0x400>;
+	interrupts = <10>;
+	no-eeprom;
+};
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
index 68a9ba6..6a87097 100644
--- a/drivers/net/ethernet/via/Kconfig
+++ b/drivers/net/ethernet/via/Kconfig
@@ -5,7 +5,6 @@
 config NET_VENDOR_VIA
 	bool "VIA devices"
 	default y
-	depends on PCI
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y
 	  and read the Ethernet-HOWTO, available from
@@ -45,7 +44,7 @@ config VIA_RHINE_MMIO
 
 config VIA_VELOCITY
 	tristate "VIA Velocity support"
-	depends on PCI
+	depends on (PCI || USE_OF)
 	select CRC32
 	select CRC_CCITT
 	select NET_CORE
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index 5996cee..d8d5bc5 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -65,7 +65,11 @@
 #include <linux/if.h>
 #include <linux/uaccess.h>
 #include <linux/proc_fs.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
 #include <linux/inetdevice.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/ethtool.h>
 #include <linux/mii.h>
@@ -84,6 +88,16 @@
 static int velocity_nics;
 static int msglevel = MSG_LEVEL_INFO;
 
+static void velocity_set_power_state(struct velocity_info *vptr, char state)
+{
+	void *addr = vptr->mac_regs;
+
+	if (vptr->bustype == BUS_PCI)
+		pci_set_power_state(vptr->pdev, state);
+	else
+		writeb(state, addr + 0x154);
+}
+
 /**
  *	mac_get_cam_mask	-	Read a CAM mask
  *	@regs: register block for this velocity
@@ -362,12 +376,23 @@ static struct velocity_info_tbl chip_info_table[] = {
  *	Describe the PCI device identifiers that we support in this
  *	device driver. Used for hotplug autoloading.
  */
-static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
+
+static DEFINE_PCI_DEVICE_TABLE(velocity_pci_id_table) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
 	{ }
 };
 
-MODULE_DEVICE_TABLE(pci, velocity_id_table);
+MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
+
+/**
+ *	Describe the OF device identifiers that we support in this
+ *	device driver. Used for devicetree nodes.
+ */
+static struct of_device_id velocity_of_ids[] = {
+	{ .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, velocity_of_ids);
 
 /**
  *	get_chip_name	- 	identifier to name
@@ -386,29 +411,6 @@ static const char *get_chip_name(enum chip_type chip_id)
 }
 
 /**
- *	velocity_remove1	-	device unplug
- *	@pdev: PCI device being removed
- *
- *	Device unload callback. Called on an unplug or on module
- *	unload for each active device that is present. Disconnects
- *	the device from the network layer and frees all the resources
- */
-static void velocity_remove1(struct pci_dev *pdev)
-{
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
-
-	unregister_netdev(dev);
-	iounmap(vptr->mac_regs);
-	pci_release_regions(pdev);
-	pci_disable_device(pdev);
-	pci_set_drvdata(pdev, NULL);
-	free_netdev(dev);
-
-	velocity_nics--;
-}
-
-/**
  *	velocity_set_int_opt	-	parser for integer options
  *	@opt: pointer to option value
  *	@val: value the user requested (or -1 for default)
@@ -1181,6 +1183,17 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
 	u16 BMCR;
 
 	switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
+	case PHYID_ICPLUS_IP101A:
+		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
+						MII_ADVERTISE, vptr->mac_regs);
+		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		else
+			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
+								vptr->mac_regs);
+		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
+		break;
 	case PHYID_CICADA_CS8201:
 		/*
 		 *	Reset to hardware default
@@ -1353,9 +1366,12 @@ static void velocity_init_registers(struct velocity_info *vptr,
 		velocity_soft_reset(vptr);
 		mdelay(5);
 
-		mac_eeprom_reload(regs);
-		for (i = 0; i < 6; i++)
-			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
+		if (!vptr->no_eeprom) {
+			mac_eeprom_reload(regs);
+			for (i = 0; i < 6; i++)
+				writeb(vptr->netdev->dev_addr[i],
+							&(regs->PAR[i]));
+		}
 
 		/*
 		 *	clear Pre_ACPI bit.
@@ -2233,15 +2249,15 @@ static int velocity_open(struct net_device *dev)
 		goto out;
 
 	/* Ensure chip is running */
-	pci_set_power_state(vptr->pdev, PCI_D0);
+	velocity_set_power_state(vptr, PCI_D0);
 
 	velocity_init_registers(vptr, VELOCITY_INIT_COLD);
 
-	ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
+	ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
 			  dev->name, dev);
 	if (ret < 0) {
 		/* Power down the chip */
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 		velocity_free_rings(vptr);
 		goto out;
 	}
@@ -2314,6 +2330,7 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
 
 		tmp_vptr->netdev = dev;
 		tmp_vptr->pdev = vptr->pdev;
+		tmp_vptr->dev = vptr->dev;
 		tmp_vptr->options = vptr->options;
 		tmp_vptr->tx.numq = vptr->tx.numq;
 
@@ -2413,7 +2430,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	   saving then we need to bring the device back up to talk to it */
 
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 
 	switch (cmd) {
 	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
@@ -2426,7 +2443,7 @@ static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 		ret = -EOPNOTSUPP;
 	}
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 
 
 	return ret;
@@ -2492,7 +2509,7 @@ static int velocity_close(struct net_device *dev)
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
 		velocity_get_ip(vptr);
 
-	free_irq(vptr->pdev->irq, dev);
+	free_irq(dev->irq, dev);
 
 	velocity_free_rings(vptr);
 
@@ -2631,13 +2648,9 @@ static const struct net_device_ops velocity_netdev_ops = {
  *	Set up the initial velocity_info struct for the device that has been
  *	discovered.
  */
-static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
-			       const struct velocity_info_tbl *info)
+static void velocity_init_info(struct velocity_info *vptr,
+				const struct velocity_info_tbl *info)
 {
-	memset(vptr, 0, sizeof(struct velocity_info));
-
-	vptr->dev = &pdev->dev;
-	vptr->pdev = pdev;
 	vptr->chip_id = info->chip_id;
 	vptr->tx.numq = info->txqueue;
 	vptr->multicast_limit = MCAM_SIZE;
@@ -2652,10 +2665,9 @@ static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
  *	Retrieve the PCI configuration space data that interests us from
  *	the kernel PCI layer
  */
-static int velocity_get_pci_info(struct velocity_info *vptr,
-				 struct pci_dev *pdev)
+static int velocity_get_pci_info(struct velocity_info *vptr)
 {
-	vptr->rev_id = pdev->revision;
+	struct pci_dev *pdev = vptr->pdev;
 
 	pci_set_master(pdev);
 
@@ -2678,7 +2690,37 @@ static int velocity_get_pci_info(struct velocity_info *vptr,
 		dev_err(&pdev->dev, "region #1 is too small.\n");
 		return -EINVAL;
 	}
-	vptr->pdev = pdev;
+
+	return 0;
+}
+
+/**
+ *	velocity_get_platform_info - retrieve platform info for device
+ *	@vptr: velocity device
+ *	@pdev: platform device it matches
+ *
+ *	Retrieve the Platform configuration data that interests us
+ */
+static int velocity_get_platform_info(struct velocity_info *vptr)
+{
+	struct resource res;
+	int ret;
+
+	if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
+		vptr->no_eeprom = 1;
+
+	ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
+	if (ret) {
+		dev_err(vptr->dev, "unable to find memory address\n");
+		return ret;
+	}
+
+	vptr->memaddr = res.start;
+
+	if (resource_size(&res) < VELOCITY_IO_SIZE) {
+		dev_err(vptr->dev, "memory region is too small.\n");
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -2707,21 +2749,22 @@ static u32 velocity_get_link(struct net_device *dev)
 }
 
 /**
- *	velocity_found1		-	set up discovered velocity card
+ *	velocity_probe - set up discovered velocity device
  *	@pdev: PCI device
  *	@ent: PCI device table entry that matched
+ *	@bustype: bus that device is connected to
  *
  *	Configure a discovered adapter from scratch. Return a negative
  *	errno error code on failure paths.
  */
-static int velocity_found1(struct pci_dev *pdev,
-			   const struct pci_device_id *ent)
+static int velocity_probe(struct device *dev, int irq,
+			   const struct velocity_info_tbl *info,
+			   enum velocity_bus_type bustype)
 {
 	static int first = 1;
-	struct net_device *dev;
+	struct net_device *netdev;
 	int i;
 	const char *drv_string;
-	const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
 	struct velocity_info *vptr;
 	struct mac_regs __iomem *regs;
 	int ret = -ENOMEM;
@@ -2730,19 +2773,19 @@ static int velocity_found1(struct pci_dev *pdev,
 	 * can support more than MAX_UNITS.
 	 */
 	if (velocity_nics >= MAX_UNITS) {
-		dev_notice(&pdev->dev, "already found %d NICs.\n",
-			   velocity_nics);
+		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
 		return -ENODEV;
 	}
 
-	dev = alloc_etherdev(sizeof(struct velocity_info));
-	if (!dev)
+	netdev = alloc_etherdev(sizeof(struct velocity_info));
+	if (!netdev)
 		goto out;
 
 	/* Chain it all together */
 
-	SET_NETDEV_DEV(dev, &pdev->dev);
-	vptr = netdev_priv(dev);
+	SET_NETDEV_DEV(netdev, dev);
+	vptr = netdev_priv(netdev);
+	memset(vptr, 0, sizeof(struct velocity_info));
 
 	if (first) {
 		printk(KERN_INFO "%s Ver. %s\n",
@@ -2752,41 +2795,41 @@ static int velocity_found1(struct pci_dev *pdev,
 		first = 0;
 	}
 
-	velocity_init_info(pdev, vptr, info);
-
-	vptr->netdev = dev;
+	netdev->irq = irq;
+	vptr->bustype = bustype;
+	vptr->netdev = netdev;
+	vptr->dev = dev;
 
-	ret = pci_enable_device(pdev);
-	if (ret < 0)
-		goto err_free_dev;
+	velocity_init_info(vptr, info);
 
-	ret = velocity_get_pci_info(vptr, pdev);
-	if (ret < 0) {
-		/* error message already printed */
-		goto err_disable;
-	}
+	if (vptr->bustype == BUS_PCI) {
+		vptr->pdev = to_pci_dev(dev);
 
-	ret = pci_request_regions(pdev, VELOCITY_NAME);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "No PCI resources.\n");
-		goto err_disable;
+		ret = velocity_get_pci_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
+	} else {
+		ret = velocity_get_platform_info(vptr);
+		if (ret < 0)
+			goto err_free_dev;
 	}
 
 	regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
 	if (regs == NULL) {
 		ret = -EIO;
-		goto err_release_res;
+		goto err_free_dev;
 	}
 
 	vptr->mac_regs = regs;
+	vptr->rev_id = readb(&regs->rev_id);
 
 	mac_wol_reset(regs);
 
 	for (i = 0; i < 6; i++)
-		dev->dev_addr[i] = readb(&regs->PAR[i]);
+		netdev->dev_addr[i] = readb(&regs->PAR[i]);
 
 
-	drv_string = dev_driver_string(&pdev->dev);
+	drv_string = dev_driver_string(dev);
 
 	velocity_get_options(&vptr->options, velocity_nics, drv_string);
 
@@ -2807,46 +2850,125 @@ static int velocity_found1(struct pci_dev *pdev,
 
 	vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
 
-	dev->netdev_ops = &velocity_netdev_ops;
-	dev->ethtool_ops = &velocity_ethtool_ops;
-	netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
+	netdev->netdev_ops = &velocity_netdev_ops;
+	netdev->ethtool_ops = &velocity_ethtool_ops;
+	netif_napi_add(netdev, &vptr->napi, velocity_poll,
+							VELOCITY_NAPI_WEIGHT);
 
-	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
+	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
 			   NETIF_F_HW_VLAN_CTAG_TX;
-	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_FILTER |
-			 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_IP_CSUM;
+	netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
+			NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
+			NETIF_F_IP_CSUM;
 
-	ret = register_netdev(dev);
+	ret = register_netdev(netdev);
 	if (ret < 0)
 		goto err_iounmap;
 
-	if (!velocity_get_link(dev)) {
-		netif_carrier_off(dev);
+	if (!velocity_get_link(netdev)) {
+		netif_carrier_off(netdev);
 		vptr->mii_status |= VELOCITY_LINK_FAIL;
 	}
 
 	velocity_print_info(vptr);
-	pci_set_drvdata(pdev, dev);
+	dev_set_drvdata(vptr->dev, netdev);
 
 	/* and leave the chip powered down */
 
-	pci_set_power_state(pdev, PCI_D3hot);
+	velocity_set_power_state(vptr, PCI_D3hot);
 	velocity_nics++;
 out:
 	return ret;
 
 err_iounmap:
 	iounmap(regs);
-err_release_res:
-	pci_release_regions(pdev);
-err_disable:
-	pci_disable_device(pdev);
 err_free_dev:
-	free_netdev(dev);
+	free_netdev(netdev);
 	goto out;
 }
 
-#ifdef CONFIG_PM
+/**
+ *	velocity_remove	- device unplug
+ *	@dev: device being removed
+ *
+ *	Device unload callback. Called on an unplug or on module
+ *	unload for each active device that is present. Disconnects
+ *	the device from the network layer and frees all the resources
+ */
+static int velocity_remove(struct device *dev)
+{
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
+
+	unregister_netdev(netdev);
+	iounmap(vptr->mac_regs);
+	free_netdev(netdev);
+	velocity_nics--;
+
+	return 0;
+}
+
+static int velocity_pci_probe(struct pci_dev *pdev,
+			   const struct pci_device_id *ent)
+{
+	int ret;
+	const struct velocity_info_tbl *info =
+					&chip_info_table[ent->driver_data];
+
+	ret = pci_enable_device(pdev);
+	if (ret < 0)
+		return ret;
+
+	ret = pci_request_regions(pdev, VELOCITY_NAME);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "No PCI resources.\n");
+		pci_disable_device(pdev);
+		return ret;
+	}
+
+	ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
+	if (ret < 0) {
+		pci_release_regions(pdev);
+		pci_disable_device(pdev);
+	}
+
+	return ret;
+}
+
+static void velocity_pci_remove(struct pci_dev *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+}
+
+static int velocity_platform_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	const struct velocity_info_tbl *info;
+	int irq;
+
+	of_id = of_match_device(velocity_of_ids, &pdev->dev);
+	if (!of_id)
+		return -EINVAL;
+	info = of_id->data;
+
+	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+	if (!irq)
+		return -EINVAL;
+
+	return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
+}
+
+static int velocity_platform_remove(struct platform_device *pdev)
+{
+	velocity_remove(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
 /**
  *	wol_calc_crc		-	WOL CRC
  *	@pattern: data pattern
@@ -3003,10 +3125,10 @@ static void velocity_save_context(struct velocity_info *vptr, struct velocity_co
 
 }
 
-static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
+static int velocity_suspend(struct device *dev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 
 	if (!netif_running(vptr->netdev))
@@ -3015,20 +3137,23 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
 	netif_device_detach(vptr->netdev);
 
 	spin_lock_irqsave(&vptr->lock, flags);
-	pci_save_state(pdev);
+	if (vptr->bustype == BUS_PCI)
+		pci_save_state(vptr->pdev);
 
 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
 		velocity_get_ip(vptr);
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
 		velocity_set_wol(vptr);
-		pci_enable_wake(pdev, PCI_D3hot, 1);
-		pci_set_power_state(pdev, PCI_D3hot);
+		if (vptr->bustype == BUS_PCI)
+			pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	} else {
 		velocity_save_context(vptr, &vptr->context);
 		velocity_shutdown(vptr);
-		pci_disable_device(pdev);
-		pci_set_power_state(pdev, pci_choose_state(pdev, state));
+		if (vptr->bustype == BUS_PCI)
+			pci_disable_device(vptr->pdev);
+		velocity_set_power_state(vptr, PCI_D3hot);
 	}
 
 	spin_unlock_irqrestore(&vptr->lock, flags);
@@ -3070,19 +3195,22 @@ static void velocity_restore_context(struct velocity_info *vptr, struct velocity
 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
 }
 
-static int velocity_resume(struct pci_dev *pdev)
+static int velocity_resume(struct device *dev)
 {
-	struct net_device *dev = pci_get_drvdata(pdev);
-	struct velocity_info *vptr = netdev_priv(dev);
+	struct net_device *netdev = dev_get_drvdata(dev);
+	struct velocity_info *vptr = netdev_priv(netdev);
 	unsigned long flags;
 	int i;
 
 	if (!netif_running(vptr->netdev))
 		return 0;
 
-	pci_set_power_state(pdev, PCI_D0);
-	pci_enable_wake(pdev, 0, 0);
-	pci_restore_state(pdev);
+	velocity_set_power_state(vptr, PCI_D0);
+
+	if (vptr->bustype == BUS_PCI) {
+		pci_enable_wake(vptr->pdev, 0, 0);
+		pci_restore_state(vptr->pdev);
+	}
 
 	mac_wol_reset(vptr->mac_regs);
 
@@ -3104,23 +3232,34 @@ static int velocity_resume(struct pci_dev *pdev)
 
 	return 0;
 }
-#endif
+#endif	/* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
 
 /*
  *	Definition for our device driver. The PCI layer interface
  *	uses this to handle all our card discover and plugging
  */
-static struct pci_driver velocity_driver = {
+static struct pci_driver velocity_pci_driver = {
 	.name		= VELOCITY_NAME,
-	.id_table	= velocity_id_table,
-	.probe		= velocity_found1,
-	.remove		= velocity_remove1,
-#ifdef CONFIG_PM
-	.suspend	= velocity_suspend,
-	.resume		= velocity_resume,
-#endif
+	.id_table	= velocity_pci_id_table,
+	.probe		= velocity_pci_probe,
+	.remove		= velocity_pci_remove,
+	.driver = {
+		.pm = &velocity_pm_ops,
+	},
 };
 
+static struct platform_driver velocity_platform_driver = {
+	.probe		= velocity_platform_probe,
+	.remove		= velocity_platform_remove,
+	.driver = {
+		.name = "via-velocity",
+		.owner = THIS_MODULE,
+		.of_match_table = velocity_of_ids,
+		.pm = &velocity_pm_ops,
+	},
+};
 
 /**
  *	velocity_ethtool_up	-	pre hook for ethtool
@@ -3133,7 +3272,7 @@ static int velocity_ethtool_up(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D0);
+		velocity_set_power_state(vptr, PCI_D0);
 	return 0;
 }
 
@@ -3148,7 +3287,7 @@ static void velocity_ethtool_down(struct net_device *dev)
 {
 	struct velocity_info *vptr = netdev_priv(dev);
 	if (!netif_running(dev))
-		pci_set_power_state(vptr->pdev, PCI_D3hot);
+		velocity_set_power_state(vptr, PCI_D3hot);
 }
 
 static int velocity_get_settings(struct net_device *dev,
@@ -3270,7 +3409,11 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
 	struct velocity_info *vptr = netdev_priv(dev);
 	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
 	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
-	strlcpy(info->bus_info, pci_name(vptr->pdev), sizeof(info->bus_info));
+	if (vptr->bustype == BUS_PCI)
+		strlcpy(info->bus_info, pci_name(vptr->pdev),
+						sizeof(info->bus_info));
+	else
+		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
 }
 
 static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -3563,9 +3706,15 @@ static int __init velocity_init_module(void)
 	int ret;
 
 	velocity_register_notifier();
-	ret = pci_register_driver(&velocity_driver);
+
+	ret = pci_register_driver(&velocity_pci_driver);
+	if (ret < 0)
+		velocity_unregister_notifier();
+
+	ret = platform_driver_register(&velocity_platform_driver);
 	if (ret < 0)
 		velocity_unregister_notifier();
+
 	return ret;
 }
 
@@ -3580,7 +3729,9 @@ static int __init velocity_init_module(void)
 static void __exit velocity_cleanup_module(void)
 {
 	velocity_unregister_notifier();
-	pci_unregister_driver(&velocity_driver);
+
+	pci_unregister_driver(&velocity_pci_driver);
+	platform_driver_unregister(&velocity_platform_driver);
 }
 
 module_init(velocity_init_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
index c38bbae..1d94612 100644
--- a/drivers/net/ethernet/via/via-velocity.h
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -1265,7 +1265,7 @@ struct velocity_context {
 #define PHYID_VT3216_64BIT  0x000FC600UL
 #define PHYID_MARVELL_1000  0x01410C50UL
 #define PHYID_MARVELL_1000S 0x01410C40UL
-
+#define PHYID_ICPLUS_IP101A 0x02430C54UL
 #define PHYID_REV_ID_MASK   0x0000000FUL
 
 #define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
@@ -1433,10 +1433,17 @@ struct velocity_opt {
 
 #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
 
+enum velocity_bus_type {
+	BUS_PCI,
+	BUS_PLATFORM,
+};
+
 struct velocity_info {
-	struct device *dev;
 	struct pci_dev *pdev;
+	struct device *dev;
 	struct net_device *netdev;
+	enum velocity_bus_type bustype;
+	int no_eeprom;
 
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	u8 ip_addr[4];
-- 
1.7.9.5



From dt.tangr at gmail.com  Sat May 18 02:40:31 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 18 May 2013 16:40:31 +1000
Subject: [RFC PATCHv3 4/6] clocksource: Add TI-Nspire timer drivers
In-Reply-To: <CACRpkdaO7ieSdo5+Yq0+CLDfP==+DBOWn8+v0ap5iMOJy0Vf=Q@mail.gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>
 <CACRpkdZBFbOnQ9rCehO0yKDN7fH9VR3VYCa_NkOGJz7KN+02FQ@mail.gmail.com>
 <26FBB324-AAA9-4C10-8978-C2EC1C26672E@gmail.com>
 <CACRpkdaO7ieSdo5+Yq0+CLDfP==+DBOWn8+v0ap5iMOJy0Vf=Q@mail.gmail.com>
Message-ID: <6807056B-84F9-468D-87C6-4C4AD7D8BA99@gmail.com>


On 17/05/2013, at 11:17 PM, Linus Walleij <linus.walleij at linaro.org> wrote:

>>> If this timer is really just 16 bits, it's a *pretty* good idea to use
>>> the prescaler (I guess this is what IO_DIVIDER is) beacuse else you
>>> will get short sleep times with CONFIG_NO_HZ_IDLE on this system,
>>> and wake up unnecessarily often.
>>> 
>>> The same goes for the clock event.
>> 
>> The clock frequency is 32768Hz. Should I be scaling it down at that frequency?
> 
> No. But that was *pretty* slow.
> 
> The thing is that the driver is getting "some clockfrequency" from
> the clk subsystem and does not know what it is.
> 
> Usually (and I've seen this hardware design pattern a lot) when you
> have a clock like this, and go talk to the clk implementation specialist
> s/he will say "oh, yeah, I can mux in this 34 MHz clock to the timer
> as well", and if that is possible then that is often what you want,
> because it's good for things like HRtimers, and then it's useful to have
> a prescaler och the clocksource/clockevent.
> 
> You can use that 32768 Hz for clock events and clocksource (but I
> suspect that HRtimers will never be useful on this platform due to this).
> 

I forgot to mention before that there is also another timer that runs at the same freq as the APB (which is usually around 30MHz). Is this what you were alluding to? I haven't tested the driver on that timer yet.

As I understand it, you're saying to use a prescaler on faster clock rates so the kernel can have a longer maximum delay time (since a 16 bit register can only hold only so much). In that case, what kind of range should I be scaling to? I suspect it needs to be large enough to keep the kernel from constantly waking but small enough for HR timers to be useful.

> Yours,
> Linus Walleij



From laurent.pinchart at ideasonboard.com  Sat May 18 02:44:30 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Sat, 18 May 2013 08:44:30 +0200
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <Pine.LNX.4.64.1305171423270.31481@axis700.grange>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <Pine.LNX.4.64.1305171423270.31481@axis700.grange>
Message-ID: <14114689.gQXHdCTQYZ@avalon>

Hi Guennadi,

On Friday 17 May 2013 14:26:48 Guennadi Liakhovetski wrote:
> Hi Laurent
> 
> On Wed, 15 May 2013, Laurent Pinchart wrote:
> > Add GPIO controller nodes to the r8a7790 core device tree.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> > ---
> > 
> >  arch/arm/boot/dts/r8a7790.dtsi | 54 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> 
> Also here a couple of things are missing (presumably, for other SoCs you
> need the same):

Thank you for testing the patch set. I'll integrate the modification in the 
next version for r8a7778, r8a7779 and r8a7790.

As the gpio-ranges property specifies the number of GPIOs handled by the 
controller, what's your opinion on dropping the #gpio-lines property from the 
bindings ?

> diff --git a/arch/arm/boot/dts/r8a7790.dtsi
> b/arch/arm/boot/dts/r8a7790.dtsi
> index 674ee39..cd1a04f 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -51,6 +51,7 @@
>  		interrupts = <0 4 0x4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +		gpio-ranges = <&pfc 0 0 32>;
>  	};
> 
>  	gpio1: gpio at ffc41000 {
> @@ -60,6 +61,7 @@
>  		interrupts = <0 5 0x4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +		gpio-ranges = <&pfc 0 32 32>;
>  	};
> 
>  	gpio2: gpio at ffc42000 {
> @@ -69,6 +71,7 @@
>  		interrupts = <0 6 0x4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +		gpio-ranges = <&pfc 0 64 32>;
>  	};
> 
>  	gpio3: gpio at ffc43000 {
> @@ -78,6 +81,7 @@
>  		interrupts = <0 7 0x4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +		gpio-ranges = <&pfc 0 96 32>;
>  	};
> 
>  	gpio4: gpio at ffc44000 {
> @@ -87,6 +91,7 @@
>  		interrupts = <0 8 0x4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +		gpio-ranges = <&pfc 0 128 32>;
>  	};
> 
>  	gpio5: gpio at ffc45000 {
> @@ -96,6 +101,7 @@
>  		interrupts = <0 9 0x4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +		gpio-ranges = <&pfc 0 160 32>;
>  	};
> 
>  	timer {
> @@ -118,6 +124,7 @@
>  	pfc: pfc at e6060000 {
>  		compatible = "renesas,pfc-r8a7790";
>  		reg = <0 0xe6060000 0 0x250>;
> +		#gpio-range-cells = <3>;
>  	};
> 
>  	/* No MMC_CAP_UHS_DDR50 (dual data rate) capability on r8a7790! */

-- 
Regards,

Laurent Pinchart



From moinejf at free.fr  Sat May 18 02:56:59 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sat, 18 May 2013 08:56:59 +0200
Subject: [RFC 3/8] drm/i2c: nxp-tda998x: ensure VIP output mux is
 properly set
In-Reply-To: <E1Ud3og-0001qm-52@rmk-PC.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <E1Ud3og-0001qm-52@rmk-PC.arm.linux.org.uk>
Message-ID: <20130518085659.40932cd8@armhf>

On Thu, 16 May 2013 20:26:18 +0100
Russell King <rmk+kernel at arm.linux.org.uk> wrote:

> When switching between various drivers for this device, it's possible
> that some critical registers are left containing values which affect
> the device operation.  One such case encountered is the VIP output
> mux register.  This defaults to 0x24 on powerup, but other drivers may
> set this to 0x12.  This results in incorrect colours.
> 
> Fix this by ensuring that the register is always set to the power on
> default setting.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  drivers/gpu/drm/i2c/tda998x_drv.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
> index d71c408..4b4db95 100644
> --- a/drivers/gpu/drm/i2c/tda998x_drv.c
> +++ b/drivers/gpu/drm/i2c/tda998x_drv.c
> @@ -110,6 +110,7 @@ struct tda998x_priv {
>  #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
>  # define VIP_CNTRL_5_CKCASE       (1 << 0)
>  # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
> +#define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
>  #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
>  # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
>  # define MAT_CONTRL_MAT_BP        (1 << 2)
> @@ -438,6 +439,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
>  
>  	switch (mode) {
>  	case DRM_MODE_DPMS_ON:
> +		/* Write the default value MUX register */
> +		reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
>  		/* enable audio and video ports */
>  		reg_write(encoder, REG_ENA_AP, 0xff);
>  		reg_write(encoder, REG_ENA_VP_0, 0xff);

This register is never touched. Should not this setting better go at
reset time (in tda998x_reset)?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From g.liakhovetski at gmx.de  Sat May 18 02:57:41 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Sat, 18 May 2013 08:57:41 +0200 (CEST)
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <14114689.gQXHdCTQYZ@avalon>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1368577100-3530-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <Pine.LNX.4.64.1305171423270.31481@axis700.grange>
 <14114689.gQXHdCTQYZ@avalon>
Message-ID: <Pine.LNX.4.64.1305180851320.9241@axis700.grange>

Hi Laurent

On Sat, 18 May 2013, Laurent Pinchart wrote:

> Hi Guennadi,
> 
> On Friday 17 May 2013 14:26:48 Guennadi Liakhovetski wrote:
> > Hi Laurent
> > 
> > On Wed, 15 May 2013, Laurent Pinchart wrote:
> > > Add GPIO controller nodes to the r8a7790 core device tree.
> > > 
> > > Signed-off-by: Laurent Pinchart
> > > <laurent.pinchart+renesas at ideasonboard.com>
> > > ---
> > > 
> > >  arch/arm/boot/dts/r8a7790.dtsi | 54 +++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 54 insertions(+)
> > 
> > Also here a couple of things are missing (presumably, for other SoCs you
> > need the same):
> 
> Thank you for testing the patch set. I'll integrate the modification in the 
> next version for r8a7778, r8a7779 and r8a7790.
> 
> As the gpio-ranges property specifies the number of GPIOs handled by the 
> controller, what's your opinion on dropping the #gpio-lines property from the 
> bindings ?

Well, gpio-ranges can contain several ranges, so, in a generic case you 
would have to sum them up to get a total count. But if you're ok with that 
or if your platforms only have 1 gpio gange per controller, of course, 
that property seems redundant. OTOH it is already used in r8a7779.dtsi, 
and thus already belongs to the ABI... Not sure whether removing it would 
be accepted.

Thanks
Guennadi

> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi
> > b/arch/arm/boot/dts/r8a7790.dtsi
> > index 674ee39..cd1a04f 100644
> > --- a/arch/arm/boot/dts/r8a7790.dtsi
> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
> > @@ -51,6 +51,7 @@
> >  		interrupts = <0 4 0x4>;
> >  		#gpio-cells = <2>;
> >  		gpio-controller;
> > +		gpio-ranges = <&pfc 0 0 32>;
> >  	};
> > 
> >  	gpio1: gpio at ffc41000 {

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From laurent.pinchart at ideasonboard.com  Sat May 18 03:03:41 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Sat, 18 May 2013 09:03:41 +0200
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <Pine.LNX.4.64.1305180851320.9241@axis700.grange>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <14114689.gQXHdCTQYZ@avalon>
 <Pine.LNX.4.64.1305180851320.9241@axis700.grange>
Message-ID: <7692964.4oKpK3W9nB@avalon>

Hi Guennadi,

On Saturday 18 May 2013 08:57:41 Guennadi Liakhovetski wrote:
> On Sat, 18 May 2013, Laurent Pinchart wrote:
> > On Friday 17 May 2013 14:26:48 Guennadi Liakhovetski wrote:
> > > On Wed, 15 May 2013, Laurent Pinchart wrote:
> > > > Add GPIO controller nodes to the r8a7790 core device tree.
> > > > 
> > > > Signed-off-by: Laurent Pinchart 
> > > > <laurent.pinchart+renesas at ideasonboard.com>
> > > > ---
> > > > 
> > > >  arch/arm/boot/dts/r8a7790.dtsi | 54 +++++++++++++++++++++++++++++++++
> > > >  1 file changed, 54 insertions(+)
> > > 
> > > Also here a couple of things are missing (presumably, for other SoCs you
> > > need the same):
> >
> > Thank you for testing the patch set. I'll integrate the modification in
> > the next version for r8a7778, r8a7779 and r8a7790.
> > 
> > As the gpio-ranges property specifies the number of GPIOs handled by the
> > controller, what's your opinion on dropping the #gpio-lines property from
> > the bindings ?
> 
> Well, gpio-ranges can contain several ranges, so, in a generic case you
> would have to sum them up to get a total count. But if you're ok with that
> or if your platforms only have 1 gpio gange per controller, of course,
> that property seems redundant.

The gpio-rcar driver exposes a single range on all the current platforms. I 
don't really foresee any change there in the future, but I might be 
overlooking something. Magnus, any opinion ?

> OTOH it is already used in r8a7779.dtsi, and thus already belongs to the
> ABI... Not sure whether removing it would be accepted.

It's only used in my DT bindings proposal that haven't been merged yet, so 
that shouldn't be an issue :-)

-- 
Regards,

Laurent Pinchart



From dirk.behme at gmail.com  Sat May 18 03:25:28 2013
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sat, 18 May 2013 09:25:28 +0200
Subject: [PATCH] ARM: i.MX6: clk: add different DualLite MLB clock config
Message-ID: <1368861928-16141-1-git-send-email-dirk.behme@gmail.com>

The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.

Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock
configuration.

Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
---

Note: This patch is against Shawn's for-next branch
https://git.linaro.org/gitweb?p=people/shawnguo/linux-2.6.git;a=shortlog;h=refs/heads/for-next

 arch/arm/mach-imx/clk-imx6q.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 50095dd..63530dd 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -506,7 +506,14 @@ int __init mx6q_clocks_init(void)
 	clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
 	clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
 	clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-	clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
+	if (cpu_is_imx6dl())
+		/*
+		 * The multiplexer and divider of the imx6q clock gpu2d get
+		 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
+		 */
+		clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+	else
+		clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
 	clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
 	clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
 	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
-- 
1.7.10.4



From g.liakhovetski at gmx.de  Sat May 18 03:50:20 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Sat, 18 May 2013 09:50:20 +0200 (CEST)
Subject: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller
 devices to device tree
In-Reply-To: <7692964.4oKpK3W9nB@avalon>
References: <1368577100-3530-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <14114689.gQXHdCTQYZ@avalon> <Pine.LNX.4.64.1305180851320.9241@axis700.grange>
 <7692964.4oKpK3W9nB@avalon>
Message-ID: <Pine.LNX.4.64.1305180949480.9241@axis700.grange>

On Sat, 18 May 2013, Laurent Pinchart wrote:

> Hi Guennadi,
> 
> On Saturday 18 May 2013 08:57:41 Guennadi Liakhovetski wrote:
> > On Sat, 18 May 2013, Laurent Pinchart wrote:
> > > On Friday 17 May 2013 14:26:48 Guennadi Liakhovetski wrote:
> > > > On Wed, 15 May 2013, Laurent Pinchart wrote:
> > > > > Add GPIO controller nodes to the r8a7790 core device tree.
> > > > > 
> > > > > Signed-off-by: Laurent Pinchart 
> > > > > <laurent.pinchart+renesas at ideasonboard.com>
> > > > > ---
> > > > > 
> > > > >  arch/arm/boot/dts/r8a7790.dtsi | 54 +++++++++++++++++++++++++++++++++
> > > > >  1 file changed, 54 insertions(+)
> > > > 
> > > > Also here a couple of things are missing (presumably, for other SoCs you
> > > > need the same):
> > >
> > > Thank you for testing the patch set. I'll integrate the modification in
> > > the next version for r8a7778, r8a7779 and r8a7790.
> > > 
> > > As the gpio-ranges property specifies the number of GPIOs handled by the
> > > controller, what's your opinion on dropping the #gpio-lines property from
> > > the bindings ?
> > 
> > Well, gpio-ranges can contain several ranges, so, in a generic case you
> > would have to sum them up to get a total count. But if you're ok with that
> > or if your platforms only have 1 gpio gange per controller, of course,
> > that property seems redundant.
> 
> The gpio-rcar driver exposes a single range on all the current platforms. I 
> don't really foresee any change there in the future, but I might be 
> overlooking something. Magnus, any opinion ?
> 
> > OTOH it is already used in r8a7779.dtsi, and thus already belongs to the
> > ABI... Not sure whether removing it would be accepted.
> 
> It's only used in my DT bindings proposal that haven't been merged yet, so 
> that shouldn't be an issue :-)

Then yes, sure, you can add it any time in the future if needed, removing 
is more difficult ;-)

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From erappleman at gmail.com  Sat May 18 04:26:45 2013
From: erappleman at gmail.com (Eric Appleman)
Date: Sat, 18 May 2013 04:26:45 -0400
Subject: Would like to form a pool of Linux copyright holders for faster GPL
 enforcement against Anthrax Kernels
Message-ID: <51973B45.7040209@gmail.com>

Background on Anthrax Kernels and their GPL violation:
http://pastebin.com/X5Cciy03

Would anyone be interested in forming such a pool? I am willing to wait 
years for this to be resolved through certain organizations, but I 
believe we can do better.

Last I checked, I have 1 long-time poster of the gpl-violations list on 
board. Would anyone else like to join? Ideally I'd like to get the LKML 
(which I have CC'd among others) involved so that authors of critical 
Linux components be a part of this. I'm not sure if my defconfig commits 
to Android kernel branches count as contributions, so I'm not going to 
consider myself a Linux contributor unless told otherwise.

This pool would be used in the following manner:

* Formally requesting source for binaries (means to request source is 
actively hidden)
* Formally requesting removal of critical copyrighted code that Linux 
cannot function without
* Informing interested parties with respect to refusals of the above

The CTO of Anthrax's hosting server is very interested in terminating 
Chad Goodman's account. Bullet point #3 might come into effect here.

If this is a bad idea, breaks list etiquette, uses incorrect logic, or 
does not follow the conventions of GPL enforcement, feel free to shoot 
this idea down with utmost prejudice.

- Eric


From linux at prisktech.co.nz  Sat May 18 04:30:21 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 20:30:21 +1200
Subject: [PATCH 4/4] MAINTAINERS: vt8500: Add clk-vt8500.c to MAINTAINERS
 file
In-Reply-To: <CABjd4Yw2LbnaUbQFW_bd_6WRGTA34-Vp_tUC2b4Jczj-MM8x1w@mail.gmail.com>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
 <1368825532-30917-5-git-send-email-linux@prisktech.co.nz>
 <CABjd4Yw2LbnaUbQFW_bd_6WRGTA34-Vp_tUC2b4Jczj-MM8x1w@mail.gmail.com>
Message-ID: <51973C1D.2080404@prisktech.co.nz>

On 18/05/13 18:40, Alexey Charkov wrote:
> On 18 May 2013 01:18, "Tony Prisk" <linux at prisktech.co.nz> wrote:
>> This file has missed being added under ARM/VT8500 ARM ARCHITECTURE,
>> and is maintained along with the rest of the vt8500 arch code.
>>
>> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
>> ---
>>   MAINTAINERS |    1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 3d7782b..5ab8ccb 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1283,6 +1283,7 @@ M:        Tony Prisk <linux at prisktech.co.nz>
>>   L:     linux-arm-kernel at lists.infradead.org (moderated for
> non-subscribers)
>>   S:     Maintained
>>   F:     arch/arm/mach-vt8500/
>> +F:     drivers/clk/vt8500-vt8500.c
> This looks like a typo (clk vs. vt8500).
>
> Best,
> Alexey
>
eeek - oops.

Mike,

Disregard this patch - I will send a more complete one through arm-soc 
as there are other files missing as well.

Regards
Tony P


From linux at prisktech.co.nz  Sat May 18 05:15:10 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 21:15:10 +1200
Subject: [PATCH 0/4] FB updates for 3.11
Message-ID: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>

Patch #1 - Move register defines inside the driver and drop the header.
Patch #2 - Convert the register defines to use the vendor preferred names.
Patch #3 - Add a device clock to wm8505fb. Without it, only the uboot
initialized resolution is supported.
Patch #4 - Add support for the VGA output found on the APC8750 board.

Tony Prisk (4):
  fb: vt8500: Move register defines inside driver
  fb: vt8500: Convert to use vendor register names
  fb: vt8500: Require a device clock for wm8505fb driver
  fb: vt8500: Add VGA output support to wm8505fb driver.

 .../devicetree/bindings/video/wm,wm8505-fb.txt     |    9 +-
 drivers/video/wm8505fb.c                           |  195 ++++++++++++--
 drivers/video/wm8505fb_regs.h                      |   76 ------
 drivers/video/wmt_ge_rops.c                        |  280 +++++++++++++++-----
 4 files changed, 394 insertions(+), 166 deletions(-)
 delete mode 100644 drivers/video/wm8505fb_regs.h

-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 05:15:13 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 21:15:13 +1200
Subject: [PATCH 3/4] fb: vt8500: Require a device clock for wm8505fb driver
In-Reply-To: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368868514-18975-4-git-send-email-linux@prisktech.co.nz>

The wm8505fb driver requires a clock to work properly. Without a clock,
the driver can only initialize the display resolution that was set in
uboot.
This patch updates the driver to get and use a clock, and updates
the devicetree documentation to indicate the requirement for a clock.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |    4 ++-
 drivers/video/wm8505fb.c                           |   30 +++++++++++++++++---
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
index 0bcadb2..601416c 100644
--- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -5,6 +5,7 @@ Required properties:
 - compatible : "wm,wm8505-fb"
 - reg : Should contain 1 register ranges(address and length)
 - bits-per-pixel : bit depth of framebuffer (16 or 32)
+- clocks : phandle to DVO clock
 
 Required subnodes:
 - display-timings: see display-timing.txt for information
@@ -15,11 +16,12 @@ Example:
 		compatible = "wm,wm8505-fb";
 		reg = <0xd8051700 0x200>;
 		bits-per-pixel = <16>;
+		clocks = <&clkdvo>;
 
 		display-timings {
 			native-mode = <&timing0>;
 			timing0: 800x480 {
-				clock-frequency = <0>; /* unused but required */
+				clock-frequency = <30000000>;
 				hactive = <800>;
 				vactive = <480>;
 				hfront-porch = <40>;
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index 167a9e2..f8bffc2 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/fb.h>
@@ -130,9 +131,11 @@
 #define to_wm8505fb_info(__info) container_of(__info, \
 						struct wm8505fb_info, fb)
 struct wm8505fb_info {
-	struct fb_info		fb;
-	void __iomem		*regbase;
-	unsigned int		contrast;
+	struct fb_info fb;
+	void __iomem *regbase;
+	unsigned int contrast;
+	struct device *dev;
+	struct clk *clk_dvo;
 };
 
 
@@ -210,6 +213,13 @@ static int wm8505fb_set_par(struct fb_info *info)
 	if (!fbi)
 		return -EINVAL;
 
+	if (info->var.pixclock == 0) {
+		dev_err(fbi->dev, "requested pixclock = 0\n");
+		return -EINVAL;
+	}
+
+	clk_set_rate(fbi->clk_dvo, PICOS2KHZ(info->var.pixclock)*1000);
+
 	if (info->var.bits_per_pixel == 32) {
 		info->var.red.offset = 16;
 		info->var.red.length = 8;
@@ -369,6 +379,8 @@ static int wm8505fb_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
+	fbi->dev = &pdev->dev;
+
 	strcpy(fbi->fb.fix.id, DRIVER_NAME);
 
 	fbi->fb.fix.type	= FB_TYPE_PACKED_PIXELS;
@@ -408,6 +420,14 @@ static int wm8505fb_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	fbi->clk_dvo = of_clk_get(pdev->dev.of_node, 0);
+	if (IS_ERR(fbi->clk_dvo)) {
+		dev_err(&pdev->dev, "Error retrieving clock\n");
+		return PTR_ERR(fbi->clk_dvo);
+	}
+
+	clk_prepare_enable(fbi->clk_dvo);
+
 	fb_videomode_to_var(&fbi->fb.var, &mode);
 
 	fbi->fb.var.nonstd		= 0;
@@ -421,7 +441,7 @@ static int wm8505fb_probe(struct platform_device *pdev)
 	fb_mem_virt = dmam_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
 				GFP_KERNEL);
 	if (!fb_mem_virt) {
-		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		dev_err(&pdev->dev, "Failed to allocate framebuffer\n");
 		return -ENOMEM;
 	}
 
@@ -480,6 +500,8 @@ static int wm8505fb_remove(struct platform_device *pdev)
 
 	unregister_framebuffer(&fbi->fb);
 
+	clk_disable_unprepare(fbi->clk_dvo);
+
 	writel(0, fbi->regbase);
 
 	if (fbi->fb.cmap.len)
-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 05:15:14 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 21:15:14 +1200
Subject: [PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.
In-Reply-To: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368868514-18975-5-git-send-email-linux@prisktech.co.nz>

The APC8750 does not support an LCD panel, but provides a VGA connector.
This patch adds support for the VGA interface, and defines an optional
devicetree property to specify the output interface. The default if not
specified is LCD for backward compatibility.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |    5 ++++
 drivers/video/wm8505fb.c                           |   31 ++++++++++++++++++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
index 601416c..9f1d648 100644
--- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -7,6 +7,10 @@ Required properties:
 - bits-per-pixel : bit depth of framebuffer (16 or 32)
 - clocks : phandle to DVO clock
 
+Optional properties:
+- output-interface : the interface the fb should output on. Valid values are
+	"lcd" or "vga". If not specified, the default is "lcd".
+
 Required subnodes:
 - display-timings: see display-timing.txt for information
 
@@ -17,6 +21,7 @@ Example:
 		reg = <0xd8051700 0x200>;
 		bits-per-pixel = <16>;
 		clocks = <&clkdvo>;
+		output-interface = "vga";
 
 		display-timings {
 			native-mode = <&timing0>;
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index f8bffc2..d1f7f33 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -130,12 +130,17 @@
 
 #define to_wm8505fb_info(__info) container_of(__info, \
 						struct wm8505fb_info, fb)
+
+#define INTERFACE_LCD	1
+#define INTERFACE_VGA	2
+
 struct wm8505fb_info {
 	struct fb_info fb;
 	void __iomem *regbase;
 	unsigned int contrast;
 	struct device *dev;
 	struct clk *clk_dvo;
+	int interface;
 };
 
 
@@ -158,7 +163,11 @@ static int wm8505fb_init_hw(struct fb_info *info)
 	 * 0x31C sets the correct color mode (RGB565) for WM8650
 	 * Bit 8+9 (0x300) are ignored on WM8505 as reserved
 	 */
-	writel(0x31c,		       fbi->regbase + REG_GOVRH_YUVRGB);
+	if (fbi->interface == INTERFACE_VGA)
+		writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB);
+	else
+		writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);
+
 	writel(1,		       fbi->regbase + REG_GOVRH_DVO_PIX);
 
 	/* Virtual buffer size */
@@ -167,7 +176,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
 
 	/* black magic ;) */
 	writel(0xf,		       fbi->regbase + REG_GOVRH_FHI);
-	writel(4,		       fbi->regbase + REG_GOVRH_DVO_SET);
+
+	if (fbi->interface == INTERFACE_VGA)
+		writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET);
+	else
+		writel(4, fbi->regbase + REG_GOVRH_DVO_SET);
+
 	writel(1,		       fbi->regbase + REG_GOVRH_MIF);
 	writel(1,		       fbi->regbase + REG_GOVRH_REG_STS);
 
@@ -194,11 +208,15 @@ static int wm8505fb_set_timing(struct fb_info *info)
 	writel(h_end,   fbi->regbase + REG_GOVRH_ACTPX_END);
 	writel(h_all,   fbi->regbase + REG_GOVRH_H_ALLPXL);
 	writel(h_sync,  fbi->regbase + REG_GOVRH_HDMI_HSYNW);
+	if (fbi->interface == INTERFACE_VGA)
+		writel(h_sync,  fbi->regbase + REG_GOVRH_VGA_HSYNW);
 
 	writel(v_start, fbi->regbase + REG_GOVRH_ACTLN_BG);
 	writel(v_end,   fbi->regbase + REG_GOVRH_ACTLN_END);
 	writel(v_all,   fbi->regbase + REG_GOVRH_V_ALLLN);
 	writel(v_sync,  fbi->regbase + REG_GOVRH_HDMI_VBISW);
+	if (fbi->interface == INTERFACE_VGA)
+		writel(info->var.pixclock,  fbi->regbase + REG_GOVRH_VGA_VSYNW);
 
 	writel(1, fbi->regbase + REG_GOVRH_TG_ENABLE);
 
@@ -371,6 +389,7 @@ static int wm8505fb_probe(struct platform_device *pdev)
 	dma_addr_t fb_mem_phys;
 	unsigned long fb_mem_len;
 	void *fb_mem_virt;
+	const char *intf;
 
 	fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
 			sizeof(u32) * 16, GFP_KERNEL);
@@ -428,6 +447,14 @@ static int wm8505fb_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(fbi->clk_dvo);
 
+	fbi->interface = INTERFACE_LCD;
+	ret = of_property_read_string(pdev->dev.of_node, "output-interface",
+					&intf);
+	if (!ret) {
+		if (!strcmp(intf, "vga"))
+			fbi->interface = INTERFACE_VGA;
+	}
+
 	fb_videomode_to_var(&fbi->fb.var, &mode);
 
 	fbi->fb.var.nonstd		= 0;
-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 05:15:11 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 21:15:11 +1200
Subject: [PATCH 1/4] fb: vt8500: Move register defines inside driver
In-Reply-To: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368868514-18975-2-git-send-email-linux@prisktech.co.nz>

The #defines in wm8505fb_regs.h are only used in the wm8505fb driver,
and don't need to be visible outside.

Move the defines into the driver and remove the header.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/video/wm8505fb.c      |   25 +++++++++++++-
 drivers/video/wm8505fb_regs.h |   76 -----------------------------------------
 2 files changed, 24 insertions(+), 77 deletions(-)
 delete mode 100644 drivers/video/wm8505fb_regs.h

diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index 01f9ace..f824af8 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -34,11 +34,34 @@
 #include <linux/wait.h>
 #include <video/of_display_timing.h>
 
-#include "wm8505fb_regs.h"
 #include "wmt_ge_rops.h"
 
 #define DRIVER_NAME "wm8505-fb"
 
+#define WMT_GOVR_COLORSPACE1	0x030
+#define WMT_GOVR_MIF_ENABLE	0x080
+#define WMT_GOVR_FBADDR		0x090
+#define WMT_GOVR_FBADDR1	0x094
+#define WMT_GOVR_XRES		0x098
+#define WMT_GOVR_XRES_VIRTUAL	0x09c
+#define WMT_GOVR_YPAN		0x0a0
+#define WMT_GOVR_XPAN		0x0a4
+#define WMT_GOVR_FHI		0x0a8
+#define WMT_GOVR_REG_UPDATE	0x0e4
+#define WMT_GOVR_TG		0x100
+#define WMT_GOVR_TIMING_H_ALL	0x108
+#define WMT_GOVR_TIMING_V_ALL	0x10c
+#define WMT_GOVR_TIMING_V_START	0x110
+#define WMT_GOVR_TIMING_V_END	0x114
+#define WMT_GOVR_TIMING_H_START	0x118
+#define WMT_GOVR_TIMING_H_END	0x11c
+#define WMT_GOVR_TIMING_V_SYNC	0x128
+#define WMT_GOVR_TIMING_H_SYNC	0x12c
+#define WMT_GOVR_DVO_SET	0x148
+#define WMT_GOVR_CONTRAST	0x1b8
+#define WMT_GOVR_BRGHTNESS	0x1bc
+#define WMT_GOVR_COLORSPACE	0x1e4
+
 #define to_wm8505fb_info(__info) container_of(__info, \
 						struct wm8505fb_info, fb)
 struct wm8505fb_info {
diff --git a/drivers/video/wm8505fb_regs.h b/drivers/video/wm8505fb_regs.h
deleted file mode 100644
index 4dd4166..0000000
--- a/drivers/video/wm8505fb_regs.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *  GOVR registers list for WM8505 chips
- *
- *  Copyright (C) 2010 Ed Spiridonov <edo.rus at gmail.com>
- *   Based on VIA/WonderMedia wm8510-govrh-reg.h
- *   http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/
- *         drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _WM8505FB_REGS_H
-#define _WM8505FB_REGS_H
-
-/*
- * Color space select register, default value 0x1c
- *   BIT0 GOVRH_DVO_YUV2RGB_ENABLE
- *   BIT1 GOVRH_VGA_YUV2RGB_ENABLE
- *   BIT2 GOVRH_RGB_MODE
- *   BIT3 GOVRH_DAC_CLKINV
- *   BIT4 GOVRH_BLANK_ZERO
- */
-#define WMT_GOVR_COLORSPACE	0x1e4
-/*
- * Another colorspace select register, default value 1
- *   BIT0 GOVRH_DVO_RGB
- *   BIT1 GOVRH_DVO_YUV422
- */
-#define WMT_GOVR_COLORSPACE1	 0x30
-
-#define WMT_GOVR_CONTRAST	0x1b8
-#define WMT_GOVR_BRGHTNESS	0x1bc /* incompatible with RGB? */
-
-/* Framubeffer address */
-#define WMT_GOVR_FBADDR		 0x90
-#define WMT_GOVR_FBADDR1	 0x94 /* UV offset in YUV mode */
-
-/* Offset of visible window */
-#define WMT_GOVR_XPAN		 0xa4
-#define WMT_GOVR_YPAN		 0xa0
-
-#define WMT_GOVR_XRES		 0x98
-#define WMT_GOVR_XRES_VIRTUAL	 0x9c
-
-#define WMT_GOVR_MIF_ENABLE	 0x80
-#define WMT_GOVR_FHI		 0xa8
-#define WMT_GOVR_REG_UPDATE	 0xe4
-
-/*
- *   BIT0 GOVRH_DVO_OUTWIDTH
- *   BIT1 GOVRH_DVO_SYNC_POLAR
- *   BIT2 GOVRH_DVO_ENABLE
- */
-#define WMT_GOVR_DVO_SET	0x148
-
-/* Timing generator? */
-#define WMT_GOVR_TG		0x100
-
-/* Timings */
-#define WMT_GOVR_TIMING_H_ALL	0x108
-#define WMT_GOVR_TIMING_V_ALL	0x10c
-#define WMT_GOVR_TIMING_V_START	0x110
-#define WMT_GOVR_TIMING_V_END	0x114
-#define WMT_GOVR_TIMING_H_START	0x118
-#define WMT_GOVR_TIMING_H_END	0x11c
-#define WMT_GOVR_TIMING_V_SYNC	0x128
-#define WMT_GOVR_TIMING_H_SYNC	0x12c
-
-#endif /* _WM8505FB_REGS_H */
-- 
1.7.9.5



From linux at prisktech.co.nz  Sat May 18 05:15:12 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sat, 18 May 2013 21:15:12 +1200
Subject: [PATCH 2/4] fb: vt8500: Convert to use vendor register names
In-Reply-To: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1368868514-18975-3-git-send-email-linux@prisktech.co.nz>

Change all the #defines to match the vendor defined names, and change the
references in wm8505fb.c and wmt_ge_rops.c.
Add all the missing register offsets as well to prevent churn in the future.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/video/wm8505fb.c    |  159 ++++++++++++++++--------
 drivers/video/wmt_ge_rops.c |  280 +++++++++++++++++++++++++++++++++----------
 2 files changed, 332 insertions(+), 107 deletions(-)

diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index f824af8..167a9e2 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -38,29 +38,94 @@
 
 #define DRIVER_NAME "wm8505-fb"
 
-#define WMT_GOVR_COLORSPACE1	0x030
-#define WMT_GOVR_MIF_ENABLE	0x080
-#define WMT_GOVR_FBADDR		0x090
-#define WMT_GOVR_FBADDR1	0x094
-#define WMT_GOVR_XRES		0x098
-#define WMT_GOVR_XRES_VIRTUAL	0x09c
-#define WMT_GOVR_YPAN		0x0a0
-#define WMT_GOVR_XPAN		0x0a4
-#define WMT_GOVR_FHI		0x0a8
-#define WMT_GOVR_REG_UPDATE	0x0e4
-#define WMT_GOVR_TG		0x100
-#define WMT_GOVR_TIMING_H_ALL	0x108
-#define WMT_GOVR_TIMING_V_ALL	0x10c
-#define WMT_GOVR_TIMING_V_START	0x110
-#define WMT_GOVR_TIMING_V_END	0x114
-#define WMT_GOVR_TIMING_H_START	0x118
-#define WMT_GOVR_TIMING_H_END	0x11c
-#define WMT_GOVR_TIMING_V_SYNC	0x128
-#define WMT_GOVR_TIMING_H_SYNC	0x12c
-#define WMT_GOVR_DVO_SET	0x148
-#define WMT_GOVR_CONTRAST	0x1b8
-#define WMT_GOVR_BRGHTNESS	0x1bc
-#define WMT_GOVR_COLORSPACE	0x1e4
+#define REG_GOVRH_CUR_ADDR		0x0000
+#define REG_GOVRH_CUR_WIDTH		0x0004
+#define REG_GOVRH_CUR_FB_WIDTH		0x0008
+#define REG_GOVRH_CUR_VCROP		0x000C
+#define REG_GOVRH_CUR_HCROP		0x0010
+#define REG_GOVRH_CUR_HCOORD		0x0014
+#define REG_GOVRH_CUR_VCOORD		0x0018
+#define REG_GOVRH_CUR_STATUS		0x001C
+#define REG_GOVRH_CUR_COLOR_KEY		0x0020
+#define REG_GOVRH_DVO_PIX		0x0030
+#define REG_GOVRH_DVO_DLY_SEL		0x0034
+#define REG_GOVRH_INT			0x0038
+#define REG_GOVRH_DVO_BLANK_DATA	0x003C
+#define REG_GOVRH_DIRPATH		0x0040	/* WM8750+ */
+#define REG_GOVRH_MIF			0x0080
+#define REG_GOVRH_COLFMT		0x0084
+#define REG_GOVRH_SRCFMT		0x0088
+#define REG_GOVRH_DSTFMT		0x008C
+#define REG_GOVRH_YSA			0x0090
+#define REG_GOVRH_CSA			0x0094
+#define REG_GOVRH_PIXWID		0x0098
+#define REG_GOVRH_BUFWID		0x009C
+#define REG_GOVRH_VCROP			0x00A0
+#define REG_GOVRH_HCROP			0x00A4
+#define REG_GOVRH_FHI			0x00A8
+#define REG_GOVRH_COLFMT2		0x00AC
+#define REG_GOVRH_YSA2			0x00B0	/* WM8950 */
+#define REG_GOVRH_CSA2			0x00B4	/* WM8950 */
+#define REG_GOVRH_MIF_FRAME_MODE	0x00B8	/* WM8950 */
+#define REG_GOVRH_REG_STS		0x00E4
+#define REG_GOVRH_SWFLD			0x00E8
+#define REG_GOVRH_TG_ENABLE		0x0100
+#define REG_GOVRH_READ_CYC		0x0104
+#define REG_GOVRH_H_ALLPXL		0x0108
+#define REG_GOVRH_V_ALLLN		0x010C
+#define REG_GOVRH_ACTLN_BG		0x0110
+#define REG_GOVRH_ACTLN_END		0x0114
+#define REG_GOVRH_ACTPX_BG		0x0118
+#define REG_GOVRH_ACTPX_END		0x011C
+#define REG_GOVRH_VBIE_LINE		0x0120
+#define REG_GOVRH_PVBI_LINE		0x0124
+#define REG_GOVRH_HDMI_VBISW		0x0128
+#define REG_GOVRH_HDMI_HSYNW		0x012C
+#define REG_GOVRH_VSYNC_OFFSET		0x0130
+#define REG_GOVRH_FIELD_STATUS		0x0134
+#define REG_GOVRH_HDMI_3D		0x013C	/* WM8950 */
+#define REG_GOVRH_DVO_SET		0x0148
+#define REG_GOVRH_CB_ENABLE		0x0150
+#define REG_GOVRH_H_ALLPXL2		0x0158
+#define REG_GOVRH_V_ALLLN2		0x015C
+#define REG_GOVRH_ACTLN_BG2		0x0160
+#define REG_GOVRH_ACTLN_END2		0x0164
+#define REG_GOVRH_ACTPX_BG2		0x0168
+#define REG_GOVRH_ACTPX_END2		0x016C
+#define REG_GOVRH_VBIE_LINE2		0x0170
+#define REG_GOVRH_PVBI_LINE2		0x0174
+#define REG_GOVRH_HDMI_VBISW2		0x0178
+#define REG_GOVRH_HDMI_HSYNW2		0x017C
+#define REG_GOVRH_LVDS_CTRL		0x0180	/* WM8750+ */
+#define REG_GOVRH_LVDS_CTRL2		0x0184	/* WM8750+ */
+#define REG_GOVRH_DAC_LP_SENSE_VAL	0x0188	/* WM8750 */
+#define REG_GOVRH_DAC_TEST_MODE		0x018C	/* WM8750 */
+#define REG_GOVRH_VGA_HSYNW		0x0190	/* WM8750 */
+#define REG_GOVRH_VGA_VSYNW		0x0194	/* WM8750 */
+#define REG_GOVRH_VGA_SYNPOLAR		0x0198	/* WM8750 */
+#define REG_GOVRH_DAC_MOD		0x019C	/* WM8750 */
+#define REG_GOVRH_DAC_VAL		0x01A0	/* WM8750 */
+#define REG_GOVRH_DAC_CON		0x01A4	/* WM8750 */
+#define REG_GOVRH_DAC_TEST		0x01A8	/* WM8750 */
+#define REG_GOVRH_DAC_BTEST		0x01AC	/* WM8750 */
+#define REG_GOVRH_DAC_CTEST		0x01B0	/* WM8750 */
+#define REG_GOVRH_DAC_DBG		0x01B4	/* WM8750 */
+#define REG_GOVRH_CONTRAST		0x01B8
+#define REG_GOVRH_BRIGHTNESS		0x01BC
+#define REG_GOVRH_DMACSC_COEF0		0x01C0
+#define REG_GOVRH_DMACSC_COEF1		0x01C4
+#define REG_GOVRH_DMACSC_COEF2		0x01C8
+#define REG_GOVRH_DMACSC_COEF3		0x01CC
+#define REG_GOVRH_DMACSC_COEF4		0x01D0
+#define REG_GOVRH_DMACSC_COEF5		0x01D8
+#define REG_GOVRH_DMACSC_COEF6		0x01DC
+#define REG_GOVRH_CSC_MODE		0x01E0
+#define REG_GOVRH_YUVRGB		0x01E4
+#define REG_GOVRH_H264_INPUT_EN		0x01E8
+#define REG_GOVRH_DISP_EN		0x01EC	/* WM8750 */
+#define REG_GOVRH_HSCALE_UP		0x01F4
+#define REG_GOVRH_IGS_MODE		0x01F8
+#define REG_GOVRH_IGS_MODE2		0x01FC
 
 #define to_wm8505fb_info(__info) container_of(__info, \
 						struct wm8505fb_info, fb)
@@ -82,26 +147,26 @@ static int wm8505fb_init_hw(struct fb_info *info)
 		writel(0, fbi->regbase + i);
 
 	/* Set frame buffer address */
-	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
-	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
+	writel(fbi->fb.fix.smem_start, fbi->regbase + REG_GOVRH_YSA);
+	writel(fbi->fb.fix.smem_start, fbi->regbase + REG_GOVRH_CSA);
 
 	/*
 	 * Set in-memory picture format to RGB
 	 * 0x31C sets the correct color mode (RGB565) for WM8650
 	 * Bit 8+9 (0x300) are ignored on WM8505 as reserved
 	 */
-	writel(0x31c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
-	writel(1,		       fbi->regbase + WMT_GOVR_COLORSPACE1);
+	writel(0x31c,		       fbi->regbase + REG_GOVRH_YUVRGB);
+	writel(1,		       fbi->regbase + REG_GOVRH_DVO_PIX);
 
 	/* Virtual buffer size */
-	writel(info->var.xres,	       fbi->regbase + WMT_GOVR_XRES);
-	writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL);
+	writel(info->var.xres,	       fbi->regbase + REG_GOVRH_PIXWID);
+	writel(info->var.xres_virtual, fbi->regbase + REG_GOVRH_BUFWID);
 
 	/* black magic ;) */
-	writel(0xf,		       fbi->regbase + WMT_GOVR_FHI);
-	writel(4,		       fbi->regbase + WMT_GOVR_DVO_SET);
-	writel(1,		       fbi->regbase + WMT_GOVR_MIF_ENABLE);
-	writel(1,		       fbi->regbase + WMT_GOVR_REG_UPDATE);
+	writel(0xf,		       fbi->regbase + REG_GOVRH_FHI);
+	writel(4,		       fbi->regbase + REG_GOVRH_DVO_SET);
+	writel(1,		       fbi->regbase + REG_GOVRH_MIF);
+	writel(1,		       fbi->regbase + REG_GOVRH_REG_STS);
 
 	return 0;
 }
@@ -120,19 +185,19 @@ static int wm8505fb_set_timing(struct fb_info *info)
 	int v_all = v_end + info->var.lower_margin;
 	int v_sync = info->var.vsync_len;
 
-	writel(0, fbi->regbase + WMT_GOVR_TG);
+	writel(0, fbi->regbase + REG_GOVRH_TG_ENABLE);
 
-	writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START);
-	writel(h_end,   fbi->regbase + WMT_GOVR_TIMING_H_END);
-	writel(h_all,   fbi->regbase + WMT_GOVR_TIMING_H_ALL);
-	writel(h_sync,  fbi->regbase + WMT_GOVR_TIMING_H_SYNC);
+	writel(h_start, fbi->regbase + REG_GOVRH_ACTPX_BG);
+	writel(h_end,   fbi->regbase + REG_GOVRH_ACTPX_END);
+	writel(h_all,   fbi->regbase + REG_GOVRH_H_ALLPXL);
+	writel(h_sync,  fbi->regbase + REG_GOVRH_HDMI_HSYNW);
 
-	writel(v_start, fbi->regbase + WMT_GOVR_TIMING_V_START);
-	writel(v_end,   fbi->regbase + WMT_GOVR_TIMING_V_END);
-	writel(v_all,   fbi->regbase + WMT_GOVR_TIMING_V_ALL);
-	writel(v_sync,  fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
+	writel(v_start, fbi->regbase + REG_GOVRH_ACTLN_BG);
+	writel(v_end,   fbi->regbase + REG_GOVRH_ACTLN_END);
+	writel(v_all,   fbi->regbase + REG_GOVRH_V_ALLLN);
+	writel(v_sync,  fbi->regbase + REG_GOVRH_HDMI_VBISW);
 
-	writel(1, fbi->regbase + WMT_GOVR_TG);
+	writel(1, fbi->regbase + REG_GOVRH_TG_ENABLE);
 
 	return 0;
 }
@@ -174,7 +239,7 @@ static int wm8505fb_set_par(struct fb_info *info)
 	wm8505fb_set_timing(info);
 
 	writel(fbi->contrast<<16 | fbi->contrast<<8 | fbi->contrast,
-		fbi->regbase + WMT_GOVR_CONTRAST);
+		fbi->regbase + REG_GOVRH_CONTRAST);
 
 	return 0;
 }
@@ -250,8 +315,8 @@ static int wm8505fb_pan_display(struct fb_var_screeninfo *var,
 {
 	struct wm8505fb_info *fbi = to_wm8505fb_info(info);
 
-	writel(var->xoffset, fbi->regbase + WMT_GOVR_XPAN);
-	writel(var->yoffset, fbi->regbase + WMT_GOVR_YPAN);
+	writel(var->xoffset, fbi->regbase + REG_GOVRH_VCROP);
+	writel(var->yoffset, fbi->regbase + REG_GOVRH_HCROP);
 	return 0;
 }
 
@@ -264,7 +329,7 @@ static int wm8505fb_blank(int blank, struct fb_info *info)
 		wm8505fb_set_timing(info);
 		break;
 	default:
-		writel(0,  fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
+		writel(0,  fbi->regbase + REG_GOVRH_HDMI_VBISW);
 		break;
 	}
 
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c
index 4aaeb18..68de46a 100644
--- a/drivers/video/wmt_ge_rops.c
+++ b/drivers/video/wmt_ge_rops.c
@@ -20,29 +20,189 @@
 #include <linux/platform_device.h>
 #include "fb_draw.h"
 
-#define GE_COMMAND_OFF		0x00
-#define GE_DEPTH_OFF		0x04
-#define GE_HIGHCOLOR_OFF	0x08
-#define GE_ROPCODE_OFF		0x14
-#define GE_FIRE_OFF		0x18
-#define GE_SRCBASE_OFF		0x20
-#define GE_SRCDISPW_OFF		0x24
-#define GE_SRCDISPH_OFF		0x28
-#define GE_SRCAREAX_OFF		0x2c
-#define GE_SRCAREAY_OFF		0x30
-#define GE_SRCAREAW_OFF		0x34
-#define GE_SRCAREAH_OFF		0x38
-#define GE_DESTBASE_OFF		0x3c
-#define GE_DESTDISPW_OFF	0x40
-#define GE_DESTDISPH_OFF	0x44
-#define GE_DESTAREAX_OFF	0x48
-#define GE_DESTAREAY_OFF	0x4c
-#define GE_DESTAREAW_OFF	0x50
-#define GE_DESTAREAH_OFF	0x54
-#define GE_PAT0C_OFF		0x88	/* Pattern 0 color */
-#define GE_ENABLE_OFF		0xec
-#define GE_INTEN_OFF		0xf0
-#define GE_STATUS_OFF		0xf8
+#define GE_COMMAND		0x0000
+#define GE_COLOR_DEPTH		0x0004
+#define GE_HM_SEL		0x0008
+#define GE_PAT_TRAN_EN		0x000C
+#define GE_FONT_TRAN_EN		0x0010
+#define GE_ROP_CODE		0x0014
+#define GE_FIRE			0x0018
+#define GE_ROP_BG_CODE		0x001C
+#define GE_SRC_BADDR		0x0020
+#define GE_SRC_DISP_W		0x0024
+#define GE_SRC_DISP_H		0x0028
+#define GE_SRC_X_START		0x002C
+#define GE_SRC_Y_START		0x0030
+#define GE_SRC_WIDTH		0x0034
+#define GE_SRC_HEIGHT		0x0038
+#define GE_DES_BADDR		0x003C
+#define GE_DES_DISP_W		0x0040
+#define GE_DES_DISP_H		0x0044
+#define GE_DES_X_START		0x0048
+#define GE_DES_Y_START		0x004C
+#define GE_DES_WIDTH		0x0050
+#define GE_DES_HEIGHT		0x0054
+#define GE_FONT0_BUF		0x0058
+#define GE_FONT1_BUF		0x005C
+#define GE_FONT2_BUF		0x0060
+#define GE_FONT3_BUF		0x0064
+#define GE_PAT0_BUF		0x0068
+#define GE_PAT1_BUF		0x006C
+#define GE_PAT2_BUF		0x0070
+#define GE_PAT3_BUF		0x0074
+#define GE_PAT4_BUF		0x0078
+#define GE_PAT5_BUF		0x007C
+#define GE_PAT6_BUF		0x0080
+#define GE_PAT7_BUF		0x0084
+#define GE_PAT0_COLOR		0x0088
+#define GE_PAT1_COLOR		0x008C
+#define GE_PAT2_COLOR		0x0090
+#define GE_PAT3_COLOR		0x0094
+#define GE_PAT4_COLOR		0x0098
+#define GE_PAT5_COLOR		0x009C
+#define GE_PAT6_COLOR		0x00A0
+#define GE_PAT7_COLOR		0x00A4
+#define GE_PAT8_COLOR		0x00A8
+#define GE_PAT9_COLOR		0x00AC
+#define GE_PAT10_COLOR		0x00B0
+#define GE_PAT11_COLOR		0x00B4
+#define GE_PAT12_COLOR		0x00B8
+#define GE_PAT13_COLOR		0x00BC
+#define GE_PAT14_COLOR		0x00C0
+#define GE_PAT15_COLOR		0x00C4
+#define GE_CK_SEL		0x00C8
+#define GE_SRC_CK		0x00CC
+#define GE_DES_CK		0x00D0
+#define GE_ALPHA_SEL		0x00D4
+#define GE_BITBLT_ALPHA		0x00D8
+#define GE_DES_PATH_EN		0x00DC
+#define GE_ROTATE_MODE		0x00E0
+#define GE_MIRROR_MODE		0x00E4
+#define GE_GE_DELAY		0x00E8
+#define GE_ENABLE		0x00EC
+#define GE_INT_EN		0x00F0
+#define GE_INT_FLAG		0x00F4
+#define GE_STATUS		0x00F8
+#define GE_SWID			0x00FC
+#define GE_LN_X_START		0x0100
+#define GE_LN_X_END		0x0104
+#define GE_LN_Y_START		0x0108
+#define GE_LN_Y_END		0x0110
+#define GE_LN_TCK		0x0114
+#define GE_AMX_CSC_BYPASS	0x0118
+#define GE_C1_COEF		0x011C
+#define GE_LN_STL_TB		0x0120
+#define GE_LN_STL_RTN		0x0124
+#define GE_LN_STL_DATA		0x0128
+#define GE_LN_STL_APA		0x012C
+#define GE_BC_P1X		0x0130
+#define GE_BC_P1Y		0x0134
+#define GE_BC_P2X		0x0138
+#define GE_BC_P2Y		0x013C
+#define GE_BC_P3X		0x0140
+#define GE_BC_P3Y		0x0144
+#define GE_BC_COLOR		0x0148
+#define GE_BC_ALPHA		0x014C
+#define GE_BC_DELTA_T		0x0150
+#define GE_BC_L_STL		0x0154
+#define GE_BC_L_STL_RTN		0x0158
+#define GE_C2_COEF		0x015C
+#define GE_C3_COEF		0x0160
+#define GE_C4_COEF		0x0164
+#define GE_C5_COEF		0x0168
+#define GE_C6_COEF		0x016C
+#define GE_C7_COEF		0x0170
+#define GE_C8_COEF		0x0174
+#define GE_YUV2_Y_BADDR		0x0178
+#define GE_YUV2_C_BADDR		0x017C
+#define GE_VQ_EN		0x0180
+#define GE_VQ_SIZE		0x0184
+#define GE_VQ_UDPTR		0x0188
+#define GE_VQ_BASEADDR		0x018C
+#define GE_VQ_WRSIZE		0x0190
+#define GE_VQ_STADDRW		0x0194
+#define GE_VQ_THR		0x0198
+#define GE_VQ_YUV2_Y_FBW	0x019C
+#define GE_ROP4_EN		0x01A0
+#define GE_ALPHA_PLANE_EN	0x01A4
+#define GE_MASK_BADDR		0x01A8
+#define GE_MASK_DISP_W		0x01AC
+#define GE_MASK_DISP_H		0x01B0
+#define GE_MASK_X_START		0x01B4
+#define GE_MASK_Y_START		0x01B8
+#define GE_MASK_WIDTH		0x01BC
+#define GE_MASK_HEIGHT		0x01C0
+#define GE_DW_MASK_BADDR	0x01C4
+#define GE_ALPHA_PLANE_WBE	0x01C8
+#define GE_YUV2_C_FBW		0x01CC
+#define GE_ADAP_BLEND_EN	0x01D0
+#define GE_SRC_ALPHA_SEL	0x01D4
+#define GE_SRC_BLEND_APA	0x01D8
+#define GE_DES_ALPHA_SEL	0x01DC
+#define GE_DES_BLEND_APA	0x01E0
+#define GE_ADAP_CLAMP_EN	0x01E4
+#define GE_YUV2_C_BLEND_SEL	0x01E8
+#define GE_SRC_INDEP_MODE	0x01EC
+#define GE_C9_COEF		0x01F0
+#define GE_COEF_I		0x01F4
+#define GE_COEF_J		0x01F8
+#define GE_COEF_K		0x01FC
+#define GE_G1_CD		0x0200
+#define GE_G2_CD		0x0204
+#define GE_G1_FG_ADDR		0x0210
+#define GE_G1_BG_ADDR		0x0214
+#define GE_G1_FB_SEL		0x0218
+#define GE_G2_FG_ADDR		0x021C
+#define GE_G2_BG_ADDR		0x0220
+#define GE_G2_FB_SEL		0x0224
+#define GE_G1_X_START		0x0230
+#define GE_G1_X_END		0x0234
+#define GE_G1_Y_START		0x0238
+#define GE_G1_Y_END		0x023C
+#define GE_G2_X_START		0x0240
+#define GE_G2_X_END		0x0244
+#define GE_G2_Y_START		0x0248
+#define GE_G2_Y_END		0x024C
+#define GE_DISP_X_END		0x0250
+#define GE_DISP_Y_END		0x0254
+#define GE_AMX_CB		0x0258
+#define GE_G1_YUV_MODE_EN	0x025C
+#define GE_G2_YUV_MODE_EN	0x0260
+#define GE_G1_YUV_FMT_SEL	0x0264
+#define GE_G1_YUV_OUTP_SEL	0x0268
+#define GE_G2_YUV_FMT_SEL	0x026C
+#define GE_G2_YUV_OUTP_SEL	0x0270
+#define GE_AMX_CSC_CFG		0x0274
+#define GE_AMX_CSC_MODE		0x0278
+#define GE_AMX_Y_SUB_16_EN	0x027C
+#define GE_G1_YUV_ADDR		0x0280
+#define GE_G2_YUV_ADDR		0x0284
+#define GE_G1_CK_EN		0x0298
+#define GE_G2_CK_EN		0x029C
+#define GE_G1_C_KEY		0x02A0
+#define GE_G2_C_KEY		0x02A4
+#define GE_G1_AMX_EN		0x02A8
+#define GE_G2_AMX_EN		0x02AC
+#define GE_CK2_APA		0x02B0
+#define GE_AMX_CTL		0x02B4
+#define GE_CK_APA		0x02B8
+#define GE_FIX_APA		0x02BC
+#define GE_G1_AMX_HM		0x02C0
+#define GE_G2_AMX_HM		0x02C4
+#define GE_NH_DATA		0x02C8
+#define GE_VSYNC_STS		0x02CC
+#define GE_REG_UPD		0x02D0
+#define GE_REG_SEL		0x02D4
+#define GE_REG_AMX2_CTL		0x02D8
+#define GE_FIX2_APA		0x02DC
+#define GE_G1_H_SCALE		0x02E0
+#define GE_G2_H_SCALE		0x02E4
+#define GE_G1_FBW		0x02E8
+#define GE_G1_VCROP		0x02EC
+#define GE_G1_HCROP		0x02F0
+#define GE_G2_FBW		0x02F4
+#define GE_G2_VCROP		0x02F8
+#define GE_G2_HCROP		0x02FC
 
 static void __iomem *regbase;
 
@@ -65,20 +225,20 @@ void wmt_ge_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
 		p->fbops->fb_sync(p);
 
 	writel(p->var.bits_per_pixel == 32 ? 3 :
-	      (p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_DEPTH_OFF);
-	writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF);
-	writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
-	writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
-	writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
-	writel(rect->dx, regbase + GE_DESTAREAX_OFF);
-	writel(rect->dy, regbase + GE_DESTAREAY_OFF);
-	writel(rect->width - 1, regbase + GE_DESTAREAW_OFF);
-	writel(rect->height - 1, regbase + GE_DESTAREAH_OFF);
-
-	writel(pat, regbase + GE_PAT0C_OFF);
-	writel(1, regbase + GE_COMMAND_OFF);
-	writel(rect->rop == ROP_XOR ? 0x5a : 0xf0, regbase + GE_ROPCODE_OFF);
-	writel(1, regbase + GE_FIRE_OFF);
+	      (p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_COLOR_DEPTH);
+	writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HM_SEL);
+	writel(p->fix.smem_start, regbase + GE_DES_BADDR);
+	writel(p->var.xres_virtual - 1, regbase + GE_DES_DISP_W);
+	writel(p->var.yres_virtual - 1, regbase + GE_DES_DISP_H);
+	writel(rect->dx, regbase + GE_DES_X_START);
+	writel(rect->dy, regbase + GE_DES_Y_START);
+	writel(rect->width - 1, regbase + GE_DES_WIDTH);
+	writel(rect->height - 1, regbase + GE_DES_HEIGHT);
+
+	writel(pat, regbase + GE_PAT0_COLOR);
+	writel(1, regbase + GE_COMMAND);
+	writel(rect->rop == ROP_XOR ? 0x5a : 0xf0, regbase + GE_ROP_CODE);
+	writel(1, regbase + GE_FIRE);
 }
 EXPORT_SYMBOL_GPL(wmt_ge_fillrect);
 
@@ -91,34 +251,34 @@ void wmt_ge_copyarea(struct fb_info *p, const struct fb_copyarea *area)
 		p->fbops->fb_sync(p);
 
 	writel(p->var.bits_per_pixel > 16 ? 3 :
-	      (p->var.bits_per_pixel > 8 ? 1 : 0), regbase + GE_DEPTH_OFF);
-
-	writel(p->fix.smem_start, regbase + GE_SRCBASE_OFF);
-	writel(p->var.xres_virtual - 1, regbase + GE_SRCDISPW_OFF);
-	writel(p->var.yres_virtual - 1, regbase + GE_SRCDISPH_OFF);
-	writel(area->sx, regbase + GE_SRCAREAX_OFF);
-	writel(area->sy, regbase + GE_SRCAREAY_OFF);
-	writel(area->width - 1, regbase + GE_SRCAREAW_OFF);
-	writel(area->height - 1, regbase + GE_SRCAREAH_OFF);
-
-	writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
-	writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
-	writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
-	writel(area->dx, regbase + GE_DESTAREAX_OFF);
-	writel(area->dy, regbase + GE_DESTAREAY_OFF);
-	writel(area->width - 1, regbase + GE_DESTAREAW_OFF);
-	writel(area->height - 1, regbase + GE_DESTAREAH_OFF);
-
-	writel(0xcc, regbase + GE_ROPCODE_OFF);
-	writel(1, regbase + GE_COMMAND_OFF);
-	writel(1, regbase + GE_FIRE_OFF);
+	      (p->var.bits_per_pixel > 8 ? 1 : 0), regbase + GE_COLOR_DEPTH);
+
+	writel(p->fix.smem_start, regbase + GE_SRC_BADDR);
+	writel(p->var.xres_virtual - 1, regbase + GE_SRC_DISP_W);
+	writel(p->var.yres_virtual - 1, regbase + GE_SRC_DISP_H);
+	writel(area->sx, regbase + GE_SRC_X_START);
+	writel(area->sy, regbase + GE_SRC_Y_START);
+	writel(area->width - 1, regbase + GE_SRC_WIDTH);
+	writel(area->height - 1, regbase + GE_SRC_HEIGHT);
+
+	writel(p->fix.smem_start, regbase + GE_DES_BADDR);
+	writel(p->var.xres_virtual - 1, regbase + GE_DES_DISP_W);
+	writel(p->var.yres_virtual - 1, regbase + GE_DES_DISP_H);
+	writel(area->dx, regbase + GE_DES_X_START);
+	writel(area->dy, regbase + GE_DES_Y_START);
+	writel(area->width - 1, regbase + GE_DES_WIDTH);
+	writel(area->height - 1, regbase + GE_DES_HEIGHT);
+
+	writel(0xcc, regbase + GE_ROP_CODE);
+	writel(1, regbase + GE_COMMAND);
+	writel(1, regbase + GE_FIRE);
 }
 EXPORT_SYMBOL_GPL(wmt_ge_copyarea);
 
 int wmt_ge_sync(struct fb_info *p)
 {
 	int loops = 5000000;
-	while ((readl(regbase + GE_STATUS_OFF) & 4) && --loops)
+	while ((readl(regbase + GE_STATUS) & 4) && --loops)
 		cpu_relax();
 	return loops > 0 ? 0 : -EBUSY;
 }
@@ -146,7 +306,7 @@ static int wmt_ge_rops_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	writel(1, regbase + GE_ENABLE_OFF);
+	writel(1, regbase + GE_ENABLE);
 	printk(KERN_INFO "Enabled support for WMT GE raster acceleration\n");
 
 	return 0;
-- 
1.7.9.5



From gnurou at gmail.com  Sat May 18 05:17:46 2013
From: gnurou at gmail.com (Alexandre Courbot)
Date: Sat, 18 May 2013 18:17:46 +0900
Subject: [PATCH] ARM: tegra: enable host1x support by default
Message-ID: <1368868666-24754-1-git-send-email-acourbot@nvidia.com>

Tegra DRM support used to be enabled in the default Tegra configuration,
but it now depends on CONFIG_TEGRA_HOST1X which is disabled by default.
Enable CONFIG_TEGRA_HOST1X so that DRM support is compiled in again.

Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
 arch/arm/configs/tegra_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index a5f0485..dbf83db 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -153,6 +153,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_DRM=y
+CONFIG_TEGRA_HOST1X=y
 CONFIG_DRM_TEGRA=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
-- 
1.8.2.3



From gnurou at gmail.com  Sat May 18 06:29:53 2013
From: gnurou at gmail.com (Alexandre Courbot)
Date: Sat, 18 May 2013 19:29:53 +0900
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <CAAVeFuJ5q4Y0QtvJX2iVmq_O2ofs1B9=MB_aA8VdcEBdM4zf2Q@mail.gmail.com>

On Thu, Apr 4, 2013 at 11:39 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> +struct simplefb_format {
> +       const char *name;
> +       u32 bits_per_pixel;
> +       struct fb_bitfield red;
> +       struct fb_bitfield green;
> +       struct fb_bitfield blue;
> +       struct fb_bitfield transp;
> +};
> +
> +struct simplefb_format simplefb_formats[] = {
> +       { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0} },
> +};

I have been adding a few extra formats to this list, and I wonder if
this could not simply be turned into a function that would directly
convert the name string into the corresponding right format. The
mapping between name and format seems to be a 1:1 and this would
probably avoid errors in the future. I'm especially thinking about
color order here - I started adding a mode that reads

    { "r8g8b8a8", 32, {0, 8}, {8, 8}, {16, 8}, {24, 8} },

while it should probably be called "a8b8g8r8" as the order of colors
is not the same as your r5g6b5.

I can submit a patch if there is no issue with that idea.

Alex.


From 21cnbao at gmail.com  Sat May 18 07:03:24 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Sat, 18 May 2013 19:03:24 +0800
Subject: [alsa-devel] [PATCH v2] ASoC: dfbmcs320: make the driver common
 for other BT modules
In-Reply-To: <20130517111523.GM1627@sirena.org.uk>
References: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>
 <20130517111523.GM1627@sirena.org.uk>
Message-ID: <CAGsJ_4zjgLhNOiwGcTjvC6dP2XPqnmjzWF12pVPomU-ERH6YYg@mail.gmail.com>

2013/5/17 Mark Brown <broonie at kernel.org>:
> On Fri, May 17, 2013 at 10:19:37AM +0800, Barry Song wrote:
>> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
>> we don't want everyone to have a seperate codec driver. anyway, the
>> feature of Bluetooth handsfree is same on all platforms, so this patch
>> makes the DFBM-CS320 driver become a common BT handsfree driver.
>
> Sorry, should have thought of this before but why are we calling this
> "handsfree"?  It's just a generic bluetooth link as far as the host
> system is concerned, "bt-sco" might be more appropriate?

agree. BT SCO should be more suitable.

>
> Otherwise this looks OK for ASoC though I'd expect to see a change to
> registration of the OpenMoko BT device (perhaps I missed it though).

sorry. i don't understand. i would think OpenMOKO can also use this driver?

-barry


From 21cnbao at gmail.com  Sat May 18 07:22:29 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Sat, 18 May 2013 19:22:29 +0800
Subject: [PATCH v3] ASoC: dfbmcs320: make the driver common for other BT
 modules
Message-ID: <1368876149-22211-1-git-send-email-Baohua.Song@csr.com>

DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
we don't want everyone to have a seperate codec driver. anyway, the
feature of Bluetooth SCO is same on all platforms, so this patch
makes the DFBM-CS320 driver become a common BT SCO link driver.

Cc: Graeme Gregory <graeme at openmoko.org>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v3: rename to sco according to Mark's comment

 sound/soc/codecs/Kconfig                   |  4 ++--
 sound/soc/codecs/Makefile                  |  4 ++--
 sound/soc/codecs/{dfbmcs320.c => bt-sco.c} | 37 +++++++++++++++++++-----------
 sound/soc/samsung/neo1973_wm8753.c         |  2 +-
 4 files changed, 28 insertions(+), 19 deletions(-)
 rename sound/soc/codecs/{dfbmcs320.c => bt-sco.c} (53%)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index d8c4f3d..386292d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -40,7 +40,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_DA7213 if I2C
 	select SND_SOC_DA732X if I2C
 	select SND_SOC_DA9055 if I2C
-	select SND_SOC_DFBMCS320
+	select SND_SOC_BT_SCO
 	select SND_SOC_ISABELLE if I2C
 	select SND_SOC_JZ4740_CODEC
 	select SND_SOC_LM4857 if I2C
@@ -263,7 +263,7 @@ config SND_SOC_DA732X
 config SND_SOC_DA9055
 	tristate
 
-config SND_SOC_DFBMCS320
+config SND_SOC_BT_SCO
 	tristate
 
 config SND_SOC_DMIC
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 49ff127..82aa34e 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -27,7 +27,7 @@ snd-soc-da7210-objs := da7210.o
 snd-soc-da7213-objs := da7213.o
 snd-soc-da732x-objs := da732x.o
 snd-soc-da9055-objs := da9055.o
-snd-soc-dfbmcs320-objs := dfbmcs320.o
+snd-soc-bt-sco-objs := bt-sco.o
 snd-soc-dmic-objs := dmic.o
 snd-soc-isabelle-objs := isabelle.o
 snd-soc-jz4740-codec-objs := jz4740.o
@@ -154,7 +154,7 @@ obj-$(CONFIG_SND_SOC_DA7210)	+= snd-soc-da7210.o
 obj-$(CONFIG_SND_SOC_DA7213)	+= snd-soc-da7213.o
 obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
 obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
-obj-$(CONFIG_SND_SOC_DFBMCS320)	+= snd-soc-dfbmcs320.o
+obj-$(CONFIG_SND_SOC_BT_SCO)	+= snd-soc-bt-sco.o
 obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
 obj-$(CONFIG_SND_SOC_ISABELLE)	+= snd-soc-isabelle.o
 obj-$(CONFIG_SND_SOC_JZ4740_CODEC)	+= snd-soc-jz4740-codec.o
diff --git a/sound/soc/codecs/dfbmcs320.c b/sound/soc/codecs/bt-sco.c
similarity index 53%
rename from sound/soc/codecs/dfbmcs320.c
rename to sound/soc/codecs/bt-sco.c
index 4f4f7f4..a081d9f 100644
--- a/sound/soc/codecs/dfbmcs320.c
+++ b/sound/soc/codecs/bt-sco.c
@@ -1,5 +1,5 @@
 /*
- * Driver for the DFBM-CS320 bluetooth module
+ * Driver for generic Bluetooth SCO link
  * Copyright 2011 Lars-Peter Clausen <lars at metafoo.de>
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -15,8 +15,8 @@
 
 #include <sound/soc.h>
 
-static struct snd_soc_dai_driver dfbmcs320_dai = {
-	.name = "dfbmcs320-pcm",
+static struct snd_soc_dai_driver bt_sco_dai = {
+	.name = "bt-sco-pcm",
 	.playback = {
 		.channels_min = 1,
 		.channels_max = 1,
@@ -31,32 +31,41 @@ static struct snd_soc_dai_driver dfbmcs320_dai = {
 	},
 };
 
-static struct snd_soc_codec_driver soc_codec_dev_dfbmcs320;
+static struct snd_soc_codec_driver soc_codec_dev_bt_sco;
 
-static int dfbmcs320_probe(struct platform_device *pdev)
+static int bt_sco_probe(struct platform_device *pdev)
 {
-	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_dfbmcs320,
-			&dfbmcs320_dai, 1);
+	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_bt_sco,
+			&bt_sco_dai, 1);
 }
 
-static int dfbmcs320_remove(struct platform_device *pdev)
+static int bt_sco_remove(struct platform_device *pdev)
 {
 	snd_soc_unregister_codec(&pdev->dev);
 
 	return 0;
 }
 
-static struct platform_driver dfmcs320_driver = {
+static struct platform_device_id bt_sco_driver_ids[] = {
+	{
+		.name		= "dfbmcs320",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(platform, bt_sco_driver_ids);
+
+static struct platform_driver bt_sco_driver = {
 	.driver = {
-		.name = "dfbmcs320",
+		.name = "bt-sco",
 		.owner = THIS_MODULE,
 	},
-	.probe = dfbmcs320_probe,
-	.remove = dfbmcs320_remove,
+	.probe = bt_sco_probe,
+	.remove = bt_sco_remove,
+	.id_table = bt_sco_driver_ids,
 };
 
-module_platform_driver(dfmcs320_driver);
+module_platform_driver(bt_sco_driver);
 
 MODULE_AUTHOR("Lars-Peter Clausen <lars at metafoo.de>");
-MODULE_DESCRIPTION("ASoC DFBM-CS320 bluethooth module driver");
+MODULE_DESCRIPTION("ASoC generic bluethooth sco link driver");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/neo1973_wm8753.c b/sound/soc/samsung/neo1973_wm8753.c
index e591c38..807db41 100644
--- a/sound/soc/samsung/neo1973_wm8753.c
+++ b/sound/soc/samsung/neo1973_wm8753.c
@@ -373,7 +373,7 @@ static struct snd_soc_dai_link neo1973_dai[] = {
 { /* Voice via BT */
 	.name = "Bluetooth",
 	.stream_name = "Voice",
-	.cpu_dai_name = "dfbmcs320-pcm",
+	.cpu_dai_name = "bt-sco-pcm",
 	.codec_dai_name = "wm8753-voice",
 	.codec_name = "wm8753.0-001a",
 	.ops = &neo1973_voice_ops,
-- 
1.8.2.3



From broonie at kernel.org  Sat May 18 07:25:05 2013
From: broonie at kernel.org (Mark Brown)
Date: Sat, 18 May 2013 12:25:05 +0100
Subject: [alsa-devel] [PATCH v2] ASoC: dfbmcs320: make the driver common
 for other BT modules
In-Reply-To: <CAGsJ_4zjgLhNOiwGcTjvC6dP2XPqnmjzWF12pVPomU-ERH6YYg@mail.gmail.com>
References: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>
 <20130517111523.GM1627@sirena.org.uk>
 <CAGsJ_4zjgLhNOiwGcTjvC6dP2XPqnmjzWF12pVPomU-ERH6YYg@mail.gmail.com>
Message-ID: <20130518112505.GS1627@sirena.org.uk>

On Sat, May 18, 2013 at 07:03:24PM +0800, Barry Song wrote:
> 2013/5/17 Mark Brown <broonie at kernel.org>:

> > Otherwise this looks OK for ASoC though I'd expect to see a change to
> > registration of the OpenMoko BT device (perhaps I missed it though).

> sorry. i don't understand. i would think OpenMOKO can also use this driver?

If you change the names the driver uses to bind you need to also update
the users so that they use the new name.
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From lars at metafoo.de  Sat May 18 07:32:39 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Sat, 18 May 2013 13:32:39 +0200
Subject: [alsa-devel] [PATCH v2] ASoC: dfbmcs320: make the driver common
 for other BT modules
In-Reply-To: <20130518112505.GS1627@sirena.org.uk>
References: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>
 <20130517111523.GM1627@sirena.org.uk>
 <CAGsJ_4zjgLhNOiwGcTjvC6dP2XPqnmjzWF12pVPomU-ERH6YYg@mail.gmail.com>
 <20130518112505.GS1627@sirena.org.uk>
Message-ID: <519766D7.9080802@metafoo.de>

On 05/18/2013 01:25 PM, Mark Brown wrote:
> On Sat, May 18, 2013 at 07:03:24PM +0800, Barry Song wrote:
>> 2013/5/17 Mark Brown <broonie at kernel.org>:
> 
>>> Otherwise this looks OK for ASoC though I'd expect to see a change to
>>> registration of the OpenMoko BT device (perhaps I missed it though).
> 
>> sorry. i don't understand. i would think OpenMOKO can also use this driver?
> 
> If you change the names the driver uses to bind you need to also update
> the users so that they use the new name.
> 

Since there's the platform_device_id table now this should not be necessary.


From 21cnbao at gmail.com  Sat May 18 07:34:25 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Sat, 18 May 2013 19:34:25 +0800
Subject: [alsa-devel] [PATCH v2] ASoC: dfbmcs320: make the driver common
 for other BT modules
In-Reply-To: <519766D7.9080802@metafoo.de>
References: <1368757177-15372-1-git-send-email-Baohua.Song@csr.com>
 <20130517111523.GM1627@sirena.org.uk>
 <CAGsJ_4zjgLhNOiwGcTjvC6dP2XPqnmjzWF12pVPomU-ERH6YYg@mail.gmail.com>
 <20130518112505.GS1627@sirena.org.uk> <519766D7.9080802@metafoo.de>
Message-ID: <CAGsJ_4xY+z8FB_ibKkRq1Na3SpQuFpxEDUfh2wUoHjdp0LEbhg@mail.gmail.com>

2013/5/18 Lars-Peter Clausen <lars at metafoo.de>:
> On 05/18/2013 01:25 PM, Mark Brown wrote:
>> On Sat, May 18, 2013 at 07:03:24PM +0800, Barry Song wrote:
>>> 2013/5/17 Mark Brown <broonie at kernel.org>:
>>
>>>> Otherwise this looks OK for ASoC though I'd expect to see a change to
>>>> registration of the OpenMoko BT device (perhaps I missed it though).
>>
>>> sorry. i don't understand. i would think OpenMOKO can also use this driver?
>>
>> If you change the names the driver uses to bind you need to also update
>> the users so that they use the new name.
>>
>
> Since there's the platform_device_id table now this should not be necessary.

i guess Mark meaned i missed to change "select SND_SOC_DFBMCS320"?

config SND_SOC_SAMSUNG_NEO1973_WM8753
        tristate "Audio support for Openmoko Neo1973 Smartphones (GTA02)"
        depends on SND_SOC_SAMSUNG && MACH_NEO1973_GTA02
        select SND_S3C24XX_I2S
        select SND_SOC_WM8753
        select SND_SOC_DFBMCS320
        help
          Say Y here to enable audio support for the Openmoko Neo1973
          Smartphones.

-barry


From 21cnbao at gmail.com  Sat May 18 07:46:06 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Sat, 18 May 2013 19:46:06 +0800
Subject: [PATCH RESEND] spi: sirf: fix the issue while transferring more than
 256 words
Message-ID: <1368877566-27812-1-git-send-email-Baohua.Song@csr.com>

From: Qipan Li <Qipan.Li at csr.com>

currently, spi irq handler only does rx processing and fetching data from rx
fifo when "FRM_END" irq happens. FRM_END indicates one transfer completes. if
rx size is less than 256, it works well.
but the problem is that spi rx fifo size is only 256 bytes, then if data size
of one frame is more than 256, before FRM_END comes, rx fifo will be filled with
RXFIFO_OFLOW overflow interrupt, it will make us lose some data due to fifo
overflow.
Explicitly we need do fetch work from device rx fifo in irq handler not only in
"FRM_END" irq but also in "THD_REACH" irq. THD_REACH means rx fifo has come to
its threshold and will come to overflow if we don't take data from it in time.

In this patch, we fix this issue. we take data from rx fifo when either FRM_END
or RX_THD_REACH irq comes, we put data into tx fifo when either TX_FIFO_EMPTY
or TX_THD_REACH irq comes.

Signed-off-by: Qipan Li <Qipan.Li at csr.com>
Signed-off-by: Zhiwu Song <Zhiwu.Song at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/spi/spi-sirf.c | 43 +++++++++++++------------------------------
 1 file changed, 13 insertions(+), 30 deletions(-)

diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index 0808cd5..ac98cec 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -142,9 +142,6 @@ struct sirfsoc_spi {
 	unsigned int left_tx_cnt;
 	unsigned int left_rx_cnt;
 
-	/* tasklet to push tx msg into FIFO */
-	struct tasklet_struct tasklet_tx;
-
 	int chipselect[0];
 };
 
@@ -236,17 +233,6 @@ static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 	sspi->left_tx_cnt--;
 }
 
-static void spi_sirfsoc_tasklet_tx(unsigned long arg)
-{
-	struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
-
-	/* Fill Tx FIFO while there are left words to be transmitted */
-	while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
-			SIRFSOC_SPI_FIFO_FULL)) &&
-			sspi->left_tx_cnt)
-		sspi->tx_word(sspi);
-}
-
 static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 {
 	struct sirfsoc_spi *sspi = dev_id;
@@ -261,25 +247,25 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 		writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 	}
 
-	if (spi_stat & SIRFSOC_SPI_FRM_END) {
+	if (spi_stat & (SIRFSOC_SPI_FRM_END
+			| SIRFSOC_SPI_RXFIFO_THD_REACH))
 		while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 				& SIRFSOC_SPI_FIFO_EMPTY)) &&
 				sspi->left_rx_cnt)
 			sspi->rx_word(sspi);
 
-		/* Received all words */
-		if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
-			complete(&sspi->done);
-			writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
-		}
-	}
-
-	if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH ||
-		spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH ||
-		spi_stat & SIRFSOC_SPI_RX_FIFO_FULL ||
-		spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
-		tasklet_schedule(&sspi->tasklet_tx);
+	if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
+			| SIRFSOC_SPI_TXFIFO_THD_REACH))
+		while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
+				& SIRFSOC_SPI_FIFO_FULL)) &&
+				sspi->left_tx_cnt)
+			sspi->tx_word(sspi);
 
+	/* Received all words */
+	if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
+		complete(&sspi->done);
+		writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
+	}
 	return IRQ_HANDLED;
 }
 
@@ -573,9 +559,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
 
 	init_completion(&sspi->done);
 
-	tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
-		     (unsigned long)sspi);
-
 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
-- 
1.8.2.3



From robert.jarzmik at free.fr  Sat May 18 05:18:40 2013
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Sat, 18 May 2013 11:18:40 +0200
Subject: GPIO sysfs : set a wake source
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
 <51926177.1050600@wwwdotorg.org> <87ip2ig1ez.fsf@free.fr>
 <CACRpkdbiZFutP_+u=ciuC6r-8N5FpkEnGVLH9LGDQ7pvdo3_-Q@mail.gmail.com>
Message-ID: <87k3mwv6ru.fsf@free.fr>

Linus Walleij <linus.walleij at linaro.org> writes:

> On Thu, May 16, 2013 at 9:39 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
>
>>>> Don't go down this path, let the kernel handle this kind of stuff.
>
>> Oh really, where ?
>>
>> Let me show you why it can't be a module.
>
> I'm not following. I haven't been talking about modules ...
> (I think?)
> Do you mean you want to show why it can't be in the kernel?
My bad. Bad wording, I should have said "why it shouldn't be in kernel".

>
>> In my case, I have a 2G modem connected to the soc :
>>  - the modem and 1 SoC UART are connected (TX, RX, CTS, ...)
>>  - the modem and SoC are connected through several gpios
>>    - one or two control to power up and reset the modem
>>    - one connected to the modem "ring" signal (the one I want a wakeup for).
>>
>> So I have no module to handle my modem :
>>  - UART is handled by pxa-uart
>>  - control/reset by gpiolib
>
> Do you mean control/reset is handled by the userspace sysfs
> interface to GPIOlib? This is not necessarily a good idea
> in that case.
Exactly, all controlled through userspace sysfs.

Well, it's the agreed method for far, see [1].
Search [1] for the string "These are really lengthy and time consuming sequences".

>> Devicetree can't help in the toggle to "activate" or "deactivate" the wakeup
>> upon this GPIO, can it ?
>
> No, I'm just saying the connection between the device and the
> GPIO tree shall be modeled in the device tree, especially since
> this is obviously deeply embedded, soldered-on stuff and the
> hardware set-up should be encoded in the device tree.
OK, expressed in DT, why not.

> I am starting so suspect that the real issue here, which has
> not been expressed so far, is that you think of this embedded
> modem as a US Robotics 28K8 modem connected to a serial
> port, and as something that should be handled by userspace.
Yes, that's what I and others think for modem startup control ([1]) but not for
modem data path.

> Is there a silent assumption that "modem drivers must be in
> userspace"?
No, certainly not. The assumption is one though that this particular modem,
which is that old and simple, doesn't require a driver other than the uart SoC
driver.

> This assumption is not necessarily true when the modem start
> to connect wires like GPIO to work. There are modems using
> other things than UART, such as HSI, for datapath. And modems
> using in-kernel protocols like CAIF or Phonet for control.
These are far more modern modems than the one I'm talking of.
Mine is a Sagem X200 (I think, from board disassembly).

> I think you need to think about how we join this modem closer
> with the kernel instead of trying to paper it over using userspace
> GPIO.
Why ? I has only one UART and several GPIOs. What good would it be to add it in
kernel ?

>> I don't yet know. Let me think this more over. I'd like some literature if you
>> can provide (especially on LAKML).
> It doesn't toggle any pins so it's not what you want anyway.
> I think you want part of your driver in the kernel.
Which driver ? The Sagem X200 ?

> I think the dilemma faced by embedded modems need to
> be considered thoroughly here.
As I said, it's an "old" modem. And if by embedded you mean "embedded in the
SoC", it's not, it's a separate chip. The interconnect are the UART lines and
the GPIO lines (solder lines as you pointed out).


Cheers.

-- 
Robert

[1] http://archive.arm.linux.org.uk/lurker/message/20080612.101303.80e8bb8b.fr.html


From a.spyridakis at virtualopensystems.com  Sat May 18 08:22:07 2013
From: a.spyridakis at virtualopensystems.com (Alexander Spyridakis)
Date: Sat, 18 May 2013 15:22:07 +0300
Subject: Problems while booting a linux system on fast models based
 CortexA15
In-Reply-To: <CAJ30i6F542sn_+_6ha-nf-kgS7u=OMBTE6DY1tmZPihLbEptxQ@mail.gmail.com>
References: <CAJ30i6HzvaKrKha7aVcR50=-5zmgivY-82J6NTqFw7Fh+sNzfQ@mail.gmail.com>
 <CAEDV+gLekd9PrX=YqFpKQyLxFHDuAV8F5NvaMkRKZQvR3q_yNg@mail.gmail.com>
 <CAJ30i6G95VHv5FoP5DXXBNgp+qxbJ-2ZyvXy8eNa_pM7xx6r-Q@mail.gmail.com>
 <CAJRNFKKwaE-JCvj52B5oba+hvYeTn3W5Qo5TOPGSSy=WfFE-fA@mail.gmail.com>
 <CAJ30i6F542sn_+_6ha-nf-kgS7u=OMBTE6DY1tmZPihLbEptxQ@mail.gmail.com>
Message-ID: <CAJRNFKJNArk+1qa9HyjmLFVqX=WP2_TpZOyAr_Qpeux9Cc7ukg@mail.gmail.com>

On 18 May 2013 03:26, Mai Daftedar <mai.daftedar at gmail.com> wrote:
>
> I still have no luck in bringing up the host on fast models.
> There is something I'm definitely missing out :
>
> Theses are my suggested potential errors:
> When I execute the following command as mentioned in the pdf
> mkfs.ext3 ./disk.img
>
> The following occurs..Is this okay?

Ah yes sorry for that, try and apply this temporary fix to boot from the MMC:
https://github.com/virtualopensystems/linux-kvm-arm/commit/17a9b9221998802d1ee2b245818cdd253ccbdab6

In the longterm though I suggest to fix your networking problem, it is
much easier to test things out with NFS.

Regards.


From 21cnbao at gmail.com  Sat May 18 08:25:00 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Sat, 18 May 2013 20:25:00 +0800
Subject: [PATCH v4] ASoC: dfbmcs320: make the driver common for other BT
 modules
Message-ID: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>

DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
we don't want everyone to have a seperate codec driver. anyway, the
feature of Bluetooth SCO is same on all platforms, so this patch
makes the DFBM-CS320 driver become a common BT SCO link driver.

Cc: Graeme Gregory <graeme at openmoko.org>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 v4:
 change "select SND_SOC_DFBMCS320" to "select SND_SOC_BT_SCO" for OpenMOKO user
 as v3 missed this

 sound/soc/codecs/Kconfig                   |  4 ++--
 sound/soc/codecs/Makefile                  |  4 ++--
 sound/soc/codecs/{dfbmcs320.c => bt-sco.c} | 37 +++++++++++++++++++-----------
 sound/soc/samsung/Kconfig                  |  2 +-
 sound/soc/samsung/neo1973_wm8753.c         |  2 +-
 5 files changed, 29 insertions(+), 20 deletions(-)
 rename sound/soc/codecs/{dfbmcs320.c => bt-sco.c} (53%)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index d8c4f3d..386292d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -40,7 +40,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_DA7213 if I2C
 	select SND_SOC_DA732X if I2C
 	select SND_SOC_DA9055 if I2C
-	select SND_SOC_DFBMCS320
+	select SND_SOC_BT_SCO
 	select SND_SOC_ISABELLE if I2C
 	select SND_SOC_JZ4740_CODEC
 	select SND_SOC_LM4857 if I2C
@@ -263,7 +263,7 @@ config SND_SOC_DA732X
 config SND_SOC_DA9055
 	tristate
 
-config SND_SOC_DFBMCS320
+config SND_SOC_BT_SCO
 	tristate
 
 config SND_SOC_DMIC
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 49ff127..82aa34e 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -27,7 +27,7 @@ snd-soc-da7210-objs := da7210.o
 snd-soc-da7213-objs := da7213.o
 snd-soc-da732x-objs := da732x.o
 snd-soc-da9055-objs := da9055.o
-snd-soc-dfbmcs320-objs := dfbmcs320.o
+snd-soc-bt-sco-objs := bt-sco.o
 snd-soc-dmic-objs := dmic.o
 snd-soc-isabelle-objs := isabelle.o
 snd-soc-jz4740-codec-objs := jz4740.o
@@ -154,7 +154,7 @@ obj-$(CONFIG_SND_SOC_DA7210)	+= snd-soc-da7210.o
 obj-$(CONFIG_SND_SOC_DA7213)	+= snd-soc-da7213.o
 obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
 obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
-obj-$(CONFIG_SND_SOC_DFBMCS320)	+= snd-soc-dfbmcs320.o
+obj-$(CONFIG_SND_SOC_BT_SCO)	+= snd-soc-bt-sco.o
 obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
 obj-$(CONFIG_SND_SOC_ISABELLE)	+= snd-soc-isabelle.o
 obj-$(CONFIG_SND_SOC_JZ4740_CODEC)	+= snd-soc-jz4740-codec.o
diff --git a/sound/soc/codecs/dfbmcs320.c b/sound/soc/codecs/bt-sco.c
similarity index 53%
rename from sound/soc/codecs/dfbmcs320.c
rename to sound/soc/codecs/bt-sco.c
index 4f4f7f4..a081d9f 100644
--- a/sound/soc/codecs/dfbmcs320.c
+++ b/sound/soc/codecs/bt-sco.c
@@ -1,5 +1,5 @@
 /*
- * Driver for the DFBM-CS320 bluetooth module
+ * Driver for generic Bluetooth SCO link
  * Copyright 2011 Lars-Peter Clausen <lars at metafoo.de>
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -15,8 +15,8 @@
 
 #include <sound/soc.h>
 
-static struct snd_soc_dai_driver dfbmcs320_dai = {
-	.name = "dfbmcs320-pcm",
+static struct snd_soc_dai_driver bt_sco_dai = {
+	.name = "bt-sco-pcm",
 	.playback = {
 		.channels_min = 1,
 		.channels_max = 1,
@@ -31,32 +31,41 @@ static struct snd_soc_dai_driver dfbmcs320_dai = {
 	},
 };
 
-static struct snd_soc_codec_driver soc_codec_dev_dfbmcs320;
+static struct snd_soc_codec_driver soc_codec_dev_bt_sco;
 
-static int dfbmcs320_probe(struct platform_device *pdev)
+static int bt_sco_probe(struct platform_device *pdev)
 {
-	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_dfbmcs320,
-			&dfbmcs320_dai, 1);
+	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_bt_sco,
+			&bt_sco_dai, 1);
 }
 
-static int dfbmcs320_remove(struct platform_device *pdev)
+static int bt_sco_remove(struct platform_device *pdev)
 {
 	snd_soc_unregister_codec(&pdev->dev);
 
 	return 0;
 }
 
-static struct platform_driver dfmcs320_driver = {
+static struct platform_device_id bt_sco_driver_ids[] = {
+	{
+		.name		= "dfbmcs320",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(platform, bt_sco_driver_ids);
+
+static struct platform_driver bt_sco_driver = {
 	.driver = {
-		.name = "dfbmcs320",
+		.name = "bt-sco",
 		.owner = THIS_MODULE,
 	},
-	.probe = dfbmcs320_probe,
-	.remove = dfbmcs320_remove,
+	.probe = bt_sco_probe,
+	.remove = bt_sco_remove,
+	.id_table = bt_sco_driver_ids,
 };
 
-module_platform_driver(dfmcs320_driver);
+module_platform_driver(bt_sco_driver);
 
 MODULE_AUTHOR("Lars-Peter Clausen <lars at metafoo.de>");
-MODULE_DESCRIPTION("ASoC DFBM-CS320 bluethooth module driver");
+MODULE_DESCRIPTION("ASoC generic bluethooth sco link driver");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 475fb0d..ae0ea87 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -39,7 +39,7 @@ config SND_SOC_SAMSUNG_NEO1973_WM8753
 	depends on SND_SOC_SAMSUNG && MACH_NEO1973_GTA02
 	select SND_S3C24XX_I2S
 	select SND_SOC_WM8753
-	select SND_SOC_DFBMCS320
+	select SND_SOC_SCO
 	help
 	  Say Y here to enable audio support for the Openmoko Neo1973
 	  Smartphones.
diff --git a/sound/soc/samsung/neo1973_wm8753.c b/sound/soc/samsung/neo1973_wm8753.c
index e591c38..807db41 100644
--- a/sound/soc/samsung/neo1973_wm8753.c
+++ b/sound/soc/samsung/neo1973_wm8753.c
@@ -373,7 +373,7 @@ static struct snd_soc_dai_link neo1973_dai[] = {
 { /* Voice via BT */
 	.name = "Bluetooth",
 	.stream_name = "Voice",
-	.cpu_dai_name = "dfbmcs320-pcm",
+	.cpu_dai_name = "bt-sco-pcm",
 	.codec_dai_name = "wm8753-voice",
 	.codec_name = "wm8753.0-001a",
 	.ops = &neo1973_voice_ops,
-- 
1.8.2.3



From alchark at gmail.com  Sat May 18 09:28:54 2013
From: alchark at gmail.com (Alexey Charkov)
Date: Sat, 18 May 2013 17:28:54 +0400
Subject: [PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.
In-Reply-To: <1368868514-18975-5-git-send-email-linux@prisktech.co.nz>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
 <1368868514-18975-5-git-send-email-linux@prisktech.co.nz>
Message-ID: <CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com>

2013/5/18 Tony Prisk <linux at prisktech.co.nz>:
> The APC8750 does not support an LCD panel, but provides a VGA connector.
> This patch adds support for the VGA interface, and defines an optional
> devicetree property to specify the output interface. The default if not
> specified is LCD for backward compatibility.
>
> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
> ---
>  .../devicetree/bindings/video/wm,wm8505-fb.txt     |    5 ++++
>  drivers/video/wm8505fb.c                           |   31 ++++++++++++++++++--
>  2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
> index 601416c..9f1d648 100644
> --- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
> +++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
> @@ -7,6 +7,10 @@ Required properties:
>  - bits-per-pixel : bit depth of framebuffer (16 or 32)
>  - clocks : phandle to DVO clock
>
> +Optional properties:
> +- output-interface : the interface the fb should output on. Valid values are
> +       "lcd" or "vga". If not specified, the default is "lcd".
> +
>  Required subnodes:
>  - display-timings: see display-timing.txt for information
>
> @@ -17,6 +21,7 @@ Example:
>                 reg = <0xd8051700 0x200>;
>                 bits-per-pixel = <16>;
>                 clocks = <&clkdvo>;
> +               output-interface = "vga";
>
>                 display-timings {
>                         native-mode = <&timing0>;
> diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
> index f8bffc2..d1f7f33 100644
> --- a/drivers/video/wm8505fb.c
> +++ b/drivers/video/wm8505fb.c
> @@ -130,12 +130,17 @@
>
>  #define to_wm8505fb_info(__info) container_of(__info, \
>                                                 struct wm8505fb_info, fb)
> +
> +#define INTERFACE_LCD  1
> +#define INTERFACE_VGA  2
> +
>  struct wm8505fb_info {
>         struct fb_info fb;
>         void __iomem *regbase;
>         unsigned int contrast;
>         struct device *dev;
>         struct clk *clk_dvo;
> +       int interface;
>  };
>
>
> @@ -158,7 +163,11 @@ static int wm8505fb_init_hw(struct fb_info *info)
>          * 0x31C sets the correct color mode (RGB565) for WM8650
>          * Bit 8+9 (0x300) are ignored on WM8505 as reserved
>          */
> -       writel(0x31c,                  fbi->regbase + REG_GOVRH_YUVRGB);
> +       if (fbi->interface == INTERFACE_VGA)
> +               writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB);
> +       else
> +               writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);
> +
>         writel(1,                      fbi->regbase + REG_GOVRH_DVO_PIX);

Tony,

Would it be possible to also define known bit offsets for those
registers, while you are at this? It would probably reduce the black
magic quite a bit :)

>         /* Virtual buffer size */
> @@ -167,7 +176,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
>
>         /* black magic ;) */
>         writel(0xf,                    fbi->regbase + REG_GOVRH_FHI);
> -       writel(4,                      fbi->regbase + REG_GOVRH_DVO_SET);
> +
> +       if (fbi->interface == INTERFACE_VGA)
> +               writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET);
> +       else
> +               writel(4, fbi->regbase + REG_GOVRH_DVO_SET);

I don't remember if HDMI is yet another option for this register or
not... If it is, it would probably warrant defining fbi->interface as
an enum and changing this if-else into a switch statement to let the
compiler add its checks/warnings.

>         writel(1,                      fbi->regbase + REG_GOVRH_MIF);
>         writel(1,                      fbi->regbase + REG_GOVRH_REG_STS);
>
> @@ -194,11 +208,15 @@ static int wm8505fb_set_timing(struct fb_info *info)
>         writel(h_end,   fbi->regbase + REG_GOVRH_ACTPX_END);
>         writel(h_all,   fbi->regbase + REG_GOVRH_H_ALLPXL);
>         writel(h_sync,  fbi->regbase + REG_GOVRH_HDMI_HSYNW);
> +       if (fbi->interface == INTERFACE_VGA)
> +               writel(h_sync,  fbi->regbase + REG_GOVRH_VGA_HSYNW);

Will it misbehave on LCD if you write to the VGA register unconditionally?

>         writel(v_start, fbi->regbase + REG_GOVRH_ACTLN_BG);
>         writel(v_end,   fbi->regbase + REG_GOVRH_ACTLN_END);
>         writel(v_all,   fbi->regbase + REG_GOVRH_V_ALLLN);
>         writel(v_sync,  fbi->regbase + REG_GOVRH_HDMI_VBISW);
> +       if (fbi->interface == INTERFACE_VGA)
> +               writel(info->var.pixclock,  fbi->regbase + REG_GOVRH_VGA_VSYNW);

Same here. I would assume that setting the pixclock should not hurt
LCD, which would then simplify the code a little.

Thanks,
Alexey


From andy.chernyak at gmail.com  Sat May 18 09:41:45 2013
From: andy.chernyak at gmail.com (Andy Chernyak)
Date: Sat, 18 May 2013 15:41:45 +0200
Subject: [PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.
In-Reply-To: <CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
 <1368868514-18975-5-git-send-email-linux@prisktech.co.nz>
 <CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com>
Message-ID: <51978519.7090907@gmail.com>

On 05/18/2013 03:28 PM, Alexey Charkov wrote:
> 2013/5/18 Tony Prisk <linux at prisktech.co.nz>:
>
>>         /* Virtual buffer size */
>> @@ -167,7 +176,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
>>
>>         /* black magic ;) */
>>         writel(0xf,                    fbi->regbase + REG_GOVRH_FHI);
>> -       writel(4,                      fbi->regbase + REG_GOVRH_DVO_SET);
>> +
>> +       if (fbi->interface == INTERFACE_VGA)
>> +               writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET);
>> +       else
>> +               writel(4, fbi->regbase + REG_GOVRH_DVO_SET);
> I don't remember if HDMI is yet another option for this register or
> not... If it is, it would probably warrant defining fbi->interface as
> an enum and changing this if-else into a switch statement to let the
> compiler add its checks/warnings.
HDMI output can work simultaneously with LCD (on 8850 at least), which
fbi->interface in its current form would not allow to express.

> +       if (fbi->interface == INTERFACE_VGA)
> +               writel(h_sync,  fbi->regbase + REG_GOVRH_VGA_HSYNW);
> Will it misbehave on LCD if you write to the VGA register unconditionally?
>
Can we have 3 flags, something like LCD_ON, VGA_ON, HDMI_ON instead of
enum for video interface selection?

Regards,
Andy.


From nerv at dawncrow.de  Sat May 18 11:02:25 2013
From: nerv at dawncrow.de (=?ISO-8859-15?Q?Andr=E9_Hentschel?=)
Date: Sat, 18 May 2013 17:02:25 +0200
Subject: [PATCHv4] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
In-Reply-To: <518AA19B.2020209@dawncrow.de>
References: <518AA19B.2020209@dawncrow.de>
Message-ID: <51979801.7010903@dawncrow.de>

Am 08.05.2013 21:03, schrieb Andr? Hentschel:
> From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>
> 
> Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
> prevent it from being used as a covert channel between two tasks.
> 
> There are more and more applications coming to WinRT, Wine could support them,
> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
> 
> This patch preserves that register per thread instead of clearing it.
> Unlike the TPIDRURO, which is already switched, the TPIDRURW
> can be updated from userspace so needs careful treatment in the case that we
> modify TPIDRURW and call fork(). To avoid this we must always read
> TPIDRURW in copy_thread.
> 
> Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com> 
> 

Hi,
I'm not yet very familiar with the development process here,
am i getting no feedback on v4 because of the mergewindow being closed?
Or is there another reason? Sry for being impatient.


From w at 1wt.eu  Sat May 18 13:01:58 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Sat, 18 May 2013 19:01:58 +0200
Subject: ARM: 3.10-rc1 does not boot anymore on OpenBlocks AX3
Message-ID: <20130518170158.GB1936@1wt.eu>

Hi Gregory,

I wanted to give a try to your marvell-pcie-v10-and-seb-clks branch on
my AX3 and got the following error, which I also got after switching
back to plain 3.10-rc1 :

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 3.10.0-rc-mvebu (willy at pcw) (gcc version 4.7.3 20130205 (prerelease) (crosstool-NG 1.18.0) ) #6 SMP Sat May 18 17:40:55 CEST 2013
CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine: Marvell Armada 370/XP (Device Tree), model: PlatHome OpenBlocks AX3-4 board
bootconsole [earlycon0] enabled
INITRD: 0x07000040+0x00a5c000 is not a memory region - disabling initrd
Memory policy: ECC disabled, Data cache writealloc
Kernel panic - not syncing: ERROR: Failed to allocate 0x1000 bytes below 0x0.

Finally I bisected this to the following patch :

  commit 74898364e717c6bd939bb88d95049fc91d2b4950
  Author: Gregory CLEMENT <gregory.clement at free-electrons.com>
  Date:   Fri Apr 12 16:29:10 2013 +0200

    ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
    
    In order to be able to use more than 4GB of RAM when the LPAE is
    activated, the dts must be converted in 64 bits.
    
    Only Armada XP is LPAE capable, but as it shares a common dtsi file
    with Armada 370, then the common file include the skeleton64. Thanks
    to the use of the overload capability of the device tree format,
    armada-370 include the 32 bit skeleton and all the armada 370 based
    dts can remain the same.
    
    This was heavily based on the work of Lior Amsalem.
    
    Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

I'm used to boot my kernel and initrd from the network this way :

  tftpboot 0x7000000 uInitrd4
  tftpboot 0x6400000 uImage-ax3.dtb
  bootm 0x6400000 0x7000000

So the address reported above clearly is the one of the initrd, and
the reported size seems to match my initrd's size (10 MB). I tried
to load at a lower address but it did not change anything. I bisected
using mvebu_defconfig.

My AX3 has 3 GB of RAM if that can make a difference (I still have
not found a 4GB DDR3 module to experiment with). Do you have any idea
of what causes the issue, or do you want me to run more tests ? I can
even open it and remove the 2GB DDR3 module if that can help diagnose
the issue.

Thanks,
Willy



From oliver+list at schinagl.nl  Sat May 18 13:19:43 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Sat, 18 May 2013 19:19:43 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <51969EA9.1060602@free-electrons.com>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <51969EA9.1060602@free-electrons.com>
Message-ID: <5197B82F.8010809@schinagl.nl>

On 05/17/13 23:18, Maxime Ripard wrote:
> Hi Oliver,
>
> Le 17/05/2013 15:35, Oliver Schinagl a ?crit :
>> From: Oliver Schinagl <oliver at schinagl.nl>
>>
>> Allwinner has electric fuses (efuse) on their line of chips. This driver
>> reads those fuses and exports them as a sysfs node. Also a symbol is exported
>> for in-kernel useage.
>>
>> While initially these fuses are used to somewhat determin the chipID, these
>> appear to be writeable by the user and thus can be used for other purpouses.
>> For example storing a 128 bit root key, a unique serial number, which could
>> then even be used as a MAC address.
>>
>> Because writing to e-fuses can be potentially dangerous, and are certainly
>> not as often writable (if at all) as flash memory, these shouldn't be easily
>> changeable, hence only a read-only mode. An offline tool to write the fuses
>> is in the works.
>>
>> Currently supported are the following known chips:
>> Allwinner sun4i (A10)
>> Allwinner sun5i (A10s A13)
>> Allwinner sun6i (A31, A31s)
>> Allwinner sun7i (A20)
>
> Since I don't think those patches have been tested on sun6i/sun7i, and
> that there's not even kernel support for those, maybe it's not worth
> mentionning them?
A31 is out in the wild, but haven't seen that functionality in, I have 
seen the register named and defined, just not used, so that could go 
until confirmed.

A20 has the same feature as we can see in the dumped sources. [0]


>
>>
>> Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
>> ---
>>   drivers/misc/eeprom/Kconfig     |  19 ++++
>>   drivers/misc/eeprom/Makefile    |   1 +
>>   drivers/misc/eeprom/sunxi_sid.c | 218 ++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 238 insertions(+)
>>   create mode 100644 drivers/misc/eeprom/sunxi_sid.c
>>
>> diff --git a/drivers/misc/eeprom/Kconfig b/drivers/misc/eeprom/Kconfig
>> index 04f2e1f..c9ddda5 100644
>> --- a/drivers/misc/eeprom/Kconfig
>> +++ b/drivers/misc/eeprom/Kconfig
>> @@ -96,4 +96,23 @@ config EEPROM_DIGSY_MTC_CFG
>>
>>   	  If unsure, say N.
>>
>> +config EEPROM_SUNXI_SID
>> +	tristate "Allwinner sunxi security ID support"
>> +	depends on ARCH_SUNXI && SYSFS
>> +	help
>> +	  This is a driver for the 'security ID' available on various Allwinner
>> +	  devices. Currently supported are:
>> +		sun4i (A10)
>> +		sun5i (A10s, A12, A13)
>> +		sun6i (A31)
>> +		sun7i (A20)
>
> Same things here.
>
>> +
>> +	  Due to the potential risks involved with changing e-fuses,
>> +	  this driver is read-only
>> +
>> +	  For more information visit http://linux-sunxi.org/SID
>> +
>> +	  This driver can also be built as a module. If so, the module
>> +	  will be called sunxi_sid.
>> +
>>   endmenu
>> diff --git a/drivers/misc/eeprom/Makefile b/drivers/misc/eeprom/Makefile
>> index fc1e81d..9507aec 100644
>> --- a/drivers/misc/eeprom/Makefile
>> +++ b/drivers/misc/eeprom/Makefile
>> @@ -4,4 +4,5 @@ obj-$(CONFIG_EEPROM_LEGACY)	+= eeprom.o
>>   obj-$(CONFIG_EEPROM_MAX6875)	+= max6875.o
>>   obj-$(CONFIG_EEPROM_93CX6)	+= eeprom_93cx6.o
>>   obj-$(CONFIG_EEPROM_93XX46)	+= eeprom_93xx46.o
>> +obj-$(CONFIG_EEPROM_SUNXI_SID)	+= sunxi_sid.o
>>   obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o
>> diff --git a/drivers/misc/eeprom/sunxi_sid.c b/drivers/misc/eeprom/sunxi_sid.c
>> new file mode 100644
>> index 0000000..953f137
>> --- /dev/null
>> +++ b/drivers/misc/eeprom/sunxi_sid.c
>> @@ -0,0 +1,218 @@
>> +/*
>> + * Copyright (c) 2013 Oliver Schinagl
>> + * http://www.linux-sunxi.org
>> + *
>> + * Oliver Schinagl <oliver at schinagl.nl>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * This driver exposes the Allwinner security ID, a 128 bit eeprom, in chunks
>> + * of 8 bytes.
>
> 16 bytes or 8 bits? because 8 bytes != 128 bits.
fixed, it was late when I wrote that :( It is indeed 8 bits, e.g. byte 
sized chunks.

>
>> + */
>> +
>> +#include <linux/compiler.h>
>> +#include <linux/device.h>
>> +#include <linux/errno.h>
>> +#include <linux/export.h>
>> +#include <linux/fs.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/kobject.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/stat.h>
>> +#include <linux/sysfs.h>
>> +#include <linux/types.h>
>> +
>> +
>> +#define DRV_NAME "sunxi-sid"
>> +#define DRV_VERSION "1.0"
>> +
>> +/* Register offsets */
>> +#define SUNXI_SID_KEY0 0x00
>> +#define SUNXI_SID_KEY1 0x04
>> +#define SUNXI_SID_KEY2 0x08
>> +#define SUNXI_SID_KEY3 0x0c
>> +
>> +/* There are 4 32-bit keys */
>> +#define SUNXI_SID_KEYS 4
>> +/* and 4 32-bit keys per 32-bit key */
>
> The comment is wrong here.
Same as above, corrected.

>
>> +#define SUNXI_SID_SIZE (SUNXI_SID_KEYS * 4)
>> +
>> +#if (SUNXI_SID_SIZE > PAGE_SIZE)
>> +#error "SUNXI_SID_SIZE is larger then the target's PAGE_SIZE, ENOMEM."
>> +#endif
>
> Hmmmm, I don't follow you here, what's the relation between your driver
> and PAGE_SIZE?
Nothing, I thought there was, but isn't. removed.
>
>> +
>> +static u8 keys_lut[] = {
>> +	SUNXI_SID_KEY0,
>> +	SUNXI_SID_KEY1,
>> +	SUNXI_SID_KEY2,
>> +	SUNXI_SID_KEY3,
>> +};
>> +
>> +struct sid_priv {
>> +	void __iomem *sid_base;
>> +};
>> +
>> +struct sid_priv *p;
>
> What's the point of having a structure here? And why putting a global
> value, !static, with a generic name, while you could have an
> instance-specific one?
Forgot the static keyword, and the struct kept on shrinking until only 
the base address was left. I guess memory wise it shouldn't make a 
difference, but the compiler also doesn't agree, so gone it is :)
>
> struct file has a private_data field, use it.
But since we don't 'open' it, we can't use that, as we talked on IRC.

>
>> +
>> +
>> +/* We read the entire key, using a look up table. Returned is only the
>> + * requested byte. This is of course slower then it could be and uses 4 times
>> + * more reads as needed but keeps code a little simpler.
>> + */
>> +u8 sunxi_sid_read_byte(const int key)
>> +{
>> +	u32 sid_key;
>> +	u8 ret;
>> +
>> +	ret = 0;
>> +	if (likely((key <= SUNXI_SID_SIZE))) {
>> +		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
>> +		switch (key % 4) {
>> +		case 0:
>> +			ret = (sid_key >> 24) & 0xff;
>> +			break;
>> +		case 1:
>> +			ret = (sid_key >> 16) & 0xff;
>> +			break;
>> +		case 2:
>> +			ret = (sid_key >> 8) & 0xff;
>> +			break;
>> +		case 3:
>> +			ret = sid_key & 0xff;
>> +			break;
>> +		}
>> +	}
>
> Come on, you can do better. This lookup table is useless.
I didn't want to depend on the fixed layout of memory, but consider it 
removed.
>
> Also, why the first key is the one with the MSBs?
> I'd expect that the key 0 is the one holding the LSBs.
Strangely enough, they have swapped the MSB and LSB bytes. I double 
checked it with u-boot and yep, swapped. Though in the end, if we write 
stuff there and we read stuff from there, order doesn't matter? So what 
do we prefer. Have it so that it makes sense and ignore how u-boot reads 
it, or correct it and be consistent?

>
>> +
>> +	return ret;
>> +}
>> +
>> +static ssize_t sid_read(struct file *fd, struct kobject *kobj,
>> +			struct bin_attribute *attr, char *buf,
>> +			loff_t pos, size_t size)
>> +{
>> +	ssize_t ret;
>> +	struct device *dev;
>> +	struct sid_priv *priv;
>> +	int i;
>> +
>> +	ret = -EPERM;
>> +	dev = kobj_to_dev(kobj);
>> +	priv = dev_get_drvdata(dev);
>> +
>> +	if ((likely(size > 0)) && ((size + pos) <= SUNXI_SID_SIZE)) {
>> +		for (i = 0; i < size; i++) {
>> +			buf[i] = sunxi_sid_read_byte(pos + i);
>> +		}
>> +		if (i < PAGE_SIZE) {
>> +			buf[i] = '\0';
>> +			ret = (ssize_t)size;
>> +		} else {
>> +			ret = -ENOMEM;
>> +		}
>
> Hmmmm, what? Why returning \0 here? It's not a string, it's binary data.
> What's the relation with PAGE_SIZE again?
I thought that buf is at most PAGE_SIZE large [1] "sysfs allocates a 
buffer of size (PAGE_SIZE) and passes it to the method."
>
> Just return the number of bytes read, that's it.
Yes, had forgotten that this was of course the binary read function and 
not the text version. So yeah, in the binary case, gone.
>
>> +	} else {
>> +		buf[0] = '\0';
>> +		ret = 0;
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +static struct of_device_id sid_of_match[] = {
>> +	{
>> +		.compatible = "allwinner,sun4i-sid",
>> +	},
>> +	{/* sentinel */}
>> +};
>> +MODULE_DEVICE_TABLE(of, sid_of_match);
>> +
>> +static struct bin_attribute sid_bin_attr = {
>> +	.attr = {
>> +		.name = "key",
>> +		.mode = S_IRUGO,
>> +	},
>> +	.size = SUNXI_SID_SIZE,
>> +	.read = sid_read,
>> +};
>> +
>> +static int sid_remove(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct sid_priv *priv;
>> +
>> +	priv = dev_get_drvdata(dev);
>> +	device_remove_bin_file(dev, &sid_bin_attr);
>> +	iounmap(priv->sid_base);
>> +	devm_kfree(dev, priv);
>> +	return 0;
>> +}
>> +
>> +static int __init sid_probe(struct platform_device *pdev)
>> +{
>> +	int ret;
>> +	struct device *dev = &pdev->dev;
>> +	struct sid_priv *priv;
>> +
>> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> +	p = priv;
>> +
>> +	dev_set_drvdata(dev, priv);
>> +
>> +	if (!priv) {
>> +		dev_err(dev, "Unable to allocate device private data\n");
>> +		ret = -ENOMEM;
>> +		goto exit;
>> +	}
>
> Isn't it a bit weird to check for the memory allocation after using the
Yes, more 'oops'. Re-arranged.
> variable. Also, you don't really need the dev_err, since if the kernel
> fails to allocate some memory, it will tell you anyway.
I had it there mostly for consistency, the other 2 did the same check. 
Initially I had 5 functions here, but you corrected me on that :)

>
>> +	priv->sid_base = of_iomap(dev->of_node, 0);
>> +	if (!priv->sid_base) {
>> +		dev_err(dev, "Unable to map memory region\n");
>> +		ret = -ENOMEM;
>> +		goto exit_free;
>> +	}
>> +
>> +	ret = device_create_bin_file(dev, &sid_bin_attr);
>> +	if (ret) {
>> +		dev_err(dev, "Unable to create sysfs bin entry\n");
>> +		goto exit_unmap;
>> +	}
>
> Hmmm, maybe it's not worth all these gotos just for an iounmap, I'd
> probably return right away, but that's your call.
I saw a lot of drivers do the goto: dance in init/probe/exit/remove 
functions, I don't think the overhead here would be so bad?
>
>> +	dev_info(dev, "Sunxi security ID driver loaded successfully.\n");
>> +
>> +	return 0;
>> +
>> +
>> +exit_unmap:
>> +	iounmap(priv->sid_base);
>> +exit_free:
>> +	devm_kfree(dev, priv);
>> +exit:
>> +	return ret;
>> +}
>> +
>> +static struct platform_driver sid_driver = {
>> +	.probe = sid_probe,
>> +	.remove = sid_remove,
>> +	.driver = {
>> +		.name = DRV_NAME,
>> +		.owner = THIS_MODULE,
>> +		.of_match_table = sid_of_match,
>> +	},
>> +};
>> +module_platform_driver(sid_driver);
>> +
>> +
>> +MODULE_AUTHOR("Oliver Schinagl <oliver at schinagl.nl>");
>> +MODULE_DESCRIPTION("Allwinner sunxi security id driver");
>> +MODULE_VERSION(DRV_VERSION);
>> +MODULE_LICENSE("GPL");
>>
>
> Thanks for this driver!
> Maxime
>
You are welcome! :D While awaiting more feedback, i've pushed the 
current version to my github [2].

Oliver

[0] 
https://github.com/amery/linux-allwinner/blob/lichee-3.3/sun7i-dev/arch/arm/mach-sun7i/security_id.c#L91
[1] https://www.kernel.org/doc/Documentation/filesystems/sysfs.txt
[2] 
https://github.com/oliv3r/linux/blob/wip/sunxi-security-id/drivers/misc/eeprom/sunxi_sid.c


From gregory.clement at free-electrons.com  Sat May 18 13:21:18 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sat, 18 May 2013 19:21:18 +0200
Subject: ARM: 3.10-rc1 does not boot anymore on OpenBlocks AX3
In-Reply-To: <20130518170158.GB1936@1wt.eu>
References: <20130518170158.GB1936@1wt.eu>
Message-ID: <5197B88E.1050305@free-electrons.com>

Hi Willy,

On 05/18/2013 07:01 PM, Willy Tarreau wrote:
> Hi Gregory,
> 
> I wanted to give a try to your marvell-pcie-v10-and-seb-clks branch on
> my AX3 and got the following error, which I also got after switching
> back to plain 3.10-rc1 :
> 
> Uncompressing Linux... done, booting the kernel.
> Booting Linux on physical CPU 0x0
> Linux version 3.10.0-rc-mvebu (willy at pcw) (gcc version 4.7.3 20130205 (prerelease) (crosstool-NG 1.18.0) ) #6 SMP Sat May 18 17:40:55 CEST 2013
> CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c53c7d
> CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> Machine: Marvell Armada 370/XP (Device Tree), model: PlatHome OpenBlocks AX3-4 board
> bootconsole [earlycon0] enabled
> INITRD: 0x07000040+0x00a5c000 is not a memory region - disabling initrd
> Memory policy: ECC disabled, Data cache writealloc
> Kernel panic - not syncing: ERROR: Failed to allocate 0x1000 bytes below 0x0.

This is a known issue (at least by me! ;) ).
You have 2 choices:
- either you disable CONFIG_ARM_APPENDED_DTB
- or you appliy the patch "ARM: zImage: Convert 32bits memory size
 and address from ATAG to 64bits DTB"
see https://patchwork.kernel.org/patch/2566771/

This patch have been applied by Russell King in his git tree, and I hope
he will push it soon to Linus for the 3.10-rc2.

By the way I also sent an other fix for led and gpio button:
https://patchwork.kernel.org/patch/2582531/

Regards,


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From ezequiel.garcia at free-electrons.com  Sat May 18 13:22:13 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Sat, 18 May 2013 14:22:13 -0300
Subject: ARM: 3.10-rc1 does not boot anymore on OpenBlocks AX3
In-Reply-To: <20130518170158.GB1936@1wt.eu>
References: <20130518170158.GB1936@1wt.eu>
Message-ID: <20130518172212.GA21837@localhost>

Hi Willy,

On Sat, May 18, 2013 at 07:01:58PM +0200, Willy Tarreau wrote:
> 
> Uncompressing Linux... done, booting the kernel.
> Booting Linux on physical CPU 0x0
> Linux version 3.10.0-rc-mvebu (willy at pcw) (gcc version 4.7.3 20130205 (prerelease) (crosstool-NG 1.18.0) ) #6 SMP Sat May 18 17:40:55 CEST 2013
> CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c53c7d
> CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> Machine: Marvell Armada 370/XP (Device Tree), model: PlatHome OpenBlocks AX3-4 board
> bootconsole [earlycon0] enabled
> INITRD: 0x07000040+0x00a5c000 is not a memory region - disabling initrd
> Memory policy: ECC disabled, Data cache writealloc
> Kernel panic - not syncing: ERROR: Failed to allocate 0x1000 bytes below 0x0.

This is a known issue.
Please try again with this patch:

[PATCH] ARM: zImage: Convert 32bits memory size and address from ATAG to
64bits DTB

which has been posted on LAKML on May 14th.
-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com


From w at 1wt.eu  Sat May 18 13:26:33 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Sat, 18 May 2013 19:26:33 +0200
Subject: ARM: 3.10-rc1 does not boot anymore on OpenBlocks AX3
In-Reply-To: <20130518172212.GA21837@localhost>
References: <20130518170158.GB1936@1wt.eu> <20130518172212.GA21837@localhost>
Message-ID: <20130518172633.GD1936@1wt.eu>

Hi Gregory & Ezequeil,

On Sat, May 18, 2013 at 02:22:13PM -0300, Ezequiel Garcia wrote:
> Hi Willy,
> 
> On Sat, May 18, 2013 at 07:01:58PM +0200, Willy Tarreau wrote:
> > 
> > Uncompressing Linux... done, booting the kernel.
> > Booting Linux on physical CPU 0x0
> > Linux version 3.10.0-rc-mvebu (willy at pcw) (gcc version 4.7.3 20130205 (prerelease) (crosstool-NG 1.18.0) ) #6 SMP Sat May 18 17:40:55 CEST 2013
> > CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c53c7d
> > CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> > Machine: Marvell Armada 370/XP (Device Tree), model: PlatHome OpenBlocks AX3-4 board
> > bootconsole [earlycon0] enabled
> > INITRD: 0x07000040+0x00a5c000 is not a memory region - disabling initrd
> > Memory policy: ECC disabled, Data cache writealloc
> > Kernel panic - not syncing: ERROR: Failed to allocate 0x1000 bytes below 0x0.
> 
> This is a known issue.
> Please try again with this patch:
> 
> [PATCH] ARM: zImage: Convert 32bits memory size and address from ATAG to
> 64bits DTB
> 
> which has been posted on LAKML on May 14th.

Thanks to you both for your simultaneous response :-)
I did notice this patch a few days ago but did not understant it could be
related to this issue. Back to patching and testing then :-)

Thanks!
Willy



From elezegarcia at gmail.com  Sat May 18 13:28:57 2013
From: elezegarcia at gmail.com (Ezequiel Garcia)
Date: Sat, 18 May 2013 14:28:57 -0300
Subject: ARM: 3.10-rc1 does not boot anymore on OpenBlocks AX3
In-Reply-To: <20130518172633.GD1936@1wt.eu>
References: <20130518170158.GB1936@1wt.eu> <20130518172212.GA21837@localhost>
 <20130518172633.GD1936@1wt.eu>
Message-ID: <CALF0-+UfQeh-vKMmm7Eehbw6MNtouL0i+BceC2zVmBk5s7QfGg@mail.gmail.com>

On Sat, May 18, 2013 at 2:26 PM, Willy Tarreau <w at 1wt.eu> wrote:
> Hi Gregory & Ezequeil,
>
> On Sat, May 18, 2013 at 02:22:13PM -0300, Ezequiel Garcia wrote:
>> Hi Willy,
>>
>> On Sat, May 18, 2013 at 07:01:58PM +0200, Willy Tarreau wrote:
>> >
>> > Uncompressing Linux... done, booting the kernel.
>> > Booting Linux on physical CPU 0x0
>> > Linux version 3.10.0-rc-mvebu (willy at pcw) (gcc version 4.7.3 20130205 (prerelease) (crosstool-NG 1.18.0) ) #6 SMP Sat May 18 17:40:55 CEST 2013
>> > CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c53c7d
>> > CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
>> > Machine: Marvell Armada 370/XP (Device Tree), model: PlatHome OpenBlocks AX3-4 board
>> > bootconsole [earlycon0] enabled
>> > INITRD: 0x07000040+0x00a5c000 is not a memory region - disabling initrd
>> > Memory policy: ECC disabled, Data cache writealloc
>> > Kernel panic - not syncing: ERROR: Failed to allocate 0x1000 bytes below 0x0.
>>
>> This is a known issue.
>> Please try again with this patch:
>>
>> [PATCH] ARM: zImage: Convert 32bits memory size and address from ATAG to
>> 64bits DTB
>>
>> which has been posted on LAKML on May 14th.
>
> Thanks to you both for your simultaneous response :-)

That's because our mvebu stuff has enabled parallel user support :-)
-- 
    Ezequiel


From moinejf at free.fr  Sat May 18 13:33:54 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sat, 18 May 2013 19:33:54 +0200
Subject: [RFC 2/4] ARM: dove: add video card node for SolidRun CuBox
In-Reply-To: <1368897139-25485-3-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-3-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130518193354.1be73084@armhf>

On Sat, 18 May 2013 19:12:17 +0200
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:

> This adds a video card node required for rmk's dove_drm driver. Reg
> property matches reserved memory region (currently 16M at top of memory),
> clocks property should carry extclk0 for now.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: dri-devel at lists.freedesktop.org
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> ---
>  arch/arm/boot/dts/dove-cubox.dts |   16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
> index ed2b7b2..f26d0d2 100644
> --- a/arch/arm/boot/dts/dove-cubox.dts
> +++ b/arch/arm/boot/dts/dove-cubox.dts
> @@ -8,7 +8,7 @@
>  
>  	memory {
>  		device_type = "memory";
> -		reg = <0x00000000 0x40000000>;
> +		reg = <0x00000000 0x3f000000>;
>  	};
>  
>  	chosen {
> @@ -52,10 +52,24 @@
>  			#clock-cells = <0>;
>  		};
>  	};
> +
> +	video {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		vcard: video-card {
> +			compatible = "marvell,dove-video-card";
> +			reg = <0x3f000000 0x1000000>;
> +			clocks = <&si5351 0>, <&si5351 0>;
> +		};
> +	};
>  };
>  
>  &uart0 { status = "okay"; };
>  &sata0 { status = "okay"; };
> +&lcd0 { status = "okay"; };
>  
>  &i2c0 {
>  	status = "okay";

May you explain a bit more this strange hack?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From moinejf at free.fr  Sat May 18 13:45:02 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sat, 18 May 2013 19:45:02 +0200
Subject: [RFC 3/4] DRM: add OF support for Dove DRM driver
In-Reply-To: <1368897139-25485-4-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-4-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130518194502.102caa9e@armhf>

On Sat, 18 May 2013 19:12:18 +0200
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:

> This adds OF support for the Dove DRM driver recently posted as RFC by
> Russell King.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: dri-devel at lists.freedesktop.org
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> ---
>  drivers/gpu/drm/dove/Kconfig     |    4 ++
>  drivers/gpu/drm/dove/Makefile    |    1 +
>  drivers/gpu/drm/dove/dove_card.c |  110 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 115 insertions(+)
>  create mode 100644 drivers/gpu/drm/dove/dove_card.c
> 
> diff --git a/drivers/gpu/drm/dove/Kconfig b/drivers/gpu/drm/dove/Kconfig
> index 718d3c5..a943ea5 100644
> --- a/drivers/gpu/drm/dove/Kconfig
> +++ b/drivers/gpu/drm/dove/Kconfig
> @@ -28,4 +28,8 @@ config DRM_DOVE_TDA1998X
>  config DRM_DOVE_CURSOR
>  	bool "Enable Dove DRM hardware cursor support"
>  
> +config DRM_DOVE_OF
> +	bool "Enable Dove DRM OF video card"
> +	depends on OF
> +
>  endif
> diff --git a/drivers/gpu/drm/dove/Makefile b/drivers/gpu/drm/dove/Makefile
> index 65c701e..f0b6eed 100644
> --- a/drivers/gpu/drm/dove/Makefile
> +++ b/drivers/gpu/drm/dove/Makefile
> @@ -5,5 +5,6 @@ dove-y			:= dove_crtc.o dove_drv.o dove_fb.o dove_fbdev.o \
>  dove-$(CONFIG_DEBUG_FS) += dove_debugfs.o
>  
>  dove-$(CONFIG_DRM_DOVE_TDA1998X) += dove_tda19988.o
> +dove-$(CONFIG_DRM_DOVE_OF) += dove_card.o
>  
>  obj-$(CONFIG_DRM_DOVE) := dove.o
> diff --git a/drivers/gpu/drm/dove/dove_card.c b/drivers/gpu/drm/dove/dove_card.c
> new file mode 100644
> index 0000000..e4bcb5b
> --- /dev/null
> +++ b/drivers/gpu/drm/dove/dove_card.c
> @@ -0,0 +1,110 @@
> +/*
> + * Copyright (C) 2013
> + *   Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +#define DOVE_LCD0_BASE	0x20000
> +#define DOVE_LCD1_BASE	0x10000
> +
> +static struct resource dove_drm_resources[5];
> +static struct platform_device dove_drm_platform_device = {
> +	.name = "dove-drm",
> +	.id = 0,
> +	.dev = { .coherent_dma_mask = ~0, },
> +	.resource = dove_drm_resources,
> +};
> +
> +static int dove_card_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct device_node *lcdnp;
> +	struct resource *res = dove_drm_resources;
> +	int ret, n = 0, crtcs = 0;
> +
> +	/* get video memory resource */
> +	if (of_address_to_resource(np, 0, &res[n++])) {
> +		dev_err(&pdev->dev, "invalid or missing video memory\n");
> +		return -EINVAL;
> +	}
> +
> +	/* get reg and irq resource from each enabled lcdc */
> +	for_each_compatible_node(lcdnp, NULL, "marvell,dove-lcd") {
> +		struct clk_lookup *cl;
> +		struct clk *clk;
> +		int lcd;
> +
> +		if (!of_device_is_available(lcdnp))
> +			continue;
> +
> +		ret = of_address_to_resource(lcdnp, 0, &res[n]);
> +		if (ret)
> +			return ret;
> +		lcd = ((res[n].start & 0xfffff) == DOVE_LCD1_BASE);
> +		n++;
> +
> +		ret = of_irq_to_resource(lcdnp, 0, &res[n]);
> +		if (ret < 0)
> +			return ret;
> +		n++;
> +
> +		crtcs++;
> +
> +		clk = clk_get(&pdev->dev, NULL);
> +		if (IS_ERR(clk)) {
> +			ret = PTR_ERR(clk);
> +			if (ret == -ENOENT)
> +				return -EPROBE_DEFER;
> +			return ret;
> +		}
> +
> +		/* add clock alias for dovefb.0 */
> +		cl = clkdev_alloc(clk, "extclk", "dovefb.0");
> +		if (cl)
> +			clkdev_add(cl);
> +		clk_put(clk);
> +	}
> +
> +	if (!crtcs)
> +		return -ENODEV;
> +
> +	dove_drm_platform_device.num_resources = n;
> +	ret = platform_device_register(&dove_drm_platform_device);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to register drm device\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id dove_card_of_ids[] = {
> +	{ .compatible = "marvell,dove-video-card", },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, dove_card_of_ids);
> +
> +static struct platform_driver dove_card_driver = {
> +	.probe	= dove_card_probe,
> +	.driver	= {
> +		.owner	= THIS_MODULE,
> +		.name	= "dove-drm-card",
> +		.of_match_table = of_match_ptr(dove_card_of_ids),
> +	},
> +};
> +module_platform_driver(dove_card_driver);
> +
> +MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
> +MODULE_DESCRIPTION("Dove DRM Graphics Card");
> +MODULE_LICENSE("GPL");

It seems we are moving backwards:
- what about the display controller?
- how do you clone the lcd 0 output to the port B?
- what occurs when the si5351 and the tda998x are modules?

My driver had the same layout as Russell's when I proposed it to you
and when you insisted to handle the 2 LCDs and the 2 ports as one card.
I spent 2 months to have a nice design and you put it to garbage!
I am not happy...

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From moinejf at free.fr  Sat May 18 13:46:44 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sat, 18 May 2013 19:46:44 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130518194644.2a02a4fc@armhf>

On Sat, 18 May 2013 19:12:19 +0200
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:

> The RFC sent by Russell King was missing an include for tda998x. This
> is just a compatible clone to remember Russell to add that later.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: dri-devel at lists.freedesktop.org
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> ---
>  include/drm/i2c/tda998x.h |   23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 include/drm/i2c/tda998x.h
> 
> diff --git a/include/drm/i2c/tda998x.h b/include/drm/i2c/tda998x.h
> new file mode 100644
> index 0000000..41f799f
> --- /dev/null
> +++ b/include/drm/i2c/tda998x.h
> @@ -0,0 +1,23 @@
> +#ifndef __TDA998X_H__
> +#define __TDA998X_H__
> +
> +enum tda998x_audio_format {
> +	AFMT_I2S,
> +	AFMT_SPDIF,
> +};
> +
> +struct tda998x_encoder_params {
> +	int audio_cfg;
> +	int audio_clk_cfg;
> +	enum tda998x_audio_format audio_format;
> +	int audio_sample_rate;
> +	char audio_frame[6];
> +	int swap_a, mirr_a;
> +	int swap_b, mirr_b;
> +	int swap_c, mirr_c;
> +	int swap_d, mirr_d;
> +	int swap_e, mirr_e;
> +	int swap_f, mirr_f;
> +};
> +
> +#endif

These parameters should not be there. It seems to me that the DT is the
right place.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From w at 1wt.eu  Sat May 18 13:48:17 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Sat, 18 May 2013 19:48:17 +0200
Subject: ARM: 3.10-rc1 does not boot anymore on OpenBlocks AX3
In-Reply-To: <CALF0-+UfQeh-vKMmm7Eehbw6MNtouL0i+BceC2zVmBk5s7QfGg@mail.gmail.com>
References: <20130518170158.GB1936@1wt.eu> <20130518172212.GA21837@localhost>
 <20130518172633.GD1936@1wt.eu>
 <CALF0-+UfQeh-vKMmm7Eehbw6MNtouL0i+BceC2zVmBk5s7QfGg@mail.gmail.com>
Message-ID: <20130518174817.GE1936@1wt.eu>

On Sat, May 18, 2013 at 02:28:57PM -0300, Ezequiel Garcia wrote:
> On Sat, May 18, 2013 at 2:26 PM, Willy Tarreau <w at 1wt.eu> wrote:
> > Hi Gregory & Ezequeil,
> >
> > On Sat, May 18, 2013 at 02:22:13PM -0300, Ezequiel Garcia wrote:
> >> Hi Willy,
> >>
> >> On Sat, May 18, 2013 at 07:01:58PM +0200, Willy Tarreau wrote:
> >> >
> >> > Uncompressing Linux... done, booting the kernel.
> >> > Booting Linux on physical CPU 0x0
> >> > Linux version 3.10.0-rc-mvebu (willy at pcw) (gcc version 4.7.3 20130205 (prerelease) (crosstool-NG 1.18.0) ) #6 SMP Sat May 18 17:40:55 CEST 2013
> >> > CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c53c7d
> >> > CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> >> > Machine: Marvell Armada 370/XP (Device Tree), model: PlatHome OpenBlocks AX3-4 board
> >> > bootconsole [earlycon0] enabled
> >> > INITRD: 0x07000040+0x00a5c000 is not a memory region - disabling initrd
> >> > Memory policy: ECC disabled, Data cache writealloc
> >> > Kernel panic - not syncing: ERROR: Failed to allocate 0x1000 bytes below 0x0.
> >>
> >> This is a known issue.
> >> Please try again with this patch:
> >>
> >> [PATCH] ARM: zImage: Convert 32bits memory size and address from ATAG to
> >> 64bits DTB
> >>
> >> which has been posted on LAKML on May 14th.
> >
> > Thanks to you both for your simultaneous response :-)
> 
> That's because our mvebu stuff has enabled parallel user support :-)

:-)

I confirm the fix is OK for me. I'll play a bit with the new
kernel on the box now.

Have a nice week-end,

Willy



From sebastian.hesselbarth at gmail.com  Sat May 18 14:20:00 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 18 May 2013 20:20:00 +0200
Subject: [RFC 3/4] DRM: add OF support for Dove DRM driver
In-Reply-To: <20130518194502.102caa9e@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194502.102caa9e@armhf>
Message-ID: <5197C650.9020802@gmail.com>

On 05/18/2013 07:45 PM, Jean-Francois Moine wrote:
> On Sat, 18 May 2013 19:12:18 +0200
> Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>  wrote:
>> This adds OF support for the Dove DRM driver recently posted as RFC by
>> Russell King.
>>
...

Jean-Francois,

one thing first: It is an RFC! It is to allow you to _test_ rmk's driver
on DT. Nothing more, nothing less.

I will comment on your questions but that all can change for a full
patch set of rmk, you, or me.

The "video-card" node combines all devices that will be available and
active on a specific Dove board. As you may have noticed about rmk's
driver, it is registering crtcs from IORESOURCE_MEM passed with the
platform_device.

To match with this approach we _have to_ recreate that platform_device
from what we see on DT. On DT each bus node gets registered as its own
platform_device. So in the video-card driver we look for node we know
of and put together a platform_device for rmk's driver. We cannot hook
DT upon either an lcd node nor dcon node as they might be disabled and
the driver will get called multiple times.

> It seems we are moving backwards:
> - what about the display controller?

That would be part of probing DT nodes above. I did not take care of
that because rmk doesn't support dcon for now.

> - how do you clone the lcd 0 output to the port B?

Pass properties on video-card node or even better let dcon driver
take care of it when it sees a video-card with more than one crtc.

> - what occurs when the si5351 and the tda998x are modules?

Touche, forgot that part. Feel free to add module support to the
RFC.

> My driver had the same layout as Russell's when I proposed it to you
> and when you insisted to handle the 2 LCDs and the 2 ports as one card.

I still insist to handle 2 LCDs and DCON.

> I spent 2 months to have a nice design and you put it to garbage!
> I am not happy...

I put nothing to garbage. _You_ also agreed to merge with rmk's driver!
We can now put in all features we implemented differently
_step-by-step_.

Merging the drivers starts with adding support for DT - that is what
I provided. You know the HW better than me, why don't you start picking
features from your driver and add them in rmk's driver?

Sebastian


From sebastian.hesselbarth at gmail.com  Sat May 18 14:21:25 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 18 May 2013 20:21:25 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <20130518194644.2a02a4fc@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
Message-ID: <5197C6A5.5070106@gmail.com>

On 05/18/2013 07:46 PM, Jean-Francois Moine wrote:
> On Sat, 18 May 2013 19:12:19 +0200
> Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>  wrote:
>
>> The RFC sent by Russell King was missing an include for tda998x. This
>> is just a compatible clone to remember Russell to add that later.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
...
> These parameters should not be there. It seems to me that the DT is the
> right place.

True, but if you just read the description above:
"RFC sent by Russell King was missing an include for tda998x".

You want to test the RFC, you need that include.

Sebastian


From robdclark at gmail.com  Sat May 18 14:23:19 2013
From: robdclark at gmail.com (Rob Clark)
Date: Sat, 18 May 2013 14:23:19 -0400
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <20130518194644.2a02a4fc@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
Message-ID: <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>

On Sat, May 18, 2013 at 1:46 PM, Jean-Francois Moine <moinejf at free.fr> wrote:
> On Sat, 18 May 2013 19:12:19 +0200
> Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:
>
>> The RFC sent by Russell King was missing an include for tda998x. This
>> is just a compatible clone to remember Russell to add that later.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
>> ---
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: dri-devel at lists.freedesktop.org
>> Cc: Jason Cooper <jason at lakedaemon.net>
>> Cc: Jean-Francois Moine <moinejf at free.fr>
>> ---
>>  include/drm/i2c/tda998x.h |   23 +++++++++++++++++++++++
>>  1 file changed, 23 insertions(+)
>>  create mode 100644 include/drm/i2c/tda998x.h
>>
>> diff --git a/include/drm/i2c/tda998x.h b/include/drm/i2c/tda998x.h
>> new file mode 100644
>> index 0000000..41f799f
>> --- /dev/null
>> +++ b/include/drm/i2c/tda998x.h
>> @@ -0,0 +1,23 @@
>> +#ifndef __TDA998X_H__
>> +#define __TDA998X_H__
>> +
>> +enum tda998x_audio_format {
>> +     AFMT_I2S,
>> +     AFMT_SPDIF,
>> +};
>> +
>> +struct tda998x_encoder_params {
>> +     int audio_cfg;
>> +     int audio_clk_cfg;
>> +     enum tda998x_audio_format audio_format;
>> +     int audio_sample_rate;
>> +     char audio_frame[6];
>> +     int swap_a, mirr_a;
>> +     int swap_b, mirr_b;
>> +     int swap_c, mirr_c;
>> +     int swap_d, mirr_d;
>> +     int swap_e, mirr_e;
>> +     int swap_f, mirr_f;
>> +};
>> +
>> +#endif
>
> These parameters should not be there. It seems to me that the DT is the
> right place.

You might not want to directly have a hard DT dependency in tda998x,
as the encoder could be used on non-DT platforms.  Although a DT to
encoder-params helper might be a nice idea for platforms which do have
DT.

BR,
-R

> --
> Ken ar c'henta? |             ** Breizh ha Linux atav! **
> Jef             |               http://moinejf.free.fr/
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From sebastian.hesselbarth at gmail.com  Sat May 18 14:33:50 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 18 May 2013 20:33:50 +0200
Subject: [RFC 2/4] ARM: dove: add video card node for SolidRun CuBox
In-Reply-To: <20130518193354.1be73084@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-3-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518193354.1be73084@armhf>
Message-ID: <5197C98E.1060104@gmail.com>

On 05/18/2013 07:33 PM, Jean-Francois Moine wrote:
> On Sat, 18 May 2013 19:12:17 +0200
> Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>  wrote:
>> This adds a video card node required for rmk's dove_drm driver. Reg
>> property matches reserved memory region (currently 16M at top of memory),
>> clocks property should carry extclk0 for now.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>> ---
...
>> +		vcard: video-card {
>> +			compatible = "marvell,dove-video-card";
>> +			reg =<0x3f000000 0x1000000>;
>> +			clocks =<&si5351 0>,<&si5351 0>;
>> +		};
>> +	};
...
>> +&lcd0 { status = "okay"; };
>
> May you explain a bit more this strange hack?

This "hack" adds the video-card device node that describes the board
dependent part of Dove SoC video. Remember, it is a device tree node
to match Russel's driver!

You have the video memory passed, the clocks property will vanish
later. And you enable lcd0 as you may have noticed that there is
nothing connected on lcd1 on the _CuBox_.

But there is on the D2Plug, and that DT description _will_ enable
lcd0, lcd1 and dcon.

Maybe, there is a misunderstanding in in the concept of DT here.
DT does _not_ describe the driver layout but the HW. And for Linux
this basically means, you replace board/SoC dependent init code
that register some platform_device with a description in DT.

The actual driver does _not_ need to know about non-DT or DT except
that somebody has to parse it and create a platform_device for it.
If you only have standard properties like reg and irq, it all gets
parsed automagically by DT bus probing. But as you already pointed
out, a video card on Dove is a little bit more complex as reg and
irq - so I provided a DT parser for rmk's *RFC* driver as *RFC*!

Sebastian


From romieu at fr.zoreil.com  Sat May 18 14:55:26 2013
From: romieu at fr.zoreil.com (Francois Romieu)
Date: Sat, 18 May 2013 20:55:26 +0200
Subject: [PATCHv8 3/3] net: velocity: Add platform device support to VIA
 velocity driver
In-Reply-To: <1368853187-17823-4-git-send-email-linux@prisktech.co.nz>
References: <1368853187-17823-1-git-send-email-linux@prisktech.co.nz>
 <1368853187-17823-4-git-send-email-linux@prisktech.co.nz>
Message-ID: <20130518185526.GA25486@electric-eye.fr.zoreil.com>

Tony Prisk <linux at prisktech.co.nz> :
[...]
> diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
> index 5996cee..d8d5bc5 100644
> --- a/drivers/net/ethernet/via/via-velocity.c
> +++ b/drivers/net/ethernet/via/via-velocity.c
[...]
> @@ -84,6 +88,16 @@
>  static int velocity_nics;
>  static int msglevel = MSG_LEVEL_INFO;
>  
> +static void velocity_set_power_state(struct velocity_info *vptr, char state)
> +{
> +	void *addr = vptr->mac_regs;

Your choice but it's only used once.

[...]
> @@ -1353,9 +1366,12 @@ static void velocity_init_registers(struct velocity_info *vptr,
>  		velocity_soft_reset(vptr);
>  		mdelay(5);
>  
> -		mac_eeprom_reload(regs);
> -		for (i = 0; i < 6; i++)
> -			writeb(vptr->netdev->dev_addr[i], &(regs->PAR[i]));
> +		if (!vptr->no_eeprom) {
> +			mac_eeprom_reload(regs);
> +			for (i = 0; i < 6; i++)
> +				writeb(vptr->netdev->dev_addr[i],
> +							&(regs->PAR[i]));
> +		}

velocity_init_registers would not suffer from a local vptr->netdev variable.

If you change this code, you may replace &(regs->PAR[i]) with regs->PAR + i.

[...]
> @@ -2730,19 +2773,19 @@ static int velocity_found1(struct pci_dev *pdev,
>  	 * can support more than MAX_UNITS.
>  	 */
>  	if (velocity_nics >= MAX_UNITS) {
> -		dev_notice(&pdev->dev, "already found %d NICs.\n",
> -			   velocity_nics);
> +		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
>  		return -ENODEV;
>  	}
>  
> -	dev = alloc_etherdev(sizeof(struct velocity_info));
> -	if (!dev)
> +	netdev = alloc_etherdev(sizeof(struct velocity_info));
> +	if (!netdev)
>  		goto out;
>  
>  	/* Chain it all together */
>  
> -	SET_NETDEV_DEV(dev, &pdev->dev);
> -	vptr = netdev_priv(dev);
> +	SET_NETDEV_DEV(netdev, dev);
> +	vptr = netdev_priv(netdev);
> +	memset(vptr, 0, sizeof(struct velocity_info));

memset is not needed (alloc_etherdev indirectly uses kzalloc).

[...]
> +static int velocity_pci_probe(struct pci_dev *pdev,
> +			   const struct pci_device_id *ent)

It does not seem to line up as it should.

> +{
> +	int ret;
> +	const struct velocity_info_tbl *info =
> +					&chip_info_table[ent->driver_data];

Long lines ought to come first.

> +
> +	ret = pci_enable_device(pdev);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = pci_request_regions(pdev, VELOCITY_NAME);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "No PCI resources.\n");
> +		pci_disable_device(pdev);
> +		return ret;
> +	}
> +
> +	ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
> +	if (ret < 0) {
> +		pci_release_regions(pdev);
> +		pci_disable_device(pdev);
> +	}

Please use gotos for the error paths.

[...]
> @@ -3270,7 +3409,11 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
>  	struct velocity_info *vptr = netdev_priv(dev);
>  	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));

You may sneak an empty line after the declaration.

>  	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
> -	strlcpy(info->bus_info, pci_name(vptr->pdev), sizeof(info->bus_info));
> +	if (vptr->bustype == BUS_PCI)
> +		strlcpy(info->bus_info, pci_name(vptr->pdev),
> +						sizeof(info->bus_info));
> +	else
> +		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));

	strlcpy(info->bus_info, vptr->pdev ? pci_name(vptr->pdev) : "platform",
		sizeof(info->bus_info));

>  static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
> @@ -3563,9 +3706,15 @@ static int __init velocity_init_module(void)
>  	int ret;
>  
>  	velocity_register_notifier();
> -	ret = pci_register_driver(&velocity_driver);
> +
> +	ret = pci_register_driver(&velocity_pci_driver);
> +	if (ret < 0)
> +		velocity_unregister_notifier();
> +
> +	ret = platform_driver_register(&velocity_platform_driver);
>  	if (ret < 0)
>  		velocity_unregister_notifier();
> +

I'd rather velocity_unregister_notifier iif both driver registrations
failed.

[...]
> diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
> index c38bbae..1d94612 100644
> --- a/drivers/net/ethernet/via/via-velocity.h
> +++ b/drivers/net/ethernet/via/via-velocity.h
[...]
> @@ -1433,10 +1433,17 @@ struct velocity_opt {
>  
>  #define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
>  
> +enum velocity_bus_type {
> +	BUS_PCI,
> +	BUS_PLATFORM,
> +};
> +
>  struct velocity_info {
> -	struct device *dev;
>  	struct pci_dev *pdev;
> +	struct device *dev;

Please don't move the fields you added.

>  	struct net_device *netdev;
> +	enum velocity_bus_type bustype;

velocity_bus_type is not really needed since you always have pdev to
check against.

-- 
Ueimor


From moinejf at free.fr  Sat May 18 14:58:45 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sat, 18 May 2013 20:58:45 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
Message-ID: <20130518205845.2dfe9fe5@armhf>

On Sat, 18 May 2013 14:23:19 -0400
Rob Clark <robdclark at gmail.com> wrote:

> > These parameters should not be there. It seems to me that the DT is the
> > right place.  
> 
> You might not want to directly have a hard DT dependency in tda998x,
> as the encoder could be used on non-DT platforms.  Although a DT to
> encoder-params helper might be a nice idea for platforms which do have
> DT.

If I correctly understand:

- Russell does not use any DT, so his drm driver should be declared in
  some cubox-setup code in mach-dove/

- this code should also declare the tda998x

- the drm driver contains/passes parameters to the tda998x

As the connection Dove LCD <-> tda998x is Cubox specific, the question
is: why are'nt the tda998x parameters in the cubox-setup code?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From carlo.caione at gmail.com  Sat May 18 15:05:56 2013
From: carlo.caione at gmail.com (Carlo Caione)
Date: Sat, 18 May 2013 21:05:56 +0200
Subject: [PATCH v2] ARM: sunxi: New watchdog driver for Allwinner A10/A13
Message-ID: <1368903956-32388-1-git-send-email-carlo.caione@gmail.com>

This patch adds the driver for the watchdog found in the Allwinner A10 and
A13 SoCs. It has DT-support and uses the new watchdog framework.

Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
---
 drivers/watchdog/Kconfig     |  10 ++
 drivers/watchdog/Makefile    |   1 +
 drivers/watchdog/sunxi_wdt.c | 226 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 237 insertions(+)
 create mode 100644 drivers/watchdog/sunxi_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e89fc31..8ad2238 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -299,6 +299,16 @@ config ORION_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called orion_wdt.
 
+config SUNXI_WATCHDOG
+	tristate "Allwinner SoCs watchdog support"
+	depends on ARCH_SUNXI
+	select WATCHDOG_CORE
+	help
+	  Say Y here to include support for the watchdog timer
+	  in Allwinner SoCs.
+	  To compile this driver as a module, choose M here: the
+	  module will be called sunxi_wdt.
+
 config COH901327_WATCHDOG
 	bool "ST-Ericsson COH 901 327 watchdog"
 	depends on ARCH_U300
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a300b94..5012d5f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
 obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
 obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
+obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
 obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
 obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
new file mode 100644
index 0000000..105b26a
--- /dev/null
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -0,0 +1,226 @@
+/*
+ *      sunxi Watchdog Driver
+ *
+ *      Copyright (c) 2013 Carlo Caione
+ *                    2012 Henrik Nordstrom
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Based on xen_wdt.c
+ *      (c) Copyright 2010 Novell, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/watchdog.h>
+
+#define WDT_MAX_TIMEOUT         16
+#define WDT_MIN_TIMEOUT         1
+#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
+#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
+
+#define WDT_CTRL                0x00
+#define WDT_CTRL_RESTART        (1 << 0)
+#define WDT_CTRL_RESERVED       (0x0a57 << 1)
+
+#define WDT_MODE                0x04
+#define WDT_MODE_EN             (1 << 0)
+#define WDT_MODE_RST_EN         (1 << 1)
+
+#define DRV_NAME		"sunxi-wdt"
+#define DRV_VERSION		"1.0"
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+static int heartbeat = WDT_MAX_TIMEOUT;
+
+/*
+ * wdt_timeout_map maps the watchdog timer interval value in seconds to
+ * the value of the register WDT_MODE bit 3:6
+ *
+ * [timeout seconds] = register value
+ *
+ */
+
+static const int wdt_timeout_map[] = {
+	[1] = 0b0001,  /* 1s  */
+	[2] = 0b0010,  /* 2s  */
+	[3] = 0b0011,  /* 3s  */
+	[4] = 0b0100,  /* 4s  */
+	[5] = 0b0101,  /* 5s  */
+	[6] = 0b0110,  /* 6s  */
+	[8] = 0b0111,  /* 8s  */
+	[10] = 0b1000, /* 10s */
+	[12] = 0b1001, /* 12s */
+	[14] = 0b1010, /* 14s */
+	[16] = 0b1011, /* 16s */
+};
+
+static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	reg = ioread32(wdt_base + WDT_CTRL);
+	reg |= (WDT_CTRL_RESTART | WDT_CTRL_RESERVED);
+	iowrite32(reg, wdt_base + WDT_CTRL);
+
+	return 0;
+}
+
+static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
+		unsigned int timeout)
+{
+	u32 reg;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout]))
+		return -EINVAL;
+
+	sunxi_wdt_dev->timeout = timeout;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg &= ~(WDT_TIMEOUT_MASK);
+	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	sunxi_wdt_ping(sunxi_wdt_dev);
+
+	return 0;
+}
+
+static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg &= ~(WDT_MODE_RST_EN | WDT_MODE_EN);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	return 0;
+}
+
+static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	int ret;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
+	if (ret < 0)
+		return ret;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	return 0;
+}
+
+static const struct watchdog_info sunxi_wdt_info = {
+	.identity	= DRV_NAME,
+	.options	= WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING |
+			  WDIOF_MAGICCLOSE,
+};
+
+static const struct watchdog_ops sunxi_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= sunxi_wdt_start,
+	.stop		= sunxi_wdt_stop,
+	.ping		= sunxi_wdt_ping,
+	.set_timeout	= sunxi_wdt_set_timeout,
+};
+
+static struct watchdog_device sunxi_wdt_dev = {
+	.info		= &sunxi_wdt_info,
+	.ops		= &sunxi_wdt_ops,
+	.timeout	= WDT_MAX_TIMEOUT,
+	.max_timeout	= WDT_MAX_TIMEOUT,
+	.min_timeout	= WDT_MIN_TIMEOUT,
+};
+
+static int __init sunxi_wdt_probe(struct platform_device *pdev)
+{
+	int err;
+	void __iomem *wdt_base;
+
+	wdt_base = of_iomap(pdev->dev.of_node, 0);
+	if (unlikely(!wdt_base)) {
+		err = -ENOMEM;
+		goto error_mem_out;
+	}
+
+	sunxi_wdt_dev.parent = &pdev->dev;
+	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
+	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
+
+	err = watchdog_register_device(&sunxi_wdt_dev);
+	if (unlikely(err))
+		goto error_wdt;
+
+	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
+
+	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
+			sunxi_wdt_dev.timeout, nowayout);
+	return 0;
+
+error_wdt:
+	iounmap(wdt_base);
+error_mem_out:
+	return err;
+}
+
+static int __exit sunxi_wdt_remove(struct platform_device *pdev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
+
+	sunxi_wdt_stop(&sunxi_wdt_dev);
+	watchdog_unregister_device(&sunxi_wdt_dev);
+	iounmap(wdt_base);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_wdt_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-wdt" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
+
+static struct platform_driver sunxi_wdt_driver = {
+	.probe		= sunxi_wdt_probe,
+	.remove		= sunxi_wdt_remove,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= DRV_NAME,
+		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
+	},
+};
+
+module_platform_driver(sunxi_wdt_driver);
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
+
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
+		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
+MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
+MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
+MODULE_VERSION(DRV_VERSION);
-- 
1.8.2.3



From robdclark at gmail.com  Sat May 18 15:11:03 2013
From: robdclark at gmail.com (Rob Clark)
Date: Sat, 18 May 2013 15:11:03 -0400
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <20130518205845.2dfe9fe5@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf>
Message-ID: <CAF6AEGuvte+tfWwC-zDG=TeAo0Qh9-sN-K+0oMTGGa9kBUntOw@mail.gmail.com>

On Sat, May 18, 2013 at 2:58 PM, Jean-Francois Moine <moinejf at free.fr> wrote:
> On Sat, 18 May 2013 14:23:19 -0400
> Rob Clark <robdclark at gmail.com> wrote:
>
>> > These parameters should not be there. It seems to me that the DT is the
>> > right place.
>>
>> You might not want to directly have a hard DT dependency in tda998x,
>> as the encoder could be used on non-DT platforms.  Although a DT to
>> encoder-params helper might be a nice idea for platforms which do have
>> DT.
>
> If I correctly understand:
>
> - Russell does not use any DT, so his drm driver should be declared in
>   some cubox-setup code in mach-dove/
>
> - this code should also declare the tda998x
>
> - the drm driver contains/passes parameters to the tda998x
>
> As the connection Dove LCD <-> tda998x is Cubox specific, the question
> is: why are'nt the tda998x parameters in the cubox-setup code?

ok, maybe I am misunderstanding you.  I think the parameters should be
filled in by the board file on a non-DT setup.  But the part in
drivers/gpu/drm/i2c should not pull them directly out of DT, or should
have an arrangement like

 #ifdef CONFIG_OF
 .. pull params out of DT ..
#else
 .. use params passed in from via params struct, which is populated in
board file ..
#endif

to accommodate non-DT builds.  (Although I think just having a helper
to populate 'struct tda998x_encoder_params' from DT seems cleaner.)


BR,
-R

> --
> Ken ar c'henta? |             ** Breizh ha Linux atav! **
> Jef             |               http://moinejf.free.fr/


From moinejf at free.fr  Sat May 18 15:18:46 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sat, 18 May 2013 21:18:46 +0200
Subject: [RFC 3/4] DRM: add OF support for Dove DRM driver
In-Reply-To: <5197C650.9020802@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194502.102caa9e@armhf> <5197C650.9020802@gmail.com>
Message-ID: <20130518211846.0ef5a14b@armhf>

On Sat, 18 May 2013 20:20:00 +0200
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:

> I put nothing to garbage. _You_ also agreed to merge with rmk's driver!
> We can now put in all features we implemented differently
> _step-by-step_.
> 
> Merging the drivers starts with adding support for DT - that is what
> I provided. You know the HW better than me, why don't you start picking
> features from your driver and add them in rmk's driver?

The general hardware code of both drivers is close enough for merging
may be done starting from anyone. But the general layout is not:

- my driver is DT driven and has one card with 2 CTRC's and 2 connectors.

- Russell's is non-DT, so, with some extra code I am not aware of, with
  any number of cards each one with one CRTC and one connector (no, I
  tried it, you cannot clone a connector of one card to the connector
  of another card).

So, for me, merging means enhance my code from Russell's, but I will
not go to a non-DT kernel.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From sebastian.hesselbarth at gmail.com  Sat May 18 15:30:09 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 18 May 2013 21:30:09 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <20130518205845.2dfe9fe5@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf>
Message-ID: <5197D6C1.3060702@gmail.com>

On 05/18/2013 08:58 PM, Jean-Francois Moine wrote:
> On Sat, 18 May 2013 14:23:19 -0400
> Rob Clark<robdclark at gmail.com>  wrote:
>
>>> These parameters should not be there. It seems to me that the DT is the
>>> right place.
>>
>> You might not want to directly have a hard DT dependency in tda998x,
>> as the encoder could be used on non-DT platforms.  Although a DT to
>> encoder-params helper might be a nice idea for platforms which do have
>> DT.
>
> If I correctly understand:
>
> - Russell does not use any DT, so his drm driver should be declared in
>    some cubox-setup code in mach-dove/

No. The _device_ is declared in some cubox-setup but the _driver_ goes
into drivers/gpu/drm. Reading vendor provided kernel code may be
misleading as they often just put all stuff in arch/arm/mach-something.

> - this code should also declare the tda998x

The device for tda998x yes, but not the driver. Anyway, Russel decided
to have tda998x probed by his drm_driver.

> - the drm driver contains/passes parameters to the tda998x
>
> As the connection Dove LCD<->  tda998x is Cubox specific, the question
> is: why are'nt the tda998x parameters in the cubox-setup code?

The connection of Dove LCD and tda998x is _not_ Cubox specific, it is
also on the D2Plug. To be precise, even "Dove LCD" is not Dove specific
as you can find the very same controller on other Marvell SoCs with
little differences.

So in the end, we will have a DT node for the HW controllers found
in Dove SoCs, a node for TDA998x, and a node for the video card, i.e.
_how_ lcd controllers, external encoders, clocks, maybe audio, ...
are hooked up on that specific board.

There is so much to take care of like pixel format on lcd pins driving
an external encoder (_not_ only tda998x), what gpio pin is connected to
TDA interrupt line, one or two lcds, ...

The corresponding drivers _will_ take care of it .. but in the future.
All I try to make sure is that driver architecture does not prevent us
from e.g. having two lcds plus dcon later on. Or allows to reuse
dove-drm on pxa where only one lcd but no dcon is available.

Sebastian


From robherring2 at gmail.com  Sat May 18 15:51:04 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Sat, 18 May 2013 14:51:04 -0500
Subject: spurious bL cpufreq driver messages
In-Reply-To: <CAKohpom0cGfWvsCf-jaMyu0cQJi2hVk9_0wskEDH2X7MaeHDLw@mail.gmail.com>
References: <519686BC.3090101@gmail.com>
 <CAKohpom0cGfWvsCf-jaMyu0cQJi2hVk9_0wskEDH2X7MaeHDLw@mail.gmail.com>
Message-ID: <CAL_JsqLEv38DwnL4=ToXtEKNrDbgYv_0qiOc+cXZSjnfKVbeNg@mail.gmail.com>

On Fri, May 17, 2013 at 9:03 PM, Viresh Kumar <viresh.kumar at linaro.org> wrote:
> On 18 May 2013 01:06, Rob Herring <robherring2 at gmail.com> wrote:
>> The bL cpufreq driver appears to collide with the cpufreq-cpu0 driver.
>> There doesn't appear to be a functional problem, but just spurious
>> prints which indicate it is trying to do something. I think it needs
>> better checking whether the chip is actually multi-cluster. This is what
>> I get when I hotplug cpus:
>>
>> [  909.372319] CPU1: Booted secondary processor
>> [  909.372616] cpu cpu1: get_cluster_clk_and_freq_table: init_opp_table
>> failed, cpu: 1, err: -61
>> [  909.385411] cpu cpu1: get_cluster_clk_and_freq_table: Failed to get
>> data for cluster: 9
>> [  909.394161] CPU2: shutdown
>> [  909.400957] CPU2: Booted secondary processor
>> [  909.401253] cpu cpu2: get_cluster_clk_and_freq_table: init_opp_table
>> failed, cpu: 2, err: -61
>> [  909.414044] cpu cpu2: get_cluster_clk_and_freq_table: Failed to get
>> data for cluster: 9
>
> See if this fixes your issue.
>
> https://groups.google.com/forum/?fromgroups#!topic/linux.kernel/XJF-82rad4o
>
> Attached too.

No, it still registers the bL driver. The problem is not that DT data
is missing, but it is present on a single cluster system. This is what
my 1st cpu node looks like:

$ ls /proc/device-tree/cpus/cpu at 900/
clock-latency  clocks      device_type  next-level-cache  reg
clock-names    compatible  name         operating-points  transition-latency

This is the boot log:

[    1.192186] cpu cpu0: get_cluster_clk_and_freq_table: Failed to get
clk for cpu: 0, cluster: 9
[    1.200804] cpu cpu0: get_cluster_clk_and_freq_table: Failed to get
data for cluster: 9
[    1.208815] cpu cpu1: get_cluster_clk_and_freq_table:
init_opp_table failed, cpu: 1, err: -61
[    1.217345] cpu cpu1: get_cluster_clk_and_freq_table: Failed to get
data for cluster: 9
[    1.225354] cpu cpu2: get_cluster_clk_and_freq_table:
init_opp_table failed, cpu: 2, err: -61
[    1.233879] cpu cpu2: get_cluster_clk_and_freq_table: Failed to get
data for cluster: 9
[    1.241880] cpu cpu3: get_cluster_clk_and_freq_table:
init_opp_table failed, cpu: 3, err: -61
[    1.250403] cpu cpu3: get_cluster_clk_and_freq_table: Failed to get
data for cluster: 9
[    1.258406] arm_big_little: bL_cpufreq_register: Registered
platform driver: dt-bl
[    1.266123] cpufreq_cpu0: failed to get cpu0 regulator: -19
[    1.271704] cpufreq_cpu0: failed register driver: -16
[    1.276764] cpufreq-cpu0: probe of cpufreq-cpu0.0 failed with error -16

Rob


From linux at prisktech.co.nz  Sat May 18 15:51:38 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sun, 19 May 2013 07:51:38 +1200
Subject: [PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.
In-Reply-To: <CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
 <1368868514-18975-5-git-send-email-linux@prisktech.co.nz>
 <CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com>
Message-ID: <5197DBCA.8050708@prisktech.co.nz>

On 19/05/13 01:28, Alexey Charkov wrote:
> 2013/5/18 Tony Prisk <linux at prisktech.co.nz>:
>> The APC8750 does not support an LCD panel, but provides a VGA connector.
>> This patch adds support for the VGA interface, and defines an optional
>> devicetree property to specify the output interface. The default if not
>> specified is LCD for backward compatibility.
>>
>> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
>> ---
>>   .../devicetree/bindings/video/wm,wm8505-fb.txt     |    5 ++++
>>   drivers/video/wm8505fb.c                           |   31 ++++++++++++++++++--
>>   2 files changed, 34 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
>> index 601416c..9f1d648 100644
>> --- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
>> +++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
>> @@ -7,6 +7,10 @@ Required properties:
>>   - bits-per-pixel : bit depth of framebuffer (16 or 32)
>>   - clocks : phandle to DVO clock
>>
>> +Optional properties:
>> +- output-interface : the interface the fb should output on. Valid values are
>> +       "lcd" or "vga". If not specified, the default is "lcd".
>> +
>>   Required subnodes:
>>   - display-timings: see display-timing.txt for information
>>
>> @@ -17,6 +21,7 @@ Example:
>>                  reg = <0xd8051700 0x200>;
>>                  bits-per-pixel = <16>;
>>                  clocks = <&clkdvo>;
>> +               output-interface = "vga";
>>
>>                  display-timings {
>>                          native-mode = <&timing0>;
>> diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
>> index f8bffc2..d1f7f33 100644
>> --- a/drivers/video/wm8505fb.c
>> +++ b/drivers/video/wm8505fb.c
>> @@ -130,12 +130,17 @@
>>
>>   #define to_wm8505fb_info(__info) container_of(__info, \
>>                                                  struct wm8505fb_info, fb)
>> +
>> +#define INTERFACE_LCD  1
>> +#define INTERFACE_VGA  2
>> +
>>   struct wm8505fb_info {
>>          struct fb_info fb;
>>          void __iomem *regbase;
>>          unsigned int contrast;
>>          struct device *dev;
>>          struct clk *clk_dvo;
>> +       int interface;
>>   };
>>
>>
>> @@ -158,7 +163,11 @@ static int wm8505fb_init_hw(struct fb_info *info)
>>           * 0x31C sets the correct color mode (RGB565) for WM8650
>>           * Bit 8+9 (0x300) are ignored on WM8505 as reserved
>>           */
>> -       writel(0x31c,                  fbi->regbase + REG_GOVRH_YUVRGB);
>> +       if (fbi->interface == INTERFACE_VGA)
>> +               writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB);
>> +       else
>> +               writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);
>> +
>>          writel(1,                      fbi->regbase + REG_GOVRH_DVO_PIX);
> Tony,
>
> Would it be possible to also define known bit offsets for those
> registers, while you are at this? It would probably reduce the black
> magic quite a bit :)
On my list of things to do :)
>>          /* Virtual buffer size */
>> @@ -167,7 +176,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
>>
>>          /* black magic ;) */
>>          writel(0xf,                    fbi->regbase + REG_GOVRH_FHI);
>> -       writel(4,                      fbi->regbase + REG_GOVRH_DVO_SET);
>> +
>> +       if (fbi->interface == INTERFACE_VGA)
>> +               writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET);
>> +       else
>> +               writel(4, fbi->regbase + REG_GOVRH_DVO_SET);
> I don't remember if HDMI is yet another option for this register or
> not... If it is, it would probably warrant defining fbi->interface as
> an enum and changing this if-else into a switch statement to let the
> compiler add its checks/warnings.
This register defines the h/v syncpolarity and enable/disable for DVO.
>
>>          writel(1,                      fbi->regbase + REG_GOVRH_MIF);
>>          writel(1,                      fbi->regbase + REG_GOVRH_REG_STS);
>>
>> @@ -194,11 +208,15 @@ static int wm8505fb_set_timing(struct fb_info *info)
>>          writel(h_end,   fbi->regbase + REG_GOVRH_ACTPX_END);
>>          writel(h_all,   fbi->regbase + REG_GOVRH_H_ALLPXL);
>>          writel(h_sync,  fbi->regbase + REG_GOVRH_HDMI_HSYNW);
>> +       if (fbi->interface == INTERFACE_VGA)
>> +               writel(h_sync,  fbi->regbase + REG_GOVRH_VGA_HSYNW);
> Will it misbehave on LCD if you write to the VGA register unconditionally?
Don't know - wouldn't imagine so. I will test it and see.
>
>>          writel(v_start, fbi->regbase + REG_GOVRH_ACTLN_BG);
>>          writel(v_end,   fbi->regbase + REG_GOVRH_ACTLN_END);
>>          writel(v_all,   fbi->regbase + REG_GOVRH_V_ALLLN);
>>          writel(v_sync,  fbi->regbase + REG_GOVRH_HDMI_VBISW);
>> +       if (fbi->interface == INTERFACE_VGA)
>> +               writel(info->var.pixclock,  fbi->regbase + REG_GOVRH_VGA_VSYNW);
> Same here. I would assume that setting the pixclock should not hurt
> LCD, which would then simplify the code a little.
>
> Thanks,
> Alexey
Regards
Tony Prisk


From w at 1wt.eu  Sat May 18 15:52:23 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Sat, 18 May 2013 21:52:23 +0200
Subject: [PATCH] arm: mvebu: enable the third USB interface on OpenBlocks
 AX3
In-Reply-To: <519634F9.7060700@free-electrons.com>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
 <519634F9.7060700@free-electrons.com>
Message-ID: <20130518195223.GG1936@1wt.eu>

Hi Gregory,

On Fri, May 17, 2013 at 03:47:37PM +0200, Gregory CLEMENT wrote:
> I applied and tested on my OpenBlocks AX3 and get the 3rd USB
> interface detected. As I don't have any mini-PCIe card which use USB,
> I didn't tested it furthermore, but as Atsushi Yamagata managed to
> detect an USB device on this interface, we can be pretty confident
> with this patch:

I do have a mini-PCIe to PCIe+USB adapter [1]. I have plugged it
with a USB flash and it was correctly detected as well after I
applied the patch :

usb 3-1: new high-speed USB device number 2 using orion-ehci
usb 3-1: New USB device found, idVendor=0781, idProduct=5567
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 3-1: Product: Cruzer Blade
usb 3-1: Manufacturer: SanDisk

Best regards,
Willy

[1] : http://www.hwtools.net/Adapter/PM2.html



From linux at arm.linux.org.uk  Sat May 18 16:26:04 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 18 May 2013 21:26:04 +0100
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <5197D6C1.3060702@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf> <5197D6C1.3060702@gmail.com>
Message-ID: <20130518202604.GM18614@n2100.arm.linux.org.uk>

On Sat, May 18, 2013 at 09:30:09PM +0200, Sebastian Hesselbarth wrote:
> The device for tda998x yes, but not the driver. Anyway, Russel decided
> to have tda998x probed by his drm_driver.

For the simple reason that _that_ is how DRM slave encoders work.
Sometimes, reading the code of the subsystem you're using is well
worth the effort.

If Jean-Francois would like to read drm_encoder_slave.c, then it will
be found that in order to use the TDA998x driver, which is itself a
DRM slave encoder, you must use drm_i2c_encoder_init().  In order to
use that, you must provide the I2C adapter structure, and a board
info structure.

If you don't want to do that, your options are:
(a) you don't use the existing TDA998x DRM slave encoder, and instead
    write your own TDA998x driver, which will likely be justifyable
    rejected, or
(b) you propose a new DRM interface to allow DRM components to be
    registered independently, without reference to a core drm_device
    structure.

> The connection of Dove LCD and tda998x is _not_ Cubox specific, it is
> also on the D2Plug. To be precise, even "Dove LCD" is not Dove specific
> as you can find the very same controller on other Marvell SoCs with
> little differences.

Well, to spoil the argument a little, actually, the interconnection
between the two is in no way "standardized".  There's many different
ways to wire the two chips together and have it work - because the
TDA998x chips have a set of input muxes and swaps which allow you to
connect the red, green, blue high/low nibbles in various ways and
still have a correctly working system.  The TDA998x connectivity is
_highly_ configuable.

So, just because one board connects LCD_D0 (red bit 0) to a particular
pin on the TDA998x does not mean that another board does it that way
too.

So Jean-Francois is quite correct that this data needs to be provided
by the board in some manner.  The question is - how to do that sensibly.

One possible stop-gap solution is to provide a default set which just
happens to match the cubox, and allow OF to override it. :)

> There is so much to take care of like pixel format on lcd pins driving
> an external encoder (_not_ only tda998x), what gpio pin is connected to
> TDA interrupt line, one or two lcds, ...

Luckily, drivers/gpu/drm/i2c/tda998x.c does not make use of the IRQ
signal at present - it's fairly basic and it currently operates by
polling.  Eventually, this could change of course. :)

I think people need to keep a sense of perspective here: this is all
entirely "new" stuff which is still being actively developed.  It is
not fully polished.  We've not had a true open source TDA998x driver
before 3.9 (that's when it was introduced.)  It has teething problems
at the moment, but I'm working with the authors to resolve these issues.
I'm also still working on the DRM driver.

For example, I've been playing with the RGB888 cursor support today,
which seems to be suffering from a one pixel error in the hotspot
location.  I've not got to the bottom of it, but that kind of error
_is_ important to understand and resolve, because it means that
things like drawing programmes become unusable.

What I'm starting to suspect is a bug in the X server causing this
and not either my DRM driver or Xorg driver.


From linux at arm.linux.org.uk  Sat May 18 16:46:56 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 18 May 2013 21:46:56 +0100
Subject: [RFC 3/4] DRM: add OF support for Dove DRM driver
In-Reply-To: <20130518194502.102caa9e@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194502.102caa9e@armhf>
Message-ID: <20130518204655.GN18614@n2100.arm.linux.org.uk>

On Sat, May 18, 2013 at 07:45:02PM +0200, Jean-Francois Moine wrote:
> It seems we are moving backwards:
> - what about the display controller?
> - how do you clone the lcd 0 output to the port B?
> - what occurs when the si5351 and the tda998x are modules?

I've no idea why you keep bringing that last point up.  I've already
told you what happens when the SI5351 is a module.  It is already not
a problem as I have already evidenced by my boot log.  So please get
that and stop repeating this same point which I've already answered,
or I will start ranting at you and we will have a massive falling out.

As for cloning output to the VGA port, that's just a matter of dealing
with the display controller.  That's _not_ difficult.

> My driver had the same layout as Russell's when I proposed it to you
> and when you insisted to handle the 2 LCDs and the 2 ports as one card.

This seems to be a misrepresentation.  So what you're saying is that
your driver originally handled the two LCDs as two separate cards.

That is _not_ the same as my driver.  My driver handles the two LCDs
as two separate CRTs of the same DRM device.  This allows X to drive
the two CRTs together in any manner it desires depending on the
capabilities of the "connectors" associated with each CRTC and the
user preferences.

> I spent 2 months to have a nice design and you put it to garbage!
> I am not happy...

Stop that right now.  If you want to start whinging about the amount of
time you've spent on this, then I can tell you now that if you have only
spent two months on this, you are a total newbie to this and your effort
is utterly insignificant compared to mine.  And you *have* touched a
nerve here by making that statement.


From sebastian.hesselbarth at gmail.com  Sat May 18 16:50:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 18 May 2013 22:50:40 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <20130518202604.GM18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf> <5197D6C1.3060702@gmail.com>
 <20130518202604.GM18614@n2100.arm.linux.org.uk>
Message-ID: <5197E9A0.1020607@gmail.com>

On 05/18/2013 10:26 PM, Russell King - ARM Linux wrote:
> On Sat, May 18, 2013 at 09:30:09PM +0200, Sebastian Hesselbarth wrote:
>> The device for tda998x yes, but not the driver. Anyway, Russel decided
>> to have tda998x probed by his drm_driver.
>
> For the simple reason that _that_ is how DRM slave encoders work.
> Sometimes, reading the code of the subsystem you're using is well
> worth the effort.

I agree and add that the probing itself doesn't prevent you from using
DT for tda driver at all. You can still have an marvell,external-slave
property pointing to the phandle of tda node. With that you get the
adapter and i2c slave address for what is currently called
dove_tda19989.c and may become e.g. dove_ext_i2c.c. In tda998x_drv you
find the node and get all properties for input config or interrupt
gpio.

I have done that in the drivers before, but DT node parsing here is
_added_ to the driver as it can be used on other non-DT platforms as
well.

>> The connection of Dove LCD and tda998x is _not_ Cubox specific, it is
>> also on the D2Plug. To be precise, even "Dove LCD" is not Dove specific
>> as you can find the very same controller on other Marvell SoCs with
>> little differences.
>
> Well, to spoil the argument a little, actually, the interconnection
> between the two is in no way "standardized".  There's many different
> ways to wire the two chips together and have it work - because the
> TDA998x chips have a set of input muxes and swaps which allow you to
> connect the red, green, blue high/low nibbles in various ways and
> still have a correctly working system.  The TDA998x connectivity is
> _highly_ configuable.
>
> So, just because one board connects LCD_D0 (red bit 0) to a particular
> pin on the TDA998x does not mean that another board does it that way
> too.
>
> So Jean-Francois is quite correct that this data needs to be provided
> by the board in some manner.  The question is - how to do that sensibly.
>
> One possible stop-gap solution is to provide a default set which just
> happens to match the cubox, and allow OF to override it. :)

While I agree, Rob may have a different view on that for tda998x ;)

>> There is so much to take care of like pixel format on lcd pins driving
>> an external encoder (_not_ only tda998x), what gpio pin is connected to
>> TDA interrupt line, one or two lcds, ...
>
> Luckily, drivers/gpu/drm/i2c/tda998x.c does not make use of the IRQ
> signal at present - it's fairly basic and it currently operates by
> polling.  Eventually, this could change of course. :)

Again, that is in the driver Jean-Francois has available. Make sure irq
handler runs in a separate thread from get_edid and hpd and you will
be interrupted on hpd. Having said, that should finally lead to the
slave encoder setting .connector_type and .polled as this is where you
know it.

Sebastian


From linus.walleij at linaro.org  Sat May 18 18:13:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 19 May 2013 00:13:04 +0200
Subject: [PATCH] ARM: nomadik: add led and key for S8815
Message-ID: <1368915184-29657-1-git-send-email-linus.walleij@linaro.org>

This adds device tree hunks for the LED and userbutton on the
USB S8815 board, and set up a heartbeat trigger on the LED and
an escape key on the user button. Alter the defconfig to enable
these standard DT-enabled GPIO drivers.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-nomadik-s8815.dts | 22 ++++++++++++++++++++++
 arch/arm/configs/nhk8815_defconfig      |  6 ++++++
 arch/arm/mach-nomadik/cpu-8815.c        |  4 ++++
 3 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index b28fbf3..666945a 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -27,4 +27,26 @@
 			gpios = <&gpio3 16 0x1>;
 		};
 	};
+
+	/* The user LED on the board is set up to be used for heartbeat */
+	leds {
+		compatible = "gpio-leds";
+		user-led {
+			label = "user_led";
+			gpios = <&gpio0 2 0x1>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	/* User key mapped in as "escape" */
+	gpio-keys {
+		compatible = "gpio-keys";
+		user-button {
+			label = "user_button";
+			gpios = <&gpio0 3 0x1>;
+			linux,code = <1>; /* KEY_ESC */
+			gpio-key,wakeup;
+		};
+	};
 };
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index b01e763..35f8cf2 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -81,6 +81,7 @@ CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -96,6 +97,11 @@ CONFIG_DEBUG_GPIO=y
 CONFIG_MMC=y
 CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..1e0ec38 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -99,6 +99,10 @@ static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
 static struct pinctrl_map __initdata nhk8815_pinmap[] = {
 	PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
+	/* User LED on S8815 */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO2_C5", out_high),
+	/* User button on S8815 */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO3_A4", in_nopull),
 	/* Hog in MMC/SD card mux */
 	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
 	/* MCCLK */
-- 
1.8.1.4



From tomasz.figa at gmail.com  Sat May 18 18:31:21 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:31:21 +0200
Subject: [PATCH] ARM: s5p64x0: Use common uncompress.h part for plat-samsung
Message-ID: <1368916282-22896-1-git-send-email-tomasz.figa@gmail.com>

Since uart_base can be set dynamically in arch_detect_cpu(), there is no
need to have a copy of all code locally, just to override UART base
address.

This patch removes any duplicate code in uncompress.h variant of s5p64x0
and implements proper arch_detect_cpu() function to initialize UART with
SoC-specific parameters.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 arch/arm/mach-s5p64x0/include/mach/uncompress.h | 155 +-----------------------
 1 file changed, 5 insertions(+), 150 deletions(-)

diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 19e0d64..b383b81 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -15,37 +15,11 @@
 
 #include <mach/map.h>
 
-/*
- * cannot use commonly <plat/uncompress.h>
- * because uart base of S5P6440 and S5P6450 is different
- */
-
-typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-unsigned int fifo_mask;
-unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX	 (14)
-
 unsigned long uart_base;
 
-static __inline__ void get_uart_base(void)
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
 {
 	unsigned int chipid;
 
@@ -57,128 +31,9 @@ static __inline__ void get_uart_base(void)
 		uart_base += 0xEC800000;
 	else
 		uart_base += 0xEC000000;
-}
-
-static __inline__ void uart_wr(unsigned int reg, unsigned int val)
-{
-	volatile unsigned int *ptr;
 
-	get_uart_base();
-	ptr = (volatile unsigned int *)(reg + uart_base);
-	*ptr = val;
-}
-
-static __inline__ unsigned int uart_rd(unsigned int reg)
-{
-	volatile unsigned int *ptr;
-
-	get_uart_base();
-	ptr = (volatile unsigned int *)(reg + uart_base);
-	return *ptr;
-}
-
-/*
- * we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
- */
-
-static void putc(int ch)
-{
-	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-		int level;
-
-		while (1) {
-			level = uart_rd(S3C2410_UFSTAT);
-			level &= fifo_mask;
-
-			if (level < fifo_max)
-				break;
-		}
-
-	} else {
-		/* not using fifos */
-
-		while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-			barrier();
-	}
-
-	/* write byte to transmission register */
-	uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d, ad)			\
-	do {							\
-		*((volatile unsigned int __force *)(ad)) = (d); \
-	} while (0)
-
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-	putstr("\n\n");
-	putstr(x);
-	putstr("\n\n -- System resetting\n");
-
-	__raw_writel(0x4000, S3C2410_WTDAT);
-	__raw_writel(0x4000, S3C2410_WTCNT);
-	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-	while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-	u32 fifocon = uart_rd(S3C2410_UFCON);
-
-	if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
-		fifocon |= S3C2410_UFCON_RESETBOTH;
-		uart_wr(S3C2410_UFCON, fifocon);
-
-		/* wait for fifo reset to complete */
-		while (1) {
-			fifocon = uart_rd(S3C2410_UFCON);
-			if (!(fifocon & S3C2410_UFCON_RESETBOTH))
-				break;
-		}
-	}
-}
-#else
-#define arch_enable_uart_fifo() do { } while(0)
-#endif
-
-static void arch_decomp_setup(void)
-{
-	/*
-	 * we may need to setup the uart(s) here if we are not running
-	 * on an BAST... the BAST will have left the uarts configured
-	 * after calling linux.
-	 */
-
-	arch_detect_cpu();
-
-	/*
-	 * Enable the UART FIFOs if they where not enabled and our
-	 * configuration says we should turn them on.
-	 */
-
-	arch_enable_uart_fifo();
-}
-
-
-
-static void arch_detect_cpu(void)
-{
-	/* we do not need to do any cpu detection here at the moment. */
+	fifo_mask = S3C2440_UFSTAT_TXMASK;
+	fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:01 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:01 +0200
Subject: [PATCH 0/6] Samsung watchdog support clean-up
Message-ID: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>

This series is aiming at cleaning up a bit watchdog support on Samsung
SoCs. The patches tweak a bit all the watchdog handling code here and
there, with the goal of making it DT- and multiplatform-friendly.

See particular patches for more detailed descriptions.

On S3C6410-based Tiny6410 board (Mini6410-compatible):

Tested-by: Tomasz Figa <tomasz.figa at gmail.com>

Depends on:
 - [PATCH] ARM: s5p64x0: Use common uncompress.h part for plat-samsung

Tomasz Figa (6):
  watchdog: s3c2410_wdt: Use local register definitions
  ARM: SAMSUNG: uncompress: Use local definitions of watchdog registers
  ARM: SAMSUNG: Add watchdog reset driver
  ARM: SAMSUNG: Let platforms use the new watchdog reset driver
  ARM: SAMSUNG: Remove legacy watchdog reset code
  ARM: SAMSUNG: Remove unused plat/regs-watchdog.h header

 arch/arm/Kconfig                                   |  3 +
 arch/arm/mach-s3c24xx/Kconfig                      |  2 +
 arch/arm/mach-s3c24xx/s3c2410.c                    |  3 +-
 arch/arm/mach-s3c24xx/s3c244x.c                    |  3 +-
 arch/arm/mach-s3c64xx/common.c                     |  8 +-
 arch/arm/mach-s5p64x0/common.c                     |  4 +-
 arch/arm/mach-s5pc100/common.c                     |  3 +-
 arch/arm/plat-samsung/Kconfig                      |  6 ++
 arch/arm/plat-samsung/Makefile                     |  1 +
 arch/arm/plat-samsung/include/plat/regs-watchdog.h | 41 ---------
 arch/arm/plat-samsung/include/plat/uncompress.h    | 15 +++-
 .../arm/plat-samsung/include/plat/watchdog-reset.h | 38 ++-------
 arch/arm/plat-samsung/watchdog-reset.c             | 97 ++++++++++++++++++++++
 drivers/watchdog/s3c2410_wdt.c                     | 17 +++-
 14 files changed, 156 insertions(+), 85 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-watchdog.h
 create mode 100644 arch/arm/plat-samsung/watchdog-reset.c

-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:02 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:02 +0200
Subject: [PATCH 1/6] watchdog: s3c2410_wdt: Use local register definitions
In-Reply-To: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <1368916627-23139-2-git-send-email-tomasz.figa@gmail.com>

This patch moves register and bitfield definitions to the driver itself,
removing remaining dependencies on plat/ and mach/ headers.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 drivers/watchdog/s3c2410_wdt.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index ee03135..3a9f696 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -42,12 +42,21 @@
 #include <linux/err.h>
 #include <linux/of.h>
 
-#include <mach/map.h>
+#define S3C2410_WTCON		0x00
+#define S3C2410_WTDAT		0x04
+#define S3C2410_WTCNT		0x08
 
-#undef S3C_VA_WATCHDOG
-#define S3C_VA_WATCHDOG (0)
+#define S3C2410_WTCON_RSTEN	(1 << 0)
+#define S3C2410_WTCON_INTEN	(1 << 2)
+#define S3C2410_WTCON_ENABLE	(1 << 5)
 
-#include <plat/regs-watchdog.h>
+#define S3C2410_WTCON_DIV16	(0 << 3)
+#define S3C2410_WTCON_DIV32	(1 << 3)
+#define S3C2410_WTCON_DIV64	(2 << 3)
+#define S3C2410_WTCON_DIV128	(3 << 3)
+
+#define S3C2410_WTCON_PRESCALE(x)	((x) << 8)
+#define S3C2410_WTCON_PRESCALE_MASK	(0xff << 8)
 
 #define CONFIG_S3C2410_WATCHDOG_ATBOOT		(0)
 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME	(15)
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:04 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:04 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: Add watchdog reset driver
In-Reply-To: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <1368916627-23139-4-git-send-email-tomasz.figa@gmail.com>

This patch adds a watchdog reset driver that can be used on Samsung SoCs
that do not provide dedicated reset method. It replaces the legacy
helper function that relies on static IO mapping.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 arch/arm/plat-samsung/Kconfig                      |  6 ++
 arch/arm/plat-samsung/Makefile                     |  1 +
 .../arm/plat-samsung/include/plat/watchdog-reset.h |  9 ++
 arch/arm/plat-samsung/watchdog-reset.c             | 97 ++++++++++++++++++++++
 4 files changed, 113 insertions(+)
 create mode 100644 arch/arm/plat-samsung/watchdog-reset.c

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de..ec68155 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -475,6 +475,12 @@ config SAMSUNG_WAKEMASK
 	  and above. This code allows a set of interrupt to wakeup-mask
 	  mappings. See <plat/wakeup-mask.h>
 
+config SAMSUNG_WDT_RESET
+	bool
+	help
+	  Compile support for system restart by triggering watchdog reset.
+	  Used on SoCs that do not provide dedicated reset control.
+
 config S5P_PM
 	bool
 	help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460..03cea14 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_PM)		+= pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)	+= pm-check.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK)	+= wakeup-mask.o
+obj-$(CONFIG_SAMSUNG_WDT_RESET)	+= watchdog-reset.o
 
 obj-$(CONFIG_S5P_PM)		+= s5p-pm.o s5p-irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)		+= s5p-sleep.o
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index bc4db9b..4def1b2 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,6 +10,9 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __PLAT_WATCHDOG_RESET_H
+#define __PLAT_WATCHDOG_RESET_H
+
 #include <plat/clock.h>
 #include <plat/regs-watchdog.h>
 #include <mach/map.h>
@@ -44,3 +47,9 @@ static inline void arch_wdt_reset(void)
 	/* delay to allow the serial port to show the message */
 	mdelay(50);
 }
+
+extern void samsung_wdt_reset(void);
+extern void samsung_wdt_reset_of_init(void);
+extern void samsung_wdt_reset_init(void __iomem *base);
+
+#endif /* __PLAT_WATCHDOG_RESET_H */
diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c
new file mode 100644
index 0000000..2ecb50be
--- /dev/null
+++ b/arch/arm/plat-samsung/watchdog-reset.c
@@ -0,0 +1,97 @@
+/* arch/arm/plat-samsung/watchdog-reset.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *	Ben Dooks <ben at simtec.co.uk>
+ *
+ * Coyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
+ *
+ * Watchdog reset support for Samsung SoCs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define S3C2410_WTCON			0x00
+#define S3C2410_WTDAT			0x04
+#define S3C2410_WTCNT			0x08
+
+#define S3C2410_WTCON_ENABLE		(1 << 5)
+#define S3C2410_WTCON_DIV16		(0 << 3)
+#define S3C2410_WTCON_RSTEN		(1 << 0)
+#define S3C2410_WTCON_PRESCALE(x)	((x) << 8)
+
+static void __iomem *wdt_base;
+static struct clk *wdt_clock;
+
+void samsung_wdt_reset(void)
+{
+	if (!wdt_base) {
+		pr_err("%s: wdt reset not initialized\n", __func__);
+		/* delay to allow the serial port to show the message */
+		mdelay(50);
+		return;
+	}
+
+	if (!IS_ERR(wdt_clock))
+		clk_prepare_enable(wdt_clock);
+
+	/* disable watchdog, to be safe  */
+	__raw_writel(0, wdt_base + S3C2410_WTCON);
+
+	/* put initial values into count and data */
+	__raw_writel(0x80, wdt_base + S3C2410_WTCNT);
+	__raw_writel(0x80, wdt_base + S3C2410_WTDAT);
+
+	/* set the watchdog to go and reset... */
+	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
+			S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
+			wdt_base + S3C2410_WTCON);
+
+	/* wait for reset to assert... */
+	mdelay(500);
+
+	pr_err("Watchdog reset failed to assert reset\n");
+
+	/* delay to allow the serial port to show the message */
+	mdelay(50);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id s3c2410_wdt_match[] = {
+	{ .compatible = "samsung,s3c2410-wdt" },
+	{},
+};
+
+void __init samsung_wdt_reset_of_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, s3c2410_wdt_match);
+	if (!np) {
+		pr_err("%s: failed to find watchdog node\n", __func__);
+		return;
+	}
+
+	wdt_base = of_iomap(np, 0);
+	if (!wdt_base) {
+		pr_err("%s: failed to map watchdog registers\n", __func__);
+		return;
+	}
+
+	wdt_clock = of_clk_get(np, 0);
+}
+#endif
+
+void __init samsung_wdt_reset_init(void __iomem *base)
+{
+	wdt_base = base;
+	wdt_clock = clk_get(NULL, "watchdog");
+}
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:03 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:03 +0200
Subject: [PATCH 2/6] ARM: SAMSUNG: uncompress: Use local definitions of
 watchdog registers
In-Reply-To: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <1368916627-23139-3-git-send-email-tomasz.figa@gmail.com>

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 arch/arm/plat-samsung/include/plat/uncompress.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 438b248..e8954b8 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -28,11 +28,20 @@ static void arch_detect_cpu(void);
 /* defines for UART registers */
 
 #include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
 
 /* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+#define S3C_WDOGREG(x)	((S3C_PA_WDT + (x)))
+
+#define S3C2410_WTCON	S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT	S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT	S3C_WDOGREG(0x08)
+
+#define S3C2410_WTCON_RSTEN	(1 << 0)
+#define S3C2410_WTCON_ENABLE	(1 << 5)
+
+#define S3C2410_WTCON_DIV128	(3 << 3)
+
+#define S3C2410_WTCON_PRESCALE(x)	((x) << 8)
 
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:05 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:05 +0200
Subject: [PATCH 4/6] ARM: SAMSUNG: Let platforms use the new watchdog reset
 driver
In-Reply-To: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <1368916627-23139-5-git-send-email-tomasz.figa@gmail.com>

This patch moves all platforms using the legacy watchdog reset helper
function to the new watchdog reset driver.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 arch/arm/Kconfig                | 3 +++
 arch/arm/mach-s3c24xx/Kconfig   | 2 ++
 arch/arm/mach-s3c24xx/s3c2410.c | 3 ++-
 arch/arm/mach-s3c24xx/s3c244x.c | 3 ++-
 arch/arm/mach-s3c64xx/common.c  | 8 +++++++-
 arch/arm/mach-s5p64x0/common.c  | 4 +++-
 arch/arm/mach-s5pc100/common.c  | 3 ++-
 7 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7b7ab65..676df53 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -731,6 +731,7 @@ config ARCH_S3C64XX
 	select SAMSUNG_CLKSRC
 	select SAMSUNG_GPIOLIB_4BIT
 	select SAMSUNG_IRQ_VIC_TIMER
+	select SAMSUNG_WDT_RESET
 	select USB_ARCH_HAS_OHCI
 	help
 	  Samsung S3C64XX series based systems
@@ -746,6 +747,7 @@ config ARCH_S5P64X0
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 	select HAVE_S3C_RTC if RTC_CLASS
 	select NEED_MACH_GPIO_H
+	select SAMSUNG_WDT_RESET
 	help
 	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 	  SMDK6450.
@@ -762,6 +764,7 @@ config ARCH_S5PC100
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 	select HAVE_S3C_RTC if RTC_CLASS
 	select NEED_MACH_GPIO_H
+	select SAMSUNG_WDT_RESET
 	help
 	  Samsung S5PC100 series based systems
 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index f2f7088..f8d1912 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -31,6 +31,7 @@ config CPU_S3C2410
 	select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
 	select S3C2410_PM if PM
 	select SAMSUNG_HRT
+	select SAMSUNG_WDT_RESET
 	help
 	  Support for S3C2410 and S3C2410A family from the S3C24XX line
 	  of Samsung Mobile CPUs.
@@ -81,6 +82,7 @@ config CPU_S3C2442
 config CPU_S3C244X
 	def_bool y
 	depends on CPU_S3C2440 || CPU_S3C2442
+	select SAMSUNG_WDT_RESET
 
 config CPU_S3C2443
 	bool "SAMSUNG S3C2443"
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5..ff384ac 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -138,6 +138,7 @@ void __init s3c2410_init_clocks(int xtal)
 	s3c2410_baseclk_add();
 	s3c24xx_register_clock(&s3c2410_armclk);
 	clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
+	samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 
 struct bus_type s3c2410_subsys = {
@@ -201,7 +202,7 @@ void s3c2410_restart(char mode, const char *cmd)
 		soft_restart(0);
 	}
 
-	arch_wdt_reset();
+	samsung_wdt_reset();
 
 	/* we'll take a jump through zero as a poor second */
 	soft_restart(0);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb..d0423e2 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -133,6 +133,7 @@ void __init s3c244x_init_clocks(int xtal)
 	s3c24xx_register_baseclocks(xtal);
 	s3c244x_setup_clocks();
 	s3c2410_baseclk_add();
+	samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 
 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
@@ -202,7 +203,7 @@ void s3c244x_restart(char mode, const char *cmd)
 	if (mode == 's')
 		soft_restart(0);
 
-	arch_wdt_reset();
+	samsung_wdt_reset();
 
 	/* we'll take a jump through zero as a poor second */
 	soft_restart(0);
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba..1aed6f4 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -183,6 +183,12 @@ core_initcall(s3c64xx_dev_init);
 
 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
+	/*
+	 * FIXME: there is no better place to put this at the moment
+	 * (samsung_wdt_reset_init needs clocks)
+	 */
+	samsung_wdt_reset_init(S3C_VA_WATCHDOG);
+
 	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
 	/* initialise the pair of VICs */
@@ -378,7 +384,7 @@ arch_initcall(s3c64xx_init_irq_eint);
 void s3c64xx_restart(char mode, const char *cmd)
 {
 	if (mode != 's')
-		arch_wdt_reset();
+		samsung_wdt_reset();
 
 	/* if all else fails, or mode was for soft, jump to 0 */
 	soft_restart(0);
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800..76d0053 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -173,6 +173,8 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
 	s5p_init_cpu(S5P64X0_SYS_ID);
 
 	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+	samsung_wdt_reset_init(S3C_VA_WATCHDOG);
+
 }
 
 void __init s5p6440_map_io(void)
@@ -440,7 +442,7 @@ arch_initcall(s5p64x0_init_irq_eint);
 void s5p64x0_restart(char mode, const char *cmd)
 {
 	if (mode != 's')
-		arch_wdt_reset();
+		samsung_wdt_reset();
 
 	soft_restart(0);
 }
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561..5110315 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -178,6 +178,7 @@ void __init s5pc100_init_clocks(int xtal)
 	s5p_register_clocks(xtal);
 	s5pc100_register_clocks();
 	s5pc100_setup_clocks();
+	samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 }
 
 void __init s5pc100_init_irq(void)
@@ -219,7 +220,7 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 void s5pc100_restart(char mode, const char *cmd)
 {
 	if (mode != 's')
-		arch_wdt_reset();
+		samsung_wdt_reset();
 
 	soft_restart(0);
 }
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:06 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:06 +0200
Subject: [PATCH 5/6] ARM: SAMSUNG: Remove legacy watchdog reset code
In-Reply-To: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <1368916627-23139-6-git-send-email-tomasz.figa@gmail.com>

Since all platforms have been moved to the new watchdog reset driver,
the legacy code can be removed safely.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 .../arm/plat-samsung/include/plat/watchdog-reset.h | 35 ----------------------
 1 file changed, 35 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index 4def1b2..f2dc304 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -13,41 +13,6 @@
 #ifndef __PLAT_WATCHDOG_RESET_H
 #define __PLAT_WATCHDOG_RESET_H
 
-#include <plat/clock.h>
-#include <plat/regs-watchdog.h>
-#include <mach/map.h>
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-
-static inline void arch_wdt_reset(void)
-{
-	printk("arch_reset: attempting watchdog reset\n");
-
-	__raw_writel(0, S3C2410_WTCON);	  /* disable watchdog, to be safe  */
-
-	if (!IS_ERR(s3c2410_wdtclk))
-		clk_enable(s3c2410_wdtclk);
-
-	/* put initial values into count and data */
-	__raw_writel(0x80, S3C2410_WTCNT);
-	__raw_writel(0x80, S3C2410_WTDAT);
-
-	/* set the watchdog to go and reset... */
-	__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-		     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-
-	/* wait for reset to assert... */
-	mdelay(500);
-
-	printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-
-	/* delay to allow the serial port to show the message */
-	mdelay(50);
-}
-
 extern void samsung_wdt_reset(void);
 extern void samsung_wdt_reset_of_init(void);
 extern void samsung_wdt_reset_init(void __iomem *base);
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 18:37:07 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:37:07 +0200
Subject: [PATCH 6/6] ARM: SAMSUNG: Remove unused plat/regs-watchdog.h header
In-Reply-To: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <1368916627-23139-7-git-send-email-tomasz.figa@gmail.com>

Since there are no remaining users of this header, it can be safely
dropped.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 arch/arm/plat-samsung/include/plat/regs-watchdog.h | 41 ----------------------
 1 file changed, 41 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-watchdog.h

diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
deleted file mode 100644
index 4938492..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux at simtec.co.uk>
- *		      http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H
-
-#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-
-#define S3C2410_WTCON	   S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT	   S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT	   S3C_WDOGREG(0x08)
-
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-
-#define S3C2410_WTCON_RSTEN   (0x01)
-#define S3C2410_WTCON_INTEN   (1<<2)
-#define S3C2410_WTCON_ENABLE  (1<<5)
-
-#define S3C2410_WTCON_DIV16   (0<<3)
-#define S3C2410_WTCON_DIV32   (1<<3)
-#define S3C2410_WTCON_DIV64   (2<<3)
-#define S3C2410_WTCON_DIV128  (3<<3)
-
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
-
-
-- 
1.8.2.1



From linus.walleij at linaro.org  Sat May 18 18:47:39 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 19 May 2013 00:47:39 +0200
Subject: [PATCH] ARM: nomadik: fix IRQ assignment for SMC ethernet
Message-ID: <1368917259-7883-1-git-send-email-linus.walleij@linaro.org>

The assignment of IRQ for the SMC91x ethernet adapter had two
problems making it non-working:

- It was not put into the ethernet device node. Let's do this
  by using the board-specific overlay, so we can make other
  overlays on other Nomadik boards.

- The IRQ number was actually completely wrong, this was the
  number for NHK8815, not S8815.

After this ethernet starts working on the USB S8815.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ARM SoC folks: I would appreciate if you apply this patch
directly for v3.10 fixes.
---
 arch/arm/boot/dts/ste-nomadik-s8815.dts | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index b28fbf3..6f82d93 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -14,13 +14,19 @@
 		bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
 	};
 
+	/* This is where the interrupt is routed on the S8815 board */
+	external-bus at 34000000 {
+		ethernet at 300 {
+			interrupt-parent = <&gpio3>;
+			interrupts = <8 0x1>;
+		};
+	};
+
 	/* Custom board node with GPIO pins to active etc */
 	usb-s8815 {
 		/* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
 		ethernet-gpio {
-			gpios = <&gpio3 19 0x1>;
-			interrupts = <19 0x1>;
-			interrupt-parent = <&gpio3>;
+			gpios = <&gpio3 8 0x1>;
 		};
 		/* This will bias the MMC/SD card detect line */
 		mmcsd-gpio {
-- 
1.8.1.4



From tomasz.figa at gmail.com  Sat May 18 18:50:05 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:50:05 +0200
Subject: [PATCH v2 2/6] ARM: SAMSUNG: uncompress: Use local definitions of
 watchdog registers
In-Reply-To: <1368916627-23139-3-git-send-email-tomasz.figa@gmail.com>
References: <1368916627-23139-1-git-send-email-tomasz.figa@gmail.com>
 <1368916627-23139-3-git-send-email-tomasz.figa@gmail.com>
Message-ID: <3859367.63djUfrUBu@flatron>

This patch adds local definitions of required watchdog registers and
bitfields to the uncompress header, allowing to remove the dependency on
plat/regs-watchdog.h header and the ugly hack to replace virtual with
physical addresses.

In addition, it fixes reboot on decompression failure feature, due to
the mentioned ugly hack not working anymore (the macro being redefined
got renamed, without fixing this code).

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
Changes since v1:
 - Proper commit message. I have sent wrong version previously, sorry
  for the noise.

 arch/arm/plat-samsung/include/plat/uncompress.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 438b248..e8954b8 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -28,11 +28,20 @@ static void arch_detect_cpu(void);
 /* defines for UART registers */
 
 #include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
 
 /* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+#define S3C_WDOGREG(x)	((S3C_PA_WDT + (x)))
+
+#define S3C2410_WTCON	S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT	S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT	S3C_WDOGREG(0x08)
+
+#define S3C2410_WTCON_RSTEN	(1 << 0)
+#define S3C2410_WTCON_ENABLE	(1 << 5)
+
+#define S3C2410_WTCON_DIV128	(3 << 3)
+
+#define S3C2410_WTCON_PRESCALE(x)	((x) << 8)
 
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
-- 
1.8.2.1




From tomasz.figa at gmail.com  Sat May 18 18:56:30 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 00:56:30 +0200
Subject: [PATCH] of: irq: Pass trigger type in IRQ resource flags
Message-ID: <1368917790-23770-1-git-send-email-tomasz.figa@gmail.com>

Some drivers might rely on availability of trigger flags in IRQ
resource, for example to configure the hardware for particular interrupt
type. However current code creating IRQ resources from data in device
tree does not configure trigger flags in resulting resources.

This patch solves the problem, based on the fact that
irq_of_parse_and_map() configures the trigger based on DT interrupt
specifier, IRQD_TRIGGER_* flags are consistent with IORESOURCE_IRQ_*,
and we can get trigger type by calling irqd_get_trigger_type() after
mapping the interrupt.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 drivers/of/irq.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index a3c1c5a..79a7a26 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -355,6 +355,16 @@ int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
 		r->start = r->end = irq;
 		r->flags = IORESOURCE_IRQ;
 		r->name = name ? name : dev->full_name;
+
+		/*
+		 * Some drivers might rely on availability of trigger flags
+		 * in IRQ resource. Since irq_of_parse_and_map() configures the
+		 * trigger based on interrupt specifier and IRQD_TRIGGER_*
+		 * flags are consistent with IORESOURCE_IRQ_*, we can get
+		 * trigger type that was just set and pass it through resource
+		 * flags as well.
+		 */
+		r->flags |= irqd_get_trigger_type(irq_get_irq_data(irq));
 	}
 
 	return irq;
-- 
1.8.2.1



From tomasz.figa at gmail.com  Sat May 18 19:03:14 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 01:03:14 +0200
Subject: [PATCH] net: dm9000: Allow instantiation using device tree
Message-ID: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>

This patch adds Device Tree support to dm9000 driver.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---
 .../devicetree/bindings/net/davicom-dm9000.txt     | 27 ++++++++++
 .../devicetree/bindings/vendor-prefixes.txt        |  1 +
 drivers/net/ethernet/davicom/dm9000.c              | 60 ++++++++++++++++++++++
 3 files changed, 88 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/davicom-dm9000.txt

diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
new file mode 100644
index 0000000..d2902db
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
@@ -0,0 +1,27 @@
+Davicom DM9000 Fast Ethernet controller
+
+Required properties:
+- compatible = "davicom,dm9000";
+- reg : physical addresses and sizes of registers, must contain 2 entries:
+    first entry : address register,
+    second entry : address register.
+- interrupt-parent : interrupt controller to which the device is connected
+- interrupts : interrupt specifier specific to interrupt controller
+
+Optional properties:
+- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC address
+    to use (from firmware or bootloader)
+- davicom,no-eeprom : Configuration EEPROM is not available
+- davicom,ext-phy : Use external PHY
+- davicom,simple-phy : Use NSR to find LinkStatus
+
+Example:
+
+	ethernet at 18000000 {
+		compatible = "davicom,dm9000";
+		reg = <0x18000000 0x2 0x18000004 0x2>;
+		interrupt-parent = <&gpn>;
+		interrupts = <7 4>;
+		local-mac-address = [00 00 de ad be ef];
+		davicom,no-eeprom;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c43..2fe74e6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -18,6 +18,7 @@ chrp	Common Hardware Reference Platform
 cirrus	Cirrus Logic, Inc.
 cortina	Cortina Systems, Inc.
 dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
+davicom	DAVICOM Semiconductor, Inc.
 denx	Denx Software Engineering
 emmicro	EM Microelectronic
 epson	Seiko Epson Corp.
diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
index 9105465..6c91708 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -29,6 +29,7 @@
 #include <linux/spinlock.h>
 #include <linux/crc32.h>
 #include <linux/mii.h>
+#include <linux/of.h>
 #include <linux/ethtool.h>
 #include <linux/dm9000.h>
 #include <linux/delay.h>
@@ -1358,6 +1359,50 @@ static const struct net_device_ops dm9000_netdev_ops = {
 #endif
 };
 
+#ifdef CONFIG_OF
+static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
+{
+	struct dm9000_plat_data *pdata;
+	struct device_node *np = dev->of_node;
+	const void *prop;
+	int len;
+
+	if (!np)
+		return NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata) {
+		dev_err(dev, "failed to allocate platform data struct\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	if (of_find_property(np, "davicom,ext-phy", NULL))
+		pdata->flags |= DM9000_PLATF_EXT_PHY;
+	if (of_find_property(np, "davicom,no-eeprom", NULL))
+		pdata->flags |= DM9000_PLATF_NO_EEPROM;
+	if (of_find_property(np, "davicom,simple-phy", NULL))
+		pdata->flags |= DM9000_PLATF_SIMPLE_PHY;
+
+	prop = of_get_property(np, "local-mac-address", &len);
+	if (!prop)
+		return pdata;
+
+	if (len < sizeof(pdata->dev_addr)) {
+		dev_err(dev, "invalid length of local-mac-address property\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	memcpy(pdata->dev_addr, prop, sizeof(pdata->dev_addr));
+
+	return pdata;
+}
+#else
+static struct dm9000_plat_data *dm9000_parse_dt(struct device *unused)
+{
+	return NULL;
+}
+#endif
+
 /*
  * Search DM9000 board, allocate space and register it
  */
@@ -1373,6 +1418,12 @@ dm9000_probe(struct platform_device *pdev)
 	int i;
 	u32 id_val;
 
+	if (!pdata) {
+		pdata = dm9000_parse_dt(&pdev->dev);
+		if (IS_ERR(pdata))
+			return PTR_ERR(pdata);
+	}
+
 	/* Init network device */
 	ndev = alloc_etherdev(sizeof(struct board_info));
 	if (!ndev)
@@ -1683,11 +1734,20 @@ dm9000_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id dm9000_of_matches[] = {
+	{ .compatible = "davicom,dm9000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dm9000_of_matches);
+#endif
+
 static struct platform_driver dm9000_driver = {
 	.driver	= {
 		.name    = "dm9000",
 		.owner	 = THIS_MODULE,
 		.pm	 = &dm9000_drv_pm_ops,
+		.of_match_table = of_match_ptr(dm9000_of_matches),
 	},
 	.probe   = dm9000_probe,
 	.remove  = dm9000_drv_remove,
-- 
1.8.2.1



From moinejf at free.fr  Sun May 19 02:01:52 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sun, 19 May 2013 08:01:52 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <5197D6C1.3060702@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf> <5197D6C1.3060702@gmail.com>
Message-ID: <20130519080152.0b486b75@armhf>

On Sat, 18 May 2013 21:30:09 +0200
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:

> So in the end, we will have a DT node for the HW controllers found
> in Dove SoCs, a node for TDA998x, and a node for the video card, i.e.
> _how_ lcd controllers, external encoders, clocks, maybe audio, ...
> are hooked up on that specific board.

Here is my dove-cubox.dts. What is wrong with it?

/dts-v1/;

/include/ "dove.dtsi"

/ {
	model = "SolidRun CuBox";
	compatible = "solidrun,cubox", "marvell,dove";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_gpio_18>;
		pinctrl-names = "default";

		power {
			label = "Power";
			gpios = <&gpio0 18 1>;
			linux,default-trigger = "default-on";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		usb_power: regulator at 1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 1 0>;
		};
	};

	clocks {
		/* 25MHz reference crystal */
		ref25: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		lcdclk: fixed-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <400000000>;
		};
	};

	audio {
		compatible = "marvell,kirkwood-spdif-audio";
		id = <1>;
	};

	video {
		compatible = "marvell,dove-video";
	};
};

&uart0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	si5351: clock-generator {
		compatible = "silabs,si5351a-msop";
		reg = <0x60>;
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;

		/* connect xtal input to 25MHz reference */
		clocks = <&ref25>;

		/* connect xtal input as source of pll0 and pll1 */
		silabs,pll-source = <0 0>, <1 0>;

		clkout0 {
			reg = <0>;
			silabs,drive-strength = <8>;
			silabs,multisynth-source = <0>;
			silabs,clock-source = <0>;
			silabs,pll-master;
		};

		clkout1 {
			reg = <1>;
			silabs,drive-strength = <8>;
			silabs,multisynth-source = <1>;
			silabs,clock-source = <0>;
			silabs,pll-master;
		};

		clkout2 {
			reg = <2>;
			silabs,multisynth-source = <1>;
			silabs,clock-source = <0>;
		};
	};

	tda998x: hdmi-encoder {
		compatible = "nxp,tda998x";
		reg = <0x70>;
		interrupt-parent = <&gpio0>;
		interrupts = <27 2>;		/* falling edge */
	};
};

&sdio0 {
	status = "okay";
	/* sdio0 card detect is connected to wrong pin on CuBox */
	cd-gpios = <&gpio0 12 1>;
};

&spi0 {
	status = "okay";

	/* spi0.0: 4M Flash Winbond W25Q32BV */
	spi-flash at 0 {
		compatible = "st,w25q32";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&pinctrl {
	pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12 &pmx_gpio_13 &pmx_gpio_camera>;
	pinctrl-names = "default";

	pmx_gpio_1: pmx-gpio-1 {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_gpio_12: pmx-gpio-12 {
		marvell,pins = "mpp12";
		marvell,function = "gpio";
	};

/* kirkwood i2s */
	pmx_gpio_13: pmx-gpio-13 {
		marvell,pins = "mpp13";
		marvell,function = "gpio";
	};

	pmx_gpio_18: pmx-gpio-18 {
		marvell,pins = "mpp18";
		marvell,function = "gpio";
	};
/* nxp HDMI irq on pin 27 */
	pmx_gpio_camera: pmx-gpio-camera {
		marvell,pins = "mpp_camera";
		marvell,function = "gpio";
	};
};

&mdio { status = "okay"; };
&ethernet { status = "okay"; };
&lcd0 {
	status = "okay";
	clocks = <&core_clk 3>, <0>, <&lcdclk>, <&si5351 0>;
	marvell,port-type = <11>;		/* HDMIA */
	marvell,external-encoder = <&tda998x>;
};

&i2s1 { status = "okay"; };

/* --- test (not cubox) ---- *
&dcon { status = "okay"; };

&lcd1 {
	status = "okay";
	clocks = <&core_clk 3>, <0>, <&lcdclk>, <0>;
	marvell,port-type = <1>;
	display-timings {
		mode {
			hactive = <1920>;
			vactive = <1080>;
			hfront-porch = <88>;
			hsync-len = <44>;
			hback-porch = <148>;
			vfront-porch = <4>;
			vsync-len = <5>;
			vback-porch = <36>;
			clock = <148500>;
		};
	};
};
 * ---- */

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From s.hauer at pengutronix.de  Sun May 19 03:05:38 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 19 May 2013 09:05:38 +0200
Subject: [PATCH] net: dm9000: Allow instantiation using device tree
In-Reply-To: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>
References: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <20130519070538.GX32299@pengutronix.de>

Hi Tomasz,

On Sun, May 19, 2013 at 01:03:14AM +0200, Tomasz Figa wrote:
> This patch adds Device Tree support to dm9000 driver.
> 
> Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
> ---
>  .../devicetree/bindings/net/davicom-dm9000.txt     | 27 ++++++++++
>  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
>  drivers/net/ethernet/davicom/dm9000.c              | 60 ++++++++++++++++++++++
>  3 files changed, 88 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/davicom-dm9000.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> new file mode 100644
> index 0000000..d2902db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> @@ -0,0 +1,27 @@
> +Davicom DM9000 Fast Ethernet controller
> +
> +Required properties:
> +- compatible = "davicom,dm9000";
> +- reg : physical addresses and sizes of registers, must contain 2 entries:
> +    first entry : address register,
> +    second entry : address register.
> +- interrupt-parent : interrupt controller to which the device is connected
> +- interrupts : interrupt specifier specific to interrupt controller
> +
> +Optional properties:
> +- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC address
> +    to use (from firmware or bootloader)
> +- davicom,no-eeprom : Configuration EEPROM is not available
> +- davicom,ext-phy : Use external PHY
> +- davicom,simple-phy : Use NSR to find LinkStatus

Do we really need to expose this simple-phy property? Looking at the
drvier code this more looks like a work around shortcomings of the
driver code rather than something really necessary.

> +#ifdef CONFIG_OF
> +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
> +{
> +	struct dm9000_plat_data *pdata;
> +	struct device_node *np = dev->of_node;
> +	const void *prop;
> +	int len;
> +
> +	if (!np)
> +		return NULL;

You should be able to kill the ifdef around this function by doing

	if (!IS_ENABLED(CONFIG_OF) || !np)
		return NULL;

> +
> +	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata) {
> +		dev_err(dev, "failed to allocate platform data struct\n");
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	if (of_find_property(np, "davicom,ext-phy", NULL))
> +		pdata->flags |= DM9000_PLATF_EXT_PHY;
> +	if (of_find_property(np, "davicom,no-eeprom", NULL))
> +		pdata->flags |= DM9000_PLATF_NO_EEPROM;
> +	if (of_find_property(np, "davicom,simple-phy", NULL))
> +		pdata->flags |= DM9000_PLATF_SIMPLE_PHY;
> +
> +	prop = of_get_property(np, "local-mac-address", &len);
> +	if (!prop)
> +		return pdata;

I think you should use of_get_mac_address() here.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thomas.petazzoni at free-electrons.com  Sun May 19 03:13:26 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sun, 19 May 2013 09:13:26 +0200
Subject: [PATCH 2/2] ARM: mvebu: Add support for NOR flash device on
 Armada XP-DB board
In-Reply-To: <20130517165656.GE11137@titan.lakedaemon.net>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
 <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>
 <20130517165656.GE11137@titan.lakedaemon.net>
Message-ID: <20130519091326.74a77b91@skate>

Dear Jason Cooper,

On Fri, 17 May 2013 12:56:56 -0400, Jason Cooper wrote:
> On Fri, May 17, 2013 at 08:09:58AM -0300, Ezequiel Garcia wrote:
> > The Armada XP Development Board (DB-78460-BP) has a NOR flash device
> > connected to the Device Bus. This commit adds the device tree node
> > to support this device.
> > 
> > This SoC supports a flexible and dynamic decoding window allocation
> > scheme; but since this feature is still not implemented we need
> > to specify the window base address in the device tree node itself.
> > 
> > This base address has been selected in a completely arbitrary fashion.
> > 
> > Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> > Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> > ---
> >  arch/arm/boot/dts/armada-xp-db.dts | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> 
> Applied to mvebu/fixes

Is mvebu/fixes the branch intended to be pushed to 3.10-rcX, or to
3.11 ?

I'm asking because you've applied both 1/2 and 2/2 on the same
mvebu/fixes branch, while 1/2 is intended for 3.10-rcX (fixing
existing DT data), and 2/2 is intended for 3.11 (adding support for a
new device in the DT).

Thanks,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linux at prisktech.co.nz  Sun May 19 04:06:45 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Sun, 19 May 2013 20:06:45 +1200
Subject: [PATCH 0/4] FB updates for 3.11
In-Reply-To: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
References: <1368868514-18975-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <51988815.40006@prisktech.co.nz>

On 18/05/13 21:15, Tony Prisk wrote:
> Patch #1 - Move register defines inside the driver and drop the header.
> Patch #2 - Convert the register defines to use the vendor preferred names.
> Patch #3 - Add a device clock to wm8505fb. Without it, only the uboot
> initialized resolution is supported.
> Patch #4 - Add support for the VGA output found on the APC8750 board.
>
> Tony Prisk (4):
>    fb: vt8500: Move register defines inside driver
>    fb: vt8500: Convert to use vendor register names
>    fb: vt8500: Require a device clock for wm8505fb driver
>    fb: vt8500: Add VGA output support to wm8505fb driver.
>
>   .../devicetree/bindings/video/wm,wm8505-fb.txt     |    9 +-
>   drivers/video/wm8505fb.c                           |  195 ++++++++++++--
>   drivers/video/wm8505fb_regs.h                      |   76 ------
>   drivers/video/wmt_ge_rops.c                        |  280 +++++++++++++++-----
>   4 files changed, 394 insertions(+), 166 deletions(-)
>   delete mode 100644 drivers/video/wm8505fb_regs.h
>
Florian/Tomi,

Please ignore these patches. This driver needs a bit more work, so I 
will do a
more thorough series and resubmit.

Regards
Tony Prisk


From sebastian.hesselbarth at gmail.com  Sun May 19 04:30:00 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sun, 19 May 2013 10:30:00 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <20130519080152.0b486b75@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf> <5197D6C1.3060702@gmail.com>
 <20130519080152.0b486b75@armhf>
Message-ID: <51988D88.10306@gmail.com>

On 05/19/2013 08:01 AM, Jean-Francois Moine wrote:
> On Sat, 18 May 2013 21:30:09 +0200
> Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>  wrote:
>> So in the end, we will have a DT node for the HW controllers found
>> in Dove SoCs, a node for TDA998x, and a node for the video card, i.e.
>> _how_ lcd controllers, external encoders, clocks, maybe audio, ...
>> are hooked up on that specific board.
>
> Here is my dove-cubox.dts. What is wrong with it?

Oh come on, seriously?

There is _nothing_ wrong with it, it already reflects what I told you
would be required for generic Dove SoC board video.

> 	video {
> 		compatible = "marvell,dove-video";
> 	};

As you may have noticed, the RFC node I sent yesterday. Is in _no_ way
different from a functional point of view. I added a video-memory
property, I renamed the compatible string. And I moved clocks property
to the video card *but* as I said in the RFC description:

"This adds a video card node required for rmk's dove_drm driver. Reg
property matches reserved memory region (currently 16M at top of 
memory), clocks property should carry extclk0 for now."

It is a node *required for rmk's dove_drm driver* for you to _test_
that very driver.

> &lcd0 {
> 	status = "okay";
> 	clocks =<&core_clk 3>,<0>,<&lcdclk>,<&si5351 0>;
> 	marvell,port-type =<11>;		/* HDMIA */
> 	marvell,external-encoder =<&tda998x>;
> };

Again, there is no DT support in *rmk's driver*! I didn't add those
to the RFC node. I provided a DT node to *test* rmk driver. While
you were busy with complaining about things we already answered,
I did test the driver on both Cubox and D2Plug. Now I can start
with looking into rmk's driver and _suggest_ to fix this or that.

> /* --- test (not cubox) ---- *
> &dcon { status = "okay"; };
>
> &lcd1 {
> 	status = "okay";
> 	clocks =<&core_clk 3>,<0>,<&lcdclk>,<0>;
> 	marvell,port-type =<1>;
> 	display-timings {
> 		mode {
> 			hactive =<1920>;
> 			vactive =<1080>;
> 			hfront-porch =<88>;
> 			hsync-len =<44>;
> 			hback-porch =<148>;
> 			vfront-porch =<4>;
> 			vsync-len =<5>;
> 			vback-porch =<36>;
> 			clock =<148500>;
> 		};
> 	};

I would be surprised if, lcd1 will ever be capable of driving
1080p60 on a *VGA port*!

Seriously, start _reading_ what we say. I want all those
features I already told you for your driver, in mainline driver
too. All I told you was to prevent you from doing dirty little
Cubox specific hacks that I would have to remove for e.g. D2Plug.

*But* if you ask me if we should take Russell's or your driver
as a basis, the answer is Russell's. Colon.

Sebastian


From romieu at fr.zoreil.com  Sun May 19 04:38:22 2013
From: romieu at fr.zoreil.com (Francois Romieu)
Date: Sun, 19 May 2013 10:38:22 +0200
Subject: [PATCH] net: dm9000: Allow instantiation using device tree
In-Reply-To: <20130519070538.GX32299@pengutronix.de>
References: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>
 <20130519070538.GX32299@pengutronix.de>
Message-ID: <20130519083822.GA31087@electric-eye.fr.zoreil.com>

Sascha Hauer <s.hauer at pengutronix.de> :
[...]
> > +#ifdef CONFIG_OF
> > +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
> > +{
> > +	struct dm9000_plat_data *pdata;
> > +	struct device_node *np = dev->of_node;
> > +	const void *prop;
> > +	int len;
> > +
> > +	if (!np)
> > +		return NULL;
> 
> You should be able to kill the ifdef around this function by doing
> 
> 	if (!IS_ENABLED(CONFIG_OF) || !np)
> 		return NULL;

It will be the first such use of IS_ENABLED in net land.

David, is it ok ?

-- 
Ueimor


From tomasz.figa at gmail.com  Sun May 19 04:54:53 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 10:54:53 +0200
Subject: [PATCH] net: dm9000: Allow instantiation using device tree
In-Reply-To: <20130519070538.GX32299@pengutronix.de>
References: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>
 <20130519070538.GX32299@pengutronix.de>
Message-ID: <2763249.7aFBh8NOHl@flatron>

Hi Sascha,

On Sunday 19 of May 2013 09:05:38 Sascha Hauer wrote:
> Hi Tomasz,
> 
> On Sun, May 19, 2013 at 01:03:14AM +0200, Tomasz Figa wrote:
> > This patch adds Device Tree support to dm9000 driver.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
> > ---
> > 
> >  .../devicetree/bindings/net/davicom-dm9000.txt     | 27 ++++++++++
> >  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
> >  drivers/net/ethernet/davicom/dm9000.c              | 60
> >  ++++++++++++++++++++++ 3 files changed, 88 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/net/davicom-dm9000.txt> 
> > diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > b/Documentation/devicetree/bindings/net/davicom-dm9000.txt new file
> > mode 100644
> > index 0000000..d2902db
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > @@ -0,0 +1,27 @@
> > +Davicom DM9000 Fast Ethernet controller
> > +
> > +Required properties:
> > +- compatible = "davicom,dm9000";
> > +- reg : physical addresses and sizes of registers, must contain 2
> > entries: +    first entry : address register,
> > +    second entry : address register.
> > +- interrupt-parent : interrupt controller to which the device is
> > connected +- interrupts : interrupt specifier specific to interrupt
> > controller +
> > +Optional properties:
> > +- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC
> > address +    to use (from firmware or bootloader)
> > +- davicom,no-eeprom : Configuration EEPROM is not available
> > +- davicom,ext-phy : Use external PHY
> > +- davicom,simple-phy : Use NSR to find LinkStatus
> 
> Do we really need to expose this simple-phy property? Looking at the
> drvier code this more looks like a work around shortcomings of the
> driver code rather than something really necessary.

Well, depending on this property it can use two different methods of 
checking carrier status and it seems to depend on hardware, which one 
should be used. I don't see any driver shortcomings here, but maybe I'm 
missing something.

> > +#ifdef CONFIG_OF
> > +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
> > +{
> > +	struct dm9000_plat_data *pdata;
> > +	struct device_node *np = dev->of_node;
> > +	const void *prop;
> > +	int len;
> > +
> > +	if (!np)
> > +		return NULL;
> 
> You should be able to kill the ifdef around this function by doing

Basically this would be a kill with a double-edged sword.

I could completely drop the #ifdef without any additional check, as it is 
not possible that np is not NULL with !CONFIG_OF, but I decided to keep 
the code conditional to reduce driver code a bit on platforms that don't 
need OF.

Maybe this single driver wouldn't give any significant difference, but if 
you make all the drivers used on the platform this way, you will save some 
kilobytes.

> 	if (!IS_ENABLED(CONFIG_OF) || !np)
> 		return NULL;
> 
> > +
> > +	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> > +	if (!pdata) {
> > +		dev_err(dev, "failed to allocate platform data struct\n");
> > +		return ERR_PTR(-ENOMEM);
> > +	}
> > +
> > +	if (of_find_property(np, "davicom,ext-phy", NULL))
> > +		pdata->flags |= DM9000_PLATF_EXT_PHY;
> > +	if (of_find_property(np, "davicom,no-eeprom", NULL))
> > +		pdata->flags |= DM9000_PLATF_NO_EEPROM;
> > +	if (of_find_property(np, "davicom,simple-phy", NULL))
> > +		pdata->flags |= DM9000_PLATF_SIMPLE_PHY;
> > +
> > +	prop = of_get_property(np, "local-mac-address", &len);
> > +	if (!prop)
> > +		return pdata;
> 
> I think you should use of_get_mac_address() here.

Oops. Right, this is what I was looking for, but somehow I failed. Will 
change this in next version. Thanks.

Best regards,
Tomasz



From linux at arm.linux.org.uk  Sun May 19 04:59:20 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 19 May 2013 09:59:20 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517194023.0c385ea0@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
Message-ID: <20130519085920.GO18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 07:40:23PM +0200, Jean-Francois Moine wrote:
> Maybe I did not explain correctly: the colored cursor maybe RGB888 +
> transparency (64x64) or full ARGB (64x32 or 32x64). I coded the first
> case. And, yes, I better like a hardware cursor: it asks for less
> computation, and I get it immediately at graphic starting time!

Having looked at this now, using the RGB+transparency is less than ideal
because we're having to reduce an alpha channel down to a simple on/off
transparency.  X cursors really are alphablended components!

So, the options here are:
(a) use "software" rendered cursor
    + correct and expected cursor size
    + correct rendering
    + possible to use the GPU (I believe mine does)
    - maybe time consuming as it has to be removed/replaced on the screen
(b) use RGB+transparency for 64x64 hardware cursor
    + correct and expected cursor size
    + does not have to be removed/replaced when screen contents change
    - incorrect rendering due to reducing the alpha channel to a simple
      on/off transparency mask
    - has to be reloaded when the pointer is close to the edges of the
      screen which is CPU intensive
    - cursor image data passed into DRM is required to be ARGB (I've
      discussed this with David Airlie last night.)  This means we have
      to do translation to RGB+T in the kernel which is *not* nice.
(c) use ARGB 32x64 or 64x32 hardware cursor
    + does not have to be removed/replaced when screen contents change
    + correct rendering of cursor
    - unexpected cursor size; user clients do not expect to be restricted
      to 32 rows or 32 lines of cursor
    - can only select maximum cursor size on initialization of hardware
      cursor; can't dynamically switch between 32x64 and 64x32 sizes
    - has to be reloaded when the pointer is close to the edges of the
      screen which is CPU intensive

While I would like to have hardware cursor support, I don't think it's
worth the effort.  The one which tips it for me is the need to reload
the cursor near the edges - note the restriction in the documentation
that the cursor position + cursor size can't be outside the active
size.  Also, cursors generally have 7 or so transparent pixels to the
left of them (which of course changes depending on the cursor shape.)

It's also less CPU intensive to (probably) allow the GPU to render it
than it is for the CPU to deal with these hardware restrictions.

I would've liked to see hardware cursor support, but I think what I'm
going to be doing is stripping the cursor code out of the main driver
into a separate optional patch which will ultimately be dropped.


From mst at redhat.com  Sun May 19 05:35:26 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Sun, 19 May 2013 12:35:26 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130516184041.GP19669@dyad.programming.kicks-ass.net>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
Message-ID: <20130519093526.GD19883@redhat.com>

On Thu, May 16, 2013 at 08:40:41PM +0200, Peter Zijlstra wrote:
> On Thu, May 16, 2013 at 02:16:10PM +0300, Michael S. Tsirkin wrote:
> > There are several ways to make sure might_fault
> > calling function does not sleep.
> > One is to use it on kernel or otherwise locked memory - apparently
> > nfs/sunrpc does this. As noted by Ingo, this is handled by the
> > migh_fault() implementation in mm/memory.c but not the one in
> > linux/kernel.h so in the current code might_fault() schedules
> > differently depending on CONFIG_PROVE_LOCKING, which is an undesired
> > semantical side effect.
> > 
> > Another is to call pagefault_disable: in this case the page fault
> > handler will go to fixups processing and we get an error instead of
> > sleeping, so the might_sleep annotation is a false positive.
> > vhost driver wants to do this now in order to reuse socket ops
> > under a spinlock (and fall back on slower thread handler
> > on error).
> 
> Are you using the assumption that spin_lock() implies preempt_disable() implies
> pagefault_disable()? Note that this assumption isn't valid for -rt where the
> spinlock becomes preemptible but we'll not disable pagefaults.

No, I was not assuming that. What I'm trying to say is that a caller
that does something like this under a spinlock:
	preempt_disable
	pagefault_disable
	error = copy_to_user
	pagefault_enable
	preempt_enable_no_resched

is not doing anything wrong and should not get a warning,
as long as error is handled correctly later.
Right?

> > Address both issues by:
> > 	- dropping the unconditional call to might_sleep
> > 	  from the fast might_fault code in linux/kernel.h
> > 	- checking for pagefault_disable() in the
> > 	  CONFIG_PROVE_LOCKING implementation
> > 
> > Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
> > ---
> >  include/linux/kernel.h |  1 -
> >  mm/memory.c            | 14 +++++++++-----
> >  2 files changed, 9 insertions(+), 6 deletions(-)
> > 
> > diff --git a/include/linux/kernel.h b/include/linux/kernel.h
> > index e96329c..322b065 100644
> > --- a/include/linux/kernel.h
> > +++ b/include/linux/kernel.h
> > @@ -198,7 +198,6 @@ void might_fault(void);
> >  #else
> >  static inline void might_fault(void)
> >  {
> > -	might_sleep();
> 
> This removes potential resched points for PREEMPT_VOLUNTARY -- was that
> intentional?

No it's a bug. Thanks for pointing this out.
OK so I guess it should be might_sleep_if(!in_atomic())
and this means might_fault would have to move from linux/kernel.h to
linux/uaccess.h, since in_atomic() is in linux/hardirq.h

Makes sense?

> >  }
> >  #endif
> >  
> > diff --git a/mm/memory.c b/mm/memory.c
> > index 6dc1882..1b8327b 100644
> > --- a/mm/memory.c
> > +++ b/mm/memory.c
> > @@ -4222,13 +4222,17 @@ void might_fault(void)
> >  	if (segment_eq(get_fs(), KERNEL_DS))
> >  		return;
> >  
> > -	might_sleep();
> >  	/*
> > -	 * it would be nicer only to annotate paths which are not under
> > -	 * pagefault_disable, however that requires a larger audit and
> > -	 * providing helpers like get_user_atomic.
> > +	 * It would be nicer to annotate paths which are under preempt_disable
> > +	 * but not under pagefault_disable, however that requires a new flag
> > +	 * for differentiating between the two.
> 
> -rt has this, pagefault_disable() doesn't change the preempt count but pokes
> at task_struct::pagefault_disable.

Good to know.

So maybe we can import this at least for CONFIG_PROVE_LOCKING?
To make the patch smaller I'd prefer doing both for now,
this way this patchset does not have to poke in too many
mm internals.
I can try doing that - unless
someone else has plans to merge this part soon anyway?

> >  	 */
> > -	if (!in_atomic() && current->mm)
> > +	if (in_atomic())
> > +		return;
> > +
> > +	might_sleep();
> > +
> > +	if (current->mm)
> >  		might_lock_read(&current->mm->mmap_sem);
> >  }
> >  EXPORT_SYMBOL(might_fault);
> > -- 
> > MST


From linux at arm.linux.org.uk  Sun May 19 06:30:49 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 19 May 2013 11:30:49 +0100
Subject: [RFC 3/8] drm/i2c: nxp-tda998x: ensure VIP output mux is
 properly set
In-Reply-To: <20130518085659.40932cd8@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <E1Ud3og-0001qm-52@rmk-PC.arm.linux.org.uk> <20130518085659.40932cd8@armhf>
Message-ID: <20130519103049.GQ18614@n2100.arm.linux.org.uk>

On Sat, May 18, 2013 at 08:56:59AM +0200, Jean-Francois Moine wrote:
> On Thu, 16 May 2013 20:26:18 +0100
> Russell King <rmk+kernel at arm.linux.org.uk> wrote:
> 
> > When switching between various drivers for this device, it's possible
> > that some critical registers are left containing values which affect
> > the device operation.  One such case encountered is the VIP output
> > mux register.  This defaults to 0x24 on powerup, but other drivers may
> > set this to 0x12.  This results in incorrect colours.
> > 
> > Fix this by ensuring that the register is always set to the power on
> > default setting.
> > 
> > Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> > ---
> >  drivers/gpu/drm/i2c/tda998x_drv.c |    3 +++
> >  1 files changed, 3 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
> > index d71c408..4b4db95 100644
> > --- a/drivers/gpu/drm/i2c/tda998x_drv.c
> > +++ b/drivers/gpu/drm/i2c/tda998x_drv.c
> > @@ -110,6 +110,7 @@ struct tda998x_priv {
> >  #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
> >  # define VIP_CNTRL_5_CKCASE       (1 << 0)
> >  # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
> > +#define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
> >  #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
> >  # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
> >  # define MAT_CONTRL_MAT_BP        (1 << 2)
> > @@ -438,6 +439,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
> >  
> >  	switch (mode) {
> >  	case DRM_MODE_DPMS_ON:
> > +		/* Write the default value MUX register */
> > +		reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
> >  		/* enable audio and video ports */
> >  		reg_write(encoder, REG_ENA_AP, 0xff);
> >  		reg_write(encoder, REG_ENA_VP_0, 0xff);
> 
> This register is never touched. Should not this setting better go at
> reset time (in tda998x_reset)?

Yes, you're right, it could be done there without any additional side
effects.  I've just moved it there.


From s.hauer at pengutronix.de  Sun May 19 06:35:44 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 19 May 2013 12:35:44 +0200
Subject: [PATCH] net: dm9000: Allow instantiation using device tree
In-Reply-To: <2763249.7aFBh8NOHl@flatron>
References: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>
 <20130519070538.GX32299@pengutronix.de>
 <2763249.7aFBh8NOHl@flatron>
Message-ID: <20130519103544.GZ32299@pengutronix.de>

On Sun, May 19, 2013 at 10:54:53AM +0200, Tomasz Figa wrote:
> Hi Sascha,
> 
> On Sunday 19 of May 2013 09:05:38 Sascha Hauer wrote:
> > Hi Tomasz,
> > 
> > On Sun, May 19, 2013 at 01:03:14AM +0200, Tomasz Figa wrote:
> > > This patch adds Device Tree support to dm9000 driver.
> > > 
> > > Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
> > > ---
> > > 
> > >  .../devicetree/bindings/net/davicom-dm9000.txt     | 27 ++++++++++
> > >  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
> > >  drivers/net/ethernet/davicom/dm9000.c              | 60
> > >  ++++++++++++++++++++++ 3 files changed, 88 insertions(+)
> > >  create mode 100644
> > >  Documentation/devicetree/bindings/net/davicom-dm9000.txt> 
> > > diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > > b/Documentation/devicetree/bindings/net/davicom-dm9000.txt new file
> > > mode 100644
> > > index 0000000..d2902db
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > > @@ -0,0 +1,27 @@
> > > +Davicom DM9000 Fast Ethernet controller
> > > +
> > > +Required properties:
> > > +- compatible = "davicom,dm9000";
> > > +- reg : physical addresses and sizes of registers, must contain 2
> > > entries: +    first entry : address register,
> > > +    second entry : address register.
> > > +- interrupt-parent : interrupt controller to which the device is
> > > connected +- interrupts : interrupt specifier specific to interrupt
> > > controller +
> > > +Optional properties:
> > > +- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC
> > > address +    to use (from firmware or bootloader)
> > > +- davicom,no-eeprom : Configuration EEPROM is not available
> > > +- davicom,ext-phy : Use external PHY
> > > +- davicom,simple-phy : Use NSR to find LinkStatus
> > 
> > Do we really need to expose this simple-phy property? Looking at the
> > drvier code this more looks like a work around shortcomings of the
> > driver code rather than something really necessary.
> 
> Well, depending on this property it can use two different methods of 
> checking carrier status and it seems to depend on hardware, which one 
> should be used. I don't see any driver shortcomings here, but maybe I'm 
> missing something.

It's not hardware dependent, at least not from the original commit log.

The driver doesn't use mdiobus_register which you normally would do
today. If someone ports the driver over to mdiobus we would still have
to support this legacy flag as a special case.

Since no mainline user makes use of this flag I suggest to skip it from
the devicetree, at least until someone really asks for this specific
flag (and has good reasons to use it)

> 
> > > +#ifdef CONFIG_OF
> > > +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
> > > +{
> > > +	struct dm9000_plat_data *pdata;
> > > +	struct device_node *np = dev->of_node;
> > > +	const void *prop;
> > > +	int len;
> > > +
> > > +	if (!np)
> > > +		return NULL;
> > 
> > You should be able to kill the ifdef around this function by doing
> 
> Basically this would be a kill with a double-edged sword.
> 
> I could completely drop the #ifdef without any additional check, as it is 
> not possible that np is not NULL with !CONFIG_OF,

Yes, but the compiler doesn't know this.

> but I decided to keep 
> the code conditional to reduce driver code a bit on platforms that don't 
> need OF.

IS_ENABLED(CONFIG_OF) will expand to 0 without OF and the compiler will
through the unused code away. You won't find differences in the binary
size.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tomasz.figa at gmail.com  Sun May 19 07:04:59 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 13:04:59 +0200
Subject: [PATCH] net: dm9000: Allow instantiation using device tree
In-Reply-To: <20130519103544.GZ32299@pengutronix.de>
References: <1368918194-24030-1-git-send-email-tomasz.figa@gmail.com>
 <2763249.7aFBh8NOHl@flatron> <20130519103544.GZ32299@pengutronix.de>
Message-ID: <1433733.7VTOAEOlx2@flatron>

On Sunday 19 of May 2013 12:35:44 Sascha Hauer wrote:
> On Sun, May 19, 2013 at 10:54:53AM +0200, Tomasz Figa wrote:
> > Hi Sascha,
> > 
> > On Sunday 19 of May 2013 09:05:38 Sascha Hauer wrote:
> > > Hi Tomasz,
> > > 
> > > On Sun, May 19, 2013 at 01:03:14AM +0200, Tomasz Figa wrote:
> > > > This patch adds Device Tree support to dm9000 driver.
> > > > 
> > > > Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
> > > > ---
> > > > 
> > > >  .../devicetree/bindings/net/davicom-dm9000.txt     | 27
> > > >  ++++++++++
> > > >  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
> > > >  drivers/net/ethernet/davicom/dm9000.c              | 60
> > > >  ++++++++++++++++++++++ 3 files changed, 88 insertions(+)
> > > >  create mode 100644
> > > >  Documentation/devicetree/bindings/net/davicom-dm9000.txt>
> > > > 
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > > > b/Documentation/devicetree/bindings/net/davicom-dm9000.txt new
> > > > file
> > > > mode 100644
> > > > index 0000000..d2902db
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > > > @@ -0,0 +1,27 @@
> > > > +Davicom DM9000 Fast Ethernet controller
> > > > +
> > > > +Required properties:
> > > > +- compatible = "davicom,dm9000";
> > > > +- reg : physical addresses and sizes of registers, must contain 2
> > > > entries: +    first entry : address register,
> > > > +    second entry : address register.
> > > > +- interrupt-parent : interrupt controller to which the device is
> > > > connected +- interrupts : interrupt specifier specific to
> > > > interrupt
> > > > controller +
> > > > +Optional properties:
> > > > +- local-mac-address : A bytestring of 6 bytes specifying Ethernet
> > > > MAC
> > > > address +    to use (from firmware or bootloader)
> > > > +- davicom,no-eeprom : Configuration EEPROM is not available
> > > > +- davicom,ext-phy : Use external PHY
> > > > +- davicom,simple-phy : Use NSR to find LinkStatus
> > > 
> > > Do we really need to expose this simple-phy property? Looking at the
> > > drvier code this more looks like a work around shortcomings of the
> > > driver code rather than something really necessary.
> > 
> > Well, depending on this property it can use two different methods of
> > checking carrier status and it seems to depend on hardware, which one
> > should be used. I don't see any driver shortcomings here, but maybe
> > I'm
> > missing something.
> 
> It's not hardware dependent, at least not from the original commit log.
> 
> The driver doesn't use mdiobus_register which you normally would do
> today. If someone ports the driver over to mdiobus we would still have
> to support this legacy flag as a special case.
> 
> Since no mainline user makes use of this flag I suggest to skip it from
> the devicetree, at least until someone really asks for this specific
> flag (and has good reasons to use it)

Well, I don't need this flag on my platform, so I'm not strongly against 
removing it. If you really don't like it, I will remove it in v2.

> > > > +#ifdef CONFIG_OF
> > > > +static struct dm9000_plat_data *dm9000_parse_dt(struct device
> > > > *dev)
> > > > +{
> > > > +	struct dm9000_plat_data *pdata;
> > > > +	struct device_node *np = dev->of_node;
> > > > +	const void *prop;
> > > > +	int len;
> > > > +
> > > > +	if (!np)
> > > > +		return NULL;
> > > 
> > > You should be able to kill the ifdef around this function by doing
> > 
> > Basically this would be a kill with a double-edged sword.
> > 
> > I could completely drop the #ifdef without any additional check, as it
> > is not possible that np is not NULL with !CONFIG_OF,
> 
> Yes, but the compiler doesn't know this.
> 
> > but I decided to keep
> > the code conditional to reduce driver code a bit on platforms that
> > don't need OF.
> 
> IS_ENABLED(CONFIG_OF) will expand to 0 without OF and the compiler will
> through the unused code away. You won't find differences in the binary
> size.

Hmm, so IS_ENABLED returns a constant, OK. I have never bothered to look 
that up and ended with a strange belief that it is a runtime check (which 
doesn't make sense...). Always good to learn something, thanks.

OK, I'm fine with this, will change it in v2.

Best regards,
Tomasz



From dt.tangr at gmail.com  Sun May 19 07:09:17 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sun, 19 May 2013 21:09:17 +1000
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <201305161417.28133.arnd@arndb.de>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <201305151607.54442.arnd@arndb.de>
 <15FD6543-D04A-4953-A56A-40B27F0026E4@gmail.com>
 <201305161417.28133.arnd@arndb.de>
Message-ID: <F8915E01-0FCA-4C9F-8440-63B5A73B349B@gmail.com>


On 16/05/2013, at 10:17 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Thursday 16 May 2013, Daniel Tang wrote:
>> 
>> On 16/05/2013, at 12:07 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> 
>>> You are missing a binding in Documentation/devicetree, same as for some of
>>> the other drivers in this series.
>> 
>> Should we be adding a vendor prefix to it too? If so, we're not sure whether
>> to use "ti," or not since this isn't an official port by TI.
> 
> The binding describes the hardware, it should not matter who does the port.
> However, any part of the tree that is not actually from TI should have a
> vendor prefix indicating who made that part. IIRC, the SoC used in there
> is from TI, so you should use something else for the on-soc components.
> 

If the vendors for the on-SOC components are unknown, should we just leave the compatible strings as is (i.e. "nspire-XXX")?

>>> It seems strange to assign the clk_name variable to node->name
>>> first and then overriding it with the clock-output-names property.
>>> Is that intentional? If so, please explain it in a comment.
>>> 
>> 
>> I copied that bit of boilerplate from drivers/clk/clk-fixed-rate.c but
>> I'm guessing it's to use the node name as the clock name unless there
>> is a property called "clock-output-names"
> 
> Ah, I see. It seems you forgot to add the clock maintainer to Cc in the
> mail. Mike is the one who will have to take you patch anyway, so I assume
> he will comment on this if you did it wrong.
> 
> 	Arnd



From tomasz.figa at gmail.com  Sun May 19 07:16:31 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 13:16:31 +0200
Subject: [PATCH v2] net: dm9000: Allow instantiation using device tree
Message-ID: <1368962191-32594-1-git-send-email-tomasz.figa@gmail.com>

This patch adds Device Tree support to dm9000 driver.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---

Changes since v1:
 - dropped davicom,simple-phy property as it seems to be of no use
 - used of_get_mac_address() to get MAC address from device tree
 - replaced #ifdef CONFIG_OF around dm9000_parse_dt() with IS_ENABLED

 .../devicetree/bindings/net/davicom-dm9000.txt     | 26 +++++++++++++
 .../devicetree/bindings/vendor-prefixes.txt        |  1 +
 drivers/net/ethernet/davicom/dm9000.c              | 44 ++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/davicom-dm9000.txt

diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
new file mode 100644
index 0000000..653df17
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
@@ -0,0 +1,26 @@
+Davicom DM9000 Fast Ethernet controller
+
+Required properties:
+- compatible = "davicom,dm9000";
+- reg : physical addresses and sizes of registers, must contain 2 entries:
+    first entry : address register,
+    second entry : address register.
+- interrupt-parent : interrupt controller to which the device is connected
+- interrupts : interrupt specifier specific to interrupt controller
+
+Optional properties:
+- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC address
+    to use (from firmware or bootloader)
+- davicom,no-eeprom : Configuration EEPROM is not available
+- davicom,ext-phy : Use external PHY
+
+Example:
+
+	ethernet at 18000000 {
+		compatible = "davicom,dm9000";
+		reg = <0x18000000 0x2 0x18000004 0x2>;
+		interrupt-parent = <&gpn>;
+		interrupts = <7 4>;
+		local-mac-address = [00 00 de ad be ef];
+		davicom,no-eeprom;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c43..2fe74e6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -18,6 +18,7 @@ chrp	Common Hardware Reference Platform
 cirrus	Cirrus Logic, Inc.
 cortina	Cortina Systems, Inc.
 dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
+davicom	DAVICOM Semiconductor, Inc.
 denx	Denx Software Engineering
 emmicro	EM Microelectronic
 epson	Seiko Epson Corp.
diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
index 9105465..8b69586 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -29,6 +29,8 @@
 #include <linux/spinlock.h>
 #include <linux/crc32.h>
 #include <linux/mii.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
 #include <linux/ethtool.h>
 #include <linux/dm9000.h>
 #include <linux/delay.h>
@@ -1358,6 +1360,33 @@ static const struct net_device_ops dm9000_netdev_ops = {
 #endif
 };
 
+static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
+{
+	struct dm9000_plat_data *pdata;
+	struct device_node *np = dev->of_node;
+	const void *mac_addr;
+
+	if (!IS_ENABLED(CONFIG_OF) || !np)
+		return NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata) {
+		dev_err(dev, "failed to allocate platform data struct\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	if (of_find_property(np, "davicom,ext-phy", NULL))
+		pdata->flags |= DM9000_PLATF_EXT_PHY;
+	if (of_find_property(np, "davicom,no-eeprom", NULL))
+		pdata->flags |= DM9000_PLATF_NO_EEPROM;
+
+	mac_addr = of_get_mac_address(np);
+	if (mac_addr)
+		memcpy(pdata->dev_addr, mac_addr, sizeof(pdata->dev_addr));
+
+	return pdata;
+}
+
 /*
  * Search DM9000 board, allocate space and register it
  */
@@ -1373,6 +1402,12 @@ dm9000_probe(struct platform_device *pdev)
 	int i;
 	u32 id_val;
 
+	if (!pdata) {
+		pdata = dm9000_parse_dt(&pdev->dev);
+		if (IS_ERR(pdata))
+			return PTR_ERR(pdata);
+	}
+
 	/* Init network device */
 	ndev = alloc_etherdev(sizeof(struct board_info));
 	if (!ndev)
@@ -1683,11 +1718,20 @@ dm9000_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id dm9000_of_matches[] = {
+	{ .compatible = "davicom,dm9000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dm9000_of_matches);
+#endif
+
 static struct platform_driver dm9000_driver = {
 	.driver	= {
 		.name    = "dm9000",
 		.owner	 = THIS_MODULE,
 		.pm	 = &dm9000_drv_pm_ops,
+		.of_match_table = of_match_ptr(dm9000_of_matches),
 	},
 	.probe   = dm9000_probe,
 	.remove  = dm9000_drv_remove,
-- 
1.8.2.1



From linux at arm.linux.org.uk  Sun May 19 07:25:52 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 19 May 2013 12:25:52 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130517133345.7c1368f5@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
Message-ID: <20130519112552.GR18614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 01:33:45PM +0200, Jean-Francois Moine wrote:
> I quickly compared your dove drm driver and ours (Sebastian and me):
> 
> - CMA helper
> 
>   You don't use DRM_KMS_CMA_HELPER and DRM_GEM_CMA_HELPER which would
>   simplify some code.

Looking at the CMA helper code in DRM, it makes some fundamental errors:

1. It assumes the returned DMA address is a physical address.  This
   is not necessarily the case (there are a number of ARM platforms
   where this is most definitely not true.)  So:

        cma_obj->vaddr = dma_alloc_writecombine(drm->dev, size,
                        &cma_obj->paddr, GFP_KERNEL | __GFP_NOWARN);
...
        ret = remap_pfn_range(vma, vma->vm_start, cma_obj->paddr >> PAGE_SHIFT,
                        vma->vm_end - vma->vm_start, vma->vm_page_prot);

   is extremely broken.

2. If you use the CMA helper, then all your GEM objects must be CMA
   objects.  You can't combine different types of objects (eg, SHM-backed
   objects) with CMA objects.  This will be a massive performance
   regression with GPUs which can handle scatter-gathered SHM objects
   such as the Vivante GPU on the Armada 510.

So, for me, the last point especially is a very strong argument not to
use the DRM CMA helper.  Yes, I could switch to using the DMA coherent/
writecombine allocation API and thus make use of CMA, and that's
something I will be looking at.


From gleb at redhat.com  Sun May 19 08:14:38 2013
From: gleb at redhat.com (Gleb Natapov)
Date: Sun, 19 May 2013 15:14:38 +0300
Subject: [PATCH v3 0/2] ARM: KVM: Moving GIC/timer out of arch/arm
In-Reply-To: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
References: <1368538262-25546-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130519121438.GG4725@redhat.com>

On Tue, May 14, 2013 at 02:31:00PM +0100, Marc Zyngier wrote:
> As KVM/arm64 is looming on the horizon, it makes sense to move some
> of the common code to a single location in order to reduce duplication.
> 
> The code could live anywhere. Actually, most of KVM is already built
> with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
> not exactly talking about style here. But maybe it is time to start
> moving into a less ugly direction.
> 
> The include files must be in a "public" location, as they are accessed
> from non-KVM files (arch/arm/kernel/asm-offsets.c).
> 
> For this purpose, introduce two new locations:
> - virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
>   virt/kvm, so this could be seen as a (very ugly) precedent.
> - include/kvm/  : there is already an include/xen, and while the
>   intent is slightly different, this seems as good a location as
>   any
> 
> A second, tree-wide patch also removes the use of the addprefix used
> to refer to the main KVM code from the arch code, and replace it with
> a KVM variable that does the same thing.
> 
> * From v2:
>   - Fix silly bug breaking compilation on x86...
> 
Applied, thanks.

> Marc Zyngier (2):
>   ARM: KVM: move GIC/timer code to a common location
>   KVM: get rid of $(addprefix ../../../virt/kvm/, ...) in Makefiles
> 
>  arch/arm/include/asm/kvm_host.h                             |  4 ++--
>  arch/arm/kvm/Makefile                                       |  7 ++++---
>  arch/ia64/kvm/Makefile                                      |  7 ++++---
>  arch/powerpc/kvm/Makefile                                   | 13 +++++++------
>  arch/s390/kvm/Makefile                                      |  3 ++-
>  arch/x86/kvm/Makefile                                       | 13 +++++++------
>  .../asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h    |  0
>  arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h   |  0
>  {arch/arm/kvm => virt/kvm/arm}/arch_timer.c                 |  4 ++--
>  {arch/arm/kvm => virt/kvm/arm}/vgic.c                       |  0
>  10 files changed, 28 insertions(+), 23 deletions(-)
>  rename arch/arm/include/asm/kvm_arch_timer.h => include/kvm/arm_arch_timer.h (100%)
>  rename arch/arm/include/asm/kvm_vgic.h => include/kvm/arm_vgic.h (100%)
>  rename {arch/arm/kvm => virt/kvm/arm}/arch_timer.c (99%)
>  rename {arch/arm/kvm => virt/kvm/arm}/vgic.c (100%)
> 
> -- 
> 1.8.2.3
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

--
			Gleb.


From rostedt at goodmis.org  Sun May 19 08:34:04 2013
From: rostedt at goodmis.org (Steven Rostedt)
Date: Sun, 19 May 2013 08:34:04 -0400
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130519093526.GD19883@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
Message-ID: <1368966844.6828.111.camel@gandalf.local.home>

On Sun, 2013-05-19 at 12:35 +0300, Michael S. Tsirkin wrote:

> No, I was not assuming that. What I'm trying to say is that a caller
> that does something like this under a spinlock:
> 	preempt_disable
> 	pagefault_disable
> 	error = copy_to_user
> 	pagefault_enable
> 	preempt_enable_no_resched
> 
> is not doing anything wrong and should not get a warning,
> as long as error is handled correctly later.
> Right?
> 

What I see wrong with the above is the preempt_enable_no_resched(). The
only place that should be ever used is right before a schedule(), as you
don't want to schedule twice (once for the preempt_enable() and then
again for the schedule itself).

Remember, in -rt, a spin lock does not disable preemption.

-- Steve




From sylvester.nawrocki at gmail.com  Sun May 19 09:27:53 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sun, 19 May 2013 15:27:53 +0200
Subject: [PATCH v2] net: dm9000: Allow instantiation using device tree
In-Reply-To: <1368962191-32594-1-git-send-email-tomasz.figa@gmail.com>
References: <1368962191-32594-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <5198D359.5060608@gmail.com>

Hi,

On 05/19/2013 01:16 PM, Tomasz Figa wrote:
> +++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> @@ -0,0 +1,26 @@
> +Davicom DM9000 Fast Ethernet controller
> +
> +Required properties:
> +- compatible = "davicom,dm9000";
> +- reg : physical addresses and sizes of registers, must contain 2 entries:
> +    first entry : address register,
> +    second entry : address register.

Two address registers ? Shouldn't one of these be "data register" ?

> +Example:
> +
> +	ethernet at 18000000 {
> +		compatible = "davicom,dm9000";
> +		reg =<0x18000000 0x2 0x18000004 0x2>;
> +		interrupt-parent =<&gpn>;
> +		interrupts =<7 4>;
> +		local-mac-address = [00 00 de ad be ef];
> +		davicom,no-eeprom;
> +	};

> +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
> +{
> +	struct dm9000_plat_data *pdata;
> +	struct device_node *np = dev->of_node;
> +	const void *mac_addr;
> +
> +	if (!IS_ENABLED(CONFIG_OF) || !np)
> +		return NULL;

Shouldn't ERR_PTR() value be returned here ?

> +	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata) {
> +		dev_err(dev, "failed to allocate platform data struct\n");

There is no need for this error log, k*alloc already logs any failures.

> @@ -1373,6 +1402,12 @@ dm9000_probe(struct platform_device *pdev)
>   	int i;
>   	u32 id_val;
>
> +	if (!pdata) {
> +		pdata = dm9000_parse_dt(&pdev->dev);
> +		if (IS_ERR(pdata))
> +			return PTR_ERR(pdata);
> +	}

Thanks,

Sylwester


From mst at redhat.com  Sun May 19 09:34:18 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Sun, 19 May 2013 16:34:18 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <1368966844.6828.111.camel@gandalf.local.home>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <1368966844.6828.111.camel@gandalf.local.home>
Message-ID: <20130519133418.GA24381@redhat.com>

On Sun, May 19, 2013 at 08:34:04AM -0400, Steven Rostedt wrote:
> On Sun, 2013-05-19 at 12:35 +0300, Michael S. Tsirkin wrote:
> 
> > No, I was not assuming that. What I'm trying to say is that a caller
> > that does something like this under a spinlock:
> > 	preempt_disable
> > 	pagefault_disable
> > 	error = copy_to_user
> > 	pagefault_enable
> > 	preempt_enable_no_resched
> > 
> > is not doing anything wrong and should not get a warning,
> > as long as error is handled correctly later.
> > Right?
> > 
> 
> What I see wrong with the above is the preempt_enable_no_resched(). The
> only place that should be ever used is right before a schedule(), as you
> don't want to schedule twice (once for the preempt_enable() and then
> again for the schedule itself).
> 
> Remember, in -rt, a spin lock does not disable preemption.
> 
> -- Steve

Right but we need to keep it working on upstream as well.
If I do preempt_enable under a spinlock upstream won't it
try to sleep under spinlock?


-- 
MST


From tomasz.figa at gmail.com  Sun May 19 09:41:55 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 19 May 2013 15:41:55 +0200
Subject: [PATCH v2] net: dm9000: Allow instantiation using device tree
In-Reply-To: <5198D359.5060608@gmail.com>
References: <1368962191-32594-1-git-send-email-tomasz.figa@gmail.com>
 <5198D359.5060608@gmail.com>
Message-ID: <15046898.dr5fzcR9ZS@flatron>

Hi Sylwester,

On Sunday 19 of May 2013 15:27:53 Sylwester Nawrocki wrote:
> Hi,
> 
> On 05/19/2013 01:16 PM, Tomasz Figa wrote:
> > +++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
> > @@ -0,0 +1,26 @@
> > +Davicom DM9000 Fast Ethernet controller
> > +
> > +Required properties:
> > +- compatible = "davicom,dm9000";
> > +- reg : physical addresses and sizes of registers, must contain 2
> > entries: +    first entry : address register,
> > +    second entry : address register.
> 
> Two address registers ? Shouldn't one of these be "data register" ?

Oops. I thought I already corrected this typo. Thanks.

> > +Example:
> > +
> > +	ethernet at 18000000 {
> > +		compatible = "davicom,dm9000";
> > +		reg =<0x18000000 0x2 0x18000004 0x2>;
> > +		interrupt-parent =<&gpn>;
> > +		interrupts =<7 4>;
> > +		local-mac-address = [00 00 de ad be ef];
> > +		davicom,no-eeprom;
> > +	};
> > 
> > +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
> > +{
> > +	struct dm9000_plat_data *pdata;
> > +	struct device_node *np = dev->of_node;
> > +	const void *mac_addr;
> > +
> > +	if (!IS_ENABLED(CONFIG_OF) || !np)
> > +		return NULL;
> 
> Shouldn't ERR_PTR() value be returned here ?

Nope. No platform data is a valid case, so no error here.

> > +	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> > +	if (!pdata) {
> > +		dev_err(dev, "failed to allocate platform data struct\n");
> 
> There is no need for this error log, k*alloc already logs any failures.

Hmm. Does it print what allocation exactly failed? (e.g. a backtrace)

Not that it would give anything that could help you in an out of memory 
condition like this, but in general it's good to know in what point the 
failure happened.

Best regards,
Tomasz

> > @@ -1373,6 +1402,12 @@ dm9000_probe(struct platform_device *pdev)
> > 
> >   	int i;
> >   	u32 id_val;
> > 
> > +	if (!pdata) {
> > +		pdata = dm9000_parse_dt(&pdev->dev);
> > +		if (IS_ERR(pdata))
> > +			return PTR_ERR(pdata);
> > +	}
> 
> Thanks,
> 
> Sylwester


From shawn.guo at linaro.org  Sun May 19 10:14:27 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 19 May 2013 22:14:27 +0800
Subject: [PATCH v3 3/4] ARM: dts: add SoC level device tree source for
 MVF600
In-Reply-To: <1368684648-20826-4-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-4-git-send-email-b35083@freescale.com>
Message-ID: <20130519141409.GB18553@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:10:47PM +0800, Jingchang Lu wrote:
> diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi
> new file mode 100644
> index 0000000..a3c3353
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600.dtsi
> @@ -0,0 +1,475 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include "skeleton.dtsi"
> +#include "mvf600-pinfunc.h"
> +#include <dt-bindings/clock/mvf600-clock.h>
> +
> +/ {
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at 0 {
> +			compatible = "arm,cortex-a5";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			next-level-cache = <&L2>;
> +		};
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		sxosc {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +		};
> +
> +		fxosc {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&intc>;
> +		ranges;
> +
> +		aips0: aips-bus at 40000000 {
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-parent = <&intc>;
> +			reg = <0x40000000 0x70000>;
> +			ranges;
> +
> +			mscm: mscm at 40001000 {
> +				compatible = "fsl,mvf600-mscm";
> +				reg = <0x40001000 0x1000>;
> +			};
> +
> +			intc: interrupt-controller at 40002000 {
> +				compatible = "arm,cortex-a9-gic";
> +				#interrupt-cells = <3>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				interrupt-controller;
> +				reg = <0x40003000 0x1000>,
> +				      <0x40002100 0x100>;
> +			};
> +
> +			L2: l2-cache at 40006000 {
> +				compatible = "arm,pl310-cache";
> +				reg = <0x40006000 0x1000>;
> +				cache-unified;
> +				cache-level = <2>;
> +				arm,data-latency = <1 1 1>;
> +				arm,tag-latency = <2 2 2>;
> +			};
> +
> +			uart0: serial at 40027000 {
> +				compatible = "fsl,mvf600-uart","fsl,lpuart";

We generally avoid using generic compatible string for IP block but
prefer to encode SoC name in the string to define the version/revision
using SoC part name.  That said, "fsl,mvf600-uart" is good enough to
specify the IP block.  More on this later.

> +				reg = <0x40027000 0x1000>;
> +				interrupts = <0 61 0x00>;
> +				clocks = <&clks MVF600_CLK_UART0>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart1: serial at 40028000 {
> +				compatible = "fsl,mvf600-uart","fsl,lpuart";
> +				reg = <0x40028000 0x1000>;
> +				interrupts = <0 62 0x04>;
> +				clocks = <&clks MVF600_CLK_UART1>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart2: serial at 40029000 {
> +				compatible = "fsl,mvf600-uart","fsl,lpuart";
> +				reg = <0x40029000 0x1000>;
> +				interrupts = <0 63 0x04>;
> +				clocks = <&clks MVF600_CLK_UART2>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart3: serial at 4002a000 {
> +				compatible = "fsl,mvf600-uart","fsl,lpuart";
> +				reg = <0x4002a000 0x1000>;
> +				interrupts = <0 64 0x04>;
> +				clocks = <&clks MVF600_CLK_UART3>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			sai2: sai at 40031000 {
> +				compatible = "fsl,mvf600-sai";
> +				reg = <0x40031000 0x1000>;
> +				interrupts = <0 86 0x04>;
> +				clocks = <&clks MVF600_CLK_SAI2>;
> +				clock-names = "sai";
> +				status = "disabled";
> +			};
> +
> +			pit:pit at 40037000 {

Nit: put a space after "pit:".

> +				compatible = "fsl,mvf600-pit";
> +				reg = <0x40037000 0x1000>;
> +				interrupts = <0 39 0x04>;
> +				clock-names = "pit";
> +				clocks = <&clks MVF600_CLK_PIT>;

Nit: I've seen some nodes have "clock-names" before "clocks" and others
have it after "clocks".  Please be consistent.

> +			};
> +
> +			wdog at 4003e000 {
> +				compatible = "fsl,mvf600-wdt","fsl,imx21-wdt";

Nit: please have a space between two strings (after comma).

> +				reg = <0x4003e000 0x1000>;
> +				clock-names = "wdog";
> +				clocks = <&clks MVF600_CLK_WDT>;
> +			};
> +
> +			qspi0: quadspi at 40044000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,mvf600-qspi";
> +				reg = <0x40044000 0x1000>;
> +				interrupts = <0 24 0x04>;
> +				clocks = <&clks MVF600_CLK_QSPI0_EN>,
> +					<&clks MVF600_CLK_QSPI0>;
> +				clock-names = "qspi0_en", "qspi0";
> +				status = "disabled";
> +			};
> +
> +			iomuxc: iomuxc at 40048000 {
> +				compatible = "fsl,mvf600-iomuxc";
> +				reg = <0x40048000 0x1000>;
> +				#gpio-range-cells = <2>;
> +
> +				/* functions and groups pins */
> +
> +				dcu0 {
> +					pinctrl_dcu0_1: dcu0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB8__GPIO_30	0x42
> +						MVF600_PAD_PTE0__DCU0_HSYNC	0x42
> +						MVF600_PAD_PTE1__DCU0_VSYNC	0x42
> +						MVF600_PAD_PTE2__DCU0_PCLK	0x42
> +						MVF600_PAD_PTE4__DCU0_DE	0x42
> +						MVF600_PAD_PTE5__DCU0_R0	0x42
> +						MVF600_PAD_PTE6__DCU0_R1	0x42
> +						MVF600_PAD_PTE7__DCU0_R2	0x42
> +						MVF600_PAD_PTE8__DCU0_R3	0x42
> +						MVF600_PAD_PTE9__DCU0_R4	0x42
> +						MVF600_PAD_PTE10__DCU0_R5	0x42
> +						MVF600_PAD_PTE11__DCU0_R6	0x42
> +						MVF600_PAD_PTE12__DCU0_R7	0x42
> +						MVF600_PAD_PTE13__DCU0_G0	0x42
> +						MVF600_PAD_PTE14__DCU0_G1	0x42
> +						MVF600_PAD_PTE15__DCU0_G2	0x42
> +						MVF600_PAD_PTE16__DCU0_G3	0x42
> +						MVF600_PAD_PTE17__DCU0_G4	0x42
> +						MVF600_PAD_PTE18__DCU0_G5	0x42
> +						MVF600_PAD_PTE19__DCU0_G6	0x42
> +						MVF600_PAD_PTE20__DCU0_G7	0x42
> +						MVF600_PAD_PTE21__DCU0_B0	0x42
> +						MVF600_PAD_PTE22__DCU0_B1	0x42
> +						MVF600_PAD_PTE23__DCU0_B2	0x42
> +						MVF600_PAD_PTE24__DCU0_B3	0x42
> +						MVF600_PAD_PTE25__DCU0_B4	0x42
> +						MVF600_PAD_PTE26__DCU0_B5	0x42
> +						MVF600_PAD_PTE27__DCU0_B6	0x42
> +						MVF600_PAD_PTE28__DCU0_B7	0x42
> +						>;
> +					};
> +				};
> +
> +				dspi0 {
> +					pinctrl_dspi0_1: dspi0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB19__DSPI0_CS0	0x1182
> +						MVF600_PAD_PTB20__DSPI0_SIN	0x1181
> +						MVF600_PAD_PTB21__DSPI0_SOUT	0x1182
> +						MVF600_PAD_PTB22__DSPI0_SCK	0x1182
> +						>;
> +					};
> +				};
> +
> +				esdhc1 {
> +					pinctrl_esdhc1_1: esdhc1grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA24__ESDHC1_CLK	0x31ef
> +						MVF600_PAD_PTA25__ESDHC1_CMD	0x31ef
> +						MVF600_PAD_PTA26__ESDHC1_DAT0	0x31ef
> +						MVF600_PAD_PTA27__ESDHC1_DAT1	0x31ef
> +						MVF600_PAD_PTA28__ESDHC1_DATA2	0x31ef
> +						MVF600_PAD_PTA29__ESDHC1_DAT3	0x31ef
> +						MVF600_PAD_PTA7__GPIO_134	0x219d
> +						>;
> +					};
> +				};
> +
> +				fec0 {
> +					pinctrl_fec0_1: fec0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA6__RMII_CLKIN		0x30d1
> +						MVF600_PAD_PTC0__ENET_RMII0_MDC		0x30d3
> +						MVF600_PAD_PTC1__ENET_RMII0_MDIO	0x30d1
> +						MVF600_PAD_PTC2__ENET_RMII0_CRS		0x30d1
> +						MVF600_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
> +						MVF600_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
> +						MVF600_PAD_PTC5__ENET_RMII0_RXER	0x30d1
> +						MVF600_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
> +						MVF600_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
> +						MVF600_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
> +						>;
> +					};
> +				};
> +
> +				fec1 {
> +					pinctrl_fec1_1: fec1grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTC9__ENET_RMII1_MDC		0x30d2
> +						MVF600_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
> +						MVF600_PAD_PTC11__ENET_RMII1_CRS	0x30d1
> +						MVF600_PAD_PTC12__ENET_RMII_RXD1	0x30d1
> +						MVF600_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
> +						MVF600_PAD_PTC14__ENET_RMII1_RXER	0x30d1
> +						MVF600_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
> +						MVF600_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
> +						MVF600_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
> +						>;
> +					};
> +				};
> +
> +				i2c0 {
> +					pinctrl_i2c0_1: i2c0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB14__I2C0_SCL	0x30d3
> +						MVF600_PAD_PTB15__I2C0_SDA	0x30d3
> +						>;
> +					};
> +				};
> +
> +				pwm0 {
> +					pinctrl_pwm0_1: pwm0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB0__FTM0_CH0	0x1582
> +						MVF600_PAD_PTB1__FTM0_CH1	0x1582
> +						MVF600_PAD_PTB2__FTM0_CH2	0x1582
> +						MVF600_PAD_PTB3__FTM0_CH3	0x1582
> +						MVF600_PAD_PTB6__FTM0_CH6	0x1582
> +						MVF600_PAD_PTB7__FTM0_CH7	0x1582
> +						>;
> +					};
> +				};
> +
> +				qspi0 {
> +					pinctrl_qspi0_1: qspi0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTD0__QSPI0_A_QSCK	0x307b
> +						MVF600_PAD_PTD1__QSPI0_A_CS0	0x307f
> +						MVF600_PAD_PTD2__QSPI0_A_DATA3	0x3073
> +						MVF600_PAD_PTD3__QSPI0_A_DATA2	0x3073
> +						MVF600_PAD_PTD4__QSPI0_A_DATA1	0x3073
> +						MVF600_PAD_PTD5__QSPI0_A_DATA0	0x307b
> +						MVF600_PAD_PTD7__QSPI0_B_QSCK	0x307b
> +						MVF600_PAD_PTD8__QSPI0_B_CS0	0x307f
> +						MVF600_PAD_PTD9__QSPI0_B_DATA3	0x3073
> +						MVF600_PAD_PTD10__QSPI0_B_DATA2	0x3073
> +						MVF600_PAD_PTD11__QSPI0_B_DATA1	0x3073
> +						MVF600_PAD_PTD12__QSPI0_B_DATA0	0x307b
> +						>;
> +					};
> +				};
> +
> +				sai2 {
> +					pinctrl_sai2_1: sai2grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA16__SAI2_TX_BCLK		0x02ed
> +						MVF600_PAD_PTA18__SAI2_TX_DATA		0x02ee
> +						MVF600_PAD_PTA19__SAI2_TX_SYNC		0x02ed
> +						MVF600_PAD_PTA21__SAI2_RX_BCLK		0x02ed
> +						MVF600_PAD_PTA22__SAI2_RX_DATA		0x02ed
> +						MVF600_PAD_PTA23__SAI2_RX_SYNC		0x02ed
> +						MVF600_PAD_PTB18__EXT_AUDIO_MCLK	0x02ed
> +						>;
> +					};
> +				};
> +
> +				touchscreen0 {
> +					pinctrl_ts0_1: ts0grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA31__GPIO_21	0x219d
> +						>;
> +					};
> +				};

The pin group represented in <soc>.dtsi should be those defined by SoC
design.  This group does not look like the case.

> +
> +				uart1 {
> +					pinctrl_uart1_1: uart1grp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTB4__UART1_TX(0x21a2)
> +						MVF600_PAD_PTB5__UART1_RX(0x21a1)

Something forgot to change from last version.

> +						>;
> +					};
> +				};
> +
> +				usbvbus {
> +					pinctrl_usbvbus_1: usbvbusgrp_1 {
> +						fsl,pins = <
> +						MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c)
> +						MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c)

Ditto

> +						>;
> +					};
> +				};
> +
> +			};
> +
> +			gpio1: gpio at 40049000 {
> +				compatible = "fsl,mvf600-gpio";
> +				reg = <0x40049000 0x1000 0x400ff000 0x40>;
> +				interrupts = <0 107 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 0 32>;
> +			};
> +
> +			gpio2: gpio at 4004a000 {
> +				compatible = "fsl,mvf600-gpio";
> +				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
> +				interrupts = <0 108 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 32 32>;
> +			};
> +
> +			gpio3: gpio at 4004b000 {
> +				compatible = "fsl,mvf600-gpio";
> +				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
> +				interrupts = <0 109 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 64 32>;
> +			};
> +
> +			gpio4: gpio at 4004c000 {
> +				compatible = "fsl,mvf600-gpio";
> +				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
> +				interrupts = <0 110 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 96 32>;
> +			};
> +
> +			gpio5: gpio at 4004d000 {
> +				compatible = "fsl,mvf600-gpio";
> +				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
> +				interrupts = <0 111 0x04>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				gpio-ranges = <&iomuxc 128 7>;
> +			};
> +
> +			anatop at 40050000 {
> +				compatible = "fsl,mvf600-anatop";
> +				reg = <0x40050000 0x1000>;
> +			};
> +
> +			i2c0: i2c at 40066000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,mvf600-i2c";
> +				reg = <0x40066000 0x1000>;
> +				interrupts =<0 71 0x04>;
> +				clocks = <&clks MVF600_CLK_I2C0>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			clks: ccm at 4006b000 {
> +				compatible = "fsl,mvf600-ccm";
> +				reg = <0x4006b000 0x1000>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +
> +		aips1: aips-bus at 40080000 {
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x40080000 0x80000>;
> +			ranges;
> +
> +			uart4: serial at 400a9000 {
> +				compatible = "fsl,mvf600-uart","fsl,lpuart";
> +				reg = <0x400a9000 0x1000>;
> +				interrupts = <0 65 0x04>;
> +				clocks = <&clks MVF600_CLK_UART4>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			uart5: serial at 400aa000 {
> +				compatible = "fsl,mvf600-uart","fsl,lpuart";
> +				reg = <0x400aa000 0x1000>;
> +				interrupts = <0 66 0x04>;
> +				clocks = <&clks MVF600_CLK_UART5>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			fec0: ethernet at 400d0000 {
> +				compatible = "fsl,mvf600-fec","fsl,mvf-fec";

"fsl,mvf-fec" is not a good compatible string.  I will try to send a
patch to change fec driver on this.

Shawn

> +				reg = <0x400d0000 0x1000>;
> +				interrupts = <0 78 0x04>;
> +				clocks = <&clks MVF600_CLK_ENET>,
> +					<&clks MVF600_CLK_ENET>,
> +					<&clks MVF600_CLK_ENET>;
> +				clock-names = "ipg", "ahb", "ptp";
> +			};
> +
> +			fec1: ethernet at 400d1000 {
> +				compatible = "fsl,mvf600-fec","fsl,mvf-fec";
> +				reg = <0x400d1000 0x1000>;
> +				interrupts = <0 79 0x04>;
> +				clocks = <&clks MVF600_CLK_ENET>,
> +					<&clks MVF600_CLK_ENET>,
> +					<&clks MVF600_CLK_ENET>;
> +				clock-names = "ipg", "ahb", "ptp";
> +			};
> +		};
> +	};
> +};
> -- 
> 1.8.0
> 
> 



From maxime.ripard at free-electrons.com  Sun May 19 11:13:14 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 19 May 2013 17:13:14 +0200
Subject: [PATCH 0/4] ARM: Remove boilerplate debug_ll_io_init code
In-Reply-To: <201305171531.16240.arnd@arndb.de>
References: <1368440169-29088-1-git-send-email-maxime.ripard@free-electrons.com>
 <201305160040.54399.arnd@arndb.de>
 <5194F944.2040803@free-electrons.com>
 <201305171531.16240.arnd@arndb.de>
Message-ID: <20130519151314.GA7717@lukather>

Hi Arnd,

On Fri, May 17, 2013 at 03:31:16PM +0200, Arnd Bergmann wrote:
> On Thursday 16 May 2013, Maxime Ripard wrote:
> 
> > 
> > How will we merge this? The first patch would be merged by Russel and
> > the 3 others by their respective maintainers?
> 
> I think since it's mostly platform code and all trivial, we can merge
> it into the next/cleanup branch in arm-soc directly.

Ok, then I can probably merge it into the branch with the irqchip_init
patches and send both these cleanups into the same branch in a few
weeks?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Sun May 19 11:22:40 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 19 May 2013 17:22:40 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <5197B82F.8010809@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <51969EA9.1060602@free-electrons.com>
 <5197B82F.8010809@schinagl.nl>
Message-ID: <20130519152240.GB7717@lukather>

On Sat, May 18, 2013 at 07:19:43PM +0200, Oliver Schinagl wrote:
> On 05/17/13 23:18, Maxime Ripard wrote:
> >Hi Oliver,
> >
> >Le 17/05/2013 15:35, Oliver Schinagl a ?crit :
> >>From: Oliver Schinagl <oliver at schinagl.nl>
> >>
> >>Allwinner has electric fuses (efuse) on their line of chips. This driver
> >>reads those fuses and exports them as a sysfs node. Also a symbol is exported
> >>for in-kernel useage.
> >>
> >>While initially these fuses are used to somewhat determin the chipID, these
> >>appear to be writeable by the user and thus can be used for other purpouses.
> >>For example storing a 128 bit root key, a unique serial number, which could
> >>then even be used as a MAC address.
> >>
> >>Because writing to e-fuses can be potentially dangerous, and are certainly
> >>not as often writable (if at all) as flash memory, these shouldn't be easily
> >>changeable, hence only a read-only mode. An offline tool to write the fuses
> >>is in the works.
> >>
> >>Currently supported are the following known chips:
> >>Allwinner sun4i (A10)
> >>Allwinner sun5i (A10s A13)
> >>Allwinner sun6i (A31, A31s)
> >>Allwinner sun7i (A20)
> >
> >Since I don't think those patches have been tested on sun6i/sun7i, and
> >that there's not even kernel support for those, maybe it's not worth
> >mentionning them?
> A31 is out in the wild, but haven't seen that functionality in, I
> have seen the register named and defined, just not used, so that
> could go until confirmed.
> 
> A20 has the same feature as we can see in the dumped sources. [0]

Yet, we can't even boot a mainline kernel, and this list will probably
need some update when new SoCs come out.

Anyway, it's not a big deal.

> 
> 
> >
> >>
> >>Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
> >>---
> >>  drivers/misc/eeprom/Kconfig     |  19 ++++
> >>  drivers/misc/eeprom/Makefile    |   1 +
> >>  drivers/misc/eeprom/sunxi_sid.c | 218 ++++++++++++++++++++++++++++++++++++++++
> >>  3 files changed, 238 insertions(+)
> >>  create mode 100644 drivers/misc/eeprom/sunxi_sid.c
> >>
> >>diff --git a/drivers/misc/eeprom/Kconfig b/drivers/misc/eeprom/Kconfig
> >>index 04f2e1f..c9ddda5 100644
> >>--- a/drivers/misc/eeprom/Kconfig
> >>+++ b/drivers/misc/eeprom/Kconfig
> >>@@ -96,4 +96,23 @@ config EEPROM_DIGSY_MTC_CFG
> >>
> >>  	  If unsure, say N.
> >>
> >>+config EEPROM_SUNXI_SID
> >>+	tristate "Allwinner sunxi security ID support"
> >>+	depends on ARCH_SUNXI && SYSFS
> >>+	help
> >>+	  This is a driver for the 'security ID' available on various Allwinner
> >>+	  devices. Currently supported are:
> >>+		sun4i (A10)
> >>+		sun5i (A10s, A12, A13)
> >>+		sun6i (A31)
> >>+		sun7i (A20)
> >
> >Same things here.
> >
> >>+
> >>+	  Due to the potential risks involved with changing e-fuses,
> >>+	  this driver is read-only
> >>+
> >>+	  For more information visit http://linux-sunxi.org/SID
> >>+
> >>+	  This driver can also be built as a module. If so, the module
> >>+	  will be called sunxi_sid.
> >>+
> >>  endmenu
> >>diff --git a/drivers/misc/eeprom/Makefile b/drivers/misc/eeprom/Makefile
> >>index fc1e81d..9507aec 100644
> >>--- a/drivers/misc/eeprom/Makefile
> >>+++ b/drivers/misc/eeprom/Makefile
> >>@@ -4,4 +4,5 @@ obj-$(CONFIG_EEPROM_LEGACY)	+= eeprom.o
> >>  obj-$(CONFIG_EEPROM_MAX6875)	+= max6875.o
> >>  obj-$(CONFIG_EEPROM_93CX6)	+= eeprom_93cx6.o
> >>  obj-$(CONFIG_EEPROM_93XX46)	+= eeprom_93xx46.o
> >>+obj-$(CONFIG_EEPROM_SUNXI_SID)	+= sunxi_sid.o
> >>  obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o
> >>diff --git a/drivers/misc/eeprom/sunxi_sid.c b/drivers/misc/eeprom/sunxi_sid.c
> >>new file mode 100644
> >>index 0000000..953f137
> >>--- /dev/null
> >>+++ b/drivers/misc/eeprom/sunxi_sid.c
> >>@@ -0,0 +1,218 @@
> >>+/*
> >>+ * Copyright (c) 2013 Oliver Schinagl
> >>+ * http://www.linux-sunxi.org
> >>+ *
> >>+ * Oliver Schinagl <oliver at schinagl.nl>
> >>+ *
> >>+ * This program is free software; you can redistribute it and/or modify
> >>+ * it under the terms of the GNU General Public License as published by
> >>+ * the Free Software Foundation; either version 2 of the License, or
> >>+ * (at your option) any later version.
> >>+ *
> >>+ * This program is distributed in the hope that it will be useful,
> >>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >>+ * GNU General Public License for more details.
> >>+ *
> >>+ * This driver exposes the Allwinner security ID, a 128 bit eeprom, in chunks
> >>+ * of 8 bytes.
> >
> >16 bytes or 8 bits? because 8 bytes != 128 bits.
> fixed, it was late when I wrote that :( It is indeed 8 bits, e.g.
> byte sized chunks.
> 
> >
> >>+ */
> >>+
> >>+#include <linux/compiler.h>
> >>+#include <linux/device.h>
> >>+#include <linux/errno.h>
> >>+#include <linux/export.h>
> >>+#include <linux/fs.h>
> >>+#include <linux/init.h>
> >>+#include <linux/io.h>
> >>+#include <linux/kobject.h>
> >>+#include <linux/module.h>
> >>+#include <linux/of_address.h>
> >>+#include <linux/platform_device.h>
> >>+#include <linux/stat.h>
> >>+#include <linux/sysfs.h>
> >>+#include <linux/types.h>
> >>+
> >>+
> >>+#define DRV_NAME "sunxi-sid"
> >>+#define DRV_VERSION "1.0"
> >>+
> >>+/* Register offsets */
> >>+#define SUNXI_SID_KEY0 0x00
> >>+#define SUNXI_SID_KEY1 0x04
> >>+#define SUNXI_SID_KEY2 0x08
> >>+#define SUNXI_SID_KEY3 0x0c
> >>+
> >>+/* There are 4 32-bit keys */
> >>+#define SUNXI_SID_KEYS 4
> >>+/* and 4 32-bit keys per 32-bit key */
> >
> >The comment is wrong here.
> Same as above, corrected.
> 
> >
> >>+#define SUNXI_SID_SIZE (SUNXI_SID_KEYS * 4)
> >>+
> >>+#if (SUNXI_SID_SIZE > PAGE_SIZE)
> >>+#error "SUNXI_SID_SIZE is larger then the target's PAGE_SIZE, ENOMEM."
> >>+#endif
> >
> >Hmmmm, I don't follow you here, what's the relation between your driver
> >and PAGE_SIZE?
> Nothing, I thought there was, but isn't. removed.
> >
> >>+
> >>+static u8 keys_lut[] = {
> >>+	SUNXI_SID_KEY0,
> >>+	SUNXI_SID_KEY1,
> >>+	SUNXI_SID_KEY2,
> >>+	SUNXI_SID_KEY3,
> >>+};
> >>+
> >>+struct sid_priv {
> >>+	void __iomem *sid_base;
> >>+};
> >>+
> >>+struct sid_priv *p;
> >
> >What's the point of having a structure here? And why putting a global
> >value, !static, with a generic name, while you could have an
> >instance-specific one?
> Forgot the static keyword, and the struct kept on shrinking until
> only the base address was left. I guess memory wise it shouldn't
> make a difference, but the compiler also doesn't agree, so gone it
> is :)
> >
> >struct file has a private_data field, use it.
> But since we don't 'open' it, we can't use that, as we talked on IRC.

Then, use the passed kobject to retrieve its parent device structure,
and from there, get the drvdata to get back on your feet.

Actually, you already seem to do that and I overlooked that part in my
previous review.

So just use the priv structure you have defined in your read function
and that is useless right now.

> >
> >>+
> >>+
> >>+/* We read the entire key, using a look up table. Returned is only the
> >>+ * requested byte. This is of course slower then it could be and uses 4 times
> >>+ * more reads as needed but keeps code a little simpler.
> >>+ */
> >>+u8 sunxi_sid_read_byte(const int key)
> >>+{
> >>+	u32 sid_key;
> >>+	u8 ret;
> >>+
> >>+	ret = 0;
> >>+	if (likely((key <= SUNXI_SID_SIZE))) {
> >>+		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
> >>+		switch (key % 4) {
> >>+		case 0:
> >>+			ret = (sid_key >> 24) & 0xff;
> >>+			break;
> >>+		case 1:
> >>+			ret = (sid_key >> 16) & 0xff;
> >>+			break;
> >>+		case 2:
> >>+			ret = (sid_key >> 8) & 0xff;
> >>+			break;
> >>+		case 3:
> >>+			ret = sid_key & 0xff;
> >>+			break;
> >>+		}
> >>+	}
> >
> >Come on, you can do better. This lookup table is useless.
> I didn't want to depend on the fixed layout of memory, but consider
> it removed.
> >
> >Also, why the first key is the one with the MSBs?
> >I'd expect that the key 0 is the one holding the LSBs.
> Strangely enough, they have swapped the MSB and LSB bytes. I double
> checked it with u-boot and yep, swapped. Though in the end, if we
> write stuff there and we read stuff from there, order doesn't
> matter? So what do we prefer. Have it so that it makes sense and
> ignore how u-boot reads it, or correct it and be consistent?

Which u-boot are you talking about?
I'd really prefer to have a sane and logical behaviour rather than a
broken one, even though it used to be like that in the
Allwinner-provided kernel.

> >
> >>+
> >>+	return ret;
> >>+}
> >>+
> >>+static ssize_t sid_read(struct file *fd, struct kobject *kobj,
> >>+			struct bin_attribute *attr, char *buf,
> >>+			loff_t pos, size_t size)
> >>+{
> >>+	ssize_t ret;
> >>+	struct device *dev;
> >>+	struct sid_priv *priv;
> >>+	int i;
> >>+
> >>+	ret = -EPERM;
> >>+	dev = kobj_to_dev(kobj);
> >>+	priv = dev_get_drvdata(dev);
> >>+
> >>+	if ((likely(size > 0)) && ((size + pos) <= SUNXI_SID_SIZE)) {
> >>+		for (i = 0; i < size; i++) {
> >>+			buf[i] = sunxi_sid_read_byte(pos + i);
> >>+		}
> >>+		if (i < PAGE_SIZE) {
> >>+			buf[i] = '\0';
> >>+			ret = (ssize_t)size;
> >>+		} else {
> >>+			ret = -ENOMEM;
> >>+		}
> >
> >Hmmmm, what? Why returning \0 here? It's not a string, it's binary data.
> >What's the relation with PAGE_SIZE again?
> I thought that buf is at most PAGE_SIZE large [1] "sysfs allocates a
> buffer of size (PAGE_SIZE) and passes it to the method."

And you already check the size passed.

> >
> >Just return the number of bytes read, that's it.
> Yes, had forgotten that this was of course the binary read function
> and not the text version. So yeah, in the binary case, gone.
> >
> >>+	} else {
> >>+		buf[0] = '\0';
> >>+		ret = 0;
> >>+	}
> >>+
> >>+	return ret;
> >>+}
> >>+
> >>+static struct of_device_id sid_of_match[] = {
> >>+	{
> >>+		.compatible = "allwinner,sun4i-sid",
> >>+	},
> >>+	{/* sentinel */}
> >>+};
> >>+MODULE_DEVICE_TABLE(of, sid_of_match);
> >>+
> >>+static struct bin_attribute sid_bin_attr = {
> >>+	.attr = {
> >>+		.name = "key",
> >>+		.mode = S_IRUGO,
> >>+	},
> >>+	.size = SUNXI_SID_SIZE,
> >>+	.read = sid_read,
> >>+};
> >>+
> >>+static int sid_remove(struct platform_device *pdev)
> >>+{
> >>+	struct device *dev = &pdev->dev;
> >>+	struct sid_priv *priv;
> >>+
> >>+	priv = dev_get_drvdata(dev);
> >>+	device_remove_bin_file(dev, &sid_bin_attr);
> >>+	iounmap(priv->sid_base);
> >>+	devm_kfree(dev, priv);
> >>+	return 0;
> >>+}
> >>+
> >>+static int __init sid_probe(struct platform_device *pdev)
> >>+{
> >>+	int ret;
> >>+	struct device *dev = &pdev->dev;
> >>+	struct sid_priv *priv;
> >>+
> >>+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> >>+	p = priv;
> >>+
> >>+	dev_set_drvdata(dev, priv);
> >>+
> >>+	if (!priv) {
> >>+		dev_err(dev, "Unable to allocate device private data\n");
> >>+		ret = -ENOMEM;
> >>+		goto exit;
> >>+	}
> >
> >Isn't it a bit weird to check for the memory allocation after using the
> Yes, more 'oops'. Re-arranged.
> >variable. Also, you don't really need the dev_err, since if the kernel
> >fails to allocate some memory, it will tell you anyway.
> I had it there mostly for consistency, the other 2 did the same
> check. Initially I had 5 functions here, but you corrected me on
> that :)
> 
> >
> >>+	priv->sid_base = of_iomap(dev->of_node, 0);
> >>+	if (!priv->sid_base) {
> >>+		dev_err(dev, "Unable to map memory region\n");
> >>+		ret = -ENOMEM;
> >>+		goto exit_free;
> >>+	}
> >>+
> >>+	ret = device_create_bin_file(dev, &sid_bin_attr);
> >>+	if (ret) {
> >>+		dev_err(dev, "Unable to create sysfs bin entry\n");
> >>+		goto exit_unmap;
> >>+	}
> >
> >Hmmm, maybe it's not worth all these gotos just for an iounmap, I'd
> >probably return right away, but that's your call.
> I saw a lot of drivers do the goto: dance in init/probe/exit/remove
> functions, I don't think the overhead here would be so bad?

It's not really that it's bad, but using return directly would take less
code overall, but that's not a big deal, if you prefer to keep it that
way, I'm fine with it.

> >
> >>+	dev_info(dev, "Sunxi security ID driver loaded successfully.\n");
> >>+
> >>+	return 0;
> >>+
> >>+
> >>+exit_unmap:
> >>+	iounmap(priv->sid_base);
> >>+exit_free:
> >>+	devm_kfree(dev, priv);
> >>+exit:
> >>+	return ret;
> >>+}
> >>+
> >>+static struct platform_driver sid_driver = {
> >>+	.probe = sid_probe,
> >>+	.remove = sid_remove,
> >>+	.driver = {
> >>+		.name = DRV_NAME,
> >>+		.owner = THIS_MODULE,
> >>+		.of_match_table = sid_of_match,
> >>+	},
> >>+};
> >>+module_platform_driver(sid_driver);
> >>+
> >>+
> >>+MODULE_AUTHOR("Oliver Schinagl <oliver at schinagl.nl>");
> >>+MODULE_DESCRIPTION("Allwinner sunxi security id driver");
> >>+MODULE_VERSION(DRV_VERSION);
> >>+MODULE_LICENSE("GPL");
> >>
> >
> >Thanks for this driver!
> >Maxime
> >
> You are welcome! :D While awaiting more feedback, i've pushed the
> current version to my github [2].
> 
> Oliver
> 
> [0] https://github.com/amery/linux-allwinner/blob/lichee-3.3/sun7i-dev/arch/arm/mach-sun7i/security_id.c#L91
> [1] https://www.kernel.org/doc/Documentation/filesystems/sysfs.txt
> [2] https://github.com/oliv3r/linux/blob/wip/sunxi-security-id/drivers/misc/eeprom/sunxi_sid.c

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From shawn.guo at linaro.org  Sun May 19 11:29:34 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 19 May 2013 23:29:34 +0800
Subject: [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts
 support
In-Reply-To: <1368684648-20826-5-git-send-email-b35083@freescale.com>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-5-git-send-email-b35083@freescale.com>
Message-ID: <20130519152932.GA24301@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:10:48PM +0800, Jingchang Lu wrote:
> Add initial MVF600 Tower board  support with uart, fec,
> i2c, qspi, and sai enabled.
> 
> Signed-off-by: Xiaochun Li <b41219 at freescale.com>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   split DTS support to SoC and board patches.
>   sort node by alphabet order of labels.
> 
>  arch/arm/boot/dts/Makefile       |   3 +-
>  arch/arm/boot/dts/mvf600-twr.dts | 108 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 110 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 87e603c..968164b 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -122,7 +122,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
>  	imx6q-sabrelite.dtb \
>  	imx6q-sabresd.dtb \
>  	imx6q-sbc6x.dtb \
> -	imx6sl-evk.dtb
> +	imx6sl-evk.dtb \
> +	mvf600-twr.dtb
>  dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
>  	imx23-olinuxino.dtb \
>  	imx23-stmp378x_devb.dtb \
> diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts
> new file mode 100644
> index 0000000..fe2e0e6
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600-twr.dts
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +/dts-v1/;
> +#include "mvf600.dtsi"
> +
> +/ {
> +	model = "MVF600 Tower Board";
> +	compatible = "fsl,mvf600-twr", "fsl,mvf600";
> +
> +	chosen {
> +		bootargs = "console=ttyLP1,115200";
> +	};
> +
> +	memory {
> +		reg = <0x80000000 0x8000000>;
> +	};
> +
> +	clocks {
> +		audio_ext {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24576000>;
> +		};
> +
> +		enet_ext {
> +			compatible = "fixed-clock";
> +			clock-frequency = <50000000>;
> +		};
> +	};
> +
> +	sound {
> +		compatible = "fsl,mvf600-audio-sgtl5000";
> +		model = "mvf600-sgtl5000";
> +		sai-controller = <&sai2>;
> +		audio-codec = <&codec>;
> +		audio-routing =
> +			"MIC_IN", "Mic Jack",
> +			"Mic Jack", "Mic Bias",
> +			"Headphone Jack", "HP_OUT";
> +	};

Has this been tested against mainline kernel?  If not, please remove it.

> +
> +};
> +
> +&fec0 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec0_1>;
> +};
> +
> +&fec1 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1_1>;
> +};

For the peripherals where the availability can be a decision of board
designers, we generally disable them in <soc>.dtsi by default with
status = "disabled", and only enable them on boards where they are
available in <board>.dts with status = "okay".

One way to judge this type of peripherals could be seeing if they will
need to have their pins routed on boards to function.

> +
> +&i2c0 {
> +	status = "okay";

We generally put status at the end of property list of a node.

> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c0_1>;
> +
> +	codec: sgtl5000 at 0a {
> +		compatible = "fsl,sgtl5000";
> +		reg = <0x0a>;
> +		clocks = <&clks MVF600_CLK_SAI2>;

The sgtl5000 uses SAI2 clock?

> +	};
> +};

Is i2c-imx driver working for mvf600 right now?

> +
> +&qspi0 { /* QuadSPI0 */
> +	fsl,spi-num-chipselects = <1>;
> +	fsl,spi-flash-chipselects = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_qspi0_1>;
> +	status = "okay";
> +
> +	flash: s25fl128s at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "spansion,s25fl128s";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +		linux,modalias = "m25p80";
> +		modal = "s25fl128s";
> +		partition at 0 {
> +			label = "s25fl128s";
> +			reg = <0x0 0x1000000>;
> +		};
> +	};
> +};

Do we have a QuadSPI driver on mainline kernel?  Please only add it when
it's been tested against mainline kernel.

> +
> +&sai2 {
> +	fsl,mode = "i2s-slave";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sai2_1>;
> +	status = "okay";
> +};

Ditto

Shawn

> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1_1>;
> +	status = "okay";
> +};
> -- 
> 1.8.0
> 
> 



From maxime.ripard at free-electrons.com  Sun May 19 11:32:35 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 19 May 2013 17:32:35 +0200
Subject: [PATCH v2] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <1368903956-32388-1-git-send-email-carlo.caione@gmail.com>
References: <1368903956-32388-1-git-send-email-carlo.caione@gmail.com>
Message-ID: <20130519153235.GC7717@lukather>

Hi Carlo,

On Sat, May 18, 2013 at 09:05:56PM +0200, Carlo Caione wrote:
> This patch adds the driver for the watchdog found in the Allwinner A10 and
> A13 SoCs. It has DT-support and uses the new watchdog framework.
> 
> Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
> ---
>  drivers/watchdog/Kconfig     |  10 ++
>  drivers/watchdog/Makefile    |   1 +
>  drivers/watchdog/sunxi_wdt.c | 226 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 237 insertions(+)
>  create mode 100644 drivers/watchdog/sunxi_wdt.c
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index e89fc31..8ad2238 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -299,6 +299,16 @@ config ORION_WATCHDOG
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called orion_wdt.
>  
> +config SUNXI_WATCHDOG
> +	tristate "Allwinner SoCs watchdog support"
> +	depends on ARCH_SUNXI
> +	select WATCHDOG_CORE
> +	help
> +	  Say Y here to include support for the watchdog timer
> +	  in Allwinner SoCs.
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called sunxi_wdt.
> +
>  config COH901327_WATCHDOG
>  	bool "ST-Ericsson COH 901 327 watchdog"
>  	depends on ARCH_U300
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index a300b94..5012d5f 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
>  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
>  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
>  obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
> +obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
>  obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
>  obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
>  obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
> diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
> new file mode 100644
> index 0000000..105b26a
> --- /dev/null
> +++ b/drivers/watchdog/sunxi_wdt.c
> @@ -0,0 +1,226 @@
> +/*
> + *      sunxi Watchdog Driver
> + *
> + *      Copyright (c) 2013 Carlo Caione
> + *                    2012 Henrik Nordstrom
> + *
> + *      This program is free software; you can redistribute it and/or
> + *      modify it under the terms of the GNU General Public License
> + *      as published by the Free Software Foundation; either version
> + *      2 of the License, or (at your option) any later version.
> + *
> + *      Based on xen_wdt.c
> + *      (c) Copyright 2010 Novell, Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +#include <linux/watchdog.h>
> +
> +#define WDT_MAX_TIMEOUT         16
> +#define WDT_MIN_TIMEOUT         1
> +#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
> +#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
> +
> +#define WDT_CTRL                0x00
> +#define WDT_CTRL_RESTART        (1 << 0)
> +#define WDT_CTRL_RESERVED       (0x0a57 << 1)

You didn't replied to me on that part in the previous mail. It doesn't
seem to be needed, so why keeping it?

> +#define WDT_MODE                0x04
> +#define WDT_MODE_EN             (1 << 0)
> +#define WDT_MODE_RST_EN         (1 << 1)
> +
> +#define DRV_NAME		"sunxi-wdt"
> +#define DRV_VERSION		"1.0"
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +static int heartbeat = WDT_MAX_TIMEOUT;
> +
> +/*
> + * wdt_timeout_map maps the watchdog timer interval value in seconds to
> + * the value of the register WDT_MODE bit 3:6
> + *
> + * [timeout seconds] = register value
> + *
> + */
> +
> +static const int wdt_timeout_map[] = {
> +	[1] = 0b0001,  /* 1s  */
> +	[2] = 0b0010,  /* 2s  */
> +	[3] = 0b0011,  /* 3s  */
> +	[4] = 0b0100,  /* 4s  */
> +	[5] = 0b0101,  /* 5s  */
> +	[6] = 0b0110,  /* 6s  */
> +	[8] = 0b0111,  /* 8s  */
> +	[10] = 0b1000, /* 10s */
> +	[12] = 0b1001, /* 12s */
> +	[14] = 0b1010, /* 14s */
> +	[16] = 0b1011, /* 16s */
> +};

Much better, thanks :)

> +
> +static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	reg = ioread32(wdt_base + WDT_CTRL);
> +	reg |= (WDT_CTRL_RESTART | WDT_CTRL_RESERVED);
> +	iowrite32(reg, wdt_base + WDT_CTRL);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
> +		unsigned int timeout)
> +{
> +	u32 reg;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout]))
> +		return -EINVAL;
> +
> +	sunxi_wdt_dev->timeout = timeout;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg &= ~(WDT_TIMEOUT_MASK);
> +	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	sunxi_wdt_ping(sunxi_wdt_dev);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg &= ~(WDT_MODE_RST_EN | WDT_MODE_EN);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	int ret;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
> +	if (ret < 0)
> +		return ret;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	return 0;
> +}
> +
> +static const struct watchdog_info sunxi_wdt_info = {
> +	.identity	= DRV_NAME,
> +	.options	= WDIOF_SETTIMEOUT |
> +			  WDIOF_KEEPALIVEPING |
> +			  WDIOF_MAGICCLOSE,
> +};
> +
> +static const struct watchdog_ops sunxi_wdt_ops = {
> +	.owner		= THIS_MODULE,
> +	.start		= sunxi_wdt_start,
> +	.stop		= sunxi_wdt_stop,
> +	.ping		= sunxi_wdt_ping,
> +	.set_timeout	= sunxi_wdt_set_timeout,
> +};
> +
> +static struct watchdog_device sunxi_wdt_dev = {
> +	.info		= &sunxi_wdt_info,
> +	.ops		= &sunxi_wdt_ops,
> +	.timeout	= WDT_MAX_TIMEOUT,
> +	.max_timeout	= WDT_MAX_TIMEOUT,
> +	.min_timeout	= WDT_MIN_TIMEOUT,
> +};
> +
> +static int __init sunxi_wdt_probe(struct platform_device *pdev)
> +{
> +	int err;
> +	void __iomem *wdt_base;
> +
> +	wdt_base = of_iomap(pdev->dev.of_node, 0);
> +	if (unlikely(!wdt_base)) {
> +		err = -ENOMEM;
> +		goto error_mem_out;
> +	}
> +
> +	sunxi_wdt_dev.parent = &pdev->dev;
> +	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
> +	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
> +
> +	err = watchdog_register_device(&sunxi_wdt_dev);
> +	if (unlikely(err))
> +		goto error_wdt;
> +
> +	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
> +
> +	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
> +			sunxi_wdt_dev.timeout, nowayout);
> +	return 0;
> +
> +error_wdt:
> +	iounmap(wdt_base);
> +error_mem_out:
> +	return err;
> +}
> +
> +static int __exit sunxi_wdt_remove(struct platform_device *pdev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
> +
> +	sunxi_wdt_stop(&sunxi_wdt_dev);
> +	watchdog_unregister_device(&sunxi_wdt_dev);
> +	iounmap(wdt_base);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sunxi_wdt_dt_ids[] = {
> +	{ .compatible = "allwinner,sun4i-wdt" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
> +
> +static struct platform_driver sunxi_wdt_driver = {
> +	.probe		= sunxi_wdt_probe,
> +	.remove		= sunxi_wdt_remove,
> +	.driver		= {
> +		.owner		= THIS_MODULE,
> +		.name		= DRV_NAME,
> +		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
> +	},
> +};
> +
> +module_platform_driver(sunxi_wdt_driver);
> +
> +module_param(heartbeat, int, 0);
> +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
> +
> +module_param(nowayout, bool, 0);
> +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
> +		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
> +MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
> +MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
> +MODULE_VERSION(DRV_VERSION);
> -- 
> 1.8.2.3
> 

I'm pretty happy with this driver, we only need to figure out this
reserved bits stuff, and we'll be fine.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From rostedt at goodmis.org  Sun May 19 12:06:19 2013
From: rostedt at goodmis.org (Steven Rostedt)
Date: Sun, 19 May 2013 12:06:19 -0400
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130519133418.GA24381@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <1368966844.6828.111.camel@gandalf.local.home>
 <20130519133418.GA24381@redhat.com>
Message-ID: <1368979579.6828.114.camel@gandalf.local.home>

On Sun, 2013-05-19 at 16:34 +0300, Michael S. Tsirkin wrote:

> Right but we need to keep it working on upstream as well.
> If I do preempt_enable under a spinlock upstream won't it
> try to sleep under spinlock?

No it wont. A spinlock calls preempt_disable implicitly, and a
preempt_enable() will not schedule unless preempt_count is zero, which
it wont be under a spinlock.

If it did, there would be lots of bugs all over the place because this
is done throughout the kernel (a preempt_enable() under a spinlock).

In other words, don't ever use preempt_enable_no_resched().

-- Steve




From mst at redhat.com  Sun May 19 12:40:09 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Sun, 19 May 2013 19:40:09 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <1368979579.6828.114.camel@gandalf.local.home>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <1368966844.6828.111.camel@gandalf.local.home>
 <20130519133418.GA24381@redhat.com>
 <1368979579.6828.114.camel@gandalf.local.home>
Message-ID: <20130519164009.GA2434@redhat.com>

On Sun, May 19, 2013 at 12:06:19PM -0400, Steven Rostedt wrote:
> On Sun, 2013-05-19 at 16:34 +0300, Michael S. Tsirkin wrote:
> 
> > Right but we need to keep it working on upstream as well.
> > If I do preempt_enable under a spinlock upstream won't it
> > try to sleep under spinlock?
> 
> No it wont. A spinlock calls preempt_disable implicitly, and a
> preempt_enable() will not schedule unless preempt_count is zero, which
> it wont be under a spinlock.
> 
> If it did, there would be lots of bugs all over the place because this
> is done throughout the kernel (a preempt_enable() under a spinlock).
> 
> In other words, don't ever use preempt_enable_no_resched().
> 
> -- Steve
> 


OK I get it. So let me correct myself. The simple code
that does something like this under a spinlock:
>       preempt_disable
>       pagefault_disable
>       error = copy_to_user
>       pagefault_enable
>       preempt_enable
>
is not doing anything wrong and should not get a warning,
as long as error is handled correctly later.
Right?


From moinejf at free.fr  Sun May 19 12:49:05 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Sun, 19 May 2013 18:49:05 +0200
Subject: [RFC 4/4] DRM: tda998x: add missing include
In-Reply-To: <51988D88.10306@gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194644.2a02a4fc@armhf>
 <CAF6AEGtx7RbvKEEc5uSFvz-2uveB1cnJNf_ESn6JYhfte5UmZQ@mail.gmail.com>
 <20130518205845.2dfe9fe5@armhf> <5197D6C1.3060702@gmail.com>
 <20130519080152.0b486b75@armhf> <51988D88.10306@gmail.com>
Message-ID: <20130519184905.1f238710@armhf>

On Sun, 19 May 2013 10:30:00 +0200
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> wrote:
> > /* --- test (not cubox) ---- *
> > &dcon { status = "okay"; };
> > 
> > &lcd1 {
> > 	status = "okay";
> > 	clocks =<&core_clk 3>,<0>,<&lcdclk>,<0>;
> > 	marvell,port-type =<1>;
> > 	display-timings {
> > 		mode {
> > 			hactive =<1920>;
> > 			vactive =<1080>;
> > 			hfront-porch =<88>;
> > 			hsync-len =<44>;
> > 			hback-porch =<148>;
> > 			vfront-porch =<4>;
> > 			vsync-len =<5>;
> > 			vback-porch =<36>;
> > 			clock =<148500>;
> > 		};
> > 	};  
> 
> I would be surprised if, lcd1 will ever be capable of driving
> 1080p60 on a *VGA port*!

As you may see, this sequence is preceded by an open comment: "test".

Now, as the port B of the display controller is only VGA (this is
checked in my driver), as there is no VGA connector on the Cubox, as
there is no VGA DAC code in my driver, and as I had to test the display
controller, I:

- defined the port B as VGA,

- set the timings of the mode I use for my HDMI display.

This does not mean the example must be used in the real word. It is
just a working example for test purpose.

> Seriously, start _reading_ what we say. I want all those
> features I already told you for your driver, in mainline driver
> too. All I told you was to prevent you from doing dirty little
> Cubox specific hacks that I would have to remove for e.g. D2Plug.

There is _NO_ Cubox specific stuff in my driver (I don't even use any
cubox-setup as Russell) and it should work without any change (except
the DT) in your D2plug. Remember, all my drm driver work is in
http://moinejf.free.fr/cubox/ as a big kernel patch (I will add the
I2C: mv64xxx which work fine - thanks Russell).

> *But* if you ask me if we should take Russell's or your driver
> as a basis, the answer is Russell's. Colon.

OK. Do what you want. My driver works fine enough for my usage:
software development. For video, my ISP gives us for free a Atom based
multimedia player with a Blue-Ray reader, and I have a AMD64 double
core on my family TV set for internet video (it will be a long time
till there will be VP8 decoding with vMeta). The only interest I see
in the Cubox is its low power consumption.

Now, I will switch back to my favorite long-distance development...

See you.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From carlo.caione at gmail.com  Sun May 19 13:01:54 2013
From: carlo.caione at gmail.com (Carlo Caione)
Date: Sun, 19 May 2013 19:01:54 +0200
Subject: [PATCH v2] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <20130519153235.GC7717@lukather>
References: <1368903956-32388-1-git-send-email-carlo.caione@gmail.com>
 <20130519153235.GC7717@lukather>
Message-ID: <F595BD7D-09B6-452A-B8FF-C7B667CE1DF8@gmail.com>


On May 19, 2013, at 5:32 PM, Maxime Ripard <maxime.ripard at free-electrons.com> wrote:

> Hi Carlo,

Hi Maxime,

>> +
>> +#define WDT_CTRL                0x00
>> +#define WDT_CTRL_RESTART        (1 << 0)
>> +#define WDT_CTRL_RESERVED       (0x0a57 << 1)
> 
> You didn't replied to me on that part in the previous mail. It doesn't
> seem to be needed, so why keeping it?

Actually I wrote you about this on irc (probably you were afk)
Anyway I tested the driver without using the 0x0a57 and without these bits the watchdog is never successfully kicked.
I'm going to submit a v3 soon, addressing also the suggestions given by Henrik on linux-sunxi ml.

Regards,

--
Carlo Caione





From sylvester.nawrocki at gmail.com  Sun May 19 13:18:41 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sun, 19 May 2013 19:18:41 +0200
Subject: [PATCH v2] net: dm9000: Allow instantiation using device tree
In-Reply-To: <15046898.dr5fzcR9ZS@flatron>
References: <1368962191-32594-1-git-send-email-tomasz.figa@gmail.com>
 <5198D359.5060608@gmail.com> <15046898.dr5fzcR9ZS@flatron>
Message-ID: <51990971.2050306@gmail.com>

On 05/19/2013 03:41 PM, Tomasz Figa wrote:
>>> +static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
>>> >  >  +{
>>> >  >  +	struct dm9000_plat_data *pdata;
>>> >  >  +	struct device_node *np = dev->of_node;
>>> >  >  +	const void *mac_addr;
>>> >  >  +
>>> >  >  +	if (!IS_ENABLED(CONFIG_OF) || !np)
>>> >  >  +		return NULL;
>> >
>> >  Shouldn't ERR_PTR() value be returned here ?
>
> Nope. No platform data is a valid case, so no error here.

OK, sorry, I should have checked that.

>>> >  >  +	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
>>> >  >  +	if (!pdata) {
>>> >  >  +		dev_err(dev, "failed to allocate platform data struct\n");
>> >
>> >  There is no need for this error log, k*alloc already logs any failures.
>
> Hmm. Does it print what allocation exactly failed? (e.g. a backtrace)

It seems the caller tracking is supported in subset of the kernel 
configurations.

> Not that it would give anything that could help you in an out of memory
> condition like this, but in general it's good to know in what point the
> failure happened.

As long as it is ENOMEM and the driver core reports failed probe I wouldn't
really care. Nevertheless I saw patch series removing such already existing
"Not enough memory" kind of error logs from the kernel, pointing out that mm
already provides relevant error logging.

Thanks,
Sylwester


From jason at lakedaemon.net  Sun May 19 14:16:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 14:16:32 -0400
Subject: [PATCH 2/2] ARM: mvebu: Add support for NOR flash device on
 Armada XP-DB board
In-Reply-To: <20130519091326.74a77b91@skate>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
 <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>
 <20130517165656.GE11137@titan.lakedaemon.net>
 <20130519091326.74a77b91@skate>
Message-ID: <20130519181632.GG11137@titan.lakedaemon.net>

On Sun, May 19, 2013 at 09:13:26AM +0200, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Fri, 17 May 2013 12:56:56 -0400, Jason Cooper wrote:
> > On Fri, May 17, 2013 at 08:09:58AM -0300, Ezequiel Garcia wrote:
> > > The Armada XP Development Board (DB-78460-BP) has a NOR flash device
> > > connected to the Device Bus. This commit adds the device tree node
> > > to support this device.
> > > 
> > > This SoC supports a flexible and dynamic decoding window allocation
> > > scheme; but since this feature is still not implemented we need
> > > to specify the window base address in the device tree node itself.
> > > 
> > > This base address has been selected in a completely arbitrary fashion.
> > > 
> > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
> > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> > > ---
> > >  arch/arm/boot/dts/armada-xp-db.dts | 32 ++++++++++++++++++++++++++++++++
> > >  1 file changed, 32 insertions(+)
> > 
> > Applied to mvebu/fixes
> 
> Is mvebu/fixes the branch intended to be pushed to 3.10-rcX, or to
> 3.11 ?
> 
> I'm asking because you've applied both 1/2 and 2/2 on the same
> mvebu/fixes branch, while 1/2 is intended for 3.10-rcX (fixing
> existing DT data), and 2/2 is intended for 3.11 (adding support for a
> new device in the DT).

I've added it to /fixes because it implements the same fix the other
patch did for the change in DT parsing.  I debated asking Ezequiel to
split it into two patches, one for the ranges fix, the other for the new
nodes.  In the end, since it isn't C code, I elected for simplicity.

thx,

Jason.


From thomas.petazzoni at free-electrons.com  Sun May 19 14:45:15 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sun, 19 May 2013 20:45:15 +0200
Subject: [PATCH 2/2] ARM: mvebu: Add support for NOR flash device on
 Armada XP-DB board
In-Reply-To: <20130519181632.GG11137@titan.lakedaemon.net>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
 <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>
 <20130517165656.GE11137@titan.lakedaemon.net>
 <20130519091326.74a77b91@skate>
 <20130519181632.GG11137@titan.lakedaemon.net>
Message-ID: <20130519204515.3f746331@skate>

Dear Jason Cooper,

On Sun, 19 May 2013 14:16:32 -0400, Jason Cooper wrote:

> > Is mvebu/fixes the branch intended to be pushed to 3.10-rcX, or to
> > 3.11 ?
> > 
> > I'm asking because you've applied both 1/2 and 2/2 on the same
> > mvebu/fixes branch, while 1/2 is intended for 3.10-rcX (fixing
> > existing DT data), and 2/2 is intended for 3.11 (adding support for a
> > new device in the DT).
> 
> I've added it to /fixes because it implements the same fix the other
> patch did for the change in DT parsing.  I debated asking Ezequiel to
> split it into two patches, one for the ranges fix, the other for the new
> nodes.  In the end, since it isn't C code, I elected for simplicity.

The addition to the range property is *only* needed because the NOR DT
node is added. The two are needed together, so splitting them would
make absolutely no sense.

The reason why for the other board is was done in two patches is
because at the time Ezequiel sent the patch for the NOR, we were not
using this common ranges = <...> property in the DT. The additional
entry in the ranges = <...> property should have been added when the DT
reorganization was merged with the NOR patch from Ezequiel, but it
was not done. So Ezequiel sent a fixup patch to fix this.

There's no need to repeat the same story for the NOR flash of the
Armada XP DB.

Again, PATCH 1/2 is a fix for something that exists in 3.10-rc, while
PATCH 2/2 is enabling a new device, so presumably, it should go in 3.11.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jason at lakedaemon.net  Sun May 19 15:36:17 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 15:36:17 -0400
Subject: [PATCH 2/2] ARM: mvebu: Add support for NOR flash device on
 Armada XP-DB board
In-Reply-To: <20130519204515.3f746331@skate>
References: <1368788998-4672-1-git-send-email-ezequiel.garcia@free-electrons.com>
 <1368788998-4672-2-git-send-email-ezequiel.garcia@free-electrons.com>
 <20130517165656.GE11137@titan.lakedaemon.net>
 <20130519091326.74a77b91@skate>
 <20130519181632.GG11137@titan.lakedaemon.net>
 <20130519204515.3f746331@skate>
Message-ID: <20130519193617.GI11137@titan.lakedaemon.net>

On Sun, May 19, 2013 at 08:45:15PM +0200, Thomas Petazzoni wrote:
> Again, PATCH 1/2 is a fix for something that exists in 3.10-rc, while
> PATCH 2/2 is enabling a new device, so presumably, it should go in 3.11.

Thanks, I'll moving it over to mvebu/dt.

thx,

Jason.


From arnd at arndb.de  Sun May 19 15:48:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 19 May 2013 21:48:46 +0200
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <F8915E01-0FCA-4C9F-8440-63B5A73B349B@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <201305161417.28133.arnd@arndb.de>
 <F8915E01-0FCA-4C9F-8440-63B5A73B349B@gmail.com>
Message-ID: <201305192148.46398.arnd@arndb.de>

On Sunday 19 May 2013, Daniel Tang wrote:
> If the vendors for the on-SOC components are unknown, should we just
> leave the compatible strings as is (i.e. "nspire-XXX")?

In that case, I would use the name of the company that made the SoC.
I believe someone mentioned it was made by LSI logic.

	Arnd


From gregory.clement at free-electrons.com  Sun May 19 16:12:43 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 22:12:43 +0200
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and ge11
Message-ID: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>

When platform data were moved from arch/arm/mach-mv78xx0/common.c to
arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion:
Consolidate ethernet platform data", there were few typo made on
gigabit Ethernet interface ge10 and ge11. This commit writes back
their initial value, which allows to use this interfaces again.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/plat-orion/common.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 251f827..c019b7a 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = {
 
 static struct platform_device orion_ge10_shared = {
 	.name		= MV643XX_ETH_SHARED_NAME,
-	.id		= 1,
+	.id		= 2,
 	.dev		= {
 		.platform_data	= &orion_ge10_shared_data,
 	},
@@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = {
 
 static struct platform_device orion_ge10 = {
 	.name		= MV643XX_ETH_NAME,
-	.id		= 1,
-	.num_resources	= 2,
+	.id		= 2,
+	.num_resources	= 1,
 	.resource	= orion_ge10_resources,
 	.dev		= {
 		.coherent_dma_mask	= DMA_BIT_MASK(32),
@@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = {
 
 static struct platform_device orion_ge11_shared = {
 	.name		= MV643XX_ETH_SHARED_NAME,
-	.id		= 1,
+	.id		= 3,
 	.dev		= {
 		.platform_data	= &orion_ge11_shared_data,
 	},
@@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = {
 
 static struct platform_device orion_ge11 = {
 	.name		= MV643XX_ETH_NAME,
-	.id		= 1,
-	.num_resources	= 2,
+	.id		= 3,
+	.num_resources	= 1,
 	.resource	= orion_ge11_resources,
 	.dev		= {
 		.coherent_dma_mask	= DMA_BIT_MASK(32),
-- 
1.8.1.2



From jason at lakedaemon.net  Sun May 19 16:13:12 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:13:12 -0400
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130519201312.GJ11137@titan.lakedaemon.net>

Sebastian,

On Sat, May 11, 2013 at 03:08:00AM +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
> 
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
> 
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
> 
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> 
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> 
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
> 
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
> 
> Sebastian Hesselbarth (10):
>   clk: mvebu: introduce per-clock-gate flags
>   clk: mvebu: add common clock functions for core clk and clk gating
>   clk: mvebu: add Dove SoC-centric clock init
>   clk: mvebu: add Kirkwood SoC-centric clock init
>   clk: mvebu: add Armada 370 SoC-centric clock init
>   clk: mvebu: add Armada XP SoC-centric clock init
>   ARM: dove: move DT boards to SoC-centric clock init
>   ARM: kirkwood: move DT boards to SoC-centric clock init
>   ARM: mvebu: move DT boards to SoC-centric clock init
>   clk: mvebu: desintegrate obsolete file
> 
>  arch/arm/mach-dove/Kconfig          |    3 +-
>  arch/arm/mach-dove/board-dt.c       |    3 +-
>  arch/arm/mach-dove/common.c         |    1 -
>  arch/arm/mach-kirkwood/Kconfig      |    3 +-
>  arch/arm/mach-kirkwood/board-dt.c   |    3 +-
>  arch/arm/mach-mvebu/Kconfig         |    5 +-
>  arch/arm/mach-mvebu/armada-370-xp.c |    4 +-
>  drivers/clk/mvebu/Kconfig           |   25 +-
>  drivers/clk/mvebu/Makefile          |    8 +-
>  drivers/clk/mvebu/armada-370.c      |  176 +++++++++
>  drivers/clk/mvebu/armada-xp.c       |  204 +++++++++++
>  drivers/clk/mvebu/clk-core.c        |  675 -----------------------------------
>  drivers/clk/mvebu/clk-core.h        |   18 -
>  drivers/clk/mvebu/clk-gating-ctrl.c |  250 -------------
>  drivers/clk/mvebu/clk-gating-ctrl.h |   22 --
>  drivers/clk/mvebu/clk.c             |   23 --
>  drivers/clk/mvebu/common.c          |  163 +++++++++
>  drivers/clk/mvebu/common.h          |   48 +++
>  drivers/clk/mvebu/dove.c            |  194 ++++++++++
>  drivers/clk/mvebu/kirkwood.c        |  247 +++++++++++++
>  include/linux/clk/mvebu.h           |   22 --
>  21 files changed, 1066 insertions(+), 1031 deletions(-)
>  create mode 100644 drivers/clk/mvebu/armada-370.c
>  create mode 100644 drivers/clk/mvebu/armada-xp.c
>  delete mode 100644 drivers/clk/mvebu/clk-core.c
>  delete mode 100644 drivers/clk/mvebu/clk-core.h
>  delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
>  delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
>  delete mode 100644 drivers/clk/mvebu/clk.c
>  create mode 100644 drivers/clk/mvebu/common.c
>  create mode 100644 drivers/clk/mvebu/common.h
>  create mode 100644 drivers/clk/mvebu/dove.c
>  create mode 100644 drivers/clk/mvebu/kirkwood.c
>  delete mode 100644 include/linux/clk/mvebu.h
> ---

I've tentatively applied the whole series to mvebu/seb_clk and merged it
into for-next.  This will get it a few rounds of testing in linux-next
until Mike has a chance to review it.

thx,

Jason.


From jason at lakedaemon.net  Sun May 19 16:17:23 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:17:23 -0400
Subject: [PATCH 15/20] ARM: mvebu: Remove init_irq declaration in
 machine description
In-Reply-To: <1368545933-7430-16-git-send-email-maxime.ripard@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-16-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130519201723.GK11137@titan.lakedaemon.net>

On Tue, May 14, 2013 at 05:38:48PM +0200, Maxime Ripard wrote:
> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
> specified") removed the need to explictly setup the init_irq field in
> the machine description when using only irqchip_init. Remove that
> declaration for mvebu as well.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Acked-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/mach-mvebu/armada-370-xp.c | 2 --
>  1 file changed, 2 deletions(-)

Applied to mvebu/cleanup

thx,

Jason.


From jason at lakedaemon.net  Sun May 19 16:19:39 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:19:39 -0400
Subject: [PATCH] arm: mvebu: enable the third USB interface on
 OpenBlocks AX3
In-Reply-To: <20130517.111810.02327269.yamagata@plathome.co.jp>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
Message-ID: <20130519201939.GL11137@titan.lakedaemon.net>

Mr Yamagata, Willy,

I don't like to assume for people, so if you could please provided a
"Tested-by:" I'd appreciate it.

thx,

Jason.

On Fri, May 17, 2013 at 11:18:10AM +0900, yamagata at plathome.co.jp wrote:
> Dear Mr. Petazzoni
> 
> > Besides the two "classic" USB interfaces with normal USB ports on the
> > front side, the PlatHome OpenBlocks AX3 uses the third USB interface
> > of the Marvell SoC in the mini-PCIe connector. This allows certain
> > mini-PCIe cards to expose parts of their functionality as a USB
> > peripheral.
> > 
> > This commit enables this third USB interface in the OpenBlocks AX3
> > Device Tree, and also adds comments on top of the two other USB
> > interfaces so that the Device Tree makes it clear which USB interface
> > at the SoC level matches which USB interface visible on the board.
> 
> I see the following messages by dmesg with your patch for
> linux-3.10-rc1 and 3.9.2.
> 
> ...
> usb 3-1: New USB device found, idVendor=0a5c, idProduct=219c
> usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
> usb 3-1: Product: Broadcom BCM2070 Bluetooth Device
> usb 3-1: Manufacturer: Broadcom Corp
> usb 3-1: SerialNumber: B4749F63C1B6
> ...
> Bluetooth: Core ver 2.16
> NET: Registered protocol family 31
> Bluetooth: HCI device and connection manager initialized
> Bluetooth: HCI socket layer initialized
> Bluetooth: L2CAP socket layer initialized
> Bluetooth: SCO socket layer initialized
> usbcore: registered new interface driver btusb
> ...
> 
> Best regards
> 
> Atsushi Yamagata
> --- Atsushi Yamagata
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From rostedt at goodmis.org  Sun May 19 16:23:22 2013
From: rostedt at goodmis.org (Steven Rostedt)
Date: Sun, 19 May 2013 16:23:22 -0400
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130519164009.GA2434@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <1368966844.6828.111.camel@gandalf.local.home>
 <20130519133418.GA24381@redhat.com>
 <1368979579.6828.114.camel@gandalf.local.home>
 <20130519164009.GA2434@redhat.com>
Message-ID: <1368995002.6828.117.camel@gandalf.local.home>

On Sun, 2013-05-19 at 19:40 +0300, Michael S. Tsirkin wrote:

> OK I get it. So let me correct myself. The simple code
> that does something like this under a spinlock:
> >       preempt_disable
> >       pagefault_disable
> >       error = copy_to_user
> >       pagefault_enable
> >       preempt_enable
> >
> is not doing anything wrong and should not get a warning,
> as long as error is handled correctly later.
> Right?

I came in mid thread and I don't know the context. Anyway, the above
looks to me as you just don't want to sleep. If you try to copy data to
user space that happens not to be currently mapped for any reason, you
will get an error. Even if the address space is completely valid. Is
that what you want?

-- Steve




From jason at lakedaemon.net  Sun May 19 16:24:05 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:24:05 -0400
Subject: [PATCH] arm: kirkwood: use the default of match table
In-Reply-To: <1368626700-29226-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368626700-29226-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130519202405.GM11137@titan.lakedaemon.net>

On Wed, May 15, 2013 at 04:04:59PM +0200, Thomas Petazzoni wrote:
> mach-kirkwood/board-dt.c defines its own OF matching table, but in
> fact, it is the same to the default of_default_bus_match_table[] which
> is already used by mach-mvebu, mach-dove and mach-orion5x.
> 
> This patch therefore makes mach-kirkwood use the same default OF
> matching table.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/mach-kirkwood/board-dt.c |    7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)

Applied to mvebu/soc

thx,

Jason.


From jason at lakedaemon.net  Sun May 19 16:28:24 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:28:24 -0400
Subject: [PATCHv10 1/9] arm: mvebu: fix the 'ranges' property to handle
 PCIe
In-Reply-To: <1368719725-21265-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130519202824.GN11137@titan.lakedaemon.net>

On Thu, May 16, 2013 at 05:55:16PM +0200, Thomas Petazzoni wrote:
> Since 82a682676 ('ARM: dts: mvebu: Convert all the mvebu files to use
> the range property') all the device nodes of Armada 370/XP are under a
> common 'ranges' property that translates the device register addresses
> into their absolute address, thanks to the base address of the
> internal register space.
> 
> However, beyond just the register areas, there are also PCIe I/O and
> memory regions, whose addresses should be properly translated. This
> patch fixes the Armada 370 and XP ranges property to take PCIe into
> account properly.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
> Since the PCIe Device Tree description has been merged in 3.10-rc1,
> this commit should go in 3.10-rc as well.
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |    3 ++-
>  arch/arm/boot/dts/armada-370.dtsi    |    3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Sun May 19 16:31:56 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:31:56 -0400
Subject: [PATCHv10 2/9] of/pci: Provide support for parsing PCI DT
 ranges property
In-Reply-To: <1368719725-21265-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130519203156.GO11137@titan.lakedaemon.net>

On Thu, May 16, 2013 at 05:55:17PM +0200, Thomas Petazzoni wrote:
> From: Andrew Murray <Andrew.Murray at arm.com>
> 
> This patch factors out common implementation patterns to reduce overall kernel
> code and provide a means for host bridge drivers to directly obtain struct
> resources from the DT's ranges property without relying on architecture specific
> DT handling. This will make it easier to write archiecture independent host bridge
> drivers and mitigate against further duplication of DT parsing code.
> 
> This patch can be used in the following way:
> 
> 	struct of_pci_range_parser parser;
> 	struct of_pci_range range;
> 
> 	if (of_pci_range_parser_init(&parser, np))
> 		; //no ranges property
> 
> 	for_each_of_pci_range(&parser, &range) {
> 
> 		/*
> 			directly access properties of the address range, e.g.:
> 			range.pci_space, range.pci_addr, range.cpu_addr,
> 			range.size, range.flags
> 
> 			alternatively obtain a struct resource, e.g.:
> 			struct resource res;
> 			of_pci_range_to_resource(&range, np, &res);
> 		*/
> 	}
> 
> Additionally the implementation takes care of adjacent ranges and merges them
> into a single range (as was the case with powerpc and microblaze).
> 
> Signed-off-by: Andrew Murray <Andrew.Murray at arm.com>
> Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Reviewed-by: Rob Herring <rob.herring at calxeda.com>
> Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Tested-by: Linus Walleij <linus.walleij at linaro.org>
> Tested-by: Jingoo Han <jg1.han at samsung.com>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
> ---
>  drivers/of/address.c       |   67 ++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/of_address.h |   48 +++++++++++++++++++++++++++++++
>  2 files changed, 115 insertions(+)

patches 2, 3, and 4 applied to mvebu/of_pci to facilitate others
(LinusW) basing their work off of it.

thx,

Jason.


From mst at redhat.com  Sun May 19 16:35:51 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Sun, 19 May 2013 23:35:51 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <1368995002.6828.117.camel@gandalf.local.home>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <1368966844.6828.111.camel@gandalf.local.home>
 <20130519133418.GA24381@redhat.com>
 <1368979579.6828.114.camel@gandalf.local.home>
 <20130519164009.GA2434@redhat.com>
 <1368995002.6828.117.camel@gandalf.local.home>
Message-ID: <20130519203551.GA27708@redhat.com>

On Sun, May 19, 2013 at 04:23:22PM -0400, Steven Rostedt wrote:
> On Sun, 2013-05-19 at 19:40 +0300, Michael S. Tsirkin wrote:
> 
> > OK I get it. So let me correct myself. The simple code
> > that does something like this under a spinlock:
> > >       preempt_disable
> > >       pagefault_disable
> > >       error = copy_to_user
> > >       pagefault_enable
> > >       preempt_enable
> > >
> > is not doing anything wrong and should not get a warning,
> > as long as error is handled correctly later.
> > Right?
> 
> I came in mid thread and I don't know the context.

The context is that I want to change might_fault
from might_sleep to
might_sleep_if(!in_atomic())
so that above does not trigger warnings even with
CONFIG_DEBUG_ATOMIC_SLEEP enabled.


> Anyway, the above
> looks to me as you just don't want to sleep.

Exactly. upstream we can just do pagefault_disable but to make
this code -rt ready it's best to do preempt_disable as well.

> If you try to copy data to
> user space that happens not to be currently mapped for any reason, you
> will get an error. Even if the address space is completely valid. Is
> that what you want?
> 
> -- Steve
> 

Yes, this is by design.
We detect that and bounce the work to a thread outside
any locks.

Thanks,

-- 
MST


From jason at lakedaemon.net  Sun May 19 16:47:03 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:47:03 -0400
Subject: [PATCHv10 5/9] clk: mvebu: create parent-child relation for
 PCIe clocks on Armada 370
In-Reply-To: <1368719725-21265-6-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-6-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130519204703.GP11137@titan.lakedaemon.net>

On Thu, May 16, 2013 at 05:55:20PM +0200, Thomas Petazzoni wrote:
> The Armada 370 has two gatable clocks for each PCIe interface, and we
> want both of them to be enabled. We therefore make one of the two
> clocks a child of the other, as we did for the sataX and sataXlnk
> clocks on Armada XP.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> ---
>  drivers/clk/mvebu/clk-gating-ctrl.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Patches 5 - 8 applied to mvebu/pcie, with a dep on Sebastian's clock
rework and mvebu/of_pci.  Thanks for the head's up on the clk conflict.
My resolution should match yours.  Please let me know if it doesn't.

thx,

Jason.


From jason at lakedaemon.net  Sun May 19 16:49:57 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 19 May 2013 16:49:57 -0400
Subject: [PATCHv10 9/9] arm: mvebu: update defconfig with PCI and USB
 support
In-Reply-To: <1368719725-21265-10-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-10-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130519204957.GQ11137@titan.lakedaemon.net>

On Thu, May 16, 2013 at 05:55:24PM +0200, Thomas Petazzoni wrote:
> Now that we have the necessary drivers and Device Tree informations to
> support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
> option.
> 
> Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
> connected on the PCIe bus, enable the corresponding options as well.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/configs/mvebu_defconfig |    3 +++
>  1 file changed, 3 insertions(+)

Applied to mvebu/defconfig

thx,

Jason.


From w at 1wt.eu  Sun May 19 17:30:40 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Sun, 19 May 2013 23:30:40 +0200
Subject: [PATCH] arm: mvebu: enable the third USB interface on OpenBlocks
 AX3
In-Reply-To: <20130519201939.GL11137@titan.lakedaemon.net>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
 <20130519201939.GL11137@titan.lakedaemon.net>
Message-ID: <20130519213040.GD8651@1wt.eu>

On Sun, May 19, 2013 at 04:19:39PM -0400, Jason Cooper wrote:
> Mr Yamagata, Willy,
> 
> I don't like to assume for people, so if you could please provided a
> "Tested-by:" I'd appreciate it.

Yes of course, I didn't propose it in order to save you the work of
collecting these tags :-)

  Tested-by: Willy Tarreau <w at 1wt.eu>

Best regards,
Willy



From gregory.clement at free-electrons.com  Sun May 19 17:39:34 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 23:39:34 +0200
Subject: [RFC PATCH 1/5] ARM: mv78x00: Add generic support for the Device Tree
 boards
In-Reply-To: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368999578-19938-2-git-send-email-gregory.clement@free-electrons.com>

This commit add the generic support for the MV78X00 based boards
converted to the device tree.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mv78xx0/board-dt.c | 46 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 arch/arm/mach-mv78xx0/board-dt.c

diff --git a/arch/arm/mach-mv78xx0/board-dt.c b/arch/arm/mach-mv78xx0/board-dt.c
new file mode 100644
index 0000000..4995fee
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/board-dt.c
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-mv78xx0/board-dt.c
+ *
+ * Flattened Device Tree board initialization
+ *
+ * Copyright (C) 2013  Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <mach/mv78xx0.h>
+#include <plat/irq.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+
+static void __init mv78x00_dt_init(void)
+{
+	/*
+	 * Basic MV78xx0 setup. Needs to be called early.
+	 */
+	mv78xx0_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *mv78x00_dt_compat[] = {
+	"marvell,mv78x00",
+	NULL,
+};
+
+DT_MACHINE_START(MV78X00_DT, "Marvell MV78x00 (Flattened Device Tree)")
+	/* Maintainer: Gregory CLEMENT <gregory.clement at free-electrons.com> */
+	.init_machine	= mv78x00_dt_init,
+	.map_io		= mv78xx0_map_io,
+	.init_early	= mv78xx0_init_early,
+	.init_irq	= orion_dt_init_irq,
+	.init_time	= mv78xx0_timer_init,
+	.restart	= mv78xx0_restart,
+	.dt_compat	= mv78x00_dt_compat,
+MACHINE_END
-- 
1.8.1.2



From gregory.clement at free-electrons.com  Sun May 19 17:39:36 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 23:39:36 +0200
Subject: [RFC PATCH 3/5] ARM: mv78x00: Add infrastructure to support boards
 converted to DT
In-Reply-To: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368999578-19938-4-git-send-email-gregory.clement@free-electrons.com>

This commit updates the Kconfig and the Makefile to allow to build the
boards converted to the Device Tree.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mv78xx0/Kconfig  | 7 +++++++
 arch/arm/mach-mv78xx0/Makefile | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
index f2d309d..2390a6e 100644
--- a/arch/arm/mach-mv78xx0/Kconfig
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -20,6 +20,13 @@ config MACH_TERASTATION_WXL
 	  Say 'Y' here if you want your kernel to support the
 	  Buffalo WXL Nas.
 
+config ARCH_MV78X00_DT
+	bool "Marvell MV78X00 Flattened Device Tree"
+	select USE_OF
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell MV78X00 using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
index 7cd0463..8935e48 100644
--- a/arch/arm/mach-mv78xx0/Makefile
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -2,3 +2,4 @@ obj-y				+= common.o mpp.o irq.o pcie.o
 obj-$(CONFIG_MACH_DB78X00_BP)	+= db78x00-bp-setup.o
 obj-$(CONFIG_MACH_RD78X00_MASA)	+= rd78x00-masa-setup.o
 obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
+obj-$(CONFIG_ARCH_MV78X00_DT)	+= board-dt.o
-- 
1.8.1.2



From gregory.clement at free-electrons.com  Sun May 19 17:39:33 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 23:39:33 +0200
Subject: [RFC PATCH 0/5] ARM: mv78x00: First step to convert mv78x00 to Device
 Tree
Message-ID: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>

Hello,

This patch set is a first step in order to convert mach-mv78x00 to
device tree before it joins mach-mvebu.

I managed to test it on the RD-78X00-mASA board. All the peripherals I
have tested work as they work before the migration to the device tree:
- UART
- Ethernet
- USB
- SATA

My main concern is that the mv78x00 are MP but not SMP
capable. Currently the same kernel run on the 2 cores and it is in the
board file that the peripherals are assigned for each CPU. (Actually I
didn't test this behavior, but the code is written in this way.)

I don't know how to assign a peripheral to a given CPU with the device
tree. The only way I have in mind is to have a dts per CPU, but I am
not sure it is very convenient.

So for now the code assigns all the peripherals to the CPU.

I am also concerned by the 2 other boards: the Marvell DB-78x00-BP
Development Board and the Buffalo WLX (Terastation Duo) NAS. I don't
have them and so I can't test them if I want to convert them to device
tree too.

Comments and ideas are welcome

Thanks,

Gregory CLEMENT (5):
  ARM: mv78x00: Add generic support for the Device Tree boards
  ARM: mv78x00: Convert RD-78X00-mASA board to device tree
  ARM: mv78x00: Add infrastructure to support boards converted to DT
  ARM: mv78x00: Add the Device Tree support for MV78X00 family
  ARM: mv78x00: Add Device Tree support for the RD-78X00-mASA board

 arch/arm/boot/dts/Makefile                 |   1 +
 arch/arm/boot/dts/mv78x00-masa-db.dts      |  61 ++++++++++++++
 arch/arm/boot/dts/mv78x00.dtsi             | 126 +++++++++++++++++++++++++++++
 arch/arm/mach-mv78xx0/Kconfig              |   7 ++
 arch/arm/mach-mv78xx0/Makefile             |   1 +
 arch/arm/mach-mv78xx0/board-dt.c           |  49 +++++++++++
 arch/arm/mach-mv78xx0/common.h             |   7 ++
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c |  10 +++
 8 files changed, 262 insertions(+)
 create mode 100644 arch/arm/boot/dts/mv78x00-masa-db.dts
 create mode 100644 arch/arm/boot/dts/mv78x00.dtsi
 create mode 100644 arch/arm/mach-mv78xx0/board-dt.c

-- 
1.8.1.2



From gregory.clement at free-electrons.com  Sun May 19 17:39:35 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 23:39:35 +0200
Subject: [RFC PATCH 2/5] ARM: mv78x00: Convert RD-78X00-mASA board to device
 tree
In-Reply-To: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368999578-19938-3-git-send-email-gregory.clement@free-electrons.com>

This commit converts the 'RD-78X00-mASA' board to the Device
Tree. Most of the devices are converted to the Device Tree, the only
devices which have not their Device Tree bindings are the Gigabit
Ethernet ones and remain instantiated in the old way.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mv78xx0/board-dt.c           |  3 +++
 arch/arm/mach-mv78xx0/common.h             |  7 +++++++
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 10 ++++++++++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/mach-mv78xx0/board-dt.c b/arch/arm/mach-mv78xx0/board-dt.c
index 4995fee..5111cbd 100644
--- a/arch/arm/mach-mv78xx0/board-dt.c
+++ b/arch/arm/mach-mv78xx0/board-dt.c
@@ -26,6 +26,9 @@ static void __init mv78x00_dt_init(void)
 	 */
 	mv78xx0_init();
 
+	if (of_machine_is_compatible("marvell,rd-78x00-masa"))
+		rd78x00_masa_init_dt();
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485b..6e9140d 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -17,6 +17,13 @@ struct mv_sata_platform_data;
 /*
  * Basic MV78xx0 init functions used early by machine-setup.
  */
+#ifdef CONFIG_MACH_RD78X00_MASA
+void rd78x00_masa_init_dt(void);
+#else
+static inline void rd78x00_masa_init_dt(void) {};
+#endif
+
+
 int mv78xx0_core_index(void);
 void mv78xx0_map_io(void);
 void mv78xx0_init(void);
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index d2d06f3..8d88657 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -64,6 +64,16 @@ static void __init rd78x00_masa_init(void)
 	}
 }
 
+void __init rd78x00_masa_init_dt(void)
+{
+	/* Internal devices not ported to DT yet */
+	mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
+	mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
+		mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
+		mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
+
+}
+
 static int __init rd78x00_pci_init(void)
 {
 	/*
-- 
1.8.1.2



From gregory.clement at free-electrons.com  Sun May 19 17:39:37 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 23:39:37 +0200
Subject: [RFC PATCH 4/5] ARM: mv78x00: Add the Device Tree support for MV78X00
 family
In-Reply-To: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368999578-19938-5-git-send-email-gregory.clement@free-electrons.com>

This commit adds the Device Tree support for the mv78x00 SoC
family. It adds an mv78x00.dtsi description of the mv78x00 SoC

So far, the Device Tree contains the interrupt controller, the GPIO
bank, the UART controllers, the USB host controllers, the SATA
controllers and the I2C controllers.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/mv78x00.dtsi | 126 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)
 create mode 100644 arch/arm/boot/dts/mv78x00.dtsi

diff --git a/arch/arm/boot/dts/mv78x00.dtsi b/arch/arm/boot/dts/mv78x00.dtsi
new file mode 100644
index 0000000..df496f5
--- /dev/null
+++ b/arch/arm/boot/dts/mv78x00.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2013 Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Marvell MV78X00 SoC";
+	compatible = "marvell,mv78x00";
+	interrupt-parent = <&intc>;
+
+	intc: interrupt-controller {
+		compatible = "marvell,orion-intc", "marvell,intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xf1020210 0x04>,
+		      <0xf1020214 0x04>,
+		      <0xf102020c 0x04>;
+	};
+
+	ocp at f1000000 {
+		compatible = "simple-bus";
+		ranges = <0x00000000 0xf1000000 0x4000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		gpio0: gpio at 10100 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0x10100 0x40>;
+			ngpios = <32>;
+			interrupts = <56>, <57>, <58>, <59>;
+		};
+
+		serial at 12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <12>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+
+		serial at 12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <13>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+
+		serial at 12200 {
+			compatible = "ns16550a";
+			reg = <0x12200 0x100>;
+			reg-shift = <2>;
+			interrupts = <14>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+
+		serial at 12300 {
+			compatible = "ns16550a";
+			reg = <0x12300 0x100>;
+			reg-shift = <2>;
+			interrupts = <15>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+
+
+		sata at a0000 {
+			compatible = "marvell,orion-sata";
+			reg = <0xa0000 0x5000>;
+			interrupts = <26>;
+			status = "disabled";
+		};
+
+		i2c at 10000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x10000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c at 11000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x11000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <3>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		ehci at 50000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x50000 0x1000>;
+			interrupts = <16>;
+			status = "disabled";
+		};
+
+		ehci at 51000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x51000 0x1000>;
+			interrupts = <17>;
+			status = "disabled";
+		};
+
+		ehci at 52000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x52000 0x1000>;
+			interrupts = <18>;
+			status = "disabled";
+		};
+
+	};
+};
-- 
1.8.1.2



From gregory.clement at free-electrons.com  Sun May 19 17:39:38 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Sun, 19 May 2013 23:39:38 +0200
Subject: [RFC PATCH 5/5] ARM: mv78x00: Add Device Tree support for the
 RD-78X00-mASA board
In-Reply-To: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1368999578-19938-6-git-send-email-gregory.clement@free-electrons.com>

This commit adds the device tree support for the RD-78X00-mASA board.
It mainly converts the platform resource from the former board file
to the dts. It also add this device tree to the list of the dtbs
make rule.

Currently support includes:
- UARTs
- USBs
- I2Cs
- RTC
- SATAs

The mains lacks are PCI and Ethernet which will be added when
converted to device tree.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/Makefile            |  1 +
 arch/arm/boot/dts/mv78x00-masa-db.dts | 61 +++++++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 arch/arm/boot/dts/mv78x00-masa-db.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..f152b89 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
 	msm8960-cdp.dtb
+dtb-$(CONFIG_ARCH_MV78X00) += mv78x00-masa-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
 	armada-370-mirabox.dtb \
 	armada-370-rd.dtb \
diff --git a/arch/arm/boot/dts/mv78x00-masa-db.dts b/arch/arm/boot/dts/mv78x00-masa-db.dts
new file mode 100644
index 0000000..f87f84d
--- /dev/null
+++ b/arch/arm/boot/dts/mv78x00-masa-db.dts
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2013  Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "mv78x00.dtsi"
+
+/ {
+	model = "Marvell RD-78x00-MASA Development Board";
+	compatible = "marvell,rd-78x00-masa", "marvell,mv78x00";
+
+	memory {
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "okay";
+		};
+
+		serial at 12200 {
+			clock-frequency = <200000000>;
+			status = "okay";
+		};
+
+		sata at a0000 {
+			nr-ports = <2>;
+			status = "okay";
+		};
+
+		i2c0: i2c at 10000 {
+			status = "okay";
+			rtc: rtc at 68 {
+				compatible = "dallas,ds1338";
+				reg = <0x68>;
+			};
+		};
+
+		ehci at 50000 {
+			status = "okay";
+		};
+
+		ehci at 51000 {
+			status = "okay";
+		};
+
+		ehci at 52000 {
+			status = "okay";
+		};
+	};
+};
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Sun May 19 17:40:33 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 19 May 2013 23:40:33 +0200
Subject: [PATCH v2] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <F595BD7D-09B6-452A-B8FF-C7B667CE1DF8@gmail.com>
References: <1368903956-32388-1-git-send-email-carlo.caione@gmail.com>
 <20130519153235.GC7717@lukather>
 <F595BD7D-09B6-452A-B8FF-C7B667CE1DF8@gmail.com>
Message-ID: <20130519214033.GA8509@lukather>

On Sun, May 19, 2013 at 07:01:54PM +0200, Carlo Caione wrote:
> 
> On May 19, 2013, at 5:32 PM, Maxime Ripard <maxime.ripard at free-electrons.com> wrote:
> 
> > Hi Carlo,
> 
> Hi Maxime,
> 
> >> +
> >> +#define WDT_CTRL                0x00
> >> +#define WDT_CTRL_RESTART        (1 << 0)
> >> +#define WDT_CTRL_RESERVED       (0x0a57 << 1)
> > 
> > You didn't replied to me on that part in the previous mail. It doesn't
> > seem to be needed, so why keeping it?
> 
> Actually I wrote you about this on irc (probably you were afk)
> Anyway I tested the driver without using the 0x0a57 and without these bits the watchdog is never successfully kicked.
> I'm going to submit a v3 soon, addressing also the suggestions given by Henrik on linux-sunxi ml.

Ok, please discuss this both using mails and by keeping all the
recipients... I wasn't in copy of these mails anymore, neither were the
kernel mailing lists which makes it a pain for the archives and for
other people being part of the discussions.

Please always reply-to-all, and with mails, to these questions.

Anyway, ok. Put a comment explaining why you need it then.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From paul at pwsan.com  Sun May 19 18:03:39 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Sun, 19 May 2013 22:03:39 +0000 (UTC)
Subject: OMAP baseline test results for v3.10-rc1
Message-ID: <alpine.DEB.2.00.1305192159080.2656@utopia.booyaka.com>



Here are some basic OMAP test results for Linux v3.10-rc1.
Logs and other details at:

    http://www.pwsan.com/omap/testlogs/test_v3.10-rc1/20130518212204/


Test summary
------------

Build: uImage:
    Pass (16/16): am33xx_only, n800_multi_omap2xxx, n800_only_a,
                  omap1_defconfig, omap1_defconfig_1510innovator_only, 
                  omap1_defconfig_5912osk_only, omap2plus_defconfig, 
                  omap2plus_defconfig_2430sdp_only
                  omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, 
                  omap2plus_defconfig_omap2_4_only, 
                  omap2plus_defconfig_omap3_4_only, 
                  rmk_omap3430_ldp_allnoconfig, 
                  rmk_omap3430_ldp_oldconfig, 
                  rmk_omap4430_sdp_allnoconfig, 
                  rmk_omap4430_sdp_oldconfig

Build: zImage:
    Pass ( 1/ 1): omap2plus_defconfig

Boot to userspace:
    FAIL ( 6/12): 2430sdp, 3517evm, 37xxevm, am335xbone, am335xbonelt, cmt3517
    Pass ( 6/12): 2420n800, 3530es3beagle, 3730beaglexm, 4430es2panda,
                  4460pandaes, 5912osk

PM: chip retention via suspend:
    FAIL ( 4/ 6): 2430sdp, 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 2/ 6): 3530es3beagle, 3730beaglexm

PM: chip retention via dynamic idle:
    FAIL ( 4/ 6): 2430sdp, 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 2/ 6): 3530es3beagle, 3730beaglexm

PM: chip off except CORE via suspend:
    Pass ( 1/ 1): 3730beaglexm

PM: chip off except CORE via dynamic idle:
    Pass ( 1/ 1): 3730beaglexm

PM: chip off via suspend:
    FAIL ( 3/ 4): 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 1/ 4): 3530es3beagle

PM: chip off via dynamic idle:
    FAIL ( 3/ 4): 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 1/ 4): 3530es3beagle



Failing tests: fixed by posted patches
--------------------------------------

Boot:

* ARMv6 OMAPs don't boot with omap2plus_defconfig
  - missing Kconfig 
  - http://marc.info/?l=linux-omap&m=136872761502689&w=2

* 3517EVM & CM-T3517: boot hangs with MMC root
  - Possibly fixed by https://lkml.org/lkml/2013/5/5/6


Failing tests: needing investigation
------------------------------------

Boot tests:

* 3517EVM & CM-T3517: boot hangs with NFS root
  - Likely some Kconfig, board file, and PM issues with EMAC
  - Longstanding bug
  - Not currently part of the automated test suite

* 37xx EVM: boot fails
  - Cause unknown

Boot warnings:

* CM-T3517: L3 in-band error with IPSS during boot
  - Cause unknown but see http://marc.info/?l=linux-omap&m=134833869730129&w=2
  - Longstanding issue; does not occur on the 3517EVM

PM tests:

* 2430sdp: power domains not entering retention
  - Cause unknown

* 3730 Beagle XM: does not serial wake from off-idle suspend when console
  UART doesn't clock-gate ("debug ignore_loglevel")
  - Cause unknown
  - Not yet part of the automated test suite
  - Re-tested at v3.7; still failing:
    http://www.pwsan.com/omap/transcripts/20121211-3730beaglexm-3.7-pm-offmode-fail-debug.txt

* 4430es2panda: pwrdm state mismatch on CAM, DSS

* 4430es2panda: CORE, TESLA, IVAHD, L3INIT didn't enter target state
  - Probably due to lack of reset code for M3, DSP, SL2IF, FSUSB
    per discussion with Tero Kristo
  - Likely dependent on the bootloader version
    - fails with 2012.07-00136-g755de79
  - http://marc.info/?l=linux-arm-kernel&m=136432340618226&w=2

* 4430es2panda: MPU, ABE didn't enter target state
  - New for v3.10-rc

* 4460pandaes: pwrdm state mismatch on DSS, ABE, IVAHD, TESLA

* 4460pandaes: chip not entering retention in dynamic idle
  - Presumably 4430es2panda also fails this
  - Suspend-to-RAM enters full chip retention

Other:

* 4430es2panda: omap_hwmod: l3_instr: _wait_target_disable failed
  - Unknown cause; could be due to the lack of hierarchical enable/disable
    in hwmod code
  - Jon Hunter and Santosh Shilimkar report this does not appear with
    the same X-loader/bootloader on his 4430ES2.3 Panda, so could be
    ES-level dependent


From paul at pwsan.com  Sun May 19 18:29:40 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Sun, 19 May 2013 22:29:40 +0000 (UTC)
Subject: OMAP baseline test results for v3.10-rc1
In-Reply-To: <alpine.DEB.2.00.1305192159080.2656@utopia.booyaka.com>
References: <alpine.DEB.2.00.1305192159080.2656@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1305192219240.2656@utopia.booyaka.com>


Looks like a few messages were missed, so here's an updated version, along 
with the size data.

- Paul


Here are some basic OMAP test results for Linux v3.10-rc1.
Logs and other details at:

    http://www.pwsan.com/omap/testlogs/test_v3.10-rc1/20130518212204/


Test summary
------------

Build: uImage:
    Pass (16/16): am33xx_only, n800_multi_omap2xxx, n800_only_a,
                  omap1_defconfig, omap1_defconfig_1510innovator_only, 
                  omap1_defconfig_5912osk_only, omap2plus_defconfig, 
                  omap2plus_defconfig_2430sdp_only
                  omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, 
                  omap2plus_defconfig_omap2_4_only, 
                  omap2plus_defconfig_omap3_4_only, 
                  rmk_omap3430_ldp_allnoconfig, 
                  rmk_omap3430_ldp_oldconfig, 
                  rmk_omap4430_sdp_allnoconfig, 
                  rmk_omap4430_sdp_oldconfig

Build: zImage:
    Pass ( 1/ 1): omap2plus_defconfig

Boot to userspace:
    FAIL ( 6/12): 2430sdp, 3517evm, 37xxevm, am335xbone, am335xbonelt, cmt3517
    Pass ( 6/12): 2420n800, 3530es3beagle, 3730beaglexm, 4430es2panda,
                  4460pandaes, 5912osk

PM: chip retention via suspend:
    FAIL ( 4/ 6): 2430sdp, 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 2/ 6): 3530es3beagle, 3730beaglexm

PM: chip retention via dynamic idle:
    FAIL ( 4/ 6): 2430sdp, 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 2/ 6): 3530es3beagle, 3730beaglexm

PM: chip off except CORE via suspend:
    Pass ( 1/ 1): 3730beaglexm

PM: chip off except CORE via dynamic idle:
    Pass ( 1/ 1): 3730beaglexm

PM: chip off via suspend:
    FAIL ( 3/ 4): 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 1/ 4): 3530es3beagle

PM: chip off via dynamic idle:
    FAIL ( 3/ 4): 37xxevm, 4430es2panda, 4460pandaes
    Pass ( 1/ 4): 3530es3beagle



Failing tests: fixed by posted patches
--------------------------------------

Boot:

* ARMv6 OMAPs don't boot with omap2plus_defconfig
  - missing Kconfig 
  - http://marc.info/?l=linux-omap&m=136872761502689&w=2

* 3517EVM & CM-T3517: boot hangs with MMC root
  - Possibly fixed by https://lkml.org/lkml/2013/5/5/6


Failing tests: needing investigation
------------------------------------

Boot tests:

* 3517EVM & CM-T3517: boot hangs with NFS root
  - Likely some Kconfig, board file, and PM issues with EMAC
  - Longstanding bug
  - Not currently part of the automated test suite

* 37xx EVM: boot fails
  - Cause unknown

Boot warnings:

* 2420N800: failed to get counter_32k resource
  - "omap2_sync32k_clocksource_init: failed to get counter_32k resource"
  - Cause unknown

* CM-T3517: L3 in-band error with IPSS during boot
  - Cause unknown but see http://marc.info/?l=linux-omap&m=134833869730129&w=2
  - Longstanding issue; does not occur on the 3517EVM

* 3730 Beagle XM, 3530 Beagle, 3517EVM, CM-T3517: {dmic,mcpdm} lookup failure
  - Cause unknown
  - These IP blocks don't exist on OMAP3xxx/AM35xx chips

* 3730 Beagle XM, am335xbone, CM-T3517: uart4_rx.uart4_rx mux failure
  - Cause unknown

PM tests:

* 2430sdp: power domains not entering retention
  - Cause unknown

* 3730 Beagle XM: does not serial wake from off-idle suspend when console
  UART doesn't clock-gate ("debug ignore_loglevel")
  - Cause unknown
  - Not yet part of the automated test suite
  - Re-tested at v3.7; still failing:
    http://www.pwsan.com/omap/transcripts/20121211-3730beaglexm-3.7-pm-offmode-fail-debug.txt

* 4430es2panda: pwrdm state mismatch on CAM, DSS

* 4430es2panda: CORE, TESLA, IVAHD, L3INIT didn't enter target state
  - Probably due to lack of reset code for M3, DSP, SL2IF, FSUSB
    per discussion with Tero Kristo
  - Likely dependent on the bootloader version
    - fails with 2012.07-00136-g755de79
  - http://marc.info/?l=linux-arm-kernel&m=136432340618226&w=2

* 4430es2panda: MPU, ABE didn't enter target state
  - New for v3.10-rc

* 4460pandaes: pwrdm state mismatch on DSS, ABE, IVAHD, TESLA

* 4460pandaes: chip not entering retention in dynamic idle
  - Presumably 4430es2panda also fails this
  - Suspend-to-RAM enters full chip retention

Other:

* 4430es2panda: omap_hwmod: l3_instr: _wait_target_disable failed
  - Unknown cause; could be due to the lack of hierarchical enable/disable
    in hwmod code
  - Jon Hunter and Santosh Shilimkar report this does not appear with
    the same X-loader/bootloader on his 4430ES2.3 Panda, so could be
    ES-level dependent

vmlinux object size
(delta in bytes from test_v3.9 
(c1be5a5b1b355d40e6cf79cc979eb66dafa24ad1)):
   text     data      bss    total  kernel
+7698786  +424812  +5648088  +13771686  am33xx_only
 -18104   -20920     +684   -38340  n800_multi_omap2xxx
 -13776   -20896     +716   -33956  n800_only_a
 +61099    +2064   +41912  +105075  omap1_defconfig
 +61586    +2016   +41912  +105514  omap1_defconfig_1510innovator_only
 +56576    +1896   +41976  +100448  omap1_defconfig_5912osk_only
 -59854   -98552   +37136  -121270  omap2plus_defconfig
+7419117  +402860  +5622032  +13444009  omap2plus_defconfig_2430sdp_only
 -58570   -98248   +37136  -119682  omap2plus_defconfig_cpupm
 -60068   -96504   +37072  -119500  omap2plus_defconfig_no_pm
 +17627   -16936   +37328   +38019  omap2plus_defconfig_omap2_4_only
 +13196   -20536   +37200   +29860  omap2plus_defconfig_omap3_4_only
 -37304   -74116     +476  -110944  rmk_omap3430_ldp_allnoconfig
 +26264   -15928   +37568   +47904  rmk_omap3430_ldp_oldconfig
 -37304   -74116     +476  -110944  rmk_omap4430_sdp_allnoconfig
 +29503    -8576    +9400   +30327  rmk_omap4430_sdp_oldconfig

am33xx_only and omap2plus_defconfig_2430sdp_only kernel didn't build 
during the v3.9 series.

Good to see that the kernel size has decreased for omap2plus_defconfig.  
Hopefully most of this will remain after ARMv6 support is re-enabled.  
Unfortunately kernel size has increased considerably for 
omap1plus_defconfig.


Boot-time memory difference
(delta in bytes from test_v3.9 
(c1be5a5b1b355d40e6cf79cc979eb66dafa24ad1))
  avail  rsrvd   high  freed  board          kconfig
    44k   -44k      .  -144k  2420n800       n800_only_a
   120k  -120k      .  -340k  3517evm        omap2plus_defconfig
   120k  -120k      .  -340k  3530es3beagle  omap2plus_defconfig
   120k  -120k      .  -340k  3730beaglexm   omap2plus_defconfig
   120k  -120k      .  -340k  4430es2panda   omap2plus_defconfig
   120k  -120k      .  -340k  4460pandaes    omap2plus_defconfig
  -108k   108k      .  -172k  5912osk        omap1_defconfig



From paul at pwsan.com  Sun May 19 19:07:55 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Sun, 19 May 2013 23:07:55 +0000 (UTC)
Subject: [PATCH v3 0/6] ARM: OMAP2+: hwmod and SERIAL: Remove sysc handling
 from driver
In-Reply-To: <87txm1smrz.fsf@linaro.org>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
 <alpine.DEB.2.00.1305161831390.21357@utopia.booyaka.com>
 <87txm1smrz.fsf@linaro.org>
Message-ID: <alpine.DEB.2.00.1305192307360.2656@utopia.booyaka.com>

Hi,

On Fri, 17 May 2013, Kevin Hilman wrote:

> I reviewed and tested v2 of this (Rajendra forgot to add the tags in
> v3) and also just sanity tested v3 of this on 4430/panda DT boot to
> verify the console issue is resolved.  Feel free to add:
> 
> Reviewed-by: Kevin Hilman <khilman at linaro.org>
> Tested-by: Kevin Hilman <khilman at linaro.org>  # OMAP4/Panda

Added.

- Paul


From paul at pwsan.com  Sun May 19 19:33:33 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Sun, 19 May 2013 23:33:33 +0000 (UTC)
Subject: [GIT PULL] ARM: OMAP2+: hwmod/serial: fix DT case
Message-ID: <alpine.DEB.2.00.1305192331390.2656@utopia.booyaka.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/omap-fixes-a-for-3.10-rc

for you to fetch changes up to 3260c76055afc6c9396e5ad9f9e599505ea8891f:

  ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis (2013-05-19 16:37:15 -0600)

- ----------------------------------------------------------------
Fix the OMAP serial driver to work correctly on OMAP4 when booting
with DT.

Basic build, boot, and PM test logs are here - unfortunately, not for
the DT case yet:

http://www.pwsan.com/omap/testlogs/uart_idle_fix_v3.10-rc/20130519164010/

- ----------------------------------------------------------------
Rajendra Nayak (2):
      ARM: OMAP2+: hwmod: Fix sidle programming in _enable_sysc()/_idle_sysc()
      ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in active

Santosh Shilimkar (4):
      ARM: OMAP2+: hwmod-data: UART IP needs software control to manage sidle modes
      ARM: OMAP2+: serial: Remove the un-used slave idle hooks
      SERIAL: OMAP: Remove the slave idle handling from the driver
      ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis

 arch/arm/mach-omap2/omap_hwmod.c                   |  111 +++++---------------
 arch/arm/mach-omap2/omap_hwmod.h                   |    7 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    3 +
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |    6 ++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    4 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 +-
 arch/arm/mach-omap2/serial.c                       |   31 ------
 drivers/tty/serial/omap-serial.c                   |   23 ----
 include/linux/platform_data/serial-omap.h          |    2 -
 9 files changed, 48 insertions(+), 145 deletions(-)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)


5YklPSOrg1rhK1WxoRFw
=OI73
-----END PGP SIGNATURE-----


From wenyou.yang at atmel.com  Sun May 19 21:05:10 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Mon, 20 May 2013 09:05:10 +0800
Subject: [PATCH] Change internal SRAM memory type to "MT_MEMORY_SO"
Message-ID: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>

Hi Russell,

This patch is to change the internal SRAM memory type to "MT_MEMORY_SO", the right type.

It tested on sama5d3xek boards.

It based on v3.10-rc1.

Best Regards,
Wenyou Yang

Wenyou Yang (1):
  ARM: at91: Fix: Change internal SRAM memory type to "MT_MEMORY_SO"

 arch/arm/mach-at91/setup.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
1.7.9.5



From wenyou.yang at atmel.com  Sun May 19 21:06:19 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Mon, 20 May 2013 09:06:19 +0800
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>

Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
---
 arch/arm/mach-at91/setup.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index e2f4bdd..d68be6c 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -80,7 +80,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 
 	desc->pfn = __phys_to_pfn(base);
 	desc->length = length;
-	desc->type = MT_DEVICE;
+	desc->type = MT_MEMORY_SO;
 
 	pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
 		base, length, desc->virtual);
-- 
1.7.9.5



From shawn.guo at linaro.org  Sun May 19 22:27:49 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 10:27:49 +0800
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
In-Reply-To: <1368684924-1560-1-git-send-email-b35083@freescale.com>
References: <1368684924-1560-1-git-send-email-b35083@freescale.com>
Message-ID: <20130520022747.GA25113@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:15:24PM +0800, Jingchang Lu wrote:
> Add Freescale Vybrid MVF600 period interrupt timer support.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   move the pit driver to drivers/clocksource.
> 
>  drivers/clocksource/Kconfig            |   5 +
>  drivers/clocksource/Makefile           |   1 +
>  drivers/clocksource/mvf600_pit_timer.c | 224 +++++++++++++++++++++++++++++++++

This is a driver for PIT, a timer IP block found on mvf family.  Even
though we prefer to use particular SoC name to specify the compatibility
and version of the block, all the versions of the IP block should be
ideally supported by single PIT driver.  This is just like we have
drivers spi-imx and i2c-imx support all SPI and I2C controllers found on
IMX SoCs.

That said, I suggest you use family name "mvf" to name the driver,
Kconfig symbol etc. and use "mvf600" only in compatible string.

>  3 files changed, 230 insertions(+)
>  create mode 100644 drivers/clocksource/mvf600_pit_timer.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index f151c6c..2808a76 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
>  	  Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
>  	  for all devicetree enabled platforms. This driver will be
>  	  needed only on systems that do not have the Exynos MCT available.
> +
> +config MVF600_PIT_TIMER
> +	bool
> +	help
> +	  Support for Period Interrupt Timer on Freescale Vybrid MVF600 SoC.
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 8d979c7..f471ca3 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
>  obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
>  obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
>  obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
> +obj-$(CONFIG_MVF600_PIT_TIMER)	+= mvf600_pit_timer.o
>  
>  obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
>  obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
> diff --git a/drivers/clocksource/mvf600_pit_timer.c b/drivers/clocksource/mvf600_pit_timer.c
> new file mode 100644
> index 0000000..74f7963
> --- /dev/null
> +++ b/drivers/clocksource/mvf600_pit_timer.c
> @@ -0,0 +1,224 @@
> +/*
> + *  Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/clockchips.h>
> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <asm/sched_clock.h>
> +
> +/*
> + * 8 timers: pit0 - pit7,
> + * Each takes 0x10 Bytes register sapce

s/sapce/space

> + */
> +#define PITMCR		0x00
> +#define PIT0_OFFSET	0x100
> +#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
> +#define PITLDVAL	0x00
> +#define PITCVAL		0x04
> +#define PITTCTRL	0x08
> +#define PITTFLG		0x0c
> +
> +#define PITTCTRL_TEN		(0x1 << 0)
> +#define PITTCTRL_TIE		(0x1 << 1)
> +#define	PITCTRL_CHN		(0x1 << 2)

Use space than tab between "#define" and macro name.

> +
> +#define PITTFLG_TIF		0x1
> +
> +static struct clock_event_device clockevent_pit;
> +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
> +
> +static void __iomem *clksrc_base;
> +static void __iomem *clkevt_base;
> +static void __iomem *sched_clock_reg;
> +static unsigned long pit_cycle_per_jiffy;
> +
> +static inline void pit_timer_enable(void)
> +{
> +	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_timer_disable(void)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_disable(void)
> +{
> +	unsigned long val;
> +
> +	val = __raw_readl(clkevt_base + PITTCTRL);
> +	val &= ~PITTCTRL_TIE;
> +	__raw_writel(val, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_enable(void)
> +{
> +	unsigned long val;
> +
> +	val = __raw_readl(clkevt_base + PITTCTRL);
> +	val |= PITTCTRL_TIE;
> +	__raw_writel(val, clkevt_base + PITTCTRL);
> +}
> +
> +static void pit_irq_acknowledge(void)
> +{
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +}
> +
> +static unsigned int pit_read_sched_clock(void)
> +{
> +	return __raw_readl(sched_clock_reg);
> +}
> +
> +
> +static int __init pit_clocksource_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	sched_clock_reg = clksrc_base + PITCVAL;
> +
> +	setup_sched_clock(pit_read_sched_clock, 32, c);
> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "mvf600-pit", c,
> +			300, 32, clocksource_mmio_readl_down);
> +}
> +
> +/* set clock event */
> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_irq_acknowledge();
> +	pit_timer_enable();
> +
> +	return 0;
> +}
> +
> +static void pit_set_mode(enum clock_event_mode mode,
> +				struct clock_event_device *evt)
> +{
> +	unsigned long flags;
> +
> +	local_irq_save(flags);
> +
> +	pit_timer_disable();
> +	pit_irq_acknowledge();
> +
> +	/* Remember timer mode */
> +	clockevent_mode = mode;
> +	local_irq_restore(flags);
> +
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +
Nit: remove this blank line.

> +		__raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
> +		pit_timer_enable();
> +
Ditto

> +		break;
> +	case CLOCK_EVT_MODE_ONESHOT:
> +
> +		break;
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_RESUME:
> +
Ditto

> +		break;
> +	default:
> +		WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
> +		break;
> +	}
> +}
> +
> +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = &clockevent_pit;
> +
> +	pit_irq_acknowledge();
> +
> +	if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT)
> +		pit_timer_disable();
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction pit_timer_irq = {
> +	.name		= "MVF600 pit timer",
> +	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= pit_timer_interrupt,
> +};
> +
> +static struct clock_event_device clockevent_pit = {
> +	.name		= "MVF600 pit timer",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= pit_set_mode,
> +	.set_next_event	= pit_set_next_event,
> +	.rating		= 300,
> +};
> +
> +static int __init pit_clockevent_init(struct clk *pit_clk)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	clockevent_pit.cpumask = cpumask_of(0);
> +	clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00);
> +
> +	return 0;
> +}
> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	int irq;
> +
> +	if (!np) {
> +		pr_err("Failed to find MVF600 pit DT node\n");
> +		BUG();
> +	}
> +
> +	timer_base = of_iomap(np, 0);
> +	WARN_ON(!timer_base);
> +
> +	/* choose PIT2 as clocksource, PIT3 as clockevent dev */

Reading the comment, I have a natural question - what PIT0 and PIT1 are
used for?

Shawn

> +	clksrc_base = timer_base + PITn_OFFSET(2);
> +	clkevt_base = timer_base + PITn_OFFSET(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +
> +	pit_clk = of_clk_get(np, 0);
> +	if (IS_ERR(pit_clk)) {
> +		pr_err("Vybrid MVF600 pit timer: unable to get clk\n");
> +		return;
> +	}
> +
> +	clk_prepare_enable(pit_clk);
> +
> +	pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
> +
> +	__raw_writel(0x0, timer_base + PITMCR);
> +
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +	__raw_writel(0xffffffff, clkevt_base + PITLDVAL);
> +
> +	__raw_writel(0, clksrc_base + PITTCTRL);
> +	__raw_writel(0xffffffff, clksrc_base + PITLDVAL);
> +	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
> +
> +	pit_clocksource_init(pit_clk);
> +
> +	setup_irq(irq, &pit_timer_irq);
> +
> +	pit_clockevent_init(pit_clk);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf600-pit", pit_timer_init);
> -- 
> 1.8.0
> 
> 



From paul at pwsan.com  Sun May 19 22:47:21 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 20 May 2013 02:47:21 +0000 (UTC)
Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output
 on SoC pad
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EC8C081@DBDE04.ent.ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83EC8C081@DBDE04.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1305200246080.2656@utopia.booyaka.com>

On Fri, 17 May 2013, Hiremath, Vaibhav wrote:

> Tony, Paul and Benoit,
> 
> Any update on this series?

Most of the changes are DT-related, so it should probably go in via 
Beno?t.  I'll ack the clock side, but have a comment on patch 2, to be 
sent shortly.


- Paul

From paul at pwsan.com  Sun May 19 22:50:17 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 20 May 2013 02:50:17 +0000 (UTC)
Subject: [PATCH 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2 as part
 of init
In-Reply-To: <1367919574-21353-2-git-send-email-hvaibhav@ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <1367919574-21353-2-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.00.1305200248280.2656@utopia.booyaka.com>

On Tue, 7 May 2013, Vaibhav Hiremath wrote:

> clkout2 comes out on the pad and is being used by various
> external on-board peripherals like, Audio codecs and stuff.
> So enable the clkout2 by default during init sequence itself.

I don't like this: the clock should be enabled by the drivers for those 
external peripherals, not enabled by default.  So I think you should 
reconsider the part of the patch that enables it upon init.  But if you 
really want to do this, I'm not inclined to stand in the way; you can add 
my ack.

- Paul

> 
> Also, add the missing entry of "clkout2_ck" to the clock table.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> ---
>  arch/arm/mach-omap2/cclock33xx_data.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
> index 6fd0ed1..a8140b6 100644
> --- a/arch/arm/mach-omap2/cclock33xx_data.c
> +++ b/arch/arm/mach-omap2/cclock33xx_data.c
> @@ -979,6 +979,7 @@ static struct omap_clk am33xx_clks[] = {
>  	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
>  	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
>  	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
> +	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
>  };
>  
>  
> @@ -989,6 +990,7 @@ static const char *enable_init_clks[] = {
>  	"l4hs_gclk",
>  	"l4fw_gclk",
>  	"l4ls_gclk",
> +	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
>  };
>  
>  int __init am33xx_clk_init(void)
> -- 
> 1.7.0.4
> 


- Paul


From paul at pwsan.com  Sun May 19 22:51:02 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 20 May 2013 02:51:02 +0000 (UTC)
Subject: [PATCH 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad used
 for clock output
In-Reply-To: <1367919574-21353-3-git-send-email-hvaibhav@ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <1367919574-21353-3-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.00.1305200250250.2656@utopia.booyaka.com>

Hi

something that you should fix:

On Tue, 7 May 2013, Vaibhav Hiremath wrote:

> xdma_event_intr1.clkout2 pad can be used to source clock
> from either 32K OSC or any of the PLL (except MPU) outputs.
> On the existing AM335x based boards (EVM, EVM-SK and Bone),
> this pad is used to feed the clock to audio codes.
> 
> So, this patch configures the pinmux to get clkout2 on the pad.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> ---
>  arch/arm/boot/dts/am335x-bone.dts  |    8 +++++++-
>  arch/arm/boot/dts/am335x-evm.dts   |    8 +++++++-
>  arch/arm/boot/dts/am335x-evmsk.dts |    8 +++++++-
>  3 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
> index bfba6fc..f4630a3 100644
> --- a/arch/arm/boot/dts/am335x-bone.dts
> +++ b/arch/arm/boot/dts/am335x-bone.dts
> @@ -26,7 +26,7 @@
>  
>  	am33xx_pinmux: pinmux at 44e10800 {
>  		pinctrl-names = "default";
> -		pinctrl-0 = <>;
> +		pinctrl-0 = <&clkout2_pin>;
>  
>  		user_leds_s0: user_leds_s0 {
>  			pinctrl-single,pins = <
> @@ -50,6 +50,12 @@
>  				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>  			>;
>  		};
> +
> +		clkout2_pin: pinumx_clkout2_pin {

"pinmux" is misspelled here and in several other parts of this file.




- Paul


From shawn.guo at linaro.org  Sun May 19 23:05:25 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 11:05:25 +0800
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <1368685096-13177-1-git-send-email-b35083@freescale.com>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
Message-ID: <20130520030523.GB25113@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:18:15PM +0800, Jingchang Lu wrote:
> Add Freescale lpuart driver support. The lpuart device
> can be founded on Vybrid MVF600 and Layerscape LS-1 SoCs.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   change the uart driver name from mvf to lpuart for further share between SoCs.

I do not think it's going to be a problem to name the IP with mvf family
name even though it will be used on LS-1 too.  That can simply telling
the history that the IP is firstly used on mvf family and then get
reused on LS-1.  But I'm fine you name the driver in a generic way,
purely using the IP name, if you feel like to do that strongly ...

>   add bind doc in Documentation/devicetree/bindings/tty/serial.
>   remove unused #include header lines.
>   clean up code.
> 
>  .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
>  drivers/tty/serial/Kconfig                         |  14 +
>  drivers/tty/serial/Makefile                        |   1 +
>  drivers/tty/serial/fsl_lpuart.c                    | 916 +++++++++++++++++++++
>  include/uapi/linux/serial_core.h                   |   3 +
>  5 files changed, 948 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
>  create mode 100644 drivers/tty/serial/fsl_lpuart.c
> 
> diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
> new file mode 100644
> index 0000000..46ffdb1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
> @@ -0,0 +1,14 @@
> +* Freescale Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
> +
> +Required properties:
> +- compatible : Should be "fsl,lpuart"

... but I don't think purely using IP name as the compatible string is a
such a good idea, since it tells nothing about compatibility/version
info.  So please encode the SoC name (mvf600) in the string.

> +- reg : Address and length of the register set for the device
> +- interrupts : Should contain uart interrupt
> +
> +Example:
> +
> +uart0: serial at 40027000 {
> +	       compatible = "fsl,lpuart";
> +	       reg = <0x40027000 0x1000>;
> +	       interrupts = <0 61 0x00>;
> +       };
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 7e7006f..2cea1a0 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1484,6 +1484,20 @@ config SERIAL_RP2_NR_UARTS
>  	  If multiple cards are present, the default limit of 32 ports may
>  	  need to be increased.
>  
> +config SERIAL_FSL_LPUART
> +	bool "Freescale Lpuart serial port support"
> +	select SERIAL_CORE
> +	help
> +	  Support for the on-chip LPUARTs on some Freescal SOCs.
> +
> +config SERIAL_FSL_LPUART_CONSOLE
> +	bool "Console on Vybrid serial port"

This should be updated accordingly since the prompt text of
SERIAL_FSL_LPUART has changed?

Shawn

> +	depends on SERIAL_FSL_LPUART
> +	select SERIAL_CORE_CONSOLE
> +	help
> +	  If you have enabled the lpuart serial port on the Freescale SoCs,
> +	  you can make it the console by answering Y to this option.
> +
>  endmenu



From B35083 at freescale.com  Sun May 19 23:08:54 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Mon, 20 May 2013 03:08:54 +0000
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
In-Reply-To: <20130520022747.GA25113@S2101-09.ap.freescale.net>
References: <1368684924-1560-1-git-send-email-b35083@freescale.com>
 <20130520022747.GA25113@S2101-09.ap.freescale.net>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CB223@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo at linaro.org]
>Sent: Monday, May 20, 2013 10:28 AM
>To: Lu Jingchang-B35083
>Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
>john.stultz at linaro.org; tglx at linutronix.de; s.hauer at pengutronix.de
>Subject: Re: [PATCH v3] clocksource: add MVF600 pit timer support
>
>On Thu, May 16, 2013 at 02:15:24PM +0800, Jingchang Lu wrote:
>> Add Freescale Vybrid MVF600 period interrupt timer support.
>>
>> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
>> ---
>> v3:
>>   move the pit driver to drivers/clocksource.
>>
>>  drivers/clocksource/Kconfig            |   5 +
>>  drivers/clocksource/Makefile           |   1 +
>>  drivers/clocksource/mvf600_pit_timer.c | 224
>> +++++++++++++++++++++++++++++++++
>
>This is a driver for PIT, a timer IP block found on mvf family.  Even
>though we prefer to use particular SoC name to specify the compatibility
>and version of the block, all the versions of the IP block should be
>ideally supported by single PIT driver.  This is just like we have drivers
>spi-imx and i2c-imx support all SPI and I2C controllers found on IMX SoCs.
>That said, I suggest you use family name "mvf" to name the driver, Kconfig
>symbol etc. and use "mvf600" only in compatible string.
>
[Lu Jingchang-B35083] 
  I am not sure MVF5xx and MVF7xx have the same PIT block, if you have information that it is the same on other Vybrid SoCs, it is ok to change the driver name to mvf. Thanks!
>>  3 files changed, 230 insertions(+)
>> +
>> +	/* choose PIT2 as clocksource, PIT3 as clockevent dev */
>
>Reading the comment, I have a natural question - what PIT0 and PIT1 are
>used for?
>
[Lu Jingchang-B35083] 
PIT0 and PIT1 can be chained to build a 64-bit timer, so PIT2 and PIT3 are selected as the clocksource and clockevent device, and leave PIT0 and PIT1 unused for anyone else who needs them. Thanks!
>




From shawn.guo at linaro.org  Sun May 19 23:21:16 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 11:21:16 +0800
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CB223@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1368684924-1560-1-git-send-email-b35083@freescale.com>
 <20130520022747.GA25113@S2101-09.ap.freescale.net>
 <B56CDBE15CE27145A4B77D2D24263E851CB223@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <20130520032114.GC25113@S2101-09.ap.freescale.net>

On Mon, May 20, 2013 at 03:08:54AM +0000, Lu Jingchang-B35083 wrote:
> [Lu Jingchang-B35083] 
>   I am not sure MVF5xx and MVF7xx have the same PIT block, if you have information that it is the same on other Vybrid SoCs, it is ok to change the driver name to mvf. Thanks!

Even the PIT block on other Vybrid SoCs have differences from the one
integrated on mvf600, we can handle them using device tree compatible
string.  And that's why we need to encode SoC name in compatible.

> [Lu Jingchang-B35083] 
> PIT0 and PIT1 can be chained to build a 64-bit timer, so PIT2 and PIT3 are selected as the clocksource and clockevent device, and leave PIT0 and PIT1 unused for anyone else who needs them. Thanks!

This could be an useful info to be in the comment.

Shawn



From voice.shen at atmel.com  Sun May 19 23:26:02 2013
From: voice.shen at atmel.com (Bo Shen)
Date: Mon, 20 May 2013 11:26:02 +0800
Subject: [PATCH 1/5] usb: add Atmel USBA UDC DT support
In-Reply-To: <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <519997CA.8010503@atmel.com>

Hi Jean-Christophe,

On 5/17/2013 22:42, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Allow to compile the driver all the time if AT91 enabled.
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org
> ---
>   .../devicetree/bindings/usb/atmel-usb.txt          |   82 ++++++++
>   drivers/usb/gadget/Kconfig                         |    2 +-
>   drivers/usb/gadget/atmel_usba_udc.c                |  214 +++++++++++++++-----
>   drivers/usb/gadget/atmel_usba_udc.h                |    1 +
>   4 files changed, 244 insertions(+), 55 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
> index 60bd215..878556b2 100644
> --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
> @@ -47,3 +47,85 @@ usb1: gadget at fffa4000 {
>   	interrupts = <10 4>;
>   	atmel,vbus-gpio = <&pioC 5 0>;
>   };
> +
> +Atmel High-Speed USB device controller
> +
> +Required properties:
> + - compatible: Should be "atmel,at91sam9rl-udc"
> + - reg: Address and length of the register set for the device
> + - interrupts: Should contain macb interrupt

s/macb/udphs

> + - ep childnode: To specifiy the number of endpoints and their properties.

s/specifiy/specify

> +
> +Optional properties:
> + - atmel,vbus-gpio: If present, specifies a gpio that needs to be
> +   activated for the bus to be powered.
> +
> +Required child node properties:
> + - name: Name of the endpoint.
> + - reg: Num of the endpoint.
> + - atmel,fifo-size: Size of the fifo.
> + - atmel,nb-banks: Number of banks.
> + - atmel,can-dma: Boolean to specify if the endpoint support DMA.
> + - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
> +
> +usb2: gadget at fff78000 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	compatible = "atmel,at91sam9rl-udc";
> +	reg = <0x00600000 0x80000
> +	       0xfff78000 0x400>;
> +	interrupts = <27 4>;

s/interrupts = <27 4>/interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;

> +	atmel,vbus-gpio = <&pioB 19 0>;
> +
> +	ep0 {
> +		reg = <0>;
> +		atmel,fifo-size = <64>;
> +		atmel,nb-banks = <1>;
> +	};
> +
> +	ep1 {
> +		reg = <1>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <2>;
> +		atmel,can-dma;
> +		atmel,can-isoc;
> +	};
> +
> +	ep2 {
> +		reg = <2>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <2>;
> +		atmel,can-dma;
> +		atmel,can-isoc;
> +	};
> +
> +	ep3 {
> +		reg = <3>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma;
> +	};
> +
> +	ep4 {
> +		reg = <4>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma;
> +	};
> +
> +	ep5 {
> +		reg = <5>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma;
> +		atmel,can-isoc;
> +	};
> +
> +	ep6 {
> +		reg = <6>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma;
> +		atmel,can-isoc;
> +	};
> +};
> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
> index 83300d9..5e47d50 100644
> --- a/drivers/usb/gadget/Kconfig
> +++ b/drivers/usb/gadget/Kconfig
> @@ -156,7 +156,7 @@ config USB_LPC32XX
>
>   config USB_ATMEL_USBA
>   	tristate "Atmel USBA"
> -	depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
> +	depends on AVR32 || ARCH_AT91
>   	help
>   	  USBA is the integrated high-speed USB Device controller on
>   	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
> index f2a970f..b3084b9 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/atmel_usba_udc.c
> @@ -22,6 +22,8 @@
>   #include <linux/usb/atmel_usba_udc.h>
>   #include <linux/delay.h>
>   #include <linux/platform_data/atmel.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
>
>   #include <asm/gpio.h>
>
> @@ -1835,9 +1837,143 @@ static int atmel_usba_stop(struct usb_gadget *gadget,
>   	return 0;
>   }
>
> -static int __init usba_udc_probe(struct platform_device *pdev)
> +#ifdef CONFIG_OF
> +static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
> +						    struct usba_udc *udc)
> +{
> +	u32 val;
> +	const char *name;
> +	enum of_gpio_flags flags;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct device_node *pp;
> +	int i, ret;
> +	struct usba_ep *eps, *ep;
> +
> +	udc->num_ep = 0;
> +
> +	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
> +						&flags);
> +	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
> +
> +	pp = NULL;
> +	while ((pp = of_get_next_child(np, pp)))
> +		udc->num_ep++;
> +
> +	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
> +			   GFP_KERNEL);

Using devm_kzalloc will cause issue when build as modules, and load and 
unload this driver, the second time unload, it will come out following 
segment fault, log as following. Using kzalloc will fix it.

---8>---
Unable to handle kernel NULL pointer dereference at virtual address 00000054
pgd = c7bac000
[00000054] *pgd=27b6f831, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#1] ARM
Modules linked in: atmel_usba_udc(-) [last unloaded: atmel_usba_udc]
CPU: 0 PID: 519 Comm: rmmod Not tainted 3.10.0-rc1+ #13
task: c796d580 ti: c7b68000 task.ti: c7b68000
PC is at kfree+0x4c/0xb4
LR is at free_module+0xe4/0x168
pc : [<c007470c>]    lr : [<c0045884>]    psr: 40000093
sp : c7b69f10  ip : 00000010  fp : 00000000
r10: 00000000  r9 : c7b68000  r8 : c0009484
r7 : 00000000  r6 : c7ba0c00  r5 : a0000013  r4 : bf009240
r3 : c061d400  r2 : 00000000  r1 : 00007ba0  r0 : c7ba0c00
Flags: nZcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 0005317f  Table: 27bac000  DAC: 00000015
Process rmmod (pid: 519, stack limit = 0xc7b681b8)
Stack: (0xc7b69f10 to 0xc7b6a000)
9f00:                                     0000000f bf009240 000000a8 
bf009288
9f20: c7afe6a8 c0045884 bf009240 00000000 00000013 becbfbd0 c0009484 
c0045c10
9f40: 00000000 656d7461 73755f6c 755f6162 b6006364 b6f1c000 c796d580 
b6f1c000
9f60: b6f1c000 c7afb140 00000000 becbf984 00005401 00000001 c7b68000 
00000000
9f80: bf009240 00000880 c7b69f8c 00000000 becbf9bc b6f0a380 00000880 
becbfbd0
9fa0: 00000081 c0009320 b6f0a380 00000880 becbfbd0 00000880 0000000e 
00000000
9fc0: b6f0a380 00000880 becbfbd0 00000081 0000009c 0000ce8c 0000b7f0 
00000000
9fe0: b6ebda20 becbfbc0 00019750 b6ebda2c a0000010 becbfbd0 00000000 
00000000
[<c007470c>] (kfree+0x4c/0xb4) from [<c0045884>] (free_module+0xe4/0x168)
[<c0045884>] (free_module+0xe4/0x168) from [<c0045c10>] 
(SyS_delete_module+0x1d8/0x210)
[<c0045c10>] (SyS_delete_module+0x1d8/0x210) from [<c0009320>] 
(ret_fast_syscall+0x0/0x2c)
Code: e7922281 e3120902 1593301c e593701c (e5974054)
---[ end trace cb98ff9cd16ea901 ]---
Segmentation fault
---<8---

> +	if (!eps)
> +		return ERR_PTR(-ENOMEM);
> +
> +	udc->gadget.ep0 = &eps[0].ep;
> +
> +	INIT_LIST_HEAD(&eps[0].ep.ep_list);
> +
> +	pp = NULL;
> +	i = 0;
> +	while ((pp = of_get_next_child(np, pp))) {
> +		ep = &eps[i];
> +
> +		ret = of_property_read_u32(pp, "reg", &val);
> +		if (ret) {
> +			dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
> +			goto err;
> +		}
> +		ep->index = val;
> +
> +		ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
> +		if (ret) {
> +			dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
> +			goto err;
> +		}
> +		ep->fifo_size = val;
> +
> +		ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
> +		if (ret) {
> +			dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
> +			goto err;
> +		}
> +		ep->nr_banks = val;
> +
> +		ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
> +		ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
> +
> +		ret = of_property_read_string(pp, "name", &name);
> +		ep->ep.name = name;
> +
> +		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
> +		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
> +		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
> +		ep->ep.ops = &usba_ep_ops;
> +		ep->ep.maxpacket = ep->fifo_size;
> +		ep->udc = udc;
> +		INIT_LIST_HEAD(&ep->queue);
> +
> +		if (i)
> +			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
> +
> +		i++;
> +	}
> +
> +	return eps;
> +err:
> +	return ERR_PTR(ret);
> +}
> +#else
> +static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
> +						    struct usba_udc *udc)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +#endif
> +
> +static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
> +						 struct usba_udc *udc)
>   {
>   	struct usba_platform_data *pdata = pdev->dev.platform_data;
> +	struct usba_ep *eps;
> +	int i;
> +
> +	if (!pdata)
> +		return ERR_PTR(-ENXIO);
> +
> +	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
> +			   GFP_KERNEL);
> +	if (!eps)
> +		return ERR_PTR(-ENOMEM);
> +
> +	udc->gadget.ep0 = &eps[0].ep;
> +
> +	udc->vbus_pin = pdata->vbus_pin;
> +	udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
> +	udc->num_ep = pdata->num_ep;
> +
> +	INIT_LIST_HEAD(&eps[0].ep.ep_list);
> +
> +	for (i = 0; i < pdata->num_ep; i++) {
> +		struct usba_ep *ep = &eps[i];
> +
> +		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
> +		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
> +		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
> +		ep->ep.ops = &usba_ep_ops;
> +		ep->ep.name = pdata->ep[i].name;
> +		ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size;
> +		ep->udc = udc;
> +		INIT_LIST_HEAD(&ep->queue);
> +		ep->nr_banks = pdata->ep[i].nr_banks;
> +		ep->index = pdata->ep[i].index;
> +		ep->can_dma = pdata->ep[i].can_dma;
> +		ep->can_isoc = pdata->ep[i].can_isoc;
> +
> +		if (i)
> +			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
> +	}
> +
> +	return eps;
> +}
> +
> +static int __init usba_udc_probe(struct platform_device *pdev)
> +{
>   	struct resource *regs, *fifo;
>   	struct clk *pclk, *hclk;
>   	struct usba_udc *udc = &the_udc;
> @@ -1845,7 +1981,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>
>   	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
>   	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
> -	if (!regs || !fifo || !pdata)
> +	if (!regs || !fifo)
>   		return -ENXIO;
>
>   	irq = platform_get_irq(pdev, 0);
> @@ -1891,46 +2027,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>   	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
>   	clk_disable(pclk);
>
> -	usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
> -			  GFP_KERNEL);
> -	if (!usba_ep)
> -		goto err_alloc_ep;
> -
> -	the_udc.gadget.ep0 = &usba_ep[0].ep;
> -
> -	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
> -	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
> -	usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
> -	usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
> -	usba_ep[0].ep.ops = &usba_ep_ops;
> -	usba_ep[0].ep.name = pdata->ep[0].name;
> -	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
> -	usba_ep[0].udc = &the_udc;
> -	INIT_LIST_HEAD(&usba_ep[0].queue);
> -	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
> -	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
> -	usba_ep[0].index = pdata->ep[0].index;
> -	usba_ep[0].can_dma = pdata->ep[0].can_dma;
> -	usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
> -
> -	for (i = 1; i < pdata->num_ep; i++) {
> -		struct usba_ep *ep = &usba_ep[i];
> -
> -		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
> -		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
> -		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
> -		ep->ep.ops = &usba_ep_ops;
> -		ep->ep.name = pdata->ep[i].name;
> -		ep->ep.maxpacket = pdata->ep[i].fifo_size;
> -		ep->udc = &the_udc;
> -		INIT_LIST_HEAD(&ep->queue);
> -		ep->fifo_size = pdata->ep[i].fifo_size;
> -		ep->nr_banks = pdata->ep[i].nr_banks;
> -		ep->index = pdata->ep[i].index;
> -		ep->can_dma = pdata->ep[i].can_dma;
> -		ep->can_isoc = pdata->ep[i].can_isoc;
> +	if (pdev->dev.of_node)
> +		usba_ep = atmel_udc_of_init(pdev, udc);
> +	else
> +		usba_ep = usba_udc_pdata(pdev, udc);
>
> -		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
> +	if (IS_ERR(usba_ep)) {
> +		ret = PTR_ERR(usba_ep);
> +		goto err_alloc_ep;
>   	}
>
>   	ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
> @@ -1941,16 +2045,12 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>   	}
>   	udc->irq = irq;
>
> -	if (gpio_is_valid(pdata->vbus_pin)) {
> -		if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
> -			udc->vbus_pin = pdata->vbus_pin;
> -			udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
> -
> +	if (gpio_is_valid(udc->vbus_pin)) {
> +		if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
>   			ret = request_irq(gpio_to_irq(udc->vbus_pin),
>   					usba_vbus_irq, 0,
>   					"atmel_usba_udc", udc);
>   			if (ret) {
> -				gpio_free(udc->vbus_pin);
>   				udc->vbus_pin = -ENODEV;
>   				dev_warn(&udc->pdev->dev,
>   					 "failed to request vbus irq; "
> @@ -1969,16 +2069,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>   		goto err_add_udc;
>
>   	usba_init_debugfs(udc);
> -	for (i = 1; i < pdata->num_ep; i++)
> +	for (i = 1; i < udc->num_ep; i++)
>   		usba_ep_init_debugfs(udc, &usba_ep[i]);
>
>   	return 0;
>
>   err_add_udc:
> -	if (gpio_is_valid(pdata->vbus_pin)) {
> +	if (gpio_is_valid(udc->vbus_pin))
>   		free_irq(gpio_to_irq(udc->vbus_pin), udc);
> -		gpio_free(udc->vbus_pin);
> -	}
>
>   	free_irq(irq, udc);
>   err_request_irq:
> @@ -2001,19 +2099,17 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
>   {
>   	struct usba_udc *udc;
>   	int i;
> -	struct usba_platform_data *pdata = pdev->dev.platform_data;
>
>   	udc = platform_get_drvdata(pdev);
>
>   	usb_del_gadget_udc(&udc->gadget);
>
> -	for (i = 1; i < pdata->num_ep; i++)
> +	for (i = 1; i < udc->num_ep; i++)
>   		usba_ep_cleanup_debugfs(&usba_ep[i]);
>   	usba_cleanup_debugfs(udc);
>
>   	if (gpio_is_valid(udc->vbus_pin)) {
>   		free_irq(gpio_to_irq(udc->vbus_pin), udc);
> -		gpio_free(udc->vbus_pin);
>   	}
>
>   	free_irq(udc->irq, udc);
> @@ -2026,11 +2122,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
>   	return 0;
>   }
>
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmel_udc_dt_ids[] = {
> +	{ .compatible = "atmel,at91sam9rl-udc" },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
> +#endif
> +
>   static struct platform_driver udc_driver = {
>   	.remove		= __exit_p(usba_udc_remove),
>   	.driver		= {
>   		.name		= "atmel_usba_udc",
>   		.owner		= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(atmel_udc_dt_ids),
>   	},
>   };
>
> diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
> index d65a618..6999a26 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.h
> +++ b/drivers/usb/gadget/atmel_usba_udc.h
> @@ -317,6 +317,7 @@ struct usba_udc {
>   	int irq;
>   	int vbus_pin;
>   	int vbus_pin_inverted;
> +	int num_ep;
>   	struct clk *pclk;
>   	struct clk *hclk;
>
>

Best Regards,
Bo Shen



From B35083 at freescale.com  Sun May 19 23:26:50 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Mon, 20 May 2013 03:26:50 +0000
Subject: [PATCH v3] clocksource: add MVF600 pit timer support
In-Reply-To: <20130520032114.GC25113@S2101-09.ap.freescale.net>
References: <1368684924-1560-1-git-send-email-b35083@freescale.com>
 <20130520022747.GA25113@S2101-09.ap.freescale.net>
 <B56CDBE15CE27145A4B77D2D24263E851CB223@039-SN1MPN1-003.039d.mgd.msft.net>
 <20130520032114.GC25113@S2101-09.ap.freescale.net>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CB244@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo at linaro.org]
>Sent: Monday, May 20, 2013 11:21 AM
>To: Lu Jingchang-B35083
>Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
>john.stultz at linaro.org; tglx at linutronix.de; s.hauer at pengutronix.de
>Subject: Re: [PATCH v3] clocksource: add MVF600 pit timer support
>
>On Mon, May 20, 2013 at 03:08:54AM +0000, Lu Jingchang-B35083 wrote:
>> [Lu Jingchang-B35083]
>>   I am not sure MVF5xx and MVF7xx have the same PIT block, if you have
>information that it is the same on other Vybrid SoCs, it is ok to change
>the driver name to mvf. Thanks!
>
>Even the PIT block on other Vybrid SoCs have differences from the one
>integrated on mvf600, we can handle them using device tree compatible
>string.  And that's why we need to encode SoC name in compatible.
>
[Lu Jingchang-B35083] 
  Ok, I will rename the driver and the configure option, thanks!
>> [Lu Jingchang-B35083]
>> PIT0 and PIT1 can be chained to build a 64-bit timer, so PIT2 and PIT3
>are selected as the clocksource and clockevent device, and leave PIT0 and
>PIT1 unused for anyone else who needs them. Thanks!
>
>This could be an useful info to be in the comment.
>
[Lu Jingchang-B35083] 
  I will add a comment for this, thanks!




From shawn.guo at linaro.org  Sun May 19 23:32:09 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 11:32:09 +0800
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <1368685224-17915-1-git-send-email-b35083@freescale.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
Message-ID: <20130520033207.GD25113@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:20:23PM +0800, Jingchang Lu wrote:
> Adds Freescale Vybrid Family MVF600 pin controller
> driver to IMX iomuxc common driver framework.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   clean up code.
>   update binding document according recommendation.
> 
>  .../bindings/pinctrl/fsl,mvf600-pinctrl.txt        |  41 +++
>  drivers/pinctrl/Kconfig                            |   8 +
>  drivers/pinctrl/Makefile                           |   1 +
>  drivers/pinctrl/pinctrl-mvf600.c                   | 338 +++++++++++++++++++++
>  4 files changed, 388 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt
>  create mode 100644 drivers/pinctrl/pinctrl-mvf600.c
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt
> new file mode 100644
> index 0000000..a4d04d2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,mvf600-pinctrl.txt
> @@ -0,0 +1,41 @@
> +Freescale Vybrid IOMUX Controller

Freescale Vybrid MVF600 IOMUX Controller

> +
> +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
> +and usage.
> +
> +Required properties:
> +- compatible: "fsl,mvf600-iomuxc"
> +- fsl,pins: two integers array, represents a group of pins mux and config
> +  setting. The format is fsl,pins = < PIN_FUNC_ID >, PIN_FUNC_ID is a pin

fsl,pins = <PIN_FUNC_ID CONFIG>

> +  working on a specific function, CONFIG is the pad setting value such as
> +  pull-up, speed, ode for this pin. Please refer to Vybrid MVF600 datasheet
> +  for the valid pad config settings.
> +
> +CONFIG bits definition:
> +PAD_CTL_SPEED_LOW		(1 << 12)
> +PAD_CTL_SPEED_MED		(2 << 12)
> +PAD_CTL_SPEED_HIGH		(3 << 12)
> +PAD_CTL_SRE_FAST		(1 << 11)
> +PAD_CTL_SRE_SLOW		(0 << 11)
> +PAD_CTL_ODE			(1 << 10)
> +PAD_CTL_HYS			(1 << 9)
> +PAD_CTL_DSE_DISABLE		(0 << 6)
> +PAD_CTL_DSE_150ohm		(1 << 6)
> +PAD_CTL_DSE_75ohm		(2 << 6)
> +PAD_CTL_DSE_50ohm		(3 << 6)
> +PAD_CTL_DSE_37ohm		(4 << 6)
> +PAD_CTL_DSE_30ohm		(5 << 6)
> +PAD_CTL_DSE_25ohm		(6 << 6)
> +PAD_CTL_DSE_20ohm		(7 << 6)
> +PAD_CTL_PUS_100K_DOWN		(0 << 4)
> +PAD_CTL_PUS_47K_UP		(1 << 4)
> +PAD_CTL_PUS_100K_UP		(2 << 4)
> +PAD_CTL_PUS_22K_UP		(3 << 4)
> +PAD_CTL_PKE			(1 << 3)
> +PAD_CTL_PUE			(1 << 2)
> +PAD_CTL_OBE_ENABLE		(1 << 1)
> +PAD_CTL_IBE_ENABLE		(1 << 0)
> +PAD_CTL_OBE_IBE_ENABLE		(3 << 0)
> +
> +Please refer to mvf600-pinfunc.h in device tree source folder
> +for all available PIN_FUNC_ID for Vybrid.

for Vybrid MVF600.

> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 8f66924..5cb3987 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -108,6 +108,14 @@ config PINCTRL_IMX6SL
>  	help
>  	  Say Y here to enable the imx6sl pinctrl driver
>  
> +config PINCTRL_MVF600
> +	bool "Freescale Vybrid MVF600 pinctrl driver"
> +	depends on OF
> +	depends on SOC_MVF600
> +	select PINCTRL_IMX
> +	help
> +	  Say Y here to enable the Freescale Vybrid MVF600 pinctrl driver
> +
>  config PINCTRL_LANTIQ
>  	bool
>  	depends on LANTIQ
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 34c4ae6..dfec292 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o
>  obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o
>  obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
>  obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
> +obj-$(CONFIG_PINCTRL_MVF600)	+= pinctrl-mvf600.o
>  
>  obj-$(CONFIG_PLAT_ORION)        += mvebu/
>  obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
> diff --git a/drivers/pinctrl/pinctrl-mvf600.c b/drivers/pinctrl/pinctrl-mvf600.c
> new file mode 100644
> index 0000000..6e2bcc0
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-mvf600.c
> @@ -0,0 +1,338 @@
> +/*
> + * MVF600 pinctrl driver based on imx pinmux and pinconf core
> + *
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-imx.h"
> +
> +enum mvf600_pads {
> +	MVF600_PAD_PTA6 = 0,
> +	MVF600_PAD_PTA8 = 1,
> +	MVF600_PAD_PTA9 = 2,
...
> +	MVF600_PAD_PTE27 = 132,
> +	MVF600_PAD_PTE28 = 133,
> +	MVF600_PAD_PTA7 = 134,
> +	};

No tab here, please.

> +
> +/* Pad names for the pinmux subsystem */
> +static const struct pinctrl_pin_desc mvf600_pinctrl_pads[] = {
...
> +};
> +
> +static struct imx_pinctrl_soc_info mvf600_pinctrl_info = {
> +	.pins = mvf600_pinctrl_pads,
> +	.npins = ARRAY_SIZE(mvf600_pinctrl_pads),
> +	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,

The flags should be introduced in the same patch where they are used
in the first place.

Shawn

> +};
> +
> +static struct of_device_id mvf600_pinctrl_of_match[] = {
> +	{ .compatible = "fsl,mvf600-iomuxc", },
> +	{ /* sentinel */ }
> +};
> +
> +static int mvf600_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return imx_pinctrl_probe(pdev, &mvf600_pinctrl_info);
> +}
> +
> +static struct platform_driver mvf600_pinctrl_driver = {
> +	.driver = {
> +		.name = "mvf600-pinctrl",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_match_ptr(mvf600_pinctrl_of_match),
> +	},
> +	.probe = mvf600_pinctrl_probe,
> +	.remove = imx_pinctrl_remove,
> +};
> +
> +static int __init mvf600_pinctrl_init(void)
> +{
> +	return platform_driver_register(&mvf600_pinctrl_driver);
> +}
> +arch_initcall(mvf600_pinctrl_init);
> +
> +static void __exit mvf600_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&mvf600_pinctrl_driver);
> +}
> +module_exit(mvf600_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("Freescale MVF600 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.0
> 
> 



From shawn.guo at linaro.org  Sun May 19 23:51:59 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 11:51:59 +0800
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <20130520033207.GD25113@S2101-09.ap.freescale.net>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <20130520033207.GD25113@S2101-09.ap.freescale.net>
Message-ID: <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>

On 20 May 2013 11:32, Shawn Guo <shawn.guo at linaro.org> wrote:
>> +static struct imx_pinctrl_soc_info mvf600_pinctrl_info = {
>> +     .pins = mvf600_pinctrl_pads,
>> +     .npins = ARRAY_SIZE(mvf600_pinctrl_pads),
>> +     .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
>
> The flags should be introduced in the same patch where they are used
> in the first place.
>
I just found what you need to do is just to reverse the patch order,
having this patch be the second one.

Shawn


From tushar.behera at linaro.org  Sun May 19 23:53:19 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Mon, 20 May 2013 09:23:19 +0530
Subject: [PATCH] ARM: dts: add max8997 device node for exynos4210-origen
 board
In-Reply-To: <518C9807.80906@linaro.org>
References: <1353664412-17678-1-git-send-email-thomas.abraham@linaro.org>
 <50EA598D.6090604@linaro.org> <518C9807.80906@linaro.org>
Message-ID: <51999E2F.9030703@linaro.org>

On 05/10/2013 12:17 PM, Tushar Behera wrote:
> On 01/07/2013 10:43 AM, Tushar Behera wrote:
>> On 11/23/2012 03:23 PM, Thomas Abraham wrote:
>>> Add max8997 regulator device node for exynos4210-origen board and list
>>> all the supported regulators.
>>>
>>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>>
>> Tested-by: Tushar Behera <tushar.behera at linaro.org>
>>
> Kukjin,
> 
> This patch got missed for 3.10 merge window. This patch still applies on
> the latest mainline kernel and is essential for Origen board. Would you
> please take this patch?
> 

Ping !!!

-- 
Tushar Behera


From shawn.guo at linaro.org  Mon May 20 00:01:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 12:01:05 +0800
Subject: [PATCH v3 2/2] pinctrl: imx: add MVF600 support to imx pinctrl
 framework
In-Reply-To: <1368685224-17915-2-git-send-email-b35083@freescale.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <1368685224-17915-2-git-send-email-b35083@freescale.com>
Message-ID: <20130520040103.GE25113@S2101-09.ap.freescale.net>

On Thu, May 16, 2013 at 02:20:24PM +0800, Jingchang Lu wrote:
> On some platforms such as MVF600, offset of mux and pad ctrl register
> may be zero, and the mux_mode and config_val are in one 32-bit register.
> This patch adds support to imx core pinctrl framework to handle these
> cases.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>



From sboyd at codeaurora.org  Mon May 20 00:15:08 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Sun, 19 May 2013 21:15:08 -0700
Subject: [PATCH v3 2/4] clk: add support for clock reparent on set_rate
In-Reply-To: <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
 <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130520041508.GA27676@codeaurora.org>

Noticed another minor thing. I'm working on the set rate and
parent at the same time op on top of this patch series. Hopefully
have something soon.

On 05/15, James Hogan wrote:
> @@ -1181,6 +1242,11 @@ static void clk_change_rate(struct clk *clk)
>  
>  	old_rate = clk->rate;
>  
> +	/* set parent */
> +	if (clk->new_parent && clk->new_parent != clk->parent)
> +		__clk_set_parent_no_recalc(clk, clk->new_parent,
> +					   clk->new_parent_index);
> +

This check here for new_parent != clk->parent ...

> @@ -1451,6 +1501,27 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
>  	return 0;
>  }
>  
> +static int __clk_set_parent_no_recalc(struct clk *clk, struct clk *parent,
> +				      u8 p_index)
> +{
> +	int ret = 0;
> +
> +	if (clk->parent == parent)
> +		goto out;

causes this to never be true, so we can probably drop it.

> +
> +	/* only re-parent if the clock is not in use */
> +	ret = __clk_set_parent(clk, parent, p_index);
> +	if (ret)
> +		goto out;
> +
> +	/* reparent, but don't propagate rate recalculation downstream */
> +	clk_reparent(clk, parent);
> +	clk_debug_reparent(clk, parent);
> +
> +out:
> +	return ret;
> +}

Also, we never check the return code so it's sort of useless.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From gang.chen at asianux.com  Mon May 20 00:19:31 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 12:19:31 +0800
Subject: [PATCH] arm64: compiling issue for allmodconfig, need "asm/parport.h"
 by "drivers/parport/parport_pc.c"
In-Reply-To: <20130424110511.GK23397@arm.com>
References: <5177551D.8090007@asianux.com> <20130424082237.GA23397@arm.com>
 <5177B1F0.10106@asianux.com>
 <20130424102327.GF21850@mudshark.cambridge.arm.com>
 <5177BAD0.9000500@asianux.com> <20130424110511.GK23397@arm.com>
Message-ID: <5199A453.4080402@asianux.com>


Need add the default file in 'asm/Kbuild' just like arm has done.

The build command is:
  make EXTRA_CFLAGS=-W ARCH=arm64 allmodconfig
  make EXTRA_CFLAGS=-W ARCH=arm64 menuconfig
    set "aarch64-linux-gnu-" as cross compiling prefix.
  make EXTRA_CFLAGS=-W ARCH=arm64

The related error:
  drivers/parport/parport_pc.c:67:25: fatal error: asm/parport.h: No such file or directory


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/include/asm/Kbuild |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index 79a642d..9005e81 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -25,6 +25,7 @@ generic-y += local64.h
 generic-y += mman.h
 generic-y += msgbuf.h
 generic-y += mutex.h
+generic-y += parport.h
 generic-y += pci.h
 generic-y += percpu.h
 generic-y += poll.h
-- 
1.7.7.6


From viresh.kumar at linaro.org  Mon May 20 00:36:49 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 20 May 2013 10:06:49 +0530
Subject: spurious bL cpufreq driver messages
In-Reply-To: <CAL_JsqLEv38DwnL4=ToXtEKNrDbgYv_0qiOc+cXZSjnfKVbeNg@mail.gmail.com>
References: <519686BC.3090101@gmail.com>
 <CAKohpom0cGfWvsCf-jaMyu0cQJi2hVk9_0wskEDH2X7MaeHDLw@mail.gmail.com>
 <CAL_JsqLEv38DwnL4=ToXtEKNrDbgYv_0qiOc+cXZSjnfKVbeNg@mail.gmail.com>
Message-ID: <CAKohpomG5E2FAeZGnX3eBw8fOiX3K8sWEeHgb5NT_FT3y+Cg1w@mail.gmail.com>

On 19 May 2013 01:21, Rob Herring <robherring2 at gmail.com> wrote:
> No, it still registers the bL driver. The problem is not that DT data
> is missing, but it is present on a single cluster system.

I misread your mail.. I got the problem now.. Below should fix your
issue (It is rebased on the patch I pointed to you earlier):

Attached too for testing as gmail copy-paste will break it.

@Rafael: Once Rob gives his Tested-by, please queue it for 3.10-rcs

------------x-----------------x-----------------

From: Viresh Kumar <viresh.kumar at linaro.org>
Date: Mon, 20 May 2013 09:57:17 +0530
Subject: [PATCH] cpufreq: arm_big_little_dt: Instantiate as platform_driver

As multiplatform build is being adopted by more and more ARM platforms, initcall
function should be used very carefully. For example, when both arm_big_little_dt
and cpufreq-cpu0 drivers are compiled in, arm_big_little_dt driver may try to
register even if we had platform device for cpufreq-cpu0 registered.

To eliminate this undesired the effect, the patch changes arm_big_little_dt
driver to have it instantiated as a platform_driver. Then it will only run on
platforms that create the platform_device "arm-bL-cpufreq-dt".

Reported-by: Rob Herring <robherring2 at gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>
---
 drivers/cpufreq/arm_big_little_dt.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/cpufreq/arm_big_little_dt.c
b/drivers/cpufreq/arm_big_little_dt.c
index 27e2f45..fd9e3ea 100644
--- a/drivers/cpufreq/arm_big_little_dt.c
+++ b/drivers/cpufreq/arm_big_little_dt.c
@@ -26,6 +26,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/opp.h>
+#include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 #include "arm_big_little.h"
@@ -95,7 +96,7 @@ static struct cpufreq_arm_bL_ops dt_bL_ops = {
 	.init_opp_table = dt_init_opp_table,
 };

-static int generic_bL_init(void)
+static int generic_bL_probe(struct platform_device *pdev)
 {
 	struct device_node *np;

@@ -106,13 +107,22 @@ static int generic_bL_init(void)
 	of_node_put(np);
 	return bL_cpufreq_register(&dt_bL_ops);
 }
-module_init(generic_bL_init);

-static void generic_bL_exit(void)
+static int generic_bL_remove(struct platform_device *pdev)
 {
-	return bL_cpufreq_unregister(&dt_bL_ops);
+	bL_cpufreq_unregister(&dt_bL_ops);
+	return 0;
 }
-module_exit(generic_bL_exit);
+
+static struct platform_driver generic_bL_platdrv = {
+	.driver = {
+		.name	= "arm-bL-cpufreq-dt",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= generic_bL_probe,
+	.remove		= generic_bL_remove,
+};
+module_platform_driver(generic_bL_platdrv);

 MODULE_AUTHOR("Viresh Kumar <viresh.kumar at linaro.org>");
 MODULE_DESCRIPTION("Generic ARM big LITTLE cpufreq driver via DT");
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From pekon at ti.com  Mon May 20 00:44:31 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Mon, 20 May 2013 04:44:31 +0000
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com> <20130508235404.GX32546@atomide.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>
Message-ID: <20980858CB6D3A4BAE95CA194937D5E73E9C5629@DBDE04.ent.ti.com>

 
> > > >
> > > >  	am33xx_pinmux: pinmux at 44e10800 {
> > > >  		pinctrl-names = "default";
> > > > -		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
> > > > +		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
> > > > +			&nandflash_pins_s0>;
> > >
> > > Why add this to the board level fallback (called pinctrl hogs, I think)?
> > > This can be part of nand node you added below so that the pinctrl will
> > > take effect when nand gets probed instead of all the time.
> >
> > Yes we should have all the pinctrl entries under the related drivers.
> > This makes it easy remux pins during runtime if needed, and also
> > allows unloading pinctrl-single.ko for development.
> >
> Yes, accepted. This has been already fixed in v3 of this patch set.
> If all fine, then please pull this for next merge..
> 
> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046712.html
> 
> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046814.html
> 
> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046710.html
> 
> 
> with regards, pekon

Request you to please accept | provide feedbacks on this patch series.
These are waiting acceptance since Jan-2013, and are necessary for 
DT based configs for board having NAND support.

with regards, pekon


From B35083 at freescale.com  Mon May 20 01:01:47 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Mon, 20 May 2013 05:01:47 +0000
Subject: [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts
 support
In-Reply-To: <20130519152932.GA24301@S2101-09.ap.freescale.net>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-5-git-send-email-b35083@freescale.com>
 <20130519152932.GA24301@S2101-09.ap.freescale.net>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CB26E@039-SN1MPN1-003.039d.mgd.msft.net>

>> +
>> +	sound {
>> +		compatible = "fsl,mvf600-audio-sgtl5000";
>> +		model = "mvf600-sgtl5000";
>> +		sai-controller = <&sai2>;
>> +		audio-codec = <&codec>;
>> +		audio-routing =
>> +			"MIC_IN", "Mic Jack",
>> +			"Mic Jack", "Mic Bias",
>> +			"Headphone Jack", "HP_OUT";
>> +	};
>
>Has this been tested against mainline kernel?  If not, please remove it.
>
>> +	clock-frequency = <100000>;
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_i2c0_1>;
>> +
>> +	codec: sgtl5000 at 0a {
>> +		compatible = "fsl,sgtl5000";
>> +		reg = <0x0a>;
>> +		clocks = <&clks MVF600_CLK_SAI2>;
>
>The sgtl5000 uses SAI2 clock?
[Lu Jingchang-B35083] 
  Yes, the sgtl5000 uses the SAI2 clock on MVF600 Tower board. Thanks!
>
>> +	};
>> +};
>
>Is i2c-imx driver working for mvf600 right now?
>
>
>Do we have a QuadSPI driver on mainline kernel?  Please only add it when
>it's been tested against mainline kernel.
[Lu Jingchang-B35083] 
 Sound, I2C, QuadSPI and SAI added in the initial dts have been test locally on the mainline kernel, and the patches will be sent to maillist later. Thanks!




From viresh.kumar at linaro.org  Mon May 20 01:29:42 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 20 May 2013 10:59:42 +0530
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <2001452.Fn2HjLbNED@vostro.rjw.lan>
References: <cover.1365079581.git.viresh.kumar@linaro.org>
 <CAKohponkFB7ND38jv5oGnQLx8cq0b=uHTCmL3EERe6P54ijYhw@mail.gmail.com>
 <093901ce509f$afe92f40$0fbb8dc0$%kim@samsung.com>
 <2001452.Fn2HjLbNED@vostro.rjw.lan>
Message-ID: <CAKohpon97dbLDF0xU7vhf5V+UVeJv7WdeMuZ1jXLUTey2+gD2A@mail.gmail.com>

On 14 May 2013 18:30, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> On Tuesday, May 14, 2013 09:36:42 PM Kukjin Kim wrote:
>> Viresh Kumar wrote:
>> >
>> > On 13 May 2013 16:21, Rafael J. Wysocki <rjw at sisk.pl> wrote:
>> > > That doesn't matter I suppose.  I can take it, but please rebase it on
>> > top
>> > > of current linux-next.
>> >
>> > I have already done that (attached). But i wasn't sure what Kukjin wants
>> > as
>> > he may report conflicts again and i will ask the same question for 3.12 :)
>> >
>> Since this missed last time, this would be sent to upstream via samsung tree
>> again. It means the conflicts should be handled by myself.
>>
>> Rafael, if you don't mind, let me take this into Samsung tree for v3.11.
>
> Sure, please go ahead.

Kukjin,

I hope you have already applied this for linux-next?


From hvaibhav at ti.com  Mon May 20 01:30:17 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 20 May 2013 05:30:17 +0000
Subject: [PATCH 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2 as
 part of init
In-Reply-To: <alpine.DEB.2.00.1305200248280.2656@utopia.booyaka.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <1367919574-21353-2-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1305200248280.2656@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8E70F@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Monday, May 20, 2013 8:20 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; Cousson, Benoit;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2
> as part of init
> 
> On Tue, 7 May 2013, Vaibhav Hiremath wrote:
> 
> > clkout2 comes out on the pad and is being used by various
> > external on-board peripherals like, Audio codecs and stuff.
> > So enable the clkout2 by default during init sequence itself.
> 
> I don't like this: the clock should be enabled by the drivers for those
> external peripherals, not enabled by default.  

Neither do I. And certainly respective driver should make sure that
he enables all required clocks.

The gap here is, we only support DT only boot and currently clock bindings
Is not coming from DT. Once we get there this needs to change.

Also, note that, I do not expect impact on PM (atleast on AM335x).

> So I think you should
> reconsider the part of the patch that enables it upon init.  But if you
> really want to do this, I'm not inclined to stand in the way; you can
> add
> my ack.
> 

Thanks for your ack, I will send out next version shortly.

Thanks,
Vaibhav


From hvaibhav at ti.com  Mon May 20 01:30:21 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 20 May 2013 05:30:21 +0000
Subject: [PATCH 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad used
 for clock output
In-Reply-To: <alpine.DEB.2.00.1305200250250.2656@utopia.booyaka.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <1367919574-21353-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1305200250250.2656@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8E716@DBDE04.ent.ti.com>



> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Monday, May 20, 2013 8:21 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; Cousson, Benoit;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad
> used for clock output
> 
> Hi
> 
> something that you should fix:
> 
> On Tue, 7 May 2013, Vaibhav Hiremath wrote:
> 
> > xdma_event_intr1.clkout2 pad can be used to source clock
> > from either 32K OSC or any of the PLL (except MPU) outputs.
> > On the existing AM335x based boards (EVM, EVM-SK and Bone),
> > this pad is used to feed the clock to audio codes.
> >
> > So, this patch configures the pinmux to get clkout2 on the pad.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > ---
> >  arch/arm/boot/dts/am335x-bone.dts  |    8 +++++++-
> >  arch/arm/boot/dts/am335x-evm.dts   |    8 +++++++-
> >  arch/arm/boot/dts/am335x-evmsk.dts |    8 +++++++-
> >  3 files changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/am335x-bone.dts
> b/arch/arm/boot/dts/am335x-bone.dts
> > index bfba6fc..f4630a3 100644
> > --- a/arch/arm/boot/dts/am335x-bone.dts
> > +++ b/arch/arm/boot/dts/am335x-bone.dts
> > @@ -26,7 +26,7 @@
> >
> >  	am33xx_pinmux: pinmux at 44e10800 {
> >  		pinctrl-names = "default";
> > -		pinctrl-0 = <>;
> > +		pinctrl-0 = <&clkout2_pin>;
> >
> >  		user_leds_s0: user_leds_s0 {
> >  			pinctrl-single,pins = <
> > @@ -50,6 +50,12 @@
> >  				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN |
> MODE0 */
> >  			>;
> >  		};
> > +
> > +		clkout2_pin: pinumx_clkout2_pin {
> 
> "pinmux" is misspelled here and in several other parts of this file.
> 

Very good catch. Once misspelled and it gets copy-pasted everywhere :)

Will send next version shortly.

Thanks,
Vaibhav


From hvaibhav at ti.com  Mon May 20 01:31:06 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 20 May 2013 05:31:06 +0000
Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output
 on SoC pad
In-Reply-To: <alpine.DEB.2.00.1305200246080.2656@utopia.booyaka.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83EC8C081@DBDE04.ent.ti.com>
 <alpine.DEB.2.00.1305200246080.2656@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8E72D@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Monday, May 20, 2013 8:17 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; Cousson, Benoit;
> linux-arm-kernel at lists.infradead.org
> Subject: RE: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2
> output on SoC pad
> 
> On Fri, 17 May 2013, Hiremath, Vaibhav wrote:
> 
> > Tony, Paul and Benoit,
> >
> > Any update on this series?
> 
> Most of the changes are DT-related, so it should probably go in via
> Beno?t.  I'll ack the clock side, but have a comment on patch 2, to be
> sent shortly.
> 
> 

Thanks Paul for the review, I will next version shortly with your ack.


Thanks,
Vaibhav


From tgih.jun at samsung.com  Mon May 20 01:40:04 2013
From: tgih.jun at samsung.com (Seungwon Jeon)
Date: Mon, 20 May 2013 14:40:04 +0900
Subject: [PATCHv2 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1368731117-4749-6-git-send-email-dinguyen@altera.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
 <1368731117-4749-6-git-send-email-dinguyen@altera.com>
Message-ID: <000a01ce551c$7b174190$7145c4b0$%jun@samsung.com>

On 05/17/13 4:05, Dinh Nguyen wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Seungwon Jeon <tgih.jun at samsung.com>
> CC: Jaehoon Chung <jh80.chung at samsung.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: linux-mmc at vger.kernel.org
> 
> v2:
> - Use syscon and regmap
> - Avoid divide by zero
> - Remove the need to set PWR_EN
> ---
>  drivers/mmc/host/Kconfig          |    8 +++
>  drivers/mmc/host/Makefile         |    1 +
>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>  drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
>  drivers/mmc/host/dw_mmc.h         |    1 +
>  5 files changed, 149 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 9ab8f8d..1be2289 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>  	  for platforms based on Exynos4 and Exynos5 SoC's.
> 
> +config MMC_DW_SOCFPGA
> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
> +	depends on MMC_DW
> +	select MMC_DW_PLTFM
> +	help
> +	  This selects support for Altera SoCFPGA specific extensions to the
> +	  Synopsys DesignWare Memory Card Interface driver.
> +
>  config MMC_DW_PCI
>  	tristate "Synopsys Designware MCI support on PCI bus"
>  	depends on MMC_DW && PCI
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index cd32280..67718c1 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index f013e7e..866edef 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -31,8 +31,6 @@
>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
> 
> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
> -
>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
> 
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> new file mode 100644
> index 0000000..af89685
> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> @@ -0,0 +1,139 @@
> +/*
> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
> + *
> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> + *  Copyright (C) 2013 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Taken from dw_mmc_exynos.c
> + */
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/dw_mmc.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "dw_mmc.h"
> +#include "dw_mmc-pltfm.h"
> +
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
Did you check Jaehoon Chung's comment?
It's trivial, but more common.
((((smplsel) & 0x38) << 3) | (((drvsel) & 0x7) << 0))

> +
> +extern void __iomem *sys_manager_base_addr;
> +
> +/* SOCFPGA implementation specific driver private data */
> +struct dw_mci_socfpga_priv_data {
> +	u8	ciu_div;
> +	u32	hs_timing;
> +	struct regmap   *sysreg;
> +};
> +
> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv;
> +	struct device *dev = host->dev;
> +
> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv) {
> +		dev_err(host->dev, "mem alloc failed for private data\n");
> +		return -ENOMEM;
> +	}
> +
> +	host->priv = priv;
> +	return 0;
> +}
> +
> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	clk_disable(host->ciu_clk);
> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
> +	clk_enable(host->ciu_clk);
You can use clk_prepare_enable/clk_disable_unprepare instead of clk_enable/clk_disable.

> +
> +	host->bus_hz /= (priv->ciu_div + 1);
> +	return 0;
> +}
> +
> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
> +}
> +
> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +	struct device_node *np = host->dev->of_node;
> +	u32 timing[2];
> +	u32 div = 0;
> +	int ret;
> +
> +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
How about placing syscon_regmap_lookup_by_compatible in dw_mci_socfpga_priv_init.
It seems more proper place.

> +	if (IS_ERR(priv->sysreg)) {
> +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> +		return PTR_ERR(priv->sysreg);
> +	}
> +
> +	of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
Error check would be helpful.
ret = of_property_read_u32();

Thanks,
Seungwon Jeon

> +	priv->ciu_div = div;
> +
> +	ret = of_property_read_u32_array(np,
> +			"altr,dw-mshc-sdr-timing", timing, 2);
> +	if (ret)
> +		return ret;
> +
> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> +	return 0;
> +}
> +
> +static const struct dw_mci_drv_data socfpga_drv_data = {
> +	.init			= dw_mci_socfpga_priv_init,
> +	.setup_clock		= dw_mci_socfpga_setup_clock,
> +	.prepare_command	= dw_mci_socfpga_prepare_command,
> +	.parse_dt		= dw_mci_socfpga_parse_dt,
> +};
> +
> +static const struct of_device_id dw_mci_socfpga_match[] = {
> +	{ .compatible = "altr,socfpga-dw-mshc",
> +			.data = &socfpga_drv_data, },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
> +
> +int dw_mci_socfpga_probe(struct platform_device *pdev)
> +{
> +	const struct dw_mci_drv_data *drv_data;
> +	const struct of_device_id *match;
> +
> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
> +	drv_data = match->data;
> +	return dw_mci_pltfm_register(pdev, drv_data);
> +}
> +
> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
> +	.probe		= dw_mci_socfpga_probe,
> +	.remove		= __exit_p(dw_mci_pltfm_remove),
> +	.driver		= {
> +		.name		= "dwmmc_socfpga",
> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
> +		.pm		= &dw_mci_pltfm_pmops,
> +	},
> +};
> +
> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
> +
> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:dwmmc-socfpga");
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 0b74189..3700cb2 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -111,6 +111,7 @@
>  #define SDMMC_INT_ERROR			0xbfc2
>  /* Command register defines */
>  #define SDMMC_CMD_START			BIT(31)
> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>  #define SDMMC_CMD_UPD_CLK		BIT(21)
> --
> 1.7.9.5
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From rnayak at ti.com  Mon May 20 01:42:22 2013
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 20 May 2013 11:12:22 +0530
Subject: [PATCH v3 0/6] ARM: OMAP2+: hwmod and SERIAL: Remove sysc handling
 from driver
In-Reply-To: <87txm1smrz.fsf@linaro.org>
References: <1368629322-3170-1-git-send-email-rnayak@ti.com>
 <alpine.DEB.2.00.1305161831390.21357@utopia.booyaka.com>
 <87txm1smrz.fsf@linaro.org>
Message-ID: <5199B7BE.8060808@ti.com>

On Friday 17 May 2013 07:59 PM, Kevin Hilman wrote:
> Hi Paul,
> 
> Paul Walmsley <paul at pwsan.com> writes:
> 
>> On Wed, 15 May 2013, Rajendra Nayak wrote:
>>
>>> OMAP UART IP needs manual idle modes based on functional state of the
>>> IP. Currently this is handled by the driver with function pointers
>>> implemented in platform code.
>>>
>>> This however breaks in case of device tree because of missing
>>> idle handling. 
>>>
>>> The series tries to address the issue and tries to remove complete
>>> sysc handling from serial driver.
>>
>> These look good to me.  Will queue them for v3.10-rc once they pass local 
>> testing here.
> 
> I reviewed and tested v2 of this (Rajendra forgot to add the tags in

Oops, sorry about that Kevin, and thanks for the repeated reviews and
tests on this series.

regards,
Rajendra

> v3) and also just sanity tested v3 of this on 4430/panda DT boot to
> verify the console issue is resolved.  Feel free to add:
> 
> Reviewed-by: Kevin Hilman <khilman at linaro.org>
> Tested-by: Kevin Hilman <khilman at linaro.org>  # OMAP4/Panda
> 
> Kevin
> 



From gang.chen at asianux.com  Mon May 20 01:42:46 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 13:42:46 +0800
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for related
 driver using.
Message-ID: <5199B7D6.40907@asianux.com>


Add the extern variable 'screen_info' according to arm32 has done.

The related error:
  drivers/video/console/vgacon.c:1305: undefined reference to `screen_info'


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/kernel/setup.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index add6ea6..1055992 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -374,3 +374,14 @@ const struct seq_operations cpuinfo_op = {
 	.stop	= c_stop,
 	.show	= c_show
 };
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
+struct screen_info screen_info = {
+	.orig_video_lines	= 30,
+	.orig_video_cols	= 80,
+	.orig_video_mode	= 0,
+	.orig_video_ega_bx	= 0,
+	.orig_video_isVGA	= 1,
+	.orig_video_points	= 8
+};
+#endif
-- 
1.7.7.6


From hvaibhav at ti.com  Mon May 20 01:50:29 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 20 May 2013 05:50:29 +0000
Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to
 GFX hwmod
In-Reply-To: <20130517172451.GY5600@atomide.com>
References: <1367693284-7870-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83EC8C092@DBDE04.ent.ti.com>
 <20130517172451.GY5600@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8E77E@DBDE04.ent.ti.com>

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Friday, May 17, 2013 10:55 PM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Paul Walmsley
> Subject: Re: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info
> to GFX hwmod
> 
> * Hiremath, Vaibhav <hvaibhav at ti.com> [130517 04:13]:
> >
> > > -----Original Message-----
> > > From: Hiremath, Vaibhav
> > > Sent: Sunday, May 05, 2013 12:18 AM
> > > To: linux-omap at vger.kernel.org
> > > Cc: tony at atomide.com; linux-arm-kernel at lists.infradead.org;
> Hiremath,
> > > Vaibhav; Paul Walmsley
> > > Subject: [PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info
> to
> > > GFX hwmod
> > >
> > > GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
> > > so update the GFX hwmod data with .rstst_off and .st_shift
> > > information.
> > >
> > > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > > Cc: Paul Walmsley <paul at pwsan.com>
> > > ---
> > >  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    3 ++-
> > >  1 files changed, 2 insertions(+), 1 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > > b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > > index d1cf3ab..38c7b04 100644
> > > --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > > +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> > > @@ -329,7 +329,7 @@ static struct omap_hwmod_class
> > > am33xx_gfx_hwmod_class = {
> > >  };
> > >
> > >  static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
> > > -	{ .name = "gfx", .rst_shift = 0 },
> > > +	{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
> > >  };
> > >
> > >  static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
> > > @@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
> > >  		.omap4	= {
> > >  			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
> > >  			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
> > > +			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
> > >  			.modulemode	= MODULEMODE_SWCTRL,
> > >  		},
> > >  	},
> > > --
> >
> > Tony and Paul,
> >
> > Any Update on this one as well?
> 
> Is this needed for v3.10 as a fix? If so, it should describe the
> regression or error.
> 

Certainly this is fix, but no impact on kernel boot.
I will describe it more in the description and send next version shortly.

Thanks,
Vaibhav



From yamagata at plathome.co.jp  Mon May 20 01:50:44 2013
From: yamagata at plathome.co.jp (yamagata at plathome.co.jp)
Date: Mon, 20 May 2013 14:50:44 +0900 (JST)
Subject: [PATCH] arm: mvebu: enable the third USB interface on
 OpenBlocks AX3
In-Reply-To: <20130519201939.GL11137@titan.lakedaemon.net>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
 <20130519201939.GL11137@titan.lakedaemon.net>
Message-ID: <20130520.145044.280780615.yamagata@plathome.co.jp>

Dear Mr. Jason Cooper

> I don't like to assume for people, so if you could please provided a
> "Tested-by:" I'd appreciate it.

Tested-by: Atsushi Yamagata <yamagata at plathome.co.jp>

Best regards

Atsushi Yamagata
--- Atsushi Yamagata


From hvaibhav at ti.com  Mon May 20 01:51:09 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 20 May 2013 05:51:09 +0000
Subject: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
 clkdiv32k_ick clock
In-Reply-To: <20130517171016.GV5600@atomide.com>
References: <1364378666-23641-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1303271744510.17356@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EC8BFA7@DBDE04.ent.ti.com>
 <20130517171016.GV5600@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8E78A@DBDE04.ent.ti.com>


> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Friday, May 17, 2013 10:40 PM
> To: Hiremath, Vaibhav
> Cc: Paul Walmsley; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Nayak, Rajendra
> Subject: Re: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
> clkdiv32k_ick clock
> 
> * Hiremath, Vaibhav <hvaibhav at ti.com> [130517 03:36]:
> >
> > > -----Original Message-----
> > > From: Paul Walmsley [mailto:paul at pwsan.com]
> > > Sent: Wednesday, March 27, 2013 11:15 PM
> > > To: Tony Lindgren; Hiremath, Vaibhav
> > > Cc: linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org;
> > > Nayak, Rajendra
> > > Subject: Re: [PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to
> > > clkdiv32k_ick clock
> > >
> > > On Wed, 27 Mar 2013, Vaibhav Hiremath wrote:
> > >
> > > > It is required to enable respective clock-domain before
> > > > enabling any clock/module inside that clock-domain.
> > > >
> > > > During common-clock migration, .clkdm_name field got missed
> > > > for "clkdiv32k_ick" clock, which leaves "clk_24mhz_clkdm"
> > > > unused; so it will be disabled even if childs of this clock-
> domain
> > > > is enabled, which keeps child modules in idle mode.
> > > >
> > > > This fixes the kernel crash observed on AM335xEVM-SK platform,
> > > > where clkdiv32_ick clock is being used as a gpio debounce clock
> > > > and since clkdiv32k_ick is in idle mode it leads to below crash -
> > > >
> > > > Crash Log:
> > > > ==========
> > > > [    2.598347] Unhandled fault: external abort on non-linefetch
> > > (0x1028) at
> > > > 0xfa1ac150
> > > > [    2.606434] Internal error: : 1028 [#1] SMP ARM
> > > > [    2.611207] Modules linked in:
> > > > [    2.614449] CPU: 0    Not tainted  (3.8.4-01382-g1f449cd-dirty
> #4)
> > > > [    2.620973] PC is at _set_gpio_debounce+0x60/0x104
> > > > [    2.626025] LR is at clk_enable+0x30/0x3c
> > > >
> > > > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > > > Cc: Tony Lindgren <tony at atomide.com>
> > > > Cc: Paul Walmsley <paul at pwsan.com>
> > > > Cc: Rajendra Nayak <rnayak at ti.com>
> > >
> > > Acked-by: Paul Walmsley <paul at pwsan.com>
> > >
> > > Tony, if it isn't too late, could this one be added to your 3.9-rc
> > > fixes
> > > series?
> > >
> > >
> >
> > Looks like we missed this so far.
> >
> > Tony, can you merge this patch for v3.10-rc ?
> 
> Oops, sorry somehow this did not make it. I'll apply it to omap-for-
> v3.10/fixes
> with cc: stable flag.
> 

Thanks Tony, I saw it in your yesterday's pull request.

Thanks,
Vaibhav


From shawn.guo at linaro.org  Mon May 20 01:53:52 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 13:53:52 +0800
Subject: [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts
 support
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CB26E@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <1368684648-20826-5-git-send-email-b35083@freescale.com>
 <20130519152932.GA24301@S2101-09.ap.freescale.net>
 <B56CDBE15CE27145A4B77D2D24263E851CB26E@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <20130520055350.GF25113@S2101-09.ap.freescale.net>

On Mon, May 20, 2013 at 05:01:47AM +0000, Lu Jingchang-B35083 wrote:
> [Lu Jingchang-B35083] 
>  Sound, I2C, QuadSPI and SAI added in the initial dts have been test locally on the mainline kernel, and the patches will be sent to maillist later. Thanks!
> 

Please add them after driver patches get accepted by subsystem
maintainers.  If the DT bindings can not be accepted as it is, we will
end up changing the dts files back and forth.

Shawn



From shawn.guo at linaro.org  Mon May 20 02:06:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 14:06:51 +0800
Subject: [PATCH 1/2] ARM: imx: disable pll8_mlb in mx6q_clks
In-Reply-To: <1368780045-6481-2-git-send-email-jiada_wang@mentor.com>
References: <1368780045-6481-1-git-send-email-jiada_wang@mentor.com>
 <1368780045-6481-2-git-send-email-jiada_wang@mentor.com>
Message-ID: <20130520060649.GG25113@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 05:40:44PM +0900, Jiada Wang wrote:
> The MLB PLL clock's operation doesn't fit for clock framework and
> it should be handled internally in MLB driver.
> Remove initialization of pll8_mlb clock device but leave its
> declaration in mx6q_clks to avoid affecting imx6q clock numbering.
> 
> Signed-off-by: Jiada Wang <jiada_wang at mentor.com>
> CC: Shawn Guo <shawn.guo at linaro.org>
> CC: Dirk Behme <dirk.behme at de.bosch.com>

Applied both, thanks.



From shawn.guo at linaro.org  Mon May 20 02:11:41 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 14:11:41 +0800
Subject: [PATCH] ARM: imx6q: clk: add the eim_slow clock
In-Reply-To: <1368782123-15523-1-git-send-email-b32955@freescale.com>
References: <1368782123-15523-1-git-send-email-b32955@freescale.com>
Message-ID: <20130520061140.GH25113@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 05:15:23PM +0800, Huang Shijie wrote:
> Add the eim_slow clock, since the weim needs it.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Applied, thanks.



From shawn.guo at linaro.org  Mon May 20 02:13:41 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 14:13:41 +0800
Subject: [PATCH 1/2] ARM i.MX53: Add SATA clock
In-Reply-To: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>
References: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <20130520061339.GI25113@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 03:49:02PM +0200, Philipp Zabel wrote:
> From: Sascha Hauer <s.hauer at pengutronix.de>
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>

Both applied, thanks.



From shawn.guo at linaro.org  Mon May 20 02:18:56 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 May 2013 14:18:56 +0800
Subject: [PATCH] ARM: i.MX6: clk: add different DualLite MLB clock config
In-Reply-To: <1368861928-16141-1-git-send-email-dirk.behme@gmail.com>
References: <1368861928-16141-1-git-send-email-dirk.behme@gmail.com>
Message-ID: <20130520061854.GJ25113@S2101-09.ap.freescale.net>

On Sat, May 18, 2013 at 09:25:28AM +0200, Dirk Behme wrote:
> The CCM_CBCMR register (address 0x02C4018) has different meaning
> between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.
> 
> Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
> i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock
> configuration.
> 
> Signed-off-by: Dirk Behme <dirk.behme at gmail.com>

Applied, thanks.



From sanjay.rawat at linaro.org  Mon May 20 02:33:22 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:22 +0530
Subject: [RFC PATCH 0/6] ARM: cpuhotplug: move common functions to core
Message-ID: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>

Various SoCs with arm processors define their own platform hotplug related
functions. These functions can be defined as part of the core cpu hotplug
functions, this will avoid the duplication. This patchset is intended to
address this issue.

This patchset covers arm-Cortex-A9 of exynos, imx, realview, spear and
vexpress SoCs. Not having h/w, the patch is not tested.

Sanjay Singh Rawat (6):
  ARM: cpuhotplug: move common hotplug related functions to core
  ARM: imx: use the core cpu hotplug functions
  ARM: RealView: use the core cpu hotplug functions
  ARM: spear: use the core cpu hotplug functions
  ARM: vexpress: use the core cpu hotplug functions
  ARM: EXYNOS: use the core cpu hotplug functions

 arch/arm/include/asm/hotplug.h   |   24 ++++++++++++++
 arch/arm/kernel/Makefile         |    1 +
 arch/arm/kernel/cpuhotplug.c     |   64 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/hotplug.c   |   40 ++----------------------
 arch/arm/mach-imx/hotplug.c      |   22 +------------
 arch/arm/mach-realview/hotplug.c |   37 +---------------------
 arch/arm/mach-spear/hotplug.c    |   37 +---------------------
 arch/arm/mach-vexpress/hotplug.c |   38 +---------------------
 8 files changed, 95 insertions(+), 168 deletions(-)
 create mode 100644 arch/arm/include/asm/hotplug.h
 create mode 100644 arch/arm/kernel/cpuhotplug.c

-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 20 02:33:23 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:23 +0530
Subject: [RFC PATCH 1/6] ARM: cpuhotplug: move common hotplug related
 functions to core
In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369031608-27347-2-git-send-email-sanjay.rawat@linaro.org>

Add function which prepare arm processors to enter the low power for hotplug
functionality and handle the return path.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/include/asm/hotplug.h |   24 +++++++++++++++
 arch/arm/kernel/Makefile       |    1 +
 arch/arm/kernel/cpuhotplug.c   |   64 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+)
 create mode 100644 arch/arm/include/asm/hotplug.h
 create mode 100644 arch/arm/kernel/cpuhotplug.c

diff --git a/arch/arm/include/asm/hotplug.h b/arch/arm/include/asm/hotplug.h
new file mode 100644
index 0000000..ae80f0e
--- /dev/null
+++ b/arch/arm/include/asm/hotplug.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/include/asm/hotplug.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+extern inline void cpu_enter_lowpower(void);
+extern inline void cpu_leave_lowpower(void);
+
+#else
+static inline void cpu_enter_lowpower(void)
+{
+	return -ENODEV;
+}
+static inline void cpu_leave_lowpower(void)
+{
+	return -ENODEV;
+}
+
+#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..9bd370b 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_ISA_DMA)		+= dma-isa.o
 obj-$(CONFIG_PCI)		+= bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
 obj-$(CONFIG_SMP)		+= smp.o smp_tlb.o
+obj-$(CONFIG_HOTPLUG_CPU)	+= cpuhotplug.o
 obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)	+= arch_timer.o
diff --git a/arch/arm/kernel/cpuhotplug.c b/arch/arm/kernel/cpuhotplug.c
new file mode 100644
index 0000000..8651b96
--- /dev/null
+++ b/arch/arm/kernel/cpuhotplug.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <asm/cp15.h>
+
+/*
+ * For Cortex-A9 processor
+ */
+static inline void ca9_enter_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"	mcr	p15, 0, %1, c7, c5, 0\n"
+	"	mcr	p15, 0, %1, c7, c10, 4\n"
+	/*
+	 * Turn off coherency
+	 */
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, %3\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %2\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+	  : "cc");
+}
+
+inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"mrc	p15, 0, %0, c1, c0, 0\n"
+	"	orr	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, %2\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C), "Ir" (0x40)
+	  : "cc");
+}
+
+void cpu_enter_lowpower(void)
+{
+	int id = 0;
+
+	/* check the cpuid */
+	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(id) : : "cc");
+
+	if ((id & 0xffffffff) == 0x411fc090)
+		ca9_enter_lowpower();
+	else
+		pr_warn(KERN_WARNING "Unknown CPU type\n");
+}
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 20 02:33:25 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:25 +0530
Subject: [RFC PATCH 3/6] ARM: RealView: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369031608-27347-4-git-send-email-sanjay.rawat@linaro.org>

Generic arm cpu hotplug related functions are moved to core hotplug code,
remove the functions from the platform code.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-realview/hotplug.c |   37 +------------------------------------
 1 file changed, 1 insertion(+), 36 deletions(-)

diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index ac22dd4..a48cc71 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -14,42 +14,7 @@
 
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
-
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C)
-	  : "cc");
-}
+#include <asm/hotplug.h>
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 20 02:33:24 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:24 +0530
Subject: [RFC PATCH 2/6] ARM: imx: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369031608-27347-3-git-send-email-sanjay.rawat@linaro.org>

Generic arm cpu hotplug related functions are moved to core hotplug code,
remove the functions from the platform code.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-imx/hotplug.c |   22 +---------------------
 1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 3daf1ed..280c6f3 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -14,30 +14,10 @@
 #include <linux/jiffies.h>
 #include <asm/cp15.h>
 #include <asm/proc-fns.h>
+#include <asm/hotplug.h>
 
 #include "common.h"
 
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-		"mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, %3\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 20 02:33:27 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:27 +0530
Subject: [RFC PATCH 5/6] ARM: vexpress: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369031608-27347-6-git-send-email-sanjay.rawat@linaro.org>

Generic arm cpu hotplug related functions are moved to core hotplug code,
remove the functions from the platform code.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-vexpress/hotplug.c |   38 +-------------------------------------
 1 file changed, 1 insertion(+), 37 deletions(-)

diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index f0ce6b8..cca1361 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -14,43 +14,7 @@
 
 #include <asm/smp_plat.h>
 #include <asm/cp15.h>
-
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-		"mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, %3\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-		"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
+#include <asm/hotplug.h>
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 20 02:33:26 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:26 +0530
Subject: [RFC PATCH 4/6] ARM: spear: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369031608-27347-5-git-send-email-sanjay.rawat@linaro.org>

Generic arm cpu hotplug related functions are moved to core hotplug code,
remove the functions from the platform code.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-spear/hotplug.c |   37 +------------------------------------
 1 file changed, 1 insertion(+), 36 deletions(-)

diff --git a/arch/arm/mach-spear/hotplug.c b/arch/arm/mach-spear/hotplug.c
index d97749c..988a9a6 100644
--- a/arch/arm/mach-spear/hotplug.c
+++ b/arch/arm/mach-spear/hotplug.c
@@ -15,42 +15,7 @@
 #include <linux/smp.h>
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
-
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	dsb\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	: "=&r" (v)
-	: "r" (0), "Ir" (CR_C)
-	: "cc", "memory");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile("mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	: "=&r" (v)
-	: "Ir" (CR_C)
-	: "cc");
-}
+#include <asm/hotplug.h>
 
 static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
 {
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 20 02:33:28 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 20 May 2013 12:03:28 +0530
Subject: [RFC PATCH 6/6] ARM: EXYNOS: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369031608-27347-7-git-send-email-sanjay.rawat@linaro.org>

Generic arm cpu hotplug related functions are moved to core hotplug code,
Exynos-4 is having Cortex-A9, remove the functions from the platform code.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-exynos/hotplug.c |   40 ++--------------------------------------
 1 file changed, 2 insertions(+), 38 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index af90cfa..3489760 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -21,30 +21,10 @@
 
 #include <mach/regs-pmu.h>
 #include <plat/cpu.h>
+#include <asm/hotplug.h>
 
 #include "common.h"
 
-static inline void cpu_enter_lowpower_a9(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, %3\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
 static inline void cpu_enter_lowpower_a15(void)
 {
 	unsigned int v;
@@ -74,22 +54,6 @@ static inline void cpu_enter_lowpower_a15(void)
 	dsb();
 }
 
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
 	for (;;) {
@@ -144,7 +108,7 @@ void __ref exynos_cpu_die(unsigned int cpu)
 	if ((primary_part & 0xfff0) == 0xc0f0)
 		cpu_enter_lowpower_a15();
 	else
-		cpu_enter_lowpower_a9();
+		cpu_enter_lowpower();
 
 	platform_do_lowpower(cpu, &spurious);
 
-- 
1.7.9.5



From gang.chen at asianux.com  Mon May 20 02:48:05 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 14:48:05 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL_GPL(read_current_timer)'
Message-ID: <5199C725.8050102@asianux.com>


Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with allmodconfig.

The related error:
  ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
  ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
  ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
  ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/kernel/time.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index a551f88..7fcba80 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
 	*timer_value = arch_timer_read_counter();
 	return 0;
 }
+EXPORT_SYMBOL_GPL(read_current_timer);
 
 void __init time_init(void)
 {
-- 
1.7.7.6


From girishks2000 at gmail.com  Mon May 20 02:51:31 2013
From: girishks2000 at gmail.com (Girish K S)
Date: Mon, 20 May 2013 12:21:31 +0530
Subject: [PATCH v1 0/3] Polling support for s3c64xx spi controller
Message-ID: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>

This patch series adds support for the polling mode only. Also 2nd patch
in the series adds support for dedicated cs pin. After Thomas's patch for
using default gpio is merged(commit id: 00ab539), one of the patch in this
series is dropped and new series is generated.

Girish K S (3):
  spi: s3c64xx: added support for polling mode
  spi: s3c64xx: Added provision for dedicated cs pin
  spi: s3c64xx: Added support for exynos5440 spi

 drivers/spi/spi-s3c64xx.c |  197 ++++++++++++++++++++++++++++++++-------------
 1 files changed, 140 insertions(+), 57 deletions(-)

-- 
1.7.5.4



From girishks2000 at gmail.com  Mon May 20 02:51:34 2013
From: girishks2000 at gmail.com (Girish K S)
Date: Mon, 20 May 2013 12:21:34 +0530
Subject: [PATCH v1 3/3] spi: s3c64xx: Added support for exynos5440 spi
In-Reply-To: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
References: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
Message-ID: <1369032694-13183-4-git-send-email-ks.giri@samsung.com>

From: Girish K S <girishks2000 at gmail.com>

This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.

Signed-off-by: Girish K S <ks.giri at samsung.com>
---
 drivers/spi/spi-s3c64xx.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index eaf9e1c..bd43888 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1608,6 +1608,15 @@ static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
 	.clk_from_cmu	= true,
 };
 
+static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
+	.fifo_lvl_mask	= { 0x1ff },
+	.rx_lvl_offset	= 15,
+	.tx_st_done	= 25,
+	.high_speed	= true,
+	.clk_from_cmu	= true,
+	.quirks		= S3C64XX_SPI_QUIRK_POLL,
+};
+
 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
 	{
 		.name		= "s3c2443-spi",
@@ -1636,6 +1645,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
 	{ .compatible = "samsung,exynos4210-spi",
 			.data = (void *)&exynos4_spi_port_config,
 	},
+	{ .compatible = "samsung,exynos5440-spi",
+			.data = (void *)&exynos5440_spi_port_config,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
-- 
1.7.5.4



From girishks2000 at gmail.com  Mon May 20 02:51:32 2013
From: girishks2000 at gmail.com (Girish K S)
Date: Mon, 20 May 2013 12:21:32 +0530
Subject: [PATCH v1 1/3] spi: s3c64xx: added support for polling mode
In-Reply-To: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
References: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
Message-ID: <1369032694-13183-2-git-send-email-ks.giri@samsung.com>

From: Girish K S <girishks2000 at gmail.com>

The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.

Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling mode
and gives flexibity for the user to select poll/dma mode.

Signed-off-by: Girish K S <ks.giri at samsung.com>
---
changes in v1:
		Addressed the performance issue reported by Mark Brown
caused due to this patch. The wait_for_timeout function is modified to
address this issue in dma mode.

 drivers/spi/spi-s3c64xx.c |  153 ++++++++++++++++++++++++++++++--------------
 1 files changed, 104 insertions(+), 49 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 5000586..0a80692 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -39,6 +39,7 @@
 #endif
 
 #define MAX_SPI_PORTS		3
+#define S3C64XX_SPI_QUIRK_POLL		(1 << 0)
 
 /* Registers and bit-fields */
 
@@ -130,6 +131,7 @@
 #define S3C64XX_SPI_TRAILCNT		S3C64XX_SPI_MAX_TRAILCNT
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
+#define is_polling(x)	(x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 
 #define RXBUSY    (1<<2)
 #define TXBUSY    (1<<3)
@@ -158,6 +160,7 @@ struct s3c64xx_spi_port_config {
 	int	fifo_lvl_mask[MAX_SPI_PORTS];
 	int	rx_lvl_offset;
 	int	tx_st_done;
+	int	quirks;
 	bool	high_speed;
 	bool	clk_from_cmu;
 };
@@ -344,8 +347,12 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 {
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 
-	/* Acquire DMA channels */
-	while (!acquire_dma(sdd))
+	/*
+	 * If DMA resource was not available during
+	 * probe, no need to continue with dma requests
+	 * else Acquire DMA channels
+	 */
+	while (!is_polling(sdd) && !acquire_dma(sdd))
 		usleep_range(10000, 11000);
 
 	pm_runtime_get_sync(&sdd->pdev->dev);
@@ -358,9 +365,12 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 
 	/* Free DMA channels */
-	sdd->ops->release((enum dma_ch)sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
-	sdd->ops->release((enum dma_ch)sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
-
+	if (!is_polling(sdd)) {
+		sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
+					&s3c64xx_spi_dma_client);
+		sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
+					&s3c64xx_spi_dma_client);
+	}
 	pm_runtime_put(&sdd->pdev->dev);
 
 	return 0;
@@ -464,8 +474,10 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 
 	/* Free DMA channels */
-	dma_release_channel(sdd->rx_dma.ch);
-	dma_release_channel(sdd->tx_dma.ch);
+	if (!is_polling(sdd)) {
+		dma_release_channel(sdd->rx_dma.ch);
+		dma_release_channel(sdd->tx_dma.ch);
+	}
 
 	pm_runtime_put(&sdd->pdev->dev);
 	return 0;
@@ -566,6 +578,30 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 
 	cs = spi->controller_data;
 	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
+
+	/* Start the signals */
+	writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
+}
+
+static u32 wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
+					int timeout_ms)
+{
+	void __iomem *regs = sdd->regs;
+	unsigned long val = 1;
+	u32 status;
+
+	/* max fifo depth available */
+	u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
+
+	if (timeout_ms)
+		val = msecs_to_loops(timeout_ms);
+
+	do {
+		status = readl(regs + S3C64XX_SPI_STATUS);
+	} while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
+
+	/* return the actual received data length */
+	return RX_FIFO_LVL(status, sdd);
 }
 
 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
@@ -590,20 +626,19 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 		} while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 	}
 
-	if (!val)
-		return -EIO;
-
 	if (dma_mode) {
 		u32 status;
 
 		/*
+		 * If the previous xfer was completed within timeout, then
+		 * proceed further else return -EIO.
 		 * DmaTx returns after simply writing data in the FIFO,
 		 * w/o waiting for real transmission on the bus to finish.
 		 * DmaRx returns only after Dma read data from FIFO which
 		 * needs bus transmission to finish, so we don't worry if
 		 * Xfer involved Rx(with or without Tx).
 		 */
-		if (xfer->rx_buf == NULL) {
+		if (val && !xfer->rx_buf) {
 			val = msecs_to_loops(10);
 			status = readl(regs + S3C64XX_SPI_STATUS);
 			while ((TX_FIFO_LVL(status, sdd)
@@ -613,30 +648,53 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 				status = readl(regs + S3C64XX_SPI_STATUS);
 			}
 
-			if (!val)
-				return -EIO;
 		}
+
+		/* If timed out while checking rx/tx status return error */
+		if (!val)
+			return -EIO;
 	} else {
+		int loops;
+		u32 cpy_len;
+		u8 *buf;
+
 		/* If it was only Tx */
-		if (xfer->rx_buf == NULL) {
+		if (!xfer->rx_buf) {
 			sdd->state &= ~TXBUSY;
 			return 0;
 		}
 
-		switch (sdd->cur_bpw) {
-		case 32:
-			ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
-				xfer->rx_buf, xfer->len / 4);
-			break;
-		case 16:
-			ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
-				xfer->rx_buf, xfer->len / 2);
-			break;
-		default:
-			ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
-				xfer->rx_buf, xfer->len);
-			break;
-		}
+		/*
+		 * If the receive length is bigger than the controller fifo
+		 * size, calculate the loops and read the fifo as many times.
+		 * loops = length / max fifo size (calculated by using the
+		 * fifo mask).
+		 * For any size less than the fifo size the below code is
+		 * executed atleast once.
+		 */
+		loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
+		buf = xfer->rx_buf;
+		do {
+			/* wait for data to be received in the fifo */
+			cpy_len = wait_for_timeout(sdd, (loops ? ms : 0));
+
+			switch (sdd->cur_bpw) {
+			case 32:
+				ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
+					buf, cpy_len / 4);
+				break;
+			case 16:
+				ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
+					buf, cpy_len / 2);
+				break;
+			default:
+				ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
+					buf, cpy_len);
+				break;
+			}
+
+			buf = buf + cpy_len;
+		} while (loops--);
 		sdd->state &= ~RXBUSY;
 	}
 
@@ -652,6 +710,9 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 		sdd->tgl_spi = NULL;
 
 	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
+
+	/* Quiese the signals */
+	writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 }
 
 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
@@ -733,7 +794,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 	struct device *dev = &sdd->pdev->dev;
 	struct spi_transfer *xfer;
 
-	if (msg->is_dma_mapped)
+	if (is_polling(sdd) || msg->is_dma_mapped)
 		return 0;
 
 	/* First mark all xfer unmapped */
@@ -782,7 +843,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 	struct device *dev = &sdd->pdev->dev;
 	struct spi_transfer *xfer;
 
-	if (msg->is_dma_mapped)
+	if (is_polling(sdd) || msg->is_dma_mapped)
 		return;
 
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
@@ -861,8 +922,9 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 
 		/* Polling method for xfers not bigger than FIFO capacity */
 		use_dma = 0;
-		if (sdd->rx_dma.ch && sdd->tx_dma.ch &&
-		    (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))
+		if (!is_polling(sdd) &&
+			(sdd->rx_dma.ch && sdd->tx_dma.ch &&
+			(xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 			use_dma = 1;
 
 		spin_lock_irqsave(&sdd->lock, flags);
@@ -876,17 +938,10 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 		/* Slave Select */
 		enable_cs(sdd, spi);
 
-		/* Start the signals */
-		writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
-
 		spin_unlock_irqrestore(&sdd->lock, flags);
 
 		status = wait_for_xfer(sdd, xfer, use_dma);
 
-		/* Quiese the signals */
-		writel(S3C64XX_SPI_SLAVE_SIG_INACT,
-		       sdd->regs + S3C64XX_SPI_SLAVE_SEL);
-
 		if (status) {
 			dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 				xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
@@ -1287,19 +1342,19 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
 	if (!sdd->pdev->dev.of_node) {
 		res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
 		if (!res) {
-			dev_err(&pdev->dev, "Unable to get SPI tx dma "
-					"resource\n");
-			return -ENXIO;
-		}
-		sdd->tx_dma.dmach = res->start;
+			dev_warn(&pdev->dev, "Unable to get SPI tx dma "
+					"resource. Switching to poll mode\n");
+			sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
+		} else
+			sdd->tx_dma.dmach = res->start;
 
 		res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
 		if (!res) {
-			dev_err(&pdev->dev, "Unable to get SPI rx dma "
-					"resource\n");
-			return -ENXIO;
-		}
-		sdd->rx_dma.dmach = res->start;
+			dev_warn(&pdev->dev, "Unable to get SPI rx dma "
+					"resource. Switching to poll mode\n");
+			sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
+		} else
+			sdd->rx_dma.dmach = res->start;
 	}
 
 	sdd->tx_dma.direction = DMA_MEM_TO_DEV;
-- 
1.7.5.4



From girishks2000 at gmail.com  Mon May 20 02:51:33 2013
From: girishks2000 at gmail.com (Girish K S)
Date: Mon, 20 May 2013 12:21:33 +0530
Subject: [PATCH v1 2/3] spi: s3c64xx: Added provision for dedicated cs pin
In-Reply-To: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
References: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
Message-ID: <1369032694-13183-3-git-send-email-ks.giri@samsung.com>

From: Girish K S <girishks2000 at gmail.com>

The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted/deasserted using gpio pin.

This patch adds support for controllers with dedicated /cs pin.
if "cs-gpio" property doesnt exist in a spi dts node, the controller
would treat the /cs pin as dedicated.

Signed-off-by: Girish K S <ks.giri at samsung.com>
---
changes in v1:
		Added the missing data structure that caused the
compilation error

 drivers/spi/spi-s3c64xx.c |   34 ++++++++++++++++++++++++++--------
 1 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 0a80692..eaf9e1c 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -208,6 +208,7 @@ struct s3c64xx_spi_driver_data {
 	struct s3c64xx_spi_port_config	*port_conf;
 	unsigned int			port_id;
 	unsigned long			gpios[4];
+	bool				cs_gpio;
 };
 
 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
@@ -570,14 +571,16 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 		if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 			/* Deselect the last toggled device */
 			cs = sdd->tgl_spi->controller_data;
-			gpio_set_value(cs->line,
-				spi->mode & SPI_CS_HIGH ? 0 : 1);
+			if (sdd->cs_gpio)
+				gpio_set_value(cs->line,
+					spi->mode & SPI_CS_HIGH ? 0 : 1);
 		}
 		sdd->tgl_spi = NULL;
 	}
 
 	cs = spi->controller_data;
-	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
+	if (sdd->cs_gpio)
+		gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 
 	/* Start the signals */
 	writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
@@ -709,7 +712,8 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 	if (sdd->tgl_spi == spi)
 		sdd->tgl_spi = NULL;
 
-	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
+	if (sdd->cs_gpio)
+		gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 
 	/* Quiese the signals */
 	writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
@@ -997,8 +1001,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 {
 	struct s3c64xx_spi_csinfo *cs;
 	struct device_node *slave_np, *data_np = NULL;
+	struct s3c64xx_spi_driver_data *sdd;
 	u32 fb_delay = 0;
 
+	sdd = spi_master_get_devdata(spi->master);
 	slave_np = spi->dev.of_node;
 	if (!slave_np) {
 		dev_err(&spi->dev, "device node not found\n");
@@ -1018,7 +1024,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 		return ERR_PTR(-ENOMEM);
 	}
 
-	cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
+	/* The CS line is asserted/deasserted by the gpio pin */
+	if (sdd->cs_gpio)
+		cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
+
 	if (!gpio_is_valid(cs->line)) {
 		dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
 		kfree(cs);
@@ -1058,7 +1067,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
 		return -ENODEV;
 	}
 
-	if (!spi_get_ctldata(spi)) {
+	/* Request gpio only if cs line is asserted by gpio pins */
+	if (sdd->cs_gpio) {
 		err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
 				       dev_name(&spi->dev));
 		if (err) {
@@ -1067,9 +1077,11 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
 				cs->line, err);
 			goto err_gpio_req;
 		}
-		spi_set_ctldata(spi, cs);
 	}
 
+	if (!spi_get_ctldata(spi))
+		spi_set_ctldata(spi, cs);
+
 	sci = sdd->cntrlr_info;
 
 	spin_lock_irqsave(&sdd->lock, flags);
@@ -1147,8 +1159,10 @@ err_gpio_req:
 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 {
 	struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
+	struct s3c64xx_spi_driver_data *sdd;
 
-	if (cs) {
+	sdd = spi_master_get_devdata(spi->master);
+	if (cs && sdd->cs_gpio) {
 		gpio_free(cs->line);
 		if (spi->dev.of_node)
 			kfree(cs);
@@ -1325,7 +1339,11 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
 	sdd->cntrlr_info = sci;
 	sdd->pdev = pdev;
 	sdd->sfr_start = mem_res->start;
+	sdd->cs_gpio = false;
 	if (pdev->dev.of_node) {
+		if (of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
+			sdd->cs_gpio = true;
+
 		ret = of_alias_get_id(pdev->dev.of_node, "spi");
 		if (ret < 0) {
 			dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
-- 
1.7.5.4



From viresh.kumar at linaro.org  Mon May 20 02:52:16 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 20 May 2013 12:22:16 +0530
Subject: [RFC PATCH 4/6] ARM: spear: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-5-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
 <1369031608-27347-5-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <CAKohpo==Kfh-MqdiGQBBgi3X+s61o-J880YZffY20A3aTWpQvQ@mail.gmail.com>

Please write spear as SPEAr.

On 20 May 2013 12:03, Sanjay Singh Rawat <sanjay.rawat at linaro.org> wrote:
> Generic arm cpu hotplug related functions are moved to core hotplug code,
> remove the functions from the platform code.
>
> Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
> ---
>  arch/arm/mach-spear/hotplug.c |   37 +------------------------------------
>  1 file changed, 1 insertion(+), 36 deletions(-)
>
> diff --git a/arch/arm/mach-spear/hotplug.c b/arch/arm/mach-spear/hotplug.c
> index d97749c..988a9a6 100644
> --- a/arch/arm/mach-spear/hotplug.c
> +++ b/arch/arm/mach-spear/hotplug.c
> @@ -15,42 +15,7 @@
>  #include <linux/smp.h>
>  #include <asm/cp15.h>
>  #include <asm/smp_plat.h>
> -
> -static inline void cpu_enter_lowpower(void)
> -{
> -       unsigned int v;
> -
> -       asm volatile(
> -       "       mcr     p15, 0, %1, c7, c5, 0\n"
> -       "       dsb\n"
> -       /*
> -        * Turn off coherency
> -        */
> -       "       mrc     p15, 0, %0, c1, c0, 1\n"
> -       "       bic     %0, %0, #0x20\n"
> -       "       mcr     p15, 0, %0, c1, c0, 1\n"
> -       "       mrc     p15, 0, %0, c1, c0, 0\n"
> -       "       bic     %0, %0, %2\n"
> -       "       mcr     p15, 0, %0, c1, c0, 0\n"
> -       : "=&r" (v)
> -       : "r" (0), "Ir" (CR_C)
> -       : "cc", "memory");
> -}
> -
> -static inline void cpu_leave_lowpower(void)
> -{
> -       unsigned int v;
> -
> -       asm volatile("mrc       p15, 0, %0, c1, c0, 0\n"
> -       "       orr     %0, %0, %1\n"
> -       "       mcr     p15, 0, %0, c1, c0, 0\n"
> -       "       mrc     p15, 0, %0, c1, c0, 1\n"
> -       "       orr     %0, %0, #0x20\n"
> -       "       mcr     p15, 0, %0, c1, c0, 1\n"
> -       : "=&r" (v)
> -       : "Ir" (CR_C)
> -       : "cc");
> -}

I am not the best at assembly code but I can see that the
two codes (here and hotplug.c) are slightly different.

How can we ensure if this patch is okay?


From linus.walleij at linaro.org  Mon May 20 03:03:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 09:03:00 +0200
Subject: [PATCHv10 2/9] of/pci: Provide support for parsing PCI DT ranges
 property
In-Reply-To: <20130519203156.GO11137@titan.lakedaemon.net>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-3-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130519203156.GO11137@titan.lakedaemon.net>
Message-ID: <CACRpkdamm9vh_bXenJigwTYmN=n_SsEp+GQqAe9rdm8PRxPsqw@mail.gmail.com>

On Sun, May 19, 2013 at 10:31 PM, Jason Cooper <jason at lakedaemon.net> wrote:

> patches 2, 3, and 4 applied to mvebu/of_pci to facilitate others
> (LinusW) basing their work off of it.

Thanks, is this going to be pulled into ARM SoC soon-ish?

I think Arnd may need this for some PCI work too.

Yours,
Linus Walleij


From gang.chen at asianux.com  Mon May 20 03:12:57 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 15:12:57 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL(clear_page)'
Message-ID: <5199CCF9.4030305@asianux.com>


Need 'EXPORT_SYMBOL(clear_page)' if building with allmodconfig.

The related errors:
  ERROR: "clear_page" [fs/ocfs2/dlm/ocfs2_dlm.ko] undefined!
  ERROR: "clear_page" [fs/ntfs/ntfs.ko] undefined!
  ERROR: "clear_page" [fs/gfs2/gfs2.ko] undefined!
  ERROR: "clear_page" [fs/fuse/fuse.ko] undefined!
  ERROR: "clear_page" [fs/ext3/ext3.ko] undefined!
  ERROR: "clear_page" [fs/ext2/ext2.ko] undefined!
  ERROR: "clear_page" [fs/exofs/libore.ko] undefined!
  ERROR: "clear_page" [fs/exofs/exofs.ko] undefined!
  ERROR: "clear_page" [drivers/block/brd.ko] undefined!


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/kernel/arm64ksyms.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
index 7df1aad..41b4f62 100644
--- a/arch/arm64/kernel/arm64ksyms.c
+++ b/arch/arm64/kernel/arm64ksyms.c
@@ -34,6 +34,7 @@ EXPORT_SYMBOL(__strnlen_user);
 EXPORT_SYMBOL(__strncpy_from_user);
 
 EXPORT_SYMBOL(copy_page);
+EXPORT_SYMBOL(clear_page);
 
 EXPORT_SYMBOL(__copy_from_user);
 EXPORT_SYMBOL(__copy_to_user);
-- 
1.7.7.6


From marc.zyngier at arm.com  Mon May 20 03:15:04 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 20 May 2013 09:15:04 +0200
Subject: [PATCH] arm64: kernel: compiling issue,
 need =?UTF-8?Q?=27EXPORT=5FSY?=
 =?UTF-8?Q?MBOL=5FGPL=28read=5Fcurrent=5Ftimer=29=27?=
In-Reply-To: <5199C725.8050102@asianux.com>
References: <5199C725.8050102@asianux.com>
Message-ID: <168084c28e8ba5124c05553e97463172@localhost>

On Mon, 20 May 2013 14:48:05 +0800, Chen Gang <gang.chen at asianux.com>
wrote:
> Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with allmodconfig.
> 
> The related error:
>   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
>   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
>   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
>   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/kernel/time.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
> index a551f88..7fcba80 100644
> --- a/arch/arm64/kernel/time.c
> +++ b/arch/arm64/kernel/time.c
> @@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
>  	*timer_value = arch_timer_read_counter();
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(read_current_timer);
>  
>  void __init time_init(void)
>  {

While this solves the problem, I'm not sure this is the best fix. The real
issue is with get_cycles, which is a macro around read_current_timer.

AArch32 exports it because of the number of timer implementations. On
arm64, we should be able to just return CNTVCT_EL0.

Catalin, Will, what do you think?

        M.
-- 
Fast, cheap, reliable. Pick two.


From gang.chen at asianux.com  Mon May 20 03:15:08 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 15:15:08 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL(clear_page)'
In-Reply-To: <5199CCF9.4030305@asianux.com>
References: <5199CCF9.4030305@asianux.com>
Message-ID: <5199CD7C.4080304@asianux.com>


After this patch, can pass building arm64 with allmodconfig under
next-20130517 tree. :-)

On 05/20/2013 03:12 PM, Chen Gang wrote:
> 
> Need 'EXPORT_SYMBOL(clear_page)' if building with allmodconfig.
> 
> The related errors:
>   ERROR: "clear_page" [fs/ocfs2/dlm/ocfs2_dlm.ko] undefined!
>   ERROR: "clear_page" [fs/ntfs/ntfs.ko] undefined!
>   ERROR: "clear_page" [fs/gfs2/gfs2.ko] undefined!
>   ERROR: "clear_page" [fs/fuse/fuse.ko] undefined!
>   ERROR: "clear_page" [fs/ext3/ext3.ko] undefined!
>   ERROR: "clear_page" [fs/ext2/ext2.ko] undefined!
>   ERROR: "clear_page" [fs/exofs/libore.ko] undefined!
>   ERROR: "clear_page" [fs/exofs/exofs.ko] undefined!
>   ERROR: "clear_page" [drivers/block/brd.ko] undefined!
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/kernel/arm64ksyms.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
> index 7df1aad..41b4f62 100644
> --- a/arch/arm64/kernel/arm64ksyms.c
> +++ b/arch/arm64/kernel/arm64ksyms.c
> @@ -34,6 +34,7 @@ EXPORT_SYMBOL(__strnlen_user);
>  EXPORT_SYMBOL(__strncpy_from_user);
>  
>  EXPORT_SYMBOL(copy_page);
> +EXPORT_SYMBOL(clear_page);
>  
>  EXPORT_SYMBOL(__copy_from_user);
>  EXPORT_SYMBOL(__copy_to_user);
> 


-- 
Chen Gang

Asianux Corporation


From asia at aluzyjna.waw.pl  Mon May 20 03:30:48 2013
From: asia at aluzyjna.waw.pl (=?windows-1251?B?8ujs7vTl6Q==?=)
Date: Mon, 20 May 2013 10:30:48 +0300
Subject: =?windows-1251?B?xfHr6CDt4OTu4eXtIOTu4fDu8u3l6fjo6SD9?=
 =?windows-1251?B?9PTl6vI=?=
Message-ID: <352B5B20984E4B23973517F4B7CF6066@idkczsk>

  ????????? ??? ?????????? ? ??? ?? ???????????. ?????????? ????????. ????????? ?????? ???? ?? ????? ??????. ???????? ???? ???????. ?? ??????????? ??????????? ????????? ?? ???????????? ??????????????? ?????? ????? ?????????? ?????. ?? ??????: http://goo.gl/5JQX1?/qbBPPi . 
 


From gang.chen at asianux.com  Mon May 20 03:48:53 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 15:48:53 +0800
Subject: [PATCH] kernel/sched/core.c: need return NULL when BUG() is defined
 as empty.
Message-ID: <5199D565.4070307@asianux.com>


When neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, need let function
return failure value ('NULL') instead of random value.

It is generated by randconfig with MMU for arm s5pv210 with
EXTRA_CFALGS=-W.

The related warnings:
  kernel/sched/core.c:2353:1: warning: control reaches end of non-void function [-Wreturn-type]

Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 kernel/sched/core.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 9ff7744..94ef8ff 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -2350,6 +2350,7 @@ pick_next_task(struct rq *rq)
 	}
 
 	BUG(); /* the idle class will always have a runnable task */
+	return NULL;
 }
 
 /*
-- 
1.7.7.6


From andriy.shevchenko at linux.intel.com  Mon May 20 03:52:34 2013
From: andriy.shevchenko at linux.intel.com (Andy Shevchenko)
Date: Mon, 20 May 2013 10:52:34 +0300
Subject: dmatest regression in 3.10-rc1
In-Reply-To: <20130517141857.GM23112@mudshark.cambridge.arm.com>
References: <20130515152803.GL23869@mudshark.cambridge.arm.com>
 <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <20130517123423.GR14863@intel.com>
 <20130517141857.GM23112@mudshark.cambridge.arm.com>
Message-ID: <1369036354.29283.115.camel@smile>

On Fri, 2013-05-17 at 15:18 +0100, Will Deacon wrote: 
> On Fri, May 17, 2013 at 01:34:23PM +0100, Vinod Koul wrote:
> > On Thu, May 16, 2013 at 04:35:53PM +0100, Will Deacon wrote:
> > > Right, so I think I understand what's causing this, but I'll leave it to
> > > Andriy to suggest a fix.

Thanks for the report.

Unfortunately neither me nor other guys in the team could not reproduce
mentioned issue on our hardware.
Nevertheless I will try to allocate time and suggest possible fix if any
comes to my mind. So, your testing and analysis is appreciated.

-- 
Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Intel Finland Oy


From linus.walleij at linaro.org  Mon May 20 04:16:35 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 10:16:35 +0200
Subject: [PATCH] pinctrl: sirf: save the status in suspend and restore
 after resuming
In-Reply-To: <1368674229-11813-1-git-send-email-Baohua.Song@csr.com>
References: <1368674229-11813-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <CACRpkdaSTC8cLi-C_gwZEk8iF=bnAce920DbKvxN6S-=75xbnA@mail.gmail.com>

On Thu, May 16, 2013 at 5:17 AM, Barry Song <Baohua.Song at csr.com> wrote:

> this patch saves the status of pinctrl registers and restore them while
> resuming. this makes all drivers have coherent status for pinmux after
> suspending and resuming.
>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

Applied, but a quick remark that you may want to fix up:

(...)

> +#ifdef CONFIG_PM_SLEEP
> +static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
> +{
> +       int i, j;
> +       struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
> +
> +       for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
> +               for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
> +                       spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
> +                               SIRFSOC_GPIO_CTRL(i, j));
> +               }
> +               spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
> +                       SIRFSOC_GPIO_INT_STATUS(i));
> +               spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
> +                       SIRFSOC_GPIO_PAD_EN(i));
> +       }
> +       spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
> +
> +       for (i = 0; i < 3; i++)

Why are you hard-coding 3 here? It looks fragile.

> +               spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
> +
> +       return 0;
> +}
> +
> +static int sirfsoc_pinmux_resume_noirq(struct device *dev)
> +{
> +       int i, j;
> +       struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
> +
> +       for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
> +               for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
> +                       writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
> +                               SIRFSOC_GPIO_CTRL(i, j));
> +               }
> +               writel(spmx->ints_regs[i], spmx->gpio_virtbase +
> +                       SIRFSOC_GPIO_INT_STATUS(i));
> +               writel(spmx->paden_regs[i], spmx->gpio_virtbase +
> +                       SIRFSOC_GPIO_PAD_EN(i));
> +       }
> +       writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
> +
> +       for (i = 0; i < 3; i++)

Dito.

Yours,
Linus Walleij


From gang.chen at asianux.com  Mon May 20 04:16:34 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 16:16:34 +0800
Subject: [PATCH] include/linux/posix_acl.h: need 'return NULL' when BUG(),
 if neither CONFIG_BUG nor HAVE_ARCH_BUG is defined.
Message-ID: <5199DBE2.5080707@asianux.com>


If neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, the BUG() will
defined as empty (e.g. randconfig with MMU for arm s5pv210)

In this case, need 'return NULL' to let upper caller knows the failure.


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 include/linux/posix_acl.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/posix_acl.h b/include/linux/posix_acl.h
index 7931efe..2c48d06 100644
--- a/include/linux/posix_acl.h
+++ b/include/linux/posix_acl.h
@@ -104,6 +104,7 @@ static inline struct posix_acl **acl_by_type(struct inode *inode, int type)
 		return &inode->i_default_acl;
 	default:
 		BUG();
+		return NULL;
 	}
 }
 
-- 
1.7.7.6


From andrew at lunn.ch  Mon May 20 04:22:05 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 May 2013 10:22:05 +0200
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and
 ge11
In-Reply-To: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520082205.GC26249@lunn.ch>

On Sun, May 19, 2013 at 10:12:43PM +0200, Gregory CLEMENT wrote:
> When platform data were moved from arch/arm/mach-mv78xx0/common.c to
> arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion:
> Consolidate ethernet platform data", there were few typo made on
> gigabit Ethernet interface ge10 and ge11. This commit writes back
> their initial value, which allows to use this interfaces again.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/plat-orion/common.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> index 251f827..c019b7a 100644
> --- a/arch/arm/plat-orion/common.c
> +++ b/arch/arm/plat-orion/common.c
> @@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = {
>  
>  static struct platform_device orion_ge10_shared = {
>  	.name		= MV643XX_ETH_SHARED_NAME,
> -	.id		= 1,
> +	.id		= 2,
>  	.dev		= {
>  		.platform_data	= &orion_ge10_shared_data,
>  	},
> @@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = {
>  
>  static struct platform_device orion_ge10 = {
>  	.name		= MV643XX_ETH_NAME,
> -	.id		= 1,
> -	.num_resources	= 2,
> +	.id		= 2,
> +	.num_resources	= 1,
>  	.resource	= orion_ge10_resources,
>  	.dev		= {
>  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> @@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = {
>  
>  static struct platform_device orion_ge11_shared = {
>  	.name		= MV643XX_ETH_SHARED_NAME,
> -	.id		= 1,
> +	.id		= 3,
>  	.dev		= {
>  		.platform_data	= &orion_ge11_shared_data,
>  	},
> @@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = {
>  
>  static struct platform_device orion_ge11 = {
>  	.name		= MV643XX_ETH_NAME,
> -	.id		= 1,
> -	.num_resources	= 2,
> +	.id		= 3,
> +	.num_resources	= 1,
>  	.resource	= orion_ge11_resources,
>  	.dev		= {
>  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> -- 
> 1.8.1.2
> 

Hi Gregory

My Bad. Thanks for fixing this.

Acked-by: Andrew Lunn <andrew at lunn.ch>

Jason, this can go into stable, as far back as 3.0.

       Andrew


From gang.chen at asianux.com  Mon May 20 04:54:07 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 20 May 2013 16:54:07 +0800
Subject: [PATCH] ARM: S5PV210: dependency issue,
 S5P_SLEEP is depend on ARM_CPU_SUSPEND
Message-ID: <5199E4AF.7040607@asianux.com>


When randconfig with MMU for arm s5pv210 (and select all cpu type),
need let S5P_SLEEP depend on ARM_CPU_SUSPEND, or will cause issue below:

  arch/arm/plat-samsung/built-in.o: In function `s3c_cpu_resume':
  arch/arm/plat-samsung/s5p-sleep.S:83: undefined reference to `cpu_resume'


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm/plat-samsung/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de..1d38541 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -483,6 +483,7 @@ config S5P_PM
 
 config S5P_SLEEP
 	bool
+	select ARM_CPU_SUSPEND
 	help
 	  Internal config node to apply common S5P sleep management code.
 	  Can be selected by S5P and newer SoCs with similar sleep procedure.
-- 
1.7.7.6


From b32955 at freescale.com  Mon May 20 04:48:56 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:48:56 +0800
Subject: [PATCH 0/6] ARM: imx6q{dl}: add the WEIM driver
Message-ID: <1369039742-10893-1-git-send-email-b32955@freescale.com>

This patch set adds a new driver for WEIM in the imx6q{dl}-sabreauto boards.

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, only the NOR is connected to WEIM.

Huang Shijie (6):
  drivers: bus: add a new driver for WEIM
  ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
  ARM: dts: imx6qdl: add more information for WEIM
  ARM: dts: imx6q: add pinctrl for WEIM NOR
  ARM: dts: imx6ql: add a pinctrl for WEIM NOR
  ARM: dts: imx6qdl: enable the WEIM NOR

 Documentation/devicetree/bindings/bus/imx-weim.txt |   69 +++++++++
 arch/arm/boot/dts/imx6dl-sabreauto.dts             |    9 +-
 arch/arm/boot/dts/imx6dl.dtsi                      |   57 ++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts              |    9 +-
 arch/arm/boot/dts/imx6q.dtsi                       |   58 ++++++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |   23 +++-
 arch/arm/boot/dts/imx6qdl.dtsi                     |    4 +-
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  145 ++++++++++++++++++++
 10 files changed, 380 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c




From b32955 at freescale.com  Mon May 20 04:49:00 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:49:00 +0800
Subject: [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
In-Reply-To: <1369039742-10893-1-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
Message-ID: <1369039742-10893-5-git-send-email-b32955@freescale.com>

Add a pinctrl for WEIM nor.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   58 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 58 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..e6174c7 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -323,6 +323,64 @@
 						>;
 					};
 				};
+
+				weim {
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_OE__EIM_OE_B     0x10
+							MX6Q_PAD_EIM_RW__EIM_RW       0x10
+							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0x10
+							MX6Q_PAD_EIM_LBA__EIM_LBA_B   0x10
+							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x8000
+							MX6Q_PAD_EIM_BCLK__EIM_BCLK   0x8000
+
+							/* data */
+							MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+							MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+							MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+							MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+							MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+							MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+							MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+							MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+							MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+							MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+							MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+							MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+							MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+							MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+							MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+							MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+
+							/* address */
+							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 			};
 		};
 
-- 
1.7.1




From b32955 at freescale.com  Mon May 20 04:48:57 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:48:57 +0800
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369039742-10893-1-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
Message-ID: <1369039742-10893-2-git-send-email-b32955@freescale.com>

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.

This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 Documentation/devicetree/bindings/bus/imx-weim.txt |   69 +++++++++
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  145 ++++++++++++++++++++
 4 files changed, 224 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c

diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644
index 0000000..9913454
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -0,0 +1,69 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+
+The term ???wireless??? does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+
+The actual devices are instantiated from the child nodes of a WEIM node.
+But now we only have the NOR device.
+
+NOR flash connected to the WEIM (found on i.MX boards) are represented as
+child nodes with a name of "nor".
+
+Required properties:
+
+ - compatible:		Should be set to "fsl, imx6q-weim"
+ - reg:			A resource specifier for the register space
+			(see the example below)
+ - interrupts:		the interrupt number, see the example below.
+ - clocks:		the clock, see the example below.
+ - #address-cells:	Must be set to 2 to allow memory address translation
+ - #size-cells:		Must be set to 1 to allow CS address passing
+ - ranges:		Must be set up to reflect the memory layout with four
+			integer values for each chip-select line in use:
+
+			   <cs-number> 0 <physical address of mapping> <size>
+
+Timing properties for child nodes. All are mandatory, not optional.
+
+ -weim-cs-index:	The CS index which the device is attaching on.
+ -weim-cs-timing:	The timing array, contains 6 timing values for the
+			weim-cs-index.
+
+Example for an i.MX6q-sabreauto board:
+	weim: weim at 021b8000 {
+		compatible = "fsl,imx6q-weim";
+		reg = <0x021b8000 0x4000>;
+		interrupts = <0 14 0x04>;
+		clocks = <&clks 196>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0x08000000 0x08000000>;
+
+		nor at 0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x02000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+
+			weim-cs-index = <0>;
+			weim-cs-timing = <0x00620081 0x00000001 0x1C022000
+					0x0000C000 0x1404a38e 0x00000000>;
+			partition at 0 {
+				label = "U-Boot";
+				reg = <0x0 0x40000>;
+			};
+
+			partition at 40000 {
+				label = "U-Boot-ENV";
+				reg = <0x40000 0x10000>;
+				read-only;
+			};
+
+			partition at 50000 {
+				label = "Kernel";
+				reg = <0x50000 0x3b0000>;
+			};
+		};
+	};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab..0f997af 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,15 @@
 
 menu "Bus devices"
 
+config IMX_WEIM
+	tristate "Freescale EIM DRIVER"
+	depends on ARCH_MXC && MTD_PHYSMAP_OF
+	help
+	  Driver for i.MX6 WEIM controller.
+	  The WEIM(Wireless External Interface Module) works like a bus.
+	  You can attach many different devices on it, such as NOR, onenand.
+	  But now, we only support the Parallel NOR.
+
 config MVEBU_MBUS
 	bool
 	depends on PLAT_ORION
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c..436bbcc 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
new file mode 100644
index 0000000..8bd9362
--- /dev/null
+++ b/drivers/bus/imx-weim.c
@@ -0,0 +1,145 @@
+/*
+ * EIM driver for Freescale's i.MX chips
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+
+struct imx_weim {
+	void __iomem *base;
+	struct clk *clk;
+};
+
+static const struct of_device_id weim_id_table[] = {
+	{ .compatible = "fsl,imx6q-weim", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, weim_id_table);
+
+#define CS_TIMING_LEN 6
+#define CS_REG_RANGE  0x18
+/* Parse and set the timing for this device. */
+static int weim_timing(struct platform_device *pdev, struct device_node *np)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+	u32 value[CS_TIMING_LEN];
+	u32 cs_idx;
+	int ret;
+	int i;
+
+	ret = of_property_read_u32(np, "weim-cs-index", &cs_idx);
+	if (ret)
+		goto weim_parse_err;
+
+	ret = of_property_read_u32_array(np, "weim-cs-timing",
+					value, CS_TIMING_LEN);
+	if (ret)
+		goto weim_parse_err;
+
+	/* set the timing for WEIM */
+	for (i = 0; i < CS_TIMING_LEN; i++)
+		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
+	return 0;
+
+weim_parse_err:
+	return ret;
+}
+
+static int weim_parse_dt(struct platform_device *pdev)
+{
+	struct device_node *child;
+	int ret;
+
+	/* We only support the Parallel NOR now. We may add more in future. */
+	child = of_find_node_by_name(NULL, "nor");
+	if (child) {
+		ret = weim_timing(pdev, child);
+		if (ret)
+			goto parse_fail;
+
+		if (!of_platform_device_create(child, NULL, &pdev->dev)) {
+			ret = -EINVAL;
+			goto parse_fail;
+		}
+	}
+	return 0;
+
+parse_fail:
+	return ret;
+}
+
+static int weim_probe(struct platform_device *pdev)
+{
+	struct imx_weim *weim;
+	struct resource *res;
+	int ret = -EINVAL;
+
+	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
+	if (!weim) {
+		ret = -ENOMEM;
+		goto weim_err;
+	}
+	platform_set_drvdata(pdev, weim);
+
+	/* get the resource */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENOENT;
+		goto weim_err;
+	}
+
+	weim->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(weim->base)) {
+		ret = PTR_ERR(weim->base);
+		goto weim_err;
+	}
+
+	/* get the clock */
+	weim->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(weim->clk))
+		goto weim_err;
+
+	clk_prepare_enable(weim->clk);
+
+	/* parse the device node */
+	ret = weim_parse_dt(pdev);
+	if (ret) {
+		clk_disable_unprepare(weim->clk);
+		goto weim_err;
+	}
+
+	dev_info(&pdev->dev, "WEIM driver registered.\n");
+	return 0;
+
+weim_err:
+	return ret;
+}
+
+static int weim_remove(struct platform_device *pdev)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(weim->clk);
+	return 0;
+}
+
+static struct platform_driver weim_driver = {
+	.driver = {
+		.name = "imx-weim",
+		.of_match_table = weim_id_table,
+	},
+	.probe   = weim_probe,
+	.remove  = weim_remove,
+};
+
+module_platform_driver(weim_driver);
+MODULE_AUTHOR("Freescale Inc.");
+MODULE_DESCRIPTION("i.MX EIM Controller Driver");
+MODULE_LICENSE("GPL");
-- 
1.7.1




From b32955 at freescale.com  Mon May 20 04:48:58 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:48:58 +0800
Subject: [PATCH 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between SPI and
 WEIM
In-Reply-To: <1369039742-10893-1-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
Message-ID: <1369039742-10893-3-git-send-email-b32955@freescale.com>

In the imx6q-sabreauto and imx6dl-sabreauto boards,
the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
it is used as a data pin for the WEIM NOR.

In order to fix the conflict, this patch removes the pin from the hog,
and adds a new pinctrl item: pinctrl_ecspi1_2.

The SPI NOR selects this pinctrl_ecspi1_2 when it is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl-sabreauto.dts   |    9 ++++++++-
 arch/arm/boot/dts/imx6q-sabreauto.dts    |    9 ++++++++-
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    2 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 60f3038..7695f70 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -25,7 +25,14 @@
 			fsl,pins = <
 				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_2: ecspi1grp-2 {
+			fsl,pins = <
+				MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 9fb3e99..67a3a6b 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -29,7 +29,14 @@
 			fsl,pins = <
 				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_2: ecspi1grp-2 {
+			fsl,pins = <
+				MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d6baa51..eb293f5 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -20,7 +20,7 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio3 19 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_2>;
 	status = "disabled"; /* pin conflict with WEIM NOR */
 
 	flash: m25p80 at 0 {
-- 
1.7.1




From b32955 at freescale.com  Mon May 20 04:48:59 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:48:59 +0800
Subject: [PATCH 3/6] ARM: dts: imx6qdl: add more information for WEIM
In-Reply-To: <1369039742-10893-1-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
Message-ID: <1369039742-10893-4-git-send-email-b32955@freescale.com>

Add the clock and compatible information for the weim.
Also adds the weim label.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461c..f21d259 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -744,9 +744,11 @@
 				reg = <0x021b4000 0x4000>;
 			};
 
-			weim at 021b8000 {
+			weim: weim at 021b8000 {
+				compatible = "fsl,imx6q-weim";
 				reg = <0x021b8000 0x4000>;
 				interrupts = <0 14 0x04>;
+				clocks = <&clks 196>;
 			};
 
 			ocotp at 021bc000 {
-- 
1.7.1




From b32955 at freescale.com  Mon May 20 04:49:01 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:49:01 +0800
Subject: [PATCH 5/6] ARM: dts: imx6ql: add a pinctrl for WEIM NOR
In-Reply-To: <1369039742-10893-1-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
Message-ID: <1369039742-10893-6-git-send-email-b32955@freescale.com>

Add a new pinctrl for WEIN NOR.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   57 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 4b13454..e51c5b7 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -183,6 +183,63 @@
 					};
 				};
 
+				weim {
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_OE__EIM_OE_B     0x10
+							MX6DL_PAD_EIM_RW__EIM_RW       0x10
+							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0x10
+							MX6DL_PAD_EIM_LBA__EIM_LBA_B   0x10
+							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x8000
+							MX6DL_PAD_EIM_BCLK__EIM_BCLK   0x8000
+
+							/* data */
+							MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+							MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+							MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+							MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+							MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+							MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+							MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+							MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+							MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+							MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+							MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+							MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+							MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+							MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+							MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+							MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+
+							/* address */
+							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 
 			};
 
-- 
1.7.1




From b32955 at freescale.com  Mon May 20 04:49:02 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 20 May 2013 16:49:02 +0800
Subject: [PATCH 6/6] ARM: dts: imx6qdl: enable the WEIM NOR
In-Reply-To: <1369039742-10893-1-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
Message-ID: <1369039742-10893-7-git-send-email-b32955@freescale.com>

Enable the WEIM NOR for imx6q{dl} boards.

For the pin conflict with SPI NOR, its status is set to "disabled".

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index eb293f5..9ce7c1d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -58,3 +58,24 @@
 	wp-gpios = <&gpio1 13 0>;
 	status = "okay";
 };
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	status = "disabled"; /* pin conflict with SPI NOR */
+
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+
+		weim-cs-index = <0>;
+		weim-cs-timing = <0x00620081 0x00000001 0x1C022000
+				0x0000C000 0x1404a38e 0x00000000>;
+	};
+};
-- 
1.7.1




From will.deacon at arm.com  Mon May 20 05:10:08 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 10:10:08 +0100
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <5199B7D6.40907@asianux.com>
References: <5199B7D6.40907@asianux.com>
Message-ID: <20130520091008.GB31359@mudshark.cambridge.arm.com>

Hi Chen,

On Mon, May 20, 2013 at 06:42:46AM +0100, Chen Gang wrote:
> 
> Add the extern variable 'screen_info' according to arm32 has done.
> 
> The related error:
>   drivers/video/console/vgacon.c:1305: undefined reference to `screen_info'
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/kernel/setup.c |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> index add6ea6..1055992 100644
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -374,3 +374,14 @@ const struct seq_operations cpuinfo_op = {
>  	.stop	= c_stop,
>  	.show	= c_show
>  };
> +
> +#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
> +struct screen_info screen_info = {
> +	.orig_video_lines	= 30,
> +	.orig_video_cols	= 80,
> +	.orig_video_mode	= 0,
> +	.orig_video_ega_bx	= 0,
> +	.orig_video_isVGA	= 1,
> +	.orig_video_points	= 8
> +};
> +#endif

I think it would be better if we added a something like
CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
like x86 can then select the former, and we can remove the long list of
architectures from the current option.

Will


From james.hogan at imgtec.com  Mon May 20 05:13:11 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 10:13:11 +0100
Subject: [PATCH v3 2/4] clk: add support for clock reparent on set_rate
In-Reply-To: <20130520041508.GA27676@codeaurora.org>
References: <1368625263-23136-1-git-send-email-james.hogan@imgtec.com>
 <1368625263-23136-3-git-send-email-james.hogan@imgtec.com>
 <20130520041508.GA27676@codeaurora.org>
Message-ID: <5199E927.3080500@imgtec.com>

On 20/05/13 05:15, Stephen Boyd wrote:
> Noticed another minor thing. I'm working on the set rate and
> parent at the same time op on top of this patch series. Hopefully
> have something soon.
> 
> On 05/15, James Hogan wrote:
>> @@ -1181,6 +1242,11 @@ static void clk_change_rate(struct clk *clk)
>>  
>>  	old_rate = clk->rate;
>>  
>> +	/* set parent */
>> +	if (clk->new_parent && clk->new_parent != clk->parent)
>> +		__clk_set_parent_no_recalc(clk, clk->new_parent,
>> +					   clk->new_parent_index);
>> +
> 
> This check here for new_parent != clk->parent ...
> 
>> @@ -1451,6 +1501,27 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
>>  	return 0;
>>  }
>>  
>> +static int __clk_set_parent_no_recalc(struct clk *clk, struct clk *parent,
>> +				      u8 p_index)
>> +{
>> +	int ret = 0;
>> +
>> +	if (clk->parent == parent)
>> +		goto out;
> 
> causes this to never be true, so we can probably drop it.
> 
>> +
>> +	/* only re-parent if the clock is not in use */
>> +	ret = __clk_set_parent(clk, parent, p_index);
>> +	if (ret)
>> +		goto out;
>> +
>> +	/* reparent, but don't propagate rate recalculation downstream */
>> +	clk_reparent(clk, parent);
>> +	clk_debug_reparent(clk, parent);
>> +
>> +out:
>> +	return ret;
>> +}
> 
> Also, we never check the return code so it's sort of useless.
> 

Hi Stephen,

Well spotted, and as you pointed it privately it can use
__clk_set_parent() instead of __clk_set_parent_no_recalc() now :)

Thanks
James



From tushar.behera at linaro.org  Mon May 20 05:35:37 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Mon, 20 May 2013 15:05:37 +0530
Subject: [PATCH 0/6] Fix suspend/resume issues created by pinmux on exynos, 
 part 2
In-Reply-To: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
Message-ID: <5199EE69.7090605@linaro.org>

On 05/17/2013 09:54 PM, Tomasz Figa wrote:
> This series aims at fixing problems with suspend/resume on Exynos SoCs
> introduced by migration of GPIO and EINT support to pin control driver
> on DT-enabled platforms.
> 
> The patches fix following issues:
>  - missing support for IRQ wake of pinctrl-exynos driver
>  - legacy GPIO and EINT save/restore handling in platform PM code
>    inappropriate on pinctrl-enabled platforms
>  - several EINT-related registers must be saved as well
>  
> The series is based on a patch by Doug Anderson that adds suspend/restore
> of pinctrl registers to pinctrl-samsung driver:
> [PATCH v3] pinctrl: samsung: fix suspend/resume functionality
> http://www.spinics.net/lists/kernel/msg1534119.html
> 
> On Exynos4210-based Trats board:
> Tested-by: Tomasz Figa <t.figa at samsung.com>
> 

On Exynos5250-based Arndale board:
Tested-by: Tushar Behera <tushar.behera at linaro.org>

> Tomasz Figa (6):
>   pinctrl: exynos: Add support for set_irq_wake of wake-up EINTs
>   ARM: EXYNOS: Fix EINT wake-up mask configuration when pinctrl is used
>   ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled platforms
>   pinctrl: samsung: Add support for SoC-specific suspend/resume
>     callbacks
>   pinctrl: samsung: Allow per-bank SoC-specific private data
>   pinctrl: exynos: Handle suspend/resume of GPIO EINT registers
> 
>  arch/arm/mach-exynos/include/mach/pm-core.h |  14 +++-
>  arch/arm/plat-samsung/pm.c                  |  17 +++--
>  drivers/pinctrl/pinctrl-exynos.c            | 106 ++++++++++++++++++++++++++++
>  drivers/pinctrl/pinctrl-exynos.h            |   1 +
>  drivers/pinctrl/pinctrl-samsung.c           |   6 ++
>  drivers/pinctrl/pinctrl-samsung.h           |   4 ++
>  6 files changed, 142 insertions(+), 6 deletions(-)
> 


-- 
Tushar Behera


From andrew at lunn.ch  Mon May 20 05:43:18 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 May 2013 11:43:18 +0200
Subject: [RFC PATCH 0/5] ARM: mv78x00: First step to convert mv78x00 to
 Device Tree
In-Reply-To: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520094318.GD26249@lunn.ch>

On Sun, May 19, 2013 at 11:39:33PM +0200, Gregory CLEMENT wrote:
> Hello,
> 
> This patch set is a first step in order to convert mach-mv78x00 to
> device tree before it joins mach-mvebu.
> 
> I managed to test it on the RD-78X00-mASA board. All the peripherals I
> have tested work as they work before the migration to the device tree:
> - UART
> - Ethernet
> - USB
> - SATA
> 
> My main concern is that the mv78x00 are MP but not SMP
> capable. Currently the same kernel run on the 2 cores and it is in the
> board file that the peripherals are assigned for each CPU. (Actually I
> didn't test this behavior, but the code is written in this way.)
> 
> I don't know how to assign a peripheral to a given CPU with the device
> tree. The only way I have in mind is to have a dts per CPU, but I am
> not sure it is very convenient.
> 
> So for now the code assigns all the peripherals to the CPU.

Hi Gregory

Could you explain what you have in a bit more detail. Are you just
bringing up one CPU and assigning all peripherals to that? Or do all
peripherals get assigned to the first CPU but both are running?

As you say, it looks like you need a DTS subtree per CPU for placing
peripherals. No idea if it will work, but i guess i would try:

       ocp at f1000000@cpu0 {
/include/ "mv78x00-peripherals.dtsi"
       }
       ocp at f1000000@cpu1 {
/include/ "mv78x00-peripherals.dtsi"
       }
 
so you get all the peripherals twice, disabled by default. In the
board-dt.c you can then do something like:


	if (mv78xx0_core_index() == 0) {
	   np = of_find_node_by_name(NULL, "ocp at f1000000@cpu0");
	else
	   np = of_find_node_by_name(NULL, "ocp at f1000000@cpu1");
	
        of_platform_populate(np, kirkwood_dt_match_table, NULL, NULL);

There are a few more details, like the GPIO controller has a different
mask register for CPU1, but that is not supported in the current mvebu
gpio code. However none of the current 3 boards make use of GPIO, let
alone GPIO interrupts.

> I am also concerned by the 2 other boards: the Marvell DB-78x00-BP
> Development Board and the Buffalo WLX (Terastation Duo) NAS. I don't
> have them and so I can't test them if I want to convert them to device
> tree too.

The Buffalo WLX is interesting. The wxl_init() does not differentiate
between CPU0 and CPU1, where as the Marvell reference boards do. So i
suspect only one CPU is running, or its broken.

It might be interesting to ask on the buffalo forums if anybody is
actually using mainline on TS-WLX.

      Andrew


From will.deacon at arm.com  Mon May 20 05:46:04 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 10:46:04 +0100
Subject: [PATCH] arm64: extable: sort the exception table at build time
In-Reply-To: <51967811.7090709@gmail.com>
References: <1368809021-25130-1-git-send-email-will.deacon@arm.com>
 <51967811.7090709@gmail.com>
Message-ID: <20130520094604.GF31359@mudshark.cambridge.arm.com>

Hi David,

On Fri, May 17, 2013 at 07:33:53PM +0100, David Daney wrote:
> On 05/17/2013 09:43 AM, Will Deacon wrote:
> > As is done for other architectures, sort the exception table at
> > build-time rather than during boot.
> >
> > Since sortextable appears to be a standalone C program relying on the
> > host elf.h to provide EM_AARCH64, I've had to add a conditional check in
> > order to allow cross-compilation on machines that aren't running a
> > bleeding-edge libc-dev.
> >
> > Signed-off-by: Will Deacon <will.deacon at arm.com>
> > ---
> >   arch/arm64/Kconfig              |  1 +
> >   arch/arm64/kernel/vmlinux.lds.S | 15 +++++++--------
> >   scripts/sortextable.c           |  5 +++++
> >   3 files changed, 13 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > index 48347dc..fb8fd90 100644
> > --- a/arch/arm64/Kconfig
> > +++ b/arch/arm64/Kconfig
> > @@ -7,6 +7,7 @@ config ARM64
> >   	select ARM_AMBA
> >   	select ARM_ARCH_TIMER
> >   	select ARM_GIC
> > +	select BUILDTIME_EXTABLE_SORT
> >   	select CLONE_BACKWARDS
> >   	select COMMON_CLK
> >   	select GENERIC_CLOCKEVENTS
> > diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> > index 3fae2be..3d527726 100644
> > --- a/arch/arm64/kernel/vmlinux.lds.S
> > +++ b/arch/arm64/kernel/vmlinux.lds.S
> > @@ -57,6 +57,13 @@ SECTIONS
> >
> >   	RO_DATA(PAGE_SIZE)
> >
> > +	. = ALIGN(8);
> > +	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
> > +		__start___ex_table = .;
> > +		*(__ex_table)
> > +		__stop___ex_table = .;
> > +	}
> > +
> >   	_etext = .;			/* End of text and rodata section */
> 
> 
> You have moved this to rodata.

I don't think I have moved this to rodata. The RO_DATA macro expands to a
bunch of sections, but it doesn't leave any of them open at the end.

> o Will the runtime sort still work like this?
> 
> o Do we care?  Maybe not.

For arm64 we'd be moving exclusively to build-time sorting, so I guess we
*could* stick the thing in rodata if we wanted to. Not sure it's worth the
linker script munging though.

Will


From linux at arm.linux.org.uk  Mon May 20 05:43:08 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 May 2013 10:43:08 +0100
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and
 ge11
In-Reply-To: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520094308.GU18614@n2100.arm.linux.org.uk>

On Sun, May 19, 2013 at 10:12:43PM +0200, Gregory CLEMENT wrote:
>  static struct platform_device orion_ge10 = {
>  	.name		= MV643XX_ETH_NAME,
> -	.id		= 1,
> -	.num_resources	= 2,
> +	.id		= 2,
> +	.num_resources	= 1,

Please consider using:

	.num_resources	= ARRAY_SIZE(orion_ge10_resources),

to help you avoid having the wrong number of resources specified.


From will.deacon at arm.com  Mon May 20 05:49:50 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 10:49:50 +0100
Subject: [PATCH] arm64: extable: sort the exception table at build time
In-Reply-To: <20130517184950.GA22304@merkur.ravnborg.org>
References: <1368809021-25130-1-git-send-email-will.deacon@arm.com>
 <20130517184950.GA22304@merkur.ravnborg.org>
Message-ID: <20130520094950.GG31359@mudshark.cambridge.arm.com>

On Fri, May 17, 2013 at 07:49:50PM +0100, Sam Ravnborg wrote:
> On Fri, May 17, 2013 at 05:43:41PM +0100, Will Deacon wrote:
> > +	. = ALIGN(8);
> > +	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
> > +		__start___ex_table = .;
> > +		*(__ex_table)
> > +		__stop___ex_table = .;
> > +	}
> 
> Here you could use:
>      EXCEPTION_TABLE(align)
> 
> (From include/asm-generic/vmlinux.lds.h)

Good spot, I'll spin a v2 using that. Looks like we don't use that for
arch/arm/ because we want to discard the section ifdef CONFIG_MMU. Maybe we
could change the generic macro to expand to nothing if !MMU, but I'm not
sure if other MMU-less architectures are playing tricks with this.

Will


From andrew at lunn.ch  Mon May 20 05:52:31 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 May 2013 11:52:31 +0200
Subject: [RFC PATCH 2/5] ARM: mv78x00: Convert RD-78X00-mASA board to
 device tree
In-Reply-To: <1368999578-19938-3-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <1368999578-19938-3-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520095231.GE26249@lunn.ch>

On Sun, May 19, 2013 at 11:39:35PM +0200, Gregory CLEMENT wrote:
> This commit converts the 'RD-78X00-mASA' board to the Device
> Tree. Most of the devices are converted to the Device Tree, the only
> devices which have not their Device Tree bindings are the Gigabit
> Ethernet ones and remain instantiated in the old way.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/mach-mv78xx0/board-dt.c           |  3 +++
>  arch/arm/mach-mv78xx0/common.h             |  7 +++++++
>  arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 10 ++++++++++
>  3 files changed, 20 insertions(+)
> 
> diff --git a/arch/arm/mach-mv78xx0/board-dt.c b/arch/arm/mach-mv78xx0/board-dt.c
> index 4995fee..5111cbd 100644
> --- a/arch/arm/mach-mv78xx0/board-dt.c
> +++ b/arch/arm/mach-mv78xx0/board-dt.c
> @@ -26,6 +26,9 @@ static void __init mv78x00_dt_init(void)
>  	 */
>  	mv78xx0_init();
>  
> +	if (of_machine_is_compatible("marvell,rd-78x00-masa"))
> +		rd78x00_masa_init_dt();
> +
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
>  
> diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
> index 5e9485b..6e9140d 100644
> --- a/arch/arm/mach-mv78xx0/common.h
> +++ b/arch/arm/mach-mv78xx0/common.h
> @@ -17,6 +17,13 @@ struct mv_sata_platform_data;
>  /*
>   * Basic MV78xx0 init functions used early by machine-setup.
>   */
> +#ifdef CONFIG_MACH_RD78X00_MASA
> +void rd78x00_masa_init_dt(void);
> +#else
> +static inline void rd78x00_masa_init_dt(void) {};
> +#endif
> +
> +
>  int mv78xx0_core_index(void);
>  void mv78xx0_map_io(void);
>  void mv78xx0_init(void);
> diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
> index d2d06f3..8d88657 100644
> --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
> +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
> @@ -64,6 +64,16 @@ static void __init rd78x00_masa_init(void)
>  	}
>  }
>  
> +void __init rd78x00_masa_init_dt(void)
> +{
> +	/* Internal devices not ported to DT yet */
> +	mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
> +	mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
> +		mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
> +		mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
> +
> +}

Hi Gregory

First off, the indentation looks wrong. Might be a space/tab issue.

I would also be tempted to place this code into board-dt.c and not
touch or even compile rd78x00-masa-setup.c when using DT. If i
remember correctly, Jason had a patch for Kirkwood which centralized
all the ethernet setup code. You can maybe copy/paste that.

> +
>  static int __init rd78x00_pci_init(void)
>  {
>  	/*
> -- 
> 1.8.1.2
> 


From linux at arm.linux.org.uk  Mon May 20 05:54:47 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 May 2013 10:54:47 +0100
Subject: [PATCH 1/6] ARM: OMAP2+: Remove board-4430sdp.c
In-Reply-To: <20130517191751.468.89202.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
 <20130517191751.468.89202.stgit@localhost>
Message-ID: <20130520095447.GR21614@n2100.arm.linux.org.uk>

On Fri, May 17, 2013 at 12:17:51PM -0700, Tony Lindgren wrote:
> We can now boot with device tree. If you don't want to update u-boot,
> you can boot with appended DTB with the following instructions:
> 
> 1. Make sure you have the appended DTB support in .config
> 
>    CONFIG_ARM_APPENDED_DTB=y
>    CONFIG_ARM_ATAG_DTB_COMPAT=y
>    CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y
> 
> 2. Build the zImage
> 
>    $ ARCH=arm CROSS_COMPILE=... make zImage
> 
> 3. Build the device tree blobs
> 
>    $ ARCH=arm CROSS_COMPILE=... make dtbs
> 
> 4. Append the dtb to zImage
> 
>    $ cat arch/arm/boot/zImage arch/arm/boot/dts/omap4-sdp.dtb > /tmp/appended
> 
> 5. Use mkimage to produce the appended device tree uImage
> 
>    $ mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 \
>      -n "Linux" -d /tmp/appended /tmp/uImage
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Okay, I'm removing the 4430SDP from the boot test system once this goes
in, because this will mean rewriting the build system to cope with this
stuff.


From will.deacon at arm.com  Mon May 20 05:56:06 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 10:56:06 +0100
Subject: [PATCH] arm64: kernel: compiling issue, need
 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <168084c28e8ba5124c05553e97463172@localhost>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
Message-ID: <20130520095606.GH31359@mudshark.cambridge.arm.com>

On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
> On Mon, 20 May 2013 14:48:05 +0800, Chen Gang <gang.chen at asianux.com>
> wrote:
> > Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with allmodconfig.
> > 
> > The related error:
> >   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
> >   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
> >   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
> >   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
> > 
> > 
> > Signed-off-by: Chen Gang <gang.chen at asianux.com>
> > ---
> >  arch/arm64/kernel/time.c |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
> > index a551f88..7fcba80 100644
> > --- a/arch/arm64/kernel/time.c
> > +++ b/arch/arm64/kernel/time.c
> > @@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
> >  	*timer_value = arch_timer_read_counter();
> >  	return 0;
> >  }
> > +EXPORT_SYMBOL_GPL(read_current_timer);
> >  
> >  void __init time_init(void)
> >  {
> 
> While this solves the problem, I'm not sure this is the best fix. The real
> issue is with get_cycles, which is a macro around read_current_timer.
> 
> AArch32 exports it because of the number of timer implementations. On
> arm64, we should be able to just return CNTVCT_EL0.
> 
> Catalin, Will, what do you think?

Should be ok once the arch timer driver has moved exclusively to virtual
time. I'm also not sure we even need to implement read_current_timer() --
it's only used for delay-loop calibration, which we don't need for the
arch timer.

Will


From pavel at ucw.cz  Mon May 20 05:59:04 2013
From: pavel at ucw.cz (Pavel Machek)
Date: Mon, 20 May 2013 11:59:04 +0200
Subject: [RFC PATCH 1/2] ARM: delay: print dummy values for bogomips
In-Reply-To: <alpine.LFD.2.03.1305150830540.31158@syhkavp.arg>
References: <1367602547-19322-1-git-send-email-will.deacon@arm.com>
 <1367602547-19322-2-git-send-email-will.deacon@arm.com>
 <20130506231554.GB16801@amd.pavel.ucw.cz>
 <5188B8B2.5030601@arm.com>
 <alpine.LFD.2.03.1305141547180.31158@syhkavp.arg>
 <CAL_Jsq+Q5UMGo3J+vKKCRU+w4Kj0YN0exs7UCWTEOxmFjWfo3g@mail.gmail.com>
 <alpine.LFD.2.03.1305141945160.31158@syhkavp.arg>
 <20130515090103.GA12907@mudshark.cambridge.arm.com>
 <20130515114737.GA7900@amd.pavel.ucw.cz>
 <alpine.LFD.2.03.1305150830540.31158@syhkavp.arg>
Message-ID: <20130520095904.GA7279@amd.pavel.ucw.cz>

Hi!

> > > In fact, I just tried it and at least my linaro filesystem seems happy
> > > enough.
> > 
> > Would it be too much work to simply put the field back with the right
> > value? We don't have to get it as precise as we used to, that should
> > make slowdown minimum.
> 
> There is simply no right value.  And whenever there is a value, people 
> read too much into it.

You are right that there is no right value. But there are many _wrong_
values.

Take a look at CPU temperature. There's no right value there, either,
as CPU has different temperatures at different places. Displaying
heatsink temp +5C is probably ok. Displaying case temperature or
compile time constant is not.

Now, bogoMIPS is supposed to be instructions per second. Measure
instructions per second, and you have acceptable value to display. Put
back code from previous version, and you have acceptable value to
display.

"0", "1" or value from Kconfig is _not_ acceptable value.

Maybe bogomips should not have been exposed in /proc in the first
place, but it is too late now. "No regressions".

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From will.deacon at arm.com  Mon May 20 05:58:57 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 10:58:57 +0100
Subject: dmatest regression in 3.10-rc1
In-Reply-To: <1369036354.29283.115.camel@smile>
References: <20130515152803.GL23869@mudshark.cambridge.arm.com>
 <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <20130517123423.GR14863@intel.com>
 <20130517141857.GM23112@mudshark.cambridge.arm.com>
 <1369036354.29283.115.camel@smile>
Message-ID: <20130520095857.GI31359@mudshark.cambridge.arm.com>

Hi Andy,

On Mon, May 20, 2013 at 08:52:34AM +0100, Andy Shevchenko wrote:
> On Fri, 2013-05-17 at 15:18 +0100, Will Deacon wrote: 
> > On Fri, May 17, 2013 at 01:34:23PM +0100, Vinod Koul wrote:
> > > On Thu, May 16, 2013 at 04:35:53PM +0100, Will Deacon wrote:
> > > > Right, so I think I understand what's causing this, but I'll leave it to
> > > > Andriy to suggest a fix.
> 
> Thanks for the report.
> 
> Unfortunately neither me nor other guys in the team could not reproduce
> mentioned issue on our hardware.
> Nevertheless I will try to allocate time and suggest possible fix if any
> comes to my mind. So, your testing and analysis is appreciated.

Sure. They way I trigger it is to unload the module whilst the DMA is
ongoing (I'm using a software model, so I can make the DMA nice and slow --
I guess you could try using some large buffers).

My script (I just run from busybox) is:

  #!/bin/sh

  mount proc -t proc /proc
  mount sysfs -t sysfs /sys
  mount debugfs -t debugfs /sys/kernel/debug

  echo 9 > /proc/sysrq-trigger

  modprobe dmatest
  echo 8 > /sys/kernel/debug/dmatest/iterations
  echo 8 > /sys/kernel/debug/dmatest/threads_per_chan
  echo 131072 > /sys/kernel/debug/dmatest/test_buf_size
  echo 1 > /sys/kernel/debug/dmatest/run
  modprobe -r dmatest

Will


From gregory.clement at free-electrons.com  Mon May 20 05:59:04 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 20 May 2013 11:59:04 +0200
Subject: [RFC PATCH 0/5] ARM: mv78x00: First step to convert mv78x00 to
 Device Tree
In-Reply-To: <20130520094318.GD26249@lunn.ch>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <20130520094318.GD26249@lunn.ch>
Message-ID: <5199F3E8.8060008@free-electrons.com>

On 05/20/2013 11:43 AM, Andrew Lunn wrote:
> On Sun, May 19, 2013 at 11:39:33PM +0200, Gregory CLEMENT wrote:
>> Hello,
>>
>> This patch set is a first step in order to convert mach-mv78x00 to
>> device tree before it joins mach-mvebu.
>>
>> I managed to test it on the RD-78X00-mASA board. All the peripherals I
>> have tested work as they work before the migration to the device tree:
>> - UART
>> - Ethernet
>> - USB
>> - SATA
>>
>> My main concern is that the mv78x00 are MP but not SMP
>> capable. Currently the same kernel run on the 2 cores and it is in the
>> board file that the peripherals are assigned for each CPU. (Actually I
>> didn't test this behavior, but the code is written in this way.)
>>
>> I don't know how to assign a peripheral to a given CPU with the device
>> tree. The only way I have in mind is to have a dts per CPU, but I am
>> not sure it is very convenient.
>>
>> So for now the code assigns all the peripherals to the CPU.
> 
> Hi Gregory

Hi Andrew,

> 
> Could you explain what you have in a bit more detail. Are you just
> bringing up one CPU and assigning all peripherals to that? Or do all
> peripherals get assigned to the first CPU but both are running?

Currently I didn't find (but I didn't looked for so much) how to
boot the kernel on both CPU even with the legacy code. So I am just
bringing up one CPU and assigning all peripherals to that.

> 
> As you say, it looks like you need a DTS subtree per CPU for placing
> peripherals. No idea if it will work, but i guess i would try:
> 
>        ocp at f1000000@cpu0 {
> /include/ "mv78x00-peripherals.dtsi"
>        }
>        ocp at f1000000@cpu1 {
> /include/ "mv78x00-peripherals.dtsi"
>        }
>  
> so you get all the peripherals twice, disabled by default. In the
> board-dt.c you can then do something like:
> 
> 
> 	if (mv78xx0_core_index() == 0) {
> 	   np = of_find_node_by_name(NULL, "ocp at f1000000@cpu0");
> 	else
> 	   np = of_find_node_by_name(NULL, "ocp at f1000000@cpu1");
> 	
>         of_platform_populate(np, kirkwood_dt_match_table, NULL, NULL);
> 

very interesting idea, I will try it to see how it goes!

> There are a few more details, like the GPIO controller has a different
> mask register for CPU1, but that is not supported in the current mvebu
> gpio code. However none of the current 3 boards make use of GPIO, let
> alone GPIO interrupts.
> 
>> I am also concerned by the 2 other boards: the Marvell DB-78x00-BP
>> Development Board and the Buffalo WLX (Terastation Duo) NAS. I don't
>> have them and so I can't test them if I want to convert them to device
>> tree too.
> 
> The Buffalo WLX is interesting. The wxl_init() does not differentiate
> between CPU0 and CPU1, where as the Marvell reference boards do. So i
> suspect only one CPU is running, or its broken.

It looked like a copy and paste of the rd78x00_masa_init function: it kept
the comment about the 2 CPUs "Partition on-chip peripherals between the
two CPU cores."

> 
> It might be interesting to ask on the buffalo forums if anybody is
> actually using mainline on TS-WLX.

Do you know where is this forum?

Thanks for your review and your ideas!

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Mon May 20 06:00:08 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 20 May 2013 12:00:08 +0200
Subject: [RFC PATCH 2/5] ARM: mv78x00: Convert RD-78X00-mASA board to
 device tree
In-Reply-To: <20130520095231.GE26249@lunn.ch>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <1368999578-19938-3-git-send-email-gregory.clement@free-electrons.com>
 <20130520095231.GE26249@lunn.ch>
Message-ID: <5199F428.7000305@free-electrons.com>

On 05/20/2013 11:52 AM, Andrew Lunn wrote:
> On Sun, May 19, 2013 at 11:39:35PM +0200, Gregory CLEMENT wrote:
>> This commit converts the 'RD-78X00-mASA' board to the Device
>> Tree. Most of the devices are converted to the Device Tree, the only
>> devices which have not their Device Tree bindings are the Gigabit
>> Ethernet ones and remain instantiated in the old way.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
>> ---
>>  arch/arm/mach-mv78xx0/board-dt.c           |  3 +++
>>  arch/arm/mach-mv78xx0/common.h             |  7 +++++++
>>  arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 10 ++++++++++
>>  3 files changed, 20 insertions(+)
>>
>> diff --git a/arch/arm/mach-mv78xx0/board-dt.c b/arch/arm/mach-mv78xx0/board-dt.c
>> index 4995fee..5111cbd 100644
>> --- a/arch/arm/mach-mv78xx0/board-dt.c
>> +++ b/arch/arm/mach-mv78xx0/board-dt.c
>> @@ -26,6 +26,9 @@ static void __init mv78x00_dt_init(void)
>>  	 */
>>  	mv78xx0_init();
>>  
>> +	if (of_machine_is_compatible("marvell,rd-78x00-masa"))
>> +		rd78x00_masa_init_dt();
>> +
>>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>>  }
>>  
>> diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
>> index 5e9485b..6e9140d 100644
>> --- a/arch/arm/mach-mv78xx0/common.h
>> +++ b/arch/arm/mach-mv78xx0/common.h
>> @@ -17,6 +17,13 @@ struct mv_sata_platform_data;
>>  /*
>>   * Basic MV78xx0 init functions used early by machine-setup.
>>   */
>> +#ifdef CONFIG_MACH_RD78X00_MASA
>> +void rd78x00_masa_init_dt(void);
>> +#else
>> +static inline void rd78x00_masa_init_dt(void) {};
>> +#endif
>> +
>> +
>>  int mv78xx0_core_index(void);
>>  void mv78xx0_map_io(void);
>>  void mv78xx0_init(void);
>> diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
>> index d2d06f3..8d88657 100644
>> --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
>> +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
>> @@ -64,6 +64,16 @@ static void __init rd78x00_masa_init(void)
>>  	}
>>  }
>>  
>> +void __init rd78x00_masa_init_dt(void)
>> +{
>> +	/* Internal devices not ported to DT yet */
>> +	mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
>> +	mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
>> +		mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
>> +		mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
>> +
>> +}
> 
> Hi Gregory
> 
> First off, the indentation looks wrong. Might be a space/tab issue.

Thanks I will fix it

> 
> I would also be tempted to place this code into board-dt.c and not
> touch or even compile rd78x00-masa-setup.c when using DT. If i
> remember correctly, Jason had a patch for Kirkwood which centralized
> all the ethernet setup code. You can maybe copy/paste that.

OK I will have a look on it.
> 
>> +
>>  static int __init rd78x00_pci_init(void)
>>  {
>>  	/*
>> -- 
>> 1.8.1.2
>>


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From andrew at lunn.ch  Mon May 20 06:07:14 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 May 2013 12:07:14 +0200
Subject: [RFC PATCH 0/5] ARM: mv78x00: First step to convert mv78x00 to
 Device Tree
In-Reply-To: <5199F3E8.8060008@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <20130520094318.GD26249@lunn.ch>
 <5199F3E8.8060008@free-electrons.com>
Message-ID: <20130520100714.GF26249@lunn.ch>

On Mon, May 20, 2013 at 11:59:04AM +0200, Gregory CLEMENT wrote:
> On 05/20/2013 11:43 AM, Andrew Lunn wrote:
> > On Sun, May 19, 2013 at 11:39:33PM +0200, Gregory CLEMENT wrote:
> >> Hello,
> >>
> >> This patch set is a first step in order to convert mach-mv78x00 to
> >> device tree before it joins mach-mvebu.
> >>
> >> I managed to test it on the RD-78X00-mASA board. All the peripherals I
> >> have tested work as they work before the migration to the device tree:
> >> - UART
> >> - Ethernet
> >> - USB
> >> - SATA
> >>
> >> My main concern is that the mv78x00 are MP but not SMP
> >> capable. Currently the same kernel run on the 2 cores and it is in the
> >> board file that the peripherals are assigned for each CPU. (Actually I
> >> didn't test this behavior, but the code is written in this way.)
> >>
> >> I don't know how to assign a peripheral to a given CPU with the device
> >> tree. The only way I have in mind is to have a dts per CPU, but I am
> >> not sure it is very convenient.
> >>
> >> So for now the code assigns all the peripherals to the CPU.
> > 
> > Hi Gregory
> 
> Hi Andrew,
> 
> > 
> > Could you explain what you have in a bit more detail. Are you just
> > bringing up one CPU and assigning all peripherals to that? Or do all
> > peripherals get assigned to the first CPU but both are running?
> 
> Currently I didn't find (but I didn't looked for so much) how to
> boot the kernel on both CPU even with the legacy code. So I am just
> bringing up one CPU and assigning all peripherals to that.

Hi Gregory

Did you try looking at UART 1. It could be there is a second uboot
instance running on it which is for CPU1.

> > It might be interesting to ask on the buffalo forums if anybody is
> > actually using mainline on TS-WLX.
> 
> Do you know where is this forum?

http://forum.buffalo.nas-central.org

	Andrew


From linux at arm.linux.org.uk  Mon May 20 06:16:24 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 May 2013 11:16:24 +0100
Subject: [RFC 3/4] DRM: add OF support for Dove DRM driver
In-Reply-To: <20130518211846.0ef5a14b@armhf>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <1368897139-25485-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368897139-25485-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130518194502.102caa9e@armhf> <5197C650.9020802@gmail.com>
 <20130518211846.0ef5a14b@armhf>
Message-ID: <20130520101624.GV18614@n2100.arm.linux.org.uk>

On Sat, May 18, 2013 at 09:18:46PM +0200, Jean-Francois Moine wrote:
> The general hardware code of both drivers is close enough for merging
> may be done starting from anyone. But the general layout is not:
> 
> - my driver is DT driven and has one card with 2 CTRC's and 2 connectors.
> 
> - Russell's is non-DT, so, with some extra code I am not aware of, with
>   any number of cards each one with one CRTC and one connector (no, I

Utter shit, and I've told you before.  I'm not going to repeat it again,
and I warned you that we would have a falling out.  As you seem to be
immune to my comments provided in a sane manner, I'm now just going to
ignore you in the future because you're clearly not bothering to read
anything I'm telling you.  That makes further discussion with you utterly
pointless.

>   tried it, you cannot clone a connector of one card to the connector
>   of another card).
> 
> So, for me, merging means enhance my code from Russell's, but I will
> not go to a non-DT kernel.

You seem to see DT setups vs non-DT setups as two entirely separate things.
They are not.  We have plenty of drivers which work in both setups just
fine.

So really all of your points above are utter trash to me - really.

As to illustrate the point, my TDA19988 backend is now _just_ a slave
encoder backend, it has nothing TDA19988 specific, nor does it have
anything cubox specific there; the cubox specific part has been moved
up into dove_drv.c as pure data, and that data can be constructed
either from platform data or from OF properties parsed by dove_drv.c.

But why did I just bother to type that.  You're just going to ignore it
and keep repeating your same old claptrap.


From will.deacon at arm.com  Mon May 20 06:18:41 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 11:18:41 +0100
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130517201639.GL10369@alberich>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
 <20130513095846.GC29814@mudshark.cambridge.arm.com>
 <20130513104147.GF10369@alberich> <20130517201639.GL10369@alberich>
Message-ID: <20130520101841.GK31359@mudshark.cambridge.arm.com>

Hi Andreas,

On Fri, May 17, 2013 at 09:16:39PM +0100, Andreas Herrmann wrote:
> On Mon, May 13, 2013 at 12:41:47PM +0200, Andreas Herrmann wrote:
> > On Mon, May 13, 2013 at 05:58:46AM -0400, Will Deacon wrote:
> > > Again, you also need to tie in topology information if you go down this
> > > route.
> 
> I still don't like the approach of having two independend lists that
> must be in sync to associate a master with its stream-ids.
> 
> Why? Say you have 8 masters for an SMMU with 1 or 2 stream-ids each:
> 
>      	 smmu {
> 		...
>                 mmu-masters = <&dma0>, <&dma0>, <&dma1>, <&dma1>,
> 			      <&dma2>, <&dma2>, <&dma4>, <&dma4>,
> 			      <&dma5>, <&dma6>, <&dma7>, <&dma8>;
>                 stream-ids =	<0>, <1>, <2>, <3>,
> 				<4>, <5>, <6>, <7>,
> 		                <8>, <9>, <0xa>, <0xb>;
> 	}
> 
> Couldn't we use of_phandle_args for this purpose? So your example
> 
> +        smmu {
> 		 ...
> +                mmu-masters = <&dma0>,
> +                              <&dma0>,
> +                              <&dma1>;
> +                stream-ids  = <0xd01d>,
> +                              <0xd01e>,
> +                              <0xd11c>;
> +        };
> 
> would look like
> 
> 	dma0 {
> 		...
> 		#stream-id-cells = <2>
> 		...
> 	}
> 
> 	dma1 {
> 		...
> 		#stream-id-cells = <1>
> 		...
> 	}
> 
>         smmu {
> 		...
> 		mmu-masters = <&dma0 0xd01d 0xd01e
> 			       &dma1 0xd11c>,
>        };
> 
> and my example would be converted to
> 
> 	smmu {
> 		...
>                 mmu-masters = <&dma0 0 1 &dma1 2 3 &dma2 4 5
> 			       &dma4 6 7 &dma5 8 &dma6 9
> 			       &dma7 0xa &dma8 0xb>
> 		...
> 	}

That also looks fine to me, although I'd like to write the parsing code in
my driver before I commit to anything!

> Of course usage of of_phandle_args would restrict the number of
> stream-ids per master to 8 (which is currently used as
> MAX_PHANDLE_ARGS). But I don't think that this is a restriction in
> practice or do you expect to have more than 8 stream-ids per master
> (ie. per struct device in Linux)?

Actually, I think that could be a problem. It doesn't sound unlikely that
multi-channel DMA controllers could have:

	- Separate instruction fetch streamid per channel
	- Separate read/write streamids per channel

so 8 does sound a bit small to me. How difficult would it be to bump that
number in the future if we needed to?

Will


From plagnioj at jcrosoft.com  Mon May 20 06:12:37 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 12:12:37 +0200
Subject: [PATCH 1/5] usb: add Atmel USBA UDC DT support
In-Reply-To: <519997CA.8010503@atmel.com>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
 <519997CA.8010503@atmel.com>
Message-ID: <20130520101237.GA9937@game.jcrosoft.org>

> >
> >-static int __init usba_udc_probe(struct platform_device *pdev)
> >+#ifdef CONFIG_OF
> >+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
> >+						    struct usba_udc *udc)
> >+{
> >+	u32 val;
> >+	const char *name;
> >+	enum of_gpio_flags flags;
> >+	struct device_node *np = pdev->dev.of_node;
> >+	struct device_node *pp;
> >+	int i, ret;
> >+	struct usba_ep *eps, *ep;
> >+
> >+	udc->num_ep = 0;
> >+
> >+	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
> >+						&flags);
> >+	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
> >+
> >+	pp = NULL;
> >+	while ((pp = of_get_next_child(np, pp)))
> >+		udc->num_ep++;
> >+
> >+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
> >+			   GFP_KERNEL);
> 
> Using devm_kzalloc will cause issue when build as modules, and load
> and unload this driver, the second time unload, it will come out
> following segment fault, log as following. Using kzalloc will fix
> it.

no devm_kzalloc is the right one to use

if there is a this not in the drivers and kzalloc is not the solution
we need to find the real reason as devm_xxx are used everywhere by now

Best Regards,
J.


From josephl at nvidia.com  Mon May 20 06:39:23 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:23 +0800
Subject: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
Message-ID: <1369046369-12489-1-git-send-email-josephl@nvidia.com>

Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
as CPU core and a enhanced flow controller for CPU power control. So
we need to skip some code that was for Contex-A9 and some other support
code that was for other Tegra SoC chips. Then adding the proper power up
and hot plug control for Tegra114.

Verified on Seaboard, Cardhu and Dalmore.

V2:
* Double confirmed the patch set is OK with THUMB2_KERNEL enabled.

Joseph Lo (6):
  ARM: tegra: add an assembly marco to check Tegra SoC ID
  ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
  ARM: tegra: make tegra_resume can work for Tegra114
  ARM: tegra114: add power up sequence for warm boot CPU
  clk: tegra114: implement wait_for_reset and disable_clock for
    tegra_cpu_car_ops
  ARM: tegra114: add CPU hotplug support

 arch/arm/mach-tegra/Makefile        |  1 +
 arch/arm/mach-tegra/flowctrl.h      |  1 +
 arch/arm/mach-tegra/fuse.h          | 22 ++++++++--------
 arch/arm/mach-tegra/hotplug.c       |  2 ++
 arch/arm/mach-tegra/platsmp.c       | 25 +++++++++++++++++-
 arch/arm/mach-tegra/reset-handler.S | 51 +++++++++++++++++++++----------------
 arch/arm/mach-tegra/sleep-tegra30.S | 30 ++++++++++++++++++----
 arch/arm/mach-tegra/sleep.S         |  8 +++---
 arch/arm/mach-tegra/sleep.h         | 35 ++++++++++++++++++++-----
 drivers/clk/tegra/clk-tegra114.c    | 23 ++++++++++++++++-
 10 files changed, 150 insertions(+), 48 deletions(-)

-- 
1.8.2.2



From josephl at nvidia.com  Mon May 20 06:39:24 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:24 +0800
Subject: [PATCH V2 1/6] ARM: tegra: add an assembly marco to check Tegra SoC ID
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369046369-12489-2-git-send-email-josephl@nvidia.com>

There are some Tegra SoC ID checking code around the low level assembly
code. Adding a marco to replace them. For the single image to support all
the Tegra series, we may also need the marco in other common code. So we
make it become a marco for the usage.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V2:
* refine the tegra_get_soc_id marco
---
 arch/arm/mach-tegra/fuse.h          | 22 ++++++++++++----------
 arch/arm/mach-tegra/reset-handler.S | 25 +++++++++----------------
 arch/arm/mach-tegra/sleep.h         |  9 +++++++++
 3 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d..def7968 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
 #ifndef __MACH_TEGRA_FUSE_H
 #define __MACH_TEGRA_FUSE_H
 
-enum tegra_revision {
-	TEGRA_REVISION_UNKNOWN = 0,
-	TEGRA_REVISION_A01,
-	TEGRA_REVISION_A02,
-	TEGRA_REVISION_A03,
-	TEGRA_REVISION_A03p,
-	TEGRA_REVISION_A04,
-	TEGRA_REVISION_MAX,
-};
-
 #define SKU_ID_T20	8
 #define SKU_ID_T25SE	20
 #define SKU_ID_AP25	23
@@ -40,6 +30,17 @@ enum tegra_revision {
 #define TEGRA30		0x30
 #define TEGRA114	0x35
 
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+	TEGRA_REVISION_UNKNOWN = 0,
+	TEGRA_REVISION_A01,
+	TEGRA_REVISION_A02,
+	TEGRA_REVISION_A03,
+	TEGRA_REVISION_A03p,
+	TEGRA_REVISION_A04,
+	TEGRA_REVISION_MAX,
+};
+
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
 #else
 static inline void tegra114_init_speedo_data(void) {}
 #endif
+#endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a..40af405 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
 #include <asm/hardware/cache-l2x0.h>
 
 #include "flowctrl.h"
+#include "fuse.h"
 #include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
 
-#define APB_MISC_GP_HIDREV	0x804
 #define PMC_SCRATCH41	0x140
 
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
@@ -49,10 +49,8 @@ ENTRY(tegra_resume)
 
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 	/* Are we on Tegra20? */
-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r0, [r6, #APB_MISC_GP_HIDREV]
-	and	r0, r0, #0xff00
-	cmp	r0, #(0x20 << 8)
+	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+	cmp	r6, #TEGRA20
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
 	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
@@ -98,7 +96,7 @@ ENTRY(__tegra_cpu_reset_handler_start)
  * Register usage within the reset handler:
  *
  *      Others: scratch
- *      R6  = SoC ID << 8
+ *      R6  = SoC ID
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -115,12 +113,10 @@ ENTRY(__tegra_cpu_reset_handler)
 
 	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
 
-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
-	and	r6, r6, #0xff00
+	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 t20_check:
-	cmp	r6, #(0x20 << 8)
+	cmp	r6, #TEGRA20
 	bne	after_t20_check
 t20_errata:
 	# Tegra20 is a Cortex-A9 r1p1
@@ -136,7 +132,7 @@ after_t20_check:
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 t30_check:
-	cmp	r6, #(0x30 << 8)
+	cmp	r6, #TEGRA30
 	bne	after_t30_check
 t30_errata:
 	# Tegra30 is a Cortex-A9 r2p9
@@ -163,7 +159,7 @@ after_errata:
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
-	cmp	r6, #(0x20 << 8)
+	cmp	r6, #TEGRA20
 	bne	1f
 	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
 	mov32	r5, TEGRA_PMC_BASE
@@ -210,10 +206,7 @@ __die:
 	mov32	r7, TEGRA_CLK_RESET_BASE
 
 	/* Are we on Tegra20? */
-	mov32	r6, TEGRA_APB_MISC_BASE
-	ldr	r0, [r6, #APB_MISC_GP_HIDREV]
-	and	r0, r0, #0xff00
-	cmp	r0, #(0x20 << 8)
+	cmp	r6, #TEGRA20
 	bne	1f
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb1..f9f2164 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -85,6 +85,15 @@
 	dsb
 .endm
 
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV	0x804
+.macro tegra_get_soc_id base, tmp1
+	mov32	\tmp1, \base
+	ldr	\tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
+	and	\tmp1, \tmp1, #0xff00
+	mov	\tmp1, \tmp1, lsr #8
+.endm
+
 /* Macro to resume & re-enable L2 cache */
 #ifndef L2X0_CTRL_EN
 #define L2X0_CTRL_EN	1
-- 
1.8.2.2



From josephl at nvidia.com  Mon May 20 06:39:27 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:27 +0800
Subject: [PATCH V2 4/6] ARM: tegra114: add power up sequence for warm boot CPU
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369046369-12489-5-git-send-email-josephl@nvidia.com>

For Tegra114, once the CPUs were powered up by PMC in cold boot flow. The
flow controller will maintain the power state and control power sequence
for each CPU by setting event trigger (e.g. CPU hotplug ,idle and
suspend power down/up).

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V2:
* no change
---
 arch/arm/mach-tegra/flowctrl.h |  1 +
 arch/arm/mach-tegra/platsmp.c  | 25 ++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56..7a29bae 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
 #define FLOW_CTRL_WAITEVENT		(2 << 29)
 #define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
 #define FLOW_CTRL_JTAG_RESUME		(1 << 28)
+#define FLOW_CTRL_SCLK_RESUME		(1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
 #define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
 #define FLOW_CTRL_CPU0_CSR		0x8
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226..554aedc 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -140,8 +140,31 @@ remove_clamps:
 
 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+	int ret = 0;
+
 	cpu = cpu_logical_map(cpu);
-	return tegra_pmc_cpu_power_on(cpu);
+
+	if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+		/*
+		 * Warm boot flow
+		 * The flow controller in charge of the power state and
+		 * control for each CPU.
+		 */
+		/* set SCLK as event trigger for flow controller */
+		flowctrl_write_cpu_csr(cpu, 1);
+		flowctrl_write_cpu_halt(cpu,
+				FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+	} else {
+		/*
+		 * Cold boot flow
+		 * The CPU is powered up by toggling PMC directly. It will
+		 * also initial power state in flow controller. After that,
+		 * the CPU's power state is maintained by flow controller.
+		 */
+		ret = tegra_pmc_cpu_power_on(cpu);
+	}
+
+	return ret;
 }
 
 static int __cpuinit tegra_boot_secondary(unsigned int cpu,
-- 
1.8.2.2



From josephl at nvidia.com  Mon May 20 06:39:26 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:26 +0800
Subject: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369046369-12489-4-git-send-email-josephl@nvidia.com>

Tegra114 had a newer flow controller hardware that makes its behavior and
configurations are different with other Tegra series. We fix the common
resume function of tegra_resume to make it can work on Tegra114 by checking
SoC ID. And also checking CPU primary part number to isolate the support
code for Cortex A9 and A15.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V2:
* update the commit message
* update the comment message for the CSR flags
---
 arch/arm/mach-tegra/reset-handler.S | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 40af405..424e01f 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -47,23 +47,27 @@ ENTRY(tegra_resume)
  THUMB(	it	ne )
 	bne	cpu_resume			@ no
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
 	cmp	r6, #TEGRA20
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
-	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
-	ldr	r1, [r2]
+	cpu_to_csr_req r1, r0
+	mov32	r2, TEGRA_FLOW_CTRL_BASE
+	ldr	r1, [r2, r1]
 	/* Clear event & intr flag */
 	orr	r1, r1, \
 		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
+	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, bitmaps
+				@ & ext flags for CPU power mgnt
 	bic	r1, r1, r0
 	str	r1, [r2]
 1:
 #endif
 
+	check_cpu_part_num 0xc09, r8, r9
+	bne	not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
 	/* enable SCU */
 	mov32	r0, TEGRA_ARM_PERIF_BASE
@@ -74,6 +78,7 @@ ENTRY(tegra_resume)
 
 	/* L2 cache resume & re-enable */
 	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
 
 	b	cpu_resume
 ENDPROC(tegra_resume)
-- 
1.8.2.2



From josephl at nvidia.com  Mon May 20 06:39:25 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:25 +0800
Subject: [PATCH V2 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not
 Cortex-A9
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369046369-12489-3-git-send-email-josephl@nvidia.com>

For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V2:
* no change; but double confirmed the patch is OK with THUMB2_KERNEL
---
 arch/arm/mach-tegra/sleep.S |  8 +++++---
 arch/arm/mach-tegra/sleep.h | 24 ++++++++++++++++++------
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d845..9daaef2 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
 	isb
 #ifdef CONFIG_CACHE_L2X0
 	/* Disable L2 cache */
-	mov32	r4, TEGRA_ARM_PERIF_BASE + 0x3000
-	mov	r5, #0
-	str	r5, [r4, #L2X0_CTRL]
+	check_cpu_part_num 0xc09, r9, r10
+	movweq	r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+	movteq	r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+	moveq	r5, #0
+	streq	r5, [r4, #L2X0_CTRL]
 #endif
 	mov	pc, r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index f9f2164..2269c0d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -70,19 +70,31 @@
 	movt	\reg, #:upper16:\val
 .endm
 
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+	mrc	p15, 0, \tmp1, c0, c0, 0
+	ubfx	\tmp1, \tmp1, #4, #12
+	mov32	\tmp2, \part_num
+	cmp	\tmp1, \tmp2
+.endm
+
 /* Macro to exit SMP coherency. */
 .macro exit_smp, tmp1, tmp2
 	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
 	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
 	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
 	isb
-	cpu_id	\tmp1
-	mov	\tmp1, \tmp1, lsl #2
-	mov	\tmp2, #0xf
-	mov	\tmp2, \tmp2, lsl \tmp1
-	mov32	\tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
-	str	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+	check_cpu_part_num 0xc09, \tmp1, \tmp2
+	mrceq	p15, 0, \tmp1, c0, c0, 5
+	andeq	\tmp1, \tmp1, #0xF
+	moveq	\tmp1, \tmp1, lsl #2
+	moveq	\tmp2, #0xf
+	moveq	\tmp2, \tmp2, lsl \tmp1
+	ldreq	\tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+	streq	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
 	dsb
+#endif
 .endm
 
 /* Macro to check Tegra revision */
-- 
1.8.2.2



From josephl at nvidia.com  Mon May 20 06:39:28 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:28 +0800
Subject: [PATCH V2 5/6] clk: tegra114: implement wait_for_reset and
 disable_clock for tegra_cpu_car_ops
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369046369-12489-6-git-send-email-josephl@nvidia.com>

The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
Acked-by: Mike Turquette <mturquette at linaro.org>
---
V2:
* no change
---
 drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..40d939d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 #define CLK_SOURCE_EMC 0x19c
 
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 	}
 }
 
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+	/* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+	.wait_for_reset	= tegra114_wait_cpu_in_reset,
+	.disable_clock	= tegra114_disable_cpu_clock,
+};
 
 static const struct of_device_id pmc_match[] __initconst = {
 	{ .compatible = "nvidia,tegra114-pmc" },
-- 
1.8.2.2



From josephl at nvidia.com  Mon May 20 06:39:29 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Mon, 20 May 2013 18:39:29 +0800
Subject: [PATCH V2 6/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369046369-12489-7-git-send-email-josephl@nvidia.com>

The Tegra114 is a quad cores SoC. Each core can be hotplugged including
CPU0. The hotplug sequence can be controlled by setting event trigger in
flow controller. Then the flow controller will take care all the power
sequence that include CPU up and down.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V2:
* add init value (r3) in tegra30_cpu_shutdown
* update some comment message
---
 arch/arm/mach-tegra/Makefile        |  1 +
 arch/arm/mach-tegra/hotplug.c       |  2 ++
 arch/arm/mach-tegra/reset-handler.S | 15 ++++++++++++---
 arch/arm/mach-tegra/sleep-tegra30.S | 30 +++++++++++++++++++++++++-----
 arch/arm/mach-tegra/sleep.h         |  2 ++
 5 files changed, 42 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0a..98b184e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= sleep-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a..d07f152 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -55,4 +55,6 @@ void __init tegra_hotplug_init(void)
 		tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
 		tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+	if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+		tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 424e01f..d2042ac 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -38,18 +38,24 @@
  *	  CPU boot vector when restarting the a CPU following
  *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
  *	  re-enabling sdram.
+ *
+ *	r6: SoC ID
  */
 ENTRY(tegra_resume)
 	bl	v7_invalidate_l1
 
 	cpu_id	r0
+	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+	cmp	r6, #TEGRA114
+	beq	no_cpu0_chk
+
 	cmp	r0, #0				@ CPU0?
  THUMB(	it	ne )
 	bne	cpu_resume			@ no
+no_cpu0_chk:
 
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
-	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
 	cmp	r6, #TEGRA20
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
@@ -187,11 +193,14 @@ __is_not_lp2:
 
 #ifdef CONFIG_SMP
 	/*
-	 * Can only be secondary boot (initial or hotplug) but CPU 0
-	 * cannot be here.
+	 * Can only be secondary boot (initial or hotplug)
+	 * CPU0 can't be here for Tegra20/30
 	 */
+	cmp	r6, #TEGRA114
+	beq	__no_cpu0_chk
 	cmp	r10, #0
 	bleq	__die				@ CPU0 cannot be here
+__no_cpu0_chk:
 	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
 	cmp	lr, #0
 	bleq	__die				@ no secondary startup handler
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcc..ada8821 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 
+#include "fuse.h"
 #include "sleep.h"
 #include "flowctrl.h"
 
@@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown)
  *
  * Puts the current CPU in wait-for-event mode on the flow controller
  * and powergates it -- flags (in R0) indicate the request type.
- * Must never be called for CPU 0.
  *
- * corrupts r0-r4, r12
+ * r10 = SoC ID
+ * corrupts r0-r4, r10-r12
  */
 ENTRY(tegra30_cpu_shutdown)
 	cpu_id	r3
+	tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
+	cmp	r10, #TEGRA30
+	bne	_no_cpu0_chk	@ It's not Tegra30
+
 	cmp	r3, #0
 	moveq	pc, lr		@ Must never be called for CPU 0
+_no_cpu0_chk:
 
 	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
 	cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
 	movw	r12, \
 		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
 		FLOW_CTRL_CSR_ENABLE
-	mov	r4, #(1 << 4)
+	cmp	r10, #TEGRA30
+	moveq	r4, #(1 << 4)			@ wfe bitmap
+	movne	r4, #(1 << 8)			@ wfi bitmap
  ARM(	orr	r12, r12, r4, lsl r3	)
  THUMB(	lsl	r4, r4, r3		)
  THUMB(	orr	r12, r12, r4		)
@@ -79,9 +87,20 @@ delay_1:
 	cpsid	a				@ disable imprecise aborts.
 	ldr	r3, [r1]			@ read CSR
 	str	r3, [r1]			@ clear CSR
+
 	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	beq	flow_ctrl_setting_for_lp2
+
+	/* flow controller set up for hotplug */
+	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+	b	flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+	/* flow controller set up for LP2 */
+	cmp	r10, #TEGRA30
 	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
-	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+	movne	r3, #FLOW_CTRL_WAITEVENT
+flow_ctrl_done:
+	cmp	r10, #TEGRA30
 	str	r3, [r2]
 	ldr	r0, [r2]
 	b	wfe_war
@@ -89,7 +108,8 @@ delay_1:
 __cpu_reset_again:
 	dsb
 	.align 5
-	wfe					@ CPU should be power gated here
+	wfeeq					@ CPU should be power gated here
+	wfine
 wfe_war:
 	b	__cpu_reset_again
 
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2269c0d..98b7da6 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
 					+ IO_PPSB_VIRT)
 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+					+ IO_APB_VIRT)
 #define TEGRA_PMC_VIRT	(TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
 
 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
-- 
1.8.2.2



From jonathan.austin at arm.com  Mon May 20 07:03:41 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Mon, 20 May 2013 12:03:41 +0100
Subject: [PATCHv4] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
In-Reply-To: <51979801.7010903@dawncrow.de>
References: <518AA19B.2020209@dawncrow.de> <51979801.7010903@dawncrow.de>
Message-ID: <519A030D.1030809@arm.com>

Hi Andr?

On 18/05/13 16:02, Andr? Hentschel wrote:
> Am 08.05.2013 21:03, schrieb Andr? Hentschel:
>> From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>
>>

This is strangely formatted for me too, and I use a different client 
from Will so I'm not sure that the problem is just at our end...

(Also see that the list archive has weird formatting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/167325.html )

Your first couple of patches didn't come out strangely formatted, so I'm 
not really sure what's going on.

>> Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
>> prevent it from being used as a covert channel between two tasks.
>>
>> There are more and more applications coming to WinRT, Wine could support them,
>> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
>>
>> This patch preserves that register per thread instead of clearing it.
>> Unlike the TPIDRURO, which is already switched, the TPIDRURW
>> can be updated from userspace so needs careful treatment in the case that we
>> modify TPIDRURW and call fork(). To avoid this we must always read
>> TPIDRURW in copy_thread.
>>
>> Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
>> Signed-off-by: Will Deacon <will.deacon at arm.com>
>> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
>>
>
> Hi,
> I'm not yet very familiar with the development process here,
> am i getting no feedback on v4 because of the mergewindow being closed?
> Or is there another reason? Sry for being impatient.
>

This is a feature, not a fix, so most likely it'll be included at the 
next merge window. For that to happen it should be in Russell's tree 
around the middle of this cycle.

Can you please rebase on 3.10-rc2 (when it happens) and post one more 
version? After that, assuming nobody else has any final comments, you 
could put it in to Russell's patch system...

Just as a hint - one thing you might have done to increase the chances 
of getting comments to clarify what's different between v3 and v4 - as a 
way to make life easier for reviewers you can highlight the differences 
between versions after the "---" (where you currently have the 
description of why there are so many S-o-Bs).

Hope that helps,
Jonny





From dt.tangr at gmail.com  Mon May 20 07:19:33 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Mon, 20 May 2013 21:19:33 +1000
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <201305192148.46398.arnd@arndb.de>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <201305161417.28133.arnd@arndb.de>
 <F8915E01-0FCA-4C9F-8440-63B5A73B349B@gmail.com>
 <201305192148.46398.arnd@arndb.de>
Message-ID: <C574C0B3-194E-451A-8584-A351D85C5792@gmail.com>


On 20/05/2013, at 5:48 AM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Sunday 19 May 2013, Daniel Tang wrote:
>> If the vendors for the on-SOC components are unknown, should we just
>> leave the compatible strings as is (i.e. "nspire-XXX")?
> 
> In that case, I would use the name of the company that made the SoC.
> I believe someone mentioned it was made by LSI logic.

Yep, that's right. So "lsi,nspire-XXX" should be fine?

> 
> 	Arnd



From linus.walleij at linaro.org  Mon May 20 08:01:06 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:01:06 +0200
Subject: [PATCH 02/39] dmaengine: ste_dma40: Remove unnecessary call to
 d40_phy_cfg()
In-Reply-To: <20130516105959.GI3269@gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-3-git-send-email-lee.jones@linaro.org>
 <20130516063546.GD14863@intel.com>
 <20130516072557.GD3269@gmail.com>
 <20130516094014.GJ14863@intel.com>
 <20130516105959.GI3269@gmail.com>
Message-ID: <CACRpkdabfNb_KeRqNgQQ2fVpS-_8q26k697cFOwamDLugExrhA@mail.gmail.com>

On Thu, May 16, 2013 at 12:59 PM, Lee Jones <lee.jones at linaro.org> wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
>
>> On Thu, May 16, 2013 at 08:25:57AM +0100, Lee Jones wrote:
>> > On Thu, 16 May 2013, Vinod Koul wrote:
>> >
>> > > On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
>> > > > All configuration left in d40_phy_cfg() is runtime configurable and
>> > > > there is already a call into it from d40_runtime_config(), so let's
>> > > > rely on that.
>> > > >
>> > > > Acked-by: Vinod Koul <vnod.koul at intel.com>
>> > > That needs up update!
>> >
>> > Ah, where did I get that from that?
>> >
>> > Was that my mistake, or was this in the MAINTAINERS file?
>> Certainly not in MAINTAINERS file :)
>
> My bad then, sorry.
>
> Linus,
>
> Would you be kind enough to fix it please, as it's in your tree now.

I've fixed it up!

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:05:11 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:05:11 +0200
Subject: [PATCH 12/39] crypto: ux500/hash - Prepare clock before enabling
 it
In-Reply-To: <1368611522-9984-13-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-13-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbER9p+RkNauKtpby5Mr=Tu20F-Hd_0jMfpGJYPTEOwvg@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> If we fail to prepare the ux500-hash clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my dma40 branch with Herbert's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:06:52 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:06:52 +0200
Subject: [PATCH 13/39] crypto: ux500/hash - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1368611522-9984-14-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-14-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZBoB_2dBtvNFSfz9FxfaekR9TDQmt1FQbtd3oaFJjg=g@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my dma40 branch with Herbert's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:09:11 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:09:11 +0200
Subject: [PATCH 14/39] ARM: ux500: Stop passing Hash DMA channel config
 information though pdata
In-Reply-To: <1368611522-9984-15-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-15-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZWtm_6WD=ifYLH5QogzrCyHHuhJ4xHzAjiTWX_fYAKcQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> DMA channel configuration information should be setup in the driver.
> The Ux500 Hash driver now does this, so there's no need to send it
> though here too.
>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied now that the deps are in!

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:10:54 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:10:54 +0200
Subject: [PATCH 15/39] crypto: ux500/cryp - Prepare clock before enabling
 it
In-Reply-To: <1368611522-9984-16-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-16-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaMMn10nPGXedR5J_AmDEC3a5dff2CoJ5jNcWo6jXe9VQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Ulf Hansson <ulf.hansson at linaro.org>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Herbert's ACK.

Yours,
Linus Walleij


From tixy at linaro.org  Mon May 20 08:11:21 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Mon, 20 May 2013 13:11:21 +0100
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1369051881.3511.4.camel@linaro1.home>

On Thu, 2013-05-09 at 11:34 +0100, Lorenzo Pieralisi wrote:
[...]
> +static int __init cci_probe(void)
> +{
> +	struct cci_nb_ports const *cci_config;
> +	int ret, i, nb_ace = 0, nb_ace_lite = 0;
> +	struct device_node *np, *cp;
> +	const char *match_str;
> +	bool is_ace;
> +
> +	np = of_find_matching_node(NULL, arm_cci_matches);
> +	if (!np)
> +		return -ENODEV;
> +
> +	cci_config = of_match_node(arm_cci_matches, np)->data;
> +	if (!cci_config)
> +		return -ENODEV;
> +
> +	nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
> +
> +	ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
> +	if (!ports)
> +		return -ENOMEM;
> +
> +	cci_ctrl_base = of_iomap(np, 0);
> +
> +	if (!cci_ctrl_base) {
> +		WARN(1, "unable to ioremap CCI ctrl\n");
> +		ret = -ENXIO;
> +		goto memalloc_err;
> +	}
> +
> +	for_each_child_of_node(np, cp) {
> +		i = nb_ace + nb_ace_lite;
> +
> +		if (i >= nb_cci_ports)
> +			break;

I know this is a bit late, but...

Would it not be best to check here that the node type is in fact
"slave-if", that way if we add support in later versions for other node
types (e.g. for the PMU) then we don't cause backward compatibility
issues. I'm thinking here of the same concerns that Rob raised with
"ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes"


> +		if (of_property_read_string(cp, "interface-type",
> +					&match_str)) {
> +			WARN(1, "node %s missing interface-type property\n",
> +				  cp->full_name);
> +			continue;
> +		}
> +
[..]

-- 
Tixy



From linus.walleij at linaro.org  Mon May 20 08:12:17 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:12:17 +0200
Subject: [PATCH 16/39] crypto: ux500/cryp - Set DMA configuration though
 dma_slave_config()
In-Reply-To: <1368611522-9984-17-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-17-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaROt9-L-VY8bh7Xj7W+4-VgVVOxedbt_JeGRyRi3aLEQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Herbert's ACK.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:15:23 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:15:23 +0200
Subject: [PATCH 18/39] crypto: ux500/[cryp|hash] - Show successful
 start-up in the bootlog
In-Reply-To: <1368611522-9984-19-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-19-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYUAFm4G1R=0u_c8rFH1ke5n67E_POf0wysQKVmX2pD7Q@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The Cryp driver is currently silent and the Hash driver prints the
> name of its probe function unnecessarily. Let's just put a nice
> descriptive one-liner there instead.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: Andreas Westin <andreas.westin at stericsson.com>
> Cc: linux-crypto at vger.kernel.org
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Herbert's ACK.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:17:10 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:17:10 +0200
Subject: [PATCH 19/39] ARM: ux500: Register Cyrp and Hash platform drivers
 on Snowball
In-Reply-To: <1368611522-9984-20-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-20-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdb4YKHSHf6yPC7KQWxxhP1tEdZuVfY-8ELYqj+xFNhPjw@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> These drivers are now operational and even use the latest common clk
> and DMA APIs. There's no reason why we shouldn't start them up now.
>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied now that the deps are in place.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:19:40 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:19:40 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbhzdPGRPFvcSupCJ_vYCdFOnbM-vhp60f9A5Q+jxrP=w@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I have now gone over and collected ACKs etc for the patches up until here.

Now you need Felipe's consent to proceed with the MUSB changes
through my tree.

Yours,
Linus Walleij


From arnd at arndb.de  Mon May 20 08:26:30 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 May 2013 14:26:30 +0200
Subject: [RFC PATCHv3 3/6] clk: Add TI-Nspire clock drivers
In-Reply-To: <C574C0B3-194E-451A-8584-A351D85C5792@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <201305192148.46398.arnd@arndb.de>
 <C574C0B3-194E-451A-8584-A351D85C5792@gmail.com>
Message-ID: <4603632.xLpXUpmrfP@wuerfel>

On Monday 20 May 2013 21:19:33 Daniel Tang wrote:
> On 20/05/2013, at 5:48 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> 
> > On Sunday 19 May 2013, Daniel Tang wrote:
> >> If the vendors for the on-SOC components are unknown, should we just
> >> leave the compatible strings as is (i.e. "nspire-XXX")?
> > 
> > In that case, I would use the name of the company that made the SoC.
> > I believe someone mentioned it was made by LSI logic.
> 
> Yep, that's right. So "lsi,nspire-XXX" should be fine?

I wouldn't use that combination, since lsi did not make the nspire.
For anything on the LSI chip, "lsi,zevio-XXX" would be correct,
or maybe "lsi,zevio1020-XXX" for something specific to a particular
SoC variant. For off-SoC parts, "ti,nspire-XXX" would be right,
or "ti,nspire-cx-XXX" if you care about the model.

	Arnd


From linus.walleij at linaro.org  Mon May 20 08:29:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:29:26 +0200
Subject: [PATCH 23/63] dmaengine: ste_dma40: Also report the number of
 logical channels
In-Reply-To: <1367591569-32197-24-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-24-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZQityADLQTcyLBzDsTNA18ij3c94qiFYFXKBQDQNFasQ@mail.gmail.com>

On Fri, May 3, 2013 at 4:32 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Now we know the total of physical and logical channels, we may as
> well report them within the information log.
>
> Before:
> dma40 dma40.0: hardware revision: 3 @ 0x801c0000 with 8 physical channels
>
> After:
> <as above ...> and 256 logical channels
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I'm missing Vinod's ACK on this before I can proceed with my
branch to ARM SoC.

Vinod?

Yours,
Linus Walleij


From ezequiel.garcia at free-electrons.com  Mon May 20 08:31:54 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Mon, 20 May 2013 09:31:54 -0300
Subject: mvebu: mbus device tree binding
Message-ID: <20130520123153.GA2904@localhost>

Hello Arnd and Jason,

Let's advance with the DT binding for mvebu-mbus,
and perhaps have it ready for v3.11.

Our current approach to the mbus-windows allocation is as follows:

1. Every device is located as a child of the soc/internal-regs node.
   The DT contains information for the assigned address space,
   encoded in the 'ranges' property, like this:

   soc {
   
   	ranges =  < internal-regs
        	    PCIe
		    NOR
		    ... >;
   	internal-regs {
		...
   	};
   }


2. Each driver is in charge of allocating the mbus windows, using
   the mbus API and the address region obtained through the information
   on the device tree.

Now, this approach is particularly error-prone because of (1). The
'ranges' entry in a given .dtsi file is overrided by the 'ranges'
in the per-board .dts file. So, when if we need to declare a node for a
NOR device, we need to duplicate all ranges entries from the parent
.dtsi files.

This does not seem to be hugely problematic, for one could put the
'ranges' property only in the per-board files, and remove it from the
common dtsi.

Therefore, first of all I'd like to know:

**1** What's so broken with the current approach that makes us seek for
      solution, in the form of an mbus DT binding?

In addition, reading the previous discussion you've had about this, I
noticed Arnd suggested (and even required) that the mbus binding should
update the ranges property in the DT blob each time an address window
is dynamically allocated.

**2** Why is this required? Who will read the updated ranges
      information?
      Why can't the kernel access the mbus API to obtain information
      about currently allocated windows?

Those are my questions for now and I'm quite sure many more will come
in the future, so please bare with me!

Thanks a lot,
-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com


From linus.walleij at linaro.org  Mon May 20 08:32:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:32:38 +0200
Subject: [PATCH 12/63] dmaengine: ste_dma40: Remove home-brew MAX() macro
In-Reply-To: <1367591569-32197-13-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-13-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY3TvuYjT-YEMcG1gfMTHs7Zz_rNvo+00z4Gqg4uPc63Q@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The current implementation of the DMA40's local MAX() macro evaluates
> its arguments more times than is necessary and it not type checked.
> This patch strips replaces it with a new, more efficient constant.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Reported-by: Harvey Harrison <harvey.harrison at gmail.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Still waiting for Vinod's ACK on this as well.

Vinod?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:35:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:35:01 +0200
Subject: [PATCH 10/63] dmaengine: ste_dma40: Amalgamate DMA source and
 destination channel numbers
In-Reply-To: <1367591569-32197-11-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-11-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdai7y+LBiFyK+b-CvW6p7n+TbC1iX0+XiLyg2V_8rFL+A@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Devices which utilise DMA use the same device numbers for transmitting
> and receiving. In this patch we encode the source and destination
> information into one single attribute. We can subsequently exploit the
> direction attribute to see which of the transfer directions are being
> described. This also lessens the burden on platform data.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Still waiting for an ACK from Vinod on this as well.

Vinod?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 20 08:36:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:36:31 +0200
Subject: [PATCH 09/63] dmaengine: ste_dma40: Rectify incorrect
 configuration validation checking
In-Reply-To: <1367591569-32197-10-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-10-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZO4d4jj3EEAAN-QLWj70ivc69rSqXpVwt+R68VGmxBAg@mail.gmail.com>

On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> If we compare an event's group (dev_type / 16) with STEDMA40_DEV_DST_MEMORY
> (-1), the only way we'd obtain a positive result is if we passed -16 as a
> device type, which is unfeasible. Instead, it would be much more sane to
> compare STEDMA40_DEV_DST_MEMORY against the raw dev_type in order to expect
> the expected result.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Still waiting for Vinod's ACK on this as well.

Vinod?

Yours,
Linus Walleij


From ezequiel.garcia at free-electrons.com  Mon May 20 08:44:21 2013
From: ezequiel.garcia at free-electrons.com (Ezequiel Garcia)
Date: Mon, 20 May 2013 09:44:21 -0300
Subject: mvebu: mbus device tree binding
In-Reply-To: <20130520123153.GA2904@localhost>
References: <20130520123153.GA2904@localhost>
Message-ID: <20130520124420.GA3030@localhost>

Hi,

Adding Jason to the discussion.

On Mon, May 20, 2013 at 09:31:53AM -0300, Ezequiel Garcia wrote:
> Hello Arnd and Jason,
> 
> Let's advance with the DT binding for mvebu-mbus,
> and perhaps have it ready for v3.11.
> 
> Our current approach to the mbus-windows allocation is as follows:
> 
> 1. Every device is located as a child of the soc/internal-regs node.
>    The DT contains information for the assigned address space,
>    encoded in the 'ranges' property, like this:
> 
>    soc {
>    
>    	ranges =  < internal-regs
>         	    PCIe
> 		    NOR
> 		    ... >;
>    	internal-regs {
> 		...
>    	};
>    }
> 
> 
> 2. Each driver is in charge of allocating the mbus windows, using
>    the mbus API and the address region obtained through the information
>    on the device tree.
> 
> Now, this approach is particularly error-prone because of (1). The
> 'ranges' entry in a given .dtsi file is overrided by the 'ranges'
> in the per-board .dts file. So, when if we need to declare a node for a
> NOR device, we need to duplicate all ranges entries from the parent
> .dtsi files.
> 
> This does not seem to be hugely problematic, for one could put the
> 'ranges' property only in the per-board files, and remove it from the
> common dtsi.
> 
> Therefore, first of all I'd like to know:
> 
> **1** What's so broken with the current approach that makes us seek for
>       solution, in the form of an mbus DT binding?
> 
> In addition, reading the previous discussion you've had about this, I
> noticed Arnd suggested (and even required) that the mbus binding should
> update the ranges property in the DT blob each time an address window
> is dynamically allocated.
> 
> **2** Why is this required? Who will read the updated ranges
>       information?
>       Why can't the kernel access the mbus API to obtain information
>       about currently allocated windows?
> 
> Those are my questions for now and I'm quite sure many more will come
> in the future, so please bare with me!
> 
> Thanks a lot,
> -- 
> Ezequiel Garc?a, Free Electrons
> Embedded Linux, Kernel and Android Engineering
> http://free-electrons.com

-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com


From linus.walleij at linaro.org  Mon May 20 08:49:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 14:49:01 +0200
Subject: [RFC PATCHv3 4/6] clocksource: Add TI-Nspire timer drivers
In-Reply-To: <6807056B-84F9-468D-87C6-4C4AD7D8BA99@gmail.com>
References: <1368332581-94691-1-git-send-email-dt.tangr@gmail.com>
 <1368332581-94691-5-git-send-email-dt.tangr@gmail.com>
 <CACRpkdZBFbOnQ9rCehO0yKDN7fH9VR3VYCa_NkOGJz7KN+02FQ@mail.gmail.com>
 <26FBB324-AAA9-4C10-8978-C2EC1C26672E@gmail.com>
 <CACRpkdaO7ieSdo5+Yq0+CLDfP==+DBOWn8+v0ap5iMOJy0Vf=Q@mail.gmail.com>
 <6807056B-84F9-468D-87C6-4C4AD7D8BA99@gmail.com>
Message-ID: <CACRpkdZ+nkRVwh9RguJkctCk4U7wnYBxuyg5j2nAUg7o3SvWPg@mail.gmail.com>

On Sat, May 18, 2013 at 8:40 AM, Daniel Tang <dt.tangr at gmail.com> wrote:
> On 17/05/2013, at 11:17 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
>
>>>> If this timer is really just 16 bits, it's a *pretty* good idea to use
>>>> the prescaler (I guess this is what IO_DIVIDER is) beacuse else you
>>>> will get short sleep times with CONFIG_NO_HZ_IDLE on this system,
>>>> and wake up unnecessarily often.
>>>>
>>>> The same goes for the clock event.
>>>
>>> The clock frequency is 32768Hz. Should I be scaling it down at that frequency?
>>
>> No. But that was *pretty* slow.
>>
>> The thing is that the driver is getting "some clockfrequency" from
>> the clk subsystem and does not know what it is.
>>
>> Usually (and I've seen this hardware design pattern a lot) when you
>> have a clock like this, and go talk to the clk implementation specialist
>> s/he will say "oh, yeah, I can mux in this 34 MHz clock to the timer
>> as well", and if that is possible then that is often what you want,
>> because it's good for things like HRtimers, and then it's useful to have
>> a prescaler och the clocksource/clockevent.
>>
>> You can use that 32768 Hz for clock events and clocksource (but I
>> suspect that HRtimers will never be useful on this platform due to this).
>>
>
> I forgot to mention before that there is also another timer that runs
> at the same freq as the APB (which is usually around 30MHz).
> Is this what you were alluding to? I haven't tested the driver on that timer yet.

OK then that is probably the timer you will use for clock event and
also sched_clock() in the end. (You'll be setting a better rating on it.)

I'm not alluding to it as I didn't know of it, but it makes HW-sense
that it exists :-)

> As I understand it, you're saying to use a prescaler on faster clock rates
> so the kernel can have a longer maximum delay time (since a 16 bit register
> can only hold only so much). In that case, what kind of range should I be
> scaling to? I suspect it needs to be large enough to keep the kernel from
> constantly waking but small enough for HR timers to be useful.

Yeah :-/

This is one of the cases where one thing excludes the other.

But if it's hard-wired to 32kHz you probably want to leave it as it
is.

Yours,
Linus Walleij


From nerv at dawncrow.de  Mon May 20 08:51:48 2013
From: nerv at dawncrow.de (=?UTF-8?B?QW5kcsOpIEhlbnRzY2hlbA==?=)
Date: Mon, 20 May 2013 14:51:48 +0200
Subject: [PATCHv4] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
In-Reply-To: <519A030D.1030809@arm.com>
References: <518AA19B.2020209@dawncrow.de> <51979801.7010903@dawncrow.de>
 <519A030D.1030809@arm.com>
Message-ID: <519A1C64.3020807@dawncrow.de>

Am 20.05.2013 13:03, schrieb Jonathan Austin:
> Hi Andr?
> 
> On 18/05/13 16:02, Andr? Hentschel wrote:
>> Am 08.05.2013 21:03, schrieb Andr? Hentschel:
>>> From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv at dawncrow.de>
>>>
> 
> This is strangely formatted for me too, and I use a different client from Will so I'm not sure that the problem is just at our end...
> 
> (Also see that the list archive has weird formatting:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/167325.html )
> 
> Your first couple of patches didn't come out strangely formatted, so I'm not really sure what's going on.

I'll retry it with plain Text or something. AFAIK git should understand this =UTF= style, though.

>>> Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
>>> prevent it from being used as a covert channel between two tasks.
>>>
>>> There are more and more applications coming to WinRT, Wine could support them,
>>> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
>>>
>>> This patch preserves that register per thread instead of clearing it.
>>> Unlike the TPIDRURO, which is already switched, the TPIDRURW
>>> can be updated from userspace so needs careful treatment in the case that we
>>> modify TPIDRURW and call fork(). To avoid this we must always read
>>> TPIDRURW in copy_thread.
>>>
>>> Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
>>> Signed-off-by: Will Deacon <will.deacon at arm.com>
>>> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
>>>
>>
>> Hi,
>> I'm not yet very familiar with the development process here,
>> am i getting no feedback on v4 because of the mergewindow being closed?
>> Or is there another reason? Sry for being impatient.
>>
> 
> This is a feature, not a fix, so most likely it'll be included at the next merge window. For that to happen it should be in Russell's tree around the middle of this cycle.
> 
> Can you please rebase on 3.10-rc2 (when it happens) and post one more version? After that, assuming nobody else has any final comments, you could put it in to Russell's patch system...
> 
> Just as a hint - one thing you might have done to increase the chances of getting comments to clarify what's different between v3 and v4 - as a way to make life easier for reviewers you can highlight the differences between versions after the "---" (where you currently have the description of why there are so many S-o-Bs).

I'll do, thank you very much for the reply and the clarification.



From jiada_wang at mentor.com  Mon May 20 08:51:51 2013
From: jiada_wang at mentor.com (Jiada Wang)
Date: Mon, 20 May 2013 21:51:51 +0900
Subject: [PATCH] ARM i.MX6q: fix for ldb_di_sels
Message-ID: <1369054311-2519-1-git-send-email-jiada_wang@mentor.com>

As pll5_video_div has been introduced to represent the clock
generated from post-divider for video.
Instead of pll5_video, pll5_video_div should be proper root clock
for ldb_di_sel.

Signed-off-by: Jiada Wang <jiada_wang at mentor.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/clk-imx6q.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1512590..19ea58d 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -187,7 +187,7 @@ static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m"
 static const char *gpu3d_core_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
 static const char *ipu_sels[]		= { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
-static const char *ldb_di_sels[]	= { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
+static const char *ldb_di_sels[]	= { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
 static const char *ipu_di_pre_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
 static const char *ipu1_di0_sels[]	= { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *ipu1_di1_sels[]	= { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
-- 
1.8.1.1



From srinivas.kandagatla at st.com  Mon May 20 08:48:59 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Mon, 20 May 2013 13:48:59 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <201305171636.49627.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305082148.10933.arnd@arndb.de> <518B77C1.70107@st.com>
 <201305171636.49627.arnd@arndb.de>
Message-ID: <519A1BBB.2070903@st.com>

Hi Arnd,
Thankyou for the comments.

On 17/05/13 15:36, Arnd Bergmann wrote:
> On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
>> On 08/05/13 20:48, Arnd Bergmann wrote:
>> I agree, my initial approach was having a dedicated driver specific to
>> ST syscon, however syscon seems to do things very much similar to what
>> we want, so I have integrated those 3 functions in syscon.
>> Am happy to go back with my first approach of adding ST specific syscon
>> driver if no one is actually going to benefit with such a change to
>> syscon driver.
> 
> That would at least be less controversial.

yes I agree.
> 
>> Total layout of the sysconf changes per SOC, and the bit arrangements
>> aswell, however the core IP(pinctrl, etherenet ...) and logic to drive
>> those bits remains exactly same.
> 
> It sounds like you really need a driver with high-level interfaces
> for the bits that change by each core and are needed by otherwise
> identical drivers, like the Ethernet driver you mention.
> 
> I would not go as far as you did describing the individual bits in
> the device node using these however. That driver can be layered on
> top of the existing syscon driver, but hardcode the bits for each
> SoC it knows of.
Some of the drivers like Ethernet already provide higher level
interfaces via callbacks. We did implement such a callbacks per each SOC
in non-DT case, and ended up having code duplicated for each SOC.

On the other hand using device trees to describe the HW
configuration(sysconfs) made more sense and got rid of SOC specific
callbacks.

> 
> For drivers that are essentially just wrappers around sysconf,
> I would make them one driver per SoC and use a low-level interface
> but still hardcode the offsets in the driver instead of using DT
> to find the registers.
> 
> The pinctrl and reset drivers are examples of this.

In pinctrl bindings case, I think we could do better job by replacing
the existing bindings of sysconfs for a group of banks with just two
integer offsets. This would mean that, we can still use the a common
driver across the SOCs.

And w.r.t to reset, we are planning on using sysconf based
reset-controller API sitting underneath the reset-controller subsystem.
Passing the information from device trees would be much clear and
flexible than adding new driver per/SOC.

>> 2> The infrastructure should protect the claimed registers from
>> over-writing by other drivers. We do this by claim-read/write-release
>> style API.
> 
> I don't understand this part. Is it about atomicity of accesses to
> 32-bit registers when you only want to change a bit? That is something
> the regmap interface handles already.

I forget to mention a important point here, the protection is at bit
level for the sysconfs. Some of sysconfs have bits shared across IPs, so
protecting them while the IP is still using it is what we are trying to
achieve with sysconf-claim/release apis.
While it may be overkill, but In past it has found bugs and been helpful
with a meaning full debug output.

>> 3> The driver should be able to set a group of sysconf registers bits to
>> a particular values before initialises the IP. I was thinking of doing
>> this in a same way as pinctrl state.
> 
> That does not fit well with the model we use for other subsystems. If possible,
> try to use the existing abstractions for clock, regulator, pinctrl, reset,
> etc. and call generic interfaces from the driver. When that does not work,
> create a high-level function call from your sysconf driver to do a particular
> thing (e.g. stih_sysconf_ethernet_set_phy_mode()) rather than set up random
> bits from the driver.
I agree going for a higher level api in this case makes sense.

Thanks,
srini

> 
> 	Arnd
> 
> 



From s.hauer at pengutronix.de  Mon May 20 09:18:27 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 20 May 2013 15:18:27 +0200
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369039742-10893-2-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <1369039742-10893-2-git-send-email-b32955@freescale.com>
Message-ID: <20130520131827.GB32299@pengutronix.de>

On Mon, May 20, 2013 at 04:48:57PM +0800, Huang Shijie wrote:
> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  Documentation/devicetree/bindings/bus/imx-weim.txt |   69 +++++++++
>  drivers/bus/Kconfig                                |    9 ++
>  drivers/bus/Makefile                               |    1 +
>  drivers/bus/imx-weim.c                             |  145 ++++++++++++++++++++
>  4 files changed, 224 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
>  create mode 100644 drivers/bus/imx-weim.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
> new file mode 100644
> index 0000000..9913454
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
> @@ -0,0 +1,69 @@
> +Device tree bindings for i.MX Wireless External Interface Module (WEIM)
> +
> +The term ???wireless??? does not imply that the WEIM is literally an interface
> +without wires. It simply means that this module was originally designed for
> +wireless and mobile applications that use low-power technology.
> +
> +The actual devices are instantiated from the child nodes of a WEIM node.
> +But now we only have the NOR device.
> +
> +NOR flash connected to the WEIM (found on i.MX boards) are represented as
> +child nodes with a name of "nor".
> +
> +Required properties:
> +
> + - compatible:		Should be set to "fsl, imx6q-weim"
> + - reg:			A resource specifier for the register space
> +			(see the example below)
> + - interrupts:		the interrupt number, see the example below.
> + - clocks:		the clock, see the example below.
> + - #address-cells:	Must be set to 2 to allow memory address translation
> + - #size-cells:		Must be set to 1 to allow CS address passing
> + - ranges:		Must be set up to reflect the memory layout with four
> +			integer values for each chip-select line in use:
> +
> +			   <cs-number> 0 <physical address of mapping> <size>
> +
> +Timing properties for child nodes. All are mandatory, not optional.
> +
> + -weim-cs-index:	The CS index which the device is attaching on.
> + -weim-cs-timing:	The timing array, contains 6 timing values for the
> +			weim-cs-index.
> +
> +Example for an i.MX6q-sabreauto board:
> +	weim: weim at 021b8000 {
> +		compatible = "fsl,imx6q-weim";
> +		reg = <0x021b8000 0x4000>;
> +		interrupts = <0 14 0x04>;
> +		clocks = <&clks 196>;
> +		#address-cells = <2>;

Why is address cells 2 in this example?

> +		#size-cells = <1>;
> +		ranges = <0 0 0x08000000 0x08000000>;
> +
> +		nor at 0,0 {
> +			compatible = "cfi-flash";
> +			reg = <0 0 0x02000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			bank-width = <2>;
> +
> +			weim-cs-index = <0>;
> +			weim-cs-timing = <0x00620081 0x00000001 0x1C022000
> +					0x0000C000 0x1404a38e 0x00000000>;
> +			partition at 0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x40000>;
> +			};
> +
> +			partition at 40000 {
> +				label = "U-Boot-ENV";
> +				reg = <0x40000 0x10000>;
> +				read-only;
> +			};
> +
> +			partition at 50000 {
> +				label = "Kernel";
> +				reg = <0x50000 0x3b0000>;
> +			};

The partitions are unnecessary to understand the example. Please drop them.

> +#define CS_TIMING_LEN 6
> +#define CS_REG_RANGE  0x18
> +/* Parse and set the timing for this device. */
> +static int weim_timing(struct platform_device *pdev, struct device_node *np)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +	u32 value[CS_TIMING_LEN];
> +	u32 cs_idx;
> +	int ret;
> +	int i;
> +
> +	ret = of_property_read_u32(np, "weim-cs-index", &cs_idx);
> +	if (ret)
> +		goto weim_parse_err;

It would be nice to check for cs_idx being valid.

> +
> +	ret = of_property_read_u32_array(np, "weim-cs-timing",
> +					value, CS_TIMING_LEN);
> +	if (ret)
> +		goto weim_parse_err;
> +
> +	/* set the timing for WEIM */
> +	for (i = 0; i < CS_TIMING_LEN; i++)
> +		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
> +	return 0;
> +
> +weim_parse_err:
> +	return ret;
> +}
> +
> +static int weim_parse_dt(struct platform_device *pdev)
> +{
> +	struct device_node *child;
> +	int ret;
> +
> +	/* We only support the Parallel NOR now. We may add more in future. */
> +	child = of_find_node_by_name(NULL, "nor");
> +	if (child) {
> +		ret = weim_timing(pdev, child);
> +		if (ret)
> +			goto parse_fail;
> +
> +		if (!of_platform_device_create(child, NULL, &pdev->dev)) {
> +			ret = -EINVAL;
> +			goto parse_fail;
> +		}
> +	}

What you want to do here is:

- iterate over your child nodes
- call weim_timing() for each of them
- call of_platform_device_create for each child (or even
  of_platform_populate() with the parent node)


> +	return 0;
> +
> +parse_fail:
> +	return ret;
> +}
> +
> +static int weim_probe(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim;
> +	struct resource *res;
> +	int ret = -EINVAL;
> +
> +	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
> +	if (!weim) {
> +		ret = -ENOMEM;
> +		goto weim_err;
> +	}
> +	platform_set_drvdata(pdev, weim);
> +
> +	/* get the resource */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		ret = -ENOENT;
> +		goto weim_err;
> +	}

No need to do error checking here. devm_ioremap_resource() will do this
for you and also print an error message.

> +
> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(weim->base)) {
> +		ret = PTR_ERR(weim->base);
> +		goto weim_err;
> +	}
> +
> +	/* get the clock */
> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(weim->clk))
> +		goto weim_err;
> +
> +	clk_prepare_enable(weim->clk);

what is this clock used for? Is it necessary for the register access or
is it necessary for the chipselects on the WEIM to work?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From hvaibhav at ti.com  Mon May 20 09:28:08 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 20 May 2013 18:58:08 +0530
Subject: [PATCH-V2 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output on
 SoC pad
Message-ID: <1369056490-12632-1-git-send-email-hvaibhav@ti.com>

'clkout2' comes out on the device pad and is being used by various
external on-board peripherals like, Audio codecs, Wilink and stuff.
So enable the clkout2 by default during init sequence itself
along with right pinmux configuration clkout2 output.

Also, add the missing entry of "clkout2_ck" to the AM33xx clock table.

As far as enabling of clkout2 during init is concerned,
we can argue that it can be handled using DT property and enable
the clock only when specified; but not until OMAP clock-tree
migration to DT.

Changes from V1:
	- Fixed spelling mistake in dts file
	- Added Acked-by from 'Paul Walmsley'

Vaibhav Hiremath (2):
  ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init
  ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output

 arch/arm/boot/dts/am335x-bone.dts     |    8 +++++++-
 arch/arm/boot/dts/am335x-evm.dts      |    8 +++++++-
 arch/arm/boot/dts/am335x-evmsk.dts    |    8 +++++++-
 arch/arm/mach-omap2/cclock33xx_data.c |    2 ++
 4 files changed, 23 insertions(+), 3 deletions(-)



From hvaibhav at ti.com  Mon May 20 09:28:09 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 20 May 2013 18:58:09 +0530
Subject: [PATCH-V2 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2 as part
 of init
In-Reply-To: <1369056490-12632-1-git-send-email-hvaibhav@ti.com>
References: <1369056490-12632-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1369056490-12632-2-git-send-email-hvaibhav@ti.com>

clkout2 comes out on the pad and is being used by various
external on-board peripherals like, Audio codecs and stuff.
So enable the clkout2 by default during init sequence itself.

Also, add the missing entry of "clkout2_ck" to the clock table.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Acked-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/cclock33xx_data.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 6fd0ed1..a8140b6 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -979,6 +979,7 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
 	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
 	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
+	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
 };


@@ -989,6 +990,7 @@ static const char *enable_init_clks[] = {
 	"l4hs_gclk",
 	"l4fw_gclk",
 	"l4ls_gclk",
+	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
 };

 int __init am33xx_clk_init(void)
--
1.7.0.4



From hvaibhav at ti.com  Mon May 20 09:28:10 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 20 May 2013 18:58:10 +0530
Subject: [PATCH-V2 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad used for
 clock output
In-Reply-To: <1369056490-12632-1-git-send-email-hvaibhav@ti.com>
References: <1369056490-12632-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1369056490-12632-3-git-send-email-hvaibhav@ti.com>

xdma_event_intr1.clkout2 pad can be used to source clock
from either 32K OSC or any of the PLL (except MPU) outputs.
On the existing AM335x based boards (EVM, EVM-SK and Bone),
this pad is used to feed the clock to audio codes.

So, this patch configures the pinmux to get clkout2 on the pad.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts  |    8 +++++++-
 arch/arm/boot/dts/am335x-evm.dts   |    8 +++++++-
 arch/arm/boot/dts/am335x-evmsk.dts |    8 +++++++-
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index bfba6fc..74bfcc6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@

 	am33xx_pinmux: pinmux at 44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <>;
+		pinctrl-0 = <&clkout2_pin>;

 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
@@ -50,6 +50,12 @@
 				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
 			>;
 		};
+
+		clkout2_pin: pinmux_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			>;
+		};
 	};

 	ocp {
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7647c9d..896d392 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,7 @@

 	am33xx_pinmux: pinmux at 44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;

 		matrix_keypad_s0: matrix_keypad_s0 {
 			pinctrl-single,pins = <
@@ -65,6 +65,12 @@
 				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
 			>;
 		};
+
+		clkout2_pin: pinmux_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			>;
+		};
 	};

 	ocp {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 0eec644..4d81dbc 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@

 	am33xx_pinmux: pinmux at 44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&gpio_keys_s0>;
+		pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;

 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
@@ -65,6 +65,12 @@
 				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
 			>;
 		};
+
+		clkout2_pin: pinmux_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			>;
+		};
 	};

 	ocp {
--
1.7.0.4



From james.hogan at imgtec.com  Mon May 20 09:28:22 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 14:28:22 +0100
Subject: [PATCH v4 0/5] clk: implement remuxing during set_rate
Message-ID: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>

This patchset adds support for automatic selection of the best parent
for a clock mux, i.e. the one which can provide the closest clock rate
to that requested. It can be disabled by a new CLK_SET_RATE_NO_REPARENT
flag (which is set for all uses of clk_register_mux().

This works by way of adding a new op, determine_rate, similar to
round_rate but with an extra parameter to allow the clock driver to
optionally select a different parent clock. This is used in
clk_calc_new_rates to decide whether to initiate a set_parent operation.

Changes in v4:

* rebased on clk-next ("clk: sun5i: Add compatibles for Allwinner A13").
* replace __clk_set_parent_no_recalc with __clk_set_parent.
* never pass NULL to determine_rate's best_parent_clk parameter, and
  slight refactor of __clk_round_rate to use local copy of clk->parent.
* a few new comments around use of clk::new_child.
* new patch (patch 2) split out of patch 3 to avoid having to declare
  static __clk_set_parent() at the top of clk.c, and to ease readability
  of patch 3.

Changes in v3:

* rebased on v3.10-rc1.
* remove double underscore prefix from clk_get_parent_by_index()
* store new_parent_index in struct clk too (calculated from
  clk_fetch_parent_index, and passed through __clk_set_parent_no_recalc
  to __clk_set_parent).
* allow determine_rate to satisfy recalc_rate check in __clk_init.
* rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
  to patch 3.
* patch 3: add CLK_SET_RATE_NO_REPARENT flag to all callers of
  clk_register_mux. If you don't mind your clocks being reparented in
  response to set_rate please let me know and I'll drop the relevant
  portion of the patch.

Changes in v2:

I've moved the mux determine_rate implementation into a core helper, but
I haven't pushed it fully into the core, as I think it just wouldn't
work correctly for more complex clocks, e.g. if you (theoretically) had
a combined mux and divide, you'd want to intercept the determine_rate
and ask for a larger rate from the parent clocks, then return the
divided rate. This should be possible by wrapping the mux determine_rate
helper.

Patch 1 still exports the __clk_get_parent_by_index as it seems like it
might be a useful thing for clock implementations to have access to if
they ever wanted to do something more fancy with changing clock parents.

I haven't made any attempt to implement the atomic set_parent+set_rate
as I don't have hardware that could take proper advantage of it, but it
shouldn't be too difficult for others to implement if they wanted since
they're fairly close to one another (in clk_change_rate()).

* switched to using new determine_rate op rather than adding an argument
  to round_rate.
* moved mux implementation into a single helper which should be usable
  from more complex clocks which can mux.
* rewrite main implementation so that no changes are made until after
  the PRE notifications have been sent, and in a way that should ensure
  correct notifications without duplicates, and I think should be safe
  in the event of a notification failing.
* various tidy ups and fixes.

James Hogan (5):
  clk: abstract parent cache
  clk: move some parent related functions upwards
  clk: add support for clock reparent on set_rate
  clk: add CLK_SET_RATE_NO_REPARENT flag
  clk: clk-mux: implement remuxing on set_rate

 Documentation/clk.txt                |   4 +
 arch/arm/mach-imx/clk.h              |   5 +-
 drivers/clk/clk-mux.c                |   1 +
 drivers/clk/clk.c                    | 416 ++++++++++++++++++++++-------------
 drivers/clk/mmp/clk-mmp2.c           |  39 ++--
 drivers/clk/mmp/clk-pxa168.c         |  40 ++--
 drivers/clk/mmp/clk-pxa910.c         |  31 ++-
 drivers/clk/mxs/clk.h                |   4 +-
 drivers/clk/samsung/clk.h            |   2 +-
 drivers/clk/spear/spear1310_clock.c  | 179 +++++++--------
 drivers/clk/spear/spear1340_clock.c  |  97 ++++----
 drivers/clk/spear/spear3xx_clock.c   |  57 +++--
 drivers/clk/spear/spear6xx_clock.c   |  35 +--
 drivers/clk/sunxi/clk-sunxi.c        |   3 +-
 drivers/clk/tegra/clk-tegra114.c     |  36 ++-
 drivers/clk/tegra/clk-tegra20.c      |   6 +-
 drivers/clk/tegra/clk-tegra30.c      |  33 ++-
 drivers/clk/versatile/clk-vexpress.c |   4 +-
 include/linux/clk-private.h          |   3 +
 include/linux/clk-provider.h         |  12 +
 20 files changed, 614 insertions(+), 393 deletions(-)

-- 
1.8.1.2




From james.hogan at imgtec.com  Mon May 20 09:28:25 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 14:28:25 +0100
Subject: [PATCH v4 3/5] clk: add support for clock reparent on set_rate
In-Reply-To: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1369056507-32521-4-git-send-email-james.hogan@imgtec.com>

Add core support to allow clock implementations to select the best
parent clock when rounding a rate, e.g. the one which can provide the
closest clock rate to that requested. This is by way of adding a new
clock op, determine_rate(), which is like round_rate() but has an extra
parameter to allow the clock implementation to optionally select a
different parent clock. The core then takes care of reparenting the
clock when setting the rate.

The parent change takes place with the help of some new private data
members. struct clk::new_parent specifies a clock's new parent (NULL
indicates no change), and struct clk::new_child specifies a clock's new
child (whose new_parent member points back to it). The purpose of these
are to allow correct walking of the future tree for notifications prior
to actually reparenting any clocks, specifically to skip child clocks
who are being reparented to another clock (they will be notified via the
new parent), and to include any new child clock. These pointers are set
by clk_calc_subtree(), and the new_child pointer gets cleared when a
child is actually reparented to avoid duplicate POST_RATE_CHANGE
notifications.

Each place where round_rate() is called, determine_rate() is checked
first and called in preference. This restructures a few of the call
sites to simplify the logic into if/else blocks.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v4:

* (not included Stephen Boyd's Reviewed-by due to changes)
* replace __clk_set_parent_no_recalc with __clk_set_parent.
* never pass NULL to determine_rate's best_parent_clk parameter, and
  slight refactor of __clk_round_rate to use local copy of clk->parent.
* a few new comments around use of clk::new_child.

Changes in v3:

* rebased on v3.10-rc1.
* store new_parent_index in struct clk too (calculated from
  clk_fetch_parent_index, and passed through __clk_set_parent_no_recalc
  to __clk_set_parent).
* allow determine_rate to satisfy recalc_rate check in __clk_init.

 Documentation/clk.txt        |   4 ++
 drivers/clk/clk.c            | 142 +++++++++++++++++++++++++++++--------------
 include/linux/clk-private.h  |   3 +
 include/linux/clk-provider.h |   7 +++
 4 files changed, 110 insertions(+), 46 deletions(-)

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index b9911c2..3110ba4 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -70,6 +70,10 @@ the operations defined in clk.h:
 						unsigned long parent_rate);
 		long		(*round_rate)(struct clk_hw *hw, unsigned long,
 						unsigned long *);
+		long		(*determine_rate)(struct clk_hw *hw,
+						unsigned long rate,
+						unsigned long *best_parent_rate,
+						struct clk **best_parent_clk);
 		int		(*set_parent)(struct clk_hw *hw, u8 index);
 		u8		(*get_parent)(struct clk_hw *hw);
 		int		(*set_rate)(struct clk_hw *hw, unsigned long);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index a4cd6bc..3ce4810 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -888,21 +888,24 @@ EXPORT_SYMBOL_GPL(clk_enable);
 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 {
 	unsigned long parent_rate = 0;
+	struct clk *parent;
 
 	if (!clk)
 		return 0;
 
-	if (!clk->ops->round_rate) {
-		if (clk->flags & CLK_SET_RATE_PARENT)
-			return __clk_round_rate(clk->parent, rate);
-		else
-			return clk->rate;
-	}
-
-	if (clk->parent)
-		parent_rate = clk->parent->rate;
-
-	return clk->ops->round_rate(clk->hw, rate, &parent_rate);
+	parent = clk->parent;
+	if (parent)
+		parent_rate = parent->rate;
+
+	if (clk->ops->determine_rate)
+		return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
+						&parent);
+	else if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk->hw, rate, &parent_rate);
+	else if (clk->flags & CLK_SET_RATE_PARENT)
+		return __clk_round_rate(clk->parent, rate);
+	else
+		return clk->rate;
 }
 
 /**
@@ -1055,6 +1058,10 @@ static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
 
 static void clk_reparent(struct clk *clk, struct clk *new_parent)
 {
+	/* avoid duplicate POST_RATE_CHANGE notifications */
+	if (new_parent->new_child == clk)
+		new_parent->new_child = NULL;
+
 	hlist_del(&clk->child_node);
 
 	if (new_parent)
@@ -1173,18 +1180,25 @@ out:
 	return ret;
 }
 
-static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
+static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
+			     struct clk *new_parent, u8 p_index)
 {
 	struct clk *child;
 
 	clk->new_rate = new_rate;
+	clk->new_parent = new_parent;
+	clk->new_parent_index = p_index;
+	/* include clk in new parent's PRE_RATE_CHANGE notifications */
+	clk->new_child = NULL;
+	if (new_parent && new_parent != clk->parent)
+		new_parent->new_child = clk;
 
 	hlist_for_each_entry(child, &clk->children, child_node) {
 		if (child->ops->recalc_rate)
 			child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
 		else
 			child->new_rate = new_rate;
-		clk_calc_subtree(child, child->new_rate);
+		clk_calc_subtree(child, child->new_rate, NULL, 0);
 	}
 }
 
@@ -1195,50 +1209,63 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
 static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
 	struct clk *top = clk;
+	struct clk *old_parent, *parent;
 	unsigned long best_parent_rate = 0;
 	unsigned long new_rate;
+	u8 p_index = 0;
 
 	/* sanity */
 	if (IS_ERR_OR_NULL(clk))
 		return NULL;
 
 	/* save parent rate, if it exists */
-	if (clk->parent)
-		best_parent_rate = clk->parent->rate;
-
-	/* never propagate up to the parent */
-	if (!(clk->flags & CLK_SET_RATE_PARENT)) {
-		if (!clk->ops->round_rate) {
-			clk->new_rate = clk->rate;
-			return NULL;
-		}
-		new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
+	parent = old_parent = clk->parent;
+	if (parent)
+		best_parent_rate = parent->rate;
+
+	/* find the closest rate and parent clk/rate */
+	if (clk->ops->determine_rate) {
+		new_rate = clk->ops->determine_rate(clk->hw, rate,
+						    &best_parent_rate,
+						    &parent);
+	} else if (clk->ops->round_rate) {
+		new_rate = clk->ops->round_rate(clk->hw, rate,
+						&best_parent_rate);
+	} else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
+		/* pass-through clock without adjustable parent */
+		clk->new_rate = clk->rate;
+		return NULL;
+	} else {
+		/* pass-through clock with adjustable parent */
+		top = clk_calc_new_rates(parent, rate);
+		new_rate = parent->new_rate;
 		goto out;
 	}
 
-	/* need clk->parent from here on out */
-	if (!clk->parent) {
-		pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
+	/* some clocks must be gated to change parent */
+	if (parent != old_parent &&
+	    (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
+		pr_debug("%s: %s not gated but wants to reparent\n",
+			 __func__, clk->name);
 		return NULL;
 	}
 
-	if (!clk->ops->round_rate) {
-		top = clk_calc_new_rates(clk->parent, rate);
-		new_rate = clk->parent->new_rate;
-
-		goto out;
+	/* try finding the new parent index */
+	if (parent) {
+		p_index = clk_fetch_parent_index(clk, parent);
+		if (p_index == clk->num_parents) {
+			pr_debug("%s: clk %s can not be parent of clk %s\n",
+				 __func__, parent->name, clk->name);
+			return NULL;
+		}
 	}
 
-	new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
-
-	if (best_parent_rate != clk->parent->rate) {
-		top = clk_calc_new_rates(clk->parent, best_parent_rate);
-
-		goto out;
-	}
+	if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
+	    best_parent_rate != parent->rate)
+		top = clk_calc_new_rates(parent, best_parent_rate);
 
 out:
-	clk_calc_subtree(clk, new_rate);
+	clk_calc_subtree(clk, new_rate, parent, p_index);
 
 	return top;
 }
@@ -1250,7 +1277,7 @@ out:
  */
 static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
 {
-	struct clk *child, *fail_clk = NULL;
+	struct clk *child, *tmp_clk, *fail_clk = NULL;
 	int ret = NOTIFY_DONE;
 
 	if (clk->rate == clk->new_rate)
@@ -1263,9 +1290,19 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
 	}
 
 	hlist_for_each_entry(child, &clk->children, child_node) {
-		clk = clk_propagate_rate_change(child, event);
-		if (clk)
-			fail_clk = clk;
+		/* Skip children who will be reparented to another clock */
+		if (child->new_parent && child->new_parent != clk)
+			continue;
+		tmp_clk = clk_propagate_rate_change(child, event);
+		if (tmp_clk)
+			fail_clk = tmp_clk;
+	}
+
+	/* handle the new child who might not be in clk->children yet */
+	if (clk->new_child) {
+		tmp_clk = clk_propagate_rate_change(clk->new_child, event);
+		if (tmp_clk)
+			fail_clk = tmp_clk;
 	}
 
 	return fail_clk;
@@ -1283,6 +1320,10 @@ static void clk_change_rate(struct clk *clk)
 
 	old_rate = clk->rate;
 
+	/* set parent */
+	if (clk->new_parent && clk->new_parent != clk->parent)
+		__clk_set_parent(clk, clk->new_parent, clk->new_parent_index);
+
 	if (clk->parent)
 		best_parent_rate = clk->parent->rate;
 
@@ -1297,8 +1338,16 @@ static void clk_change_rate(struct clk *clk)
 	if (clk->notifier_count && old_rate != clk->rate)
 		__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
 
-	hlist_for_each_entry(child, &clk->children, child_node)
+	hlist_for_each_entry(child, &clk->children, child_node) {
+		/* Skip children who will be reparented to another clock */
+		if (child->new_parent && child->new_parent != clk)
+			continue;
 		clk_change_rate(child);
+	}
+
+	/* handle the new child who might not be in clk->children yet */
+	if (clk->new_child)
+		clk_change_rate(clk->new_child);
 }
 
 /**
@@ -1545,8 +1594,9 @@ int __clk_init(struct device *dev, struct clk *clk)
 
 	/* check that clk_ops are sane.  See Documentation/clk.txt */
 	if (clk->ops->set_rate &&
-			!(clk->ops->round_rate && clk->ops->recalc_rate)) {
-		pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
+	    !((clk->ops->round_rate || clk->ops->determine_rate) &&
+	      clk->ops->recalc_rate)) {
+		pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
 				__func__, clk->name);
 		ret = -EINVAL;
 		goto out;
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index dd7adff..8138c94 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -33,8 +33,11 @@ struct clk {
 	const char		**parent_names;
 	struct clk		**parents;
 	u8			num_parents;
+	u8			new_parent_index;
 	unsigned long		rate;
 	unsigned long		new_rate;
+	struct clk		*new_parent;
+	struct clk		*new_child;
 	unsigned long		flags;
 	unsigned int		enable_count;
 	unsigned int		prepare_count;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 76b1667..24cb2ee 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -79,6 +79,10 @@ struct clk_hw;
  * @round_rate:	Given a target rate as input, returns the closest rate actually
  * 		supported by the clock.
  *
+ * @determine_rate: Given a target rate as input, returns the closest rate
+ *		actually supported by the clock, and optionally the parent clock
+ *		that should be used to provide the clock rate.
+ *
  * @get_parent:	Queries the hardware to determine the parent of a clock.  The
  * 		return value is a u8 which specifies the index corresponding to
  * 		the parent clock.  This index can be applied to either the
@@ -126,6 +130,9 @@ struct clk_ops {
 					unsigned long parent_rate);
 	long		(*round_rate)(struct clk_hw *hw, unsigned long,
 					unsigned long *);
+	long		(*determine_rate)(struct clk_hw *hw, unsigned long rate,
+					unsigned long *best_parent_rate,
+					struct clk **best_parent_clk);
 	int		(*set_parent)(struct clk_hw *hw, u8 index);
 	u8		(*get_parent)(struct clk_hw *hw);
 	int		(*set_rate)(struct clk_hw *hw, unsigned long,
-- 
1.8.1.2




From james.hogan at imgtec.com  Mon May 20 09:28:23 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 14:28:23 +0100
Subject: [PATCH v4 1/5] clk: abstract parent cache
In-Reply-To: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1369056507-32521-2-git-send-email-james.hogan@imgtec.com>

Abstract access to the clock parent cache by defining
clk_get_parent_by_index(clk, index). This allows access to parent
clocks from clock drivers.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v3:

* remove double underscore prefix from clk_get_parent_by_index()

 drivers/clk/clk.c            | 21 ++++++++++++++-------
 include/linux/clk-provider.h |  1 +
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 74e5ab2..f0ebada 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -559,6 +559,19 @@ struct clk *__clk_get_parent(struct clk *clk)
 	return !clk ? NULL : clk->parent;
 }
 
+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
+{
+	if (!clk || index >= clk->num_parents)
+		return NULL;
+	else if (!clk->parents)
+		return __clk_lookup(clk->parent_names[index]);
+	else if (!clk->parents[index])
+		return clk->parents[index] =
+			__clk_lookup(clk->parent_names[index]);
+	else
+		return clk->parents[index];
+}
+
 unsigned int __clk_get_enable_count(struct clk *clk)
 {
 	return !clk ? 0 : clk->enable_count;
@@ -1315,13 +1328,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
 			kzalloc((sizeof(struct clk*) * clk->num_parents),
 					GFP_KERNEL);
 
-	if (!clk->parents)
-		ret = __clk_lookup(clk->parent_names[index]);
-	else if (!clk->parents[index])
-		ret = clk->parents[index] =
-			__clk_lookup(clk->parent_names[index]);
-	else
-		ret = clk->parents[index];
+	ret = clk_get_parent_by_index(clk, index);
 
 out:
 	return ret;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1186098..76b1667 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -403,6 +403,7 @@ const char *__clk_get_name(struct clk *clk);
 struct clk_hw *__clk_get_hw(struct clk *clk);
 u8 __clk_get_num_parents(struct clk *clk);
 struct clk *__clk_get_parent(struct clk *clk);
+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
-- 
1.8.1.2




From james.hogan at imgtec.com  Mon May 20 09:28:27 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 14:28:27 +0100
Subject: [PATCH v4 5/5] clk: clk-mux: implement remuxing on set_rate
In-Reply-To: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1369056507-32521-6-git-send-email-james.hogan@imgtec.com>

Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't
set. This implements determine_rate for clk-mux to propagate to each
parent and to choose the best one (like clk-divider this chooses the
parent which provides the fastest rate <= the requested rate).

The determine_rate op is implemented as a core helper function so that
it can be easily used by more complex clocks which incorporate muxes.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v4:

* never pass NULL to determine_rate's best_parent_clk parameter.

Changes in v3:

* rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
  to patch 3.

 drivers/clk/clk-mux.c        |  1 +
 drivers/clk/clk.c            | 49 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h |  3 +++
 3 files changed, 53 insertions(+)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 25b1734..cecfa01 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -100,6 +100,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 const struct clk_ops clk_mux_ops = {
 	.get_parent = clk_mux_get_parent,
 	.set_parent = clk_mux_set_parent,
+	.determine_rate = __clk_mux_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 3ce4810..85b661d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -692,6 +692,55 @@ struct clk *__clk_lookup(const char *name)
 	return NULL;
 }
 
+/*
+ * Helper for finding best parent to provide a given frequency. This can be used
+ * directly as a determine_rate callback (e.g. for a mux), or from a more
+ * complex clock that may combine a mux with other operations.
+ */
+long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *best_parent_rate,
+			      struct clk **best_parent_p)
+{
+	struct clk *clk = hw->clk, *parent, *best_parent = NULL;
+	int i, num_parents;
+	unsigned long parent_rate, best = 0;
+
+	/* if NO_REPARENT flag set, pass through to current parent */
+	if (clk->flags & CLK_SET_RATE_NO_REPARENT) {
+		parent = clk->parent;
+		if (clk->flags & CLK_SET_RATE_PARENT)
+			best = __clk_round_rate(parent, rate);
+		else if (parent)
+			best = __clk_get_rate(parent);
+		else
+			best = __clk_get_rate(clk);
+		goto out;
+	}
+
+	/* find the parent that can provide the fastest rate <= rate */
+	num_parents = clk->num_parents;
+	for (i = 0; i < num_parents; i++) {
+		parent = clk_get_parent_by_index(clk, i);
+		if (!parent)
+			continue;
+		if (clk->flags & CLK_SET_RATE_PARENT)
+			parent_rate = __clk_round_rate(parent, rate);
+		else
+			parent_rate = __clk_get_rate(parent);
+		if (parent_rate <= rate && parent_rate > best) {
+			best_parent = parent;
+			best = parent_rate;
+		}
+	}
+
+out:
+	if (best_parent)
+		*best_parent_p = best_parent;
+	*best_parent_rate = best;
+
+	return best;
+}
+
 /***        clk api        ***/
 
 void __clk_unprepare(struct clk *clk)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index bb2d812..d6057eb 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -419,6 +419,9 @@ unsigned long __clk_get_flags(struct clk *clk);
 bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
+long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *best_parent_rate,
+			      struct clk **best_parent_p);
 
 /*
  * FIXME clock api without lock protection
-- 
1.8.1.2




From james.hogan at imgtec.com  Mon May 20 09:28:24 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 14:28:24 +0100
Subject: [PATCH v4 2/5] clk: move some parent related functions upwards
In-Reply-To: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1369056507-32521-3-git-send-email-james.hogan@imgtec.com>

Move some parent related functions up in clk.c so they can be used by
the modifications in the following patch which enables clock reparenting
during set_rate. No other changes are made so this patch makes no
functional difference in isolation. This is separate from the following
patch primarily to ease readability of that patch.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
---
Changes in v4:

* new patch (patch 2) split out of patch 3 to avoid having to declare
  static __clk_set_parent() at the top of clk.c, and to ease readability
  of patch 3.

 drivers/clk/clk.c | 220 +++++++++++++++++++++++++++---------------------------
 1 file changed, 110 insertions(+), 110 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f0ebada..a4cd6bc 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1027,6 +1027,108 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(clk_get_rate);
 
+static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
+{
+	u8 i;
+
+	if (!clk->parents)
+		clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
+								GFP_KERNEL);
+
+	/*
+	 * find index of new parent clock using cached parent ptrs,
+	 * or if not yet cached, use string name comparison and cache
+	 * them now to avoid future calls to __clk_lookup.
+	 */
+	for (i = 0; i < clk->num_parents; i++) {
+		if (clk->parents && clk->parents[i] == parent)
+			break;
+		else if (!strcmp(clk->parent_names[i], parent->name)) {
+			if (clk->parents)
+				clk->parents[i] = __clk_lookup(parent->name);
+			break;
+		}
+	}
+
+	return i;
+}
+
+static void clk_reparent(struct clk *clk, struct clk *new_parent)
+{
+	hlist_del(&clk->child_node);
+
+	if (new_parent)
+		hlist_add_head(&clk->child_node, &new_parent->children);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+	clk->parent = new_parent;
+}
+
+static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
+{
+	unsigned long flags;
+	int ret = 0;
+	struct clk *old_parent = clk->parent;
+
+	/*
+	 * Migrate prepare state between parents and prevent race with
+	 * clk_enable().
+	 *
+	 * If the clock is not prepared, then a race with
+	 * clk_enable/disable() is impossible since we already have the
+	 * prepare lock (future calls to clk_enable() need to be preceded by
+	 * a clk_prepare()).
+	 *
+	 * If the clock is prepared, migrate the prepared state to the new
+	 * parent and also protect against a race with clk_enable() by
+	 * forcing the clock and the new parent on.  This ensures that all
+	 * future calls to clk_enable() are practically NOPs with respect to
+	 * hardware and software states.
+	 */
+	if (clk->prepare_count) {
+		__clk_prepare(parent);
+		clk_enable(parent);
+		clk_enable(clk);
+	}
+
+	/* update the clk tree topology */
+	flags = clk_enable_lock();
+	clk_reparent(clk, parent);
+	clk_enable_unlock(flags);
+
+	/* change clock input source */
+	if (parent && clk->ops->set_parent)
+		ret = clk->ops->set_parent(clk->hw, p_index);
+
+	if (ret) {
+		flags = clk_enable_lock();
+		clk_reparent(clk, old_parent);
+		clk_enable_unlock(flags);
+
+		if (clk->prepare_count) {
+			clk_disable(clk);
+			clk_disable(parent);
+			__clk_unprepare(parent);
+		}
+		return ret;
+	}
+
+	/*
+	 * Finish the migration of prepare state and undo the changes done
+	 * for preventing a race with clk_enable().
+	 */
+	if (clk->prepare_count) {
+		clk_disable(clk);
+		clk_disable(old_parent);
+		__clk_unprepare(old_parent);
+	}
+
+	/* update debugfs with new clk tree topology */
+	clk_debug_reparent(clk, parent);
+	return 0;
+}
+
 /**
  * __clk_speculate_rates
  * @clk: first clk in the subtree
@@ -1334,18 +1436,6 @@ out:
 	return ret;
 }
 
-static void clk_reparent(struct clk *clk, struct clk *new_parent)
-{
-	hlist_del(&clk->child_node);
-
-	if (new_parent)
-		hlist_add_head(&clk->child_node, &new_parent->children);
-	else
-		hlist_add_head(&clk->child_node, &clk_orphan_list);
-
-	clk->parent = new_parent;
-}
-
 void __clk_reparent(struct clk *clk, struct clk *new_parent)
 {
 	clk_reparent(clk, new_parent);
@@ -1353,96 +1443,6 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
 	__clk_recalc_rates(clk, POST_RATE_CHANGE);
 }
 
-static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
-{
-	u8 i;
-
-	if (!clk->parents)
-		clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
-								GFP_KERNEL);
-
-	/*
-	 * find index of new parent clock using cached parent ptrs,
-	 * or if not yet cached, use string name comparison and cache
-	 * them now to avoid future calls to __clk_lookup.
-	 */
-	for (i = 0; i < clk->num_parents; i++) {
-		if (clk->parents && clk->parents[i] == parent)
-			break;
-		else if (!strcmp(clk->parent_names[i], parent->name)) {
-			if (clk->parents)
-				clk->parents[i] = __clk_lookup(parent->name);
-			break;
-		}
-	}
-
-	return i;
-}
-
-static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
-{
-	unsigned long flags;
-	int ret = 0;
-	struct clk *old_parent = clk->parent;
-
-	/*
-	 * Migrate prepare state between parents and prevent race with
-	 * clk_enable().
-	 *
-	 * If the clock is not prepared, then a race with
-	 * clk_enable/disable() is impossible since we already have the
-	 * prepare lock (future calls to clk_enable() need to be preceded by
-	 * a clk_prepare()).
-	 *
-	 * If the clock is prepared, migrate the prepared state to the new
-	 * parent and also protect against a race with clk_enable() by
-	 * forcing the clock and the new parent on.  This ensures that all
-	 * future calls to clk_enable() are practically NOPs with respect to
-	 * hardware and software states.
-	 */
-	if (clk->prepare_count) {
-		__clk_prepare(parent);
-		clk_enable(parent);
-		clk_enable(clk);
-	}
-
-	/* update the clk tree topology */
-	flags = clk_enable_lock();
-	clk_reparent(clk, parent);
-	clk_enable_unlock(flags);
-
-	/* change clock input source */
-	if (parent && clk->ops->set_parent)
-		ret = clk->ops->set_parent(clk->hw, p_index);
-
-	if (ret) {
-		flags = clk_enable_lock();
-		clk_reparent(clk, old_parent);
-		clk_enable_unlock(flags);
-
-		if (clk->prepare_count) {
-			clk_disable(clk);
-			clk_disable(parent);
-			__clk_unprepare(parent);
-		}
-		return ret;
-	}
-
-	/*
-	 * Finish the migration of prepare state and undo the changes done
-	 * for preventing a race with clk_enable().
-	 */
-	if (clk->prepare_count) {
-		clk_disable(clk);
-		clk_disable(old_parent);
-		__clk_unprepare(old_parent);
-	}
-
-	/* update debugfs with new clk tree topology */
-	clk_debug_reparent(clk, parent);
-	return 0;
-}
-
 /**
  * clk_set_parent - switch the parent of a mux clk
  * @clk: the mux clk whose input we are switching
-- 
1.8.1.2




From james.hogan at imgtec.com  Mon May 20 09:28:26 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Mon, 20 May 2013 14:28:26 +0100
Subject: [PATCH v4 4/5] clk: add CLK_SET_RATE_NO_REPARENT flag
In-Reply-To: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <1369056507-32521-5-git-send-email-james.hogan@imgtec.com>

Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan <james.hogan at imgtec.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Viresh Kumar <viresh.linux at gmail.com>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Chao Xie <xiechao.mail at gmail.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: "Emilio L?pez" <emilio at elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad at nvidia.com>
Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Joseph Lo <josephl at nvidia.com>
Cc: Peter De Schrijver <pdeschrijver at nvidia.com>
Cc: Pawel Moll <pawel.moll at arm.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: spear-devel at list.st.com
Cc: linux-tegra at vger.kernel.org
---
Changes in v3:

* rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
  to this new patch.
* patch 3: add CLK_SET_RATE_NO_REPARENT flag to all callers of
  clk_register_mux. If you don't mind your clocks being reparented in
  response to set_rate please let me know and I'll drop the relevant
  portion of the patch.

 arch/arm/mach-imx/clk.h              |   5 +-
 drivers/clk/mmp/clk-mmp2.c           |  39 +++++---
 drivers/clk/mmp/clk-pxa168.c         |  40 +++++---
 drivers/clk/mmp/clk-pxa910.c         |  31 +++---
 drivers/clk/mxs/clk.h                |   4 +-
 drivers/clk/samsung/clk.h            |   2 +-
 drivers/clk/spear/spear1310_clock.c  | 179 ++++++++++++++++++-----------------
 drivers/clk/spear/spear1340_clock.c  |  97 ++++++++++---------
 drivers/clk/spear/spear3xx_clock.c   |  57 +++++++----
 drivers/clk/spear/spear6xx_clock.c   |  35 +++----
 drivers/clk/sunxi/clk-sunxi.c        |   3 +-
 drivers/clk/tegra/clk-tegra114.c     |  36 ++++---
 drivers/clk/tegra/clk-tegra20.c      |   6 +-
 drivers/clk/tegra/clk-tegra30.c      |  33 ++++---
 drivers/clk/versatile/clk-vexpress.c |   4 +-
 include/linux/clk-provider.h         |   1 +
 16 files changed, 334 insertions(+), 238 deletions(-)

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c..244db2b 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -77,7 +77,8 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
+	return clk_register_mux(NULL, name, parents, num_parents,
+			CLK_SET_RATE_NO_REPARENT, reg, shift,
 			width, 0, &imx_ccm_lock);
 }
 
@@ -86,7 +87,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
 		int num_parents, unsigned long flags)
 {
 	return clk_register_mux(NULL, name, parents, num_parents,
-			flags, reg, shift, width, 0,
+			flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
 			&imx_ccm_lock);
 }
 
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index d1f1a19..b2721ca 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -248,7 +248,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
 
 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -258,7 +259,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 
 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -268,7 +270,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 
 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -278,7 +281,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 
 	clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, vctcxo);
 	clk_register_clkdev(clk, "uart_mux.3", NULL);
@@ -288,7 +292,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
 
 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
 
@@ -297,7 +302,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 
 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
 
@@ -306,7 +312,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 
 	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.2", NULL);
 
@@ -315,7 +322,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 
 	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.3", NULL);
 
@@ -324,7 +332,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 
 	clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh_mux", NULL);
 
@@ -354,7 +363,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "usb_clk", NULL);
 
 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.0", NULL);
 
@@ -376,7 +386,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "disp_sphy.0", NULL);
 
 	clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.1", NULL);
 
@@ -394,7 +405,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "ccic_arbiter", NULL);
 
 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
 
@@ -421,7 +433,8 @@ void __init mmp2_clk_init(void)
 	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
 
 	clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.1", NULL);
 
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 28b3b51..014396b 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -199,7 +199,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
 
 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -209,7 +210,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 
 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -219,7 +221,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 
 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -229,7 +232,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 
 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
 
@@ -238,7 +242,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 
 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
 
@@ -247,7 +252,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 
 	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.2", NULL);
 
@@ -256,7 +262,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 
 	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.3", NULL);
 
@@ -265,7 +272,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 
 	clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.4", NULL);
 
@@ -278,7 +286,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
 
 	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh0_mux", NULL);
 
@@ -287,7 +296,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
 
 	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh1_mux", NULL);
 
@@ -304,7 +314,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, "sph_clk", NULL);
 
 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.0", NULL);
 
@@ -317,7 +328,8 @@ void __init pxa168_clk_init(void)
 	clk_register_clkdev(clk, "hclk", "mmp-disp.0");
 
 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
 
@@ -327,8 +339,8 @@ void __init pxa168_clk_init(void)
 
 	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
 				ARRAY_SIZE(ccic_phy_parent),
-				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
-				7, 1, 0, &clk_lock);
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
 
 	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 6ec0569..9efc6a4 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -204,7 +204,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
 
 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -214,7 +215,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 
 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -224,7 +226,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 
 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
-				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(uart_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
 	clk_set_parent(clk, uart_pll);
 	clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -234,7 +237,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 
 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "uart_mux.0", NULL);
 
@@ -243,7 +247,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 
 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
-				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ssp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
 
@@ -256,7 +261,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
 
 	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh0_mux", NULL);
 
@@ -265,7 +271,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
 
 	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
-				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(sdh_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "sdh1_mux", NULL);
 
@@ -282,7 +289,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, "sph_clk", NULL);
 
 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
-				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(disp_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "disp_mux.0", NULL);
 
@@ -291,7 +299,8 @@ void __init pxa910_clk_init(void)
 	clk_register_clkdev(clk, NULL, "mmp-disp.0");
 
 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
-				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				ARRAY_SIZE(ccic_parent),
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
 
@@ -301,8 +310,8 @@ void __init pxa910_clk_init(void)
 
 	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
 				ARRAY_SIZE(ccic_phy_parent),
-				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
-				7, 1, 0, &clk_lock);
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
 	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
 
 	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 81421e2..ef10ad9 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -52,8 +52,8 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parent_names, int num_parents)
 {
 	return clk_register_mux(NULL, name, parent_names, num_parents,
-				CLK_SET_RATE_PARENT, reg, shift, width,
-				0, &mxs_lock);
+				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+				reg, shift, width, 0, &mxs_lock);
 }
 
 static inline struct clk *mxs_clk_fixed_factor(const char *name,
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index e4ad6ea..eb672ba 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -127,7 +127,7 @@ struct samsung_mux_clock {
 		.name		= cname,			\
 		.parent_names	= pnames,			\
 		.num_parents	= ARRAY_SIZE(pnames),		\
-		.flags		= f,				\
+		.flags		= (f) | CLK_SET_RATE_NO_REPARENT, \
 		.offset		= o,				\
 		.shift		= s,				\
 		.width		= w,				\
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index aedbbe1..65894f7 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -416,9 +416,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	/* clock derived from 24 or 25 MHz osc clk */
 	/* vco-pll */
 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
-			SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
+			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco1_mclk", NULL);
 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
 			0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
@@ -427,9 +427,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "pll1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
-			SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
+			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco2_mclk", NULL);
 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
 			0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
@@ -438,9 +438,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "pll2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
-			SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
+			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco3_mclk", NULL);
 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
 			0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
@@ -515,9 +515,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* gpt clocks */
 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
@@ -525,9 +525,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
@@ -535,9 +535,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "gpt1");
 
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
@@ -545,9 +545,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "gpt2");
 
 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
-			SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
+			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
@@ -562,7 +562,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
-			ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uart0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
 			SPEAR1310_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -602,7 +603,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
-			ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(c3_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
 			SPEAR1310_C3_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -614,8 +616,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* gmac */
 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
-			ARRAY_SIZE(gmac_phy_input_parents), 0,
-			SPEAR1310_GMAC_CLK_CFG,
+			ARRAY_SIZE(gmac_phy_input_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
 			SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 			SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -627,15 +629,16 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
-			ARRAY_SIZE(gmac_phy_parents), 0,
+			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 			SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
-			ARRAY_SIZE(clcd_synth_parents), 0,
-			SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
+			ARRAY_SIZE(clcd_synth_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
+			SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 			SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 
@@ -645,7 +648,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
-			ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(clcd_pixel_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 			SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -657,9 +661,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* i2s */
 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
-			ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
-			SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
+			SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 
 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
@@ -668,7 +672,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
-			ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(i2s_ref_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
 			SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -806,13 +811,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	/* RAS clks */
 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
-			ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
+			ARRAY_SIZE(gen_synth0_1_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
 			SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 			SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
-			ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
+			ARRAY_SIZE(gen_synth2_3_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
 			SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 			SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
@@ -929,8 +936,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 
 	clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
 			smii_rgmii_phy_parents,
-			ARRAY_SIZE(smii_rgmii_phy_parents), 0,
-			SPEAR1310_RAS_CTRL_REG1,
+			ARRAY_SIZE(smii_rgmii_phy_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
 			SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.1", NULL);
@@ -938,15 +945,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, "stmmacphy.4", NULL);
 
 	clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
-			ARRAY_SIZE(rmii_phy_parents), 0,
+			ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
 			SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.3", NULL);
 
 	clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -955,9 +962,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5c800000.serial");
 
 	clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
@@ -966,9 +973,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5c900000.serial");
 
 	clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart3_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
@@ -977,9 +984,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5ca00000.serial");
 
 	clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart4_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
@@ -988,9 +995,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cb00000.serial");
 
 	clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
+			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart5_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
@@ -999,9 +1006,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cc00000.serial");
 
 	clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
@@ -1010,9 +1017,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cd00000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
@@ -1021,9 +1028,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5ce00000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c3_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
@@ -1032,9 +1039,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5cf00000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c4_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
@@ -1043,9 +1050,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d000000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c5_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
@@ -1054,9 +1061,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d100000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c6_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
@@ -1065,9 +1072,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d200000.i2c");
 
 	clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
-			ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
+			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2c7_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
@@ -1076,9 +1083,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d300000.i2c");
 
 	clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
-			ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
+			SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ssp1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
@@ -1087,9 +1094,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "5d400000.spi");
 
 	clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
-			ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
+			SPEAR1310_PCI_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "pci_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
@@ -1098,9 +1105,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "pci");
 
 	clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
-			ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
+			SPEAR1310_TDM_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "tdm1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
@@ -1109,9 +1116,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
 
 	clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
-			ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
-			SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
+			SPEAR1310_TDM_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "tdm2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 9d0b394..fe835c1 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -473,9 +473,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	/* clock derived from 24 or 25 MHz osc clk */
 	/* vco-pll */
 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
-			SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
+			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco1_mclk", NULL);
 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
 			SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
@@ -484,9 +484,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "pll1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
-			SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
+			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco2_mclk", NULL);
 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
 			SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
@@ -495,9 +495,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "pll2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
-			ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
-			SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
+			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "vco3_mclk", NULL);
 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
 			SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
@@ -561,8 +561,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "amba_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
-			ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
-			SPEAR1340_SCLK_SRC_SEL_SHIFT,
+			ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
 			SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "sys_mclk", NULL);
 
@@ -583,8 +583,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "smp_twd");
 
 	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
-			ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
-			SPEAR1340_HCLK_SRC_SEL_SHIFT,
+			ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
 			SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ahb_clk", NULL);
 
@@ -594,9 +594,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* gpt clocks */
 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
@@ -604,9 +604,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
@@ -614,9 +614,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "gpt1");
 
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
@@ -624,9 +624,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "gpt2");
 
 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
-			ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
+			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
@@ -641,7 +641,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
-			ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uart0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
 			SPEAR1340_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -658,9 +659,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
-			ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
-			SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
+			SPEAR1340_UART_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "uart1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -698,7 +699,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
-			ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(c3_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
 			SPEAR1340_C3_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -710,8 +712,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* gmac */
 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
-			ARRAY_SIZE(gmac_phy_input_parents), 0,
-			SPEAR1340_GMAC_CLK_CFG,
+			ARRAY_SIZE(gmac_phy_input_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
 			SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
 			SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -723,15 +725,16 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
-			ARRAY_SIZE(gmac_phy_parents), 0,
+			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
 			SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
-			ARRAY_SIZE(clcd_synth_parents), 0,
-			SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
+			ARRAY_SIZE(clcd_synth_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
+			SPEAR1340_CLCD_SYNT_CLK_SHIFT,
 			SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 
@@ -741,7 +744,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
-			ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(clcd_pixel_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
 			SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -753,9 +757,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* i2s */
 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
-			ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
-			SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
-			0, &_lock);
+			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
+			SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 
 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
@@ -765,7 +769,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 
 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
-			ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(i2s_ref_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
 			SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -891,13 +896,15 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 
 	/* RAS clks */
 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
-			ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG,
+			ARRAY_SIZE(gen_synth0_1_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
 			SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
 
 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
-			ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG,
+			ARRAY_SIZE(gen_synth2_3_parents),
+			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
 			SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
@@ -938,7 +945,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "spear_cec.1");
 
 	clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
-			ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(spdif_out_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "spdif_out_mclk", NULL);
@@ -949,7 +957,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
 
 	clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
-			ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(spdif_in_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "spdif_in_mclk", NULL);
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index f9ec43f..4e3bb9e 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -294,7 +294,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
 	clk_register_clkdev(clk, NULL, "a9400000.i2s");
 
 	clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
-			ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(i2s_ref_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
 			I2S_REF_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "i2s_ref_clk", NULL);
@@ -313,57 +314,66 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
 	clk_register_clkdev(clk, "hclk", "ab000000.eth");
 
 	clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a9300000.serial");
 
 	clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
-			ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(sdhci_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "70000000.sdhci");
 
 	clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
-			ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
-			SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
+			ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
+			SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
+			0, &_lock);
 	clk_register_clkdev(clk, NULL, "smii_pclk");
 
 	clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
 	clk_register_clkdev(clk, NULL, "smii");
 
 	clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "a3000000.serial");
 
 	clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a4000000.serial");
 
 	clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a9100000.serial");
 
 	clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a9200000.serial");
 
 	clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "60000000.serial");
 
 	clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
-			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uartx_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "60100000.serial");
@@ -427,7 +437,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
-			ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(uart0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
 			&_lock);
 	clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -444,7 +455,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
-			ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(firda_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
 			&_lock);
 	clk_register_clkdev(clk, "firda_mclk", NULL);
@@ -458,14 +470,16 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
 			ARRAY_SIZE(gpt_rtbl), &_lock);
 	clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
-			ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(gpt0_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
 			ARRAY_SIZE(gpt_rtbl), &_lock);
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
-			ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(gpt1_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
@@ -476,7 +490,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
 			ARRAY_SIZE(gpt_rtbl), &_lock);
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
-			ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
+			ARRAY_SIZE(gpt2_parents),
+			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
@@ -498,9 +513,9 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
-			ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
-			GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
-			&_lock);
+			ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
+			CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
+			GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
 
 	clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
@@ -540,8 +555,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
 	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
-			ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
-			MCTR_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
+			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ddr_clk", NULL);
 
 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index 9406f24..4f649c9 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -169,8 +169,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
-			ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
-			UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
+			&_lock);
 	clk_register_clkdev(clk, "uart_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
@@ -188,8 +189,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
-			ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
-			FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
+			&_lock);
 	clk_register_clkdev(clk, "firda_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
@@ -203,8 +205,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
 
 	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
-			ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
-			CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
+			&_lock);
 	clk_register_clkdev(clk, "clcd_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
@@ -217,13 +220,13 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
-			ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
-			GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "gpt0");
 
 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
-			ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
-			GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
@@ -235,8 +238,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
-			ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
-			GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
@@ -248,8 +251,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
 
 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
-			ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
-			GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
+			PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
@@ -277,8 +280,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 
 	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
-			ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
-			MCTR_CLK_MASK, 0, &_lock);
+			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
+			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, "ddr_clk", NULL);
 
 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 930d36f..f47df26 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -261,7 +261,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
 	while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 		i++;
 
-	clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg,
+	clk = clk_register_mux(NULL, clk_name, parents, i,
+			       CLK_SET_RATE_NO_REPARENT, reg,
 			       data->shift, SUNXI_MUX_GATE_WIDTH,
 			       0, &clk_lock);
 
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..21aa7bb 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1435,7 +1435,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio0 */
 	clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
 			       NULL);
 	clks[audio0_mux] = clk;
@@ -1447,7 +1448,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio1 */
 	clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
 			       NULL);
 	clks[audio1_mux] = clk;
@@ -1459,7 +1461,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio2 */
 	clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
 			       NULL);
 	clks[audio2_mux] = clk;
@@ -1471,7 +1474,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio3 */
 	clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
 			       NULL);
 	clks[audio3_mux] = clk;
@@ -1483,7 +1487,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* audio4 */
 	clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
 			       NULL);
 	clks[audio4_mux] = clk;
@@ -1495,7 +1500,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
 
 	/* spdif */
 	clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
-			       ARRAY_SIZE(mux_audio_sync_clk), 0,
+			       ARRAY_SIZE(mux_audio_sync_clk),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
 			       NULL);
 	clks[spdif_mux] = clk;
@@ -1590,7 +1596,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_1 */
 	clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_1_mux] = clk;
@@ -1602,7 +1609,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_2 */
 	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_2_mux] = clk;
@@ -1614,7 +1622,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_3 */
 	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_3_mux] = clk;
@@ -1928,7 +1937,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 
 	/* dsia */
 	clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
-			       ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+			       ARRAY_SIZE(mux_plld_out0_plld2_out0),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
 	clks[dsia_mux] = clk;
 	clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
@@ -1938,7 +1948,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 
 	/* dsib */
 	clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
-			       ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+			       ARRAY_SIZE(mux_plld_out0_plld2_out0),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
 	clks[dsib_mux] = clk;
 	clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
@@ -1975,7 +1986,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm), 0,
+			       ARRAY_SIZE(mux_pllmcp_clkm),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       29, 3, 0, NULL);
 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 8292a00..48868deb 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -778,7 +778,8 @@ static void __init tegra20_audio_clk_init(void)
 
 	/* audio */
 	clk = clk_register_mux(NULL, "audio_mux", audio_parents,
-				ARRAY_SIZE(audio_parents), 0,
+				ARRAY_SIZE(audio_parents),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
 				clk_base + AUDIO_SYNC_CLK, 4,
@@ -933,7 +934,8 @@ static void __init tegra20_periph_clk_init(void)
 
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm), 0,
+			       ARRAY_SIZE(mux_pllmcp_clkm),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       30, 2, 0, NULL);
 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c6921f5..b4abfa5 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1008,7 +1008,8 @@ static void __init tegra30_pll_init(void)
 
 	/* PLLE */
 	clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
-			       ARRAY_SIZE(pll_e_parents), 0,
+			       ARRAY_SIZE(pll_e_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + PLLE_AUX, 2, 1, 0, NULL);
 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
 			     CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
@@ -1068,7 +1069,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio0 */
 	clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S0, 4,
@@ -1078,7 +1080,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio1 */
 	clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S1, 4,
@@ -1088,7 +1091,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio2 */
 	clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S2, 4,
@@ -1098,7 +1102,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio3 */
 	clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S3, 4,
@@ -1108,7 +1113,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* audio4 */
 	clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_I2S4, 4,
@@ -1118,7 +1124,8 @@ static void __init tegra30_audio_clk_init(void)
 
 	/* spdif */
 	clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
-				ARRAY_SIZE(mux_audio_sync_clk), 0,
+				ARRAY_SIZE(mux_audio_sync_clk),
+				CLK_SET_RATE_NO_REPARENT,
 				clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
 	clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
 				clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
@@ -1211,7 +1218,8 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_1 */
 	clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_1_mux] = clk;
@@ -1223,7 +1231,8 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_2 */
 	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
 			       &clk_out_lock);
 	clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1234,7 +1243,8 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_3 */
 	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out1_parents),
+			       CLK_SET_RATE_NO_REPARENT,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
 			       &clk_out_lock);
 	clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
@@ -1655,7 +1665,8 @@ static void __init tegra30_periph_clk_init(void)
 
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm), 0,
+			       ARRAY_SIZE(mux_pllmcp_clkm),
+			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       30, 2, 0, NULL);
 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
index a4a728d..2d5e1b4 100644
--- a/drivers/clk/versatile/clk-vexpress.c
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -37,8 +37,8 @@ static void __init vexpress_sp810_init(void __iomem *base)
 		snprintf(name, ARRAY_SIZE(name), "timerclken%d", i);
 
 		vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name,
-				parents, 2, 0, base + SCCTRL,
-				SCCTRL_TIMERENnSEL_SHIFT(i), 1,
+				parents, 2, CLK_SET_RATE_NO_REPARENT,
+				base + SCCTRL, SCCTRL_TIMERENnSEL_SHIFT(i), 1,
 				0, &vexpress_sp810_lock);
 
 		if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i])))
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 24cb2ee..bb2d812 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -27,6 +27,7 @@
 #define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
 #define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
+#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
 
 struct clk_hw;
 
-- 
1.8.1.2




From alexdeucher at gmail.com  Mon May 20 09:36:02 2013
From: alexdeucher at gmail.com (Alex Deucher)
Date: Mon, 20 May 2013 09:36:02 -0400
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130519085920.GO18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
 <20130519085920.GO18614@n2100.arm.linux.org.uk>
Message-ID: <CADnq5_Pajy4jxLdd9QGBrUooWYFjfQRQgdbvbu9UDE8-7Tmm8g@mail.gmail.com>

On Sun, May 19, 2013 at 4:59 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Fri, May 17, 2013 at 07:40:23PM +0200, Jean-Francois Moine wrote:
>> Maybe I did not explain correctly: the colored cursor maybe RGB888 +
>> transparency (64x64) or full ARGB (64x32 or 32x64). I coded the first
>> case. And, yes, I better like a hardware cursor: it asks for less
>> computation, and I get it immediately at graphic starting time!
>
> Having looked at this now, using the RGB+transparency is less than ideal
> because we're having to reduce an alpha channel down to a simple on/off
> transparency.  X cursors really are alphablended components!
>
> So, the options here are:
> (a) use "software" rendered cursor
>     + correct and expected cursor size
>     + correct rendering
>     + possible to use the GPU (I believe mine does)
>     - maybe time consuming as it has to be removed/replaced on the screen
> (b) use RGB+transparency for 64x64 hardware cursor
>     + correct and expected cursor size
>     + does not have to be removed/replaced when screen contents change
>     - incorrect rendering due to reducing the alpha channel to a simple
>       on/off transparency mask
>     - has to be reloaded when the pointer is close to the edges of the
>       screen which is CPU intensive
>     - cursor image data passed into DRM is required to be ARGB (I've
>       discussed this with David Airlie last night.)  This means we have
>       to do translation to RGB+T in the kernel which is *not* nice.
> (c) use ARGB 32x64 or 64x32 hardware cursor
>     + does not have to be removed/replaced when screen contents change
>     + correct rendering of cursor
>     - unexpected cursor size; user clients do not expect to be restricted
>       to 32 rows or 32 lines of cursor
>     - can only select maximum cursor size on initialization of hardware
>       cursor; can't dynamically switch between 32x64 and 64x32 sizes
>     - has to be reloaded when the pointer is close to the edges of the
>       screen which is CPU intensive

You can tell the xserver what size cursor you support when you call
xf86_cursors_init() in the ddx.  Just expose a 32x64 or 64x32 ARGB
cursor.  Most apps don't use a 64x64 cursor anyway.  I've used
hardware with non-64x64 cursors and haven't run into any problems yet.

Alex


From hvaibhav at ti.com  Mon May 20 09:38:36 2013
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 20 May 2013 19:08:36 +0530
Subject: [PATCH-V2] ARM: OMAP2+: AM33xx: Fix missing reset status data to GFX
 hwmod
Message-ID: <1369057116-31423-1-git-send-email-hvaibhav@ti.com>

GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
so update the GFX hwmod data with .rstst_off and .st_shift
information.

Although it doesn't have impact on kernel boot, but this is
regression fix from original hwmod commit.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Tony Lindgren <tony at atomide.com>
---
Changes from V1 (No code change):
	- Updated commit description to mention its regression
	  from original commit.

 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index d1cf3ab..38c7b04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 };

 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-	{ .name = "gfx", .rst_shift = 0 },
+	{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
 };

 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
 			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
+			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
--
1.7.0.4



From kgene.kim at samsung.com  Mon May 20 09:47:59 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 20 May 2013 22:47:59 +0900
Subject: [PATCH 07/18] cpufreq: s3c24xx: move cpufreq driver to
 drivers/cpufreq
In-Reply-To: <CAKohpon97dbLDF0xU7vhf5V+UVeJv7WdeMuZ1jXLUTey2+gD2A@mail.gmail.com>
References: <cover.1365079581.git.viresh.kumar@linaro.org>	<CAKohponkFB7ND38jv5oGnQLx8cq0b=uHTCmL3EERe6P54ijYhw@mail.gmail.com>	<093901ce509f$afe92f40$0fbb8dc0$%kim@samsung.com>	<2001452.Fn2HjLbNED@vostro.rjw.lan>
 <CAKohpon97dbLDF0xU7vhf5V+UVeJv7WdeMuZ1jXLUTey2+gD2A@mail.gmail.com>
Message-ID: <519A298F.2040605@samsung.com>

On 05/20/13 14:29, Viresh Kumar wrote:

[...]

>>> Rafael, if you don't mind, let me take this into Samsung tree for v3.11.
>>
>> Sure, please go ahead.
>
> Kukjin,
>
> I hope you have already applied this for linux-next?

Yeah, already done in my local and you can see it in my public tree in a 
couple of hours :-)

Thanks.

- Kukjin


From linux at arm.linux.org.uk  Mon May 20 09:53:21 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 May 2013 14:53:21 +0100
Subject: [RFC PATCH 2/6] ARM: imx: use the core cpu hotplug functions
In-Reply-To: <1369031608-27347-3-git-send-email-sanjay.rawat@linaro.org>
References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org>
 <1369031608-27347-3-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <20130520135321.GW18614@n2100.arm.linux.org.uk>

Please read back on this list for my comments about such moves of this
very code.  You're not the first.

On Mon, May 20, 2013 at 12:03:24PM +0530, Sanjay Singh Rawat wrote:
> Generic arm cpu hotplug related functions are moved to core hotplug code,
> remove the functions from the platform code.
> 
> Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
> ---
>  arch/arm/mach-imx/hotplug.c |   22 +---------------------
>  1 file changed, 1 insertion(+), 21 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
> index 3daf1ed..280c6f3 100644
> --- a/arch/arm/mach-imx/hotplug.c
> +++ b/arch/arm/mach-imx/hotplug.c
> @@ -14,30 +14,10 @@
>  #include <linux/jiffies.h>
>  #include <asm/cp15.h>
>  #include <asm/proc-fns.h>
> +#include <asm/hotplug.h>
>  
>  #include "common.h"
>  
> -static inline void cpu_enter_lowpower(void)
> -{
> -	unsigned int v;
> -
> -	asm volatile(
> -		"mcr	p15, 0, %1, c7, c5, 0\n"
> -	"	mcr	p15, 0, %1, c7, c10, 4\n"
> -	/*
> -	 * Turn off coherency
> -	 */
> -	"	mrc	p15, 0, %0, c1, c0, 1\n"
> -	"	bic	%0, %0, %3\n"
> -	"	mcr	p15, 0, %0, c1, c0, 1\n"
> -	"	mrc	p15, 0, %0, c1, c0, 0\n"
> -	"	bic	%0, %0, %2\n"
> -	"	mcr	p15, 0, %0, c1, c0, 0\n"
> -	  : "=&r" (v)
> -	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
> -	  : "cc");
> -}
> -
>  /*
>   * platform-specific code to shutdown a CPU
>   *
> -- 
> 1.7.9.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From fabio.estevam at freescale.com  Mon May 20 09:59:57 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 20 May 2013 10:59:57 -0300
Subject: [PATCH] ARM: imx: imx_v6_v7_defconfig: Select CONFIG_DRM_IMX_TVE
Message-ID: <1369058397-25071-1-git-send-email-fabio.estevam@freescale.com>

Let the mx53 TVE driver be built by default.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/imx_v6_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f..a50d9af 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -208,6 +208,7 @@ CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
+CONFIG_DRM_IMX_TVE=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
-- 
1.8.1.2




From gregory.clement at free-electrons.com  Mon May 20 10:13:27 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 20 May 2013 16:13:27 +0200
Subject: [PATCH] ARM: dts: mvebu: Fix wrong the address reg value for the
 L2-cache node
Message-ID: <1369059207-32210-1-git-send-email-gregory.clement@free-electrons.com>

During the conversion to the internal-regs' subnode, the L2-cache node
haven not been converted (due to a wrong choice made by myself during
the resolution of the merge conflict when I rebased the commit). This
leads to wrong address for L2 cache which prevent it to be used on
Armada 370. This commit fix the address reg of the e L2-cache node.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/armada-370.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index b2c1b5a..a38a262 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -38,7 +38,7 @@
 
 			L2: l2-cache {
 				compatible = "marvell,aurora-outer-cache";
-				reg = <0xd0008000 0x1000>;
+				reg = <0x08000 0x1000>;
 				cache-id-part = <0x100>;
 				wt-override;
 			};
-- 
1.8.1.2



From catalin.marinas at arm.com  Mon May 20 10:18:09 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 15:18:09 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <1368810473-26070-15-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
Message-ID: <20130520141809.GA27473@arm.com>

On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
> CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
> userspace software can avoid having to use the exclusive variants of
> these instructions if they wish.
> 
> This patch advertises the atomicity of these instructions via the
> hwcaps, so userspace can detect this CPU feature.
> 
> Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
...
> +
> +	/* LPAE implies atomic ldrd/strd instructions */
> +	vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
> +	if (vmsa >= 5)
> +		elf_hwcap |= HWCAP_LPAE;

As I mentioned in the past, I don't agree with exposing the "LPAE"
feature to user-space, it's not a feature that user space should care
about. An atomic double hwcap is better and you can even make this per
CPU via __v7_proc.

-- 
Catalin


From will.deacon at arm.com  Mon May 20 10:24:59 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 15:24:59 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130520141809.GA27473@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
Message-ID: <20130520142459.GN31359@mudshark.cambridge.arm.com>

On Mon, May 20, 2013 at 03:18:09PM +0100, Catalin Marinas wrote:
> On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
> > CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
> > userspace software can avoid having to use the exclusive variants of
> > these instructions if they wish.
> > 
> > This patch advertises the atomicity of these instructions via the
> > hwcaps, so userspace can detect this CPU feature.
> > 
> > Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
> > Signed-off-by: Will Deacon <will.deacon at arm.com>
> ...
> > +
> > +	/* LPAE implies atomic ldrd/strd instructions */
> > +	vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
> > +	if (vmsa >= 5)
> > +		elf_hwcap |= HWCAP_LPAE;
> 
> As I mentioned in the past, I don't agree with exposing the "LPAE"
> feature to user-space, it's not a feature that user space should care
> about. An atomic double hwcap is better and you can even make this per
> CPU via __v7_proc.

I don't buy the argument that this could be per-CPU: doubleword atomicity
requires support in the whole system -- not just in the CPU. The only way we
can rely on it, is by guarantees made in the architecture, which are made
as part of LPAE.

If this just boils down to a naming issue, thn I'm happy to change it, but
we *are* reporting whether LPAE is supported and I can't think of a better
name than that.

Will


From catalin.marinas at arm.com  Mon May 20 10:29:58 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 15:29:58 +0100
Subject: [PATCH v4 01/32] arm64: KVM: define HYP and Stage-2
 translation page flags
In-Reply-To: <1368540840-26750-2-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520142958.GB27473@arm.com>

On Tue, May 14, 2013 at 03:13:29PM +0100, Marc Zyngier wrote:
> Add HYP and S2 page flags, for both normal and device memory.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From paul at pwsan.com  Mon May 20 10:39:21 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 20 May 2013 14:39:21 +0000 (UTC)
Subject: [PATCH-V2] ARM: OMAP2+: AM33xx: Fix missing reset status data
 to GFX hwmod
In-Reply-To: <1369057116-31423-1-git-send-email-hvaibhav@ti.com>
References: <1369057116-31423-1-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.02.1305201439020.6174@utopia.booyaka.com>

On Mon, 20 May 2013, Vaibhav Hiremath wrote:

> GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
> so update the GFX hwmod data with .rstst_off and .st_shift
> information.
> 
> Although it doesn't have impact on kernel boot, but this is
> regression fix from original hwmod commit.
> 

Did it ever work?  If not, then it's not a regression, right?


- Paul


From dinh.linux at gmail.com  Mon May 20 10:40:18 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Mon, 20 May 2013 09:40:18 -0500
Subject: [PATCHv2 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <20130517114607.GB3466@amd.pavel.ucw.cz>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
 <1368731117-4749-6-git-send-email-dinguyen@altera.com>
 <20130517114607.GB3466@amd.pavel.ucw.cz>
Message-ID: <519A35D2.4010601@gmail.com>

Hi Pavel,

On 05/17/2013 06:46 AM, Pavel Machek wrote:
> Hi!
> 
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>> can use this define.
> 
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> @@ -0,0 +1,139 @@
>> +/*
>> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
>> + *
>> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
>> + *  Copyright (C) 2013 Altera Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Taken from dw_mmc_exynos.c
> 
> Actually it is   dw_mmc-exynos.c

Will fix in rev3.

> 
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
>> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> 
> Should SYSMGR stuff go to shared header file somewhere?
> 
>> +extern void __iomem *sys_manager_base_addr;
> 
> This is unused.

Will remove.

> 
>> +/* SOCFPGA implementation specific driver private data */
>> +struct dw_mci_socfpga_priv_data {
>> +	u8	ciu_div;
> 
> comment would be nice, something like
> /* card interface unit divisor */ ?
> 
>> +	u32	hs_timing;
> 
> /* card interface unit phase shift for RX/TX mode */
> ?

Will add comments.

> 
>> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	clk_disable(host->ciu_clk);
>> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
>> +	clk_enable(host->ciu_clk);
>> +
>> +	host->bus_hz /= (priv->ciu_div + 1);
> 
> Previous version said:
> 
> +       host->bus_hz /= priv->ciu_div;
> 
> I see you want to avoid division by zero, but this will introduce
> significant error for low divisors, right? Is divisor of 0 valid?

Divisor of 0 is not valid. Not sure what you mean my low divisos?

Thanks,
Dinh
> 
> Otherwise it looks good. Thanks,
> 									Pavel
> 


From ebiederm at xmission.com  Mon May 20 10:40:24 2013
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Mon, 20 May 2013 07:40:24 -0700
Subject: [PATCH] include/linux/posix_acl.h: need 'return NULL' when BUG(),
 if neither CONFIG_BUG nor HAVE_ARCH_BUG is defined.
In-Reply-To: <5199DBE2.5080707@asianux.com>
References: <5199DBE2.5080707@asianux.com>
Message-ID: <97dada79-cd78-4799-8f18-ed2bf8eee508@email.android.com>



Chen Gang <gang.chen at asianux.com> wrote:

>
>If neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, the BUG() will
>defined as empty (e.g. randconfig with MMU for arm s5pv210)
>
>In this case, need 'return NULL' to let upper caller knows the failure.

Seriously?  The correct fix it would seem is to give a useful default BUG definition.  Say *NULL.

Further we should never hit that code in the first place if it calls BUG.  So upper callers should never get there.

If it is ever possible to get there the callers need to be fixed.

Eric

>Signed-off-by: Chen Gang <gang.chen at asianux.com>
>---
> include/linux/posix_acl.h |    1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
>diff --git a/include/linux/posix_acl.h b/include/linux/posix_acl.h
>index 7931efe..2c48d06 100644
>--- a/include/linux/posix_acl.h
>+++ b/include/linux/posix_acl.h
>@@ -104,6 +104,7 @@ static inline struct posix_acl **acl_by_type(struct
>inode *inode, int type)
> 		return &inode->i_default_acl;
> 	default:
> 		BUG();
>+		return NULL;
> 	}
> }
> 
>-- 
>1.7.7.6



From dinh.linux at gmail.com  Mon May 20 10:47:43 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Mon, 20 May 2013 09:47:43 -0500
Subject: [PATCHv2 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <000a01ce551c$7b174190$7145c4b0$%jun@samsung.com>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
 <1368731117-4749-6-git-send-email-dinguyen@altera.com>
 <000a01ce551c$7b174190$7145c4b0$%jun@samsung.com>
Message-ID: <519A378F.7070409@gmail.com>

Hi Seungwon,

On 05/20/2013 12:40 AM, Seungwon Jeon wrote:
> On 05/17/13 4:05, Dinh Nguyen wrote:
>> From: Dinh Nguyen <dinguyen at altera.com>
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>> can use this define.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
>> CC: Seungwon Jeon <tgih.jun at samsung.com>
>> CC: Jaehoon Chung <jh80.chung at samsung.com>
>> CC: Arnd Bergmann <arnd at arndb.de>
>> CC: Olof Johansson <olof at lixom.net>
>> CC: Pavel Machek <pavel at denx.de>
>> CC: linux-mmc at vger.kernel.org
>>
>> v2:
>> - Use syscon and regmap
>> - Avoid divide by zero
>> - Remove the need to set PWR_EN
>> ---
>>  drivers/mmc/host/Kconfig          |    8 +++
>>  drivers/mmc/host/Makefile         |    1 +
>>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>>  drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
>>  drivers/mmc/host/dw_mmc.h         |    1 +
>>  5 files changed, 149 insertions(+), 2 deletions(-)
>>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
>>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 9ab8f8d..1be2289 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>>
>> +config MMC_DW_SOCFPGA
>> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
>> +	depends on MMC_DW
>> +	select MMC_DW_PLTFM
>> +	help
>> +	  This selects support for Altera SoCFPGA specific extensions to the
>> +	  Synopsys DesignWare Memory Card Interface driver.
>> +
>>  config MMC_DW_PCI
>>  	tristate "Synopsys Designware MCI support on PCI bus"
>>  	depends on MMC_DW && PCI
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index cd32280..67718c1 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
>> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index f013e7e..866edef 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -31,8 +31,6 @@
>>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
>>
>> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
>> -
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
>>
>> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
>> new file mode 100644
>> index 0000000..af89685
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> @@ -0,0 +1,139 @@
>> +/*
>> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
>> + *
>> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
>> + *  Copyright (C) 2013 Altera Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Taken from dw_mmc_exynos.c
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/mmc/host.h>
>> +#include <linux/mmc/dw_mmc.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include "dw_mmc.h"
>> +#include "dw_mmc-pltfm.h"
>> +
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)		\
>> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> Did you check Jaehoon Chung's comment?
> It's trivial, but more common.
> ((((smplsel) & 0x38) << 3) | (((drvsel) & 0x7) << 0))
>

Yes, I missed the comment. Will change in rev3.

>> +
>> +extern void __iomem *sys_manager_base_addr;
>> +
>> +/* SOCFPGA implementation specific driver private data */
>> +struct dw_mci_socfpga_priv_data {
>> +	u8	ciu_div;
>> +	u32	hs_timing;
>> +	struct regmap   *sysreg;
>> +};
>> +
>> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv;
>> +	struct device *dev = host->dev;
>> +
>> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> +	if (!priv) {
>> +		dev_err(host->dev, "mem alloc failed for private data\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	host->priv = priv;
>> +	return 0;
>> +}
>> +
>> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	clk_disable(host->ciu_clk);
>> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
>> +	clk_enable(host->ciu_clk);
> You can use clk_prepare_enable/clk_disable_unprepare instead of clk_enable/clk_disable.
> 

OK.

>> +
>> +	host->bus_hz /= (priv->ciu_div + 1);
>> +	return 0;
>> +}
>> +
>> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
>> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> +}
>> +
>> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +	struct device_node *np = host->dev->of_node;
>> +	u32 timing[2];
>> +	u32 div = 0;
>> +	int ret;
>> +
>> +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> How about placing syscon_regmap_lookup_by_compatible in dw_mci_socfpga_priv_init.
> It seems more proper place.
>

Ok, will move.

>> +	if (IS_ERR(priv->sysreg)) {
>> +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
>> +		return PTR_ERR(priv->sysreg);
>> +	}
>> +
>> +	of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> Error check would be helpful.
> ret = of_property_read_u32();
> 
> Thanks,
> Seungwon Jeon
>

Thanks for the review.

Dinh

>> +	priv->ciu_div = div;
>> +
>> +	ret = of_property_read_u32_array(np,
>> +			"altr,dw-mshc-sdr-timing", timing, 2);
>> +	if (ret)
>> +		return ret;
>> +
>> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
>> +	return 0;
>> +}
>> +
>> +static const struct dw_mci_drv_data socfpga_drv_data = {
>> +	.init			= dw_mci_socfpga_priv_init,
>> +	.setup_clock		= dw_mci_socfpga_setup_clock,
>> +	.prepare_command	= dw_mci_socfpga_prepare_command,
>> +	.parse_dt		= dw_mci_socfpga_parse_dt,
>> +};
>> +
>> +static const struct of_device_id dw_mci_socfpga_match[] = {
>> +	{ .compatible = "altr,socfpga-dw-mshc",
>> +			.data = &socfpga_drv_data, },
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
>> +
>> +int dw_mci_socfpga_probe(struct platform_device *pdev)
>> +{
>> +	const struct dw_mci_drv_data *drv_data;
>> +	const struct of_device_id *match;
>> +
>> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
>> +	drv_data = match->data;
>> +	return dw_mci_pltfm_register(pdev, drv_data);
>> +}
>> +
>> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
>> +	.probe		= dw_mci_socfpga_probe,
>> +	.remove		= __exit_p(dw_mci_pltfm_remove),
>> +	.driver		= {
>> +		.name		= "dwmmc_socfpga",
>> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
>> +		.pm		= &dw_mci_pltfm_pmops,
>> +	},
>> +};
>> +
>> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
>> +
>> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:dwmmc-socfpga");
>> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
>> index 0b74189..3700cb2 100644
>> --- a/drivers/mmc/host/dw_mmc.h
>> +++ b/drivers/mmc/host/dw_mmc.h
>> @@ -111,6 +111,7 @@
>>  #define SDMMC_INT_ERROR			0xbfc2
>>  /* Command register defines */
>>  #define SDMMC_CMD_START			BIT(31)
>> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>>  #define SDMMC_CMD_UPD_CLK		BIT(21)
>> --
>> 1.7.9.5
>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From dinh.linux at gmail.com  Mon May 20 10:59:59 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Mon, 20 May 2013 09:59:59 -0500
Subject: [PATCHv2 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <20130517110940.GA3466@amd.pavel.ucw.cz>
References: <1368731117-4749-1-git-send-email-dinguyen@altera.com>
 <1368731117-4749-3-git-send-email-dinguyen@altera.com>
 <20130517110940.GA3466@amd.pavel.ucw.cz>
Message-ID: <519A3A6F.7020700@gmail.com>

Hi Pavel,

On 05/17/2013 06:09 AM, Pavel Machek wrote:
> Hi!
> 
>> From: Dinh Nguyen <dinguyen at altera.com>
>>
>> Add support to gate the clocks that directly feed peripherals. For clocks
>> with multiple parents, add the ability to determine the correct parent,
>> and also set parents. Also add support to calculate and set the clocks'
>> rate.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
>> Reviewed-by: Pavel Machek <pavel at denx.de>
>> CC: Mike Turquette <mturquette at linaro.org>
>> CC: Arnd Bergmann <arnd at arndb.de>
>> CC: Olof Johansson <olof at lixom.net>
>> Cc: Pavel Machek <pavel at denx.de>
>> CC: <linux at arm.linux.org.uk>
>>
>> v2:
>> - Fix space/indent errors
>> - Add streq for strcmp == 0
>> ---
> 
>> +static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>> +{
>> +	u32 l4_src;
>> +	u32 perpll_src;
>> +	u8 parent;
>> +
>> +	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
>> +		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
>> +		l4_src &= 0x1;
>> +		parent = l4_src;
>> +	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
>> +		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
>> +		l4_src = ((l4_src & 0x2) >> 1);
>> +		parent = l4_src;
>> +	} else {
>> +		perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
>> +		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
>> +			perpll_src &= 0x3;
>> +		else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
>> +			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
>> +			perpll_src = ((perpll_src & 0xC) >> 2);
>> +		else /*QSPI clock */
>> +			perpll_src = ((perpll_src & 0x30) >> 4);
>> +		parent = perpll_src;
> 
> I really don't like the "else" here. If some new clock name appears in
> hwclk->init->name or if there's problem somewhere, it will just
> silently operate wrong clock. WARN_ON(!streq(...))?
> 
> (I tried to append patch to previous email, with suggested
> cleanups....)
> 

Ok, will fix in rev3.

>> +		} else {/*QSPI clock */
>> +			src_reg &= ~0x30;
>> +			src_reg |= (parent << 4);
>> +		}
> 
> Same here. (And there should be space after /* ).
>

OK...

>> +	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
>> +	if (WARN_ON(!socfpga_clk))
>> +		return;
>> +
>> +	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
>> +	if (rc)
>> +		clk_gate[0] = 0;
>> +
>> +	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
>> +	if (rc)
>> +		socfpga_clk->fixed_div = 0;
>> +	else
>> +		socfpga_clk->fixed_div = fixed_div;
>> +
>> +	if (clk_gate[0]) {
>> +		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
>> +		socfpga_clk->hw.bit_idx = clk_gate[1];
>> +
>> +		gateclk_ops.enable = clk_gate_ops.enable;
>> +		gateclk_ops.disable = clk_gate_ops.disable;
>> +	}
>> +
> 
> Could if (clk_gate[]) be moved one block above? It uses
> partially-initialized array, so it would be nice to have code as clear
> as possible.
> 

OK..

> 
>> +	of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +	init.name = clk_name;
>> +	init.ops = ops;
>> +	init.flags = 0;
>> +	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
>> +			of_clk_get_parent_name(node, i)) != NULL)
>> +		i++;
> 
> I'd suggest explicit loop, like
> 
> +       while (i < SOCFGPA_MAX_PARENTS) {
> +               char *name = of_clk_get_parent_name(node, i);
> +               parent_name[i] = name;
> +               if (name == NULL)
> +                       break;
>                 i++;
> +       }
> 
> This is a bit too subtle.

I don't know, it seems like the previous simple loop is pretty explicit.

> 
>> +	init.parent_names = parent_name;
>> +	init.num_parents = i;
>> +	socfpga_clk->hw.hw.init = &init;
>> +
>> +	clk = clk_register(NULL, &socfpga_clk->hw.hw);
> 
> init is local variable, yet pointer passed to it is in globally
> alocated structure. What is going on there? Are there some comments
> needed?

Same code is used everywhere in drivers/clk.

Dinh
> 
> Thanks,
> 									Pavel
> 


From jason at lakedaemon.net  Mon May 20 11:10:33 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 11:10:33 -0400
Subject: [PATCH] arm: mvebu: enable the third USB interface on
 OpenBlocks AX3
In-Reply-To: <20130519213040.GD8651@1wt.eu>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
 <20130519201939.GL11137@titan.lakedaemon.net>
 <20130519213040.GD8651@1wt.eu>
Message-ID: <20130520151033.GS31290@titan.lakedaemon.net>

On Sun, May 19, 2013 at 11:30:40PM +0200, Willy Tarreau wrote:
> On Sun, May 19, 2013 at 04:19:39PM -0400, Jason Cooper wrote:
> > Mr Yamagata, Willy,
> > 
> > I don't like to assume for people, so if you could please provided a
> > "Tested-by:" I'd appreciate it.
> 
> Yes of course, I didn't propose it in order to save you the work of
> collecting these tags :-)
> 
>   Tested-by: Willy Tarreau <w at 1wt.eu>

Thanks!

Jason.


From jason at lakedaemon.net  Mon May 20 11:10:53 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 11:10:53 -0400
Subject: [PATCH] arm: mvebu: enable the third USB interface on
 OpenBlocks AX3
In-Reply-To: <20130520.145044.280780615.yamagata@plathome.co.jp>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130517.111810.02327269.yamagata@plathome.co.jp>
 <20130519201939.GL11137@titan.lakedaemon.net>
 <20130520.145044.280780615.yamagata@plathome.co.jp>
Message-ID: <20130520151053.GT31290@titan.lakedaemon.net>

On Mon, May 20, 2013 at 02:50:44PM +0900, yamagata at plathome.co.jp wrote:
> Dear Mr. Jason Cooper
> 
> > I don't like to assume for people, so if you could please provided a
> > "Tested-by:" I'd appreciate it.
> 
> Tested-by: Atsushi Yamagata <yamagata at plathome.co.jp>

Thanks!

Jason.


From catalin.marinas at arm.com  Mon May 20 11:11:58 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:11:58 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130520142459.GN31359@mudshark.cambridge.arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <20130520142459.GN31359@mudshark.cambridge.arm.com>
Message-ID: <20130520151158.GA3520@MacBook-Pro.local>

On Mon, May 20, 2013 at 03:24:59PM +0100, Will Deacon wrote:
> On Mon, May 20, 2013 at 03:18:09PM +0100, Catalin Marinas wrote:
> > On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
> > > CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
> > > userspace software can avoid having to use the exclusive variants of
> > > these instructions if they wish.
> > > 
> > > This patch advertises the atomicity of these instructions via the
> > > hwcaps, so userspace can detect this CPU feature.
> > > 
> > > Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
> > > Signed-off-by: Will Deacon <will.deacon at arm.com>
> > ...
> > > +
> > > +	/* LPAE implies atomic ldrd/strd instructions */
> > > +	vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
> > > +	if (vmsa >= 5)
> > > +		elf_hwcap |= HWCAP_LPAE;
> > 
> > As I mentioned in the past, I don't agree with exposing the "LPAE"
> > feature to user-space, it's not a feature that user space should care
> > about. An atomic double hwcap is better and you can even make this per
> > CPU via __v7_proc.
> 
> I don't buy the argument that this could be per-CPU: doubleword atomicity
> requires support in the whole system -- not just in the CPU. The only way we
> can rely on it, is by guarantees made in the architecture, which are made
> as part of LPAE.

Well, you know that for A7/A15 you have this feature as they support
LPAE. You can have it as a generic LPAE test (only that the ARM ARM
isn't entirely clear here, so for people asking in the future we could
say it's a feature of the A7/A15/etc.)

> If this just boils down to a naming issue, thn I'm happy to change it, but
> we *are* reporting whether LPAE is supported and I can't think of a better
> name than that.

Given that the ARM ARM isn't clear (though this is the case on the
actual implementations), user space may not necessarily assume that
LPAE==atomic doubles. That's why I think reporting the actual atomic
feature is better.

-- 
Catalin


From rklein at nvidia.com  Mon May 20 11:24:23 2013
From: rklein at nvidia.com (Rhyland Klein)
Date: Mon, 20 May 2013 11:24:23 -0400
Subject: [PATCH] ARM: tegra: Add charger subnode to tps65090 node
In-Reply-To: <5196C3F2.8070204@wwwdotorg.org>
References: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
 <5196C3F2.8070204@wwwdotorg.org>
Message-ID: <519A4027.2020801@nvidia.com>

On 5/17/2013 7:57 PM, Stephen Warren wrote:
> On 04/10/2013 01:51 PM, Rhyland Klein wrote:
>> The charger is now represented by a distinct subnode of the tps65090
>> device. Add this node and enable low current charging with it.
> 
> What's the status of the TPS60590 bindings; are they agreed upon by
> NVIDIA, TI, and SlimLogic yet? In other words, is this patch still
> something I should apply for 3.11, or does it need to be reworked?

I haven't seen any discussion with slimlogic or TI about the tps65090.
As far as I know the bindings for this driver haven't changed.

Laxman, do you think the work on the palmas driver will impact the
design of the bindings for the tps65090?

-rhyland

> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

-- 
nvpublic


From swarren at wwwdotorg.org  Mon May 20 11:25:46 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 09:25:46 -0600
Subject: [PATCH V2] video: implement a simple framebuffer driver
In-Reply-To: <CAAVeFuJ5q4Y0QtvJX2iVmq_O2ofs1B9=MB_aA8VdcEBdM4zf2Q@mail.gmail.com>
References: <1365043183-28905-1-git-send-email-swarren@wwwdotorg.org>
 <CAAVeFuJ5q4Y0QtvJX2iVmq_O2ofs1B9=MB_aA8VdcEBdM4zf2Q@mail.gmail.com>
Message-ID: <519A407A.4040006@wwwdotorg.org>

On 05/18/2013 04:29 AM, Alexandre Courbot wrote:
> On Thu, Apr 4, 2013 at 11:39 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>> +struct simplefb_format {
>> +       const char *name;
>> +       u32 bits_per_pixel;
>> +       struct fb_bitfield red;
>> +       struct fb_bitfield green;
>> +       struct fb_bitfield blue;
>> +       struct fb_bitfield transp;
>> +};
>> +
>> +struct simplefb_format simplefb_formats[] = {
>> +       { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0} },
>> +};
> 
> I have been adding a few extra formats to this list, and I wonder if
> this could not simply be turned into a function that would directly
> convert the name string into the corresponding right format. The
> mapping between name and format seems to be a 1:1 and this would
> probably avoid errors in the future. I'm especially thinking about
> color order here - I started adding a mode that reads
> 
>     { "r8g8b8a8", 32, {0, 8}, {8, 8}, {16, 8}, {24, 8} },
> 
> while it should probably be called "a8b8g8r8" as the order of colors
> is not the same as your r5g6b5.
> 
> I can submit a patch if there is no issue with that idea.

I chose r5g6b5 rather than rgb565 specifically to make that format
trivially name machine-parsable. So, I'm not opposed to converting that
table to code. I'm not 100% sure if it's worth it or necessary by the
time we get to just 2 formats in the array, but I don't see any big
disadvantage, so why not. The DT binding documentation might want
enhancing with a more general description of how formats should be
represented if this is implemented.


From swarren at wwwdotorg.org  Mon May 20 11:28:08 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 09:28:08 -0600
Subject: [PATCH] ARM: tegra: Add charger subnode to tps65090 node
In-Reply-To: <519A4027.2020801@nvidia.com>
References: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
 <5196C3F2.8070204@wwwdotorg.org> <519A4027.2020801@nvidia.com>
Message-ID: <519A4108.2040606@wwwdotorg.org>

On 05/20/2013 09:24 AM, Rhyland Klein wrote:
> On 5/17/2013 7:57 PM, Stephen Warren wrote:
>> On 04/10/2013 01:51 PM, Rhyland Klein wrote:
>>> The charger is now represented by a distinct subnode of the tps65090
>>> device. Add this node and enable low current charging with it.
>>
>> What's the status of the TPS60590 bindings; are they agreed upon by
>> NVIDIA, TI, and SlimLogic yet? In other words, is this patch still
>> something I should apply for 3.11, or does it need to be reworked?
> 
> I haven't seen any discussion with slimlogic or TI about the tps65090.
> As far as I know the bindings for this driver haven't changed.
> 
> Laxman, do you think the work on the palmas driver will impact the
> design of the bindings for the tps65090?

Sorry, perhaps I'm confusing two different chips. If TPS65090 isn't
Palmas, then ignore my question. In which case, I suppose I should just
apply your patch then?


From catalin.marinas at arm.com  Mon May 20 11:31:43 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:31:43 +0100
Subject: [PATCH v4 02/32] arm64: KVM: HYP mode idmap support
In-Reply-To: <1368540840-26750-3-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520153142.GA3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:30PM +0100, Marc Zyngier wrote:
> Add the necessary infrastructure for identity-mapped HYP page
> tables. Idmap-ed code must be in the ".hyp.idmap.text" linker
> section.
> 
> The rest of the HYP ends up in ".hyp.text".
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
...
> +/*
> + * The HYP init code can't be more than a page long.
> + */
> +ASSERT(((__hyp_idmap_text_start + PAGE_SIZE) >= __hyp_idmap_text_end),
> +       "HYP init code too big")

Is __hyp_idmap_text_end inclusive or exclusive? I think the latter and
you can use greater than (without equal).

Otherwise:

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From rklein at nvidia.com  Mon May 20 11:35:03 2013
From: rklein at nvidia.com (Rhyland Klein)
Date: Mon, 20 May 2013 11:35:03 -0400
Subject: [PATCH] ARM: tegra: Add charger subnode to tps65090 node
In-Reply-To: <519A4108.2040606@wwwdotorg.org>
References: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
 <5196C3F2.8070204@wwwdotorg.org> <519A4027.2020801@nvidia.com>
 <519A4108.2040606@wwwdotorg.org>
Message-ID: <519A42A7.5080208@nvidia.com>

On 5/20/2013 11:28 AM, Stephen Warren wrote:
> On 05/20/2013 09:24 AM, Rhyland Klein wrote:
>> On 5/17/2013 7:57 PM, Stephen Warren wrote:
>>> On 04/10/2013 01:51 PM, Rhyland Klein wrote:
>>>> The charger is now represented by a distinct subnode of the tps65090
>>>> device. Add this node and enable low current charging with it.
>>>
>>> What's the status of the TPS60590 bindings; are they agreed upon by
>>> NVIDIA, TI, and SlimLogic yet? In other words, is this patch still
>>> something I should apply for 3.11, or does it need to be reworked?
>>
>> I haven't seen any discussion with slimlogic or TI about the tps65090.
>> As far as I know the bindings for this driver haven't changed.
>>
>> Laxman, do you think the work on the palmas driver will impact the
>> design of the bindings for the tps65090?
> 
> Sorry, perhaps I'm confusing two different chips. If TPS65090 isn't
> Palmas, then ignore my question. In which case, I suppose I should just
> apply your patch then?
> 

I would say yes. The design of having the child node this way was how we
had agreed worked best. The only reason I would see a significant reason
to change this, is if something was decided that all mfd devices should
start to follow some pattern which differed, which would mean changing
existing bindings and therefore is unlikely.

-rhyland

-- 
nvpublic


From catalin.marinas at arm.com  Mon May 20 11:35:58 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:35:58 +0100
Subject: [PATCH v4 03/32] arm64: KVM: EL2 register definitions
In-Reply-To: <1368540840-26750-4-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-4-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520153558.GB3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:31PM +0100, Marc Zyngier wrote:
> Define all the useful bitfields for EL2 registers.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Mon May 20 11:38:23 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:38:23 +0100
Subject: [PATCH v4 04/32] arm64: KVM: system register definitions for
 64bit guests
In-Reply-To: <1368540840-26750-5-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-5-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520153823.GC3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:32PM +0100, Marc Zyngier wrote:
> Define the saved/restored registers for 64bit guests.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Mon May 20 11:41:43 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:41:43 +0100
Subject: [PATCH v4 05/32] arm64: KVM: Basic ESR_EL2 helpers and vcpu
 register access
In-Reply-To: <1368540840-26750-6-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-6-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520154142.GD3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:33PM +0100, Marc Zyngier wrote:
> Implements helpers for dealing with the EL2 syndrome register as
> well as accessing the vcpu registers.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
...
> +static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
> +{
> +	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);
> +}

You kept these '!!' ;). BTW, would the compiler handle the conversion
between the integer and bool here?

Either way is fine by me:

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From marc.zyngier at arm.com  Mon May 20 11:43:06 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 20 May 2013 16:43:06 +0100
Subject: [PATCH v4 02/32] arm64: KVM: HYP mode idmap support
In-Reply-To: <20130520153142.GA3639@MacBook-Pro.local>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-3-git-send-email-marc.zyngier@arm.com>
 <20130520153142.GA3639@MacBook-Pro.local>
Message-ID: <519A448A.4000506@arm.com>

On 20/05/13 16:31, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:30PM +0100, Marc Zyngier wrote:
>> Add the necessary infrastructure for identity-mapped HYP page
>> tables. Idmap-ed code must be in the ".hyp.idmap.text" linker
>> section.
>>
>> The rest of the HYP ends up in ".hyp.text".
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ...
>> +/*
>> + * The HYP init code can't be more than a page long.
>> + */
>> +ASSERT(((__hyp_idmap_text_start + PAGE_SIZE) >= __hyp_idmap_text_end),
>> +       "HYP init code too big")
> 
> Is __hyp_idmap_text_end inclusive or exclusive? I think the latter and
> you can use greater than (without equal).

Indeed. I'll update the check.

> Otherwise:
> 
> Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From marc.zyngier at arm.com  Mon May 20 11:45:15 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 20 May 2013 16:45:15 +0100
Subject: [PATCH v4 05/32] arm64: KVM: Basic ESR_EL2 helpers and vcpu
 register access
In-Reply-To: <20130520154142.GD3639@MacBook-Pro.local>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-6-git-send-email-marc.zyngier@arm.com>
 <20130520154142.GD3639@MacBook-Pro.local>
Message-ID: <519A450B.5030309@arm.com>

On 20/05/13 16:41, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:33PM +0100, Marc Zyngier wrote:
>> Implements helpers for dealing with the EL2 syndrome register as
>> well as accessing the vcpu registers.
>>
>> Reviewed-by: Christopher Covington <cov at codeaurora.org>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ...
>> +static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
>> +{
>> +	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);
>> +}
> 
> You kept these '!!' ;). BTW, would the compiler handle the conversion
> between the integer and bool here?

I like them very much. The compiler handles the conversion perfectly
fine, but the '!!' makes the intent explicit, and someone reviewing the
code won't be tempted to change the return type to u64 or something similar.

> Either way is fine by me:
> 
> Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From plagnioj at jcrosoft.com  Mon May 20 11:44:15 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 17:44:15 +0200
Subject: [PATCH 1/5] usb: add Atmel USBA UDC DT support
In-Reply-To: <20130520101237.GA9937@game.jcrosoft.org>
References: <20130517141443.GB16804@game.jcrosoft.org>
 <1368801730-31383-1-git-send-email-plagnioj@jcrosoft.com>
 <519997CA.8010503@atmel.com>
 <20130520101237.GA9937@game.jcrosoft.org>
Message-ID: <20130520154415.GB9937@game.jcrosoft.org>

On 12:12 Mon 20 May     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >
> > >-static int __init usba_udc_probe(struct platform_device *pdev)
> > >+#ifdef CONFIG_OF
> > >+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
> > >+						    struct usba_udc *udc)
> > >+{
> > >+	u32 val;
> > >+	const char *name;
> > >+	enum of_gpio_flags flags;
> > >+	struct device_node *np = pdev->dev.of_node;
> > >+	struct device_node *pp;
> > >+	int i, ret;
> > >+	struct usba_ep *eps, *ep;
> > >+
> > >+	udc->num_ep = 0;
> > >+
> > >+	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
> > >+						&flags);
> > >+	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
> > >+
> > >+	pp = NULL;
> > >+	while ((pp = of_get_next_child(np, pp)))
> > >+		udc->num_ep++;
> > >+
> > >+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
> > >+			   GFP_KERNEL);
> > 
> > Using devm_kzalloc will cause issue when build as modules, and load
> > and unload this driver, the second time unload, it will come out
> > following segment fault, log as following. Using kzalloc will fix
> > it.
> 
> no devm_kzalloc is the right one to use
> 
> if there is a this not in the drivers and kzalloc is not the solution
> we need to find the real reason as devm_xxx are used everywhere by now

The issue come from that the current driver have some hack that forbiden
multi-instance

I'll drop that

so yes devm_kzalloc is the right alloc to use


From catalin.marinas at arm.com  Mon May 20 11:53:02 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:53:02 +0100
Subject: [PATCH v4 06/32] arm64: KVM: fault injection into a guest
In-Reply-To: <1368540840-26750-7-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-7-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520155302.GE3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:34PM +0100, Marc Zyngier wrote:
> Implement the injection of a fault (undefined, data abort or
> prefetch abort) into a 64bit guest.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Mon May 20 11:57:40 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 16:57:40 +0100
Subject: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend
In-Reply-To: <1368540840-26750-8-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-8-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520155739.GF3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
> +static inline bool kvm_is_write_fault(unsigned long esr)
> +{
> +	unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;

Not that it would make much difference but for consistency - we use esr
as an 'unsigned int' in the arm64 code (only 32-bit needed).

-- 
Catalin


From catalin.marinas at arm.com  Mon May 20 12:01:48 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 17:01:48 +0100
Subject: [PATCH v4 08/32] arm64: KVM: user space interface
In-Reply-To: <1368540840-26750-9-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-9-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520160147.GG3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:36PM +0100, Marc Zyngier wrote:
> Provide the kvm.h file that defines the user space visible
> interface.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From will.deacon at arm.com  Mon May 20 12:04:07 2013
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 May 2013 17:04:07 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130520151158.GA3520@MacBook-Pro.local>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <20130520142459.GN31359@mudshark.cambridge.arm.com>
 <20130520151158.GA3520@MacBook-Pro.local>
Message-ID: <20130520160407.GS31359@mudshark.cambridge.arm.com>

On Mon, May 20, 2013 at 04:11:58PM +0100, Catalin Marinas wrote:
> On Mon, May 20, 2013 at 03:24:59PM +0100, Will Deacon wrote:
> > On Mon, May 20, 2013 at 03:18:09PM +0100, Catalin Marinas wrote:
> > > As I mentioned in the past, I don't agree with exposing the "LPAE"
> > > feature to user-space, it's not a feature that user space should care
> > > about. An atomic double hwcap is better and you can even make this per
> > > CPU via __v7_proc.
> > 
> > I don't buy the argument that this could be per-CPU: doubleword atomicity
> > requires support in the whole system -- not just in the CPU. The only way we
> > can rely on it, is by guarantees made in the architecture, which are made
> > as part of LPAE.
> 
> Well, you know that for A7/A15 you have this feature as they support
> LPAE. You can have it as a generic LPAE test (only that the ARM ARM
> isn't entirely clear here, so for people asking in the future we could
> say it's a feature of the A7/A15/etc.)

No, as far as Linux is concerned, it's a feature of any system claiming to
have support for LPAE. Given that we allocate page tables using our usual
allocators, all memory that we map as normal must be capable of doubleword
atomics. We make use of this in our atomic64_{read,set} implementations.

> > If this just boils down to a naming issue, thn I'm happy to change it, but
> > we *are* reporting whether LPAE is supported and I can't think of a better
> > name than that.
> 
> Given that the ARM ARM isn't clear (though this is the case on the
> actual implementations), user space may not necessarily assume that
> LPAE==atomic doubles. That's why I think reporting the actual atomic
> feature is better.

The ARM ARM isn't too bad: it's just avoiding mandating 64-bit-wide paths
around the entire SoC (and I've checked this with the architects). The only
way we can probe this feature is using the MMFR0 and checking if LPAE is
supported, and that's exactly what userspace will need to rely on. We can
change the name, but the probe code will remain the same so I'm not sure it
makes anything clearer. We had "atomicd" originally, but that sounds like a
techno band.

Will


From mkl at pengutronix.de  Mon May 20 12:06:24 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Mon, 20 May 2013 18:06:24 +0200
Subject: [PATCH v2] can: flexcan: remove HAVE_CAN_FLEXCAN Kconfig symbol
In-Reply-To: <20130517090949.GI8607@S2101-09.ap.freescale.net>
References: <1368781157-4646-1-git-send-email-mkl@pengutronix.de>
 <20130517090949.GI8607@S2101-09.ap.freescale.net>
Message-ID: <519A4A00.8000109@pengutronix.de>

On 05/17/2013 11:09 AM, Shawn Guo wrote:
> On Fri, May 17, 2013 at 10:59:17AM +0200, Marc Kleine-Budde wrote:
>> This patch removes the Kconfig symbol HAVE_CAN_FLEXCAN from arch/{arm,powerpc}
>> and allowing compilation unconditionally on all arm and powerpc platforms.
>>
>> This brings a bigger compile time coverage and removes the following dependency
>> warning found by Arnd Bergmann:
>>
>>     warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 && IMX_HAVE_PLATFORM_FLEXCAN &&
>>         SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
>>     which has unmet direct dependencies (NET && CAN && CAN_DEV)
>>
>> Cc: Arnd Bergmann <arnd at arndb.de>
>> Cc: Shawn Guo <shawn.guo at linaro.org>
> 
> Acked-by: Shawn Guo <shawn.guo at linaro.org>

Thanks.

An Acked-by by the powerpc people would be fine. However, if nobody
doesn't object, I'm sending this patch via linux-can and net-next upstream.

regards,
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From kgene.kim at samsung.com  Mon May 20 12:07:35 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 01:07:35 +0900
Subject: [PATCH v2] ARM: S3C24XX: add devicetree support for smdk2416
In-Reply-To: <201304131606.48278.heiko@sntech.de>
References: <201304131606.48278.heiko@sntech.de>
Message-ID: <519A4A47.1010300@samsung.com>

On 04/13/13 23:06, Heiko St?bner wrote:
> Definitions in s3c24xx.dtsi are usable for all s3c24xx SoCs, but some
> need to be extended with proper compatible properties, as can be seen
> in s3c2416.dtsi .
>
> Signed-off-by: Heiko Stuebner<heiko at sntech.de>
> Reviewed-by: Sylwester Nawrocki<s.nawrocki at samsung.com>

Looks good to me, applied, thanks.

- Kukjin

> ---
> changes since v1:
>    fix compatible property of default irq controller
>    (the correct one is samsung,s3c2410-irq)
>
>   arch/arm/boot/dts/Makefile              |    1 +
>   arch/arm/boot/dts/s3c2416-pinctrl.dtsi  |  173 +++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/s3c2416-smdk2416.dts  |   72 +++++++++++++
>   arch/arm/boot/dts/s3c2416.dtsi          |   79 ++++++++++++++
>   arch/arm/boot/dts/s3c24xx.dtsi          |   92 ++++++++++++++++
>   arch/arm/mach-s3c24xx/Kconfig           |   12 ++
>   arch/arm/mach-s3c24xx/Makefile          |    1 +
>   arch/arm/mach-s3c24xx/mach-s3c2416-dt.c |   91 ++++++++++++++++
>   8 files changed, 521 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/boot/dts/s3c2416-pinctrl.dtsi
>   create mode 100644 arch/arm/boot/dts/s3c2416-smdk2416.dts
>   create mode 100644 arch/arm/boot/dts/s3c2416.dtsi
>   create mode 100644 arch/arm/boot/dts/s3c24xx.dtsi
>   create mode 100644 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c


From marc.zyngier at arm.com  Mon May 20 12:17:31 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 20 May 2013 17:17:31 +0100
Subject: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend
In-Reply-To: <20130520155739.GF3639@MacBook-Pro.local>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-8-git-send-email-marc.zyngier@arm.com>
 <20130520155739.GF3639@MacBook-Pro.local>
Message-ID: <519A4C9B.8070307@arm.com>

On 20/05/13 16:57, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
>> +static inline bool kvm_is_write_fault(unsigned long esr)
>> +{
>> +	unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
> 
> Not that it would make much difference but for consistency - we use esr
> as an 'unsigned int' in the arm64 code (only 32-bit needed).

Indeed. Changing it would require a 32bit patch though, as I'd like to
keep the two code bases in line.

If you don't mind, I'll queue a patch changing this to "unsigned int" on
both architectures once this is merged.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From kgene.kim at samsung.com  Mon May 20 12:19:49 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 01:19:49 +0900
Subject: [PATCH] ARM: dts: add max8997 device node for exynos4210-origen
 board
In-Reply-To: <518C9807.80906@linaro.org>
References: <1353664412-17678-1-git-send-email-thomas.abraham@linaro.org>
 <50EA598D.6090604@linaro.org> <518C9807.80906@linaro.org>
Message-ID: <519A4D25.9090001@samsung.com>

On 05/10/13 15:47, Tushar Behera wrote:
> On 01/07/2013 10:43 AM, Tushar Behera wrote:
>> On 11/23/2012 03:23 PM, Thomas Abraham wrote:
>>> Add max8997 regulator device node for exynos4210-origen board and list
>>> all the supported regulators.
>>>
>>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>>
>> Tested-by: Tushar Behera<tushar.behera at linaro.org>
>>
> Kukjin,
>
> This patch got missed for 3.10 merge window. This patch still applies on
> the latest mainline kernel and is essential for Origen board. Would you
> please take this patch?
>
Applied, thanks.

- Kukjin


From catalin.marinas at arm.com  Mon May 20 12:21:48 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 17:21:48 +0100
Subject: [PATCH v4 09/32] arm64: KVM: system register handling
In-Reply-To: <1368540840-26750-10-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-10-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520162148.GH3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:37PM +0100, Marc Zyngier wrote:
> Provide 64bit system register handling, modeled after the cp15
> handling for ARM.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Mon May 20 12:25:28 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 17:25:28 +0100
Subject: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend
In-Reply-To: <519A4C9B.8070307@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-8-git-send-email-marc.zyngier@arm.com>
 <20130520155739.GF3639@MacBook-Pro.local>
 <519A4C9B.8070307@arm.com>
Message-ID: <20130520162528.GI3639@MacBook-Pro.local>

On Mon, May 20, 2013 at 05:17:31PM +0100, Marc Zyngier wrote:
> On 20/05/13 16:57, Catalin Marinas wrote:
> > On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
> >> +static inline bool kvm_is_write_fault(unsigned long esr)
> >> +{
> >> +	unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
> > 
> > Not that it would make much difference but for consistency - we use esr
> > as an 'unsigned int' in the arm64 code (only 32-bit needed).
> 
> Indeed. Changing it would require a 32bit patch though, as I'd like to
> keep the two code bases in line.
> 
> If you don't mind, I'll queue a patch changing this to "unsigned int" on
> both architectures once this is merged.

I'm OK if you push the patch afterwards, you can add my reviewed-by on
this patch.

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From plagnioj at jcrosoft.com  Mon May 20 12:21:49 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:21:49 +0200
Subject: [PATCH 0/7 v4] ARM: at91: dt: add USBA support
Message-ID: <20130520162149.GC9937@game.jcrosoft.org>

HI,

	v4:
	fix multi instance support

	v3:
	rebase againt 3.10-rc1 + dt macro cleanup

	This patch serie finish to add the usb device support to dt for at91
	with the usba support present on the last at91 generation since sam9g45

The following changes since commit b3f442b0eedbc20b5ce3f4a96530588d14901199:

  ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git j/for-3.11-usba

for you to fetch changes up to 910026a08e2c2205953f2507cc11f4822998989b:

  ARM: at91: sam9m10g45ek add udc DT support (2013-05-20 23:52:17 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (7):
      USB: gadget: atmel_usba: move global struct usba_ep usba_ep to struct usba_udc
      USB: gadget: atmel_usba: allow multi instance
      USB: gadget: atmel_usba: add DT support
      ARM: at91: sam9x5 add udc DT support
      ARM: at91: sam9x5ek add udc DT support
      ARM: at91: sam9g45 add udc DT support
      ARM: at91: sam9m10g45ek add udc DT support

 Documentation/devicetree/bindings/usb/atmel-usb.txt |   82 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi                  |   62 +++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts              |    5 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                   |   62 +++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi                 |    5 ++
 arch/arm/mach-at91/at91sam9g45.c                    |    2 +
 arch/arm/mach-at91/at91sam9x5.c                     |    2 +
 drivers/usb/gadget/Kconfig                          |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                 |  264 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----------------------------
 drivers/usb/gadget/atmel_usba_udc.h                 |    2 +
 10 files changed, 407 insertions(+), 81 deletions(-)

Best Regards,
J.


From catalin.marinas at arm.com  Mon May 20 12:26:26 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 17:26:26 +0100
Subject: [PATCH v4 10/32] arm64: KVM: CPU specific system registers
 handling
In-Reply-To: <1368540840-26750-11-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-11-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520162625.GJ3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:38PM +0100, Marc Zyngier wrote:
> Add the support code for CPU specific system registers. Not much
> here yet.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From itooo at itooo.com  Mon May 20 12:25:46 2013
From: itooo at itooo.com (Greg)
Date: Mon, 20 May 2013 18:25:46 +0200
Subject: mvebu: mbus device tree binding
In-Reply-To: <20130520124420.GA3030@localhost>
References: <20130520123153.GA2904@localhost> <20130520124420.GA3030@localhost>
Message-ID: <519A4E8A.80608@itooo.com>

Le 20/05/2013 14:44, Ezequiel Garcia a ?crit :
> Hi,
>
> Adding Jason to the discussion.
>
> On Mon, May 20, 2013 at 09:31:53AM -0300, Ezequiel Garcia wrote:
>> Hello Arnd and Jason,
>>
>> Let's advance with the DT binding for mvebu-mbus,
>> and perhaps have it ready for v3.11.
>>
>> Our current approach to the mbus-windows allocation is as follows:
>>
>> 1. Every device is located as a child of the soc/internal-regs node.
>>     The DT contains information for the assigned address space,
>>     encoded in the 'ranges' property, like this:
>>
>>     soc {
>>     
>>     	ranges =  < internal-regs
>>          	    PCIe
>> 		    NOR
>> 		    ... >;
>>     	internal-regs {
>> 		...
>>     	};
>>     }
>>
>>
>> 2. Each driver is in charge of allocating the mbus windows, using
>>     the mbus API and the address region obtained through the information
>>     on the device tree.
>>
>> Now, this approach is particularly error-prone because of (1). The
>> 'ranges' entry in a given .dtsi file is overrided by the 'ranges'
>> in the per-board .dts file. So, when if we need to declare a node for a
>> NOR device, we need to duplicate all ranges entries from the parent
>> .dtsi files.
>>
>> This does not seem to be hugely problematic, for one could put the
>> 'ranges' property only in the per-board files, and remove it from the
>> common dtsi.
>>
>> Therefore, first of all I'd like to know:
>>
>> **1** What's so broken with the current approach that makes us seek for
>>        solution, in the form of an mbus DT binding?
>>
>> In addition, reading the previous discussion you've had about this, I
>> noticed Arnd suggested (and even required) that the mbus binding should
>> update the ranges property in the DT blob each time an address window
>> is dynamically allocated.
>>
>> **2** Why is this required? Who will read the updated ranges
>>        information?
>>        Why can't the kernel access the mbus API to obtain information
>>        about currently allocated windows?
>>
>> Those are my questions for now and I'm quite sure many more will come
>> in the future, so please bare with me!
>>
I might be completely off-topic (I'm very new to the discussion) but 
here is my opinion : I would not to let the device drivers configure the 
MBUS if this is possible to avoid. I'd configure the MBUS globally and 
the drivers should just use whatever configuration is applied to the 
MBUS by calling the API.
This would allow a centralized configuration of the MBUS where it is 
easy to find mistakes and conflicts.
This would also place this configuration "deeper" in the DT files, most 
people will not really care about configuring this and don't even need 
to know about this, if this is "hidden" to them, they can focus on what 
they really need to do.

These questions will arise again when implementing the SERDES pins 
multiplexer I guess (I didn't see any code for this yet).

Cheers,


From marc.zyngier at arm.com  Mon May 20 12:27:23 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 20 May 2013 17:27:23 +0100
Subject: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend
In-Reply-To: <20130520162528.GI3639@MacBook-Pro.local>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-8-git-send-email-marc.zyngier@arm.com>
 <20130520155739.GF3639@MacBook-Pro.local> <519A4C9B.8070307@arm.com>
 <20130520162528.GI3639@MacBook-Pro.local>
Message-ID: <519A4EEB.5040206@arm.com>

On 20/05/13 17:25, Catalin Marinas wrote:
> On Mon, May 20, 2013 at 05:17:31PM +0100, Marc Zyngier wrote:
>> On 20/05/13 16:57, Catalin Marinas wrote:
>>> On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
>>>> +static inline bool kvm_is_write_fault(unsigned long esr)
>>>> +{
>>>> +	unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
>>>
>>> Not that it would make much difference but for consistency - we use esr
>>> as an 'unsigned int' in the arm64 code (only 32-bit needed).
>>
>> Indeed. Changing it would require a 32bit patch though, as I'd like to
>> keep the two code bases in line.
>>
>> If you don't mind, I'll queue a patch changing this to "unsigned int" on
>> both architectures once this is merged.
> 
> I'm OK if you push the patch afterwards, you can add my reviewed-by on
> this patch.

Sure, will do.

> Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From catalin.marinas at arm.com  Mon May 20 12:27:23 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 17:27:23 +0100
Subject: [PATCH v4 11/32] arm64: KVM: virtual CPU reset
In-Reply-To: <1368540840-26750-12-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-12-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520162723.GK3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:39PM +0100, Marc Zyngier wrote:
> Provide the reset code for a virtual CPU booted in 64bit mode.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Mon May 20 12:29:23 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 17:29:23 +0100
Subject: [PATCH v4 12/32] arm64: KVM: kvm_arch and kvm_vcpu_arch
 definitions
In-Reply-To: <1368540840-26750-13-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-13-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130520162922.GL3639@MacBook-Pro.local>

On Tue, May 14, 2013 at 03:13:40PM +0100, Marc Zyngier wrote:
> Provide the architecture dependent structures for VM and
> vcpu abstractions.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From plagnioj at jcrosoft.com  Mon May 20 12:25:45 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:45 +0200
Subject: [PATCH 1/7] USB: gadget: atmel_usba: move global struct usba_ep
 usba_ep to struct usba_udc
Message-ID: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>

so we can have multiple usb gadget instance

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/gadget/atmel_usba_udc.c |   20 +++++++++++---------
 drivers/usb/gadget/atmel_usba_udc.h |    1 +
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f2a970f..d2ffd04 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -29,7 +29,6 @@
 
 
 static struct usba_udc the_udc;
-static struct usba_ep *usba_ep;
 
 #ifdef CONFIG_USB_GADGET_DEBUG_FS
 #include <linux/debugfs.h>
@@ -1147,7 +1146,7 @@ static int do_test_mode(struct usba_udc *udc)
 		 * Test_SE0_NAK: Force high-speed mode and set up ep0
 		 * for Bulk IN transfers
 		 */
-		ep = &usba_ep[0];
+		ep = &udc->usba_ep[0];
 		usba_writel(udc, TST,
 				USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
 		usba_ep_writel(ep, CFG,
@@ -1165,7 +1164,7 @@ static int do_test_mode(struct usba_udc *udc)
 		break;
 	case 0x0400:
 		/* Test_Packet */
-		ep = &usba_ep[0];
+		ep = &udc->usba_ep[0];
 		usba_ep_writel(ep, CFG,
 				USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
 				| USBA_EPT_DIR_IN
@@ -1668,7 +1667,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
 
 		for (i = 1; i < USBA_NR_ENDPOINTS; i++)
 			if (dma_status & (1 << i))
-				usba_dma_irq(udc, &usba_ep[i]);
+				usba_dma_irq(udc, &udc->usba_ep[i]);
 	}
 
 	ep_status = USBA_BFEXT(EPT_INT, status);
@@ -1677,10 +1676,10 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
 
 		for (i = 0; i < USBA_NR_ENDPOINTS; i++)
 			if (ep_status & (1 << i)) {
-				if (ep_is_control(&usba_ep[i]))
-					usba_control_irq(udc, &usba_ep[i]);
+				if (ep_is_control(&udc->usba_ep[i]))
+					usba_control_irq(udc, &udc->usba_ep[i]);
 				else
-					usba_ep_irq(udc, &usba_ep[i]);
+					usba_ep_irq(udc, &udc->usba_ep[i]);
 			}
 	}
 
@@ -1705,7 +1704,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
 		DBG(DBG_BUS, "%s bus reset detected\n",
 		    usb_speed_string(udc->gadget.speed));
 
-		ep0 = &usba_ep[0];
+		ep0 = &udc->usba_ep[0];
 		ep0->ep.desc = &usba_ep0_desc;
 		ep0->state = WAIT_FOR_SETUP;
 		usba_ep_writel(ep0, CFG,
@@ -1841,6 +1840,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
 	struct usba_udc *udc = &the_udc;
+	static struct usba_ep *usba_ep;
 	int irq, ret, i;
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
@@ -1896,6 +1896,8 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	if (!usba_ep)
 		goto err_alloc_ep;
 
+	udc->usba_ep = usba_ep;
+
 	the_udc.gadget.ep0 = &usba_ep[0].ep;
 
 	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
@@ -2008,7 +2010,7 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 	usb_del_gadget_udc(&udc->gadget);
 
 	for (i = 1; i < pdata->num_ep; i++)
-		usba_ep_cleanup_debugfs(&usba_ep[i]);
+		usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
 	usba_cleanup_debugfs(udc);
 
 	if (gpio_is_valid(udc->vbus_pin)) {
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index d65a618..0841986 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -319,6 +319,7 @@ struct usba_udc {
 	int vbus_pin_inverted;
 	struct clk *pclk;
 	struct clk *hclk;
+	struct usba_ep *usba_ep;
 
 	u16 devstatus;
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:46 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:46 +0200
Subject: [PATCH 2/7] USB: gadget: atmel_usba: allow multi instance
In-Reply-To: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>
References: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067151-3178-2-git-send-email-plagnioj@jcrosoft.com>

drop static struct usba_udc the_udc

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/gadget/atmel_usba_udc.c |   36 +++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index d2ffd04..eea57a3 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -27,9 +27,6 @@
 
 #include "atmel_usba_udc.h"
 
-
-static struct usba_udc the_udc;
-
 #ifdef CONFIG_USB_GADGET_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/uaccess.h>
@@ -1013,16 +1010,13 @@ static void nop_release(struct device *dev)
 
 }
 
-static struct usba_udc the_udc = {
-	.gadget	= {
-		.ops		= &usba_udc_ops,
-		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
-		.max_speed	= USB_SPEED_HIGH,
-		.name		= "atmel_usba_udc",
-		.dev	= {
-			.init_name	= "gadget",
-			.release	= nop_release,
-		},
+struct usb_gadget usba_gadget_template = {
+	.ops		= &usba_udc_ops,
+	.max_speed	= USB_SPEED_HIGH,
+	.name		= "atmel_usba_udc",
+	.dev	= {
+		.init_name	= "gadget",
+		.release	= nop_release,
 	},
 };
 
@@ -1839,10 +1833,17 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	struct usba_platform_data *pdata = pdev->dev.platform_data;
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
-	struct usba_udc *udc = &the_udc;
+	struct usba_udc *udc;
 	static struct usba_ep *usba_ep;
 	int irq, ret, i;
 
+	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
+	if (!udc)
+		return -ENOMEM;
+
+	udc->gadget = usba_gadget_template;
+	INIT_LIST_HEAD(&udc->gadget.ep_list);
+
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
 	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
 	if (!regs || !fifo || !pdata)
@@ -1897,8 +1898,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_alloc_ep;
 
 	udc->usba_ep = usba_ep;
-
-	the_udc.gadget.ep0 = &usba_ep[0].ep;
+	udc->gadget.ep0 = &usba_ep[0].ep;
 
 	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
 	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
@@ -1907,7 +1907,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	usba_ep[0].ep.ops = &usba_ep_ops;
 	usba_ep[0].ep.name = pdata->ep[0].name;
 	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
-	usba_ep[0].udc = &the_udc;
+	usba_ep[0].udc = udc;
 	INIT_LIST_HEAD(&usba_ep[0].queue);
 	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
 	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
@@ -1924,7 +1924,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		ep->ep.ops = &usba_ep_ops;
 		ep->ep.name = pdata->ep[i].name;
 		ep->ep.maxpacket = pdata->ep[i].fifo_size;
-		ep->udc = &the_udc;
+		ep->udc = udc;
 		INIT_LIST_HEAD(&ep->queue);
 		ep->fifo_size = pdata->ep[i].fifo_size;
 		ep->nr_banks = pdata->ep[i].nr_banks;
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:48 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:48 +0200
Subject: [PATCH 4/7] ARM: at91: sam9x5 add udc DT support
In-Reply-To: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>
References: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067151-3178-4-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   62 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9x5.c   |    2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599..01a815d 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -645,6 +645,68 @@
 				status = "disabled";
 			};
 
+			usb2: gadget at f803c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00500000 0x80000
+				       0xf803c000 0x400>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+			};
+
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x40>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec..2abee66 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 
 /*
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:47 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:47 +0200
Subject: [PATCH 3/7] USB: gadget: atmel_usba: add DT support
In-Reply-To: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>
References: <1369067151-3178-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067151-3178-3-git-send-email-plagnioj@jcrosoft.com>

Allow to compile the driver all the time if AT91 enabled.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 .../devicetree/bindings/usb/atmel-usb.txt          |   82 ++++++++
 drivers/usb/gadget/Kconfig                         |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                |  220 ++++++++++++++------
 drivers/usb/gadget/atmel_usba_udc.h                |    1 +
 4 files changed, 245 insertions(+), 60 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 60bd215..55f51af 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -47,3 +47,85 @@ usb1: gadget at fffa4000 {
 	interrupts = <10 4>;
 	atmel,vbus-gpio = <&pioC 5 0>;
 };
+
+Atmel High-Speed USB device controller
+
+Required properties:
+ - compatible: Should be "atmel,at91sam9rl-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain usba interrupt
+ - ep childnode: To specify the number of endpoints and their properties.
+
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+Required child node properties:
+ - name: Name of the endpoint.
+ - reg: Num of the endpoint.
+ - atmel,fifo-size: Size of the fifo.
+ - atmel,nb-banks: Number of banks.
+ - atmel,can-dma: Boolean to specify if the endpoint support DMA.
+ - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
+
+usb2: gadget at fff78000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "atmel,at91sam9rl-udc";
+	reg = <0x00600000 0x80000
+	       0xfff78000 0x400>;
+	interrupts = <27 4 0>;
+	atmel,vbus-gpio = <&pioB 19 0>;
+
+	ep0 {
+		reg = <0>;
+		atmel,fifo-size = <64>;
+		atmel,nb-banks = <1>;
+	};
+
+	ep1 {
+		reg = <1>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep2 {
+		reg = <2>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep3 {
+		reg = <3>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+	};
+
+	ep4 {
+		reg = <4>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+	};
+
+	ep5 {
+		reg = <5>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep6 {
+		reg = <6>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 83300d9..5e47d50 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_LPC32XX
 
 config USB_ATMEL_USBA
 	tristate "Atmel USBA"
-	depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on AVR32 || ARCH_AT91
 	help
 	  USBA is the integrated high-speed USB Device controller on
 	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index eea57a3..f89ce5e 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -22,6 +22,8 @@
 #include <linux/usb/atmel_usba_udc.h>
 #include <linux/delay.h>
 #include <linux/platform_data/atmel.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 
 #include <asm/gpio.h>
 
@@ -1828,13 +1830,146 @@ static int atmel_usba_stop(struct usb_gadget *gadget,
 	return 0;
 }
 
-static int __init usba_udc_probe(struct platform_device *pdev)
+#ifdef CONFIG_OF
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	u32 val;
+	const char *name;
+	enum of_gpio_flags flags;
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *pp;
+	int i, ret;
+	struct usba_ep *eps, *ep;
+
+	udc->num_ep = 0;
+
+	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
+						&flags);
+	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+	pp = NULL;
+	while ((pp = of_get_next_child(np, pp)))
+		udc->num_ep++;
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	pp = NULL;
+	i = 0;
+	while ((pp = of_get_next_child(np, pp))) {
+		ep = &eps[i];
+
+		ret = of_property_read_u32(pp, "reg", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
+			goto err;
+		}
+		ep->index = val;
+
+		ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
+			goto err;
+		}
+		ep->fifo_size = val;
+
+		ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
+			goto err;
+		}
+		ep->nr_banks = val;
+
+		ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
+		ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
+
+		ret = of_property_read_string(pp, "name", &name);
+		ep->ep.name = name;
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.maxpacket = ep->fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+
+		i++;
+	}
+
+	return eps;
+err:
+	return ERR_PTR(ret);
+}
+#else
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	return ERR_PTR(-ENOSYS);
+}
+#endif
+
+static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
+						 struct usba_udc *udc)
 {
 	struct usba_platform_data *pdata = pdev->dev.platform_data;
+	struct usba_ep *eps;
+	int i;
+
+	if (!pdata)
+		return ERR_PTR(-ENXIO);
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	udc->vbus_pin = pdata->vbus_pin;
+	udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
+	udc->num_ep = pdata->num_ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	for (i = 0; i < pdata->num_ep; i++) {
+		struct usba_ep *ep = &eps[i];
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.name = pdata->ep[i].name;
+		ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+		ep->nr_banks = pdata->ep[i].nr_banks;
+		ep->index = pdata->ep[i].index;
+		ep->can_dma = pdata->ep[i].can_dma;
+		ep->can_isoc = pdata->ep[i].can_isoc;
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	}
+
+	return eps;
+}
+
+static int __init usba_udc_probe(struct platform_device *pdev)
+{
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
 	struct usba_udc *udc;
-	static struct usba_ep *usba_ep;
 	int irq, ret, i;
 
 	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
@@ -1846,7 +1981,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
 	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
-	if (!regs || !fifo || !pdata)
+	if (!regs || !fifo)
 		return -ENXIO;
 
 	irq = platform_get_irq(pdev, 0);
@@ -1892,47 +2027,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
 	clk_disable(pclk);
 
-	usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
-			  GFP_KERNEL);
-	if (!usba_ep)
-		goto err_alloc_ep;
-
-	udc->usba_ep = usba_ep;
-	udc->gadget.ep0 = &usba_ep[0].ep;
-
-	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
-	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
-	usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
-	usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
-	usba_ep[0].ep.ops = &usba_ep_ops;
-	usba_ep[0].ep.name = pdata->ep[0].name;
-	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
-	usba_ep[0].udc = udc;
-	INIT_LIST_HEAD(&usba_ep[0].queue);
-	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
-	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
-	usba_ep[0].index = pdata->ep[0].index;
-	usba_ep[0].can_dma = pdata->ep[0].can_dma;
-	usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
-
-	for (i = 1; i < pdata->num_ep; i++) {
-		struct usba_ep *ep = &usba_ep[i];
-
-		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
-		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
-		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
-		ep->ep.ops = &usba_ep_ops;
-		ep->ep.name = pdata->ep[i].name;
-		ep->ep.maxpacket = pdata->ep[i].fifo_size;
-		ep->udc = udc;
-		INIT_LIST_HEAD(&ep->queue);
-		ep->fifo_size = pdata->ep[i].fifo_size;
-		ep->nr_banks = pdata->ep[i].nr_banks;
-		ep->index = pdata->ep[i].index;
-		ep->can_dma = pdata->ep[i].can_dma;
-		ep->can_isoc = pdata->ep[i].can_isoc;
+	if (pdev->dev.of_node)
+		udc->usba_ep = atmel_udc_of_init(pdev, udc);
+	else
+		udc->usba_ep = usba_udc_pdata(pdev, udc);
 
-		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	if (IS_ERR(udc->usba_ep)) {
+		ret = PTR_ERR(udc->usba_ep);
+		goto err_alloc_ep;
 	}
 
 	ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
@@ -1943,16 +2045,12 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	}
 	udc->irq = irq;
 
-	if (gpio_is_valid(pdata->vbus_pin)) {
-		if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
-			udc->vbus_pin = pdata->vbus_pin;
-			udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
-
+	if (gpio_is_valid(udc->vbus_pin)) {
+		if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
 			ret = request_irq(gpio_to_irq(udc->vbus_pin),
 					usba_vbus_irq, 0,
 					"atmel_usba_udc", udc);
 			if (ret) {
-				gpio_free(udc->vbus_pin);
 				udc->vbus_pin = -ENODEV;
 				dev_warn(&udc->pdev->dev,
 					 "failed to request vbus irq; "
@@ -1971,20 +2069,17 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_add_udc;
 
 	usba_init_debugfs(udc);
-	for (i = 1; i < pdata->num_ep; i++)
-		usba_ep_init_debugfs(udc, &usba_ep[i]);
+	for (i = 1; i < udc->num_ep; i++)
+		usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
 
 	return 0;
 
 err_add_udc:
-	if (gpio_is_valid(pdata->vbus_pin)) {
+	if (gpio_is_valid(udc->vbus_pin))
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
-		gpio_free(udc->vbus_pin);
-	}
 
 	free_irq(irq, udc);
 err_request_irq:
-	kfree(usba_ep);
 err_alloc_ep:
 	iounmap(udc->fifo);
 err_map_fifo:
@@ -2003,23 +2098,20 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 {
 	struct usba_udc *udc;
 	int i;
-	struct usba_platform_data *pdata = pdev->dev.platform_data;
 
 	udc = platform_get_drvdata(pdev);
 
 	usb_del_gadget_udc(&udc->gadget);
 
-	for (i = 1; i < pdata->num_ep; i++)
+	for (i = 1; i < udc->num_ep; i++)
 		usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
 	usba_cleanup_debugfs(udc);
 
 	if (gpio_is_valid(udc->vbus_pin)) {
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
-		gpio_free(udc->vbus_pin);
 	}
 
 	free_irq(udc->irq, udc);
-	kfree(usba_ep);
 	iounmap(udc->fifo);
 	iounmap(udc->regs);
 	clk_put(udc->hclk);
@@ -2028,11 +2120,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_udc_dt_ids[] = {
+	{ .compatible = "atmel,at91sam9rl-udc" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
+#endif
+
 static struct platform_driver udc_driver = {
 	.remove		= __exit_p(usba_udc_remove),
 	.driver		= {
 		.name		= "atmel_usba_udc",
 		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_udc_dt_ids),
 	},
 };
 
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index 0841986..2922db5 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -317,6 +317,7 @@ struct usba_udc {
 	int irq;
 	int vbus_pin;
 	int vbus_pin_inverted;
+	int num_ep;
 	struct clk *pclk;
 	struct clk *hclk;
 	struct usba_ep *usba_ep;
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:55 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:55 +0200
Subject: [PATCH 2/7] USB: gadget: atmel_usba: allow multi instance
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067160-3230-2-git-send-email-plagnioj@jcrosoft.com>

drop static struct usba_udc the_udc

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/gadget/atmel_usba_udc.c |   36 +++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index d2ffd04..eea57a3 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -27,9 +27,6 @@
 
 #include "atmel_usba_udc.h"
 
-
-static struct usba_udc the_udc;
-
 #ifdef CONFIG_USB_GADGET_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/uaccess.h>
@@ -1013,16 +1010,13 @@ static void nop_release(struct device *dev)
 
 }
 
-static struct usba_udc the_udc = {
-	.gadget	= {
-		.ops		= &usba_udc_ops,
-		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
-		.max_speed	= USB_SPEED_HIGH,
-		.name		= "atmel_usba_udc",
-		.dev	= {
-			.init_name	= "gadget",
-			.release	= nop_release,
-		},
+struct usb_gadget usba_gadget_template = {
+	.ops		= &usba_udc_ops,
+	.max_speed	= USB_SPEED_HIGH,
+	.name		= "atmel_usba_udc",
+	.dev	= {
+		.init_name	= "gadget",
+		.release	= nop_release,
 	},
 };
 
@@ -1839,10 +1833,17 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	struct usba_platform_data *pdata = pdev->dev.platform_data;
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
-	struct usba_udc *udc = &the_udc;
+	struct usba_udc *udc;
 	static struct usba_ep *usba_ep;
 	int irq, ret, i;
 
+	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
+	if (!udc)
+		return -ENOMEM;
+
+	udc->gadget = usba_gadget_template;
+	INIT_LIST_HEAD(&udc->gadget.ep_list);
+
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
 	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
 	if (!regs || !fifo || !pdata)
@@ -1897,8 +1898,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_alloc_ep;
 
 	udc->usba_ep = usba_ep;
-
-	the_udc.gadget.ep0 = &usba_ep[0].ep;
+	udc->gadget.ep0 = &usba_ep[0].ep;
 
 	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
 	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
@@ -1907,7 +1907,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	usba_ep[0].ep.ops = &usba_ep_ops;
 	usba_ep[0].ep.name = pdata->ep[0].name;
 	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
-	usba_ep[0].udc = &the_udc;
+	usba_ep[0].udc = udc;
 	INIT_LIST_HEAD(&usba_ep[0].queue);
 	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
 	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
@@ -1924,7 +1924,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		ep->ep.ops = &usba_ep_ops;
 		ep->ep.name = pdata->ep[i].name;
 		ep->ep.maxpacket = pdata->ep[i].fifo_size;
-		ep->udc = &the_udc;
+		ep->udc = udc;
 		INIT_LIST_HEAD(&ep->queue);
 		ep->fifo_size = pdata->ep[i].fifo_size;
 		ep->nr_banks = pdata->ep[i].nr_banks;
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:58 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:58 +0200
Subject: [PATCH 5/7] ARM: at91: sam9x5ek add udc DT support
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067160-3230-5-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5ek.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 19c8ebb..5e10027 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -52,6 +52,11 @@
 				status = "okay";
 			};
 
+			usb2: gadget at f803c000 {
+				atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
+
 			i2c0: i2c at f8010000 {
 				status = "okay";
 			};
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:56 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:56 +0200
Subject: [PATCH 3/7] USB: gadget: atmel_usba: add DT support
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067160-3230-3-git-send-email-plagnioj@jcrosoft.com>

Allow to compile the driver all the time if AT91 enabled.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 .../devicetree/bindings/usb/atmel-usb.txt          |   82 ++++++++
 drivers/usb/gadget/Kconfig                         |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                |  220 ++++++++++++++------
 drivers/usb/gadget/atmel_usba_udc.h                |    1 +
 4 files changed, 245 insertions(+), 60 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 60bd215..55f51af 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -47,3 +47,85 @@ usb1: gadget at fffa4000 {
 	interrupts = <10 4>;
 	atmel,vbus-gpio = <&pioC 5 0>;
 };
+
+Atmel High-Speed USB device controller
+
+Required properties:
+ - compatible: Should be "atmel,at91sam9rl-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain usba interrupt
+ - ep childnode: To specify the number of endpoints and their properties.
+
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+Required child node properties:
+ - name: Name of the endpoint.
+ - reg: Num of the endpoint.
+ - atmel,fifo-size: Size of the fifo.
+ - atmel,nb-banks: Number of banks.
+ - atmel,can-dma: Boolean to specify if the endpoint support DMA.
+ - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
+
+usb2: gadget at fff78000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "atmel,at91sam9rl-udc";
+	reg = <0x00600000 0x80000
+	       0xfff78000 0x400>;
+	interrupts = <27 4 0>;
+	atmel,vbus-gpio = <&pioB 19 0>;
+
+	ep0 {
+		reg = <0>;
+		atmel,fifo-size = <64>;
+		atmel,nb-banks = <1>;
+	};
+
+	ep1 {
+		reg = <1>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep2 {
+		reg = <2>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep3 {
+		reg = <3>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+	};
+
+	ep4 {
+		reg = <4>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+	};
+
+	ep5 {
+		reg = <5>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+
+	ep6 {
+		reg = <6>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma;
+		atmel,can-isoc;
+	};
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 83300d9..5e47d50 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_LPC32XX
 
 config USB_ATMEL_USBA
 	tristate "Atmel USBA"
-	depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on AVR32 || ARCH_AT91
 	help
 	  USBA is the integrated high-speed USB Device controller on
 	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index eea57a3..f89ce5e 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -22,6 +22,8 @@
 #include <linux/usb/atmel_usba_udc.h>
 #include <linux/delay.h>
 #include <linux/platform_data/atmel.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 
 #include <asm/gpio.h>
 
@@ -1828,13 +1830,146 @@ static int atmel_usba_stop(struct usb_gadget *gadget,
 	return 0;
 }
 
-static int __init usba_udc_probe(struct platform_device *pdev)
+#ifdef CONFIG_OF
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	u32 val;
+	const char *name;
+	enum of_gpio_flags flags;
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *pp;
+	int i, ret;
+	struct usba_ep *eps, *ep;
+
+	udc->num_ep = 0;
+
+	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
+						&flags);
+	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+	pp = NULL;
+	while ((pp = of_get_next_child(np, pp)))
+		udc->num_ep++;
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	pp = NULL;
+	i = 0;
+	while ((pp = of_get_next_child(np, pp))) {
+		ep = &eps[i];
+
+		ret = of_property_read_u32(pp, "reg", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
+			goto err;
+		}
+		ep->index = val;
+
+		ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
+			goto err;
+		}
+		ep->fifo_size = val;
+
+		ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
+			goto err;
+		}
+		ep->nr_banks = val;
+
+		ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
+		ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
+
+		ret = of_property_read_string(pp, "name", &name);
+		ep->ep.name = name;
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.maxpacket = ep->fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+
+		i++;
+	}
+
+	return eps;
+err:
+	return ERR_PTR(ret);
+}
+#else
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	return ERR_PTR(-ENOSYS);
+}
+#endif
+
+static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
+						 struct usba_udc *udc)
 {
 	struct usba_platform_data *pdata = pdev->dev.platform_data;
+	struct usba_ep *eps;
+	int i;
+
+	if (!pdata)
+		return ERR_PTR(-ENXIO);
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	udc->vbus_pin = pdata->vbus_pin;
+	udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
+	udc->num_ep = pdata->num_ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	for (i = 0; i < pdata->num_ep; i++) {
+		struct usba_ep *ep = &eps[i];
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.name = pdata->ep[i].name;
+		ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+		ep->nr_banks = pdata->ep[i].nr_banks;
+		ep->index = pdata->ep[i].index;
+		ep->can_dma = pdata->ep[i].can_dma;
+		ep->can_isoc = pdata->ep[i].can_isoc;
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	}
+
+	return eps;
+}
+
+static int __init usba_udc_probe(struct platform_device *pdev)
+{
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
 	struct usba_udc *udc;
-	static struct usba_ep *usba_ep;
 	int irq, ret, i;
 
 	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
@@ -1846,7 +1981,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
 	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
-	if (!regs || !fifo || !pdata)
+	if (!regs || !fifo)
 		return -ENXIO;
 
 	irq = platform_get_irq(pdev, 0);
@@ -1892,47 +2027,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
 	clk_disable(pclk);
 
-	usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
-			  GFP_KERNEL);
-	if (!usba_ep)
-		goto err_alloc_ep;
-
-	udc->usba_ep = usba_ep;
-	udc->gadget.ep0 = &usba_ep[0].ep;
-
-	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
-	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
-	usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
-	usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
-	usba_ep[0].ep.ops = &usba_ep_ops;
-	usba_ep[0].ep.name = pdata->ep[0].name;
-	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
-	usba_ep[0].udc = udc;
-	INIT_LIST_HEAD(&usba_ep[0].queue);
-	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
-	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
-	usba_ep[0].index = pdata->ep[0].index;
-	usba_ep[0].can_dma = pdata->ep[0].can_dma;
-	usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
-
-	for (i = 1; i < pdata->num_ep; i++) {
-		struct usba_ep *ep = &usba_ep[i];
-
-		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
-		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
-		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
-		ep->ep.ops = &usba_ep_ops;
-		ep->ep.name = pdata->ep[i].name;
-		ep->ep.maxpacket = pdata->ep[i].fifo_size;
-		ep->udc = udc;
-		INIT_LIST_HEAD(&ep->queue);
-		ep->fifo_size = pdata->ep[i].fifo_size;
-		ep->nr_banks = pdata->ep[i].nr_banks;
-		ep->index = pdata->ep[i].index;
-		ep->can_dma = pdata->ep[i].can_dma;
-		ep->can_isoc = pdata->ep[i].can_isoc;
+	if (pdev->dev.of_node)
+		udc->usba_ep = atmel_udc_of_init(pdev, udc);
+	else
+		udc->usba_ep = usba_udc_pdata(pdev, udc);
 
-		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	if (IS_ERR(udc->usba_ep)) {
+		ret = PTR_ERR(udc->usba_ep);
+		goto err_alloc_ep;
 	}
 
 	ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
@@ -1943,16 +2045,12 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	}
 	udc->irq = irq;
 
-	if (gpio_is_valid(pdata->vbus_pin)) {
-		if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
-			udc->vbus_pin = pdata->vbus_pin;
-			udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
-
+	if (gpio_is_valid(udc->vbus_pin)) {
+		if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
 			ret = request_irq(gpio_to_irq(udc->vbus_pin),
 					usba_vbus_irq, 0,
 					"atmel_usba_udc", udc);
 			if (ret) {
-				gpio_free(udc->vbus_pin);
 				udc->vbus_pin = -ENODEV;
 				dev_warn(&udc->pdev->dev,
 					 "failed to request vbus irq; "
@@ -1971,20 +2069,17 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_add_udc;
 
 	usba_init_debugfs(udc);
-	for (i = 1; i < pdata->num_ep; i++)
-		usba_ep_init_debugfs(udc, &usba_ep[i]);
+	for (i = 1; i < udc->num_ep; i++)
+		usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
 
 	return 0;
 
 err_add_udc:
-	if (gpio_is_valid(pdata->vbus_pin)) {
+	if (gpio_is_valid(udc->vbus_pin))
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
-		gpio_free(udc->vbus_pin);
-	}
 
 	free_irq(irq, udc);
 err_request_irq:
-	kfree(usba_ep);
 err_alloc_ep:
 	iounmap(udc->fifo);
 err_map_fifo:
@@ -2003,23 +2098,20 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 {
 	struct usba_udc *udc;
 	int i;
-	struct usba_platform_data *pdata = pdev->dev.platform_data;
 
 	udc = platform_get_drvdata(pdev);
 
 	usb_del_gadget_udc(&udc->gadget);
 
-	for (i = 1; i < pdata->num_ep; i++)
+	for (i = 1; i < udc->num_ep; i++)
 		usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
 	usba_cleanup_debugfs(udc);
 
 	if (gpio_is_valid(udc->vbus_pin)) {
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
-		gpio_free(udc->vbus_pin);
 	}
 
 	free_irq(udc->irq, udc);
-	kfree(usba_ep);
 	iounmap(udc->fifo);
 	iounmap(udc->regs);
 	clk_put(udc->hclk);
@@ -2028,11 +2120,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_udc_dt_ids[] = {
+	{ .compatible = "atmel,at91sam9rl-udc" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
+#endif
+
 static struct platform_driver udc_driver = {
 	.remove		= __exit_p(usba_udc_remove),
 	.driver		= {
 		.name		= "atmel_usba_udc",
 		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_udc_dt_ids),
 	},
 };
 
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index 0841986..2922db5 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -317,6 +317,7 @@ struct usba_udc {
 	int irq;
 	int vbus_pin;
 	int vbus_pin_inverted;
+	int num_ep;
 	struct clk *pclk;
 	struct clk *hclk;
 	struct usba_ep *usba_ep;
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:59 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:59 +0200
Subject: [PATCH 6/7] ARM: at91: sam9g45 add udc DT support
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067160-3230-6-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g45.dtsi |   62 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9g45.c   |    2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index f0091af..fccc488 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -582,6 +582,68 @@
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
+
+			usb2: gadget at fff78000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00600000 0x80000
+				       0xfff78000 0x400>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..95a418a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+	CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:54 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:54 +0200
Subject: [PATCH 1/7] USB: gadget: atmel_usba: move global struct usba_ep
 usba_ep to struct usba_udc
In-Reply-To: <20130520162149.GC9937@game.jcrosoft.org>
References: <20130520162149.GC9937@game.jcrosoft.org>
Message-ID: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>

so we can have multiple usb gadget instance

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/gadget/atmel_usba_udc.c |   20 +++++++++++---------
 drivers/usb/gadget/atmel_usba_udc.h |    1 +
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f2a970f..d2ffd04 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -29,7 +29,6 @@
 
 
 static struct usba_udc the_udc;
-static struct usba_ep *usba_ep;
 
 #ifdef CONFIG_USB_GADGET_DEBUG_FS
 #include <linux/debugfs.h>
@@ -1147,7 +1146,7 @@ static int do_test_mode(struct usba_udc *udc)
 		 * Test_SE0_NAK: Force high-speed mode and set up ep0
 		 * for Bulk IN transfers
 		 */
-		ep = &usba_ep[0];
+		ep = &udc->usba_ep[0];
 		usba_writel(udc, TST,
 				USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
 		usba_ep_writel(ep, CFG,
@@ -1165,7 +1164,7 @@ static int do_test_mode(struct usba_udc *udc)
 		break;
 	case 0x0400:
 		/* Test_Packet */
-		ep = &usba_ep[0];
+		ep = &udc->usba_ep[0];
 		usba_ep_writel(ep, CFG,
 				USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
 				| USBA_EPT_DIR_IN
@@ -1668,7 +1667,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
 
 		for (i = 1; i < USBA_NR_ENDPOINTS; i++)
 			if (dma_status & (1 << i))
-				usba_dma_irq(udc, &usba_ep[i]);
+				usba_dma_irq(udc, &udc->usba_ep[i]);
 	}
 
 	ep_status = USBA_BFEXT(EPT_INT, status);
@@ -1677,10 +1676,10 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
 
 		for (i = 0; i < USBA_NR_ENDPOINTS; i++)
 			if (ep_status & (1 << i)) {
-				if (ep_is_control(&usba_ep[i]))
-					usba_control_irq(udc, &usba_ep[i]);
+				if (ep_is_control(&udc->usba_ep[i]))
+					usba_control_irq(udc, &udc->usba_ep[i]);
 				else
-					usba_ep_irq(udc, &usba_ep[i]);
+					usba_ep_irq(udc, &udc->usba_ep[i]);
 			}
 	}
 
@@ -1705,7 +1704,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
 		DBG(DBG_BUS, "%s bus reset detected\n",
 		    usb_speed_string(udc->gadget.speed));
 
-		ep0 = &usba_ep[0];
+		ep0 = &udc->usba_ep[0];
 		ep0->ep.desc = &usba_ep0_desc;
 		ep0->state = WAIT_FOR_SETUP;
 		usba_ep_writel(ep0, CFG,
@@ -1841,6 +1840,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
 	struct usba_udc *udc = &the_udc;
+	static struct usba_ep *usba_ep;
 	int irq, ret, i;
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
@@ -1896,6 +1896,8 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	if (!usba_ep)
 		goto err_alloc_ep;
 
+	udc->usba_ep = usba_ep;
+
 	the_udc.gadget.ep0 = &usba_ep[0].ep;
 
 	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
@@ -2008,7 +2010,7 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 	usb_del_gadget_udc(&udc->gadget);
 
 	for (i = 1; i < pdata->num_ep; i++)
-		usba_ep_cleanup_debugfs(&usba_ep[i]);
+		usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
 	usba_cleanup_debugfs(udc);
 
 	if (gpio_is_valid(udc->vbus_pin)) {
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index d65a618..0841986 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -319,6 +319,7 @@ struct usba_udc {
 	int vbus_pin_inverted;
 	struct clk *pclk;
 	struct clk *hclk;
+	struct usba_ep *usba_ep;
 
 	u16 devstatus;
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon May 20 12:25:57 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:25:57 +0200
Subject: [PATCH 4/7] ARM: at91: sam9x5 add udc DT support
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067160-3230-4-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   62 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9x5.c   |    2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599..01a815d 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -645,6 +645,68 @@
 				status = "disabled";
 			};
 
+			usb2: gadget at f803c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00500000 0x80000
+				       0xf803c000 0x400>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+			};
+
 			rtc at fffffeb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffeb0 0x40>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec..2abee66 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 
 /*
-- 
1.7.10.4



From linux at arm.linux.org.uk  Mon May 20 12:31:18 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 May 2013 17:31:18 +0100
Subject: [PATCH] include/linux/posix_acl.h: need 'return NULL' when
 BUG(), if neither CONFIG_BUG nor HAVE_ARCH_BUG is defined.
In-Reply-To: <97dada79-cd78-4799-8f18-ed2bf8eee508@email.android.com>
References: <5199DBE2.5080707@asianux.com>
 <97dada79-cd78-4799-8f18-ed2bf8eee508@email.android.com>
Message-ID: <20130520163118.GX18614@n2100.arm.linux.org.uk>

On Mon, May 20, 2013 at 07:40:24AM -0700, Eric W. Biederman wrote:
> Seriously?  The correct fix it would seem is to give a useful default BUG
> definition.  Say *NULL.

Absolutely.

The real question is... how is this happening.  I've seen it occasionally
in the randconfig builds - though I don't have any logs to hand which
show that in the build system at the moment.  So, looking at the files:

arch/arm/include/asm/bug.h:
#ifdef CONFIG_BUG
#define BUG() _BUG(__FILE__, __LINE__, BUG_INSTR_VALUE)
#define _BUG(file, line, value) __BUG(file, line, value)
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define __BUG(__file, __line, __value)                          \
...
        unreachable();                                          \
...
#else  /* not CONFIG_DEBUG_BUGVERBOSE */
#define __BUG(__file, __line, __value)                          \
...
        unreachable();                                          \
...
#endif  /* CONFIG_DEBUG_BUGVERBOSE */

#define HAVE_ARCH_BUG
#endif  /* CONFIG_BUG */

#include <asm-generic/bug.h>

So here, whenever we have CONFIG_BUG enabled, we always define a non-empty
BUG() macro to override the generic version.  So far so good.

include/asm-generic/bug.h:

#ifdef CONFIG_BUG
... we're providing our own version ...

#else /* !CONFIG_BUG */
#ifndef HAVE_ARCH_BUG
#define BUG() do {} while(0)
#endif

#ifndef HAVE_ARCH_BUG_ON
#define BUG_ON(condition) do { if (condition) ; } while(0)
#endif

So, the generic stuff becomes no-ops which just fall through.  Seriously?
Is this really what we want?

So either we need to fix the generic bug.h code, or fix every site which
uses BUG()/BUG_ON().

Note - I'm not saying *NULL as you did, because that isn't guaranteed to
fault on all platforms.  NoMMU may allow *NULL to succeed without causing
an exception.


From plagnioj at jcrosoft.com  Mon May 20 12:26:00 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 May 2013 18:26:00 +0200
Subject: [PATCH 7/7] ARM: at91: sam9m10g45ek add udc DT support
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369067160-3230-7-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 89c50d1..17665ef 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -112,6 +112,11 @@
 					reg = <0>;
 				};
 			};
+
+			usb2: gadget at fff78000 {
+				atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.10.4



From kgene.kim at samsung.com  Mon May 20 12:38:23 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 01:38:23 +0900
Subject: [PATCH 30/33] arch/arm/plat-samsung: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-31-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
 <1368702961-4325-31-git-send-email-wsa@the-dreams.de>
Message-ID: <519A517F.5020003@samsung.com>

On 05/16/13 20:15, Wolfram Sang wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang<wsa at the-dreams.de>

Looks good to me, applied into Samsung tree.

Wolfram, if you want to take this into your tree, let me know.

Thanks.

- Kukjin

> ---
>   arch/arm/plat-samsung/adc.c |    5 -----
>   1 file changed, 5 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> index ca07cb1..79690f2 100644
> --- a/arch/arm/plat-samsung/adc.c
> +++ b/arch/arm/plat-samsung/adc.c
> @@ -381,11 +381,6 @@ static int s3c_adc_probe(struct platform_device *pdev)
>   	}
>
>   	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!regs) {
> -		dev_err(dev, "failed to find registers\n");
> -		return -ENXIO;
> -	}
> -
>   	adc->regs = devm_ioremap_resource(dev, regs);
>   	if (IS_ERR(adc->regs))
>   		return PTR_ERR(adc->regs);



From bkuhn at sfconservancy.org  Mon May 20 11:13:00 2013
From: bkuhn at sfconservancy.org (Bradley M. Kuhn)
Date: Mon, 20 May 2013 11:13:00 -0400
Subject: Would like to form a pool of Linux copyright holders for faster
 GPL enforcement against Anthrax Kernels
In-Reply-To: <51973B45.7040209@gmail.com> (Eric Appleman's message of "Sat, 18
 May 2013 04:26:45 -0400")
References: <51973B45.7040209@gmail.com>
Message-ID: <87a9npvg5f.fsf@ebb.org>

Eric Appleman wrote at 04:26 (EDT) on Saturday:
> Would anyone be interested in forming such a pool? I am willing to
> wait years for this to be resolved through certain organizations, but
> I believe we can do better.

As some on these lists likely already know, Conservancy's GPL Compliance
Project for Linux Developers [0] is aware of this matter and is
considering what actions to take, and how such actions should be ranked
in priority given the queue of the hundreds of known GPL violations on
Linux occurring every day.

We very much appreciate that Eric has brought the matter to our
attention and I'm continuing to correspond with Eric privately in the
hopes that we can resolve the matter.

If anyone wants to join Conservancy's GPL Compliance Project for Linux
Developers, please do contact me!

[0] More details on Conservancy's GPL Compliance Project for Linux
    Developers can be found at
    https://sfconservancy.org/news/2012/may/29/compliance/

Sincerely,
-- 
Bradley M. Kuhn, Executive Director, Software Freedom Conservancy


From kgene.kim at samsung.com  Mon May 20 12:40:46 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 01:40:46 +0900
Subject: [PATCH 08/33] drivers/i2c/busses: don't check resource with
 devm_ioremap_resource
In-Reply-To: <1368702961-4325-9-git-send-email-wsa@the-dreams.de>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
 <1368702961-4325-9-git-send-email-wsa@the-dreams.de>
Message-ID: <519A520E.3060801@samsung.com>

On 05/16/13 20:15, Wolfram Sang wrote:
> devm_ioremap_resource does sanity checks on the given resource. No need to
> duplicate this in the driver.
>
> Signed-off-by: Wolfram Sang<wsa at the-dreams.de>

For i2c-s3c2410:
Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks.

- Kukjin

> ---
>   drivers/i2c/busses/i2c-s3c2410.c |    5 -----
>   drivers/i2c/busses/i2c-sirf.c    |    6 ------
>   drivers/i2c/busses/i2c-tegra.c   |    5 -----
>   3 files changed, 16 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
> index 6e8ee92..cab1c91 100644
> --- a/drivers/i2c/busses/i2c-s3c2410.c
> +++ b/drivers/i2c/busses/i2c-s3c2410.c
> @@ -1082,11 +1082,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
>   	/* map the registers */
>
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (res == NULL) {
> -		dev_err(&pdev->dev, "cannot find IO resource\n");
> -		return -ENOENT;
> -	}
> -
>   	i2c->regs = devm_ioremap_resource(&pdev->dev, res);
>
>   	if (IS_ERR(i2c->regs))
> diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c
> index 5a7ad24..a63c7d5 100644
> --- a/drivers/i2c/busses/i2c-sirf.c
> +++ b/drivers/i2c/busses/i2c-sirf.c
> @@ -303,12 +303,6 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
>   	adap->class = I2C_CLASS_HWMON;
>
>   	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (mem_res == NULL) {
> -		dev_err(&pdev->dev, "Unable to get MEM resource\n");
> -		err = -EINVAL;
> -		goto out;
> -	}
> -
>   	siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
>   	if (IS_ERR(siic->base)) {
>   		err = PTR_ERR(siic->base);
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index b60ff90..9aa1b60 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -714,11 +714,6 @@ static int tegra_i2c_probe(struct platform_device *pdev)
>   	int ret = 0;
>
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(&pdev->dev, "no mem resource\n");
> -		return -EINVAL;
> -	}
> -
>   	base = devm_ioremap_resource(&pdev->dev, res);
>   	if (IS_ERR(base))
>   		return PTR_ERR(base);


From jason at lakedaemon.net  Mon May 20 13:08:16 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:08:16 -0400
Subject: [PATCHv10 2/9] of/pci: Provide support for parsing PCI DT
 ranges property
In-Reply-To: <CACRpkdamm9vh_bXenJigwTYmN=n_SsEp+GQqAe9rdm8PRxPsqw@mail.gmail.com>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-3-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130519203156.GO11137@titan.lakedaemon.net>
 <CACRpkdamm9vh_bXenJigwTYmN=n_SsEp+GQqAe9rdm8PRxPsqw@mail.gmail.com>
Message-ID: <20130520170816.GU31290@titan.lakedaemon.net>

On Mon, May 20, 2013 at 09:03:00AM +0200, Linus Walleij wrote:
> On Sun, May 19, 2013 at 10:31 PM, Jason Cooper <jason at lakedaemon.net> wrote:
> 
> > patches 2, 3, and 4 applied to mvebu/of_pci to facilitate others
> > (LinusW) basing their work off of it.
> 
> Thanks, is this going to be pulled into ARM SoC soon-ish?
> 
> I think Arnd may need this for some PCI work too.

I was half expecting -rc2 to drop yesterday.  Since it didn't, I'll go
ahead and send another round of PRs, including this one.  Probably today
or tomorrow.

thx,

Jason.


From tony at atomide.com  Mon May 20 13:08:28 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 20 May 2013 10:08:28 -0700
Subject: [PATCH] ARM: OMAP2+: Fix multiple randconfig errors if no SoC
 is selected, take3
In-Reply-To: <20130517210317.GB10378@atomide.com>
References: <20130517210317.GB10378@atomide.com>
Message-ID: <20130520170827.GF10378@atomide.com>

* Tony Lindgren <tony at atomide.com> [130517 14:08]:
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -6,7 +6,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>  	-I$(srctree)/arch/arm/plat-omap/include
>  
>  # Common support
> -obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
> +soc-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
>  	 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
>  	 omap_device.o sram.o
>  
> @@ -85,7 +85,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
>  obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
>  obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o
>  obj-$(CONFIG_SOC_OMAP5)			+= omap-mpuss-lowpower.o
> -obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
> +pm-$(CONFIG_ARCH_OMAP)			+= pm-debug.o
> +obj-$(CONFIG_PM_DEBUG)			+= $(pm-y)
>  
>  obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o
>  obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
> @@ -201,7 +202,8 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
>  
>  # EMU peripherals
>  obj-$(CONFIG_OMAP3_EMU)			+= emu.o
> -obj-$(CONFIG_HW_PERF_EVENTS)		+= pmu.o
> +pmu-$(CONFIG_ARCH_OMAP)			+= pmu.o
> +obj-$(CONFIG_HW_PERF_EVENTS)		+= $(pmu-y)
>  
>  obj-$(CONFIG_OMAP_MBOX_FWK)		+= mailbox_mach.o
>  mailbox_mach-objs			:= mailbox.o

Oops, both pm-debug.o and pmu.o should now be just:

soc-$(CONFIG_PM_DEBUG)			+= pm-debug.o
soc-$(CONFIG_ARCH_OMAP)			+= pmu.o

Will repost after running make randconfig for few hours today.

Regards,

Tony


From wsa at the-dreams.de  Mon May 20 13:11:22 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Mon, 20 May 2013 19:11:22 +0200
Subject: [PATCH 30/33] arch/arm/plat-samsung: don't check resource with
 devm_ioremap_resource
In-Reply-To: <519A517F.5020003@samsung.com>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
 <1368702961-4325-31-git-send-email-wsa@the-dreams.de>
 <519A517F.5020003@samsung.com>
Message-ID: <20130520171118.GA5717@katana>

On Tue, May 21, 2013 at 01:38:23AM +0900, Kukjin Kim wrote:
> On 05/16/13 20:15, Wolfram Sang wrote:
> >devm_ioremap_resource does sanity checks on the given resource. No need to
> >duplicate this in the driver.
> >
> >Signed-off-by: Wolfram Sang<wsa at the-dreams.de>
> 
> Looks good to me, applied into Samsung tree.
> 
> Wolfram, if you want to take this into your tree, let me know.

It is already upstream :)



From tony at atomide.com  Mon May 20 13:10:16 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 20 May 2013 10:10:16 -0700
Subject: [PATCH 1/6] ARM: OMAP2+: Remove board-4430sdp.c
In-Reply-To: <20130520095447.GR21614@n2100.arm.linux.org.uk>
References: <20130517191304.468.73487.stgit@localhost>
 <20130517191751.468.89202.stgit@localhost>
 <20130520095447.GR21614@n2100.arm.linux.org.uk>
Message-ID: <20130520171012.GG10378@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [130520 03:00]:
> On Fri, May 17, 2013 at 12:17:51PM -0700, Tony Lindgren wrote:
> > We can now boot with device tree. If you don't want to update u-boot,
> > you can boot with appended DTB with the following instructions:
> > 
> > 1. Make sure you have the appended DTB support in .config
> > 
> >    CONFIG_ARM_APPENDED_DTB=y
> >    CONFIG_ARM_ATAG_DTB_COMPAT=y
> >    CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y
> > 
> > 2. Build the zImage
> > 
> >    $ ARCH=arm CROSS_COMPILE=... make zImage
> > 
> > 3. Build the device tree blobs
> > 
> >    $ ARCH=arm CROSS_COMPILE=... make dtbs
> > 
> > 4. Append the dtb to zImage
> > 
> >    $ cat arch/arm/boot/zImage arch/arm/boot/dts/omap4-sdp.dtb > /tmp/appended
> > 
> > 5. Use mkimage to produce the appended device tree uImage
> > 
> >    $ mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 \
> >      -n "Linux" -d /tmp/appended /tmp/uImage
> > 
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> Okay, I'm removing the 4430SDP from the boot test system once this goes
> in, because this will mean rewriting the build system to cope with this
> stuff.

OK, up to you. At least I check the results of your build system
occasionally though.

I know people don't want to have more uImage handling in the kernel,
but maybe we could add handling for board specific uImage targets
for compability?

Maybe something like dtbname.uImage-dtba:

$ make omap4-sdp.uImage-dtba

And then that would take care of steps 3 - 5 automatically?

Of course the alternative is to update u-boot, but that's not always
possible for some legacy boards.

Regards,

Tony


From swarren at wwwdotorg.org  Mon May 20 13:10:45 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 11:10:45 -0600
Subject: [PATCH V2 3/4] ARM: tegra: convert device tree files to use GPIO
 defines
Message-ID: <1369069845-7601-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: Rebase on recent *.dts changes

Note: I'm only reposting patch 3/4 as V2, since it's the only one that
changed. Typically I wouldn't do this, but since I'm applying the
patches, I'm not confusing myself too much doing this:-)
---
 arch/arm/boot/dts/tegra114-dalmore.dts     |   12 ++++----
 arch/arm/boot/dts/tegra114.dtsi            |    2 ++
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |   19 +++++++-----
 arch/arm/boot/dts/tegra20-harmony.dts      |   46 ++++++++++++++++------------
 arch/arm/boot/dts/tegra20-iris-512.dts     |    2 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |    6 ++--
 arch/arm/boot/dts/tegra20-paz00.dts        |   24 +++++++++------
 arch/arm/boot/dts/tegra20-plutux.dts       |    6 ++--
 arch/arm/boot/dts/tegra20-seaboard.dts     |   39 ++++++++++++-----------
 arch/arm/boot/dts/tegra20-tamonten.dtsi    |    7 +++--
 arch/arm/boot/dts/tegra20-tec.dts          |    7 +++--
 arch/arm/boot/dts/tegra20-trimslice.dts    |   19 +++++++-----
 arch/arm/boot/dts/tegra20-ventana.dts      |   41 ++++++++++++++-----------
 arch/arm/boot/dts/tegra20-whistler.dts     |   10 +++---
 arch/arm/boot/dts/tegra20.dtsi             |    2 ++
 arch/arm/boot/dts/tegra30-beaver.dts       |   24 +++++++--------
 arch/arm/boot/dts/tegra30-cardhu-a02.dts   |   14 ++++-----
 arch/arm/boot/dts/tegra30-cardhu-a04.dts   |   16 +++++-----
 arch/arm/boot/dts/tegra30-cardhu.dtsi      |   39 +++++++++++------------
 arch/arm/boot/dts/tegra30.dtsi             |    2 ++
 20 files changed, 186 insertions(+), 151 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index acc5257..2571525 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -838,7 +838,7 @@
 	};
 
 	sdhci at 78000400 {
-		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 		bus-width = <4>;
 		status = "okay";
 	};
@@ -883,7 +883,7 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			enable-active-high;
-			gpio = <&gpio 61 0>; /* GPIO PH5 */
+			gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
 		};
 
 		lcd_bl_en_reg: regulator at 2 {
@@ -893,7 +893,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 58 0>; /* GPIO PH2 */
+			gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 3 {
@@ -903,7 +903,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 108 0>; /* GPIO PN4 */
+			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
@@ -915,7 +915,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 86 0>; /* GPIO PK6 */
+			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
@@ -927,7 +927,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 81 0>; /* GPIO PK1 */
+			gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
 	};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index aeeb53b..6cd6d41 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index efd7051..146a65b 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -14,7 +14,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&i2c_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -443,21 +444,25 @@
 
 	ac97: ac97 {
 		status = "okay";
-		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
-		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+		nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5004000 {
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 	};
 
 	clocks {
@@ -514,7 +519,7 @@
 			enable-active-high;
 			regulator-boot-on;
 			regulator-always-on;
-			gpio = <&gpio 217 0>;
+			gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 0f788f9..1ec11a5 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -262,7 +263,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -434,12 +435,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -452,17 +455,17 @@
 
 	sdhci at c8000200 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 155 0>; /* gpio PT3 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
 	sdhci at c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <8>;
 	};
 
@@ -484,7 +487,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -627,7 +630,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -636,7 +639,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -646,7 +649,7 @@
 			regulator-name = "vdd_1v05";
 			regulator-min-microvolt = <1050000>;
 			regulator-max-microvolt = <1050000>;
-			gpio = <&pmic 2 0>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 			/* Hack until board-harmony-pcie.c is removed */
 			status = "disabled";
@@ -658,7 +661,7 @@
 			regulator-name = "vdd_pnl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 22 0>; /* gpio PC6 */
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -668,7 +671,7 @@
 			regulator-name = "vdd_bl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 176 0>; /* gpio PW0 */
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -691,10 +694,13 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
-		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 9de10a2..f2222bd 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -80,7 +80,7 @@
 			regulator-max-microvolt = <5000000>;
 			regulator-boot-on;
 			regulator-always-on;
-			gpio = <&gpio 178 0>;
+			gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		vcc_sd_reg: regulator at 1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index d7e32fa..3adfbfe 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -15,7 +15,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -56,8 +56,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index cbbd85a..f223b83 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -274,7 +275,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clock-frequency = <80000>;
-		request-gpios = <&gpio 170 0>; /* gpio PV2 */
+		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
 		clocks = <&tegra_car 67>, <&tegra_car 124>;
 		clock-names = "div-clk", "fast-clk";
@@ -433,12 +434,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -451,9 +454,9 @@
 
 	sdhci at c8000000 {
 		status = "okay";
-		cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-		wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
-		power-gpios = <&gpio 169 0>; /* gpio PV1 */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -481,7 +484,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -492,7 +495,7 @@
 
 		wifi {
 			label = "wifi-led";
-			gpios = <&gpio 24 0>; /* gpio PD0 */
+			gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "rfkill0";
 		};
 	};
@@ -529,7 +532,8 @@
 
 		nvidia,audio-codec = <&alc5632>;
 		nvidia,i2s-controller = <&tegra_i2s1>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 508e56a..3d8e69b 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -50,8 +50,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 0855b5e..1df2c2a 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -313,7 +314,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -328,14 +329,14 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <202 0x04>; /* GPIO PZ2 */
+			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
 		};
 
 		gyrometer at 68 {
 			compatible = "invn,mpu3050";
 			reg = <0x68>;
 			interrupt-parent = <&gpio>;
-			interrupts = <204 0x04>; /* gpio PZ4 */
+			interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
 		};
 	};
 
@@ -511,7 +512,7 @@
 			compatible = "ak,ak8975";
 			reg = <0xc>;
 			interrupt-parent = <&gpio>;
-			interrupts = <109 0x04>; /* gpio PN5 */
+			interrupts = <TEGRA_GPIO(N, 5) 0x04>;
 		};
 	};
 
@@ -565,7 +566,7 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 		dr_mode = "otg";
 	};
 
@@ -577,12 +578,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -595,16 +598,16 @@
 
 	sdhci at c8000000 {
 		status = "okay";
-		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -632,14 +635,14 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
 
 		lid {
 			label = "Lid";
-			gpios = <&gpio 23 0>; /* gpio PC7 */
+			gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
@@ -806,7 +809,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -815,7 +818,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -847,8 +850,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4e18fdf..321cb20 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -14,7 +14,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -475,8 +476,8 @@
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		status = "okay";
 	};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9a2a6a4..db58bb7 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -50,8 +50,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index d2966b2..44677ee 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -311,7 +312,7 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5000000 {
@@ -321,12 +322,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -344,8 +347,8 @@
 
 	sdhci at c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+		cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -367,7 +370,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 190 1>; /* gpio PX6, active low */
+			gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -375,7 +378,7 @@
 
 	poweroff {
 		compatible = "gpio-poweroff";
-		gpios = <&gpio 191 1>; /* gpio PX7, active low */
+		gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
 	};
 
 	regulators {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 51feeb4..9568e69 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -310,7 +311,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -325,7 +326,7 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <202 0x04>; /*gpio PZ2 */
+			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
 		};
 	};
 
@@ -511,12 +512,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5008000 {
@@ -529,16 +532,16 @@
 
 	sdhci at c8000000 {
 		status = "okay";
-		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -566,7 +569,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -592,7 +595,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -601,7 +604,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -611,7 +614,7 @@
 			regulator-name = "vdd_pnl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 22 0>; /* gpio PC6 */
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -621,7 +624,7 @@
 			regulator-name = "vdd_bl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 176 0>; /* gpio PW0 */
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -644,10 +647,12 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-		nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
-		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 1748be5..2b7a655 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -508,7 +509,7 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+		nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5000000 {
@@ -518,7 +519,7 @@
 
 	usb at c5008000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+		nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5008000 {
@@ -528,8 +529,7 @@
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+		wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
 		bus-width = <8>;
 	};
 
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index cde2f80..673f386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index e86c280..d23d9ed 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -264,9 +264,9 @@
 
 	sdhci at 78000000 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -312,7 +312,7 @@
 			regulator-boot-on;
 			regulator-always-on;
 			enable-active-high;
-			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		ddr_reg: regulator at 2 {
@@ -324,7 +324,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -337,7 +337,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 30 0>; /* gpio PD6 */
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -348,7 +348,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 68 0>; /* GPIO PI4 */
+			gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
@@ -360,7 +360,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 63 0>; /* GPIO PH7 */
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
@@ -374,7 +374,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -387,7 +387,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 95 0>; /* gpio PL7 */
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 	};
@@ -397,11 +397,11 @@
 
 		gpled1 {
 			label = "LED1"; /* CR5A1 (blue) */
-			gpios = <&gpio 89 0>; /* gpio PL1 */
+			gpio = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
 		};
 		gpled2 {
 			label = "LED2"; /* CR4A2 (green) */
-			gpios = <&gpio 88 0>; /* gpio PL0 */
+			gpio = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 3934b0f..1082c5e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -22,7 +22,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		sys_3v3_reg: regulator at 101 {
@@ -34,7 +34,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 102 {
@@ -44,7 +44,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 68 0>; /* GPIO PI4 */
+			gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 63 0>; /* GPIO PH7 */
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -68,7 +68,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&pmic 2 0>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl_reg: regulator at 105 {
@@ -80,13 +80,13 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 83 0>; /* GPIO PK3 */
+			gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	sdhci at 78000400 {
 		status = "okay";
-		power-gpios = <&gpio 28 0>; /* gpio PD4 */
+		power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index af3ff7a..bf012bdd 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -22,7 +22,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		sys_3v3_reg: regulator at 101 {
@@ -34,7 +34,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 102 {
@@ -44,7 +44,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 238 0>; /* GPIO PDD6 */
+			gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 236 0>; /* GPIO PDD4 */
+			gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -68,7 +68,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&pmic 8 0>;
+			gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl_reg: regulator at 105 {
@@ -80,7 +80,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 234 0>; /* GPIO PDD2 */
+			gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl2_reg: regulator at 106 {
@@ -92,13 +92,13 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 232 0>; /* GPIO PDD0 */
+			gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	sdhci at 78000400 {
 		status = "okay";
-		power-gpios = <&gpio 27 0>; /* gpio PD3 */
+		power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index e54eed2..c177fd9 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -146,7 +146,7 @@
 			compatible = "isil,isl29028";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <88 0x04>; /*gpio PL0 */
+			interrupts = <TEGRA_GPIO(L, 0) 0x04>;
 		};
 	};
 
@@ -163,7 +163,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <179 0x04>; /* gpio PW3 */
+			interrupts = <TEGRA_GPIO(W, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -318,9 +318,9 @@
 
 	sdhci at 78000000 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -364,7 +364,7 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			enable-active-high;
-			gpio = <&gpio 220 0>; /* gpio PBB4 */
+			gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vio_reg>;
 		};
 
@@ -377,7 +377,7 @@
 			regulator-boot-on;
 			regulator-always-on;
 			enable-active-high;
-			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		emmc_3v3_reg: regulator at 3 {
@@ -389,7 +389,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 25 0>; /* gpio PD1 */
+			gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -400,7 +400,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 30 0>; /* gpio PD6 */
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 		};
 
 		pex_hvdd_3v3_reg: regulator at 5 {
@@ -410,7 +410,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 95 0>; /* gpio PL7 */
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -421,7 +421,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			enable-active-high;
-			gpio = <&gpio 142 0>; /* gpio PR6 */
+			gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -432,7 +432,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			enable-active-high;
-			gpio = <&gpio 143 0>; /* gpio PR7 */
+			gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -443,7 +443,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 144 0>; /* gpio PS0 */
+			gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -456,7 +456,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 24 0>; /* gpio PD0 */
+			gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -467,7 +467,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 94 0>; /* gpio PL6 */
+			gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -480,7 +480,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 92 0>; /* gpio PL4 */
+			gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -491,7 +491,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 152 0>; /* GPIO PT0 */
+			gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -515,8 +515,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 38967fd..1fe8c3a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.10.4



From kgene.kim at samsung.com  Mon May 20 13:11:15 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 02:11:15 +0900
Subject: [GIT PULL] Samsung fixes-2 for v3.10
Message-ID: <519A5933.3040005@samsung.com>

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-fixes-2

for you to fetch changes up to 7ec892ef5f1bd707e2d5ab128069cb6af75c7f07:

   ARM: dts: Enabling samsung-usb2phy driver for exynos5250 (2013-05-21 
01:26:17 +0900)

----------------------------------------------------------------
Fix to get usb2 working on the Chromebook with adding the
usb phy node for usb2 on exynos5250

----------------------------------------------------------------
Vivek Gautam (1):
       ARM: dts: Enabling samsung-usb2phy driver for exynos5250

  arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++
  1 file changed, 15 insertions(+)


From jason at lakedaemon.net  Mon May 20 13:13:01 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:13:01 -0400
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and
 ge11
In-Reply-To: <20130520082205.GC26249@lunn.ch>
References: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
 <20130520082205.GC26249@lunn.ch>
Message-ID: <20130520171301.GV31290@titan.lakedaemon.net>

On Mon, May 20, 2013 at 10:22:05AM +0200, Andrew Lunn wrote:
> On Sun, May 19, 2013 at 10:12:43PM +0200, Gregory CLEMENT wrote:
> > When platform data were moved from arch/arm/mach-mv78xx0/common.c to
> > arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion:
> > Consolidate ethernet platform data", there were few typo made on
> > gigabit Ethernet interface ge10 and ge11. This commit writes back
> > their initial value, which allows to use this interfaces again.
> > 
> > Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> > ---
> >  arch/arm/plat-orion/common.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> > index 251f827..c019b7a 100644
> > --- a/arch/arm/plat-orion/common.c
> > +++ b/arch/arm/plat-orion/common.c
> > @@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = {
> >  
> >  static struct platform_device orion_ge10_shared = {
> >  	.name		= MV643XX_ETH_SHARED_NAME,
> > -	.id		= 1,
> > +	.id		= 2,
> >  	.dev		= {
> >  		.platform_data	= &orion_ge10_shared_data,
> >  	},
> > @@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = {
> >  
> >  static struct platform_device orion_ge10 = {
> >  	.name		= MV643XX_ETH_NAME,
> > -	.id		= 1,
> > -	.num_resources	= 2,
> > +	.id		= 2,
> > +	.num_resources	= 1,
> >  	.resource	= orion_ge10_resources,
> >  	.dev		= {
> >  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> > @@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = {
> >  
> >  static struct platform_device orion_ge11_shared = {
> >  	.name		= MV643XX_ETH_SHARED_NAME,
> > -	.id		= 1,
> > +	.id		= 3,
> >  	.dev		= {
> >  		.platform_data	= &orion_ge11_shared_data,
> >  	},
> > @@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = {
> >  
> >  static struct platform_device orion_ge11 = {
> >  	.name		= MV643XX_ETH_NAME,
> > -	.id		= 1,
> > -	.num_resources	= 2,
> > +	.id		= 3,
> > +	.num_resources	= 1,
> >  	.resource	= orion_ge11_resources,
> >  	.dev		= {
> >  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> > -- 
> > 1.8.1.2
> > 
> 
> Hi Gregory
> 
> My Bad. Thanks for fixing this.
> 
> Acked-by: Andrew Lunn <andrew at lunn.ch>
> 
> Jason, this can go into stable, as far back as 3.0.

Ok, thanks for the heads up.  I'll wait for v2 (with rmk's suggestion)
and tag it for stable.

thx,

Jason.


From kgene.kim at samsung.com  Mon May 20 13:13:00 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 02:13:00 +0900
Subject: [PATCH 30/33] arch/arm/plat-samsung: don't check resource with
 devm_ioremap_resource
In-Reply-To: <20130520171118.GA5717@katana>
References: <1368702961-4325-1-git-send-email-wsa@the-dreams.de>
 <1368702961-4325-31-git-send-email-wsa@the-dreams.de>
 <519A517F.5020003@samsung.com> <20130520171118.GA5717@katana>
Message-ID: <519A599C.2020702@samsung.com>

On 05/21/13 02:11, Wolfram Sang wrote:
> On Tue, May 21, 2013 at 01:38:23AM +0900, Kukjin Kim wrote:
>> On 05/16/13 20:15, Wolfram Sang wrote:
>>> devm_ioremap_resource does sanity checks on the given resource. No need to
>>> duplicate this in the driver.
>>>
>>> Signed-off-by: Wolfram Sang<wsa at the-dreams.de>
>>
>> Looks good to me, applied into Samsung tree.
>>
>> Wolfram, if you want to take this into your tree, let me know.
>
> It is already upstream :)
>
Oh, OK. Let me drop it in my tree ;-)

Thanks.

- Kukjin


From catalin.marinas at arm.com  Mon May 20 13:13:52 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 May 2013 18:13:52 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130520160407.GS31359@mudshark.cambridge.arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <20130520142459.GN31359@mudshark.cambridge.arm.com>
 <20130520151158.GA3520@MacBook-Pro.local>
 <20130520160407.GS31359@mudshark.cambridge.arm.com>
Message-ID: <20130520171349.GM3639@MacBook-Pro.local>

On Mon, May 20, 2013 at 05:04:07PM +0100, Will Deacon wrote:
> On Mon, May 20, 2013 at 04:11:58PM +0100, Catalin Marinas wrote:
> > On Mon, May 20, 2013 at 03:24:59PM +0100, Will Deacon wrote:
> > > On Mon, May 20, 2013 at 03:18:09PM +0100, Catalin Marinas wrote:
> > > > As I mentioned in the past, I don't agree with exposing the "LPAE"
> > > > feature to user-space, it's not a feature that user space should care
> > > > about. An atomic double hwcap is better and you can even make this per
> > > > CPU via __v7_proc.
> > > 
> > > I don't buy the argument that this could be per-CPU: doubleword atomicity
> > > requires support in the whole system -- not just in the CPU. The only way we
> > > can rely on it, is by guarantees made in the architecture, which are made
> > > as part of LPAE.
> > 
> > Well, you know that for A7/A15 you have this feature as they support
> > LPAE. You can have it as a generic LPAE test (only that the ARM ARM
> > isn't entirely clear here, so for people asking in the future we could
> > say it's a feature of the A7/A15/etc.)
> 
> No, as far as Linux is concerned, it's a feature of any system claiming to
> have support for LPAE. Given that we allocate page tables using our usual
> allocators, all memory that we map as normal must be capable of doubleword
> atomics. We make use of this in our atomic64_{read,set} implementations.

I guess we don't have non-LPAE processors that do atomic doubles (if we
would, they can use __v7_proc explicitly, though with a different name).

> > > If this just boils down to a naming issue, thn I'm happy to change it, but
> > > we *are* reporting whether LPAE is supported and I can't think of a better
> > > name than that.
> > 
> > Given that the ARM ARM isn't clear (though this is the case on the
> > actual implementations), user space may not necessarily assume that
> > LPAE==atomic doubles. That's why I think reporting the actual atomic
> > feature is better.
> 
> The ARM ARM isn't too bad: it's just avoiding mandating 64-bit-wide paths
> around the entire SoC (and I've checked this with the architects). The only
> way we can probe this feature is using the MMFR0 and checking if LPAE is
> supported, and that's exactly what userspace will need to rely on.

Well, LPAE implies atomic doubles but I wouldn't say that's the "only"
way, it can always be a feature of the CPU. Now, would the user
developers fully understand the implications of LPAE?

> We can
> change the name, but the probe code will remain the same so I'm not sure it
> makes anything clearer. We had "atomicd" originally, but that sounds like a
> techno band.

We can make it longer, 'atomicdbl', if that's the issue ;).

-- 
Catalin


From jason at lakedaemon.net  Mon May 20 13:21:51 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:21:51 -0400
Subject: [RFC PATCH 4/5] ARM: mv78x00: Add the Device Tree support for
 MV78X00 family
In-Reply-To: <1368999578-19938-5-git-send-email-gregory.clement@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <1368999578-19938-5-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520172151.GW31290@titan.lakedaemon.net>

On Sun, May 19, 2013 at 11:39:37PM +0200, Gregory CLEMENT wrote:
> This commit adds the Device Tree support for the mv78x00 SoC
> family. It adds an mv78x00.dtsi description of the mv78x00 SoC
> 
> So far, the Device Tree contains the interrupt controller, the GPIO
> bank, the UART controllers, the USB host controllers, the SATA
> controllers and the I2C controllers.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/boot/dts/mv78x00.dtsi | 126 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 126 insertions(+)
>  create mode 100644 arch/arm/boot/dts/mv78x00.dtsi
> 
> diff --git a/arch/arm/boot/dts/mv78x00.dtsi b/arch/arm/boot/dts/mv78x00.dtsi
> new file mode 100644
> index 0000000..df496f5
> --- /dev/null
> +++ b/arch/arm/boot/dts/mv78x00.dtsi
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright (C) 2013 Gregory CLEMENT <gregory.clement at free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	model = "Marvell MV78X00 SoC";
> +	compatible = "marvell,mv78x00";
> +	interrupt-parent = <&intc>;
> +
> +	intc: interrupt-controller {
> +		compatible = "marvell,orion-intc", "marvell,intc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		reg = <0xf1020210 0x04>,
> +		      <0xf1020214 0x04>,
> +		      <0xf102020c 0x04>;
> +	};
> +
> +	ocp at f1000000 {
> +		compatible = "simple-bus";
> +		ranges = <0x00000000 0xf1000000 0x4000000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		gpio0: gpio at 10100 {
> +			compatible = "marvell,orion-gpio";
> +			#gpio-cells = <2>;
> +			gpio-controller;
> +			reg = <0x10100 0x40>;
> +			ngpios = <32>;
> +			interrupts = <56>, <57>, <58>, <59>;
> +		};
> +
> +		serial at 12000 {
> +			compatible = "ns16550a";
> +			reg = <0x12000 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <12>;
> +			/* set clock-frequency in board dts */
> +			status = "disabled";
> +		};
> +
> +		serial at 12100 {
> +			compatible = "ns16550a";
> +			reg = <0x12100 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <13>;
> +			/* set clock-frequency in board dts */
> +			status = "disabled";
> +		};
> +
> +		serial at 12200 {
> +			compatible = "ns16550a";
> +			reg = <0x12200 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <14>;
> +			/* set clock-frequency in board dts */
> +			status = "disabled";
> +		};
> +
> +		serial at 12300 {
> +			compatible = "ns16550a";
> +			reg = <0x12300 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <15>;
> +			/* set clock-frequency in board dts */

We should probably add a note to these comments that this is only until
mv78x00 is converted to the clock infrastructure.

thx,

Jason.

> +			status = "disabled";
> +		};
> +
> +
> +		sata at a0000 {
> +			compatible = "marvell,orion-sata";
> +			reg = <0xa0000 0x5000>;
> +			interrupts = <26>;
> +			status = "disabled";
> +		};
> +
> +		i2c at 10000 {
> +			compatible = "marvell,mv64xxx-i2c";
> +			reg = <0x10000 0x20>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <2>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +		};
> +
> +		i2c at 11000 {
> +			compatible = "marvell,mv64xxx-i2c";
> +			reg = <0x11000 0x20>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <3>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +		};
> +
> +		ehci at 50000 {
> +			compatible = "marvell,orion-ehci";
> +			reg = <0x50000 0x1000>;
> +			interrupts = <16>;
> +			status = "disabled";
> +		};
> +
> +		ehci at 51000 {
> +			compatible = "marvell,orion-ehci";
> +			reg = <0x51000 0x1000>;
> +			interrupts = <17>;
> +			status = "disabled";
> +		};
> +
> +		ehci at 52000 {
> +			compatible = "marvell,orion-ehci";
> +			reg = <0x52000 0x1000>;
> +			interrupts = <18>;
> +			status = "disabled";
> +		};
> +
> +	};
> +};
> -- 
> 1.8.1.2
> 


From sebastian.hesselbarth at gmail.com  Mon May 20 13:23:41 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 May 2013 19:23:41 +0200
Subject: [RFC PATCH 4/5] ARM: mv78x00: Add the Device Tree support for
 MV78X00 family
In-Reply-To: <20130520172151.GW31290@titan.lakedaemon.net>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <1368999578-19938-5-git-send-email-gregory.clement@free-electrons.com>
 <20130520172151.GW31290@titan.lakedaemon.net>
Message-ID: <519A5C1D.9030307@gmail.com>

On 05/20/2013 07:21 PM, Jason Cooper wrote:
> On Sun, May 19, 2013 at 11:39:37PM +0200, Gregory CLEMENT wrote:
>> This commit adds the Device Tree support for the mv78x00 SoC
>> family. It adds an mv78x00.dtsi description of the mv78x00 SoC
>>
>> So far, the Device Tree contains the interrupt controller, the GPIO
>> bank, the UART controllers, the USB host controllers, the SATA
>> controllers and the I2C controllers.
>>
>> Signed-off-by: Gregory CLEMENT<gregory.clement at free-electrons.com>
>> ---
...
>> +		serial at 12300 {
>> +			compatible = "ns16550a";
>> +			reg =<0x12300 0x100>;
>> +			reg-shift =<2>;
>> +			interrupts =<15>;
>> +			/* set clock-frequency in board dts */
>
> We should probably add a note to these comments that this is only until
> mv78x00 is converted to the clock infrastructure.

Or use a fixed-rate clock node, reference here, and set that in board
dts?

Sebastian


From andrew at lunn.ch  Mon May 20 13:24:24 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 May 2013 19:24:24 +0200
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and
 ge11
In-Reply-To: <20130520171301.GV31290@titan.lakedaemon.net>
References: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
 <20130520082205.GC26249@lunn.ch>
 <20130520171301.GV31290@titan.lakedaemon.net>
Message-ID: <20130520172424.GI26249@lunn.ch>

On Mon, May 20, 2013 at 01:13:01PM -0400, Jason Cooper wrote:
> On Mon, May 20, 2013 at 10:22:05AM +0200, Andrew Lunn wrote:
> > On Sun, May 19, 2013 at 10:12:43PM +0200, Gregory CLEMENT wrote:
> > > When platform data were moved from arch/arm/mach-mv78xx0/common.c to
> > > arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion:
> > > Consolidate ethernet platform data", there were few typo made on
> > > gigabit Ethernet interface ge10 and ge11. This commit writes back
> > > their initial value, which allows to use this interfaces again.
> > > 
> > > Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> > > ---
> > >  arch/arm/plat-orion/common.c | 12 ++++++------
> > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> > > index 251f827..c019b7a 100644
> > > --- a/arch/arm/plat-orion/common.c
> > > +++ b/arch/arm/plat-orion/common.c
> > > @@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = {
> > >  
> > >  static struct platform_device orion_ge10_shared = {
> > >  	.name		= MV643XX_ETH_SHARED_NAME,
> > > -	.id		= 1,
> > > +	.id		= 2,
> > >  	.dev		= {
> > >  		.platform_data	= &orion_ge10_shared_data,
> > >  	},
> > > @@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = {
> > >  
> > >  static struct platform_device orion_ge10 = {
> > >  	.name		= MV643XX_ETH_NAME,
> > > -	.id		= 1,
> > > -	.num_resources	= 2,
> > > +	.id		= 2,
> > > +	.num_resources	= 1,
> > >  	.resource	= orion_ge10_resources,
> > >  	.dev		= {
> > >  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> > > @@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = {
> > >  
> > >  static struct platform_device orion_ge11_shared = {
> > >  	.name		= MV643XX_ETH_SHARED_NAME,
> > > -	.id		= 1,
> > > +	.id		= 3,
> > >  	.dev		= {
> > >  		.platform_data	= &orion_ge11_shared_data,
> > >  	},
> > > @@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = {
> > >  
> > >  static struct platform_device orion_ge11 = {
> > >  	.name		= MV643XX_ETH_NAME,
> > > -	.id		= 1,
> > > -	.num_resources	= 2,
> > > +	.id		= 3,
> > > +	.num_resources	= 1,
> > >  	.resource	= orion_ge11_resources,
> > >  	.dev		= {
> > >  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> > > -- 
> > > 1.8.1.2
> > > 
> > 
> > Hi Gregory
> > 
> > My Bad. Thanks for fixing this.
> > 
> > Acked-by: Andrew Lunn <andrew at lunn.ch>
> > 
> > Jason, this can go into stable, as far back as 3.0.
> 
> Ok, thanks for the heads up.  I'll wait for v2 (with rmk's suggestion)
> and tag it for stable.

Hi Jason

RMK suggestion would apply to the whole file, not just this one
instance. As such, it would be a bigger patch going into -cleanup for
the next merge window.

I suggest you take this patch as is for the next -rc and i can work on
RMKs suggestion soon along with a couple of other cleanups.

     Andrew


From jason at lakedaemon.net  Mon May 20 13:28:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:28:32 -0400
Subject: [RFC PATCH 4/5] ARM: mv78x00: Add the Device Tree support for
 MV78X00 family
In-Reply-To: <519A5C1D.9030307@gmail.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <1368999578-19938-5-git-send-email-gregory.clement@free-electrons.com>
 <20130520172151.GW31290@titan.lakedaemon.net>
 <519A5C1D.9030307@gmail.com>
Message-ID: <20130520172832.GX31290@titan.lakedaemon.net>

On Mon, May 20, 2013 at 07:23:41PM +0200, Sebastian Hesselbarth wrote:
> On 05/20/2013 07:21 PM, Jason Cooper wrote:
> >On Sun, May 19, 2013 at 11:39:37PM +0200, Gregory CLEMENT wrote:
> >>This commit adds the Device Tree support for the mv78x00 SoC
> >>family. It adds an mv78x00.dtsi description of the mv78x00 SoC
> >>
> >>So far, the Device Tree contains the interrupt controller, the GPIO
> >>bank, the UART controllers, the USB host controllers, the SATA
> >>controllers and the I2C controllers.
> >>
> >>Signed-off-by: Gregory CLEMENT<gregory.clement at free-electrons.com>
> >>---
> ...
> >>+		serial at 12300 {
> >>+			compatible = "ns16550a";
> >>+			reg =<0x12300 0x100>;
> >>+			reg-shift =<2>;
> >>+			interrupts =<15>;
> >>+			/* set clock-frequency in board dts */
> >
> >We should probably add a note to these comments that this is only until
> >mv78x00 is converted to the clock infrastructure.
> 
> Or use a fixed-rate clock node, reference here, and set that in board
> dts?

Yes, I realized (of course _after_ hitting send), that the whole issue I
was recalling was wrt gated clocks.  iirc now, mv78xx0 doesn't have
gated clocks.

thx,

Jason.


From jason at lakedaemon.net  Mon May 20 13:30:20 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:30:20 -0400
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and
 ge11
In-Reply-To: <20130520172424.GI26249@lunn.ch>
References: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
 <20130520082205.GC26249@lunn.ch>
 <20130520171301.GV31290@titan.lakedaemon.net>
 <20130520172424.GI26249@lunn.ch>
Message-ID: <20130520173020.GY31290@titan.lakedaemon.net>

On Mon, May 20, 2013 at 07:24:24PM +0200, Andrew Lunn wrote:
> On Mon, May 20, 2013 at 01:13:01PM -0400, Jason Cooper wrote:
> > On Mon, May 20, 2013 at 10:22:05AM +0200, Andrew Lunn wrote:
> > > On Sun, May 19, 2013 at 10:12:43PM +0200, Gregory CLEMENT wrote:
> > > > When platform data were moved from arch/arm/mach-mv78xx0/common.c to
> > > > arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion:
> > > > Consolidate ethernet platform data", there were few typo made on
> > > > gigabit Ethernet interface ge10 and ge11. This commit writes back
> > > > their initial value, which allows to use this interfaces again.
> > > > 
> > > > Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> > > > ---
> > > >  arch/arm/plat-orion/common.c | 12 ++++++------
> > > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> > > > index 251f827..c019b7a 100644
> > > > --- a/arch/arm/plat-orion/common.c
> > > > +++ b/arch/arm/plat-orion/common.c
> > > > @@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = {
> > > >  
> > > >  static struct platform_device orion_ge10_shared = {
> > > >  	.name		= MV643XX_ETH_SHARED_NAME,
> > > > -	.id		= 1,
> > > > +	.id		= 2,
> > > >  	.dev		= {
> > > >  		.platform_data	= &orion_ge10_shared_data,
> > > >  	},
> > > > @@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = {
> > > >  
> > > >  static struct platform_device orion_ge10 = {
> > > >  	.name		= MV643XX_ETH_NAME,
> > > > -	.id		= 1,
> > > > -	.num_resources	= 2,
> > > > +	.id		= 2,
> > > > +	.num_resources	= 1,
> > > >  	.resource	= orion_ge10_resources,
> > > >  	.dev		= {
> > > >  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> > > > @@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = {
> > > >  
> > > >  static struct platform_device orion_ge11_shared = {
> > > >  	.name		= MV643XX_ETH_SHARED_NAME,
> > > > -	.id		= 1,
> > > > +	.id		= 3,
> > > >  	.dev		= {
> > > >  		.platform_data	= &orion_ge11_shared_data,
> > > >  	},
> > > > @@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = {
> > > >  
> > > >  static struct platform_device orion_ge11 = {
> > > >  	.name		= MV643XX_ETH_NAME,
> > > > -	.id		= 1,
> > > > -	.num_resources	= 2,
> > > > +	.id		= 3,
> > > > +	.num_resources	= 1,
> > > >  	.resource	= orion_ge11_resources,
> > > >  	.dev		= {
> > > >  		.coherent_dma_mask	= DMA_BIT_MASK(32),
> > > > -- 
> > > > 1.8.1.2
> > > > 
> > > 
> > > Hi Gregory
> > > 
> > > My Bad. Thanks for fixing this.
> > > 
> > > Acked-by: Andrew Lunn <andrew at lunn.ch>
> > > 
> > > Jason, this can go into stable, as far back as 3.0.
> > 
> > Ok, thanks for the heads up.  I'll wait for v2 (with rmk's suggestion)
> > and tag it for stable.
> 
> Hi Jason
> 
> RMK suggestion would apply to the whole file, not just this one
> instance. As such, it would be a bigger patch going into -cleanup for
> the next merge window.
> 
> I suggest you take this patch as is for the next -rc and i can work on
> RMKs suggestion soon along with a couple of other cleanups.

ok, sounds good.  I'll queue it up for the next /fixes PR.

thx,

Jason.


From swarren at wwwdotorg.org  Mon May 20 13:38:20 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 11:38:20 -0600
Subject: [PATCH V3 3/4] ARM: tegra: convert device tree files to use GPIO
 defines
Message-ID: <1369071500-10513-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v3: Fix some silly mistakes in v2. Now, there are 0 diffs in all .dtb files
* nvidia,phy-reset-gpio should be ACTIVE_LOW not ACTIVE_HIGH.
* Don't remove cd-gpios from tegra20-whistler.dts.
* Whistler's SD slot wp-gpios should be ACTIVE_HIGH not ACTIVE_LOW.
* Don't s/gpio/gpios/ in Beaver's gpio-leds property names.
v2: Rebase on recent *.dts changes

Note: I'm only reposting patch 3/4 as V2, since it's the only one that
changed. Typically I wouldn't do this, but since I'm applying the
patches, I'm not confusing myself too much doing this:-)

 arch/arm/boot/dts/tegra114-dalmore.dts     |   12 ++++----
 arch/arm/boot/dts/tegra114.dtsi            |    2 ++
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |   19 +++++++-----
 arch/arm/boot/dts/tegra20-harmony.dts      |   46 ++++++++++++++++------------
 arch/arm/boot/dts/tegra20-iris-512.dts     |    2 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |    6 ++--
 arch/arm/boot/dts/tegra20-paz00.dts        |   24 +++++++++------
 arch/arm/boot/dts/tegra20-plutux.dts       |    6 ++--
 arch/arm/boot/dts/tegra20-seaboard.dts     |   39 ++++++++++++-----------
 arch/arm/boot/dts/tegra20-tamonten.dtsi    |    7 +++--
 arch/arm/boot/dts/tegra20-tec.dts          |    7 +++--
 arch/arm/boot/dts/tegra20-trimslice.dts    |   19 +++++++-----
 arch/arm/boot/dts/tegra20-ventana.dts      |   41 ++++++++++++++-----------
 arch/arm/boot/dts/tegra20-whistler.dts     |   11 ++++---
 arch/arm/boot/dts/tegra20.dtsi             |    2 ++
 arch/arm/boot/dts/tegra30-beaver.dts       |   24 +++++++--------
 arch/arm/boot/dts/tegra30-cardhu-a02.dts   |   14 ++++-----
 arch/arm/boot/dts/tegra30-cardhu-a04.dts   |   16 +++++-----
 arch/arm/boot/dts/tegra30-cardhu.dtsi      |   39 +++++++++++------------
 arch/arm/boot/dts/tegra30.dtsi             |    2 ++
 20 files changed, 187 insertions(+), 151 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index acc5257..2571525 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -838,7 +838,7 @@
 	};
 
 	sdhci at 78000400 {
-		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 		bus-width = <4>;
 		status = "okay";
 	};
@@ -883,7 +883,7 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			enable-active-high;
-			gpio = <&gpio 61 0>; /* GPIO PH5 */
+			gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
 		};
 
 		lcd_bl_en_reg: regulator at 2 {
@@ -893,7 +893,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 58 0>; /* GPIO PH2 */
+			gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 3 {
@@ -903,7 +903,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 108 0>; /* GPIO PN4 */
+			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
@@ -915,7 +915,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 86 0>; /* GPIO PK6 */
+			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
@@ -927,7 +927,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 81 0>; /* GPIO PK1 */
+			gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&tps65090_dcdc1_reg>;
 		};
 	};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index aeeb53b..6cd6d41 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index efd7051..a80be14 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -14,7 +14,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&i2c_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -443,21 +444,25 @@
 
 	ac97: ac97 {
 		status = "okay";
-		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
-		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+		nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+			GPIO_ACTIVE_HIGH>;
 	};
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb-phy at c5004000 {
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 	};
 
 	clocks {
@@ -514,7 +519,7 @@
 			enable-active-high;
 			regulator-boot-on;
 			regulator-always-on;
-			gpio = <&gpio 217 0>;
+			gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 0f788f9..8fac82b 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -262,7 +263,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -434,12 +435,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb at c5008000 {
@@ -452,17 +455,17 @@
 
 	sdhci at c8000200 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 155 0>; /* gpio PT3 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
 	sdhci at c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <8>;
 	};
 
@@ -484,7 +487,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -627,7 +630,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -636,7 +639,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -646,7 +649,7 @@
 			regulator-name = "vdd_1v05";
 			regulator-min-microvolt = <1050000>;
 			regulator-max-microvolt = <1050000>;
-			gpio = <&pmic 2 0>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 			/* Hack until board-harmony-pcie.c is removed */
 			status = "disabled";
@@ -658,7 +661,7 @@
 			regulator-name = "vdd_pnl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 22 0>; /* gpio PC6 */
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -668,7 +671,7 @@
 			regulator-name = "vdd_bl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 176 0>; /* gpio PW0 */
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -691,10 +694,13 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
-		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 9de10a2..f2222bd 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -80,7 +80,7 @@
 			regulator-max-microvolt = <5000000>;
 			regulator-boot-on;
 			regulator-always-on;
-			gpio = <&gpio 178 0>;
+			gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		vcc_sd_reg: regulator at 1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index d7e32fa..3adfbfe 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -15,7 +15,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -56,8 +56,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index cbbd85a..0f267d8 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -274,7 +275,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clock-frequency = <80000>;
-		request-gpios = <&gpio 170 0>; /* gpio PV2 */
+		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
 		clocks = <&tegra_car 67>, <&tegra_car 124>;
 		clock-names = "div-clk", "fast-clk";
@@ -433,12 +434,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb at c5008000 {
@@ -451,9 +454,9 @@
 
 	sdhci at c8000000 {
 		status = "okay";
-		cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-		wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
-		power-gpios = <&gpio 169 0>; /* gpio PV1 */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -481,7 +484,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -492,7 +495,7 @@
 
 		wifi {
 			label = "wifi-led";
-			gpios = <&gpio 24 0>; /* gpio PD0 */
+			gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "rfkill0";
 		};
 	};
@@ -529,7 +532,8 @@
 
 		nvidia,audio-codec = <&alc5632>;
 		nvidia,i2s-controller = <&tegra_i2s1>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 508e56a..3d8e69b 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -50,8 +50,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 0855b5e..3952757 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -313,7 +314,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -328,14 +329,14 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <202 0x04>; /* GPIO PZ2 */
+			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
 		};
 
 		gyrometer at 68 {
 			compatible = "invn,mpu3050";
 			reg = <0x68>;
 			interrupt-parent = <&gpio>;
-			interrupts = <204 0x04>; /* gpio PZ4 */
+			interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
 		};
 	};
 
@@ -511,7 +512,7 @@
 			compatible = "ak,ak8975";
 			reg = <0xc>;
 			interrupt-parent = <&gpio>;
-			interrupts = <109 0x04>; /* gpio PN5 */
+			interrupts = <TEGRA_GPIO(N, 5) 0x04>;
 		};
 	};
 
@@ -565,7 +566,7 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 		dr_mode = "otg";
 	};
 
@@ -577,12 +578,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb at c5008000 {
@@ -595,16 +598,16 @@
 
 	sdhci at c8000000 {
 		status = "okay";
-		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -632,14 +635,14 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
 
 		lid {
 			label = "Lid";
-			gpios = <&gpio 23 0>; /* gpio PC7 */
+			gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
@@ -806,7 +809,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -815,7 +818,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -847,8 +850,8 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4e18fdf..321cb20 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -14,7 +14,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -475,8 +476,8 @@
 	};
 
 	sdhci at c8000600 {
-		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		status = "okay";
 	};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9a2a6a4..db58bb7 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -17,7 +17,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -50,8 +50,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index d2966b2..4257ab4 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -311,7 +312,7 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5000000 {
@@ -321,12 +322,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb at c5008000 {
@@ -344,8 +347,8 @@
 
 	sdhci at c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+		cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -367,7 +370,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 190 1>; /* gpio PX6, active low */
+			gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -375,7 +378,7 @@
 
 	poweroff {
 		compatible = "gpio-poweroff";
-		gpios = <&gpio 191 1>; /* gpio PX7, active low */
+		gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
 	};
 
 	regulators {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 51feeb4..ff8817b 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -310,7 +311,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <187 0x04>;
+			interrupts = <TEGRA_GPIO(X, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -325,7 +326,7 @@
 			compatible = "isil,isl29018";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <202 0x04>; /*gpio PZ2 */
+			interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
 		};
 	};
 
@@ -511,12 +512,14 @@
 
 	usb at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb-phy at c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb at c5008000 {
@@ -529,16 +532,16 @@
 
 	sdhci at c8000000 {
 		status = "okay";
-		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -566,7 +569,7 @@
 
 		power {
 			label = "Power";
-			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
@@ -592,7 +595,7 @@
 			regulator-name = "vdd_1v5";
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
-			gpio = <&pmic 0 0>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		regulator at 2 {
@@ -601,7 +604,7 @@
 			regulator-name = "vdd_1v2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
-			gpio = <&pmic 1 0>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -611,7 +614,7 @@
 			regulator-name = "vdd_pnl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 22 0>; /* gpio PC6 */
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -621,7 +624,7 @@
 			regulator-name = "vdd_bl";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpio = <&gpio 176 0>; /* gpio PW0 */
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 	};
@@ -644,10 +647,12 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-		nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
-		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 1748be5..9a773bb 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -18,7 +18,8 @@
 			pll-supply = <&hdmi_pll_reg>;
 
 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -508,7 +509,7 @@
 
 	usb at c5000000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+		nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5000000 {
@@ -518,7 +519,7 @@
 
 	usb at c5008000 {
 		status = "okay";
-		nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+		nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy at c5008000 {
@@ -528,8 +529,8 @@
 
 	sdhci at c8000400 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
 		bus-width = <8>;
 	};
 
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index cde2f80..673f386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index e86c280..40b0bd70 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -264,9 +264,9 @@
 
 	sdhci at 78000000 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -312,7 +312,7 @@
 			regulator-boot-on;
 			regulator-always-on;
 			enable-active-high;
-			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		ddr_reg: regulator at 2 {
@@ -324,7 +324,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -337,7 +337,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 30 0>; /* gpio PD6 */
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -348,7 +348,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 68 0>; /* GPIO PI4 */
+			gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
@@ -360,7 +360,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 63 0>; /* GPIO PH7 */
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
@@ -374,7 +374,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vdd_5v_in_reg>;
 		};
 
@@ -387,7 +387,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 95 0>; /* gpio PL7 */
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 	};
@@ -397,11 +397,11 @@
 
 		gpled1 {
 			label = "LED1"; /* CR5A1 (blue) */
-			gpios = <&gpio 89 0>; /* gpio PL1 */
+			gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
 		};
 		gpled2 {
 			label = "LED2"; /* CR4A2 (green) */
-			gpios = <&gpio 88 0>; /* gpio PL0 */
+			gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 3934b0f..1082c5e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -22,7 +22,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		sys_3v3_reg: regulator at 101 {
@@ -34,7 +34,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 102 {
@@ -44,7 +44,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 68 0>; /* GPIO PI4 */
+			gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 63 0>; /* GPIO PH7 */
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -68,7 +68,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&pmic 2 0>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl_reg: regulator at 105 {
@@ -80,13 +80,13 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 83 0>; /* GPIO PK3 */
+			gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	sdhci at 78000400 {
 		status = "okay";
-		power-gpios = <&gpio 28 0>; /* gpio PD4 */
+		power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index af3ff7a..bf012bdd 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -22,7 +22,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 7 0>;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		sys_3v3_reg: regulator at 101 {
@@ -34,7 +34,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&pmic 6 0>;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb1_vbus_reg: regulator at 102 {
@@ -44,7 +44,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 238 0>; /* GPIO PDD6 */
+			gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 236 0>; /* GPIO PDD4 */
+			gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -68,7 +68,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&pmic 8 0>;
+			gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl_reg: regulator at 105 {
@@ -80,7 +80,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 234 0>; /* GPIO PDD2 */
+			gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
 		};
 
 		vdd_bl2_reg: regulator at 106 {
@@ -92,13 +92,13 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 232 0>; /* GPIO PDD0 */
+			gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
 	sdhci at 78000400 {
 		status = "okay";
-		power-gpios = <&gpio 27 0>; /* gpio PD3 */
+		power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 		keep-power-in-suspend;
 	};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index e54eed2..c177fd9 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -146,7 +146,7 @@
 			compatible = "isil,isl29028";
 			reg = <0x44>;
 			interrupt-parent = <&gpio>;
-			interrupts = <88 0x04>; /*gpio PL0 */
+			interrupts = <TEGRA_GPIO(L, 0) 0x04>;
 		};
 	};
 
@@ -163,7 +163,7 @@
 			compatible = "wlf,wm8903";
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
-			interrupts = <179 0x04>; /* gpio PW3 */
+			interrupts = <TEGRA_GPIO(W, 3) 0x04>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -318,9 +318,9 @@
 
 	sdhci at 78000000 {
 		status = "okay";
-		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
@@ -364,7 +364,7 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			enable-active-high;
-			gpio = <&gpio 220 0>; /* gpio PBB4 */
+			gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&vio_reg>;
 		};
 
@@ -377,7 +377,7 @@
 			regulator-boot-on;
 			regulator-always-on;
 			enable-active-high;
-			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		emmc_3v3_reg: regulator at 3 {
@@ -389,7 +389,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 25 0>; /* gpio PD1 */
+			gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -400,7 +400,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 30 0>; /* gpio PD6 */
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 		};
 
 		pex_hvdd_3v3_reg: regulator at 5 {
@@ -410,7 +410,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 95 0>; /* gpio PL7 */
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -421,7 +421,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			enable-active-high;
-			gpio = <&gpio 142 0>; /* gpio PR6 */
+			gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -432,7 +432,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			enable-active-high;
-			gpio = <&gpio 143 0>; /* gpio PR7 */
+			gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -443,7 +443,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 144 0>; /* gpio PS0 */
+			gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -456,7 +456,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 24 0>; /* gpio PD0 */
+			gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -467,7 +467,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			enable-active-high;
-			gpio = <&gpio 94 0>; /* gpio PL6 */
+			gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -480,7 +480,7 @@
 			regulator-always-on;
 			regulator-boot-on;
 			enable-active-high;
-			gpio = <&gpio 92 0>; /* gpio PL4 */
+			gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
 			vin-supply = <&sys_3v3_reg>;
 		};
 
@@ -491,7 +491,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio 152 0>; /* GPIO PT0 */
+			gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 			gpio-open-drain;
 			vin-supply = <&vdd_5v0_reg>;
 		};
@@ -515,8 +515,9 @@
 		nvidia,i2s-controller = <&tegra_i2s1>;
 		nvidia,audio-codec = <&wm8903>;
 
-		nvidia,spkr-en-gpios = <&wm8903 2 0>;
-		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 38967fd..1fe8c3a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.10.4



From jason at lakedaemon.net  Mon May 20 13:44:17 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:44:17 -0400
Subject: [PATCH] ARM: plat-orion: Fix num_resources and id for ge10 and
 ge11
In-Reply-To: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
References: <1368994363-14762-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520174417.GZ31290@titan.lakedaemon.net>

On Sun, May 19, 2013 at 10:12:43PM +0200, Gregory CLEMENT wrote:
> When platform data were moved from arch/arm/mach-mv78xx0/common.c to
> arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion:
> Consolidate ethernet platform data", there were few typo made on
> gigabit Ethernet interface ge10 and ge11. This commit writes back
> their initial value, which allows to use this interfaces again.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/plat-orion/common.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)

Applied to mvebu/fixes and marked for stable back to v3.0.x

thx,

Jason.


From tony at atomide.com  Mon May 20 13:46:21 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 20 May 2013 10:46:21 -0700
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130516214430.GN5600@atomide.com>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com>
Message-ID: <20130520174621.GI10378@atomide.com>

* Tony Lindgren <tony at atomide.com> [130516 14:50]:
> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
> > On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> > > * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> > > > I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> > > > 
> > > > [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> > > > [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> > > > [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> > > > 
> > > > The error is coming from regmap code. According to git bisect, it is
> > > > caused by:
> > > > 
> > > > 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> > > > 	Author: Jon Hunter <jon-hunter at ti.com>
> > > > 	Date:   Fri Mar 1 11:22:47 2013 -0600
> > > > 
> > > > 	    gpio/omap: convert gpio irq domain to linear mapping
> > > > 
> > > > The commit does not anymore revert cleanly, and I haven't yet tried
> > > > crafting a manual revert, so any fix proposals/ideas are welcome...
> > > 
> > > Hmm this might be a bit trickier to fix. Obviously the real solution
> > > is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> > > 
> > > For the -rc cycle, it might be possible to fix this by adding a
> > > different irq_to_gpio() and gpio_to_irq() functions for omap1.
> > 
> > The commit reverts cleanly if we also revert
> > 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
> > service routine), which seems to be just some minor optimization. The
> > result is below, and with it 770 works again.
> 
> Hmm in this case it seems that we should just fix it rather than go back
> to the old code, so let's take a look at that first.

Does the following fix it for you or do we need to fix something else
there too?

Regards,

Tony


--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1094,6 +1094,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
 	const struct omap_gpio_platform_data *pdata;
 	struct resource *res;
 	struct gpio_bank *bank;
+	int irq_base;
 
 	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
 
@@ -1135,11 +1136,23 @@ static int omap_gpio_probe(struct platform_device *pdev)
 				pdata->get_context_loss_count;
 	}
 
-
-	bank->domain = irq_domain_add_linear(node, bank->width,
-					     &irq_domain_simple_ops, NULL);
-	if (!bank->domain)
+	/*
+	 * REVISIT: Once we have omap1 supporting  SPARSE_IRQ, we can drop
+	 * irq_alloc_descs() and irq_domain_add_legacy() and just do:
+	 *
+	 * bank->domain = irq_domain_add_linear(node, bank->width,
+	 *				     &irq_domain_simple_ops, NULL);
+	 * if (!bank->domain)
+	 *	return -ENODEV;
+	 */
+	irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
+	if (irq_base < 0) {
+		dev_err(dev, "Couldn't allocate IRQ numbers\n");
 		return -ENODEV;
+	}
+
+	bank->domain = irq_domain_add_legacy(node, bank->width, irq_base,
+					     0, &irq_domain_simple_ops, NULL);
 
 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
 		bank->set_dataout = _set_gpio_dataout_reg;


From swarren at wwwdotorg.org  Mon May 20 13:46:54 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 11:46:54 -0600
Subject: [PATCH 1/4] ARM: tegra: use #include for all device trees
In-Reply-To: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
References: <1368473072-10145-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <519A618E.4040400@wwwdotorg.org>

On 05/13/2013 01:24 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT
> files, so that gcc -E handles the entire include tree, and hence any of
> those files can #include some other file e.g. for constant definitions.
> 
> This allows future use of #defines and header files in order to define
> names for various constants, such as the IDs and flags in GPIO
> specifiers. Use of those features will increase the readability of the
> device tree files.

I have applied this series, with patch 3/4 replaced with V3 of that patch.


From swarren at wwwdotorg.org  Mon May 20 13:47:21 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 11:47:21 -0600
Subject: [PATCH V2 3/4] ARM: tegra: convert device tree files to use GPIO
 defines
In-Reply-To: <1369069845-7601-1-git-send-email-swarren@wwwdotorg.org>
References: <1369069845-7601-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <519A61A9.2040407@wwwdotorg.org>

On 05/20/2013 11:10 AM, Stephen Warren wrote:
> Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
> and some interrupts properties. Use standard GPIO flag defines too.

Applied (along with the reset of the series) to Tegra's for-3.11/dt branch.


From jason at lakedaemon.net  Mon May 20 13:48:05 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:48:05 -0400
Subject: [PATCH] ARM: dts: mvebu: Fix wrong the address reg value for
 the L2-cache node
In-Reply-To: <1369059207-32210-1-git-send-email-gregory.clement@free-electrons.com>
References: <1369059207-32210-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130520174805.GA31290@titan.lakedaemon.net>

On Mon, May 20, 2013 at 04:13:27PM +0200, Gregory CLEMENT wrote:
> During the conversion to the internal-regs' subnode, the L2-cache node
> haven not been converted (due to a wrong choice made by myself during
> the resolution of the merge conflict when I rebased the commit). This
> leads to wrong address for L2 cache which prevent it to be used on
> Armada 370. This commit fix the address reg of the e L2-cache node.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Mon May 20 13:51:54 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:51:54 -0400
Subject: [PATCH] arm: mvebu: enable the third USB interface on
 OpenBlocks AX3
In-Reply-To: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368720444-29357-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130520175154.GB31290@titan.lakedaemon.net>

On Thu, May 16, 2013 at 06:07:24PM +0200, Thomas Petazzoni wrote:
> Besides the two "classic" USB interfaces with normal USB ports on the
> front side, the PlatHome OpenBlocks AX3 uses the third USB interface
> of the Marvell SoC in the mini-PCIe connector. This allows certain
> mini-PCIe cards to expose parts of their functionality as a USB
> peripheral.
> 
> This commit enables this third USB interface in the OpenBlocks AX3
> Device Tree, and also adds comments on top of the two other USB
> interfaces so that the Device Tree makes it clear which USB interface
> at the SoC level matches which USB interface visible on the board.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts |    9 +++++++++
>  1 file changed, 9 insertions(+)

Applied to mvebu/dt with Willy's and Mr. Yamagata's Tested-by's

thx,

Jason.


From hvaibhav at ti.com  Mon May 20 13:55:58 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 20 May 2013 17:55:58 +0000
Subject: [PATCH-V2] ARM: OMAP2+: AM33xx: Fix missing reset status data
 to GFX hwmod
In-Reply-To: <alpine.DEB.2.02.1305201439020.6174@utopia.booyaka.com>
References: <1369057116-31423-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.02.1305201439020.6174@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC8EF8A@DBDE04.ent.ti.com>

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Monday, May 20, 2013 8:09 PM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH-V2] ARM: OMAP2+: AM33xx: Fix missing reset status
> data to GFX hwmod
> 
> On Mon, 20 May 2013, Vaibhav Hiremath wrote:
> 
> > GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
> > so update the GFX hwmod data with .rstst_off and .st_shift
> > information.
> >
> > Although it doesn't have impact on kernel boot, but this is
> > regression fix from original hwmod commit.
> >
> 
> Did it ever work?  If not, then it's not a regression, right?
> 

As we know none of the GFX sw is available in the mainline, so never got
exercised so far; but kernel boots up fine without any issues.
I was also confused a bit on this, but then thought, this could be regression
As it is fixing wrong/missing data without which GFX will not work.
May be I was wrong.

Thanks,
Vaibhav


From jason at lakedaemon.net  Mon May 20 13:58:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 13:58:27 -0400
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130516184658.0650f838@skate>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130516184658.0650f838@skate>
Message-ID: <20130520175827.GC31290@titan.lakedaemon.net>

On Thu, May 16, 2013 at 06:46:58PM +0200, Thomas Petazzoni wrote:
> Sebastian, Jason, Andrew, Gregory,
> 
> On Sat, 11 May 2013 03:08:00 +0200, Sebastian Hesselbarth wrote:
> > Marvell EBU SoCs share some common clock functions that register core
> > clocks or clock gates from SoC specific data. These clock drivers are
> > organized by function and over time the drivers filled up with #ifdefs
> > to separate different SoC specific code.
> > 
> > This patch set first adds a new element to clock gate descriptors to
> > allow to pass clk flags per clock gate. (Patch 1)
> > 
> > Then it restructures MVEBU clock drivers into common clock setup and
> > SoC specific files and Kconfig options. The driver's init functions
> > are also registered to get called with of_clk_init. (Patches 2, 3-6)
> > 
> > It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> > of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> > 
> > Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> > 
> > It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> > Armada 370 and XP are compile tested only and should get their Tested-by
> > from Thomas and Gregory, respectively.
> > 
> > @Mike: As this only touches MVEBU related code, I suggest to take it
> > all through the corresponding ARM branch.
> > 
> > Sebastian Hesselbarth (10):
> >   clk: mvebu: introduce per-clock-gate flags
> >   clk: mvebu: add common clock functions for core clk and clk gating
> >   clk: mvebu: add Dove SoC-centric clock init
> >   clk: mvebu: add Kirkwood SoC-centric clock init
> >   clk: mvebu: add Armada 370 SoC-centric clock init
> >   clk: mvebu: add Armada XP SoC-centric clock init
> >   ARM: dove: move DT boards to SoC-centric clock init
> >   ARM: kirkwood: move DT boards to SoC-centric clock init
> >   ARM: mvebu: move DT boards to SoC-centric clock init
> >   clk: mvebu: desintegrate obsolete file
> 
> Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> 
> I've tested on Armada 370 DB (after reverting the ARM core patch that
> prevents this platform from booting) and the Armada XP DB. Both boards
> boot fine, and detect PCIe devices as they should.
> 
> There is some conflict between this set of commits and the two commits
> that modify the PCIe clocks in my PCIe series. I've pushed a branch at
> https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
> which has the mvebu PCIe stuff + Sebastian patches on top of it, with
> the conflicts resolved. The tricky thing is that since Sebastian is
> adding new clock files, and then removing the old ones, it's pretty
> easy to "loose" the changes the two PCIe clock patches are doing. The
> branch above works on Armada 370/XP, so you can compare the clock files
> if needed.

hmm, in my haste yesterday, I did this in the opposite order (clk, then
pcie on top).  I'm going to reshuffle them because I don't want pcie
depending on and waiting for this clock series to be ready :)

The good news is everything (except kirkwood-pcie, ran out of time) made
it through linux-next!  Also, kisskb is now building mvebu_defconfig in
addition to all the other ones.

thx,

Jason.


From jason at lakedaemon.net  Mon May 20 14:02:54 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 14:02:54 -0400
Subject: [PATCHv10 5/9] clk: mvebu: create parent-child relation for
 PCIe clocks on Armada 370
In-Reply-To: <20130519204703.GP11137@titan.lakedaemon.net>
References: <1368719725-21265-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368719725-21265-6-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130519204703.GP11137@titan.lakedaemon.net>
Message-ID: <20130520180254.GD31290@titan.lakedaemon.net>

On Sun, May 19, 2013 at 04:47:03PM -0400, Jason Cooper wrote:
> On Thu, May 16, 2013 at 05:55:20PM +0200, Thomas Petazzoni wrote:
> > The Armada 370 has two gatable clocks for each PCIe interface, and we
> > want both of them to be enabled. We therefore make one of the two
> > clocks a child of the other, as we did for the sataX and sataXlnk
> > clocks on Armada XP.
> > 
> > Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> > Cc: Mike Turquette <mturquette at linaro.org>
> > ---
> >  drivers/clk/mvebu/clk-gating-ctrl.c |    4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> Patches 5 - 8 applied to mvebu/pcie, with a dep on Sebastian's clock
> rework and mvebu/of_pci.  Thanks for the head's up on the clk conflict.
> My resolution should match yours.  Please let me know if it doesn't.

As stated in the clk thread, I'm going to re-order this so pcie doesn't
depend on the clk series.

thx,

Jason.


From linus.walleij at linaro.org  Mon May 20 14:15:43 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 20:15:43 +0200
Subject: [PATCH] gpio: mxs: Use set and clear capabilities of the gpio
 controller
In-Reply-To: <1367244438-5322-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367244438-5322-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CACRpkdbXHvhnmk=QfmmZiYwdVedP2P5zY12cqRtb6QfYCu3o=A@mail.gmail.com>

On Mon, Apr 29, 2013 at 4:07 PM, Maxime Ripard
<maxime.ripard at free-electrons.com> wrote:

> The current driver doesn't use the set and clear registers found on the
> mxs gpio controller.
>
> This leads the generic gpio controller to be using some internal value
> to avoid looking up the value stored in the registers, making it behave
> pretty much like a cache.
>
> This raises some coherency problem when a gpio is not modified by the
> gpio controller, while it can easily be fixed by using the set and clear
> registers.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Patch applied for rc-fixes with Shawns ACK.

Yours,
Linus Walleij


From thomas.petazzoni at free-electrons.com  Mon May 20 14:15:49 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 20 May 2013 20:15:49 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130520175827.GC31290@titan.lakedaemon.net>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130516184658.0650f838@skate>
 <20130520175827.GC31290@titan.lakedaemon.net>
Message-ID: <20130520201549.475e50d0@skate>

Dear Jason Cooper,

On Mon, 20 May 2013 13:58:27 -0400, Jason Cooper wrote:

> > I've tested on Armada 370 DB (after reverting the ARM core patch
> > that prevents this platform from booting) and the Armada XP DB.
> > Both boards boot fine, and detect PCIe devices as they should.
> > 
> > There is some conflict between this set of commits and the two
> > commits that modify the PCIe clocks in my PCIe series. I've pushed
> > a branch at
> > https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
> > which has the mvebu PCIe stuff + Sebastian patches on top of it,
> > with the conflicts resolved. The tricky thing is that since
> > Sebastian is adding new clock files, and then removing the old
> > ones, it's pretty easy to "loose" the changes the two PCIe clock
> > patches are doing. The branch above works on Armada 370/XP, so you
> > can compare the clock files if needed.
> 
> hmm, in my haste yesterday, I did this in the opposite order (clk,
> then pcie on top).  I'm going to reshuffle them because I don't want
> pcie depending on and waiting for this clock series to be ready :)

Ok. Either way is fine with me, but it's true that chronologically, the
PCIe stuff has been around for way more time than the clk
restructure patches.

> The good news is everything (except kirkwood-pcie, ran out of time)
> made it through linux-next!  Also, kisskb is now building
> mvebu_defconfig in addition to all the other ones.

Ok. Gregory can give more details, but I believe we are also building
daily linux-next and Linus master for the mvebu_defconfig.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linus.walleij at linaro.org  Mon May 20 14:25:35 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 20:25:35 +0200
Subject: GPIO sysfs : set a wake source
In-Reply-To: <87k3mwv6ru.fsf@free.fr>
References: <87fvxwia0s.fsf@free.fr>
 <CACRpkdYjQD9phVtWNh2QGkZWOdEJyZENnYatXt7bd23bgqXitw@mail.gmail.com>
 <51926177.1050600@wwwdotorg.org> <87ip2ig1ez.fsf@free.fr>
 <CACRpkdbiZFutP_+u=ciuC6r-8N5FpkEnGVLH9LGDQ7pvdo3_-Q@mail.gmail.com>
 <87k3mwv6ru.fsf@free.fr>
Message-ID: <CACRpkdYX4w-efLMZKbEg4MS2odGi9jhj5FssNyi=LEhf32-P6w@mail.gmail.com>

On Sat, May 18, 2013 at 11:18 AM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
> Linus Walleij <linus.walleij at linaro.org> writes:

>> I think you need to think about how we join this modem closer
>> with the kernel instead of trying to paper it over using userspace
>> GPIO.

> Why ? I has only one UART and several GPIOs. What good would it be to add it in
> kernel ?

Because of the Subject: of this email.

You are starting to set up interrupts and wakeup sources and
other kernel proprietary stuff from userspace and basically (IMO)
trespassing on kernel territory.

>> I think the dilemma faced by embedded modems need to
>> be considered thoroughly here.
>
> As I said, it's an "old" modem. And if by embedded you mean "embedded in the
> SoC", it's not, it's a separate chip. The interconnect are the UART lines and
> the GPIO lines (solder lines as you pointed out).

I do not worry about the age of the modem. I would have thought
the same if you took the PCB out of a Robotics 28K8 and soldered
it onto some chipset and soldered a wakeup line on a GPIO pin.

I worry about userspace getting to know everthing about interrupts
and wake up sources and it just IMO *shouldn't*. I don't think
userspace should know anything about IRQs beside /proc/interrupts
but I'm CC:ing tglx so he can say something here.

Yours,
Linus Walleij


From gregory.clement at free-electrons.com  Mon May 20 14:56:16 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 20 May 2013 20:56:16 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130520201549.475e50d0@skate>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130516184658.0650f838@skate> <20130520175827.GC31290@titan.lakedaemon.net>
 <20130520201549.475e50d0@skate>
Message-ID: <519A71D0.7090103@free-electrons.com>

On 05/20/2013 08:15 PM, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Mon, 20 May 2013 13:58:27 -0400, Jason Cooper wrote:
> 
>>> I've tested on Armada 370 DB (after reverting the ARM core patch
>>> that prevents this platform from booting) and the Armada XP DB.
>>> Both boards boot fine, and detect PCIe devices as they should.
>>>
>>> There is some conflict between this set of commits and the two
>>> commits that modify the PCIe clocks in my PCIe series. I've pushed
>>> a branch at
>>> https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
>>> which has the mvebu PCIe stuff + Sebastian patches on top of it,
>>> with the conflicts resolved. The tricky thing is that since
>>> Sebastian is adding new clock files, and then removing the old
>>> ones, it's pretty easy to "loose" the changes the two PCIe clock
>>> patches are doing. The branch above works on Armada 370/XP, so you
>>> can compare the clock files if needed.
>>
>> hmm, in my haste yesterday, I did this in the opposite order (clk,
>> then pcie on top).  I'm going to reshuffle them because I don't want
>> pcie depending on and waiting for this clock series to be ready :)
> 
> Ok. Either way is fine with me, but it's true that chronologically, the
> PCIe stuff has been around for way more time than the clk
> restructure patches.
> 
>> The good news is everything (except kirkwood-pcie, ran out of time)
>> made it through linux-next!  Also, kisskb is now building
>> mvebu_defconfig in addition to all the other ones.
> 
> Ok. Gregory can give more details, but I believe we are also building
> daily linux-next and Linus master for the mvebu_defconfig.

Indeed every day we build linux-next for the mvebu_defconfig and for
multi_v7_defconfig (as mvebu is part of it). You can see the status here:

http://jenkins.free-electrons.com/job/linux-next/

However we don't build Linus master but we could add it.


> 
> Best regards,
> 
> Thomas
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregkh at linuxfoundation.org  Mon May 20 14:57:25 2013
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Mon, 20 May 2013 11:57:25 -0700
Subject: [PATCH v2 1/5] tty: xuartps: Remove suspend/resume functions
In-Reply-To: <51961E02.9020501@monstr.eu>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
 <1368467199-8702-2-git-send-email-soren.brinkmann@xilinx.com>
 <51961E02.9020501@monstr.eu>
Message-ID: <20130520185725.GA21134@kroah.com>

On Fri, May 17, 2013 at 02:09:38PM +0200, Michal Simek wrote:
> Hi Greg,
> 
> can you please add this patch to your tree?
> It is unrelated to clk changes which Soren sent.

Ok, will do.

greg k-h


From swarren at wwwdotorg.org  Mon May 20 15:08:04 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 13:08:04 -0600
Subject: [PATCH] ARM: tegra: enable host1x support by default
In-Reply-To: <1368868666-24754-1-git-send-email-acourbot@nvidia.com>
References: <1368868666-24754-1-git-send-email-acourbot@nvidia.com>
Message-ID: <519A7494.1050206@wwwdotorg.org>

On 05/18/2013 03:17 AM, Alexandre Courbot wrote:
> Tegra DRM support used to be enabled in the default Tegra configuration,
> but it now depends on CONFIG_TEGRA_HOST1X which is disabled by default.
> Enable CONFIG_TEGRA_HOST1X so that DRM support is compiled in again.

I've forwarded this to arm at kernel.org in the hope it can be pulled into
3.10. If not, I'll apply it to the Tegra tree once I hear back.


From swarren at wwwdotorg.org  Mon May 20 15:12:35 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 13:12:35 -0600
Subject: [PATCH] ARM: tegra: config: enable TPS65090 charger
Message-ID: <1369077155-1483-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

This is part of the TPS65090 MFD chip on the Dalmore board.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/configs/tegra_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 9de7693..4dbcd9f 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -130,6 +130,7 @@ CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May 20 15:15:11 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 13:15:11 -0600
Subject: [PATCH] ARM: tegra: Add charger subnode to tps65090 node
In-Reply-To: <519A42A7.5080208@nvidia.com>
References: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
 <5196C3F2.8070204@wwwdotorg.org> <519A4027.2020801@nvidia.com>
 <519A4108.2040606@wwwdotorg.org> <519A42A7.5080208@nvidia.com>
Message-ID: <519A763F.7030906@wwwdotorg.org>

On 05/20/2013 09:35 AM, Rhyland Klein wrote:
> On 5/20/2013 11:28 AM, Stephen Warren wrote:
>> On 05/20/2013 09:24 AM, Rhyland Klein wrote:
>>> On 5/17/2013 7:57 PM, Stephen Warren wrote:
>>>> On 04/10/2013 01:51 PM, Rhyland Klein wrote:
>>>>> The charger is now represented by a distinct subnode of the tps65090
>>>>> device. Add this node and enable low current charging with it.
>>>>
>>>> What's the status of the TPS60590 bindings; are they agreed upon by
>>>> NVIDIA, TI, and SlimLogic yet? In other words, is this patch still
>>>> something I should apply for 3.11, or does it need to be reworked?
>>>
>>> I haven't seen any discussion with slimlogic or TI about the tps65090.
>>> As far as I know the bindings for this driver haven't changed.
>>>
>>> Laxman, do you think the work on the palmas driver will impact the
>>> design of the bindings for the tps65090?
>>
>> Sorry, perhaps I'm confusing two different chips. If TPS65090 isn't
>> Palmas, then ignore my question. In which case, I suppose I should just
>> apply your patch then?
>>
> 
> I would say yes. The design of having the child node this way was how we
> had agreed worked best. The only reason I would see a significant reason
> to change this, is if something was decided that all mfd devices should
> start to follow some pattern which differed, which would mean changing
> existing bindings and therefore is unlikely.

OK, I have applied this patch to Tegra's for-3.11/dt branch. I also sent
a patch to actually enable the new driver in tegra_defconfig.


From swarren at wwwdotorg.org  Mon May 20 15:07:19 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 13:07:19 -0600
Subject: [PATCH] ARM: tegra: defconfig fixes
Message-ID: <1369076839-31787-1-git-send-email-swarren@wwwdotorg.org>

From: Alexandre Courbot <gnurou at gmail.com>

The AK8975 Kconfig option was renamed during the 3.10 merge window.
Adjust tegra_defconfig to enable the new name, so it's not missing
useful features.

Tegra DRM support used to be enabled in the default Tegra configuration,
but it now depends on CONFIG_TEGRA_HOST1X which is disabled by default.
Enable CONFIG_TEGRA_HOST1X so that DRM support is compiled in again.

Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
[swarren, squashed Alex's and my changes together]
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
Olof, Arnd,

Can this be taken into 3.10? Hopefully Linus won't mind defconfig changes
sneaking in now. If not, let me know, and I'll for it into Tegra's
for-3.11/dt branch instead. Thanks.

 arch/arm/configs/tegra_defconfig |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index a5f0485..f7ba3161 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -153,6 +153,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_DRM=y
+CONFIG_TEGRA_HOST1X=y
 CONFIG_DRM_TEGRA=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
@@ -202,7 +203,7 @@ CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
-CONFIG_SENSORS_AK8975=y
+CONFIG_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
-- 
1.7.10.4



From swarren at wwwdotorg.org  Mon May 20 15:15:50 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 13:15:50 -0600
Subject: [PATCH] ARM: tegra: config: enable TPS65090 charger
In-Reply-To: <1369077155-1483-1-git-send-email-swarren@wwwdotorg.org>
References: <1369077155-1483-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <519A7666.4000007@wwwdotorg.org>

On 05/20/2013 01:12 PM, Stephen Warren wrote:
> This is part of the TPS65090 MFD chip on the Dalmore board.

I have squashed this into Tegra's for-3.11/defconfig branch.


From tomasz.figa at gmail.com  Mon May 20 15:16:58 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Mon, 20 May 2013 21:16:58 +0200
Subject: [PATCH v3] net: dm9000: Allow instantiation using device tree
Message-ID: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>

This patch adds Device Tree support to dm9000 driver.

Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
---

Changes since v2:
 - corrected a typo in bindings documentation
 - removed redundant error message about failed memory allocation
Changes since v1:
 - dropped davicom,simple-phy property as it seems to be of no use
 - used of_get_mac_address() to get MAC address from device tree
 - replaced #ifdef CONFIG_OF around dm9000_parse_dt() with IS_ENABLED

 .../devicetree/bindings/net/davicom-dm9000.txt     | 26 ++++++++++++++
 .../devicetree/bindings/vendor-prefixes.txt        |  1 +
 drivers/net/ethernet/davicom/dm9000.c              | 42 ++++++++++++++++++++++
 3 files changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/davicom-dm9000.txt

diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
new file mode 100644
index 0000000..2d39c99
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
@@ -0,0 +1,26 @@
+Davicom DM9000 Fast Ethernet controller
+
+Required properties:
+- compatible = "davicom,dm9000";
+- reg : physical addresses and sizes of registers, must contain 2 entries:
+    first entry : address register,
+    second entry : data register.
+- interrupt-parent : interrupt controller to which the device is connected
+- interrupts : interrupt specifier specific to interrupt controller
+
+Optional properties:
+- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC address
+    to use (from firmware or bootloader)
+- davicom,no-eeprom : Configuration EEPROM is not available
+- davicom,ext-phy : Use external PHY
+
+Example:
+
+	ethernet at 18000000 {
+		compatible = "davicom,dm9000";
+		reg = <0x18000000 0x2 0x18000004 0x2>;
+		interrupt-parent = <&gpn>;
+		interrupts = <7 4>;
+		local-mac-address = [00 00 de ad be ef];
+		davicom,no-eeprom;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c43..2fe74e6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -18,6 +18,7 @@ chrp	Common Hardware Reference Platform
 cirrus	Cirrus Logic, Inc.
 cortina	Cortina Systems, Inc.
 dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
+davicom	DAVICOM Semiconductor, Inc.
 denx	Denx Software Engineering
 emmicro	EM Microelectronic
 epson	Seiko Epson Corp.
diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
index 9105465..7af6126 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -29,6 +29,8 @@
 #include <linux/spinlock.h>
 #include <linux/crc32.h>
 #include <linux/mii.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
 #include <linux/ethtool.h>
 #include <linux/dm9000.h>
 #include <linux/delay.h>
@@ -1358,6 +1360,31 @@ static const struct net_device_ops dm9000_netdev_ops = {
 #endif
 };
 
+static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
+{
+	struct dm9000_plat_data *pdata;
+	struct device_node *np = dev->of_node;
+	const void *mac_addr;
+
+	if (!IS_ENABLED(CONFIG_OF) || !np)
+		return NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return ERR_PTR(-ENOMEM);
+
+	if (of_find_property(np, "davicom,ext-phy", NULL))
+		pdata->flags |= DM9000_PLATF_EXT_PHY;
+	if (of_find_property(np, "davicom,no-eeprom", NULL))
+		pdata->flags |= DM9000_PLATF_NO_EEPROM;
+
+	mac_addr = of_get_mac_address(np);
+	if (mac_addr)
+		memcpy(pdata->dev_addr, mac_addr, sizeof(pdata->dev_addr));
+
+	return pdata;
+}
+
 /*
  * Search DM9000 board, allocate space and register it
  */
@@ -1373,6 +1400,12 @@ dm9000_probe(struct platform_device *pdev)
 	int i;
 	u32 id_val;
 
+	if (!pdata) {
+		pdata = dm9000_parse_dt(&pdev->dev);
+		if (IS_ERR(pdata))
+			return PTR_ERR(pdata);
+	}
+
 	/* Init network device */
 	ndev = alloc_etherdev(sizeof(struct board_info));
 	if (!ndev)
@@ -1683,11 +1716,20 @@ dm9000_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id dm9000_of_matches[] = {
+	{ .compatible = "davicom,dm9000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dm9000_of_matches);
+#endif
+
 static struct platform_driver dm9000_driver = {
 	.driver	= {
 		.name    = "dm9000",
 		.owner	 = THIS_MODULE,
 		.pm	 = &dm9000_drv_pm_ops,
+		.of_match_table = of_match_ptr(dm9000_of_matches),
 	},
 	.probe   = dm9000_probe,
 	.remove  = dm9000_drv_remove,
-- 
1.8.2.1



From gregory.clement at free-electrons.com  Mon May 20 15:18:42 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 20 May 2013 21:18:42 +0200
Subject: [RFC PATCH 2/5] ARM: mv78x00: Convert RD-78X00-mASA board to
 device tree
In-Reply-To: <5199F428.7000305@free-electrons.com>
References: <1368999578-19938-1-git-send-email-gregory.clement@free-electrons.com>
 <1368999578-19938-3-git-send-email-gregory.clement@free-electrons.com>
 <20130520095231.GE26249@lunn.ch> <5199F428.7000305@free-electrons.com>
Message-ID: <519A7712.3060903@free-electrons.com>

On 05/20/2013 12:00 PM, Gregory CLEMENT wrote:
> On 05/20/2013 11:52 AM, Andrew Lunn wrote:
>> On Sun, May 19, 2013 at 11:39:35PM +0200, Gregory CLEMENT wrote:
>>> This commit converts the 'RD-78X00-mASA' board to the Device
>>> Tree. Most of the devices are converted to the Device Tree, the only
>>> devices which have not their Device Tree bindings are the Gigabit
>>> Ethernet ones and remain instantiated in the old way.
>>>
>>> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
>>> ---
>>>  arch/arm/mach-mv78xx0/board-dt.c           |  3 +++
>>>  arch/arm/mach-mv78xx0/common.h             |  7 +++++++
>>>  arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 10 ++++++++++
>>>  3 files changed, 20 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-mv78xx0/board-dt.c b/arch/arm/mach-mv78xx0/board-dt.c
>>> index 4995fee..5111cbd 100644
>>> --- a/arch/arm/mach-mv78xx0/board-dt.c
>>> +++ b/arch/arm/mach-mv78xx0/board-dt.c
>>> @@ -26,6 +26,9 @@ static void __init mv78x00_dt_init(void)
>>>  	 */
>>>  	mv78xx0_init();
>>>  
>>> +	if (of_machine_is_compatible("marvell,rd-78x00-masa"))
>>> +		rd78x00_masa_init_dt();
>>> +
>>>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>>>  }
>>>  
>>> diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
>>> index 5e9485b..6e9140d 100644
>>> --- a/arch/arm/mach-mv78xx0/common.h
>>> +++ b/arch/arm/mach-mv78xx0/common.h
>>> @@ -17,6 +17,13 @@ struct mv_sata_platform_data;
>>>  /*
>>>   * Basic MV78xx0 init functions used early by machine-setup.
>>>   */
>>> +#ifdef CONFIG_MACH_RD78X00_MASA
>>> +void rd78x00_masa_init_dt(void);
>>> +#else
>>> +static inline void rd78x00_masa_init_dt(void) {};
>>> +#endif
>>> +
>>> +
>>>  int mv78xx0_core_index(void);
>>>  void mv78xx0_map_io(void);
>>>  void mv78xx0_init(void);
>>> diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
>>> index d2d06f3..8d88657 100644
>>> --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
>>> +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
>>> @@ -64,6 +64,16 @@ static void __init rd78x00_masa_init(void)
>>>  	}
>>>  }
>>>  
>>> +void __init rd78x00_masa_init_dt(void)
>>> +{
>>> +	/* Internal devices not ported to DT yet */
>>> +	mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
>>> +	mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
>>> +		mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
>>> +		mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
>>> +
>>> +}
>>
>> Hi Gregory
>>
>> First off, the indentation looks wrong. Might be a space/tab issue.
> 
> Thanks I will fix it
> 
>>
>> I would also be tempted to place this code into board-dt.c and not
>> touch or even compile rd78x00-masa-setup.c when using DT. If i
>> remember correctly, Jason had a patch for Kirkwood which centralized
>> all the ethernet setup code. You can maybe copy/paste that.
> 
> OK I will have a look on it.

Initially I wanted to avoid duplicating the platform data, which are
the PHY address for the ethernet. But for coherency I will do the same
that it have been done in mach-kirkwood.

>>
>>> +
>>>  static int __init rd78x00_pci_init(void)
>>>  {
>>>  	/*
>>> -- 
>>> 1.8.1.2
>>>
> 
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jason at lakedaemon.net  Mon May 20 15:30:09 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 15:30:09 -0400
Subject: [PATCHv4 9/9] arm: kirkwood: update defconfig with PCIe driver
 and board updates
In-Reply-To: <1368625022-25243-10-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368625022-25243-10-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130520193009.GF31290@titan.lakedaemon.net>

On Wed, May 15, 2013 at 03:37:02PM +0200, Thomas Petazzoni wrote:
> This commit enables the mvebu PCIe driver in kirkwood_defconfig and
> updates various options related to Kirkwood boards.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/configs/kirkwood_defconfig |    2 ++
>  1 file changed, 2 insertions(+)

Applied to mvebu/defconfig

thx,

Jason.


From jason at lakedaemon.net  Mon May 20 15:38:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 15:38:25 -0400
Subject: [PATCHv4 1/9] pci: mvebu: enable driver usage on Kirkwood
In-Reply-To: <1368625022-25243-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1368625022-25243-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1368625022-25243-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130520193825.GG31290@titan.lakedaemon.net>

On Wed, May 15, 2013 at 03:36:54PM +0200, Thomas Petazzoni wrote:
> We allow the pci-mvebu driver to be compiled on the Kirkwood platform,
> and add the 'marvell,kirkwood-pcie' as a compatible string supported
> by the driver.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Tested-by: Andrew Lunn <andrew at lunn.ch>
> ---
>  .../devicetree/bindings/pci/mvebu-pci.txt          |    1 +
>  drivers/pci/host/Kconfig                           |    2 +-
>  drivers/pci/host/pci-mvebu.c                       |    1 +
>  3 files changed, 3 insertions(+), 1 deletion(-)

Applied patches 1-8 to mvebu/pcie.

thx,

Jason.


From cov at codeaurora.org  Mon May 20 15:48:16 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Mon, 20 May 2013 15:48:16 -0400
Subject: [PATCHv2 3/5] clocksource: arch_timer: use virtual counters
In-Reply-To: <1368631441-28434-4-git-send-email-mark.rutland@arm.com>
References: <1368631441-28434-1-git-send-email-mark.rutland@arm.com>
 <1368631441-28434-4-git-send-email-mark.rutland@arm.com>
Message-ID: <519A7E00.7090600@codeaurora.org>

Hi Mark,

On 05/15/2013 11:23 AM, Mark Rutland wrote:

[...]

> Instead, this patch makes us always use the virtual counters. If we're a
> guest, or don't have hyp mode, we'll use the virtual timers, and as such
> don't care about CNTVOFF as long as it doesn't change in such a way as
> to make time travel backwards. If we do have hyp mode, and might be a
> KVM host, we have to use the physical timers, and require CNTVOFF to be
> zero so as to have a consistent view of time between the physical timers
> and virtual counters.

[...]

> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index a2b2541..053d846 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -287,7 +279,7 @@ static int __init arch_timer_register(void)
>  	cyclecounter.mult = clocksource_counter.mult;
>  	cyclecounter.shift = clocksource_counter.shift;
>  	timecounter_init(&timecounter, &cyclecounter,
> -			 arch_counter_get_cntpct());
> +			 arch_counter_get_cntvct());
>  
>  	if (arch_timer_use_virtual) {
>  		ppi = arch_timer_ppi[VIRT_PPI];

[...]


You say "we have to use the physical timers", but then change the code to read
exclusively from the virtual counter. I think it'd make more sense to just say
that CNTVOFF has to be zero (and why exactly?).

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From jason at lakedaemon.net  Mon May 20 15:51:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 15:51:35 -0400
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 2)
Message-ID: <20130520195135.GH31290@titan.lakedaemon.net>


The following changes since commit 00ed4a0bd964555fe9276f2299564c384d50ae7d:

  ARM: mvebu: Add a ranges entry to translate devbus childs (2013-05-13 16:23:47 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-2

for you to fetch changes up to 489e138eec96f529c5e8d4cd3ea45882ecdbf5ca:

  ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node (2013-05-20 17:44:54 +0000)

----------------------------------------------------------------
mvebu fixes for v3.10 (round 2)

 - mvebu (and orion SoCs)
    - remove init_dma_coherent_pool_size()

 - mvebu
    - fix ranges DT property
    - fix DT reg value for L2 cache
    - select ARCH_REQUIRE_GPIOLIB

 - orion legacy
    - fix num_resources and id for ge10 and ge11

----------------------------------------------------------------
Andrew Lunn (1):
      ARM: Orion: Remove redundant init_dma_coherent_pool_size()

Ezequiel Garcia (1):
      ARM: mvebu: Fix ranges entry on XP GP board

Gregory CLEMENT (3):
      ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform
      ARM: plat-orion: Fix num_resources and id for ge10 and ge11
      ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node

Thomas Petazzoni (1):
      arm: mvebu: fix the 'ranges' property to handle PCIe

 arch/arm/boot/dts/armada-370-xp.dtsi |  3 ++-
 arch/arm/boot/dts/armada-370.dtsi    |  5 +++--
 arch/arm/boot/dts/armada-xp-gp.dts   |  3 +++
 arch/arm/mach-kirkwood/common.c      |  6 ------
 arch/arm/mach-mvebu/Kconfig          |  1 +
 arch/arm/mach-mvebu/armada-370-xp.c  |  7 -------
 arch/arm/mach-orion5x/common.c       |  7 -------
 arch/arm/plat-orion/common.c         | 12 ++++++------
 8 files changed, 15 insertions(+), 29 deletions(-)


From jason at lakedaemon.net  Mon May 20 15:55:45 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 15:55:45 -0400
Subject: [GIT PULL] ARM: mvebu: cleanup for v3.11 (round 2)
Message-ID: <20130520195545.GI31290@titan.lakedaemon.net>


The following changes since commit 49ed97f751bfaea133ae5c44f1247db09b9ca144:

  ARM: Orion: Remove redundant init_dma_coherent_pool_size() (2013-05-13 19:35:39 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/cleanup-3.11-2

for you to fetch changes up to 84f013bc3a2e36365abff9416714e34c2993a4a5:

  ARM: mvebu: Remove init_irq declaration in machine description (2013-05-19 20:15:56 +0000)

----------------------------------------------------------------
mvebu cleanup for v3.11 (round 2)

 - mvebu: remove init_irq decl in machine desc.

----------------------------------------------------------------
Maxime Ripard (1):
      ARM: mvebu: Remove init_irq declaration in machine description

 arch/arm/mach-mvebu/armada-370-xp.c | 2 --
 1 file changed, 2 deletions(-)


From tomasz.figa at gmail.com  Mon May 20 15:58:37 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Mon, 20 May 2013 21:58:37 +0200
Subject: [PATCH] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
In-Reply-To: <1368630484-29939-1-git-send-email-t.figa@samsung.com>
References: <1368630484-29939-1-git-send-email-t.figa@samsung.com>
Message-ID: <1623377.nVo7nUcid2@flatron>

Hi Kukjin,

On Wednesday 15 of May 2013 17:08:04 Tomasz Figa wrote:
> This patch extends exynos_init_time() function to handle Exynos4210 rev0
> SoC, which differs in availability of system timers and needs different
> clocksource initialization.
> 
> This makes it possible to use exynos_init_time() function as init_time
> callback for all Exynos-based boards, including Universal_C210, which
> originally had to use samsung_timer_init().
> 
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig               |  3 ++-
>  arch/arm/mach-exynos/common.c              | 30
> +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h           
>   |  2 ++
>  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++---
>  4 files changed, 35 insertions(+), 5 deletions(-)

Could you pick this patch to your fixes branch?

This is a fix of a regression in handling Exynos4210 rev0 SoC (e.g. 
Universal C210 board) introduced by patches merged to 3.10.

Best regards,
Tomasz



From jason at lakedaemon.net  Mon May 20 16:00:29 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 16:00:29 -0400
Subject: [GIT PULL] ARM: mvebu: soc changes for v3.11 (round 1)
Message-ID: <20130520200029.GJ31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/soc-3.11-1

for you to fetch changes up to 3207792e62498f872d64f12e2fc368aa9d7e3795:

  arm: kirkwood: use the default of match table (2013-05-19 20:20:49 +0000)

----------------------------------------------------------------
mvebu soc changes for v3.11 (round 1)

 - kirkwood: use default of match table

----------------------------------------------------------------
Thomas Petazzoni (1):
      arm: kirkwood: use the default of match table

 arch/arm/mach-kirkwood/board-dt.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)


From tomasz.figa at gmail.com  Mon May 20 16:01:27 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Mon, 20 May 2013 22:01:27 +0200
Subject: [PATCH] ARM: SAMSUNG: devs: Add names to fimd0 IRQ resources
In-Reply-To: <1368630584-30147-1-git-send-email-t.figa@samsung.com>
References: <1368630584-30147-1-git-send-email-t.figa@samsung.com>
Message-ID: <2346119.JROXYaUvrv@flatron>

Hi Kukjin,

On Wednesday 15 of May 2013 17:09:44 Tomasz Figa wrote:
> Since commit 1977e6d8 (drm/exynos: change the method for getting the
> interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
> named. This patch fixes probe failure in non-DT cases by adding
> appropriate resource names to fimd0 platform device.
> 
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/plat-samsung/devs.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index 30c2fe2..0f9c3f4 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
>  #ifdef CONFIG_S5P_DEV_FIMD0
>  static struct resource s5p_fimd0_resource[] = {
>  	[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
> -	[1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
> -	[2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
> -	[3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
> +	[1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
> +	[2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
> +	[3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
>  };
> 
>  struct platform_device s5p_device_fimd0 = {

This is a fix of a regression introduced to 3.10-rc1. Could you apply this 
patch to your fixes branch, please?

Best regards,
Tomasz



From jason at lakedaemon.net  Mon May 20 16:03:58 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 16:03:58 -0400
Subject: [GIT PULL] ARM: mvebu: boards for v3.11 (round 1)
Message-ID: <20130520200358.GK31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/boards-3.11-1

for you to fetch changes up to 193da78bec1b510ab0a743348a7e9a2c24766268:

  ARM: Kirkwood: add DT support for Sheevaplug and Sheevaplug eSATA (2013-05-15 00:33:18 +0000)

----------------------------------------------------------------
mvebu boards for v3.11 (round 1)

 - kirkwood: add sheevaplug and sheevaplug eSATA

----------------------------------------------------------------
Simon Baatz (1):
      ARM: Kirkwood: add DT support for Sheevaplug and Sheevaplug eSATA

 arch/arm/mach-kirkwood/Kconfig            |  7 +++++++
 arch/arm/mach-kirkwood/Makefile           |  1 +
 arch/arm/mach-kirkwood/board-dt.c         |  4 ++++
 arch/arm/mach-kirkwood/board-sheevaplug.c | 27 +++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h           |  5 +++++
 5 files changed, 44 insertions(+)
 create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c


From tomasz.figa at gmail.com  Mon May 20 16:05:33 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Mon, 20 May 2013 22:05:33 +0200
Subject: [PATCH] rtc: max8998: Check for pdata presence before
 dereferencing
In-Reply-To: <1368630968-30460-1-git-send-email-t.figa@samsung.com>
References: <1368630968-30460-1-git-send-email-t.figa@samsung.com>
Message-ID: <5315595.u903qx3Wqg@flatron>

Hi Alessandro,

On Wednesday 15 of May 2013 17:16:08 Tomasz Figa wrote:
> Currently the driver can crash with a NULL pointer dereference if no
> pdata is provided, despite of successful registration of MFD part. This
> patch fixes the problem by adding a NULL check before dereferencing the
> pdata pointer.
> 
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/rtc/rtc-max8998.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/rtc/rtc-max8998.c b/drivers/rtc/rtc-max8998.c
> index 48b6612..d5af7ba 100644
> --- a/drivers/rtc/rtc-max8998.c
> +++ b/drivers/rtc/rtc-max8998.c
> @@ -285,7 +285,7 @@ static int max8998_rtc_probe(struct platform_device
> *pdev) info->irq, ret);
> 
>  	dev_info(&pdev->dev, "RTC CHIP NAME: %s\n", pdev->id_entry->name);
> -	if (pdata->rtc_delay) {
> +	if (pdata && pdata->rtc_delay) {
>  		info->lp3974_bug_workaround = true;
>  		dev_warn(&pdev->dev, "LP3974 with RTC REGERR option."
>  				" RTC updates will be extremely slow.\n");

Since this is a fix, could you apply this patch to your fixes branch for 
3.10-rc2, please?

Best regards,
Tomasz



From jason at lakedaemon.net  Mon May 20 16:09:12 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 16:09:12 -0400
Subject: [GIT PULL] ARM: mvebu: defconfig changes for v3.11 (round 2)
Message-ID: <20130520200912.GL31290@titan.lakedaemon.net>


The following changes since commit 366c0b76416ed15feb90ba4ef0bd8f03d62d1091:

  ARM: mvebu: Add support for USB storage class in mvebu_defconfig (2013-05-13 20:06:06 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/defconfig-3.11-2

for you to fetch changes up to 921b1ab0af2c5e0718e0e0ef334a91aa9c4507d4:

  arm: kirkwood: update defconfig with PCIe driver and board updates (2013-05-20 19:29:31 +0000)

----------------------------------------------------------------
mvebu defconfig changes for v3.11 (round 2)

 - mvebu
    - add PCI and USB

 - kirkwood
    - add DT sheevaplug, usb3 and pcie

----------------------------------------------------------------
Andrew Lunn (1):
      ARM: Kirkwood: Enable USB 3.0 in kirkwood_defconfig

Jason Cooper (1):
      ARM: kirkwood: enable Sheevaplug DT in defconfig

Thomas Petazzoni (2):
      arm: mvebu: update defconfig with PCI and USB support
      arm: kirkwood: update defconfig with PCIe driver and board updates

 arch/arm/configs/kirkwood_defconfig | 7 ++++---
 arch/arm/configs/mvebu_defconfig    | 3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)


From sylvester.nawrocki at gmail.com  Mon May 20 16:11:04 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Mon, 20 May 2013 22:11:04 +0200
Subject: [PATCH v3] net: dm9000: Allow instantiation using device tree
In-Reply-To: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>
References: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <519A8358.9040607@gmail.com>

On 05/20/2013 09:16 PM, Tomasz Figa wrote:
> This patch adds Device Tree support to dm9000 driver.
>
> Signed-off-by: Tomasz Figa<tomasz.figa at gmail.com>

Looks good. I'm going to test also this version at the end of this
week on Mini2440.

Reviewed-by: Sylwester Nawrocki <sylvester.nawrocki at gmail.com>


From jason at lakedaemon.net  Mon May 20 16:13:47 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 16:13:47 -0400
Subject: [GIT PULL] ARM: mvebu: dt changes for v3.11 (round 2)
Message-ID: <20130520201347.GM31290@titan.lakedaemon.net>


The following changes since commit 53e9cb1dcde882cc667497328eca776a9835f965:

  ARM: dove: add si5351 clock driver to CuBox DT (2013-05-13 20:14:56 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/dt-3.11-2

for you to fetch changes up to 8034891b81f0f7285c1efa3ae29e46b3f177536e:

  arm: mvebu: enable the third USB interface on OpenBlocks AX3 (2013-05-20 17:50:34 +0000)

----------------------------------------------------------------
mvebu dt changes for v3.11 (round 2)

 - mvebu
    - standard mmc binding for mvsdio users
    - add NOR flash to Armada XP-DB
    - add 3rd usb interface on OpenBlocks AX3

 - kirkwood
    - dts files for sheevaplug and sheevaplug eSATA

----------------------------------------------------------------
Ezequiel Garcia (1):
      ARM: mvebu: Add support for NOR flash device on Armada XP-DB board

Simon Baatz (2):
      ARM: mvebu: Use standard MMC binding for all users of mvsdio
      ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug

Thomas Petazzoni (1):
      arm: mvebu: enable the third USB interface on OpenBlocks AX3

 arch/arm/boot/dts/Makefile                         |  2 +
 arch/arm/boot/dts/armada-370-db.dts                |  1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |  1 +
 arch/arm/boot/dts/armada-370-rd.dts                |  1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |  4 +
 arch/arm/boot/dts/armada-xp-db.dts                 | 33 ++++++++
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   |  9 ++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |  1 +
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |  2 +
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |  2 +-
 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi  | 97 ++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts    | 40 +++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug.dts          | 45 ++++++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |  1 +
 arch/arm/boot/dts/kirkwood.dtsi                    |  4 +
 15 files changed, 242 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts


From s.hauer at pengutronix.de  Mon May 20 16:14:54 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 20 May 2013 22:14:54 +0200
Subject: [PATCH v3] net: dm9000: Allow instantiation using device tree
In-Reply-To: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>
References: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <20130520201454.GD32299@pengutronix.de>

On Mon, May 20, 2013 at 09:16:58PM +0200, Tomasz Figa wrote:
> This patch adds Device Tree support to dm9000 driver.
> 
> Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>

Looks good for me aswell, thanks.

Reviewed-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at arm.linux.org.uk  Mon May 20 16:15:36 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 May 2013 21:15:36 +0100
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <CADnq5_Pajy4jxLdd9QGBrUooWYFjfQRQgdbvbu9UDE8-7Tmm8g@mail.gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
 <20130519085920.GO18614@n2100.arm.linux.org.uk>
 <CADnq5_Pajy4jxLdd9QGBrUooWYFjfQRQgdbvbu9UDE8-7Tmm8g@mail.gmail.com>
Message-ID: <20130520201536.GY18614@n2100.arm.linux.org.uk>

On Mon, May 20, 2013 at 09:36:02AM -0400, Alex Deucher wrote:
> You can tell the xserver what size cursor you support when you call
> xf86_cursors_init() in the ddx.  Just expose a 32x64 or 64x32 ARGB
> cursor.  Most apps don't use a 64x64 cursor anyway.  I've used
> hardware with non-64x64 cursors and haven't run into any problems yet.

I guess the xf86 backend will fall back to software cursors if it gets
a cursor larger than the hardware supports, so maybe 64x32 will be
fine.

However, my comments concerning the less-than-64x64 size come from
David Airlie who said "X and userside programs expect 64x64 to work.
so its possibly pointless supporting anything less, as in you'd write
code but nobody would end up using it".

Note also that the generic DRM KMS code assumes cursor support at
64x64, and there's no generic way for a driver at present (that I know
of) to inform it of anything different.


From peterhuewe at gmx.de  Mon May 20 16:22:04 2013
From: peterhuewe at gmx.de (Peter Huewe)
Date: Mon, 20 May 2013 22:22:04 +0200
Subject: [PATCH] arm/mach-u300/dummyspichip: Use module_spi_driver to register
 driver
Message-ID: <1369081324-8062-1-git-send-email-peterhuewe@gmx.de>

Removing some boilerplate by using module_spi_driver instead of calling
register and unregister in the otherwise empty init/exit functions.

Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
---
 arch/arm/mach-u300/dummyspichip.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb6..aee609d 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -272,19 +272,7 @@ static struct spi_driver pl022_dummy_driver = {
 	.remove	= pl022_dummy_remove,
 };
 
-static int __init pl022_init_dummy(void)
-{
-	return spi_register_driver(&pl022_dummy_driver);
-}
-
-static void __exit pl022_exit_dummy(void)
-{
-	spi_unregister_driver(&pl022_dummy_driver);
-}
-
-module_init(pl022_init_dummy);
-module_exit(pl022_exit_dummy);
-
+module_spi_driver(pl022_dummy_driver);
 MODULE_AUTHOR("Linus Walleij <linus.walleij at stericsson.com>");
 MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
 MODULE_LICENSE("GPL");
-- 
1.8.1.5



From jason at lakedaemon.net  Mon May 20 16:19:59 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 16:19:59 -0400
Subject: [GIT PULL 1/2] of/pci dependency for mvebu/arm-soc
Message-ID: <20130520201959.GN31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/of_pci-3.11

for you to fetch changes up to 4e23d3f505e8acfeac7cc33d4113fbb5a25c3090:

  of/pci: Add of_pci_parse_bus_range() function (2013-05-19 20:30:10 +0000)

----------------------------------------------------------------
of/pci changes for v3.11

 - parse DT ranges property
 - add of_pci_get_devfn()
 - add of_pci_parse_bus_range()

Note:
 - mvebu/pcie will depend on this branch
 - work by LinusW and possibly Arnd will depend on this branch

----------------------------------------------------------------
Andrew Murray (1):
      of/pci: Provide support for parsing PCI DT ranges property

Thierry Reding (2):
      of/pci: Add of_pci_get_devfn() function
      of/pci: Add of_pci_parse_bus_range() function

 drivers/of/address.c       | 67 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/of/of_pci.c        | 59 ++++++++++++++++++++++++++++++++++++----
 include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++
 include/linux/of_pci.h     |  2 ++
 4 files changed, 171 insertions(+), 5 deletions(-)


From alexdeucher at gmail.com  Mon May 20 16:23:33 2013
From: alexdeucher at gmail.com (Alex Deucher)
Date: Mon, 20 May 2013 16:23:33 -0400
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <20130520201536.GY18614@n2100.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
 <20130519085920.GO18614@n2100.arm.linux.org.uk>
 <CADnq5_Pajy4jxLdd9QGBrUooWYFjfQRQgdbvbu9UDE8-7Tmm8g@mail.gmail.com>
 <20130520201536.GY18614@n2100.arm.linux.org.uk>
Message-ID: <CADnq5_O8nLi1=HOrXO0AeQuX17tGj05fhao4mmauzZ5h8Ciyaw@mail.gmail.com>

On Mon, May 20, 2013 at 4:15 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, May 20, 2013 at 09:36:02AM -0400, Alex Deucher wrote:
>> You can tell the xserver what size cursor you support when you call
>> xf86_cursors_init() in the ddx.  Just expose a 32x64 or 64x32 ARGB
>> cursor.  Most apps don't use a 64x64 cursor anyway.  I've used
>> hardware with non-64x64 cursors and haven't run into any problems yet.
>
> I guess the xf86 backend will fall back to software cursors if it gets
> a cursor larger than the hardware supports, so maybe 64x32 will be
> fine.
>
> However, my comments concerning the less-than-64x64 size come from
> David Airlie who said "X and userside programs expect 64x64 to work.
> so its possibly pointless supporting anything less, as in you'd write
> code but nobody would end up using it".
>
> Note also that the generic DRM KMS code assumes cursor support at
> 64x64, and there's no generic way for a driver at present (that I know
> of) to inform it of anything different.

It shouldn't be too hard to add a new cap for querying the cursor size
to the drm cap interface.

Alex


From jason at lakedaemon.net  Mon May 20 16:23:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 20 May 2013 16:23:27 -0400
Subject: [GIT PULL 2/2] ARM: mvebu: pcie changes for v3.11 (round 1)
In-Reply-To: <20130520201959.GN31290@titan.lakedaemon.net>
References: <20130520201959.GN31290@titan.lakedaemon.net>
Message-ID: <20130520202327.GO31290@titan.lakedaemon.net>


The following changes since commit 4e23d3f505e8acfeac7cc33d4113fbb5a25c3090:

  of/pci: Add of_pci_parse_bus_range() function (2013-05-19 20:30:10 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/pcie-3.11-1

for you to fetch changes up to bda7aabd6d9a473f14c94280d8dc6d2d9a299479:

  arm: mvebu: PCIe support is now available on mvebu (2013-05-20 19:18:44 +0000)

----------------------------------------------------------------
mvebu pcie DT support for v3.11 (round 1)

depends
 - mvebu/of_pci

----------------------------------------------------------------
Thomas Petazzoni (4):
      clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
      clk: mvebu: add more PCIe clocks for Armada XP
      pci: PCIe driver for Marvell Armada 370/XP systems
      arm: mvebu: PCIe support is now available on mvebu

 .../devicetree/bindings/pci/mvebu-pci.txt          | 220 ++++++
 arch/arm/mach-mvebu/Kconfig                        |   2 +
 drivers/clk/mvebu/clk-gating-ctrl.c                |  18 +-
 drivers/pci/Kconfig                                |   2 +
 drivers/pci/Makefile                               |   3 +
 drivers/pci/host/Kconfig                           |   8 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pci-mvebu.c                       | 880 +++++++++++++++++++++
 8 files changed, 1128 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
 create mode 100644 drivers/pci/host/Kconfig
 create mode 100644 drivers/pci/host/Makefile
 create mode 100644 drivers/pci/host/pci-mvebu.c


From linus.walleij at linaro.org  Mon May 20 16:36:15 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 May 2013 22:36:15 +0200
Subject: [PATCH] arm/mach-u300/dummyspichip: Use module_spi_driver to
 register driver
In-Reply-To: <1369081324-8062-1-git-send-email-peterhuewe@gmx.de>
References: <1369081324-8062-1-git-send-email-peterhuewe@gmx.de>
Message-ID: <CACRpkdZvkRh1jEL9rtZMDb1ZBezvYeijFRsJfruQ8igA1+axHQ@mail.gmail.com>

On Mon, May 20, 2013 at 10:22 PM, Peter Huewe <peterhuewe at gmx.de> wrote:

> Removing some boilerplate by using module_spi_driver instead of calling
> register and unregister in the otherwise empty init/exit functions.
>
> Signed-off-by: Peter Huewe <peterhuewe at gmx.de>

Applied to my U300 branch for v3.11, thanks!

Yours,
Linus Walleij


From swarren at wwwdotorg.org  Mon May 20 16:40:55 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 14:40:55 -0600
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
In-Reply-To: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
References: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <519A8A57.9060007@wwwdotorg.org>

On 05/16/2013 01:48 AM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> The pinctrldev_list_mutex is sinked into the functions that
> actually traverse the list and lock it there. The code makes
> much more sense in this way. All the callers are in
> non-performance critical paths and the code is way more
> readable this way.
> 
> Also refactor the function get_pinctrl_dev_from_devname() to
> follow the design pattern of get_pinctrl_dev_from_of_node()
> which is slightly simpler.

This seems fine on the surface, but I do have one question:

I think the pinctrl lock serves a couple of purposes:

1) Basic protection for accesses to the pinctrldev_list itself.

This patch seems just fine w.r.t. this point.

2) Preventing pinctrl drivers from being unregistered (and their modules
unloaded) when some operation is being performed on/to them.

So, that means some code is written as follows:

lock
find pinctrl device
perform operation on pinctrl device
unlock
// only now could the found pinctrl device be unregistered

However, I think this patch changes that to the following for some
operations:

lock
find pinctrl device
unlock
// now the found pinctrl device can be unregistered
perform operation on pinctrl device

Is this true here, or am I off-base?

If this isn't an issue, then the patch is fine by me. But, how is the
unregistration prevented while the device is being operated on then?


From swarren at wwwdotorg.org  Mon May 20 16:44:05 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 14:44:05 -0600
Subject: [PATCH v4 4/5] clk: add CLK_SET_RATE_NO_REPARENT flag
In-Reply-To: <1369056507-32521-5-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-5-git-send-email-james.hogan@imgtec.com>
Message-ID: <519A8B15.4040702@wwwdotorg.org>

On 05/20/2013 07:28 AM, James Hogan wrote:
> Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
> being reparented during clk_set_rate.
> 
> To avoid breaking existing platforms, all callers of clk_register_mux()
> are adjusted to pass the new flag. Platform maintainers are encouraged
> to remove the flag if they wish to allow mux reparenting on set_rate.

The Tegra parts,
Acked-by: Stephen Warren <swarren at nvidia.com>


From rklein at nvidia.com  Mon May 20 16:45:09 2013
From: rklein at nvidia.com (Rhyland Klein)
Date: Mon, 20 May 2013 16:45:09 -0400
Subject: [PATCH] ARM: tegra: Add charger subnode to tps65090 node
In-Reply-To: <519A763F.7030906@wwwdotorg.org>
References: <1365623505-6309-1-git-send-email-rklein@nvidia.com>
 <5196C3F2.8070204@wwwdotorg.org> <519A4027.2020801@nvidia.com>
 <519A4108.2040606@wwwdotorg.org> <519A42A7.5080208@nvidia.com>
 <519A763F.7030906@wwwdotorg.org>
Message-ID: <519A8B55.9080703@nvidia.com>

On 5/20/2013 3:15 PM, Stephen Warren wrote:
> On 05/20/2013 09:35 AM, Rhyland Klein wrote:
>> On 5/20/2013 11:28 AM, Stephen Warren wrote:
>>> On 05/20/2013 09:24 AM, Rhyland Klein wrote:
>>>> On 5/17/2013 7:57 PM, Stephen Warren wrote:
>>>>> On 04/10/2013 01:51 PM, Rhyland Klein wrote:
>>>>>> The charger is now represented by a distinct subnode of the tps65090
>>>>>> device. Add this node and enable low current charging with it.
>>>>>
>>>>> What's the status of the TPS60590 bindings; are they agreed upon by
>>>>> NVIDIA, TI, and SlimLogic yet? In other words, is this patch still
>>>>> something I should apply for 3.11, or does it need to be reworked?
>>>>
>>>> I haven't seen any discussion with slimlogic or TI about the tps65090.
>>>> As far as I know the bindings for this driver haven't changed.
>>>>
>>>> Laxman, do you think the work on the palmas driver will impact the
>>>> design of the bindings for the tps65090?
>>>
>>> Sorry, perhaps I'm confusing two different chips. If TPS65090 isn't
>>> Palmas, then ignore my question. In which case, I suppose I should just
>>> apply your patch then?
>>>
>>
>> I would say yes. The design of having the child node this way was how we
>> had agreed worked best. The only reason I would see a significant reason
>> to change this, is if something was decided that all mfd devices should
>> start to follow some pattern which differed, which would mean changing
>> existing bindings and therefore is unlikely.
> 
> OK, I have applied this patch to Tegra's for-3.11/dt branch. I also sent
> a patch to actually enable the new driver in tegra_defconfig.
> 

thanks, that was the next patch I was going to send :) Beat me to it.

-rhyland

-- 
nvpublic


From davem at davemloft.net  Mon May 20 17:04:31 2013
From: davem at davemloft.net (David Miller)
Date: Mon, 20 May 2013 14:04:31 -0700 (PDT)
Subject: [PATCH v3] net: dm9000: Allow instantiation using device tree
In-Reply-To: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>
References: <1369077418-5966-1-git-send-email-tomasz.figa@gmail.com>
Message-ID: <20130520.140431.198584024410831638.davem@davemloft.net>

From: Tomasz Figa <tomasz.figa at gmail.com>
Date: Mon, 20 May 2013 21:16:58 +0200

> This patch adds Device Tree support to dm9000 driver.
> 
> Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>

APplied.


From daniel at ffwll.ch  Mon May 20 17:13:04 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Mon, 20 May 2013 23:13:04 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
References: <5190D14A.7050904@canonical.com>
 <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
Message-ID: <20130520211304.GV12292@phenom.ffwll.local>

On Sat, May 18, 2013 at 03:47:43PM +0900, Inki Dae wrote:
> 2013/5/15 Rob Clark <robdclark at gmail.com>
> 
> > On Wed, May 15, 2013 at 1:19 AM, Inki Dae <inki.dae at samsung.com> wrote:
> > >
> > >
> > >> -----Original Message-----
> > >> From: Rob Clark [mailto:robdclark at gmail.com]
> > >> Sent: Tuesday, May 14, 2013 10:39 PM
> > >> To: Inki Dae
> > >> Cc: linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham; YoungJun
> > >> Cho; linux-arm-kernel at lists.infradead.org; linux-media at vger.kernel.org
> > >> Subject: Re: Introduce a new helper framework for buffer synchronization
> > >>
> > >> On Mon, May 13, 2013 at 10:52 PM, Inki Dae <inki.dae at samsung.com>
> > wrote:
> > >> >> well, for cache management, I think it is a better idea.. I didn't
> > >> >> really catch that this was the motivation from the initial patch, but
> > >> >> maybe I read it too quickly.  But cache can be decoupled from
> > >> >> synchronization, because CPU access is not asynchronous.  For
> > >> >> userspace/CPU access to buffer, you should:
> > >> >>
> > >> >>   1) wait for buffer
> > >> >>   2) prepare-access
> > >> >>   3)  ... do whatever cpu access to buffer ...
> > >> >>   4) finish-access
> > >> >>   5) submit buffer for new dma-operation
> > >> >>
> > >> >
> > >> >
> > >> > For data flow from CPU to DMA device,
> > >> > 1) wait for buffer
> > >> > 2) prepare-access (dma_buf_begin_cpu_access)
> > >> > 3) cpu access to buffer
> > >> >
> > >> >
> > >> > For data flow from DMA device to CPU
> > >> > 1) wait for buffer
> > >>
> > >> Right, but CPU access isn't asynchronous (from the point of view of
> > >> the CPU), so there isn't really any wait step at this point.  And if
> > >> you do want the CPU to be able to signal a fence from userspace for
> > >> some reason, you probably what something file/fd based so the
> > >> refcnting/cleanup when process dies doesn't leave some pending DMA
> > >> action wedged.  But I don't really see the point of that complexity
> > >> when the CPU access isn't asynchronous in the first place.
> > >>
> > >
> > > There was my missing comments, please see the below sequence.
> > >
> > > For data flow from CPU to DMA device and then from DMA device to CPU,
> > > 1) wait for buffer <- at user side - ioctl(fd, DMA_BUF_GET_FENCE, ...)
> > >         - including prepare-access (dma_buf_begin_cpu_access)
> > > 2) cpu access to buffer
> > > 3) wait for buffer <- at device driver
> > >         - but CPU is already accessing the buffer so blocked.
> > > 4) signal <- at user side - ioctl(fd, DMA_BUF_PUT_FENCE, ...)
> > > 5) the thread, blocked at 3), is waked up by 4).
> > >         - and then finish-access (dma_buf_end_cpu_access)
> >
> > right, I understand you can have background threads, etc, in
> > userspace.  But there are already plenty of synchronization primitives
> > that can be used for cpu->cpu synchronization, either within the same
> > process or between multiple processes.  For cpu access, even if it is
> > handled by background threads/processes, I think it is better to use
> > the traditional pthreads or unix synchronization primitives.  They
> > have existed forever, they are well tested, and they work.
> >
> > So while it seems nice and orthogonal/clean to couple cache and
> > synchronization and handle dma->cpu and cpu->cpu and cpu->dma in the
> > same generic way, but I think in practice we have to make things more
> > complex than they otherwise need to be to do this.  Otherwise I think
> > we'll be having problems with badly behaved or crashing userspace.
> >
> >
> Right, this is very important. I think it's not esay to solve this
> issue. Aand at least for ARM based embedded system, such feature is useful
> to us; coupling cache operation and buffer synchronization. I'd like to
> collect other opinions and advices to solve this issue.

Maybe we have a bit a misunderstanding here. The kernel really should take
care of sync and cache coherency, and I agree that with the current
dma_buf code (and the proposed fences) that part is still a bit hazy. But
the kernel should not allow userspace to block access to a buffer until
userspace is done. It should only sync with any oustanding fences and
flush buffers before that userspace access happens.

Then the kernel would again flush caches on the next dma access (which
hopefully is only started once userspace completed access). Atm this isn't
possible in an efficient way since the dma_buf api only exposes map/unmap
attachment and not a function to just sync an existing mapping like
dma_sync_single_for_device. I guess we should add a
dma_buf_sync_attachment interface for that - we already have range-based
cpu sync support with the begin/end_cpu_access interfaces.

Yours, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From sboyd at codeaurora.org  Mon May 20 17:16:42 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 20 May 2013 14:16:42 -0700
Subject: [PATCH v4 2/5] clk: move some parent related functions upwards
In-Reply-To: <1369056507-32521-3-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-3-git-send-email-james.hogan@imgtec.com>
Message-ID: <519A92BA.1090702@codeaurora.org>

On 05/20/13 06:28, James Hogan wrote:
> Move some parent related functions up in clk.c so they can be used by
> the modifications in the following patch which enables clock reparenting
> during set_rate. No other changes are made so this patch makes no
> functional difference in isolation. This is separate from the following
> patch primarily to ease readability of that patch.
>
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org

Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Mon May 20 17:17:16 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 20 May 2013 14:17:16 -0700
Subject: [PATCH v4 3/5] clk: add support for clock reparent on set_rate
In-Reply-To: <1369056507-32521-4-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-4-git-send-email-james.hogan@imgtec.com>
Message-ID: <519A92DC.2030208@codeaurora.org>

On 05/20/13 06:28, James Hogan wrote:
> diff --git a/Documentation/clk.txt b/Documentation/clk.txt
> index b9911c2..3110ba4 100644
> --- a/Documentation/clk.txt
> +++ b/Documentation/clk.txt
> @@ -70,6 +70,10 @@ the operations defined in clk.h:
>  						unsigned long parent_rate);
>  		long		(*round_rate)(struct clk_hw *hw, unsigned long,
>  						unsigned long *);
> +		long		(*determine_rate)(struct clk_hw *hw,
> +						unsigned long rate,
> +						unsigned long *best_parent_rate,
> +						struct clk **best_parent_clk);
>  		int		(*set_parent)(struct clk_hw *hw, u8 index);
>  		u8		(*get_parent)(struct clk_hw *hw);
>  		int		(*set_rate)(struct clk_hw *hw, unsigned long);

Can you update the clock hardware characteristics table as well?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From gmbnomis at gmail.com  Mon May 20 17:19:31 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 20 May 2013 23:19:31 +0200
Subject: [PATCH v3 1/7] net: mv643xx_eth: add Device Tree bindings
In-Reply-To: <1367854420-8006-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367854420-8006-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130520211930.GA25725@schnuecks.de>

Hi Sebastian,

On Mon, May 06, 2013 at 05:33:34PM +0200, Sebastian Hesselbarth wrote:
> From: Florian Fainelli <florian at openwrt.org>
> 
> This patch adds Device Tree bindings following the already defined
> bindings at Documentation/devicetree/bindings/marvell.txt. The binding
> documentation is also enhanced with new optionnal properties required
> for supporting certain devices (RX/TX queue and SRAM). Since we now have
> proper support for the orion MDIO bus driver, there is no need to fiddle
> around with device tree phandles. PHY-less (MAC connected to switch)
> configurations are supported by not specifying any phy phandle for an
> ethernet node.
> 
> Signed-off-by: Florian Fainelli <florian at openwrt.org>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Changelog:
> v2->v3:
> - rebase on top of mv643xx_eth clean-ups
> - do not reparse existing platform_data
> - use managed devm_kzalloc for parsed platform_data
> - use of_property_read_u32 where applicable
> - add phy_node to platform_data
> - use of_connect_phy if DT phy node was found
> 
> v1->v2:
> - properly ifdef of_platform_bus_probe with CONFIG_OF
> - handle of_platform_bus_probe errors and cleanup accordingly
> - use of_property_read_u32 where applicable
> - parse "duplex" and "speed" property in PHY-less configuration
> 
> Cc: Grant Likely <grant.likely at linaro.org>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Rob Landley <rob at landley.net>
> Cc: Lennert Buytenhek <buytenh at wantstofly.org>
> Cc: David Miller <davem at davemloft.net>
> Cc: Florian Fainelli <florian at openwrt.org>
> Cc: Arnaud Patard <arnaud.patard at rtp-net.org>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Jean-Francois Moine <moinejf at free.fr>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Simon Guinot <simon.guinot at sequanux.org>
> Cc: Jamie Lentin <jm at lentin.co.uk>
> Cc: Michael Walle <michael at walle.cc>
> Cc: Eric Hutter <hutter.eric at gmail.com>
> Cc: Joshua Coombs <josh.coombs at gmail.com>
> Cc: Willy Tarreau <w at 1wt.eu>
> Cc: Simon Baatz <gmbnomis at gmail.com>
> Cc: Alan M Butler <alanbutty12 at gmail.com>
> Cc: Nigel Roberts <nigel at nobiscuit.com>
> Cc: Valentin Longchamp <valentin.longchamp at keymile.com>
> Cc: Stefan Peter <s.peter at mpl.ch>
> Cc: Arnaud Ebalard <arno at natisbad.org>
> Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
> Cc: netdev at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  Documentation/devicetree/bindings/marvell.txt |   22 +++++-
>  drivers/net/ethernet/marvell/mv643xx_eth.c    |  108 ++++++++++++++++++++++++-
>  include/linux/mv643xx_eth.h                   |    3 +
>  3 files changed, 128 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/marvell.txt b/Documentation/devicetree/bindings/marvell.txt
> index f7a0da6..73ea12f 100644
> --- a/Documentation/devicetree/bindings/marvell.txt
> +++ b/Documentation/devicetree/bindings/marvell.txt
> @@ -112,11 +112,13 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
>     Required properties:
>       - #address-cells : <1>
>       - #size-cells : <0>
> -     - compatible : "marvell,mv64360-eth-block"
> +     - compatible : "marvell,mv64360-eth-block", "marvell,mv643xx-eth-block"
>       - reg : Offset and length of the register set for this block
>  
>     Optional properties:
>       - clocks : Phandle to the clock control device and gate bit
> +     - tx-csum-limit : Hardware limit above which transmit checksumming
> +                       is disabled.
>  
>     Example Discovery Ethernet block node:
>       ethernet-block at 2000 {
> @@ -133,7 +135,7 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
>  
>     Required properties:
>       - device_type : Should be "network".
> -     - compatible : Should be "marvell,mv64360-eth".
> +     - compatible : Should be "marvell,mv64360-eth", "marvell,mv643xx-eth"
>       - reg : Should be <0>, <1>, or <2>, according to which registers
>         within the silicon block the device uses.
>       - interrupts : <a> where a is the interrupt number for the port.
> @@ -143,6 +145,22 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
>         controller.
>       - local-mac-address : 6 bytes, MAC address
>  
> +   Optional properties:
> +     - clocks : Phandle to the clock control device and gate bit
> +     - clock-names : String describing the clock gate bit
> +     - speed : Speed to force the link (10, 100, 1000), used when no
> +               phy property is defined
> +     - duplex : Duplex to force the link (0: half, 1: full), used when no
> +               phy property is defined
> +     - rx-queue-count : number of RX queues to use
> +     - tx-queue-count : number of TX queues to use
> +     - rx-queue-size : size of the RX queue (in bytes)
> +     - tx-queue-size : size of the TX queue (in bytes)
> +     - rx-sram-addr : address of the SRAM for RX path (non 0 means used)
> +     - rx-sram-size : size of the SRAM for RX path (non 0 means used)
> +     - tx-sram-addr : address of the SRAM for TX path (non 0 means used)
> +     - tx-sram-size : size of the SRAM for TX path (non 0 means used)
> +
>     Example Discovery Ethernet port node:
>       ethernet at 0 {
>  	     device_type = "network";
> diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
> index d0afeea..efa5a2f 100644
> --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> @@ -60,6 +60,11 @@
>  #include <linux/types.h>
>  #include <linux/slab.h>
>  #include <linux/clk.h>
> +#include <linux/stringify.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_mdio.h>
> +#include <linux/of_net.h>
>  
>  static char mv643xx_eth_driver_name[] = "mv643xx_eth";
>  static char mv643xx_eth_driver_version[] = "1.4";
> @@ -2450,13 +2455,22 @@ static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
>  	}
>  }
>  
> +static const struct of_device_id mv643xx_eth_match[] = {
> +	{ .compatible = "marvell,mv64360-eth" },
> +	{ .compatible = "marvell,mv643xx-eth" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mv643xx_eth_match);
> +
>  static int mv643xx_eth_shared_probe(struct platform_device *pdev)
>  {
>  	static int mv643xx_eth_version_printed;
> +	struct device_node *np = pdev->dev.of_node;
>  	struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
>  	struct mv643xx_eth_shared_private *msp;
>  	const struct mbus_dram_target_info *dram;
>  	struct resource *res;
> +	int tx_csum_limit = 0;
>  
>  	if (!mv643xx_eth_version_printed++)
>  		pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
> @@ -2485,13 +2499,21 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
>  	if (dram)
>  		mv643xx_eth_conf_mbus_windows(msp, dram);
>  
> -	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
> -					pd->tx_csum_limit : 9 * 1024;
> +	if (np)
> +		of_property_read_u32(np, "tx-csum-limit", &tx_csum_limit);
> +	else
> +		tx_csum_limit = pd->tx_csum_limit;
> +
> +	msp->tx_csum_limit = tx_csum_limit ? tx_csum_limit : 9 * 1024;
>  	infer_hw_params(msp);
>  
>  	platform_set_drvdata(pdev, msp);
>  
> +#ifdef CONFIG_OF
> +	return of_platform_bus_probe(np, mv643xx_eth_match, &pdev->dev);

I have tested this on Kirkwood (Sheevaplug eSATA). When using
mv643xx_eth as a module with a built-in mvmdio the GbE port works. 
However, when unloading the mv643xx_eth module and loading it again,
the second call to of_platform_bus_probe() results in a warning:

[  190.542992] WARNING: at fs/sysfs/dir.c:530 sysfs_add_one+0x7c/0xa4()         
[  190.549372] sysfs: cannot create duplicate filename '/devices/ocp.0/f1072000.
ethernet-controller/0.ethernet-port'                                            

(Looks more like a problem of of_platform_bus_probe() than a problem
in the driver?)

> +#else
>  	return 0;
> +#endif
>  }
>  
>  static int mv643xx_eth_shared_remove(struct platform_device *pdev)
> @@ -2505,12 +2527,20 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static const struct of_device_id mv643xx_eth_shared_match[] = {
> +	{ .compatible = "marvell,mv64360-eth-block" },
> +	{ .compatible = "marvell,mv643xx-eth-block" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_match);
> +
>  static struct platform_driver mv643xx_eth_shared_driver = {
>  	.probe		= mv643xx_eth_shared_probe,
>  	.remove		= mv643xx_eth_shared_remove,
>  	.driver = {
>  		.name	= MV643XX_ETH_SHARED_NAME,
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(mv643xx_eth_shared_match),
>  	},
>  };
>  
> @@ -2669,6 +2699,68 @@ static const struct net_device_ops mv643xx_eth_netdev_ops = {
>  #endif
>  };
>  
> +#ifdef CONFIG_OF
> +static int mv643xx_eth_of_probe(struct platform_device *pdev)
> +{
> +	struct mv643xx_eth_platform_data *pd;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct device_node *shared = of_get_parent(np);
> +	const int *prop;
> +	const char *mac_addr;
> +
> +	if (pdev->dev.platform_data || !pdev->dev.of_node)
> +		return 0;
> +
> +	pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
> +	if (!pd)
> +		return -ENOMEM;
> +
> +	pdev->dev.platform_data = pd;
> +
> +	pd->shared = of_find_device_by_node(shared);
> +	if (!pd->shared)
> +		return -ENODEV;
> +
> +	if (of_property_read_u32(np, "reg", &pd->port_number))
> +		return -EINVAL;
> +
> +	pd->phy_node = of_parse_phandle(np, "phy", 0);
> +	if (!pd->phy_node) {
> +		pd->phy_addr = MV643XX_ETH_PHY_NONE;
> +
> +		of_property_read_u32(np, "speed", &pd->speed);
> +		of_property_read_u32(np, "duplex", &pd->duplex);
> +	}
> +
> +	mac_addr = of_get_mac_address(np);
> +	if (mac_addr)
> +		memcpy(pd->mac_addr, mac_addr, ETH_ALEN);
> +
> +#define rx_tx_queue_sram_property(_name)				\
> +	do {								\
> +		prop = of_get_property(np, __stringify(_name), NULL);	\
> +		if (prop)						\
> +			pd->_name = be32_to_cpup(prop);			\
> +	} while (0)
> +
> +	rx_tx_queue_sram_property(rx_queue_count);
> +	rx_tx_queue_sram_property(tx_queue_count);
> +	rx_tx_queue_sram_property(rx_queue_size);
> +	rx_tx_queue_sram_property(tx_queue_size);
> +	rx_tx_queue_sram_property(rx_sram_addr);
> +	rx_tx_queue_sram_property(rx_sram_size);
> +	rx_tx_queue_sram_property(tx_sram_addr);
> +	rx_tx_queue_sram_property(rx_sram_size);
> +
> +	return 0;
> +}
> +#else
> +static inline int mv643xx_eth_of_probe(struct platform_device *dev)
> +{
> +	return 0;
> +}
> +#endif
> +
>  static int mv643xx_eth_probe(struct platform_device *pdev)
>  {
>  	struct mv643xx_eth_platform_data *pd;
> @@ -2677,6 +2769,10 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
>  	struct resource *res;
>  	int err;
>  
> +	err = mv643xx_eth_of_probe(pdev);
> +	if (err)
> +		return err;
> +
>  	pd = pdev->dev.platform_data;
>  	if (pd == NULL) {
>  		dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");


If the clock isn't already enabled (mvmdio and mv643xx_eth both built
as modules), a delay seems to be necessary in mv643xx_eth_probe()
after enabling the clock on my hardware.  Otherwise the device hangs. 
Andrew found the same in the past (see [1]).  udelay(50) seems to be
sufficient in my case.

> @@ -2717,7 +2813,12 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
>  	netif_set_real_num_rx_queues(dev, mp->rxq_count);
>  
>  	if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
> -		mp->phy = phy_scan(mp, pd->phy_addr);
> +		if (pd->phy_node)
> +			mp->phy = of_phy_connect(mp->dev, pd->phy_node,
> +						mv643xx_eth_adjust_link, 0,
> +						PHY_INTERFACE_MODE_GMII);

of_phy_connect() returns NULL in case of an error and no ERR_PTR.

- Simon

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-June/103521.html


From gmbnomis at gmail.com  Mon May 20 17:27:08 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 20 May 2013 23:27:08 +0200
Subject: [PATCH v3 6/7] ARM: kirkwood: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <1367854420-8006-7-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367854420-8006-7-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130520212708.GA26519@schnuecks.de>

Hi Sebastian,

On Mon, May 06, 2013 at 05:33:39PM +0200, Sebastian Hesselbarth wrote:
> This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
> Kirkwood boards. Phy nodes are also added with reg property set on a
> per-board basis.
...
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index fada7e6..c01a273 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -202,5 +202,57 @@
>  			clocks = <&gate_clk 4>;
>  			status = "disabled";
>  		};
> +
> +		mdio: mdio-bus at 72004 {
> +			compatible = "marvell,orion-mdio";
> +			reg = <0x72004 0x84>;
> +			interrupts = <11>;

Shouldn't this be 46?

- Simon



From daniel at ffwll.ch  Mon May 20 17:30:33 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Mon, 20 May 2013 23:30:33 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <20130520211304.GV12292@phenom.ffwll.local>
References: <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
Message-ID: <20130520213033.GW12292@phenom.ffwll.local>

On Mon, May 20, 2013 at 11:13:04PM +0200, Daniel Vetter wrote:
> On Sat, May 18, 2013 at 03:47:43PM +0900, Inki Dae wrote:
> > 2013/5/15 Rob Clark <robdclark at gmail.com>
> > 
> > > On Wed, May 15, 2013 at 1:19 AM, Inki Dae <inki.dae at samsung.com> wrote:
> > > >
> > > >
> > > >> -----Original Message-----
> > > >> From: Rob Clark [mailto:robdclark at gmail.com]
> > > >> Sent: Tuesday, May 14, 2013 10:39 PM
> > > >> To: Inki Dae
> > > >> Cc: linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham; YoungJun
> > > >> Cho; linux-arm-kernel at lists.infradead.org; linux-media at vger.kernel.org
> > > >> Subject: Re: Introduce a new helper framework for buffer synchronization
> > > >>
> > > >> On Mon, May 13, 2013 at 10:52 PM, Inki Dae <inki.dae at samsung.com>
> > > wrote:
> > > >> >> well, for cache management, I think it is a better idea.. I didn't
> > > >> >> really catch that this was the motivation from the initial patch, but
> > > >> >> maybe I read it too quickly.  But cache can be decoupled from
> > > >> >> synchronization, because CPU access is not asynchronous.  For
> > > >> >> userspace/CPU access to buffer, you should:
> > > >> >>
> > > >> >>   1) wait for buffer
> > > >> >>   2) prepare-access
> > > >> >>   3)  ... do whatever cpu access to buffer ...
> > > >> >>   4) finish-access
> > > >> >>   5) submit buffer for new dma-operation
> > > >> >>
> > > >> >
> > > >> >
> > > >> > For data flow from CPU to DMA device,
> > > >> > 1) wait for buffer
> > > >> > 2) prepare-access (dma_buf_begin_cpu_access)
> > > >> > 3) cpu access to buffer
> > > >> >
> > > >> >
> > > >> > For data flow from DMA device to CPU
> > > >> > 1) wait for buffer
> > > >>
> > > >> Right, but CPU access isn't asynchronous (from the point of view of
> > > >> the CPU), so there isn't really any wait step at this point.  And if
> > > >> you do want the CPU to be able to signal a fence from userspace for
> > > >> some reason, you probably what something file/fd based so the
> > > >> refcnting/cleanup when process dies doesn't leave some pending DMA
> > > >> action wedged.  But I don't really see the point of that complexity
> > > >> when the CPU access isn't asynchronous in the first place.
> > > >>
> > > >
> > > > There was my missing comments, please see the below sequence.
> > > >
> > > > For data flow from CPU to DMA device and then from DMA device to CPU,
> > > > 1) wait for buffer <- at user side - ioctl(fd, DMA_BUF_GET_FENCE, ...)
> > > >         - including prepare-access (dma_buf_begin_cpu_access)
> > > > 2) cpu access to buffer
> > > > 3) wait for buffer <- at device driver
> > > >         - but CPU is already accessing the buffer so blocked.
> > > > 4) signal <- at user side - ioctl(fd, DMA_BUF_PUT_FENCE, ...)
> > > > 5) the thread, blocked at 3), is waked up by 4).
> > > >         - and then finish-access (dma_buf_end_cpu_access)
> > >
> > > right, I understand you can have background threads, etc, in
> > > userspace.  But there are already plenty of synchronization primitives
> > > that can be used for cpu->cpu synchronization, either within the same
> > > process or between multiple processes.  For cpu access, even if it is
> > > handled by background threads/processes, I think it is better to use
> > > the traditional pthreads or unix synchronization primitives.  They
> > > have existed forever, they are well tested, and they work.
> > >
> > > So while it seems nice and orthogonal/clean to couple cache and
> > > synchronization and handle dma->cpu and cpu->cpu and cpu->dma in the
> > > same generic way, but I think in practice we have to make things more
> > > complex than they otherwise need to be to do this.  Otherwise I think
> > > we'll be having problems with badly behaved or crashing userspace.
> > >
> > >
> > Right, this is very important. I think it's not esay to solve this
> > issue. Aand at least for ARM based embedded system, such feature is useful
> > to us; coupling cache operation and buffer synchronization. I'd like to
> > collect other opinions and advices to solve this issue.
> 
> Maybe we have a bit a misunderstanding here. The kernel really should take
> care of sync and cache coherency, and I agree that with the current
> dma_buf code (and the proposed fences) that part is still a bit hazy. But
> the kernel should not allow userspace to block access to a buffer until
> userspace is done. It should only sync with any oustanding fences and
> flush buffers before that userspace access happens.
> 
> Then the kernel would again flush caches on the next dma access (which
> hopefully is only started once userspace completed access). Atm this isn't
> possible in an efficient way since the dma_buf api only exposes map/unmap
> attachment and not a function to just sync an existing mapping like
> dma_sync_single_for_device. I guess we should add a
> dma_buf_sync_attachment interface for that - we already have range-based
> cpu sync support with the begin/end_cpu_access interfaces.

I think my mail here was a bit unclear, so let me try to rephrase.
Re-reading through part of this discussion I think you raise some good
shortcomings of the current dma_buf interfaces and the proposed fence
patches. But I think we should address the individual pieces bit-by-bit.
On a quick survey I see a few parts to what you're trying to solve:

- More efficient cache coherency management. I think we already have all
  required interfaces for efficient cpu-side access with
  begin/end_cpu_access. So I think we only need a device-side dma sync
  mechanism to be able to flush cpu caches after userspace/cpu access has
  completed (before the next dma op).

- More efficient mmap handling. The current dma_buf mmap support is
  explicitly designed as something simply, but probably dead-slow for
  last-resort fallback ops. I'm not sure whether we should fix this up and
  extend with special ioctls. But the current coherency interface should
  be good enough for you to write an efficient private mmap implementation
  for exynos drm.

- Integration of fence syncing into dma_buf. Imo we should have a
  per-attachment mode which decides whether map/unmap (and the new sync)
  should wait for fences or whether the driver takes care of syncing
  through the new fence framework itself (for direct hw sync). Imo cpu
  access should also have such a flag. I guess in both cases we should
  sync by default.

- cpu/cpu sync additions to dma_buf. Like I've said, I'm not sold at all
  on this idea. I think it would be best if we try to fix up all the other
  current shortcomings first though and then take a fresh look at this
  issue here.

Have I missed or misunderstood something?

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From sebastian.hesselbarth at gmail.com  Mon May 20 17:34:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 May 2013 23:34:40 +0200
Subject: [PATCH v3 1/7] net: mv643xx_eth: add Device Tree bindings
In-Reply-To: <20130520211930.GA25725@schnuecks.de>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367854420-8006-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130520211930.GA25725@schnuecks.de>
Message-ID: <519A96F0.3010905@gmail.com>

On 05/20/2013 11:19 PM, Simon Baatz wrote:
> On Mon, May 06, 2013 at 05:33:34PM +0200, Sebastian Hesselbarth wrote:
>> From: Florian Fainelli<florian at openwrt.org>
>>
...
>> @@ -2485,13 +2499,21 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
>>   	if (dram)
>>   		mv643xx_eth_conf_mbus_windows(msp, dram);
>>
>> -	msp->tx_csum_limit = (pd != NULL&&  pd->tx_csum_limit) ?
>> -					pd->tx_csum_limit : 9 * 1024;
>> +	if (np)
>> +		of_property_read_u32(np, "tx-csum-limit",&tx_csum_limit);
>> +	else
>> +		tx_csum_limit = pd->tx_csum_limit;
>> +
>> +	msp->tx_csum_limit = tx_csum_limit ? tx_csum_limit : 9 * 1024;
>>   	infer_hw_params(msp);
>>
>>   	platform_set_drvdata(pdev, msp);
>>
>> +#ifdef CONFIG_OF
>> +	return of_platform_bus_probe(np, mv643xx_eth_match,&pdev->dev);
>
> I have tested this on Kirkwood (Sheevaplug eSATA). When using
> mv643xx_eth as a module with a built-in mvmdio the GbE port works.
> However, when unloading the mv643xx_eth module and loading it again,
> the second call to of_platform_bus_probe() results in a warning:
>
> [  190.542992] WARNING: at fs/sysfs/dir.c:530 sysfs_add_one+0x7c/0xa4()
> [  190.549372] sysfs: cannot create duplicate filename '/devices/ocp.0/f1072000.
> ethernet-controller/0.ethernet-port'
>
> (Looks more like a problem of of_platform_bus_probe() than a problem
> in the driver?)

Hi Simon,

thanks for the review. I am right now working on a v4 of the DT support
patches for mv643xx_eth and the above will not be there anymore. I will
test v4 for rmmod/modprobe issues before posting.

>> @@ -2677,6 +2769,10 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
>>   	struct resource *res;
>>   	int err;
>>
>> +	err = mv643xx_eth_of_probe(pdev);
>> +	if (err)
>> +		return err;
>> +
>>   	pd = pdev->dev.platform_data;
>>   	if (pd == NULL) {
>>   		dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
>
> If the clock isn't already enabled (mvmdio and mv643xx_eth both built
> as modules), a delay seems to be necessary in mv643xx_eth_probe()
> after enabling the clock on my hardware.  Otherwise the device hangs.
> Andrew found the same in the past (see [1]).  udelay(50) seems to be
> sufficient in my case.

Hmm, I am wondering if that delay shouldn't be in the clock provider
then. I test it on Dove also and look for a way to insert the delay
if neccessary. Maybe Andrew can also comment on this.

>> @@ -2717,7 +2813,12 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
>>   	netif_set_real_num_rx_queues(dev, mp->rxq_count);
>>
>>   	if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
>> -		mp->phy = phy_scan(mp, pd->phy_addr);
>> +		if (pd->phy_node)
>> +			mp->phy = of_phy_connect(mp->dev, pd->phy_node,
>> +						mv643xx_eth_adjust_link, 0,
>> +						PHY_INTERFACE_MODE_GMII);
>
> of_phy_connect() returns NULL in case of an error and no ERR_PTR.

True, will take care of that.

Sebastian


From sebastian.hesselbarth at gmail.com  Mon May 20 17:38:00 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 May 2013 23:38:00 +0200
Subject: [PATCH v3 6/7] ARM: kirkwood: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <20130520212708.GA26519@schnuecks.de>
References: <1365071235-11611-1-git-send-email-florian@openwrt.org>
 <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1367854420-8006-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130520212708.GA26519@schnuecks.de>
Message-ID: <519A97B8.1090503@gmail.com>

On 05/20/2013 11:27 PM, Simon Baatz wrote:
> Hi Sebastian,
>
> On Mon, May 06, 2013 at 05:33:39PM +0200, Sebastian Hesselbarth wrote:
>> This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
>> Kirkwood boards. Phy nodes are also added with reg property set on a
>> per-board basis.
> ...
>> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
>> index fada7e6..c01a273 100644
>> --- a/arch/arm/boot/dts/kirkwood.dtsi
>> +++ b/arch/arm/boot/dts/kirkwood.dtsi
>> @@ -202,5 +202,57 @@
>>   			clocks =<&gate_clk 4>;
>>   			status = "disabled";
>>   		};
>> +
>> +		mdio: mdio-bus at 72004 {
>> +			compatible = "marvell,orion-mdio";
>> +			reg =<0x72004 0x84>;
>> +			interrupts =<11>;
>
> Shouldn't this be 46?

Yes, mdio is using GbE0Err interrupt and that is 14 on IRQ HIGH CAUSE.
I was misled by 11 on IRQ LOW CAUSE.

Sebastian


From sboyd at codeaurora.org  Mon May 20 17:55:54 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 20 May 2013 14:55:54 -0700
Subject: [PATCHv6 03/11] ARM: smp: Remove duplicate dummy timer
 implementation
In-Reply-To: <1368473175-4841-4-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
 <1368473175-4841-4-git-send-email-sboyd@codeaurora.org>
Message-ID: <519A9BEA.1010404@codeaurora.org>

On 05/13/13 12:26, Stephen Boyd wrote:
> Drop ARM's version of the dummy timer now that we have a generic
> implementation in drivers/clocksource.
>
> Cc: Russell King <linux at arm.linux.org.uk>
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>

Russell, can you please ack this patch and patch #11?

> ---
>  arch/arm/kernel/smp.c | 22 ++--------------------
>  1 file changed, 2 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 47ab905..4dc883a 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -503,24 +503,6 @@ void tick_broadcast(const struct cpumask *mask)
>  }
>  #endif
>  
> -static void broadcast_timer_set_mode(enum clock_event_mode mode,
> -	struct clock_event_device *evt)
> -{
> -}
> -
> -static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
> -{
> -	evt->name	= "dummy_timer";
> -	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
> -			  CLOCK_EVT_FEAT_PERIODIC |
> -			  CLOCK_EVT_FEAT_DUMMY;
> -	evt->rating	= 100;
> -	evt->mult	= 1;
> -	evt->set_mode	= broadcast_timer_set_mode;
> -
> -	clockevents_register_device(evt);
> -}
> -
>  static struct local_timer_ops *lt_ops;
>  
>  #ifdef CONFIG_LOCAL_TIMERS
> @@ -544,8 +526,8 @@ static void __cpuinit percpu_timer_setup(void)
>  
>  	evt->cpumask = cpumask_of(cpu);
>  
> -	if (!lt_ops || lt_ops->setup(evt))
> -		broadcast_timer_setup(evt);
> +	if (lt_ops)
> +		lt_ops->setup(evt);
>  }
>  
>  #ifdef CONFIG_HOTPLUG_CPU


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From tony at atomide.com  Mon May 20 18:05:40 2013
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 20 May 2013 15:05:40 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
 <20130517185620.GF28484@animalcreek.com>
 <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>
Message-ID: <20130520220540.GL10378@atomide.com>

* Yegor Yefremov <yegorslists at googlemail.com> [130517 14:34]:
> On Fri, May 17, 2013 at 8:56 PM, Mark A. Greer <mgreer at animalcreek.com> wrote:
> > On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
> >> On 15.05.2013 23:50, Mark A. Greer wrote:
> >> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
> >
> >> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
> >> >> idle states with?
> >> >
> >> > I have an am35xx which isn't supposed to have an IVA so I can test with it
> >> > (although, I'm not sure how well the kernel works on the am35xx these days).
> >> >
> >> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
> >> > comes up, see what I can figure out.
> >>
> >> I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
> >> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
> >>
> >> I have such a system running, so if you have any other patches/ideas to test, I would do it.
> >
> > Yegor, since I've so far been unable to get my am3517evm to fire up, can
> > you play around with the 3517 to see if there appears to be iva registers
> > that can be read/written to safely?  In particular, can the code that idles
> > the iva be run safely on an am3517?
> 
> I'll look into this next week. am3517 and IVA seems to be a really big
> mystery. In the TI forum will be stated, there is no IVA:
> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/150961.aspx, but TRM
> has various appearances of IVA2 registers, but no real
> description/explanation of what is IVA and how to eat it.

On 3703 it looks like the whole omap3_iva_idle() reset is needed, except
for setting the iva2 bootmode to idle. So I'm planning to merge the following
patch with just comments update this week unless somebody has a better fix
in mind.

Regards,

Tony


From: Tony Lindgren <tony at atomide.com>
Date: Tue, 14 May 2013 20:28:15 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703

Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
changed PM to not access IVA registers on omaps that don't have
them. Turns out we still need to idle iva2 as otherwise
iva2_pwrdm will stay on and block deeper idle states.

It seems that the only part of the reset that may not be needed
is the setting of the iva2 boot mode to idle. But as that register
seems to be there and is harmless if no iva2 is on the SoC, it's
probably safest to do the complete reset.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
 	/* Clear any pending PRCM interrupts */
 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-	if (omap3_has_iva())
-		omap3_iva_idle();
+	/*
+	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
+	 */
+	omap3_iva_idle();
 
 	omap3_d2d_idle();
 }


From jamie at jamieiles.com  Mon May 20 18:42:14 2013
From: jamie at jamieiles.com (Jamie Iles)
Date: Mon, 20 May 2013 23:42:14 +0100
Subject: [PATCH 04/20] ARM: picoxcell: Remove init_irq declaration in
 machine description
In-Reply-To: <519496AC.1070809@free-electrons.com>
References: <1368545933-7430-1-git-send-email-maxime.ripard@free-electrons.com>
 <1368545933-7430-5-git-send-email-maxime.ripard@free-electrons.com>
 <20130514162046.GA16346@page> <519496AC.1070809@free-electrons.com>
Message-ID: <20130520224214.GA4659@page>

On Thu, May 16, 2013 at 10:19:56AM +0200, Maxime Ripard wrote:
> Hi Jamie,
> 
> Le 14/05/2013 18:20, Jamie Iles a ?crit :
> > Hi Maxime,
> > 
> > Thanks for this, I'll add it to my tree.  I've modified it slightly to 
> > kill off the other irq includes, hopefully that's okay with you.
> 
> Yes, I was pretty conservative since I was not familiar with most of the
> code, but yes, I'm fine with the changes.

Thanks Maxime, applied to picoxcell-next.

Jamie


From gmbnomis at gmail.com  Mon May 20 19:01:44 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:44 +0200
Subject: [PATCH V3 03/10] mmc: tmio-mmc: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-4-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
---
 drivers/mmc/host/tmio_mmc_pio.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c
index f508ecb..f1a9d4a 100644
--- a/drivers/mmc/host/tmio_mmc_pio.c
+++ b/drivers/mmc/host/tmio_mmc_pio.c
@@ -988,7 +988,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host,
 	if (!mmc)
 		return -ENOMEM;
 
-	mmc_of_parse(mmc);
+	ret = mmc_of_parse(mmc);
+	if (ret < 0)
+		goto host_free;
 
 	pdata->dev = &pdev->dev;
 	_host = mmc_priv(mmc);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:46 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:46 +0200
Subject: [PATCH V3 05/10] mmc: sdhci-pxav3: handle mmc_of_parse() errors
 during probe
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-6-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/sdhci-pxav3.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 1ae358e..67ea388 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -252,7 +252,9 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 
 	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 	if (match) {
-		mmc_of_parse(host->mmc);
+		ret = mmc_of_parse(host->mmc);
+		if (ret)
+			goto err_of_parse;
 		sdhci_get_of_property(pdev);
 		pdata = pxav3_get_mmc_pdata(dev);
 	} else if (pdata) {
@@ -313,10 +315,11 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 
 	return 0;
 
+err_of_parse:
+err_cd_req:
 err_add_host:
 	clk_disable_unprepare(clk);
 	clk_put(clk);
-err_cd_req:
 err_clk_get:
 	sdhci_pltfm_free(pdev);
 	kfree(pxa);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:45 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:45 +0200
Subject: [PATCH V3 04/10] mmc: mxcmmc: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-5-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/mxcmmc.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index d503635..f47546f 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -1067,7 +1067,9 @@ static int mxcmci_probe(struct platform_device *pdev)
 		goto out_release_mem;
 	}
 
-	mmc_of_parse(mmc);
+	ret = mmc_of_parse(mmc);
+	if (ret)
+		goto out_free;
 	mmc->ops = &mxcmci_ops;
 
 	/* For devicetree parsing, the bus width is read from devicetree */
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:43 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:43 +0200
Subject: [PATCH V3 02/10] mmc: sh_mmcif: handle mmc_of_parse() errors during
 probe
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-3-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
---
 drivers/mmc/host/sh_mmcif.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index ba76a53..6ded7fb 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -1369,7 +1369,11 @@ static int sh_mmcif_probe(struct platform_device *pdev)
 		ret = -ENOMEM;
 		goto ealloch;
 	}
-	mmc_of_parse(mmc);
+
+	ret = mmc_of_parse(mmc);
+	if (ret < 0)
+		goto eofparse;
+
 	host		= mmc_priv(mmc);
 	host->mmc	= mmc;
 	host->addr	= reg;
@@ -1464,6 +1468,7 @@ eclkupdate:
 	clk_put(host->hclk);
 eclkget:
 	pm_runtime_disable(&pdev->dev);
+eofparse:
 	mmc_free_host(mmc);
 ealloch:
 	iounmap(reg);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:42 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:42 +0200
Subject: [PATCH V3 01/10] mmc: return mmc_of_parse() errors to caller
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-2-git-send-email-gmbnomis@gmail.com>

In addition to just logging errors encountered during DT parsing or
allocating GPIO slots for CD/WP, mmc_of_parse() now returns with an error.

In particular, this is needed if the GPIO allocation may return
EPROBE_DEFER.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---

changes in V3:
- Handle EPROBE_DEFER case

 drivers/mmc/core/host.c  |   30 +++++++++++++++++++++++++-----
 include/linux/mmc/host.h |    2 +-
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 2a3593d..89f5849 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -306,7 +306,7 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
  * parse the properties and set respective generic mmc-host flags and
  * parameters.
  */
-void mmc_of_parse(struct mmc_host *host)
+int mmc_of_parse(struct mmc_host *host)
 {
 	struct device_node *np;
 	u32 bus_width;
@@ -315,7 +315,7 @@ void mmc_of_parse(struct mmc_host *host)
 	int len, ret, gpio;
 
 	if (!host->parent || !host->parent->of_node)
-		return;
+		return 0;
 
 	np = host->parent->of_node;
 
@@ -338,6 +338,7 @@ void mmc_of_parse(struct mmc_host *host)
 	default:
 		dev_err(host->parent,
 			"Invalid \"bus-width\" value %ud!\n", bus_width);
+		return -EINVAL;
 	}
 
 	/* f_max is obtained from the optional "max-frequency" property */
@@ -367,18 +368,22 @@ void mmc_of_parse(struct mmc_host *host)
 			host->caps |= MMC_CAP_NEEDS_POLL;
 
 		gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags);
+		if (gpio == -EPROBE_DEFER)
+			return gpio;
 		if (gpio_is_valid(gpio)) {
 			if (!(flags & OF_GPIO_ACTIVE_LOW))
 				gpio_inv_cd = true;
 
 			ret = mmc_gpio_request_cd(host, gpio);
-			if (ret < 0)
+			if (ret < 0) {
 				dev_err(host->parent,
 					"Failed to request CD GPIO #%d: %d!\n",
 					gpio, ret);
-			else
+				return ret;
+			} else {
 				dev_info(host->parent, "Got CD GPIO #%d.\n",
 					 gpio);
+			}
 		}
 
 		if (explicit_inv_cd ^ gpio_inv_cd)
@@ -389,14 +394,23 @@ void mmc_of_parse(struct mmc_host *host)
 	explicit_inv_wp = of_property_read_bool(np, "wp-inverted");
 
 	gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags);
+	if (gpio == -EPROBE_DEFER) {
+		ret = -EPROBE_DEFER;
+		goto out;
+	}
 	if (gpio_is_valid(gpio)) {
 		if (!(flags & OF_GPIO_ACTIVE_LOW))
 			gpio_inv_wp = true;
 
 		ret = mmc_gpio_request_ro(host, gpio);
-		if (ret < 0)
+		if (ret < 0) {
 			dev_err(host->parent,
 				"Failed to request WP GPIO: %d!\n", ret);
+			goto out;
+		} else {
+				dev_info(host->parent, "Got WP GPIO #%d.\n",
+					 gpio);
+		}
 	}
 	if (explicit_inv_wp ^ gpio_inv_wp)
 		host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
@@ -413,6 +427,12 @@ void mmc_of_parse(struct mmc_host *host)
 		host->pm_caps |= MMC_PM_KEEP_POWER;
 	if (of_find_property(np, "enable-sdio-wakeup", &len))
 		host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
+
+	return 0;
+
+out:
+	mmc_gpio_free_cd(host);
+	return ret;
 }
 
 EXPORT_SYMBOL(mmc_of_parse);
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index e326ae2..c8c4fbc 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -369,7 +369,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *);
 int mmc_add_host(struct mmc_host *);
 void mmc_remove_host(struct mmc_host *);
 void mmc_free_host(struct mmc_host *);
-void mmc_of_parse(struct mmc_host *host);
+int mmc_of_parse(struct mmc_host *host);
 
 static inline void *mmc_priv(struct mmc_host *host)
 {
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:41 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:41 +0200
Subject: [PATCH V3 00/10] mmc_of_parse() adaptations,
 DT support for Sheevaplugs
Message-ID: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>

Hi,

	V3 changes:
	- Patch 01/10: Added EPROBE_DEFER case to mmc_of_parse() 
	- Added Acked-By to (unmodified) patches 02 and 03.

	V2 changes:
	- Converted mvsdio to use mmc_of_parse()
	- Adapted DTS files using mvsdio accordingly
	- Changed mmc_of_parse() to return errors to the caller

While adding DT support for the Sheevaplugs by Globalscale Technologies
(Kirkwood), it turned out that the DT binding of mvsdio lacked features to
properly support the hardware (active high/low of CD and WP pins could not
be described in DT).

This is standard functionality provided by the mmc_of_parse() helper
function.  However, mmc_of_parse() may allocate GPIO lines.  If the
allocation fails, it outputs an error, but does not return an error to its
caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.

The patch set is structured as follows:

1   Adapt mmc_of_parse() to return errors
2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
    only)
7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
    kirkwood)
9   Add dts files for (eSATA) Sheevaplug
10  Add DT support for (eSATA) Sheevaplug


I could only test on an eSATA Sheevaplug. I found patches with
different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
someone with the hardware could give this a spin on a non-eSATA
version.  Some additional testing of the change detect and write
protect behaviour for mvsdio can't hurt either.  I hope that there aren't
board revisions with different CD/WP pins out there.

Simon Baatz (10):
  mmc: return mmc_of_parse() errors to caller
  mmc: sh_mmcif: handle mmc_of_parse() errors during probe
  mmc: tmio-mmc: handle mmc_of_parse() errors during probe
  mmc: mxcmmc: handle mmc_of_parse() errors during probe
  mmc: sdhci-pxav3: handle mmc_of_parse() errors during probe
  mmc: tegra: handle mmc_of_parse() errors during probe
  ARM: mvebu: Use standard MMC binding for all users of mvsdio
  mmc: mvsdio: use standard MMC device-tree binding parser
    mmc_of_parse()
  ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug
  ARM: Kirkwood: add DT support for Sheevaplug and Sheevaplug eSATA

 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/armada-370-db.dts                |    1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |    1 +
 arch/arm/boot/dts/armada-370-rd.dts                |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    1 +
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |    1 +
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    2 +
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |    2 +-
 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi  |   97 ++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts    |   40 ++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug.dts          |   45 +++++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |    1 +
 arch/arm/boot/dts/kirkwood.dtsi                    |    4 +
 arch/arm/mach-kirkwood/Kconfig                     |    7 ++
 arch/arm/mach-kirkwood/Makefile                    |    1 +
 arch/arm/mach-kirkwood/board-dt.c                  |    4 +
 arch/arm/mach-kirkwood/board-sheevaplug.c          |   27 ++++++
 arch/arm/mach-kirkwood/common.h                    |    5 +
 drivers/mmc/core/host.c                            |   30 +++++-
 drivers/mmc/host/mvsdio.c                          |   73 ++++++++-------
 drivers/mmc/host/mxcmmc.c                          |    4 +-
 drivers/mmc/host/sdhci-pxav3.c                     |    7 +-
 drivers/mmc/host/sdhci-tegra.c                     |    9 +-
 drivers/mmc/host/sh_mmcif.c                        |    7 +-
 drivers/mmc/host/tmio_mmc_pio.c                    |    4 +-
 include/linux/mmc/host.h                           |    2 +-
 27 files changed, 334 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts
 create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c

-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:47 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:47 +0200
Subject: [PATCH V3 06/10] mmc: tegra: handle mmc_of_parse() errors during probe
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-7-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/sdhci-tegra.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index e0dba74..7eb62f8 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -205,7 +205,7 @@ static const struct of_device_id sdhci_tegra_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
 
-static void sdhci_tegra_parse_dt(struct device *dev)
+static int sdhci_tegra_parse_dt(struct device *dev)
 {
 	struct device_node *np = dev->of_node;
 	struct sdhci_host *host = dev_get_drvdata(dev);
@@ -213,7 +213,7 @@ static void sdhci_tegra_parse_dt(struct device *dev)
 	struct sdhci_tegra *tegra_host = pltfm_host->priv;
 
 	tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
-	mmc_of_parse(host->mmc);
+	return mmc_of_parse(host->mmc);
 }
 
 static int sdhci_tegra_probe(struct platform_device *pdev)
@@ -245,7 +245,9 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 	tegra_host->soc_data = soc_data;
 	pltfm_host->priv = tegra_host;
 
-	sdhci_tegra_parse_dt(&pdev->dev);
+	rc = sdhci_tegra_parse_dt(&pdev->dev);
+	if (rc)
+		goto err_parse_dt;
 
 	if (gpio_is_valid(tegra_host->power_gpio)) {
 		rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
@@ -278,6 +280,7 @@ err_add_host:
 err_clk_get:
 	if (gpio_is_valid(tegra_host->power_gpio))
 		gpio_free(tegra_host->power_gpio);
+err_parse_dt:
 err_power_req:
 err_alloc_tegra_host:
 	sdhci_pltfm_free(pdev);
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:48 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:48 +0200
Subject: [PATCH V3 07/10] ARM: mvebu: Use standard MMC binding for all users
 of mvsdio
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-8-git-send-email-gmbnomis@gmail.com>

In order to prepare the switch to the standard MMC device tree parser
for mvsdio, adapt all current uses of mvsdio in the dts files to the
standard format.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 arch/arm/boot/dts/armada-370-db.dts                |    1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |    1 +
 arch/arm/boot/dts/armada-370-rd.dts                |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    4 ++++
 arch/arm/boot/dts/armada-xp-db.dts                 |    1 +
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |    1 +
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    2 ++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |    2 +-
 arch/arm/boot/dts/kirkwood-topkick.dts             |    1 +
 arch/arm/boot/dts/kirkwood.dtsi                    |    4 ++++
 10 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 2353b1f..beee169 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -74,6 +74,7 @@
 				 */
 				status = "disabled";
 				/* No CD or WP GPIOs */
+				broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 14e36e1..45b1077 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -99,6 +99,7 @@
 				 * No CD or WP GPIOs: SDIO interface used for
 				 * Wifi/Bluetooth chip
 				 */
+				 broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 130f839..89c2110 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,6 +64,7 @@
 				pinctrl-names = "default";
 				status = "okay";
 				/* No CD or WP GPIOs */
+				broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..031894e 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -142,6 +142,10 @@
 				reg = <0xd4000 0x200>;
 				interrupts = <54>;
 				clocks = <&gateclk 17>;
+				bus-width = <4>;
+				cap-sdio-irq;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index d6cc8bf..7c22a20 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -97,6 +97,7 @@
 				pinctrl-names = "default";
 				status = "okay";
 				/* No CD or WP GPIOs */
+				broken-cd;
 			};
 
 			usb at 50000 {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d..be16a84 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -79,6 +79,7 @@
 			pinctrl-names = "default";
 			status = "okay";
 			/* No CD or WP GPIOs */
+			broken-cd;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97d..484a2a6 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -72,6 +72,8 @@
 
 		mvsdio at 90000 {
 			status = "okay";
+			/* No CD or WP GPIOs */
+			broken-cd;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..bf3a58c 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -136,7 +136,7 @@
 			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
 			pinctrl-names = "default";
 			status = "okay";
-			cd-gpios = <&gpio1 15 0>;
+			cd-gpios = <&gpio1 15 1>;
 			/* No WP GPIO */
 		};
 	};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b..7dc14f4 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -154,6 +154,7 @@
 			pinctrl-names = "default";
 			status = "okay";
 			/* No CD or WP GPIOs */
+			broken-cd;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..e2a28db 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -200,6 +200,10 @@
 			reg = <0x90000 0x200>;
 			interrupts = <28>;
 			clocks = <&gate_clk 4>;
+			bus-width = <4>;
+			cap-sdio-irq;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
 			status = "disabled";
 		};
 	};
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:49 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:49 +0200
Subject: [PATCH V3 08/10] mmc: mvsdio: use standard MMC device-tree binding
 parser mmc_of_parse()
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-9-git-send-email-gmbnomis@gmail.com>

Instead of parsing the DT binding on our own, use the standard parser
mmc_of_parse(), introduced by commit 6c56e7a.

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 drivers/mmc/host/mvsdio.c |   73 +++++++++++++++++++++++++--------------------
 1 file changed, 40 insertions(+), 33 deletions(-)

diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c
index 8960fc8..edfc481 100644
--- a/drivers/mmc/host/mvsdio.c
+++ b/drivers/mmc/host/mvsdio.c
@@ -35,7 +35,7 @@
 
 #define DRIVER_NAME	"mvsdio"
 
-static int maxfreq = MVSD_CLOCKRATE_MAX;
+static int maxfreq;
 static int nodma;
 
 struct mvsd_host {
@@ -685,7 +685,6 @@ static int __init mvsd_probe(struct platform_device *pdev)
 	const struct mbus_dram_target_info *dram;
 	struct resource *r;
 	int ret, irq;
-	int gpio_card_detect, gpio_write_protect;
 	struct pinctrl *pinctrl;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -718,6 +717,20 @@ static int __init mvsd_probe(struct platform_device *pdev)
 	if (!IS_ERR(host->clk))
 		clk_prepare_enable(host->clk);
 
+	mmc->ops = &mvsd_ops;
+
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
+	mmc->f_max = MVSD_CLOCKRATE_MAX;
+
+	mmc->max_blk_size = 2048;
+	mmc->max_blk_count = 65535;
+
+	mmc->max_segs = 1;
+	mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
+	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+
 	if (np) {
 		if (IS_ERR(host->clk)) {
 			dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
@@ -726,35 +739,38 @@ static int __init mvsd_probe(struct platform_device *pdev)
 		}
 
 		host->base_clock = clk_get_rate(host->clk) / 2;
-		gpio_card_detect = of_get_named_gpio(np, "cd-gpios", 0);
-		gpio_write_protect = of_get_named_gpio(np, "wp-gpios", 0);
+		ret = mmc_of_parse(mmc);
+		if (ret < 0)
+			goto out;
 	} else {
 		const struct mvsdio_platform_data *mvsd_data;
+
 		mvsd_data = pdev->dev.platform_data;
 		if (!mvsd_data) {
 			ret = -ENXIO;
 			goto out;
 		}
+		mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
+			    MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
 		host->base_clock = mvsd_data->clock / 2;
-		gpio_card_detect = mvsd_data->gpio_card_detect ? : -EINVAL;
-		gpio_write_protect = mvsd_data->gpio_write_protect ? : -EINVAL;
-	}
-
-	mmc->ops = &mvsd_ops;
-
-	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
-		    MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
-
-	mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
-	mmc->f_max = maxfreq;
+		/* GPIO 0 regarded as invalid for backward compatibility */
+		if (mvsd_data->gpio_card_detect &&
+		    gpio_is_valid(mvsd_data->gpio_card_detect)) {
+			ret = mmc_gpio_request_cd(mmc,
+						  mvsd_data->gpio_card_detect);
+			if (ret)
+				goto out;
+		} else {
+			mmc->caps |= MMC_CAP_NEEDS_POLL;
+		}
 
-	mmc->max_blk_size = 2048;
-	mmc->max_blk_count = 65535;
+		if (mvsd_data->gpio_write_protect &&
+		    gpio_is_valid(mvsd_data->gpio_write_protect))
+			mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect);
+	}
 
-	mmc->max_segs = 1;
-	mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
-	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+	if (maxfreq)
+		mmc->f_max = maxfreq;
 
 	spin_lock_init(&host->lock);
 
@@ -777,15 +793,6 @@ static int __init mvsd_probe(struct platform_device *pdev)
 		goto out;
 	}
 
-	if (gpio_is_valid(gpio_card_detect)) {
-		ret = mmc_gpio_request_cd(mmc, gpio_card_detect);
-		if (ret)
-			goto out;
-	} else
-		mmc->caps |= MMC_CAP_NEEDS_POLL;
-
-	mmc_gpio_request_ro(mmc, gpio_write_protect);
-
 	setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
 	platform_set_drvdata(pdev, mmc);
 	ret = mmc_add_host(mmc);
@@ -793,10 +800,10 @@ static int __init mvsd_probe(struct platform_device *pdev)
 		goto out;
 
 	if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
-		dev_notice(&pdev->dev, "using GPIO %d for card detection\n",
-			   gpio_card_detect);
+		dev_notice(&pdev->dev, "using GPIO for card detection\n");
 	else
-		dev_notice(&pdev->dev, "lacking card detect (fall back to polling)\n");
+		dev_notice(&pdev->dev,
+			   "lacking card detect (fall back to polling)\n");
 	return 0;
 
 out:
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:51 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:51 +0200
Subject: [PATCH V3 10/10] ARM: Kirkwood: add DT support for Sheevaplug and
 Sheevaplug eSATA
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-11-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig            |    7 +++++++
 arch/arm/mach-kirkwood/Makefile           |    1 +
 arch/arm/mach-kirkwood/board-dt.c         |    4 ++++
 arch/arm/mach-kirkwood/board-sheevaplug.c |   27 +++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h           |    5 +++++
 5 files changed, 44 insertions(+)
 create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..58518a2 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -296,6 +296,13 @@ config MACH_READYNAS_DT
 	  Say 'Y' here if you want your kernel to support the
 	  NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
+config MACH_SHEEVAPLUG_DT
+	bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell (eSATA) SheevaPlug (Flattened Device Tree).
+
 config MACH_TOPKICK_DT
 	bool "USI Topkick (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735..8846abf 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)		+= board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)	+= board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
+obj-$(CONFIG_MACH_SHEEVAPLUG_DT)	+= board-sheevaplug.o
 obj-$(CONFIG_MACH_TOPKICK_DT)		+= board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..a09dbac 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -112,6 +112,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("globalscale,guruplug"))
 		guruplug_dt_init();
 
+	if (of_machine_is_compatible("globalscale,sheevaplug"))
+		sheevaplug_dt_init();
+
 	if (of_machine_is_compatible("dlink,dns-kirkwood"))
 		dnskw_init();
 
@@ -165,6 +168,7 @@ static void __init kirkwood_dt_init(void)
 static const char * const kirkwood_dt_board_compat[] = {
 	"globalscale,dreamplug",
 	"globalscale,guruplug",
+	"globalscale,sheevaplug",
 	"dlink,dns-320",
 	"dlink,dns-325",
 	"iom,iconnect",
diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
new file mode 100644
index 0000000..fa38937
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-sheevaplug.c
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-kirkwood/board-sheevaplug.c
+ *
+ * Marvell Sheevaplug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+void __init sheevaplug_dt_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_ge00_init(&sheevaplug_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1..974442e 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -65,6 +65,11 @@ void guruplug_dt_init(void);
 #else
 static inline void guruplug_dt_init(void) {};
 #endif
+#ifdef CONFIG_MACH_SHEEVAPLUG_DT
+void sheevaplug_dt_init(void);
+#else
+static inline void sheevaplug_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
-- 
1.7.9.5



From gmbnomis at gmail.com  Mon May 20 19:01:50 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Tue, 21 May 2013 01:01:50 +0200
Subject: [PATCH V3 09/10] ARM: Kirkwood: Add dts files for Sheevaplug and
 eSATA Sheevaplug
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <1369090911-1479-10-git-send-email-gmbnomis@gmail.com>

Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
---
 arch/arm/boot/dts/Makefile                        |    2 +
 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi |   97 +++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts   |   40 +++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug.dts         |   45 ++++++++++
 4 files changed, 184 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..e81a387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -84,6 +84,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
 	kirkwood-ns2max.dtb \
 	kirkwood-ns2mini.dtb \
 	kirkwood-nsa310.dtb \
+	kirkwood-sheevaplug.dtb \
+	kirkwood-sheevaplug-esata.dtb \
 	kirkwood-topkick.dtb \
 	kirkwood-ts219-6281.dtb \
 	kirkwood-ts219-6282.dtb \
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
new file mode 100644
index 0000000..9d59475
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -0,0 +1,97 @@
+/*
+ * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		pinctrl: pinctrl at 10000 {
+
+			pmx_usb_power_enable: pmx-usb-power-enable {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+			pmx_led_red: pmx-led-red {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_led_blue: pmx-led-blue {
+				marvell,pins = "mpp49";
+				marvell,function = "gpio";
+			};
+			pmx_sdio_cd: pmx-sdio-cd {
+				marvell,pins = "mpp44";
+				marvell,function = "gpio";
+			};
+			pmx_sdio_wp: pmx-sdio-wp {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+		};
+		serial at 12000 {
+			status = "okay";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x400000>;
+			};
+
+			partition at 500000 {
+				label = "root";
+				reg = <0x0500000 0x1fb00000>;
+			};
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_power: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 29 0>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		health {
+			label = "sheevaplug:blue:health";
+			gpios = <&gpio1 17 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
new file mode 100644
index 0000000..1c6946a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -0,0 +1,40 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+	model = "Globalscale Technologies eSATA SheevaPlug";
+	compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	ocp at f1000000 {
+		pinctrl: pinctrl at 10000 {
+
+			pinctrl-0 = < &pmx_nand &pmx_uart0
+				      &pmx_usb_power_enable
+				      &pmx_led_blue>;
+			pinctrl-names = "default";
+
+		};
+
+		sata at 80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+		mvsdio at 90000 {
+			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
+			pinctrl-names = "default";
+			status = "okay";
+			cd-gpios = <&gpio1 12 1>;
+			wp-gpios = <&gpio1 15 0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
new file mode 100644
index 0000000..f7684066
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -0,0 +1,45 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+	model = "Globalscale Technologies SheevaPlug";
+	compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	ocp at f1000000 {
+		pinctrl: pinctrl at 10000 {
+
+			pinctrl-0 = < &pmx_nand &pmx_uart0
+				      &pmx_usb_power_enable
+				      &pmx_led_red
+				      &pmx_led_blue>;
+			pinctrl-names = "default";
+
+		};
+
+		mvsdio at 90000 {
+			pinctrl-0 = <&pmx_sdio>;
+			pinctrl-names = "default";
+			status = "okay";
+			/* No CD or WP GPIOs */
+			broken-cd;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		misc {
+			label = "sheevaplug:red:misc";
+			gpios = <&gpio1 14 1>;
+		};
+	};
+};
-- 
1.7.9.5



From swarren at wwwdotorg.org  Mon May 20 19:20:43 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 17:20:43 -0600
Subject: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <519AAFCB.8060007@wwwdotorg.org>

On 05/20/2013 04:39 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.

This version still doesn't enable hotplug of CPU0, yet at least patch
6/6 contains some changes that support enabling that. Are you planning
on sending a separate patch to enable this later, or was this an oversight?


From sboyd at codeaurora.org  Mon May 20 20:50:37 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 20 May 2013 17:50:37 -0700
Subject: [PATCH] ARM: dts: msm: Fix bad register addresses
Message-ID: <1369097437-19217-1-git-send-email-sboyd@codeaurora.org>

Some bad copy/paste got in as well as too many zeroes. Fix
everything up so that the registers after the @ sign are
consistent with the first reg property.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/boot/dts/msm8660-surf.dts | 4 ++--
 arch/arm/boot/dts/msm8960-cdp.dts  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 9bf49b3..d347082 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -15,7 +15,7 @@
 		      < 0x02081000 0x1000 >;
 	};
 
-	timer at 2000004 {
+	timer at 2000000 {
 		compatible = "qcom,scss-timer", "qcom,msm-timer";
 		interrupts = <1 0 0x301>,
 			     <1 1 0x301>,
@@ -26,7 +26,7 @@
 		cpu-offset = <0x40000>;
 	};
 
-	serial at 19c400000 {
+	serial at 19c40000 {
 		compatible = "qcom,msm-hsuart", "qcom,msm-uart";
 		reg = <0x19c40000 0x1000>,
 		      <0x19c00000 0x1000>;
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index 2e4d87a..7c9ef9b 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -26,7 +26,7 @@
 		cpu-offset = <0x80000>;
 	};
 
-	serial at 19c400000 {
+	serial at 16440000 {
 		compatible = "qcom,msm-hsuart", "qcom,msm-uart";
 		reg = <0x16440000 0x1000>,
 		      <0x16400000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From kgene.kim at samsung.com  Mon May 20 21:27:27 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 10:27:27 +0900
Subject: [PATCH] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
In-Reply-To: <1623377.nVo7nUcid2@flatron>
References: <1368630484-29939-1-git-send-email-t.figa@samsung.com>
 <1623377.nVo7nUcid2@flatron>
Message-ID: <0f8101ce55c2$5b084c90$1118e5b0$%kim@samsung.com>

Tomasz Figa wrote:
> 
> Hi Kukjin,
> 
Hi,

> On Wednesday 15 of May 2013 17:08:04 Tomasz Figa wrote:
> > This patch extends exynos_init_time() function to handle Exynos4210 rev0
> > SoC, which differs in availability of system timers and needs different
> > clocksource initialization.
> >
> > This makes it possible to use exynos_init_time() function as init_time
> > callback for all Exynos-based boards, including Universal_C210, which
> > originally had to use samsung_timer_init().
> >
> > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  arch/arm/mach-exynos/Kconfig               |  3 ++-
> >  arch/arm/mach-exynos/common.c              | 30
> > +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h
> >   |  2 ++
> >  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++---
> >  4 files changed, 35 insertions(+), 5 deletions(-)
> 
> Could you pick this patch to your fixes branch?
> 
Yeah, I will after looking at.

> This is a fix of a regression in handling Exynos4210 rev0 SoC (e.g.
> Universal C210 board) introduced by patches merged to 3.10.
> 
OK, I see but I didn't review yet and I  will within a couple of days ;-)

- Kukjin



From bill4carson at gmail.com  Mon May 20 21:35:07 2013
From: bill4carson at gmail.com (bill4carson)
Date: Tue, 21 May 2013 09:35:07 +0800
Subject: hugetlbfs support plan for ARM
In-Reply-To: <3E54258959B69E4282D79E01AB1F32B7044F299D@DFLE11.ent.ti.com>
References: <3E54258959B69E4282D79E01AB1F32B7044F299D@DFLE11.ent.ti.com>
Message-ID: <519ACF4B.9070502@gmail.com>

Hi, Karichri

On 2013?05?21? 02:26, Karicheri, Muralidharan wrote:
> Hi Bill,
>
> I see the patch at http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/084360.html
>
> Is there a plan to merge this to upstream Linux kernel? I would appreciate your response on this.

I tried to post several round of this patch set, but haven't got more time to merge it.
Steve Capper from ARM proposed both HUGEPAGE and THP in below link,
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/148451.html

Look https://wiki.linaro.org/LEG/Engineering/Kernel/HugePages here to find what you needs.

> Thanks.
>
> Murali Karicheri
>
> /Software Design Engineer/
>

-- 
?????????,??????????

--bill


From neidhard.kim at lge.com  Mon May 20 21:39:46 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Tue, 21 May 2013 10:39:46 +0900
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org> <022d01ce5107$8bc668e0$a3533aa0$@lge.com>
 <5193164E.6050400@wwwdotorg.org> 
Message-ID: <007001ce55c4$139f96e0$3adec4a0$@lge.com>

Jongsung Kim <neidhard.kim at lge.com> :
> Stephen Warren <swarren at wwwdotorg.org> :
>>> All r1p5 have 32-byte FIFO depth and it's not configurable. From the 
>>> PL011
>>> TRM:
>>> 
>>> r1p4-r1p5	Contains the following differences in functionality:
>>> 		* The receive and transmit FIFOs are increased to a depth of
32.
>>> 		* The Revision field in the UARTPeriphID2 Register on page
3-24
>>> 		  bits [7:4] now reads back as 0x3.
>>
>> Well, that certainly isn't true in practice. I think we should revert 
>> this commit until we can determine what the problem is.
>
> I asked to the ARM support about this. Waiting for reply..

ARM support said they doesn't have information about BCM2835 UART. Does
anyone have a communication channel to Broadcom? It takes time for me to
get contact point to Broadcom.. (I'm trying)

However, ARM support also said:

"If the Broadcom part definitely has 16-deep FIFOs, it cannot be based
on a PL011 r1p5, so I might guess that Broadcom have just referenced
the latest version of the documentation on our website, but have actually
implemented an earlier version."



From gang.chen at asianux.com  Mon May 20 21:51:57 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 09:51:57 +0800
Subject: [PATCH] include/linux/posix_acl.h: need 'return NULL' when BUG(), 
 if neither CONFIG_BUG nor HAVE_ARCH_BUG is defined.
In-Reply-To: <20130520163118.GX18614@n2100.arm.linux.org.uk>
References: <5199DBE2.5080707@asianux.com>
 <97dada79-cd78-4799-8f18-ed2bf8eee508@email.android.com>
 <20130520163118.GX18614@n2100.arm.linux.org.uk>
Message-ID: <519AD33D.1030106@asianux.com>

On 05/21/2013 12:31 AM, Russell King - ARM Linux wrote:
> On Mon, May 20, 2013 at 07:40:24AM -0700, Eric W. Biederman wrote:
>> Seriously?  The correct fix it would seem is to give a useful default BUG
>> definition.  Say *NULL.
> 
> Absolutely.
> 
> The real question is... how is this happening.  I've seen it occasionally
> in the randconfig builds - though I don't have any logs to hand which
> show that in the build system at the moment.  So, looking at the files:
> 

Maybe it is my fault for the incorrect configuration.

My operation:
  make EXTRA_CFLAGS=-W ARCH=arm randconfig
  make EXTRA_CFLAGS=-W ARCH=arm menuconfig
    set 'arm-linux-gnu-' as cross compiler prefix.
    select "MMU-based Paged Memory" in "System Type".
    select "Samsung S5PV210/S5PC110" in "ARM System type"
  make EXTRA_CFLAGS=-W ARCH=arm
  ...

In menuconfig, I do not touch the "S5PV210 Machines" or "S5PC110
Machines" in "System Type", and no machines will be chosen as default.

I think, it may be my fault, or need provide a default machine for S5P*
with randconfig (also better to select MMU automatically).


Thanks.
-- 
Chen Gang

Asianux Corporation


From shawn.guo at linaro.org  Mon May 20 22:12:03 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 21 May 2013 10:12:03 +0800
Subject: [PATCH 1/2] ARM: imx6q: call of_clk_init() to register fixed rate
 clocks
Message-ID: <1369102324-3084-1-git-send-email-shawn.guo@linaro.org>

As the fixed rate clocks are defined in device tree, we can just call
of_clk_init() to register them.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/clk-imx6q.c |   19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index a805911..1b883c7 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -276,21 +276,12 @@ int __init mx6q_clocks_init(void)
 	void __iomem *base;
 	int i, irq;
 
-	clk[dummy] = imx_clk_fixed("dummy", 0);
+	of_clk_init(NULL);
 
-	/* retrieve the freqency of fixed clocks from device tree */
-	for_each_compatible_node(np, NULL, "fixed-clock") {
-		u32 rate;
-		if (of_property_read_u32(np, "clock-frequency", &rate))
-			continue;
-
-		if (of_device_is_compatible(np, "fsl,imx-ckil"))
-			clk[ckil] = imx_clk_fixed("ckil", rate);
-		else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-			clk[ckih] = imx_clk_fixed("ckih", rate);
-		else if (of_device_is_compatible(np, "fsl,imx-osc"))
-			clk[osc] = imx_clk_fixed("osc", rate);
-	}
+	clk[dummy] = imx_clk_fixed("dummy", 0);
+	clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
+	clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
+	clk[osc] = imx_obtain_fixed_clock("osc", 0);
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
 	base = of_iomap(np, 0);
-- 
1.7.9.5




From shawn.guo at linaro.org  Mon May 20 22:12:04 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 21 May 2013 10:12:04 +0800
Subject: [PATCH 2/2] ARM: imx6: use common of_clk_init() call to initialize
 clocks
In-Reply-To: <1369102324-3084-1-git-send-email-shawn.guo@linaro.org>
References: <1369102324-3084-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1369102324-3084-2-git-send-email-shawn.guo@linaro.org>

Instead of explicitly calling clock initialization functions, we can
declare the functions with CLK_OF_DECLARE() and then call common
of_clk_init() to have them invoked properly.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/clk-imx6q.c   |    9 +++------
 arch/arm/mach-imx/clk-imx6sl.c  |    9 +++------
 arch/arm/mach-imx/common.h      |    2 --
 arch/arm/mach-imx/mach-imx6q.c  |    3 ++-
 arch/arm/mach-imx/mach-imx6sl.c |    3 ++-
 5 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1b883c7..0a4a658 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -270,14 +270,12 @@ static struct clk_div_table video_div_table[] = {
 	{ }
 };
 
-int __init mx6q_clocks_init(void)
+static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
 	struct device_node *np;
 	void __iomem *base;
 	int i, irq;
 
-	of_clk_init(NULL);
-
 	clk[dummy] = imx_clk_fixed("dummy", 0);
 	clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
 	clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
@@ -350,7 +348,7 @@ int __init mx6q_clocks_init(void)
 	clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
 	clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
-	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
+	np = ccm_node;
 	base = of_iomap(np, 0);
 	WARN_ON(!base);
 	ccm_base = base;
@@ -581,6 +579,5 @@ int __init mx6q_clocks_init(void)
 	WARN_ON(!base);
 	irq = irq_of_parse_and_map(np, 0);
 	mxc_timer_init(base, irq);
-
-	return 0;
 }
+CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 76835a7..a307ac2 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -66,15 +66,13 @@ static struct clk_div_table video_div_table[] = {
 static struct clk *clks[IMX6SL_CLK_CLK_END];
 static struct clk_onecell_data clk_data;
 
-int __init imx6sl_clocks_init(void)
+static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
 	struct device_node *np;
 	void __iomem *base;
 	int irq;
 	int i;
 
-	of_clk_init(NULL);
-
 	clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
 	clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
 	clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
@@ -125,7 +123,7 @@ int __init imx6sl_clocks_init(void)
 	clks[IMX6SL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
 	clks[IMX6SL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
 
-	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ccm");
+	np = ccm_node;
 	base = of_iomap(np, 0);
 	WARN_ON(!base);
 
@@ -265,6 +263,5 @@ int __init imx6sl_clocks_init(void)
 	WARN_ON(!base);
 	irq = irq_of_parse_and_map(np, 0);
 	mxc_timer_init(base, irq);
-
-	return 0;
 }
+CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 208e76f..ee78847 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,8 +68,6 @@ extern int mx27_clocks_init_dt(void);
 extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
-extern int mx6q_clocks_init(void);
-extern int imx6sl_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index ec4b7fc..045e5e3 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/cpu.h>
@@ -298,7 +299,7 @@ static void __init imx6q_init_irq(void)
 
 static void __init imx6q_timer_init(void)
 {
-	mx6q_clocks_init();
+	of_clk_init(NULL);
 	clocksource_of_init();
 	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
 			      imx6q_revision());
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 0130ee6..132db260 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -7,6 +7,7 @@
  *
  */
 
+#include <linux/clk-provider.h>
 #include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
@@ -33,7 +34,7 @@ static void __init imx6sl_init_irq(void)
 
 static void __init imx6sl_timer_init(void)
 {
-	imx6sl_clocks_init();
+	of_clk_init(NULL);
 }
 
 static const char *imx6sl_dt_compat[] __initdata = {
-- 
1.7.9.5




From swarren at wwwdotorg.org  Mon May 20 22:12:58 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 May 2013 20:12:58 -0600
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of
 PL011-r1p5
In-Reply-To: <007001ce55c4$139f96e0$3adec4a0$@lge.com>
References: <007301ce375e$bcf6d6b0$36e48410$@lge.com>
 <5191D200.3040604@wwwdotorg.org> <01fd01ce5072$d6b9fcd0$842df670$@lge.com>
 <5192A692.4010700@wwwdotorg.org> <022d01ce5107$8bc668e0$a3533aa0$@lge.com>
 <5193164E.6050400@wwwdotorg.org> <007001ce55c4$139f96e0$3adec4a0$@lge.com>
Message-ID: <519AD82A.6090809@wwwdotorg.org>

On 05/20/2013 07:39 PM, Jongsung Kim wrote:
> Jongsung Kim <neidhard.kim at lge.com> :
>> Stephen Warren <swarren at wwwdotorg.org> :
>>>> All r1p5 have 32-byte FIFO depth and it's not configurable. From the 
>>>> PL011
>>>> TRM:
>>>>
>>>> r1p4-r1p5	Contains the following differences in functionality:
>>>> 		* The receive and transmit FIFOs are increased to a depth of
> 32.
>>>> 		* The Revision field in the UARTPeriphID2 Register on page
> 3-24
>>>> 		  bits [7:4] now reads back as 0x3.
>>>
>>> Well, that certainly isn't true in practice. I think we should revert 
>>> this commit until we can determine what the problem is.
>>
>> I asked to the ARM support about this. Waiting for reply..
> 
> ARM support said they doesn't have information about BCM2835 UART. Does
> anyone have a communication channel to Broadcom? It takes time for me to
> get contact point to Broadcom.. (I'm trying)
> 
> However, ARM support also said:
> 
> "If the Broadcom part definitely has 16-deep FIFOs, it cannot be based
> on a PL011 r1p5, so I might guess that Broadcom have just referenced
> the latest version of the documentation on our website, but have actually
> implemented an earlier version."

This all seems rather academic. Irrespective of what the cause of the
problem is, the commit actively breaks a previously working
configuration. I still believe we should revert it first, then find out
exactly what's going on later. Should I sent the revert commit?



From shawn.guo at linaro.org  Mon May 20 22:17:20 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 21 May 2013 10:17:20 +0800
Subject: [PATCH v3 2/4] ARM: imx: add initial support for MVF600
In-Reply-To: <4003326.AbobOukrYT@wuerfel>
References: <1368684648-20826-1-git-send-email-b35083@freescale.com>
 <201305171429.52646.arnd@arndb.de>
 <20130517130603.GJ8607@S2101-09.ap.freescale.net>
 <4003326.AbobOukrYT@wuerfel>
Message-ID: <20130521021718.GA3080@S2101-09.ap.freescale.net>

On Fri, May 17, 2013 at 03:17:31PM +0200, Arnd Bergmann wrote:
> On Friday 17 May 2013 21:06:05 Shawn Guo wrote:
> > On Fri, May 17, 2013 at 02:29:52PM +0200, Arnd Bergmann wrote:
> > > > > Actually I think you should move that driver to drivers/clk and use
> > > > > of_clk_init(NULL) to initialize it.
> > > > > 
> > > > The mvf600 clock driver uses a lot of base clk support from mach-imx,
> > > > and can not be moved into drivers/clk as a single driver.  Right now, in
> > > > IMX clock drivers, we call of_clk_init() to only register fixed rate
> > > > clocks, since all the other clocks are not represented in device tree.
> > > 
> > > What are your plans for this in the long run?
> > > 
> > We can move all the IMX clock drivers into drivers/clk at some point
> > when necessary.  But I do not have a plan to register all the clocks
> > by merely calling of_clk_init(), because doing that would mean we have
> > to represent all these clocks in device tree.  For imx6q example, it's
> > about 200 ~ 300 nodes addition to DTB.  Device tree maintainers are
> > against to the idea.  They are perfectly fine with having clock driver
> > in kernel to represent/register these SoC internal clocks to clk
> > framework.
> 
> Can't we move the driver to drivers/clk and have it initialized through
> of_clk_init() without representing all clocks in the DT?

Sorry.  I just get aware of that I misunderstood your comment.  Yes,
declaring the clock initialization function with CLK_OF_DECLARE(),
we can use of_clk_init() to have them invoked properly.  I just sent a
patch to change imx6 clock driver to do that.

Shawn



From libo.chen at huawei.com  Mon May 20 22:42:00 2013
From: libo.chen at huawei.com (Libo Chen)
Date: Tue, 21 May 2013 10:42:00 +0800
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
Message-ID: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>

I find a lot of mistakes using struct platform_driver without owner.
So I pick up some of them including usb and net modules

Libo Chen (19):
  drivers/usb/musb: add missing platform_driver owner
  drivers/usb/host: add missing platform_driver owner
  drivers/usb/chipidea: add missing platform_driver owner
  drivers/usb/dwc3: add missing platform_driver owner
  drivers/ust/renesas_usbhs: add missing platform_driver owner
  drivers/usb/phy: add missing platform_driver owner
  drivers/usb/gadget: add missing platform_driver owner
  drivers/net/ethernet/amd: add missing platform_driver owner
  drivers/net/ethernet: add missing platform_driver owner
  drivers/net/ethernet/freescale: add missing platform_driver owner
  drivers/net/ethernet/natsemi: add missing platform_driver owner
  drivers/net/ethernet/xscale: add missing platform_driver owner
  drivers/net/ethernet/calxeda: add missing platform_driver owner
  drivers/net/wireless/brcm80211/brcmfmac: add missing platform_driver
    owner
  drivers/net/irda: add missing platform_driver owner
  drivers/net/wan: add missing platform_driver owner
  drivers/net/ethernet/nxp: add missing platform_driver owner
  drivers/net/ethernet/marvell: add missing platform_driver owne
  drivers/net/ethernet/renesas: add missing platform_driver owner

 drivers/net/ethernet/amd/am79c961a.c                   | 1 +
 drivers/net/ethernet/calxeda/xgmac.c                   | 1 +
 drivers/net/ethernet/dnet.c                            | 3 ++-
 drivers/net/ethernet/freescale/xgmac_mdio.c            | 1 +
 drivers/net/ethernet/korina.c                          | 1 +
 drivers/net/ethernet/marvell/mvneta.c                  | 1 +
 drivers/net/ethernet/natsemi/xtsonic.c                 | 1 +
 drivers/net/ethernet/nxp/lpc_eth.c                     | 1 +
 drivers/net/ethernet/renesas/sh_eth.c                  | 1 +
 drivers/net/ethernet/xscale/ixp4xx_eth.c               | 1 +
 drivers/net/irda/bfin_sir.c                            | 1 +
 drivers/net/irda/sh_irda.c                             | 1 +
 drivers/net/irda/sh_sir.c                              | 1 +
 drivers/net/irda/smsc-ircc2.c                          | 1 +
 drivers/net/wan/ixp4xx_hss.c                           | 1 +
 drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c | 3 ++-
 drivers/usb/chipidea/ci13xxx_msm.c                     | 2 +-
 drivers/usb/chipidea/core.c                            | 1 +
 drivers/usb/dwc3/core.c                                | 1 +
 drivers/usb/dwc3/dwc3-exynos.c                         | 1 +
 drivers/usb/dwc3/dwc3-omap.c                           | 1 +
 drivers/usb/gadget/r8a66597-udc.c                      | 1 +
 drivers/usb/host/ehci-atmel.c                          | 1 +
 drivers/usb/host/ehci-msm.c                            | 1 +
 drivers/usb/host/ehci-mv.c                             | 1 +
 drivers/usb/host/ehci-mxc.c                            | 1 +
 drivers/usb/host/ehci-omap.c                           | 1 +
 drivers/usb/host/ehci-spear.c                          | 1 +
 drivers/usb/host/isp1760-if.c                          | 1 +
 drivers/usb/host/oxu210hp-hcd.c                        | 1 +
 drivers/usb/host/xhci-plat.c                           | 1 +
 drivers/usb/musb/am35x.c                               | 1 +
 drivers/usb/musb/blackfin.c                            | 1 +
 drivers/usb/musb/da8xx.c                               | 1 +
 drivers/usb/musb/davinci.c                             | 1 +
 drivers/usb/musb/omap2430.c                            | 1 +
 drivers/usb/musb/tusb6010.c                            | 1 +
 drivers/usb/musb/ux500.c                               | 1 +
 drivers/usb/phy/phy-rcar-usb.c                         | 1 +
 drivers/usb/renesas_usbhs/common.c                     | 1 +
 40 files changed, 42 insertions(+), 3 deletions(-)

-- 
1.8.1.2




From gang.chen at asianux.com  Mon May 20 23:15:35 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 11:15:35 +0800
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <20130520091008.GB31359@mudshark.cambridge.arm.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
Message-ID: <519AE6D7.1090401@asianux.com>

On 05/20/2013 05:10 PM, Will Deacon wrote:
> Hi Chen,
> 
> On Mon, May 20, 2013 at 06:42:46AM +0100, Chen Gang wrote:
>>
>> Add the extern variable 'screen_info' according to arm32 has done.
>>
>> The related error:
>>   drivers/video/console/vgacon.c:1305: undefined reference to `screen_info'
>>
>>
>> Signed-off-by: Chen Gang <gang.chen at asianux.com>
>> ---
>>  arch/arm64/kernel/setup.c |   11 +++++++++++
>>  1 files changed, 11 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
>> index add6ea6..1055992 100644
>> --- a/arch/arm64/kernel/setup.c
>> +++ b/arch/arm64/kernel/setup.c
>> @@ -374,3 +374,14 @@ const struct seq_operations cpuinfo_op = {
>>  	.stop	= c_stop,
>>  	.show	= c_show
>>  };
>> +
>> +#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
>> +struct screen_info screen_info = {
>> +	.orig_video_lines	= 30,
>> +	.orig_video_cols	= 80,
>> +	.orig_video_mode	= 0,
>> +	.orig_video_ega_bx	= 0,
>> +	.orig_video_isVGA	= 1,
>> +	.orig_video_points	= 8
>> +};
>> +#endif
> 
> I think it would be better if we added a something like
> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
> like x86 can then select the former, and we can remove the long list of
> architectures from the current option.
> 

I guess your meaning is:

  under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
  So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.

Is it correct ?

If so, I recommend to add depend item for VGA_CONSOLE directly:

-------------------diff begin----------------------------------

diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index bc922c4..b759157 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -6,7 +6,7 @@ menu "Console display driver support"
 
 config VGA_CONSOLE
 	bool "VGA text console" if EXPERT || !X86
-	depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER)
+	depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !ARM64 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER)
 	default y
 	help
 	  Saying Y here will allow you to use Linux in text mode through a

-------------------diff end------------------------------------


Thanks.
-- 
Chen Gang

Asianux Corporation


From sfr at canb.auug.org.au  Mon May 20 23:49:35 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 21 May 2013 13:49:35 +1000
Subject: [PATCH] Finally eradicate CONFIG_HOTPLUG
Message-ID: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>

Ever since commit 45f035ab9b8f ("CONFIG_HOTPLUG should be always on"),
it has been basically impossible to build a kernel with CONFIG_HOTPLUG
turned off.  Remove all the remaining references to it.

Cc: linux-arch at vger.kernel.org
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: Doug Thompson <dougthompson at xmission.com>
Cc: linux-edac at vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas at google.com>
Cc: linux-pci at vger.kernel.org
Cc: linux-pcmcia at lists.infradead.org
Cc: Hans Verkuil <hans.verkuil at cisco.com>
Cc: Steven Whitehouse <swhiteho at redhat.com>
Cc: cluster-devel at redhat.com
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Pavel Machek <pavel at ucw.cz>
Cc: "Rafael J. Wysocki" <rjw at sisk.pl>
Cc: linux-pm at vger.kernel.org
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: linux-mm at kvack.org
Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au>
---
 Documentation/ABI/testing/sysfs-bus-pci |  5 +----
 Documentation/SubmitChecklist           |  2 +-
 Documentation/cpu-hotplug.txt           |  2 +-
 Documentation/hwmon/submitting-patches  |  3 +--
 Documentation/kbuild/kconfig.txt        |  2 +-
 Documentation/usb/hotplug.txt           |  6 +++---
 arch/arm/Kconfig                        |  2 +-
 arch/arm/kernel/module.c                |  8 --------
 arch/arm/kernel/vmlinux.lds.S           |  4 ----
 arch/arm/mach-ixp4xx/Kconfig            |  1 -
 arch/blackfin/Kconfig                   |  2 +-
 arch/cris/arch-v32/drivers/Kconfig      |  1 -
 arch/ia64/Kconfig                       |  1 -
 arch/mips/Kconfig                       |  2 +-
 arch/parisc/Kconfig                     |  1 -
 arch/powerpc/Kconfig                    |  2 +-
 arch/powerpc/mm/tlb_hash64.c            |  4 ++--
 arch/s390/Kconfig                       |  1 -
 arch/sh/Kconfig                         |  2 +-
 arch/sparc/Kconfig                      |  1 -
 arch/x86/Kconfig                        |  2 +-
 drivers/base/Kconfig                    |  2 --
 drivers/char/pcmcia/Kconfig             |  2 +-
 drivers/edac/Kconfig                    |  2 +-
 drivers/pci/Kconfig                     |  2 --
 drivers/pci/hotplug/Kconfig             |  2 +-
 drivers/pcmcia/Kconfig                  |  1 -
 drivers/staging/media/go7007/go7007.txt |  1 -
 fs/gfs2/Kconfig                         |  5 ++---
 include/asm-generic/vmlinux.lds.h       | 20 --------------------
 init/Kconfig                            |  3 ---
 kernel/power/Kconfig                    |  1 -
 mm/Kconfig                              |  2 +-
 33 files changed, 22 insertions(+), 75 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
index 1ce5ae3..5210a51 100644
--- a/Documentation/ABI/testing/sysfs-bus-pci
+++ b/Documentation/ABI/testing/sysfs-bus-pci
@@ -64,7 +64,6 @@ Description:
 		Writing a non-zero value to this attribute will
 		force a rescan of all PCI buses in the system, and
 		re-discover previously removed devices.
-		Depends on CONFIG_HOTPLUG.
 
 What:		/sys/bus/pci/devices/.../msi_irqs/
 Date:		September, 2011
@@ -90,7 +89,6 @@ Contact:	Linux PCI developers <linux-pci at vger.kernel.org>
 Description:
 		Writing a non-zero value to this attribute will
 		hot-remove the PCI device and any of its children.
-		Depends on CONFIG_HOTPLUG.
 
 What:		/sys/bus/pci/devices/.../pci_bus/.../rescan
 Date:		May 2011
@@ -99,7 +97,7 @@ Description:
 		Writing a non-zero value to this attribute will
 		force a rescan of the bus and all child buses,
 		and re-discover devices removed earlier from this
-		part of the device tree.  Depends on CONFIG_HOTPLUG.
+		part of the device tree.
 
 What:		/sys/bus/pci/devices/.../rescan
 Date:		January 2009
@@ -109,7 +107,6 @@ Description:
 		force a rescan of the device's parent bus and all
 		child buses, and re-discover devices removed earlier
 		from this part of the device tree.
-		Depends on CONFIG_HOTPLUG.
 
 What:		/sys/bus/pci/devices/.../reset
 Date:		July 2009
diff --git a/Documentation/SubmitChecklist b/Documentation/SubmitChecklist
index dc0e332..2b7e32d 100644
--- a/Documentation/SubmitChecklist
+++ b/Documentation/SubmitChecklist
@@ -105,5 +105,5 @@ kernel patches.
     same time, just various/random combinations of them]:
 
     CONFIG_SMP, CONFIG_SYSFS, CONFIG_PROC_FS, CONFIG_INPUT, CONFIG_PCI,
-    CONFIG_BLOCK, CONFIG_PM, CONFIG_HOTPLUG, CONFIG_MAGIC_SYSRQ,
+    CONFIG_BLOCK, CONFIG_PM, CONFIG_MAGIC_SYSRQ,
     CONFIG_NET, CONFIG_INET=n (but latter with CONFIG_NET=y)
diff --git a/Documentation/cpu-hotplug.txt b/Documentation/cpu-hotplug.txt
index 9f40135..0efd1b9 100644
--- a/Documentation/cpu-hotplug.txt
+++ b/Documentation/cpu-hotplug.txt
@@ -128,7 +128,7 @@ A: When doing make defconfig, Enable CPU hotplug support
 
    "Processor type and Features" -> Support for Hotpluggable CPUs
 
-Make sure that you have CONFIG_HOTPLUG, and CONFIG_SMP turned on as well.
+Make sure that you have CONFIG_SMP turned on as well.
 
 You would need to enable CONFIG_HOTPLUG_CPU for SMP suspend/resume support
 as well.
diff --git a/Documentation/hwmon/submitting-patches b/Documentation/hwmon/submitting-patches
index 843751c..4628646 100644
--- a/Documentation/hwmon/submitting-patches
+++ b/Documentation/hwmon/submitting-patches
@@ -27,8 +27,7 @@ increase the chances of your change being accepted.
   explicitly below the patch header.
 
 * If your patch (or the driver) is affected by configuration options such as
-  CONFIG_SMP or CONFIG_HOTPLUG, make sure it compiles for all configuration
-  variants.
+  CONFIG_SMP, make sure it compiles for all configuration variants.
 
 
 2. Adding functionality to existing drivers
diff --git a/Documentation/kbuild/kconfig.txt b/Documentation/kbuild/kconfig.txt
index 3f429ed..213859e 100644
--- a/Documentation/kbuild/kconfig.txt
+++ b/Documentation/kbuild/kconfig.txt
@@ -165,7 +165,7 @@ Searching in menuconfig:
 	Example:
 		/hotplug
 		This lists all config symbols that contain "hotplug",
-		e.g., HOTPLUG, HOTPLUG_CPU, MEMORY_HOTPLUG.
+		e.g., HOTPLUG_CPU, MEMORY_HOTPLUG.
 
 	For search help, enter / followed TAB-TAB-TAB (to highlight
 	<Help>) and Enter.  This will tell you that you can also use
diff --git a/Documentation/usb/hotplug.txt b/Documentation/usb/hotplug.txt
index 4c94571..6424b13 100644
--- a/Documentation/usb/hotplug.txt
+++ b/Documentation/usb/hotplug.txt
@@ -33,9 +33,9 @@ you get the best hotplugging when you configure a highly modular system.
 
 KERNEL HOTPLUG HELPER (/sbin/hotplug)
 
-When you compile with CONFIG_HOTPLUG, you get a new kernel parameter:
-/proc/sys/kernel/hotplug, which normally holds the pathname "/sbin/hotplug".
-That parameter names a program which the kernel may invoke at various times.
+There is a kernel parameter: /proc/sys/kernel/hotplug, which normally
+holds the pathname "/sbin/hotplug".  That parameter names a program
+which the kernel may invoke at various times.
 
 The /sbin/hotplug program can be invoked by any subsystem as part of its
 reaction to a configuration change, from a thread in that subsystem.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..b30db02 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1527,7 +1527,7 @@ config NR_CPUS
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
-	depends on SMP && HOTPLUG
+	depends on SMP
 	help
 	  Say Y here to experiment with turning CPUs off and on.  CPUs
 	  can be controlled through /sys/devices/system/cpu.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d..85c3fb6 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -288,24 +288,16 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
 
 		if (strcmp(".ARM.exidx.init.text", secname) == 0)
 			maps[ARM_SEC_INIT].unw_sec = s;
-		else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-			maps[ARM_SEC_DEVINIT].unw_sec = s;
 		else if (strcmp(".ARM.exidx", secname) == 0)
 			maps[ARM_SEC_CORE].unw_sec = s;
 		else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
 			maps[ARM_SEC_EXIT].unw_sec = s;
-		else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
-			maps[ARM_SEC_DEVEXIT].unw_sec = s;
 		else if (strcmp(".init.text", secname) == 0)
 			maps[ARM_SEC_INIT].txt_sec = s;
-		else if (strcmp(".devinit.text", secname) == 0)
-			maps[ARM_SEC_DEVINIT].txt_sec = s;
 		else if (strcmp(".text", secname) == 0)
 			maps[ARM_SEC_CORE].txt_sec = s;
 		else if (strcmp(".exit.text", secname) == 0)
 			maps[ARM_SEC_EXIT].txt_sec = s;
-		else if (strcmp(".devexit.text", secname) == 0)
-			maps[ARM_SEC_DEVEXIT].txt_sec = s;
 	}
 
 	for (i = 0; i < ARM_SEC_MAX; i++)
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index a871b8e..fa25e4e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -70,10 +70,6 @@ SECTIONS
 		ARM_EXIT_DISCARD(EXIT_TEXT)
 		ARM_EXIT_DISCARD(EXIT_DATA)
 		EXIT_CALL
-#ifndef CONFIG_HOTPLUG
-		*(.ARM.exidx.devexit.text)
-		*(.ARM.extab.devexit.text)
-#endif
 #ifndef CONFIG_MMU
 		*(.fixup)
 		*(__ex_table)
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 73a2d90..30e1ebe 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -235,7 +235,6 @@ config IXP4XX_QMGR
 config IXP4XX_NPE
 	tristate "IXP4xx Network Processor Engine support"
 	select FW_LOADER
-	select HOTPLUG
 	help
 	  This driver supports IXP4xx built-in network coprocessors
 	  and is automatically selected by Ethernet and HSS drivers.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index a117652..b573827 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -253,7 +253,7 @@ config NR_CPUS
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
-	depends on SMP && HOTPLUG
+	depends on SMP
 	default y
 
 config BF_REV_MIN
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index c55971a..ab725ed 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -617,7 +617,6 @@ config ETRAX_PV_CHANGEABLE_BITS
 config ETRAX_CARDBUS
         bool "Cardbus support"
         depends on ETRAX_ARCH_V32
-        select HOTPLUG
         help
 	 Enabled the ETRAX Cardbus driver.
 
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 1a2b774..5a768ad 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -376,7 +376,6 @@ config NR_CPUS
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
 	depends on SMP
-	select HOTPLUG
 	default n
 	---help---
 	  Say Y here to experiment with turning CPUs off and on.  CPUs
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7a58ab9..e433b90 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -962,7 +962,7 @@ config SYS_HAS_EARLY_PRINTK
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
-	depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU
+	depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
 	help
 	  Say Y here to allow turning CPUs off and on. CPUs can be
 	  controlled through /sys/devices/system/cpu.
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index cad060f..6d0969a 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -254,7 +254,6 @@ config IRQSTACKS
 config HOTPLUG_CPU
 	bool
 	default y if SMP
-	select HOTPLUG
 
 config ARCH_SELECT_MEMORY_MODEL
 	def_bool y
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c33e3ad..508e3fe 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -341,7 +341,7 @@ config SWIOTLB
 
 config HOTPLUG_CPU
 	bool "Support for enabling/disabling CPUs"
-	depends on SMP && HOTPLUG && (PPC_PSERIES || \
+	depends on SMP && (PPC_PSERIES || \
 	PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
 	---help---
 	  Say Y here to be able to disable and re-enable individual
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 023ec8a..7df1c5e 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -183,8 +183,8 @@ void tlb_flush(struct mmu_gather *tlb)
  * since 64K pages may overlap with other bridges when using 64K pages
  * with 4K HW pages on IO space.
  *
- * Because of that usage pattern, it's only available with CONFIG_HOTPLUG
- * and is implemented for small size rather than speed.
+ * Because of that usage pattern, it is implemented for small size rather
+ * than speed.
  */
 void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
 			      unsigned long end)
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 2c9789d..d97868b 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -302,7 +302,6 @@ config HOTPLUG_CPU
 	def_bool y
 	prompt "Support for hot-pluggable CPUs"
 	depends on SMP
-	select HOTPLUG
 	help
 	  Say Y here to be able to turn CPUs off and on. CPUs
 	  can be controlled through /sys/devices/system/cpu/cpu#.
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8c868cf..1020dd8 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -748,7 +748,7 @@ config NR_CPUS
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
-	depends on SMP && HOTPLUG
+	depends on SMP
 	help
 	  Say Y here to experiment with turning CPUs off and on.  CPUs
 	  can be controlled through /sys/devices/system/cpu.
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 9ac9f16..a00cbd3 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -243,7 +243,6 @@ config SECCOMP
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
 	depends on SPARC64 && SMP
-	select HOTPLUG
 	help
 	  Say Y here to experiment with turning CPUs off and on.  CPUs
 	  can be controlled through /sys/devices/system/cpu/cpu#.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 6a154a9..770cf04 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1726,7 +1726,7 @@ config PHYSICAL_ALIGN
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
-	depends on SMP && HOTPLUG
+	depends on SMP
 	---help---
 	  Say Y here to allow turning CPUs off and on. CPUs can be
 	  controlled through /sys/devices/system/cpu.
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index 07abd9d..5daa259 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -2,7 +2,6 @@ menu "Generic Driver Options"
 
 config UEVENT_HELPER_PATH
 	string "path to uevent helper"
-	depends on HOTPLUG
 	default ""
 	help
 	  Path to uevent helper program forked by the kernel for
@@ -23,7 +22,6 @@ config UEVENT_HELPER_PATH
 
 config DEVTMPFS
 	bool "Maintain a devtmpfs filesystem to mount at /dev"
-	depends on HOTPLUG
 	help
 	  This creates a tmpfs/ramfs filesystem instance early at bootup.
 	  In this filesystem, the kernel driver core maintains device
diff --git a/drivers/char/pcmcia/Kconfig b/drivers/char/pcmcia/Kconfig
index 2a166d5..b27f534 100644
--- a/drivers/char/pcmcia/Kconfig
+++ b/drivers/char/pcmcia/Kconfig
@@ -3,7 +3,7 @@
 #
 
 menu "PCMCIA character devices"
-	depends on HOTPLUG && PCMCIA!=n
+	depends on PCMCIA!=n
 
 config SYNCLINK_CS
 	tristate "SyncLink PC Card support"
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index e443f2c1..a697a64 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -145,7 +145,7 @@ config EDAC_E7XXX
 
 config EDAC_E752X
 	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
-	depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
+	depends on EDAC_MM_EDAC && PCI && X86
 	help
 	  Support for error detection and correction on the Intel
 	  E7520, E7525, E7320 server chipsets.
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6d51aa6..77497f1 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -55,7 +55,6 @@ config PCI_STUB
 config XEN_PCIDEV_FRONTEND
         tristate "Xen PCI Frontend"
         depends on PCI && X86 && XEN
-        select HOTPLUG
         select PCI_XEN
 	select XEN_XENBUS_FRONTEND
         default y
@@ -113,7 +112,6 @@ config PCI_IOAPIC
 	tristate "PCI IO-APIC hotplug support" if X86
 	depends on PCI
 	depends on ACPI
-	depends on HOTPLUG
 	default !X86
 
 config PCI_LABEL
diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig
index 9fcb87f..bb7ebb2 100644
--- a/drivers/pci/hotplug/Kconfig
+++ b/drivers/pci/hotplug/Kconfig
@@ -4,7 +4,7 @@
 
 menuconfig HOTPLUG_PCI
 	tristate "Support for PCI Hotplug"
-	depends on PCI && HOTPLUG && SYSFS
+	depends on PCI && SYSFS
 	---help---
 	  Say Y here if you have a motherboard with a PCI Hotplug controller.
 	  This allows you to add and remove PCI cards while the machine is
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index b90f85b..1c63624 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -4,7 +4,6 @@
 
 menuconfig PCCARD
 	tristate "PCCard (PCMCIA/CardBus) support"
-	depends on HOTPLUG
 	---help---
 	  Say Y here if you want to attach PCMCIA- or PC-cards to your Linux
 	  computer.  These are credit-card size devices such as network cards,
diff --git a/drivers/staging/media/go7007/go7007.txt b/drivers/staging/media/go7007/go7007.txt
index fcb3e23..dc0026c 100644
--- a/drivers/staging/media/go7007/go7007.txt
+++ b/drivers/staging/media/go7007/go7007.txt
@@ -78,7 +78,6 @@ All vendor-built kernels should already be configured properly.  However,
 for custom-built kernels, the following options need to be enabled in the
 kernel as built-in or modules:
 
-	CONFIG_HOTPLUG           - Support for hot-pluggable devices
 	CONFIG_MODULES           - Enable loadable module support
 	CONFIG_KMOD              - Automatic kernel module loading
 	CONFIG_FW_LOADER         - Hotplug firmware loading support
diff --git a/fs/gfs2/Kconfig b/fs/gfs2/Kconfig
index eb08c9e..432ea56 100644
--- a/fs/gfs2/Kconfig
+++ b/fs/gfs2/Kconfig
@@ -20,13 +20,12 @@ config GFS2_FS
 	  be found here: http://sources.redhat.com/cluster
 
 	  The "nolock" lock module is now built in to GFS2 by default. If
-	  you want to use the DLM, be sure to enable HOTPLUG and IPv4/6
-	  networking.
+	  you want to use the DLM, be sure to enable IPv4/6 networking.
 
 config GFS2_FS_LOCKING_DLM
 	bool "GFS2 DLM locking"
 	depends on (GFS2_FS!=n) && NET && INET && (IPV6 || IPV6=n) && \
-		HOTPLUG && DLM && CONFIGFS_FS && SYSFS
+		DLM && CONFIGFS_FS && SYSFS
 	help
 	  Multiple node locking module for GFS2
 
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index eb58d2d..4f27372 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -68,14 +68,6 @@
  * are handled as text/data or they can be discarded (which
  * often happens at runtime)
  */
-#ifdef CONFIG_HOTPLUG
-#define DEV_KEEP(sec)    *(.dev##sec)
-#define DEV_DISCARD(sec)
-#else
-#define DEV_KEEP(sec)
-#define DEV_DISCARD(sec) *(.dev##sec)
-#endif
-
 #ifdef CONFIG_HOTPLUG_CPU
 #define CPU_KEEP(sec)    *(.cpu##sec)
 #define CPU_DISCARD(sec)
@@ -182,8 +174,6 @@
 	*(.data)							\
 	*(.ref.data)							\
 	*(.data..shared_aligned) /* percpu related */			\
-	DEV_KEEP(init.data)						\
-	DEV_KEEP(exit.data)						\
 	CPU_KEEP(init.data)						\
 	CPU_KEEP(exit.data)						\
 	MEM_KEEP(init.data)						\
@@ -372,8 +362,6 @@
 	/* __*init sections */						\
 	__init_rodata : AT(ADDR(__init_rodata) - LOAD_OFFSET) {		\
 		*(.ref.rodata)						\
-		DEV_KEEP(init.rodata)					\
-		DEV_KEEP(exit.rodata)					\
 		CPU_KEEP(init.rodata)					\
 		CPU_KEEP(exit.rodata)					\
 		MEM_KEEP(init.rodata)					\
@@ -416,8 +404,6 @@
 		*(.text.hot)						\
 		*(.text)						\
 		*(.ref.text)						\
-	DEV_KEEP(init.text)						\
-	DEV_KEEP(exit.text)						\
 	CPU_KEEP(init.text)						\
 	CPU_KEEP(exit.text)						\
 	MEM_KEEP(init.text)						\
@@ -503,7 +489,6 @@
 /* init and exit section handling */
 #define INIT_DATA							\
 	*(.init.data)							\
-	DEV_DISCARD(init.data)						\
 	CPU_DISCARD(init.data)						\
 	MEM_DISCARD(init.data)						\
 	KERNEL_CTORS()							\
@@ -511,7 +496,6 @@
 	*(.init.rodata)							\
 	FTRACE_EVENTS()							\
 	TRACE_SYSCALLS()						\
-	DEV_DISCARD(init.rodata)					\
 	CPU_DISCARD(init.rodata)					\
 	MEM_DISCARD(init.rodata)					\
 	CLK_OF_TABLES()							\
@@ -521,14 +505,11 @@
 
 #define INIT_TEXT							\
 	*(.init.text)							\
-	DEV_DISCARD(init.text)						\
 	CPU_DISCARD(init.text)						\
 	MEM_DISCARD(init.text)
 
 #define EXIT_DATA							\
 	*(.exit.data)							\
-	DEV_DISCARD(exit.data)						\
-	DEV_DISCARD(exit.rodata)					\
 	CPU_DISCARD(exit.data)						\
 	CPU_DISCARD(exit.rodata)					\
 	MEM_DISCARD(exit.data)						\
@@ -536,7 +517,6 @@
 
 #define EXIT_TEXT							\
 	*(.exit.text)							\
-	DEV_DISCARD(exit.text)						\
 	CPU_DISCARD(exit.text)						\
 	MEM_DISCARD(exit.text)
 
diff --git a/init/Kconfig b/init/Kconfig
index 9d3a788..a5e0917 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1244,9 +1244,6 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
 	  the unaligned access emulation.
 	  see arch/parisc/kernel/unaligned.c for reference
 
-config HOTPLUG
-	def_bool y
-
 config HAVE_PCSPKR_PLATFORM
 	bool
 
diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig
index 5dfdc9e..9c39de0 100644
--- a/kernel/power/Kconfig
+++ b/kernel/power/Kconfig
@@ -100,7 +100,6 @@ config PM_SLEEP_SMP
 	depends on SMP
 	depends on ARCH_SUSPEND_POSSIBLE || ARCH_HIBERNATION_POSSIBLE
 	depends on PM_SLEEP
-	select HOTPLUG
 	select HOTPLUG_CPU
 
 config PM_AUTOSLEEP
diff --git a/mm/Kconfig b/mm/Kconfig
index e742d06..f5e698e 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -173,7 +173,7 @@ config HAVE_BOOTMEM_INFO_NODE
 config MEMORY_HOTPLUG
 	bool "Allow for memory hot-add"
 	depends on SPARSEMEM || X86_64_ACPI_NUMA
-	depends on HOTPLUG && ARCH_ENABLE_MEMORY_HOTPLUG
+	depends on ARCH_ENABLE_MEMORY_HOTPLUG
 	depends on (IA64 || X86 || PPC_BOOK3S_64 || SUPERH || S390)
 
 config MEMORY_HOTPLUG_SPARSE
-- 
1.8.1

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From gang.chen at asianux.com  Tue May 21 00:06:52 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 12:06:52 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <20130520095606.GH31359@mudshark.cambridge.arm.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
Message-ID: <519AF2DC.2040200@asianux.com>

On 05/20/2013 05:56 PM, Will Deacon wrote:
> On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
>> On Mon, 20 May 2013 14:48:05 +0800, Chen Gang <gang.chen at asianux.com>
>> wrote:
>>> Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with allmodconfig.
>>>
>>> The related error:
>>>   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
>>>   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
>>>   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
>>>   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>>>
>>>
>>> Signed-off-by: Chen Gang <gang.chen at asianux.com>
>>> ---
>>>  arch/arm64/kernel/time.c |    1 +
>>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
>>> index a551f88..7fcba80 100644
>>> --- a/arch/arm64/kernel/time.c
>>> +++ b/arch/arm64/kernel/time.c
>>> @@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
>>>  	*timer_value = arch_timer_read_counter();
>>>  	return 0;
>>>  }
>>> +EXPORT_SYMBOL_GPL(read_current_timer);
>>>  
>>>  void __init time_init(void)
>>>  {
>>
>> While this solves the problem, I'm not sure this is the best fix. The real
>> issue is with get_cycles, which is a macro around read_current_timer.
>>
>> AArch32 exports it because of the number of timer implementations. On
>> arm64, we should be able to just return CNTVCT_EL0.
>>
>> Catalin, Will, what do you think?
> 
> Should be ok once the arch timer driver has moved exclusively to virtual
> time. I'm also not sure we even need to implement read_current_timer() --
> it's only used for delay-loop calibration, which we don't need for the
> arch timer.
> 

For whether we need implement read_current_timer():

  many platforms have implemented it (openrisc, arm, sparc, hexagon, avr32, x86).
  it is called by init/calibrate.c when 'ARCH_HAS_READ_CURRENT_TIMER' is defined.
  since arm64 can implement it, better to provide it as an architect features to let outside use.

For the implementation of read_current_timer():

  it has to face various configurations
    (e.g. CONFIG_ARM_ARCH_TIMER, arch_timer_read_zero, arch_counter_get_cntvct, arch_counter_get_cntpct)
  so better still use variable instead of.
    (excuse me, I do not know what is 'CNTVCT_EL0', is it like a constant number ?)

For the implementation of get_cycles()

  if read_current_timer() is provided,
  better to let get_cycles() to call it, instead of implement once again.



Thanks.
-- 
Chen Gang

Asianux Corporation


From skannan at codeaurora.org  Tue May 21 00:44:38 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 20 May 2013 21:44:38 -0700
Subject: [PATCH v4 5/5] clk: clk-mux: implement remuxing on set_rate
In-Reply-To: <1369056507-32521-6-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-6-git-send-email-james.hogan@imgtec.com>
Message-ID: <519AFBB6.90700@codeaurora.org>

On 05/20/2013 06:28 AM, James Hogan wrote:
> Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't
> set. This implements determine_rate for clk-mux to propagate to each
> parent and to choose the best one (like clk-divider this chooses the
> parent which provides the fastest rate <= the requested rate).
>
> The determine_rate op is implemented as a core helper function so that
> it can be easily used by more complex clocks which incorporate muxes.
>
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> ---
> Changes in v4:
>
> * never pass NULL to determine_rate's best_parent_clk parameter.
>
> Changes in v3:
>
> * rename/invert CLK_SET_RATE_REMUX to CLK_SET_RATE_NO_REPARENT and move
>    to patch 3.
>
>   drivers/clk/clk-mux.c        |  1 +
>   drivers/clk/clk.c            | 49 ++++++++++++++++++++++++++++++++++++++++++++
>   include/linux/clk-provider.h |  3 +++
>   3 files changed, 53 insertions(+)
>
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 25b1734..cecfa01 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -100,6 +100,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>   const struct clk_ops clk_mux_ops = {
>   	.get_parent = clk_mux_get_parent,
>   	.set_parent = clk_mux_set_parent,
> +	.determine_rate = __clk_mux_determine_rate,
>   };
>   EXPORT_SYMBOL_GPL(clk_mux_ops);
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 3ce4810..85b661d 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -692,6 +692,55 @@ struct clk *__clk_lookup(const char *name)
>   	return NULL;
>   }
>
> +/*
> + * Helper for finding best parent to provide a given frequency. This can be used
> + * directly as a determine_rate callback (e.g. for a mux), or from a more
> + * complex clock that may combine a mux with other operations.
> + */
> +long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
> +			      unsigned long *best_parent_rate,
> +			      struct clk **best_parent_p)
> +{
> +	struct clk *clk = hw->clk, *parent, *best_parent = NULL;
> +	int i, num_parents;
> +	unsigned long parent_rate, best = 0;
> +
> +	/* if NO_REPARENT flag set, pass through to current parent */
> +	if (clk->flags & CLK_SET_RATE_NO_REPARENT) {
> +		parent = clk->parent;
> +		if (clk->flags & CLK_SET_RATE_PARENT)
> +			best = __clk_round_rate(parent, rate);
> +		else if (parent)
> +			best = __clk_get_rate(parent);
> +		else
> +			best = __clk_get_rate(clk);
> +		goto out;
> +	}
> +
> +	/* find the parent that can provide the fastest rate <= rate */
> +	num_parents = clk->num_parents;
> +	for (i = 0; i < num_parents; i++) {

While writing a similar code for our internal tree, I quickly came to 
the realization that, "all parents are equal, but some are more equal 
than others". The simplest example is a clock tree like this:

Source -> Divider -> Mux
Source -> Mux

A rate of Y can be achieved for Mux by either running Source at Y and 
picking that input or running Source at Y * 2 and Divider set to div-2 
and picking the Divider input.

The solution seems to be a priority list of parents. I'm sure there 
would be other reason (jitter, clock quality, etc) for a mux to pick one 
parent vs. another when both of them can provide the required rate.

I think this loop should loop over parents based on their priority 
order. So, parents should become a struct of { clk, index } and have the 
parents listed in the order of priority. Well, at least in that long run 
that would be better to avoid messing up parent/index values. But for 
now, you could just have a priority array of index or parents.

It might not fit 100% of the cases where two parents can provide the 
same rate, but it should fit most use cases.

> +		parent = clk_get_parent_by_index(clk, i);
> +		if (!parent)
> +			continue;
> +		if (clk->flags & CLK_SET_RATE_PARENT)
> +			parent_rate = __clk_round_rate(parent, rate);
> +		else
> +			parent_rate = __clk_get_rate(parent);
> +		if (parent_rate <= rate && parent_rate > best) {
> +			best_parent = parent;
> +			best = parent_rate;
> +		}
> +	}
> +
> +out:
> +	if (best_parent)
> +		*best_parent_p = best_parent;
> +	*best_parent_rate = best;
> +
> +	return best;
> +}
> +

Thanks,
Saravana

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From kishon at ti.com  Tue May 21 01:01:09 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Tue, 21 May 2013 10:31:09 +0530
Subject: [PATCH v6 0/9] Generic PHY Framework
In-Reply-To: <1367229812-30574-1-git-send-email-kishon@ti.com>
References: <1367229812-30574-1-git-send-email-kishon@ti.com>
Message-ID: <519AFF95.9060002@ti.com>

Hi,

On Monday 29 April 2013 03:33 PM, Kishon Vijay Abraham I wrote:
> Added a generic PHY framework that provides a set of APIs for the PHY drivers
> to create/destroy a PHY and APIs for the PHY users to obtain a reference to
> the PHY with or without using phandle.
>
> This framework will be of use only to devices that uses external PHY (PHY
> functionality is not embedded within the controller).
>
> The intention of creating this framework is to bring the phy drivers spread
> all over the Linux kernel to drivers/phy to increase code re-use and to
> increase code maintainability.
>
> Comments to make PHY as bus wasn't done because PHY devices can be part of
> other bus and making a same device attached to multiple bus leads to bad
> design.
>
> If the PHY driver has to send notification on connect/disconnect, the PHY
> driver should make use of the extcon framework. Using this susbsystem
> to use extcon framwork will have to be analysed.
>
> Making omap-usb2 and twl4030 to use this framework is provided as a sample.
>
> This patch series is developed on linux-next tree.

Any comments on this patch series?

Thanks
Kishon


From skannan at codeaurora.org  Tue May 21 01:10:55 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 20 May 2013 22:10:55 -0700
Subject: [PATCH v4 3/5] clk: add support for clock reparent on set_rate
In-Reply-To: <1369056507-32521-4-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-4-git-send-email-james.hogan@imgtec.com>
Message-ID: <519B01DF.1080700@codeaurora.org>

On 05/20/2013 06:28 AM, James Hogan wrote:
> Add core support to allow clock implementations to select the best
> parent clock when rounding a rate, e.g. the one which can provide the
> closest clock rate to that requested. This is by way of adding a new
> clock op, determine_rate(), which is like round_rate() but has an extra
> parameter to allow the clock implementation to optionally select a
> different parent clock. The core then takes care of reparenting the
> clock when setting the rate.
>
> The parent change takes place with the help of some new private data
> members. struct clk::new_parent specifies a clock's new parent (NULL
> indicates no change), and struct clk::new_child specifies a clock's new
> child (whose new_parent member points back to it). The purpose of these
> are to allow correct walking of the future tree for notifications prior
> to actually reparenting any clocks, specifically to skip child clocks
> who are being reparented to another clock (they will be notified via the
> new parent), and to include any new child clock. These pointers are set
> by clk_calc_subtree(), and the new_child pointer gets cleared when a
> child is actually reparented to avoid duplicate POST_RATE_CHANGE
> notifications.
>
> Each place where round_rate() is called, determine_rate() is checked
> first and called in preference. This restructures a few of the call
> sites to simplify the logic into if/else blocks.
>
> Signed-off-by: James Hogan <james.hogan at imgtec.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> ---
> Changes in v4:
>
> * (not included Stephen Boyd's Reviewed-by due to changes)
> * replace __clk_set_parent_no_recalc with __clk_set_parent.
> * never pass NULL to determine_rate's best_parent_clk parameter, and
>    slight refactor of __clk_round_rate to use local copy of clk->parent.
> * a few new comments around use of clk::new_child.
>
> Changes in v3:
>
> * rebased on v3.10-rc1.
> * store new_parent_index in struct clk too (calculated from
>    clk_fetch_parent_index, and passed through __clk_set_parent_no_recalc
>    to __clk_set_parent).
> * allow determine_rate to satisfy recalc_rate check in __clk_init.
>
>   Documentation/clk.txt        |   4 ++
>   drivers/clk/clk.c            | 142 +++++++++++++++++++++++++++++--------------
>   include/linux/clk-private.h  |   3 +
>   include/linux/clk-provider.h |   7 +++
>   4 files changed, 110 insertions(+), 46 deletions(-)
>
> diff --git a/Documentation/clk.txt b/Documentation/clk.txt
> index b9911c2..3110ba4 100644
> --- a/Documentation/clk.txt
> +++ b/Documentation/clk.txt
> @@ -70,6 +70,10 @@ the operations defined in clk.h:
>   						unsigned long parent_rate);
>   		long		(*round_rate)(struct clk_hw *hw, unsigned long,
>   						unsigned long *);
> +		long		(*determine_rate)(struct clk_hw *hw,
> +						unsigned long rate,
> +						unsigned long *best_parent_rate,
> +						struct clk **best_parent_clk);
>   		int		(*set_parent)(struct clk_hw *hw, u8 index);
>   		u8		(*get_parent)(struct clk_hw *hw);
>   		int		(*set_rate)(struct clk_hw *hw, unsigned long);
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index a4cd6bc..3ce4810 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -888,21 +888,24 @@ EXPORT_SYMBOL_GPL(clk_enable);
>   unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
>   {
>   	unsigned long parent_rate = 0;
> +	struct clk *parent;
>
>   	if (!clk)
>   		return 0;
>
> -	if (!clk->ops->round_rate) {
> -		if (clk->flags & CLK_SET_RATE_PARENT)
> -			return __clk_round_rate(clk->parent, rate);
> -		else
> -			return clk->rate;
> -	}
> -
> -	if (clk->parent)
> -		parent_rate = clk->parent->rate;
> -
> -	return clk->ops->round_rate(clk->hw, rate, &parent_rate);
> +	parent = clk->parent;
> +	if (parent)
> +		parent_rate = parent->rate;
> +
> +	if (clk->ops->determine_rate)
> +		return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
> +						&parent);
> +	else if (clk->ops->round_rate)
> +		return clk->ops->round_rate(clk->hw, rate, &parent_rate);
> +	else if (clk->flags & CLK_SET_RATE_PARENT)
> +		return __clk_round_rate(clk->parent, rate);
> +	else
> +		return clk->rate;
>   }
>
>   /**
> @@ -1055,6 +1058,10 @@ static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
>
>   static void clk_reparent(struct clk *clk, struct clk *new_parent)
>   {
> +	/* avoid duplicate POST_RATE_CHANGE notifications */
> +	if (new_parent->new_child == clk)
> +		new_parent->new_child = NULL;
> +
>   	hlist_del(&clk->child_node);
>
>   	if (new_parent)
> @@ -1173,18 +1180,25 @@ out:
>   	return ret;
>   }
>
> -static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
> +static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
> +			     struct clk *new_parent, u8 p_index)
>   {
>   	struct clk *child;
>
>   	clk->new_rate = new_rate;
> +	clk->new_parent = new_parent;
> +	clk->new_parent_index = p_index;
> +	/* include clk in new parent's PRE_RATE_CHANGE notifications */
> +	clk->new_child = NULL;
> +	if (new_parent && new_parent != clk->parent)
> +		new_parent->new_child = clk;
>
>   	hlist_for_each_entry(child, &clk->children, child_node) {
>   		if (child->ops->recalc_rate)
>   			child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
>   		else
>   			child->new_rate = new_rate;
> -		clk_calc_subtree(child, child->new_rate);
> +		clk_calc_subtree(child, child->new_rate, NULL, 0);
>   	}
>   }
>
> @@ -1195,50 +1209,63 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
>   static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
>   {
>   	struct clk *top = clk;
> +	struct clk *old_parent, *parent;
>   	unsigned long best_parent_rate = 0;
>   	unsigned long new_rate;
> +	u8 p_index = 0;
>
>   	/* sanity */
>   	if (IS_ERR_OR_NULL(clk))
>   		return NULL;
>
>   	/* save parent rate, if it exists */
> -	if (clk->parent)
> -		best_parent_rate = clk->parent->rate;
> -
> -	/* never propagate up to the parent */
> -	if (!(clk->flags & CLK_SET_RATE_PARENT)) {
> -		if (!clk->ops->round_rate) {
> -			clk->new_rate = clk->rate;
> -			return NULL;
> -		}
> -		new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
> +	parent = old_parent = clk->parent;
> +	if (parent)
> +		best_parent_rate = parent->rate;
> +
> +	/* find the closest rate and parent clk/rate */
> +	if (clk->ops->determine_rate) {
> +		new_rate = clk->ops->determine_rate(clk->hw, rate,
> +						    &best_parent_rate,
> +						    &parent);
> +	} else if (clk->ops->round_rate) {
> +		new_rate = clk->ops->round_rate(clk->hw, rate,
> +						&best_parent_rate);
> +	} else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
> +		/* pass-through clock without adjustable parent */
> +		clk->new_rate = clk->rate;
> +		return NULL;
> +	} else {
> +		/* pass-through clock with adjustable parent */
> +		top = clk_calc_new_rates(parent, rate);
> +		new_rate = parent->new_rate;
>   		goto out;
>   	}
>
> -	/* need clk->parent from here on out */
> -	if (!clk->parent) {
> -		pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
> +	/* some clocks must be gated to change parent */
> +	if (parent != old_parent &&
> +	    (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
> +		pr_debug("%s: %s not gated but wants to reparent\n",
> +			 __func__, clk->name);
>   		return NULL;
>   	}
>
> -	if (!clk->ops->round_rate) {
> -		top = clk_calc_new_rates(clk->parent, rate);
> -		new_rate = clk->parent->new_rate;
> -
> -		goto out;
> +	/* try finding the new parent index */
> +	if (parent) {
> +		p_index = clk_fetch_parent_index(clk, parent);
> +		if (p_index == clk->num_parents) {
> +			pr_debug("%s: clk %s can not be parent of clk %s\n",
> +				 __func__, parent->name, clk->name);
> +			return NULL;
> +		}
>   	}
>
> -	new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
> -
> -	if (best_parent_rate != clk->parent->rate) {
> -		top = clk_calc_new_rates(clk->parent, best_parent_rate);
> -
> -		goto out;
> -	}
> +	if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
> +	    best_parent_rate != parent->rate)
> +		top = clk_calc_new_rates(parent, best_parent_rate);
>
>   out:
> -	clk_calc_subtree(clk, new_rate);
> +	clk_calc_subtree(clk, new_rate, parent, p_index);
>
>   	return top;
>   }
> @@ -1250,7 +1277,7 @@ out:
>    */
>   static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
>   {
> -	struct clk *child, *fail_clk = NULL;
> +	struct clk *child, *tmp_clk, *fail_clk = NULL;
>   	int ret = NOTIFY_DONE;
>
>   	if (clk->rate == clk->new_rate)
> @@ -1263,9 +1290,19 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
>   	}
>
>   	hlist_for_each_entry(child, &clk->children, child_node) {
> -		clk = clk_propagate_rate_change(child, event);
> -		if (clk)
> -			fail_clk = clk;
> +		/* Skip children who will be reparented to another clock */
> +		if (child->new_parent && child->new_parent != clk)
> +			continue;
> +		tmp_clk = clk_propagate_rate_change(child, event);
> +		if (tmp_clk)
> +			fail_clk = tmp_clk;
> +	}
> +
> +	/* handle the new child who might not be in clk->children yet */
> +	if (clk->new_child) {
> +		tmp_clk = clk_propagate_rate_change(clk->new_child, event);
> +		if (tmp_clk)
> +			fail_clk = tmp_clk;
>   	}
>
>   	return fail_clk;
> @@ -1283,6 +1320,10 @@ static void clk_change_rate(struct clk *clk)
>
>   	old_rate = clk->rate;
>
> +	/* set parent */
> +	if (clk->new_parent && clk->new_parent != clk->parent)
> +		__clk_set_parent(clk, clk->new_parent, clk->new_parent_index);
> +
>   	if (clk->parent)
>   		best_parent_rate = clk->parent->rate;
>
> @@ -1297,8 +1338,16 @@ static void clk_change_rate(struct clk *clk)
>   	if (clk->notifier_count && old_rate != clk->rate)
>   		__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
>
> -	hlist_for_each_entry(child, &clk->children, child_node)
> +	hlist_for_each_entry(child, &clk->children, child_node) {
> +		/* Skip children who will be reparented to another clock */
> +		if (child->new_parent && child->new_parent != clk)
> +			continue;
>   		clk_change_rate(child);
> +	}
> +
> +	/* handle the new child who might not be in clk->children yet */
> +	if (clk->new_child)
> +		clk_change_rate(clk->new_child);
>   }
>
>   /**
> @@ -1545,8 +1594,9 @@ int __clk_init(struct device *dev, struct clk *clk)
>
>   	/* check that clk_ops are sane.  See Documentation/clk.txt */
>   	if (clk->ops->set_rate &&
> -			!(clk->ops->round_rate && clk->ops->recalc_rate)) {
> -		pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
> +	    !((clk->ops->round_rate || clk->ops->determine_rate) &&
> +	      clk->ops->recalc_rate)) {
> +		pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
>   				__func__, clk->name);
>   		ret = -EINVAL;
>   		goto out;
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index dd7adff..8138c94 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -33,8 +33,11 @@ struct clk {
>   	const char		**parent_names;
>   	struct clk		**parents;
>   	u8			num_parents;
> +	u8			new_parent_index;

Why do you need this? Given the new_parent, can't the specific clock 
implementation just look it up when set_rate() is called? Wouldn't that 
be the only time you would actually need the index?

If it's just for optimization of some error cases, I think we should 
drop this to keep the code simpler. One less state to keep track of when 
reading, writing or reviewing the clock framework.

I would like to do a more thorough review of this patch, but it's been a 
while since I have looked at clk.c. So, I might not be able to do it 
soon enough. But I can't ask to hold off this patch just because I don't 
have time. So, I'll see what I can do.

-Saravana




-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From andrew at lunn.ch  Tue May 21 01:11:32 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 21 May 2013 07:11:32 +0200
Subject: [PATCH V3 09/10] ARM: Kirkwood: Add dts files for Sheevaplug and
 eSATA Sheevaplug
In-Reply-To: <1369090911-1479-10-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
 <1369090911-1479-10-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130521051132.GJ26249@lunn.ch>

On Tue, May 21, 2013 at 01:01:50AM +0200, Simon Baatz wrote:
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  arch/arm/boot/dts/Makefile                        |    2 +
>  arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi |   97 +++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts   |   40 +++++++++
>  arch/arm/boot/dts/kirkwood-sheevaplug.dts         |   45 ++++++++++
>  4 files changed, 184 insertions(+)
>  create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
>  create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
>  create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b9f7121..e81a387 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -84,6 +84,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
>  	kirkwood-ns2max.dtb \
>  	kirkwood-ns2mini.dtb \
>  	kirkwood-nsa310.dtb \
> +	kirkwood-sheevaplug.dtb \
> +	kirkwood-sheevaplug-esata.dtb \
>  	kirkwood-topkick.dtb \
>  	kirkwood-ts219-6281.dtb \
>  	kirkwood-ts219-6282.dtb \
> diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
> new file mode 100644
> index 0000000..9d59475
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
> @@ -0,0 +1,97 @@
> +/*
> + * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
> + *
> + * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
> + *
> + * Licensed under GPLv2
> + */
> +
> +/include/ "kirkwood.dtsi"
> +/include/ "kirkwood-6281.dtsi"
> +
> +/ {
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x20000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	ocp at f1000000 {
> +		pinctrl: pinctrl at 10000 {
> +
> +			pmx_usb_power_enable: pmx-usb-power-enable {
> +				marvell,pins = "mpp29";
> +				marvell,function = "gpio";
> +			};
> +			pmx_led_red: pmx-led-red {
> +				marvell,pins = "mpp46";
> +				marvell,function = "gpio";
> +			};
> +			pmx_led_blue: pmx-led-blue {
> +				marvell,pins = "mpp49";
> +				marvell,function = "gpio";
> +			};
> +			pmx_sdio_cd: pmx-sdio-cd {
> +				marvell,pins = "mpp44";
> +				marvell,function = "gpio";
> +			};
> +			pmx_sdio_wp: pmx-sdio-wp {
> +				marvell,pins = "mpp47";
> +				marvell,function = "gpio";
> +			};
> +		};
> +		serial at 12000 {
> +			status = "okay";
> +		};
> +
> +		nand at 3000000 {
> +			status = "okay";
> +
> +			partition at 0 {
> +				label = "u-boot";
> +				reg = <0x0000000 0x100000>;
> +			};
> +
> +			partition at 100000 {
> +				label = "uImage";
> +				reg = <0x0100000 0x400000>;
> +			};
> +
> +			partition at 500000 {
> +				label = "root";
> +				reg = <0x0500000 0x1fb00000>;
> +			};
> +		};
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		usb_power: regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "USB Power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&gpio0 29 0>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		health {
> +			label = "sheevaplug:blue:health";
> +			gpios = <&gpio1 17 1>;
> +			linux,default-trigger = "default-on";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
> new file mode 100644
> index 0000000..1c6946a
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
> @@ -0,0 +1,40 @@
> +/*
> + * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
> + *
> + * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
> + *
> + * Licensed under GPLv2
> + */
> +
> +/dts-v1/;
> +
> +/include/ "kirkwood-sheevaplug-common.dtsi"
> +
> +/ {
> +	model = "Globalscale Technologies eSATA SheevaPlug";
> +	compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	ocp at f1000000 {
> +		pinctrl: pinctrl at 10000 {
> +
> +			pinctrl-0 = < &pmx_nand &pmx_uart0
> +				      &pmx_usb_power_enable
> +				      &pmx_led_blue>;
> +			pinctrl-names = "default";
> +
> +		};
> +
> +		sata at 80000 {
> +			status = "okay";
> +			nr-ports = <2>;
> +		};
> +
> +		mvsdio at 90000 {
> +			pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
> +			pinctrl-names = "default";
> +			status = "okay";
> +			cd-gpios = <&gpio1 12 1>;
> +			wp-gpios = <&gpio1 15 0>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
> new file mode 100644
> index 0000000..f7684066
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
> @@ -0,0 +1,45 @@
> +/*
> + * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
> + *
> + * Copyright (C) 2013 Simon Baatz <gmbnomis at gmail.com>
> + *
> + * Licensed under GPLv2
> + */
> +
> +/dts-v1/;
> +
> +/include/ "kirkwood-sheevaplug-common.dtsi"
> +
> +/ {
> +	model = "Globalscale Technologies SheevaPlug";
> +	compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	ocp at f1000000 {
> +		pinctrl: pinctrl at 10000 {
> +
> +			pinctrl-0 = < &pmx_nand &pmx_uart0
> +				      &pmx_usb_power_enable
> +				      &pmx_led_red
> +				      &pmx_led_blue>;
> +			pinctrl-names = "default";
> +
> +		};
> +
> +		mvsdio at 90000 {
> +			pinctrl-0 = <&pmx_sdio>;
> +			pinctrl-names = "default";
> +			status = "okay";
> +			/* No CD or WP GPIOs */
> +			broken-cd;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		misc {
> +			label = "sheevaplug:red:misc";
> +			gpios = <&gpio1 14 1>;
> +		};
> +	};
> +};
> -- 
> 1.7.9.5
> 

Hi Simon

Looks good

Acked-by: Andrew Lunn <andrew at lunn.ch>


From andrew at lunn.ch  Tue May 21 01:13:15 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 21 May 2013 07:13:15 +0200
Subject: [PATCH V3 10/10] ARM: Kirkwood: add DT support for Sheevaplug
 and Sheevaplug eSATA
In-Reply-To: <1369090911-1479-11-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
 <1369090911-1479-11-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130521051315.GK26249@lunn.ch>

On Tue, May 21, 2013 at 01:01:51AM +0200, Simon Baatz wrote:
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>  arch/arm/mach-kirkwood/Kconfig            |    7 +++++++
>  arch/arm/mach-kirkwood/Makefile           |    1 +
>  arch/arm/mach-kirkwood/board-dt.c         |    4 ++++
>  arch/arm/mach-kirkwood/board-sheevaplug.c |   27 +++++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h           |    5 +++++
>  5 files changed, 44 insertions(+)
>  create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c
> 
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index 7509a89..58518a2 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -296,6 +296,13 @@ config MACH_READYNAS_DT
>  	  Say 'Y' here if you want your kernel to support the
>  	  NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
>  
> +config MACH_SHEEVAPLUG_DT
> +	bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Marvell (eSATA) SheevaPlug (Flattened Device Tree).
> +
>  config MACH_TOPKICK_DT
>  	bool "USI Topkick (Flattened Device Tree)"
>  	select ARCH_KIRKWOOD_DT
> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
> index e1f3735..8846abf 100644
> --- a/arch/arm/mach-kirkwood/Makefile
> +++ b/arch/arm/mach-kirkwood/Makefile
> @@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
>  obj-$(CONFIG_MACH_NSA310_DT)		+= board-nsa310.o
>  obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)	+= board-openblocks_a6.o
>  obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
> +obj-$(CONFIG_MACH_SHEEVAPLUG_DT)	+= board-sheevaplug.o
>  obj-$(CONFIG_MACH_TOPKICK_DT)		+= board-usi_topkick.o
>  obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index e9647b8..a09dbac 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -112,6 +112,9 @@ static void __init kirkwood_dt_init(void)
>  	if (of_machine_is_compatible("globalscale,guruplug"))
>  		guruplug_dt_init();
>  
> +	if (of_machine_is_compatible("globalscale,sheevaplug"))
> +		sheevaplug_dt_init();
> +
>  	if (of_machine_is_compatible("dlink,dns-kirkwood"))
>  		dnskw_init();
>  
> @@ -165,6 +168,7 @@ static void __init kirkwood_dt_init(void)
>  static const char * const kirkwood_dt_board_compat[] = {
>  	"globalscale,dreamplug",
>  	"globalscale,guruplug",
> +	"globalscale,sheevaplug",
>  	"dlink,dns-320",
>  	"dlink,dns-325",
>  	"iom,iconnect",
> diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
> new file mode 100644
> index 0000000..fa38937
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-sheevaplug.c
> @@ -0,0 +1,27 @@
> +/*
> + * arch/arm/mach-kirkwood/board-sheevaplug.c
> + *
> + * Marvell Sheevaplug Reference Board Init for drivers not converted to
> + * flattened device tree yet.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/mv643xx_eth.h>
> +#include "common.h"
> +
> +static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
> +};
> +
> +void __init sheevaplug_dt_init(void)
> +{
> +	/*
> +	 * Basic setup. Needs to be called early.
> +	 */
> +	kirkwood_ge00_init(&sheevaplug_ge00_data);
> +}
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index 21da3b1..974442e 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -65,6 +65,11 @@ void guruplug_dt_init(void);
>  #else
>  static inline void guruplug_dt_init(void) {};
>  #endif
> +#ifdef CONFIG_MACH_SHEEVAPLUG_DT
> +void sheevaplug_dt_init(void);
> +#else
> +static inline void sheevaplug_dt_init(void) {};
> +#endif
>  #ifdef CONFIG_MACH_TS219_DT
>  void qnap_dt_ts219_init(void);
>  #else
> -- 
> 1.7.9.5
> 

Acked-by: Andrew Lunn <andrew at lunn.ch>


From shawn.guo at linaro.org  Tue May 21 01:43:25 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 21 May 2013 13:43:25 +0800
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369039742-10893-2-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <1369039742-10893-2-git-send-email-b32955@freescale.com>
Message-ID: <20130521054323.GE3080@S2101-09.ap.freescale.net>

On Mon, May 20, 2013 at 04:48:57PM +0800, Huang Shijie wrote:
> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  Documentation/devicetree/bindings/bus/imx-weim.txt |   69 +++++++++
>  drivers/bus/Kconfig                                |    9 ++
>  drivers/bus/Makefile                               |    1 +
>  drivers/bus/imx-weim.c                             |  145 ++++++++++++++++++++
>  4 files changed, 224 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
>  create mode 100644 drivers/bus/imx-weim.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
> new file mode 100644
> index 0000000..9913454
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
> @@ -0,0 +1,69 @@
> +Device tree bindings for i.MX Wireless External Interface Module (WEIM)
> +
> +The term ???wireless??? does not imply that the WEIM is literally an interface

"wireless"

> +without wires. It simply means that this module was originally designed for
> +wireless and mobile applications that use low-power technology.
> +
> +The actual devices are instantiated from the child nodes of a WEIM node.
> +But now we only have the NOR device.
> +
> +NOR flash connected to the WEIM (found on i.MX boards) are represented as
> +child nodes with a name of "nor".

I doubt that WEIM should care the particular device type connected on
it.

> +
> +Required properties:
> +
> + - compatible:		Should be set to "fsl, imx6q-weim"

Drop the space in middle of compatible string.

> + - reg:			A resource specifier for the register space
> +			(see the example below)
> + - interrupts:		the interrupt number, see the example below.
> + - clocks:		the clock, see the example below.
> + - #address-cells:	Must be set to 2 to allow memory address translation
> + - #size-cells:		Must be set to 1 to allow CS address passing
> + - ranges:		Must be set up to reflect the memory layout with four
> +			integer values for each chip-select line in use:
> +
> +			   <cs-number> 0 <physical address of mapping> <size>
> +
> +Timing properties for child nodes. All are mandatory, not optional.
> +
> + -weim-cs-index:	The CS index which the device is attaching on.

It seems we can find it out from "reg" property, so that we can save
this property?

> + -weim-cs-timing:	The timing array, contains 6 timing values for the
> +			weim-cs-index.

This is a vendor specific property, and should have a vendor (fsl)
perfix.  Also please put a space after the first "-" which acts as
a bullet symbol here.

> +
> +Example for an i.MX6q-sabreauto board:

You can write it as i.MX6Q SABRE Auto or imx6q-sabreauto.

> +	weim: weim at 021b8000 {
> +		compatible = "fsl,imx6q-weim";
> +		reg = <0x021b8000 0x4000>;
> +		interrupts = <0 14 0x04>;
> +		clocks = <&clks 196>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0x08000000 0x08000000>;
> +
> +		nor at 0,0 {
> +			compatible = "cfi-flash";
> +			reg = <0 0 0x02000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			bank-width = <2>;
> +
> +			weim-cs-index = <0>;
> +			weim-cs-timing = <0x00620081 0x00000001 0x1C022000
> +					0x0000C000 0x1404a38e 0x00000000>;
> +			partition at 0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x40000>;
> +			};
> +
> +			partition at 40000 {
> +				label = "U-Boot-ENV";
> +				reg = <0x40000 0x10000>;
> +				read-only;
> +			};
> +
> +			partition at 50000 {
> +				label = "Kernel";
> +				reg = <0x50000 0x3b0000>;
> +			};
> +		};
> +	};
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index b05ecab..0f997af 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -4,6 +4,15 @@
>  
>  menu "Bus devices"
>  
> +config IMX_WEIM
> +	tristate "Freescale EIM DRIVER"
> +	depends on ARCH_MXC && MTD_PHYSMAP_OF

I do not see how this driver depends on MTD_PHYSMAP_OF.

> +	help
> +	  Driver for i.MX6 WEIM controller.
> +	  The WEIM(Wireless External Interface Module) works like a bus.
> +	  You can attach many different devices on it, such as NOR, onenand.
> +	  But now, we only support the Parallel NOR.
> +
>  config MVEBU_MBUS
>  	bool
>  	depends on PLAT_ORION
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index 3c7b53c..436bbcc 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -2,6 +2,7 @@
>  # Makefile for the bus drivers.
>  #
>  
> +obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
>  obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
>  obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
>  
> diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
> new file mode 100644
> index 0000000..8bd9362
> --- /dev/null
> +++ b/drivers/bus/imx-weim.c
> @@ -0,0 +1,145 @@
> +/*
> + * EIM driver for Freescale's i.MX chips
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +
> +struct imx_weim {
> +	void __iomem *base;
> +	struct clk *clk;
> +};
> +
> +static const struct of_device_id weim_id_table[] = {
> +	{ .compatible = "fsl,imx6q-weim", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, weim_id_table);
> +
> +#define CS_TIMING_LEN 6
> +#define CS_REG_RANGE  0x18

Nit: put a blank line here.

> +/* Parse and set the timing for this device. */
> +static int weim_timing(struct platform_device *pdev, struct device_node *np)

Name the function weim_timing_setup for better?

> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +	u32 value[CS_TIMING_LEN];
> +	u32 cs_idx;
> +	int ret;
> +	int i;
> +
> +	ret = of_property_read_u32(np, "weim-cs-index", &cs_idx);
> +	if (ret)
> +		goto weim_parse_err;

Why not simply "return ret;"?

> +
> +	ret = of_property_read_u32_array(np, "weim-cs-timing",
> +					value, CS_TIMING_LEN);
> +	if (ret)
> +		goto weim_parse_err;

Ditto

> +
> +	/* set the timing for WEIM */
> +	for (i = 0; i < CS_TIMING_LEN; i++)
> +		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
> +	return 0;
> +
> +weim_parse_err:
> +	return ret;
> +}
> +
> +static int weim_parse_dt(struct platform_device *pdev)
> +{
> +	struct device_node *child;
> +	int ret;
> +
> +	/* We only support the Parallel NOR now. We may add more in future. */
> +	child = of_find_node_by_name(NULL, "nor");
> +	if (child) {
> +		ret = weim_timing(pdev, child);
> +		if (ret)
> +			goto parse_fail;
> +
> +		if (!of_platform_device_create(child, NULL, &pdev->dev)) {
> +			ret = -EINVAL;
> +			goto parse_fail;
> +		}
> +	}
> +	return 0;
> +
> +parse_fail:
> +	return ret;
> +}

I second Sascha's comments on this function.

> +
> +static int weim_probe(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim;
> +	struct resource *res;
> +	int ret = -EINVAL;
> +
> +	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
> +	if (!weim) {
> +		ret = -ENOMEM;
> +		goto weim_err;
> +	}
> +	platform_set_drvdata(pdev, weim);
> +
> +	/* get the resource */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		ret = -ENOENT;
> +		goto weim_err;
> +	}
> +
> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(weim->base)) {
> +		ret = PTR_ERR(weim->base);
> +		goto weim_err;
> +	}
> +
> +	/* get the clock */
> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(weim->clk))
> +		goto weim_err;
> +
> +	clk_prepare_enable(weim->clk);
> +
> +	/* parse the device node */
> +	ret = weim_parse_dt(pdev);
> +	if (ret) {
> +		clk_disable_unprepare(weim->clk);
> +		goto weim_err;
> +	}
> +
> +	dev_info(&pdev->dev, "WEIM driver registered.\n");
> +	return 0;
> +
> +weim_err:
> +	return ret;
> +}
> +
> +static int weim_remove(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(weim->clk);
> +	return 0;
> +}
> +
> +static struct platform_driver weim_driver = {
> +	.driver = {
> +		.name = "imx-weim",
> +		.of_match_table = weim_id_table,
> +	},
> +	.probe   = weim_probe,
> +	.remove  = weim_remove,
> +};
> +
> +module_platform_driver(weim_driver);
> +MODULE_AUTHOR("Freescale Inc.");

"Freescale Semiconductor, Inc."

Shawn

> +MODULE_DESCRIPTION("i.MX EIM Controller Driver");
> +MODULE_LICENSE("GPL");
> -- 
> 1.7.1
> 
> 



From shawn.guo at linaro.org  Tue May 21 01:49:33 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 21 May 2013 13:49:33 +0800
Subject: [PATCH 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between
 SPI and WEIM
In-Reply-To: <1369039742-10893-3-git-send-email-b32955@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <1369039742-10893-3-git-send-email-b32955@freescale.com>
Message-ID: <20130521054931.GF3080@S2101-09.ap.freescale.net>

On Mon, May 20, 2013 at 04:48:58PM +0800, Huang Shijie wrote:
> In the imx6q-sabreauto and imx6dl-sabreauto boards,
> the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
> it is used as a data pin for the WEIM NOR.
> 
> In order to fix the conflict, this patch removes the pin from the hog,
> and adds a new pinctrl item: pinctrl_ecspi1_2.
> 
> The SPI NOR selects this pinctrl_ecspi1_2 when it is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6dl-sabreauto.dts   |    9 ++++++++-
>  arch/arm/boot/dts/imx6q-sabreauto.dts    |    9 ++++++++-
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    2 +-
>  3 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
> index 60f3038..7695f70 100644
> --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
> +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
> @@ -25,7 +25,14 @@
>  			fsl,pins = <
>  				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
>  				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
> -				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
> +			>;
> +		};
> +	};
> +
> +	ecspi1 {
> +		pinctrl_ecspi1_2: ecspi1grp-2 {

The naming sounds like another ecspi1 pin groups beside
pinctrl_ecspi1_1, both of which should be ecspi1 pin groups defined by
SoC.  Please encode the board name in there to suggest this is a board
specific pin setup for ecspi1, something like pinctrl_ecspi1_sabreauto.

Shawn

> +			fsl,pins = <
> +				MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
>  			>;
>  		};
>  	};
> diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
> index 9fb3e99..67a3a6b 100644
> --- a/arch/arm/boot/dts/imx6q-sabreauto.dts
> +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
> @@ -29,7 +29,14 @@
>  			fsl,pins = <
>  				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
>  				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
> -				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
> +			>;
> +		};
> +	};
> +
> +	ecspi1 {
> +		pinctrl_ecspi1_2: ecspi1grp-2 {
> +			fsl,pins = <
> +				MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
>  			>;
>  		};
>  	};
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index d6baa51..eb293f5 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -20,7 +20,7 @@
>  	fsl,spi-num-chipselects = <1>;
>  	cs-gpios = <&gpio3 19 0>;
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_ecspi1_1>;
> +	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_2>;
>  	status = "disabled"; /* pin conflict with WEIM NOR */
>  
>  	flash: m25p80 at 0 {
> -- 
> 1.7.1
> 
> 



From b32955 at freescale.com  Tue May 21 01:53:51 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 21 May 2013 13:53:51 +0800
Subject: [PATCH 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between
 SPI and WEIM
In-Reply-To: <20130521054931.GF3080@S2101-09.ap.freescale.net>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <1369039742-10893-3-git-send-email-b32955@freescale.com>
 <20130521054931.GF3080@S2101-09.ap.freescale.net>
Message-ID: <519B0BEF.60505@freescale.com>

? 2013?05?21? 13:49, Shawn Guo ??:
> specific pin setup for ecspi1, something like pinctrl_ecspi1_sabreauto.
ok.

thanks
Huang Shijie



From shawn.guo at linaro.org  Tue May 21 02:01:47 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 21 May 2013 14:01:47 +0800
Subject: [PATCH] ARM i.MX6q: fix for ldb_di_sels
In-Reply-To: <1369054311-2519-1-git-send-email-jiada_wang@mentor.com>
References: <1369054311-2519-1-git-send-email-jiada_wang@mentor.com>
Message-ID: <20130521060145.GG3080@S2101-09.ap.freescale.net>

On Mon, May 20, 2013 at 09:51:51PM +0900, Jiada Wang wrote:
> As pll5_video_div has been introduced to represent the clock
> generated from post-divider for video.
> Instead of pll5_video, pll5_video_div should be proper root clock
> for ldb_di_sel.
> 
> Signed-off-by: Jiada Wang <jiada_wang at mentor.com>

Applied, thanks.



From neidhard.kim at lge.com  Tue May 21 02:02:29 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Tue, 21 May 2013 15:02:29 +0900
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
In-Reply-To: <519AD82A.6090809@wwwdotorg.org>
References: <519AD82A.6090809@wwwdotorg.org>
Message-ID: <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>

Stephen Warren reported the recent commit 78506f2 (add support for
extended FIFO-size of PL011-r1p5) breaks the serial port on the
BCM2835 ARM SoC.

A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
this compatibility issue, this patch overrides the HW UART periphid
register values with the actually compatible UART periphid 0x00241011
(r1p3 or r1p4).

Reported-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Jongsung Kim <neidhard.kim at lge.com>
---
 arch/arm/boot/dts/bcm2835.dtsi |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index f0052dc..1e12aef 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -44,6 +44,7 @@
 			reg = <0x7e201000 0x1000>;
 			interrupts = <2 25>;
 			clock-frequency = <3000000>;
+			arm,primecell-periphid = <0x00241011>;
 		};
 
 		gpio: gpio {
-- 
1.7.1



From olof at lixom.net  Tue May 21 02:07:13 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:07:13 -0700
Subject: [GIT PULL] OMAP PM cleanups for v3.10
In-Reply-To: <20130516153023.GR5600@atomide.com>
References: <87ehej1ena.fsf@linaro.org> <20130410181452.GG10155@atomide.com>
 <20130423175934.GA6728@quad.lixom.net> <87ppwrt43o.fsf@linaro.org>
 <20130516153023.GR5600@atomide.com>
Message-ID: <20130521060713.GA19627@quad.lixom.net>

On Thu, May 16, 2013 at 08:30:23AM -0700, Tony Lindgren wrote:
> * Kevin Hilman <khilman at linaro.org> [130516 07:08]:
> > Olof Johansson <olof at lixom.net> writes:
> > 
> > > On Wed, Apr 10, 2013 at 11:14:52AM -0700, Tony Lindgren wrote:
> > >> Hi,
> > >> 
> > >> Added Olof to cc, I suggest Olof pull this directly as we're starting
> > >> to run out of time.
> > >
> > > Hi,
> > >
> > > I'm terribly sorry for dropping this one on the floor, in spite of repeated
> > > pings from Tony. :(
> > >
> > > If it wasn't for the fact that we're pushing back on some of the other
> > > late submissions I'd be open to taking this, but to be fair it makes
> > > more sense to merge it right after -rc1. The changes don't look like
> > > they're truly critical for 3.10, and you should still be able to use
> > > this as a base for your 3.11 changes, so hopefully this doesn't cause
> > > too much trouble.
> > >
> > > So, please resend right after the merge window closes.
> > 
> > Pull request below.  It is unchanged and merges cleanly with v3.10-rc1.
> 
> I've pulled this into omap-for-v3.11/pm. Olof, you can also pull Kevin's
> branch now or later on along with other omap pull requests whichever you
> prefer.

I'll hold off until you've batched it with other things, just as easy for
everyone that way I think.

Thanks!

-Olof


From neidhard.kim at lge.com  Tue May 21 02:07:34 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Tue, 21 May 2013 15:07:34 +0900
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
In-Reply-To: <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
References: <519AD82A.6090809@wwwdotorg.org>
 <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
Message-ID: <008d01ce55e9$7c479510$74d6bf30$@lge.com>

Jongsung Kim <neidhard.kim at lge.com> :
> diff --git a/arch/arm/boot/dts/bcm2835.dtsi
b/arch/arm/boot/dts/bcm2835.dtsi
> index f0052dc..1e12aef 100644
> --- a/arch/arm/boot/dts/bcm2835.dtsi
> +++ b/arch/arm/boot/dts/bcm2835.dtsi
> @@ -44,6 +44,7 @@
>  			reg = <0x7e201000 0x1000>;
>  			interrupts = <2 25>;
>  			clock-frequency = <3000000>;
> +			arm,primecell-periphid = <0x00241011>;
>  		};
>  
>  		gpio: gpio {

Stephen, how do you think about this kind of approach instead?



From marc.zyngier at arm.com  Tue May 21 02:13:54 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 21 May 2013 08:13:54 +0200
Subject: [PATCH] arm64: kernel: compiling issue,
 need =?UTF-8?Q?=27EXPORT=5FSY?=
 =?UTF-8?Q?MBOL=5FGPL=28read=5Fcurrent=5Ftimer=29=27?=
In-Reply-To: <519AF2DC.2040200@asianux.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com>
Message-ID: <5bf8a8dd20ecd01c14f0ed9aa054f2df@localhost>

On Tue, 21 May 2013 12:06:52 +0800, Chen Gang <gang.chen at asianux.com>
wrote:
> On 05/20/2013 05:56 PM, Will Deacon wrote:
>> On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
>>> On Mon, 20 May 2013 14:48:05 +0800, Chen Gang <gang.chen at asianux.com>
>>> wrote:
>>>> Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with
>>>> allmodconfig.
>>>>
>>>> The related error:
>>>>   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
>>>>   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
>>>>   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
>>>>   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>>>>
>>>>
>>>> Signed-off-by: Chen Gang <gang.chen at asianux.com>
>>>> ---
>>>>  arch/arm64/kernel/time.c |    1 +
>>>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
>>>> index a551f88..7fcba80 100644
>>>> --- a/arch/arm64/kernel/time.c
>>>> +++ b/arch/arm64/kernel/time.c
>>>> @@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
>>>>  	*timer_value = arch_timer_read_counter();
>>>>  	return 0;
>>>>  }
>>>> +EXPORT_SYMBOL_GPL(read_current_timer);
>>>>  
>>>>  void __init time_init(void)
>>>>  {
>>>
>>> While this solves the problem, I'm not sure this is the best fix. The
>>> real
>>> issue is with get_cycles, which is a macro around read_current_timer.
>>>
>>> AArch32 exports it because of the number of timer implementations. On
>>> arm64, we should be able to just return CNTVCT_EL0.
>>>
>>> Catalin, Will, what do you think?
>> 
>> Should be ok once the arch timer driver has moved exclusively to
virtual
>> time. I'm also not sure we even need to implement read_current_timer()
--
>> it's only used for delay-loop calibration, which we don't need for the
>> arch timer.
>> 
> 
> For whether we need implement read_current_timer():
> 
>   many platforms have implemented it (openrisc, arm, sparc, hexagon,
>   avr32, x86).
>   it is called by init/calibrate.c when 'ARCH_HAS_READ_CURRENT_TIMER' is
>   defined.
>   since arm64 can implement it, better to provide it as an architect
>   features to let outside use.

Nobody disputes the interest of read_current_timer.

> For the implementation of read_current_timer():
> 
>   it has to face various configurations
>     (e.g. CONFIG_ARM_ARCH_TIMER, arch_timer_read_zero,
>     arch_counter_get_cntvct, arch_counter_get_cntpct)
>   so better still use variable instead of.
>     (excuse me, I do not know what is 'CNTVCT_EL0', is it like a
constant
>     number ?)

Architected timer is mandatory on arm64, so we can always rely on it it be
present. CNTVCT_EL0 is the system register accessing the Virtual Counter,
which is basically what read_current_timer() returns.

> For the implementation of get_cycles()
> 
>   if read_current_timer() is provided,
>   better to let get_cycles() to call it, instead of implement once
again.

There is certainly some value in reusing existing code, but in this
particular case we can simply inline two instructions (isb + mrs
cntvct_el0), and I'm not even completely sure about the isb.

        M.
-- 
Fast, cheap, reliable. Pick two.


From linux at prisktech.co.nz  Tue May 21 02:16:21 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Tue, 21 May 2013 18:16:21 +1200
Subject: [PATCH] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs
In-Reply-To: <1368350634-12654-1-git-send-email-linux@prisktech.co.nz>
References: <1368350634-12654-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <519B1135.4060509@prisktech.co.nz>

On 12/05/13 21:23, Tony Prisk wrote:
> This patch adds support for the I2C bus controllers found on Wondermedia
> 8xxx-series SoCs. Only master-mode is supported.
>
> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
> ---
>   .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
>   MAINTAINERS                                        |    1 +
>   drivers/i2c/busses/Kconfig                         |   10 +
>   drivers/i2c/busses/Makefile                        |    1 +
>   drivers/i2c/busses/i2c-wmt.c                       |  488 ++++++++++++++++++++
>   5 files changed, 524 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
>   create mode 100644 drivers/i2c/busses/i2c-wmt.c
>
>
This patch seems to have stalled. Any news?

Regards
Tony Prisk


From olof at lixom.net  Tue May 21 02:19:06 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:19:06 -0700
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 1)
In-Reply-To: <20130513170325.GT31290@titan.lakedaemon.net>
References: <20130513170325.GT31290@titan.lakedaemon.net>
Message-ID: <20130521061906.GB19627@quad.lixom.net>

On Mon, May 13, 2013 at 01:03:25PM -0400, Jason Cooper wrote:
> 
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-1
> 
> for you to fetch changes up to 00ed4a0bd964555fe9276f2299564c384d50ae7d:
> 
>   ARM: mvebu: Add a ranges entry to translate devbus childs (2013-05-13 16:23:47 +0000)

Children? :)

Pulled, thanks.


-Olof


From olof at lixom.net  Tue May 21 02:25:27 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:25:27 -0700
Subject: [GIT PULL] at91: fixes for 3.10 #1
In-Reply-To: <1368614747-1737-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368614747-1737-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20130521062527.GD19627@quad.lixom.net>

On Wed, May 15, 2013 at 12:45:47PM +0200, Nicolas Ferre wrote:
> Arnd, Olof,
> 
> This is the first AT91 fixes pull-request for 3.10-rc.
> 
> Thanks, best regards,
> 
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/at91linux/linux-at91.git tags/at91-fixes

Pulled, thanks.


-Olof


From davem at davemloft.net  Tue May 21 02:26:19 2013
From: davem at davemloft.net (David Miller)
Date: Mon, 20 May 2013 23:26:19 -0700 (PDT)
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
Message-ID: <20130520.232619.964940909999914694.davem@davemloft.net>

From: Libo Chen <libo.chen at huawei.com>
Date: Tue, 21 May 2013 10:42:00 +0800

> I find a lot of mistakes using struct platform_driver without owner.
> So I pick up some of them including usb and net modules

Instead of doing it this way, which is obviously error prone and
easy to forget, make platform_driver_register() be a macro which
sets the module owner field then calls the real __platform_driver_register().


From moinejf at free.fr  Tue May 21 02:30:31 2013
From: moinejf at free.fr (Jean-Francois Moine)
Date: Tue, 21 May 2013 08:30:31 +0200
Subject: [RFC 0/8] rmk's Dove DRM/TDA19988 Cubox driver
In-Reply-To: <CADnq5_O8nLi1=HOrXO0AeQuX17tGj05fhao4mmauzZ5h8Ciyaw@mail.gmail.com>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <20130517133345.7c1368f5@armhf>
 <20130517120115.GF18614@n2100.arm.linux.org.uk>
 <20130517194023.0c385ea0@armhf>
 <20130519085920.GO18614@n2100.arm.linux.org.uk>
 <CADnq5_Pajy4jxLdd9QGBrUooWYFjfQRQgdbvbu9UDE8-7Tmm8g@mail.gmail.com>
 <20130520201536.GY18614@n2100.arm.linux.org.uk>
 <CADnq5_O8nLi1=HOrXO0AeQuX17tGj05fhao4mmauzZ5h8Ciyaw@mail.gmail.com>
Message-ID: <20130521083031.48f1e43e@armhf>

On Mon, 20 May 2013 16:23:33 -0400
Alex Deucher <alexdeucher at gmail.com> wrote:

> > Note also that the generic DRM KMS code assumes cursor support at
> > 64x64, and there's no generic way for a driver at present (that I know
> > of) to inform it of anything different.  
> 
> It shouldn't be too hard to add a new cap for querying the cursor size
> to the drm cap interface.

There was already a patch request for that, but the functions were
surely useless.

Otherwise, you may do a search on "largest cursor:" (xdpyinfo output).
The results are surprising..

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/


From olof at lixom.net  Tue May 21 02:31:39 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:31:39 -0700
Subject: [PATCH] ARM: vt8500: Add missing NULL terminator in dt_compat
In-Reply-To: <5195EA34.7000409@prisktech.co.nz>
References: <1368776657-23035-1-git-send-email-srinivas.kandagatla@st.com>
 <5195EA34.7000409@prisktech.co.nz>
Message-ID: <20130521063139.GA20453@quad.lixom.net>

On Fri, May 17, 2013 at 08:28:36PM +1200, Tony Prisk wrote:
> On 17/05/13 19:44, Srinivas KANDAGATLA wrote:
> >From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> >
> >When I tried booting a stih415 Dual core A9 with multi_v7_defconfig, it
> >failed to boot. The issues seems to be changing by enabling or disabling
> >VT8550 platform. Having a quick look at dt_compat list, it seems to miss
> >a NULL terminator, which means of_flat_dt_match will compat check will
> >cross the boundary of dt_compat and fault at some point , which is what
> >was happening in my case.
> >
> >Without this patch if we try to boot multi_v7_defconfig you might notice
> >that some of the platforms might fault if they fall after vt8500 in
> >machine-desc list. Other platforms which fall before vt8500 in mdesc list
> >will not fault.
> >
> >Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> >---
> >  arch/arm/mach-vt8500/vt8500.c |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> >diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
> >index 1dd281e..f5c33df 100644
> >--- a/arch/arm/mach-vt8500/vt8500.c
> >+++ b/arch/arm/mach-vt8500/vt8500.c
> >@@ -173,6 +173,7 @@ static const char * const vt8500_dt_compat[] = {
> >  	"wm,wm8505",
> >  	"wm,wm8750",
> >  	"wm,wm8850",
> >+	NULL
> >  };
> >  DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
> My bad. Thanks for the fix.
> 
> Acked-by: Tony Prisk <linux at prisktech.co.nz>
> 
> Arnd, Olof: Can you apply this directly please.

Done.

Thanks,

-Olof


From olof at lixom.net  Tue May 21 02:37:32 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:37:32 -0700
Subject: [GIT PULL] omap fixes for v3.10-rc1
In-Reply-To: <20130517192515.GC5600@atomide.com>
References: <20130517192515.GC5600@atomide.com>
Message-ID: <20130521063732.GD20453@quad.lixom.net>

On Fri, May 17, 2013 at 12:25:16PM -0700, Tony Lindgren wrote:
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10-rc1/fixes

Well, it's for -rc3 now but it can never have been for -rc1 since that's
what the branch is base on. :-)


IOW: Pulled, thanks!


-Olof


From olof at lixom.net  Tue May 21 02:40:34 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:40:34 -0700
Subject: [GIT PULL] Samsung fixes-2 for v3.10
In-Reply-To: <519A5933.3040005@samsung.com>
References: <519A5933.3040005@samsung.com>
Message-ID: <20130521064034.GE20453@quad.lixom.net>

On Tue, May 21, 2013 at 02:11:15AM +0900, Kukjin Kim wrote:
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 

> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> tags/samsung-fixes-2

What happened to the 4210 rev0 regression fixes from Tomasz? I would
have expected them in this batch?

Might as well hold off this one until that is reviewed and ready, since
it's silly to keep pulling one-patch branches. At least if that's happening
this week.


-Olof


From thomas.petazzoni at free-electrons.com  Tue May 21 02:41:08 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 08:41:08 +0200
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <20130520.232619.964940909999914694.davem@davemloft.net>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
Message-ID: <20130521084108.1a585f32@skate>

Dear David Miller,

On Mon, 20 May 2013 23:26:19 -0700 (PDT), David Miller wrote:
> From: Libo Chen <libo.chen at huawei.com>
> Date: Tue, 21 May 2013 10:42:00 +0800
> 
> > I find a lot of mistakes using struct platform_driver without owner.
> > So I pick up some of them including usb and net modules
> 
> Instead of doing it this way, which is obviously error prone and
> easy to forget, make platform_driver_register() be a macro which
> sets the module owner field then calls the real
> __platform_driver_register().

Or, maybe make the existing module_platform_driver() macro do this?

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From olof at lixom.net  Tue May 21 02:44:13 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:44:13 -0700
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 2)
In-Reply-To: <20130520195135.GH31290@titan.lakedaemon.net>
References: <20130520195135.GH31290@titan.lakedaemon.net>
Message-ID: <20130521064413.GF20453@quad.lixom.net>

On Mon, May 20, 2013 at 03:51:35PM -0400, Jason Cooper wrote:
> 
> The following changes since commit 00ed4a0bd964555fe9276f2299564c384d50ae7d:
> 
>   ARM: mvebu: Add a ranges entry to translate devbus childs (2013-05-13 16:23:47 +0000)
> 
> are available in the git repository at:
> 
>   git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-2
> 
> for you to fetch changes up to 489e138eec96f529c5e8d4cd3ea45882ecdbf5ca:
> 
>   ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node (2013-05-20 17:44:54 +0000)

Pulled, thanks.

> 
> ----------------------------------------------------------------
> mvebu fixes for v3.10 (round 2)
> 
>  - mvebu (and orion SoCs)
>     - remove init_dma_coherent_pool_size()
> 
>  - mvebu
>     - fix ranges DT property

We've seen two of these now. Can someone please make a sweep and make sure
there are no more of these pending?


Thanks,

-Olof


From olof at lixom.net  Tue May 21 02:47:02 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:47:02 -0700
Subject: [GIT PULL] ARM: imx: fixes for 3.10
In-Reply-To: <20130514084430.GC16250@S2101-09.ap.freescale.net>
References: <20130514084430.GC16250@S2101-09.ap.freescale.net>
Message-ID: <20130521064702.GG20453@quad.lixom.net>

On Tue, May 14, 2013 at 04:44:32PM +0800, Shawn Guo wrote:
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/shawnguo/linux-2.6.git tags/imx-fixes-3.10
> 
> for you to fetch changes up to de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0:
> 
>   ARM: imx: fix typo in gpu3d_shader_sels (2013-05-12 21:39:51 +0800)

Pulled, thanks!


-Olof


From olof at lixom.net  Tue May 21 02:48:58 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:48:58 -0700
Subject: [GIT PULL] ux500 fixes for v3.10-rc1+
In-Reply-To: <CACRpkdY2Pd9o+PMmabKs5Zj56GRsGtva8eQENgu8w-VjZy2hHw@mail.gmail.com>
References: <CACRpkdY2Pd9o+PMmabKs5Zj56GRsGtva8eQENgu8w-VjZy2hHw@mail.gmail.com>
Message-ID: <20130521064858.GH20453@quad.lixom.net>

On Wed, May 15, 2013 at 06:17:21PM +0200, Linus Walleij wrote:
> Hi ARM SoC folks,
> 
> please pull the following ux500 fixes for the v3.10-rc series.
> Brief info in the signed tag.
> 
> Yours,
> Linus Walleij
> 
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
> tags/ux500-arm-soc-v3.10-fixes

Pulled, thanks.

> Emilio L??pez (1):

Broken UTF-8 cut-and-paste? Looks alright in the git contents though.


-Olof


From olof at lixom.net  Tue May 21 02:50:03 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:50:03 -0700
Subject: [PATCH] ARM: nomadik: fix IRQ assignment for SMC ethernet
In-Reply-To: <1368917259-7883-1-git-send-email-linus.walleij@linaro.org>
References: <1368917259-7883-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <20130521065003.GI20453@quad.lixom.net>

On Sun, May 19, 2013 at 12:47:39AM +0200, Linus Walleij wrote:
> The assignment of IRQ for the SMC91x ethernet adapter had two
> problems making it non-working:
> 
> - It was not put into the ethernet device node. Let's do this
>   by using the board-specific overlay, so we can make other
>   overlays on other Nomadik boards.
> 
> - The IRQ number was actually completely wrong, this was the
>   number for NHK8815, not S8815.
> 
> After this ethernet starts working on the USB S8815.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> ARM SoC folks: I would appreciate if you apply this patch
> directly for v3.10 fixes.

Done.

-Olof


From olof at lixom.net  Tue May 21 02:51:13 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 20 May 2013 23:51:13 -0700
Subject: [PATCH] ARM: tegra: defconfig fixes
In-Reply-To: <1369076839-31787-1-git-send-email-swarren@wwwdotorg.org>
References: <1369076839-31787-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20130521065113.GJ20453@quad.lixom.net>

On Mon, May 20, 2013 at 01:07:19PM -0600, Stephen Warren wrote:
> From: Alexandre Courbot <gnurou at gmail.com>
> 
> The AK8975 Kconfig option was renamed during the 3.10 merge window.
> Adjust tegra_defconfig to enable the new name, so it's not missing
> useful features.
> 
> Tegra DRM support used to be enabled in the default Tegra configuration,
> but it now depends on CONFIG_TEGRA_HOST1X which is disabled by default.
> Enable CONFIG_TEGRA_HOST1X so that DRM support is compiled in again.
> 
> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
> [swarren, squashed Alex's and my changes together]
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
> Olof, Arnd,
> 
> Can this be taken into 3.10? Hopefully Linus won't mind defconfig changes
> sneaking in now. If not, let me know, and I'll for it into Tegra's
> for-3.11/dt branch instead. Thanks.

Since people actually use the defconfigs it does make sense to keep them
working and regression-free.

I think we'll be fine with a rare occurrance of it. We'll find out. :)



-Olof


From geert at linux-m68k.org  Tue May 21 02:57:36 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Tue, 21 May 2013 08:57:36 +0200
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <519AE6D7.1090401@asianux.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
Message-ID: <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>

On Tue, May 21, 2013 at 5:15 AM, Chen Gang <gang.chen at asianux.com> wrote:
>> I think it would be better if we added a something like
>> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
>> like x86 can then select the former, and we can remove the long list of
>> architectures from the current option.
>
> I guess your meaning is:
>
>   under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
>   So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.
>
> Is it correct ?

No, you missed "and we can remove the long list of architectures from the
current option".

> If so, I recommend to add depend item for VGA_CONSOLE directly:

I strongly support CONFIG_HAVE_VGA_CONSOLE.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From ulf.hansson at linaro.org  Tue May 21 03:00:09 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Tue, 21 May 2013 09:00:09 +0200
Subject: [PATCH V3 01/10] mmc: return mmc_of_parse() errors to caller
In-Reply-To: <1369090911-1479-2-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
 <1369090911-1479-2-git-send-email-gmbnomis@gmail.com>
Message-ID: <CAPDyKFoE-_Kpn_FBmrePEGF84jwSADC+=6ibBmA_ePVg7B4z9Q@mail.gmail.com>

On 21 May 2013 01:01, Simon Baatz <gmbnomis at gmail.com> wrote:
> In addition to just logging errors encountered during DT parsing or
> allocating GPIO slots for CD/WP, mmc_of_parse() now returns with an error.
>
> In particular, this is needed if the GPIO allocation may return
> EPROBE_DEFER.
>
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> ---
>
> changes in V3:
> - Handle EPROBE_DEFER case
>
>  drivers/mmc/core/host.c  |   30 +++++++++++++++++++++++++-----
>  include/linux/mmc/host.h |    2 +-
>  2 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index 2a3593d..89f5849 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -306,7 +306,7 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
>   * parse the properties and set respective generic mmc-host flags and
>   * parameters.
>   */
> -void mmc_of_parse(struct mmc_host *host)
> +int mmc_of_parse(struct mmc_host *host)
>  {
>         struct device_node *np;
>         u32 bus_width;
> @@ -315,7 +315,7 @@ void mmc_of_parse(struct mmc_host *host)
>         int len, ret, gpio;
>
>         if (!host->parent || !host->parent->of_node)
> -               return;
> +               return 0;
>
>         np = host->parent->of_node;
>
> @@ -338,6 +338,7 @@ void mmc_of_parse(struct mmc_host *host)
>         default:
>                 dev_err(host->parent,
>                         "Invalid \"bus-width\" value %ud!\n", bus_width);
> +               return -EINVAL;
>         }
>
>         /* f_max is obtained from the optional "max-frequency" property */
> @@ -367,18 +368,22 @@ void mmc_of_parse(struct mmc_host *host)
>                         host->caps |= MMC_CAP_NEEDS_POLL;
>
>                 gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags);
> +               if (gpio == -EPROBE_DEFER)
> +                       return gpio;
>                 if (gpio_is_valid(gpio)) {
>                         if (!(flags & OF_GPIO_ACTIVE_LOW))
>                                 gpio_inv_cd = true;
>
>                         ret = mmc_gpio_request_cd(host, gpio);
> -                       if (ret < 0)
> +                       if (ret < 0) {
>                                 dev_err(host->parent,
>                                         "Failed to request CD GPIO #%d: %d!\n",
>                                         gpio, ret);
> -                       else
> +                               return ret;
> +                       } else {
>                                 dev_info(host->parent, "Got CD GPIO #%d.\n",
>                                          gpio);
> +                       }
>                 }
>
>                 if (explicit_inv_cd ^ gpio_inv_cd)
> @@ -389,14 +394,23 @@ void mmc_of_parse(struct mmc_host *host)
>         explicit_inv_wp = of_property_read_bool(np, "wp-inverted");
>
>         gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags);
> +       if (gpio == -EPROBE_DEFER) {
> +               ret = -EPROBE_DEFER;
> +               goto out;
> +       }
>         if (gpio_is_valid(gpio)) {
>                 if (!(flags & OF_GPIO_ACTIVE_LOW))
>                         gpio_inv_wp = true;
>
>                 ret = mmc_gpio_request_ro(host, gpio);
> -               if (ret < 0)
> +               if (ret < 0) {
>                         dev_err(host->parent,
>                                 "Failed to request WP GPIO: %d!\n", ret);
> +                       goto out;
> +               } else {
> +                               dev_info(host->parent, "Got WP GPIO #%d.\n",
> +                                        gpio);
> +               }
>         }
>         if (explicit_inv_wp ^ gpio_inv_wp)
>                 host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
> @@ -413,6 +427,12 @@ void mmc_of_parse(struct mmc_host *host)
>                 host->pm_caps |= MMC_PM_KEEP_POWER;
>         if (of_find_property(np, "enable-sdio-wakeup", &len))
>                 host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
> +
> +       return 0;
> +
> +out:
> +       mmc_gpio_free_cd(host);
> +       return ret;
>  }
>
>  EXPORT_SYMBOL(mmc_of_parse);
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index e326ae2..c8c4fbc 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -369,7 +369,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *);
>  int mmc_add_host(struct mmc_host *);
>  void mmc_remove_host(struct mmc_host *);
>  void mmc_free_host(struct mmc_host *);
> -void mmc_of_parse(struct mmc_host *host);
> +int mmc_of_parse(struct mmc_host *host);
>
>  static inline void *mmc_priv(struct mmc_host *host)
>  {
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Reviewed-by: Ulf Hansson <ulf.hansson at linaro.org>


From inki.dae at samsung.com  Tue May 21 03:03:06 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 21 May 2013 16:03:06 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <20130520213033.GW12292@phenom.ffwll.local>
References: <028a01ce4fd4$5ec6f000$1c54d000$%dae@samsung.com>
 <CAF6AEGvWazezZdLDn5=H8wNQdQSWV=EmqE1a4wh7QwrT_h6vKQ@mail.gmail.com>
 <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
Message-ID: <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>



> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Tuesday, May 21, 2013 6:31 AM
> To: Inki Dae
> Cc: Rob Clark; linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham;
> YoungJun Cho; linux-arm-kernel at lists.infradead.org; linux-
> media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Mon, May 20, 2013 at 11:13:04PM +0200, Daniel Vetter wrote:
> > On Sat, May 18, 2013 at 03:47:43PM +0900, Inki Dae wrote:
> > > 2013/5/15 Rob Clark <robdclark at gmail.com>
> > >
> > > > On Wed, May 15, 2013 at 1:19 AM, Inki Dae <inki.dae at samsung.com>
> wrote:
> > > > >
> > > > >
> > > > >> -----Original Message-----
> > > > >> From: Rob Clark [mailto:robdclark at gmail.com]
> > > > >> Sent: Tuesday, May 14, 2013 10:39 PM
> > > > >> To: Inki Dae
> > > > >> Cc: linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham;
> YoungJun
> > > > >> Cho; linux-arm-kernel at lists.infradead.org; linux-
> media at vger.kernel.org
> > > > >> Subject: Re: Introduce a new helper framework for buffer
> synchronization
> > > > >>
> > > > >> On Mon, May 13, 2013 at 10:52 PM, Inki Dae <inki.dae at samsung.com>
> > > > wrote:
> > > > >> >> well, for cache management, I think it is a better idea.. I
> didn't
> > > > >> >> really catch that this was the motivation from the initial
> patch, but
> > > > >> >> maybe I read it too quickly.  But cache can be decoupled from
> > > > >> >> synchronization, because CPU access is not asynchronous.  For
> > > > >> >> userspace/CPU access to buffer, you should:
> > > > >> >>
> > > > >> >>   1) wait for buffer
> > > > >> >>   2) prepare-access
> > > > >> >>   3)  ... do whatever cpu access to buffer ...
> > > > >> >>   4) finish-access
> > > > >> >>   5) submit buffer for new dma-operation
> > > > >> >>
> > > > >> >
> > > > >> >
> > > > >> > For data flow from CPU to DMA device,
> > > > >> > 1) wait for buffer
> > > > >> > 2) prepare-access (dma_buf_begin_cpu_access)
> > > > >> > 3) cpu access to buffer
> > > > >> >
> > > > >> >
> > > > >> > For data flow from DMA device to CPU
> > > > >> > 1) wait for buffer
> > > > >>
> > > > >> Right, but CPU access isn't asynchronous (from the point of view
> of
> > > > >> the CPU), so there isn't really any wait step at this point.  And
> if
> > > > >> you do want the CPU to be able to signal a fence from userspace
> for
> > > > >> some reason, you probably what something file/fd based so the
> > > > >> refcnting/cleanup when process dies doesn't leave some pending
> DMA
> > > > >> action wedged.  But I don't really see the point of that
> complexity
> > > > >> when the CPU access isn't asynchronous in the first place.
> > > > >>
> > > > >
> > > > > There was my missing comments, please see the below sequence.
> > > > >
> > > > > For data flow from CPU to DMA device and then from DMA device to
> CPU,
> > > > > 1) wait for buffer <- at user side - ioctl(fd,
> DMA_BUF_GET_FENCE, ...)
> > > > >         - including prepare-access (dma_buf_begin_cpu_access)
> > > > > 2) cpu access to buffer
> > > > > 3) wait for buffer <- at device driver
> > > > >         - but CPU is already accessing the buffer so blocked.
> > > > > 4) signal <- at user side - ioctl(fd, DMA_BUF_PUT_FENCE, ...)
> > > > > 5) the thread, blocked at 3), is waked up by 4).
> > > > >         - and then finish-access (dma_buf_end_cpu_access)
> > > >
> > > > right, I understand you can have background threads, etc, in
> > > > userspace.  But there are already plenty of synchronization
> primitives
> > > > that can be used for cpu->cpu synchronization, either within the
> same
> > > > process or between multiple processes.  For cpu access, even if it
> is
> > > > handled by background threads/processes, I think it is better to use
> > > > the traditional pthreads or unix synchronization primitives.  They
> > > > have existed forever, they are well tested, and they work.
> > > >
> > > > So while it seems nice and orthogonal/clean to couple cache and
> > > > synchronization and handle dma->cpu and cpu->cpu and cpu->dma in the
> > > > same generic way, but I think in practice we have to make things
> more
> > > > complex than they otherwise need to be to do this.  Otherwise I
> think
> > > > we'll be having problems with badly behaved or crashing userspace.
> > > >
> > > >
> > > Right, this is very important. I think it's not esay to solve this
> > > issue. Aand at least for ARM based embedded system, such feature is
> useful
> > > to us; coupling cache operation and buffer synchronization. I'd like
> to
> > > collect other opinions and advices to solve this issue.
> >
> > Maybe we have a bit a misunderstanding here. The kernel really should
> take
> > care of sync and cache coherency, and I agree that with the current
> > dma_buf code (and the proposed fences) that part is still a bit hazy.
> But
> > the kernel should not allow userspace to block access to a buffer until
> > userspace is done. It should only sync with any oustanding fences and
> > flush buffers before that userspace access happens.
> >
> > Then the kernel would again flush caches on the next dma access (which
> > hopefully is only started once userspace completed access). Atm this
> isn't
> > possible in an efficient way since the dma_buf api only exposes
> map/unmap
> > attachment and not a function to just sync an existing mapping like
> > dma_sync_single_for_device. I guess we should add a
> > dma_buf_sync_attachment interface for that - we already have range-based
> > cpu sync support with the begin/end_cpu_access interfaces.
> 
> I think my mail here was a bit unclear, so let me try to rephrase.
> Re-reading through part of this discussion I think you raise some good
> shortcomings of the current dma_buf interfaces and the proposed fence
> patches. But I think we should address the individual pieces bit-by-bit.
> On a quick survey I see a few parts to what you're trying to solve:
> 
> - More efficient cache coherency management. I think we already have all
>   required interfaces for efficient cpu-side access with
>   begin/end_cpu_access. So I think we only need a device-side dma sync
>   mechanism to be able to flush cpu caches after userspace/cpu access has
>   completed (before the next dma op).
> 
> - More efficient mmap handling. The current dma_buf mmap support is
>   explicitly designed as something simply, but probably dead-slow for
>   last-resort fallback ops. I'm not sure whether we should fix this up and
>   extend with special ioctls. But the current coherency interface should
>   be good enough for you to write an efficient private mmap implementation
>   for exynos drm.

I agree with you.

> 
> - Integration of fence syncing into dma_buf. Imo we should have a
>   per-attachment mode which decides whether map/unmap (and the new sync)
>   should wait for fences or whether the driver takes care of syncing
>   through the new fence framework itself (for direct hw sync).

I think it's a good idea to have per-attachment mode for buffer sync. But
I'd like to say we make sure what is the purpose of map
(dma_buf_map_attachment)first. This interface is used to get a sgt;
containing pages to physical memory region, and map that region with
device's iommu table. The important thing is that this interface is called
just one time when user wants to share an allocated buffer with dma. But cpu
will try to access the buffer every time as long as it wants. Therefore, we
need cache control every time cpu and dma access the shared buffer: cache
clean when cpu goes to dma and cache invalidate when dma goes to cpu. That
is why I added new interfaces, DMA_BUF_GET_FENCE and DMA_BUF_PUT_FENCE, to
dma buf framework. Of course, Those are ugly so we need a better way: I just
wanted to show you that in such way, we can synchronize the shared buffer
between cpu and dma. By any chance, is there any way that kernel can be
aware of when cpu accesses the shared buffer or is there any point I didn't
catch up?

>   Imo cpu access should also have such a flag. I guess in both cases we
should
>   sync by default.
> 
> - cpu/cpu sync additions to dma_buf. Like I've said, I'm not sold at all

I think we should concentrate on cpu and dma sync. 

>   on this idea. I think it would be best if we try to fix up all the other
>   current shortcomings first though and then take a fresh look at this
>   issue here.

Right, agree.

> 
> Have I missed or misunderstood something?
> 

Your comments are very useful to me. Thanks again.

In Linux kernel, especially embedded system, we had tried to implement
generic interfaces for buffer management; how to allocate a buffer and how
to share a buffer. As a result, now we have CMA (Contiguous Memory
Allocator) for buffer allocation, and we have DMA-BUF for buffer sharing
between cpu and dma. And then how to synchronize a buffer between cpu and
dma? I think now it's best time to discuss buffer synchronization mechanism,
and that is very natural.

Please give me more comments and advices if there is my missing or
misunderstanding point.

Thanks,
Inki Dae

> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



From davem at davemloft.net  Tue May 21 03:13:15 2013
From: davem at davemloft.net (David Miller)
Date: Tue, 21 May 2013 00:13:15 -0700 (PDT)
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <20130521084108.1a585f32@skate>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate>
Message-ID: <20130521.001315.148105250495357251.davem@davemloft.net>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Date: Tue, 21 May 2013 08:41:08 +0200

> Dear David Miller,
> 
> On Mon, 20 May 2013 23:26:19 -0700 (PDT), David Miller wrote:
>> From: Libo Chen <libo.chen at huawei.com>
>> Date: Tue, 21 May 2013 10:42:00 +0800
>> 
>> > I find a lot of mistakes using struct platform_driver without owner.
>> > So I pick up some of them including usb and net modules
>> 
>> Instead of doing it this way, which is obviously error prone and
>> easy to forget, make platform_driver_register() be a macro which
>> sets the module owner field then calls the real
>> __platform_driver_register().
> 
> Or, maybe make the existing module_platform_driver() macro do this?

Even better.


From hansverk at cisco.com  Tue May 21 03:38:42 2013
From: hansverk at cisco.com (Hans Verkuil)
Date: Tue, 21 May 2013 09:38:42 +0200
Subject: [PATCH] Finally eradicate CONFIG_HOTPLUG
In-Reply-To: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
References: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
Message-ID: <201305210938.43064.hansverk@cisco.com>

On Tue 21 May 2013 05:49:35 Stephen Rothwell wrote:
> Ever since commit 45f035ab9b8f ("CONFIG_HOTPLUG should be always on"),
> it has been basically impossible to build a kernel with CONFIG_HOTPLUG
> turned off.  Remove all the remaining references to it.
> 
> Cc: linux-arch at vger.kernel.org
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Doug Thompson <dougthompson at xmission.com>
> Cc: linux-edac at vger.kernel.org
> Cc: Bjorn Helgaas <bhelgaas at google.com>
> Cc: linux-pci at vger.kernel.org
> Cc: linux-pcmcia at lists.infradead.org
> Cc: Hans Verkuil <hans.verkuil at cisco.com>
> Cc: Steven Whitehouse <swhiteho at redhat.com>
> Cc: cluster-devel at redhat.com
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Pavel Machek <pavel at ucw.cz>
> Cc: "Rafael J. Wysocki" <rjw at sisk.pl>
> Cc: linux-pm at vger.kernel.org
> Cc: Andrew Morton <akpm at linux-foundation.org>
> Cc: linux-mm at kvack.org
> Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au>

For drivers/staging/media/go7007/go7007.txt:

Acked-by: Hans Verkuil <hans.verkuil at cisco.com>

Regards,

	Hans


From daniel at ffwll.ch  Tue May 21 03:44:41 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Tue, 21 May 2013 09:44:41 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
Message-ID: <20130521074441.GZ12292@phenom.ffwll.local>

On Tue, May 21, 2013 at 04:03:06PM +0900, Inki Dae wrote:
> > - Integration of fence syncing into dma_buf. Imo we should have a
> >   per-attachment mode which decides whether map/unmap (and the new sync)
> >   should wait for fences or whether the driver takes care of syncing
> >   through the new fence framework itself (for direct hw sync).
> 
> I think it's a good idea to have per-attachment mode for buffer sync. But
> I'd like to say we make sure what is the purpose of map
> (dma_buf_map_attachment)first. This interface is used to get a sgt;
> containing pages to physical memory region, and map that region with
> device's iommu table. The important thing is that this interface is called
> just one time when user wants to share an allocated buffer with dma. But cpu
> will try to access the buffer every time as long as it wants. Therefore, we
> need cache control every time cpu and dma access the shared buffer: cache
> clean when cpu goes to dma and cache invalidate when dma goes to cpu. That
> is why I added new interfaces, DMA_BUF_GET_FENCE and DMA_BUF_PUT_FENCE, to
> dma buf framework. Of course, Those are ugly so we need a better way: I just
> wanted to show you that in such way, we can synchronize the shared buffer
> between cpu and dma. By any chance, is there any way that kernel can be
> aware of when cpu accesses the shared buffer or is there any point I didn't
> catch up?

Well dma_buf_map/unmap_attachment should also flush/invalidate any caches,
and with the current dma_buf spec those two functions are the _only_ means
you have to do so. Which strictly means that if you interleave device dma
and cpu acccess you need to unmap/map every time.

Which is obviously horribly inefficient, but a known gap in the dma_buf
interface. Hence why I proposed to add dma_buf_sync_attachment similar to
dma_sync_single_for_device:

/**
 * dma_buf_sync_sg_attachment - sync caches for dma access
 * @attach: dma-buf attachment to sync
 * @sgt: the sg table to sync (returned by dma_buf_map_attachement)
 * @direction: dma direction to sync for
 *
 * This function synchronizes caches for device dma through the given
 * dma-buf attachment when interleaving dma from different devices and the
 * cpu. Other device dma needs to be synced also by calls to this
 * function (or a pair of dma_buf_map/unmap_attachment calls), cpu access
 * needs to be synced with dma_buf_begin/end_cpu_access.
 */
void dma_buf_sync_sg_attachment(struct dma_buf_attachment *attach,
				struct sg_table *sgt,
				enum dma_data_direction direction)

Note that "sync" here only means to synchronize caches, not wait for any
outstanding fences. This is simply to be consistent with the established
lingo of the dma api. How the dma-buf fences fit into this is imo a
different topic, but my idea is that all the cache coherency barriers
(i.e. dma_buf_map/unmap_attachment, dma_buf_sync_sg_attachment and
dma_buf_begin/end_cpu_access) would automatically block for any attached
fences (i.e. block for write fences when doing read-only access, block for
all fences otherwise).

Then we could do a new dma_buf_attach_flags interface for special cases
(might also be useful for other things, similar to the recently added
flags in the dma api for wc/no-kernel-mapping/...). A new flag like
DMA_BUF_ATTACH_NO_AUTOFENCE would then mean that the driver takes care of all
fencing for this attachment and the dma-buf functions should not do the
automagic fence blocking.

> In Linux kernel, especially embedded system, we had tried to implement
> generic interfaces for buffer management; how to allocate a buffer and how
> to share a buffer. As a result, now we have CMA (Contiguous Memory
> Allocator) for buffer allocation, and we have DMA-BUF for buffer sharing
> between cpu and dma. And then how to synchronize a buffer between cpu and
> dma? I think now it's best time to discuss buffer synchronization mechanism,
> and that is very natural.

I think it's important to differentiate between the two meanings of sync:
- synchronize caches (i.e. cpu cache flushing in most cases)
- and synchronize in-flight dma with fences.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From nh-ky at jinso.co.jp  Tue May 21 03:51:14 2013
From: nh-ky at jinso.co.jp (Nguyen Hong Ky)
Date: Tue, 21 May 2013 16:51:14 +0900
Subject: [PATCH] ARM: shmobile: marzen: Use error values in usb_power_*
In-Reply-To: <1368679681-10779-1-git-send-email-horms+renesas@verge.net.au>
References: <1368679681-10779-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <CAK9_=nDQ01EMOhbRWnMEJP-KKCQ+U5LoKirfEimdTFRU2ABbGw@mail.gmail.com>

Tested-by: Nguyen Hong Ky <nh-ky at jinso.co.jp>


On Thu, May 16, 2013 at 1:48 PM, Simon Horman
<horms+renesas at verge.net.au> wrote:
> This patch updates the marzen board code as if USB PHY isn't enabled
> they phy will have a value set by ERR_PTR() rather than be NULL.
>
> Without this patch a NULL pointer dereference  and kernel panic
> occurs on initialisation of USB on marzen.
>
> This resolves a regression introduced in 3.10-rc1 by
> b7fa5c2aec5be083eb2719b405089703608e9bc6
> ("usb: phy: return -ENXIO when PHY layer isn't enabled").
>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/board-marzen.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
> index 9105285..b9594e9 100644
> --- a/arch/arm/mach-shmobile/board-marzen.c
> +++ b/arch/arm/mach-shmobile/board-marzen.c
> @@ -212,8 +212,8 @@ static struct platform_device *marzen_devices[] __initdata = {
>  static struct usb_phy *phy;
>  static int usb_power_on(struct platform_device *pdev)
>  {
> -       if (!phy)
> -               return -EIO;
> +       if (IS_ERR(phy))
> +               return PTR_ERR(phy);
>
>         pm_runtime_enable(&pdev->dev);
>         pm_runtime_get_sync(&pdev->dev);
> @@ -225,7 +225,7 @@ static int usb_power_on(struct platform_device *pdev)
>
>  static void usb_power_off(struct platform_device *pdev)
>  {
> -       if (!phy)
> +       if (IS_ERR(phy))
>                 return;
>
>         usb_phy_shutdown(phy);
> --
> 1.8.2.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From gang.chen at asianux.com  Tue May 21 03:51:39 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 15:51:39 +0800
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
Message-ID: <519B278B.6030708@asianux.com>

On 05/21/2013 02:57 PM, Geert Uytterhoeven wrote:
> On Tue, May 21, 2013 at 5:15 AM, Chen Gang <gang.chen at asianux.com> wrote:
>>> >> I think it would be better if we added a something like
>>> >> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
>>> >> like x86 can then select the former, and we can remove the long list of
>>> >> architectures from the current option.
>> >
>> > I guess your meaning is:
>> >
>> >   under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
>> >   So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.
>> >
>> > Is it correct ?
> No, you missed "and we can remove the long list of architectures from the
> current option".
> 

OK, thanks.

Is it correct: "it is unnecessary to add 'screen_info' to the code, for
arm64 will never support 'VGA_CONSOLE'" ?


>> > If so, I recommend to add depend item for VGA_CONSOLE directly:
> I strongly support CONFIG_HAVE_VGA_CONSOLE.

For me, I still recommend add 'ARM64' in the long list of architectures
for 'VGA_CONSOLE', I have 3 reasons, please check:

a. current implementation only changes one area which only related with
arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
touch many multiple platforms dependency, at least we need discuss about
it with multiple platforms guys for it, firstly.

b. We can find some cases to use CONFIG_HAVE_* as dpend on, but I can
not find any cases which let CONFIG_'samename' depend on
CONFIG_HAVE_'samename'.

c. The original way still has effect, although it seems not quit
beautiful, but it is correct and still clear for readers, it is still
sustainable.


Thanks.
-- 
Chen Gang

Asianux Corporation


From guz.fnst at cn.fujitsu.com  Tue May 21 04:00:19 2013
From: guz.fnst at cn.fujitsu.com (Gu Zheng)
Date: Tue, 21 May 2013 16:00:19 +0800
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <20130521084108.1a585f32@skate>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate>
Message-ID: <519B2993.4090409@cn.fujitsu.com>

On 05/21/2013 02:41 PM, Thomas Petazzoni wrote:

> Dear David Miller,
> 
> On Mon, 20 May 2013 23:26:19 -0700 (PDT), David Miller wrote:
>> From: Libo Chen <libo.chen at huawei.com>
>> Date: Tue, 21 May 2013 10:42:00 +0800
>>
>>> I find a lot of mistakes using struct platform_driver without owner.
>>> So I pick up some of them including usb and net modules
>>
>> Instead of doing it this way, which is obviously error prone and
>> easy to forget, make platform_driver_register() be a macro which
>> sets the module owner field then calls the real
>> __platform_driver_register().
> 
> Or, maybe make the existing module_platform_driver() macro do this?


But not all the modules use module_platform_driver() macro to replace the module init/exit.

Thanks,
Gu

> 
> Best regards,
> 
> Thomas




From clbchenlibo.chen at huawei.com  Tue May 21 04:26:47 2013
From: clbchenlibo.chen at huawei.com (Libo Chen)
Date: Tue, 21 May 2013 16:26:47 +0800
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <519B2993.4090409@cn.fujitsu.com>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate> <519B2993.4090409@cn.fujitsu.com>
Message-ID: <519B2FC7.6000801@huawei.com>

On 2013/5/21 16:00, Gu Zheng wrote:
> On 05/21/2013 02:41 PM, Thomas Petazzoni wrote:
> 
>> Dear David Miller,
>>
>> On Mon, 20 May 2013 23:26:19 -0700 (PDT), David Miller wrote:
>>> From: Libo Chen <libo.chen at huawei.com>
>>> Date: Tue, 21 May 2013 10:42:00 +0800
>>>
>>>> I find a lot of mistakes using struct platform_driver without owner.
>>>> So I pick up some of them including usb and net modules
>>>
>>> Instead of doing it this way, which is obviously error prone and
>>> easy to forget, make platform_driver_register() be a macro which
>>> sets the module owner field then calls the real
>>> __platform_driver_register().
>>
>> Or, maybe make the existing module_platform_driver() macro do this?
> 
> 
> But not all the modules use module_platform_driver() macro to replace the module init/exit.
> 
> Thanks,
> Gu
> 

yes, there are many drivers register platform_driver by platform_driver_register manually.

make both platform_driver_register() and module_platform_driver()  to check and set the module owner field?



>>
>> Best regards,
>>
>> Thomas
> 
> 
> 
> .
> 




From gang.chen at asianux.com  Tue May 21 04:41:19 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 16:41:19 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <5bf8a8dd20ecd01c14f0ed9aa054f2df@localhost>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com> <5bf8a8dd20ecd01c14f0ed9aa054f2df@localhost>
Message-ID: <519B332F.1000404@asianux.com>

On 05/21/2013 02:13 PM, Marc Zyngier wrote:
> On Tue, 21 May 2013 12:06:52 +0800, Chen Gang <gang.chen at asianux.com>
> wrote:
>> On 05/20/2013 05:56 PM, Will Deacon wrote:
>>> On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
>>>> On Mon, 20 May 2013 14:48:05 +0800, Chen Gang <gang.chen at asianux.com>
>>>> wrote:
>>>>> Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with
>>>>> allmodconfig.
>>>>>
>>>>> The related error:
>>>>>   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
>>>>>   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
>>>>>   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
>>>>>   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>>>>>
>>>>>
>>>>> Signed-off-by: Chen Gang <gang.chen at asianux.com>
>>>>> ---
>>>>>  arch/arm64/kernel/time.c |    1 +
>>>>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
>>>>> index a551f88..7fcba80 100644
>>>>> --- a/arch/arm64/kernel/time.c
>>>>> +++ b/arch/arm64/kernel/time.c
>>>>> @@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
>>>>>  	*timer_value = arch_timer_read_counter();
>>>>>  	return 0;
>>>>>  }
>>>>> +EXPORT_SYMBOL_GPL(read_current_timer);
>>>>>  
>>>>>  void __init time_init(void)
>>>>>  {
>>>>
>>>> While this solves the problem, I'm not sure this is the best fix. The
>>>> real
>>>> issue is with get_cycles, which is a macro around read_current_timer.
>>>>
>>>> AArch32 exports it because of the number of timer implementations. On
>>>> arm64, we should be able to just return CNTVCT_EL0.
>>>>
>>>> Catalin, Will, what do you think?
>>>
>>> Should be ok once the arch timer driver has moved exclusively to
> virtual
>>> time. I'm also not sure we even need to implement read_current_timer()
> --
>>> it's only used for delay-loop calibration, which we don't need for the
>>> arch timer.
>>>
>>
>> For whether we need implement read_current_timer():
>>
>>   many platforms have implemented it (openrisc, arm, sparc, hexagon,
>>   avr32, x86).
>>   it is called by init/calibrate.c when 'ARCH_HAS_READ_CURRENT_TIMER' is
>>   defined.
>>   since arm64 can implement it, better to provide it as an architect
>>   features to let outside use.
> 
> Nobody disputes the interest of read_current_timer.
> 

It is for Will said "I'm also not sure we even need to implement
read_current_timer()".

I think we still need it.


>> For the implementation of read_current_timer():
>>
>>   it has to face various configurations
>>     (e.g. CONFIG_ARM_ARCH_TIMER, arch_timer_read_zero,
>>     arch_counter_get_cntvct, arch_counter_get_cntpct)
>>   so better still use variable instead of.
>>     (excuse me, I do not know what is 'CNTVCT_EL0', is it like a
> constant
>>     number ?)
> 
> Architected timer is mandatory on arm64, so we can always rely on it it be
> present. CNTVCT_EL0 is the system register accessing the Virtual Counter,
> which is basically what read_current_timer() returns.
> 

OK, thanks. for CNTVCT_EL0, can we use arch_counter_get_cntvct() which
is defined in "arch/arm64/include/asm/arch_timer.h" ?


>> For the implementation of get_cycles()
>>
>>   if read_current_timer() is provided,
>>   better to let get_cycles() to call it, instead of implement once
> again.
> 
> There is certainly some value in reusing existing code, but in this
> particular case we can simply inline two instructions (isb + mrs
> cntvct_el0), and I'm not even completely sure about the isb.
> 

OK, thanks.


So, how about the fix below :)

------------------------diff begin-------------------------------

diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h
index b24a31a..768ba44 100644
--- a/arch/arm64/include/asm/timex.h
+++ b/arch/arm64/include/asm/timex.h
@@ -16,11 +16,13 @@
 #ifndef __ASM_TIMEX_H
 #define __ASM_TIMEX_H
 
+#include <asm/arch_timer.h>
+
 /*
  * Use the current timer as a cycle counter since this is what we use for
  * the delay loop.
  */
-#define get_cycles()	({ cycles_t c; read_current_timer(&c); c; })
+#define get_cycles()	arch_counter_get_cntvct()
 
 #include <asm-generic/timex.h>
 
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index a551f88..6d7ce08 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -38,6 +38,7 @@
 
 #include <asm/thread_info.h>
 #include <asm/stacktrace.h>
+#include <asm/arch_timer.h>
 
 #ifdef CONFIG_SMP
 unsigned long profile_pc(struct pt_regs *regs)
@@ -70,7 +71,7 @@ unsigned long long notrace sched_clock(void)
 
 int read_current_timer(unsigned long *timer_value)
 {
-	*timer_value = arch_timer_read_counter();
+	*timer_value = arch_counter_get_cntvct();
 	return 0;
 }


------------------------diff end---------------------------------

-- 
Chen Gang

Asianux Corporation


From guz.fnst at cn.fujitsu.com  Tue May 21 04:50:38 2013
From: guz.fnst at cn.fujitsu.com (Gu Zheng)
Date: Tue, 21 May 2013 16:50:38 +0800
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <519B2FC7.6000801@huawei.com>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate> <519B2993.4090409@cn.fujitsu.com>
 <519B2FC7.6000801@huawei.com>
Message-ID: <519B355E.8020505@cn.fujitsu.com>

On 05/21/2013 04:26 PM, Libo Chen wrote:

> On 2013/5/21 16:00, Gu Zheng wrote:
>> On 05/21/2013 02:41 PM, Thomas Petazzoni wrote:
>>
>>> Dear David Miller,
>>>
>>> On Mon, 20 May 2013 23:26:19 -0700 (PDT), David Miller wrote:
>>>> From: Libo Chen <libo.chen at huawei.com>
>>>> Date: Tue, 21 May 2013 10:42:00 +0800
>>>>
>>>>> I find a lot of mistakes using struct platform_driver without owner.
>>>>> So I pick up some of them including usb and net modules
>>>>
>>>> Instead of doing it this way, which is obviously error prone and
>>>> easy to forget, make platform_driver_register() be a macro which
>>>> sets the module owner field then calls the real
>>>> __platform_driver_register().
>>>
>>> Or, maybe make the existing module_platform_driver() macro do this?
>>
>>
>> But not all the modules use module_platform_driver() macro to replace the module init/exit.
>>
>> Thanks,
>> Gu
>>
> 
> yes, there are many drivers register platform_driver by platform_driver_register manually.
> 
> make both platform_driver_register() and module_platform_driver()  to check and set the module owner field?


No, module_platform_driver() will call platform_driver_register() to register platform_driver, just do it in
platform_driver_register() is enough.
As David mentioned, making platform_driver_register() be a macro and sets the module owner field in it, seems
a good way.

Thanks,
Gu

> 
> 
> 
>>>
>>> Best regards,
>>>
>>> Thomas
>>
>>
>>
>> .
>>
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 




From will.deacon at arm.com  Tue May 21 04:53:25 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 May 2013 09:53:25 +0100
Subject: [PATCH] arm64: kernel: compiling issue, need
 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <519AF2DC.2040200@asianux.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com>
Message-ID: <20130521085325.GB10453@mudshark.cambridge.arm.com>

On Tue, May 21, 2013 at 05:06:52AM +0100, Chen Gang wrote:
> On 05/20/2013 05:56 PM, Will Deacon wrote:
> > Should be ok once the arch timer driver has moved exclusively to virtual
> > time. I'm also not sure we even need to implement read_current_timer() --
> > it's only used for delay-loop calibration, which we don't need for the
> > arch timer.
> > 
> 
> For whether we need implement read_current_timer():
> 
>   many platforms have implemented it (openrisc, arm, sparc, hexagon, avr32, x86).
>   it is called by init/calibrate.c when 'ARCH_HAS_READ_CURRENT_TIMER' is defined.
>   since arm64 can implement it, better to provide it as an architect features to let outside use.

No, that code is not needed on arm64 because we calibrate the delay loop
statically using a known timer frequency.

> For the implementation of read_current_timer():
> 
>   it has to face various configurations
>     (e.g. CONFIG_ARM_ARCH_TIMER, arch_timer_read_zero, arch_counter_get_cntvct, arch_counter_get_cntpct)
>   so better still use variable instead of.
>     (excuse me, I do not know what is 'CNTVCT_EL0', is it like a constant number ?)

cntvct_el0 is a system register, which provides the virtual counter value.

> For the implementation of get_cycles()
> 
>   if read_current_timer() is provided,
>   better to let get_cycles() to call it, instead of implement once again.

You can implement it as a macro if you like, I'm just suggesting that we
might not need read_current_timer after all.

Will


From sameo at linux.intel.com  Tue May 21 04:56:50 2013
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Tue, 21 May 2013 10:56:50 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130517075140.GA25077@balto.lan>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
 <20130516224337.GZ22822@zurbaran>
 <20130517075140.GA25077@balto.lan>
Message-ID: <20130521085650.GB4589@zurbaran>

Hi Fabio,

On Fri, May 17, 2013 at 09:51:40AM +0200, Fabio Baltieri wrote:
> Hello Samuel,
> 
> On Fri, May 17, 2013 at 12:43:37AM +0200, Samuel Ortiz wrote:
> > > Fabio Baltieri (5):
> > >       mfd: abx500-core: Fix sparse warning
> > >       mfd: ab8500-sysctrl: Fix sparse warning
> > >       mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> > >       mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> > Unless I'm missing something here, this one is not really rcN material, so
> > I'd appreciate if you could queue it to your for-mfd branch instead.
> 
> The last two:
> 
>   mfd: ab8500-sysctrl: Set sysctrl_dev during probe
This one is already in mfd-fixes, the commit log was clear enough.


>   mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
This one is not, as the commit log is not showing it actually fixes something
but only makes the code cleaner. If it really fixes something, could you
please provide me with a commit log that describes what exactly it fixes ?

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From marc.zyngier at arm.com  Tue May 21 04:58:32 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 21 May 2013 09:58:32 +0100
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <519B332F.1000404@asianux.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com> <5bf8a8dd20ecd01c14f0ed9aa054f2df@localhost>
 <519B332F.1000404@asianux.com>
Message-ID: <519B3738.1010004@arm.com>

On 21/05/13 09:41, Chen Gang wrote:
> On 05/21/2013 02:13 PM, Marc Zyngier wrote:
>> On Tue, 21 May 2013 12:06:52 +0800, Chen Gang <gang.chen at asianux.com>
>> wrote:
>>> On 05/20/2013 05:56 PM, Will Deacon wrote:
>>>> On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
>>>>> On Mon, 20 May 2013 14:48:05 +0800, Chen Gang <gang.chen at asianux.com>
>>>>> wrote:
>>>>>> Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with
>>>>>> allmodconfig.
>>>>>>
>>>>>> The related error:
>>>>>>   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
>>>>>>   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
>>>>>>   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
>>>>>>   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>>>>>>
>>>>>>
>>>>>> Signed-off-by: Chen Gang <gang.chen at asianux.com>
>>>>>> ---
>>>>>>  arch/arm64/kernel/time.c |    1 +
>>>>>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
>>>>>> index a551f88..7fcba80 100644
>>>>>> --- a/arch/arm64/kernel/time.c
>>>>>> +++ b/arch/arm64/kernel/time.c
>>>>>> @@ -73,6 +73,7 @@ int read_current_timer(unsigned long *timer_value)
>>>>>>  	*timer_value = arch_timer_read_counter();
>>>>>>  	return 0;
>>>>>>  }
>>>>>> +EXPORT_SYMBOL_GPL(read_current_timer);
>>>>>>  
>>>>>>  void __init time_init(void)
>>>>>>  {
>>>>>
>>>>> While this solves the problem, I'm not sure this is the best fix. The
>>>>> real
>>>>> issue is with get_cycles, which is a macro around read_current_timer.
>>>>>
>>>>> AArch32 exports it because of the number of timer implementations. On
>>>>> arm64, we should be able to just return CNTVCT_EL0.
>>>>>
>>>>> Catalin, Will, what do you think?
>>>>
>>>> Should be ok once the arch timer driver has moved exclusively to
>> virtual
>>>> time. I'm also not sure we even need to implement read_current_timer()
>> --
>>>> it's only used for delay-loop calibration, which we don't need for the
>>>> arch timer.
>>>>
>>>
>>> For whether we need implement read_current_timer():
>>>
>>>   many platforms have implemented it (openrisc, arm, sparc, hexagon,
>>>   avr32, x86).
>>>   it is called by init/calibrate.c when 'ARCH_HAS_READ_CURRENT_TIMER' is
>>>   defined.
>>>   since arm64 can implement it, better to provide it as an architect
>>>   features to let outside use.
>>
>> Nobody disputes the interest of read_current_timer.
>>
> 
> It is for Will said "I'm also not sure we even need to implement
> read_current_timer()".
> 
> I think we still need it.

Not really. The only use of read_current_timer is for calibrating the
delay loop, and we just do not need this, because we can actually rely
on the timer to give us an accurate timing information.

>>> For the implementation of read_current_timer():
>>>
>>>   it has to face various configurations
>>>     (e.g. CONFIG_ARM_ARCH_TIMER, arch_timer_read_zero,
>>>     arch_counter_get_cntvct, arch_counter_get_cntpct)
>>>   so better still use variable instead of.
>>>     (excuse me, I do not know what is 'CNTVCT_EL0', is it like a
>> constant
>>>     number ?)
>>
>> Architected timer is mandatory on arm64, so we can always rely on it it be
>> present. CNTVCT_EL0 is the system register accessing the Virtual Counter,
>> which is basically what read_current_timer() returns.
>>
> 
> OK, thanks. for CNTVCT_EL0, can we use arch_counter_get_cntvct() which
> is defined in "arch/arm64/include/asm/arch_timer.h" ?

Yes.

>>> For the implementation of get_cycles()
>>>
>>>   if read_current_timer() is provided,
>>>   better to let get_cycles() to call it, instead of implement once
>> again.
>>
>> There is certainly some value in reusing existing code, but in this
>> particular case we can simply inline two instructions (isb + mrs
>> cntvct_el0), and I'm not even completely sure about the isb.
>>
> 
> OK, thanks.
> 
> 
> So, how about the fix below :)
> 
> ------------------------diff begin-------------------------------
> 
> diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h
> index b24a31a..768ba44 100644
> --- a/arch/arm64/include/asm/timex.h
> +++ b/arch/arm64/include/asm/timex.h
> @@ -16,11 +16,13 @@
>  #ifndef __ASM_TIMEX_H
>  #define __ASM_TIMEX_H
>  
> +#include <asm/arch_timer.h>
> +
>  /*
>   * Use the current timer as a cycle counter since this is what we use for
>   * the delay loop.
>   */
> -#define get_cycles()	({ cycles_t c; read_current_timer(&c); c; })
> +#define get_cycles()	arch_counter_get_cntvct()
>  
>  #include <asm-generic/timex.h>
>  
> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
> index a551f88..6d7ce08 100644
> --- a/arch/arm64/kernel/time.c
> +++ b/arch/arm64/kernel/time.c
> @@ -38,6 +38,7 @@
>  
>  #include <asm/thread_info.h>
>  #include <asm/stacktrace.h>
> +#include <asm/arch_timer.h>
>  
>  #ifdef CONFIG_SMP
>  unsigned long profile_pc(struct pt_regs *regs)
> @@ -70,7 +71,7 @@ unsigned long long notrace sched_clock(void)
>  
>  int read_current_timer(unsigned long *timer_value)
>  {
> -	*timer_value = arch_timer_read_counter();
> +	*timer_value = arch_counter_get_cntvct();
>  	return 0;
>  }
> 
> 
> ------------------------diff end---------------------------------

I think you should try to implement Will's suggestion and drop
read_current_timer (and the ARCH_HAS_READ_CURRENT_TIMER macro) altogether.

It would be a much better fix.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From gordon at holliweb.co.uk  Tue May 21 05:00:37 2013
From: gordon at holliweb.co.uk (Gordon Hollingworth)
Date: Tue, 21 May 2013 10:00:37 +0100
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
In-Reply-To: <008d01ce55e9$7c479510$74d6bf30$@lge.com>
References: <519AD82A.6090809@wwwdotorg.org>
 <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
 <008d01ce55e9$7c479510$74d6bf30$@lge.com>
Message-ID: <CAE8Q9tD8UiV=3sYbPPFGgiPCGzMS6xUWSGCRnR8tpGwQegyEQQ@mail.gmail.com>

Have checked with the designer of the UART block and he confirmed that
the 2835 PL011 contains a 16 deep fifo not 32 deep...

Hardware guys, they can never just leave it alone!!!

Gordon

On 21 May 2013 07:07, Jongsung Kim <neidhard.kim at lge.com> wrote:
> Jongsung Kim <neidhard.kim at lge.com> :
>> diff --git a/arch/arm/boot/dts/bcm2835.dtsi
> b/arch/arm/boot/dts/bcm2835.dtsi
>> index f0052dc..1e12aef 100644
>> --- a/arch/arm/boot/dts/bcm2835.dtsi
>> +++ b/arch/arm/boot/dts/bcm2835.dtsi
>> @@ -44,6 +44,7 @@
>>                       reg = <0x7e201000 0x1000>;
>>                       interrupts = <2 25>;
>>                       clock-frequency = <3000000>;
>> +                     arm,primecell-periphid = <0x00241011>;
>>               };
>>
>>               gpio: gpio {
>
> Stephen, how do you think about this kind of approach instead?
>
>
> _______________________________________________
> linux-rpi-kernel mailing list
> linux-rpi-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rpi-kernel


From will.deacon at arm.com  Tue May 21 05:03:36 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 May 2013 10:03:36 +0100
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <519B278B.6030708@asianux.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
 <519B278B.6030708@asianux.com>
Message-ID: <20130521090336.GC10453@mudshark.cambridge.arm.com>

On Tue, May 21, 2013 at 08:51:39AM +0100, Chen Gang wrote:
> On 05/21/2013 02:57 PM, Geert Uytterhoeven wrote:
> > On Tue, May 21, 2013 at 5:15 AM, Chen Gang <gang.chen at asianux.com> wrote:
> >>> >> I think it would be better if we added a something like
> >>> >> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
> >>> >> like x86 can then select the former, and we can remove the long list of
> >>> >> architectures from the current option.
> >> >
> >> > I guess your meaning is:
> >> >
> >> >   under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
> >> >   So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.
> >> >
> >> > Is it correct ?
> > No, you missed "and we can remove the long list of architectures from the
> > current option".
> > 
> 
> OK, thanks.
> 
> Is it correct: "it is unnecessary to add 'screen_info' to the code, for
> arm64 will never support 'VGA_CONSOLE'" ?

We can add the screen_info if and when we need to support a VGA console. In
the meantime, let's not add things on a whim.

> >> > If so, I recommend to add depend item for VGA_CONSOLE directly:
> > I strongly support CONFIG_HAVE_VGA_CONSOLE.
> 
> For me, I still recommend add 'ARM64' in the long list of architectures
> for 'VGA_CONSOLE', I have 3 reasons, please check:
> 
> a. current implementation only changes one area which only related with
> arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
> touch many multiple platforms dependency, at least we need discuss about
> it with multiple platforms guys for it, firstly.

That's a weak argument. You might as well propose the cleanup and see what
people say.

> b. We can find some cases to use CONFIG_HAVE_* as dpend on, but I can
> not find any cases which let CONFIG_'samename' depend on
> CONFIG_HAVE_'samename'.

Erm. PERF_EVENTS, BPF_JIT, IDE, ...?

> c. The original way still has effect, although it seems not quit
> beautiful, but it is correct and still clear for readers, it is still
> sustainable.

Sure, it works, but we're just contributing to the mess that's been built up
ever time another architecture has done the same thing. It's not hard to try
and clean it up.

Will


From nicolas.ferre at atmel.com  Tue May 21 05:06:00 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 May 2013 11:06:00 +0200
Subject: [PATCH] Change internal SRAM memory type to "MT_MEMORY_SO"
In-Reply-To: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <519B38F8.1040601@atmel.com>

On 20/05/2013 03:05, Wenyou Yang :
> Hi Russell,

Wenyou, In fact this patch is targeted for myself and not Russell. It 
will join mainline using arm-soc git tree which is managed by Arnd and Olof.

> This patch is to change the internal SRAM memory type to "MT_MEMORY_SO", the right type.
>
> It tested on sama5d3xek boards.
>
> It based on v3.10-rc1.
>
> Best Regards,
> Wenyou Yang
>
> Wenyou Yang (1):
>    ARM: at91: Fix: Change internal SRAM memory type to "MT_MEMORY_SO"
>
>   arch/arm/mach-at91/setup.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Bye,
-- 
Nicolas Ferre


From thomas.petazzoni at free-electrons.com  Tue May 21 05:06:16 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 11:06:16 +0200
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <519B2993.4090409@cn.fujitsu.com>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate> <519B2993.4090409@cn.fujitsu.com>
Message-ID: <20130521110616.21eee053@skate>

Dear Gu Zheng,

On Tue, 21 May 2013 16:00:19 +0800, Gu Zheng wrote:

> > Or, maybe make the existing module_platform_driver() macro do this?
> 
> But not all the modules use module_platform_driver() macro to replace the module init/exit.

Then maybe it's a good opportunity to convert those ones to use
module_platform_driver() ?

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From nicolas.ferre at atmel.com  Tue May 21 05:06:58 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 May 2013 11:06:58 +0200
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <519B3932.7030508@atmel.com>

On 20/05/2013 03:06, Wenyou Yang :
> Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

And stacked on at91-3.10-fixes.

Best regards,

> ---
>   arch/arm/mach-at91/setup.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index e2f4bdd..d68be6c 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -80,7 +80,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
>
>   	desc->pfn = __phys_to_pfn(base);
>   	desc->length = length;
> -	desc->type = MT_DEVICE;
> +	desc->type = MT_MEMORY_SO;
>
>   	pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
>   		base, length, desc->virtual);
>


-- 
Nicolas Ferre


From fabio.baltieri at linaro.org  Tue May 21 05:12:30 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Tue, 21 May 2013 11:12:30 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130521085650.GB4589@zurbaran>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
 <20130516224337.GZ22822@zurbaran>
 <20130517075140.GA25077@balto.lan> <20130521085650.GB4589@zurbaran>
Message-ID: <20130521091230.GA28756@balto.lan>

Hi Samuel,

On Tue, May 21, 2013 at 10:56:50AM +0200, Samuel Ortiz wrote:
> Hi Fabio,
> 
> On Fri, May 17, 2013 at 09:51:40AM +0200, Fabio Baltieri wrote:
> > Hello Samuel,
> > 
> > On Fri, May 17, 2013 at 12:43:37AM +0200, Samuel Ortiz wrote:
> > > > Fabio Baltieri (5):
> > > >       mfd: abx500-core: Fix sparse warning
> > > >       mfd: ab8500-sysctrl: Fix sparse warning
> > > >       mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> > > >       mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> > > Unless I'm missing something here, this one is not really rcN material, so
> > > I'd appreciate if you could queue it to your for-mfd branch instead.
> > 
> > The last two:
> > 
> >   mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> This one is already in mfd-fixes, the commit log was clear enough.

Great!

> >   mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> This one is not, as the commit log is not showing it actually fixes something
> but only makes the code cleaner. If it really fixes something, could you
> please provide me with a commit log that describes what exactly it fixes ?

Ok, the fix here is that right now that driver is initialized without a
specific pdata (that is plat->sysctrl), so enforcing it breaks existing
platforms for no reason.  To make the commit more clear I would just
point that out as in (just last two sentences):

--- >8 ---
mfd: ab8500-sysctrl: Let sysctrl driver work without pdata

A check for a valid plat->sysctrl was introduced in:

2377e52 mfd: ab8500-sysctrl: Error check clean up

but the driver works just fine even without that initialization data,
and enforcing it breaks existing platforms for no reason.

This patch removes the check and let the driver go ahead with probe.
--- >8 ---

Is it better?

Thanks,
Fabio

-- 
Fabio Baltieri


From yegorslists at googlemail.com  Tue May 21 05:17:16 2013
From: yegorslists at googlemail.com (Yegor Yefremov)
Date: Tue, 21 May 2013 11:17:16 +0200
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130520220540.GL10378@atomide.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com> <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de> <20130517185620.GF28484@animalcreek.com>
 <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>
 <20130520220540.GL10378@atomide.com>
Message-ID: <CAGm1_ku3Fgib8+ZkF0XOq6K9QxY80dAMZAP65uz4jpMEXQtWLg@mail.gmail.com>

On Tue, May 21, 2013 at 12:05 AM, Tony Lindgren <tony at atomide.com> wrote:
> * Yegor Yefremov <yegorslists at googlemail.com> [130517 14:34]:
>> On Fri, May 17, 2013 at 8:56 PM, Mark A. Greer <mgreer at animalcreek.com> wrote:
>> > On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
>> >> On 15.05.2013 23:50, Mark A. Greer wrote:
>> >> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
>> >
>> >> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
>> >> >> idle states with?
>> >> >
>> >> > I have an am35xx which isn't supposed to have an IVA so I can test with it
>> >> > (although, I'm not sure how well the kernel works on the am35xx these days).
>> >> >
>> >> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
>> >> > comes up, see what I can figure out.
>> >>
>> >> I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
>> >> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
>> >>
>> >> I have such a system running, so if you have any other patches/ideas to test, I would do it.
>> >
>> > Yegor, since I've so far been unable to get my am3517evm to fire up, can
>> > you play around with the 3517 to see if there appears to be iva registers
>> > that can be read/written to safely?  In particular, can the code that idles
>> > the iva be run safely on an am3517?
>>
>> I'll look into this next week. am3517 and IVA seems to be a really big
>> mystery. In the TI forum will be stated, there is no IVA:
>> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/150961.aspx, but TRM
>> has various appearances of IVA2 registers, but no real
>> description/explanation of what is IVA and how to eat it.
>
> On 3703 it looks like the whole omap3_iva_idle() reset is needed, except
> for setting the iva2 bootmode to idle. So I'm planning to merge the following
> patch with just comments update this week unless somebody has a better fix
> in mind.

calling omap3_iva_idle() made no difference so far. I still can boot
3.10-rc2 with 'nohlt' and omap3_iva_idle() and vice versa, without
'nohlt' I cannot boot whether with or without calling
omap3_iva_idle().

BTW Tony I've sent a patch to fix MUSB clock naming. Should I also
make a recent including linux-usb mailing list or can we handle this
internally on omap/arm list?

Yegor


From lorenzo.pieralisi at arm.com  Tue May 21 05:21:19 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Tue, 21 May 2013 10:21:19 +0100
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <1369051881.3511.4.camel@linaro1.home>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
 <1369051881.3511.4.camel@linaro1.home>
Message-ID: <20130521092119.GA1885@e102568-lin.cambridge.arm.com>

On Mon, May 20, 2013 at 01:11:21PM +0100, Jon Medhurst (Tixy) wrote:
> On Thu, 2013-05-09 at 11:34 +0100, Lorenzo Pieralisi wrote:
> [...]
> > +static int __init cci_probe(void)
> > +{
> > +	struct cci_nb_ports const *cci_config;
> > +	int ret, i, nb_ace = 0, nb_ace_lite = 0;
> > +	struct device_node *np, *cp;
> > +	const char *match_str;
> > +	bool is_ace;
> > +
> > +	np = of_find_matching_node(NULL, arm_cci_matches);
> > +	if (!np)
> > +		return -ENODEV;
> > +
> > +	cci_config = of_match_node(arm_cci_matches, np)->data;
> > +	if (!cci_config)
> > +		return -ENODEV;
> > +
> > +	nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
> > +
> > +	ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
> > +	if (!ports)
> > +		return -ENOMEM;
> > +
> > +	cci_ctrl_base = of_iomap(np, 0);
> > +
> > +	if (!cci_ctrl_base) {
> > +		WARN(1, "unable to ioremap CCI ctrl\n");
> > +		ret = -ENXIO;
> > +		goto memalloc_err;
> > +	}
> > +
> > +	for_each_child_of_node(np, cp) {
> > +		i = nb_ace + nb_ace_lite;
> > +
> > +		if (i >= nb_cci_ports)
> > +			break;
> 
> I know this is a bit late, but...
> 
> Would it not be best to check here that the node type is in fact
> "slave-if", that way if we add support in later versions for other node
> types (e.g. for the PMU) then we don't cause backward compatibility
> issues. I'm thinking here of the same concerns that Rob raised with
> "ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes"

The node name, not type, but point is taken. I prefer to add a
compatible property to slave-if nodes (eg "arm,cci-400-control-if"),
I do not think that checking the node name is the standard way of doing
things in DT world.

Thoughts ?

Thanks,
Lorenzo

> > +		if (of_property_read_string(cp, "interface-type",
> > +					&match_str)) {
> > +			WARN(1, "node %s missing interface-type property\n",
> > +				  cp->full_name);
> > +			continue;
> > +		}
> > +
> [..]
> 
> -- 
> Tixy
> 
> 



From inki.dae at samsung.com  Tue May 21 05:22:49 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 21 May 2013 18:22:49 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <20130521074441.GZ12292@phenom.ffwll.local>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
Message-ID: <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>



> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Tuesday, May 21, 2013 4:45 PM
> To: Inki Dae
> Cc: 'Daniel Vetter'; 'Rob Clark'; 'linux-fbdev'; 'DRI mailing list';
> 'Kyungmin Park'; 'myungjoo.ham'; 'YoungJun Cho'; linux-arm-
> kernel at lists.infradead.org; linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Tue, May 21, 2013 at 04:03:06PM +0900, Inki Dae wrote:
> > > - Integration of fence syncing into dma_buf. Imo we should have a
> > >   per-attachment mode which decides whether map/unmap (and the new
> sync)
> > >   should wait for fences or whether the driver takes care of syncing
> > >   through the new fence framework itself (for direct hw sync).
> >
> > I think it's a good idea to have per-attachment mode for buffer sync.
> But
> > I'd like to say we make sure what is the purpose of map
> > (dma_buf_map_attachment)first. This interface is used to get a sgt;
> > containing pages to physical memory region, and map that region with
> > device's iommu table. The important thing is that this interface is
> called
> > just one time when user wants to share an allocated buffer with dma. But
> cpu
> > will try to access the buffer every time as long as it wants. Therefore,
> we
> > need cache control every time cpu and dma access the shared buffer:
> cache
> > clean when cpu goes to dma and cache invalidate when dma goes to cpu.
> That
> > is why I added new interfaces, DMA_BUF_GET_FENCE and DMA_BUF_PUT_FENCE,
> to
> > dma buf framework. Of course, Those are ugly so we need a better way: I
> just
> > wanted to show you that in such way, we can synchronize the shared
> buffer
> > between cpu and dma. By any chance, is there any way that kernel can be
> > aware of when cpu accesses the shared buffer or is there any point I
> didn't
> > catch up?
> 
> Well dma_buf_map/unmap_attachment should also flush/invalidate any caches,
> and with the current dma_buf spec those two functions are the _only_ means

I know that dma buf exporter should make sure that cache clean/invalidate
are done when dma_buf_map/unmap_attachement is called. For this, already we
do so. However, this function is called when dma buf import is requested by
user to map a dmabuf fd with dma. This means that dma_buf_map_attachement()
is called ONCE when user wants to share the dmabuf fd with dma. Actually, in
case of exynos drm, dma_map_sg_attrs(), performing cache operation
internally, is called when dmabuf import is requested by user.

> you have to do so. Which strictly means that if you interleave device dma
> and cpu acccess you need to unmap/map every time.
> 
> Which is obviously horribly inefficient, but a known gap in the dma_buf

Right, and also this has big overhead.

> interface. Hence why I proposed to add dma_buf_sync_attachment similar to
> dma_sync_single_for_device:
> 
> /**
>  * dma_buf_sync_sg_attachment - sync caches for dma access
>  * @attach: dma-buf attachment to sync
>  * @sgt: the sg table to sync (returned by dma_buf_map_attachement)
>  * @direction: dma direction to sync for
>  *
>  * This function synchronizes caches for device dma through the given
>  * dma-buf attachment when interleaving dma from different devices and the
>  * cpu. Other device dma needs to be synced also by calls to this
>  * function (or a pair of dma_buf_map/unmap_attachment calls), cpu access
>  * needs to be synced with dma_buf_begin/end_cpu_access.
>  */
> void dma_buf_sync_sg_attachment(struct dma_buf_attachment *attach,
> 				struct sg_table *sgt,
> 				enum dma_data_direction direction)
> 
> Note that "sync" here only means to synchronize caches, not wait for any
> outstanding fences. This is simply to be consistent with the established
> lingo of the dma api. How the dma-buf fences fit into this is imo a
> different topic, but my idea is that all the cache coherency barriers
> (i.e. dma_buf_map/unmap_attachment, dma_buf_sync_sg_attachment and
> dma_buf_begin/end_cpu_access) would automatically block for any attached
> fences (i.e. block for write fences when doing read-only access, block for
> all fences otherwise).

As I mentioned already, kernel can't aware of when cpu accesses a shared
buffer: user can access a shared buffer after mmap anytime and the shared
buffer should be synchronized between cpu and dma. Therefore, the above
cache coherency barriers should be called every time cpu and dma tries to
access a shared buffer, checking before and after of cpu and dma access. And
exactly, the proposed way do such thing. For this, you can refer to the
below link,
	
http://www.mail-archive.com/linux-media at vger.kernel.org/msg62124.html

My point is that how kernel can aware of when those cache coherency barriers
should be called to synchronize caches and buffer access between cpu and
dma.

> 
> Then we could do a new dma_buf_attach_flags interface for special cases
> (might also be useful for other things, similar to the recently added
> flags in the dma api for wc/no-kernel-mapping/...). A new flag like
> DMA_BUF_ATTACH_NO_AUTOFENCE would then mean that the driver takes care of
> all
> fencing for this attachment and the dma-buf functions should not do the
> automagic fence blocking.
> 
> > In Linux kernel, especially embedded system, we had tried to implement
> > generic interfaces for buffer management; how to allocate a buffer and
> how
> > to share a buffer. As a result, now we have CMA (Contiguous Memory
> > Allocator) for buffer allocation, and we have DMA-BUF for buffer sharing
> > between cpu and dma. And then how to synchronize a buffer between cpu
> and
> > dma? I think now it's best time to discuss buffer synchronization
> mechanism,
> > and that is very natural.
> 
> I think it's important to differentiate between the two meanings of sync:
> - synchronize caches (i.e. cpu cache flushing in most cases)
> - and synchronize in-flight dma with fences.
> 

Agree, and I meant that the buffer synchronization mechanism includes the
above two things. And I think the two things should be addressed together.

Thanks,
Inki Dae

> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



From gang.chen at asianux.com  Tue May 21 05:26:08 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 17:26:08 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <519B3738.1010004@arm.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com> <5bf8a8dd20ecd01c14f0ed9aa054f2df@localhost>
 <519B332F.1000404@asianux.com> <519B3738.1010004@arm.com>
Message-ID: <519B3DB0.4020806@asianux.com>

On 05/21/2013 04:58 PM, Marc Zyngier wrote:
> I think you should try to implement Will's suggestion and drop
> read_current_timer (and the ARCH_HAS_READ_CURRENT_TIMER macro) altogether.
> 
> It would be a much better fix.

OK, thanks. I will send patch v2.

-- 
Chen Gang

Asianux Corporation


From gang.chen at asianux.com  Tue May 21 05:27:20 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 17:27:20 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL_GPL(read_current_timer)'
In-Reply-To: <20130521085325.GB10453@mudshark.cambridge.arm.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com>
 <20130521085325.GB10453@mudshark.cambridge.arm.com>
Message-ID: <519B3DF8.9060902@asianux.com>

On 05/21/2013 04:53 PM, Will Deacon wrote:
> On Tue, May 21, 2013 at 05:06:52AM +0100, Chen Gang wrote:
>> On 05/20/2013 05:56 PM, Will Deacon wrote:
>>> Should be ok once the arch timer driver has moved exclusively to virtual
>>> time. I'm also not sure we even need to implement read_current_timer() --
>>> it's only used for delay-loop calibration, which we don't need for the
>>> arch timer.
>>>
>>
>> For whether we need implement read_current_timer():
>>
>>   many platforms have implemented it (openrisc, arm, sparc, hexagon, avr32, x86).
>>   it is called by init/calibrate.c when 'ARCH_HAS_READ_CURRENT_TIMER' is defined.
>>   since arm64 can implement it, better to provide it as an architect features to let outside use.
> 
> No, that code is not needed on arm64 because we calibrate the delay loop
> statically using a known timer frequency.
> 
>> For the implementation of read_current_timer():
>>
>>   it has to face various configurations
>>     (e.g. CONFIG_ARM_ARCH_TIMER, arch_timer_read_zero, arch_counter_get_cntvct, arch_counter_get_cntpct)
>>   so better still use variable instead of.
>>     (excuse me, I do not know what is 'CNTVCT_EL0', is it like a constant number ?)
> 
> cntvct_el0 is a system register, which provides the virtual counter value.
> 
>> For the implementation of get_cycles()
>>
>>   if read_current_timer() is provided,
>>   better to let get_cycles() to call it, instead of implement once again.
> 
> You can implement it as a macro if you like, I'm just suggesting that we
> might not need read_current_timer after all.
> 
> Will
> 
> 

Thanks, I should try patch v2.  :-)

-- 
Chen Gang

Asianux Corporation


From thomas.petazzoni at free-electrons.com  Tue May 21 05:35:02 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 11:35:02 +0200
Subject: mvebu: mbus device tree binding
In-Reply-To: <20130520123153.GA2904@localhost>
References: <20130520123153.GA2904@localhost>
Message-ID: <20130521113502.231a5f38@skate>

Dear Ezequiel Garcia,

On Mon, 20 May 2013 09:31:54 -0300, Ezequiel Garcia wrote:

> This does not seem to be hugely problematic, for one could put the
> 'ranges' property only in the per-board files, and remove it from the
> common dtsi.
> 
> Therefore, first of all I'd like to know:
> 
> **1** What's so broken with the current approach that makes us seek for
>       solution, in the form of an mbus DT binding?

Currently, the addresses of the registers to configure the MBUS windows
and get the current values of the DRAM windows (to provide those
values to the device drivers so that they can configure their own DRAM
windows for DMA) are completely hardcoded. See
mach-mvebu/armada-370-xp.h.

For sure, we want those values to move into the Device Tree, just like
for all other peripherals. This is what my original DT binding of the
mvebu-mbus driver was doing, but since the DT binding was not complete,
Arnd suggested to completely remove it, merge the driver without a DT
binding, and think about it later.

So, for sure, we want a DT binding for the mvebu-mbus driver.

> In addition, reading the previous discussion you've had about this, I
> noticed Arnd suggested (and even required) that the mbus binding should
> update the ranges property in the DT blob each time an address window
> is dynamically allocated.
> 
> **2** Why is this required? Who will read the updated ranges
>       information?
>       Why can't the kernel access the mbus API to obtain information
>       about currently allocated windows?

This has already been asked by me in the past, and answered by Arnd at
the end of
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/160923.html.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From benh at kernel.crashing.org  Tue May 21 05:38:38 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Tue, 21 May 2013 19:38:38 +1000
Subject: [RFC PATCH v3] drivers: bus: add ARM CCI support
In-Reply-To: <20130521092119.GA1885@e102568-lin.cambridge.arm.com>
References: <1368095640-3675-1-git-send-email-lorenzo.pieralisi@arm.com>
 <1368095640-3675-2-git-send-email-lorenzo.pieralisi@arm.com>
 <1369051881.3511.4.camel@linaro1.home>
 <20130521092119.GA1885@e102568-lin.cambridge.arm.com>
Message-ID: <1369129118.6387.61.camel@pasglop>

On Tue, 2013-05-21 at 10:21 +0100, Lorenzo Pieralisi wrote:
> The node name, not type, but point is taken. I prefer to add a
> compatible property to slave-if nodes (eg "arm,cci-400-control-if"),
> I do not think that checking the node name is the standard way of
> doing
> things in DT world.
> 
> Thoughts ?

Agreed.

Cheers,
Ben.




From ulf.hansson at linaro.org  Tue May 21 05:46:14 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Tue, 21 May 2013 11:46:14 +0200
Subject: [PATCH 1/3] ARM: ux500: Enable MMC_UNSAFE_RESUME
In-Reply-To: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
References: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
Message-ID: <1369129576-28617-2-git-send-email-ulf.hansson@linaro.org>

Enable CONFIG_MMC_UNSAFE_RESUME to be accomplish a proper
suspend/resume cycle for SD/SDIO/(e)MMC.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/configs/u300_defconfig  |    1 +
 arch/arm/configs/u8500_defconfig |    1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000e..c839375 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -51,6 +51,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index c037aa1..f9e3f38 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -82,6 +82,7 @@ CONFIG_REGULATOR_GPIO=y
 CONFIG_USB_GADGET=y
 CONFIG_AB8500_USB=y
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
-- 
1.7.10



From ulf.hansson at linaro.org  Tue May 21 05:46:15 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Tue, 21 May 2013 11:46:15 +0200
Subject: [PATCH 2/3] ARM: ux500: Don't use MMC_CLKGATE
In-Reply-To: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
References: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
Message-ID: <1369129576-28617-3-git-send-email-ulf.hansson@linaro.org>

Since ARMMMCI host driver now supports clock gating through runtime PM
CONFIG_MMC_CLKGATE is not needed anymore.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/configs/u300_defconfig  |    1 -
 arch/arm/configs/u8500_defconfig |    1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index c839375..ffe2db8 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -52,7 +52,6 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index f9e3f38..45d9087 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -83,7 +83,6 @@ CONFIG_USB_GADGET=y
 CONFIG_AB8500_USB=y
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
-- 
1.7.10



From ulf.hansson at linaro.org  Tue May 21 05:46:16 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Tue, 21 May 2013 11:46:16 +0200
Subject: [PATCH 3/3] ARM: ux500: Disable MMC_BLOCK_BOUNCE
In-Reply-To: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
References: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
Message-ID: <1369129576-28617-4-git-send-email-ulf.hansson@linaro.org>

Since ARMMMCI can do scatter-gather we don't need CONFIG_MMC_BLOCK_BOUNCE.
Explicity disable it since it's default enabled, to skip unnecessarry
bounce buffer copying.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/configs/u300_defconfig  |    1 +
 arch/arm/configs/u8500_defconfig |    1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index ffe2db8..9c7941d 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -52,6 +52,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 45d9087..8fe6293 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -83,6 +83,7 @@ CONFIG_USB_GADGET=y
 CONFIG_AB8500_USB=y
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
-- 
1.7.10



From gang.chen at asianux.com  Tue May 21 05:46:05 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 17:46:05 +0800
Subject: [PATCH v2] arm64: kernel: compiling issue,
 need delete read_current_timer().
In-Reply-To: <20130521085325.GB10453@mudshark.cambridge.arm.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com>
 <20130521085325.GB10453@mudshark.cambridge.arm.com>
Message-ID: <519B425D.4030806@asianux.com>


Under arm64, we will calibrate the delay loop statically using a known
timer frequency, so delete read_current_timer(), or it will cause
compiling issue with allmodconfig.

The related error:
  ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
  ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
  ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
  ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/include/asm/timex.h |    6 +++---
 arch/arm64/kernel/time.c       |    6 ------
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h
index b24a31a..81a076e 100644
--- a/arch/arm64/include/asm/timex.h
+++ b/arch/arm64/include/asm/timex.h
@@ -16,14 +16,14 @@
 #ifndef __ASM_TIMEX_H
 #define __ASM_TIMEX_H
 
+#include <asm/arch_timer.h>
+
 /*
  * Use the current timer as a cycle counter since this is what we use for
  * the delay loop.
  */
-#define get_cycles()	({ cycles_t c; read_current_timer(&c); c; })
+#define get_cycles()	arch_counter_get_cntvct()
 
 #include <asm-generic/timex.h>
 
-#define ARCH_HAS_READ_CURRENT_TIMER
-
 #endif
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index a551f88..03dc371 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -68,12 +68,6 @@ unsigned long long notrace sched_clock(void)
 	return arch_timer_read_counter() * sched_clock_mult;
 }
 
-int read_current_timer(unsigned long *timer_value)
-{
-	*timer_value = arch_timer_read_counter();
-	return 0;
-}
-
 void __init time_init(void)
 {
 	u32 arch_timer_rate;
-- 
1.7.7.6


From clbchenlibo.chen at huawei.com  Tue May 21 05:42:34 2013
From: clbchenlibo.chen at huawei.com (Libo Chen)
Date: Tue, 21 May 2013 17:42:34 +0800
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <20130521110616.21eee053@skate>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate> <519B2993.4090409@cn.fujitsu.com>
 <20130521110616.21eee053@skate>
Message-ID: <519B418A.7060805@huawei.com>

On 2013/5/21 17:06, Thomas Petazzoni wrote:
> Dear Gu Zheng,
> 
> On Tue, 21 May 2013 16:00:19 +0800, Gu Zheng wrote:
> 
>>> Or, maybe make the existing module_platform_driver() macro do this?
>>
>> But not all the modules use module_platform_driver() macro to replace the module init/exit.
> 
> Then maybe it's a good opportunity to convert those ones to use
> module_platform_driver() ?
> 
> Thomas
> 

 In my opinion, not all modules can use module_platform_driver() macro to replace the module init/exit easily, like us3mc_init.

 Furthermore this work will touch various platforms and architectures, I am worried it is hard to *test* (compile and boot).

 What do you think?



From ulf.hansson at linaro.org  Tue May 21 05:46:13 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Tue, 21 May 2013 11:46:13 +0200
Subject: [PATCH 0/3] ARM: ux500: Update defconfigs for MMC
Message-ID: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>

This patchset updates the MMC defconfigs in the u8500|u300_defconfig.

Ulf Hansson (3):
  ARM: ux500: Enable MMC_UNSAFE_RESUME
  ARM: ux500: Don't use MMC_CLKGATE
  ARM: ux500: Disable MMC_BLOCK_BOUNCE

 arch/arm/configs/u300_defconfig  |    3 ++-
 arch/arm/configs/u8500_defconfig |    3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

-- 
1.7.10



From steve.capper at linaro.org  Tue May 21 06:05:31 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Tue, 21 May 2013 11:05:31 +0100
Subject: hugetlbfs support plan for ARM
In-Reply-To: <519ACF4B.9070502@gmail.com>
References: <3E54258959B69E4282D79E01AB1F32B7044F299D@DFLE11.ent.ti.com>
 <519ACF4B.9070502@gmail.com>
Message-ID: <20130521100507.GA14248@linaro.org>

On Tue, May 21, 2013 at 09:35:07AM +0800, bill4carson wrote:
> Hi, Karichri
> 
> On 2013?05?21? 02:26, Karicheri, Muralidharan wrote:
> >Hi Bill,
> >
> >I see the patch at http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/084360.html
> >
> >Is there a plan to merge this to upstream Linux kernel? I would appreciate your response on this.
> 
> I tried to post several round of this patch set, but haven't got more time to merge it.
> Steve Capper from ARM proposed both HUGEPAGE and THP in below link,
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/148451.html
> 
> Look https://wiki.linaro.org/LEG/Engineering/Kernel/HugePages here to find what you needs.
> 

Hi,
Apologies for the delay, I am working on rebasing HugeTLB+THP for 3.10-rc1. An
issue with PROT_NONE has arisen, and I'm currently fixing this.

Cheers,
-- 
Steve

> >Thanks.
> >
> >Murali Karicheri
> >
> >/Software Design Engineer/
> >
> 
> -- 
> ?????????,??????????
> 
> --bill



From peter at stuge.se  Tue May 21 06:13:49 2013
From: peter at stuge.se (Peter Stuge)
Date: Tue, 21 May 2013 12:13:49 +0200
Subject: [PATCH] Finally eradicate CONFIG_HOTPLUG
In-Reply-To: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
References: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
Message-ID: <20130521101349.30660.qmail@stuge.se>

Are you changing the code to have HOTPLUG always -on- or -off- ?

From the commit message I had expected always -on-.


Stephen Rothwell wrote:
> --- a/include/asm-generic/vmlinux.lds.h
> +++ b/include/asm-generic/vmlinux.lds.h
> @@ -68,14 +68,6 @@
>   * are handled as text/data or they can be discarded (which
>   * often happens at runtime)
>   */
> -#ifdef CONFIG_HOTPLUG
> -#define DEV_KEEP(sec)    *(.dev##sec)
> -#define DEV_DISCARD(sec)
> -#else
> -#define DEV_KEEP(sec)
> -#define DEV_DISCARD(sec) *(.dev##sec)
> -#endif
> -
>  #ifdef CONFIG_HOTPLUG_CPU
>  #define CPU_KEEP(sec)    *(.cpu##sec)
>  #define CPU_DISCARD(sec)
> @@ -182,8 +174,6 @@
>  	*(.data)							\
>  	*(.ref.data)							\
>  	*(.data..shared_aligned) /* percpu related */			\
> -	DEV_KEEP(init.data)						\
> -	DEV_KEEP(exit.data)						\
..
> @@ -503,7 +489,6 @@
>  /* init and exit section handling */
>  #define INIT_DATA							\
>  	*(.init.data)							\
> -	DEV_DISCARD(init.data)						\

Shouldn't the effect of one of the above remain?


//Peter
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From gang.chen at asianux.com  Tue May 21 06:13:08 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 18:13:08 +0800
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <20130521090336.GC10453@mudshark.cambridge.arm.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
 <519B278B.6030708@asianux.com>
 <20130521090336.GC10453@mudshark.cambridge.arm.com>
Message-ID: <519B48B4.6050607@asianux.com>

On 05/21/2013 05:03 PM, Will Deacon wrote:
> On Tue, May 21, 2013 at 08:51:39AM +0100, Chen Gang wrote:
>> On 05/21/2013 02:57 PM, Geert Uytterhoeven wrote:
>>> On Tue, May 21, 2013 at 5:15 AM, Chen Gang <gang.chen at asianux.com> wrote:
>>>>>>> I think it would be better if we added a something like
>>>>>>> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
>>>>>>> like x86 can then select the former, and we can remove the long list of
>>>>>>> architectures from the current option.
>>>>>
>>>>> I guess your meaning is:
>>>>>
>>>>>   under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
>>>>>   So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.
>>>>>
>>>>> Is it correct ?
>>> No, you missed "and we can remove the long list of architectures from the
>>> current option".
>>>
>>
>> OK, thanks.
>>
>> Is it correct: "it is unnecessary to add 'screen_info' to the code, for
>> arm64 will never support 'VGA_CONSOLE'" ?
> 
> We can add the screen_info if and when we need to support a VGA console. In
> the meantime, let's not add things on a whim.
> 

OK, thanks. At least now (for our case), need not add 'screen_info', is
it correct ?


>>>>> If so, I recommend to add depend item for VGA_CONSOLE directly:
>>> I strongly support CONFIG_HAVE_VGA_CONSOLE.
>>
>> For me, I still recommend add 'ARM64' in the long list of architectures
>> for 'VGA_CONSOLE', I have 3 reasons, please check:
>>
>> a. current implementation only changes one area which only related with
>> arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
>> touch many multiple platforms dependency, at least we need discuss about
>> it with multiple platforms guys for it, firstly.
> 
> That's a weak argument. You might as well propose the cleanup and see what
> people say.
> 

Hmm.. I think at least, we need discuss it with the 'final applier'
firstly (and now, I even do not know who is the 'final applier').


>> b. We can find some cases to use CONFIG_HAVE_* as dpend on, but I can
>> not find any cases which let CONFIG_'samename' depend on
>> CONFIG_HAVE_'samename'.
> 
> Erm. PERF_EVENTS, BPF_JIT, IDE, ...?
> 

CONFIG_PERF_EVENTS is not directly depend on CONFIG_HAVE_PERF_EVENTS.
CONFIG_BPF_JIT is not directly depend on CONFIG_HAVE_BPF_JIT.
CONFIG_IDE is not directly depend on CONFIG_HAVE_IDE.
...

But I guess what we will do is to let "CONFIG_VGA_CONSOLE is directly
depend on CONFIG_HAVE_VGA_CONSOLE".

So I think we really need discuss it firstly with the 'final applier'.


>> c. The original way still has effect, although it seems not quit
>> beautiful, but it is correct and still clear for readers, it is still
>> sustainable.
> 
> Sure, it works, but we're just contributing to the mess that's been built up
> ever time another architecture has done the same thing. It's not hard to try
> and clean it up.
> 

Can we separate into 2 patches ?. One is for current compiling issue
with allmodconfig (the priority is a litter higher), the other is for
fixup patch (the priority is lower).  ;-)


BTW: In fact, if we really need send the related fixup patch, I am also
unwilling to do that, I guess (in my experience), the fixup patch like
that, will never be applied. :-(


Thanks.
-- 
Chen Gang

Asianux Corporation


From daniel.lezcano at linaro.org  Tue May 21 06:14:12 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 21 May 2013 12:14:12 +0200
Subject: [PATCH v4] clocksource: add Vybrid Family pit timer support
In-Reply-To: <1369121274-9371-1-git-send-email-b35083@freescale.com>
References: <1369121274-9371-1-git-send-email-b35083@freescale.com>
Message-ID: <519B48F4.8050005@linaro.org>

On 05/21/2013 09:27 AM, Jingchang Lu wrote:
> Add Freescale Vybrid Family period interrupt timer support.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v4:
>   use family name names driver and symbol instead of SoC name.
>   remove redundant code.
>   use BUG_ON instead of WARN_ON.
>   add necessory comment information.
> 
>  drivers/clocksource/Kconfig         |   5 +
>  drivers/clocksource/Makefile        |   1 +
>  drivers/clocksource/mvf_pit_timer.c | 187 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 193 insertions(+)
>  create mode 100644 drivers/clocksource/mvf_pit_timer.c

[ ... ]

> +
> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	/*
> +	 * set a new value to PITLDVAL register will not restart the timer,
> +	 * to abort the current cycle and start a timer period with the new
> +	 * value, the timer must be disabled and enabled again.
> +	 * and the PITLAVAL should be set to delta minus one.

Why delta "minus one" ?

> +	 */
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_timer_enable();
> +
> +	return 0;
> +}
> +
> +static void pit_set_mode(enum clock_event_mode mode,
> +				struct clock_event_device *evt)
> +{
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		pit_timer_disable();
> +		__raw_writel(cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
> +		pit_timer_enable();

You can call pit_set_next_event(cycle_per_jiffy, evt) instead of adding
redundant code, no ?

> +		break;
> +	default:
> +		break;
> +	}
> +}

[ ... ]

> +
> +static struct clock_event_device clockevent_pit = {
> +	.name		= "MVF pit timer",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= pit_set_mode,
> +	.set_next_event	= pit_set_next_event,
> +	.rating		= 300,
> +};
> +
> +static struct irqaction pit_timer_irq = {
> +	.name		= "MVF pit timer",
> +	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,

Did you take into account Thomas's comment ?

> +	.handler	= pit_timer_interrupt,
> +	.dev_id		= &clockevent_pit,
> +};
> +
> +static int __init pit_clockevent_init(struct clk *pit_clk, int irq)
> +{
> +	unsigned int c = clk_get_rate(pit_clk);
> +
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +
> +	clockevent_pit.cpumask = cpumask_of(0);

The irq initialization is missing.

	clockevent_pit.irq = irq;

> +	clockevents_config_and_register(&clockevent_pit, c, 2, 0xffffffff);

Is it possible to have a comment with the justification for these values ?

> +
> +	BUG_ON(setup_irq(irq, &pit_timer_irq));
> +	return 0;

Everything is ok if you can't setup your timer ?

> +}
> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	int irq;
> +
> +	timer_base = of_iomap(np, 0);
> +	BUG_ON(!timer_base);

You raise a bug and then you go ahead setting up the address with an
invalid value, leading to a random crash.

> +	/*
> +	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
> +	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
> +	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
> +	 */
> +	clksrc_base = timer_base + PITn_OFFSET(2);
> +	clkevt_base = timer_base + PITn_OFFSET(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +
> +	pit_clk = of_clk_get(np, 0);
> +	BUG_ON(IS_ERR(pit_clk));
> +
> +	BUG_ON(clk_prepare_enable(pit_clk));

Same here.

> +	cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
> +
> +	/* enable the pit module */
> +	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
> +
> +	BUG_ON(pit_clocksource_init(pit_clk));
> +
> +	pit_clockevent_init(pit_clk, irq);

Please, remove these BUG_ON, this is inconsistent especially with a one
call init function. If pit_timer_init can't be initialized, just pr_err
+ BUG.

Thanks
  -- Daniel


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

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From andreas.herrmann at calxeda.com  Tue May 21 06:25:01 2013
From: andreas.herrmann at calxeda.com (Andreas Herrmann)
Date: Tue, 21 May 2013 12:25:01 +0200
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130520101841.GK31359@mudshark.cambridge.arm.com>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
 <20130513095846.GC29814@mudshark.cambridge.arm.com>
 <20130513104147.GF10369@alberich> <20130517201639.GL10369@alberich>
 <20130520101841.GK31359@mudshark.cambridge.arm.com>
Message-ID: <20130521102501.GB14432@alberich>

On Mon, May 20, 2013 at 06:18:41AM -0400, Will Deacon wrote:
> Hi Andreas,
> 
> On Fri, May 17, 2013 at 09:16:39PM +0100, Andreas Herrmann wrote:
> > On Mon, May 13, 2013 at 12:41:47PM +0200, Andreas Herrmann wrote:
> > > On Mon, May 13, 2013 at 05:58:46AM -0400, Will Deacon wrote:
> > > > Again, you also need to tie in topology information if you go down this
> > > > route.
> > 
> > I still don't like the approach of having two independend lists that
> > must be in sync to associate a master with its stream-ids.
> > 
> > Why? Say you have 8 masters for an SMMU with 1 or 2 stream-ids each:
> > 
> >      	 smmu {
> > 		...
> >                 mmu-masters = <&dma0>, <&dma0>, <&dma1>, <&dma1>,
> > 			      <&dma2>, <&dma2>, <&dma4>, <&dma4>,
> > 			      <&dma5>, <&dma6>, <&dma7>, <&dma8>;
> >                 stream-ids =	<0>, <1>, <2>, <3>,
> > 				<4>, <5>, <6>, <7>,
> > 		                <8>, <9>, <0xa>, <0xb>;
> > 	}
> > 
> > Couldn't we use of_phandle_args for this purpose? So your example
> > 
> > +        smmu {
> > 		 ...
> > +                mmu-masters = <&dma0>,
> > +                              <&dma0>,
> > +                              <&dma1>;
> > +                stream-ids  = <0xd01d>,
> > +                              <0xd01e>,
> > +                              <0xd11c>;
> > +        };
> > 
> > would look like
> > 
> > 	dma0 {
> > 		...
> > 		#stream-id-cells = <2>
> > 		...
> > 	}
> > 
> > 	dma1 {
> > 		...
> > 		#stream-id-cells = <1>
> > 		...
> > 	}
> > 
> >         smmu {
> > 		...
> > 		mmu-masters = <&dma0 0xd01d 0xd01e
> > 			       &dma1 0xd11c>,
> >        };
> > 
> > and my example would be converted to
> > 
> > 	smmu {
> > 		...
> >                 mmu-masters = <&dma0 0 1 &dma1 2 3 &dma2 4 5
> > 			       &dma4 6 7 &dma5 8 &dma6 9
> > 			       &dma7 0xa &dma8 0xb>
> > 		...
> > 	}
> 
> That also looks fine to me, although I'd like to write the parsing code in
> my driver before I commit to anything!
> 
> > Of course usage of of_phandle_args would restrict the number of
> > stream-ids per master to 8 (which is currently used as
> > MAX_PHANDLE_ARGS). But I don't think that this is a restriction in
> > practice or do you expect to have more than 8 stream-ids per master
> > (ie. per struct device in Linux)?
> 
> Actually, I think that could be a problem. It doesn't sound unlikely that
> multi-channel DMA controllers could have:
> 
> 	- Separate instruction fetch streamid per channel
> 	- Separate read/write streamids per channel
> 
> so 8 does sound a bit small to me. How difficult would it be to bump that
> number in the future if we needed to?

Seems it was introduced with commit 15c9a0acc3f7873db4b7d35d016729b2dc229b49
(of: create of_phandle_args to simplify return of phandle parsing data)
by Grant Likely.

The macro is primarily used in struct of_phandle_args. I don't believe
that increasing the number of args (e.g. doubling it if necessary)
would cause objections.

struct of_phandle_args is used as argument for various (parsing
functions). In several functions objects of that type are on the
stack.

And there is a private data structure in gpiolib-of.c which also
contains an object of that type:

  struct gg_data {
        enum of_gpio_flags *flags;
        struct of_phandle_args gpiospec;
        int out_gpio;
  };

I don't expect that stack overflows or significant blowup of kernel
size will be casued by a moderate bump of MAX_PHANDLE_ARGS. I think
doubling it or even increasing it to 32 will not cause issues.

(Of course its impossible to increase it to the theoretical maximum of
32k (15-bit) stream-ids. But 32k stream-ids for just one Linux device?
I'd say practically irrelevant.)


Andreas


From b35083 at freescale.com  Tue May 21 03:27:54 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 21 May 2013 15:27:54 +0800
Subject: [PATCH v4] clocksource: add Vybrid Family pit timer support
Message-ID: <1369121274-9371-1-git-send-email-b35083@freescale.com>

Add Freescale Vybrid Family period interrupt timer support.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  use family name names driver and symbol instead of SoC name.
  remove redundant code.
  use BUG_ON instead of WARN_ON.
  add necessory comment information.

 drivers/clocksource/Kconfig         |   5 +
 drivers/clocksource/Makefile        |   1 +
 drivers/clocksource/mvf_pit_timer.c | 187 ++++++++++++++++++++++++++++++++++++
 3 files changed, 193 insertions(+)
 create mode 100644 drivers/clocksource/mvf_pit_timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f151c6c..4f3ca11 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
 	  Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
 	  for all devicetree enabled platforms. This driver will be
 	  needed only on systems that do not have the Exynos MCT available.
+
+config MVF_PIT_TIMER
+	bool
+	help
+	  Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c7..e28783c 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
 obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
+obj-$(CONFIG_MVF_PIT_TIMER)	+= mvf_pit_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
diff --git a/drivers/clocksource/mvf_pit_timer.c b/drivers/clocksource/mvf_pit_timer.c
new file mode 100644
index 0000000..34f4871
--- /dev/null
+++ b/drivers/clocksource/mvf_pit_timer.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/sched_clock.h>
+
+/*
+ * Each pit takes 0x10 Bytes register space
+ */
+#define PITMCR		0x00
+#define PIT0_OFFSET	0x100
+#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
+#define PITLDVAL	0x00
+#define PITCVAL		0x04
+#define PITTCTRL	0x08
+#define PITTFLG		0x0c
+
+#define PITMCR_MDIS	(0x1 << 1)
+
+#define PITTCTRL_TEN	(0x1 << 0)
+#define PITTCTRL_TIE	(0x1 << 1)
+#define PITCTRL_CHN	(0x1 << 2)
+
+#define PITTFLG_TIF	0x1
+
+static void __iomem *clksrc_base;
+static void __iomem *clkevt_base;
+static unsigned long cycle_per_jiffy;
+
+static inline void pit_timer_enable(void)
+{
+	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_timer_disable(void)
+{
+	__raw_writel(0, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_acknowledge(void)
+{
+	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+}
+
+static unsigned int pit_read_sched_clock(void)
+{
+	return __raw_readl(clksrc_base + PITCVAL);
+}
+
+static int __init pit_clocksource_init(struct clk *pit_clk)
+{
+	unsigned int c = clk_get_rate(pit_clk);
+
+	/* set the max load value and start the clock source counter */
+	__raw_writel(0, clksrc_base + PITTCTRL);
+	__raw_writel(~0UL, clksrc_base + PITLDVAL);
+	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
+
+	setup_sched_clock(pit_read_sched_clock, 32, c);
+	return clocksource_mmio_init(clksrc_base + PITCVAL, "mvf-pit", c,
+			300, 32, clocksource_mmio_readl_down);
+}
+
+static int pit_set_next_event(unsigned long delta,
+				struct clock_event_device *unused)
+{
+	/*
+	 * set a new value to PITLDVAL register will not restart the timer,
+	 * to abort the current cycle and start a timer period with the new
+	 * value, the timer must be disabled and enabled again.
+	 * and the PITLAVAL should be set to delta minus one.
+	 */
+	pit_timer_disable();
+	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
+	pit_timer_enable();
+
+	return 0;
+}
+
+static void pit_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		pit_timer_disable();
+		__raw_writel(cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
+		pit_timer_enable();
+		break;
+	default:
+		break;
+	}
+}
+
+static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	pit_irq_acknowledge();
+
+	/*
+	 * pit hardware doesn't support oneshot, it will generate an interrupt
+	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,
+	 * and start the counter again. So software need to disable the timer
+	 * to stop the counter loop in ONESHOT mode.
+	 */
+	if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
+		pit_timer_disable();
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_pit = {
+	.name		= "MVF pit timer",
+	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode	= pit_set_mode,
+	.set_next_event	= pit_set_next_event,
+	.rating		= 300,
+};
+
+static struct irqaction pit_timer_irq = {
+	.name		= "MVF pit timer",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= pit_timer_interrupt,
+	.dev_id		= &clockevent_pit,
+};
+
+static int __init pit_clockevent_init(struct clk *pit_clk, int irq)
+{
+	unsigned int c = clk_get_rate(pit_clk);
+
+	__raw_writel(0, clkevt_base + PITTCTRL);
+	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+
+	clockevent_pit.cpumask = cpumask_of(0);
+	clockevents_config_and_register(&clockevent_pit, c, 2, 0xffffffff);
+
+	BUG_ON(setup_irq(irq, &pit_timer_irq));
+
+	return 0;
+}
+
+static void __init pit_timer_init(struct device_node *np)
+{
+	struct clk *pit_clk;
+	void __iomem *timer_base;
+	int irq;
+
+	timer_base = of_iomap(np, 0);
+	BUG_ON(!timer_base);
+
+	/*
+	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
+	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
+	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
+	 */
+	clksrc_base = timer_base + PITn_OFFSET(2);
+	clkevt_base = timer_base + PITn_OFFSET(3);
+
+	irq = irq_of_parse_and_map(np, 0);
+
+	pit_clk = of_clk_get(np, 0);
+	BUG_ON(IS_ERR(pit_clk));
+
+	BUG_ON(clk_prepare_enable(pit_clk));
+
+	cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
+
+	/* enable the pit module */
+	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
+
+	BUG_ON(pit_clocksource_init(pit_clk));
+
+	pit_clockevent_init(pit_clk, irq);
+}
+CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf600-pit", pit_timer_init);
-- 
1.8.0




From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:26 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:26 +0200
Subject: [PATCH 1/9] arm: mvebu: fix length of SATA registers area in .dtsi
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-2-git-send-email-thomas.petazzoni@free-electrons.com>

The length of the registers area for the Marvell 370/XP SATA
controller was incorrect in the .dtsi: 0x2400 while it should have
been 0x5000. Until now, this problem wasn't noticed because there was
a large static mapping for all I/Os set up by ->map_io(). But since
we're going to get rid of this static mapping, we need to ensure that
the register areas are properly sized.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..75de3fe 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -79,7 +79,7 @@
 
 			sata at a0000 {
 				compatible = "marvell,orion-sata";
-				reg = <0xa0000 0x2400>;
+				reg = <0xa0000 0x5000>;
 				interrupts = <55>;
 				clocks = <&gateclk 15>, <&gateclk 30>;
 				clock-names = "0", "1";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:27 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:27 +0200
Subject: [PATCH 2/9] arm: mvebu: fix length of Ethernet registers area in .dtsi
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-3-git-send-email-thomas.petazzoni@free-electrons.com>

The length of the registers area for the Marvell 370/XP Ethernet
controller was incorrect in the .dtsi: 0x2400 while it should have
been 0x4000. Until now, this problem wasn't noticed because there was
a large static mapping for all I/Os set up by ->map_io(). But since
we're going to get rid of this static mapping, we need to ensure that
the register areas are properly sized.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi     |    4 ++--
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |    2 +-
 arch/arm/boot/dts/armada-xp.dtsi         |    2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 75de3fe..96a6bcd 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -95,7 +95,7 @@
 
 			ethernet at 70000 {
 				compatible = "marvell,armada-370-neta";
-				reg = <0x70000 0x2500>;
+				reg = <0x70000 0x4000>;
 				interrupts = <8>;
 				clocks = <&gateclk 4>;
 				status = "disabled";
@@ -103,7 +103,7 @@
 
 			ethernet at 74000 {
 				compatible = "marvell,armada-370-neta";
-				reg = <0x74000 0x2500>;
+				reg = <0x74000 0x4000>;
 				interrupts = <10>;
 				clocks = <&gateclk 3>;
 				status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6ab56bd..488ca5e 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -107,7 +107,7 @@
 
 			ethernet at 34000 {
 				compatible = "marvell,armada-370-neta";
-				reg = <0x34000 0x2500>;
+				reg = <0x34000 0x4000>;
 				interrupts = <14>;
 				clocks = <&gateclk 1>;
 				status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index bacab11..67936f89 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -88,7 +88,7 @@
 
 			ethernet at 30000 {
 				compatible = "marvell,armada-370-neta";
-				reg = <0x30000 0x2500>;
+				reg = <0x30000 0x4000>;
 				interrupts = <12>;
 				clocks = <&gateclk 2>;
 				status = "disabled";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:28 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:28 +0200
Subject: [PATCH 3/9] arm: mvebu: mark functions of armada-370-xp.c as static
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-4-git-send-email-thomas.petazzoni@free-electrons.com>

All the functions in armada-370-xp.c are called from the
DT_MACHINE_START function pointers, so there is no need for them to be
visible outside of this file, and we therefore mark them as static.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3..bfe337d 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -38,18 +38,18 @@ static struct map_desc armada_370_xp_io_desc[] __initdata = {
 	},
 };
 
-void __init armada_370_xp_map_io(void)
+static void __init armada_370_xp_map_io(void)
 {
 	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
 }
 
-void __init armada_370_xp_timer_and_clk_init(void)
+static void __init armada_370_xp_timer_and_clk_init(void)
 {
 	mvebu_clocks_init();
 	armada_370_xp_timer_init();
 }
 
-void __init armada_370_xp_init_early(void)
+static void __init armada_370_xp_init_early(void)
 {
 	char *mbus_soc_name;
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:29 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:29 +0200
Subject: [PATCH 4/9] arm: mvebu: remove dependency of SMP init on static I/O
 mapping
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-5-git-send-email-thomas.petazzoni@free-electrons.com>

The ->smp_init_cpus() function is called very early during boot, at a
point where dynamic I/O mappings are not yet possible. However, in the
Armada 370/XP implementation of this function, we have to get the
number of CPUs. We used to do that by accessing a hardware register,
which requires relying on a static I/O mapping set up by
->map_io(). Not only this requires hardcoding a virtual address, but
it also prevents us from removing the static I/O mapping.

So this commit changes the way used to get the number of CPUs: we now
use the Device Tree, which is a representation of the hardware, and
provides us the number of available CPUs. This is also more accurate,
because it potentially allows to boot the Linux kernel on only a
number of CPUs given by the Device Tree, instead of unconditionally on
all CPUs.

As a consequence, the coherency_get_cpu_count() function becomes no
longer used, so we remove it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/coherency.c |   12 ------------
 arch/arm/mach-mvebu/coherency.h |    4 ----
 arch/arm/mach-mvebu/common.h    |    2 ++
 arch/arm/mach-mvebu/platsmp.c   |   10 +++++++++-
 4 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 8278960..46d66c0 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -47,18 +47,6 @@ static struct of_device_id of_coherency_table[] = {
 	{ /* end of list */ },
 };
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void)
-{
-	int reg, cnt;
-
-	reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
-	cnt = (reg & 0xF) + 1;
-
-	return cnt;
-}
-#endif
-
 /* Function defined in coherency_ll.S */
 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
 
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 2f42813..df33ad8 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,10 +14,6 @@
 #ifndef __MACH_370_XP_COHERENCY_H
 #define __MACH_370_XP_COHERENCY_H
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void);
-#endif
-
 int set_cpu_coherent(int cpu_id, int smp_group_id);
 int coherency_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..98defd5 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,6 +15,8 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
+#define ARMADA_XP_MAX_CPUS 4
+
 void mvebu_restart(char mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 875ea74..93f2f3a 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
 
 static void __init armada_xp_smp_init_cpus(void)
 {
+	struct device_node *np;
 	unsigned int i, ncores;
-	ncores = coherency_get_cpu_count();
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np)
+		panic("No 'cpus' node found\n");
+
+	ncores = of_get_child_count(np);
+	if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
+		panic("Invalid number of CPUs in DT\n");
 
 	/* Limit possible CPUs to defconfig */
 	if (ncores > nr_cpu_ids) {
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:25 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:25 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada 370/XP
Message-ID: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

The aim of this patch series is to move the internal registers space
of the Armada 370 and Armada XP support to 0xf1000000 instead of
0xd0000000, and prepare for the support of the new versions of U-Boot
installed by Marvell on Armada 370 and XP platforms that boot the
kernel with the internal registers space already mapped at 0xf1000000.

Before reading the patches, and especially the last one, please read
on for a description of the problem and the proposed solution. The
solution has been carefully thought of, and all the details explained
below are important to understand how the proposed solution was
designed.

On Marvell EBU SoCs, including earlier families such as Kirkwood or
Dove, all the peripheral registers belong to a memory window of 1 MB,
called the "internal registers window". This window of physical memory
can be freely moved to an arbitrary physical address. At reset, this
memory window is at 0xD0000000, but it can be changed by software to
another address if needed.

The *very* important thing to remember is that the mechanism to get or
change the base address of this "internal registers" window is a
register, which is itself part of this "internal registers"
window. The bottom line is that when you run code on a Marvell SoC,
you have to *know* where the internal registers are located, because
you can't guess dynamically by reading some hardware register. Again,
this is a *very* important characteristic, because it explains many of
the choices of the proposed solution below.

Historically, the bootloaders for Dove and Kirkwood have always
remapped the internal registers window at 0xF1000000, so for those
platforms, the Linux kernel has always made the assumption that
internal registers are accessible at 0xF1000000.

Unfortunately, for Armada 370 and Armada XP, the current generation of
bootloaders that are being shipped on Marvell evaluation boards, but
also on products like the Plathome OpenBlocks AX3 or the Globalscale
Mirabox do not do the remapping, and are leaving the internal
registers at 0xD0000000.

However, this is causing some problems:

 1 The internal registers window sits at 3 GB, in the middle of the
   0-4 GB area of physical memory, which is quite annoying when you
   have more than 3 GB of memory. Having them at 0xF1000000 means that
   you lose less RAM when you have more than 3 GB of physical memory
   installed. And since Armada XP is LPAE capable, you can even have
   more than 4 GB memory: we already have boards with 8 GB of memory
   installed.

 2 This is different from Kirkwood and Dove, which makes sharing some
   early code like earlyprintk complicated, while our goal is
   ultimately to merge all Marvell EBU platforms into mach-mvebu.

(1) is really the primary motivation here, (2) is only a nice
side-effect.

So, the new generation of bootloaders that are shipped on new Marvell
Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
starting Linux. The current kernel cannot boot on such platforms.

One solution is to move the kernel to use 0xF1000000, and assume the
bootloader has already done the remapping. This can be one option, but
it means that newer kernels would no longer boot on platforms that use
an old bootloader. All existing users of Globalscale Mirabox or
Plathome OpenBlocks AX3, next time they upgrade their kernel, would
have a kernel that simply doesn't boot (and without showing *any*
message, because even the address of the UART has changed).

If the only Armada 370/XP platforms in use today had been evaluation
boards that are available only to a selected number of people,
dropping the compatibility would probably have been
acceptable. However, with a large number of Mirabox and OpenBlocks AX3
devices being already shipped, we believe that breaking the
compatibility is not an option.

Therefore, the last patch of this series adds some early code in the
kernel, at the ->map_io() stage, to switch the internal registers from
0xD0000000 to 0xF1000000 if this has not been done already by the
bootloader. As it was explained above, we unfortunately can't read the
current base address of the internal register window, so we need a
different mechanism to know if the bootloader has done the remapping
at 0xF1000000 (new generation bootloader) or has left the internal
registers at 0xD0000000 (old generation bootloader). In order to
distinguish between those two cases, a CP15 bit is being used. Old
bootloaders do not touch this CP15, so it is set to 0. New bootloaders
set this CP15 bit to 1, so that the kernel knows that the remapping
has already been done. The ->map_io() code looks at this bit to know
if the remapping should be done or not.

Unfortunately, tweaking ->map_io() is not sufficient: we also want
earlyprintk to work. And earlyprintk is used *before* ->map_io() is
called, and *after* ->map_io() is called. So in the earlyprintk code,
we also need to do a little bit of magic to know if we're booted on an
old or new bootloader, and if the remapping has occured or not in the
case of an old bootloader. Since the CP15 bit that we use gets cleared
the first time the 'wfi' instruction is cleared, we use this bit only
in the early kernel boot. As soon as ->map_io() as done its job, it
sets a global variable that tells the earlyprintk code that the
registers are now at 0xF1000000.

I hope this long explanation gives enough context to understand the
problem and the proposed solution. Do not hesitate to ask for more
details if needed.

Notice that the solution would be much simpler if we could do this
remapping earlier in the kernel initialization. Unfortunately,
->map_io() is really the first piece of code that is being called into
SoC-specific code, so it's the only way of doing this without making
changes in generic places in the kernel.

In detail, the patch series has:

 * Patches 1 and 2 fix the Device Tree informations that were
   incorrect for some peripherals: the register area length was
   incorrect. This was not visible until the removal of the bit static
   I/O mapping in patch 6, but is clearly a bug.

   Presumably those patches should be applied on 3.10-rc if possible,
   and therefore they should most likely be applied to mvebu/fixes.

 * Patch 3 is a cleanup, adds 'static' to some functions that lacked
   this qualifier.

   To be applied to mvebu/cleanups

 * Patch 4 and 5 slightly rework the way the SMP initialization and
   the coherency unit initialization is done, in order to avoid the
   hardcoded virtual address in the coherency.c file.

   To be applied to mvebu/soc

 * Patch 6 moves the L2 cache and mvebu-mbus initialization a bit
   later (i.e from ->init_early() to ->init_time()) so that they can
   ioremap() their registers without crashing once we remove the
   static I/O mapping (next patch).

 * Patch 7 removes the static I/O mapping that was set up at
   ->map_io() time to cover the entire "internal registers" area. This
   is possible thanks to patches 1, 2, 4, 5 and 6.

   To be applied to mvebu/soc

 * Patch 8 removes the hardcoded physical address in the SMP
   initialization code. This is made possible thanks to patches 4 and
   5.

   To be applied to mvebu/soc

 * Patch 9 implements the internal register address change itself. The
   DTS changes are included in the same patch as the code changes. It
   is possible to split them in two patches, but applying just one
   patch and not the other would lead to a kernel that doesn't boot at
   all.

   To be applied to mvebu/soc (even though there are admittedly some
   DT changes in here).

Best regards,

Thomas

Thomas Petazzoni (9):
  arm: mvebu: fix length of SATA registers area in .dtsi
  arm: mvebu: fix length of Ethernet registers area in .dtsi
  arm: mvebu: mark functions of armada-370-xp.c as static
  arm: mvebu: remove dependency of SMP init on static I/O mapping
  arm: mvebu: avoid hardcoded virtual address in coherency code
  arm: mvebu: move cache and mvebu-mbus initialization later
  arm: mvebu: remove hardcoded static I/O mapping
  arm: mvebu: don't hardcode a physical address in headsmp.S
  arm: mvebu: switch internal register address at runtime if needed

 arch/arm/boot/dts/armada-370-xp.dtsi     |    8 +-
 arch/arm/boot/dts/armada-370.dtsi        |    2 +-
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |    2 +-
 arch/arm/boot/dts/armada-xp.dtsi         |    2 +-
 arch/arm/include/debug/mvebu.S           |   77 +++++++++++++++--
 arch/arm/mach-mvebu/armada-370-xp.c      |  137 +++++++++++++++++++++++++-----
 arch/arm/mach-mvebu/armada-370-xp.h      |    4 +-
 arch/arm/mach-mvebu/coherency.c          |   36 +++-----
 arch/arm/mach-mvebu/coherency.h          |    4 -
 arch/arm/mach-mvebu/common.h             |    2 +
 arch/arm/mach-mvebu/headsmp.S            |   20 +++--
 arch/arm/mach-mvebu/platsmp.c            |   10 ++-
 12 files changed, 231 insertions(+), 73 deletions(-)

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:32 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:32 +0200
Subject: [PATCH 7/9] arm: mvebu: remove hardcoded static I/O mapping
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-8-git-send-email-thomas.petazzoni@free-electrons.com>

Now that we have removed the need of the static I/O mapping for early
initialization reasons, and fixed the registers area length that were
broken, we can get rid of the static I/O mapping. Only the earlyprintk
mapping needs to be set up, using the debug_ll_io_init() helper
function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |   11 +----------
 arch/arm/mach-mvebu/armada-370-xp.h |    2 --
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 23cdabd..90cc0e8 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -29,18 +29,9 @@
 #include "common.h"
 #include "coherency.h"
 
-static struct map_desc armada_370_xp_io_desc[] __initdata = {
-	{
-		.virtual	= (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
-		.pfn		= __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
-		.length		= ARMADA_370_XP_REGS_SIZE,
-		.type		= MT_DEVICE,
-	},
-};
-
 static void __init armada_370_xp_map_io(void)
 {
-	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+	debug_ll_io_init();
 }
 
 static void __init armada_370_xp_timer_and_clk_init(void)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 2070e1b..585e147 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,8 +16,6 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE	IOMEM(0xfec00000)
-#define ARMADA_370_XP_REGS_SIZE		SZ_1M
 
 /* These defines can go away once mvebu-mbus has a DT binding */
 #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:31 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:31 +0200
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus initialization later
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>

Current, the L2 cache and the mvebu-mbus drivers are initialized at
->init_early() time. However, at ->init_early() time, ioremap() only
works if a static I/O mapping has already been put in place. If it's
not the case, it tries to do a memory allocation with kmalloc() which
is not possible so early at this stage of the initialization.

Since we want to get rid of the static I/O mapping, we cannot
initialize the L2 cache driver and the mvebu-mbus driver so early. So,
we move their initialization to the ->init_time() level, which is
slightly later (so ioremap() works properly), but sufficiently early
to be before the call of the ->smp_prepare_cpus() hook, which creates
an address decoding window for the BootROM, which requires the
mvebu-mbus driver to be properly initialized.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |   24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 3af5628..23cdabd 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -45,21 +45,11 @@ static void __init armada_370_xp_map_io(void)
 
 static void __init armada_370_xp_timer_and_clk_init(void)
 {
+	char *mbus_soc_name;
+
 	mvebu_clocks_init();
 	armada_370_xp_timer_init();
 	coherency_init();
-}
-
-static void __init armada_370_xp_init_early(void)
-{
-	char *mbus_soc_name;
-
-	/*
-	 * Some Armada 370/XP devices allocate their coherent buffers
-	 * from atomic context. Increase size of atomic coherent pool
-	 * to make sure such the allocations won't fail.
-	 */
-	init_dma_coherent_pool_size(SZ_1M);
 
 	/*
 	 * This initialization will be replaced by a DT-based
@@ -81,6 +71,16 @@ static void __init armada_370_xp_init_early(void)
 #endif
 }
 
+static void __init armada_370_xp_init_early(void)
+{
+	/*
+	 * Some Armada 370/XP devices allocate their coherent buffers
+	 * from atomic context. Increase size of atomic coherent pool
+	 * to make sure such the allocations won't fail.
+	 */
+	init_dma_coherent_pool_size(SZ_1M);
+}
+
 static void __init armada_370_xp_dt_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:30 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:30 +0200
Subject: [PATCH 5/9] arm: mvebu: avoid hardcoded virtual address in coherency
 code
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-6-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the coherency_get_cpu_count() function no longer requires a
very early mapping of the coherency unit registers, we can avoid the
hardcoded virtual address in coherency.c. However, the coherency
features are still used quite early, so we need to do the of_iomap()
early enough, at the ->init_timer() level, so we have the call of
coherency_init() at this point.

Unfortunately, at ->init_timer() time, it is not possible to register
a bus notifier, so we add a separate coherency_late_init() function
that gets called as as postcore_initcall(), when bus notifiers are
available.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |    2 +-
 arch/arm/mach-mvebu/coherency.c     |   20 ++++++++++----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index bfe337d..3af5628 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -47,6 +47,7 @@ static void __init armada_370_xp_timer_and_clk_init(void)
 {
 	mvebu_clocks_init();
 	armada_370_xp_timer_init();
+	coherency_init();
 }
 
 static void __init armada_370_xp_init_early(void)
@@ -83,7 +84,6 @@ static void __init armada_370_xp_init_early(void)
 static void __init armada_370_xp_dt_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-	coherency_init();
 }
 
 static const char * const armada_370_xp_dt_compat[] = {
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 46d66c0..d74794a 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -27,14 +27,7 @@
 #include <asm/smp_plat.h>
 #include "armada-370-xp.h"
 
-/*
- * Some functions in this file are called very early during SMP
- * initialization. At that time the device tree framework is not yet
- * ready, and it is not possible to get the register address to
- * ioremap it. That's why the pointer below is given with an initial
- * value matching its virtual mapping
- */
-static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
+static void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 
 /* Coherency fabric registers */
@@ -135,9 +128,16 @@ int __init coherency_init(void)
 		coherency_base = of_iomap(np, 0);
 		coherency_cpu_base = of_iomap(np, 1);
 		set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-		bus_register_notifier(&platform_bus_type,
-					&mvebu_hwcc_platform_nb);
 	}
 
 	return 0;
 }
+
+static int __init coherency_late_init(void)
+{
+	bus_register_notifier(&platform_bus_type,
+			      &mvebu_hwcc_platform_nb);
+	return 0;
+}
+
+postcore_initcall(coherency_late_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:33 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:33 +0200
Subject: [PATCH 8/9] arm: mvebu: don't hardcode a physical address in headsmp.S
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-9-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the coherency_init() function is called a bit earlier, we can
actually read the physical address of the coherency unit registers
from the Device Tree, and communicate that to the headsmp.S code,
which avoids hardcoding a physical address.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/coherency.c |    4 ++++
 arch/arm/mach-mvebu/headsmp.S   |   20 +++++++++++---------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index d74794a..3d8f40f 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -27,6 +27,7 @@
 #include <asm/smp_plat.h>
 #include "armada-370-xp.h"
 
+unsigned long __cpuinitdata coherency_phys_base;
 static void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 
@@ -124,7 +125,10 @@ int __init coherency_init(void)
 
 	np = of_find_matching_node(NULL, of_coherency_table);
 	if (np) {
+		struct resource res;
 		pr_info("Initializing Coherency fabric\n");
+		of_address_to_resource(np, 0, &res);
+		coherency_phys_base = res.start;
 		coherency_base = of_iomap(np, 0);
 		coherency_cpu_base = of_iomap(np, 1);
 		set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ed..095b590 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -21,12 +21,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-/*
- * At this stage the secondary CPUs don't have acces yet to the MMU, so
- * we have to provide physical addresses
- */
-#define ARMADA_XP_CFB_BASE	     0xD0020200
-
 	__CPUINIT
 
 /*
@@ -35,15 +29,23 @@
  * startup
  */
 ENTRY(armada_xp_secondary_startup)
+	/* Add CPU to coherency fabric */
+	adr	r0, 1f
+	ldmia	r0, {r1, r2}
+	sub	r0, r0, r1
+	add	r2, r2, r0
+	ldr	r0, [r2]
 
 	/* Read CPU id */
 	mrc     p15, 0, r1, c0, c0, 5
 	and     r1, r1, #0xF
 
-	/* Add CPU to coherency fabric */
-	ldr     r0, =ARMADA_XP_CFB_BASE
-
 	bl	ll_set_cpu_coherent
 	b	secondary_startup
 
 ENDPROC(armada_xp_secondary_startup)
+
+	.align 2
+1:
+	.long	.
+	.long	coherency_phys_base
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue May 21 06:33:34 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 12:33:34 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at runtime
 if needed
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>

On Marvell platforms, the "internal registers" is a window of 1 MB of
the physical address space that contains all the registers for the
various peripherals of the SoC (timers, interrupt controllers, GPIO
controllers, Ethernet, etc.). The base address of this 1 MB window is
configurable, and this base address is configured using a register
that is itself part of this window.

All earlier families of Marvell EBU SoCs supported by Linux used
0xf1000000 as the base address of the internal registers window. For
some reason, early versions of the Marvell 370/XP platforms used
0xd0000000 as the base address. This base address is set up by the
bootloader. However, in order to keep as much physical address space
to address RAM below the 4 GB limit, we had to switch the base address
of the internal registers window back to 0xf1000000, and we wanted to
achieve that without breaking existing platforms, where the bootloader
was initially setting the base address to 0xd0000000. So the kernel is
responsible for switching to 0xf1000000 when needed.

One particular bit of a CP15 register has been chosen to indicate
whether we use an old bootloader (setting the address at 0xd0000000)
or a new bootloader (setting the address at 0xf1000000). In the
->map_io() function, when the bit is already set, there is nothing to
do, we are already using a new bootloader and internal registers are
at 0xf1000000.

However, when the bit is not set, we do a static mapping of the
register area that allows to change the internal register address, we
change this address, and set this bit.

Note that this mechanism also needs cooperation from the earlyprintk
addruart handler (in arch/arm/include/debug/mvebu.S). This is where
things get complex: the CP15 bit that has been chosen gets reset to
zero at the first call to the 'wfi' instruction. So it cannot be used
during the entire life of the system. Instead, whenever the ->map_io()
function has switched to the internal register space to the new
address, it sets a global variable 'mvebu_switched_regs', which the
earlyprintk reads. If it's true, then the move has already been done
and there is no need to read the CP15 register. If
'mvebu_switched_regs' is false, we are before the register move, so we
need to read the CP15 bit to find out whether we're being booted from
an old bootloader (which mapped the register space at 0xd0000000) or a
new bootloader (which mapped the register space at 0xf1000000).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
 arch/arm/boot/dts/armada-370.dtsi    |    2 +-
 arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++++++--
 arch/arm/mach-mvebu/armada-370-xp.c  |  104 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/armada-370-xp.h  |    2 +-
 5 files changed, 178 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 96a6bcd..1e7561e 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -33,7 +33,7 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&mpic>;
-		ranges = <0 0 0xd0000000 0x100000>;
+		ranges = <0 0 0xf1000000 0x100000>;
 
 		internal-regs {
 			compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index b2c1b5a..7ff9c1b 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -29,7 +29,7 @@
 	};
 
 	soc {
-		ranges = <0 0xd0000000 0x100000>;
+		ranges = <0 0xf1000000 0x100000>;
 		internal-regs {
 			system-controller at 18200 {
 				compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191af..dba702a 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -5,20 +5,85 @@
  *
  * Lior Amsalem <alior at marvell.com>
  * Gregory Clement <gregory.clement at free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000
+#define ARMADA_370_XP_UART_PHYS_BASE_OLD	0xd0012000
+#define ARMADA_370_XP_UART_PHYS_BASE_NEW	0xf1012000
+#define ARMADA_370_XP_UART_VIRT_BASE_OLD	0xfec12000
+#define ARMADA_370_XP_UART_VIRT_BASE_NEW	0xfebff000
 
 	.macro	addruart, rp, rv, tmp
-	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
-	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
-	orr	\rp, \rp, #0x00012000
-	orr	\rv, \rv, #0x00012000
+
+#ifndef ZIMAGE
+	/*
+	 * This loads the value of mvebu_switched_regs. We need a
+	 * little bit of gymnastic here to handle the fact that the
+	 * addruart code is duplicated in different places, and called
+	 * sometimes with the MMU disabled, sometimes the MMU enabled.
+	 *
+	 * Notice that when this earlyprintk code is linked into the
+	 * kernel decompressor (i.e ZIMAGE is defined), this code isn't
+	 * compiled. The reason is because the global mvebu_switched_regs
+	 * variable is not available in the decompressor code. At this
+	 * early stage, we simply test the CP15 bit (below) to know where
+	 * the internal registers are.
+	 */
+	adr	\rp, addruart_switched_regs_\@
+	ldr	\rv, [\rp]
+	sub	\rv, \rv, \rp
+	ldr	\rp, [\rp, #4]
+	sub	\tmp, \rp, \rv
+	ldr	\rp, [\tmp, #0]
+	cmp	\rp, #0
+
+	/* If we have already switched, then use the new register
+	   address */
+	bne	addruart_new_\@
+#endif
+
+	/*
+	 * We haven't switched the register location, so test the CP15
+	 * register bit to find whether we are:
+	 * - with an old bootloader setting the base address to
+	 *   0xd0000000
+	 * - with a new bootloader that has already set the
+	 *   base address to 0xf1000000
+	 * We adapt the physical address returned depending on the
+	 * value of this bit, but also the virtual address, because we
+	 * can't remap the old physical address and the new physical
+	 * address at the same location.
+	 */
+	mrc	p15, 0, \tmp, c5, c0, 0
+	and	\tmp, \tmp, #(1 << 11)
+	cmp	\tmp, #0
+	bne	addruart_new_\@
+
+addruart_old_\@:
+	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_OLD
+	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_OLD
+	b	addruart_out_\@
+addruart_new_\@:
+	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_NEW
+	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_NEW
+	b	addruart_out_\@
+
+#ifndef ZIMAGE
+	/*
+	 * Global variable mvebu_switched_regs not visible in the
+	 * decompressor code
+	 */
+	.align
+addruart_switched_regs_\@:
+	.long	.
+	.long	mvebu_switched_regs
+#endif
+
+addruart_out_\@:
 	.endm
 
 #define UART_SHIFT	2
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 90cc0e8..c56875e 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -29,8 +29,112 @@
 #include "common.h"
 #include "coherency.h"
 
+/*
+ * Note on the internal register address.
+ *
+ * On Marvell platforms, the "internal registers" is a window of 1 MB
+ * of the physical address space that contains all the registers for
+ * the various peripherals of the SoC (timers, interrupt controllers,
+ * GPIO controllers, Ethernet, etc.). The base address of this 1 MB
+ * window is configurable, and this base address is configured using a
+ * register that is itself part of this window.
+ *
+ * All earlier families of Marvell EBU SoCs supported by Linux used
+ * 0xf1000000 as the base address of the internal registers
+ * window. For some reason, early versions of the Marvell 370/XP
+ * platforms used 0xd0000000 as the base address. This base address is
+ * set up by the bootloader. However, in order to keep as much
+ * physical address space to address RAM below the 4 GB limit, we had
+ * to switch the base address of the internal registers window back to
+ * 0xf1000000, and we wanted to achieve that without breaking existing
+ * platforms, where the bootloader was initially setting the base
+ * address to 0xd0000000. So the kernel is responsible for switching
+ * to 0xf1000000 when needed.
+ *
+ * One particular bit of a CP15 register has been chosen to indicate
+ * whether we use an old bootloader (setting the address at
+ * 0xd0000000) or a new bootloader (setting the address at
+ * 0xf1000000). In the ->map_io() function, when the bit is already
+ * set, there is nothing to do, we are already using a new bootloader
+ * and internal registers are at 0xf1000000.
+ *
+ * However, when the bit is not set, we do a static mapping of the
+ * register area that allows to change the internal register address,
+ * we change this address, and set this bit.
+ *
+ * Note that this mechanism also needs cooperation from the
+ * earlyprintk addruart handler (in arch/arm/include/debug/mvebu.S)
+ * and the early secondary CPU initialization code (in
+ * arch/arm/mach-mvebu/headsmp.S).
+ */
+
+#define NEW_INTERNAL_REGS_ADDR  0xf1000000
+#define OLD_INTERNAL_REGS_ADDR  0xd0000000
+#define MBUS_OLD_PHYS_ADDR      (OLD_INTERNAL_REGS_ADDR + 0x20000)
+#define MBUS_OLD_VIRT_ADDR      0xfebfe000
+#define  MBUS_INTERNAL_REGS_ADDR      0x80
+
+/*
+ * We really want this variable to be part of the .data section,
+ * because it gets accessed by the earlyprintk code before BSS gets
+ * initialized to zero. This variable indicates whether the switch to
+ * the new register has taken place or not. It is needed because the
+ * CP15 bit used by the bootloader to tell the kernel where the
+ * registers are mapped is cleared to 0 at the first 'wfi'
+ * instruction. So we can't use it for the entire life of the system,
+ * and we instead use this boolean to indicate to the earlyprintk code
+ * that the switch has occured and it doesn't need to look at the CP15
+ * bit anymore.
+ */
+unsigned int __section(.data) mvebu_switched_regs = 0;
+
+/*
+ * Detect if we're running an old bootloader that has set the physical
+ * base address of internal registers to 0xd0000000
+ */
+static int armada_370_xp_has_old_bootloader(void)
+{
+	u32 val;
+	asm volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(val));
+	return !(val & BIT(11));
+}
+
 static void __init armada_370_xp_map_io(void)
 {
+	if (armada_370_xp_has_old_bootloader()) {
+		struct map_desc desc;
+		void __iomem *mbus = IOMEM(MBUS_OLD_VIRT_ADDR);
+
+		desc.virtual = MBUS_OLD_VIRT_ADDR;
+		desc.pfn     = __phys_to_pfn(MBUS_OLD_PHYS_ADDR);
+		desc.length  = PAGE_SIZE;
+		desc.type    = MT_DEVICE;
+
+		/*
+		 * Map the area that contains the registers that
+		 * allows to change the base address of internal
+		 * registers.
+		 */
+		iotable_init(&desc, 1);
+
+		/*
+		 * Change the physical base address of the
+		 * registers. From now on, and until
+		 * debug_ll_io_init() is called below, it is not
+		 * possible to do any print, because earlyprintk will
+		 * not work.
+		 */
+		writel(NEW_INTERNAL_REGS_ADDR, mbus + MBUS_INTERNAL_REGS_ADDR);
+	}
+
+	/*
+	 * Either the registers have been switched by the above code,
+	 * or the bootloader had already set the register space at the
+	 * right location. In both cases, tell the earlyprintk code it
+	 * can now use the new location.
+	 */
+	mvebu_switched_regs = 1;
+
 	debug_ll_io_init();
 }
 
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 585e147..ff9adc4 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -15,7 +15,7 @@
 #ifndef __MACH_ARMADA_370_XP_H
 #define __MACH_ARMADA_370_XP_H
 
-#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
+#define ARMADA_370_XP_REGS_PHYS_BASE	0xf1000000
 
 /* These defines can go away once mvebu-mbus has a DT binding */
 #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-- 
1.7.9.5



From kgene.kim at samsung.com  Tue May 21 06:52:36 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 21 May 2013 19:52:36 +0900
Subject: [GIT PULL] Samsung fixes-2 for v3.10
In-Reply-To: <20130521064034.GE20453@quad.lixom.net>
References: <519A5933.3040005@samsung.com>
 <20130521064034.GE20453@quad.lixom.net>
Message-ID: <102901ce5611$4df09bd0$e9d1d370$%kim@samsung.com>

Olof Johansson wrote:
> 
> On Tue, May 21, 2013 at 02:11:15AM +0900, Kukjin Kim wrote:
> > The following changes since commit
> f722406faae2d073cc1d01063d1123c35425939e:
> >
> >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> >
> > are available in the git repository at:
> >
> 
> > git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> > tags/samsung-fixes-2
> 
> What happened to the 4210 rev0 regression fixes from Tomasz? I would
> have expected them in this batch?
> 
Hmm... please see below:
https://patchwork.kernel.org/patch/2478431/

Since many conflicts at that time, the 11/13 patch missed in the last merge
window. Then, seems as Tomasz replied, he re-submitted after -rc1.

OK, I will pick that up into upcoming fixes for Samsung stuff.

> Might as well hold off this one until that is reviewed and ready, since
> it's silly to keep pulling one-patch branches. At least if that's
> happening
> this week.
> 
Yeah, agreed. Let me sort out other fixes within a couple of days.

Please kindly ignore this pull request :-)

Thanks.

- Kukjin



From linux at arm.linux.org.uk  Tue May 21 06:59:59 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 21 May 2013 11:59:59 +0100
Subject: [PATCH] include/linux/posix_acl.h: need 'return NULL' when
 BUG(), if neither CONFIG_BUG nor HAVE_ARCH_BUG is defined.
In-Reply-To: <519AD33D.1030106@asianux.com>
References: <5199DBE2.5080707@asianux.com>
 <97dada79-cd78-4799-8f18-ed2bf8eee508@email.android.com>
 <20130520163118.GX18614@n2100.arm.linux.org.uk>
 <519AD33D.1030106@asianux.com>
Message-ID: <20130521105959.GZ18614@n2100.arm.linux.org.uk>

On Tue, May 21, 2013 at 09:51:57AM +0800, Chen Gang wrote:
> On 05/21/2013 12:31 AM, Russell King - ARM Linux wrote:
> > On Mon, May 20, 2013 at 07:40:24AM -0700, Eric W. Biederman wrote:
> >> Seriously?  The correct fix it would seem is to give a useful default BUG
> >> definition.  Say *NULL.
> > 
> > Absolutely.
> > 
> > The real question is... how is this happening.  I've seen it occasionally
> > in the randconfig builds - though I don't have any logs to hand which
> > show that in the build system at the moment.  So, looking at the files:
> > 
> 
> Maybe it is my fault for the incorrect configuration.
> 
> My operation:
>   make EXTRA_CFLAGS=-W ARCH=arm randconfig
>   make EXTRA_CFLAGS=-W ARCH=arm menuconfig
>     set 'arm-linux-gnu-' as cross compiler prefix.
>     select "MMU-based Paged Memory" in "System Type".
>     select "Samsung S5PV210/S5PC110" in "ARM System type"
>   make EXTRA_CFLAGS=-W ARCH=arm
>   ...
> 
> In menuconfig, I do not touch the "S5PV210 Machines" or "S5PC110
> Machines" in "System Type", and no machines will be chosen as default.

You know, telling us that you're using a random configuration to produce
a problem and not providing the actual configuration file is utterly
insane.  How many iterations do you think it might take to generate a
random configuration which shows the same problem you're seeing?


From geert at linux-m68k.org  Tue May 21 07:07:58 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Tue, 21 May 2013 13:07:58 +0200
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <519B278B.6030708@asianux.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
 <519B278B.6030708@asianux.com>
Message-ID: <CAMuHMdWqDDe4gtjO8A2ds_46NQ_XGkVFj9TqJPGWtAtr7_ef8A@mail.gmail.com>

On Tue, May 21, 2013 at 9:51 AM, Chen Gang <gang.chen at asianux.com> wrote:
> On 05/21/2013 02:57 PM, Geert Uytterhoeven wrote:
>> On Tue, May 21, 2013 at 5:15 AM, Chen Gang <gang.chen at asianux.com> wrote:
>>>> >> I think it would be better if we added a something like
>>>> >> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
>>>> >> like x86 can then select the former, and we can remove the long list of
>>>> >> architectures from the current option.
>>> >
>>> > I guess your meaning is:
>>> >
>>> >   under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
>>> >   So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.
>>> >
>>> > Is it correct ?
>> No, you missed "and we can remove the long list of architectures from the
>> current option".
>>
>
> OK, thanks.
>
> Is it correct: "it is unnecessary to add 'screen_info' to the code, for
> arm64 will never support 'VGA_CONSOLE'" ?

On arm (not (yet?) arm64), drivers/video/console/dummycon.c also uses
screen_info. The default text mode resolution may come from atags.

>>> > If so, I recommend to add depend item for VGA_CONSOLE directly:
>> I strongly support CONFIG_HAVE_VGA_CONSOLE.
>
> For me, I still recommend add 'ARM64' in the long list of architectures
> for 'VGA_CONSOLE', I have 3 reasons, please check:
>
> a. current implementation only changes one area which only related with
> arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
> touch many multiple platforms dependency, at least we need discuss about
> it with multiple platforms guys for it, firstly.

Sure. But this can be one cleanup patch.

> b. We can find some cases to use CONFIG_HAVE_* as dpend on, but I can
> not find any cases which let CONFIG_'samename' depend on
> CONFIG_HAVE_'samename'.

A similar mechanism is used for PC-style floppy support, but the naming
is different, cfr. drivers/block/Kconfig:

config BLK_DEV_FD
        tristate "Normal floppy disk support"
        depends on ARCH_MAY_HAVE_PC_FDC

so perhaps ARCH_MAY_HAVE_VGA?

PARPORT_PC could use the same mechanism.

> c. The original way still has effect, although it seems not quit
> beautiful, but it is correct and still clear for readers, it is still
> sustainable.

Most/every new architecture needs to add a depend to it.

BTW, I should have done this when sending out the patch to add CRIS to the
list of dependencies...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From gang.chen at asianux.com  Tue May 21 07:16:11 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 19:16:11 +0800
Subject: [PATCH] include/linux/posix_acl.h: need 'return NULL' when BUG(), 
 if neither CONFIG_BUG nor HAVE_ARCH_BUG is defined.
In-Reply-To: <20130521105959.GZ18614@n2100.arm.linux.org.uk>
References: <5199DBE2.5080707@asianux.com>
 <97dada79-cd78-4799-8f18-ed2bf8eee508@email.android.com>
 <20130520163118.GX18614@n2100.arm.linux.org.uk>
 <519AD33D.1030106@asianux.com>
 <20130521105959.GZ18614@n2100.arm.linux.org.uk>
Message-ID: <519B577B.8080204@asianux.com>

On 05/21/2013 06:59 PM, Russell King - ARM Linux wrote:
> On Tue, May 21, 2013 at 09:51:57AM +0800, Chen Gang wrote:
>> On 05/21/2013 12:31 AM, Russell King - ARM Linux wrote:
>>> On Mon, May 20, 2013 at 07:40:24AM -0700, Eric W. Biederman wrote:
>>>> Seriously?  The correct fix it would seem is to give a useful default BUG
>>>> definition.  Say *NULL.
>>>
>>> Absolutely.
>>>
>>> The real question is... how is this happening.  I've seen it occasionally
>>> in the randconfig builds - though I don't have any logs to hand which
>>> show that in the build system at the moment.  So, looking at the files:
>>>
>>
>> Maybe it is my fault for the incorrect configuration.
>>
>> My operation:
>>   make EXTRA_CFLAGS=-W ARCH=arm randconfig
>>   make EXTRA_CFLAGS=-W ARCH=arm menuconfig
>>     set 'arm-linux-gnu-' as cross compiler prefix.
>>     select "MMU-based Paged Memory" in "System Type".
>>     select "Samsung S5PV210/S5PC110" in "ARM System type"
>>   make EXTRA_CFLAGS=-W ARCH=arm
>>   ...
>>
>> In menuconfig, I do not touch the "S5PV210 Machines" or "S5PC110
>> Machines" in "System Type", and no machines will be chosen as default.
> 
> You know, telling us that you're using a random configuration to produce
> a problem and not providing the actual configuration file is utterly
> insane.  How many iterations do you think it might take to generate a
> random configuration which shows the same problem you're seeing?
> 
> 

Oh, it is my fault for my original reply (it is another issue which
also need further discussed)

But for current issue, we can repeat it only in menuconfig, unset " >
General setup > Configure standard kernel features (expert users) >
BUG() Support ", it will report related warnings.

For arm architecture, allmodconfig

  make ARCH=arm  allmodconfig
  make ARCH=arm  menuconfig
    set "arm-linux-gnu-" as cross compiler prefix.
    unset " > General setup > Configure standard kernel features (expert users) > BUG() Support "
  make ARCH=arm
  ...
  kernel/sched/core.c:2353:1: warning: control reaches end of non-void function [-Wreturn-type]
  mm/bootmem.c:386:1: warning: control reaches end of non-void function [-Wreturn-type]
  include/linux/posix_acl.h:108:1: warning: control reaches end of non-void function [-Wreturn-type]
  ...

For x86 architecture, allmodconfig:

  make allmodconfig
  make menuconfig
    unset " > General setup > Configure standard kernel features (expert users) > BUG() Support "
  make ARCH=arm
  ...
  arch/x86/kvm/x86.c:4298:5: warning: ?exchanged? may be used uninitialized in this function [-Wuninitialized]
  kernel/sched/core.c:2353:1: warning: control reaches end of non-void function [-Wreturn-type]
  mm/mempolicy.c:1755:1: warning: control reaches end of non-void function [-Wreturn-type]
  include/linux/posix_acl.h:108:1: warning: control reaches end of non-void function [-Wreturn-type]
  ...


So, we need fix the generic bug.h code, it is not arm specific.


Thanks.-- 
Chen Gang

Asianux Corporation


From linus.walleij at linaro.org  Tue May 21 07:17:11 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 May 2013 13:17:11 +0200
Subject: [GIT PULL] ux500 fixes for v3.10-rc1+
In-Reply-To: <20130521064858.GH20453@quad.lixom.net>
References: <CACRpkdY2Pd9o+PMmabKs5Zj56GRsGtva8eQENgu8w-VjZy2hHw@mail.gmail.com>
 <20130521064858.GH20453@quad.lixom.net>
Message-ID: <CACRpkdb=Msn4qgaTjL-FrNvB5PPnW85cj_qpVCt-PpLhmKgq7g@mail.gmail.com>

On Tue, May 21, 2013 at 8:48 AM, Olof Johansson <olof at lixom.net> wrote:

>> Emilio L?pez (1):
>
> Broken UTF-8 cut-and-paste? Looks alright in the git contents though.

I try all the time to get this right and I *think* I got it right in
git atleast.

When git am does not scream (after using gedit and setting
LANG=en_US.UTF-8 in the terminal) it's usually right ...

The remaining problems in git request-pull I blame on either
me doing that in a non-UTF-8 terminal or gmail's cutnpaste
problems or something....

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Tue May 21 07:25:16 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 May 2013 13:25:16 +0200
Subject: [PATCH 1/6] pinctrl: exynos: Add support for set_irq_wake of
 wake-up EINTs
In-Reply-To: <1368807872-2601-2-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-2-git-send-email-t.figa@samsung.com>
Message-ID: <CACRpkdZReXCt_pcMPvuyGBc09UPWN0MjMmJBOokJRjBaf-m4YA@mail.gmail.com>

On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa <t.figa at samsung.com> wrote:

> This patch adds support of IRQ wake-up ability configuration for
> wake-up EINTs on Exynos SoCs.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Patch applied on my fixes branch for v3.10

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 21 07:27:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 May 2013 13:27:12 +0200
Subject: [PATCH 2/6] ARM: EXYNOS: Fix EINT wake-up mask configuration when
 pinctrl is used
In-Reply-To: <1368807872-2601-3-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-3-git-send-email-t.figa@samsung.com>
Message-ID: <CACRpkdZ51KBZQTSR7CpqknnQZ8LU+P2p=FFAcUOCV3wXP5foMg@mail.gmail.com>

On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa <t.figa at samsung.com> wrote:

> On DT-enabled systems pinctrl-exynos driver is responsible for handling
> of wake-up EINT interrupts. This patch adjusts wake-up mask
> configuration code to take wake-up mask value from pinctrl-exynos driver
> on DT-enabled systems.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Patch applied to my fixes branch for v3.10.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 21 07:29:23 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 May 2013 13:29:23 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <1666561.1GujhmlVbA@flatron>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <4241187.TFCdy2kUT6@flatron>
 <CAD=FV=XcmzogZc9mWQ+FSr9dg9jML-ACUJY2M2-s+_rBw9gMzQ@mail.gmail.com>
 <1666561.1GujhmlVbA@flatron>
Message-ID: <CACRpkdbVnPhTMKDBtPNAka_V8H-2w2gK7prw9LVPRk_P7NMt7w@mail.gmail.com>

On Fri, May 17, 2013 at 11:07 PM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> On Friday 17 of May 2013 13:56:39 Doug Anderson wrote:
>> I wouldn't be opposed to a re-spin to address some of the above, but I
>> also won't object to this landing and remaining issues being addressed
>> in future patches.  This patch definitely does make things better and
>> no worse.  :)
>
> Let's see. If nobody takes this until Monday, which is very likely, I will
> send new version.

I applied 1 & 2 so pls repost your updated patches 3,4,5,6 on
monday and let's continue fixing.

Yours,
Linus Walleij


From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 07:40:04 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 13:40:04 +0200
Subject: [RFC/PATCH v2 0/2] R-Car GPIO DT bindings
Message-ID: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Hello,

Here's the second version of the gpio-rcar driver DT bindings. I've tested the
patches on the Marzen board (r8a7779).

Once again I'd appreciate feedback on the DT bindings. I'm particularly
wondering whether getting the number of lines through the gpio-ranges property
instead of using a dedicated #gpio-lines property as in v1 is a good idea.

Changes since v1:

- Initialize the gpiochip dev field at probe time.
- Add the gpio-ranges property.
- Remove the #gpio-lines property. The number of lines is now passed through
  the gpio-ranges property.

Laurent Pinchart (2):
  gpio-rcar: Make the platform data gpio_base field signed
  gpio-rcar: Add DT support

 .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 52 +++++++++++++++++
 drivers/gpio/gpio-rcar.c                           | 66 ++++++++++++++++++----
 include/linux/platform_data/gpio-rcar.h            |  2 +-
 3 files changed, 109 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt

-- 
Regards,

Laurent Pinchart



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 07:40:05 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 13:40:05 +0200
Subject: [RFC/PATCH v2 1/2] gpio-rcar: Make the platform data gpio_base field
 signed
In-Reply-To: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369136406-23800-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

The gpio_base field is used to specify the desired GPIO base for the
GPIO controller. The GPIO core can automatically allocate a GPIO number
range when the base is set to -1. To make this possible, make the field
signed.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
 include/linux/platform_data/gpio-rcar.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index cc472f6..fb2c718 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -17,7 +17,7 @@
 #define __GPIO_RCAR_H__
 
 struct gpio_rcar_config {
-	unsigned int gpio_base;
+	int gpio_base;
 	unsigned int irq_base;
 	unsigned int number_of_pins;
 	const char *pctl_name;
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 07:40:06 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 13:40:06 +0200
Subject: [RFC/PATCH v2 2/2] gpio-rcar: Add DT support
In-Reply-To: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369136406-23800-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add DT bindings for the gpio-rcar driver and read the device
configuration from the DT node at probe time if available.

Cc: devicetree-discuss at lists.ozlabs.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 52 +++++++++++++++++
 drivers/gpio/gpio-rcar.c                           | 66 ++++++++++++++++++----
 2 files changed, 108 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
new file mode 100644
index 0000000..46d76a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -0,0 +1,52 @@
+* Renesas R-Car GPIO Controller
+
+Required Properties:
+
+  - compatible: should be one of the following.
+    - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
+    - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
+    - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
+    - "renesas,gpio-rcar": for generic R-Car GPIO controller.
+
+  - reg: Base address and length of each memory resource used by the GPIO
+    controller hardware module.
+
+  - interrupt-parent: phandle of the parent interrupt controller.
+  - interrupts: Interrupt specifier for the controllers interrupt.
+
+  - gpio-controller: Marks the device node as a gpio controller.
+  - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+    cell is used to specify optional parameters as bit flags. Only the GPIO
+    active low flag (bit 0) is currently supported.
+  - gpio-ranges: Range of pins managed by the GPIO controller as a 4-cells
+    tuple using the following syntax.
+
+    <[phandle of the pin controller node]
+     0
+     [index of the first pin]
+     [number of pins]>
+
+Please refer to gpio.txt in this directory for details of the common GPIO
+bindings used by client devices.
+
+Example: R8A7779 (R-Car H1) GPIO controller nodes
+
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc40000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 141 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 32>;
+	};
+	...
+	gpio6: gpio at ffc46000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc46000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 147 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 192 9>;
+	};
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 0f3d647..c153837 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -50,6 +50,8 @@ struct gpio_rcar_priv {
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
 
+#define RCAR_MAX_GPIO_PER_BANK		32
+
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
 	return ioread32(p->base + offs);
@@ -258,9 +260,39 @@ static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
 	.map	= gpio_rcar_irq_domain_map,
 };
 
+static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
+{
+	struct gpio_rcar_config *pdata = p->pdev->dev.platform_data;
+#ifdef CONFIG_OF
+	struct device_node *np = p->pdev->dev.of_node;
+	struct of_phandle_args args;
+	int ret;
+#endif
+
+	if (pdata)
+		p->config = *pdata;
+#ifdef CONFIG_OF
+	else if (np) {
+		ret = of_parse_phandle_with_args(np, "gpio-ranges",
+				"#gpio-range-cells", 0, &args);
+		p->config.number_of_pins = ret == 0 && args.args_count == 3
+					 ? args.args[2]
+					 : RCAR_MAX_GPIO_PER_BANK;
+		p->config.gpio_base = -1;
+	}
+#endif
+
+	if (p->config.number_of_pins == 0 ||
+	    p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
+		dev_warn(&p->pdev->dev,
+			 "Invalid number of gpio lines %u, using %u\n",
+			 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
+		p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
+	}
+}
+
 static int gpio_rcar_probe(struct platform_device *pdev)
 {
-	struct gpio_rcar_config *pdata = pdev->dev.platform_data;
 	struct gpio_rcar_priv *p;
 	struct resource *io, *irq;
 	struct gpio_chip *gpio_chip;
@@ -275,14 +307,14 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 		goto err0;
 	}
 
-	/* deal with driver instance configuration */
-	if (pdata)
-		p->config = *pdata;
-
 	p->pdev = pdev;
-	platform_set_drvdata(pdev, p);
 	spin_lock_init(&p->lock);
 
+	/* Get device configuration from DT node or platform data. */
+	gpio_rcar_parse_pdata(p);
+
+	platform_set_drvdata(pdev, p);
+
 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 
@@ -309,6 +341,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 	gpio_chip->set = gpio_rcar_set;
 	gpio_chip->to_irq = gpio_rcar_to_irq;
 	gpio_chip->label = name;
+	gpio_chip->dev = &pdev->dev;
 	gpio_chip->owner = THIS_MODULE;
 	gpio_chip->base = p->config.gpio_base;
 	gpio_chip->ngpio = p->config.number_of_pins;
@@ -355,10 +388,12 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 				 p->config.irq_base, ret);
 	}
 
-	ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
-				     gpio_chip->base, gpio_chip->ngpio);
-	if (ret < 0)
-		dev_warn(&pdev->dev, "failed to add pin range\n");
+	if (p->config.pctl_name) {
+		ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
+					     gpio_chip->base, gpio_chip->ngpio);
+		if (ret < 0)
+			dev_warn(&pdev->dev, "failed to add pin range\n");
+	}
 
 	return 0;
 
@@ -381,11 +416,22 @@ static int gpio_rcar_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id gpio_rcar_of_table[] = {
+	{
+		.compatible = "renesas,gpio-rcar",
+	},
+};
+
+MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
+#endif
+
 static struct platform_driver gpio_rcar_device_driver = {
 	.probe		= gpio_rcar_probe,
 	.remove		= gpio_rcar_remove,
 	.driver		= {
 		.name	= "gpio_rcar",
+		.of_match_table = of_match_ptr(gpio_rcar_of_table),
 	}
 };
 
-- 
1.8.1.5



From gang.chen at asianux.com  Tue May 21 07:40:52 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 21 May 2013 19:40:52 +0800
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <CAMuHMdWqDDe4gtjO8A2ds_46NQ_XGkVFj9TqJPGWtAtr7_ef8A@mail.gmail.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
 <519B278B.6030708@asianux.com>
 <CAMuHMdWqDDe4gtjO8A2ds_46NQ_XGkVFj9TqJPGWtAtr7_ef8A@mail.gmail.com>
Message-ID: <519B5D44.70506@asianux.com>

On 05/21/2013 07:07 PM, Geert Uytterhoeven wrote:
> On Tue, May 21, 2013 at 9:51 AM, Chen Gang <gang.chen at asianux.com> wrote:
>> > On 05/21/2013 02:57 PM, Geert Uytterhoeven wrote:
>>> >> On Tue, May 21, 2013 at 5:15 AM, Chen Gang <gang.chen at asianux.com> wrote:
>>>>>>> >>>> >> I think it would be better if we added a something like
>>>>>>> >>>> >> CONFIG_HAVE_VGA_CONSOLE, which VGA_CONSOLE can then depend on. Architectures
>>>>>>> >>>> >> like x86 can then select the former, and we can remove the long list of
>>>>>>> >>>> >> architectures from the current option.
>>>>> >>> >
>>>>> >>> > I guess your meaning is:
>>>>> >>> >
>>>>> >>> >   under arm64, actually, need not support 'VGA_CONSOLE', and 'screen_info' is useless.
>>>>> >>> >   So better to define 'CONFIG_HAVE_VGA_CONSOLE' which 'VGA_CONSOLE' can depend on it, and in arm64, we do not define CONFIG_HAVE_VGA_CONSOLE.
>>>>> >>> >
>>>>> >>> > Is it correct ?
>>> >> No, you missed "and we can remove the long list of architectures from the
>>> >> current option".
>>> >>
>> >
>> > OK, thanks.
>> >
>> > Is it correct: "it is unnecessary to add 'screen_info' to the code, for
>> > arm64 will never support 'VGA_CONSOLE'" ?
> On arm (not (yet?) arm64), drivers/video/console/dummycon.c also uses
> screen_info. The default text mode resolution may come from atags.
> 

Oh, really it is, we need consider them both.


>>>>> >>> > If so, I recommend to add depend item for VGA_CONSOLE directly:
>>> >> I strongly support CONFIG_HAVE_VGA_CONSOLE.
>> >
>> > For me, I still recommend add 'ARM64' in the long list of architectures
>> > for 'VGA_CONSOLE', I have 3 reasons, please check:
>> >
>> > a. current implementation only changes one area which only related with
>> > arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
>> > touch many multiple platforms dependency, at least we need discuss about
>> > it with multiple platforms guys for it, firstly.
> Sure. But this can be one cleanup patch.
> 

Hmm..., it seems so, but I think we'd better to discuss it with the
'final applier' firstly.


>> > b. We can find some cases to use CONFIG_HAVE_* as dpend on, but I can
>> > not find any cases which let CONFIG_'samename' depend on
>> > CONFIG_HAVE_'samename'.
> A similar mechanism is used for PC-style floppy support, but the naming
> is different, cfr. drivers/block/Kconfig:
> 
> config BLK_DEV_FD
>         tristate "Normal floppy disk support"
>         depends on ARCH_MAY_HAVE_PC_FDC
> 
> so perhaps ARCH_MAY_HAVE_VGA?
> 
> PARPORT_PC could use the same mechanism.
> 

Oh, really, it is !!

Hmm.., most of current machines do not have floppy, now, and will be
less and less in the future, it has to use the variables in this way to
avoid a very very very long list (not only include architectures, but
also include the each features companition) !!

But for VIDEO_CONSOL, most of machines need it, and will be more and
more in the future (maybe arm64 will also support it, too, in the future).

So...


>> > c. The original way still has effect, although it seems not quit
>> > beautiful, but it is correct and still clear for readers, it is still
>> > sustainable.
> Most/every new architecture needs to add a depend to it.
> 
> BTW, I should have done this when sending out the patch to add CRIS to the
> list of dependencies...

I suggest better to discuss it with the 'final applier' firstly.

Good Luck !!


Thanks.
-- 
Chen Gang

Asianux Corporation


From linus.walleij at stericsson.com  Tue May 21 07:44:25 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 21 May 2013 13:44:25 +0200
Subject: [PATCH] ARM: ux500: build ccu8540 device tree blob
Message-ID: <1369136665-17226-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This makes sure the new ccu8540 DTB file is generated by
the build system.

Cc: Lee Jones <lee.jones at linaro.org>
Cc: Gabriel Fernandez <gabriel.fernandez.st at gmail.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..77ea6d4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -158,6 +158,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
 	hrefprev60.dtb \
 	hrefv60plus.dtb \
+	ccu8540.dtb \
 	ccu9540.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a7740-armadillo800eva.dtb \
-- 
1.7.11.3



From kishon at ti.com  Tue May 21 07:53:46 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Tue, 21 May 2013 17:23:46 +0530
Subject: [PATCH 6/6] ARM: OMAP2+: Remove omap4 ocp2scp pdata
In-Reply-To: <20130517191803.468.32800.stgit@localhost>
References: <20130517191304.468.73487.stgit@localhost>
 <20130517191803.468.32800.stgit@localhost>
Message-ID: <519B604A.9040300@ti.com>

On Saturday 18 May 2013 12:48 AM, Tony Lindgren wrote:
> This is omap4+ only and no longer needed as omap4+ can be booted
> using device tree.
>
> Also remove the related pdata handling from the driver and the
> now unneeded platform_data/omap_ocp2scp.h.
>
> Cc: Kishon Vijay Abraham I <kishon at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Olof Johansson <olof at lixom.net>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Reviewed-by: Kishon Vijay Abraham I <kishon at ti.com>

Thanks
Kishon


From linus.walleij at stericsson.com  Tue May 21 07:56:42 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 21 May 2013 13:56:42 +0200
Subject: [PATCH] ARM: ux500: fix typo in STUIB device tree
Message-ID: <1369137402-17580-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The Rohm vendor name was twisted in the STUIB device tree
include file. Fix it up.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/stuib.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 7fa10a7..0fdb259 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -53,25 +53,25 @@
 
 		i2c at 80110000 {
 			bu21013_tp at 0x5c {
-				compatible = "rhom,bu21013_tp";
+				compatible = "rohm,bu21013_tp";
 				reg = <0x5c>;
 				touch-gpio = <&gpio2 20 0x4>;
 				avdd-supply = <&ab8500_ldo_aux1_reg>;
 
-				rhom,touch-max-x = <384>;
-				rhom,touch-max-y = <704>;
-				rhom,flip-y;
+				rohm,touch-max-x = <384>;
+				rohm,touch-max-y = <704>;
+				rohm,flip-y;
 			};
 
 			bu21013_tp at 0x5d {
-				compatible = "rhom,bu21013_tp";
+				compatible = "rohm,bu21013_tp";
 				reg = <0x5d>;
 				touch-gpio = <&gpio2 20 0x4>;
 				avdd-supply = <&ab8500_ldo_aux1_reg>;
 
-				rhom,touch-max-x = <384>;
-				rhom,touch-max-y = <704>;
-				rhom,flip-y;
+				rohm,touch-max-x = <384>;
+				rohm,touch-max-y = <704>;
+				rohm,flip-y;
 			};
 		};
 	};
-- 
1.7.11.3



From lee.jones at linaro.org  Tue May 21 08:09:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 May 2013 13:09:57 +0100
Subject: [PATCH] ARM: ux500: fix typo in STUIB device tree
In-Reply-To: <1369137402-17580-1-git-send-email-linus.walleij@stericsson.com>
References: <1369137402-17580-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130521120957.GA9471@gmail.com>

On Tue, 21 May 2013, Linus Walleij wrote:

> From: Linus Walleij <linus.walleij at linaro.org>
> 
> The Rohm vendor name was twisted in the STUIB device tree
> include file. Fix it up.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/stuib.dtsi | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)

Acked-by: Lee Jones <lee.jones at linaro.org>

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:22 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:22 +0200
Subject: [PATCH v4 01/21] sh-pfc: Remove support for platform data
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Platform data isn't used, support can thus be removed.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 drivers/pinctrl/sh-pfc/core.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 3b2fd43..ac45084 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -354,8 +354,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
 	struct sh_pfc *pfc;
 	int ret;
 
-	info = pdev->id_entry->driver_data
-	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
+	info = (void *)pdev->id_entry->driver_data;
 	if (info == NULL)
 		return -ENODEV;
 
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:21 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:21 +0200
Subject: [PATCH v4 00/21] SH pinctrl DT support
Message-ID: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Hello,

Here's the fourth version of the SuperH and SH Mobile pin controllers (PFC) DT
support patch set.

The patches are based on tags/renesas-next-20130513 from Simon's tree
(git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git), the R-Car
GPIO DT bindings proposal ("[RFC/PATCH v2 0/2] R-Car GPIO DT bindings") and the
marzen-reference ethernet patches ("[PATCH v2 0/4] marzen-reference ethernet
patches"). The result is available in my tree at

        git://linuxtv.org/pinchartl/fbdev.git pinmux/3.9/dt

The series is pretty self-explanatory. DT bindings are added in patch 02/21,
and the following patches gradually move SoC code and board code over to the
device tree for the armadilla800eva-reference, kzm9g-reference and
marzen-reference boards. The code has been tested on the three boards, but
armadillo800eva has received less testing as it can't be booted all the way to
userspace with network support due to missing DT bindings.

Comments will be very appreciated on the DT bindings (02/21). Points I'm a bit
unsure about include:

- Should the driver support pin configuration subnodes as currently
  implemented, or should the subnodes be promoted to regular pin configuration
  nodes, with clients referencing multiple nodes ?
- Should the driver allow mixing function and configuration properties in a pin
  configuration node as currently implemented, or should it restrict the pin
  configuration nodes to either a function or one (or more) configuration(s) ?
- Should we specify common bindings for pinconf-generic instead of using
  Renesas-specific properties ? (If the answer to this question is yes, please
  help :-)).

Changes since v3:

- Fixed the GPIO flags description in the DT bindings documentation
- Mention the gpio-rcar driver in the DT bindings documentation for platforms
  that use it
- Removed unneeded #ifdef CONFIG_OF...#endif
- Removed unused support for platform data
- Simplified error path in sh_pfc_dt_node_to_map()
- Added gpio-ranges for r8a7778, r8a7779 and r8a7790

Changes since v2:

- Added pin configuration properties
- Rewrote all arch changes

Changes since v1:

- Fixed gpio cell number 2 documentation
- Added missing gpio-controller and #gpio-cells properties to r8a7740 DT
- Split kzm9g DT patch into SoC and board patches
- Dropped pinctrl mappings move to DT


Laurent Pinchart (21):
  sh-pfc: Remove support for platform data
  sh-pfc: Add DT support
  ARM: shmobile: r8a73a4: Add pin control device to device tree
  ARM: shmobile: r8a7740: Add pin control device to device tree
  ARM: shmobile: r8a7778: Add pin control device to device tree
  ARM: shmobile: r8a7778: Add GPIO controller devices to device tree
  ARM: shmobile: r8a7779: Add pin control device to device tree
  ARM: shmobile: r8a7779: Add GPIO controller devices to device tree
  ARM: shmobile: r8a7790: Add pin control device to device tree
  ARM: shmobile: r8a7790: Add GPIO controller devices to device tree
  ARM: shmobile: sh7372: Add pin control device to device tree
  ARM: shmobile: sh73a0: Add pin control device to device tree
  ARM: shmobile: armadillo-reference: Move pinctrl mappings to device
    tree
  ARM: shmobile: armadillo-reference: Add st1232 pin mappings
  ARM: shmobile: armadillo-reference: Move st1232 reset GPIO to DT
  ARM: shmobile: armadillo-reference: Add LED1-LED4 to the device tree
  ARM: shmobile: kzm9g-reference: Move pinctrl mappings to device tree
  ARM: shmobile: kzm9g-reference: Move SDHI regulators to DT
  ARM: shmobile: kzm9g-reference: Add LED1-LED4 to the device tree
  ARM: shmobile: marzen-reference: Move pinctrl mappings to device tree
  ARM: shmobile: marzen-reference: Add LED2-LED4 to the device tree

 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       | 155 +++++++++++++
 arch/arm/boot/dts/r8a73a4.dtsi                     |   7 +
 .../boot/dts/r8a7740-armadillo800eva-reference.dts |  33 +++
 arch/arm/boot/dts/r8a7740.dtsi                     |   8 +
 arch/arm/boot/dts/r8a7778.dtsi                     |  56 +++++
 arch/arm/boot/dts/r8a7779-marzen-reference.dts     |  48 ++++
 arch/arm/boot/dts/r8a7779.dtsi                     |  76 +++++++
 arch/arm/boot/dts/r8a7790.dtsi                     |  66 ++++++
 arch/arm/boot/dts/sh7372.dtsi                      |   8 +
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts       |  89 +++++++-
 arch/arm/boot/dts/sh73a0.dtsi                      |   8 +
 .../board-armadillo800eva-reference.c              |  18 +-
 arch/arm/mach-shmobile/board-kzm9g-reference.c     |  47 ----
 arch/arm/mach-shmobile/board-marzen-reference.c    |  28 ---
 drivers/pinctrl/sh-pfc/core.c                      |  60 ++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   | 242 +++++++++++++++++++++
 16 files changed, 853 insertions(+), 96 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

-- 
Regards,

Laurent Pinchart



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:24 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:24 +0200
Subject: [PATCH v4 03/21] ARM: shmobile: r8a73a4: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-4-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a73a4 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a73a4.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fde2a33..358898c 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -91,4 +91,11 @@
 		interrupt-parent = <&gic>;
 		interrupts = <0 69 4>;
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-r8a73a4";
+		reg = <0xe6050000 0x9000>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:23 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:23 +0200
Subject: [PATCH v4 02/21] sh-pfc: Add DT support
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.

Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.

Cc: devicetree-discuss at lists.ozlabs.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       | 155 +++++++++++++
 drivers/pinctrl/sh-pfc/core.c                      |  59 ++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   | 242 +++++++++++++++++++++
 3 files changed, 455 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 0000000..7651a90
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,155 @@
+* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
+
+The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
+SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
+
+
+Pin Control
+-----------
+
+Required Properties:
+
+  - compatible: should be one of the following.
+    - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
+    - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+    - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
+    - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+    - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+    - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
+    - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+
+  - reg: Base address and length of each memory resource used by the pin
+    controller hardware module.
+
+Optional properties:
+
+  - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
+    otherwise. Should be 3.
+
+The PFC node also acts as a container for pin configuration nodes. Please refer
+to pinctrl-bindings.txt in this directory for the definition of the term "pin
+configuration node" and for the common pinctrl bindings used by client devices.
+
+Each pin configuration node represents a desired configuration for a pin, a
+pin group, or a list of pins or pin groups. The configuration can include the
+function to select on those pin(s) and pin configuration parameters (such as
+pull-up and pull-down).
+
+Pin configuration nodes contain pin configuration properties, either directly
+or grouped in child subnodes. Both pin muxing and configuration parameters can
+be grouped in that way and referenced as a single pin configuration node by
+client devices.
+
+A configuration node or subnode must reference at least one pin (through the
+pins or pin groups properties) and contain at least a function or one
+configuration parameter. When the function is present only pin groups can be
+used to reference pins.
+
+All pin configuration nodes and subnodes names are ignored. All of those nodes
+are parsed through phandles and processed purely based on their content.
+
+Pin Configuration Node Properties:
+
+- renesas,pins : An array of strings, each string containing the name of a pin.
+- renesas,groups : An array of strings, each string containing the name of a pin
+  group.
+
+- renesas,function: A string containing the name of the function to mux to the
+  pin group(s) specified by the renesas,groups property
+
+  Valid values for pin, group and function names can be found in the group and
+  function arrays of the PFC data file corresponding to the SoC
+  (drivers/pinctrl/sh-pfc/pfc-*.c)
+
+- renesas,pull-up: An integer representing the pull-up strength to be applied
+  to all pins specified by the renesas,pins and renesas-groups properties.
+  0 disables the pull-up, 1 enables it. Other values should not be used.
+- renesas,pull-down: An integer representing the pull-down strength to be
+  applied to all pins specified by the renesas,pins and renesas-groups
+  properties. 0 disables the pull-down, 1 enables it. Other values should not
+  be used.
+
+
+GPIO
+----
+
+On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
+node.
+
+Required Properties:
+
+  - gpio-controller: Marks the device node as a gpio controller.
+
+  - #gpio-cells: Should be 2. The first cell is the pin number and the second
+    cell is used to specify optional parameters as bit flags. Only the GPIO
+    active low flag (bit 0) is currently supported.
+
+The syntax of the gpio specifier used by client nodes should be the following
+with values derived from the SoC user manual.
+
+  <[phandle of the gpio controller node]
+   [pin number within the gpio controller]
+   [flags]>
+
+On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
+Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+for documentation of the GPIO device tree bindings on those platforms.
+
+
+Examples
+--------
+
+Example 1: SH73A0 (SH-Mobile AG5) pin controller node
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-sh73a0";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+Example 2: A GPIO LED node that references a GPIO
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&pfc 20 1>; /* Active low */
+		};
+	};
+
+Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
+           for the MMCIF and SCIFA4 devices
+
+	&pfc {
+		pinctrl-0 = <&scifa4_pins>;
+		pinctrl-names = "default";
+
+		mmcif_pins: mmcif {
+			mux {
+				renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
+				renesas,function = "mmc0";
+			};
+			cfg {
+				renesas,groups = "mmc0_data8_0";
+				renesas,pins = "PORT279";
+				renesas,pull-up = <1>;
+			};
+		};
+
+		scifa4_pins: scifa4 {
+			renesas,groups = "scifa4_data", "scifa4_ctrl";
+			renesas,function = "scifa4";
+		};
+	};
+
+Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
+
+	&mmcif {
+		pinctrl-0 = <&mmcif_pins>;
+		pinctrl-names = "default";
+
+		bus-width = <8>;
+		vmmc-supply = <&reg_1p8v>;
+		status = "okay";
+	};
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index ac45084..80d8d74 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -18,6 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
@@ -348,13 +349,68 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id sh_pfc_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A73A4
+	{
+		.compatible = "renesas,pfc-r8a73a4",
+		.data = &r8a73a4_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7740
+	{
+		.compatible = "renesas,pfc-r8a7740",
+		.data = &r8a7740_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+	{
+		.compatible = "renesas,pfc-r8a7778",
+		.data = &r8a7778_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7779
+	{
+		.compatible = "renesas,pfc-r8a7779",
+		.data = &r8a7779_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+	{
+		.compatible = "renesas,pfc-r8a7790",
+		.data = &r8a7790_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7372
+	{
+		.compatible = "renesas,pfc-sh7372",
+		.data = &sh7372_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH73A0
+	{
+		.compatible = "renesas,pfc-sh73a0",
+		.data = &sh73a0_pinmux_info,
+	},
+#endif
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
+#endif
+
 static int sh_pfc_probe(struct platform_device *pdev)
 {
+	const struct platform_device_id *platid = platform_get_device_id(pdev);
+	struct device_node *np = pdev->dev.of_node;
 	const struct sh_pfc_soc_info *info;
 	struct sh_pfc *pfc;
 	int ret;
 
-	info = (void *)pdev->id_entry->driver_data;
+	if (np)
+		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
+	else
+		info = platid ? (const void *)platid->driver_data : NULL;
+
 	if (info == NULL)
 		return -ENODEV;
 
@@ -500,6 +556,7 @@ static struct platform_driver sh_pfc_driver = {
 	.driver		= {
 		.name	= DRV_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(sh_pfc_of_table),
 	},
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 3492ec9..6a0de2c 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -14,7 +14,9 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/pinctrl/pinctrl.h>
@@ -72,11 +74,251 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 	seq_printf(s, "%s", DRV_NAME);
 }
 
+static int sh_pfc_map_add_config(struct pinctrl_map *map,
+				 const char *group_or_pin,
+				 enum pinctrl_map_type type,
+				 unsigned long *configs,
+				 unsigned int num_configs)
+{
+	unsigned long *cfgs;
+
+	cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
+		       GFP_KERNEL);
+	if (cfgs == NULL)
+		return -ENOMEM;
+
+	map->type = type;
+	map->data.configs.group_or_pin = group_or_pin;
+	map->data.configs.configs = cfgs;
+	map->data.configs.num_configs = num_configs;
+
+	return 0;
+}
+
+static int sh_pfc_dt_parse_config(unsigned long **configs,
+				  unsigned int *num_configs,
+				  unsigned long config)
+{
+	unsigned int count = *num_configs + 1;
+	unsigned long *cfgs;
+
+	cfgs = krealloc(*configs, sizeof(*cfgs) * count, GFP_KERNEL);
+	if (cfgs == NULL)
+		return -ENOMEM;
+
+	cfgs[count - 1] = config;
+
+	*configs = cfgs;
+	*num_configs = count;
+
+	return 0;
+}
+
+struct sh_pfc_config_param {
+	const char *name;
+	enum pin_config_param param;
+};
+
+static const struct sh_pfc_config_param sh_pfc_config_params[] = {
+	{ "renesas,pull-up", PIN_CONFIG_BIAS_PULL_UP },
+	{ "renesas,pull-down", PIN_CONFIG_BIAS_PULL_DOWN },
+};
+
+static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
+				    struct pinctrl_map **map,
+				    unsigned int *num_maps, unsigned int *index)
+{
+	struct pinctrl_map *maps = *map;
+	unsigned int nmaps = *num_maps;
+	unsigned int idx = *index;
+	unsigned long *configs = NULL;
+	unsigned int num_configs = 0;
+	const char *function = NULL;
+	struct property *prop;
+	unsigned int num_pins;
+	const char *group;
+	const char *pin;
+	unsigned int i;
+	int ret;
+
+	/* Parse the function and configuration properties. At least a function
+	 * or one configuration must be specified.
+	 */
+	ret = of_property_read_string(np, "renesas,function", &function);
+	if (ret < 0 && ret != -EINVAL) {
+		dev_err(dev, "Invalid function in DT\n");
+		return ret;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sh_pfc_config_params); ++i) {
+		const struct sh_pfc_config_param *param =
+			&sh_pfc_config_params[i];
+		unsigned long config;
+		u32 val;
+
+		ret = of_property_read_u32(np, param->name, &val);
+		if (!ret) {
+			config = pinconf_to_config_packed(param->param, val);
+			ret = sh_pfc_dt_parse_config(&configs, &num_configs,
+						     config);
+			if (ret < 0)
+				goto done;
+		} else if (ret != -EINVAL) {
+			dev_err(dev, "Could not parse property %s\n",
+				param->name);
+		}
+	}
+
+	if (!function && num_configs == 0) {
+		dev_err(dev,
+			"DT node must contain at least a function or config\n");
+		goto done;
+	}
+
+	/* Count the number of pins and groups and reallocate mappings. */
+	ret = of_property_count_strings(np, "renesas,pins");
+	if (ret < 0 && ret != -EINVAL) {
+		dev_err(dev, "Invalid pins list in DT\n");
+		goto done;
+	}
+	num_pins = ret;
+
+	if (configs)
+		nmaps += ret;
+
+	ret = of_property_count_strings(np, "renesas,groups");
+	if (ret < 0 && ret != -EINVAL) {
+		dev_err(dev, "Invalid pin groups list in DT\n");
+		goto done;
+	}
+	num_pins += ret;
+
+	if (function)
+		nmaps += ret;
+	if (configs)
+		nmaps += ret;
+
+	if (!num_pins) {
+		dev_err(dev, "No pin or group provided in DT node\n");
+		ret = -ENODEV;
+		goto done;
+	}
+
+	maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
+	if (maps == NULL) {
+		ret = -ENOMEM;
+		goto done;
+	}
+
+	*map = maps;
+	*num_maps = nmaps;
+
+	/* Iterate over pins and groups and create the mappings. */
+	of_property_for_each_string(np, "renesas,groups", prop, group) {
+		if (function) {
+			maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
+			maps[idx].data.mux.group = group;
+			maps[idx].data.mux.function = function;
+			idx++;
+		}
+
+		if (configs) {
+			ret = sh_pfc_map_add_config(&maps[idx], group,
+						    PIN_MAP_TYPE_CONFIGS_GROUP,
+						    configs, num_configs);
+			if (ret < 0)
+				goto done;
+
+			idx++;
+		}
+	}
+
+	if (!configs) {
+		ret = 0;
+		goto done;
+	}
+
+	of_property_for_each_string(np, "renesas,pins", prop, pin) {
+		ret = sh_pfc_map_add_config(&maps[idx], pin,
+					    PIN_MAP_TYPE_CONFIGS_PIN,
+					    configs, num_configs);
+		if (ret < 0)
+			goto done;
+
+		idx++;
+	}
+
+done:
+	*index = idx;
+	kfree(configs);
+	return ret;
+}
+
+static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
+			       struct pinctrl_map *map, unsigned num_maps)
+{
+	unsigned int i;
+
+	if (map == NULL)
+		return;
+
+	for (i = 0; i < num_maps; ++i) {
+		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
+		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
+			kfree(map[i].data.configs.configs);
+	}
+
+	kfree(map);
+}
+
+static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
+				 struct device_node *np,
+				 struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+	struct device *dev = pmx->pfc->dev;
+	struct device_node *child;
+	unsigned int index;
+	int ret;
+
+	*map = NULL;
+	*num_maps = 0;
+	index = 0;
+
+	for_each_child_of_node(np, child) {
+		ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
+					       &index);
+		if (ret < 0)
+			goto done;
+	}
+
+	/* If no mapping has been found in child nodes try the config node. */
+	if (*num_maps == 0) {
+		ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
+		if (ret < 0)
+			goto done;
+	}
+
+	if (*num_maps)
+		return 0;
+
+	dev_err(dev, "no mapping found in node %s\n", np->full_name);
+	ret = -EINVAL;
+
+done:
+	if (ret < 0)
+		sh_pfc_dt_free_map(pctldev, *map, *num_maps);
+
+	return ret;
+}
+
 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
 	.get_groups_count	= sh_pfc_get_groups_count,
 	.get_group_name		= sh_pfc_get_group_name,
 	.get_group_pins		= sh_pfc_get_group_pins,
 	.pin_dbg_show		= sh_pfc_pin_dbg_show,
+	.dt_node_to_map		= sh_pfc_dt_node_to_map,
+	.dt_free_map		= sh_pfc_dt_free_map,
 };
 
 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:26 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:26 +0200
Subject: [PATCH v4 05/21] ARM: shmobile: r8a7778: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-6-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7778 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7778.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 4743735..c8dbf14 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -32,4 +32,9 @@
 		reg = <0xfe438000 0x1000>,
 		      <0xfe430000 0x100>;
 	};
+
+	pfc: pfc at fffc0000 {
+		compatible = "renesas,pfc-r8a7778";
+		reg = <0xfffc000 0x118>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:25 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:25 +0200
Subject: [PATCH v4 04/21] ARM: shmobile: r8a7740: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-5-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7740 device tree and remove manual pinmux
initialization from the corresponding board files.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740.dtsi                           |  8 ++++++++
 arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 16 ++++++++--------
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 25dc930..2fa3708 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -135,4 +135,12 @@
 			      0 72 0x4
 			      0 73 0x4>;
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-r8a7740";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605800c 0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index 03b85fe..f25b6aa 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -121,7 +121,7 @@
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
 	/* SCIFA1 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "e6050000.pfc",
 				  "scifa1_data", "scifa1"),
 };
 
@@ -170,22 +170,22 @@ static void __init eva_init(void)
 	eva_clock_init();
 
 	pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
-	r8a7740_pinmux_init();
 
 	r8a7740_meram_workaround();
 
-	/*
-	 * Touchscreen
-	 * TODO: Move reset GPIO over to .dts when we can reference it
-	 */
-	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
-
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
 	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
 #endif
 
 	r8a7740_add_standard_devices_dt();
+
+	/*
+	 * Touchscreen
+	 * TODO: Move reset GPIO over to .dts when we can reference it
+	 */
+	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+
 	r8a7740_pm_init();
 }
 
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:27 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:27 +0200
Subject: [PATCH v4 06/21] ARM: shmobile: r8a7778: Add GPIO controller devices
 to device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-7-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add GPIO controller nodes to the r8a7778 core device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7778.dtsi | 51 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index c8dbf14..0639e8b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -33,8 +33,59 @@
 		      <0xfe430000 0x100>;
 	};
 
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc40000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 32>;
+	};
+
+	gpio1: gpio at ffc41000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc41000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 32>;
+	};
+
+	gpio2: gpio at ffc42000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc42000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 64 32>;
+	};
+
+	gpio3: gpio at ffc43000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc43000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 96 32>;
+	};
+
+	gpio4: gpio at ffc44000 {
+		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
+		reg = <0xffc44000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 103 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 128 27>;
+	};
+
 	pfc: pfc at fffc0000 {
 		compatible = "renesas,pfc-r8a7778";
 		reg = <0xfffc000 0x118>;
+		#gpio-range-cells = <3>;
 	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:28 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:28 +0200
Subject: [PATCH v4 07/21] ARM: shmobile: r8a7779: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-8-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7779 device tree and remove manual pinmux
initialization from the corresponding board files.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779.dtsi                  |  5 +++++
 arch/arm/mach-shmobile/board-marzen-reference.c | 17 ++++++++---------
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 7f146c6..9dfc438 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -101,6 +101,11 @@
 		interrupts = <0 81 0x4>;
 	};
 
+	pfc: pfc at fffc0000 {
+		compatible = "renesas,pfc-r8a7779";
+		reg = <0xfffc0000 0x23c>;
+	};
+
 	thermal at ffc48000 {
 		compatible = "renesas,rcar-thermal";
 		reg = <0xffc48000 0x38>;
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 5332e89..fa7fc07 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -28,24 +28,24 @@
 
 static const struct pinctrl_map marzen_pinctrl_map[] = {
 	/* SCIF2 (CN18: DEBUG0) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "fffc0000.pfc",
 				  "scif2_data_c", "scif2"),
 	/* SCIF4 (CN19: DEBUG1) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "fffc0000.pfc",
 				  "scif4_data", "scif4"),
 	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
 				  "sdhi0_wp", "sdhi0"),
 	/* SMSC */
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
 				  "intc_irq1_b", "intc"),
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "pfc-r8a7779",
+	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
 				  "lbsc_ex_cs0", "lbsc"),
 };
 
@@ -53,7 +53,6 @@ static void __init marzen_init(void)
 {
 	pinctrl_register_mappings(marzen_pinctrl_map,
 				  ARRAY_SIZE(marzen_pinctrl_map));
-	r8a7779_pinmux_init();
 
 	r8a7779_add_standard_devices_dt();
 }
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:30 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:30 +0200
Subject: [PATCH v4 09/21] ARM: shmobile: r8a7790: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-10-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the r8a7790 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7a17110..c14fbd1 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -60,4 +60,9 @@
 		interrupt-parent = <&gic>;
 		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>;
 	};
+
+	pfc: pfc at e6060000 {
+		compatible = "renesas,pfc-r8a7790";
+		reg = <0 0xe6060000 0 0x250>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:29 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:29 +0200
Subject: [PATCH v4 08/21] ARM: shmobile: r8a7779: Add GPIO controller devices
 to device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-9-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add GPIO controller nodes to the r8a7779 core device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779.dtsi | 71 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 9dfc438..2bbb4cb 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -48,6 +48,76 @@
                       <0xf0000100 0x100>;
         };
 
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc40000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 141 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 32>;
+	};
+
+	gpio1: gpio at ffc41000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc41000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 142 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 32>;
+	};
+
+	gpio2: gpio at ffc42000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc42000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 143 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 64 32>;
+	};
+
+	gpio3: gpio at ffc43000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc43000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 144 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 96 32>;
+	};
+
+	gpio4: gpio at ffc44000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc44000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 145 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 128 32>;
+	};
+
+	gpio5: gpio at ffc45000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc45000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 146 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 160 32>;
+	};
+
+	gpio6: gpio at ffc46000 {
+		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+		reg = <0xffc46000 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 147 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 192 9>;
+	};
+
 	irqpin0: irqpin at fe780010 {
 		compatible = "renesas,intc-irqpin";
 		#interrupt-cells = <2>;
@@ -104,6 +174,7 @@
 	pfc: pfc at fffc0000 {
 		compatible = "renesas,pfc-r8a7779";
 		reg = <0xfffc0000 0x23c>;
+		#gpio-range-cells = <3>;
 	};
 
 	thermal at ffc48000 {
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:32 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:32 +0200
Subject: [PATCH v4 11/21] ARM: shmobile: sh7372: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-12-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the sh7372 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh7372.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..ce19398 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -18,4 +18,12 @@
 			compatible = "arm,cortex-a8";
 		};
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-sh7372";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:31 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:31 +0200
Subject: [PATCH v4 10/21] ARM: shmobile: r8a7790: Add GPIO controller devices
 to device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-11-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add GPIO controller nodes to the r8a7790 core device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 61 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index c14fbd1..89afccd 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -44,6 +44,66 @@
 		};
 	};
 
+	gpio0: gpio at ffc40000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0 0xffc40000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 4 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 32>;
+	};
+
+	gpio1: gpio at ffc41000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0 0xffc41000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 5 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 32>;
+	};
+
+	gpio2: gpio at ffc42000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0 0xffc42000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 6 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 64 32>;
+	};
+
+	gpio3: gpio at ffc43000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0 0xffc43000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 7 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 96 32>;
+	};
+
+	gpio4: gpio at ffc44000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0 0xffc44000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 8 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 128 32>;
+	};
+
+	gpio5: gpio at ffc45000 {
+		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
+		reg = <0 0xffc45000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 9 0x4>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 160 32>;
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <1 13 0xf08>,
@@ -64,5 +124,6 @@
 	pfc: pfc at e6060000 {
 		compatible = "renesas,pfc-r8a7790";
 		reg = <0 0xe6060000 0 0x250>;
+		#gpio-range-cells = <3>;
 	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:33 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:33 +0200
Subject: [PATCH v4 12/21] ARM: shmobile: sh73a0: Add pin control device to
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-13-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add a pfc node to the sh73a0 device tree and remove manual pinmux
initialization from the corresponding board files.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0.dtsi                  |  8 ++++++++
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 27 +++++++++++++-------------
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 17fd9c6..9b1e8f8 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -233,4 +233,12 @@
 		cap-sd-highspeed;
 		status = "disabled";
 	};
+
+	pfc: pfc at e6050000 {
+		compatible = "renesas,pfc-sh73a0";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 44055fe..6ff6ca2 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -40,35 +40,35 @@ static unsigned long pin_pullup_conf[] = {
 };
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
-	PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "e6050000.pfc",
 				  "i2c3_1", "i2c3"),
 	/* MMCIF */
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				  "mmc0_data8_0", "mmc0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				  "mmc0_ctrl_0", "mmc0"),
-	PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				    "PORT279", pin_pullup_conf),
-	PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+	PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
 				      "mmc0_data8_0", pin_pullup_conf),
 	/* SCIFA4 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
 				  "scifa4_data", "scifa4"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
 				  "scifa4_ctrl", "scifa4"),
 	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
 				  "sdhi0_wp", "sdhi0"),
 	/* SDHI2 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
 				  "sdhi2_data4", "sdhi2"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
 				  "sdhi2_ctrl", "sdhi2"),
 };
 
@@ -76,7 +76,6 @@ static void __init kzm_init(void)
 {
 	sh73a0_add_standard_devices_dt();
 	pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
-	sh73a0_pinmux_init();
 
 	/* enable SD */
 	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:34 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:34 +0200
Subject: [PATCH v4 13/21] ARM: shmobile: armadillo-reference: Move pinctrl
 mappings to device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-14-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Replace the pinctrl mappings in board code by device tree mappings.
For devices that are still instantiated from board code reference the
mappings as the default pin controller state to apply them at boot time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts  | 10 ++++++++++
 arch/arm/mach-shmobile/board-armadillo800eva-reference.c |  9 ---------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 09ea22c..4a7ae32 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -43,3 +43,13 @@
 		interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
 	};
 };
+
+&pfc {
+	pinctrl-0 = <&scifa1_pins>;
+	pinctrl-names = "default";
+
+	scifa1_pins: scifa1 {
+		renesas,groups = "scifa1_data";
+		renesas,function = "scifa1";
+	};
+};
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index f25b6aa..4ddd299 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -24,7 +24,6 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <linux/pinctrl/machine.h>
 #include <mach/common.h>
 #include <mach/r8a7740.h>
 #include <asm/mach/arch.h>
@@ -119,12 +118,6 @@
  *	usbhsf_power_ctrl()
  */
 
-static const struct pinctrl_map eva_pinctrl_map[] = {
-	/* SCIFA1 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "e6050000.pfc",
-				  "scifa1_data", "scifa1"),
-};
-
 static void __init eva_clock_init(void)
 {
 	struct clk *system	= clk_get(NULL, "system_clk");
@@ -169,8 +162,6 @@ static void __init eva_init(void)
 	r8a7740_clock_init(MD_CK0 | MD_CK2);
 	eva_clock_init();
 
-	pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
-
 	r8a7740_meram_workaround();
 
 #ifdef CONFIG_CACHE_L2X0
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:36 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:36 +0200
Subject: [PATCH v4 15/21] ARM: shmobile: armadillo-reference: Move st1232
 reset GPIO to DT
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-16-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Reference the st1232 reset GPIO from the device tree and remove it from
board code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts  | 1 +
 arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 7 -------
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index a6c6606..a037776 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -43,6 +43,7 @@
 		interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
 		pinctrl-0 = <&st1232_pins>;
 		pinctrl-names = "default";
+		gpios = <&pfc 166 1>;
 	};
 };
 
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index 4ddd299..002d8d3 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -158,7 +158,6 @@ clock_error:
  */
 static void __init eva_init(void)
 {
-
 	r8a7740_clock_init(MD_CK0 | MD_CK2);
 	eva_clock_init();
 
@@ -171,12 +170,6 @@ static void __init eva_init(void)
 
 	r8a7740_add_standard_devices_dt();
 
-	/*
-	 * Touchscreen
-	 * TODO: Move reset GPIO over to .dts when we can reference it
-	 */
-	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
-
 	r8a7740_pm_init();
 }
 
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:35 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:35 +0200
Subject: [PATCH v4 14/21] ARM: shmobile: armadillo-reference: Add st1232 pin
 mappings
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-15-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Add pin mappings for the st1232 device to the device tree and reference
them as the default state for the device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 4a7ae32..a6c6606 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -41,6 +41,8 @@
 		reg = <0x55>;
 		interrupt-parent = <&irqpin1>;
 		interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+		pinctrl-0 = <&st1232_pins>;
+		pinctrl-names = "default";
 	};
 };
 
@@ -52,4 +54,9 @@
 		renesas,groups = "scifa1_data";
 		renesas,function = "scifa1";
 	};
+
+	st1232_pins: st1232 {
+		renesas,groups = "intc_irq10";
+		renesas,function = "intc";
+	};
 };
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:37 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:37 +0200
Subject: [PATCH v4 16/21] ARM: shmobile: armadillo-reference: Add LED1-LED4 to
 the device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-17-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

LED1 to LED4 are GPIO LEDs. Add corresponding DT nodes.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index a037776..746c64a 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -33,6 +33,21 @@
 		regulator-boot-on;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&pfc 102 0>;
+		};
+		led2 {
+			gpios = <&pfc 111 0>;
+		};
+		led3 {
+			gpios = <&pfc 110 0>;
+		};
+		led4 {
+			gpios = <&pfc 177 0>;
+		};
+	};
 };
 
 &i2c0 {
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:38 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:38 +0200
Subject: [PATCH v4 17/21] ARM: shmobile: kzm9g-reference: Move pinctrl
 mappings to device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-18-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Replace the pinctrl mappings in board code by device tree mappings.
For devices that are still instantiated from board code reference the
mappings as the default pin controller state to apply them at boot time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts   | 51 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 40 --------------------
 2 files changed, 51 insertions(+), 40 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index b6f759e..475535f 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -145,19 +145,70 @@
 	};
 };
 
+&i2c3 {
+	pinctrl-0 = <&i2c3_pins>;
+	pinctrl-names = "default";
+};
+
 &mmcif {
+	pinctrl-0 = <&mmcif_pins>;
+	pinctrl-names = "default";
+
 	bus-width = <8>;
 	vmmc-supply = <&reg_1p8v>;
 	status = "okay";
 };
 
+&pfc {
+	pinctrl-0 = <&scifa4_pins>;
+	pinctrl-names = "default";
+
+	i2c3_pins: i2c3 {
+		renesas,groups = "i2c3_1";
+		renesas,function = "i2c3";
+	};
+
+	mmcif_pins: mmcif {
+		mux {
+			renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
+			renesas,function = "mmc0";
+		};
+		cfg {
+			renesas,groups = "mmc0_data8_0";
+			renesas,pins = "PORT279";
+			renesas,pull-up = <1>;
+		};
+	};
+
+	scifa4_pins: scifa4 {
+		renesas,groups = "scifa4_data", "scifa4_ctrl";
+		renesas,function = "scifa4";
+	};
+
+	sdhi0_pins: sdhi0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
+		renesas,function = "sdhi0";
+	};
+
+	sdhi2_pins: sdhi2 {
+		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+		renesas,function = "sdhi2";
+	};
+};
+
 &sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
 	vmmc-supply = <&reg_3p3v>;
 	bus-width = <4>;
 	status = "okay";
 };
 
 &sdhi2 {
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-names = "default";
+
 	vmmc-supply = <&reg_3p3v>;
 	bus-width = <4>;
 	broken-cd;
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 6ff6ca2..fc2bb37 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -27,55 +27,15 @@
 #include <linux/irqchip.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
 #include <mach/sh73a0.h>
 #include <mach/common.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-static unsigned long pin_pullup_conf[] = {
-	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
-};
-
-static const struct pinctrl_map kzm_pinctrl_map[] = {
-	PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "e6050000.pfc",
-				  "i2c3_1", "i2c3"),
-	/* MMCIF */
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				  "mmc0_data8_0", "mmc0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				  "mmc0_ctrl_0", "mmc0"),
-	PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				    "PORT279", pin_pullup_conf),
-	PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc",
-				      "mmc0_data8_0", pin_pullup_conf),
-	/* SCIFA4 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
-				  "scifa4_data", "scifa4"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc",
-				  "scifa4_ctrl", "scifa4"),
-	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc",
-				  "sdhi0_wp", "sdhi0"),
-	/* SDHI2 */
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
-				  "sdhi2_data4", "sdhi2"),
-	PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc",
-				  "sdhi2_ctrl", "sdhi2"),
-};
-
 static void __init kzm_init(void)
 {
 	sh73a0_add_standard_devices_dt();
-	pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
 
 	/* enable SD */
 	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:39 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:39 +0200
Subject: [PATCH v4 18/21] ARM: shmobile: kzm9g-reference: Move SDHI regulators
 to DT
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-19-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Create two GPIO-controlled fixed-voltage regulators in the
kzm9g-reference DT and remove manual configuration of the corresponding
GPIOs from board code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts   | 22 ++++++++++++++++++++--
 arch/arm/mach-shmobile/board-kzm9g-reference.c |  6 ------
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 475535f..cdfd71a 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -58,6 +58,24 @@
 		regulator-boot-on;
 	};
 
+	vmmc_sdhi0: regulator at 2 {
+	        compatible = "regulator-fixed";
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pfc 15 0>;
+		enable-active-high;
+	};
+
+	vmmc_sdhi2: regulator at 3 {
+	        compatible = "regulator-fixed";
+		regulator-name = "SDHI2 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pfc 14 0>;
+		enable-active-high;
+	};
+
 	lan9220 at 10000000 {
 		compatible = "smsc,lan9220", "smsc,lan9115";
 		reg = <0x10000000 0x100>;
@@ -200,7 +218,7 @@
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
 
-	vmmc-supply = <&reg_3p3v>;
+	vmmc-supply = <&vmmc_sdhi0>;
 	bus-width = <4>;
 	status = "okay";
 };
@@ -209,7 +227,7 @@
 	pinctrl-0 = <&sdhi2_pins>;
 	pinctrl-names = "default";
 
-	vmmc-supply = <&reg_3p3v>;
+	vmmc-supply = <&vmmc_sdhi2>;
 	bus-width = <4>;
 	broken-cd;
 	status = "okay";
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index fc2bb37..1847b4d 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -21,7 +21,6 @@
  */
 
 #include <linux/delay.h>
-#include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
@@ -37,11 +36,6 @@ static void __init kzm_init(void)
 {
 	sh73a0_add_standard_devices_dt();
 
-	/* enable SD */
-	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
-	gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
 	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:40 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:40 +0200
Subject: [PATCH v4 19/21] ARM: shmobile: kzm9g-reference: Add LED1-LED4 to the
 device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-20-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

LED1 to LED4 are GPIO LEDs. Add corresponding DT nodes.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index cdfd71a..21b0fe3 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -88,6 +88,22 @@
 		vddvario-supply = <&reg_1p8v>;
 		vdd33a-supply = <&reg_3p3v>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&pfc 20 1>; /* Active low */
+		};
+		led2 {
+			gpios = <&pfc 21 1>; /* Active low */
+		};
+		led3 {
+			gpios = <&pfc 22 1>; /* Active low */
+		};
+		led4 {
+			gpios = <&pfc 23 1>; /* Active low */
+		};
+	};
 };
 
 &i2c0 {
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:42 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:42 +0200
Subject: [PATCH v4 21/21] ARM: shmobile: marzen-reference: Add LED2-LED4 to
 the device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-22-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

LED2 to LED4 are GPIO LEDs. Add corresponding DT nodes.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 596e313..48e254b 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -48,6 +48,19 @@
 		vddvario-supply = <&fixedregulator3v3>;
 		vdd33a-supply = <&fixedregulator3v3>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 0>;
+		};
+		led3 {
+			gpios = <&gpio4 30 0>;
+		};
+		led4 {
+			gpios = <&gpio4 31 0>;
+		};
+	};
 };
 
 &pfc {
-- 
1.8.1.5



From laurent.pinchart+renesas at ideasonboard.com  Tue May 21 08:14:41 2013
From: laurent.pinchart+renesas at ideasonboard.com (Laurent Pinchart)
Date: Tue, 21 May 2013 14:14:41 +0200
Subject: [PATCH v4 20/21] ARM: shmobile: marzen-reference: Move pinctrl
 mappings to device tree
In-Reply-To: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <1369138482-5871-21-git-send-email-laurent.pinchart+renesas@ideasonboard.com>

Replace the pinctrl mappings in board code by device tree mappings.
For devices that are still instantiated from board code reference the
mappings as the default pin controller state to apply them at boot time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts  | 35 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-marzen-reference.c | 27 -------------------
 2 files changed, 35 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index fe32e1a..596e313 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -37,6 +37,9 @@
 	lan0 at 18000000 {
 		compatible = "smsc,lan9220", "smsc,lan9115";
 		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&lan0_pins>;
+		pinctrl-names = "default";
+
 		phy-mode = "mii";
 		interrupt-parent = <&irqpin0>;
 		interrupts = <1 0x4>;
@@ -46,3 +49,35 @@
 		vdd33a-supply = <&fixedregulator3v3>;
 	};
 };
+
+&pfc {
+	pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>;
+	pinctrl-names = "default";
+
+	lan0_pins: lan0 {
+		intc {
+			renesas,groups = "intc_irq1_b";
+			renesas,function = "intc";
+		};
+		lbsc {
+			renesas,groups = "lbsc_ex_cs0";
+			renesas,function = "lbsc";
+		};
+	};
+
+	scif2_pins: scif2 {
+		renesas,groups = "scif2_data_c";
+		renesas,function = "scif2";
+	};
+
+	scif4_pins: scif4 {
+		renesas,groups = "scif4_data";
+		renesas,function = "scif4";
+	};
+
+	sdhi0_pins: sdhi0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd",
+				 "sdhi0_wp";
+		renesas,function = "sdhi0";
+	};
+};
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index fa7fc07..3d1c439 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,41 +19,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/pinctrl/machine.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
-static const struct pinctrl_map marzen_pinctrl_map[] = {
-	/* SCIF2 (CN18: DEBUG0) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "fffc0000.pfc",
-				  "scif2_data_c", "scif2"),
-	/* SCIF4 (CN19: DEBUG1) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "fffc0000.pfc",
-				  "scif4_data", "scif4"),
-	/* SDHI0 */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_data4", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_ctrl", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_cd", "sdhi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc",
-				  "sdhi0_wp", "sdhi0"),
-	/* SMSC */
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
-				  "intc_irq1_b", "intc"),
-	PIN_MAP_MUX_GROUP_DEFAULT("18000000.lan0", "fffc0000.pfc",
-				  "lbsc_ex_cs0", "lbsc"),
-};
-
 static void __init marzen_init(void)
 {
-	pinctrl_register_mappings(marzen_pinctrl_map,
-				  ARRAY_SIZE(marzen_pinctrl_map));
-
 	r8a7779_add_standard_devices_dt();
 }
 
-- 
1.8.1.5



From B35083 at freescale.com  Tue May 21 03:56:21 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Tue, 21 May 2013 07:56:21 +0000
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <20130520033207.GD25113@S2101-09.ap.freescale.net>
 <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CBBA4@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo at linaro.org]
>Sent: Monday, May 20, 2013 11:52 AM
>To: Lu Jingchang-B35083
>Cc: linux-arm-kernel; Linus Walleij; Sascha Hauer
>Subject: Re: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
>
>On 20 May 2013 11:32, Shawn Guo <shawn.guo at linaro.org> wrote:
>>> +static struct imx_pinctrl_soc_info mvf600_pinctrl_info = {
>>> +     .pins = mvf600_pinctrl_pads,
>>> +     .npins = ARRAY_SIZE(mvf600_pinctrl_pads),
>>> +     .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
>>
>> The flags should be introduced in the same patch where they are used
>> in the first place.
>>
>I just found what you need to do is just to reverse the patch order,
>having this patch be the second one.
>
[Lu Jingchang-B35083] 
I see you have Acked [PATCH v3 2/2] pinctrl: imx: add MVF600 support to imx pinctrl framework, do I need resend it as the first one. Thanks!




From m-karicheri2 at ti.com  Tue May 21 08:24:32 2013
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Tue, 21 May 2013 12:24:32 +0000
Subject: hugetlbfs support plan for ARM
In-Reply-To: <20130521100507.GA14248@linaro.org>
References: <3E54258959B69E4282D79E01AB1F32B7044F299D@DFLE11.ent.ti.com>
 <519ACF4B.9070502@gmail.com> <20130521100507.GA14248@linaro.org>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7044F32CC@DFLE11.ent.ti.com>

Steve, Bill and Will

Thanks all for the response. So I understand this will get merged eventually to a future kernel version. If this is true, I would like to pull in the latest and give it a try on our Cortex A15 SMP ARM platform. We haven't upstream-ed this machine, but have plan to do so this year. I am on 3.8.4 kernel currently (due to dependency with RT Preempt patch) and will start using this patch and let you know the feedback.  BTW, do you see any issues with using this patch with RT Preempt kernel patch and also on A15 SMP kernel?

Thanks

Murali Karicheri
Software Design Engineer


>> -----Original Message-----
>> From: Steve Capper [mailto:steve.capper at linaro.org]
>> Sent: Tuesday, May 21, 2013 6:06 AM
>> To: bill4carson
>> Cc: Karicheri, Muralidharan; linux-arm-kernel at lists.infradead.org
>> Subject: Re: hugetlbfs support plan for ARM
>> 
>> On Tue, May 21, 2013 at 09:35:07AM +0800, bill4carson wrote:
>> > Hi, Karichri
>> >
>> > On 2013?05?21? 02:26, Karicheri, Muralidharan wrote:
>> > >Hi Bill,
>> > >
>> > >I see the patch at
>> > >http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/0
>> > >84360.html
>> > >
>> > >Is there a plan to merge this to upstream Linux kernel? I would appreciate your
>> response on this.
>> >
>> > I tried to post several round of this patch set, but haven't got more time to merge it.
>> > Steve Capper from ARM proposed both HUGEPAGE and THP in below link,
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/14
>> > 8451.html
>> >
>> > Look https://wiki.linaro.org/LEG/Engineering/Kernel/HugePages here to find what you
>> needs.
>> >
>> 
>> Hi,
>> Apologies for the delay, I am working on rebasing HugeTLB+THP for 3.10-rc1. An issue
>> with PROT_NONE has arisen, and I'm currently fixing this.
>> 
>> Cheers,
>> --
>> Steve
>> 
>> > >Thanks.
>> > >
>> > >Murali Karicheri
>> > >
>> > >/Software Design Engineer/
>> > >
>> >
>> > --
>> > ?????????,??????????
>> >
>> > --bill


From andriy.shevchenko at linux.intel.com  Tue May 21 08:31:00 2013
From: andriy.shevchenko at linux.intel.com (Andy Shevchenko)
Date: Tue, 21 May 2013 15:31:00 +0300
Subject: dmatest regression in 3.10-rc1
In-Reply-To: <20130520095857.GI31359@mudshark.cambridge.arm.com>
References: <20130515152803.GL23869@mudshark.cambridge.arm.com>
 <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <20130517123423.GR14863@intel.com>
 <20130517141857.GM23112@mudshark.cambridge.arm.com>
 <1369036354.29283.115.camel@smile>
 <20130520095857.GI31359@mudshark.cambridge.arm.com>
Message-ID: <1369139460.29283.147.camel@smile>

On Mon, 2013-05-20 at 10:58 +0100, Will Deacon wrote: 
> Sure. They way I trigger it is to unload the module whilst the DMA is
> ongoing (I'm using a software model, so I can make the DMA nice and slow --
> I guess you could try using some large buffers).

Thank you for the script. It looks like I managed to reproduce it with
help of your script. I'm about to send the patch. I will appreciate to
collect a Tested-by tags in case it solves the issue.


-- 
Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Intel Finland Oy


From peterz at infradead.org  Tue May 21 07:57:34 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Tue, 21 May 2013 13:57:34 +0200
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130519093526.GD19883@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
Message-ID: <20130521115734.GA9554@twins.programming.kicks-ass.net>

On Sun, May 19, 2013 at 12:35:26PM +0300, Michael S. Tsirkin wrote:
> > > --- a/include/linux/kernel.h
> > > +++ b/include/linux/kernel.h
> > > @@ -198,7 +198,6 @@ void might_fault(void);
> > >  #else
> > >  static inline void might_fault(void)
> > >  {
> > > -	might_sleep();
> > 
> > This removes potential resched points for PREEMPT_VOLUNTARY -- was that
> > intentional?
> 
> No it's a bug. Thanks for pointing this out.
> OK so I guess it should be might_sleep_if(!in_atomic())
> and this means might_fault would have to move from linux/kernel.h to
> linux/uaccess.h, since in_atomic() is in linux/hardirq.h
> 
> Makes sense?

So the only difference between PROVE_LOCKING and not should be the
might_lock_read() thing; so how about something like this?

---
 include/linux/kernel.h  |  7 ++-----
 include/linux/uaccess.h | 26 ++++++++++++++++++++++++++
 mm/memory.c             | 14 ++------------
 3 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index e96329c..70812f4 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -194,12 +194,9 @@ extern int _cond_resched(void);
 	})
 
 #ifdef CONFIG_PROVE_LOCKING
-void might_fault(void);
+void might_fault_lockdep(void);
 #else
-static inline void might_fault(void)
-{
-	might_sleep();
-}
+static inline void might_fault_lockdep(void) { }
 #endif
 
 extern struct atomic_notifier_head panic_notifier_list;
diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
index 5ca0951..50a2cc9 100644
--- a/include/linux/uaccess.h
+++ b/include/linux/uaccess.h
@@ -38,6 +38,32 @@ static inline void pagefault_enable(void)
 	preempt_check_resched();
 }
 
+static inline bool __can_fault(void)
+{
+	/*
+	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
+	 * holding the mmap_sem, this is safe because kernel memory doesn't
+	 * get paged out, therefore we'll never actually fault, and the
+	 * below annotations will generate false positives.
+	 */
+	if (segment_eq(get_fs(), KERNEL_DS))
+		return false;
+
+	if (in_atomic() /* || pagefault_disabled() */)
+		return false;
+
+	return true;
+}
+
+static inline void might_fault(void)
+{
+	if (!__can_fault())
+		return;
+
+	might_sleep();
+	might_fault_lockdep();
+}
+
 #ifndef ARCH_HAS_NOCACHE_UACCESS
 
 static inline unsigned long __copy_from_user_inatomic_nocache(void *to,
diff --git a/mm/memory.c b/mm/memory.c
index 6dc1882..266610c 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -4211,19 +4211,9 @@ void print_vma_addr(char *prefix, unsigned long ip)
 }
 
 #ifdef CONFIG_PROVE_LOCKING
-void might_fault(void)
+void might_fault_lockdep(void)
 {
 	/*
-	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
-	 * holding the mmap_sem, this is safe because kernel memory doesn't
-	 * get paged out, therefore we'll never actually fault, and the
-	 * below annotations will generate false positives.
-	 */
-	if (segment_eq(get_fs(), KERNEL_DS))
-		return;
-
-	might_sleep();
-	/*
 	 * it would be nicer only to annotate paths which are not under
 	 * pagefault_disable, however that requires a larger audit and
 	 * providing helpers like get_user_atomic.
@@ -4231,7 +4221,7 @@ void might_fault(void)
 	if (!in_atomic() && current->mm)
 		might_lock_read(&current->mm->mmap_sem);
 }
-EXPORT_SYMBOL(might_fault);
+EXPORT_SYMBOL(might_fault_lockdep);
 #endif
 
 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLBFS)



From peterz at infradead.org  Tue May 21 07:18:18 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Tue, 21 May 2013 13:18:18 +0200
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130519164009.GA2434@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <1368966844.6828.111.camel@gandalf.local.home>
 <20130519133418.GA24381@redhat.com>
 <1368979579.6828.114.camel@gandalf.local.home>
 <20130519164009.GA2434@redhat.com>
Message-ID: <20130521111818.GI26912@twins.programming.kicks-ass.net>

On Sun, May 19, 2013 at 07:40:09PM +0300, Michael S. Tsirkin wrote:
> OK I get it. So let me correct myself. The simple code
> that does something like this under a spinlock:
> >       preempt_disable
> >       pagefault_disable
> >       error = copy_to_user
> >       pagefault_enable
> >       preempt_enable
> >
> is not doing anything wrong and should not get a warning,
> as long as error is handled correctly later.
> Right?

Indeed, but I don't get the point of the preempt_{disable,enable}()
here. Why does it have to disable preemption explicitly here? I thought
all you wanted was to avoid the pagefault handler and make it do the
exception table thing; for that pagefault_disable() is sufficient.


From andriy.shevchenko at linux.intel.com  Tue May 21 08:33:17 2013
From: andriy.shevchenko at linux.intel.com (Andy Shevchenko)
Date: Tue, 21 May 2013 15:33:17 +0300
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <20130516153553.GI11706@mudshark.cambridge.arm.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
Message-ID: <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>

When thread is going to be stopped we have to unconditionally terminate all
ongoing transfers. Otherwise it would be possible that callback function will
be called on the next interrupt and will try to access to already freed
structures.

The patch introduces specific error message for this, though it doesn't
increase the counter of the failed tests.

Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Reported-by: Will Deacon <will.deacon at arm.com>
---
 drivers/dma/dmatest.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index d8ce4ec..f61bd55 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -92,6 +92,7 @@ enum dmatest_error_type {
 	DMATEST_ET_MAP_DST,
 	DMATEST_ET_PREP,
 	DMATEST_ET_SUBMIT,
+	DMATEST_ET_ABORT,
 	DMATEST_ET_TIMEOUT,
 	DMATEST_ET_DMA_ERROR,
 	DMATEST_ET_DMA_IN_PROGRESS,
@@ -366,6 +367,7 @@ static char *thread_result_get(const char *name,
 		[DMATEST_ET_MAP_DST]		= "dst mapping error",
 		[DMATEST_ET_PREP]		= "prep error",
 		[DMATEST_ET_SUBMIT]		= "submit error",
+		[DMATEST_ET_ABORT]		= "transfer aborted",
 		[DMATEST_ET_TIMEOUT]		= "test timed out",
 		[DMATEST_ET_DMA_ERROR]		=
 			"got completion callback (DMA_ERROR)",
@@ -720,6 +722,15 @@ static int dmatest_func(void *data)
 					     done.done || kthread_should_stop(),
 					     msecs_to_jiffies(params->timeout));
 
+		/* terminate all transfers on specified channel if needed */
+		if (kthread_should_stop()) {
+			dmaengine_terminate_all(chan);
+			thread_result_add(info, result, DMATEST_ET_ABORT,
+					  total_tests, src_off, dst_off,
+					  len, 0);
+			break;
+		}
+
 		status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
 
 		if (!done.done) {
-- 
1.8.2.rc0.22.gb3600c3



From florian.vaussard at epfl.ch  Tue May 21 08:08:51 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Tue, 21 May 2013 14:08:51 +0200
Subject: [PATCH] ARM: OMAP4: change the device names in usb_bind_phy
In-Reply-To: <20130517172335.GX5600@atomide.com>
References: <1366697656-14315-1-git-send-email-kishon@ti.com>
 <51936946.3030507@iki.fi> <20130516155857.GV5600@atomide.com>
 <519503DA.5070303@iki.fi> <20130516162034.GX5600@atomide.com>
 <5195C28C.40300@ti.com> <20130517172335.GX5600@atomide.com>
Message-ID: <519B63D3.7040600@epfl.ch>


On 05/17/2013 07:23 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kishon at ti.com> [130516 22:45]:
>> Hi,
>>
>> On Thursday 16 May 2013 09:50 PM, Tony Lindgren wrote:
>>> * Tomi Valkeinen <tomi.valkeinen at iki.fi> [130516 09:11]:
>>>> On 16/05/13 18:58, Tony Lindgren wrote:
>>>>> * Tomi Valkeinen <tomi.valkeinen at iki.fi> [130515 03:59]:
>>>>>
>>>>> Just checking.. Do you have CONFIG_OMAP_OCP2SCP=y in your .config? Sounds
>>>>> like the some transceivers should depend on that for omap4.
>>>>
>>>> Yes, I have OCP2SCP=y.
>>>
>>> Hmm well no idea beyond that then. Sounds like Kishon should check it.
>>>
>>>>>> The musb-hdrc id is wrong on overo also.
>>>>>
>>>>> Hmm has there been a fix posted for that?
>>>>
>>>> I couldn't find with a quick look. We debugged and discussed this on an irc
>>>> channel with Kishon, who said he'll send a patch. Changing the musb-hdrc ID
>>>> on overo fixed the issue, and it looks very similar to the error on 4430sdp.
>>>> The overo fix was just:
>>
>> hmm.. I think using device name to bind the controller and the phy
>> can no longer be used reliably. I think it's better to have
>> something like what Grant suggested in my other patch series.. to
>> have the phy reference into the host controllers platform_data
>> structure. And for the phy reference I'll have label and id.
>>
>> Does this makes sense to you?
>
> Sounds OK to me, but I guess that would be for v3.11. I think we
> still need a fix for at least overo for v3.10?
>

Indead, musb-hdrc is broken on overo with 3.10-rc2. The patch posted in this
thread fixes the issue.

Regards,

Florian


From peterz at infradead.org  Tue May 21 07:21:26 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Tue, 21 May 2013 13:21:26 +0200
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130519093526.GD19883@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
Message-ID: <20130521112126.GJ26912@twins.programming.kicks-ass.net>

On Sun, May 19, 2013 at 12:35:26PM +0300, Michael S. Tsirkin wrote:
> On Thu, May 16, 2013 at 08:40:41PM +0200, Peter Zijlstra wrote:
> > On Thu, May 16, 2013 at 02:16:10PM +0300, Michael S. Tsirkin wrote:
> > > There are several ways to make sure might_fault
> > > calling function does not sleep.
> > > One is to use it on kernel or otherwise locked memory - apparently
> > > nfs/sunrpc does this. As noted by Ingo, this is handled by the
> > > migh_fault() implementation in mm/memory.c but not the one in
> > > linux/kernel.h so in the current code might_fault() schedules
> > > differently depending on CONFIG_PROVE_LOCKING, which is an undesired
> > > semantical side effect.
> > > 
> > > Another is to call pagefault_disable: in this case the page fault
> > > handler will go to fixups processing and we get an error instead of
> > > sleeping, so the might_sleep annotation is a false positive.
> > > vhost driver wants to do this now in order to reuse socket ops
> > > under a spinlock (and fall back on slower thread handler
> > > on error).
> > 
> > Are you using the assumption that spin_lock() implies preempt_disable() implies
> > pagefault_disable()? Note that this assumption isn't valid for -rt where the
> > spinlock becomes preemptible but we'll not disable pagefaults.
> 
> No, I was not assuming that. What I'm trying to say is that a caller
> that does something like this under a spinlock:
> 	preempt_disable
> 	pagefault_disable
> 	error = copy_to_user
> 	pagefault_enable
> 	preempt_enable_no_resched
> 
> is not doing anything wrong and should not get a warning,
> as long as error is handled correctly later.
> Right?

Aside from the no_resched() thing which Steven already explained and my
previous email asking why you need the preempt_disable() at all, that
should indeed work.

The reason I was asking was that I wasn't sure you weren't doing:

  spin_lock(&my_lock);
  error = copy_to_user();
  spin_unlock(&my_lock);

and expecting the copy_to_user() to always take the exception table
route. This works on mainline (since spin_lock implies a preempt disable
and preempt_disable is the same as pagefault_disable). However as should
be clear by now, it doesn't quite work that way for -rt.




From hdoyu at nvidia.com  Tue May 21 05:10:44 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 21 May 2013 12:10:44 +0300
Subject: [v2 0/6] CLK: tegra: convert device tree files to use CLK defines
Message-ID: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com>

This patchset converts device tree files to use CLK defines. This
version was updated along with the latest DT changes.

The following changes since commit 7479d8bb5650f43053d0e82fa44db668cf968f11:

  TESTING: Build Tegra USB as a module (2013-05-20 13:11:19 -0600)

are available in the git repository at:

  git://nv-tegra.nvidia.com/user/hdoyu/linux.git dt-replace-clkid

for you to fetch changes up to cfafa8272866ecc3e8baad7f3066921b279890fe:

  ARM: tegra114: convert device tree files to use CLK defines (2013-05-21 11:16:47 +0300)

----------------------------------------------------------------
Hiroshi Doyu (6):
      ARM: tegra20: create a DT header defining CLK IDs
      ARM: tegra20: convert device tree files to use CLK defines
      ARM: tegra30: create a DT header defining CLK IDs
      ARM: tegra30: convert device tree files to use CLK defines
      ARM: tegra114: create a DT header defining CLK IDs
      ARM: tegra114: convert device tree files to use CLK defines

 .../bindings/clock/nvidia,tegra114-car.txt         | 252 +--------------
 .../bindings/clock/nvidia,tegra20-car.txt          | 154 +---------
 .../bindings/clock/nvidia,tegra30-car.txt          | 211 +------------
 arch/arm/boot/dts/tegra114-dalmore.dts             |   4 +-
 arch/arm/boot/dts/tegra114.dtsi                    |  79 ++---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi         |   4 +-
 arch/arm/boot/dts/tegra20-harmony.dts              |   4 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts          |   4 +-
 arch/arm/boot/dts/tegra20-paz00.dts                |   4 +-
 arch/arm/boot/dts/tegra20-plutux.dts               |   4 +-
 arch/arm/boot/dts/tegra20-seaboard.dts             |   4 +-
 arch/arm/boot/dts/tegra20-tec.dts                  |   4 +-
 arch/arm/boot/dts/tegra20-trimslice.dts            |   4 +-
 arch/arm/boot/dts/tegra20-ventana.dts              |   4 +-
 arch/arm/boot/dts/tegra20-whistler.dts             |   4 +-
 arch/arm/boot/dts/tegra20.dtsi                     | 116 +++----
 arch/arm/boot/dts/tegra30-beaver.dts               |   4 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |   4 +-
 arch/arm/boot/dts/tegra30.dtsi                     | 110 ++++---
 include/dt-bindings/clk/tegra114-car.h             | 342 +++++++++++++++++++++
 include/dt-bindings/clk/tegra20-car.h              | 158 ++++++++++
 include/dt-bindings/clk/tegra30-car.h              | 265 ++++++++++++++++
 22 files changed, 984 insertions(+), 755 deletions(-)
 create mode 100644 include/dt-bindings/clk/tegra114-car.h
 create mode 100644 include/dt-bindings/clk/tegra20-car.h
 create mode 100644 include/dt-bindings/clk/tegra30-car.h


From josephl at nvidia.com  Tue May 21 05:58:02 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 21 May 2013 17:58:02 +0800
Subject: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <519AAFCB.8060007@wwwdotorg.org>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
 <519AAFCB.8060007@wwwdotorg.org>
Message-ID: <1369130282.21734.0.camel@jlo-ubuntu-64.nvidia.com>

On Tue, 2013-05-21 at 07:20 +0800, Stephen Warren wrote:
> On 05/20/2013 04:39 AM, Joseph Lo wrote:
> > Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> > as CPU core and a enhanced flow controller for CPU power control. So
> > we need to skip some code that was for Contex-A9 and some other support
> > code that was for other Tegra SoC chips. Then adding the proper power up
> > and hot plug control for Tegra114.
> 
> This version still doesn't enable hotplug of CPU0, yet at least patch
> 6/6 contains some changes that support enabling that. Are you planning
> on sending a separate patch to enable this later, or was this an oversight?

I will provide another patch to support it.

Joseph



From shc_work at mail.ru  Tue May 21 04:27:25 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Tue, 21 May 2013 12:27:25 +0400
Subject: [PATCH] ARM: iomux-mx51: Always define PUE for pins used as GPIO
Message-ID: <1369124845-19244-1-git-send-email-shc_work@mail.ru>

This patch adds a PUE bit for pins which used as GPIO. This allow
to use the GPIOs correctly as inputs when source is open-drain with
external pullup resistor (IRQ open-drain outputs for example).

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-imx/iomux-mx51.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
index 75bbcc4..7dc187c 100644
--- a/arch/arm/mach-imx/iomux-mx51.h
+++ b/arch/arm/mach-imx/iomux-mx51.h
@@ -34,7 +34,8 @@
 #define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
 				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
-#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
+				PAD_CTL_PUE | PAD_CTL_SRE_FAST)
 
 #define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
 #define MX51_PAD_CTRL_3		(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-- 
1.8.1.5



From sameo at linux.intel.com  Tue May 21 09:02:28 2013
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Tue, 21 May 2013 15:02:28 +0200
Subject: Patch merge request for STE Snowball build failure on
 linux-arm-soc-for-next.
In-Reply-To: <CAMGVPmWRLddtZ3fS8DWovW=X7oQzy2x_-_SU60u+x9eTGaO9+A@mail.gmail.com>
References: <CAMGVPmWRLddtZ3fS8DWovW=X7oQzy2x_-_SU60u+x9eTGaO9+A@mail.gmail.com>
Message-ID: <20130521130228.GD4589@zurbaran>

Hi Botao,

On Tue, May 21, 2013 at 09:34:52PM +1000, Botao Sun wrote:
> Hi,
> 
> There is a build failure for STE Snowball on "linux-arm-soc-for-next"
> branch in Linaro Kernel CI system:
> 
> https://ci.linaro.org/jenkins/job/linux-arm-soc-for-next/hwpack=snowball,label=kernel_cloud/46/console
> 
> which is caused by:
> 
> 01:31:32
> /mnt/ci_build/workspace/linux-arm-soc-for-next/hwpack/snowball/label/kernel_cloud/drivers/mfd/ab8500-debugfs.c:95:23:
> fatal error: mach/irqs.h: No such file or directory
> 01:31:32  #include <mach/irqs.h>
> 01:31:32                        ^
> 01:31:32 compilation terminated.
> 01:31:32 make[3]: *** [drivers/mfd/ab8500-debugfs.o] Error 1
> 01:31:32 make[2]: *** [drivers/mfd] Error 2
> 01:31:32 make[1]: *** [drivers] Error 2
> 
> To solve this issue, here is the patch which Linux Walleij provided on 11
> April 2013:
> 
> https://lkml.org/lkml/2013/4/11/101
> 
> Would anyone like to merge the patch to fix this compiling error?
It is queued in mfd-fixes, and I will send a pull request for that either
tonight or tomorrow.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From catalin.marinas at arm.com  Tue May 21 09:15:40 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 14:15:40 +0100
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <519B48B4.6050607@asianux.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
 <519B278B.6030708@asianux.com>
 <20130521090336.GC10453@mudshark.cambridge.arm.com>
 <519B48B4.6050607@asianux.com>
Message-ID: <20130521131539.GC27002@arm.com>

On Tue, May 21, 2013 at 11:13:08AM +0100, Chen Gang wrote:
> On 05/21/2013 05:03 PM, Will Deacon wrote:
> > On Tue, May 21, 2013 at 08:51:39AM +0100, Chen Gang wrote:
> >> For me, I still recommend add 'ARM64' in the long list of architectures
> >> for 'VGA_CONSOLE', I have 3 reasons, please check:
> >>
> >> a. current implementation only changes one area which only related with
> >> arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
> >> touch many multiple platforms dependency, at least we need discuss about
> >> it with multiple platforms guys for it, firstly.
> > 
> > That's a weak argument. You might as well propose the cleanup and see what
> > people say.
> 
> Hmm.. I think at least, we need discuss it with the 'final applier'
> firstly (and now, I even do not know who is the 'final applier').

Well, you can post the patch to linux-arch, cc'ing the arch maintainers
whose Kconfig files you touch. If there are no comments, it will most
likely be picked by Andrew Morton and sent to Linus (make sure you cc
Andrew as well).

-- 
Catalin


From t.figa at samsung.com  Tue May 21 09:15:45 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 21 May 2013 15:15:45 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <CACRpkdbVnPhTMKDBtPNAka_V8H-2w2gK7prw9LVPRk_P7NMt7w@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1666561.1GujhmlVbA@flatron>
 <CACRpkdbVnPhTMKDBtPNAka_V8H-2w2gK7prw9LVPRk_P7NMt7w@mail.gmail.com>
Message-ID: <1738596.V1D84NEkmc@amdc1227>

Hi Linus,

On Tuesday 21 of May 2013 13:29:23 Linus Walleij wrote:
> On Fri, May 17, 2013 at 11:07 PM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> > On Friday 17 of May 2013 13:56:39 Doug Anderson wrote:
> >> I wouldn't be opposed to a re-spin to address some of the above, but I
> >> also won't object to this landing and remaining issues being addressed
> >> in future patches.  This patch definitely does make things better and
> >> no worse.  :)
> > 
> > Let's see. If nobody takes this until Monday, which is very likely, I will
> > send new version.
> 
> I applied 1 & 2 so pls repost your updated patches 3,4,5,6 on
> monday and let's continue fixing.

Thanks.

Feel free to apply current version of patches 3, 4 and 5 as well. I will post 
updated patch 6 in a while.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics
 
> Yours,
> Linus Walleij
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From catalin.marinas at arm.com  Tue May 21 09:17:34 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 14:17:34 +0100
Subject: [PATCH] arm64: compiling issue for allmodconfig, need
 "asm/parport.h" by "drivers/parport/parport_pc.c"
In-Reply-To: <5199A453.4080402@asianux.com>
References: <5177551D.8090007@asianux.com> <20130424082237.GA23397@arm.com>
 <5177B1F0.10106@asianux.com>
 <20130424102327.GF21850@mudshark.cambridge.arm.com>
 <5177BAD0.9000500@asianux.com> <20130424110511.GK23397@arm.com>
 <5199A453.4080402@asianux.com>
Message-ID: <20130521131734.GD27002@arm.com>

On Mon, May 20, 2013 at 05:19:31AM +0100, Chen Gang wrote:
> 
> Need add the default file in 'asm/Kbuild' just like arm has done.
> 
> The build command is:
>   make EXTRA_CFLAGS=-W ARCH=arm64 allmodconfig
>   make EXTRA_CFLAGS=-W ARCH=arm64 menuconfig
>     set "aarch64-linux-gnu-" as cross compiling prefix.
>   make EXTRA_CFLAGS=-W ARCH=arm64
> 
> The related error:
>   drivers/parport/parport_pc.c:67:25: fatal error: asm/parport.h: No such file or directory

As I don't see when we'd need this driver, you can probably change the
Kconfig entry (similar to the VGA_CONSOLE one).

Thanks.

-- 
Catalin


From catalin.marinas at arm.com  Tue May 21 09:19:31 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 14:19:31 +0100
Subject: [PATCH v4 13/32] arm64: KVM: MMIO access backend
In-Reply-To: <1368540840-26750-14-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-14-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521131930.GE27002@arm.com>

On Tue, May 14, 2013 at 03:13:41PM +0100, Marc Zyngier wrote:
> Define the necessary structures to perform an MMIO access.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From jason at lakedaemon.net  Tue May 21 09:14:55 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 09:14:55 -0400
Subject: [PATCH V3 00/10] mmc_of_parse() adaptations, DT support for
 Sheevaplugs
In-Reply-To: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130521131455.GP31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 01:01:41AM +0200, Simon Baatz wrote:
> Hi,
> 
> 	V3 changes:
> 	- Patch 01/10: Added EPROBE_DEFER case to mmc_of_parse() 
> 	- Added Acked-By to (unmodified) patches 02 and 03.
> 
> 	V2 changes:
> 	- Converted mvsdio to use mmc_of_parse()
> 	- Adapted DTS files using mvsdio accordingly
> 	- Changed mmc_of_parse() to return errors to the caller
> 
> While adding DT support for the Sheevaplugs by Globalscale Technologies
> (Kirkwood), it turned out that the DT binding of mvsdio lacked features to
> properly support the hardware (active high/low of CD and WP pins could not
> be described in DT).
> 
> This is standard functionality provided by the mmc_of_parse() helper
> function.  However, mmc_of_parse() may allocate GPIO lines.  If the
> allocation fails, it outputs an error, but does not return an error to its
> caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.
> 
> The patch set is structured as follows:
> 
> 1   Adapt mmc_of_parse() to return errors
> 2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
>     only)
> 7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
>     kirkwood)
> 9   Add dts files for (eSATA) Sheevaplug
> 10  Add DT support for (eSATA) Sheevaplug

Patches 7, 9, and 10 already pulled into mvebu/dt.  You can drop those
from this series if you need to do another revision.

> I could only test on an eSATA Sheevaplug. I found patches with
> different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
> someone with the hardware could give this a spin on a non-eSATA
> version.  

I happen to have one.  Unfortunately, it is currently my primary email
server, dhcp, dns, file server, and a few other irreplaceable things. :(
I *really* need to upgrade/reconfigure ...

thx,

Jason.


From mchehab at redhat.com  Tue May 21 06:21:49 2013
From: mchehab at redhat.com (Mauro Carvalho Chehab)
Date: Tue, 21 May 2013 07:21:49 -0300
Subject: [PATCH] Finally eradicate CONFIG_HOTPLUG
In-Reply-To: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
References: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
Message-ID: <20130521072149.0dac0d9e@redhat.com>

Em Tue, 21 May 2013 13:49:35 +1000
Stephen Rothwell <sfr at canb.auug.org.au> escreveu:

> Ever since commit 45f035ab9b8f ("CONFIG_HOTPLUG should be always on"),
> it has been basically impossible to build a kernel with CONFIG_HOTPLUG
> turned off.  Remove all the remaining references to it.
> 
> Cc: linux-arch at vger.kernel.org
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Doug Thompson <dougthompson at xmission.com>
> Cc: linux-edac at vger.kernel.org
> Cc: Bjorn Helgaas <bhelgaas at google.com>
> Cc: linux-pci at vger.kernel.org
> Cc: linux-pcmcia at lists.infradead.org
> Cc: Hans Verkuil <hans.verkuil at cisco.com>
> Cc: Steven Whitehouse <swhiteho at redhat.com>
> Cc: cluster-devel at redhat.com
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Pavel Machek <pavel at ucw.cz>
> Cc: "Rafael J. Wysocki" <rjw at sisk.pl>
> Cc: linux-pm at vger.kernel.org
> Cc: Andrew Morton <akpm at linux-foundation.org>
> Cc: linux-mm at kvack.org
> Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au>

Acked-by: Mauro Carvalho Chehab <mchehab at redhat.com>

Cheers,
Mauro


From jason at lakedaemon.net  Tue May 21 09:25:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 09:25:27 -0400
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 2)
In-Reply-To: <20130521064413.GF20453@quad.lixom.net>
References: <20130520195135.GH31290@titan.lakedaemon.net>
 <20130521064413.GF20453@quad.lixom.net>
Message-ID: <20130521132527.GQ31290@titan.lakedaemon.net>

Ezequiel,

On Mon, May 20, 2013 at 11:44:13PM -0700, Olof Johansson wrote:
> On Mon, May 20, 2013 at 03:51:35PM -0400, Jason Cooper wrote:
> > 
> > The following changes since commit 00ed4a0bd964555fe9276f2299564c384d50ae7d:
> > 
> >   ARM: mvebu: Add a ranges entry to translate devbus childs (2013-05-13 16:23:47 +0000)
> > 
> > are available in the git repository at:
> > 
> >   git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-2
> > 
> > for you to fetch changes up to 489e138eec96f529c5e8d4cd3ea45882ecdbf5ca:
> > 
> >   ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node (2013-05-20 17:44:54 +0000)
> 
> Pulled, thanks.
> 
> > 
> > ----------------------------------------------------------------
> > mvebu fixes for v3.10 (round 2)
> > 
> >  - mvebu (and orion SoCs)
> >     - remove init_dma_coherent_pool_size()
> > 
> >  - mvebu
> >     - fix ranges DT property
> 
> We've seen two of these now. Can someone please make a sweep and make sure
> there are no more of these pending?

Mind doing a sweep?  You've first hand knowledge of the devbus stuff.

thx,

Jason.


From csd at broadcom.com  Tue May 21 04:22:05 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 21 May 2013 01:22:05 -0700
Subject: [PATCH V2 1/2] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <201305170009.46244.arnd@arndb.de>
References: <1368200883-15668-1-git-send-email-csd@broadcom.com>
 <201305170009.46244.arnd@arndb.de>
Message-ID: <519B2EAD.4000208@broadcom.com>

Hi Arnd,
  Thanks for the review. See below for comments.

On 13-05-16 03:09 PM, Arnd Bergmann wrote:
> On Friday 10 May 2013, Christian Daudt wrote:
>> +
>> +struct sdhci_bcm_kona_cfg {
>> +	unsigned int	max_freq;
>> +	int		is_8bit;
>> +	int		irq;
>> +	int		cd_gpio;
>> +	int		wp_gpio;
>> +	int		non_removable;
>> +};
> I see no use for this structure to be separate: a lot of the fields are
> duplicated in the sdhci_host, or should just get merged into
> sdhci_bcm_kona_dev.
ok. Will do
>> +struct sdhci_bcm_kona_dev {
>> +	struct sdhci_bcm_kona_cfg *cfg;
>> +	struct device *dev;
>> +	struct sdhci_host *host;
>> +	struct clk *peri_clk;
>> +	struct clk *sleep_clk;
>> +};
> The *dev and *host members in this structure are redundant, just
> allocate it together with sdhci_host and use use container_of()
> to get from the sdhci_host back it it.
ok.
>> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
>> +{
>> +	unsigned int val;
>> +
>> +	/* enable the interrupt from the IP core */
>> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
>> +	val |= KONA_SDHOST_IP;
>> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
>> +
>> +	/* Enable the AHB clock gating module to the host */
>> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
>> +	val |= KONA_SDHOST_EN;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 */
>> +	mdelay(1);
>> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
>> +}
> Why not use msleep() instead of mdelay() here?
I don't think that there's any reason. will replace.
>
>> +static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
>> +{
>> +	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
>> +	struct sdhci_bcm_kona_dev *kona_dev = pltfm_priv->priv;
>> +	u32 val;
>> +	unsigned long flags;
>> +
>> +	/* this function can be called from various contexts including ISR */
>> +	spin_lock_irqsave(&host->lock, flags);
>> +	/* Ensure SD bus scanning to detect media change */
>> +	host->mmc->rescan_disable = 0;
>> +
>> +	/*
>> +	 * Back-to-Back register write needs a delay of min 10uS.
>> +	 * Back-to-Back writes to same register needs delay when SD bus clock
>> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
>> +	 * insert-removal.
>> +	 * We keep 20uS
>> +	 */
>> +	udelay(20);
>> +	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
> Does the delay have to be done with interrupts disabled? That is not particularly
> nice.
>
> I hope the hardware designers have been appropriately punished for the creating
> such crap.
I had some internal discussions on this one, and the code was originally 
written for non-threaded irqs. Now that it is only called as 
threaded_irq thread_fn, it is safe to replace the spinlock that includes 
the delay with a mutex instead.

>> +static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
>> +				u8 power_mode)
>> +{
>> +	if (power_mode == MMC_POWER_OFF)
>> +		return;
>> +	else
>> +		mdelay(10);
>> +}
> This requires at the minimum a comment about why the mdelay is needed.
> Maybe we can change the set_ios function so we never need to call it
> in atomic context.
I'll look into this one.
>> +static struct sdhci_bcm_kona_cfg * __init sdhci_bcm_kona_parse_dt(
>> +			struct platform_device *pdev)
>> +{
>> +	struct sdhci_bcm_kona_cfg *cfg;
>> +	struct device_node *np = pdev->dev.of_node;
>> +	u32 temp;
> fold this function into probe()
ok.
>> +	if (!np)
>> +		return NULL;
> impossible
ok
>> +	cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
>> +	if (!cfg) {
>> +		dev_err(&pdev->dev, "Can't allocate platform cfg\n");
>> +		return NULL;
>> +	}
> Not needed
what is not needed ?
>> +static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
>> +{
>> +	const struct of_device_id *match;
> constant, so not needed.
I'll remove it.
>> +	struct sdhci_bcm_kona_cfg *kona_cfg = NULL;
> No need to initialize this.
ok
>> +	const struct sdhci_pltfm_data *plat_data;
> make it global.
why make this global ?
>
>> +	struct sdhci_bcm_kona_dev *kona_dev = NULL;
> No need to initialize this.
ok.
>> +	kona_dev = devm_kzalloc(dev, sizeof(*kona_dev), GFP_KERNEL);
>> +	if (!kona_dev) {
>> +		dev_err(dev, "Can't allocate kona_dev\n");
>> +		ret = -ENOMEM;
>> +		goto err_pltfm_free;
>> +	}
> It is rather silly to have the base sdhci code allocate extra
> memory for the platform drivers but then require an extra allocation.
> Better change the sdhci_pltfm_init function to let you pass the extra
> allocation size.
ok, I'll look into this.
>> +MODULE_AUTHOR("Broadcom");
> No person?
>
A collective effort :)


  Thanks,
    csd




From g.liakhovetski at gmx.de  Tue May 21 06:37:42 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Tue, 21 May 2013 12:37:42 +0200 (CEST)
Subject: [PATCH 3/2] ARM: shmobile: r8a7790: add a "cpufreq-cpu0" platform
 device
In-Reply-To: <Pine.LNX.4.64.1305211206570.2863@axis700.grange>
References: <Pine.LNX.4.64.1305211202380.2863@axis700.grange>
 <Pine.LNX.4.64.1305211206570.2863@axis700.grange>
Message-ID: <Pine.LNX.4.64.1305211236180.2863@axis700.grange>

Add a "cpufreq-cpu0" platform device, needed to activate the equally named
CPUFreq driver.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---

It can actually be merged with patch 1 from this series

 arch/arm/mach-shmobile/setup-r8a7790.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index eeef5f6..49c3166 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -166,6 +166,7 @@ void __init r8a7790_timer_init(void)
 #ifdef CONFIG_USE_OF
 void __init r8a7790_add_standard_devices_dt(void)
 {
+	platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.7.2.5



From jason at lakedaemon.net  Tue May 21 09:42:44 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 09:42:44 -0400
Subject: [PATCH 1/9] arm: mvebu: fix length of SATA registers area in .dtsi
In-Reply-To: <1369132414-18959-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130521134244.GR31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 12:33:26PM +0200, Thomas Petazzoni wrote:
> The length of the registers area for the Marvell 370/XP SATA
> controller was incorrect in the .dtsi: 0x2400 while it should have
> been 0x5000. Until now, this problem wasn't noticed because there was
> a large static mapping for all I/Os set up by ->map_io(). But since
> we're going to get rid of this static mapping, we need to ensure that
> the register areas are properly sized.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Tue May 21 09:43:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 09:43:27 -0400
Subject: [PATCH 2/9] arm: mvebu: fix length of Ethernet registers area
 in .dtsi
In-Reply-To: <1369132414-18959-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130521134327.GS31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 12:33:27PM +0200, Thomas Petazzoni wrote:
> The length of the registers area for the Marvell 370/XP Ethernet
> controller was incorrect in the .dtsi: 0x2400 while it should have
> been 0x4000. Until now, this problem wasn't noticed because there was
> a large static mapping for all I/Os set up by ->map_io(). But since
> we're going to get rid of this static mapping, we need to ensure that
> the register areas are properly sized.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi     |    4 ++--
>  arch/arm/boot/dts/armada-xp-mv78460.dtsi |    2 +-
>  arch/arm/boot/dts/armada-xp.dtsi         |    2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Tue May 21 09:45:36 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 09:45:36 -0400
Subject: [PATCH 3/9] arm: mvebu: mark functions of armada-370-xp.c as
 static
In-Reply-To: <1369132414-18959-4-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-4-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130521134536.GT31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 12:33:28PM +0200, Thomas Petazzoni wrote:
> All the functions in armada-370-xp.c are called from the
> DT_MACHINE_START function pointers, so there is no need for them to be
> visible outside of this file, and we therefore mark them as static.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/mach-mvebu/armada-370-xp.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied to mvebu/cleanup

thx,

Jason.


From florian.vaussard at epfl.ch  Tue May 21 09:47:51 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Tue, 21 May 2013 15:47:51 +0200
Subject: [PATCH] arm: omap: board-overo: reset GPIO for SMSC911x
Message-ID: <1369144071-10673-1-git-send-email-florian.vaussard@epfl.ch>

The reset GPIO should be set for the SMSC911x, otherwise the controller
will not work and probing will fail. In the case of the tobi-duo
expansion board, the second controller shares the same GPIO, thus no
more changes are required (not tested).

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/mach-omap2/board-overo.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4ca6b68..5748b5d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -68,6 +68,7 @@
 
 #define OVERO_SMSC911X_CS      5
 #define OVERO_SMSC911X_GPIO    176
+#define OVERO_SMSC911X_NRESET  64
 #define OVERO_SMSC911X2_CS     4
 #define OVERO_SMSC911X2_GPIO   65
 
@@ -122,7 +123,7 @@ static struct omap_smsc911x_platform_data smsc911x_cfg = {
 	.id		= 0,
 	.cs             = OVERO_SMSC911X_CS,
 	.gpio_irq       = OVERO_SMSC911X_GPIO,
-	.gpio_reset     = -EINVAL,
+	.gpio_reset     = OVERO_SMSC911X_NRESET,
 	.flags		= SMSC911X_USE_32BIT,
 };
 
-- 
1.7.5.4



From josephl at nvidia.com  Tue May 21 06:13:35 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 21 May 2013 18:13:35 +0800
Subject: [PATCH] ARM: tegra: add cpu_disable for hotplug
Message-ID: <1369131215-2920-1-git-send-email-josephl@nvidia.com>

The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
support that. Adding a Tegra specific cpu_disable function for it.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
This patch depends on the series of "ARM: tegra114: add CPU hotplug support".
---
 arch/arm/mach-tegra/common.h  |  1 +
 arch/arm/mach-tegra/hotplug.c | 10 ++++++++++
 arch/arm/mach-tegra/platsmp.c |  1 +
 3 files changed, 12 insertions(+)

diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 5900cc4..32f8eb3 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops;
 
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d07f152..9695b63 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -46,6 +46,16 @@ void __ref tegra_cpu_die(unsigned int cpu)
 	BUG();
 }
 
+int tegra_cpu_disable(unsigned int cpu)
+{
+	switch (tegra_chip_id) {
+	case TEGRA114:
+		return 0;
+	default:
+		return cpu == 0 ? -EPERM : 0;
+	}
+}
+
 void __init tegra_hotplug_init(void)
 {
 	if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 554aedc..24db4ac 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -196,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= tegra_cpu_kill,
 	.cpu_die		= tegra_cpu_die,
+	.cpu_disable		= tegra_cpu_disable,
 #endif
 };
-- 
1.8.2.2



From tobetter at gmail.com  Tue May 21 09:56:04 2013
From: tobetter at gmail.com (Dongjin Kim)
Date: Tue, 21 May 2013 22:56:04 +0900
Subject: [PATCH] ARM: dts: add max77686 node entry for ODROID-X
Message-ID: <1369144571-16901-1-git-send-email-tobetter@gmail.com>

ODROID-X board have a max77686 PMIC on i2c channel 0. The properties of used
LDO and BUCK are defined according the schematic.

Signed-off-by: Dongjin Kim <tobetter at gmail.com>
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |  195 ++++++++++++++++++++++++++++++
 1 file changed, 195 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..1786225 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -108,4 +108,199 @@
 			clock-frequency = <24000000>;
 		};
 	};
+
+	i2c at 13860000 {
+		pinctrl-0 = <&i2c0_bus>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		max77686: pmic at 09 {
+			compatible = "maxim,max77686";
+			reg = <0x09>;
+
+			voltage-regulators {
+				ldo1_reg: LDO1 {
+					regulator-name = "VDD_ALIVE_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo2_reg: LDO2 {
+					regulator-name = "VDDQ_M1_2_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo3_reg: LDO3 {
+					regulator-name = "VDDQ_EXT_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo4_reg: LDO4 {
+					regulator-name = "VDDQ_MMC2_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo5_reg: LDO5 {
+					regulator-name = "VDDQ_MMC1_3_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo6_reg: LDO6 {
+					regulator-name = "VDD10_MPLL_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo7_reg: LDO7 {
+					regulator-name = "VDD10_XPLL_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo11_reg: LDO11 {
+					regulator-name = "VDD18_ABB1_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo12_reg: LDO12 {
+					regulator-name = "VDD33_USB_3.3V";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo13_reg: LDO13 {
+					regulator-name = "VDDQ_C2C_W_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo14_reg: LDO14 {
+					regulator-name = "VDD18_ABB0_2_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo15_reg: LDO15 {
+					regulator-name = "VDD10_HSIC_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo16_reg: LDO16 {
+					regulator-name = "VDD18_HSIC_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo20_reg: LDO20 {
+					regulator-name = "LDO20_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+				};
+
+				ldo21_reg: LDO21 {
+					regulator-name = "LDO21_3.3V";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo25_reg: LDO25 {
+					regulator-name = "VDDQ_LCD_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck1_reg: BUCK1 {
+					regulator-name = "vdd_mif";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck2_reg: BUCK2 {
+					regulator-name = "vdd_arm";
+					regulator-min-microvolt = <900000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck3_reg: BUCK3 {
+					regulator-name = "vdd_int";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck4_reg: BUCK4 {
+					regulator-name = "vdd_g3d";
+					regulator-min-microvolt = <900000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-microvolt-offset = <50000>;
+				};
+
+				buck5_reg: BUCK5 {
+					regulator-name = "VDDQ_CKEM1_2_1.2V";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck6_reg: BUCK6 {
+					regulator-name = "BUCK6_1.35V";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck7_reg: BUCK7 {
+					regulator-name = "BUCK7_2.0V";
+					regulator-min-microvolt = <2000000>;
+					regulator-max-microvolt = <2000000>;
+					regulator-always-on;
+				};
+
+				buck8_reg: BUCK8 {
+					regulator-name = "BUCK8_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+			};
+		};
+	};
 };
-- 
1.7.9.5



From prakash.pm at ti.com  Tue May 21 10:07:58 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 21 May 2013 19:37:58 +0530
Subject: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to
 configure multiple pins of different modules
Message-ID: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>

Based function-mask and submask preoperties patch allocates and registers pins.
Patch is fixes the issue reported and discussed here:
http://www.spinics.net/lists/arm-kernel/msg235213.html

Applies on top of 3.10-rc2 of linus's tree.

Tested on da850-evm.

Manjunathappa, Prakash (3):
  pinctrl: pinctrl-single: enhance to configure multiple pins of
    different     modules
  pinctrl: pinctrl-single: pin names for pinctrl-single.bits
  ARM: davinci: da850: adopt to pinctrl-single driver to configure
    multiple     pins

 .../devicetree/bindings/pinctrl/pinctrl-single.txt |    3 +-
 arch/arm/boot/dts/da850.dtsi                       |    2 +-
 drivers/pinctrl/pinctrl-single.c                   |  215 ++++++++++++++++----
 3 files changed, 179 insertions(+), 41 deletions(-)

-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 21 10:08:00 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 21 May 2013 19:38:00 +0530
Subject: [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple
 pins of different modules
In-Reply-To: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
References: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369145282-14419-3-git-send-email-prakash.pm@ti.com>

Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html

With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.

Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.

[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
(9e605cb68a21d5704839a192a46ebcf387773704),

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
Reported-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
Tested-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
---
 .../devicetree/bindings/pinctrl/pinctrl-single.txt |    3 +-
 drivers/pinctrl/pinctrl-single.c                   |  198 ++++++++++++++++----
 2 files changed, 167 insertions(+), 34 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 08f0c3d..5a02e30 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -18,7 +18,8 @@ Optional properties:
   pin functions is ignored
 
 - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
-  more than one pin
+  more than one pin, for which "pinctrl-single,function-mask" property specifies
+ position mask of pin.
 
 - pinctrl-single,drive-strength : array of value that are used to configure
   drive strength in the pinmux register. They're value of drive strength
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index b9fa046..9a1ea65 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -163,6 +163,7 @@ struct pcs_name {
  * @foff:	value to turn mux off
  * @fmax:	max number of functions in fmask
  * @is_pinconf:	whether supports pinconf
+ * @bits_per_pin:number of bits per pin
  * @names:	array of register names for pins
  * @pins:	physical pins on the SoC
  * @pgtree:	pingroup index radix tree
@@ -190,6 +191,7 @@ struct pcs_device {
 	unsigned fmax;
 	bool bits_per_mux;
 	bool is_pinconf;
+	unsigned bits_per_pin;
 	struct pcs_name *names;
 	struct pcs_data pins;
 	struct radix_tree_root pgtree;
@@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
 
 		vals = &func->vals[i];
 		val = pcs->read(vals->reg);
-		if (!vals->mask)
-			mask = pcs->fmask;
+
+		if (pcs->bits_per_mux)
+			mask = vals->mask;
 		else
-			mask = pcs->fmask & vals->mask;
+			mask = pcs->fmask;
 
 		val &= ~mask;
 		val |= (vals->val & mask);
@@ -779,7 +782,13 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
 	int mux_bytes, nr_pins, i;
 
 	mux_bytes = pcs->width / BITS_PER_BYTE;
-	nr_pins = pcs->size / mux_bytes;
+
+	if (pcs->bits_per_mux) {
+		pcs->bits_per_pin = fls(pcs->fmask);
+		nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
+	} else {
+		nr_pins = pcs->size / mux_bytes;
+	}
 
 	dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 	pcs->pins.pa = devm_kzalloc(pcs->dev,
@@ -800,8 +809,14 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
 	for (i = 0; i < pcs->desc.npins; i++) {
 		unsigned offset;
 		int res;
+		int byte_num;
 
-		offset = i * mux_bytes;
+		if (pcs->bits_per_mux) {
+			byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
+			offset = (byte_num / mux_bytes) * mux_bytes;
+		} else {
+			offset = i * mux_bytes;
+		}
 		res = pcs_add_pin(pcs, offset);
 		if (res < 0) {
 			dev_err(pcs->dev, "error adding pins: %i\n", res);
@@ -919,7 +934,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 		return -EINVAL;
 	}
 
-	index = offset / (pcs->width / BITS_PER_BYTE);
+	if (pcs->bits_per_mux)
+		index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
+	else
+		index = offset / (pcs->width / BITS_PER_BYTE);
 
 	return index;
 }
@@ -1097,29 +1115,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 {
 	struct pcs_func_vals *vals;
 	const __be32 *mux;
-	int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
+	int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
 	struct pcs_function *function;
 
-	if (pcs->bits_per_mux) {
-		params = 3;
-		mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
-	} else {
-		params = 2;
-		mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
-	}
-
-	if (!mux) {
-		dev_err(pcs->dev, "no valid property for %s\n", np->name);
-		return -EINVAL;
-	}
-
-	if (size < (sizeof(*mux) * params)) {
-		dev_err(pcs->dev, "bad data for %s\n", np->name);
+	mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
+	if ((!mux) || (size < sizeof(*mux) * 2)) {
+		dev_err(pcs->dev, "bad data for mux %s\n",
+			np->name);
 		return -EINVAL;
 	}
 
 	size /= sizeof(*mux);	/* Number of elements in array */
-	rows = size / params;
+	rows = size / 2;
 
 	vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
 	if (!vals)
@@ -1137,10 +1144,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 		val = be32_to_cpup(mux + index++);
 		vals[found].reg = pcs->base + offset;
 		vals[found].val = val;
-		if (params == 3) {
-			val = be32_to_cpup(mux + index++);
-			vals[found].mask = val;
-		}
 
 		pin = pcs_get_pin_by_offset(pcs, offset);
 		if (pin < 0) {
@@ -1189,6 +1192,125 @@ free_vals:
 
 	return res;
 }
+
+#define PARAMS_FOR_BITS_PER_MUX 3
+
+static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
+						struct device_node *np,
+						struct pinctrl_map **map,
+						unsigned *num_maps,
+						const char **pgnames)
+{
+	struct pcs_func_vals *vals;
+	const __be32 *mux;
+	int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
+	int npins_in_row;
+	struct pcs_function *function;
+
+	mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
+
+	if (!mux) {
+		dev_err(pcs->dev, "no valid property for %s\n", np->name);
+		return -EINVAL;
+	}
+
+	if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
+		dev_err(pcs->dev, "bad data for %s\n", np->name);
+		return -EINVAL;
+	}
+
+	/* Number of elements in array */
+	size /= sizeof(*mux);
+
+	rows = size / PARAMS_FOR_BITS_PER_MUX;
+	npins_in_row = pcs->width / pcs->bits_per_pin;
+
+	vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
+			GFP_KERNEL);
+	if (!vals)
+		return -ENOMEM;
+
+	pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
+			GFP_KERNEL);
+	if (!pins)
+		goto free_vals;
+
+	while (index < size) {
+		unsigned offset, val;
+		unsigned mask, bit_pos, val_pos, mask_pos, submask;
+		unsigned pin_num_from_lsb;
+		int pin;
+
+		offset = be32_to_cpup(mux + index++);
+		val = be32_to_cpup(mux + index++);
+		mask = be32_to_cpup(mux + index++);
+
+		/* Parse pins in each row from LSB */
+		while (mask) {
+			bit_pos = ffs(mask);
+			pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
+			mask_pos = ((pcs->fmask) << (bit_pos - 1));
+			val_pos = val & mask_pos;
+			submask = mask & mask_pos;
+			mask &= ~mask_pos;
+
+			if (submask != mask_pos) {
+				dev_warn(pcs->dev,
+						"Invalid submask 0x%x for %s at 0x%x\n",
+						submask, np->name, offset);
+				continue;
+			}
+
+			vals[found].mask = submask;
+			vals[found].reg = pcs->base + offset;
+			vals[found].val = val_pos;
+
+			pin = pcs_get_pin_by_offset(pcs, offset);
+			if (pin < 0) {
+				dev_err(pcs->dev,
+					"could not add functions for %s %ux\n",
+					np->name, offset);
+				break;
+			}
+			pins[found++] = pin + pin_num_from_lsb;
+		}
+	}
+
+	pgnames[0] = np->name;
+	function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
+	if (!function)
+		goto free_pins;
+
+	res = pcs_add_pingroup(pcs, np, np->name, pins, found);
+	if (res < 0)
+		goto free_function;
+
+	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
+	(*map)->data.mux.group = np->name;
+	(*map)->data.mux.function = np->name;
+
+	if (pcs->is_pinconf) {
+		dev_err(pcs->dev, "pinconf not supported\n");
+		goto free_pingroups;
+	}
+
+	*num_maps = 1;
+	return 0;
+
+free_pingroups:
+	pcs_free_pingroups(pcs);
+	*num_maps = 1;
+free_function:
+	pcs_remove_function(pcs, function);
+
+free_pins:
+	devm_kfree(pcs->dev, pins);
+
+free_vals:
+	devm_kfree(pcs->dev, vals);
+
+	return res;
+}
 /**
  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
  * @pctldev: pinctrl instance
@@ -1219,12 +1341,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 		goto free_map;
 	}
 
-	ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps,
-					  pgnames);
-	if (ret < 0) {
-		dev_err(pcs->dev, "no pins entries for %s\n",
-			np_config->name);
-		goto free_pgnames;
+	if (pcs->bits_per_mux) {
+		ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
+				num_maps, pgnames);
+		if (ret < 0) {
+			dev_err(pcs->dev, "no pins entries for %s\n",
+				np_config->name);
+			goto free_pgnames;
+		}
+	} else {
+		ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
+				num_maps, pgnames);
+		if (ret < 0) {
+			dev_err(pcs->dev, "no pins entries for %s\n",
+				np_config->name);
+			goto free_pgnames;
+		}
 	}
 
 	return 0;
-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 21 10:08:01 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 21 May 2013 19:38:01 +0530
Subject: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits
In-Reply-To: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
References: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369145282-14419-4-git-send-email-prakash.pm@ti.com>

Take care to name pin names as
register-offset.bit-pos-of-pin-in-register in case configuring multiple
pins in register.

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
 drivers/pinctrl/pinctrl-single.c |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 9a1ea65..2899c86 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -30,7 +30,7 @@
 #define DRIVER_NAME			"pinctrl-single"
 #define PCS_MUX_PINS_NAME		"pinctrl-single,pins"
 #define PCS_MUX_BITS_NAME		"pinctrl-single,bits"
-#define PCS_REG_NAME_LEN		((sizeof(unsigned long) * 2) + 1)
+#define PCS_REG_NAME_LEN		((sizeof(unsigned long) * 2) + 3)
 #define PCS_OFF_DISABLED		~0U
 
 /**
@@ -744,7 +744,8 @@ static const struct pinconf_ops pcs_pinconf_ops = {
  * @pcs: pcs driver instance
  * @offset: register offset from base
  */
-static int pcs_add_pin(struct pcs_device *pcs, unsigned offset)
+static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
+		unsigned pin_pos)
 {
 	struct pinctrl_pin_desc *pin;
 	struct pcs_name *pn;
@@ -759,8 +760,8 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset)
 
 	pin = &pcs->pins.pa[i];
 	pn = &pcs->names[i];
-	sprintf(pn->name, "%lx",
-		(unsigned long)pcs->res->start + offset);
+	sprintf(pn->name, "%lx.%d",
+		(unsigned long)pcs->res->start + offset, pin_pos);
 	pin->name = pn->name;
 	pin->number = i;
 	pcs->pins.cur++;
@@ -780,12 +781,14 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset)
 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 {
 	int mux_bytes, nr_pins, i;
+	int num_pins_in_register = 0;
 
 	mux_bytes = pcs->width / BITS_PER_BYTE;
 
 	if (pcs->bits_per_mux) {
 		pcs->bits_per_pin = fls(pcs->fmask);
 		nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
+		num_pins_in_register = pcs->width / pcs->bits_per_pin;
 	} else {
 		nr_pins = pcs->size / mux_bytes;
 	}
@@ -810,14 +813,16 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
 		unsigned offset;
 		int res;
 		int byte_num;
+		int pin_pos = 0;
 
 		if (pcs->bits_per_mux) {
 			byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 			offset = (byte_num / mux_bytes) * mux_bytes;
+			pin_pos = i % num_pins_in_register;
 		} else {
 			offset = i * mux_bytes;
 		}
-		res = pcs_add_pin(pcs, offset);
+		res = pcs_add_pin(pcs, offset, pin_pos);
 		if (res < 0) {
 			dev_err(pcs->dev, "error adding pins: %i\n", res);
 			return res;
-- 
1.7.4.1



From g.liakhovetski at gmx.de  Tue May 21 10:07:46 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Tue, 21 May 2013 16:07:46 +0200 (CEST)
Subject: [PATCH v2 1/2] ARM: shmobile: r8a7790: implement CPU clock scaling
 for CPUFreq
Message-ID: <Pine.LNX.4.64.1305211601180.2863@axis700.grange>

This patch adds support for the Z-clock on r8a7790 SoCs, which is driving
the Cortex A15 core, and a "cpufreq-cpu0" platform device. Adding an
"operating-points" property to the CPU0 DT node and a regulator, this
patch allows platforms to use the generic cpufreq-cpu0 driver to use
SoC's DVFS capabilities.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---

v2:
1. a typo in the r8a7790 datasheet confused me to implement kick-bit 
handling wrongly, this is fixed in this version
2. patch 3 merged with this one

Same comments, as to v1 of this series, apply.

 arch/arm/mach-shmobile/Kconfig         |    2 +
 arch/arm/mach-shmobile/clock-r8a7790.c |  129 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/setup-r8a7790.c |    1 +
 3 files changed, 132 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0319cf9..97bc6cf 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -60,6 +60,8 @@ config ARCH_R8A7790
 	select ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_OPP
 
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 53a13b4..0f2aa68 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -47,6 +47,9 @@
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
+#define FRQCRB   0xe6150004
+#define FRQCRC   0xe61500e0
+
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
@@ -83,11 +86,132 @@ static struct clk main_clk = {
  * clock ratio of these clock will be updated
  * on r8a7790_clock_init()
  */
+SH_FIXED_RATIO_CLK_SET(pll0_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(lb_clk,			pll1_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);
 
+/* If more clocks need to access FRQCRB, we'll have to lock eventually */
+static int frqcr_kick_check(struct clk *clk)
+{
+	return ioread32(clk->mapped_reg) & BIT(31) ? -EBUSY : 0;
+}
+
+static int frqcr_kick_do(struct clk *clk)
+{
+	int i;
+
+	/* set KICK bit in FRQCRB to update hardware setting, check success */
+	iowrite32(ioread32(clk->mapped_reg) | BIT(31), clk->mapped_reg);
+	for (i = 1000; i; i--)
+		if (ioread32(clk->mapped_reg) & BIT(31))
+			cpu_relax();
+		else
+			return 0;
+
+	return -ETIMEDOUT;
+}
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	void __iomem *frqcrc;
+	int ret;
+	unsigned long step, p_rate;
+	u32 val;
+
+	if (!clk->parent || !__clk_get(clk->parent))
+		return -ENODEV;
+
+	ret = frqcr_kick_check(clk);
+	if (ret < 0)
+		goto done;
+
+	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
+	p_rate = clk_get_rate(clk->parent);
+	if (rate == p_rate) {
+		val = 0;
+	} else {
+		step = DIV_ROUND_CLOSEST(p_rate, 32);
+		val = 32 - rate / step;
+	}
+
+	iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
+		  (val << clk->enable_bit), frqcrc);
+
+	ret = frqcr_kick_do(clk);
+
+done:
+	__clk_put(clk->parent);
+	return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	/*
+	 * theoretical rate = parent rate * multiplier / 32,
+	 * where 1 <= multiplier <= 32. Therefore we should do
+	 * multiplier = rate * 32 / parent rate
+	 * rounded rate = parent rate * multiplier / 32.
+	 * However, multiplication before division won't fit in 32 bits, so
+	 * we sacrifice some precision by first dividing and then multiplying.
+	 * To find the nearest divisor we calculate both and pick up the best
+	 * one. This avoids 64-bit arithmetics.
+	 */
+	unsigned long step, mul_min, mul_max, rate_min, rate_max;
+
+	rate_max = clk_get_rate(clk->parent);
+
+	/* output freq <= parent */
+	if (rate >= rate_max)
+		return rate_max;
+
+	step = DIV_ROUND_CLOSEST(rate_max, 32);
+	/* output freq >= parent / 32 */
+	if (step >= rate)
+		return step;
+
+	mul_min = rate / step;
+	mul_max = DIV_ROUND_UP(rate, step);
+	rate_min = step * mul_min;
+	if (mul_max == mul_min)
+		return rate_min;
+
+	rate_max = step * mul_max;
+
+	if (rate_max - rate <  rate - rate_min)
+		return rate_max;
+
+	return rate_min;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+	void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
+	unsigned int max = clk->div_mask + 1;
+	unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
+			     clk->div_mask);
+
+	return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
+		(max - val);
+}
+
+static struct sh_clk_ops zclk_ops = {
+	.recalc = zclk_recalc,
+	.set_rate = zclk_set_rate,
+	.round_rate = zclk_round_rate,
+};
+
+static struct clk z_clk = {
+	.parent = &pll0_clk,
+	.div_mask = 0x1f,
+	.enable_bit = 8,
+	/* We'll need to access FRQCRB and FRQCRC */
+	.enable_reg = (void __iomem *)FRQCRB,
+	.ops = &zclk_ops,
+};
+
 /* fixed ratio clock */
 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
 SH_FIXED_RATIO_CLK_SET(cp_clk,			extal_clk,	1, 2);
@@ -115,11 +239,13 @@ static struct clk *main_clks[] = {
 	&extal_clk,
 	&extal_div2_clk,
 	&main_clk,
+	&pll0_clk,
 	&pll1_clk,
 	&pll1_div2_clk,
 	&pll3_clk,
 	&lb_clk,
 	&qspi_clk,
+	&z_clk,
 	&zg_clk,
 	&zx_clk,
 	&zs_clk,
@@ -213,6 +339,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("pll1",		&pll1_clk),
 	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),
 	CLKDEV_CON_ID("pll3",		&pll3_clk),
+	CLKDEV_DEV_ID("cpufreq-cpu0",	&z_clk),
 	CLKDEV_CON_ID("zg",		&zg_clk),
 	CLKDEV_CON_ID("zx",		&zx_clk),
 	CLKDEV_CON_ID("zs",		&zs_clk),
@@ -263,9 +390,11 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 };
 
+/* "/ 2" is a "fixed divider" - see the "PLL Multiplication Ratio" table */
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
 	extal_clk.rate	= e * 1000 * 1000;			\
 	main_clk.parent	= m;					\
+	SH_CLK_SET_RATIO(&pll0_clk_ratio, p0 / 2, 1);		\
 	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);		\
 	if (mode & MD(19))					\
 		SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);	\
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index eeef5f6..49c3166 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -166,6 +166,7 @@ void __init r8a7790_timer_init(void)
 #ifdef CONFIG_USE_OF
 void __init r8a7790_add_standard_devices_dt(void)
 {
+	platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.7.2.5



From prakash.pm at ti.com  Tue May 21 10:08:02 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 21 May 2013 19:38:02 +0530
Subject: [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to
 configure multiple pins
In-Reply-To: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
References: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369145282-14419-5-git-send-email-prakash.pm@ti.com>

function-mask property is a mask for a pin at each pin configure offset
in a pincontrol register.

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
 arch/arm/boot/dts/da850.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 4d43046..9bec36c 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -37,7 +37,7 @@
 			#size-cells = <0>;
 			pinctrl-single,bit-per-mux;
 			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0xffffffff>;
+			pinctrl-single,function-mask = <0xf>;
 			status = "disabled";
 
 			nand_cs3_pins: pinmux_nand_pins {
-- 
1.7.4.1



From jason at lakedaemon.net  Tue May 21 10:16:21 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 10:16:21 -0400
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus
 initialization later
In-Reply-To: <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130521141621.GU31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 12:33:31PM +0200, Thomas Petazzoni wrote:
> Current, the L2 cache and the mvebu-mbus drivers are initialized at
> ->init_early() time. However, at ->init_early() time, ioremap() only
> works if a static I/O mapping has already been put in place. If it's
> not the case, it tries to do a memory allocation with kmalloc() which
> is not possible so early at this stage of the initialization.
> 
> Since we want to get rid of the static I/O mapping, we cannot
> initialize the L2 cache driver and the mvebu-mbus driver so early. So,
> we move their initialization to the ->init_time() level, which is
> slightly later (so ioremap() works properly), but sufficiently early
> to be before the call of the ->smp_prepare_cpus() hook, which creates
> an address decoding window for the BootROM, which requires the
> mvebu-mbus driver to be properly initialized.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/mach-mvebu/armada-370-xp.c |   24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)

This doesn't apply when based on mvebu/cleanup because of:

  49ed97f ARM: Orion: Remove redundant init_dma_coherent_pool_size()

I tried hacking it up to put it in mvebu/soc-internal_regs for a few
rounds of testing in linux-next during review, however, I'd prefer you
rebase this on top of mvebu/cleanup.

My version ended up looking like:

---8<----
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index b9319c4..75ebf56 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -44,14 +44,11 @@ static void __init armada_370_xp_map_io(void)
 
 static void __init armada_370_xp_timer_and_clk_init(void)
 {
+	char *mbus_soc_name;
+
 	mvebu_clocks_init();
 	armada_370_xp_timer_init();
 	coherency_init();
-}
-
-static void __init armada_370_xp_init_early(void)
-{
-	char *mbus_soc_name;
 
 	/*
 	 * This initialization will be replaced by a DT-based
@@ -87,7 +84,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
 	.smp		= smp_ops(armada_xp_smp_ops),
 	.init_machine	= armada_370_xp_dt_init,
 	.map_io		= armada_370_xp_map_io,
-	.init_early	= armada_370_xp_init_early,
 	.init_time	= armada_370_xp_timer_and_clk_init,
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_370_xp_dt_compat,


From prakash.pm at ti.com  Tue May 21 10:16:58 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 21 May 2013 14:16:58 +0000
Subject: Query on pinctrl usage for DT nodes
In-Reply-To: <20130423181753.GK10155@atomide.com>
References: <CA+V-a8uiPwsAD--OHFAE=i2ed+-wbXm4p2deZXr92+Zv6GDS1w@mail.gmail.com>
 <515C5C76.3080009@wwwdotorg.org>
 <CA+V-a8t3wtP77DdeUoQHKMjAuWmV+ude+1J3UjJmMTqobgStjA@mail.gmail.com>
 <5162FD4A.1030909@wwwdotorg.org>
 <CA+V-a8vwdCkyMqiynj5BodXbjwJ=e4qNb-29FhLweqbjc7DBQA@mail.gmail.com>
 <5165A22B.4070200@wwwdotorg.org> <20130410203408.GP10155@atomide.com>
 <516BB99F.2080502@ti.com> <20130416213232.GU10155@atomide.com>
 <51763B7B.707@ti.com> <20130423181753.GK10155@atomide.com>
Message-ID: <A73F36158E33644199EB82C5EC81C7BC3EA661EB@DBDE04.ent.ti.com>

Hi,

On Tue, Apr 23, 2013 at 23:47:54, Tony Lindgren wrote:
> * Peter Ujfalusi <peter.ujfalusi at ti.com> [130423 00:47]:
> > On 04/16/2013 11:32 PM, Tony Lindgren wrote:
> > > * Peter Ujfalusi <peter.ujfalusi at ti.com> [130415 01:30]:
> > >> On 04/10/2013 10:34 PM, Tony Lindgren wrote:
> > >>> Yeah how about just change the pintctrl-single,bits register
> > >>> naming to be register + bit?  Something like 0xdeadbeef.0 and
> > >>> 0xdeadbeef.1 and so on.
> > >>
> > >> Something like this might work I think. It is going to be a bit tricky IMHO
> > >> since we might need span out new 'register' every time a device requests for a
> > >> new pinctrl-single,bits for already used register in the
> > >> pinctrl-single,bit-per-mux area. In this way we still can make sure that
> > >> certain bit are only used by a single driver.
> > > 
> > > OK. If it's one bit per mux type register we should be able to create
> > > the right amount of entries based on the submask in pinctrs-single,bit?
> > 
> > Right now it seams to be true that we have one bit per mux (in DEVCONF0 on
> > OMAP3 for example). So that would work fine, but There could be different
> > registers around with more than one bit per mux.
> 
> Yes you are right, we should cover that case too. But maybe we
> can wait until we have such an example :)
>  
> > Another way to deal with this is to:
> > in case of pinctrl-single,bit-per-mux we assume one bit per mux and create
> > entries based on the pinctrl-single,function-mask's bits.
> > 
> > In case we have more than one bit for the mux in the register we could have
> > optional property stating the number of different muxes handled by the register.
> 
> Yes that's doable.
>  
> > One bit per mux type:
> > 
> > control_devconf0: pinmux at 48002274 {
> >         compatible = "pinctrl-single";
> >         reg = <0x48002274 4>;   /* Single register */
> >         #address-cells = <1>;
> >         #size-cells = <0>;
> >         pinctrl-single,bit-per-mux;
> >         pinctrl-single,register-width = <32>;
> >         pinctrl-single,function-mask = <0x5F>;
> > };
> > 
> > Results six entries.
> 
> Yup, I think this is the way to go for now, see below..
>  
> > control_devconf0: pinmux at 48002274 {
> >         compatible = "pinctrl-single";
> >         reg = <0x48002274 4>;   /* Single register */
> >         #address-cells = <1>;
> >         #size-cells = <0>;
> >         pinctrl-single,bit-per-mux;
> >         pinctrl-single,functions-in-register = <3>;
> >         pinctrl-single,register-width = <32>;
> >         pinctrl-single,function-mask = <0x5F>;
> > };
> > 
> > Will results three entries.
> 
> ..but let's not add this. The reason why I'd like to postpone adding
> pinctrl-single,functions-in-register is because we may be able to
> do it automatically.
> 

I have posted patch to take care of this:
http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-0-3-pinctrl-pinctrl-single-Add-full-fledge-support-to-configure-multiple-pins-of-different-mods-tt7583066.html

Please review this solution.

Thanks,
Prakash


From g.liakhovetski at gmx.de  Tue May 21 06:09:53 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Tue, 21 May 2013 12:09:53 +0200 (CEST)
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: implement CPU clock scaling for
 CPUFreq
Message-ID: <Pine.LNX.4.64.1305211202380.2863@axis700.grange>

This patch adds support for the Z-clock on r8a7790 SoCs, which is driving
the Cortex A15 core. Adding an "operating-points" property to the CPU0 DT
node and a regulator, this patch allows platforms to use the generic
cpufreq-cpu0 driver to use SoC's DVFS capabilities.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---

Since I cannot use the regulator, supplying the DVFS voltage to the CPU on 
Lager, I only tested this patch without voltage adjustments, but that 
shouldn't matter for this specific change. I did verify, using the 
ondemand CPUFreq governor, that the frequency and the CPU performance 
change, depending on CPU load.

 arch/arm/mach-shmobile/Kconfig         |    2 +
 arch/arm/mach-shmobile/clock-r8a7790.c |  134 ++++++++++++++++++++++++++++++++
 2 files changed, 136 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0319cf9..97bc6cf 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -60,6 +60,8 @@ config ARCH_R8A7790
 	select ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_OPP
 
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 53a13b4..d78d6ff 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -47,6 +47,9 @@
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
+#define FRQCRB   0xe6150004
+#define FRQCRC   0xe61500e0
+
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
@@ -83,11 +86,137 @@ static struct clk main_clk = {
  * clock ratio of these clock will be updated
  * on r8a7790_clock_init()
  */
+SH_FIXED_RATIO_CLK_SET(pll0_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(lb_clk,			pll1_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);
 
+/* If more clocks need to access FRQCRB, we'll have to lock eventually */
+static int frqcr_kick_check(struct clk *clk)
+{
+	return ioread32(clk->mapped_reg) & BIT(31) ? -EBUSY : 0;
+}
+
+static int frqcr_kick_do(struct clk *clk)
+{
+	int i;
+
+	/* set KICK bit in FRQCRB to update hardware setting, check success */
+	iowrite32(ioread32(clk->mapped_reg) | BIT(31), clk->mapped_reg);
+	for (i = 1000; i; i--)
+		if (!(ioread32(clk->mapped_reg) & BIT(31)))
+			cpu_relax();
+		else
+			break;
+
+	if (!i)
+		return -ETIMEDOUT;
+
+	iowrite32(ioread32(clk->mapped_reg) & ~BIT(31), clk->mapped_reg);
+
+	return 0;
+}
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	void __iomem *frqcrc;
+	int ret;
+	unsigned long step, p_rate;
+	u32 val;
+
+	if (!clk->parent || !__clk_get(clk->parent))
+		return -ENODEV;
+
+	ret = frqcr_kick_check(clk);
+	if (ret < 0)
+		goto done;
+
+	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
+	p_rate = clk_get_rate(clk->parent);
+	if (rate == p_rate) {
+		val = 0;
+	} else {
+		step = DIV_ROUND_CLOSEST(p_rate, 32);
+		val = 32 - rate / step;
+	}
+
+	iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
+		  (val << clk->enable_bit), frqcrc);
+
+	ret = frqcr_kick_do(clk);
+
+done:
+	__clk_put(clk->parent);
+	return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	/*
+	 * theoretical rate = parent rate * multiplier / 32,
+	 * where 1 <= multiplier <= 32. Therefore we should do
+	 * multiplier = rate * 32 / parent rate
+	 * rounded rate = parent rate * multiplier / 32.
+	 * However, multiplication before division won't fit in 32 bits, so
+	 * we sacrifice some precision by first dividing and then multiplying.
+	 * To find the nearest divisor we calculate both and pick up the best
+	 * one. This avoids 64-bit arithmetics.
+	 */
+	unsigned long step, mul_min, mul_max, rate_min, rate_max;
+
+	rate_max = clk_get_rate(clk->parent);
+
+	/* output freq <= parent */
+	if (rate >= rate_max)
+		return rate_max;
+
+	step = DIV_ROUND_CLOSEST(rate_max, 32);
+	/* output freq >= parent / 32 */
+	if (step >= rate)
+		return step;
+
+	mul_min = rate / step;
+	mul_max = DIV_ROUND_UP(rate, step);
+	rate_min = step * mul_min;
+	if (mul_max == mul_min)
+		return rate_min;
+
+	rate_max = step * mul_max;
+
+	if (rate_max - rate <  rate - rate_min)
+		return rate_max;
+
+	return rate_min;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+	void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
+	unsigned int max = clk->div_mask + 1;
+	unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
+			     clk->div_mask);
+
+	return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
+		(max - val);
+}
+
+static struct sh_clk_ops zclk_ops = {
+	.recalc = zclk_recalc,
+	.set_rate = zclk_set_rate,
+	.round_rate = zclk_round_rate,
+};
+
+static struct clk z_clk = {
+	.parent = &pll0_clk,
+	.div_mask = 0x1f,
+	.enable_bit = 8,
+	/* We'll need to access FRQCRB and FRQCRC */
+	.enable_reg = (void __iomem *)FRQCRB,
+	.ops = &zclk_ops,
+};
+
 /* fixed ratio clock */
 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
 SH_FIXED_RATIO_CLK_SET(cp_clk,			extal_clk,	1, 2);
@@ -115,11 +244,13 @@ static struct clk *main_clks[] = {
 	&extal_clk,
 	&extal_div2_clk,
 	&main_clk,
+	&pll0_clk,
 	&pll1_clk,
 	&pll1_div2_clk,
 	&pll3_clk,
 	&lb_clk,
 	&qspi_clk,
+	&z_clk,
 	&zg_clk,
 	&zx_clk,
 	&zs_clk,
@@ -213,6 +344,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("pll1",		&pll1_clk),
 	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),
 	CLKDEV_CON_ID("pll3",		&pll3_clk),
+	CLKDEV_DEV_ID("cpufreq-cpu0",	&z_clk),
 	CLKDEV_CON_ID("zg",		&zg_clk),
 	CLKDEV_CON_ID("zx",		&zx_clk),
 	CLKDEV_CON_ID("zs",		&zs_clk),
@@ -263,9 +395,11 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 };
 
+/* "/ 2" is a "fixed divider" - see the "PLL Multiplication Ratio" table */
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
 	extal_clk.rate	= e * 1000 * 1000;			\
 	main_clk.parent	= m;					\
+	SH_CLK_SET_RATIO(&pll0_clk_ratio, p0 / 2, 1);		\
 	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);		\
 	if (mode & MD(19))					\
 		SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);	\
-- 
1.7.2.5



From catalin.marinas at arm.com  Tue May 21 10:30:16 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 15:30:16 +0100
Subject: [PATCH v4 14/32] arm64: KVM: guest one-reg interface
In-Reply-To: <1368540840-26750-15-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-15-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521143015.GF27002@arm.com>

On Tue, May 14, 2013 at 03:13:42PM +0100, Marc Zyngier wrote:
> Let userspace play with the guest registers.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> --- /dev/null
> +++ b/arch/arm64/kvm/guest.c
...
> +static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
> +{
> +	__u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
> +	struct kvm_regs *regs = vcpu_gp_regs(vcpu);
> +	int nr_regs = sizeof(*regs) / sizeof(__u32);

Was there any conclusion on using __u32 rather than __u64 here? At least
you should add a comment since it's slightly confusing.

-- 
Catalin


From tony at atomide.com  Tue May 21 10:34:40 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 21 May 2013 07:34:40 -0700
Subject: [GIT PULL] omap fixes for v3.10-rc1
In-Reply-To: <20130521063732.GD20453@quad.lixom.net>
References: <20130517192515.GC5600@atomide.com>
 <20130521063732.GD20453@quad.lixom.net>
Message-ID: <20130521143439.GO10378@atomide.com>

* Olof Johansson <olof at lixom.net> [130520 23:43]:
> On Fri, May 17, 2013 at 12:25:16PM -0700, Tony Lindgren wrote:
> > The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> > 
> >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.10-rc1/fixes
> 
> Well, it's for -rc3 now but it can never have been for -rc1 since that's
> what the branch is base on. :-)

Heh OK I'll change the naming in the future to be "patches against v3.10-rc1"
then.

Using some future tag name that does not yet exist may never happen either :)
 
> IOW: Pulled, thanks!

Regards,

Tony


From michal.simek at xilinx.com  Tue May 21 10:34:49 2013
From: michal.simek at xilinx.com (Michal Simek)
Date: Tue, 21 May 2013 16:34:49 +0200
Subject: [PATCH v2 0/5] Zynq: revised CCF code
In-Reply-To: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
Message-ID: <6d3d9b84-3438-4d74-9565-5c969e72b1df@CO9EHSMHS025.ehs.local>

On 05/13/2013 07:46 PM, Soren Brinkmann wrote:
> I rebased this series on v3.10-rc1 eliminating all dependencies and incorporated
> Greg's feedback.
> I'll push this also to my github repository.
> https://github.com/sorenb-xlnx/linux-xlnx/tree/zynq/clkc
> 
> v2:
>  - dropped the 'sort #includes' patches
> 
> 	S?ren
> 
> 
> Soren Brinkmann (5):
>   tty: xuartps: Remove suspend/resume functions

This patch will go through Greg trees.

>   clk: zynq: Factor out PLL driver
>   clk: zynq: Add clock controller driver
>   arm: zynq: Migrate platform to clock controller
>   clk: zynq: Remove deprecated clock code

I have added these patches to my arm-next branch
and also to zynq/clk branch.

Thanks,
Michal




From marc.zyngier at arm.com  Tue May 21 10:36:27 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 21 May 2013 15:36:27 +0100
Subject: [PATCH v4 14/32] arm64: KVM: guest one-reg interface
In-Reply-To: <20130521143015.GF27002@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-15-git-send-email-marc.zyngier@arm.com>
 <20130521143015.GF27002@arm.com>
Message-ID: <519B866B.5080101@arm.com>

On 21/05/13 15:30, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:42PM +0100, Marc Zyngier wrote:
>> Let userspace play with the guest registers.
>>
>> Reviewed-by: Christopher Covington <cov at codeaurora.org>
>> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
>> --- /dev/null
>> +++ b/arch/arm64/kvm/guest.c
> ...
>> +static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
>> +{
>> +	__u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
>> +	struct kvm_regs *regs = vcpu_gp_regs(vcpu);
>> +	int nr_regs = sizeof(*regs) / sizeof(__u32);
> 
> Was there any conclusion on using __u32 rather than __u64 here? At least
> you should add a comment since it's slightly confusing.

To use __u64, we'd have to move the FP/SIMD stuff out of struct kvm_regs
and use a separate one_reg bank. Actually, probably two, as the FP stuff
is already a mix of 32b and 128b registers.

I'll add a comment about the __u32 addressing of the structure.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From catalin.marinas at arm.com  Tue May 21 10:40:05 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 15:40:05 +0100
Subject: [PATCH v4 15/32] arm64: KVM: hypervisor initialization code
In-Reply-To: <1368540840-26750-16-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-16-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521144005.GG27002@arm.com>

On Tue, May 14, 2013 at 03:13:43PM +0100, Marc Zyngier wrote:
> --- /dev/null
> +++ b/arch/arm64/kvm/hyp-init.S
...
> +	.text
> +	.pushsection	.hyp.idmap.text, "ax"
> +
> +	.align	11
> +
> +__kvm_hyp_init:
> +	.global	__kvm_hyp_init
> +
> +ENTRY(__kvm_hyp_init_vector)

Why do you need both __kvm_hyp_init and __kvm_hyp_init_vector? You could
drop the former.

> +__do_hyp_init:
> +
> +	msr	ttbr0_el2, x0
> +
> +	mrs	x4, tcr_el1
> +	ldr	x5, =TCR_EL2_MASK
> +	and	x4, x4, x5
> +	ldr	x5, =TCR_EL2_FLAGS
> +	orr	x4, x4, x5
> +	msr	tcr_el2, x4
> +
> +	ldr	x4, =VTCR_EL2_FLAGS
> +	msr	vtcr_el2, x4
> +
> +	mrs	x4, mair_el1
> +	msr	mair_el2, x4
> +	isb
> +
> +	mov	x4, #SCTLR_EL2_FLAGS
> +	msr	sctlr_el2, x4
> +	isb
> +
> +	/* MMU is now enabled. Get ready for the trampoline dance */
> +	ldr	x4, =TRAMPOLINE_VA
> +	adr	x5, target
> +	bfi	x4, x5, #0, #PAGE_SHIFT
> +	br	x4
> +
> +	nop

What is this nop for?

-- 
Catalin


From marc.zyngier at arm.com  Tue May 21 10:49:08 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 21 May 2013 15:49:08 +0100
Subject: [PATCH v4 15/32] arm64: KVM: hypervisor initialization code
In-Reply-To: <20130521144005.GG27002@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-16-git-send-email-marc.zyngier@arm.com>
 <20130521144005.GG27002@arm.com>
Message-ID: <519B8964.3050802@arm.com>

On 21/05/13 15:40, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:43PM +0100, Marc Zyngier wrote:
>> --- /dev/null
>> +++ b/arch/arm64/kvm/hyp-init.S
> ...
>> +	.text
>> +	.pushsection	.hyp.idmap.text, "ax"
>> +
>> +	.align	11
>> +
>> +__kvm_hyp_init:
>> +	.global	__kvm_hyp_init
>> +
>> +ENTRY(__kvm_hyp_init_vector)
> 
> Why do you need both __kvm_hyp_init and __kvm_hyp_init_vector? You could
> drop the former.

Actually, __kvm_hyp_init is refered to by the 32/64 shared code, so I
can't get rid of it right now.

I'll remove __kvm_hyp_init_vector for the time being, as it isn't used
anywhere.

>> +__do_hyp_init:
>> +
>> +	msr	ttbr0_el2, x0
>> +
>> +	mrs	x4, tcr_el1
>> +	ldr	x5, =TCR_EL2_MASK
>> +	and	x4, x4, x5
>> +	ldr	x5, =TCR_EL2_FLAGS
>> +	orr	x4, x4, x5
>> +	msr	tcr_el2, x4
>> +
>> +	ldr	x4, =VTCR_EL2_FLAGS
>> +	msr	vtcr_el2, x4
>> +
>> +	mrs	x4, mair_el1
>> +	msr	mair_el2, x4
>> +	isb
>> +
>> +	mov	x4, #SCTLR_EL2_FLAGS
>> +	msr	sctlr_el2, x4
>> +	isb
>> +
>> +	/* MMU is now enabled. Get ready for the trampoline dance */
>> +	ldr	x4, =TRAMPOLINE_VA
>> +	adr	x5, target
>> +	bfi	x4, x5, #0, #PAGE_SHIFT
>> +	br	x4
>> +
>> +	nop
> 
> What is this nop for?

Nothing. I thought I had it removed already. Will get rid of it for good
this time.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From stefano.stabellini at eu.citrix.com  Tue May 21 10:38:39 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 21 May 2013 15:38:39 +0100
Subject: [GIT PULL for 3.11] arm: introduce psci_smp_ops
Message-ID: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>

Russell,
please pull (based on v3.10-rc2):

git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git 3.10-rc2-psci-ops-11-tag


It contains the generic PSCI patch and the smp_init patch that we
discussed so much about.
I think it would be helpful for other people if you could create a
stable branch with these patches so that SoC devs can base their work on
it.


Jon Medhurst (1):
      ARM: Enable selection of SMP operations at boot time

Stefano Stabellini (1):
      arm: introduce psci_smp_ops

 arch/arm/include/asm/mach/arch.h |    5 ++
 arch/arm/include/asm/psci.h      |    9 ++++
 arch/arm/kernel/Makefile         |    5 ++-
 arch/arm/kernel/psci.c           |    7 +--
 arch/arm/kernel/psci_smp.c       |   84 ++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/setup.c          |    9 ++++-
 arch/arm/mach-virt/Makefile      |    1 -
 arch/arm/mach-virt/platsmp.c     |   50 ----------------------
 arch/arm/mach-virt/virt.c        |    3 -
 9 files changed, 113 insertions(+), 60 deletions(-)
 create mode 100644 arch/arm/kernel/psci_smp.c
 delete mode 100644 arch/arm/mach-virt/platsmp.c



From stefano.stabellini at eu.citrix.com  Tue May 21 10:38:53 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 21 May 2013 15:38:53 +0100
Subject: [PATCH v11 2/2] ARM: Enable selection of SMP operations at boot time
In-Reply-To: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
Message-ID: <1369147133-29729-2-git-send-email-stefano.stabellini@eu.citrix.com>

From: Jon Medhurst <tixy at linaro.org>

Add a new 'smp_init' hook to machine_desc so platforms can specify a
function to be used to setup smp ops instead of having a statically
defined value.  The hook must return true when smp_ops are initialized.
If false the static mdesc->smp_ops will be used by default.

Add the definition of "bool" by including the linux/types.h file to
asm/mach/arch.h and make it self-contained.

Signed-off-by: Jon Medhurst <tixy at linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/include/asm/mach/arch.h |    5 +++++
 arch/arm/kernel/setup.c          |   10 ++++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..75bf079 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,6 +8,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/types.h>
+
 #ifndef __ASSEMBLY__
 
 struct tag;
@@ -16,8 +18,10 @@ struct pt_regs;
 struct smp_operations;
 #ifdef CONFIG_SMP
 #define smp_ops(ops) (&(ops))
+#define smp_init_ops(ops) (&(ops))
 #else
 #define smp_ops(ops) (struct smp_operations *)NULL
+#define smp_init_ops(ops) (bool (*)(void))NULL
 #endif
 
 struct machine_desc {
@@ -41,6 +45,7 @@ struct machine_desc {
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
 	char			restart_mode;	/* default restart mode	*/
 	struct smp_operations	*smp;		/* SMP operations	*/
+	bool			(*smp_init)(void);
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
 	void			(*reserve)(void);/* reserve mem blocks	*/
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 8f7a6e9..2b3ba15 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -800,10 +800,12 @@ void __init setup_arch(char **cmdline_p)
 	psci_init();
 #ifdef CONFIG_SMP
 	if (is_smp()) {
-		if (psci_smp_available())
-			smp_set_ops(&psci_smp_ops);
-		else if (mdesc->smp)
-			smp_set_ops(mdesc->smp);
+		if (!mdesc->smp_init || !mdesc->smp_init()) {
+			if (psci_smp_available())
+				smp_set_ops(&psci_smp_ops);
+			else if (mdesc->smp)
+				smp_set_ops(mdesc->smp);
+		}
 		smp_init_cpus();
 	}
 #endif
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Tue May 21 10:38:52 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 21 May 2013 15:38:52 +0100
Subject: [PATCH v11 1/2] arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
Message-ID: <1369147133-29729-1-git-send-email-stefano.stabellini@eu.citrix.com>

Rename virt_smp_ops to psci_smp_ops and move them to arch/arm/kernel/psci_smp.c.
Remove mach-virt/platsmp.c, now unused.
Compile psci_smp if CONFIG_ARM_PSCI and CONFIG_SMP.

Add a cpu_die smp_op based on psci_ops.cpu_off.

Initialize PSCI before setting smp_ops in setup_arch.

If PSCI is available on the platform, prefer psci_smp_ops over the
platform smp_ops.


Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Will Deacon <will.deacon at arm.com>
CC: arnd at arndb.de
CC: marc.zyngier at arm.com
CC: linux at arm.linux.org.uk
CC: nico at linaro.org
CC: rob.herring at calxeda.com
---
 arch/arm/include/asm/psci.h  |    9 ++++
 arch/arm/kernel/Makefile     |    5 ++-
 arch/arm/kernel/psci.c       |    7 +--
 arch/arm/kernel/psci_smp.c   |   84 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/setup.c      |    7 +++-
 arch/arm/mach-virt/Makefile  |    1 -
 arch/arm/mach-virt/platsmp.c |   50 -------------------------
 arch/arm/mach-virt/virt.c    |    3 -
 8 files changed, 106 insertions(+), 60 deletions(-)
 create mode 100644 arch/arm/kernel/psci_smp.c
 delete mode 100644 arch/arm/mach-virt/platsmp.c

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7..c4ae171 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
 };
 
 extern struct psci_operations psci_ops;
+extern struct smp_operations psci_smp_ops;
+
+#ifdef CONFIG_ARM_PSCI
+void psci_init(void);
+bool psci_smp_available(void);
+#else
+static inline void psci_init(void) { }
+static inline bool psci_smp_available(void) { return false; }
+#endif
 
 #endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..dd9d90a 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -82,6 +82,9 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 
 obj-$(CONFIG_ARM_VIRT_EXT)	+= hyp-stub.o
-obj-$(CONFIG_ARM_PSCI)		+= psci.o
+ifeq ($(CONFIG_ARM_PSCI),y)
+obj-y				+= psci.o
+obj-$(CONFIG_SMP)		+= psci_smp.o
+endif
 
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
index 3653164..4693188 100644
--- a/arch/arm/kernel/psci.c
+++ b/arch/arm/kernel/psci.c
@@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
 	{},
 };
 
-static int __init psci_init(void)
+void __init psci_init(void)
 {
 	struct device_node *np;
 	const char *method;
@@ -166,7 +166,7 @@ static int __init psci_init(void)
 
 	np = of_find_matching_node(NULL, psci_of_match);
 	if (!np)
-		return 0;
+		return;
 
 	pr_info("probing function IDs from device-tree\n");
 
@@ -206,6 +206,5 @@ static int __init psci_init(void)
 
 out_put_node:
 	of_node_put(np);
-	return 0;
+	return;
 }
-early_initcall(psci_init);
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
new file mode 100644
index 0000000..23a1142
--- /dev/null
+++ b/arch/arm/kernel/psci_smp.c
@@ -0,0 +1,84 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+
+#include <asm/psci.h>
+#include <asm/smp_plat.h>
+
+/*
+ * psci_smp assumes that the following is true about PSCI:
+ *
+ * cpu_suspend   Suspend the execution on a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * cpu_off       Power down a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * no return on successful call
+ *
+ * cpu_on        Power up a CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * migrate       Migrate the context to a different CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * returns 0  success, < 0 on failure
+ *
+ */
+
+extern void secondary_startup(void);
+
+static int __cpuinit psci_boot_secondary(unsigned int cpu,
+					 struct task_struct *idle)
+{
+	if (psci_ops.cpu_on)
+		return psci_ops.cpu_on(cpu_logical_map(cpu),
+				       __pa(secondary_startup));
+	return -ENODEV;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+void __ref psci_cpu_die(unsigned int cpu)
+{
+       const struct psci_power_state ps = {
+               .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+       };
+
+       if (psci_ops.cpu_off)
+               psci_ops.cpu_off(ps);
+
+       /* We should never return */
+       panic("psci: cpu %d failed to shutdown\n", cpu);
+}
+#else
+#define psci_cpu_die NULL
+#endif
+
+bool __init psci_smp_available(void)
+{
+	/* is cpu_on available at least? */
+	return (psci_ops.cpu_on != NULL);
+}
+
+struct smp_operations __initdata psci_smp_ops = {
+	.smp_boot_secondary	= psci_boot_secondary,
+	.cpu_die		= psci_cpu_die,
+};
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7a..8f7a6e9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -37,6 +37,7 @@
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
+#include <asm/psci.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp_plat.h>
@@ -796,9 +797,13 @@ void __init setup_arch(char **cmdline_p)
 	unflatten_device_tree();
 
 	arm_dt_init_cpu_maps();
+	psci_init();
 #ifdef CONFIG_SMP
 	if (is_smp()) {
-		smp_set_ops(mdesc->smp);
+		if (psci_smp_available())
+			smp_set_ops(&psci_smp_ops);
+		else if (mdesc->smp)
+			smp_set_ops(mdesc->smp);
 		smp_init_cpus();
 	}
 #endif
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
index 042afc1..7ddbfa6 100644
--- a/arch/arm/mach-virt/Makefile
+++ b/arch/arm/mach-virt/Makefile
@@ -3,4 +3,3 @@
 #
 
 obj-y					:= virt.o
-obj-$(CONFIG_SMP)			+= platsmp.o
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
deleted file mode 100644
index f4143f5..0000000
--- a/arch/arm/mach-virt/platsmp.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Author: Will Deacon <will.deacon at arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/of.h>
-
-#include <asm/psci.h>
-#include <asm/smp_plat.h>
-
-extern void secondary_startup(void);
-
-static void __init virt_smp_init_cpus(void)
-{
-}
-
-static void __init virt_smp_prepare_cpus(unsigned int max_cpus)
-{
-}
-
-static int __cpuinit virt_boot_secondary(unsigned int cpu,
-					 struct task_struct *idle)
-{
-	if (psci_ops.cpu_on)
-		return psci_ops.cpu_on(cpu_logical_map(cpu),
-				       __pa(secondary_startup));
-	return -ENODEV;
-}
-
-struct smp_operations __initdata virt_smp_ops = {
-	.smp_init_cpus		= virt_smp_init_cpus,
-	.smp_prepare_cpus	= virt_smp_prepare_cpus,
-	.smp_boot_secondary	= virt_boot_secondary,
-};
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 061f283..a67d2dd 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -36,11 +36,8 @@ static const char *virt_dt_match[] = {
 	NULL
 };
 
-extern struct smp_operations virt_smp_ops;
-
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
 	.init_irq	= irqchip_init,
 	.init_machine	= virt_init,
-	.smp		= smp_ops(virt_smp_ops),
 	.dt_compat	= virt_dt_match,
 MACHINE_END
-- 
1.7.2.5



From will.deacon at arm.com  Tue May 21 11:11:43 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 May 2013 16:11:43 +0100
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
Message-ID: <20130521151143.GH10453@mudshark.cambridge.arm.com>

Hi Andy,

On Tue, May 21, 2013 at 01:33:17PM +0100, Andy Shevchenko wrote:
> When thread is going to be stopped we have to unconditionally terminate all
> ongoing transfers. Otherwise it would be possible that callback function will
> be called on the next interrupt and will try to access to already freed
> structures.
> 
> The patch introduces specific error message for this, though it doesn't
> increase the counter of the failed tests.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
> Reported-by: Will Deacon <will.deacon at arm.com>

Thanks for persevering with this! Although this patch definitely fixes the
panic I was seeing, I now observe buffer verification failures in subsequent
test runs after an aborted run:

[   43.888424] dma0chan0-copy0: #1: transfer aborted with src_off=0x81f0 dst_off=0x9f4 len=0xdf29 (0)
[   43.888526] dma0chan0-copy0: terminating after 1 tests, 0 failures (status 0)
[   43.888635] dmatest: thread dma0chan0-copy0 exited with status 0

<reload module and start new tests>

[   77.341405] dma0chan0-copy0: #1: errors with src_off=0x8e29 dst_off=0x11dc8 len=0x2b93 (370)
[   77.341505] dma0chan0-copy0: terminating after 1 tests, 1 failures (status 0)

Note that the non-aborted transfers (I have 4 dma controllers) seem fine.

Looking at the results file doesn't show anything obvious, although I do
see some strange entries:

	[...]
	dstbuf not copied! [0xffffffff] Expected ff, got ff
	dstbuf not copied! [0xffffffff] Expected ff, got ff
	dstbuf not copied! [0xffffffff] Expected 00, got 00
	dstbuf not copied! [0xffffffff] Expected 00, got 00
	dstbuf not copied! [0xffffffff] Expected ff, got ff
	[...]

The more alarming ones look like:

	[...]
	dstbuf not copied! [0x147e9] Expected d5, got 36
	dstbuf not copied! [0x147ea] Expected d4, got 35
	dstbuf not copied! [0x147eb] Expected d3, got 34
	dstbuf not copied! [0x147ec] Expected d2, got 33
	dstbuf not copied! [0x147ed] Expected d1, got 32
	dstbuf not copied! [0x147ee] Expected d0, got 31
	[...]

Of course, this could be a driver bug with the PL330 that is being exposed
by this aborting code.

Will


From catalin.marinas at arm.com  Tue May 21 11:16:04 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:16:04 +0100
Subject: [PATCH v4 16/32] arm64: KVM: HYP mode world switch implementation
In-Reply-To: <1368540840-26750-17-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-17-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521151604.GH27002@arm.com>

On Tue, May 14, 2013 at 03:13:44PM +0100, Marc Zyngier wrote:
> +// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
> +ENTRY(__kvm_tlb_flush_vmid_ipa)
> +       kern_hyp_va     x0
> +       ldr     x2, [x0, #KVM_VTTBR]
> +       msr     vttbr_el2, x2
> +       isb
> +
> +       /*
> +        * We could do so much better if we had the VA as well.
> +        * Instead, we invalidate Stage-2 for this IPA, and the
> +        * whole of Stage-1. Weep...
> +        */
> +       tlbi    ipas2e1is, x1
> +       dsb     sy
> +       tlbi    vmalle1is
> +       dsb     sy
> +       isb
> +
> +       msr     vttbr_el2, xzr
> +       isb
> +       ret
> +ENDPROC(__kvm_tlb_flush_vmid_ipa)

There are some isbs here which could be removed if you need an eret
anyway.

> +ENTRY(__kvm_flush_vm_context)
> +       tlbi    alle1is
> +       ic      ialluis
> +       dsb     sy
> +       isb
> +       ret
> +ENDPROC(__kvm_flush_vm_context)

I didn't fully understand - why do we need I-cache maintenance here? Is
it for ASID-tagged VIVT I-cache?

BTW, the arch/arm equivalent has some better comments on this code ;).

-- 
Catalin


From catalin.marinas at arm.com  Tue May 21 11:20:25 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:20:25 +0100
Subject: [PATCH v4 17/32] arm64: KVM: Exit handling
In-Reply-To: <1368540840-26750-18-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-18-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521152025.GI27002@arm.com>

On Tue, May 14, 2013 at 03:13:45PM +0100, Marc Zyngier wrote:
> Handle the exit of a VM, decoding the exit reason from HYP mode
> and calling the corresponding handler.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Tue May 21 11:21:54 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:21:54 +0100
Subject: [PATCH v4 18/32] arm64: KVM: Plug the VGIC
In-Reply-To: <1368540840-26750-19-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-19-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521152154.GJ27002@arm.com>

On Tue, May 14, 2013 at 03:13:46PM +0100, Marc Zyngier wrote:
> Add support for the in-kernel GIC emulation.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Tue May 21 11:27:06 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:27:06 +0100
Subject: [PATCH v4 19/32] arm64: KVM: Plug the arch timer
In-Reply-To: <1368540840-26750-20-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-20-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521152706.GK27002@arm.com>

On Tue, May 14, 2013 at 03:13:47PM +0100, Marc Zyngier wrote:
> Add support for the in-kernel timer emulation.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

I think same comment as one of the previous patches, you could get rid
of some ISBs if you get an ERET anyway. Otherwise:

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From thomas.petazzoni at free-electrons.com  Tue May 21 11:37:07 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 17:37:07 +0200
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus
 initialization later
In-Reply-To: <20130521141621.GU31290@titan.lakedaemon.net>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521141621.GU31290@titan.lakedaemon.net>
Message-ID: <20130521173707.5a49eaec@skate>

Dear Jason Cooper,

On Tue, 21 May 2013 10:16:21 -0400, Jason Cooper wrote:

> This doesn't apply when based on mvebu/cleanup because of:
> 
>   49ed97f ARM: Orion: Remove redundant init_dma_coherent_pool_size()

Right.

> I tried hacking it up to put it in mvebu/soc-internal_regs for a few
> rounds of testing in linux-next during review, however, I'd prefer you
> rebase this on top of mvebu/cleanup.

So you mean my next version of the "Internal registers switch" should
be based on mvebu/cleanup, right? There will be some next version in
any case, because I just found a bug in the latest patch when booting
from a bootloader that has already done the switch to 0xF1.

> My version ended up looking like:
> 
> ---8<----
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
> index b9319c4..75ebf56 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.c
> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
> @@ -44,14 +44,11 @@ static void __init armada_370_xp_map_io(void)
>  
>  static void __init armada_370_xp_timer_and_clk_init(void)
>  {
> +	char *mbus_soc_name;
> +
>  	mvebu_clocks_init();
>  	armada_370_xp_timer_init();
>  	coherency_init();
> -}
> -
> -static void __init armada_370_xp_init_early(void)
> -{
> -	char *mbus_soc_name;
>  
>  	/*
>  	 * This initialization will be replaced by a DT-based
> @@ -87,7 +84,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
>  	.smp		= smp_ops(armada_xp_smp_ops),
>  	.init_machine	= armada_370_xp_dt_init,
>  	.map_io		= armada_370_xp_map_io,
> -	.init_early	= armada_370_xp_init_early,
>  	.init_time	= armada_370_xp_timer_and_clk_init,
>  	.restart	= mvebu_restart,
>  	.dt_compat	= armada_370_xp_dt_compat,

From a quick look your version looks correct. Everything ends up into
the ->init_time() hook, which is correct. The only thing I had left in
->init_early() in my version was the DMA coherent thing, which is no
longer needed.

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From catalin.marinas at arm.com  Tue May 21 11:38:21 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:38:21 +0100
Subject: [PATCH v4 20/32] arm64: KVM: PSCI implementation
In-Reply-To: <1368540840-26750-21-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-21-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521153820.GL27002@arm.com>

On Tue, May 14, 2013 at 03:13:48PM +0100, Marc Zyngier wrote:
> Wire the PSCI backend into the exit handling code.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Tue May 21 11:42:27 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:42:27 +0100
Subject: [PATCH v4 21/32] arm64: KVM: Build system integration
In-Reply-To: <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521154227.GM27002@arm.com>

On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote:
> --- /dev/null
> +++ b/arch/arm64/kvm/Kconfig
...
> +config KVM_ARM_VGIC
> +        bool
> +	depends on KVM_ARM_HOST && OF
> +	select HAVE_KVM_IRQCHIP
> +	---help---
> +	  Adds support for a hardware assisted, in-kernel GIC emulation.
> +
> +config KVM_ARM_TIMER
> +        bool
> +	depends on KVM_ARM_VGIC
> +	select HAVE_KVM_IRQCHIP
> +	---help---
> +	  Adds support for the Architected Timers in virtual machines
> +
> +source drivers/virtio/Kconfig

Shouldn't the above configs go to drivers/virtio/Kconfig as well (or
drivers/virtio/arm/Kconfig)?

-- 
Catalin


From jason at lakedaemon.net  Tue May 21 11:43:13 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 11:43:13 -0400
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus
 initialization later
In-Reply-To: <20130521173707.5a49eaec@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521141621.GU31290@titan.lakedaemon.net>
 <20130521173707.5a49eaec@skate>
Message-ID: <20130521154313.GV31290@titan.lakedaemon.net>

Thomas,

On Tue, May 21, 2013 at 05:37:07PM +0200, Thomas Petazzoni wrote:
> On Tue, 21 May 2013 10:16:21 -0400, Jason Cooper wrote:
> > This doesn't apply when based on mvebu/cleanup because of:
> > 
> >   49ed97f ARM: Orion: Remove redundant init_dma_coherent_pool_size()
> 
> Right.
> 
> > I tried hacking it up to put it in mvebu/soc-internal_regs for a few
> > rounds of testing in linux-next during review, however, I'd prefer you
> > rebase this on top of mvebu/cleanup.
> 
> So you mean my next version of the "Internal registers switch" should
> be based on mvebu/cleanup, right?

Yes, sorry I wasn't clear, I meant the series.  You can drop 1-3 as
well for the next version, since I've pulled those.

> There will be some next version in any case, because I just found a
> bug in the latest patch when booting from a bootloader that has
> already done the switch to 0xF1.

Ok, I'll hold off putting it up for testing until v2.

thx,

Jason.


From catalin.marinas at arm.com  Tue May 21 11:44:41 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 16:44:41 +0100
Subject: [PATCH v4 31/32] arm64: KVM: MAINTAINERS update
In-Reply-To: <1368540840-26750-32-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-32-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521154441.GN27002@arm.com>

On Tue, May 14, 2013 at 03:13:59PM +0100, Marc Zyngier wrote:
> Elect myself as the KVM/arm64 maintainer.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From mgreer at animalcreek.com  Tue May 21 11:56:12 2013
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Tue, 21 May 2013 08:56:12 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130520220540.GL10378@atomide.com>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
 <20130517185620.GF28484@animalcreek.com>
 <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>
 <20130520220540.GL10378@atomide.com>
Message-ID: <20130521155612.GA5870@animalcreek.com>

On Mon, May 20, 2013 at 03:05:40PM -0700, Tony Lindgren wrote:
> * Yegor Yefremov <yegorslists at googlemail.com> [130517 14:34]:
> > On Fri, May 17, 2013 at 8:56 PM, Mark A. Greer <mgreer at animalcreek.com> wrote:
> > > On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
> > >> On 15.05.2013 23:50, Mark A. Greer wrote:
> > >> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
> > >
> > >> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
> > >> >> idle states with?
> > >> >
> > >> > I have an am35xx which isn't supposed to have an IVA so I can test with it
> > >> > (although, I'm not sure how well the kernel works on the am35xx these days).
> > >> >
> > >> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
> > >> > comes up, see what I can figure out.
> > >>
> > >> I think this issue is relevant to am3517 as you can see from this thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
> > >> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
> > >>
> > >> I have such a system running, so if you have any other patches/ideas to test, I would do it.
> > >
> > > Yegor, since I've so far been unable to get my am3517evm to fire up, can
> > > you play around with the 3517 to see if there appears to be iva registers
> > > that can be read/written to safely?  In particular, can the code that idles
> > > the iva be run safely on an am3517?
> > 
> > I'll look into this next week. am3517 and IVA seems to be a really big
> > mystery. In the TI forum will be stated, there is no IVA:
> > http://e2e.ti.com/support/arm/sitara_arm/f/791/t/150961.aspx, but TRM
> > has various appearances of IVA2 registers, but no real
> > description/explanation of what is IVA and how to eat it.
> 
> On 3703 it looks like the whole omap3_iva_idle() reset is needed, except
> for setting the iva2 bootmode to idle. So I'm planning to merge the following
> patch with just comments update this week unless somebody has a better fix
> in mind.
> 
> Regards,
> 
> Tony
> 
> 
> From: Tony Lindgren <tony at atomide.com>
> Date: Tue, 14 May 2013 20:28:15 -0700
> Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
> 
> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> changed PM to not access IVA registers on omaps that don't have
> them. Turns out we still need to idle iva2 as otherwise
> iva2_pwrdm will stay on and block deeper idle states.
> 
> It seems that the only part of the reset that may not be needed
> is the setting of the iva2 boot mode to idle. But as that register
> seems to be there and is harmless if no iva2 is on the SoC, it's
> probably safest to do the complete reset.
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
>  	/* Clear any pending PRCM interrupts */
>  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
>  
> -	if (omap3_has_iva())
> -		omap3_iva_idle();
> +	/*
> +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> +	 */
> +	omap3_iva_idle();
>  
>  	omap3_d2d_idle();
>  }

I think that patch will work fine.  That's basically how that piece of code
was before a819c4f16 (ARM: OMAP3: PM: Only access IVA if one exists) which
ran fine on the am3517 and am3703 (AFAIK).  In addition, Yegor has verified
that the am3517 still works so...

Acked-by: Mark A. Greer <mgreer at animalcreek.com>


From swarren at wwwdotorg.org  Tue May 21 12:05:49 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 May 2013 10:05:49 -0600
Subject: [v2 0/6] CLK: tegra: convert device tree files to use CLK defines
In-Reply-To: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com>
References: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <519B9B5D.4050402@wwwdotorg.org>

On 05/21/2013 03:10 AM, Hiroshi Doyu wrote:
> This patchset converts device tree files to use CLK defines. This
> version was updated along with the latest DT changes.
> 
> The following changes since commit 7479d8bb5650f43053d0e82fa44db668cf968f11:
> 
>   TESTING: Build Tegra USB as a module (2013-05-20 13:11:19 -0600)

That commit is in my personal work-in-progress branch. This series
should be based on Tegra's for-3.11/dt branch. This will make a
difference (at least) in patch 6/6, where you've edited some DT nodes
that don't yet exist upstream (i.e. Tegra's for-3.11/dt branch) and
hence this series won't apply there.

I assume you're planning to send a series for 3.11 that converts
drivers/clk/tegra/ to use these new header files?

If so, I'll need to apply patches 1, 3, 5 to a separate branch, so it
can be pulled into the branch where the drivers/clk changes are applied,
then apply patches 2, 4, 6 to Tegra's for-3.11/dt after merging in the
branch with the header files.


From catalin.marinas at arm.com  Tue May 21 12:07:26 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 May 2013 17:07:26 +0100
Subject: [PATCH v3 0/7] ARM: KVM: various mmu related fixes for 3.10
In-Reply-To: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130521160725.GP27002@arm.com>

On Tue, May 14, 2013 at 12:11:33PM +0100, Marc Zyngier wrote:
> This patch series fixes a number of of KVM/ARM issues that have either
> been spotted during the review of the arm64 code, or while reworking
> related code.
> 
> Only the first patch fixes a potential (if unlikely) problem, the
> others are either cosmetic or performance related.
> 
> Tested on TC-2, based on 3.10-rc1.
> 
> * From v2:
>   - [1/7] Drop the unnecessary "TLB invalidate all", as we already do
>   it on a page-per-page level.
>   - [3/7] Add a cache cleaning primitive, move the cleaning outside of
>   kvm_set_pte(), and clean a range as large as possible when inserting
>   PTEs.
>   - [4,5,7/7] New patches
> 
> Marc Zyngier (7):
>   ARM: KVM: be more thorough when invalidating TLBs
>   ARM: KVM: remove dead prototype for __kvm_tlb_flush_vmid
>   ARM: KVM: relax cache maintainance when building page tables
>   ARM: KVM: use phys_addr_t instead of unsigned long long for HYP PGDs
>   ARM: KVM: don't special case PC when doing an MMIO
>   ARM: KVM: get rid of S2_PGD_SIZE
>   ARM: KVM: drop use of PAGE_S2_DEVICE

This series looks good to me:

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From pbonzini at redhat.com  Tue May 21 12:09:47 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Tue, 21 May 2013 12:09:47 -0400 (EDT)
Subject: [PATCH v4 21/32] arm64: KVM: Build system integration
In-Reply-To: <20130521154227.GM27002@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>
 <20130521154227.GM27002@arm.com>
Message-ID: <850310439.5245685.1369152587054.JavaMail.root@redhat.com>



----- Messaggio originale -----
> Da: "Catalin Marinas" <catalin.marinas at arm.com>
> A: "Marc Zyngier" <Marc.Zyngier at arm.com>
> Cc: linux-arm-kernel at lists.infradead.org, kvmarm at lists.cs.columbia.edu, kvm at vger.kernel.org, "Will Deacon"
> <Will.Deacon at arm.com>, pbonzini at redhat.com, gleb at redhat.com, "Christopher Covington" <cov at codeaurora.org>
> Inviato: Marted?, 21 maggio 2013 17:42:27
> Oggetto: Re: [PATCH v4 21/32] arm64: KVM: Build system integration
> 
> On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote:
> > --- /dev/null
> > +++ b/arch/arm64/kvm/Kconfig
> ...
> > +config KVM_ARM_VGIC
> > +        bool
> > +	depends on KVM_ARM_HOST && OF
> > +	select HAVE_KVM_IRQCHIP
> > +	---help---
> > +	  Adds support for a hardware assisted, in-kernel GIC emulation.
> > +
> > +config KVM_ARM_TIMER
> > +        bool
> > +	depends on KVM_ARM_VGIC
> > +	select HAVE_KVM_IRQCHIP
> > +	---help---
> > +	  Adds support for the Architected Timers in virtual machines
> > +
> > +source drivers/virtio/Kconfig
> 
> Shouldn't the above configs go to drivers/virtio/Kconfig as well (or
> drivers/virtio/arm/Kconfig)?

virtio doesn't mean "virtual versions of devices that also exist in
hardware"; those are indeed in arch/ARCH/kvm.  virtio is a specific bus
for paravirtualized devices.  It is not KVM-specific and the code runs
in the guest (whereas arch/arm64/kvm/Kconfig is host code).

That said, drivers/virtio/Kconfig is already sourced by drivers/Kconfig.
Why do you need to source it again here?

Paolo


From thomas.petazzoni at free-electrons.com  Tue May 21 12:10:18 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 18:10:18 +0200
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus
 initialization later
In-Reply-To: <20130521154313.GV31290@titan.lakedaemon.net>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521141621.GU31290@titan.lakedaemon.net>
 <20130521173707.5a49eaec@skate>
 <20130521154313.GV31290@titan.lakedaemon.net>
Message-ID: <20130521181018.401ddabf@skate>

Dear Jason Cooper,

On Tue, 21 May 2013 11:43:13 -0400, Jason Cooper wrote:

> > > I tried hacking it up to put it in mvebu/soc-internal_regs for a few
> > > rounds of testing in linux-next during review, however, I'd prefer you
> > > rebase this on top of mvebu/cleanup.
> > 
> > So you mean my next version of the "Internal registers switch" should
> > be based on mvebu/cleanup, right?
> 
> Yes, sorry I wasn't clear, I meant the series.  You can drop 1-3 as
> well for the next version, since I've pulled those.

Ok. 1-2 have been merged in mvebu/fixes, and 3 in mvebu/cleanup. So I
suppose mvebu/cleanup is based on mvebu/fixes ? Or should I base on
mvebu/cleanup and assume when it will lend in mainline, the mvebu/fixes
patches will be there (which doesn't make the thing easy for testing
here, because to test, I actually need all the patches in the same
branch). Just trying to figure the workflow :)

> > There will be some next version in any case, because I just found a
> > bug in the latest patch when booting from a bootloader that has
> > already done the switch to 0xF1.
> 
> Ok, I'll hold off putting it up for testing until v2.

Well, the current version should be ok build-wise, and works with all
currently available Marvell bootloaders. The bug can only be seen with
a bootloader version that has not yet been really released by Marvell.

But anyway, v2 will follow shortly. With this v1, I was mainly hoping
for some feedback, to see if the solution was acceptable or not.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From swarren at wwwdotorg.org  Tue May 21 12:13:31 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 May 2013 10:13:31 -0600
Subject: [v2 2/6] ARM: tegra20: convert device tree files to use CLK
 defines
In-Reply-To: <1369127450-15203-3-git-send-email-hdoyu@nvidia.com>
References: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com>
 <1369127450-15203-3-git-send-email-hdoyu@nvidia.com>
Message-ID: <519B9D2B.5010101@wwwdotorg.org>

On 05/21/2013 03:10 AM, Hiroshi Doyu wrote:
> Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic
> numbers in the device tree. For example,
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

> diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts

> -		clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
> +		clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, <&tegra_car TEGRA20_CLK_CDEV1>;

That's well over 80 columns. Can you wrap it and make sure there aren't
any other instances of this? I guess checkpatch doesn't actually impose
this rule on *.dts files, since it didn't complain about this.


From marc.zyngier at arm.com  Tue May 21 12:14:07 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 21 May 2013 17:14:07 +0100
Subject: [PATCH v4 21/32] arm64: KVM: Build system integration
In-Reply-To: <850310439.5245685.1369152587054.JavaMail.root@redhat.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>
 <20130521154227.GM27002@arm.com>
 <850310439.5245685.1369152587054.JavaMail.root@redhat.com>
Message-ID: <519B9D4F.9030308@arm.com>

On 21/05/13 17:09, Paolo Bonzini wrote:
> 
> 
> ----- Messaggio originale -----
>> Da: "Catalin Marinas" <catalin.marinas at arm.com>
>> A: "Marc Zyngier" <Marc.Zyngier at arm.com>
>> Cc: linux-arm-kernel at lists.infradead.org, kvmarm at lists.cs.columbia.edu, kvm at vger.kernel.org, "Will Deacon"
>> <Will.Deacon at arm.com>, pbonzini at redhat.com, gleb at redhat.com, "Christopher Covington" <cov at codeaurora.org>
>> Inviato: Marted?, 21 maggio 2013 17:42:27
>> Oggetto: Re: [PATCH v4 21/32] arm64: KVM: Build system integration
>>
>> On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote:
>>> --- /dev/null
>>> +++ b/arch/arm64/kvm/Kconfig
>> ...
>>> +config KVM_ARM_VGIC
>>> +        bool
>>> +	depends on KVM_ARM_HOST && OF
>>> +	select HAVE_KVM_IRQCHIP
>>> +	---help---
>>> +	  Adds support for a hardware assisted, in-kernel GIC emulation.
>>> +
>>> +config KVM_ARM_TIMER
>>> +        bool
>>> +	depends on KVM_ARM_VGIC
>>> +	select HAVE_KVM_IRQCHIP
>>> +	---help---
>>> +	  Adds support for the Architected Timers in virtual machines
>>> +
>>> +source drivers/virtio/Kconfig
>>
>> Shouldn't the above configs go to drivers/virtio/Kconfig as well (or
>> drivers/virtio/arm/Kconfig)?
> 
> virtio doesn't mean "virtual versions of devices that also exist in
> hardware"; those are indeed in arch/ARCH/kvm.  virtio is a specific bus
> for paravirtualized devices.  It is not KVM-specific and the code runs
> in the guest (whereas arch/arm64/kvm/Kconfig is host code).
> 
> That said, drivers/virtio/Kconfig is already sourced by drivers/Kconfig.
> Why do you need to source it again here?

Probably some brain fart on my side. I'll get rid of it.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From swarren at wwwdotorg.org  Tue May 21 12:15:48 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 May 2013 10:15:48 -0600
Subject: [PATCH] ARM: tegra: add cpu_disable for hotplug
In-Reply-To: <1369131215-2920-1-git-send-email-josephl@nvidia.com>
References: <1369131215-2920-1-git-send-email-josephl@nvidia.com>
Message-ID: <519B9DB4.7070106@wwwdotorg.org>

On 05/21/2013 04:13 AM, Joseph Lo wrote:
> The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
> support that. Adding a Tegra specific cpu_disable function for it.
> 
> Signed-off-by: Joseph Lo <josephl at nvidia.com>

> diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c

> +int tegra_cpu_disable(unsigned int cpu)
> +{
> +	switch (tegra_chip_id) {
> +	case TEGRA114:
> +		return 0;
> +	default:
> +		return cpu == 0 ? -EPERM : 0;
> +	}
> +}

Do we expect all/most future chips to support hotplug of CPU0? Or at
least, fewer chips to have the restriction than not? If so, it might be
more forward-looking to write that as:

if (tegra_chip_id == TEGRA30)
    return cpu == 0 ? -EPERM : 0;

return 0;

?


From jonathan.austin at arm.com  Tue May 21 12:25:11 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 21 May 2013 17:25:11 +0100
Subject: [PATCH v2 1/3] ARM: allow platforms to use generic headers without
 ARCH_MULTIPLATFORM
In-Reply-To: <20130515233335.GO5600@atomide.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
 <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>
 <5192532B.1070705@gmail.com> <20130515233335.GO5600@atomide.com>
Message-ID: <519B9FE7.3030907@arm.com>

Hi Tony,

On 16/05/13 00:33, Tony Lindgren wrote:
> * Rob Herring <robherring2 at gmail.com> [130514 08:12]:
>> On 05/14/2013 06:27 AM, Jonathan Austin wrote:
>>> Currently the use of generic mach headers is only is controlled by the same
>>> config option as selection of a multiplatform kernel (i.e.
>>> ARCH_MULTIPLATFORM). However, there are cases where it is valid to use the
>>> generic headers but still build a single platform kernel.
>>>
>>> One such example is when using the vexpress platform with a core that does
>>> not have an MMU; a multiplatform kernel does not make sense, but use of the
>>> generic headers is required by the vexpress platform since 617276307cd4c
>>> ("ARM: vexpress: convert to multi-platform").
>>>
>>> This patch untangles these two options by introducing a new
>>> ARM_GENERIC_HEADERS config option that ARCH_MULTIPLATFORM selects. Other
>>> platforms can now select ARM_GENERIC_HEADERS independently.
>>
>> I find this name confusing. It is no headers you are selecting and
>> generic is a bit overused IMHO. So how about something like
>> NEED_NO_MACH_HEADERS to somewhat align to the other header related
>> config options (e.g. NEED_MACH_GPIO_H).
>
> Hmm it _looks_ like this won't allow the drivers again to
> #include <plat/*.h> and <mach/*.h>. Have you checked that?
>
> It might be worth checking as we really don't want to go back there
> again.. Currently arch/arm/Makefile has:
>
> ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
> ifeq ($(KBUILD_SRC),)
> KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
> else
> KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
> endif
> endif
>
> So you may need to do something there to prevent drivers from again
> including machdirs and platdirs.
>
If I've understood you correctly, then this patch already deals with 
this case (though it isn't hugely obvious from the diff...) by replacing 
CONFIG_ARCH_MULTIPLATFORM in your example above with 
CONFIG_ARM_GENERIC_HEADERS (soon to be renamed, as per Rob's suggestion).

Because ARCH_MULTIPLATFORM selects 
CONFIG_(FORMERLY_KNOWN_AS_)ARM_GENERIC_HEADERS it shouldn't be possible 
for anything multi-platform to start including <plat/*.h> and <mach/*.h> 
again.

This seems to be the right thing to do because it also makes it 
impossible to include <plat/*.h> and <mach/*.h> in !MULTIPLATFORM 
situations that don't need mach/plat headers, like the VEXPRESS_NOMMU case.

Is that what you were getting at? Please let me know if not...

Thanks,

Jonny

> Regards,
>
> Tony
>




From swarren at wwwdotorg.org  Tue May 21 12:34:17 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 May 2013 10:34:17 -0600
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
In-Reply-To: <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
References: <519AD82A.6090809@wwwdotorg.org>
 <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
Message-ID: <519BA209.6050407@wwwdotorg.org>

On 05/21/2013 12:02 AM, Jongsung Kim wrote:
> Stephen Warren reported the recent commit 78506f2 (add support for
> extended FIFO-size of PL011-r1p5) breaks the serial port on the
> BCM2835 ARM SoC.
> 
> A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
> The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
> FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
> this compatibility issue, this patch overrides the HW UART periphid
> register values with the actually compatible UART periphid 0x00241011
> (r1p3 or r1p4).
> 
> Reported-by: Stephen Warren <swarren at wwwdotorg.org>
> Signed-off-by: Jongsung Kim <neidhard.kim at lge.com>

I know this will work, because I tried out the same thing last week.

However, I'm not convinced that it's the correct approach. What other
changes exist between r1p4 and r1p5; can you check in the TRM? Faking
the periphid would prevent the driver from taking account of any other
changes. Should we instead add a DT property solely to override the FIFO
size, and then set that for bcm2835? I guess if there really aren't any
other SW-visible changes in r1p5, this approach is fine.


From jonathan.austin at arm.com  Tue May 21 12:36:50 2013
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 21 May 2013 17:36:50 +0100
Subject: [PATCH v2 1/3] ARM: allow platforms to use generic headers without
 ARCH_MULTIPLATFORM
In-Reply-To: <5192532B.1070705@gmail.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
 <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>
 <5192532B.1070705@gmail.com>
Message-ID: <519BA2A2.4060306@arm.com>

Hi Rob,

On 14/05/13 16:07, Rob Herring wrote:
> On 05/14/2013 06:27 AM, Jonathan Austin wrote:
>> Currently the use of generic mach headers is only is controlled by the same
>> config option as selection of a multiplatform kernel (i.e.
>> ARCH_MULTIPLATFORM). However, there are cases where it is valid to use the
>> generic headers but still build a single platform kernel.
>>
>> One such example is when using the vexpress platform with a core that does
>> not have an MMU; a multiplatform kernel does not make sense, but use of the
>> generic headers is required by the vexpress platform since 617276307cd4c
>> ("ARM: vexpress: convert to multi-platform").
>>
>> This patch untangles these two options by introducing a new
>> ARM_GENERIC_HEADERS config option that ARCH_MULTIPLATFORM selects. Other
>> platforms can now select ARM_GENERIC_HEADERS independently.
>
> I find this name confusing. It is no headers you are selecting and
> generic is a bit overused IMHO. So how about something like
> NEED_NO_MACH_HEADERS to somewhat align to the other header related
> config options (e.g. NEED_MACH_GPIO_H).

NEED_NO_MACH_HEADERS is fine by me... Expresses things well.

I'll post a v3 around -rc3 with this changed.

Thanks,

Jonny

>
> Rob
>
>> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
>> CC: Rob Herring <rob.herring at calxeda.com>
>> CC: Pawel Moll <pawel.moll at arm.com>
>> CC: Jason Cooper <jason at lakedaemon.net>
>> CC: Andrew Lunn <andrew at lunn.ch>
>> CC: Gregory Clement <gregory.clement at free-electrons.com>
>> CC: Tony Lindgren <tony at atomide.com>
>> CC: Stephen Boyd <sboyd at codeaurora.org>
>> CC: Will Deacon <will.deacon at arm.com>
>> ---
>>   arch/arm/Kconfig                 |    4 ++++
>>   arch/arm/Kconfig.debug           |    4 ++--
>>   arch/arm/Makefile                |    2 +-
>>   arch/arm/include/asm/timex.h     |    2 +-
>>   arch/arm/mach-mvebu/Makefile     |    2 +-
>>   arch/arm/mach-omap2/Makefile     |    2 +-
>>   arch/arm/mach-vexpress/Makefile  |    2 +-
>>   arch/arm/plat-omap/Makefile      |    2 +-
>>   arch/arm/plat-orion/Makefile     |    2 +-
>>   arch/arm/plat-versatile/Makefile |    2 +-
>>   10 files changed, 14 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index d423d58..408eb33 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -206,6 +206,9 @@ config NEED_RET_TO_USER
>>   config ARCH_MTD_XIP
>>   	bool
>>
>> +config ARM_GENERIC_HEADERS
>> +	bool
>> +
>>   config VECTORS_BASE
>>   	hex
>>   	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
>> @@ -295,6 +298,7 @@ config ARCH_MULTIPLATFORM
>>   	select MULTI_IRQ_HANDLER
>>   	select SPARSE_IRQ
>>   	select USE_OF
>> +	select ARM_GENERIC_HEADERS
>>
>>   config ARCH_INTEGRATOR
>>   	bool "ARM Ltd. Integrator family"
>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
>> index 1d41908..ede909b 100644
>> --- a/arch/arm/Kconfig.debug
>> +++ b/arch/arm/Kconfig.debug
>> @@ -652,13 +652,13 @@ config DEBUG_LL_INCLUDE
>>
>>   config DEBUG_UNCOMPRESS
>>   	bool
>> -	default y if ARCH_MULTIPLATFORM && DEBUG_LL && \
>> +	default y if ARM_GENERIC_HEADERS && DEBUG_LL && \
>>   		     !DEBUG_OMAP2PLUS_UART && \
>>   		     !DEBUG_TEGRA_UART
>>
>>   config UNCOMPRESS_INCLUDE
>>   	string
>> -	default "debug/uncompress.h" if ARCH_MULTIPLATFORM
>> +	default "debug/uncompress.h" if ARM_GENERIC_HEADERS
>>   	default "mach/uncompress.h"
>>
>>   config EARLY_PRINTK
>> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
>> index 4737408..ab0416f 100644
>> --- a/arch/arm/Makefile
>> +++ b/arch/arm/Makefile
>> @@ -229,7 +229,7 @@ endif
>>   machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>>   platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
>>
>> -ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
>> +ifneq ($(CONFIG_ARM_GENERIC_HEADERS),y)
>>   ifeq ($(KBUILD_SRC),)
>>   KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
>>   else
>> diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
>> index 83f2aa8..586a9c2 100644
>> --- a/arch/arm/include/asm/timex.h
>> +++ b/arch/arm/include/asm/timex.h
>> @@ -12,7 +12,7 @@
>>   #ifndef _ASMARM_TIMEX_H
>>   #define _ASMARM_TIMEX_H
>>
>> -#ifdef CONFIG_ARCH_MULTIPLATFORM
>> +#ifdef CONFIG_ARM_GENERIC_HEADERS
>>   #define CLOCK_TICK_RATE 1000000
>>   #else
>>   #include <mach/timex.h>
>> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
>> index 2d04f0e..d3c0e0b 100644
>> --- a/arch/arm/mach-mvebu/Makefile
>> +++ b/arch/arm/mach-mvebu/Makefile
>> @@ -1,4 +1,4 @@
>> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
>>   	-I$(srctree)/arch/arm/plat-orion/include
>>
>>   AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
>> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
>> index 55a9d67..ab204bc 100644
>> --- a/arch/arm/mach-omap2/Makefile
>> +++ b/arch/arm/mach-omap2/Makefile
>> @@ -2,7 +2,7 @@
>>   # Makefile for the linux kernel.
>>   #
>>
>> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
>>   	-I$(srctree)/arch/arm/plat-omap/include
>>
>>   # Common support
>> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
>> index 42703e8..6768e7f 100644
>> --- a/arch/arm/mach-vexpress/Makefile
>> +++ b/arch/arm/mach-vexpress/Makefile
>> @@ -1,7 +1,7 @@
>>   #
>>   # Makefile for the linux kernel.
>>   #
>> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include \
>>   	-I$(srctree)/arch/arm/plat-versatile/include
>>
>>   obj-y					:= v2m.o
>> diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
>> index 3119941..3e1ba10 100644
>> --- a/arch/arm/plat-omap/Makefile
>> +++ b/arch/arm/plat-omap/Makefile
>> @@ -2,7 +2,7 @@
>>   # Makefile for the linux kernel.
>>   #
>>
>> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
>> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/arch/arm/plat-omap/include
>>
>>   # Common support
>>   obj-y := sram.o dma.o counter_32k.o
>> diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
>> index 9433605..79a042ed 100644
>> --- a/arch/arm/plat-orion/Makefile
>> +++ b/arch/arm/plat-orion/Makefile
>> @@ -1,7 +1,7 @@
>>   #
>>   # Makefile for the linux kernel.
>>   #
>> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
>> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include
>>
>>   orion-gpio-$(CONFIG_GPIOLIB)      += gpio.o
>>   obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
>> diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
>> index f88d448..19495c6 100644
>> --- a/arch/arm/plat-versatile/Makefile
>> +++ b/arch/arm/plat-versatile/Makefile
>> @@ -1,4 +1,4 @@
>> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
>> +ccflags-$(CONFIG_ARM_GENERIC_HEADERS) := -I$(srctree)/$(src)/include
>>
>>   obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
>>   obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
>>
>
>




From jason at lakedaemon.net  Tue May 21 12:37:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 12:37:25 -0400
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus
 initialization later
In-Reply-To: <20130521181018.401ddabf@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521141621.GU31290@titan.lakedaemon.net>
 <20130521173707.5a49eaec@skate>
 <20130521154313.GV31290@titan.lakedaemon.net>
 <20130521181018.401ddabf@skate>
Message-ID: <20130521163725.GW31290@titan.lakedaemon.net>

Thomas,

On Tue, May 21, 2013 at 06:10:18PM +0200, Thomas Petazzoni wrote:
> On Tue, 21 May 2013 11:43:13 -0400, Jason Cooper wrote:
> > > > I tried hacking it up to put it in mvebu/soc-internal_regs for a few
> > > > rounds of testing in linux-next during review, however, I'd prefer you
> > > > rebase this on top of mvebu/cleanup.
> > > 
> > > So you mean my next version of the "Internal registers switch" should
> > > be based on mvebu/cleanup, right?
> > 
> > Yes, sorry I wasn't clear, I meant the series.  You can drop 1-3 as
> > well for the next version, since I've pulled those.
> 
> Ok. 1-2 have been merged in mvebu/fixes, and 3 in mvebu/cleanup. So I
> suppose mvebu/cleanup is based on mvebu/fixes ? Or should I base on
> mvebu/cleanup and assume when it will lend in mainline, the mvebu/fixes
> patches will be there (which doesn't make the thing easy for testing
> here, because to test, I actually need all the patches in the same
> branch). Just trying to figure the workflow :)

For your development, I would checkout v3.10-rc2, merge /fixes, then
merge /cleanup, the put 4-9 on top.  Then, when sending, just do 4-9
with a note about the merge dependency on /cleanup, and the boot
dependency on /fixes.

If you'd like, I can hold off on merging it until I can base the series
on an -rc including patches 1 and 2.  As is, I might move #3 into the
same branch as 4-9, but we'll still have the conflict I highlighted
earlier.  And anyone resolving it will probably miss the .init_early
removal.

> > > There will be some next version in any case, because I just found a
> > > bug in the latest patch when booting from a bootloader that has
> > > already done the switch to 0xF1.
> > 
> > Ok, I'll hold off putting it up for testing until v2.
> 
> Well, the current version should be ok build-wise, and works with all
> currently available Marvell bootloaders. The bug can only be seen with
> a bootloader version that has not yet been really released by Marvell.
> 
> But anyway, v2 will follow shortly. With this v1, I was mainly hoping
> for some feedback, to see if the solution was acceptable or not.

That was a great explanation of a Schr?dinger's Register ;-)

thx,

Jason.


From robherring2 at gmail.com  Tue May 21 12:42:12 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 21 May 2013 11:42:12 -0500
Subject: spurious bL cpufreq driver messages
In-Reply-To: <CAKohpomG5E2FAeZGnX3eBw8fOiX3K8sWEeHgb5NT_FT3y+Cg1w@mail.gmail.com>
References: <519686BC.3090101@gmail.com>
 <CAKohpom0cGfWvsCf-jaMyu0cQJi2hVk9_0wskEDH2X7MaeHDLw@mail.gmail.com>
 <CAL_JsqLEv38DwnL4=ToXtEKNrDbgYv_0qiOc+cXZSjnfKVbeNg@mail.gmail.com>
 <CAKohpomG5E2FAeZGnX3eBw8fOiX3K8sWEeHgb5NT_FT3y+Cg1w@mail.gmail.com>
Message-ID: <CAL_JsqKrZzV+kpQ9rUUkhEAV=kiouAWEuuZnKqX63X6ZPsu3cQ@mail.gmail.com>

On Sun, May 19, 2013 at 11:36 PM, Viresh Kumar <viresh.kumar at linaro.org> wrote:
> On 19 May 2013 01:21, Rob Herring <robherring2 at gmail.com> wrote:
>> No, it still registers the bL driver. The problem is not that DT data
>> is missing, but it is present on a single cluster system.
>
> I misread your mail.. I got the problem now.. Below should fix your
> issue (It is rebased on the patch I pointed to you earlier):
>
> Attached too for testing as gmail copy-paste will break it.
>
> @Rafael: Once Rob gives his Tested-by, please queue it for 3.10-rcs
>
> ------------x-----------------x-----------------
>
> From: Viresh Kumar <viresh.kumar at linaro.org>
> Date: Mon, 20 May 2013 09:57:17 +0530
> Subject: [PATCH] cpufreq: arm_big_little_dt: Instantiate as platform_driver
>
> As multiplatform build is being adopted by more and more ARM platforms, initcall
> function should be used very carefully. For example, when both arm_big_little_dt
> and cpufreq-cpu0 drivers are compiled in, arm_big_little_dt driver may try to
> register even if we had platform device for cpufreq-cpu0 registered.
>
> To eliminate this undesired the effect, the patch changes arm_big_little_dt
> driver to have it instantiated as a platform_driver. Then it will only run on
> platforms that create the platform_device "arm-bL-cpufreq-dt".
>
> Reported-by: Rob Herring <robherring2 at gmail.com>
> Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>

That works. Thanks.

Tested-by: Rob Herring <rob.herring at calxeda.com>


From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:38 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:38 +0200
Subject: [PATCH v4 00/12] net: mv643xx_eth DT support and fixes
In-Reply-To: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set picks up work by Florian Fainelli bringing full DT
support to mv643xx_eth and Marvell SoCs using it.

The current v4 patch set drops 1:1 compatibiliy with PPC binding
for two reasons:
(a) PPC parses DT nodes in arch/ppc/sysdev and creates non-DT
    platform_devices itself,
(b) property and node naming for new ethernet devices is slightly
    different ("phy" vs "phy-handle", "marvell," prefix)

Anyway, the two bindings are functionally compatible and PPC bindings
can be converted if desireable. The patch set if fully bisectable and
care has been taken to (a) not reparse on PPC platforms, (b) allow to
use platform_device based registration even if on CONFIG_OF. Not tested
is double registration issues, i.e. if DT nodes are provided but legacy
registration it not yet removed. This double registration should lead
to either non-DT or DT registered device fail on already claimed
ressources.

Also this patch set picks up the opportunity to fix some repeatedly
reported issues with modular mvmdio/mv643xx_eth loading, unloading,
and reloading. It has been tested on SolidRun CuBox (Dove) and
Seagate Dockstar (Kirkwood) so far.

Patch 1 fixes an issue introduced with switch to separate mvmdio
driver, where detaching mv643xx_eth from a phy will not stop the
phy state machine and finally dereference the already removed network
device. Using phy_disconnect properly stops the phy state machine
before detaching from it. Perhaps, this patch should go back in
stable (most likely 3.9 only) if mvmdio separation patch went in
there.

Patch 2 makes use of managed devm_ioremap for the last remaining
non-managed resource.

Patches 3-4 prepare DT support for mv643xx_eth by adding a phy_node
pointer to platform_data and exploiting that phy_node when attaching
to a phy.

Patch 5 introduces DT parsing support for mv643xx_eth by adding a
match table to the shared driver and adding a platform_device for
each of its child nodes.

Patches 6-8 add corresponding device tree nodes to Marvell Dove,
Kirkwood, and Orion5x including all boards. Where known, also
the PHY compatible string has been set to what is reported in the
boards boot loader.

Patches 9, 10-11, and 12 finally remove all legacy platform_device
based registration from Dove, Kirkwood, and Orion5x DT setup. For
Kirkwood also now obsolete board specific setup is removed from
common DT board setup, Kconfig, Makefile, and kirkwood_defconfig.

For the patches above I suggest to take Patches 1-5 through David
Miller's branch, and Patches 6-12 through Jason Cooper's when they
have appeared on mainline linux. The patch set has been based on
todays net-next, if I shall rebase them on any other branch please
name it.

Sebastian Hesselbarth (12):
  net: mv643xx_eth: use phy_disconnect instead of phy_detach
  net: mv643xx_eth: use managed devm_ioremap for port registers
  net: mv643xx_eth: add phy_node to platform_data struct
  net: mv643xx_eth: use of_phy_connect if phy_node present
  net: mv643xx_eth: add DT parsing support
  ARM: dove: add gigabit ethernet and mvmdio device tree nodes
  ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
  ARM: orion5x: add gigabit ethernet and mvmdio device tree nodes
  ARM: dove: remove legacy mv643xx_eth setup
  ARM: kirkwood: remove legacy clk alias for mv643xx_eth
  ARM: kirkwood: remove redundant DT board files
  ARM: orion5x: remove legacy mv643xx_eth board setup

 .../devicetree/bindings/net/marvell-orion-net.txt  |   83 +++++++++
 arch/arm/boot/dts/dove-cubox.dts                   |    7 +
 arch/arm/boot/dts/dove.dtsi                        |   35 ++++
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   16 ++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   16 ++
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   17 ++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   28 +++
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   16 ++
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |   30 ++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   16 ++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   16 ++
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   24 +++
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   16 ++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   28 +++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   27 +++
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   16 ++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   16 ++
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |   16 ++
 arch/arm/boot/dts/kirkwood-topkick.dts             |   16 ++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   16 ++
 arch/arm/boot/dts/kirkwood.dtsi                    |   52 ++++++
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |   17 ++
 arch/arm/boot/dts/orion5x.dtsi                     |   29 ++++
 arch/arm/configs/kirkwood_defconfig                |   16 --
 arch/arm/mach-dove/board-dt.c                      |    9 -
 arch/arm/mach-kirkwood/Kconfig                     |  117 -------------
 arch/arm/mach-kirkwood/Makefile                    |   16 --
 arch/arm/mach-kirkwood/board-dnskw.c               |    7 -
 arch/arm/mach-kirkwood/board-dockstar.c            |   32 ----
 arch/arm/mach-kirkwood/board-dreamplug.c           |   35 ----
 arch/arm/mach-kirkwood/board-dt.c                  |   40 -----
 arch/arm/mach-kirkwood/board-goflexnet.c           |   34 ----
 arch/arm/mach-kirkwood/board-guruplug.c            |   33 ----
 arch/arm/mach-kirkwood/board-ib62x0.c              |   29 ----
 arch/arm/mach-kirkwood/board-iconnect.c            |   10 --
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c      |   34 ----
 arch/arm/mach-kirkwood/board-km_kirkwood.c         |   44 -----
 arch/arm/mach-kirkwood/board-lsxl.c                |   16 --
 arch/arm/mach-kirkwood/board-mplcec4.c             |   14 --
 arch/arm/mach-kirkwood/board-ns2.c                 |   35 ----
 arch/arm/mach-kirkwood/board-openblocks_a6.c       |   26 ---
 arch/arm/mach-kirkwood/board-readynas.c            |    6 -
 arch/arm/mach-kirkwood/board-ts219.c               |   13 --
 arch/arm/mach-kirkwood/board-usi_topkick.c         |   29 ----
 arch/arm/mach-orion5x/edmini_v2-setup.c            |   10 --
 drivers/net/ethernet/marvell/mv643xx_eth.c         |  182 ++++++++++++++++++--
 include/linux/mv643xx_eth.h                        |    2 +
 54 files changed, 739 insertions(+), 621 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-orion-net.txt
 delete mode 100644 arch/arm/mach-kirkwood/board-dockstar.c
 delete mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-goflexnet.c
 delete mode 100644 arch/arm/mach-kirkwood/board-guruplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ib62x0.c
 delete mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
 delete mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ns2.c
 delete mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
 delete mode 100644 arch/arm/mach-kirkwood/board-usi_topkick.c
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org

-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:39 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:39 +0200
Subject: [PATCH v4 01/12] net: mv643xx_eth: use phy_disconnect instead of
 phy_detach
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-2-git-send-email-sebastian.hesselbarth@gmail.com>

Using a separated mdio bus driver with mvmdio, phy_detach on network device
removal will not stop the phy and finally lead to NULL pointer dereference
in mvmdio due to non-existent network device. Use phy_disconnect instead
to properly stop phy device from accessing network device prior removal of
the network device.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: I observed this behavior when removing a modular mv643xx_eth driver
after attaching it to a phy handled by (also modular) mvmdio. The mvmdio
conversion has been done in

commit c3a07134e6aa5b93a37f72ffa3d11fadf72bf757
 ("mv643xx_eth: convert to use the Marvell Orion MDIO driver")

and should go back any -stable version with that commit (propably only 3.9)

@David: I am not sure if the above description is sufficient for a -stable
patch, if you need more, like actual kernel failure, I am sure I can reproduce
it.

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index d0afeea..ef3454c 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2805,7 +2805,7 @@ static int mv643xx_eth_remove(struct platform_device *pdev)
 
 	unregister_netdev(mp->dev);
 	if (mp->phy != NULL)
-		phy_detach(mp->phy);
+		phy_disconnect(mp->phy);
 	cancel_work_sync(&mp->tx_timeout_task);
 
 	if (!IS_ERR(mp->clk))
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:41 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:41 +0200
Subject: [PATCH v4 03/12] net: mv643xx_eth: add phy_node to platform_data
 struct
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-4-git-send-email-sebastian.hesselbarth@gmail.com>

This adds a struct device_node pointer for a phy passed by phandle
to mv643xx_eth node.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 include/linux/mv643xx_eth.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 141d395..6e8215b 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -30,6 +30,7 @@ struct mv643xx_eth_shared_platform_data {
 #define MV643XX_ETH_PHY_ADDR(x)		(0x80 | (x))
 #define MV643XX_ETH_PHY_NONE		0xff
 
+struct device_node;
 struct mv643xx_eth_platform_data {
 	/*
 	 * Pointer back to our parent instance, and our port number.
@@ -41,6 +42,7 @@ struct mv643xx_eth_platform_data {
 	 * Whether a PHY is present, and if yes, at which address.
 	 */
 	int			phy_addr;
+	struct device_node	*phy_node;
 
 	/*
 	 * Use this MAC address if it is valid, overriding the
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:40 +0200
Subject: [PATCH v4 02/12] net: mv643xx_eth: use managed devm_ioremap for port
 registers
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-3-git-send-email-sebastian.hesselbarth@gmail.com>

Make use of managed devm_ioremap and remove corresponding iounmap.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org       
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index ef3454c..e658ebd 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2470,7 +2470,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	if (msp == NULL)
 		return -ENOMEM;
 
-	msp->base = ioremap(res->start, resource_size(res));
+	msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 	if (msp->base == NULL)
 		return -ENOMEM;
 
@@ -2498,7 +2498,6 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
 {
 	struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
 
-	iounmap(msp->base);
 	if (!IS_ERR(msp->clk))
 		clk_disable_unprepare(msp->clk);
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:42 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:42 +0200
Subject: [PATCH v4 04/12] net: mv643xx_eth: use of_phy_connect if phy_node
 present
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-5-git-send-email-sebastian.hesselbarth@gmail.com>

This connects to a phy node passed to the port device instead of probing
the phy by phy_addr.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org       
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |   25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index e658ebd..0f5c3c2 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -60,6 +60,7 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/of_mdio.h>
 
 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
 static char mv643xx_eth_driver_version[] = "1.4";
@@ -2715,17 +2716,27 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	netif_set_real_num_tx_queues(dev, mp->txq_count);
 	netif_set_real_num_rx_queues(dev, mp->rxq_count);
 
-	if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
+	err = 0;
+	if (pd->phy_node) {
+		mp->phy = of_phy_connect(mp->dev, pd->phy_node,
+					 mv643xx_eth_adjust_link, 0,
+					 PHY_INTERFACE_MODE_GMII);
+		if (!mp->phy)
+			err = -ENODEV;
+	} else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
 		mp->phy = phy_scan(mp, pd->phy_addr);
 
-		if (IS_ERR(mp->phy)) {
+		if (IS_ERR(mp->phy))
 			err = PTR_ERR(mp->phy);
-			if (err == -ENODEV)
-				err = -EPROBE_DEFER;
-			goto out;
-		}
-		phy_init(mp, pd->speed, pd->duplex);
+		else
+			phy_init(mp, pd->speed, pd->duplex);
 	}
+	if (err == -ENODEV) {
+		err = -EPROBE_DEFER;
+		goto out;
+	}
+	if (err)
+		goto out;
 
 	SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:46 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:46 +0200
Subject: [PATCH v4 08/12] ARM: orion5x: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-9-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Orion5x boards. Phy nodes are also added with reg property set on a
per-board basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v3->v4:
- convert to new device tree binding

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |   17 ++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   29 ++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 0077fc8..c7e2efd 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -53,3 +53,20 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	&ethphy: ethernet-phy {
+		device-type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		phy-handle = <&ethphy>;
+	};
+};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 892c64e..6fe45d5 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -132,5 +132,34 @@
 			interrupts = <28>;
 			status = "okay";
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72004 0x84>;
+			interrupts = <22>;
+			status = "disabled";
+
+			/* add phy nodes in board file */
+		};
+
+		eth: ethernet-controller at 72000 {
+			compatible = "marvell,orion-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72000 0x4000>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet-port at 0 {
+				device_type = "network";
+				compatible = "marvell,orion-eth-port";
+				reg = <0>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				/* set phy-handle property in board file */
+			};
+		};
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:44 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:44 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds orion-eth and mvmdio device tree nodes for DT enabled
Dove boards. As there is only one ethernet controller on Dove, a default
phy node is also added with a note to set its reg property on a per-board
basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v3->v4:
- convert to new device tree binding

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove-cubox.dts |    7 +++++++
 arch/arm/boot/dts/dove.dtsi      |   35 +++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7e3065a..02618fa 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -49,6 +49,13 @@
 &uart0 { status = "okay"; };
 &sata0 { status = "okay"; };
 &i2c0 { status = "okay"; };
+&mdio { status = "okay"; };
+&eth { status = "okay"; };
+
+&ethphy {
+	compatible = "marvell,88e1310";
+	reg = <1>;
+};
 
 &sdio0 {
 	status = "okay";
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 6cab468..8612658 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -258,5 +258,40 @@
 				dmacap,xor;
 			};
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72004 0x84>;
+			interrupts = <30>;
+			clocks = <&gate_clk 2>;
+			status = "disabled";
+
+			ethphy: ethernet-phy {
+				device-type = "ethernet-phy";
+				/* set phy address in board file */
+			};
+		};
+
+		eth: ethernet-controller at 72000 {
+			compatible = "marvell,orion-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72000 0x4000>;
+			clocks = <&gate_clk 2>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet-port at 0 {
+				device_type = "network";
+				compatible = "marvell,orion-eth-port";
+				reg = <0>;
+				interrupts = <29>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				phy-handle = <&ethphy>;
+			};
+		};
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:47 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:47 +0200
Subject: [PATCH v4 09/12] ARM: dove: remove legacy mv643xx_eth setup
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-10-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards anymore.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/board-dt.c |    9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b14280..048e942 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -34,10 +34,6 @@ static void __init dove_legacy_clk_init(void)
 	clkspec.np = np;
 	clkspec.args_count = 1;
 
-	clkspec.args[0] = CLOCK_GATING_BIT_GBE;
-	orion_clkdev_add(NULL, "mv643xx_eth_port.0",
-			 of_clk_get_from_provider(&clkspec));
-
 	clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
 	orion_clkdev_add("0", "pcie",
 			 of_clk_get_from_provider(&clkspec));
@@ -53,10 +49,6 @@ static void __init dove_of_clk_init(void)
 	dove_legacy_clk_init();
 }
 
-static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
-	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
-};
-
 static void __init dove_dt_init(void)
 {
 	pr_info("Dove 88AP510 SoC\n");
@@ -70,7 +62,6 @@ static void __init dove_dt_init(void)
 	dove_of_clk_init();
 
 	/* Internal devices not ported to DT yet */
-	dove_ge00_init(&dove_dt_ge00_data);
 	dove_pcie_init(1, 1);
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:48 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:48 +0200
Subject: [PATCH v4 10/12] ARM: kirkwood: remove legacy clk alias for
 mv643xx_eth
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-11-git-send-email-sebastian.hesselbarth@gmail.com>

With all boards converted to DT enabled mv643xx_eth we can now
remove the clock alias for gbe clocks. The workaround for ge0/ge1 clock
gates is not removed, as Kirkwood ethernet controllers loose MAC address
stored in internal registers on gated ge0/ge1 clocks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: I confirm that the above workaround is still required, i.e. when
booting DT kernel with non-DT boot loader (no local-mac-address property)
MAC address registers looses its content on clock gating.

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/board-dt.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..8db388a 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -66,12 +66,10 @@ static void __init kirkwood_legacy_clk_init(void)
 	 */
 	clkspec.args[0] = CGC_BIT_GE0;
 	clk = of_clk_get_from_provider(&clkspec);
-	orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
 	clk_prepare_enable(clk);
 
 	clkspec.args[0] = CGC_BIT_GE1;
 	clk = of_clk_get_from_provider(&clkspec);
-	orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
 	clk_prepare_enable(clk);
 }
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:43 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:43 +0200
Subject: [PATCH v4 05/12] net: mv643xx_eth: add DT parsing support
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-6-git-send-email-sebastian.hesselbarth@gmail.com>

This adds device tree parsing support for the shared driver of mv643xx_eth.
As the bindings are slightly different from current PPC bindings new binding
documentation is also added. Following PPC-style device setup, the shared
driver now also adds port platform_devices and sets up port platform_data.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: Although different, device tree bindings are compatible with PPC
bindings. As I do not have access to any PPC platform using mv643xx_eth,
I leave conversion ("phy" vs "phy-handle") and compatible string name
up to PPC guys.

Due to hang reports for modular built mvmdio and mv643xx_eth, I have
tested module loading/unloading/reloading on CuBox (Dove) and Dockstar
(Kirkwood) without any issues for the whole patch set.

Changelog:
v3->v4:
- separation of independent patches (phy, of_mdio, devm)
- stand-alone device tree binding compatible to existing mv64x60 binding
- device node match for shared driver only
- device node registration for port drivers
- properly return -EPROBE_DEFER on missing of phy (Reported by Simon Baatz)

v2->v3:
- rebase on top of mv643xx_eth clean-ups
- do not reparse existing platform_data
- use managed devm_kzalloc for parsed platform_data
- use of_property_read_u32 where applicable
- add phy_node to platform_data
- use of_connect_phy if DT phy node was found

v1->v2:
- properly ifdef of_platform_bus_probe with CONFIG_OF
- handle of_platform_bus_probe errors and cleanup accordingly
- use of_property_read_u32 where applicable
- parse "duplex" and "speed" property in PHY-less configuration

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 .../devicetree/bindings/net/marvell-orion-net.txt  |   83 +++++++++++
 drivers/net/ethernet/marvell/mv643xx_eth.c         |  152 +++++++++++++++++++-
 2 files changed, 231 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-orion-net.txt

diff --git a/Documentation/devicetree/bindings/net/marvell-orion-net.txt b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
new file mode 100644
index 0000000..23ffd57
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
@@ -0,0 +1,83 @@
+Marvell Orion/Discovery ethernet controller
+=============================================
+
+The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
+(Kirkwood, Dove, Orion5x, and Discovery Innovation) and as part of Marvell
+Discovery system controller chips (mv64[345]60).
+
+The Discovery ethernet controller is described with two levels of nodes. The
+first level describes the ethernet controller itself and the second level
+describes up to 3 ethernet port nodes within that controller. The reason for
+the multiple levels is that the port registers are interleaved within a single
+set of controller registers. Each port node describes port-specific properties.
+
+Note: The above separation is only true for Discovery system controllers.
+For Orion SoCs we stick to the separation, although there each controller has
+only one port associated. Multiple ports are implemented as multiple single-port
+controllers.
+
+* Ethernet controller node
+
+Required controller properties:
+ - #address-cells: shall be 1.
+ - #size-cells: shall be 0.
+ - compatible: shall be "marvell,orion-eth".
+ - reg: address and length of the controller registers.
+
+Optional controller properties:
+ - clocks: phandle reference to the controller clock.
+ - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
+
+* Ethernet port node
+
+Required port properties:
+ - device_type: shall be "network".
+ - compatible: shall be "marvell,orion-eth-port".
+ - reg: port number relative to ethernet controller, shall be 0, 1, or 2.
+ - interrupts: port interrupt.
+ - local-mac-address: 6 bytes MAC address.
+
+Optional port properties:
+ - marvell,tx-queue-size: size of the transmit ring buffer.
+ - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
+ - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
+ - marvell,rx-queue-size: size of the receive ring buffer.
+ - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
+ - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
+
+and
+
+ - phy-handle: phandle reference to ethernet PHY.
+
+or
+
+ - speed: port speed if no PHY connected.
+ - duplex: port mode if no PHY connected.
+
+* Node example:
+
+mdio-bus {
+	...
+	ethphy: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		...
+	};
+};
+
+eth: ethernet-controller at 72000 {
+	compatible = "marvell,orion-eth";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x72000 0x2000>;
+	clocks = <&gate_clk 2>;
+	marvell,tx-checksum-limit = <1600>;
+
+	ethernet at 0 {
+		device_type = "network";
+		compatible = "marvell,orion-eth-port";
+		reg = <0>;
+		interrupts = <29>;
+		phy-handle = <&ethphy>;
+		local-mac-address = [00 00 00 00 00 00];
+	};
+};
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 0f5c3c2..f2c229c 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -60,6 +60,9 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_net.h>
 #include <linux/of_mdio.h>
 
 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
@@ -2451,13 +2454,147 @@ static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
 	}
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id mv643xx_eth_shared_ids[] = {
+	{ .compatible = "marvell,orion-eth", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
+#endif
+
+#if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
+#define mv643xx_eth_property(_np, _name, _v)				\
+	do {								\
+		u32 tmp;						\
+		if (!of_property_read_u32(_np, "marvell," _name, &tmp))	\
+			_v = tmp;					\
+	} while (0)
+
+static struct platform_device *port_platdev[3];
+
+static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
+					  struct device_node *pnp)
+{
+	struct platform_device *ppdev;
+	struct mv643xx_eth_platform_data ppd;
+	struct resource res;
+	const char *mac_addr;
+	int ret;
+
+	memset(&ppd, 0, sizeof(ppd));
+	ppd.shared = pdev;
+
+	memset(&res, 0, sizeof(res));
+	if (!of_irq_to_resource(pnp, 0, &res)) {
+		dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
+		dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
+		return -EINVAL;
+	}
+
+	if (ppd.port_number >= 3) {
+		dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
+		return -EINVAL;
+	}
+
+	mac_addr = of_get_mac_address(pnp);
+	if (mac_addr)
+		memcpy(ppd.mac_addr, mac_addr, 6);
+
+	mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
+	mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
+	mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
+	mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
+	mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
+	mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
+
+	ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
+	if (!ppd.phy_node) {
+		ppd.phy_addr = MV643XX_ETH_PHY_NONE;
+		of_property_read_u32(pnp, "speed", &ppd.speed);
+		of_property_read_u32(pnp, "duplex", &ppd.duplex);
+	}
+
+	ppdev = platform_device_alloc(MV643XX_ETH_NAME, ppd.port_number);
+	if (!ppdev)
+		return -ENOMEM;
+	ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+	ret = platform_device_add_resources(ppdev, &res, 1);
+	if (ret)
+		goto port_err;
+
+	ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
+	if (ret)
+		goto port_err;
+
+	ret = platform_device_add(ppdev);
+	if (ret)
+		goto port_err;
+
+	port_platdev[ppd.port_number] = ppdev;
+
+	return 0;
+
+port_err:
+	platform_device_put(ppdev);
+	return ret;
+}
+
+static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
+{
+	struct mv643xx_eth_shared_platform_data *pd;
+	struct device_node *pnp, *np = pdev->dev.of_node;
+	int ret;
+
+	/* bail out if not registered from DT */
+	if (!np)
+		return 0;
+
+	pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return -ENOMEM;
+	pdev->dev.platform_data = pd;
+
+	mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
+
+	for_each_available_child_of_node(np, pnp) {
+		ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
+static void mv643xx_eth_shared_of_remove(void)
+{
+	int n;
+
+	for (n = 0; n < 3; n++) {
+		platform_device_del(port_platdev[n]);
+		port_platdev[n] = NULL;
+	}
+}
+#else
+static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
+{
+	return 0
+}
+
+#define mv643xx_eth_shared_of_remove()
+#endif
+
 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 {
 	static int mv643xx_eth_version_printed;
-	struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
+	struct mv643xx_eth_shared_platform_data *pd;
 	struct mv643xx_eth_shared_private *msp;
 	const struct mbus_dram_target_info *dram;
 	struct resource *res;
+	int ret;
 
 	if (!mv643xx_eth_version_printed++)
 		pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
@@ -2470,6 +2607,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
 	if (msp == NULL)
 		return -ENOMEM;
+	platform_set_drvdata(pdev, msp);
 
 	msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 	if (msp->base == NULL)
@@ -2486,12 +2624,15 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	if (dram)
 		mv643xx_eth_conf_mbus_windows(msp, dram);
 
+	ret = mv643xx_eth_shared_of_probe(pdev);
+	if (ret)
+		return ret;
+	pd = pdev->dev.platform_data;
+
 	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
 					pd->tx_csum_limit : 9 * 1024;
 	infer_hw_params(msp);
 
-	platform_set_drvdata(pdev, msp);
-
 	return 0;
 }
 
@@ -2499,9 +2640,9 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
 {
 	struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
 
+	mv643xx_eth_shared_of_remove();
 	if (!IS_ERR(msp->clk))
 		clk_disable_unprepare(msp->clk);
-
 	return 0;
 }
 
@@ -2511,6 +2652,7 @@ static struct platform_driver mv643xx_eth_shared_driver = {
 	.driver = {
 		.name	= MV643XX_ETH_SHARED_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
 	},
 };
 
@@ -2710,6 +2852,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	if (!IS_ERR(mp->clk)) {
 		clk_prepare_enable(mp->clk);
 		mp->t_clk = clk_get_rate(mp->clk);
+	} else if (!IS_ERR(mp->shared->clk)) {
+		mp->t_clk = clk_get_rate(mp->shared->clk);
 	}
 
 	set_params(mp, pd);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:45 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:45 +0200
Subject: [PATCH v4 07/12] ARM: kirkwood: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-8-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Kirkwood boards. Phy nodes are also added with reg property set on a
per-board basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v3->v4:
- convert to new device tree binding
- fix phy addr of kirkwood-ts219-6282.dts (Reported by Andrew Lunn)
- fix mvmdio interrupt (Reported by Simon Baatz)

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   16 ++++++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   16 ++++++
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   17 +++++++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   28 +++++++++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   16 ++++++
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |   30 +++++++++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   16 ++++++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   16 ++++++
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   24 +++++++++
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   16 ++++++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   28 +++++++++++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   27 ++++++++++
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   16 ++++++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   16 ++++++
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |   16 ++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |   16 ++++++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   16 ++++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   52 ++++++++++++++++++++
 25 files changed, 398 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e..03e1b68 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -87,3 +87,19 @@
 		gpios = <&gpio0 17 0>;
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac0..7c8bc17 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -217,3 +217,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6..b5aebbc 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -91,3 +91,20 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		compatible = "marvell,88e1116";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d..e0c93d4 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -99,3 +99,31 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be..aba5849 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -170,3 +170,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97d..210dfb9 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -96,3 +96,33 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		compatible = "marvell,88e1121";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		compatible = "marvell,88e1121";
+		reg = <1>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1a..fff3e65 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -119,3 +119,19 @@
 
 
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74..cfaf6bc 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -168,3 +168,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 11 {
+		device_type = "ethernet-phy";
+		reg = <11>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94..315f095 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -191,3 +191,27 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy1: ethernet-phy at 11 {
+		device_type = "ethernet-phy";
+		reg = <11>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0a..2e5fe72 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd054..f9194b1 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -43,3 +43,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4..dcc6470 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -201,3 +201,31 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..ceac0de 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -182,3 +182,30 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+
+	ethphy1: ethernet-phy at 2 {
+		device_type = "ethernet-phy";
+		reg = <2>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab..b66b2cd 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -178,3 +178,19 @@
                 };
         };
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd92..6a48bfd 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -82,3 +82,19 @@
 	};
 
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy {
+		device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf..8ffd552 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4e..16332f8 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6..68d767d 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -47,3 +47,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab..5b1b17b 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -48,3 +48,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f724..f8be3e3 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -210,3 +210,19 @@
 		};
         };
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b..34eacf2 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -201,3 +201,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c83..0bd67bf 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -49,4 +49,6 @@
 			gpios = <&gpio0 16 1>;
 		};
 	};
-};
\ No newline at end of file
+};
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95d..a675278 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -49,4 +49,6 @@
 			gpios = <&gpio1 5 1>;
 		};
 	};
-};
\ No newline at end of file
+};
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..68fe091 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -76,3 +76,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy {
+		device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..7c2b690 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -202,5 +202,57 @@
 			clocks = <&gate_clk 4>;
 			status = "disabled";
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72004 0x84>;
+			interrupts = <46>;
+			clocks = <&gate_clk 0>;
+			status = "disabled";
+
+			/* add phy nodes in board file */
+		};
+
+		eth0: ethernet-controller at 72000 {
+			compatible = "marvell,orion-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72000 0x4000>;
+			clocks = <&gate_clk 0>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet0-port at 0 {
+				device_type = "network";
+				compatible = "marvell,orion-eth-port";
+				reg = <0>;
+				interrupts = <11>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				/* set phy-handle property in board file */
+			};
+		};
+
+		eth1: ethernet-controller at 76000 {
+			compatible = "marvell,orion-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x76000 0x4000>;
+			clocks = <&gate_clk 19>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet1-port at 1 {
+				device_type = "network";
+				compatible = "marvell,orion-eth-port";
+				reg = <1>;
+				interrupts = <15>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				/* set phy-handle property in board file */
+			};
+		};
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:49 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:49 +0200
Subject: [PATCH v4 11/12] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-12-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth, board specific init for some boards now
is unneccessary. Remove those board files, Kconfig entries, and
corresponding entries in kirkwood_defconfig.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
the lock-up is not caused by accessing clock gating registers but rather
non-existent device registers. This will be addressed by dtsi separation
for kirkwood and bobcat SoC variants.

Changelog:
v3->v4:
- remove more boards that don't require board specific setup

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/configs/kirkwood_defconfig           |   16 ----
 arch/arm/mach-kirkwood/Kconfig                |  117 -------------------------
 arch/arm/mach-kirkwood/Makefile               |   16 ----
 arch/arm/mach-kirkwood/board-dnskw.c          |    7 --
 arch/arm/mach-kirkwood/board-dockstar.c       |   32 -------
 arch/arm/mach-kirkwood/board-dreamplug.c      |   35 --------
 arch/arm/mach-kirkwood/board-dt.c             |   38 --------
 arch/arm/mach-kirkwood/board-goflexnet.c      |   34 -------
 arch/arm/mach-kirkwood/board-guruplug.c       |   33 -------
 arch/arm/mach-kirkwood/board-ib62x0.c         |   29 ------
 arch/arm/mach-kirkwood/board-iconnect.c       |   10 ---
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   34 -------
 arch/arm/mach-kirkwood/board-km_kirkwood.c    |   44 ----------
 arch/arm/mach-kirkwood/board-lsxl.c           |   16 ----
 arch/arm/mach-kirkwood/board-mplcec4.c        |   14 ---
 arch/arm/mach-kirkwood/board-ns2.c            |   35 --------
 arch/arm/mach-kirkwood/board-openblocks_a6.c  |   26 ------
 arch/arm/mach-kirkwood/board-readynas.c       |    6 --
 arch/arm/mach-kirkwood/board-ts219.c          |   13 ---
 arch/arm/mach-kirkwood/board-usi_topkick.c    |   29 ------
 20 files changed, 584 deletions(-)
 delete mode 100644 arch/arm/mach-kirkwood/board-dockstar.c
 delete mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-goflexnet.c
 delete mode 100644 arch/arm/mach-kirkwood/board-guruplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ib62x0.c
 delete mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
 delete mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ns2.c
 delete mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
 delete mode 100644 arch/arm/mach-kirkwood/board-usi_topkick.c

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252..540ca51 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -30,27 +30,11 @@ CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_T5325=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
-CONFIG_MACH_CLOUDBOX_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
-CONFIG_MACH_DOCKSTAR_DT=y
-CONFIG_MACH_DREAMPLUG_DT=y
-CONFIG_MACH_GOFLEXNET_DT=y
-CONFIG_MACH_GURUPLUG_DT=y
-CONFIG_MACH_IB62X0_DT=y
-CONFIG_MACH_ICONNECT_DT=y
-CONFIG_MACH_INETSPACE_V2_DT=y
-CONFIG_MACH_IOMEGA_IX2_200_DT=y
-CONFIG_MACH_KM_KIRKWOOD_DT=y
 CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_MPLCEC4_DT=y
-CONFIG_MACH_NETSPACE_LITE_V2_DT=y
-CONFIG_MACH_NETSPACE_MAX_V2_DT=y
-CONFIG_MACH_NETSPACE_MINI_V2_DT=y
-CONFIG_MACH_NETSPACE_V2_DT=y
 CONFIG_MACH_NSA310_DT=y
-CONFIG_MACH_OPENBLOCKS_A6_DT=y
 CONFIG_MACH_READYNAS_DT=y
-CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PREEMPT=y
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..c2fd30b 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -146,13 +146,6 @@ config ARCH_KIRKWOOD_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Kirkwood using flattened device tree.
 
-config MACH_CLOUDBOX_DT
-	bool "LaCie CloudBox NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  CloudBox NAS, using Flattened Device Tree.
-
 config MACH_DLINK_KIRKWOOD_DT
 	bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -161,69 +154,6 @@ config MACH_DLINK_KIRKWOOD_DT
 	  Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
 	  using Flattened Device Tree.
 
-config MACH_DOCKSTAR_DT
-	bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Seagate FreeAgent Dockstar (Flattened Device Tree).
-
-config MACH_DREAMPLUG_DT
-	bool "Marvell DreamPlug (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Marvell DreamPlug (Flattened Device Tree).
-
-config MACH_GOFLEXNET_DT
-	bool "Seagate GoFlex Net (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Seagate GoFlex Net (Flattened Device Tree).
-
-config MACH_GURUPLUG_DT
-	bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Marvell GuruPlug Reference Board (Flattened Device Tree).
-
-config MACH_IB62X0_DT
-	bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
-	  Flattened Device Tree.
-
-config MACH_ICONNECT_DT
-	bool "Iomega Iconnect (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here to enable Iomega Iconnect support.
-
-config MACH_INETSPACE_V2_DT
-	bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Internet Space v2 NAS, using Flattened Device Tree.
-
-config MACH_IOMEGA_IX2_200_DT
-	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Iomega StorCenter ix2-200 (Flattened Device Tree).
-
-config MACH_KM_KIRKWOOD_DT
-	bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
-
 config MACH_LSXL_DT
 	bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -239,39 +169,6 @@ config MACH_MPLCEC4_DT
 	  Say 'Y' here if you want your kernel to support the
 	  MPL CEC4 (Flattened Device Tree).
 
-config MACH_NETSPACE_LITE_V2_DT
-	bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space Lite v2 NAS, using Flattened Device Tree.
-
-config MACH_NETSPACE_MAX_V2_DT
-	bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space Max v2 NAS, using Flattened Device Tree.
-
-config MACH_NETSPACE_MINI_V2_DT
-	bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space Mini v2 NAS using Flattened Device Tree.
-
-	  This board is embedded in a product named CloudBox, which
-	  provides automatic backup on a 100GB cloud storage. This
-	  should not confused with a more recent LaCie NAS also named
-	  CloudBox. For this last, the disk capacity is 1TB or above.
-
-config MACH_NETSPACE_V2_DT
-	bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space v2 NAS, using Flattened Device Tree.
-
 config MACH_NSA310_DT
 	bool "ZyXEL NSA-310 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -280,13 +177,6 @@ config MACH_NSA310_DT
 	  Say 'Y' here if you want your kernel to support the
 	  ZyXEL NSA-310 board (Flattened Device Tree).
 
-config MACH_OPENBLOCKS_A6_DT
-	bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Plat'Home OpenBlocks A6 (Flattened Device Tree).
-
 config MACH_READYNAS_DT
 	bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -296,13 +186,6 @@ config MACH_READYNAS_DT
 	  Say 'Y' here if you want your kernel to support the
 	  NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
-config MACH_TOPKICK_DT
-	bool "USI Topkick (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  USI Topkick, using Flattened Device Tree
-
 config MACH_TS219_DT
 	bool "Device Tree for QNAP TS-11X, TS-21X NAS"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735..8e7fa4f 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -20,25 +20,9 @@ obj-$(CONFIG_MACH_TS219)		+= ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
-obj-$(CONFIG_MACH_CLOUDBOX_DT)		+= board-ns2.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)	+= board-dnskw.o
-obj-$(CONFIG_MACH_DOCKSTAR_DT)		+= board-dockstar.o
-obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
-obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
-obj-$(CONFIG_MACH_GURUPLUG_DT)		+= board-guruplug.o
-obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
-obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
-obj-$(CONFIG_MACH_INETSPACE_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
-obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)	+= board-km_kirkwood.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
 obj-$(CONFIG_MACH_MPLCEC4_DT)		+= board-mplcec4.o
-obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)		+= board-nsa310.o
-obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)	+= board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
-obj-$(CONFIG_MACH_TOPKICK_DT)		+= board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index a1aa87f..2af7a95 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,14 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data dnskw_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 /* Register any GPIO for output and set the value */
 static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 {
@@ -36,8 +31,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 
 void __init dnskw_init(void)
 {
-	kirkwood_ge00_init(&dnskw_ge00_data);
-
 	/* Set NAS to turn back on after a power failure */
 	dnskw_gpio_register(37, "dnskw:power:recover", 1);
 }
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
deleted file mode 100644
index d7196db..0000000
--- a/arch/arm/mach-kirkwood/board-dockstar.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-dockstar.c
- *
- * Seagate FreeAgent Dockstar Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * Copied and modified for Seagate GoFlex Net support by
- * Joshua Coombs <josh.coombs at gmail.com> based on ArchLinux ARM's
- * GoFlex kernel patches.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data dockstar_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init dockstar_dt_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&dockstar_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
deleted file mode 100644
index 0903242..0000000
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-dreamplug.c
- *
- * Marvell DreamPlug Reference Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-void __init dreamplug_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&dreamplug_ge00_data);
-	kirkwood_ge01_init(&dreamplug_ge01_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 8db388a..a86b41c 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -104,59 +104,21 @@ static void __init kirkwood_dt_init(void)
 	kexec_reinit = kirkwood_enable_pcie;
 #endif
 
-	if (of_machine_is_compatible("globalscale,dreamplug"))
-		dreamplug_init();
-
-	if (of_machine_is_compatible("globalscale,guruplug"))
-		guruplug_dt_init();
-
 	if (of_machine_is_compatible("dlink,dns-kirkwood"))
 		dnskw_init();
 
-	if (of_machine_is_compatible("iom,iconnect"))
-		iconnect_init();
-
-	if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
-		ib62x0_init();
-
 	if (of_machine_is_compatible("qnap,ts219"))
 		qnap_dt_ts219_init();
 
-	if (of_machine_is_compatible("seagate,dockstar"))
-		dockstar_dt_init();
-
-	if (of_machine_is_compatible("seagate,goflexnet"))
-		goflexnet_init();
-
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
-	if (of_machine_is_compatible("iom,ix2-200"))
-		iomega_ix2_200_init();
-
-	if (of_machine_is_compatible("keymile,km_kirkwood"))
-		km_kirkwood_init();
-
-	if (of_machine_is_compatible("lacie,cloudbox") ||
-	    of_machine_is_compatible("lacie,inetspace_v2") ||
-	    of_machine_is_compatible("lacie,netspace_lite_v2") ||
-	    of_machine_is_compatible("lacie,netspace_max_v2") ||
-	    of_machine_is_compatible("lacie,netspace_mini_v2") ||
-	    of_machine_is_compatible("lacie,netspace_v2"))
-		ns2_init();
-
 	if (of_machine_is_compatible("mpl,cec4"))
 		mplcec4_init();
 
 	if (of_machine_is_compatible("netgear,readynas-duo-v2"))
 		netgear_readynas_init();
 
-	if (of_machine_is_compatible("plathome,openblocks-a6"))
-		openblocks_a6_init();
-
-	if (of_machine_is_compatible("usi,topkick"))
-		usi_topkick_init();
-
 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
deleted file mode 100644
index 9db979a..0000000
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-goflexnet.c
- *
- * Seagate GoFlext Net Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * Copied and modified for Seagate GoFlex Net support by
- * Joshua Coombs <josh.coombs at gmail.com> based on ArchLinux ARM's
- * GoFlex kernel patches.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init goflexnet_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&goflexnet_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
deleted file mode 100644
index a857163..0000000
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-guruplug.c
- *
- * Marvell Guruplug Reference Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data guruplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data guruplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-void __init guruplug_dt_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&guruplug_ge00_data);
-	kirkwood_ge01_init(&guruplug_ge01_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
deleted file mode 100644
index 9a857ae..0000000
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2012 (C), Simon Baatz <gmbnomis at gmail.com>
- *
- * arch/arm/mach-kirkwood/board-ib62x0.c
- *
- * RaidSonic ICY BOX IB-NAS6210 & IB-NAS6220 init for drivers not
- * converted to flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-void __init ib62x0_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&ib62x0_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4..fcaf136 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -11,18 +11,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data iconnect_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
-};
-
-void __init iconnect_init(void)
-{
-	kirkwood_ge00_init(&iconnect_ge00_data);
-}
-
 static int __init iconnect_pci_init(void)
 {
 	if (of_machine_is_compatible("iom,iconnect"))
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
deleted file mode 100644
index e5f7041..0000000
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
- *
- * Iomega StorCenter ix2-200
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
-	.phy_addr       = MV643XX_ETH_PHY_NONE,
-	.speed          = SPEED_1000,
-	.duplex         = DUPLEX_FULL,
-};
-
-static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
-};
-
-void __init iomega_ix2_200_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
-	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
deleted file mode 100644
index 44e4605..0000000
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
- * Valentin Longchamp <valentin.longchamp at keymile.com>
- *
- * arch/arm/mach-kirkwood/board-km_kirkwood.c
- *
- * Keymile km_kirkwood Reference Desing Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/clk.h>
-#include <linux/clk-private.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init km_kirkwood_init(void)
-{
-	struct clk *sata_clk;
-	/*
-	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
-	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
-	 * devices are also not present in this variant, their clocks get
-	 * disabled because unused when clk_disable_unused() gets called.
-	 * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
-	 */
-	sata_clk = clk_get_sys("sata_mv.0", "0");
-	if (!IS_ERR(sata_clk))
-		sata_clk->flags |= CLK_IGNORE_UNUSED;
-	sata_clk = clk_get_sys("sata_mv.0", "1");
-	if (!IS_ERR(sata_clk))
-		sata_clk->flags |= CLK_IGNORE_UNUSED;
-
-	kirkwood_ge00_init(&km_kirkwood_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..3dc0929 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -14,17 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data lsxl_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data lsxl_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 /*
  * On the LS-XHL/LS-CHLv2, the shutdown process is following:
  * - Userland monitors key events until the power switch goes to off position
@@ -40,13 +31,6 @@ static void lsxl_power_off(void)
 
 void __init lsxl_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-
-	kirkwood_ge00_init(&lsxl_ge00_data);
-	kirkwood_ge01_init(&lsxl_ge01_data);
-
 	/* register power-off method */
 	pm_power_off = lsxl_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc66..dd1f655 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -11,24 +11,10 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(2),
-};
-
 void __init mplcec4_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&mplcec4_ge00_data);
-	kirkwood_ge01_init(&mplcec4_ge01_data);
 	kirkwood_pcie_init(KW_PCIE0);
 }
 
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
deleted file mode 100644
index f8f6605..0000000
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2012 (C), Simon Guinot <simon.guinot at sequanux.org>
- *
- * arch/arm/mach-kirkwood/board-ns2.c
- *
- * LaCie Network Space v2 board (and parents) initialization for drivers
- * not converted to flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/of.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data ns2_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-void __init ns2_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	if (of_machine_is_compatible("lacie,cloudbox") ||
-	    of_machine_is_compatible("lacie,netspace_lite_v2") ||
-	    of_machine_is_compatible("lacie,netspace_mini_v2"))
-		ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-	kirkwood_ge00_init(&ns2_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
deleted file mode 100644
index b11d8fd..0000000
--- a/arch/arm/mach-kirkwood/board-openblocks_a6.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
- *
- * arch/arm/mach-kirkwood/board-openblocks_a6.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data openblocks_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init openblocks_a6_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&openblocks_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20..3ab3e0e 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -13,16 +13,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init netgear_readynas_init(void)
 {
-	kirkwood_ge00_init(&netgear_readynas_ge00_data);
 	kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index acb0187..854d448 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -18,27 +18,14 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 #include "tsx1x-common.h"
 
-static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 void __init qnap_dt_ts219_init(void)
 {
-	u32 dev, rev;
-
-	kirkwood_pcie_id(&dev, &rev);
-	if (dev == MV88F6282_DEV_ID)
-		qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-
-	kirkwood_ge00_init(&qnap_ts219_ge00_data);
-
 	pm_power_off = qnap_tsx1x_power_off;
 }
 
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
deleted file mode 100644
index 1cc04ec..0000000
--- a/arch/arm/mach-kirkwood/board-usi_topkick.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-usi_topkick.c
- *
- * USI Topkick Init for drivers not converted to flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data topkick_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init usi_topkick_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&topkick_ge00_data);
-}
-- 
1.7.10.4



From marc.zyngier at arm.com  Tue May 21 12:43:20 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 21 May 2013 17:43:20 +0100
Subject: [PATCH v4 16/32] arm64: KVM: HYP mode world switch implementation
In-Reply-To: <20130521151604.GH27002@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-17-git-send-email-marc.zyngier@arm.com>
 <20130521151604.GH27002@arm.com>
Message-ID: <519BA428.2030506@arm.com>

On 21/05/13 16:16, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:44PM +0100, Marc Zyngier wrote:
>> +// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
>> +ENTRY(__kvm_tlb_flush_vmid_ipa)
>> +       kern_hyp_va     x0
>> +       ldr     x2, [x0, #KVM_VTTBR]
>> +       msr     vttbr_el2, x2
>> +       isb
>> +
>> +       /*
>> +        * We could do so much better if we had the VA as well.
>> +        * Instead, we invalidate Stage-2 for this IPA, and the
>> +        * whole of Stage-1. Weep...
>> +        */
>> +       tlbi    ipas2e1is, x1
>> +       dsb     sy
>> +       tlbi    vmalle1is
>> +       dsb     sy
>> +       isb
>> +
>> +       msr     vttbr_el2, xzr
>> +       isb
>> +       ret
>> +ENDPROC(__kvm_tlb_flush_vmid_ipa)
> 
> There are some isbs here which could be removed if you need an eret
> anyway.

There was some discussions a long while ago on kvmarm about keeping
these isbs in we decided to call them from EL2. I could remove them
altogether and only reintroduce them if/when we decide to do that.

>> +ENTRY(__kvm_flush_vm_context)
>> +       tlbi    alle1is
>> +       ic      ialluis
>> +       dsb     sy
>> +       isb
>> +       ret
>> +ENDPROC(__kvm_flush_vm_context)
> 
> I didn't fully understand - why do we need I-cache maintenance here? Is
> it for ASID-tagged VIVT I-cache?

We do that on VMID rollover, as that's basically the only thing we can
do (nuke everything). There's a comment about that in the call site
(arch/arm/arm.c:update_vttbr).

> BTW, the arch/arm equivalent has some better comments on this code ;).

Sure. I'll try to add some more... But this code has much better arm64
support! ;-)

	M.
-- 
Jazz is not dead. It just smells funny...



From thomas.petazzoni at free-electrons.com  Tue May 21 12:44:13 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 18:44:13 +0200
Subject: [PATCH 6/9] arm: mvebu: move cache and mvebu-mbus
 initialization later
In-Reply-To: <20130521163725.GW31290@titan.lakedaemon.net>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-7-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521141621.GU31290@titan.lakedaemon.net>
 <20130521173707.5a49eaec@skate>
 <20130521154313.GV31290@titan.lakedaemon.net>
 <20130521181018.401ddabf@skate>
 <20130521163725.GW31290@titan.lakedaemon.net>
Message-ID: <20130521184413.68cca154@skate>

Dear Jason Cooper,

On Tue, 21 May 2013 12:37:25 -0400, Jason Cooper wrote:

> On Tue, May 21, 2013 at 06:10:18PM +0200, Thomas Petazzoni wrote:
> > On Tue, 21 May 2013 11:43:13 -0400, Jason Cooper wrote:
> > > > > I tried hacking it up to put it in mvebu/soc-internal_regs for a few
> > > > > rounds of testing in linux-next during review, however, I'd prefer you
> > > > > rebase this on top of mvebu/cleanup.
> > > > 
> > > > So you mean my next version of the "Internal registers switch" should
> > > > be based on mvebu/cleanup, right?
> > > 
> > > Yes, sorry I wasn't clear, I meant the series.  You can drop 1-3 as
> > > well for the next version, since I've pulled those.
> > 
> > Ok. 1-2 have been merged in mvebu/fixes, and 3 in mvebu/cleanup. So I
> > suppose mvebu/cleanup is based on mvebu/fixes ? Or should I base on
> > mvebu/cleanup and assume when it will lend in mainline, the mvebu/fixes
> > patches will be there (which doesn't make the thing easy for testing
> > here, because to test, I actually need all the patches in the same
> > branch). Just trying to figure the workflow :)
> 
> For your development, I would checkout v3.10-rc2, merge /fixes, then
> merge /cleanup, the put 4-9 on top.  Then, when sending, just do 4-9
> with a note about the merge dependency on /cleanup, and the boot
> dependency on /fixes.

Ok, sounds good.

> If you'd like, I can hold off on merging it until I can base the series
> on an -rc including patches 1 and 2.  As is, I might move #3 into the
> same branch as 4-9, but we'll still have the conflict I highlighted
> earlier.  And anyone resolving it will probably miss the .init_early
> removal.

Don't worry, the solution you've proposed earlier sounds fine to me.

> > Well, the current version should be ok build-wise, and works with all
> > currently available Marvell bootloaders. The bug can only be seen with
> > a bootloader version that has not yet been really released by Marvell.
> > 
> > But anyway, v2 will follow shortly. With this v1, I was mainly hoping
> > for some feedback, to see if the solution was acceptable or not.
> 
> That was a great explanation of a Schr?dinger's Register ;-)

That's a nice name for such a complicated register, indeed :)

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sebastian.hesselbarth at gmail.com  Tue May 21 12:41:50 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 May 2013 18:41:50 +0200
Subject: [PATCH v4 12/12] ARM: orion5x: remove legacy mv643xx_eth board setup
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369154510-4927-13-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards. This patch removes eth setup
for all orion5x DT board files.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-orion5x/edmini_v2-setup.c |   10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 1476155..d9de926 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -24,7 +24,6 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
@@ -96,14 +95,6 @@ static struct platform_device edmini_v2_nor_flash = {
 };
 
 /*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data edmini_v2_eth_data = {
-	.phy_addr	= 8,
-};
-
-/*****************************************************************************
  * RTC 5C372a on I2C bus
  ****************************************************************************/
 
@@ -152,7 +143,6 @@ void __init edmini_v2_init(void)
 	 * Configure peripherals.
 	 */
 	orion5x_ehci0_init();
-	orion5x_eth_init(&edmini_v2_eth_data);
 
 	mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
 			      EDMINI_V2_NOR_BOOT_SIZE);
-- 
1.7.10.4



From t.figa at samsung.com  Tue May 21 13:05:45 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 21 May 2013 19:05:45 +0200
Subject: [PATCH v2 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <CAD=FV=XiWET3Xptfk2CVWMw=xVCE4zUJhJtgXHbhiND12rJGnQ@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <18754346.1REWN52J0K@flatron>
 <CAD=FV=XiWET3Xptfk2CVWMw=xVCE4zUJhJtgXHbhiND12rJGnQ@mail.gmail.com>
Message-ID: <4536937.hnhaYZLnaG@amdc1227>

Some GPIO EINT control registers needs to be preserved across
suspend/resume cycle. This patch extends the driver to take care of
this.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---

Changes since v1:
 - Added optional debugging messages
 - Added proper error path in initialization

 drivers/pinctrl/pinctrl-exynos.c | 116 ++++++++++++++++++++++++++++++++++++++-
 drivers/pinctrl/pinctrl-exynos.h |   1 +
 2 files changed, 115 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 4f868e5..864e2c0 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -196,6 +196,12 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+struct exynos_eint_gpio_save {
+	u32 eint_con;
+	u32 eint_fltcon0;
+	u32 eint_fltcon1;
+};
+
 /*
  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
  * @d: driver data of samsung pinctrl driver.
@@ -204,8 +210,9 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 {
 	struct samsung_pin_bank *bank;
 	struct device *dev = d->dev;
-	unsigned int ret;
+	int ret;
 	unsigned int i;
+	unsigned int undo;
 
 	if (!d->irq) {
 		dev_err(dev, "irq number not available\n");
@@ -227,11 +234,30 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 				bank->nr_pins, &exynos_gpio_irqd_ops, bank);
 		if (!bank->irq_domain) {
 			dev_err(dev, "gpio irq domain add failed\n");
-			return -ENXIO;
+			ret = -ENXIO;
+			goto err_domains;
+		}
+
+		bank->soc_priv = devm_kzalloc(d->dev,
+			sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
+		if (!bank->soc_priv) {
+			++i;
+			ret = -ENOMEM;
+			goto err_domains;
 		}
 	}
 
 	return 0;
+
+err_domains:
+	bank = d->ctrl->pin_banks;
+	for (undo = 0; undo < i; ++undo) {
+		if (bank->eint_type != EINT_TYPE_GPIO)
+			continue;
+		irq_domain_remove(bank->irq_domain);
+	}
+
+	return ret;
 }
 
 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
@@ -528,6 +554,72 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 	return 0;
 }
 
+static void exynos_pinctrl_suspend_bank(
+				struct samsung_pinctrl_drv_data *drvdata,
+				struct samsung_pin_bank *bank)
+{
+	struct exynos_eint_gpio_save *save = bank->soc_priv;
+	void __iomem *regs = drvdata->virt_base;
+
+	save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+						+ bank->eint_offset);
+	save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset);
+	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset + 4);
+
+	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
+	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
+	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
+}
+
+static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+		if (bank->eint_type == EINT_TYPE_GPIO)
+			exynos_pinctrl_suspend_bank(drvdata, bank);
+}
+
+static void exynos_pinctrl_resume_bank(
+				struct samsung_pinctrl_drv_data *drvdata,
+				struct samsung_pin_bank *bank)
+{
+	struct exynos_eint_gpio_save *save = bank->soc_priv;
+	void __iomem *regs = drvdata->virt_base;
+
+	pr_debug("%s:     con %#010x => %#010x\n", bank->name,
+			readl(regs + EXYNOS_GPIO_ECON_OFFSET
+			+ bank->eint_offset), save->eint_con);
+	pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
+			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+			+ 2 * bank->eint_offset), save->eint_fltcon0);
+	pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
+			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
+
+	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+						+ bank->eint_offset);
+	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset);
+	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset + 4);
+}
+
+static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+		if (bank->eint_type == EINT_TYPE_GPIO)
+			exynos_pinctrl_resume_bank(drvdata, bank);
+}
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -591,6 +683,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4210-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -605,6 +699,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4210-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -686,6 +782,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -700,6 +798,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -710,6 +810,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl2",
 	}, {
 		/* pin-controller instance 3 data */
@@ -720,6 +822,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl3",
 	},
 };
@@ -798,6 +902,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -808,6 +914,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -818,6 +926,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl2",
 	}, {
 		/* pin-controller instance 3 data */
@@ -828,6 +938,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl3",
 	},
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 9b1f77a..3c91c35 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -19,6 +19,7 @@
 
 /* External GPIO and wakeup interrupt related definitions */
 #define EXYNOS_GPIO_ECON_OFFSET		0x700
+#define EXYNOS_GPIO_EFLTCON_OFFSET	0x800
 #define EXYNOS_GPIO_EMASK_OFFSET	0x900
 #define EXYNOS_GPIO_EPEND_OFFSET	0xA00
 #define EXYNOS_WKUP_ECON_OFFSET		0xE00
-- 
1.8.2.1




From t.figa at samsung.com  Tue May 21 13:06:12 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 21 May 2013 19:06:12 +0200
Subject: [PATCH 3/6] ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled
 platforms
In-Reply-To: <1738596.V1D84NEkmc@amdc1227>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <CACRpkdbVnPhTMKDBtPNAka_V8H-2w2gK7prw9LVPRk_P7NMt7w@mail.gmail.com>
 <1738596.V1D84NEkmc@amdc1227>
Message-ID: <5854402.6rszAeKLin@amdc1227>

Just posted updated version of patch 6/6.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics

On Tuesday 21 of May 2013 15:15:45 Tomasz Figa wrote:
> Hi Linus,
> 
> On Tuesday 21 of May 2013 13:29:23 Linus Walleij wrote:
> > On Fri, May 17, 2013 at 11:07 PM, Tomasz Figa <tomasz.figa at gmail.com> 
wrote:
> > > On Friday 17 of May 2013 13:56:39 Doug Anderson wrote:
> > >> I wouldn't be opposed to a re-spin to address some of the above, but I
> > >> also won't object to this landing and remaining issues being addressed
> > >> in future patches.  This patch definitely does make things better and
> > >> no worse.  :)
> > > 
> > > Let's see. If nobody takes this until Monday, which is very likely, I
> > > will
> > > send new version.
> > 
> > I applied 1 & 2 so pls repost your updated patches 3,4,5,6 on
> > monday and let's continue fixing.
> 
> Thanks.
> 
> Feel free to apply current version of patches 3, 4 and 5 as well. I will
> post updated patch 6 in a while.
> 
> Best regards,
> 
> > Yours,
> > Linus Walleij
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From andy.shevchenko at gmail.com  Tue May 21 13:24:15 2013
From: andy.shevchenko at gmail.com (Andy Shevchenko)
Date: Tue, 21 May 2013 20:24:15 +0300
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <20130521151143.GH10453@mudshark.cambridge.arm.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <20130521151143.GH10453@mudshark.cambridge.arm.com>
Message-ID: <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>

On Tue, May 21, 2013 at 6:11 PM, Will Deacon <will.deacon at arm.com> wrote:
> Hi Andy,
>
> On Tue, May 21, 2013 at 01:33:17PM +0100, Andy Shevchenko wrote:
>> When thread is going to be stopped we have to unconditionally terminate all
>> ongoing transfers. Otherwise it would be possible that callback function will
>> be called on the next interrupt and will try to access to already freed
>> structures.
>>
>> The patch introduces specific error message for this, though it doesn't
>> increase the counter of the failed tests.
>>
>> Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
>> Reported-by: Will Deacon <will.deacon at arm.com>
>
> Thanks for persevering with this! Although this patch definitely fixes the
> panic I was seeing, I now observe buffer verification failures in subsequent
> test runs after an aborted run:

I think the description to the commit adfa543e "dmatest: don't use
set_freezable_with_signal()" may shed light on this.

The background (if  I got it correctly) is in race with done flag. So,
we got a callback call from the DMA engine, but we don't know which
transfer triggers it.
I might be wrong. This is just an assumption.

Have you ever see such behaviour on pre v3.10-rc1 kernels? (I mean
with old dmatest module)

--
With Best Regards,
Andy Shevchenko


From broonie at kernel.org  Mon May 20 12:09:30 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 20 May 2013 11:09:30 -0500
Subject: [PATCH RESEND] spi: sirf: fix the issue while transferring more
 than 256 words
In-Reply-To: <1368877566-27812-1-git-send-email-Baohua.Song@csr.com>
References: <1368877566-27812-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130520160930.GX1627@sirena.org.uk>

On Sat, May 18, 2013 at 07:46:06PM +0800, Barry Song wrote:
> From: Qipan Li <Qipan.Li at csr.com>
> 
> currently, spi irq handler only does rx processing and fetching data from rx
> fifo when "FRM_END" irq happens. FRM_END indicates one transfer completes. if
> rx size is less than 256, it works well.

Applied, thanks.
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From will.deacon at arm.com  Tue May 21 13:33:58 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 May 2013 18:33:58 +0100
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130521102501.GB14432@alberich>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
 <20130513095846.GC29814@mudshark.cambridge.arm.com>
 <20130513104147.GF10369@alberich> <20130517201639.GL10369@alberich>
 <20130520101841.GK31359@mudshark.cambridge.arm.com>
 <20130521102501.GB14432@alberich>
Message-ID: <20130521173357.GA26251@mudshark.cambridge.arm.com>

On Tue, May 21, 2013 at 11:25:01AM +0100, Andreas Herrmann wrote:
> On Mon, May 20, 2013 at 06:18:41AM -0400, Will Deacon wrote:
> > That also looks fine to me, although I'd like to write the parsing code in
> > my driver before I commit to anything!

Right, I hacked that up this afternoon and it seems to be working ok. I'll
post a revised binding soon (hopefully I'll include my driver this time too!).

Will


From aaro.koskinen at iki.fi  Tue May 21 13:39:36 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 21 May 2013 20:39:36 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130520174621.GI10378@atomide.com>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com>
 <20130520174621.GI10378@atomide.com>
Message-ID: <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>

On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
> > * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
> > > On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> > > > * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> > > > > I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> > > > > 
> > > > > [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> > > > > [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> > > > > [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> > > > > 
> > > > > The error is coming from regmap code. According to git bisect, it is
> > > > > caused by:
> > > > > 
> > > > > 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> > > > > 	Author: Jon Hunter <jon-hunter at ti.com>
> > > > > 	Date:   Fri Mar 1 11:22:47 2013 -0600
> > > > > 
> > > > > 	    gpio/omap: convert gpio irq domain to linear mapping
> > > > > 
> > > > > The commit does not anymore revert cleanly, and I haven't yet tried
> > > > > crafting a manual revert, so any fix proposals/ideas are welcome...
> > > > 
> > > > Hmm this might be a bit trickier to fix. Obviously the real solution
> > > > is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> > > > 
> > > > For the -rc cycle, it might be possible to fix this by adding a
> > > > different irq_to_gpio() and gpio_to_irq() functions for omap1.
> > > 
> > > The commit reverts cleanly if we also revert
> > > 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
> > > service routine), which seems to be just some minor optimization. The
> > > result is below, and with it 770 works again.
> > 
> > Hmm in this case it seems that we should just fix it rather than go back
> > to the old code, so let's take a look at that first.
> 
> Does the following fix it for you or do we need to fix something else
> there too?

Thanks, that fixes Retu probe on 770.

Tested-by: Aaro Koskinen <aaro.koskinen at iki.fi>

A.

> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -1094,6 +1094,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
>  	const struct omap_gpio_platform_data *pdata;
>  	struct resource *res;
>  	struct gpio_bank *bank;
> +	int irq_base;
>  
>  	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
>  
> @@ -1135,11 +1136,23 @@ static int omap_gpio_probe(struct platform_device *pdev)
>  				pdata->get_context_loss_count;
>  	}
>  
> -
> -	bank->domain = irq_domain_add_linear(node, bank->width,
> -					     &irq_domain_simple_ops, NULL);
> -	if (!bank->domain)
> +	/*
> +	 * REVISIT: Once we have omap1 supporting  SPARSE_IRQ, we can drop
> +	 * irq_alloc_descs() and irq_domain_add_legacy() and just do:
> +	 *
> +	 * bank->domain = irq_domain_add_linear(node, bank->width,
> +	 *				     &irq_domain_simple_ops, NULL);
> +	 * if (!bank->domain)
> +	 *	return -ENODEV;
> +	 */
> +	irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
> +	if (irq_base < 0) {
> +		dev_err(dev, "Couldn't allocate IRQ numbers\n");
>  		return -ENODEV;
> +	}
> +
> +	bank->domain = irq_domain_add_legacy(node, bank->width, irq_base,
> +					     0, &irq_domain_simple_ops, NULL);
>  
>  	if (bank->regs->set_dataout && bank->regs->clr_dataout)
>  		bank->set_dataout = _set_gpio_dataout_reg;


From andrew at lunn.ch  Tue May 21 13:41:48 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 21 May 2013 19:41:48 +0200
Subject: [PATCH] ARM: Kirkwood: TS219: Fix crash by double PCIe instantiation
Message-ID: <1369158108-5603-1-git-send-email-andrew@lunn.ch>

When creating the DT based boards-ts219.c the none DT ts219-setup.c
was used as a template. This includes a lateinit() call to initialize
the PCIe bus. The code makes use of machine_is_ts219() which is never
true on DT, so a FIXME was added and the code left as is. This was
unproblematic until b73690c8f8b5d: "ARM: Kirkwood: Support basic
hotplug for PCI-E" which changes the way the PCIe bus is
initialized. The non-DT ts219-setup.c now crashes during boot.  The
lateinit() call in the DT boards-ts219.c is being called,
machine_is_ts219() is true and so the PCIe is initialized a second
time.

This patch removes the useless, and now clearly dangerous, code from
boards-ts219.c, making ts219-setup.c work again.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
This can also be tagged for stable 3.9

 arch/arm/mach-kirkwood/board-ts219.c |   10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index acb0187..4695d5f 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -41,13 +41,3 @@ void __init qnap_dt_ts219_init(void)
 
 	pm_power_off = qnap_tsx1x_power_off;
 }
-
-/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */
-static int __init ts219_pci_init(void)
-{
-	if (machine_is_ts219())
-		kirkwood_pcie_init(KW_PCIE0);
-
-	return 0;
-}
-subsys_initcall(ts219_pci_init);
-- 
1.7.10.4



From khilman at linaro.org  Tue May 21 13:46:51 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 21 May 2013 10:46:51 -0700
Subject: OMAP baseline test results for v3.10-rc1
In-Reply-To: <alpine.DEB.2.00.1305192219240.2656@utopia.booyaka.com> (Paul
 Walmsley's message of "Sun, 19 May 2013 22:29:40 +0000 (UTC)")
References: <alpine.DEB.2.00.1305192159080.2656@utopia.booyaka.com>
 <alpine.DEB.2.00.1305192219240.2656@utopia.booyaka.com>
Message-ID: <874ndwmdis.fsf@linaro.org>

Paul Walmsley <paul at pwsan.com> writes:

[...]

> PM: chip retention via suspend:
>     FAIL ( 4/ 6): 2430sdp, 37xxevm, 4430es2panda, 4460pandaes
>     Pass ( 2/ 6): 3530es3beagle, 3730beaglexm

FYI...

I also just noticed that 3730beaglexm has stopped waking from suspend
via RTC (non-DT boot.)  Waking from UART console still works.

Worked fine on v3.9, so there's a regressions somewhere.

Kevin


From andrew at lunn.ch  Tue May 21 13:48:49 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 21 May 2013 19:48:49 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130521174849.GL26249@lunn.ch>

On Tue, May 21, 2013 at 06:41:44PM +0200, Sebastian Hesselbarth wrote:
> This patch adds orion-eth and mvmdio device tree nodes for DT enabled
> Dove boards. As there is only one ethernet controller on Dove, a default
> phy node is also added with a note to set its reg property on a per-board
> basis.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Changelog:
> v3->v4:
> - convert to new device tree binding
> 
> Cc: David Miller <davem at davemloft.net>
> Cc: Lennert Buytenhek <buytenh at wantstofly.org>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: netdev at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linuxppc-dev at lists.ozlabs.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/boot/dts/dove-cubox.dts |    7 +++++++
>  arch/arm/boot/dts/dove.dtsi      |   35 +++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
> index 7e3065a..02618fa 100644
> --- a/arch/arm/boot/dts/dove-cubox.dts
> +++ b/arch/arm/boot/dts/dove-cubox.dts
> @@ -49,6 +49,13 @@
>  &uart0 { status = "okay"; };
>  &sata0 { status = "okay"; };
>  &i2c0 { status = "okay"; };
> +&mdio { status = "okay"; };
> +&eth { status = "okay"; };
> +
> +&ethphy {
> +	compatible = "marvell,88e1310";
> +	reg = <1>;
> +};
>  
>  &sdio0 {
>  	status = "okay";
> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
> index 6cab468..8612658 100644
> --- a/arch/arm/boot/dts/dove.dtsi
> +++ b/arch/arm/boot/dts/dove.dtsi
> @@ -258,5 +258,40 @@
>  				dmacap,xor;
>  			};
>  		};
> +
> +		mdio: mdio-bus at 72004 {
> +			compatible = "marvell,orion-mdio";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x72004 0x84>;
> +			interrupts = <30>;
> +			clocks = <&gate_clk 2>;
> +			status = "disabled";
> +
> +			ethphy: ethernet-phy {
> +				device-type = "ethernet-phy";
> +				/* set phy address in board file */
> +			};
> +		};
> +
> +		eth: ethernet-controller at 72000 {
> +			compatible = "marvell,orion-eth";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x72000 0x4000>;
> +			clocks = <&gate_clk 2>;
> +			marvell,tx-checksum-limit = <1600>;
> +			status = "disabled";
> +
> +			ethernet-port at 0 {
> +				device_type = "network";
> +				compatible = "marvell,orion-eth-port";
> +				reg = <0>;
> +				interrupts = <29>;
> +				/* overwrite MAC address in bootloader */
> +				local-mac-address = [00 00 00 00 00 00];

Hi Sebastian

Its probably a good idea to set the local administration bit in this
MAC address. i.e. first byte is 02.

    Andrew


From thomas.petazzoni at free-electrons.com  Tue May 21 13:53:09 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 19:53:09 +0200
Subject: [PATCH] arm: mvebu: enable two USB interfaces on the Armada XP GP
 board
Message-ID: <1369158789-3218-1-git-send-email-thomas.petazzoni@free-electrons.com>

The Armada XP GP board has two USB slots: one on the front side and
one on the back side. This commit enables the two USB host controllers
that correspond to those wo USB slots.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-xp-gp.dts |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 26ad06f..f63426e 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -101,6 +101,16 @@
 				phy-mode = "rgmii-id";
 			};
 
+			/* Front-side USB slot */
+			usb at 50000 {
+				status = "okay";
+			};
+
+			/* Back-side USB slot */
+			usb at 51000 {
+				status = "okay";
+			};
+
 			spi0: spi at 10600 {
 				status = "okay";
 
-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Tue May 21 14:04:05 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Tue, 21 May 2013 20:04:05 +0200
Subject: [PATCH v2 1/3] staging: drm/imx: set correct sync pins for display
In-Reply-To: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>
References: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>
Message-ID: <1369159448-14584-2-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

Have to call imx_drm_crtc_panel_format_pins in imx_drm_crtc_panel_format
with the correct pins instead of (0, 0) This enables configuration of
correct waveforms for vsync / hsync for parallel display, LDB (i.MX53 and
i.MX6) as well as HDMI and MIPI (i.MX6)

TODO: configure pins via device tree

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
---
V2:
  changed patch as suggested by Philipp Zabel. This will
  fix regressions for other interfaces, too

 drivers/staging/imx-drm/imx-drm-core.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 6455305..8c433fc 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -144,7 +144,7 @@ int imx_drm_crtc_panel_format(struct drm_crtc *crtc, u32 encoder_type,
 		u32 interface_pix_fmt)
 {
 	return imx_drm_crtc_panel_format_pins(crtc, encoder_type,
-					      interface_pix_fmt, 0, 0);
+					      interface_pix_fmt, 2, 3);
 }
 EXPORT_SYMBOL_GPL(imx_drm_crtc_panel_format);
 
-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Tue May 21 14:04:04 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Tue, 21 May 2013 20:04:04 +0200
Subject: [PATCH v2 0/3] staging: fix parallel display regressions
Message-ID: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

Support for VGA via TVE on i.MX53 causes regressions, which prevents
parallel display from working. This series brings the parallel display
functionality back.

The updated series was tested with 3.10-rc2 on a TQMa53 module with
modified device tree.

Markus Niebel (3):
  staging: drm/imx: set correct sync pins for display
  staging: drm/imx: fix spelling error for vsync flag config
  staging: drm/imx: revert vsync_cnt for di->id 1

 drivers/staging/imx-drm/imx-drm-core.c  |    2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-di.c |   13 +++++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)

-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Tue May 21 14:04:07 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Tue, 21 May 2013 20:04:07 +0200
Subject: [PATCH v2 3/3] staging: drm/imx: revert vsync_cnt for di->id 1
In-Reply-To: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>
References: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>
Message-ID: <1369159448-14584-4-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

parallel display support / DVI needs the original setting to work

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
Acked-by: Philipp Zabel <p.zabel at pengutronix.de>
---
V2:
  - no changes in patch
  - add Acked-by from v1 of patch

 drivers/staging/imx-drm/ipu-v3/ipu-di.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index e7b9c98..0b6806e 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
@@ -603,7 +603,12 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 		vsync_cnt = 3;
 		if (di->id == 1)
-			vsync_cnt = 6;
+			/*
+			 * TODO: change only for TVEv2, parallel display
+			 * uses pin 2 / 3
+			 */
+			if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
+				vsync_cnt = 6;
 
 		if (sig->Hsync_pol) {
 			if (sig->hsync_pin == 2)
-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Tue May 21 14:04:06 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Tue, 21 May 2013 20:04:06 +0200
Subject: [PATCH v2 2/3] staging: drm/imx: fix spelling error for vsync flag
 config
In-Reply-To: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>
References: <1369159448-14584-1-git-send-email-list-09_linux_arm@tqsc.de>
Message-ID: <1369159448-14584-3-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

Have to check for vsync_pin instead of hsync_pin to set Vsync_pol.

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
Acked-by: Philipp Zabel <p.zabel at pengutronix.de>
---
V2:
  - no changes in patch
  - add Acked-by from v1 of patch

 drivers/staging/imx-drm/ipu-v3/ipu-di.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index 19d777e..e7b9c98 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
@@ -614,11 +614,11 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 				di_gen |= DI_GEN_POLARITY_7;
 		}
 		if (sig->Vsync_pol) {
-			if (sig->hsync_pin == 3)
+			if (sig->vsync_pin == 3)
 				di_gen |= DI_GEN_POLARITY_3;
-			else if (sig->hsync_pin == 6)
+			else if (sig->vsync_pin == 6)
 				di_gen |= DI_GEN_POLARITY_6;
-			else if (sig->hsync_pin == 8)
+			else if (sig->vsync_pin == 8)
 				di_gen |= DI_GEN_POLARITY_8;
 		}
 	}
-- 
1.7.9.5



From will.deacon at arm.com  Tue May 21 14:02:01 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 May 2013 19:02:01 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130520171349.GM3639@MacBook-Pro.local>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <20130520142459.GN31359@mudshark.cambridge.arm.com>
 <20130520151158.GA3520@MacBook-Pro.local>
 <20130520160407.GS31359@mudshark.cambridge.arm.com>
 <20130520171349.GM3639@MacBook-Pro.local>
Message-ID: <20130521180201.GB26251@mudshark.cambridge.arm.com>

On Mon, May 20, 2013 at 06:13:52PM +0100, Catalin Marinas wrote:
> On Mon, May 20, 2013 at 05:04:07PM +0100, Will Deacon wrote:
> > On Mon, May 20, 2013 at 04:11:58PM +0100, Catalin Marinas wrote:
> > > Given that the ARM ARM isn't clear (though this is the case on the
> > > actual implementations), user space may not necessarily assume that
> > > LPAE==atomic doubles. That's why I think reporting the actual atomic
> > > feature is better.
> > 
> > The ARM ARM isn't too bad: it's just avoiding mandating 64-bit-wide paths
> > around the entire SoC (and I've checked this with the architects). The only
> > way we can probe this feature is using the MMFR0 and checking if LPAE is
> > supported, and that's exactly what userspace will need to rely on.
> 
> Well, LPAE implies atomic doubles but I wouldn't say that's the "only"
> way, it can always be a feature of the CPU. Now, would the user
> developers fully understand the implications of LPAE?

I don't think it *can* be a feature of the CPU, because it depends on
system-wide support. It could be a feature of an SoC, but per-SoC hwcaps
isn't something we currently support. As I said, the only reason we can even
probe this is because the architecture helps us out.

> > We can
> > change the name, but the probe code will remain the same so I'm not sure it
> > makes anything clearer. We had "atomicd" originally, but that sounds like a
> > techno band.
> 
> We can make it longer, 'atomicdbl', if that's the issue ;).

Argh! :)

Will


From tony at atomide.com  Tue May 21 14:11:10 2013
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 21 May 2013 11:11:10 -0700
Subject: [GIT PULL] ARM: OMAP2+: hwmod/serial: fix DT case
In-Reply-To: <alpine.DEB.2.00.1305192331390.2656@utopia.booyaka.com>
References: <alpine.DEB.2.00.1305192331390.2656@utopia.booyaka.com>
Message-ID: <20130521181109.GR10378@atomide.com>

Olof,

Care to pull this into your fixes directly?

Regards,

Tony

* Paul Walmsley <paul at pwsan.com> [130519 16:39]:
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/omap-fixes-a-for-3.10-rc
> 
> for you to fetch changes up to 3260c76055afc6c9396e5ad9f9e599505ea8891f:
> 
>   ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis (2013-05-19 16:37:15 -0600)
> 
> ----------------------------------------------------------------
> Fix the OMAP serial driver to work correctly on OMAP4 when booting
> with DT.
> 
> Basic build, boot, and PM test logs are here - unfortunately, not for
> the DT case yet:
> 
> http://www.pwsan.com/omap/testlogs/uart_idle_fix_v3.10-rc/20130519164010/
> 
> ----------------------------------------------------------------
> Rajendra Nayak (2):
>       ARM: OMAP2+: hwmod: Fix sidle programming in _enable_sysc()/_idle_sysc()
>       ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in active
> 
> Santosh Shilimkar (4):
>       ARM: OMAP2+: hwmod-data: UART IP needs software control to manage sidle modes
>       ARM: OMAP2+: serial: Remove the un-used slave idle hooks
>       SERIAL: OMAP: Remove the slave idle handling from the driver
>       ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis
> 
>  arch/arm/mach-omap2/omap_hwmod.c                   |  111 +++++---------------
>  arch/arm/mach-omap2/omap_hwmod.h                   |    7 +-
>  arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    3 +
>  arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |    6 ++
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    4 +
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 +-
>  arch/arm/mach-omap2/serial.c                       |   31 ------
>  drivers/tty/serial/omap-serial.c                   |   23 ----
>  include/linux/platform_data/serial-omap.h          |    2 -
>  9 files changed, 48 insertions(+), 145 deletions(-)


From khilman at linaro.org  Tue May 21 14:20:03 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 21 May 2013 11:20:03 -0700
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <20130520220540.GL10378@atomide.com> (Tony Lindgren's message of
 "Mon, 20 May 2013 15:05:40 -0700")
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com>
 <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de>
 <20130517185620.GF28484@animalcreek.com>
 <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>
 <20130520220540.GL10378@atomide.com>
Message-ID: <87zjvokxf0.fsf@linaro.org>

Tony Lindgren <tony at atomide.com> writes:

> * Yegor Yefremov <yegorslists at googlemail.com> [130517 14:34]:
>> On Fri, May 17, 2013 at 8:56 PM, Mark A. Greer <mgreer at animalcreek.com> wrote:
>> > On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
>> >> On 15.05.2013 23:50, Mark A. Greer wrote:
>> >> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
>> >
>> >> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
>> >> >> idle states with?
>> >> >
>> >> > I have an am35xx which isn't supposed to have an IVA so I can test with it
>> >> > (although, I'm not sure how well the kernel works on the am35xx these days).
>> >> >
>> >> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
>> >> > comes up, see what I can figure out.
>> >>
>> >> I think this issue is relevant to am3517 as you can see from this
>> >> thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
>> >> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
>> >>
>> >> I have such a system running, so if you have any other patches/ideas to test, I would do it.
>> >
>> > Yegor, since I've so far been unable to get my am3517evm to fire up, can
>> > you play around with the 3517 to see if there appears to be iva registers
>> > that can be read/written to safely?  In particular, can the code that idles
>> > the iva be run safely on an am3517?
>> 
>> I'll look into this next week. am3517 and IVA seems to be a really big
>> mystery. In the TI forum will be stated, there is no IVA:
>> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/150961.aspx, but TRM
>> has various appearances of IVA2 registers, but no real
>> description/explanation of what is IVA and how to eat it.
>
> On 3703 it looks like the whole omap3_iva_idle() reset is needed, except
> for setting the iva2 bootmode to idle. So I'm planning to merge the following
> patch with just comments update this week unless somebody has a better fix
> in mind.
>
> Regards,
>
> Tony
>
>
> From: Tony Lindgren <tony at atomide.com>
> Date: Tue, 14 May 2013 20:28:15 -0700
> Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
>
> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
> changed PM to not access IVA registers on omaps that don't have
> them. Turns out we still need to idle iva2 as otherwise
> iva2_pwrdm will stay on and block deeper idle states.
>
> It seems that the only part of the reset that may not be needed
> is the setting of the iva2 boot mode to idle. But as that register
> seems to be there and is harmless if no iva2 is on the SoC, it's
> probably safest to do the complete reset.
>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Acked-by: Kevin Hilman <khilman at linaro.org>

> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
>  	/* Clear any pending PRCM interrupts */
>  	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
>  
> -	if (omap3_has_iva())
> -		omap3_iva_idle();
> +	/*
> +	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
> +	 */
> +	omap3_iva_idle();
>  
>  	omap3_d2d_idle();
>  }


From lars at metafoo.de  Tue May 21 14:23:16 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Tue, 21 May 2013 20:23:16 +0200
Subject: [PATCH v4] ASoC: dfbmcs320: make the driver common for other
 BT modules
In-Reply-To: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>
References: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <519BBB94.5010408@metafoo.de>

On 05/18/2013 02:25 PM, Barry Song wrote:
> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips, we
> don't want everyone to have a seperate codec driver. anyway, the feature
> of Bluetooth SCO is same on all platforms, so this patch makes the
> DFBM-CS320 driver become a common BT SCO link driver.
> 
> Cc: Graeme Gregory <graeme at openmoko.org> Cc: Lars-Peter Clausen
> <lars at metafoo.de> Signed-off-by: Barry Song <Baohua.Song at csr.com> --- v4: 
> change "select SND_SOC_DFBMCS320" to "select SND_SOC_BT_SCO" for OpenMOKO
> user as v3 missed this
> 

Looks good to me.

Acked-by: Lars-Peter Clausen <lars at metafoo.de>


From arnd at arndb.de  Tue May 21 14:23:03 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 May 2013 20:23:03 +0200
Subject: [PATCH V2 1/2] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <519B2EAD.4000208@broadcom.com>
References: <1368200883-15668-1-git-send-email-csd@broadcom.com>
 <201305170009.46244.arnd@arndb.de> <519B2EAD.4000208@broadcom.com>
Message-ID: <201305212023.03272.arnd@arndb.de>

On Tuesday 21 May 2013, Christian Daudt wrote:
> >> +    cfg = devm_kzalloc(&pdev->dev, sizeof(*cfg), GFP_KERNEL);
> >> +    if (!cfg) {
> >> +            dev_err(&pdev->dev, "Can't allocate platform cfg\n");
> >> +            return NULL;
> >> +    }
> > Not needed
> what is not needed ?

The allocation, it can be part of the sdhci_pltfm_host data.

> >> +    const struct sdhci_pltfm_data *plat_data;
> > make it global.
> why make this global ?

Sorry for being unclear. I mean you can just use &sdhci_pltfm_data_kona
in the probe function, since the data is constant anyway, no need to have
a local variable for pulling this out of the device id.

	Arnd


From broonie at kernel.org  Tue May 21 14:18:49 2013
From: broonie at kernel.org (Mark Brown)
Date: Tue, 21 May 2013 13:18:49 -0500
Subject: [PATCH v4] ASoC: dfbmcs320: make the driver common for other BT
 modules
In-Reply-To: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>
References: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130521181849.GG1627@sirena.org.uk>

On Sat, May 18, 2013 at 08:25:00PM +0800, Barry Song wrote:
> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
> we don't want everyone to have a seperate codec driver. anyway, the
> feature of Bluetooth SCO is same on all platforms, so this patch
> makes the DFBM-CS320 driver become a common BT SCO link driver.

Applied, thanks.
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From andreas.herrmann at calxeda.com  Tue May 21 14:35:07 2013
From: andreas.herrmann at calxeda.com (Andreas Herrmann)
Date: Tue, 21 May 2013 20:35:07 +0200
Subject: [PATCH v2] documentation: iommu: add description of ARM System
 MMU binding
In-Reply-To: <20130521173357.GA26251@mudshark.cambridge.arm.com>
References: <1365789727-5371-1-git-send-email-will.deacon@arm.com>
 <20130513095020.GB10369@alberich>
 <20130513095846.GC29814@mudshark.cambridge.arm.com>
 <20130513104147.GF10369@alberich> <20130517201639.GL10369@alberich>
 <20130520101841.GK31359@mudshark.cambridge.arm.com>
 <20130521102501.GB14432@alberich>
 <20130521173357.GA26251@mudshark.cambridge.arm.com>
Message-ID: <20130521183507.GB2723@alberich>

On Tue, May 21, 2013 at 01:33:58PM -0400, Will Deacon wrote:
> On Tue, May 21, 2013 at 11:25:01AM +0100, Andreas Herrmann wrote:
> > On Mon, May 20, 2013 at 06:18:41AM -0400, Will Deacon wrote:
> > > That also looks fine to me, although I'd like to write the parsing code in
> > > my driver before I commit to anything!
> 
> Right, I hacked that up this afternoon and it seems to be working ok. I'll
> post a revised binding soon (hopefully I'll include my driver this time too!).

Cool.


Thanks,

Andreas


From gregkh at linuxfoundation.org  Tue May 21 14:40:46 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Tue, 21 May 2013 11:40:46 -0700
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
Message-ID: <20130521184046.GA7827@kroah.com>

On Tue, May 21, 2013 at 10:42:00AM +0800, Libo Chen wrote:
> I find a lot of mistakes using struct platform_driver without owner.
> So I pick up some of them including usb and net modules

Like others said, make the function call a macro that sets the module
owner in it, like all of the other major subsystem registration calls do
(usb_drivers, pci_drivers, etc.)

thanks,

greg k-h


From robherring2 at gmail.com  Tue May 21 14:48:35 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 21 May 2013 13:48:35 -0500
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130520141809.GA27473@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
Message-ID: <CAL_JsqLSC2QgMdTGtH5G_F5SYjA3Hs--jMmxBES=fqGLwapptQ@mail.gmail.com>

On Mon, May 20, 2013 at 9:18 AM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
>> CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
>> userspace software can avoid having to use the exclusive variants of
>> these instructions if they wish.
>>
>> This patch advertises the atomicity of these instructions via the
>> hwcaps, so userspace can detect this CPU feature.
>>
>> Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
>> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ...
>> +
>> +     /* LPAE implies atomic ldrd/strd instructions */
>> +     vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
>> +     if (vmsa >= 5)
>> +             elf_hwcap |= HWCAP_LPAE;
>
> As I mentioned in the past, I don't agree with exposing the "LPAE"
> feature to user-space, it's not a feature that user space should care
> about. An atomic double hwcap is better and you can even make this per
> CPU via __v7_proc.

How does userspace know whether to install a non-LPAE or LPAE kernel
in a generic way?

Rob


From s.hauer at pengutronix.de  Tue May 21 15:24:30 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 21 May 2013 21:24:30 +0200
Subject: [PATCH] ARM: iomux-mx51: Always define PUE for pins used as GPIO
In-Reply-To: <1369124845-19244-1-git-send-email-shc_work@mail.ru>
References: <1369124845-19244-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130521192430.GU32299@pengutronix.de>

On Tue, May 21, 2013 at 12:27:25PM +0400, Alexander Shiyan wrote:
> This patch adds a PUE bit for pins which used as GPIO. This allow
> to use the GPIOs correctly as inputs when source is open-drain with
> external pullup resistor (IRQ open-drain outputs for example).

I don't understand. If there's an external pullup why do you want to
turn on the internal one?

Sascha

> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  arch/arm/mach-imx/iomux-mx51.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
> index 75bbcc4..7dc187c 100644
> --- a/arch/arm/mach-imx/iomux-mx51.h
> +++ b/arch/arm/mach-imx/iomux-mx51.h
> @@ -34,7 +34,8 @@
>  #define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
>  				PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
>  				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
> -#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
> +#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
> +				PAD_CTL_PUE | PAD_CTL_SRE_FAST)
>  
>  #define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
>  #define MX51_PAD_CTRL_3		(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
> -- 
> 1.8.1.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jgchunter at gmail.com  Tue May 21 15:37:16 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Tue, 21 May 2013 20:37:16 +0100
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com> <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
Message-ID: <519BCCEC.8010303@gmail.com>


On 21/05/13 18:39, Aaro Koskinen wrote:
> On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
>> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
>>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
>>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
>>>>>>
>>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
>>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
>>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
>>>>>>
>>>>>> The error is coming from regmap code. According to git bisect, it is
>>>>>> caused by:
>>>>>>
>>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
>>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
>>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
>>>>>>
>>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
>>>>>>
>>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
>>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
>>>>>
>>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
>>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
>>>>>
>>>>> For the -rc cycle, it might be possible to fix this by adding a
>>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
>>>>
>>>> The commit reverts cleanly if we also revert
>>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
>>>> service routine), which seems to be just some minor optimization. The
>>>> result is below, and with it 770 works again.
>>>
>>> Hmm in this case it seems that we should just fix it rather than go back
>>> to the old code, so let's take a look at that first.
>>
>> Does the following fix it for you or do we need to fix something else
>> there too?
> 
> Thanks, that fixes Retu probe on 770.

Sorry for not responding sooner, but I have been moving. 

>From looking at the code it appears that the regmap_add_irq_chip()
is failing in the retu driver. I am not sure if this will work, 
but have you tried making the following change to the retu driver 
so that it also uses irq_domain_add_linear() as well? Just a thought ...

Cheers
Jon

diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
index a183098..7ad8cd4 100644
--- a/drivers/mfd/retu-mfd.c
+++ b/drivers/mfd/retu-mfd.c
@@ -267,7 +267,7 @@ static int retu_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
        if (ret < 0)
                return ret;
 
-       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, -1,
+       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, 0,
                                  rdat->irq_chip, &rdev->irq_data);
        if (ret < 0)
                return ret;



From w at 1wt.eu  Tue May 21 15:38:03 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Tue, 21 May 2013 21:38:03 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130521193803.GA20882@1wt.eu>

Hi Thomas,

On Tue, May 21, 2013 at 12:33:25PM +0200, Thomas Petazzoni wrote:
(...)
> As it was explained above, we unfortunately can't read the
> current base address of the internal register window, so we need a
> different mechanism to know if the bootloader has done the remapping
> at 0xF1000000 (new generation bootloader) or has left the internal
> registers at 0xD0000000 (old generation bootloader).

Just out of curiosity, what happens if you touch the register at the
wrong address ? I mean, if you blindly write to the 0xD0xxxxxx address
that you want the registers to be mapped at 0xF1xxxxxx. Will the chip
hang, will it silently ignore the sequence ? Because maybe you don't
need to detect using CP15 whether the remapping was done, you could
simply perform it unconditionally. Another point would be that if the
boot loader is the only one to know whether the registeres were remapped,
then maybe it could put something into the atags or DT about this. And
maybe we'll simply find that DT-enabled boot loaders are remapped and
that non-DT ones are not.

Just a few ideas since you feel a bit worried about the fragility of
the CP15 bit :-)

Willy



From thomas.petazzoni at free-electrons.com  Tue May 21 16:12:35 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 May 2013 22:12:35 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130521193803.GA20882@1wt.eu>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu>
Message-ID: <20130521221235.61491ecb@skate>

Dear Willy Tarreau,

On Tue, 21 May 2013 21:38:03 +0200, Willy Tarreau wrote:

> Just out of curiosity, what happens if you touch the register at the
> wrong address ?

On Armada 370/XP, it hangs the CPU.

> I mean, if you blindly write to the 0xD0xxxxxx address
> that you want the registers to be mapped at 0xF1xxxxxx. Will the chip
> hang, will it silently ignore the sequence ?

Answered above: it hangs.

> Because maybe you don't need to detect using CP15 whether the remapping was done,
> you could simply perform it unconditionally. Another point would be that if the
> boot loader is the only one to know whether the registeres were remapped,
> then maybe it could put something into the atags or DT about this. And
> maybe we'll simply find that DT-enabled boot loaders are remapped and
> that non-DT ones are not.
> 
> Just a few ideas since you feel a bit worried about the fragility of
> the CP15 bit :-)

No, as explained above, we have considered a way of "detecting" whether
the remapping occurred, or to unconditionally do the remapping. But
none of those solutions work: we need to know, through some external
mechanism, whether the remapping has already taken place or not.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From w at 1wt.eu  Tue May 21 16:26:01 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Tue, 21 May 2013 22:26:01 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130521221235.61491ecb@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu> <20130521221235.61491ecb@skate>
Message-ID: <20130521202601.GB20882@1wt.eu>

On Tue, May 21, 2013 at 10:12:35PM +0200, Thomas Petazzoni wrote:
> Dear Willy Tarreau,
> 
> On Tue, 21 May 2013 21:38:03 +0200, Willy Tarreau wrote:
> 
> > Just out of curiosity, what happens if you touch the register at the
> > wrong address ?
> 
> On Armada 370/XP, it hangs the CPU.
> 
> > I mean, if you blindly write to the 0xD0xxxxxx address
> > that you want the registers to be mapped at 0xF1xxxxxx. Will the chip
> > hang, will it silently ignore the sequence ?
> 
> Answered above: it hangs.
> 
> > Because maybe you don't need to detect using CP15 whether the remapping was done,
> > you could simply perform it unconditionally. Another point would be that if the
> > boot loader is the only one to know whether the registeres were remapped,
> > then maybe it could put something into the atags or DT about this. And
> > maybe we'll simply find that DT-enabled boot loaders are remapped and
> > that non-DT ones are not.
> > 
> > Just a few ideas since you feel a bit worried about the fragility of
> > the CP15 bit :-)
> 
> No, as explained above, we have considered a way of "detecting" whether
> the remapping occurred, or to unconditionally do the remapping. But
> none of those solutions work: we need to know, through some external
> mechanism, whether the remapping has already taken place or not.

OK, thank you for these precisions.

Best regards,
Willy



From sameo at linux.intel.com  Tue May 21 17:58:06 2013
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Tue, 21 May 2013 23:58:06 +0200
Subject: [GIT PULL v2] MFD: Fixes due for the v3.10 -rc:s
In-Reply-To: <20130521091230.GA28756@balto.lan>
References: <20130514091956.GG3297@gmail.com> <20130515090449.GA3494@gmail.com>
 <20130516224337.GZ22822@zurbaran>
 <20130517075140.GA25077@balto.lan> <20130521085650.GB4589@zurbaran>
 <20130521091230.GA28756@balto.lan>
Message-ID: <20130521215806.GC4566@zurbaran>

Hi Fabio,

On Tue, May 21, 2013 at 11:12:30AM +0200, Fabio Baltieri wrote:
> On Tue, May 21, 2013 at 10:56:50AM +0200, Samuel Ortiz wrote:
> > On Fri, May 17, 2013 at 09:51:40AM +0200, Fabio Baltieri wrote:
> > > Hello Samuel,
> > > 
> > > On Fri, May 17, 2013 at 12:43:37AM +0200, Samuel Ortiz wrote:
> > > > > Fabio Baltieri (5):
> > > > >       mfd: abx500-core: Fix sparse warning
> > > > >       mfd: ab8500-sysctrl: Fix sparse warning
> > > > >       mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> > > > >       mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> > > > Unless I'm missing something here, this one is not really rcN material, so
> > > > I'd appreciate if you could queue it to your for-mfd branch instead.
> > > 
> > > The last two:
> > > 
> > >   mfd: ab8500-sysctrl: Set sysctrl_dev during probe
> > This one is already in mfd-fixes, the commit log was clear enough.
> 
> Great!
> 
> > >   mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> > This one is not, as the commit log is not showing it actually fixes something
> > but only makes the code cleaner. If it really fixes something, could you
> > please provide me with a commit log that describes what exactly it fixes ?
> 
> Ok, the fix here is that right now that driver is initialized without a
> specific pdata (that is plat->sysctrl), so enforcing it breaks existing
> platforms for no reason.  To make the commit more clear I would just
> point that out as in (just last two sentences):
> 
> --- >8 ---
> mfd: ab8500-sysctrl: Let sysctrl driver work without pdata
> 
> A check for a valid plat->sysctrl was introduced in:
> 
> 2377e52 mfd: ab8500-sysctrl: Error check clean up
> 
> but the driver works just fine even without that initialization data,
> and enforcing it breaks existing platforms for no reason.
> 
> This patch removes the check and let the driver go ahead with probe.
> --- >8 ---
> 
> Is it better?
Slightly. Next time please describe how it breaks.
I applied and pushed this patch now, I'll send a pull request to Linus
tomorrow morning.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From dgilbert at interlog.com  Tue May 21 18:21:07 2013
From: dgilbert at interlog.com (Douglas Gilbert)
Date: Tue, 21 May 2013 18:21:07 -0400
Subject: [PATCH] v2 rtc-at91rm9200: add support for at91sam9x5
Message-ID: <519BF353.2060800@interlog.com>

An unspecified number of SoCs from the Atmel's
at91sam9x5 family including the at91sam9g25 have a
broken AT91_RTC_IMR (interrupt mask) register which
always returns zero.

If this bug can be neutralized, then the existing
rtc-at91rm9200 driver will work. On the other hand,
leaving this bug in place, and starting the RTC
causes unhandled interrupts which result in the
"SYS" interrupt being disabled. And that takes down
several other interrupts wired or-ed through the
SYS interrupt including the DBG port.

This is the second version of this patch, and is
against lk 3.10.0-rc2 .

ChangeLog:
    - checks in probe() function if AT91_RTC_IMR is broken.
      If so, uses a shadow imr
    - apart from that check, SoCs with a good IMR register
      take the same paths through rtc-at91rm9200.c as before
    - SoCs with a broken IMR take a spinlock while changing
      the state of IER or IDR (and the shadow), mainly to
      disable interrupts **.

** similar technique used in arch/arm/mach-at91/clock.c

Tested on an Aria G25 (at91sam9g25 based).

Signed-off-by: Douglas Gilbert <dgilbert at interlog.com>


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From jason at lakedaemon.net  Tue May 21 18:27:44 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 18:27:44 -0400
Subject: [PATCH] ARM: Kirkwood: TS219: Fix crash by double PCIe
 instantiation
In-Reply-To: <1369158108-5603-1-git-send-email-andrew@lunn.ch>
References: <1369158108-5603-1-git-send-email-andrew@lunn.ch>
Message-ID: <20130521222744.GX31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 07:41:48PM +0200, Andrew Lunn wrote:
> When creating the DT based boards-ts219.c the none DT ts219-setup.c
> was used as a template. This includes a lateinit() call to initialize
> the PCIe bus. The code makes use of machine_is_ts219() which is never
> true on DT, so a FIXME was added and the code left as is. This was
> unproblematic until b73690c8f8b5d: "ARM: Kirkwood: Support basic
> hotplug for PCI-E" which changes the way the PCIe bus is
> initialized. The non-DT ts219-setup.c now crashes during boot.  The
> lateinit() call in the DT boards-ts219.c is being called,
> machine_is_ts219() is true and so the PCIe is initialized a second
> time.
> 
> This patch removes the useless, and now clearly dangerous, code from
> boards-ts219.c, making ts219-setup.c work again.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> ---
> This can also be tagged for stable 3.9
> 
>  arch/arm/mach-kirkwood/board-ts219.c |   10 ----------
>  1 file changed, 10 deletions(-)

Applied to mvebu/fixes

thx,

Jason.


From jason at lakedaemon.net  Tue May 21 18:32:50 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 21 May 2013 18:32:50 -0400
Subject: [PATCH] arm: mvebu: enable two USB interfaces on the Armada XP
 GP board
In-Reply-To: <1369158789-3218-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369158789-3218-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130521223250.GY31290@titan.lakedaemon.net>

On Tue, May 21, 2013 at 07:53:09PM +0200, Thomas Petazzoni wrote:
> The Armada XP GP board has two USB slots: one on the front side and
> one on the back side. This commit enables the two USB host controllers
> that correspond to those wo USB slots.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-xp-gp.dts |   10 ++++++++++
>  1 file changed, 10 insertions(+)

Applied to mvebu/dt

thx,

Jason.


From elyas.r at gmail.com  Tue May 21 18:36:52 2013
From: elyas.r at gmail.com (Elyas Razzaghi)
Date: Wed, 22 May 2013 01:36:52 +0300
Subject: AT91SAM9260 I2C Driver
References: c88e466f0708070426i44ee92l3ed67fdefd9fa707@mail.gmail.com
Message-ID: <519BF704.40706@gmail.com>

Hello,

I have decided to use the PCA9665 I2C controller on my AT91RM9200 custom 
board. Could you help me with my board specific code to initialize the 
driver? How should I modify the code for PCA(I2C) part of my 
arch/arm/mach-at91/board-xxx.c file?

Best regards,
Elyas

On 2007-08-07 11:26, Michel Benoit wrote:
 > Hello Alex,
 >
 > I've cc'ed this email to the linux-arm-kernel list.
 >
 > > I too have decided to use the PCA9564 I2C controller, as the on-chip
 > > TWI controller was too buggy. I'm now trying to utilize the PCA9564
 > > driver included in 2.6.21, but am having some trouble figuring out how
 > > to use it. Would you mind answering a few questions for me?
 > >
 > > First off, I've included the PCA driver (not the ISA version) in my
 > > kernel using the menu configuration (not as a loadable module, but
 > > included it directly in the kernel), but I can't find anything in the
 > > running kernel that lets me know it has been included, except that the
 > > directory "/sys/bus/platform/drivers/pca9564" exists. I see nothing
 > > in the startup text stating that the driver is loaded and there is no
 > > entry in "/dev". Do you know what steps I need to take to load the
 > > driver?
 >
 > Have you included any board specific code to initialise the driver?
 >
 > Here is some code from my arch/arm/mach-at91rm9200/board-xxx.c file.
 >
 >
 > #if defined(CONFIG_I2C_PCA) || defined(CONFIG_I2C_PCA_MODULE)
 >
 > static struct at91_pca_data pca_data;
 >
 >
 >
 >
 > void __init at91_add_device_i2c_pca(struct at91_pca_data *data)
 > {
 >
 >
 >
 >
 >
 >
 >
 >
 >
 >
 >
 >
 > >
 > > Second, how do you physically connect the PCA9564 to your processor?
 > > Do you use GPIO, or is it placed on the data bus?
 >
 > The PCA9564 is on the system data bus with the irq and the reset pins
 > connected to gpio.
 >
 > I had to tweak the driver a little in order to use the GPIO reset pin
 > when the PCA detects an error condition on the bus.
 >
 >
 > > Thanks in advance for any help you can provide,
 > > Alex Parkinson
 > >
 > > On 5/30/07, Michel Benoit <murpme at gmail.com> wrote:
 > > > Hi Alex,
 > > >
 > > > Here is a copy of the driver that I wrote to test the 9260 i2c
 > > > interface. Its raw but it supports both master and slave mode. I did
 > > > not manage to get the twi hw to work in slave mode on the EK
 > > > development board so we chose to use an external PCA i2c controller
 > > > instead on our hw. I was told that the i2c (twi) controller is buggy
 > > > and cannot be trusted 100% of the time even in master mode.
 > > >
 > > > There are some folks that have been discussing an implementation of
 > > > interrupt based at91 i2c driver on the lm-sensors mailing list. I'm
 > > > not sure what the status of that drive ris but I know that 
someone was
 > > > trying to get the driver into mainline.
 > > >
 > > > Good luck!
 > > >
 > > >
 > > >
 > > >
 > > > On 5/29/07, Alex Parkinson <okalex at gmail.com> wrote:
 > > > > Michel,
 > > > >
 > > > > I've seen on a number of mailing lists that you've worked with 
the I2C
 > > > > driver for the SAM9260 quite a bit. I'm about to dive into the code
 > > > > now, and I just wanted to ask you if you ever managed to get it
 > > > > working. I saw on the lm-sensors mailing list that you modified the
 > > > > driver to be interrupt-based. Has your code made it into the 
mainline
 > > > > kernel? If not, would you mind sharing it with me?
 > > > >
 > > > > Sincerely,
 > > > > Alex Parkinson
 > > > >
 > > >
 > > >
 > >
 >
 >
 >


From rjw at sisk.pl  Tue May 21 19:45:46 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 22 May 2013 01:45:46 +0200
Subject: spurious bL cpufreq driver messages
In-Reply-To: <CAKohpomG5E2FAeZGnX3eBw8fOiX3K8sWEeHgb5NT_FT3y+Cg1w@mail.gmail.com>
References: <519686BC.3090101@gmail.com>
 <CAL_JsqLEv38DwnL4=ToXtEKNrDbgYv_0qiOc+cXZSjnfKVbeNg@mail.gmail.com>
 <CAKohpomG5E2FAeZGnX3eBw8fOiX3K8sWEeHgb5NT_FT3y+Cg1w@mail.gmail.com>
Message-ID: <11917612.jOVuLqOMKF@vostro.rjw.lan>

On Monday, May 20, 2013 10:06:49 AM Viresh Kumar wrote:
> On 19 May 2013 01:21, Rob Herring <robherring2 at gmail.com> wrote:
> > No, it still registers the bL driver. The problem is not that DT data
> > is missing, but it is present on a single cluster system.
> 
> I misread your mail.. I got the problem now.. Below should fix your
> issue (It is rebased on the patch I pointed to you earlier):
> 
> Attached too for testing as gmail copy-paste will break it.
> 
> @Rafael: Once Rob gives his Tested-by, please queue it for 3.10-rcs
> 
> ------------x-----------------x-----------------
> 
> From: Viresh Kumar <viresh.kumar at linaro.org>
> Date: Mon, 20 May 2013 09:57:17 +0530
> Subject: [PATCH] cpufreq: arm_big_little_dt: Instantiate as platform_driver
> 
> As multiplatform build is being adopted by more and more ARM platforms, initcall
> function should be used very carefully. For example, when both arm_big_little_dt
> and cpufreq-cpu0 drivers are compiled in, arm_big_little_dt driver may try to
> register even if we had platform device for cpufreq-cpu0 registered.
> 
> To eliminate this undesired the effect, the patch changes arm_big_little_dt
> driver to have it instantiated as a platform_driver. Then it will only run on
> platforms that create the platform_device "arm-bL-cpufreq-dt".
> 
> Reported-by: Rob Herring <robherring2 at gmail.com>
> Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>

The patch (from the attachment) didn't apply for me.  Please check the
bleeding-edge branch.

Thanks,
Rafael


> ---
>  drivers/cpufreq/arm_big_little_dt.c | 20 +++++++++++++++-----
>  1 file changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/cpufreq/arm_big_little_dt.c
> b/drivers/cpufreq/arm_big_little_dt.c
> index 27e2f45..fd9e3ea 100644
> --- a/drivers/cpufreq/arm_big_little_dt.c
> +++ b/drivers/cpufreq/arm_big_little_dt.c
> @@ -26,6 +26,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/opp.h>
> +#include <linux/platform_device.h>
>  #include <linux/slab.h>
>  #include <linux/types.h>
>  #include "arm_big_little.h"
> @@ -95,7 +96,7 @@ static struct cpufreq_arm_bL_ops dt_bL_ops = {
>  	.init_opp_table = dt_init_opp_table,
>  };
> 
> -static int generic_bL_init(void)
> +static int generic_bL_probe(struct platform_device *pdev)
>  {
>  	struct device_node *np;
> 
> @@ -106,13 +107,22 @@ static int generic_bL_init(void)
>  	of_node_put(np);
>  	return bL_cpufreq_register(&dt_bL_ops);
>  }
> -module_init(generic_bL_init);
> 
> -static void generic_bL_exit(void)
> +static int generic_bL_remove(struct platform_device *pdev)
>  {
> -	return bL_cpufreq_unregister(&dt_bL_ops);
> +	bL_cpufreq_unregister(&dt_bL_ops);
> +	return 0;
>  }
> -module_exit(generic_bL_exit);
> +
> +static struct platform_driver generic_bL_platdrv = {
> +	.driver = {
> +		.name	= "arm-bL-cpufreq-dt",
> +		.owner	= THIS_MODULE,
> +	},
> +	.probe		= generic_bL_probe,
> +	.remove		= generic_bL_remove,
> +};
> +module_platform_driver(generic_bL_platdrv);
> 
>  MODULE_AUTHOR("Viresh Kumar <viresh.kumar at linaro.org>");
>  MODULE_DESCRIPTION("Generic ARM big LITTLE cpufreq driver via DT");
-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From sfr at canb.auug.org.au  Tue May 21 20:04:47 2013
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Wed, 22 May 2013 10:04:47 +1000
Subject: [PATCH] Finally eradicate CONFIG_HOTPLUG
In-Reply-To: <20130521101349.30660.qmail@stuge.se>
References: <20130521134935.d18c3f5c23485fb5ddabc365@canb.auug.org.au>
 <20130521101349.30660.qmail@stuge.se>
Message-ID: <20130522100447.0f04799ea138a2f391d38850@canb.auug.org.au>

Hi Peter,

On Tue, 21 May 2013 12:13:49 +0200 Peter Stuge <peter at stuge.se> wrote:
>
> Are you changing the code to have HOTPLUG always -on- or -off- ?
> 
> From the commit message I had expected always -on-.

Yes, it has been that way for some time.

> Stephen Rothwell wrote:
> > --- a/include/asm-generic/vmlinux.lds.h
> > +++ b/include/asm-generic/vmlinux.lds.h
> > @@ -68,14 +68,6 @@
> >   * are handled as text/data or they can be discarded (which
> >   * often happens at runtime)
> >   */
> > -#ifdef CONFIG_HOTPLUG
> > -#define DEV_KEEP(sec)    *(.dev##sec)
> > -#define DEV_DISCARD(sec)
> > -#else
> > -#define DEV_KEEP(sec)
> > -#define DEV_DISCARD(sec) *(.dev##sec)
> > -#endif
> > -
> >  #ifdef CONFIG_HOTPLUG_CPU
> >  #define CPU_KEEP(sec)    *(.cpu##sec)
> >  #define CPU_DISCARD(sec)
> > @@ -182,8 +174,6 @@
> >  	*(.data)							\
> >  	*(.ref.data)							\
> >  	*(.data..shared_aligned) /* percpu related */			\
> > -	DEV_KEEP(init.data)						\
> > -	DEV_KEEP(exit.data)						\
> ..
> > @@ -503,7 +489,6 @@
> >  /* init and exit section handling */
> >  #define INIT_DATA							\
> >  	*(.init.data)							\
> > -	DEV_DISCARD(init.data)						\
> 
> Shouldn't the effect of one of the above remain?

As far as I can tell, all references to devinit and devexit have now been
removed from the kernel, so nothing will generate code in these sections
any more, so the linker script no longer needs to deal with them at all.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From linux at arm.linux.org.uk  Tue May 21 20:14:57 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 May 2013 01:14:57 +0100
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <20130522001457.GA18614@n2100.arm.linux.org.uk>

On Mon, May 20, 2013 at 09:06:19AM +0800, Wenyou Yang wrote:
> Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>

This needs more of a description.  Also, for a single patch, it's silly
to send two mails, the first being a cover which has a little more
information in it about the patch than the patch itself.

You need to explain _why_ you're making this change.  What I want to see
is that you've thought about the implications of this - particularly that
you know that strongly ordered memory does *not* imply any ordering with
any other memory types.

In other words, I want to know that this change is not a bodge but there's
a real reason behind it.


From gang.chen at asianux.com  Tue May 21 20:45:45 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Wed, 22 May 2013 08:45:45 +0800
Subject: [PATCH] arm64: compiling issue for allmodconfig,
 need "asm/parport.h" by "drivers/parport/parport_pc.c"
In-Reply-To: <20130521131734.GD27002@arm.com>
References: <5177551D.8090007@asianux.com> <20130424082237.GA23397@arm.com>
 <5177B1F0.10106@asianux.com>
 <20130424102327.GF21850@mudshark.cambridge.arm.com>
 <5177BAD0.9000500@asianux.com> <20130424110511.GK23397@arm.com>
 <5199A453.4080402@asianux.com> <20130521131734.GD27002@arm.com>
Message-ID: <519C1539.10908@asianux.com>

On 05/21/2013 09:17 PM, Catalin Marinas wrote:
> On Mon, May 20, 2013 at 05:19:31AM +0100, Chen Gang wrote:
>>
>> Need add the default file in 'asm/Kbuild' just like arm has done.
>>
>> The build command is:
>>   make EXTRA_CFLAGS=-W ARCH=arm64 allmodconfig
>>   make EXTRA_CFLAGS=-W ARCH=arm64 menuconfig
>>     set "aarch64-linux-gnu-" as cross compiling prefix.
>>   make EXTRA_CFLAGS=-W ARCH=arm64
>>
>> The related error:
>>   drivers/parport/parport_pc.c:67:25: fatal error: asm/parport.h: No such file or directory
> 
> As I don't see when we'd need this driver, you can probably change the
> Kconfig entry (similar to the VGA_CONSOLE one).
> 

Oh, really it is, it is for PC, it seems except x86, no one else will
use it. And for x86, it will be less and less used, in the future.

It seems it is a better candidate than VGA_CONSOLE. I will define
CONFIG_HAVE_PARPORT_PC for it.  :-)

Thanks.
-- 
Chen Gang

Asianux Corporation


From gang.chen at asianux.com  Tue May 21 20:50:32 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Wed, 22 May 2013 08:50:32 +0800
Subject: [PATCH] arm64: kernel: need extern variable 'screen_info' for
 related driver using.
In-Reply-To: <20130521131539.GC27002@arm.com>
References: <5199B7D6.40907@asianux.com>
 <20130520091008.GB31359@mudshark.cambridge.arm.com>
 <519AE6D7.1090401@asianux.com>
 <CAMuHMdWNHPDkf35MYMKnxt5pn3a+dsT4jgYxuuHrp+mpZMckfw@mail.gmail.com>
 <519B278B.6030708@asianux.com>
 <20130521090336.GC10453@mudshark.cambridge.arm.com>
 <519B48B4.6050607@asianux.com> <20130521131539.GC27002@arm.com>
Message-ID: <519C1658.3040209@asianux.com>

On 05/21/2013 09:15 PM, Catalin Marinas wrote:
> On Tue, May 21, 2013 at 11:13:08AM +0100, Chen Gang wrote:
>> > On 05/21/2013 05:03 PM, Will Deacon wrote:
>>> > > On Tue, May 21, 2013 at 08:51:39AM +0100, Chen Gang wrote:
>>>> > >> For me, I still recommend add 'ARM64' in the long list of architectures
>>>> > >> for 'VGA_CONSOLE', I have 3 reasons, please check:
>>>> > >>
>>>> > >> a. current implementation only changes one area which only related with
>>>> > >> arm64 and 'VGA_CONSOLE', but if use 'CONFIG_HAVE_VGA_CONSOLE', that will
>>>> > >> touch many multiple platforms dependency, at least we need discuss about
>>>> > >> it with multiple platforms guys for it, firstly.
>>> > > 
>>> > > That's a weak argument. You might as well propose the cleanup and see what
>>> > > people say.
>> > 
>> > Hmm.. I think at least, we need discuss it with the 'final applier'
>> > firstly (and now, I even do not know who is the 'final applier').
> Well, you can post the patch to linux-arch, cc'ing the arch maintainers
> whose Kconfig files you touch. If there are no comments, it will most
> likely be picked by Andrew Morton and sent to Linus (make sure you cc
> Andrew as well).

OK, thanks. I will do with PARPORT_PC firstly, I think, it is a better
candidate than VGA_CONSOLE.

And excuse me, I have to do another things now, and I think I should
finish the PARPORT_PC within this week.


Thanks.
-- 
Chen Gang

Asianux Corporation


From viresh.kumar at linaro.org  Tue May 21 21:14:20 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Wed, 22 May 2013 06:44:20 +0530
Subject: spurious bL cpufreq driver messages
In-Reply-To: <11917612.jOVuLqOMKF@vostro.rjw.lan>
References: <519686BC.3090101@gmail.com>
 <CAL_JsqLEv38DwnL4=ToXtEKNrDbgYv_0qiOc+cXZSjnfKVbeNg@mail.gmail.com>
 <CAKohpomG5E2FAeZGnX3eBw8fOiX3K8sWEeHgb5NT_FT3y+Cg1w@mail.gmail.com>
 <11917612.jOVuLqOMKF@vostro.rjw.lan>
Message-ID: <CAKohpokkMvEhotcow8qfCGP0SxNfRsxw7swo-ZFbTSKE-F8Xtw@mail.gmail.com>

On 22 May 2013 05:15, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> On Monday, May 20, 2013 10:06:49 AM Viresh Kumar wrote:
>> On 19 May 2013 01:21, Rob Herring <robherring2 at gmail.com> wrote:
>> > No, it still registers the bL driver. The problem is not that DT data
>> > is missing, but it is present on a single cluster system.
>>
>> I misread your mail.. I got the problem now.. Below should fix your
>> issue (It is rebased on the patch I pointed to you earlier):
>>
>> Attached too for testing as gmail copy-paste will break it.
>>
>> @Rafael: Once Rob gives his Tested-by, please queue it for 3.10-rcs
>>
>> ------------x-----------------x-----------------
>>
>> From: Viresh Kumar <viresh.kumar at linaro.org>
>> Date: Mon, 20 May 2013 09:57:17 +0530
>> Subject: [PATCH] cpufreq: arm_big_little_dt: Instantiate as platform_driver
>>
>> As multiplatform build is being adopted by more and more ARM platforms, initcall
>> function should be used very carefully. For example, when both arm_big_little_dt
>> and cpufreq-cpu0 drivers are compiled in, arm_big_little_dt driver may try to
>> register even if we had platform device for cpufreq-cpu0 registered.
>>
>> To eliminate this undesired the effect, the patch changes arm_big_little_dt
>> driver to have it instantiated as a platform_driver. Then it will only run on
>> platforms that create the platform_device "arm-bL-cpufreq-dt".
>>
>> Reported-by: Rob Herring <robherring2 at gmail.com>
>> Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>
>
> The patch (from the attachment) didn't apply for me.  Please check the
> bleeding-edge branch.

Have you tried applying this before it (As written in my last mail)?

https://groups.google.com/forum/?fromgroups#!topic/linux.kernel/XJF-82rad4o

Above is also required fix for 3.10-rc3


From guz.fnst at cn.fujitsu.com  Tue May 21 21:30:11 2013
From: guz.fnst at cn.fujitsu.com (Gu Zheng)
Date: Wed, 22 May 2013 09:30:11 +0800
Subject: [PATCH 00/19] driver:usb&net: add missing platform_driver owner
In-Reply-To: <519B418A.7060805@huawei.com>
References: <1369104120-35552-1-git-send-email-libo.chen@huawei.com>
 <20130520.232619.964940909999914694.davem@davemloft.net>
 <20130521084108.1a585f32@skate> <519B2993.4090409@cn.fujitsu.com>
 <20130521110616.21eee053@skate> <519B418A.7060805@huawei.com>
Message-ID: <519C1FA3.2020500@cn.fujitsu.com>

On 05/21/2013 05:42 PM, Libo Chen wrote:

> On 2013/5/21 17:06, Thomas Petazzoni wrote:
>> Dear Gu Zheng,
>>
>> On Tue, 21 May 2013 16:00:19 +0800, Gu Zheng wrote:
>>
>>>> Or, maybe make the existing module_platform_driver() macro do this?
>>>
>>> But not all the modules use module_platform_driver() macro to replace the module init/exit.
>>
>> Then maybe it's a good opportunity to convert those ones to use
>> module_platform_driver() ?
>>
>> Thomas
>>
> 
>  In my opinion, not all modules can use module_platform_driver() macro to replace the module init/exit easily, like us3mc_init.
> 
>  Furthermore this work will touch various platforms and architectures, I am worried it is hard to *test* (compile and boot).

Agree. I stick to the way that David mentioned.

Thanks,
Gu

> 
>  What do you think?
> 
> 




From swarren at wwwdotorg.org  Tue May 21 21:43:39 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 May 2013 19:43:39 -0600
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
In-Reply-To: <519BA209.6050407@wwwdotorg.org>
References: <519AD82A.6090809@wwwdotorg.org>
 <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
 <519BA209.6050407@wwwdotorg.org>
Message-ID: <519C22CB.5040009@wwwdotorg.org>

On 05/21/2013 10:34 AM, Stephen Warren wrote:
> On 05/21/2013 12:02 AM, Jongsung Kim wrote:
>> Stephen Warren reported the recent commit 78506f2 (add support for
>> extended FIFO-size of PL011-r1p5) breaks the serial port on the
>> BCM2835 ARM SoC.
>>
>> A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
>> The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
>> FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
>> this compatibility issue, this patch overrides the HW UART periphid
>> register values with the actually compatible UART periphid 0x00241011
>> (r1p3 or r1p4).
>>
>> Reported-by: Stephen Warren <swarren at wwwdotorg.org>
>> Signed-off-by: Jongsung Kim <neidhard.kim at lge.com>
> 
> I know this will work, because I tried out the same thing last week.
> 
> However, I'm not convinced that it's the correct approach. What other
> changes exist between r1p4 and r1p5; can you check in the TRM?

Looking at the TRM, it seems this is really the only change, according
to the changelog in the documentation (although it's a little difficult
to tell since the document seems to have a bunch of changes that
presumably don't affect behaviour). So, faking the periphid seems OK.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>

Let's apply for 3.10.


From neidhard.kim at lge.com  Tue May 21 21:52:22 2013
From: neidhard.kim at lge.com (Jongsung Kim)
Date: Wed, 22 May 2013 10:52:22 +0900
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
In-Reply-To: <519C22CB.5040009@wwwdotorg.org>
References: <519AD82A.6090809@wwwdotorg.org>
 <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
 <519BA209.6050407@wwwdotorg.org> <519C22CB.5040009@wwwdotorg.org>
Message-ID: <013101ce568f$002d6490$00882db0$@lge.com>

Stephen Warren <swarren at wwwdotorg.org> :
> Looking at the TRM, it seems this is really the only change, according
> to the changelog in the documentation (although it's a little difficult
> to tell since the document seems to have a bunch of changes that
presumably
> don't affect behaviour). So, faking the periphid seems OK.
>
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>
>
> Let's apply for 3.10.

Thank you, Stephen.




From axel.lin at ingics.com  Tue May 21 22:23:16 2013
From: axel.lin at ingics.com (Axel Lin)
Date: Wed, 22 May 2013 10:23:16 +0800
Subject: [RESEND][PATCH 1/2] clk: wm831x: Fix update wrong register for
 enable/disable FLL
Message-ID: <1369189396.19416.0.camel@phoenix>

According to the datasheet, FLL Enable is controlled by
R16530 (4092h) FLL Control1
        BIT 0: FLL Enable
                0 = Disable
                1 = Enable

Thus the code should update WM831X_FLL_CONTROL_1 register rather than
WM831X_FLL_CONTROL_2 register.

Also fixes a trivial typo in dev_crit message.

Signed-off-by: Axel Lin <axel.lin at ingics.com>
Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
Hi Mike,
This patch serial was sent on http://lkml.org/lkml/2013/5/1/152
With Mark's Ack.

Regards,
Axel
 drivers/clk/clk-wm831x.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 16ed068..4bdf0b0 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -97,7 +97,7 @@ static int wm831x_fll_prepare(struct clk_hw *hw)
 	struct wm831x *wm831x = clkdata->wm831x;
 	int ret;
 
-	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
 			      WM831X_FLL_ENA, WM831X_FLL_ENA);
 	if (ret != 0)
 		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
@@ -114,9 +114,9 @@ static void wm831x_fll_unprepare(struct clk_hw *hw)
 	struct wm831x *wm831x = clkdata->wm831x;
 	int ret;
 
-	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
 	if (ret != 0)
-		dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
+		dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
 }
 
 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
-- 
1.8.1.2





From axel.lin at ingics.com  Tue May 21 22:24:16 2013
From: axel.lin at ingics.com (Axel Lin)
Date: Wed, 22 May 2013 10:24:16 +0800
Subject: [RESEND][PATCH 2/2] clk: wm831x: Fix wm831x_clkout_get_parent
In-Reply-To: <1369189396.19416.0.camel@phoenix>
References: <1369189396.19416.0.camel@phoenix>
Message-ID: <1369189456.19416.1.camel@phoenix>

Current code looks strange because calling wm831x_clkout_set_parent() with 0 as
parent parameter, wm831x_clkout_get_parent() will return 1.

According to the datasheet:
R16528 (4090h) Clock Control1
        BIT 0: CLKOUT output source select
                0 = FLL output
                1 = 32.768kHz oscillator

Thus fix the entry order in wm831x_clkout_parents[] to make it has
the same meaning as the datasheet and make the return value
of wm831x_clkout_get_parent() consistent with the parent pass to
wm831x_clkout_set_parent().

Signed-off-by: Axel Lin <axel.lin at ingics.com>
Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/clk/clk-wm831x.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 4bdf0b0..58d08a6 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -299,8 +299,8 @@ static void wm831x_clkout_unprepare(struct clk_hw *hw)
 }
 
 static const char *wm831x_clkout_parents[] = {
-	"xtal",
 	"fll",
+	"xtal",
 };
 
 static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
@@ -318,9 +318,9 @@ static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
 	}
 
 	if (ret & WM831X_CLKOUT_SRC)
-		return 0;
-	else
 		return 1;
+	else
+		return 0;
 }
 
 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
-- 
1.8.1.2





From dhobsong at igel.co.jp  Tue May 21 22:37:17 2013
From: dhobsong at igel.co.jp (Damian Hobson-Garcia)
Date: Wed, 22 May 2013 11:37:17 +0900
Subject: [PATCH v2 0/4] dma-mapping: Define dma_{alloc,free}_attrs() for
 all archs
In-Reply-To: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
References: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
Message-ID: <519C2F5D.8000809@igel.co.jp>

Hello,
On 2013/04/30 12:01, Damian Hobson-Garcia wrote:
> Most architectures that define CONFIG_HAVE_DMA=y, have implementations for
> both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
> not define CONFIG_HAVE_DMA also have both of these definitions provided by
> dma-mapping-broken.h.
> 
> Provide a default definition for the archs that define CONFIG_HAVE_DMA=y,
> but have no implementation for dma_{alloc,free}_attrs(). 
> 
> As I don't have hardware for any of these systems, the patches are only
> compile-tested where I could (arm64, s390) and untested for the archs
> where I couldn't find a readily available prebuilt cross-compiler (c6x, parisc).
> 


>  arch/arm64/include/asm/dma-mapping.h  |   17 +++++++++++------
>  arch/c6x/include/asm/dma-mapping.h    |    3 +++
>  arch/parisc/include/asm/dma-mapping.h |    3 +++
>  arch/s390/include/asm/dma-mapping.h   |   17 +++++++++++------
>  4 files changed, 28 insertions(+), 12 deletions(-)
> 

Since this series spans several architectures, what would be the best
way to have this patch series merged?
Should I resubmit each patch to the mailing list for each architecture
separately?

Thank you,
Damian

-- 
Damian Hobson-Garcia
IGEL Co.,Ltd
http://www.igel.co.jp


From shawn.guo at linaro.org  Tue May 21 23:24:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 May 2013 11:24:05 +0800
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CBBA4@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <20130520033207.GD25113@S2101-09.ap.freescale.net>
 <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>
 <B56CDBE15CE27145A4B77D2D24263E851CBBA4@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <CAAQ0ZWTBZ=10B+0Zc4iZmvrr0hzdBKf1mn1CzhJokWE44dxsoA@mail.gmail.com>

On 21 May 2013 15:56, Lu Jingchang-B35083 <B35083 at freescale.com> wrote:
> [Lu Jingchang-B35083]
> I see you have Acked [PATCH v3 2/2] pinctrl: imx: add MVF600 support to imx pinctrl framework, do I need resend it as the first one. Thanks!
>

Since LinusW hasn't applied it, you should just resend.

Shawn


From dianders at chromium.org  Wed May 22 00:46:35 2013
From: dianders at chromium.org (Doug Anderson)
Date: Tue, 21 May 2013 21:46:35 -0700
Subject: [PATCH v2 6/6] pinctrl: exynos: Handle suspend/resume of GPIO
 EINT registers
In-Reply-To: <4536937.hnhaYZLnaG@amdc1227>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <18754346.1REWN52J0K@flatron>
 <CAD=FV=XiWET3Xptfk2CVWMw=xVCE4zUJhJtgXHbhiND12rJGnQ@mail.gmail.com>
 <4536937.hnhaYZLnaG@amdc1227>
Message-ID: <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>

Tomasz,

On Tue, May 21, 2013 at 10:05 AM, Tomasz Figa <t.figa at samsung.com> wrote:
>         return 0;
> +
> +err_domains:
> +       bank = d->ctrl->pin_banks;
> +       for (undo = 0; undo < i; ++undo) {

++bank is missing, I think.  This will free the same bank many times.

optional: could also avoid extra 'undo' variable and remove in reverse
order by changing i to signed and counting down to 0.

-Doug


From 21cnbao at gmail.com  Wed May 22 01:15:26 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 22 May 2013 13:15:26 +0800
Subject: [PATCH v4] ASoC: dfbmcs320: make the driver common for other BT
 modules
In-Reply-To: <20130521181849.GG1627@sirena.org.uk>
References: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>
 <20130521181849.GG1627@sirena.org.uk>
Message-ID: <CAGsJ_4x3QrvReOnFQFqRMWfUf-v-Js4+L_Vr8jht_wR-ApQJrg@mail.gmail.com>

2013/5/22 Mark Brown <broonie at kernel.org>:
> On Sat, May 18, 2013 at 08:25:00PM +0800, Barry Song wrote:
>> DFBM-CS320 is only one of bluetooth modules using CSR bluetooth chips,
>> we don't want everyone to have a seperate codec driver. anyway, the
>> feature of Bluetooth SCO is same on all platforms, so this patch
>> makes the DFBM-CS320 driver become a common BT SCO link driver.
>
> Applied, thanks.

thanks, Mark. can we also do something in omap-hdmi to make the HDMI
codec common as well?
i think it is in the same situation with BT SCO:
http://comments.gmane.org/gmane.linux.alsa.devel/108234

-barry


From hdoyu at nvidia.com  Wed May 22 02:12:48 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 May 2013 09:12:48 +0300
Subject: [v2 0/6] CLK: tegra: convert device tree files to use CLK defines
In-Reply-To: <519B9B5D.4050402@wwwdotorg.org>
References: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com>
 <519B9B5D.4050402@wwwdotorg.org>
Message-ID: <20130522091248.b3acd9c56ab66535d75b8fd1@nvidia.com>

On Tue, 21 May 2013 18:05:49 +0200
Stephen Warren <swarren at wwwdotorg.org> wrote:

> On 05/21/2013 03:10 AM, Hiroshi Doyu wrote:
> > This patchset converts device tree files to use CLK defines. This
> > version was updated along with the latest DT changes.
> > 
> > The following changes since commit 7479d8bb5650f43053d0e82fa44db668cf968f11:
> > 
> >   TESTING: Build Tegra USB as a module (2013-05-20 13:11:19 -0600)
> 
> That commit is in my personal work-in-progress branch. This series
> should be based on Tegra's for-3.11/dt branch. This will make a
> difference (at least) in patch 6/6, where you've edited some DT nodes
> that don't yet exist upstream (i.e. Tegra's for-3.11/dt branch) and
> hence this series won't apply there.

I'll rebase.

> I assume you're planning to send a series for 3.11 that converts
> drivers/clk/tegra/ to use these new header files?

I think that I'll work on SMMU first, which diverted from the
downstream now. So the above may come a bit later.


From shc_work at mail.ru  Wed May 22 02:19:12 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Wed, 22 May 2013 10:19:12 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSF0gQVJNOiBpb211eC1teDUxOiBBbHdheXMgZGVmaW5lIFBV?=
 =?UTF-8?B?RSBmb3IgcGlucyB1c2VkIGFzIEdQSU8=?=
In-Reply-To: <20130521192430.GU32299@pengutronix.de>
References: <1369124845-19244-1-git-send-email-shc_work@mail.ru>
 <20130521192430.GU32299@pengutronix.de>
Message-ID: <1369203552.559574351@f389.i.mail.ru>

> On Tue, May 21, 2013 at 12:27:25PM +0400, Alexander Shiyan wrote:
> > This patch adds a PUE bit for pins which used as GPIO. This allow
> > to use the GPIOs correctly as inputs when source is open-drain with
> > external pullup resistor (IRQ open-drain outputs for example).
> 
> I don't understand. If there's an external pullup why do you want to
> turn on the internal one?

It is just switch off keeper circuit.

Some pads not have internal pullup, probably this is affected only for such pins.
This is example of this issue:
Used pad MX51_PAD_DISPB2_SER_CLK__GPIO3_7, (GPIO3.7 = 71).
External pullup resistor is used.

gpio_direction output 71 1
gpio_direction_input 71
gpio_get_value 71; echo $?
1
gpio_direction output 71 0
gpio_direction_input 71
gpio_get_value 71; echo $?
0

So, we cannot get "1" here anymore if only pullup is used for this pad. The pad is keep last logic state...
The second solution for this is disable PKE, i am not sure which solution is the best...

> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > ---
> >  arch/arm/mach-imx/iomux-mx51.h | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
> > index 75bbcc4..7dc187c 100644
> > --- a/arch/arm/mach-imx/iomux-mx51.h
> > +++ b/arch/arm/mach-imx/iomux-mx51.h
> > @@ -34,7 +34,8 @@
> >  #define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
> >  				PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
> >  				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
> > -#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
> > +#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
> > +				PAD_CTL_PUE | PAD_CTL_SRE_FAST)
> >  
> >  #define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
> >  #define MX51_PAD_CTRL_3		(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
> > -- 

---

From nvmarkzhang at gmail.com  Wed May 22 02:24:43 2013
From: nvmarkzhang at gmail.com (Mark Zhang)
Date: Wed, 22 May 2013 14:24:43 +0800
Subject: Naming convention DSI + device tree
In-Reply-To: <5195C1E2.4020009@nvidia.com>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org> <20130516071537.GA13573@mail.o2s.ch>
 <519522C1.5010107@wwwdotorg.org> <5195C1E2.4020009@nvidia.com>
Message-ID: <519C64AB.2090708@gmail.com>

Cool. Alex, do you know any updates on DSI part of CDF? I recall few
months ago, Laurent wrote mail to share some infos about the CDF
discussions, and it mentioned that the DSI will be considered in next
version of CDF... you know, for t114, the DSI support is a must.

Mark
On 05/17/2013 01:36 PM, Alex Courbot wrote:
> On 05/17/2013 03:17 AM, Stephen Warren wrote:
>>> Is this upcoming CDF included within your "linux-next_common"
>>> branch?
>>
>> No. That branch of mine is basd on linux-next, so whatever is in
>> linux-next is in my branch, and I certainly haven't applied the CDF
>> locally.
>>
>> I believe the CDF has been posted to various mailing lists a few
>> times, but it isn't checked in yet since there isn't a final version.
>> I CC'd Alex; he might know the status better than me.
> 
> Current version is RFC v2 - I know Laurent is working on a v3, but it is
> taking some time. It will probably differ considerably from v2, so be
> warned if you use it.
> 
> Still, if you want to play around with the CDF, you can have a look at
> the tegra-cdf branch of my github repo:
> https://github.com/Gnurou/linux/commits/tegra-cdf
> 
> It was kind of old so I rebased it on top of 3.10rc1. It includes the
> CDF v2 patch, adds CDF support to the tegra-drm driver, and also
> implements a driver for the Tegra 2-based Ventana panel. It's pretty
> straightforward to read so I guess you can use that as a guide.
> 
> I checked whether the rebase worked and it does - you just need to
> enable host1x/tegradrm support on top of the default settings (Stephen,
> why aren't these enabled by default?)
> 
> So long story short, CDF works well and is small enough to be easy to
> maintain out-of-tree. A proper panel framework is desperately needed in
> the kernel, so I hope it will move forward soon.
> 
> Hope this helps,
> Alex.
> 
> -- 
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From R64188 at freescale.com  Wed May 22 02:40:21 2013
From: R64188 at freescale.com (Jin Zhengxiong-R64188)
Date: Wed, 22 May 2013 06:40:21 +0000
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <20130520030523.GB25113@S2101-09.ap.freescale.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
Message-ID: <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>

> -----Original Message-----
> From: Shawn Guo [mailto:shawn.guo at linaro.org]
> Sent: Monday, May 20, 2013 11:05 AM
> To: Lu Jingchang-B35083
> Cc: linux-serial at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> gregkh at linuxfoundation.org; s.hauer at pengutronix.de
> Subject: Re: [PATCH v3] tty: serial: add Freescale lpuart driver support
> 
> On Thu, May 16, 2013 at 02:18:15PM +0800, Jingchang Lu wrote:
> > Add Freescale lpuart driver support. The lpuart device can be founded
> > on Vybrid MVF600 and Layerscape LS-1 SoCs.
> >
> > Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> > ---
> > v3:
> >   change the uart driver name from mvf to lpuart for further share
> between SoCs.
> 
> I do not think it's going to be a problem to name the IP with mvf family
> name even though it will be used on LS-1 too.  That can simply telling
> the history that the IP is firstly used on mvf family and then get reused
> on LS-1.  But I'm fine you name the driver in a generic way, purely using
> the IP name, if you feel like to do that strongly ...
> 
[Jason Jin-R64188] Reuse the same LPUART on LS-1 with the compatible strings 'fsl,mvf600-lpuart' is technically OK, But it will fuss the route map of the product Line. The general name can show that the IP is shared between several product lines, and the history for which SOC firstly used the IP is not very important. With general compatible name, We can setup the general dts for the shared IPs.

That's also the case for the IPs used on Power platform, Take the IFC for example, this IP implemented on Power platform will also be reused LS-1, The compatible string is set as  "fsl,ifc", "simple-bus" but not the soc name on which the IP first used.

 Another example, though a little different, the nor flash driver, which is used for many platform, the compatible "cfi-flash" will be more reasonable than the soc/board name.

With the general name for the compatible string in the driver, if there is minor difference for the different implementation of the same IP, we can add the soc related compatible string to the driver to pass different .data structure for that soc.  

Jason





From horms+renesas at verge.net.au  Wed May 22 02:48:10 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 15:48:10 +0900
Subject: [PATCH] ARM: shmobile: marzen: Use error values in usb_power_*
In-Reply-To: <1369205290-6272-1-git-send-email-horms+renesas@verge.net.au>
References: <1369205290-6272-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369205290-6272-2-git-send-email-horms+renesas@verge.net.au>

This patch updates the marzen board code as if USB PHY isn't enabled
they phy will have a value set by ERR_PTR() rather than be NULL.

Without this patch a NULL pointer dereference  and kernel panic
occurs on initialisation of USB on marzen.

This resolves a regression introduced in 3.10-rc1 by
b7fa5c2aec5be083eb2719b405089703608e9bc6
("usb: phy: return -ENXIO when PHY layer isn't enabled").

Tested-by: Nguyen Hong Ky <nh-ky at jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 9105285..b9594e9 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -212,8 +212,8 @@ static struct platform_device *marzen_devices[] __initdata = {
 static struct usb_phy *phy;
 static int usb_power_on(struct platform_device *pdev)
 {
-	if (!phy)
-		return -EIO;
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
 
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_get_sync(&pdev->dev);
@@ -225,7 +225,7 @@ static int usb_power_on(struct platform_device *pdev)
 
 static void usb_power_off(struct platform_device *pdev)
 {
-	if (!phy)
+	if (IS_ERR(phy))
 		return;
 
 	usb_phy_shutdown(phy);
-- 
1.8.2.1



From horms+renesas at verge.net.au  Wed May 22 02:48:09 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 15:48:09 +0900
Subject: [GIT PULL] Renesas ARM SoC based marzen board fix for v3.10
Message-ID: <1369205290-6272-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

please consider the following fix for v3.10.
It resolves a boot-failure regression on the marzen board.

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-boards-marzen-fixes-for-v3.10

for you to fetch changes up to 5f10428e4a6d99cc019270c51ad5a33fb38addeb:

  ARM: shmobile: marzen: Use error values in usb_power_* (2013-05-22 15:43:16 +0900)

----------------------------------------------------------------
Correct USB PHY initialisation on the marzen board.

----------------------------------------------------------------
Simon Horman (1):
      ARM: shmobile: marzen: Use error values in usb_power_*

 arch/arm/mach-shmobile/board-marzen.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)


From B45370 at freescale.com  Wed May 22 02:54:17 2013
From: B45370 at freescale.com (Sharma Bhupesh-B45370)
Date: Wed, 22 May 2013 06:54:17 +0000
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
Message-ID: <A1A6EA40F8503D48BB002B42BD65974E2AC5CF@039-SN2MPN1-013.039d.mgd.msft.net>

> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Jin Zhengxiong-R64188
> Sent: Wednesday, May 22, 2013 12:10 PM
> To: Shawn Guo; Lu Jingchang-B35083
> Cc: gregkh at linuxfoundation.org; s.hauer at pengutronix.de; linux-arm-
> kernel at lists.infradead.org; linux-serial at vger.kernel.org
> Subject: RE: [PATCH v3] tty: serial: add Freescale lpuart driver support
> 
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawn.guo at linaro.org]
> > Sent: Monday, May 20, 2013 11:05 AM
> > To: Lu Jingchang-B35083
> > Cc: linux-serial at vger.kernel.org;
> > linux-arm-kernel at lists.infradead.org;
> > gregkh at linuxfoundation.org; s.hauer at pengutronix.de
> > Subject: Re: [PATCH v3] tty: serial: add Freescale lpuart driver
> > support
> >
> > On Thu, May 16, 2013 at 02:18:15PM +0800, Jingchang Lu wrote:
> > > Add Freescale lpuart driver support. The lpuart device can be
> > > founded on Vybrid MVF600 and Layerscape LS-1 SoCs.
> > >
> > > Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> > > ---
> > > v3:
> > >   change the uart driver name from mvf to lpuart for further share
> > between SoCs.
> >
> > I do not think it's going to be a problem to name the IP with mvf
> > family name even though it will be used on LS-1 too.  That can simply
> > telling the history that the IP is firstly used on mvf family and then
> > get reused on LS-1.  But I'm fine you name the driver in a generic
> > way, purely using the IP name, if you feel like to do that strongly ...
> >
> [Jason Jin-R64188] Reuse the same LPUART on LS-1 with the compatible
> strings 'fsl,mvf600-lpuart' is technically OK, But it will fuss the route
> map of the product Line. The general name can show that the IP is shared
> between several product lines, and the history for which SOC firstly used
> the IP is not very important. With general compatible name, We can setup
> the general dts for the shared IPs.
> 
> That's also the case for the IPs used on Power platform, Take the IFC for
> example, this IP implemented on Power platform will also be reused LS-1,
> The compatible string is set as  "fsl,ifc", "simple-bus" but not the soc
> name on which the IP first used.
> 
>  Another example, though a little different, the nor flash driver, which
> is used for many platform, the compatible "cfi-flash" will be more
> reasonable than the soc/board name.
> 
> With the general name for the compatible string in the driver, if there
> is minor difference for the different implementation of the same IP, we
> can add the soc related compatible string to the driver to pass different
> .data structure for that soc.
> 
> Jason
> 

It's better to use the generic name lpuart in the compatible string as it provides
much closer association with the lpuart driver which can be generic across SoCs.

As Jason pointed out, minor differences in IP implementation across SoCs can be
handled by passing the soc related compatible string.

Regards,
Bhupesh




From jonas at microbit.se  Wed May 22 02:52:45 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Wed, 22 May 2013 08:52:45 +0200
Subject: imx53 cspi clock problem
Message-ID: <519C6B3D.3030106@microbit.se>

Hi,

i have found a problem when using the cspi port in a imx53 soc. I am 
using kernel 3.10-rc2. This is the dts defenition:

cspi: cspi at 63fc0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
	reg = <0x63fc0000 0x4000>;
	interrupts = <38>;
	clocks = <&clks 55>, <&clks 0>;
	clock-names = "ipg", "per";
	status = "disabled";
};

then in the driver spi-imx.c:

spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);

clk_get_rate() will return the rate 0. In function mx31_config, this line:

reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
	MX31_CSPICTRL_DR_SHIFT;

will always configure the port for full speed (16.7 MHz in my system).

This "per" clock rate should be around 67MHz.

Jonas


From LW at KARO-electronics.de  Wed May 22 03:02:56 2013
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Wed, 22 May 2013 09:02:56 +0200
Subject: [PATCH] ARM: iomux-mx51: Always define PU
 E for pins used as GPIO
In-Reply-To: <1369203552.559574351@f389.i.mail.ru>
References: <1369124845-19244-1-git-send-email-shc_work@mail.ru>
 <20130521192430.GU32299@pengutronix.de>
 <1369203552.559574351@f389.i.mail.ru>
Message-ID: <20892.28064.82907.942799@ipc1.ka-ro>

Hi,

Alexander Shiyan writes:
> > On Tue, May 21, 2013 at 12:27:25PM +0400, Alexander Shiyan wrote:
> > > This patch adds a PUE bit for pins which used as GPIO. This allow
> > > to use the GPIOs correctly as inputs when source is open-drain with
> > > external pullup resistor (IRQ open-drain outputs for example).
> > 
> > I don't understand. If there's an external pullup why do you want to
> > turn on the internal one?
> 
> It is just switch off keeper circuit.
> 
If you want to switch the keeper circuit off why don't you do that by
removing PAD_CTL_PKE rather than adding PAD_CTL_PUE?


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From avinashphilip at ti.com  Wed May 22 03:10:24 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:24 +0530
Subject: [PATCH 01/11] ARM: davinci: GPIO: Add platform data structure
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-2-git-send-email-avinashphilip@ti.com>

From: KV Sujith <sujithkv at ti.com>

Add struct davinci_gpio_platform_data davinci gpio module.

Signed-off-by: KV Sujith <sujithkv at ti.com>
Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 include/linux/platform_data/gpio-davinci.h |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 include/linux/platform_data/gpio-davinci.h

diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h
new file mode 100644
index 0000000..f1c8277
--- /dev/null
+++ b/include/linux/platform_data/gpio-davinci.h
@@ -0,0 +1,27 @@
+/*
+ * gpio-davinci.h
+ *
+ * DaVinci GPIO Platform Related Defines
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_DAVINCI_GPIO_H
+#define __ASM_ARCH_DAVINCI_GPIO_H
+
+struct davinci_gpio_platform_data {
+	u32	ngpio;
+	u32	gpio_unbanked;
+	u32	intc_irq_num;
+};
+
+#endif
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:23 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:23 +0530
Subject: [PATCH 00/11] Convert GPIO Davinci to platform driver
Message-ID: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>

GPIO Davinci driver converted to platform driver to support DT booting.
In this patch series
- Cleaned gpio Davinci driver code with proper commenting style and appropriate
  variable names.
- Create platform driver for GPIO Davinci in da8xx and dm* platforms and removed
  gpio related member updation in davinci_soc_info structure.
- DT support added for da850 board and tested on da850 EVM.
- Remove soc_info reference in the gpio davinci driver and start uses
  gpiolib interface.

This sereise based on [1] and is avilable at [2].
1. http://gitorious.org/linux-davinci/linux-davinci/trees/davinci-for-v3.10/soc
2. https://github.com/avinashphilip/am335x_linux/commits/linux_davinci_v3.10_soc_gpio

KV Sujith (6):
  ARM: davinci: GPIO: Add platform data structure
  gpio: davinci: Modify to platform driver
  ARM: davinci: da8xx: creation of gpio platform device
  gpio: davinci: DT changes for driver
  ARM: davinci: da850: add GPIO DT entries
  ARM: davinci: da850 evm: add GPIO DT data

Philip Avinash (5):
  gpio: davinci: coding style correction
  ARM: davinci: creation of gpio platform device for dm platforms
  ARM: davinci: da8xx: gpio device creation
  ARM: davinci: create davinci gpio device for dm platforms
  ARM: davinci: start using gpiolib support

 .../devicetree/bindings/gpio/gpio-davinci.txt      |   26 ++
 arch/arm/Kconfig                                   |    1 -
 arch/arm/boot/dts/da850-evm.dts                    |   19 ++
 arch/arm/boot/dts/da850.dtsi                       |    9 +
 arch/arm/mach-davinci/board-da830-evm.c            |   19 +-
 arch/arm/mach-davinci/board-da850-evm.c            |   11 +
 arch/arm/mach-davinci/board-dm355-evm.c            |   27 ++
 arch/arm/mach-davinci/board-dm355-leopard.c        |    1 +
 arch/arm/mach-davinci/board-dm365-evm.c            |   28 ++
 arch/arm/mach-davinci/board-dm644x-evm.c           |   26 ++
 arch/arm/mach-davinci/board-dm646x-evm.c           |   27 ++
 arch/arm/mach-davinci/board-neuros-osd2.c          |    1 +
 arch/arm/mach-davinci/board-omapl138-hawk.c        |    2 +
 arch/arm/mach-davinci/da830.c                      |    4 -
 arch/arm/mach-davinci/da850.c                      |    4 -
 arch/arm/mach-davinci/devices-da8xx.c              |   26 ++
 arch/arm/mach-davinci/devices.c                    |   14 +
 arch/arm/mach-davinci/dm355.c                      |    4 -
 arch/arm/mach-davinci/dm365.c                      |    5 -
 arch/arm/mach-davinci/dm644x.c                     |    4 -
 arch/arm/mach-davinci/dm646x.c                     |    4 -
 arch/arm/mach-davinci/include/mach/common.h        |    4 +
 arch/arm/mach-davinci/include/mach/da8xx.h         |    1 +
 arch/arm/mach-davinci/include/mach/gpio-davinci.h  |    8 +-
 drivers/gpio/gpio-davinci.c                        |  346 +++++++++++++-------
 include/linux/platform_data/gpio-davinci.h         |   79 +++++
 26 files changed, 543 insertions(+), 157 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-davinci.txt
 create mode 100644 include/linux/platform_data/gpio-davinci.h

-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:25 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:25 +0530
Subject: [PATCH 02/11] gpio: davinci: coding style correction
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-3-git-send-email-avinashphilip@ti.com>

1. Corrects coding and commenting styles
2. Variables name change to meaningful name
3. Remove unnecessary variable usage
4. Add BINTEN macro definition

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 drivers/gpio/gpio-davinci.c |  182 +++++++++++++++++++++----------------------
 1 file changed, 89 insertions(+), 93 deletions(-)

diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 17df6db..d308955 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -9,12 +9,12 @@
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
-#include <linux/gpio.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
+
 #include <linux/clk.h>
-#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
 
 #include <asm/mach/irq.h>
 
@@ -31,10 +31,11 @@ struct davinci_gpio_regs {
 	u32	intstat;
 };
 
+#define BINTEN	0x08 /* GPIO Interrupt Per-Bank Enable Register */
 #define chip2controller(chip)	\
 	container_of(chip, struct davinci_gpio_controller, chip)
 
-static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static struct davinci_gpio_controller ctlrs[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 static void __iomem *gpio_base;
 
 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
@@ -53,42 +54,37 @@ static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 		ptr = gpio_base + 0xb0;
 	else
 		ptr = NULL;
+
 	return ptr;
 }
 
 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 {
-	struct davinci_gpio_regs __iomem *g;
-
-	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
-
-	return g;
+	return (__force struct davinci_gpio_regs __iomem *)
+		irq_get_chip_data(irq);
 }
 
 static int __init davinci_gpio_irq_setup(void);
 
-/*--------------------------------------------------------------------------*/
-
-/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
 static inline int __davinci_direction(struct gpio_chip *chip,
 			unsigned offset, bool out, int value)
 {
-	struct davinci_gpio_controller *d = chip2controller(chip);
-	struct davinci_gpio_regs __iomem *g = d->regs;
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *regs = ctlr->regs;
 	unsigned long flags;
 	u32 temp;
 	u32 mask = 1 << offset;
 
-	spin_lock_irqsave(&d->lock, flags);
-	temp = __raw_readl(&g->dir);
+	spin_lock_irqsave(&ctlr->lock, flags);
+	temp = __raw_readl(&regs->dir);
 	if (out) {
 		temp &= ~mask;
-		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
+		__raw_writel(mask, value ? &regs->set_data : &regs->clr_data);
 	} else {
 		temp |= mask;
 	}
-	__raw_writel(temp, &g->dir);
-	spin_unlock_irqrestore(&d->lock, flags);
+	__raw_writel(temp, &regs->dir);
+	spin_unlock_irqrestore(&ctlr->lock, flags);
 
 	return 0;
 }
@@ -98,8 +94,8 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 	return __davinci_direction(chip, offset, false, 0);
 }
 
-static int
-davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
+static int davinci_direction_out(struct gpio_chip *chip, unsigned offset,
+		int value)
 {
 	return __davinci_direction(chip, offset, true, value);
 }
@@ -113,22 +109,22 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  */
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio_controller *d = chip2controller(chip);
-	struct davinci_gpio_regs __iomem *g = d->regs;
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *regs = ctlr->regs;
 
-	return (1 << offset) & __raw_readl(&g->in_data);
+	return (1 << offset) & __raw_readl(&regs->in_data);
 }
 
 /*
  * Assuming the pin is muxed as a gpio output, set its output value.
  */
-static void
-davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
+		int value)
 {
-	struct davinci_gpio_controller *d = chip2controller(chip);
-	struct davinci_gpio_regs __iomem *g = d->regs;
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *regs = ctlr->regs;
 
-	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
+	__raw_writel((1 << offset), value ? &regs->set_data : &regs->clr_data);
 }
 
 static int __init davinci_gpio_setup(void)
@@ -160,30 +156,30 @@ static int __init davinci_gpio_setup(void)
 		return -ENOMEM;
 
 	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
-		chips[i].chip.label = "DaVinci";
+		ctlrs[i].chip.label = "DaVinci";
 
-		chips[i].chip.direction_input = davinci_direction_in;
-		chips[i].chip.get = davinci_gpio_get;
-		chips[i].chip.direction_output = davinci_direction_out;
-		chips[i].chip.set = davinci_gpio_set;
+		ctlrs[i].chip.direction_input = davinci_direction_in;
+		ctlrs[i].chip.direction_output = davinci_direction_out;
+		ctlrs[i].chip.get = davinci_gpio_get;
+		ctlrs[i].chip.set = davinci_gpio_set;
 
-		chips[i].chip.base = base;
-		chips[i].chip.ngpio = ngpio - base;
-		if (chips[i].chip.ngpio > 32)
-			chips[i].chip.ngpio = 32;
+		ctlrs[i].chip.base = base;
+		ctlrs[i].chip.ngpio = ngpio - base;
+		if (ctlrs[i].chip.ngpio > 32)
+			ctlrs[i].chip.ngpio = 32;
 
-		spin_lock_init(&chips[i].lock);
+		spin_lock_init(&ctlrs[i].lock);
 
 		regs = gpio2regs(base);
-		chips[i].regs = regs;
-		chips[i].set_data = &regs->set_data;
-		chips[i].clr_data = &regs->clr_data;
-		chips[i].in_data = &regs->in_data;
+		ctlrs[i].regs = regs;
+		ctlrs[i].set_data = &regs->set_data;
+		ctlrs[i].clr_data = &regs->clr_data;
+		ctlrs[i].in_data = &regs->in_data;
 
-		gpiochip_add(&chips[i].chip);
+		gpiochip_add(&ctlrs[i].chip);
 	}
 
-	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs = ctlrs;
 	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
 
 	davinci_gpio_irq_setup();
@@ -191,7 +187,6 @@ static int __init davinci_gpio_setup(void)
 }
 pure_initcall(davinci_gpio_setup);
 
-/*--------------------------------------------------------------------------*/
 /*
  * We expect irqs will normally be set up as input pins, but they can also be
  * used as output pins ... which is convenient for testing.
@@ -205,16 +200,16 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(struct irq_data *d)
 {
-	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+	struct davinci_gpio_regs __iomem *regs = irq2regs(d->irq);
 	u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
-	__raw_writel(mask, &g->clr_falling);
-	__raw_writel(mask, &g->clr_rising);
+	__raw_writel(mask, &regs->clr_falling);
+	__raw_writel(mask, &regs->clr_rising);
 }
 
 static void gpio_irq_enable(struct irq_data *d)
 {
-	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+	struct davinci_gpio_regs __iomem *regs = irq2regs(d->irq);
 	u32 mask = (u32) irq_data_get_irq_handler_data(d);
 	unsigned status = irqd_get_trigger_type(d);
 
@@ -223,9 +218,9 @@ static void gpio_irq_enable(struct irq_data *d)
 		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 
 	if (status & IRQ_TYPE_EDGE_FALLING)
-		__raw_writel(mask, &g->set_falling);
+		__raw_writel(mask, &regs->set_falling);
 	if (status & IRQ_TYPE_EDGE_RISING)
-		__raw_writel(mask, &g->set_rising);
+		__raw_writel(mask, &regs->set_rising);
 }
 
 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
@@ -244,15 +239,15 @@ static struct irq_chip gpio_irqchip = {
 	.flags		= IRQCHIP_SET_TYPE_MASKED,
 };
 
-static void
-gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct davinci_gpio_regs __iomem *g;
 	u32 mask = 0xffff;
-	struct davinci_gpio_controller *d;
+	struct davinci_gpio_controller *ctlr;
+	struct davinci_gpio_regs __iomem *regs;
 
-	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
-	g = (struct davinci_gpio_regs __iomem *)d->regs;
+	ctlr = (struct davinci_gpio_controller *)
+		irq_desc_get_handler_data(desc);
+	regs = ctlr->regs;
 
 	/* we only care about one bank */
 	if (irq & 1)
@@ -267,13 +262,13 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 		int		res;
 
 		/* ack any irqs */
-		status = __raw_readl(&g->intstat) & mask;
+		status = __raw_readl(&regs->intstat) & mask;
 		if (!status)
 			break;
-		__raw_writel(status, &g->intstat);
+		__raw_writel(status, &regs->intstat);
 
 		/* now demux them to the right lowlevel handler */
-		n = d->irq_base;
+		n = ctlr->irq_base;
 		if (irq & 1) {
 			n += 16;
 			status >>= 16;
@@ -292,10 +287,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
 
-	if (d->irq_base >= 0)
-		return d->irq_base + offset;
+	if (ctlr->irq_base >= 0)
+		return ctlr->irq_base + offset;
 	else
 		return -ENODEV;
 }
@@ -304,7 +299,8 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
-	/* NOTE:  we assume for now that only irqs in the first gpio_chip
+	/*
+	 * NOTE:  we assume for now that only irqs in the first gpio_chip
 	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 	 */
 	if (offset < soc_info->gpio_unbanked)
@@ -315,22 +311,22 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 {
-	struct davinci_gpio_controller *d;
-	struct davinci_gpio_regs __iomem *g;
+	struct davinci_gpio_controller *ctlr;
+	struct davinci_gpio_regs __iomem *regs;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	u32 mask;
 
-	d = (struct davinci_gpio_controller *)data->handler_data;
-	g = (struct davinci_gpio_regs __iomem *)d->regs;
+	ctlr = (struct davinci_gpio_controller *)data->handler_data;
+	regs = (struct davinci_gpio_regs __iomem *)ctlr->regs;
 	mask = __gpio_mask(data->irq - soc_info->gpio_irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 		return -EINVAL;
 
 	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
-		     ? &g->set_falling : &g->clr_falling);
+		     ? &regs->set_falling : &regs->clr_falling);
 	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
-		     ? &g->set_rising : &g->clr_rising);
+		     ? &regs->set_rising : &regs->clr_rising);
 
 	return 0;
 }
@@ -345,12 +341,11 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 
 static int __init davinci_gpio_irq_setup(void)
 {
-	unsigned	gpio, irq, bank;
-	struct clk	*clk;
 	u32		binten = 0;
-	unsigned	ngpio, bank_irq;
+	unsigned	gpio, irq, bank, ngpio, bank_irq;
+	struct clk	*clk;
+	struct davinci_gpio_regs __iomem *regs;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct davinci_gpio_regs	__iomem *g;
 
 	ngpio = soc_info->gpio_num;
 
@@ -368,16 +363,16 @@ static int __init davinci_gpio_irq_setup(void)
 	}
 	clk_prepare_enable(clk);
 
-	/* Arrange gpio_to_irq() support, handling either direct IRQs or
+	/*
+	 * Arrange gpio_to_irq() support, handling either direct IRQs or
 	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 	 * IRQs, while the others use banked IRQs, would need some setup
 	 * tweaks to recognize hardware which can do that.
 	 */
 	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
-		chips[bank].chip.to_irq = gpio_to_irq_banked;
-		chips[bank].irq_base = soc_info->gpio_unbanked
-			? -EINVAL
-			: (soc_info->intc_irq_num + gpio);
+		ctlrs[bank].chip.to_irq = gpio_to_irq_banked;
+		ctlrs[bank].irq_base = soc_info->gpio_unbanked ?
+			-EINVAL : (soc_info->intc_irq_num + gpio);
 	}
 
 	/*
@@ -389,7 +384,7 @@ static int __init davinci_gpio_irq_setup(void)
 		static struct irq_chip_type gpio_unbanked;
 
 		/* pass "bank 0" GPIO IRQs to AINTC */
-		chips[0].chip.to_irq = gpio_to_irq_unbanked;
+		ctlrs[0].chip.to_irq = gpio_to_irq_unbanked;
 		binten = BIT(0);
 
 		/* AINTC handles mask/unmask; GPIO handles triggering */
@@ -400,14 +395,14 @@ static int __init davinci_gpio_irq_setup(void)
 		gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
 
 		/* default trigger: both edges */
-		g = gpio2regs(0);
-		__raw_writel(~0, &g->set_falling);
-		__raw_writel(~0, &g->set_rising);
+		regs = gpio2regs(0);
+		__raw_writel(~0, &regs->set_falling);
+		__raw_writel(~0, &regs->set_rising);
 
 		/* set the direct IRQs up to use that irqchip */
 		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 			irq_set_chip(irq, &gpio_unbanked.chip);
-			irq_set_handler_data(irq, &chips[gpio / 32]);
+			irq_set_handler_data(irq, &ctlrs[gpio / 32]);
 			irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
 		}
 
@@ -424,9 +419,9 @@ static int __init davinci_gpio_irq_setup(void)
 		unsigned		i;
 
 		/* disabled by default, enabled only as needed */
-		g = gpio2regs(gpio);
-		__raw_writel(~0, &g->clr_falling);
-		__raw_writel(~0, &g->clr_rising);
+		regs = gpio2regs(gpio);
+		__raw_writel(~0, &regs->clr_falling);
+		__raw_writel(~0, &regs->clr_rising);
 
 		/* set up all irqs in this bank */
 		irq_set_chained_handler(bank_irq, gpio_irq_handler);
@@ -436,11 +431,11 @@ static int __init davinci_gpio_irq_setup(void)
 		 * gpio irqs. Pass the irq bank's corresponding controller to
 		 * the chained irq handler.
 		 */
-		irq_set_handler_data(bank_irq, &chips[gpio / 32]);
+		irq_set_handler_data(bank_irq, &ctlrs[gpio / 32]);
 
 		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 			irq_set_chip(irq, &gpio_irqchip);
-			irq_set_chip_data(irq, (__force void *)g);
+			irq_set_chip_data(irq, (__force void *)regs);
 			irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
 			irq_set_handler(irq, handle_simple_irq);
 			set_irq_flags(irq, IRQF_VALID);
@@ -450,10 +445,11 @@ static int __init davinci_gpio_irq_setup(void)
 	}
 
 done:
-	/* BINTEN -- per-bank interrupt enable. genirq would also let these
+	/*
+	 * BINTEN -- per-bank interrupt enable. genirq would also let these
 	 * bits be set/cleared dynamically.
 	 */
-	__raw_writel(binten, gpio_base + 0x08);
+	__raw_writel(binten, gpio_base + BINTEN);
 
 	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:26 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:26 +0530
Subject: [PATCH 03/11] gpio: davinci: Modify to platform driver
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-4-git-send-email-avinashphilip@ti.com>

From: KV Sujith <sujithkv at ti.com>

Modify GPIO Davinci driver to be compliant to standard platform drivers.
The driver did not have platform driver structure or a probe. Instead,
had a davinci_gpio_setup() function which is called in the pure_init
sequence. The function also had dependency on davinci_soc_info structure
of the corresponding platform. For Device Tree(DT) implementation, we
need to get rid of the dependency on the davinci_soc_info structure.
Hence as a first stage of DT conversion, we implement a probe. Future
commits shall modify the probe to read platform related data from DT.

- Add platform_driver structure and driver register function for davinci
  GPIO driver. The driver registration is made to happen in
  postcore_initcall. This is required since machine init functions like
  da850_lcd_hw_init() make use of GPIO.
- Convert the davinci_gpio_setup() to davinci_gpio_probe().
- Remove access of members in soc_info structure. Instead, relevant data
  are taken from davinci_gpio_platform_data structure pointed by
  pdev->dev.platform_data.
- Change clk_get() to devm_clk_get() as devm_clk_get() is a device
  managed function and makes error handling simpler.
- Change pr_err to dev_err for ngpio error reporting.
- Arrange include files and variables in alphabetical order

Signed-off-by: KV Sujith <sujithkv at ti.com>
[avinashphilip at ti.com: Move global definition for "struct
davinci_gpio_controller" variable to local in probe and set it as driver
data.]
Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/mach-davinci/include/mach/gpio-davinci.h |    2 +
 drivers/gpio/gpio-davinci.c                       |  121 +++++++++++++++------
 2 files changed, 87 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/gpio-davinci.h b/arch/arm/mach-davinci/include/mach/gpio-davinci.h
index 1fdd1fd..b325a1d 100644
--- a/arch/arm/mach-davinci/include/mach/gpio-davinci.h
+++ b/arch/arm/mach-davinci/include/mach/gpio-davinci.h
@@ -60,6 +60,8 @@ struct davinci_gpio_controller {
 	void __iomem		*set_data;
 	void __iomem		*clr_data;
 	void __iomem		*in_data;
+	int			gpio_unbanked;
+	unsigned		gpio_irq;
 };
 
 /* The __gpio_to_controller() and __gpio_mask() functions inline to constants
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index d308955..08830aa 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -11,10 +11,17 @@
  */
 
 #include <linux/clk.h>
+#include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/gpio-davinci.h>
+#include <mach/gpio-davinci.h>
 
 #include <asm/mach/irq.h>
 
@@ -35,10 +42,9 @@ struct davinci_gpio_regs {
 #define chip2controller(chip)	\
 	container_of(chip, struct davinci_gpio_controller, chip)
 
-static struct davinci_gpio_controller ctlrs[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 static void __iomem *gpio_base;
 
-static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
+static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
 {
 	void __iomem *ptr;
 
@@ -64,7 +70,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 		irq_get_chip_data(irq);
 }
 
-static int __init davinci_gpio_irq_setup(void);
+static int davinci_gpio_irq_setup(struct platform_device *pdev);
 
 static inline int __davinci_direction(struct gpio_chip *chip,
 			unsigned offset, bool out, int value)
@@ -127,33 +133,52 @@ static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
 	__raw_writel((1 << offset), value ? &regs->set_data : &regs->clr_data);
 }
 
-static int __init davinci_gpio_setup(void)
+static int davinci_gpio_probe(struct platform_device *pdev)
 {
 	int i, base;
 	unsigned ngpio;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct davinci_gpio_controller *ctlrs;
+	struct davinci_gpio_platform_data *pdata;
 	struct davinci_gpio_regs *regs;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
 
-	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
-		return 0;
+	pdata = dev->platform_data;
+	if (!pdata) {
+		dev_err(dev, "GPIO: No Platform Data Supplied\n");
+		return -EINVAL;
+	}
 
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
 	 * and "ngpio" is one more than the largest zero-based
 	 * bit index that's valid.
 	 */
-	ngpio = soc_info->gpio_num;
+	ngpio = pdata->ngpio;
 	if (ngpio == 0) {
-		pr_err("GPIO setup:  how many GPIOs?\n");
+		dev_err(dev, "GPIO Probe: how many GPIOs?\n");
 		return -EINVAL;
 	}
 
 	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 		ngpio = DAVINCI_N_GPIO;
 
-	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
-	if (WARN_ON(!gpio_base))
+	ctlrs = devm_kzalloc(dev,
+		ngpio * sizeof(struct davinci_gpio_controller), GFP_KERNEL);
+	if (!ctlrs) {
+		dev_err(dev, "Memory alloc failed\n");
 		return -ENOMEM;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (unlikely(!res)) {
+		dev_err(dev, "Invalid mem resource\n");
+		return -ENODEV;
+	}
+
+	gpio_base = devm_ioremap_resource(dev, res);
+	if (!gpio_base)
+		return -EADDRNOTAVAIL;
 
 	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 		ctlrs[i].chip.label = "DaVinci";
@@ -179,13 +204,10 @@ static int __init davinci_gpio_setup(void)
 		gpiochip_add(&ctlrs[i].chip);
 	}
 
-	soc_info->gpio_ctlrs = ctlrs;
-	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
-
-	davinci_gpio_irq_setup();
+	platform_set_drvdata(pdev, ctlrs);
+	davinci_gpio_irq_setup(pdev);
 	return 0;
 }
-pure_initcall(davinci_gpio_setup);
 
 /*
  * We expect irqs will normally be set up as input pins, but they can also be
@@ -297,14 +319,14 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
 
 	/*
 	 * NOTE:  we assume for now that only irqs in the first gpio_chip
 	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 	 */
-	if (offset < soc_info->gpio_unbanked)
-		return soc_info->gpio_irq + offset;
+	if (offset < ctlr->irq_base)
+		return ctlr->gpio_irq + offset;
 	else
 		return -ENODEV;
 }
@@ -313,12 +335,11 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 {
 	struct davinci_gpio_controller *ctlr;
 	struct davinci_gpio_regs __iomem *regs;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	u32 mask;
 
 	ctlr = (struct davinci_gpio_controller *)data->handler_data;
 	regs = (struct davinci_gpio_regs __iomem *)ctlr->regs;
-	mask = __gpio_mask(data->irq - soc_info->gpio_irq);
+	mask = __gpio_mask(data->irq - ctlr->gpio_irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 		return -EINVAL;
@@ -339,23 +360,33 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
  * (dm6446) can be set appropriately for GPIOV33 pins.
  */
 
-static int __init davinci_gpio_irq_setup(void)
+static int davinci_gpio_irq_setup(struct platform_device *pdev)
 {
-	u32		binten = 0;
-	unsigned	gpio, irq, bank, ngpio, bank_irq;
-	struct clk	*clk;
+	u32 binten = 0;
+	unsigned gpio, irq, bank, ngpio, bank_irq;
+	struct clk *clk;
+	struct davinci_gpio_controller *ctlrs = platform_get_drvdata(pdev);
+	struct davinci_gpio_platform_data *pdata;
 	struct davinci_gpio_regs __iomem *regs;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+
+	pdata = dev->platform_data;
+	ngpio = pdata->ngpio;
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (unlikely(!res)) {
+		dev_err(dev, "Invalid IRQ resource\n");
+		return -ENODEV;
+	}
 
-	ngpio = soc_info->gpio_num;
+	bank_irq = res->start;
 
-	bank_irq = soc_info->gpio_irq;
-	if (bank_irq == 0) {
-		printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
-		return -EINVAL;
+	if (unlikely(!bank_irq)) {
+		dev_err(dev, "Invalid IRQ resource\n");
+		return -ENODEV;
 	}
 
-	clk = clk_get(NULL, "gpio");
+	clk = devm_clk_get(dev, "gpio");
 	if (IS_ERR(clk)) {
 		printk(KERN_ERR "Error %ld getting gpio clock?\n",
 		       PTR_ERR(clk));
@@ -371,8 +402,8 @@ static int __init davinci_gpio_irq_setup(void)
 	 */
 	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
 		ctlrs[bank].chip.to_irq = gpio_to_irq_banked;
-		ctlrs[bank].irq_base = soc_info->gpio_unbanked ?
-			-EINVAL : (soc_info->intc_irq_num + gpio);
+		ctlrs[bank].irq_base = pdata->gpio_unbanked ?
+			-EINVAL : (pdata->intc_irq_num + gpio);
 	}
 
 	/*
@@ -380,7 +411,7 @@ static int __init davinci_gpio_irq_setup(void)
 	 * controller only handling trigger modes.  We currently assume no
 	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 	 */
-	if (soc_info->gpio_unbanked) {
+	if (pdata->gpio_unbanked) {
 		static struct irq_chip_type gpio_unbanked;
 
 		/* pass "bank 0" GPIO IRQs to AINTC */
@@ -400,7 +431,7 @@ static int __init davinci_gpio_irq_setup(void)
 		__raw_writel(~0, &regs->set_rising);
 
 		/* set the direct IRQs up to use that irqchip */
-		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
+		for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
 			irq_set_chip(irq, &gpio_unbanked.chip);
 			irq_set_handler_data(irq, &ctlrs[gpio / 32]);
 			irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
@@ -455,3 +486,21 @@ done:
 
 	return 0;
 }
+
+static struct platform_driver davinci_gpio_driver = {
+	.probe		= davinci_gpio_probe,
+	.driver		= {
+		.name	= "davinci_gpio",
+		.owner	= THIS_MODULE,
+	},
+};
+
+/**
+ * gpio driver register needs to be done before machine_init functions
+ * access gpio APIs. Hence davinci_gpio_drv_reg() is a postcore_initcall.
+ */
+static int __init davinci_gpio_drv_reg(void)
+{
+	return platform_driver_register(&davinci_gpio_driver);
+}
+postcore_initcall(davinci_gpio_drv_reg);
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:27 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:27 +0530
Subject: [PATCH 04/11] ARM: davinci: da8xx: creation of gpio platform device
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-5-git-send-email-avinashphilip@ti.com>

From: KV Sujith <sujithkv at ti.com>

gpio controller resource information being associated with
davinci_soc_info structure and not created any device. Hence davinci
gpio didn't fall under proper device model. This patch creates gpio
davinci as a platform device for da8xx platforms.

- Add Memory and IRQ resources for DA8xx.
- Register GPIO platform driver for DA8xx.
- Add da8xx_register_gpio API to create platform device for da8xx
  platforms.

Signed-off-by: KV Sujith <sujithkv at ti.com>
Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/mach-davinci/devices-da8xx.c      |   26 ++++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/da8xx.h |    1 +
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..892ad86 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -640,6 +640,32 @@ int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 	return platform_device_register(&da8xx_lcdc_device);
 }
 
+static struct resource da8xx_gpio_resources[] = {
+	{ /* registers */
+		.start	= DA8XX_GPIO_BASE,
+		.end	= DA8XX_GPIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{ /* interrupt */
+		.start	= IRQ_DA8XX_GPIO0,
+		.end	= IRQ_DA8XX_GPIO8,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device da8xx_gpio_device = {
+	.name		= "davinci_gpio",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(da8xx_gpio_resources),
+	.resource	= da8xx_gpio_resources,
+};
+
+int __init da8xx_register_gpio(void *pdata)
+{
+	da8xx_gpio_device.dev.platform_data = pdata;
+	return platform_device_register(&da8xx_gpio_device);
+}
+
 static struct resource da8xx_mmcsd0_resources[] = {
 	{		/* registers */
 		.start	= DA8XX_MMCSD0_BASE,
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..aa66690 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -96,6 +96,7 @@ int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 int da850_register_mmcsd1(struct davinci_mmc_config *config);
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
+int da8xx_register_gpio(void *pdata);
 int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:28 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:28 +0530
Subject: [PATCH 05/11] ARM: davinci: creation of gpio platform device for dm
 platforms
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-6-git-send-email-avinashphilip@ti.com>

gpio controller resource information being associated with
davinci_soc_info structure and not created any device. Hence davinci
gpio didn't fall under proper device model. This patch creates gpio
davinci as a platform device for dm platforms.
Also add daivinci_register_gpio API to create platform device for dm*
platforms.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/mach-davinci/devices.c             |   13 +++++++++++++
 arch/arm/mach-davinci/include/mach/common.h |    2 ++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3..b4f345b 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -313,6 +313,19 @@ static void davinci_init_wdt(void)
 	platform_device_register(&davinci_wdt_device);
 }
 
+static struct platform_device davinci_gpio_device = {
+	.name		= "davinci_gpio",
+	.id		= -1,
+};
+
+int davinci_gpio_register(struct resource *res, int size, void *pdata)
+{
+	davinci_gpio_device.resource = res;
+	davinci_gpio_device.num_resources = size;
+	davinci_gpio_device.dev.platform_data = pdata;
+	return platform_device_register(&davinci_gpio_device);
+}
+
 /*-------------------------------------------------------------------------*/
 
 /*-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..bd389ba 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/ioport.h>
 
 extern void davinci_timer_init(void);
 
@@ -83,6 +84,7 @@ extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
 void davinci_restart(char mode, const char *cmd);
 void davinci_init_late(void);
+int davinci_gpio_register(struct resource *res, int size, void *pdata);
 
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
 int davinci_clk_disable_unused(void);
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:29 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:29 +0530
Subject: [PATCH 06/11] ARM: davinci: da8xx: gpio device creation
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-7-git-send-email-avinashphilip@ti.com>

Create davinci gpio device and remove references in davinci_soc_info
structure. Also rearrange header file inclusion in group basis.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/mach-davinci/board-da830-evm.c     |   19 +++++++++++++++----
 arch/arm/mach-davinci/board-da850-evm.c     |   11 +++++++++++
 arch/arm/mach-davinci/board-omapl138-hawk.c |    2 ++
 arch/arm/mach-davinci/da830.c               |    4 ----
 arch/arm/mach-davinci/da850.c               |    4 ----
 5 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 1332de8..4e8bcc1 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -22,17 +22,19 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/gpio-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/spi-davinci.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/cp_intc.h>
 #include <mach/mux.h>
-#include <linux/platform_data/mtd-davinci.h>
+#include <mach/common.h>
 #include <mach/da8xx.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
 
 #define DA830_EVM_PHY_ID		""
 /*
@@ -590,11 +592,20 @@ static struct spi_board_info da830evm_spi_info[] = {
 	},
 };
 
+static struct davinci_gpio_platform_data da830_gpio_platform_data = {
+	.ngpio = 128,
+	.intc_irq_num = DA830_N_CP_INTC_IRQ,
+};
+
 static __init void da830_evm_init(void)
 {
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	int ret;
 
+	ret = da8xx_register_gpio(&da830_gpio_platform_data);
+	if (ret)
+		pr_warn("da830_evm_init: GPIO init failed: %d\n", ret);
+
 	ret = da830_register_edma(da830_edma_rsv);
 	if (ret)
 		pr_warning("da830_evm_init: edma registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 8a24b6c..d5dd010 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/gpio-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mtd-davinci-aemif.h>
 #include <linux/platform_data/spi-davinci.h>
@@ -42,6 +43,7 @@
 #include <mach/da8xx.h>
 #include <mach/mux.h>
 #include <mach/sram.h>
+#include <mach/common.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -1138,6 +1140,11 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
 	&da850_edma_cc1_rsv,
 };
 
+static struct davinci_gpio_platform_data da850_gpio_platform_data = {
+	.ngpio = 144,
+	.intc_irq_num = DA850_N_CP_INTC_IRQ,
+};
+
 #ifdef CONFIG_CPU_FREQ
 static __init int da850_evm_init_cpufreq(void)
 {
@@ -1444,6 +1451,10 @@ static __init void da850_evm_init(void)
 {
 	int ret;
 
+	ret = da8xx_register_gpio(&da850_gpio_platform_data);
+	if (ret)
+		pr_warn("da850_evm_init: GPIO init failed: %d\n", ret);
+
 	ret = pmic_tps65070_init();
 	if (ret)
 		pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index b8c20de..1f44a1b 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/console.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-davinci.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -20,6 +21,7 @@
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
 #include <mach/mux.h>
+#include <mach/common.h>
 
 #define HAWKBOARD_PHY_ID		"davinci_mdio-0:07"
 #define DA850_HAWK_MMCSD_CD_PIN		GPIO_TO_PIN(3, 12)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index abbaf02..e7b79ee 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1195,10 +1195,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.intc_irq_prios		= da830_default_priorities,
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
 	.timer_info		= &da830_timer_info,
-	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= DA8XX_GPIO_BASE,
-	.gpio_num		= 128,
-	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
 };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4d69338..5f7cfa4 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1297,10 +1297,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.intc_irq_prios		= da850_default_priorities,
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
 	.timer_info		= &da850_timer_info,
-	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= DA8XX_GPIO_BASE,
-	.gpio_num		= 144,
-	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
 	.sram_dma		= DA8XX_SHARED_RAM_BASE,
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:30 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:30 +0530
Subject: [PATCH 07/11] ARM: davinci: create davinci gpio device for dm
 platforms
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-8-git-send-email-avinashphilip@ti.com>

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/mach-davinci/board-dm355-evm.c     |   27 ++++++++++++++++++++++++++
 arch/arm/mach-davinci/board-dm355-leopard.c |    1 +
 arch/arm/mach-davinci/board-dm365-evm.c     |   28 +++++++++++++++++++++++++++
 arch/arm/mach-davinci/board-dm644x-evm.c    |   26 +++++++++++++++++++++++++
 arch/arm/mach-davinci/board-dm646x-evm.c    |   27 ++++++++++++++++++++++++++
 arch/arm/mach-davinci/board-neuros-osd2.c   |    1 +
 arch/arm/mach-davinci/dm355.c               |    4 ----
 arch/arm/mach-davinci/dm365.c               |    5 -----
 arch/arm/mach-davinci/dm644x.c              |    4 ----
 arch/arm/mach-davinci/dm646x.c              |    4 ----
 arch/arm/mach-davinci/include/mach/common.h |    2 ++
 11 files changed, 112 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index bfdf8b9..785c7b8 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -28,9 +28,11 @@
 
 #include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
+#include <mach/common.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/gpio-davinci.h>
 
 #include "davinci.h"
 
@@ -311,9 +313,34 @@ static struct spi_board_info dm355_evm_spi_info[] __initconst = {
 	},
 };
 
+static struct resource dm355_gpio_resources[] = {
+	{ /* registers */
+		.start	= DAVINCI_GPIO_BASE,
+		.end	= DAVINCI_GPIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{ /* interrupt */
+		.start	= IRQ_DM355_GPIOBNK0,
+		.end	= IRQ_DM355_GPIOBNK6,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
+	.ngpio = 104,
+	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
+};
+
 static __init void dm355_evm_init(void)
 {
 	struct clk *aemif;
+	int ret;
+
+	ret = davinci_gpio_register(dm355_gpio_resources,
+			sizeof(dm355_gpio_resources),
+			&dm355_gpio_platform_data);
+	if (ret)
+		pr_warn("dm355_evm_init: GPIO init failed: %d\n", ret);
 
 	gpio_request(1, "dm9000");
 	gpio_direction_input(1);
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index dff4ddc..34a2b64 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -25,6 +25,7 @@
 
 #include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
+#include <mach/common.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 4cfdd91..623263e 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -38,6 +38,7 @@
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/keyscan-davinci.h>
+#include <linux/platform_data/gpio-davinci.h>
 
 #include <media/tvp514x.h>
 
@@ -586,8 +587,35 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
 	},
 };
 
+static struct resource dm365_gpio_resources[] = {
+	{ /* registers */
+		.start	= DAVINCI_GPIO_BASE,
+		.end	= DAVINCI_GPIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{ /* interrupt */
+		.start	= IRQ_DM365_GPIO0,
+		.end	= IRQ_DM365_GPIO7,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
+	.ngpio = 104,
+	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
+	.gpio_unbanked = 8,
+};
+
 static __init void dm365_evm_init(void)
 {
+	int ret;
+
+	ret = davinci_gpio_register(dm365_gpio_resources,
+			sizeof(dm365_gpio_resources),
+			&dm365_gpio_platform_data);
+	if (ret)
+		pr_warn("dm365_evm_init: GPIO init failed: %d\n", ret);
+
 	evm_init_i2c();
 	davinci_serial_init(&uart_config);
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index fc8e38e..76d9f6b 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -39,6 +39,7 @@
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
 #include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/gpio-davinci.h>
 
 #include "davinci.h"
 
@@ -755,11 +756,36 @@ static int davinci_phy_fixup(struct phy_device *phydev)
 
 #define HAS_NAND	IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 
+static struct resource dm644_gpio_resources[] = {
+	{ /* registers */
+		.start	= DAVINCI_GPIO_BASE,
+		.end	= DAVINCI_GPIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{ /* interrupt */
+		.start	= IRQ_GPIOBNK0,
+		.end	= IRQ_GPIOBNK4,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
+	.ngpio = 71,
+	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
+};
+
 static __init void davinci_evm_init(void)
 {
+	int ret;
 	struct clk *aemif_clk;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
+	ret = davinci_gpio_register(dm644_gpio_resources,
+			sizeof(dm644_gpio_resources),
+			&dm644_gpio_platform_data);
+	if (ret)
+		pr_warn("davinci_evm_init: GPIO init failed: %d\n", ret);
+
 	aemif_clk = clk_get(NULL, "aemif");
 	clk_prepare_enable(aemif_clk);
 
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 03785e0..e419d9e 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -39,11 +39,13 @@
 
 #include <mach/common.h>
 #include <mach/serial.h>
+#include <mach/irqs.h>
 #include <linux/platform_data/i2c-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <mach/clock.h>
 #include <mach/cdce949.h>
 #include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
@@ -787,10 +789,35 @@ static struct edma_rsv_info dm646x_edma_rsv[] = {
 	},
 };
 
+static struct resource dm646_gpio_resources[] = {
+	{ /* registers */
+		.start	= DAVINCI_GPIO_BASE,
+		.end	= DAVINCI_GPIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{ /* interrupt */
+		.start	= IRQ_DM646X_GPIOBNK0,
+		.end	= IRQ_DM646X_GPIOBNK2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct davinci_gpio_platform_data dm646_gpio_platform_data = {
+	.ngpio = 43,
+	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
+};
+
 static __init void evm_init(void)
 {
+	int ret;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
+	ret = davinci_gpio_register(dm646_gpio_resources,
+			sizeof(dm646_gpio_resources),
+			&dm646_gpio_platform_data);
+	if (ret)
+		pr_warn("evm_init: GPIO init failed: %d\n", ret);
+
 	evm_init_i2c();
 	davinci_serial_init(&uart_config);
 	dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 2bc112a..c2b96ec 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -37,6 +37,7 @@
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/gpio-davinci.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 87e6104..2ecbb71 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -840,10 +840,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.intc_irq_prios		= dm355_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm355_timer_info,
-	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= DAVINCI_GPIO_BASE,
-	.gpio_num		= 104,
-	.gpio_irq		= IRQ_DM355_GPIOBNK0,
 	.serial_dev		= &dm355_serial_device,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 2791df9..861dec9 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1084,11 +1084,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.intc_irq_prios		= dm365_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm365_timer_info,
-	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= DAVINCI_GPIO_BASE,
-	.gpio_num		= 104,
-	.gpio_irq		= IRQ_DM365_GPIO0,
-	.gpio_unbanked		= 8,	/* really 16 ... skip muxed GPIOs */
 	.serial_dev		= &dm365_serial_device,
 	.emac_pdata		= &dm365_emac_pdata,
 	.sram_dma		= 0x00010000,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index ab6bf54..d1d7670 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -868,10 +868,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.intc_irq_prios 	= dm644x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm644x_timer_info,
-	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= DAVINCI_GPIO_BASE,
-	.gpio_num		= 71,
-	.gpio_irq		= IRQ_GPIOBNK0,
 	.serial_dev		= &dm644x_serial_device,
 	.emac_pdata		= &dm644x_emac_pdata,
 	.sram_dma		= 0x00008000,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index ac7b431..1058e7c 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -845,10 +845,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.intc_irq_prios		= dm646x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm646x_timer_info,
-	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= DAVINCI_GPIO_BASE,
-	.gpio_num		= 43, /* Only 33 usable */
-	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
 	.serial_dev		= &dm646x_serial_device,
 	.emac_pdata		= &dm646x_emac_pdata,
 	.sram_dma		= 0x10010000,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index bd389ba..f9d81fb 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -38,6 +38,8 @@ struct davinci_timer_info {
 
 struct davinci_gpio_controller;
 
+#define DAVINCI_GPIO_BASE 0x01C67000
+
 /*
  * SoC info passed into common davinci modules.
  *
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:31 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:31 +0530
Subject: [PATCH 08/11] ARM: davinci: start using gpiolib support
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-9-git-send-email-avinashphilip@ti.com>

- Remove NEED_MACH_GPIO_H config option for Davinci platforms to start
  using common gpio library interface.
- Added struct davinci_gpio_controller definitions in platform_data
  directory for Davinci gpio devices.
- Removed GPIO_TYPE_DAVINCI enum definition as GPIO Davinci is converted
  to Linux device driver model.

Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/Kconfig                                  |    1 -
 arch/arm/mach-davinci/include/mach/gpio-davinci.h |    6 +++--
 include/linux/platform_data/gpio-davinci.h        |   27 +++++++++++++++++++++
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13b7394..74d3e85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -955,7 +955,6 @@ config ARCH_DAVINCI
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_IRQ_CHIP
 	select HAVE_IDE
-	select NEED_MACH_GPIO_H
 	select USE_OF
 	select ZONE_DMA
 	help
diff --git a/arch/arm/mach-davinci/include/mach/gpio-davinci.h b/arch/arm/mach-davinci/include/mach/gpio-davinci.h
index b325a1d..18140e0 100644
--- a/arch/arm/mach-davinci/include/mach/gpio-davinci.h
+++ b/arch/arm/mach-davinci/include/mach/gpio-davinci.h
@@ -23,9 +23,10 @@
 
 #define DAVINCI_GPIO_BASE 0x01C67000
 
+#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
+
 enum davinci_gpio_type {
-	GPIO_TYPE_DAVINCI = 0,
-	GPIO_TYPE_TNETV107X,
+	GPIO_TYPE_TNETV107X = 0,
 };
 
 /*
@@ -90,4 +91,5 @@ static inline u32 __gpio_mask(unsigned gpio)
 	return 1 << (gpio % 32);
 }
 
+#endif	/* CONFIG_ARCH_DAVINCI_TNETV107X */
 #endif	/* __DAVINCI_DAVINCI_GPIO_H */
diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h
index f1c8277..75805d4 100644
--- a/include/linux/platform_data/gpio-davinci.h
+++ b/include/linux/platform_data/gpio-davinci.h
@@ -18,10 +18,37 @@
 #ifndef __ASM_ARCH_DAVINCI_GPIO_H
 #define __ASM_ARCH_DAVINCI_GPIO_H
 
+#include <asm-generic/gpio.h>
+
 struct davinci_gpio_platform_data {
 	u32	ngpio;
 	u32	gpio_unbanked;
 	u32	intc_irq_num;
 };
 
+
+struct davinci_gpio_controller {
+	struct gpio_chip	chip;
+	int			irq_base;
+	spinlock_t		lock;
+	void __iomem		*regs;
+	void __iomem		*set_data;
+	void __iomem		*clr_data;
+	void __iomem		*in_data;
+	int			gpio_unbanked;
+	unsigned		gpio_irq;
+};
+
+/*
+ * basic gpio routines
+ */
+#define	GPIO(X)		(X)	/* 0 <= X <= (DAVINCI_N_GPIO - 1) */
+
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio)	(16 * (bank) + (gpio))
+
+static inline u32 __gpio_mask(unsigned gpio)
+{
+	return 1 << (gpio % 32);
+}
 #endif
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:32 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:32 +0530
Subject: [PATCH 09/11] gpio: davinci: DT changes for driver
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-10-git-send-email-avinashphilip@ti.com>

From: KV Sujith <sujithkv at ti.com>

- Add of_device_id for Davinci GPIO driver.
- Add function to populate data from DT.
- Modify the probe to read from DT if DT match is found.
- Add DT binding documentation for Davinci GPIO properties in a new file
  gpio-davinci.txt located at Documentation/devicetree/bindings/gpio/.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Signed-off-by: KV Sujith <sujithkv at ti.com>
Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 .../devicetree/bindings/gpio/gpio-davinci.txt      |   26 +++++++++
 drivers/gpio/gpio-davinci.c                        |   57 ++++++++++++++++++--
 2 files changed, 80 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-davinci.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
new file mode 100644
index 0000000..0d599d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -0,0 +1,26 @@
+Davinci GPIO controller bindings
+
+Required Properties:
+- compatible:"ti,da830-gpio"
+
+- reg: Physical base address of the controller and length of memory mapped
+	region.
+
+- interrupts: The Starting IRQ number for GPIO
+
+- ngpio: The number of GPIO pins supported
+
+- intc_irq_num: The number of IRQs supported by the Interrupt Controller
+
+- gpio_unbanked: The number of GPIOs that have an individual interrupt
+		line to processor.
+
+Example:
+gpio: gpio at 1e26000 {
+	compatible = "ti,da830-gpio";
+	reg = <0x226000 0x1000>;
+	interrupts = <42>;
+	ngpio = <144>;
+	intc_irq_num = <101>;
+	gpio_unbanked = <0>;
+};
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 08830aa..dbe3b83 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -19,6 +19,8 @@
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/gpio-davinci.h>
 #include <mach/gpio-davinci.h>
@@ -133,6 +135,50 @@ static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
 	__raw_writel((1 << offset), value ? &regs->set_data : &regs->clr_data);
 }
 
+static struct davinci_gpio_platform_data *davinci_gpio_set_pdata_of(
+						struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct davinci_gpio_platform_data *pdata;
+	u32 val, ret;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (pdata) {
+		ret = of_property_read_u32(dn, "ngpio", &val);
+		if (ret)
+			goto of_err;
+
+		pdata->ngpio = val;
+
+		ret = of_property_read_u32(dn, "gpio_unbanked", &val);
+		if (ret)
+			goto of_err;
+
+		pdata->gpio_unbanked = val;
+
+		ret = of_property_read_u32(dn, "intc_irq_num", &val);
+		if (ret)
+			goto of_err;
+
+		pdata->intc_irq_num = val;
+	}
+
+	return pdata;
+
+of_err:
+	dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
+	return NULL;
+}
+
+static const struct of_device_id davinci_gpio_ids[] = {
+	{
+		.compatible = "ti,da830-gpio",
+	},
+	{ },
+};
+
+MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
+
 static int davinci_gpio_probe(struct platform_device *pdev)
 {
 	int i, base;
@@ -142,13 +188,17 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 	struct davinci_gpio_regs *regs;
 	struct device *dev = &pdev->dev;
 	struct resource *res;
+	const struct of_device_id *match =
+		of_match_device(of_match_ptr(davinci_gpio_ids), &pdev->dev);
 
-	pdata = dev->platform_data;
+	pdata = match ? davinci_gpio_set_pdata_of(pdev) : dev->platform_data;
 	if (!pdata) {
 		dev_err(dev, "GPIO: No Platform Data Supplied\n");
 		return -EINVAL;
 	}
 
+	dev->platform_data = pdata;
+
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
 	 * and "ngpio" is one more than the largest zero-based
@@ -490,8 +540,9 @@ done:
 static struct platform_driver davinci_gpio_driver = {
 	.probe		= davinci_gpio_probe,
 	.driver		= {
-		.name	= "davinci_gpio",
-		.owner	= THIS_MODULE,
+		.name		= "davinci_gpio",
+		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(davinci_gpio_ids),
 	},
 };
 
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:33 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:33 +0530
Subject: [PATCH 10/11] ARM: davinci: da850: add GPIO DT entries
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-11-git-send-email-avinashphilip@ti.com>

From: KV Sujith <sujithkv at ti.com>

Add DT entries for Davinci GPIO.

Signed-off-by: KV Sujith <sujithkv at ti.com>
Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/boot/dts/da850.dtsi |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 452bdc6..9014eba 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -126,6 +126,15 @@
 				>;
 			};
 		};
+		gpio: gpio at 1e26000 {
+			compatible = "ti,da830-gpio";
+			reg = <0x226000 0x1000>;
+			interrupts = <42>;
+			ngpio = <144>;
+			intc_irq_num = <101>;
+			gpio_unbanked = <0>;
+			status = "disabled";
+		};
 		serial0: serial at 1c42000 {
 			compatible = "ns16550a";
 			reg = <0x42000 0x100>;
-- 
1.7.9.5



From avinashphilip at ti.com  Wed May 22 03:10:34 2013
From: avinashphilip at ti.com (Philip Avinash)
Date: Wed, 22 May 2013 12:40:34 +0530
Subject: [PATCH 11/11] ARM: davinci: da850 evm: add GPIO DT data
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <1369206634-6778-12-git-send-email-avinashphilip@ti.com>

From: KV Sujith <sujithkv at ti.com>

- Add GPIO DT Data and pinmux for DA850 EVM. GPIO is configurable differently
  on different boards. So add GPIO pinmuxing in dts file.
- Dependency: This patch is dependent on Grab-pin-control patch;
  https://patchwork.kernel.org/patch/2013751/

Signed-off-by: KV Sujith <sujithkv at ti.com>
Signed-off-by: Philip Avinash <avinashphilip at ti.com>
---
 arch/arm/boot/dts/da850-evm.dts |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c914357..ab59e60 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -17,6 +17,20 @@
 	soc {
 		pmx_core: pinmux at 1c14120 {
 			status = "okay";
+			gpio_pins: pinmux_gpio_pins {
+				pinctrl-single,bits = <
+					/* GPIO2_4 GPIO2_6 */
+					0x18 0x00008080 0x0000f0f0
+					/* GPIO2_8 GPIO2_15 */
+					0x14 0x80000008 0xf000000f
+					/* GPIO3_12 GPIO3_13 */
+					0x1C 0x00008800 0x0000ff00
+					/* GPIO4_0 GPIO4_1 */
+					0x28 0x88000000 0xff000000
+					/* GPIO6_9 GPIO6_10 GPIO6_13 */
+					0x34 0x08800800 0x0ff00f00
+				>;
+			};
 		};
 		serial0: serial at 1c42000 {
 			status = "okay";
@@ -90,6 +104,11 @@
 				};
 			};
 		};
+		gpio: gpio at 1e26000 {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&gpio_pins>;
+		};
 	};
 	nand_cs3 at 62000000 {
 		status = "okay";
-- 
1.7.9.5



From shc_work at mail.ru  Wed May 22 03:17:36 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Wed, 22 May 2013 11:17:36 +0400
Subject: =?UTF-8?B?UmVbM106IFtQQVRDSF0gQVJNOiBpb211eC1teDUxOiBBbHdheXMgZGVmaW5l?=
 =?UTF-8?B?IFBVIEUgZm9yIHBpbnMgdXNlZCBhcyBHUElP?=
In-Reply-To: <20892.28064.82907.942799@ipc1.ka-ro>
References: <1369124845-19244-1-git-send-email-shc_work@mail.ru>
 <1369203552.559574351@f389.i.mail.ru>
 <20892.28064.82907.942799@ipc1.ka-ro>
Message-ID: <1369207056.596630214@f96.mail.ru>

> Alexander Shiyan writes:
> > > On Tue, May 21, 2013 at 12:27:25PM +0400, Alexander Shiyan wrote:
> > > > This patch adds a PUE bit for pins which used as GPIO. This allow
> > > > to use the GPIOs correctly as inputs when source is open-drain with
> > > > external pullup resistor (IRQ open-drain outputs for example).
> > > 
> > > I don't understand. If there's an external pullup why do you want to
> > > turn on the internal one?
> > 
> > It is just switch off keeper circuit.
> > 
> If you want to switch the keeper circuit off why don't you do that by
> removing PAD_CTL_PKE rather than adding PAD_CTL_PUE?

Again, I do not know which the solution here is better. If we remove
the PKE bit, for some pins it will be removed the default pullup/pulldown (PUS = 0),
so it may affect the some running configuration.

---

From jg1.han at samsung.com  Wed May 22 03:20:24 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 22 May 2013 16:20:24 +0900
Subject: [PATCH] ARM: EXYNOS: add __cpuinit annotation to write_pen_release()
Message-ID: <000201ce56bc$d399b770$7acd2650$@samsung.com>

The variable __cpuinitdata pen_release is referenced by write_pen_release().
Also, write_pen_release() is called by exynos_secondary_init() which is
annotated with __cpuinit. Thus, __cpuinit should be added write_pen_release()
to fix section mismatch warning.

Fixed section mismatch warning as below:

  WARNING: vmlinux.o(.text.unlikely+0x1f4): Section mismatch in reference from the function write_pen_release() to the variable
.cpuinit.data:pen_release
  The function write_pen_release() references the variable __cpuinitdata pen_release.
  This is often because write_pen_release lacks a __cpuinitdata annotation or the annotation of pen_release is wrong.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
 arch/arm/mach-exynos/platsmp.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7..9676af2 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -58,7 +58,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
-static void write_pen_release(int val)
+static void __cpuinit write_pen_release(int val)
 {
 	pen_release = val;
 	smp_wmb();
-- 
1.7.10.4




From shawn.guo at linaro.org  Wed May 22 03:23:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 May 2013 15:23:05 +0800
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
Message-ID: <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>

On 22 May 2013 14:40, Jin Zhengxiong-R64188 <R64188 at freescale.com> wrote:
> [Jason Jin-R64188] Reuse the same LPUART on LS-1 with the compatible strings 'fsl,mvf600-lpuart' is technically OK, But it will fuss the route map of the product Line. The general name can show that the IP is shared between several product lines, and the history for which SOC firstly used the IP is not very important. With general compatible name, We can setup the general dts for the shared IPs.
>
> That's also the case for the IPs used on Power platform, Take the IFC for example, this IP implemented on Power platform will also be reused LS-1, The compatible string is set as  "fsl,ifc", "simple-bus" but not the soc name on which the IP first used.
>
>  Another example, though a little different, the nor flash driver, which is used for many platform, the compatible "cfi-flash" will be more reasonable than the soc/board name.
>
> With the general name for the compatible string in the driver, if there is minor difference for the different implementation of the same IP, we can add the soc related compatible string to the driver to pass different .data structure for that soc.
>

As I already said, a generic compatible string does not specify
anything about compatibility/version, and hence it's not a good
compatible for IP block which is possibly to be integrated on multiple
SoCs with slight differences.

For example, if there is a new SoC mvf900 integrating the IP with
everything compatible to the version used on mvf600,

  compatible = <fsl,mvf900-uart>, <fsl,mvf600-uart>;
  compatible = <fsl,mvf900-uart>, <fsl,lpuart>;

which one do you think is better to tell the compatibility/version?

Shawn


From gang.chen at asianux.com  Wed May 22 03:32:20 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Wed, 22 May 2013 15:32:20 +0800
Subject: [PATCH] arm64: compiling issue for allmodconfig,
 need "asm/parport.h" by "drivers/parport/parport_pc.c"
In-Reply-To: <519C1539.10908@asianux.com>
References: <5177551D.8090007@asianux.com> <20130424082237.GA23397@arm.com>
 <5177B1F0.10106@asianux.com>
 <20130424102327.GF21850@mudshark.cambridge.arm.com>
 <5177BAD0.9000500@asianux.com> <20130424110511.GK23397@arm.com>
 <5199A453.4080402@asianux.com> <20130521131734.GD27002@arm.com>
 <519C1539.10908@asianux.com>
Message-ID: <519C7484.9020709@asianux.com>

On 05/22/2013 08:45 AM, Chen Gang wrote:
> On 05/21/2013 09:17 PM, Catalin Marinas wrote:
>> On Mon, May 20, 2013 at 05:19:31AM +0100, Chen Gang wrote:
>>>
>>> Need add the default file in 'asm/Kbuild' just like arm has done.
>>>
>>> The build command is:
>>>   make EXTRA_CFLAGS=-W ARCH=arm64 allmodconfig
>>>   make EXTRA_CFLAGS=-W ARCH=arm64 menuconfig
>>>     set "aarch64-linux-gnu-" as cross compiling prefix.
>>>   make EXTRA_CFLAGS=-W ARCH=arm64
>>>
>>> The related error:
>>>   drivers/parport/parport_pc.c:67:25: fatal error: asm/parport.h: No such file or directory
>>
>> As I don't see when we'd need this driver, you can probably change the
>> Kconfig entry (similar to the VGA_CONSOLE one).
>>

After check the Kconfig in drivers, we can find quite a few using long
list args which related with ARCH.

And they are not only depend on ARCHs, but also depend on another
things (e.g. VGA_CONSOL also depend on !4xx && !8xx, and another
combinations).

We also can find another long list for depend on, but not related with
ARCH.

They seems not quit difficult for reading (in fact, if we separate them
into pieces and let them spread into another areas, the reader will not
see the whole dependency clearly)

For fixing bug, better as local as possible, as independent as possible,
it will be OK if only add !ARM64 for PARPORT_PC depend on, and it has
no any negative effect. But if we define CONFIG_HAVE_*, we have to let
it related with multiple platforms.

For design: if can bear current design, better not to touch it, I think
current design is still sustainable, and not complex for understanding,
so not need redesign.


The depends on samples which related with ARCH:

  ./ide/Kconfig:  depends on ALPHA || X86 || IA64 || M32R || MIPS || ARCH_RPC || ARCH_SHARK
  ./dma/Kconfig:  depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
  ./misc/Kconfig: depends on (IA64_GENERIC || IA64_SGI_SN2 || IA64_SGI_UV || X86_UV) && SMP
  ./gpio/Kconfig: depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || ...
  ./gpio/Kconfig: depends on GPIOLIB && ARCH_MSM && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
  ./mtd/onenand/Kconfig:        depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4
  ./net/ethernet/ti/Kconfig:      depends on PCI || EISA || AR7 || (ARM && (ARCH_DAVINCI || ARCH_OMAP3 || SOC_AM33XX))
  ./net/ethernet/ibm/Kconfig:     depends on MCA || PPC_PSERIES || PPC_PSERIES || PPC_DCR || ...
  ./net/ethernet/smsc/Kconfig:    depends on (ARM || M32R || SUPERH || MIPS || BLACKFIN || ...
  ./net/ethernet/smsc/Kconfig:    depends on (ARM || SUPERH || BLACKFIN || MIPS || MN10300)
  ./rtc/Kconfig:  depends on X86 || ALPHA || ARM || M32R || ATARI || PPC || MIPS || SPARC64
  ./rtc/Kconfig:  depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX || SOC_AM33XX
  ./isdn/hisax/Kconfig:   depends on PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN)))
  ./isdn/hisax/Kconfig:   depends on PCI && (BROKEN || !(PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN)))
  ./isdn/hisax/Kconfig:   depends on PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN)))
  ./isdn/hisax/Kconfig:   depends on HISAX_NETJET && PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN)))
  ./input/serio/Kconfig:  depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && ...
  ./char/Kconfig: depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32 && !BLACKFIN && !UML
  ./video/console/Kconfig:        depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER)
  ./video/Kconfig:        depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || ARCH_S5P64X0 || ...
  ...



> 
> Oh, really it is, it is for PC, it seems except x86, no one else will
> use it. And for x86, it will be less and less used, in the future.
> 
> It seems it is a better candidate than VGA_CONSOLE. I will define
> CONFIG_HAVE_PARPORT_PC for it.  :-)
> 
> Thanks.
> 


-- 
Chen Gang

Asianux Corporation


From yegorslists at googlemail.com  Wed May 22 04:09:30 2013
From: yegorslists at googlemail.com (Yegor Yefremov)
Date: Wed, 22 May 2013 10:09:30 +0200
Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
In-Reply-To: <87zjvokxf0.fsf@linaro.org>
References: <20130515002537.GG5600@atomide.com>
 <20130515015212.GB3268@animalcreek.com>
 <20130515170734.GI5600@atomide.com> <20130515215028.GA11883@animalcreek.com>
 <5194B2A8.8020608@visionsystems.de> <20130517185620.GF28484@animalcreek.com>
 <CAGm1_ks10f=6aBxWHzd6KxAaFGfnZUNWrQrSZeFwsT3He9r0Ow@mail.gmail.com>
 <20130520220540.GL10378@atomide.com> <87zjvokxf0.fsf@linaro.org>
Message-ID: <CAGm1_kvoJ=y5t4SY_3p2Bk1PgU1DOJ39yOBFO83yBo__oLUGuw@mail.gmail.com>

On Tue, May 21, 2013 at 8:20 PM, Kevin Hilman <khilman at linaro.org> wrote:
> Tony Lindgren <tony at atomide.com> writes:
>
>> * Yegor Yefremov <yegorslists at googlemail.com> [130517 14:34]:
>>> On Fri, May 17, 2013 at 8:56 PM, Mark A. Greer <mgreer at animalcreek.com> wrote:
>>> > On Thu, May 16, 2013 at 12:19:20PM +0200, Yegor Yefremov wrote:
>>> >> On 15.05.2013 23:50, Mark A. Greer wrote:
>>> >> > On Wed, May 15, 2013 at 10:07:35AM -0700, Tony Lindgren wrote:
>>> >
>>> >> >> Mark, do you have some omap3 with no iva (other than am3703) to test the
>>> >> >> idle states with?
>>> >> >
>>> >> > I have an am35xx which isn't supposed to have an IVA so I can test with it
>>> >> > (although, I'm not sure how well the kernel works on the am35xx these days).
>>> >> >
>>> >> > I'm a bit busy today but I'll try booting the am35xx tomorrow and if it
>>> >> > comes up, see what I can figure out.
>>> >>
>>> >> I think this issue is relevant to am3517 as you can see from this
>>> >> thread: http://thread.gmane.org/gmane.linux.ports.arm.omap/97903
>>> >> I could boot only with your patch http://www.spinics.net/lists/arm-kernel/msg168865.html
>>> >>
>>> >> I have such a system running, so if you have any other patches/ideas to test, I would do it.
>>> >
>>> > Yegor, since I've so far been unable to get my am3517evm to fire up, can
>>> > you play around with the 3517 to see if there appears to be iva registers
>>> > that can be read/written to safely?  In particular, can the code that idles
>>> > the iva be run safely on an am3517?
>>>
>>> I'll look into this next week. am3517 and IVA seems to be a really big
>>> mystery. In the TI forum will be stated, there is no IVA:
>>> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/150961.aspx, but TRM
>>> has various appearances of IVA2 registers, but no real
>>> description/explanation of what is IVA and how to eat it.
>>
>> On 3703 it looks like the whole omap3_iva_idle() reset is needed, except
>> for setting the iva2 bootmode to idle. So I'm planning to merge the following
>> patch with just comments update this week unless somebody has a better fix
>> in mind.
>>
>> Regards,
>>
>> Tony
>>
>>
>> From: Tony Lindgren <tony at atomide.com>
>> Date: Tue, 14 May 2013 20:28:15 -0700
>> Subject: [PATCH] ARM: OMAP3: Fix iva2_pwrdm settings for 3703
>>
>> Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
>> changed PM to not access IVA registers on omaps that don't have
>> them. Turns out we still need to idle iva2 as otherwise
>> iva2_pwrdm will stay on and block deeper idle states.
>>
>> It seems that the only part of the reset that may not be needed
>> is the setting of the iva2 boot mode to idle. But as that register
>> seems to be there and is harmless if no iva2 is on the SoC, it's
>> probably safest to do the complete reset.
>>
>> Signed-off-by: Tony Lindgren <tony at atomide.com>
>
> Acked-by: Kevin Hilman <khilman at linaro.org>

Tested-by: Yegor Yefremov <yegorslists at googlemail.com>


From linus.walleij at stericsson.com  Wed May 22 04:12:11 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 May 2013 10:12:11 +0200
Subject: [PATCH] ARM: ux500: register LP5521 LEDs in the device tree
Message-ID: <1369210331-18545-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Based on pending device tree support in the LP55xx drivers
we can add the correct LED and channel configuration from the
ux500 device tree for all HREF variants.

Cc: Milo Kim <Milo.Kim at ti.com>
Cc: Bryan Wu <cooloney at gmail.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/href.dtsi | 38 ++++++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index 62523f6..e315429 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -63,16 +63,42 @@
 		};
 
 		i2c at 80128000 {
-			lp5521 at 0x33 {
-				compatible = "lp5521";
+			lp5521 at 33 {
+				compatible = "national,lp5521";
 				reg = <0x33>;
+				label = "lp5521_pri";
+				clock-mode = /bits/ 8 <2>;
+				chan0 {
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+				};
+				chan1 {
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+				};
+				chan2 {
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+				};
 			};
-
-			lp5521 at 0x34 {
-				compatible = "lp5521";
+			lp5521 at 34 {
+				compatible = "national,lp5521";
 				reg = <0x34>;
+				label = "lp5521_sec";
+				clock-mode = /bits/ 8 <2>;
+				chan0 {
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+				};
+				chan1 {
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+				};
+				chan2 {
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+				};
 			};
-
 			bh1780 at 0x29 {
 				compatible = "rohm,bh1780gli";
 				reg = <0x33>;
-- 
1.7.11.3



From b32955 at freescale.com  Wed May 22 04:16:19 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 22 May 2013 16:16:19 +0800
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <20130521054323.GE3080@S2101-09.ap.freescale.net>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <1369039742-10893-2-git-send-email-b32955@freescale.com>
 <20130521054323.GE3080@S2101-09.ap.freescale.net>
Message-ID: <519C7ED3.3030004@freescale.com>

? 2013?05?21? 13:43, Shawn Guo ??:
> It seems we can find it out from "reg" property, so that we can save
> this property?
>
we may have several devices attaching to the weim, each device has its 
own CS index.
it's better to keep this property, make it more clear.

thanks
Huang Shijie



From b32955 at freescale.com  Wed May 22 04:30:03 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 22 May 2013 16:30:03 +0800
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <20130520131827.GB32299@pengutronix.de>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <1369039742-10893-2-git-send-email-b32955@freescale.com>
 <20130520131827.GB32299@pengutronix.de>
Message-ID: <519C820B.2080800@freescale.com>

? 2013?05?20? 21:18, Sascha Hauer ??:
> On Mon, May 20, 2013 at 04:48:57PM +0800, Huang Shijie wrote:
>> 			weim-cs-index.
>> +
>> +Example for an i.MX6q-sabreauto board:
>> +	weim: weim at 021b8000 {
>> +		compatible = "fsl,imx6q-weim";
>> +		reg =<0x021b8000 0x4000>;
>> +		interrupts =<0 14 0x04>;
>> +		clocks =<&clks 196>;
>> +		#address-cells =<2>;
> Why is address cells 2 in this example?
Must be set to 2 to allow memory address translation.
>> +		#size-cells =<1>;
>> +		ranges =<0 0 0x08000000 0x08000000>;
>> +
>> +		nor at 0,0 {
>> +			compatible = "cfi-flash";
>> +			reg =<0 0 0x02000000>;
>> +			#address-cells =<1>;
>> +			#size-cells =<1>;
>> +			bank-width =<2>;
>> +
>> +			weim-cs-index =<0>;
>> +			weim-cs-timing =<0x00620081 0x00000001 0x1C022000
>> +					0x0000C000 0x1404a38e 0x00000000>;
>> +			partition at 0 {
>> +				label = "U-Boot";
>> +				reg =<0x0 0x40000>;
>> +			};
>> +
>> +			partition at 40000 {
>> +				label = "U-Boot-ENV";
>> +				reg =<0x40000 0x10000>;
>> +				read-only;
>> +			};
>> +
>> +			partition at 50000 {
>> +				label = "Kernel";
>> +				reg =<0x50000 0x3b0000>;
>> +			};
> The partitions are unnecessary to understand the example. Please drop them.
okay.
>> +#define CS_TIMING_LEN 6
>> +#define CS_REG_RANGE  0x18
>> +/* Parse and set the timing for this device. */
>> +static int weim_timing(struct platform_device *pdev, struct device_node *np)
>> +{
>> +	struct imx_weim *weim = platform_get_drvdata(pdev);
>> +	u32 value[CS_TIMING_LEN];
>> +	u32 cs_idx;
>> +	int ret;
>> +	int i;
>> +
>> +	ret = of_property_read_u32(np, "weim-cs-index",&cs_idx);
>> +	if (ret)
>> +		goto weim_parse_err;
> It would be nice to check for cs_idx being valid.
>
>> +
>> +	ret = of_property_read_u32_array(np, "weim-cs-timing",
>> +					value, CS_TIMING_LEN);
>> +	if (ret)
>> +		goto weim_parse_err;
>> +
>> +	/* set the timing for WEIM */
>> +	for (i = 0; i<  CS_TIMING_LEN; i++)
>> +		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
>> +	return 0;
>> +
>> +weim_parse_err:
>> +	return ret;
>> +}
>> +
>> +static int weim_parse_dt(struct platform_device *pdev)
>> +{
>> +	struct device_node *child;
>> +	int ret;
>> +
>> +	/* We only support the Parallel NOR now. We may add more in future. */
>> +	child = of_find_node_by_name(NULL, "nor");
>> +	if (child) {
>> +		ret = weim_timing(pdev, child);
>> +		if (ret)
>> +			goto parse_fail;
>> +
>> +		if (!of_platform_device_create(child, NULL,&pdev->dev)) {
>> +			ret = -EINVAL;
>> +			goto parse_fail;
>> +		}
>> +	}
> What you want to do here is:
>
> - iterate over your child nodes
> - call weim_timing() for each of them
> - call of_platform_device_create for each child (or even
>    of_platform_populate() with the parent node)
>
yes.
>> +	return 0;
>> +
>> +parse_fail:
>> +	return ret;
>> +}
>> +
>> +static int weim_probe(struct platform_device *pdev)
>> +{
>> +	struct imx_weim *weim;
>> +	struct resource *res;
>> +	int ret = -EINVAL;
>> +
>> +	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
>> +	if (!weim) {
>> +		ret = -ENOMEM;
>> +		goto weim_err;
>> +	}
>> +	platform_set_drvdata(pdev, weim);
>> +
>> +	/* get the resource */
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	if (!res) {
>> +		ret = -ENOENT;
>> +		goto weim_err;
>> +	}
> No need to do error checking here. devm_ioremap_resource() will do this
> for you and also print an error message.
>
>> +
>> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
>> +	if (IS_ERR(weim->base)) {
>> +		ret = PTR_ERR(weim->base);
>> +		goto weim_err;
>> +	}
>> +
>> +	/* get the clock */
>> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
>> +	if (IS_ERR(weim->clk))
>> +		goto weim_err;
>> +
>> +	clk_prepare_enable(weim->clk);
> what is this clock used for? Is it necessary for the register access or
> is it necessary for the chipselects on the WEIM to work?
>
>
yes. We need this clock.

in actually, this clock is just a clock gate for several clocks, 
including clock for register access, and
other necessary clocks.

thanks
Huang Shijie
.








From LW at KARO-electronics.de  Wed May 22 04:36:33 2013
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Wed, 22 May 2013 10:36:33 +0200
Subject: [PATCH] ARM: iomux-mx51: Always define
 PU E for pins used as GPIO
In-Reply-To: <1369207056.596630214@f96.mail.ru>
References: <1369124845-19244-1-git-send-email-shc_work@mail.ru>
 <1369203552.559574351@f389.i.mail.ru>
 <20892.28064.82907.942799@ipc1.ka-ro>
 <1369207056.596630214@f96.mail.ru>
Message-ID: <20892.33681.753710.620640@ipc1.ka-ro>

Hi,

Alexander Shiyan writes:
> > Alexander Shiyan writes:
> > > > On Tue, May 21, 2013 at 12:27:25PM +0400, Alexander Shiyan wrote:
> > > > > This patch adds a PUE bit for pins which used as GPIO. This allow
> > > > > to use the GPIOs correctly as inputs when source is open-drain with
> > > > > external pullup resistor (IRQ open-drain outputs for example).
> > > > 
> > > > I don't understand. If there's an external pullup why do you want to
> > > > turn on the internal one?
> > > 
> > > It is just switch off keeper circuit.
> > > 
> > If you want to switch the keeper circuit off why don't you do that by
> > removing PAD_CTL_PKE rather than adding PAD_CTL_PUE?
> 
> Again, I do not know which the solution here is better. If we remove
> the PKE bit, for some pins it will be removed the default pullup/pulldown (PUS = 0),
> so it may affect the some running configuration.
> 
IMO the current approach of defining the pad config with the pad
definition is broken anyway. It would be much better to specify the
pad configuration at the point where a specific pad is used, rather
than where it is defined.
The pin mux setting for a specific function of a pin is always the
same for any platform but the pad config may be different for
different platforms.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From catalin.marinas at arm.com  Wed May 22 04:42:14 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 May 2013 09:42:14 +0100
Subject: [PATCH v4 21/32] arm64: KVM: Build system integration
In-Reply-To: <850310439.5245685.1369152587054.JavaMail.root@redhat.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>
 <20130521154227.GM27002@arm.com>
 <850310439.5245685.1369152587054.JavaMail.root@redhat.com>
Message-ID: <20130522084214.GB14322@arm.com>

On Tue, May 21, 2013 at 05:09:47PM +0100, Paolo Bonzini wrote:
> 
> 
> ----- Messaggio originale -----
> > Da: "Catalin Marinas" <catalin.marinas at arm.com>
> > A: "Marc Zyngier" <Marc.Zyngier at arm.com>
> > Cc: linux-arm-kernel at lists.infradead.org, kvmarm at lists.cs.columbia.edu, kvm at vger.kernel.org, "Will Deacon"
> > <Will.Deacon at arm.com>, pbonzini at redhat.com, gleb at redhat.com, "Christopher Covington" <cov at codeaurora.org>
> > Inviato: Marted?, 21 maggio 2013 17:42:27
> > Oggetto: Re: [PATCH v4 21/32] arm64: KVM: Build system integration
> > 
> > On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote:
> > > --- /dev/null
> > > +++ b/arch/arm64/kvm/Kconfig
> > ...
> > > +config KVM_ARM_VGIC
> > > +        bool
> > > +	depends on KVM_ARM_HOST && OF
> > > +	select HAVE_KVM_IRQCHIP
> > > +	---help---
> > > +	  Adds support for a hardware assisted, in-kernel GIC emulation.
> > > +
> > > +config KVM_ARM_TIMER
> > > +        bool
> > > +	depends on KVM_ARM_VGIC
> > > +	select HAVE_KVM_IRQCHIP
> > > +	---help---
> > > +	  Adds support for the Architected Timers in virtual machines
> > > +
> > > +source drivers/virtio/Kconfig
> > 
> > Shouldn't the above configs go to drivers/virtio/Kconfig as well (or
> > drivers/virtio/arm/Kconfig)?
> 
> virtio doesn't mean "virtual versions of devices that also exist in
> hardware"; those are indeed in arch/ARCH/kvm.  virtio is a specific bus
> for paravirtualized devices.  It is not KVM-specific and the code runs
> in the guest (whereas arch/arm64/kvm/Kconfig is host code).

You are right. What I meant was kvm/virt/arm/Kconfig (the place where
the vgic and timer driver goes).

-- 
Catalin


From catalin.marinas at arm.com  Wed May 22 04:43:28 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 May 2013 09:43:28 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130521180201.GB26251@mudshark.cambridge.arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <20130520142459.GN31359@mudshark.cambridge.arm.com>
 <20130520151158.GA3520@MacBook-Pro.local>
 <20130520160407.GS31359@mudshark.cambridge.arm.com>
 <20130520171349.GM3639@MacBook-Pro.local>
 <20130521180201.GB26251@mudshark.cambridge.arm.com>
Message-ID: <20130522084328.GC14322@arm.com>

On Tue, May 21, 2013 at 07:02:01PM +0100, Will Deacon wrote:
> On Mon, May 20, 2013 at 06:13:52PM +0100, Catalin Marinas wrote:
> > On Mon, May 20, 2013 at 05:04:07PM +0100, Will Deacon wrote:
> > > On Mon, May 20, 2013 at 04:11:58PM +0100, Catalin Marinas wrote:
> > > > Given that the ARM ARM isn't clear (though this is the case on the
> > > > actual implementations), user space may not necessarily assume that
> > > > LPAE==atomic doubles. That's why I think reporting the actual atomic
> > > > feature is better.
> > > 
> > > The ARM ARM isn't too bad: it's just avoiding mandating 64-bit-wide paths
> > > around the entire SoC (and I've checked this with the architects). The only
> > > way we can probe this feature is using the MMFR0 and checking if LPAE is
> > > supported, and that's exactly what userspace will need to rely on.
> > 
> > Well, LPAE implies atomic doubles but I wouldn't say that's the "only"
> > way, it can always be a feature of the CPU. Now, would the user
> > developers fully understand the implications of LPAE?
> 
> I don't think it *can* be a feature of the CPU, because it depends on
> system-wide support. It could be a feature of an SoC, but per-SoC hwcaps
> isn't something we currently support. As I said, the only reason we can even
> probe this is because the architecture helps us out.

LPAE is also a feature of the CPU, not the SoC.

-- 
Catalin


From pbonzini at redhat.com  Wed May 22 04:45:08 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Wed, 22 May 2013 10:45:08 +0200
Subject: [PATCH v4 21/32] arm64: KVM: Build system integration
In-Reply-To: <20130522084214.GB14322@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-22-git-send-email-marc.zyngier@arm.com>
 <20130521154227.GM27002@arm.com>
 <850310439.5245685.1369152587054.JavaMail.root@redhat.com>
 <20130522084214.GB14322@arm.com>
Message-ID: <519C8594.3050305@redhat.com>

Il 22/05/2013 10:42, Catalin Marinas ha scritto:
> On Tue, May 21, 2013 at 05:09:47PM +0100, Paolo Bonzini wrote:
>>
>>
>> ----- Messaggio originale -----
>>> Da: "Catalin Marinas" <catalin.marinas at arm.com>
>>> A: "Marc Zyngier" <Marc.Zyngier at arm.com>
>>> Cc: linux-arm-kernel at lists.infradead.org, kvmarm at lists.cs.columbia.edu, kvm at vger.kernel.org, "Will Deacon"
>>> <Will.Deacon at arm.com>, pbonzini at redhat.com, gleb at redhat.com, "Christopher Covington" <cov at codeaurora.org>
>>> Inviato: Marted?, 21 maggio 2013 17:42:27
>>> Oggetto: Re: [PATCH v4 21/32] arm64: KVM: Build system integration
>>>
>>> On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote:
>>>> --- /dev/null
>>>> +++ b/arch/arm64/kvm/Kconfig
>>> ...
>>>> +config KVM_ARM_VGIC
>>>> +        bool
>>>> +	depends on KVM_ARM_HOST && OF
>>>> +	select HAVE_KVM_IRQCHIP
>>>> +	---help---
>>>> +	  Adds support for a hardware assisted, in-kernel GIC emulation.
>>>> +
>>>> +config KVM_ARM_TIMER
>>>> +        bool
>>>> +	depends on KVM_ARM_VGIC
>>>> +	select HAVE_KVM_IRQCHIP
>>>> +	---help---
>>>> +	  Adds support for the Architected Timers in virtual machines
>>>> +
>>>> +source drivers/virtio/Kconfig
>>>
>>> Shouldn't the above configs go to drivers/virtio/Kconfig as well (or
>>> drivers/virtio/arm/Kconfig)?
>>
>> virtio doesn't mean "virtual versions of devices that also exist in
>> hardware"; those are indeed in arch/ARCH/kvm.  virtio is a specific bus
>> for paravirtualized devices.  It is not KVM-specific and the code runs
>> in the guest (whereas arch/arm64/kvm/Kconfig is host code).
> 
> You are right. What I meant was kvm/virt/arm/Kconfig (the place where
> the vgic and timer driver goes).

Ah yeah, that could make sense.

Paolo



From catalin.marinas at arm.com  Wed May 22 04:47:44 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 May 2013 09:47:44 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <CAL_JsqLSC2QgMdTGtH5G_F5SYjA3Hs--jMmxBES=fqGLwapptQ@mail.gmail.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <CAL_JsqLSC2QgMdTGtH5G_F5SYjA3Hs--jMmxBES=fqGLwapptQ@mail.gmail.com>
Message-ID: <20130522084744.GD14322@arm.com>

On Tue, May 21, 2013 at 07:48:35PM +0100, Rob Herring wrote:
> On Mon, May 20, 2013 at 9:18 AM, Catalin Marinas
> <catalin.marinas at arm.com> wrote:
> > On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
> >> CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
> >> userspace software can avoid having to use the exclusive variants of
> >> these instructions if they wish.
> >>
> >> This patch advertises the atomicity of these instructions via the
> >> hwcaps, so userspace can detect this CPU feature.
> >>
> >> Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
> >> Signed-off-by: Will Deacon <will.deacon at arm.com>
> > ...
> >> +
> >> +     /* LPAE implies atomic ldrd/strd instructions */
> >> +     vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
> >> +     if (vmsa >= 5)
> >> +             elf_hwcap |= HWCAP_LPAE;
> >
> > As I mentioned in the past, I don't agree with exposing the "LPAE"
> > feature to user-space, it's not a feature that user space should care
> > about. An atomic double hwcap is better and you can even make this per
> > CPU via __v7_proc.
> 
> How does userspace know whether to install a non-LPAE or LPAE kernel
> in a generic way?

This is a valid reason to expose LPAE to user, though elf_hwcap sounds a
bit strange.

-- 
Catalin


From R64188 at freescale.com  Wed May 22 04:59:20 2013
From: R64188 at freescale.com (Jin Zhengxiong-R64188)
Date: Wed, 22 May 2013 08:59:20 +0000
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
 <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
Message-ID: <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>

> Subject: Re: [PATCH v3] tty: serial: add Freescale lpuart driver support
> 
> On 22 May 2013 14:40, Jin Zhengxiong-R64188 <R64188 at freescale.com> wrote:
> > [Jason Jin-R64188] Reuse the same LPUART on LS-1 with the compatible
> strings 'fsl,mvf600-lpuart' is technically OK, But it will fuss the route
> map of the product Line. The general name can show that the IP is shared
> between several product lines, and the history for which SOC firstly used
> the IP is not very important. With general compatible name, We can setup
> the general dts for the shared IPs.
> >
> > That's also the case for the IPs used on Power platform, Take the IFC
> for example, this IP implemented on Power platform will also be reused
> LS-1, The compatible string is set as  "fsl,ifc", "simple-bus" but not
> the soc name on which the IP first used.
> >
> >  Another example, though a little different, the nor flash driver,
> which is used for many platform, the compatible "cfi-flash" will be more
> reasonable than the soc/board name.
> >
> > With the general name for the compatible string in the driver, if there
> is minor difference for the different implementation of the same IP, we
> can add the soc related compatible string to the driver to pass
> different .data structure for that soc.
> >
> 
> As I already said, a generic compatible string does not specify anything
> about compatibility/version, and hence it's not a good compatible for IP
> block which is possibly to be integrated on multiple SoCs with slight
> differences.
> 
> For example, if there is a new SoC mvf900 integrating the IP with
> everything compatible to the version used on mvf600,
> 
>   compatible = <fsl,mvf900-uart>, <fsl,mvf600-uart>;
>   compatible = <fsl,mvf900-uart>, <fsl,lpuart>;
> 
> which one do you think is better to tell the compatibility/version?
> 
> Shawn
[Jason Jin-R64188] For the lpuart itself, I do not think it will have different version IP. The general name is sufficient and soc related name can introduce the minor difference. If the there are update version, we can name it lpuart2.0 or something like that.

For the compatible property itself, the ePAPR described it as:
---- 
The compatible property value consists of one or more strings that define the specific programming model for the device. This list of strings should be used by a client program for device driver selection. The property value consists of a concatenated list of null terminated strings, from most specific to most general. 
----
So for the IPs especially for the peripheral IPs, the compatible just used to select the driver for the device. It should not used to describe the version information. If the version changed and the driver cannot be used for the device then another compatible strings should be used.

As I said, Another reason for the general strings used is the across platform issue, It's maybe reasonably to name the compatible strings as you recommended for the IPs share in the same SoC family. But for the IPs shared across platform, general name sound more reasonably to avoid the product line confusing. 

The compatible strings once named as you said for Power platform, but more general strings were used later as IPs shared for more SoCs.

I was wondering what's kind of strings should be used for this kind of IPs across different platforms. I added Grant Likely for comments, Thanks.

Jason 



From pdeschrijver at nvidia.com  Wed May 22 05:03:04 2013
From: pdeschrijver at nvidia.com (Peter De Schrijver)
Date: Wed, 22 May 2013 12:03:04 +0300
Subject: [PATCH] ARM: tegra: add cpu_disable for hotplug
In-Reply-To: <519B9DB4.7070106@wwwdotorg.org>
References: <1369131215-2920-1-git-send-email-josephl@nvidia.com>
 <519B9DB4.7070106@wwwdotorg.org>
Message-ID: <20130522090304.GT21944@tbergstrom-lnx.Nvidia.com>

On Tue, May 21, 2013 at 06:15:48PM +0200, Stephen Warren wrote:
> On 05/21/2013 04:13 AM, Joseph Lo wrote:
> > The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
> > support that. Adding a Tegra specific cpu_disable function for it.
> > 
> > Signed-off-by: Joseph Lo <josephl at nvidia.com>
> 
> > diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
> 
> > +int tegra_cpu_disable(unsigned int cpu)
> > +{
> > +	switch (tegra_chip_id) {
> > +	case TEGRA114:
> > +		return 0;
> > +	default:
> > +		return cpu == 0 ? -EPERM : 0;
> > +	}
> > +}
> 
> Do we expect all/most future chips to support hotplug of CPU0? Or at
> least, fewer chips to have the restriction than not? If so, it might be

Yes. I think we can safely assume future chips will support hotplugging CPU0.

> more forward-looking to write that as:
> 
> if (tegra_chip_id == TEGRA30)
>     return cpu == 0 ? -EPERM : 0;
> 

Also Tegra20 doesn't support hotplugging CPU0?

Cheers,

Peter.


From peterz at infradead.org  Wed May 22 05:11:56 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Wed, 22 May 2013 11:11:56 +0200
Subject: [PATCH] kernel/sched/core.c: need return NULL when BUG() is
 defined as empty.
In-Reply-To: <5199D565.4070307@asianux.com>
References: <5199D565.4070307@asianux.com>
Message-ID: <20130522091156.GC18810@twins.programming.kicks-ass.net>

On Mon, May 20, 2013 at 03:48:53PM +0800, Chen Gang wrote:
> 
> When neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, need let function
> return failure value ('NULL') instead of random value.

What will such a kernel do? Happily continue running whenever we hit a
BUG? that seems like a particularly bad idea. Should we not have a stub
BUG() function like:

void BUG(void) __attribute__((noreturn))
{
	local_irq_disable();
	while (1) ;
}

Which would at least halt things?


From g.liakhovetski at gmx.de  Wed May 22 05:12:37 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 22 May 2013 11:12:37 +0200 (CEST)
Subject: [PATCH 2/2] ARM: shmobile: r8a73a4: implement CPU clock scaling for
 CPUFreq
In-Reply-To: <Pine.LNX.4.64.1305221108500.12715@axis700.grange>
References: <Pine.LNX.4.64.1305221108500.12715@axis700.grange>
Message-ID: <Pine.LNX.4.64.1305221111210.12715@axis700.grange>

This patch adds support for the Z-clock on r8a73a4 SoCs, which is driving
the Cortex A15 core, and a "cpufreq-cpu0" platform device. Adding an
"operating-points" property to the CPU0 DT node and a regulator, this
patch allows platforms to use the generic cpufreq-cpu0 driver to use
SoC's DVFS capabilities.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---
 arch/arm/mach-shmobile/Kconfig         |    2 +
 arch/arm/mach-shmobile/clock-r8a73a4.c |  123 +++++++++++++++++++++++++++++++-
 arch/arm/mach-shmobile/setup-r8a73a4.c |    1 +
 3 files changed, 125 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 97bc6cf..ec349ad 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -26,6 +26,8 @@ config ARCH_R8A73A4
 	select ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_OPP
 
 config ARCH_R8A7740
 	bool "R-Mobile A1 (R8A77400)"
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index d5176d0..824789c 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -34,6 +34,7 @@
 
 #define FRQCRA		0xE6150000
 #define FRQCRB		0xE6150004
+#define FRQCRC		0xE61500E0
 #define VCLKCR1		0xE6150008
 #define VCLKCR2		0xE615000C
 #define VCLKCR3		0xE615001C
@@ -52,6 +53,7 @@
 #define HSICKCR		0xE615026C
 #define M4CKCR		0xE6150098
 #define PLLECR		0xE61500D0
+#define PLL0CR		0xE61500D8
 #define PLL1CR		0xE6150028
 #define PLL2CR		0xE615002C
 #define PLL2SCR		0xE61501F4
@@ -177,6 +179,7 @@ static struct sh_clk_ops pll_clk_ops = {
 		.mapping	= &cpg_mapping,		\
 	}
 
+PLL_CLOCK(pll0_clk,  &main_clk,      pll_parent_main,      1, 20, PLL0CR,  0);
 PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
 PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
 PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
@@ -184,6 +187,14 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 
 SH_FIXED_RATIO_CLK(pll1_div2_clk,	pll1_clk,	div2);
 
+static atomic_t frqcr_lock;
+
+/* Several clocks need to access FRQCRB, have to lock */
+static bool frqcr_kick_check(struct clk *clk)
+{
+	return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
+}
+
 static int frqcr_kick_do(struct clk *clk)
 {
 	int i;
@@ -199,6 +210,107 @@ static int frqcr_kick_do(struct clk *clk)
 	return -ETIMEDOUT;
 }
 
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	void __iomem *frqcrc;
+	int ret;
+	unsigned long step, p_rate;
+	u32 val;
+
+	if (!clk->parent || !__clk_get(clk->parent))
+		return -ENODEV;
+
+	if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
+		ret = -EBUSY;
+		goto done;
+	}
+
+	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
+	p_rate = clk_get_rate(clk->parent);
+	if (rate == p_rate) {
+		val = 0;
+	} else {
+		step = DIV_ROUND_CLOSEST(p_rate, 32);
+		val = 32 - rate / step;
+	}
+
+	iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
+		  (val << clk->enable_bit), frqcrc);
+
+	ret = frqcr_kick_do(clk);
+
+done:
+	atomic_dec(&frqcr_lock);
+	__clk_put(clk->parent);
+	return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	/*
+	 * theoretical rate = parent rate * multiplier / 32,
+	 * where 1 <= multiplier <= 32. Therefore we should do
+	 * multiplier = rate * 32 / parent rate
+	 * rounded rate = parent rate * multiplier / 32.
+	 * However, multiplication before division won't fit in 32 bits, so
+	 * we sacrifice some precision by first dividing and then multiplying.
+	 * To find the nearest divisor we calculate both and pick up the best
+	 * one. This avoids 64-bit arithmetics.
+	 */
+	unsigned long step, mul_min, mul_max, rate_min, rate_max;
+
+	rate_max = clk_get_rate(clk->parent);
+
+	/* output freq <= parent */
+	if (rate >= rate_max)
+		return rate_max;
+
+	step = DIV_ROUND_CLOSEST(rate_max, 32);
+	/* output freq >= parent / 32 */
+	if (step >= rate)
+		return step;
+
+	mul_min = rate / step;
+	mul_max = DIV_ROUND_UP(rate, step);
+	rate_min = step * mul_min;
+	if (mul_max == mul_min)
+		return rate_min;
+
+	rate_max = step * mul_max;
+
+	if (rate_max - rate <  rate - rate_min)
+		return rate_max;
+
+	return rate_min;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+	void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
+	unsigned int max = clk->div_mask + 1;
+	unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
+			     clk->div_mask);
+
+	return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
+		(max - val);
+}
+
+static struct sh_clk_ops zclk_ops = {
+	.recalc = zclk_recalc,
+	.set_rate = zclk_set_rate,
+	.round_rate = zclk_round_rate,
+};
+
+static struct clk z_clk = {
+	.parent = &pll0_clk,
+	.div_mask = 0x1f,
+	.enable_bit = 8,
+	/* We'll need to access FRQCRB and FRQCRC */
+	.enable_reg = (void __iomem *)FRQCRB,
+	.ops = &zclk_ops,
+};
+
 static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,
@@ -210,17 +322,21 @@ static struct clk *main_clks[] = {
 	&main_div2_clk,
 	&fsiack_clk,
 	&fsibck_clk,
+	&pll0_clk,
 	&pll1_clk,
 	&pll1_div2_clk,
 	&pll2_clk,
 	&pll2s_clk,
 	&pll2h_clk,
+	&z_clk,
 };
 
 /* DIV4 */
 static void div4_kick(struct clk *clk)
 {
-	frqcr_kick_do(clk);
+	if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
+		frqcr_kick_do(clk);
+	atomic_dec(&frqcr_lock);
 }
 
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
@@ -396,6 +512,9 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("pll2s",			&pll2s_clk),
 	CLKDEV_CON_ID("pll2h",			&pll2h_clk),
 
+	/* CPU clock */
+	CLKDEV_DEV_ID("cpufreq-cpu0",		&z_clk),
+
 	/* DIV6 */
 	CLKDEV_CON_ID("zb",			&div6_clks[DIV6_ZB]),
 	CLKDEV_CON_ID("vck1",			&div6_clks[DIV6_VCK1]),
@@ -439,6 +558,8 @@ void __init r8a73a4_clock_init(void)
 	int k, ret = 0;
 	u32 ckscr;
 
+	atomic_set(&frqcr_lock, -1);
+
 	reg = ioremap_nocache(CKSCR, PAGE_SIZE);
 	BUG_ON(!reg);
 	ckscr = ioread32(reg);
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c5a75a7..7265e14 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -185,6 +185,7 @@ void __init r8a73a4_add_standard_devices(void)
 #ifdef CONFIG_USE_OF
 void __init r8a73a4_add_standard_devices_dt(void)
 {
+	platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.7.2.5



From g.liakhovetski at gmx.de  Wed May 22 05:12:33 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 22 May 2013 11:12:33 +0200 (CEST)
Subject: [PATCH 1/2] ARM: shmobile: r8a73a4: wait for completion when kicking
 the clock
Message-ID: <Pine.LNX.4.64.1305221108500.12715@axis700.grange>

To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to
be set and to make sure the setting has taken effect, it has to be read
back repeatedly until it is cleared by the hardware. This patch adds the
waiting part, that was missing until now.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   22 ++++++++++++++++------
 1 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5f7fe62..d5176d0 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -184,6 +184,21 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 
 SH_FIXED_RATIO_CLK(pll1_div2_clk,	pll1_clk,	div2);
 
+static int frqcr_kick_do(struct clk *clk)
+{
+	int i;
+
+	/* set KICK bit in FRQCRB to update hardware setting, check success */
+	iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
+	for (i = 1000; i; i--)
+		if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
+			cpu_relax();
+		else
+			return 0;
+
+	return -ETIMEDOUT;
+}
+
 static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,
@@ -205,12 +220,7 @@ static struct clk *main_clks[] = {
 /* DIV4 */
 static void div4_kick(struct clk *clk)
 {
-	unsigned long value;
-
-	/* set KICK bit in FRQCRB to update hardware setting */
-	value = ioread32(CPG_MAP(FRQCRB));
-	value |= (1 << 31);
-	iowrite32(value, CPG_MAP(FRQCRB));
+	frqcr_kick_do(clk);
 }
 
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
-- 
1.7.2.5



From arnd at arndb.de  Wed May 22 05:25:36 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 11:25:36 +0200
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <201305221125.36284.arnd@arndb.de>

On Thursday 16 May 2013, Michael S. Tsirkin wrote:
> This improves the might_fault annotations used
> by uaccess routines:
> 
> 1. The only reason uaccess routines might sleep
>    is if they fault. Make this explicit for
>    all architectures.
> 2. Accesses (e.g through socket ops) to kernel memory
>    with KERNEL_DS like net/sunrpc does will never sleep.
>    Remove an unconditinal might_sleep in the inline
>    might_fault in kernel.h
>    (used when PROVE_LOCKING is not set).
> 3. Accesses with pagefault_disable return EFAULT
>    but won't cause caller to sleep.
>    Check for that and avoid might_sleep when
>    PROVE_LOCKING is set.
> 
> I'd like these changes to go in for the benefit of
> the vhost driver where we want to call socket ops
> under a spinlock, and fall back on slower thread handler
> on error.

Hi Michael,

I have recently stumbled over a related topic, which is the highly
inconsistent placement of might_fault() or might_sleep() in certain
classes of uaccess functions. Your patches seem completely reasonable,
but it would be good to also fix the other problem, at least on
the architectures we most care about.

Given the most commonly used functions and a couple of architectures
I'm familiar with, these are the ones that currently call might_fault()

			x86-32	x86-64	arm	arm64	powerpc	s390	generic
copy_to_user		-	x	-	-	-	x	x
copy_from_user		-	x	-	-	-	x	x
put_user		x	x	x	x	x	x	x
get_user		x	x	x	x	x	x	x
__copy_to_user		x	x	-	-	x	-	-
__copy_from_user	x	x	-	-	x	-	-
__put_user		-	-	x	-	x	-	-
__get_user		-	-	x	-	x	-	-

WTF?

Calling might_fault() for every __get_user/__put_user is rather expensive
because it turns what should be a single instruction (plus fixup) into an
external function call.

My feeling is that we should do might_fault() only in access_ok() to get
the right balance.

	Arnd


From gang.chen at asianux.com  Wed May 22 05:29:51 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Wed, 22 May 2013 17:29:51 +0800
Subject: [PATCH] kernel/sched/core.c: need return NULL when BUG() is
 defined as empty.
In-Reply-To: <20130522091156.GC18810@twins.programming.kicks-ass.net>
References: <5199D565.4070307@asianux.com>
 <20130522091156.GC18810@twins.programming.kicks-ass.net>
Message-ID: <519C900F.1040008@asianux.com>

On 05/22/2013 05:11 PM, Peter Zijlstra wrote:
> On Mon, May 20, 2013 at 03:48:53PM +0800, Chen Gang wrote:
>> > 
>> > When neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, need let function
>> > return failure value ('NULL') instead of random value.
> What will such a kernel do? Happily continue running whenever we hit a
> BUG? that seems like a particularly bad idea. Should we not have a stub
> BUG() function like:
> 
> void BUG(void) __attribute__((noreturn))
> {
> 	local_irq_disable();
> 	while (1) ;
> }
> 
> Which would at least halt things?
> 
> 

At least for me, it is a good idea. :-)

In menuconfig we can set !CONFIG_BUG and !HAVE_ARCH_BUG manually under
any architectures:

  "> General setup > Configure standard kernel features (expert users) > BUG() Support"

So I think, we really need your patch.


Thanks.
-- 
Chen Gang

Asianux Corporation


From sebastian.hesselbarth at gmail.com  Wed May 22 05:43:15 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 11:43:15 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130521174849.GL26249@lunn.ch>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch>
Message-ID: <519C9333.20609@gmail.com>

On 05/21/2013 07:48 PM, Andrew Lunn wrote:
> On Tue, May 21, 2013 at 06:41:44PM +0200, Sebastian Hesselbarth wrote:
>> This patch adds orion-eth and mvmdio device tree nodes for DT enabled
>> Dove boards. As there is only one ethernet controller on Dove, a default
>> phy node is also added with a note to set its reg property on a per-board
>> basis.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>> ---
...
>> +			ethernet-port at 0 {
>> +				device_type = "network";
>> +				compatible = "marvell,orion-eth-port";
>> +				reg =<0>;
>> +				interrupts =<29>;
>> +				/* overwrite MAC address in bootloader */
>> +				local-mac-address = [00 00 00 00 00 00];
>
> Hi Sebastian
>
> Its probably a good idea to set the local administration bit in this
> MAC address. i.e. first byte is 02.

Andrew,

we just need an invalid address here to trigger the default behavior of
the driver and load the MAC address from its register. As PPC binding
documentation also has all zero, I just took it.

Sebastian


From catalin.marinas at arm.com  Wed May 22 05:47:41 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 May 2013 10:47:41 +0100
Subject: [PATCH v2 0/4] dma-mapping: Define dma_{alloc,free}_attrs()
 for all archs
In-Reply-To: <519C2F5D.8000809@igel.co.jp>
References: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
 <519C2F5D.8000809@igel.co.jp>
Message-ID: <20130522094741.GE14322@arm.com>

On Wed, May 22, 2013 at 03:37:17AM +0100, Damian Hobson-Garcia wrote:
> Hello,
> On 2013/04/30 12:01, Damian Hobson-Garcia wrote:
> > Most architectures that define CONFIG_HAVE_DMA=y, have implementations for
> > both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
> > not define CONFIG_HAVE_DMA also have both of these definitions provided by
> > dma-mapping-broken.h.

BTW, shouldn't this be called CONFIG_HAVE_DMA_ATTRS?

> > Provide a default definition for the archs that define CONFIG_HAVE_DMA=y,
> > but have no implementation for dma_{alloc,free}_attrs(). 
> > 
> > As I don't have hardware for any of these systems, the patches are only
> > compile-tested where I could (arm64, s390) and untested for the archs
> > where I couldn't find a readily available prebuilt cross-compiler (c6x, parisc).
> 
> >  arch/arm64/include/asm/dma-mapping.h  |   17 +++++++++++------
> >  arch/c6x/include/asm/dma-mapping.h    |    3 +++
> >  arch/parisc/include/asm/dma-mapping.h |    3 +++
> >  arch/s390/include/asm/dma-mapping.h   |   17 +++++++++++------
> >  4 files changed, 28 insertions(+), 12 deletions(-)
> > 
> 
> Since this series spans several architectures, what would be the best
> way to have this patch series merged?
> Should I resubmit each patch to the mailing list for each architecture
> separately?

I'm happy to take the arm64 patch.

Thanks.

-- 
Catalin


From mst at redhat.com  Wed May 22 05:47:09 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 12:47:09 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130521115734.GA9554@twins.programming.kicks-ass.net>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <20130521115734.GA9554@twins.programming.kicks-ass.net>
Message-ID: <20130522094709.GA26451@redhat.com>

On Tue, May 21, 2013 at 01:57:34PM +0200, Peter Zijlstra wrote:
> On Sun, May 19, 2013 at 12:35:26PM +0300, Michael S. Tsirkin wrote:
> > > > --- a/include/linux/kernel.h
> > > > +++ b/include/linux/kernel.h
> > > > @@ -198,7 +198,6 @@ void might_fault(void);
> > > >  #else
> > > >  static inline void might_fault(void)
> > > >  {
> > > > -	might_sleep();
> > > 
> > > This removes potential resched points for PREEMPT_VOLUNTARY -- was that
> > > intentional?
> > 
> > No it's a bug. Thanks for pointing this out.
> > OK so I guess it should be might_sleep_if(!in_atomic())
> > and this means might_fault would have to move from linux/kernel.h to
> > linux/uaccess.h, since in_atomic() is in linux/hardirq.h
> > 
> > Makes sense?
> 
> So the only difference between PROVE_LOCKING and not should be the
> might_lock_read() thing; so how about something like this?
> 
> ---
>  include/linux/kernel.h  |  7 ++-----
>  include/linux/uaccess.h | 26 ++++++++++++++++++++++++++
>  mm/memory.c             | 14 ++------------
>  3 files changed, 30 insertions(+), 17 deletions(-)
> 
> diff --git a/include/linux/kernel.h b/include/linux/kernel.h
> index e96329c..70812f4 100644
> --- a/include/linux/kernel.h
> +++ b/include/linux/kernel.h
> @@ -194,12 +194,9 @@ extern int _cond_resched(void);
>  	})
>  
>  #ifdef CONFIG_PROVE_LOCKING
> -void might_fault(void);
> +void might_fault_lockdep(void);
>  #else
> -static inline void might_fault(void)
> -{
> -	might_sleep();
> -}
> +static inline void might_fault_lockdep(void) { }
>  #endif
>  
>  extern struct atomic_notifier_head panic_notifier_list;
> diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
> index 5ca0951..50a2cc9 100644
> --- a/include/linux/uaccess.h
> +++ b/include/linux/uaccess.h
> @@ -38,6 +38,32 @@ static inline void pagefault_enable(void)
>  	preempt_check_resched();
>  }
>  
> +static inline bool __can_fault(void)
> +{
> +	/*
> +	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
> +	 * holding the mmap_sem, this is safe because kernel memory doesn't
> +	 * get paged out, therefore we'll never actually fault, and the
> +	 * below annotations will generate false positives.
> +	 */
> +	if (segment_eq(get_fs(), KERNEL_DS))
> +		return false;
> +
> +	if (in_atomic() /* || pagefault_disabled() */)

One question here: I'm guessing you put this comment here
for illustrative purposes, implying code that will
be enabled in -rt?
We don't want it upstream I think, right?


> +		return false;
> +
> +	return true;
> +}
> +
> +static inline void might_fault(void)
> +{
> +	if (!__can_fault())
> +		return;
> +
> +	might_sleep();
> +	might_fault_lockdep();
> +}
> +
>  #ifndef ARCH_HAS_NOCACHE_UACCESS
>  
>  static inline unsigned long __copy_from_user_inatomic_nocache(void *to,
> diff --git a/mm/memory.c b/mm/memory.c
> index 6dc1882..266610c 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -4211,19 +4211,9 @@ void print_vma_addr(char *prefix, unsigned long ip)
>  }
>  
>  #ifdef CONFIG_PROVE_LOCKING
> -void might_fault(void)
> +void might_fault_lockdep(void)
>  {
>  	/*
> -	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
> -	 * holding the mmap_sem, this is safe because kernel memory doesn't
> -	 * get paged out, therefore we'll never actually fault, and the
> -	 * below annotations will generate false positives.
> -	 */
> -	if (segment_eq(get_fs(), KERNEL_DS))
> -		return;
> -
> -	might_sleep();
> -	/*
>  	 * it would be nicer only to annotate paths which are not under
>  	 * pagefault_disable, however that requires a larger audit and
>  	 * providing helpers like get_user_atomic.
> @@ -4231,7 +4221,7 @@ void might_fault(void)
>  	if (!in_atomic() && current->mm)
>  		might_lock_read(&current->mm->mmap_sem);
>  }
> -EXPORT_SYMBOL(might_fault);
> +EXPORT_SYMBOL(might_fault_lockdep);
>  #endif
>  
>  #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLBFS)


From B35083 at freescale.com  Wed May 22 05:47:37 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Wed, 22 May 2013 09:47:37 +0000
Subject: [PATCH v4] clocksource: add Vybrid Family pit timer support
In-Reply-To: <519B48F4.8050005@linaro.org>
References: <1369121274-9371-1-git-send-email-b35083@freescale.com>
 <519B48F4.8050005@linaro.org>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CBE88@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Daniel Lezcano [mailto:daniel.lezcano at linaro.org]
>Sent: Tuesday, May 21, 2013 6:14 PM
>To: Lu Jingchang-B35083
>Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
>john.stultz at linaro.org; tglx at linutronix.de; shawn.guo at linaro.org;
>s.hauer at pengutronix.de
>Subject: Re: [PATCH v4] clocksource: add Vybrid Family pit timer support
>
>On 05/21/2013 09:27 AM, Jingchang Lu wrote:
>> Add Freescale Vybrid Family period interrupt timer support.
>>
>> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
>> ---
>> v4:
>>   use family name names driver and symbol instead of SoC name.
>>   remove redundant code.
>>   use BUG_ON instead of WARN_ON.
>>   add necessory comment information.
>>
>>  drivers/clocksource/Kconfig         |   5 +
>>  drivers/clocksource/Makefile        |   1 +
>>  drivers/clocksource/mvf_pit_timer.c | 187
>> ++++++++++++++++++++++++++++++++++++
>>  3 files changed, 193 insertions(+)
>>  create mode 100644 drivers/clocksource/mvf_pit_timer.c
>
>[ ... ]
>
>> +
>> +static int pit_set_next_event(unsigned long delta,
>> +				struct clock_event_device *unused) {
>> +	/*
>> +	 * set a new value to PITLDVAL register will not restart the timer,
>> +	 * to abort the current cycle and start a timer period with the new
>> +	 * value, the timer must be disabled and enabled again.
>> +	 * and the PITLAVAL should be set to delta minus one.
>
>Why delta "minus one" ?
[Lu Jingchang-B35083] 
This is required by the PIT hardware, it is a down counter, the PITLAVAL register should be set to (delta-1), it will raise an interrupt when it counts down to 0. Thanks!
>
>> +	 */
>> +	pit_timer_disable();
>> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
>> +	pit_timer_enable();
>> +
>> +	return 0;
>> +}
>> +
>> +static void pit_set_mode(enum clock_event_mode mode,
>> +				struct clock_event_device *evt)
>> +{
>> +	switch (mode) {
>> +	case CLOCK_EVT_MODE_PERIODIC:
>> +		pit_timer_disable();
>> +		__raw_writel(cycle_per_jiffy - 1, clkevt_base + PITLDVAL);
>> +		pit_timer_enable();
>
>You can call pit_set_next_event(cycle_per_jiffy, evt) instead of adding
>redundant code, no ?
[Lu Jingchang-B35083] 
 Yes, I will do that. Thanks!
>
>> +		break;
>> +	default:
>> +		break;
>> +	}
>> +}
>
>[ ... ]
>
>> +
>> +static struct clock_event_device clockevent_pit = {
>> +	.name		= "MVF pit timer",
>> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
>> +	.set_mode	= pit_set_mode,
>> +	.set_next_event	= pit_set_next_event,
>> +	.rating		= 300,
>> +};
>> +
>> +static struct irqaction pit_timer_irq = {
>> +	.name		= "MVF pit timer",
>> +	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
>
>Did you take into account Thomas's comment ?
[Lu Jingchang-B35083] 
Sorry, I misunderstand Thomas's meaning, I will remove IRQF_DISABLED flag. Thanks! 
>
>> +	.handler	= pit_timer_interrupt,
>> +	.dev_id		= &clockevent_pit,
>> +};
>> +
>> +static int __init pit_clockevent_init(struct clk *pit_clk, int irq) {
>> +	unsigned int c = clk_get_rate(pit_clk);
>> +
>> +	__raw_writel(0, clkevt_base + PITTCTRL);
>> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
>> +
>> +	clockevent_pit.cpumask = cpumask_of(0);
>
>The irq initialization is missing.
>
>	clockevent_pit.irq = irq;
>
[Lu Jingchang-B35083] 
Yes, I will add this. Thanks!

>> +	clockevents_config_and_register(&clockevent_pit, c, 2, 0xffffffff);
>
>Is it possible to have a comment with the justification for these values ?
[Lu Jingchang-B35083] 
Yes, I will add a comment for these values. Thanks!
>
>> +
>> +	BUG_ON(setup_irq(irq, &pit_timer_irq));
>> +	return 0;
>
>Everything is ok if you can't setup your timer ?
>
>> +}
>> +
>> +static void __init pit_timer_init(struct device_node *np) {
>> +	struct clk *pit_clk;
>> +	void __iomem *timer_base;
>> +	int irq;
>> +
>> +	timer_base = of_iomap(np, 0);
>> +	BUG_ON(!timer_base);
>
>You raise a bug and then you go ahead setting up the address with an
>invalid value, leading to a random crash.
[Lu Jingchang-B35083] 
The BUG_ON() will call BUG() if condition is true. It will print the stack trace and the current process will die, it won't go ahead, won't it? Thanks! 
>
>> +	/*
>> +	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
>> +	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
>> +	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
>> +	 */
>> +	clksrc_base = timer_base + PITn_OFFSET(2);
>> +	clkevt_base = timer_base + PITn_OFFSET(3);
>> +
>> +	irq = irq_of_parse_and_map(np, 0);
>> +
>> +	pit_clk = of_clk_get(np, 0);
>> +	BUG_ON(IS_ERR(pit_clk));
>> +
>> +	BUG_ON(clk_prepare_enable(pit_clk));
>
>Same here.
>
>> +	cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
>> +
>> +	/* enable the pit module */
>> +	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
>> +
>> +	BUG_ON(pit_clocksource_init(pit_clk));
>> +
>> +	pit_clockevent_init(pit_clk, irq);
>
>Please, remove these BUG_ON, this is inconsistent especially with a one
>call init function. If pit_timer_init can't be initialized, just pr_err
>+ BUG.
[Lu Jingchang-B35083] 
Do you mean that I should not use the BUG_ON or I need print an error information by pr_err before BUG. Thanks!
>
>Thanks
>  -- Daniel
>
>
>--
> <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
>
>Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
><http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-
>blog/> Blog
>


From jhovold at gmail.com  Wed May 22 05:55:45 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Wed, 22 May 2013 11:55:45 +0200
Subject: [PATCH] v2 rtc-at91rm9200: add support for at91sam9x5
In-Reply-To: <519BF353.2060800@interlog.com>
References: <519BF353.2060800@interlog.com>
Message-ID: <20130522095545.GA11420@localhost>

On Tue, May 21, 2013 at 06:21:07PM -0400, Douglas Gilbert wrote:
> An unspecified number of SoCs from the Atmel's
> at91sam9x5 family including the at91sam9g25 have a
> broken AT91_RTC_IMR (interrupt mask) register which
> always returns zero.
> 
> If this bug can be neutralized, then the existing
> rtc-at91rm9200 driver will work. On the other hand,
> leaving this bug in place, and starting the RTC
> causes unhandled interrupts which result in the
> "SYS" interrupt being disabled. And that takes down
> several other interrupts wired or-ed through the
> SYS interrupt including the DBG port.
> 
> This is the second version of this patch, and is
> against lk 3.10.0-rc2 .

Your patch is almost identical to the one I submitted about two months
ago in this thread:

	https://lkml.org/lkml/2013/4/3/166

except that you do not use DT to the detect SoCs with broken IMR. (Your
patch is also lacking the register-read-back heuristic to make sure the
interrupts have been disabled before you update the mask.)

Are there sam9x5 SoCs with non-broken RTC_IMR which would prevent us
from using DT for detection? If so, I'd rather see your test for
broken-IMR implemented on top of my implementation.

Thanks,
Johan

> ChangeLog:
>     - checks in probe() function if AT91_RTC_IMR is broken.
>       If so, uses a shadow imr
>     - apart from that check, SoCs with a good IMR register
>       take the same paths through rtc-at91rm9200.c as before
>     - SoCs with a broken IMR take a spinlock while changing
>       the state of IER or IDR (and the shadow), mainly to
>       disable interrupts **.


From mst at redhat.com  Wed May 22 05:58:18 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 12:58:18 +0300
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <201305221125.36284.arnd@arndb.de>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
Message-ID: <20130522095818.GB24931@redhat.com>

On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> On Thursday 16 May 2013, Michael S. Tsirkin wrote:
> > This improves the might_fault annotations used
> > by uaccess routines:
> > 
> > 1. The only reason uaccess routines might sleep
> >    is if they fault. Make this explicit for
> >    all architectures.
> > 2. Accesses (e.g through socket ops) to kernel memory
> >    with KERNEL_DS like net/sunrpc does will never sleep.
> >    Remove an unconditinal might_sleep in the inline
> >    might_fault in kernel.h
> >    (used when PROVE_LOCKING is not set).
> > 3. Accesses with pagefault_disable return EFAULT
> >    but won't cause caller to sleep.
> >    Check for that and avoid might_sleep when
> >    PROVE_LOCKING is set.
> > 
> > I'd like these changes to go in for the benefit of
> > the vhost driver where we want to call socket ops
> > under a spinlock, and fall back on slower thread handler
> > on error.
> 
> Hi Michael,
> 
> I have recently stumbled over a related topic, which is the highly
> inconsistent placement of might_fault() or might_sleep() in certain
> classes of uaccess functions. Your patches seem completely reasonable,
> but it would be good to also fix the other problem, at least on
> the architectures we most care about.
> 
> Given the most commonly used functions and a couple of architectures
> I'm familiar with, these are the ones that currently call might_fault()
> 
> 			x86-32	x86-64	arm	arm64	powerpc	s390	generic
> copy_to_user		-	x	-	-	-	x	x
> copy_from_user		-	x	-	-	-	x	x
> put_user		x	x	x	x	x	x	x
> get_user		x	x	x	x	x	x	x
> __copy_to_user		x	x	-	-	x	-	-
> __copy_from_user	x	x	-	-	x	-	-
> __put_user		-	-	x	-	x	-	-
> __get_user		-	-	x	-	x	-	-
> 
> WTF?

Yea.

> Calling might_fault() for every __get_user/__put_user is rather expensive
> because it turns what should be a single instruction (plus fixup) into an
> external function call.

You mean _cond_resched with CONFIG_PREEMPT_VOLUNTARY? Or do you
mean when we build with PROVE_LOCKING?

> My feeling is that we should do might_fault() only in access_ok() to get
> the right balance.
> 
> 	Arnd

Well access_ok is currently non-blocking I think - we'd have to audit
all callers. There are some 200 of these in drivers and some
1000 total so ... a bit risky.

-- 
MST


From sebastian.hesselbarth at gmail.com  Wed May 22 06:01:29 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 12:01:29 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130521193803.GA20882@1wt.eu>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu>
Message-ID: <519C9779.1040104@gmail.com>

On 05/21/2013 09:38 PM, Willy Tarreau wrote:
> On Tue, May 21, 2013 at 12:33:25PM +0200, Thomas Petazzoni wrote:
> (...)
>> As it was explained above, we unfortunately can't read the
>> current base address of the internal register window, so we need a
>> different mechanism to know if the bootloader has done the remapping
>> at 0xF1000000 (new generation bootloader) or has left the internal
>> registers at 0xD0000000 (old generation bootloader).
>
> Just out of curiosity, what happens if you touch the register at the
> wrong address ? I mean, if you blindly write to the 0xD0xxxxxx address
> that you want the registers to be mapped at 0xF1xxxxxx. Will the chip
> hang, will it silently ignore the sequence ? Because maybe you don't
> need to detect using CP15 whether the remapping was done, you could
> simply perform it unconditionally.

Willy,

I tried the above on Dove which is possibly affected by the workaround
as it is also ARMv7. In Dove you can access unmapped addresses without
any problems, but as Thomas already stated Armada 370/XP just hang.
Must be some default AHB slave in Dove, which Armada 370/XP is missing.

Sebastian


From tiejun.chen at windriver.com  Wed May 22 06:04:18 2013
From: tiejun.chen at windriver.com (tiejun.chen)
Date: Wed, 22 May 2013 18:04:18 +0800
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <519C9333.20609@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
Message-ID: <519C9822.9040909@windriver.com>

On 05/22/2013 05:43 PM, Sebastian Hesselbarth wrote:
> On 05/21/2013 07:48 PM, Andrew Lunn wrote:
>> On Tue, May 21, 2013 at 06:41:44PM +0200, Sebastian Hesselbarth wrote:
>>> This patch adds orion-eth and mvmdio device tree nodes for DT enabled
>>> Dove boards. As there is only one ethernet controller on Dove, a default
>>> phy node is also added with a note to set its reg property on a per-board
>>> basis.
>>>
>>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>> ---
> ...
>>> +            ethernet-port at 0 {
>>> +                device_type = "network";
>>> +                compatible = "marvell,orion-eth-port";
>>> +                reg =<0>;
>>> +                interrupts =<29>;
>>> +                /* overwrite MAC address in bootloader */
>>> +                local-mac-address = [00 00 00 00 00 00];
>>
>> Hi Sebastian
>>
>> Its probably a good idea to set the local administration bit in this
>> MAC address. i.e. first byte is 02.
>
> Andrew,
>
> we just need an invalid address here to trigger the default behavior of
> the driver and load the MAC address from its register. As PPC binding
> documentation also has all zero, I just took it.

The truth is in PPC case, often we set the real mac address with some variables 
like 'eth[x]addr' in u-boot prompt, then u-boot will parse that value to fill 
the dtb. At last the associated driver can get the actual mac address from the 
dtb. And especially for those older u-boot version, even you have to reset the 
'local-mac-address' property in dts directly with the real mac address before 
generate the dtb since the older u-boot have no this ability to fill dtb again 
before pass the kernel.

Tiejun



From hdoyu at nvidia.com  Wed May 22 06:07:30 2013
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 May 2013 12:07:30 +0200
Subject: [v2 0/6] CLK: tegra: convert device tree files to use CLK defines
In-Reply-To: <20130522091248.b3acd9c56ab66535d75b8fd1@nvidia.com>
References: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com><519B9B5D.4050402@wwwdotorg.org><20130522091248.b3acd9c56ab66535d75b8fd1@nvidia.com>
Message-ID: <20130522.130730.1153046210420942555.hdoyu@nvidia.com>

Hiroshi Doyu <hdoyu at nvidia.com> wrote @ Wed, 22 May 2013 08:12:48 +0200:

> On Tue, 21 May 2013 18:05:49 +0200
> Stephen Warren <swarren at wwwdotorg.org> wrote:
> 
> > On 05/21/2013 03:10 AM, Hiroshi Doyu wrote:
> > > This patchset converts device tree files to use CLK defines. This
> > > version was updated along with the latest DT changes.
> > > 
> > > The following changes since commit 7479d8bb5650f43053d0e82fa44db668cf968f11:
> > > 
> > >   TESTING: Build Tegra USB as a module (2013-05-20 13:11:19 -0600)
> > 
> > That commit is in my personal work-in-progress branch. This series
> > should be based on Tegra's for-3.11/dt branch. This will make a
> > difference (at least) in patch 6/6, where you've edited some DT nodes
> > that don't yet exist upstream (i.e. Tegra's for-3.11/dt branch) and
> > hence this series won't apply there.
> 
> I'll rebase.

Rebased on Tegra's for-3.11/dt, including fix: [2/6] over 80 columns.

If you want me to send patches again, please let me know.

The following changes since commit 4d0c81c723f78a2f7f6ef844ff8e1fd174180029:

  ARM: tegra: Add charger subnode to tps65090 node (2013-05-20 13:14:09 -0600)

are available in the git repository at:

  git://nv-tegra.nvidia.com/user/hdoyu/linux.git dt-replace-clkid3

for you to fetch changes up to 00535ac4b17af0691a73737a70b0cbd78a9d2262:

  ARM: tegra114: convert device tree files to use CLK defines (2013-05-22 12:58:04 +0300)

----------------------------------------------------------------
Hiroshi Doyu (6):
      ARM: tegra20: create a DT header defining CLK IDs
      ARM: tegra20: convert device tree files to use CLK defines
      ARM: tegra30: create a DT header defining CLK IDs
      ARM: tegra30: convert device tree files to use CLK defines
      ARM: tegra114: create a DT header defining CLK IDs
      ARM: tegra114: convert device tree files to use CLK defines

 .../bindings/clock/nvidia,tegra114-car.txt         | 252 +--------------
 .../bindings/clock/nvidia,tegra20-car.txt          | 154 +---------
 .../bindings/clock/nvidia,tegra30-car.txt          | 211 +------------
 arch/arm/boot/dts/tegra114.dtsi                    |  51 +--
 arch/arm/boot/dts/tegra20-colibri-512.dtsi         |   4 +-
 arch/arm/boot/dts/tegra20-harmony.dts              |   4 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts          |   4 +-
 arch/arm/boot/dts/tegra20-paz00.dts                |   7 +-
 arch/arm/boot/dts/tegra20-plutux.dts               |   4 +-
 arch/arm/boot/dts/tegra20-seaboard.dts             |   4 +-
 arch/arm/boot/dts/tegra20-tec.dts                  |   4 +-
 arch/arm/boot/dts/tegra20-trimslice.dts            |   4 +-
 arch/arm/boot/dts/tegra20-ventana.dts              |   4 +-
 arch/arm/boot/dts/tegra20-whistler.dts             |   4 +-
 arch/arm/boot/dts/tegra20.dtsi                     | 116 +++----
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |   4 +-
 arch/arm/boot/dts/tegra30.dtsi                     | 110 ++++---
 include/dt-bindings/clk/tegra114-car.h             | 342 +++++++++++++++++++++
 include/dt-bindings/clk/tegra20-car.h              | 158 ++++++++++
 include/dt-bindings/clk/tegra30-car.h              | 265 ++++++++++++++++
 20 files changed, 963 insertions(+), 743 deletions(-)
 create mode 100644 include/dt-bindings/clk/tegra114-car.h
 create mode 100644 include/dt-bindings/clk/tegra20-car.h
 create mode 100644 include/dt-bindings/clk/tegra30-car.h


From james.hogan at imgtec.com  Wed May 22 06:13:17 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Wed, 22 May 2013 11:13:17 +0100
Subject: [PATCH v4 3/5] clk: add support for clock reparent on set_rate
In-Reply-To: <519B01DF.1080700@codeaurora.org>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-4-git-send-email-james.hogan@imgtec.com>
 <519B01DF.1080700@codeaurora.org>
Message-ID: <519C9A3D.1010902@imgtec.com>

On 21/05/13 06:10, Saravana Kannan wrote:
> On 05/20/2013 06:28 AM, James Hogan wrote:
>> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
>> index dd7adff..8138c94 100644
>> --- a/include/linux/clk-private.h
>> +++ b/include/linux/clk-private.h
>> @@ -33,8 +33,11 @@ struct clk {
>>       const char        **parent_names;
>>       struct clk        **parents;
>>       u8            num_parents;
>> +    u8            new_parent_index;
> 
> Why do you need this? Given the new_parent, can't the specific clock
> implementation just look it up when set_rate() is called? Wouldn't that
> be the only time you would actually need the index?
>
> If it's just for optimization of some error cases, I think we should
> drop this to keep the code simpler. One less state to keep track of when
> reading, writing or reviewing the clock framework.

clk_change_rate cannot currently return an error condition so I had
assumed it was better to check that the requested parent clock has a
valid parent index prior to starting to change any clock rates or firing
off any notifications.

Cheers
James



From sebastian.hesselbarth at gmail.com  Wed May 22 06:13:58 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 12:13:58 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <519C9822.9040909@windriver.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com>
Message-ID: <519C9A66.3050807@gmail.com>

On 05/22/2013 12:04 PM, tiejun.chen wrote:
> On 05/22/2013 05:43 PM, Sebastian Hesselbarth wrote:
>> On 05/21/2013 07:48 PM, Andrew Lunn wrote:
>>> On Tue, May 21, 2013 at 06:41:44PM +0200, Sebastian Hesselbarth wrote:
>>>> This patch adds orion-eth and mvmdio device tree nodes for DT enabled
>>>> Dove boards. As there is only one ethernet controller on Dove, a
>>>> default
>>>> phy node is also added with a note to set its reg property on a
>>>> per-board
>>>> basis.
>>>>
>>>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>>> ---
>> ...
>>>> + ethernet-port at 0 {
>>>> + device_type = "network";
>>>> + compatible = "marvell,orion-eth-port";
>>>> + reg =<0>;
>>>> + interrupts =<29>;
>>>> + /* overwrite MAC address in bootloader */
>>>> + local-mac-address = [00 00 00 00 00 00];
>>>
>>> Hi Sebastian
>>>
>>> Its probably a good idea to set the local administration bit in this
>>> MAC address. i.e. first byte is 02.
>>
>> Andrew,
>>
>> we just need an invalid address here to trigger the default behavior of
>> the driver and load the MAC address from its register. As PPC binding
>> documentation also has all zero, I just took it.
>
> The truth is in PPC case, often we set the real mac address with some
> variables like 'eth[x]addr' in u-boot prompt, then u-boot will parse
> that value to fill the dtb. At last the associated driver can get the
> actual mac address from the dtb. And especially for those older u-boot
> version, even you have to reset the 'local-mac-address' property in dts
> directly with the real mac address before generate the dtb since the
> older u-boot have no this ability to fill dtb again before pass the kernel.

Tiejun,

with Marvell SoCs it is no different, except that there is almost no dtb
support in their u-boot. The default behavior of the driver always was
to load the MAC address from its register if there is no valid overwrite
value. Using an invalid address (and all zero above is invalid) will
cause of_get_mac_address() to fail (which we allow), the corresponding
platform_data will never be written, and cause the default behavior.

We only need an invalid address passed initially on local-mac-address.
DT aware boot loader will overwrite but DT agnositic boot loader will
not. I can put any invalid MAC address in here, so I have chosen the
very first I can think of.

Sebastian


From peterz at infradead.org  Wed May 22 06:16:10 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Wed, 22 May 2013 12:16:10 +0200
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130522094709.GA26451@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <20130521115734.GA9554@twins.programming.kicks-ass.net>
 <20130522094709.GA26451@redhat.com>
Message-ID: <20130522101610.GL18810@twins.programming.kicks-ass.net>

On Wed, May 22, 2013 at 12:47:09PM +0300, Michael S. Tsirkin wrote:
> >  
> > +static inline bool __can_fault(void)
> > +{
> > +	/*
> > +	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
> > +	 * holding the mmap_sem, this is safe because kernel memory doesn't
> > +	 * get paged out, therefore we'll never actually fault, and the
> > +	 * below annotations will generate false positives.
> > +	 */
> > +	if (segment_eq(get_fs(), KERNEL_DS))
> > +		return false;
> > +
> > +	if (in_atomic() /* || pagefault_disabled() */)
> 
> One question here: I'm guessing you put this comment here
> for illustrative purposes, implying code that will
> be enabled in -rt?
> We don't want it upstream I think, right?

Right, and as a reminder that when we do this we need to add a patch to
-rt. But yeah, we should have a look and see if its worth pulling those
patches from -rt into mainline in some way shape or form. They're big
but trivial IIRC.

I'm fine with you leaving that comment out though.. 


From peterz at infradead.org  Wed May 22 06:19:16 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Wed, 22 May 2013 12:19:16 +0200
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <201305221125.36284.arnd@arndb.de>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
Message-ID: <20130522101916.GM18810@twins.programming.kicks-ass.net>

On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> Calling might_fault() for every __get_user/__put_user is rather expensive
> because it turns what should be a single instruction (plus fixup) into an
> external function call.

We could hide it all behind CONFIG_DEBUG_ATOMIC_SLEEP just like
might_sleep() is. I'm not sure there's a point to might_fault() when
might_sleep() is a NOP.


From jbe at pengutronix.de  Wed May 22 06:19:43 2013
From: jbe at pengutronix.de (Juergen Beisert)
Date: Wed, 22 May 2013 12:19:43 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>
 <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
Message-ID: <201305221219.43558.jbe@pengutronix.de>

Hi Fabio,

> i2c slowness is a different issue.

Same happens here for my i.M23 based platform. It seems the PIO mode does not
work, or at least not like it works on a i.MX28. Each short transfer needs
about one second (without an error message) but does not send anything on the
I2C lines.

I need the following patches to make I2C master work within a 3.10-rc2 kernel:

Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C controller
Signed-off-by: Juergen Beisert <jbe at pengutronix.de>

---
 drivers/i2c/busses/i2c-mxs.c | 39 +++++++++++++++++++++++++++++++++------
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 2039f23..5e69d8c 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -97,10 +97,17 @@
 #define MXS_CMD_I2C_READ	(MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
 				 MXS_I2C_CTRL0_MASTER_MODE)
 
+enum mxs_i2c_devtype {
+	MXS_I2C_UNKNOWN = 0,
+	MXS_I2C_V1,
+	MXS_I2C_V2,
+};
+
 /**
  * struct mxs_i2c_dev - per device, private MXS-I2C data
  *
  * @dev: driver model device node
+ * @dev_type: distinguish i.MX23/i.MX28 features
  * @regs: IO registers pointer
  * @cmd_complete: completion object for transaction wait
  * @cmd_err: error code for last transaction
@@ -108,6 +115,7 @@
  */
 struct mxs_i2c_dev {
 	struct device *dev;
+	enum mxs_i2c_devtype dev_type;
 	void __iomem *regs;
 	struct completion cmd_complete;
 	int cmd_err;
@@ -633,8 +641,28 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 	return 0;
 }
 
+static struct platform_device_id mxs_i2c_devtype[] = {
+	{
+		.name = "imx23-i2c",
+		.driver_data = MXS_I2C_V1,
+	}, {
+		.name = "imx28-i2c",
+		.driver_data = MXS_I2C_V2,
+	}, { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
+
+static const struct of_device_id mxs_i2c_dt_ids[] = {
+	{ .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
+	{ .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
+
 static int mxs_i2c_probe(struct platform_device *pdev)
 {
+	const struct of_device_id *of_id =
+				of_match_device(mxs_i2c_dt_ids, &pdev->dev);
 	struct device *dev = &pdev->dev;
 	struct mxs_i2c_dev *i2c;
 	struct i2c_adapter *adap;
@@ -651,6 +679,11 @@ static int mxs_i2c_probe(struct platform_device *pdev)
 	if (!i2c)
 		return -ENOMEM;
 
+	if (of_id) {
+		const struct platform_device_id *device_id = of_id->data;
+		i2c->dev_type = device_id->driver_data;
+	}
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irq = platform_get_irq(pdev, 0);
 
@@ -726,12 +759,6 @@ static int mxs_i2c_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id mxs_i2c_dt_ids[] = {
-	{ .compatible = "fsl,imx28-i2c", },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
-
 static struct platform_driver mxs_i2c_driver = {
 	.driver = {
 		   .name = DRIVER_NAME,
---------------------------------------------------------------------------------------------

Subject: [PATCH] I2C/MXS: on i.MX23 only do DMA based I2C transfers
Signed-off-by: Juergen Beisert <jbe at pengutronix.de>

---
 drivers/i2c/busses/i2c-mxs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 5e69d8c..90cbac5 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -500,9 +500,10 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 	 * is set to 8 bytes, transfers shorter than 8 bytes are transfered
 	 * using PIO mode while longer transfers use DMA. The 8 byte border is
 	 * based on this empirical measurement and a lot of previous frobbing.
+	 * Note: this special feature only works on i.MX28 SoC
 	 */
 	i2c->cmd_err = 0;
-	if (msg->len < 8) {
+	if (i2c->dev_type == MXS_I2C_V2 && msg->len < 8) {
 		ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
 		if (ret)
 			mxs_i2c_reset(i2c);

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-5121-206917-5128 |
Peiner Str. 6-8, 31137 Hildesheim, Germany    | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |


From plagnioj at jcrosoft.com  Wed May 22 06:35:25 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 22 May 2013 12:35:25 +0200
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred
 probing is done
In-Reply-To: <518D7CC3.6050000@codeaurora.org>
References: <1368076726-11492-1-git-send-email-skannan@codeaurora.org>
 <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
 <20130510064520.GI3041@game.jcrosoft.org>
 <518D7CC3.6050000@codeaurora.org>
Message-ID: <20130522103525.GD9937@game.jcrosoft.org>

On 16:03 Fri 10 May     , Saravana Kannan wrote:
> On 05/09/2013 11:45 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >On 11:35 Thu 09 May     , Saravana Kannan wrote:
> >>With deferred probing, late_initcall() is too soon to declare a clock as
> >>unused. Wait for deferred probing to finish before declaring a clock as
> >>unused. Since deferred probing is done in late_initcall(), do the unused
> >>check to late_initcall_sync.
> >
> >Nack for both regulator & clk
> >
> >you can not known when the clock need to be shutdown
> >
> >example display splash screen set by the bootloader and display as module
> >
> >Best Regards,
> >J.
> 
> You are joking right? This is already done in the kernel. If you
> don't want that, please rip out the code and try to get that picked
> up. I'm sending out this patch for fix what's currently in the
> kernel for those who care for the current feature.

so this feature is nightmare we need to KILL it

Best Regards,
J.
> 
> Regards,
> Saravana
> 
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation


From rjw at sisk.pl  Wed May 22 06:54:18 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 22 May 2013 12:54:18 +0200
Subject: spurious bL cpufreq driver messages
In-Reply-To: <CAKohpokkMvEhotcow8qfCGP0SxNfRsxw7swo-ZFbTSKE-F8Xtw@mail.gmail.com>
References: <519686BC.3090101@gmail.com> <11917612.jOVuLqOMKF@vostro.rjw.lan>
 <CAKohpokkMvEhotcow8qfCGP0SxNfRsxw7swo-ZFbTSKE-F8Xtw@mail.gmail.com>
Message-ID: <2544320.us1o8zUn7V@vostro.rjw.lan>

On Wednesday, May 22, 2013 06:44:20 AM Viresh Kumar wrote:
> On 22 May 2013 05:15, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> > On Monday, May 20, 2013 10:06:49 AM Viresh Kumar wrote:
> >> On 19 May 2013 01:21, Rob Herring <robherring2 at gmail.com> wrote:
> >> > No, it still registers the bL driver. The problem is not that DT data
> >> > is missing, but it is present on a single cluster system.
> >>
> >> I misread your mail.. I got the problem now.. Below should fix your
> >> issue (It is rebased on the patch I pointed to you earlier):
> >>
> >> Attached too for testing as gmail copy-paste will break it.
> >>
> >> @Rafael: Once Rob gives his Tested-by, please queue it for 3.10-rcs
> >>
> >> ------------x-----------------x-----------------
> >>
> >> From: Viresh Kumar <viresh.kumar at linaro.org>
> >> Date: Mon, 20 May 2013 09:57:17 +0530
> >> Subject: [PATCH] cpufreq: arm_big_little_dt: Instantiate as platform_driver
> >>
> >> As multiplatform build is being adopted by more and more ARM platforms, initcall
> >> function should be used very carefully. For example, when both arm_big_little_dt
> >> and cpufreq-cpu0 drivers are compiled in, arm_big_little_dt driver may try to
> >> register even if we had platform device for cpufreq-cpu0 registered.
> >>
> >> To eliminate this undesired the effect, the patch changes arm_big_little_dt
> >> driver to have it instantiated as a platform_driver. Then it will only run on
> >> platforms that create the platform_device "arm-bL-cpufreq-dt".
> >>
> >> Reported-by: Rob Herring <robherring2 at gmail.com>
> >> Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>
> >
> > The patch (from the attachment) didn't apply for me.  Please check the
> > bleeding-edge branch.
> 
> Have you tried applying this before it (As written in my last mail)?

No and I'm not sure which mail you're referring to.  There's been quite
a number of them recently. :-)

> https://groups.google.com/forum/?fromgroups#!topic/linux.kernel/XJF-82rad4o
>
> Above is also required fix for 3.10-rc3

OK, that worked.

Please check the bleeding-edge branch now and see if anything for-3.10-rc is
still missing.

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From pranavkumar at linaro.org  Wed May 22 06:48:33 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Wed, 22 May 2013 16:18:33 +0530
Subject: [RFC] arm64: Add support to pass earlyprintk argument via device tree
Message-ID: <1369219713-18590-1-git-send-email-pranavkumar@linaro.org>

This patch adds support for defining and passing earlyprintk
related information i.e. device and address information via
device tree by adding it inside "chosen" node.

This will help user to just specify "earlyprintk" from bootargs
without actually knowing the address and device to enable
earlyprintk.

Mechanism:

One can just append earlyprintk=device-type,address (same as we pass
through command line) in "/chosen" node to notify kernel which is the
earlyprintk device and what is its address.

Backward Compatibility:

This patch also allows existing method of specifying earlyprintk
parameter via bootargs.

Existing method i.e. passing via bootargs will still have precedence
over device tree i.e. if one specifies earlyprintk=device-type,address
in bootargs then kernel will use information from bootargs instead of
device tree.

If user just specifies earlyprintk (without =...) then kernel will
look for device tree earlyprintk parameter.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar at linaro.org>
Signed-off-by: Anup Patel <anup.patel at linaro.org>
---
 arch/arm64/kernel/early_printk.c |    7 +++++++
 arch/arm64/kernel/setup.c        |   22 +++++++++++++++++++++-
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/early_printk.c b/arch/arm64/kernel/early_printk.c
index fbb6e18..4e6f845 100644
--- a/arch/arm64/kernel/early_printk.c
+++ b/arch/arm64/kernel/early_printk.c
@@ -29,6 +29,8 @@
 static void __iomem *early_base;
 static void (*printch)(char ch);
 
+extern char *earlyprintk_dt_args;
+
 /*
  * PL011 single character TX.
  */
@@ -116,6 +118,11 @@ static int __init setup_early_printk(char *buf)
 	phys_addr_t paddr = 0;
 
 	if (!buf) {
+		/* Try to check if Device Tree has this argument or not ? */
+		buf = earlyprintk_dt_args;
+	}
+
+	if (!buf) {
 		pr_warning("No earlyprintk arguments passed.\n");
 		return 0;
 	}
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 6a9a532..94ce7a9 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -60,6 +60,9 @@ EXPORT_SYMBOL(processor_id);
 unsigned int elf_hwcap __read_mostly;
 EXPORT_SYMBOL_GPL(elf_hwcap);
 
+char *earlyprintk_dt_args;
+EXPORT_SYMBOL_GPL(earlyprintk_dt_args);
+
 static const char *cpu_name;
 static const char *machine_name;
 phys_addr_t __fdt_pointer __initdata;
@@ -122,6 +125,23 @@ static void __init setup_processor(void)
 	elf_hwcap = 0;
 }
 
+int __init early_init_dt_scan_chosen_arm64(unsigned long node,
+					   const char *uname,
+					   int depth, void *data)
+{
+	char *prop;
+
+	/* Check if this is chosen node */
+	if (early_init_dt_scan_chosen(node, uname, depth, data) == 0)
+		return 0;
+
+	prop = of_get_flat_dt_prop(node, "earlyprintk", NULL);
+	if (prop)
+		earlyprintk_dt_args = prop;
+
+	return 1;
+}
+
 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 {
 	struct boot_param_header *devtree;
@@ -165,7 +185,7 @@ static void __init setup_machine_fdt(phys_addr_t dt_phys)
 	pr_info("Machine: %s\n", machine_name);
 
 	/* Retrieve various information from the /chosen node */
-	of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
+	of_scan_flat_dt(early_init_dt_scan_chosen_arm64, boot_command_line);
 	/* Initialize {size,address}-cells info */
 	of_scan_flat_dt(early_init_dt_scan_root, NULL);
 	/* Setup memory, calling early_init_dt_add_memory_arch */
-- 
1.7.9.5



From viresh.kumar at linaro.org  Wed May 22 06:52:58 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Wed, 22 May 2013 16:22:58 +0530
Subject: spurious bL cpufreq driver messages
In-Reply-To: <2544320.us1o8zUn7V@vostro.rjw.lan>
References: <519686BC.3090101@gmail.com> <11917612.jOVuLqOMKF@vostro.rjw.lan>
 <CAKohpokkMvEhotcow8qfCGP0SxNfRsxw7swo-ZFbTSKE-F8Xtw@mail.gmail.com>
 <2544320.us1o8zUn7V@vostro.rjw.lan>
Message-ID: <CAKohpomP+_XcjQSpKUiZQnGLT6mSSZCoT2h1w2+P-US9eBo7YA@mail.gmail.com>

On 22 May 2013 16:24, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> Please check the bleeding-edge branch now and see if anything for-3.10-rc is
> still missing.

You have picked all my pending patches for current rc release.. All pending
are targeted for 3.11 or linux-next. So all good.

thanks.


From marex at denx.de  Wed May 22 07:05:09 2013
From: marex at denx.de (Marek Vasut)
Date: Wed, 22 May 2013 13:05:09 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <201305221219.43558.jbe@pengutronix.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
 <201305221219.43558.jbe@pengutronix.de>
Message-ID: <201305221305.09579.marex@denx.de>

Dear Juergen Beisert,

> Hi Fabio,
> 
> > i2c slowness is a different issue.
> 
> Same happens here for my i.M23 based platform. It seems the PIO mode does
> not work, or at least not like it works on a i.MX28. Each short transfer
> needs about one second (without an error message) but does not send
> anything on the I2C lines.
> 
> I need the following patches to make I2C master work within a 3.10-rc2
> kernel:
> 
> Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C

I'm all for it, but then ... won't it be better if you actually fixed the PIO 
and mixed-mode on MX23 instead of implementing such hack? It might actually turn 
out to be beneficial for MX28 too.

Best regards,
Marek Vasut


From mst at redhat.com  Wed May 22 07:07:29 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 14:07:29 +0300
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <20130522101916.GM18810@twins.programming.kicks-ass.net>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
 <20130522101916.GM18810@twins.programming.kicks-ass.net>
Message-ID: <20130522110729.GB5643@redhat.com>

On Wed, May 22, 2013 at 12:19:16PM +0200, Peter Zijlstra wrote:
> On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> > Calling might_fault() for every __get_user/__put_user is rather expensive
> > because it turns what should be a single instruction (plus fixup) into an
> > external function call.
> 
> We could hide it all behind CONFIG_DEBUG_ATOMIC_SLEEP just like
> might_sleep() is. I'm not sure there's a point to might_fault() when
> might_sleep() is a NOP.

The patch that you posted gets pretty close.
E.g. I'm testing this now:
+#define might_fault() do { \
+       if (_might_fault()) \
+               __might_sleep(__FILE__, __LINE__, 0); \
+       might_resched(); \
+} while(0)

So if might_sleep is a NOP, __might_sleep and might_resched are NOPs
so compiler will optimize this all out.

However, in a related thread, you pointed out that might_sleep is not a NOP if
CONFIG_PREEMPT_VOLUNTARY is set, even without CONFIG_DEBUG_ATOMIC_SLEEP.

Do you think we should drop the preemption point in might_fault?
Only copy_XX_user?
Only __copy_XXX_user ?

-- 
MST


From horms at verge.net.au  Wed May 22 07:16:05 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 20:16:05 +0900
Subject: [PATCH v4 5/7] ARM: mach-shmobile: sh73a0: Setup the timer CMT10
 using DT
In-Reply-To: <1365679443-25456-5-git-send-email-hechtb+renesas@gmail.com>
References: <1365679443-25456-1-git-send-email-hechtb+renesas@gmail.com>
 <1365679443-25456-5-git-send-email-hechtb+renesas@gmail.com>
Message-ID: <20130522111601.GA16095@verge.net.au>

On Thu, Apr 11, 2013 at 01:24:01PM +0200, Bastian Hecht wrote:
> We can now use the Device Tree for bringing up our timer device CMT10 on
> the SoC sh73a0.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>

I had queued-up this patch for v3.11 inthe soc-sh73a0 branch.

However, on request from Magnus, I am dropping it as it prevents
the kzm9g (non-reference) from booting if CONFIG_TMU is not
enabled. This is particularly problematic as I am told it
is not desirable to enable TMU in production as it conflicts
with power management.

The problem that this patch introduces appears to be that CMT is
now started too late for it to be used as a clocks source
when Calibrating the delay loop. If TMU is present then it masks
this problem by providing a clocksource at this point.

With this in mind Magnus has indicated that for the forseable future
he would like CMT and TMU to be initialised using C-code rather
than using DT.

Magnus, please feel free to jump in an correct anything above that
is incomplete or incorrect.

> ---
> v4: same. only patch 2 and 3 changed
> 
>  arch/arm/boot/dts/sh73a0.dtsi         |   11 +++++++++++
>  arch/arm/mach-shmobile/setup-sh73a0.c |   32 --------------------------------
>  2 files changed, 11 insertions(+), 32 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
> index ec40bf7..67b5089 100644
> --- a/arch/arm/boot/dts/sh73a0.dtsi
> +++ b/arch/arm/boot/dts/sh73a0.dtsi
> @@ -222,4 +222,15 @@
>  		cap-sd-highspeed;
>  		status = "disabled";
>  	};
> +
> +	timer at e6138010 {
> +		compatible = "renesas,cmt-timer";
> +		interrupt-parent = <&gic>;
> +		reg = <0xe6138010 0xc>;
> +		interrupts = <0 65 0x4>;
> +		renesas,device-id = <1>;
> +		renesas,channel-id = <0>;
> +		renesas,source-quality = <3>;
> +		renesas,event-quality = <3>;
> +	};
>  };
> diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> index d10ded0..024b7a6 100644
> --- a/arch/arm/mach-shmobile/setup-sh73a0.c
> +++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> @@ -235,37 +235,6 @@ static struct platform_device scif8_device = {
>  	},
>  };
>  
> -static struct sh_timer_config cmt10_platform_data = {
> -	.name = "CMT10",
> -	.channel_offset = 0x10,
> -	.timer_bit = 0,
> -	.clockevent_rating = 125,
> -	.clocksource_rating = 125,
> -};
> -
> -static struct resource cmt10_resources[] = {
> -	[0] = {
> -		.name	= "CMT10",
> -		.start	= 0xe6138010,
> -		.end	= 0xe613801b,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[1] = {
> -		.start	= gic_spi(65),
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -};
> -
> -static struct platform_device cmt10_device = {
> -	.name		= "sh_cmt",
> -	.id		= 10,
> -	.dev = {
> -		.platform_data	= &cmt10_platform_data,
> -	},
> -	.resource	= cmt10_resources,
> -	.num_resources	= ARRAY_SIZE(cmt10_resources),
> -};
> -
>  /* TMU */
>  static struct sh_timer_config tmu00_platform_data = {
>  	.name = "TMU00",
> @@ -930,7 +899,6 @@ static struct platform_device *sh73a0_devices_dt[] __initdata = {
>  	&scif6_device,
>  	&scif7_device,
>  	&scif8_device,
> -	&cmt10_device,
>  };
>  
>  static struct platform_device *sh73a0_early_devices[] __initdata = {
> -- 
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From peterz at infradead.org  Wed May 22 07:27:36 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Wed, 22 May 2013 13:27:36 +0200
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <20130522110729.GB5643@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
 <20130522101916.GM18810@twins.programming.kicks-ass.net>
 <20130522110729.GB5643@redhat.com>
Message-ID: <20130522112736.GN18810@twins.programming.kicks-ass.net>

On Wed, May 22, 2013 at 02:07:29PM +0300, Michael S. Tsirkin wrote:
> On Wed, May 22, 2013 at 12:19:16PM +0200, Peter Zijlstra wrote:
> > On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> > > Calling might_fault() for every __get_user/__put_user is rather expensive
> > > because it turns what should be a single instruction (plus fixup) into an
> > > external function call.
> > 
> > We could hide it all behind CONFIG_DEBUG_ATOMIC_SLEEP just like
> > might_sleep() is. I'm not sure there's a point to might_fault() when
> > might_sleep() is a NOP.
> 
> The patch that you posted gets pretty close.
> E.g. I'm testing this now:
> +#define might_fault() do { \
> +       if (_might_fault()) \
> +               __might_sleep(__FILE__, __LINE__, 0); \
> +       might_resched(); \
> +} while(0)
> 
> So if might_sleep is a NOP, __might_sleep and might_resched are NOPs
> so compiler will optimize this all out.
> 
> However, in a related thread, you pointed out that might_sleep is not a NOP if
> CONFIG_PREEMPT_VOLUNTARY is set, even without CONFIG_DEBUG_ATOMIC_SLEEP.

Oh crud yeah.. and you actually need that _might_fault() stuff for that
too. Bugger.

Yeah, I wouldn't know what the effects of dropping ita (for the copy
functions) would be, VOLUNTARY isn't a preemption mode I ever use (even
though it seems most distros default to it).




From itooo at itooo.com  Wed May 22 07:46:53 2013
From: itooo at itooo.com (Greg)
Date: Wed, 22 May 2013 13:46:53 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <519C9779.1040104@gmail.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu> <519C9779.1040104@gmail.com>
Message-ID: <519CB02D.3090304@itooo.com>

Le 22/05/2013 12:01, Sebastian Hesselbarth a ?crit :
> On 05/21/2013 09:38 PM, Willy Tarreau wrote:
>> On Tue, May 21, 2013 at 12:33:25PM +0200, Thomas Petazzoni wrote:
>> (...)
>>> As it was explained above, we unfortunately can't read the
>>> current base address of the internal register window, so we need a
>>> different mechanism to know if the bootloader has done the remapping
>>> at 0xF1000000 (new generation bootloader) or has left the internal
>>> registers at 0xD0000000 (old generation bootloader).
>>
>> Just out of curiosity, what happens if you touch the register at the
>> wrong address ? I mean, if you blindly write to the 0xD0xxxxxx address
>> that you want the registers to be mapped at 0xF1xxxxxx. Will the chip
>> hang, will it silently ignore the sequence ? Because maybe you don't
>> need to detect using CP15 whether the remapping was done, you could
>> simply perform it unconditionally.
>
> Willy,
>
> I tried the above on Dove which is possibly affected by the workaround
> as it is also ARMv7. In Dove you can access unmapped addresses without
> any problems, but as Thomas already stated Armada 370/XP just hang.
> Must be some default AHB slave in Dove, which Armada 370/XP is missing.

According to functionnal specs, when accessing a unmapped address, you 
will trigger a "coherency fabric" error named AccessErr (register 
0x00020258).
I guess this will trigger an interrupt which will hang the CPU if the 
vector is not handled.

Greg


From ming.lei at canonical.com  Wed May 22 07:55:11 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Wed, 22 May 2013 19:55:11 +0800
Subject: [RFC PATCH] ARM: mm: lazy cache flushing on non-mapped pages
Message-ID: <1369223711-2995-1-git-send-email-ming.lei@canonical.com>

Currently flush_dcache_page() thinks pages as non-mapped if
mapping_mapped(mapping) return false. This approach is very
coase:
	- mmap on part of file may cause all pages backed on
	the file being thought as mmaped

	- file-backed pages aren't mapped into user space actually
	if the memory mmaped on the file isn't accessed

This patch also uses page_mapcount() to decide if the page has been
mapped.

>From the attached test code, we can see there is much performance
improvement(>25%) when accessing page caches via read under this
situations, so memcpy benefits a lot from not flushing cache
under this situations.

Seq.   read time without the patch	Seq. read time with the patch
================================================================
No. 0, time  22615636 us		No. 0, time  22014717 us
No. 1, time  4387851 us 		No. 1, time  3113184 us
No. 2, time  4276535 us 		No. 2, time  3005244 us
No. 3, time  4259821 us 		No. 3, time  3001565 us
No. 4, time  4263811 us 		No. 4, time  3002748 us
No. 5, time  4258486 us 		No. 5, time  3004104 us
No. 6, time  4253009 us 		No. 6, time  3002188 us
No. 7, time  4262809 us 		No. 7, time  2998196 us
No. 8, time  4264525 us 		No. 8, time  3007255 us
No. 9, time  4267795 us 		No. 9, time  3005094 us

1), No.0. is to read the file from storage device, and others are
to read the file from page caches basically.
2), file size is 512M, and is on ext4 over usb mass storage.
3), the test is done on Pandaboard.

unsigned int  sum = 0;
unsigned long sum_val = 0;

static unsigned long tv_diff(struct timeval *tv1, struct timeval *tv2)
{
	return (tv2->tv_sec - tv1->tv_sec) * 1000000 +
		(tv2->tv_usec - tv1->tv_usec);
}

int main(int argc, char *argv[])
{
	char *mbuf, fbuf;
	int fd;
	int i;
	unsigned long page_size, size;
	struct stat stat;
	struct timeval t1, t2;
	unsigned char *rbuf = malloc(32 * page_size);

	if (!rbuf) {
		printf("	%s\n", "malloc failed");
		exit(-1);
	}

	page_size = getpagesize();
	fd = open(argv[1], O_RDWR);
	assert(fd >= 0);

	fstat(fd, &stat);
	size = stat.st_size;
	printf("%s: file %s, size %lu, page size %lu\n",
		argv[0],
		argv[1], size, page_size);

	gettimeofday(&t1, NULL);
	mbuf = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
	if (!mbuf) {
		printf("	%s\n", "mmap failed");
		exit(-1);
	}

	for (i = 0 ; i < size ; i += (page_size * 32)) {
		int rcnt;
		lseek(fd, i, SEEK_SET);
		rcnt = read(fd, rbuf, page_size * 32);
		if (rcnt != page_size * 32) {
			printf("%s: read faild\n", __func__);
			exit(-1);
		}
	}
	free(rbuf);
	munmap(mbuf, size);
	gettimeofday(&t2, NULL);
	printf("\tread mmaped time: %luus\n", tv_diff(&t1, &t2));

	close(fd);
}

Cc: Michel Lespinasse <walken at google.com>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Ming Lei <ming.lei at canonical.com>
---
 arch/arm/mm/flush.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 9251d56..1d0e8d5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -283,8 +283,8 @@ void flush_dcache_page(struct page *page)
 
 	mapping = page_mapping(page);
 
-	if (!cache_ops_need_broadcast() &&
-	    mapping && !mapping_mapped(mapping))
+	if (!cache_ops_need_broadcast() && mapping &&
+		(!mapping_mapped(mapping) || !page_mapcount(page)))
 		clear_bit(PG_dcache_clean, &page->flags);
 	else {
 		__flush_dcache_page(mapping, page);
-- 
1.7.9.5



From will.deacon at arm.com  Wed May 22 08:41:12 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 22 May 2013 13:41:12 +0100
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <20130521151143.GH10453@mudshark.cambridge.arm.com>
 <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
Message-ID: <20130522124112.GA16361@mudshark.cambridge.arm.com>

On Tue, May 21, 2013 at 06:24:15PM +0100, Andy Shevchenko wrote:
> On Tue, May 21, 2013 at 6:11 PM, Will Deacon <will.deacon at arm.com> wrote:
> > Hi Andy,
> >
> > On Tue, May 21, 2013 at 01:33:17PM +0100, Andy Shevchenko wrote:
> >> When thread is going to be stopped we have to unconditionally terminate all
> >> ongoing transfers. Otherwise it would be possible that callback function will
> >> be called on the next interrupt and will try to access to already freed
> >> structures.
> >>
> >> The patch introduces specific error message for this, though it doesn't
> >> increase the counter of the failed tests.
> >>
> >> Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
> >> Reported-by: Will Deacon <will.deacon at arm.com>
> >
> > Thanks for persevering with this! Although this patch definitely fixes the
> > panic I was seeing, I now observe buffer verification failures in subsequent
> > test runs after an aborted run:
> 
> I think the description to the commit adfa543e "dmatest: don't use
> set_freezable_with_signal()" may shed light on this.
> 
> The background (if  I got it correctly) is in race with done flag. So,
> we got a callback call from the DMA engine, but we don't know which
> transfer triggers it.
> I might be wrong. This is just an assumption.

I've not managed to work out exactly what's going on, but it's certainly
something like that. In fact, I just managed to trigger a case where all but
one of the transfers is aborted, whilst the remaining one fails. Looking at
the code, I can't see how that situation comes about, since the threads are
protected with the info mutex and kthread_stop is synchronous.

> Have you ever see such behaviour on pre v3.10-rc1 kernels? (I mean
> with old dmatest module)

No, dmatest from 3.9 is completely reliable in my experience.

Will


From lee.jones at linaro.org  Wed May 22 08:47:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 13:47:31 +0100
Subject: [RC FIXES] Fix broken MMC devices on Snowball
Message-ID: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>

The newly introduced ab8500 external regulator driver causes an
unexpected quirk when used with the Snowball low-cost development
board. When the 3 ab8500 external regulators are registered, the
ones which can be freed, are. Unfortunately, on Snowball one of
them is connected to the MMC power line. Once freed, this turns
off the MMC device. External regulators are not used on Snowball,
so it's pointless registering them in the first place.

These two patches ensure external regulators aren't registered 
on Snowball or any other platforms which do not require them.



From lee.jones at linaro.org  Wed May 22 08:47:32 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 13:47:32 +0100
Subject: [PATCH] ARM: ux500: Allow Snowball to pass its own regulator settings
In-Reply-To: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369226853-16978-2-git-send-email-lee.jones@linaro.org>

This patch fixes a bug introduced in the v3.10 merge window.

Currently the external regulator settings are passed though to the AB8500
regulator driver regards of whether they can or should be used on any
ux500 based platform. They are not applicable for the u8505 and when
enabled, they turn off AUX2 which adversely affects the eMMC on Snowball.

The driver already knows that the external regulator settings are not
appropriate for the u8505, however it's more difficult for driver code to
distinguish between two different u8500 based platforms.

Using the new semantics, we can just not pass the external regulator
initialisation values from platform code and the external regulator
driver will know not to register them.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-regulators.c |    8 ++++++++
 arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
 arch/arm/mach-ux500/board-mop500.c            |    2 ++
 3 files changed, 11 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index b34441b..7399e90 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -996,6 +996,14 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
 	.num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
 };
 
+/* External regulators turn off VAUX2 when in use on Snowball. */
+struct ab8500_regulator_platform_data snowball_regulator_plat_data = {
+	.reg_init               = ab8500_reg_init,
+	.num_reg_init           = ARRAY_SIZE(ab8500_reg_init),
+	.regulator              = ab8500_regulators,
+	.num_regulator          = ARRAY_SIZE(ab8500_regulators),
+};
+
 struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
 	.reg_init               = ab8505_reg_init,
 	.num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 039f513..6300e79 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -16,6 +16,7 @@
 
 extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
 extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
+extern struct ab8500_regulator_platform_data snowball_regulator_plat_data;
 extern struct regulator_init_data tps61052_regulator;
 extern struct regulator_init_data gpio_en_3v3_regulator;
 extern struct regulator_init_data sdi0_reg_init_data;
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0b018c4..2d609d4 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -615,6 +615,8 @@ static void __init snowball_init_machine(void)
 	struct device *parent = NULL;
 	int i;
 
+	ab8500_platdata.regulator = &snowball_regulator_plat_data;
+
 	platform_device_register(&db8500_prcmu_device);
 
 	sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 08:47:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 13:47:33 +0100
Subject: [PATCH] regulator: ab8500-ext: Don't register without initialisation
 data
In-Reply-To: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369226853-16978-3-git-send-email-lee.jones@linaro.org>

This patch fixes a bug introduced in the v3.10 merge window.

Some platforms will not want external registers. Rather than setting up
lots of different clauses in the core ab8500 regulator driver not to
call ab8500-ext init() we just won't pass the initialisation data from
platform code. This patch checks for it and if it's missing, we won't
register the external regulators.

Cc: Mark Brown <broonie at kernel.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/regulator/ab8500-ext.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/regulator/ab8500-ext.c b/drivers/regulator/ab8500-ext.c
index b4d4547..8421537 100644
--- a/drivers/regulator/ab8500-ext.c
+++ b/drivers/regulator/ab8500-ext.c
@@ -334,6 +334,12 @@ int ab8500_ext_regulator_init(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	/* have any external regulators been specified? */
+	if (pdata->num_ext_regulator == 0) {
+		dev_warn(&pdev->dev, "Not using external regulators\n");
+		return 0;
+	}
+
 	/* make sure the platform data has the correct size */
 	if (pdata->num_ext_regulator != ARRAY_SIZE(ab8500_ext_regulator_info)) {
 		dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
-- 
1.7.10.4



From horms+renesas at verge.net.au  Wed May 22 08:49:40 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 21:49:40 +0900
Subject: [PATCH] ARM: shmobile: kzm9g-reference: Update CMT clocksource rating
 to 80
Message-ID: <1369226980-16203-1-git-send-email-horms+renesas@verge.net.au>

Update the CMT clocksource rating from 100 to 10.

This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
Avoid dummy clockevent being preferred over real").

The patch noted above reduces the rating of dummy clockevent from 400 to 100.
This patch reduces the rating of CMT so that it is once again less than that
of the dummy clockevent.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

I also plan to reduce the rating of the STI clocksource to less than 100.
However, as I am not aware of any problems relating to STI in v3.10-rc
my plan is to update STI in the v3.11 timeframe.
---
 arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..9696f36 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
 	.name = "CMT10",
 	.channel_offset = 0x10,
 	.timer_bit = 0,
-	.clockevent_rating = 125,
+	.clockevent_rating = 80,
 	.clocksource_rating = 125,
 };
 
-- 
1.8.2.1



From daniel.lezcano at linaro.org  Wed May 22 08:54:13 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 22 May 2013 14:54:13 +0200
Subject: [PATCH v4] clocksource: add Vybrid Family pit timer support
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CBE88@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1369121274-9371-1-git-send-email-b35083@freescale.com>
 <519B48F4.8050005@linaro.org>
 <B56CDBE15CE27145A4B77D2D24263E851CBE88@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <519CBFF5.3060900@linaro.org>

On 05/22/2013 11:47 AM, Lu Jingchang-B35083 wrote:
> 

[ ... ]

>>
>>> +}
>>> +
>>> +static void __init pit_timer_init(struct device_node *np) {
>>> +	struct clk *pit_clk;
>>> +	void __iomem *timer_base;
>>> +	int irq;
>>> +
>>> +	timer_base = of_iomap(np, 0);
>>> +	BUG_ON(!timer_base);
>>
>> You raise a bug and then you go ahead setting up the address with an
>> invalid value, leading to a random crash.
> [Lu Jingchang-B35083] 
> The BUG_ON() will call BUG() if condition is true. It will print the stack trace and the current process will die, it won't go ahead, won't it? Thanks! 

Pff, right. I just puzzled myself. Never mind.


>>> +	/*
>>> +	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
>>> +	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
>>> +	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
>>> +	 */
>>> +	clksrc_base = timer_base + PITn_OFFSET(2);
>>> +	clkevt_base = timer_base + PITn_OFFSET(3);
>>> +
>>> +	irq = irq_of_parse_and_map(np, 0);
>>> +
>>> +	pit_clk = of_clk_get(np, 0);
>>> +	BUG_ON(IS_ERR(pit_clk));
>>> +
>>> +	BUG_ON(clk_prepare_enable(pit_clk));
>>
>> Same here.
>>
>>> +	cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ);
>>> +
>>> +	/* enable the pit module */
>>> +	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
>>> +
>>> +	BUG_ON(pit_clocksource_init(pit_clk));
>>> +
>>> +	pit_clockevent_init(pit_clk, irq);
>>
>> Please, remove these BUG_ON, this is inconsistent especially with a one
>> call init function. If pit_timer_init can't be initialized, just pr_err
>> + BUG.
> [Lu Jingchang-B35083] 
> Do you mean that I should not use the BUG_ON or I need print an error information by pr_err before BUG. Thanks!

Actually, my initial comment was wrong, so you can ignore it.

Thank
  -- Daniel

-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog



From sergei.shtylyov at cogentembedded.com  Wed May 22 08:59:46 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 22 May 2013 16:59:46 +0400
Subject: [PATCH 02/11] gpio: davinci: coding style correction
In-Reply-To: <1369206634-6778-3-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-3-git-send-email-avinashphilip@ti.com>
Message-ID: <519CC142.7050301@cogentembedded.com>

Hello.

On 22-05-2013 11:10, Philip Avinash wrote:

> 1. Corrects coding and commenting styles
> 2. Variables name change to meaningful name
> 3. Remove unnecessary variable usage
> 4. Add BINTEN macro definition
>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>
> ---
>   drivers/gpio/gpio-davinci.c |  182 +++++++++++++++++++++----------------------
>   1 file changed, 89 insertions(+), 93 deletions(-)

> diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
> index 17df6db..d308955 100644
> --- a/drivers/gpio/gpio-davinci.c
> +++ b/drivers/gpio/gpio-davinci.c
[...]
> @@ -31,10 +31,11 @@ struct davinci_gpio_regs {
>   	u32	intstat;
>   };
>
> +#define BINTEN	0x08 /* GPIO Interrupt Per-Bank Enable Register */

    Empty line needed here.

>   #define chip2controller(chip)	\
>   	container_of(chip, struct davinci_gpio_controller, chip)
>
[...]
> @@ -98,8 +94,8 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
>   	return __davinci_direction(chip, offset, false, 0);
>   }
>
> -static int
> -davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
> +static int davinci_direction_out(struct gpio_chip *chip, unsigned offset,
> +		int value)

     This line should be aligned under the next character after (.

[...]
> @@ -113,22 +109,22 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
[...]
>   /*
>    * Assuming the pin is muxed as a gpio output, set its output value.
>    */
> -static void
> -davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
> +static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
> +		int value)

     Same here.

[...]
> @@ -368,16 +363,16 @@ static int __init davinci_gpio_irq_setup(void)
[...]
>   	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
> -		chips[bank].chip.to_irq = gpio_to_irq_banked;
> -		chips[bank].irq_base = soc_info->gpio_unbanked
> -			? -EINVAL
> -			: (soc_info->intc_irq_num + gpio);
> +		ctlrs[bank].chip.to_irq = gpio_to_irq_banked;
> +		ctlrs[bank].irq_base = soc_info->gpio_unbanked ?
> +			-EINVAL : (soc_info->intc_irq_num + gpio);

    () not needed here.

WBR, Sergei



From arnd at arndb.de  Wed May 22 08:59:34 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 14:59:34 +0200
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <519C7ED3.3030004@freescale.com>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <20130521054323.GE3080@S2101-09.ap.freescale.net>
 <519C7ED3.3030004@freescale.com>
Message-ID: <201305221459.34859.arnd@arndb.de>

On Wednesday 22 May 2013, Huang Shijie wrote:
> ? 2013?05?21? 13:43, Shawn Guo ??:
> > It seems we can find it out from "reg" property, so that we can save
> > this property?
> >
> we may have several devices attaching to the weim, each device has its 
> own CS index.
> it's better to keep this property, make it more clear.

I agree with Shawn, we should not have this property when it is the
same as the upper half of the "reg" property.

	Arnd


From lee.jones at linaro.org  Wed May 22 09:06:35 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 14:06:35 +0100
Subject: [PATCH] ARM: ux500: regulators: Remove misleading comment
Message-ID: <1369227995-17142-1-git-send-email-lee.jones@linaro.org>

This patch removes a comment which explains that the ab8505 platform
uses the same initialisation settings as the ab8500. Well when this
changed and the ab8505 started using its own set of initialisation
values, someone forgot to remove it.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-regulators.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 33c353b..b34441b 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -996,7 +996,6 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
 	.num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
 };
 
-/* Use the AB8500 init settings for AB8505 as they are the same right now */
 struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
 	.reg_init               = ab8505_reg_init,
 	.num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 09:07:05 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 14:07:05 +0100
Subject: [PATCH] regulator: ab8500: Remove external regulator init() clauses
Message-ID: <1369228025-17192-1-git-send-email-lee.jones@linaro.org>

The driver no longer needs to worry about which platform can and can't
use external regulators successfully. Instead platform code will hold
back external regulator initialisation data in the use-cases where the
driver isn't applicable.

Cc: Mark Brown <broonie at kernel.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/regulator/ab8500.c |   10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
index f6656b8..b6270f5 100644
--- a/drivers/regulator/ab8500.c
+++ b/drivers/regulator/ab8500.c
@@ -3156,12 +3156,10 @@ static int ab8500_regulator_probe(struct platform_device *pdev)
 			return err;
 	}
 
-	if (!is_ab8505(ab8500)) {
-		/* register external regulators (before Vaux1, 2 and 3) */
-		err = ab8500_ext_regulator_init(pdev);
-		if (err)
-			return err;
-	}
+	/* register external regulators (before Vaux1, 2 and 3) */
+	err = ab8500_ext_regulator_init(pdev);
+	if (err)
+		return err;
 
 	/* register all regulators */
 	for (i = 0; i < abx500_regulator.info_size; i++) {
-- 
1.7.10.4



From jason at lakedaemon.net  Wed May 22 09:10:10 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 09:10:10 -0400
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <519C9A66.3050807@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
Message-ID: <20130522131010.GB31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 12:13:58PM +0200, Sebastian Hesselbarth wrote:
> On 05/22/2013 12:04 PM, tiejun.chen wrote:
> >On 05/22/2013 05:43 PM, Sebastian Hesselbarth wrote:
> >>On 05/21/2013 07:48 PM, Andrew Lunn wrote:
> >>>On Tue, May 21, 2013 at 06:41:44PM +0200, Sebastian Hesselbarth wrote:
> >>>>This patch adds orion-eth and mvmdio device tree nodes for DT enabled
> >>>>Dove boards. As there is only one ethernet controller on Dove, a
> >>>>default
> >>>>phy node is also added with a note to set its reg property on a
> >>>>per-board
> >>>>basis.
> >>>>
> >>>>Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> >>>>---
> >>...
> >>>>+ ethernet-port at 0 {
> >>>>+ device_type = "network";
> >>>>+ compatible = "marvell,orion-eth-port";
> >>>>+ reg =<0>;
> >>>>+ interrupts =<29>;
> >>>>+ /* overwrite MAC address in bootloader */
> >>>>+ local-mac-address = [00 00 00 00 00 00];
> >>>
> >>>Hi Sebastian
> >>>
> >>>Its probably a good idea to set the local administration bit in this
> >>>MAC address. i.e. first byte is 02.
> >>
> >>Andrew,
> >>
> >>we just need an invalid address here to trigger the default behavior of
> >>the driver and load the MAC address from its register. As PPC binding
> >>documentation also has all zero, I just took it.
> >
> >The truth is in PPC case, often we set the real mac address with some
> >variables like 'eth[x]addr' in u-boot prompt, then u-boot will parse
> >that value to fill the dtb. At last the associated driver can get the
> >actual mac address from the dtb. And especially for those older u-boot
> >version, even you have to reset the 'local-mac-address' property in dts
> >directly with the real mac address before generate the dtb since the
> >older u-boot have no this ability to fill dtb again before pass the kernel.
> 
> Tiejun,
> 
> with Marvell SoCs it is no different, except that there is almost no dtb
> support in their u-boot.

iirc, our solution to this was to parse the ATAGs for the mac addr and
update the appended dtb.  This way, module load and unload would work
without loosing the mac address.  I believe Jason Gunthorpe has a patch
to atags_to_fdt() for this...  This should allow us to get rid of the
clocks hack.

thx,

Jason.


From thomas.petazzoni at free-electrons.com  Wed May 22 09:12:38 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:12:38 +0200
Subject: [PATCH 4/4] pci: mvebu: fix the emulation of the status register
In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369228358-32580-5-git-send-email-thomas.petazzoni@free-electrons.com>

In a PCI configuration header, the 'devsel' bits of the status
register are read-only, and indicate the timing of the secondary
interface. Currently, we implement them as read/write, so when the
Linux PCI core writes all 1's to this register, it gets 11b as the
'devsel' value, which is reserved.

This commit fixes the PCI-to-PCI bridge emulation of the Marvell PCIe
driver to ensure those bits remain set to 00b, which indicate a fast
devsel decoding.

This allows to fix the lspci -v output from:

  Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0

to:

  Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index c887598..d730bf4 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -490,6 +490,11 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
 	case PCI_COMMAND:
 		bridge->command = value & 0xffff;
 		bridge->status = value >> 16;
+		/*
+		 * The devsel bits are read-only, and we want to keep
+		 * them set to 0
+		 */
+		bridge->status &= ~PCI_STATUS_DEVSEL_MASK;
 		break;
 
 	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 22 09:12:34 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:12:34 +0200
Subject: [PATCH 0/4] Marvell PCIe driver improvements
Message-ID: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>

Bjorn, Jason, Andrew, Gregory,

You'll find in this patch series 4 small patches that make various
improvements to the Marvell PCIe driver.

I'd like those improvements to be kept separated from the original
PCIe driver itself: while the PCIe driver has been around and reviewed
for a long time, those improvements are newer. And I clearly do not
want the PCIe driver to miss 3.11 because of any problem that could be
found in those additional improvements.

The main improvement being brought here is that the PCI-to-PCI bridge
logic is fixed/extended to properly support physical PCIe bridges that
are connected on a PCIe interface of a Marvell board. Without this
improvement, only the devices connected directly to the PCIe
interfaces of the board are properly enumerated. Any device that would
sit beyond a physical bridge is not visible.

The other improvements are more minor, and the patch description
should be sufficient to understand what's going on.

Those patches have been tested on both Armada 370/XP and Kirkwood.

Bjorn, with your Acked-by, could the Marvell maintainers include those
patches in their branch, merged through arm-soc? They already have the
Marvell PCIe driver itself, so I believe it makes sense to merge those
improvements through the same path.

Jason, those patches have been prepared on top of my marvell-pcie-v10
branch, I hope that's ok for you. If you want me to rebase them on
some other branch in which you have integrated the PCIe driver, don't
hesitate to tell me to do so. That said, since those patches are only
touching the driver itself and no other file, they should not cause
any conflict with other changes.

Thanks,

Thomas

Thomas Petazzoni (4):
  pci: mvebu: no longer fake the slot location of downstream devices
  pci: mvebu: allow the enumeration of devices beyond physical bridges
  pci: mvebu: emulate an empty capability list
  pci: mvebu: fix the emulation of the status register

 drivers/pci/host/pci-mvebu.c |   65 +++++++++++++++++++++++++++++++++++++-----
 1 file changed, 58 insertions(+), 7 deletions(-)

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 22 09:12:37 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:12:37 +0200
Subject: [PATCH 3/4] pci: mvebu: emulate an empty capability list
In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369228358-32580-4-git-send-email-thomas.petazzoni@free-electrons.com>

Currently, our PCI-to-PCI bridge emulation doesn't emulate a proper
capability list, which leads 'lspci -v' to show:

  Capabilities: [fc] <chain broken>

In order to fix this, this commit improve the PCI-to-PCI bridge
emulation to emulate an empty capability list. It might be later
extended to expose things like the PCI Express Capability header, but
an empty capability list is sufficient for now.

lspci -v now shows the much nicer:

  Capabilities: [40] #00 [0000]

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index c21ca84..c887598 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -440,6 +440,16 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
 		*value = 0;
 		break;
 
+	case PCI_CAPABILITY_LIST:
+		/* Offset of the capability list */
+		*value = 0x40;
+		break;
+
+	case 0x40:
+		/* We have no element in our capability list */
+		*value = 0;
+		break;
+
 	default:
 		*value = 0xffffffff;
 		return PCIBIOS_BAD_REGISTER_NUMBER;
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 22 09:12:36 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:12:36 +0200
Subject: [PATCH 2/4] pci: mvebu: allow the enumeration of devices beyond
 physical bridges
In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369228358-32580-3-git-send-email-thomas.petazzoni@free-electrons.com>

Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.

However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.

This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.

Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:

-[0000:00]-+-01.0-[01]----00.0
           +-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
           |                               +-05.0-[05]--
           |                               +-07.0-[06]--
           |                               \-09.0-[07]----00.0
           \-0a.0-[08]----00.0

Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |   31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 0bc21b0..c21ca84 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -554,7 +554,8 @@ mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
 		if (bus->number == 0 && port->devfn == devfn)
 			return port;
 		if (bus->number != 0 &&
-		    port->bridge.secondary_bus == bus->number)
+		    bus->number >= port->bridge.secondary_bus &&
+		    bus->number <= port->bridge.subordinate_bus)
 			return port;
 	}
 
@@ -578,7 +579,18 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 	if (bus->number == 0)
 		return mvebu_sw_pci_bridge_write(port, where, size, val);
 
-	if (!port->haslink || PCI_SLOT(devfn) != 0)
+	if (!port->haslink)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	/*
+	 * On the secondary bus, we don't want to expose any other
+	 * device that the device physically connected in the PCIe
+	 * slot, visible in slot 0. In slot 1, there's a special
+	 * Marvell device that only makes sense when the Armada is
+	 * used as a PCIe endpoint.
+	 */
+	if (bus->number == port->bridge.secondary_bus &&
+	    PCI_SLOT(devfn) != 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	/* Access the real PCIe interface */
@@ -609,7 +621,20 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 	if (bus->number == 0)
 		return mvebu_sw_pci_bridge_read(port, where, size, val);
 
-	if (!port->haslink || PCI_SLOT(devfn) != 0) {
+	if (!port->haslink) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/*
+	 * On the secondary bus, we don't want to expose any other
+	 * device that the device physically connected in the PCIe
+	 * slot, visible in slot 0. In slot 1, there's a special
+	 * Marvell device that only makes sense when the Armada is
+	 * used as a PCIe endpoint.
+	 */
+	if (bus->number == port->bridge.secondary_bus &&
+	    PCI_SLOT(devfn) != 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Wed May 22 09:12:35 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:12:35 +0200
Subject: [PATCH 1/4] pci: mvebu: no longer fake the slot location of
 downstream devices
In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369228358-32580-2-git-send-email-thomas.petazzoni@free-electrons.com>

By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:

 * On slot 0, a "Marvell Memory controller", identical on all PCIe
   interfaces, and which isn't useful when the Marvell SoC is the PCIe
   root complex (i.e, the normal case when we run Linux on the Marvell
   SoC).

 * On slot 1, the real PCIe card connected into the PCIe slot of the
   board.

So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.

However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.

Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |   19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index ad1c46b..0bc21b0 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -51,6 +51,7 @@
 #define  PCIE_CTRL_X1_MODE		0x0001
 #define PCIE_STAT_OFF		0x1a04
 #define  PCIE_STAT_BUS                  0xff00
+#define  PCIE_STAT_DEV                  0x1f0000
 #define  PCIE_STAT_LINK_DOWN		BIT(0)
 #define PCIE_DEBUG_CTRL         0x1a60
 #define  PCIE_DEBUG_SOFT_RESET		BIT(20)
@@ -148,6 +149,16 @@ static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
 	writel(stat, port->base + PCIE_STAT_OFF);
 }
 
+static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
+{
+	u32 stat;
+
+	stat = readl(port->base + PCIE_STAT_OFF);
+	stat &= ~PCIE_STAT_DEV;
+	stat |= nr << 16;
+	writel(stat, port->base + PCIE_STAT_OFF);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -572,8 +583,7 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 
 	/* Access the real PCIe interface */
 	spin_lock_irqsave(&port->conf_lock, flags);
-	ret = mvebu_pcie_hw_wr_conf(port, bus,
-				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+	ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
 				    where, size, val);
 	spin_unlock_irqrestore(&port->conf_lock, flags);
 
@@ -606,8 +616,7 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 
 	/* Access the real PCIe interface */
 	spin_lock_irqsave(&port->conf_lock, flags);
-	ret = mvebu_pcie_hw_rd_conf(port, bus,
-				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+	ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
 				    where, size, val);
 	spin_unlock_irqrestore(&port->conf_lock, flags);
 
@@ -817,6 +826,8 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
 			continue;
 		}
 
+		mvebu_pcie_set_local_dev_nr(port, 1);
+
 		if (mvebu_pcie_link_up(port)) {
 			port->haslink = 1;
 			dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
-- 
1.7.9.5



From linus.walleij at linaro.org  Wed May 22 09:18:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 May 2013 15:18:01 +0200
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYHiwbGonH80aJfHxP6F+hLb+_KdCr_g5ae1Yr-v=WcxA@mail.gmail.com>

On Wed, May 22, 2013 at 2:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch fixes a bug introduced in the v3.10 merge window.
>
> Some platforms will not want external registers. Rather than setting up
> lots of different clauses in the core ab8500 regulator driver not to
> call ab8500-ext init() we just won't pass the initialisation data from
> platform code. This patch checks for it and if it's missing, we won't
> register the external regulators.
>
> Cc: Mark Brown <broonie at kernel.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/regulator/ab8500-ext.c |    6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/regulator/ab8500-ext.c b/drivers/regulator/ab8500-ext.c
> index b4d4547..8421537 100644
> --- a/drivers/regulator/ab8500-ext.c
> +++ b/drivers/regulator/ab8500-ext.c
> @@ -334,6 +334,12 @@ int ab8500_ext_regulator_init(struct platform_device *pdev)
>                 return -EINVAL;
>         }
>
> +       /* have any external regulators been specified? */
> +       if (pdata->num_ext_regulator == 0) {
> +               dev_warn(&pdev->dev, "Not using external regulators\n");
> +               return 0;
> +       }

dev_warn() is really when we warn about something really nasty, worse
than dev_err(). It seems dev_info() is more apropriate.

Anyway since it's an urgent regression:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Linus


From linus.walleij at linaro.org  Wed May 22 09:20:19 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 May 2013 15:20:19 +0200
Subject: [PATCH] regulator: ab8500: Remove external regulator init()
 clauses
In-Reply-To: <1369228025-17192-1-git-send-email-lee.jones@linaro.org>
References: <1369228025-17192-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda0Oupr56a+Tj7jKCh2vCaD_R0_KVFBe8ZuYQYgVtG2CA@mail.gmail.com>

On Wed, May 22, 2013 at 3:07 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The driver no longer needs to worry about which platform can and can't
> use external regulators successfully. Instead platform code will hold
> back external regulator initialisation data in the use-cases where the
> driver isn't applicable.
>
> Cc: Mark Brown <broonie at kernel.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From andy.shevchenko at gmail.com  Wed May 22 09:26:20 2013
From: andy.shevchenko at gmail.com (Andy Shevchenko)
Date: Wed, 22 May 2013 16:26:20 +0300
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <20130522124112.GA16361@mudshark.cambridge.arm.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <20130521151143.GH10453@mudshark.cambridge.arm.com>
 <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
 <20130522124112.GA16361@mudshark.cambridge.arm.com>
Message-ID: <CAHp75Ve=W7bNYK3Vr_xx41SCHsHtAAA1NcPK1CwetoZNsuVe1Q@mail.gmail.com>

On Wed, May 22, 2013 at 3:41 PM, Will Deacon <will.deacon at arm.com> wrote:
> On Tue, May 21, 2013 at 06:24:15PM +0100, Andy Shevchenko wrote:
>> On Tue, May 21, 2013 at 6:11 PM, Will Deacon <will.deacon at arm.com> wrote:
>> > I now observe buffer verification failures in subsequent
>> > test runs after an aborted run:
>>
>> I think the description to the commit adfa543e "dmatest: don't use
>> set_freezable_with_signal()" may shed light on this.
>>
>> The background (if  I got it correctly) is in race with done flag. So,
>> we got a callback call from the DMA engine, but we don't know which
>> transfer triggers it.
>> I might be wrong. This is just an assumption.
>
> I've not managed to work out exactly what's going on, but it's certainly
> something like that. In fact, I just managed to trigger a case where all but
> one of the transfers is aborted, whilst the remaining one fails. Looking at
> the code, I can't see how that situation comes about, since the threads are
> protected with the info mutex and kthread_stop is synchronous.

>> Have you ever see such behaviour on pre v3.10-rc1 kernels? (I mean
>> with old dmatest module)
>
> No, dmatest from 3.9 is completely reliable in my experience.

Yeah, I supposed that was a rhetorical question.

So, have I understood correctly that if you revert the 77101ce5
("cancel thread ...")
everything is working fine / as before?

--
With Best Regards,
Andy Shevchenko


From thomas.petazzoni at free-electrons.com  Wed May 22 09:27:00 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:27:00 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130522152700.4dab10a1@skate>

Arnd, Olof, Jason, Andrew, Gregory,

(Taking the terrible freedom of doing some top-posting)

As the arm-soc and Marvell maintainers, would you mind having a look
specifically at the below patch, and give your Acked-by or comments?

I believe the other 8 patches that come earlier in this series are
relatively straightforward. However, this specific patch is a bit
complex, and may raise some eye balls.

So rather than having the eye balls raised late in the development
cycle, I'd like to have them raised now, so that if some comments are
made, I have enough time to either discuss them and/or rework the code
accordingly.

Before making comments, please also have a read to the cover letter of
the patch series
(http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/169701.html),
which explains other details of why this solution is needed. The entire
problem cannot be understood if you don't have a serious read at the
commit log and the cover letter.

Thanks,

Thomas

On Tue, 21 May 2013 12:33:34 +0200, Thomas Petazzoni wrote:
> On Marvell platforms, the "internal registers" is a window of 1 MB of
> the physical address space that contains all the registers for the
> various peripherals of the SoC (timers, interrupt controllers, GPIO
> controllers, Ethernet, etc.). The base address of this 1 MB window is
> configurable, and this base address is configured using a register
> that is itself part of this window.
> 
> All earlier families of Marvell EBU SoCs supported by Linux used
> 0xf1000000 as the base address of the internal registers window. For
> some reason, early versions of the Marvell 370/XP platforms used
> 0xd0000000 as the base address. This base address is set up by the
> bootloader. However, in order to keep as much physical address space
> to address RAM below the 4 GB limit, we had to switch the base address
> of the internal registers window back to 0xf1000000, and we wanted to
> achieve that without breaking existing platforms, where the bootloader
> was initially setting the base address to 0xd0000000. So the kernel is
> responsible for switching to 0xf1000000 when needed.
> 
> One particular bit of a CP15 register has been chosen to indicate
> whether we use an old bootloader (setting the address at 0xd0000000)
> or a new bootloader (setting the address at 0xf1000000). In the
> ->map_io() function, when the bit is already set, there is nothing to
> do, we are already using a new bootloader and internal registers are
> at 0xf1000000.
> 
> However, when the bit is not set, we do a static mapping of the
> register area that allows to change the internal register address, we
> change this address, and set this bit.
> 
> Note that this mechanism also needs cooperation from the earlyprintk
> addruart handler (in arch/arm/include/debug/mvebu.S). This is where
> things get complex: the CP15 bit that has been chosen gets reset to
> zero at the first call to the 'wfi' instruction. So it cannot be used
> during the entire life of the system. Instead, whenever the ->map_io()
> function has switched to the internal register space to the new
> address, it sets a global variable 'mvebu_switched_regs', which the
> earlyprintk reads. If it's true, then the move has already been done
> and there is no need to read the CP15 register. If
> 'mvebu_switched_regs' is false, we are before the register move, so we
> need to read the CP15 bit to find out whether we're being booted from
> an old bootloader (which mapped the register space at 0xd0000000) or a
> new bootloader (which mapped the register space at 0xf1000000).
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
>  arch/arm/boot/dts/armada-370.dtsi    |    2 +-
>  arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++++++--
>  arch/arm/mach-mvebu/armada-370-xp.c  |  104 ++++++++++++++++++++++++++++++++++
>  arch/arm/mach-mvebu/armada-370-xp.h  |    2 +-
>  5 files changed, 178 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 96a6bcd..1e7561e 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -33,7 +33,7 @@
>  		#size-cells = <1>;
>  		compatible = "simple-bus";
>  		interrupt-parent = <&mpic>;
> -		ranges = <0 0 0xd0000000 0x100000>;
> +		ranges = <0 0 0xf1000000 0x100000>;
>  
>  		internal-regs {
>  			compatible = "simple-bus";
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> index b2c1b5a..7ff9c1b 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -29,7 +29,7 @@
>  	};
>  
>  	soc {
> -		ranges = <0 0xd0000000 0x100000>;
> +		ranges = <0 0xf1000000 0x100000>;
>  		internal-regs {
>  			system-controller at 18200 {
>  				compatible = "marvell,armada-370-xp-system-controller";
> diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
> index df191af..dba702a 100644
> --- a/arch/arm/include/debug/mvebu.S
> +++ b/arch/arm/include/debug/mvebu.S
> @@ -5,20 +5,85 @@
>   *
>   * Lior Amsalem <alior at marvell.com>
>   * Gregory Clement <gregory.clement at free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
>  */
>  
> -#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> -#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000
> +#define ARMADA_370_XP_UART_PHYS_BASE_OLD	0xd0012000
> +#define ARMADA_370_XP_UART_PHYS_BASE_NEW	0xf1012000
> +#define ARMADA_370_XP_UART_VIRT_BASE_OLD	0xfec12000
> +#define ARMADA_370_XP_UART_VIRT_BASE_NEW	0xfebff000
>  
>  	.macro	addruart, rp, rv, tmp
> -	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
> -	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
> -	orr	\rp, \rp, #0x00012000
> -	orr	\rv, \rv, #0x00012000
> +
> +#ifndef ZIMAGE
> +	/*
> +	 * This loads the value of mvebu_switched_regs. We need a
> +	 * little bit of gymnastic here to handle the fact that the
> +	 * addruart code is duplicated in different places, and called
> +	 * sometimes with the MMU disabled, sometimes the MMU enabled.
> +	 *
> +	 * Notice that when this earlyprintk code is linked into the
> +	 * kernel decompressor (i.e ZIMAGE is defined), this code isn't
> +	 * compiled. The reason is because the global mvebu_switched_regs
> +	 * variable is not available in the decompressor code. At this
> +	 * early stage, we simply test the CP15 bit (below) to know where
> +	 * the internal registers are.
> +	 */
> +	adr	\rp, addruart_switched_regs_\@
> +	ldr	\rv, [\rp]
> +	sub	\rv, \rv, \rp
> +	ldr	\rp, [\rp, #4]
> +	sub	\tmp, \rp, \rv
> +	ldr	\rp, [\tmp, #0]
> +	cmp	\rp, #0
> +
> +	/* If we have already switched, then use the new register
> +	   address */
> +	bne	addruart_new_\@
> +#endif
> +
> +	/*
> +	 * We haven't switched the register location, so test the CP15
> +	 * register bit to find whether we are:
> +	 * - with an old bootloader setting the base address to
> +	 *   0xd0000000
> +	 * - with a new bootloader that has already set the
> +	 *   base address to 0xf1000000
> +	 * We adapt the physical address returned depending on the
> +	 * value of this bit, but also the virtual address, because we
> +	 * can't remap the old physical address and the new physical
> +	 * address at the same location.
> +	 */
> +	mrc	p15, 0, \tmp, c5, c0, 0
> +	and	\tmp, \tmp, #(1 << 11)
> +	cmp	\tmp, #0
> +	bne	addruart_new_\@
> +
> +addruart_old_\@:
> +	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_OLD
> +	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_OLD
> +	b	addruart_out_\@
> +addruart_new_\@:
> +	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_NEW
> +	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_NEW
> +	b	addruart_out_\@
> +
> +#ifndef ZIMAGE
> +	/*
> +	 * Global variable mvebu_switched_regs not visible in the
> +	 * decompressor code
> +	 */
> +	.align
> +addruart_switched_regs_\@:
> +	.long	.
> +	.long	mvebu_switched_regs
> +#endif
> +
> +addruart_out_\@:
>  	.endm
>  
>  #define UART_SHIFT	2
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
> index 90cc0e8..c56875e 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.c
> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
> @@ -29,8 +29,112 @@
>  #include "common.h"
>  #include "coherency.h"
>  
> +/*
> + * Note on the internal register address.
> + *
> + * On Marvell platforms, the "internal registers" is a window of 1 MB
> + * of the physical address space that contains all the registers for
> + * the various peripherals of the SoC (timers, interrupt controllers,
> + * GPIO controllers, Ethernet, etc.). The base address of this 1 MB
> + * window is configurable, and this base address is configured using a
> + * register that is itself part of this window.
> + *
> + * All earlier families of Marvell EBU SoCs supported by Linux used
> + * 0xf1000000 as the base address of the internal registers
> + * window. For some reason, early versions of the Marvell 370/XP
> + * platforms used 0xd0000000 as the base address. This base address is
> + * set up by the bootloader. However, in order to keep as much
> + * physical address space to address RAM below the 4 GB limit, we had
> + * to switch the base address of the internal registers window back to
> + * 0xf1000000, and we wanted to achieve that without breaking existing
> + * platforms, where the bootloader was initially setting the base
> + * address to 0xd0000000. So the kernel is responsible for switching
> + * to 0xf1000000 when needed.
> + *
> + * One particular bit of a CP15 register has been chosen to indicate
> + * whether we use an old bootloader (setting the address at
> + * 0xd0000000) or a new bootloader (setting the address at
> + * 0xf1000000). In the ->map_io() function, when the bit is already
> + * set, there is nothing to do, we are already using a new bootloader
> + * and internal registers are at 0xf1000000.
> + *
> + * However, when the bit is not set, we do a static mapping of the
> + * register area that allows to change the internal register address,
> + * we change this address, and set this bit.
> + *
> + * Note that this mechanism also needs cooperation from the
> + * earlyprintk addruart handler (in arch/arm/include/debug/mvebu.S)
> + * and the early secondary CPU initialization code (in
> + * arch/arm/mach-mvebu/headsmp.S).
> + */
> +
> +#define NEW_INTERNAL_REGS_ADDR  0xf1000000
> +#define OLD_INTERNAL_REGS_ADDR  0xd0000000
> +#define MBUS_OLD_PHYS_ADDR      (OLD_INTERNAL_REGS_ADDR + 0x20000)
> +#define MBUS_OLD_VIRT_ADDR      0xfebfe000
> +#define  MBUS_INTERNAL_REGS_ADDR      0x80
> +
> +/*
> + * We really want this variable to be part of the .data section,
> + * because it gets accessed by the earlyprintk code before BSS gets
> + * initialized to zero. This variable indicates whether the switch to
> + * the new register has taken place or not. It is needed because the
> + * CP15 bit used by the bootloader to tell the kernel where the
> + * registers are mapped is cleared to 0 at the first 'wfi'
> + * instruction. So we can't use it for the entire life of the system,
> + * and we instead use this boolean to indicate to the earlyprintk code
> + * that the switch has occured and it doesn't need to look at the CP15
> + * bit anymore.
> + */
> +unsigned int __section(.data) mvebu_switched_regs = 0;
> +
> +/*
> + * Detect if we're running an old bootloader that has set the physical
> + * base address of internal registers to 0xd0000000
> + */
> +static int armada_370_xp_has_old_bootloader(void)
> +{
> +	u32 val;
> +	asm volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(val));
> +	return !(val & BIT(11));
> +}
> +
>  static void __init armada_370_xp_map_io(void)
>  {
> +	if (armada_370_xp_has_old_bootloader()) {
> +		struct map_desc desc;
> +		void __iomem *mbus = IOMEM(MBUS_OLD_VIRT_ADDR);
> +
> +		desc.virtual = MBUS_OLD_VIRT_ADDR;
> +		desc.pfn     = __phys_to_pfn(MBUS_OLD_PHYS_ADDR);
> +		desc.length  = PAGE_SIZE;
> +		desc.type    = MT_DEVICE;
> +
> +		/*
> +		 * Map the area that contains the registers that
> +		 * allows to change the base address of internal
> +		 * registers.
> +		 */
> +		iotable_init(&desc, 1);
> +
> +		/*
> +		 * Change the physical base address of the
> +		 * registers. From now on, and until
> +		 * debug_ll_io_init() is called below, it is not
> +		 * possible to do any print, because earlyprintk will
> +		 * not work.
> +		 */
> +		writel(NEW_INTERNAL_REGS_ADDR, mbus + MBUS_INTERNAL_REGS_ADDR);
> +	}
> +
> +	/*
> +	 * Either the registers have been switched by the above code,
> +	 * or the bootloader had already set the register space at the
> +	 * right location. In both cases, tell the earlyprintk code it
> +	 * can now use the new location.
> +	 */
> +	mvebu_switched_regs = 1;
> +
>  	debug_ll_io_init();
>  }
>  
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
> index 585e147..ff9adc4 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.h
> +++ b/arch/arm/mach-mvebu/armada-370-xp.h
> @@ -15,7 +15,7 @@
>  #ifndef __MACH_ARMADA_370_XP_H
>  #define __MACH_ARMADA_370_XP_H
>  
> -#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> +#define ARMADA_370_XP_REGS_PHYS_BASE	0xf1000000
>  
>  /* These defines can go away once mvebu-mbus has a DT binding */
>  #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)



-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From t.figa at samsung.com  Wed May 22 09:32:36 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 22 May 2013 15:32:36 +0200
Subject: [PATCH v2 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <4536937.hnhaYZLnaG@amdc1227>
 <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>
Message-ID: <4391865.a7p9jbyZ7B@amdc1227>

On Tuesday 21 of May 2013 21:46:35 Doug Anderson wrote:
> Tomasz,
> 
> On Tue, May 21, 2013 at 10:05 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> >         return 0;
> > 
> > +
> > +err_domains:
> > +       bank = d->ctrl->pin_banks;
> > +       for (undo = 0; undo < i; ++undo) {
> 
> ++bank is missing, I think.  This will free the same bank many times.

Shit, this is what happens when you post patches so late and in a hurry. Will 
send something sane in a while.

> optional: could also avoid extra 'undo' variable and remove in reverse
> order by changing i to signed and counting down to 0.

Sure.

Best regards,
Tomasz

> -Doug
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From linux at arm.linux.org.uk  Wed May 22 09:33:17 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 May 2013 14:33:17 +0100
Subject: [PATCH] kernel/sched/core.c: need return NULL when BUG() is
 defined as empty.
In-Reply-To: <20130522091156.GC18810@twins.programming.kicks-ass.net>
References: <5199D565.4070307@asianux.com>
 <20130522091156.GC18810@twins.programming.kicks-ass.net>
Message-ID: <20130522133317.GC18614@n2100.arm.linux.org.uk>

On Wed, May 22, 2013 at 11:11:56AM +0200, Peter Zijlstra wrote:
> On Mon, May 20, 2013 at 03:48:53PM +0800, Chen Gang wrote:
> > 
> > When neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, need let function
> > return failure value ('NULL') instead of random value.
> 
> What will such a kernel do? Happily continue running whenever we hit a
> BUG? that seems like a particularly bad idea. Should we not have a stub
> BUG() function like:
> 
> void BUG(void) __attribute__((noreturn))
> {
> 	local_irq_disable();
> 	while (1) ;
> }

Eww.  So you've a platform where you have things like panic_on_oops
enabled, and you hit this bug... do we really want to just stop?
Wouldn't replacing BUG() with panic("BUG"); be better ?

But, this begs the question - what is the point of being able to turn
off BUG() ?  As BUG() on any sensible architecture is implemented by
placing the minimum of code at the callsite (eg, one instruction if
not using verbose) anything like the above is likely to be bigger.

So, I'd actually argue that rather than trying to "fix" this, get rid
of CONFIG_BUG and make it always enabled everywhere - just like what
has recently been done with hotplug.


From tjohnson at fcu.org  Wed May 22 09:39:33 2013
From: tjohnson at fcu.org (labiopharyngealu)
Date: Wed, 22 May 2013 16:39:33 +0300
Subject: =?windows-1251?B?0eDs7uUg4evg4+7v8Oj/8u3u5SDv8OXk6+7m?=
 =?windows-1251?B?5e3o5SDk6/8g4ujn6PLl8O7iIO3g+OXj7iDx?=
 =?windows-1251?B?4Ony4A==?=
Message-ID: <F6A5365CD62B48B3839D57D74E5FA32B@eqhtiy>

???????????????? ??????????? ?? ???????? ? ??? ?? ?????  http://goo.gl/tDXfv?/eJrBxb ??? ?????? ????????? ? ???: ? ???? ????, ??? ??? ? ? ??????????? ??????????? ???????? ?, ??????? ? ??????????? ?? ????? ???????. ???? ????? ? ???? ??? ?????? ? ??? ??????????? ????? ???????.


From festevam at gmail.com  Wed May 22 09:41:47 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 22 May 2013 10:41:47 -0300
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <201305221219.43558.jbe@pengutronix.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5AWBi4gDJCOJf5muFuRXygQAysYCHEL+gb_LwsXiy-knA@mail.gmail.com>
 <CAOMZO5AKKVeTMsXpG9wa-eeLocBStUwPjQEe3n6fRVY2aSc7Nw@mail.gmail.com>
 <201305221219.43558.jbe@pengutronix.de>
Message-ID: <CAOMZO5Cd19Jx0sXdD55hat579E9CsPqWEKS-FQfVz5LMmuvXjw@mail.gmail.com>

Hi Juergen,

On Wed, May 22, 2013 at 7:19 AM, Juergen Beisert <jbe at pengutronix.de> wrote:
> Hi Fabio,
>
>> i2c slowness is a different issue.
>
> Same happens here for my i.M23 based platform. It seems the PIO mode does not
> work, or at least not like it works on a i.MX28. Each short transfer needs
> about one second (without an error message) but does not send anything on the
> I2C lines.
>
> I need the following patches to make I2C master work within a 3.10-rc2 kernel:

Thanks, I tried forcing dma mode and I got the following probe issue
on a mx28evk running today's linux-next:

[    6.403193] mxs-sgtl5000 sound.12: ASoC: CODEC (null) not registered
[    6.412175] mxs-sgtl5000 sound.12: snd_soc_register_card failed (-517)
[    6.425582] platform sound.12: Driver mxs-sgtl5000 requests probe deferral
[    6.434043]  mmcblk0: p1 p2 p3
[    6.439586] stmp3xxx-rtc 80056000.rtc: setting system clock to
2013-04-23 21:00:42 UTC (1366750842)
[    6.458141] mxs-sgtl5000 sound.12: ASoC: CODEC (null) not registered
[    6.464773] mxs-sgtl5000 sound.12: snd_soc_register_card failed (-517)

If I run linux-next with 2f769432d8554 reverted then I get a 23
seconds delay in the probe (1 second for each sgtl5000 register
write).

Regards,

Fabio Estevam


From jason at lakedaemon.net  Wed May 22 09:43:19 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 09:43:19 -0400
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130522134319.GC31290@titan.lakedaemon.net>

Thomas,

On Wed, May 22, 2013 at 03:12:34PM +0200, Thomas Petazzoni wrote:
> Bjorn, Jason, Andrew, Gregory,
> 
> You'll find in this patch series 4 small patches that make various
> improvements to the Marvell PCIe driver.
> 
> I'd like those improvements to be kept separated from the original
> PCIe driver itself: while the PCIe driver has been around and reviewed
> for a long time, those improvements are newer. And I clearly do not
> want the PCIe driver to miss 3.11 because of any problem that could be
> found in those additional improvements.

Agreed.

For Bjorn and others:

The original patch series Thomas is referring to missed the merge window
for v3.10 due to a build failure.  It is currently sitting in our mvebu
repo.  The first three patches, "of/pci ..." are in mvebu/of_pci.  The
rest of the series is on top of that in the branch mvebu/pcie.

I've sent pull requests for both branches to arm-soc.  There are two
other arm SoC pcie efforts which are depending on mvebu/of_pci.  Hence
why I did a separate branch.

Both branches are also merged into mvebu/for-next, and have survived
linux-next for three days or so.  But, it's early, so we'll see how it
goes. :-)

> Bjorn, with your Acked-by, could the Marvell maintainers include those
> patches in their branch, merged through arm-soc? They already have the
> Marvell PCIe driver itself, so I believe it makes sense to merge those
> improvements through the same path.

I agree, please see above regarding arm-soc dependencies.

> Jason, those patches have been prepared on top of my marvell-pcie-v10
> branch, I hope that's ok for you. If you want me to rebase them on
> some other branch in which you have integrated the PCIe driver, don't
> hesitate to tell me to do so. That said, since those patches are only
> touching the driver itself and no other file, they should not cause
> any conflict with other changes.

Should be fine, I'll let you know.

thx,

Jason.


From linux at arm.linux.org.uk  Wed May 22 09:41:24 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 May 2013 14:41:24 +0100
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <201305221125.36284.arnd@arndb.de>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
Message-ID: <20130522134124.GD18614@n2100.arm.linux.org.uk>

On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> Given the most commonly used functions and a couple of architectures
> I'm familiar with, these are the ones that currently call might_fault()
> 
> 			x86-32	x86-64	arm	arm64	powerpc	s390	generic
> copy_to_user		-	x	-	-	-	x	x
> copy_from_user		-	x	-	-	-	x	x
> put_user		x	x	x	x	x	x	x
> get_user		x	x	x	x	x	x	x
> __copy_to_user		x	x	-	-	x	-	-
> __copy_from_user	x	x	-	-	x	-	-
> __put_user		-	-	x	-	x	-	-
> __get_user		-	-	x	-	x	-	-
> 
> WTF?

I think your table is rather screwed - especially on ARM.  Tell me -
how can __copy_to_user() use might_fault() but copy_to_user() not when
copy_to_user() is implemented using __copy_to_user() ?  Same for
copy_from_user() but the reverse argument - there's nothing special
in our copy_from_user() which would make it do might_fault() when
__copy_from_user() wouldn't.

The correct position for ARM is: our (__)?(pu|ge)t_user all use
might_fault(), but (__)?copy_(to|from)_user do not.  Neither does
(__)?clear_user.  We might want to fix those to use might_fault().


From sergei.shtylyov at cogentembedded.com  Wed May 22 09:43:51 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 22 May 2013 17:43:51 +0400
Subject: [PATCH] ARM: shmobile: kzm9g-reference: Update CMT clocksource
 rating to 80
In-Reply-To: <1369226980-16203-1-git-send-email-horms+renesas@verge.net.au>
References: <1369226980-16203-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <519CCB97.20207@cogentembedded.com>

Hello.

On 22-05-2013 16:49, Simon Horman wrote:

> Update the CMT clocksource rating from 100 to 10.

    s/100/125/ and s/10/80/, apparently.

> This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
> introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
> Avoid dummy clockevent being preferred over real").

> The patch noted above reduces the rating of dummy clockevent from 400 to 100.

    400 seems very high rating for a dummy clockevent...

> This patch reduces the rating of CMT so that it is once again less than that
> of the dummy clockevent.

> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

> ---

> I also plan to reduce the rating of the STI clocksource to less than 100.
> However, as I am not aware of any problems relating to STI in v3.10-rc
> my plan is to update STI in the v3.11 timeframe.
> ---
>   arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

> diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> index fdf3894..9696f36 100644
> --- a/arch/arm/mach-shmobile/setup-sh73a0.c
> +++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> @@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
>   	.name = "CMT10",
>   	.channel_offset = 0x10,
>   	.timer_bit = 0,
> -	.clockevent_rating = 125,
> +	.clockevent_rating = 80,
>   	.clocksource_rating = 125,
>   };

WBR, Sergei




From linux at arm.linux.org.uk  Wed May 22 09:43:36 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 May 2013 14:43:36 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <519C9779.1040104@gmail.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu> <519C9779.1040104@gmail.com>
Message-ID: <20130522134336.GE18614@n2100.arm.linux.org.uk>

On Wed, May 22, 2013 at 12:01:29PM +0200, Sebastian Hesselbarth wrote:
> I tried the above on Dove which is possibly affected by the workaround
> as it is also ARMv7. In Dove you can access unmapped addresses without
> any problems, but as Thomas already stated Armada 370/XP just hang.
> Must be some default AHB slave in Dove, which Armada 370/XP is missing.

It may be some clock setting somewhere on the 370/XP.  The Dove will hang
as well if you prod at peripherals which you've turned their clocks off.


From thomas.petazzoni at free-electrons.com  Wed May 22 09:52:18 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 15:52:18 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522134336.GE18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu> <519C9779.1040104@gmail.com>
 <20130522134336.GE18614@n2100.arm.linux.org.uk>
Message-ID: <20130522155218.1c2af492@skate>

Dear Russell King - ARM Linux,

On Wed, 22 May 2013 14:43:36 +0100, Russell King - ARM Linux wrote:
> On Wed, May 22, 2013 at 12:01:29PM +0200, Sebastian Hesselbarth wrote:
> > I tried the above on Dove which is possibly affected by the workaround
> > as it is also ARMv7. In Dove you can access unmapped addresses without
> > any problems, but as Thomas already stated Armada 370/XP just hang.
> > Must be some default AHB slave in Dove, which Armada 370/XP is missing.
> 
> It may be some clock setting somewhere on the 370/XP.  The Dove will hang
> as well if you prod at peripherals which you've turned their clocks off.

The register in question (offset 0x20080 from the base address of the
internal register) is part of the "core" registers, so I clearly don't
see how the system could even be booting if this clock was gated. No?

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From horms at verge.net.au  Wed May 22 09:56:13 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 22:56:13 +0900
Subject: [PATCH] ARM: shmobile: kzm9g-reference: Update CMT clocksource
 rating to 80
In-Reply-To: <519CCB97.20207@cogentembedded.com>
References: <1369226980-16203-1-git-send-email-horms+renesas@verge.net.au>
 <519CCB97.20207@cogentembedded.com>
Message-ID: <20130522135608.GA32012@verge.net.au>

On Wed, May 22, 2013 at 05:43:51PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 22-05-2013 16:49, Simon Horman wrote:
> 
> >Update the CMT clocksource rating from 100 to 10.
> 
>    s/100/125/ and s/10/80/, apparently.

Thanks, I don't know what I was thinking.

> 
> >This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
> >introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
> >Avoid dummy clockevent being preferred over real").
> 
> >The patch noted above reduces the rating of dummy clockevent from 400 to 100.
> 
>    400 seems very high rating for a dummy clockevent...
> 
> >This patch reduces the rating of CMT so that it is once again less than that
> >of the dummy clockevent.
> 
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> >---
> 
> >I also plan to reduce the rating of the STI clocksource to less than 100.
> >However, as I am not aware of any problems relating to STI in v3.10-rc
> >my plan is to update STI in the v3.11 timeframe.
> >---
> >  arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> >diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> >index fdf3894..9696f36 100644
> >--- a/arch/arm/mach-shmobile/setup-sh73a0.c
> >+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> >@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
> >  	.name = "CMT10",
> >  	.channel_offset = 0x10,
> >  	.timer_bit = 0,
> >-	.clockevent_rating = 125,
> >+	.clockevent_rating = 80,
> >  	.clocksource_rating = 125,
> >  };
> 
> WBR, Sergei
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From arnd at arndb.de  Wed May 22 09:59:01 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 15:59:01 +0200
Subject: [PATCH v2 07/10] powerpc: uaccess s/might_sleep/might_fault/
In-Reply-To: <2aa6c3da21a28120126732b5e0b4ecd6cba8ca3b.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <2aa6c3da21a28120126732b5e0b4ecd6cba8ca3b.1368702323.git.mst@redhat.com>
Message-ID: <201305221559.01806.arnd@arndb.de>

On Thursday 16 May 2013, Michael S. Tsirkin wrote:
> @@ -178,7 +178,7 @@ do {                                                                \
>         long __pu_err;                                          \
>         __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
>         if (!is_kernel_addr((unsigned long)__pu_addr))          \
> -               might_sleep();                                  \
> +               might_fault();                                  \
>         __chk_user_ptr(ptr);                                    \
>         __put_user_size((x), __pu_addr, (size), __pu_err);      \
>         __pu_err;                                               \
> 

Another observation:

	if (!is_kernel_addr((unsigned long)__pu_addr))
		might_sleep();

is almost the same as

	might_fault();

except that it does not call might_lock_read().

The version above may have been put there intentionally and correctly, but
if you want to replace it with might_fault(), you should remove the
"if ()" condition.

	Arnd


From t.figa at samsung.com  Wed May 22 10:03:17 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 22 May 2013 16:03:17 +0200
Subject: [PATCH v3 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <4536937.hnhaYZLnaG@amdc1227>
 <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>
Message-ID: <3059629.yu4Ei1BXhd@amdc1227>

Some GPIO EINT control registers needs to be preserved across
suspend/resume cycle. This patch extends the driver to take care of
this.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---

Changes since v2:
 - Fixed error path
Changes since v1:
 - Added optional debugging messages
 - Added proper error path in initialization

 drivers/pinctrl/pinctrl-exynos.c | 116 ++++++++++++++++++++++++++++++++++++++-
 drivers/pinctrl/pinctrl-exynos.h |   1 +
 2 files changed, 114 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 4f868e5..2d76f66 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -196,6 +196,12 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+struct exynos_eint_gpio_save {
+	u32 eint_con;
+	u32 eint_fltcon0;
+	u32 eint_fltcon1;
+};
+
 /*
  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
  * @d: driver data of samsung pinctrl driver.
@@ -204,8 +210,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 {
 	struct samsung_pin_bank *bank;
 	struct device *dev = d->dev;
-	unsigned int ret;
-	unsigned int i;
+	int ret;
+	int i;
 
 	if (!d->irq) {
 		dev_err(dev, "irq number not available\n");
@@ -227,11 +233,29 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 				bank->nr_pins, &exynos_gpio_irqd_ops, bank);
 		if (!bank->irq_domain) {
 			dev_err(dev, "gpio irq domain add failed\n");
-			return -ENXIO;
+			ret = -ENXIO;
+			goto err_domains;
+		}
+
+		bank->soc_priv = devm_kzalloc(d->dev,
+			sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
+		if (!bank->soc_priv) {
+			irq_domain_remove(bank->irq_domain);
+			ret = -ENOMEM;
+			goto err_domains;
 		}
 	}
 
 	return 0;
+
+err_domains:
+	for (--i, --bank; i >= 0; --i, --bank) {
+		if (bank->eint_type != EINT_TYPE_GPIO)
+			continue;
+		irq_domain_remove(bank->irq_domain);
+	}
+
+	return ret;
 }
 
 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
@@ -528,6 +552,72 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 	return 0;
 }
 
+static void exynos_pinctrl_suspend_bank(
+				struct samsung_pinctrl_drv_data *drvdata,
+				struct samsung_pin_bank *bank)
+{
+	struct exynos_eint_gpio_save *save = bank->soc_priv;
+	void __iomem *regs = drvdata->virt_base;
+
+	save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+						+ bank->eint_offset);
+	save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset);
+	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset + 4);
+
+	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
+	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
+	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
+}
+
+static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+		if (bank->eint_type == EINT_TYPE_GPIO)
+			exynos_pinctrl_suspend_bank(drvdata, bank);
+}
+
+static void exynos_pinctrl_resume_bank(
+				struct samsung_pinctrl_drv_data *drvdata,
+				struct samsung_pin_bank *bank)
+{
+	struct exynos_eint_gpio_save *save = bank->soc_priv;
+	void __iomem *regs = drvdata->virt_base;
+
+	pr_debug("%s:     con %#010x => %#010x\n", bank->name,
+			readl(regs + EXYNOS_GPIO_ECON_OFFSET
+			+ bank->eint_offset), save->eint_con);
+	pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
+			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+			+ 2 * bank->eint_offset), save->eint_fltcon0);
+	pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
+			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
+
+	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+						+ bank->eint_offset);
+	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset);
+	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+						+ 2 * bank->eint_offset + 4);
+}
+
+static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+		if (bank->eint_type == EINT_TYPE_GPIO)
+			exynos_pinctrl_resume_bank(drvdata, bank);
+}
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -591,6 +681,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4210-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -605,6 +697,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4210-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -686,6 +780,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -700,6 +796,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -710,6 +808,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl2",
 	}, {
 		/* pin-controller instance 3 data */
@@ -720,6 +820,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos4x12-gpio-ctrl3",
 	},
 };
@@ -798,6 +900,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl0",
 	}, {
 		/* pin-controller instance 1 data */
@@ -808,6 +912,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl1",
 	}, {
 		/* pin-controller instance 2 data */
@@ -818,6 +924,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl2",
 	}, {
 		/* pin-controller instance 3 data */
@@ -828,6 +936,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
 		.svc		= EXYNOS_SVC_OFFSET,
 		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
 		.label		= "exynos5250-gpio-ctrl3",
 	},
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 9b1f77a..3c91c35 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -19,6 +19,7 @@
 
 /* External GPIO and wakeup interrupt related definitions */
 #define EXYNOS_GPIO_ECON_OFFSET		0x700
+#define EXYNOS_GPIO_EFLTCON_OFFSET	0x800
 #define EXYNOS_GPIO_EMASK_OFFSET	0x900
 #define EXYNOS_GPIO_EPEND_OFFSET	0xA00
 #define EXYNOS_WKUP_ECON_OFFSET		0xE00
-- 
1.8.2.1




From andrew at lunn.ch  Wed May 22 10:04:44 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 16:04:44 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <20130522152700.4dab10a1@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522152700.4dab10a1@skate>
Message-ID: <20130522140444.GK2824@lunn.ch>

On Wed, May 22, 2013 at 03:27:00PM +0200, Thomas Petazzoni wrote:
> Arnd, Olof, Jason, Andrew, Gregory,
> 
> (Taking the terrible freedom of doing some top-posting)
> 
> As the arm-soc and Marvell maintainers, would you mind having a look
> specifically at the below patch, and give your Acked-by or comments?
> 
> I believe the other 8 patches that come earlier in this series are
> relatively straightforward. However, this specific patch is a bit
> complex, and may raise some eye balls.
> 
> So rather than having the eye balls raised late in the development
> cycle, I'd like to have them raised now, so that if some comments are
> made, I have enough time to either discuss them and/or rework the code
> accordingly.
> 
> Before making comments, please also have a read to the cover letter of
> the patch series
> (http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/169701.html),
> which explains other details of why this solution is needed. The entire
> problem cannot be understood if you don't have a serious read at the
> commit log and the cover letter.

Hi Thomas

You gave a good explanation why the CP15 bit its needed, etc. I liked
the comment.

It might be worth cross posting both u-boot and barebox lists, since
they are somewhat involved as well. Are there any other boot loaders
used on 370 and XP.

What happens with future chips. 375 springs to mind. I assume its
Marvell bootloader will do the mapping before handing over to
Linux. Is it required to also set the bit in CP15? Are we setting off
down a road where all future Marvell chips which are compatible with
370/XP now need to set this bit?

How does this effect dove? It will get compiled into the same multi
arch kernel as 370/XP. I'm thinking about
arch/arm/include/debug/mvebu.S which might be shared. Dove is not
going to have this bit set. Kirkwood could also share this code, now
that the serial ports are all in the same location.

What does the ARM reference documentation say about this bit? Is its
meaning defined? Is there any danger when this bit is used for its
intended purpose?

	Andrew


From arnd at arndb.de  Wed May 22 10:04:48 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 16:04:48 +0200
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <20130522134124.GD18614@n2100.arm.linux.org.uk>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
 <20130522134124.GD18614@n2100.arm.linux.org.uk>
Message-ID: <201305221604.49185.arnd@arndb.de>

On Wednesday 22 May 2013, Russell King - ARM Linux wrote:
> On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> > Given the most commonly used functions and a couple of architectures
> > I'm familiar with, these are the ones that currently call might_fault()
> > 
> >                       x86-32  x86-64  arm     arm64   powerpc s390    generic
> > copy_to_user          -       x       -       -       -       x       x
> > copy_from_user        -       x       -       -       -       x       x
> > put_user              x       x       x       x       x       x       x
> > get_user              x       x       x       x       x       x       x
> > __copy_to_user        x       x       -       -       x       -       -
> > __copy_from_user      x       x       -       -       x       -       -
> > __put_user            -       -       x       -       x       -       -
> > __get_user            -       -       x       -       x       -       -
> > 
> > WTF?
> 
> I think your table is rather screwed - especially on ARM.  Tell me -
> how can __copy_to_user() use might_fault() but copy_to_user() not when
> copy_to_user() is implemented using __copy_to_user() ?  Same for
> copy_from_user() but the reverse argument - there's nothing special
> in our copy_from_user() which would make it do might_fault() when
> __copy_from_user() wouldn't.

I think something went wrong with formatting of the tabstobs in
the table. I've tried to correct it above to the same version I
see on the mailing list.

> The correct position for ARM is: our (__)?(pu|ge)t_user all use
> might_fault(), but (__)?copy_(to|from)_user do not.  Neither does
> (__)?clear_user.  We might want to fix those to use might_fault().

Yes, that sounds like a good idea, especially since they are all
implemented out-of-line.

For __get_user()/__put_user(), I would probably do the reverse and make
them not call might_fault() though, like we do on most other architectures:

Look at the object code produced for setup_sigframe for instance, it calls
might_fault() around 25 times where one should really be enough. Using
__put_user() instead of put_user() is normally an indication that the
author of that function has made performance considerations and move the
(trivial) access_ok() call out, but now we add a more expensive
call instead.

	Arnd


From arnd at arndb.de  Wed May 22 10:08:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 16:08:10 +0200
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <CACRpkdYHiwbGonH80aJfHxP6F+hLb+_KdCr_g5ae1Yr-v=WcxA@mail.gmail.com>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdYHiwbGonH80aJfHxP6F+hLb+_KdCr_g5ae1Yr-v=WcxA@mail.gmail.com>
Message-ID: <201305221608.10759.arnd@arndb.de>

On Wednesday 22 May 2013, Linus Walleij wrote:
> > diff --git a/drivers/regulator/ab8500-ext.c b/drivers/regulator/ab8500-ext.c
> > index b4d4547..8421537 100644
> > --- a/drivers/regulator/ab8500-ext.c
> > +++ b/drivers/regulator/ab8500-ext.c
> > @@ -334,6 +334,12 @@ int ab8500_ext_regulator_init(struct platform_device *pdev)
> >                 return -EINVAL;
> >         }
> >
> > +       /* have any external regulators been specified? */
> > +       if (pdata->num_ext_regulator == 0) {
> > +               dev_warn(&pdev->dev, "Not using external regulators\n");
> > +               return 0;
> > +       }
> 
> dev_warn() is really when we warn about something really nasty, worse
> than dev_err(). It seems dev_info() is more apropriate.

Are you confusing it with dev_crit()?

This is how the levels are defined, and "warning" is less urgent than "error":

#define KERN_EMERG      KERN_SOH "0"    /* system is unusable */
#define KERN_ALERT      KERN_SOH "1"    /* action must be taken immediately */
#define KERN_CRIT       KERN_SOH "2"    /* critical conditions */
#define KERN_ERR        KERN_SOH "3"    /* error conditions */
#define KERN_WARNING    KERN_SOH "4"    /* warning conditions */
#define KERN_NOTICE     KERN_SOH "5"    /* normal but significant condition */
#define KERN_INFO       KERN_SOH "6"    /* informational */
#define KERN_DEBUG      KERN_SOH "7"    /* debug-level messages */

	Arnd


From florian.meier at koalo.de  Wed May 22 10:10:20 2013
From: florian.meier at koalo.de (Florian Meier)
Date: Wed, 22 May 2013 16:10:20 +0200
Subject: [PATCH] ASoC: Add support for BCM2708
Message-ID: <519CD1CC.8070507@koalo.de>

This driver adds support for digital audio (I2S)
for the BCM2708 SoC that is used by the
Raspberry Pi. External audio codecs can be
connected to the Raspberry Pi via P5 header.

It relies on cyclic DMA engine support for BCM2708
that is not included in this patch.

The currently supported audio codecs are
TLV320AIC23 and WM8731.

Signed-off-by: Florian Meier <florian.meier at koalo.de>
---

A Raspberry Pi kernel featuring this driver can be found at
https://github.com/koalo/linux rpi-3.8.y-asocdev

You can find more information about how to use it at
http://blog.koalo.de/2013/05/i2s-support-for-raspberry-pi.html

 sound/soc/Kconfig               |    1 +
 sound/soc/Makefile              |    1 +
 sound/soc/bcm2708/Kconfig       |   29 ++
 sound/soc/bcm2708/Makefile      |   12 +
 sound/soc/bcm2708/bcm2708-i2s.c |  964 +++++++++++++++++++++++++++++++++++++++
 sound/soc/bcm2708/bcm2708-pcm.c |  303 ++++++++++++
 sound/soc/bcm2708/bcm2708-pcm.h |   40 ++
 sound/soc/bcm2708/rpi-mbed.c    |  113 +++++
 sound/soc/bcm2708/rpi-proto.c   |  131 ++++++
 9 files changed, 1594 insertions(+)
 create mode 100644 sound/soc/bcm2708/Kconfig
 create mode 100644 sound/soc/bcm2708/Makefile
 create mode 100644 sound/soc/bcm2708/bcm2708-i2s.c
 create mode 100644 sound/soc/bcm2708/bcm2708-pcm.c
 create mode 100644 sound/soc/bcm2708/bcm2708-pcm.h
 create mode 100644 sound/soc/bcm2708/rpi-mbed.c
 create mode 100644 sound/soc/bcm2708/rpi-proto.c

diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 9e675c7..d3852f8 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -36,6 +36,7 @@ config SND_SOC_GENERIC_DMAENGINE_PCM
 # All the supported SoCs
 source "sound/soc/atmel/Kconfig"
 source "sound/soc/au1x/Kconfig"
+source "sound/soc/bcm2708/Kconfig"
 source "sound/soc/blackfin/Kconfig"
 source "sound/soc/cirrus/Kconfig"
 source "sound/soc/davinci/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 197b6ae..eef1a7b 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SND_SOC)	+= codecs/
 obj-$(CONFIG_SND_SOC)	+= generic/
 obj-$(CONFIG_SND_SOC)	+= atmel/
 obj-$(CONFIG_SND_SOC)	+= au1x/
+obj-$(CONFIG_SND_SOC)	+= bcm2708/
 obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= cirrus/
 obj-$(CONFIG_SND_SOC)	+= davinci/
diff --git a/sound/soc/bcm2708/Kconfig b/sound/soc/bcm2708/Kconfig
new file mode 100644
index 0000000..f47c2c0
--- /dev/null
+++ b/sound/soc/bcm2708/Kconfig
@@ -0,0 +1,29 @@
+config SND_BCM2708_SOC_I2S
+	tristate
+
+config SND_BCM2708_SOC
+	tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
+	depends on MACH_BCM2708
+	select SND_SOC_DMAENGINE_PCM
+	select DMA_BCM2708
+	select SND_SOC_GENERIC_DMAENGINE_PCM
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the BCM2708 I2S interface. You will also need
+	  to select the audio interfaces to support below.
+
+config SND_BCM2708_SOC_RPI_CODEC_MBED
+	tristate "Support for AudioCODEC for mbed (TLV320AIC32B)"
+	depends on SND_BCM2708_SOC
+	select SND_BCM2708_SOC_I2S
+	select SND_SOC_TLV320AIC3X
+	help
+	  Say Y if you want to add support for AudioCODEC for mbed (TLV320AIC32B)
+
+config SND_BCM2708_SOC_RPI_CODEC_PROTO
+	tristate "Support for Audio Codec Board - PROTO (WM8731)"
+	depends on SND_BCM2708_SOC
+	select SND_BCM2708_SOC_I2S
+	select SND_SOC_WM8731
+	help
+	  Say Y if you want to add support for Audio Codec Board - PROTO (WM8731)
diff --git a/sound/soc/bcm2708/Makefile b/sound/soc/bcm2708/Makefile
new file mode 100644
index 0000000..284d76d
--- /dev/null
+++ b/sound/soc/bcm2708/Makefile
@@ -0,0 +1,12 @@
+# BCM2708 Platform Support
+snd-soc-bcm2708-objs := bcm2708-pcm.o
+snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
+snd-soc-rpi-mbed-objs := rpi-mbed.o
+snd-soc-rpi-proto-objs := rpi-proto.o
+
+obj-$(CONFIG_SND_BCM2708_SOC) += snd-soc-bcm2708.o
+obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
+
+# BCM2708 Machine Support
+obj-$(CONFIG_SND_BCM2708_SOC_RPI_CODEC_MBED) += snd-soc-rpi-mbed.o
+obj-$(CONFIG_SND_BCM2708_SOC_RPI_CODEC_PROTO) += snd-soc-rpi-proto.o
diff --git a/sound/soc/bcm2708/bcm2708-i2s.c b/sound/soc/bcm2708/bcm2708-i2s.c
new file mode 100644
index 0000000..a8e995f
--- /dev/null
+++ b/sound/soc/bcm2708/bcm2708-i2s.c
@@ -0,0 +1,964 @@
+/*
+ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
+ *
+ * Author:	Florian Meier, <florian.meier at koalo.de>
+ *		Copyright 2013
+ *
+ * based on
+ *	Raspberry Pi PCM I2S ALSA Driver
+ *	Copyright (c) by Phil Poole 2013
+ *
+ *	ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
+ *      Vladimir Barinov, <vbarinov at embeddedalley.com>
+ *	Copyright (C) 2007 MontaVista Software, Inc., <source at mvista.com>
+ *
+ *	OMAP ALSA SoC DAI driver using McBSP port
+ *	Copyright (C) 2008 Nokia Corporation
+ *	Contact: Jarkko Nikula <jarkko.nikula at bitmer.com>
+ *		 Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ *	Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
+ *	Author: Timur Tabi <timur at freescale.com>
+ *	Copyright 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include "bcm2708-pcm.h"
+
+/* Clock registers */
+#define BCM2708_CLK_PCMCTL_REG  0x00
+#define BCM2708_CLK_PCMDIV_REG  0x04
+
+/* Clock register settings */
+#define BCM2708_CLK_PASSWD	(0x5a000000)
+#define BCM2708_CLK_MASH(v)	((v) << 9)
+#define BCM2708_CLK_FLIP	(1 << 8)
+#define BCM2708_CLK_BUSY	(1 << 7)
+#define BCM2708_CLK_KILL	(1 << 5)
+#define BCM2708_CLK_ENAB	(1 << 4)
+#define BCM2708_CLK_SRC(v)	(v)
+
+#define BCM2708_CLK_DIVI(v)	((v) << 12)
+#define BCM2708_CLK_DIVF(v)	(v)
+
+enum {
+	BCM2708_CLK_MASH_0 = 0,
+	BCM2708_CLK_MASH_1,
+	BCM2708_CLK_MASH_2,
+	BCM2708_CLK_MASH_3,
+};
+
+enum {
+	BCM2708_CLK_SRC_GND = 0,
+	BCM2708_CLK_SRC_OSC,
+	BCM2708_CLK_SRC_DBG0,
+	BCM2708_CLK_SRC_DBG1,
+	BCM2708_CLK_SRC_PLLA,
+	BCM2708_CLK_SRC_PLLC,
+	BCM2708_CLK_SRC_PLLD,
+	BCM2708_CLK_SRC_HDMI,
+};
+
+/* Most clocks are not useable (freq = 0) */
+static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
+	[BCM2708_CLK_SRC_GND]		= 0,
+	[BCM2708_CLK_SRC_OSC]		= 19200000,
+	[BCM2708_CLK_SRC_DBG0]		= 0,
+	[BCM2708_CLK_SRC_DBG1]		= 0,
+	[BCM2708_CLK_SRC_PLLA]		= 0,
+	[BCM2708_CLK_SRC_PLLC]		= 0,
+	[BCM2708_CLK_SRC_PLLD]		= 500000000,
+	[BCM2708_CLK_SRC_HDMI]		= 0,
+};
+
+
+/* I2S registers */
+#define BCM2708_I2S_CS_A_REG		0x00
+#define BCM2708_I2S_FIFO_A_REG		0x04
+#define BCM2708_I2S_MODE_A_REG		0x08
+#define BCM2708_I2S_RXC_A_REG		0x0c
+#define BCM2708_I2S_TXC_A_REG		0x10
+#define BCM2708_I2S_DREQ_A_REG		0x14
+#define BCM2708_I2S_INTEN_A_REG		0x18
+#define BCM2708_I2S_INTSTC_A_REG	0x1c
+#define BCM2708_I2S_GRAY_REG		0x20
+
+/* I2S register settings */
+#define BCM2708_I2S_STBY		(1 << 25)
+#define BCM2708_I2S_SYNC		(1 << 24)
+#define BCM2708_I2S_RXSEX		(1 << 23)
+#define BCM2708_I2S_RXF			(1 << 22)
+#define BCM2708_I2S_TXE			(1 << 21)
+#define BCM2708_I2S_RXD			(1 << 20)
+#define BCM2708_I2S_TXD			(1 << 19)
+#define BCM2708_I2S_RXR			(1 << 18)
+#define BCM2708_I2S_TXW			(1 << 17)
+#define BCM2708_I2S_CS_RXERR		(1 << 16)
+#define BCM2708_I2S_CS_TXERR		(1 << 15)
+#define BCM2708_I2S_RXSYNC		(1 << 14)
+#define BCM2708_I2S_TXSYNC		(1 << 13)
+#define BCM2708_I2S_DMAEN		(1 << 9)
+#define BCM2708_I2S_RXTHR(v)		((v) << 7)
+#define BCM2708_I2S_TXTHR(v)		((v) << 5)
+#define BCM2708_I2S_RXCLR		(1 << 4)
+#define BCM2708_I2S_TXCLR		(1 << 3)
+#define BCM2708_I2S_TXON		(1 << 2)
+#define BCM2708_I2S_RXON		(1 << 1)
+#define BCM2708_I2S_EN			(1)
+
+#define BCM2708_I2S_CLKDIS		(1 << 28)
+#define BCM2708_I2S_PDMN		(1 << 27)
+#define BCM2708_I2S_PDME		(1 << 26)
+#define BCM2708_I2S_FRXP		(1 << 25)
+#define BCM2708_I2S_FTXP		(1 << 24)
+#define BCM2708_I2S_CLKM		(1 << 23)
+#define BCM2708_I2S_CLKI		(1 << 22)
+#define BCM2708_I2S_FSM			(1 << 21)
+#define BCM2708_I2S_FSI			(1 << 20)
+#define BCM2708_I2S_FLEN(v)		((v) << 10)
+#define BCM2708_I2S_FSLEN(v)		(v)
+
+#define BCM2708_I2S_CHWEX		(1 << 15)
+#define BCM2708_I2S_CHEN		(1 << 14)
+#define BCM2708_I2S_CHPOS(v)		((v) << 4)
+#define BCM2708_I2S_CHWID(v)		(v)
+#define BCM2708_I2S_CH1(v)		((v) << 16)
+#define BCM2708_I2S_CH2(v)		(v)
+
+#define BCM2708_I2S_TX_PANIC(v)		((v) << 24)
+#define BCM2708_I2S_RX_PANIC(v)		((v) << 16)
+#define BCM2708_I2S_TX(v)		((v) << 8)
+#define BCM2708_I2S_RX(v)		(v)
+
+#define BCM2708_I2S_INT_RXERR		(1 << 3)
+#define BCM2708_I2S_INT_TXERR		(1 << 2)
+#define BCM2708_I2S_INT_RXR		(1 << 1)
+#define BCM2708_I2S_INT_TXW		(1 << 0)
+
+/* I2S DMA interface */
+#define BCM2708_I2S_FIFO_PHYSICAL_ADDR	0x7E203004
+#define BCM2708_DMA_DREQ_PCM_TX		2
+#define BCM2708_DMA_DREQ_PCM_RX		3
+
+/* General device struct */
+struct bcm2708_i2s_dev {
+	struct device				*dev;
+	struct bcm2708_pcm_dma_data		dma_params[2];
+	void __iomem				*i2s_base;
+	void __iomem				*clk_base;
+	unsigned int				fmt;
+	struct snd_pcm_substream		*first_stream;
+	struct snd_pcm_substream		*second_stream;
+};
+
+static inline void bcm2708_i2s_write_reg(struct bcm2708_i2s_dev *dev,
+					   int reg, u32 val)
+{
+	dev_dbg(dev->dev, "I2S write to register %p = %x\n",
+			dev->clk_base + reg, val);
+	__raw_writel(val, dev->i2s_base + reg);
+}
+
+static inline u32 bcm2708_i2s_read_reg(struct bcm2708_i2s_dev *dev, int reg)
+{
+	return __raw_readl(dev->i2s_base + reg);
+}
+
+static inline void bcm2708_i2s_set_bits(struct bcm2708_i2s_dev *dev,
+					   int reg, u32 val)
+{
+	u32 oldval = __raw_readl(dev->i2s_base + reg);
+	bcm2708_i2s_write_reg(dev, reg, oldval | val);
+}
+
+static inline void bcm2708_i2s_clear_bits(struct bcm2708_i2s_dev *dev,
+					   int reg, u32 val)
+{
+	u32 oldval = __raw_readl(dev->i2s_base + reg);
+	bcm2708_i2s_write_reg(dev, reg, oldval & ~val);
+}
+
+static inline void bcm2708_clk_write_reg(struct bcm2708_i2s_dev *dev,
+					   int reg, u32 val)
+{
+	dev_dbg(dev->dev, "PCM clk write to register %p = %x\n",
+			dev->clk_base + reg, val);
+	__raw_writel(val, dev->clk_base + reg);
+}
+
+static inline u32 bcm2708_clk_read_reg(struct bcm2708_i2s_dev *dev, int reg)
+{
+	return __raw_readl(dev->clk_base + reg);
+}
+
+static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
+{
+	/*
+	 * Start the clock if in master mode.
+	 */
+	unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
+	if (master == SND_SOC_DAIFMT_CBS_CFS
+			|| master == SND_SOC_DAIFMT_CBS_CFM) {
+		unsigned int clkreg = bcm2708_clk_read_reg(dev,
+				BCM2708_CLK_PCMCTL_REG);
+		bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMCTL_REG,
+				BCM2708_CLK_PASSWD | clkreg | BCM2708_CLK_ENAB);
+	}
+}
+
+static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
+{
+	int timeout = 1000;
+
+	/* stop clock */
+	unsigned int clkreg = bcm2708_clk_read_reg(dev, BCM2708_CLK_PCMCTL_REG);
+	bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMCTL_REG, ~(BCM2708_CLK_ENAB)
+		& (BCM2708_CLK_PASSWD | clkreg));
+
+	/* wait for the BUSY flag going down */
+	while ((bcm2708_clk_read_reg(dev, BCM2708_CLK_PCMCTL_REG)
+				& BCM2708_CLK_BUSY)
+			&& timeout > 0) {
+		timeout--;
+	}
+
+	if (timeout <= 0) {
+		/* KILL the clock */
+		dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
+		bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMCTL_REG,
+				BCM2708_CLK_KILL | BCM2708_CLK_PASSWD
+				| clkreg);
+	}
+}
+
+static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev)
+{
+	int timeout = 1000;
+	unsigned int syncval;
+
+	/* Backup the current state */
+	unsigned int i2s_active_state = bcm2708_i2s_read_reg(dev,
+			BCM2708_I2S_CS_A_REG)
+			& (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
+
+	unsigned int clk_active_state = bcm2708_clk_read_reg(dev,
+			BCM2708_CLK_PCMCTL_REG) & BCM2708_CLK_ENAB;
+
+	/* Start clock if not running */
+	if (!clk_active_state) {
+		unsigned int clkreg = bcm2708_clk_read_reg(dev,
+				BCM2708_CLK_PCMCTL_REG);
+		bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMCTL_REG,
+				BCM2708_CLK_PASSWD | clkreg | BCM2708_CLK_ENAB);
+	}
+
+	/* Stop I2S module */
+	bcm2708_i2s_clear_bits(dev, BCM2708_I2S_CS_A_REG, BCM2708_I2S_RXON
+							| BCM2708_I2S_TXON);
+
+	/*
+	 * Clear the FIFOs
+	 * Requires at least 2 PCM clock cycles to take effect
+	 */
+	bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG, BCM2708_I2S_RXCLR
+							| BCM2708_I2S_TXCLR);
+
+	/* Wait for 2 PCM clock cycles */
+
+	/*
+	 * Toggle the SYNC flag - after 2 PCM clock cycles it can be read back
+	 * FIXME: This does not seem to work for slave mode!
+	 */
+	syncval = bcm2708_i2s_read_reg(dev, BCM2708_I2S_CS_A_REG)
+					& BCM2708_I2S_SYNC;
+	if (syncval)
+		bcm2708_i2s_clear_bits(dev, BCM2708_I2S_CS_A_REG,
+					BCM2708_I2S_SYNC);
+	else
+		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG,
+					BCM2708_I2S_SYNC);
+
+	/* Wait for the SYNC flag changing it's state */
+	while (((bcm2708_i2s_read_reg(dev, BCM2708_I2S_CS_A_REG)
+					& BCM2708_I2S_SYNC) == syncval)
+			&& timeout > 0) {
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		dev_err(dev->dev, "I2S SYNC error!\n");
+
+	/* Stop clock if it was not running before */
+	if (!clk_active_state)
+		bcm2708_i2s_stop_clock(dev);
+
+	/* Restore I2S state */
+	bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG, i2s_active_state);
+}
+
+static void bcm2708_i2s_start(struct bcm2708_i2s_dev *dev,
+		struct snd_pcm_substream *substream)
+{
+	bcm2708_i2s_start_clock(dev);
+
+	/*
+	 * Enable the stream.
+	 */
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG,
+				BCM2708_I2S_RXON);
+	} else {
+		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG,
+				BCM2708_I2S_TXON);
+	}
+}
+
+static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
+		struct snd_pcm_substream *substream)
+{
+	unsigned int still_running;
+
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+		bcm2708_i2s_clear_bits(dev, BCM2708_I2S_CS_A_REG,
+				BCM2708_I2S_RXON);
+	} else {
+		bcm2708_i2s_clear_bits(dev, BCM2708_I2S_CS_A_REG,
+				BCM2708_I2S_TXON);
+	}
+
+	still_running = bcm2708_i2s_read_reg(dev, BCM2708_I2S_CS_A_REG)
+				& (BCM2708_I2S_TXON | BCM2708_I2S_RXON);
+
+	/* Stop also the clock when not SND_SOC_DAIFMT_CONT */
+	if (!still_running && !(dev->fmt & SND_SOC_DAIFMT_CONT))
+		bcm2708_i2s_stop_clock(dev);
+
+}
+
+static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
+				      unsigned int fmt)
+{
+	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+	dev->fmt = fmt;
+	return 0;
+}
+
+static bool bcm2708_i2s_check_other_stream(struct bcm2708_i2s_dev *dev,
+					struct snd_pcm_substream *substream,
+					struct snd_pcm_substream *other_stream,
+					struct snd_pcm_hw_params *params)
+{
+	if (other_stream->runtime->format &&
+		(other_stream->runtime->format != params_format(params))) {
+		dev_err(dev->dev,
+			"Sample formats of streams are different. %i (%s) != %i (%s) Initialization failed!\n",
+			other_stream->runtime->format,
+			(other_stream->stream ==
+			 SNDRV_PCM_STREAM_PLAYBACK ?
+			 "playback" : "capture"),
+			params_format(params),
+			(substream->stream ==
+			 SNDRV_PCM_STREAM_PLAYBACK ?
+			 "playback" : "capture"));
+		return false;
+	}
+
+	if (other_stream->runtime->rate &&
+			(other_stream->runtime->rate != params_rate(params))) {
+		dev_err(dev->dev,
+			"Sampling rates of streams are different. %i (%s) != %i (%s) Initialization failed!\n",
+			other_stream->runtime->rate,
+			(other_stream->stream ==
+			 SNDRV_PCM_STREAM_PLAYBACK ?
+			 "playback" : "capture"),
+			params_rate(params),
+			(substream->stream ==
+			 SNDRV_PCM_STREAM_PLAYBACK ?
+			 "playback" : "capture"));
+		return false;
+	}
+
+	return true;
+}
+
+static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
+				 struct snd_pcm_hw_params *params,
+				 struct snd_soc_dai *dai)
+{
+	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+
+	unsigned int sampling_rate = params_rate(params);
+	unsigned int data_length, data_delay, half_frame;
+	unsigned int ch1pos, ch2pos, mode, format;
+	unsigned int mash = BCM2708_CLK_MASH_1;
+	unsigned int divi, divf, target_frequency;
+	int clk_src = -1;
+	unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
+	unsigned int bit_master =	(master == SND_SOC_DAIFMT_CBS_CFS
+					|| master == SND_SOC_DAIFMT_CBS_CFM);
+
+	unsigned int frame_master =	(master == SND_SOC_DAIFMT_CBS_CFS
+					|| master == SND_SOC_DAIFMT_CBM_CFS);
+
+	/* Ensure, that both streams have the same settings */
+	struct snd_pcm_substream *other_stream = dev->first_stream;
+	if (other_stream == substream)
+		other_stream = dev->second_stream;
+
+	if (other_stream != NULL
+		&& !bcm2708_i2s_check_other_stream(dev,
+			substream, other_stream, params))
+		return -EINVAL;
+
+	/*
+	 * If a stream is already enabled,
+	 * the registers are already set properly.
+	 */
+	if (bcm2708_i2s_read_reg(dev, BCM2708_I2S_CS_A_REG)
+			& (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
+		return 0;
+
+	/*
+	 * Adjust the data length according to the format.
+	 * We prefill the half frame length with an integer
+	 * divider of 2400 as explained at the clock settings.
+	 * Maybe it is overwritten there, if the Integer mode
+	 * does not apply.
+	 */
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		data_length = 16;
+		half_frame = 20;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		data_length = 32;
+		half_frame = 40;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*
+	 * Clock Settings
+	 *
+	 * The target frequency of the bit clock is
+	 *	sampling rate * frame length
+	 *
+	 * Integer mode:
+	 * Sampling rates that are multiples of 8000 kHz
+	 * can be driven by the oscillator of 19.2 MHz
+	 * with an integer divider as long as the frame length
+	 * is an integer divider of 19200000/8000=2400 as set up above.
+	 * This is no longer possible if the sampling rate
+	 * is too high (e.g. 192 kHz), because the oscillator is too slow.
+	 *
+	 * MASH mode:
+	 * For all other sampling rates, it is not possible to
+	 * have an integer divider. Approximate the clock
+	 * with the MASH module that induces a slight frequency
+	 * variance. To minimize that it is best to have the fastest
+	 * clock here. That is PLLD with 500 MHz.
+	 */
+	target_frequency = sampling_rate*half_frame*2;
+	clk_src = BCM2708_CLK_SRC_OSC;
+	mash = BCM2708_CLK_MASH_0;
+
+	if (bcm2708_clk_freq[clk_src] % target_frequency == 0
+			&& bit_master && frame_master) {
+		divi = bcm2708_clk_freq[clk_src]/target_frequency;
+		divf = 0;
+	} else {
+		uint64_t dividend;
+
+		/*
+		 * Overwrite half frame length, because the
+		 * above trick is not needed.
+		 * This is fixed, because a bit clock of 64*fs
+		 * seems to be what most codecs want.
+		 * Is it necessary to have this dynamic?
+		 */
+		half_frame = 32;
+		target_frequency = sampling_rate*half_frame*2;
+
+		clk_src = BCM2708_CLK_SRC_PLLD;
+		mash = BCM2708_CLK_MASH_1;
+
+		dividend = bcm2708_clk_freq[clk_src];
+		dividend *= 1024;
+		do_div(dividend, target_frequency);
+		divi = dividend / 1024;
+		divf = dividend % 1024;
+	}
+
+	/* Set clock divider */
+	bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
+			| BCM2708_CLK_DIVI(divi)
+			| BCM2708_CLK_DIVF(divf));
+
+	/* Setup clock, but don't start it yet */
+	bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
+			| BCM2708_CLK_MASH(mash)
+			| BCM2708_CLK_SRC(clk_src));
+
+
+	/* Setup the frame format */
+	format = BCM2708_I2S_CHEN;
+
+	if (data_length > 24)
+		format |= BCM2708_I2S_CHWEX;
+
+	format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
+
+	switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		data_delay = 1;
+		break;
+	default:
+		/* TODO
+		 * Others are possible but are not implemented at the moment.
+		 */
+		dev_err(dev->dev, "%s:bad format\n", __func__);
+		return -EINVAL;
+	}
+
+	ch1pos = data_delay;
+	ch2pos = half_frame+data_delay;
+
+	switch (params_channels(params)) {
+	case 2:
+		format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
+		format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
+		format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*
+	 * Set format for both streams.
+	 * We cannot set another frame length
+	 * (and therefore word length) anyway,
+	 * so the format will be the same.
+	 */
+	bcm2708_i2s_write_reg(dev, BCM2708_I2S_RXC_A_REG, format);
+	bcm2708_i2s_write_reg(dev, BCM2708_I2S_TXC_A_REG, format);
+
+
+	/* Setup the I2S mode */
+	mode = 0;
+
+	if (data_length <= 16) {
+		/*
+		 * Use frame packed mode (2 channels per 32 bit word)
+		 * We cannot set another frame length in the second stream
+		 * (and therefore word length) anyway,
+		 * so the format will be the same.
+		 */
+		mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
+	}
+
+	mode |= BCM2708_I2S_FLEN(half_frame*2-1);
+	mode |= BCM2708_I2S_FSLEN(half_frame);
+
+	/* master or slave? */
+	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		/* cpu is master */
+		break;
+	case SND_SOC_DAIFMT_CBM_CFS:
+		/*
+		 * codec is bit clock master
+		 * cpu is frame master
+		 */
+		mode |= BCM2708_I2S_CLKM;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFM:
+		/*
+		 * codec is frame master
+		 * cpu is bit clock master
+		 */
+		mode |= BCM2708_I2S_FSM;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFM:
+		/* codec is master */
+		mode |= BCM2708_I2S_CLKM;
+		mode |= BCM2708_I2S_FSM;
+		break;
+	default:
+		dev_err(dev->dev, "%s:bad master\n", __func__);
+		return -EINVAL;
+	}
+
+	/*
+	 * Invert clocks?
+	 *
+	 * The BCM approach seems to be inverted to the classical I2S approach.
+	 */
+	switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		/* none - therefore, both for BCM */
+		mode |= BCM2708_I2S_CLKI;
+		mode |= BCM2708_I2S_FSI;
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		/* both - therefore, none for BCM*/
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		/*
+		 * invert only frame sync - therefore,
+		 * invert only bit clock for BCM
+		 */
+		mode |= BCM2708_I2S_CLKI;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		/*
+		 * invert only bit clock - therefore,
+		 * invert only frame sync for BCM
+		 */
+		mode |= BCM2708_I2S_FSI;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	bcm2708_i2s_write_reg(dev, BCM2708_I2S_MODE_A_REG, mode);
+
+
+	/* Setup the DMA parameters */
+	bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG, BCM2708_I2S_RXTHR(1)
+			| BCM2708_I2S_TXTHR(1)
+			| BCM2708_I2S_DMAEN);
+
+	bcm2708_i2s_write_reg(dev, BCM2708_I2S_DREQ_A_REG,
+			  BCM2708_I2S_TX_PANIC(0x10)
+			| BCM2708_I2S_RX_PANIC(0x30)
+			| BCM2708_I2S_TX(0x30)
+			| BCM2708_I2S_RX(0x20));
+
+	/* Clear FIFOs */
+	bcm2708_i2s_clear_fifos(dev);
+
+	return 0;
+}
+
+
+static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+	unsigned int cs_reg;
+
+	bcm2708_i2s_start_clock(dev);
+
+	/*
+	 * Clear both FIFOs if the one that should be started
+	 * is not empty at the moment. This should only happen
+	 * after overrun. Otherwise, hw_params would have cleared
+	 * the FIFO.
+	 */
+	cs_reg = bcm2708_i2s_read_reg(dev, BCM2708_I2S_CS_A_REG);
+
+	switch (substream->stream) {
+	case SNDRV_PCM_STREAM_PLAYBACK:
+		if (cs_reg & BCM2708_I2S_TXE)
+			break;
+	case SNDRV_PCM_STREAM_CAPTURE:
+		if (!(cs_reg & BCM2708_I2S_RXD))
+			break;
+
+		bcm2708_i2s_clear_fifos(dev);
+	}
+
+	return 0;
+}
+
+static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
+			       struct snd_soc_dai *dai)
+{
+	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		bcm2708_i2s_start(dev, substream);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		bcm2708_i2s_stop(dev, substream);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
+			       struct snd_soc_dai *dai)
+{
+	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+
+	if (!dev->first_stream) {
+		dev->first_stream = substream;
+
+		/* should this still be running stop it */
+		bcm2708_i2s_stop_clock(dev);
+
+		/* enable PCM block */
+		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG, BCM2708_I2S_EN);
+
+		/*
+		 * Disable STBY
+		 * Requires at least 4 PCM clock cycles to take effect
+		 */
+		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG,
+				BCM2708_I2S_STBY);
+	} else {
+		struct snd_pcm_runtime *first_runtime =
+			dev->first_stream->runtime;
+
+		/*
+		 * This is the second stream open, so we need to impose
+		 * sample size and sampling rate constraints.
+		 * This is because frame length and clock cannot be specified
+		 * seperately.
+		 *
+		 * Note that this can cause a race condition if the
+		 * second stream is opened before the first stream is
+		 * fully initialized.  We provide some protection by
+		 * checking to make sure the first stream is
+		 * initialized, but it's not perfect.  ALSA sometimes
+		 * re-initializes the driver with a different sample
+		 * rate or size.  If the second stream is opened
+		 * before the first stream has received its final
+		 * parameters, then the second stream may be
+		 * constrained to the wrong sample rate or size.
+		 *
+		 * We will continue in case of failure and recheck the
+		 * constraint in hw_params.
+		 */
+		if (!first_runtime->format) {
+			dev_err(substream->pcm->card->dev,
+					"Set format in %s stream first! "
+					"Initialization may fail.\n",
+					substream->stream ==
+					SNDRV_PCM_STREAM_PLAYBACK
+					? "capture" : "playback");
+		} else {
+			snd_pcm_hw_constraint_minmax(substream->runtime,
+					SNDRV_PCM_HW_PARAM_FORMAT,
+					first_runtime->format,
+					first_runtime->format);
+		}
+
+		if (!first_runtime->rate) {
+			dev_err(substream->pcm->card->dev,
+					"Set sampling rate in %s stream first! "
+					"Initialization may fail!\n",
+					substream->stream ==
+					SNDRV_PCM_STREAM_PLAYBACK
+					? "capture" : "playback");
+		} else {
+			snd_pcm_hw_constraint_minmax(substream->runtime,
+					SNDRV_PCM_HW_PARAM_RATE,
+					first_runtime->rate,
+					first_runtime->rate);
+		}
+
+		dev->second_stream = substream;
+	}
+
+	snd_soc_dai_set_dma_data(dai, substream,
+			&dev->dma_params[substream->stream]);
+
+	return 0;
+}
+
+static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+
+	bcm2708_i2s_stop(dev, substream);
+
+	if (dev->first_stream == substream)
+		dev->first_stream = dev->second_stream;
+
+	dev->second_stream = NULL;
+
+	/* If both streams are stopped, disable module and clock */
+	if (!dev->first_stream) {
+		/* Disable the module */
+		bcm2708_i2s_clear_bits(dev, BCM2708_I2S_CS_A_REG,
+				BCM2708_I2S_EN);
+
+		/*
+		 * Stopping clock is necessary, because stop does
+		 * not stop the clock when SND_SOC_DAIFMT_CONT
+		 */
+		bcm2708_i2s_stop_clock(dev);
+	}
+}
+
+static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
+	.startup	= bcm2708_i2s_startup,
+	.shutdown	= bcm2708_i2s_shutdown,
+	.prepare	= bcm2708_i2s_prepare,
+	.trigger	= bcm2708_i2s_trigger,
+	.hw_params	= bcm2708_i2s_hw_params,
+	.set_fmt	= bcm2708_i2s_set_dai_fmt,
+};
+
+static struct snd_soc_dai_driver bcm2708_i2s_dai = {
+	.playback = {
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates =	SNDRV_PCM_RATE_8000_192000,
+		.formats =	SNDRV_PCM_FMTBIT_S16_LE
+				| SNDRV_PCM_FMTBIT_S32_LE
+		},
+	.capture = {
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates =	SNDRV_PCM_RATE_8000_192000,
+		.formats =	SNDRV_PCM_FMTBIT_S16_LE
+				| SNDRV_PCM_FMTBIT_S32_LE
+		},
+	.ops = &bcm2708_i2s_dai_ops,
+	.symmetric_rates = 1
+};
+
+static void bcm2708_i2s_setup_gpio(void)
+{
+	/*
+	 * This is the common way to handle the GPIO pins for
+	 * the Raspberry Pi.
+	 * TODO Better way would be to handle
+	 * this in the device tree!
+	 */
+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
+
+	unsigned int *gpio;
+	int pin;
+	gpio = ioremap(GPIO_BASE, SZ_16K);
+
+	/* SPI is on GPIO 7..11 */
+	for (pin = 28; pin <= 31; pin++) {
+		INP_GPIO(pin);		/* set mode to GPIO input first */
+		SET_GPIO_ALT(pin, 2);	/* set mode to ALT 0 */
+	}
+#undef INP_GPIO
+#undef SET_GPIO_ALT
+}
+
+static int bcm2708_i2s_probe(struct platform_device *pdev)
+{
+	struct bcm2708_i2s_dev *dev;
+	int i;
+	void __iomem *base[2];
+
+	/* request both ioareas */
+	for (i = 0; i <= 1; i++) {
+		struct resource *mem, *ioarea;
+		mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
+		if (!mem) {
+			dev_err(&pdev->dev, "I2S probe: Memory resource could not be found.\n");
+			return -ENODEV;
+		}
+
+		ioarea = devm_request_mem_region(&pdev->dev, mem->start,
+					   resource_size(mem),
+					   pdev->name);
+		if (!ioarea) {
+			dev_err(&pdev->dev, "I2S probe: Memory region already claimed.\n");
+			return -EBUSY;
+		}
+
+		base[i] = devm_ioremap(&pdev->dev, mem->start,
+				resource_size(mem));
+		if (!base[i]) {
+			dev_err(&pdev->dev, "I2S probe: ioremap failed.\n");
+			return -ENOMEM;
+		}
+	}
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(struct bcm2708_i2s_dev),
+			   GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "I2S probe: kzalloc failed.\n");
+		return -ENOMEM;
+	}
+
+	dev->i2s_base = base[0];
+	dev->clk_base = base[1];
+
+	bcm2708_i2s_setup_gpio();
+
+	/* Set the appropriate DMA parameters */
+	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].port_addr =
+		(dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
+	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].port_addr =
+		(dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
+
+	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_req =
+		BCM2708_DMA_DREQ_PCM_TX;
+	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_req =
+		BCM2708_DMA_DREQ_PCM_RX;
+
+	/* Store the pdev */
+	dev->dev = &pdev->dev;
+	dev_set_drvdata(&pdev->dev, dev);
+
+	return snd_soc_register_dai(&pdev->dev, &bcm2708_i2s_dai);
+}
+
+static int bcm2708_i2s_remove(struct platform_device *pdev)
+{
+	snd_soc_unregister_dai(&pdev->dev);
+	return 0;
+}
+
+static struct platform_driver bcm2708_i2s_driver = {
+	.probe		= bcm2708_i2s_probe,
+	.remove		= bcm2708_i2s_remove,
+	.driver		= {
+		.name	= "bcm2708-i2s",
+		.owner	= THIS_MODULE,
+	},
+};
+
+module_platform_driver(bcm2708_i2s_driver);
+
+MODULE_AUTHOR("Florian Meier");
+MODULE_DESCRIPTION("BCM2708 I2S Interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/bcm2708/bcm2708-pcm.c b/sound/soc/bcm2708/bcm2708-pcm.c
new file mode 100644
index 0000000..4b3e688
--- /dev/null
+++ b/sound/soc/bcm2708/bcm2708-pcm.c
@@ -0,0 +1,303 @@
+/*
+ * ALSA PCM interface for Broadcom BCM2708 SoC
+ *
+ * Author:	Florian Meier, <florian.meier at koalo.de>
+ *		Copyright 2013
+ *
+ * based on
+ *	ALSA PCM interface for the OMAP SoC
+ *	Copyright (C) 2008 Nokia Corporation
+ *	Contact: Jarkko Nikula <jarkko.nikula at bitmer.com>
+ *	Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * TODO This should be transferred to the generic DMA engine driver
+ *	as soon as the official BCM2708 kernel migrates to 3.10.
+ *	Otherwise, it would be difficult to test.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/bcm2708-dmaengine.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/soc.h>
+
+#include "bcm2708-pcm.h"
+
+static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
+	.info			= SNDRV_PCM_INFO_MMAP |
+				  SNDRV_PCM_INFO_MMAP_VALID |
+				  SNDRV_PCM_INFO_INTERLEAVED |
+				  SNDRV_PCM_INFO_PAUSE |
+				  SNDRV_PCM_INFO_RESUME |
+				  SNDRV_PCM_INFO_JOINT_DUPLEX |
+				  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
+	.formats		= SNDRV_PCM_FMTBIT_S16_LE |
+				  SNDRV_PCM_FMTBIT_S32_LE,
+	.period_bytes_min	= 32,
+	.period_bytes_max	= 64 * 1024,
+	.periods_min		= 2,
+	.periods_max		= 255,
+	.buffer_bytes_max	= 128 * 1024,
+};
+
+static int bcm2708_pcm_hw_params(struct snd_pcm_substream *substream,
+			      struct snd_pcm_hw_params *params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct bcm2708_pcm_dma_data *dma_data;
+	struct bcm2708_dma_slave_config config;
+	struct dma_chan *chan;
+	int err = 0;
+
+	/* get DMA data (e.g. FIFO address and DREQ) */
+	dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+
+	/*
+	 * There seems to be no use for bufferless
+	 * transfer with this SoC.
+	 */
+	if (!dma_data)
+		return 0;
+
+	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+	runtime->dma_bytes = params_buffer_bytes(params);
+
+	chan = snd_dmaengine_pcm_get_chan(substream);
+	if (!chan)
+		return -EINVAL;
+
+	/* fills in addr_width and direction */
+	err = snd_hwparams_to_dma_slave_config(substream, params, &config.cfg);
+	if (err)
+		return err;
+
+	/* Override the *_dma addr_width if requested by the DAI driver */
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		config.cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	else
+		config.cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+	config.cfg.src_addr = dma_data->port_addr;
+	config.cfg.dst_addr = dma_data->port_addr;
+	config.cfg.src_maxburst = dma_data->packet_size;
+	config.cfg.dst_maxburst = dma_data->packet_size;
+	config.sync_dreq = dma_data->dma_req;
+
+	return dmaengine_slave_config(chan, &config.cfg);
+}
+
+static int bcm2708_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+	snd_pcm_set_runtime_buffer(substream, NULL);
+	return 0;
+}
+
+static int bcm2708_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct bcm2708_pcm_dma_data *dma_data;
+	int ret = 0;
+
+	dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	if (ret == 0)
+		ret = snd_dmaengine_pcm_trigger(substream, cmd);
+
+	return ret;
+}
+
+static snd_pcm_uframes_t bcm2708_pcm_pointer(
+		struct snd_pcm_substream *substream)
+{
+	return snd_dmaengine_pcm_pointer(substream);
+}
+
+static int bcm2708_pcm_open(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct bcm2708_pcm_dma_data *dma_data;
+	int ret;
+
+	snd_soc_set_runtime_hwparams(substream, &bcm2708_pcm_hardware);
+
+	/* Ensure that buffer size is a multiple of period size */
+	ret = snd_pcm_hw_constraint_integer(runtime,
+					    SNDRV_PCM_HW_PARAM_PERIODS);
+	if (ret < 0)
+		return ret;
+
+	dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+	return snd_dmaengine_pcm_open(substream, NULL, NULL);
+}
+
+static int bcm2708_pcm_close(struct snd_pcm_substream *substream)
+{
+	snd_dmaengine_pcm_close(substream);
+	return 0;
+}
+
+static int bcm2708_pcm_mmap(struct snd_pcm_substream *substream,
+	struct vm_area_struct *vma)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+				     runtime->dma_area,
+				     runtime->dma_addr,
+				     runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops bcm2708_pcm_ops = {
+	.open		= bcm2708_pcm_open,
+	.close		= bcm2708_pcm_close,
+	.ioctl		= snd_pcm_lib_ioctl,
+	.hw_params	= bcm2708_pcm_hw_params,
+	.hw_free	= bcm2708_pcm_hw_free,
+	.trigger	= bcm2708_pcm_trigger,
+	.pointer	= bcm2708_pcm_pointer,
+	.mmap		= bcm2708_pcm_mmap,
+};
+
+static u64 bcm2708_pcm_dmamask = DMA_BIT_MASK(64);
+
+static int bcm2708_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
+	int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = bcm2708_pcm_hardware.buffer_bytes_max;
+
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+					   &buf->addr, GFP_KERNEL);
+	if (!buf->area)
+		return -ENOMEM;
+
+	buf->bytes = size;
+	return 0;
+}
+
+static void bcm2708_pcm_free_dma_buffers(struct snd_pcm *pcm)
+{
+	struct snd_pcm_substream *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+
+		dma_free_writecombine(pcm->card->dev, buf->bytes,
+				      buf->area, buf->addr);
+		buf->area = NULL;
+	}
+}
+
+static int bcm2708_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_card *card = rtd->card->snd_card;
+	struct snd_pcm *pcm = rtd->pcm;
+	int ret = 0;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &bcm2708_pcm_dmamask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = DMA_BIT_MASK(64);
+
+	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+		ret = bcm2708_pcm_preallocate_dma_buffer(pcm,
+			SNDRV_PCM_STREAM_PLAYBACK);
+		if (ret)
+			goto out;
+	}
+
+	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+		ret = bcm2708_pcm_preallocate_dma_buffer(pcm,
+			SNDRV_PCM_STREAM_CAPTURE);
+		if (ret)
+			goto out;
+	}
+
+out:
+	/* free preallocated buffers in case of error */
+	if (ret)
+		bcm2708_pcm_free_dma_buffers(pcm);
+
+	return ret;
+}
+
+static struct snd_soc_platform_driver bcm2708_soc_platform = {
+	.ops		= &bcm2708_pcm_ops,
+	.pcm_new	= bcm2708_pcm_new,
+	.pcm_free	= bcm2708_pcm_free_dma_buffers,
+};
+
+static int bcm2708_pcm_probe(struct platform_device *pdev)
+{
+	return snd_soc_register_platform(&pdev->dev,
+			&bcm2708_soc_platform);
+}
+
+static int bcm2708_pcm_remove(struct platform_device *pdev)
+{
+	snd_soc_unregister_platform(&pdev->dev);
+	return 0;
+}
+
+static struct platform_driver bcm2708_pcm_driver = {
+	.driver = {
+			.name = "bcm2708-pcm-audio",
+			.owner = THIS_MODULE,
+	},
+
+	.probe = bcm2708_pcm_probe,
+	.remove = bcm2708_pcm_remove,
+};
+
+module_platform_driver(bcm2708_pcm_driver);
+
+MODULE_AUTHOR("Florian Meier");
+MODULE_DESCRIPTION("BCM2708 PCM DMA module");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:bcm2708-pcm-audio");
diff --git a/sound/soc/bcm2708/bcm2708-pcm.h b/sound/soc/bcm2708/bcm2708-pcm.h
new file mode 100644
index 0000000..e6a6acb
--- /dev/null
+++ b/sound/soc/bcm2708/bcm2708-pcm.h
@@ -0,0 +1,40 @@
+/*
+ * ALSA PCM interface for Broadcom BCM2708 SoC
+ *
+ * Author:	Florian Meier, <florian.meier at koalo.de>
+ *		Copyright 2013
+ *
+ * based on
+ *	ALSA PCM interface for the OMAP SoC
+ *	Copyright (C) 2008 Nokia Corporation
+ *	Contact: Jarkko Nikula <jarkko.nikula at bitmer.com>
+ *		 Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __BCM2708_PCM_H__
+#define __BCM2708_PCM_H__
+
+struct snd_pcm_substream;
+
+struct bcm2708_pcm_dma_data {
+	char		*name;		/* stream identifier */
+	int		dma_req;	/* DMA request line */
+	unsigned long	port_addr;	/* transmit/receive register */
+	int		packet_size;
+};
+
+#endif
diff --git a/sound/soc/bcm2708/rpi-mbed.c b/sound/soc/bcm2708/rpi-mbed.c
new file mode 100644
index 0000000..cb8d25f
--- /dev/null
+++ b/sound/soc/bcm2708/rpi-mbed.c
@@ -0,0 +1,113 @@
+/*
+ * ASoC driver for mbed AudioCODEC (with a TLV320AIC23B)
+ * connected to a Raspberry Pi
+ *
+ * Author:	Florian Meier, <florian.meier at koalo.de>
+ *		Copyright 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+
+#include "../codecs/tlv320aic23.h"
+
+static int snd_rpi_mbed_init(struct snd_soc_pcm_runtime *rtd)
+{
+	return 0;
+}
+
+static int snd_rpi_mbed_hw_params(struct snd_pcm_substream *substream,
+				       struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	int sysclk;
+
+	sysclk = 12000000; /* this is fixed on this board */
+
+	/* set tlv320aic23 sysclk */
+	snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, 0);
+
+	return 0;
+}
+
+/* machine stream operations */
+static struct snd_soc_ops snd_rpi_mbed_ops = {
+	.hw_params = snd_rpi_mbed_hw_params,
+};
+
+static struct snd_soc_dai_link snd_rpi_mbed_dai[] = {
+{
+	.name		= "TLV320AIC23",
+	.stream_name	= "TLV320AIC23 HiFi",
+	.cpu_dai_name	= "bcm2708-i2s.0",
+	.codec_dai_name	= "tlv320aic23-hifi",
+	.platform_name	= "bcm2708-pcm-audio.0",
+	.codec_name	= "tlv320aic23-codec.1-001b",
+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+				SND_SOC_DAIFMT_CBS_CFS,
+	.ops		= &snd_rpi_mbed_ops,
+	.init		= snd_rpi_mbed_init,
+},
+};
+
+/* audio machine driver */
+static struct snd_soc_card snd_rpi_mbed = {
+	.name	 = "snd_rpi_mbed",
+	.dai_link     = snd_rpi_mbed_dai,
+	.num_links    = ARRAY_SIZE(snd_rpi_mbed_dai),
+};
+
+static int snd_rpi_mbed_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+
+	snd_rpi_mbed.dev = &pdev->dev;
+	ret = snd_soc_register_card(&snd_rpi_mbed);
+	if (ret) {
+		dev_err(&pdev->dev,
+				"snd_soc_register_card() failed: %d\n", ret);
+	}
+
+	return ret;
+}
+
+
+static int snd_rpi_mbed_remove(struct platform_device *pdev)
+{
+	return snd_soc_unregister_card(&snd_rpi_mbed);
+}
+
+static struct platform_driver snd_rpi_mbed_driver = {
+	.driver = {
+		.name   = "snd-rpi-mbed",
+		.owner  = THIS_MODULE,
+	},
+	.probe	  = snd_rpi_mbed_probe,
+	.remove	 = snd_rpi_mbed_remove,
+};
+
+module_platform_driver(snd_rpi_mbed_driver);
+
+MODULE_AUTHOR("Florian Meier");
+MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to mbed AudioCODEC");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/bcm2708/rpi-proto.c b/sound/soc/bcm2708/rpi-proto.c
new file mode 100644
index 0000000..25be85a
--- /dev/null
+++ b/sound/soc/bcm2708/rpi-proto.c
@@ -0,0 +1,131 @@
+/*
+ * ASoC driver for PROTO AudioCODEC (with a WM8731)
+ * connected to a Raspberry Pi
+ *
+ * Author:	Florian Meier, <florian.meier at koalo.de>
+ *		Copyright 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+
+#include "../codecs/wm8731.h"
+
+static const unsigned int wm8731_rates_12288000[] = {
+	8000, 32000, 48000, 96000,
+};
+
+static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {
+	.list = wm8731_rates_12288000,
+	.count = ARRAY_SIZE(wm8731_rates_12288000),
+};
+
+static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)
+{
+	/* Setup constraints, because there is a 12.288 MHz XTAL on the board */
+	snd_pcm_hw_constraint_list(substream->runtime, 0,
+				SNDRV_PCM_HW_PARAM_RATE,
+				&wm8731_constraints_12288000);
+	return 0;
+}
+
+static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,
+				       struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	int sysclk = 12288000; /* This is fixed on this board */
+
+	/* Set proto sysclk */
+	int ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
+		sysclk, SND_SOC_CLOCK_IN);
+	if (ret < 0) {
+		dev_err(substream->pcm->dev,
+				"Failed to set WM8731 SYSCLK: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* machine stream operations */
+static struct snd_soc_ops snd_rpi_proto_ops = {
+	.startup = snd_rpi_proto_startup,
+	.hw_params = snd_rpi_proto_hw_params,
+};
+
+static struct snd_soc_dai_link snd_rpi_proto_dai[] = {
+{
+	.name		= "WM8731",
+	.stream_name	= "WM8731 HiFi",
+	.cpu_dai_name	= "bcm2708-i2s.0",
+	.codec_dai_name	= "wm8731-hifi",
+	.platform_name	= "bcm2708-pcm-audio.0",
+	.codec_name	= "wm8731.1-001a",
+	.dai_fmt	= SND_SOC_DAIFMT_I2S
+				| SND_SOC_DAIFMT_NB_NF
+				| SND_SOC_DAIFMT_CBM_CFM,
+	.ops		= &snd_rpi_proto_ops,
+},
+};
+
+/* audio machine driver */
+static struct snd_soc_card snd_rpi_proto = {
+	.name		= "snd_rpi_proto",
+	.dai_link	= snd_rpi_proto_dai,
+	.num_links	= ARRAY_SIZE(snd_rpi_proto_dai),
+};
+
+static int snd_rpi_proto_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+
+	snd_rpi_proto.dev = &pdev->dev;
+	ret = snd_soc_register_card(&snd_rpi_proto);
+	if (ret) {
+		dev_err(&pdev->dev,
+				"snd_soc_register_card() failed: %d\n", ret);
+	}
+
+	return ret;
+}
+
+
+static int snd_rpi_proto_remove(struct platform_device *pdev)
+{
+	return snd_soc_unregister_card(&snd_rpi_proto);
+}
+
+static struct platform_driver snd_rpi_proto_driver = {
+	.driver = {
+		.name   = "snd-rpi-proto",
+		.owner  = THIS_MODULE,
+	},
+	.probe	  = snd_rpi_proto_probe,
+	.remove	 = snd_rpi_proto_remove,
+};
+
+module_platform_driver(snd_rpi_proto_driver);
+
+MODULE_AUTHOR("Florian Meier");
+MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)");
+MODULE_LICENSE("GPL");
-- 
1.7.9.5



From arnd at arndb.de  Wed May 22 10:11:08 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 16:11:08 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522155218.1c2af492@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522134336.GE18614@n2100.arm.linux.org.uk>
 <20130522155218.1c2af492@skate>
Message-ID: <201305221611.08823.arnd@arndb.de>

On Wednesday 22 May 2013, Thomas Petazzoni wrote:
> Dear Russell King - ARM Linux,
> 
> On Wed, 22 May 2013 14:43:36 +0100, Russell King - ARM Linux wrote:
> > On Wed, May 22, 2013 at 12:01:29PM +0200, Sebastian Hesselbarth wrote:
> > > I tried the above on Dove which is possibly affected by the workaround
> > > as it is also ARMv7. In Dove you can access unmapped addresses without
> > > any problems, but as Thomas already stated Armada 370/XP just hang.
> > > Must be some default AHB slave in Dove, which Armada 370/XP is missing.
> > 
> > It may be some clock setting somewhere on the 370/XP.  The Dove will hang
> > as well if you prod at peripherals which you've turned their clocks off.
> 
> The register in question (offset 0x20080 from the base address of the
> internal register) is part of the "core" registers, so I clearly don't
> see how the system could even be booting if this clock was gated. No?

It would hang if you add that offset to the wrong base address though.

	Arnd


From horms+renesas at verge.net.au  Wed May 22 10:13:40 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 23:13:40 +0900
Subject: [PATCH FOR v3.10 v2] ARM: shmobile: kzm9g-reference: Update CMT
 clocksource rating to 80
Message-ID: <1369232020-22681-1-git-send-email-horms+renesas@verge.net.au>

Update the CMT clocksource rating from 125 to 80.

This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
Avoid dummy clockevent being preferred over real").

The patch noted above reduces the rating of dummy clockevent from 400 to 100.
This patch reduces the rating of CMT so that it is once again less than that
of the dummy clockevent.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

---

I also plan to reduce the rating of the STI clocksource to less than 100.
However, as I am not aware of any problems relating to STI in v3.10-rc
my plan is to update STI in the v3.11 timeframe.
---
 arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..9696f36 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
 	.name = "CMT10",
 	.channel_offset = 0x10,
 	.timer_bit = 0,
-	.clockevent_rating = 125,
+	.clockevent_rating = 80,
 	.clocksource_rating = 125,
 };
 
-- 
1.8.2.1



From thomas.petazzoni at free-electrons.com  Wed May 22 10:16:22 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 16:16:22 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <20130522140444.GK2824@lunn.ch>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522152700.4dab10a1@skate> <20130522140444.GK2824@lunn.ch>
Message-ID: <20130522161622.3a65e45d@skate>

Dear Andrew Lunn,

On Wed, 22 May 2013 16:04:44 +0200, Andrew Lunn wrote:

> You gave a good explanation why the CP15 bit its needed, etc. I liked
> the comment.

Thanks.

> It might be worth cross posting both u-boot and barebox lists, since
> they are somewhat involved as well. Are there any other boot loaders
> used on 370 and XP.

As far as Barebox is concerned, Sebastian Hesselbarth and myself have
recently started the Marvell SoC support, so we kind of know what to do.
The current status is that (thanks to the latest patches from
Sebastian), Barebox remaps registers to 0xf1 very early, on all
platforms (currently, we support Kirkwood, Armada 370/XP and Dove). The
CP15 bit is *not* set yet, simply because we don't have enough drivers
yet in Barebox to even load a kernel to then boot it. But once it
happens, I'll adjust the Armada 370/XP code to set this CP15 bit.

As far as mainline U-Boot is concerned, it has zero support for Armada
370/XP at the moment.

> What happens with future chips. 375 springs to mind. I assume its
> Marvell bootloader will do the mapping before handing over to
> Linux. Is it required to also set the bit in CP15? Are we setting off
> down a road where all future Marvell chips which are compatible with
> 370/XP now need to set this bit?

No, the bootloaders provided by Marvell for the future chips will not
have this CP15 bit set. It will only be set for Armada 370/XP platforms.

> How does this effect dove? It will get compiled into the same multi
> arch kernel as 370/XP. I'm thinking about
> arch/arm/include/debug/mvebu.S which might be shared. Dove is not
> going to have this bit set. Kirkwood could also share this code, now
> that the serial ports are all in the same location.

This code will have to be conditionally compiled. When we'll integrate
Dove support in mach-mvebu, we'll make the code conditional. So you'll
have a choice:

 * Either you want to run a multiplatform capable kernel with support
   for Dove, Armada 370 and Armada XP in the same kernel, and you'll
   have to run a recent enough bootloader.

 * Or you have an old bootloader and you don't want to upgrade it, in
   this case you'll have to build a kernel which will only work on
   Armada 370/XP.

My plan is also to make this code show a warning when it detects that
the user is running an old bootloader, in order to encourage users to
move to newer versions of the bootloader. I don't want to show this
message right now, because such new versions are not yet widely
available, but let's say in 1 or 2 release cycles (3.12 or 3.13), we
can add such a message.

Currently, the only two platforms that are widely available with Armada
370 or Armada XP are the Globalscale Mirabox and the Plathome
Openblocks AX3. Once Globalscale and Plathome have released new
versions of their bootloader, we can document how users can upgrade. So
that hopefully, in the future, we may even decide to get rid of this
'hack' entirely.

> What does the ARM reference documentation say about this bit? Is its
> meaning defined? Is there any danger when this bit is used for its
> intended purpose?

I haven't checked myself the ARM reference documentation for this CP15
bit, but I know it has been chosen with care by Marvell engineers. It
is used when the CPU goes idle with the 'wfi' instruction, so the
entire hack makes the assumption that the CPU doesn't go idle between
the moment the bootloader sets the CP15 bit and the moment the kernel
checks it to understand where the internal registers are. If you want,
I can do some more research to give a (hopefully) more compelling
explanation for the choice of this particular bit.

Thanks again for your review and all your questions!

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sebastian.hesselbarth at gmail.com  Wed May 22 10:17:18 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 16:17:18 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <20130522140444.GK2824@lunn.ch>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522152700.4dab10a1@skate> <20130522140444.GK2824@lunn.ch>
Message-ID: <519CD36E.1090900@gmail.com>

On 05/22/2013 04:04 PM, Andrew Lunn wrote:
> It might be worth cross posting both u-boot and barebox lists, since
> they are somewhat involved as well. Are there any other boot loaders
> used on 370 and XP.

barebox is not neccessary, Thomas and I just merged SoC init to always
map on KW, Dove, and A370/XP. It is in a very early stage (console-only)
and will take some time to actually boot linux. And we have SoC
specific init that can set CP15 there.

> How does this effect dove? It will get compiled into the same multi
> arch kernel as 370/XP. I'm thinking about
> arch/arm/include/debug/mvebu.S which might be shared. Dove is not
> going to have this bit set. Kirkwood could also share this code, now
> that the serial ports are all in the same location.

Dove is difficult because u-boot always remaps and never sets the bit
in CP15 _but_ doesn't hang on writing wrong addresses. So remap by
writing to 0xd0.. will do no harm.

Sebastian


From linux at arm.linux.org.uk  Wed May 22 10:17:51 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 May 2013 15:17:51 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130522155218.1c2af492@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu> <519C9779.1040104@gmail.com>
 <20130522134336.GE18614@n2100.arm.linux.org.uk>
 <20130522155218.1c2af492@skate>
Message-ID: <20130522141751.GF18614@n2100.arm.linux.org.uk>

On Wed, May 22, 2013 at 03:52:18PM +0200, Thomas Petazzoni wrote:
> Dear Russell King - ARM Linux,
> 
> On Wed, 22 May 2013 14:43:36 +0100, Russell King - ARM Linux wrote:
> > On Wed, May 22, 2013 at 12:01:29PM +0200, Sebastian Hesselbarth wrote:
> > > I tried the above on Dove which is possibly affected by the workaround
> > > as it is also ARMv7. In Dove you can access unmapped addresses without
> > > any problems, but as Thomas already stated Armada 370/XP just hang.
> > > Must be some default AHB slave in Dove, which Armada 370/XP is missing.
> > 
> > It may be some clock setting somewhere on the 370/XP.  The Dove will hang
> > as well if you prod at peripherals which you've turned their clocks off.
> 
> The register in question (offset 0x20080 from the base address of the
> internal register) is part of the "core" registers, so I clearly don't
> see how the system could even be booting if this clock was gated. No?

The question which was asked was:

	What happens if you access a register at 0xd0xxxxxx when the
	registers are remapped to 0xf1xxxxxx?

The answer which was given was:

	It hangs on XP / 370, but doesn't on Dove.

If the registers have been remapped, then 0xd0xxxxxx is _not_ going to
hit any of the "core" registers.  We're hitting "something else" and
what I'm saying is that Dove will also hang if you hit a peripheral with
its clocks turned off.  Now, it may not be a peripheral, but a bus
segment which is unclocked on those which hang.

As Dove only has clock gating in a few of its peripherals, it could be
that whatever you hit at 0xd0xxxxxx on Dove is allowed to succeed because
of this.  Is that also true on XP or 370?

What we need to know is: after the boot loader passes control to the
kernel, and before _we_ start fiddling around with any clocks, is the
region at 0xd0xxxxxx accessible without hanging the CPU?

That's the point at which we'd want to probe for the remapped registers,
so that's the point where the test access must be made - and with the
system clocks in whatever state was left by the reset+boot loader.


From sergei.shtylyov at cogentembedded.com  Wed May 22 10:19:28 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 22 May 2013 18:19:28 +0400
Subject: [PATCH FOR v3.10 v2] ARM: shmobile: kzm9g-reference: Update CMT
 clocksource rating to 80
In-Reply-To: <1369232020-22681-1-git-send-email-horms+renesas@verge.net.au>
References: <1369232020-22681-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <519CD3F0.7050002@cogentembedded.com>

On 22-05-2013 18:13, Simon Horman wrote:

> Update the CMT clocksource rating from 125 to 80.

> This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
> introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
> Avoid dummy clockevent being preferred over real").

> The patch noted above reduces the rating of dummy clockevent from 400 to 100.
> This patch reduces the rating of CMT so that it is once again less than that
> of the dummy clockevent.

> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

> ---

> I also plan to reduce the rating of the STI clocksource to less than 100.
> However, as I am not aware of any problems relating to STI in v3.10-rc
> my plan is to update STI in the v3.11 timeframe.
> ---
>   arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

    BTW, shouldn't the subject be "ARM: shmobile: sh73a0: Update CMT 
clocksource rating to 80"?

WBR, Sergei



From sebastian.hesselbarth at gmail.com  Wed May 22 10:23:17 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 16:23:17 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522141751.GF18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130521193803.GA20882@1wt.eu> <519C9779.1040104@gmail.com>
 <20130522134336.GE18614@n2100.arm.linux.org.uk>
 <20130522155218.1c2af492@skate>
 <20130522141751.GF18614@n2100.arm.linux.org.uk>
Message-ID: <519CD4D5.9060401@gmail.com>

On 05/22/2013 04:17 PM, Russell King - ARM Linux wrote:
> The question which was asked was:
>
> 	What happens if you access a register at 0xd0xxxxxx when the
> 	registers are remapped to 0xf1xxxxxx?
>
> The answer which was given was:
>
> 	It hangs on XP / 370, but doesn't on Dove.
>
...
> What we need to know is: after the boot loader passes control to the
> kernel, and before _we_ start fiddling around with any clocks, is the
> region at 0xd0xxxxxx accessible without hanging the CPU?
>
> That's the point at which we'd want to probe for the remapped registers,
> so that's the point where the test access must be made - and with the
> system clocks in whatever state was left by the reset+boot loader.

Russell,

I tried both Armada 370 and Dove on a very minimal console-only barebox.
Poking the wrong addresses always hangs 370 while Dove happily returns
zero.

Sebastian


From florian.vaussard at epfl.ch  Wed May 22 10:27:39 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 16:27:39 +0200
Subject: [PATCH 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
Message-ID: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

Following a similar proposal by Stephen Warren for tegra [1], this series
makes use of the C preprocessor when compiling OMAP DT files, and
accomplishes some improvements to improve overall readability.

Patch 2 creates a header file to define the OMAP_GPIO() macro, used by
patch 3 to make GPIOs more readable.
Likewise patch 5 uses the existing constants to make IRQs more readable.
Patch 4 is a small random fix.

This series was boot-tested on omap3-tobi. For other targets, the
decompiled .dtb were diff'ed before and after applying the series
to guarantee identity.

Best regards,

Florian

[1] https://patchwork.kernel.org/patch/2560091/

Florian Vaussard (5):
  ARM: dts: OMAP2+: use #include for all device trees
  ARM: dts: OMAP2+: create a DT header for GPIO
  ARM: dts: OMAP2+: convert DT files to use the new OMAP_GPIO macro
  ARM: dts: OMAP3: fix incorrect notation for musb-hdrc interrupt
  ARM: dts: OMAP4/5: use existing constants for IRQs

 arch/arm/boot/dts/omap2.dtsi              |    4 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    8 +-
 arch/arm/boot/dts/omap3-beagle.dts        |   10 +-
 arch/arm/boot/dts/omap3-devkit8000.dts    |   10 +-
 arch/arm/boot/dts/omap3-evm.dts           |    4 +-
 arch/arm/boot/dts/omap3-igep.dtsi         |    4 +-
 arch/arm/boot/dts/omap3-igep0020.dts      |    8 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |    4 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 +-
 arch/arm/boot/dts/omap3-tobi.dts          |    4 +-
 arch/arm/boot/dts/omap3.dtsi              |    6 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 +-
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |    4 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   18 +-
 arch/arm/boot/dts/omap4-panda-es.dts      |    4 +-
 arch/arm/boot/dts/omap4-panda.dts         |    4 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    2 +-
 arch/arm/boot/dts/omap4-sdp.dts           |   32 ++--
 arch/arm/boot/dts/omap4-var-som.dts       |    8 +-
 arch/arm/boot/dts/omap4.dtsi              |  117 ++++++------
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    6 +-
 arch/arm/boot/dts/omap5-evm.dts           |    4 +-
 arch/arm/boot/dts/omap5.dtsi              |  125 +++++++------
 include/dt-bindings/gpio/omap-gpio.h      |  289 +++++++++++++++++++++++++++++
 30 files changed, 497 insertions(+), 198 deletions(-)
 create mode 100644 include/dt-bindings/gpio/omap-gpio.h

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Wed May 22 10:27:43 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 16:27:43 +0200
Subject: [PATCH 4/5] ARM: dts: OMAP3: fix incorrect notation for musb-hdrc
 interrupt
In-Reply-To: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369232864-14460-5-git-send-email-florian.vaussard@epfl.ch>

On OMAP3, the INTC interrupt controller has only 1 cell.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap3.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 15049b8..0f3be20 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -518,7 +518,7 @@
 		usb_otg_hs: usb_otg_hs at 480ab000 {
 			compatible = "ti,omap3-musb";
 			reg = <0x480ab000 0x1000>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <92>, <93>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			multipoint = <1>;
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Wed May 22 10:27:42 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 16:27:42 +0200
Subject: [PATCH 3/5] ARM: dts: OMAP2+: convert DT files to use the new
 OMAP_GPIO macro
In-Reply-To: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369232864-14460-4-git-send-email-florian.vaussard@epfl.ch>

Use OMAP_GPIO(), in conjunction with standard GPIO flags, to enhance the
readability of DT GPIOs.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 ++
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    6 +++---
 arch/arm/boot/dts/omap3-devkit8000.dts    |    6 +++---
 arch/arm/boot/dts/omap3-igep0020.dts      |    6 +++---
 arch/arm/boot/dts/omap3-igep0030.dts      |    2 +-
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 ++
 arch/arm/boot/dts/omap4-panda-common.dtsi |    6 +++---
 arch/arm/boot/dts/omap4-sdp.dts           |   20 ++++++++++----------
 arch/arm/boot/dts/omap4.dtsi              |    2 ++
 arch/arm/boot/dts/omap5.dtsi              |    2 ++
 12 files changed, 34 insertions(+), 26 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index e6e4587..7ea5df4 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/omap-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index e0ce823..e773a5e 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -29,13 +29,13 @@
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = OMAP_GPIO(150, GPIO_ACTIVE_HIGH); /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = OMAP_GPIO(149, GPIO_ACTIVE_HIGH); /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index fcac96a..f1fd002 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -33,13 +33,13 @@
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = OMAP_GPIO(150, GPIO_ACTIVE_HIGH); /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = OMAP_GPIO(149, GPIO_ACTIVE_HIGH); /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
@@ -50,7 +50,7 @@
 		regulator-name = "hsusb2_reset";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio5 19 0>;	/* gpio_147 */
+		gpio = OMAP_GPIO(147, GPIO_ACTIVE_HIGH);
 		startup-delay-us = <70000>;
 		enable-active-high;
 	};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8d0f5e4..fecb5ac 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -22,21 +22,21 @@
 
 		heartbeat {
 			label = "devkit8000::led1";
-			gpios = <&gpio6 26 0>;	/* 186 -> LED1 */
+			gpios = OMAP_GPIO(186, GPIO_ACTIVE_HIGH);	/* 186 -> LED1 */
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "devkit8000::led2";
-			gpios = <&gpio6 3 0>;	/* 163 -> LED2 */
+			gpios = OMAP_GPIO(163, GPIO_ACTIVE_HIGH);	/* 163 -> LED2 */
 			default-state = "on";
 			linux,default-trigger = "none";
 		};
 
 		usr {
 			label = "devkit8000::led3";
-			gpios = <&gpio6 4 0>;	/* 164 -> LED3 */
+			gpios = OMAP_GPIO(164, GPIO_ACTIVE_HIGH);	/* 164 -> LED3 */
 			default-state = "on";
 			linux,default-trigger = "usr";
                 };
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 2f96a5c..4be8ba1 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -19,19 +19,19 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&gpio1 26 0>;
+			 gpios = OMAP_GPIO(26, GPIO_ACTIVE_HIGH);
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&gpio1 27 0>;
+			 gpios = OMAP_GPIO(27, GPIO_ACTIVE_HIGH);
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 28 0>;
+			 gpios = OMAP_GPIO(28, GPIO_ACTIVE_HIGH);
 			 default-state = "off";
 		};
 
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index f3a1bf0..5a2c7a6 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -37,7 +37,7 @@
 
 		user2 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 16 1>;
+			 gpios = OMAP_GPIO(16, GPIO_ACTIVE_LOW);
 			 default-state = "off";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 5df894f..8390c8b 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -20,7 +20,7 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "overo:red:gpio21";
-			gpios = <&gpio1 21 0>;
+			gpios = OMAP_GPIO(21, GPIO_ACTIVE_HIGH);
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7c7d494..15049b8 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/omap-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 63148d1..b71f5cd 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -20,13 +20,13 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "pandaboard::status1";
-			gpios = <&gpio1 7 0>;
+			gpios = OMAP_GPIO(7, GPIO_ACTIVE_HIGH);
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "pandaboard::status2";
-			gpios = <&gpio1 8 0>;
+			gpios = OMAP_GPIO(8, GPIO_ACTIVE_HIGH);
 			linux,default-trigger = "mmc0";
 		};
 	};
@@ -156,7 +156,7 @@
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
 		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
-		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+		ti,audpwron-gpio = OMAP_GPIO(127, GPIO_ACTIVE_HIGH);
 
 		vio-supply = <&v1v8>;
 		v2v1-supply = <&v2v1>;
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5edd08e..f55bb68 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -24,7 +24,7 @@
 		regulator-name = "VDD_ETH";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio2 16 0>;  /* gpio line 48 */
+		gpio = OMAP_GPIO(48, GPIO_ACTIVE_HIGH);
 		enable-active-high;
 		regulator-boot-on;
 	};
@@ -41,42 +41,42 @@
 		compatible = "gpio-leds";
 		debug0 {
 			label = "omap4:green:debug0";
-			gpios = <&gpio2 29 0>; /* 61 */
+			gpios = OMAP_GPIO(61, GPIO_ACTIVE_HIGH);
 		};
 
 		debug1 {
 			label = "omap4:green:debug1";
-			gpios = <&gpio1 30 0>; /* 30 */
+			gpios = OMAP_GPIO(30, GPIO_ACTIVE_HIGH);
 		};
 
 		debug2 {
 			label = "omap4:green:debug2";
-			gpios = <&gpio1 7 0>; /* 7 */
+			gpios = OMAP_GPIO(7, GPIO_ACTIVE_HIGH);
 		};
 
 		debug3 {
 			label = "omap4:green:debug3";
-			gpios = <&gpio1 8 0>; /* 8 */
+			gpios = OMAP_GPIO(8, GPIO_ACTIVE_HIGH);
 		};
 
 		debug4 {
 			label = "omap4:green:debug4";
-			gpios = <&gpio2 18 0>; /* 50 */
+			gpios = OMAP_GPIO(50, GPIO_ACTIVE_HIGH);
 		};
 
 		user1 {
 			label = "omap4:blue:user";
-			gpios = <&gpio6 9 0>; /* 169 */
+			gpios = OMAP_GPIO(169, GPIO_ACTIVE_HIGH);
 		};
 
 		user2 {
 			label = "omap4:red:user";
-			gpios = <&gpio6 10 0>; /* 170 */
+			gpios = OMAP_GPIO(170, GPIO_ACTIVE_HIGH);
 		};
 
 		user3 {
 			label = "omap4:green:user";
-			gpios = <&gpio5 11 0>; /* 139 */
+			gpios = OMAP_GPIO(139, GPIO_ACTIVE_HIGH);
 		};
 	};
 
@@ -296,7 +296,7 @@
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
 		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
-		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+		ti,audpwron-gpio = OMAP_GPIO(127, GPIO_ACTIVE_HIGH);
 
 		vio-supply = <&v1v8>;
 		v2v1-supply = <&v2v1>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 53d80aa..3c00b72 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,6 +14,8 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
+#include <dt-bindings/gpio/omap-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e8e6653..af849e6 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -15,6 +15,8 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
+#include <dt-bindings/gpio/omap-gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Wed May 22 10:27:41 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 16:27:41 +0200
Subject: [PATCH 2/5] ARM: dts: OMAP2+: create a DT header for GPIO
In-Reply-To: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369232864-14460-3-git-send-email-florian.vaussard@epfl.ch>

Define the OMAP_GPIO macro to conveniently use GPIO inside OMAP DT.
For example:

	gpios = <&gpio6 3 0>;  /* GPIO 163 */

can be replaced by

	gpios = OMAP_GPIO(163, 0);

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 include/dt-bindings/gpio/omap-gpio.h |  289 ++++++++++++++++++++++++++++++++++
 1 files changed, 289 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/gpio/omap-gpio.h

diff --git a/include/dt-bindings/gpio/omap-gpio.h b/include/dt-bindings/gpio/omap-gpio.h
new file mode 100644
index 0000000..64f2686
--- /dev/null
+++ b/include/dt-bindings/gpio/omap-gpio.h
@@ -0,0 +1,289 @@
+/*
+ * This header provides macros and constants for binding ti,omap*-gpio
+ *
+ * Compatible with OMAP2, OMAP3, OMAP4 and OMAP5.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_OMAP_GPIO_H
+#define _DT_BINDINGS_GPIO_OMAP_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define OMAP_GPIO_0_BANK        gpio1
+#define OMAP_GPIO_1_BANK        gpio1
+#define OMAP_GPIO_2_BANK        gpio1
+#define OMAP_GPIO_3_BANK        gpio1
+#define OMAP_GPIO_4_BANK        gpio1
+#define OMAP_GPIO_5_BANK        gpio1
+#define OMAP_GPIO_6_BANK        gpio1
+#define OMAP_GPIO_7_BANK        gpio1
+#define OMAP_GPIO_8_BANK        gpio1
+#define OMAP_GPIO_9_BANK        gpio1
+#define OMAP_GPIO_10_BANK       gpio1
+#define OMAP_GPIO_11_BANK       gpio1
+#define OMAP_GPIO_12_BANK       gpio1
+#define OMAP_GPIO_13_BANK       gpio1
+#define OMAP_GPIO_14_BANK       gpio1
+#define OMAP_GPIO_15_BANK       gpio1
+#define OMAP_GPIO_16_BANK       gpio1
+#define OMAP_GPIO_17_BANK       gpio1
+#define OMAP_GPIO_18_BANK       gpio1
+#define OMAP_GPIO_19_BANK       gpio1
+#define OMAP_GPIO_20_BANK       gpio1
+#define OMAP_GPIO_21_BANK       gpio1
+#define OMAP_GPIO_22_BANK       gpio1
+#define OMAP_GPIO_23_BANK       gpio1
+#define OMAP_GPIO_24_BANK       gpio1
+#define OMAP_GPIO_25_BANK       gpio1
+#define OMAP_GPIO_26_BANK       gpio1
+#define OMAP_GPIO_27_BANK       gpio1
+#define OMAP_GPIO_28_BANK       gpio1
+#define OMAP_GPIO_29_BANK       gpio1
+#define OMAP_GPIO_30_BANK       gpio1
+#define OMAP_GPIO_31_BANK       gpio1
+
+#define OMAP_GPIO_32_BANK       gpio2
+#define OMAP_GPIO_33_BANK       gpio2
+#define OMAP_GPIO_34_BANK       gpio2
+#define OMAP_GPIO_35_BANK       gpio2
+#define OMAP_GPIO_36_BANK       gpio2
+#define OMAP_GPIO_37_BANK       gpio2
+#define OMAP_GPIO_38_BANK       gpio2
+#define OMAP_GPIO_39_BANK       gpio2
+#define OMAP_GPIO_40_BANK       gpio2
+#define OMAP_GPIO_41_BANK       gpio2
+#define OMAP_GPIO_42_BANK       gpio2
+#define OMAP_GPIO_43_BANK       gpio2
+#define OMAP_GPIO_44_BANK       gpio2
+#define OMAP_GPIO_45_BANK       gpio2
+#define OMAP_GPIO_46_BANK       gpio2
+#define OMAP_GPIO_47_BANK       gpio2
+#define OMAP_GPIO_48_BANK       gpio2
+#define OMAP_GPIO_49_BANK       gpio2
+#define OMAP_GPIO_50_BANK       gpio2
+#define OMAP_GPIO_51_BANK       gpio2
+#define OMAP_GPIO_52_BANK       gpio2
+#define OMAP_GPIO_53_BANK       gpio2
+#define OMAP_GPIO_54_BANK       gpio2
+#define OMAP_GPIO_55_BANK       gpio2
+#define OMAP_GPIO_56_BANK       gpio2
+#define OMAP_GPIO_57_BANK       gpio2
+#define OMAP_GPIO_58_BANK       gpio2
+#define OMAP_GPIO_59_BANK       gpio2
+#define OMAP_GPIO_60_BANK       gpio2
+#define OMAP_GPIO_61_BANK       gpio2
+#define OMAP_GPIO_62_BANK       gpio2
+#define OMAP_GPIO_63_BANK       gpio2
+
+#define OMAP_GPIO_64_BANK       gpio3
+#define OMAP_GPIO_65_BANK       gpio3
+#define OMAP_GPIO_66_BANK       gpio3
+#define OMAP_GPIO_67_BANK       gpio3
+#define OMAP_GPIO_68_BANK       gpio3
+#define OMAP_GPIO_69_BANK       gpio3
+#define OMAP_GPIO_70_BANK       gpio3
+#define OMAP_GPIO_71_BANK       gpio3
+#define OMAP_GPIO_72_BANK       gpio3
+#define OMAP_GPIO_73_BANK       gpio3
+#define OMAP_GPIO_74_BANK       gpio3
+#define OMAP_GPIO_75_BANK       gpio3
+#define OMAP_GPIO_76_BANK       gpio3
+#define OMAP_GPIO_77_BANK       gpio3
+#define OMAP_GPIO_78_BANK       gpio3
+#define OMAP_GPIO_79_BANK       gpio3
+#define OMAP_GPIO_80_BANK       gpio3
+#define OMAP_GPIO_81_BANK       gpio3
+#define OMAP_GPIO_82_BANK       gpio3
+#define OMAP_GPIO_83_BANK       gpio3
+#define OMAP_GPIO_84_BANK       gpio3
+#define OMAP_GPIO_85_BANK       gpio3
+#define OMAP_GPIO_86_BANK       gpio3
+#define OMAP_GPIO_87_BANK       gpio3
+#define OMAP_GPIO_88_BANK       gpio3
+#define OMAP_GPIO_89_BANK       gpio3
+#define OMAP_GPIO_90_BANK       gpio3
+#define OMAP_GPIO_91_BANK       gpio3
+#define OMAP_GPIO_92_BANK       gpio3
+#define OMAP_GPIO_93_BANK       gpio3
+#define OMAP_GPIO_94_BANK       gpio3
+#define OMAP_GPIO_95_BANK       gpio3
+
+#define OMAP_GPIO_96_BANK       gpio4
+#define OMAP_GPIO_97_BANK       gpio4
+#define OMAP_GPIO_98_BANK       gpio4
+#define OMAP_GPIO_99_BANK       gpio4
+#define OMAP_GPIO_100_BANK      gpio4
+#define OMAP_GPIO_101_BANK      gpio4
+#define OMAP_GPIO_102_BANK      gpio4
+#define OMAP_GPIO_103_BANK      gpio4
+#define OMAP_GPIO_104_BANK      gpio4
+#define OMAP_GPIO_105_BANK      gpio4
+#define OMAP_GPIO_106_BANK      gpio4
+#define OMAP_GPIO_107_BANK      gpio4
+#define OMAP_GPIO_108_BANK      gpio4
+#define OMAP_GPIO_109_BANK      gpio4
+#define OMAP_GPIO_110_BANK      gpio4
+#define OMAP_GPIO_111_BANK      gpio4
+#define OMAP_GPIO_112_BANK      gpio4
+#define OMAP_GPIO_113_BANK      gpio4
+#define OMAP_GPIO_114_BANK      gpio4
+#define OMAP_GPIO_115_BANK      gpio4
+#define OMAP_GPIO_116_BANK      gpio4
+#define OMAP_GPIO_117_BANK      gpio4
+#define OMAP_GPIO_118_BANK      gpio4
+#define OMAP_GPIO_119_BANK      gpio4
+#define OMAP_GPIO_120_BANK      gpio4
+#define OMAP_GPIO_121_BANK      gpio4
+#define OMAP_GPIO_122_BANK      gpio4
+#define OMAP_GPIO_123_BANK      gpio4
+#define OMAP_GPIO_124_BANK      gpio4
+#define OMAP_GPIO_125_BANK      gpio4
+#define OMAP_GPIO_126_BANK      gpio4
+#define OMAP_GPIO_127_BANK      gpio4
+
+/* Not available on OMAP2420 */
+#define OMAP_GPIO_128_BANK      gpio5
+#define OMAP_GPIO_129_BANK      gpio5
+#define OMAP_GPIO_130_BANK      gpio5
+#define OMAP_GPIO_131_BANK      gpio5
+#define OMAP_GPIO_132_BANK      gpio5
+#define OMAP_GPIO_133_BANK      gpio5
+#define OMAP_GPIO_134_BANK      gpio5
+#define OMAP_GPIO_135_BANK      gpio5
+#define OMAP_GPIO_136_BANK      gpio5
+#define OMAP_GPIO_137_BANK      gpio5
+#define OMAP_GPIO_138_BANK      gpio5
+#define OMAP_GPIO_139_BANK      gpio5
+#define OMAP_GPIO_140_BANK      gpio5
+#define OMAP_GPIO_141_BANK      gpio5
+#define OMAP_GPIO_142_BANK      gpio5
+#define OMAP_GPIO_143_BANK      gpio5
+#define OMAP_GPIO_144_BANK      gpio5
+#define OMAP_GPIO_145_BANK      gpio5
+#define OMAP_GPIO_146_BANK      gpio5
+#define OMAP_GPIO_147_BANK      gpio5
+#define OMAP_GPIO_148_BANK      gpio5
+#define OMAP_GPIO_149_BANK      gpio5
+#define OMAP_GPIO_150_BANK      gpio5
+#define OMAP_GPIO_151_BANK      gpio5
+#define OMAP_GPIO_152_BANK      gpio5
+#define OMAP_GPIO_153_BANK      gpio5
+#define OMAP_GPIO_154_BANK      gpio5
+#define OMAP_GPIO_155_BANK      gpio5
+#define OMAP_GPIO_156_BANK      gpio5
+#define OMAP_GPIO_157_BANK      gpio5
+#define OMAP_GPIO_158_BANK      gpio5
+#define OMAP_GPIO_159_BANK      gpio5
+
+/* Not available on OMAP2 */
+#define OMAP_GPIO_160_BANK      gpio6
+#define OMAP_GPIO_161_BANK      gpio6
+#define OMAP_GPIO_162_BANK      gpio6
+#define OMAP_GPIO_163_BANK      gpio6
+#define OMAP_GPIO_164_BANK      gpio6
+#define OMAP_GPIO_165_BANK      gpio6
+#define OMAP_GPIO_166_BANK      gpio6
+#define OMAP_GPIO_167_BANK      gpio6
+#define OMAP_GPIO_168_BANK      gpio6
+#define OMAP_GPIO_169_BANK      gpio6
+#define OMAP_GPIO_170_BANK      gpio6
+#define OMAP_GPIO_171_BANK      gpio6
+#define OMAP_GPIO_172_BANK      gpio6
+#define OMAP_GPIO_173_BANK      gpio6
+#define OMAP_GPIO_174_BANK      gpio6
+#define OMAP_GPIO_175_BANK      gpio6
+#define OMAP_GPIO_176_BANK      gpio6
+#define OMAP_GPIO_177_BANK      gpio6
+#define OMAP_GPIO_178_BANK      gpio6
+#define OMAP_GPIO_179_BANK      gpio6
+#define OMAP_GPIO_180_BANK      gpio6
+#define OMAP_GPIO_181_BANK      gpio6
+#define OMAP_GPIO_182_BANK      gpio6
+#define OMAP_GPIO_183_BANK      gpio6
+#define OMAP_GPIO_184_BANK      gpio6
+#define OMAP_GPIO_185_BANK      gpio6
+#define OMAP_GPIO_186_BANK      gpio6
+#define OMAP_GPIO_187_BANK      gpio6
+#define OMAP_GPIO_188_BANK      gpio6
+#define OMAP_GPIO_189_BANK      gpio6
+#define OMAP_GPIO_190_BANK      gpio6
+#define OMAP_GPIO_191_BANK      gpio6
+
+/* Only available on OMAP5 */
+#define OMAP_GPIO_192_BANK      gpio7
+#define OMAP_GPIO_193_BANK      gpio7
+#define OMAP_GPIO_194_BANK      gpio7
+#define OMAP_GPIO_195_BANK      gpio7
+#define OMAP_GPIO_196_BANK      gpio7
+#define OMAP_GPIO_197_BANK      gpio7
+#define OMAP_GPIO_198_BANK      gpio7
+#define OMAP_GPIO_199_BANK      gpio7
+#define OMAP_GPIO_200_BANK      gpio7
+#define OMAP_GPIO_201_BANK      gpio7
+#define OMAP_GPIO_202_BANK      gpio7
+#define OMAP_GPIO_203_BANK      gpio7
+#define OMAP_GPIO_204_BANK      gpio7
+#define OMAP_GPIO_205_BANK      gpio7
+#define OMAP_GPIO_206_BANK      gpio7
+#define OMAP_GPIO_207_BANK      gpio7
+#define OMAP_GPIO_208_BANK      gpio7
+#define OMAP_GPIO_209_BANK      gpio7
+#define OMAP_GPIO_210_BANK      gpio7
+#define OMAP_GPIO_211_BANK      gpio7
+#define OMAP_GPIO_212_BANK      gpio7
+#define OMAP_GPIO_213_BANK      gpio7
+#define OMAP_GPIO_214_BANK      gpio7
+#define OMAP_GPIO_215_BANK      gpio7
+#define OMAP_GPIO_216_BANK      gpio7
+#define OMAP_GPIO_217_BANK      gpio7
+#define OMAP_GPIO_218_BANK      gpio7
+#define OMAP_GPIO_219_BANK      gpio7
+#define OMAP_GPIO_220_BANK      gpio7
+#define OMAP_GPIO_221_BANK      gpio7
+#define OMAP_GPIO_222_BANK      gpio7
+#define OMAP_GPIO_223_BANK      gpio7
+
+/* Only available on OMAP5 */
+#define OMAP_GPIO_224_BANK      gpio8
+#define OMAP_GPIO_225_BANK      gpio8
+#define OMAP_GPIO_226_BANK      gpio8
+#define OMAP_GPIO_227_BANK      gpio8
+#define OMAP_GPIO_228_BANK      gpio8
+#define OMAP_GPIO_229_BANK      gpio8
+#define OMAP_GPIO_230_BANK      gpio8
+#define OMAP_GPIO_231_BANK      gpio8
+#define OMAP_GPIO_232_BANK      gpio8
+#define OMAP_GPIO_233_BANK      gpio8
+#define OMAP_GPIO_234_BANK      gpio8
+#define OMAP_GPIO_235_BANK      gpio8
+#define OMAP_GPIO_236_BANK      gpio8
+#define OMAP_GPIO_237_BANK      gpio8
+#define OMAP_GPIO_238_BANK      gpio8
+#define OMAP_GPIO_239_BANK      gpio8
+#define OMAP_GPIO_240_BANK      gpio8
+#define OMAP_GPIO_241_BANK      gpio8
+#define OMAP_GPIO_242_BANK      gpio8
+#define OMAP_GPIO_243_BANK      gpio8
+#define OMAP_GPIO_244_BANK      gpio8
+#define OMAP_GPIO_245_BANK      gpio8
+#define OMAP_GPIO_246_BANK      gpio8
+#define OMAP_GPIO_247_BANK      gpio8
+#define OMAP_GPIO_248_BANK      gpio8
+#define OMAP_GPIO_249_BANK      gpio8
+#define OMAP_GPIO_250_BANK      gpio8
+#define OMAP_GPIO_251_BANK      gpio8
+#define OMAP_GPIO_252_BANK      gpio8
+#define OMAP_GPIO_253_BANK      gpio8
+#define OMAP_GPIO_254_BANK      gpio8
+#define OMAP_GPIO_255_BANK      gpio8
+
+
+#define _OMAP_GPIO_OFFSET(gpio) \
+	(gpio & 0x1F)
+
+
+/* Declare a reference to an OMAP GPIO */
+#define OMAP_GPIO(gpio, level) \
+	<&OMAP_GPIO_##gpio##_BANK _OMAP_GPIO_OFFSET(gpio) level>
+
+#endif
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Wed May 22 10:27:40 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 16:27:40 +0200
Subject: [PATCH 1/5] ARM: dts: OMAP2+: use #include for all device trees
In-Reply-To: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369232864-14460-2-git-send-email-florian.vaussard@epfl.ch>

Replace /include/ by #include for OMAP2+ DT, in order to use the
C pre-processor, making use of #define features possible.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    4 ++--
 arch/arm/boot/dts/omap3-devkit8000.dts    |    4 ++--
 arch/arm/boot/dts/omap3-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap3-igep.dtsi         |    4 ++--
 arch/arm/boot/dts/omap3-igep0020.dts      |    2 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |    2 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 ++--
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 ++--
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-panda-es.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda.dts         |    4 ++--
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    2 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +++---
 arch/arm/boot/dts/omap4-var-som.dts       |    4 ++--
 arch/arm/boot/dts/omap4.dtsi              |    2 +-
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    2 +-
 arch/arm/boot/dts/omap5-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap5.dtsi              |    2 +-
 29 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..e6e4587 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee..224c08f 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 
 / {
 	model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285..c8f9c55 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc44..c535a5a 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..e0ce823 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard xM";
@@ -75,7 +75,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..fcac96a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard";
@@ -107,7 +107,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc..8d0f5e4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
 	model = "TimLL OMAP3 Devkit8000";
 	compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -80,7 +80,7 @@
 	status = "disabled";
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c20..d75759b 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -44,7 +44,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index f8fe3b7..54588b0 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	memory {
@@ -80,7 +80,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e2b9849..2f96a5c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEPv2";
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 9dc48d2..f3a1bf0 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEP COM Module";
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50..e112a42 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	pwmleds {
@@ -49,7 +49,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 /* i2c2 pins are used for gpio */
 &i2c2 {
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12d..5df894f 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 
 / {
 	model = "TI OMAP3 Gumstix Overo on Tobi";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..7c7d494 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap3430", "ti,omap3";
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43..2a725a0 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3430 SDP";
@@ -28,7 +28,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae..5355d61 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc..f8b3765 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0..f18fb5c 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..63148d1 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 PandaBoard";
@@ -164,7 +164,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c6f012e 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f..6189a8b 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ff..4f26355 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd..5edd08e 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 SDP board";
@@ -316,7 +316,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103..6593607 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 
 / {
 	model = "Variscite OMAP4 SOM";
@@ -39,7 +39,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..53d80aa 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,7 +14,7 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..a81f8df 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..41762c2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 982acd1..f5f55d1 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
+#include "omap5.dtsi"
+#include "samsung_k3pe0e000b.dtsi"
 
 / {
 	model = "TI OMAP5 EVM board";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..e8e6653 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -15,7 +15,7 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	#address-cells = <1>;
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Wed May 22 10:27:44 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 16:27:44 +0200
Subject: [PATCH 5/5] ARM: dts: OMAP4/5: use existing constants for IRQs
In-Reply-To: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369232864-14460-6-git-send-email-florian.vaussard@epfl.ch>

Use the constants defined in include/dt-bindings/interrupt-controller/
to enhance readability.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +-
 arch/arm/boot/dts/omap4-var-som.dts       |    4 +-
 arch/arm/boot/dts/omap4.dtsi              |  113 ++++++++++++++-------------
 arch/arm/boot/dts/omap4460.dtsi           |    4 +-
 arch/arm/boot/dts/omap5.dtsi              |  121 +++++++++++++++--------------
 6 files changed, 129 insertions(+), 127 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index b71f5cd..c2354c9 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -145,16 +145,16 @@
 
 	twl: twl at 48 {
 		reg = <0x48>;
-		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		/* IRQ# = 7 */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
 	twl6040: twl at 4b {
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
-		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		/* IRQ# = 119 */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = OMAP_GPIO(127, GPIO_ACTIVE_HIGH);
 
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index f55bb68..3ce4987 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -286,7 +286,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
@@ -294,7 +294,7 @@
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = OMAP_GPIO(127, GPIO_ACTIVE_HIGH);
 
@@ -375,7 +375,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <2 8>; /* gpio line 34, low triggered */
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34, low triggered */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6593607..135ba45 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -34,7 +34,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 };
@@ -68,7 +68,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <11 8>; /* gpio line 171, low triggered */
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171, low triggered */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3c00b72..d1037ac 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -15,6 +15,7 @@
 /memreserve/ 0x9d000000 0x03000000;
 
 #include <dt-bindings/gpio/omap-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -58,7 +59,7 @@
 	local-timer at 0x48240600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x48240600 0x20>;
-		interrupts = <1 13 0x304>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	/*
@@ -99,8 +100,8 @@
 		reg = <0x44000000 0x1000>,
 		      <0x44800000 0x2000>,
 		      <0x45000000 0x1000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4a304000 {
 			compatible = "ti,omap-counter32k";
@@ -128,10 +129,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -140,7 +141,7 @@
 		gpio1: gpio at 4a310000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4a310000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -152,7 +153,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -163,7 +164,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -174,7 +175,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -185,7 +186,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -196,7 +197,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -209,7 +210,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -218,7 +219,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -226,7 +227,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -234,7 +235,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -242,7 +243,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -250,7 +251,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -259,7 +260,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -268,7 +269,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -277,7 +278,7 @@
 		i2c4: i2c at 48350000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48350000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -286,7 +287,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -306,7 +307,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -321,7 +322,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -333,7 +334,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -345,7 +346,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -356,7 +357,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -366,7 +367,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -376,7 +377,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -386,7 +387,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -396,7 +397,7 @@
 		wdt2: wdt at 4a314000 {
 			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 			reg = <0x4a314000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -405,7 +406,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -417,7 +418,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -428,7 +429,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -442,7 +443,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -456,7 +457,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -469,7 +470,7 @@
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */
 			reg-names = "mpu";
-			interrupts = <0 16 0x4>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp4";
@@ -481,7 +482,7 @@
 		keypad: keypad at 4a31c000 {
 			compatible = "ti,omap4-keypad";
 			reg = <0x4a31c000 0x80>;
-			interrupts = <0 120 0x4>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
 		};
@@ -489,7 +490,7 @@
 		emif1: emif at 4c000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4c000000 0x100>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif1";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -500,7 +501,7 @@
 		emif2: emif at 4d000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4d000000 0x100>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif2";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -525,7 +526,7 @@
 		timer1: timer at 4a318000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x4a318000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -533,21 +534,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -555,7 +556,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -564,7 +565,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 		};
@@ -573,7 +574,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -582,7 +583,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
@@ -591,7 +592,7 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
 		};
@@ -599,7 +600,7 @@
 		timer10: timer at 48086000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
 		};
@@ -607,7 +608,7 @@
 		timer11: timer at 48088000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -615,7 +616,7 @@
 		usbhstll: usbhstll at 4a062000 {
 			compatible = "ti,usbhs-tll";
 			reg = <0x4a062000 0x1000>;
-			interrupts = <0 78 0x4>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
 		};
 
@@ -631,14 +632,14 @@
 				compatible = "ti,ohci-omap3", "usb-ohci";
 				reg = <0x4a064800 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 76 0x4>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			usbhsehci: ehci at 4a064c00 {
 				compatible = "ti,ehci-omap", "usb-ehci";
 				reg = <0x4a064c00 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 77 0x4>;
+				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
 
@@ -653,7 +654,7 @@
 		usb_otg_hs: usb_otg_hs at 4a0ab000 {
 			compatible = "ti,omap4-musb";
 			reg = <0x4a0ab000 0x7ff>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 41762c2..19628b1 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -25,8 +25,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 54 0x4>,
-			     <0 55 0x4>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		ti,hwmods = "debugss";
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index af849e6..cbdaa3c 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -16,6 +16,7 @@
 /memreserve/ 0x9d000000 0x03000000;
 
 #include <dt-bindings/gpio/omap-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -47,10 +48,10 @@
 	timer {
 		compatible = "arm,armv7-timer";
 		/* PPI secure/nonsecure IRQ, active low level-sensitive */
-		interrupts = <1 13 0x308>,
-			     <1 14 0x308>,
-			     <1 11 0x308>,
-			     <1 10 0x308>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <6144000>;
 	};
 
@@ -92,8 +93,8 @@
 		reg = <0x44000000 0x2000>,
 		      <0x44800000 0x3000>,
 		      <0x45000000 0x4000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
@@ -121,10 +122,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -133,7 +134,7 @@
 		gpio1: gpio at 4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -145,7 +146,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -156,7 +157,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -167,7 +168,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -178,7 +179,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -189,7 +190,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -200,7 +201,7 @@
 		gpio7: gpio at 48051000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48051000 0x200>;
-			interrupts = <0 35 0x4>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio7";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -211,7 +212,7 @@
 		gpio8: gpio at 48053000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48053000 0x200>;
-			interrupts = <0 121 0x4>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio8";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -224,7 +225,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -233,7 +234,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -242,7 +243,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -251,7 +252,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -260,7 +261,7 @@
 		i2c4: i2c at 4807a000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807a000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -269,7 +270,7 @@
 		i2c5: i2c at 4807c000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807c000 0x100>;
-			interrupts = <0 60 0x4>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c5";
@@ -278,7 +279,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -298,7 +299,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -313,7 +314,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -325,7 +326,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -337,7 +338,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -345,7 +346,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -353,7 +354,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -361,7 +362,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -369,7 +370,7 @@
 		uart5: serial at 48066000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48066000 0x100>;
-			interrupts = <0 105 0x4>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 		};
@@ -377,7 +378,7 @@
 		uart6: serial at 48068000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48068000 0x100>;
-			interrupts = <0 106 0x4>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 		};
@@ -385,7 +386,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -396,7 +397,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -406,7 +407,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -416,7 +417,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -426,7 +427,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -444,7 +445,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -456,7 +457,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -467,7 +468,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -481,7 +482,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -495,7 +496,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -507,7 +508,7 @@
 		timer1: timer at 4ae18000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4ae18000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -515,21 +516,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -537,7 +538,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -546,7 +547,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -556,7 +557,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -565,7 +566,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -574,21 +575,21 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 		};
 
 		timer10: timer at 48086000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 		};
 
 		timer11: timer at 48088000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -596,7 +597,7 @@
 		wdt2: wdt at 4ae14000 {
 			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 			reg = <0x4ae14000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -605,7 +606,7 @@
 			ti,hwmods	= "emif1";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4c000000 0x400>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -616,7 +617,7 @@
 			ti,hwmods	= "emif2";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4d000000 0x400>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -634,7 +635,7 @@
 			compatible = "ti,dwc3";
 			ti,hwmods = "usb_otg_ss";
 			reg = <0x4a020000 0x1000>;
-			interrupts = <0 93 4>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			utmi-mode = <2>;
@@ -642,7 +643,7 @@
 			dwc3 at 4a030000 {
 				compatible = "synopsys,dwc3";
 				reg = <0x4a030000 0x1000>;
-				interrupts = <0 92 4>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 				usb-phy = <&usb2_phy>, <&usb3_phy>;
 				tx-fifo-resize;
 			};
-- 
1.7.5.4



From mst at redhat.com  Wed May 22 10:30:00 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 17:30:00 +0300
Subject: [PATCH v2 07/10] powerpc: uaccess s/might_sleep/might_fault/
In-Reply-To: <201305221559.01806.arnd@arndb.de>
References: <cover.1368702323.git.mst@redhat.com>
 <2aa6c3da21a28120126732b5e0b4ecd6cba8ca3b.1368702323.git.mst@redhat.com>
 <201305221559.01806.arnd@arndb.de>
Message-ID: <20130522143000.GA21886@redhat.com>

On Wed, May 22, 2013 at 03:59:01PM +0200, Arnd Bergmann wrote:
> On Thursday 16 May 2013, Michael S. Tsirkin wrote:
> > @@ -178,7 +178,7 @@ do {                                                                \
> >         long __pu_err;                                          \
> >         __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
> >         if (!is_kernel_addr((unsigned long)__pu_addr))          \
> > -               might_sleep();                                  \
> > +               might_fault();                                  \
> >         __chk_user_ptr(ptr);                                    \
> >         __put_user_size((x), __pu_addr, (size), __pu_err);      \
> >         __pu_err;                                               \
> > 
> 
> Another observation:
> 
> 	if (!is_kernel_addr((unsigned long)__pu_addr))
> 		might_sleep();
> 
> is almost the same as
> 
> 	might_fault();
> 
> except that it does not call might_lock_read().
> 
> The version above may have been put there intentionally and correctly, but
> if you want to replace it with might_fault(), you should remove the
> "if ()" condition.
> 
> 	Arnd

Good point, thanks.
I think I'll do it in a separate patch on top,
just to make sure bisect does not result in a revision that
produces false positive warnings.

-- 
MST


From lee.jones at linaro.org  Wed May 22 10:22:54 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:22:54 +0100
Subject: [PATCH 0/7] ARM: ux500: Change naming convention for pinctrl 
Message-ID: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>

Our naming convention started off sensibly, but with the addition of
more supported platforms it's slipped a little. Most compatible strings
standardise themselves with "<vendor>,<device_name>-<device_type>",
which we had initially with "stericsson,nmk-pinctrl", but with more
devices to support we now have a tail, so we are using
"<vendor>,<driver_name>-<device_type>-<device_name>", which is
unsuitable.

This patch-set ensures the standard convention is used again.



From lee.jones at linaro.org  Wed May 22 10:22:56 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:22:56 +0100
Subject: [PATCH 2/7] ARM: ux500: Standardise Nomadik STN8815 based Pinctrl
 compat string in the DTS
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-3-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/ste-nomadik-stn8815.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 4a4aab3..a6c2112 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -84,7 +84,7 @@
 	};
 
 	pinctrl {
-		compatible = "stericsson,nmk-pinctrl-stn8815";
+		compatible = "stericsson,stn8815-pinctrl";
 	};
 
 	/* A NAND flash of 128 MiB */
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 10:22:55 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:22:55 +0100
Subject: [PATCH 1/7] ARM: ux500: Standardise DBx5x0 based Pinctrl compat
 string in the DTS
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-2-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 6c25fbe..d0835ca 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -171,7 +171,7 @@
 		};
 
 		pinctrl {
-			compatible = "stericsson,nmk-pinctrl";
+			compatible = "stericsson,db8500-pinctrl";
 			prcm = <&prcmu>;
 		};
 
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 10:22:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:22:57 +0100
Subject: [PATCH 3/7] ARM: ux500: Standardise Pinctrl compatible string for
 Nomadik based platforms
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-4-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-nomadik/cpu-8815.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5..316fe82 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -288,7 +288,7 @@ static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
 		"gpio.2", NULL),
 	OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
 		"gpio.3", NULL),
-	OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
+	OF_DEV_AUXDATA("stericsson,stn8815-pinctrl", 0,
 		"pinctrl-stn8815", NULL),
 	OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
 		"uart0", NULL),
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 10:23:00 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:23:00 +0100
Subject: [PATCH 6/7] pinctrl/nomadik: Standardise Pinctrl compat string for
 DBx5x based platforms
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-7-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/pinctrl/pinctrl-nomadik.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 7712d93..8a4f9c5 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -2108,11 +2108,11 @@ static const struct of_device_id nmk_pinctrl_match[] = {
 		.data = (void *)PINCTRL_NMK_STN8815,
 	},
 	{
-		.compatible = "stericsson,nmk-pinctrl",
+		.compatible = "stericsson,db8500-pinctrl",
 		.data = (void *)PINCTRL_NMK_DB8500,
 	},
 	{
-		.compatible = "stericsson,nmk-pinctrl-db8540",
+		.compatible = "stericsson,db8540-pinctrl",
 		.data = (void *)PINCTRL_NMK_DB8540,
 	},
 	{},
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 10:22:58 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:22:58 +0100
Subject: [PATCH 4/7] ARM: ux500: Standardise Pinctrl compatible string for
 DBx5x based platforms
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-5-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 8305bad..27c9382 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -249,7 +249,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
 	OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
 	/* Requires device name bindings. */
-	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
+	OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
 	/* Requires clock name and DMA bindings. */
 	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 10:22:59 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:22:59 +0100
Subject: [PATCH 5/7] pinctrl/nomadik: Standardise Pinctrl compat string for
 Nomadik based platforms
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-6-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/pinctrl/pinctrl-nomadik.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 3428175..7712d93 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -2104,7 +2104,7 @@ static struct pinctrl_desc nmk_pinctrl_desc = {
 
 static const struct of_device_id nmk_pinctrl_match[] = {
 	{
-		.compatible = "stericsson,nmk-pinctrl-stn8815",
+		.compatible = "stericsson,stn8815-pinctrl",
 		.data = (void *)PINCTRL_NMK_STN8815,
 	},
 	{
-- 
1.7.10.4



From lee.jones at linaro.org  Wed May 22 10:23:01 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:23:01 +0100
Subject: [PATCH 7/7] Documentation: Update binding for Nomadik and DBx5x based
 platforms
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1369232581-18923-8-git-send-email-lee.jones@linaro.org>

Change compatible string to something more standard.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
index 9a2f3f4..c3d8a89 100644
--- a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
@@ -1,8 +1,8 @@
 ST Ericsson Nomadik pinmux controller
 
 Required properties:
-- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
-              "stericsson,nmk-pinctrl-stn8815"
+- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
+              "stericsson,stn8815-pinctrl"
 - reg: Should contain the register physical address and length of the PRCMU.
 
 Please refer to pinctrl-bindings.txt in this directory for details of the
@@ -68,7 +68,7 @@ Optional subnode-properties:
 Example board file extract:
 
 	pinctrl at 80157000 {
-		compatible = "stericsson,nmk-pinctrl";
+		compatible = "stericsson,u8500-pinctrl";
 		reg = <0x80157000 0x2000>;
 
 		pinctrl-names = "default";
-- 
1.7.10.4



From bhelgaas at google.com  Wed May 22 10:31:33 2013
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 22 May 2013 08:31:33 -0600
Subject: [PATCH 2/4] pci: mvebu: allow the enumeration of devices beyond
 physical bridges
In-Reply-To: <1369228358-32580-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369228358-32580-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <CAErSpo6J2ZFOosTWQ5uN_6aAFziUEFK2Es3e3A8pTtrdrf6bdQ@mail.gmail.com>

On Wed, May 22, 2013 at 7:12 AM, Thomas Petazzoni
<thomas.petazzoni at free-electrons.com> wrote:
> Until now, the Marvell PCIe driver was only allowing the enumeration
> of the devices in the secondary bus of the emulated PCI-to-PCI
> bridge. This works fine when a PCIe device is directly connected into
> a PCIe slot of the Marvell board.
>
> However, when the device connected in the PCIe slot is a physical PCIe
> bridge, beyond which a real PCIe device is connected, it no longer
> worked, as the driver was preventing the Linux PCI core from seeing
> such devices.
>
> This commit fixes that by ensuring that configuration transactions on
> subordinate busses are properly forwarded on the right PCIe interface.
>
> Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
> the emulated PCI-to-PCI bridge is properly detected, with the
> following layout:
>
> -[0000:00]-+-01.0-[01]----00.0
>            +-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
>            |                               +-05.0-[05]--
>            |                               +-07.0-[06]--
>            |                               \-09.0-[07]----00.0
>            \-0a.0-[08]----00.0
>
> Where the PCIe interface that sits beyond the emulated PCI-to-PCI
> bridge at 09.0 allows to access the secondary bus 02, on which there
> is a PCIe bridge that allows to access the 3 to 7 busses, that are
> subordinates to this bridge. And on one of this bus (bus 7), there is
> one real PCIe device connected.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  drivers/pci/host/pci-mvebu.c |   31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> index 0bc21b0..c21ca84 100644
> --- a/drivers/pci/host/pci-mvebu.c
> +++ b/drivers/pci/host/pci-mvebu.c
> @@ -554,7 +554,8 @@ mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
>                 if (bus->number == 0 && port->devfn == devfn)
>                         return port;
>                 if (bus->number != 0 &&
> -                   port->bridge.secondary_bus == bus->number)
> +                   bus->number >= port->bridge.secondary_bus &&
> +                   bus->number <= port->bridge.subordinate_bus)
>                         return port;
>         }
>
> @@ -578,7 +579,18 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>         if (bus->number == 0)
>                 return mvebu_sw_pci_bridge_write(port, where, size, val);
>
> -       if (!port->haslink || PCI_SLOT(devfn) != 0)
> +       if (!port->haslink)
> +               return PCIBIOS_DEVICE_NOT_FOUND;
> +
> +       /*
> +        * On the secondary bus, we don't want to expose any other
> +        * device that the device physically connected in the PCIe

s/that/than/ (also below)

> +        * slot, visible in slot 0. In slot 1, there's a special
> +        * Marvell device that only makes sense when the Armada is
> +        * used as a PCIe endpoint.
> +        */
> +       if (bus->number == port->bridge.secondary_bus &&
> +           PCI_SLOT(devfn) != 0)
>                 return PCIBIOS_DEVICE_NOT_FOUND;
>
>         /* Access the real PCIe interface */
> @@ -609,7 +621,20 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
>         if (bus->number == 0)
>                 return mvebu_sw_pci_bridge_read(port, where, size, val);
>
> -       if (!port->haslink || PCI_SLOT(devfn) != 0) {
> +       if (!port->haslink) {
> +               *val = 0xffffffff;
> +               return PCIBIOS_DEVICE_NOT_FOUND;
> +       }
> +
> +       /*
> +        * On the secondary bus, we don't want to expose any other
> +        * device that the device physically connected in the PCIe
> +        * slot, visible in slot 0. In slot 1, there's a special
> +        * Marvell device that only makes sense when the Armada is
> +        * used as a PCIe endpoint.
> +        */
> +       if (bus->number == port->bridge.secondary_bus &&
> +           PCI_SLOT(devfn) != 0) {
>                 *val = 0xffffffff;
>                 return PCIBIOS_DEVICE_NOT_FOUND;
>         }
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From horms at verge.net.au  Wed May 22 10:32:04 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 23:32:04 +0900
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
Message-ID: <20130522143204.GE32012@verge.net.au>

On Fri, May 17, 2013 at 03:00:23PM +0200, Guennadi Liakhovetski wrote:
> Hi Simon, Magnus
> 
> On Wed, 3 Apr 2013, Simon Horman wrote:
> 
> > From: Magnus Damm <damm at opensource.se>
> > 
> > Add LAN9220 support to the APE6EVM board using C and DT.
> > At this point the PFC driver lacks DT bindings so to
> > configure the PFC we use PINCTRL in C board code.
> > 
> > Signed-off-by: Magnus Damm <damm at opensource.se>
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > ---
> >  arch/arm/boot/dts/r8a73a4-ape6evm.dts  |   23 ++++++++++++++++++-
> >  arch/arm/mach-shmobile/board-ape6evm.c |   38 ++++++++++++++++++++++++++++++++
> >  2 files changed, 60 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > index 833f703..f603c69 100644
> > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > @@ -16,7 +16,7 @@
> >  	compatible = "renesas,ape6evm", "renesas,r8a73a4";
> >  
> >  	chosen {
> > -		bootargs = "console=ttySC0,115200 ignore_loglevel";
> > +		bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
> >  	};
> >  
> >  	memory at 40000000 {
> > @@ -24,8 +24,29 @@
> >  		reg = <0 0x40000000 0 0x40000000>;
> >  	};
> >  
> > +	ape6evm_fixed_3v3: fixedregulator at 0 {
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "3V3";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		regulator-always-on;
> > +	};
> > +
> >  	lbsc {
> >  		#address-cells = <1>;
> >  		#size-cells = <1>;
> > +
> > +		ethernet at 8000000 {
> > +			compatible = "smsc,lan9118", "smsc,lan9115";
> > +			reg = <0x08000000 0x1000>;
> > +			interrupt-parent = <&irqc1>;
> > +			interrupts = <8 0x4>;
> > +			phy-mode = "mii";
> > +			reg-io-width = <4>;
> > +			smsc,irq-active-high;
> > +			smsc,irq-push-pull;
> > +			vdd33a-supply = <&ape6evm_fixed_3v3>;
> > +			vddvario-supply = <&ape6evm_fixed_3v3>;
> > +		};
> >  	};
> >  };
> 
> The above didn't work in my tests without this:
> 
> diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
> b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> index f603c69..4fb0102 100644
> --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> @@ -33,8 +33,10 @@
>  	};
>  
>  	lbsc {
> +		compatible = "simple-bus";
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> +		ranges = <0 0 0 0x80000000>;
>  
>  		ethernet at 8000000 {
>  			compatible = "smsc,lan9118", "smsc,lan9115";
> 

Could you please post this as a formal patch and indicate
if you would like it included as a fix in v3.10 or not?

Also, I am curious to know what your tests are.


From arnd at arndb.de  Wed May 22 10:33:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 16:33:46 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <201305221633.46705.arnd@arndb.de>

On Tuesday 21 May 2013, Thomas Petazzoni wrote:
> Unfortunately, for Armada 370 and Armada XP, the current generation of
> bootloaders that are being shipped on Marvell evaluation boards, but
> also on products like the Plathome OpenBlocks AX3 or the Globalscale
> Mirabox do not do the remapping, and are leaving the internal
> registers at 0xD0000000.
> 
> However, this is causing some problems:
> 
>  1 The internal registers window sits at 3 GB, in the middle of the
>    0-4 GB area of physical memory, which is quite annoying when you
>    have more than 3 GB of memory. Having them at 0xF1000000 means that
>    you lose less RAM when you have more than 3 GB of physical memory
>    installed. And since Armada XP is LPAE capable, you can even have
>    more than 4 GB memory: we already have boards with 8 GB of memory
>    installed.

Just for completeness:

Do any of the machines that use the old boot loader have more
than 3 GB of memory?

>  2 This is different from Kirkwood and Dove, which makes sharing some
>    early code like earlyprintk complicated, while our goal is
>    ultimately to merge all Marvell EBU platforms into mach-mvebu.
> 
> (1) is really the primary motivation here, (2) is only a nice
> side-effect.
> 
> So, the new generation of bootloaders that are shipped on new Marvell
> Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
> starting Linux. The current kernel cannot boot on such platforms.

Does it boot if you disable the DEBUG_LL code and apply your
patches 1-8? The reason I'm asking is that you already cannot have
DEBUG_LL on a multiplatform kernel targeted at systems which don't
use the same UART. Adding a further restriction that they must map
the internal registers to the same physical address does not change
this a lot.

> Therefore, the last patch of this series adds some early code in the
> kernel, at the ->map_io() stage, to switch the internal registers from
> 0xD0000000 to 0xF1000000 if this has not been done already by the
> bootloader. As it was explained above, we unfortunately can't read the
> current base address of the internal register window, so we need a
> different mechanism to know if the bootloader has done the remapping
> at 0xF1000000 (new generation bootloader) or has left the internal
> registers at 0xD0000000 (old generation bootloader). In order to
> distinguish between those two cases, a CP15 bit is being used. Old
> bootloaders do not touch this CP15, so it is set to 0. New bootloaders
> set this CP15 bit to 1, so that the kernel knows that the remapping
> has already been done. The ->map_io() code looks at this bit to know
> if the remapping should be done or not.

As you already admit, using the CP15 register is a hack. It sounds
to me that a cleaner approach would be to put the correct address
into the device tree and use that value everywhere, rather than
hardcoding one or more addresses.

> Unfortunately, tweaking ->map_io() is not sufficient: we also want
> earlyprintk to work. And earlyprintk is used *before* ->map_io() is
> called, and *after* ->map_io() is called.

Note that by the time map_io is called, we no longer care about
the physical address, since the uart is only accessed through the
virtual mapping after __enable_mmu.

	Arnd


From lee.jones at linaro.org  Wed May 22 10:36:42 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:36:42 +0100
Subject: [PATCH] ARM: ux500: Apply other compatible name to the u8540 DTS file
Message-ID: <1369233402-19225-1-git-send-email-lee.jones@linaro.org>

The common name for the 8540 is the u8540, but the fully qualified
name, or proper name is ccu8540. Ensure both are available to drivers
and platform code that wish to use them.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/ccu8540.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
index 18daa01..af4487f 100644
--- a/arch/arm/boot/dts/ccu8540.dts
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -14,7 +14,7 @@
 
 / {
 	model = "ST-Ericsson U8540 platform with Device Tree";
-	compatible = "st-ericsson,u8540";
+	compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
 
 	memory {
 		reg = <0x00000000 0x20000000>;
-- 
1.7.10.4



From bhelgaas at google.com  Wed May 22 10:39:03 2013
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 22 May 2013 08:39:03 -0600
Subject: [PATCH 3/4] pci: mvebu: emulate an empty capability list
In-Reply-To: <1369228358-32580-4-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369228358-32580-4-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <CAErSpo6gFf9ou-VtZ=F0+1GqcSoPS_dDMGphhgv=8mD602=BRA@mail.gmail.com>

On Wed, May 22, 2013 at 7:12 AM, Thomas Petazzoni
<thomas.petazzoni at free-electrons.com> wrote:
> Currently, our PCI-to-PCI bridge emulation doesn't emulate a proper
> capability list, which leads 'lspci -v' to show:
>
>   Capabilities: [fc] <chain broken>
>
> In order to fix this, this commit improve the PCI-to-PCI bridge

s/improve/improves/

> emulation to emulate an empty capability list. It might be later
> extended to expose things like the PCI Express Capability header, but
> an empty capability list is sufficient for now.
>
> lspci -v now shows the much nicer:
>
>   Capabilities: [40] #00 [0000]

It'd be even better if you could make the Capabilities List bit in the
Device Status register be zero.  Then lspci wouldn't even try to read
the Capabilities Pointer at 0x34, and you wouldn't have to deal with
reads of 0x40.

> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  drivers/pci/host/pci-mvebu.c |   10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> index c21ca84..c887598 100644
> --- a/drivers/pci/host/pci-mvebu.c
> +++ b/drivers/pci/host/pci-mvebu.c
> @@ -440,6 +440,16 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
>                 *value = 0;
>                 break;
>
> +       case PCI_CAPABILITY_LIST:
> +               /* Offset of the capability list */
> +               *value = 0x40;
> +               break;
> +
> +       case 0x40:
> +               /* We have no element in our capability list */
> +               *value = 0;
> +               break;
> +
>         default:
>                 *value = 0xffffffff;
>                 return PCIBIOS_BAD_REGISTER_NUMBER;
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From horms at verge.net.au  Wed May 22 10:39:40 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 23:39:40 +0900
Subject: [PATCH FOR v3.10 v2] ARM: shmobile: kzm9g-reference: Update CMT
 clocksource rating to 80
In-Reply-To: <519CD3F0.7050002@cogentembedded.com>
References: <1369232020-22681-1-git-send-email-horms+renesas@verge.net.au>
 <519CD3F0.7050002@cogentembedded.com>
Message-ID: <20130522143940.GF32012@verge.net.au>

On Wed, May 22, 2013 at 06:19:28PM +0400, Sergei Shtylyov wrote:
> On 22-05-2013 18:13, Simon Horman wrote:
> 
> >Update the CMT clocksource rating from 125 to 80.
> 
> >This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
> >introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
> >Avoid dummy clockevent being preferred over real").
> 
> >The patch noted above reduces the rating of dummy clockevent from 400 to 100.
> >This patch reduces the rating of CMT so that it is once again less than that
> >of the dummy clockevent.
> 
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> >---
> 
> >I also plan to reduce the rating of the STI clocksource to less than 100.
> >However, as I am not aware of any problems relating to STI in v3.10-rc
> >my plan is to update STI in the v3.11 timeframe.
> >---
> >  arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> 
>    BTW, shouldn't the subject be "ARM: shmobile: sh73a0: Update CMT
> clocksource rating to 80"?

Yes, silly me.

I'll fix that.


From linux at arm.linux.org.uk  Wed May 22 10:40:42 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 May 2013 15:40:42 +0100
Subject: [PATCH 02/11] gpio: davinci: coding style correction
In-Reply-To: <1369206634-6778-3-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-3-git-send-email-avinashphilip@ti.com>
Message-ID: <20130522144042.GG18614@n2100.arm.linux.org.uk>

On Wed, May 22, 2013 at 12:40:25PM +0530, Philip Avinash wrote:
>  /*
>   * Assuming the pin is muxed as a gpio output, set its output value.
>   */
> -static void
> -davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
> +static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
> +		int value)

This kind of stuff is just churn.  If you read Documentation/CodingStyle:

Statements longer than 80 columns will be broken into sensible chunks, unless
exceeding 80 columns significantly increases readability and does not hide
information. Descendants are always substantially shorter than the parent and
are placed substantially to the right. The same applies to function headers
with a long argument list. However, never break user-visible strings such as
printk messages, because that breaks the ability to grep for them.

"broken into sensible chunks".  Here's the question: is the former a
sensible format?  Arguably it is because it results in all the arguments
fitting on one line at the expense of missing the return value.

The latter is also a sensible format - but breaks the arguments instead
of the return value.

Both formats can be found in their entirety by grep by function name alone:

	grep -1 davinci_gpio_set

or if you prefer to type some more then you end up with more specific

	grep -A1 davinci_gpio_set
or
	grep -B1 davinci_gpio_set

depending on the version.

Where there's no clear advantage one way or the other, let the authors
preference stand.


From arnd at arndb.de  Wed May 22 10:41:33 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 16:41:33 +0200
Subject: [PATCH] ARM: ux500: Apply other compatible name to the u8540 DTS
 file
In-Reply-To: <1369233402-19225-1-git-send-email-lee.jones@linaro.org>
References: <1369233402-19225-1-git-send-email-lee.jones@linaro.org>
Message-ID: <201305221641.33602.arnd@arndb.de>

On Wednesday 22 May 2013, Lee Jones wrote:
> The common name for the 8540 is the u8540, but the fully qualified
> name, or proper name is ccu8540. Ensure both are available to drivers
> and platform code that wish to use them.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I'm confused by this. I thought that u8540 is the chipset while ccu8540 is
the board. Is that wrong?

	Arnd


From gregory.clement at free-electrons.com  Wed May 22 10:41:36 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 22 May 2013 16:41:36 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305221633.46705.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de>
Message-ID: <519CD920.5030301@free-electrons.com>

On 05/22/2013 04:33 PM, Arnd Bergmann wrote:
> On Tuesday 21 May 2013, Thomas Petazzoni wrote:
>> Unfortunately, for Armada 370 and Armada XP, the current generation of
>> bootloaders that are being shipped on Marvell evaluation boards, but
>> also on products like the Plathome OpenBlocks AX3 or the Globalscale
>> Mirabox do not do the remapping, and are leaving the internal
>> registers at 0xD0000000.
>>
>> However, this is causing some problems:
>>
>>  1 The internal registers window sits at 3 GB, in the middle of the
>>    0-4 GB area of physical memory, which is quite annoying when you
>>    have more than 3 GB of memory. Having them at 0xF1000000 means that
>>    you lose less RAM when you have more than 3 GB of physical memory
>>    installed. And since Armada XP is LPAE capable, you can even have
>>    more than 4 GB memory: we already have boards with 8 GB of memory
>>    installed.
> 
> Just for completeness:
> 
> Do any of the machines that use the old boot loader have more
> than 3 GB of memory?

As far as I know at least the Armada XP GP boards.

Moreover the OpenBlocks AX3 have non soldered memory, so
it could be possible to plug any amount of memory you want.
Howevere it is true that in this case you will have to update the
bootloader to setup the memory chip.

> 
>>  2 This is different from Kirkwood and Dove, which makes sharing some
>>    early code like earlyprintk complicated, while our goal is
>>    ultimately to merge all Marvell EBU platforms into mach-mvebu.
>>
>> (1) is really the primary motivation here, (2) is only a nice
>> side-effect.
>>
>> So, the new generation of bootloaders that are shipped on new Marvell
>> Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
>> starting Linux. The current kernel cannot boot on such platforms.
> 
> Does it boot if you disable the DEBUG_LL code and apply your
> patches 1-8? The reason I'm asking is that you already cannot have
> DEBUG_LL on a multiplatform kernel targeted at systems which don't
> use the same UART. Adding a further restriction that they must map
> the internal registers to the same physical address does not change
> this a lot.

Thomas will confirm, but I am pretty sure he also made test without
DEBUG_LL

> 
>> Therefore, the last patch of this series adds some early code in the
>> kernel, at the ->map_io() stage, to switch the internal registers from
>> 0xD0000000 to 0xF1000000 if this has not been done already by the
>> bootloader. As it was explained above, we unfortunately can't read the
>> current base address of the internal register window, so we need a
>> different mechanism to know if the bootloader has done the remapping
>> at 0xF1000000 (new generation bootloader) or has left the internal
>> registers at 0xD0000000 (old generation bootloader). In order to
>> distinguish between those two cases, a CP15 bit is being used. Old
>> bootloaders do not touch this CP15, so it is set to 0. New bootloaders
>> set this CP15 bit to 1, so that the kernel knows that the remapping
>> has already been done. The ->map_io() code looks at this bit to know
>> if the remapping should be done or not.
> 
> As you already admit, using the CP15 register is a hack. It sounds
> to me that a cleaner approach would be to put the correct address
> into the device tree and use that value everywhere, rather than
> hardcoding one or more addresses.

That means reading and decoding the device tree very early in the
auto-uncompress part of the kernel.

> 
>> Unfortunately, tweaking ->map_io() is not sufficient: we also want
>> earlyprintk to work. And earlyprintk is used *before* ->map_io() is
>> called, and *after* ->map_io() is called.
> 
> Note that by the time map_io is called, we no longer care about
> the physical address, since the uart is only accessed through the
> virtual mapping after __enable_mmu.
> 
> 	Arnd
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From catalin.marinas at arm.com  Wed May 22 10:42:41 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 May 2013 15:42:41 +0100
Subject: [RFC PATCH] ARM: mm: lazy cache flushing on non-mapped pages
In-Reply-To: <1369223711-2995-1-git-send-email-ming.lei@canonical.com>
References: <1369223711-2995-1-git-send-email-ming.lei@canonical.com>
Message-ID: <20130522144240.GA4173@localhost.cambridge.arm.com>

On Wed, May 22, 2013 at 12:55:11PM +0100, Ming Lei wrote:
> Currently flush_dcache_page() thinks pages as non-mapped if
> mapping_mapped(mapping) return false. This approach is very
> coase:
> 	- mmap on part of file may cause all pages backed on
> 	the file being thought as mmaped
> 
> 	- file-backed pages aren't mapped into user space actually
> 	if the memory mmaped on the file isn't accessed

That's the meaning of mapping_mapped(), it doesn't tell whether the page
has a user virtual address.

> This patch also uses page_mapcount() to decide if the page has been
> mapped.

Better use page_mapped() instead.

-- 
Catalin


From mst at redhat.com  Wed May 22 10:44:06 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 17:44:06 +0300
Subject: [PATCH v2 00/10] uaccess: better might_sleep/might_fault behavior
In-Reply-To: <201305221604.49185.arnd@arndb.de>
References: <cover.1368702323.git.mst@redhat.com>
 <201305221125.36284.arnd@arndb.de>
 <20130522134124.GD18614@n2100.arm.linux.org.uk>
 <201305221604.49185.arnd@arndb.de>
Message-ID: <20130522144406.GB21886@redhat.com>

On Wed, May 22, 2013 at 04:04:48PM +0200, Arnd Bergmann wrote:
> On Wednesday 22 May 2013, Russell King - ARM Linux wrote:
> > On Wed, May 22, 2013 at 11:25:36AM +0200, Arnd Bergmann wrote:
> > > Given the most commonly used functions and a couple of architectures
> > > I'm familiar with, these are the ones that currently call might_fault()
> > > 
> > >                       x86-32  x86-64  arm     arm64   powerpc s390    generic
> > > copy_to_user          -       x       -       -       -       x       x
> > > copy_from_user        -       x       -       -       -       x       x
> > > put_user              x       x       x       x       x       x       x
> > > get_user              x       x       x       x       x       x       x
> > > __copy_to_user        x       x       -       -       x       -       -
> > > __copy_from_user      x       x       -       -       x       -       -
> > > __put_user            -       -       x       -       x       -       -
> > > __get_user            -       -       x       -       x       -       -
> > > 
> > > WTF?
> > 
> > I think your table is rather screwed - especially on ARM.  Tell me -
> > how can __copy_to_user() use might_fault() but copy_to_user() not when
> > copy_to_user() is implemented using __copy_to_user() ?  Same for
> > copy_from_user() but the reverse argument - there's nothing special
> > in our copy_from_user() which would make it do might_fault() when
> > __copy_from_user() wouldn't.
> 
> I think something went wrong with formatting of the tabstobs in
> the table. I've tried to correct it above to the same version I
> see on the mailing list.
> 
> > The correct position for ARM is: our (__)?(pu|ge)t_user all use
> > might_fault(), but (__)?copy_(to|from)_user do not.  Neither does
> > (__)?clear_user.  We might want to fix those to use might_fault().
> 
> Yes, that sounds like a good idea, especially since they are all
> implemented out-of-line.
> 
> For __get_user()/__put_user(), I would probably do the reverse and make
> them not call might_fault() though, like we do on most other architectures:
> 
> Look at the object code produced for setup_sigframe for instance, it calls
> might_fault() around 25 times where one should really be enough.

Well it depends on what config options you set.
But with VOLUNTARY you are right.
Also, look at memcpy_fromiovec and weep.

> Using
> __put_user() instead of put_user() is normally an indication that the
> author of that function has made performance considerations and move the
> (trivial) access_ok() call out, but now we add a more expensive
> call instead.
> 
> 	Arnd

I think exactly the same rules should apply to __XXX_user and
__copy_XXX_user - otherwise it's really confusing.

Maybe a preempt point in might_fault should go away?
Basically

#define might_fault() __might_sleep(__FILE__, __LINE__, 0)

Possibly adding the in_atomic() etc checks that Peter suggested.

Ingo, what do you think? And what testing would be appropriate
for such a change?


Thanks,

-- 
MST


From horms+renesas at verge.net.au  Wed May 22 10:48:09 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Wed, 22 May 2013 23:48:09 +0900
Subject: [PATCH v3] ARM: shmobile: sh73a0: Update CMT clockevent rating to 80
Message-ID: <1369234089-736-1-git-send-email-horms+renesas@verge.net.au>

Update the CMT clockevent rating from 125 to 80.

This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
Avoid dummy clockevent being preferred over real").

The patch noted above reduces the rating of dummy clockevent from 400 to 100.
This patch reduces the rating of CMT so that it is once again less than that
of the dummy clockevent.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

I also plan to reduce the rating of the STI clockevent to less than 100.
However, as I am not aware of any problems relating to STI in v3.10-rc
my plan is to update STI in the v3.11 timeframe.

v3
* s/kzm9g-reference/sh73a0/ in subject, as suggested by Sergei Shtylyov

v2
* Fix typos pointed out by Sergei Shtylyov

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..9696f36 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
 	.name = "CMT10",
 	.channel_offset = 0x10,
 	.timer_bit = 0,
-	.clockevent_rating = 125,
+	.clockevent_rating = 80,
 	.clocksource_rating = 125,
 };
 
-- 
1.8.2.1



From lee.jones at linaro.org  Wed May 22 10:49:57 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 15:49:57 +0100
Subject: [PATCH v2] ARM: ux500: Apply other compatible name to the u8540 DTS
 file
In-Reply-To: <1369233402-19225-1-git-send-email-lee.jones@linaro.org>
References: <1369233402-19225-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20130522144957.GA18714@gmail.com>

ARM: ux500: Apply other compatible name to the u8540 DTS file
    
Devices in board DTS files are usually searchable by multiple
compatible strings. In this case the 8540 based SoC should be
obtainable via the chipset [DB8540 & AB8540] name 'u8540' or
the board name 'ccu8540'. It's already possible to obtain the
Device Tree via its chipset name, this patch makes it possible
to get it by its board name too.
    
Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
index 18daa01..af4487f 100644
--- a/arch/arm/boot/dts/ccu8540.dts
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -14,7 +14,7 @@
 
 / {
 	model = "ST-Ericsson U8540 platform with Device Tree";
-	compatible = "st-ericsson,u8540";
+	compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
 
 	memory {
 		reg = <0x00000000 0x20000000>;


From bhelgaas at google.com  Wed May 22 10:49:41 2013
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 22 May 2013 08:49:41 -0600
Subject: [PATCH 4/4] pci: mvebu: fix the emulation of the status register
In-Reply-To: <1369228358-32580-5-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369228358-32580-5-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <CAErSpo5LAOFtWUQpDk4OdfrCPr4gAnp_+nkmZcOib0531Who-A@mail.gmail.com>

On Wed, May 22, 2013 at 7:12 AM, Thomas Petazzoni
<thomas.petazzoni at free-electrons.com> wrote:
> In a PCI configuration header, the 'devsel' bits of the status
> register are read-only, and indicate the timing of the secondary
> interface. Currently, we implement them as read/write, so when the
> Linux PCI core writes all 1's to this register, it gets 11b as the
> 'devsel' value, which is reserved.

I suppose the problem is that pci_scan_bridge() writes 0xffff to the
PCI_STATUS register?

PCI_STATUS is documented as containing either RO or RW1C
(write-1-to-clear status) bits, so it makes sense to write all ones to
clear all status bits.  But there are other RO bits that I think you
should mask out, too: Interrupt Status, Capabilities List, etc.

Maybe if you fix this, it will also fix the Capability List issue you
saw in patch 3/4.

> This commit fixes the PCI-to-PCI bridge emulation of the Marvell PCIe
> driver to ensure those bits remain set to 00b, which indicate a fast
> devsel decoding.
>
> This allows to fix the lspci -v output from:
>
>   Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0
>
> to:
>
>   Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  drivers/pci/host/pci-mvebu.c |    5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> index c887598..d730bf4 100644
> --- a/drivers/pci/host/pci-mvebu.c
> +++ b/drivers/pci/host/pci-mvebu.c
> @@ -490,6 +490,11 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
>         case PCI_COMMAND:
>                 bridge->command = value & 0xffff;
>                 bridge->status = value >> 16;
> +               /*
> +                * The devsel bits are read-only, and we want to keep
> +                * them set to 0
> +                */
> +               bridge->status &= ~PCI_STATUS_DEVSEL_MASK;
>                 break;
>
>         case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From thomas.petazzoni at free-electrons.com  Wed May 22 10:55:29 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 16:55:29 +0200
Subject: [PATCH 3/4] pci: mvebu: emulate an empty capability list
In-Reply-To: <CAErSpo6gFf9ou-VtZ=F0+1GqcSoPS_dDMGphhgv=8mD602=BRA@mail.gmail.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369228358-32580-4-git-send-email-thomas.petazzoni@free-electrons.com>
 <CAErSpo6gFf9ou-VtZ=F0+1GqcSoPS_dDMGphhgv=8mD602=BRA@mail.gmail.com>
Message-ID: <20130522165529.64174e06@skate>

Dear Bjorn Helgaas,

On Wed, 22 May 2013 08:39:03 -0600, Bjorn Helgaas wrote:

> > emulation to emulate an empty capability list. It might be later
> > extended to expose things like the PCI Express Capability header, but
> > an empty capability list is sufficient for now.
> >
> > lspci -v now shows the much nicer:
> >
> >   Capabilities: [40] #00 [0000]
> 
> It'd be even better if you could make the Capabilities List bit in the
> Device Status register be zero.  Then lspci wouldn't even try to read
> the Capabilities Pointer at 0x34, and you wouldn't have to deal with
> reads of 0x40.

The Device Status register is emulated with an initial value of zero.
Then, whenever the Linux PCI core writes into it, those writes are
preserved. So to me, it looks like the Linux PCI core might be setting
this Capabilities List bit, and later re-reads it and finds it to be
set to 1.

Should this bit be emulated as a read-only bit (it's not made explicit
for this particular bit in the PCI-to-PCI bridge specification that I
have in front of me) ? Or even the entire Device Status register ?

Thanks for your comments!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From thomas.petazzoni at free-electrons.com  Wed May 22 11:06:43 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 17:06:43 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305221633.46705.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de>
Message-ID: <20130522170643.54a2b9d2@skate>

Dear Arnd Bergmann,

On Wed, 22 May 2013 16:33:46 +0200, Arnd Bergmann wrote:

> >  1 The internal registers window sits at 3 GB, in the middle of the
> >    0-4 GB area of physical memory, which is quite annoying when you
> >    have more than 3 GB of memory. Having them at 0xF1000000 means that
> >    you lose less RAM when you have more than 3 GB of physical memory
> >    installed. And since Armada XP is LPAE capable, you can even have
> >    more than 4 GB memory: we already have boards with 8 GB of memory
> >    installed.
> 
> Just for completeness:
> 
> Do any of the machines that use the old boot loader have more
> than 3 GB of memory?

As Gregory said: yes. The Armada XP GP board has 8 GB of RAM. And the
OpenBlocks has 1 GB soldered, and an expansion slot in which you can
add more RAM, possibly over 3 GB.

> >  2 This is different from Kirkwood and Dove, which makes sharing some
> >    early code like earlyprintk complicated, while our goal is
> >    ultimately to merge all Marvell EBU platforms into mach-mvebu.
> > 
> > (1) is really the primary motivation here, (2) is only a nice
> > side-effect.
> > 
> > So, the new generation of bootloaders that are shipped on new Marvell
> > Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
> > starting Linux. The current kernel cannot boot on such platforms.
> 
> Does it boot if you disable the DEBUG_LL code and apply your
> patches 1-8?

Patches 1-8 do not change anything in terms of the internal register
window base address. So just like the kernel was working with and
without DEBUG_LL before patches 1-8, it continues to work after those
cleanups/improvements.

> The reason I'm asking is that you already cannot have
> DEBUG_LL on a multiplatform kernel targeted at systems which don't
> use the same UART. Adding a further restriction that they must map
> the internal registers to the same physical address does not change
> this a lot.

I'm sorry, but I don't follow you here. When you have patches 1-8 (or
no patch applied at all), the UART for mach-mvebu is *always* at
0xd0012000.

> > Therefore, the last patch of this series adds some early code in the
> > kernel, at the ->map_io() stage, to switch the internal registers from
> > 0xD0000000 to 0xF1000000 if this has not been done already by the
> > bootloader. As it was explained above, we unfortunately can't read the
> > current base address of the internal register window, so we need a
> > different mechanism to know if the bootloader has done the remapping
> > at 0xF1000000 (new generation bootloader) or has left the internal
> > registers at 0xD0000000 (old generation bootloader). In order to
> > distinguish between those two cases, a CP15 bit is being used. Old
> > bootloaders do not touch this CP15, so it is set to 0. New bootloaders
> > set this CP15 bit to 1, so that the kernel knows that the remapping
> > has already been done. The ->map_io() code looks at this bit to know
> > if the remapping should be done or not.
> 
> As you already admit, using the CP15 register is a hack. It sounds
> to me that a cleaner approach would be to put the correct address
> into the device tree and use that value everywhere, rather than
> hardcoding one or more addresses.

I don't see how this can fix the problem. Which internal register base
address do we put in our Device Tree source in arch/arm/boot/dts? The
old one? The new one?

Again, I'd like people to carefully read and read once again the cover
letter and commit log before jumping into the conclusion that 'CP15 is
a hack', and come up with a solution that seriously takes into account
all the problems that are highlighted in the cover letter and commit
log. "Putting the correct address into the device tree and use that
value everywhere" simply doesn't work for earlyprintk, for example.

I'm afraid that the only alternative to the proposed solution is to
unconditionally assume that the switch to the 0xf1000000 base address
has been made by the bootloader. This will work for all new Marvell
platforms, but will break all existing users of Mirabox and OpenBlocks
platform.

> > Unfortunately, tweaking ->map_io() is not sufficient: we also want
> > earlyprintk to work. And earlyprintk is used *before* ->map_io() is
> > called, and *after* ->map_io() is called.
> 
> Note that by the time map_io is called, we no longer care about
> the physical address, since the uart is only accessed through the
> virtual mapping after __enable_mmu.

That's not correct. ->map_io() calls debug_ll_io_init(), which calls
the addruart code of earlyprintk, from which it gets the virtual
address *AND* physical address of the UART, and sets up a mapping with
create_mapping(). See the implementation of debug_ll_io_init().

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Wed May 22 11:09:46 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 22 May 2013 17:09:46 +0200
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <20130522134319.GC31290@titan.lakedaemon.net>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522134319.GC31290@titan.lakedaemon.net>
Message-ID: <519CDFBA.8010607@free-electrons.com>

On 05/22/2013 03:43 PM, Jason Cooper wrote:
> Thomas,
> 
> On Wed, May 22, 2013 at 03:12:34PM +0200, Thomas Petazzoni wrote:
>> Bjorn, Jason, Andrew, Gregory,
>>
>> You'll find in this patch series 4 small patches that make various
>> improvements to the Marvell PCIe driver.
>>
>> I'd like those improvements to be kept separated from the original
>> PCIe driver itself: while the PCIe driver has been around and reviewed
>> for a long time, those improvements are newer. And I clearly do not
>> want the PCIe driver to miss 3.11 because of any problem that could be
>> found in those additional improvements.
> 
> Agreed.

All the changes are located in one single file drivers/pci/host/pci-mvebu.c.
So as soon as they will be acked by Bjron, I think we can make a PR for them.
As nothing else depend of it, even if for a reason or another it is dropped,
there will be no reason to drop anything else.

> 
> For Bjorn and others:
> 
> The original patch series Thomas is referring to missed the merge window
> for v3.10 due to a build failure.  It is currently sitting in our mvebu
> repo.  The first three patches, "of/pci ..." are in mvebu/of_pci.  The
> rest of the series is on top of that in the branch mvebu/pcie.
> 
> I've sent pull requests for both branches to arm-soc.  There are two
> other arm SoC pcie efforts which are depending on mvebu/of_pci.  Hence
> why I did a separate branch.
> 
> Both branches are also merged into mvebu/for-next, and have survived
> linux-next for three days or so.  But, it's early, so we'll see how it
> goes. :-)
> 
>> Bjorn, with your Acked-by, could the Marvell maintainers include those
>> patches in their branch, merged through arm-soc? They already have the
>> Marvell PCIe driver itself, so I believe it makes sense to merge those
>> improvements through the same path.
> 
> I agree, please see above regarding arm-soc dependencies.
> 
>> Jason, those patches have been prepared on top of my marvell-pcie-v10
>> branch, I hope that's ok for you. If you want me to rebase them on
>> some other branch in which you have integrated the PCIe driver, don't
>> hesitate to tell me to do so. That said, since those patches are only
>> touching the driver itself and no other file, they should not cause
>> any conflict with other changes.
> 
> Should be fine, I'll let you know.
> 
> thx,
> 
> Jason.
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jason at lakedaemon.net  Wed May 22 11:18:29 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 11:18:29 -0400
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <519CDFBA.8010607@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522134319.GC31290@titan.lakedaemon.net>
 <519CDFBA.8010607@free-electrons.com>
Message-ID: <20130522151829.GD31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 05:09:46PM +0200, Gregory CLEMENT wrote:
> On 05/22/2013 03:43 PM, Jason Cooper wrote:
> > Thomas,
> > 
> > On Wed, May 22, 2013 at 03:12:34PM +0200, Thomas Petazzoni wrote:
> >> Bjorn, Jason, Andrew, Gregory,
> >>
> >> You'll find in this patch series 4 small patches that make various
> >> improvements to the Marvell PCIe driver.
> >>
> >> I'd like those improvements to be kept separated from the original
> >> PCIe driver itself: while the PCIe driver has been around and reviewed
> >> for a long time, those improvements are newer. And I clearly do not
> >> want the PCIe driver to miss 3.11 because of any problem that could be
> >> found in those additional improvements.
> > 
> > Agreed.
> 
> All the changes are located in one single file drivers/pci/host/pci-mvebu.c.
> So as soon as they will be acked by Bjron, I think we can make a PR for them.
> As nothing else depend of it, even if for a reason or another it is dropped,
> there will be no reason to drop anything else.

Right, which is why we'll put it in a separate branch.  Say,
mvebu/pcie_bridge.  This way if /pcie_bridge has to be dropped (say an
API that it used is changed), /pcie would remain.  Which is the main
concern.

Had I known enough last time around, I would have done the /of_pci |
/pcie split.  /pcie would have been dropped, and /of_pci would have made
it in.  As well as LinusW's work which depends upon it (and now Arnd
might have something using it as well).

thx,

Jason.


From arnd at arndb.de  Wed May 22 11:18:53 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 17:18:53 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <519CD920.5030301@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <519CD920.5030301@free-electrons.com>
Message-ID: <201305221718.53759.arnd@arndb.de>

On Wednesday 22 May 2013, Gregory CLEMENT wrote:
> >> Therefore, the last patch of this series adds some early code in the
> >> kernel, at the ->map_io() stage, to switch the internal registers from
> >> 0xD0000000 to 0xF1000000 if this has not been done already by the
> >> bootloader. As it was explained above, we unfortunately can't read the
> >> current base address of the internal register window, so we need a
> >> different mechanism to know if the bootloader has done the remapping
> >> at 0xF1000000 (new generation bootloader) or has left the internal
> >> registers at 0xD0000000 (old generation bootloader). In order to
> >> distinguish between those two cases, a CP15 bit is being used. Old
> >> bootloaders do not touch this CP15, so it is set to 0. New bootloaders
> >> set this CP15 bit to 1, so that the kernel knows that the remapping
> >> has already been done. The ->map_io() code looks at this bit to know
> >> if the remapping should be done or not.
> > 
> > As you already admit, using the CP15 register is a hack. It sounds
> > to me that a cleaner approach would be to put the correct address
> > into the device tree and use that value everywhere, rather than
> > hardcoding one or more addresses.
> 
> That means reading and decoding the device tree very early in the
> auto-uncompress part of the kernel.

Why that? I was only implying that we would have no console output in
the uncompressor, which is already the case on multiplatform these
days when DEBUG_LL is disabled.

	Arnd


From swarren at wwwdotorg.org  Wed May 22 11:19:43 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 09:19:43 -0600
Subject: [v2 0/6] CLK: tegra: convert device tree files to use CLK defines
In-Reply-To: <20130522091248.b3acd9c56ab66535d75b8fd1@nvidia.com>
References: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com>
 <519B9B5D.4050402@wwwdotorg.org>
 <20130522091248.b3acd9c56ab66535d75b8fd1@nvidia.com>
Message-ID: <519CE20F.8020203@wwwdotorg.org>

On 05/22/2013 12:12 AM, Hiroshi Doyu wrote:
> On Tue, 21 May 2013 18:05:49 +0200
> Stephen Warren <swarren at wwwdotorg.org> wrote:
> 
>> On 05/21/2013 03:10 AM, Hiroshi Doyu wrote:
>>> This patchset converts device tree files to use CLK defines. This
>>> version was updated along with the latest DT changes.
>>>
>>> The following changes since commit 7479d8bb5650f43053d0e82fa44db668cf968f11:
>>>
>>>   TESTING: Build Tegra USB as a module (2013-05-20 13:11:19 -0600)
>>
>> That commit is in my personal work-in-progress branch. This series
>> should be based on Tegra's for-3.11/dt branch. This will make a
>> difference (at least) in patch 6/6, where you've edited some DT nodes
>> that don't yet exist upstream (i.e. Tegra's for-3.11/dt branch) and
>> hence this series won't apply there.
> 
> I'll rebase.
> 
>> I assume you're planning to send a series for 3.11 that converts
>> drivers/clk/tegra/ to use these new header files?
> 
> I think that I'll work on SMMU first, which diverted from the
> downstream now. So the above may come a bit later.

Really? SMMU support upstream is pretty low priority right now since we
don't use it yet, and only converting one of the two potential users of
this new binding header file means it isn't particularly useful.


From swarren at wwwdotorg.org  Wed May 22 11:20:04 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 09:20:04 -0600
Subject: [v2 0/6] CLK: tegra: convert device tree files to use CLK defines
In-Reply-To: <20130522.130730.1153046210420942555.hdoyu@nvidia.com>
References: <1369127450-15203-1-git-send-email-hdoyu@nvidia.com><519B9B5D.4050402@wwwdotorg.org><20130522091248.b3acd9c56ab66535d75b8fd1@nvidia.com>
 <20130522.130730.1153046210420942555.hdoyu@nvidia.com>
Message-ID: <519CE224.3010107@wwwdotorg.org>

On 05/22/2013 04:07 AM, Hiroshi Doyu wrote:
> Hiroshi Doyu <hdoyu at nvidia.com> wrote @ Wed, 22 May 2013 08:12:48 +0200:
> 
>> On Tue, 21 May 2013 18:05:49 +0200
>> Stephen Warren <swarren at wwwdotorg.org> wrote:
>>
>>> On 05/21/2013 03:10 AM, Hiroshi Doyu wrote:
>>>> This patchset converts device tree files to use CLK defines. This
>>>> version was updated along with the latest DT changes.
>>>>
>>>> The following changes since commit 7479d8bb5650f43053d0e82fa44db668cf968f11:
>>>>
>>>>   TESTING: Build Tegra USB as a module (2013-05-20 13:11:19 -0600)
>>>
>>> That commit is in my personal work-in-progress branch. This series
>>> should be based on Tegra's for-3.11/dt branch. This will make a
>>> difference (at least) in patch 6/6, where you've edited some DT nodes
>>> that don't yet exist upstream (i.e. Tegra's for-3.11/dt branch) and
>>> hence this series won't apply there.
>>
>> I'll rebase.
> 
> Rebased on Tegra's for-3.11/dt, including fix: [2/6] over 80 columns.
> 
> If you want me to send patches again, please let me know.

Yes, you should always send the patches for review on mailing lists.


From swarren at wwwdotorg.org  Wed May 22 11:22:31 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 09:22:31 -0600
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CD1CC.8070507@koalo.de>
References: <519CD1CC.8070507@koalo.de>
Message-ID: <519CE2B7.8080704@wwwdotorg.org>

On 05/22/2013 08:10 AM, Florian Meier wrote:
> This driver adds support for digital audio (I2S)
> for the BCM2708 SoC that is used by the
> Raspberry Pi. External audio codecs can be
> connected to the Raspberry Pi via P5 header.
> 
> It relies on cyclic DMA engine support for BCM2708
> that is not included in this patch.

This SoC is actually the BCM2835, so the files should be named for that.

Upstream only uses device tree for BCM2835. Does this driver support DT?
Where is the DT binding definition file?

I assume you're planning on sending the DMA driver upstream too? I guess
this driver isn't useful without it.

I'll take a look at the actual patch content later.


From swarren at wwwdotorg.org  Wed May 22 11:26:51 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 09:26:51 -0600
Subject: [PATCH 2/5] ARM: dts: OMAP2+: create a DT header for GPIO
In-Reply-To: <1369232864-14460-3-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-3-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <519CE3BB.3040704@wwwdotorg.org>

On 05/22/2013 08:27 AM, Florian Vaussard wrote:
> Define the OMAP_GPIO macro to conveniently use GPIO inside OMAP DT.
> For example:
> 
> 	gpios = <&gpio6 3 0>;  /* GPIO 163 */
> 
> can be replaced by
> 
> 	gpios = OMAP_GPIO(163, 0);

> diff --git a/include/dt-bindings/gpio/omap-gpio.h b/include/dt-bindings/gpio/omap-gpio.h

> +#define OMAP_GPIO_0_BANK        gpio1
> +#define OMAP_GPIO_1_BANK        gpio1
> +#define OMAP_GPIO_2_BANK        gpio1
> +#define OMAP_GPIO_3_BANK        gpio1

There are a /lot/ of those. Is this really worth it?

If the OMAP GPIO HW is already represented as a bunch of separate DT
nodes which represent separate GPIO blocks, then I would have thought
the syntax <&gpioN M 0> more directly represents what would be found in
the HW manual? If not, surely the DT should have a single node to
represent a single GPIO controller, which just happens to internally
support a bunch of register arrays.


From swarren at wwwdotorg.org  Wed May 22 11:28:51 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 09:28:51 -0600
Subject: [PATCH 3/5] ARM: dts: OMAP2+: convert DT files to use the new
 OMAP_GPIO macro
In-Reply-To: <1369232864-14460-4-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-4-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <519CE433.10903@wwwdotorg.org>

On 05/22/2013 08:27 AM, Florian Vaussard wrote:
> Use OMAP_GPIO(), in conjunction with standard GPIO flags, to enhance the
> readability of DT GPIOs.

> diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
> index e0ce823..e773a5e 100644
> --- a/arch/arm/boot/dts/omap3-beagle-xm.dts
> +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
> @@ -29,13 +29,13 @@
>  
>  		heartbeat {
>  			label = "beagleboard::usr0";
> -			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
> +			gpios = OMAP_GPIO(150, GPIO_ACTIVE_HIGH); /* 150 -> D6 LED */

One of the advantages of cpp support for me is the ability to remove the
redundant part of the command. In other words, perhaps remove the "150
->" since that information is part of the OMAP_GPIO() "call", leaving
just /* D6 LED */. I might have expected "D6" to be the label too, thus
removing any need for the comment.


From tony at atomide.com  Wed May 22 11:34:52 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 22 May 2013 08:34:52 -0700
Subject: [PATCH 2/5] ARM: dts: OMAP2+: create a DT header for GPIO
In-Reply-To: <519CE3BB.3040704@wwwdotorg.org>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-3-git-send-email-florian.vaussard@epfl.ch>
 <519CE3BB.3040704@wwwdotorg.org>
Message-ID: <20130522153452.GZ10378@atomide.com>

* Stephen Warren <swarren at wwwdotorg.org> [130522 08:32]:
> On 05/22/2013 08:27 AM, Florian Vaussard wrote:
> > Define the OMAP_GPIO macro to conveniently use GPIO inside OMAP DT.
> > For example:
> > 
> > 	gpios = <&gpio6 3 0>;  /* GPIO 163 */
> > 
> > can be replaced by
> > 
> > 	gpios = OMAP_GPIO(163, 0);
> 
> > diff --git a/include/dt-bindings/gpio/omap-gpio.h b/include/dt-bindings/gpio/omap-gpio.h
> 
> > +#define OMAP_GPIO_0_BANK        gpio1
> > +#define OMAP_GPIO_1_BANK        gpio1
> > +#define OMAP_GPIO_2_BANK        gpio1
> > +#define OMAP_GPIO_3_BANK        gpio1
> 
> There are a /lot/ of those. Is this really worth it?
> 
> If the OMAP GPIO HW is already represented as a bunch of separate DT
> nodes which represent separate GPIO blocks, then I would have thought
> the syntax <&gpioN M 0> more directly represents what would be found in
> the HW manual? If not, surely the DT should have a single node to
> represent a single GPIO controller, which just happens to internally
> support a bunch of register arrays.

Yes I agree, let's not go back to numbering anything except within the
a single instance. If anything, we can put the gpio number into comments.

Regards,

Tony


From tony at atomide.com  Wed May 22 11:35:53 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 22 May 2013 08:35:53 -0700
Subject: [PATCH 4/5] ARM: dts: OMAP3: fix incorrect notation for
 musb-hdrc interrupt
In-Reply-To: <1369232864-14460-5-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-5-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <20130522153552.GA10378@atomide.com>

* Florian Vaussard <florian.vaussard at epfl.ch> [130522 07:33]:
> On OMAP3, the INTC interrupt controller has only 1 cell.
> 
> Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>

Thanks a similar fix is already queued up and on it's way to mainline
tree.

Regards,

Tony

> ---
>  arch/arm/boot/dts/omap3.dtsi |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index 15049b8..0f3be20 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -518,7 +518,7 @@
>  		usb_otg_hs: usb_otg_hs at 480ab000 {
>  			compatible = "ti,omap3-musb";
>  			reg = <0x480ab000 0x1000>;
> -			interrupts = <0 92 0x4>, <0 93 0x4>;
> +			interrupts = <92>, <93>;
>  			interrupt-names = "mc", "dma";
>  			ti,hwmods = "usb_otg_hs";
>  			multipoint = <1>;
> -- 
> 1.7.5.4
> 


From arnd at arndb.de  Wed May 22 11:35:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 17:35:11 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522170643.54a2b9d2@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
Message-ID: <201305221735.11815.arnd@arndb.de>

On Wednesday 22 May 2013, Thomas Petazzoni wrote:
> On Wed, 22 May 2013 16:33:46 +0200, Arnd Bergmann wrote:
> > >  1 The internal registers window sits at 3 GB, in the middle of the
> > >    0-4 GB area of physical memory, which is quite annoying when you
> > >    have more than 3 GB of memory. Having them at 0xF1000000 means that
> > >    you lose less RAM when you have more than 3 GB of physical memory
> > >    installed. And since Armada XP is LPAE capable, you can even have
> > >    more than 4 GB memory: we already have boards with 8 GB of memory
> > >    installed.
> > 
> > Just for completeness:
> > 
> > Do any of the machines that use the old boot loader have more
> > than 3 GB of memory?
> 
> As Gregory said: yes. The Armada XP GP board has 8 GB of RAM. And the
> OpenBlocks has 1 GB soldered, and an expansion slot in which you can
> add more RAM, possibly over 3 GB.

Ok, but going back to the discussion about remapping physical memory
addresses, would you actually be able to map more of the available
RAM when the registers are moved out of the way?

IIRC the translation is rather coarse-grained, and the new location
is still in the same 1GB window from 0xc0000000-0xffffffff.

> > > So, the new generation of bootloaders that are shipped on new Marvell
> > > Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
> > > starting Linux. The current kernel cannot boot on such platforms.
> > 
> > Does it boot if you disable the DEBUG_LL code and apply your
> > patches 1-8?
> 
> Patches 1-8 do not change anything in terms of the internal register
> window base address. So just like the kernel was working with and
> without DEBUG_LL before patches 1-8, it continues to work after those
> cleanups/improvements.

I mean with the new boot loader which breaks unmodified kernels.

> > The reason I'm asking is that you already cannot have
> > DEBUG_LL on a multiplatform kernel targeted at systems which don't
> > use the same UART. Adding a further restriction that they must map
> > the internal registers to the same physical address does not change
> > this a lot.
> 
> I'm sorry, but I don't follow you here. When you have patches 1-8 (or
> no patch applied at all), the UART for mach-mvebu is *always* at
> 0xd0012000.

No. UART0 is always at 0xd0012000 but there are also UARTs at 0xd0012100,
0xd0012200 and 0xd0012300. You don't currently support using them for
early output, but you might need to add that, similar to how other
SoC platforms handle this.

More importantly, you can build a kernel with any number of other SoCs
already, and if you have a combined ArmadaXP+OMAP+Highbank kernel,
there is no way to get a working early debug output.

> > > Therefore, the last patch of this series adds some early code in the
> > > kernel, at the ->map_io() stage, to switch the internal registers from
> > > 0xD0000000 to 0xF1000000 if this has not been done already by the
> > > bootloader. As it was explained above, we unfortunately can't read the
> > > current base address of the internal register window, so we need a
> > > different mechanism to know if the bootloader has done the remapping
> > > at 0xF1000000 (new generation bootloader) or has left the internal
> > > registers at 0xD0000000 (old generation bootloader). In order to
> > > distinguish between those two cases, a CP15 bit is being used. Old
> > > bootloaders do not touch this CP15, so it is set to 0. New bootloaders
> > > set this CP15 bit to 1, so that the kernel knows that the remapping
> > > has already been done. The ->map_io() code looks at this bit to know
> > > if the remapping should be done or not.
> > 
> > As you already admit, using the CP15 register is a hack. It sounds
> > to me that a cleaner approach would be to put the correct address
> > into the device tree and use that value everywhere, rather than
> > hardcoding one or more addresses.
> 
> I don't see how this can fix the problem. Which internal register base
> address do we put in our Device Tree source in arch/arm/boot/dts? The
> old one? The new one?

The one matching the boot loader for that board, i.e. the new address
for all boards but Mirabox and OpenBlocks.

> > > Unfortunately, tweaking ->map_io() is not sufficient: we also want
> > > earlyprintk to work. And earlyprintk is used *before* ->map_io() is
> > > called, and *after* ->map_io() is called.
> > 
> > Note that by the time map_io is called, we no longer care about
> > the physical address, since the uart is only accessed through the
> > virtual mapping after __enable_mmu.
> 
> That's not correct. ->map_io() calls debug_ll_io_init(), which calls
> the addruart code of earlyprintk, from which it gets the virtual
> address *AND* physical address of the UART, and sets up a mapping with
> create_mapping(). See the implementation of debug_ll_io_init().

Ah right, but that is also something that could easily be changed.

	Arnd


From gregory.clement at free-electrons.com  Wed May 22 11:37:53 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 22 May 2013 17:37:53 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305221718.53759.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <519CD920.5030301@free-electrons.com>
 <201305221718.53759.arnd@arndb.de>
Message-ID: <519CE651.6070209@free-electrons.com>

On 05/22/2013 05:18 PM, Arnd Bergmann wrote:
> On Wednesday 22 May 2013, Gregory CLEMENT wrote:
>>>> Therefore, the last patch of this series adds some early code in the
>>>> kernel, at the ->map_io() stage, to switch the internal registers from
>>>> 0xD0000000 to 0xF1000000 if this has not been done already by the
>>>> bootloader. As it was explained above, we unfortunately can't read the
>>>> current base address of the internal register window, so we need a
>>>> different mechanism to know if the bootloader has done the remapping
>>>> at 0xF1000000 (new generation bootloader) or has left the internal
>>>> registers at 0xD0000000 (old generation bootloader). In order to
>>>> distinguish between those two cases, a CP15 bit is being used. Old
>>>> bootloaders do not touch this CP15, so it is set to 0. New bootloaders
>>>> set this CP15 bit to 1, so that the kernel knows that the remapping
>>>> has already been done. The ->map_io() code looks at this bit to know
>>>> if the remapping should be done or not.
>>>
>>> As you already admit, using the CP15 register is a hack. It sounds
>>> to me that a cleaner approach would be to put the correct address
>>> into the device tree and use that value everywhere, rather than
>>> hardcoding one or more addresses.
>>
>> That means reading and decoding the device tree very early in the
>> auto-uncompress part of the kernel.
> 
> Why that? I was only implying that we would have no console output in
> the uncompressor, which is already the case on multiplatform these
> days when DEBUG_LL is disabled.

Loosing the earlyprintk would be a big regression. Having DEBUG_LL disabled
in multiplatform case is fine. If the kernel seems to not run at all we
can still build a kernel for only for mvebu, activate earlyprintk and see
what happened. With your proposal we won't have any more this feature, and
it will make the debug or the bug report for the user much harder. As we still
in active development I really want to avoid it.

> 
> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From tony at atomide.com  Wed May 22 11:40:06 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 22 May 2013 08:40:06 -0700
Subject: [PATCH 1/5] ARM: dts: OMAP2+: use #include for all device trees
In-Reply-To: <1369232864-14460-2-git-send-email-florian.vaussard@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-2-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <20130522154006.GB10378@atomide.com>

* Florian Vaussard <florian.vaussard at epfl.ch> [130522 07:33]:
> Replace /include/ by #include for OMAP2+ DT, in order to use the
> C pre-processor, making use of #define features possible.

This is good, but let's use it with case. Probably the best use
for this right now is to add defines for the mux modes from
mach-omap2/mux.h as that makes the raw values readable without
comments.

Regards,

Tony


From arnd at arndb.de  Wed May 22 11:43:47 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 17:43:47 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <519CE651.6070209@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221718.53759.arnd@arndb.de> <519CE651.6070209@free-electrons.com>
Message-ID: <201305221743.47679.arnd@arndb.de>

On Wednesday 22 May 2013, Gregory CLEMENT wrote:
> Loosing the earlyprintk would be a big regression. Having DEBUG_LL disabled
> in multiplatform case is fine.

EARLY_PRINTK depends on DEBUG_LL, so that makes no sense.

> If the kernel seems to not run at all we
> can still build a kernel for only for mvebu, activate earlyprintk and see
> what happened. With your proposal we won't have any more this feature, and
> it will make the debug or the bug report for the user much harder. As we still
> in active development I really want to avoid it.

I don't understand. You should still be able to turn on DEBUG_LL when you need
it. It will just work only on the machines it is configured for, as it always
does. You will need a separate Kconfig option for each physical address though,
but that is also nothing new.

	Arnd


From morten.rasmussen at arm.com  Wed May 22 11:46:39 2013
From: morten.rasmussen at arm.com (Morten Rasmussen)
Date: Wed, 22 May 2013 16:46:39 +0100
Subject: [PATCH 13/14] sched: update the cpu_power
In-Reply-To: <1366910611-20048-14-git-send-email-vincent.guittot@linaro.org>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <1366910611-20048-14-git-send-email-vincent.guittot@linaro.org>
Message-ID: <20130522154639.GA4935@e103034-lin>

On Thu, Apr 25, 2013 at 06:23:29PM +0100, Vincent Guittot wrote:
> @@ -4596,8 +4597,12 @@ static void update_cpu_power(struct sched_domain *sd, int cpu)
>  	cpu_rq(cpu)->cpu_available = power;
>  	sdg->sgp->power_available = power;
>  
> +	if (!is_my_buddy(cpu, cpu))
> +		power = 1;
> +

Using your fix for is_my_buddy() for patch 11 the above will always be
true when sched_packing_mode is to anything else than
SCHED_PACKING_FULL. So cpu_power for all cpus in
SCHED_PACKING_{DEFAULT,NONE} is 1.

As far is I understand, this is not the intention?

Cheers,
Morten

>  	cpu_rq(cpu)->cpu_power = power;
>  	sdg->sgp->power = power;
> +
>  }
>  
>  void update_group_power(struct sched_domain *sd, int cpu)
> -- 
> 1.7.9.5
> 
> 



From andrew at lunn.ch  Wed May 22 11:51:34 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 17:51:34 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305221735.11815.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de>
Message-ID: <20130522155134.GL2824@lunn.ch>

> > I don't see how this can fix the problem. Which internal register base
> > address do we put in our Device Tree source in arch/arm/boot/dts? The
> > old one? The new one?
> 
> The one matching the boot loader for that board, i.e. the new address
> for all boards but Mirabox and OpenBlocks.

Hi Thomas

Maybe i'm missunderstand Arnd, but i think he is suggesting a property
somewhere in DT which says where the bootloader left the register
space before jumping to the kernel. You can then look at this property
and then decide if you need to remap or not. Only this one property
needs to differ between old and new bootloader. You could even say, if
the property is not in DT, a remap is needed.

However, i don't know if this can actually work. How early can you
parse the DT in order to know where the serial port is for
earlyprintk()? It also gets messy keeping track of the two different
DT binary blobs and somehow having the probe the uboot version in
order to install the right one. I don't know how i would include this
into the debian flash-kernel for example.

I prefer the CP15 bit.

	Andrew


From maxime.ripard at free-electrons.com  Wed May 22 11:52:23 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 22 May 2013 17:52:23 +0200
Subject: [PATCH v4 4/5] clk: add CLK_SET_RATE_NO_REPARENT flag
In-Reply-To: <1369056507-32521-5-git-send-email-james.hogan@imgtec.com>
References: <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
 <1369056507-32521-5-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130522155223.GC8595@lukather>

Hi James,

On Mon, May 20, 2013 at 02:28:26PM +0100, James Hogan wrote:
> Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
> being reparented during clk_set_rate.
> 
> To avoid breaking existing platforms, all callers of clk_register_mux()
> are adjusted to pass the new flag. Platform maintainers are encouraged
> to remove the flag if they wish to allow mux reparenting on set_rate.

For the sunxi part,
Acked-by: Maxime Ripard <maxime.ripard at free-electrons.com>

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From gregory.clement at free-electrons.com  Wed May 22 11:56:31 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 22 May 2013 17:56:31 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305221743.47679.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221718.53759.arnd@arndb.de> <519CE651.6070209@free-electrons.com>
 <201305221743.47679.arnd@arndb.de>
Message-ID: <519CEAAF.2050600@free-electrons.com>

On 05/22/2013 05:43 PM, Arnd Bergmann wrote:
> On Wednesday 22 May 2013, Gregory CLEMENT wrote:
>> Loosing the earlyprintk would be a big regression. Having DEBUG_LL disabled
>> in multiplatform case is fine.
> 
> EARLY_PRINTK depends on DEBUG_LL, so that makes no sense.
> 
>> If the kernel seems to not run at all we
>> can still build a kernel for only for mvebu, activate earlyprintk and see
>> what happened. With your proposal we won't have any more this feature, and
>> it will make the debug or the bug report for the user much harder. As we still
>> in active development I really want to avoid it.
> 
> I don't understand. You should still be able to turn on DEBUG_LL when you need
> it. It will just work only on the machines it is configured for, as it always
> does. You will need a separate Kconfig option for each physical address though,
> but that is also nothing new.

But you proposed to use device tree instead of CP15. In this case we won't be
able to use earlyprintk that was my point. You justified the fact to not use
earlyprintk because we can't use it for multiplatform. So I am fine to not being
able to use earlyprintk in multiplatform, but it sill important to be able to
continue to use in non multiplatform case, hence the need of the use of CP15
bit.



> 
> 	Arnd
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From morten.rasmussen at arm.com  Wed May 22 11:56:58 2013
From: morten.rasmussen at arm.com (Morten Rasmussen)
Date: Wed, 22 May 2013 16:56:58 +0100
Subject: [PATCH 11/14] sched: filter task pull request
In-Reply-To: <CAKfTPtCUvKmTHzyVRCkGyM-nWOSWP8OUzMgyCyzPEXf1NoxsQQ@mail.gmail.com>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <1366910611-20048-12-git-send-email-vincent.guittot@linaro.org>
 <CAKfTPtCUvKmTHzyVRCkGyM-nWOSWP8OUzMgyCyzPEXf1NoxsQQ@mail.gmail.com>
Message-ID: <20130522155658.GB4935@e103034-lin>

On Fri, Apr 26, 2013 at 11:00:58AM +0100, Vincent Guittot wrote:
> Part of this patch is missing, the fix below is needed
> 
> @@ -3497,7 +3497,9 @@ static bool is_buddy_full(int cpu)
>  static bool is_my_buddy(int cpu, int buddy)
>  {
>   int my_buddy = per_cpu(sd_pack_buddy, cpu);
> - return (my_buddy == -1) || (buddy == my_buddy);
> +
> + return ((sysctl_sched_packing_mode == SCHED_PACKING_FULL) &&
> +               ((my_buddy == -1) || (buddy == my_buddy)));
>  }
> 
>  static bool is_light_task(struct task_struct *p)
> 
> 
> On 25 April 2013 19:23, Vincent Guittot <vincent.guittot at linaro.org> wrote:
> > Only CPUs that participates to the packing effort can pull tasks on a busiest
> > group.
> >
> > Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
> > ---
> >  kernel/sched/fair.c |   14 ++++++++++++--
> >  1 file changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> > index 28f8ea7..6f63fb9 100644
> > --- a/kernel/sched/fair.c
> > +++ b/kernel/sched/fair.c
> > @@ -3494,6 +3494,12 @@ static bool is_buddy_full(int cpu)
> >         return (sum * 1024 >= period * 1000);
> >  }
> >
> > +static bool is_my_buddy(int cpu, int buddy)
> > +{
> > +       int my_buddy = per_cpu(sd_pack_buddy, cpu);
> > +       return (my_buddy == -1) || (buddy == my_buddy);
> > +}

Would it make sense to change the function name to something like
is_packing_target() and only have one argument?

is_my_buddy() is only used with the same variable for both arguments
like below.

> > +
> >  static bool is_light_task(struct task_struct *p)
> >  {
> >         /* A light task runs less than 20% in average */
> > @@ -4688,8 +4694,8 @@ static inline void update_sg_lb_stats(struct lb_env *env,
> >
> >                 /* Bias balancing toward cpus of our domain */
> >                 if (local_group) {
> > -                       if (idle_cpu(i) && !first_idle_cpu &&
> > -                                       cpumask_test_cpu(i, sched_group_mask(group))) {
> > +                       if (is_my_buddy(i, i) && idle_cpu(i) && !first_idle_cpu
> > +                        && cpumask_test_cpu(i, sched_group_mask(group))) {
> >                                 first_idle_cpu = 1;
> >                                 balance_cpu = i;
> >                         }
> > @@ -4817,6 +4823,10 @@ static void update_plb_buddy(int cpu, int *balance, struct sd_lb_stats *sds,
> >
> >         /* Get my new buddy */
> >         buddy = per_cpu(sd_pack_buddy, cpu);
> > +
> > +       /* This CPU doesn't act for agressive packing */
> > +       if (buddy != cpu)
> > +               sds->busiest = 0;

sds->busiest is a pointer, so I think it should be assigned to NULL
instead of 0.

Morten

> >  }
> >
> >  /**
> > --
> > 1.7.9.5
> >
> 



From dianders at chromium.org  Wed May 22 11:57:39 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed, 22 May 2013 08:57:39 -0700
Subject: [PATCH v3 6/6] pinctrl: exynos: Handle suspend/resume of GPIO
 EINT registers
In-Reply-To: <3059629.yu4Ei1BXhd@amdc1227>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <4536937.hnhaYZLnaG@amdc1227>
 <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>
 <3059629.yu4Ei1BXhd@amdc1227>
Message-ID: <CAD=FV=X3B9feSMmRQd5PYj01U+GEXMFG3tvj7hCY=89Uh9ccEg@mail.gmail.com>

Tomasz,

On Wed, May 22, 2013 at 7:03 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> Some GPIO EINT control registers needs to be preserved across
> suspend/resume cycle. This patch extends the driver to take care of
> this.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>
> Changes since v2:
>  - Fixed error path
> Changes since v1:
>  - Added optional debugging messages
>  - Added proper error path in initialization
>
>  drivers/pinctrl/pinctrl-exynos.c | 116 ++++++++++++++++++++++++++++++++++++++-
>  drivers/pinctrl/pinctrl-exynos.h |   1 +
>  2 files changed, 114 insertions(+), 3 deletions(-)

Looks good to me.  Thanks!

Good thing I tried the printouts too--they pointed to the fact that
"git am" had somehow applied part 4 ("Add support for SoC-specific
suspend/resume callbacks") incorrectly and with no warning!  It had
put the resume() call at the beginning of the suspend function.
Weird.  I had to fall back to using "patch -p1 to apply".  :-/


On exynos5250-snow (pinmux backported to 3.8):

Tested-by: Doug Anderson <dianders at chromium.org>

Reviewed-by: Doug Anderson <dianders at chromium.org>


From vincent.guittot at linaro.org  Wed May 22 11:58:58 2013
From: vincent.guittot at linaro.org (Vincent Guittot)
Date: Wed, 22 May 2013 17:58:58 +0200
Subject: [PATCH 13/14] sched: update the cpu_power
In-Reply-To: <20130522154639.GA4935@e103034-lin>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <1366910611-20048-14-git-send-email-vincent.guittot@linaro.org>
 <20130522154639.GA4935@e103034-lin>
Message-ID: <CAKfTPtBxt=W9m97=Ec5yjoMZX=TjpBanbRDQV=HV3b9DC_fDQw@mail.gmail.com>

On 22 May 2013 17:46, Morten Rasmussen <morten.rasmussen at arm.com> wrote:
> On Thu, Apr 25, 2013 at 06:23:29PM +0100, Vincent Guittot wrote:
>> @@ -4596,8 +4597,12 @@ static void update_cpu_power(struct sched_domain *sd, int cpu)
>>       cpu_rq(cpu)->cpu_available = power;
>>       sdg->sgp->power_available = power;
>>
>> +     if (!is_my_buddy(cpu, cpu))
>> +             power = 1;
>> +
>
> Using your fix for is_my_buddy() for patch 11 the above will always be
> true when sched_packing_mode is to anything else than
> SCHED_PACKING_FULL. So cpu_power for all cpus in
> SCHED_PACKING_{DEFAULT,NONE} is 1.
>
> As far is I understand, this is not the intention?

yes, the too quick fix for 11/14 has not fixed anything... the final
fix is available in git://git.linaro.org/people/vingu/kernel.git
sched-pack-small-tasks-v4-fixed.

And it will be part of the next version that i prepare

Vincent
>
> Cheers,
> Morten
>
>>       cpu_rq(cpu)->cpu_power = power;
>>       sdg->sgp->power = power;
>> +
>>  }
>>
>>  void update_group_power(struct sched_domain *sd, int cpu)
>> --
>> 1.7.9.5
>>
>>
>


From broonie at kernel.org  Wed May 22 11:53:47 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 22 May 2013 10:53:47 -0500
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20130522155347.GJ1627@sirena.org.uk>

On Wed, May 22, 2013 at 01:47:33PM +0100, Lee Jones wrote:
> This patch fixes a bug introduced in the v3.10 merge window.
> 
> Some platforms will not want external registers. Rather than setting up
> lots of different clauses in the core ab8500 regulator driver not to
> call ab8500-ext init() we just won't pass the initialisation data from
> platform code. This patch checks for it and if it's missing, we won't
> register the external regulators.

This seems problematic - if the regulators are unused then they
shouldn't have anything enabled in the constraints and the regulator
driver ought to be read only in which case it doesn't matter if it's
running or not, the worst that should happen is that the state can be
read back.  I'd therefore expect the fix here to be in the board side
code that enables the regulators.
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From florian.vaussard at epfl.ch  Wed May 22 12:00:32 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 18:00:32 +0200
Subject: [PATCH 2/5] ARM: dts: OMAP2+: create a DT header for GPIO
In-Reply-To: <20130522153452.GZ10378@atomide.com>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-3-git-send-email-florian.vaussard@epfl.ch>
 <519CE3BB.3040704@wwwdotorg.org> <20130522153452.GZ10378@atomide.com>
Message-ID: <519CEBA0.1080103@epfl.ch>

Hello Stephan, Tony,

Thank you for your reviews.

On 05/22/2013 05:34 PM, Tony Lindgren wrote:
> * Stephen Warren <swarren at wwwdotorg.org> [130522 08:32]:
>> On 05/22/2013 08:27 AM, Florian Vaussard wrote:
>>> Define the OMAP_GPIO macro to conveniently use GPIO inside OMAP DT.
>>> For example:
>>>
>>> 	gpios = <&gpio6 3 0>;  /* GPIO 163 */
>>>
>>> can be replaced by
>>>
>>> 	gpios = OMAP_GPIO(163, 0);
>>
>>> diff --git a/include/dt-bindings/gpio/omap-gpio.h b/include/dt-bindings/gpio/omap-gpio.h
>>
>>> +#define OMAP_GPIO_0_BANK        gpio1
>>> +#define OMAP_GPIO_1_BANK        gpio1
>>> +#define OMAP_GPIO_2_BANK        gpio1
>>> +#define OMAP_GPIO_3_BANK        gpio1
>>
>> There are a /lot/ of those. Is this really worth it?
>>
>> If the OMAP GPIO HW is already represented as a bunch of separate DT
>> nodes which represent separate GPIO blocks, then I would have thought
>> the syntax <&gpioN M 0> more directly represents what would be found in
>> the HW manual? If not, surely the DT should have a single node to
>> represent a single GPIO controller, which just happens to internally
>> support a bunch of register arrays.
>
> Yes I agree, let's not go back to numbering anything except within the
> a single instance. If anything, we can put the gpio number into comments.
>

 From a board point a view, I consider this macro as being easier to use,
than having to perform the necessary arithmetic to get the bank + offset
for each GPIO when converting existing boards or developing new ones.

But I also agree with you, and I was sad not to find a more elegant
way. Maybe someone with better preprocessor skills could come up with
a better solution?

Regards,

Florian


From florian.vaussard at epfl.ch  Wed May 22 12:02:51 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 18:02:51 +0200
Subject: [PATCH 3/5] ARM: dts: OMAP2+: convert DT files to use the new
 OMAP_GPIO macro
In-Reply-To: <519CE433.10903@wwwdotorg.org>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-4-git-send-email-florian.vaussard@epfl.ch>
 <519CE433.10903@wwwdotorg.org>
Message-ID: <519CEC2B.3040802@epfl.ch>

Hi Stepen,

Thank you for your review,

On 05/22/2013 05:28 PM, Stephen Warren wrote:
> On 05/22/2013 08:27 AM, Florian Vaussard wrote:
>> Use OMAP_GPIO(), in conjunction with standard GPIO flags, to enhance the
>> readability of DT GPIOs.
>
>> diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
>> index e0ce823..e773a5e 100644
>> --- a/arch/arm/boot/dts/omap3-beagle-xm.dts
>> +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
>> @@ -29,13 +29,13 @@
>>
>>   		heartbeat {
>>   			label = "beagleboard::usr0";
>> -			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
>> +			gpios = OMAP_GPIO(150, GPIO_ACTIVE_HIGH); /* 150 -> D6 LED */
>
> One of the advantages of cpp support for me is the ability to remove the
> redundant part of the command. In other words, perhaps remove the "150
> ->" since that information is part of the OMAP_GPIO() "call", leaving
> just /* D6 LED */. I might have expected "D6" to be the label too, thus
> removing any need for the comment.
>

I agree. I removed almost all the comments from the other files. For 
here, I would
leave /* D6 LED */ as you suggest.

Regards,

Florian


From swarren at wwwdotorg.org  Wed May 22 12:03:26 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 10:03:26 -0600
Subject: [PATCH 2/5] ARM: dts: OMAP2+: create a DT header for GPIO
In-Reply-To: <519CEBA0.1080103@epfl.ch>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-3-git-send-email-florian.vaussard@epfl.ch>
 <519CE3BB.3040704@wwwdotorg.org> <20130522153452.GZ10378@atomide.com>
 <519CEBA0.1080103@epfl.ch>
Message-ID: <519CEC4E.2060208@wwwdotorg.org>

On 05/22/2013 10:00 AM, Florian Vaussard wrote:
> Hello Stephan, Tony,
> 
> Thank you for your reviews.
> 
> On 05/22/2013 05:34 PM, Tony Lindgren wrote:
>> * Stephen Warren <swarren at wwwdotorg.org> [130522 08:32]:
>>> On 05/22/2013 08:27 AM, Florian Vaussard wrote:
>>>> Define the OMAP_GPIO macro to conveniently use GPIO inside OMAP DT.
>>>> For example:
>>>>
>>>>     gpios = <&gpio6 3 0>;  /* GPIO 163 */
>>>>
>>>> can be replaced by
>>>>
>>>>     gpios = OMAP_GPIO(163, 0);
>>>
>>>> diff --git a/include/dt-bindings/gpio/omap-gpio.h
>>>> b/include/dt-bindings/gpio/omap-gpio.h
>>>
>>>> +#define OMAP_GPIO_0_BANK        gpio1
>>>> +#define OMAP_GPIO_1_BANK        gpio1
>>>> +#define OMAP_GPIO_2_BANK        gpio1
>>>> +#define OMAP_GPIO_3_BANK        gpio1
>>>
>>> There are a /lot/ of those. Is this really worth it?
...
> From a board point a view, I consider this macro as being easier to use,
> than having to perform the necessary arithmetic to get the bank + offset
> for each GPIO when converting existing boards or developing new ones.
> 
> But I also agree with you, and I was sad not to find a more elegant
> way. Maybe someone with better preprocessor skills could come up with
> a better solution?

I did a quick bit of searching before, and while cpp is certainly
capable of doing the shifting/masking required to calculate the bank ID
directly, I don't think it's capable of constructing the symbol gpio1 as
opposed to the string "gpio1":-( I'd love to be proven wrong though, but
the torture e.g. cpp "99 bottles of beer on the wall" goes through to
stuff implies it isn't possible.


From vincent.guittot at linaro.org  Wed May 22 12:03:43 2013
From: vincent.guittot at linaro.org (Vincent Guittot)
Date: Wed, 22 May 2013 18:03:43 +0200
Subject: [PATCH 11/14] sched: filter task pull request
In-Reply-To: <20130522155658.GB4935@e103034-lin>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <1366910611-20048-12-git-send-email-vincent.guittot@linaro.org>
 <CAKfTPtCUvKmTHzyVRCkGyM-nWOSWP8OUzMgyCyzPEXf1NoxsQQ@mail.gmail.com>
 <20130522155658.GB4935@e103034-lin>
Message-ID: <CAKfTPtBO5-7ExugqCm7ChYCeBUUT9CUZ5gTZ9ASnt9AaJXZFkg@mail.gmail.com>

On 22 May 2013 17:56, Morten Rasmussen <morten.rasmussen at arm.com> wrote:
> On Fri, Apr 26, 2013 at 11:00:58AM +0100, Vincent Guittot wrote:
>> Part of this patch is missing, the fix below is needed
>>
>> @@ -3497,7 +3497,9 @@ static bool is_buddy_full(int cpu)
>>  static bool is_my_buddy(int cpu, int buddy)
>>  {
>>   int my_buddy = per_cpu(sd_pack_buddy, cpu);
>> - return (my_buddy == -1) || (buddy == my_buddy);
>> +
>> + return ((sysctl_sched_packing_mode == SCHED_PACKING_FULL) &&
>> +               ((my_buddy == -1) || (buddy == my_buddy)));
>>  }
>>
>>  static bool is_light_task(struct task_struct *p)
>>
>>
>> On 25 April 2013 19:23, Vincent Guittot <vincent.guittot at linaro.org> wrote:
>> > Only CPUs that participates to the packing effort can pull tasks on a busiest
>> > group.
>> >
>> > Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
>> > ---
>> >  kernel/sched/fair.c |   14 ++++++++++++--
>> >  1 file changed, 12 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
>> > index 28f8ea7..6f63fb9 100644
>> > --- a/kernel/sched/fair.c
>> > +++ b/kernel/sched/fair.c
>> > @@ -3494,6 +3494,12 @@ static bool is_buddy_full(int cpu)
>> >         return (sum * 1024 >= period * 1000);
>> >  }
>> >
>> > +static bool is_my_buddy(int cpu, int buddy)
>> > +{
>> > +       int my_buddy = per_cpu(sd_pack_buddy, cpu);
>> > +       return (my_buddy == -1) || (buddy == my_buddy);
>> > +}
>
> Would it make sense to change the function name to something like
> is_packing_target() and only have one argument?

I have replaced it with is_packing_cpu(int cpu) in my next version.
This function returns true if the cpu is part of the packing effort

>
> is_my_buddy() is only used with the same variable for both arguments
> like below.
>
>> > +
>> >  static bool is_light_task(struct task_struct *p)
>> >  {
>> >         /* A light task runs less than 20% in average */
>> > @@ -4688,8 +4694,8 @@ static inline void update_sg_lb_stats(struct lb_env *env,
>> >
>> >                 /* Bias balancing toward cpus of our domain */
>> >                 if (local_group) {
>> > -                       if (idle_cpu(i) && !first_idle_cpu &&
>> > -                                       cpumask_test_cpu(i, sched_group_mask(group))) {
>> > +                       if (is_my_buddy(i, i) && idle_cpu(i) && !first_idle_cpu
>> > +                        && cpumask_test_cpu(i, sched_group_mask(group))) {
>> >                                 first_idle_cpu = 1;
>> >                                 balance_cpu = i;
>> >                         }
>> > @@ -4817,6 +4823,10 @@ static void update_plb_buddy(int cpu, int *balance, struct sd_lb_stats *sds,
>> >
>> >         /* Get my new buddy */
>> >         buddy = per_cpu(sd_pack_buddy, cpu);
>> > +
>> > +       /* This CPU doesn't act for agressive packing */
>> > +       if (buddy != cpu)
>> > +               sds->busiest = 0;
>
> sds->busiest is a pointer, so I think it should be assigned to NULL
> instead of 0.

yes

Thanks
Vincent

>
> Morten
>
>> >  }
>> >
>> >  /**
>> > --
>> > 1.7.9.5
>> >
>>
>


From broonie at kernel.org  Wed May 22 12:03:42 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 22 May 2013 11:03:42 -0500
Subject: [PATCH v4] ASoC: dfbmcs320: make the driver common for other BT
 modules
In-Reply-To: <CAGsJ_4x3QrvReOnFQFqRMWfUf-v-Js4+L_Vr8jht_wR-ApQJrg@mail.gmail.com>
References: <1368879900-28395-1-git-send-email-Baohua.Song@csr.com>
 <20130521181849.GG1627@sirena.org.uk>
 <CAGsJ_4x3QrvReOnFQFqRMWfUf-v-Js4+L_Vr8jht_wR-ApQJrg@mail.gmail.com>
Message-ID: <20130522160342.GN1627@sirena.org.uk>

On Wed, May 22, 2013 at 01:15:26PM +0800, Barry Song wrote:

> thanks, Mark. can we also do something in omap-hdmi to make the HDMI
> codec common as well?
> i think it is in the same situation with BT SCO:
> http://comments.gmane.org/gmane.linux.alsa.devel/108234

None of the OMAP guys have reviewed that yet and you only sent it last
week.
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From florian.vaussard at epfl.ch  Wed May 22 12:05:35 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 22 May 2013 18:05:35 +0200
Subject: [PATCH 1/5] ARM: dts: OMAP2+: use #include for all device trees
In-Reply-To: <20130522154006.GB10378@atomide.com>
References: <1369232864-14460-1-git-send-email-florian.vaussard@epfl.ch>
 <1369232864-14460-2-git-send-email-florian.vaussard@epfl.ch>
 <20130522154006.GB10378@atomide.com>
Message-ID: <519CECCF.2080405@epfl.ch>

Hi Tony,

On 05/22/2013 05:40 PM, Tony Lindgren wrote:
> * Florian Vaussard <florian.vaussard at epfl.ch> [130522 07:33]:
>> Replace /include/ by #include for OMAP2+ DT, in order to use the
>> C pre-processor, making use of #define features possible.
>
> This is good, but let's use it with case. Probably the best use
> for this right now is to add defines for the mux modes from
> mach-omap2/mux.h as that makes the raw values readable without
> comments.
>

I think that one first good case is the IRQs in patch 5. But I
agree, adding defines for the mux modes would be great. I can have
a look at it for a v2.

Regards,

Florian


From florian.meier at koalo.de  Wed May 22 12:08:18 2013
From: florian.meier at koalo.de (Florian Meier)
Date: Wed, 22 May 2013 18:08:18 +0200
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CE2B7.8080704@wwwdotorg.org>
References: <519CD1CC.8070507@koalo.de> <519CE2B7.8080704@wwwdotorg.org>
Message-ID: <519CED72.40406@koalo.de>

On 22.05.2013 17:22, Stephen Warren wrote:
> On 05/22/2013 08:10 AM, Florian Meier wrote:
>> This driver adds support for digital audio (I2S)
>> for the BCM2708 SoC that is used by the
>> Raspberry Pi. External audio codecs can be
>> connected to the Raspberry Pi via P5 header.
>>
>> It relies on cyclic DMA engine support for BCM2708
>> that is not included in this patch.
> 
> This SoC is actually the BCM2835, so the files should be named for that.

Actually, I changed the name several times and in the end I sticked to
https://github.com/raspberrypi/linux/issues/22
but if you think it is better to use BCM2835 I am happy to agree with
you and change it.

> Upstream only uses device tree for BCM2835. Does this driver support DT?
> Where is the DT binding definition file?

I have not accomplished to use the mainline kernel and DT with the
Raspberry Pi. Do you have any introductive information about how to do this?

> I assume you're planning on sending the DMA driver upstream too? I guess
> this driver isn't useful without it.

I would like to, but it only supports cyclic DMA. Should I send it
upstream anyway? In case you are interested:

https://github.com/koalo/linux/blob/rpi-3.8.y-asocdev/drivers/dma/bcm2708-dmaengine.c

> I'll take a look at the actual patch content later.

That would be great!




From thomas.petazzoni at free-electrons.com  Wed May 22 12:08:42 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 18:08:42 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305221735.11815.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de>
Message-ID: <20130522180842.7edcc3ee@skate>

Dear Arnd Bergmann,

On Wed, 22 May 2013 17:35:11 +0200, Arnd Bergmann wrote:

> Ok, but going back to the discussion about remapping physical memory
> addresses, would you actually be able to map more of the available
> RAM when the registers are moved out of the way?

Yes, we can.

> IIRC the translation is rather coarse-grained, and the new location
> is still in the same 1GB window from 0xc0000000-0xffffffff.

We have four different CS for RAM, and therefore when we have 8 GB of
RAM installed, if the internal registers are at 0xD0000000, we loose
768 MB of RAM. When they are mapped at 0xF1000000, we loose only 256 MB
of RAM. A win of 512 MB of RAM, which is not negligible.

And the new bootloaders that are remapping to 0xf1000000 on Armada
370/XP are already being shipped by Marvell, so it's not like we have
much choice here.

> > > > So, the new generation of bootloaders that are shipped on new Marvell
> > > > Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
> > > > starting Linux. The current kernel cannot boot on such platforms.
> > > 
> > > Does it boot if you disable the DEBUG_LL code and apply your
> > > patches 1-8?
> > 
> > Patches 1-8 do not change anything in terms of the internal register
> > window base address. So just like the kernel was working with and
> > without DEBUG_LL before patches 1-8, it continues to work after those
> > cleanups/improvements.
> 
> I mean with the new boot loader which breaks unmodified kernels.

If you boot the kernel with, or without 1-8, it will not boot with a
new bootloader. Only if you apply the 9th patch will it work. And the
kernel will continue to work with both an old and a new bootloader.

> > I'm sorry, but I don't follow you here. When you have patches 1-8 (or
> > no patch applied at all), the UART for mach-mvebu is *always* at
> > 0xd0012000.
> 
> No. UART0 is always at 0xd0012000 but there are also UARTs at 0xd0012100,
> 0xd0012200 and 0xd0012300. You don't currently support using them for
> early output, but you might need to add that, similar to how other
> SoC platforms handle this.

Right.

> More importantly, you can build a kernel with any number of other SoCs
> already, and if you have a combined ArmadaXP+OMAP+Highbank kernel,
> there is no way to get a working early debug output.

So you're proposing to add two Kconfig options, one to have the UART at
0xd0012000 and the other one to have the UART at 0xf1012000. The user
would have to know whether he is going to boot with an old bootloader
or new bootloader, and select the appropriate option. This means that
the mvebu_defconfig would no longer be able to have earlyprintk enabled
by default, otherwise the resulting kernel may not boot for some
people, but maybe it's a reasonable tradeoff.

> > > As you already admit, using the CP15 register is a hack. It sounds
> > > to me that a cleaner approach would be to put the correct address
> > > into the device tree and use that value everywhere, rather than
> > > hardcoding one or more addresses.
> > 
> > I don't see how this can fix the problem. Which internal register base
> > address do we put in our Device Tree source in arch/arm/boot/dts? The
> > old one? The new one?
> 
> The one matching the boot loader for that board, i.e. the new address
> for all boards but Mirabox and OpenBlocks.

And what happens when Globalscale (Mirabox manufacturer) or Plathome
(manufacturer of OpenBlocks) release a new bootloader version, based on
the new bootloader from Marvell, which remaps things at 0xf1000000 ? Or
when those people boot from Barebox, which remaps at 0xf1000000 ?

Conclusion: you can't classify on one side boards that are at 0xd0 and
boards that are at 0xf1. It depends on *which* bootloader each
particular instance of those boards will be using. Will it be a
bootloader that complies with the "old" protocol (CP15 bit cleared and
registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
0xf1).

So we can't encode into the boards Device Tree whether the registers
are at 0xd0 or 0xf1, because it's not a board-related information, but
a bootloader-related information.

> > > > Unfortunately, tweaking ->map_io() is not sufficient: we also want
> > > > earlyprintk to work. And earlyprintk is used *before* ->map_io() is
> > > > called, and *after* ->map_io() is called.
> > > 
> > > Note that by the time map_io is called, we no longer care about
> > > the physical address, since the uart is only accessed through the
> > > virtual mapping after __enable_mmu.
> > 
> > That's not correct. ->map_io() calls debug_ll_io_init(), which calls
> > the addruart code of earlyprintk, from which it gets the virtual
> > address *AND* physical address of the UART, and sets up a mapping with
> > create_mapping(). See the implementation of debug_ll_io_init().
> 
> Ah right, but that is also something that could easily be changed.

I must admit I'm not sure why we have this debug_ll_io_init() function.
When DEBUG_LL is enabled, there is already a call to addruart from
arch/arm/kernel/head.S, which does create a virtual -> physical mapping
that covers the UART area. Since debug_ll_io_init() is also only
enabled under DEBUG_LL, I am not sure to understand what it does that
the assembly code in arch/arm/kernel/head.S hasn't done already. Adding
Rob in Cc, as he's the one who added debug_ll_io_init() in the first
place.

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From 21cnbao at gmail.com  Wed May 22 12:13:18 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 23 May 2013 00:13:18 +0800
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
Message-ID: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>

From: Binghua Duan <Binghua.Duan at csr.com>

there is an embedded PWRC(power controller) in SiRFprimaII and SiRFatlasVI,
we have an ONKEY button which can generate interrupt to IRQ controller.
in a typical user scenarios, at the runtime, if users touch the key, we put
system to s2ram status.

Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/input/misc/Kconfig         |  10 +++
 drivers/input/misc/Makefile        |   1 +
 drivers/input/misc/sirfsoc_onkey.c | 176 +++++++++++++++++++++++++++++++++++++
 3 files changed, 187 insertions(+)
 create mode 100644 drivers/input/misc/sirfsoc_onkey.c

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index bb698e1..1d91d1b 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -637,4 +637,14 @@ config INPUT_XEN_KBDDEV_FRONTEND
 	  To compile this driver as a module, choose M here: the
 	  module will be called xen-kbdfront.
 
+config INPUT_SIRFSOC_ONKEY
+	bool "CSR SiRFSoC power on/off/suspend key support"
+	depends on ARCH_SIRF
+	default y
+	help
+	  Say Y here if you want to support for the SiRFSoC power on/off/suspend key
+	  in Linux, after you press the onkey, system will suspend.
+
+	  If unsure, say N.
+
 endif
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index d7fc17f..1d66f03 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS)	+= wistron_btns.o
 obj-$(CONFIG_INPUT_WM831X_ON)		+= wm831x-on.o
 obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND)	+= xen-kbdfront.o
 obj-$(CONFIG_INPUT_YEALINK)		+= yealink.o
+obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)	+= sirfsoc_onkey.o
diff --git a/drivers/input/misc/sirfsoc_onkey.c b/drivers/input/misc/sirfsoc_onkey.c
new file mode 100644
index 0000000..3e48db9
--- /dev/null
+++ b/drivers/input/misc/sirfsoc_onkey.c
@@ -0,0 +1,176 @@
+/*
+ * Power key driver for SiRF PrimaII
+ *
+ * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/rtc/sirfsoc_rtciobrg.h>
+#include <linux/of.h>
+
+struct sirfsoc_pwrc_drvdata {
+	u32			pwrc_base;
+	int			irq;
+	struct input_dev	*input;
+};
+
+#define PWRC_ON_KEY_BIT			(1 << 0)
+
+#define PWRC_INT_STATUS			0xc
+#define PWRC_INT_MASK			0x10
+
+static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
+{
+	struct sirfsoc_pwrc_drvdata *pwrcdrv =
+			(struct sirfsoc_pwrc_drvdata *)dev_id;
+	u32 int_status;
+	int_status = sirfsoc_rtc_iobrg_readl(
+			pwrcdrv->pwrc_base + PWRC_INT_STATUS);
+	sirfsoc_rtc_iobrg_writel(int_status & (~PWRC_ON_KEY_BIT),
+			pwrcdrv->pwrc_base + PWRC_INT_STATUS);
+
+	/*
+	 * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
+	 * to queue a SUSPEND APM event
+	 */
+	input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
+	input_sync(pwrcdrv->input);
+
+	/*
+	 * Todo: report KEY_POWER event for Android platforms, Android PowerManager
+	 * will handle the suspend and powerdown/hibernation
+	 */
+
+	return IRQ_HANDLED;
+}
+
+static const struct of_device_id sirfsoc_pwrc_of_match[] = {
+	{ .compatible = "sirf,prima2-pwrc" },
+	{},
+}
+MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
+
+static int sirfsoc_pwrc_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct sirfsoc_pwrc_drvdata *pwrcdrv = NULL;
+	struct device_node *np = pdev->dev.of_node;
+
+	pwrcdrv = devm_kzalloc(&pdev->dev,
+		sizeof(struct sirfsoc_pwrc_drvdata), GFP_KERNEL);
+	if (!pwrcdrv) {
+		dev_info(&pdev->dev, "kzalloc fail!\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * we can't use of_iomap because pwrc is not mapped in memory, the so-called base
+	 * address is only offset in rtciobrg
+	 */
+	ret = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to find base address of pwrc node in dtb\n");
+		return ret;
+	}
+
+	pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
+	if (!pwrcdrv->input)
+		return -ENOMEM;
+
+	pwrcdrv->input->name = "sirfsoc pwrckey";
+	pwrcdrv->input->phys = "pwrc/input0";
+
+	platform_set_drvdata(pdev, pwrcdrv);
+
+	pwrcdrv->irq = platform_get_irq(pdev, 0);
+	ret = devm_request_irq(&pdev->dev, pwrcdrv->irq,
+			sirfsoc_pwrc_isr, IRQF_SHARED,
+			"sirfsoc_pwrc_int", pwrcdrv);
+
+	sirfsoc_rtc_iobrg_writel(
+		sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK)
+		| PWRC_ON_KEY_BIT, pwrcdrv->pwrc_base + PWRC_INT_MASK);
+	if (ret) {
+		dev_err(&pdev->dev, "pwrc: Unable to claim irq %d; error %d\n",
+			pwrcdrv->irq, ret);
+		return ret;
+	}
+
+	pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
+	set_bit(KEY_POWER, pwrcdrv->input->keybit);
+
+	ret = input_register_device(pwrcdrv->input);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"pwrc: Unable to register input device,error: %d\n",
+			ret);
+		return ret;
+	}
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	return 0;
+}
+
+static int sirfsoc_pwrc_remove(struct platform_device *pdev)
+{
+	device_init_wakeup(&pdev->dev, 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pwrc_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int pwrc_resume(struct device *dev)
+{
+	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
+
+	/* 
+	 * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
+	 * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
+	 */
+	sirfsoc_rtc_iobrg_writel(
+		sirfsoc_rtc_iobrg_readl(
+		pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
+		pwrcdrv->pwrc_base + PWRC_INT_MASK);
+
+	return 0;
+}
+
+static const struct dev_pm_ops sirfsoc_pwrc_pm_ops = {
+	.suspend = pwrc_suspend,
+	.resume	= pwrc_resume,
+};
+#endif
+
+static struct platform_driver sirfsoc_pwrc_driver = {
+	.probe		= sirfsoc_pwrc_probe,
+	.remove		= sirfsoc_pwrc_remove,
+	.driver		= {
+		.name	= "sirfsoc-pwrc",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &sirfsoc_pwrc_pm_ops,
+#endif
+		.of_match_table = of_match_ptr(sirfsoc_pwrc_of_match),
+	}
+};
+
+module_platform_driver(sirfsoc_pwrc_driver);
+
+MODULE_LICENSE("GPLv2");
+MODULE_AUTHOR("Binghua Duan <Binghua.Duan at csr.com>, "
+		"Xianglong Du <Xianglong.Du at csr.com>");
+MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
+MODULE_ALIAS("platform:sirfsoc-pwrc");
-- 
1.8.2.3



From swarren at wwwdotorg.org  Wed May 22 12:15:56 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 10:15:56 -0600
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CED72.40406@koalo.de>
References: <519CD1CC.8070507@koalo.de> <519CE2B7.8080704@wwwdotorg.org>
 <519CED72.40406@koalo.de>
Message-ID: <519CEF3C.4000502@wwwdotorg.org>

On 05/22/2013 10:08 AM, Florian Meier wrote:
> On 22.05.2013 17:22, Stephen Warren wrote:
>> On 05/22/2013 08:10 AM, Florian Meier wrote:
>>> This driver adds support for digital audio (I2S)
>>> for the BCM2708 SoC that is used by the
>>> Raspberry Pi. External audio codecs can be
>>> connected to the Raspberry Pi via P5 header.
>>>
>>> It relies on cyclic DMA engine support for BCM2708
>>> that is not included in this patch.
>>
>> This SoC is actually the BCM2835, so the files should be named for that.
> 
> Actually, I changed the name several times and in the end I sticked to
> https://github.com/raspberrypi/linux/issues/22
> but if you think it is better to use BCM2835 I am happy to agree with
> you and change it.
> 
>> Upstream only uses device tree for BCM2835. Does this driver support DT?
>> Where is the DT binding definition file?
> 
> I have not accomplished to use the mainline kernel and DT with the
> Raspberry Pi. Do you have any introductive information about how to do this?

Oh, so is this patch intended for the downstream Raspberry Pi Foundation
kernel, or the upstream kernel?

The fact you haven't run it on the upstream kernel implies that you
intend the patch to be applied to the downstream kernel.

The fact you sent the driver to all the upstream mailing lists implies
that you intend the patch to be applied to the upstream kernel.

BTW, I wrote a Google+ post on using the upstream kernel on the Pi:
https://plus.google.com/101715070573995136397/posts/gWkwrfNfYVm

>> I assume you're planning on sending the DMA driver upstream too? I guess
>> this driver isn't useful without it.
> 
> I would like to, but it only supports cyclic DMA. Should I send it
> upstream anyway? In case you are interested:

I don't think that limitation would stop it being useful upstream;
somebody else might always enhance it.


From andrew at lunn.ch  Wed May 22 12:16:21 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 18:16:21 +0200
Subject: [PATCH v4 00/12] net: mv643xx_eth DT support and fixes
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130522161621.GM2824@lunn.ch>

On Tue, May 21, 2013 at 06:41:38PM +0200, Sebastian Hesselbarth wrote:
> This patch set picks up work by Florian Fainelli bringing full DT
> support to mv643xx_eth and Marvell SoCs using it.

Hi Sebastian

I tested on my QNAP and topkick. Works great.

Tested-by: Andrew Lunn <andrew at lunn.ch>

   Andrew


From peterz at infradead.org  Wed May 22 12:19:35 2013
From: peterz at infradead.org (Peter Zijlstra)
Date: Wed, 22 May 2013 18:19:35 +0200
Subject: [PATCH] kernel/sched/core.c: need return NULL when BUG() is
 defined as empty.
In-Reply-To: <20130522133317.GC18614@n2100.arm.linux.org.uk>
References: <5199D565.4070307@asianux.com>
 <20130522091156.GC18810@twins.programming.kicks-ass.net>
 <20130522133317.GC18614@n2100.arm.linux.org.uk>
Message-ID: <20130522161935.GR18810@twins.programming.kicks-ass.net>

On Wed, May 22, 2013 at 02:33:17PM +0100, Russell King - ARM Linux wrote:
> On Wed, May 22, 2013 at 11:11:56AM +0200, Peter Zijlstra wrote:
> > On Mon, May 20, 2013 at 03:48:53PM +0800, Chen Gang wrote:
> > > 
> > > When neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, need let function
> > > return failure value ('NULL') instead of random value.
> > 
> > What will such a kernel do? Happily continue running whenever we hit a
> > BUG? that seems like a particularly bad idea. Should we not have a stub
> > BUG() function like:
> > 
> > void BUG(void) __attribute__((noreturn))
> > {
> > 	local_irq_disable();
> > 	while (1) ;
> > }
> 
> Eww.  So you've a platform where you have things like panic_on_oops
> enabled, and you hit this bug... do we really want to just stop?
> Wouldn't replacing BUG() with panic("BUG"); be better ?
> 
> But, this begs the question - what is the point of being able to turn
> off BUG() ?  As BUG() on any sensible architecture is implemented by
> placing the minimum of code at the callsite (eg, one instruction if
> not using verbose) anything like the above is likely to be bigger.
> 
> So, I'd actually argue that rather than trying to "fix" this, get rid
> of CONFIG_BUG and make it always enabled everywhere - just like what
> has recently been done with hotplug.

Works for me. 


From thomas.petazzoni at free-electrons.com  Wed May 22 12:22:19 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 18:22:19 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522155134.GL2824@lunn.ch>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522155134.GL2824@lunn.ch>
Message-ID: <20130522182219.062079ac@skate>

Dear Andrew Lunn,

On Wed, 22 May 2013 17:51:34 +0200, Andrew Lunn wrote:

> Maybe i'm missunderstand Arnd, but i think he is suggesting a property
> somewhere in DT which says where the bootloader left the register
> space before jumping to the kernel. You can then look at this property
> and then decide if you need to remap or not. Only this one property
> needs to differ between old and new bootloader. You could even say, if
> the property is not in DT, a remap is needed.

The problem is that neither the old nor the new bootloaders are setting
such property in the DT. Old bootloaders shipped by Marvell don't have
DT support at all. New bootloaders shipped by Marvell do have DT
support, but they are not adding any specific DT property that allows
us to tell whether the registers are mapped here or there.

We could maybe find a way of detecting whether if the bootloader is DT
capable, and assume that if it's DT capable, the registers are already
mapped at 0xf1. But that's very fragile: nothing prevents an user to
use a DT-capable bootloader to boot a kernel in the old style way
(appended DTB). In this case, we would assume that the registers are at
0xd0, because we're being booted old-style, and therefore it must be an
old bootloader. Very fragile, clearly not better than the CP15 trick.

> However, i don't know if this can actually work. How early can you
> parse the DT in order to know where the serial port is for
> earlyprintk()? It also gets messy keeping track of the two different
> DT binary blobs and somehow having the probe the uboot version in
> order to install the right one. I don't know how i would include this
> into the debian flash-kernel for example.

For earlyprintk, we can "solve" it as Arnd suggested: just have two
Kconfig options, one for 0xd0, one for 0xf1, and it's up to the user to
choose the right one. It's not entirely nice because it's no longer
automatic, and I'm sure our users will have a hard time figuring out
whether they have an "old" or a "new" bootloader. But let's assume we
do this. earlyprintk knows the physical address of the UART.

Then, we enter ->map_io(). We have access to the Device Tree. But the
Device Tree doesn't tell us whether the bootloader has mapped the
registers. As I explained to Arnd, it's not a per-board criteria: when
I'm booting my OpenBlocks with the manufacturer U-Boot, registers are
mapped at 0xd0. When I boot the same OpenBlocks with the (admittedly
work-in-progress) Barebox bootloader, registers are mapped at 0xf1.
Same board, different register location.

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From 21cnbao at gmail.com  Wed May 22 12:28:21 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 23 May 2013 00:28:21 +0800
Subject: [PATCH] pinctrl: sirf: save the status in suspend and restore
 after resuming
In-Reply-To: <CACRpkdaSTC8cLi-C_gwZEk8iF=bnAce920DbKvxN6S-=75xbnA@mail.gmail.com>
References: <1368674229-11813-1-git-send-email-Baohua.Song@csr.com>
 <CACRpkdaSTC8cLi-C_gwZEk8iF=bnAce920DbKvxN6S-=75xbnA@mail.gmail.com>
Message-ID: <CAGsJ_4wPd1_T--ezGQQVbeL3sJQwSTACJvE787JUoDQVvZ_muw@mail.gmail.com>

2013/5/20 Linus Walleij <linus.walleij at linaro.org>:
> On Thu, May 16, 2013 at 5:17 AM, Barry Song <Baohua.Song at csr.com> wrote:
>
>> this patch saves the status of pinctrl registers and restore them while
>> resuming. this makes all drivers have coherent status for pinmux after
>> suspending and resuming.
>>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>
> Applied, but a quick remark that you may want to fix up:

thanks, linus. i will have an incremental patch to fix it.

>
> (...)
>
>> +#ifdef CONFIG_PM_SLEEP
>> +static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
>> +{
>> +       int i, j;
>> +       struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
>> +
>> +       for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
>> +               for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
>> +                       spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
>> +                               SIRFSOC_GPIO_CTRL(i, j));
>> +               }
>> +               spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
>> +                       SIRFSOC_GPIO_INT_STATUS(i));
>> +               spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
>> +                       SIRFSOC_GPIO_PAD_EN(i));
>> +       }
>> +       spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
>> +
>> +       for (i = 0; i < 3; i++)
>
> Why are you hard-coding 3 here? It looks fragile.

that means i have 3 registers beginning from spmx->rsc_virtbase to
save and restore. i missed to check the name of everyone.

>
>> +               spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
>> +ery
>> +       return 0;
>> +}
>> +
>> +static int sirfsoc_pinmux_resume_noirq(struct device *dev)
>> +{
>> +       int i, j;
>> +       struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
>> +
>> +       for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
>> +               for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
>> +                       writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
>> +                               SIRFSOC_GPIO_CTRL(i, j));
>> +               }
>> +               writel(spmx->ints_regs[i], spmx->gpio_virtbase +
>> +                       SIRFSOC_GPIO_INT_STATUS(i));
>> +               writel(spmx->paden_regs[i], spmx->gpio_virtbase +
>> +                       SIRFSOC_GPIO_PAD_EN(i));
>> +       }
>> +       writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
>> +
>> +       for (i = 0; i < 3; i++)
>
> Dito.
>
> Yours,
> Linus Walleij
>

-barry


From w at 1wt.eu  Wed May 22 12:35:57 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Wed, 22 May 2013 18:35:57 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522180842.7edcc3ee@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
Message-ID: <20130522163557.GC27348@1wt.eu>

Hi Thomas,

On Wed, May 22, 2013 at 06:08:42PM +0200, Thomas Petazzoni wrote:
> And the new bootloaders that are remapping to 0xf1000000 on Armada
> 370/XP are already being shipped by Marvell, so it's not like we have
> much choice here.

Which also means we can't request to modify new boot loaders to pass
any specific information.

(...)
> And what happens when Globalscale (Mirabox manufacturer) or Plathome
> (manufacturer of OpenBlocks) release a new bootloader version, based on
> the new bootloader from Marvell, which remaps things at 0xf1000000 ? Or
> when those people boot from Barebox, which remaps at 0xf1000000 ?

We experienced a similar issue some time ago when something changed
in the boot loader spec. Kernels >= 3.2 would randomly hang at boot
when using old boot loaders, and many boot loaders had to be upgraded.
It was quite painful because there was no information reported with
this hang but I guess most people managed to upgrade the boot loaders.
I don't know for how long devices have been shipped with boot loaders
mapping at 0xd0, nor if all these platforms do have a new boot loader,
but maybe the same forced upgrade could be reasonable, I have no idea.
On the other hand, if we consider the forced upgrade as mostly acceptable,
then the CP15 trick already is an acceptable workaround in that it is
used as an indicator to detect the old boot loader. So even if for any
reason it fails on some users, they'll have to upgrade anyway.

> Conclusion: you can't classify on one side boards that are at 0xd0 and
> boards that are at 0xf1. It depends on *which* bootloader each
> particular instance of those boards will be using. Will it be a
> bootloader that complies with the "old" protocol (CP15 bit cleared and
> registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> 0xf1).

Just a point I'm thinking about, is it possible to detect the boot loader's
mode via ATAGs ? ATAGs are present very early as well (but maybe too late
already).

> So we can't encode into the boards Device Tree whether the registers
> are at 0xd0 or 0xf1, because it's not a board-related information, but
> a bootloader-related information.

I totally agree with you. The issue is only the boot loader.

Best regards,
Willy



From broonie at kernel.org  Wed May 22 12:39:42 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 22 May 2013 11:39:42 -0500
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CD1CC.8070507@koalo.de>
References: <519CD1CC.8070507@koalo.de>
Message-ID: <20130522163942.GQ1627@sirena.org.uk>

On Wed, May 22, 2013 at 04:10:20PM +0200, Florian Meier wrote:

> This driver adds support for digital audio (I2S)
> for the BCM2708 SoC that is used by the
> Raspberry Pi. External audio codecs can be
> connected to the Raspberry Pi via P5 header.

Split this up into a patch series, for example one per CPU side driver
and one per machine driver.  I've given the code a relatively quick run
through here, it looks mostly sensible though DT would be nice but
there's a few comments.

> +static inline void bcm2708_i2s_write_reg(struct bcm2708_i2s_dev *dev,
> +					   int reg, u32 val)
> +{
> +	dev_dbg(dev->dev, "I2S write to register %p = %x\n",
> +			dev->clk_base + reg, val);
> +	__raw_writel(val, dev->i2s_base + reg);
> +}

This all looks like you want to use regmap-mmio - that'll get you all
the logging and so on for free too.

> +static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
> +{
> +	/*
> +	 * Start the clock if in master mode.
> +	 */
> +	unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
> +	if (master == SND_SOC_DAIFMT_CBS_CFS
> +			|| master == SND_SOC_DAIFMT_CBS_CFM) {

This looks like it should be a switch statement.

> +		unsigned int clkreg = bcm2708_clk_read_reg(dev,
> +				BCM2708_CLK_PCMCTL_REG);
> +		bcm2708_clk_write_reg(dev, BCM2708_CLK_PCMCTL_REG,
> +				BCM2708_CLK_PASSWD | clkreg | BCM2708_CLK_ENAB);
> +	}

Shouldn't this be using your set bits operation?

> +static bool bcm2708_i2s_check_other_stream(struct bcm2708_i2s_dev *dev,
> +					struct snd_pcm_substream *substream,
> +					struct snd_pcm_substream *other_stream,
> +					struct snd_pcm_hw_params *params)
> +{
> +	if (other_stream->runtime->format &&
> +		(other_stream->runtime->format != params_format(params))) {
> +		dev_err(dev->dev,
> +			"Sample formats of streams are different. %i (%s) != %i (%s) Initialization failed!\n",
> +			other_stream->runtime->format,
> +			(other_stream->stream ==
> +			 SNDRV_PCM_STREAM_PLAYBACK ?
> +			 "playback" : "capture"),
> +			params_format(params),
> +			(substream->stream ==
> +			 SNDRV_PCM_STREAM_PLAYBACK ?
> +			 "playback" : "capture"));

This is illegible.

> +	/* Ensure, that both streams have the same settings */
> +	struct snd_pcm_substream *other_stream = dev->first_stream;
> +	if (other_stream == substream)
> +		other_stream = dev->second_stream;

Set constraints for this so that the upper layers will stop mismatched
settings being configured.

> +	/*
> +	 * Clear both FIFOs if the one that should be started
> +	 * is not empty at the moment. This should only happen
> +	 * after overrun. Otherwise, hw_params would have cleared
> +	 * the FIFO.
> +	 */

Why both?

> +	case SNDRV_PCM_TRIGGER_START:
> +	case SNDRV_PCM_TRIGGER_RESUME:
> +	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> +		bcm2708_i2s_start(dev, substream);

These functions are pretty small, I'd just inline them.

> +		/*
> +		 * This is the second stream open, so we need to impose
> +		 * sample size and sampling rate constraints.
> +		 * This is because frame length and clock cannot be specified
> +		 * seperately.
> +		 *
> +		 * Note that this can cause a race condition if the
> +		 * second stream is opened before the first stream is
> +		 * fully initialized.  We provide some protection by
> +		 * checking to make sure the first stream is
> +		 * initialized, but it's not perfect.  ALSA sometimes
> +		 * re-initializes the driver with a different sample
> +		 * rate or size.  If the second stream is opened
> +		 * before the first stream has received its final
> +		 * parameters, then the second stream may be
> +		 * constrained to the wrong sample rate or size.
> +		 *
> +		 * We will continue in case of failure and recheck the
> +		 * constraint in hw_params.
> +		 */
> +		if (!first_runtime->format) {
> +			dev_err(substream->pcm->card->dev,
> +					"Set format in %s stream first! "
> +					"Initialization may fail.\n",

Don't split strings, but in any case you should just let people set up -
hopefully they'll try to set something that might work anyway.  Any code
for fixing this up should be in the core, like symmetric_rates.

> +static void bcm2708_i2s_setup_gpio(void)
> +{
> +	/*
> +	 * This is the common way to handle the GPIO pins for
> +	 * the Raspberry Pi.
> +	 * TODO Better way would be to handle
> +	 * this in the device tree!
> +	 */

Yup.

> +	/* request both ioareas */
> +	for (i = 0; i <= 1; i++) {
> +		struct resource *mem, *ioarea;
> +		mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
> +		if (!mem) {

devm_ioremap_resource().

> +	/* get DMA data (e.g. FIFO address and DREQ) */
> +	dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
> +
> +	/*
> +	 * There seems to be no use for bufferless
> +	 * transfer with this SoC.
> +	 */
> +	if (!dma_data)
> +		return 0;

This is now supported properly by the framework, no need for this.

> +	dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
> +
> +	switch (cmd) {
> +	case SNDRV_PCM_TRIGGER_START:
> +	case SNDRV_PCM_TRIGGER_RESUME:
> +	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> +		break;
> +
> +	case SNDRV_PCM_TRIGGER_STOP:
> +	case SNDRV_PCM_TRIGGER_SUSPEND:
> +	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> +		break;
> +	default:
> +		ret = -EINVAL;
> +	}
> +
> +	if (ret == 0)
> +		ret = snd_dmaengine_pcm_trigger(substream, cmd);

Juse don't have switch statement.

> +static snd_pcm_uframes_t bcm2708_pcm_pointer(
> +		struct snd_pcm_substream *substream)
> +{
> +	return snd_dmaengine_pcm_pointer(substream);
> +}

Should just be able to use snd_dmaengine_pcm_pointer() as the ops.

> +static int bcm2708_pcm_mmap(struct snd_pcm_substream *substream,
> +	struct vm_area_struct *vma)

This should be a generic op...

> +{
> +	struct snd_pcm_runtime *runtime = substream->runtime;
> +
> +	return dma_mmap_writecombine(substream->pcm->card->dev, vma,

Should be using the DMA controller device not the card.

> +				     runtime->dma_area,
> +				     runtime->dma_addr,
> +				     runtime->dma_bytes);
> +}

> +static int bcm2708_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
> +	int stream)
> +{
> +	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
> +	struct snd_dma_buffer *buf = &substream->dma_buffer;
> +	size_t size = bcm2708_pcm_hardware.buffer_bytes_max;
> +
> +	buf->dev.type = SNDRV_DMA_TYPE_DEV;
> +	buf->dev.dev = pcm->card->dev;

DMA controller device.

> +static int snd_rpi_mbed_init(struct snd_soc_pcm_runtime *rtd)
> +{
> +	return 0;
> +}

Empty functions can just be removed.

> +static const unsigned int wm8731_rates_12288000[] = {
> +	8000, 32000, 48000, 96000,
> +};
> +
> +static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {
> +	.list = wm8731_rates_12288000,
> +	.count = ARRAY_SIZE(wm8731_rates_12288000),
> +};
> +
> +static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)
> +{
> +	/* Setup constraints, because there is a 12.288 MHz XTAL on the board */
> +	snd_pcm_hw_constraint_list(substream->runtime, 0,
> +				SNDRV_PCM_HW_PARAM_RATE,
> +				&wm8731_constraints_12288000);
> +	return 0;
> +}

Push this into the CODEC driver, this will be true for the device on any
platform with a fixed clock.

> +static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,
> +				       struct snd_pcm_hw_params *params)
> +{
> +	struct snd_soc_pcm_runtime *rtd = substream->private_data;
> +	struct snd_soc_dai *codec_dai = rtd->codec_dai;
> +	int sysclk = 12288000; /* This is fixed on this board */
> +
> +	/* Set proto sysclk */
> +	int ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
> +		sysclk, SND_SOC_CLOCK_IN);
> +	if (ret < 0) {
> +		dev_err(substream->pcm->dev,
> +				"Failed to set WM8731 SYSCLK: %d\n", ret);
> +		return ret;
> +	}

Since this is fixed just do it once on init (eg, in late_probe()) rather
than every single time.
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From broonie at kernel.org  Wed May 22 12:42:10 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 22 May 2013 11:42:10 -0500
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CED72.40406@koalo.de>
References: <519CD1CC.8070507@koalo.de> <519CE2B7.8080704@wwwdotorg.org>
 <519CED72.40406@koalo.de>
Message-ID: <20130522164210.GS1627@sirena.org.uk>

On Wed, May 22, 2013 at 06:08:18PM +0200, Florian Meier wrote:
> On 22.05.2013 17:22, Stephen Warren wrote:

> > I assume you're planning on sending the DMA driver upstream too? I guess
> > this driver isn't useful without it.

> I would like to, but it only supports cyclic DMA. Should I send it
> upstream anyway? In case you are interested:

It seems better to send something partially featured upstream so that
people can work on enhancing it rather than having nothing all upstream.
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From thomas.petazzoni at free-electrons.com  Wed May 22 12:42:50 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 18:42:50 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522163557.GC27348@1wt.eu>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu>
Message-ID: <20130522184250.1d5f2f10@skate>

Dear Willy Tarreau,

On Wed, 22 May 2013 18:35:57 +0200, Willy Tarreau wrote:

> On Wed, May 22, 2013 at 06:08:42PM +0200, Thomas Petazzoni wrote:
> > And the new bootloaders that are remapping to 0xf1000000 on Armada
> > 370/XP are already being shipped by Marvell, so it's not like we have
> > much choice here.
> 
> Which also means we can't request to modify new boot loaders to pass
> any specific information.

Correct.

> > And what happens when Globalscale (Mirabox manufacturer) or Plathome
> > (manufacturer of OpenBlocks) release a new bootloader version, based on
> > the new bootloader from Marvell, which remaps things at 0xf1000000 ? Or
> > when those people boot from Barebox, which remaps at 0xf1000000 ?
> 
> We experienced a similar issue some time ago when something changed
> in the boot loader spec. Kernels >= 3.2 would randomly hang at boot
> when using old boot loaders, and many boot loaders had to be upgraded.
> It was quite painful because there was no information reported with
> this hang but I guess most people managed to upgrade the boot loaders.

Agreed. I already receive quite a number of e-mails from users trying
to do this or that with the Mirabox, and I'm not sure I would receive
many more e-mails if the kernel would not "just" work without having to
do some bizarre configuration. Especially if the kernel just hangs with
no useful information.

> I don't know for how long devices have been shipped with boot loaders
> mapping at 0xd0, nor if all these platforms do have a new boot loader,
> but maybe the same forced upgrade could be reasonable, I have no idea.

I guess the Mirabox and OpenBlocks have been shipping for about 9-10
months now. Judging by the amount of e-mails are received about Mirabox
kernel (asking when PCIe support will be available, when NAND will be
available), there is definitely a certain number of people who have
those platforms in their hands.

> On the other hand, if we consider the forced upgrade as mostly acceptable,
> then the CP15 trick already is an acceptable workaround in that it is
> used as an indicator to detect the old boot loader. So even if for any
> reason it fails on some users, they'll have to upgrade anyway.

My plan would be to have this CP15 trick for now. In two release
cycles, show a big fat warning to users that are booting with old
bootloaders, which would encourage them to update their bootloader. By
this time, hopefully, the manufacturers of OpenBlocks and Mirabox will
have released updated bootloader versions, and we can tell users to
upgrade. The upgrade process is easy and safe, because it takes place
through the UART, as you know.

Then, another two release cycles later, we could remove the CP15 trick
entirely.

So it's just a matter of living with this for about 4 release cycles,
approximately a year.

> > Conclusion: you can't classify on one side boards that are at 0xd0 and
> > boards that are at 0xf1. It depends on *which* bootloader each
> > particular instance of those boards will be using. Will it be a
> > bootloader that complies with the "old" protocol (CP15 bit cleared and
> > registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> > 0xf1).
> 
> Just a point I'm thinking about, is it possible to detect the boot loader's
> mode via ATAGs ? ATAGs are present very early as well (but maybe too late
> already).

As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
ARM register that was used to pass the pointer to the ATAGS is now used
to pass the pointer to the DTB in memory.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From s.hauer at pengutronix.de  Wed May 22 12:47:10 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 22 May 2013 18:47:10 +0200
Subject: imx53 cspi clock problem
In-Reply-To: <519C6B3D.3030106@microbit.se>
References: <519C6B3D.3030106@microbit.se>
Message-ID: <20130522164710.GE31135@pengutronix.de>

On Wed, May 22, 2013 at 08:52:45AM +0200, Jonas Andersson wrote:
> Hi,
> 
> i have found a problem when using the cspi port in a imx53 soc. I am
> using kernel 3.10-rc2. This is the dts defenition:
> 
> cspi: cspi at 63fc0000 {
> 	#address-cells = <1>;
> 	#size-cells = <0>;
> 	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
> 	reg = <0x63fc0000 0x4000>;
> 	interrupts = <38>;
> 	clocks = <&clks 55>, <&clks 0>;

Unlike the eCSPI controller the CSPI controller seems to have only one
clock. This should probably be

	clocks = <&clks 55>, <&clks 55>;

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From w at 1wt.eu  Wed May 22 12:49:28 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Wed, 22 May 2013 18:49:28 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522184250.1d5f2f10@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
Message-ID: <20130522164928.GD27348@1wt.eu>

On Wed, May 22, 2013 at 06:42:50PM +0200, Thomas Petazzoni wrote:
> > I don't know for how long devices have been shipped with boot loaders
> > mapping at 0xd0, nor if all these platforms do have a new boot loader,
> > but maybe the same forced upgrade could be reasonable, I have no idea.
> 
> I guess the Mirabox and OpenBlocks have been shipping for about 9-10
> months now. Judging by the amount of e-mails are received about Mirabox
> kernel (asking when PCIe support will be available, when NAND will be
> available), there is definitely a certain number of people who have
> those platforms in their hands.

Indeed, but either these people are running stock kernel on them and don't
care, or they're ready to hack their box and should not be much frightened
by a boot loader upgrade (especially since it's safe from the UART as we
have found).

> > On the other hand, if we consider the forced upgrade as mostly acceptable,
> > then the CP15 trick already is an acceptable workaround in that it is
> > used as an indicator to detect the old boot loader. So even if for any
> > reason it fails on some users, they'll have to upgrade anyway.
> 
> My plan would be to have this CP15 trick for now. In two release
> cycles, show a big fat warning to users that are booting with old
> bootloaders, which would encourage them to update their bootloader. By
> this time, hopefully, the manufacturers of OpenBlocks and Mirabox will
> have released updated bootloader versions, and we can tell users to
> upgrade. The upgrade process is easy and safe, because it takes place
> through the UART, as you know.
> 
> Then, another two release cycles later, we could remove the CP15 trick
> entirely.
> 
> So it's just a matter of living with this for about 4 release cycles,
> approximately a year.

This seems reasonable to me indeed!

> > > Conclusion: you can't classify on one side boards that are at 0xd0 and
> > > boards that are at 0xf1. It depends on *which* bootloader each
> > > particular instance of those boards will be using. Will it be a
> > > bootloader that complies with the "old" protocol (CP15 bit cleared and
> > > registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> > > 0xf1).
> > 
> > Just a point I'm thinking about, is it possible to detect the boot loader's
> > mode via ATAGs ? ATAGs are present very early as well (but maybe too late
> > already).
> 
> As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> ARM register that was used to pass the pointer to the ATAGS is now used
> to pass the pointer to the DTB in memory.

OK so one possibility could be to rely on this as well if we're certain there
is a 1:1 relation between DT support and new mapping. But at least you have
working code now with CP15, so let's not complexify the situation !

Best regards,
Willy



From jason at lakedaemon.net  Wed May 22 12:49:36 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 12:49:36 -0400
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130522184250.1d5f2f10@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
Message-ID: <20130522164936.GE31290@titan.lakedaemon.net>


Thomas,

On Wed, May 22, 2013 at 06:42:50PM +0200, Thomas Petazzoni wrote:
> On Wed, 22 May 2013 18:35:57 +0200, Willy Tarreau wrote:
> > On Wed, May 22, 2013 at 06:08:42PM +0200, Thomas Petazzoni wrote:
> > > Conclusion: you can't classify on one side boards that are at 0xd0 and
> > > boards that are at 0xf1. It depends on *which* bootloader each
> > > particular instance of those boards will be using. Will it be a
> > > bootloader that complies with the "old" protocol (CP15 bit cleared and
> > > registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> > > 0xf1).
> > 
> > Just a point I'm thinking about, is it possible to detect the boot loader's
> > mode via ATAGs ? ATAGs are present very early as well (but maybe too late
> > already).
> 
> As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> ARM register that was used to pass the pointer to the ATAGS is now used
> to pass the pointer to the DTB in memory.

So we could look for the ATAG magic or the dtb magic at that address,
then we know if we have an old or new bootloader...

thx,

Jason.


From morten.rasmussen at arm.com  Wed May 22 12:50:35 2013
From: morten.rasmussen at arm.com (Morten Rasmussen)
Date: Wed, 22 May 2013 17:50:35 +0100
Subject: [PATCH 09/14] sched: evaluate the activity level of the system
In-Reply-To: <1366910611-20048-10-git-send-email-vincent.guittot@linaro.org>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <1366910611-20048-10-git-send-email-vincent.guittot@linaro.org>
Message-ID: <20130522165035.GC4935@e103034-lin>

On Thu, Apr 25, 2013 at 06:23:25PM +0100, Vincent Guittot wrote:
> We evaluate the activity level of CPUs, groups and domains in order to define
> how many CPUs are required to handle the current activity.
> 
> Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
> ---
>  kernel/sched/fair.c |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 954adfd..234ecdd 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -3465,7 +3465,22 @@ static int check_pack_buddy(int cpu, struct task_struct *p)
>  		return true;
>  
>  	return false;
> +}
> +
> +static int get_cpu_activity(int cpu)
> +{
> +	struct rq *rq = cpu_rq(cpu);
> +	u32 sum = rq->avg.runnable_avg_sum;
> +	u32 period = rq->avg.runnable_avg_period;
> +
> +	sum = min(sum, period);
> +
> +	if (sum == period) {
> +		u32 overload = rq->nr_running > 1 ? 1 : 0;
> +		return power_of(cpu) + overload;
> +	}

Adding one to indicate cpu overload seems to work well in the cases that
I can think of. It may take some time to have effect if the overloaded
cpu is in a group with nearly overloaded cpus. Adding one won't enable
more cpus in another group until they have all reached overload.

Reaching sum == period takes quite a long time. Would it be an idea to
use sum*1024 >= period*1000 like you do in is_buddy_full()?

I think that would be more consistent since overloaded is essential the
same as full.

Cheers,
Morten

>  
> +	return (sum * power_of(cpu)) / period;
>  }
>  
>  /*
> @@ -4355,6 +4370,7 @@ struct sd_lb_stats {
>  	struct sched_group *busiest; /* Busiest group in this sd */
>  	struct sched_group *this;  /* Local group in this sd */
>  	unsigned long total_load;  /* Total load of all groups in sd */
> +	unsigned long total_activity;  /* Total activity of all groups in sd */
>  	unsigned long total_pwr;   /*	Total power of all groups in sd */
>  	unsigned long avg_load;	   /* Average load across all groups in sd */
>  
> @@ -4383,6 +4399,7 @@ struct sd_lb_stats {
>  struct sg_lb_stats {
>  	unsigned long avg_load; /*Avg load across the CPUs of the group */
>  	unsigned long group_load; /* Total load over the CPUs of the group */
> +	unsigned long group_activity; /* Total activity of the group */
>  	unsigned long sum_nr_running; /* Nr tasks running in the group */
>  	unsigned long sum_weighted_load; /* Weighted load of group's tasks */
>  	unsigned long group_capacity;
> @@ -4629,6 +4646,7 @@ static inline void update_sg_lb_stats(struct lb_env *env,
>  		}
>  
>  		sgs->group_load += load;
> +		sgs->group_activity += get_cpu_activity(i);
>  		sgs->sum_nr_running += nr_running;
>  		sgs->sum_weighted_load += weighted_cpuload(i);
>  		if (idle_cpu(i))
> @@ -4752,6 +4770,7 @@ static inline void update_sd_lb_stats(struct lb_env *env,
>  			return;
>  
>  		sds->total_load += sgs.group_load;
> +		sds->total_activity += sgs.group_activity;
>  		sds->total_pwr += sg->sgp->power;
>  
>  		/*
> -- 
> 1.7.9.5
> 
> 



From lee.jones at linaro.org  Wed May 22 12:53:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 May 2013 17:53:53 +0100
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130522155347.GJ1627@sirena.org.uk>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
Message-ID: <20130522165353.GB18714@gmail.com>

On Wed, 22 May 2013, Mark Brown wrote:

> On Wed, May 22, 2013 at 01:47:33PM +0100, Lee Jones wrote:
> > This patch fixes a bug introduced in the v3.10 merge window.
> > 
> > Some platforms will not want external registers. Rather than setting up
> > lots of different clauses in the core ab8500 regulator driver not to
> > call ab8500-ext init() we just won't pass the initialisation data from
> > platform code. This patch checks for it and if it's missing, we won't
> > register the external regulators.
> 
> This seems problematic - if the regulators are unused then they
> shouldn't have anything enabled in the constraints

Right, that's what this does.

"we just won't pass the initialisation data from platform code."

'initialisation data' == 'constraints'.

> and the regulator
> driver ought to be read only in which case it doesn't matter if it's
> running or not, the worst that should happen is that the state can be
> read back.  I'd therefore expect the fix here to be in the board side
> code that enables the regulators.

It's both.

>From the platform side we have stopped passing the external regulator
driver's constraints for Snowball:

https://lkml.org/lkml/2013/5/22/280

All I've done here is stop the ext driver from crapping out with the
misleading error "Configuration error: size mismatch", because a)
it's not an error, it's expected and b) It's not a size mismatch,
instead we have chosen to keep the constraints back in the Snowball
(and u8505) case.

Strictly speaking 'this' part of the fix is not an -rc candidate, but
without it someone could waste a great deal of time finding out why
this 'error' has appeared when it's not actually an error at all. Thus,
it would be more than helpful if it made it into the -rcs along with
the real platform fix.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
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From thomas.petazzoni at free-electrons.com  Wed May 22 12:57:57 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 18:57:57 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522164936.GE31290@titan.lakedaemon.net>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
Message-ID: <20130522185757.60091a66@skate>

Dear Jason Cooper,

On Wed, 22 May 2013 12:49:36 -0400, Jason Cooper wrote:

> > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > ARM register that was used to pass the pointer to the ATAGS is now used
> > to pass the pointer to the DTB in memory.
> 
> So we could look for the ATAG magic or the dtb magic at that address,
> then we know if we have an old or new bootloader...

No, because you can use an old bootloader, and still do some old-style
appended-DTB booting, in which case you have a new bootloader
(registers mapped at 0xf1), but you see the ATAG magic, which will make
you think you booted from an old bootloader (registers mapped at 0xd0).

For example, I'm currently booting alternatively with an old and a new
bootloader (to test that things work properly), and in both cases I'm
booting old style, DTB-appended, with ATAGs.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jgunthorpe at obsidianresearch.com  Wed May 22 12:59:08 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Wed, 22 May 2013 10:59:08 -0600
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <20130522131010.GB31290@titan.lakedaemon.net>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
Message-ID: <20130522165908.GB12320@obsidianresearch.com>

On Wed, May 22, 2013 at 09:10:10AM -0400, Jason Cooper wrote:

> iirc, our solution to this was to parse the ATAGs for the mac addr and
> update the appended dtb.  This way, module load and unload would work
> without loosing the mac address.  I believe Jason Gunthorpe has a patch
> to atags_to_fdt() for this...  This should allow us to get rid of the
> clocks hack.

Sorry, no, we don't use ATAGs here, our platforms start the kernel
with a correct DTB that has the correct mac address to use. My patch
was to have the driver accept it, and I think Sebastian has already
got that functionality...

Jason


From thomas.petazzoni at free-electrons.com  Wed May 22 13:00:04 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 19:00:04 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522164928.GD27348@1wt.eu>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164928.GD27348@1wt.eu>
Message-ID: <20130522190004.67880320@skate>

Dear Willy Tarreau,

On Wed, 22 May 2013 18:49:28 +0200, Willy Tarreau wrote:

> > I guess the Mirabox and OpenBlocks have been shipping for about 9-10
> > months now. Judging by the amount of e-mails are received about Mirabox
> > kernel (asking when PCIe support will be available, when NAND will be
> > available), there is definitely a certain number of people who have
> > those platforms in their hands.
> 
> Indeed, but either these people are running stock kernel on them and don't
> care, or they're ready to hack their box and should not be much frightened
> by a boot loader upgrade (especially since it's safe from the UART as we
> have found).

Yes, they could upgrade. But as of today, such upgrades do not even
exist for the Mirabox and OpenBlocks AX3 boards. So what do we tell to
those users?

Of course, one option is simply to have a kconfig option "I am booting
from an old bootloader", but with the CP15 trick, we've tried to make
this automatic so that users don't have to understand the kind of gory
details we are discussing right now.


> > 
> > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > ARM register that was used to pass the pointer to the ATAGS is now used
> > to pass the pointer to the DTB in memory.
> 
> OK so one possibility could be to rely on this as well if we're certain there
> is a 1:1 relation between DT support and new mapping. But at least you have
> working code now with CP15, so let's not complexify the situation !

There is absolutely no 1:1 relation between DT support and new mapping.

As I've just written in a reply to Jason Cooper, I'm currently using a
new bootloader (which uses the new mapping at 0xf1), but I'm booting
the kernel old style (appended DTB).

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jason at lakedaemon.net  Wed May 22 13:01:57 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 13:01:57 -0400
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <20130522165908.GB12320@obsidianresearch.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
Message-ID: <20130522170157.GF31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 10:59:08AM -0600, Jason Gunthorpe wrote:
> On Wed, May 22, 2013 at 09:10:10AM -0400, Jason Cooper wrote:
> 
> > iirc, our solution to this was to parse the ATAGs for the mac addr and
> > update the appended dtb.  This way, module load and unload would work
> > without loosing the mac address.  I believe Jason Gunthorpe has a patch
> > to atags_to_fdt() for this...  This should allow us to get rid of the
> > clocks hack.
> 
> Sorry, no, we don't use ATAGs here, our platforms start the kernel
> with a correct DTB that has the correct mac address to use. My patch
> was to have the driver accept it, and I think Sebastian has already
> got that functionality...

Yes, you're right.

thx,

Jason.


From w at 1wt.eu  Wed May 22 13:08:07 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Wed, 22 May 2013 19:08:07 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522190004.67880320@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164928.GD27348@1wt.eu> <20130522190004.67880320@skate>
Message-ID: <20130522170807.GE27348@1wt.eu>

On Wed, May 22, 2013 at 07:00:04PM +0200, Thomas Petazzoni wrote:
> Yes, they could upgrade. But as of today, such upgrades do not even
> exist for the Mirabox and OpenBlocks AX3 boards. So what do we tell to
> those users?

I was assuming these boot loaders do already exist if they're shipping
on some devices, but maybe not all yet.

> Of course, one option is simply to have a kconfig option "I am booting
> from an old bootloader", but with the CP15 trick, we've tried to make
> this automatic so that users don't have to understand the kind of gory
> details we are discussing right now.

Same as for ATAGS right now which are not necessarily the most obvious
setting for end users. Better keep the trick on by default if it's safe
enough. In fact I'm mostly concerned about the risk that it later breaks
for even newer boot loaders. But then we'll have more feedback to decide.

> > > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > > ARM register that was used to pass the pointer to the ATAGS is now used
> > > to pass the pointer to the DTB in memory.
> > 
> > OK so one possibility could be to rely on this as well if we're certain there
> > is a 1:1 relation between DT support and new mapping. But at least you have
> > working code now with CP15, so let's not complexify the situation !
> 
> There is absolutely no 1:1 relation between DT support and new mapping.
>
> As I've just written in a reply to Jason Cooper, I'm currently using a
> new bootloader (which uses the new mapping at 0xf1), but I'm booting
> the kernel old style (appended DTB).

OK, that was what I was wondering about. Sorry for having bothere you with
my questions but at least not it's much clearer that CP15 probably is the
only viable solution.

Best regards,
Willy



From florian.meier at koalo.de  Wed May 22 13:11:09 2013
From: florian.meier at koalo.de (Florian Meier)
Date: Wed, 22 May 2013 19:11:09 +0200
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CEF3C.4000502@wwwdotorg.org>
References: <519CD1CC.8070507@koalo.de> <519CE2B7.8080704@wwwdotorg.org>
 <519CED72.40406@koalo.de> <519CEF3C.4000502@wwwdotorg.org>
Message-ID: <519CFC2D.1020008@koalo.de>

On 22.05.2013 18:15, Stephen Warren wrote:
> On 05/22/2013 10:08 AM, Florian Meier wrote:
>> On 22.05.2013 17:22, Stephen Warren wrote:
>>> On 05/22/2013 08:10 AM, Florian Meier wrote:
>>>> This driver adds support for digital audio (I2S)
>>>> for the BCM2708 SoC that is used by the
>>>> Raspberry Pi. External audio codecs can be
>>>> connected to the Raspberry Pi via P5 header.
>>>>
>>>> It relies on cyclic DMA engine support for BCM2708
>>>> that is not included in this patch.
>>>
>>> This SoC is actually the BCM2835, so the files should be named for that.
>>
>> Actually, I changed the name several times and in the end I sticked to
>> https://github.com/raspberrypi/linux/issues/22
>> but if you think it is better to use BCM2835 I am happy to agree with
>> you and change it.
>>
>>> Upstream only uses device tree for BCM2835. Does this driver support DT?
>>> Where is the DT binding definition file?
>>
>> I have not accomplished to use the mainline kernel and DT with the
>> Raspberry Pi. Do you have any introductive information about how to do this?
> 
> Oh, so is this patch intended for the downstream Raspberry Pi Foundation
> kernel, or the upstream kernel?
> 
> The fact you haven't run it on the upstream kernel implies that you
> intend the patch to be applied to the downstream kernel.
> 
> The fact you sent the driver to all the upstream mailing lists implies
> that you intend the patch to be applied to the upstream kernel.
>
> BTW, I wrote a Google+ post on using the upstream kernel on the Pi:
> https://plus.google.com/101715070573995136397/posts/gWkwrfNfYVm

I chatted with Mark Brown about this issue and if I understood him
correctly he suggested to send it upstream anyway.

Either way, your blog post gives me great hope to get this running
tomorrow so this won't be an issue anymore.



From jason at lakedaemon.net  Wed May 22 13:13:59 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 13:13:59 -0400
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130522185757.60091a66@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
Message-ID: <20130522171359.GG31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 06:57:57PM +0200, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Wed, 22 May 2013 12:49:36 -0400, Jason Cooper wrote:
> 
> > > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > > ARM register that was used to pass the pointer to the ATAGS is now used
> > > to pass the pointer to the DTB in memory.
> > 
> > So we could look for the ATAG magic or the dtb magic at that address,
> > then we know if we have an old or new bootloader...
> 
> No, because you can use an old bootloader, and still do some old-style

Did you mean 'new bootloader'?

> appended-DTB booting, in which case you have a new bootloader
> (registers mapped at 0xf1), but you see the ATAG magic, which will make
> you think you booted from an old bootloader (registers mapped at 0xd0).
> 
> For example, I'm currently booting alternatively with an old and a new
> bootloader (to test that things work properly), and in both cases I'm
> booting old style, DTB-appended, with ATAGs.

Is this something users would experience?  I think it is fairly safe to
say that once dt-able bootloaders are shipped, they will provide a dtb.
So, OF_DT_MAGIC == new bootloader might hold true for users.

thx,

Jason.


From thomas.petazzoni at free-electrons.com  Wed May 22 13:14:20 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 19:14:20 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522170807.GE27348@1wt.eu>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164928.GD27348@1wt.eu> <20130522190004.67880320@skate>
 <20130522170807.GE27348@1wt.eu>
Message-ID: <20130522191420.1ef08f8d@skate>

Dear Willy Tarreau,

On Wed, 22 May 2013 19:08:07 +0200, Willy Tarreau wrote:
> On Wed, May 22, 2013 at 07:00:04PM +0200, Thomas Petazzoni wrote:
> > Yes, they could upgrade. But as of today, such upgrades do not even
> > exist for the Mirabox and OpenBlocks AX3 boards. So what do we tell to
> > those users?
> 
> I was assuming these boot loaders do already exist if they're shipping
> on some devices, but maybe not all yet.

The new bootloaders have started being offered by Marvell to
board/system manufacturers since only a few weeks or so, so besides
evaluation boards, there are not yet public products that use the new
bootloaders. But the vast majority of Armada 370 and Armada XP
platforms are still to be coming, and this vast majority will be using
the new bootloader.

> > Of course, one option is simply to have a kconfig option "I am booting
> > from an old bootloader", but with the CP15 trick, we've tried to make
> > this automatic so that users don't have to understand the kind of gory
> > details we are discussing right now.
> 
> Same as for ATAGS right now which are not necessarily the most obvious
> setting for end users. Better keep the trick on by default if it's safe
> enough. In fact I'm mostly concerned about the risk that it later breaks
> for even newer boot loaders. But then we'll have more feedback to decide.

As I suggested earlier, we can print a warning when people boot from an
old bootloader, and then down the road get rid of the trick. Or move it
under a conditional compilation so that the minority of remaining users
will have to enable this particular option. This will anyway be needed
if we want to go multiplatform with Dove, for example.

> OK, that was what I was wondering about. Sorry for having bothere you with
> my questions but at least not it's much clearer that CP15 probably is the
> only viable solution.

We've also gone through a lot of thinking about this problem, and we've
considered various options, and we came down to the following two
options:

 * Assume we're booted with a bootloader that has done the remapping at
   0xf1. Works for all new platforms, breaks all the older platforms,
   unless people upgrade their bootloaders.

 * Have a nicer way to handle the transition, and in this case, when
   you take into account all the complexities, the CP15 turned out to
   be the only really viable solution.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From florian.meier at koalo.de  Wed May 22 13:16:41 2013
From: florian.meier at koalo.de (Florian Meier)
Date: Wed, 22 May 2013 19:16:41 +0200
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <20130522163942.GQ1627@sirena.org.uk>
References: <519CD1CC.8070507@koalo.de> <20130522163942.GQ1627@sirena.org.uk>
Message-ID: <519CFD79.3050002@koalo.de>

On 22.05.2013 18:39, Mark Brown wrote:
> On Wed, May 22, 2013 at 04:10:20PM +0200, Florian Meier wrote:
> 
>> This driver adds support for digital audio (I2S)
>> for the BCM2708 SoC that is used by the
>> Raspberry Pi. External audio codecs can be
>> connected to the Raspberry Pi via P5 header.
> 
> Split this up into a patch series, for example one per CPU side driver
> and one per machine driver.  I've given the code a relatively quick run
> through here, it looks mostly sensible though DT would be nice but
> there's a few comments.
> 
>> +static inline void bcm2708_i2s_write_reg(struct bcm2708_i2s_dev *dev,
>> +					   int reg, u32 val)
>> +{
>> +	dev_dbg(dev->dev, "I2S write to register %p = %x\n",
>> +			dev->clk_base + reg, val);
>> +	__raw_writel(val, dev->i2s_base + reg);
>> +}
> 
> This all looks like you want to use regmap-mmio.........

Thank you for your comments! I will have a look at them and send a new
patch series taking them into account.
Before that I will create a patch for the DMA engine driver.



From g.liakhovetski at gmx.de  Wed May 22 13:22:59 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 22 May 2013 19:22:59 +0200 (CEST)
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <20130522143204.GE32012@verge.net.au>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
 <20130522143204.GE32012@verge.net.au>
Message-ID: <Pine.LNX.4.64.1305221911380.12715@axis700.grange>

Hi Simon

On Wed, 22 May 2013, Simon Horman wrote:

> On Fri, May 17, 2013 at 03:00:23PM +0200, Guennadi Liakhovetski wrote:
> > Hi Simon, Magnus
> > 
> > On Wed, 3 Apr 2013, Simon Horman wrote:
> > 
> > > From: Magnus Damm <damm at opensource.se>
> > > 
> > > Add LAN9220 support to the APE6EVM board using C and DT.
> > > At this point the PFC driver lacks DT bindings so to
> > > configure the PFC we use PINCTRL in C board code.
> > > 
> > > Signed-off-by: Magnus Damm <damm at opensource.se>
> > > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > > ---
> > >  arch/arm/boot/dts/r8a73a4-ape6evm.dts  |   23 ++++++++++++++++++-
> > >  arch/arm/mach-shmobile/board-ape6evm.c |   38 ++++++++++++++++++++++++++++++++
> > >  2 files changed, 60 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > index 833f703..f603c69 100644
> > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > @@ -16,7 +16,7 @@
> > >  	compatible = "renesas,ape6evm", "renesas,r8a73a4";
> > >  
> > >  	chosen {
> > > -		bootargs = "console=ttySC0,115200 ignore_loglevel";
> > > +		bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
> > >  	};
> > >  
> > >  	memory at 40000000 {
> > > @@ -24,8 +24,29 @@
> > >  		reg = <0 0x40000000 0 0x40000000>;
> > >  	};
> > >  
> > > +	ape6evm_fixed_3v3: fixedregulator at 0 {
> > > +		compatible = "regulator-fixed";
> > > +		regulator-name = "3V3";
> > > +		regulator-min-microvolt = <3300000>;
> > > +		regulator-max-microvolt = <3300000>;
> > > +		regulator-always-on;
> > > +	};
> > > +
> > >  	lbsc {
> > >  		#address-cells = <1>;
> > >  		#size-cells = <1>;
> > > +
> > > +		ethernet at 8000000 {
> > > +			compatible = "smsc,lan9118", "smsc,lan9115";
> > > +			reg = <0x08000000 0x1000>;
> > > +			interrupt-parent = <&irqc1>;
> > > +			interrupts = <8 0x4>;
> > > +			phy-mode = "mii";
> > > +			reg-io-width = <4>;
> > > +			smsc,irq-active-high;
> > > +			smsc,irq-push-pull;
> > > +			vdd33a-supply = <&ape6evm_fixed_3v3>;
> > > +			vddvario-supply = <&ape6evm_fixed_3v3>;
> > > +		};
> > >  	};
> > >  };
> > 
> > The above didn't work in my tests without this:
> > 
> > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
> > b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > index f603c69..4fb0102 100644
> > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > @@ -33,8 +33,10 @@
> >  	};
> >  
> >  	lbsc {
> > +		compatible = "simple-bus";
> >  		#address-cells = <1>;
> >  		#size-cells = <1>;
> > +		ranges = <0 0 0 0x80000000>;
> >  
> >  		ethernet at 8000000 {
> >  			compatible = "smsc,lan9118", "smsc,lan9115";
> > 
> 
> Could you please post this as a formal patch and indicate
> if you would like it included as a fix in v3.10 or not?

Can do that, sure, just thought maybe it would be better to fix the 
original patch. Besides, I wasn't sure what the correct values for 
"ranges" are, I just picked up something, that would be sufficient for 
ethernet. But if more devices are added to it in the future, maybe 
different ranges values would be needed. I think actually, lbsc should map 
the 3 BSC areas, so, the correct property would be

+		ranges = <0 0 0 0x14000000>;

> Also, I am curious to know what your tests are.

Just booting with NFS root. I think, anything involving ethernet. Without 
the "simple-bus" property the lbsc node doesn't get scanned, so, no device 
is added. Without "ranges" addresses cannot be mapped correctly.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From lars at metafoo.de  Wed May 22 13:26:53 2013
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Wed, 22 May 2013 19:26:53 +0200
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CD1CC.8070507@koalo.de>
References: <519CD1CC.8070507@koalo.de>
Message-ID: <519CFFDD.4080203@metafoo.de>

On 05/22/2013 04:10 PM, Florian Meier wrote:
[...]
> diff --git a/sound/soc/bcm2708/bcm2708-i2s.c b/sound/soc/bcm2708/bcm2708-i2s.c
> new file mode 100644
> index 0000000..a8e995f
> --- /dev/null
> +++ b/sound/soc/bcm2708/bcm2708-i2s.c
> @@ -0,0 +1,964 @@
[...]
> +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
> +			       struct snd_soc_dai *dai)
> +{
> +	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
> +
> +	if (!dev->first_stream) {
> +		dev->first_stream = substream;
> +
> +		/* should this still be running stop it */
> +		bcm2708_i2s_stop_clock(dev);
> +
> +		/* enable PCM block */
> +		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG, BCM2708_I2S_EN);
> +
> +		/*
> +		 * Disable STBY
> +		 * Requires at least 4 PCM clock cycles to take effect
> +		 */
> +		bcm2708_i2s_set_bits(dev, BCM2708_I2S_CS_A_REG,
> +				BCM2708_I2S_STBY);
> +	} else {
> +		struct snd_pcm_runtime *first_runtime =
> +			dev->first_stream->runtime;
> +
> +		/*
> +		 * This is the second stream open, so we need to impose
> +		 * sample size and sampling rate constraints.
> +		 * This is because frame length and clock cannot be specified
> +		 * seperately.
> +		 *
> +		 * Note that this can cause a race condition if the
> +		 * second stream is opened before the first stream is
> +		 * fully initialized.  We provide some protection by
> +		 * checking to make sure the first stream is
> +		 * initialized, but it's not perfect.  ALSA sometimes
> +		 * re-initializes the driver with a different sample
> +		 * rate or size.  If the second stream is opened
> +		 * before the first stream has received its final
> +		 * parameters, then the second stream may be
> +		 * constrained to the wrong sample rate or size.
> +		 *
> +		 * We will continue in case of failure and recheck the
> +		 * constraint in hw_params.
> +		 */
> +		if (!first_runtime->format) {
> +			dev_err(substream->pcm->card->dev,
> +					"Set format in %s stream first! "
> +					"Initialization may fail.\n",
> +					substream->stream ==
> +					SNDRV_PCM_STREAM_PLAYBACK
> +					? "capture" : "playback");
> +		} else {
> +			snd_pcm_hw_constraint_minmax(substream->runtime,
> +					SNDRV_PCM_HW_PARAM_FORMAT,
> +					first_runtime->format,
> +					first_runtime->format);
> +		}
> +
> +		if (!first_runtime->rate) {
> +			dev_err(substream->pcm->card->dev,
> +					"Set sampling rate in %s stream first! "
> +					"Initialization may fail!\n",
> +					substream->stream ==
> +					SNDRV_PCM_STREAM_PLAYBACK
> +					? "capture" : "playback");
> +		} else {
> +			snd_pcm_hw_constraint_minmax(substream->runtime,
> +					SNDRV_PCM_HW_PARAM_RATE,
> +					first_runtime->rate,
> +					first_runtime->rate);
> +		}

Setting the symmetric_rates lets the core take care of setting the proper
constraints on the rate. It probably makes sense to also add a
symmetric_formats since this isn't the only driver that has the requirement
that the formats for playback and capture match.

> +
> +		dev->second_stream = substream;
> +	}
> +
> +	snd_soc_dai_set_dma_data(dai, substream,
> +			&dev->dma_params[substream->stream]);
> +
> +	return 0;
> +}
> +
> +static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
> +		struct snd_soc_dai *dai)
> +{
> +	struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
> +
> +	bcm2708_i2s_stop(dev, substream);
> +
> +	if (dev->first_stream == substream)
> +		dev->first_stream = dev->second_stream;
> +
> +	dev->second_stream = NULL;
> +
> +	/* If both streams are stopped, disable module and clock */
> +	if (!dev->first_stream) {
> +		/* Disable the module */
> +		bcm2708_i2s_clear_bits(dev, BCM2708_I2S_CS_A_REG,
> +				BCM2708_I2S_EN);
> +
> +		/*
> +		 * Stopping clock is necessary, because stop does
> +		 * not stop the clock when SND_SOC_DAIFMT_CONT
> +		 */
> +		bcm2708_i2s_stop_clock(dev);
> +	}
> +}
[...]
> diff --git a/sound/soc/bcm2708/bcm2708-pcm.c b/sound/soc/bcm2708/bcm2708-pcm.c
> new file mode 100644
> index 0000000..4b3e688
> --- /dev/null
> +++ b/sound/soc/bcm2708/bcm2708-pcm.c
> @@ -0,0 +1,303 @@

I think you should be able to remove the bulk of this driver by using the
generic PCM dmaengine driver.

[...]
> +
> +#include "bcm2708-pcm.h"
> +
> +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
> +	.info			= SNDRV_PCM_INFO_MMAP |
> +				  SNDRV_PCM_INFO_MMAP_VALID |
> +				  SNDRV_PCM_INFO_INTERLEAVED |
> +				  SNDRV_PCM_INFO_PAUSE |
> +				  SNDRV_PCM_INFO_RESUME |
> +				  SNDRV_PCM_INFO_JOINT_DUPLEX |
> +				  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,

I don't think you actually support the last one, and neither pause and
resume are supported.

> +	.formats		= SNDRV_PCM_FMTBIT_S16_LE |
> +				  SNDRV_PCM_FMTBIT_S32_LE,
> +	.period_bytes_min	= 32,
> +	.period_bytes_max	= 64 * 1024,
> +	.periods_min		= 2,
> +	.periods_max		= 255,
> +	.buffer_bytes_max	= 128 * 1024,
> +};
> +
[...]


From sebastian.hesselbarth at gmail.com  Wed May 22 13:32:51 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 19:32:51 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130522165908.GB12320@obsidianresearch.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
Message-ID: <519D0143.1000203@gmail.com>

On 05/22/2013 06:59 PM, Jason Gunthorpe wrote:
> On Wed, May 22, 2013 at 09:10:10AM -0400, Jason Cooper wrote:
>> iirc, our solution to this was to parse the ATAGs for the mac addr and
>> update the appended dtb.  This way, module load and unload would work
>> without loosing the mac address.  I believe Jason Gunthorpe has a patch
>> to atags_to_fdt() for this...  This should allow us to get rid of the
>> clocks hack.
>
> Sorry, no, we don't use ATAGs here, our platforms start the kernel
> with a correct DTB that has the correct mac address to use. My patch
> was to have the driver accept it, and I think Sebastian has already
> got that functionality...

Not neccessary anyway, after talking Jason C in a Kirkwood-only
workaround I prepared a patch that reads mac address registers early
and stores it in the local-mac-address property.

Just tested on Dockstar with gated clocks and modular DT mv643xx_eth.

Will append to the DT mv643xx_eth patch set if a v5 will be required
or as single patch prior Jason C taking in the ARM part of it
otherwise.

Sebastian


From jason at lakedaemon.net  Wed May 22 13:35:05 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 13:35:05 -0400
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <519D0143.1000203@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
 <519D0143.1000203@gmail.com>
Message-ID: <20130522173505.GH31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 07:32:51PM +0200, Sebastian Hesselbarth wrote:
> On 05/22/2013 06:59 PM, Jason Gunthorpe wrote:
> >On Wed, May 22, 2013 at 09:10:10AM -0400, Jason Cooper wrote:
> >>iirc, our solution to this was to parse the ATAGs for the mac addr and
> >>update the appended dtb.  This way, module load and unload would work
> >>without loosing the mac address.  I believe Jason Gunthorpe has a patch
> >>to atags_to_fdt() for this...  This should allow us to get rid of the
> >>clocks hack.
> >
> >Sorry, no, we don't use ATAGs here, our platforms start the kernel
> >with a correct DTB that has the correct mac address to use. My patch
> >was to have the driver accept it, and I think Sebastian has already
> >got that functionality...
> 
> Not neccessary anyway, after talking Jason C in a Kirkwood-only
> workaround I prepared a patch that reads mac address registers early
> and stores it in the local-mac-address property.

Sweet!

> Just tested on Dockstar with gated clocks and modular DT mv643xx_eth.
> 
> Will append to the DT mv643xx_eth patch set if a v5 will be required
> or as single patch prior Jason C taking in the ARM part of it
> otherwise.

Please post, in-reply-to v4 is fine.

thx,

Jason.


From sebastian.hesselbarth at gmail.com  Wed May 22 13:42:36 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 19:42:36 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130522173505.GH31290@titan.lakedaemon.net>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com> <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net>
Message-ID: <519D038C.9000605@gmail.com>

On 05/22/2013 07:35 PM, Jason Cooper wrote:
> On Wed, May 22, 2013 at 07:32:51PM +0200, Sebastian Hesselbarth wrote:
>> On 05/22/2013 06:59 PM, Jason Gunthorpe wrote:
>>> On Wed, May 22, 2013 at 09:10:10AM -0400, Jason Cooper wrote:
>>>> iirc, our solution to this was to parse the ATAGs for the mac addr and
>>>> update the appended dtb.  This way, module load and unload would work
>>>> without loosing the mac address.  I believe Jason Gunthorpe has a patch
>>>> to atags_to_fdt() for this...  This should allow us to get rid of the
>>>> clocks hack.
>>>
>>> Sorry, no, we don't use ATAGs here, our platforms start the kernel
>>> with a correct DTB that has the correct mac address to use. My patch
>>> was to have the driver accept it, and I think Sebastian has already
>>> got that functionality...
>>
>> Not neccessary anyway, after talking Jason C in a Kirkwood-only
>> workaround I prepared a patch that reads mac address registers early
>> and stores it in the local-mac-address property.
>
> Sweet!
>
>> Just tested on Dockstar with gated clocks and modular DT mv643xx_eth.
>>
>> Will append to the DT mv643xx_eth patch set if a v5 will be required
>> or as single patch prior Jason C taking in the ARM part of it
>> otherwise.
>
> Please post, in-reply-to v4 is fine.

Hmm, maybe a little bit too early. While restoring the MAC address now
works, another bug arises which I guess is related with phy setup
and aneg.

Will investigate and update patch set accordingly.

Sebastian


From andrew at lunn.ch  Wed May 22 13:42:58 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 19:42:58 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130522174258.GO2824@lunn.ch>

On Tue, May 21, 2013 at 12:33:34PM +0200, Thomas Petazzoni wrote:
> On Marvell platforms, the "internal registers" is a window of 1 MB of
> the physical address space that contains all the registers for the
> various peripherals of the SoC (timers, interrupt controllers, GPIO
> controllers, Ethernet, etc.). The base address of this 1 MB window is
> configurable, and this base address is configured using a register
> that is itself part of this window.
> 
> All earlier families of Marvell EBU SoCs supported by Linux used
> 0xf1000000 as the base address of the internal registers window. For
> some reason, early versions of the Marvell 370/XP platforms used
> 0xd0000000 as the base address. This base address is set up by the
> bootloader. However, in order to keep as much physical address space
> to address RAM below the 4 GB limit, we had to switch the base address
> of the internal registers window back to 0xf1000000, and we wanted to
> achieve that without breaking existing platforms, where the bootloader
> was initially setting the base address to 0xd0000000. So the kernel is
> responsible for switching to 0xf1000000 when needed.
> 
> One particular bit of a CP15 register has been chosen to indicate
> whether we use an old bootloader (setting the address at 0xd0000000)
> or a new bootloader (setting the address at 0xf1000000). In the
> ->map_io() function, when the bit is already set, there is nothing to
> do, we are already using a new bootloader and internal registers are
> at 0xf1000000.
> 
> However, when the bit is not set, we do a static mapping of the
> register area that allows to change the internal register address, we
> change this address, and set this bit.
> 
> Note that this mechanism also needs cooperation from the earlyprintk
> addruart handler (in arch/arm/include/debug/mvebu.S). This is where
> things get complex: the CP15 bit that has been chosen gets reset to
> zero at the first call to the 'wfi' instruction. So it cannot be used
> during the entire life of the system. Instead, whenever the ->map_io()
> function has switched to the internal register space to the new
> address, it sets a global variable 'mvebu_switched_regs', which the
> earlyprintk reads. If it's true, then the move has already been done
> and there is no need to read the CP15 register. If
> 'mvebu_switched_regs' is false, we are before the register move, so we
> need to read the CP15 bit to find out whether we're being booted from
> an old bootloader (which mapped the register space at 0xd0000000) or a
> new bootloader (which mapped the register space at 0xf1000000).
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
>  arch/arm/boot/dts/armada-370.dtsi    |    2 +-
>  arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++++++--
>  arch/arm/mach-mvebu/armada-370-xp.c  |  104 ++++++++++++++++++++++++++++++++++
>  arch/arm/mach-mvebu/armada-370-xp.h  |    2 +-
>  5 files changed, 178 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 96a6bcd..1e7561e 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -33,7 +33,7 @@
>  		#size-cells = <1>;
>  		compatible = "simple-bus";
>  		interrupt-parent = <&mpic>;
> -		ranges = <0 0 0xd0000000 0x100000>;
> +		ranges = <0 0 0xf1000000 0x100000>;
>  
>  		internal-regs {
>  			compatible = "simple-bus";
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> index b2c1b5a..7ff9c1b 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -29,7 +29,7 @@
>  	};
>  
>  	soc {
> -		ranges = <0 0xd0000000 0x100000>;
> +		ranges = <0 0xf1000000 0x100000>;
>  		internal-regs {
>  			system-controller at 18200 {
>  				compatible = "marvell,armada-370-xp-system-controller";
> diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
> index df191af..dba702a 100644
> --- a/arch/arm/include/debug/mvebu.S
> +++ b/arch/arm/include/debug/mvebu.S
> @@ -5,20 +5,85 @@
>   *
>   * Lior Amsalem <alior at marvell.com>
>   * Gregory Clement <gregory.clement at free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
>  */
>  
> -#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> -#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000
> +#define ARMADA_370_XP_UART_PHYS_BASE_OLD	0xd0012000
> +#define ARMADA_370_XP_UART_PHYS_BASE_NEW	0xf1012000
> +#define ARMADA_370_XP_UART_VIRT_BASE_OLD	0xfec12000
> +#define ARMADA_370_XP_UART_VIRT_BASE_NEW	0xfebff000
>  
>  	.macro	addruart, rp, rv, tmp
> -	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
> -	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
> -	orr	\rp, \rp, #0x00012000
> -	orr	\rv, \rv, #0x00012000
> +
> +#ifndef ZIMAGE
> +	/*
> +	 * This loads the value of mvebu_switched_regs. We need a
> +	 * little bit of gymnastic here to handle the fact that the
> +	 * addruart code is duplicated in different places, and called
> +	 * sometimes with the MMU disabled, sometimes the MMU enabled.
> +	 *
> +	 * Notice that when this earlyprintk code is linked into the
> +	 * kernel decompressor (i.e ZIMAGE is defined), this code isn't
> +	 * compiled. The reason is because the global mvebu_switched_regs
> +	 * variable is not available in the decompressor code. At this
> +	 * early stage, we simply test the CP15 bit (below) to know where
> +	 * the internal registers are.
> +	 */
> +	adr	\rp, addruart_switched_regs_\@
> +	ldr	\rv, [\rp]
> +	sub	\rv, \rv, \rp
> +	ldr	\rp, [\rp, #4]
> +	sub	\tmp, \rp, \rv
> +	ldr	\rp, [\tmp, #0]
> +	cmp	\rp, #0
> +
> +	/* If we have already switched, then use the new register
> +	   address */
> +	bne	addruart_new_\@
> +#endif
> +
> +	/*
> +	 * We haven't switched the register location, so test the CP15
> +	 * register bit to find whether we are:
> +	 * - with an old bootloader setting the base address to
> +	 *   0xd0000000
> +	 * - with a new bootloader that has already set the
> +	 *   base address to 0xf1000000
> +	 * We adapt the physical address returned depending on the
> +	 * value of this bit, but also the virtual address, because we
> +	 * can't remap the old physical address and the new physical
> +	 * address at the same location.
> +	 */
> +	mrc	p15, 0, \tmp, c5, c0, 0
> +	and	\tmp, \tmp, #(1 << 11)
> +	cmp	\tmp, #0
> +	bne	addruart_new_\@
> +
> +addruart_old_\@:
> +	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_OLD
> +	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_OLD
> +	b	addruart_out_\@
> +addruart_new_\@:
> +	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_NEW
> +	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_NEW
> +	b	addruart_out_\@
> +
> +#ifndef ZIMAGE
> +	/*
> +	 * Global variable mvebu_switched_regs not visible in the
> +	 * decompressor code
> +	 */
> +	.align
> +addruart_switched_regs_\@:
> +	.long	.
> +	.long	mvebu_switched_regs
> +#endif
> +
> +addruart_out_\@:
>  	.endm
>  
>  #define UART_SHIFT	2
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
> index 90cc0e8..c56875e 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.c
> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
> @@ -29,8 +29,112 @@
>  #include "common.h"
>  #include "coherency.h"
>  
> +/*
> + * Note on the internal register address.
> + *
> + * On Marvell platforms, the "internal registers" is a window of 1 MB
> + * of the physical address space that contains all the registers for
> + * the various peripherals of the SoC (timers, interrupt controllers,
> + * GPIO controllers, Ethernet, etc.). The base address of this 1 MB
> + * window is configurable, and this base address is configured using a
> + * register that is itself part of this window.
> + *
> + * All earlier families of Marvell EBU SoCs supported by Linux used
> + * 0xf1000000 as the base address of the internal registers
> + * window. For some reason, early versions of the Marvell 370/XP
> + * platforms used 0xd0000000 as the base address. This base address is
> + * set up by the bootloader. However, in order to keep as much
> + * physical address space to address RAM below the 4 GB limit, we had
> + * to switch the base address of the internal registers window back to
> + * 0xf1000000, and we wanted to achieve that without breaking existing
> + * platforms, where the bootloader was initially setting the base
> + * address to 0xd0000000. So the kernel is responsible for switching
> + * to 0xf1000000 when needed.
> + *
> + * One particular bit of a CP15 register has been chosen to indicate
> + * whether we use an old bootloader (setting the address at
> + * 0xd0000000) or a new bootloader (setting the address at
> + * 0xf1000000). In the ->map_io() function, when the bit is already
> + * set, there is nothing to do, we are already using a new bootloader
> + * and internal registers are at 0xf1000000.
> + *
> + * However, when the bit is not set, we do a static mapping of the
> + * register area that allows to change the internal register address,
> + * we change this address, and set this bit.

Hi Thomas

Please could you explain this "and set this bit".

If i understand the comment correctly, you are talking about the bit
in CP15. Why is it necessary to set it, since at the next WFI its
going to get cleared. I also don't actually see any code doing the
setting of this bit.

> + *
> + * Note that this mechanism also needs cooperation from the
> + * earlyprintk addruart handler (in arch/arm/include/debug/mvebu.S)
> + * and the early secondary CPU initialization code (in
> + * arch/arm/mach-mvebu/headsmp.S).
> + */
> +
> +#define NEW_INTERNAL_REGS_ADDR  0xf1000000
> +#define OLD_INTERNAL_REGS_ADDR  0xd0000000
> +#define MBUS_OLD_PHYS_ADDR      (OLD_INTERNAL_REGS_ADDR + 0x20000)
> +#define MBUS_OLD_VIRT_ADDR      0xfebfe000
> +#define  MBUS_INTERNAL_REGS_ADDR      0x80
> +
> +/*
> + * We really want this variable to be part of the .data section,
> + * because it gets accessed by the earlyprintk code before BSS gets
> + * initialized to zero. This variable indicates whether the switch to
> + * the new register has taken place or not. It is needed because the
> + * CP15 bit used by the bootloader to tell the kernel where the
> + * registers are mapped is cleared to 0 at the first 'wfi'
> + * instruction. So we can't use it for the entire life of the system,
> + * and we instead use this boolean to indicate to the earlyprintk code
> + * that the switch has occured and it doesn't need to look at the CP15
> + * bit anymore.
> + */
> +unsigned int __section(.data) mvebu_switched_regs = 0;
> +
> +/*
> + * Detect if we're running an old bootloader that has set the physical
> + * base address of internal registers to 0xd0000000
> + */
> +static int armada_370_xp_has_old_bootloader(void)
> +{
> +	u32 val;
> +	asm volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(val));
> +	return !(val & BIT(11));
> +}
> +
>  static void __init armada_370_xp_map_io(void)
>  {
> +	if (armada_370_xp_has_old_bootloader()) {
> +		struct map_desc desc;
> +		void __iomem *mbus = IOMEM(MBUS_OLD_VIRT_ADDR);
> +
> +		desc.virtual = MBUS_OLD_VIRT_ADDR;
> +		desc.pfn     = __phys_to_pfn(MBUS_OLD_PHYS_ADDR);
> +		desc.length  = PAGE_SIZE;
> +		desc.type    = MT_DEVICE;
> +
> +		/*
> +		 * Map the area that contains the registers that
> +		 * allows to change the base address of internal
> +		 * registers.
> +		 */
> +		iotable_init(&desc, 1);
> +
> +		/*
> +		 * Change the physical base address of the
> +		 * registers. From now on, and until
> +		 * debug_ll_io_init() is called below, it is not
> +		 * possible to do any print, because earlyprintk will
> +		 * not work.

Is its "not work" or "locks up the CPU as dead as a Dodo?".

Thanks
	Andrew

> +		 */
> +		writel(NEW_INTERNAL_REGS_ADDR, mbus + MBUS_INTERNAL_REGS_ADDR);
> +	}
> +
> +	/*
> +	 * Either the registers have been switched by the above code,
> +	 * or the bootloader had already set the register space at the
> +	 * right location. In both cases, tell the earlyprintk code it
> +	 * can now use the new location.
> +	 */
> +	mvebu_switched_regs = 1;
> +
>  	debug_ll_io_init();
>  }
>  
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
> index 585e147..ff9adc4 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.h
> +++ b/arch/arm/mach-mvebu/armada-370-xp.h
> @@ -15,7 +15,7 @@
>  #ifndef __MACH_ARMADA_370_XP_H
>  #define __MACH_ARMADA_370_XP_H
>  
> -#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> +#define ARMADA_370_XP_REGS_PHYS_BASE	0xf1000000
>  
>  /* These defines can go away once mvebu-mbus has a DT binding */
>  #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
> -- 
> 1.7.9.5
> 


From broonie at kernel.org  Wed May 22 13:45:16 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 22 May 2013 12:45:16 -0500
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130522165353.GB18714@gmail.com>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
 <20130522165353.GB18714@gmail.com>
Message-ID: <20130522174516.GT1627@sirena.org.uk>

On Wed, May 22, 2013 at 05:53:53PM +0100, Lee Jones wrote:
> On Wed, 22 May 2013, Mark Brown wrote:

> > running or not, the worst that should happen is that the state can be
> > read back.  I'd therefore expect the fix here to be in the board side
> > code that enables the regulators.

> It's both.

> From the platform side we have stopped passing the external regulator
> driver's constraints for Snowball:

> https://lkml.org/lkml/2013/5/22/280

> All I've done here is stop the ext driver from crapping out with the
> misleading error "Configuration error: size mismatch", because a)
> it's not an error, it's expected and b) It's not a size mismatch,
> instead we have chosen to keep the constraints back in the Snowball
> (and u8505) case.

OK, so the regulator driver is buggy and insisting on having constraints
passed in for every regulator then?
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From jason at lakedaemon.net  Wed May 22 13:48:15 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 13:48:15 -0400
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <519D038C.9000605@gmail.com>
References: <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
 <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net>
 <519D038C.9000605@gmail.com>
Message-ID: <20130522174815.GI31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 07:42:36PM +0200, Sebastian Hesselbarth wrote:
> On 05/22/2013 07:35 PM, Jason Cooper wrote:
> >On Wed, May 22, 2013 at 07:32:51PM +0200, Sebastian Hesselbarth wrote:
> >>On 05/22/2013 06:59 PM, Jason Gunthorpe wrote:
> >>>On Wed, May 22, 2013 at 09:10:10AM -0400, Jason Cooper wrote:
> >>>>iirc, our solution to this was to parse the ATAGs for the mac addr and
> >>>>update the appended dtb.  This way, module load and unload would work
> >>>>without loosing the mac address.  I believe Jason Gunthorpe has a patch
> >>>>to atags_to_fdt() for this...  This should allow us to get rid of the
> >>>>clocks hack.
> >>>
> >>>Sorry, no, we don't use ATAGs here, our platforms start the kernel
> >>>with a correct DTB that has the correct mac address to use. My patch
> >>>was to have the driver accept it, and I think Sebastian has already
> >>>got that functionality...
> >>
> >>Not neccessary anyway, after talking Jason C in a Kirkwood-only
> >>workaround I prepared a patch that reads mac address registers early
> >>and stores it in the local-mac-address property.
> >
> >Sweet!
> >
> >>Just tested on Dockstar with gated clocks and modular DT mv643xx_eth.
> >>
> >>Will append to the DT mv643xx_eth patch set if a v5 will be required
> >>or as single patch prior Jason C taking in the ARM part of it
> >>otherwise.
> >
> >Please post, in-reply-to v4 is fine.
> 
> Hmm, maybe a little bit too early. While restoring the MAC address now
> works, another bug arises which I guess is related with phy setup
> and aneg.
> 
> Will investigate and update patch set accordingly.

Cool, chances are, we should be able to take that patch in by itself for
this merge window...

thx,

Jason.


From thomas.petazzoni at free-electrons.com  Wed May 22 13:59:42 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 19:59:42 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <20130522174258.GO2824@lunn.ch>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522174258.GO2824@lunn.ch>
Message-ID: <20130522195942.33ff1131@skate>

Dear Andrew Lunn,

On Wed, 22 May 2013 19:42:58 +0200, Andrew Lunn wrote:

> > + * However, when the bit is not set, we do a static mapping of the
> > + * register area that allows to change the internal register address,
> > + * we change this address, and set this bit.
> 
> Hi Thomas
> 
> Please could you explain this "and set this bit".
> 
> If i understand the comment correctly, you are talking about the bit
> in CP15. Why is it necessary to set it, since at the next WFI its
> going to get cleared. I also don't actually see any code doing the
> setting of this bit.

Nice catch. This is a left-over from a previous implementation. For
experimentation purposes, I have been using a different CP15 bit that
was not getting cleared on WFIs, so once the register address switch was
done, I was setting this bit to indicate to further invocations of
earlyprintk that the switch has occurred.

In the mean time, the code has been changed to use the final bit used
by Marvell bootloaders, and this one gets cleared at the next WFI. So
I'm now using a global variable instead to indicate that the switch has
occurred making this comment inaccurate.

I'll fix that in the next revision of this patch set.


> > +		/*
> > +		 * Change the physical base address of the
> > +		 * registers. From now on, and until
> > +		 * debug_ll_io_init() is called below, it is not
> > +		 * possible to do any print, because earlyprintk will
> > +		 * not work.
> 
> Is its "not work" or "locks up the CPU as dead as a Dodo?".

locks up the CPU as a Dodo: you have switched the registers from 0xd0
to 0xf1, but the earlyprintk virtual mapping still points to 0xd0. So
if you try to do a printk, it will call earlyprintk, which will use the
old virtual mapping (since mvebu_switched_regs isn't set yet, it will
be at the next line), and that will make it use the old physical
address of the UART. So you'll write to 0xd0012000, and you're dead.

Thanks for the review!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From matt.porter at linaro.org  Wed May 22 14:01:14 2013
From: matt.porter at linaro.org (Matt Porter)
Date: Wed, 22 May 2013 14:01:14 -0400
Subject: [PATCH V2 2/2] ARM: mmc: bcm281xx SDHCI driver (dt mods)
In-Reply-To: <1368200883-15668-2-git-send-email-csd@broadcom.com>
References: <1368200883-15668-1-git-send-email-csd@broadcom.com>
 <1368200883-15668-2-git-send-email-csd@broadcom.com>
Message-ID: <20130522180114.GA8235@beef>

Hi Christian,

On Fri, May 10, 2013 at 08:48:03AM -0700, Christian Daudt wrote:
> Add SDHCI driver for the Broadcom 281xx SoCs. Also
> add bindings for it into bcm281xx dts files.

Since this is independent of the driver, the description should probably
be updated to reflect that this is just the DT support for the bcm281xx
(or kona) SDHCI hw.

> Changes from V1:
>  - split original patch into 2, one for driver and this one for dt
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> 
> diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
> new file mode 100644
> index 0000000..ad1c4bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
> @@ -0,0 +1,16 @@
> +Broadcom BCM281xx SDHCI driver

s/driver//

> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties in the bcm281xx driver.

The hardware binding should not mention the supporting driver. Borrowing
from other examples, you'd want something more like:

"
This file documents differences between the core properties described
by mmc.txt and the properties that represent the bcm281xx [kona?] SDHCI.
"

-Matt


From will.deacon at arm.com  Wed May 22 14:03:32 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 22 May 2013 19:03:32 +0100
Subject: [PATCH v2] arm64: extable: sort the exception table at build time
Message-ID: <1369245812-27231-1-git-send-email-will.deacon@arm.com>

As is done for other architectures, sort the exception table at
build-time rather than during boot.

Since sortextable appears to be a standalone C program relying on the
host elf.h to provide EM_AARCH64, I've had to add a conditional check in
order to allow cross-compilation on machines that aren't running a
bleeding-edge libc-dev.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm64/Kconfig              |  1 +
 arch/arm64/kernel/vmlinux.lds.S | 10 +---------
 scripts/sortextable.c           |  5 +++++
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 56b3f6d..c3e3a17 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -7,6 +7,7 @@ config ARM64
 	select ARM_AMBA
 	select ARM_ARCH_TIMER
 	select ARM_GIC
+	select BUILDTIME_EXTABLE_SORT
 	select CLONE_BACKWARDS
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 3fae2be..5e06a17 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -56,7 +56,7 @@ SECTIONS
 	}
 
 	RO_DATA(PAGE_SIZE)
-
+	EXCEPTION_TABLE(8)
 	_etext = .;			/* End of text and rodata section */
 
 	. = ALIGN(PAGE_SIZE);
@@ -99,14 +99,6 @@ SECTIONS
 		READ_MOSTLY_DATA(64)
 
 		/*
-		 * The exception fixup table (might need resorting at runtime)
-		 */
-		. = ALIGN(32);
-		__start___ex_table = .;
-		*(__ex_table)
-		__stop___ex_table = .;
-
-		/*
 		 * and the usual data section
 		 */
 		DATA_DATA
diff --git a/scripts/sortextable.c b/scripts/sortextable.c
index 1f10e89..f9ce116 100644
--- a/scripts/sortextable.c
+++ b/scripts/sortextable.c
@@ -31,6 +31,10 @@
 #include <tools/be_byteshift.h>
 #include <tools/le_byteshift.h>
 
+#ifndef EM_AARCH64
+#define EM_AARCH64	183
+#endif
+
 static int fd_map;	/* File descriptor for file being modified. */
 static int mmap_failed; /* Boolean flag. */
 static void *ehdr_curr; /* current ElfXX_Ehdr *  for resource cleanup */
@@ -249,6 +253,7 @@ do_file(char const *const fname)
 		custom_sort = sort_relative_table;
 		break;
 	case EM_ARM:
+	case EM_AARCH64:
 	case EM_MIPS:
 		break;
 	}  /* end switch */
-- 
1.8.2.2



From thomas.petazzoni at free-electrons.com  Wed May 22 14:05:13 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 20:05:13 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522171359.GG31290@titan.lakedaemon.net>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522171359.GG31290@titan.lakedaemon.net>
Message-ID: <20130522200513.5e266edc@skate>

Dear Jason Cooper,

On Wed, 22 May 2013 13:13:59 -0400, Jason Cooper wrote:

> > On Wed, 22 May 2013 12:49:36 -0400, Jason Cooper wrote:
> > 
> > > > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > > > ARM register that was used to pass the pointer to the ATAGS is now used
> > > > to pass the pointer to the DTB in memory.
> > > 
> > > So we could look for the ATAG magic or the dtb magic at that address,
> > > then we know if we have an old or new bootloader...
> > 
> > No, because you can use an old bootloader, and still do some old-style
> 
> Did you mean 'new bootloader'?

Gaah, yes, of course. Getting myself confused with all this old/new
discussion :)

"No, because you can use a new bootloader, and still do some
old-style..."

> > appended-DTB booting, in which case you have a new bootloader
> > (registers mapped at 0xf1), but you see the ATAG magic, which will make
> > you think you booted from an old bootloader (registers mapped at 0xd0).
> > 
> > For example, I'm currently booting alternatively with an old and a new
> > bootloader (to test that things work properly), and in both cases I'm
> > booting old style, DTB-appended, with ATAGs.
> 
> Is this something users would experience?  I think it is fairly safe to
> say that once dt-able bootloaders are shipped, they will provide a dtb.
> So, OF_DT_MAGIC == new bootloader might hold true for users.

We could be tempted to say that, but since what users trying to do this
would experience is a completely silent kernel, no message, nothing,
I'm not sure I like this too much.

Especially since users of the mainline kernel for Marvell platforms
have become used to do the appended DTB gymnastic, it's pretty likely
that they will do the same gymnastic when they'll move to more recent
Marvell platforms or bootloaders, not necessarily knowing that the
bootloader is now capable of doing DT-based booting.

Therefore, I continue to believe that making the assumptions that being
booted from DT == new bootloader == new mapping, being booted from ATAGS
== old boot == old mapping, should not be made.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jason at lakedaemon.net  Wed May 22 14:09:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 14:09:35 -0400
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130522200513.5e266edc@skate>
References: <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522171359.GG31290@titan.lakedaemon.net>
 <20130522200513.5e266edc@skate>
Message-ID: <20130522180935.GJ31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 08:05:13PM +0200, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Wed, 22 May 2013 13:13:59 -0400, Jason Cooper wrote:
> 
> > > On Wed, 22 May 2013 12:49:36 -0400, Jason Cooper wrote:
> > > 
> > > > > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > > > > ARM register that was used to pass the pointer to the ATAGS is now used
> > > > > to pass the pointer to the DTB in memory.
> > > > 
> > > > So we could look for the ATAG magic or the dtb magic at that address,
> > > > then we know if we have an old or new bootloader...
> > > 
> > > No, because you can use an old bootloader, and still do some old-style
> > 
> > Did you mean 'new bootloader'?
> 
> Gaah, yes, of course. Getting myself confused with all this old/new
> discussion :)
> 
> "No, because you can use a new bootloader, and still do some
> old-style..."
> 
> > > appended-DTB booting, in which case you have a new bootloader
> > > (registers mapped at 0xf1), but you see the ATAG magic, which will make
> > > you think you booted from an old bootloader (registers mapped at 0xd0).
> > > 
> > > For example, I'm currently booting alternatively with an old and a new
> > > bootloader (to test that things work properly), and in both cases I'm
> > > booting old style, DTB-appended, with ATAGs.
> > 
> > Is this something users would experience?  I think it is fairly safe to
> > say that once dt-able bootloaders are shipped, they will provide a dtb.
> > So, OF_DT_MAGIC == new bootloader might hold true for users.
> 
> We could be tempted to say that, but since what users trying to do this
> would experience is a completely silent kernel, no message, nothing,
> I'm not sure I like this too much.

Ok, I buy that.  Having stared at blank terminals many times, that's
not cool. :(  It really hurts to hear the HD spin down too.  It just
sounds like something died a horrible agonizing death.

thx,

Jason.


From will.deacon at arm.com  Wed May 22 14:09:42 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 22 May 2013 19:09:42 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130522084744.GD14322@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <CAL_JsqLSC2QgMdTGtH5G_F5SYjA3Hs--jMmxBES=fqGLwapptQ@mail.gmail.com>
 <20130522084744.GD14322@arm.com>
Message-ID: <20130522180942.GK16361@mudshark.cambridge.arm.com>

On Wed, May 22, 2013 at 09:47:44AM +0100, Catalin Marinas wrote:
> On Tue, May 21, 2013 at 07:48:35PM +0100, Rob Herring wrote:
> > On Mon, May 20, 2013 at 9:18 AM, Catalin Marinas
> > <catalin.marinas at arm.com> wrote:
> > > On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
> > >> CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
> > >> userspace software can avoid having to use the exclusive variants of
> > >> these instructions if they wish.
> > >>
> > >> This patch advertises the atomicity of these instructions via the
> > >> hwcaps, so userspace can detect this CPU feature.
> > >>
> > >> Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
> > >> Signed-off-by: Will Deacon <will.deacon at arm.com>
> > > ...
> > >> +
> > >> +     /* LPAE implies atomic ldrd/strd instructions */
> > >> +     vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
> > >> +     if (vmsa >= 5)
> > >> +             elf_hwcap |= HWCAP_LPAE;
> > >
> > > As I mentioned in the past, I don't agree with exposing the "LPAE"
> > > feature to user-space, it's not a feature that user space should care
> > > about. An atomic double hwcap is better and you can even make this per
> > > CPU via __v7_proc.
> > 
> > How does userspace know whether to install a non-LPAE or LPAE kernel
> > in a generic way?
> 
> This is a valid reason to expose LPAE to user, though elf_hwcap sounds a
> bit strange.

In lieu of anything else, do you mind if I continue with the patch as it
stands?

Will


From thomas.petazzoni at free-electrons.com  Wed May 22 14:13:23 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 20:13:23 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522180935.GJ31290@titan.lakedaemon.net>
References: <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522171359.GG31290@titan.lakedaemon.net>
 <20130522200513.5e266edc@skate>
 <20130522180935.GJ31290@titan.lakedaemon.net>
Message-ID: <20130522201323.1c7ba6e0@skate>

Dear Jason Cooper,

On Wed, 22 May 2013 14:09:35 -0400, Jason Cooper wrote:

> > > Is this something users would experience?  I think it is fairly safe to
> > > say that once dt-able bootloaders are shipped, they will provide a dtb.
> > > So, OF_DT_MAGIC == new bootloader might hold true for users.
> > 
> > We could be tempted to say that, but since what users trying to do this
> > would experience is a completely silent kernel, no message, nothing,
> > I'm not sure I like this too much.
> 
> Ok, I buy that.  Having stared at blank terminals many times, that's
> not cool. :(  It really hurts to hear the HD spin down too.  It just
> sounds like something died a horrible agonizing death.

The other day, I was precisely trying to boot a kernel in a DT-way from
a bootloader that was in fact not DT capable (but I hadn't realized
that). And the kernel had no earlyprintk support. It was really
frustrating. No message at all, nothing. If we can avoid that
experience to the users of the Marvell platforms, I'd prefer. Something
that fails later on during boot is less problematic because at least
you get an error message that you can copy/paste in Google, or that
gives you some initial clue of what's going on. But a completely silent
kernel is terrifying.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From nm at ti.com  Wed May 22 14:18:33 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 22 May 2013 13:18:33 -0500
Subject: [RFC PATCH 0/4] regulator/OMAP: support VC/VP support in dts
Message-ID: <1369246717-4167-1-git-send-email-nm@ti.com>

Hi,

Texas Instrument's OMAP Processor have a dedicated hardware module
which is customised to operate with Power Management IC(PMIC) over an dedicated
I2C. The communication involves a few SoC internal modules as follows:
PMIC - The power management chip on the dedicated I2C (sometimes called I2C_SR)
Voltage controller - consists of an hardware i2c controller and interface
customized for PMICs. VC consists of multiple VC Channels, each channel
representing a variable voltage rail supply to the SoC.
Voltage Processor(VP) - controls the voltage requests to VC channel
SmartReflex(Adaptive Voltage control) - (SR/AVS)- specialized hardware block
which can dynamically control device voltage without software intervention. This
module communicates with VP.

In the simplest view, a simple voltage set operation is as follows:
Vp->VC Channel -> VC -> PMIC

Note, there may be dedicated PMIC per variable voltage rail OR PMICs which
provide control for multiple SMPS supplying variable rails etc.

In addition, there is an Adaptive Voltage Control (AVS) technique called
SmartReflex which can operate (in a configuration called continous monitoring
hardware loop or class 3 mode of operation), in which the SmartReflex block
communicates with Voltage Processor.

We have an OMAP specific implementation in arch/arm/mach-omap2 which does not
tree VC/VP or PMIC as Linux devices, but as data which is configured as needed.

In this series, we introduce replacement approach which has support for only
Device Tree as OMAP is transitioning completely away from non-DT approach.

As an overview, the following approach is taken.

PMIC is now the regulator driver - generic omap-pmic-regulator (patch #1)
Voltage controller and voltage controller channel is handled by
driver/power/avs/omap_vc.c

Voltage processor is handled by driver/power/avs/omap_vp.c

Benefit of using drivers/power/avs is also to set the foundation to convert
SmartReflex AVS into device tree based solution. (next stage).

S/w dependency is as follows:
Voltage controller <- Voltage Processor
Voltage Processor registers with OMAP_PMIC it's controller operations
OMAP_PMIC uses the controller operations to call vp which in turn calls VC to
setup the communication chain.

This allows us to maintain this as a module if needed as well (something our
existing implementation was not capable  of doing).

The series is also available here:
https://github.com/nmenon/linux-2.6-playground/commits/devel/vc-vp-regulator-rfc
git://github.com/nmenon/linux-2.6-playground.git
branch: devel/vc-vp-regulator-rfc

This depends on a few patches for cpufreq/clock node i added in, merged with
3.10-rc2 master and a intermediate GPIO fix from Dan that I picked up available in
branch devel/vc-vp-base

Note: 
1. AVS device tree conversion will have to depend on this due to dependency on VP
2. Clock node strategy used here is based on implementation I had posted here:
	http://marc.info/?t=136804008400001&r=1&w=2
3. I chose OMAP4460 based PandaBoard ES platform as my development platform
   and patch #4 in this series is an attempt to showcase how it will look like.
   Rationale: weird PMIC configuration was used in PandaBoard ES. Ability to
   handle that platform makes introduction to other platforms/SoCs trivial.
   example patch for 4430 sdp: http://pastebin.com/SkAGB273
4. Once this approach is agreed upon, I can do the dts changes for all SoCs
   OMAP3-5 and will post a formal series.

Related defects:
  https://bugzilla.kernel.org/show_bug.cgi?id=58541
  https://bugzilla.kernel.org/show_bug.cgi?id=58611

Nishanth Menon (4):
  regulator: Introduce OMAP regulator to control PMIC over VC/VP
  PM / AVS: Introduce support for OMAP Voltage Controller(VC) with
    device tree nodes
  PM / AVS: Introduce support for OMAP Voltage Processor(VP) with
    device tree nodes
  HACK: OMAP4460/TPS/TWL/PandaBoardES - Enable VP regulator for cpufreq

 .../devicetree/bindings/power/omap-vc.txt          |   99 ++
 .../devicetree/bindings/power/omap-vp.txt          |   39 +
 .../bindings/regulator/omap-pmic-regulator.txt     |  121 ++
 arch/arm/boot/dts/omap4-panda-es.dts               |   55 +-
 arch/arm/boot/dts/omap4.dtsi                       |   84 ++
 arch/arm/boot/dts/omap4460.dtsi                    |    1 +
 arch/arm/boot/dts/tps62361.dtsi                    |   90 ++
 arch/arm/boot/dts/twl6030.dtsi                     |   68 +
 drivers/power/avs/Kconfig                          |   15 +
 drivers/power/avs/Makefile                         |   20 +
 drivers/power/avs/omap_vc.c                        | 1508 ++++++++++++++++++++
 drivers/power/avs/omap_vc.h                        |   67 +
 drivers/power/avs/omap_vp.c                        |  886 ++++++++++++
 drivers/regulator/Kconfig                          |   12 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/omap-pmic-regulator.c            |  554 +++++++
 include/linux/regulator/omap-pmic-regulator.h      |  147 ++
 17 files changed, 3763 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/power/omap-vc.txt
 create mode 100644 Documentation/devicetree/bindings/power/omap-vp.txt
 create mode 100644 Documentation/devicetree/bindings/regulator/omap-pmic-regulator.txt
 create mode 100644 arch/arm/boot/dts/tps62361.dtsi
 create mode 100644 drivers/power/avs/omap_vc.c
 create mode 100644 drivers/power/avs/omap_vc.h
 create mode 100644 drivers/power/avs/omap_vp.c
 create mode 100644 drivers/regulator/omap-pmic-regulator.c
 create mode 100644 include/linux/regulator/omap-pmic-regulator.h

Regards,
Nishanth Menon
-- 
1.7.9.5


From nm at ti.com  Wed May 22 14:18:37 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 22 May 2013 13:18:37 -0500
Subject: [RFC PATCH 4/4] HACK: OMAP4460/TPS/TWL/PandaBoardES - Enable VP
 regulator for cpufreq
In-Reply-To: <1369246717-4167-1-git-send-email-nm@ti.com>
References: <1369246717-4167-1-git-send-email-nm@ti.com>
Message-ID: <1369246717-4167-5-git-send-email-nm@ti.com>

This is just an example patch - Tested on PandaBoard-ES OMAP4460
Connectivity is as follows:
VP_MPU -> VC_CH_MPU -> VC -> TPS62361
TPS62631 Voltage register selection is done using GPIO (GPIO_WK 7)
VP_IVA -> VC_CH_IVA -> VC -> TWL6030/vcore2
VP_CORE -> VC_CH_CORE -> VC -> TWL6030/vcore1

NOT-Signed-off-by: Nishanth Menon <nm at ti.com>
---
 arch/arm/boot/dts/omap4-panda-es.dts |   55 +++++++++++++++++++--
 arch/arm/boot/dts/omap4.dtsi         |   84 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4460.dtsi      |    1 +
 arch/arm/boot/dts/tps62361.dtsi      |   90 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/twl6030.dtsi       |   68 +++++++++++++++++++++++++
 5 files changed, 294 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/tps62361.dtsi

diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 08d2e38..71aa5f3 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -43,10 +43,18 @@
 	};
 };
 
-&led_wkgpio_pins {
-	pinctrl-single,pins = <
-		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
-	>;
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+
+	tps62361_wkgpio_pins: pinmux_tps62361_wkpins {
+		pinctrl-single,pins = <
+			0x1a 0xa03	/* gpio_wk7 OUTPUT | MODE 3 |OFF_HI */
+		>;
+	};
 };
 
 &leds {
@@ -68,3 +76,42 @@
 		linux,default-trigger = "mmc0";
 	};
 };
+
+#define TPS62361_PD_VSEL0
+#include "tps62361.dtsi"
+
+/* Board Specific configuration */
+&omap_tps62361 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&tps62361_wkgpio_pins
+	>;
+	gpios = <&gpio1 7 1>;	/* gpio_wk7 Set to HIGH */
+
+	ti,boot-voltage-micro-volts=<1203000>;
+	ti,vp=<&vp_mpu>;
+};
+
+&omap_twl6030_vcore1 {
+	ti,boot-voltage-micro-volts=<1200000>;
+	ti,vp=<&vp_core>;
+};
+
+&omap_twl6030_vcore2 {
+	ti,boot-voltage-micro-volts=<1200000>;
+	ti,vp = <&vp_iva>;
+};
+
+&omap_twl6030_vcore3 {
+	status = "disabled";
+};
+
+&vc_mpu {
+	/* Due to potential lifetime impact, OFF voltage is set to RET V: TPS*/
+	ti,off-micro-volts = <750000>;
+};
+
+&vc {
+	ti,i2c-high-speed;
+	ti,i2c-pad-load=<3>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 1c6d969..b9fd360 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -108,6 +108,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		sysclk_in: sys_clkin {
+			#clock-cells = <0>;
+			compatible = "ti,omap-clock";
+		};
+
 		dpll_mpu: dpll_mpu {
 			#clock-cells = <0>;
 			compatible = "ti,omap-clock";
@@ -667,5 +672,84 @@
 			ram-bits = <12>;
 			ti,has-mailbox;
 		};
+
+	vc: vc at 0x4A307B88 {
+			compatible = "ti,omap4-vc";
+			clocks = <&sysclk_in>;
+			reg = <0x4A307B88 0x40>;
+			reg-names = "base-address";
+
+			ti,i2c-high-speed; /* belongs to board file */
+			vc_mpu: vc_mpu {
+				compatible = "ti,omap4-vc-channel-mpu";
+				ti,master-channel;
+				ti,retention-micro-volts = <750000>;
+				ti,off-micro-volts = <0>;
+			};
+
+			vc_iva: vc_iva {
+				compatible = "ti,omap4-vc-channel-iva";
+				ti,retention-micro-volts = <750000>;
+				ti,off-micro-volts = <0>;
+			};
+
+			vc_core: vc_core {
+				compatible = "ti,omap4-vc-channel-core";
+				ti,retention-micro-volts = <750000>;
+				ti,off-micro-volts = <0>;
+			};
+		};
+
+		vp_mpu: vp at 0x4a307b58 {
+			compatible = "ti,omap4-vp";
+
+			reg = <0x4a307b58 0x18>, <0x4A306014 0x4>;
+			reg-names = "base-address", "int-address";
+			ti,tranxdone-status-mask=<0x20>;
+
+			clocks = <&sysclk_in>;
+
+			ti,vc-channel = <&vc_mpu>;
+			ti,min-step-micro-volts = <10000>;
+			ti,max-step-micro-volts = <50000>;
+			/* HACKs: belongs to SoC specific file */
+			ti,min-micro-volts = <750000>;
+			ti,max-micro-volts = <1410000>;
+		};
+
+		vp_iva: vp at 0x4a307b70 {
+			compatible = "ti,omap4-vp";
+
+			reg = <0x4a307b70 0x18>, <0x4A306010 0x4>;
+			reg-names = "base-address", "int-address";
+			ti,tranxdone-status-mask=<0x20000000>;
+
+			clocks = <&sysclk_in>;
+
+			ti,vc-channel = <&vc_iva>;
+			/* HACKs: belongs to SoC specific file */
+			ti,min-step-micro-volts = <10000>;
+			ti,max-step-micro-volts = <50000>;
+			ti,min-micro-volts = <750000>;
+			ti,max-micro-volts = <1260000>;
+		};
+
+		vp_core: vp at 0x4a307b40 {
+			compatible = "ti,omap4-vp";
+
+			reg = <0x4a307b40 0x18>, <0x4A306010 0x4>;
+			reg-names = "base-address", "int-address";
+			ti,tranxdone-status-mask=<0x200000>;
+
+			clocks = <&sysclk_in>;
+
+			regulator_name = "vdd_core";
+			ti,vc-channel = <&vc_core>;
+			/* HACKs: belongs to SoC specific file */
+			ti,min-step-micro-volts = <10000>;
+			ti,max-step-micro-volts = <50000>;
+			ti,min-micro-volts = <830000>;
+			ti,max-micro-volts = <1200000>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..6937d92 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -20,6 +20,7 @@
 				920000  1313000
 			>;
 			clock-latency = <300000>; /* From legacy driver */
+			cpu0-supply = <&omap_tps62361>; /* HACK: belongs to board file */
 		};
 	};
 
diff --git a/arch/arm/boot/dts/tps62361.dtsi b/arch/arm/boot/dts/tps62361.dtsi
new file mode 100644
index 0000000..b82a50f
--- /dev/null
+++ b/arch/arm/boot/dts/tps62361.dtsi
@@ -0,0 +1,90 @@
+
+/* Add blah blah */
+
+/* Register set definitions */
+#define REG_TPS6236X_SET_0		0x00
+#define REG_TPS6236X_SET_1		0x01
+#define REG_TPS6236X_SET_2		0x02
+#define REG_TPS6236X_SET_3		0x03
+#define REG_TPS6236X_CTRL		0x04
+#define REG_TPS6236X_TEMP		0x05
+#define REG_TPS6236X_RAMP_CTRL		0x06
+#define REG_TPS6236X_CHIP_ID0		0x08
+#define REG_TPS6236X_CHIP_ID1		0x09
+
+/* Register field definitions for REG_TPS6236X_CTRL */
+#define REG_TPS6236X_CTRL_PD_EN		(1 << 7)
+#define REG_TPS6236X_CTRL_PD_VSEL0	(1 << 6)
+#define REG_TPS6236X_CTRL_PD_VSEL1	(1 << 5)
+
+/* Register field definitions for REG_TPS6236X_RAMP_CTRL */
+#define REG_TPS6236X_RAMP_CTRL_RMP_SHIFT 5
+#define REG_TPS6236X_RAMP_CTRL_EN_DISC	(1 << 2)
+#define REG_TPS6236X_RAMP_CTRL_RAMP_PFM	(1 << 1)
+
+/* Value definitions for REG_TPS6236X_RAMP_CTRL::RMP field */
+#define RMP_32MV_USEC			0x0
+#define RMP_16MV_USEC			0x1
+#define RMP_8MV_USEC			0x2
+#define RMP_4MV_USEC			0x3
+#define RMP_2MV_USEC			0x4
+#define RMP_1MV_USEC			0x5
+
+/* Selected values */
+#define RMP_VALUE			(RMP_32MV_USEC << REG_TPS6236X_RAMP_CTRL_RMP_SHIFT | REG_TPS6236X_RAMP_CTRL_EN_DISC | REG_TPS6236X_RAMP_CTRL_RAMP_PFM)
+
+#ifdef TPS62361_PD_VSEL0
+#define _CTRL_VALUE0			(REG_TPS6236X_CTRL_PD_EN | REG_TPS6236X_CTRL_PD_VSEL0)
+#else
+#define _CTRL_VALUE0			0x0
+#endif
+#ifdef TPS62361_PD_VSEL1
+#define _CTRL_VALUE1			(REG_TPS6236X_CTRL_PD_EN | REG_TPS6236X_CTRL_PD_VSEL0)
+#else
+#define _CTRL_VALUE1			0x0
+#endif
+
+#if defined(TPS62361_PD_VSEL0) || defined(TPS62361_PD_VSEL1)
+#define _CTRL_VALUE			(_CTRL_VALUE0 | _CTRL_VALUE0)
+#endif
+
+/ {
+	omap_tps62361: tps62361 {
+		compatible = "ti,omap-pmic";
+		ti,non-zero-voltage-selector;
+
+		/* Slave address */
+		ti,i2c-slave-address = <0x60>;
+		/* I2C register address */
+		ti,i2c-voltage-register = <0x01>; /* Set 1 */
+		ti,i2c-command-register = <0x01>; /* Set 1 */
+
+		/* Slew rate in uV */
+		ti,slew-rate-microvolt = <32000>;
+		/* Step size in uV */
+		ti,step-size-microvolt = <10000>;
+		regulator-min-microvolt= <500000>;
+		regulator-max-microvolt= <1770000>;
+
+		/* Optional - any voltage selector offset to care about */
+		ti,voltage-selector-offset = <0x0>;
+		/* Optional - what mask to apply on vsel value before doing operations on it */
+		ti,voltage-selector-mask =<0x7F>;
+		/* Optional - what bits to always set on voltage selector when sending to PMIC */
+		ti,voltage-selector-set-bits =<0x80>; /* PFM mode */
+
+		/* Optional - Any access to be done over I2C SR to setup registers */
+		ti,setup_commands=<
+			/* register_addr value */
+			/* Setup Slew (ramp) rate */
+			REG_TPS6236X_RAMP_CTRL RMP_VALUE
+			/* Setup PMIC internal pull if needed */
+#ifdef _CTRL_VALUE
+			REG_TPS6236X_CTRL  _CTRL_VALUE
+#endif
+			/* Enable thermal shutdown - 0 is enable :) */
+			REG_TPS6236X_TEMP	0x0
+			/* Setup the internal pulls */
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 2e3bd31..5e1f4ed 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -103,4 +103,72 @@
 		compatible = "ti,twl6030-pwmled";
 		#pwm-cells = <2>;
 	};
+
+	omap_twl6030_vcore1: vcore1 {
+		compatible = "ti,omap-pmic";
+
+		/* Slave address */
+		ti,i2c-slave-address = <0x12>;
+		/* I2C register address */
+		ti,i2c-voltage-register = <0x55>;
+		ti,i2c-command-register = <0x56>;
+
+		/* Slew rate in uV */
+		ti,slew-rate-microvolt = <9000>;
+		/* Step size in uV */
+		ti,step-size-microvolt = <12660>;
+		regulator-min-microvolt= <709000>;
+		regulator-max-microvolt= <1418000>;
+
+		/* Optional - any voltage selector offset to care about */
+		ti,voltage-selector-offset = <0x1>;
+		/* Optional - what mask to apply on vsel value before doing operations on it */
+		ti,voltage-selector-mask =<0x7F>;
+	};
+
+	omap_twl6030_vcore2: vcore2 {
+		compatible = "ti,omap-pmic";
+
+		/* Slave address */
+		ti,i2c-slave-address = <0x12>;
+		/* I2C register address */
+		ti,i2c-voltage-register = <0x5b>;
+		ti,i2c-command-register = <0x5c>;
+
+		/* Slew rate in uV */
+		ti,slew-rate-microvolt = <9000>;
+		/* Step size in uV */
+		ti,step-size-microvolt = <12660>;
+		/* Min voltage in uV for continous operational range at step size */
+		regulator-min-microvolt= <709000>;
+		regulator-max-microvolt= <1418000>;
+
+		/* Optional - any voltage selector offset to care about */
+		ti,voltage-selector-offset = <0x1>;
+		/* Optional - what mask to apply on vsel value before doing operations on it */
+		ti,voltage-selector-mask =<0x7F>;
+	};
+
+	omap_twl6030_vcore3: vcore3 {
+		compatible = "ti,omap-pmic";
+
+		/* Slave address */
+		ti,i2c-slave-address = <0x12>;
+		/* I2C register address */
+		ti,i2c-voltage-register = <0x61>;
+		ti,i2c-command-register = <0x62>;
+
+
+		/* Slew rate in uV */
+		ti,slew-rate-microvolt = <9000>;
+		/* Step size in uV */
+		ti,step-size-microvolt = <12660>;
+		regulator-min-microvolt= <709000>;
+		regulator-max-microvolt= <1418000>;
+
+		/* Optional - any voltage selector offset to care about */
+		ti,voltage-selector-offset = <0x1>;
+		/* Optional - what mask to apply on vsel value before doing operations on it */
+		ti,voltage-selector-mask =<0x7F>;
+	};
 };
-- 
1.7.9.5



From nm at ti.com  Wed May 22 14:18:36 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 22 May 2013 13:18:36 -0500
Subject: [RFC PATCH 3/4] PM / AVS: Introduce support for OMAP Voltage
 Processor(VP) with device tree nodes
In-Reply-To: <1369246717-4167-1-git-send-email-nm@ti.com>
References: <1369246717-4167-1-git-send-email-nm@ti.com>
Message-ID: <1369246717-4167-4-git-send-email-nm@ti.com>

Texas Instrument's OMAP SoC generations since OMAP3-5 introduced an TI
custom hardware block to better facilitate and standardize integration
of Power Management ICs which communicate over I2C called Voltage
Processor(VP).

This is an specialized hardware block meant to support PMIC chips only
over Voltage Controller(VC) interface. This provides an interface for
SmartReflex AVS module to send adjustment steps which is converted into
voltage values and send onwards by VP to VC. VP is also used to set the
voltage of the PMIC by commanding using "forceupdate".

We have an existing implementation in mach-omap2 which has been
re factored and moved out as a separate driver. This new driver is DT
only and the separation was meant to get a maintainable driver which
does not have to deal with legacy platform_data dependencies. The legacy
driver is retained to support non-DT boot and functionality will be
migrated to the DT-only version as we enable features.

Currently, this implementation considers only the basic steps needed for
voltage scaling and exposing voltage processor which hooks on to Voltage
Controller driver and OMAP PMIC driver to provide an regulator interface
over OMAP PMIC driver.

We may need to do additional timing configurations to enable Low power
mode voltage transitions and to hook the Adaptive Voltage
Scaling(AVS) implementation for OMAP which also uses the same voltage
controller to talk to PMICs. This needs to be addressed in a later
series.

This driver is meant to interface with OMAP PMIC driver when the
controller driver registers it's operations with OMAP PMIC driver and
associates with an voltage controller channel. This enables the full
communication path between the OMAP PMIC regulator to the external PMIC
hardware over OMAP Voltage Processor and OMAP Voltage Controller.

[grygorii.strashko at ti.com: co-developer]
Signed-off-by: Grygorii Strashko <grygorii.strashko at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
 .../devicetree/bindings/power/omap-vp.txt          |   39 +
 drivers/power/avs/Makefile                         |    2 +-
 drivers/power/avs/omap_vp.c                        |  886 ++++++++++++++++++++
 3 files changed, 926 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/power/omap-vp.txt
 create mode 100644 drivers/power/avs/omap_vp.c

diff --git a/Documentation/devicetree/bindings/power/omap-vp.txt b/Documentation/devicetree/bindings/power/omap-vp.txt
new file mode 100644
index 0000000..b690e35
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/omap-vp.txt
@@ -0,0 +1,39 @@
+Voltage Controller driver for Texas Instruments OMAP SoCs
+
+Voltage Controller Properties:
+The following are the properties of the voltage controller node
+Required Properties:
+- compatible: Should be one of:
+  - "ti,omap3-vp" - for OMAP3 family of devices
+  - "ti,omap4-vp" - for OMAP4 family of devices
+  - "ti,omap5-vp" - for OMAP5 family of devices
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  - "base-address"	- contains base address of VP module
+  - "int-address"	- contains base address of interrupt register for VP module
+- clocks: should point to the clock node used by VC module, usually sysclk
+- ti,min-micro-volts - SoC supported min operational voltage in micro-volts
+- ti,max-micro-volts - SoC supported max operational voltage in micro-volts
+- ti,min-step-micro-volts - SoC supported min operational voltage steps in micro-volts
+- ti,max-step-micro-volts - SoC supported max operational voltage steps in micro-volts
+- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
+	indicating VP has completed operation in sending command to Voltage Controller.
+- ti,vc-channel - phandle to the Voltage Controller Channel device used by this Voltage
+	Processor.
+Example:
+vp_mpu: vp at 0x4a307b58 {
+	compatible = "ti,omap4-vp";
+
+	reg = <0x4a307b58 0x18>, <0x4A306014 0x4>;
+	reg-names = "base-address", "int-address";
+	ti,tranxdone-status-mask=<0x20>;
+
+	clocks = <&sysclk_in>;
+
+	ti,vc-channel = <&vc_mpu>;
+	ti,min-step-micro-volts = <10000>;
+	ti,max-step-micro-volts = <50000>;
+	ti,min-micro-volts = <750000>;
+	ti,max-micro-volts = <1410000>;
+};
diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
index 95d5f59..535cab5 100644
--- a/drivers/power/avs/Makefile
+++ b/drivers/power/avs/Makefile
@@ -3,7 +3,7 @@ obj-$(CONFIG_POWER_AVS_OMAP)		+= smartreflex.o
 ifneq ($(CONFIG_POWER_TI_HARDWARE_VOLTAGE_CONTROL),)
 
 # OMAP Common
-omap-volt-common			=  omap_vc.o
+omap-volt-common			=  omap_vc.o omap_vp.o
 
 # OMAP SoC specific
 ifneq ($(CONFIG_ARCH_OMAP3),)
diff --git a/drivers/power/avs/omap_vp.c b/drivers/power/avs/omap_vp.c
new file mode 100644
index 0000000..b6a155d
--- /dev/null
+++ b/drivers/power/avs/omap_vp.c
@@ -0,0 +1,886 @@
+/*
+ * OMAP Voltage Processor (VP) interface
+ *
+ * Idea based on arch/arm/mach-omap2/vp.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ * Grygorii Strashko
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/omap-pmic-regulator.h>
+#include <linux/regmap.h>
+#include "omap_vc.h"
+
+#define DRIVER_NAME	"omap-vp"
+
+/**
+ * omap_vp_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_vp_test_timeout(cond, timeout, index)		\
+({								\
+	for (index = 0; index < timeout; index++) {		\
+		if (cond)					\
+			break;					\
+		udelay(1);					\
+	}							\
+})
+
+/**
+ * struct omap_vp_reg_data - Voltage processor register offsets
+ * @config:	CONFIG register
+ * @status:	STATUS register
+ * @vlimitto:	VLIMITTO register
+ * @voltage:	VOLTAGE register
+ * @step_max:	STEP_MAX register
+ * @step_min:	STEP_MAX register
+ */
+struct omap_vp_reg_data {
+	u8 config;
+	u8 status;
+	u8 vlimitto;
+	u8 voltage;
+	u8 step_max;
+	u8 step_min;
+};
+
+static const struct omap_vp_reg_data omap_vp_reg_type1 = {
+	.config = 0x00,
+	.status = 0x14,
+	.vlimitto = 0x0C,
+	.voltage = 0x10,
+	.step_max = 0x08,
+	.step_min = 0x04,
+};
+
+static const struct omap_vp_reg_data omap_vp_reg_type2 = {
+	.config = 0x00,
+	.status = 0x04,
+	.vlimitto = 0x08,
+	.voltage = 0x0C,
+	.step_max = 0x10,
+	.step_min = 0x14,
+};
+
+/* Config register masks - All revisions */
+#define CONFIG_ERROR_OFFSET_MASK	(0xff << 24)
+#define CONFIG_ERROR_GAIN_MASK		(0xff << 16)
+#define CONFIG_INIT_VOLTAGE_MASK	(0xff << 8)
+#define CONFIG_TIMEOUT_ENABLE_MASK	(0x01 << 3)
+#define CONFIG_INITVDD_MASK		(0x01 << 2)
+#define CONFIG_FORCEUPDATE_MASK		(0x01 << 1)
+#define CONFIG_VP_ENABLE_MASK		(0x01 << 0)
+
+/* Status register masks - All revisions */
+#define STATUS_VP_IN_IDLE_MASK		(0x01 << 0)
+
+/* Vlmitto register masks - All revisions */
+#define VLIMITTO_VDDMAX_MASK		(0xff << 24)
+#define VLIMITTO_VDDMIN_MASK		(0xff << 16)
+#define VLIMITTO_TIMEOUT_MASK		(0xffff << 0)
+
+/* Voltage register masks - All revisions */
+#define VOLTAGE_MASK			(0xff << 0)
+
+/* Step max/min register masks - All revisions */
+#define STEP_SMPSTIMEOUT_MASK		(0xffff << 8)
+#define STEP_VSTEP_MASK			(0xff << 0)
+
+/* 32 bit voltage processor registers */
+static struct regmap_config omap_vp_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+/**
+ * struct omap_vp - Structure representing Voltage Processor info
+ * @dev:		device pointer for Voltage Processor
+ * @list:		list head for VP list.
+ * @usage_count:	Usage count - only 1 user at a time.(not always module)
+ * @clk_rate:		Sysclk rate for VP computation.
+ * @vc:			Voltage controller channel corresponding to VP
+ * @pmic:		PMIC used for this path
+ * @regmap:		regmap for VP instance
+ * @regs:		register map
+ * @int_base:		interrupt register base address
+ * @txdone_mask:	TRANXDONE interrupt mask for this VP instance in intreg
+ * @min_uV:		minimum voltage allowed by VP in micro-volts
+ * @max_uV:		maximum voltage allowed by VP in micro-volts
+ * @min_step_uV:	minimum continous voltage step in micro-volts for VP
+ * @max_step_uV:	maximum continous voltage step in micro-volts for VP
+ */
+struct omap_vp {
+	struct device *dev;
+	struct list_head list;
+	int usage_count;
+
+	unsigned long clk_rate;
+	struct omap_vc_channel_info *vc;
+	struct omap_pmic *pmic;
+
+	struct regmap *regmap;
+	const struct omap_vp_reg_data *regs;
+
+	void __iomem *int_base;
+	u32 txdone_mask;
+
+	u32 min_uV;
+	u32 max_uV;
+	u32 min_step_uV;
+	u32 max_step_uV;
+};
+
+static const struct of_device_id omap_vp_of_match[] = {
+	{.compatible = "ti,omap3-vp", .data = &omap_vp_reg_type1},
+	{.compatible = "ti,omap4-vp", .data = &omap_vp_reg_type2},
+	{.compatible = "ti,omap5-vp", .data = &omap_vp_reg_type2},
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap_vp_of_match);
+
+static LIST_HEAD(omap_vp_list);
+static DEFINE_MUTEX(omap_vp_list_mutex);
+
+/**
+ * omap_vp_check_txdone() - inline helper to see if TRANXDONE is set
+ * @vp:	pointer to voltage processor
+ */
+static inline bool omap_vp_check_txdone(const struct omap_vp *vp)
+{
+	return !!(readl(vp->int_base) & vp->txdone_mask);
+}
+
+/**
+ * omap_vp_clear_txdone() - inline helper to clear TRANXDONE
+ * @vp:	pointer to voltage processor
+ *
+ * write of 1 bit clears that interrupt bit only.
+ */
+static inline void omap_vp_clear_txdone(const struct omap_vp *vp)
+{
+	writel(vp->txdone_mask, vp->int_base);
+};
+
+/**
+ * omap_vp_read_idle() - inline helper to read idle register
+ * @regmap:	regmap for voltage processor
+ * @regs:	registers for voltage processor
+ */
+static inline u32 omap_vp_read_idle(struct regmap *regmap,
+				    const struct omap_vp_reg_data *regs)
+{
+	u32 val = 0;
+	regmap_read(regmap, regs->status, &val);
+	return val;
+}
+
+/**
+ * omap_vp_wait_for_idle() - Wait for Voltage processor to idle
+ * @vp:	pointer to voltage processor
+ *
+ * helper to ensure that VP is idle (no pending AVS / previous VP operations)
+ */
+static inline int omap_vp_wait_for_idle(struct omap_vp *vp)
+{
+	struct device *dev = vp->dev;
+	struct regmap *regmap = vp->regmap;
+	const struct omap_vp_reg_data *regs = vp->regs;
+	struct omap_pmic *pmic = vp->pmic;
+	int timeout;
+
+	omap_vp_test_timeout((omap_vp_read_idle(regmap, regs) &
+			      STATUS_VP_IN_IDLE_MASK), pmic->i2c_timeout_us,
+			     timeout);
+
+	if (timeout >= pmic->i2c_timeout_us) {
+		dev_warn_ratelimited(dev, "%s: idle timedout(%d)\n",
+				     __func__, pmic->i2c_timeout_us);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+/**
+ * omap_vp_set_init_voltage() - Setup voltage for transmission.
+ * @vp:	pointer to voltage processor
+ * @volt: voltage to setup the voltage processor with
+ */
+static int omap_vp_set_init_voltage(struct omap_vp *vp, u32 volt)
+{
+	struct regmap *regmap = vp->regmap;
+	const struct omap_vp_reg_data *regs = vp->regs;
+	struct omap_pmic *pmic = vp->pmic;
+	struct omap_pmic_ops *ops = pmic->ops;
+	char vsel;
+	int ret;
+
+	ret = ops->uv_to_vsel(pmic, volt, &vsel);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(regmap, regs->config,
+				 (CONFIG_INIT_VOLTAGE_MASK |
+				  CONFIG_FORCEUPDATE_MASK |
+				  CONFIG_INITVDD_MASK),
+				 vsel << __ffs(CONFIG_INIT_VOLTAGE_MASK));
+	if (ret)
+		return ret;
+
+	/* Trigger initVDD value copy to voltage processor */
+	ret = regmap_update_bits(regmap, regs->config,
+				 CONFIG_INITVDD_MASK, CONFIG_INITVDD_MASK);
+	if (ret)
+		return ret;
+
+	/* Clear initVDD copy trigger bit */
+	ret = regmap_update_bits(regmap, regs->config,
+				 CONFIG_INITVDD_MASK, 0x0);
+
+	return ret;
+}
+
+/**
+ * omap_vp_get_current_voltage() - get the current voltage processor voltage
+ * @vp:	pointer to voltage processor
+ * @uv:	returns with voltage in micro-volts if read was successful.
+ */
+static int omap_vp_get_current_voltage(struct omap_vp *vp, u32 *uv)
+{
+	struct device *dev = vp->dev;
+	struct regmap *regmap = vp->regmap;
+	const struct omap_vp_reg_data *regs = vp->regs;
+	struct omap_pmic *pmic = vp->pmic;
+	struct omap_pmic_ops *ops = pmic->ops;
+	u32 val;
+	u8 vsel;
+	int ret;
+
+	ret = regmap_read(regmap, regs->config, &val);
+	if (ret) {
+		dev_warn_ratelimited(dev,
+				     "%s: unable to read config reg (%d)\n",
+				     __func__, ret);
+		return ret;
+	}
+
+	val &= CONFIG_INIT_VOLTAGE_MASK;
+	vsel = val >> __ffs(CONFIG_INIT_VOLTAGE_MASK);
+	ret = ops->vsel_to_uv(pmic, vsel, &val);
+
+	if (!ret)
+		*uv = val;
+	return ret;
+}
+
+/**
+ * omap_vp_forceupdate_scale() - Update voltage on PMIC using VP "Forceupdate"
+ * @vp:			pointer to voltage processor
+ * @target_volt:	voltage to set the PMIC to
+ *
+ * This will wait for the slew duration to ensure that the voltage is sync-ed
+ * on the PMIC.
+ */
+static int omap_vp_forceupdate_scale(struct omap_vp *vp, u32 target_volt)
+{
+	struct device *dev = vp->dev;
+	struct regmap *regmap = vp->regmap;
+	const struct omap_vp_reg_data *regs = vp->regs;
+	struct omap_pmic *pmic = vp->pmic;
+	int ret, timeout = 0, max_timeout;
+	u32 old_volt = 0;
+	u32 smps_transition_uv, smps_delay;
+
+	ret = omap_vp_wait_for_idle(vp);
+	if (ret)
+		return ret;
+
+	ret = omap_vp_get_current_voltage(vp, &old_volt);
+	if (ret) {
+		dev_warn_ratelimited(dev,
+				     "%s: Unable to convert old voltage(%d)\n",
+				     __func__, ret);
+		/* We will use worst case start voltage - 0V for delay */
+	}
+
+	/*
+	 * Clear all pending TransactionDone interrupt/status. Typical latency
+	 * is <3us - use an conservative value from pmic info.
+	 */
+	max_timeout = 2 * pmic->i2c_timeout_us;
+	while (timeout++ < max_timeout) {
+		omap_vp_clear_txdone(vp);
+		if (!omap_vp_check_txdone(vp))
+			break;
+		udelay(1);
+	}
+	if (timeout >= max_timeout) {
+		dev_warn_ratelimited(dev,
+				     "%s: TRANXDONE not clear(t=%d v=%d)\n",
+				     __func__, max_timeout, target_volt);
+		return -ETIMEDOUT;
+	}
+
+	ret = omap_vp_set_init_voltage(vp, target_volt);
+	if (ret) {
+		dev_warn_ratelimited(dev,
+				     "%s: Fail set init voltage at v=%d(%d)\n",
+				     __func__, target_volt, ret);
+		return ret;
+	}
+
+	/* Force update of voltage */
+	ret = regmap_update_bits(regmap, regs->config,
+				 CONFIG_FORCEUPDATE_MASK,
+				 CONFIG_FORCEUPDATE_MASK);
+	if (ret) {
+		dev_warn_ratelimited(dev,
+				     "%s: Forceupdate not set v=%d (%d)\n",
+				     __func__, target_volt, ret);
+		return ret;
+	}
+
+	/*
+	 * Wait for TransactionDone. Typical latency is <200us.
+	 * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+	 */
+	timeout = 0;
+	omap_vp_test_timeout(omap_vp_check_txdone(vp), max_timeout, timeout);
+	if (timeout >= max_timeout) {
+		dev_warn_ratelimited(dev,
+				     "%s: TRANXDONE not set(t=%d v=%d)\n",
+				     __func__, max_timeout, target_volt);
+		return -ETIMEDOUT;
+	}
+
+	/*
+	 * Due to the inability of OMAP Voltage controller OR voltage processor
+	 * to precisely know when the voltage has achieved the requested value,
+	 * we need a delay loop to ensure that the voltage has transitioned to
+	 * the required level.
+	 */
+	smps_transition_uv = abs(target_volt - old_volt);
+
+	/* delta_voltage / slew_rate, 2uS added as buffer */
+	smps_delay = DIV_ROUND_UP(smps_transition_uv, pmic->slew_rate_uV) + 2;
+
+	/* We dont want to sleep for too long either */
+	usleep_range(smps_delay, smps_delay + 2);
+
+	/*
+	 * Disable TransactionDone interrupt , clear all status, clear
+	 * control registers
+	 */
+	timeout = 0;
+	while (timeout++ < max_timeout) {
+		omap_vp_clear_txdone(vp);
+		if (!omap_vp_check_txdone(vp))
+			break;
+		udelay(1);
+	}
+	if (timeout >= max_timeout) {
+		dev_warn_ratelimited(dev,
+				     "%s: TRANXDONE not recleared(t=%d v=%d)\n",
+				     __func__, max_timeout, target_volt);
+		return -ETIMEDOUT;
+	}
+
+	/* Clear force bit */
+	ret = regmap_update_bits(regmap, regs->config,
+				 CONFIG_FORCEUPDATE_MASK, 0x0);
+	if (ret) {
+		dev_warn_ratelimited(dev,
+				     "%s: Forceupdate not cleared v=%d (%d)\n",
+				     __func__, target_volt, ret);
+		return ret;
+	}
+
+	/* Do the required updates */
+	ret = omap_vc_channel_set_on_voltage(vp->vc, target_volt);
+	if (ret) {
+		dev_warn_ratelimited(dev,
+				     "%s: Fail update VC onV at v=%d (%d)\n",
+				     __func__, target_volt, ret);
+		return ret;
+	}
+
+	/* Now, Wait for VP to idle down */
+	ret = omap_vp_wait_for_idle(vp);
+
+	return ret;
+}
+
+/**
+ * omap_vp_setup() - Setup voltage processor
+ * @vp:	pointer to voltage processor
+ */
+static int omap_vp_setup(struct omap_vp *vp)
+{
+	struct omap_pmic *pmic = vp->pmic;
+	struct omap_pmic_ops *ops = pmic->ops;
+	struct regmap *regmap = vp->regmap;
+	const struct omap_vp_reg_data *regs = vp->regs;
+	u32 val, clk_rate, timeout, waittime;
+	u8 vstepmin, vstepmax;
+	u8 vddmin, vddmax;
+	int ret;
+
+	/* Div 1000 to avoid overflow */
+	clk_rate = vp->clk_rate / 1000;
+
+	ret = ops->uv_to_vsel(pmic, vp->min_uV, &vddmin);
+	if (ret)
+		return ret;
+	ret = ops->uv_to_vsel(pmic, vp->max_uV, &vddmax);
+	if (ret)
+		return ret;
+
+	timeout = DIV_ROUND_UP_ULL(clk_rate * pmic->i2c_timeout_us, 1000);
+	waittime = DIV_ROUND_UP_ULL(pmic->step_size_uV * clk_rate,
+				    1000 * pmic->slew_rate_uV);
+
+	vstepmin = DIV_ROUND_UP(vp->min_step_uV, pmic->step_size_uV);
+	vstepmax = DIV_ROUND_UP(vp->max_step_uV, pmic->step_size_uV);
+
+	/* VSTEPMIN */
+	val =
+	    (waittime << __ffs(STEP_SMPSTIMEOUT_MASK)) & STEP_SMPSTIMEOUT_MASK;
+	val |= (vstepmin << __ffs(STEP_VSTEP_MASK)) & STEP_VSTEP_MASK;
+	ret = regmap_write(regmap, regs->step_min, val);
+	if (ret)
+		return ret;
+
+	/* VSTEPMIN */
+	val =
+	    (waittime << __ffs(STEP_SMPSTIMEOUT_MASK)) & STEP_SMPSTIMEOUT_MASK;
+	val |= (vstepmax << __ffs(STEP_VSTEP_MASK)) & STEP_VSTEP_MASK;
+	ret = regmap_write(regmap, regs->step_max, val);
+	if (ret)
+		return ret;
+
+	/* VLIMITTO */
+	val = (vddmax << __ffs(VLIMITTO_VDDMAX_MASK)) & VLIMITTO_VDDMAX_MASK;
+	val |= (vddmin << __ffs(VLIMITTO_VDDMIN_MASK)) & VLIMITTO_VDDMIN_MASK;
+	val |=
+	    (timeout << __ffs(VLIMITTO_TIMEOUT_MASK)) & VLIMITTO_TIMEOUT_MASK;
+	ret = regmap_write(regmap, regs->vlimitto, val);
+	if (ret)
+		return ret;
+
+	/* CONFIG */
+	ret =
+	    regmap_update_bits(regmap, regs->config, CONFIG_TIMEOUT_ENABLE_MASK,
+			       CONFIG_TIMEOUT_ENABLE_MASK);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+/**
+ * devm_omap_vp_release() -  helper to keep track of free usage.
+ * @dev:	device
+ * @res:	resource
+ */
+static void devm_omap_vp_release(struct device *dev, void *res)
+{
+	struct omap_vp *vp = *((struct omap_vp **)res);
+
+	mutex_lock(&omap_vp_list_mutex);
+
+	if (!vp->usage_count) {
+		vp->pmic = NULL;
+		vp->vc = NULL;
+	}
+	module_put(vp->dev->driver->owner);
+
+	mutex_unlock(&omap_vp_list_mutex);
+
+	return;
+}
+
+/**
+ * of_get_omap_vp() - get the pmic node
+ * @dev:	device to pull information from
+ */
+static struct device_node *of_get_omap_vp(struct device *dev)
+{
+	struct device_node *pmic_node = NULL;
+	char *prop_name = "ti,vp";
+
+	dev_dbg(dev, "%s: Looking up %s from device tree\n", __func__,
+		prop_name);
+
+	pmic_node = of_parse_phandle(dev->of_node, prop_name, 0);
+
+	if (!pmic_node) {
+		dev_err(dev, "%s: Looking up %s property in node %s failed",
+			__func__, prop_name, dev->of_node->full_name);
+		return ERR_PTR(-ENODEV);
+	}
+	return pmic_node;
+}
+
+/**
+ * devm_omap_vp_get() - managed request to get a VP device
+ * @dev:	Generic device to handle the request for
+ * @pmic:	PMIC resource this will be assigned to
+ *
+ * Ensures that vp usage count is maintained. Uses managed device,
+ * so everything is undone on driver detach.
+ *
+ * Return: -EPROBE_DEFER if the node is present, however device is
+ * not yet probed.
+ * -EINVAL if bad pointers or node description is not found.
+ * -ENODEV if the property cannot be found
+ * -ENOMEM if allocation could not be done.
+ *  device pointer to vp dev if all successful.
+ *  Error handling should be performed with IS_ERR
+ */
+static struct device *devm_omap_vp_get(struct device *dev,
+				       struct omap_pmic *pmic)
+{
+	struct omap_vp *vp, **ptr;
+	struct device_node *node;
+	struct device *vp_dev;
+	struct omap_vc_channel_info *vc;
+	u32 min_uV, max_uV;
+	int ret = 0;
+
+	if (!dev || !dev->of_node) {
+		pr_err("%s: invalid parameters\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	node = of_get_omap_vp(dev);
+	if (IS_ERR(node))
+		return (void *)node;
+
+	mutex_lock(&omap_vp_list_mutex);
+	list_for_each_entry(vp, &omap_vp_list, list)
+	    if (vp->dev->of_node == node)
+		goto found;
+
+	/* Node definition is present, but not probed yet.. request defer */
+	vp_dev = ERR_PTR(-EPROBE_DEFER);
+	goto out_unlock;
+
+found:
+	vp_dev = vp->dev;
+	if (!try_module_get(vp_dev->driver->owner)) {
+		dev_err(dev, "%s: Cant get device owner\n", __func__);
+		vp_dev = ERR_PTR(-EINVAL);
+		goto out_unlock;
+	}
+
+	/* Allow ONLY 1 user at a time */
+	if (vp->usage_count) {
+		dev_err(dev, "%s: device %s is busy..\n", __func__,
+			dev_name(vp_dev));
+		ret = -EBUSY;
+		goto out;
+	}
+	vc = devm_omap_vc_channel_get(vp_dev, pmic);
+	if (IS_ERR(vc)) {
+		ret = PTR_ERR(vc);
+		dev_err(dev, "%s: vc channel not ready(%d) in %s?\n",
+			__func__, ret, dev_name(vp_dev));
+		goto out;
+	}
+	vp->vc = vc;
+	vp->pmic = pmic;
+
+	/* Adjust our voltages */
+	/* Cant go below PMIC min voltage */
+	min_uV = max(vp->min_uV, pmic->min_uV);
+	/* Cant go below SoC retention voltage for operational case */
+	min_uV = max(min_uV, vc->retention_uV);
+	vp->min_uV = min_uV;
+
+	/* Cant go above PMIC max voltage */
+	max_uV = min(vp->max_uV, pmic->max_uV);
+	vp->max_uV = max_uV;
+
+	ret = omap_vp_setup(vp);
+	if (ret) {
+		dev_err(dev, "%s: Failed to setup vp (%d) dev %s\n",
+			__func__, ret, dev_name(vp_dev));
+		goto out;
+	}
+
+	if (pmic->boot_voltage_uV) {
+		ret = omap_vp_forceupdate_scale(vp, pmic->boot_voltage_uV);
+		if (ret) {
+			dev_err(dev, "%s: Failed to set boot voltage %d(%d)\n",
+				__func__, pmic->boot_voltage_uV, ret);
+			goto out;
+		}
+	}
+
+	ptr = devres_alloc(devm_omap_vp_release, sizeof(*ptr), GFP_KERNEL);
+	if (!ptr) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	*ptr = vp;
+	vp->usage_count++;
+	devres_add(dev, ptr);
+
+out:
+	if (ret) {
+		module_put(vp_dev->driver->owner);
+		vp_dev = ERR_PTR(ret);
+	}
+out_unlock:
+	mutex_unlock(&omap_vp_list_mutex);
+
+	return vp_dev;
+}
+
+/**
+ * omap_vp_voltage_set() - controller operation to set voltage
+ * @dev:	VP device to set voltage
+ * @uv:		voltage in micro-volts to set
+ */
+static int omap_vp_voltage_set(struct device *dev, u32 uv)
+{
+	struct omap_vp *vp = dev_get_drvdata(dev);
+
+	if (!vp)
+		return -EINVAL;
+	if (!vp->pmic || !vp->vc)
+		return -EINVAL;
+
+	return omap_vp_forceupdate_scale(vp, uv);
+}
+
+/**
+ * omap_vp_voltage_get() - controller operation to get voltage
+ * @dev:	VP device to get voltage from
+ * @uv:		returns voltage in micro-volts if successful
+ */
+static int omap_vp_voltage_get(struct device *dev, u32 *uv)
+{
+	struct omap_vp *vp = dev_get_drvdata(dev);
+
+	if (!vp || !uv)
+		return -EINVAL;
+	if (!vp->pmic || !vp->vc)
+		return -EINVAL;
+
+	return omap_vp_get_current_voltage(vp, uv);
+}
+
+/**
+ * omap_vp_voltage_get_range() - controller function to return VP voltage range
+ * @dev:	VP device to query
+ * @min_uv:	if successful, returns min voltage supported by VP
+ * @max_uv:	if successful, returns max voltage supported by VP
+ */
+static int omap_vp_voltage_get_range(struct device *dev, u32 *min_uv,
+				     u32 *max_uv)
+{
+	struct omap_vp *vp = dev_get_drvdata(dev);
+
+	if (!vp || !min_uv || !max_uv)
+		return -EINVAL;
+	if (!vp->pmic || !vp->vc)
+		return -EINVAL;
+
+	*min_uv = vp->min_uV;
+	*max_uv = vp->max_uV;
+	return 0;
+}
+
+static struct omap_pmic_controller_ops voltage_processor_ops = {
+	.devm_pmic_register = devm_omap_vp_get,
+	.voltage_set = omap_vp_voltage_set,
+	.voltage_get = omap_vp_voltage_get,
+	.voltage_get_range = omap_vp_voltage_get_range,
+};
+static bool voltage_processor_ops_registered;
+
+static int omap_vp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	const struct of_device_id *match;
+	struct omap_vp *vp;
+	struct resource *res;
+	struct regmap *regmap;
+	char *pname;
+	struct clk *clk;
+	int ret = 0;
+	void __iomem *base, *int_base;
+
+	if (!node) {
+		dev_err(dev, "%s: missing device tree nodes?\n", __func__);
+		return -EINVAL;
+	}
+
+	match = of_match_device(omap_vp_of_match, dev);
+	if (!match) {
+		/* We do not expect this to happen */
+		dev_err(dev, "%s: Unable to match device\n", __func__);
+		return -ENODEV;
+	}
+	if (!match->data) {
+		dev_err(dev, "%s: Bad data in match\n", __func__);
+		return -EINVAL;
+	}
+
+	pname = "base-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	base = devm_request_and_ioremap(dev, res);
+	if (!base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		return -EADDRNOTAVAIL;
+	}
+	pname = "int-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	if (!res) {
+		dev_err(dev, "Missing '%s' IO resource\n", pname);
+		return -ENODEV;
+	}
+
+	/*
+	 * We may have shared interrupt register offsets which are
+	 * write-1-to-clear between domains ensuring exclusivity.
+	 */
+	int_base = devm_ioremap_nocache(dev, res->start, resource_size(res));
+	if (!int_base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		return -ENOMEM;
+	}
+
+	regmap = devm_regmap_init_mmio(dev, base, &omap_vp_regmap_config);
+	if (IS_ERR(regmap)) {
+		ret = PTR_ERR(regmap);
+		dev_err(dev, "regmap init failed(%d)\n", ret);
+		return ret;
+	}
+
+	vp = devm_kzalloc(dev, sizeof(*vp), GFP_KERNEL);
+	if (!vp) {
+		dev_err(dev, "%s: Unable to allocate VP\n", __func__);
+		return -ENOMEM;
+	}
+	vp->dev = dev;
+	vp->regs = match->data;
+	vp->regmap = regmap;
+	vp->int_base = int_base;
+
+	clk = clk_get(dev, NULL);
+	if (IS_ERR(clk)) {
+		ret = PTR_ERR(clk);
+		dev_err(dev, "%s: Unable to get clk(%d)\n", __func__, ret);
+		return ret;
+	}
+	vp->clk_rate = clk_get_rate(clk);
+	/* We dont need the clk any more */
+	clk_put(clk);
+
+	pname = "ti,min-micro-volts";
+	ret = of_property_read_u32(node, pname, &vp->min_uV);
+	if (ret)
+		goto invalid_of_property;
+
+	pname = "ti,max-micro-volts";
+	ret = of_property_read_u32(node, pname, &vp->max_uV);
+	if (ret || !vp->max_uV)
+		goto invalid_of_property;
+
+	pname = "ti,min-step-micro-volts";
+	ret = of_property_read_u32(node, pname, &vp->min_step_uV);
+	if (ret || !vp->min_step_uV)
+		goto invalid_of_property;
+
+	pname = "ti,max-step-micro-volts";
+	ret = of_property_read_u32(node, pname, &vp->max_step_uV);
+	if (ret || !vp->max_step_uV)
+		goto invalid_of_property;
+
+	pname = "ti,tranxdone-status-mask";
+	ret = of_property_read_u32(node, pname, &vp->txdone_mask);
+	if (ret || !vp->txdone_mask)
+		goto invalid_of_property;
+
+	platform_set_drvdata(pdev, vp);
+
+	mutex_lock(&omap_vp_list_mutex);
+	if (!voltage_processor_ops_registered) {
+		ret = omap_pmic_register_controller_ops(&voltage_processor_ops);
+		if (ret)
+			dev_err(dev, "Failed register pmic cops (%d)\n", ret);
+		else
+			voltage_processor_ops_registered = true;
+	}
+	if (!ret)
+		list_add(&vp->list, &omap_vp_list);
+
+	mutex_unlock(&omap_vp_list_mutex);
+	return ret;
+
+invalid_of_property:
+	if (!ret) {
+		dev_err(dev, "%s: Invalid value 0x0 in '%s' property.\n",
+			__func__, pname);
+		ret = -EINVAL;
+	} else {
+		dev_err(dev, "%s: Missing/Invalid '%s' property - error(%d)\n",
+			__func__, pname, ret);
+	}
+	return ret;
+}
+
+static int omap_vp_remove(struct platform_device *pdev)
+{
+	struct omap_vp *vp = platform_get_drvdata(pdev);
+
+	mutex_lock(&omap_vp_list_mutex);
+	list_del(&vp->list);
+	mutex_unlock(&omap_vp_list_mutex);
+
+	return 0;
+}
+
+static struct platform_driver omap_vp_driver = {
+	.probe = omap_vp_probe,
+	.remove = omap_vp_remove,
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   .of_match_table = of_match_ptr(omap_vp_of_match),
+		   },
+};
+module_platform_driver(omap_vp_driver);
+
+MODULE_DESCRIPTION("OMAP Voltage Processor Regulator Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc.");
-- 
1.7.9.5



From nm at ti.com  Wed May 22 14:18:34 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 22 May 2013 13:18:34 -0500
Subject: [RFC PATCH 1/4] regulator: Introduce OMAP regulator to control PMIC
 over VC/VP
In-Reply-To: <1369246717-4167-1-git-send-email-nm@ti.com>
References: <1369246717-4167-1-git-send-email-nm@ti.com>
Message-ID: <1369246717-4167-2-git-send-email-nm@ti.com>

Texas Instrument's OMAP SoC generations since OMAP3-5 introduced
an TI custom hardware block to better facilitate and standardize
integration of Power Management ICs which communicate over I2C.

In fact, many custom PMICs were designed to be usable over this
interface. On the other hand, generic PMICs which are compatible
to the I2C protocol supported by Voltage controller may also be
used.

In general, the following categories of PMICs exist:

a) PMICs which are completely controlled by voltage controller/voltage
processor pair - this implies even configuration needs to be done
over the same interface. Example: TPS62361 used on PandaBoard-ES and
many OMAP4460 based platforms. Few Maxim and Fairchild PMICs used on
certain products would fall in this category.
- Note: in this case, there may not even exist/needed to support an
"traditional Linux regulator driver"

b) PMICs which provide two views over two I2C interfaces - however,
voltage can only be set only on one of them. Example: TWL4030/5030:
allows us to use Voltage controller once we set up a bit over regular
I2C - This is used in OMAP3. TWO6030/TWL6032 - configuration *has*
to be performed over regular i2c (example smps_offset) and voltage
control *has* to be performed by using voltage controller/processor.
- Note: in this case, there may exist "traditional Linux regulator driver"
however, it may not support in any form SMPS modelling for that part of
the device which is exposed to voltage controller/processor.
c) PMICs which allow voltage and configurations over either i2c
interfaces - TWL6035/TWL6037/Palmas family of TI processor
- Note: in this case, there may exist "traditional Linux regulator driver"
and, it may support in some form SMPS modelling for that part of
the device which is exposed to voltage controller/processor.
d) custom PMICs which are setup so that no configuration is needed to be
performed and they operate with preset register offsets and minimal
conferability using voltage controller/processor.
- Note: in this case, there may not even exist/needed to support an
"traditional Linux regulator driver"

However, no matter the type of PMIC used, the OMAP view of a PMIC is
generic when used over voltage controller/processor. We attempt to
model this generic view of the regulator represented by OMAP SoC.

Alternative to this approach would be to "hack" into the get
voltage/set voltage interfaces of regulator drivers which represent
the rest of the PMIC controlled over regular I2C interface and
re-route the requests to voltage controller/processor. But, by doing
that, we needlessly create additional code which may be abstracted out
into device tree node information.

Since the regulator node representing PMIC, voltage controller,
processors are probed at varied points in time, probe deferral is used
to sequence in the right order. It is expected by the driver to register
omap_pmic_register_controller_ops providing mandatory operations at the
earliest possible opportunity.

Despite the current SoCs implementing the solution based on voltage
controller and voltage processor (which are part of the OMAP SoC modules
which enable Adaptive Voltage Scaling class support), the interfaces are
generic enough to handle future equivalent modules.

[grygorii.strashko at ti.com: co-developer]
Signed-off-by: Grygorii Strashko <grygorii.strashko at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
 .../bindings/regulator/omap-pmic-regulator.txt     |  121 +++++
 drivers/regulator/Kconfig                          |   12 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/omap-pmic-regulator.c            |  554 ++++++++++++++++++++
 include/linux/regulator/omap-pmic-regulator.h      |  147 ++++++
 5 files changed, 835 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/regulator/omap-pmic-regulator.txt
 create mode 100644 drivers/regulator/omap-pmic-regulator.c
 create mode 100644 include/linux/regulator/omap-pmic-regulator.h

diff --git a/Documentation/devicetree/bindings/regulator/omap-pmic-regulator.txt b/Documentation/devicetree/bindings/regulator/omap-pmic-regulator.txt
new file mode 100644
index 0000000..b87dd3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/omap-pmic-regulator.txt
@@ -0,0 +1,121 @@
+Generic Power Management IC(PMIC) Regulator for Texas Instruments OMAP SoCs
+
+Required Properties:
+- compatible: Should be:
+  - "ti,omap-pmic"
+
+- ti,i2c-slave-address - I2C slave address of the PMIC
+- ti,i2c-voltage-register - I2C register address where voltage commands are
+	to be set.
+- ti,i2c-command-register - I2C register address where commands are to be set
+	when OMAP enters low power state. This may be the same as
+	ti,i2c-voltage-register depending on the PMIC.
+- ti,slew-rate-microvolt - worst case slew rate of rise / fall for voltage
+	transition in microvolts per microseconds (uV/uS)
+- step-size-micro-volts - Step size in micovolts as to what one step in voltage
+	selector increment translates to. See example.
+- regulator-min-microvolt - Minimum voltage in microvolts which is supported by
+	the PMIC in ti,step-size-microvolt increments. See example.
+- regulator-max-microvolt - Maximum voltage in microvolts which is supported
+	by the PMIC in ti,step-size-microvolt increments. See example.
+
+Optional Properties:
+- gpios: OF device-tree gpio specification - can be an array, will be setup
+	in the order of definition and set to the flags.
+- pinctrl: OF device-tree pinctrl definitions as needed (usually for the GPIOs)
+- ti,boot-voltage-micro-volts - voltage in microvolts that bootloader is leaving
+	over the PMIC at. This may be 'PMIC data manual configuration' if
+	bootloader does not set an value, or appropritate value.
+- ti,voltage-selector-set-bits - what bits to set permenantly for the PMIC
+	voltage selector - this may have PMIC specific meaning.
+- ti,voltage-selector-mask - what mask to use for the vsel value - this is
+	useful for PMICs where the vsel has to be applied at an offset.
+- ti,voltage-selector-offset - what offset to apply to conversion routine when
+	operating on vsel.
+- ti,non-zero-voltage-selector - Special case handling if 0 value does NOT
+	indicates power-off for PMIC.
+- ti,setup_commands - An array of 2-tuples items, and each item consists
+  of register address and command like <address data>
+	addr: I2C register address to send the command (over Voltage controller)
+	data: What data to send
+
+Example: defining step-size, min/max voltages
+NOTE: OMAP can only handle continous voltages. In a case of an PMIC such as the
+follows:
+	vsel- corresponding voltage
+	0x1 - 500mV
+	0x2 - 800mV
+	0x3 - 810mV
+	0x4 - 820mV
+	..
+	0x14 - 1v
+	0x15 - 1.5v
+OMAP can only suppport voltages for voltage operations when the voltages
+are in equal increments. In the above example, it is 800mV to 1v at 10mV steps
+This corresponds to the following properties:
+step-size-micro-volts  = <10000>;
+regulator-min-microvolt = <800000>;
+regulator-max-microvolt = <1000000>;
+
+Example: Setup PMIC with PFM mode to be enabled for voltage operations
+Lets say that the bit in voltage selector(vsel) is 0x80. in this case,
+ti,voltage-selector-set-bits =<0x80>;
+
+Example: setup PMIC where the vsel bits are set from bits 7:4
+Consider an following example
+0x10 - 800mV
+0xf0 - 1v
+in this case,
+ti,voltage-selector-mask = <0xF0>;
+
+Example: Conversion routine needs an offset
+Consider an PMIC with the following behavior for vsel.
+	0 - OFF voltage
+	1 - 709mV
+	2 - 721.66mV
+	etc..
+	regulator-min-microvolt would be 709, however vsel offsets needs to be
+	accounted for. Hence, we could use
+ti,voltage-selector-offset = <1>;	/* incremental vsel starts at 1 */
+
+On the other hand, when 0 indicates voltage = regulator-min-microvolt, use:
+ti,non-zero-voltage-selector;
+
+Example: Sample PMIC description
+omap_tps62361: tps62361 {
+	compatible = "ti,omap-pmic";
+	ti,non-zero-voltage-selector;
+
+	ti,i2c-slave-address = <0x60>;
+	/* We have only one register to set voltage / low power voltage  to */
+	ti,i2c-voltage-register = <0x01>; /* Set 1 register */
+	ti,i2c-command-register = <0x01>; /* Set 1 register */
+
+	ti,slew-rate-microvolt = <32000>;
+	ti,step-size-microvolt = <10000>;
+	regulator-min-microvolt = <500000>;
+	regulator-max-microvolt = <1770000>;
+
+	ti,voltage-selector-offset = <0x0>;
+	ti,voltage-selector-set-bits =<0x80>; /* PFM mode */
+	ti,non-zero-voltage-selector;
+
+	ti,setup_commands=<
+		/* register_addr value */
+		/* Setup Slew (ramp) rate (0 - 32mV/uS) */
+		0x06	0x0
+		/* Enable thermal shutdown - 0 is enable :( */
+		0x5	0x0
+	>;
+};
+
+/* Board Specific configuration */
+&omap_tps62361 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&tps62361_wkgpio_pins
+	>;
+	gpios = <&gpio1 7 1>;	/* gpio_wk7 */
+
+	ti,boot-voltage-micro-volts=<1200000>;
+};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 8bb2644..3a2d625 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -472,6 +472,18 @@ config REGULATOR_TWL4030
 	  This driver supports the voltage regulators provided by
 	  this family of companion chips.
 
+config REGULATOR_TI_OMAP_PMIC
+	tristate "TI Generic regulator for Voltage Processor / Controller"
+	depends on ARCH_OMAP
+	help
+	  Select this option to support PMICs over Texas Instruments'
+	  custom Voltage Processor + Voltage Controller data interface
+	  used in OMAP SoCs. This is a specific "write-only" interface
+	  designed to interface with I2C based PMICs.
+
+	  This option enables the regulator driver representing the PMIC
+	  on the OMAP VC/VP hardware.
+
 config REGULATOR_VEXPRESS
 	tristate "Versatile Express regulators"
 	depends on VEXPRESS_CONFIG
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 47a34ff..32c882e 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_TPS65912) += tps65912-regulator.o
 obj-$(CONFIG_REGULATOR_TPS80031) += tps80031-regulator.o
 obj-$(CONFIG_REGULATOR_TWL4030) += twl-regulator.o
+obj-$(CONFIG_REGULATOR_TI_OMAP_PMIC) += omap-pmic-regulator.o
 obj-$(CONFIG_REGULATOR_VEXPRESS) += vexpress.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o
diff --git a/drivers/regulator/omap-pmic-regulator.c b/drivers/regulator/omap-pmic-regulator.c
new file mode 100644
index 0000000..31ac186
--- /dev/null
+++ b/drivers/regulator/omap-pmic-regulator.c
@@ -0,0 +1,554 @@
+/*
+ * OMAP Generic PMIC Regulator
+ *
+ * Idea based on arch/arm/mach-omap2/omap_twl.c
+ * Copyright (C) 2010 Texas Instruments Incorporated.
+ * Thara Gopinath
+ * Copyright (C) 2009 Texas Instruments Incorporated.
+ * Nishanth Menon
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ * Grygorii Strashko
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/omap-pmic-regulator.h>
+
+#define DRIVER_NAME	"omap-pmic"
+
+static DEFINE_MUTEX(omap_pmic_cops_mutex);
+static struct omap_pmic_controller_ops *pmic_cops;
+
+/**
+ * omap_pmic_register_controller_ops() - Register voltage operations
+ * @cops:	voltage operations
+ *
+ * It is expected that appropriate controller register it's functions
+ * with this driver using this interface, If this is not done, the probe
+ * for the corresponding device will defer till it fails.
+ *
+ * Return: -EBUSY if already registered, else returns 0
+ */
+int omap_pmic_register_controller_ops(struct omap_pmic_controller_ops *cops)
+{
+	int ret = 0;
+
+	mutex_lock(&omap_pmic_cops_mutex);
+	if (pmic_cops) {
+		pr_err("Controller operations already registered\n");
+		ret = -EBUSY;
+		goto out;
+	}
+	if (!cops->devm_pmic_register || !cops->voltage_set ||
+	    !cops->voltage_get || !cops->voltage_get_range) {
+		pr_err("Missing operations!\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	pmic_cops = cops;
+out:
+	mutex_unlock(&omap_pmic_cops_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(omap_pmic_register_controller_ops);
+
+/**
+ * omap_pmic_vsel_to_uv() - Convert voltage selector(vsel) to microvolts
+ * @pmic:	pointer to pmic struct
+ * @vsel:	voltage selector(vsel)
+ * @uv:		If conversion is successful, returns the voltage in micro volts
+ *
+ * Return: 0 if conversion is successful and *uv has proper value, else
+ * appropriate error value for failure.
+ */
+static int omap_pmic_vsel_to_uv(struct omap_pmic *pmic, u8 vsel, u32 *uv)
+{
+	u32 tmp = vsel;
+
+	if (!pmic || !uv) {
+		pr_err("Bad parameters pmic=%p uv=%p!\n", pmic, uv);
+		return -EINVAL;
+	}
+
+	if (pmic->voltage_selector_mask) {
+		tmp &= pmic->voltage_selector_mask;
+		tmp >>= __ffs(pmic->voltage_selector_mask);
+	}
+
+	if (!tmp && pmic->voltage_selector_zero)
+		goto out;
+
+	tmp -= pmic->voltage_selector_offset;
+	tmp *= pmic->step_size_uV;
+	tmp += pmic->min_uV;
+
+	if (tmp < pmic->min_uV || tmp > pmic->max_uV) {
+		dev_dbg(pmic->dev, "%s: Out of range 0x%02x[%d] (%d <-> %d)\n",
+			__func__, vsel, tmp, pmic->min_uV, pmic->max_uV);
+		return -ERANGE;
+	}
+
+out:
+	*uv = tmp;
+	dev_dbg(pmic->dev, "%s: uv=%d vsel=0x%02x\n", __func__, *uv, vsel);
+
+	return 0;
+}
+
+/**
+ * omap_pmic_uv_to_vsel() - Convert microvolts to voltage selector(vsel)
+ * @pmic:	pointer to pmic struct
+ * @uv:		voltage in micro volts
+ * @vsel:	If conversion is successful, voltage selector(vsel)
+ *
+ * Return: 0 if conversion is successful and *vsel has proper value, else
+ * appropriate error value for failure.
+ */
+static int omap_pmic_uv_to_vsel(struct omap_pmic *pmic, u32 uv, u8 *vsel)
+{
+	u32 tmp = uv;
+
+	if (!pmic || !vsel) {
+		pr_err("Bad parameters pmic=%p vsel=%p!\n", pmic, vsel);
+		return -EINVAL;
+	}
+
+	if (!tmp && pmic->voltage_selector_zero)
+		goto skip_convert;
+
+	if (tmp > pmic->max_uV)
+		goto skip_convert;
+
+	tmp -= pmic->min_uV;
+	tmp = DIV_ROUND_UP(tmp, pmic->step_size_uV);
+
+	tmp += pmic->voltage_selector_offset;
+
+skip_convert:
+	if (tmp > 0xFF) {
+		dev_dbg(pmic->dev, "%s: Out of range 0x%04x[%d] (%d - %d)\n",
+			__func__, tmp, uv, pmic->min_uV, pmic->max_uV);
+		return -ERANGE;
+	}
+	if (pmic->voltage_selector_mask) {
+		tmp <<= __ffs(pmic->voltage_selector_mask);
+		if (tmp > 0xFF) {
+			dev_warn(pmic->dev, "%s: Out of range 0x%04x[%d]\n",
+				 __func__, tmp, uv);
+			return -ERANGE;
+		}
+		tmp &= pmic->voltage_selector_mask;
+	}
+
+	tmp |= pmic->voltage_selector_setbits;
+
+	*vsel = tmp;
+	dev_dbg(pmic->dev, "%s: uv=%d vsel=0x%02x\n", __func__, uv, *vsel);
+
+	return 0;
+}
+
+/**
+ * omap_pmic_of_read_setup_commands() - read setup commands from OF
+ * @dev:	device to pick up setup commands from
+ * @pmic:	pointer to pmic structure
+ */
+static int omap_pmic_of_read_setup_commands(struct device *dev,
+					    struct omap_pmic *pmic)
+{
+	char *pname = "ti,setup_commands";
+	const struct property *prop;
+	const __be32 *v;
+	struct omap_pmic_setup_commands *setup;
+	const u8 num_values = 2;
+	u32 num_entries;
+	int i;
+
+	prop = of_find_property(dev->of_node, pname, NULL);
+	if (!prop)
+		return 0;
+
+	if (!prop->value) {
+		dev_err(dev, "Empty '%s' property?\n", pname);
+		return -ENODATA;
+	}
+
+	/* Each setup command is a tuple consisting of reg_addr, value */
+	num_entries = prop->length / sizeof(u32);
+	if (!num_entries || (num_entries % num_values)) {
+		dev_err(dev, "All '%s' list entries need %d vals\n", pname,
+			num_values);
+		return -EINVAL;
+	}
+	num_entries /= num_values;
+
+	setup = devm_kzalloc(dev, sizeof(*setup) * num_entries, GFP_KERNEL);
+	if (!setup) {
+		dev_err(dev, "Can't allocate info table for '%s' property\n",
+			pname);
+		return -ENOMEM;
+	}
+
+	pmic->setup_command_list = setup;
+	pmic->setup_num_commands = num_entries;
+
+	v = prop->value;
+	for (i = 0; i < num_entries; i++, setup++) {
+		u32 reg, cmd_val;
+
+		/* NOTE: num_values should equal to entries picked up here */
+		reg = be32_to_cpup(v++);
+		cmd_val = be32_to_cpup(v++);
+
+		/* Setup commands and registers are 8 bit wide. */
+		if (reg > 0xFF || cmd_val > 0xFF) {
+			dev_err(dev, "Bad entries in '%s' property idx=%d\n",
+				pname, i);
+			return -EINVAL;
+		}
+
+		setup->reg = reg;
+		setup->cmd_val = cmd_val;
+		dev_dbg(dev, "[setup cmd %d] reg=0x%02x val=0x%02x\n", i,
+			setup->reg, setup->cmd_val);
+	}
+
+	return 0;
+}
+
+/**
+ * omap_pmic_of_setup_gpios() - Setup GPIO array if needed.
+ * @dev:	device to pick up the gpios from
+ */
+static int omap_pmic_of_setup_gpios(struct device *dev)
+{
+	struct device_node *node = dev->of_node;
+	int num_gpios, i, ret;
+
+	num_gpios = of_gpio_count(node);
+	if (num_gpios < 0)
+		return 0;
+
+	for (i = 0; i < num_gpios; i++) {
+		int gpio;
+		enum of_gpio_flags flags;
+
+		gpio = of_get_gpio_flags(node, i, &flags);
+		if (!gpio_is_valid(gpio)) {
+			dev_err(dev, "Invalid GPIO[%d]: %d\n", i, gpio);
+			return -EINVAL;
+		}
+
+		ret = devm_gpio_request(dev, gpio, dev_name(dev));
+		if (ret) {
+			dev_err(dev, "Unable to get GPIO %d (%d)\n", gpio, ret);
+			return ret;
+		}
+		ret = gpio_direction_output(gpio,
+					    !!(flags & OF_GPIO_ACTIVE_LOW));
+		if (ret) {
+			dev_err(dev, "Failed to set GPIO %d (%d)\n", gpio, ret);
+			return ret;
+		}
+		dev_dbg(dev, "GPIO=%d set_to=%d\n", gpio,
+			!!(flags & OF_GPIO_ACTIVE_LOW));
+	}
+
+	return 0;
+}
+
+/**
+ * omap_pmic_set_voltage() - regulator interface to set voltage
+ * @rdev:	regulator device
+ * @min_uV:	min voltage in micro-volts
+ * @max_uV:	max voltage in micro-volts
+ * @unused:	unused.. we dont use sel
+ *
+ * Return: -ERANGE for out of range values, appropriate error code if conversion
+ * fails, else returns 0.
+ */
+static int omap_pmic_set_voltage(struct regulator_dev *rdev, int min_uV,
+				 int max_uV, unsigned *unused)
+{
+	struct omap_pmic *pmic = rdev_get_drvdata(rdev);
+
+	return pmic_cops->voltage_set(pmic->v_dev, min_uV);
+}
+
+/**
+ * omap_pmic_get_voltage() - regulator interface to get voltage
+ * @rdev: regulator device
+ *
+ * Return: current voltage set on PMIC OR appropriate error value
+ */
+static int omap_pmic_get_voltage(struct regulator_dev *rdev)
+{
+	struct omap_pmic *pmic = rdev_get_drvdata(rdev);
+	int ret;
+	u32 uv;
+
+	ret = pmic_cops->voltage_get(pmic->v_dev, &uv);
+	if (ret)
+		return ret;
+
+	return uv;
+}
+
+static struct omap_pmic_ops omap_generic_pmic_ops = {
+	.vsel_to_uv = omap_pmic_vsel_to_uv,
+	.uv_to_vsel = omap_pmic_uv_to_vsel,
+};
+
+static struct regulator_ops omap_pmic_reg_ops = {
+	.list_voltage = regulator_list_voltage_linear,
+
+	.set_voltage = omap_pmic_set_voltage,
+	.get_voltage = omap_pmic_get_voltage,
+};
+
+/**
+ * omap_pmic_parse_of() - Do DT OF node parsing
+ * @pmic:	pointer to PMIC
+ */
+static int omap_pmic_parse_of(struct omap_pmic *pmic)
+{
+	struct device *dev = pmic->dev;
+	struct device_node *node = dev->of_node;
+	u32 val = 0;
+	char *pname;
+	int ret;
+
+	pname = "ti,i2c-slave-address";
+	ret = of_property_read_u32(node, pname, &val);
+	/* Only 7 bit addressing allowed for slave address */
+	if (ret || val >= 0x80)
+		goto invalid_of_property;
+	pmic->slave_addr = val;
+
+	pname = "ti,i2c-voltage-register";
+	ret = of_property_read_u32(node, pname, &val);
+	if (ret || val >= 0xFF)
+		goto invalid_of_property;
+	pmic->voltage_reg_addr = val;
+
+	pname = "ti,i2c-command-register";
+	ret = of_property_read_u32(node, pname, &val);
+	if (ret || val >= 0xFF)
+		goto invalid_of_property;
+	pmic->cmd_reg_addr = val;
+
+	pname = "ti,slew-rate-microvolt";
+	ret = of_property_read_u32(node, pname, &val);
+	if (ret || !val)
+		goto invalid_of_property;
+	pmic->slew_rate_uV = val;
+
+	pname = "ti,step-size-microvolt";
+	ret = of_property_read_u32(node, pname, &val);
+	if (ret || !val)
+		goto invalid_of_property;
+	pmic->step_size_uV = val;
+
+	/* Optional parameters */
+	pmic->voltage_selector_zero =
+	    !of_property_read_bool(node, "ti,non-zero-voltage-selector");
+
+	pname = "ti,boot-voltage-micro-volts";
+	ret = of_property_read_u32(node, pname, &val);
+	if (!ret) {
+		if (!val)
+			goto invalid_of_property;
+		pmic->boot_voltage_uV = val;
+	}
+
+	ret = of_property_read_u32(node, "ti,i2c-timeout-microsecond",
+				   &pmic->i2c_timeout_us);
+	/* If we dont have custom parameter, use arbitary un-realistic value */
+	if (ret)
+		pmic->i2c_timeout_us = 200;
+
+	pname = "ti,voltage-selector-offset";
+	ret = of_property_read_u32(node, pname, &val);
+	if (!ret) {
+		if (val > 0xFF)
+			goto invalid_of_property;
+		pmic->voltage_selector_offset = val;
+	}
+	pname = "ti,voltage-selector-mask";
+	ret = of_property_read_u32(node, pname, &val);
+	if (!ret) {
+		if (val > 0xFF)
+			goto invalid_of_property;
+		pmic->voltage_selector_mask = val;
+	}
+	pname = "ti,voltage-selector-set-bits";
+	ret = of_property_read_u32(node, pname, &val);
+	if (!ret) {
+		if (val > 0xFF)
+			goto invalid_of_property;
+		pmic->voltage_selector_setbits = val;
+	}
+
+	ret = omap_pmic_of_read_setup_commands(dev, pmic);
+
+	return ret;
+
+invalid_of_property:
+	if (!ret) {
+		dev_err(dev, "Invalid value 0x%x[%d] in '%s' property.\n",
+			val, val, pname);
+		ret = -EINVAL;
+	} else {
+		dev_err(dev, "Missing/Invalid '%s' property - error(%d)\n",
+			pname, ret);
+	}
+	return ret;
+}
+
+static int omap_pmic_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct omap_pmic *pmic;
+	struct regulator_desc *desc;
+	struct regulation_constraints *c;
+	struct regulator_config config = { };
+	struct regulator_init_data *initdata = NULL;
+	struct regulator_dev *rdev = NULL;
+	int ret = 0;
+	bool ops_ready;
+
+	if (!node) {
+		dev_err(dev, "%s: missing device tree nodes?\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&omap_pmic_cops_mutex);
+	ops_ready = pmic_cops ? true : false;
+	mutex_unlock(&omap_pmic_cops_mutex);
+	if (!ops_ready) {
+		dev_dbg(dev, "Voltage Operations not ready yet..\n");
+		return -EPROBE_DEFER;
+	}
+
+	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
+	if (!desc) {
+		dev_err(dev, "%s: unable to allocate desc\n", __func__);
+		return -ENOMEM;
+	}
+
+	pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+	if (!pmic) {
+		dev_err(dev, "%s: unable to allocate pmic\n", __func__);
+		return -ENOMEM;
+	}
+
+	/* Read mandatory OF parameters */
+	pmic->dev = dev;
+	pmic->ops = &omap_generic_pmic_ops;
+
+	initdata = of_get_regulator_init_data(dev, node);
+	if (!initdata) {
+		dev_err(dev, "%s: Unable to alloc regulator init data\n",
+			__func__);
+		return -ENOMEM;
+	}
+	c = &initdata->constraints;
+	if (!c->max_uV) {
+		dev_err(dev, "regulator-max-microvolt is set as 0?\n");
+		return -EINVAL;
+	}
+
+	pmic->min_uV = c->min_uV;
+	pmic->max_uV = c->max_uV;
+
+	ret = omap_pmic_parse_of(pmic);
+	if (ret)
+		return ret;
+
+	ret = omap_pmic_of_setup_gpios(dev);
+	if (ret)
+		return ret;
+
+	pmic->v_dev = pmic_cops->devm_pmic_register(dev, pmic);
+	if (IS_ERR(pmic->v_dev)) {
+		dev_dbg(dev, "Registration of pmic failed (%d)\n", ret);
+		ret = PTR_ERR(pmic->v_dev);
+		return ret;
+	}
+	desc->name = dev_name(dev);
+	desc->owner = THIS_MODULE;
+	desc->type = REGULATOR_VOLTAGE;
+	desc->ops = &omap_pmic_reg_ops;
+	desc->uV_step = pmic->step_size_uV;
+	desc->ramp_delay = pmic->slew_rate_uV;
+
+	c->valid_ops_mask |= REGULATOR_CHANGE_VOLTAGE;
+	c->always_on = true;
+	ret = pmic_cops->voltage_get_range(pmic->v_dev, &c->min_uV, &c->max_uV);
+	if (ret) {
+		dev_err(dev, "Voltage Range get failed (%d)\n", ret);
+		return ret;
+	}
+
+	config.dev = dev;
+	config.init_data = initdata;
+	config.driver_data = pmic;
+	config.of_node = node;
+
+	rdev = regulator_register(desc, &config);
+	if (IS_ERR(rdev)) {
+		ret = PTR_ERR(rdev);
+		dev_err(dev, "%s: failed to register regulator(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+	return ret;
+}
+
+static const struct of_device_id omap_pmic_of_match_tbl[] = {
+	{.compatible = "ti,omap-pmic",},
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap_pmic_of_match_tbl);
+
+static struct platform_driver omap_pmic_driver = {
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   .of_match_table = of_match_ptr(omap_pmic_of_match_tbl),
+		   },
+	.probe = omap_pmic_probe,
+};
+module_platform_driver(omap_pmic_driver);
+
+MODULE_DESCRIPTION("OMAP Generic PMIC Regulator");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc.");
diff --git a/include/linux/regulator/omap-pmic-regulator.h b/include/linux/regulator/omap-pmic-regulator.h
new file mode 100644
index 0000000..97e7697
--- /dev/null
+++ b/include/linux/regulator/omap-pmic-regulator.h
@@ -0,0 +1,147 @@
+/*
+ * OMAP Generic PMIC Regulator interfaces
+ *
+ * Idea based on arch/arm/mach-omap2/omap_twl.c and
+ * arch/arm/mach-omap2/voltage.h
+ * Copyright (C) 2010 Texas Instruments Incorporated.
+ * Thara Gopinath
+ * Copyright (C) 2009 Texas Instruments Incorporated.
+ * Nishanth Menon
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated.
+ * Grygorii Strashko
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __POWER_OMAP_PMIC_H
+#define __POWER_OMAP_PMIC_H
+
+struct omap_pmic;
+
+/**
+ * struct omap_pmic_setup_commands - setup commands over voltage controller
+ * @reg:	device's i2c register address
+ * @cmd_val:	command to send.
+ */
+struct omap_pmic_setup_commands {
+	u8 reg;
+	u8 cmd_val;
+};
+
+/**
+ * struct omap_pmic_ops - Conversion routines for voltage controller/processor
+ * @vsel_to_uv: convert voltage selector to micro-volts
+ * @uv_to_vsel: convert micro-volts to voltage selector
+ *
+ * voltage controller/processor drivers SHOULD NOT do modifications on vsel or
+ * make any assumptions about vsel. Instead, they may operate on micro-volts
+ * and request vsel conversion once they are ready to do hardware operations.
+ *
+ * This is provided over the omap_pmic structure.
+ */
+struct omap_pmic_ops {
+	int (*vsel_to_uv) (struct omap_pmic *pmic, u8 vsel, u32 *uv);
+	int (*uv_to_vsel) (struct omap_pmic *pmic, u32 uv, u8 *vsel);
+};
+
+/**
+ * struct omap_pmic_controller_ops - regulator operations implemented
+ * @devm_pmic_register: managed registration of an PMIC device with a specific
+ *			voltage processor. Voltage processor provides an device
+ *			handle which is remaining operations.
+ *			NOTE:
+ *			- This will be first interface to be invoked by
+ *			omap_pmic regulator.
+ *			- if the underlying layers are not ready, this is
+ *			expected to return -EPROBE_DEFER
+ *			- if failure, appropriate error code is expected.
+ *			- This is expected to be a managed device to avoid
+ *			explicit cleanup operations
+ *			- Once this succeeds, this returns the pointer to
+ *			the controller device and all other operations are
+ *			expected to be ready for functionality.
+ * @voltage_set:	set the voltage - expected to be synchronous.
+ * @voltage_get:	get the current voltage in micro-volts set on PMIC.
+ * @voltage_get_range:	Get minimum and maxium permissible operational voltage
+ *			range for the device - used to set initial regulator
+ *			constraints.
+ *
+ * These voltage processor interfaces are registered by voltage processor driver
+ * using omap_pmic_register_controller_ops. This allows the omap_pmic driver to
+ * operate with a specific voltage processor driver.
+ */
+struct omap_pmic_controller_ops {
+	struct device *(*devm_pmic_register) (struct device *dev,
+					      struct omap_pmic *pmic);
+	int (*voltage_set) (struct device *control_dev, u32 uv);
+	int (*voltage_get) (struct device *control_dev, u32 *uv);
+	int (*voltage_get_range) (struct device *control_dev, u32 *min_uv,
+				  u32 *max_uv);
+};
+
+/**
+ * struct omap_pmic - represents the OMAP PMIC device.
+ * @slave_addr:		7 bit address representing I2C slave address.
+ * @voltage_reg_addr:	I2C register address for setting voltage
+ * @cmd_reg_addr:	I2C register address for low power transition commands
+ * @i2c_timeout_us:	worst case latency for I2C operations for the device
+ * @slew_rate_uV:	Slew rate in uV/uSeconds for voltage transitions
+ * @step_size_uV:	Step size in uV for one vsel increment.
+ * @min_uV:		represents the minimum step_sized incremental voltage
+ * @max_uV:		represents the maximum step_sized incremental voltage
+ * @boot_voltage_uV:	voltage for the PMIC handed over to Linux kernel
+ * @setup_command_list:	array of setup commands for PMIC to operate
+ * @setup_num_commands:	number of setup commands for PMIC to operate
+ * @ops:		PMIC conversion operations.
+ *
+ * NOTE: the fields marked Private are meant for PMIC driver.
+ */
+struct omap_pmic {
+	u8 slave_addr;
+	u8 voltage_reg_addr;
+	u8 cmd_reg_addr;
+	u32 i2c_timeout_us;
+
+	u32 boot_voltage_uV;
+	u32 slew_rate_uV;
+	u32 step_size_uV;
+	u32 min_uV;
+	u32 max_uV;
+
+	struct omap_pmic_setup_commands *setup_command_list;
+	u8 setup_num_commands;
+
+	struct omap_pmic_ops *ops;
+
+	/* Private */
+	u8 voltage_selector_offset;
+	u8 voltage_selector_mask;
+	u8 voltage_selector_setbits;
+	bool voltage_selector_zero;
+	struct device *dev;
+	struct device *v_dev;
+};
+
+#if IS_ENABLED(CONFIG_REGULATOR_TI_OMAP_PMIC)
+int omap_pmic_register_controller_ops(struct omap_pmic_controller_ops *cops);
+#else
+static inline int omap_pmic_register_controller_ops(struct
+						    omap_pmic_controller_ops
+						    *cops)
+{
+	return -EINVAL;
+}
+#endif
+
+#endif				/* __POWER_OMAP_PMIC_H */
-- 
1.7.9.5



From nm at ti.com  Wed May 22 14:18:35 2013
From: nm at ti.com (Nishanth Menon)
Date: Wed, 22 May 2013 13:18:35 -0500
Subject: [RFC PATCH 2/4] PM / AVS: Introduce support for OMAP Voltage
 Controller(VC) with device tree nodes
In-Reply-To: <1369246717-4167-1-git-send-email-nm@ti.com>
References: <1369246717-4167-1-git-send-email-nm@ti.com>
Message-ID: <1369246717-4167-3-git-send-email-nm@ti.com>

Texas Instrument's OMAP SoC generations since OMAP3-5 introduced an TI
custom hardware block to better facilitate and standardize integration
of Power Management ICs which communicate over I2C called Voltage
Controller(VC).

This is an specialized hardware block meant to support PMIC chips and
is customized to that requirement. Even though it functions as an I2C
controller, it is a write-only interface whose configurations are custom
to PMICs.

We have an existing implementation in mach-omap2 which has been
re factored and moved out as a separate driver. This new driver is DT
only and the separation was meant to get a maintainable driver which
does not have to deal with legacy platform_data dependencies. The legacy
driver is retained to support non-DT boot and functionality will be
migrated to the DT-only version as we enable features.

Currently, this implementation considers only the basic steps needed for
voltage scaling and exposing voltage controller as a device whose
child devices are voltage controller channel devices.

We may need to do additional timing configurations to enable Low power
mode voltage transitions, but this will be completed in a following
series. We may need a few tweaks to hook the Adaptive Voltage
Scaling(AVS) implementation for OMAP which also uses the same voltage
controller to talk to PMICs.

This driver is meant to interface with voltage processor when the
voltage processor attempts devm_omap_vc_channel_get for the
VC channel corresponding to the voltage processor.

[grygorii.strashko at ti.com: co-developer]
Signed-off-by: Grygorii Strashko <grygorii.strashko at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
 .../devicetree/bindings/power/omap-vc.txt          |   99 ++
 drivers/power/avs/Kconfig                          |   15 +
 drivers/power/avs/Makefile                         |   20 +
 drivers/power/avs/omap_vc.c                        | 1508 ++++++++++++++++++++
 drivers/power/avs/omap_vc.h                        |   67 +
 5 files changed, 1709 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/omap-vc.txt
 create mode 100644 drivers/power/avs/omap_vc.c
 create mode 100644 drivers/power/avs/omap_vc.h

diff --git a/Documentation/devicetree/bindings/power/omap-vc.txt b/Documentation/devicetree/bindings/power/omap-vc.txt
new file mode 100644
index 0000000..f97737c
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/omap-vc.txt
@@ -0,0 +1,99 @@
+Voltage Controller driver for Texas Instruments OMAP SoCs
+
+Voltage Controller Properties:
+The following are the properties of the voltage controller node
+Required Properties:
+- compatible: Should be one of:
+  - "ti,omap3-vc" - for OMAP3 family of devices
+  - "ti,omap4-vc" - for OMAP4 family of devices
+  - "ti,omap5-vc" - for OMAP5 family of devices
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  - "base-address"	- contains base address of VC module
+- clocks: should point to the clock node used by VC module, usually sysclk
+- ti,i2c-clk-scl-low: is mandatory if ti,i2c-pad-load is not used. contains
+  hex to represent timing for slow I2C phase low clock time.
+- ti,i2c-clk-scl-high: is mandatory if ti,i2c-pad-load is not used. contains
+  hex to represent timing for slow I2C phase high clock time.
+- ti,i2c-clk-hsscl-low: is mandatory if ti,i2c-pad-load is not used and
+  ti,i2c-high-speed is used, contains hex to represent timing for high speed I2C
+  phase low clock time.
+- ti,i2c-clk-hsscl-high: is mandatory if ti,i2c-pad-load is not used and
+  ti,i2c-high-speed is used, contains hex to represent timing for high speed I2C
+  phase high clock time.
+- Must contain VC channel nodes which belong to the Voltage controller.
+
+Optional Properties:
+- ti,i2c-high-speed: bool to indicate if VC should operate in high speed I2C
+  mode.
+- ti,i2c-pad-load: if ti,i2c-high-speed, then this is optional to auto load
+  pre-calculated I2C clock timing configuration. This is denoted in pico-farads.
+- ti,i2c-pcb-length: if ti,i2c-pad-load, then this is optional to select the
+  pre-calculated I2C clock timing configuration. default of '63' is used.
+  This is denoted in millimeters.
+- pinctrl: Most OMAP SoCs do not allow pinctrl option to select VC's I2C path.
+  it is usually hardcoded by default. Define "default" pinctrl-0 as needed.
+
+Voltage Controller Channel Properties:
+The following are the properties of the voltage controller channel nodes
+Required Properties:
+- compatible: Should be one of:
+  - ti,omap3-vc-channel-0 - Channel 0 on OMAP3 family of devices
+  - ti,omap3-vc-channel-1 - Channel 1 on OMAP3 family of devices
+  - ti,omap4-vc-channel-mpu - Channel MPU on OMAP4 family of devices
+  - ti,omap4-vc-channel-iva - Channel IVA on OMAP4 family of devices
+  - ti,omap4-vc-channel-core - Channel CORE on OMAP4 family of devices
+  - ti,omap5-vc-channel-mpu - Channel MPU on OMAP5 family of devices
+  - ti,omap5-vc-channel-mm - Channel MM on OMAP5 family of devices
+  - ti,omap5-vc-channel-core - Channel CORE on OMAP5 family of devices
+- ti,master-channel: bool to mark the "master channel". Only ONE channel is
+  to be marked as master channel depending on SoC specification.
+
+Optional Properties:
+- ti,retention-micro-volts: retention voltage for the voltage controller in
+  micro-volts
+- ti,off-micro-volts: OFF mode voltage for the voltage controller in micro-volts
+- ti,use-master-slave-addr: available only for a "non-master" channel. This
+  indicates the the channel will use master channel's slave address. Usually
+  used when the PMIC has the same slave address for all SMPSs.
+- ti,use-master-voltage-reg-addr: available only for a "non-master" channel.
+  channel will use voltage register of the master channel to send voltage
+  commands - usually used in "ganged" voltage rail configuration - NOTE: this
+  is useful only when doing voltage transitions alone and not using AVS.
+- ti,use-master-command-reg-addr: available only for a "non-master" channel.
+  channel will use command register of the master channel to send command
+  values - usually used in "ganged" voltage rail configuration - NOTE: this
+  is useful only when doing voltage transitions alone and not using AVS.
+- ti,use-master-command-reg-val: available only for a "non-master" channel.
+  channel will use command value of the master channel to send commands
+  - usually used in "ganged" voltage rail configuration - NOTE: this
+  is useful only when doing voltage transitions alone and not using AVS.
+
+Example:
+SoC file: (example from OMAP4)
+vc: vc at 0x4A307B88 {
+		compatible = "ti,omap4-vc";
+		clocks = <&sysclk_in>;
+		reg = <0x4A307B88 0x40>;
+		reg-names = "base-address";
+
+		vc_mpu: vc_mpu {
+			compatible = "ti,omap4-vc-channel-mpu";
+			ti,master-channel;
+			ti,retention-micro-volts = <750000>;
+			ti,off-micro-volts = <0>;
+		};
+
+		vc_iva: vc_iva {
+			compatible = "ti,omap4-vc-channel-iva";
+			ti,retention-micro-volts = <750000>;
+			ti,off-micro-volts = <0>;
+		};
+
+		vc_core: vc_core {
+			compatible = "ti,omap4-vc-channel-core";
+			ti,retention-micro-volts = <750000>;
+			ti,off-micro-volts = <0>;
+		};
+	};
diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
index 2a1008b..68dff06 100644
--- a/drivers/power/avs/Kconfig
+++ b/drivers/power/avs/Kconfig
@@ -10,3 +10,18 @@ menuconfig POWER_AVS
 	  AVS is also called SmartReflex on OMAP devices.
 
 	  Say Y here to enable Adaptive Voltage Scaling class support.
+
+config POWER_TI_HARDWARE_VOLTAGE_CONTROL
+	tristate "TI OMAP SoC Voltage Control support"
+	depends on OF && ARCH_OMAP && REGULATOR_TI_OMAP_PMIC
+	select REGMAP_MMIO
+	help
+	  Select this option to support Texas Instruments' custom Voltage
+	  Processor + Voltage Controller data interface used in OMAP SoCs
+	  to enable Adaptive Voltage Scaling(AVS) and Device Frequency and
+	  Voltage Scaling(DVFS). This is a specific "write-only" interface
+	  designed to interface with I2C based PMICs. These two subsystems
+	  in OMAP do not exist independent of each other as they are
+	  practically useless without each other.
+
+	  Say Y here to enable TI OMAP SoC Voltage Control support.
diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
index 0843386..95d5f59 100644
--- a/drivers/power/avs/Makefile
+++ b/drivers/power/avs/Makefile
@@ -1 +1,21 @@
 obj-$(CONFIG_POWER_AVS_OMAP)		+= smartreflex.o
+
+ifneq ($(CONFIG_POWER_TI_HARDWARE_VOLTAGE_CONTROL),)
+
+# OMAP Common
+omap-volt-common			=  omap_vc.o
+
+# OMAP SoC specific
+ifneq ($(CONFIG_ARCH_OMAP3),)
+obj-$(CONFIG_POWER_TI_HARDWARE_VOLTAGE_CONTROL) += $(omap-volt-common)
+endif
+
+ifneq ($(CONFIG_ARCH_OMAP4),)
+obj-$(CONFIG_POWER_TI_HARDWARE_VOLTAGE_CONTROL) += $(omap-volt-common)
+endif
+
+ifneq ($(CONFIG_SOC_OMAP5),)
+obj-$(CONFIG_POWER_TI_HARDWARE_VOLTAGE_CONTROL) += $(omap-volt-common)
+endif
+
+endif
diff --git a/drivers/power/avs/omap_vc.c b/drivers/power/avs/omap_vc.c
new file mode 100644
index 0000000..4efb8ce
--- /dev/null
+++ b/drivers/power/avs/omap_vc.c
@@ -0,0 +1,1508 @@
+/*
+ * OMAP Voltage Controller (VC) interface
+ *
+ * Idea based on arch/arm/mach-omap2/vc.c
+ * Copyright (C) 2011 Texas Instruments Incorporated.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ * Grygorii Strashko
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regulator/omap-pmic-regulator.h>
+#include <linux/regmap.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include "omap_vc.h"
+
+#define DRIVER_NAME	"omap-vc"
+
+/**
+ * struct vc_channel_regs - Register description for VC channel
+ * @cfg_reg_offset:  Channel configuration register offset
+ * @sa_reg_offset: Slave Address configuration register offset
+ * @voltage_reg_offset: Voltage address register offset
+ * @command_addr_reg_offset: Command address register offset
+ * @command_val_reg_offset: Command value register offset
+ *
+ * NOTE: All register offsets are from VC base, as certain flavor
+ * of SoCs use shared registers and other have unique register offsets
+ */
+struct vc_channel_regs {
+	u16 cfg_reg_offset;
+	u16 sa_reg_offset;
+	u16 voltage_reg_offset;
+	u16 command_addr_reg_offset;
+	u16 command_val_reg_offset;
+
+	/* private: */
+	/* cfg_reg_offset details */
+	u32 racen_mask;
+	u32 rac_enable_mask;
+	u32 rav_enable_mask;
+	u32 cmd_sel_mask;
+	u32 sa_enable_mask;
+
+	/* sa_reg_offset details */
+	u32 sa_addr_mask;
+
+	/* voltage_reg_offset details */
+	u32 voltage_addr_mask;
+
+	/* command_addr_reg_offset details */
+	u32 command_addr_mask;
+
+	/* command_val_reg_offset details */
+	u32 command_val_on_mask;
+	u32 command_val_onlp_mask;
+	u32 command_val_ret_mask;
+	u32 command_val_off_mask;
+};
+
+/**
+ * struct omap_vc_channel - internal representation of VC channel
+ * @dev:		device pointer for VC channel device
+ * @list:		channel list
+ * @usage_count:	Usage count - only 1 user at a time.(not always module)
+ * @is_master_channel:	Is this channel the master channel?
+ * @use_master_channel_sa: if this channel uses master channel's slave address
+ * @use_master_channel_voltage_reg: if this channel uses master channel's
+ *			voltage register address
+ * @use_master_channel_cmd_reg: if this channel uses master channel's command
+ *			register address
+ * @use_master_channel_cmd_val: if this channel uses master channel's command
+ *			value address
+ * @ch_regs:		Channel register description
+ * @info:		exported information containing PMIC hooked to this
+ *			channel, low power state voltage information etc.
+ */
+struct omap_vc_channel {
+	struct device *dev;
+	struct list_head list;
+	int usage_count;
+	bool is_master_channel;
+	bool use_master_channel_sa;
+	bool use_master_channel_voltage_reg;
+	bool use_master_channel_cmd_reg;
+	bool use_master_channel_cmd_val;
+	const struct vc_channel_regs *ch_regs;
+	struct omap_vc_channel_info info;
+};
+
+/**
+ * struct omap_omap_vc_i2c_config - Voltage controller channel's I2C config
+ * @clk_rate:		Frequency of sys_clock for the voltage controller's I2C
+ * @highspeed:		used in I2C highspeed mode?
+ * @mcode:		Master Code used in High speed mode
+ * @i2c_clk_pad_load:	What is the pad load at i2c
+ * @i2c_clk_pcb_length:	What is the pcb length to the PMIC (all inclusive)
+ * @i2c_clk_scll:	Clock low timing config for slow speed
+ * @i2c_clk_sclh:	Clock high timing config for slow speed
+ * @i2c_clk_hsscll:	Clock low timing config for high speed
+ * @i2c_clk_hssclh:	Clock high timing config for high speed
+ *
+ * Used one time at boot.
+ */
+struct omap_omap_vc_i2c_config {
+	unsigned long clk_rate;
+	bool highspeed;
+	u8 mcode;
+	u32 i2c_clk_pad_load;
+	u32 i2c_clk_pcb_length;
+	u8 i2c_clk_scll;
+	u8 i2c_clk_sclh;
+	u8 i2c_clk_hsscll;
+	u8 i2c_clk_hssclh;
+};
+
+/**
+ * struct omap_vc_common_reg - Voltage Controller Common registers
+ * @i2c_clk_cfg_reg:	I2C clock configuration register offset
+ * @i2c_clk_mode_reg:	I2C clock operation mode register offset
+ * @bypass_cmd_reg:	VC_BYPASS (very low level control) register offset
+ *
+ * These may be -1 to indicate register not being present.
+ */
+struct omap_vc_common_reg {
+	s16 i2c_clk_cfg_reg;
+	u16 i2c_clk_mode_reg;
+	u16 bypass_cmd_reg;
+};
+
+/**
+ * struct omap_vc - represents the voltage controller(vc) device
+ * @regmap:	regmap to the entire voltage controller region(includes channel)
+ * @regs:	Voltage Controller common registers
+ * @master_channel_configured:	Is Master channel has been configured.
+ */
+struct omap_vc {
+	struct regmap *regmap;
+	const struct omap_vc_common_reg *regs;
+	bool master_channel_configured;
+};
+
+/* VC Channel register configurations */
+static const struct vc_channel_regs omap3_ch_1_regs = {
+	.cfg_reg_offset = 0x14,
+	.racen_mask = 0x80000,
+	.rac_enable_mask = 0x40000,
+	.rav_enable_mask = 0x20000,
+	.cmd_sel_mask = 0x100000,
+	.sa_enable_mask = 0x10000,
+
+	.sa_reg_offset = 0x0,
+	.sa_addr_mask = 0x7f0000,
+
+	.voltage_reg_offset = 0x4,
+	.voltage_addr_mask = 0xFF0000,
+
+	.command_addr_reg_offset = 0x8,
+	.command_addr_mask = 0xFF0000,
+
+	.command_val_reg_offset = 0x10,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0xFF,
+};
+
+static const struct vc_channel_regs omap3_ch_0_regs = {
+	.cfg_reg_offset = 0x14,
+	.racen_mask = 0x8,
+	.rac_enable_mask = 0x4,
+	.rav_enable_mask = 0x2,
+	.cmd_sel_mask = 0x10,
+	.sa_enable_mask = 0x1,
+
+	.sa_reg_offset = 0x0,
+	.sa_addr_mask = 0x7f,
+
+	.voltage_reg_offset = 0x4,
+	.voltage_addr_mask = 0xFF,
+
+	.command_addr_reg_offset = 0x8,
+	.command_addr_mask = 0xFF,
+
+	.command_val_reg_offset = 0xC,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0xFF,
+};
+
+static const struct vc_channel_regs omap4_ch_mpu_regs = {
+	.cfg_reg_offset = 0x1c,
+	.racen_mask = 0x100000,
+	.rac_enable_mask = 0x80000,
+	.rav_enable_mask = 0x40000,
+	.cmd_sel_mask = 0x20000,
+	.sa_enable_mask = 0x10000,
+
+	.sa_reg_offset = 0x0,
+	.sa_addr_mask = 0x7f0000,
+
+	.voltage_reg_offset = 0x4,
+	.voltage_addr_mask = 0xFF0000,
+
+	.command_addr_reg_offset = 0x8,
+	.command_addr_mask = 0xFF0000,
+
+	.command_val_reg_offset = 0x10,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0xFF,
+};
+
+static const struct vc_channel_regs omap4_ch_iva_regs = {
+	.cfg_reg_offset = 0x1c,
+	.racen_mask = 0x800,
+	.rac_enable_mask = 0x400,
+	.rav_enable_mask = 0x200,
+	.cmd_sel_mask = 0x1000,
+	.sa_enable_mask = 0x100,
+
+	.sa_reg_offset = 0x0,
+	.sa_addr_mask = 0x7f00,
+
+	.voltage_reg_offset = 0x4,
+	.voltage_addr_mask = 0xFF00,
+
+	.command_addr_reg_offset = 0x8,
+	.command_addr_mask = 0xFF00,
+
+	.command_val_reg_offset = 0x14,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0xFF,
+};
+
+static const struct vc_channel_regs omap4_ch_core_regs = {
+	.cfg_reg_offset = 0x1c,
+	.racen_mask = 0x8,
+	.rac_enable_mask = 0x4,
+	.rav_enable_mask = 0x2,
+	.cmd_sel_mask = 0x10,
+	.sa_enable_mask = 0x1,
+
+	.sa_reg_offset = 0x0,
+	.sa_addr_mask = 0x7f,
+
+	.voltage_reg_offset = 0x4,
+	.voltage_addr_mask = 0xFF,
+
+	.command_addr_reg_offset = 0x8,
+	.command_addr_mask = 0xFF,
+
+	.command_val_reg_offset = 0xC,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0xFF,
+};
+
+static const struct vc_channel_regs omap5_ch_core_regs = {
+	.cfg_reg_offset = 0x0,
+	.racen_mask = 0x8000000,
+	.rac_enable_mask = 0x4000000,
+	.rav_enable_mask = 0x2000000,
+	.cmd_sel_mask = 0x10000000,
+	.sa_enable_mask = 0x1000000,
+
+	.sa_reg_offset = 0x0,
+	.sa_addr_mask = 0x7f,
+
+	.voltage_reg_offset = 0x0,
+	.voltage_addr_mask = 0xFF00,
+
+	.command_addr_reg_offset = 0x0,
+	.command_addr_mask = 0xFF0000,
+
+	.command_val_reg_offset = 0xC,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0x00,	/* Reserved */
+};
+
+static const struct vc_channel_regs omap5_ch_mm_regs = {
+	.cfg_reg_offset = 0x4,
+	.racen_mask = 0x8000000,
+	.rac_enable_mask = 0x4000000,
+	.rav_enable_mask = 0x2000000,
+	.cmd_sel_mask = 0x10000000,
+	.sa_enable_mask = 0x1000000,
+
+	.sa_reg_offset = 0x4,
+	.sa_addr_mask = 0x7f,
+
+	.voltage_reg_offset = 0x4,
+	.voltage_addr_mask = 0xFF00,
+
+	.command_addr_reg_offset = 0x4,
+	.command_addr_mask = 0xFF0000,
+
+	.command_val_reg_offset = 0x10,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0x00,	/* Reserved */
+};
+
+static const struct vc_channel_regs omap5_ch_mpu_regs = {
+	.cfg_reg_offset = 0x8,
+	.racen_mask = 0x8000000,
+	.rac_enable_mask = 0x4000000,
+	.rav_enable_mask = 0x2000000,
+	.cmd_sel_mask = 0x10000000,
+	.sa_enable_mask = 0x1000000,
+
+	.sa_reg_offset = 0x8,
+	.sa_addr_mask = 0x7f,
+
+	.voltage_reg_offset = 0x8,
+	.voltage_addr_mask = 0xFF00,
+
+	.command_addr_reg_offset = 0x8,
+	.command_addr_mask = 0xFF0000,
+
+	.command_val_reg_offset = 0x14,
+	.command_val_on_mask = 0xFF000000,
+	.command_val_onlp_mask = 0xFF0000,
+	.command_val_ret_mask = 0xFF00,
+	.command_val_off_mask = 0x00,	/* Reserved */
+};
+
+/* VC Generic register configurations */
+static const struct omap_vc_common_reg omap3_vc_regs = {
+	.i2c_clk_cfg_reg = -1,
+	/* NOTE: register is called I2C_CFG in TRM, but compatible with MODE */
+	.i2c_clk_mode_reg = 0x18,
+	.bypass_cmd_reg = 0x1C,
+};
+
+static const struct omap_vc_common_reg omap4_vc_regs = {
+	.i2c_clk_cfg_reg = 0x24,
+	.i2c_clk_mode_reg = 0x20,
+	.bypass_cmd_reg = 0x18,
+};
+
+static const struct omap_vc_common_reg omap5_vc_regs = {
+	.i2c_clk_cfg_reg = 0x30,
+	.i2c_clk_mode_reg = 0x2c,
+	.bypass_cmd_reg = 0x18,
+};
+
+/* VCBYPASS register bit definitions - No variance at all */
+#define VC_BYPASS_VALID_MASK	(0x01 << 24)
+#define VC_BYPASS_DATA_MASK	(0xff << 16)
+#define VC_BYPASS_REGADDR_MASK	(0xff << 8)
+#define VC_BYPASS_SA_MASK	(0x7f << 0)
+/* I2C_CLK_MODE register bit definitions - No variance at all */
+#define VC_MODE_REPEAT_START_MASK	BIT(4)
+#define VC_MODE_HSENABLE_MASK		BIT(3)
+#define VC_MODE_MCODE_MASK		(0x3 << 0)
+/* I2C_CLK_CONFIG register bit definitions - No variance at all */
+#define VC_CLK_CFG_HSSCLL_MASK		(0xff << 24)
+#define VC_CLK_CFG_HSSCLH_MASK		(0xff << 16)
+#define VC_CLK_CFG_SCLL_MASK		(0xff << 8)
+#define VC_CLK_CFG_SCLH_MASK		(0xff << 0)
+
+/* Stores the list containing all voltage controller channels */
+static LIST_HEAD(omap_vc_channel_list);
+static DEFINE_MUTEX(omap_vc_channel_list_mutex);
+
+/**
+ * omap_vc_channel_set_on_voltage() - Update the ON transition voltage
+ * @info:	channel info (must be valid pointer from
+ *		devm_omap_vc_channel_get)
+ * @uv:		ON voltage in micro volts.
+ *
+ * Updates the voltage that OMAP comes back to when resuming from a low
+ * power state. It is recommended to invoke this as part of voltage transition
+ * as the low power transitions are more performance sensitive that voltage
+ * transition path (part of DVFS).
+ *
+ * This needs to be invoked either as part of DVFS sequence or prior to
+ * attempting to enter low power state.
+ *
+ * NOTE: no extra error handling is performed to reduce overhead as much as
+ * sanely possible. No explicit locks are needed as regmap takes care of
+ * the same.
+ *
+ * Return: 0 if all operations are successful, else returns appropriate
+ * error value.
+ */
+int omap_vc_channel_set_on_voltage(struct omap_vc_channel_info *info, u32 uv)
+{
+	struct omap_vc *vc;
+	struct omap_vc_channel *vc_channel;
+	struct device *dev;
+	const struct vc_channel_regs *ch_regs;
+	struct omap_pmic *pmic;
+	struct omap_pmic_ops *ops;
+	struct regmap *regmap;
+	int ret = 0;
+	u32 val = 0;
+	u8 vsel;
+
+	if (!info) {
+		pr_err("Bad parameters\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	vc_channel = info->ch;
+	dev = vc_channel->dev;
+	ch_regs = vc_channel->ch_regs;
+	pmic = info->pmic;
+	ops = pmic->ops;
+
+	vc = dev_get_drvdata(dev->parent);
+	if (!vc) {
+		dev_err(dev, "Unable to find parent VC data\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = ops->uv_to_vsel(pmic, uv, &vsel);
+	if (ret) {
+		dev_err(dev, "%s: Conversion onV %d to vsel fail(%d)\n",
+			__func__, uv, ret);
+		goto out;
+	}
+	regmap = vc->regmap;
+
+	if (ch_regs->command_val_onlp_mask) {
+		val = vsel << __ffs(ch_regs->command_val_onlp_mask);
+		ret = regmap_update_bits(regmap,
+					 ch_regs->command_val_reg_offset,
+					 ch_regs->command_val_onlp_mask,
+					 val);
+	}
+	if (ret)
+		goto fail_reg;
+
+	if (ch_regs->command_val_on_mask) {
+		val = vsel << __ffs(ch_regs->command_val_on_mask);
+		ret = regmap_update_bits(regmap,
+					 ch_regs->command_val_reg_offset,
+					 ch_regs->command_val_on_mask, val);
+	}
+
+fail_reg:
+	if (ret)
+		dev_err(dev, "%s: Register operation failed with %d\n",
+			__func__, ret);
+out:
+	return ret;
+}
+EXPORT_SYMBOL_GPL(omap_vc_channel_set_on_voltage);
+
+/**
+ * omap_vc_channel_setup_lp() - Low power voltage configuration
+ * @vc_channel:	VC channel to configure for
+ * @vc:		VC to which this channel belongs to.
+ *
+ * The Low power states such as OFF, RETENTION are pre-determined SoC specific
+ * voltage values. These can be configured at boot time and the voltages are
+ * achieved as needed. This also configures the boot voltage as ON voltage if
+ * it is available.
+ */
+static int omap_vc_channel_setup_lp(struct omap_vc_channel *vc_channel,
+				    struct omap_vc *vc)
+{
+	struct device *dev = vc_channel->dev;
+	const struct vc_channel_regs *ch_regs = vc_channel->ch_regs;
+	struct regmap *regmap = vc->regmap;
+	struct omap_pmic *pmic = vc_channel->info.pmic;
+	struct omap_pmic_ops *ops = pmic->ops;
+	struct omap_vc_channel_info *info = &vc_channel->info;
+	int ret = 0;
+	u32 val;
+	u8 vsel;
+
+	if (ch_regs->command_val_off_mask) {
+		ret = ops->uv_to_vsel(pmic, info->off_uV, &vsel);
+		if (ret) {
+			dev_err(dev, "%s: Conversion OFF %d to vsel fail(%d)\n",
+				__func__, info->off_uV, ret);
+			goto out;
+		}
+		val = vsel << __ffs(ch_regs->command_val_off_mask);
+		ret = regmap_update_bits(regmap,
+					 ch_regs->command_val_reg_offset,
+					 ch_regs->command_val_off_mask, val);
+		if (ret)
+			goto fail_reg;
+	}
+
+	if (ch_regs->command_val_ret_mask) {
+		ret = ops->uv_to_vsel(pmic, info->retention_uV, &vsel);
+		if (ret) {
+			dev_err(dev, "%s: Conversion RET %d to vsel fail(%d)\n",
+				__func__, info->retention_uV, ret);
+			goto out;
+		}
+		val = vsel << __ffs(ch_regs->command_val_ret_mask);
+		ret = regmap_update_bits(regmap,
+					 ch_regs->command_val_reg_offset,
+					 ch_regs->command_val_ret_mask, val);
+		if (ret)
+			goto fail_reg;
+	}
+
+	if (pmic->boot_voltage_uV && (ch_regs->command_val_on_mask |
+				      ch_regs->command_val_onlp_mask)) {
+		ret = ops->uv_to_vsel(pmic, pmic->boot_voltage_uV, &vsel);
+		if (ret) {
+			dev_err(dev, "%s: Conversion ON %d to vsel fail(%d)\n",
+				__func__,  pmic->boot_voltage_uV, ret);
+			goto out;
+		}
+	}
+	if (pmic->boot_voltage_uV && ch_regs->command_val_on_mask) {
+		val = vsel << __ffs(ch_regs->command_val_on_mask);
+		ret = regmap_update_bits(regmap,
+					 ch_regs->command_val_reg_offset,
+					 ch_regs->command_val_on_mask, val);
+		if (ret)
+			goto fail_reg;
+	}
+
+	if (pmic->boot_voltage_uV && ch_regs->command_val_onlp_mask) {
+		val = vsel << __ffs(ch_regs->command_val_onlp_mask);
+		ret = regmap_update_bits(regmap,
+					 ch_regs->command_val_reg_offset,
+					 ch_regs->command_val_onlp_mask,
+					 val);
+	}
+
+fail_reg:
+	if (ret)
+		dev_err(dev, "%s: Register operation failed with %d\n",
+			__func__, ret);
+
+out:
+	return ret;
+}
+
+/**
+ * omap_vc_send_msg() - Send a VC bypass command
+ * @vc:		Voltage controller
+ * @vc_channel:	Voltage controller channel
+ * @reg_addr:	Register address to write to
+ * @data:	data to write.
+ *
+ * This bypasses all channel scheduling mechanisms inside Voltage controller
+ * and must be used sparingly in controlled environments. Using this to scale
+ * voltage is NOT a recommended procedure.
+ *
+ * The only safe usage is when Voltage Processors, SmartReflex, VFSM(PRCM)
+ * is in idle or known state - example at boot, this may be used for
+ * configuration.
+ */
+static int omap_vc_send_msg(struct omap_vc *vc,
+			    struct omap_vc_channel *vc_channel, u8 reg_addr,
+			    u8 data)
+{
+	struct device *dev = vc_channel->dev;
+	struct regmap *regmap = vc->regmap;
+	struct omap_pmic *pmic = vc_channel->info.pmic;
+	u32 loop_cnt = 0, retries_cnt = 0;
+	u32 vc_bypass_value;
+	int ret = 0;
+
+	ret = regmap_update_bits(regmap, vc->regs->bypass_cmd_reg,
+				 VC_BYPASS_DATA_MASK,
+				 data << __ffs(VC_BYPASS_DATA_MASK));
+	if (ret)
+		goto reg_fail;
+	ret = regmap_update_bits(regmap, vc->regs->bypass_cmd_reg,
+				 VC_BYPASS_REGADDR_MASK,
+				 reg_addr << __ffs(VC_BYPASS_REGADDR_MASK));
+	if (ret)
+		goto reg_fail;
+	ret = regmap_update_bits(regmap, vc->regs->bypass_cmd_reg,
+				 VC_BYPASS_SA_MASK,
+				 pmic->slave_addr << __ffs(VC_BYPASS_SA_MASK));
+	if (ret)
+		goto reg_fail;
+	/* Activate the transfer */
+	ret = regmap_update_bits(regmap, vc->regs->bypass_cmd_reg,
+				 VC_BYPASS_VALID_MASK, VC_BYPASS_VALID_MASK);
+	if (ret)
+		goto reg_fail;
+
+	/* See if transfer complete */
+	ret = regmap_read(regmap, vc->regs->bypass_cmd_reg, &vc_bypass_value);
+	if (ret)
+		goto reg_fail;
+
+	dev_dbg(dev,
+		"bypass_val = 0x%08x, sa=0x%02x, reg=0x%02x, data=0x%02x\n",
+		vc_bypass_value, pmic->slave_addr, reg_addr, data);
+
+	/*
+	 * Loop which polls continously 50 times before sleeping and retry
+	 * around for atleast pmic->i2c_timeout_us * 5. Rationale as follows:
+	 * 1) continuous poll loops for 50 times, if it cant get it, then (2)
+	 * 2) sleeps between 5-15 uSec. then try (1)
+	 * if it cant get in timeout_us *5 ish (in step 1) then give up
+	 *
+	 * The continous loop(1) is used because the first VALID setting
+	 * is expected to appear quiet fast. However, the delay occurs only
+	 * when VC internally does round robin scheduling between PRCM's VFSM,
+	 * VC channels (1-n) followed by vcbypass. Only if there is pending
+	 * transaction will the bypass valid bit get delayed, 99.99% of the
+	 * cases at this point in time(configuration and setup time), we do
+	 * not expect this conflict to take place.
+	 */
+	while (vc_bypass_value & VC_BYPASS_VALID_MASK) {
+		loop_cnt++;
+
+		/* Get at least 5 times pmic->i2c_timeout_us for completion */
+		if (retries_cnt > pmic->i2c_timeout_us) {
+			dev_err(dev, "%s: Retry count exceeded\n", __func__);
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (loop_cnt > 50) {
+			retries_cnt++;
+			loop_cnt = 0;
+			usleep_range(5, 15);
+		}
+		ret =
+		    regmap_read(regmap, vc->regs->bypass_cmd_reg,
+				&vc_bypass_value);
+		if (ret)
+			goto reg_fail;
+	}
+
+reg_fail:
+	if (ret)
+		dev_err(dev, "%s: register operation failed(%d)\n",
+			__func__, ret);
+
+out:
+	return ret;
+}
+
+/**
+ * omap_vc_channel_setup_pmic() - Setup PMIC configuration commands if any
+ * @vc_channel:	vc channel
+ * @vc:		vc
+ *
+ * Uses vc_bypass to send commands to the PMIC for mandatory configurations
+ * for the device to function.
+ */
+static int omap_vc_channel_setup_pmic(struct omap_vc_channel *vc_channel,
+				      struct omap_vc *vc)
+{
+	struct device *dev = vc_channel->dev;
+	struct omap_pmic *pmic = vc_channel->info.pmic;
+	struct omap_pmic_setup_commands *cmd;
+	int i, ret = 0;
+
+	if (!pmic->setup_num_commands)
+		return 0;
+	if (!pmic->setup_command_list) {
+		dev_err(dev, "Bad setup command list\n");
+		return -EINVAL;
+	}
+	cmd = pmic->setup_command_list;
+
+	for (i = 0; i < pmic->setup_num_commands; i++, cmd++) {
+		ret = omap_vc_send_msg(vc, vc_channel, cmd->reg, cmd->cmd_val);
+		if (ret) {
+			dev_err(dev, "Failed cmd [r=0x%02x v=0x%02x] [%d]\n",
+				cmd->reg, cmd->cmd_val, ret);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+/* Quick helper to avoid having to define /bits/ 8 <0x20> for 8 bit params */
+static inline int vc_property_read_u8(const struct device_node *np,
+				      const char *propname, u8 *out_value)
+{
+	u32 val;
+	int r;
+
+	r = of_property_read_u32(np, propname, &val);
+	if (r)
+		return r;
+
+	if (val > 0xFF)
+		return -ERANGE;
+
+	*out_value = (u8) val;
+	return 0;
+}
+
+/**
+ * omap_vc_channel_setup_sa() - setup Slave address
+ * @vc_channel:	vc channel
+ * @vc:		vc
+ *
+ * setups the slave address configuration as needed.
+ */
+static int omap_vc_channel_setup_sa(struct omap_vc_channel *vc_channel,
+				    struct omap_vc *vc)
+{
+	struct device *dev = vc_channel->dev;
+	const struct vc_channel_regs *ch_regs = vc_channel->ch_regs;
+	struct regmap *regmap = vc->regmap;
+	struct omap_pmic *pmic = vc_channel->info.pmic;
+	int ret;
+	u32 enable_mask = 0;
+
+	if (!vc_channel->use_master_channel_sa) {
+		u32 val;
+
+		val = pmic->slave_addr << __ffs(ch_regs->sa_addr_mask);
+		ret =
+		    regmap_update_bits(regmap, ch_regs->sa_reg_offset,
+				       ch_regs->sa_addr_mask, val);
+		if (ret)
+			goto out;
+
+		/* SA bit is never set for master */
+		if (!vc_channel->is_master_channel)
+			enable_mask = ch_regs->sa_enable_mask;
+	}
+
+	ret = regmap_update_bits(regmap, ch_regs->cfg_reg_offset,
+				 ch_regs->sa_enable_mask, enable_mask);
+
+out:
+	if (ret)
+		dev_err(dev, "%s: update reg failed(%d)\n", __func__, ret);
+
+	return ret;
+}
+
+/**
+ * omap_vc_channel_setup_voltage() - configure channel's voltage register addr
+ * @vc_channel:	vc channel
+ * @vc:		voltage controller
+ */
+static int omap_vc_channel_setup_voltage(struct omap_vc_channel *vc_channel,
+					 struct omap_vc *vc)
+{
+	struct device *dev = vc_channel->dev;
+	struct regmap *regmap = vc->regmap;
+	const struct vc_channel_regs *ch_regs = vc_channel->ch_regs;
+	struct omap_pmic *pmic = vc_channel->info.pmic;
+	int ret;
+	u32 enable_mask = 0;
+
+	if (!vc_channel->use_master_channel_voltage_reg) {
+		u32 val;
+
+		val =
+		    pmic->voltage_reg_addr << __ffs(ch_regs->voltage_addr_mask);
+		ret = regmap_update_bits(regmap, ch_regs->voltage_reg_offset,
+				       ch_regs->voltage_addr_mask, val);
+		if (ret)
+			goto out;
+
+		/* RAV bit is never set for master */
+		if (!vc_channel->is_master_channel)
+			enable_mask = ch_regs->rav_enable_mask;
+	}
+	ret = regmap_update_bits(regmap, ch_regs->cfg_reg_offset,
+				 ch_regs->rav_enable_mask, enable_mask);
+out:
+	if (ret)
+		dev_err(dev, "%s: update reg failed(%d)\n", __func__, ret);
+
+	return ret;
+}
+
+/**
+ * omap_vc_channel_setup_command() - configure channel's command register addr
+ * @vc_channel:	vc channel
+ * @vc:		voltage controller
+ */
+static int omap_vc_channel_setup_command(struct omap_vc_channel *vc_channel,
+					 struct omap_vc *vc)
+{
+	struct device *dev = vc_channel->dev;
+	struct regmap *regmap = vc->regmap;
+	const struct vc_channel_regs *ch_regs = vc_channel->ch_regs;
+	struct omap_pmic *pmic = vc_channel->info.pmic;
+	int ret;
+	u32 cmd_sel_mask = ch_regs->cmd_sel_mask;
+	u32 rac_enable_mask = 0;
+	u32 racen_mask = 0;
+
+	if (!vc_channel->use_master_channel_cmd_reg) {
+		u32 val;
+
+		val = pmic->cmd_reg_addr << __ffs(ch_regs->command_addr_mask);
+		ret =
+		    regmap_update_bits(regmap, ch_regs->command_addr_reg_offset,
+				       ch_regs->command_addr_mask, val);
+		if (ret)
+			goto out;
+
+		/* RAC bit is never set for master */
+		if (!vc_channel->is_master_channel)
+			rac_enable_mask = ch_regs->rac_enable_mask;
+	}
+
+	ret = regmap_update_bits(regmap, ch_regs->cfg_reg_offset,
+				 ch_regs->rac_enable_mask, rac_enable_mask);
+	if (ret)
+		goto out;
+
+	/* Retaining legacy logic - if needed for special case, switch to DT? */
+	if (pmic->cmd_reg_addr == pmic->voltage_reg_addr)
+		racen_mask = ch_regs->racen_mask;
+
+	ret = regmap_update_bits(regmap, ch_regs->cfg_reg_offset,
+				 ch_regs->racen_mask, racen_mask);
+	if (ret)
+		goto out;
+
+	/* CMD bit is never set for master */
+	if (vc_channel->is_master_channel ||
+	    vc_channel->use_master_channel_cmd_val)
+		cmd_sel_mask = 0;
+
+	ret = regmap_update_bits(regmap, ch_regs->cfg_reg_offset,
+				 ch_regs->cmd_sel_mask, cmd_sel_mask);
+out:
+	if (ret)
+		dev_err(dev, "%s: update reg failed(%d)\n", __func__, ret);
+
+	return ret;
+}
+
+/* Quick helper to find the OF node for a device matching to channel */
+static struct device_node *of_get_omap_vc_channel(struct device *dev)
+{
+	struct device_node *vc_channel_node = NULL;
+	char *prop_name = "ti,vc-channel";
+
+	dev_dbg(dev, "Looking up %s from device tree\n", prop_name);
+	vc_channel_node = of_parse_phandle(dev->of_node, prop_name, 0);
+
+	if (!vc_channel_node) {
+		dev_err(dev, "Looking up %s property in node %s failed",
+			prop_name, dev->of_node->full_name);
+		return ERR_PTR(-ENODEV);
+	}
+	return vc_channel_node;
+}
+
+/* Helper to cleanup when the managed device is released */
+static void devm_omap_vc_channel_release(struct device *dev, void *res)
+{
+	struct omap_vc_channel *vc_channel = *((struct omap_vc_channel **)res);
+
+	mutex_lock(&omap_vc_channel_list_mutex);
+
+	vc_channel->usage_count--;
+	if (!vc_channel->usage_count)
+		vc_channel->info.pmic = NULL;
+	module_put(vc_channel->dev->driver->owner);
+
+	mutex_unlock(&omap_vc_channel_list_mutex);
+
+	return;
+}
+
+/**
+ * devm_omap_vc_channel_get() - managed request to get a VC channel
+ * @dev:	Generic device to handle the request for
+ * @pmic:	PMIC resource this will be assigned to
+ *
+ * Ensures that usage count is maintained. Uses managed device,
+ * so everything is undone on driver detach.
+ *
+ * Return: -EPROBE_DEFER if the node is present, however device is
+ * not yet probed.
+ * -EINVAL if bad pointers or node description is not found.
+ * -ENODEV if the property cannot be found
+ * -ENOMEM if allocation could not be done.
+ *  device pointer to vp dev if all successful. error handling should be
+ *  performed with IS_ERR
+ */
+struct omap_vc_channel_info *devm_omap_vc_channel_get(struct device *dev,
+						      struct omap_pmic *pmic)
+{
+	struct omap_vc_channel *vc_channel, **ptr;
+	struct device_node *node;
+	struct device *vc_dev;
+	struct omap_vc_channel_info *info;
+	struct omap_vc *vc;
+	int ret = 0;
+
+	if (!dev || !dev->of_node || !pmic) {
+		pr_err("Invalid parameters\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	node = of_get_omap_vc_channel(dev);
+	if (IS_ERR(node))
+		return (void *)node;
+
+	mutex_lock(&omap_vc_channel_list_mutex);
+	list_for_each_entry(vc_channel, &omap_vc_channel_list, list)
+	    if (vc_channel->dev->of_node == node)
+		goto found;
+
+	/* Node definition is present, but not probed yet.. request defer */
+	info = ERR_PTR(-EPROBE_DEFER);
+	goto out_unlock;
+
+found:
+	vc_dev = vc_channel->dev;
+	if (!try_module_get(vc_dev->driver->owner)) {
+		dev_err(dev, "%s: Cant get device owner\n", __func__);
+		info = ERR_PTR(-EINVAL);
+		goto out_unlock;
+	}
+
+	/* Allow ONLY 1 user at a time */
+	if (vc_channel->usage_count) {
+		dev_err(dev, "%s: device %s is busy..\n", __func__,
+			dev_name(vc_dev));
+		ret = -EBUSY;
+		goto out;
+	}
+	ptr = devres_alloc(devm_omap_vc_channel_release, sizeof(*ptr),
+			   GFP_KERNEL);
+	if (!ptr) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	info = &vc_channel->info;
+
+	vc = dev_get_drvdata(vc_dev->parent);
+	if (!vc) {
+		dev_err(dev, "Unable to find parent VC data\n");
+		ret = -EINVAL;
+		goto out;
+	}
+	info->pmic = pmic;
+	ret = omap_vc_channel_setup_sa(vc_channel, vc);
+	if (ret)
+		goto out;
+
+	ret = omap_vc_channel_setup_voltage(vc_channel, vc);
+	if (ret)
+		goto out;
+
+	ret = omap_vc_channel_setup_command(vc_channel, vc);
+	if (ret)
+		goto out;
+
+	ret = omap_vc_channel_setup_pmic(vc_channel, vc);
+	if (ret)
+		goto out;
+
+	ret = omap_vc_channel_setup_lp(vc_channel, vc);
+	if (ret)
+		goto out;
+
+	if (vc_channel->is_master_channel)
+		vc->master_channel_configured = true;
+
+	*ptr = vc_channel;
+	vc_channel->usage_count++;
+	devres_add(dev, ptr);
+
+out:
+	if (ret) {
+		module_put(vc_dev->driver->owner);
+		info = ERR_PTR(ret);
+		dev_err(dev, "Failed setup vc with (%d)\n", ret);
+	}
+
+out_unlock:
+	mutex_unlock(&omap_vc_channel_list_mutex);
+
+	return info;
+}
+EXPORT_SYMBOL_GPL(devm_omap_vc_channel_get);
+
+static const struct of_device_id omap_vc_channel_of_match_tbl[] = {
+	{.compatible = "ti,omap3-vc-channel-0", .data = &omap3_ch_0_regs},
+	{.compatible = "ti,omap3-vc-channel-1", .data = &omap3_ch_1_regs},
+	{.compatible = "ti,omap4-vc-channel-mpu", .data = &omap4_ch_mpu_regs},
+	{.compatible = "ti,omap4-vc-channel-iva", .data = &omap4_ch_iva_regs},
+	{.compatible = "ti,omap4-vc-channel-core", .data = &omap4_ch_core_regs},
+	{.compatible = "ti,omap5-vc-channel-mpu", .data = &omap5_ch_mpu_regs},
+	{.compatible = "ti,omap5-vc-channel-mm", .data = &omap5_ch_mm_regs},
+	{.compatible = "ti,omap5-vc-channel-core", .data = &omap5_ch_core_regs},
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap_vc_channel_of_match_tbl);
+
+static int omap_vc_channel_probe(struct platform_device *pdev)
+{
+	struct device *vc_dev, *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct omap_vc *vc;
+	struct omap_vc_channel *vc_channel;
+	struct omap_vc_channel_info *info;
+	const struct of_device_id *match;
+
+	if (!node) {
+		dev_err(dev, "%s: no OF information?\n", __func__);
+		return -EINVAL;
+	}
+
+	match = of_match_device(omap_vc_channel_of_match_tbl, dev);
+	if (!match) {
+		/* We do not expect this to happen */
+		dev_err(dev, "%s: Unable to match device\n", __func__);
+		return -ENODEV;
+	}
+	if (!match->data) {
+		dev_err(dev, "%s: Bad data in match\n", __func__);
+		return -EINVAL;
+	}
+
+	if (!dev->parent) {
+		dev_err(dev, "%s: Unable to find parent VC device\n", __func__);
+		return -EINVAL;
+	}
+	vc_dev = dev->parent;
+
+	vc = dev_get_drvdata(vc_dev);
+	if (!vc) {
+		dev_err(dev, "%s: Unable to find parent VC data\n", __func__);
+		return -EINVAL;
+	}
+
+	vc_channel = devm_kzalloc(dev, sizeof(*vc_channel), GFP_KERNEL);
+	if (!vc_channel) {
+		dev_err(dev, "%s: Unable to allocate vc channel\n", __func__);
+		return -ENOMEM;
+	}
+	vc_channel->dev = dev;
+	vc_channel->ch_regs = match->data;
+	info = &vc_channel->info;
+	info->ch = vc_channel;
+
+	/* Pick up optional parameters */
+	of_property_read_u32(node, "ti,retention-micro-volts",
+			     &info->retention_uV);
+	of_property_read_u32(node, "ti,off-micro-volts", &info->off_uV);
+
+	vc_channel->is_master_channel =
+	    of_property_read_bool(node, "ti,master-channel");
+	if (vc_channel->is_master_channel && vc->master_channel_configured) {
+		dev_err(dev, "There can only be a single master channel!\n");
+		return -EINVAL;
+	}
+	vc_channel->use_master_channel_sa =
+	    of_property_read_bool(node, "ti,use-master-slave-addr");
+	vc_channel->use_master_channel_voltage_reg =
+	    of_property_read_bool(node, "ti,use-master-voltage-reg-addr");
+	vc_channel->use_master_channel_cmd_reg =
+	    of_property_read_bool(node, "ti,use-master-command-reg-addr");
+	vc_channel->use_master_channel_cmd_val =
+	    of_property_read_bool(node, "ti,use-master-command-reg-val");
+
+	if (vc_channel->is_master_channel &&
+	    (vc_channel->use_master_channel_sa ||
+	     vc_channel->use_master_channel_voltage_reg ||
+	     vc_channel->use_master_channel_cmd_reg ||
+	     vc_channel->use_master_channel_cmd_val)) {
+		dev_err(dev, "Master channel cannot route to slave channel!\n");
+		return -EINVAL;
+	}
+	if (!vc->master_channel_configured &&
+	    (vc_channel->use_master_channel_sa ||
+	     vc_channel->use_master_channel_voltage_reg ||
+	     vc_channel->use_master_channel_cmd_reg ||
+	     vc_channel->use_master_channel_cmd_val)) {
+		dev_dbg(dev, "Deferring - Master channel not yet ready!\n");
+		return -EPROBE_DEFER;
+	}
+
+	platform_set_drvdata(pdev, vc_channel);
+
+	/* Add it to VC channel list */
+	mutex_lock(&omap_vc_channel_list_mutex);
+	list_add(&vc_channel->list, &omap_vc_channel_list);
+	mutex_unlock(&omap_vc_channel_list_mutex);
+
+	return 0;
+}
+
+/**
+ * omap_vc_channel_remove() - Cleanup operations for channel
+ * @pdev:	platform device
+ *
+ * Return: -EBUSY if all users have not transitioned out, else return 0
+ */
+static int omap_vc_channel_remove(struct platform_device *pdev)
+{
+	struct omap_vc_channel *vc_channel = platform_get_drvdata(pdev);
+	int ret = 0;
+
+	mutex_lock(&omap_vc_channel_list_mutex);
+	list_del(&vc_channel->list);
+	mutex_unlock(&omap_vc_channel_list_mutex);
+
+	return ret;
+}
+
+static struct platform_driver omap_vc_channel_driver = {
+	.driver = {
+		   .name = DRIVER_NAME "-channel",
+		   .owner = THIS_MODULE,
+		   .of_match_table = of_match_ptr(omap_vc_channel_of_match_tbl),
+		   },
+	.probe = omap_vc_channel_probe,
+	.remove = omap_vc_channel_remove,
+};
+
+/* Regular 32 bit registers for Voltage controller */
+static struct regmap_config omap_vc_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+/**
+ * omap_vc_i2c_config() - configure the I2C clock and Mode registers
+ * @vc:		voltage controller
+ * @i2c_config:	i2c configuration to configure
+ */
+static int omap_vc_i2c_config(struct omap_vc *vc,
+			 struct omap_omap_vc_i2c_config *i2c_config)
+{
+	u32 mask;
+
+	mask = VC_MODE_HSENABLE_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_mode_reg, mask,
+			   i2c_config->highspeed << __ffs(mask));
+	mask = VC_MODE_MCODE_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_mode_reg, mask,
+			   i2c_config->mcode << __ffs(mask));
+	/* Disable repeated start */
+	mask = VC_MODE_REPEAT_START_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_mode_reg, mask, 0);
+
+	/* if there is clock config register on the SoC, skip.. */
+	if (vc->regs->i2c_clk_cfg_reg < 0)
+		return 0;
+
+	if (!i2c_config->i2c_clk_hsscll &&
+	    !i2c_config->i2c_clk_hssclh &&
+	    !i2c_config->i2c_clk_scll && !i2c_config->i2c_clk_sclh)
+		return -EINVAL;
+
+	/* Configure up clk timings */
+	mask = VC_CLK_CFG_HSSCLL_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_cfg_reg, mask,
+			   i2c_config->i2c_clk_hsscll << __ffs(mask));
+	mask = VC_CLK_CFG_HSSCLH_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_cfg_reg, mask,
+			   i2c_config->i2c_clk_hssclh << __ffs(mask));
+	mask = VC_CLK_CFG_SCLL_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_cfg_reg, mask,
+			   i2c_config->i2c_clk_scll << __ffs(mask));
+	mask = VC_CLK_CFG_SCLH_MASK;
+	regmap_update_bits(vc->regmap, vc->regs->i2c_clk_cfg_reg, mask,
+			   i2c_config->i2c_clk_sclh << __ffs(mask));
+	return 0;
+}
+
+/**
+ * struct i2c_load_data - table mapping load to clock configs
+ * @load:	load of the I2C bus
+ * @hsscll_38_4:	38.4MHz Sysclk HSSCLL configuration
+ * @hsscll_26:		26MHz Sysclk HSSCLL configuration
+ * @hsscll_19_2:	19.2MHz Sysclk HSSCLL configuration
+ * @hsscll_16_8:	16.8MHz Sysclk HSSCLL configuration
+ * @hsscll_12:		12MHz Sysclk HSSCLL configuration
+ *
+ * Instead of doing an hard multi-parameter computation, if load is provided by
+ * OF data then we pick the values from the table, There is always an option
+ * of defining the clocks from OF data itself.
+ */
+struct i2c_load_data {
+	u8 load;
+	u8 hsscll_38_4;
+	u8 hsscll_26;
+	u8 hsscll_19_2;
+	u8 hsscll_16_8;
+	u8 hsscll_12;
+};
+
+/**
+ * omap_vc_i2c_timing_init() - sets up board I2C timing parameters
+ * @dev:	vc channel device
+ * @cfg:	I2C configuration
+ *
+ * Use PMIC + board supplied settings for calculating the total I2C channel
+ * capacitance and set the timing parameters based on this. Pre-calculated
+ * values are provided in data tables, as it is not too straightforward to
+ * calculate these runtime.
+ */
+static int omap_vc_i2c_timing_init(struct device *dev,
+				   struct omap_omap_vc_i2c_config *cfg)
+{
+	u32 capacitance;
+	u16 hsscll;
+	const struct i2c_load_data i2c_timing_data[] = {
+		{
+		 .load = 50,
+		 .hsscll_38_4 = 13,
+		 .hsscll_26 = 11,
+		 .hsscll_19_2 = 9,
+		 .hsscll_16_8 = 9,
+		 .hsscll_12 = 8,
+		 },
+		{
+		 .load = 25,
+		 .hsscll_38_4 = 13,
+		 .hsscll_26 = 11,
+		 .hsscll_19_2 = 9,
+		 .hsscll_16_8 = 9,
+		 .hsscll_12 = 8,
+		 },
+		{
+		 .load = 12,
+		 .hsscll_38_4 = 11,
+		 .hsscll_26 = 10,
+		 .hsscll_19_2 = 9,
+		 .hsscll_16_8 = 9,
+		 .hsscll_12 = 8,
+		 },
+		{
+		 .load = 0,
+		 .hsscll_38_4 = 12,
+		 .hsscll_26 = 10,
+		 .hsscll_19_2 = 9,
+		 .hsscll_16_8 = 8,
+		 .hsscll_12 = 8,
+		 },
+	};
+	const struct i2c_load_data *i2c_data;
+
+	if (!cfg->i2c_clk_pad_load && !cfg->i2c_clk_pcb_length)
+		return 0;
+
+	/* PCB trace capacitance, 0.125pF / mm => mm / 8 */
+	capacitance = DIV_ROUND_UP(cfg->i2c_clk_pcb_length, 8);
+
+	/* OMAP pad capacitance */
+	capacitance += 4;
+
+	/* PMIC pad capacitance */
+	capacitance += cfg->i2c_clk_pad_load;
+
+	/* Search for capacitance match in the table */
+	i2c_data = i2c_timing_data;
+
+	while (i2c_data->load > capacitance)
+		i2c_data++;
+
+	/* Select proper values based on sysclk frequency */
+	switch (cfg->clk_rate) {
+	case 38400000:
+		hsscll = i2c_data->hsscll_38_4;
+		break;
+	case 26000000:
+		hsscll = i2c_data->hsscll_26;
+		break;
+	case 19200000:
+		hsscll = i2c_data->hsscll_19_2;
+		break;
+	case 16800000:
+		hsscll = i2c_data->hsscll_16_8;
+		break;
+	case 12000000:
+		hsscll = i2c_data->hsscll_12;
+		break;
+	default:
+		dev_err(dev, "%s: Unsupported sysclk rate: %ld!\n", __func__,
+			cfg->clk_rate);
+		return -ERANGE;
+	}
+
+	/* HSSCLH can always be zero */
+	cfg->i2c_clk_hssclh = 0x0;
+	cfg->i2c_clk_hsscll = hsscll;
+	/* FS timing - standard */
+	cfg->i2c_clk_scll = 0x28;
+	cfg->i2c_clk_sclh = 0x2C;
+
+	return 0;
+}
+
+static const struct of_device_id omap_vc_of_match_tbl[] = {
+	{.compatible = "ti,omap3-vc", .data = &omap3_vc_regs,},
+	{.compatible = "ti,omap4-vc", .data = &omap4_vc_regs,},
+	{.compatible = "ti,omap5-vc", .data = &omap5_vc_regs,},
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap_vc_of_match_tbl);
+
+static int omap_vc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct omap_vc *vc;
+	struct omap_omap_vc_i2c_config i2c_config = { 0 };
+	int ret;
+	struct resource *res;
+	char *pname;
+	struct clk *clk;
+	void __iomem *base;
+	struct regmap *regmap;
+	struct device_node *node = dev->of_node;
+	const struct of_device_id *match;
+
+	if (!node) {
+		dev_err(dev, "no OF information?\n");
+		return -EINVAL;
+	}
+
+	match = of_match_device(omap_vc_of_match_tbl, dev);
+	if (!match) {
+		/* We do not expect this to happen */
+		dev_err(dev, "%s: Unable to match device\n", __func__);
+		return -ENODEV;
+	}
+	if (!match->data) {
+		dev_err(dev, "%s: Bad data in match\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Read mandatory parameters */
+	clk = clk_get(dev, NULL);
+	if (IS_ERR(clk)) {
+		ret = PTR_ERR(clk);
+		dev_err(dev, "%s: Unable to get clk(%d)\n", __func__, ret);
+		return ret;
+	}
+	i2c_config.clk_rate = clk_get_rate(clk);
+	/* We do not need the clock any more */
+	clk_put(clk);
+
+	pname = "base-address";
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pname);
+	base = devm_request_and_ioremap(dev, res);
+	if (!base) {
+		dev_err(dev, "Unable to map '%s'\n", pname);
+		return -EADDRNOTAVAIL;
+	}
+
+	regmap = devm_regmap_init_mmio(dev, base, &omap_vc_regmap_config);
+	if (IS_ERR(regmap)) {
+		ret = PTR_ERR(regmap);
+		dev_err(dev, "regmap init failed(%d)\n", ret);
+		return ret;
+	}
+
+	/* Read optional highspeed mode param */
+	pname = "ti,i2c-high-speed";
+	i2c_config.highspeed = of_property_read_bool(node, pname);
+
+	/* Mcode if the platform likes to set it explicitly */
+	if (i2c_config.highspeed)
+		vc_property_read_u8(node, "ti,i2c-high-speed-mcode",
+				    &i2c_config.mcode);
+
+	if (i2c_config.highspeed) {
+		pname = "ti,i2c-pad-load";
+		of_property_read_u32(node, pname, &i2c_config.i2c_clk_pad_load);
+		pname = "ti,i2c-pcb-length";
+		of_property_read_u32(node, pname,
+				     &i2c_config.i2c_clk_pcb_length);
+
+		if (i2c_config.i2c_clk_pad_load) {
+			if (!i2c_config.i2c_clk_pcb_length)
+				i2c_config.i2c_clk_pcb_length = 63;
+
+			ret = omap_vc_i2c_timing_init(dev, &i2c_config);
+			if (ret)
+				goto out;
+
+			goto skip_i2c_clk_config;
+		}
+	}
+
+	/* So, we do not have pad load defined, expect proper timing config */
+	pname = "ti,i2c-clk-scl-low";
+	ret = vc_property_read_u8(node, pname, &i2c_config.i2c_clk_scll);
+	if (ret)
+		goto invalid_of_property;
+
+	pname = "ti,i2c-clk-scl-high";
+	ret = vc_property_read_u8(node, pname, &i2c_config.i2c_clk_sclh);
+	if (ret)
+		goto invalid_of_property;
+
+	pname = "ti,i2c-clk-hsscl-low";
+	ret = vc_property_read_u8(node, pname, &i2c_config.i2c_clk_hsscll);
+	if (ret && i2c_config.highspeed)
+		goto invalid_of_property;
+
+	pname = "ti,i2c-clk-hsscl-high";
+	ret = vc_property_read_u8(node, pname, &i2c_config.i2c_clk_hssclh);
+	if (ret && i2c_config.highspeed)
+		goto invalid_of_property;
+
+skip_i2c_clk_config:
+	vc = devm_kzalloc(dev, sizeof(*vc), GFP_KERNEL);
+	if (!vc) {
+		dev_err(dev, "unable to allocate vc\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+	vc->regmap = regmap;
+	vc->regs = match->data;
+
+	ret = omap_vc_i2c_config(vc, &i2c_config);
+	if (ret) {
+		dev_err(dev, "Bad I2C configuration: %d\n", ret);
+		goto out;
+	}
+
+	platform_set_drvdata(pdev, vc);
+	ret = of_platform_populate(dev->of_node,
+				   omap_vc_channel_of_match_tbl, NULL, dev);
+
+	if (ret)
+		dev_err(dev, "Failed to create DT children: %d\n", ret);
+
+out:
+	return ret;
+
+invalid_of_property:
+	dev_err(dev, "Missing/Invalid '%s' property - error(%d)\n", pname, ret);
+	return ret;
+}
+
+static struct platform_driver omap_vc_driver = {
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   .of_match_table = of_match_ptr(omap_vc_of_match_tbl),
+		   },
+	.probe = omap_vc_probe,
+};
+
+static int __init omap_vc_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&omap_vc_driver);
+	if (ret) {
+		pr_err("%s: platform driver register failed for VC\n",
+			__func__);
+		return ret;
+	}
+
+	ret = platform_driver_register(&omap_vc_channel_driver);
+	if (ret) {
+		pr_err("%s: platform driver register failed for VC\n",
+			__func__);
+		return ret;
+	}
+
+	return 0;
+}
+module_init(omap_vc_init);
+
+static void __exit omap_vc_exit(void)
+{
+	platform_driver_unregister(&omap_vc_channel_driver);
+	platform_driver_unregister(&omap_vc_driver);
+}
+module_exit(omap_vc_exit);
+
+MODULE_DESCRIPTION("OMAP Voltage Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc.");
diff --git a/drivers/power/avs/omap_vc.h b/drivers/power/avs/omap_vc.h
new file mode 100644
index 0000000..11503b0
--- /dev/null
+++ b/drivers/power/avs/omap_vc.h
@@ -0,0 +1,67 @@
+/*
+ * OMAP Voltage Controller (VC) interface exported functions
+ *
+ * Idea based on arch/arm/mach-omap2/vc.h
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak at ti.com>
+ * Lesly A M <x0080970 at ti.com>
+ * Thara Gopinath <thara at ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ * Grygorii Strashko
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _POWER_AVS_OMAP_VC_H
+#define _POWER_AVS_OMAP_VC_H
+
+struct omap_pmic;
+/* Internal to VC */
+struct omap_vc_channel;
+
+/**
+ * struct omap_vc_channel_info - Channel information visible to users
+ * @pmic:		PMIC pointer
+ * @retention_uV:	retention voltage in micro volts
+ * @off_uV:		OFF voltage in micro volts
+ */
+struct omap_vc_channel_info {
+	struct omap_pmic *pmic;
+	u32 retention_uV;
+	u32 off_uV;
+	/* private: */
+	/* Used internally by Voltage Controller driver */
+	struct omap_vc_channel *ch;
+};
+
+#if IS_ENABLED(CONFIG_POWER_TI_HARDWARE_VOLTAGE_CONTROL)
+struct omap_vc_channel_info *devm_omap_vc_channel_get(struct device *dev,
+						      struct omap_pmic *pmic);
+int omap_vc_channel_set_on_voltage(struct omap_vc_channel_info *info, u32 uv);
+#else
+struct inline omap_vc_channel_info *
+	devm_omap_vc_channel_get(struct device *dev, struct omap_pmic *pmic)
+{
+	return ERR_PTR(-ENODEV);
+}
+
+static inline int omap_vc_channel_set_on_voltage(struct omap_vc_channel_info
+						 *info, u32 uv)
+{
+	return -ENODEV;
+}
+#endif
+
+#endif				/* _POWER_AVS_OMAP_VC_H */
-- 
1.7.9.5



From deller at gmx.de  Wed May 22 14:19:37 2013
From: deller at gmx.de (Helge Deller)
Date: Wed, 22 May 2013 20:19:37 +0200
Subject: [PATCH v2 0/4] dma-mapping: Define dma_{alloc,free}_attrs() for
 all archs
In-Reply-To: <519C2F5D.8000809@igel.co.jp>
References: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
 <519C2F5D.8000809@igel.co.jp>
Message-ID: <519D0C39.6090201@gmx.de>

On 05/22/2013 04:37 AM, Damian Hobson-Garcia wrote:
> Hello,
> On 2013/04/30 12:01, Damian Hobson-Garcia wrote:
>> Most architectures that define CONFIG_HAVE_DMA=y, have implementations for
>> both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
>> not define CONFIG_HAVE_DMA also have both of these definitions provided by
>> dma-mapping-broken.h.
>>
>> Provide a default definition for the archs that define CONFIG_HAVE_DMA=y,
>> but have no implementation for dma_{alloc,free}_attrs(). 
>>
>> As I don't have hardware for any of these systems, the patches are only
>> compile-tested where I could (arm64, s390) and untested for the archs
>> where I couldn't find a readily available prebuilt cross-compiler (c6x, parisc).
>>
> 
> 
>>  arch/arm64/include/asm/dma-mapping.h  |   17 +++++++++++------
>>  arch/c6x/include/asm/dma-mapping.h    |    3 +++
>>  arch/parisc/include/asm/dma-mapping.h |    3 +++
>>  arch/s390/include/asm/dma-mapping.h   |   17 +++++++++++------
>>  4 files changed, 28 insertions(+), 12 deletions(-)
>>
> 
> Since this series spans several architectures, what would be the best
> way to have this patch series merged?
> Should I resubmit each patch to the mailing list for each architecture
> separately?

I already pushed the parisc change upstream.
See commit 7f64fb41aad9a8504dd76e81b2391eae64e1498a

Helge


From jgunthorpe at obsidianresearch.com  Wed May 22 14:19:53 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Wed, 22 May 2013 12:19:53 -0600
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522185757.60091a66@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
Message-ID: <20130522181953.GD12320@obsidianresearch.com>

On Wed, May 22, 2013 at 06:57:57PM +0200, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Wed, 22 May 2013 12:49:36 -0400, Jason Cooper wrote:
> 
> > > As far as I know, a DT-capable bootloader doesn't pass any ATAG. The
> > > ARM register that was used to pass the pointer to the ATAGS is now used
> > > to pass the pointer to the DTB in memory.
> > 
> > So we could look for the ATAG magic or the dtb magic at that address,
> > then we know if we have an old or new bootloader...
> 
> No, because you can use an old bootloader, and still do some old-style
> appended-DTB booting, in which case you have a new bootloader
> (registers mapped at 0xf1), but you see the ATAG magic, which will make
> you think you booted from an old bootloader (registers mapped at 0xd0).

Just to chime in a bit here.. We also hit this problem on Kirkwood,
and fixed it in the bootloader. The power on default for Kirkwood
chips is 0xd0000000 and Linux has long required the bootloader to move
it.. Not sure why 370/XP dropped this.

Also, can you talk abit more about how this works to give more low DDR
memory? The docs say you can't overlap windows, and DDR CS's have a
power of two size/alignment requirement.

Does this mean the desire is to place a DDR CS from 3G -> 3.5G?

> For example, I'm currently booting alternatively with an old and a new
> bootloader (to test that things work properly), and in both cases I'm
> booting old style, DTB-appended, with ATAGs.

IMHO the DTB must match both the hardware *and* the bootloader. The
bootloader is setting the address map, the DTB contains that address
map, they must all match together.

Using a DTB property really is the right way to go.

Yes, I realize this means you now need to vary the DTB you will use
depending on boot loader version (see below)

To use a DTB property, the approach would be to make the internal regs
base address inside the kernel dynamic instead of hard coded. Do not
remap the internal regs, just use whatever the bootloader setup
directly. The kernel can early parse the FDT to find the correct
address, instead of hardwiring an arbitary base address.

Also, the blind remapping approach in these patches is sketchy. If the
bootloader has placed some other mapping at the 0xf1.. target address
this will blow up. The mbus driver gets it right, to change the window
layout you have to clear out and disable all window registers except
for internal, then rebuild the entire mapping from scratch to avoid
address overlap conflicts. That approach doesn't seem possible from
early assembly.. :(

All things considered, I think it is much safer and cleaner to make
the physical base of internal regs dynamic within the kernel, than to
try and relocate it during early boot.

So, please consider this instead. The kernel has functions already to
parse the fdt directly, they can be called before anything attempts to
map internal regs based stuff.

You can combine this idea with the CP15 signalling mechanism. Check
CP15 and use it to alter the DTB, similar to how ATAGs are used to
fixup the DTB. Don't relocate the registers.

Jason


From jgunthorpe at obsidianresearch.com  Wed May 22 14:24:48 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Wed, 22 May 2013 12:24:48 -0600
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <519D0143.1000203@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
 <519D0143.1000203@gmail.com>
Message-ID: <20130522182448.GA17206@obsidianresearch.com>

On Wed, May 22, 2013 at 07:32:51PM +0200, Sebastian Hesselbarth wrote:
 
> Not neccessary anyway, after talking Jason C in a Kirkwood-only
> workaround I prepared a patch that reads mac address registers early
> and stores it in the local-mac-address property.

That sounds great, but, FWIW, our bootloaders don't set the MAC
address registers. Does the work around only trigger if the
local-mac-address property is 0?

Jason


From andrew at lunn.ch  Wed May 22 14:31:05 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 20:31:05 +0200
Subject: [PATCH 9/9] arm: mvebu: switch internal register address at
 runtime if needed
In-Reply-To: <20130522195942.33ff1131@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369132414-18959-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522174258.GO2824@lunn.ch> <20130522195942.33ff1131@skate>
Message-ID: <20130522183105.GQ26249@lunn.ch>

> > > +		/*
> > > +		 * Change the physical base address of the
> > > +		 * registers. From now on, and until
> > > +		 * debug_ll_io_init() is called below, it is not
> > > +		 * possible to do any print, because earlyprintk will
> > > +		 * not work.
> > 
> > Is its "not work" or "locks up the CPU as dead as a Dodo?".
> 
> locks up the CPU as a Dodo

Then i would suggest something a bit strong than "will not work".

     Andrew


From sebastian.hesselbarth at gmail.com  Wed May 22 14:44:20 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 20:44:20 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130522174815.GI31290@titan.lakedaemon.net>
References: <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com> <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net> <519D038C.9000605@gmail.com>
 <20130522174815.GI31290@titan.lakedaemon.net>
Message-ID: <519D1204.4090701@gmail.com>

On 05/22/2013 07:48 PM, Jason Cooper wrote:
> On Wed, May 22, 2013 at 07:42:36PM +0200, Sebastian Hesselbarth wrote:
>> Hmm, maybe a little bit too early. While restoring the MAC address now
>> works, another bug arises which I guess is related with phy setup
>> and aneg.
>>
>> Will investigate and update patch set accordingly.
>
> Cool, chances are, we should be able to take that patch in by itself for
> this merge window...

Which patch do you mean? The local-mac-address workaround will only be
available for DT mv643xx_eth because it uses the DT node to store the
MAC.

Anyway, I found the bit that caused the other issue. It is the
Clk125_Bypass_En bit in PORT_SERIAL_CONTROL1 register. What bothers me
about it is:
- Only Dove and Kirkwood have the bit, MV78x00 doesn't have it, Orion5x
   doesn't have the register at all. With ppc mv64x60 I can only guess,
   but think it is like in Orion5x.
- Reset value of that bit should be 0, but after gating clock on
   Kirkwood it is set to 1 causing wrong port clock to be selected.
   Also Thomas Petazzoni confirmed that it is set after reset so
   either FS is wrong about it or BootROM messes with it.
- Kirkwood and Dove FS tell me that port link must be down when you
   change the bit.

As I can't be sure about how mv643xx_eth will behave on other platforms
except Kirkwood and Dove when writing that register, I tend to force
that bit to zero in the driver but only for those two by #ifdefs.

Sebastian


From jason at lakedaemon.net  Wed May 22 14:49:36 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 14:49:36 -0400
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <519D1204.4090701@gmail.com>
References: <519C9333.20609@gmail.com> <519C9822.9040909@windriver.com>
 <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
 <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net>
 <519D038C.9000605@gmail.com>
 <20130522174815.GI31290@titan.lakedaemon.net>
 <519D1204.4090701@gmail.com>
Message-ID: <20130522184936.GK31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 08:44:20PM +0200, Sebastian Hesselbarth wrote:
> On 05/22/2013 07:48 PM, Jason Cooper wrote:
> >On Wed, May 22, 2013 at 07:42:36PM +0200, Sebastian Hesselbarth wrote:
> >>Hmm, maybe a little bit too early. While restoring the MAC address now
> >>works, another bug arises which I guess is related with phy setup
> >>and aneg.
> >>
> >>Will investigate and update patch set accordingly.
> >
> >Cool, chances are, we should be able to take that patch in by itself for
> >this merge window...
> 
> Which patch do you mean? The local-mac-address workaround will only be
> available for DT mv643xx_eth because it uses the DT node to store the
> MAC.

I thought you were replacing the unconditional ethernet clock grabbing
with reading the mac from the registers and updating the dtb?  In
mach-kirkwood/board-dt.c?

confused. :-/

Jason.


From sebastian.hesselbarth at gmail.com  Wed May 22 14:51:26 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 20:51:26 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130522182448.GA17206@obsidianresearch.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com> <519D0143.1000203@gmail.com>
 <20130522182448.GA17206@obsidianresearch.com>
Message-ID: <519D13AE.4020807@gmail.com>

On 05/22/2013 08:24 PM, Jason Gunthorpe wrote:
> On Wed, May 22, 2013 at 07:32:51PM +0200, Sebastian Hesselbarth wrote:
>> Not neccessary anyway, after talking Jason C in a Kirkwood-only
>> workaround I prepared a patch that reads mac address registers early
>> and stores it in the local-mac-address property.
>
> That sounds great, but, FWIW, our bootloaders don't set the MAC
> address registers. Does the work around only trigger if the
> local-mac-address property is 0?

I already thought about bootloaders not setting the register, but I will
not start parsing 1001 places for a valid MAC only for those. Also
reading the MAC address registers is default behavior of mv643xx_eth if
no MAC address is passed through platform_data.

But you are right, there is plenty of sanity checks in the workaround to
ensure that local-mac-address is only overwritten by it when
- you are on DT
- there is no valid MAC address in that node (of_get_mac_address)
- there is a local-mac-address property with a length of 6 bytes

So this workaround only applies on DT booted kernels with no mac set in
DT.

Sebastian


From sebastian.hesselbarth at gmail.com  Wed May 22 14:55:01 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 20:55:01 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130522184936.GK31290@titan.lakedaemon.net>
References: <519C9333.20609@gmail.com> <519C9822.9040909@windriver.com>
 <519C9A66.3050807@gmail.com> <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com> <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net> <519D038C.9000605@gmail.com>
 <20130522174815.GI31290@titan.lakedaemon.net> <519D1204.4090701@gmail.com>
 <20130522184936.GK31290@titan.lakedaemon.net>
Message-ID: <519D1485.50801@gmail.com>

On 05/22/2013 08:49 PM, Jason Cooper wrote:
> On Wed, May 22, 2013 at 08:44:20PM +0200, Sebastian Hesselbarth wrote:
>> On 05/22/2013 07:48 PM, Jason Cooper wrote:
>>> On Wed, May 22, 2013 at 07:42:36PM +0200, Sebastian Hesselbarth wrote:
>>>> Hmm, maybe a little bit too early. While restoring the MAC address now
>>>> works, another bug arises which I guess is related with phy setup
>>>> and aneg.
>>>>
>>>> Will investigate and update patch set accordingly.
>>>
>>> Cool, chances are, we should be able to take that patch in by itself for
>>> this merge window...
>>
>> Which patch do you mean? The local-mac-address workaround will only be
>> available for DT mv643xx_eth because it uses the DT node to store the
>> MAC.
>
> I thought you were replacing the unconditional ethernet clock grabbing
> with reading the mac from the registers and updating the dtb?  In
> mach-kirkwood/board-dt.c?

True. But there is no node for ethernet controllers in kirkwood.dtsi
yet. It will be there with mv643xx_eth DT patches applied and that is
when the corresponding replacement patch should also be taken in.

I was just confused about your referral to the merge window, because I
guess it is up to David Miller to decide when/whether to take
mv643xx_eth patches in.

Sebastian



From andrew at lunn.ch  Wed May 22 14:55:21 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 20:55:21 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522181953.GD12320@obsidianresearch.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522181953.GD12320@obsidianresearch.com>
Message-ID: <20130522185521.GR26249@lunn.ch>

> Just to chime in a bit here.. We also hit this problem on Kirkwood,
> and fixed it in the bootloader. The power on default for Kirkwood
> chips is 0xd0000000 and Linux has long required the bootloader to move
> it.. Not sure why 370/XP dropped this.
> 
> Also, can you talk abit more about how this works to give more low DDR
> memory? The docs say you can't overlap windows, and DDR CS's have a
> power of two size/alignment requirement.
> 
> Does this mean the desire is to place a DDR CS from 3G -> 3.5G?
> 
> > For example, I'm currently booting alternatively with an old and a new
> > bootloader (to test that things work properly), and in both cases I'm
> > booting old style, DTB-appended, with ATAGs.
> 
> IMHO the DTB must match both the hardware *and* the bootloader. The
> bootloader is setting the address map, the DTB contains that address
> map, they must all match together.
> 
> Using a DTB property really is the right way to go.

Interesting you said that, yet for your kirkwood, you hacked your
bootloader rather than Linux.

I think in practice, it is not going to be easy to match the DTB to
the hardware and the bootloader. Look at debians flash-kernel, used to
prepare the kernel for an embedded system. For each target it has a
database entry:

Machine: Globalscale Technologies Dreamplug
Kernel-Flavors: kirkwood
DTB-Id: kirkwood-dreamplug.dtb
DTB-Append: yes
U-Boot-Kernel-Address: 0x00008000
U-Boot-Initrd-Address: 0x0
Boot-Device: /dev/sda1
Boot-Kernel-Path: uImage
Boot-Initrd-Path: uInitrd
Boot-DTB-Path: dtb
Required-Packages: u-boot-tools
Bootloader-sets-root: no

So it appends the kirkwood-dreamplug.dtb blob to the kernel.  What you
are saying is that it also needs to somehow query the version of uboot
running on the hardware so it can pick the correct dtb blob from a
collection of kirkwood-dreamplug.dtb blobs and append it to the
kernel.

Is it even possible to query the uboot version from Linux?

To keep the problems tractable, we should not really be dependent on
the bootloader version.

    Andrew


From jason at lakedaemon.net  Wed May 22 14:58:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 14:58:35 -0400
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <519D1485.50801@gmail.com>
References: <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com>
 <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net>
 <519D038C.9000605@gmail.com>
 <20130522174815.GI31290@titan.lakedaemon.net>
 <519D1204.4090701@gmail.com>
 <20130522184936.GK31290@titan.lakedaemon.net>
 <519D1485.50801@gmail.com>
Message-ID: <20130522185834.GL31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 08:55:01PM +0200, Sebastian Hesselbarth wrote:
> On 05/22/2013 08:49 PM, Jason Cooper wrote:
> >On Wed, May 22, 2013 at 08:44:20PM +0200, Sebastian Hesselbarth wrote:
> >>On 05/22/2013 07:48 PM, Jason Cooper wrote:
> >>>On Wed, May 22, 2013 at 07:42:36PM +0200, Sebastian Hesselbarth wrote:
> >>>>Hmm, maybe a little bit too early. While restoring the MAC address now
> >>>>works, another bug arises which I guess is related with phy setup
> >>>>and aneg.
> >>>>
> >>>>Will investigate and update patch set accordingly.
> >>>
> >>>Cool, chances are, we should be able to take that patch in by itself for
> >>>this merge window...
> >>
> >>Which patch do you mean? The local-mac-address workaround will only be
> >>available for DT mv643xx_eth because it uses the DT node to store the
> >>MAC.
> >
> >I thought you were replacing the unconditional ethernet clock grabbing
> >with reading the mac from the registers and updating the dtb?  In
> >mach-kirkwood/board-dt.c?
> 
> True. But there is no node for ethernet controllers in kirkwood.dtsi
> yet. It will be there with mv643xx_eth DT patches applied and that is
> when the corresponding replacement patch should also be taken in.
> 
> I was just confused about your referral to the merge window, because I
> guess it is up to David Miller to decide when/whether to take
> mv643xx_eth patches in.

Ahh, no, that was me.  I was contemplating adding the dt entries in this
merge window at one point and must've got my wires crossed.  Sorry for
the confusion.

thx,

Jason.


From broonie at kernel.org  Wed May 22 15:05:18 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 22 May 2013 14:05:18 -0500
Subject: [PATCH 7/9] I2C: mv64xxx: remove I2C_M_NOSTART code
In-Reply-To: <E1Ud4vH-0004Jz-F6@rmk-PC.arm.linux.org.uk>
References: <20130516202921.GW18614@n2100.arm.linux.org.uk>
 <E1Ud4vH-0004Jz-F6@rmk-PC.arm.linux.org.uk>
Message-ID: <20130522190518.GA1627@sirena.org.uk>

On Thu, May 16, 2013 at 09:37:11PM +0100, Russell King wrote:

> As this driver does not advertise protocol mangling support
> (I2C_FUNC_PROTOCOL_MANGLING is not set), having code to act on
> I2C_M_NOSTART is illogical, and in any case isn't supportable on
> anything but the first message - which makes no sense.  Remove
> the I2C_M_NOSTART code.

There is I2C_FUNC_NOSTART, though if it's only possible to use it on the
first message that is pretty much useless as you say.
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From gmbnomis at gmail.com  Wed May 22 15:25:02 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Wed, 22 May 2013 21:25:02 +0200
Subject: [PATCH V3 00/10] mmc_of_parse() adaptations, DT support for
 Sheevaplugs
In-Reply-To: <20130521131455.GP31290@titan.lakedaemon.net>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
 <20130521131455.GP31290@titan.lakedaemon.net>
Message-ID: <20130522192501.GC25367@schnuecks.de>

Hi Jason,

On Tue, May 21, 2013 at 09:14:55AM -0400, Jason Cooper wrote:
> On Tue, May 21, 2013 at 01:01:41AM +0200, Simon Baatz wrote:
> > Hi,
> > 
> > 	V3 changes:
> > 	- Patch 01/10: Added EPROBE_DEFER case to mmc_of_parse() 
> > 	- Added Acked-By to (unmodified) patches 02 and 03.
> > 
> > 	V2 changes:
> > 	- Converted mvsdio to use mmc_of_parse()
> > 	- Adapted DTS files using mvsdio accordingly
> > 	- Changed mmc_of_parse() to return errors to the caller
> > 
> > While adding DT support for the Sheevaplugs by Globalscale Technologies
> > (Kirkwood), it turned out that the DT binding of mvsdio lacked features to
> > properly support the hardware (active high/low of CD and WP pins could not
> > be described in DT).
> > 
> > This is standard functionality provided by the mmc_of_parse() helper
> > function.  However, mmc_of_parse() may allocate GPIO lines.  If the
> > allocation fails, it outputs an error, but does not return an error to its
> > caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.
> > 
> > The patch set is structured as follows:
> > 
> > 1   Adapt mmc_of_parse() to return errors
> > 2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
> >     only)
> > 7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
> >     kirkwood)
> > 9   Add dts files for (eSATA) Sheevaplug
> > 10  Add DT support for (eSATA) Sheevaplug
> 
> Patches 7, 9, and 10 already pulled into mvebu/dt.  You can drop those
> from this series if you need to do another revision.

If you don't mind too much, as this crosses two trees, I would prefer
to keep the series "self-contained" if people want to test.
Additionally, I have two Acked-bys for 9 and 10 from Andrew that are
not part of the patches yet.
 
> > I could only test on an eSATA Sheevaplug. I found patches with
> > different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
> > someone with the hardware could give this a spin on a non-eSATA
> > version.  
> 
> I happen to have one.  Unfortunately, it is currently my primary email
> server, dhcp, dns, file server, and a few other irreplaceable things. :(
> I *really* need to upgrade/reconfigure ...

Even without reinstalling, can you please have a look if your
"plug:green:health" LED is really green (mine is blue)?  And if your
kernel already has a "plug:red:misc" LED could you verify whether it
is really there?  Do you happen to know which board revision you
have?


Thanks,
   Simon


From jgunthorpe at obsidianresearch.com  Wed May 22 15:36:29 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Wed, 22 May 2013 13:36:29 -0600
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522185521.GR26249@lunn.ch>
References: <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522181953.GD12320@obsidianresearch.com>
 <20130522185521.GR26249@lunn.ch>
Message-ID: <20130522193629.GA18344@obsidianresearch.com>

On Wed, May 22, 2013 at 08:55:21PM +0200, Andrew Lunn wrote:
> > Just to chime in a bit here.. We also hit this problem on Kirkwood,
> > and fixed it in the bootloader. The power on default for Kirkwood
> > chips is 0xd0000000 and Linux has long required the bootloader to move
> > it.. Not sure why 370/XP dropped this.
> > 
> > Also, can you talk abit more about how this works to give more low DDR
> > memory? The docs say you can't overlap windows, and DDR CS's have a
> > power of two size/alignment requirement.
> > 
> > Does this mean the desire is to place a DDR CS from 3G -> 3.5G?
> > 
> > > For example, I'm currently booting alternatively with an old and a new
> > > bootloader (to test that things work properly), and in both cases I'm
> > > booting old style, DTB-appended, with ATAGs.
> > 
> > IMHO the DTB must match both the hardware *and* the bootloader. The
> > bootloader is setting the address map, the DTB contains that address
> > map, they must all match together.
> > 
> > Using a DTB property really is the right way to go.
> 
> Interesting you said that, yet for your kirkwood, you hacked your
> bootloader rather than Linux.

Not sure what you mean?

I don't care where internal-regs is on my box, so least-work is to
have the bootloader produce a DTB and memory map that matches the
hardwired expectations in Linux.

Keep in mind, the internal regs base is already encoded in the DTB,
but it must be 0xf1.. otherwise Linux blows up. That is a Linux 'bug',
IMHO.

> I think in practice, it is not going to be easy to match the DTB to
> the hardware and the bootloader. Look at debians flash-kernel, used to
> prepare the kernel for an embedded system. For each target it has a
> database entry:

Right, that is why I suggested using the CP15 indication to fix the
DTB on-the-fly. Similar to how ATAGs fixes the DTB. This makes the
meaning of the CP15 bit much cleaner: 'If set, override the internal
regs base in the DTB to be XYZ, if clear do not mangle the DTB'

Obviously this mangling should migrate into the DTB aware bootloader.

> So it appends the kirkwood-dreamplug.dtb blob to the kernel.  What
> you are saying is that it also needs to somehow query the version of
> uboot running on the hardware so it can pick the correct dtb blob
> from a collection of kirkwood-dreamplug.dtb blobs and append it to
> the kernel.

IMHO, if you are already booted and running in Linux you can just look
at the DTB Linux is already using to find a match in the available
DTBs. A DTB database is only needed for the OS install.

> To keep the problems tractable, we should not really be dependent on
> the bootloader version.

So, as bootloaders get updated to support native DTB, how do you
envision supporting that through flash-kernel? The way to set the DTB
is bootloader version dependent..

Jason


From sergei.shtylyov at cogentembedded.com  Wed May 22 15:50:21 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Wed, 22 May 2013 23:50:21 +0400
Subject: [PATCH] ARM: shmobile: marzen: Use error values in usb_power_*
In-Reply-To: <1369205290-6272-2-git-send-email-horms+renesas@verge.net.au>
References: <1369205290-6272-1-git-send-email-horms+renesas@verge.net.au>
 <1369205290-6272-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <519D217D.2060405@cogentembedded.com>

Hello.

On 05/22/2013 10:48 AM, Simon Horman wrote:

> This patch updates the marzen board code as if USB PHY isn't enabled
> they phy will have a value set by ERR_PTR() rather than be NULL.
>
> Without this patch a NULL pointer dereference  and kernel panic
> occurs on initialisation of USB on marzen.
>
> This resolves a regression introduced in 3.10-rc1 by
> b7fa5c2aec5be083eb2719b405089703608e9bc6
> ("usb: phy: return -ENXIO when PHY layer isn't enabled").
>
> Tested-by: Nguyen Hong Ky <nh-ky at jinso.co.jp>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>   arch/arm/mach-shmobile/board-marzen.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
> index 9105285..b9594e9 100644
> --- a/arch/arm/mach-shmobile/board-marzen.c
> +++ b/arch/arm/mach-shmobile/board-marzen.c
> @@ -212,8 +212,8 @@ static struct platform_device *marzen_devices[] __initdata = {
>   static struct usb_phy *phy;
>   static int usb_power_on(struct platform_device *pdev)
>   {
> -	if (!phy)
> -		return -EIO;
> +	if (IS_ERR(phy))

    And even before the mentioned commit the right check should have 
been IS_ERR_OR_NULL().
Thanks for finding/fixing this. Too bad I'll have to respin my USB 
patches now... :-)

WBR, Sergei



From sebastian.hesselbarth at gmail.com  Wed May 22 15:52:40 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 21:52:40 +0200
Subject: [PATCH v4 06/12] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <20130522174815.GI31290@titan.lakedaemon.net>
References: <1369154510-4927-7-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130521174849.GL26249@lunn.ch> <519C9333.20609@gmail.com>
 <519C9822.9040909@windriver.com> <519C9A66.3050807@gmail.com>
 <20130522131010.GB31290@titan.lakedaemon.net>
 <20130522165908.GB12320@obsidianresearch.com> <519D0143.1000203@gmail.com>
 <20130522173505.GH31290@titan.lakedaemon.net> <519D038C.9000605@gmail.com>
 <20130522174815.GI31290@titan.lakedaemon.net>
Message-ID: <519D2208.8040902@gmail.com>

On 05/22/2013 07:48 PM, Jason Cooper wrote:
> On Wed, May 22, 2013 at 07:42:36PM +0200, Sebastian Hesselbarth wrote:
>> On 05/22/2013 07:35 PM, Jason Cooper wrote:
>>> On Wed, May 22, 2013 at 07:32:51PM +0200, Sebastian Hesselbarth wrote:
>>>> Just tested on Dockstar with gated clocks and modular DT mv643xx_eth.
>>>>
>>>> Will append to the DT mv643xx_eth patch set if a v5 will be required
>>>> or as single patch prior Jason C taking in the ARM part of it
>>>> otherwise.
>>>
>>> Please post, in-reply-to v4 is fine.
>>
>> Hmm, maybe a little bit too early. While restoring the MAC address now
>> works, another bug arises which I guess is related with phy setup
>> and aneg.
>>
>> Will investigate and update patch set accordingly.

Ok, have it working now by properly clearing CLK125_BYPASS_EN bit in
PORT_SERIAL_CTRL1 register for Kirkwood only. I have two more patches
ready that I will post as single patches in reply to v4.

If David gives his ACK for the patch set and names a branch to base it
on, I will send a v5 including all patches.

Sebastian


From sebastian.hesselbarth at gmail.com  Wed May 22 16:04:01 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 22:04:01 +0200
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround on DT
 ethernet
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>

Kirkwood ethernet controllers suffer from loosing MAC register content
on gated clocks. In the past this was prevented by not gating the ethernet
controller clocks. With DT support for mv643xx_eth and corresponding
nodes available, a different approach is more reasonable.

This patch replaces the former clock gating workaround by parsing the
ethernet controller nodes for *invalid* MAC addresses and overwrites
the local-mac-address property with MAC register contents early. The
clock can now properly gated in modular mv643xx_eth and DT agnostic
boot loader scenarios because mv643xx_eth will find the stored MAC
in the corresponding MAC address property.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/board-dt.c |   67 +++++++++++++++++++++++++++++--------
 1 file changed, 53 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index a86b41c..0aad9f7 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -13,6 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_net.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
@@ -31,6 +33,56 @@ static struct of_device_id kirkwood_dt_match_table[] __initdata = {
 };
 
 /*
+ * Kirkwood ethernet controllers suffer from loosing the MAC address
+ * register content on gated clocks. Rather than always ungate the
+ * clocks, we get the MAC address early and put it into DT for those
+ * boot loaders that don't provide a valid MAC address property.
+ */
+#define ETH_MAC_ADDR_L(n)	(0x400 + ((n) * 0x400) + 0x14)
+#define ETH_MAC_ADDR_H(n)	(0x400 + ((n) * 0x400) + 0x18)
+
+static void __init kirkwood_dt_eth_quirk(void)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, "marvell,orion-eth") {
+		struct device_node *pnp;
+		void __iomem *base;
+
+		if (!of_device_is_available(np))
+			continue;
+
+		base = of_iomap(np, 0);
+		if (!base)
+			continue;
+
+		for_each_available_child_of_node(np, pnp) {
+			const void *mac_addr;
+			struct property *p;
+			u32 n, reg[2];
+
+			mac_addr = of_get_mac_address(pnp);
+			if (mac_addr)
+				continue;
+
+			p = of_find_property(pnp, "local-mac-address", NULL);
+			if (!p || p->length != 6)
+				continue;
+
+			if (of_property_read_u32(pnp, "reg", &n))
+				continue;
+
+			reg[0] = cpu_to_be32(readl(base + ETH_MAC_ADDR_H(n)));
+			reg[1] = cpu_to_be32(readl(base +
+						   ETH_MAC_ADDR_L(n)) << 16);
+			memcpy((void *)p->value, reg, 6);
+		}
+
+		iounmap(base);
+	}
+}
+
+/*
  * There are still devices that doesn't know about DT yet.  Get clock
  * gates here and add a clock lookup alias, so that old platform
  * devices still work.
@@ -42,7 +94,6 @@ static void __init kirkwood_legacy_clk_init(void)
 	struct device_node *np = of_find_compatible_node(
 		NULL, NULL, "marvell,kirkwood-gating-clock");
 	struct of_phandle_args clkspec;
-	struct clk *clk;
 
 	clkspec.np = np;
 	clkspec.args_count = 1;
@@ -58,19 +109,6 @@ static void __init kirkwood_legacy_clk_init(void)
 	clkspec.args[0] = CGC_BIT_SDIO;
 	orion_clkdev_add(NULL, "mvsdio",
 			 of_clk_get_from_provider(&clkspec));
-
-	/*
-	 * The ethernet interfaces forget the MAC address assigned by
-	 * u-boot if the clocks are turned off. Until proper DT support
-	 * is available we always enable them for now.
-	 */
-	clkspec.args[0] = CGC_BIT_GE0;
-	clk = of_clk_get_from_provider(&clkspec);
-	clk_prepare_enable(clk);
-
-	clkspec.args[0] = CGC_BIT_GE1;
-	clk = of_clk_get_from_provider(&clkspec);
-	clk_prepare_enable(clk);
 }
 
 static void __init kirkwood_of_clk_init(void)
@@ -97,6 +135,7 @@ static void __init kirkwood_dt_init(void)
 
 	/* Setup root of clk tree */
 	kirkwood_of_clk_init();
+	kirkwood_dt_eth_quirk();
 
 	kirkwood_cpuidle_init();
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 22 16:04:02 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 22:04:02 +0200
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood SoCs
In-Reply-To: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>

Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
MAC address register contents on clock gating but also some important
registers are reset to values that would break ethernet. This patch
clears the CLK125_BYPASS_EN bit for DT enabled Kirkwood only by using
of_machine_is_compatible() instead of #ifdefs. Non-DT Kirkwood is not
affected as it installs a clock gating workaround because of the MAC
address issue above. Other Orion SoCs do not suffer from register reset,
do not have the bit in question, or do not have the register at all.
Moreover, system controllers on PPC using this driver should also be
protected from clearing that bit.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: In contrast to the reset value of 0 for CLK125_BYPASS_EN bit as
stated in Kirkwood datasheet, we confirmed that reset value is 1 instead.
Either datasheet is wrong about it, there is some post-boot self-check or
BootROM flips that bit.

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index f2c229c..d9ad8c7 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -119,6 +119,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define  LINK_UP			0x00000002
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
+#define PORT_SERIAL_CONTROL1		0x004c
+#define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
 #define TX_BW_BURST			0x005c
@@ -2843,6 +2845,14 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
 	mp->dev = dev;
 
+	/* Kirkwood resets some registers on gated clocks. Especially
+	 * CLK125_BYPASS_EN must be cleared but is not available on
+	 * all other SoCs/System Controllers using this driver.
+	 */
+	if (of_machine_is_compatible("marvell,kirkwood"))
+		wrlp(mp, PORT_SERIAL_CONTROL1,
+		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
+
 	/*
 	 * Start with a default rate, and if there is a clock, allow
 	 * it to override the default.
-- 
1.7.10.4



From olof at lixom.net  Wed May 22 16:10:56 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed, 22 May 2013 13:10:56 -0700
Subject: [GIT PULL] ARM: OMAP2+: hwmod/serial: fix DT case
In-Reply-To: <20130521181109.GR10378@atomide.com>
References: <alpine.DEB.2.00.1305192331390.2656@utopia.booyaka.com>
 <20130521181109.GR10378@atomide.com>
Message-ID: <20130522201056.GA21266@quad.lixom.net>

On Tue, May 21, 2013 at 11:11:10AM -0700, Tony Lindgren wrote:
> Olof,
> 
> Care to pull this into your fixes directly?


Pulled, thanks.

-Olof


From jgunthorpe at obsidianresearch.com  Wed May 22 16:16:07 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Wed, 22 May 2013 14:16:07 -0600
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130522201607.GA18823@obsidianresearch.com>

On Wed, May 22, 2013 at 10:04:02PM +0200, Sebastian Hesselbarth wrote:

> Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
> MAC address register contents on clock gating but also some important
> registers are reset to values that would break ethernet. This patch

FWIW, we found that the bootloader has to write to PSC1, the driver
doesn't work with the power on/reset value of the register. So I think
it is safe to assume that all kirkwood bootloaders alter the value.

Our systems write the value 0x00638488 to PSC1.

I looked at patching mv643xx_eth, but ran into the same complexity you
did, it isn't clear what variants of this IP block have the
register/etc.

> +	/* Kirkwood resets some registers on gated clocks. Especially
> +	 * CLK125_BYPASS_EN must be cleared but is not available on
> +	 * all other SoCs/System Controllers using this driver.
> +	 */
> +	if (of_machine_is_compatible("marvell,kirkwood"))
> +		wrlp(mp, PORT_SERIAL_CONTROL1,
> +		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);

of_machine_is_compatible seems heavy handed, I would expect this to be
based on the compatible string of the ethernet node itself, not the
machine??

Jason


From arnd at arndb.de  Wed May 22 16:30:18 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 22:30:18 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <519CEAAF.2050600@free-electrons.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221743.47679.arnd@arndb.de> <519CEAAF.2050600@free-electrons.com>
Message-ID: <201305222230.18848.arnd@arndb.de>

On Wednesday 22 May 2013, Gregory CLEMENT wrote:
> But you proposed to use device tree instead of CP15. In this case we won't be
> able to use earlyprintk that was my point. You justified the fact to not use
> earlyprintk because we can't use it for multiplatform. So I am fine to not being
> able to use earlyprintk in multiplatform, but it sill important to be able to
> continue to use in non multiplatform case, hence the need of the use of CP15
> bit.

The use of devicetree would only be for the regualar kernel operation, not
for DEBUG_LL. DEBUG_LL can easily be hardcoded.

	Arnd


From andrew at lunn.ch  Wed May 22 16:31:55 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 22 May 2013 22:31:55 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522193629.GA18344@obsidianresearch.com>
References: <20130522170643.54a2b9d2@skate> <201305221735.11815.arnd@arndb.de>
 <20130522180842.7edcc3ee@skate> <20130522163557.GC27348@1wt.eu>
 <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522181953.GD12320@obsidianresearch.com>
 <20130522185521.GR26249@lunn.ch>
 <20130522193629.GA18344@obsidianresearch.com>
Message-ID: <20130522203155.GT26249@lunn.ch>

> So, as bootloaders get updated to support native DTB, how do you
> envision supporting that through flash-kernel? The way to set the DTB
> is bootloader version dependent..

You need to ask the Debian people. But my guess is, they will keep
appending the DTB blob to the kernel. They then have control of it in
an easy way. I've no idea what happens if there is both an appended
blob and one passed by the boot loader. I've not yet actually seen a
kirkwood u-boot which supports DT on COTS hardware. So it may never
actually come to pass, except for machines in the hands of kernel
hackers who update the bootloader.

	Andrew


From arnd at arndb.de  Wed May 22 16:36:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 22:36:12 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522182219.062079ac@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522155134.GL2824@lunn.ch> <20130522182219.062079ac@skate>
Message-ID: <201305222236.12652.arnd@arndb.de>

On Wednesday 22 May 2013, Thomas Petazzoni wrote:
> On Wed, 22 May 2013 17:51:34 +0200, Andrew Lunn wrote:
> 
> > Maybe i'm missunderstand Arnd, but i think he is suggesting a property
> > somewhere in DT which says where the bootloader left the register
> > space before jumping to the kernel. You can then look at this property
> > and then decide if you need to remap or not. Only this one property
> > needs to differ between old and new bootloader. You could even say, if
> > the property is not in DT, a remap is needed.

No, the idea was that we don't need to remap if we know where the registers
are. The mbus driver might remap them if it is really careful about not
breaking any existing mappings, but it's probably easier to just leave
them alone.

> The problem is that neither the old nor the new bootloaders are setting
> such property in the DT. Old bootloaders shipped by Marvell don't have
> DT support at all. New bootloaders shipped by Marvell do have DT
> support, but they are not adding any specific DT property that allows
> us to tell whether the registers are mapped here or there.
> 
> We could maybe find a way of detecting whether if the bootloader is DT
> capable, and assume that if it's DT capable, the registers are already
> mapped at 0xf1. But that's very fragile: nothing prevents an user to
> use a DT-capable bootloader to boot a kernel in the old style way
> (appended DTB). In this case, we would assume that the registers are at
> 0xd0, because we're being booted old-style, and therefore it must be an
> old bootloader. Very fragile, clearly not better than the CP15 trick.

Yes, that would not be an improvement. However, since we know what boot
loader we have when we pass the devicetree, that devicetree can just
contain the correct 'reg' property for the internal registers.

> > However, i don't know if this can actually work. How early can you
> > parse the DT in order to know where the serial port is for
> > earlyprintk()? It also gets messy keeping track of the two different
> > DT binary blobs and somehow having the probe the uboot version in
> > order to install the right one. I don't know how i would include this
> > into the debian flash-kernel for example.
> 
> For earlyprintk, we can "solve" it as Arnd suggested: just have two
> Kconfig options, one for 0xd0, one for 0xf1, and it's up to the user to
> choose the right one. It's not entirely nice because it's no longer
> automatic, and I'm sure our users will have a hard time figuring out
> whether they have an "old" or a "new" bootloader. But let's assume we
> do this. earlyprintk knows the physical address of the UART.
> 
> Then, we enter ->map_io(). We have access to the Device Tree. But the
> Device Tree doesn't tell us whether the bootloader has mapped the
> registers. As I explained to Arnd, it's not a per-board criteria: when
> I'm booting my OpenBlocks with the manufacturer U-Boot, registers are
> mapped at 0xd0. When I boot the same OpenBlocks with the (admittedly
> work-in-progress) Barebox bootloader, registers are mapped at 0xf1.
> Same board, different register location.

But since you control barebox, you can find the "regs" property of the
mbus node in it and set it up to the same address you use when you
map the internal registers.

	Arnd


From gmbnomis at gmail.com  Wed May 22 16:36:33 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Wed, 22 May 2013 22:36:33 +0200
Subject: [PATCH v4 11/12] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <1369154510-4927-12-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-12-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130522203633.GA28394@schnuecks.de>

Hi Sebastian,

On Tue, May 21, 2013 at 06:41:49PM +0200, Sebastian Hesselbarth wrote:
> With DT support for mv643xx_eth, board specific init for some boards now
> is unneccessary. Remove those board files, Kconfig entries, and
> corresponding entries in kirkwood_defconfig.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
> the lock-up is not caused by accessing clock gating registers but rather
> non-existent device registers. This will be addressed by dtsi separation
> for kirkwood and bobcat SoC variants.
> 
> Changelog:
> v3->v4:
> - remove more boards that don't require board specific setup
> 
> Cc: David Miller <davem at davemloft.net>
> Cc: Lennert Buytenhek <buytenh at wantstofly.org>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: netdev at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linuxppc-dev at lists.ozlabs.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/configs/kirkwood_defconfig           |   16 ----
>  arch/arm/mach-kirkwood/Kconfig                |  117 -------------------------
>  arch/arm/mach-kirkwood/Makefile               |   16 ----
>  arch/arm/mach-kirkwood/board-dnskw.c          |    7 --
>  arch/arm/mach-kirkwood/board-dockstar.c       |   32 -------
>  arch/arm/mach-kirkwood/board-dreamplug.c      |   35 --------
>  arch/arm/mach-kirkwood/board-dt.c             |   38 --------
>  arch/arm/mach-kirkwood/board-goflexnet.c      |   34 -------
>  arch/arm/mach-kirkwood/board-guruplug.c       |   33 -------
>  arch/arm/mach-kirkwood/board-ib62x0.c         |   29 ------
>  arch/arm/mach-kirkwood/board-iconnect.c       |   10 ---
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   34 -------
>  arch/arm/mach-kirkwood/board-km_kirkwood.c    |   44 ----------
>  arch/arm/mach-kirkwood/board-lsxl.c           |   16 ----
>  arch/arm/mach-kirkwood/board-mplcec4.c        |   14 ---
>  arch/arm/mach-kirkwood/board-ns2.c            |   35 --------
>  arch/arm/mach-kirkwood/board-openblocks_a6.c  |   26 ------
>  arch/arm/mach-kirkwood/board-readynas.c       |    6 --
>  arch/arm/mach-kirkwood/board-ts219.c          |   13 ---
>  arch/arm/mach-kirkwood/board-usi_topkick.c    |   29 ------
>  20 files changed, 584 deletions(-)
>  delete mode 100644 arch/arm/mach-kirkwood/board-dockstar.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-goflexnet.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-guruplug.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-ib62x0.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-ns2.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
>  delete mode 100644 arch/arm/mach-kirkwood/board-usi_topkick.c
> 
...
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 8db388a..a86b41c 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -104,59 +104,21 @@ static void __init kirkwood_dt_init(void)
>  	kexec_reinit = kirkwood_enable_pcie;
>  #endif
>  
> -	if (of_machine_is_compatible("globalscale,dreamplug"))
> -		dreamplug_init();
> -
> -	if (of_machine_is_compatible("globalscale,guruplug"))
> -		guruplug_dt_init();
> -
>  	if (of_machine_is_compatible("dlink,dns-kirkwood"))
>  		dnskw_init();
>  
> -	if (of_machine_is_compatible("iom,iconnect"))
> -		iconnect_init();
> -
> -	if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
> -		ib62x0_init();
> -
>  	if (of_machine_is_compatible("qnap,ts219"))
>  		qnap_dt_ts219_init();
>  
> -	if (of_machine_is_compatible("seagate,dockstar"))
> -		dockstar_dt_init();
> -
> -	if (of_machine_is_compatible("seagate,goflexnet"))
> -		goflexnet_init();
> -
>  	if (of_machine_is_compatible("buffalo,lsxl"))
>  		lsxl_init();
>  
> -	if (of_machine_is_compatible("iom,ix2-200"))
> -		iomega_ix2_200_init();
> -
> -	if (of_machine_is_compatible("keymile,km_kirkwood"))
> -		km_kirkwood_init();
> -
> -	if (of_machine_is_compatible("lacie,cloudbox") ||
> -	    of_machine_is_compatible("lacie,inetspace_v2") ||
> -	    of_machine_is_compatible("lacie,netspace_lite_v2") ||
> -	    of_machine_is_compatible("lacie,netspace_max_v2") ||
> -	    of_machine_is_compatible("lacie,netspace_mini_v2") ||
> -	    of_machine_is_compatible("lacie,netspace_v2"))
> -		ns2_init();
> -
>  	if (of_machine_is_compatible("mpl,cec4"))
>  		mplcec4_init();
>  
>  	if (of_machine_is_compatible("netgear,readynas-duo-v2"))
>  		netgear_readynas_init();
>  
> -	if (of_machine_is_compatible("plathome,openblocks-a6"))
> -		openblocks_a6_init();
> -
> -	if (of_machine_is_compatible("usi,topkick"))
> -		usi_topkick_init();
> -
>  	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
>  }

We still have:

static const char * const kirkwood_dt_board_compat[] = {
	"globalscale,dreamplug",
	"globalscale,guruplug",
	"dlink,dns-320",
	"dlink,dns-325",
	"iom,iconnect",
	"raidsonic,ib-nas62x0",
	"qnap,ts219",
	"seagate,dockstar",
	"seagate,goflexnet",
	"buffalo,lsxl",
	"iom,ix2-200",
	"keymile,km_kirkwood",
	"lacie,cloudbox",
	"lacie,inetspace_v2",
	"lacie,netspace_lite_v2",
	"lacie,netspace_max_v2",
	"lacie,netspace_mini_v2",
	"lacie,netspace_v2",
	"mpl,cec4",
	"netgear,readynas-duo-v2",
	"plathome,openblocks-a6",
	"usi,topkick",
	"zyxel,nsa310",
	NULL
};

in that file. I think it does not make sense that we need to list
boards here that can be described fully by DT. When adding such a
board in the future, you will still need to adapt board-dt.c.

Should we remove the boards that you removed above here as well and
add

	"marvell,kirkwood-88f6192",
	"marvell,kirkwood-88f6281",
	"marvell,kirkwood-88f6282",
	"marvell,kirkwood-88f6283",
	"marvell,kirkwood-88f6702",
	"marvell,kirkwood-98DX4122",

or even just state "marvell,kirkwood"?

- Simon


From mst at redhat.com  Wed May 22 16:36:45 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 23:36:45 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130516184041.GP19669@dyad.programming.kicks-ass.net>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
Message-ID: <20130522203645.GA28296@redhat.com>

On Thu, May 16, 2013 at 08:40:41PM +0200, Peter Zijlstra wrote:
> On Thu, May 16, 2013 at 02:16:10PM +0300, Michael S. Tsirkin wrote:
> > There are several ways to make sure might_fault
> > calling function does not sleep.
> > One is to use it on kernel or otherwise locked memory - apparently
> > nfs/sunrpc does this. As noted by Ingo, this is handled by the
> > migh_fault() implementation in mm/memory.c but not the one in
> > linux/kernel.h so in the current code might_fault() schedules
> > differently depending on CONFIG_PROVE_LOCKING, which is an undesired
> > semantical side effect.
> > 
> > Another is to call pagefault_disable: in this case the page fault
> > handler will go to fixups processing and we get an error instead of
> > sleeping, so the might_sleep annotation is a false positive.
> > vhost driver wants to do this now in order to reuse socket ops
> > under a spinlock (and fall back on slower thread handler
> > on error).
> 
> Are you using the assumption that spin_lock() implies preempt_disable() implies
> pagefault_disable()? Note that this assumption isn't valid for -rt where the
> spinlock becomes preemptible but we'll not disable pagefaults.
> 
> > Address both issues by:
> > 	- dropping the unconditional call to might_sleep
> > 	  from the fast might_fault code in linux/kernel.h
> > 	- checking for pagefault_disable() in the
> > 	  CONFIG_PROVE_LOCKING implementation
> > 
> > Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
> > ---
> >  include/linux/kernel.h |  1 -
> >  mm/memory.c            | 14 +++++++++-----
> >  2 files changed, 9 insertions(+), 6 deletions(-)
> > 
> > diff --git a/include/linux/kernel.h b/include/linux/kernel.h
> > index e96329c..322b065 100644
> > --- a/include/linux/kernel.h
> > +++ b/include/linux/kernel.h
> > @@ -198,7 +198,6 @@ void might_fault(void);
> >  #else
> >  static inline void might_fault(void)
> >  {
> > -	might_sleep();
> 
> This removes potential resched points for PREEMPT_VOLUNTARY -- was that
> intentional?

OK so I'm thinking of going back to this idea:
it has the advantage of being very simple,
and just might make some workloads faster
if they do lots of copy_XX_user in a loop.

Will have to be tested of course - anyone
has objections?

> >  }
> >  #endif
> >  
> > diff --git a/mm/memory.c b/mm/memory.c
> > index 6dc1882..1b8327b 100644
> > --- a/mm/memory.c
> > +++ b/mm/memory.c
> > @@ -4222,13 +4222,17 @@ void might_fault(void)
> >  	if (segment_eq(get_fs(), KERNEL_DS))
> >  		return;
> >  
> > -	might_sleep();
> >  	/*
> > -	 * it would be nicer only to annotate paths which are not under
> > -	 * pagefault_disable, however that requires a larger audit and
> > -	 * providing helpers like get_user_atomic.
> > +	 * It would be nicer to annotate paths which are under preempt_disable
> > +	 * but not under pagefault_disable, however that requires a new flag
> > +	 * for differentiating between the two.
> 
> -rt has this, pagefault_disable() doesn't change the preempt count but pokes
> at task_struct::pagefault_disable.
> 
> >  	 */
> > -	if (!in_atomic() && current->mm)
> > +	if (in_atomic())
> > +		return;
> > +
> > +	might_sleep();
> > +
> > +	if (current->mm)
> >  		might_lock_read(&current->mm->mmap_sem);
> >  }
> >  EXPORT_SYMBOL(might_fault);
> > -- 
> > MST


From mst at redhat.com  Wed May 22 16:38:31 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Wed, 22 May 2013 23:38:31 +0300
Subject: [PATCH v2 10/10] kernel: might_fault does not imply might_sleep
In-Reply-To: <20130521115734.GA9554@twins.programming.kicks-ass.net>
References: <cover.1368702323.git.mst@redhat.com>
 <1f85dc8e6a0149677563a2dfb4cef9a9c7eaa391.1368702323.git.mst@redhat.com>
 <20130516184041.GP19669@dyad.programming.kicks-ass.net>
 <20130519093526.GD19883@redhat.com>
 <20130521115734.GA9554@twins.programming.kicks-ass.net>
Message-ID: <20130522203831.GB28296@redhat.com>

On Tue, May 21, 2013 at 01:57:34PM +0200, Peter Zijlstra wrote:
> On Sun, May 19, 2013 at 12:35:26PM +0300, Michael S. Tsirkin wrote:
> > > > --- a/include/linux/kernel.h
> > > > +++ b/include/linux/kernel.h
> > > > @@ -198,7 +198,6 @@ void might_fault(void);
> > > >  #else
> > > >  static inline void might_fault(void)
> > > >  {
> > > > -	might_sleep();
> > > 
> > > This removes potential resched points for PREEMPT_VOLUNTARY -- was that
> > > intentional?
> > 
> > No it's a bug. Thanks for pointing this out.
> > OK so I guess it should be might_sleep_if(!in_atomic())
> > and this means might_fault would have to move from linux/kernel.h to
> > linux/uaccess.h, since in_atomic() is in linux/hardirq.h
> > 
> > Makes sense?
> 
> So the only difference between PROVE_LOCKING and not should be the
> might_lock_read() thing; so how about something like this?

So the problem with the below is that might_fault is needed
in asm/uaccess.h.
I'm still trying various approaches but the dependencies there
are very complex.

> ---
>  include/linux/kernel.h  |  7 ++-----
>  include/linux/uaccess.h | 26 ++++++++++++++++++++++++++
>  mm/memory.c             | 14 ++------------
>  3 files changed, 30 insertions(+), 17 deletions(-)
> 
> diff --git a/include/linux/kernel.h b/include/linux/kernel.h
> index e96329c..70812f4 100644
> --- a/include/linux/kernel.h
> +++ b/include/linux/kernel.h
> @@ -194,12 +194,9 @@ extern int _cond_resched(void);
>  	})
>  
>  #ifdef CONFIG_PROVE_LOCKING
> -void might_fault(void);
> +void might_fault_lockdep(void);
>  #else
> -static inline void might_fault(void)
> -{
> -	might_sleep();
> -}
> +static inline void might_fault_lockdep(void) { }
>  #endif
>  
>  extern struct atomic_notifier_head panic_notifier_list;
> diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
> index 5ca0951..50a2cc9 100644
> --- a/include/linux/uaccess.h
> +++ b/include/linux/uaccess.h
> @@ -38,6 +38,32 @@ static inline void pagefault_enable(void)
>  	preempt_check_resched();
>  }
>  
> +static inline bool __can_fault(void)
> +{
> +	/*
> +	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
> +	 * holding the mmap_sem, this is safe because kernel memory doesn't
> +	 * get paged out, therefore we'll never actually fault, and the
> +	 * below annotations will generate false positives.
> +	 */
> +	if (segment_eq(get_fs(), KERNEL_DS))
> +		return false;
> +
> +	if (in_atomic() /* || pagefault_disabled() */)
> +		return false;
> +
> +	return true;
> +}
> +
> +static inline void might_fault(void)
> +{
> +	if (!__can_fault())
> +		return;
> +
> +	might_sleep();
> +	might_fault_lockdep();
> +}
> +
>  #ifndef ARCH_HAS_NOCACHE_UACCESS
>  
>  static inline unsigned long __copy_from_user_inatomic_nocache(void *to,
> diff --git a/mm/memory.c b/mm/memory.c
> index 6dc1882..266610c 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -4211,19 +4211,9 @@ void print_vma_addr(char *prefix, unsigned long ip)
>  }
>  
>  #ifdef CONFIG_PROVE_LOCKING
> -void might_fault(void)
> +void might_fault_lockdep(void)
>  {
>  	/*
> -	 * Some code (nfs/sunrpc) uses socket ops on kernel memory while
> -	 * holding the mmap_sem, this is safe because kernel memory doesn't
> -	 * get paged out, therefore we'll never actually fault, and the
> -	 * below annotations will generate false positives.
> -	 */
> -	if (segment_eq(get_fs(), KERNEL_DS))
> -		return;
> -
> -	might_sleep();
> -	/*
>  	 * it would be nicer only to annotate paths which are not under
>  	 * pagefault_disable, however that requires a larger audit and
>  	 * providing helpers like get_user_atomic.
> @@ -4231,7 +4221,7 @@ void might_fault(void)
>  	if (!in_atomic() && current->mm)
>  		might_lock_read(&current->mm->mmap_sem);
>  }
> -EXPORT_SYMBOL(might_fault);
> +EXPORT_SYMBOL(might_fault_lockdep);
>  #endif
>  
>  #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLBFS)


From sboyd at codeaurora.org  Wed May 22 16:40:15 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 May 2013 13:40:15 -0700
Subject: [RFC/PATCH 0/2] Remove most of_device_match() calls
Message-ID: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>

Sending this as an RFC with one driver converted to see what people
think. The goal is to avoid having to run the match twice and be
similar to how platform_device_id works right now. If people agree
I can go through and send out patches for all the drivers doing
the duplicate search (~100 files).

Stephen Boyd (2):
  of: Assign of_device_id to matching device_node
  gpio/omap: Use of_node->id_entry directly

 drivers/gpio/gpio-omap.c  |  4 +---
 drivers/of/device.c       | 18 ++++++++++++++++++
 include/linux/of.h        |  1 +
 include/linux/of_device.h | 12 ++----------
 4 files changed, 22 insertions(+), 13 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sboyd at codeaurora.org  Wed May 22 16:40:16 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 May 2013 13:40:16 -0700
Subject: [RFC/PATCH 1/2] of: Assign of_device_id to matching device_node
In-Reply-To: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>
References: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1369255217-29764-2-git-send-email-sboyd@codeaurora.org>

Platform drivers have to match the compatible field twice if they
want to use the .data field of the of_device_id struct when their
driver matches multiple devicetree compatible fields. The first
match happens when the driver core probes for a matching
device and the second match typically happens during their probe
routine when the driver calls of_match_device() to get the
of_device_id that this device matches.

Skip this duplicate search by assigning the of_device_id to a new
id_entry pointer in the device_node struct when the driver core
matches up an of_device_id with a device_node. Drivers can then
get the entry pointer via dev->of_node->id_entry and access the
.data field to differentiate which device they matched.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/of/device.c       | 18 ++++++++++++++++++
 include/linux/of.h        |  1 +
 include/linux/of_device.h | 12 ++----------
 3 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/of/device.c b/drivers/of/device.c
index f685e55..f3eab88 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -27,6 +27,24 @@ const struct of_device_id *of_match_device(const struct of_device_id *matches,
 }
 EXPORT_SYMBOL(of_match_device);
 
+/**
+ * of_driver_match_device - Tell if a driver's of_match_table matches a device.
+ * @drv: the device_driver structure to test
+ * @dev: the device structure to match against
+ */
+int of_driver_match_device(struct device *dev,
+			   const struct device_driver *drv)
+{
+	const struct of_device_id *id;
+
+	id = of_match_device(drv->of_match_table, dev);
+	if (id)
+		dev->of_node->id_entry = id;
+
+	return id != NULL;
+}
+EXPORT_SYMBOL(of_driver_match_device);
+
 struct platform_device *of_dev_get(struct platform_device *dev)
 {
 	struct device *tmp;
diff --git a/include/linux/of.h b/include/linux/of.h
index 1fd08ca..6c847af 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -59,6 +59,7 @@ struct device_node {
 	struct	proc_dir_entry *pde;	/* this node's proc directory */
 	struct	kref kref;
 	unsigned long _flags;
+	const struct  of_device_id *id_entry;
 	void	*data;
 #if defined(CONFIG_SPARC)
 	const char *path_component_name;
diff --git a/include/linux/of_device.h b/include/linux/of_device.h
index 901b743..5b2a69a 100644
--- a/include/linux/of_device.h
+++ b/include/linux/of_device.h
@@ -14,16 +14,8 @@ extern const struct of_device_id *of_match_device(
 	const struct of_device_id *matches, const struct device *dev);
 extern void of_device_make_bus_id(struct device *dev);
 
-/**
- * of_driver_match_device - Tell if a driver's of_match_table matches a device.
- * @drv: the device_driver structure to test
- * @dev: the device structure to match against
- */
-static inline int of_driver_match_device(struct device *dev,
-					 const struct device_driver *drv)
-{
-	return of_match_device(drv->of_match_table, dev) != NULL;
-}
+extern int of_driver_match_device(struct device *dev,
+				  const struct device_driver *drv);
 
 extern struct platform_device *of_dev_get(struct platform_device *dev);
 extern void of_dev_put(struct platform_device *dev);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From arnd at arndb.de  Wed May 22 16:40:04 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 May 2013 22:40:04 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522180842.7edcc3ee@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
Message-ID: <201305222240.05124.arnd@arndb.de>

On Wednesday 22 May 2013, Thomas Petazzoni wrote:
> > More importantly, you can build a kernel with any number of other SoCs
> > already, and if you have a combined ArmadaXP+OMAP+Highbank kernel,
> > there is no way to get a working early debug output.
> 
> So you're proposing to add two Kconfig options, one to have the UART at
> 0xd0012000 and the other one to have the UART at 0xf1012000. The user
> would have to know whether he is going to boot with an old bootloader
> or new bootloader, and select the appropriate option. This means that
> the mvebu_defconfig would no longer be able to have earlyprintk enabled
> by default, otherwise the resulting kernel may not boot for some
> people, but maybe it's a reasonable tradeoff.

Yes. It may also be reasonable to use the CP15 hack for DEBUG_LL, but
I would not like to see that information getting used anywhere in the
kernel outside of DEBUG_LL. That should really come from the DT.

> > > > As you already admit, using the CP15 register is a hack. It sounds
> > > > to me that a cleaner approach would be to put the correct address
> > > > into the device tree and use that value everywhere, rather than
> > > > hardcoding one or more addresses.
> > > 
> > > I don't see how this can fix the problem. Which internal register base
> > > address do we put in our Device Tree source in arch/arm/boot/dts? The
> > > old one? The new one?
> > 
> > The one matching the boot loader for that board, i.e. the new address
> > for all boards but Mirabox and OpenBlocks.
> 
> And what happens when Globalscale (Mirabox manufacturer) or Plathome
> (manufacturer of OpenBlocks) release a new bootloader version, based on
> the new bootloader from Marvell, which remaps things at 0xf1000000 ? Or
> when those people boot from Barebox, which remaps at 0xf1000000 ?
> 
> Conclusion: you can't classify on one side boards that are at 0xd0 and
> boards that are at 0xf1. It depends on which bootloader each
> particular instance of those boards will be using. Will it be a
> bootloader that complies with the "old" protocol (CP15 bit cleared and
> registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> 0xf1).
> 
> So we can't encode into the boards Device Tree whether the registers
> are at 0xd0 or 0xf1, because it's not a board-related information, but
> a bootloader-related information.

The new boot loaders will of course know that they are remapping the
registers, so they are also able to put the correct information into the
DT.

	Arnd


From sboyd at codeaurora.org  Wed May 22 16:40:17 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 May 2013 13:40:17 -0700
Subject: [RFC/PATCH 2/2] gpio/omap: Use of_node->id_entry directly
In-Reply-To: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>
References: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1369255217-29764-3-git-send-email-sboyd@codeaurora.org>

Now that the driver core is assigning the of_device_id that
matches to the of_node before calling probe we can skip this
duplicate search and just use of_node->id_entry directly.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 drivers/gpio/gpio-omap.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 2050891..04ae7e7 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1083,8 +1083,6 @@ static void omap_gpio_chip_init(struct gpio_bank *bank)
 	irq_set_handler_data(bank->irq, bank);
 }
 
-static const struct of_device_id omap_gpio_match[];
-
 static int omap_gpio_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1094,7 +1092,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct gpio_bank *bank;
 
-	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
+	match = pdev->dev.of_node->id_entry;
 
 	pdata = match ? match->data : dev->platform_data;
 	if (!pdata)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation



From sebastian.hesselbarth at gmail.com  Wed May 22 16:47:52 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 22:47:52 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522191420.1ef08f8d@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164928.GD27348@1wt.eu> <20130522190004.67880320@skate>
 <20130522170807.GE27348@1wt.eu> <20130522191420.1ef08f8d@skate>
Message-ID: <519D2EF8.7040804@gmail.com>

On 05/22/2013 07:14 PM, Thomas Petazzoni wrote:
> On Wed, 22 May 2013 19:08:07 +0200, Willy Tarreau wrote:
>> On Wed, May 22, 2013 at 07:00:04PM +0200, Thomas Petazzoni wrote:
>>> Of course, one option is simply to have a kconfig option "I am booting
>>> from an old bootloader", but with the CP15 trick, we've tried to make
>>> this automatic so that users don't have to understand the kind of gory
>>> details we are discussing right now.
>>
>> Same as for ATAGS right now which are not necessarily the most obvious
>> setting for end users. Better keep the trick on by default if it's safe
>> enough. In fact I'm mostly concerned about the risk that it later breaks
>> for even newer boot loaders. But then we'll have more feedback to decide.
>
> As I suggested earlier, we can print a warning when people boot from an
> old bootloader, and then down the road get rid of the trick. Or move it
> under a conditional compilation so that the minority of remaining users
> will have to enable this particular option. This will anyway be needed
> if we want to go multiplatform with Dove, for example.

I am not so sure Kconfig for Dove is really required, if it moves to
mach-mvebu. As I already stated before, Dove is happily accessing
0xd0000000 even if internal registers mapped on 0xf1000000. So maybe
the enforced remap will do no harm and at max write in some RAM mapped
there.

Although, I doubt that there will ever be a Dove board with RAM at 3GB
addresses with only two DDR CS available. Currently, for DDR3 DRAMs
8Gbit is the largest you can get, DDR2 ends at 4Gbit but >3GB RAM would 
require 16Gbit DRAMs.

Also I guess Dove is about to be replaced by Armada 1000/1500 for new
products.

Sebastian


From sebastian.hesselbarth at gmail.com  Wed May 22 16:55:43 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 22:55:43 +0200
Subject: [PATCH v4 11/12] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <20130522203633.GA28394@schnuecks.de>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-12-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522203633.GA28394@schnuecks.de>
Message-ID: <519D30CF.9040904@gmail.com>

On 05/22/2013 10:36 PM, Simon Baatz wrote:
> Hi Sebastian,
>
> On Tue, May 21, 2013 at 06:41:49PM +0200, Sebastian Hesselbarth wrote:
>> With DT support for mv643xx_eth, board specific init for some boards now
>> is unneccessary. Remove those board files, Kconfig entries, and
>> corresponding entries in kirkwood_defconfig.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>> ---
>> Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
>> the lock-up is not caused by accessing clock gating registers but rather
>> non-existent device registers. This will be addressed by dtsi separation
>> for kirkwood and bobcat SoC variants.
>>
>> Changelog:
>> v3->v4:
>> - remove more boards that don't require board specific setup
>>
...
> We still have:
>
> static const char * const kirkwood_dt_board_compat[] = {
> 	"globalscale,dreamplug",
> 	"globalscale,guruplug",
> 	"dlink,dns-320",
> 	"dlink,dns-325",
> 	"iom,iconnect",
> 	"raidsonic,ib-nas62x0",
> 	"qnap,ts219",
> 	"seagate,dockstar",
> 	"seagate,goflexnet",
> 	"buffalo,lsxl",
> 	"iom,ix2-200",
> 	"keymile,km_kirkwood",
> 	"lacie,cloudbox",
> 	"lacie,inetspace_v2",
> 	"lacie,netspace_lite_v2",
> 	"lacie,netspace_max_v2",
> 	"lacie,netspace_mini_v2",
> 	"lacie,netspace_v2",
> 	"mpl,cec4",
> 	"netgear,readynas-duo-v2",
> 	"plathome,openblocks-a6",
> 	"usi,topkick",
> 	"zyxel,nsa310",
> 	NULL
> };
>
> in that file. I think it does not make sense that we need to list
> boards here that can be described fully by DT. When adding such a
> board in the future, you will still need to adapt board-dt.c.

True, will remove the redundant compatible strings for v5.
Actually, if I am not missing something, all compatible strings except
"marvell,kirkwood" are redundant as long as board.dts append it
correctly.

> Should we remove the boards that you removed above here as well and
> add
>
> 	"marvell,kirkwood-88f6192",
> 	"marvell,kirkwood-88f6281",
> 	"marvell,kirkwood-88f6282",
> 	"marvell,kirkwood-88f6283",
> 	"marvell,kirkwood-88f6702",
> 	"marvell,kirkwood-98DX4122",
>
> or even just state "marvell,kirkwood"?

I would stick with "marvell,kirkwood" only. This is SoC init code and
we do not distinguish variants here at all.

Sebastian


From sebastian.hesselbarth at gmail.com  Wed May 22 17:02:05 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 23:02:05 +0200
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130522201607.GA18823@obsidianresearch.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
Message-ID: <519D324D.6070903@gmail.com>

On 05/22/2013 10:16 PM, Jason Gunthorpe wrote:
> On Wed, May 22, 2013 at 10:04:02PM +0200, Sebastian Hesselbarth wrote:
>> Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
>> MAC address register contents on clock gating but also some important
>> registers are reset to values that would break ethernet. This patch
>
> FWIW, we found that the bootloader has to write to PSC1, the driver
> doesn't work with the power on/reset value of the register. So I think
> it is safe to assume that all kirkwood bootloaders alter the value.

It is safe to assume the bootloader alters it, but that modification is
lost when clocks get gated. I assume on clock ungate, the controller is
reset. Saying this, I will double check Dove's reset value but looks 
like reset mess has been fixed in that later SoC.

> Our systems write the value 0x00638488 to PSC1.
>
> I looked at patching mv643xx_eth, but ran into the same complexity you
> did, it isn't clear what variants of this IP block have the
> register/etc.

For Orion SoCs it is quite clear to me, with Gregory Clement and Thomas
Petazzoni we could also confirm if it does any harm there if we
unconditionally clear it. But for PPC system controllers I have no
idea...

>> +	/* Kirkwood resets some registers on gated clocks. Especially
>> +	 * CLK125_BYPASS_EN must be cleared but is not available on
>> +	 * all other SoCs/System Controllers using this driver.
>> +	 */
>> +	if (of_machine_is_compatible("marvell,kirkwood"))
>> +		wrlp(mp, PORT_SERIAL_CONTROL1,
>> +		     rdlp(mp, PORT_SERIAL_CONTROL1)&  ~CLK125_BYPASS_EN);
>
> of_machine_is_compatible seems heavy handed, I would expect this to be
> based on the compatible string of the ethernet node itself, not the
> machine??

I have no strong opinion about checking the machine compatible or have
an extra compatible string for Kirkwood ethernet. Both would work fine
and are checked once upon probe anyway.

Sebastian


From jason at lakedaemon.net  Wed May 22 17:02:57 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 22 May 2013 17:02:57 -0400
Subject: [PATCH v4 11/12] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <519D30CF.9040904@gmail.com>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-12-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522203633.GA28394@schnuecks.de> <519D30CF.9040904@gmail.com>
Message-ID: <20130522210257.GM31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 10:55:43PM +0200, Sebastian Hesselbarth wrote:
> On 05/22/2013 10:36 PM, Simon Baatz wrote:
> >Hi Sebastian,
> >
> >On Tue, May 21, 2013 at 06:41:49PM +0200, Sebastian Hesselbarth wrote:
> >>With DT support for mv643xx_eth, board specific init for some boards now
> >>is unneccessary. Remove those board files, Kconfig entries, and
> >>corresponding entries in kirkwood_defconfig.
> >>
> >>Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> >>---
> >>Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
> >>the lock-up is not caused by accessing clock gating registers but rather
> >>non-existent device registers. This will be addressed by dtsi separation
> >>for kirkwood and bobcat SoC variants.
> >>
> >>Changelog:
> >>v3->v4:
> >>- remove more boards that don't require board specific setup
> >>
> ...
> >We still have:
> >
> >static const char * const kirkwood_dt_board_compat[] = {
> >	"globalscale,dreamplug",
> >	"globalscale,guruplug",
> >	"dlink,dns-320",
> >	"dlink,dns-325",
> >	"iom,iconnect",
> >	"raidsonic,ib-nas62x0",
> >	"qnap,ts219",
> >	"seagate,dockstar",
> >	"seagate,goflexnet",
> >	"buffalo,lsxl",
> >	"iom,ix2-200",
> >	"keymile,km_kirkwood",
> >	"lacie,cloudbox",
> >	"lacie,inetspace_v2",
> >	"lacie,netspace_lite_v2",
> >	"lacie,netspace_max_v2",
> >	"lacie,netspace_mini_v2",
> >	"lacie,netspace_v2",
> >	"mpl,cec4",
> >	"netgear,readynas-duo-v2",
> >	"plathome,openblocks-a6",
> >	"usi,topkick",
> >	"zyxel,nsa310",
> >	NULL
> >};
> >
> >in that file. I think it does not make sense that we need to list
> >boards here that can be described fully by DT. When adding such a
> >board in the future, you will still need to adapt board-dt.c.
> 
> True, will remove the redundant compatible strings for v5.
> Actually, if I am not missing something, all compatible strings except
> "marvell,kirkwood" are redundant as long as board.dts append it
> correctly.
> 
> >Should we remove the boards that you removed above here as well and
> >add
> >
> >	"marvell,kirkwood-88f6192",
> >	"marvell,kirkwood-88f6281",
> >	"marvell,kirkwood-88f6282",
> >	"marvell,kirkwood-88f6283",
> >	"marvell,kirkwood-88f6702",
> >	"marvell,kirkwood-98DX4122",
> >
> >or even just state "marvell,kirkwood"?
> 
> I would stick with "marvell,kirkwood" only. This is SoC init code and
> we do not distinguish variants here at all.

Agreed, nice catch Simon.

thx,

Jason.


From nerv at dawncrow.de  Wed May 22 17:04:34 2013
From: nerv at dawncrow.de (=?ISO-8859-15?Q?Andr=E9_Hentschel?=)
Date: Wed, 22 May 2013 23:04:34 +0200
Subject: [PATCH v5] arm: Preserve the user r/w register TPIDRURW on context
 switch and fork
Message-ID: <519D32E2.5050102@dawncrow.de>

From: Andr? Hentschel <nerv at dawncrow.de>

Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
prevent it from being used as a covert channel between two tasks.

There are more and more applications coming to Windows RT,
Wine could support them, but mostly they expect to have
the thread environment block (TEB) in TPIDRURW.

This patch preserves that register per thread instead of clearing it.
Unlike the TPIDRURO, which is already switched, the TPIDRURW
can be updated from userspace so needs careful treatment in the case that we
modify TPIDRURW and call fork(). To avoid this we must always read
TPIDRURW in copy_thread.

Signed-off-by: Andr? Hentschel <nerv at dawncrow.de>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com> 

---
This patch is against Linux 3.10-rc2 (c7788792a5e7b0d5d7f96d0766b4cb6112d47d75)

v2: rework and fixup of v1, based on a suggested patch by Will Deacon
v3: total rework and fixup of v2
v4: removed condition on assembler instruction,
    adapted my code to kernel-style, both based on comments by Will Deacon
v5: rebased v4 on 3.10-rc2 and adding this version history

As suggested by Jonathan Austin, i'll send this patch to RMK's patch tracker in
case there are no more comments on it.

Why so much Signed-off-bys? Some History:
The first patch had performance issues pointed out by Russel King,
so Will Deacon jumped in to help me with that. The second one again
had performance issues and the missing copy_thread part was uncovered.
After some iterations by me, Jonathan Austin proposed a patch and
Russel King sent his idea of the assembler part. All this was finally
merged and refined into this patch.
Thanks to everyone!

 arch/arm/include/asm/thread_info.h |  2 +-
 arch/arm/include/asm/tls.h         | 40 +++++++++++++++++++++++++-------------
 arch/arm/kernel/entry-armv.S       |  4 ++--
 arch/arm/kernel/process.c          |  4 +++-
 arch/arm/kernel/ptrace.c           |  2 +-
 arch/arm/kernel/traps.c            |  4 ++--
 6 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 1995d1a..214d415 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
 	struct cpu_context_save	cpu_context;	/* cpu context */
 	__u32			syscall;	/* syscall number */
 	__u8			used_cp[16];	/* thread used copro */
-	unsigned long		tp_value;
+	unsigned long		tp_value[2];	/* TLS registers */
 #ifdef CONFIG_CRUNCH
 	struct crunch_state	crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6..83259b8 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-	.macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+	.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
 	.endm
 
-	.macro set_tls_v6k, tp, tmp1, tmp2
+	.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+	mrc	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
 	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
-	mov	\tmp1, #0
-	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
+	mcr	p15, 0, \tpuser, c13, c0, 2	@ and the user r/w register
+	str	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_v6, tp, tmp1, tmp2
+	.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
 	ldr	\tmp1, =elf_hwcap
 	ldr	\tmp1, [\tmp1, #0]
 	mov	\tmp2, #0xffff0fff
 	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
-	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
-	movne	\tmp1, #0
-	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register
 	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	mrcne	p15, 0, \tmp2, c13, c0, 2	@ get the user r/w register
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	mcrne	p15, 0, \tpuser, c13, c0, 2	@ set user r/w register
+	strne	\tmp2, [\base, #TI_TP_VALUE + 4] @ save it
 	.endm
 
-	.macro set_tls_software, tp, tmp1, tmp2
+	.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
 	mov	\tmp1, #0xffff0fff
 	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
 	.endm
@@ -31,19 +34,30 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu		1
 #define has_tls_reg		1
-#define set_tls		set_tls_none
+#define switch_tls	switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu		0
 #define has_tls_reg		(elf_hwcap & HWCAP_TLS)
-#define set_tls		set_tls_v6
+#define switch_tls	switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu		0
 #define has_tls_reg		1
-#define set_tls		set_tls_v6k
+#define switch_tls	switch_tls_v6k
 #else
 #define tls_emu		0
 #define has_tls_reg		0
-#define set_tls		set_tls_software
+#define switch_tls	switch_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tpuser(void)
+{
+	unsigned long reg = 0;
+
+	if (has_tls_reg && !tls_emu)
+		__asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
+
+	return reg;
+}
+#endif
 #endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582b405..ee1d257 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -685,15 +685,15 @@ ENTRY(__switch_to)
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	add	ip, r1, #TI_CPU_SAVE
-	ldr	r3, [r2, #TI_TP_VALUE]
  ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
+	ldrd	r4, r5, [r2, #TI_TP_VALUE]
 #ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-	set_tls	r3, r4, r5
+	switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	ldr	r7, [r2, #TI_TASK]
 	ldr	r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f219703..0870641 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -343,7 +344,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
 	clear_ptrace_hw_breakpoint(p);
 
 	if (clone_flags & CLONE_SETTLS)
-		thread->tp_value = childregs->ARM_r3;
+		thread->tp_value[0] = childregs->ARM_r3;
+	thread->tp_value[1] = get_tpuser();
 
 	thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeff..2bc1514 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
 		case PTRACE_GET_THREAD_AREA:
-			ret = put_user(task_thread_info(child)->tp_value,
+			ret = put_user(task_thread_info(child)->tp_value[0],
 				       datap);
 			break;
 
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 18b32e8..517bfd4 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -581,7 +581,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		return regs->ARM_r0;
 
 	case NR(set_tls):
-		thread->tp_value = regs->ARM_r0;
+		thread->tp_value[0] = regs->ARM_r0;
 		if (tls_emu)
 			return 0;
 		if (has_tls_reg) {
@@ -699,7 +699,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
 	int reg = (instr >> 12) & 15;
 	if (reg == 15)
 		return 1;
-	regs->uregs[reg] = current_thread_info()->tp_value;
+	regs->uregs[reg] = current_thread_info()->tp_value[0];
 	regs->ARM_pc += 4;
 	return 0;
 }
-- 
1.8.1.2


From robdclark at gmail.com  Wed May 22 17:08:01 2013
From: robdclark at gmail.com (Rob Clark)
Date: Wed, 22 May 2013 17:08:01 -0400
Subject: [RFC 6/8] drm/i2c: nxp-tda998x: add video and audio input
 configuration
In-Reply-To: <E1Ud3pe-0001r0-HU@rmk-PC.arm.linux.org.uk>
References: <20130516192510.GV18614@n2100.arm.linux.org.uk>
 <E1Ud3pe-0001r0-HU@rmk-PC.arm.linux.org.uk>
Message-ID: <CAF6AEGu-G2YkhVkii-JZxCbijRJMK+z1+bSHgSiJKh3t2JnvPw@mail.gmail.com>

On Thu, May 16, 2013 at 3:27 PM, Russell King
<rmk+kernel at arm.linux.org.uk> wrote:
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  drivers/gpu/drm/i2c/tda998x_drv.c |  308 ++++++++++++++++++++++++++++++++++++-
>  1 files changed, 301 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
> index d6afd02..8ffb844 100644
> --- a/drivers/gpu/drm/i2c/tda998x_drv.c
> +++ b/drivers/gpu/drm/i2c/tda998x_drv.c
> @@ -23,7 +23,7 @@
>  #include <drm/drm_crtc_helper.h>
>  #include <drm/drm_encoder_slave.h>
>  #include <drm/drm_edid.h>
> -
> +#include <drm/i2c/tda998x.h>
>
>  #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
>
> @@ -32,9 +32,11 @@ struct tda998x_priv {
>         uint16_t rev;
>         uint8_t current_page;
>         int dpms;
> +       bool is_hdmi_sink;
>         u8 vip_cntrl_0;
>         u8 vip_cntrl_1;
>         u8 vip_cntrl_2;
> +       struct tda998x_encoder_params params;
>  };
>
>  #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
> @@ -71,10 +73,13 @@ struct tda998x_priv {
>  # define I2C_MASTER_DIS_MM        (1 << 0)
>  # define I2C_MASTER_DIS_FILT      (1 << 1)
>  # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
> +#define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
> +# define FEAT_POWERDOWN_SPDIF     (1 << 3)
>  #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
>  #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
>  #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
>  # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
> +#define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
>  #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
>  #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
>  #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
> @@ -113,6 +118,7 @@ struct tda998x_priv {
>  #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
>  # define VIP_CNTRL_5_CKCASE       (1 << 0)
>  # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
> +#define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
>  #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
>  #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
>  # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
> @@ -175,6 +181,12 @@ struct tda998x_priv {
>  # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
>  # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
>  #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
> +#define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
> +# define I2S_FORMAT(x)            (((x) & 3) << 0)
> +#define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
> +# define AIP_CLKSEL_FS(x)         (((x) & 3) << 0)
> +# define AIP_CLKSEL_CLK_POL(x)    (((x) & 1) << 2)
> +# define AIP_CLKSEL_AIP(x)        (((x) & 7) << 3)
>
>
>  /* Page 02h: PLL settings */
> @@ -216,6 +228,11 @@ struct tda998x_priv {
>
>
>  /* Page 10h: information frames and packets */
> +#define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
> +#define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
> +#define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
> +#define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
> +#define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
>
>
>  /* Page 11h: audio settings and content info packets */
> @@ -225,10 +242,33 @@ struct tda998x_priv {
>  # define AIP_CNTRL_0_LAYOUT       (1 << 2)
>  # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
>  # define AIP_CNTRL_0_RST_CTS      (1 << 6)
> +#define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
> +# define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
> +# define CA_I2S_HBR_CHSTAT        (1 << 6)
> +#define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
> +#define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
> +#define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
> +#define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
> +#define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
> +#define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
> +#define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
> +#define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
> +# define CTS_N_K(x)               (((x) & 7) << 0)
> +# define CTS_N_M(x)               (((x) & 3) << 4)
>  #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
>  # define ENC_CNTRL_RST_ENC        (1 << 0)
>  # define ENC_CNTRL_RST_SEL        (1 << 1)
>  # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
> +#define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
> +# define DIP_FLAGS_ACR            (1 << 0)
> +# define DIP_FLAGS_GC             (1 << 1)
> +#define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
> +# define DIP_IF_FLAGS_IF1         (1 << 1)
> +# define DIP_IF_FLAGS_IF2         (1 << 2)
> +# define DIP_IF_FLAGS_IF3         (1 << 3)
> +# define DIP_IF_FLAGS_IF4         (1 << 4)
> +# define DIP_IF_FLAGS_IF5         (1 << 5)
> +#define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
>
>
>  /* Page 12h: HDCP and OTP */
> @@ -344,6 +384,23 @@ reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt)
>         return ret;
>  }
>
> +static void
> +reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt)
> +{
> +       struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
> +       uint8_t buf[cnt+1];
> +       int ret;
> +
> +       buf[0] = REG2ADDR(reg);
> +       memcpy(&buf[1], p, cnt);
> +
> +       set_page(encoder, reg);
> +
> +       ret = i2c_master_send(client, buf, cnt + 1);
> +       if (ret < 0)
> +               dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
> +}
> +
>  static uint8_t
>  reg_read(struct drm_encoder *encoder, uint16_t reg)
>  {
> @@ -421,11 +478,192 @@ tda998x_reset(struct drm_encoder *encoder)
>         reg_write(encoder, REG_PLL_SCG2,     0x10);
>  }
>
> +static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
> +{
> +       uint8_t sum = 0;
> +
> +       while (bytes--)
> +               sum += *buf++;
> +       return (255 - sum) + 1;
> +}
> +
> +#define HB(x) (x)
> +#define PB(x) (HB(2) + 1 + (x))
> +
> +static void
> +tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr,
> +                uint8_t *buf, size_t size)
> +{
> +       buf[PB(0)] = tda998x_cksum(buf, size);
> +
> +       reg_clear(encoder, REG_DIP_IF_FLAGS, bit);
> +       reg_write_range(encoder, addr, buf, size);
> +       reg_set(encoder, REG_DIP_IF_FLAGS, bit);
> +}
> +
> +static void
> +tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p)
> +{
> +       uint8_t buf[PB(5) + 1];
> +
> +       buf[HB(0)] = 0x84;
> +       buf[HB(1)] = 0x01;
> +       buf[HB(2)] = 10;
> +       buf[PB(0)] = 0;
> +       buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
> +       buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
> +       buf[PB(4)] = p->audio_frame[4];
> +       buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
> +
> +       tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
> +                        sizeof(buf));
> +}
> +
> +static void
> +tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode)
> +{
> +       uint8_t buf[PB(13) + 1];
> +
> +       memset(buf, 0, sizeof(buf));
> +       buf[HB(0)] = 0x82;
> +       buf[HB(1)] = 0x02;
> +       buf[HB(2)] = 13;
> +       buf[PB(4)] = drm_match_cea_mode(mode);
> +
> +       tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
> +                        sizeof(buf));
> +}

fwiw, I expect you could use the hdmi infoframe helpers for some of
this (drivers/video/hdmi.c).. it is a relatively recent addition, in
case you hadn't seen them already

BR,
-R

> +static void tda998x_audio_mute(struct drm_encoder *encoder, bool on)
> +{
> +       if (on) {
> +               reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO);
> +               reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO);
> +               reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
> +       } else {
> +               reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
> +       }
> +}
> +
> +static void
> +tda998x_configure_audio(struct drm_encoder *encoder, struct tda998x_encoder_params *p)
> +{
> +       uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n;
> +       uint32_t n;
> +
> +       /* SetAudioPortConfig */
> +       reg_write(encoder, REG_ENA_AP, p->audio_cfg);
> +       /* SetAudioClockPortConfig */
> +       reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg);
> +
> +       /*
> +        * layout = channelAllocation ? 1 : 0;
> +        * AudioInSetConfig(format, i2sFormat, channelAllocation,
> +        *   HDMITX_CHAN_NO_CHANGE, HDMITX_CLKPOLDSD_NO_CHANGE,
> +        *   HDMITX_SWAPDSD_NO_CHANGE, layout, HDMITX_LATENCY_CURRENT,
> +        *   dstRate)
> +        */
> +       switch (p->audio_format) {
> +       case AFMT_SPDIF:
> +               reg_write(encoder, REG_MUX_AP, 0x40);
> +               clksel_aip = AIP_CLKSEL_AIP(0);
> +               /* FS64SPDIF */
> +               clksel_fs = AIP_CLKSEL_FS(2);
> +               cts_n = CTS_N_M(3) | CTS_N_K(3);
> +               ca_i2s = 0;
> +               break;
> +
> +       case AFMT_I2S:
> +               reg_write(encoder, REG_MUX_AP, 0x64);
> +               clksel_aip = AIP_CLKSEL_AIP(1);
> +               /* ACLK */
> +               clksel_fs = AIP_CLKSEL_FS(0);
> +               cts_n = CTS_N_M(3) | CTS_N_K(3);
> +               ca_i2s = CA_I2S_CA_I2S(0 /* channel allocation */);
> +               break;
> +       }
> +
> +       reg_write(encoder, REG_AIP_CLKSEL, clksel_aip);
> +//     reg_write(encoder, REG_CA_I2S, ca_i2s);
> +//     reg_write(encoder, REG_I2S_FORMAT, I2S_FORMAT(0 /* i2s format */));
> +       reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT);
> +       /* latency? */
> +
> +       /* get video format */
> +
> +       /*
> +        * ctsRef = HDMITX_CTSREF_FS64SPDIF, uCtsX = HDMITX_CTSX_64
> +        * AudioInSetCts(ctsRef, rate, VidFmt, vOutFreq,
> +        *   HDMITX_CTS_AUTO, uCtsX, HDMITX_CTSK_USE_CTSX,
> +        *   HDMITX_CTSMTS_USE_CTSX, dstRate)
> +        */
> +       /* Auto CTS */
> +       reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN);
> +       reg_write(encoder, REG_CTS_N, cts_n);
> +       reg_write(encoder, REG_AUDIO_DIV, 3);
> +
> +       /*
> +        * This is the approximate value of N, which happens to be
> +        * the recommended values for non-coherent clocks.
> +        */
> +       n = 128 * p->audio_sample_rate / 1000;
> +
> +       /* Write the CTS and N values */
> +       buf[0] = 0x44;
> +       buf[1] = 0x42;
> +       buf[2] = 0x01;
> +       buf[3] = n;
> +       buf[4] = n >> 8;
> +       buf[5] = n >> 16;
> +       reg_write_range(encoder, REG_ACR_CTS_0, buf, 6);
> +
> +       /* Set CTS clock reference */
> +       reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
> +
> +       /* Reset CTS generator */
> +       reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
> +       reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
> +
> +       /* Write the channel status */
> +       buf[0] = 0x04;
> +       buf[1] = 0x00;
> +       buf[2] = 0x00;
> +       buf[3] = 0xf1;
> +       reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4);
> +
> +       tda998x_audio_mute(encoder, true);
> +       mdelay(20);
> +       tda998x_audio_mute(encoder, false);
> +
> +       /* Write the audio information packet */
> +       tda998x_write_aif(encoder, p);
> +}
> +
>  /* DRM encoder functions */
>
>  static void
>  tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
>  {
> +       struct tda998x_priv *priv = to_tda998x_priv(encoder);
> +       struct tda998x_encoder_params *p = params;
> +
> +       priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
> +                           (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
> +                           VIP_CNTRL_0_SWAP_B(p->swap_b) |
> +                           (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
> +       priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
> +                           (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
> +                           VIP_CNTRL_1_SWAP_D(p->swap_d) |
> +                           (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
> +       priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
> +                           (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
> +                           VIP_CNTRL_2_SWAP_F(p->swap_f) |
> +                           (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
> +
> +       priv->params = *p;
> +
> +       if (p->audio_cfg)
> +               tda998x_configure_audio(encoder, p);
>  }
>
>  static void
> @@ -445,7 +683,8 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
>                 /* Write the default value MUX register */
>                 reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
>                 /* enable audio and video ports */
> -               reg_write(encoder, REG_ENA_AP, 0xff);
> +//             reg_write(encoder, REG_ENA_AP, priv->ena_ap);
> +//             reg_write(encoder, REG_ENA_ACLK, priv->ena_aclk);
>                 reg_write(encoder, REG_ENA_VP_0, 0xff);
>                 reg_write(encoder, REG_ENA_VP_1, 0xff);
>                 reg_write(encoder, REG_ENA_VP_2, 0xff);
> @@ -456,7 +695,7 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
>                 break;
>         case DRM_MODE_DPMS_OFF:
>                 /* disable audio and video ports */
> -               reg_write(encoder, REG_ENA_AP, 0x00);
> +//             reg_write(encoder, REG_ENA_AP, 0x00);
>                 reg_write(encoder, REG_ENA_VP_0, 0x00);
>                 reg_write(encoder, REG_ENA_VP_1, 0x00);
>                 reg_write(encoder, REG_ENA_VP_2, 0x00);
> @@ -607,17 +846,31 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
>         reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
>         reg_write16(encoder, REG_REFLINE_MSB, ref_line);
>
> -       reg = TBG_CNTRL_1_VHX_EXT_DE |
> -                       TBG_CNTRL_1_VHX_EXT_HS |
> -                       TBG_CNTRL_1_VHX_EXT_VS |
> -                       TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
> +       reg = TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
>                         TBG_CNTRL_1_VH_TGL_2;
> +       /*
> +        * It is questionable whether this is correct - the nxp driver
> +        * does not set VH_TGL_2 and the below for all display modes.
> +        */
>         if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC))
>                 reg |= TBG_CNTRL_1_VH_TGL_0;
>         reg_set(encoder, REG_TBG_CNTRL_1, reg);
>
>         /* must be last register set: */
>         reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
> +
> +       /* Only setup the info frames if the sink is HDMI */
> +       if (priv->is_hdmi_sink) {
> +               /* We need to turn HDMI HDCP stuff on to get audio through */
> +               reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
> +               reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
> +               reg_set(encoder, REG_TX33, TX33_HDMI);
> +
> +               tda998x_write_avi(encoder, adjusted_mode);
> +
> +               if (priv->params.audio_cfg)
> +                       tda998x_configure_audio(encoder, &priv->params);
> +       }
>  }
>
>  static enum drm_connector_status
> @@ -743,12 +996,14 @@ static int
>  tda998x_encoder_get_modes(struct drm_encoder *encoder,
>                          struct drm_connector *connector)
>  {
> +       struct tda998x_priv *priv = to_tda998x_priv(encoder);
>         struct edid *edid = (struct edid *)do_get_edid(encoder);
>         int n = 0;
>
>         if (edid) {
>                 drm_mode_connector_update_edid_property(connector, edid);
>                 n = drm_add_edid_modes(connector, edid);
> +               priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
>                 kfree(edid);
>         }
>
> @@ -810,6 +1065,40 @@ tda998x_remove(struct i2c_client *client)
>         return 0;
>  }
>
> +static ssize_t i2c_read_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size)
> +{
> +       struct drm_encoder *encoder = dev_get_drvdata(dev);
> +       unsigned int page, addr;
> +       unsigned char val;
> +
> +       sscanf(buf, "%x %x", &page, &addr);
> +
> +       val = reg_read(encoder, REG(page, addr));
> +
> +       printk("i2c read %02x @ page:%02x address:%02x\n", val, page, addr);
> +       return size;
> +}
> +
> +static ssize_t i2c_write_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size)
> +{
> +       struct drm_encoder *encoder = dev_get_drvdata(dev);
> +       unsigned int page, addr, mask, val;
> +       unsigned char rval;
> +
> +       sscanf(buf, "%x %x %x %x", &page, &addr, &mask, &val);
> +
> +       rval = reg_read(encoder, REG(page, addr));
> +       rval &= ~mask;
> +       rval |= val & mask;
> +       reg_write(encoder, REG(page, addr), rval);
> +
> +       printk("i2c write %02x @ page:%02x address:%02x\n", rval, page, addr);
> +       return size;
> +}
> +
> +static DEVICE_ATTR(i2c_read, S_IWUSR, NULL, i2c_read_store);
> +static DEVICE_ATTR(i2c_write, S_IWUSR, NULL, i2c_write_store);
> +
>  static int
>  tda998x_encoder_init(struct i2c_client *client,
>                     struct drm_device *dev,
> @@ -817,6 +1106,11 @@ tda998x_encoder_init(struct i2c_client *client,
>  {
>         struct drm_encoder *encoder = &encoder_slave->base;
>         struct tda998x_priv *priv;
> +/* debug */
> +       device_create_file(&client->dev, &dev_attr_i2c_read);
> +       device_create_file(&client->dev, &dev_attr_i2c_write);
> +       dev_set_drvdata(&client->dev, encoder);
> +/* debug end */
>
>         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>         if (!priv)
> --
> 1.7.4.4
>


From sebastian.hesselbarth at gmail.com  Wed May 22 17:17:46 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 May 2013 23:17:46 +0200
Subject: [PATCH v4 11/12] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <20130522210257.GM31290@titan.lakedaemon.net>
References: <1367854420-8006-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369154510-4927-12-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522203633.GA28394@schnuecks.de> <519D30CF.9040904@gmail.com>
 <20130522210257.GM31290@titan.lakedaemon.net>
Message-ID: <519D35FA.2060002@gmail.com>

On 05/22/2013 11:02 PM, Jason Cooper wrote:
> On Wed, May 22, 2013 at 10:55:43PM +0200, Sebastian Hesselbarth wrote:
>> On 05/22/2013 10:36 PM, Simon Baatz wrote:
>>> Hi Sebastian,
>>>
>>> On Tue, May 21, 2013 at 06:41:49PM +0200, Sebastian Hesselbarth wrote:
>>>> With DT support for mv643xx_eth, board specific init for some boards now
>>>> is unneccessary. Remove those board files, Kconfig entries, and
>>>> corresponding entries in kirkwood_defconfig.
>>>>
>>>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
>>>> ---
>>>> Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
>>>> the lock-up is not caused by accessing clock gating registers but rather
>>>> non-existent device registers. This will be addressed by dtsi separation
>>>> for kirkwood and bobcat SoC variants.
>>>>
>>>> Changelog:
>>>> v3->v4:
>>>> - remove more boards that don't require board specific setup
>>>>
>> ...
>>
>> I would stick with "marvell,kirkwood" only. This is SoC init code and
>> we do not distinguish variants here at all.
>
> Agreed, nice catch Simon.

I just confirmed all kirkwood dts/dtsi properly set "marvell,kirkwood"
in their compatible strings. Will remove all other comapatible strings
from mach-kirkwood/board-dt.c as Simon suggested for v5.

Sebastian


From swarren at wwwdotorg.org  Wed May 22 17:18:54 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 15:18:54 -0600
Subject: [PATCH] ARM: tegra: add cpu_disable for hotplug
In-Reply-To: <20130522090304.GT21944@tbergstrom-lnx.Nvidia.com>
References: <1369131215-2920-1-git-send-email-josephl@nvidia.com>
 <519B9DB4.7070106@wwwdotorg.org>
 <20130522090304.GT21944@tbergstrom-lnx.Nvidia.com>
Message-ID: <519D363E.4000409@wwwdotorg.org>

On 05/22/2013 03:03 AM, Peter De Schrijver wrote:
> On Tue, May 21, 2013 at 06:15:48PM +0200, Stephen Warren wrote:
>> On 05/21/2013 04:13 AM, Joseph Lo wrote:
>>> The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
>>> support that. Adding a Tegra specific cpu_disable function for it.
>>>
>>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
>>
>>> diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
>>
>>> +int tegra_cpu_disable(unsigned int cpu)
>>> +{
>>> +	switch (tegra_chip_id) {
>>> +	case TEGRA114:
>>> +		return 0;
>>> +	default:
>>> +		return cpu == 0 ? -EPERM : 0;
>>> +	}
>>> +}
>>
>> Do we expect all/most future chips to support hotplug of CPU0? Or at
>> least, fewer chips to have the restriction than not? If so, it might be
> 
> Yes. I think we can safely assume future chips will support hotplugging CPU0.
> 
>> more forward-looking to write that as:
>>
>> if (tegra_chip_id == TEGRA30)
>>     return cpu == 0 ? -EPERM : 0;
>>
> 
> Also Tegra20 doesn't support hotplugging CPU0?

Oh right, this isn't a Tegra30+ file. How about just inverting the
switch so it doesn't need to change later:

	switch (tegra_chip_id) {
	case TEGRA20:
	case TEGRA30:
		return cpu == 0 ? -EPERM : 0;
	default:
		return 0;
	}



From aaro.koskinen at iki.fi  Wed May 22 17:20:54 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Thu, 23 May 2013 00:20:54 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <519BCCEC.8010303@gmail.com>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com>
 <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
Message-ID: <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>

On Tue, May 21, 2013 at 08:37:16PM +0100, Jon Hunter wrote:
> On 21/05/13 18:39, Aaro Koskinen wrote:
> > On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
> >> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
> >>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
> >>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> >>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> >>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> >>>>>>
> >>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> >>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> >>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> >>>>>>
> >>>>>> The error is coming from regmap code. According to git bisect, it is
> >>>>>> caused by:
> >>>>>>
> >>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> >>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
> >>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
> >>>>>>
> >>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
> >>>>>>
> >>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
> >>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
> >>>>>
> >>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
> >>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> >>>>>
> >>>>> For the -rc cycle, it might be possible to fix this by adding a
> >>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
> >>>>
> >>>> The commit reverts cleanly if we also revert
> >>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
> >>>> service routine), which seems to be just some minor optimization. The
> >>>> result is below, and with it 770 works again.
> >>>
> >>> Hmm in this case it seems that we should just fix it rather than go back
> >>> to the old code, so let's take a look at that first.
> >>
> >> Does the following fix it for you or do we need to fix something else
> >> there too?
> > 
> > Thanks, that fixes Retu probe on 770.
> 
> Sorry for not responding sooner, but I have been moving. 
> 
> From looking at the code it appears that the regmap_add_irq_chip()
> is failing in the retu driver. I am not sure if this will work, 
> but have you tried making the following change to the retu driver 
> so that it also uses irq_domain_add_linear() as well? Just a thought ...

This will trigger WARNING: at drivers/base/regmap/regmap-irq.c:514.

Also other drivers report GPIO IRQ issues later in the boot, e.g.

[    3.907928] genirq: Flags mismatch irq 0. 00000001 (serial wakeup) vs. 00002000 (RETU)
[    3.923706] No interrupt for UART wake GPIO: 37

With Tony's patch (without any Retu modifications), the boot is clean. So
I guess gpio-omap fix is needed.

A.

> diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
> index a183098..7ad8cd4 100644
> --- a/drivers/mfd/retu-mfd.c
> +++ b/drivers/mfd/retu-mfd.c
> @@ -267,7 +267,7 @@ static int retu_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
>         if (ret < 0)
>                 return ret;
>  
> -       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, -1,
> +       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, 0,
>                                   rdat->irq_chip, &rdev->irq_data);
>         if (ret < 0)
>                 return ret;
> 


From swarren at wwwdotorg.org  Wed May 22 17:21:24 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 May 2013 15:21:24 -0600
Subject: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
Message-ID: <519D36D4.3010100@wwwdotorg.org>

On 05/20/2013 04:39 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.

I have applied the series to Tegra's for-3.11/soc branch.


From robherring2 at gmail.com  Wed May 22 17:27:55 2013
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 22 May 2013 16:27:55 -0500
Subject: [RFC/PATCH 0/2] Remove most of_device_match() calls
In-Reply-To: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>
References: <1369255217-29764-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <CAL_JsqLm5VAj-5ctWVsCmx5Jewv-hyi2j65XWo4h1WFBMPPumg@mail.gmail.com>

On Wed, May 22, 2013 at 3:40 PM, Stephen Boyd <sboyd at codeaurora.org> wrote:
> Sending this as an RFC with one driver converted to see what people
> think. The goal is to avoid having to run the match twice and be
> similar to how platform_device_id works right now. If people agree
> I can go through and send out patches for all the drivers doing
> the duplicate search (~100 files).
>

See this commit:

commit b1608d69cb804e414d0887140ba08a9398e4e638
Author: Grant Likely <grant.likely at secretlab.ca>
Date:   Wed May 18 11:19:24 2011 -0600

    drivercore: revert addition of of_match to struct device

    Commit b826291c, "drivercore/dt: add a match table pointer to struct
    device" added an of_match pointer to struct device to cache the
    of_match_table entry discovered at driver match time.  This was unsafe
    because matching is not an atomic operation with probing a driver.  If
    two or more drivers are attempted to be matched to a driver at the
    same time, then the cached matching entry pointer could get
    overwritten.

    This patch reverts the of_match cache pointer and reworks all users to
    call of_match_device() directly instead.

    Signed-off-by: Grant Likely <grant.likely at secretlab.ca>


From thomas.petazzoni at free-electrons.com  Wed May 22 17:31:08 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 22 May 2013 23:31:08 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305222240.05124.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <201305222240.05124.arnd@arndb.de>
Message-ID: <20130522233108.01cb51f0@skate>

Dear Arnd Bergmann,

On Wed, 22 May 2013 22:40:04 +0200, Arnd Bergmann wrote:

> > So you're proposing to add two Kconfig options, one to have the UART at
> > 0xd0012000 and the other one to have the UART at 0xf1012000. The user
> > would have to know whether he is going to boot with an old bootloader
> > or new bootloader, and select the appropriate option. This means that
> > the mvebu_defconfig would no longer be able to have earlyprintk enabled
> > by default, otherwise the resulting kernel may not boot for some
> > people, but maybe it's a reasonable tradeoff.
> 
> Yes. It may also be reasonable to use the CP15 hack for DEBUG_LL, but
> I would not like to see that information getting used anywhere in the
> kernel outside of DEBUG_LL. That should really come from the DT.

Ok.


> > Conclusion: you can't classify on one side boards that are at 0xd0 and
> > boards that are at 0xf1. It depends on which bootloader each
> > particular instance of those boards will be using. Will it be a
> > bootloader that complies with the "old" protocol (CP15 bit cleared and
> > registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> > 0xf1).
> > 
> > So we can't encode into the boards Device Tree whether the registers
> > are at 0xd0 or 0xf1, because it's not a board-related information, but
> > a bootloader-related information.
> 
> The new boot loaders will of course know that they are remapping the
> registers, so they are also able to put the correct information into the
> DT.

The thing that I believe you don't realize is that those new bootloaders
are already shipping *today*. And they are not putting whatever
"correct" information into the DT you believe they should be putting.

So what do we do, today, with those new bootloaders, that are not the
future, but the present. Again, they do *not* add any information in
the DT that allows us to know that they have remapped the registers to
0xf1.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From Milo.Kim at ti.com  Wed May 22 19:14:49 2013
From: Milo.Kim at ti.com (Kim, Milo)
Date: Wed, 22 May 2013 23:14:49 +0000
Subject: [PATCH] ARM: ux500: register LP5521 LEDs in the device tree
In-Reply-To: <1369210331-18545-1-git-send-email-linus.walleij@stericsson.com>
References: <1369210331-18545-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <A874F61F95741C4A9BA573A70FE3998F82E5FC0E@DQHE06.ent.ti.com>

> Based on pending device tree support in the LP55xx drivers
> we can add the correct LED and channel configuration from the
> ux500 device tree for all HREF variants.
> 
> Cc: Milo Kim <Milo.Kim at ti.com>
> Cc: Bryan Wu <cooloney at gmail.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Acked-by: Milo Kim <Milo.Kim at ti.com>


From w at 1wt.eu  Wed May 22 20:13:53 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Thu, 23 May 2013 02:13:53 +0200
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130523001353.GH31625@1wt.eu>

Hi Thomas,

On Wed, May 22, 2013 at 03:12:34PM +0200, Thomas Petazzoni wrote:
> Bjorn, Jason, Andrew, Gregory,
> 
> You'll find in this patch series 4 small patches that make various
> improvements to the Marvell PCIe driver.
(...)

FWIW, these patches applied on top of your pcie-v10 tree have made
my mini-pcie dual-nic appear for the first time on the mirabox. Till
now I never knew if it was a hardware or software issue since the NIC
does not appear in u-boot nor lspci, whatever the kernel versions,
including the original Marvell one's. The NIC has two functions (one
per controller) and no bridge, so it may be a side effect of your
improvements (or maybe you fixed a bug).

Anyway for me it's a great improvement !

I've not tried it on the OpenBlocks AX3 yet (it was not detected
there previously). But I have good hopes.

For reference, the NIC is Jetway's ADMPEIDLA (intel i350-AM2).

Best regards,
Willy



From gang.chen at asianux.com  Wed May 22 21:00:45 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Thu, 23 May 2013 09:00:45 +0800
Subject: [PATCH] kernel/sched/core.c: need return NULL when BUG() is
 defined as empty.
In-Reply-To: <20130522161935.GR18810@twins.programming.kicks-ass.net>
References: <5199D565.4070307@asianux.com>
 <20130522091156.GC18810@twins.programming.kicks-ass.net>
 <20130522133317.GC18614@n2100.arm.linux.org.uk>
 <20130522161935.GR18810@twins.programming.kicks-ass.net>
Message-ID: <519D6A3D.5050003@asianux.com>

On 05/23/2013 12:19 AM, Peter Zijlstra wrote:
> On Wed, May 22, 2013 at 02:33:17PM +0100, Russell King - ARM Linux wrote:
>> > On Wed, May 22, 2013 at 11:11:56AM +0200, Peter Zijlstra wrote:
>>> > > On Mon, May 20, 2013 at 03:48:53PM +0800, Chen Gang wrote:
>>>> > > > 
>>>> > > > When neither CONFIG_BUG nor HAVE_ARCH_BUG is defined, need let function
>>>> > > > return failure value ('NULL') instead of random value.
>>> > > 
>>> > > What will such a kernel do? Happily continue running whenever we hit a
>>> > > BUG? that seems like a particularly bad idea. Should we not have a stub
>>> > > BUG() function like:
>>> > > 
>>> > > void BUG(void) __attribute__((noreturn))
>>> > > {
>>> > > 	local_irq_disable();
>>> > > 	while (1) ;
>>> > > }
>> > 
>> > Eww.  So you've a platform where you have things like panic_on_oops
>> > enabled, and you hit this bug... do we really want to just stop?
>> > Wouldn't replacing BUG() with panic("BUG"); be better ?
>> > 
>> > But, this begs the question - what is the point of being able to turn
>> > off BUG() ?  As BUG() on any sensible architecture is implemented by
>> > placing the minimum of code at the callsite (eg, one instruction if
>> > not using verbose) anything like the above is likely to be bigger.
>> > 
>> > So, I'd actually argue that rather than trying to "fix" this, get rid
>> > of CONFIG_BUG and make it always enabled everywhere - just like what
>> > has recently been done with hotplug.
> Works for me. 
> 

Thanks all, I should send the related patch for it.

Excuse me, I have to do another things, so I will finish it within this
week (2013-05-26)

Welcome any additional suggestions and completions.


Thanks.
-- 
Chen Gang

Asianux Corporation


From kgene.kim at samsung.com  Wed May 22 21:11:17 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 23 May 2013 10:11:17 +0900
Subject: [PATCH] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
References: <1368630484-29939-1-git-send-email-t.figa@samsung.com>
 <1623377.nVo7nUcid2@flatron>
Message-ID: <120501ce5752$6daef380$490cda80$%kim@samsung.com>

Kukjin Kim wrote:
> 
> Tomasz Figa wrote:
> >
> > Hi Kukjin,
> >
> Hi,
> 
> > On Wednesday 15 of May 2013 17:08:04 Tomasz Figa wrote:
> > > This patch extends exynos_init_time() function to handle Exynos4210
> rev0
> > > SoC, which differs in availability of system timers and needs
> different
> > > clocksource initialization.
> > >
> > > This makes it possible to use exynos_init_time() function as init_time
> > > callback for all Exynos-based boards, including Universal_C210, which
> > > originally had to use samsung_timer_init().
> > >
> > > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > > ---
> > >  arch/arm/mach-exynos/Kconfig               |  3 ++-
> > >  arch/arm/mach-exynos/common.c              | 30
> > > +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h
> > >   |  2 ++
> > >  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++---
> > >  4 files changed, 35 insertions(+), 5 deletions(-)
> >
> > Could you pick this patch to your fixes branch?
> >
> Yeah, I will after looking at.
> 
> > This is a fix of a regression in handling Exynos4210 rev0 SoC (e.g.
> > Universal C210 board) introduced by patches merged to 3.10.
> >
> OK, I see but I didn't review yet and I  will within a couple of days ;-)
> 
OK, looks fine, this will be sent to upstream during -rc for v3.10.

But, Tomasz, as you know, non-DT supporting files will be gone away in
v3.11, just note.

Thanks.

- Kukjin



From horms at verge.net.au  Wed May 22 21:39:02 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 23 May 2013 10:39:02 +0900
Subject: [PATCH v4 4/7] ARM: shmobile: sh73a0: Add timer DT names to
 clock list
In-Reply-To: <1365679443-25456-4-git-send-email-hechtb+renesas@gmail.com>
References: <1365679443-25456-1-git-send-email-hechtb+renesas@gmail.com>
 <1365679443-25456-4-git-send-email-hechtb+renesas@gmail.com>
Message-ID: <20130523013902.GB22608@verge.net.au>

On Thu, Apr 11, 2013 at 01:24:00PM +0200, Bastian Hecht wrote:
> This adds temporarily the alternative device names to the clock list
> that are used when booting via Device Tree setup.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>

As per my recent email regarding "ARM: shmobile: sh73a0: Add timer DT names
to clock list", I have dropped this patch which was previously queued-up
for v3.11.

> ---
> v4: same. only patches 2 and 3 are changed.
> 
>  arch/arm/mach-shmobile/clock-sh73a0.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
> index 784fbaa..5d98322 100644
> --- a/arch/arm/mach-shmobile/clock-sh73a0.c
> +++ b/arch/arm/mach-shmobile/clock-sh73a0.c
> @@ -535,7 +535,9 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
>  	CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
>  	CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
> +	CLKDEV_DEV_ID("fff60008.timer", &mstp_clks[MSTP125]), /* TMU00 */
>  	CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
> +	CLKDEV_DEV_ID("fff60014.timer", &mstp_clks[MSTP125]), /* TMU01 */
>  	CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
>  	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
>  	CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
> @@ -552,6 +554,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
>  	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
>  	CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
> +	CLKDEV_DEV_ID("e6138010.timer", &mstp_clks[MSTP329]), /* CMT10 */
>  	CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
>  	CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
>  	CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
> -- 
> 1.7.9.5
> 


From horms at verge.net.au  Wed May 22 21:39:08 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 23 May 2013 10:39:08 +0900
Subject: [PATCH v4 1/7] ARM: shmobile: Define DT bindings for timer devices
In-Reply-To: <1365679443-25456-1-git-send-email-hechtb+renesas@gmail.com>
References: <1365679443-25456-1-git-send-email-hechtb+renesas@gmail.com>
Message-ID: <20130523013908.GC22608@verge.net.au>

On Thu, Apr 11, 2013 at 01:23:57PM +0200, Bastian Hecht wrote:
> The SH mobile series currently features 3 timer devices in the kernel:
> Compare Match Timer (CMT), Timer Unit (TMU) and MTU2. These devices
> share register layout characteristics amongst each that enable us to
> define common DT bindings for them.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> ---
> v4: same. only patch 2 and 3 changed

As per my recent email regarding "ARM: shmobile: sh73a0: Add timer DT names
to clock list", I have dropped this patch which was previously queued-up
for v3.11.

> 
>  .../devicetree/bindings/timer/renesas,timer.txt    |   45 ++++++++++++++++++++
>  1 file changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/renesas,timer.txt
> 
> diff --git a/Documentation/devicetree/bindings/timer/renesas,timer.txt b/Documentation/devicetree/bindings/timer/renesas,timer.txt
> new file mode 100644
> index 0000000..2c001bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/renesas,timer.txt
> @@ -0,0 +1,45 @@
> +* Renesas SH Mobile Timer
> +
> +Bindings for several timer devices from Renesas including CMT, TMU and MTU2.
> +
> +Required properties:
> +- compatible : Should be "renesas,{device}-timer",
> +  whereas device is "cmt", "tmu" or "mtu2".
> +- reg : Address and length of the register set for the device
> +- interrupts : Timer interrupt
> +- renesas,device-id : The ID of the timer device
> +- renesas,channel-id : The channel ID of the timer device
> +- renesas,source-quality : The viability to use this device as a free
> +  running clock. From 0 (do not use) to 10 (best possible clock).
> +- renesas,event-quality : The viability to use this device as an event
> +  generator. From 0 (do not use) to 10 (best possible clock).
> +
> +The properties renesas,{source,event}-quality reflect the situation that the
> +usability of the timer devices depend on the location within their SoCs. E.g.
> +the power domain affinty affects power management, some mux-ed lines might be
> +preferred to be assigned to other functions and other constraints.
> +
> +Example for CMT1 channel 0 on the R8A7740 SoC:
> +
> +	timer at e6138010 {
> +		compatible = "renesas,cmt-timer";
> +		interrupt-parent = <&intca>;
> +		reg = <0xe6138010 0xc>;
> +		interrupts = <0x0b00>;
> +		renesas,device-id = <1>;
> +		renesas,channel-id = <0>;
> +		renesas,source-quality = <3>;
> +		renesas,event-quality = <3>;
> +	};
> +
> +Example for TMU0 channel 1 on the SH7372 SoC:
> +	timer at fff60014 {
> +		compatible = "renesas,tmu-timer";
> +		interrupt-parent = <&intcs>;
> +		reg = <0xfff60014 0xc>;
> +		interrupts = <0xea0>;
> +		renesas,device-id = <0>;
> +		renesas,channel-id = <1>;
> +		renesas,source-quality = <4>;
> +		renesas,event-quality = <0>;
> +	};
> -- 
> 1.7.9.5
> 


From horms at verge.net.au  Wed May 22 21:39:14 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 23 May 2013 10:39:14 +0900
Subject: [PATCH v4 2/7] clocksource: sh_cmt: Add OF support
In-Reply-To: <1365679443-25456-2-git-send-email-hechtb+renesas@gmail.com>
References: <1365679443-25456-1-git-send-email-hechtb+renesas@gmail.com>
 <1365679443-25456-2-git-send-email-hechtb+renesas@gmail.com>
Message-ID: <20130523013914.GD22608@verge.net.au>

On Thu, Apr 11, 2013 at 01:23:58PM +0200, Bastian Hecht wrote:
> We add the capabilty to probe SH CMT timer devices using Device Tree
> setup.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>

As per my recent email regarding "ARM: shmobile: sh73a0: Add timer DT names
to clock list", I have dropped this patch which was previously queued-up
for v3.11.

> ---
> v4:
> Moved the assignments of p->channel_offset and p->timer_bit so that
> they are ready as soon as setup_irq() is called
> 
>  drivers/clocksource/sh_cmt.c |  108 +++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 95 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
> index 08d0c41..66a12e9 100644
> --- a/drivers/clocksource/sh_cmt.c
> +++ b/drivers/clocksource/sh_cmt.c
> @@ -34,10 +34,13 @@
>  #include <linux/module.h>
>  #include <linux/pm_domain.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/of.h>
>  
>  struct sh_cmt_priv {
>  	void __iomem *mapbase;
>  	struct clk *clk;
> +	long channel_offset;
> +	int timer_bit;
>  	unsigned long width; /* 16 or 32 bit version of hardware block */
>  	unsigned long overflow_bit;
>  	unsigned long clear_bits;
> @@ -109,9 +112,7 @@ static void sh_cmt_write32(void __iomem *base, unsigned long offs,
>  
>  static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p)
>  {
> -	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
> -
> -	return p->read_control(p->mapbase - cfg->channel_offset, 0);
> +	return p->read_control(p->mapbase - p->channel_offset, 0);
>  }
>  
>  static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p)
> @@ -127,9 +128,7 @@ static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p)
>  static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p,
>  				      unsigned long value)
>  {
> -	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
> -
> -	p->write_control(p->mapbase - cfg->channel_offset, 0, value);
> +	p->write_control(p->mapbase - p->channel_offset, 0, value);
>  }
>  
>  static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p,
> @@ -176,7 +175,6 @@ static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
>  
>  static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
>  {
> -	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
>  	unsigned long flags, value;
>  
>  	/* start stop register shared by multiple timer channels */
> @@ -184,9 +182,9 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
>  	value = sh_cmt_read_cmstr(p);
>  
>  	if (start)
> -		value |= 1 << cfg->timer_bit;
> +		value |= 1 << p->timer_bit;
>  	else
> -		value &= ~(1 << cfg->timer_bit);
> +		value &= ~(1 << p->timer_bit);
>  
>  	sh_cmt_write_cmstr(p, value);
>  	raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
> @@ -673,15 +671,93 @@ static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
>  	return 0;
>  }
>  
> -static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
> +static const struct of_device_id of_sh_cmt_match[] = {
> +	{ .compatible = "renesas,cmt-timer" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, of_sh_cmt_match);
> +
> +static const int sh_cmt_offset_multiplier[] = { 0x60, 0x10, 0x40, 0x40, 0x40 };
> +#define CMT_MAX_CHANNELS	6
> +
> +static struct sh_timer_config *sh_cmt_parse_dt(struct device *dev)
> +{
> +	struct sh_timer_config *cfg;
> +	struct device_node *np = dev->of_node;
> +	u32 timer_id, channel_id, rating;
> +
> +	if (!IS_ENABLED(CONFIG_OF) || !np)
> +		return NULL;
> +
> +	cfg = devm_kzalloc(dev, sizeof(struct sh_timer_config), GFP_KERNEL);
> +	if (!cfg) {
> +		dev_err(dev, "failed to allocate DT config data\n");
> +		return NULL;
> +	}
> +
> +	if (of_property_read_u32(np, "renesas,device-id", &timer_id)) {
> +		dev_err(dev, "device id missing\n");
> +		return NULL;
> +	}
> +	if (timer_id >= ARRAY_SIZE(sh_cmt_offset_multiplier)) {
> +		dev_err(dev, "invalid device id\n");
> +		return NULL;
> +	}
> +
> +	if (of_property_read_u32(np, "renesas,channel-id", &channel_id)) {
> +		dev_err(dev, "channel id missing\n");
> +		return NULL;
> +	}
> +	if (channel_id >= CMT_MAX_CHANNELS) {
> +		dev_err(dev, "invalid channel id\n");
> +		return NULL;
> +	}
> +
> +	cfg->channel_offset = sh_cmt_offset_multiplier[timer_id] *
> +							(channel_id + 1);
> +	cfg->timer_bit = channel_id;
> +
> +	/*
> +	 * We convert the {source,event}-quality DT properties to linux specific
> +	 * clock{source,event}_ratings.
> +	 */
> +	if (!of_property_read_u32(np, "renesas,source-quality", &rating)) {
> +		if (rating > 10) {
> +			dev_err(dev, "invalid source-quality\n");
> +			return NULL;
> +		}
> +		if (rating)
> +			cfg->clocksource_rating = rating * 50 - 1;
> +	}
> +
> +	if (!of_property_read_u32(np, "renesas,event-quality", &rating)) {
> +		if (rating > 10) {
> +			dev_err(dev, "invalid event-quality\n");
> +			return NULL;
> +		}
> +		if (rating)
> +			cfg->clockevent_rating = rating * 50 - 1;
> +	}
> +
> +	if (!cfg->clocksource_rating && !cfg->clockevent_rating) {
> +		dev_err(dev, "source- and event-quality 0, timer is unused\n");
> +		return NULL;
> +	}
> +
> +	return cfg;
> +}
> +
> +static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev,
> +						struct sh_timer_config *cfg)
>  {
> -	struct sh_timer_config *cfg = pdev->dev.platform_data;
>  	struct resource *res;
>  	int irq, ret;
>  	ret = -ENXIO;
>  
>  	memset(p, 0, sizeof(*p));
>  	p->pdev = pdev;
> +	p->channel_offset = cfg->channel_offset;
> +	p->timer_bit = cfg->timer_bit;
>  
>  	if (!cfg) {
>  		dev_err(&p->pdev->dev, "missing platform data\n");
> @@ -777,7 +853,7 @@ err0:
>  static int sh_cmt_probe(struct platform_device *pdev)
>  {
>  	struct sh_cmt_priv *p = platform_get_drvdata(pdev);
> -	struct sh_timer_config *cfg = pdev->dev.platform_data;
> +	struct sh_timer_config *cfg;
>  	int ret;
>  
>  	if (!is_early_platform_device(pdev)) {
> @@ -785,6 +861,11 @@ static int sh_cmt_probe(struct platform_device *pdev)
>  		pm_runtime_enable(&pdev->dev);
>  	}
>  
> +	if (pdev->dev.of_node)
> +		cfg = sh_cmt_parse_dt(&pdev->dev);
> +	else
> +		cfg = pdev->dev.platform_data;
> +
>  	if (p) {
>  		dev_info(&pdev->dev, "kept as earlytimer\n");
>  		goto out;
> @@ -796,7 +877,7 @@ static int sh_cmt_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  	}
>  
> -	ret = sh_cmt_setup(p, pdev);
> +	ret = sh_cmt_setup(p, pdev, cfg);
>  	if (ret) {
>  		kfree(p);
>  		pm_runtime_idle(&pdev->dev);
> @@ -824,6 +905,7 @@ static struct platform_driver sh_cmt_device_driver = {
>  	.remove		= sh_cmt_remove,
>  	.driver		= {
>  		.name	= "sh_cmt",
> +		.of_match_table = of_match_ptr(of_sh_cmt_match),
>  	}
>  };
>  
> -- 
> 1.7.9.5
> 


From horms at verge.net.au  Wed May 22 21:39:18 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 23 May 2013 10:39:18 +0900
Subject: [PATCH v4 3/7] clocksource: sh_tmu: Add OF support
In-Reply-To: <1365679443-25456-3-git-send-email-hechtb+renesas@gmail.com>
References: <1365679443-25456-1-git-send-email-hechtb+renesas@gmail.com>
 <1365679443-25456-3-git-send-email-hechtb+renesas@gmail.com>
Message-ID: <20130523013918.GE22608@verge.net.au>

On Thu, Apr 11, 2013 at 01:23:59PM +0200, Bastian Hecht wrote:
> We add the capabilty to probe SH CMT timer devices using Device Tree
> setup.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>

As per my recent email regarding "ARM: shmobile: sh73a0: Add timer DT names
to clock list", I have dropped this patch which was previously queued-up
for v3.11.

> ---
> v4:
> Moved the assignments of p->channel_offset and p->timer_bit so that
> they are ready as soon as setup_irq() is called.
> 
>  drivers/clocksource/sh_tmu.c |   96 +++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 85 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
> index 78b8dae..17bb607 100644
> --- a/drivers/clocksource/sh_tmu.c
> +++ b/drivers/clocksource/sh_tmu.c
> @@ -34,10 +34,13 @@
>  #include <linux/module.h>
>  #include <linux/pm_domain.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/of.h>
>  
>  struct sh_tmu_priv {
>  	void __iomem *mapbase;
>  	struct clk *clk;
> +	long channel_offset;
> +	int timer_bit;
>  	struct irqaction irqaction;
>  	struct platform_device *pdev;
>  	unsigned long rate;
> @@ -57,12 +60,11 @@ static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
>  
>  static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
>  {
> -	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
>  	void __iomem *base = p->mapbase;
>  	unsigned long offs;
>  
>  	if (reg_nr == TSTR)
> -		return ioread8(base - cfg->channel_offset);
> +		return ioread8(base - p->channel_offset);
>  
>  	offs = reg_nr << 2;
>  
> @@ -75,12 +77,11 @@ static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
>  static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
>  				unsigned long value)
>  {
> -	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
>  	void __iomem *base = p->mapbase;
>  	unsigned long offs;
>  
>  	if (reg_nr == TSTR) {
> -		iowrite8(value, base - cfg->channel_offset);
> +		iowrite8(value, base - p->channel_offset);
>  		return;
>  	}
>  
> @@ -94,7 +95,6 @@ static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
>  
>  static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
>  {
> -	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
>  	unsigned long flags, value;
>  
>  	/* start stop register shared by multiple timer channels */
> @@ -102,9 +102,9 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
>  	value = sh_tmu_read(p, TSTR);
>  
>  	if (start)
> -		value |= 1 << cfg->timer_bit;
> +		value |= 1 << p->timer_bit;
>  	else
> -		value &= ~(1 << cfg->timer_bit);
> +		value &= ~(1 << p->timer_bit);
>  
>  	sh_tmu_write(p, TSTR, value);
>  	raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
> @@ -421,15 +421,83 @@ static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
>  	return 0;
>  }
>  
> -static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
> +static const struct of_device_id of_sh_tmu_match[] = {
> +	{ .compatible = "renesas,tmu-timer" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, of_sh_tmu_match);
> +
> +#define TMU_OFFSET_MULTIPLIER	0xc
> +#define TMU_MAX_CHANNELS	3
> +
> +static struct sh_timer_config *sh_tmu_parse_dt(struct device *dev)
> +{
> +	struct sh_timer_config *cfg;
> +	struct device_node *np = dev->of_node;
> +	u32 channel_id, rating;
> +
> +	if (!IS_ENABLED(CONFIG_OF) || !np)
> +		return NULL;
> +
> +	cfg = devm_kzalloc(dev, sizeof(struct sh_timer_config), GFP_KERNEL);
> +	if (!cfg) {
> +		dev_err(dev, "failed to allocate DT config data\n");
> +		return NULL;
> +	}
> +
> +	if (of_property_read_u32(np, "renesas,channel-id", &channel_id)) {
> +		dev_err(dev, "channel id missing\n");
> +		return NULL;
> +	}
> +	if (channel_id >= TMU_MAX_CHANNELS) {
> +		dev_err(dev, "invalid channel id\n");
> +		return NULL;
> +	}
> +
> +	cfg->channel_offset = channel_id * TMU_OFFSET_MULTIPLIER + 4;
> +	cfg->timer_bit = channel_id;
> +
> +	/*
> +	 * We convert the {source,event}-quality DT properties to linux specific
> +	 * clock{source,event}_ratings.
> +	 */
> +	if (!of_property_read_u32(np, "renesas,source-quality", &rating)) {
> +		if (rating > 10) {
> +			dev_err(dev, "invalid source-quality\n");
> +			return NULL;
> +		}
> +		if (rating)
> +			cfg->clocksource_rating = rating * 50 - 1;
> +	}
> +
> +	if (!of_property_read_u32(np, "renesas,event-quality", &rating)) {
> +		if (rating > 10) {
> +			dev_err(dev, "invalid event-quality\n");
> +			return NULL;
> +		}
> +		if (rating)
> +			cfg->clockevent_rating = rating * 50 - 1;
> +	}
> +
> +	if (!cfg->clocksource_rating && !cfg->clockevent_rating) {
> +		dev_err(dev, "source- and event-quality 0, timer is unused\n");
> +		return NULL;
> +	}
> +
> +	return cfg;
> +}
> +
> +static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev,
> +						struct sh_timer_config *cfg)
>  {
> -	struct sh_timer_config *cfg = pdev->dev.platform_data;
>  	struct resource *res;
>  	int irq, ret;
>  	ret = -ENXIO;
>  
>  	memset(p, 0, sizeof(*p));
>  	p->pdev = pdev;
> +	p->channel_offset = cfg->channel_offset;
> +	p->timer_bit = cfg->timer_bit;
>  
>  	if (!cfg) {
>  		dev_err(&p->pdev->dev, "missing platform data\n");
> @@ -487,7 +555,7 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
>  static int sh_tmu_probe(struct platform_device *pdev)
>  {
>  	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
> -	struct sh_timer_config *cfg = pdev->dev.platform_data;
> +	struct sh_timer_config *cfg;
>  	int ret;
>  
>  	if (!is_early_platform_device(pdev)) {
> @@ -495,6 +563,11 @@ static int sh_tmu_probe(struct platform_device *pdev)
>  		pm_runtime_enable(&pdev->dev);
>  	}
>  
> +	if (pdev->dev.of_node)
> +		cfg = sh_tmu_parse_dt(&pdev->dev);
> +	else
> +		cfg = pdev->dev.platform_data;
> +
>  	if (p) {
>  		dev_info(&pdev->dev, "kept as earlytimer\n");
>  		goto out;
> @@ -506,7 +579,7 @@ static int sh_tmu_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  	}
>  
> -	ret = sh_tmu_setup(p, pdev);
> +	ret = sh_tmu_setup(p, pdev, cfg);
>  	if (ret) {
>  		kfree(p);
>  		platform_set_drvdata(pdev, NULL);
> @@ -535,6 +608,7 @@ static struct platform_driver sh_tmu_device_driver = {
>  	.remove		= sh_tmu_remove,
>  	.driver		= {
>  		.name	= "sh_tmu",
> +		.of_match_table = of_sh_tmu_match,
>  	}
>  };
>  
> -- 
> 1.7.9.5
> 


From horms at verge.net.au  Wed May 22 21:39:30 2013
From: horms at verge.net.au (Simon Horman)
Date: Thu, 23 May 2013 10:39:30 +0900
Subject: [RFC/PATCH v2 1/2] gpio-rcar: Make the platform data gpio_base
 field signed
In-Reply-To: <1369136406-23800-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369136406-23800-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <20130523013930.GH22608@verge.net.au>

On Tue, May 21, 2013 at 01:40:05PM +0200, Laurent Pinchart wrote:
> The gpio_base field is used to specify the desired GPIO base for the
> GPIO controller. The GPIO core can automatically allocate a GPIO number
> range when the base is set to -1. To make this possible, make the field
> signed.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Thanks, this is queued-up for v3.11 in the gpio-rcar branch.

> ---
>  include/linux/platform_data/gpio-rcar.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
> index cc472f6..fb2c718 100644
> --- a/include/linux/platform_data/gpio-rcar.h
> +++ b/include/linux/platform_data/gpio-rcar.h
> @@ -17,7 +17,7 @@
>  #define __GPIO_RCAR_H__
>  
>  struct gpio_rcar_config {
> -	unsigned int gpio_base;
> +	int gpio_base;
>  	unsigned int irq_base;
>  	unsigned int number_of_pins;
>  	const char *pctl_name;
> -- 
> 1.8.1.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From tony at atomide.com  Wed May 22 22:06:43 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 22 May 2013 19:06:43 -0700
Subject: [PATCH v2 1/3] ARM: allow platforms to use generic headers
 without ARCH_MULTIPLATFORM
In-Reply-To: <519B9FE7.3030907@arm.com>
References: <1368530845-7415-1-git-send-email-jonathan.austin@arm.com>
 <1368530845-7415-2-git-send-email-jonathan.austin@arm.com>
 <5192532B.1070705@gmail.com> <20130515233335.GO5600@atomide.com>
 <519B9FE7.3030907@arm.com>
Message-ID: <20130523020643.GB13507@atomide.com>

* Jonathan Austin <jonathan.austin at arm.com> [130521 09:30]:
> Hi Tony,
> 
> On 16/05/13 00:33, Tony Lindgren wrote:
> >* Rob Herring <robherring2 at gmail.com> [130514 08:12]:
> >>On 05/14/2013 06:27 AM, Jonathan Austin wrote:
> >>>Currently the use of generic mach headers is only is controlled by the same
> >>>config option as selection of a multiplatform kernel (i.e.
> >>>ARCH_MULTIPLATFORM). However, there are cases where it is valid to use the
> >>>generic headers but still build a single platform kernel.
> >>>
> >>>One such example is when using the vexpress platform with a core that does
> >>>not have an MMU; a multiplatform kernel does not make sense, but use of the
> >>>generic headers is required by the vexpress platform since 617276307cd4c
> >>>("ARM: vexpress: convert to multi-platform").
> >>>
> >>>This patch untangles these two options by introducing a new
> >>>ARM_GENERIC_HEADERS config option that ARCH_MULTIPLATFORM selects. Other
> >>>platforms can now select ARM_GENERIC_HEADERS independently.
> >>
> >>I find this name confusing. It is no headers you are selecting and
> >>generic is a bit overused IMHO. So how about something like
> >>NEED_NO_MACH_HEADERS to somewhat align to the other header related
> >>config options (e.g. NEED_MACH_GPIO_H).
> >
> >Hmm it _looks_ like this won't allow the drivers again to
> >#include <plat/*.h> and <mach/*.h>. Have you checked that?
> >
> >It might be worth checking as we really don't want to go back there
> >again.. Currently arch/arm/Makefile has:
> >
> >ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
> >ifeq ($(KBUILD_SRC),)
> >KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
> >else
> >KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
> >endif
> >endif
> >
> >So you may need to do something there to prevent drivers from again
> >including machdirs and platdirs.
> >
> If I've understood you correctly, then this patch already deals with
> this case (though it isn't hugely obvious from the diff...) by
> replacing CONFIG_ARCH_MULTIPLATFORM in your example above with
> CONFIG_ARM_GENERIC_HEADERS (soon to be renamed, as per Rob's
> suggestion).
> 
> Because ARCH_MULTIPLATFORM selects
> CONFIG_(FORMERLY_KNOWN_AS_)ARM_GENERIC_HEADERS it shouldn't be
> possible for anything multi-platform to start including <plat/*.h>
> and <mach/*.h> again.
> 
> This seems to be the right thing to do because it also makes it
> impossible to include <plat/*.h> and <mach/*.h> in !MULTIPLATFORM
> situations that don't need mach/plat headers, like the
> VEXPRESS_NOMMU case.
> 
> Is that what you were getting at? Please let me know if not...

Yes that's exactly what I was worried about as it was a bit hard to
see from the patch. Thanks for checking it.

Regards,

Tony 



From shawn.guo at linaro.org  Wed May 22 22:13:04 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 May 2013 10:13:04 +0800
Subject: [PATCH] ARM: imx: imx_v6_v7_defconfig: Select CONFIG_DRM_IMX_TVE
In-Reply-To: <1369058397-25071-1-git-send-email-fabio.estevam@freescale.com>
References: <1369058397-25071-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20130523021302.GA2704@S2101-09.ap.freescale.net>

On Mon, May 20, 2013 at 10:59:57AM -0300, Fabio Estevam wrote:
> Let the mx53 TVE driver be built by default.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

> ---
>  arch/arm/configs/imx_v6_v7_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index 6ec010f..a50d9af 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -208,6 +208,7 @@ CONFIG_IMX_SDMA=y
>  CONFIG_MXS_DMA=y
>  CONFIG_STAGING=y
>  CONFIG_DRM_IMX=y
> +CONFIG_DRM_IMX_TVE=y
>  CONFIG_DRM_IMX_IPUV3_CORE=y
>  CONFIG_DRM_IMX_IPUV3=y
>  CONFIG_COMMON_CLK_DEBUG=y
> -- 
> 1.8.1.2
> 
> 



From b32955 at freescale.com  Wed May 22 22:17:16 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 10:17:16 +0800
Subject: [PATCH 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <201305221459.34859.arnd@arndb.de>
References: <1369039742-10893-1-git-send-email-b32955@freescale.com>
 <20130521054323.GE3080@S2101-09.ap.freescale.net>
 <519C7ED3.3030004@freescale.com> <201305221459.34859.arnd@arndb.de>
Message-ID: <519D7C2C.9080506@freescale.com>

? 2013?05?22? 20:59, Arnd Bergmann ??:
> On Wednesday 22 May 2013, Huang Shijie wrote:
>> ? 2013?05?21? 13:43, Shawn Guo ??:
>>> It seems we can find it out from "reg" property, so that we can save
>>> this property?
>>>
>> we may have several devices attaching to the weim, each device has its 
>> own CS index.
>> it's better to keep this property, make it more clear.
> I agree with Shawn, we should not have this property when it is the
> same as the upper half of the "reg" property.
okay. I will remove this property.

thanks
Huang Shijie




From voice.shen at atmel.com  Wed May 22 22:23:27 2013
From: voice.shen at atmel.com (Bo Shen)
Date: Thu, 23 May 2013 10:23:27 +0800
Subject: [PATCH 1/7] USB: gadget: atmel_usba: move global struct usba_ep
 usba_ep to struct usba_udc
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <519D7D9F.1070109@atmel.com>

Hi J,

On 5/21/2013 00:25, Jean-Christophe PLAGNIOL-VILLARD wrote:
> so we can have multiple usb gadget instance
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org

For this series, test OK on at91sam9m10g45ek and at91sam9x5ek board
Tested-by: Bo Shen <voice.shen at atmel.com>

PS: When do testing, we need build in or choose as module: "Device 
Drivers ---> Generic Target Core Mod (TCM) and ConfigFS infrastructure"

Best Regards,
Bo Shen


From dhobsong at igel.co.jp  Wed May 22 22:47:13 2013
From: dhobsong at igel.co.jp (Damian Hobson-Garcia)
Date: Thu, 23 May 2013 11:47:13 +0900
Subject: [PATCH v2 0/4] dma-mapping: Define dma_{alloc,free}_attrs() for
 all archs
In-Reply-To: <20130522094741.GE14322@arm.com>
References: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
 <519C2F5D.8000809@igel.co.jp> <20130522094741.GE14322@arm.com>
Message-ID: <519D8331.3060203@igel.co.jp>

Hi Catalin,
On 2013/05/22 18:47, Catalin Marinas wrote:
> On Wed, May 22, 2013 at 03:37:17AM +0100, Damian Hobson-Garcia wrote:
>> Hello,
>> On 2013/04/30 12:01, Damian Hobson-Garcia wrote:
>>> Most architectures that define CONFIG_HAVE_DMA=y, have implementations for
>>> both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
>>> not define CONFIG_HAVE_DMA also have both of these definitions provided by
>>> dma-mapping-broken.h.
> 
> BTW, shouldn't this be called CONFIG_HAVE_DMA_ATTRS?

CONFIG_HAVE_DMA_ATTRS is currently used to enable the functions to
set/get the DMA attribute values. Poking through the headers, it looks
like the struct dma_attrs is defined regardless of the
CONFIG_HAVE_DMA_ATTRS setting, so in that respect
we always seem to "have" DMA attributes (if we have DMA), but they may
not always be meaningful (ie. set to some value).

> 
>>> Provide a default definition for the archs that define CONFIG_HAVE_DMA=y,
>>> but have no implementation for dma_{alloc,free}_attrs(). 
>>>
>>> As I don't have hardware for any of these systems, the patches are only
>>> compile-tested where I could (arm64, s390) and untested for the archs
>>> where I couldn't find a readily available prebuilt cross-compiler (c6x, parisc).
>>
>>>  arch/arm64/include/asm/dma-mapping.h  |   17 +++++++++++------
>>>  arch/c6x/include/asm/dma-mapping.h    |    3 +++
>>>  arch/parisc/include/asm/dma-mapping.h |    3 +++
>>>  arch/s390/include/asm/dma-mapping.h   |   17 +++++++++++------
>>>  4 files changed, 28 insertions(+), 12 deletions(-)
>>>
>>
>> Since this series spans several architectures, what would be the best
>> way to have this patch series merged?
>> Should I resubmit each patch to the mailing list for each architecture
>> separately?
> 
> I'm happy to take the arm64 patch.
Very much appreciated.

> 
> Thanks.
> 
Damian
-- 
Damian Hobson-Garcia
IGEL Co.,Ltd
http://www.igel.co.jp


From shawn.guo at linaro.org  Wed May 22 22:51:01 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 May 2013 10:51:01 +0800
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
 <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
 <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>
Message-ID: <20130523025059.GB2704@S2101-09.ap.freescale.net>

On Wed, May 22, 2013 at 08:59:20AM +0000, Jin Zhengxiong-R64188 wrote:
> [Jason Jin-R64188] For the lpuart itself, I do not think it will have different version IP.

You can never tell in 5 or 10 years.  Also no major version doesn't
necessarily mean no minor updates or revise.

> The general name is sufficient and soc related name can introduce the minor difference. If the there are update version, we can name it lpuart2.0 or something like that.
> 

Yeah, if IP designers name it lpuart2.0, it surely works.  But from my
experience on IMX, hardware guys are not always properly updating IP
name.  Then the version 2.0 becomes a versioning given by software
people which is improper to be used in compatible string.

> For the compatible property itself, the ePAPR described it as:
> ---- 
> The compatible property value consists of one or more strings that define the specific programming model for the device. This list of strings should be used by a client program for device driver selection. The property value consists of a concatenated list of null terminated strings, from most specific to most general. 
> ----
> So for the IPs especially for the peripheral IPs, the compatible just used to select the driver for the device.

Not only select the driver but also the programing model implemented in
the driver.  Take a look at drivers/mmc/host/sdhci-esdhc-imx.c or
drivers/net/ethernet/freescale/fec_main.c, multiple compatible strings
select the same driver but the different programing model implemented in
the driver.

> It should not used to describe the version information.

Seriously?  The "version" equally means the compatibility here.  How can
a compatible string be not used to describe "version" - compatibility?

> If the version changed and the driver cannot be used for the device then another compatible strings should be used.
> 

If the IP gets a revise, the driver should be updated to support a new
programing model with a new compatible string.

> As I said, Another reason for the general strings used is the across platform issue, It's maybe reasonably to name the compatible strings as you recommended for the IPs share in the same SoC family. But for the IPs shared across platform, general name sound more reasonably to avoid the product line confusing. 
> 

Think about it from "compatibility" point of view.  It does not cause
confusion but just help understand the compatible history.  Saying the
same IP is reused on LS-1 SoC, I do not see a problem with putting the
following compatible into LS-1 <soc>.dtsi under UART node, to tell that
the UART block on LS-1 is completely compatible with the one used on
MVF600.

  compatible = "fsl,ls1-uart", "fsl,mvf600-uart";

> The compatible strings once named as you said for Power platform, but more general strings were used later as IPs shared for more SoCs.
> 

I think IMX device tree support is added more recently than Power.
Encoding SoC name in IP compatible string is a general practise for IMX
device tree bindings.

Shawn

> I was wondering what's kind of strings should be used for this kind of IPs across different platforms. I added Grant Likely for comments, Thanks.
> 
> Jason 
> 



From ming.lei at canonical.com  Wed May 22 22:47:30 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Thu, 23 May 2013 10:47:30 +0800
Subject: [RFC PATCH] ARM: mm: lazy cache flushing on non-mapped pages
In-Reply-To: <20130522144240.GA4173@localhost.cambridge.arm.com>
References: <1369223711-2995-1-git-send-email-ming.lei@canonical.com>
 <20130522144240.GA4173@localhost.cambridge.arm.com>
Message-ID: <CACVXFVMsWHf6t-P9Q3YbE3WyhAQX1pcmFLni7uGH3PxXt=R+eg@mail.gmail.com>

On Wed, May 22, 2013 at 10:42 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
>
> That's the meaning of mapping_mapped(), it doesn't tell whether the page
> has a user virtual address.

Yes, I mean pages only need to flush if they has been mapped, so we can
use page_mapped() to decide that.

>
>> This patch also uses page_mapcount() to decide if the page has been
>> mapped.
>
> Better use page_mapped() instead.

Good idea, will do it v1, :-)

Thanks,
--
Ming Lei


From festevam at gmail.com  Thu May 23 00:16:31 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 23 May 2013 01:16:31 -0300
Subject: [PATCH 2/2] ARM i.MX5: Add S/PDIF clocks
In-Reply-To: <1368798543-23285-2-git-send-email-p.zabel@pengutronix.de>
References: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>
 <1368798543-23285-2-git-send-email-p.zabel@pengutronix.de>
Message-ID: <CAOMZO5Dy_Tvzcs1QgBjBBvUxdqmFZ1tuVyrQ1nqaz7yL_rdadA@mail.gmail.com>

Hi Philipp,

On Fri, May 17, 2013 at 10:49 AM, Philipp Zabel <p.zabel at pengutronix.de> wrote:
> This patch adds the S/PDIF clocks for i.MX51 and i.MX53. Tested on i.MX53.

Do you also have the spdif driver part?

Regards,

Fabio Estevam


From andrew at lunn.ch  Thu May 23 01:53:06 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 23 May 2013 07:53:06 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522233108.01cb51f0@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <201305222240.05124.arnd@arndb.de> <20130522233108.01cb51f0@skate>
Message-ID: <20130523055306.GV26249@lunn.ch>

> > The new boot loaders will of course know that they are remapping the
> > registers, so they are also able to put the correct information into the
> > DT.
> 
> The thing that I believe you don't realize is that those new bootloaders
> are already shipping *today*. And they are not putting whatever
> "correct" information into the DT you believe they should be putting.
> 
> So what do we do, today, with those new bootloaders, that are not the
> future, but the present. Again, they do *not* add any information in
> the DT that allows us to know that they have remapped the registers to
> 0xf1.

That is a key point. Compared to the kernel, the bootloaders a very
slow to evolve new features, even slower to get deployed, and have a
very long life without ever getting upgraded. The kernel has to deal
with legacy bootloaders.

What we seem to be heading towards is a bootloader which actually uses
the DT itself, can modify it dynamically to reflect the running system,
and pass it to the kernel.

What we have today, on Marvell boards, is mostly no support for DT at
all with blobs appended to the kernel with tools like debians
flash-kernel. Maybe this new Marvell uboot can load the blob in the
same way it can load the kernel, or initrd, from flash, a file on a
disk, tftpboot, etc, but i expect it is just an opaque binary blob to
uboot.

I guess your bootloader which will put the correct information into
the DT is a few years away.

    Andrew


From avinashphilip at ti.com  Thu May 23 02:27:09 2013
From: avinashphilip at ti.com (Philip, Avinash)
Date: Thu, 23 May 2013 06:27:09 +0000
Subject: [PATCH 02/11] gpio: davinci: coding style correction
In-Reply-To: <20130522144042.GG18614@n2100.arm.linux.org.uk>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-3-git-send-email-avinashphilip@ti.com>
 <20130522144042.GG18614@n2100.arm.linux.org.uk>
Message-ID: <518397C60809E147AF5323E0420B992E3EAC7AE8@DBDE04.ent.ti.com>

On Wed, May 22, 2013 at 20:10:42, Russell King - ARM Linux wrote:
> On Wed, May 22, 2013 at 12:40:25PM +0530, Philip Avinash wrote:
> >  /*
> >   * Assuming the pin is muxed as a gpio output, set its output value.
> >   */
> > -static void
> > -davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
> > +static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
> > +		int value)
> 
> This kind of stuff is just churn.  If you read Documentation/CodingStyle:
> 
> Statements longer than 80 columns will be broken into sensible chunks, unless
> exceeding 80 columns significantly increases readability and does not hide
> information. Descendants are always substantially shorter than the parent and
> are placed substantially to the right. The same applies to function headers
> with a long argument list. However, never break user-visible strings such as
> printk messages, because that breaks the ability to grep for them.
> 
> "broken into sensible chunks".  Here's the question: is the former a
> sensible format?  Arguably it is because it results in all the arguments
> fitting on one line at the expense of missing the return value.
> 
> The latter is also a sensible format - but breaks the arguments instead
> of the return value.
> 
> Both formats can be found in their entirety by grep by function name alone:
> 
> 	grep -1 davinci_gpio_set
> 
> or if you prefer to type some more then you end up with more specific
> 
> 	grep -A1 davinci_gpio_set
> or
> 	grep -B1 davinci_gpio_set
> 
> depending on the version.
> 
> Where there's no clear advantage one way or the other, let the authors
> preference stand.

Ok I understood and I will remove these changes in next version.

Thanks
Avinash

> 



From avinashphilip at ti.com  Thu May 23 02:27:08 2013
From: avinashphilip at ti.com (Philip, Avinash)
Date: Thu, 23 May 2013 06:27:08 +0000
Subject: [PATCH 02/11] gpio: davinci: coding style correction
In-Reply-To: <519CC142.7050301@cogentembedded.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-3-git-send-email-avinashphilip@ti.com>
 <519CC142.7050301@cogentembedded.com>
Message-ID: <518397C60809E147AF5323E0420B992E3EAC7AE3@DBDE04.ent.ti.com>

On Wed, May 22, 2013 at 18:29:46, Sergei Shtylyov wrote:
> Hello.
> 
> On 22-05-2013 11:10, Philip Avinash wrote:
> 
> > 1. Corrects coding and commenting styles
> > 2. Variables name change to meaningful name
> > 3. Remove unnecessary variable usage
> > 4. Add BINTEN macro definition
> >
> > Signed-off-by: Philip Avinash <avinashphilip at ti.com>
> > ---
> >   drivers/gpio/gpio-davinci.c |  182 +++++++++++++++++++++----------------------
> >   1 file changed, 89 insertions(+), 93 deletions(-)
> 
> > diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
> > index 17df6db..d308955 100644
> > --- a/drivers/gpio/gpio-davinci.c
> > +++ b/drivers/gpio/gpio-davinci.c
> [...]
> > @@ -31,10 +31,11 @@ struct davinci_gpio_regs {
> >   	u32	intstat;
> >   };
> >
> > +#define BINTEN	0x08 /* GPIO Interrupt Per-Bank Enable Register */
> 
>     Empty line needed here.

Ok, I will add.

> 
> >   #define chip2controller(chip)	\
> >   	container_of(chip, struct davinci_gpio_controller, chip)
> >
> [...]
> > @@ -98,8 +94,8 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
> >   	return __davinci_direction(chip, offset, false, 0);
> >   }
> >
> > -static int
> > -davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
> > +static int davinci_direction_out(struct gpio_chip *chip, unsigned offset,
> > +		int value)
> 
>      This line should be aligned under the next character after (.

Will remove this change as Russel pointed out.

> 
> [...]
> > @@ -113,22 +109,22 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
> [...]
> >   /*
> >    * Assuming the pin is muxed as a gpio output, set its output value.
> >    */
> > -static void
> > -davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
> > +static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset,
> > +		int value)
> 
>      Same here.

I will remove this change as Russel pointed out.

> 
> [...]
> > @@ -368,16 +363,16 @@ static int __init davinci_gpio_irq_setup(void)
> [...]
> >   	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
> > -		chips[bank].chip.to_irq = gpio_to_irq_banked;
> > -		chips[bank].irq_base = soc_info->gpio_unbanked
> > -			? -EINVAL
> > -			: (soc_info->intc_irq_num + gpio);
> > +		ctlrs[bank].chip.to_irq = gpio_to_irq_banked;
> > +		ctlrs[bank].irq_base = soc_info->gpio_unbanked ?
> > +			-EINVAL : (soc_info->intc_irq_num + gpio);
> 
>     () not needed here.

Ok will remove in next version ().

Thanks
Avinash

> 
> WBR, Sergei
> 
> 



From thomas.petazzoni at free-electrons.com  Thu May 23 02:35:09 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 08:35:09 +0200
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <20130523001353.GH31625@1wt.eu>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523001353.GH31625@1wt.eu>
Message-ID: <20130523083509.79297513@skate>

Dear Willy Tarreau,

On Thu, 23 May 2013 02:13:53 +0200, Willy Tarreau wrote:

> > You'll find in this patch series 4 small patches that make various
> > improvements to the Marvell PCIe driver.
> (...)
> 
> FWIW, these patches applied on top of your pcie-v10 tree have made
> my mini-pcie dual-nic appear for the first time on the mirabox. Till
> now I never knew if it was a hardware or software issue since the NIC
> does not appear in u-boot nor lspci, whatever the kernel versions,
> including the original Marvell one's. The NIC has two functions (one
> per controller) and no bridge, so it may be a side effect of your
> improvements (or maybe you fixed a bug).

Hum, interesting. Can you show the output of lspci -v and lspci -t
(which a pciutils version of lspci, not Busybox one) ? I'm interested
in seeing the layout of the PCIe bus with such a device, to get a
better understanding.

> Anyway for me it's a great improvement !
> 
> I've not tried it on the OpenBlocks AX3 yet (it was not detected
> there previously). But I have good hopes.
> 
> For reference, the NIC is Jetway's ADMPEIDLA (intel i350-AM2).

Should I be taking this as a formal Tested-by from you? :-)

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From w at 1wt.eu  Thu May 23 02:52:59 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Thu, 23 May 2013 08:52:59 +0200
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <20130523083509.79297513@skate>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523001353.GH31625@1wt.eu> <20130523083509.79297513@skate>
Message-ID: <20130523065259.GK31625@1wt.eu>

On Thu, May 23, 2013 at 08:35:09AM +0200, Thomas Petazzoni wrote:
> > FWIW, these patches applied on top of your pcie-v10 tree have made
> > my mini-pcie dual-nic appear for the first time on the mirabox. Till
> > now I never knew if it was a hardware or software issue since the NIC
> > does not appear in u-boot nor lspci, whatever the kernel versions,
> > including the original Marvell one's. The NIC has two functions (one
> > per controller) and no bridge, so it may be a side effect of your
> > improvements (or maybe you fixed a bug).
> 
> Hum, interesting. Can you show the output of lspci -v and lspci -t
> (which a pciutils version of lspci, not Busybox one) ? I'm interested
> in seeing the layout of the PCIe bus with such a device, to get a
> better understanding.

(send privately in another thread).

> > Anyway for me it's a great improvement !
> > 
> > I've not tried it on the OpenBlocks AX3 yet (it was not detected
> > there previously). But I have good hopes.
> > 
> > For reference, the NIC is Jetway's ADMPEIDLA (intel i350-AM2).
> 
> Should I be taking this as a formal Tested-by from you? :-)

Yes, obviously, feel free to add this one :

  Tested-by: Willy Tarreau <w at 1wt.eu>

Willy



From lee.jones at linaro.org  Thu May 23 03:09:05 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 May 2013 08:09:05 +0100
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130522174516.GT1627@sirena.org.uk>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
 <20130522165353.GB18714@gmail.com>
 <20130522174516.GT1627@sirena.org.uk>
Message-ID: <20130523070905.GD18714@gmail.com>

On Wed, 22 May 2013, Mark Brown wrote:

> On Wed, May 22, 2013 at 05:53:53PM +0100, Lee Jones wrote:
> > On Wed, 22 May 2013, Mark Brown wrote:
> 
> > > running or not, the worst that should happen is that the state can be
> > > read back.  I'd therefore expect the fix here to be in the board side
> > > code that enables the regulators.
> 
> > It's both.
> 
> > From the platform side we have stopped passing the external regulator
> > driver's constraints for Snowball:
> 
> > https://lkml.org/lkml/2013/5/22/280
> 
> > All I've done here is stop the ext driver from crapping out with the
> > misleading error "Configuration error: size mismatch", because a)
> > it's not an error, it's expected and b) It's not a size mismatch,
> > instead we have chosen to keep the constraints back in the Snowball
> > (and u8505) case.
> 
> OK, so the regulator driver is buggy and insisting on having constraints
> passed in for every regulator then?

If that's not how it's meant to work then, yes.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From jbe at pengutronix.de  Thu May 23 03:20:17 2013
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 23 May 2013 09:20:17 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <201305221305.09579.marex@denx.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <201305221219.43558.jbe@pengutronix.de> <201305221305.09579.marex@denx.de>
Message-ID: <201305230920.18200.jbe@pengutronix.de>

Hi Marek,

Marek Vasut wrote:
> > > i2c slowness is a different issue.
> >
> > Same happens here for my i.M23 based platform. It seems the PIO mode does
> > not work, or at least not like it works on a i.MX28. Each short transfer
> > needs about one second (without an error message) but does not send
> > anything on the I2C lines.
> >
> > I need the following patches to make I2C master work within a 3.10-rc2
> > kernel:
> >
> > Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C
>
> I'm all for it, but then ... won't it be better if you actually fixed the
> PIO and mixed-mode on MX23 instead of implementing such hack?

If the PIO mode or my patch is a hack depends on the point of view: Lucas told 
me the PIO mode is *mentioned* but *not specified* in the i.MX23/i.MX28 
datasheets.
So, the PIO mode seems to depend on some undocumented status bits in the 
i.MX28 I2C controller implementation.

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-5121-206917-5128 |
Peiner Str. 6-8, 31137 Hildesheim, Germany    | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |


From ard.biesheuvel at linaro.org  Thu May 23 03:28:24 2013
From: ard.biesheuvel at linaro.org (Ard Biesheuvel)
Date: Thu, 23 May 2013 09:28:24 +0200
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
Message-ID: <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>

In order to use the NEON/VFP unit in the kernel, we should
initialize it a bit earlier in the boot process so NEON users
that like to do a quick benchmark at load time (like the
xor_blocks or RAID-6 code) find the NEON/VFP unit already
enabled.

Replaced late_initcall() with core_initcall().

Signed-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
---
 arch/arm/vfp/vfpmodule.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index ab1eeae..e5413c3 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -770,4 +770,4 @@ static int __init vfp_init(void)
 	return 0;
 }
 
-late_initcall(vfp_init);
+core_initcall(vfp_init);
-- 
1.8.1.2



From ard.biesheuvel at linaro.org  Thu May 23 03:28:23 2013
From: ard.biesheuvel at linaro.org (Ard Biesheuvel)
Date: Thu, 23 May 2013 09:28:23 +0200
Subject: [PATCH 1/2] ARM: add support for kernel mode NEON/VFP
Message-ID: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>

In order to safely support the use of NEON or VFP instructions in
kernel mode, some precautions need to be taken:
- the userland context that may be present in the registers (even
  if the NEON/VFP is currently disabled) must be stored under the
  correct task (which may not be 'current' in the UP case),
- to avoid having to keep track of additional vfpstates for the
  kernel side, disallow the use of NEON/VFP in interrupt context
  and run with preemption disabled,
- after use, re-enable preemption and re-enable the lazy restore
  machinery by disabling the NEON/VFP unit.

This patch adds the functions kernel_vfp_begin() and kernel_vfp_end()
which take care of the above.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
---
 arch/arm/include/asm/vfp.h |  5 +++++
 arch/arm/vfp/vfpmodule.c   | 39 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
index f4ab34f..a488876 100644
--- a/arch/arm/include/asm/vfp.h
+++ b/arch/arm/include/asm/vfp.h
@@ -82,3 +82,8 @@
 #define VFPOPDESC_UNUSED_BIT	(24)
 #define VFPOPDESC_UNUSED_MASK	(0xFF << VFPOPDESC_UNUSED_BIT)
 #define VFPOPDESC_OPDESC_MASK	(~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
+
+#ifndef __ASSEMBLY__
+void kernel_vfp_begin(void);
+void kernel_vfp_end(void);
+#endif
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 5dfbb0b..ab1eeae 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/uaccess.h>
 #include <linux/user.h>
+#include <linux/export.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -649,6 +650,44 @@ static int vfp_hotplug(struct notifier_block *b, unsigned long action,
 }
 
 /*
+ * Kernel-side NEON/VFP support functions
+ */
+void kernel_vfp_begin(void)
+{
+	struct thread_info *thread = current_thread_info();
+	unsigned int cpu;
+	u32 fpexc;
+
+	/* Avoid using the NEON/VFP in interrupt context */
+	might_sleep();
+	cpu = get_cpu();
+
+	fpexc = fmrx(FPEXC) | FPEXC_EN;
+	fmxr(FPEXC, fpexc);
+
+	/*
+	 * Save the userland NEON/VFP state. Under UP, the owner could be a task
+	 * other than 'current'
+	 */
+	if (vfp_state_in_hw(cpu, thread))
+		vfp_save_state(&thread->vfpstate, fpexc);
+#ifndef CONFIG_SMP
+	else if (vfp_current_hw_state[cpu] != NULL)
+		vfp_save_state(vfp_current_hw_state[cpu], fpexc);
+#endif
+	vfp_current_hw_state[cpu] = NULL;
+}
+EXPORT_SYMBOL(kernel_vfp_begin);
+
+void kernel_vfp_end(void)
+{
+	/* Disable the NEON/VFP unit. */
+	fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
+	put_cpu();
+}
+EXPORT_SYMBOL(kernel_vfp_end);
+
+/*
  * VFP support code initialisation.
  */
 static int __init vfp_init(void)
-- 
1.8.1.2



From linux at arm.linux.org.uk  Thu May 23 03:53:04 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 08:53:04 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130522233108.01cb51f0@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <201305222240.05124.arnd@arndb.de> <20130522233108.01cb51f0@skate>
Message-ID: <20130523075304.GH18614@n2100.arm.linux.org.uk>

On Wed, May 22, 2013 at 11:31:08PM +0200, Thomas Petazzoni wrote:
> Dear Arnd Bergmann,
> 
> The thing that I believe you don't realize is that those new bootloaders
> are already shipping *today*. And they are not putting whatever
> "correct" information into the DT you believe they should be putting.

Well, if they're not putting addresses of registers into the DT, then
that DT information is surely pretty much useless to the kernel - or
anything.

If it's putting _wrong_ addresses in the DT, then the same thing applies.

Either way, it says "you need to change the DT blob passed to the kernel."

Luckily, as has already been agreed, DT blobs will not be hard-coded into
boot loaders, so that's easily sorted - you just tell people in the
installation instructions "if you have X versions of the boot loader, you
need to use DT blob X, otherwise you need to use blob Y."

>From what you're saying, that's the best that can be done - the kernel
can't do much else.

I'd also hasten to point out that even if we could detect the base of the
registers, with DT, what matters is what's in the DT blob itself, which
should override any detection.  So the DT blob would need to be updated
in any case.


From linus.walleij at linaro.org  Thu May 23 03:56:46 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 May 2013 09:56:46 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
Message-ID: <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>

On Fri, May 17, 2013 at 3:35 PM, Oliver Schinagl
<oliver+list at schinagl.nl> wrote:

(...)
> While initially these fuses are used to somewhat determin the chipID, these
> appear to be writeable by the user and thus can be used for other purpouses.
> For example storing a 128 bit root key, a unique serial number, which could
> then even be used as a MAC address.
(...)
Then follows some code to read out the keys from sysfs I guess..
> +static int __init sid_probe(struct platform_device *pdev)

It's really simple to actually make the kernel use this to seed the
entropy pool.

#include <linux/random.h>
add_device_randomness(u8 *, num);

If you know after probe that you can read out a number of bytes
of device-unique data, I think you should add those bytes to the
entropy pool like this.

Yours,
Linus Walleij


From gang.chen at asianux.com  Thu May 23 03:57:35 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Thu, 23 May 2013 15:57:35 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always need
 it.
Message-ID: <519DCBEF.3090208@asianux.com>


The crazy user can unset 'CONFIG_BUG' in menuconfig: "> General setup >
Configure standard kernel features (expert users) > BUG() Support".

But in fact, we always need it, and quite a few of architectures have
already implemented it (e.g. alpha, arc, arm, avr32, blackfin, cris,
frv, ia64, m68k, mips, mn10300, parisc, powerpc, s390, sh, sparc, x86).

And kernel also already has prepared a default effective implementation
for the architectures which is unwilling to implement it by themselves
(e.g. arm64, c6x, h8300, hexagon, m32r, metag, microblaze, openrisc,
score, tile, um, unicore32, xtensa).

So need get rid of 'CONFIG_BUG', and let it always enabled everywhere.


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm/Kconfig          |    1 -
 arch/avr32/Kconfig        |    1 -
 arch/blackfin/Kconfig     |    1 -
 arch/h8300/Kconfig        |    1 -
 arch/hexagon/Kconfig      |    1 -
 arch/parisc/Kconfig       |    2 --
 arch/powerpc/Kconfig      |    1 -
 arch/s390/Kconfig         |    2 +-
 arch/sh/Kconfig           |    2 +-
 arch/um/Kconfig.common    |    1 -
 arch/x86/Kconfig          |    1 -
 include/asm-generic/bug.h |   29 -----------------------------
 init/Kconfig              |   10 ----------
 lib/Kconfig.debug         |    2 +-
 14 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a7fc5ea..ea4a146 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -265,7 +265,6 @@ config PHYS_OFFSET
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 source "init/Kconfig"
 
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index bdc3558..7c9005a 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -55,7 +55,6 @@ config GENERIC_CALIBRATE_DELAY
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 source "init/Kconfig"
 
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index a117652..637dc42 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -47,7 +47,6 @@ config GENERIC_CSUM
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 config ZONE_DMA
 	def_bool y
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 303e4f9..88848da 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -56,7 +56,6 @@ config GENERIC_CALIBRATE_DELAY
 
 config GENERIC_BUG
         bool
-        depends on BUG
 
 config TIME_LOW_RES
 	bool
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 33a9792..f50cc8f 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -84,7 +84,6 @@ config STACKTRACE_SUPPORT
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 menu "Machine selection"
 
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 6507dab..5de1f8c 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -10,7 +10,6 @@ config PARISC
 	select RTC_CLASS
 	select RTC_DRV_GENERIC
 	select INIT_ALL_POSSIBLE
-	select BUG
 	select HAVE_PERF_EVENTS
 	select GENERIC_ATOMIC64 if !64BIT
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -62,7 +61,6 @@ config ARCH_HAS_ILOG2_U64
 config GENERIC_BUG
 	bool
 	default y
-	depends on BUG
 
 config GENERIC_HWEIGHT
 	bool
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c33e3ad..34f4ca9 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -187,7 +187,6 @@ config AUDIT_ARCH
 config GENERIC_BUG
 	bool
 	default y
-	depends on BUG
 
 config SYS_SUPPORTS_APM_EMULATION
 	default y if PMAC_APM_EMU
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index da183c5..5d7b3db 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -29,7 +29,7 @@ config GENERIC_HWEIGHT
 	def_bool y
 
 config GENERIC_BUG
-	def_bool y if BUG
+	def_bool y
 
 config GENERIC_BUG_RELATIVE_POINTERS
 	def_bool y
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8c868cf..d555e7f 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -84,7 +84,7 @@ config RWSEM_XCHGADD_ALGORITHM
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG && SUPERH32
+	depends on SUPERH32
 
 config GENERIC_CSUM
 	def_bool y
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index bceee66..7aae42a 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -53,7 +53,6 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_BUG
 	bool
 	default y
-	depends on BUG
 
 config HZ
 	int
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 723e42e..a36e1b4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -166,7 +166,6 @@ config GENERIC_ISA_DMA
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 	select GENERIC_BUG_RELATIVE_POINTERS if X86_64
 
 config GENERIC_BUG_RELATIVE_POINTERS
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..5d50903 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -12,8 +12,6 @@
 #ifndef __ASSEMBLY__
 #include <linux/kernel.h>
 
-#ifdef CONFIG_BUG
-
 #ifdef CONFIG_GENERIC_BUG
 struct bug_entry {
 #ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
@@ -106,33 +104,6 @@ extern void warn_slowpath_null(const char *file, const int line);
 	unlikely(__ret_warn_on);					\
 })
 
-#else /* !CONFIG_BUG */
-#ifndef HAVE_ARCH_BUG
-#define BUG() do {} while(0)
-#endif
-
-#ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
-#endif
-
-#ifndef HAVE_ARCH_WARN_ON
-#define WARN_ON(condition) ({						\
-	int __ret_warn_on = !!(condition);				\
-	unlikely(__ret_warn_on);					\
-})
-#endif
-
-#ifndef WARN
-#define WARN(condition, format...) ({					\
-	int __ret_warn_on = !!(condition);				\
-	unlikely(__ret_warn_on);					\
-})
-#endif
-
-#define WARN_TAINT(condition, taint, format...) WARN_ON(condition)
-
-#endif
-
 #define WARN_ON_ONCE(condition)	({				\
 	static bool __section(.data.unlikely) __warned;		\
 	int __ret_warn_once = !!(condition);			\
diff --git a/init/Kconfig b/init/Kconfig
index 7fb26a6..bc1dd49 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1360,16 +1360,6 @@ config PRINTK
 	  very difficult to diagnose system problems, saying N here is
 	  strongly discouraged.
 
-config BUG
-	bool "BUG() support" if EXPERT
-	default y
-	help
-          Disabling this option eliminates support for BUG and WARN, reducing
-          the size of your kernel image and potentially quietly ignoring
-          numerous fatal conditions. You should only consider disabling this
-          option for embedded systems with no facilities for reporting errors.
-          Just say Y.
-
 config ELF_CORE
 	depends on COREDUMP
 	default y
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 566cf2b..54b3251 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -700,7 +700,7 @@ config HAVE_DEBUG_BUGVERBOSE
 
 config DEBUG_BUGVERBOSE
 	bool "Verbose BUG() reporting (adds 70K)" if DEBUG_KERNEL && EXPERT
-	depends on BUG && (GENERIC_BUG || HAVE_DEBUG_BUGVERBOSE)
+	depends on GENERIC_BUG || HAVE_DEBUG_BUGVERBOSE
 	default y
 	help
 	  Say Y here to make BUG() panics output the file name and line number
-- 
1.7.7.6


From oliver+list at schinagl.nl  Thu May 23 04:10:17 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Thu, 23 May 2013 10:10:17 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>
Message-ID: <519DCEE9.6070208@schinagl.nl>

On 05/23/13 09:56, Linus Walleij wrote:
> On Fri, May 17, 2013 at 3:35 PM, Oliver Schinagl
> <oliver+list at schinagl.nl> wrote:
>
> (...)
>> While initially these fuses are used to somewhat determin the chipID, these
>> appear to be writeable by the user and thus can be used for other purpouses.
>> For example storing a 128 bit root key, a unique serial number, which could
>> then even be used as a MAC address.
> (...)
> Then follows some code to read out the keys from sysfs I guess..
>> +static int __init sid_probe(struct platform_device *pdev)
>
> It's really simple to actually make the kernel use this to seed the
> entropy pool.
>
> #include <linux/random.h>
> add_device_randomness(u8 *, num);
>
> If you know after probe that you can read out a number of bytes
> of device-unique data, I think you should add those bytes to the
> entropy pool like this.
While that is a great idea, we can't guarantee device uniqueness. We've 
already seen some chips that where 'forgotten' to program and default 
set to all 0. I guess that doesn't have to be a bad thing.

Then, i'm not sure if the driver is the best for this to be loaded? 
Maxime, what do you think? Personally I would feel more in having this 
in the mach-sunxi/core.c bit, but then again, this is currently a module 
and wouldn't be useful to have there. Maxime is far more knowledgeable 
to answer that.

It should probably be noted, that the sunxi series have a hardware 
crypto engine, with hardware random seed generator, one for a later project.
>
> Yours,
> Linus Walleij
>



From jonas at microbit.se  Thu May 23 04:08:59 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Thu, 23 May 2013 10:08:59 +0200
Subject: imx53 cspi clock problem
In-Reply-To: <20130522164710.GE31135@pengutronix.de>
References: <519C6B3D.3030106@microbit.se>
 <20130522164710.GE31135@pengutronix.de>
Message-ID: <519DCE9B.2060909@microbit.se>

On 2013-05-22 18:47, Sascha Hauer wrote:
> On Wed, May 22, 2013 at 08:52:45AM +0200, Jonas Andersson wrote:
>> 	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
>> 	reg = <0x63fc0000 0x4000>;
>> 	interrupts = <38>;
>> 	clocks = <&clks 55>, <&clks 0>;
> Unlike the eCSPI controller the CSPI controller seems to have only one
> clock. This should probably be
>
> 	clocks = <&clks 55>, <&clks 55>;
>
This works fine.

Is it the right solution to define both clocks to the same in all the 
imx*.dtsi files? imx25.dtsi defines only one clock "ipg" so 
spi_imx_probe() will probably fail.

Jonas


From vincent.guittot at linaro.org  Thu May 23 04:11:34 2013
From: vincent.guittot at linaro.org (Vincent Guittot)
Date: Thu, 23 May 2013 10:11:34 +0200
Subject: [PATCH 09/14] sched: evaluate the activity level of the system
In-Reply-To: <20130522165035.GC4935@e103034-lin>
References: <1366910611-20048-1-git-send-email-vincent.guittot@linaro.org>
 <1366910611-20048-10-git-send-email-vincent.guittot@linaro.org>
 <20130522165035.GC4935@e103034-lin>
Message-ID: <CAKfTPtDTO+u5Cj_oMM1AVBbp0yYJCgZqP1vkA+=+iHw_0taw0w@mail.gmail.com>

On 22 May 2013 18:50, Morten Rasmussen <morten.rasmussen at arm.com> wrote:
> On Thu, Apr 25, 2013 at 06:23:25PM +0100, Vincent Guittot wrote:
>> We evaluate the activity level of CPUs, groups and domains in order to define
>> how many CPUs are required to handle the current activity.
>>
>> Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
>> ---
>>  kernel/sched/fair.c |   19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
>> index 954adfd..234ecdd 100644
>> --- a/kernel/sched/fair.c
>> +++ b/kernel/sched/fair.c
>> @@ -3465,7 +3465,22 @@ static int check_pack_buddy(int cpu, struct task_struct *p)
>>               return true;
>>
>>       return false;
>> +}
>> +
>> +static int get_cpu_activity(int cpu)
>> +{
>> +     struct rq *rq = cpu_rq(cpu);
>> +     u32 sum = rq->avg.runnable_avg_sum;
>> +     u32 period = rq->avg.runnable_avg_period;
>> +
>> +     sum = min(sum, period);
>> +
>> +     if (sum == period) {
>> +             u32 overload = rq->nr_running > 1 ? 1 : 0;
>> +             return power_of(cpu) + overload;
>> +     }
>
> Adding one to indicate cpu overload seems to work well in the cases that
> I can think of. It may take some time to have effect if the overloaded
> cpu is in a group with nearly overloaded cpus. Adding one won't enable
> more cpus in another group until they have all reached overload.

This output expresses the activity of the CPU and i don't want to hack
it unnecessarily.  The +1 is only used to make difference between a
cpu fully loaded by 1 task and a cpu which need help of other cpus
because it is fully loaded by several tasks which share the runtime of
 the cpu.

When we define how many cpus are needed for the packing effort, we can
take some margins like the is_buddy_full function.

>
> Reaching sum == period takes quite a long time. Would it be an idea to
> use sum*1024 >= period*1000 like you do in is_buddy_full()?

We could probably use this margin when we update the list of cpus that
are involved in the packing effort

Thanks for the comments
Vincent

>
> I think that would be more consistent since overloaded is essential the
> same as full.
>
> Cheers,
> Morten
>
>>
>> +     return (sum * power_of(cpu)) / period;
>>  }
>>
>>  /*
>> @@ -4355,6 +4370,7 @@ struct sd_lb_stats {
>>       struct sched_group *busiest; /* Busiest group in this sd */
>>       struct sched_group *this;  /* Local group in this sd */
>>       unsigned long total_load;  /* Total load of all groups in sd */
>> +     unsigned long total_activity;  /* Total activity of all groups in sd */
>>       unsigned long total_pwr;   /*   Total power of all groups in sd */
>>       unsigned long avg_load;    /* Average load across all groups in sd */
>>
>> @@ -4383,6 +4399,7 @@ struct sd_lb_stats {
>>  struct sg_lb_stats {
>>       unsigned long avg_load; /*Avg load across the CPUs of the group */
>>       unsigned long group_load; /* Total load over the CPUs of the group */
>> +     unsigned long group_activity; /* Total activity of the group */
>>       unsigned long sum_nr_running; /* Nr tasks running in the group */
>>       unsigned long sum_weighted_load; /* Weighted load of group's tasks */
>>       unsigned long group_capacity;
>> @@ -4629,6 +4646,7 @@ static inline void update_sg_lb_stats(struct lb_env *env,
>>               }
>>
>>               sgs->group_load += load;
>> +             sgs->group_activity += get_cpu_activity(i);
>>               sgs->sum_nr_running += nr_running;
>>               sgs->sum_weighted_load += weighted_cpuload(i);
>>               if (idle_cpu(i))
>> @@ -4752,6 +4770,7 @@ static inline void update_sd_lb_stats(struct lb_env *env,
>>                       return;
>>
>>               sds->total_load += sgs.group_load;
>> +             sds->total_activity += sgs.group_activity;
>>               sds->total_pwr += sg->sgp->power;
>>
>>               /*
>> --
>> 1.7.9.5
>>
>>
>


From p.zabel at pengutronix.de  Thu May 23 04:13:23 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Thu, 23 May 2013 10:13:23 +0200
Subject: [PATCH 2/2] ARM i.MX5: Add S/PDIF clocks
In-Reply-To: <CAOMZO5Dy_Tvzcs1QgBjBBvUxdqmFZ1tuVyrQ1nqaz7yL_rdadA@mail.gmail.com>
References: <1368798543-23285-1-git-send-email-p.zabel@pengutronix.de>
 <1368798543-23285-2-git-send-email-p.zabel@pengutronix.de>
 <CAOMZO5Dy_Tvzcs1QgBjBBvUxdqmFZ1tuVyrQ1nqaz7yL_rdadA@mail.gmail.com>
Message-ID: <1369296803.4109.12.camel@pizza.hi.pengutronix.de>

Hi Fabio,

Am Donnerstag, den 23.05.2013, 01:16 -0300 schrieb Fabio Estevam:
> Hi Philipp,
> 
> On Fri, May 17, 2013 at 10:49 AM, Philipp Zabel <p.zabel at pengutronix.de> wrote:
> > This patch adds the S/PDIF clocks for i.MX51 and i.MX53. Tested on i.MX53.
> 
> Do you also have the spdif driver part?

Yes, work in progress. I'll put you on Cc: when I post them.

regards
Philipp



From linus.walleij at linaro.org  Thu May 23 04:20:09 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 May 2013 10:20:09 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <519DCEE9.6070208@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>
 <519DCEE9.6070208@schinagl.nl>
Message-ID: <CACRpkdZveQsVpw7_FnecGNZX4nVwWMtVwme7JEcy1R7uvdEe8A@mail.gmail.com>

On Thu, May 23, 2013 at 10:10 AM, Oliver Schinagl
<oliver+list at schinagl.nl> wrote:
> On 05/23/13 09:56, Linus Walleij wrote:
>>
>> On Fri, May 17, 2013 at 3:35 PM, Oliver Schinagl
>> <oliver+list at schinagl.nl> wrote:
>>
>> (...)
>>>
>>> While initially these fuses are used to somewhat determin the chipID,
>>> these
>>> appear to be writeable by the user and thus can be used for other
>>> purpouses.
>>> For example storing a 128 bit root key, a unique serial number, which
>>> could
>>> then even be used as a MAC address.
>>
>> (...)
>> Then follows some code to read out the keys from sysfs I guess..
>>>
>>> +static int __init sid_probe(struct platform_device *pdev)
>>
>>
>> It's really simple to actually make the kernel use this to seed the
>> entropy pool.
>>
>> #include <linux/random.h>
>> add_device_randomness(u8 *, num);
>>
>> If you know after probe that you can read out a number of bytes
>> of device-unique data, I think you should add those bytes to the
>> entropy pool like this.
>
> While that is a great idea, we can't guarantee device uniqueness. We've
> already seen some chips that where 'forgotten' to program and default set to
> all 0. I guess that doesn't have to be a bad thing.

Ted can confirm but AFAIK that is not a problem. This device-unique
numer is just one of the things mixed into the pool, if it's on some
devices just an array of zeroes it does not make things worse, but
in the cases when there is some uniqueness in it make things better.

> It should probably be noted, that the sunxi series have a hardware crypto
> engine, with hardware random seed generator, one for a later project.

That will anyway be augmented with the contents of the entropy
pool rather than returned to random clients right off if I know the
recent changes to random code right.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 23 04:23:43 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 May 2013 10:23:43 +0200
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <201305221608.10759.arnd@arndb.de>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdYHiwbGonH80aJfHxP6F+hLb+_KdCr_g5ae1Yr-v=WcxA@mail.gmail.com>
 <201305221608.10759.arnd@arndb.de>
Message-ID: <CACRpkdacteTbFkOQ9w3LQCwN+RDviK04j77itz7uyTiY56+nCg@mail.gmail.com>

On Wed, May 22, 2013 at 4:08 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 22 May 2013, Linus Walleij wrote:
>> > diff --git a/drivers/regulator/ab8500-ext.c b/drivers/regulator/ab8500-ext.c
>> > index b4d4547..8421537 100644
>> > --- a/drivers/regulator/ab8500-ext.c
>> > +++ b/drivers/regulator/ab8500-ext.c
>> > @@ -334,6 +334,12 @@ int ab8500_ext_regulator_init(struct platform_device *pdev)
>> >                 return -EINVAL;
>> >         }
>> >
>> > +       /* have any external regulators been specified? */
>> > +       if (pdata->num_ext_regulator == 0) {
>> > +               dev_warn(&pdev->dev, "Not using external regulators\n");
>> > +               return 0;
>> > +       }
>>
>> dev_warn() is really when we warn about something really nasty, worse
>> than dev_err(). It seems dev_info() is more apropriate.
>
> Are you confusing it with dev_crit()?
>
> This is how the levels are defined, and "warning" is less urgent than "error":

Yeah :-/

But I still think this should be just dev_info().

No big deal though.

Yours,
Linus Walleij


From s.hauer at pengutronix.de  Thu May 23 04:33:23 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 23 May 2013 10:33:23 +0200
Subject: imx53 cspi clock problem
In-Reply-To: <519DCE9B.2060909@microbit.se>
References: <519C6B3D.3030106@microbit.se>
 <20130522164710.GE31135@pengutronix.de>
 <519DCE9B.2060909@microbit.se>
Message-ID: <20130523083323.GE32299@pengutronix.de>

On Thu, May 23, 2013 at 10:08:59AM +0200, Jonas Andersson wrote:
> On 2013-05-22 18:47, Sascha Hauer wrote:
> >On Wed, May 22, 2013 at 08:52:45AM +0200, Jonas Andersson wrote:
> >>	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
> >>	reg = <0x63fc0000 0x4000>;
> >>	interrupts = <38>;
> >>	clocks = <&clks 55>, <&clks 0>;
> >Unlike the eCSPI controller the CSPI controller seems to have only one
> >clock. This should probably be
> >
> >	clocks = <&clks 55>, <&clks 55>;
> >
> This works fine.
> 
> Is it the right solution to define both clocks to the same in all
> the imx*.dtsi files? imx25.dtsi defines only one clock "ipg" so
> spi_imx_probe() will probably fail.

Yes, they should all be fixed that way. Care to send a patch?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From b32955 at freescale.com  Thu May 23 04:16:15 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:15 +0800
Subject: [PATCH V2 3/6] ARM: dts: imx6qdl: add more information for WEIM
In-Reply-To: <1369296978-7669-1-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
Message-ID: <1369296978-7669-4-git-send-email-b32955@freescale.com>

Add the clock and compatible information for the weim.
Also adds the weim label.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461c..f21d259 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -744,9 +744,11 @@
 				reg = <0x021b4000 0x4000>;
 			};
 
-			weim at 021b8000 {
+			weim: weim at 021b8000 {
+				compatible = "fsl,imx6q-weim";
 				reg = <0x021b8000 0x4000>;
 				interrupts = <0 14 0x04>;
+				clocks = <&clks 196>;
 			};
 
 			ocotp at 021bc000 {
-- 
1.7.1




From b32955 at freescale.com  Thu May 23 04:16:17 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:17 +0800
Subject: [PATCH V2 5/6] ARM: dts: imx6dl: add a pinctrl for WEIM NOR
In-Reply-To: <1369296978-7669-1-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
Message-ID: <1369296978-7669-6-git-send-email-b32955@freescale.com>

Add a new pinctrl for WEIN NOR.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   55 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 4b13454..4c8f838 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -183,6 +183,61 @@
 					};
 				};
 
+				weim {
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+							MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+
+							/* data */
+							MX6DL_PAD_EIM_D16__EIM_DATA16 0xb0b1
+							MX6DL_PAD_EIM_D17__EIM_DATA17 0xb0b1
+							MX6DL_PAD_EIM_D18__EIM_DATA18 0xb0b1
+							MX6DL_PAD_EIM_D19__EIM_DATA19 0xb0b1
+							MX6DL_PAD_EIM_D20__EIM_DATA20 0xb0b1
+							MX6DL_PAD_EIM_D21__EIM_DATA21 0xb0b1
+							MX6DL_PAD_EIM_D22__EIM_DATA22 0xb0b1
+							MX6DL_PAD_EIM_D23__EIM_DATA23 0xb0b1
+							MX6DL_PAD_EIM_D24__EIM_DATA24 0xb0b1
+							MX6DL_PAD_EIM_D25__EIM_DATA25 0xb0b1
+							MX6DL_PAD_EIM_D26__EIM_DATA26 0xb0b1
+							MX6DL_PAD_EIM_D27__EIM_DATA27 0xb0b1
+							MX6DL_PAD_EIM_D28__EIM_DATA28 0xb0b1
+							MX6DL_PAD_EIM_D29__EIM_DATA29 0xb0b1
+							MX6DL_PAD_EIM_D30__EIM_DATA30 0xb0b1
+							MX6DL_PAD_EIM_D31__EIM_DATA31 0xb0b1
+
+							/* address */
+							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 
 			};
 
-- 
1.7.1




From b32955 at freescale.com  Thu May 23 04:16:13 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:13 +0800
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369296978-7669-1-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
Message-ID: <1369296978-7669-2-git-send-email-b32955@freescale.com>

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.

This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  146 ++++++++++++++++++++
 4 files changed, 206 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c

diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644
index 0000000..3db588e
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -0,0 +1,50 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+
+The term "wireless" does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+
+The actual devices are instantiated from the child nodes of a WEIM node.
+
+Required properties:
+
+ - compatible:		Should be set to "fsl,imx6q-weim"
+ - reg:			A resource specifier for the register space
+			(see the example below)
+ - interrupts:		the interrupt number, see the example below.
+ - clocks:		the clock, see the example below.
+ - #address-cells:	Must be set to 2 to allow memory address translation
+ - #size-cells:		Must be set to 1 to allow CS address passing
+ - ranges:		Must be set up to reflect the memory layout with four
+			integer values for each chip-select line in use:
+
+			   <cs-number> 0 <physical address of mapping> <size>
+
+Timing property for child nodes. It is mandatory, not optional.
+
+ - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
+			child node. We can get the CS index from the child
+			node's "reg" property.
+
+Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
+
+	weim: weim at 021b8000 {
+		compatible = "fsl,imx6q-weim";
+		reg = <0x021b8000 0x4000>;
+		interrupts = <0 14 0x04>;
+		clocks = <&clks 196>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0x08000000 0x08000000>;
+
+		nor at 0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x02000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+
+			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
+					0x0000C000 0x1404a38e 0x00000000>;
+		};
+	};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab..488702b 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,15 @@
 
 menu "Bus devices"
 
+config IMX_WEIM
+	tristate "Freescale EIM DRIVER"
+	depends on ARCH_MXC
+	help
+	  Driver for i.MX6 WEIM controller.
+	  The WEIM(Wireless External Interface Module) works like a bus.
+	  You can attach many different devices on it, such as NOR, onenand.
+	  But now, we only support the Parallel NOR.
+
 config MVEBU_MBUS
 	bool
 	depends on PLAT_ORION
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c..436bbcc 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
new file mode 100644
index 0000000..b932add
--- /dev/null
+++ b/drivers/bus/imx-weim.c
@@ -0,0 +1,146 @@
+/*
+ * EIM driver for Freescale's i.MX chips
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+
+struct imx_weim {
+	void __iomem *base;
+	struct clk *clk;
+};
+
+static const struct of_device_id weim_id_table[] = {
+	{ .compatible = "fsl,imx6q-weim", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, weim_id_table);
+
+#define CS_TIMING_LEN 6
+#define CS_REG_RANGE  0x18
+
+/* Parse and set the timing for this device. */
+static int
+weim_timing_setup(struct platform_device *pdev, struct device_node *np)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+	u32 value[CS_TIMING_LEN];
+	u32 cs_idx;
+	int ret;
+	int i;
+
+	/* get the CS index from this child node's "reg" property. */
+	ret = of_property_read_u32(np, "reg", &cs_idx);
+	if (ret)
+		return ret;
+
+	/* The weim has four chip selects. */
+	if (cs_idx > 3)
+		return -EINVAL;
+
+	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
+					value, CS_TIMING_LEN);
+	if (ret)
+		return ret;
+
+	/* set the timing for WEIM */
+	for (i = 0; i < CS_TIMING_LEN; i++)
+		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
+	return 0;
+}
+
+static int weim_parse_dt(struct platform_device *pdev)
+{
+	struct device_node *child;
+	int ret;
+
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		if (!child->name)
+			continue;
+
+		ret = weim_timing_setup(pdev, child);
+		if (ret)
+			goto parse_fail;
+
+		if (!of_platform_device_create(child, NULL, &pdev->dev)) {
+			ret = -EINVAL;
+			goto parse_fail;
+		}
+
+	}
+	return 0;
+
+parse_fail:
+	return ret;
+}
+
+static int weim_probe(struct platform_device *pdev)
+{
+	struct imx_weim *weim;
+	struct resource *res;
+	int ret = -EINVAL;
+
+	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
+	if (!weim) {
+		ret = -ENOMEM;
+		goto weim_err;
+	}
+	platform_set_drvdata(pdev, weim);
+
+	/* get the resource */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	weim->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(weim->base)) {
+		ret = PTR_ERR(weim->base);
+		goto weim_err;
+	}
+
+	/* get the clock */
+	weim->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(weim->clk))
+		goto weim_err;
+
+	clk_prepare_enable(weim->clk);
+
+	/* parse the device node */
+	ret = weim_parse_dt(pdev);
+	if (ret) {
+		clk_disable_unprepare(weim->clk);
+		goto weim_err;
+	}
+
+	dev_info(&pdev->dev, "WEIM driver registered.\n");
+	return 0;
+
+weim_err:
+	return ret;
+}
+
+static int weim_remove(struct platform_device *pdev)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(weim->clk);
+	return 0;
+}
+
+static struct platform_driver weim_driver = {
+	.driver = {
+		.name = "imx-weim",
+		.of_match_table = weim_id_table,
+	},
+	.probe   = weim_probe,
+	.remove  = weim_remove,
+};
+
+module_platform_driver(weim_driver);
+MODULE_AUTHOR("Freescale Semiconductor Inc.");
+MODULE_DESCRIPTION("i.MX EIM Controller Driver");
+MODULE_LICENSE("GPL");
-- 
1.7.1




From b32955 at freescale.com  Thu May 23 04:16:12 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:12 +0800
Subject: [PATCH V2 0/6] ARM: imx6q{dl}: add the WEIM driver
Message-ID: <1369296978-7669-1-git-send-email-b32955@freescale.com>

This patch set adds a new driver for WEIM in the imx6q{dl}-sabreauto boards.

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, only the NOR is connected to WEIM.

v1 --> v2:
	[0] remove used PADs.
	[1] fix the wrong pad values, (thanks Alison Chaiken)
	[2] remove the weim-cs-index.
	[3] add "fsl" for the weim-cs-timing.
	[4] remove the partitions info in the document.
	[5] rewrite the drivers(follow Sascha and Shawn's comments)

Huang Shijie (6):
  drivers: bus: add a new driver for WEIM
  ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
  ARM: dts: imx6qdl: add more information for WEIM
  ARM: dts: imx6q: add pinctrl for WEIM NOR
  ARM: dts: imx6dl: add a pinctrl for WEIM NOR
  ARM: dts: imx6qdl: enable the WEIM NOR

 Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
 arch/arm/boot/dts/imx6dl-sabreauto.dts             |    9 +-
 arch/arm/boot/dts/imx6dl.dtsi                      |   55 ++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts              |    9 +-
 arch/arm/boot/dts/imx6q.dtsi                       |   56 ++++++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |   22 +++-
 arch/arm/boot/dts/imx6qdl.dtsi                     |    4 +-
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  146 ++++++++++++++++++++
 10 files changed, 357 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c




From b32955 at freescale.com  Thu May 23 04:16:16 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:16 +0800
Subject: [PATCH V2 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
In-Reply-To: <1369296978-7669-1-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
Message-ID: <1369296978-7669-5-git-send-email-b32955@freescale.com>

Add a pinctrl for WEIM nor.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   56 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..2a6327a 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -323,6 +323,62 @@
 						>;
 					};
 				};
+
+				weim {
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+
+							/* data */
+							MX6Q_PAD_EIM_D16__EIM_DATA16 0xb0b1
+							MX6Q_PAD_EIM_D17__EIM_DATA17 0xb0b1
+							MX6Q_PAD_EIM_D18__EIM_DATA18 0xb0b1
+							MX6Q_PAD_EIM_D19__EIM_DATA19 0xb0b1
+							MX6Q_PAD_EIM_D20__EIM_DATA20 0xb0b1
+							MX6Q_PAD_EIM_D21__EIM_DATA21 0xb0b1
+							MX6Q_PAD_EIM_D22__EIM_DATA22 0xb0b1
+							MX6Q_PAD_EIM_D23__EIM_DATA23 0xb0b1
+							MX6Q_PAD_EIM_D24__EIM_DATA24 0xb0b1
+							MX6Q_PAD_EIM_D25__EIM_DATA25 0xb0b1
+							MX6Q_PAD_EIM_D26__EIM_DATA26 0xb0b1
+							MX6Q_PAD_EIM_D27__EIM_DATA27 0xb0b1
+							MX6Q_PAD_EIM_D28__EIM_DATA28 0xb0b1
+							MX6Q_PAD_EIM_D29__EIM_DATA29 0xb0b1
+							MX6Q_PAD_EIM_D30__EIM_DATA30 0xb0b1
+							MX6Q_PAD_EIM_D31__EIM_DATA31 0xb0b1
+
+							/* address */
+							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 			};
 		};
 
-- 
1.7.1




From b32955 at freescale.com  Thu May 23 04:16:14 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:14 +0800
Subject: [PATCH V2 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between SPI
 and WEIM
In-Reply-To: <1369296978-7669-1-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
Message-ID: <1369296978-7669-3-git-send-email-b32955@freescale.com>

In the imx6q-sabreauto and imx6dl-sabreauto boards,
the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
it is used as a data pin for the WEIM NOR.

In order to fix the conflict, this patch removes the pin from the hog,
and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto.

The SPI NOR selects this pinctrl_ecspi1_sabreauto when it is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl-sabreauto.dts   |    9 ++++++++-
 arch/arm/boot/dts/imx6q-sabreauto.dts    |    9 ++++++++-
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    2 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 60f3038..95da711 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -25,7 +25,14 @@
 			fsl,pins = <
 				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+			fsl,pins = <
+				MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 9fb3e99..09a7580 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -29,7 +29,14 @@
 			fsl,pins = <
 				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+			fsl,pins = <
+				MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d6baa51..a4466e6 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -20,7 +20,7 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio3 19 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
 	status = "disabled"; /* pin conflict with WEIM NOR */
 
 	flash: m25p80 at 0 {
-- 
1.7.1




From b32955 at freescale.com  Thu May 23 04:16:18 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 16:16:18 +0800
Subject: [PATCH V2 6/6] ARM: dts: imx6qdl: enable the WEIM NOR
In-Reply-To: <1369296978-7669-1-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
Message-ID: <1369296978-7669-7-git-send-email-b32955@freescale.com>

Enable the WEIM NOR for imx6q{dl} boards.

For the pin conflict with SPI NOR, its status is set to "disabled".

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index a4466e6..684b208 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -58,3 +58,23 @@
 	wp-gpios = <&gpio1 13 0>;
 	status = "okay";
 };
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	status = "disabled"; /* pin conflict with SPI NOR */
+
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+
+		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
+				0x0000C000 0x1404a38e 0x00000000>;
+	};
+};
-- 
1.7.1




From jhovold at gmail.com  Thu May 23 04:38:50 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Thu, 23 May 2013 10:38:50 +0200
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
Message-ID: <1369298335-24597-1-git-send-email-jhovold@gmail.com>

This is an update of the shadow-interrupt-mask series against v3.10-rc2.

I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
affected. If not, then some probing mechanism as the one Doug suggested
could be implemented on top of (a subset of) these patches. What do you
say, Nicolas?

Note that the first patch (adding a missing OF compile guard) could be
applied straight away.

Thanks,
Johan


v3:
 - rebase against v3.10-rc2
 - remove some comments

v2:
 - rebase on top of DT-support patch by Joachim Eastwood
 - add missing brace in DT-id table


Johan Hovold (5):
  rtc-at91rm9200: add match-table compile guard
  rtc-at91rm9200: add configuration support
  rtc-at91rm9200: refactor interrupt-register handling
  rtc-at91rm9200: add shadow interrupt mask
  rtc-at91rm9200: use shadow IMR on at91sam9x5

 .../bindings/rtc/atmel,at91rm9200-rtc.txt          |   2 +-
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   2 +-
 drivers/rtc/rtc-at91rm9200.c                       | 131 +++++++++++++++++----
 3 files changed, 113 insertions(+), 22 deletions(-)

-- 
1.8.2.1



From jhovold at gmail.com  Thu May 23 04:38:53 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Thu, 23 May 2013 10:38:53 +0200
Subject: [PATCH v3 3/5] rtc-at91rm9200: refactor interrupt-register handling
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <1369298335-24597-4-git-send-email-jhovold@gmail.com>

Add accessors for the interrupt register.

This will allow us to easily add a shadow interrupt-mask register to
use on SoCs where the interrupt-mask register cannot be used.

Signed-off-by: Johan Hovold <jhovold at gmail.com>
---
 drivers/rtc/rtc-at91rm9200.c | 43 +++++++++++++++++++++++++++++--------------
 1 file changed, 29 insertions(+), 14 deletions(-)

diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index ab2024b..9592d08 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -51,6 +51,21 @@ static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
 
+static void at91_rtc_write_ier(u32 mask)
+{
+	at91_rtc_write(AT91_RTC_IER, mask);
+}
+
+static void at91_rtc_write_idr(u32 mask)
+{
+	at91_rtc_write(AT91_RTC_IDR, mask);
+}
+
+static u32 at91_rtc_read_imr(void)
+{
+	return at91_rtc_read(AT91_RTC_IMR);
+}
+
 /*
  * Decode time/date into rtc_time structure
  */
@@ -114,9 +129,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
 	cr = at91_rtc_read(AT91_RTC_CR);
 	at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 
-	at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
+	at91_rtc_write_ier(AT91_RTC_ACKUPD);
 	wait_for_completion(&at91_rtc_updated);	/* wait for ACKUPD interrupt */
-	at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
+	at91_rtc_write_idr(AT91_RTC_ACKUPD);
 
 	at91_rtc_write(AT91_RTC_TIMR,
 			  bin2bcd(tm->tm_sec) << 0
@@ -148,7 +163,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
 	tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
 	tm->tm_year = at91_alarm_year - 1900;
 
-	alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM)
+	alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
 			? 1 : 0;
 
 	dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -173,7 +188,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 	tm.tm_min = alrm->time.tm_min;
 	tm.tm_sec = alrm->time.tm_sec;
 
-	at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+	at91_rtc_write_idr(AT91_RTC_ALARM);
 	at91_rtc_write(AT91_RTC_TIMALR,
 		  bin2bcd(tm.tm_sec) << 0
 		| bin2bcd(tm.tm_min) << 8
@@ -186,7 +201,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 
 	if (alrm->enabled) {
 		at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-		at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+		at91_rtc_write_ier(AT91_RTC_ALARM);
 	}
 
 	dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -202,9 +217,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 
 	if (enabled) {
 		at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-		at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+		at91_rtc_write_ier(AT91_RTC_ALARM);
 	} else
-		at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+		at91_rtc_write_idr(AT91_RTC_ALARM);
 
 	return 0;
 }
@@ -213,7 +228,7 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  */
 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
 {
-	unsigned long imr = at91_rtc_read(AT91_RTC_IMR);
+	unsigned long imr = at91_rtc_read_imr();
 
 	seq_printf(seq, "update_IRQ\t: %s\n",
 			(imr & AT91_RTC_ACKUPD) ? "yes" : "no");
@@ -233,7 +248,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
 	unsigned int rtsr;
 	unsigned long events = 0;
 
-	rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR);
+	rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
 	if (rtsr) {		/* this interrupt is shared!  Is it ours? */
 		if (rtsr & AT91_RTC_ALARM)
 			events |= (RTC_AF | RTC_IRQF);
@@ -328,7 +343,7 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
 	at91_rtc_write(AT91_RTC_MR, 0);		/* 24 hour mode */
 
 	/* Disable all interrupts */
-	at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+	at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
 					AT91_RTC_SECEV | AT91_RTC_TIMEV |
 					AT91_RTC_CALEV);
 
@@ -373,7 +388,7 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
 	struct rtc_device *rtc = platform_get_drvdata(pdev);
 
 	/* Disable all interrupts */
-	at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+	at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
 					AT91_RTC_SECEV | AT91_RTC_TIMEV |
 					AT91_RTC_CALEV);
 	free_irq(irq, pdev);
@@ -396,13 +411,13 @@ static int at91_rtc_suspend(struct device *dev)
 	/* this IRQ is shared with DBGU and other hardware which isn't
 	 * necessarily doing PM like we are...
 	 */
-	at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR)
+	at91_rtc_imr = at91_rtc_read_imr()
 			& (AT91_RTC_ALARM|AT91_RTC_SECEV);
 	if (at91_rtc_imr) {
 		if (device_may_wakeup(dev))
 			enable_irq_wake(irq);
 		else
-			at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr);
+			at91_rtc_write_idr(at91_rtc_imr);
 	}
 	return 0;
 }
@@ -413,7 +428,7 @@ static int at91_rtc_resume(struct device *dev)
 		if (device_may_wakeup(dev))
 			disable_irq_wake(irq);
 		else
-			at91_rtc_write(AT91_RTC_IER, at91_rtc_imr);
+			at91_rtc_write_ier(at91_rtc_imr);
 	}
 	return 0;
 }
-- 
1.8.2.1



From jhovold at gmail.com  Thu May 23 04:38:52 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Thu, 23 May 2013 10:38:52 +0200
Subject: [PATCH v3 2/5] rtc-at91rm9200: add configuration support
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <1369298335-24597-3-git-send-email-jhovold@gmail.com>

Add configuration support which can be used to implement SoC-specific
workarounds for broken hardware.

Signed-off-by: Johan Hovold <jhovold at gmail.com>
---
 drivers/rtc/rtc-at91rm9200.c | 46 ++++++++++++++++++++++++++++++++++++--------
 1 file changed, 38 insertions(+), 8 deletions(-)

diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index eeeb73f..ab2024b 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -42,6 +42,10 @@
 
 #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
 
+struct at91_rtc_config {
+};
+
+static const struct at91_rtc_config *at91_rtc_config;
 static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
@@ -250,6 +254,36 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
 	return IRQ_NONE;		/* not handled */
 }
 
+static const struct at91_rtc_config at91rm9200_config = {
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id at91_rtc_dt_ids[] = {
+	{
+		.compatible = "atmel,at91rm9200-rtc",
+		.data = &at91rm9200_config,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
+#endif
+
+static const struct at91_rtc_config *
+at91_rtc_get_config(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+
+	if (pdev->dev.of_node) {
+		match = of_match_node(at91_rtc_dt_ids, pdev->dev.of_node);
+		if (!match)
+			return NULL;
+		return (const struct at91_rtc_config *)match->data;
+	}
+
+	return &at91rm9200_config;
+}
+
 static const struct rtc_class_ops at91_rtc_ops = {
 	.read_time	= at91_rtc_readtime,
 	.set_time	= at91_rtc_settime,
@@ -268,6 +302,10 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
 	struct resource *regs;
 	int ret = 0;
 
+	at91_rtc_config = at91_rtc_get_config(pdev);
+	if (!at91_rtc_config)
+		return -ENODEV;
+
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!regs) {
 		dev_err(&pdev->dev, "no mmio resource defined\n");
@@ -383,14 +421,6 @@ static int at91_rtc_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
 
-#ifdef CONFIG_OF
-static const struct of_device_id at91_rtc_dt_ids[] = {
-	{ .compatible = "atmel,at91rm9200-rtc" },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
-#endif
-
 static struct platform_driver at91_rtc_driver = {
 	.remove		= __exit_p(at91_rtc_remove),
 	.driver		= {
-- 
1.8.2.1



From jhovold at gmail.com  Thu May 23 04:38:51 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Thu, 23 May 2013 10:38:51 +0200
Subject: [PATCH v3 1/5] rtc-at91rm9200: add match-table compile guard
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <1369298335-24597-2-git-send-email-jhovold@gmail.com>

Add missing match-table compile guard.

Signed-off-by: Johan Hovold <jhovold at gmail.com>
---
 drivers/rtc/rtc-at91rm9200.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 0eab77b..eeeb73f 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -383,11 +383,13 @@ static int at91_rtc_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
 
+#ifdef CONFIG_OF
 static const struct of_device_id at91_rtc_dt_ids[] = {
 	{ .compatible = "atmel,at91rm9200-rtc" },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
+#endif
 
 static struct platform_driver at91_rtc_driver = {
 	.remove		= __exit_p(at91_rtc_remove),
-- 
1.8.2.1



From jhovold at gmail.com  Thu May 23 04:38:55 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Thu, 23 May 2013 10:38:55 +0200
Subject: [PATCH v3 5/5] rtc-at91rm9200: use shadow IMR on at91sam9x5
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <1369298335-24597-6-git-send-email-jhovold@gmail.com>

Add support for the at91sam9x5-family which must use the shadow
interrupt mask due to a hardware issue (causing RTC_IMR to always be
zero).

Signed-off-by: Johan Hovold <jhovold at gmail.com>
---
 Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 2 +-
 arch/arm/boot/dts/at91sam9x5.dtsi                              | 2 +-
 drivers/rtc/rtc-at91rm9200.c                                   | 7 +++++++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 2a3feab..34c1505 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,7 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..b5833d1f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -643,7 +643,7 @@
 			};
 
 			rtc at fffffeb0 {
-				compatible = "atmel,at91rm9200-rtc";
+				compatible = "atmel,at91sam9x5-rtc";
 				reg = <0xfffffeb0 0x40>;
 				interrupts = <1 4 7>;
 				status = "disabled";
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 205701e..47416e9 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -309,12 +309,19 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
 static const struct at91_rtc_config at91rm9200_config = {
 };
 
+static const struct at91_rtc_config at91sam9x5_config = {
+	.use_shadow_imr	= true,
+};
+
 #ifdef CONFIG_OF
 static const struct of_device_id at91_rtc_dt_ids[] = {
 	{
 		.compatible = "atmel,at91rm9200-rtc",
 		.data = &at91rm9200_config,
 	}, {
+		.compatible = "atmel,at91sam9x5-rtc",
+		.data = &at91sam9x5_config,
+	}, {
 		/* sentinel */
 	}
 };
-- 
1.8.2.1



From jhovold at gmail.com  Thu May 23 04:38:54 2013
From: jhovold at gmail.com (Johan Hovold)
Date: Thu, 23 May 2013 10:38:54 +0200
Subject: [PATCH v3 4/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <1369298335-24597-5-git-send-email-jhovold@gmail.com>

Add shadow interrupt-mask register which can be used on SoCs where the
actual hardware register is broken.

Note that some care needs to be taken to make sure the shadow mask
corresponds to the actual hardware state. The added overhead is not an
issue for the non-broken SoCs due to the relatively infrequent
interrupt-mask updates. We do, however, only use the shadow mask value
as a fall-back when it actually needed as there is still a theoretical
possibility that the mask is incorrect (see the code for details).

Signed-off-by: Johan Hovold <jhovold at gmail.com>
---
 drivers/rtc/rtc-at91rm9200.c | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 9592d08..205701e 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -30,6 +30,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/spinlock.h>
 
 #include <asm/uaccess.h>
 
@@ -43,6 +44,7 @@
 #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
 
 struct at91_rtc_config {
+	bool use_shadow_imr;
 };
 
 static const struct at91_rtc_config *at91_rtc_config;
@@ -50,20 +52,55 @@ static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
+static DEFINE_SPINLOCK(at91_rtc_lock);
+static u32 at91_rtc_shadow_imr;
 
 static void at91_rtc_write_ier(u32 mask)
 {
+	unsigned long flags;
+
+	spin_lock_irqsave(&at91_rtc_lock, flags);
+	at91_rtc_shadow_imr |= mask;
 	at91_rtc_write(AT91_RTC_IER, mask);
+	spin_unlock_irqrestore(&at91_rtc_lock, flags);
 }
 
 static void at91_rtc_write_idr(u32 mask)
 {
+	unsigned long flags;
+
+	spin_lock_irqsave(&at91_rtc_lock, flags);
 	at91_rtc_write(AT91_RTC_IDR, mask);
+	/*
+	 * Register read back (of any RTC-register) needed to make sure
+	 * IDR-register write has reached the peripheral before updating
+	 * shadow mask.
+	 *
+	 * Note that there is still a possibility that the mask is updated
+	 * before interrupts have actually been disabled in hardware. The only
+	 * way to be certain would be to poll the IMR-register, which is is
+	 * the very register we are trying to emulate. The register read back
+	 * is a reasonable heuristic.
+	 */
+	at91_rtc_read(AT91_RTC_SR);
+	at91_rtc_shadow_imr &= ~mask;
+	spin_unlock_irqrestore(&at91_rtc_lock, flags);
 }
 
 static u32 at91_rtc_read_imr(void)
 {
-	return at91_rtc_read(AT91_RTC_IMR);
+	unsigned long flags;
+	u32 mask;
+
+	if (at91_rtc_config->use_shadow_imr) {
+		spin_lock_irqsave(&at91_rtc_lock, flags);
+		mask = at91_rtc_shadow_imr;
+		spin_unlock_irqrestore(&at91_rtc_lock, flags);
+	} else {
+		mask = at91_rtc_read(AT91_RTC_IMR);
+	}
+
+	return mask;
 }
 
 /*
-- 
1.8.2.1



From linux at arm.linux.org.uk  Thu May 23 04:41:26 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 09:41:26 +0100
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
 <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
Message-ID: <20130523084126.GI18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 09:28:24AM +0200, Ard Biesheuvel wrote:
> In order to use the NEON/VFP unit in the kernel, we should
> initialize it a bit earlier in the boot process so NEON users
> that like to do a quick benchmark at load time (like the
> xor_blocks or RAID-6 code) find the NEON/VFP unit already
> enabled.

So what are the results of those benchmarks that the RAID-6 code does?

This isn't something which will get accepted without there being a very
strong case for it; firstly, we've always said "no FP in the kernel".
Secondly, it makes it too easy for people to start thinking that FP is
safe in the kernel.  It isn't - this will go horribly wrong if the VFP
hardware bounces an instruction to the support code.

Lastly, what happens if you sleep between kernel_vfp_start() and
kernel_vfp_end() ?  That's a context switch which will mess up your
VFP state.  I think you need to take a spinlock (not _bh nor _irqsave
versions) in here to ensure that people don't get the idea that they
_can_ sleep between these two.

So, good attempt, but I think you need to think about this more, and
also justify the need for it.


From jonas at microbit.se  Thu May 23 04:44:47 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Thu, 23 May 2013 10:44:47 +0200
Subject: imx53 cspi clock problem
In-Reply-To: <20130523083323.GE32299@pengutronix.de>
References: <519C6B3D.3030106@microbit.se>
 <20130522164710.GE31135@pengutronix.de> <519DCE9B.2060909@microbit.se>
 <20130523083323.GE32299@pengutronix.de>
Message-ID: <519DD6FF.9070405@microbit.se>

On 2013-05-23 10:33, Sascha Hauer wrote:
> Yes, they should all be fixed that way. Care to send a patch?
>
Yes i can send a patch.

Jonas



From shc_work at mail.ru  Thu May 23 04:46:46 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 12:46:46 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSCBWMiAxLzZdIGRyaXZlcnM6IGJ1czogYWRkIGEgbmV3IGRy?=
 =?UTF-8?B?aXZlciBmb3IgV0VJTQ==?=
In-Reply-To: <1369296978-7669-2-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-2-git-send-email-b32955@freescale.com>
Message-ID: <1369298806.527290461@f60.mail.ru>

> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
>  drivers/bus/Kconfig                                |    9 ++
>  drivers/bus/Makefile                               |    1 +
>  drivers/bus/imx-weim.c                             |  146 ++++++++++++++++++++
>  4 files changed, 206 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
>  create mode 100644 drivers/bus/imx-weim.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
> new file mode 100644
> index 0000000..3db588e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
> @@ -0,0 +1,50 @@
> +Device tree bindings for i.MX Wireless External Interface Module (WEIM)
> +
> +The term "wireless" does not imply that the WEIM is literally an interface
> +without wires. It simply means that this module was originally designed for
> +wireless and mobile applications that use low-power technology.
> +
> +The actual devices are instantiated from the child nodes of a WEIM node.
> +
> +Required properties:
> +
> + - compatible:		Should be set to "fsl,imx6q-weim"
> + - reg:			A resource specifier for the register space
> +			(see the example below)
> + - interrupts:		the interrupt number, see the example below.

Where interrupt is used in the driver?

> + - clocks:		the clock, see the example below.
> + - #address-cells:	Must be set to 2 to allow memory address translation
> + - #size-cells:		Must be set to 1 to allow CS address passing
> + - ranges:		Must be set up to reflect the memory layout with four
> +			integer values for each chip-select line in use:
> +
> +			   <cs-number> 0 <physical address of mapping> <size>
> +
> +Timing property for child nodes. It is mandatory, not optional.
> +
> + - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
> +			child node. We can get the CS index from the child
> +			node's "reg" property.
> +
> +Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
> +
> +	weim: weim at 021b8000 {
> +		compatible = "fsl,imx6q-weim";
> +		reg = <0x021b8000 0x4000>;
> +		interrupts = <0 14 0x04>;
> +		clocks = <&clks 196>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0x08000000 0x08000000>;
> +
> +		nor at 0,0 {
> +			compatible = "cfi-flash";
> +			reg = <0 0 0x02000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			bank-width = <2>;
> +
> +			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
> +					0x0000C000 0x1404a38e 0x00000000>;
> +		};
> +	};
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index b05ecab..488702b 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -4,6 +4,15 @@
>  
>  menu "Bus devices"
>  
> +config IMX_WEIM
> +	tristate "Freescale EIM DRIVER"
> +	depends on ARCH_MXC
> +	help
> +	  Driver for i.MX6 WEIM controller.
> +	  The WEIM(Wireless External Interface Module) works like a bus.
> +	  You can attach many different devices on it, such as NOR, onenand.
> +	  But now, we only support the Parallel NOR.
> +
>  config MVEBU_MBUS
>  	bool
>  	depends on PLAT_ORION
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index 3c7b53c..436bbcc 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -2,6 +2,7 @@
>  # Makefile for the bus drivers.
>  #
>  
> +obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
>  obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
>  obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
>  
> diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
> new file mode 100644
> index 0000000..b932add
> --- /dev/null
> +++ b/drivers/bus/imx-weim.c
> @@ -0,0 +1,146 @@
> +/*
> + * EIM driver for Freescale's i.MX chips
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +
> +struct imx_weim {
> +	void __iomem *base;
> +	struct clk *clk;
> +};
> +
> +static const struct of_device_id weim_id_table[] = {
> +	{ .compatible = "fsl,imx6q-weim", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, weim_id_table);
> +
> +#define CS_TIMING_LEN 6
> +#define CS_REG_RANGE  0x18
> +
> +/* Parse and set the timing for this device. */
> +static int
> +weim_timing_setup(struct platform_device *pdev, struct device_node *np)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +	u32 value[CS_TIMING_LEN];
> +	u32 cs_idx;
> +	int ret;
> +	int i;
> +
> +	/* get the CS index from this child node's "reg" property. */
> +	ret = of_property_read_u32(np, "reg", &cs_idx);
> +	if (ret)
> +		return ret;
> +
> +	/* The weim has four chip selects. */
> +	if (cs_idx > 3)
> +		return -EINVAL;
> +
> +	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
> +					value, CS_TIMING_LEN);
> +	if (ret)
> +		return ret;
> +
> +	/* set the timing for WEIM */
> +	for (i = 0; i < CS_TIMING_LEN; i++)
> +		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
> +	return 0;
> +}
> +
> +static int weim_parse_dt(struct platform_device *pdev)
> +{
> +	struct device_node *child;
> +	int ret;
> +
> +	for_each_child_of_node(pdev->dev.of_node, child) {
> +		if (!child->name)
> +			continue;
> +
> +		ret = weim_timing_setup(pdev, child);
> +		if (ret)
> +			goto parse_fail;
> +
> +		if (!of_platform_device_create(child, NULL, &pdev->dev)) {
> +			ret = -EINVAL;
> +			goto parse_fail;
> +		}
> +
> +	}
> +	return 0;
> +
> +parse_fail:
> +	return ret;
> +}
> +
> +static int weim_probe(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim;
> +	struct resource *res;
> +	int ret = -EINVAL;
> +
> +	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
> +	if (!weim) {
> +		ret = -ENOMEM;
> +		goto weim_err;
> +	}
> +	platform_set_drvdata(pdev, weim);
> +
> +	/* get the resource */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(weim->base)) {
> +		ret = PTR_ERR(weim->base);
> +		goto weim_err;
> +	}
> +
> +	/* get the clock */
> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(weim->clk))
> +		goto weim_err;
> +
> +	clk_prepare_enable(weim->clk);
> +
> +	/* parse the device node */
> +	ret = weim_parse_dt(pdev);
> +	if (ret) {
> +		clk_disable_unprepare(weim->clk);
> +		goto weim_err;
> +	}
> +
> +	dev_info(&pdev->dev, "WEIM driver registered.\n");
> +	return 0;
> +
> +weim_err:
> +	return ret;
> +}
> +
> +static int weim_remove(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(weim->clk);
> +	return 0;
> +}
> +
> +static struct platform_driver weim_driver = {
> +	.driver = {
> +		.name = "imx-weim",
> +		.of_match_table = weim_id_table,
> +	},
> +	.probe   = weim_probe,
> +	.remove  = weim_remove,
> +};
> +
> +module_platform_driver(weim_driver);
> +MODULE_AUTHOR("Freescale Semiconductor Inc.");
> +MODULE_DESCRIPTION("i.MX EIM Controller Driver");
> +MODULE_LICENSE("GPL");
> -- 

---

From geert at linux-m68k.org  Thu May 23 04:40:29 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 23 May 2013 10:40:29 +0200
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <519DCBEF.3090208@asianux.com>
References: <519DCBEF.3090208@asianux.com>
Message-ID: <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>

On Thu, May 23, 2013 at 9:57 AM, Chen Gang <gang.chen at asianux.com> wrote:
> The crazy user can unset 'CONFIG_BUG' in menuconfig: "> General setup >
> Configure standard kernel features (expert users) > BUG() Support".
>
> But in fact, we always need it, and quite a few of architectures have

Sorry, but we don't. I think you don't get the meaning of the BUG config symbol
(see below).

> already implemented it (e.g. alpha, arc, arm, avr32, blackfin, cris,
> frv, ia64, m68k, mips, mn10300, parisc, powerpc, s390, sh, sparc, x86).

What do you mean by "already implemented it"? E.g. on m68k, I can disable
or enable CONFIG_BUG. Both work.

> And kernel also already has prepared a default effective implementation
> for the architectures which is unwilling to implement it by themselves
> (e.g. arm64, c6x, h8300, hexagon, m32r, metag, microblaze, openrisc,
> score, tile, um, unicore32, xtensa).

This is not about providing an implementation or not...

> -config BUG
> -       bool "BUG() support" if EXPERT
> -       default y
> -       help
> -          Disabling this option eliminates support for BUG and WARN, reducing
> -          the size of your kernel image and potentially quietly ignoring
> -          numerous fatal conditions. You should only consider disabling this
> -          option for embedded systems with no facilities for reporting errors.
> -          Just say Y.

... It's about reducing memory size on devices where you can't show bug or
warning messages.

> So need get rid of 'CONFIG_BUG', and let it always enabled everywhere.

So please keep it.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From plagnioj at jcrosoft.com  Thu May 23 04:45:38 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 10:45:38 +0200
Subject: [PATCH 0/7 v4] ARM: at91: dt: add USBA support
In-Reply-To: <20130520162149.GC9937@game.jcrosoft.org>
References: <20130520162149.GC9937@game.jcrosoft.org>
Message-ID: <20130523084538.GE9937@game.jcrosoft.org>

Hi Felipe,

	if it's ok with you I send the patch series via at91
	with the DT

Best Regards,
J.
On 18:21 Mon 20 May     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> HI,
> 
> 	v4:
> 	fix multi instance support
> 
> 	v3:
> 	rebase againt 3.10-rc1 + dt macro cleanup
> 
> 	This patch serie finish to add the usb device support to dt for at91
> 	with the usba support present on the last at91 generation since sam9g45
> 
> The following changes since commit b3f442b0eedbc20b5ce3f4a96530588d14901199:
> 
>   ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)
> 
> are available in the git repository at:
> 
>   git://github.com/at91linux/linux-at91.git j/for-3.11-usba
> 
> for you to fetch changes up to 910026a08e2c2205953f2507cc11f4822998989b:
> 
>   ARM: at91: sam9m10g45ek add udc DT support (2013-05-20 23:52:17 +0800)
> 
> ----------------------------------------------------------------
> Jean-Christophe PLAGNIOL-VILLARD (7):
>       USB: gadget: atmel_usba: move global struct usba_ep usba_ep to struct usba_udc
>       USB: gadget: atmel_usba: allow multi instance
>       USB: gadget: atmel_usba: add DT support
>       ARM: at91: sam9x5 add udc DT support
>       ARM: at91: sam9x5ek add udc DT support
>       ARM: at91: sam9g45 add udc DT support
>       ARM: at91: sam9m10g45ek add udc DT support
> 
>  Documentation/devicetree/bindings/usb/atmel-usb.txt |   82 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9g45.dtsi                  |   62 +++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9m10g45ek.dts              |    5 ++
>  arch/arm/boot/dts/at91sam9x5.dtsi                   |   62 +++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9x5ek.dtsi                 |    5 ++
>  arch/arm/mach-at91/at91sam9g45.c                    |    2 +
>  arch/arm/mach-at91/at91sam9x5.c                     |    2 +
>  drivers/usb/gadget/Kconfig                          |    2 +-
>  drivers/usb/gadget/atmel_usba_udc.c                 |  264 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----------------------------
>  drivers/usb/gadget/atmel_usba_udc.h                 |    2 +
>  10 files changed, 407 insertions(+), 81 deletions(-)
> 
> Best Regards,
> J.
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From catalin.marinas at arm.com  Thu May 23 04:50:07 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 09:50:07 +0100
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic
 ldrd/strd instructions
In-Reply-To: <20130522180942.GK16361@mudshark.cambridge.arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <1368810473-26070-15-git-send-email-will.deacon@arm.com>
 <20130520141809.GA27473@arm.com>
 <CAL_JsqLSC2QgMdTGtH5G_F5SYjA3Hs--jMmxBES=fqGLwapptQ@mail.gmail.com>
 <20130522084744.GD14322@arm.com>
 <20130522180942.GK16361@mudshark.cambridge.arm.com>
Message-ID: <20130523085006.GA16722@arm.com>

On Wed, May 22, 2013 at 07:09:42PM +0100, Will Deacon wrote:
> On Wed, May 22, 2013 at 09:47:44AM +0100, Catalin Marinas wrote:
> > On Tue, May 21, 2013 at 07:48:35PM +0100, Rob Herring wrote:
> > > On Mon, May 20, 2013 at 9:18 AM, Catalin Marinas
> > > <catalin.marinas at arm.com> wrote:
> > > > On Fri, May 17, 2013 at 06:07:53PM +0100, Will Deacon wrote:
> > > >> CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
> > > >> userspace software can avoid having to use the exclusive variants of
> > > >> these instructions if they wish.
> > > >>
> > > >> This patch advertises the atomicity of these instructions via the
> > > >> hwcaps, so userspace can detect this CPU feature.
> > > >>
> > > >> Reported-by: Vladimir Danushevsky <vladimir.danushevsky at oracle.com>
> > > >> Signed-off-by: Will Deacon <will.deacon at arm.com>
> > > > ...
> > > >> +
> > > >> +     /* LPAE implies atomic ldrd/strd instructions */
> > > >> +     vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
> > > >> +     if (vmsa >= 5)
> > > >> +             elf_hwcap |= HWCAP_LPAE;
> > > >
> > > > As I mentioned in the past, I don't agree with exposing the "LPAE"
> > > > feature to user-space, it's not a feature that user space should care
> > > > about. An atomic double hwcap is better and you can even make this per
> > > > CPU via __v7_proc.
> > > 
> > > How does userspace know whether to install a non-LPAE or LPAE kernel
> > > in a generic way?
> > 
> > This is a valid reason to expose LPAE to user, though elf_hwcap sounds a
> > bit strange.
> 
> In lieu of anything else, do you mind if I continue with the patch as it
> stands?

OK, I give up ;)

-- 
Catalin


From b.brezillon at overkiz.com  Thu May 23 04:49:47 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 10:49:47 +0200
Subject: [PATCH 0/3] ARM: at91: move aic driver to drivers/irqchip
Message-ID: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>

Hello,

This patch series move the at91 AIC (Advance Interrupt Controller)
driver to the irqchip subsystem directory (drivers/irqchip).

It also make use of IRQCHIP_DECLARE to register irqchip for dt boards
instead of using the machine specific "init_irq" function.

Finally it register the arch specific irq handler inside the the init
functions using set_handle_irq. This way we can remove all the machine
specific "handle_irq".

This patch series was tested on kizbox board (sam9g20 SoC) using
device tree. Could someone test it on other boards (both dt and non dt)?

Best Regards,
Boris


Boris BREZILLON (3):
  ARM: at91: move at91 aic driver to drivers/irqchip
  ARM: at91: use IRQCHIP_DECLARE instead of machine specific init_irq
  ARM: at91: use set_handle_irq instead of machine specific handle_irq

 arch/arm/mach-at91/Makefile                |    2 +-
 arch/arm/mach-at91/at91_aic.h              |   99 -----
 arch/arm/mach-at91/at91rm9200.c            |    2 +-
 arch/arm/mach-at91/at91sam9260.c           |    2 +-
 arch/arm/mach-at91/at91sam9261.c           |    2 +-
 arch/arm/mach-at91/at91sam9263.c           |    2 +-
 arch/arm/mach-at91/at91sam9g45.c           |    2 +-
 arch/arm/mach-at91/at91sam9rl.c            |    2 +-
 arch/arm/mach-at91/at91x40.c               |    2 +-
 arch/arm/mach-at91/board-1arm.c            |    3 +-
 arch/arm/mach-at91/board-afeb-9260v1.c     |    3 +-
 arch/arm/mach-at91/board-cam60.c           |    3 +-
 arch/arm/mach-at91/board-carmeva.c         |    3 +-
 arch/arm/mach-at91/board-cpu9krea.c        |    3 +-
 arch/arm/mach-at91/board-cpuat91.c         |    3 +-
 arch/arm/mach-at91/board-csb337.c          |    3 +-
 arch/arm/mach-at91/board-csb637.c          |    3 +-
 arch/arm/mach-at91/board-dt-rm9200.c       |   15 +-
 arch/arm/mach-at91/board-dt-sam9.c         |   16 +-
 arch/arm/mach-at91/board-dt-sama5.c        |   16 +-
 arch/arm/mach-at91/board-eb01.c            |    4 +-
 arch/arm/mach-at91/board-eb9200.c          |    4 +-
 arch/arm/mach-at91/board-ecbat91.c         |    3 +-
 arch/arm/mach-at91/board-eco920.c          |    3 +-
 arch/arm/mach-at91/board-flexibity.c       |    3 +-
 arch/arm/mach-at91/board-foxg20.c          |    3 +-
 arch/arm/mach-at91/board-gsia18s.c         |    3 +-
 arch/arm/mach-at91/board-kafa.c            |    3 +-
 arch/arm/mach-at91/board-kb9202.c          |    3 +-
 arch/arm/mach-at91/board-pcontrol-g20.c    |    3 +-
 arch/arm/mach-at91/board-picotux200.c      |    3 +-
 arch/arm/mach-at91/board-qil-a9260.c       |    3 +-
 arch/arm/mach-at91/board-rm9200dk.c        |    3 +-
 arch/arm/mach-at91/board-rm9200ek.c        |    3 +-
 arch/arm/mach-at91/board-rsi-ews.c         |    4 +-
 arch/arm/mach-at91/board-sam9-l9260.c      |    3 +-
 arch/arm/mach-at91/board-sam9260ek.c       |    3 +-
 arch/arm/mach-at91/board-sam9261ek.c       |    3 +-
 arch/arm/mach-at91/board-sam9263ek.c       |    3 +-
 arch/arm/mach-at91/board-sam9g20ek.c       |    4 +-
 arch/arm/mach-at91/board-sam9m10g45ek.c    |    3 +-
 arch/arm/mach-at91/board-sam9rlek.c        |    3 +-
 arch/arm/mach-at91/board-snapper9260.c     |    3 +-
 arch/arm/mach-at91/board-stamp9g20.c       |    4 +-
 arch/arm/mach-at91/board-usb-a926x.c       |    5 +-
 arch/arm/mach-at91/board-yl-9200.c         |    3 +-
 arch/arm/mach-at91/generic.h               |    5 -
 arch/arm/mach-at91/include/mach/at91_aic.h |   96 +++++
 arch/arm/mach-at91/irq.c                   |  547 ---------------------------
 arch/arm/mach-at91/pm.c                    |    2 +-
 drivers/irqchip/Makefile                   |    1 +
 drivers/irqchip/irq-at91.c                 |  557 ++++++++++++++++++++++++++++
 52 files changed, 706 insertions(+), 773 deletions(-)
 delete mode 100644 arch/arm/mach-at91/at91_aic.h
 create mode 100644 arch/arm/mach-at91/include/mach/at91_aic.h
 delete mode 100644 arch/arm/mach-at91/irq.c
 create mode 100644 drivers/irqchip/irq-at91.c

-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 04:49:49 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 10:49:49 +0200
Subject: [PATCH 2/3] ARM: at91: use IRQCHIP_DECLARE instead of machine
 specific init_irq
In-Reply-To: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
References: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369298990-9826-3-git-send-email-b.brezillon@overkiz.com>

From: Boris BREZILLON <brezillonboris at gmail.com>

Replace machine specific init_irq functions with IRQCHIP_DECLARE.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/board-dt-rm9200.c |   11 -----------
 arch/arm/mach-at91/board-dt-sam9.c   |   12 ------------
 arch/arm/mach-at91/board-dt-sama5.c  |   12 ------------
 arch/arm/mach-at91/generic.h         |    5 -----
 drivers/irqchip/irq-at91.c           |    4 ++++
 5 files changed, 4 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 0c2a06d..523a9ae 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -27,16 +27,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91rm9200_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static void __init at91rm9200_dt_device_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -52,7 +42,6 @@ DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.map_io		= at91_map_io,
 	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91rm9200_dt_initialize,
-	.init_irq	= at91rm9200_dt_init_irq,
 	.init_machine	= at91rm9200_dt_device_init,
 	.dt_compat	= at91rm9200_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index ac899d8..a07da3b 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -27,17 +27,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static void __init at91_dt_device_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -54,7 +43,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	.map_io		= at91_map_io,
 	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 43b8f7a..65cf099 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -28,17 +28,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
 	int value;
@@ -81,7 +70,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	.map_io		= at91_map_io,
 	.handle_irq	= at91_aic5_handle_irq,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= sama5_dt_device_init,
 	.dt_compat	= sama5_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..23077cf 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,11 +29,6 @@ extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[],
 				 unsigned int ext_irq_mask);
-extern int  __init at91_aic_of_init(struct device_node *node,
-				    struct device_node *parent);
-extern int  __init at91_aic5_of_init(struct device_node *node,
-				    struct device_node *parent);
-
 
  /* Timer */
 extern void at91rm9200_ioremap_st(u32 addr);
diff --git a/drivers/irqchip/irq-at91.c b/drivers/irqchip/irq-at91.c
index daf2959..b45fe2c 100644
--- a/drivers/irqchip/irq-at91.c
+++ b/drivers/irqchip/irq-at91.c
@@ -44,6 +44,8 @@
 
 #include <mach/at91_aic.h>
 
+#include "irqchip.h"
+
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
 static struct device_node *at91_aic_np;
@@ -471,6 +473,7 @@ int __init at91_aic_of_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", at91_aic_of_init);
 
 int __init at91_aic5_of_init(struct device_node *node,
 				     struct device_node *parent)
@@ -493,6 +496,7 @@ int __init at91_aic5_of_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(sama5d3_aic, "atmel,sama5d3-aic", at91_aic5_of_init);
 #endif
 
 /*
-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 04:49:48 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 10:49:48 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
References: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369298990-9826-2-git-send-email-b.brezillon@overkiz.com>

From: Boris BREZILLON <brezillonboris at gmail.com>

Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
Move arch/arm/mach-at91/at91_aic.h to
arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
to header file :
#include "../../arch/arm/mach-at91/at91_aic.h"

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/Makefile                |    2 +-
 arch/arm/mach-at91/at91_aic.h              |   99 -----
 arch/arm/mach-at91/at91rm9200.c            |    2 +-
 arch/arm/mach-at91/at91sam9260.c           |    2 +-
 arch/arm/mach-at91/at91sam9261.c           |    2 +-
 arch/arm/mach-at91/at91sam9263.c           |    2 +-
 arch/arm/mach-at91/at91sam9g45.c           |    2 +-
 arch/arm/mach-at91/at91sam9rl.c            |    2 +-
 arch/arm/mach-at91/at91x40.c               |    2 +-
 arch/arm/mach-at91/board-1arm.c            |    2 +-
 arch/arm/mach-at91/board-afeb-9260v1.c     |    2 +-
 arch/arm/mach-at91/board-cam60.c           |    2 +-
 arch/arm/mach-at91/board-carmeva.c         |    2 +-
 arch/arm/mach-at91/board-cpu9krea.c        |    2 +-
 arch/arm/mach-at91/board-cpuat91.c         |    2 +-
 arch/arm/mach-at91/board-csb337.c          |    2 +-
 arch/arm/mach-at91/board-csb637.c          |    2 +-
 arch/arm/mach-at91/board-dt-rm9200.c       |    3 +-
 arch/arm/mach-at91/board-dt-sam9.c         |    3 +-
 arch/arm/mach-at91/board-dt-sama5.c        |    3 +-
 arch/arm/mach-at91/board-eb01.c            |    3 +-
 arch/arm/mach-at91/board-eb9200.c          |    3 +-
 arch/arm/mach-at91/board-ecbat91.c         |    2 +-
 arch/arm/mach-at91/board-eco920.c          |    2 +-
 arch/arm/mach-at91/board-flexibity.c       |    2 +-
 arch/arm/mach-at91/board-foxg20.c          |    2 +-
 arch/arm/mach-at91/board-gsia18s.c         |    2 +-
 arch/arm/mach-at91/board-kafa.c            |    2 +-
 arch/arm/mach-at91/board-kb9202.c          |    2 +-
 arch/arm/mach-at91/board-pcontrol-g20.c    |    2 +-
 arch/arm/mach-at91/board-picotux200.c      |    2 +-
 arch/arm/mach-at91/board-qil-a9260.c       |    2 +-
 arch/arm/mach-at91/board-rm9200dk.c        |    2 +-
 arch/arm/mach-at91/board-rm9200ek.c        |    2 +-
 arch/arm/mach-at91/board-rsi-ews.c         |    3 +-
 arch/arm/mach-at91/board-sam9-l9260.c      |    2 +-
 arch/arm/mach-at91/board-sam9260ek.c       |    2 +-
 arch/arm/mach-at91/board-sam9261ek.c       |    2 +-
 arch/arm/mach-at91/board-sam9263ek.c       |    2 +-
 arch/arm/mach-at91/board-sam9g20ek.c       |    2 +-
 arch/arm/mach-at91/board-sam9m10g45ek.c    |    2 +-
 arch/arm/mach-at91/board-sam9rlek.c        |    2 +-
 arch/arm/mach-at91/board-snapper9260.c     |    2 +-
 arch/arm/mach-at91/board-stamp9g20.c       |    2 +-
 arch/arm/mach-at91/board-usb-a926x.c       |    2 +-
 arch/arm/mach-at91/board-yl-9200.c         |    2 +-
 arch/arm/mach-at91/include/mach/at91_aic.h |   99 +++++
 arch/arm/mach-at91/irq.c                   |  547 ----------------------------
 arch/arm/mach-at91/pm.c                    |    2 +-
 drivers/irqchip/Makefile                   |    1 +
 drivers/irqchip/irq-at91.c                 |  547 ++++++++++++++++++++++++++++
 51 files changed, 699 insertions(+), 692 deletions(-)

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562d..5333701 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y		:= irq.o gpio.o setup.o
+obj-y		:= gpio.o setup.o
 obj-m		:=
 obj-n		:=
 obj-		:=
diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
deleted file mode 100644
index eaea661..0000000
--- a/arch/arm/mach-at91/at91_aic.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_aic.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Advanced Interrupt Controller (AIC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_AIC_H
-#define AT91_AIC_H
-
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_aic_base;
-
-#define at91_aic_read(field) \
-	__raw_readl(at91_aic_base + field)
-
-#define at91_aic_write(field, value) \
-	__raw_writel(value, at91_aic_base + field)
-#else
-.extern at91_aic_base
-#endif
-
-/* Number of irq lines managed by AIC */
-#define NR_AIC_IRQS	32
-#define NR_AIC5_IRQS	128
-
-#define AT91_AIC5_SSR		0x0			/* Source Select Register [AIC5] */
-#define 	AT91_AIC5_INTSEL_MSK	(0x7f << 0)		/* Interrupt Line Selection Mask */
-
-#define AT91_AIC_IRQ_MIN_PRIORITY	0
-#define AT91_AIC_IRQ_MAX_PRIORITY	7
-
-#define AT91_AIC_SMR(n)		((n) * 4)		/* Source Mode Registers 0-31 */
-#define AT91_AIC5_SMR		0x4			/* Source Mode Register [AIC5] */
-#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */
-#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */
-#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)
-#define			AT91_AIC_SRCTYPE_FALLING	(1 << 5)
-#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)
-#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)
-
-#define AT91_AIC_SVR(n)		(0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */
-#define AT91_AIC5_SVR		0x8			/* Source Vector Register [AIC5] */
-#define AT91_AIC_IVR		0x100			/* Interrupt Vector Register */
-#define AT91_AIC5_IVR		0x10			/* Interrupt Vector Register [AIC5] */
-#define AT91_AIC_FVR		0x104			/* Fast Interrupt Vector Register */
-#define AT91_AIC5_FVR		0x14			/* Fast Interrupt Vector Register [AIC5] */
-#define AT91_AIC_ISR		0x108			/* Interrupt Status Register */
-#define AT91_AIC5_ISR		0x18			/* Interrupt Status Register [AIC5] */
-#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */
-
-#define AT91_AIC_IPR		0x10c			/* Interrupt Pending Register */
-#define AT91_AIC5_IPR0		0x20			/* Interrupt Pending Register 0 [AIC5] */
-#define AT91_AIC5_IPR1		0x24			/* Interrupt Pending Register 1 [AIC5] */
-#define AT91_AIC5_IPR2		0x28			/* Interrupt Pending Register 2 [AIC5] */
-#define AT91_AIC5_IPR3		0x2c			/* Interrupt Pending Register 3 [AIC5] */
-#define AT91_AIC_IMR		0x110			/* Interrupt Mask Register */
-#define AT91_AIC5_IMR		0x30			/* Interrupt Mask Register [AIC5] */
-#define AT91_AIC_CISR		0x114			/* Core Interrupt Status Register */
-#define AT91_AIC5_CISR		0x34			/* Core Interrupt Status Register [AIC5] */
-#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */
-#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */
-
-#define AT91_AIC_IECR		0x120			/* Interrupt Enable Command Register */
-#define AT91_AIC5_IECR		0x40			/* Interrupt Enable Command Register [AIC5] */
-#define AT91_AIC_IDCR		0x124			/* Interrupt Disable Command Register */
-#define AT91_AIC5_IDCR		0x44			/* Interrupt Disable Command Register [AIC5] */
-#define AT91_AIC_ICCR		0x128			/* Interrupt Clear Command Register */
-#define AT91_AIC5_ICCR		0x48			/* Interrupt Clear Command Register [AIC5] */
-#define AT91_AIC_ISCR		0x12c			/* Interrupt Set Command Register */
-#define AT91_AIC5_ISCR		0x4c			/* Interrupt Set Command Register [AIC5] */
-#define AT91_AIC_EOICR		0x130			/* End of Interrupt Command Register */
-#define AT91_AIC5_EOICR		0x38			/* End of Interrupt Command Register [AIC5] */
-#define AT91_AIC_SPU		0x134			/* Spurious Interrupt Vector Register */
-#define AT91_AIC5_SPU		0x3c			/* Spurious Interrupt Vector Register [AIC5] */
-#define AT91_AIC_DCR		0x138			/* Debug Control Register */
-#define AT91_AIC5_DCR		0x6c			/* Debug Control Register [AIC5] */
-#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */
-#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */
-
-#define AT91_AIC_FFER		0x140			/* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC5_FFER		0x50			/* Fast Forcing Enable Register [AIC5] */
-#define AT91_AIC_FFDR		0x144			/* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC5_FFDR		0x54			/* Fast Forcing Disable Register [AIC5] */
-#define AT91_AIC_FFSR		0x148			/* Fast Forcing Status Register [SAM9 only] */
-#define AT91_AIC5_FFSR		0x58			/* Fast Forcing Status Register [AIC5] */
-
-void at91_aic_handle_irq(struct pt_regs *regs);
-void at91_aic5_handle_irq(struct pt_regs *regs);
-
-#endif
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..6c1204a 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -20,8 +20,8 @@
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a8ce245..55332fa 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -21,8 +21,8 @@
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 25efb5a..6db61e6 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -20,8 +20,8 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f44ffd2..b9ec043 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -19,8 +19,8 @@
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..1270707 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,8 +20,8 @@
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f77fae5..d5f77d6 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -20,8 +20,8 @@
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 19ca793..e8b30fb 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -20,8 +20,8 @@
 #include <mach/at91x40.h>
 #include <mach/at91_st.h>
 #include <mach/timex.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632..8037dfe 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/at91_aic.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31c..28bea23 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -42,8 +42,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index ade948b..6ebdf32 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -39,8 +39,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 9298305..842db49 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -35,8 +35,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527e..4714e9e 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,8 +43,8 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..c1663ed 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -39,8 +39,8 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215..3231703 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -38,8 +38,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf1106..d58c7e6 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -35,8 +35,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb662..0c2a06d 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -22,7 +22,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "generic.h"
 
 
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db3013..ac899d8 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,7 +21,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..43b8f7a 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -23,7 +23,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "generic.h"
 
 
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index becf0a6..4097ede 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -28,7 +28,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be816..afa5ebb 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -35,7 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71..c794768 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -38,8 +38,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..fc3e373 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -27,8 +27,8 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c085..59a1958 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -33,8 +33,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870..4b4df05 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -42,8 +42,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d2..1babcbd 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -31,8 +31,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d..aca52d3 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -35,8 +35,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..7768df0 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,8 +38,8 @@
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b..6df21db 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -30,8 +30,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..566b30c 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,8 +39,8 @@
 
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index aa3bc9b..0ae5eb1 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -41,8 +41,8 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 690541b..82f0335e 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,8 +41,8 @@
 #include <mach/hardware.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..5e8a4f7 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,8 +41,8 @@
 #include <mach/hardware.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f19..e7d0a69 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -28,7 +28,8 @@
 
 #include <linux/gpio.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc..2e400cd 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -38,8 +38,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0b153c8..66ee7ac 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -43,8 +43,8 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b446645..515957e 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -47,8 +47,8 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 3284df0..1099272 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -46,8 +46,8 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2..9fe718b 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -45,8 +45,8 @@
 
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 2a94896..1846647 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -44,8 +44,8 @@
 
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index aa265dc..623f2d1 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -31,9 +31,9 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa978..8fef38a 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -33,8 +33,8 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbec..6bda942 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -26,8 +26,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 2487d94..cedbc66 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -42,8 +42,8 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..c61d8c9 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -46,8 +46,8 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
new file mode 100644
index 0000000..eaea661
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -0,0 +1,99 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_aic.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Advanced Interrupt Controller (AIC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_AIC_H
+#define AT91_AIC_H
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_aic_base;
+
+#define at91_aic_read(field) \
+	__raw_readl(at91_aic_base + field)
+
+#define at91_aic_write(field, value) \
+	__raw_writel(value, at91_aic_base + field)
+#else
+.extern at91_aic_base
+#endif
+
+/* Number of irq lines managed by AIC */
+#define NR_AIC_IRQS	32
+#define NR_AIC5_IRQS	128
+
+#define AT91_AIC5_SSR		0x0			/* Source Select Register [AIC5] */
+#define 	AT91_AIC5_INTSEL_MSK	(0x7f << 0)		/* Interrupt Line Selection Mask */
+
+#define AT91_AIC_IRQ_MIN_PRIORITY	0
+#define AT91_AIC_IRQ_MAX_PRIORITY	7
+
+#define AT91_AIC_SMR(n)		((n) * 4)		/* Source Mode Registers 0-31 */
+#define AT91_AIC5_SMR		0x4			/* Source Mode Register [AIC5] */
+#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */
+#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */
+#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)
+#define			AT91_AIC_SRCTYPE_FALLING	(1 << 5)
+#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)
+#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)
+
+#define AT91_AIC_SVR(n)		(0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */
+#define AT91_AIC5_SVR		0x8			/* Source Vector Register [AIC5] */
+#define AT91_AIC_IVR		0x100			/* Interrupt Vector Register */
+#define AT91_AIC5_IVR		0x10			/* Interrupt Vector Register [AIC5] */
+#define AT91_AIC_FVR		0x104			/* Fast Interrupt Vector Register */
+#define AT91_AIC5_FVR		0x14			/* Fast Interrupt Vector Register [AIC5] */
+#define AT91_AIC_ISR		0x108			/* Interrupt Status Register */
+#define AT91_AIC5_ISR		0x18			/* Interrupt Status Register [AIC5] */
+#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR		0x10c			/* Interrupt Pending Register */
+#define AT91_AIC5_IPR0		0x20			/* Interrupt Pending Register 0 [AIC5] */
+#define AT91_AIC5_IPR1		0x24			/* Interrupt Pending Register 1 [AIC5] */
+#define AT91_AIC5_IPR2		0x28			/* Interrupt Pending Register 2 [AIC5] */
+#define AT91_AIC5_IPR3		0x2c			/* Interrupt Pending Register 3 [AIC5] */
+#define AT91_AIC_IMR		0x110			/* Interrupt Mask Register */
+#define AT91_AIC5_IMR		0x30			/* Interrupt Mask Register [AIC5] */
+#define AT91_AIC_CISR		0x114			/* Core Interrupt Status Register */
+#define AT91_AIC5_CISR		0x34			/* Core Interrupt Status Register [AIC5] */
+#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */
+#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */
+
+#define AT91_AIC_IECR		0x120			/* Interrupt Enable Command Register */
+#define AT91_AIC5_IECR		0x40			/* Interrupt Enable Command Register [AIC5] */
+#define AT91_AIC_IDCR		0x124			/* Interrupt Disable Command Register */
+#define AT91_AIC5_IDCR		0x44			/* Interrupt Disable Command Register [AIC5] */
+#define AT91_AIC_ICCR		0x128			/* Interrupt Clear Command Register */
+#define AT91_AIC5_ICCR		0x48			/* Interrupt Clear Command Register [AIC5] */
+#define AT91_AIC_ISCR		0x12c			/* Interrupt Set Command Register */
+#define AT91_AIC5_ISCR		0x4c			/* Interrupt Set Command Register [AIC5] */
+#define AT91_AIC_EOICR		0x130			/* End of Interrupt Command Register */
+#define AT91_AIC5_EOICR		0x38			/* End of Interrupt Command Register [AIC5] */
+#define AT91_AIC_SPU		0x134			/* Spurious Interrupt Vector Register */
+#define AT91_AIC5_SPU		0x3c			/* Spurious Interrupt Vector Register [AIC5] */
+#define AT91_AIC_DCR		0x138			/* Debug Control Register */
+#define AT91_AIC5_DCR		0x6c			/* Debug Control Register [AIC5] */
+#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */
+#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */
+
+#define AT91_AIC_FFER		0x140			/* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC5_FFER		0x50			/* Fast Forcing Enable Register [AIC5] */
+#define AT91_AIC_FFDR		0x144			/* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC5_FFDR		0x54			/* Fast Forcing Disable Register [AIC5] */
+#define AT91_AIC_FFSR		0x148			/* Fast Forcing Status Register [SAM9 only] */
+#define AT91_AIC5_FFSR		0x58			/* Fast Forcing Status Register [AIC5] */
+
+void at91_aic_handle_irq(struct pt_regs *regs);
+void at91_aic5_handle_irq(struct pt_regs *regs);
+
+#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
deleted file mode 100644
index e0ca591..0000000
--- a/arch/arm/mach-at91/irq.c
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/irq.c
- *
- *  Copyright (C) 2004 SAN People
- *  Copyright (C) 2004 ATMEL
- *  Copyright (C) Rick Bronson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/bitmap.h>
-#include <linux/types.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-
-#include <asm/exception.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-
-#include "at91_aic.h"
-
-void __iomem *at91_aic_base;
-static struct irq_domain *at91_aic_domain;
-static struct device_node *at91_aic_np;
-static unsigned int n_irqs = NR_AIC_IRQS;
-static unsigned long at91_aic_caps = 0;
-
-/* AIC5 introduces a Source Select Register */
-#define AT91_AIC_CAP_AIC5	(1 << 0)
-#define has_aic5()		(at91_aic_caps & AT91_AIC_CAP_AIC5)
-
-#ifdef CONFIG_PM
-
-static unsigned long *wakeups;
-static unsigned long *backups;
-
-#define set_backup(bit) set_bit(bit, backups)
-#define clear_backup(bit) clear_bit(bit, backups)
-
-static int at91_aic_pm_init(void)
-{
-	backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
-	if (!backups)
-		return -ENOMEM;
-
-	wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
-	if (!wakeups) {
-		kfree(backups);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static int at91_aic_set_wake(struct irq_data *d, unsigned value)
-{
-	if (unlikely(d->hwirq >= n_irqs))
-		return -EINVAL;
-
-	if (value)
-		set_bit(d->hwirq, wakeups);
-	else
-		clear_bit(d->hwirq, wakeups);
-
-	return 0;
-}
-
-void at91_irq_suspend(void)
-{
-	int bit = -1;
-
-	if (has_aic5()) {
-		/* disable enabled irqs */
-		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IDCR, 1);
-		}
-		/* enable wakeup irqs */
-		bit = -1;
-		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IECR, 1);
-		}
-	} else {
-		at91_aic_write(AT91_AIC_IDCR, *backups);
-		at91_aic_write(AT91_AIC_IECR, *wakeups);
-	}
-}
-
-void at91_irq_resume(void)
-{
-	int bit = -1;
-
-	if (has_aic5()) {
-		/* disable wakeup irqs */
-		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IDCR, 1);
-		}
-		/* enable irqs disabled for suspend */
-		bit = -1;
-		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
-			at91_aic_write(AT91_AIC5_SSR,
-				       bit & AT91_AIC5_INTSEL_MSK);
-			at91_aic_write(AT91_AIC5_IECR, 1);
-		}
-	} else {
-		at91_aic_write(AT91_AIC_IDCR, *wakeups);
-		at91_aic_write(AT91_AIC_IECR, *backups);
-	}
-}
-
-#else
-static inline int at91_aic_pm_init(void)
-{
-	return 0;
-}
-
-#define set_backup(bit)
-#define clear_backup(bit)
-#define at91_aic_set_wake	NULL
-
-#endif /* CONFIG_PM */
-
-asmlinkage void __exception_irq_entry
-at91_aic_handle_irq(struct pt_regs *regs)
-{
-	u32 irqnr;
-	u32 irqstat;
-
-	irqnr = at91_aic_read(AT91_AIC_IVR);
-	irqstat = at91_aic_read(AT91_AIC_ISR);
-
-	/*
-	 * ISR value is 0 when there is no current interrupt or when there is
-	 * a spurious interrupt
-	 */
-	if (!irqstat)
-		at91_aic_write(AT91_AIC_EOICR, 0);
-	else
-		handle_IRQ(irqnr, regs);
-}
-
-asmlinkage void __exception_irq_entry
-at91_aic5_handle_irq(struct pt_regs *regs)
-{
-	u32 irqnr;
-	u32 irqstat;
-
-	irqnr = at91_aic_read(AT91_AIC5_IVR);
-	irqstat = at91_aic_read(AT91_AIC5_ISR);
-
-	if (!irqstat)
-		at91_aic_write(AT91_AIC5_EOICR, 0);
-	else
-		handle_IRQ(irqnr, regs);
-}
-
-static void at91_aic_mask_irq(struct irq_data *d)
-{
-	/* Disable interrupt on AIC */
-	at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
-	/* Update ISR cache */
-	clear_backup(d->hwirq);
-}
-
-static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
-{
-	/* Disable interrupt on AIC5 */
-	at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
-	at91_aic_write(AT91_AIC5_IDCR, 1);
-	/* Update ISR cache */
-	clear_backup(d->hwirq);
-}
-
-static void at91_aic_unmask_irq(struct irq_data *d)
-{
-	/* Enable interrupt on AIC */
-	at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
-	/* Update ISR cache */
-	set_backup(d->hwirq);
-}
-
-static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
-{
-	/* Enable interrupt on AIC5 */
-	at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
-	at91_aic_write(AT91_AIC5_IECR, 1);
-	/* Update ISR cache */
-	set_backup(d->hwirq);
-}
-
-static void at91_aic_eoi(struct irq_data *d)
-{
-	/*
-	 * Mark end-of-interrupt on AIC, the controller doesn't care about
-	 * the value written. Moreover it's a write-only register.
-	 */
-	at91_aic_write(AT91_AIC_EOICR, 0);
-}
-
-static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
-{
-	at91_aic_write(AT91_AIC5_EOICR, 0);
-}
-
-unsigned long *at91_extern_irq;
-
-#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
-
-static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
-{
-	int srctype;
-
-	switch (type) {
-	case IRQ_TYPE_LEVEL_HIGH:
-		srctype = AT91_AIC_SRCTYPE_HIGH;
-		break;
-	case IRQ_TYPE_EDGE_RISING:
-		srctype = AT91_AIC_SRCTYPE_RISING;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))		/* only supported on external interrupts */
-			srctype = AT91_AIC_SRCTYPE_LOW;
-		else
-			srctype = -EINVAL;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))		/* only supported on external interrupts */
-			srctype = AT91_AIC_SRCTYPE_FALLING;
-		else
-			srctype = -EINVAL;
-		break;
-	default:
-		srctype = -EINVAL;
-	}
-
-	return srctype;
-}
-
-static int at91_aic_set_type(struct irq_data *d, unsigned type)
-{
-	unsigned int smr;
-	int srctype;
-
-	srctype = at91_aic_compute_srctype(d, type);
-	if (srctype < 0)
-		return srctype;
-
-	if (has_aic5()) {
-		at91_aic_write(AT91_AIC5_SSR,
-			       d->hwirq & AT91_AIC5_INTSEL_MSK);
-		smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
-		at91_aic_write(AT91_AIC5_SMR, smr | srctype);
-	} else {
-		smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
-		      & ~AT91_AIC_SRCTYPE;
-		at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
-	}
-
-	return 0;
-}
-
-static struct irq_chip at91_aic_chip = {
-	.name		= "AIC",
-	.irq_mask	= at91_aic_mask_irq,
-	.irq_unmask	= at91_aic_unmask_irq,
-	.irq_set_type	= at91_aic_set_type,
-	.irq_set_wake	= at91_aic_set_wake,
-	.irq_eoi	= at91_aic_eoi,
-};
-
-static void __init at91_aic_hw_init(unsigned int spu_vector)
-{
-	int i;
-
-	/*
-	 * Perform 8 End Of Interrupt Command to make sure AIC
-	 * will not Lock out nIRQ
-	 */
-	for (i = 0; i < 8; i++)
-		at91_aic_write(AT91_AIC_EOICR, 0);
-
-	/*
-	 * Spurious Interrupt ID in Spurious Vector Register.
-	 * When there is no current interrupt, the IRQ Vector Register
-	 * reads the value stored in AIC_SPU
-	 */
-	at91_aic_write(AT91_AIC_SPU, spu_vector);
-
-	/* No debugging in AIC: Debug (Protect) Control Register */
-	at91_aic_write(AT91_AIC_DCR, 0);
-
-	/* Disable and clear all interrupts initially */
-	at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-	at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
-}
-
-static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
-{
-	int i;
-
-	/*
-	 * Perform 8 End Of Interrupt Command to make sure AIC
-	 * will not Lock out nIRQ
-	 */
-	for (i = 0; i < 8; i++)
-		at91_aic_write(AT91_AIC5_EOICR, 0);
-
-	/*
-	 * Spurious Interrupt ID in Spurious Vector Register.
-	 * When there is no current interrupt, the IRQ Vector Register
-	 * reads the value stored in AIC_SPU
-	 */
-	at91_aic_write(AT91_AIC5_SPU, spu_vector);
-
-	/* No debugging in AIC: Debug (Protect) Control Register */
-	at91_aic_write(AT91_AIC5_DCR, 0);
-
-	/* Disable and clear all interrupts initially */
-	for (i = 0; i < n_irqs; i++) {
-		at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
-		at91_aic_write(AT91_AIC5_IDCR, 1);
-		at91_aic_write(AT91_AIC5_ICCR, 1);
-	}
-}
-
-#if defined(CONFIG_OF)
-static unsigned int *at91_aic_irq_priorities;
-
-static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
-							irq_hw_number_t hw)
-{
-	/* Put virq number in Source Vector Register */
-	at91_aic_write(AT91_AIC_SVR(hw), virq);
-
-	/* Active Low interrupt, with priority */
-	at91_aic_write(AT91_AIC_SMR(hw),
-		       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
-
-	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
-	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-	return 0;
-}
-
-static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
-		irq_hw_number_t hw)
-{
-	at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
-
-	/* Put virq number in Source Vector Register */
-	at91_aic_write(AT91_AIC5_SVR, virq);
-
-	/* Active Low interrupt, with priority */
-	at91_aic_write(AT91_AIC5_SMR,
-		       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
-
-	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
-	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-	return 0;
-}
-
-static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
-				const u32 *intspec, unsigned int intsize,
-				irq_hw_number_t *out_hwirq, unsigned int *out_type)
-{
-	if (WARN_ON(intsize < 3))
-		return -EINVAL;
-	if (WARN_ON(intspec[0] >= n_irqs))
-		return -EINVAL;
-	if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
-		    || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
-		return -EINVAL;
-
-	*out_hwirq = intspec[0];
-	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
-	at91_aic_irq_priorities[*out_hwirq] = intspec[2];
-
-	return 0;
-}
-
-static struct irq_domain_ops at91_aic_irq_ops = {
-	.map	= at91_aic_irq_map,
-	.xlate	= at91_aic_irq_domain_xlate,
-};
-
-int __init at91_aic_of_common_init(struct device_node *node,
-				    struct device_node *parent)
-{
-	struct property *prop;
-	const __be32 *p;
-	u32 val;
-
-	at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
-				  * sizeof(*at91_extern_irq), GFP_KERNEL);
-	if (!at91_extern_irq)
-		return -ENOMEM;
-
-	if (at91_aic_pm_init()) {
-		kfree(at91_extern_irq);
-		return -ENOMEM;
-	}
-
-	at91_aic_irq_priorities = kzalloc(n_irqs
-					  * sizeof(*at91_aic_irq_priorities),
-					  GFP_KERNEL);
-	if (!at91_aic_irq_priorities)
-		return -ENOMEM;
-
-	at91_aic_base = of_iomap(node, 0);
-	at91_aic_np = node;
-
-	at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
-						&at91_aic_irq_ops, NULL);
-	if (!at91_aic_domain)
-		panic("Unable to add AIC irq domain (DT)\n");
-
-	of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
-		if (val >= n_irqs)
-			pr_warn("AIC: external irq %d >= %d skip it\n",
-				val, n_irqs);
-		else
-			set_bit(val, at91_extern_irq);
-	}
-
-	irq_set_default_host(at91_aic_domain);
-
-	return 0;
-}
-
-int __init at91_aic_of_init(struct device_node *node,
-				     struct device_node *parent)
-{
-	int err;
-
-	err = at91_aic_of_common_init(node, parent);
-	if (err)
-		return err;
-
-	at91_aic_hw_init(n_irqs);
-
-	return 0;
-}
-
-int __init at91_aic5_of_init(struct device_node *node,
-				     struct device_node *parent)
-{
-	int err;
-
-	at91_aic_caps |= AT91_AIC_CAP_AIC5;
-	n_irqs = NR_AIC5_IRQS;
-	at91_aic_chip.irq_ack           = at91_aic5_mask_irq;
-	at91_aic_chip.irq_mask		= at91_aic5_mask_irq;
-	at91_aic_chip.irq_unmask	= at91_aic5_unmask_irq;
-	at91_aic_chip.irq_eoi		= at91_aic5_eoi;
-	at91_aic_irq_ops.map		= at91_aic5_irq_map;
-
-	err = at91_aic_of_common_init(node, parent);
-	if (err)
-		return err;
-
-	at91_aic5_hw_init(n_irqs);
-
-	return 0;
-}
-#endif
-
-/*
- * Initialize the AIC interrupt controller.
- */
-void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
-{
-	unsigned int i;
-	int irq_base;
-
-	at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
-				  * sizeof(*at91_extern_irq), GFP_KERNEL);
-
-	if (at91_aic_pm_init() || at91_extern_irq == NULL)
-		panic("Unable to allocate bit maps\n");
-
-	*at91_extern_irq = ext_irq_mask;
-
-	at91_aic_base = ioremap(AT91_AIC, 512);
-	if (!at91_aic_base)
-		panic("Unable to ioremap AIC registers\n");
-
-	/* Add irq domain for AIC */
-	irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
-	if (irq_base < 0) {
-		WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
-		irq_base = 0;
-	}
-	at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
-						irq_base, 0,
-						&irq_domain_simple_ops, NULL);
-
-	if (!at91_aic_domain)
-		panic("Unable to add AIC irq domain\n");
-
-	irq_set_default_host(at91_aic_domain);
-
-	/*
-	 * The IVR is used by macro get_irqnr_and_base to read and verify.
-	 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
-	 */
-	for (i = 0; i < n_irqs; i++) {
-		/* Put hardware irq number in Source Vector Register: */
-		at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
-		/* Active Low interrupt, with the specified priority */
-		at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
-		irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
-		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-	}
-
-	at91_aic_hw_init(n_irqs);
-}
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 530db30..d2a24e8 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -26,9 +26,9 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 #include "pm.h"
 
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5..208b708 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
+obj-$(CONFIG_ARCH_AT91)			+= irq-at91.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
diff --git a/drivers/irqchip/irq-at91.c b/drivers/irqchip/irq-at91.c
new file mode 100644
index 0000000..daf2959
--- /dev/null
+++ b/drivers/irqchip/irq-at91.c
@@ -0,0 +1,547 @@
+/*
+ * linux/arch/arm/mach-at91/irq.c
+ *
+ *  Copyright (C) 2004 SAN People
+ *  Copyright (C) 2004 ATMEL
+ *  Copyright (C) Rick Bronson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/bitmap.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+
+#include <asm/exception.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+
+#include <mach/at91_aic.h>
+
+void __iomem *at91_aic_base;
+static struct irq_domain *at91_aic_domain;
+static struct device_node *at91_aic_np;
+static unsigned int n_irqs = NR_AIC_IRQS;
+static unsigned long at91_aic_caps = 0;
+
+/* AIC5 introduces a Source Select Register */
+#define AT91_AIC_CAP_AIC5	(1 << 0)
+#define has_aic5()		(at91_aic_caps & AT91_AIC_CAP_AIC5)
+
+#ifdef CONFIG_PM
+
+static unsigned long *wakeups;
+static unsigned long *backups;
+
+#define set_backup(bit) set_bit(bit, backups)
+#define clear_backup(bit) clear_bit(bit, backups)
+
+static int at91_aic_pm_init(void)
+{
+	backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
+	if (!backups)
+		return -ENOMEM;
+
+	wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
+	if (!wakeups) {
+		kfree(backups);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int at91_aic_set_wake(struct irq_data *d, unsigned value)
+{
+	if (unlikely(d->hwirq >= n_irqs))
+		return -EINVAL;
+
+	if (value)
+		set_bit(d->hwirq, wakeups);
+	else
+		clear_bit(d->hwirq, wakeups);
+
+	return 0;
+}
+
+void at91_irq_suspend(void)
+{
+	int bit = -1;
+
+	if (has_aic5()) {
+		/* disable enabled irqs */
+		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
+			at91_aic_write(AT91_AIC5_SSR,
+				       bit & AT91_AIC5_INTSEL_MSK);
+			at91_aic_write(AT91_AIC5_IDCR, 1);
+		}
+		/* enable wakeup irqs */
+		bit = -1;
+		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
+			at91_aic_write(AT91_AIC5_SSR,
+				       bit & AT91_AIC5_INTSEL_MSK);
+			at91_aic_write(AT91_AIC5_IECR, 1);
+		}
+	} else {
+		at91_aic_write(AT91_AIC_IDCR, *backups);
+		at91_aic_write(AT91_AIC_IECR, *wakeups);
+	}
+}
+
+void at91_irq_resume(void)
+{
+	int bit = -1;
+
+	if (has_aic5()) {
+		/* disable wakeup irqs */
+		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
+			at91_aic_write(AT91_AIC5_SSR,
+				       bit & AT91_AIC5_INTSEL_MSK);
+			at91_aic_write(AT91_AIC5_IDCR, 1);
+		}
+		/* enable irqs disabled for suspend */
+		bit = -1;
+		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
+			at91_aic_write(AT91_AIC5_SSR,
+				       bit & AT91_AIC5_INTSEL_MSK);
+			at91_aic_write(AT91_AIC5_IECR, 1);
+		}
+	} else {
+		at91_aic_write(AT91_AIC_IDCR, *wakeups);
+		at91_aic_write(AT91_AIC_IECR, *backups);
+	}
+}
+
+#else
+static inline int at91_aic_pm_init(void)
+{
+	return 0;
+}
+
+#define set_backup(bit)
+#define clear_backup(bit)
+#define at91_aic_set_wake	NULL
+
+#endif /* CONFIG_PM */
+
+asmlinkage void __exception_irq_entry
+at91_aic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqnr;
+	u32 irqstat;
+
+	irqnr = at91_aic_read(AT91_AIC_IVR);
+	irqstat = at91_aic_read(AT91_AIC_ISR);
+
+	/*
+	 * ISR value is 0 when there is no current interrupt or when there is
+	 * a spurious interrupt
+	 */
+	if (!irqstat)
+		at91_aic_write(AT91_AIC_EOICR, 0);
+	else
+		handle_IRQ(irqnr, regs);
+}
+
+asmlinkage void __exception_irq_entry
+at91_aic5_handle_irq(struct pt_regs *regs)
+{
+	u32 irqnr;
+	u32 irqstat;
+
+	irqnr = at91_aic_read(AT91_AIC5_IVR);
+	irqstat = at91_aic_read(AT91_AIC5_ISR);
+
+	if (!irqstat)
+		at91_aic_write(AT91_AIC5_EOICR, 0);
+	else
+		handle_IRQ(irqnr, regs);
+}
+
+static void at91_aic_mask_irq(struct irq_data *d)
+{
+	/* Disable interrupt on AIC */
+	at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
+	/* Update ISR cache */
+	clear_backup(d->hwirq);
+}
+
+static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
+{
+	/* Disable interrupt on AIC5 */
+	at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
+	at91_aic_write(AT91_AIC5_IDCR, 1);
+	/* Update ISR cache */
+	clear_backup(d->hwirq);
+}
+
+static void at91_aic_unmask_irq(struct irq_data *d)
+{
+	/* Enable interrupt on AIC */
+	at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
+	/* Update ISR cache */
+	set_backup(d->hwirq);
+}
+
+static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
+{
+	/* Enable interrupt on AIC5 */
+	at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
+	at91_aic_write(AT91_AIC5_IECR, 1);
+	/* Update ISR cache */
+	set_backup(d->hwirq);
+}
+
+static void at91_aic_eoi(struct irq_data *d)
+{
+	/*
+	 * Mark end-of-interrupt on AIC, the controller doesn't care about
+	 * the value written. Moreover it's a write-only register.
+	 */
+	at91_aic_write(AT91_AIC_EOICR, 0);
+}
+
+static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
+{
+	at91_aic_write(AT91_AIC5_EOICR, 0);
+}
+
+unsigned long *at91_extern_irq;
+
+#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
+
+static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
+{
+	int srctype;
+
+	switch (type) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		srctype = AT91_AIC_SRCTYPE_HIGH;
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		srctype = AT91_AIC_SRCTYPE_RISING;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))		/* only supported on external interrupts */
+			srctype = AT91_AIC_SRCTYPE_LOW;
+		else
+			srctype = -EINVAL;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))		/* only supported on external interrupts */
+			srctype = AT91_AIC_SRCTYPE_FALLING;
+		else
+			srctype = -EINVAL;
+		break;
+	default:
+		srctype = -EINVAL;
+	}
+
+	return srctype;
+}
+
+static int at91_aic_set_type(struct irq_data *d, unsigned type)
+{
+	unsigned int smr;
+	int srctype;
+
+	srctype = at91_aic_compute_srctype(d, type);
+	if (srctype < 0)
+		return srctype;
+
+	if (has_aic5()) {
+		at91_aic_write(AT91_AIC5_SSR,
+			       d->hwirq & AT91_AIC5_INTSEL_MSK);
+		smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
+		at91_aic_write(AT91_AIC5_SMR, smr | srctype);
+	} else {
+		smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
+		      & ~AT91_AIC_SRCTYPE;
+		at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
+	}
+
+	return 0;
+}
+
+static struct irq_chip at91_aic_chip = {
+	.name		= "AIC",
+	.irq_mask	= at91_aic_mask_irq,
+	.irq_unmask	= at91_aic_unmask_irq,
+	.irq_set_type	= at91_aic_set_type,
+	.irq_set_wake	= at91_aic_set_wake,
+	.irq_eoi	= at91_aic_eoi,
+};
+
+static void __init at91_aic_hw_init(unsigned int spu_vector)
+{
+	int i;
+
+	/*
+	 * Perform 8 End Of Interrupt Command to make sure AIC
+	 * will not Lock out nIRQ
+	 */
+	for (i = 0; i < 8; i++)
+		at91_aic_write(AT91_AIC_EOICR, 0);
+
+	/*
+	 * Spurious Interrupt ID in Spurious Vector Register.
+	 * When there is no current interrupt, the IRQ Vector Register
+	 * reads the value stored in AIC_SPU
+	 */
+	at91_aic_write(AT91_AIC_SPU, spu_vector);
+
+	/* No debugging in AIC: Debug (Protect) Control Register */
+	at91_aic_write(AT91_AIC_DCR, 0);
+
+	/* Disable and clear all interrupts initially */
+	at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+	at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+}
+
+static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
+{
+	int i;
+
+	/*
+	 * Perform 8 End Of Interrupt Command to make sure AIC
+	 * will not Lock out nIRQ
+	 */
+	for (i = 0; i < 8; i++)
+		at91_aic_write(AT91_AIC5_EOICR, 0);
+
+	/*
+	 * Spurious Interrupt ID in Spurious Vector Register.
+	 * When there is no current interrupt, the IRQ Vector Register
+	 * reads the value stored in AIC_SPU
+	 */
+	at91_aic_write(AT91_AIC5_SPU, spu_vector);
+
+	/* No debugging in AIC: Debug (Protect) Control Register */
+	at91_aic_write(AT91_AIC5_DCR, 0);
+
+	/* Disable and clear all interrupts initially */
+	for (i = 0; i < n_irqs; i++) {
+		at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
+		at91_aic_write(AT91_AIC5_IDCR, 1);
+		at91_aic_write(AT91_AIC5_ICCR, 1);
+	}
+}
+
+#if defined(CONFIG_OF)
+static unsigned int *at91_aic_irq_priorities;
+
+static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
+							irq_hw_number_t hw)
+{
+	/* Put virq number in Source Vector Register */
+	at91_aic_write(AT91_AIC_SVR(hw), virq);
+
+	/* Active Low interrupt, with priority */
+	at91_aic_write(AT91_AIC_SMR(hw),
+		       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
+
+	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
+		irq_hw_number_t hw)
+{
+	at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
+
+	/* Put virq number in Source Vector Register */
+	at91_aic_write(AT91_AIC5_SVR, virq);
+
+	/* Active Low interrupt, with priority */
+	at91_aic_write(AT91_AIC5_SMR,
+		       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
+
+	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+				const u32 *intspec, unsigned int intsize,
+				irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+	if (WARN_ON(intsize < 3))
+		return -EINVAL;
+	if (WARN_ON(intspec[0] >= n_irqs))
+		return -EINVAL;
+	if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
+		    || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
+		return -EINVAL;
+
+	*out_hwirq = intspec[0];
+	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+	at91_aic_irq_priorities[*out_hwirq] = intspec[2];
+
+	return 0;
+}
+
+static struct irq_domain_ops at91_aic_irq_ops = {
+	.map	= at91_aic_irq_map,
+	.xlate	= at91_aic_irq_domain_xlate,
+};
+
+int __init at91_aic_of_common_init(struct device_node *node,
+				    struct device_node *parent)
+{
+	struct property *prop;
+	const __be32 *p;
+	u32 val;
+
+	at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
+				  * sizeof(*at91_extern_irq), GFP_KERNEL);
+	if (!at91_extern_irq)
+		return -ENOMEM;
+
+	if (at91_aic_pm_init()) {
+		kfree(at91_extern_irq);
+		return -ENOMEM;
+	}
+
+	at91_aic_irq_priorities = kzalloc(n_irqs
+					  * sizeof(*at91_aic_irq_priorities),
+					  GFP_KERNEL);
+	if (!at91_aic_irq_priorities)
+		return -ENOMEM;
+
+	at91_aic_base = of_iomap(node, 0);
+	at91_aic_np = node;
+
+	at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
+						&at91_aic_irq_ops, NULL);
+	if (!at91_aic_domain)
+		panic("Unable to add AIC irq domain (DT)\n");
+
+	of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
+		if (val >= n_irqs)
+			pr_warn("AIC: external irq %d >= %d skip it\n",
+				val, n_irqs);
+		else
+			set_bit(val, at91_extern_irq);
+	}
+
+	irq_set_default_host(at91_aic_domain);
+
+	return 0;
+}
+
+int __init at91_aic_of_init(struct device_node *node,
+				     struct device_node *parent)
+{
+	int err;
+
+	err = at91_aic_of_common_init(node, parent);
+	if (err)
+		return err;
+
+	at91_aic_hw_init(n_irqs);
+
+	return 0;
+}
+
+int __init at91_aic5_of_init(struct device_node *node,
+				     struct device_node *parent)
+{
+	int err;
+
+	at91_aic_caps |= AT91_AIC_CAP_AIC5;
+	n_irqs = NR_AIC5_IRQS;
+	at91_aic_chip.irq_ack           = at91_aic5_mask_irq;
+	at91_aic_chip.irq_mask		= at91_aic5_mask_irq;
+	at91_aic_chip.irq_unmask	= at91_aic5_unmask_irq;
+	at91_aic_chip.irq_eoi		= at91_aic5_eoi;
+	at91_aic_irq_ops.map		= at91_aic5_irq_map;
+
+	err = at91_aic_of_common_init(node, parent);
+	if (err)
+		return err;
+
+	at91_aic5_hw_init(n_irqs);
+
+	return 0;
+}
+#endif
+
+/*
+ * Initialize the AIC interrupt controller.
+ */
+void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
+{
+	unsigned int i;
+	int irq_base;
+
+	at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
+				  * sizeof(*at91_extern_irq), GFP_KERNEL);
+
+	if (at91_aic_pm_init() || at91_extern_irq == NULL)
+		panic("Unable to allocate bit maps\n");
+
+	*at91_extern_irq = ext_irq_mask;
+
+	at91_aic_base = ioremap(AT91_AIC, 512);
+	if (!at91_aic_base)
+		panic("Unable to ioremap AIC registers\n");
+
+	/* Add irq domain for AIC */
+	irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
+	if (irq_base < 0) {
+		WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
+		irq_base = 0;
+	}
+	at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
+						irq_base, 0,
+						&irq_domain_simple_ops, NULL);
+
+	if (!at91_aic_domain)
+		panic("Unable to add AIC irq domain\n");
+
+	irq_set_default_host(at91_aic_domain);
+
+	/*
+	 * The IVR is used by macro get_irqnr_and_base to read and verify.
+	 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
+	 */
+	for (i = 0; i < n_irqs; i++) {
+		/* Put hardware irq number in Source Vector Register: */
+		at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
+		/* Active Low interrupt, with the specified priority */
+		at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
+		irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
+		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+	}
+
+	at91_aic_hw_init(n_irqs);
+}
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Thu May 23 04:54:01 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu, 23 May 2013 10:54:01 +0200
Subject: [PATCH for 3.10-rc] ARM: mvebu: Fix bug in coherency fabric low level
 init function
Message-ID: <1369299242-16506-1-git-send-email-gregory.clement@free-electrons.com>

Hello Jason and Andrew,

This a new fix for 3.10-rc coming from Marvell. I wasn't impacted
(until now) by the bug fixed by this commit, but I trust Nadav with
his patch, and I didn't see any flaw in his code. Furthermore, I
applied and tested it and saw no regression.

So please applied it for 3.10-rc and we can also consider to applied
it to 3.8 and 3.9.

Thanks

Nadav Haklai (1):
  ARM: mvebu: Fix bug in coherency fabric low level init function

 arch/arm/mach-mvebu/coherency_ll.S | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

-- 
1.8.1.2



From gregory.clement at free-electrons.com  Thu May 23 04:54:02 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu, 23 May 2013 10:54:02 +0200
Subject: [PATCH] ARM: mvebu: Fix bug in coherency fabric low level init
 function
In-Reply-To: <1369299242-16506-1-git-send-email-gregory.clement@free-electrons.com>
References: <1369299242-16506-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1369299242-16506-2-git-send-email-gregory.clement@free-electrons.com>

From: Nadav Haklai <nadavh at marvell.com>

When adding CPU to the SMP group and enabling the coherency on this
CPU we must protect the register access.
The previous implementation claims to be atomic but doesn't provide
any protection against parallel access to the coherency fabric control
and configuration registers.

This patch fixes this by using the ldrex and strex mechanism.
This method should be used in all accesses to those registers.

[gregory.clement at free-electrons.com: fixed the commit's topic]
Signed-off-by: Nadav Haklai <nadavh at marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mvebu/coherency_ll.S | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391..5476669 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent)
 
 	/* Add CPU to SMP group - Atomic */
 	add	r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
-	ldr	r2, [r3]
+1:
+	ldrex	r2, [r3]
 	orr	r2, r2, r1
-	str	r2, [r3]
+	strex 	r0, r2, [r3]
+	cmp	r0, #0
+	bne 1b
 
 	/* Enable coherency on CPU - Atomic */
-	add	r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET
-	ldr	r2, [r3]
+	add	r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+1:
+	ldrex	r2, [r3]
 	orr	r2, r2, r1
-	str	r2, [r3]
+	strex	r0, r2, [r3]
+	cmp	r0, #0
+	bne 1b
 
 	dsb
 
-- 
1.8.1.2



From arnd at arndb.de  Thu May 23 04:54:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 10:54:10 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>
Message-ID: <201305231054.10735.arnd@arndb.de>

On Thursday 23 May 2013, Geert Uytterhoeven wrote:
> > -config BUG
> > -       bool "BUG() support" if EXPERT
> > -       default y
> > -       help
> > -          Disabling this option eliminates support for BUG and WARN, reducing
> > -          the size of your kernel image and potentially quietly ignoring
> > -          numerous fatal conditions. You should only consider disabling this
> > -          option for embedded systems with no facilities for reporting errors.
> > -          Just say Y.
> 
> ... It's about reducing memory size on devices where you can't show bug or
> warning messages.
> 
> > So need get rid of 'CONFIG_BUG', and let it always enabled everywhere.
> 
> So please keep it.

Agreed. The one annoying property of disabling BUG() support is that it causes
a large number of build warnings since the compiler now has to assume that a lot
of code is reachable when it is normally annotate as unreachable.

When I do "randconfig" tests, I always turn on CONFIG_BUG because of this.

	Arnd


From plagnioj at jcrosoft.com  Thu May 23 04:51:22 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 10:51:22 +0200
Subject: [PATCH 0/3] ARM: at91: move aic driver to drivers/irqchip
In-Reply-To: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
References: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <20130523085122.GF9937@game.jcrosoft.org>

Hi,

	please resend with git format-path -M so see the diff not the copy

Best Regsards,
J.
On 10:49 Thu 23 May     , Boris BREZILLON wrote:
> Hello,
> 
> This patch series move the at91 AIC (Advance Interrupt Controller)
> driver to the irqchip subsystem directory (drivers/irqchip).
> 
> It also make use of IRQCHIP_DECLARE to register irqchip for dt boards
> instead of using the machine specific "init_irq" function.
> 
> Finally it register the arch specific irq handler inside the the init
> functions using set_handle_irq. This way we can remove all the machine
> specific "handle_irq".
> 
> This patch series was tested on kizbox board (sam9g20 SoC) using
> device tree. Could someone test it on other boards (both dt and non dt)?
> 
> Best Regards,
> Boris
> 
> 
> Boris BREZILLON (3):
>   ARM: at91: move at91 aic driver to drivers/irqchip
>   ARM: at91: use IRQCHIP_DECLARE instead of machine specific init_irq
>   ARM: at91: use set_handle_irq instead of machine specific handle_irq
> 
>  arch/arm/mach-at91/Makefile                |    2 +-
>  arch/arm/mach-at91/at91_aic.h              |   99 -----
>  arch/arm/mach-at91/at91rm9200.c            |    2 +-
>  arch/arm/mach-at91/at91sam9260.c           |    2 +-
>  arch/arm/mach-at91/at91sam9261.c           |    2 +-
>  arch/arm/mach-at91/at91sam9263.c           |    2 +-
>  arch/arm/mach-at91/at91sam9g45.c           |    2 +-
>  arch/arm/mach-at91/at91sam9rl.c            |    2 +-
>  arch/arm/mach-at91/at91x40.c               |    2 +-
>  arch/arm/mach-at91/board-1arm.c            |    3 +-
>  arch/arm/mach-at91/board-afeb-9260v1.c     |    3 +-
>  arch/arm/mach-at91/board-cam60.c           |    3 +-
>  arch/arm/mach-at91/board-carmeva.c         |    3 +-
>  arch/arm/mach-at91/board-cpu9krea.c        |    3 +-
>  arch/arm/mach-at91/board-cpuat91.c         |    3 +-
>  arch/arm/mach-at91/board-csb337.c          |    3 +-
>  arch/arm/mach-at91/board-csb637.c          |    3 +-
>  arch/arm/mach-at91/board-dt-rm9200.c       |   15 +-
>  arch/arm/mach-at91/board-dt-sam9.c         |   16 +-
>  arch/arm/mach-at91/board-dt-sama5.c        |   16 +-
>  arch/arm/mach-at91/board-eb01.c            |    4 +-
>  arch/arm/mach-at91/board-eb9200.c          |    4 +-
>  arch/arm/mach-at91/board-ecbat91.c         |    3 +-
>  arch/arm/mach-at91/board-eco920.c          |    3 +-
>  arch/arm/mach-at91/board-flexibity.c       |    3 +-
>  arch/arm/mach-at91/board-foxg20.c          |    3 +-
>  arch/arm/mach-at91/board-gsia18s.c         |    3 +-
>  arch/arm/mach-at91/board-kafa.c            |    3 +-
>  arch/arm/mach-at91/board-kb9202.c          |    3 +-
>  arch/arm/mach-at91/board-pcontrol-g20.c    |    3 +-
>  arch/arm/mach-at91/board-picotux200.c      |    3 +-
>  arch/arm/mach-at91/board-qil-a9260.c       |    3 +-
>  arch/arm/mach-at91/board-rm9200dk.c        |    3 +-
>  arch/arm/mach-at91/board-rm9200ek.c        |    3 +-
>  arch/arm/mach-at91/board-rsi-ews.c         |    4 +-
>  arch/arm/mach-at91/board-sam9-l9260.c      |    3 +-
>  arch/arm/mach-at91/board-sam9260ek.c       |    3 +-
>  arch/arm/mach-at91/board-sam9261ek.c       |    3 +-
>  arch/arm/mach-at91/board-sam9263ek.c       |    3 +-
>  arch/arm/mach-at91/board-sam9g20ek.c       |    4 +-
>  arch/arm/mach-at91/board-sam9m10g45ek.c    |    3 +-
>  arch/arm/mach-at91/board-sam9rlek.c        |    3 +-
>  arch/arm/mach-at91/board-snapper9260.c     |    3 +-
>  arch/arm/mach-at91/board-stamp9g20.c       |    4 +-
>  arch/arm/mach-at91/board-usb-a926x.c       |    5 +-
>  arch/arm/mach-at91/board-yl-9200.c         |    3 +-
>  arch/arm/mach-at91/generic.h               |    5 -
>  arch/arm/mach-at91/include/mach/at91_aic.h |   96 +++++
>  arch/arm/mach-at91/irq.c                   |  547 ---------------------------
>  arch/arm/mach-at91/pm.c                    |    2 +-
>  drivers/irqchip/Makefile                   |    1 +
>  drivers/irqchip/irq-at91.c                 |  557 ++++++++++++++++++++++++++++
>  52 files changed, 706 insertions(+), 773 deletions(-)
>  delete mode 100644 arch/arm/mach-at91/at91_aic.h
>  create mode 100644 arch/arm/mach-at91/include/mach/at91_aic.h
>  delete mode 100644 arch/arm/mach-at91/irq.c
>  create mode 100644 drivers/irqchip/irq-at91.c
> 
> -- 
> 1.7.9.5
> 


From b32955 at freescale.com  Thu May 23 05:02:36 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 17:02:36 +0800
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369298806.527290461@f60.mail.ru>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-2-git-send-email-b32955@freescale.com>
 <1369298806.527290461@f60.mail.ru>
Message-ID: <519DDB2C.5040500@freescale.com>

? 2013?05?23? 16:46, Alexander Shiyan ??:
> Where interrupt is used in the driver?
the driver does not use this interrtupt now, but i am not sure whether 
we use it in
the future.

thanks
Huang Shijie



From b.brezillon at overkiz.com  Thu May 23 04:49:50 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 10:49:50 +0200
Subject: [PATCH 3/3] ARM: at91: use set_handle_irq instead of machine specific
 handle_irq
In-Reply-To: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
References: <1369298990-9826-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369298990-9826-4-git-send-email-b.brezillon@overkiz.com>

From: Boris BREZILLON <brezillonboris at gmail.com>

Set machine specific irq handler using set_handle_irq inside aic init
functions instead of handle_irq pointer from machine_desc.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/board-1arm.c            |    1 -
 arch/arm/mach-at91/board-afeb-9260v1.c     |    1 -
 arch/arm/mach-at91/board-cam60.c           |    1 -
 arch/arm/mach-at91/board-carmeva.c         |    1 -
 arch/arm/mach-at91/board-cpu9krea.c        |    1 -
 arch/arm/mach-at91/board-cpuat91.c         |    1 -
 arch/arm/mach-at91/board-csb337.c          |    1 -
 arch/arm/mach-at91/board-csb637.c          |    1 -
 arch/arm/mach-at91/board-dt-rm9200.c       |    1 -
 arch/arm/mach-at91/board-dt-sam9.c         |    1 -
 arch/arm/mach-at91/board-dt-sama5.c        |    1 -
 arch/arm/mach-at91/board-eb01.c            |    1 -
 arch/arm/mach-at91/board-eb9200.c          |    1 -
 arch/arm/mach-at91/board-ecbat91.c         |    1 -
 arch/arm/mach-at91/board-eco920.c          |    1 -
 arch/arm/mach-at91/board-flexibity.c       |    1 -
 arch/arm/mach-at91/board-foxg20.c          |    1 -
 arch/arm/mach-at91/board-gsia18s.c         |    1 -
 arch/arm/mach-at91/board-kafa.c            |    1 -
 arch/arm/mach-at91/board-kb9202.c          |    1 -
 arch/arm/mach-at91/board-pcontrol-g20.c    |    1 -
 arch/arm/mach-at91/board-picotux200.c      |    1 -
 arch/arm/mach-at91/board-qil-a9260.c       |    1 -
 arch/arm/mach-at91/board-rm9200dk.c        |    1 -
 arch/arm/mach-at91/board-rm9200ek.c        |    1 -
 arch/arm/mach-at91/board-rsi-ews.c         |    1 -
 arch/arm/mach-at91/board-sam9-l9260.c      |    1 -
 arch/arm/mach-at91/board-sam9260ek.c       |    1 -
 arch/arm/mach-at91/board-sam9261ek.c       |    1 -
 arch/arm/mach-at91/board-sam9263ek.c       |    1 -
 arch/arm/mach-at91/board-sam9g20ek.c       |    2 --
 arch/arm/mach-at91/board-sam9m10g45ek.c    |    1 -
 arch/arm/mach-at91/board-sam9rlek.c        |    1 -
 arch/arm/mach-at91/board-snapper9260.c     |    1 -
 arch/arm/mach-at91/board-stamp9g20.c       |    2 --
 arch/arm/mach-at91/board-usb-a926x.c       |    3 ---
 arch/arm/mach-at91/board-yl-9200.c         |    1 -
 arch/arm/mach-at91/include/mach/at91_aic.h |    3 ---
 drivers/irqchip/irq-at91.c                 |    6 ++++++
 39 files changed, 6 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 8037dfe..33366d04 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -92,7 +92,6 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
 	/* Maintainer: Lennert Buytenhek <buytenh at wantstofly.org> */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= onearm_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= onearm_board_init,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 28bea23..c2026ff 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -212,7 +212,6 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board")
 	/* Maintainer: Sergey Lapin <slapin at ossfans.org> */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= afeb9260_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= afeb9260_board_init,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 6ebdf32..64deb3d 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -189,7 +189,6 @@ MACHINE_START(CAM60, "KwikByte CAM60")
 	/* Maintainer: KwikByte */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cam60_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cam60_board_init,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 842db49..6c4a243 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -159,7 +159,6 @@ MACHINE_START(CARMEVA, "Carmeva")
 	/* Maintainer: Conitec Datasystems */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= carmeva_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= carmeva_board_init,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 4714e9e..80c5a94 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -376,7 +376,6 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 	/* Maintainer: Eric Benard - EUKREA Electromatique */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cpu9krea_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cpu9krea_board_init,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index c1663ed..d91ec57 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -180,7 +180,6 @@ MACHINE_START(CPUAT91, "Eukrea")
 	/* Maintainer: Eric Benard - EUKREA Electromatique */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cpuat91_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cpuat91_board_init,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 3231703..f660331 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -253,7 +253,6 @@ MACHINE_START(CSB337, "Cogent CSB337")
 	/* Maintainer: Bill Gatliff */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= csb337_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= csb337_board_init,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index d58c7e6..27ce1ce 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -134,7 +134,6 @@ MACHINE_START(CSB637, "Cogent CSB637")
 	/* Maintainer: Bill Gatliff */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= csb637_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= csb637_board_init,
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 523a9ae..72a0658 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -40,7 +40,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.init_time      = at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91rm9200_dt_initialize,
 	.init_machine	= at91rm9200_dt_device_init,
 	.dt_compat	= at91rm9200_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index a07da3b..404a45c 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -41,7 +41,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91_dt_initialize,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 65cf099..68619a8 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -68,7 +68,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic5_handle_irq,
 	.init_early	= at91_dt_initialize,
 	.init_machine	= sama5_dt_device_init,
 	.dt_compat	= sama5_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 4097ede..6159ba1 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -46,7 +46,6 @@ static void __init at91eb01_init_early(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
 	/* Maintainer: Greg Ungerer <gerg at snapgear.com> */
 	.init_time	= at91x40_timer_init,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91eb01_init_early,
 	.init_irq	= at91eb01_init_irq,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index afa5ebb..f1459c5 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -119,7 +119,6 @@ static void __init eb9200_board_init(void)
 MACHINE_START(ATEB9200, "Embest ATEB9200")
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= eb9200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= eb9200_board_init,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index c794768..38e4fec 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -183,7 +183,6 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
 	/* Maintainer: emQbit.com */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ecb_at91init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ecb_at91board_init,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index fc3e373..f89904f 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -151,7 +151,6 @@ MACHINE_START(ECO920, "eco920")
 	/* Maintainer: Sascha Hauer */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= eco920_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= eco920_board_init,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 59a1958..090b17a 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -161,7 +161,6 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect")
 	/* Maintainer: Maxim Osipov */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= flexibity_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= flexibity_board_init,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 4b4df05..6c90394 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -264,7 +264,6 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
 	/* Maintainer: Sergio Tanzilli */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= foxg20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= foxg20_board_init,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 1babcbd..07ebfd3 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -576,7 +576,6 @@ static void __init gsia18s_board_init(void)
 MACHINE_START(GSIA18S, "GS_IA18_S")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= gsia18s_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= gsia18s_board_init,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index aca52d3..82d2113 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -105,7 +105,6 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA")
 	/* Maintainer: Sergei Sharonov */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= kafa_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= kafa_board_init,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 7768df0..3a2040f 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -151,7 +151,6 @@ MACHINE_START(KB9200, "KB920x")
 	/* Maintainer: KwikByte, Inc. */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= kb9202_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= kb9202_board_init,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 6df21db..0df7d60 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -219,7 +219,6 @@ MACHINE_START(PCONTROL_G20, "PControl G20")
 	/* Maintainer: pgsellmann at portner-elektronik.at */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= pcontrol_g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= pcontrol_g20_board_init,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 566b30c..eada86d 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -121,7 +121,6 @@ MACHINE_START(PICOTUX2XX, "picotux 200")
 	/* Maintainer: Kleinhenz Elektronik GmbH */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= picotux200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= picotux200_board_init,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 0ae5eb1..19096a1 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -259,7 +259,6 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 82f0335e..30b23cc 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -221,7 +221,6 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
 	/* Maintainer: SAN People/Atmel */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= dk_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= dk_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 5e8a4f7..e31b069 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -188,7 +188,6 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
 	/* Maintainer: SAN People/Atmel */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index e7d0a69..5fc429b 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -225,7 +225,6 @@ MACHINE_START(RSI_EWS, "RSI EWS")
 	/* Maintainer: Josef Holzmayr <holzmayr at rsi-elektrotechnik.de> */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= rsi_ews_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= rsi_ews_board_init,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 2e400cd..d2e1d70 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -220,7 +220,6 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
 	/* Maintainer: Olimex */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 66ee7ac..a7b2e65 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -345,7 +345,6 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 515957e..3971f1d 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -614,7 +614,6 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 1099272..3530eff 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -445,7 +445,6 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 9fe718b..154f71e 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -411,7 +411,6 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -421,7 +420,6 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 1846647..d87ffb5 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -504,7 +504,6 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 623f2d1..1a0737a 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -322,7 +322,6 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 8fef38a..2c1cfeb 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -179,7 +179,6 @@ static void __init snapper9260_board_init(void)
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= snapper9260_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= snapper9260_board_init,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 6bda942..9ded44b 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -275,7 +275,6 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
 	/* Maintainer: taskit GmbH */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= stamp9g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= portuxg20_board_init,
@@ -285,7 +284,6 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
 	/* Maintainer: taskit GmbH */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= stamp9g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= stamp9g20evb_board_init,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index cedbc66..b51978a 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -357,7 +357,6 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -367,7 +366,6 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -377,7 +375,6 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
 	/* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index c61d8c9..874a6b7 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -589,7 +589,6 @@ MACHINE_START(YL9200, "uCdragon YL-9200")
 	/* Maintainer: S.Birtles */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= yl9200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= yl9200_board_init,
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index eaea661..be8680d 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -93,7 +93,4 @@ extern void __iomem *at91_aic_base;
 #define AT91_AIC_FFSR		0x148			/* Fast Forcing Status Register [SAM9 only] */
 #define AT91_AIC5_FFSR		0x58			/* Fast Forcing Status Register [AIC5] */
 
-void at91_aic_handle_irq(struct pt_regs *regs);
-void at91_aic5_handle_irq(struct pt_regs *regs);
-
 #endif
diff --git a/drivers/irqchip/irq-at91.c b/drivers/irqchip/irq-at91.c
index b45fe2c..d20053f 100644
--- a/drivers/irqchip/irq-at91.c
+++ b/drivers/irqchip/irq-at91.c
@@ -471,6 +471,8 @@ int __init at91_aic_of_init(struct device_node *node,
 
 	at91_aic_hw_init(n_irqs);
 
+	set_handle_irq(at91_aic_handle_irq);
+
 	return 0;
 }
 IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", at91_aic_of_init);
@@ -494,6 +496,8 @@ int __init at91_aic5_of_init(struct device_node *node,
 
 	at91_aic5_hw_init(n_irqs);
 
+	set_handle_irq(at91_aic5_handle_irq);
+
 	return 0;
 }
 IRQCHIP_DECLARE(sama5d3_aic, "atmel,sama5d3-aic", at91_aic5_of_init);
@@ -548,4 +552,6 @@ void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
 	}
 
 	at91_aic_hw_init(n_irqs);
+
+	set_handle_irq(at91_aic_handle_irq);
 }
-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 05:05:06 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 11:05:06 +0200
Subject: [RESEND PATCH 0/3] ARM: at91: move aic driver to drivers/irqchip
Message-ID: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>

Hello,

Sorry for the resend. This version is made using git format-patch -M.

This patch series move the at91 AIC (Advance Interrupt Controller)
driver to the irqchip subsystem directory (drivers/irqchip).

It also make use of IRQCHIP_DECLARE to register irqchip for dt boards
instead of using the machine specific "init_irq" function.

Finally it register the arch specific irq handler inside the the init
functions using set_handle_irq. This way we can remove all the machine
specific "handle_irq".

This patch series was tested on kizbox board (sam9g20 SoC) using
device tree. Could someone test it on other boards (both dt and non dt)?

Best Regards,
Boris

Boris BREZILLON (3):
  ARM: at91: move at91 aic driver to drivers/irqchip
  ARM: at91: use IRQCHIP_DECLARE instead of machine specific init_irq
  ARM: at91: use set_handle_irq instead of machine specific handle_irq

 arch/arm/mach-at91/Makefile                        |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |    2 +-
 arch/arm/mach-at91/at91sam9261.c                   |    2 +-
 arch/arm/mach-at91/at91sam9263.c                   |    2 +-
 arch/arm/mach-at91/at91sam9g45.c                   |    2 +-
 arch/arm/mach-at91/at91sam9rl.c                    |    2 +-
 arch/arm/mach-at91/at91x40.c                       |    2 +-
 arch/arm/mach-at91/board-1arm.c                    |    3 +--
 arch/arm/mach-at91/board-afeb-9260v1.c             |    3 +--
 arch/arm/mach-at91/board-cam60.c                   |    3 +--
 arch/arm/mach-at91/board-carmeva.c                 |    3 +--
 arch/arm/mach-at91/board-cpu9krea.c                |    3 +--
 arch/arm/mach-at91/board-cpuat91.c                 |    3 +--
 arch/arm/mach-at91/board-csb337.c                  |    3 +--
 arch/arm/mach-at91/board-csb637.c                  |    3 +--
 arch/arm/mach-at91/board-dt-rm9200.c               |   15 ++-------------
 arch/arm/mach-at91/board-dt-sam9.c                 |   16 ++--------------
 arch/arm/mach-at91/board-dt-sama5.c                |   16 ++--------------
 arch/arm/mach-at91/board-eb01.c                    |    4 ++--
 arch/arm/mach-at91/board-eb9200.c                  |    4 ++--
 arch/arm/mach-at91/board-ecbat91.c                 |    3 +--
 arch/arm/mach-at91/board-eco920.c                  |    3 +--
 arch/arm/mach-at91/board-flexibity.c               |    3 +--
 arch/arm/mach-at91/board-foxg20.c                  |    3 +--
 arch/arm/mach-at91/board-gsia18s.c                 |    3 +--
 arch/arm/mach-at91/board-kafa.c                    |    3 +--
 arch/arm/mach-at91/board-kb9202.c                  |    3 +--
 arch/arm/mach-at91/board-pcontrol-g20.c            |    3 +--
 arch/arm/mach-at91/board-picotux200.c              |    3 +--
 arch/arm/mach-at91/board-qil-a9260.c               |    3 +--
 arch/arm/mach-at91/board-rm9200dk.c                |    3 +--
 arch/arm/mach-at91/board-rm9200ek.c                |    3 +--
 arch/arm/mach-at91/board-rsi-ews.c                 |    4 ++--
 arch/arm/mach-at91/board-sam9-l9260.c              |    3 +--
 arch/arm/mach-at91/board-sam9260ek.c               |    3 +--
 arch/arm/mach-at91/board-sam9261ek.c               |    3 +--
 arch/arm/mach-at91/board-sam9263ek.c               |    3 +--
 arch/arm/mach-at91/board-sam9g20ek.c               |    4 +---
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    3 +--
 arch/arm/mach-at91/board-sam9rlek.c                |    3 +--
 arch/arm/mach-at91/board-snapper9260.c             |    3 +--
 arch/arm/mach-at91/board-stamp9g20.c               |    4 +---
 arch/arm/mach-at91/board-usb-a926x.c               |    5 +----
 arch/arm/mach-at91/board-yl-9200.c                 |    3 +--
 arch/arm/mach-at91/generic.h                       |    5 -----
 arch/arm/mach-at91/{ => include/mach}/at91_aic.h   |    3 ---
 arch/arm/mach-at91/pm.c                            |    2 +-
 drivers/irqchip/Makefile                           |    1 +
 .../mach-at91/irq.c => drivers/irqchip/irq-at91.c  |   12 +++++++++++-
 50 files changed, 64 insertions(+), 131 deletions(-)
 rename arch/arm/mach-at91/{ => include/mach}/at91_aic.h (97%)
 rename arch/arm/mach-at91/irq.c => drivers/irqchip/irq-at91.c (97%)

-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 05:05:09 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 11:05:09 +0200
Subject: [PATCH 3/3] ARM: at91: use set_handle_irq instead of machine specific
 handle_irq
In-Reply-To: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369299909-10078-4-git-send-email-b.brezillon@overkiz.com>

Set machine specific irq handler using set_handle_irq inside aic init functions
instead of handle_irq pointer from machine_desc.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/board-1arm.c            |    1 -
 arch/arm/mach-at91/board-afeb-9260v1.c     |    1 -
 arch/arm/mach-at91/board-cam60.c           |    1 -
 arch/arm/mach-at91/board-carmeva.c         |    1 -
 arch/arm/mach-at91/board-cpu9krea.c        |    1 -
 arch/arm/mach-at91/board-cpuat91.c         |    1 -
 arch/arm/mach-at91/board-csb337.c          |    1 -
 arch/arm/mach-at91/board-csb637.c          |    1 -
 arch/arm/mach-at91/board-dt-rm9200.c       |    1 -
 arch/arm/mach-at91/board-dt-sam9.c         |    1 -
 arch/arm/mach-at91/board-dt-sama5.c        |    1 -
 arch/arm/mach-at91/board-eb01.c            |    1 -
 arch/arm/mach-at91/board-eb9200.c          |    1 -
 arch/arm/mach-at91/board-ecbat91.c         |    1 -
 arch/arm/mach-at91/board-eco920.c          |    1 -
 arch/arm/mach-at91/board-flexibity.c       |    1 -
 arch/arm/mach-at91/board-foxg20.c          |    1 -
 arch/arm/mach-at91/board-gsia18s.c         |    1 -
 arch/arm/mach-at91/board-kafa.c            |    1 -
 arch/arm/mach-at91/board-kb9202.c          |    1 -
 arch/arm/mach-at91/board-pcontrol-g20.c    |    1 -
 arch/arm/mach-at91/board-picotux200.c      |    1 -
 arch/arm/mach-at91/board-qil-a9260.c       |    1 -
 arch/arm/mach-at91/board-rm9200dk.c        |    1 -
 arch/arm/mach-at91/board-rm9200ek.c        |    1 -
 arch/arm/mach-at91/board-rsi-ews.c         |    1 -
 arch/arm/mach-at91/board-sam9-l9260.c      |    1 -
 arch/arm/mach-at91/board-sam9260ek.c       |    1 -
 arch/arm/mach-at91/board-sam9261ek.c       |    1 -
 arch/arm/mach-at91/board-sam9263ek.c       |    1 -
 arch/arm/mach-at91/board-sam9g20ek.c       |    2 --
 arch/arm/mach-at91/board-sam9m10g45ek.c    |    1 -
 arch/arm/mach-at91/board-sam9rlek.c        |    1 -
 arch/arm/mach-at91/board-snapper9260.c     |    1 -
 arch/arm/mach-at91/board-stamp9g20.c       |    2 --
 arch/arm/mach-at91/board-usb-a926x.c       |    3 ---
 arch/arm/mach-at91/board-yl-9200.c         |    1 -
 arch/arm/mach-at91/include/mach/at91_aic.h |    3 ---
 drivers/irqchip/irq-at91.c                 |    6 ++++++
 39 files changed, 6 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 8037dfe..33366d04 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -92,7 +92,6 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
 	/* Maintainer: Lennert Buytenhek <buytenh at wantstofly.org> */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= onearm_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= onearm_board_init,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 28bea23..c2026ff 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -212,7 +212,6 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board")
 	/* Maintainer: Sergey Lapin <slapin at ossfans.org> */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= afeb9260_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= afeb9260_board_init,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 6ebdf32..64deb3d 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -189,7 +189,6 @@ MACHINE_START(CAM60, "KwikByte CAM60")
 	/* Maintainer: KwikByte */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cam60_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cam60_board_init,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 842db49..6c4a243 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -159,7 +159,6 @@ MACHINE_START(CARMEVA, "Carmeva")
 	/* Maintainer: Conitec Datasystems */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= carmeva_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= carmeva_board_init,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 4714e9e..80c5a94 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -376,7 +376,6 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 	/* Maintainer: Eric Benard - EUKREA Electromatique */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cpu9krea_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cpu9krea_board_init,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index c1663ed..d91ec57 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -180,7 +180,6 @@ MACHINE_START(CPUAT91, "Eukrea")
 	/* Maintainer: Eric Benard - EUKREA Electromatique */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cpuat91_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cpuat91_board_init,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 3231703..f660331 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -253,7 +253,6 @@ MACHINE_START(CSB337, "Cogent CSB337")
 	/* Maintainer: Bill Gatliff */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= csb337_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= csb337_board_init,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index d58c7e6..27ce1ce 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -134,7 +134,6 @@ MACHINE_START(CSB637, "Cogent CSB637")
 	/* Maintainer: Bill Gatliff */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= csb637_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= csb637_board_init,
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 523a9ae..72a0658 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -40,7 +40,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.init_time      = at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91rm9200_dt_initialize,
 	.init_machine	= at91rm9200_dt_device_init,
 	.dt_compat	= at91rm9200_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index a07da3b..404a45c 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -41,7 +41,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91_dt_initialize,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 65cf099..68619a8 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -68,7 +68,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic5_handle_irq,
 	.init_early	= at91_dt_initialize,
 	.init_machine	= sama5_dt_device_init,
 	.dt_compat	= sama5_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 4097ede..6159ba1 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -46,7 +46,6 @@ static void __init at91eb01_init_early(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
 	/* Maintainer: Greg Ungerer <gerg at snapgear.com> */
 	.init_time	= at91x40_timer_init,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91eb01_init_early,
 	.init_irq	= at91eb01_init_irq,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index afa5ebb..f1459c5 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -119,7 +119,6 @@ static void __init eb9200_board_init(void)
 MACHINE_START(ATEB9200, "Embest ATEB9200")
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= eb9200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= eb9200_board_init,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index c794768..38e4fec 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -183,7 +183,6 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
 	/* Maintainer: emQbit.com */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ecb_at91init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ecb_at91board_init,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index fc3e373..f89904f 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -151,7 +151,6 @@ MACHINE_START(ECO920, "eco920")
 	/* Maintainer: Sascha Hauer */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= eco920_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= eco920_board_init,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 59a1958..090b17a 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -161,7 +161,6 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect")
 	/* Maintainer: Maxim Osipov */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= flexibity_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= flexibity_board_init,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 4b4df05..6c90394 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -264,7 +264,6 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
 	/* Maintainer: Sergio Tanzilli */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= foxg20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= foxg20_board_init,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 1babcbd..07ebfd3 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -576,7 +576,6 @@ static void __init gsia18s_board_init(void)
 MACHINE_START(GSIA18S, "GS_IA18_S")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= gsia18s_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= gsia18s_board_init,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index aca52d3..82d2113 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -105,7 +105,6 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA")
 	/* Maintainer: Sergei Sharonov */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= kafa_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= kafa_board_init,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 7768df0..3a2040f 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -151,7 +151,6 @@ MACHINE_START(KB9200, "KB920x")
 	/* Maintainer: KwikByte, Inc. */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= kb9202_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= kb9202_board_init,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 6df21db..0df7d60 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -219,7 +219,6 @@ MACHINE_START(PCONTROL_G20, "PControl G20")
 	/* Maintainer: pgsellmann at portner-elektronik.at */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= pcontrol_g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= pcontrol_g20_board_init,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 566b30c..eada86d 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -121,7 +121,6 @@ MACHINE_START(PICOTUX2XX, "picotux 200")
 	/* Maintainer: Kleinhenz Elektronik GmbH */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= picotux200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= picotux200_board_init,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 0ae5eb1..19096a1 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -259,7 +259,6 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 82f0335e..30b23cc 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -221,7 +221,6 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
 	/* Maintainer: SAN People/Atmel */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= dk_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= dk_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 5e8a4f7..e31b069 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -188,7 +188,6 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
 	/* Maintainer: SAN People/Atmel */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index e7d0a69..5fc429b 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -225,7 +225,6 @@ MACHINE_START(RSI_EWS, "RSI EWS")
 	/* Maintainer: Josef Holzmayr <holzmayr at rsi-elektrotechnik.de> */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= rsi_ews_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= rsi_ews_board_init,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 2e400cd..d2e1d70 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -220,7 +220,6 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
 	/* Maintainer: Olimex */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 66ee7ac..a7b2e65 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -345,7 +345,6 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 515957e..3971f1d 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -614,7 +614,6 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 1099272..3530eff 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -445,7 +445,6 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 9fe718b..154f71e 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -411,7 +411,6 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -421,7 +420,6 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 1846647..d87ffb5 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -504,7 +504,6 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 623f2d1..1a0737a 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -322,7 +322,6 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 8fef38a..2c1cfeb 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -179,7 +179,6 @@ static void __init snapper9260_board_init(void)
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= snapper9260_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= snapper9260_board_init,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 6bda942..9ded44b 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -275,7 +275,6 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
 	/* Maintainer: taskit GmbH */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= stamp9g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= portuxg20_board_init,
@@ -285,7 +284,6 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
 	/* Maintainer: taskit GmbH */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= stamp9g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= stamp9g20evb_board_init,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index cedbc66..b51978a 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -357,7 +357,6 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -367,7 +366,6 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -377,7 +375,6 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
 	/* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index c61d8c9..874a6b7 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -589,7 +589,6 @@ MACHINE_START(YL9200, "uCdragon YL-9200")
 	/* Maintainer: S.Birtles */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= yl9200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= yl9200_board_init,
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index eaea661..be8680d 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -93,7 +93,4 @@ extern void __iomem *at91_aic_base;
 #define AT91_AIC_FFSR		0x148			/* Fast Forcing Status Register [SAM9 only] */
 #define AT91_AIC5_FFSR		0x58			/* Fast Forcing Status Register [AIC5] */
 
-void at91_aic_handle_irq(struct pt_regs *regs);
-void at91_aic5_handle_irq(struct pt_regs *regs);
-
 #endif
diff --git a/drivers/irqchip/irq-at91.c b/drivers/irqchip/irq-at91.c
index b45fe2c..d20053f 100644
--- a/drivers/irqchip/irq-at91.c
+++ b/drivers/irqchip/irq-at91.c
@@ -471,6 +471,8 @@ int __init at91_aic_of_init(struct device_node *node,
 
 	at91_aic_hw_init(n_irqs);
 
+	set_handle_irq(at91_aic_handle_irq);
+
 	return 0;
 }
 IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", at91_aic_of_init);
@@ -494,6 +496,8 @@ int __init at91_aic5_of_init(struct device_node *node,
 
 	at91_aic5_hw_init(n_irqs);
 
+	set_handle_irq(at91_aic5_handle_irq);
+
 	return 0;
 }
 IRQCHIP_DECLARE(sama5d3_aic, "atmel,sama5d3-aic", at91_aic5_of_init);
@@ -548,4 +552,6 @@ void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
 	}
 
 	at91_aic_hw_init(n_irqs);
+
+	set_handle_irq(at91_aic_handle_irq);
 }
-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 05:05:07 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 11:05:07 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>

Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
Move arch/arm/mach-at91/at91_aic.h to
arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
to header file :
#include "../../arch/arm/mach-at91/at91_aic.h"

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/Makefile                        |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |    2 +-
 arch/arm/mach-at91/at91sam9261.c                   |    2 +-
 arch/arm/mach-at91/at91sam9263.c                   |    2 +-
 arch/arm/mach-at91/at91sam9g45.c                   |    2 +-
 arch/arm/mach-at91/at91sam9rl.c                    |    2 +-
 arch/arm/mach-at91/at91x40.c                       |    2 +-
 arch/arm/mach-at91/board-1arm.c                    |    2 +-
 arch/arm/mach-at91/board-afeb-9260v1.c             |    2 +-
 arch/arm/mach-at91/board-cam60.c                   |    2 +-
 arch/arm/mach-at91/board-carmeva.c                 |    2 +-
 arch/arm/mach-at91/board-cpu9krea.c                |    2 +-
 arch/arm/mach-at91/board-cpuat91.c                 |    2 +-
 arch/arm/mach-at91/board-csb337.c                  |    2 +-
 arch/arm/mach-at91/board-csb637.c                  |    2 +-
 arch/arm/mach-at91/board-dt-rm9200.c               |    3 ++-
 arch/arm/mach-at91/board-dt-sam9.c                 |    3 ++-
 arch/arm/mach-at91/board-dt-sama5.c                |    3 ++-
 arch/arm/mach-at91/board-eb01.c                    |    3 ++-
 arch/arm/mach-at91/board-eb9200.c                  |    3 ++-
 arch/arm/mach-at91/board-ecbat91.c                 |    2 +-
 arch/arm/mach-at91/board-eco920.c                  |    2 +-
 arch/arm/mach-at91/board-flexibity.c               |    2 +-
 arch/arm/mach-at91/board-foxg20.c                  |    2 +-
 arch/arm/mach-at91/board-gsia18s.c                 |    2 +-
 arch/arm/mach-at91/board-kafa.c                    |    2 +-
 arch/arm/mach-at91/board-kb9202.c                  |    2 +-
 arch/arm/mach-at91/board-pcontrol-g20.c            |    2 +-
 arch/arm/mach-at91/board-picotux200.c              |    2 +-
 arch/arm/mach-at91/board-qil-a9260.c               |    2 +-
 arch/arm/mach-at91/board-rm9200dk.c                |    2 +-
 arch/arm/mach-at91/board-rm9200ek.c                |    2 +-
 arch/arm/mach-at91/board-rsi-ews.c                 |    3 ++-
 arch/arm/mach-at91/board-sam9-l9260.c              |    2 +-
 arch/arm/mach-at91/board-sam9260ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9261ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9263ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9g20ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    2 +-
 arch/arm/mach-at91/board-sam9rlek.c                |    2 +-
 arch/arm/mach-at91/board-snapper9260.c             |    2 +-
 arch/arm/mach-at91/board-stamp9g20.c               |    2 +-
 arch/arm/mach-at91/board-usb-a926x.c               |    2 +-
 arch/arm/mach-at91/board-yl-9200.c                 |    2 +-
 arch/arm/mach-at91/{ => include/mach}/at91_aic.h   |    0
 arch/arm/mach-at91/pm.c                            |    2 +-
 drivers/irqchip/Makefile                           |    1 +
 .../mach-at91/irq.c => drivers/irqchip/irq-at91.c  |    2 +-
 49 files changed, 54 insertions(+), 47 deletions(-)

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562d..5333701 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y		:= irq.o gpio.o setup.o
+obj-y		:= gpio.o setup.o
 obj-m		:=
 obj-n		:=
 obj-		:=
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..6c1204a 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -20,8 +20,8 @@
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a8ce245..55332fa 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -21,8 +21,8 @@
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 25efb5a..6db61e6 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -20,8 +20,8 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f44ffd2..b9ec043 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -19,8 +19,8 @@
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..1270707 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,8 +20,8 @@
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f77fae5..d5f77d6 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -20,8 +20,8 @@
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 19ca793..e8b30fb 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -20,8 +20,8 @@
 #include <mach/at91x40.h>
 #include <mach/at91_st.h>
 #include <mach/timex.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632..8037dfe 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/at91_aic.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31c..28bea23 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -42,8 +42,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index ade948b..6ebdf32 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -39,8 +39,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 9298305..842db49 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -35,8 +35,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527e..4714e9e 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,8 +43,8 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..c1663ed 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -39,8 +39,8 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215..3231703 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -38,8 +38,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf1106..d58c7e6 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -35,8 +35,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb662..0c2a06d 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -22,7 +22,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "generic.h"
 
 
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db3013..ac899d8 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,7 +21,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..43b8f7a 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -23,7 +23,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "generic.h"
 
 
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index becf0a6..4097ede 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -28,7 +28,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be816..afa5ebb 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -35,7 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71..c794768 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -38,8 +38,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..fc3e373 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -27,8 +27,8 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c085..59a1958 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -33,8 +33,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870..4b4df05 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -42,8 +42,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d2..1babcbd 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -31,8 +31,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d..aca52d3 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -35,8 +35,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..7768df0 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,8 +38,8 @@
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b..6df21db 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -30,8 +30,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..566b30c 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,8 +39,8 @@
 
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index aa3bc9b..0ae5eb1 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -41,8 +41,8 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 690541b..82f0335e 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,8 +41,8 @@
 #include <mach/hardware.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..5e8a4f7 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,8 +41,8 @@
 #include <mach/hardware.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f19..e7d0a69 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -28,7 +28,8 @@
 
 #include <linux/gpio.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
+
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc..2e400cd 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -38,8 +38,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0b153c8..66ee7ac 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -43,8 +43,8 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b446645..515957e 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -47,8 +47,8 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 3284df0..1099272 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -46,8 +46,8 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2..9fe718b 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -45,8 +45,8 @@
 
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 2a94896..1846647 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -44,8 +44,8 @@
 
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index aa265dc..623f2d1 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -31,9 +31,9 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa978..8fef38a 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -33,8 +33,8 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbec..6bda942 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -26,8 +26,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 2487d94..cedbc66 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -42,8 +42,8 @@
 
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..c61d8c9 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -46,8 +46,8 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
similarity index 100%
rename from arch/arm/mach-at91/at91_aic.h
rename to arch/arm/mach-at91/include/mach/at91_aic.h
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 530db30..d2a24e8 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -26,9 +26,9 @@
 #include <asm/mach/irq.h>
 
 #include <mach/at91_pmc.h>
+#include <mach/at91_aic.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 #include "pm.h"
 
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5..208b708 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
+obj-$(CONFIG_ARCH_AT91)			+= irq-at91.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
diff --git a/arch/arm/mach-at91/irq.c b/drivers/irqchip/irq-at91.c
similarity index 99%
rename from arch/arm/mach-at91/irq.c
rename to drivers/irqchip/irq-at91.c
index e0ca591..daf2959 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/drivers/irqchip/irq-at91.c
@@ -42,7 +42,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include "at91_aic.h"
+#include <mach/at91_aic.h>
 
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 05:05:08 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 11:05:08 +0200
Subject: [PATCH 2/3] ARM: at91: use IRQCHIP_DECLARE instead of machine
 specific init_irq
In-Reply-To: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369299909-10078-3-git-send-email-b.brezillon@overkiz.com>

Replace machine specific init_irq functions with IRQCHIP_DECLARE.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/board-dt-rm9200.c |   11 -----------
 arch/arm/mach-at91/board-dt-sam9.c   |   12 ------------
 arch/arm/mach-at91/board-dt-sama5.c  |   12 ------------
 arch/arm/mach-at91/generic.h         |    5 -----
 drivers/irqchip/irq-at91.c           |    4 ++++
 5 files changed, 4 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 0c2a06d..523a9ae 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -27,16 +27,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91rm9200_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static void __init at91rm9200_dt_device_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -52,7 +42,6 @@ DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.map_io		= at91_map_io,
 	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91rm9200_dt_initialize,
-	.init_irq	= at91rm9200_dt_init_irq,
 	.init_machine	= at91rm9200_dt_device_init,
 	.dt_compat	= at91rm9200_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index ac899d8..a07da3b 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -27,17 +27,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static void __init at91_dt_device_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -54,7 +43,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	.map_io		= at91_map_io,
 	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 43b8f7a..65cf099 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -28,17 +28,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
 	int value;
@@ -81,7 +70,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	.map_io		= at91_map_io,
 	.handle_irq	= at91_aic5_handle_irq,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= sama5_dt_device_init,
 	.dt_compat	= sama5_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..23077cf 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,11 +29,6 @@ extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[],
 				 unsigned int ext_irq_mask);
-extern int  __init at91_aic_of_init(struct device_node *node,
-				    struct device_node *parent);
-extern int  __init at91_aic5_of_init(struct device_node *node,
-				    struct device_node *parent);
-
 
  /* Timer */
 extern void at91rm9200_ioremap_st(u32 addr);
diff --git a/drivers/irqchip/irq-at91.c b/drivers/irqchip/irq-at91.c
index daf2959..b45fe2c 100644
--- a/drivers/irqchip/irq-at91.c
+++ b/drivers/irqchip/irq-at91.c
@@ -44,6 +44,8 @@
 
 #include <mach/at91_aic.h>
 
+#include "irqchip.h"
+
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
 static struct device_node *at91_aic_np;
@@ -471,6 +473,7 @@ int __init at91_aic_of_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", at91_aic_of_init);
 
 int __init at91_aic5_of_init(struct device_node *node,
 				     struct device_node *parent)
@@ -493,6 +496,7 @@ int __init at91_aic5_of_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(sama5d3_aic, "atmel,sama5d3-aic", at91_aic5_of_init);
 #endif
 
 /*
-- 
1.7.9.5



From plagnioj at jcrosoft.com  Thu May 23 05:06:11 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 11:06:11 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
Message-ID: <20130523090611.GG9937@game.jcrosoft.org>

On 11:05 Thu 23 May     , Boris BREZILLON wrote:
> Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
> Move arch/arm/mach-at91/at91_aic.h to
> arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
> to header file :
> #include "../../arch/arm/mach-at91/at91_aic.h"
no we are going to drop arch/arm/mach-at91/include/mach for multi support

arch/arm/mach-at91/include/mach is for removal

Best Regards,
J.
> 
> Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
> ---
>  arch/arm/mach-at91/Makefile                        |    2 +-
>  arch/arm/mach-at91/at91rm9200.c                    |    2 +-
>  arch/arm/mach-at91/at91sam9260.c                   |    2 +-
>  arch/arm/mach-at91/at91sam9261.c                   |    2 +-
>  arch/arm/mach-at91/at91sam9263.c                   |    2 +-
>  arch/arm/mach-at91/at91sam9g45.c                   |    2 +-
>  arch/arm/mach-at91/at91sam9rl.c                    |    2 +-
>  arch/arm/mach-at91/at91x40.c                       |    2 +-
>  arch/arm/mach-at91/board-1arm.c                    |    2 +-
>  arch/arm/mach-at91/board-afeb-9260v1.c             |    2 +-
>  arch/arm/mach-at91/board-cam60.c                   |    2 +-
>  arch/arm/mach-at91/board-carmeva.c                 |    2 +-
>  arch/arm/mach-at91/board-cpu9krea.c                |    2 +-
>  arch/arm/mach-at91/board-cpuat91.c                 |    2 +-
>  arch/arm/mach-at91/board-csb337.c                  |    2 +-
>  arch/arm/mach-at91/board-csb637.c                  |    2 +-
>  arch/arm/mach-at91/board-dt-rm9200.c               |    3 ++-
>  arch/arm/mach-at91/board-dt-sam9.c                 |    3 ++-
>  arch/arm/mach-at91/board-dt-sama5.c                |    3 ++-
>  arch/arm/mach-at91/board-eb01.c                    |    3 ++-
>  arch/arm/mach-at91/board-eb9200.c                  |    3 ++-
>  arch/arm/mach-at91/board-ecbat91.c                 |    2 +-
>  arch/arm/mach-at91/board-eco920.c                  |    2 +-
>  arch/arm/mach-at91/board-flexibity.c               |    2 +-
>  arch/arm/mach-at91/board-foxg20.c                  |    2 +-
>  arch/arm/mach-at91/board-gsia18s.c                 |    2 +-
>  arch/arm/mach-at91/board-kafa.c                    |    2 +-
>  arch/arm/mach-at91/board-kb9202.c                  |    2 +-
>  arch/arm/mach-at91/board-pcontrol-g20.c            |    2 +-
>  arch/arm/mach-at91/board-picotux200.c              |    2 +-
>  arch/arm/mach-at91/board-qil-a9260.c               |    2 +-
>  arch/arm/mach-at91/board-rm9200dk.c                |    2 +-
>  arch/arm/mach-at91/board-rm9200ek.c                |    2 +-
>  arch/arm/mach-at91/board-rsi-ews.c                 |    3 ++-
>  arch/arm/mach-at91/board-sam9-l9260.c              |    2 +-
>  arch/arm/mach-at91/board-sam9260ek.c               |    2 +-
>  arch/arm/mach-at91/board-sam9261ek.c               |    2 +-
>  arch/arm/mach-at91/board-sam9263ek.c               |    2 +-
>  arch/arm/mach-at91/board-sam9g20ek.c               |    2 +-
>  arch/arm/mach-at91/board-sam9m10g45ek.c            |    2 +-
>  arch/arm/mach-at91/board-sam9rlek.c                |    2 +-
>  arch/arm/mach-at91/board-snapper9260.c             |    2 +-
>  arch/arm/mach-at91/board-stamp9g20.c               |    2 +-
>  arch/arm/mach-at91/board-usb-a926x.c               |    2 +-
>  arch/arm/mach-at91/board-yl-9200.c                 |    2 +-
>  arch/arm/mach-at91/{ => include/mach}/at91_aic.h   |    0
>  arch/arm/mach-at91/pm.c                            |    2 +-
>  drivers/irqchip/Makefile                           |    1 +
>  .../mach-at91/irq.c => drivers/irqchip/irq-at91.c  |    2 +-
>  49 files changed, 54 insertions(+), 47 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 788562d..5333701 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -2,7 +2,7 @@
>  # Makefile for the linux kernel.
>  #
>  
> -obj-y		:= irq.o gpio.o setup.o
> +obj-y		:= gpio.o setup.o
>  obj-m		:=
>  obj-n		:=
>  obj-		:=
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index d193a40..6c1204a 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -20,8 +20,8 @@
>  #include <mach/at91_pmc.h>
>  #include <mach/at91_st.h>
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "soc.h"
>  #include "generic.h"
>  #include "clock.h"
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index a8ce245..55332fa 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -21,8 +21,8 @@
>  #include <mach/at91_dbgu.h>
>  #include <mach/at91sam9260.h>
>  #include <mach/at91_pmc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_rstc.h"
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index 25efb5a..6db61e6 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -20,8 +20,8 @@
>  #include <mach/cpu.h>
>  #include <mach/at91sam9261.h>
>  #include <mach/at91_pmc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_rstc.h"
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index f44ffd2..b9ec043 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -19,8 +19,8 @@
>  #include <asm/system_misc.h>
>  #include <mach/at91sam9263.h>
>  #include <mach/at91_pmc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_rstc.h"
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 8b7fce0..1270707 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -20,8 +20,8 @@
>  #include <mach/at91sam9g45.h>
>  #include <mach/at91_pmc.h>
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "soc.h"
>  #include "generic.h"
>  #include "clock.h"
> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
> index f77fae5..d5f77d6 100644
> --- a/arch/arm/mach-at91/at91sam9rl.c
> +++ b/arch/arm/mach-at91/at91sam9rl.c
> @@ -20,8 +20,8 @@
>  #include <mach/at91_dbgu.h>
>  #include <mach/at91sam9rl.h>
>  #include <mach/at91_pmc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_rstc.h"
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
> index 19ca793..e8b30fb 100644
> --- a/arch/arm/mach-at91/at91x40.c
> +++ b/arch/arm/mach-at91/at91x40.c
> @@ -20,8 +20,8 @@
>  #include <mach/at91x40.h>
>  #include <mach/at91_st.h>
>  #include <mach/timex.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "generic.h"
>  
>  /*
> diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
> index 35ab632..8037dfe 100644
> --- a/arch/arm/mach-at91/board-1arm.c
> +++ b/arch/arm/mach-at91/board-1arm.c
> @@ -34,9 +34,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> +#include <mach/at91_aic.h>
>  #include <mach/cpu.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
> index f95e31c..28bea23 100644
> --- a/arch/arm/mach-at91/board-afeb-9260v1.c
> +++ b/arch/arm/mach-at91/board-afeb-9260v1.c
> @@ -42,8 +42,8 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
> index ade948b..6ebdf32 100644
> --- a/arch/arm/mach-at91/board-cam60.c
> +++ b/arch/arm/mach-at91/board-cam60.c
> @@ -39,8 +39,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
> index 9298305..842db49 100644
> --- a/arch/arm/mach-at91/board-carmeva.c
> +++ b/arch/arm/mach-at91/board-carmeva.c
> @@ -35,8 +35,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/hardware.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
> index 008527e..4714e9e 100644
> --- a/arch/arm/mach-at91/board-cpu9krea.c
> +++ b/arch/arm/mach-at91/board-cpu9krea.c
> @@ -43,8 +43,8 @@
>  #include <mach/at91sam9_smc.h>
>  #include <mach/at91sam9260_matrix.h>
>  #include <mach/at91_matrix.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
> index 42f1353..c1663ed 100644
> --- a/arch/arm/mach-at91/board-cpuat91.c
> +++ b/arch/arm/mach-at91/board-cpuat91.c
> @@ -39,8 +39,8 @@
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
> index e5fde215..3231703 100644
> --- a/arch/arm/mach-at91/board-csb337.c
> +++ b/arch/arm/mach-at91/board-csb337.c
> @@ -38,8 +38,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/hardware.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
> index fdf1106..d58c7e6 100644
> --- a/arch/arm/mach-at91/board-csb637.c
> +++ b/arch/arm/mach-at91/board-csb637.c
> @@ -35,8 +35,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/hardware.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
> index 3fcb662..0c2a06d 100644
> --- a/arch/arm/mach-at91/board-dt-rm9200.c
> +++ b/arch/arm/mach-at91/board-dt-rm9200.c
> @@ -22,7 +22,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
> +
>  #include "generic.h"
>  
>  
> diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
> index 8db3013..ac899d8 100644
> --- a/arch/arm/mach-at91/board-dt-sam9.c
> +++ b/arch/arm/mach-at91/board-dt-sam9.c
> @@ -21,7 +21,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
> +
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> index 705305e..43b8f7a 100644
> --- a/arch/arm/mach-at91/board-dt-sama5.c
> +++ b/arch/arm/mach-at91/board-dt-sama5.c
> @@ -23,7 +23,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
> +
>  #include "generic.h"
>  
>  
> diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
> index becf0a6..4097ede 100644
> --- a/arch/arm/mach-at91/board-eb01.c
> +++ b/arch/arm/mach-at91/board-eb01.c
> @@ -28,7 +28,8 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
> +
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
> index f9be816..afa5ebb 100644
> --- a/arch/arm/mach-at91/board-eb9200.c
> +++ b/arch/arm/mach-at91/board-eb9200.c
> @@ -35,7 +35,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
> +
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
> index b2fcd71..c794768 100644
> --- a/arch/arm/mach-at91/board-ecbat91.c
> +++ b/arch/arm/mach-at91/board-ecbat91.c
> @@ -38,8 +38,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
> index 77de410..fc3e373 100644
> --- a/arch/arm/mach-at91/board-eco920.c
> +++ b/arch/arm/mach-at91/board-eco920.c
> @@ -27,8 +27,8 @@
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
> index 737c085..59a1958 100644
> --- a/arch/arm/mach-at91/board-flexibity.c
> +++ b/arch/arm/mach-at91/board-flexibity.c
> @@ -33,8 +33,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/hardware.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
> index c20a870..4b4df05 100644
> --- a/arch/arm/mach-at91/board-foxg20.c
> +++ b/arch/arm/mach-at91/board-foxg20.c
> @@ -42,8 +42,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
> index c1d61d2..1babcbd 100644
> --- a/arch/arm/mach-at91/board-gsia18s.c
> +++ b/arch/arm/mach-at91/board-gsia18s.c
> @@ -31,8 +31,8 @@
>  #include <asm/mach/arch.h>
>  
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
> index 88e2f5d..aca52d3 100644
> --- a/arch/arm/mach-at91/board-kafa.c
> +++ b/arch/arm/mach-at91/board-kafa.c
> @@ -35,8 +35,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
> index 0c519d9..7768df0 100644
> --- a/arch/arm/mach-at91/board-kb9202.c
> +++ b/arch/arm/mach-at91/board-kb9202.c
> @@ -38,8 +38,8 @@
>  #include <mach/cpu.h>
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
> index 65c0d6b..6df21db 100644
> --- a/arch/arm/mach-at91/board-pcontrol-g20.c
> +++ b/arch/arm/mach-at91/board-pcontrol-g20.c
> @@ -30,8 +30,8 @@
>  #include <asm/mach/arch.h>
>  
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
> index ab2b2ec..566b30c 100644
> --- a/arch/arm/mach-at91/board-picotux200.c
> +++ b/arch/arm/mach-at91/board-picotux200.c
> @@ -39,8 +39,8 @@
>  
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
> index aa3bc9b..0ae5eb1 100644
> --- a/arch/arm/mach-at91/board-qil-a9260.c
> +++ b/arch/arm/mach-at91/board-qil-a9260.c
> @@ -41,8 +41,8 @@
>  
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
> index 690541b..82f0335e 100644
> --- a/arch/arm/mach-at91/board-rm9200dk.c
> +++ b/arch/arm/mach-at91/board-rm9200dk.c
> @@ -41,8 +41,8 @@
>  #include <mach/hardware.h>
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
> index 8b17dad..5e8a4f7 100644
> --- a/arch/arm/mach-at91/board-rm9200ek.c
> +++ b/arch/arm/mach-at91/board-rm9200ek.c
> @@ -41,8 +41,8 @@
>  #include <mach/hardware.h>
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
> index f6d7f19..e7d0a69 100644
> --- a/arch/arm/mach-at91/board-rsi-ews.c
> +++ b/arch/arm/mach-at91/board-rsi-ews.c
> @@ -28,7 +28,8 @@
>  
>  #include <linux/gpio.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
> +
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
> index 43ee4dc..2e400cd 100644
> --- a/arch/arm/mach-at91/board-sam9-l9260.c
> +++ b/arch/arm/mach-at91/board-sam9-l9260.c
> @@ -38,8 +38,8 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
> index 0b153c8..66ee7ac 100644
> --- a/arch/arm/mach-at91/board-sam9260ek.c
> +++ b/arch/arm/mach-at91/board-sam9260ek.c
> @@ -43,8 +43,8 @@
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
>  #include <mach/system_rev.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
> index b446645..515957e 100644
> --- a/arch/arm/mach-at91/board-sam9261ek.c
> +++ b/arch/arm/mach-at91/board-sam9261ek.c
> @@ -47,8 +47,8 @@
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
>  #include <mach/system_rev.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
> index 3284df0..1099272 100644
> --- a/arch/arm/mach-at91/board-sam9263ek.c
> +++ b/arch/arm/mach-at91/board-sam9263ek.c
> @@ -46,8 +46,8 @@
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
>  #include <mach/system_rev.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
> index f9cd1f2..9fe718b 100644
> --- a/arch/arm/mach-at91/board-sam9g20ek.c
> +++ b/arch/arm/mach-at91/board-sam9g20ek.c
> @@ -45,8 +45,8 @@
>  
>  #include <mach/at91sam9_smc.h>
>  #include <mach/system_rev.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
> index 2a94896..1846647 100644
> --- a/arch/arm/mach-at91/board-sam9m10g45ek.c
> +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
> @@ -44,8 +44,8 @@
>  
>  #include <mach/at91sam9_smc.h>
>  #include <mach/system_rev.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
> index aa265dc..623f2d1 100644
> --- a/arch/arm/mach-at91/board-sam9rlek.c
> +++ b/arch/arm/mach-at91/board-sam9rlek.c
> @@ -31,9 +31,9 @@
>  
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
> index 3aaa978..8fef38a 100644
> --- a/arch/arm/mach-at91/board-snapper9260.c
> +++ b/arch/arm/mach-at91/board-snapper9260.c
> @@ -33,8 +33,8 @@
>  
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
> index 869cbec..6bda942 100644
> --- a/arch/arm/mach-at91/board-stamp9g20.c
> +++ b/arch/arm/mach-at91/board-stamp9g20.c
> @@ -26,8 +26,8 @@
>  #include <asm/mach/arch.h>
>  
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
> index 2487d94..cedbc66 100644
> --- a/arch/arm/mach-at91/board-usb-a926x.c
> +++ b/arch/arm/mach-at91/board-usb-a926x.c
> @@ -42,8 +42,8 @@
>  
>  #include <mach/hardware.h>
>  #include <mach/at91sam9_smc.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "at91_shdwc.h"
>  #include "board.h"
>  #include "sam9_smc.h"
> diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
> index be08377..c61d8c9 100644
> --- a/arch/arm/mach-at91/board-yl-9200.c
> +++ b/arch/arm/mach-at91/board-yl-9200.c
> @@ -46,8 +46,8 @@
>  #include <mach/at91rm9200_mc.h>
>  #include <mach/at91_ramc.h>
>  #include <mach/cpu.h>
> +#include <mach/at91_aic.h>
>  
> -#include "at91_aic.h"
>  #include "board.h"
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
> similarity index 100%
> rename from arch/arm/mach-at91/at91_aic.h
> rename to arch/arm/mach-at91/include/mach/at91_aic.h
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 530db30..d2a24e8 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -26,9 +26,9 @@
>  #include <asm/mach/irq.h>
>  
>  #include <mach/at91_pmc.h>
> +#include <mach/at91_aic.h>
>  #include <mach/cpu.h>
>  
> -#include "at91_aic.h"
>  #include "generic.h"
>  #include "pm.h"
>  
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index cda4cb5..208b708 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_IRQCHIP)			+= irqchip.o
>  
> +obj-$(CONFIG_ARCH_AT91)			+= irq-at91.o
>  obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
>  obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
>  obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
> diff --git a/arch/arm/mach-at91/irq.c b/drivers/irqchip/irq-at91.c
> similarity index 99%
> rename from arch/arm/mach-at91/irq.c
> rename to drivers/irqchip/irq-at91.c
> index e0ca591..daf2959 100644
> --- a/arch/arm/mach-at91/irq.c
> +++ b/drivers/irqchip/irq-at91.c
> @@ -42,7 +42,7 @@
>  #include <asm/mach/irq.h>
>  #include <asm/mach/map.h>
>  
> -#include "at91_aic.h"
> +#include <mach/at91_aic.h>
>  
>  void __iomem *at91_aic_base;
>  static struct irq_domain *at91_aic_domain;
> -- 
> 1.7.9.5
> 


From prabhakar.csengg at gmail.com  Thu May 23 05:10:23 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Thu, 23 May 2013 14:40:23 +0530
Subject: [PATCH 2/6] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>
References: <1368619042-28252-1-git-send-email-prabhakar.csengg@gmail.com>
 <1368619042-28252-3-git-send-email-prabhakar.csengg@gmail.com>
Message-ID: <CA+V-a8vXkH-N=1cCsj2KtXz6Jz3UprNrrbA9w1TN-NrBRHuAog@mail.gmail.com>

Hi Sekhar,

On Wed, May 15, 2013 at 5:27 PM, Lad Prabhakar
<prabhakar.csengg at gmail.com> wrote:
> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>
> remove init_enable from ths7303 pdata as it is no longer exists.
>
Can you please ack this patch, as this patch is intended to go via media tree.

Regards,
--Prabhakar Lad


From linux at arm.linux.org.uk  Thu May 23 05:05:34 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 10:05:34 +0100
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since
 always need it.
In-Reply-To: <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>
Message-ID: <20130523090534.GJ18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 10:40:29AM +0200, Geert Uytterhoeven wrote:
> On Thu, May 23, 2013 at 9:57 AM, Chen Gang <gang.chen at asianux.com> wrote:
> > -config BUG
> > -       bool "BUG() support" if EXPERT
> > -       default y
> > -       help
> > -          Disabling this option eliminates support for BUG and WARN, reducing
> > -          the size of your kernel image and potentially quietly ignoring
> > -          numerous fatal conditions. You should only consider disabling this
> > -          option for embedded systems with no facilities for reporting errors.
> > -          Just say Y.
> 
> ... It's about reducing memory size on devices where you can't show bug or
> warning messages.

And turning off CONFIG_BUG causes lots of warning messages at compile time
about functions which are returning nothing which shouldn't.

The problem is: trying to fix that _will_ mean the result is a larger
kernel than if you just do the usual arch-implemented thing of placing
an defined faulting instruction at the BUG() site - which defeats the
purpose of turning off CONFIG_BUG.

Therefore, it's better that CONFIG_BUG always be y and we stop kidding
ourselves that it's possible to turn this off and safely save space.


From geert at linux-m68k.org  Thu May 23 05:12:56 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 23 May 2013 11:12:56 +0200
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <20130523090534.GJ18614@n2100.arm.linux.org.uk>
References: <519DCBEF.3090208@asianux.com>
 <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
Message-ID: <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>

On Thu, May 23, 2013 at 11:05 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, May 23, 2013 at 10:40:29AM +0200, Geert Uytterhoeven wrote:
>> On Thu, May 23, 2013 at 9:57 AM, Chen Gang <gang.chen at asianux.com> wrote:
>> > -config BUG
>> > -       bool "BUG() support" if EXPERT
>> > -       default y
>> > -       help
>> > -          Disabling this option eliminates support for BUG and WARN, reducing
>> > -          the size of your kernel image and potentially quietly ignoring
>> > -          numerous fatal conditions. You should only consider disabling this
>> > -          option for embedded systems with no facilities for reporting errors.
>> > -          Just say Y.
>>
>> ... It's about reducing memory size on devices where you can't show bug or
>> warning messages.
>
> And turning off CONFIG_BUG causes lots of warning messages at compile time
> about functions which are returning nothing which shouldn't.
>
> The problem is: trying to fix that _will_ mean the result is a larger
> kernel than if you just do the usual arch-implemented thing of placing
> an defined faulting instruction at the BUG() site - which defeats the
> purpose of turning off CONFIG_BUG.

Is __builtin_unreachable() working well these days?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From shc_work at mail.ru  Thu May 23 05:14:00 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 13:14:00 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSCBWMiA0LzZdIEFSTTogZHRzOiBpbXg2cTogYWRkIHBpbmN0?=
 =?UTF-8?B?cmwgZm9yIFdFSU0gTk9S?=
In-Reply-To: <1369296978-7669-5-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-5-git-send-email-b32955@freescale.com>
Message-ID: <1369300440.725629549@f101.mail.ru>

> Add a pinctrl for WEIM nor.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   56 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 56 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..2a6327a 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -323,6 +323,62 @@
>  						>;
>  					};
>  				};
> +
> +				weim {
> +					pinctrl_weim_nor_1: weim_norgrp-1 {

I suggest remove "nor" label here since it can be used for other devices later.

> +						fsl,pins = <
> +							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1

Since driver can support multiple chipselects it would be nice to
define EIM_CSX in other place for possible using other chipselects.

> +							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
> +							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
> +							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
> +
> +							/* data */
> +							MX6Q_PAD_EIM_D16__EIM_DATA16 0xb0b1
> +							MX6Q_PAD_EIM_D17__EIM_DATA17 0xb0b1
> +							MX6Q_PAD_EIM_D18__EIM_DATA18 0xb0b1
> +							MX6Q_PAD_EIM_D19__EIM_DATA19 0xb0b1
> +							MX6Q_PAD_EIM_D20__EIM_DATA20 0xb0b1
> +							MX6Q_PAD_EIM_D21__EIM_DATA21 0xb0b1
> +							MX6Q_PAD_EIM_D22__EIM_DATA22 0xb0b1
> +							MX6Q_PAD_EIM_D23__EIM_DATA23 0xb0b1
> +							MX6Q_PAD_EIM_D24__EIM_DATA24 0xb0b1
> +							MX6Q_PAD_EIM_D25__EIM_DATA25 0xb0b1
> +							MX6Q_PAD_EIM_D26__EIM_DATA26 0xb0b1
> +							MX6Q_PAD_EIM_D27__EIM_DATA27 0xb0b1
> +							MX6Q_PAD_EIM_D28__EIM_DATA28 0xb0b1
> +							MX6Q_PAD_EIM_D29__EIM_DATA29 0xb0b1
> +							MX6Q_PAD_EIM_D30__EIM_DATA30 0xb0b1
> +							MX6Q_PAD_EIM_D31__EIM_DATA31 0xb0b1
> +
> +							/* address */
> +							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
> +							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
> +							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
> +							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
> +							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
> +							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
> +							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
> +							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
> +							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
> +							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
> +							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
> +							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
> +							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
> +							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
> +							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
> +							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
> +							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
> +							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
> +							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
> +							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
> +							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
> +							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
> +							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
> +							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
> +						>;
> +					};
> +
> +				};
>  			};
>  		};
>  
> -- 

---

From s.hauer at pengutronix.de  Thu May 23 05:23:44 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 23 May 2013 11:23:44 +0200
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369296978-7669-2-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-2-git-send-email-b32955@freescale.com>
Message-ID: <20130523092344.GF32299@pengutronix.de>

On Thu, May 23, 2013 at 04:16:13PM +0800, Huang Shijie wrote:
> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
>  drivers/bus/Kconfig                                |    9 ++
>  drivers/bus/Makefile                               |    1 +
>  drivers/bus/imx-weim.c                             |  146 ++++++++++++++++++++
>  4 files changed, 206 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
>  create mode 100644 drivers/bus/imx-weim.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
> new file mode 100644
> index 0000000..3db588e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
> @@ -0,0 +1,50 @@
> +Device tree bindings for i.MX Wireless External Interface Module (WEIM)
> +
> +The term "wireless" does not imply that the WEIM is literally an interface
> +without wires. It simply means that this module was originally designed for
> +wireless and mobile applications that use low-power technology.
> +
> +The actual devices are instantiated from the child nodes of a WEIM node.
> +
> +
> + - compatible:		Should be set to "fsl,imx6q-weim"
> + - reg:			A resource specifier for the register space
> +			(see the example below)
> + - interrupts:		the interrupt number, see the example below.
> + - clocks:		the clock, see the example below.
> + - #address-cells:	Must be set to 2 to allow memory address translation
> + - #size-cells:		Must be set to 1 to allow CS address passing
> + - ranges:		Must be set up to reflect the memory layout with four
> +			integer values for each chip-select line in use:
> +
> +			   <cs-number> 0 <physical address of mapping> <size>
> +
> +Timing property for child nodes. It is mandatory, not optional.
> +
> + - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
> +			child node. We can get the CS index from the child
> +			node's "reg" property.

This should be more detailed, something like:

This contains the values for the registers EIM_CSnGCR1, EIM_CSnGCR2,
EIM_CSnRCR1, EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.

> +static int weim_parse_dt(struct platform_device *pdev)
> +{
> +	struct device_node *child;
> +	int ret;
> +
> +	for_each_child_of_node(pdev->dev.of_node, child) {
> +		if (!child->name)
> +			continue;
> +
> +		ret = weim_timing_setup(pdev, child);
> +		if (ret)
> +			goto parse_fail;
> +
> +		if (!of_platform_device_create(child, NULL, &pdev->dev)) {
> +			ret = -EINVAL;
> +			goto parse_fail;
> +		}

I would print some warning here for the failures in this loop, but I
don't think it's necessary to bail out. No need to make all WEIM devices
fail if one has an erroneous device node.

> +
> +	/* get the resource */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(weim->base)) {
> +		ret = PTR_ERR(weim->base);
> +		goto weim_err;
> +	}
> +
> +	/* get the clock */
> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(weim->clk))
> +		goto weim_err;
> +
> +	clk_prepare_enable(weim->clk);
> +
> +	/* parse the device node */
> +	ret = weim_parse_dt(pdev);
> +	if (ret) {
> +		clk_disable_unprepare(weim->clk);
> +		goto weim_err;
> +	}
> +
> +	dev_info(&pdev->dev, "WEIM driver registered.\n");
> +	return 0;
> +
> +weim_err:
> +	return ret;
> +}
> +
> +static int weim_remove(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(weim->clk);

Once again: Is this clock needed for the child devices? If yes, you
can't disable it here and leave the child devices registered.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From b32955 at freescale.com  Thu May 23 05:27:37 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 17:27:37 +0800
Subject: [PATCH V2 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
In-Reply-To: <1369300440.725629549@f101.mail.ru>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-5-git-send-email-b32955@freescale.com>
 <1369300440.725629549@f101.mail.ru>
Message-ID: <519DE109.1030903@freescale.com>

? 2013?05?23? 17:14, Alexander Shiyan ??:
> I suggest remove "nor" label here since it can be used for other devices later.
this pinctrl is just for NOR.

If we attach other device to WEIM, it maybe needs other PAD, such as

MX6Q_PAD_EIM_LBA__EIM_LBA_B.  We need to add another pinctrl then.



>> >  +						fsl,pins =<
>> >  +							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
> Since driver can support multiple chipselects it would be nice to
> define EIM_CSX in other place for possible using other chipselects.
>
Ditto.

thanks
Huang Shijie




From valentin.longchamp at keymile.com  Thu May 23 05:25:30 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Thu, 23 May 2013 11:25:30 +0200
Subject: [PATCH] ARM: kirkwood: refactor dtsi to largest common nodes
Message-ID: <1369301130-29900-1-git-send-email-valentin.longchamp@keymile.com>

Some kirkwood variants (for instance present in the prestera SoCs) do
not have all the peripherals whose nodes are initialized in the
kirkwood.dtsi. These missing peripherals are SATA, SDIO, and RTC.

Their corresponding nodes are moved from kirkwood.dtsi to the
kirkwood-628x.dtsi files so that they still are initialized for these
variants.

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
---
 arch/arm/boot/dts/kirkwood-6281.dtsi | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-6282.dtsi | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi      | 24 ------------------------
 3 files changed, 48 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65..29f831e 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,29 @@
 				marvell,function = "sdio";
 			};
 		};
+
+		rtc at 10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			status = "disabled";
+		};
+
+		mvsdio at 90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e4..a1c2c05 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,30 @@
 			};
 		};
 
+		rtc at 10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			status = "disabled";
+		};
+
+		mvsdio at 90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			status = "disabled";
+		};
+
 		thermal at 10078 {
 			compatible = "marvell,kirkwood-thermal";
 			reg = <0x10078 0x4>;
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..39f497e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -71,13 +71,6 @@
 			status = "disabled";
 		};
 
-		rtc at 10300 {
-			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
-			reg = <0x10300 0x20>;
-			interrupts = <53>;
-			clocks = <&gate_clk 7>;
-		};
-
 		spi at 10600 {
 			compatible = "marvell,orion-spi";
 			#address-cells = <1>;
@@ -151,15 +144,6 @@
 			status = "okay";
 		};
 
-		sata at 80000 {
-			compatible = "marvell,orion-sata";
-			reg = <0x80000 0x5000>;
-			interrupts = <21>;
-			clocks = <&gate_clk 14>, <&gate_clk 15>;
-			clock-names = "0", "1";
-			status = "disabled";
-		};
-
 		nand at 3000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -194,13 +178,5 @@
 			clocks = <&gate_clk 17>;
 			status = "okay";
 		};
-
-		mvsdio at 90000 {
-			compatible = "marvell,orion-sdio";
-			reg = <0x90000 0x200>;
-			interrupts = <28>;
-			clocks = <&gate_clk 4>;
-			status = "disabled";
-		};
 	};
 };
-- 
1.8.0.1



From b32955 at freescale.com  Thu May 23 05:35:42 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 17:35:42 +0800
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <20130523092344.GF32299@pengutronix.de>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-2-git-send-email-b32955@freescale.com>
 <20130523092344.GF32299@pengutronix.de>
Message-ID: <519DE2EE.1050006@freescale.com>

? 2013?05?23? 17:23, Sascha Hauer ??:
> On Thu, May 23, 2013 at 04:16:13PM +0800, Huang Shijie wrote:
>> +			<cs-number>  0<physical address of mapping>  <size>
>> +
>> +Timing property for child nodes. It is mandatory, not optional.
>> +
>> + - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
>> +			child node. We can get the CS index from the child
>> +			node's "reg" property.
> This should be more detailed, something like:
>
> This contains the values for the registers EIM_CSnGCR1, EIM_CSnGCR2,
> EIM_CSnRCR1, EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
>


do you mean i should add some new properties, such as
"fsl,eim_csnrcr1", "fsl,eim_csnrcr2" ...
>> +static int weim_parse_dt(struct platform_device *pdev)
>> +{
>> +	struct device_node *child;
>> +	int ret;
>> +
>> +	for_each_child_of_node(pdev->dev.of_node, child) {
>> +		if (!child->name)
>> +			continue;
>> +
>> +		ret = weim_timing_setup(pdev, child);
>> +		if (ret)
>> +			goto parse_fail;
>> +
>> +		if (!of_platform_device_create(child, NULL,&pdev->dev)) {
>> +			ret = -EINVAL;
>> +			goto parse_fail;
>> +		}
> I would print some warning here for the failures in this loop, but I
> don't think it's necessary to bail out. No need to make all WEIM devices
> fail if one has an erroneous device node.
>
ok.
>> +
>> +	/* get the resource */
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
>> +	if (IS_ERR(weim->base)) {
>> +		ret = PTR_ERR(weim->base);
>> +		goto weim_err;
>> +	}
>> +
>> +	/* get the clock */
>> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
>> +	if (IS_ERR(weim->clk))
>> +		goto weim_err;
>> +
>> +	clk_prepare_enable(weim->clk);
>> +
>> +	/* parse the device node */
>> +	ret = weim_parse_dt(pdev);
>> +	if (ret) {
>> +		clk_disable_unprepare(weim->clk);
>> +		goto weim_err;
>> +	}
>> +
>> +	dev_info(&pdev->dev, "WEIM driver registered.\n");
>> +	return 0;
>> +
>> +weim_err:
>> +	return ret;
>> +}
>> +
>> +static int weim_remove(struct platform_device *pdev)
>> +{
>> +	struct imx_weim *weim = platform_get_drvdata(pdev);
>> +
>> +	clk_disable_unprepare(weim->clk);
> Once again: Is this clock needed for the child devices? If yes, you
> can't disable it here and leave the child devices registered.
>
again. yes. we need this clock.


thanks
Huang Shijie



From shc_work at mail.ru  Thu May 23 05:39:56 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 13:39:56 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSCBWMiA0LzZdIEFSTTogZHRzOiBpbXg2cTogYWRkIHBp?=
 =?UTF-8?B?bmN0cmwgZm9yIFdFSU0gTk9S?=
In-Reply-To: <519DE109.1030903@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369300440.725629549@f101.mail.ru>
 <519DE109.1030903@freescale.com>
Message-ID: <1369301996.738631947@f310.mail.ru>

> > I suggest remove "nor" label here since it can be used for other devices later.
> this pinctrl is just for NOR.
> 
> If we attach other device to WEIM, it maybe needs other PAD, such as
> MX6Q_PAD_EIM_LBA__EIM_LBA_B. We need to add another pinctrl then.

How we should define CS1 pin in your example for second device?

---

From arnd at arndb.de  Thu May 23 05:39:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 11:39:37 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
Message-ID: <201305231139.38233.arnd@arndb.de>

On Thursday 23 May 2013, Geert Uytterhoeven wrote:
> > The problem is: trying to fix that will mean the result is a larger
> > kernel than if you just do the usual arch-implemented thing of placing
> > an defined faulting instruction at the BUG() site - which defeats the
> > purpose of turning off CONFIG_BUG.
> 
> Is __builtin_unreachable() working well these days?
> 

Hmm, I just tried the trivial patch below, which seemed to do the right thing.
Needs a little more investigation, but that might actually be the correct
solution. I thought that at some point __builtin_unreachable() was the same
as "do {} while (1)", but this is not the case with the gcc I was using --
it just tells gcc that we don't expect to ever get here.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..9afff7d 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -108,11 +108,11 @@ extern void warn_slowpath_null(const char *file, const int line);
 
 #else /* !CONFIG_BUG */
 #ifndef HAVE_ARCH_BUG
-#define BUG() do {} while(0)
+#define BUG() __builtin_unreachable ()
 #endif
 
 #ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
+#define BUG_ON(condition) do { if (condition) __builtin_unreachable(); } while(0)
 #endif
 
 #ifndef HAVE_ARCH_WARN_ON


From ulf.hansson at stericsson.com  Thu May 23 05:45:04 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 11:45:04 +0200
Subject: [PATCH V2 0/3] mmc: mmci: Support ap_sleep in cpuidle for ux500
Message-ID: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

To be able to enter ap_sleep state in cpuidle were the APE power domain
regulator will be cut, a register save and restore mechanism needs to be
implemented. This patchset adapts to these restrictions.

Ulf Hansson (3):
  mmc: mmci: Use optional sleep pinctrl state
  mmc: mmci: Adapt to register write restrictions
  mmc: mmci: Save and restore register context

 drivers/mmc/host/mmci.c |   75 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 76 insertions(+)

-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 05:45:06 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 11:45:06 +0200
Subject: [PATCH V2 2/3] mmc: mmci: Adapt to register write restrictions
In-Reply-To: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369302307-28540-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

After a write to the MMCICLOCK register data cannot be written to this
register for three feedback clock cycles. Writes to the MMCIPOWER
register must be separated by three MCLK cycles. Previously no issues
has been observered, but using higher ARM clock frequencies on STE-
platforms has triggered this problem.

The MMCICLOCK register is written to in .set_ios and for some data
transmissions for SDIO. We do not need a delay at the data transmission
path, because sending and receiving data will require more than three
clock cycles. Then we use a simple logic to only delay in .set_ios and
thus we don't affect throughput performance.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Signed-off-by: Johan Rudholm <jrudholm at gmail.com>
---

Changes in v2:
	None
---
 drivers/mmc/host/mmci.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 9fa8855..8f70e5b 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host,
 	return 0;
 }
 
+static void mmci_reg_delay(struct mmci_host *host)
+{
+	/*
+	 * According to the spec, at least three feedback clock cycles
+	 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
+	 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
+	 * Worst delay time during card init is at 100 kHz => 30 us.
+	 * Worst delay time when up and running is at 25 MHz => 120 ns.
+	 */
+	if (host->cclk < 20000000)
+		udelay(30);
+	else
+		ndelay(120);
+}
+
 /*
  * This must be called with host->lock held
  */
@@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	mmci_set_clkreg(host, ios->clock);
 	mmci_write_pwrreg(host, pwr);
+	mmci_reg_delay(host);
 
 	spin_unlock_irqrestore(&host->lock, flags);
 
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 05:45:05 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 11:45:05 +0200
Subject: [PATCH V2 1/3] mmc: mmci: Use optional sleep pinctrl state
In-Reply-To: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369302307-28540-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

By optionally putting the pins into sleep state in the .runtime_suspend
callback we can accomplish two things. One is to minimize current leakage
from pins and thus save power, second we can prevent the IP from driving
pins output in an uncontrolled manner, which may happen if the power domain
drops the domain regulator.

When returning from idle, entering .runtime_resume callback, the pins
are restored to default state.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
---

Changes in v2:
	Just adding Linus reviewed by.
---
 drivers/mmc/host/mmci.c |   16 ++++++++++++++++
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index c3785ed..9fa8855 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1527,6 +1527,12 @@ static int mmci_probe(struct amba_device *dev,
 	} else
 		dev_warn(&dev->dev, "could not get default pinstate\n");
 
+	/* fetch optional sleep state of pins */
+	host->pins_sleep = pinctrl_lookup_state(host->pinctrl,
+			PINCTRL_STATE_SLEEP);
+	if (IS_ERR(host->pins_sleep))
+		dev_dbg(&dev->dev, "could not get sleep pinstate\n");
+
 	/* Get regulators and the supported OCR mask */
 	mmc_regulator_get_supply(mmc);
 	if (!mmc->ocr_avail)
@@ -1767,6 +1773,11 @@ static int mmci_runtime_suspend(struct device *dev)
 
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
+
+		/* Optionally let pins go into sleep state */
+		if (!IS_ERR(host->pins_sleep))
+			pinctrl_select_state(host->pinctrl, host->pins_sleep);
+
 		clk_disable_unprepare(host->clk);
 	}
 
@@ -1780,7 +1791,12 @@ static int mmci_runtime_resume(struct device *dev)
 
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
+
 		clk_prepare_enable(host->clk);
+
+		/* Optionally enable pins to be muxed in and configured */
+		if (!IS_ERR(host->pins_default))
+			pinctrl_select_state(host->pinctrl, host->pins_default);
 	}
 
 	return 0;
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 69080fa..060f919 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -203,6 +203,7 @@ struct mmci_host {
 	/* pinctrl handles */
 	struct pinctrl		*pinctrl;
 	struct pinctrl_state	*pins_default;
+	struct pinctrl_state	*pins_sleep;
 
 #ifdef CONFIG_DMA_ENGINE
 	/* DMA stuff */
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 05:45:07 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 11:45:07 +0200
Subject: [PATCH V2 3/3] mmc: mmci: Save and restore register context
In-Reply-To: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369302307-28540-4-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

If a corresponding power domain exists for the device and it manages
to cut the domain regulator while the device is runtime suspended,
the IP loses it's registers context. We restore the context in the
.runtime_resume callback from the existing register caches to adapt
to this siutuation.

We also want to make sure the registers are in a known state while
restoring context in the case when the power domain did not drop the
power, since there are restrictions for the order of writing to these
registers. To handle this, we clear the registers in the
.runtime_suspend callback.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---

Changes in v2:
	Rebased on top of recently merged patchset for UHS card support.
---
 drivers/mmc/host/mmci.c |   43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 8f70e5b..ec9f17c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -62,6 +62,7 @@ static unsigned int fmax = 515633;
  * @signal_direction: input/out direction of bus signals can be indicated
  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
  * @busy_detect: true if busy detection on dat0 is supported
+ * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
  */
 struct variant_data {
 	unsigned int		clkreg;
@@ -76,6 +77,7 @@ struct variant_data {
 	bool			signal_direction;
 	bool			pwrreg_clkgate;
 	bool			busy_detect;
+	bool			pwrreg_nopower;
 };
 
 static struct variant_data variant_arm = {
@@ -109,6 +111,7 @@ static struct variant_data variant_u300 = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.pwrreg_nopower		= true,
 };
 
 static struct variant_data variant_nomadik = {
@@ -121,6 +124,7 @@ static struct variant_data variant_nomadik = {
 	.pwrreg_powerup		= MCI_PWR_ON,
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
+	.pwrreg_nopower		= true,
 };
 
 static struct variant_data variant_ux500 = {
@@ -135,6 +139,7 @@ static struct variant_data variant_ux500 = {
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
 	.busy_detect		= true,
+	.pwrreg_nopower		= true,
 };
 
 static struct variant_data variant_ux500v2 = {
@@ -150,6 +155,7 @@ static struct variant_data variant_ux500v2 = {
 	.signal_direction	= true,
 	.pwrreg_clkgate		= true,
 	.busy_detect		= true,
+	.pwrreg_nopower		= true,
 };
 
 static int mmci_card_busy(struct mmc_host *mmc)
@@ -1782,6 +1788,41 @@ static int mmci_resume(struct device *dev)
 #endif
 
 #ifdef CONFIG_PM_RUNTIME
+static void mmci_save(struct mmci_host *host)
+{
+	unsigned long flags;
+
+	if (host->variant->pwrreg_nopower) {
+		spin_lock_irqsave(&host->lock, flags);
+
+		writel(0, host->base + MMCIMASK0);
+		writel(0, host->base + MMCIDATACTRL);
+		writel(0, host->base + MMCIPOWER);
+		writel(0, host->base + MMCICLOCK);
+		mmci_reg_delay(host);
+
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+
+}
+
+static void mmci_restore(struct mmci_host *host)
+{
+	unsigned long flags;
+
+	if (host->variant->pwrreg_nopower) {
+		spin_lock_irqsave(&host->lock, flags);
+
+		writel(host->clk_reg, host->base + MMCICLOCK);
+		writel(host->datactrl_reg, host->base + MMCIDATACTRL);
+		writel(host->pwr_reg, host->base + MMCIPOWER);
+		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+		mmci_reg_delay(host);
+
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+}
+
 static int mmci_runtime_suspend(struct device *dev)
 {
 	struct amba_device *adev = to_amba_device(dev);
@@ -1794,6 +1835,7 @@ static int mmci_runtime_suspend(struct device *dev)
 		if (!IS_ERR(host->pins_sleep))
 			pinctrl_select_state(host->pinctrl, host->pins_sleep);
 
+		mmci_save(host);
 		clk_disable_unprepare(host->clk);
 	}
 
@@ -1809,6 +1851,7 @@ static int mmci_runtime_resume(struct device *dev)
 		struct mmci_host *host = mmc_priv(mmc);
 
 		clk_prepare_enable(host->clk);
+		mmci_restore(host);
 
 		/* Optionally enable pins to be muxed in and configured */
 		if (!IS_ERR(host->pins_default))
-- 
1.7.10



From catalin.marinas at arm.com  Thu May 23 05:47:09 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 10:47:09 +0100
Subject: [PATCH v2 0/4] dma-mapping: Define dma_{alloc,free}_attrs()
 for all archs
In-Reply-To: <519D8331.3060203@igel.co.jp>
References: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
 <519C2F5D.8000809@igel.co.jp> <20130522094741.GE14322@arm.com>
 <519D8331.3060203@igel.co.jp>
Message-ID: <20130523094709.GB16722@arm.com>

On Thu, May 23, 2013 at 03:47:13AM +0100, Damian Hobson-Garcia wrote:
> Hi Catalin,
> On 2013/05/22 18:47, Catalin Marinas wrote:
> > On Wed, May 22, 2013 at 03:37:17AM +0100, Damian Hobson-Garcia wrote:
> >> Hello,
> >> On 2013/04/30 12:01, Damian Hobson-Garcia wrote:
> >>> Most architectures that define CONFIG_HAVE_DMA=y, have implementations for
> >>> both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
> >>> not define CONFIG_HAVE_DMA also have both of these definitions provided by
> >>> dma-mapping-broken.h.
> > 
> > BTW, shouldn't this be called CONFIG_HAVE_DMA_ATTRS?
> 
> CONFIG_HAVE_DMA_ATTRS is currently used to enable the functions to
> set/get the DMA attribute values. Poking through the headers, it looks
> like the struct dma_attrs is defined regardless of the
> CONFIG_HAVE_DMA_ATTRS setting, so in that respect
> we always seem to "have" DMA attributes (if we have DMA), but they may
> not always be meaningful (ie. set to some value).

My point was about the commit log - grep'ing the kernel for
CONFIG_HAVE_DMA did not return anything.

-- 
Catalin


From b32955 at freescale.com  Thu May 23 05:52:16 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 23 May 2013 17:52:16 +0800
Subject: [PATCH V2 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
In-Reply-To: <1369301996.738631947@f310.mail.ru>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369300440.725629549@f101.mail.ru> <519DE109.1030903@freescale.com>
 <1369301996.738631947@f310.mail.ru>
Message-ID: <519DE6D0.2040909@freescale.com>

? 2013?05?23? 17:39, Alexander Shiyan ??:
> How we should define CS1 pin in your example for second device?
>

But in the imx6q{dl}-sabreauto boards, we only have the NOR connected to 
WEIM.
I do not need to worry about the second device.


If in customer's boards, they connect two devices to the weim.
they should add their own special pinctrl for the two devices, such as 
split out the CS pad.

But for the imx6q{dl}-sabreauto boards, i do not need to do so.




thanks
Huang Shijie




From b.brezillon at overkiz.com  Thu May 23 05:51:36 2013
From: b.brezillon at overkiz.com (boris brezillon)
Date: Thu, 23 May 2013 11:51:36 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523090611.GG9937@game.jcrosoft.org>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
Message-ID: <519DE6A8.6040502@overkiz.com>

On 23/05/2013 11:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:05 Thu 23 May     , Boris BREZILLON wrote:
>> Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
>> Move arch/arm/mach-at91/at91_aic.h to
>> arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
>> to header file :
>> #include "../../arch/arm/mach-at91/at91_aic.h"
> no we are going to drop arch/arm/mach-at91/include/mach for multi support
>
> arch/arm/mach-at91/include/mach is for removal
What should be done ?

include ../../arch/arm/mach-at91/at91_aic.h from irq-at91.c

or

move at91_aic.h into drivers/irqchips and patch every non dt board to
include ../../../drivers/irqchip/at91_aic.h

>
> Best Regards,
> J.
>> Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
>> ---
>>   arch/arm/mach-at91/Makefile                        |    2 +-
>>   arch/arm/mach-at91/at91rm9200.c                    |    2 +-
>>   arch/arm/mach-at91/at91sam9260.c                   |    2 +-
>>   arch/arm/mach-at91/at91sam9261.c                   |    2 +-
>>   arch/arm/mach-at91/at91sam9263.c                   |    2 +-
>>   arch/arm/mach-at91/at91sam9g45.c                   |    2 +-
>>   arch/arm/mach-at91/at91sam9rl.c                    |    2 +-
>>   arch/arm/mach-at91/at91x40.c                       |    2 +-
>>   arch/arm/mach-at91/board-1arm.c                    |    2 +-
>>   arch/arm/mach-at91/board-afeb-9260v1.c             |    2 +-
>>   arch/arm/mach-at91/board-cam60.c                   |    2 +-
>>   arch/arm/mach-at91/board-carmeva.c                 |    2 +-
>>   arch/arm/mach-at91/board-cpu9krea.c                |    2 +-
>>   arch/arm/mach-at91/board-cpuat91.c                 |    2 +-
>>   arch/arm/mach-at91/board-csb337.c                  |    2 +-
>>   arch/arm/mach-at91/board-csb637.c                  |    2 +-
>>   arch/arm/mach-at91/board-dt-rm9200.c               |    3 ++-
>>   arch/arm/mach-at91/board-dt-sam9.c                 |    3 ++-
>>   arch/arm/mach-at91/board-dt-sama5.c                |    3 ++-
>>   arch/arm/mach-at91/board-eb01.c                    |    3 ++-
>>   arch/arm/mach-at91/board-eb9200.c                  |    3 ++-
>>   arch/arm/mach-at91/board-ecbat91.c                 |    2 +-
>>   arch/arm/mach-at91/board-eco920.c                  |    2 +-
>>   arch/arm/mach-at91/board-flexibity.c               |    2 +-
>>   arch/arm/mach-at91/board-foxg20.c                  |    2 +-
>>   arch/arm/mach-at91/board-gsia18s.c                 |    2 +-
>>   arch/arm/mach-at91/board-kafa.c                    |    2 +-
>>   arch/arm/mach-at91/board-kb9202.c                  |    2 +-
>>   arch/arm/mach-at91/board-pcontrol-g20.c            |    2 +-
>>   arch/arm/mach-at91/board-picotux200.c              |    2 +-
>>   arch/arm/mach-at91/board-qil-a9260.c               |    2 +-
>>   arch/arm/mach-at91/board-rm9200dk.c                |    2 +-
>>   arch/arm/mach-at91/board-rm9200ek.c                |    2 +-
>>   arch/arm/mach-at91/board-rsi-ews.c                 |    3 ++-
>>   arch/arm/mach-at91/board-sam9-l9260.c              |    2 +-
>>   arch/arm/mach-at91/board-sam9260ek.c               |    2 +-
>>   arch/arm/mach-at91/board-sam9261ek.c               |    2 +-
>>   arch/arm/mach-at91/board-sam9263ek.c               |    2 +-
>>   arch/arm/mach-at91/board-sam9g20ek.c               |    2 +-
>>   arch/arm/mach-at91/board-sam9m10g45ek.c            |    2 +-
>>   arch/arm/mach-at91/board-sam9rlek.c                |    2 +-
>>   arch/arm/mach-at91/board-snapper9260.c             |    2 +-
>>   arch/arm/mach-at91/board-stamp9g20.c               |    2 +-
>>   arch/arm/mach-at91/board-usb-a926x.c               |    2 +-
>>   arch/arm/mach-at91/board-yl-9200.c                 |    2 +-
>>   arch/arm/mach-at91/{ => include/mach}/at91_aic.h   |    0
>>   arch/arm/mach-at91/pm.c                            |    2 +-
>>   drivers/irqchip/Makefile                           |    1 +
>>   .../mach-at91/irq.c => drivers/irqchip/irq-at91.c  |    2 +-
>>   49 files changed, 54 insertions(+), 47 deletions(-)
>>
>> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
>> index 788562d..5333701 100644
>> --- a/arch/arm/mach-at91/Makefile
>> +++ b/arch/arm/mach-at91/Makefile
>> @@ -2,7 +2,7 @@
>>   # Makefile for the linux kernel.
>>   #
>>   
>> -obj-y		:= irq.o gpio.o setup.o
>> +obj-y		:= gpio.o setup.o
>>   obj-m		:=
>>   obj-n		:=
>>   obj-		:=
>> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
>> index d193a40..6c1204a 100644
>> --- a/arch/arm/mach-at91/at91rm9200.c
>> +++ b/arch/arm/mach-at91/at91rm9200.c
>> @@ -20,8 +20,8 @@
>>   #include <mach/at91_pmc.h>
>>   #include <mach/at91_st.h>
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "soc.h"
>>   #include "generic.h"
>>   #include "clock.h"
>> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
>> index a8ce245..55332fa 100644
>> --- a/arch/arm/mach-at91/at91sam9260.c
>> +++ b/arch/arm/mach-at91/at91sam9260.c
>> @@ -21,8 +21,8 @@
>>   #include <mach/at91_dbgu.h>
>>   #include <mach/at91sam9260.h>
>>   #include <mach/at91_pmc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_rstc.h"
>>   #include "soc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
>> index 25efb5a..6db61e6 100644
>> --- a/arch/arm/mach-at91/at91sam9261.c
>> +++ b/arch/arm/mach-at91/at91sam9261.c
>> @@ -20,8 +20,8 @@
>>   #include <mach/cpu.h>
>>   #include <mach/at91sam9261.h>
>>   #include <mach/at91_pmc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_rstc.h"
>>   #include "soc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
>> index f44ffd2..b9ec043 100644
>> --- a/arch/arm/mach-at91/at91sam9263.c
>> +++ b/arch/arm/mach-at91/at91sam9263.c
>> @@ -19,8 +19,8 @@
>>   #include <asm/system_misc.h>
>>   #include <mach/at91sam9263.h>
>>   #include <mach/at91_pmc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_rstc.h"
>>   #include "soc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
>> index 8b7fce0..1270707 100644
>> --- a/arch/arm/mach-at91/at91sam9g45.c
>> +++ b/arch/arm/mach-at91/at91sam9g45.c
>> @@ -20,8 +20,8 @@
>>   #include <mach/at91sam9g45.h>
>>   #include <mach/at91_pmc.h>
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "soc.h"
>>   #include "generic.h"
>>   #include "clock.h"
>> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
>> index f77fae5..d5f77d6 100644
>> --- a/arch/arm/mach-at91/at91sam9rl.c
>> +++ b/arch/arm/mach-at91/at91sam9rl.c
>> @@ -20,8 +20,8 @@
>>   #include <mach/at91_dbgu.h>
>>   #include <mach/at91sam9rl.h>
>>   #include <mach/at91_pmc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_rstc.h"
>>   #include "soc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
>> index 19ca793..e8b30fb 100644
>> --- a/arch/arm/mach-at91/at91x40.c
>> +++ b/arch/arm/mach-at91/at91x40.c
>> @@ -20,8 +20,8 @@
>>   #include <mach/at91x40.h>
>>   #include <mach/at91_st.h>
>>   #include <mach/timex.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "generic.h"
>>   
>>   /*
>> diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
>> index 35ab632..8037dfe 100644
>> --- a/arch/arm/mach-at91/board-1arm.c
>> +++ b/arch/arm/mach-at91/board-1arm.c
>> @@ -34,9 +34,9 @@
>>   #include <asm/mach/map.h>
>>   #include <asm/mach/irq.h>
>>   
>> +#include <mach/at91_aic.h>
>>   #include <mach/cpu.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
>> index f95e31c..28bea23 100644
>> --- a/arch/arm/mach-at91/board-afeb-9260v1.c
>> +++ b/arch/arm/mach-at91/board-afeb-9260v1.c
>> @@ -42,8 +42,8 @@
>>   #include <asm/mach/arch.h>
>>   #include <asm/mach/map.h>
>>   #include <asm/mach/irq.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
>> index ade948b..6ebdf32 100644
>> --- a/arch/arm/mach-at91/board-cam60.c
>> +++ b/arch/arm/mach-at91/board-cam60.c
>> @@ -39,8 +39,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
>> index 9298305..842db49 100644
>> --- a/arch/arm/mach-at91/board-carmeva.c
>> +++ b/arch/arm/mach-at91/board-carmeva.c
>> @@ -35,8 +35,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/hardware.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
>> index 008527e..4714e9e 100644
>> --- a/arch/arm/mach-at91/board-cpu9krea.c
>> +++ b/arch/arm/mach-at91/board-cpu9krea.c
>> @@ -43,8 +43,8 @@
>>   #include <mach/at91sam9_smc.h>
>>   #include <mach/at91sam9260_matrix.h>
>>   #include <mach/at91_matrix.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
>> index 42f1353..c1663ed 100644
>> --- a/arch/arm/mach-at91/board-cpuat91.c
>> +++ b/arch/arm/mach-at91/board-cpuat91.c
>> @@ -39,8 +39,8 @@
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
>> index e5fde215..3231703 100644
>> --- a/arch/arm/mach-at91/board-csb337.c
>> +++ b/arch/arm/mach-at91/board-csb337.c
>> @@ -38,8 +38,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/hardware.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
>> index fdf1106..d58c7e6 100644
>> --- a/arch/arm/mach-at91/board-csb637.c
>> +++ b/arch/arm/mach-at91/board-csb637.c
>> @@ -35,8 +35,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/hardware.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
>> index 3fcb662..0c2a06d 100644
>> --- a/arch/arm/mach-at91/board-dt-rm9200.c
>> +++ b/arch/arm/mach-at91/board-dt-rm9200.c
>> @@ -22,7 +22,8 @@
>>   #include <asm/mach/map.h>
>>   #include <asm/mach/irq.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>> +
>>   #include "generic.h"
>>   
>>   
>> diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
>> index 8db3013..ac899d8 100644
>> --- a/arch/arm/mach-at91/board-dt-sam9.c
>> +++ b/arch/arm/mach-at91/board-dt-sam9.c
>> @@ -21,7 +21,8 @@
>>   #include <asm/mach/map.h>
>>   #include <asm/mach/irq.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>> +
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
>> index 705305e..43b8f7a 100644
>> --- a/arch/arm/mach-at91/board-dt-sama5.c
>> +++ b/arch/arm/mach-at91/board-dt-sama5.c
>> @@ -23,7 +23,8 @@
>>   #include <asm/mach/map.h>
>>   #include <asm/mach/irq.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>> +
>>   #include "generic.h"
>>   
>>   
>> diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
>> index becf0a6..4097ede 100644
>> --- a/arch/arm/mach-at91/board-eb01.c
>> +++ b/arch/arm/mach-at91/board-eb01.c
>> @@ -28,7 +28,8 @@
>>   #include <asm/mach/arch.h>
>>   #include <asm/mach/map.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>> +
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
>> index f9be816..afa5ebb 100644
>> --- a/arch/arm/mach-at91/board-eb9200.c
>> +++ b/arch/arm/mach-at91/board-eb9200.c
>> @@ -35,7 +35,8 @@
>>   #include <asm/mach/map.h>
>>   #include <asm/mach/irq.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>> +
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
>> index b2fcd71..c794768 100644
>> --- a/arch/arm/mach-at91/board-ecbat91.c
>> +++ b/arch/arm/mach-at91/board-ecbat91.c
>> @@ -38,8 +38,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
>> index 77de410..fc3e373 100644
>> --- a/arch/arm/mach-at91/board-eco920.c
>> +++ b/arch/arm/mach-at91/board-eco920.c
>> @@ -27,8 +27,8 @@
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
>> index 737c085..59a1958 100644
>> --- a/arch/arm/mach-at91/board-flexibity.c
>> +++ b/arch/arm/mach-at91/board-flexibity.c
>> @@ -33,8 +33,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/hardware.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
>> index c20a870..4b4df05 100644
>> --- a/arch/arm/mach-at91/board-foxg20.c
>> +++ b/arch/arm/mach-at91/board-foxg20.c
>> @@ -42,8 +42,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
>> index c1d61d2..1babcbd 100644
>> --- a/arch/arm/mach-at91/board-gsia18s.c
>> +++ b/arch/arm/mach-at91/board-gsia18s.c
>> @@ -31,8 +31,8 @@
>>   #include <asm/mach/arch.h>
>>   
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
>> index 88e2f5d..aca52d3 100644
>> --- a/arch/arm/mach-at91/board-kafa.c
>> +++ b/arch/arm/mach-at91/board-kafa.c
>> @@ -35,8 +35,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
>> index 0c519d9..7768df0 100644
>> --- a/arch/arm/mach-at91/board-kb9202.c
>> +++ b/arch/arm/mach-at91/board-kb9202.c
>> @@ -38,8 +38,8 @@
>>   #include <mach/cpu.h>
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
>> index 65c0d6b..6df21db 100644
>> --- a/arch/arm/mach-at91/board-pcontrol-g20.c
>> +++ b/arch/arm/mach-at91/board-pcontrol-g20.c
>> @@ -30,8 +30,8 @@
>>   #include <asm/mach/arch.h>
>>   
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
>> index ab2b2ec..566b30c 100644
>> --- a/arch/arm/mach-at91/board-picotux200.c
>> +++ b/arch/arm/mach-at91/board-picotux200.c
>> @@ -39,8 +39,8 @@
>>   
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
>> index aa3bc9b..0ae5eb1 100644
>> --- a/arch/arm/mach-at91/board-qil-a9260.c
>> +++ b/arch/arm/mach-at91/board-qil-a9260.c
>> @@ -41,8 +41,8 @@
>>   
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
>> index 690541b..82f0335e 100644
>> --- a/arch/arm/mach-at91/board-rm9200dk.c
>> +++ b/arch/arm/mach-at91/board-rm9200dk.c
>> @@ -41,8 +41,8 @@
>>   #include <mach/hardware.h>
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
>> index 8b17dad..5e8a4f7 100644
>> --- a/arch/arm/mach-at91/board-rm9200ek.c
>> +++ b/arch/arm/mach-at91/board-rm9200ek.c
>> @@ -41,8 +41,8 @@
>>   #include <mach/hardware.h>
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
>> index f6d7f19..e7d0a69 100644
>> --- a/arch/arm/mach-at91/board-rsi-ews.c
>> +++ b/arch/arm/mach-at91/board-rsi-ews.c
>> @@ -28,7 +28,8 @@
>>   
>>   #include <linux/gpio.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>> +
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
>> index 43ee4dc..2e400cd 100644
>> --- a/arch/arm/mach-at91/board-sam9-l9260.c
>> +++ b/arch/arm/mach-at91/board-sam9-l9260.c
>> @@ -38,8 +38,8 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
>> index 0b153c8..66ee7ac 100644
>> --- a/arch/arm/mach-at91/board-sam9260ek.c
>> +++ b/arch/arm/mach-at91/board-sam9260ek.c
>> @@ -43,8 +43,8 @@
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>>   #include <mach/system_rev.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
>> index b446645..515957e 100644
>> --- a/arch/arm/mach-at91/board-sam9261ek.c
>> +++ b/arch/arm/mach-at91/board-sam9261ek.c
>> @@ -47,8 +47,8 @@
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>>   #include <mach/system_rev.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
>> index 3284df0..1099272 100644
>> --- a/arch/arm/mach-at91/board-sam9263ek.c
>> +++ b/arch/arm/mach-at91/board-sam9263ek.c
>> @@ -46,8 +46,8 @@
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>>   #include <mach/system_rev.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
>> index f9cd1f2..9fe718b 100644
>> --- a/arch/arm/mach-at91/board-sam9g20ek.c
>> +++ b/arch/arm/mach-at91/board-sam9g20ek.c
>> @@ -45,8 +45,8 @@
>>   
>>   #include <mach/at91sam9_smc.h>
>>   #include <mach/system_rev.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
>> index 2a94896..1846647 100644
>> --- a/arch/arm/mach-at91/board-sam9m10g45ek.c
>> +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
>> @@ -44,8 +44,8 @@
>>   
>>   #include <mach/at91sam9_smc.h>
>>   #include <mach/system_rev.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
>> index aa265dc..623f2d1 100644
>> --- a/arch/arm/mach-at91/board-sam9rlek.c
>> +++ b/arch/arm/mach-at91/board-sam9rlek.c
>> @@ -31,9 +31,9 @@
>>   
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
>> index 3aaa978..8fef38a 100644
>> --- a/arch/arm/mach-at91/board-snapper9260.c
>> +++ b/arch/arm/mach-at91/board-snapper9260.c
>> @@ -33,8 +33,8 @@
>>   
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
>> index 869cbec..6bda942 100644
>> --- a/arch/arm/mach-at91/board-stamp9g20.c
>> +++ b/arch/arm/mach-at91/board-stamp9g20.c
>> @@ -26,8 +26,8 @@
>>   #include <asm/mach/arch.h>
>>   
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>>   #include "generic.h"
>> diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
>> index 2487d94..cedbc66 100644
>> --- a/arch/arm/mach-at91/board-usb-a926x.c
>> +++ b/arch/arm/mach-at91/board-usb-a926x.c
>> @@ -42,8 +42,8 @@
>>   
>>   #include <mach/hardware.h>
>>   #include <mach/at91sam9_smc.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "at91_shdwc.h"
>>   #include "board.h"
>>   #include "sam9_smc.h"
>> diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
>> index be08377..c61d8c9 100644
>> --- a/arch/arm/mach-at91/board-yl-9200.c
>> +++ b/arch/arm/mach-at91/board-yl-9200.c
>> @@ -46,8 +46,8 @@
>>   #include <mach/at91rm9200_mc.h>
>>   #include <mach/at91_ramc.h>
>>   #include <mach/cpu.h>
>> +#include <mach/at91_aic.h>
>>   
>> -#include "at91_aic.h"
>>   #include "board.h"
>>   #include "generic.h"
>>   
>> diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
>> similarity index 100%
>> rename from arch/arm/mach-at91/at91_aic.h
>> rename to arch/arm/mach-at91/include/mach/at91_aic.h
>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>> index 530db30..d2a24e8 100644
>> --- a/arch/arm/mach-at91/pm.c
>> +++ b/arch/arm/mach-at91/pm.c
>> @@ -26,9 +26,9 @@
>>   #include <asm/mach/irq.h>
>>   
>>   #include <mach/at91_pmc.h>
>> +#include <mach/at91_aic.h>
>>   #include <mach/cpu.h>
>>   
>> -#include "at91_aic.h"
>>   #include "generic.h"
>>   #include "pm.h"
>>   
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index cda4cb5..208b708 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -1,5 +1,6 @@
>>   obj-$(CONFIG_IRQCHIP)			+= irqchip.o
>>   
>> +obj-$(CONFIG_ARCH_AT91)			+= irq-at91.o
>>   obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
>>   obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
>>   obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
>> diff --git a/arch/arm/mach-at91/irq.c b/drivers/irqchip/irq-at91.c
>> similarity index 99%
>> rename from arch/arm/mach-at91/irq.c
>> rename to drivers/irqchip/irq-at91.c
>> index e0ca591..daf2959 100644
>> --- a/arch/arm/mach-at91/irq.c
>> +++ b/drivers/irqchip/irq-at91.c
>> @@ -42,7 +42,7 @@
>>   #include <asm/mach/irq.h>
>>   #include <asm/mach/map.h>
>>   
>> -#include "at91_aic.h"
>> +#include <mach/at91_aic.h>
>>   
>>   void __iomem *at91_aic_base;
>>   static struct irq_domain *at91_aic_domain;
>> -- 
>> 1.7.9.5
>>



From thomas.petazzoni at free-electrons.com  Thu May 23 05:53:21 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 11:53:21 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130522181953.GD12320@obsidianresearch.com>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522181953.GD12320@obsidianresearch.com>
Message-ID: <20130523115321.660fa521@skate>

Dear Jason Gunthorpe,

On Wed, 22 May 2013 12:19:53 -0600, Jason Gunthorpe wrote:

> Just to chime in a bit here.. We also hit this problem on Kirkwood,
> and fixed it in the bootloader. The power on default for Kirkwood
> chips is 0xd0000000 and Linux has long required the bootloader to move
> it.. Not sure why 370/XP dropped this.

This is a mistake from the original support of Armada 370/XP. What we
want to do now is to fix this mistake by moving everybody to 0xf1 and
align with the other Marvell EBU platforms.

What we're proposing here is only a *temporary* solution to provide a
smooth upgrade path for users of platforms that have an old bootloader.
This temporary solution is meant to go away when we have a good
confidence that new bootloaders for OpenBlocks and Mirabox are
available, and that enough users will have seen the warning that we
plan to add in two release cycles.

> Also, can you talk abit more about how this works to give more low DDR
> memory? The docs say you can't overlap windows, and DDR CS's have a
> power of two size/alignment requirement.
> 
> Does this mean the desire is to place a DDR CS from 3G -> 3.5G?

The MBus windows can overlap the DRAM chip selects. On Armada 370/XP,
there is a tuple of registers, called the MBus Bridge Window Base
Register and the MBus Bridge Window Control Register, that provide a
range of addresses for which the CPU should go look at MBus windows
instead of looking at the DRAM.

So, on a board with 8 GB of RAM, you have one DRAM chip select for the
first 4 GB of RAM, and a second chip select for the last 4 GB of RAM.
This is currently visible with the Armada XP GP board:

# cat /sys/kernel/debug/mvebu-mbus/sdram 
[0] 0000000000000000 - 0000000100000000 : cs0
[1] 0000000100000000 - 0000000200000000 : cs1
[2] disabled
[3] disabled

And the internal registers (be they mapped at 0xd0000000 of 0xf1000000)
and all the other windows (for PCIe and al) are overlapping the DRAM CS.

This is not a problem, because the MBus Bridge Window {Base,Control}
Register tell the CPU that memory accesses between addresses X and Y
are for MBus windows, and the other accesses are for the DRAM.

With the old bootloader, the MBus Bridge Window Base is set to
0xC0000000 (3G), so you cannot benefit from this additional memory
between 3G and 3.5G. But the only two consumers platforms available
that are using the old bootloaders have 3 GB of RAM or less (the
OpenBlocks has an expansion slot, but I believe it's reasonable to ask
the user to upgrade the bootloader if he wants to use a larger RAM on
this specific board).

With the new bootloader, the MBus Bridge Window Base is set to
0xE0000000 (3.5 GB). So any access in [ 0 ; 3.5 GB ] and [ 4 GB; ... ]
will go to the DRAM, and access between [ 3.5 GB ; 4 GB ] will go to
the MBus windows, including the internal registers one.

Does that make sense to explain how we can actually save 512 MB of RAM ?

> > For example, I'm currently booting alternatively with an old and a new
> > bootloader (to test that things work properly), and in both cases I'm
> > booting old style, DTB-appended, with ATAGs.
> 
> IMHO the DTB must match both the hardware *and* the bootloader. The
> bootloader is setting the address map, the DTB contains that address
> map, they must all match together.
> 
> Using a DTB property really is the right way to go.
> 
> Yes, I realize this means you now need to vary the DTB you will use
> depending on boot loader version (see below)
> 
> To use a DTB property, the approach would be to make the internal regs
> base address inside the kernel dynamic instead of hard coded. Do not
> remap the internal regs, just use whatever the bootloader setup
> directly. The kernel can early parse the FDT to find the correct
> address, instead of hardwiring an arbitary base address.
> 
> Also, the blind remapping approach in these patches is sketchy. If the
> bootloader has placed some other mapping at the 0xf1.. target address
> this will blow up. The mbus driver gets it right, to change the window
> layout you have to clear out and disable all window registers except
> for internal, then rebuild the entire mapping from scratch to avoid
> address overlap conflicts. That approach doesn't seem possible from
> early assembly.. :(
> 
> All things considered, I think it is much safer and cleaner to make
> the physical base of internal regs dynamic within the kernel, than to
> try and relocate it during early boot.

We believe it is not safer to make the physical base of internal regs
dynamic within the kernel. Really, the 0xd0 usage should be seen as a
mistake, and the goal is to align everybody to use 0xf1 for all Marvell
platforms.

> So, please consider this instead. The kernel has functions already to
> parse the fdt directly, they can be called before anything attempts to
> map internal regs based stuff.
> 
> You can combine this idea with the CP15 signalling mechanism. Check
> CP15 and use it to alter the DTB, similar to how ATAGs are used to
> fixup the DTB. Don't relocate the registers.

Where would the code doing this would sit? Remember, this is a
temporary solution that we want to get rid of after some time. So I've
been very careful in this proposal to only touch mvebu-specific code.

With what you're proposing, we would have to add something like:

	if (of_machine_is_compatible("marvell,armada-370-xp")) {
		/* do our crap */
	}

in some ARM generic code. That's something we would definitely like to
avoid, and I'm pretty the ARM maintainers would also like to avoid such
SoC-specific code spreading into generic kernel places.

Could you be more specific about where such early code would be
located, and what it would look like? I'm pretty sure once we will see
it, we'll clearly see that it's not acceptable to put such SoC-specific
code in a generic place of the kernel.

Thanks for your feedback,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From arnd at arndb.de  Thu May 23 05:53:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 11:53:37 +0200
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <519DE2EE.1050006@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <20130523092344.GF32299@pengutronix.de> <519DE2EE.1050006@freescale.com>
Message-ID: <201305231153.38111.arnd@arndb.de>

On Thursday 23 May 2013, Huang Shijie wrote:
> ? 2013?05?23? 17:23, Sascha Hauer ??:
> > On Thu, May 23, 2013 at 04:16:13PM +0800, Huang Shijie wrote:
> >> +			<cs-number>  0<physical address of mapping>  <size>
> >> +
> >> +Timing property for child nodes. It is mandatory, not optional.
> >> +
> >> + - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
> >> +			child node. We can get the CS index from the child
> >> +			node's "reg" property.
> > This should be more detailed, something like:
> >
> > This contains the values for the registers EIM_CSnGCR1, EIM_CSnGCR2,
> > EIM_CSnRCR1, EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
> >
> 
> 
> do you mean i should add some new properties, such as
> "fsl,eim_csnrcr1", "fsl,eim_csnrcr2" ...

No, the property is fine, just update the documentation the way that
Sascha suggested.

> >> +static int weim_remove(struct platform_device *pdev)
> >> +{
> >> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> >> +
> >> +	clk_disable_unprepare(weim->clk);
> > Once again: Is this clock needed for the child devices? If yes, you
> > can't disable it here and leave the child devices registered.
> >

But weim_remove will not be called as long as there are children
registered, right?

	Arnd


From shc_work at mail.ru  Thu May 23 05:55:06 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 13:55:06 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSCBWMiA0LzZdIEFSTTogZHRzOiBpbXg2cTogYWRkIHBp?=
 =?UTF-8?B?bmN0cmwgZm9yIFdFSU0gTk9S?=
In-Reply-To: <519DE6D0.2040909@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369301996.738631947@f310.mail.ru>
 <519DE6D0.2040909@freescale.com>
Message-ID: <1369302906.444557883@f310.mail.ru>

> > How we should define CS1 pin in your example for second device?
> 
> But in the imx6q{dl}-sabreauto boards, we only have the NOR connected to 
> WEIM.
> I do not need to worry about the second device.

OK, but you add "weim-NOR" to the arch/arm/boot/dts/imx6q.dtsi, not
in imx6qdl-sabreauto.dtsi, so you mean that this definition is generic.
Should it be moved to imx6qdl-sabreauto.dtsi then?

---

From acourbot at nvidia.com  Thu May 23 05:55:21 2013
From: acourbot at nvidia.com (Alex Courbot)
Date: Thu, 23 May 2013 18:55:21 +0900
Subject: Naming convention DSI + device tree
In-Reply-To: <519C64AB.2090708@gmail.com>
References: <20130514181745.GA2762@mail.o2s.ch>
 <51940C22.4050802@wwwdotorg.org> <20130516071537.GA13573@mail.o2s.ch>
 <519522C1.5010107@wwwdotorg.org> <5195C1E2.4020009@nvidia.com>
 <519C64AB.2090708@gmail.com>
Message-ID: <519DE789.5020308@nvidia.com>

On 05/22/2013 03:24 PM, Mark Zhang wrote:
> Cool. Alex, do you know any updates on DSI part of CDF? I recall few
> months ago, Laurent wrote mail to share some infos about the CDF
> discussions, and it mentioned that the DSI will be considered in next
> version of CDF... you know, for t114, the DSI support is a must.

I will make sure to discuss this detail with Laurent as he comes for 
LinuxCon next week. ;)

Alex.



From ard.biesheuvel at linaro.org  Thu May 23 05:57:21 2013
From: ard.biesheuvel at linaro.org (Ard Biesheuvel)
Date: Thu, 23 May 2013 11:57:21 +0200
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <20130523084126.GI18614@n2100.arm.linux.org.uk>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
 <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
 <20130523084126.GI18614@n2100.arm.linux.org.uk>
Message-ID: <CAKv+Gu_1aJiD_QB1HfvKRKDE1kCtf=fEiqQ=7UbL+je5meFvow@mail.gmail.com>

On 23 May 2013 10:41, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Thu, May 23, 2013 at 09:28:24AM +0200, Ard Biesheuvel wrote:
>> In order to use the NEON/VFP unit in the kernel, we should
>> initialize it a bit earlier in the boot process so NEON users
>> that like to do a quick benchmark at load time (like the
>> xor_blocks or RAID-6 code) find the NEON/VFP unit already
>> enabled.
>
> So what are the results of those benchmarks that the RAID-6 code does?
>

Output captured from a Cortex-A15 @ 1.7 GHz:

    xor: measuring software checksum speed
       arm4regs  :  2261.600 MB/sec
       8regs     :  1771.600 MB/sec
       32regs    :  1441.600 MB/sec
       neon      :  3619.600 MB/sec
    xor: using function: neon (3619.600 MB/sec)

Output captured from a Cortex-A15 @ 1.7 GHz:

    raid6: int32x1    200 MB/s
    raid6: int32x2    304 MB/s
    raid6: int32x4    388 MB/s
    raid6: int32x8    423 MB/s
    raid6: neonx1     799 MB/s
    raid6: neonx2    1364 MB/s
    raid6: neonx4    1731 MB/s
    raid6: neonx8    1676 MB/s
    raid6: using algorithm neonx4 (1731 MB/s)
    raid6: using intx1 recovery algorithm

I can put up both patches for RFC if you like.

> This isn't something which will get accepted without there being a very
> strong case for it; firstly, we've always said "no FP in the kernel".
> Secondly, it makes it too easy for people to start thinking that FP is
> safe in the kernel.  It isn't - this will go horribly wrong if the VFP
> hardware bounces an instruction to the support code.
>

That is clear. In the two cases I have been playing with, the
begin/end calls are in distinct compilation units from the actual
functions containing the NEON code. Perhaps we should enforce this by
conditionally turning kernel_vfp_begin() into a macro which errors out
(i.e., if __ARM_NEON__ is defined)?

> Lastly, what happens if you sleep between kernel_vfp_start() and
> kernel_vfp_end() ?  That's a context switch which will mess up your
> VFP state.  I think you need to take a spinlock (not _bh nor _irqsave
> versions) in here to ensure that people don't get the idea that they
> _can_ sleep between these two.
>

So generally, sleeping under preempt_disable() (or get cpu()) in this
case) is not currently handled in that way?
That is a misunderstanding on my part, I will address it in the code.

Regards,
-- 
Ard.



> So, good attempt, but I think you need to think about this more, and
> also justify the need for it.


From thomas.petazzoni at free-electrons.com  Thu May 23 06:02:48 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 12:02:48 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305222236.12652.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130522155134.GL2824@lunn.ch> <20130522182219.062079ac@skate>
 <201305222236.12652.arnd@arndb.de>
Message-ID: <20130523120248.51a85f50@skate>

Dear Arnd Bergmann,

On Wed, 22 May 2013 22:36:12 +0200, Arnd Bergmann wrote:

> > > Maybe i'm missunderstand Arnd, but i think he is suggesting a property
> > > somewhere in DT which says where the bootloader left the register
> > > space before jumping to the kernel. You can then look at this property
> > > and then decide if you need to remap or not. Only this one property
> > > needs to differ between old and new bootloader. You could even say, if
> > > the property is not in DT, a remap is needed.
> 
> No, the idea was that we don't need to remap if we know where the registers
> are. The mbus driver might remap them if it is really careful about not
> breaking any existing mappings, but it's probably easier to just leave
> them alone.

Again, our aim is to get everybody to run kernels with registers
remapped at 0xf1, so that we're back to what should have been done
originally.

Ideally, we'd like to completely forget about supporting old
bootloaders, and assume we only have good bootloaders that remap things
to 0xf1. We're only proposing this *temporary* solution to make the
transition easier, give some time to the board manufacturers to release
updated bootloaders, to users to upgrade their bootloaders, and finally
remove this temporary solution.

We clearly don't want to go down the road of supporting an
arbitrarily-defined base address for the internal registers. This has
never been the case for Kirkwood, Orion5x, Dove, and there is no
compelling reason to make it a requirement for Armada 370/XP.

> > The problem is that neither the old nor the new bootloaders are setting
> > such property in the DT. Old bootloaders shipped by Marvell don't have
> > DT support at all. New bootloaders shipped by Marvell do have DT
> > support, but they are not adding any specific DT property that allows
> > us to tell whether the registers are mapped here or there.
> > 
> > We could maybe find a way of detecting whether if the bootloader is DT
> > capable, and assume that if it's DT capable, the registers are already
> > mapped at 0xf1. But that's very fragile: nothing prevents an user to
> > use a DT-capable bootloader to boot a kernel in the old style way
> > (appended DTB). In this case, we would assume that the registers are at
> > 0xd0, because we're being booted old-style, and therefore it must be an
> > old bootloader. Very fragile, clearly not better than the CP15 trick.
> 
> Yes, that would not be an improvement. However, since we know what boot
> loader we have when we pass the devicetree, that devicetree can just
> contain the correct 'reg' property for the internal registers.

What do you mean by "we know what boot loader we have when we pass the
devicetree" ?

The mere user of the kernel just does:

	make ARCH=arm mvebu_defconfig
	make ARCH=arm CROSS_COMPILE=...
	cat arch/arm/boot/zImage arch/arm/boot/dts/armada-370-mirabox.dtb > zImage.mirabox
	... prepare uImage ...

and he certainly doesn't want to understand the gory details of which
internal register base address to chose depending on which bootloader
version he is using. This is really asking normal users to have a too
much intimate knowledge of the hardware details.

The temporary solution we're proposing doesn't have this drawback: an
user can boot the kernel on either an old or new bootloader, without
having to worry about checking/changing the Device Tree source about
this bizarre internal register address thing.

As a developer of the Armada 370/XP, I am frequently contacted by users
to help them getting the mainline kernel booting on their Mirabox or
OpenBlocks. And trust me: even getting the appended DTB gymnastic right
is not easy. So getting this internal register story right is going to
be a nightmare in terms of support.

Please do not inflict to us such a support pain :-)

> > > However, i don't know if this can actually work. How early can you
> > > parse the DT in order to know where the serial port is for
> > > earlyprintk()? It also gets messy keeping track of the two different
> > > DT binary blobs and somehow having the probe the uboot version in
> > > order to install the right one. I don't know how i would include this
> > > into the debian flash-kernel for example.
> > 
> > For earlyprintk, we can "solve" it as Arnd suggested: just have two
> > Kconfig options, one for 0xd0, one for 0xf1, and it's up to the user to
> > choose the right one. It's not entirely nice because it's no longer
> > automatic, and I'm sure our users will have a hard time figuring out
> > whether they have an "old" or a "new" bootloader. But let's assume we
> > do this. earlyprintk knows the physical address of the UART.
> > 
> > Then, we enter ->map_io(). We have access to the Device Tree. But the
> > Device Tree doesn't tell us whether the bootloader has mapped the
> > registers. As I explained to Arnd, it's not a per-board criteria: when
> > I'm booting my OpenBlocks with the manufacturer U-Boot, registers are
> > mapped at 0xd0. When I boot the same OpenBlocks with the (admittedly
> > work-in-progress) Barebox bootloader, registers are mapped at 0xf1.
> > Same board, different register location.
> 
> But since you control barebox, you can find the "regs" property of the
> mbus node in it and set it up to the same address you use when you
> map the internal registers.

We may control Barebox because the support is not yet written, but we
clearly do not have much control over what Marvell is doing with its
own U-Boot. And let's be pragmatic: 99.99% of the Marvell 370/XP
platforms will be running the U-Boot from Marvell.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From josephl at nvidia.com  Thu May 23 06:03:57 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 23 May 2013 18:03:57 +0800
Subject: [PATCH] ARM: tegra: add cpu_disable for hotplug
In-Reply-To: <519D363E.4000409@wwwdotorg.org>
References: <1369131215-2920-1-git-send-email-josephl@nvidia.com>
 <519B9DB4.7070106@wwwdotorg.org>
 <20130522090304.GT21944@tbergstrom-lnx.Nvidia.com>
 <519D363E.4000409@wwwdotorg.org>
Message-ID: <1369303437.9559.7.camel@jlo-ubuntu-64.nvidia.com>

On Thu, 2013-05-23 at 05:18 +0800, Stephen Warren wrote:
> On 05/22/2013 03:03 AM, Peter De Schrijver wrote:
> > On Tue, May 21, 2013 at 06:15:48PM +0200, Stephen Warren wrote:
> >> On 05/21/2013 04:13 AM, Joseph Lo wrote:
> >>> The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
> >>> support that. Adding a Tegra specific cpu_disable function for it.
> >>>
> >>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
> >>
> >>> diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
> >>
> >>> +int tegra_cpu_disable(unsigned int cpu)
> >>> +{
> >>> +	switch (tegra_chip_id) {
> >>> +	case TEGRA114:
> >>> +		return 0;
> >>> +	default:
> >>> +		return cpu == 0 ? -EPERM : 0;
> >>> +	}
> >>> +}
> >>
> >> Do we expect all/most future chips to support hotplug of CPU0? Or at
> >> least, fewer chips to have the restriction than not? If so, it might be
> > 
> > Yes. I think we can safely assume future chips will support hotplugging CPU0.
> > 
> >> more forward-looking to write that as:
> >>
> >> if (tegra_chip_id == TEGRA30)
> >>     return cpu == 0 ? -EPERM : 0;
> >>
> > 
> > Also Tegra20 doesn't support hotplugging CPU0?
> 
> Oh right, this isn't a Tegra30+ file. How about just inverting the
> switch so it doesn't need to change later:
> 
> 	switch (tegra_chip_id) {
> 	case TEGRA20:
> 	case TEGRA30:
> 		return cpu == 0 ? -EPERM : 0;
> 	default:
> 		return 0;
> 	}
> 
OK. Will update a newer version later.

Thanks,
Joseph




From gang.chen at asianux.com  Thu May 23 06:05:10 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Thu, 23 May 2013 18:05:10 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <CAMuHMdU7QuzgmWCH145p8PVebBzPo8DBAvbY+0AZa2cmGXmRHw@mail.gmail.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
Message-ID: <519DE9D6.8000707@asianux.com>

On 05/23/2013 05:12 PM, Geert Uytterhoeven wrote:
> On Thu, May 23, 2013 at 11:05 AM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
>> > On Thu, May 23, 2013 at 10:40:29AM +0200, Geert Uytterhoeven wrote:
>>> >> On Thu, May 23, 2013 at 9:57 AM, Chen Gang <gang.chen at asianux.com> wrote:
>>>> >> > -config BUG
>>>> >> > -       bool "BUG() support" if EXPERT
>>>> >> > -       default y
>>>> >> > -       help
>>>> >> > -          Disabling this option eliminates support for BUG and WARN, reducing
>>>> >> > -          the size of your kernel image and potentially quietly ignoring
>>>> >> > -          numerous fatal conditions. You should only consider disabling this
>>>> >> > -          option for embedded systems with no facilities for reporting errors.
>>>> >> > -          Just say Y.
>>> >>
>>> >> ... It's about reducing memory size on devices where you can't show bug or
>>> >> warning messages.
>> >
>> > And turning off CONFIG_BUG causes lots of warning messages at compile time
>> > about functions which are returning nothing which shouldn't.
>> >
>> > The problem is: trying to fix that _will_ mean the result is a larger
>> > kernel than if you just do the usual arch-implemented thing of placing
>> > an defined faulting instruction at the BUG() site - which defeats the
>> > purpose of turning off CONFIG_BUG.
> Is __builtin_unreachable() working well these days?

In fact, using __builtin_unreachable() is a standard way for
architectures to implemented their own BUG() (e.g. x86, s390, powerpc,
arm ...)

Before __builtin_unreachable(), must need an inline asm instruction
which architecture specific.

I have test using __builtin_unreachable() without an related asm
instruction before, it prints many unexpected things (please see the
attachment).

So I think, it is not suitable to use it in "asm-generic/bug.h"


Thanks.
-- 
Chen Gang

Asianux Corporation
-------------- next part --------------
#include <stdio.h>
#include <sys/types.h>
#include <error.h>
#include <errno.h>
#include <fcntl.h>
#include <unistd.h>
#include <sys/stat.h>

int main()
{
	int file;
	int ret;
	char buf[0x100];

	file = open("/tmp/work.c", O_RDONLY);
	if (file == -1) {
		printf("\nopen file failed. errno = %d\n", errno);
		goto err;
	} else
		printf("\nopen file succeed.\n");

	printf("before unreachable\n");
	__builtin_unreachable();
	printf("after unreachable\n");

	if (lseek(file, 10, SEEK_END) < 0) {
		printf("\nlseek file failed. errno = %d\n", errno);
		goto err;
	}

	ret = read(file, buf, 0x100);
	if (ret < 0) {
		printf("\n1st read file failed. errno = %d, ret = %d\n", errno, ret);
		goto err;
	} else
		printf("\n1st read file succeed. errno = %d, ret = %d\n", errno, ret);

	ret = read(file, buf, 0x100);
	if (ret < 0) {
		printf("\n2nd read file failed. errno = %d, ret = %d\n", errno, ret);
		goto err;
	} else
		printf("\n2nd read file succeed. errno = %d, ret = %d\n", errno, ret);

	ret = read(file, buf, 0x100);
	if (ret < 0) {
		printf("\n2rd read file failed. errno = %d, ret = %d\n", errno, ret);
		goto err;
	} else
		printf("\n3rd read file succeed. errno = %d, ret = %d\n", errno, ret);


	return 0;
err:
	return -1;
}


From linux at arm.linux.org.uk  Thu May 23 06:04:09 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 11:04:09 +0100
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since
 always need it.
In-Reply-To: <201305231139.38233.arnd@arndb.de>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de>
Message-ID: <20130523100409.GK18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 11:39:37AM +0200, Arnd Bergmann wrote:
> On Thursday 23 May 2013, Geert Uytterhoeven wrote:
> > > The problem is: trying to fix that will mean the result is a larger
> > > kernel than if you just do the usual arch-implemented thing of placing
> > > an defined faulting instruction at the BUG() site - which defeats the
> > > purpose of turning off CONFIG_BUG.
> > 
> > Is __builtin_unreachable() working well these days?
> > 
> 
> Hmm, I just tried the trivial patch below, which seemed to do the right thing.
> Needs a little more investigation, but that might actually be the correct
> solution. I thought that at some point __builtin_unreachable() was the same
> as "do {} while (1)", but this is not the case with the gcc I was using --
> it just tells gcc that we don't expect to ever get here.

All this is doing is hiding the warning, nothing more.

What the compiler does is this:

	beq	1f
	... some asm code ...
	__builtin_reachable() point
	maybe a literal table
1:	... some asm code doing some other part of the function ...

and what will happen is that the first block of asm will fall through the
(possibly present) literal table into the following asm code.  So, as
specified in the gcc manual, if you ever hit a __builtin_unreachable()
point, your program is undefined (as in, the behaviour of it can no longer
be known.)

We can't make that guarantee with BUG() - because sometimes they do fire
and sometimes in the most unlikely scenarios, particularly if you're not
looking, or at the most inconvenient time.

So, if you want to use this, then you should update the CONFIG_BUG text
to include a warning to this effect:

     Warning: if CONFIG_BUG is turned off, and control flow reaches
     a BUG(), the system behaviour will be undefined.

so that people can make an informed choice about this, because at the
moment:

          Disabling this option eliminates support for BUG and WARN, reducing
          the size of your kernel image and potentially quietly ignoring
          numerous fatal conditions. You should only consider disabling this
          option for embedded systems with no facilities for reporting errors.
          Just say Y.

will become completely misleading.  Turning this option off will _not_
result in "quietly ignoring numerous fatal conditions".

And I come back to one of my previous arguments - is it not better to
panic() if we hit one of these conditions so that the system can try to
do a panic-reboot rather than continue blindly into the unknown?


From thomas.petazzoni at free-electrons.com  Thu May 23 06:09:20 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 12:09:20 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <519DE6A8.6040502@overkiz.com>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com>
Message-ID: <20130523120920.1df8e23a@skate>

Dear boris brezillon,

On Thu, 23 May 2013 11:51:36 +0200, boris brezillon wrote:
> On 23/05/2013 11:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 11:05 Thu 23 May     , Boris BREZILLON wrote:
> >> Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
> >> Move arch/arm/mach-at91/at91_aic.h to
> >> arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
> >> to header file :
> >> #include "../../arch/arm/mach-at91/at91_aic.h"
> > no we are going to drop arch/arm/mach-at91/include/mach for multi support
> >
> > arch/arm/mach-at91/include/mach is for removal
> What should be done ?
> 
> include ../../arch/arm/mach-at91/at91_aic.h from irq-at91.c
> 
> or
> 
> move at91_aic.h into drivers/irqchips and patch every non dt board to
> include ../../../drivers/irqchip/at91_aic.h

You can put it in <linux/irqchip/at91-aic.h>, there are already a few
headers there. But I think it's not the right solution.

*However*, ideally, this header should disappear completely. All the
register defines should go directly into the driver C file. The only
usage of the AIC defines outside of the IRQ driver are for debug prints
in the pm.c code, which I think you could get rid of.

Ditto for the at91_aic_{read,write} macros.

The NR_AIC5_IRQS can also move to the driver itself.

The only remaining one would be NR_AIC_IRQS, you can't get rid of it,
because it's used for the IRQ priority arrays. But I believe keeping
this one in <linux/irqchip/at91-aic.h> is reasonable.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From ebiederm at xmission.com  Thu May 23 06:09:50 2013
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Thu, 23 May 2013 03:09:50 -0700
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <201305231139.38233.arnd@arndb.de> (Arnd Bergmann's message of
 "Thu, 23 May 2013 11:39:37 +0200")
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de>
Message-ID: <878v369fdd.fsf@xmission.com>

Arnd Bergmann <arnd at arndb.de> writes:

> On Thursday 23 May 2013, Geert Uytterhoeven wrote:
>> > The problem is: trying to fix that will mean the result is a larger
>> > kernel than if you just do the usual arch-implemented thing of placing
>> > an defined faulting instruction at the BUG() site - which defeats the
>> > purpose of turning off CONFIG_BUG.
>> 
>> Is __builtin_unreachable() working well these days?
>> 
>
> Hmm, I just tried the trivial patch below, which seemed to do the right thing.
> Needs a little more investigation, but that might actually be the correct
> solution. I thought that at some point __builtin_unreachable() was the same
> as "do {} while (1)", but this is not the case with the gcc I was using --
> it just tells gcc that we don't expect to ever get here.

Yes.

We already have this abstracted in compiler.h as the macro unreachable,
so the slight modification of your patch below should handle this case.

For compilers without __builtin_unreachable() unreachable() expands to
do {} while(1) but an infinite loop seems reasonable and preserves the
semantics of the code, unlike the current noop that is do {} while(0).

> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..9afff7d 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -108,11 +108,11 @@ extern void warn_slowpath_null(const char *file, const int line);
 
 #else /* !CONFIG_BUG */
 #ifndef HAVE_ARCH_BUG
-#define BUG() do {} while(0)
+#define BUG() unreachable ()
 #endif
 
 #ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
+#define BUG_ON(condition) do { if (condition) unreachable(); } while(0)
 #endif
 
 #ifndef HAVE_ARCH_WARN_ON


From plagnioj at jcrosoft.com  Thu May 23 06:09:51 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 12:09:51 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523120920.1df8e23a@skate>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com> <20130523120920.1df8e23a@skate>
Message-ID: <20130523100951.GH9937@game.jcrosoft.org>

On 12:09 Thu 23 May     , Thomas Petazzoni wrote:
> Dear boris brezillon,
> 
> On Thu, 23 May 2013 11:51:36 +0200, boris brezillon wrote:
> > On 23/05/2013 11:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 11:05 Thu 23 May     , Boris BREZILLON wrote:
> > >> Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
> > >> Move arch/arm/mach-at91/at91_aic.h to
> > >> arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
> > >> to header file :
> > >> #include "../../arch/arm/mach-at91/at91_aic.h"
> > > no we are going to drop arch/arm/mach-at91/include/mach for multi support
> > >
> > > arch/arm/mach-at91/include/mach is for removal
> > What should be done ?
> > 
> > include ../../arch/arm/mach-at91/at91_aic.h from irq-at91.c
> > 
> > or
> > 
> > move at91_aic.h into drivers/irqchips and patch every non dt board to
> > include ../../../drivers/irqchip/at91_aic.h
> 
> You can put it in <linux/irqchip/at91-aic.h>, there are already a few
> headers there. But I think it's not the right solution.
> 
> *However*, ideally, this header should disappear completely. All the
> register defines should go directly into the driver C file. The only
> usage of the AIC defines outside of the IRQ driver are for debug prints
> in the pm.c code, which I think you could get rid of.
> 
> Ditto for the at91_aic_{read,write} macros.
> 
> The NR_AIC5_IRQS can also move to the driver itself.
> 
> The only remaining one would be NR_AIC_IRQS, you can't get rid of it,
> because it's used for the IRQ priority arrays. But I believe keeping
> this one in <linux/irqchip/at91-aic.h> is reasonable.

do want either as we expose the register acces for pm & co

until this is cleanup NACK

Best Regards,
J.


From josh.wu at atmel.com  Thu May 23 06:18:48 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 23 May 2013 18:18:48 +0800
Subject: [PATCH] at91: sama5: fix incorrect PMC pcr div definition
Message-ID: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>


Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
 arch/arm/mach-at91/include/mach/at91_pmc.h |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 31df120..2bd7f51 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base;
 #define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command (read=0, write=1) */
 #define		AT91_PMC_PCR_DIV(n)	((n)  <<  16)		/* Divisor Value */
 #define			AT91_PMC_PCR_DIV0	0x0			/* Peripheral clock is MCK */
-#define			AT91_PMC_PCR_DIV2	0x2			/* Peripheral clock is MCK/2 */
-#define			AT91_PMC_PCR_DIV4	0x4			/* Peripheral clock is MCK/4 */
-#define			AT91_PMC_PCR_DIV8	0x8			/* Peripheral clock is MCK/8 */
+#define			AT91_PMC_PCR_DIV2	0x1			/* Peripheral clock is MCK/2 */
+#define			AT91_PMC_PCR_DIV4	0x2			/* Peripheral clock is MCK/4 */
+#define			AT91_PMC_PCR_DIV8	0x3			/* Peripheral clock is MCK/8 */
 #define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
 
 #endif
-- 
1.7.10



From linux at arm.linux.org.uk  Thu May 23 06:18:25 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 11:18:25 +0100
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
Message-ID: <20130523101825.GL18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 11:05:07AM +0200, Boris BREZILLON wrote:
> Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
> Move arch/arm/mach-at91/at91_aic.h to
> arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
> to header file :
> #include "../../arch/arm/mach-at91/at91_aic.h"

The right way to do this is to move the definitions which should only
be used by arch/arm/mach-at91/irq.c to that file or a header file along
side that file, and find a place in include/linux for the remainder.

I notice arch/arm/mach-at91/pm.c makes use of some of the register
definitions:

        at91_irq_suspend();

        pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
                        /* remember all the always-wake irqs */
                        (at91_pmc_read(AT91_PMC_PCSR)
                                        | (1 << AT91_ID_FIQ)
                                        | (1 << AT91_ID_SYS)
                                        | (at91_extern_irq))
                                & at91_aic_read(AT91_AIC_IMR),
                        state);

at91_irq_suspend() is in arch/arm/mach-at91/irq.c already, so there's no
reason that fragment can't be moved there.

That leaves: at91_aic_handle_irq, at91_aic5_handle_irq, NR_AIC_IRQS and
NR_AIC5_IRQS, which if you did patch 3 first, would leave you with just
the NR_.*_IRQS definitions to find a home for.


From linux at arm.linux.org.uk  Thu May 23 06:19:21 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 11:19:21 +0100
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369296978-7669-2-git-send-email-b32955@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-2-git-send-email-b32955@freescale.com>
Message-ID: <20130523101921.GM18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 04:16:13PM +0800, Huang Shijie wrote:
> +	/* get the clock */
> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(weim->clk))
> +		goto weim_err;
> +
> +	clk_prepare_enable(weim->clk);

I notice people are getting lazy about this.  clk_prepare_enable() can
return an error...


From thomas.petazzoni at free-electrons.com  Thu May 23 06:20:00 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 12:20:00 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523100951.GH9937@game.jcrosoft.org>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com> <20130523120920.1df8e23a@skate>
 <20130523100951.GH9937@game.jcrosoft.org>
Message-ID: <20130523122000.22a9a4d0@skate>

Dear Jean-Christophe PLAGNIOL-VILLARD,

On Thu, 23 May 2013 12:09:51 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:

> > You can put it in <linux/irqchip/at91-aic.h>, there are already a few
> > headers there. But I think it's not the right solution.
> > 
> > *However*, ideally, this header should disappear completely. All the
> > register defines should go directly into the driver C file. The only
> > usage of the AIC defines outside of the IRQ driver are for debug prints
> > in the pm.c code, which I think you could get rid of.
> > 
> > Ditto for the at91_aic_{read,write} macros.
> > 
> > The NR_AIC5_IRQS can also move to the driver itself.
> > 
> > The only remaining one would be NR_AIC_IRQS, you can't get rid of it,
> > because it's used for the IRQ priority arrays. But I believe keeping
> > this one in <linux/irqchip/at91-aic.h> is reasonable.
> 
> do want either as we expose the register acces for pm & co

Did you read what I write? In arch/arm/mach-at91/pm.c, the only
accesses made to the AIC registers are for pr_debug() calls, i.e only
to print some debugging messages. I believe those ones can simply be
removed to decouple the pm.c code from the irq.c code.

> until this is cleanup NACK

Is this really the way we want to welcome contributions in the kernel
community?

Boris, what you'd have to do is just do a few preparations patches
in your patch set. Something like:

 * PATCH 1: remove usage of AIC registers for debug messages in pm.c
 * PATCH 2: move all of at91_aic.h in irq.c, except NR_AIC_IRQS
 * PATCH 3: move irq.c to drivers/irqchip/, and at91_aic.h to
   include/linux/irqchip/, and adjust what's necessary
 * and then your other patches.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From nicolas.ferre at atmel.com  Thu May 23 06:22:32 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 May 2013 12:22:32 +0200
Subject: [PATCH 1/7] USB: gadget: atmel_usba: move global struct usba_ep
 usba_ep to struct usba_udc
In-Reply-To: <519D7D9F.1070109@atmel.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
 <519D7D9F.1070109@atmel.com>
Message-ID: <519DEDE8.3040503@atmel.com>

On 23/05/2013 04:23, Bo Shen :
> Hi J,
>
> On 5/21/2013 00:25, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> so we can have multiple usb gadget instance
>>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>> Cc: linux-usb at vger.kernel.org
>
> For this series, test OK on at91sam9m10g45ek and at91sam9x5ek board
> Tested-by: Bo Shen <voice.shen at atmel.com>

After reading this v4 series, it seems good. So, on the whole series:

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> PS: When do testing, we need build in or choose as module: "Device
> Drivers ---> Generic Target Core Mod (TCM) and ConfigFS infrastructure"

Thanks a lot to you, Bo and Jean-Christophe.

Bye,
-- 
Nicolas Ferre


From plagnioj at jcrosoft.com  Thu May 23 06:26:01 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 12:26:01 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523122000.22a9a4d0@skate>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com> <20130523120920.1df8e23a@skate>
 <20130523100951.GH9937@game.jcrosoft.org>
 <20130523122000.22a9a4d0@skate>
Message-ID: <20130523102601.GI9937@game.jcrosoft.org>

On 12:20 Thu 23 May     , Thomas Petazzoni wrote:
> Dear Jean-Christophe PLAGNIOL-VILLARD,
> 
> On Thu, 23 May 2013 12:09:51 +0200, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
> 
> > > You can put it in <linux/irqchip/at91-aic.h>, there are already a few
> > > headers there. But I think it's not the right solution.
> > > 
> > > *However*, ideally, this header should disappear completely. All the
> > > register defines should go directly into the driver C file. The only
> > > usage of the AIC defines outside of the IRQ driver are for debug prints
> > > in the pm.c code, which I think you could get rid of.
> > > 
> > > Ditto for the at91_aic_{read,write} macros.
> > > 
> > > The NR_AIC5_IRQS can also move to the driver itself.
> > > 
> > > The only remaining one would be NR_AIC_IRQS, you can't get rid of it,
> > > because it's used for the IRQ priority arrays. But I believe keeping
> > > this one in <linux/irqchip/at91-aic.h> is reasonable.
> > 
> > do want either as we expose the register acces for pm & co
> 
> Did you read what I write? In arch/arm/mach-at91/pm.c, the only
> accesses made to the AIC registers are for pr_debug() calls, i.e only
> to print some debugging messages. I believe those ones can simply be
> removed to decouple the pm.c code from the irq.c code.

yes I read and yes I do not want to move code before we do cleanup MANDATORY

unclean code in mach-at91 is fine this is legacy, move them arround NACK

we cleanup first
> 
> > until this is cleanup NACK
> 
> Is this really the way we want to welcome contributions in the kernel
> community?
> 
> Boris, what you'd have to do is just do a few preparations patches
> in your patch set. Something like:
> 
>  * PATCH 1: remove usage of AIC registers for debug messages in pm.c
NACK I do want this debug, very usefull to debug pm

Best Regards,
J.
>  * PATCH 2: move all of at91_aic.h in irq.c, except NR_AIC_IRQS
>  * PATCH 3: move irq.c to drivers/irqchip/, and at91_aic.h to
>    include/linux/irqchip/, and adjust what's necessary
>  * and then your other patches.
> 
> Best regards,
> 
> Thomas
> -- 
> Thomas Petazzoni, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com


From linux at arm.linux.org.uk  Thu May 23 06:29:34 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 11:29:34 +0100
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since
 always need it.
In-Reply-To: <878v369fdd.fsf@xmission.com>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de> <878v369fdd.fsf@xmission.com>
Message-ID: <20130523102934.GN18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 03:09:50AM -0700, Eric W. Biederman wrote:
> Arnd Bergmann <arnd at arndb.de> writes:
> 
> > On Thursday 23 May 2013, Geert Uytterhoeven wrote:
> >> > The problem is: trying to fix that will mean the result is a larger
> >> > kernel than if you just do the usual arch-implemented thing of placing
> >> > an defined faulting instruction at the BUG() site - which defeats the
> >> > purpose of turning off CONFIG_BUG.
> >> 
> >> Is __builtin_unreachable() working well these days?
> >> 
> >
> > Hmm, I just tried the trivial patch below, which seemed to do the right thing.
> > Needs a little more investigation, but that might actually be the correct
> > solution. I thought that at some point __builtin_unreachable() was the same
> > as "do {} while (1)", but this is not the case with the gcc I was using --
> > it just tells gcc that we don't expect to ever get here.
> 
> Yes.
> 
> We already have this abstracted in compiler.h as the macro unreachable,
> so the slight modification of your patch below should handle this case.
> 
> For compilers without __builtin_unreachable() unreachable() expands to
> do {} while(1) but an infinite loop seems reasonable and preserves the
> semantics of the code, unlike the current noop that is do {} while(0).

Semantics of the code really don't come in to it if you use unreachable().
unreachable() is an effective do { } while (0) to the compiler.  It just
doesn't warn about it anymore.  It's actually worse than that - it's
permission to the compiler to just stop considering flow control at that
point and do anything it likes with the following instruction slot.

What __builtin_unreachable() means to the compiler is "we will *never*
get here".  That isn't the case for BUG() - BUG() means "we hope that
we will never get here, but we might, and if we do your data is in
grave danger."

We should either have something at that point (like a call to a function
which panics) or remove the ability to turn off CONFIG_BUG and anyone who
cares about kernel size needs to come up with a single trapping
instruction BUG() implementation.


From lorenzo.pieralisi at arm.com  Thu May 23 06:33:15 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 23 May 2013 11:33:15 +0100
Subject: [GIT PULL] ARM DT cpus/cpu bindings documentation updates
Message-ID: <20130523103315.GA2866@e102568-lin.cambridge.arm.com>

Hi Grant, Rob,

please pull the cpus/cpu nodes bindings updates for ARM. This pull
request completes my previous pull request:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/169110.html

with the required changes for cpus/cpu nodes.

Thanks a lot,
Lorenzo

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://linux-arm.org/linux-2.6-lp.git dt-cpus-bindings

for you to fetch changes up to 8e11f862d6a5491bb5f8ef73e13cfd66562e7be3:

  Documentation: devicetree: arm: cpus/cpu nodes bindings updates (2013-05-23 10:46:46 +0100)

----------------------------------------------------------------
Lorenzo Pieralisi (1):
      Documentation: devicetree: arm: cpus/cpu nodes bindings updates

 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)



From t.figa at samsung.com  Thu May 23 06:37:54 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 23 May 2013 12:37:54 +0200
Subject: [PATCH] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
In-Reply-To: <120501ce5752$6daef380$490cda80$%kim@samsung.com>
References: <1368630484-29939-1-git-send-email-t.figa@samsung.com>
 <1623377.nVo7nUcid2@flatron> <120501ce5752$6daef380$490cda80$%kim@samsung.com>
Message-ID: <1781627.0kos608bv1@amdc1227>

Hi Kukjin,

On Thursday 23 of May 2013 10:11:17 Kukjin Kim wrote:
> Kukjin Kim wrote:
> > Tomasz Figa wrote:
> > > Hi Kukjin,
> > 
> > Hi,
> > 
> > > On Wednesday 15 of May 2013 17:08:04 Tomasz Figa wrote:
> > > > This patch extends exynos_init_time() function to handle Exynos4210
> > 
> > rev0
> > 
> > > > SoC, which differs in availability of system timers and needs
> > 
> > different
> > 
> > > > clocksource initialization.
> > > > 
> > > > This makes it possible to use exynos_init_time() function as init_time
> > > > callback for all Exynos-based boards, including Universal_C210, which
> > > > originally had to use samsung_timer_init().
> > > > 
> > > > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > > > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > > > ---
> > > > 
> > > >  arch/arm/mach-exynos/Kconfig               |  3 ++-
> > > >  arch/arm/mach-exynos/common.c              | 30
> > > > 
> > > > +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h
> > > > 
> > > >   |  2 ++
> > > >  
> > > >  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++---
> > > >  4 files changed, 35 insertions(+), 5 deletions(-)
> > > 
> > > Could you pick this patch to your fixes branch?
> > 
> > Yeah, I will after looking at.
> > 
> > > This is a fix of a regression in handling Exynos4210 rev0 SoC (e.g.
> > > Universal C210 board) introduced by patches merged to 3.10.
> > 
> > OK, I see but I didn't review yet and I  will within a couple of days ;-)
> 
> OK, looks fine, this will be sent to upstream during -rc for v3.10.

Thanks.

> But, Tomasz, as you know, non-DT supporting files will be gone away in
> v3.11, just note.

Sure. This is a good thing.

In 3.11 Universal C210 will be supported only using device tree, but for 3.10 
we need this patch to make the old board file still work.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics


From gang.chen at asianux.com  Thu May 23 06:41:34 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Thu, 23 May 2013 18:41:34 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <20130523100409.GK18614@n2100.arm.linux.org.uk>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
Message-ID: <519DF25E.7060304@asianux.com>

On 05/23/2013 06:04 PM, Russell King - ARM Linux wrote:
> So, if you want to use this, then you should update the CONFIG_BUG text
> to include a warning to this effect:
> 
>      Warning: if CONFIG_BUG is turned off, and control flow reaches
>      a BUG(), the system behaviour will be undefined.
> 
> so that people can make an informed choice about this, because at the
> moment:
> 
>           Disabling this option eliminates support for BUG and WARN, reducing
>           the size of your kernel image and potentially quietly ignoring
>           numerous fatal conditions. You should only consider disabling this
>           option for embedded systems with no facilities for reporting errors.
>           Just say Y.
> 
> will become completely misleading.  Turning this option off will _not_
> result in "quietly ignoring numerous fatal conditions".
> 
> And I come back to one of my previous arguments - is it not better to
> panic() if we hit one of these conditions so that the system can try to
> do a panic-reboot rather than continue blindly into the unknown?

But I still suggest to delete CONFIG_BUG in common kernel.

Since currently, disable 'CONFIG_BUG' is not a common features (most of
architectures are always enable it), it is only belongs to some
architectures specific features (may some embedded systems).

It is not suitable to still let 'CONFIG_BUG' exist in
"asm-generic/bug.h" which is only for common features.

And each architecture can customize their own BUG(), if one architecture
wants to Disabling this option, let it specify its own BUG().

So, most of architectures need not consider this issue again.


Thanks.
-- 
Chen Gang

Asianux Corporation


From catalin.marinas at arm.com  Thu May 23 06:43:03 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 11:43:03 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130523104303.GC16722@arm.com>

On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> it needs to handle are kernel mapped only.  However, for example when doing
> direct I/O, pages with user space mappings may occur.
> 
> Thus, continue to do lazy flushing if there are no user space mappings.
> Otherwise, flush the kernel cache lines directly.
> 
> Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Russell King <linux at arm.linux.org.uk>

An issue is that for kunmap_atomic() && VIVT we flush the same page
twice. I don't think we should remove the cache flushing in
__kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
flush_kernel_dcache_page() (unless we just assume that highmem && vivt
don't work together). Flushing the VIVT cache on kunmap is essential
since we just lose the alias after that.

> +void flush_kernel_dcache_page(struct page *page)
> +{
> +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {

So you could add the ((cache_is_vivt() || cache_is_vipt_aliasing()) &&
!PageHighMem(page)) check back (as it was prior to commit f8b63c184,
actually reverting it) and the mapping tests as a possible optimisation.
But in this case there is no need to split __flush_dcache_page() in two
since we don't care about the PageHighMem() case.

And we need to fix kunmap() with VIVT to flush the cache as well (in
case anyone uses highmem on VIVT hardware).

-- 
Catalin


From arunkk.samsung at gmail.com  Thu May 23 06:43:31 2013
From: arunkk.samsung at gmail.com (Arun Kumar K)
Date: Thu, 23 May 2013 16:13:31 +0530
Subject: [PATCH] clk: exynos5250: Added MUX, DIV and GATE clocks for
 Gscaler and MFC
In-Reply-To: <1364271986-30491-1-git-send-email-prasanna.ps@samsung.com>
References: <1364271986-30491-1-git-send-email-prasanna.ps@samsung.com>
Message-ID: <CALt3h78RSAPYAjPA-sODQtckTTDtwdyU71hCmbgthXSjGQk0=Q@mail.gmail.com>

NAK

In testing we have seen that, when sysmmu of mfc/gscl is used,
the respective IP clock has to be ON, or else it was malfunctioning.
So for smmu_mfcl and smmu_mfcr, the parent should be mfc
so that we make sure the parent is turned on every time sysmmu is accessed.
Same thing applies to gscl also.

Regards
Arun Kumar

On Tue, Mar 26, 2013 at 9:56 AM, Prasanna Kumar <prasanna.ps at samsung.com> wrote:
> From: Prasanna Kumar <prasanna.ps at samsung.com>
>
> Gscaler :
>
>   1. For "aclk_300_gscl",following clocks are added
>           Mux clocks
>                 mout_aclk_300_gscl_mid,
>                 mout_aclk_300_gscl_mid1,
>                 mout_aclk_300_gscl
>           Divider clock
>                 div_aclk300_gscl
>           Sub-Mux clock ( driven from output of divider clock)
>                 mout_sub_aclk300
>   2. For "aclk_266_gscl",
>            Sub-Mux clock "mout_sub_aclk266" added
>            Divider clock has been modified to refer Sub-Mux clock
>
> MFC :
>    For "aclk_333"
>         Sub-Mux clock "mout_sub_aclk333" added
>            Divider clock has been modified to refer Sub-Mux clock
> Signed-off-by: Prasanna Kumar <prasanna.ps at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |   57 +++++++++++++++++++++++++--------
>  1 files changed, 43 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index e40d6af..40dff9d 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -24,7 +24,9 @@
>  #define DIV_CPU0               0x500
>  #define SRC_CORE1              0x4204
>  #define SRC_TOP0               0x10210
> +#define SRC_TOP1               0x10214
>  #define SRC_TOP2               0x10218
> +#define SRC_TOP3               0x1021C
>  #define SRC_GSCL               0x10220
>  #define SRC_DISP1_0            0x1022c
>  #define SRC_MAU                        0x10240
> @@ -112,7 +114,9 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
>         DIV_CPU0,
>         SRC_CORE1,
>         SRC_TOP0,
> +       SRC_TOP1,
>         SRC_TOP2,
> +       SRC_TOP3,
>         SRC_GSCL,
>         SRC_DISP1_0,
>         SRC_MAU,
> @@ -167,6 +171,13 @@ PNAME(mout_mpll_user_p)    = { "fin_pll", "sclk_mpll" };
>  PNAME(mout_bpll_user_p)        = { "fin_pll", "sclk_bpll" };
>  PNAME(mout_aclk166_p)  = { "sclk_cpll", "sclk_mpll_user" };
>  PNAME(mout_aclk200_p)  = { "sclk_mpll_user", "sclk_bpll_user" };
> +PNAME(mout_sub_aclk266_p) = { "fin_pll", "div_aclk266" };
> +PNAME(mout_aclk_300_gscl_mid_p) = { "sclk_mpll_user", "sclk_bpll_user"};
> +PNAME(mout_aclk_300_gscl_mid1_p) = { "sclk_vpll", "sclk_cpll"};
> +PNAME(mout_aclk_300_gscl_p) = { "mout_aclk_300_gscl_mid",
> +                                       "mout_aclk_300_gscl_mid1" };
> +PNAME(mout_sub_aclk300_p) = { "fin_pll", "div_aclk300_gscl" };
> +PNAME(mout_sub_aclk333_p) = { "fin_pll", "div_aclk333" };
>  PNAME(mout_hdmi_p)     = { "div_hdmi_pixel", "sclk_hdmiphy" };
>  PNAME(mout_usb3_p)     = { "sclk_mpll_user", "sclk_cpll" };
>  PNAME(mout_group1_p)   = { "fin_pll", "fin_pll", "sclk_hdmi27m",
> @@ -220,8 +231,20 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
>         MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
>         MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
>         MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
> -       MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
>         MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
> +       MUX_A(none, "mout_sub_aclk266", mout_sub_aclk266_p,
> +                                       SRC_TOP3, 8, 1, "m_sub_aclk266"),
> +       MUX(none, "mout_aclk_300_gscl", mout_aclk_300_gscl_p,
> +                                               SRC_TOP0, 25, 1),
> +       MUX(none, "mout_aclk_300_gscl_mid", mout_aclk_300_gscl_mid_p,
> +                                               SRC_TOP0, 24, 1),
> +       MUX(none, "mout_aclk_300_gscl_mid1", mout_aclk_300_gscl_mid1_p,
> +                                               SRC_TOP1, 12, 1),
> +       MUX_A(none, "mout_sub_aclk300", mout_sub_aclk300_p,
> +                                       SRC_TOP3, 10, 1, "m_sub_aclk300"),
> +       MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
> +       MUX_A(none, "mout_sub_aclk333", mout_sub_aclk333_p,
> +                                       SRC_TOP3, 24, 1, "m_sub_aclk333"),
>         MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
>         MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
>         MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
> @@ -257,10 +280,12 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>         DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
>         DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
>         DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
> -       DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
>         DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
> -       DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
>         DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
> +       DIV(none, "div_aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
> +       DIV(none, "div_aclk300_gscl", "mout_aclk_300_gscl",
> +                                               DIV_TOP1, 14, 3),
> +       DIV(none, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
>         DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
>         DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
>         DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
> @@ -313,19 +338,23 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>  };
>
>  struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
> -       GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
> -       GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
> -       GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
> -       GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
> +       GATE(gscl0, "gscl0", "mout_sub_aclk266", GATE_IP_GSCL, 0, 0, 0),
> +       GATE(gscl1, "gscl1", "mout_sub_aclk266", GATE_IP_GSCL, 1, 0, 0),
> +       GATE(gscl2, "gscl2", "mout_sub_aclk266", GATE_IP_GSCL, 2, 0, 0),
> +       GATE(gscl3, "gscl3", "mout_sub_aclk266", GATE_IP_GSCL, 3, 0, 0),
>         GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
>         GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
> -       GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
> -       GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
> -       GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
> -       GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
> -       GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
> -       GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
> -       GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
> +       GATE(smmu_gscl0, "smmu_gscl0", "mout_sub_aclk266",
> +                                               GATE_IP_GSCL, 7, 0, 0),
> +       GATE(smmu_gscl1, "smmu_gscl1", "mout_sub_aclk266",
> +                                               GATE_IP_GSCL, 8, 0, 0),
> +       GATE(smmu_gscl2, "smmu_gscl2", "mout_sub_aclk266",
> +                                               GATE_IP_GSCL, 9, 0, 0),
> +       GATE(smmu_gscl3, "smmu_gscl3", "mout_sub_aclk266",
> +                                               GATE_IP_GSCL, 10, 0, 0),
> +       GATE(mfc, "mfc", "mout_sub_aclk333", GATE_IP_MFC, 0, 0, 0),
> +       GATE(smmu_mfcl, "smmu_mfcl", "mout_sub_aclk333", GATE_IP_MFC, 1, 0, 0),
> +       GATE(smmu_mfcr, "smmu_mfcr", "mout_sub_aclk333", GATE_IP_MFC, 2, 0, 0),
>         GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
>         GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
>         GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From vinod.koul at intel.com  Thu May 23 06:09:32 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 23 May 2013 15:39:32 +0530
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <20130521151143.GH10453@mudshark.cambridge.arm.com>
 <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
Message-ID: <20130523100932.GA30200@intel.com>

On Tue, May 21, 2013 at 08:24:15PM +0300, Andy Shevchenko wrote:
> On Tue, May 21, 2013 at 6:11 PM, Will Deacon <will.deacon at arm.com> wrote:
> > Hi Andy,
> >
> > On Tue, May 21, 2013 at 01:33:17PM +0100, Andy Shevchenko wrote:
> >> When thread is going to be stopped we have to unconditionally terminate all
> >> ongoing transfers. Otherwise it would be possible that callback function will
> >> be called on the next interrupt and will try to access to already freed
> >> structures.
> >>
> >> The patch introduces specific error message for this, though it doesn't
> >> increase the counter of the failed tests.
> >>
> >> Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
> >> Reported-by: Will Deacon <will.deacon at arm.com>
> >
> > Thanks for persevering with this! Although this patch definitely fixes the
> > panic I was seeing, I now observe buffer verification failures in subsequent
> > test runs after an aborted run:
> 
> I think the description to the commit adfa543e "dmatest: don't use
> set_freezable_with_signal()" may shed light on this.
> 
> The background (if  I got it correctly) is in race with done flag. So,
> we got a callback call from the DMA engine, but we don't know which
> transfer triggers it.
> I might be wrong. This is just an assumption.
> 
> Have you ever see such behaviour on pre v3.10-rc1 kernels? (I mean
> with old dmatest module)
Terminate shouldnt cause the issue with buffer verfication, can you try this on
dw_dmac, do you see similar failures on verfication?

--
~Vinod


From catalin.marinas at arm.com  Thu May 23 06:46:07 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 11:46:07 +0100
Subject: [PATCH v4 22/32] arm64: KVM: define 32bit specific registers
In-Reply-To: <1368540840-26750-23-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-23-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523104607.GD16722@arm.com>

On Tue, May 14, 2013 at 03:13:50PM +0100, Marc Zyngier wrote:
> Define the 32bit specific registers (SPSRs, cp15...).
> 
> Most CPU registers are directly mapped to a 64bit register
> (r0->x0...). Only the SPSRs have separate registers.
> 
> cp15 registers are also mapped into their 64bit counterpart in most
> cases.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Thu May 23 06:48:32 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 11:48:32 +0100
Subject: [PATCH v4 23/32] arm64: KVM: 32bit GP register access
In-Reply-To: <1368540840-26750-24-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-24-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523104832.GE16722@arm.com>

On Tue, May 14, 2013 at 03:13:51PM +0100, Marc Zyngier wrote:
> Allow access to the 32bit register file through the usual API.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From lorenzo.pieralisi at arm.com  Thu May 23 06:48:58 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 23 May 2013 11:48:58 +0100
Subject: [GIT PULL] ARM dts cpus/cpu nodes updates
Message-ID: <20130523104858.GA2986@e102568-lin.cambridge.arm.com>

Hi Arnd, Olof,

please pull dts cpus/cpu node updates for all non-compliant ARM
SoC/boards. Please notice I could not update all dts files since some of
them are missing the cpus node altogether and I simply can not know
the CPUs configuration for them, it is up to maintainers to patch the
respective dts to comply with the latest specification.

I have just sent a different pull request for related documentation:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/170234.html

dts updates comply with those Documentation updates.

Thank you very much indeed,
Lorenzo

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://linux-arm.org/linux-2.6-lp.git dts-cpus-updates

for you to fetch changes up to 14c44aa541744d4cf06db89c27a1e6df293c64d5:

  ARM: dts: sunxi: cpus/cpu nodes dts updates (2013-05-23 10:45:22 +0100)

----------------------------------------------------------------
Lorenzo Pieralisi (14):
      ARM: dts: am33xx: cpus/cpu nodes dts updates
      ARM: dts: armada-370-xp: cpus/cpu node dts updates
      ARM: dts: at91: cpus/cpu node dts updates
      ARM: dts: exynos5440: cpus/cpu nodes dts updates
      ARM: dts: imx: cpus/cpu nodes dts updates
      ARM: dts: lpc32xx: cpus/cpu nodes dts updates
      ARM: dts: omap: cpus/cpu nodes dts updates
      ARM: dts: picoxcell: cpus/cpu nodes dts updates
      ARM: dts: prima2: cpus/cpu node dts updates
      ARM: dts: pxa2xx: cpus/cpu nodes dts updates
      ARM: dts: r8a7740: cpus/cpu nodes dts updates
      ARM: dts: sh7372: cpus/cpu nodes dts updates
      ARM: dts: spear: cpus/cpu nodes dts updates
      ARM: dts: sunxi: cpus/cpu nodes dts updates

 arch/arm/boot/dts/am33xx.dtsi          | 4 ++++
 arch/arm/boot/dts/armada-370-xp.dtsi   | 4 ++++
 arch/arm/boot/dts/at91rm9200.dtsi      | 6 +++++-
 arch/arm/boot/dts/at91sam9260.dtsi     | 8 ++++++--
 arch/arm/boot/dts/at91sam9263.dtsi     | 8 ++++++--
 arch/arm/boot/dts/at91sam9g45.dtsi     | 8 ++++++--
 arch/arm/boot/dts/at91sam9n12.dtsi     | 8 ++++++--
 arch/arm/boot/dts/at91sam9x5.dtsi      | 8 ++++++--
 arch/arm/boot/dts/exynos5440.dtsi      | 4 ++++
 arch/arm/boot/dts/imx23.dtsi           | 8 ++++++--
 arch/arm/boot/dts/imx28.dtsi           | 8 ++++++--
 arch/arm/boot/dts/imx6dl.dtsi          | 2 ++
 arch/arm/boot/dts/imx6q.dtsi           | 4 ++++
 arch/arm/boot/dts/lpc32xx.dtsi         | 8 ++++++--
 arch/arm/boot/dts/omap2.dtsi           | 6 +++++-
 arch/arm/boot/dts/omap3.dtsi           | 5 +++++
 arch/arm/boot/dts/omap4.dtsi           | 7 +++++++
 arch/arm/boot/dts/omap5.dtsi           | 7 +++++++
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 ++++----
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 ++++----
 arch/arm/boot/dts/prima2.dtsi          | 2 ++
 arch/arm/boot/dts/pxa2xx.dtsi          | 7 +++++--
 arch/arm/boot/dts/r8a7740.dtsi         | 4 ++++
 arch/arm/boot/dts/sama5d3.dtsi         | 2 ++
 arch/arm/boot/dts/sh7372.dtsi          | 5 +++++
 arch/arm/boot/dts/spear13xx.dtsi       | 2 ++
 arch/arm/boot/dts/spear3xx.dtsi        | 8 ++++++--
 arch/arm/boot/dts/spear600.dtsi        | 8 ++++++--
 arch/arm/boot/dts/sun4i-a10.dtsi       | 2 ++
 arch/arm/boot/dts/sun5i-a13.dtsi       | 2 ++
 30 files changed, 139 insertions(+), 32 deletions(-)



From andy.shevchenko at gmail.com  Thu May 23 06:51:29 2013
From: andy.shevchenko at gmail.com (Andy Shevchenko)
Date: Thu, 23 May 2013 13:51:29 +0300
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <20130523100932.GA30200@intel.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <20130521151143.GH10453@mudshark.cambridge.arm.com>
 <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
 <20130523100932.GA30200@intel.com>
Message-ID: <CAHp75Vf58kq0t7+et9i54fxjEdQfBrTWxji4xk_MS-fZgWGOdQ@mail.gmail.com>

On Thu, May 23, 2013 at 1:09 PM, Vinod Koul <vinod.koul at intel.com> wrote:
> On Tue, May 21, 2013 at 08:24:15PM +0300, Andy Shevchenko wrote:
>> On Tue, May 21, 2013 at 6:11 PM, Will Deacon <will.deacon at arm.com> wrote:
>> > On Tue, May 21, 2013 at 01:33:17PM +0100, Andy Shevchenko wrote:
>> >> When thread is going to be stopped we have to unconditionally terminate all
>> >> ongoing transfers. Otherwise it would be possible that callback function will
>> >> be called on the next interrupt and will try to access to already freed
>> >> structures.
>> >>
>> >> The patch introduces specific error message for this, though it doesn't
>> >> increase the counter of the failed tests.
>> >>
>> > Thanks for persevering with this! Although this patch definitely fixes the
>> > panic I was seeing, I now observe buffer verification failures in subsequent
>> > test runs after an aborted run:
>>
>> I think the description to the commit adfa543e "dmatest: don't use
>> set_freezable_with_signal()" may shed light on this.
>>
>> The background (if  I got it correctly) is in race with done flag. So,
>> we got a callback call from the DMA engine, but we don't know which
>> transfer triggers it.
>> I might be wrong. This is just an assumption.
>>
>> Have you ever see such behaviour on pre v3.10-rc1 kernels? (I mean
>> with old dmatest module)
> Terminate shouldnt cause the issue with buffer verfication, can you try this on
> dw_dmac, do you see similar failures on verfication?

I saw the similar errors on dw_dmac on Intel Medfield device.
Anyway, I checked another approach with Will.
For now I will send a quick fix that prevents tester to abort an
ongoing transfer.
In future we could implement a robust logic when transfers can be
interrupted at any time.

-- 
With Best Regards,
Andy Shevchenko


From will.deacon at arm.com  Thu May 23 06:52:54 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 23 May 2013 11:52:54 +0100
Subject: [PATCH 3/3] ARM: cacheflush: add new iovec-based cache flushing
 system call
In-Reply-To: <20130327111210.GH801@MacBook-Pro.local>
References: <1364235486-17738-1-git-send-email-will.deacon@arm.com>
 <1364235486-17738-4-git-send-email-will.deacon@arm.com>
 <20130327111210.GH801@MacBook-Pro.local>
Message-ID: <20130523105254.GE31543@mudshark.cambridge.arm.com>

On Wed, Mar 27, 2013 at 11:12:11AM +0000, Catalin Marinas wrote:
> On Mon, Mar 25, 2013 at 06:18:06PM +0000, Will Deacon wrote:
> > +static inline int
> > +do_cache_op_iov(const struct iovec __user *uiov, unsigned long cnt, int flags)
> > +{
> > +	int i, ret = 0;
> > +	unsigned long len = cnt * sizeof(struct iovec);
> > +	struct iovec *iov = kmalloc(len, GFP_KERNEL);
> > +
> > +	if (iov == NULL) {
> > +		ret = -ENOMEM;
> > +		goto out;
> > +	}
> > +
> > +	if (copy_from_user(iov, uiov, len)) {
> > +		ret = -EFAULT;
> > +		goto out_free;
> > +	}
> > +
> > +	for (i = 0; i < cnt; ++i) {
> > +		unsigned long start = (unsigned long __force)iov[i].iov_base;
> > +		unsigned long end = start + iov[i].iov_len;
> > +		ret = do_cache_op(start, end, flags);
> > +		if (ret)
> > +			break;
> > +	}
> 
> Could you use get_user() on struct iovec fields directly to avoid
> kmalloc? It would be slightly faster.

I just had a look at this, but the problem is that we want to know the
entire (combined) region size so that we may just decide to flush the entire
cache, rather than iterate over each region line-by-line. This requires
copying the whole iovec into kernel space up front, so that we can iterate
over the regions with iov_length.

Will


From catalin.marinas at arm.com  Thu May 23 06:53:54 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 11:53:54 +0100
Subject: [PATCH v4 24/32] arm64: KVM: 32bit conditional execution emulation
In-Reply-To: <1368540840-26750-25-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-25-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523105354.GF16722@arm.com>

On Tue, May 14, 2013 at 03:13:52PM +0100, Marc Zyngier wrote:
> As conditional instructions can trap on AArch32, add the thinest
> possible emulation layer to keep 32bit guests happy.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From vinod.koul at intel.com  Thu May 23 06:22:48 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 23 May 2013 15:52:48 +0530
Subject: [PATCH] dmatest: abort transfers immediately when asked for
In-Reply-To: <CAHp75Vf58kq0t7+et9i54fxjEdQfBrTWxji4xk_MS-fZgWGOdQ@mail.gmail.com>
References: <20130516153553.GI11706@mudshark.cambridge.arm.com>
 <1369139597-24446-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <20130521151143.GH10453@mudshark.cambridge.arm.com>
 <CAHp75VdRn8baf0ak57HpoJKNues6vEsjBp1uOQ2Zpvwa+B5rjA@mail.gmail.com>
 <20130523100932.GA30200@intel.com>
 <CAHp75Vf58kq0t7+et9i54fxjEdQfBrTWxji4xk_MS-fZgWGOdQ@mail.gmail.com>
Message-ID: <20130523102248.GC30200@intel.com>

On Thu, May 23, 2013 at 01:51:29PM +0300, Andy Shevchenko wrote:
> On Thu, May 23, 2013 at 1:09 PM, Vinod Koul <vinod.koul at intel.com> wrote:
> > On Tue, May 21, 2013 at 08:24:15PM +0300, Andy Shevchenko wrote:
> >> On Tue, May 21, 2013 at 6:11 PM, Will Deacon <will.deacon at arm.com> wrote:
> >> > On Tue, May 21, 2013 at 01:33:17PM +0100, Andy Shevchenko wrote:
> >> >> When thread is going to be stopped we have to unconditionally terminate all
> >> >> ongoing transfers. Otherwise it would be possible that callback function will
> >> >> be called on the next interrupt and will try to access to already freed
> >> >> structures.
> >> >>
> >> >> The patch introduces specific error message for this, though it doesn't
> >> >> increase the counter of the failed tests.
> >> >>
> >> > Thanks for persevering with this! Although this patch definitely fixes the
> >> > panic I was seeing, I now observe buffer verification failures in subsequent
> >> > test runs after an aborted run:
> >>
> >> I think the description to the commit adfa543e "dmatest: don't use
> >> set_freezable_with_signal()" may shed light on this.
> >>
> >> The background (if  I got it correctly) is in race with done flag. So,
> >> we got a callback call from the DMA engine, but we don't know which
> >> transfer triggers it.
> >> I might be wrong. This is just an assumption.
> >>
> >> Have you ever see such behaviour on pre v3.10-rc1 kernels? (I mean
> >> with old dmatest module)
> > Terminate shouldnt cause the issue with buffer verfication, can you try this on
> > dw_dmac, do you see similar failures on verfication?
> 
> I saw the similar errors on dw_dmac on Intel Medfield device.
Ah, so may not be a driver issue.

> Anyway, I checked another approach with Will.
> For now I will send a quick fix that prevents tester to abort an
> ongoing transfer.
okay so taht should prevent regression, let me check on my setup if I find
anything

--
~Vinod
> In future we could implement a robust logic when transfers can be
> interrupted at any time.
> 
> -- 
> With Best Regards,
> Andy Shevchenko


From catalin.marinas at arm.com  Thu May 23 07:00:26 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:00:26 +0100
Subject: [PATCH v4 25/32] arm64: KVM: 32bit handling of coprocessor traps
In-Reply-To: <1368540840-26750-26-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-26-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523110025.GG16722@arm.com>

On Tue, May 14, 2013 at 03:13:53PM +0100, Marc Zyngier wrote:
> Provide the necessary infrastructure to trap coprocessor accesses that
> occur when running 32bit guests.
> 
> Also wire SMC and HVC trapped in 32bit mode while were at it.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Thu May 23 07:00:54 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:00:54 +0100
Subject: [PATCH v4 26/32] arm64: KVM: CPU specific 32bit coprocessor access
In-Reply-To: <1368540840-26750-27-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-27-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523110054.GH16722@arm.com>

On Tue, May 14, 2013 at 03:13:54PM +0100, Marc Zyngier wrote:
> Enable handling of CPU specific 32bit coprocessor access. Not much
> here either.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From arnd at arndb.de  Thu May 23 06:59:43 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 12:59:43 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <20130523100409.GK18614@n2100.arm.linux.org.uk>
References: <519DCBEF.3090208@asianux.com> <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
Message-ID: <201305231259.43750.arnd@arndb.de>

On Thursday 23 May 2013, Russell King - ARM Linux wrote:
> So, if you want to use this, then you should update the CONFIG_BUG text
> to include a warning to this effect:
> 
>      Warning: if CONFIG_BUG is turned off, and control flow reaches
>      a BUG(), the system behaviour will be undefined.
> 
> so that people can make an informed choice about this, because at the
> moment:
> 
>           Disabling this option eliminates support for BUG and WARN, reducing
>           the size of your kernel image and potentially quietly ignoring
>           numerous fatal conditions. You should only consider disabling this
>           option for embedded systems with no facilities for reporting errors.
>           Just say Y.
> 
> will become completely misleading.  Turning this option off will not
> result in "quietly ignoring numerous fatal conditions".

I must be missing something, to me the two descriptions mean the same thing.

> And I come back to one of my previous arguments - is it not better to
> panic() if we hit one of these conditions so that the system can try to
> do a panic-reboot rather than continue blindly into the unknown?

I think this all comes from the 'linux-tiny' project that tried to squeeze
out the last bits of kernel object code size at some point. The idea was
that if you have code like

	BUG_ON(something_unexpected_happened());

or

	switch (my_enum) {
	case FOO:
		return f1();
	case BAR:
		return f2();
	default:
		BUG();
	}

You don't just want to avoid the code for printing the bug message and
the invalid instruction, we also want the compiler to not emit the 
function call or check the enum for unexpected values. The meaning of
BUG() is really that person writing that statement was sure it cannot
happen unless there is a bug in the kernel, which has likely already
corrupted data. Printing a diagnostic at this point is nice if someone
is there to look at it, but letting the kernel do further actions that
may be undefined is not going to make things worse.

	Arnd


From catalin.marinas at arm.com  Thu May 23 07:02:06 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:02:06 +0100
Subject: [PATCH v4 27/32] arm64: KVM: 32bit specific register world switch
In-Reply-To: <1368540840-26750-28-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-28-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523110206.GI16722@arm.com>

On Tue, May 14, 2013 at 03:13:55PM +0100, Marc Zyngier wrote:
> Allow registers specific to 32bit guests to be saved/restored
> during the world switch.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Thu May 23 07:08:01 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:08:01 +0100
Subject: [PATCH v4 28/32] arm64: KVM: 32bit guest fault injection
In-Reply-To: <1368540840-26750-29-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-29-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523110800.GJ16722@arm.com>

On Tue, May 14, 2013 at 03:13:56PM +0100, Marc Zyngier wrote:
> Add fault injection capability for 32bit guests.
> 
> Reviewed-by: Christopher Covington <cov at codeaurora.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Thu May 23 07:08:37 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:08:37 +0100
Subject: [PATCH v4 29/32] arm64: KVM: enable initialization of a 32bit vcpu
In-Reply-To: <1368540840-26750-30-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-30-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523110837.GK16722@arm.com>

On Tue, May 14, 2013 at 03:13:57PM +0100, Marc Zyngier wrote:
> Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
> and providing sensible defaults out of reset state.
> 
> This feature is of course conditioned by the presence of 32bit
> capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
> capability.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From manjunath.goudar at linaro.org  Thu May 23 07:11:43 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 23 May 2013 16:41:43 +0530
Subject: [RFC V6 PATCH 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>

This series of patches begins the process of splitting ohci-hcd up into
a core library module and independent pci driver modules.

Patch 1/3 prepares the way by exporting a few functions from ohci-hcd
and adding a new mechanism for platform-specific drivers to initialize
their hc_driver structures.  This deserves to be done in the core
because almost all of the entries in these structures are pure
boilerplate -- practically none of the drivers need to override more
than three of the standard core values.

Patch 2/3 is part of separating the ohci pci host controller
driver from ohci-hcd host code.
Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file 
and EXPORTed, this is part of the effort to move the ohci pci related 
code to generic pci code.

Patch 3/3  separate out ohci-pci into independent driver modules.
 


Manjunath Goudar (3):
  USB: OHCI: prepare to make ohci-hcd a library module
  USB: OHCI: Generic changes to make ohci-pci a separate driver
  USB: OHCI: make ohci-pci a separate driver

 drivers/usb/host/Kconfig      |    4 +-
 drivers/usb/host/Makefile     |    3 +
 drivers/usb/host/ohci-hcd.c   |  129 +++++++++++++++++++++++++---------
 drivers/usb/host/ohci-hub.c   |    1 -
 drivers/usb/host/ohci-pci.c   |  152 ++++++++++++-----------------------------
 drivers/usb/host/ohci-q.c     |    8 ++-
 drivers/usb/host/ohci.h       |   21 ++++++
 drivers/usb/host/pci-quirks.c |   14 ++++
 drivers/usb/host/pci-quirks.h |    3 +
 9 files changed, 189 insertions(+), 146 deletions(-)

-- 
1.7.9.5



From manjunath.goudar at linaro.org  Thu May 23 07:11:44 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 23 May 2013 16:41:44 +0530
Subject: [RFC V6 PATCH 1/3] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369307506-4458-2-git-send-email-manjunath.goudar@linaro.org>

This patch prepares ohci-hcd for being split up into a core
library and separate platform driver modules.  A generic
ohci_hc_driver structure is created, containing all the "standard"
values, and a new mechanism is added whereby a driver module can
specify a set of overrides to those values.  In addition the
ohci_restart(),ohci_suspend() and ohci_resume() routines need
to be EXPORTed for use by the drivers.

Added ohci_setip(() and ohci_start() routine for to start the generic
controller rather than each having its own idiosyncratic approach.
This allow to clean duplicated code in most of SOC driver

In V2:
 -ohci_hcd_init() ohci_run() and ohci_stop() are not made non-static.
 -Adds the ohci_setup() and ohci_start() routine.

In V3:
 -purpose of ohci_setup() and ohci_start() function description written in the patch
  description.
 -ohci_init() are not made non-static but now called beginning of the ohci_restart().
 -ohci_run() signature change reverted back.
 -unrelated changes removed.
 -duplicate comment line removed.
 -inline ohci_suspend() and ohci_resume() is not needed so removed from ohci.h file.

In V4:
 -ohci-init() EXPORTed because it is called by all bus glue modules.
 -ohci-setup() removed from 1/2 added into 2/2 patch.

In V5:
 -Again ohci_setup() is added and EXPORTed because to replace the ohci_init() from
  all bus glues.
 -ohci_init() is not made non-static function.

In V6:
  -ohci_init() call is removed from ohci_quirk_nec_worker(), because it is already called in ohci_restart().

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci-hcd.c |  103 +++++++++++++++++++++++++++++++++++++++----
 drivers/usb/host/ohci-hub.c |    1 -
 drivers/usb/host/ohci-pci.c |    7 ---
 drivers/usb/host/ohci.h     |   17 +++++++
 4 files changed, 111 insertions(+), 17 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9e6de95..13ebbb7 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -79,13 +79,7 @@ static const char	hcd_name [] = "ohci_hcd";
 #include "pci-quirks.h"
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
-static int ohci_init (struct ohci_hcd *ohci);
 static void ohci_stop (struct usb_hcd *hcd);
-
-#if defined(CONFIG_PM) || defined(CONFIG_PCI)
-static int ohci_restart (struct ohci_hcd *ohci);
-#endif
-
 #ifdef CONFIG_PCI
 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
 #else
@@ -768,6 +762,30 @@ retry:
 	return 0;
 }
 
+/* ohci_setup routine for generic controller initialization */
+
+int ohci_setup(struct usb_hcd *hcd)
+{
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
+
+	return ohci_init(ohci);
+}
+EXPORT_SYMBOL_GPL(ohci_setup);
+
+/* ohci_start routine for generic controller start of all OHCI bus glue */
+static int ohci_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
+	int	ret;
+
+	ret = ohci_run(ohci);
+	if (ret < 0) {
+		ohci_err(ohci, "can't start\n");
+		ohci_stop(hcd);
+	}
+	return ret;
+}
+
 /*-------------------------------------------------------------------------*/
 
 /* an interrupt happens */
@@ -949,12 +967,13 @@ static void ohci_stop (struct usb_hcd *hcd)
 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 
 /* must not be called from interrupt context */
-static int ohci_restart (struct ohci_hcd *ohci)
+int ohci_restart(struct ohci_hcd *ohci)
 {
 	int temp;
 	int i;
 	struct urb_priv *priv;
 
+	ohci_init(ohci);
 	spin_lock_irq(&ohci->lock);
 	ohci->rh_state = OHCI_RH_HALTED;
 
@@ -1008,12 +1027,13 @@ static int ohci_restart (struct ohci_hcd *ohci)
 	ohci_dbg(ohci, "restart complete\n");
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_restart);
 
 #endif
 
 #ifdef CONFIG_PM
 
-static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
 	unsigned long	flags;
@@ -1031,9 +1051,10 @@ static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_suspend);
 
 
-static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
+int ohci_resume(struct usb_hcd *hcd, bool hibernated)
 {
 	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	int			port;
@@ -1081,8 +1102,72 @@ static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_resume);
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Generic structure: This gets copied for platform drivers so that
+ * individual entries can be overridden as needed.
+ */
 
+static const struct hc_driver ohci_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "OHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	*/
+	.irq =                  ohci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/*
+	* basic lifecycle operations
+	*/
+	.reset =                ohci_setup,
+	.start =                ohci_start,
+	.stop =                 ohci_stop,
+	.shutdown =             ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	*/
+	.urb_enqueue =          ohci_urb_enqueue,
+	.urb_dequeue =          ohci_urb_dequeue,
+	.endpoint_disable =     ohci_endpoint_disable,
+
+	/*
+	* scheduling support
+	*/
+	.get_frame_number =     ohci_get_frame,
+
+	/*
+	* root hub support
+	*/
+	.hub_status_data =      ohci_hub_status_data,
+	.hub_control =          ohci_hub_control,
+#ifdef CONFIG_PM
+	.bus_suspend =          ohci_bus_suspend,
+	.bus_resume =           ohci_bus_resume,
 #endif
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+void ohci_init_driver(struct hc_driver *drv,
+		const struct ohci_driver_overrides *over)
+{
+	/* Copy the generic table to drv and then apply the overrides */
+	*drv = ohci_hc_driver;
+
+	drv->product_desc = over->product_desc;
+	drv->hcd_priv_size += over->extra_priv_size;
+	if (over->reset)
+		drv->reset = over->reset;
+}
+EXPORT_SYMBOL_GPL(ohci_init_driver);
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index 60ff422..2347ab8 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -176,7 +176,6 @@ __acquires(ohci->lock)
 	if (status == -EBUSY) {
 		if (!autostopped) {
 			spin_unlock_irq (&ohci->lock);
-			(void) ohci_init (ohci);
 			status = ohci_restart (ohci);
 
 			usb_root_hub_lost_power(hcd->self.root_hub);
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 951514e..2c27a5f 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -123,13 +123,6 @@ static void ohci_quirk_nec_worker(struct work_struct *work)
 	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
 	int status;
 
-	status = ohci_init(ohci);
-	if (status != 0) {
-		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
-			 "ohci_init", status);
-		return;
-	}
-
 	status = ohci_restart(ohci);
 	if (status != 0)
 		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index d329914..3b58482 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -718,3 +718,20 @@ static inline u32 roothub_status (struct ohci_hcd *hc)
 	{ return ohci_readl (hc, &hc->regs->roothub.status); }
 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+/* Declarations of things exported for use by ohci platform drivers */
+
+struct ohci_driver_overrides {
+	const char	*product_desc;
+	size_t		extra_priv_size;
+	int		(*reset)(struct usb_hcd *hcd);
+};
+
+extern void	ohci_init_driver(struct hc_driver *drv,
+				const struct ohci_driver_overrides *over);
+extern int	ohci_restart(struct ohci_hcd *ohci);
+extern int	ohci_setup(struct usb_hcd *hcd);
+#ifdef CONFIG_PM
+extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
+extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
+#endif
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Thu May 23 07:11:45 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 23 May 2013 16:41:45 +0530
Subject: [RFC PATCH 2/3] USB: OHCI: Generic changes to make ohci-pci a
 separate driver
In-Reply-To: <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369307506-4458-3-git-send-email-manjunath.goudar@linaro.org>

Note that this changes is part of separating the ohci pci host controller
driver from ohci-hcd host code.
This contains :
 -Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
  and EXPORTed, this is part of the effort to move the ohci pci related
  code to generic pci code.
 -Passed "pci_dev" argument instead  of "ohci_hcd" in sb800_prefetch()
  function to avoid extra include file in pci-quirks.c.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci-hcd.c   |   11 +----------
 drivers/usb/host/ohci-pci.c   |   13 -------------
 drivers/usb/host/ohci-q.c     |    6 ++++--
 drivers/usb/host/pci-quirks.c |   12 ++++++++++++
 drivers/usb/host/pci-quirks.h |    2 ++
 5 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 13ebbb7..2490b81 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -80,15 +80,6 @@ static const char	hcd_name [] = "ohci_hcd";
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
 static void ohci_stop (struct usb_hcd *hcd);
-#ifdef CONFIG_PCI
-static void sb800_prefetch(struct ohci_hcd *ohci, int on);
-#else
-static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	return;
-}
-#endif
-
 
 #include "ohci-hub.c"
 #include "ohci-dbg.c"
@@ -1275,7 +1266,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_platform_driver
 #endif
 
-#if	!defined(PCI_DRIVER) &&		\
+#if	!defined(PCI_DRIVER) && \
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 2c27a5f..c3fa936 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -168,19 +168,6 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
 	return 0;
 }
 
-static void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	struct pci_dev *pdev;
-	u16 misc;
-
-	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
-	pci_read_config_word(pdev, 0x50, &misc);
-	if (on == 0)
-		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
-	else
-		pci_write_config_word(pdev, 0x50, misc | 0x0300);
-}
-
 /* List of quirks for OHCI */
 static const struct pci_device_id ohci_pci_quirks[] = {
 	{
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 88731b7..78e0095 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -41,6 +41,7 @@ finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
 __releases(ohci->lock)
 __acquires(ohci->lock)
 {
+	struct pci_dev *pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
 	// ASSERT (urb->hcpriv != 0);
 
 	urb_free_priv (ohci, urb->hcpriv);
@@ -55,7 +56,7 @@ __acquires(ohci->lock)
 			if (quirk_amdiso(ohci))
 				usb_amd_quirk_pll_enable();
 			if (quirk_amdprefetch(ohci))
-				sb800_prefetch(ohci, 0);
+				sb800_prefetch(pdev, 0);
 		}
 		break;
 	case PIPE_INTERRUPT:
@@ -580,6 +581,7 @@ static void td_submit_urb (
 	struct urb	*urb
 ) {
 	struct urb_priv	*urb_priv = urb->hcpriv;
+	struct pci_dev *pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
 	dma_addr_t	data;
 	int		data_len = urb->transfer_buffer_length;
 	int		cnt = 0;
@@ -689,7 +691,7 @@ static void td_submit_urb (
 			if (quirk_amdiso(ohci))
 				usb_amd_quirk_pll_disable();
 			if (quirk_amdprefetch(ohci))
-				sb800_prefetch(ohci, 1);
+				sb800_prefetch(pdev, 1);
 		}
 		periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 			&& ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 4c338ec..5f01540 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -91,6 +91,18 @@ static struct amd_chipset_info {
 
 static DEFINE_SPINLOCK(amd_lock);
 
+void sb800_prefetch(struct pci_dev *pdev, int on)
+{
+	u16 misc;
+
+	pci_read_config_word(pdev, 0x50, &misc);
+	if (on == 0)
+		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
+	else
+		pci_write_config_word(pdev, 0x50, misc | 0x0300);
+}
+EXPORT_SYMBOL_GPL(sb800_prefetch);
+
 int usb_amd_find_chipset_info(void)
 {
 	u8 rev = 0;
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h
index 7f69a39..7c5fbc1 100644
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -11,11 +11,13 @@ void usb_amd_quirk_pll_enable(void);
 bool usb_is_intel_switchable_xhci(struct pci_dev *pdev);
 void usb_enable_xhci_ports(struct pci_dev *xhci_pdev);
 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
+void sb800_prefetch(struct pci_dev *pdev, int on);
 #else
 static inline void usb_amd_quirk_pll_disable(void) {}
 static inline void usb_amd_quirk_pll_enable(void) {}
 static inline void usb_amd_dev_put(void) {}
 static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {}
+static inline void sb800_prefetch(struct pci_dev *pdev, int on) {}
 #endif  /* CONFIG_PCI */
 
 #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Thu May 23 07:11:46 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 23 May 2013 16:41:46 +0530
Subject: [RFC V6 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369307506-4458-4-git-send-email-manjunath.goudar@linaro.org>

This patch splits the PCI portion of ohci-hcd out into its
own separate driver module, called ohci-pci.

The major point of difficulty lies in ohci-pci's many vendor- and
device-specific workarounds.  Some of them have to be applied before
calling ohci_start() some after, which necessitates a fair amount of
code motion.  The other platform drivers require much smaller changes.

The complete sb800_prefetch() function moved to ohci-q.c,because its
only related to ohci-pci driver.

V2:
  - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
    and rest of the generic code is written in ohci_start of ohci-hcd.c file.
V3:
 - ohci_restart() has been called in ohci_pci_reset() function for to reset the ohci pci.

V4:
 -sb800_prefetch() moved to ohci-q.c,because its only related to ohci-pci.
 -no longer _creating_ CONFIG_USB_OHCI_PCI,creating CONFIG_USB_OHCI_HCD_PCI.
 -overrides renamed with pci_override,its giving proper meaning.

V5:
 -sb800_prefetch() moved to pci-quirks.c,because its only related to pci.

V6:
 -sb800_prefetch() function has been moved to pci-quirks.c made as separate patch in 2/3.
 -Most of the generic ohci pci changes moved in 2/3 patch,now this is complete  ohci-pci separation patch.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig      |    4 +-
 drivers/usb/host/Makefile     |    3 +
 drivers/usb/host/ohci-hcd.c   |   15 -----
 drivers/usb/host/ohci-pci.c   |  132 ++++++++++++++---------------------------
 drivers/usb/host/ohci-q.c     |    2 +
 drivers/usb/host/ohci.h       |    4 ++
 drivers/usb/host/pci-quirks.c |    2 +
 drivers/usb/host/pci-quirks.h |    1 +
 8 files changed, 59 insertions(+), 104 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 64d7209..7e75387 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -377,7 +377,7 @@ config USB_FUSBH200_HCD
 	module will be called fusbh200-hcd.
 
 config USB_OHCI_HCD
-	tristate "OHCI HCD support"
+	tristate "OHCI HCD (USB 1.1) support"
 	depends on USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	depends on USB_ISP1301 || !ARCH_LPC32XX
@@ -446,7 +446,7 @@ config USB_OHCI_HCD_PPC_OF
 	default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE
 
 config USB_OHCI_HCD_PCI
-	bool "OHCI support for PCI-bus USB controllers"
+	tristate "OHCI support for PCI-bus USB controllers"
 	depends on PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
 	default y
 	select USB_OHCI_LITTLE_ENDIAN
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 661c558..2214ded 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -42,7 +42,10 @@ obj-$(CONFIG_USB_EHCI_TEGRA)    +=ehci-tegra.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
+
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+obj-$(CONFIG_USB_OHCI_HCD_PCI)	+= ohci-pci.o
+
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 2490b81..36fc3f7 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1166,11 +1166,6 @@ MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
 
-#ifdef CONFIG_PCI
-#include "ohci-pci.c"
-#define PCI_DRIVER		ohci_pci_driver
-#endif
-
 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
 #include "ohci-sa1111.c"
 #define SA1111_DRIVER		ohci_hcd_sa1111_driver
@@ -1341,12 +1336,6 @@ static int __init ohci_hcd_mod_init(void)
 		goto error_sa1111;
 #endif
 
-#ifdef PCI_DRIVER
-	retval = pci_register_driver(&PCI_DRIVER);
-	if (retval < 0)
-		goto error_pci;
-#endif
-
 #ifdef SM501_OHCI_DRIVER
 	retval = platform_driver_register(&SM501_OHCI_DRIVER);
 	if (retval < 0)
@@ -1440,10 +1429,6 @@ static int __init ohci_hcd_mod_init(void)
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
  error_sm501:
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
- error_pci:
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
  error_sa1111:
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index c3fa936..ea088c1 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -14,12 +14,19 @@
  * This file is licenced under the GPL.
  */
 
-#ifndef CONFIG_PCI
-#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
-#endif
-
-#include <linux/pci.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+#include "pci-quirks.h"
+
+#define DRIVER_DESC "OHCI PCI platform driver"
+
+static const char hcd_name[] = "ohci-pci";
 
 
 /*-------------------------------------------------------------------------*/
@@ -229,10 +236,10 @@ static const struct pci_device_id ohci_pci_quirks[] = {
 static int ohci_pci_reset (struct usb_hcd *hcd)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
+	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 	int ret = 0;
 
 	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 		const struct pci_device_id *quirk_id;
 
 		quirk_id = pci_match_id(ohci_pci_quirks, pdev);
@@ -242,94 +249,24 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
 			ret = quirk(hcd);
 		}
 	}
-	if (ret == 0) {
-		ohci_hcd_init (ohci);
-		return ohci_init (ohci);
-	}
-	return ret;
-}
-
-
-static int ohci_pci_start (struct usb_hcd *hcd)
-{
-	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
-	int		ret;
-
-#ifdef CONFIG_PM /* avoid warnings about unused pdev */
-	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
-
-		/* RWC may not be set for add-in PCI cards, since boot
-		 * firmware probably ignored them.  This transfers PCI
-		 * PM wakeup capabilities.
-		 */
-		if (device_can_wakeup(&pdev->dev))
-			ohci->hc_control |= OHCI_CTRL_RWC;
-	}
-#endif /* CONFIG_PM */
-
-	ret = ohci_run (ohci);
-	if (ret < 0) {
-		ohci_err (ohci, "can't start\n");
-		ohci_stop (hcd);
-	}
+	if (ret == 0)
+		ohci_setup(hcd);
+	/*
+	* After ohci setup RWC may not be set for add-in PCI cards.
+	* This transfers PCI PM wakeup capabilities.
+	*/
+	if (device_can_wakeup(&pdev->dev))
+		ohci->hc_control |= OHCI_CTRL_RWC;
 	return ret;
 }
 
+static struct hc_driver __read_mostly ohci_pci_hc_driver;
 
-/*-------------------------------------------------------------------------*/
-
-static const struct hc_driver ohci_pci_hc_driver = {
-	.description =		hcd_name,
-	.product_desc =		"OHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			ohci_irq,
-	.flags =		HCD_MEMORY | HCD_USB11,
-
-	/*
-	 * basic lifecycle operations
-	 */
+static const struct ohci_driver_overrides pci_overrides __initconst = {
+	.product_desc =		"OHCI PCI host controller",
 	.reset =		ohci_pci_reset,
-	.start =		ohci_pci_start,
-	.stop =			ohci_stop,
-	.shutdown =		ohci_shutdown,
-
-#ifdef	CONFIG_PM
-	.pci_suspend =		ohci_suspend,
-	.pci_resume =		ohci_resume,
-#endif
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		ohci_urb_enqueue,
-	.urb_dequeue =		ohci_urb_dequeue,
-	.endpoint_disable =	ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data =	ohci_hub_status_data,
-	.hub_control =		ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend =		ohci_bus_suspend,
-	.bus_resume =		ohci_bus_resume,
-#endif
-	.start_port_reset =	ohci_start_port_reset,
 };
 
-/*-------------------------------------------------------------------------*/
-
-
 static const struct pci_device_id pci_ids [] = { {
 	/* handle any USB OHCI controller */
 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
@@ -357,3 +294,24 @@ static struct pci_driver ohci_pci_driver = {
 	},
 #endif
 };
+
+static int __init ohci_pci_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_pci_hc_driver, &pci_overrides);
+	return pci_register_driver(&ohci_pci_driver);
+}
+module_init(ohci_pci_init);
+
+static void __exit ohci_pci_cleanup(void)
+{
+	pci_unregister_driver(&ohci_pci_driver);
+}
+module_exit(ohci_pci_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 78e0095..0ed8187 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -9,6 +9,8 @@
 
 #include <linux/irq.h>
 #include <linux/slab.h>
+#include "ohci.h"
+#include "pci-quirks.h"
 
 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
 {
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index 3b58482..ecc471a 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -12,6 +12,9 @@
  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  * host controller implementation.
  */
+#ifndef __USB_HOST_OHCI_H
+#define __USB_HOST_OHCI_H
+
 typedef __u32 __bitwise __hc32;
 typedef __u16 __bitwise __hc16;
 
@@ -735,3 +738,4 @@ extern int	ohci_setup(struct usb_hcd *hcd);
 extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
 #endif
+#endif
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 5f01540..112c85f 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -17,6 +17,8 @@
 #include <linux/export.h>
 #include <linux/acpi.h>
 #include <linux/dmi.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
 #include "pci-quirks.h"
 #include "xhci-ext-caps.h"
 
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h
index 7c5fbc1..ba4d76b 100644
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -1,6 +1,7 @@
 #ifndef __LINUX_USB_PCI_QUIRKS_H
 #define __LINUX_USB_PCI_QUIRKS_H
 
+struct ohci_hcd;
 #ifdef CONFIG_PCI
 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
-- 
1.7.9.5



From catalin.marinas at arm.com  Thu May 23 07:12:37 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:12:37 +0100
Subject: [PATCH v4 32/32] arm64: KVM: document kernel object mappings
 in HYP
In-Reply-To: <1368540840-26750-33-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-33-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523111237.GM16722@arm.com>

On Tue, May 14, 2013 at 03:14:00PM +0100, Marc Zyngier wrote:
> HYP mode has access to some of the kernel pages. Document the
> memory mapping and the offset between kernel VA and HYP VA.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From gang.chen at asianux.com  Thu May 23 07:19:30 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Thu, 23 May 2013 19:19:30 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <201305231259.43750.arnd@arndb.de>
References: <519DCBEF.3090208@asianux.com> <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
 <201305231259.43750.arnd@arndb.de>
Message-ID: <519DFB42.7010509@asianux.com>

On 05/23/2013 06:59 PM, Arnd Bergmann wrote:
> You don't just want to avoid the code for printing the bug message and
> the invalid instruction, we also want the compiler to not emit the 
> function call or check the enum for unexpected values. The meaning of
> BUG() is really that person writing that statement was sure it cannot
> happen unless there is a bug in the kernel, which has likely already
> corrupted data. Printing a diagnostic at this point is nice if someone
> is there to look at it, but letting the kernel do further actions that
> may be undefined is not going to make things worse.

So I think neither unreachable() nor panic() are suitable for this
condition.

I guess 'CONFIG_BUG' is not belong to common features, now (and in the
future), so it is not suitable still exist in "asm-generic/bug.h", need
remove it firstly.

And then let the specific architectures to implement their own BUG(), if
they want some special features.

SO most of arches can skip this issue.


Thanks.
-- 
Chen Gang

Asianux Corporation


From thomas.petazzoni at free-electrons.com  Thu May 23 07:22:55 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 13:22:55 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523102601.GI9937@game.jcrosoft.org>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com> <20130523120920.1df8e23a@skate>
 <20130523100951.GH9937@game.jcrosoft.org>
 <20130523122000.22a9a4d0@skate>
 <20130523102601.GI9937@game.jcrosoft.org>
Message-ID: <20130523132255.3acf4431@skate>

Dear Jean-Christophe PLAGNIOL-VILLARD,

On Thu, 23 May 2013 12:26:01 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:

> > Did you read what I write? In arch/arm/mach-at91/pm.c, the only
> > accesses made to the AIC registers are for pr_debug() calls, i.e only
> > to print some debugging messages. I believe those ones can simply be
> > removed to decouple the pm.c code from the irq.c code.
> 
> yes I read and yes I do not want to move code before we do cleanup MANDATORY

Then please explain to our volunteer contributor what sort of cleanup
is required. Simply NACKing without offering any insight as to how
things should be done is completely useless, counter-productive, and a
complete abuse of a maintainer's power over contributors.

> >  * PATCH 1: remove usage of AIC registers for debug messages in pm.c
> NACK I do want this debug, very usefull to debug pm

For the cases where you need to debug this stuff, you can always re-add
some instrumentation in this code to dump whatever you want.

Or, alternatively, we can make the irqchip driver show using
pr_debug() the value of IMR in its ->suspend() hook, the value of IMR &
IPR in its ->resume() hook, and the pm.c code can show the PMC_PCSR on
suspend. This way, you have all the informations you need for debugging.

Having the PM driver and the irqchip driver step on each other register
areas is anyway a bad idea, especially when the only reason to do so is
for two debugging messages that can be implemented differently.

Notice that this solution can always be improved later on if needed,
with further cleanups from you.

But please stop rejecting valid patches from contributors, just because
the code is not coming from you. What Boris is proposing is perfectly
fine, just needs a little bit more work to sort out the header
problems as we discussed, and is a good step in the right direction. And
this step in the right direction doesn't prevent anyone else, including
you, to provide additional patches to move even further in the right
direction.

It would be good if the other AT91 maintainers could raise their voice
here, so that Boris knows whether it is worthwhile doing additional
revisions of this patch set.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From vinod.koul at intel.com  Thu May 23 06:46:58 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 23 May 2013 16:16:58 +0530
Subject: [PATCH 10/63] dmaengine: ste_dma40: Amalgamate DMA source and
 destination channel numbers
In-Reply-To: <CACRpkdai7y+LBiFyK+b-CvW6p7n+TbC1iX0+XiLyg2V_8rFL+A@mail.gmail.com>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-11-git-send-email-lee.jones@linaro.org>
 <CACRpkdai7y+LBiFyK+b-CvW6p7n+TbC1iX0+XiLyg2V_8rFL+A@mail.gmail.com>
Message-ID: <20130523104658.GF30200@intel.com>

On Mon, May 20, 2013 at 02:35:01PM +0200, Linus Walleij wrote:
> On Fri, May 3, 2013 at 4:31 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > Devices which utilise DMA use the same device numbers for transmitting
> > and receiving. In this patch we encode the source and destination
> > information into one single attribute. We can subsequently exploit the
> > direction attribute to see which of the transfer directions are being
> > described. This also lessens the burden on platform data.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Still waiting for an ACK from Vinod on this as well.
Here you go...

Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
> 
> Vinod?
> 
> Yours,
> Linus Walleij


From jason at lakedaemon.net  Thu May 23 07:23:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 07:23:35 -0400
Subject: [PATCH V3 00/10] mmc_of_parse() adaptations, DT support for
 Sheevaplugs
In-Reply-To: <20130522192501.GC25367@schnuecks.de>
References: <1369090911-1479-1-git-send-email-gmbnomis@gmail.com>
 <20130521131455.GP31290@titan.lakedaemon.net>
 <20130522192501.GC25367@schnuecks.de>
Message-ID: <20130523112335.GN31290@titan.lakedaemon.net>

On Wed, May 22, 2013 at 09:25:02PM +0200, Simon Baatz wrote:
> Hi Jason,
> 
> On Tue, May 21, 2013 at 09:14:55AM -0400, Jason Cooper wrote:
> > On Tue, May 21, 2013 at 01:01:41AM +0200, Simon Baatz wrote:
> > > Hi,
> > > 
> > > 	V3 changes:
> > > 	- Patch 01/10: Added EPROBE_DEFER case to mmc_of_parse() 
> > > 	- Added Acked-By to (unmodified) patches 02 and 03.
> > > 
> > > 	V2 changes:
> > > 	- Converted mvsdio to use mmc_of_parse()
> > > 	- Adapted DTS files using mvsdio accordingly
> > > 	- Changed mmc_of_parse() to return errors to the caller
> > > 
> > > While adding DT support for the Sheevaplugs by Globalscale Technologies
> > > (Kirkwood), it turned out that the DT binding of mvsdio lacked features to
> > > properly support the hardware (active high/low of CD and WP pins could not
> > > be described in DT).
> > > 
> > > This is standard functionality provided by the mmc_of_parse() helper
> > > function.  However, mmc_of_parse() may allocate GPIO lines.  If the
> > > allocation fails, it outputs an error, but does not return an error to its
> > > caller.  Therefore, a proposal to handle errors in mmc_of_parse() is made.
> > > 
> > > The patch set is structured as follows:
> > > 
> > > 1   Adapt mmc_of_parse() to return errors
> > > 2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
> > >     only)
> > > 7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
> > >     kirkwood)
> > > 9   Add dts files for (eSATA) Sheevaplug
> > > 10  Add DT support for (eSATA) Sheevaplug
> > 
> > Patches 7, 9, and 10 already pulled into mvebu/dt.  You can drop those
> > from this series if you need to do another revision.
> 
> If you don't mind too much, as this crosses two trees, I would prefer
> to keep the series "self-contained" if people want to test.

That's fine, you can host the series in a single branch for folks to
pull and test.  From our side, 7, 9 and 10 need to go through arm-soc,
and the rest need to go through -mmc.  There is _no_ build or merge
dependency between the two.

> Additionally, I have two Acked-bys for 9 and 10 from Andrew that are
> not part of the patches yet.

Yes, I saw those after I sent the PR.  I sent that a little too fast.
I'm developing a new system and still working out the kinks.  Sorry
about that.

> > > I could only test on an eSATA Sheevaplug. I found patches with
> > > different LEDs for the Sheevaplug.  Thus, I would highly appreciate if
> > > someone with the hardware could give this a spin on a non-eSATA
> > > version.  
> > 
> > I happen to have one.  Unfortunately, it is currently my primary email
> > server, dhcp, dns, file server, and a few other irreplaceable things. :(
> > I *really* need to upgrade/reconfigure ...

FYI:

$ uname -r
2.6.30.2

Yikes.  I'm so embarrassed.  :(  However,

$ uptime
 07:16:42 up 251 days, 0 min,...

before that was over 400 days, then I had an ups failure.

> Even without reinstalling, can you please have a look if your
> "plug:green:health" LED is really green (mine is blue)?  And if your
> kernel already has a "plug:red:misc" LED could you verify whether it
> is really there?  Do you happen to know which board revision you
> have?

I have one directory under /sys/class/leds, plug:green:health.  It
controls a *blue* led.  There is also a green led, not enumerated.  I'm
sure the results would be better with a more recent kernel...

thx,

Jason.


From vinod.koul at intel.com  Thu May 23 06:48:29 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 23 May 2013 16:18:29 +0530
Subject: [PATCH 23/63] dmaengine: ste_dma40: Also report the number of
 logical channels
In-Reply-To: <1367591569-32197-24-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-24-git-send-email-lee.jones@linaro.org>
Message-ID: <20130523104829.GG30200@intel.com>

On Fri, May 03, 2013 at 03:32:09PM +0100, Lee Jones wrote:
> Now we know the total of physical and logical channels, we may as
> well report them within the information log.
> 
> Before:
> dma40 dma40.0: hardware revision: 3 @ 0x801c0000 with 8 physical channels
> 
> After:
> <as above ...> and 256 logical channels
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
>  drivers/dma/ste_dma40.c |    5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index e5f0e3c..6d81f44 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -3213,8 +3213,9 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
>  
>  	num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
>  
> -	dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
> -		 rev, res->start, num_phy_chans);
> +	dev_info(&pdev->dev,
> +		 "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n",
> +		 rev, res->start, num_phy_chans, num_log_chans);
>  
>  	base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
>  		       (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
> -- 
> 1.7.10.4
> 


From linux at arm.linux.org.uk  Thu May 23 07:24:01 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 12:24:01 +0100
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since
 always need it.
In-Reply-To: <201305231259.43750.arnd@arndb.de>
References: <519DCBEF.3090208@asianux.com> <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
 <201305231259.43750.arnd@arndb.de>
Message-ID: <20130523112401.GO18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 12:59:43PM +0200, Arnd Bergmann wrote:
> On Thursday 23 May 2013, Russell King - ARM Linux wrote:
> > So, if you want to use this, then you should update the CONFIG_BUG text
> > to include a warning to this effect:
> > 
> >      Warning: if CONFIG_BUG is turned off, and control flow reaches
> >      a BUG(), the system behaviour will be undefined.
> > 
> > so that people can make an informed choice about this, because at the
> > moment:
> > 
> >           Disabling this option eliminates support for BUG and WARN, reducing
> >           the size of your kernel image and potentially quietly ignoring
> >           numerous fatal conditions. You should only consider disabling this
> >           option for embedded systems with no facilities for reporting errors.
> >           Just say Y.
> > 
> > will become completely misleading.  Turning this option off will not
> > result in "quietly ignoring numerous fatal conditions".
> 
> I must be missing something, to me the two descriptions mean the same thing.

To me, the current text suggests that we still detect the fatal condition
but the code continues to execute in a manner controlled by the program.

The latter is uncontrolled code (or data) execution in ways unspecified
by the program.

> You don't just want to avoid the code for printing the bug message and
> the invalid instruction, we also want the compiler to not emit the 
> function call or check the enum for unexpected values. The meaning of
> BUG() is really that person writing that statement was sure it cannot
> happen unless there is a bug in the kernel, which has likely already
> corrupted data. Printing a diagnostic at this point is nice if someone
> is there to look at it, but letting the kernel do further actions that
> may be undefined is not going to make things worse.

I'm not talking about printing a diagnostic.  I'm talking about the CPU
remaining under the control of the program it is running - that being
the Linux kernel.

With CONFIG_BUG unset, turning on things like reboot-on-panic and such
like is worthless.  Arguably even is having a hardware watchdog - because
even if you hit one of these BUG() conditions where the CPU goes off and
does its own thing, it might be sufficient that the system is still able
to take care of the watchdog.

This is the problem you guys are missing - unreachable() means "we lose
control of the CPU at this point".

If you have an embedded system and you've taken out all the printk()
stuff, you most certainly want the system to do _something_ if you hit
an unexpected condition.


From andriy.shevchenko at linux.intel.com  Thu May 23 07:29:53 2013
From: andriy.shevchenko at linux.intel.com (Andy Shevchenko)
Date: Thu, 23 May 2013 14:29:53 +0300
Subject: [PATCH] dmatest: do not allow to interrupt ongoing tests
Message-ID: <1369308593-3723-1-git-send-email-andriy.shevchenko@linux.intel.com>

When user interrupts ongoing transfers the dmatest may end up with console
lockup, oops, or data mismatch. This patch prevents user to abort any ongoing
test.

Documentation is updated accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Reported-by: Will Deacon <will.deacon at arm.com>
Tested-by: Will Deacon <will.deacon at arm.com>
---
 Documentation/dmatest.txt |  6 +++---
 drivers/dma/dmatest.c     | 45 +++++++++++++++++++++++----------------------
 2 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/Documentation/dmatest.txt b/Documentation/dmatest.txt
index 279ac0a..132a094 100644
--- a/Documentation/dmatest.txt
+++ b/Documentation/dmatest.txt
@@ -34,7 +34,7 @@ command:
 After a while you will start to get messages about current status or error like
 in the original code.
 
-Note that running a new test will stop any in progress test.
+Note that running a new test will not stop any in progress test.
 
 The following command should return actual state of the test.
 	% cat /sys/kernel/debug/dmatest/run
@@ -52,8 +52,8 @@ To wait for test done the user may perform a busy loop that checks the state.
 
 The module parameters that is supplied to the kernel command line will be used
 for the first performed test. After user gets a control, the test could be
-interrupted or re-run with same or different parameters. For the details see
-the above section "Part 2 - When dmatest is built as a module..."
+re-run with the same or different parameters. For the details see the above
+section "Part 2 - When dmatest is built as a module..."
 
 In both cases the module parameters are used as initial values for the test case.
 You always could check them at run-time by running
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index d8ce4ec..e88ded2 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -716,8 +716,7 @@ static int dmatest_func(void *data)
 		}
 		dma_async_issue_pending(chan);
 
-		wait_event_freezable_timeout(done_wait,
-					     done.done || kthread_should_stop(),
+		wait_event_freezable_timeout(done_wait, done.done,
 					     msecs_to_jiffies(params->timeout));
 
 		status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
@@ -997,7 +996,6 @@ static void stop_threaded_test(struct dmatest_info *info)
 static int __restart_threaded_test(struct dmatest_info *info, bool run)
 {
 	struct dmatest_params *params = &info->params;
-	int ret;
 
 	/* Stop any running test first */
 	__stop_threaded_test(info);
@@ -1012,13 +1010,23 @@ static int __restart_threaded_test(struct dmatest_info *info, bool run)
 	memcpy(params, &info->dbgfs_params, sizeof(*params));
 
 	/* Run test with new parameters */
-	ret = __run_threaded_test(info);
-	if (ret) {
-		__stop_threaded_test(info);
-		pr_err("dmatest: Can't run test\n");
+	return __run_threaded_test(info);
+}
+
+static bool __is_threaded_test_run(struct dmatest_info *info)
+{
+	struct dmatest_chan *dtc;
+
+	list_for_each_entry(dtc, &info->channels, node) {
+		struct dmatest_thread *thread;
+
+		list_for_each_entry(thread, &dtc->threads, node) {
+			if (!thread->done)
+				return true;
+		}
 	}
 
-	return ret;
+	return false;
 }
 
 static ssize_t dtf_write_string(void *to, size_t available, loff_t *ppos,
@@ -1091,22 +1099,10 @@ static ssize_t dtf_read_run(struct file *file, char __user *user_buf,
 {
 	struct dmatest_info *info = file->private_data;
 	char buf[3];
-	struct dmatest_chan *dtc;
-	bool alive = false;
 
 	mutex_lock(&info->lock);
-	list_for_each_entry(dtc, &info->channels, node) {
-		struct dmatest_thread *thread;
-
-		list_for_each_entry(thread, &dtc->threads, node) {
-			if (!thread->done) {
-				alive = true;
-				break;
-			}
-		}
-	}
 
-	if (alive) {
+	if (__is_threaded_test_run(info)) {
 		buf[0] = 'Y';
 	} else {
 		__stop_threaded_test(info);
@@ -1132,7 +1128,12 @@ static ssize_t dtf_write_run(struct file *file, const char __user *user_buf,
 
 	if (strtobool(buf, &bv) == 0) {
 		mutex_lock(&info->lock);
-		ret = __restart_threaded_test(info, bv);
+
+		if (__is_threaded_test_run(info))
+			ret = -EBUSY;
+		else
+			ret = __restart_threaded_test(info, bv);
+
 		mutex_unlock(&info->lock);
 	}
 
-- 
1.8.2.rc0.22.gb3600c3



From vinod.koul at intel.com  Thu May 23 06:54:40 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 23 May 2013 16:24:40 +0530
Subject: [PATCH 26/63] dmaengine: ste_dma40: Supply full Device Tree
 parsing support
In-Reply-To: <1367591569-32197-27-git-send-email-lee.jones@linaro.org>
References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org>
 <1367591569-32197-27-git-send-email-lee.jones@linaro.org>
Message-ID: <20130523105440.GH30200@intel.com>

On Fri, May 03, 2013 at 03:32:12PM +0100, Lee Jones wrote:
> Using the new DMA DT bindings and API, we can register the DMA40 driver
> as Device Tree capable. Now, when a client attempts to allocate a
> channel using the DMA DT bindings via its own node, we are able to parse
> the request and allocate a channel in the correct manner.
> 
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod
> ---
>  .../devicetree/bindings/dma/ste-dma40.txt          |   62 ++++++++++++++++++++
>  drivers/dma/ste_dma40.c                            |   52 ++++++++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/ste-dma40.txt
> 
> diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> new file mode 100644
> index 0000000..2679a87
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> @@ -0,0 +1,62 @@
> +* DMA40 DMA Controller
> +
> +Required properties:
> +- compatible: "stericsson,dma40"
> +- reg: Address range of the DMAC registers
> +- reg-names: Names of the above areas to use during resource look-up
> +- interrupt: Should contain the DMAC interrupt number
> +- #dma-cells: must be <3>
> +
> +Optional properties:
> +- dma-channels: Number of channels supported by hardware - if not present
> +		the driver will attempt to obtain the information from H/W
> +
> +Example:
> +
> +	dma: dma-controller at 801C0000 {
> +		compatible = "stericsson,db8500-dma40", "stericsson,dma40";
> +		reg = <0x801C0000 0x1000  0x40010000 0x800>;
> +		reg-names = "base", "lcpa";
> +		interrupt-parent = <&intc>;
> +		interrupts = <0 25 0x4>;
> +
> +		#dma-cells = <2>;
> +		dma-channels = <8>;
> +	};
> +
> +Clients
> +Required properties:
> +- dmas: Comma separated list of dma channel requests
> +- dma-names: Names of the aforementioned requested channels
> +
> +Each dmas request consists of 4 cells:
> +  1. A phandle pointing to the DMA controller
> +  2. Device Type
> +  3. The DMA request line number (only when 'use fixed channel' is set)
> +  4. A 32bit mask specifying; mode, direction and endianess [NB: This list will grow]
> +        0x00000001: Mode:
> +                Logical channel when unset
> +                Physical channel when set
> +        0x00000002: Direction:
> +                Memory to Device when unset
> +                Device to Memory when set
> +        0x00000004: Endianess:
> +                Little endian when unset
> +                Big endian when set
> +        0x00000008: Use fixed channel:
> +                Use automatic channel selection when unset
> +                Use DMA request line number when set
> +
> +Example:
> +
> +	uart at 80120000 {
> +		compatible = "arm,pl011", "arm,primecell";
> +		reg = <0x80120000 0x1000>;
> +		interrupts = <0 11 0x4>;
> +
> +		dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
> +		       <&dma 13 0 0x0>; /* Logical - MemToDev */
> +		dma-names = "rx", "rx";
> +
> +		status = "disabled";
> +	};
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index d7c2397..b77d508 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -18,6 +18,7 @@
>  #include <linux/pm_runtime.h>
>  #include <linux/err.h>
>  #include <linux/of.h>
> +#include <linux/of_dma.h>
>  #include <linux/amba/bus.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/platform_data/dma-ste-dma40.h>
> @@ -2419,6 +2420,50 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
>  		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
>  }
>  
> +#define D40_DT_FLAGS_MODE(flags)       ((flags >> 0) & 0x1)
> +#define D40_DT_FLAGS_DIR(flags)        ((flags >> 1) & 0x1)
> +#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
> +#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
> +
> +static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
> +				  struct of_dma *ofdma)
> +{
> +	struct stedma40_chan_cfg cfg;
> +	dma_cap_mask_t cap;
> +	u32 flags;
> +
> +	memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
> +
> +	dma_cap_zero(cap);
> +	dma_cap_set(DMA_SLAVE, cap);
> +
> +	cfg.dev_type = dma_spec->args[0];
> +	flags = dma_spec->args[2];
> +
> +	switch (D40_DT_FLAGS_MODE(flags)) {
> +	case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
> +	case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
> +	}
> +
> +	switch (D40_DT_FLAGS_DIR(flags)) {
> +	case 0:
> +		cfg.dir = STEDMA40_MEM_TO_PERIPH;
> +		cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
> +		break;
> +	case 1:
> +		cfg.dir = STEDMA40_PERIPH_TO_MEM;
> +		cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
> +		break;
> +	}
> +
> +	if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
> +		cfg.phy_channel = dma_spec->args[1];
> +		cfg.use_fixed_channel = true;
> +	}
> +
> +	return dma_request_channel(cap, stedma40_filter, &cfg);
> +}
> +
>  /* DMA ENGINE functions */
>  static int d40_alloc_chan_resources(struct dma_chan *chan)
>  {
> @@ -3632,6 +3677,13 @@ static int __init d40_probe(struct platform_device *pdev)
>  
>  	d40_hw_init(base);
>  
> +	if (np) {
> +		err = of_dma_controller_register(np, d40_xlate, NULL);
> +		if (err && err != -ENODEV)
> +			dev_err(&pdev->dev,
> +				"could not register of_dma_controller\n");
> +	}
> +
>  	dev_info(base->dev, "initialized\n");
>  	return 0;
>  
> -- 
> 1.7.10.4
> 


From jonas at microbit.se  Thu May 23 07:38:05 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Thu, 23 May 2013 13:38:05 +0200
Subject: [PATCH] ARM: dts: imx: fix clocks for cspi
Message-ID: <1369309085-31146-1-git-send-email-jonas@microbit.se>

The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.

Signed-off-by: Jonas Andersson <jonas at microbit.se>
---
 arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
 arch/arm/boot/dts/imx27.dtsi |  6 +++---
 arch/arm/boot/dts/imx51.dtsi |  2 +-
 arch/arm/boot/dts/imx53.dtsi |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index d2550e0..7011539 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -141,8 +141,8 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
 				reg = <0x43fa4000 0x4000>;
-				clocks = <&clks 62>;
-				clock-names = "ipg";
+				clocks = <&clks 62>, <&clks 62>;
+				clock-names = "ipg", "per";
 				interrupts = <14>;
 				status = "disabled";
 			};
@@ -182,8 +182,8 @@
 				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
 				reg = <0x50004000 0x4000>;
 				interrupts = <0>;
-				clocks = <&clks 80>;
-				clock-names = "ipg";
+				clocks = <&clks 80>, <&clks 80>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -210,8 +210,8 @@
 				#size-cells = <0>;
 				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
 				reg = <0x50010000 0x4000>;
-				clocks = <&clks 79>;
-				clock-names = "ipg";
+				clocks = <&clks 79>, <&clks 79>;
+				clock-names = "ipg", "per";
 				interrupts = <13>;
 				status = "disabled";
 			};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index ff4bd48..75bd113 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -131,7 +131,7 @@
 				compatible = "fsl,imx27-cspi";
 				reg = <0x1000e000 0x1000>;
 				interrupts = <16>;
-				clocks = <&clks 53>, <&clks 0>;
+				clocks = <&clks 53>, <&clks 53>;
 				clock-names = "ipg", "per";
 				status = "disabled";
 			};
@@ -142,7 +142,7 @@
 				compatible = "fsl,imx27-cspi";
 				reg = <0x1000f000 0x1000>;
 				interrupts = <15>;
-				clocks = <&clks 52>, <&clks 0>;
+				clocks = <&clks 52>, <&clks 52>;
 				clock-names = "ipg", "per";
 				status = "disabled";
 			};
@@ -223,7 +223,7 @@
 				compatible = "fsl,imx27-cspi";
 				reg = <0x10017000 0x1000>;
 				interrupts = <6>;
-				clocks = <&clks 51>, <&clks 0>;
+				clocks = <&clks 51>, <&clks 51>;
 				clock-names = "ipg", "per";
 				status = "disabled";
 			};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 21bb786..53fdde6 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -631,7 +631,7 @@
 				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 				reg = <0x83fc0000 0x4000>;
 				interrupts = <38>;
-				clocks = <&clks 55>, <&clks 0>;
+				clocks = <&clks 55>, <&clks 55>;
 				clock-names = "ipg", "per";
 				status = "disabled";
 			};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 845982e..eb83aa0 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -714,7 +714,7 @@
 				compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 				reg = <0x63fc0000 0x4000>;
 				interrupts = <38>;
-				clocks = <&clks 55>, <&clks 0>;
+				clocks = <&clks 55>, <&clks 55>;
 				clock-names = "ipg", "per";
 				status = "disabled";
 			};
-- 
1.8.1.4



From jason at lakedaemon.net  Thu May 23 07:40:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 07:40:25 -0400
Subject: [PATCH] ARM: kirkwood: refactor dtsi to largest common nodes
In-Reply-To: <1369301130-29900-1-git-send-email-valentin.longchamp@keymile.com>
References: <1369301130-29900-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <20130523114025.GO31290@titan.lakedaemon.net>

Valentin,

On Thu, May 23, 2013 at 11:25:30AM +0200, Valentin Longchamp wrote:
> Some kirkwood variants (for instance present in the prestera SoCs) do
> not have all the peripherals whose nodes are initialized in the
> kirkwood.dtsi. These missing peripherals are SATA, SDIO, and RTC.

Could you provide a little more detail here about the exact problem this
is solving?

> Their corresponding nodes are moved from kirkwood.dtsi to the
> kirkwood-628x.dtsi files so that they still are initialized for these
> variants.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
> ---
>  arch/arm/boot/dts/kirkwood-6281.dtsi | 24 ++++++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-6282.dtsi | 24 ++++++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood.dtsi      | 24 ------------------------
>  3 files changed, 48 insertions(+), 24 deletions(-)

What about kirkwood-nsa310.dts?

thx,

Jason.


From lorenzo.pieralisi at arm.com  Thu May 23 07:49:56 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Thu, 23 May 2013 12:49:56 +0100
Subject: [GIT PULL] ARM cpu logical map init updates
Message-ID: <20130523114956.GA3872@e102568-lin.cambridge.arm.com>

Hi Russell,

following the pull request for DT cpus/cpu bindings for arm/arm64
updates and relative dts files updates:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/170234.html
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/170242.html

please pull the arm core code patches that enable the parsing of the
new bindings. First two patches are two fixes, the first aimed also at
the stable kernel, as marked in the commit log.

Thank you very much indeed,
Lorenzo

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://linux-arm.org/linux-2.6-lp.git dt-init-map-updates

for you to fetch changes up to 1b4a70726dfafb82ebedc017bf02c20edaf5dd29:

  ARM: DT: kernel: DT cpus/cpu node bindings update (2013-05-23 12:35:51 +0100)

----------------------------------------------------------------
Lorenzo Pieralisi (3):
      ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
      ARM: kernel: fix __cpu_logical_map default initialization
      ARM: DT: kernel: DT cpus/cpu node bindings update

 arch/arm/include/asm/cputype.h  |   2 +
 arch/arm/include/asm/smp_plat.h |   2 +-
 arch/arm/kernel/devtree.c       | 149 ++++++++++++++++++++++++----------------
 arch/arm/kernel/setup.c         |   2 +-
 4 files changed, 95 insertions(+), 60 deletions(-)



From catalin.marinas at arm.com  Thu May 23 07:10:37 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 May 2013 12:10:37 +0100
Subject: [PATCH v4 30/32] arm64: KVM: userspace API documentation
In-Reply-To: <1368540840-26750-31-git-send-email-marc.zyngier@arm.com>
References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com>
 <1368540840-26750-31-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130523111037.GL16722@arm.com>

On Tue, May 14, 2013 at 03:13:58PM +0100, Marc Zyngier wrote:
> Unsurprisingly, the arm64 userspace API is extremely similar to
> the 32bit one, the only significant difference being the ONE_REG
> register mapping.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From s.hauer at pengutronix.de  Thu May 23 07:55:05 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 23 May 2013 13:55:05 +0200
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <201305231153.38111.arnd@arndb.de>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <20130523092344.GF32299@pengutronix.de>
 <519DE2EE.1050006@freescale.com> <201305231153.38111.arnd@arndb.de>
Message-ID: <20130523115505.GG32299@pengutronix.de>

On Thu, May 23, 2013 at 11:53:37AM +0200, Arnd Bergmann wrote:
> On Thursday 23 May 2013, Huang Shijie wrote:
> > ? 2013?05?23? 17:23, Sascha Hauer ??:
> > > On Thu, May 23, 2013 at 04:16:13PM +0800, Huang Shijie wrote:
> > >> +			<cs-number>  0<physical address of mapping>  <size>
> > >> +
> > >> +Timing property for child nodes. It is mandatory, not optional.
> > >> +
> > >> + - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
> > >> +			child node. We can get the CS index from the child
> > >> +			node's "reg" property.
> > > This should be more detailed, something like:
> > >
> > > This contains the values for the registers EIM_CSnGCR1, EIM_CSnGCR2,
> > > EIM_CSnRCR1, EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
> > >
> > 
> > 
> > do you mean i should add some new properties, such as
> > "fsl,eim_csnrcr1", "fsl,eim_csnrcr2" ...
> 
> No, the property is fine, just update the documentation the way that
> Sascha suggested.

Yes, that's what I meant.

> 
> > >> +static int weim_remove(struct platform_device *pdev)
> > >> +{
> > >> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> > >> +
> > >> +	clk_disable_unprepare(weim->clk);
> > > Once again: Is this clock needed for the child devices? If yes, you
> > > can't disable it here and leave the child devices registered.
> > >
> 
> But weim_remove will not be called as long as there are children
> registered, right?

But then weim_remove would never be called since nobody unregisters the
children, right?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From daniel at ffwll.ch  Thu May 23 07:55:39 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Thu, 23 May 2013 13:55:39 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
Message-ID: <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>

On Tue, May 21, 2013 at 11:22 AM, Inki Dae <inki.dae at samsung.com> wrote:
>> -----Original Message-----
>> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
>> Vetter
>> Sent: Tuesday, May 21, 2013 4:45 PM
>> To: Inki Dae
>> Cc: 'Daniel Vetter'; 'Rob Clark'; 'linux-fbdev'; 'DRI mailing list';
>> 'Kyungmin Park'; 'myungjoo.ham'; 'YoungJun Cho'; linux-arm-
>> kernel at lists.infradead.org; linux-media at vger.kernel.org
>> Subject: Re: Introduce a new helper framework for buffer synchronization
>>
>> On Tue, May 21, 2013 at 04:03:06PM +0900, Inki Dae wrote:
>> > > - Integration of fence syncing into dma_buf. Imo we should have a
>> > >   per-attachment mode which decides whether map/unmap (and the new
>> sync)
>> > >   should wait for fences or whether the driver takes care of syncing
>> > >   through the new fence framework itself (for direct hw sync).
>> >
>> > I think it's a good idea to have per-attachment mode for buffer sync.
>> But
>> > I'd like to say we make sure what is the purpose of map
>> > (dma_buf_map_attachment)first. This interface is used to get a sgt;
>> > containing pages to physical memory region, and map that region with
>> > device's iommu table. The important thing is that this interface is
>> called
>> > just one time when user wants to share an allocated buffer with dma. But
>> cpu
>> > will try to access the buffer every time as long as it wants. Therefore,
>> we
>> > need cache control every time cpu and dma access the shared buffer:
>> cache
>> > clean when cpu goes to dma and cache invalidate when dma goes to cpu.
>> That
>> > is why I added new interfaces, DMA_BUF_GET_FENCE and DMA_BUF_PUT_FENCE,
>> to
>> > dma buf framework. Of course, Those are ugly so we need a better way: I
>> just
>> > wanted to show you that in such way, we can synchronize the shared
>> buffer
>> > between cpu and dma. By any chance, is there any way that kernel can be
>> > aware of when cpu accesses the shared buffer or is there any point I
>> didn't
>> > catch up?
>>
>> Well dma_buf_map/unmap_attachment should also flush/invalidate any caches,
>> and with the current dma_buf spec those two functions are the _only_ means
>
> I know that dma buf exporter should make sure that cache clean/invalidate
> are done when dma_buf_map/unmap_attachement is called. For this, already we
> do so. However, this function is called when dma buf import is requested by
> user to map a dmabuf fd with dma. This means that dma_buf_map_attachement()
> is called ONCE when user wants to share the dmabuf fd with dma. Actually, in
> case of exynos drm, dma_map_sg_attrs(), performing cache operation
> internally, is called when dmabuf import is requested by user.
>
>> you have to do so. Which strictly means that if you interleave device dma
>> and cpu acccess you need to unmap/map every time.
>>
>> Which is obviously horribly inefficient, but a known gap in the dma_buf
>
> Right, and also this has big overhead.
>
>> interface. Hence why I proposed to add dma_buf_sync_attachment similar to
>> dma_sync_single_for_device:
>>
>> /**
>>  * dma_buf_sync_sg_attachment - sync caches for dma access
>>  * @attach: dma-buf attachment to sync
>>  * @sgt: the sg table to sync (returned by dma_buf_map_attachement)
>>  * @direction: dma direction to sync for
>>  *
>>  * This function synchronizes caches for device dma through the given
>>  * dma-buf attachment when interleaving dma from different devices and the
>>  * cpu. Other device dma needs to be synced also by calls to this
>>  * function (or a pair of dma_buf_map/unmap_attachment calls), cpu access
>>  * needs to be synced with dma_buf_begin/end_cpu_access.
>>  */
>> void dma_buf_sync_sg_attachment(struct dma_buf_attachment *attach,
>>                               struct sg_table *sgt,
>>                               enum dma_data_direction direction)
>>
>> Note that "sync" here only means to synchronize caches, not wait for any
>> outstanding fences. This is simply to be consistent with the established
>> lingo of the dma api. How the dma-buf fences fit into this is imo a
>> different topic, but my idea is that all the cache coherency barriers
>> (i.e. dma_buf_map/unmap_attachment, dma_buf_sync_sg_attachment and
>> dma_buf_begin/end_cpu_access) would automatically block for any attached
>> fences (i.e. block for write fences when doing read-only access, block for
>> all fences otherwise).
>
> As I mentioned already, kernel can't aware of when cpu accesses a shared
> buffer: user can access a shared buffer after mmap anytime and the shared
> buffer should be synchronized between cpu and dma. Therefore, the above
> cache coherency barriers should be called every time cpu and dma tries to
> access a shared buffer, checking before and after of cpu and dma access. And
> exactly, the proposed way do such thing. For this, you can refer to the
> below link,
>
> http://www.mail-archive.com/linux-media at vger.kernel.org/msg62124.html
>
> My point is that how kernel can aware of when those cache coherency barriers
> should be called to synchronize caches and buffer access between cpu and
> dma.
>
>>
>> Then we could do a new dma_buf_attach_flags interface for special cases
>> (might also be useful for other things, similar to the recently added
>> flags in the dma api for wc/no-kernel-mapping/...). A new flag like
>> DMA_BUF_ATTACH_NO_AUTOFENCE would then mean that the driver takes care of
>> all
>> fencing for this attachment and the dma-buf functions should not do the
>> automagic fence blocking.
>>
>> > In Linux kernel, especially embedded system, we had tried to implement
>> > generic interfaces for buffer management; how to allocate a buffer and
>> how
>> > to share a buffer. As a result, now we have CMA (Contiguous Memory
>> > Allocator) for buffer allocation, and we have DMA-BUF for buffer sharing
>> > between cpu and dma. And then how to synchronize a buffer between cpu
>> and
>> > dma? I think now it's best time to discuss buffer synchronization
>> mechanism,
>> > and that is very natural.
>>
>> I think it's important to differentiate between the two meanings of sync:
>> - synchronize caches (i.e. cpu cache flushing in most cases)
>> - and synchronize in-flight dma with fences.
>>
>
> Agree, and I meant that the buffer synchronization mechanism includes the
> above two things. And I think the two things should be addressed together.

I'm still confused about what you're trying to achive in the big
picture here exactly. I think the key point is your statement above
that the kernel can't know when the cpu access a dma-buf. That's not
true though:

For userspace mmaps the kernel can shoot down ptes and so prevent
userspace from accessing a buffer. Since that's pretty inefficient
gem/ttm have additional ioctls for cache coherency transitions.
dma_buf currently has no support for explicit coherency transitions
from userpsace, so if pte shootdown is an issue we need to improve
that.

If I read your proposal correctly you instead suggest to _alway_ flush
cache before/after each dma. That will _completely_ kill performance
(been there with i915, trust me).

For cpu access from kernel space we already have explicit mappings all
over the place (kmap&friends), so I don't see any issues with
inserting the relevant begin/end_cpu_access calls just around the cpu
access. The big exception is the framebuffer layer, but even that has
the deferred io support. KMS otoh has a nice frontbuffer dirty
interface to correctly support dumb clients, unfortunately fbcon does
not (yet) use that.

For these reasons I don't see a need to smash cache coherency and
fencing into one problem, and hence why I've proposed to tackle each
of them individually.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From s.hauer at pengutronix.de  Thu May 23 07:57:03 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 23 May 2013 13:57:03 +0200
Subject: [PATCH] ARM: dts: imx: fix clocks for cspi
In-Reply-To: <1369309085-31146-1-git-send-email-jonas@microbit.se>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
Message-ID: <20130523115702.GH32299@pengutronix.de>

On Thu, May 23, 2013 at 01:38:05PM +0200, Jonas Andersson wrote:
> The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> 
> Signed-off-by: Jonas Andersson <jonas at microbit.se>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

> ---
>  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
>  arch/arm/boot/dts/imx27.dtsi |  6 +++---
>  arch/arm/boot/dts/imx51.dtsi |  2 +-
>  arch/arm/boot/dts/imx53.dtsi |  2 +-
>  4 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> index d2550e0..7011539 100644
> --- a/arch/arm/boot/dts/imx25.dtsi
> +++ b/arch/arm/boot/dts/imx25.dtsi
> @@ -141,8 +141,8 @@
>  				#size-cells = <0>;
>  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
>  				reg = <0x43fa4000 0x4000>;
> -				clocks = <&clks 62>;
> -				clock-names = "ipg";
> +				clocks = <&clks 62>, <&clks 62>;
> +				clock-names = "ipg", "per";
>  				interrupts = <14>;
>  				status = "disabled";
>  			};
> @@ -182,8 +182,8 @@
>  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
>  				reg = <0x50004000 0x4000>;
>  				interrupts = <0>;
> -				clocks = <&clks 80>;
> -				clock-names = "ipg";
> +				clocks = <&clks 80>, <&clks 80>;
> +				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
>  
> @@ -210,8 +210,8 @@
>  				#size-cells = <0>;
>  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
>  				reg = <0x50010000 0x4000>;
> -				clocks = <&clks 79>;
> -				clock-names = "ipg";
> +				clocks = <&clks 79>, <&clks 79>;
> +				clock-names = "ipg", "per";
>  				interrupts = <13>;
>  				status = "disabled";
>  			};
> diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> index ff4bd48..75bd113 100644
> --- a/arch/arm/boot/dts/imx27.dtsi
> +++ b/arch/arm/boot/dts/imx27.dtsi
> @@ -131,7 +131,7 @@
>  				compatible = "fsl,imx27-cspi";
>  				reg = <0x1000e000 0x1000>;
>  				interrupts = <16>;
> -				clocks = <&clks 53>, <&clks 0>;
> +				clocks = <&clks 53>, <&clks 53>;
>  				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
> @@ -142,7 +142,7 @@
>  				compatible = "fsl,imx27-cspi";
>  				reg = <0x1000f000 0x1000>;
>  				interrupts = <15>;
> -				clocks = <&clks 52>, <&clks 0>;
> +				clocks = <&clks 52>, <&clks 52>;
>  				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
> @@ -223,7 +223,7 @@
>  				compatible = "fsl,imx27-cspi";
>  				reg = <0x10017000 0x1000>;
>  				interrupts = <6>;
> -				clocks = <&clks 51>, <&clks 0>;
> +				clocks = <&clks 51>, <&clks 51>;
>  				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
> diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
> index 21bb786..53fdde6 100644
> --- a/arch/arm/boot/dts/imx51.dtsi
> +++ b/arch/arm/boot/dts/imx51.dtsi
> @@ -631,7 +631,7 @@
>  				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
>  				reg = <0x83fc0000 0x4000>;
>  				interrupts = <38>;
> -				clocks = <&clks 55>, <&clks 0>;
> +				clocks = <&clks 55>, <&clks 55>;
>  				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
> diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> index 845982e..eb83aa0 100644
> --- a/arch/arm/boot/dts/imx53.dtsi
> +++ b/arch/arm/boot/dts/imx53.dtsi
> @@ -714,7 +714,7 @@
>  				compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
>  				reg = <0x63fc0000 0x4000>;
>  				interrupts = <38>;
> -				clocks = <&clks 55>, <&clks 0>;
> +				clocks = <&clks 55>, <&clks 55>;
>  				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
> -- 
> 1.8.1.4
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shc_work at mail.ru  Thu May 23 08:01:14 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 16:01:14 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSF0gQVJNOiBkdHM6IGlteDogZml4IGNsb2NrcyBmb3IgY3Nw?=
 =?UTF-8?B?aQ==?=
In-Reply-To: <1369309085-31146-1-git-send-email-jonas@microbit.se>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
Message-ID: <1369310474.965158503@f320.mail.ru>

> The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> 
> Signed-off-by: Jonas Andersson <jonas at microbit.se>
> ---
>  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
>  arch/arm/boot/dts/imx27.dtsi |  6 +++---
>  arch/arm/boot/dts/imx51.dtsi |  2 +-
>  arch/arm/boot/dts/imx53.dtsi |  2 +-
>  4 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> index d2550e0..7011539 100644
> --- a/arch/arm/boot/dts/imx25.dtsi
> +++ b/arch/arm/boot/dts/imx25.dtsi
> @@ -141,8 +141,8 @@
>  				#size-cells = <0>;
>  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
>  				reg = <0x43fa4000 0x4000>;
> -				clocks = <&clks 62>;
> -				clock-names = "ipg";
> +				clocks = <&clks 62>, <&clks 62>;
> +				clock-names = "ipg", "per";
>  				interrupts = <14>;
>  				status = "disabled";
>  			};

Why you do not use "dummy" clock for "per" here?
This variant will request/enable one clock two times.

---

From plagnioj at jcrosoft.com  Thu May 23 07:58:45 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 13:58:45 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523132255.3acf4431@skate>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com> <20130523120920.1df8e23a@skate>
 <20130523100951.GH9937@game.jcrosoft.org>
 <20130523122000.22a9a4d0@skate>
 <20130523102601.GI9937@game.jcrosoft.org>
 <20130523132255.3acf4431@skate>
Message-ID: <20130523115845.GA24476@game.jcrosoft.org>

On 13:22 Thu 23 May     , Thomas Petazzoni wrote:
> Dear Jean-Christophe PLAGNIOL-VILLARD,
> 
> On Thu, 23 May 2013 12:26:01 +0200, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
> 
> > > Did you read what I write? In arch/arm/mach-at91/pm.c, the only
> > > accesses made to the AIC registers are for pr_debug() calls, i.e only
> > > to print some debugging messages. I believe those ones can simply be
> > > removed to decouple the pm.c code from the irq.c code.
> > 
> > yes I read and yes I do not want to move code before we do cleanup MANDATORY
> 
> Then please explain to our volunteer contributor what sort of cleanup
> is required. Simply NACKing without offering any insight as to how
> things should be done is completely useless, counter-productive, and a
> complete abuse of a maintainer's power over contributors.
> 
> > >  * PATCH 1: remove usage of AIC registers for debug messages in pm.c
> > NACK I do want this debug, very usefull to debug pm
> 
> For the cases where you need to debug this stuff, you can always re-add
> some instrumentation in this code to dump whatever you want.
> 
> Or, alternatively, we can make the irqchip driver show using
> pr_debug() the value of IMR in its ->suspend() hook, the value of IMR &
> IPR in its ->resume() hook, and the pm.c code can show the PMC_PCSR on
> suspend. This way, you have all the informations you need for debugging.

if you read the code as you said both of them are link PMC & AIC so you can
not hope to split it as both of the IP contain part of the information

so no I want the information right where it's
> 
> Having the PM driver and the irqchip driver step on each other register
> areas is anyway a bad idea, especially when the only reason to do so is
> for two debugging messages that can be implemented differently.

> 
> Notice that this solution can always be improved later on if needed,
> with further cleanups from you.
> 
> But please stop rejecting valid patches from contributors, just because
> the code is not coming from you. What Boris is proposing is perfectly
so If I read you non clean code can come mainline, wow this not the way to
work. If for you do half clean is enough to go mainline. You really need to
change your way of working.

Best Regards,
J.


From plagnioj at jcrosoft.com  Thu May 23 07:59:14 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 13:59:14 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523101825.GL18614@n2100.arm.linux.org.uk>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523101825.GL18614@n2100.arm.linux.org.uk>
Message-ID: <20130523115914.GB24476@game.jcrosoft.org>

On 11:18 Thu 23 May     , Russell King - ARM Linux wrote:
> On Thu, May 23, 2013 at 11:05:07AM +0200, Boris BREZILLON wrote:
> > Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
> > Move arch/arm/mach-at91/at91_aic.h to
> > arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
> > to header file :
> > #include "../../arch/arm/mach-at91/at91_aic.h"
> 
> The right way to do this is to move the definitions which should only
> be used by arch/arm/mach-at91/irq.c to that file or a header file along
> side that file, and find a place in include/linux for the remainder.
> 
> I notice arch/arm/mach-at91/pm.c makes use of some of the register
> definitions:
> 
>         at91_irq_suspend();
> 
>         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
>                         /* remember all the always-wake irqs */
>                         (at91_pmc_read(AT91_PMC_PCSR)
>                                         | (1 << AT91_ID_FIQ)
>                                         | (1 << AT91_ID_SYS)
>                                         | (at91_extern_irq))
>                                 & at91_aic_read(AT91_AIC_IMR),
>                         state);
> 
> at91_irq_suspend() is in arch/arm/mach-at91/irq.c already, so there's no
> reason that fragment can't be moved there.
> 
> That leaves: at91_aic_handle_irq, at91_aic5_handle_irq, NR_AIC_IRQS and
> NR_AIC5_IRQS, which if you did patch 3 first, would leave you with just
> the NR_.*_IRQS definitions to find a home for.

Boris please update as this

Best Regards,
J.


From thomas.petazzoni at free-electrons.com  Thu May 23 08:09:19 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 14:09:19 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523115845.GA24476@game.jcrosoft.org>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org>
 <519DE6A8.6040502@overkiz.com> <20130523120920.1df8e23a@skate>
 <20130523100951.GH9937@game.jcrosoft.org>
 <20130523122000.22a9a4d0@skate>
 <20130523102601.GI9937@game.jcrosoft.org>
 <20130523132255.3acf4431@skate>
 <20130523115845.GA24476@game.jcrosoft.org>
Message-ID: <20130523140919.1b5800f2@skate>

Dear Jean-Christophe PLAGNIOL-VILLARD,

On Thu, 23 May 2013 13:58:45 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:

> > Or, alternatively, we can make the irqchip driver show using
> > pr_debug() the value of IMR in its ->suspend() hook, the value of IMR &
> > IPR in its ->resume() hook, and the pm.c code can show the PMC_PCSR on
> > suspend. This way, you have all the informations you need for debugging.
> 
> if you read the code as you said both of them are link PMC & AIC so you can
> not hope to split it as both of the IP contain part of the information
> 
> so no I want the information right where it's

Sorry, but that seems like a completely unreasonable requirement,
provided that it makes the PM code poke into a completely unrelated IP,
just for the sake of one debug message.

> > Having the PM driver and the irqchip driver step on each other register
> > areas is anyway a bad idea, especially when the only reason to do so is
> > for two debugging messages that can be implemented differently.
> 
> > 
> > Notice that this solution can always be improved later on if needed,
> > with further cleanups from you.
> > 
> > But please stop rejecting valid patches from contributors, just because
> > the code is not coming from you. What Boris is proposing is perfectly
> so If I read you non clean code can come mainline, wow this not the way to
> work. If for you do half clean is enough to go mainline. You really need to
> change your way of working.

Boris patches are far from being half-clean. To me, they look perfectly
sane, and are going in the right direction. Again, please stop
rejecting contributions from third-parties just because you're not the
author of such contributions.

It's you who said that they are not clean, but you still haven't given
the slightest explanation to justify that. Until a proper justification
is given, that points to specific, identifiable, and reasonable
problems in the patches, there is absolutely no reason not to consider
Boris patches as acceptable (once the header problem is fixed, of
course).

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From shc_work at mail.ru  Thu May 23 08:10:59 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 16:10:59 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSF0gQVJNOiBkdHM6IGlteDogZml4IGNsb2NrcyBmb3Ig?=
 =?UTF-8?B?Y3NwaQ==?=
In-Reply-To: <1369310474.965158503@f320.mail.ru>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
 <1369310474.965158503@f320.mail.ru>
Message-ID: <1369311059.366490908@f190.mail.ru>

> > The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> > 
> > Signed-off-by: Jonas Andersson <jonas at microbit.se>
> > ---
> >  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
> >  arch/arm/boot/dts/imx27.dtsi |  6 +++---
> >  arch/arm/boot/dts/imx51.dtsi |  2 +-
> >  arch/arm/boot/dts/imx53.dtsi |  2 +-
> >  4 files changed, 11 insertions(+), 11 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> > index d2550e0..7011539 100644
> > --- a/arch/arm/boot/dts/imx25.dtsi
> > +++ b/arch/arm/boot/dts/imx25.dtsi
> > @@ -141,8 +141,8 @@
> >  				#size-cells = <0>;
> >  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
> >  				reg = <0x43fa4000 0x4000>;
> > -				clocks = <&clks 62>;
> > -				clock-names = "ipg";
> > +				clocks = <&clks 62>, <&clks 62>;
> > +				clock-names = "ipg", "per";
> >  				interrupts = <14>;
> >  				status = "disabled";
> >  			};

Sorry, typo.

> Why you do not use "dummy" clock for "per" here?

*for "ipg"

> This variant will request/enable one clock two times.
 
---

From arnd at arndb.de  Thu May 23 08:09:02 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 14:09:02 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <20130523112401.GO18614@n2100.arm.linux.org.uk>
References: <519DCBEF.3090208@asianux.com> <201305231259.43750.arnd@arndb.de>
 <20130523112401.GO18614@n2100.arm.linux.org.uk>
Message-ID: <201305231409.02359.arnd@arndb.de>

On Thursday 23 May 2013, Russell King - ARM Linux wrote:
> This is the problem you guys are missing - unreachable() means "we lose
> control of the CPU at this point".

I'm absolutely aware of this. Again, the current behaviour of doing nothing
at all isn't very different from undefined behavior when you get when you
get to the end of a function returning a pointer without a "return" statement,
or when you return from a function that has determined that it is not safe
to continue.

> If you have an embedded system and you've taken out all the printk()
> stuff, you most certainly want the system to do something if you hit
> an unexpected condition.

I did not claim that it was a good idea to disable BUG(), all I said is
that "random stuff may happen" is probably what Matt Mackall had in mind when
he introduced the option.

	Arnd


From thomas.petazzoni at free-electrons.com  Thu May 23 08:13:44 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 14:13:44 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523101825.GL18614@n2100.arm.linux.org.uk>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523101825.GL18614@n2100.arm.linux.org.uk>
Message-ID: <20130523141344.7a01ce88@skate>

Dear Russell King - ARM Linux,

On Thu, 23 May 2013 11:18:25 +0100, Russell King - ARM Linux wrote:

> I notice arch/arm/mach-at91/pm.c makes use of some of the register
> definitions:
> 
>         at91_irq_suspend();
> 
>         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
>                         /* remember all the always-wake irqs */
>                         (at91_pmc_read(AT91_PMC_PCSR)
>                                         | (1 << AT91_ID_FIQ)
>                                         | (1 << AT91_ID_SYS)
>                                         | (at91_extern_irq))
>                                 & at91_aic_read(AT91_AIC_IMR),
>                         state);
> 
> at91_irq_suspend() is in arch/arm/mach-at91/irq.c already, so there's no
> reason that fragment can't be moved there.

The problem is that the goal of the patch set is to move
arch/arm/mach-at91/irq.c into drivers/irqchip/.

However, if you move that chunk of code to drivers/irqchip/irq-at91.c,
you are using at91_pmc_read() which is defined in
arch/arm/mach-at91/include/mach/at91_pmc.h. So,
drivers/irqchip/irq-at91.c would have to include such an header file,
which is something we want to avoid since drivers/ code should not
include something in <mach/...>, as it breaks multiplatform kernels.

So, I'm afraid, simply moving this chunk of code in at91_irq_suspend()
doesn't make the thing any better.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From plagnioj at jcrosoft.com  Thu May 23 08:11:01 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 May 2013 14:11:01 +0200
Subject: [PATCH] at91: sama5: fix incorrect PMC pcr div definition
In-Reply-To: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>
References: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>
Message-ID: <20130523121101.GC24476@game.jcrosoft.org>

On 18:18 Thu 23 May     , Josh Wu wrote:
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Best Regards,
J.
> ---
>  arch/arm/mach-at91/include/mach/at91_pmc.h |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
> index 31df120..2bd7f51 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> @@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base;
>  #define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command (read=0, write=1) */
>  #define		AT91_PMC_PCR_DIV(n)	((n)  <<  16)		/* Divisor Value */
>  #define			AT91_PMC_PCR_DIV0	0x0			/* Peripheral clock is MCK */
> -#define			AT91_PMC_PCR_DIV2	0x2			/* Peripheral clock is MCK/2 */
> -#define			AT91_PMC_PCR_DIV4	0x4			/* Peripheral clock is MCK/4 */
> -#define			AT91_PMC_PCR_DIV8	0x8			/* Peripheral clock is MCK/8 */
> +#define			AT91_PMC_PCR_DIV2	0x1			/* Peripheral clock is MCK/2 */
> +#define			AT91_PMC_PCR_DIV4	0x2			/* Peripheral clock is MCK/4 */
> +#define			AT91_PMC_PCR_DIV8	0x3			/* Peripheral clock is MCK/8 */
>  #define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
>  
>  #endif
> -- 
> 1.7.10
> 


From ludovic.desroches at atmel.com  Thu May 23 08:16:52 2013
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Thu, 23 May 2013 14:16:52 +0200
Subject: [PATCH] at91: sama5: fix incorrect PMC pcr div definition
In-Reply-To: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>
References: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>
Message-ID: <20130523121652.GB3013@ludovic.desroches@atmel.com>

On Thu, May 23, 2013 at 06:18:48PM +0800, Josh Wu wrote:
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Nice catch, thanks Josh.

Ludovic

> ---
>  arch/arm/mach-at91/include/mach/at91_pmc.h |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
> index 31df120..2bd7f51 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> @@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base;
>  #define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command (read=0, write=1) */
>  #define		AT91_PMC_PCR_DIV(n)	((n)  <<  16)		/* Divisor Value */
>  #define			AT91_PMC_PCR_DIV0	0x0			/* Peripheral clock is MCK */
> -#define			AT91_PMC_PCR_DIV2	0x2			/* Peripheral clock is MCK/2 */
> -#define			AT91_PMC_PCR_DIV4	0x4			/* Peripheral clock is MCK/4 */
> -#define			AT91_PMC_PCR_DIV8	0x8			/* Peripheral clock is MCK/8 */
> +#define			AT91_PMC_PCR_DIV2	0x1			/* Peripheral clock is MCK/2 */
> +#define			AT91_PMC_PCR_DIV4	0x2			/* Peripheral clock is MCK/4 */
> +#define			AT91_PMC_PCR_DIV8	0x3			/* Peripheral clock is MCK/8 */
>  #define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
>  
>  #endif
> -- 
> 1.7.10
> 


From thomas.petazzoni at free-electrons.com  Thu May 23 08:23:01 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 14:23:01 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305222240.05124.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <201305222240.05124.arnd@arndb.de>
Message-ID: <20130523142301.10dbeff9@skate>

Dear Arnd Bergmann,

On Wed, 22 May 2013 22:40:04 +0200, Arnd Bergmann wrote:

> > So you're proposing to add two Kconfig options, one to have the UART at
> > 0xd0012000 and the other one to have the UART at 0xf1012000. The user
> > would have to know whether he is going to boot with an old bootloader
> > or new bootloader, and select the appropriate option. This means that
> > the mvebu_defconfig would no longer be able to have earlyprintk enabled
> > by default, otherwise the resulting kernel may not boot for some
> > people, but maybe it's a reasonable tradeoff.
> 
> Yes. It may also be reasonable to use the CP15 hack for DEBUG_LL, but
> I would not like to see that information getting used anywhere in the
> kernel outside of DEBUG_LL. That should really come from the DT.

Ok.

> > And what happens when Globalscale (Mirabox manufacturer) or Plathome
> > (manufacturer of OpenBlocks) release a new bootloader version, based on
> > the new bootloader from Marvell, which remaps things at 0xf1000000 ? Or
> > when those people boot from Barebox, which remaps at 0xf1000000 ?
> > 
> > Conclusion: you can't classify on one side boards that are at 0xd0 and
> > boards that are at 0xf1. It depends on which bootloader each
> > particular instance of those boards will be using. Will it be a
> > bootloader that complies with the "old" protocol (CP15 bit cleared and
> > registers at 0xd0) or the "new" protocol (CP15 bit set and registers at
> > 0xf1).
> > 
> > So we can't encode into the boards Device Tree whether the registers
> > are at 0xd0 or 0xf1, because it's not a board-related information, but
> > a bootloader-related information.
> 
> The new boot loaders will of course know that they are remapping the
> registers, so they are also able to put the correct information into the
> DT.

But that's *not* the case. Neither the old nor the new bootloaders are
changing the Device Tree in any way that allows us to know whether
registers are mapped at 0xd0 and 0xf1. Those bootloaders are already in
the field, and we have little control over that. Even if we had
control, what we would tell Marvell to implement in their U-Boot,
today? The DT binding of the mbus driver is not complete, and therefore
the mechanism to specify the location of the internal registers is
going to change when we introduce the DT binding for the mbus driver.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From s.hauer at pengutronix.de  Thu May 23 08:36:42 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 23 May 2013 14:36:42 +0200
Subject: [PATCH] ARM: dts: imx: fix clocks for cspi
In-Reply-To: <1369311059.366490908@f190.mail.ru>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
 <1369310474.965158503@f320.mail.ru>
 <1369311059.366490908@f190.mail.ru>
Message-ID: <20130523123642.GK32299@pengutronix.de>

On Thu, May 23, 2013 at 04:10:59PM +0400, Alexander Shiyan wrote:
> > > The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> > > 
> > > Signed-off-by: Jonas Andersson <jonas at microbit.se>
> > > ---
> > >  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
> > >  arch/arm/boot/dts/imx27.dtsi |  6 +++---
> > >  arch/arm/boot/dts/imx51.dtsi |  2 +-
> > >  arch/arm/boot/dts/imx53.dtsi |  2 +-
> > >  4 files changed, 11 insertions(+), 11 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> > > index d2550e0..7011539 100644
> > > --- a/arch/arm/boot/dts/imx25.dtsi
> > > +++ b/arch/arm/boot/dts/imx25.dtsi
> > > @@ -141,8 +141,8 @@
> > >  				#size-cells = <0>;
> > >  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
> > >  				reg = <0x43fa4000 0x4000>;
> > > -				clocks = <&clks 62>;
> > > -				clock-names = "ipg";
> > > +				clocks = <&clks 62>, <&clks 62>;
> > > +				clock-names = "ipg", "per";
> > >  				interrupts = <14>;
> > >  				status = "disabled";
> > >  			};
> 
> Sorry, typo.
> 
> > Why you do not use "dummy" clock for "per" here?
> 
> *for "ipg"

Because the same clock is used for the register clock and the baudrate
clock. You have to enable the ipg clock to access registers.

> 
> > This variant will request/enable one clock two times.

Indeed, but what's the problem with this?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux-arm at overkiz.com  Thu May 23 08:42:24 2013
From: linux-arm at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 14:42:24 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523141344.7a01ce88@skate>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523101825.GL18614@n2100.arm.linux.org.uk>
 <20130523141344.7a01ce88@skate>
Message-ID: <519E0EB0.7000502@overkiz.com>

On 23/05/2013 14:13, Thomas Petazzoni wrote:
> Dear Russell King - ARM Linux,
>
> On Thu, 23 May 2013 11:18:25 +0100, Russell King - ARM Linux wrote:
>
>> I notice arch/arm/mach-at91/pm.c makes use of some of the register
>> definitions:
>>
>>          at91_irq_suspend();
>>
>>          pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
>>                          /* remember all the always-wake irqs */
>>                          (at91_pmc_read(AT91_PMC_PCSR)
>>                                          | (1 << AT91_ID_FIQ)
>>                                          | (1 << AT91_ID_SYS)
>>                                          | (at91_extern_irq))
>>                                  & at91_aic_read(AT91_AIC_IMR),
>>                          state);
>>
>> at91_irq_suspend() is in arch/arm/mach-at91/irq.c already, so there's no
>> reason that fragment can't be moved there.
>
> The problem is that the goal of the patch set is to move
> arch/arm/mach-at91/irq.c into drivers/irqchip/.
>
> However, if you move that chunk of code to drivers/irqchip/irq-at91.c,
> you are using at91_pmc_read() which is defined in
> arch/arm/mach-at91/include/mach/at91_pmc.h. So,
> drivers/irqchip/irq-at91.c would have to include such an header file,
> which is something we want to avoid since drivers/ code should not
> include something in <mach/...>, as it breaks multiplatform kernels.
>
> So, I'm afraid, simply moving this chunk of code in at91_irq_suspend()
> doesn't make the thing any better.
>
What about keeping the former at91_aic.h in arch/arm/match-at91 and copy 
the definitions we need in drivers/irqchip/irq-at91.c ?

This way we get an aic irqchip driver independant of any specific 
machine headers and keep the non dt boards and pm drivers without any 
change.

> Best regards,
>
> Thomas
>



From b.brezillon at overkiz.com  Thu May 23 08:44:03 2013
From: b.brezillon at overkiz.com (boris brezillon)
Date: Thu, 23 May 2013 14:44:03 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523141344.7a01ce88@skate>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523101825.GL18614@n2100.arm.linux.org.uk>
 <20130523141344.7a01ce88@skate>
Message-ID: <519E0F13.4080208@overkiz.com>

On 23/05/2013 14:13, Thomas Petazzoni wrote:
> Dear Russell King - ARM Linux,
>
> On Thu, 23 May 2013 11:18:25 +0100, Russell King - ARM Linux wrote:
>
>> I notice arch/arm/mach-at91/pm.c makes use of some of the register
>> definitions:
>>
>>          at91_irq_suspend();
>>
>>          pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
>>                          /* remember all the always-wake irqs */
>>                          (at91_pmc_read(AT91_PMC_PCSR)
>>                                          | (1 << AT91_ID_FIQ)
>>                                          | (1 << AT91_ID_SYS)
>>                                          | (at91_extern_irq))
>>                                  & at91_aic_read(AT91_AIC_IMR),
>>                          state);
>>
>> at91_irq_suspend() is in arch/arm/mach-at91/irq.c already, so there's no
>> reason that fragment can't be moved there.
> The problem is that the goal of the patch set is to move
> arch/arm/mach-at91/irq.c into drivers/irqchip/.
>
> However, if you move that chunk of code to drivers/irqchip/irq-at91.c,
> you are using at91_pmc_read() which is defined in
> arch/arm/mach-at91/include/mach/at91_pmc.h. So,
> drivers/irqchip/irq-at91.c would have to include such an header file,
> which is something we want to avoid since drivers/ code should not
> include something in <mach/...>, as it breaks multiplatform kernels.
>
> So, I'm afraid, simply moving this chunk of code in at91_irq_suspend()
> doesn't make the thing any better.
What about keeping the former at91_aic.h in arch/arm/match-at91 and copy 
the definitions we need in drivers/irqchip/irq-at91.c ?

This way we get an aic irqchip driver independant of any specific 
machine headers and keep the non dt boards and pm drivers without any 
change.
>
> Best regards,
>
> Thomas



From linux at arm.linux.org.uk  Thu May 23 08:50:33 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 13:50:33 +0100
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since
 always need it.
In-Reply-To: <201305231409.02359.arnd@arndb.de>
References: <519DCBEF.3090208@asianux.com> <201305231259.43750.arnd@arndb.de>
 <20130523112401.GO18614@n2100.arm.linux.org.uk>
 <201305231409.02359.arnd@arndb.de>
Message-ID: <20130523125033.GP18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 02:09:02PM +0200, Arnd Bergmann wrote:
> On Thursday 23 May 2013, Russell King - ARM Linux wrote:
> > This is the problem you guys are missing - unreachable() means "we lose
> > control of the CPU at this point".
> 
> I'm absolutely aware of this. Again, the current behaviour of doing nothing
> at all isn't very different from undefined behavior when you get when you
> get to the end of a function returning a pointer without a "return" statement,
> or when you return from a function that has determined that it is not safe
> to continue.

Running off the end of a function like that is a different kettle of fish.
The execution path is still as the compiler intends - what isn't is that
the data returned is likely to be random trash.

That's _quite_ different from the CPU starting to execute the contents
of a literal data pool.


From nicolas.ferre at atmel.com  Thu May 23 09:00:08 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 May 2013 15:00:08 +0200
Subject: [PATCH 1/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <20130523132255.3acf4431@skate>
References: <1369299909-10078-1-git-send-email-b.brezillon@overkiz.com>
 <1369299909-10078-2-git-send-email-b.brezillon@overkiz.com>
 <20130523090611.GG9937@game.jcrosoft.org> <519DE6A8.6040502@overkiz.com>
 <20130523120920.1df8e23a@skate> <20130523100951.GH9937@game.jcrosoft.org>
 <20130523122000.22a9a4d0@skate> <20130523102601.GI9937@game.jcrosoft.org>
 <20130523132255.3acf4431@skate>
Message-ID: <519E12D8.4070903@atmel.com>

On 23/05/2013 13:22, Thomas Petazzoni :
> Dear Jean-Christophe PLAGNIOL-VILLARD,

[..]

> It would be good if the other AT91 maintainers could raise their voice
> here, so that Boris knows whether it is worthwhile doing additional
> revisions of this patch set.

Guys, I do not like the role that I am forced to play...

Anyway, Boris I do like the intention of this patch series and be sure 
that we will integrate it as soon as it is ready.

Bye,
-- 
Nicolas Ferre


From maxime.ripard at free-electrons.com  Thu May 23 09:00:39 2013
From: maxime.ripard at free-electrons.com (maxime.ripard at free-electrons.com)
Date: Thu, 23 May 2013 15:00:39 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <519E03B0.1080006@digi.com>
References: <519E03B0.1080006@digi.com>
Message-ID: <20130523130039.GF8595@lukather>

Hi Hector,

On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> Hello,
> 
> I'm using an i.MX28 based board with lcd connected with 18bits data bus.
> My platform uses 32 bits per pixel:
> 
> 	mxsfb_pdata.default_bpp = 32;
> 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
> 
> With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
> at HW_LCDIF_CTRL register in function mxsfb_set_par():
> 
> 	case 32:
> 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
> 		ctrl |= CTRL_SET_WORD_LENGTH(3);
> 		switch (host->ld_intf_width) {
> 		case STMLCDIF_8BIT:
> 			dev_dbg(&host->pdev->dev,
> 					"Unsupported LCD bus width mapping\n");
> 			return -EINVAL;
> 		case STMLCDIF_16BIT:
> 		case STMLCDIF_18BIT:
> 			/* 24 bit to 18 bit mapping */
> 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> 					    *  each colour component
> 					    */
> 			break;
> 		case STMLCDIF_24BIT:
> 			/* real 24 bit */
> 			break;
> 		}
> 
> According to the manual, this flag does:
> 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
> format, such that all RGB 888 data is contained in 24 bits.
> 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
> actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
> 2 bits in each byte do not contain any useful data, and should be
> dropped.
> 
> The setting of this flag is producing bad colours with true colour
> images (i.e. the Linux penguin is displayed ok, but QT applications
> or images displayed with fbv are not).
> I believe the setting of this flag is not correct (after all, if my
> bpp is 32, then all 24bit colours are useful and dropping the upper
> 2 bits is a bad idea).
> If I don't set it, then true colour images are displayed correctly.
> The only problem is that the Linux penguin is displayed much darker
> than usual (correct colours, but darker). Perhaps the 224 colour
> format of this image justifies it?
> 
> I noticed the cfa10049 platform also uses the same configuration (18
> bits data bus and 32bpp) and was wondering if true colour images are
> correctly displayed in this platform with this flag set (for example
> with fbv application [1]).

I had the exact same problem, and suggested the exact same solution a
few weeks back.

https://patchwork.kernel.org/patch/2470441/

The conclusion of that discussion what that the userspace applications
were not honouring the bitfield correctly set by the mxsfb driver, and
as such, it was not a bug in the driver.

While this is correct, I wonder, now that since we had that same problem
in a very short amount of time, if we couldn't set this behaviour
dependant of some (dt? kernel argument?) property so that one could
customise it anyway he want.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From arnd at arndb.de  Thu May 23 09:09:57 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 15:09:57 +0200
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <20130523115505.GG32299@pengutronix.de>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <201305231153.38111.arnd@arndb.de> <20130523115505.GG32299@pengutronix.de>
Message-ID: <201305231509.57651.arnd@arndb.de>

On Thursday 23 May 2013, Sascha Hauer wrote:
> > > >> +static int weim_remove(struct platform_device *pdev)
> > > >> +{
> > > >> +        struct imx_weim *weim = platform_get_drvdata(pdev);
> > > >> +
> > > >> +        clk_disable_unprepare(weim->clk);
> > > > Once again: Is this clock needed for the child devices? If yes, you
> > > > can't disable it here and leave the child devices registered.
> > > >
> > 
> > But weim_remove will not be called as long as there are children
> > registered, right?
> 
> But then weim_remove would never be called since nobody unregisters the
> children, right?
> 

Ah, right. That is actually another problem: if the probe() function
creates the child devices, the remove() function should tear them down
again. If we do that, we can ensure that the clock is only turned
off after the last child is gone.

OTOH, I agree that it would be nicer if the clk could remain turned
off as long as no children are active. Can we do a clk_disable()
after setting up the timings for the children and then expect those
to actually start up the clk again when they need it?

Or to take things further: would it make sense to represent WEIM
itself as a clock driver and perform the settings for each child
only when it sets up its own clk?

I guess it would also make sense to use of_platform_populate() instead
of of_platform_device_create() when creating the children, so we actually
create the entire hierarchy in case of the children itself is a
"simple-bus".

	Arnd


From ulf.hansson at stericsson.com  Thu May 23 09:13:44 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:44 +0200
Subject: [PATCH 0/6] ARM: ux500: Update configurations for SD/SDIO/(e)MMC
Message-ID: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

This patchset includes especially enablement for UHS-I SD cards, but
also some cleanups and additional enabling of SD/SDIO/(e)MMC features.

These changes shall also be adapted to the corresponding DT files,
but that is left as a separate task and outside this patchset.

Ulf Hansson (6):
  ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices
  ARM: ux500: Don't set plf ocr mask for SD/MMC device
  ARM: ux500: Enable support for RPMB and Reliable Write for eMMC
  ARM: ux500: Enable support for discard for MMC/SD
  ARM: ux500: Set eMMC and WLAN card slot as non-removable
  ARM: ux500: Enable support for UHS-I SD-cards

 arch/arm/mach-ux500/board-mop500-sdi.c |   34 +++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 12 deletions(-)

-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 09:13:45 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:45 +0200
Subject: [PATCH 1/6] ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369314830-3727-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

We are able to cope with an SDMMC clock of 100MHz so let's
make use of the full frequency instead of the half.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 0ef3877..eb9b2de 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -53,7 +53,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi0_data = {
 	.ocr_mask	= MMC_VDD_29_30,
-	.f_max		= 50000000,
+	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_SD_HIGHSPEED |
 				MMC_CAP_MMC_HIGHSPEED,
@@ -106,7 +106,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi1_data = {
 	.ocr_mask	= MMC_VDD_29_30,
-	.f_max		= 50000000,
+	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA,
 	.gpio_cd	= -1,
 	.gpio_wp	= -1,
@@ -143,7 +143,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi2_data = {
 	.ocr_mask	= MMC_VDD_165_195,
-	.f_max		= 50000000,
+	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
 			  MMC_CAP_MMC_HIGHSPEED,
 	.gpio_cd	= -1,
@@ -181,7 +181,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi4_data = {
 	.ocr_mask	= MMC_VDD_29_30,
-	.f_max		= 50000000,
+	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
 			  MMC_CAP_MMC_HIGHSPEED,
 	.gpio_cd	= -1,
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 09:13:46 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:46 +0200
Subject: [PATCH 2/6] ARM: ux500: Don't set plf ocr mask for SD/MMC device
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369314830-3727-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

The mmci host driver overrides platform ocr mask when a vmmc regulator
can be used. This is the case for sdi0(SD-card) and for sdi4(eMMC).
Thus it is pointless of specifing these mask and why we do remove them.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index eb9b2de..c0573d2 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -52,7 +52,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 #endif
 
 struct mmci_platform_data mop500_sdi0_data = {
-	.ocr_mask	= MMC_VDD_29_30,
 	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_SD_HIGHSPEED |
@@ -180,7 +179,6 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 #endif
 
 struct mmci_platform_data mop500_sdi4_data = {
-	.ocr_mask	= MMC_VDD_29_30,
 	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
 			  MMC_CAP_MMC_HIGHSPEED,
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 09:13:47 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:47 +0200
Subject: [PATCH 3/6] ARM: ux500: Enable support for RPMB and Reliable Write
 for eMMC
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369314830-3727-4-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

By adding MMC_CAP_CMD23 for the eMMC devices, we can support RPMB
and Reliable Write. Additionally it will mean CMD12 will not be sent
to end a successful data transfer.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |   12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index c0573d2..9bb3ca5 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -143,8 +143,10 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 struct mmci_platform_data mop500_sdi2_data = {
 	.ocr_mask	= MMC_VDD_165_195,
 	.f_max		= 100000000,
-	.capabilities	= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-			  MMC_CAP_MMC_HIGHSPEED,
+	.capabilities	= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_8_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED |
+				MMC_CAP_CMD23,
 	.gpio_cd	= -1,
 	.gpio_wp	= -1,
 #ifdef CONFIG_STE_DMA40
@@ -180,8 +182,10 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi4_data = {
 	.f_max		= 100000000,
-	.capabilities	= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-			  MMC_CAP_MMC_HIGHSPEED,
+	.capabilities	= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_8_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED |
+				MMC_CAP_CMD23,
 	.gpio_cd	= -1,
 	.gpio_wp	= -1,
 #ifdef CONFIG_STE_DMA40
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 09:13:49 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:49 +0200
Subject: [PATCH 5/6] ARM: ux500: Set eMMC and WLAN card slot as non-removable
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369314830-3727-6-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

For several reasons, the mmc protocol layer expects devices
being non-removable to use MMC_CAP_NONREMOVABLE, so then we
adapt to this expectation.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 3c07f55..2e341fb 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -107,7 +107,8 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 struct mmci_platform_data mop500_sdi1_data = {
 	.ocr_mask	= MMC_VDD_29_30,
 	.f_max		= 100000000,
-	.capabilities	= MMC_CAP_4_BIT_DATA,
+	.capabilities	= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_NONREMOVABLE,
 	.gpio_cd	= -1,
 	.gpio_wp	= -1,
 #ifdef CONFIG_STE_DMA40
@@ -146,6 +147,7 @@ struct mmci_platform_data mop500_sdi2_data = {
 	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_8_BIT_DATA |
+				MMC_CAP_NONREMOVABLE |
 				MMC_CAP_MMC_HIGHSPEED |
 				MMC_CAP_ERASE |
 				MMC_CAP_CMD23,
@@ -186,6 +188,7 @@ struct mmci_platform_data mop500_sdi4_data = {
 	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_8_BIT_DATA |
+				MMC_CAP_NONREMOVABLE |
 				MMC_CAP_MMC_HIGHSPEED |
 				MMC_CAP_ERASE |
 				MMC_CAP_CMD23,
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 09:13:50 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:50 +0200
Subject: [PATCH 6/6] ARM: ux500: Enable support for UHS-I SD-cards
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369314830-3727-7-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

By setting the host capabilities MMC_CAP_UHS_SDR12|25 for
the SD card device we enable support for UHS cards. The
supported mode is SDR12 and SDR25.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 2e341fb..43be3e0 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -56,7 +56,9 @@ struct mmci_platform_data mop500_sdi0_data = {
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_SD_HIGHSPEED |
 				MMC_CAP_MMC_HIGHSPEED |
-				MMC_CAP_ERASE,
+				MMC_CAP_ERASE |
+				MMC_CAP_UHS_SDR12 |
+				MMC_CAP_UHS_SDR25,
 	.gpio_wp	= -1,
 	.sigdir		= MCI_ST_FBCLKEN |
 				MCI_ST_CMDDIREN |
-- 
1.7.10



From ulf.hansson at stericsson.com  Thu May 23 09:13:48 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Thu, 23 May 2013 15:13:48 +0200
Subject: [PATCH 4/6] ARM: ux500: Enable support for discard for MMC/SD
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1369314830-3727-5-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

By enabling MMC_CAP_ERASE for the SD/MMC devices the mmc block
layer will now act on DISCARD requests.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-sdi.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 9bb3ca5..3c07f55 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -55,7 +55,8 @@ struct mmci_platform_data mop500_sdi0_data = {
 	.f_max		= 100000000,
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_SD_HIGHSPEED |
-				MMC_CAP_MMC_HIGHSPEED,
+				MMC_CAP_MMC_HIGHSPEED |
+				MMC_CAP_ERASE,
 	.gpio_wp	= -1,
 	.sigdir		= MCI_ST_FBCLKEN |
 				MCI_ST_CMDDIREN |
@@ -146,6 +147,7 @@ struct mmci_platform_data mop500_sdi2_data = {
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_8_BIT_DATA |
 				MMC_CAP_MMC_HIGHSPEED |
+				MMC_CAP_ERASE |
 				MMC_CAP_CMD23,
 	.gpio_cd	= -1,
 	.gpio_wp	= -1,
@@ -185,6 +187,7 @@ struct mmci_platform_data mop500_sdi4_data = {
 	.capabilities	= MMC_CAP_4_BIT_DATA |
 				MMC_CAP_8_BIT_DATA |
 				MMC_CAP_MMC_HIGHSPEED |
+				MMC_CAP_ERASE |
 				MMC_CAP_CMD23,
 	.gpio_cd	= -1,
 	.gpio_wp	= -1,
-- 
1.7.10



From valentin.longchamp at keymile.com  Thu May 23 09:17:52 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Thu, 23 May 2013 15:17:52 +0200
Subject: [PATCH] ARM: kirkwood: refactor dtsi to largest common nodes
In-Reply-To: <20130523114025.GO31290@titan.lakedaemon.net>
References: <1369301130-29900-1-git-send-email-valentin.longchamp@keymile.com>
 <20130523114025.GO31290@titan.lakedaemon.net>
Message-ID: <519E1700.5040906@keymile.com>

Jason,

On 05/23/2013 01:40 PM, Jason Cooper wrote:
> Valentin,
> 
> On Thu, May 23, 2013 at 11:25:30AM +0200, Valentin Longchamp wrote:
>> Some kirkwood variants (for instance present in the prestera SoCs) do
>> not have all the peripherals whose nodes are initialized in the
>> kirkwood.dtsi. These missing peripherals are SATA, SDIO, and RTC.
> 
> Could you provide a little more detail here about the exact problem this
> is solving?

Sure, I will add more detail.

> 
>> Their corresponding nodes are moved from kirkwood.dtsi to the
>> kirkwood-628x.dtsi files so that they still are initialized for these
>> variants.
>>
>> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
>> ---
>>  arch/arm/boot/dts/kirkwood-6281.dtsi | 24 ++++++++++++++++++++++++
>>  arch/arm/boot/dts/kirkwood-6282.dtsi | 24 ++++++++++++++++++++++++
>>  arch/arm/boot/dts/kirkwood.dtsi      | 24 ------------------------
>>  3 files changed, 48 insertions(+), 24 deletions(-)
> 
> What about kirkwood-nsa310.dts?
> 

Argh, this one slipped through my net when I checked that all .dts except
km_kirkwood somehow include 628[x].dtsi.

I guess it would be OK to just include kirkwood-6281.dtsi in kirkwood-nsa310.dts
as well. Does someone have access to the HW to actually test it ?

Valentin


From prakash.pm at ti.com  Thu May 23 09:25:57 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Thu, 23 May 2013 13:25:57 +0000
Subject: [PATCH 1/4] ARM: davinci: uart: move to dev_id based clk_get
In-Reply-To: <517A2661.3000605@ti.com>
References: <1365510481-32129-1-git-send-email-prakash.pm@ti.com>
 <1365510664-1394-2-git-send-email-prakash.pm@ti.com>
 <517A2661.3000605@ti.com>
Message-ID: <A73F36158E33644199EB82C5EC81C7BC3EA6726A@DBDE04.ent.ti.com>

Hi Sekhar,

Thanks for reviewing.

On Fri, Apr 26, 2013 at 12:31:53, Nori, Sekhar wrote:
> Hi Prakash,
> 
> On 4/9/2013 6:01 PM, Manjunathappa, Prakash wrote:
> > For modules having single clock, clk_get should be done with dev_id.
> > But current davinci implementation handles multiple instances
> > of the UART devices with single platform_device_register. Hence clk_get
> > is based on con_id rather than dev_id, this is not correct. Do
> > platform_device_register for each instance and clk_get on dev_id.
> > 
> > Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
> > ---
> >  arch/arm/mach-davinci/da830.c                  |    8 ++--
> >  arch/arm/mach-davinci/da850.c                  |    8 ++--
> >  arch/arm/mach-davinci/devices-da8xx.c          |   40 ++++++++++++++++---
> >  arch/arm/mach-davinci/devices-tnetv107x.c      |   35 ++++++++++++++---
> >  arch/arm/mach-davinci/dm355.c                  |   48 ++++++++++++++++++-----
> >  arch/arm/mach-davinci/dm365.c                  |   35 ++++++++++++----
> >  arch/arm/mach-davinci/dm644x.c                 |   48 ++++++++++++++++++-----
> >  arch/arm/mach-davinci/dm646x.c                 |   49 +++++++++++++++++++-----
> >  arch/arm/mach-davinci/include/mach/da8xx.h     |    2 +-
> >  arch/arm/mach-davinci/include/mach/tnetv107x.h |    2 +-
> >  arch/arm/mach-davinci/serial.c                 |   19 ++++++---
> >  arch/arm/mach-davinci/tnetv107x.c              |    8 ++--
> >  12 files changed, 230 insertions(+), 72 deletions(-)
> 
> [...]
> 
> > diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
> > index fc50243..eec7132 100644
> > --- a/arch/arm/mach-davinci/devices-da8xx.c
> > +++ b/arch/arm/mach-davinci/devices-da8xx.c
> > @@ -67,7 +67,7 @@
> >  void __iomem *da8xx_syscfg0_base;
> >  void __iomem *da8xx_syscfg1_base;
> >  
> > -static struct plat_serial8250_port da8xx_serial_pdata[] = {
> > +static struct plat_serial8250_port da8xx_serial_pdata0[] = {
> 
> da8xx_serial0_pdata is more appropriate. Likewise for other entries below.
> 

True, will change them.

> >  	{
> >  		.mapbase	= DA8XX_UART0_BASE,
> >  		.irq		= IRQ_DA8XX_UARTINT0,
> > @@ -77,6 +77,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
> >  		.regshift	= 2,
> >  	},
> >  	{
> > +		.flags	= 0,
> > +	},
> 
> No need of trailing ',' on sentinel. No need of the zero initialization.
> Here and other places below.
> 

Ok. I will remove them.

> > +};
> > +static struct plat_serial8250_port da8xx_serial_pdata1[] = {
> > +	{
> >  		.mapbase	= DA8XX_UART1_BASE,
> >  		.irq		= IRQ_DA8XX_UARTINT1,
> >  		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
> > @@ -85,6 +90,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
> >  		.regshift	= 2,
> >  	},
> >  	{
> > +		.flags	= 0,
> > +	},
> > +};
> > +static struct plat_serial8250_port da8xx_serial_pdata2[] = {
> > +	{
> >  		.mapbase	= DA8XX_UART2_BASE,
> >  		.irq		= IRQ_DA8XX_UARTINT2,
> >  		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
> > @@ -97,11 +107,29 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
> >  	},
> >  };
> >  
> > -struct platform_device da8xx_serial_device = {
> > -	.name	= "serial8250",
> > -	.id	= PLAT8250_DEV_PLATFORM,
> > -	.dev	= {
> > -		.platform_data	= da8xx_serial_pdata,
> > +struct platform_device da8xx_serial_device[] = {
> > +	{
> > +		.name	= "serial8250",
> > +		.id	= PLAT8250_DEV_PLATFORM,
> > +		.dev	= {
> > +			.platform_data	= da8xx_serial_pdata0,
> > +		},
> > +	},
> > +	{
> > +		.name	= "serial8250",
> > +		.id	= PLAT8250_DEV_PLATFORM1,
> > +		.dev	= {
> > +			.platform_data	= da8xx_serial_pdata1,
> > +		},
> > +	},
> > +	{
> > +		.name	= "serial8250",
> > +		.id	= PLAT8250_DEV_PLATFORM2,
> > +		.dev	= {
> > +			.platform_data	= da8xx_serial_pdata2,
> > +		},
> > +	},
> > +	{
> >  	},
> >  };
> 
> [...]
> 
> > diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
> > index f262581..57e6150 100644
> > --- a/arch/arm/mach-davinci/serial.c
> > +++ b/arch/arm/mach-davinci/serial.c
> > @@ -76,7 +76,7 @@ int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
> >  	char name[16];
> >  	struct clk *clk;
> >  	struct davinci_soc_info *soc_info = &davinci_soc_info;
> > -	struct device *dev = &soc_info->serial_dev->dev;
> > +	struct device *dev = &soc_info->serial_dev[instance].dev;
> >  
> >  	sprintf(name, "uart%d", instance);
> >  	clk = clk_get(dev, name);
> 
> Why not pass con_id = NULL now?
> 

Correct, I will change it.

> > @@ -96,19 +96,25 @@ int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
> >  
> >  int __init davinci_serial_init(struct davinci_uart_config *info)
> >  {
> > -	int i, ret;
> > +	int i, ret = 0;
> >  	struct davinci_soc_info *soc_info = &davinci_soc_info;
> > -	struct device *dev = &soc_info->serial_dev->dev;
> > -	struct plat_serial8250_port *p = dev->platform_data;
> > +	struct device *dev;
> > +	struct plat_serial8250_port *p;
> >  
> >  	/*
> >  	 * Make sure the serial ports are muxed on at this point.
> >  	 * You have to mux them off in device drivers later on if not needed.
> >  	 */
> > -	for (i = 0; p->flags; i++, p++) {
> > +	for (i = 0; soc_info->serial_dev[i].dev.platform_data != NULL; i++) {
> > +		dev = &soc_info->serial_dev[i].dev;
> > +		p = dev->platform_data;
> >  		if (!(info->enabled_uarts & (1 << i)))
> >  			continue;
> >  
> > +		ret = platform_device_register(&soc_info->serial_dev[i]);
> > +		if (ret)
> > +			continue;
> > +
> >  		ret = davinci_serial_setup_clk(i, &p->uartclk);
> >  		if (ret)
> >  			continue;
> > @@ -125,6 +131,5 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
> >  		if (p->membase && p->type != PORT_AR7)
> >  			davinci_serial_reset(p);
> >  	}
> > -
> > -	return platform_device_register(soc_info->serial_dev);
> > +	return ret;
> >  }
> 
> Now that we are overhauling this part of code, some improvements can be
> done. First, get rid of struct davinci_uart_config. None of the board
> files use it meaningfully and we know we are not going to have more
> board files. Second, make davinci_serial_init() take pointer to serial
> platform device directly. This eliminates need for serial_dev in the
> soc_info structure (yay!). You might also find that
> davinci_serial_setup_clk() can be eliminated as well since there is not
> much to do there now.
> 

Ok I will cleanup this and submit v2.

Thanks,
Prakash

From arnd at arndb.de  Thu May 23 09:26:48 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 15:26:48 +0200
Subject: [RFC PATCH 2/3] USB: OHCI: Generic changes to make ohci-pci a
 separate driver
In-Reply-To: <1369307506-4458-3-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369307506-4458-1-git-send-email-manjunath.goudar@linaro.org>
 <1369307506-4458-3-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <201305231526.48811.arnd@arndb.de>

On Thursday 23 May 2013, Manjunath Goudar wrote:
> @@ -1275,7 +1266,7 @@ MODULE_LICENSE ("GPL");
>  #define PLATFORM_DRIVER                ohci_platform_driver
>  #endif
>  
> -#if    !defined(PCI_DRIVER) &&         \
> +#if    !defined(PCI_DRIVER) && \
>         !defined(PLATFORM_DRIVER) &&    \
>         !defined(OMAP1_PLATFORM_DRIVER) &&      \
>         !defined(OMAP3_PLATFORM_DRIVER) &&      \

This part didn't really belong here, otherwise the patch looks right to me.

	Arnd


From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:51 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:51 +0200
Subject: [PATCH v2 3/6] arm: mvebu: move cache and mvebu-mbus initialization
 later
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369315854-32724-4-git-send-email-thomas.petazzoni@free-electrons.com>

Current, the L2 cache and the mvebu-mbus drivers are initialized at
->init_early() time. However, at ->init_early() time, ioremap() only
works if a static I/O mapping has already been put in place. If it's
not the case, it tries to do a memory allocation with kmalloc() which
is not possible so early at this stage of the initialization.

Since we want to get rid of the static I/O mapping, we cannot
initialize the L2 cache driver and the mvebu-mbus driver so early. So,
we move their initialization to the ->init_time() level, which is
slightly later (so ioremap() works properly), but sufficiently early
to be before the call of the ->smp_prepare_cpus() hook, which creates
an address decoding window for the BootROM, which requires the
mvebu-mbus driver to be properly initialized.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |    8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index b9319c4..75ebf56 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -44,14 +44,11 @@ static void __init armada_370_xp_map_io(void)
 
 static void __init armada_370_xp_timer_and_clk_init(void)
 {
+	char *mbus_soc_name;
+
 	mvebu_clocks_init();
 	armada_370_xp_timer_init();
 	coherency_init();
-}
-
-static void __init armada_370_xp_init_early(void)
-{
-	char *mbus_soc_name;
 
 	/*
 	 * This initialization will be replaced by a DT-based
@@ -87,7 +84,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
 	.smp		= smp_ops(armada_xp_smp_ops),
 	.init_machine	= armada_370_xp_dt_init,
 	.map_io		= armada_370_xp_map_io,
-	.init_early	= armada_370_xp_init_early,
 	.init_time	= armada_370_xp_timer_and_clk_init,
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_370_xp_dt_compat,
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:52 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:52 +0200
Subject: [PATCH v2 4/6] arm: mvebu: remove hardcoded static I/O mapping
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369315854-32724-5-git-send-email-thomas.petazzoni@free-electrons.com>

Now that we have removed the need of the static I/O mapping for early
initialization reasons, and fixed the registers area length that were
broken, we can get rid of the static I/O mapping. Only the earlyprintk
mapping needs to be set up, using the debug_ll_io_init() helper
function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |   11 +----------
 arch/arm/mach-mvebu/armada-370-xp.h |    2 --
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 75ebf56..c1c0556 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -28,18 +28,9 @@
 #include "common.h"
 #include "coherency.h"
 
-static struct map_desc armada_370_xp_io_desc[] __initdata = {
-	{
-		.virtual	= (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
-		.pfn		= __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
-		.length		= ARMADA_370_XP_REGS_SIZE,
-		.type		= MT_DEVICE,
-	},
-};
-
 static void __init armada_370_xp_map_io(void)
 {
-	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+	debug_ll_io_init();
 }
 
 static void __init armada_370_xp_timer_and_clk_init(void)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 2070e1b..585e147 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,8 +16,6 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE	IOMEM(0xfec00000)
-#define ARMADA_370_XP_REGS_SIZE		SZ_1M
 
 /* These defines can go away once mvebu-mbus has a DT binding */
 #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:50 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:50 +0200
Subject: [PATCH v2 2/6] arm: mvebu: avoid hardcoded virtual address in
 coherency code
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369315854-32724-3-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the coherency_get_cpu_count() function no longer requires a
very early mapping of the coherency unit registers, we can avoid the
hardcoded virtual address in coherency.c. However, the coherency
features are still used quite early, so we need to do the of_iomap()
early enough, at the ->init_timer() level, so we have the call of
coherency_init() at this point.

Unfortunately, at ->init_timer() time, it is not possible to register
a bus notifier, so we add a separate coherency_late_init() function
that gets called as as postcore_initcall(), when bus notifiers are
available.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/armada-370-xp.c |    2 +-
 arch/arm/mach-mvebu/coherency.c     |   20 ++++++++++----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index cf8e357..b9319c4 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -46,6 +46,7 @@ static void __init armada_370_xp_timer_and_clk_init(void)
 {
 	mvebu_clocks_init();
 	armada_370_xp_timer_init();
+	coherency_init();
 }
 
 static void __init armada_370_xp_init_early(void)
@@ -75,7 +76,6 @@ static void __init armada_370_xp_init_early(void)
 static void __init armada_370_xp_dt_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-	coherency_init();
 }
 
 static const char * const armada_370_xp_dt_compat[] = {
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 46d66c0..d74794a 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -27,14 +27,7 @@
 #include <asm/smp_plat.h>
 #include "armada-370-xp.h"
 
-/*
- * Some functions in this file are called very early during SMP
- * initialization. At that time the device tree framework is not yet
- * ready, and it is not possible to get the register address to
- * ioremap it. That's why the pointer below is given with an initial
- * value matching its virtual mapping
- */
-static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
+static void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 
 /* Coherency fabric registers */
@@ -135,9 +128,16 @@ int __init coherency_init(void)
 		coherency_base = of_iomap(np, 0);
 		coherency_cpu_base = of_iomap(np, 1);
 		set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-		bus_register_notifier(&platform_bus_type,
-					&mvebu_hwcc_platform_nb);
 	}
 
 	return 0;
 }
+
+static int __init coherency_late_init(void)
+{
+	bus_register_notifier(&platform_bus_type,
+			      &mvebu_hwcc_platform_nb);
+	return 0;
+}
+
+postcore_initcall(coherency_late_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:49 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:49 +0200
Subject: [PATCH v2 1/6] arm: mvebu: remove dependency of SMP init on static
 I/O mapping
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369315854-32724-2-git-send-email-thomas.petazzoni@free-electrons.com>

The ->smp_init_cpus() function is called very early during boot, at a
point where dynamic I/O mappings are not yet possible. However, in the
Armada 370/XP implementation of this function, we have to get the
number of CPUs. We used to do that by accessing a hardware register,
which requires relying on a static I/O mapping set up by
->map_io(). Not only this requires hardcoding a virtual address, but
it also prevents us from removing the static I/O mapping.

So this commit changes the way used to get the number of CPUs: we now
use the Device Tree, which is a representation of the hardware, and
provides us the number of available CPUs. This is also more accurate,
because it potentially allows to boot the Linux kernel on only a
number of CPUs given by the Device Tree, instead of unconditionally on
all CPUs.

As a consequence, the coherency_get_cpu_count() function becomes no
longer used, so we remove it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/coherency.c |   12 ------------
 arch/arm/mach-mvebu/coherency.h |    4 ----
 arch/arm/mach-mvebu/common.h    |    2 ++
 arch/arm/mach-mvebu/platsmp.c   |   10 +++++++++-
 4 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 8278960..46d66c0 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -47,18 +47,6 @@ static struct of_device_id of_coherency_table[] = {
 	{ /* end of list */ },
 };
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void)
-{
-	int reg, cnt;
-
-	reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
-	cnt = (reg & 0xF) + 1;
-
-	return cnt;
-}
-#endif
-
 /* Function defined in coherency_ll.S */
 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
 
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 2f42813..df33ad8 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,10 +14,6 @@
 #ifndef __MACH_370_XP_COHERENCY_H
 #define __MACH_370_XP_COHERENCY_H
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void);
-#endif
-
 int set_cpu_coherent(int cpu_id, int smp_group_id);
 int coherency_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2..98defd5 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,6 +15,8 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
+#define ARMADA_XP_MAX_CPUS 4
+
 void mvebu_restart(char mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 875ea74..93f2f3a 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
 
 static void __init armada_xp_smp_init_cpus(void)
 {
+	struct device_node *np;
 	unsigned int i, ncores;
-	ncores = coherency_get_cpu_count();
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np)
+		panic("No 'cpus' node found\n");
+
+	ncores = of_get_child_count(np);
+	if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
+		panic("Invalid number of CPUs in DT\n");
 
 	/* Limit possible CPUs to defconfig */
 	if (ncores > nr_cpu_ids) {
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:48 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:48 +0200
Subject: [PATCH v2 0/6] Support new Marvell bootloaders for Armada 370/XP
Message-ID: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

This is the second version of this patch series, that switches Armada
370/XP to use internal registers mapped at 0xf1000000, in order to
comply with the new bootloaders shipped by Marvell. It also implements
a temporary solution to allow users of platforms having an old
bootloader to continue to boot properly. See the detailed explanation
below.

Changes since v1
================

 * The patch series is now based on jcooper/mvebu/fixes +
   jcooper/mvebu/cleanup. As a result, I've dropped the first three
   patches of this series, that have been merged by Jason Cooper
   already.

 * This I'm based on mvebu/fixes + mvebu/cleanup, I had to fix a
   conflict in "arm: mvebu: move cache and mvebu-mbus initialization
   later" since that conflicted with the removal of the coherent DMA
   workaround.

 * Improved/fixed two comments in armada-370-xp.c related to the
   register switch. Noticed and suggested by Andrew Lunn.

 * Fixed the virtual address used to remap the internal registers at
   the new address. It needs to be 2 MB aligned, like the one for the
   internal registers at the old address, in order to be compatible
   with what the assembly code in arch/arm/kernel/head.S is doing to
   set up an early virtual->physical mapping. (2 MB because sections
   with LPAE are 2 MB wide, and we support LPAE).

In detail, the patch series has
===============================

 * Patch 1 and 2 slightly rework the way the SMP initialization and
   the coherency unit initialization is done, in order to avoid the
   hardcoded virtual address in the coherency.c file.

   To be applied to mvebu/soc

 * Patch 3 moves the L2 cache and mvebu-mbus initialization a bit
   later (i.e from ->init_early() to ->init_time()) so that they can
   ioremap() their registers without crashing once we remove the
   static I/O mapping (next patch).

 * Patch 4 removes the static I/O mapping that was set up at
   ->map_io() time to cover the entire "internal registers" area.

   To be applied to mvebu/soc

 * Patch 5 removes the hardcoded physical address in the SMP
   initialization code.

   To be applied to mvebu/soc

 * Patch 6 implements the internal register address change itself. The
   DTS changes are included in the same patch as the code changes. It
   is possible to split them in two patches, but applying just one
   patch and not the other would lead to a kernel that doesn't boot at
   all.

   To be applied to mvebu/soc (even though there are admittedly some
   DT changes in here).

Additional details
==================

The aim of this patch series is to move the internal registers space
of the Armada 370 and Armada XP support to 0xf1000000 instead of
0xd0000000, and prepare for the support of the new versions of U-Boot
installed by Marvell on Armada 370 and XP platforms that boot the
kernel with the internal registers space already mapped at 0xf1000000.

Before reading the patches, and especially the last one, please read
on for a description of the problem and the proposed solution. The
solution has been carefully thought of, and all the details explained
below are important to understand how the proposed solution was
designed.

On Marvell EBU SoCs, including earlier families such as Kirkwood or
Dove, all the peripheral registers belong to a memory window of 1 MB,
called the "internal registers window". This window of physical memory
can be freely moved to an arbitrary physical address. At reset, this
memory window is at 0xD0000000, but it can be changed by software to
another address if needed.

The *very* important thing to remember is that the mechanism to get or
change the base address of this "internal registers" window is a
register, which is itself part of this "internal registers"
window. The bottom line is that when you run code on a Marvell SoC,
you have to *know* where the internal registers are located, because
you can't guess dynamically by reading some hardware register. Again,
this is a *very* important characteristic, because it explains many of
the choices of the proposed solution below.

Historically, the bootloaders for Dove and Kirkwood have always
remapped the internal registers window at 0xF1000000, so for those
platforms, the Linux kernel has always made the assumption that
internal registers are accessible at 0xF1000000.

Unfortunately, for Armada 370 and Armada XP, the current generation of
bootloaders that are being shipped on Marvell evaluation boards, but
also on products like the Plathome OpenBlocks AX3 or the Globalscale
Mirabox do not do the remapping, and are leaving the internal
registers at 0xD0000000.

However, this is causing some problems:

 1 The internal registers window sits at 3 GB, in the middle of the
   0-4 GB area of physical memory, which is quite annoying when you
   have more than 3 GB of memory. Having them at 0xF1000000 means that
   you lose less RAM when you have more than 3 GB of physical memory
   installed. And since Armada XP is LPAE capable, you can even have
   more than 4 GB memory: we already have boards with 8 GB of memory
   installed.

 2 This is different from Kirkwood and Dove, which makes sharing some
   early code like earlyprintk complicated, while our goal is
   ultimately to merge all Marvell EBU platforms into mach-mvebu.

(1) is really the primary motivation here, (2) is only a nice
side-effect.

So, the new generation of bootloaders that are shipped on new Marvell
Armada 370/XP platforms are doing the remapping at 0xF1000000 prior to
starting Linux. The current kernel cannot boot on such platforms.

One solution is to move the kernel to use 0xF1000000, and assume the
bootloader has already done the remapping. This can be one option, but
it means that newer kernels would no longer boot on platforms that use
an old bootloader. All existing users of Globalscale Mirabox or
Plathome OpenBlocks AX3, next time they upgrade their kernel, would
have a kernel that simply doesn't boot (and without showing *any*
message, because even the address of the UART has changed).

If the only Armada 370/XP platforms in use today had been evaluation
boards that are available only to a selected number of people,
dropping the compatibility would probably have been
acceptable. However, with a large number of Mirabox and OpenBlocks AX3
devices being already shipped, we believe that breaking the
compatibility is not an option.

Therefore, the last patch of this series adds some early code in the
kernel, at the ->map_io() stage, to switch the internal registers from
0xD0000000 to 0xF1000000 if this has not been done already by the
bootloader. As it was explained above, we unfortunately can't read the
current base address of the internal register window, so we need a
different mechanism to know if the bootloader has done the remapping
at 0xF1000000 (new generation bootloader) or has left the internal
registers at 0xD0000000 (old generation bootloader). In order to
distinguish between those two cases, a CP15 bit is being used. Old
bootloaders do not touch this CP15, so it is set to 0. New bootloaders
set this CP15 bit to 1, so that the kernel knows that the remapping
has already been done. The ->map_io() code looks at this bit to know
if the remapping should be done or not.

Unfortunately, tweaking ->map_io() is not sufficient: we also want
earlyprintk to work. And earlyprintk is used *before* ->map_io() is
called, and *after* ->map_io() is called. So in the earlyprintk code,
we also need to do a little bit of magic to know if we're booted on an
old or new bootloader, and if the remapping has occured or not in the
case of an old bootloader. Since the CP15 bit that we use gets cleared
the first time the 'wfi' instruction is cleared, we use this bit only
in the early kernel boot. As soon as ->map_io() as done its job, it
sets a global variable that tells the earlyprintk code that the
registers are now at 0xF1000000.

I hope this long explanation gives enough context to understand the
problem and the proposed solution. Do not hesitate to ask for more
details if needed.

Notice that the solution would be much simpler if we could do this
remapping earlier in the kernel initialization. Unfortunately,
->map_io() is really the first piece of code that is being called into
SoC-specific code, so it's the only way of doing this without making
changes in generic places in the kernel.

This code has been tested with both an old bootloader and a new
bootloader, on the Armada XP GP platform.

Best regards,

Thomas

Thomas Petazzoni (6):
  arm: mvebu: remove dependency of SMP init on static I/O mapping
  arm: mvebu: avoid hardcoded virtual address in coherency code
  arm: mvebu: move cache and mvebu-mbus initialization later
  arm: mvebu: remove hardcoded static I/O mapping
  arm: mvebu: don't hardcode a physical address in headsmp.S
  arm: mvebu: support new bootloaders shipped by Marvell

 arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
 arch/arm/boot/dts/armada-370.dtsi    |    3 +-
 arch/arm/boot/dts/armada-xp-gp.dts   |    2 +-
 arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++--
 arch/arm/mach-mvebu/armada-370-xp.c  |  124 +++++++++++++++++++++++++++++-----
 arch/arm/mach-mvebu/armada-370-xp.h  |    4 +-
 arch/arm/mach-mvebu/coherency.c      |   36 ++++------
 arch/arm/mach-mvebu/coherency.h      |    4 --
 arch/arm/mach-mvebu/common.h         |    2 +
 arch/arm/mach-mvebu/headsmp.S        |   20 +++---
 arch/arm/mach-mvebu/platsmp.c        |   10 ++-
 11 files changed, 220 insertions(+), 64 deletions(-)

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:53 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:53 +0200
Subject: [PATCH v2 5/6] arm: mvebu: don't hardcode a physical address in
 headsmp.S
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369315854-32724-6-git-send-email-thomas.petazzoni@free-electrons.com>

Now that the coherency_init() function is called a bit earlier, we can
actually read the physical address of the coherency unit registers
from the Device Tree, and communicate that to the headsmp.S code,
which avoids hardcoding a physical address.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/coherency.c |    4 ++++
 arch/arm/mach-mvebu/headsmp.S   |   20 +++++++++++---------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index d74794a..3d8f40f 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -27,6 +27,7 @@
 #include <asm/smp_plat.h>
 #include "armada-370-xp.h"
 
+unsigned long __cpuinitdata coherency_phys_base;
 static void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 
@@ -124,7 +125,10 @@ int __init coherency_init(void)
 
 	np = of_find_matching_node(NULL, of_coherency_table);
 	if (np) {
+		struct resource res;
 		pr_info("Initializing Coherency fabric\n");
+		of_address_to_resource(np, 0, &res);
+		coherency_phys_base = res.start;
 		coherency_base = of_iomap(np, 0);
 		coherency_cpu_base = of_iomap(np, 1);
 		set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ed..095b590 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -21,12 +21,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-/*
- * At this stage the secondary CPUs don't have acces yet to the MMU, so
- * we have to provide physical addresses
- */
-#define ARMADA_XP_CFB_BASE	     0xD0020200
-
 	__CPUINIT
 
 /*
@@ -35,15 +29,23 @@
  * startup
  */
 ENTRY(armada_xp_secondary_startup)
+	/* Add CPU to coherency fabric */
+	adr	r0, 1f
+	ldmia	r0, {r1, r2}
+	sub	r0, r0, r1
+	add	r2, r2, r0
+	ldr	r0, [r2]
 
 	/* Read CPU id */
 	mrc     p15, 0, r1, c0, c0, 5
 	and     r1, r1, #0xF
 
-	/* Add CPU to coherency fabric */
-	ldr     r0, =ARMADA_XP_CFB_BASE
-
 	bl	ll_set_cpu_coherent
 	b	secondary_startup
 
 ENDPROC(armada_xp_secondary_startup)
+
+	.align 2
+1:
+	.long	.
+	.long	coherency_phys_base
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 09:30:54 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 15:30:54 +0200
Subject: [PATCH v2 6/6] arm: mvebu: support new bootloaders shipped by Marvell
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369315854-32724-7-git-send-email-thomas.petazzoni@free-electrons.com>

On Marvell platforms, the "internal registers" is a window of 1 MB of
the physical address space that contains all the registers for the
various peripherals of the SoC (timers, interrupt controllers, GPIO
controllers, Ethernet, etc.). The base address of this 1 MB window is
configurable, and this base address is configured using a register
that is itself part of this window.

All earlier families of Marvell EBU SoCs supported by Linux used
0xf1000000 as the base address of the internal registers window. For
some reason, early versions of the Marvell 370/XP platforms used
0xd0000000 as the base address. This base address is set up by the
bootloader. However, in order to keep as much physical address space
to address RAM below the 4 GB limit, Marvell had to switch the base
address of the internal registers window back to 0xf1000000.

All the new bootloaders shipped by Marvell remap those registers to
0xf1000000. This commit adapts the kernel Device Tree and other
definitions so that it can boot with such bootloaders.

However, since those changing are breaking the compatibility with old
bootloader (resulting in a kernel that crashes without displaying any
message), we have implement a temporary solution for users of an old
bootloader.

One particular bit of a CP15 register has been chosen to indicate
whether we use an old bootloader (setting the address at 0xd0000000)
or a new bootloader (setting the address at 0xf1000000). In the
->map_io() function, when the bit is already set, there is nothing to
do, we are already using a new bootloader and internal registers are
at 0xf1000000.

However, when the bit is not set, we do a static mapping of the
register area that allows to change the internal register address, we
change this address, and set this bit.

Note that this mechanism also needs cooperation from the earlyprintk
addruart handler (in arch/arm/include/debug/mvebu.S). This is where
things get complex: the CP15 bit that has been chosen gets reset to
zero at the first call to the 'wfi' instruction. So it cannot be used
during the entire life of the system. Instead, whenever the ->map_io()
function has switched to the internal register space to the new
address, it sets a global variable 'mvebu_switched_regs', which the
earlyprintk reads. If it's true, then the move has already been done
and there is no need to read the CP15 register. If
'mvebu_switched_regs' is false, we are before the register move, so we
need to read the CP15 bit to find out whether we're being booted from
an old bootloader (which mapped the register space at 0xd0000000) or a
new bootloader (which mapped the register space at 0xf1000000).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
 arch/arm/boot/dts/armada-370.dtsi    |    3 +-
 arch/arm/boot/dts/armada-xp-gp.dts   |    2 +-
 arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++++++--
 arch/arm/mach-mvebu/armada-370-xp.c  |  105 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/armada-370-xp.h  |    2 +-
 6 files changed, 181 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 52a1f5e..95ec049 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -33,7 +33,7 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&mpic>;
-		ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
+		ranges = <0          0 0xf1000000 0x0100000 /* internal registers */
 			  0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
 
 		internal-regs {
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index aee2b18..030e425 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -29,8 +29,9 @@
 	};
 
 	soc {
-		ranges = <0          0xd0000000 0x0100000 /* internal registers */
+		ranges = <0          0xf1000000 0x0100000 /* internal registers */
 			  0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+
 		internal-regs {
 			system-controller at 18200 {
 				compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 3ee63d1..8fb1679 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,7 +39,7 @@
 	};
 
 	soc {
-		ranges = <0          0 0xd0000000 0x100000
+		ranges = <0          0 0xf1000000 0x100000
 			  0xf0000000 0 0xf0000000 0x1000000>;
 
 		internal-regs {
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191af..ec875c4 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -5,20 +5,85 @@
  *
  * Lior Amsalem <alior at marvell.com>
  * Gregory Clement <gregory.clement at free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000
+#define ARMADA_370_XP_UART_PHYS_BASE_OLD	0xd0012000
+#define ARMADA_370_XP_UART_PHYS_BASE_NEW	0xf1012000
+#define ARMADA_370_XP_UART_VIRT_BASE_OLD	0xfec12000
+#define ARMADA_370_XP_UART_VIRT_BASE_NEW	0xfea12000
 
 	.macro	addruart, rp, rv, tmp
-	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
-	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
-	orr	\rp, \rp, #0x00012000
-	orr	\rv, \rv, #0x00012000
+
+#ifndef ZIMAGE
+	/*
+	 * This loads the value of mvebu_switched_regs. We need a
+	 * little bit of gymnastic here to handle the fact that the
+	 * addruart code is duplicated in different places, and called
+	 * sometimes with the MMU disabled, sometimes the MMU enabled.
+	 *
+	 * Notice that when this earlyprintk code is linked into the
+	 * kernel decompressor (i.e ZIMAGE is defined), this code isn't
+	 * compiled. The reason is because the global mvebu_switched_regs
+	 * variable is not available in the decompressor code. At this
+	 * early stage, we simply test the CP15 bit (below) to know where
+	 * the internal registers are.
+	 */
+	adr	\rp, addruart_switched_regs_\@
+	ldr	\rv, [\rp]
+	sub	\rv, \rv, \rp
+	ldr	\rp, [\rp, #4]
+	sub	\tmp, \rp, \rv
+	ldr	\rp, [\tmp, #0]
+	cmp	\rp, #0
+
+	/* If we have already switched, then use the new register
+	   address */
+	bne	addruart_new_\@
+#endif
+
+	/*
+	 * We haven't switched the register location, so test the CP15
+	 * register bit to find whether we are:
+	 * - with an old bootloader setting the base address to
+	 *   0xd0000000
+	 * - with a new bootloader that has already set the
+	 *   base address to 0xf1000000
+	 * We adapt the physical address returned depending on the
+	 * value of this bit, but also the virtual address, because we
+	 * can't remap the old physical address and the new physical
+	 * address at the same location.
+	 */
+	mrc	p15, 0, \tmp, c5, c0, 0
+	and	\tmp, \tmp, #(1 << 11)
+	cmp	\tmp, #0
+	bne	addruart_new_\@
+
+addruart_old_\@:
+	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_OLD
+	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_OLD
+	b	addruart_out_\@
+addruart_new_\@:
+	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_NEW
+	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_NEW
+	b	addruart_out_\@
+
+#ifndef ZIMAGE
+	/*
+	 * Global variable mvebu_switched_regs not visible in the
+	 * decompressor code
+	 */
+	.align
+addruart_switched_regs_\@:
+	.long	.
+	.long	mvebu_switched_regs
+#endif
+
+addruart_out_\@:
 	.endm
 
 #define UART_SHIFT	2
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index c1c0556..752eedd 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -28,8 +28,113 @@
 #include "common.h"
 #include "coherency.h"
 
+/*
+ * Note on the internal register address.
+ *
+ * On Marvell platforms, the "internal registers" is a window of 1 MB
+ * of the physical address space that contains all the registers for
+ * the various peripherals of the SoC (timers, interrupt controllers,
+ * GPIO controllers, Ethernet, etc.). The base address of this 1 MB
+ * window is configurable, and this base address is configured using a
+ * register that is itself part of this window.
+ *
+ * All earlier families of Marvell EBU SoCs supported by Linux used
+ * 0xf1000000 as the base address of the internal registers
+ * window. For some reason, early versions of the Marvell 370/XP
+ * platforms used 0xd0000000 as the base address. This base address is
+ * set up by the bootloader. However, in order to keep as much
+ * physical address space to address RAM below the 4 GB limit, we had
+ * to switch the base address of the internal registers window back to
+ * 0xf1000000, and we wanted to achieve that without breaking existing
+ * platforms, where the bootloader was initially setting the base
+ * address to 0xd0000000. So the kernel is responsible for switching
+ * to 0xf1000000 when needed.
+ *
+ * One particular bit of a CP15 register has been chosen to indicate
+ * whether we use an old bootloader (setting the address at
+ * 0xd0000000) or a new bootloader (setting the address at
+ * 0xf1000000). In the ->map_io() function, when the bit is already
+ * set, there is nothing to do, we are already using a new bootloader
+ * and internal registers are at 0xf1000000.
+ *
+ * However, when the bit is not set, we do a static mapping of the
+ * register area that allows to change the internal register address
+ * and we change this address.
+ *
+ * Once those steps are done, we set a global variable,
+ * mvebu_switched_regs, that tells the earlyprintk code how to
+ * behave. Note that this mechanism also needs cooperation from the
+ * earlyprintk addruart handler (in arch/arm/include/debug/mvebu.S).
+ */
+
+#define NEW_INTERNAL_REGS_ADDR  0xf1000000
+#define OLD_INTERNAL_REGS_ADDR  0xd0000000
+#define MBUS_OLD_PHYS_ADDR      (OLD_INTERNAL_REGS_ADDR + 0x20000)
+#define MBUS_OLD_VIRT_ADDR      0xfe9ff000
+#define  MBUS_INTERNAL_REGS_ADDR      0x80
+
+/*
+ * We really want this variable to be part of the .data section,
+ * because it gets accessed by the earlyprintk code before BSS gets
+ * initialized to zero. This variable indicates whether the switch to
+ * the new register has taken place or not. It is needed because the
+ * CP15 bit used by the bootloader to tell the kernel where the
+ * registers are mapped is cleared to 0 at the first 'wfi'
+ * instruction. So we can't use it for the entire life of the system,
+ * and we instead use this boolean to indicate to the earlyprintk code
+ * that the switch has occured and it doesn't need to look at the CP15
+ * bit anymore.
+ */
+unsigned int __section(.data) mvebu_switched_regs = 0;
+
+/*
+ * Detect if we're running an old bootloader that has set the physical
+ * base address of internal registers to 0xd0000000
+ */
+static int armada_370_xp_has_old_bootloader(void)
+{
+	u32 val;
+	asm volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(val));
+	return !(val & BIT(11));
+}
+
 static void __init armada_370_xp_map_io(void)
 {
+	if (armada_370_xp_has_old_bootloader()) {
+		struct map_desc desc;
+		void __iomem *mbus = IOMEM(MBUS_OLD_VIRT_ADDR);
+
+		desc.virtual = MBUS_OLD_VIRT_ADDR;
+		desc.pfn     = __phys_to_pfn(MBUS_OLD_PHYS_ADDR);
+		desc.length  = PAGE_SIZE;
+		desc.type    = MT_DEVICE;
+
+		/*
+		 * Map the area that contains the registers that
+		 * allows to change the base address of internal
+		 * registers.
+		 */
+		iotable_init(&desc, 1);
+
+		/*
+		 * Change the physical base address of the
+		 * registers. From now on, and until
+		 * debug_ll_io_init() is called below, it is not
+		 * possible to do any print, because using earlyprintk
+		 * would lead to memory writes to the old internal
+		 * registers, which would hang the CPU.
+		 */
+		writel(NEW_INTERNAL_REGS_ADDR, mbus + MBUS_INTERNAL_REGS_ADDR);
+	}
+
+	/*
+	 * Either the registers have been switched by the above code,
+	 * or the bootloader had already set the register space at the
+	 * right location. In both cases, tell the earlyprintk code it
+	 * can now use the new location.
+	 */
+	mvebu_switched_regs = 1;
+
 	debug_ll_io_init();
 }
 
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 585e147..ff9adc4 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -15,7 +15,7 @@
 #ifndef __MACH_ARMADA_370_XP_H
 #define __MACH_ARMADA_370_XP_H
 
-#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
+#define ARMADA_370_XP_REGS_PHYS_BASE	0xf1000000
 
 /* These defines can go away once mvebu-mbus has a DT binding */
 #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-- 
1.7.9.5



From jbe at pengutronix.de  Thu May 23 09:31:31 2013
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 23 May 2013 15:31:31 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <20130523130039.GF8595@lukather>
References: <519E03B0.1080006@digi.com> <20130523130039.GF8595@lukather>
Message-ID: <201305231531.31376.jbe@pengutronix.de>

Hi Maxime,

maxime.ripard at free-electrons.com wrote:
> On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> > I'm using an i.MX28 based board with lcd connected with 18bits data bus.
> > My platform uses 32 bits per pixel:
> >
> > 	mxsfb_pdata.default_bpp = 32;
> > 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
> >
> > With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
> > at HW_LCDIF_CTRL register in function mxsfb_set_par():
> >
> > 	case 32:
> > 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
> > 		ctrl |= CTRL_SET_WORD_LENGTH(3);
> > 		switch (host->ld_intf_width) {
> > 		case STMLCDIF_8BIT:
> > 			dev_dbg(&host->pdev->dev,
> > 					"Unsupported LCD bus width mapping\n");
> > 			return -EINVAL;
> > 		case STMLCDIF_16BIT:
> > 		case STMLCDIF_18BIT:
> > 			/* 24 bit to 18 bit mapping */
> > 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> > 					    *  each colour component
> > 					    */
> > 			break;
> > 		case STMLCDIF_24BIT:
> > 			/* real 24 bit */
> > 			break;
> > 		}
> >
> > According to the manual, this flag does:
> > 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
> > format, such that all RGB 888 data is contained in 24 bits.
> > 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
> > actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
> > 2 bits in each byte do not contain any useful data, and should be
> > dropped.
> >
> > The setting of this flag is producing bad colours with true colour
> > images (i.e. the Linux penguin is displayed ok, but QT applications
> > or images displayed with fbv are not).
> > I believe the setting of this flag is not correct (after all, if my
> > bpp is 32, then all 24bit colours are useful and dropping the upper
> > 2 bits is a bad idea).
> > If I don't set it, then true colour images are displayed correctly.
> > The only problem is that the Linux penguin is displayed much darker
> > than usual (correct colours, but darker). Perhaps the 224 colour
> > format of this image justifies it?
> >
> > I noticed the cfa10049 platform also uses the same configuration (18
> > bits data bus and 32bpp) and was wondering if true colour images are
> > correctly displayed in this platform with this flag set (for example
> > with fbv application [1]).
>
> I had the exact same problem, and suggested the exact same solution a
> few weeks back.
>
> https://patchwork.kernel.org/patch/2470441/
>
> The conclusion of that discussion what that the userspace applications
> were not honouring the bitfield correctly set by the mxsfb driver, and
> as such, it was not a bug in the driver.
>
> While this is correct, I wonder, now that since we had that same problem
> in a very short amount of time, if we couldn't set this behaviour
> dependant of some (dt? kernel argument?) property so that one could
> customise it anyway he want.
>
> Maxime

i.MX2[3|8]    LCD1       LCD2       LCD3
              24bit      18bit      18bit
--------------------------------------------
LCD_D0         B0         B0         --
LCD_D1         B1         B1         --
LCD_D2         B2         B2         B0
LCD_D3         B3         B3         B1
LCD_D4         B4         B4         B2
LCD_D5         B5         B5         B3
LCD_D6         B6         G0         B4
LCD_D7         B7         G1         B5

LCD_D8         G0         G2         --
LCD_D9         G1         G3         --
LCD_D10        G2         G4         G0
LCD_D11        G3         G5         G1
LCD_D12        G4         R0         G2
LCD_D13        G5         R1         G3
LCD_D14        G6         R2         G4
LCD_D15        G7         R3         G5

LCD_D16        R0         R4         --
LCD_D17        R1         R5         --
LCD_D18        R2                    R0
LCD_D19        R3                    R1
LCD_D20        R4                    R2
LCD_D21        R5                    R3
LCD_D22        R6                    R4
LCD_D23        R7                    R5

Is your display connected like LCD2 or LCD3? LCD3 must still handled like a 24 
bit display shown in LCD1, while only the LCD2-case is the "24 bit to 18 bit 
mapping" case.

At least my current tests with an i.MX23 and a connection like LCD2 are 
working here with a Qt application. Qt honours the pixel bitfield 
description. And I'm using the "bits-per-pixel = <32>" and "bus-width = <18>" 
entries in the device tree.

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From inki.dae at samsung.com  Thu May 23 09:37:19 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Thu, 23 May 2013 22:37:19 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
Message-ID: <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>

> -----Original Message-----
> From: daniel.vetter at ffwll.ch [mailto:daniel.vetter at ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Thursday, May 23, 2013 8:56 PM
> To: Inki Dae
> Cc: Rob Clark; linux-fbdev; DRI mailing list; Kyungmin Park; myungjoo.ham;
> YoungJun Cho; linux-arm-kernel at lists.infradead.org; linux-
> media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Tue, May 21, 2013 at 11:22 AM, Inki Dae <inki.dae at samsung.com> wrote:
> >> -----Original Message-----
> >> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
> >> Vetter
> >> Sent: Tuesday, May 21, 2013 4:45 PM
> >> To: Inki Dae
> >> Cc: 'Daniel Vetter'; 'Rob Clark'; 'linux-fbdev'; 'DRI mailing list';
> >> 'Kyungmin Park'; 'myungjoo.ham'; 'YoungJun Cho'; linux-arm-
> >> kernel at lists.infradead.org; linux-media at vger.kernel.org
> >> Subject: Re: Introduce a new helper framework for buffer
> synchronization
> >>
> >> On Tue, May 21, 2013 at 04:03:06PM +0900, Inki Dae wrote:
> >> > > - Integration of fence syncing into dma_buf. Imo we should have a
> >> > >   per-attachment mode which decides whether map/unmap (and the new
> >> sync)
> >> > >   should wait for fences or whether the driver takes care of
> syncing
> >> > >   through the new fence framework itself (for direct hw sync).
> >> >
> >> > I think it's a good idea to have per-attachment mode for buffer sync.
> >> But
> >> > I'd like to say we make sure what is the purpose of map
> >> > (dma_buf_map_attachment)first. This interface is used to get a sgt;
> >> > containing pages to physical memory region, and map that region with
> >> > device's iommu table. The important thing is that this interface is
> >> called
> >> > just one time when user wants to share an allocated buffer with dma.
> But
> >> cpu
> >> > will try to access the buffer every time as long as it wants.
> Therefore,
> >> we
> >> > need cache control every time cpu and dma access the shared buffer:
> >> cache
> >> > clean when cpu goes to dma and cache invalidate when dma goes to cpu.
> >> That
> >> > is why I added new interfaces, DMA_BUF_GET_FENCE and
> DMA_BUF_PUT_FENCE,
> >> to
> >> > dma buf framework. Of course, Those are ugly so we need a better way:
> I
> >> just
> >> > wanted to show you that in such way, we can synchronize the shared
> >> buffer
> >> > between cpu and dma. By any chance, is there any way that kernel can
> be
> >> > aware of when cpu accesses the shared buffer or is there any point I
> >> didn't
> >> > catch up?
> >>
> >> Well dma_buf_map/unmap_attachment should also flush/invalidate any
> caches,
> >> and with the current dma_buf spec those two functions are the _only_
> means
> >
> > I know that dma buf exporter should make sure that cache
> clean/invalidate
> > are done when dma_buf_map/unmap_attachement is called. For this, already
> we
> > do so. However, this function is called when dma buf import is requested
> by
> > user to map a dmabuf fd with dma. This means that
> dma_buf_map_attachement()
> > is called ONCE when user wants to share the dmabuf fd with dma.
Actually,
> in
> > case of exynos drm, dma_map_sg_attrs(), performing cache operation
> > internally, is called when dmabuf import is requested by user.
> >
> >> you have to do so. Which strictly means that if you interleave device
> dma
> >> and cpu acccess you need to unmap/map every time.
> >>
> >> Which is obviously horribly inefficient, but a known gap in the dma_buf
> >
> > Right, and also this has big overhead.
> >
> >> interface. Hence why I proposed to add dma_buf_sync_attachment similar
> to
> >> dma_sync_single_for_device:
> >>
> >> /**
> >>  * dma_buf_sync_sg_attachment - sync caches for dma access
> >>  * @attach: dma-buf attachment to sync
> >>  * @sgt: the sg table to sync (returned by dma_buf_map_attachement)
> >>  * @direction: dma direction to sync for
> >>  *
> >>  * This function synchronizes caches for device dma through the given
> >>  * dma-buf attachment when interleaving dma from different devices and
> the
> >>  * cpu. Other device dma needs to be synced also by calls to this
> >>  * function (or a pair of dma_buf_map/unmap_attachment calls), cpu
> access
> >>  * needs to be synced with dma_buf_begin/end_cpu_access.
> >>  */
> >> void dma_buf_sync_sg_attachment(struct dma_buf_attachment *attach,
> >>                               struct sg_table *sgt,
> >>                               enum dma_data_direction direction)
> >>
> >> Note that "sync" here only means to synchronize caches, not wait for
> any
> >> outstanding fences. This is simply to be consistent with the
> established
> >> lingo of the dma api. How the dma-buf fences fit into this is imo a
> >> different topic, but my idea is that all the cache coherency barriers
> >> (i.e. dma_buf_map/unmap_attachment, dma_buf_sync_sg_attachment and
> >> dma_buf_begin/end_cpu_access) would automatically block for any
> attached
> >> fences (i.e. block for write fences when doing read-only access, block
> for
> >> all fences otherwise).
> >
> > As I mentioned already, kernel can't aware of when cpu accesses a shared
> > buffer: user can access a shared buffer after mmap anytime and the
> shared
> > buffer should be synchronized between cpu and dma. Therefore, the above
> > cache coherency barriers should be called every time cpu and dma tries
> to
> > access a shared buffer, checking before and after of cpu and dma access.
> And
> > exactly, the proposed way do such thing. For this, you can refer to the
> > below link,
> >
> > http://www.mail-archive.com/linux-media at vger.kernel.org/msg62124.html
> >
> > My point is that how kernel can aware of when those cache coherency
> barriers
> > should be called to synchronize caches and buffer access between cpu and
> > dma.
> >
> >>
> >> Then we could do a new dma_buf_attach_flags interface for special cases
> >> (might also be useful for other things, similar to the recently added
> >> flags in the dma api for wc/no-kernel-mapping/...). A new flag like
> >> DMA_BUF_ATTACH_NO_AUTOFENCE would then mean that the driver takes care
> of
> >> all
> >> fencing for this attachment and the dma-buf functions should not do the
> >> automagic fence blocking.
> >>
> >> > In Linux kernel, especially embedded system, we had tried to
> implement
> >> > generic interfaces for buffer management; how to allocate a buffer
> and
> >> how
> >> > to share a buffer. As a result, now we have CMA (Contiguous Memory
> >> > Allocator) for buffer allocation, and we have DMA-BUF for buffer
> sharing
> >> > between cpu and dma. And then how to synchronize a buffer between cpu
> >> and
> >> > dma? I think now it's best time to discuss buffer synchronization
> >> mechanism,
> >> > and that is very natural.
> >>
> >> I think it's important to differentiate between the two meanings of
> sync:
> >> - synchronize caches (i.e. cpu cache flushing in most cases)
> >> - and synchronize in-flight dma with fences.
> >>
> >
> > Agree, and I meant that the buffer synchronization mechanism includes
> the
> > above two things. And I think the two things should be addressed
> together.
> 
> I'm still confused about what you're trying to achive in the big
> picture here exactly. I think the key point is your statement above
> that the kernel can't know when the cpu access a dma-buf. That's not
> true though:
> 
> For userspace mmaps the kernel can shoot down ptes and so prevent
> userspace from accessing a buffer.

In this case, cpu access to user space will incur page fault. However, cpu
accesses user space region after mmap in user mode and every time user
wants. And user needs something before passing a buffer accessed into device
driver and also vice versa.

> Since that's pretty inefficient
> gem/ttm have additional ioctls for cache coherency transitions.

Yes, that's the something, and that's a way now we are using if I understood
surely. User side calls those ioctls for cache coherency between cpu and
dma: cache clean after cpu access and before dma access, and cache
invalidate after dma access and before cpu access. I thought it's better to
control cache in kernel side than user because I had found some Linux based
platforms overuse cache operations. So I thought the best place for it is
the proposed fence helper or similar thing: we would need interfaces to
notify the moment, 'before and after of cpu access', into kernel side. My
proposal is to couple those two things, synchronizing caches and in-flight
dma with fences, in kernel side. With this approach, user doesn't need to
care when dma and cpu access will be started, and when dma and cpu access
will be completed anymore when user wants to access a buffer and share it
with dma. All things, cache coherency and buffer fencing between dma and
cpu, will be done in kernel side.

> dma_buf currently has no support for explicit coherency transitions
> from userpsace, so if pte shootdown is an issue we need to improve
> that.
> 
> If I read your proposal correctly you instead suggest to _alway_ flush
> cache before/after each dma. That will _completely_ kill performance
> (been there with i915, trust me).
> 

In case of using a cachable mapped buffer and sharing the buffer with dma,
we need to clean cache after cpu access and before dma access, and we need
to invalidate cache after dma access and before cpu access every time. Isn't
that we are doing so now? I have a little knowledge about Desktop world so
there might be my misunderstanding.

Could you please give me advices and more comments if there is my missing
point or misunderstanding?

> For cpu access from kernel space we already have explicit mappings all
> over the place (kmap&friends), so I don't see any issues with
> inserting the relevant begin/end_cpu_access calls just around the cpu
> access. The big exception is the framebuffer layer, but even that has
> the deferred io support. KMS otoh has a nice frontbuffer dirty
> interface to correctly support dumb clients, unfortunately fbcon does
> not (yet) use that.
> 
> For these reasons I don't see a need to smash cache coherency and
> fencing into one problem, and hence why I've proposed to tackle each
> of them individually.

I might be really missing some points :)

Thanks,
Inki Dae

> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



From andrew at lunn.ch  Thu May 23 09:42:00 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 23 May 2013 15:42:00 +0200
Subject: [PATCH v2 6/6] arm: mvebu: support new bootloaders shipped by
 Marvell
In-Reply-To: <1369315854-32724-7-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1369315854-32724-7-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130523134200.GD8681@lunn.ch>

On Thu, May 23, 2013 at 03:30:54PM +0200, Thomas Petazzoni wrote:
> On Marvell platforms, the "internal registers" is a window of 1 MB of
> the physical address space that contains all the registers for the
> various peripherals of the SoC (timers, interrupt controllers, GPIO
> controllers, Ethernet, etc.). The base address of this 1 MB window is
> configurable, and this base address is configured using a register
> that is itself part of this window.
> 
> All earlier families of Marvell EBU SoCs supported by Linux used
> 0xf1000000 as the base address of the internal registers window. For
> some reason, early versions of the Marvell 370/XP platforms used
> 0xd0000000 as the base address. This base address is set up by the
> bootloader. However, in order to keep as much physical address space
> to address RAM below the 4 GB limit, Marvell had to switch the base
> address of the internal registers window back to 0xf1000000.
> 
> All the new bootloaders shipped by Marvell remap those registers to
> 0xf1000000. This commit adapts the kernel Device Tree and other
> definitions so that it can boot with such bootloaders.
> 
> However, since those changing are breaking the compatibility with old
> bootloader (resulting in a kernel that crashes without displaying any
> message), we have implement a temporary solution for users of an old
> bootloader.
> 
> One particular bit of a CP15 register has been chosen to indicate
> whether we use an old bootloader (setting the address at 0xd0000000)
> or a new bootloader (setting the address at 0xf1000000). In the
> ->map_io() function, when the bit is already set, there is nothing to
> do, we are already using a new bootloader and internal registers are
> at 0xf1000000.
> 
> However, when the bit is not set, we do a static mapping of the
> register area that allows to change the internal register address, we
> change this address, and set this bit.
> 
> Note that this mechanism also needs cooperation from the earlyprintk
> addruart handler (in arch/arm/include/debug/mvebu.S). This is where
> things get complex: the CP15 bit that has been chosen gets reset to
> zero at the first call to the 'wfi' instruction. So it cannot be used
> during the entire life of the system. Instead, whenever the ->map_io()
> function has switched to the internal register space to the new
> address, it sets a global variable 'mvebu_switched_regs', which the
> earlyprintk reads. If it's true, then the move has already been done
> and there is no need to read the CP15 register. If
> 'mvebu_switched_regs' is false, we are before the register move, so we
> need to read the CP15 bit to find out whether we're being booted from
> an old bootloader (which mapped the register space at 0xd0000000) or a
> new bootloader (which mapped the register space at 0xf1000000).
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Hi Thomas

Thanks for making the small changes i requested.

Acked-by: Andrew Lunn <andrew at lunn.ch>

	  Andrew



> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
>  arch/arm/boot/dts/armada-370.dtsi    |    3 +-
>  arch/arm/boot/dts/armada-xp-gp.dts   |    2 +-
>  arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++++++--
>  arch/arm/mach-mvebu/armada-370-xp.c  |  105 ++++++++++++++++++++++++++++++++++
>  arch/arm/mach-mvebu/armada-370-xp.h  |    2 +-
>  6 files changed, 181 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 52a1f5e..95ec049 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -33,7 +33,7 @@
>  		#size-cells = <1>;
>  		compatible = "simple-bus";
>  		interrupt-parent = <&mpic>;
> -		ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
> +		ranges = <0          0 0xf1000000 0x0100000 /* internal registers */
>  			  0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
>  
>  		internal-regs {
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> index aee2b18..030e425 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -29,8 +29,9 @@
>  	};
>  
>  	soc {
> -		ranges = <0          0xd0000000 0x0100000 /* internal registers */
> +		ranges = <0          0xf1000000 0x0100000 /* internal registers */
>  			  0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
> +
>  		internal-regs {
>  			system-controller at 18200 {
>  				compatible = "marvell,armada-370-xp-system-controller";
> diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
> index 3ee63d1..8fb1679 100644
> --- a/arch/arm/boot/dts/armada-xp-gp.dts
> +++ b/arch/arm/boot/dts/armada-xp-gp.dts
> @@ -39,7 +39,7 @@
>  	};
>  
>  	soc {
> -		ranges = <0          0 0xd0000000 0x100000
> +		ranges = <0          0 0xf1000000 0x100000
>  			  0xf0000000 0 0xf0000000 0x1000000>;
>  
>  		internal-regs {
> diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
> index df191af..ec875c4 100644
> --- a/arch/arm/include/debug/mvebu.S
> +++ b/arch/arm/include/debug/mvebu.S
> @@ -5,20 +5,85 @@
>   *
>   * Lior Amsalem <alior at marvell.com>
>   * Gregory Clement <gregory.clement at free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
>  */
>  
> -#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> -#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000
> +#define ARMADA_370_XP_UART_PHYS_BASE_OLD	0xd0012000
> +#define ARMADA_370_XP_UART_PHYS_BASE_NEW	0xf1012000
> +#define ARMADA_370_XP_UART_VIRT_BASE_OLD	0xfec12000
> +#define ARMADA_370_XP_UART_VIRT_BASE_NEW	0xfea12000
>  
>  	.macro	addruart, rp, rv, tmp
> -	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
> -	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
> -	orr	\rp, \rp, #0x00012000
> -	orr	\rv, \rv, #0x00012000
> +
> +#ifndef ZIMAGE
> +	/*
> +	 * This loads the value of mvebu_switched_regs. We need a
> +	 * little bit of gymnastic here to handle the fact that the
> +	 * addruart code is duplicated in different places, and called
> +	 * sometimes with the MMU disabled, sometimes the MMU enabled.
> +	 *
> +	 * Notice that when this earlyprintk code is linked into the
> +	 * kernel decompressor (i.e ZIMAGE is defined), this code isn't
> +	 * compiled. The reason is because the global mvebu_switched_regs
> +	 * variable is not available in the decompressor code. At this
> +	 * early stage, we simply test the CP15 bit (below) to know where
> +	 * the internal registers are.
> +	 */
> +	adr	\rp, addruart_switched_regs_\@
> +	ldr	\rv, [\rp]
> +	sub	\rv, \rv, \rp
> +	ldr	\rp, [\rp, #4]
> +	sub	\tmp, \rp, \rv
> +	ldr	\rp, [\tmp, #0]
> +	cmp	\rp, #0
> +
> +	/* If we have already switched, then use the new register
> +	   address */
> +	bne	addruart_new_\@
> +#endif
> +
> +	/*
> +	 * We haven't switched the register location, so test the CP15
> +	 * register bit to find whether we are:
> +	 * - with an old bootloader setting the base address to
> +	 *   0xd0000000
> +	 * - with a new bootloader that has already set the
> +	 *   base address to 0xf1000000
> +	 * We adapt the physical address returned depending on the
> +	 * value of this bit, but also the virtual address, because we
> +	 * can't remap the old physical address and the new physical
> +	 * address at the same location.
> +	 */
> +	mrc	p15, 0, \tmp, c5, c0, 0
> +	and	\tmp, \tmp, #(1 << 11)
> +	cmp	\tmp, #0
> +	bne	addruart_new_\@
> +
> +addruart_old_\@:
> +	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_OLD
> +	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_OLD
> +	b	addruart_out_\@
> +addruart_new_\@:
> +	ldr	\rp, =ARMADA_370_XP_UART_PHYS_BASE_NEW
> +	ldr	\rv, =ARMADA_370_XP_UART_VIRT_BASE_NEW
> +	b	addruart_out_\@
> +
> +#ifndef ZIMAGE
> +	/*
> +	 * Global variable mvebu_switched_regs not visible in the
> +	 * decompressor code
> +	 */
> +	.align
> +addruart_switched_regs_\@:
> +	.long	.
> +	.long	mvebu_switched_regs
> +#endif
> +
> +addruart_out_\@:
>  	.endm
>  
>  #define UART_SHIFT	2
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
> index c1c0556..752eedd 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.c
> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
> @@ -28,8 +28,113 @@
>  #include "common.h"
>  #include "coherency.h"
>  
> +/*
> + * Note on the internal register address.
> + *
> + * On Marvell platforms, the "internal registers" is a window of 1 MB
> + * of the physical address space that contains all the registers for
> + * the various peripherals of the SoC (timers, interrupt controllers,
> + * GPIO controllers, Ethernet, etc.). The base address of this 1 MB
> + * window is configurable, and this base address is configured using a
> + * register that is itself part of this window.
> + *
> + * All earlier families of Marvell EBU SoCs supported by Linux used
> + * 0xf1000000 as the base address of the internal registers
> + * window. For some reason, early versions of the Marvell 370/XP
> + * platforms used 0xd0000000 as the base address. This base address is
> + * set up by the bootloader. However, in order to keep as much
> + * physical address space to address RAM below the 4 GB limit, we had
> + * to switch the base address of the internal registers window back to
> + * 0xf1000000, and we wanted to achieve that without breaking existing
> + * platforms, where the bootloader was initially setting the base
> + * address to 0xd0000000. So the kernel is responsible for switching
> + * to 0xf1000000 when needed.
> + *
> + * One particular bit of a CP15 register has been chosen to indicate
> + * whether we use an old bootloader (setting the address at
> + * 0xd0000000) or a new bootloader (setting the address at
> + * 0xf1000000). In the ->map_io() function, when the bit is already
> + * set, there is nothing to do, we are already using a new bootloader
> + * and internal registers are at 0xf1000000.
> + *
> + * However, when the bit is not set, we do a static mapping of the
> + * register area that allows to change the internal register address
> + * and we change this address.
> + *
> + * Once those steps are done, we set a global variable,
> + * mvebu_switched_regs, that tells the earlyprintk code how to
> + * behave. Note that this mechanism also needs cooperation from the
> + * earlyprintk addruart handler (in arch/arm/include/debug/mvebu.S).
> + */
> +
> +#define NEW_INTERNAL_REGS_ADDR  0xf1000000
> +#define OLD_INTERNAL_REGS_ADDR  0xd0000000
> +#define MBUS_OLD_PHYS_ADDR      (OLD_INTERNAL_REGS_ADDR + 0x20000)
> +#define MBUS_OLD_VIRT_ADDR      0xfe9ff000
> +#define  MBUS_INTERNAL_REGS_ADDR      0x80
> +
> +/*
> + * We really want this variable to be part of the .data section,
> + * because it gets accessed by the earlyprintk code before BSS gets
> + * initialized to zero. This variable indicates whether the switch to
> + * the new register has taken place or not. It is needed because the
> + * CP15 bit used by the bootloader to tell the kernel where the
> + * registers are mapped is cleared to 0 at the first 'wfi'
> + * instruction. So we can't use it for the entire life of the system,
> + * and we instead use this boolean to indicate to the earlyprintk code
> + * that the switch has occured and it doesn't need to look at the CP15
> + * bit anymore.
> + */
> +unsigned int __section(.data) mvebu_switched_regs = 0;
> +
> +/*
> + * Detect if we're running an old bootloader that has set the physical
> + * base address of internal registers to 0xd0000000
> + */
> +static int armada_370_xp_has_old_bootloader(void)
> +{
> +	u32 val;
> +	asm volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(val));
> +	return !(val & BIT(11));
> +}
> +
>  static void __init armada_370_xp_map_io(void)
>  {
> +	if (armada_370_xp_has_old_bootloader()) {
> +		struct map_desc desc;
> +		void __iomem *mbus = IOMEM(MBUS_OLD_VIRT_ADDR);
> +
> +		desc.virtual = MBUS_OLD_VIRT_ADDR;
> +		desc.pfn     = __phys_to_pfn(MBUS_OLD_PHYS_ADDR);
> +		desc.length  = PAGE_SIZE;
> +		desc.type    = MT_DEVICE;
> +
> +		/*
> +		 * Map the area that contains the registers that
> +		 * allows to change the base address of internal
> +		 * registers.
> +		 */
> +		iotable_init(&desc, 1);
> +
> +		/*
> +		 * Change the physical base address of the
> +		 * registers. From now on, and until
> +		 * debug_ll_io_init() is called below, it is not
> +		 * possible to do any print, because using earlyprintk
> +		 * would lead to memory writes to the old internal
> +		 * registers, which would hang the CPU.
> +		 */
> +		writel(NEW_INTERNAL_REGS_ADDR, mbus + MBUS_INTERNAL_REGS_ADDR);
> +	}
> +
> +	/*
> +	 * Either the registers have been switched by the above code,
> +	 * or the bootloader had already set the register space at the
> +	 * right location. In both cases, tell the earlyprintk code it
> +	 * can now use the new location.
> +	 */
> +	mvebu_switched_regs = 1;
> +
>  	debug_ll_io_init();
>  }
>  
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
> index 585e147..ff9adc4 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.h
> +++ b/arch/arm/mach-mvebu/armada-370-xp.h
> @@ -15,7 +15,7 @@
>  #ifndef __MACH_ARMADA_370_XP_H
>  #define __MACH_ARMADA_370_XP_H
>  
> -#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> +#define ARMADA_370_XP_REGS_PHYS_BASE	0xf1000000
>  
>  /* These defines can go away once mvebu-mbus has a DT binding */
>  #define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
> -- 
> 1.7.9.5
> 


From Madhvapathi.Sriram at csr.com  Thu May 23 09:49:10 2013
From: Madhvapathi.Sriram at csr.com (Madhvapathi Sriram)
Date: Thu, 23 May 2013 13:49:10 +0000
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
References: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>

Comments inline.
________________________________________
From: Barry Song [21cnbao at gmail.com]
Sent: Wednesday, May 22, 2013 9:43 PM
To: dtor at mail.ru; dmitry.torokhov at gmail.com
Cc: linux-input at vger.kernel.org; DL-SHA-WorkGroupLinux; linux-arm-kernel at lists.infradead.org; Binghua Duan; Xianglong Du; Barry Song
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR SiRFprimaII PWRC

From: Binghua Duan <Binghua.Duan at csr.com>

there is an embedded PWRC(power controller) in SiRFprimaII and SiRFatlasVI,
we have an ONKEY button which can generate interrupt to IRQ controller.
in a typical user scenarios, at the runtime, if users touch the key, we put
system to s2ram status.

Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 drivers/input/misc/Kconfig         |  10 +++
 drivers/input/misc/Makefile        |   1 +
 drivers/input/misc/sirfsoc_onkey.c | 176 +++++++++++++++++++++++++++++++++++++
 3 files changed, 187 insertions(+)
 create mode 100644 drivers/input/misc/sirfsoc_onkey.c

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index bb698e1..1d91d1b 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -637,4 +637,14 @@ config INPUT_XEN_KBDDEV_FRONTEND
          To compile this driver as a module, choose M here: the
          module will be called xen-kbdfront.

+config INPUT_SIRFSOC_ONKEY
+       bool "CSR SiRFSoC power on/off/suspend key support"
+       depends on ARCH_SIRF
+       default y
+       help
+         Say Y here if you want to support for the SiRFSoC power on/off/suspend key
+         in Linux, after you press the onkey, system will suspend.
+
+         If unsure, say N.
+
 endif
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index d7fc17f..1d66f03 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS)      += wistron_btns.o
 obj-$(CONFIG_INPUT_WM831X_ON)          += wm831x-on.o
 obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND)        += xen-kbdfront.o
 obj-$(CONFIG_INPUT_YEALINK)            += yealink.o
+obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)      += sirfsoc_onkey.o
diff --git a/drivers/input/misc/sirfsoc_onkey.c b/drivers/input/misc/sirfsoc_onkey.c
new file mode 100644
index 0000000..3e48db9
--- /dev/null
+++ b/drivers/input/misc/sirfsoc_onkey.c
@@ -0,0 +1,176 @@
+/*
+ * Power key driver for SiRF PrimaII
+ *
+ * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/rtc/sirfsoc_rtciobrg.h>
+#include <linux/of.h>
+
+struct sirfsoc_pwrc_drvdata {
+       u32                     pwrc_base;
+       int                     irq;
+       struct input_dev        *input;
+};
+
+#define PWRC_ON_KEY_BIT                        (1 << 0)
+
+#define PWRC_INT_STATUS                        0xc
+#define PWRC_INT_MASK                  0x10
+
+static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
+{
+       struct sirfsoc_pwrc_drvdata *pwrcdrv =
+                       (struct sirfsoc_pwrc_drvdata *)dev_id;
+       u32 int_status;
+       int_status = sirfsoc_rtc_iobrg_readl(
+                       pwrcdrv->pwrc_base + PWRC_INT_STATUS);
+       sirfsoc_rtc_iobrg_writel(int_status & (~PWRC_ON_KEY_BIT),
+                       pwrcdrv->pwrc_base + PWRC_INT_STATUS);
+
+       /*
+        * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
+        * to queue a SUSPEND APM event
+        */
+       input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
+       input_sync(pwrcdrv->input);
+
+       /*
+        * Todo: report KEY_POWER event for Android platforms, Android PowerManager
+        * will handle the suspend and powerdown/hibernation
+        */
+
+       return IRQ_HANDLED;
+}
+
+static const struct of_device_id sirfsoc_pwrc_of_match[] = {
+       { .compatible = "sirf,prima2-pwrc" },
+       {},
+}
+MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
+
+static int sirfsoc_pwrc_probe(struct platform_device *pdev)
+{
+       int ret;
+       struct sirfsoc_pwrc_drvdata *pwrcdrv = NULL;
+       struct device_node *np = pdev->dev.of_node;
+
+       pwrcdrv = devm_kzalloc(&pdev->dev,
+               sizeof(struct sirfsoc_pwrc_drvdata), GFP_KERNEL);
+       if (!pwrcdrv) {
+               dev_info(&pdev->dev, "kzalloc fail!\n");
+               return -ENOMEM;
+       }
+
+       /*
+        * we can't use of_iomap because pwrc is not mapped in memory, the so-called base
+        * address is only offset in rtciobrg
+        */
+       ret = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);

Possible mem leak here  - not freeing pwrcdrv

+       if (ret) {
+               dev_err(&pdev->dev, "unable to find base address of pwrc node in dtb\n");
+               return ret;
+       }
+
+       pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
+       if (!pwrcdrv->input)
+               return -ENOMEM;
+
+       pwrcdrv->input->name = "sirfsoc pwrckey";
+       pwrcdrv->input->phys = "pwrc/input0";
+
+       platform_set_drvdata(pdev, pwrcdrv);
+
+       pwrcdrv->irq = platform_get_irq(pdev, 0);
+       ret = devm_request_irq(&pdev->dev, pwrcdrv->irq,
+                       sirfsoc_pwrc_isr, IRQF_SHARED,
+                       "sirfsoc_pwrc_int", pwrcdrv);
+
+       sirfsoc_rtc_iobrg_writel(
+               sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK)
+               | PWRC_ON_KEY_BIT, pwrcdrv->pwrc_base + PWRC_INT_MASK);

Enabling the MASK for an interrupt should only come after it has been successfully claimed? Else we might be leaving and interrupt enabled without being able to handle it?

Possible mem leak here not freeing any allocated devices/memory/irq.
I suggest all the error handling be collated at the end of this function for various stages and error handling be done there.
Please have a look at https://www.kernel.org/doc/Documentation/input/input-programming.txt

+       if (ret) {
+               dev_err(&pdev->dev, "pwrc: Unable to claim irq %d; error %d\n",
+                       pwrcdrv->irq, ret);
+               return ret;
+       }
+
+       pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
+       set_bit(KEY_POWER, pwrcdrv->input->keybit);
+
+       ret = input_register_device(pwrcdrv->input);
+       if (ret) {
+               dev_err(&pdev->dev,
+                       "pwrc: Unable to register input device,error: %d\n",
+                       ret);
+               return ret;
+       }
+
+       device_init_wakeup(&pdev->dev, 1);
+
+       return 0;
+}
+
+static int sirfsoc_pwrc_remove(struct platform_device *pdev)
+{
+       device_init_wakeup(&pdev->dev, 0);
+
+       return 0;
+}
+
+#ifdef CONFIG_PM
+static int pwrc_suspend(struct device *dev)
+{
+       return 0;
+}
+
+static int pwrc_resume(struct device *dev)
+{
+       struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
+

Typically, the wake up interrupts would be ensured to be active while going to sleep/suspend.
However, here at resume the interrupt mask is being set. Is it because, there are some caveats here?

+       /*
+        * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
+        * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
+        */
+       sirfsoc_rtc_iobrg_writel(
+               sirfsoc_rtc_iobrg_readl(
+               pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
+               pwrcdrv->pwrc_base + PWRC_INT_MASK);
+
+       return 0;
+}
+
+static const struct dev_pm_ops sirfsoc_pwrc_pm_ops = {
+       .suspend = pwrc_suspend,
+       .resume = pwrc_resume,
+};
+#endif
+
+static struct platform_driver sirfsoc_pwrc_driver = {
+       .probe          = sirfsoc_pwrc_probe,
+       .remove         = sirfsoc_pwrc_remove,
+       .driver         = {
+               .name   = "sirfsoc-pwrc",
+               .owner  = THIS_MODULE,
+#ifdef CONFIG_PM
+               .pm     = &sirfsoc_pwrc_pm_ops,
+#endif
+               .of_match_table = of_match_ptr(sirfsoc_pwrc_of_match),
+       }
+};
+
+module_platform_driver(sirfsoc_pwrc_driver);
+
+MODULE_LICENSE("GPLv2");
+MODULE_AUTHOR("Binghua Duan <Binghua.Duan at csr.com>, "
+               "Xianglong Du <Xianglong.Du at csr.com>");
+MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
+MODULE_ALIAS("platform:sirfsoc-pwrc");
--
1.8.2.3



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From geert at linux-m68k.org  Thu May 23 10:10:04 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 23 May 2013 16:10:04 +0200
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <20130523125033.GP18614@n2100.arm.linux.org.uk>
References: <519DCBEF.3090208@asianux.com> <201305231259.43750.arnd@arndb.de>
 <20130523112401.GO18614@n2100.arm.linux.org.uk>
 <201305231409.02359.arnd@arndb.de>
 <20130523125033.GP18614@n2100.arm.linux.org.uk>
Message-ID: <CAMuHMdUzcBuDupe4Fa6XieziGPMpPKC_k8X8gUUmDvLJ+Fe=Hg@mail.gmail.com>

On Thu, May 23, 2013 at 2:50 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, May 23, 2013 at 02:09:02PM +0200, Arnd Bergmann wrote:
>> On Thursday 23 May 2013, Russell King - ARM Linux wrote:
>> > This is the problem you guys are missing - unreachable() means "we lose
>> > control of the CPU at this point".
>>
>> I'm absolutely aware of this. Again, the current behaviour of doing nothing
>> at all isn't very different from undefined behavior when you get when you
>> get to the end of a function returning a pointer without a "return" statement,
>> or when you return from a function that has determined that it is not safe
>> to continue.
>
> Running off the end of a function like that is a different kettle of fish.
> The execution path is still as the compiler intends - what isn't is that
> the data returned is likely to be random trash.
>
> That's _quite_ different from the CPU starting to execute the contents
> of a literal data pool.

I agree it's best to e.g. trap and reboot.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From arnd at arndb.de  Thu May 23 10:12:42 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 16:12:42 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523120248.51a85f50@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305222236.12652.arnd@arndb.de> <20130523120248.51a85f50@skate>
Message-ID: <201305231612.42395.arnd@arndb.de>

On Thursday 23 May 2013, Thomas Petazzoni wrote:
> Dear Arnd Bergmann,
> 
> On Wed, 22 May 2013 22:36:12 +0200, Arnd Bergmann wrote:
> 
> > > > Maybe i'm missunderstand Arnd, but i think he is suggesting a property
> > > > somewhere in DT which says where the bootloader left the register
> > > > space before jumping to the kernel. You can then look at this property
> > > > and then decide if you need to remap or not. Only this one property
> > > > needs to differ between old and new bootloader. You could even say, if
> > > > the property is not in DT, a remap is needed.
> > 
> > No, the idea was that we don't need to remap if we know where the registers
> > are. The mbus driver might remap them if it is really careful about not
> > breaking any existing mappings, but it's probably easier to just leave
> > them alone.
> 
> Again, our aim is to get everybody to run kernels with registers
> remapped at 0xf1, so that we're back to what should have been done
> originally.
> 
> Ideally, we'd like to completely forget about supporting old
> bootloaders, and assume we only have good bootloaders that remap things
> to 0xf1. We're only proposing this *temporary* solution to make the
> transition easier, give some time to the board manufacturers to release
> updated bootloaders, to users to upgrade their bootloaders, and finally
> remove this temporary solution.
> 
> We clearly don't want to go down the road of supporting an
> arbitrarily-defined base address for the internal registers. This has
> never been the case for Kirkwood, Orion5x, Dove, and there is no
> compelling reason to make it a requirement for Armada 370/XP.

Well, the main reason I see now is that Marvell screwed it up by having
two incompatible versions of u-boot. Using a different base address on
new machines would have been no problem at all, but supporting the
same machine with different addresses depending on the boot loader
version is madness. As you say, it's too late to change that now, so
maybe the best solution is to make the registers always get reassigned.
5 trick.
> > 
> > Yes, that would not be an improvement. However, since we know what boot
> > loader we have when we pass the devicetree, that devicetree can just
> > contain the correct 'reg' property for the internal registers.
> 
> What do you mean by "we know what boot loader we have when we pass the
> devicetree" ?
> 
> The mere user of the kernel just does:
> 
> 	make ARCH=arm mvebu_defconfig
> 	make ARCH=arm CROSS_COMPILE=...
> 	cat arch/arm/boot/zImage arch/arm/boot/dts/armada-370-mirabox.dtb > zImage.mirabox
> 	... prepare uImage ...
> 
> and he certainly doesn't want to understand the gory details of which
> internal register base address to chose depending on which bootloader
> version he is using. This is really asking normal users to have a too
> much intimate knowledge of the hardware details.

Right, appended device tree is a problem, but if a user does that, I think
we can rightfully expect them to know what they are doing.

> The temporary solution we're proposing doesn't have this drawback: an
> user can boot the kernel on either an old or new bootloader, without
> having to worry about checking/changing the Device Tree source about
> this bizarre internal register address thing.
> 
> As a developer of the Armada 370/XP, I am frequently contacted by users
> to help them getting the mainline kernel booting on their Mirabox or
> OpenBlocks. And trust me: even getting the appended DTB gymnastic right
> is not easy. So getting this internal register story right is going to
> be a nightmare in terms of support.
> 
> Please do not inflict to us such a support pain :-)

I think we should consequently make sure we never get a production
u-boot for Mirabox or OpenBlocks that changes the internal register
address and also allows ATAGS based booting. Either those machines
continue to use the 0xd0 address for the internal registers, or they
must ensure to fix up the device tree properly.

Since you explained that we want to move the internal registers to get
more available memory, I think what you also want to do is to dynamically
reassign the internal register mapping when the mbus driver gets loaded,
just like all the other mbus mappings. That will let you move it even
higher to free up more memory, and it means we can tell the Mirabox
and OpenBlocks people to leave the internal register base address alone
in their u-boot, so we don't have two conflicting versions of those
machines.

	Arnd


From arnd at arndb.de  Thu May 23 10:14:53 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 16:14:53 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523142301.10dbeff9@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305222240.05124.arnd@arndb.de> <20130523142301.10dbeff9@skate>
Message-ID: <201305231614.53664.arnd@arndb.de>

On Thursday 23 May 2013, Thomas Petazzoni wrote:
> But that's not the case. Neither the old nor the new bootloaders are
> changing the Device Tree in any way that allows us to know whether
> registers are mapped at 0xd0 and 0xf1. Those bootloaders are already in
> the field, and we have little control over that. Even if we had
> control, what we would tell Marvell to implement in their U-Boot,
> today?

We would tell Marvell that changing the base address was a horrible
mistake and that they have to revert to 0xd0 in order to make sure
the mistake does not spread any further and all users would update.

> The DT binding of the mbus driver is not complete, and therefore
> the mechanism to specify the location of the internal registers is
> going to change when we introduce the DT binding for the mbus driver.

Right. It should not be hard to agree on the binding at least, but
you are correct that we don't have that today and we shouldn't rush
things here.

	Arnd


From broonie at kernel.org  Thu May 23 10:24:19 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 23 May 2013 09:24:19 -0500
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130523070905.GD18714@gmail.com>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
 <20130522165353.GB18714@gmail.com>
 <20130522174516.GT1627@sirena.org.uk>
 <20130523070905.GD18714@gmail.com>
Message-ID: <20130523142419.GG2412@sirena.org.uk>

On Thu, May 23, 2013 at 08:09:05AM +0100, Lee Jones wrote:
> On Wed, 22 May 2013, Mark Brown wrote:

> > OK, so the regulator driver is buggy and insisting on having constraints
> > passed in for every regulator then?

> If that's not how it's meant to work then, yes.

Yes, that's the intention - it should be possible to just not pass in
anything in and have the driver start up in read only mode (partly to
save having to do things like what you're doing).
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From stern at rowland.harvard.edu  Thu May 23 10:27:10 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 23 May 2013 10:27:10 -0400 (EDT)
Subject: [RFC V6 PATCH 1/3] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <1369307506-4458-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305231026420.925-100000@iolanthe.rowland.org>

On Thu, 23 May 2013, Manjunath Goudar wrote:

> This patch prepares ohci-hcd for being split up into a core
> library and separate platform driver modules.  A generic
> ohci_hc_driver structure is created, containing all the "standard"
> values, and a new mechanism is added whereby a driver module can
> specify a set of overrides to those values.  In addition the
> ohci_restart(),ohci_suspend() and ohci_resume() routines need
> to be EXPORTed for use by the drivers.
> 
> Added ohci_setip(() and ohci_start() routine for to start the generic
> controller rather than each having its own idiosyncratic approach.
> This allow to clean duplicated code in most of SOC driver

This patch looks good.

Acked-by: Alan Stern <stern at rowland.harvard.edu>



From shc_work at mail.ru  Thu May 23 10:28:10 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 23 May 2013 18:28:10 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSF0gQVJNOiBkdHM6IGlteDogZml4IGNsb2NrcyBmb3Ig?=
 =?UTF-8?B?Y3NwaQ==?=
In-Reply-To: <20130523123642.GK32299@pengutronix.de>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
 <1369311059.366490908@f190.mail.ru>
 <20130523123642.GK32299@pengutronix.de>
Message-ID: <1369319290.379285076@f398.i.mail.ru>

> On Thu, May 23, 2013 at 04:10:59PM +0400, Alexander Shiyan wrote:
> > > > The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> > > > 
> > > > Signed-off-by: Jonas Andersson <jonas at microbit.se>
> > > > ---
> > > >  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
> > > >  arch/arm/boot/dts/imx27.dtsi |  6 +++---
> > > >  arch/arm/boot/dts/imx51.dtsi |  2 +-
> > > >  arch/arm/boot/dts/imx53.dtsi |  2 +-
> > > >  4 files changed, 11 insertions(+), 11 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> > > > index d2550e0..7011539 100644
> > > > --- a/arch/arm/boot/dts/imx25.dtsi
> > > > +++ b/arch/arm/boot/dts/imx25.dtsi
> > > > @@ -141,8 +141,8 @@
> > > >  				#size-cells = <0>;
> > > >  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
> > > >  				reg = <0x43fa4000 0x4000>;
> > > > -				clocks = <&clks 62>;
> > > > -				clock-names = "ipg";
> > > > +				clocks = <&clks 62>, <&clks 62>;
> > > > +				clock-names = "ipg", "per";
> > > >  				interrupts = <14>;
> > > >  				status = "disabled";
> > > >  			};
> > 
> > Sorry, typo.
> > 
> > > Why you do not use "dummy" clock for "per" here?
> > 
> > *for "ipg"
> 
> Because the same clock is used for the register clock and the baudrate
> clock. You have to enable the ipg clock to access registers.

I am not see any "ipg" clock usage in the spi driver. If "ipg" clock is
a dependency for "per" clock, it should be registered in ccm as parent.
Is not it?

---

From stern at rowland.harvard.edu  Thu May 23 10:30:38 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 23 May 2013 10:30:38 -0400 (EDT)
Subject: [RFC PATCH 2/3] USB: OHCI: Generic changes to make ohci-pci a
 separate driver
In-Reply-To: <1369307506-4458-3-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305231027140.925-100000@iolanthe.rowland.org>

On Thu, 23 May 2013, Manjunath Goudar wrote:

> Note that this changes is part of separating the ohci pci host controller
> driver from ohci-hcd host code.
> This contains :
>  -Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
>   and EXPORTed, this is part of the effort to move the ohci pci related
>   code to generic pci code.
>  -Passed "pci_dev" argument instead  of "ohci_hcd" in sb800_prefetch()
>   function to avoid extra include file in pci-quirks.c.

> diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
> index 13ebbb7..2490b81 100644
> --- a/drivers/usb/host/ohci-hcd.c
> +++ b/drivers/usb/host/ohci-hcd.c

> @@ -1275,7 +1266,7 @@ MODULE_LICENSE ("GPL");
>  #define PLATFORM_DRIVER		ohci_platform_driver
>  #endif
>  
> -#if	!defined(PCI_DRIVER) &&		\
> +#if	!defined(PCI_DRIVER) && \
>  	!defined(PLATFORM_DRIVER) &&	\
>  	!defined(OMAP1_PLATFORM_DRIVER) &&	\
>  	!defined(OMAP3_PLATFORM_DRIVER) &&	\

As Arnd mentioned, this doesn't belong here.

> diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
> index 88731b7..78e0095 100644
> --- a/drivers/usb/host/ohci-q.c
> +++ b/drivers/usb/host/ohci-q.c
> @@ -41,6 +41,7 @@ finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
>  __releases(ohci->lock)
>  __acquires(ohci->lock)
>  {
> +	struct pci_dev *pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);

You shouldn't call to_pci_dev().  At this point you don't know if the 
controller is a PCI device or not.  Instead, just do

	struct device *dev = ohci_to_hcd(ohci)->self.controller;

Then in sb800_prefetch(), where it makes sense, you can call 
to_pci_dev().

> @@ -580,6 +581,7 @@ static void td_submit_urb (
>  	struct urb	*urb
>  ) {
>  	struct urb_priv	*urb_priv = urb->hcpriv;
> +	struct pci_dev *pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);

Same thing here.

Otherwise this is okay.

Alan Stern



From thomas.petazzoni at free-electrons.com  Thu May 23 10:32:50 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 16:32:50 +0200
Subject: [PATCH v2 0/3] Marvell PCIe driver improvements
Message-ID: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>

Bjorn, Jason, Andrew, Gregory,

Here is an updated version of the PCIe improvements.

Changes since v1:

 * Fix some typos in the comments of PATCH 2, noticed by Bjorn
   Helgaas.

 * Rework the two last patches (first one was fixing the capability
   list, the other one the emulation of the devsel bits in the status
   register), after the comments of Bjorn. In fact, it turns out that
   the status register is composed of read-only bits for which we want
   to emulate a value of zero, and the other bits are write-1-to-clear
   bits that expose error conditions that we do not handle in the
   emulated bridge. So, in summary, emulating a 0 status register on
   reads, and ignoring writes to the status register is the simplest
   solution. If we later on implement a capability list, we can use a
   more clever emulation of the status register, but for the moment,
   this simple solution is enough. Therefore, the two last patches are
   now one single, simpler patch.

I'd like those improvements to be kept separated from the original
PCIe driver itself: while the PCIe driver has been around and reviewed
for a long time, those improvements are newer. And I clearly do not
want the PCIe driver to miss 3.11 because of any problem that could be
found in those additional improvements.

The main improvement being brought here is that the PCI-to-PCI bridge
logic is fixed/extended to properly support physical PCIe bridges that
are connected on a PCIe interface of a Marvell board. Without this
improvement, only the devices connected directly to the PCIe
interfaces of the board are properly enumerated. Any device that would
sit beyond a physical bridge is not visible.

Bjorn, with your Acked-by, could the Marvell maintainers include those
patches in their branch, merged through arm-soc? They already have the
Marvell PCIe driver itself, so I believe it makes sense to merge those
improvements through the same path.

Jason, those patches have been prepared on top of my marvell-pcie-v10
branch, I hope that's ok for you. If you want me to rebase them on
some other branch in which you have integrated the PCIe driver, don't
hesitate to tell me to do so. That said, since those patches are only
touching the driver itself and no other file, they should not cause
any conflict with other changes.

Thanks,

Thomas

Thomas Petazzoni (3):
  pci: mvebu: no longer fake the slot location of downstream devices
  pci: mvebu: allow the enumeration of devices beyond physical bridges
  pci: mvebu: fix the emulation of the status register

 drivers/pci/host/pci-mvebu.c |   55 +++++++++++++++++++++++++++++++++---------
 1 file changed, 44 insertions(+), 11 deletions(-)

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 10:32:51 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 16:32:51 +0200
Subject: [PATCH v2 1/3] pci: mvebu: no longer fake the slot location of
 downstream devices
In-Reply-To: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369319573-19927-2-git-send-email-thomas.petazzoni@free-electrons.com>

By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:

 * On slot 0, a "Marvell Memory controller", identical on all PCIe
   interfaces, and which isn't useful when the Marvell SoC is the PCIe
   root complex (i.e, the normal case when we run Linux on the Marvell
   SoC).

 * On slot 1, the real PCIe card connected into the PCIe slot of the
   board.

So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.

However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.

Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |   19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index ad1c46b..0bc21b0 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -51,6 +51,7 @@
 #define  PCIE_CTRL_X1_MODE		0x0001
 #define PCIE_STAT_OFF		0x1a04
 #define  PCIE_STAT_BUS                  0xff00
+#define  PCIE_STAT_DEV                  0x1f0000
 #define  PCIE_STAT_LINK_DOWN		BIT(0)
 #define PCIE_DEBUG_CTRL         0x1a60
 #define  PCIE_DEBUG_SOFT_RESET		BIT(20)
@@ -148,6 +149,16 @@ static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
 	writel(stat, port->base + PCIE_STAT_OFF);
 }
 
+static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
+{
+	u32 stat;
+
+	stat = readl(port->base + PCIE_STAT_OFF);
+	stat &= ~PCIE_STAT_DEV;
+	stat |= nr << 16;
+	writel(stat, port->base + PCIE_STAT_OFF);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -572,8 +583,7 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 
 	/* Access the real PCIe interface */
 	spin_lock_irqsave(&port->conf_lock, flags);
-	ret = mvebu_pcie_hw_wr_conf(port, bus,
-				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+	ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
 				    where, size, val);
 	spin_unlock_irqrestore(&port->conf_lock, flags);
 
@@ -606,8 +616,7 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 
 	/* Access the real PCIe interface */
 	spin_lock_irqsave(&port->conf_lock, flags);
-	ret = mvebu_pcie_hw_rd_conf(port, bus,
-				    PCI_DEVFN(1, PCI_FUNC(devfn)),
+	ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
 				    where, size, val);
 	spin_unlock_irqrestore(&port->conf_lock, flags);
 
@@ -817,6 +826,8 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
 			continue;
 		}
 
+		mvebu_pcie_set_local_dev_nr(port, 1);
+
 		if (mvebu_pcie_link_up(port)) {
 			port->haslink = 1;
 			dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 10:32:52 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 16:32:52 +0200
Subject: [PATCH v2 2/3] pci: mvebu: allow the enumeration of devices beyond
 physical bridges
In-Reply-To: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369319573-19927-3-git-send-email-thomas.petazzoni@free-electrons.com>

Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.

However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.

This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.

Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:

-[0000:00]-+-01.0-[01]----00.0
           +-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
           |                               +-05.0-[05]--
           |                               +-07.0-[06]--
           |                               \-09.0-[07]----00.0
           \-0a.0-[08]----00.0

Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |   31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 0bc21b0..a3c4638 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -554,7 +554,8 @@ mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
 		if (bus->number == 0 && port->devfn == devfn)
 			return port;
 		if (bus->number != 0 &&
-		    port->bridge.secondary_bus == bus->number)
+		    bus->number >= port->bridge.secondary_bus &&
+		    bus->number <= port->bridge.subordinate_bus)
 			return port;
 	}
 
@@ -578,7 +579,18 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 	if (bus->number == 0)
 		return mvebu_sw_pci_bridge_write(port, where, size, val);
 
-	if (!port->haslink || PCI_SLOT(devfn) != 0)
+	if (!port->haslink)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	/*
+	 * On the secondary bus, we don't want to expose any other
+	 * device than the device physically connected in the PCIe
+	 * slot, visible in slot 0. In slot 1, there's a special
+	 * Marvell device that only makes sense when the Armada is
+	 * used as a PCIe endpoint.
+	 */
+	if (bus->number == port->bridge.secondary_bus &&
+	    PCI_SLOT(devfn) != 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	/* Access the real PCIe interface */
@@ -609,7 +621,20 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 	if (bus->number == 0)
 		return mvebu_sw_pci_bridge_read(port, where, size, val);
 
-	if (!port->haslink || PCI_SLOT(devfn) != 0) {
+	if (!port->haslink) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/*
+	 * On the secondary bus, we don't want to expose any other
+	 * device than the device physically connected in the PCIe
+	 * slot, visible in slot 0. In slot 1, there's a special
+	 * Marvell device that only makes sense when the Armada is
+	 * used as a PCIe endpoint.
+	 */
+	if (bus->number == port->bridge.secondary_bus &&
+	    PCI_SLOT(devfn) != 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Thu May 23 10:32:53 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 16:32:53 +0200
Subject: [PATCH v2 3/3] pci: mvebu: fix the emulation of the status register
In-Reply-To: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369319573-19927-4-git-send-email-thomas.petazzoni@free-electrons.com>

The status register of the PCI configuration space of PCI-to-PCI
bridges contain some read-only bits, and so write-1-to-clear bits. So,
the Linux PCI core sometimes writes 0xffff to this status register,
and in the current PCI-to-PCI bridge emulation code of the Marvell
driver, we do take all those 1s being written. Even the read-only bits
are being overwritten.

For now, all the read-only bits should be emulated to have the zero
value.

The other bits, that are write-1-to-clear bits are used to report
various kind of errors, and are never set by the emulated bridge, so
there is no need to support this write-1-to-clear bits mechanism.

As a conclusion, the easiest solution is to simply emulate this status
register by returning zero when read, and ignore the writes to it.

This has two visible effects:

 * The devsel is no longer 'unknown' in, i.e

   Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0

   becomes:

   Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0

   in lspci -v.

   This was caused by a value of 11b being read for devsel, which is
   an invalid value. This 11b value being read was due to a previous
   write of 0xffff into the status register.

 * The capability list is no longer broken, because we indicate to the
   Linux PCI core that we don't have a Capabilities Pointer in the PCI
   configuration space of this bridge. The following message is
   therefore no longer visible in lspci -v:

   Capabilities: [fc] <chain broken>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/pci/host/pci-mvebu.c |    5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index a3c4638..481e44a 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -69,7 +69,6 @@ struct mvebu_sw_pci_bridge {
 	u16 vendor;
 	u16 device;
 	u16 command;
-	u16 status;
 	u16 class;
 	u8 interface;
 	u8 revision;
@@ -359,7 +358,6 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
 
 	memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
 
-	bridge->status = PCI_STATUS_CAP_LIST;
 	bridge->class = PCI_CLASS_BRIDGE_PCI;
 	bridge->vendor = PCI_VENDOR_ID_MARVELL;
 	bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
@@ -386,7 +384,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
 		break;
 
 	case PCI_COMMAND:
-		*value = bridge->status << 16 | bridge->command;
+		*value = bridge->command;
 		break;
 
 	case PCI_CLASS_REVISION:
@@ -479,7 +477,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
 	switch (where & ~3) {
 	case PCI_COMMAND:
 		bridge->command = value & 0xffff;
-		bridge->status = value >> 16;
 		break;
 
 	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
-- 
1.7.9.5



From stern at rowland.harvard.edu  Thu May 23 10:37:51 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 23 May 2013 10:37:51 -0400 (EDT)
Subject: [RFC V6 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369307506-4458-4-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305231034110.925-100000@iolanthe.rowland.org>

On Thu, 23 May 2013, Manjunath Goudar wrote:

> This patch splits the PCI portion of ohci-hcd out into its
> own separate driver module, called ohci-pci.
> 
> The major point of difficulty lies in ohci-pci's many vendor- and
> device-specific workarounds.  Some of them have to be applied before
> calling ohci_start() some after, which necessitates a fair amount of
> code motion.  The other platform drivers require much smaller changes.
> 
> The complete sb800_prefetch() function moved to ohci-q.c,because its
> only related to ohci-pci driver.
> 
> V2:
>   - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
>     and rest of the generic code is written in ohci_start of ohci-hcd.c file.
> V3:
>  - ohci_restart() has been called in ohci_pci_reset() function for to reset the ohci pci.
> 
> V4:
>  -sb800_prefetch() moved to ohci-q.c,because its only related to ohci-pci.
>  -no longer _creating_ CONFIG_USB_OHCI_PCI,creating CONFIG_USB_OHCI_HCD_PCI.
>  -overrides renamed with pci_override,its giving proper meaning.
> 
> V5:
>  -sb800_prefetch() moved to pci-quirks.c,because its only related to pci.
> 
> V6:
>  -sb800_prefetch() function has been moved to pci-quirks.c made as separate patch in 2/3.
>  -Most of the generic ohci pci changes moved in 2/3 patch,now this is complete  ohci-pci separation patch.

This patch has a lot of extra stuff in it.  It looks like you forgot to
undo a bunch of things from the previous version, things that are no
longer needed.

As I said before, you really need to proofread your patches before
emailing them.  Don't rely on other people to find your mistakes.

Also, you left out one thing that should still be here.  What happened 
to the part about changing

#if	!defined(PCI_DRIVER) &&		\

to

#if	!ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\

?

Alan Stern



From gregory.clement at free-electrons.com  Thu May 23 10:41:25 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu, 23 May 2013 16:41:25 +0200
Subject: [PATCH v2 0/6] Support new Marvell bootloaders for Armada 370/XP
In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <519E2A95.1040600@free-electrons.com>

Hi Thomas,
On 05/23/2013 03:30 PM, Thomas Petazzoni wrote:

[...]

> Best regards,
> 
> Thomas
> 
> Thomas Petazzoni (6):
>   arm: mvebu: remove dependency of SMP init on static I/O mapping
>   arm: mvebu: avoid hardcoded virtual address in coherency code
>   arm: mvebu: move cache and mvebu-mbus initialization later
>   arm: mvebu: remove hardcoded static I/O mapping
>   arm: mvebu: don't hardcode a physical address in headsmp.S
>   arm: mvebu: support new bootloaders shipped by Marvell

I have already reviewed it internally. All the changes are really
limited to mvebu and do not impact any other subsystem. So you
have my acked-by, and once Jason Cooper will have given his Acked-by,
then I think we will be able to apply the series on mvebu/ branches.

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

Thanks,

> 
>  arch/arm/boot/dts/armada-370-xp.dtsi |    2 +-
>  arch/arm/boot/dts/armada-370.dtsi    |    3 +-
>  arch/arm/boot/dts/armada-xp-gp.dts   |    2 +-
>  arch/arm/include/debug/mvebu.S       |   77 +++++++++++++++++++--
>  arch/arm/mach-mvebu/armada-370-xp.c  |  124 +++++++++++++++++++++++++++++-----
>  arch/arm/mach-mvebu/armada-370-xp.h  |    4 +-
>  arch/arm/mach-mvebu/coherency.c      |   36 ++++------
>  arch/arm/mach-mvebu/coherency.h      |    4 --
>  arch/arm/mach-mvebu/common.h         |    2 +
>  arch/arm/mach-mvebu/headsmp.S        |   20 +++---
>  arch/arm/mach-mvebu/platsmp.c        |   10 ++-
>  11 files changed, 220 insertions(+), 64 deletions(-)
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From lee.jones at linaro.org  Thu May 23 10:44:53 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 May 2013 15:44:53 +0100
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130523142419.GG2412@sirena.org.uk>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
 <20130522165353.GB18714@gmail.com>
 <20130522174516.GT1627@sirena.org.uk>
 <20130523070905.GD18714@gmail.com>
 <20130523142419.GG2412@sirena.org.uk>
Message-ID: <20130523144453.GL22683@gmail.com>

On Thu, 23 May 2013, Mark Brown wrote:

> On Thu, May 23, 2013 at 08:09:05AM +0100, Lee Jones wrote:
> > On Wed, 22 May 2013, Mark Brown wrote:
> 
> > > OK, so the regulator driver is buggy and insisting on having constraints
> > > passed in for every regulator then?
> 
> > If that's not how it's meant to work then, yes.
> 
> Yes, that's the intention - it should be possible to just not pass in
> anything in and have the driver start up in read only mode (partly to
> save having to do things like what you're doing).

Okay, noted.

Well, whatever happens I'm going to be able to refactor the driver in
the -rc:s, so we still need this fix, or the world will end.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From thomas.petazzoni at free-electrons.com  Thu May 23 10:47:36 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 16:47:36 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305231612.42395.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305222236.12652.arnd@arndb.de> <20130523120248.51a85f50@skate>
 <201305231612.42395.arnd@arndb.de>
Message-ID: <20130523164736.610fc55d@skate>

Dear Arnd Bergmann,

On Thu, 23 May 2013 16:12:42 +0200, Arnd Bergmann wrote:

> > Ideally, we'd like to completely forget about supporting old
> > bootloaders, and assume we only have good bootloaders that remap
> > things to 0xf1. We're only proposing this *temporary* solution to
> > make the transition easier, give some time to the board
> > manufacturers to release updated bootloaders, to users to upgrade
> > their bootloaders, and finally remove this temporary solution.
> > 
> > We clearly don't want to go down the road of supporting an
> > arbitrarily-defined base address for the internal registers. This
> > has never been the case for Kirkwood, Orion5x, Dove, and there is no
> > compelling reason to make it a requirement for Armada 370/XP.
> 
> Well, the main reason I see now is that Marvell screwed it up by
> having two incompatible versions of u-boot. Using a different base
> address on new machines would have been no problem at all, but
> supporting the same machine with different addresses depending on the
> boot loader version is madness. As you say, it's too late to change
> that now, so maybe the best solution is to make the registers always
> get reassigned. 5 trick.

Not sure what you mean by '5 trick', and what I should understand from
this :(

> > What do you mean by "we know what boot loader we have when we pass
> > the devicetree" ?
> > 
> > The mere user of the kernel just does:
> > 
> > 	make ARCH=arm mvebu_defconfig
> > 	make ARCH=arm CROSS_COMPILE=...
> > 	cat arch/arm/boot/zImage
> > arch/arm/boot/dts/armada-370-mirabox.dtb > zImage.mirabox ...
> > prepare uImage ...
> > 
> > and he certainly doesn't want to understand the gory details of
> > which internal register base address to chose depending on which
> > bootloader version he is using. This is really asking normal users
> > to have a too much intimate knowledge of the hardware details.
> 
> Right, appended device tree is a problem, but if a user does that, I
> think we can rightfully expect them to know what they are doing.

Unfortunately, not really. Appended Device Tree is the only way to go
for old bootloaders, and we don't want users of such bootloaders to
have to modify their Device Tree to change the base address of the
internal registers.

> > The temporary solution we're proposing doesn't have this drawback:
> > an user can boot the kernel on either an old or new bootloader,
> > without having to worry about checking/changing the Device Tree
> > source about this bizarre internal register address thing.
> > 
> > As a developer of the Armada 370/XP, I am frequently contacted by
> > users to help them getting the mainline kernel booting on their
> > Mirabox or OpenBlocks. And trust me: even getting the appended DTB
> > gymnastic right is not easy. So getting this internal register
> > story right is going to be a nightmare in terms of support.
> > 
> > Please do not inflict to us such a support pain :-)
> 
> I think we should consequently make sure we never get a production
> u-boot for Mirabox or OpenBlocks that changes the internal register
> address and also allows ATAGS based booting.

It is impossible to prevent that. U-Boot always supports ATAGs booting
for ARM, and optionally Device Tree based booting.

And once again, you believe we have an enormous control over what is
happening at the bootloader level. So when you say "we should
consequently make sure ..", this is simply not possible: we have no
control over this.

> Either those machines continue to use the 0xd0 address for the
> internal registers, or they must ensure to fix up the device tree
> properly.

We don't have such control over bootloaders. I believe Marvell has done
a great achievement by pushing all this Armada 370/XP code to the
mainline kernel. However, they are not (yet) at the same level of
open-source involvement as far as bootloaders are concerned, so we have
little control over that. I'm hoping that the situation will evolve
over time, but for now, we have to live with the assumption that the
control we have over what the bootloader is doing is minimal.

So any solution you propose with "the bootloader should do X or Y" will
unfortunately not work practically for us.

> Since you explained that we want to move the internal registers to get
> more available memory, I think what you also want to do is to
> dynamically reassign the internal register mapping when the mbus
> driver gets loaded, just like all the other mbus mappings.

Ideally, it should be like this. Unfortunately, moving the internal
register mapping is really a painful operation: you have to know where
is the address to change the internal register base address (which
itself changes when the internal register base address changes), and all
code interacting with peripherals before the change of the address must
be synchronized so that after the switch it uses the new address.

Switching the internal registers address at runtime after a lot of
things have booted is *painful* and we really don't want to do that.
Sebastian Hesselbarth, who has worked on the topic, will confirm this.

So, just like it has been the case for years in Kirkwood, Dove and
Orion5x, Armada 370/XP will have their registers mapped at 0xf1000000
when the kernel is booted. As far as Linux is concerned, it should
assume that the base address of the register is *not* configurable,
just like it is the case for many other ARM SoCs.

What we're only asking is to have a temporary, SoC-specific, workaround
to ease the transition towards this goal.

We've gone through great lengths to find a solution that does not
touch *any* ARM generic code (even though it would have been much
simpler!). At least one Marvell maintainer (Andrew Lunn) is fine with
this temporary solution, and since the issue is very SoC-specific, and
completely self-contained in the SoC-specific code, would it be
possible to be pragmatic and let us merge such a workaround?

Thanks,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From marex at denx.de  Thu May 23 10:48:17 2013
From: marex at denx.de (Marek Vasut)
Date: Thu, 23 May 2013 16:48:17 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <201305230920.18200.jbe@pengutronix.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <201305221305.09579.marex@denx.de> <201305230920.18200.jbe@pengutronix.de>
Message-ID: <201305231648.17356.marex@denx.de>

Dear Juergen Beisert,

> Hi Marek,
> 
> Marek Vasut wrote:
> > > > i2c slowness is a different issue.
> > > 
> > > Same happens here for my i.M23 based platform. It seems the PIO mode
> > > does not work, or at least not like it works on a i.MX28. Each short
> > > transfer needs about one second (without an error message) but does
> > > not send anything on the I2C lines.
> > > 
> > > I need the following patches to make I2C master work within a 3.10-rc2
> > > kernel:
> > > 
> > > Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C
> > 
> > I'm all for it, but then ... won't it be better if you actually fixed the
> > PIO and mixed-mode on MX23 instead of implementing such hack?
> 
> If the PIO mode or my patch is a hack depends on the point of view: Lucas
> told me the PIO mode is *mentioned* but *not specified* in the
> i.MX23/i.MX28 datasheets.

The PIO works the same way DMA does -- set up bits and then pump data into the 
DATA register. 

> So, the PIO mode seems to depend on some undocumented status bits in the
> i.MX28 I2C controller implementation.

How would DMA work then if it used undocumented registers ? It's in the 
documentation, just read it or ask FSL ;-)

Best regards,
Marek Vasut


From thomas.petazzoni at free-electrons.com  Thu May 23 10:50:59 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 16:50:59 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305231614.53664.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305222240.05124.arnd@arndb.de> <20130523142301.10dbeff9@skate>
 <201305231614.53664.arnd@arndb.de>
Message-ID: <20130523165059.473032d2@skate>

Dear Arnd Bergmann,

On Thu, 23 May 2013 16:14:53 +0200, Arnd Bergmann wrote:
> On Thursday 23 May 2013, Thomas Petazzoni wrote:
> > But that's not the case. Neither the old nor the new bootloaders are
> > changing the Device Tree in any way that allows us to know whether
> > registers are mapped at 0xd0 and 0xf1. Those bootloaders are
> > already in the field, and we have little control over that. Even if
> > we had control, what we would tell Marvell to implement in their
> > U-Boot, today?
> 
> We would tell Marvell that changing the base address was a horrible
> mistake and that they have to revert to 0xd0 in order to make sure
> the mistake does not spread any further and all users would update.

The longer we wait to switch from 0xd0 to 0xf1, the more complex and
painful the migration will be.

Honestly, from Marvell perspective, switching to 0xf1 and dropping
support for the old platforms is not a problem. I insisted quite a lot
to be given time to find a reasonable solution, that is entirely
self-contained in SoC-specific code, to provide a transition path for
people who are using old bootloaders.

I'm humbly asking you to be pragmatic on this one, and understand that
the goal is to have the kernel assumes it's being booted with registers
configured at 0xf1 and that all the rest is a temporary workaround.

> > The DT binding of the mbus driver is not complete, and therefore
> > the mechanism to specify the location of the internal registers is
> > going to change when we introduce the DT binding for the mbus
> > driver.
> 
> Right. It should not be hard to agree on the binding at least, but
> you are correct that we don't have that today and we shouldn't rush
> things here.

Agreed. We are currently working on this, but it will take some time to
get sorted out properly.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From maxime.ripard at free-electrons.com  Thu May 23 10:58:35 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 May 2013 16:58:35 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <519DCEE9.6070208@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>
 <519DCEE9.6070208@schinagl.nl>
Message-ID: <20130523145835.GI8595@lukather>

On Thu, May 23, 2013 at 10:10:17AM +0200, Oliver Schinagl wrote:
> Then, i'm not sure if the driver is the best for this to be loaded?
> Maxime, what do you think? Personally I would feel more in having
> this in the mach-sunxi/core.c bit, but then again, this is currently
> a module and wouldn't be useful to have there. Maxime is far more
> knowledgeable to answer that.

Hmmm, I don't understand what you mean here. Could you explain what you
have in mind?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From oliver+list at schinagl.nl  Thu May 23 11:05:21 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Thu, 23 May 2013 17:05:21 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <20130523145835.GI8595@lukather>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>
 <519DCEE9.6070208@schinagl.nl> <20130523145835.GI8595@lukather>
Message-ID: <519E3031.8080604@schinagl.nl>

On 05/23/13 16:58, Maxime Ripard wrote:
> On Thu, May 23, 2013 at 10:10:17AM +0200, Oliver Schinagl wrote:
>> Then, i'm not sure if the driver is the best for this to be loaded?
>> Maxime, what do you think? Personally I would feel more in having
>> this in the mach-sunxi/core.c bit, but then again, this is currently
>> a module and wouldn't be useful to have there. Maxime is far more
>> knowledgeable to answer that.
>
> Hmmm, I don't understand what you mean here. Could you explain what you
> have in mind?
I've thought about it a little, and don't think core.c is a good spot, 
since the module will have to be loaded, or available there. And that's 
really early.

So I guess, during probe, controlled by a parameter perhaps, load all 16 
bytes into the random pool as Linus suggested?
>
> Thanks,
> Maxime
>



From lsartre at adeneo-embedded.com  Thu May 23 11:07:29 2013
From: lsartre at adeneo-embedded.com (SARTRE Leo)
Date: Thu, 23 May 2013 17:07:29 +0200
Subject: [PATCH] Add congatec conga-QEVAL minimal board support
Message-ID: <3465D313FDFB824F9A9C8CD24FA4F6BC0108CD11@frontmail.adetel.com>

Conga-QEVAL is a Qseven Evaluation Carrier board, manufactured by
Congatec, it can be used with conga-QMX6 modules based on Freescale's
i.MX6 ARM processors.
More details can be found on the manufacturer's web site:
for the board:
http://www.congatec.com/en/products/accessories/dView/conga-qeval.html
for the module:
http://www.congatec.com/en/products/qseven/dView/conga-qmx6.html

imx6q-congatec.dts: Add minimal congatec device tree (usb, fec, spi
andusdhc)
mach-imx6q.c      : Add fixup function for micrel KSZ9031RNX

Signed-off-by: Leo Sartre <lsartre at adeneo-embedded.com>
---
 arch/arm/boot/dts/imx6q-congatec.dts |   92 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mach-imx6q.c       |   41 +++++++++++++++
 2 files changed, 133 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6q-congatec.dts

diff --git a/arch/arm/boot/dts/imx6q-congatec.dts b/arch/arm/boot/dts/imx6q-congatec.dts
new file mode 100644
index 0000000..d54d31a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-congatec.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ * Copyright 2013 Adeneo Embedded
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+
+/ {
+	model = "Congatec i.MX6 Quad QSEVEN eval Board";
+	compatible = "cgt,imx6q-qmx6", "fsl,imx6q";
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+	};
+
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio3 19 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	status = "okay";
+
+	flash: m25p80 at 0 {
+		compatible = "sst,sst25vf032b";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	hog {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+				MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+				MX6Q_PAD_EIM_D23__GPIO3_IO23  0x80000000
+				MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
+			>;
+		};
+	};
+};
+
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_1>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 23 0>;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4_1>;
+	cd-gpios = <&gpio2 6 0>;
+	wp-gpios = <&gpio2 7 0>;
+	vmmc-supply = <&reg_3p3v>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_1>;
+};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..7de4208 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -96,6 +96,36 @@ soft:
 	soft_restart(0);
 }
 
+/* For congatec qmx6 board, fixup micrel KSZ9031RNX */
+static int ksz9031rnx_phy_fixup(struct phy_device *phydev)
+{
+	if (IS_BUILTIN(CONFIG_PHYLIB)) {
+		/* adjust KSZ9031 ethernet phy */
+		phy_write(phydev, 0x0d, 0x2);
+		phy_write(phydev, 0x0e, 0x4);
+		phy_write(phydev, 0x0d, 0xc002);
+		phy_write(phydev, 0x0e, 0x0000);
+
+		phy_write(phydev, 0x0d, 0x2);
+		phy_write(phydev, 0x0e, 0x5);
+		phy_write(phydev, 0x0d, 0xc002);
+		phy_write(phydev, 0x0e, 0x0000);
+
+		phy_write(phydev, 0x0d, 0x2);
+		phy_write(phydev, 0x0e, 0x6);
+		phy_write(phydev, 0x0d, 0xc002);
+		phy_write(phydev, 0x0e, 0xffff);
+
+		phy_write(phydev, 0x0d, 0x2);
+		phy_write(phydev, 0x0e, 0x8);
+		phy_write(phydev, 0x0d, 0xc002);
+		phy_write(phydev, 0x0e, 0x3fff);
+		phy_write(phydev, 0x0d, 0x0);
+	}
+
+	return 0;
+}
+
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
@@ -145,6 +175,14 @@ static void __init imx6q_sabrelite_init(void)
 	imx6q_sabrelite_cko1_setup();
 }
 
+static void __init imx6q_cgtqmx6_init(void)
+{
+	if (IS_BUILTIN(CONFIG_PHYLIB))
+		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
+				ksz9031rnx_phy_fixup);
+	imx6q_sabrelite_cko1_setup();
+}
+
 static void __init imx6q_1588_init(void)
 {
 	struct regmap *gpr;
@@ -166,6 +204,9 @@ static void __init imx6q_init_machine(void)
 	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 		imx6q_sabrelite_init();
 
+	if (of_machine_is_compatible("cgt,imx6q-qmx6"))
+		imx6q_cgtqmx6_init();
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
 	imx_anatop_init();
-- 
1.7.10.4


From broonie at kernel.org  Thu May 23 11:18:16 2013
From: broonie at kernel.org (Mark Brown)
Date: Thu, 23 May 2013 10:18:16 -0500
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130523144453.GL22683@gmail.com>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
 <20130522165353.GB18714@gmail.com>
 <20130522174516.GT1627@sirena.org.uk>
 <20130523070905.GD18714@gmail.com>
 <20130523142419.GG2412@sirena.org.uk>
 <20130523144453.GL22683@gmail.com>
Message-ID: <20130523151816.GB6406@sirena.org.uk>

On Thu, May 23, 2013 at 03:44:53PM +0100, Lee Jones wrote:

> Well, whatever happens I'm going to be able to refactor the driver in
> the -rc:s, so we still need this fix, or the world will end.

Why is it so invasive to have the driver cope with absent constraints?
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From nicolas.pitre at linaro.org  Thu May 23 11:23:25 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 23 May 2013 11:23:25 -0400 (EDT)
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <20130523084126.GI18614@n2100.arm.linux.org.uk>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
 <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
 <20130523084126.GI18614@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.03.1305231108500.1918@syhkavp.arg>

On Thu, 23 May 2013, Russell King - ARM Linux wrote:

> On Thu, May 23, 2013 at 09:28:24AM +0200, Ard Biesheuvel wrote:
> > In order to use the NEON/VFP unit in the kernel, we should
> > initialize it a bit earlier in the boot process so NEON users
> > that like to do a quick benchmark at load time (like the
> > xor_blocks or RAID-6 code) find the NEON/VFP unit already
> > enabled.
> 
> So what are the results of those benchmarks that the RAID-6 code does?
> 
> This isn't something which will get accepted without there being a very
> strong case for it; firstly, we've always said "no FP in the kernel".

That was my opinion as well.  However the numbers are compelling.

And X86 and PPC do use FP in the kernel already for very specific tasks 
because of that.

> Secondly, it makes it too easy for people to start thinking that FP is
> safe in the kernel.  It isn't - this will go horribly wrong if the VFP
> hardware bounces an instruction to the support code.

Hmmm. good point.  We probably should set a flag in kernel_vfp_begin() 
and BUG() if the support code is invoked while that flag is set.

> Lastly, what happens if you sleep between kernel_vfp_start() and
> kernel_vfp_end() ?  That's a context switch which will mess up your
> VFP state.  I think you need to take a spinlock (not _bh nor _irqsave
> versions) in here to ensure that people don't get the idea that they
> _can_ sleep between these two.

Isn't preemption off sufficient to flag that case?  The scheduler is 
very noisy when schedule() is called with preemption disabled.


Nicolas


From maxime.ripard at free-electrons.com  Thu May 23 11:27:32 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 May 2013 17:27:32 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <519E3031.8080604@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <CACRpkdaWADjy1YZXTcRaXU+ZsS6_pG0hojQdnz=qeTgyVY7_Ww@mail.gmail.com>
 <519DCEE9.6070208@schinagl.nl> <20130523145835.GI8595@lukather>
 <519E3031.8080604@schinagl.nl>
Message-ID: <20130523152732.GL8595@lukather>

On Thu, May 23, 2013 at 05:05:21PM +0200, Oliver Schinagl wrote:
> On 05/23/13 16:58, Maxime Ripard wrote:
> >On Thu, May 23, 2013 at 10:10:17AM +0200, Oliver Schinagl wrote:
> >>Then, i'm not sure if the driver is the best for this to be loaded?
> >>Maxime, what do you think? Personally I would feel more in having
> >>this in the mach-sunxi/core.c bit, but then again, this is currently
> >>a module and wouldn't be useful to have there. Maxime is far more
> >>knowledgeable to answer that.
> >
> >Hmmm, I don't understand what you mean here. Could you explain what you
> >have in mind?
> I've thought about it a little, and don't think core.c is a good
> spot, since the module will have to be loaded, or available there.
> And that's really early.
> 
> So I guess, during probe, controlled by a parameter perhaps, load
> all 16 bytes into the random pool as Linus suggested?

Yeah, though I don't really know what the parameter would be useful for,
but yes, do it in the driver's probe.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From l.stach at pengutronix.de  Thu May 23 11:28:24 2013
From: l.stach at pengutronix.de (Lucas Stach)
Date: Thu, 23 May 2013 17:28:24 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <201305231648.17356.marex@denx.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <201305221305.09579.marex@denx.de> <201305230920.18200.jbe@pengutronix.de>
 <201305231648.17356.marex@denx.de>
Message-ID: <1369322904.4142.36.camel@weser.hi.pengutronix.de>

Am Donnerstag, den 23.05.2013, 16:48 +0200 schrieb Marek Vasut:
> Dear Juergen Beisert,
> 
> > Hi Marek,
> > 
> > Marek Vasut wrote:
> > > > > i2c slowness is a different issue.
> > > > 
> > > > Same happens here for my i.M23 based platform. It seems the PIO mode
> > > > does not work, or at least not like it works on a i.MX28. Each short
> > > > transfer needs about one second (without an error message) but does
> > > > not send anything on the I2C lines.
> > > > 
> > > > I need the following patches to make I2C master work within a 3.10-rc2
> > > > kernel:
> > > > 
> > > > Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C
> > > 
> > > I'm all for it, but then ... won't it be better if you actually fixed the
> > > PIO and mixed-mode on MX23 instead of implementing such hack?
> > 
> > If the PIO mode or my patch is a hack depends on the point of view: Lucas
> > told me the PIO mode is *mentioned* but *not specified* in the
> > i.MX23/i.MX28 datasheets.
> 
> The PIO works the same way DMA does -- set up bits and then pump data into the 
> DATA register. 

> > So, the PIO mode seems to depend on some undocumented status bits in the
> > i.MX28 I2C controller implementation.
> 
> How would DMA work then if it used undocumented registers ? It's in the 
> documentation, just read it or ask FSL ;-)
> 
While the PIO mode might use the same controller mechanisms as the DMA
mode, PIO mode is _not_ a documented mode of operation for the i.MX23.

To quote the i.MX28 RM: "The I2C block on the i.MX28 supports a new PIO
mode or soft-DMA mode.", which implies the PIO mode to be a new mode of
operation not found on earlier i.MX SoCs.
The doc is slightly fuzzy here as the i.MX23 RM in contrary states:
"Short transmission (up to three bytes plus address) can be easily
triggered using only PIO operations, i.e., no DMA setup required." But
again it's not a documented mode of operation, i.MX23 doc only describes
the DMA mode.

So while we _might_ be able to get the PIO mode to work on the i.MX23
there is nothing in the doc stating that it's even meant to work. Even
while PIO and DMA mode use the same internal mechanisms, there's still
plenty of opportunities of fail in there. After all PIO mode relies on
reading a debug register in the course of normal operation.

Only more extensive experimentation could show if we are in fact able to
make it work, a first shot of using PIO mode on MX23 failed, so it might
as well be that Juergens quick fix is correct and we have to disable PIO
mode on MX23 altogether. That said please stop slapping the word "hack"
over this patch until proven otherwise.

Regards,
Lucas
-- 
Pengutronix e.K.                           | Lucas Stach                 |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From lee.jones at linaro.org  Thu May 23 11:30:15 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 May 2013 16:30:15 +0100
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <20130523151816.GB6406@sirena.org.uk>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
 <20130522155347.GJ1627@sirena.org.uk>
 <20130522165353.GB18714@gmail.com>
 <20130522174516.GT1627@sirena.org.uk>
 <20130523070905.GD18714@gmail.com>
 <20130523142419.GG2412@sirena.org.uk>
 <20130523144453.GL22683@gmail.com>
 <20130523151816.GB6406@sirena.org.uk>
Message-ID: <20130523153015.GN22683@gmail.com>

On Thu, 23 May 2013, Mark Brown wrote:

> On Thu, May 23, 2013 at 03:44:53PM +0100, Lee Jones wrote:
> 
> > Well, whatever happens I'm going to be able to refactor the driver in
> > the -rc:s, so we still need this fix, or the world will end.
> 
> Why is it so invasive to have the driver cope with absent constraints?

It probably isn't. Are you asking me to code that up for the -rc:s?

I would be happier if I could stick it onto my TODO and address it
at another time for inclusion into -next, as I have a list of priority
items to attend to in the immediate future.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From steve.capper at linaro.org  Thu May 23 11:31:16 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 16:31:16 +0100
Subject: [PATCH v2 0/4] ARM: mm: HugeTLB + THP support.
Message-ID: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>

The following patches bring both HugeTLB support and Transparent
HugePage (THP) support to ARM.

Only long descriptors (LPAE) are supported in this series.

The code has been tested on an Arndale board (Exynos 5250).

This patch set is based on 3.10-rc2.

Major changes since the Patch:
 * LPAE code has been separated from non-LPAE code (this series
   is the LPAE code).
 * PROT_NONE support for HugeTLB and THP has been implemented.

Major changes since the RFC:
 * huge pmd sharing removed from the 3-level code as this was
   found to be very rarely, if ever?, used. This allowed for some
   code simplification.

 * hardware pmd bits for 2-levels of paging are now taken from
   mmu.c. Also the mapping code now uses pte/pmd bit helper
   functions rather than the custom pre-processor logic.

Cheers,
-- 
Steve

Catalin Marinas (2):
  ARM: mm: HugeTLB support for LPAE systems.
  ARM: mm: Transparent huge page support for LPAE systems.

Steve Capper (2):
  ARM: mm: correct pte_same behaviour for LPAE.
  ARM: mm: Add support for flushing HugeTLB pages.

 arch/arm/Kconfig                            |   8 +++
 arch/arm/include/asm/hugetlb-3level.h       |  71 +++++++++++++++++++
 arch/arm/include/asm/hugetlb.h              |  84 +++++++++++++++++++++++
 arch/arm/include/asm/pgtable-3level-hwdef.h |   4 ++
 arch/arm/include/asm/pgtable-3level.h       |  88 ++++++++++++++++++++++++
 arch/arm/include/asm/pgtable.h              |   3 +
 arch/arm/include/asm/tlb.h                  |   6 ++
 arch/arm/include/asm/tlbflush.h             |   2 +
 arch/arm/mm/Makefile                        |   1 +
 arch/arm/mm/dma-mapping.c                   |   2 +-
 arch/arm/mm/flush.c                         |  25 ++++---
 arch/arm/mm/fsr-3level.c                    |   4 +-
 arch/arm/mm/hugetlbpage.c                   | 101 ++++++++++++++++++++++++++++
 13 files changed, 386 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/include/asm/hugetlb-3level.h
 create mode 100644 arch/arm/include/asm/hugetlb.h
 create mode 100644 arch/arm/mm/hugetlbpage.c

-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 11:31:17 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 16:31:17 +0100
Subject: [PATCH v2 1/4] ARM: mm: correct pte_same behaviour for LPAE.
In-Reply-To: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369323080-9673-2-git-send-email-steve.capper@linaro.org>

For 3 levels of paging the PTE_EXT_NG bit will be set for user
address ptes that are written to a page table but not for ptes
created with mk_pte.

This can cause some comparison tests made by pte_same to fail
spuriously and lead to other problems.

To correct this behaviour, we mask off PTE_EXT_NG for any pte that
is present before running the comparison.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/pgtable-3level.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 86b8fe3..70f041c 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -166,6 +166,23 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 		clean_pmd_entry(pmdp);	\
 	} while (0)
 
+/*
+ * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
+ * that are written to a page table but not for ptes created with mk_pte.
+ *
+ * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
+ * hugetlb_cow, where it is compared with an entry in a page table.
+ * This comparison test fails erroneously leading ultimately to a memory leak.
+ *
+ * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
+ * present before running the comparison.
+ */
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(pte_a,pte_b)	((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG	\
+					: pte_val(pte_a))				\
+				== (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG	\
+					: pte_val(pte_b)))
+
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
 
 #endif /* __ASSEMBLY__ */
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 11:31:18 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 16:31:18 +0100
Subject: [PATCH v2 2/4] ARM: mm: Add support for flushing HugeTLB pages.
In-Reply-To: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369323080-9673-3-git-send-email-steve.capper@linaro.org>

On ARM we use the __flush_dcache_page function to flush the dcache
of pages when needed; usually when the PG_dcache_clean bit is unset
and we are setting a PTE.

A HugeTLB page is represented as a compound page consisting of an
array of pages. Thus to flush the dcache of a HugeTLB page, one must
flush more than a single page.

This patch modifies __flush_dcache_page such that all constituent
pages of a HugeTLB page are flushed.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/flush.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 0d473cc..3706407 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/highmem.h>
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
+#include <linux/hugetlb.h>
 
 #include "mm.h"
 
@@ -168,19 +169,23 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
 	 * coherent with the kernels mapping.
 	 */
 	if (!PageHighMem(page)) {
-		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+		size_t page_size = PAGE_SIZE << compound_order(page);
+		__cpuc_flush_dcache_area(page_address(page), page_size);
 	} else {
-		void *addr;
-
+		unsigned long i;
 		if (cache_is_vipt_nonaliasing()) {
-			addr = kmap_atomic(page);
-			__cpuc_flush_dcache_area(addr, PAGE_SIZE);
-			kunmap_atomic(addr);
-		} else {
-			addr = kmap_high_get(page);
-			if (addr) {
+			for (i = 0; i < (1 << compound_order(page)); i++) {
+				void *addr = kmap_atomic(page);
 				__cpuc_flush_dcache_area(addr, PAGE_SIZE);
-				kunmap_high(page);
+				kunmap_atomic(addr);
+			}
+		} else {
+			for (i = 0; i < (1 << compound_order(page)); i++) {
+				void *addr = kmap_high_get(page);
+				if (addr) {
+					__cpuc_flush_dcache_area(addr, PAGE_SIZE);
+					kunmap_high(page);
+				}
 			}
 		}
 	}
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 11:31:19 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 16:31:19 +0100
Subject: [PATCH v2 3/4] ARM: mm: HugeTLB support for LPAE systems.
In-Reply-To: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369323080-9673-4-git-send-email-steve.capper@linaro.org>

From: Catalin Marinas <catalin.marinas at arm.com>

This patch adds support for hugetlbfs based on the x86 implementation.
It allows mapping of 2MB sections (see Documentation/vm/hugetlbpage.txt
for usage). The 64K pages configuration is not supported (section size
is 512MB in this case).

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
[steve.capper at linaro.org: symbolic constants replace numbers in places.
Split up into multiple files, to simplify future non-LPAE support,
removed huge_pmd_share code, as this is very rarely executed,
Added PROT_NONE support].
Signed-off-by: Steve Capper <steve.capper at linaro.org>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig                            |   4 ++
 arch/arm/include/asm/hugetlb-3level.h       |  71 +++++++++++++++++++
 arch/arm/include/asm/hugetlb.h              |  84 +++++++++++++++++++++++
 arch/arm/include/asm/pgtable-3level-hwdef.h |   2 +
 arch/arm/include/asm/pgtable-3level.h       |  11 +++
 arch/arm/mm/Makefile                        |   1 +
 arch/arm/mm/dma-mapping.c                   |   2 +-
 arch/arm/mm/fsr-3level.c                    |   2 +-
 arch/arm/mm/hugetlbpage.c                   | 101 ++++++++++++++++++++++++++++
 9 files changed, 276 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/hugetlb-3level.h
 create mode 100644 arch/arm/include/asm/hugetlb.h
 create mode 100644 arch/arm/mm/hugetlbpage.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..860f034 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1707,6 +1707,10 @@ config HW_PERF_EVENTS
 	  Enable hardware performance counter support for perf events. If
 	  disabled, perf events will use software events only.
 
+config SYS_SUPPORTS_HUGETLBFS
+       def_bool y
+       depends on ARM_LPAE
+
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h
new file mode 100644
index 0000000..d4014fb
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb-3level.h
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/include/asm/hugetlb-3level.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARM_HUGETLB_3LEVEL_H
+#define _ASM_ARM_HUGETLB_3LEVEL_H
+
+
+/*
+ * If our huge pte is non-zero then mark the valid bit.
+ * This allows pte_present(huge_ptep_get(ptep)) to return true for non-zero
+ * ptes.
+ * (The valid bit is automatically cleared by set_pte_at for PROT_NONE ptes).
+ */
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+	pte_t retval = *ptep;
+	if (pte_val(retval))
+		pte_val(retval) |= L_PTE_VALID;
+	return retval;
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+				   pte_t *ptep, pte_t pte)
+{
+	set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+					 unsigned long addr, pte_t *ptep)
+{
+	ptep_clear_flush(vma, addr, ptep);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+					   unsigned long addr, pte_t *ptep)
+{
+	ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+					    unsigned long addr, pte_t *ptep)
+{
+	return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+					     unsigned long addr, pte_t *ptep,
+					     pte_t pte, int dirty)
+{
+	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+#endif /* _ASM_ARM_HUGETLB_3LEVEL_H */
diff --git a/arch/arm/include/asm/hugetlb.h b/arch/arm/include/asm/hugetlb.h
new file mode 100644
index 0000000..1f1b1cd
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb.h
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARM_HUGETLB_H
+#define _ASM_ARM_HUGETLB_H
+
+#include <asm/page.h>
+#include <asm-generic/hugetlb.h>
+
+#include <asm/hugetlb-3level.h>
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+					  unsigned long addr, unsigned long end,
+					  unsigned long floor,
+					  unsigned long ceiling)
+{
+	free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+					 unsigned long addr, unsigned long len)
+{
+	return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+					 unsigned long addr, unsigned long len)
+{
+	struct hstate *h = hstate_file(file);
+	if (len & ~huge_page_mask(h))
+		return -EINVAL;
+	if (addr & ~huge_page_mask(h))
+		return -EINVAL;
+	return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+	return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+	return pte_wrprotect(pte);
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+	return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+	clear_bit(PG_dcache_clean, &page->flags);
+}
+
+#endif /* _ASM_ARM_HUGETLB_H */
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef..42df407 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -30,6 +30,7 @@
 #define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
 #define PMD_BIT4		(_AT(pmdval_t, 0))
 #define PMD_DOMAIN(x)		(_AT(pmdval_t, 0))
 #define PMD_APTABLE_SHIFT	(61)
@@ -66,6 +67,7 @@
 #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
 #define PTE_BUFFERABLE		(_AT(pteval_t, 1) << 2)		/* AttrIndx[0] */
 #define PTE_CACHEABLE		(_AT(pteval_t, 1) << 3)		/* AttrIndx[1] */
 #define PTE_EXT_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 70f041c..d1bcd82 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -62,6 +62,14 @@
 #define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)
 
 /*
+ * Hugetlb definitions.
+ */
+#define HPAGE_SHIFT		PMD_SHIFT
+#define HPAGE_SIZE		(_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
+
+/*
  * "Linux" PTE definitions for LPAE.
  *
  * These bits overlap with the hardware bits but the naming is preserved for
@@ -185,6 +193,9 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
 
+#define pte_huge(pte)		(pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 9e51be9..224a9cc 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES)		+= proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)	+= alignment.o
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
+obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
 
 obj-$(CONFIG_CPU_ABRT_NOMMU)	+= abort-nommu.o
 obj-$(CONFIG_CPU_ABRT_EV4)	+= abort-ev4.o
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7857f0b..38b78ef 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -250,7 +250,7 @@ static void __dma_free_buffer(struct page *page, size_t size)
 
 #ifdef CONFIG_MMU
 #ifdef CONFIG_HUGETLB_PAGE
-#error ARM Coherent DMA allocator does not (yet) support huge TLB
+#warning ARM Coherent DMA allocator does not (yet) support huge TLB
 #endif
 
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
diff --git a/arch/arm/mm/fsr-3level.c b/arch/arm/mm/fsr-3level.c
index 05a4e94..e115fc7 100644
--- a/arch/arm/mm/fsr-3level.c
+++ b/arch/arm/mm/fsr-3level.c
@@ -13,7 +13,7 @@ static struct fsr_info fsr_info[] = {
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 access flag fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved permission fault"	},
 	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
-	{ do_sect_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 permission fault"	},
 	{ do_bad,		SIGBUS,  0,		"synchronous external abort"	},
 	{ do_bad,		SIGBUS,  0,		"asynchronous external abort"	},
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
new file mode 100644
index 0000000..3d1e4a2
--- /dev/null
+++ b/arch/arm/mm/hugetlbpage.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h and Bill Carson's patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+/*
+ * On ARM, huge pages are backed by pmd's rather than pte's, so we do a lot
+ * of type casting from pmd_t * to pte_t *.
+ */
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd = NULL;
+
+	pgd = pgd_offset(mm, addr);
+	if (pgd_present(*pgd)) {
+		pud = pud_offset(pgd, addr);
+		if (pud_present(*pud))
+			pmd = pmd_offset(pud, addr);
+	}
+
+	return (pte_t *)pmd;
+}
+
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+			      int write)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+int pud_huge(pud_t pud)
+{
+	return 0;
+}
+
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+	return 0;
+}
+
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+			unsigned long addr, unsigned long sz)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pte_t *pte = NULL;
+
+	pgd = pgd_offset(mm, addr);
+	pud = pud_alloc(mm, pgd, addr);
+	if (pud)
+		pte = (pte_t *)pmd_alloc(mm, pud, addr);
+
+	return pte;
+}
+
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+		pmd_t *pmd, int write)
+{
+	struct page *page;
+
+	page = pte_page(*(pte_t *)pmd);
+	if (page)
+		page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
+	return page;
+}
+
+int pmd_huge(pmd_t pmd)
+{
+	return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 11:31:20 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 16:31:20 +0100
Subject: [PATCH v2 4/4] ARM: mm: Transparent huge page support for LPAE
 systems.
In-Reply-To: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369323080-9673-5-git-send-email-steve.capper@linaro.org>

From: Catalin Marinas <catalin.marinas at arm.com>

The patch adds support for THP (transparent huge pages) to LPAE
systems. When this feature is enabled, the kernel tries to map
anonymous pages as 2MB sections where possible.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
[steve.capper at linaro.org: symbolic constants used, value of
PMD_SECT_SPLITTING adjusted, tlbflush.h included in pgtable.h,
added PROT_NONE support.]
Signed-off-by: Steve Capper <steve.capper at linaro.org>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig                            |  4 ++
 arch/arm/include/asm/pgtable-3level-hwdef.h |  2 +
 arch/arm/include/asm/pgtable-3level.h       | 60 +++++++++++++++++++++++++++++
 arch/arm/include/asm/pgtable.h              |  3 ++
 arch/arm/include/asm/tlb.h                  |  6 +++
 arch/arm/include/asm/tlbflush.h             |  2 +
 arch/arm/mm/fsr-3level.c                    |  2 +-
 7 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 860f034..f07a462 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1711,6 +1711,10 @@ config SYS_SUPPORTS_HUGETLBFS
        def_bool y
        depends on ARM_LPAE
 
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+       def_bool y
+       depends on ARM_LPAE
+
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 42df407..f088c86 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -42,6 +42,8 @@
  */
 #define PMD_SECT_BUFFERABLE	(_AT(pmdval_t, 1) << 2)
 #define PMD_SECT_CACHEABLE	(_AT(pmdval_t, 1) << 3)
+#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
+#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
 #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_nG		(_AT(pmdval_t, 1) << 11)
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index d1bcd82..54733e5 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -87,6 +87,11 @@
 #define L_PTE_SPECIAL		(_AT(pteval_t, 1) << 56)	/* unused */
 #define L_PTE_NONE		(_AT(pteval_t, 1) << 57)	/* PROT_NONE */
 
+#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_DIRTY		(_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING	(_AT(pmdval_t, 1) << 56)
+#define PMD_SECT_NONE		(_AT(pmdval_t, 1) << 57)
+
 /*
  * To be used in assembly code with the upper page attributes.
  */
@@ -196,6 +201,61 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 #define pte_huge(pte)		(pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
 #define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))
 
+#define pmd_young(pmd)		(pmd_val(pmd) & PMD_SECT_AF)
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)		(!(pmd_val(pmd) & PMD_SECT_RDONLY))
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)	(pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+
+PMD_BIT_FUNC(wrprotect,	|= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,	&= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+
+#define pmd_mkhuge(pmd)		(__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+
+#define pmd_pfn(pmd)		(((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)	(__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)	pfn_pmd(page_to_pfn(page),prot)
+
+/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
+#define pmd_mknotpresent(pmd)	(__pmd(0))
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+	const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
+				PMD_SECT_VALID | PMD_SECT_NONE;
+	pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+	return pmd;
+}
+
+static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+			      pmd_t *pmdp, pmd_t pmd)
+{
+	BUG_ON(addr >= TASK_SIZE);
+
+	/* create a faulting entry if PROT_NONE protected */
+	if (pmd_val(pmd) & PMD_SECT_NONE)
+		pmd_val(pmd) &= ~PMD_SECT_VALID;
+
+	*pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
+	flush_pmd_entry(pmdp);
+}
+
+static inline int has_transparent_hugepage(void)
+{
+	return 1;
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262..eaedce7 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -24,6 +24,9 @@
 #include <asm/memory.h>
 #include <asm/pgtable-hwdef.h>
 
+
+#include <asm/tlbflush.h>
+
 #ifdef CONFIG_ARM_LPAE
 #include <asm/pgtable-3level.h>
 #else
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 99a1951..bdc62da 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -223,6 +223,12 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 #endif
 }
 
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+	tlb_add_flush(tlb, addr);
+}
+
 #define pte_free_tlb(tlb, ptep, addr)	__pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)	__pmd_free_tlb(tlb, pmdp, addr)
 #define pud_free_tlb(tlb, pudp, addr)	pud_free((tlb)->mm, pudp)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d1..c374592 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -535,6 +535,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 }
 #endif
 
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
+
 #endif
 
 #endif /* CONFIG_MMU */
diff --git a/arch/arm/mm/fsr-3level.c b/arch/arm/mm/fsr-3level.c
index e115fc7..ab4409a 100644
--- a/arch/arm/mm/fsr-3level.c
+++ b/arch/arm/mm/fsr-3level.c
@@ -9,7 +9,7 @@ static struct fsr_info fsr_info[] = {
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved access flag fault"	},
 	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 access flag fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved permission fault"	},
 	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
-- 
1.8.1.4



From florian.vaussard at epfl.ch  Thu May 23 11:36:56 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 23 May 2013 17:36:56 +0200
Subject: [PATCH v2 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
Message-ID: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

Following a similar proposal by Stephen Warren for tegra [1], this series
makes use of the C preprocessor when compiling OMAP DT files, and
accomplishes some improvements to improve overall readability.

Patch 1 is a preparation for the rest of the series.
Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
it to simplify pinctrl DT.

For all targets, the .dtb files were diff-tested before and after
applying the series to guarantee identity.

Best regards,

Florian

>From v1:
- Remove duplicated fix
- Remove OMAP_GPIO macro
- Add pinctrl constants

Florian Vaussard (5):
  ARM: dts: OMAP2+: use #include for all device trees
  ARM: dts: OMAP2+: use existing constants for GPIOs
  ARM: dts: OMAP4/5: use existing constants for IRQs
  ARM: dts: OMAP2+: header file for pinctrl constants
  ARM: dts: OMAP2+: use pinctrl constants

 arch/arm/boot/dts/omap2.dtsi              |    5 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    8 +-
 arch/arm/boot/dts/omap3-beagle.dts        |   34 ++++----
 arch/arm/boot/dts/omap3-devkit8000.dts    |   10 +-
 arch/arm/boot/dts/omap3-evm.dts           |    6 +-
 arch/arm/boot/dts/omap3-igep.dtsi         |   36 ++++----
 arch/arm/boot/dts/omap3-igep0020.dts      |   10 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |   10 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 +-
 arch/arm/boot/dts/omap3-tobi.dts          |    4 +-
 arch/arm/boot/dts/omap3.dtsi              |    5 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 +-
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |   10 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   66 ++++++++--------
 arch/arm/boot/dts/omap4-panda-es.dts      |   10 +-
 arch/arm/boot/dts/omap4-panda.dts         |    4 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |  122 ++++++++++++++--------------
 arch/arm/boot/dts/omap4-var-som.dts       |    8 +-
 arch/arm/boot/dts/omap4.dtsi              |  118 ++++++++++++++-------------
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    6 +-
 arch/arm/boot/dts/omap5-evm.dts           |   92 +++++++++++-----------
 arch/arm/boot/dts/omap5.dtsi              |  126 +++++++++++++++--------------
 include/dt-bindings/pinctrl/omap.h        |   54 ++++++++++++
 30 files changed, 420 insertions(+), 352 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/omap.h

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 23 11:37:00 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 23 May 2013 17:37:00 +0200
Subject: [PATCH v2 4/5] ARM: dts: OMAP2+: header file for pinctrl constants
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369323421-4180-5-git-send-email-florian.vaussard@epfl.ch>

Most of the constants are taken from arch/arm/mach-omap2/mux.h.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 include/dt-bindings/pinctrl/omap.h |   54 ++++++++++++++++++++++++++++++++++++
 1 files changed, 54 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/omap.h

diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
new file mode 100644
index 0000000..253ce95
--- /dev/null
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -0,0 +1,54 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define OMAP_MUX_MODE0      0
+#define OMAP_MUX_MODE1      1
+#define OMAP_MUX_MODE2      2
+#define OMAP_MUX_MODE3      3
+#define OMAP_MUX_MODE4      4
+#define OMAP_MUX_MODE5      5
+#define OMAP_MUX_MODE6      6
+#define OMAP_MUX_MODE7      7
+
+/* 24xx/34xx mux bit defines */
+#define OMAP_PULL_ENA			(1 << 3)
+#define OMAP_PULL_UP			(1 << 4)
+#define OMAP_ALTELECTRICALSEL		(1 << 5)
+
+/* 34xx specific mux bit defines */
+#define OMAP_INPUT_EN			(1 << 8)
+#define OMAP_OFF_EN			(1 << 9)
+#define OMAP_OFFOUT_EN			(1 << 10)
+#define OMAP_OFFOUT_VAL			(1 << 11)
+#define OMAP_OFF_PULL_EN		(1 << 12)
+#define OMAP_OFF_PULL_UP		(1 << 13)
+#define OMAP_WAKEUP_EN			(1 << 14)
+
+/* 44xx specific mux bit defines */
+#define OMAP_WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define OMAP_PIN_OUTPUT			0
+#define OMAP_PIN_OUTPUT_PULLUP		(OMAP_PIN_OUTPUT | OMAP_PULL_ENA \
+						| OMAP_PULL_UP)
+#define OMAP_PIN_OUTPUT_PULLDOWN	(OMAP_PIN_OUTPUT | OMAP_PULL_ENA)
+#define OMAP_PIN_INPUT			OMAP_INPUT_EN
+#define OMAP_PIN_INPUT_PULLUP		(OMAP_PULL_ENA | OMAP_INPUT_EN \
+						| OMAP_PULL_UP)
+#define OMAP_PIN_INPUT_PULLDOWN		(OMAP_PULL_ENA | OMAP_INPUT_EN)
+
+/* Off mode states */
+#define OMAP_PIN_OFF_NONE		0
+#define OMAP_PIN_OFF_OUTPUT_HIGH	(OMAP_OFF_EN | OMAP_OFFOUT_EN \
+						| OMAP_OFFOUT_VAL)
+#define OMAP_PIN_OFF_OUTPUT_LOW		(OMAP_OFF_EN | OMAP_OFFOUT_EN)
+#define OMAP_PIN_OFF_INPUT_PULLUP	(OMAP_OFF_EN | OMAP_OFF_PULL_EN \
+						| OMAP_OFF_PULL_UP)
+#define OMAP_PIN_OFF_INPUT_PULLDOWN	(OMAP_OFF_EN | OMAP_OFF_PULL_EN)
+#define OMAP_PIN_OFF_WAKEUPENABLE	OMAP_WAKEUP_EN
+
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 23 11:36:58 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 23 May 2013 17:36:58 +0200
Subject: [PATCH v2 2/5] ARM: dts: OMAP2+: use existing constants for GPIOs
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369323421-4180-3-git-send-email-florian.vaussard@epfl.ch>

Use standard GPIO constants to enhance the readability of DT GPIOs.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 ++
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    6 +++---
 arch/arm/boot/dts/omap3-devkit8000.dts    |    6 +++---
 arch/arm/boot/dts/omap3-evm.dts           |    2 +-
 arch/arm/boot/dts/omap3-igep0020.dts      |    8 ++++----
 arch/arm/boot/dts/omap3-igep0030.dts      |    8 ++++----
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 ++
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-sdp.dts           |   16 ++++++++--------
 arch/arm/boot/dts/omap4.dtsi              |    2 ++
 arch/arm/boot/dts/omap5.dtsi              |    2 ++
 13 files changed, 36 insertions(+), 28 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index e6e4587..f39b237 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index e0ce823..1e580d9 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -29,13 +29,13 @@
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index fcac96a..434288f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -28,18 +28,18 @@
 		compatible = "gpio-leds";
 		pmu_stat {
 			label = "beagleboard::pmu_stat";
-			gpios = <&twl_gpio 19 0>; /* LEDB */
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 		};
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8d0f5e4..5be71b1 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -22,21 +22,21 @@
 
 		heartbeat {
 			label = "devkit8000::led1";
-			gpios = <&gpio6 26 0>;	/* 186 -> LED1 */
+			gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;	/* 186 -> LED1 */
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "devkit8000::led2";
-			gpios = <&gpio6 3 0>;	/* 163 -> LED2 */
+			gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;	/* 163 -> LED2 */
 			default-state = "on";
 			linux,default-trigger = "none";
 		};
 
 		usr {
 			label = "devkit8000::led3";
-			gpios = <&gpio6 4 0>;	/* 164 -> LED3 */
+			gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;	/* 164 -> LED3 */
 			default-state = "on";
 			linux,default-trigger = "usr";
                 };
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index d75759b..baa24bb 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -28,7 +28,7 @@
 		compatible = "gpio-leds";
 		ledb {
 			label = "omap3evm::ledb";
-			gpios = <&twl_gpio 19 0>; /* LEDB */
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 			linux,default-trigger = "default-on";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 2f96a5c..659e57c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -19,25 +19,25 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&gpio1 26 0>;
+			 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&gpio1 27 0>;
+			 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 28 0>;
+			 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 			 default-state = "off";
 		};
 
 		user2 {
 			label = "omap3:green:user1";
-			gpios = <&twl_gpio 19 1>;
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index f3a1bf0..8d3baef 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -19,25 +19,25 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&twl_gpio 13 1>;
+			 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&twl_gpio 18 1>; /* LEDA */
+			 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:green:user1";
-			 gpios = <&twl_gpio 19 1>; /* LEDB */
+			 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
 			 default-state = "off";
 		};
 
 		user2 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 16 1>;
+			 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 			 default-state = "off";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 5df894f..c7eebbf 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -20,7 +20,7 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "overo:red:gpio21";
-			gpios = <&gpio1 21 0>;
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7c7d494..aede64d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 63148d1..a3ef2bd 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -20,13 +20,13 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "pandaboard::status1";
-			gpios = <&gpio1 7 0>;
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "pandaboard::status2";
-			gpios = <&gpio1 8 0>;
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5edd08e..564d19b 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -41,42 +41,42 @@
 		compatible = "gpio-leds";
 		debug0 {
 			label = "omap4:green:debug0";
-			gpios = <&gpio2 29 0>; /* 61 */
+			gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
 		};
 
 		debug1 {
 			label = "omap4:green:debug1";
-			gpios = <&gpio1 30 0>; /* 30 */
+			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
 		};
 
 		debug2 {
 			label = "omap4:green:debug2";
-			gpios = <&gpio1 7 0>; /* 7 */
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
 		};
 
 		debug3 {
 			label = "omap4:green:debug3";
-			gpios = <&gpio1 8 0>; /* 8 */
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
 		};
 
 		debug4 {
 			label = "omap4:green:debug4";
-			gpios = <&gpio2 18 0>; /* 50 */
+			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
 		};
 
 		user1 {
 			label = "omap4:blue:user";
-			gpios = <&gpio6 9 0>; /* 169 */
+			gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
 		};
 
 		user2 {
 			label = "omap4:red:user";
-			gpios = <&gpio6 10 0>; /* 170 */
+			gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
 		};
 
 		user3 {
 			label = "omap4:green:user";
-			gpios = <&gpio5 11 0>; /* 139 */
+			gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 53d80aa..00f6ab9 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,6 +14,8 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e8e6653..d613bf5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -15,6 +15,8 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 23 11:36:57 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 23 May 2013 17:36:57 +0200
Subject: [PATCH v2 1/5] ARM: dts: OMAP2+: use #include for all device trees
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369323421-4180-2-git-send-email-florian.vaussard@epfl.ch>

Replace /include/ by #include for OMAP2+ DT, in order to use the
C pre-processor, making use of #define features possible.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    4 ++--
 arch/arm/boot/dts/omap3-devkit8000.dts    |    4 ++--
 arch/arm/boot/dts/omap3-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap3-igep.dtsi         |    4 ++--
 arch/arm/boot/dts/omap3-igep0020.dts      |    2 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |    2 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 ++--
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 ++--
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-panda-es.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda.dts         |    4 ++--
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    2 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +++---
 arch/arm/boot/dts/omap4-var-som.dts       |    4 ++--
 arch/arm/boot/dts/omap4.dtsi              |    2 +-
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    2 +-
 arch/arm/boot/dts/omap5-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap5.dtsi              |    2 +-
 29 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..e6e4587 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee..224c08f 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 
 / {
 	model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285..c8f9c55 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc44..c535a5a 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..e0ce823 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard xM";
@@ -75,7 +75,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..fcac96a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard";
@@ -107,7 +107,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc..8d0f5e4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
 	model = "TimLL OMAP3 Devkit8000";
 	compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -80,7 +80,7 @@
 	status = "disabled";
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c20..d75759b 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -44,7 +44,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index f8fe3b7..54588b0 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	memory {
@@ -80,7 +80,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e2b9849..2f96a5c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEPv2";
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 9dc48d2..f3a1bf0 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEP COM Module";
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50..e112a42 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	pwmleds {
@@ -49,7 +49,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 /* i2c2 pins are used for gpio */
 &i2c2 {
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12d..5df894f 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 
 / {
 	model = "TI OMAP3 Gumstix Overo on Tobi";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..7c7d494 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap3430", "ti,omap3";
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43..2a725a0 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3430 SDP";
@@ -28,7 +28,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae..5355d61 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc..f8b3765 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0..f18fb5c 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..63148d1 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 PandaBoard";
@@ -164,7 +164,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c6f012e 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f..6189a8b 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ff..4f26355 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd..5edd08e 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 SDP board";
@@ -316,7 +316,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103..6593607 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 
 / {
 	model = "Variscite OMAP4 SOM";
@@ -39,7 +39,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..53d80aa 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,7 +14,7 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..a81f8df 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..41762c2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 982acd1..f5f55d1 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
+#include "omap5.dtsi"
+#include "samsung_k3pe0e000b.dtsi"
 
 / {
 	model = "TI OMAP5 EVM board";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..e8e6653 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -15,7 +15,7 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	#address-cells = <1>;
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 23 11:37:01 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 23 May 2013 17:37:01 +0200
Subject: [PATCH v2 5/5] ARM: dts: OMAP2+: use pinctrl constants
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369323421-4180-6-git-send-email-florian.vaussard@epfl.ch>

Using constants for pinctrl allows a better readability, and remove
redundancy with comments.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap2.dtsi              |    1 +
 arch/arm/boot/dts/omap3-beagle.dts        |   24 ++++----
 arch/arm/boot/dts/omap3-igep.dtsi         |   32 +++++-----
 arch/arm/boot/dts/omap3.dtsi              |    1 +
 arch/arm/boot/dts/omap4-panda-a4.dts      |    6 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   50 ++++++++--------
 arch/arm/boot/dts/omap4-panda-es.dts      |    6 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    6 +-
 arch/arm/boot/dts/omap4-sdp.dts           |   94 ++++++++++++++--------------
 arch/arm/boot/dts/omap4.dtsi              |    1 +
 arch/arm/boot/dts/omap5-evm.dts           |   88 +++++++++++++-------------
 arch/arm/boot/dts/omap5.dtsi              |    1 +
 12 files changed, 157 insertions(+), 153 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index f39b237..b3cc896 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 434288f..2518e6a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -81,18 +81,18 @@
 
 	hsusbb2_pins: pinmux_hsusbb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
-			0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
-			0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
-			0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
-			0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
-			0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
-			0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
-			0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
-			0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
-			0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
-			0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
-			0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+			0x5c0 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk */
+			0x5c2 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp */
+			0x5c4 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir */
+			0x5c6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt */
+			0x5c8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 */
+			0x5cA (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 */
+			0x1a4 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 */
+			0x1a6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 */
+			0x1a8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 */
+			0x1aa (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 */
+			0x1ac (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 */
+			0x1ae (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 54588b0..6211564 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -29,37 +29,37 @@
 &omap3_pmx_core {
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			0x152 0x100	/* uart1_rx.uart1_rx INPUT | MODE0 */
-			0x14c 0		/* uart1_tx.uart1_tx OUTPUT | MODE0 */
+			0x152 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* uart1_rx.uart1_rx */
+			0x14c (OMAP_PIN_OUTPUT |OMAP_MUX_MODE0)		/* uart1_tx.uart1_tx */
 		>;
 	};
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			0x14a 0x100	/* uart2_rx.uart2_rx INPUT | MODE0 */
-			0x148 0		/* uart2_tx.uart2_tx OUTPUT | MODE0 */
+			0x14a (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* uart2_rx.uart2_rx */
+			0x148 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* uart2_tx.uart2_tx */
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			0x16e 0x100	/* uart3_rx.uart3_rx INPUT | MODE0 */
-			0x170 0		/* uart3_tx.uart3_tx OUTPUT | MODE0 */
+			0x16e (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* uart3_rx.uart3_rx */
+			0x170 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* uart3_tx.uart3_tx */
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			0x114 0x0118    /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
-			0x116 0x0118    /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
-			0x118 0x0118 	/* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
-			0x11a 0x0118	/* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
-			0x11c 0x0118	/* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
-			0x11e 0x0118	/* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
-			0x120 0x0100	/* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
-			0x122 0x0100	/* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
-			0x124 0x0100	/* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
-			0x126 0x0100	/* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
+			0x114 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			0x116 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
+			0x118 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0) 	/* sdmmc1_dat0.sdmmc1_dat0 */
+			0x11a (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
+			0x11c (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
+			0x11e (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
+			0x120 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* sdmmc1_dat4.sdmmc1_dat4 */
+			0x122 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* sdmmc1_dat5.sdmmc1_dat5 */
+			0x124 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* sdmmc1_dat6.sdmmc1_dat6 */
+			0x126 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* sdmmc1_dat7.sdmmc1_dat7 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index aede64d..813370d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index f18fb5c..dbaf0f4 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -13,8 +13,8 @@
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 16b03fd..266a113 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -68,71 +68,71 @@
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-			0x160 0x100	/* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+			0xe0 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)	/* hdq_sio.gpio_127 */
+			0x160 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* sys_nirq2.sys_nirq2 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0xc6 0x108	/* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-			0xc8 0x108	/* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-			0xca 0x118	/* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-			0xcc 0x108	/* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-			0xce 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+			0xc6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_pdm_ul_data.abe_pdm_ul_data */
+			0xc8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_pdm_dl_data.abe_pdm_dl_data */
+			0xca (OMAP_PIN_INPUT_PULLUP   | OMAP_MUX_MODE0)	/* abe_pdm_frame.abe_pdm_frame */
+			0xcc (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_pdm_lb_clk.abe_pdm_lb_clk */
+			0xce (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_clks.abe_clks */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0xbe 0x100	/* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-			0xc0 0x108	/* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-			0xc2 0x8		/* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-			0xc4 0x100	/* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+			0xbe (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+			0xc0 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)		/* abe_mcbsp1_dr.abe_mcbsp1_dr */
+			0xc2 (OMAP_PIN_OUTPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
+			0xc4 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
 		>;
 	};
 
 	dss_hdmi_pins: pinmux_dss_hdmi_pins {
 		pinctrl-single,pins = <
-			0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-			0x5c 0x118	/* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-			0x5e 0x118	/* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+			0x5a (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+			0x5c (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_scl.hdmi_scl */
+			0x5e (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_sda.hdmi_sda */
 		>;
 	};
 
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
-			0x22 0x3	/* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-			0x48 0x3	/* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-			0x58 0x10b	/* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+			0x22 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* gpmc_a17.gpio_41 */
+			0x48 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* gpmc_nbe1.gpio_60 */
+			0x58 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* hdmi_hpd.gpio_63 */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe2 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c1_scl */
+			0xe4 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c1_sda */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe6 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c2_scl */
+			0xe8 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-			0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+			0xea (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c3_scl */
+			0xec (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+			0xee (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c4_scl */
+			0xf0 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index c6f012e..5f98e63 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -29,8 +29,8 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index 4f26355..f241513 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -10,8 +10,8 @@
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 509e27c..a2d3164 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -156,123 +156,123 @@
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			0xd8 0x118	/* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
-			0xda 0		/* uart2_rts.uart2_rts OUTPUT | MODE0 */
-			0xdc 0x118	/* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
-			0xde 0		/* uart2_tx.uart2_tx OUTPUT | MODE0 */
+			0xd8 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* uart2_cts.uart2_cts */
+			0xda (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)		/* uart2_rts.uart2_rts */
+			0xdc (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* uart2_rx.uart2_rx */
+			0xde (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)		/* uart2_tx.uart2_tx */
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			0x100 0x118	/* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
-			0x102 0		/* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
-			0x104 0x100	/* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
-			0x106 0		/* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+			0x100 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* uart3_cts_rctx.uart3_cts_rctx */
+			0x102 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* uart3_rts_sd.uart3_rts_sd */
+			0x104 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* uart3_rx_irrx.uart3_rx_irrx */
+			0x106 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* uart3_tx_irtx.uart3_tx_irtx */
 		>;
 	};
 
 	uart4_pins: pinmux_uart4_pins {
 		pinctrl-single,pins = <
-			0x11c 0x100	/* uart4_rx.uart4_rx INPUT | MODE0 */
-			0x11e 0		/* uart4_tx.uart4_tx OUTPUT | MODE0 */
+			0x11c (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* uart4_rx.uart4_rx */
+			0x11e (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* uart4_tx.uart4_tx */
 		>;
 	};
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-			0x160 0x100	/* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+			0xe0 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* hdq_sio.gpio_127 */
+			0x160 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* sys_nirq2.sys_nirq2 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0xc6 0x108	/* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-			0xc8 0x108	/* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-			0xca 0x118	/* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-			0xcc 0x108	/* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-			0xce 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+			0xc6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_pdm_ul_data.abe_pdm_ul_data */
+			0xc8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_pdm_dl_data.abe_pdm_dl_data */
+			0xca (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* abe_pdm_frame.abe_pdm_frame */
+			0xcc (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_pdm_lb_clk.abe_pdm_lb_clk */
+			0xce (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_clks.abe_clks */
 		>;
 	};
 
 	dmic_pins: pinmux_dmic_pins {
 		pinctrl-single,pins = <
-			0xd0 0		/* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
-			0xd2 0x100	/* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
-			0xd4 0x100	/* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
-			0xd6 0x100	/* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+			0xd0 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* abe_dmic_clk1.abe_dmic_clk1 */
+			0xd2 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* abe_dmic_din1.abe_dmic_din1 */
+			0xd4 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* abe_dmic_din2.abe_dmic_din2 */
+			0xd6 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* abe_dmic_din3.abe_dmic_din3 */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0xbe 0x100	/* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-			0xc0 0x108	/* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-			0xc2 0x8	/* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-			0xc4 0x100	/* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+			0xbe (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+			0xc0 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)		/* abe_mcbsp1_dr.abe_mcbsp1_dr */
+			0xc2 (OMAP_PIN_OUTPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
+			0xc4 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
 		>;
 	};
 
 	mcbsp2_pins: pinmux_mcbsp2_pins {
 		pinctrl-single,pins = <
-			0xb6 0x100	/* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
-			0xb8 0x108	/* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
-			0xba 0x8	/* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-			0xbc 0x100	/* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+			0xb6 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+			0xb8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)		/* abe_mcbsp2_dr.abe_mcbsp2_dr */
+			0xba (OMAP_PIN_OUTPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_mcbsp2_dx.abe_mcbsp2_dx */
+			0xbc (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
 		>;
 	};
 
 	mcspi1_pins: pinmux_mcspi1_pins {
 		pinctrl-single,pins = <
-			0xf2 0x100	/*  mcspi1_clk.mcspi1_clk INPUT | MODE0 */
-			0xf4 0x100	/*  mcspi1_somi.mcspi1_somi INPUT | MODE0 */
-			0xf6 0x100	/*  mcspi1_simo.mcspi1_simo INPUT | MODE0 */
-			0xf8 0x100	/*  mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/
+			0xf2 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/*  mcspi1_clk.mcspi1_clk */
+			0xf4 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/*  mcspi1_somi.mcspi1_somi */
+			0xf6 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/*  mcspi1_simo.mcspi1_simo */
+			0xf8 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/*  mcspi1_cs0.mcspi1_cs0 */
 		>;
 	};
 
 	dss_hdmi_pins: pinmux_dss_hdmi_pins {
 		pinctrl-single,pins = <
-			0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-			0x5c 0x118	/* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-			0x5e 0x118	/* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+			0x5a (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+			0x5c (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_scl.hdmi_scl */
+			0x5e (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* hdmi_sda.hdmi_sda */
 		>;
 	};
 
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
-			0x22 0x3	/* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-			0x48 0x3	/* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-			0x58 0x10b	/* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+			0x22 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* gpmc_a17.gpio_41 */
+			0x48 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* gpmc_nbe1.gpio_60 */
+			0x58 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* hdmi_hpd.gpio_63 */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe4 0x118       /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe2 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c1_scl */
+			0xe4 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c1_sda */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe6 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c2_scl */
+			0xe8 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-			0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+			0xea (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c3_scl */
+			0xec (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+			0xee (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c4_scl */
+			0xf0 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d4304a2..ebf3108 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -16,6 +16,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index f5f55d1..184f9db 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -40,106 +40,106 @@
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0x18a 0x6	/* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
+			0x18a (OMAP_PIN_OUTPUT | OMAP_MUX_MODE6)	/* perslimbus2_clock.gpio5_145 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0x142 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
-			0x15c 0x108	/* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
-			0x15e 0x108	/* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
-			0x160 0x118	/* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
-			0x162 0x108	/* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
+			0x142 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abe_clks.abe_clks */
+			0x15c (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abemcpdm_ul_data.abemcpdm_ul_data */
+			0x15e (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abemcpdm_dl_data.abemcpdm_dl_data */
+			0x160 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)		/* abemcpdm_frame.abemcpdm_frame */
+			0x162 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abemcpdm_lb_clk.abemcpdm_lb_clk */
 		>;
 	};
 
 	dmic_pins: pinmux_dmic_pins {
 		pinctrl-single,pins = <
-			0x144 0x100	/* abedmic_din1.abedmic_din1 INPUT | MODE0 */
-			0x146 0x100	/* abedmic_din2.abedmic_din2 INPUT | MODE0 */
-			0x148 0x100	/* abedmic_din3.abedmic_din3 INPUT | MODE0 */
-			0x14a 0		/* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
+			0x144 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* abedmic_din1.abedmic_din1 */
+			0x146 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* abedmic_din2.abedmic_din2 */
+			0x148 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/* abedmic_din3.abedmic_din3 */
+			0x14a (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)	/* abedmic_clk1.abedmic_clk1 */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0x14c 0x101	/* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
-			0x14e 0x9	/* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
-			0x150 0x101	/* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
-			0x152 0x109	/* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
+			0x14c (OMAP_PIN_INPUT | OMAP_MUX_MODE1)			/* abedmic_clk2.abemcbsp1_fsx */
+			0x14e (OMAP_PIN_OUTPUT_PULLDOWN | OMAP_MUX_MODE1)	/* abedmic_clk3.abemcbsp1_dx */
+			0x150 (OMAP_PIN_INPUT | OMAP_MUX_MODE1)			/* abeslimbus1_clock.abemcbsp1_clkx */
+			0x152 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE1)	/* abeslimbus1_data.abemcbsp1_dr */
 		>;
 	};
 
 	mcbsp2_pins: pinmux_mcbsp2_pins {
 		pinctrl-single,pins = <
-			0x154 0x108	/* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
-			0x156 0x8	/* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-			0x158 0x100	/* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
-			0x15a 0x100	/* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
+			0x154 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abemcbsp2_dr.abemcbsp2_dr */
+			0x156 (OMAP_PIN_OUTPUT_PULLDOWN | OMAP_MUX_MODE0)	/* abemcbsp2_dx.abemcbsp2_dx */
+			0x158 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abemcbsp2_fsx.abemcbsp2_fsx */
+			0x15a (OMAP_PIN_INPUT | OMAP_MUX_MODE0)			/* abemcbsp2_clkx.abemcbsp2_clkx */
 		>;
 	};
 
-        i2c1_pins: pinmux_i2c1_pins {
-                pinctrl-single,pins = <
-                        0x1b2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0x1b4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
-                >;
-        };
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x1b2 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c1_scl */
+			0x1b4 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/* i2c1_sda */
+		>;
+	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			0x178 0x100        /* i2c2_scl INPUTENABLE | MODE0 */
-			0x17a 0x100        /* i2c2_sda INPUTENABLE | MODE0 */
+			0x178 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c2_scl */
+			0x17a (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0x13a 0x100        /* i2c3_scl INPUTENABLE | MODE0 */
-			0x13c 0x100     /* i2c3_sda INPUTENABLE | MODE0 */
+			0x13a (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c3_scl */
+			0x13c (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xb8 0x100        /* i2c4_scl INPUTENABLE | MODE0 */
-			0xba 0x100     /* i2c4_sda INPUTENABLE | MODE0 */
+			0xb8 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c4_scl */
+			0xba (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 
 	i2c5_pins: pinmux_i2c5_pins {
 		pinctrl-single,pins = <
-			0x184 0x100        /* i2c5_scl INPUTENABLE | MODE0 */
-			0x186 0x100     /* i2c5_sda INPUTENABLE | MODE0 */
+			0x184 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c5_scl */
+			0x186 (OMAP_PIN_INPUT | OMAP_MUX_MODE0)	/* i2c5_sda */
 		>;
 	};
 
 	mcspi2_pins: pinmux_mcspi2_pins {
 		pinctrl-single,pins = <
-			0xbc 0x100	/*  MCSPI2_CLK INPUTENABLE | MODE0 */
-			0xbe 0x100	/*  MCSPI2_SIMO INPUTENABLE | MODE0 */
-			0xc0 0x118	/*  MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
-			0xc2 0x0	/*  MCSPI2_CS MODE0*/
+			0xbc (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/*  MCSPI2_CLK */
+			0xbe (OMAP_PIN_INPUT | OMAP_MUX_MODE0)		/*  MCSPI2_SIMO */
+			0xc0 (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0)	/*  MCSPI2_SOMI */
+			0xc2 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0)		/*  MCSPI2_CS */
 		>;
 	};
 
 	mcspi3_pins: pinmux_mcspi3_pins {
 		pinctrl-single,pins = <
-			0x78 0x101	/*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-			0x7a 0x101	/*  MCSPI2_CS INPUTENABLE | MODE1 */
-			0x7c 0x101	/*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-			0x7e 0x101	/*  MCSPI2_CLK INPUTENABLE | MODE1 */
+			0x78 (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_SOMI */
+			0x7a (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_CS */
+			0x7c (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_SIMO */
+			0x7e (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_CLK */
 		>;
 	};
 
 	mcspi4_pins: pinmux_mcspi4_pins {
 		pinctrl-single,pins = <
-			0x164 0x101	/*  MCSPI2_CLK INPUTENABLE | MODE1 */
-			0x168 0x101	/*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-			0x16a 0x101	/*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-			0x16c 0x101	/*  MCSPI2_CS INPUTENABLE | MODE1 */
+			0x164 (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_CLK */
+			0x168 (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_SIMO */
+			0x16a (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_SOMI */
+			0x16c (OMAP_PIN_INPUT | OMAP_MUX_MODE1)	/*  MCSPI2_CS */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 061cf70..825ce300 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -17,6 +17,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 23 11:36:59 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 23 May 2013 17:36:59 +0200
Subject: [PATCH v2 3/5] ARM: dts: OMAP4/5: use existing constants for IRQs
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369323421-4180-4-git-send-email-florian.vaussard@epfl.ch>

Use the constants defined in include/dt-bindings/interrupt-controller/
to enhance readability.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +-
 arch/arm/boot/dts/omap4-var-som.dts       |    4 +-
 arch/arm/boot/dts/omap4.dtsi              |  113 ++++++++++++++-------------
 arch/arm/boot/dts/omap4460.dtsi           |    4 +-
 arch/arm/boot/dts/omap5.dtsi              |  121 +++++++++++++++--------------
 6 files changed, 129 insertions(+), 127 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index a3ef2bd..16b03fd 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -145,16 +145,16 @@
 
 	twl: twl at 48 {
 		reg = <0x48>;
-		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		/* IRQ# = 7 */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
 	twl6040: twl at 4b {
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
-		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		/* IRQ# = 119 */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 564d19b..509e27c 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -286,7 +286,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
@@ -294,7 +294,7 @@
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
@@ -375,7 +375,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <2 8>; /* gpio line 34, low triggered */
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34, low triggered */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6593607..135ba45 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -34,7 +34,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 };
@@ -68,7 +68,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <11 8>; /* gpio line 171, low triggered */
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171, low triggered */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 00f6ab9..d4304a2 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -15,6 +15,7 @@
 /memreserve/ 0x9d000000 0x03000000;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -58,7 +59,7 @@
 	local-timer at 0x48240600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x48240600 0x20>;
-		interrupts = <1 13 0x304>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	/*
@@ -99,8 +100,8 @@
 		reg = <0x44000000 0x1000>,
 		      <0x44800000 0x2000>,
 		      <0x45000000 0x1000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4a304000 {
 			compatible = "ti,omap-counter32k";
@@ -128,10 +129,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -140,7 +141,7 @@
 		gpio1: gpio at 4a310000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4a310000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -152,7 +153,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -163,7 +164,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -174,7 +175,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -185,7 +186,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -196,7 +197,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -209,7 +210,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -218,7 +219,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -226,7 +227,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -234,7 +235,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -242,7 +243,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -250,7 +251,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -259,7 +260,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -268,7 +269,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -277,7 +278,7 @@
 		i2c4: i2c at 48350000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48350000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -286,7 +287,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -306,7 +307,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -321,7 +322,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -333,7 +334,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -345,7 +346,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -356,7 +357,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -366,7 +367,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -376,7 +377,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -386,7 +387,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -396,7 +397,7 @@
 		wdt2: wdt at 4a314000 {
 			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 			reg = <0x4a314000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -405,7 +406,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -417,7 +418,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -428,7 +429,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -442,7 +443,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -456,7 +457,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -469,7 +470,7 @@
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */
 			reg-names = "mpu";
-			interrupts = <0 16 0x4>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp4";
@@ -481,7 +482,7 @@
 		keypad: keypad at 4a31c000 {
 			compatible = "ti,omap4-keypad";
 			reg = <0x4a31c000 0x80>;
-			interrupts = <0 120 0x4>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
 		};
@@ -489,7 +490,7 @@
 		emif1: emif at 4c000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4c000000 0x100>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif1";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -500,7 +501,7 @@
 		emif2: emif at 4d000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4d000000 0x100>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif2";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -525,7 +526,7 @@
 		timer1: timer at 4a318000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x4a318000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -533,21 +534,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -555,7 +556,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -564,7 +565,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 		};
@@ -573,7 +574,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -582,7 +583,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
@@ -591,7 +592,7 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
 		};
@@ -599,7 +600,7 @@
 		timer10: timer at 48086000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
 		};
@@ -607,7 +608,7 @@
 		timer11: timer at 48088000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -615,7 +616,7 @@
 		usbhstll: usbhstll at 4a062000 {
 			compatible = "ti,usbhs-tll";
 			reg = <0x4a062000 0x1000>;
-			interrupts = <0 78 0x4>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
 		};
 
@@ -631,14 +632,14 @@
 				compatible = "ti,ohci-omap3", "usb-ohci";
 				reg = <0x4a064800 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 76 0x4>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			usbhsehci: ehci at 4a064c00 {
 				compatible = "ti,ehci-omap", "usb-ehci";
 				reg = <0x4a064c00 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 77 0x4>;
+				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
 
@@ -653,7 +654,7 @@
 		usb_otg_hs: usb_otg_hs at 4a0ab000 {
 			compatible = "ti,omap4-musb";
 			reg = <0x4a0ab000 0x7ff>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 41762c2..19628b1 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -25,8 +25,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 54 0x4>,
-			     <0 55 0x4>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		ti,hwmods = "debugss";
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index d613bf5..061cf70 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -16,6 +16,7 @@
 /memreserve/ 0x9d000000 0x03000000;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -47,10 +48,10 @@
 	timer {
 		compatible = "arm,armv7-timer";
 		/* PPI secure/nonsecure IRQ, active low level-sensitive */
-		interrupts = <1 13 0x308>,
-			     <1 14 0x308>,
-			     <1 11 0x308>,
-			     <1 10 0x308>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <6144000>;
 	};
 
@@ -92,8 +93,8 @@
 		reg = <0x44000000 0x2000>,
 		      <0x44800000 0x3000>,
 		      <0x45000000 0x4000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
@@ -121,10 +122,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -133,7 +134,7 @@
 		gpio1: gpio at 4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -145,7 +146,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -156,7 +157,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -167,7 +168,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -178,7 +179,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -189,7 +190,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -200,7 +201,7 @@
 		gpio7: gpio at 48051000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48051000 0x200>;
-			interrupts = <0 35 0x4>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio7";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -211,7 +212,7 @@
 		gpio8: gpio at 48053000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48053000 0x200>;
-			interrupts = <0 121 0x4>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio8";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -224,7 +225,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -233,7 +234,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -242,7 +243,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -251,7 +252,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -260,7 +261,7 @@
 		i2c4: i2c at 4807a000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807a000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -269,7 +270,7 @@
 		i2c5: i2c at 4807c000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807c000 0x100>;
-			interrupts = <0 60 0x4>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c5";
@@ -278,7 +279,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -298,7 +299,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -313,7 +314,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -325,7 +326,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -337,7 +338,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -345,7 +346,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -353,7 +354,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -361,7 +362,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -369,7 +370,7 @@
 		uart5: serial at 48066000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48066000 0x100>;
-			interrupts = <0 105 0x4>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 		};
@@ -377,7 +378,7 @@
 		uart6: serial at 48068000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48068000 0x100>;
-			interrupts = <0 106 0x4>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 		};
@@ -385,7 +386,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -396,7 +397,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -406,7 +407,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -416,7 +417,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -426,7 +427,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -444,7 +445,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -456,7 +457,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -467,7 +468,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -481,7 +482,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -495,7 +496,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -507,7 +508,7 @@
 		timer1: timer at 4ae18000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4ae18000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -515,21 +516,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -537,7 +538,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -546,7 +547,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -556,7 +557,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -565,7 +566,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -574,21 +575,21 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 		};
 
 		timer10: timer at 48086000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 		};
 
 		timer11: timer at 48088000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -596,7 +597,7 @@
 		wdt2: wdt at 4ae14000 {
 			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 			reg = <0x4ae14000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -605,7 +606,7 @@
 			ti,hwmods	= "emif1";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4c000000 0x400>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -616,7 +617,7 @@
 			ti,hwmods	= "emif2";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4d000000 0x400>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -634,7 +635,7 @@
 			compatible = "ti,dwc3";
 			ti,hwmods = "usb_otg_ss";
 			reg = <0x4a020000 0x1000>;
-			interrupts = <0 93 4>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			utmi-mode = <2>;
@@ -642,7 +643,7 @@
 			dwc3 at 4a030000 {
 				compatible = "synopsys,dwc3";
 				reg = <0x4a030000 0x1000>;
-				interrupts = <0 92 4>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 				usb-phy = <&usb2_phy>, <&usb3_phy>;
 				tx-fifo-resize;
 			};
-- 
1.7.5.4



From b.brezillon at overkiz.com  Thu May 23 11:48:52 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 17:48:52 +0200
Subject: [PATCH v2 0/3] ARM: at91: move aic driver to drivers/irqchip
Message-ID: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>

Hello,

This patch series :
 - register the arch specific irq handler inside the the init functions
   using set_handle_irq. This way we can remove all the machine specific
   "handle_irq"
 - move the at91 AIC (Advance Interrupt Controller) driver to the 
   irqchip subsystem directory (drivers/irqchip)
 - make use of IRQCHIP_DECLARE to register irqchip for dt boards
   instead of using the machine specific "init_irq" function

This patch series was tested on kizbox board (sam9g20 SoC) using
device tree. Could someone test it on other boards (both dt and non dt)?

Changes since v1:
 - reorder patch (3rd patch is now applied first).
 - remove references to machine specific header (<mach/at91_aic.h>).

Maybe we should cleanup include/linux/irqchip/at91.h
(as suggested by Russel).
Currently, the only MACROs needed outside of irq-at91.c are:
 - pm.c : at91_aic_read, AT91_AIC_IMR and AT91_AIC_IPR
 - at91xxx.c : NR_AICX_IRQS

Please let me know what you think is best.

Best Regards,
Boris

Boris BREZILLON (3):
  ARM: at91: use set_handle_irq instead of machine specific handle_irq
  ARM: at91: move at91 aic driver to drivers/irqchip
  ARM: at91: use IRQCHIP_DECLARE instead of machine specific init_irq

 arch/arm/mach-at91/Makefile                        |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |    2 +-
 arch/arm/mach-at91/at91sam9261.c                   |    2 +-
 arch/arm/mach-at91/at91sam9263.c                   |    2 +-
 arch/arm/mach-at91/at91sam9g45.c                   |    2 +-
 arch/arm/mach-at91/at91sam9rl.c                    |    2 +-
 arch/arm/mach-at91/at91x40.c                       |    2 +-
 arch/arm/mach-at91/board-1arm.c                    |    3 +--
 arch/arm/mach-at91/board-afeb-9260v1.c             |    3 +--
 arch/arm/mach-at91/board-cam60.c                   |    3 +--
 arch/arm/mach-at91/board-carmeva.c                 |    3 +--
 arch/arm/mach-at91/board-cpu9krea.c                |    3 +--
 arch/arm/mach-at91/board-cpuat91.c                 |    3 +--
 arch/arm/mach-at91/board-csb337.c                  |    3 +--
 arch/arm/mach-at91/board-csb637.c                  |    3 +--
 arch/arm/mach-at91/board-dt-rm9200.c               |   14 +-------------
 arch/arm/mach-at91/board-dt-sam9.c                 |   15 +--------------
 arch/arm/mach-at91/board-dt-sama5.c                |   15 +--------------
 arch/arm/mach-at91/board-eb01.c                    |    3 +--
 arch/arm/mach-at91/board-eb9200.c                  |    3 +--
 arch/arm/mach-at91/board-ecbat91.c                 |    3 +--
 arch/arm/mach-at91/board-eco920.c                  |    3 +--
 arch/arm/mach-at91/board-flexibity.c               |    3 +--
 arch/arm/mach-at91/board-foxg20.c                  |    3 +--
 arch/arm/mach-at91/board-gsia18s.c                 |    3 +--
 arch/arm/mach-at91/board-kafa.c                    |    3 +--
 arch/arm/mach-at91/board-kb9202.c                  |    3 +--
 arch/arm/mach-at91/board-pcontrol-g20.c            |    3 +--
 arch/arm/mach-at91/board-picotux200.c              |    3 +--
 arch/arm/mach-at91/board-qil-a9260.c               |    3 +--
 arch/arm/mach-at91/board-rm9200dk.c                |    3 +--
 arch/arm/mach-at91/board-rm9200ek.c                |    3 +--
 arch/arm/mach-at91/board-rsi-ews.c                 |    3 +--
 arch/arm/mach-at91/board-sam9-l9260.c              |    3 +--
 arch/arm/mach-at91/board-sam9260ek.c               |    3 +--
 arch/arm/mach-at91/board-sam9261ek.c               |    3 +--
 arch/arm/mach-at91/board-sam9263ek.c               |    3 +--
 arch/arm/mach-at91/board-sam9g20ek.c               |    4 +---
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    3 +--
 arch/arm/mach-at91/board-sam9rlek.c                |    3 +--
 arch/arm/mach-at91/board-snapper9260.c             |    3 +--
 arch/arm/mach-at91/board-stamp9g20.c               |    4 +---
 arch/arm/mach-at91/board-usb-a926x.c               |    5 +----
 arch/arm/mach-at91/board-yl-9200.c                 |    3 +--
 arch/arm/mach-at91/generic.h                       |    5 -----
 arch/arm/mach-at91/pm.c                            |    2 +-
 drivers/irqchip/Makefile                           |    1 +
 .../mach-at91/irq.c => drivers/irqchip/irq-at91.c  |   14 ++++++++++++--
 .../at91_aic.h => include/linux/irqchip/at91.h     |    9 +--------
 50 files changed, 60 insertions(+), 137 deletions(-)
 rename arch/arm/mach-at91/irq.c => drivers/irqchip/irq-at91.c (97%)
 rename arch/arm/mach-at91/at91_aic.h => include/linux/irqchip/at91.h (95%)

-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 11:48:55 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 17:48:55 +0200
Subject: [PATCH v2 3/3] ARM: at91: use IRQCHIP_DECLARE instead of machine
 specific init_irq
In-Reply-To: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>
References: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369324135-31211-4-git-send-email-b.brezillon@overkiz.com>

Replace machine specific init_irq functions with IRQCHIP_DECLARE.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/board-dt-rm9200.c |   11 -----------
 arch/arm/mach-at91/board-dt-sam9.c   |   12 ------------
 arch/arm/mach-at91/board-dt-sama5.c  |   12 ------------
 arch/arm/mach-at91/generic.h         |    5 -----
 drivers/irqchip/irq-at91.c           |    4 ++++
 5 files changed, 4 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 67fff54..7ee7e5f 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -26,16 +26,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91rm9200_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static void __init at91rm9200_dt_device_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -50,7 +40,6 @@ DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.init_time      = at91rm9200_timer_init,
 	.map_io		= at91_map_io,
 	.init_early	= at91rm9200_dt_initialize,
-	.init_irq	= at91rm9200_dt_init_irq,
 	.init_machine	= at91rm9200_dt_device_init,
 	.dt_compat	= at91rm9200_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 65edc6e..e7aa089 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -26,17 +26,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static void __init at91_dt_device_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -52,7 +41,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 015178f..b3b6a1b 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -27,17 +27,6 @@
 #include "generic.h"
 
 
-static const struct of_device_id irq_of_match[] __initconst = {
-
-	{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
-	{ /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-	of_irq_init(irq_of_match);
-}
-
 static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
 	int value;
@@ -79,7 +68,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
 	.init_early	= at91_dt_initialize,
-	.init_irq	= at91_dt_init_irq,
 	.init_machine	= sama5_dt_device_init,
 	.dt_compat	= sama5_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..23077cf 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,11 +29,6 @@ extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[],
 				 unsigned int ext_irq_mask);
-extern int  __init at91_aic_of_init(struct device_node *node,
-				    struct device_node *parent);
-extern int  __init at91_aic5_of_init(struct device_node *node,
-				    struct device_node *parent);
-
 
  /* Timer */
 extern void at91rm9200_ioremap_st(u32 addr);
diff --git a/drivers/irqchip/irq-at91.c b/drivers/irqchip/irq-at91.c
index ca49096..137d428 100644
--- a/drivers/irqchip/irq-at91.c
+++ b/drivers/irqchip/irq-at91.c
@@ -43,6 +43,8 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
+#include "irqchip.h"
+
 
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
@@ -473,6 +475,7 @@ int __init at91_aic_of_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", at91_aic_of_init);
 
 int __init at91_aic5_of_init(struct device_node *node,
 				     struct device_node *parent)
@@ -497,6 +500,7 @@ int __init at91_aic5_of_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(sama5d3_aic, "atmel,sama5d3-aic", at91_aic5_of_init);
 #endif
 
 /*
-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 11:48:53 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 17:48:53 +0200
Subject: [PATCH v2 1/3] ARM: at91: use set_handle_irq instead of machine
 specific handle_irq
In-Reply-To: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>
References: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369324135-31211-2-git-send-email-b.brezillon@overkiz.com>

Set machine specific irq handler using set_handle_irq inside aic init
functions instead of handle_irq pointer from machine_desc.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/at91_aic.h           |    3 ---
 arch/arm/mach-at91/board-1arm.c         |    1 -
 arch/arm/mach-at91/board-afeb-9260v1.c  |    1 -
 arch/arm/mach-at91/board-cam60.c        |    1 -
 arch/arm/mach-at91/board-carmeva.c      |    1 -
 arch/arm/mach-at91/board-cpu9krea.c     |    1 -
 arch/arm/mach-at91/board-cpuat91.c      |    1 -
 arch/arm/mach-at91/board-csb337.c       |    1 -
 arch/arm/mach-at91/board-csb637.c       |    1 -
 arch/arm/mach-at91/board-dt-rm9200.c    |    1 -
 arch/arm/mach-at91/board-dt-sam9.c      |    1 -
 arch/arm/mach-at91/board-dt-sama5.c     |    1 -
 arch/arm/mach-at91/board-eb01.c         |    1 -
 arch/arm/mach-at91/board-eb9200.c       |    1 -
 arch/arm/mach-at91/board-ecbat91.c      |    1 -
 arch/arm/mach-at91/board-eco920.c       |    1 -
 arch/arm/mach-at91/board-flexibity.c    |    1 -
 arch/arm/mach-at91/board-foxg20.c       |    1 -
 arch/arm/mach-at91/board-gsia18s.c      |    1 -
 arch/arm/mach-at91/board-kafa.c         |    1 -
 arch/arm/mach-at91/board-kb9202.c       |    1 -
 arch/arm/mach-at91/board-pcontrol-g20.c |    1 -
 arch/arm/mach-at91/board-picotux200.c   |    1 -
 arch/arm/mach-at91/board-qil-a9260.c    |    1 -
 arch/arm/mach-at91/board-rm9200dk.c     |    1 -
 arch/arm/mach-at91/board-rm9200ek.c     |    1 -
 arch/arm/mach-at91/board-rsi-ews.c      |    1 -
 arch/arm/mach-at91/board-sam9-l9260.c   |    1 -
 arch/arm/mach-at91/board-sam9260ek.c    |    1 -
 arch/arm/mach-at91/board-sam9261ek.c    |    1 -
 arch/arm/mach-at91/board-sam9263ek.c    |    1 -
 arch/arm/mach-at91/board-sam9g20ek.c    |    2 --
 arch/arm/mach-at91/board-sam9m10g45ek.c |    1 -
 arch/arm/mach-at91/board-sam9rlek.c     |    1 -
 arch/arm/mach-at91/board-snapper9260.c  |    1 -
 arch/arm/mach-at91/board-stamp9g20.c    |    2 --
 arch/arm/mach-at91/board-usb-a926x.c    |    3 ---
 arch/arm/mach-at91/board-yl-9200.c      |    1 -
 arch/arm/mach-at91/irq.c                |    6 ++++++
 39 files changed, 6 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
index eaea661..be8680d 100644
--- a/arch/arm/mach-at91/at91_aic.h
+++ b/arch/arm/mach-at91/at91_aic.h
@@ -93,7 +93,4 @@ extern void __iomem *at91_aic_base;
 #define AT91_AIC_FFSR		0x148			/* Fast Forcing Status Register [SAM9 only] */
 #define AT91_AIC5_FFSR		0x58			/* Fast Forcing Status Register [AIC5] */
 
-void at91_aic_handle_irq(struct pt_regs *regs);
-void at91_aic5_handle_irq(struct pt_regs *regs);
-
 #endif
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632..8389e81 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -92,7 +92,6 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
 	/* Maintainer: Lennert Buytenhek <buytenh at wantstofly.org> */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= onearm_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= onearm_board_init,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31c..82832f1 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -212,7 +212,6 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board")
 	/* Maintainer: Sergey Lapin <slapin at ossfans.org> */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= afeb9260_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= afeb9260_board_init,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index ade948b..c1146d9 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -189,7 +189,6 @@ MACHINE_START(CAM60, "KwikByte CAM60")
 	/* Maintainer: KwikByte */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cam60_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cam60_board_init,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 9298305..c0aac79 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -159,7 +159,6 @@ MACHINE_START(CARMEVA, "Carmeva")
 	/* Maintainer: Conitec Datasystems */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= carmeva_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= carmeva_board_init,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527e..c8ddf60 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -376,7 +376,6 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 	/* Maintainer: Eric Benard - EUKREA Electromatique */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cpu9krea_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cpu9krea_board_init,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..b7675c8 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -180,7 +180,6 @@ MACHINE_START(CPUAT91, "Eukrea")
 	/* Maintainer: Eric Benard - EUKREA Electromatique */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= cpuat91_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= cpuat91_board_init,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215..746120d 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -253,7 +253,6 @@ MACHINE_START(CSB337, "Cogent CSB337")
 	/* Maintainer: Bill Gatliff */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= csb337_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= csb337_board_init,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf1106..c61f7d9 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -134,7 +134,6 @@ MACHINE_START(CSB637, "Cogent CSB637")
 	/* Maintainer: Bill Gatliff */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= csb637_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= csb637_board_init,
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb662..13d7c62 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -49,7 +49,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
 	.init_time      = at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91rm9200_dt_initialize,
 	.init_irq	= at91rm9200_dt_init_irq,
 	.init_machine	= at91rm9200_dt_device_init,
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db3013..4d291ae 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -51,7 +51,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91_dt_initialize,
 	.init_irq	= at91_dt_init_irq,
 	.init_machine	= at91_dt_device_init,
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..d39a459 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -78,7 +78,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic5_handle_irq,
 	.init_early	= at91_dt_initialize,
 	.init_irq	= at91_dt_init_irq,
 	.init_machine	= sama5_dt_device_init,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index becf0a6..8d84f46 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -45,7 +45,6 @@ static void __init at91eb01_init_early(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
 	/* Maintainer: Greg Ungerer <gerg at snapgear.com> */
 	.init_time	= at91x40_timer_init,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= at91eb01_init_early,
 	.init_irq	= at91eb01_init_irq,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be816..95a4a65 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -118,7 +118,6 @@ static void __init eb9200_board_init(void)
 MACHINE_START(ATEB9200, "Embest ATEB9200")
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= eb9200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= eb9200_board_init,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71..4bababc 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -183,7 +183,6 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
 	/* Maintainer: emQbit.com */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ecb_at91init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ecb_at91board_init,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..ba6c6f7 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -151,7 +151,6 @@ MACHINE_START(ECO920, "eco920")
 	/* Maintainer: Sascha Hauer */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= eco920_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= eco920_board_init,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c085..b9b1f59 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -161,7 +161,6 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect")
 	/* Maintainer: Maxim Osipov */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= flexibity_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= flexibity_board_init,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870..816db05 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -264,7 +264,6 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
 	/* Maintainer: Sergio Tanzilli */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= foxg20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= foxg20_board_init,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d2..af6a925 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -576,7 +576,6 @@ static void __init gsia18s_board_init(void)
 MACHINE_START(GSIA18S, "GS_IA18_S")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= gsia18s_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= gsia18s_board_init,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d..31bd8c9 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -105,7 +105,6 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA")
 	/* Maintainer: Sergei Sharonov */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= kafa_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= kafa_board_init,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..df43c2e 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -151,7 +151,6 @@ MACHINE_START(KB9200, "KB920x")
 	/* Maintainer: KwikByte, Inc. */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= kb9202_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= kb9202_board_init,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b..724c91b 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -219,7 +219,6 @@ MACHINE_START(PCONTROL_G20, "PControl G20")
 	/* Maintainer: pgsellmann at portner-elektronik.at */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= pcontrol_g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= pcontrol_g20_board_init,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..479a034 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -121,7 +121,6 @@ MACHINE_START(PICOTUX2XX, "picotux 200")
 	/* Maintainer: Kleinhenz Elektronik GmbH */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= picotux200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= picotux200_board_init,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index aa3bc9b..1d7a4e7 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -259,7 +259,6 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 690541b..cc04718 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -221,7 +221,6 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
 	/* Maintainer: SAN People/Atmel */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= dk_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= dk_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..13a121a 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -188,7 +188,6 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
 	/* Maintainer: SAN People/Atmel */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f19..d15ef0c 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -224,7 +224,6 @@ MACHINE_START(RSI_EWS, "RSI EWS")
 	/* Maintainer: Josef Holzmayr <holzmayr at rsi-elektrotechnik.de> */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= rsi_ews_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= rsi_ews_board_init,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc..0907df4 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -220,7 +220,6 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
 	/* Maintainer: Olimex */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0b153c8..0361c4d 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -345,7 +345,6 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b446645..c28401a 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -614,7 +614,6 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 3284df0..1287d81 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -445,7 +445,6 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2..c6ea31d 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -411,7 +411,6 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -421,7 +420,6 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 2a94896..139a67e 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -504,7 +504,6 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index aa265dc..fdcb1cc 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -322,7 +322,6 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
 	/* Maintainer: Atmel */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa978..c07e86a 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -179,7 +179,6 @@ static void __init snapper9260_board_init(void)
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= snapper9260_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= snapper9260_board_init,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbec..4977e6e 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -275,7 +275,6 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
 	/* Maintainer: taskit GmbH */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= stamp9g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= portuxg20_board_init,
@@ -285,7 +284,6 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
 	/* Maintainer: taskit GmbH */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= stamp9g20_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= stamp9g20evb_board_init,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 2487d94..a0f7d74 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -357,7 +357,6 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -367,7 +366,6 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260")
 	/* Maintainer: calao-systems */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
@@ -377,7 +375,6 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
 	/* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
 	.init_time	= at91sam926x_pit_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= ek_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= ek_board_init,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..ac3b263 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -589,7 +589,6 @@ MACHINE_START(YL9200, "uCdragon YL-9200")
 	/* Maintainer: S.Birtles */
 	.init_time	= at91rm9200_timer_init,
 	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
 	.init_early	= yl9200_init_early,
 	.init_irq	= at91_init_irq_default,
 	.init_machine	= yl9200_board_init,
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index e0ca591..18c653f 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -469,6 +469,8 @@ int __init at91_aic_of_init(struct device_node *node,
 
 	at91_aic_hw_init(n_irqs);
 
+	set_handle_irq(at91_aic_handle_irq);
+
 	return 0;
 }
 
@@ -491,6 +493,8 @@ int __init at91_aic5_of_init(struct device_node *node,
 
 	at91_aic5_hw_init(n_irqs);
 
+	set_handle_irq(at91_aic5_handle_irq);
+
 	return 0;
 }
 #endif
@@ -544,4 +548,6 @@ void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
 	}
 
 	at91_aic_hw_init(n_irqs);
+
+	set_handle_irq(at91_aic_handle_irq);
 }
-- 
1.7.9.5



From b.brezillon at overkiz.com  Thu May 23 11:48:54 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 17:48:54 +0200
Subject: [PATCH v2 2/3] ARM: at91: move at91 aic driver to drivers/irqchip
In-Reply-To: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>
References: <1369324135-31211-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1369324135-31211-3-git-send-email-b.brezillon@overkiz.com>

Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
Move arch/arm/mach-at91/at91_aic.h to include/linux/irqchip/at91.h to
avoid reference to machine specific hearder files.
Remove __ASSEMBLY__ section in header file (at91_aic_base is only used
in .c files).

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/mach-at91/Makefile                        |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |    2 +-
 arch/arm/mach-at91/at91sam9261.c                   |    2 +-
 arch/arm/mach-at91/at91sam9263.c                   |    2 +-
 arch/arm/mach-at91/at91sam9g45.c                   |    2 +-
 arch/arm/mach-at91/at91sam9rl.c                    |    2 +-
 arch/arm/mach-at91/at91x40.c                       |    2 +-
 arch/arm/mach-at91/board-1arm.c                    |    2 +-
 arch/arm/mach-at91/board-afeb-9260v1.c             |    2 +-
 arch/arm/mach-at91/board-cam60.c                   |    2 +-
 arch/arm/mach-at91/board-carmeva.c                 |    2 +-
 arch/arm/mach-at91/board-cpu9krea.c                |    2 +-
 arch/arm/mach-at91/board-cpuat91.c                 |    2 +-
 arch/arm/mach-at91/board-csb337.c                  |    2 +-
 arch/arm/mach-at91/board-csb637.c                  |    2 +-
 arch/arm/mach-at91/board-dt-rm9200.c               |    2 +-
 arch/arm/mach-at91/board-dt-sam9.c                 |    2 +-
 arch/arm/mach-at91/board-dt-sama5.c                |    2 +-
 arch/arm/mach-at91/board-eb01.c                    |    2 +-
 arch/arm/mach-at91/board-eb9200.c                  |    2 +-
 arch/arm/mach-at91/board-ecbat91.c                 |    2 +-
 arch/arm/mach-at91/board-eco920.c                  |    2 +-
 arch/arm/mach-at91/board-flexibity.c               |    2 +-
 arch/arm/mach-at91/board-foxg20.c                  |    2 +-
 arch/arm/mach-at91/board-gsia18s.c                 |    2 +-
 arch/arm/mach-at91/board-kafa.c                    |    2 +-
 arch/arm/mach-at91/board-kb9202.c                  |    2 +-
 arch/arm/mach-at91/board-pcontrol-g20.c            |    2 +-
 arch/arm/mach-at91/board-picotux200.c              |    2 +-
 arch/arm/mach-at91/board-qil-a9260.c               |    2 +-
 arch/arm/mach-at91/board-rm9200dk.c                |    2 +-
 arch/arm/mach-at91/board-rm9200ek.c                |    2 +-
 arch/arm/mach-at91/board-rsi-ews.c                 |    2 +-
 arch/arm/mach-at91/board-sam9-l9260.c              |    2 +-
 arch/arm/mach-at91/board-sam9260ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9261ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9263ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9g20ek.c               |    2 +-
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    2 +-
 arch/arm/mach-at91/board-sam9rlek.c                |    2 +-
 arch/arm/mach-at91/board-snapper9260.c             |    2 +-
 arch/arm/mach-at91/board-stamp9g20.c               |    2 +-
 arch/arm/mach-at91/board-usb-a926x.c               |    2 +-
 arch/arm/mach-at91/board-yl-9200.c                 |    2 +-
 arch/arm/mach-at91/pm.c                            |    2 +-
 drivers/irqchip/Makefile                           |    1 +
 .../mach-at91/irq.c => drivers/irqchip/irq-at91.c  |    4 ++--
 .../at91_aic.h => include/linux/irqchip/at91.h     |    6 +-----
 49 files changed, 50 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562d..5333701 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y		:= irq.o gpio.o setup.o
+obj-y		:= gpio.o setup.o
 obj-m		:=
 obj-n		:=
 obj-		:=
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..39e7845 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -21,7 +22,6 @@
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a8ce245..5d06727 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -22,7 +23,6 @@
 #include <mach/at91sam9260.h>
 #include <mach/at91_pmc.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 25efb5a..554aa43 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -21,7 +22,6 @@
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f44ffd2..481e993 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -20,7 +21,6 @@
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..bc198a9 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -21,7 +22,6 @@
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f77fae5..65154f0 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -21,7 +22,6 @@
 #include <mach/at91sam9rl.h>
 #include <mach/at91_pmc.h>
 
-#include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 19ca793..4ae1400 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/irqchip/at91.h>
 #include <asm/proc-fns.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
@@ -21,7 +22,6 @@
 #include <mach/at91_st.h>
 #include <mach/timex.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 8389e81..7c18c14 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -24,6 +24,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -36,7 +37,6 @@
 
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 82832f1..f22552b 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -33,6 +33,7 @@
 #include <linux/spi/spi.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -43,7 +44,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index c1146d9..be01453 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -28,6 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -40,7 +41,6 @@
 
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index c0aac79..96a9bee 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -36,7 +37,6 @@
 
 #include <mach/hardware.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index c8ddf60..1148009 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -30,6 +30,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/mtd/physmap.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -44,7 +45,6 @@
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index b7675c8..75c5cd2 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -40,7 +41,6 @@
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 746120d..e651d5f 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -39,7 +40,6 @@
 
 #include <mach/hardware.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index c61f7d9..bec8c25 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -36,7 +37,6 @@
 
 #include <mach/hardware.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 13d7c62..67fff54 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -15,6 +15,7 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -22,7 +23,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 
 
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 4d291ae..65edc6e 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -14,6 +14,7 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -21,7 +22,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index d39a459..015178f 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -23,7 +24,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 
 
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 8d84f46..f0804fd 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -23,12 +23,12 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
+#include <linux/irqchip/at91.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 95a4a65..ce9ddb5 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/device.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -35,7 +36,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 4bababc..971a309 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -39,7 +40,6 @@
 
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index ba6c6f7..f8463e1 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/mach-types.h>
 
@@ -28,7 +29,6 @@
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index b9b1f59..8d3ea6d 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -25,6 +25,7 @@
 #include <linux/spi/spi.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/mach-types.h>
 
@@ -34,7 +35,6 @@
 
 #include <mach/hardware.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 816db05..14ec339 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -31,6 +31,7 @@
 #include <linux/input.h>
 #include <linux/clk.h>
 #include <linux/w1-gpio.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -43,7 +44,6 @@
 
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index af6a925..0912ba5 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -26,13 +26,13 @@
 #include <linux/i2c/pcf857x.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 31bd8c9..10970ba 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -24,6 +24,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -36,7 +37,6 @@
 
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index df43c2e..6a4a93c 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -39,7 +40,6 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 724c91b..456a5db 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -25,13 +25,13 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/w1-gpio.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 479a034..e511065 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -40,7 +41,6 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 1d7a4e7..2ffe497 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -30,6 +30,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/clk.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -42,7 +43,6 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc04718..7a1e71d 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -29,6 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -42,7 +43,6 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 13a121a..46acbf9 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -29,6 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -42,7 +43,6 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index d15ef0c..f7f4406 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -28,7 +29,6 @@
 
 #include <linux/gpio.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 0907df4..72f9163 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -27,6 +27,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -39,7 +40,6 @@
 
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0361c4d..ea5a9cb 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -44,7 +45,6 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index c28401a..a181855 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -33,6 +33,7 @@
 #include <linux/fb.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/irqchip/at91.h>
 
 #include <video/atmel_lcdc.h>
 
@@ -48,7 +49,6 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 1287d81..8f8e3f7 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -32,6 +32,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/leds.h>
+#include <linux/irqchip/at91.h>
 
 #include <video/atmel_lcdc.h>
 
@@ -47,7 +48,6 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index c6ea31d..13a4c16 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/consumer.h>
+#include <linux/irqchip/at91.h>
 
 #include <linux/platform_data/at91_adc.h>
 
@@ -46,7 +47,6 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 139a67e..98f88f2 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -26,6 +26,7 @@
 #include <linux/leds.h>
 #include <linux/atmel-mci.h>
 #include <linux/delay.h>
+#include <linux/irqchip/at91.h>
 
 #include <linux/platform_data/at91_adc.h>
 
@@ -45,7 +46,6 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index fdcb1cc..6da0fdb 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -18,6 +18,7 @@
 #include <linux/clk.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/irqchip/at91.h>
 
 #include <video/atmel_lcdc.h>
 
@@ -33,7 +34,6 @@
 #include <mach/at91sam9_smc.h>
 
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index c07e86a..7cfc767 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,7 +35,6 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 4977e6e..01d7245 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -21,13 +21,13 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/w1-gpio.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index a0f7d74..a89b733 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -31,6 +31,7 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/spi/mmc_spi.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -43,7 +44,6 @@
 #include <mach/hardware.h>
 #include <mach/at91sam9_smc.h>
 
-#include "at91_aic.h"
 #include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index ac3b263..a858ea1 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -33,6 +33,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -47,7 +48,6 @@
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 530db30..6577307 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,6 +19,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/irqchip/at91.h>
 
 #include <asm/irq.h>
 #include <linux/atomic.h>
@@ -28,7 +29,6 @@
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
-#include "at91_aic.h"
 #include "generic.h"
 #include "pm.h"
 
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5..208b708 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
+obj-$(CONFIG_ARCH_AT91)			+= irq-at91.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
diff --git a/arch/arm/mach-at91/irq.c b/drivers/irqchip/irq-at91.c
similarity index 99%
rename from arch/arm/mach-at91/irq.c
rename to drivers/irqchip/irq-at91.c
index 18c653f..ca49096 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/drivers/irqchip/irq-at91.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-at91/irq.c
+ * drivers/irqchip/irq-at91.c
  *
  *  Copyright (C) 2004 SAN People
  *  Copyright (C) 2004 ATMEL
@@ -32,6 +32,7 @@
 #include <linux/irqdomain.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/irqchip/at91.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -42,7 +43,6 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include "at91_aic.h"
 
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
diff --git a/arch/arm/mach-at91/at91_aic.h b/include/linux/irqchip/at91.h
similarity index 97%
rename from arch/arm/mach-at91/at91_aic.h
rename to include/linux/irqchip/at91.h
index be8680d..42f1260 100644
--- a/arch/arm/mach-at91/at91_aic.h
+++ b/include/linux/irqchip/at91.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-at91/include/mach/at91_aic.h
+ * include/linux/irqchip/at91.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -16,7 +16,6 @@
 #ifndef AT91_AIC_H
 #define AT91_AIC_H
 
-#ifndef __ASSEMBLY__
 extern void __iomem *at91_aic_base;
 
 #define at91_aic_read(field) \
@@ -24,9 +23,6 @@ extern void __iomem *at91_aic_base;
 
 #define at91_aic_write(field, value) \
 	__raw_writel(value, at91_aic_base + field)
-#else
-.extern at91_aic_base
-#endif
 
 /* Number of irq lines managed by AIC */
 #define NR_AIC_IRQS	32
-- 
1.7.9.5



From hector.palacios at digi.com  Thu May 23 11:56:48 2013
From: hector.palacios at digi.com (Hector Palacios)
Date: Thu, 23 May 2013 17:56:48 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <201305231531.31376.jbe@pengutronix.de>
References: <519E03B0.1080006@digi.com> <20130523130039.GF8595@lukather>
 <201305231531.31376.jbe@pengutronix.de>
Message-ID: <519E3C40.4020405@digi.com>

Hi Juergen,

On 05/23/2013 03:31 PM, Juergen Beisert wrote:
> Hi Maxime,
>
> maxime.ripard at free-electrons.com wrote:
>> On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
>>> I'm using an i.MX28 based board with lcd connected with 18bits data bus.
>>> My platform uses 32 bits per pixel:
>>>
>>> 	mxsfb_pdata.default_bpp = 32;
>>> 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
>>>
>>> With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
>>> at HW_LCDIF_CTRL register in function mxsfb_set_par():
>>>
>>> 	case 32:
>>> 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
>>> 		ctrl |= CTRL_SET_WORD_LENGTH(3);
>>> 		switch (host->ld_intf_width) {
>>> 		case STMLCDIF_8BIT:
>>> 			dev_dbg(&host->pdev->dev,
>>> 					"Unsupported LCD bus width mapping\n");
>>> 			return -EINVAL;
>>> 		case STMLCDIF_16BIT:
>>> 		case STMLCDIF_18BIT:
>>> 			/* 24 bit to 18 bit mapping */
>>> 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
>>> 					    *  each colour component
>>> 					    */
>>> 			break;
>>> 		case STMLCDIF_24BIT:
>>> 			/* real 24 bit */
>>> 			break;
>>> 		}
>>>
>>> According to the manual, this flag does:
>>> 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
>>> format, such that all RGB 888 data is contained in 24 bits.
>>> 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
>>> actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
>>> 2 bits in each byte do not contain any useful data, and should be
>>> dropped.
>>>
>>> The setting of this flag is producing bad colours with true colour
>>> images (i.e. the Linux penguin is displayed ok, but QT applications
>>> or images displayed with fbv are not).
>>> I believe the setting of this flag is not correct (after all, if my
>>> bpp is 32, then all 24bit colours are useful and dropping the upper
>>> 2 bits is a bad idea).
>>> If I don't set it, then true colour images are displayed correctly.
>>> The only problem is that the Linux penguin is displayed much darker
>>> than usual (correct colours, but darker). Perhaps the 224 colour
>>> format of this image justifies it?
>>>
>>> I noticed the cfa10049 platform also uses the same configuration (18
>>> bits data bus and 32bpp) and was wondering if true colour images are
>>> correctly displayed in this platform with this flag set (for example
>>> with fbv application [1]).
>>
>> I had the exact same problem, and suggested the exact same solution a
>> few weeks back.
>>
>> https://patchwork.kernel.org/patch/2470441/
>>
>> The conclusion of that discussion what that the userspace applications
>> were not honouring the bitfield correctly set by the mxsfb driver, and
>> as such, it was not a bug in the driver.
>>
>> While this is correct, I wonder, now that since we had that same problem
>> in a very short amount of time, if we couldn't set this behaviour
>> dependant of some (dt? kernel argument?) property so that one could
>> customise it anyway he want.
>>
>> Maxime
>
> i.MX2[3|8]    LCD1       LCD2       LCD3
>                24bit      18bit      18bit
> --------------------------------------------
> LCD_D0         B0         B0         --
> LCD_D1         B1         B1         --
> LCD_D2         B2         B2         B0
> LCD_D3         B3         B3         B1
> LCD_D4         B4         B4         B2
> LCD_D5         B5         B5         B3
> LCD_D6         B6         G0         B4
> LCD_D7         B7         G1         B5
>
> LCD_D8         G0         G2         --
> LCD_D9         G1         G3         --
> LCD_D10        G2         G4         G0
> LCD_D11        G3         G5         G1
> LCD_D12        G4         R0         G2
> LCD_D13        G5         R1         G3
> LCD_D14        G6         R2         G4
> LCD_D15        G7         R3         G5
>
> LCD_D16        R0         R4         --
> LCD_D17        R1         R5         --
> LCD_D18        R2                    R0
> LCD_D19        R3                    R1
> LCD_D20        R4                    R2
> LCD_D21        R5                    R3
> LCD_D22        R6                    R4
> LCD_D23        R7                    R5
>
> Is your display connected like LCD2 or LCD3? LCD3 must still handled like a 24
> bit display shown in LCD1, while only the LCD2-case is the "24 bit to 18 bit
> mapping" case.
>
> At least my current tests with an i.MX23 and a connection like LCD2 are
> working here with a Qt application. Qt honours the pixel bitfield
> description. And I'm using the "bits-per-pixel = <32>" and "bus-width = <18>"
> entries in the device tree.

I have a 24bit LCD display but my connection to it is done at 18bits data width.
Represented below as LCD4.
NOTE: In my LCD4 column, notation Rx/Gx/Bx represent the color bit in memory as well 
as the display data line.
Since we use 32bpp each channel has 8 bits (R7..R0, etc.).
I understand that you have an 18bit display and that your notation in LCD2 column 
represents the display data lines, not the color bit indexes in memory.

i.MX2[3|8]    LCD1       LCD2       LCD3	LCD4
               24bit      18bit      18bit	24bit connected at 18bit
-------------------------------------------------------
LCD_D0         B0         B0         --		B2
LCD_D1         B1         B1         --		B3
LCD_D2         B2         B2         B0		B4
LCD_D3         B3         B3         B1		B5
LCD_D4         B4         B4         B2		B6
LCD_D5         B5         B5         B3		B7
LCD_D6         B6         G0         B4		G2
LCD_D7         B7         G1         B5		G3

LCD_D8         G0         G2         --		G4
LCD_D9         G1         G3         --		G5
LCD_D10        G2         G4         G0		G6
LCD_D11        G3         G5         G1		G7
LCD_D12        G4         R0         G2		R2
LCD_D13        G5         R1         G3		R3
LCD_D14        G6         R2         G4		R4
LCD_D15        G7         R3         G5		R5

LCD_D16        R0         R4         --		R6
LCD_D17        R1         R5         --		R7
LCD_D18        R2                    R0
LCD_D19        R3                    R1
LCD_D20        R4                    R2
LCD_D21        R5                    R3
LCD_D22        R6                    R4
LCD_D23        R7                    R5

For 32bpp (RGB888) and 18bit data bus I would expect the LCD controller to take the 
six *most significant* bits [7..2] from each color byte out to the LCD data bus 
(LCD_D17..D0) in the order depicted in my LCD4 column.

I'm not sure what the DATA_FORMAT_24_BIT flag is doing, but dropping the two most 
significant bits of color in memory doesn't seem to be a good idea unless (maybe) 
color is in 18bpp. Previous kernels did not even touch this flag.

Does the following patch make sense?

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index b1c1a80..bb0a4e1 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -298,9 +298,6 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
                         break;
                 case STMLCDIF_16BIT:
                 case STMLCDIF_18BIT:
-                       /* 24 bit to 18 bit mapping */
-                       rgb = def_rgb666;
-                       break;
                 case STMLCDIF_24BIT:
                         /* real 24 bit */
                         rgb = def_rgb888;
@@ -424,11 +421,6 @@ static int mxsfb_set_par(struct fb_info *fb_info)
                         return -EINVAL;
                 case STMLCDIF_16BIT:
                 case STMLCDIF_18BIT:
-                       /* 24 bit to 18 bit mapping */
-                       ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
-                                           *  each colour component
-                                           */
-                       break;
                 case STMLCDIF_24BIT:
                         /* real 24 bit */
                         break;

The setting of def_rgb666 for a 32bpp color depth does not make sense to me because 
the color in memory is really rgb888.

With this patch, my true color images are displayed ok and so does the penguin logo.
I don't know however how other displays connections at 18bit will do.

Regards,
-- 
H?ctor Palacios


From santosh.shilimkar at ti.com  Thu May 23 12:00:22 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Thu, 23 May 2013 12:00:22 -0400
Subject: [PATCH v2 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <519E3D16.2090003@ti.com>

On Thursday 23 May 2013 11:36 AM, Florian Vaussard wrote:
> Hello,
> 
> Following a similar proposal by Stephen Warren for tegra [1], this series
> makes use of the C preprocessor when compiling OMAP DT files, and
> accomplishes some improvements to improve overall readability.
> 
> Patch 1 is a preparation for the rest of the series.
> Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
> IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
> it to simplify pinctrl DT.
> 
> For all targets, the .dtb files were diff-tested before and after
> applying the series to guarantee identity.
> 

> 
> Florian Vaussard (5):
>   ARM: dts: OMAP2+: use #include for all device trees
>   ARM: dts: OMAP2+: use existing constants for GPIOs
>   ARM: dts: OMAP4/5: use existing constants for IRQs
>   ARM: dts: OMAP2+: header file for pinctrl constants
>   ARM: dts: OMAP2+: use pinctrl constants
> 
I just quickly scanned the series and patches looks
good to my eyes. Its a nice clean-up to align OMAP
dts files with others.

FWIW,
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>



From jason at lakedaemon.net  Thu May 23 12:01:11 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 12:01:11 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130522201607.GA18823@obsidianresearch.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
Message-ID: <20130523160111.GP31290@titan.lakedaemon.net>

Sebastian,

On Wed, May 22, 2013 at 02:16:07PM -0600, Jason Gunthorpe wrote:
> On Wed, May 22, 2013 at 10:04:02PM +0200, Sebastian Hesselbarth wrote:
> 
> > Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
> > MAC address register contents on clock gating but also some important
> > registers are reset to values that would break ethernet. This patch
> 
> FWIW, we found that the bootloader has to write to PSC1, the driver
> doesn't work with the power on/reset value of the register. So I think
> it is safe to assume that all kirkwood bootloaders alter the value.
> 
> Our systems write the value 0x00638488 to PSC1.
> 
> I looked at patching mv643xx_eth, but ran into the same complexity you
> did, it isn't clear what variants of this IP block have the
> register/etc.
> 
> > +	/* Kirkwood resets some registers on gated clocks. Especially
> > +	 * CLK125_BYPASS_EN must be cleared but is not available on
> > +	 * all other SoCs/System Controllers using this driver.
> > +	 */
> > +	if (of_machine_is_compatible("marvell,kirkwood"))
> > +		wrlp(mp, PORT_SERIAL_CONTROL1,
> > +		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
> 
> of_machine_is_compatible seems heavy handed, I would expect this to be
> based on the compatible string of the ethernet node itself, not the
> machine??

Is there a model number variation between IP that needs this and IP that
doesn't?  If not, I'm fine with of_machine_is_compatible().

thx,

Jason.


From b.brezillon at overkiz.com  Thu May 23 12:01:21 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Thu, 23 May 2013 18:01:21 +0200
Subject: [PATCH] ARM: at91/dt: fix macb pinctrl_macb_rmii_mii_alt definition
Message-ID: <1369324881-31428-1-git-send-email-b.brezillon@overkiz.com>

The PA24 pin is wrongly assigned to peripheral B.
In the current config there is 2 ETX3 pins (PA11 and PA24) and
no ETXER pin (PA22).

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..84c4bef 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -264,7 +264,7 @@
 						atmel,pins =
 							<0 10 0x2 0x0	/* PA10 periph B */
 							 0 11 0x2 0x0	/* PA11 periph B */
-							 0 24 0x2 0x0	/* PA24 periph B */
+							 0 22 0x2 0x0	/* PA22 periph B */
 							 0 25 0x2 0x0	/* PA25 periph B */
 							 0 26 0x2 0x0	/* PA26 periph B */
 							 0 27 0x2 0x0	/* PA27 periph B */
-- 
1.7.9.5



From 21cnbao at gmail.com  Thu May 23 12:17:54 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 24 May 2013 00:17:54 +0800
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>
References: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
 <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>
Message-ID: <CAGsJ_4y6BwTpZpwYv0njvqYtp9Y0UU5qhVJhqG5X+8+Hy_LW8Q@mail.gmail.com>

hi madhvapathi,
thanks for comments.

2013/5/23 Madhvapathi Sriram <Madhvapathi.Sriram at csr.com>:
> Comments inline.
> ________________________________________
> From: Barry Song [21cnbao at gmail.com]
> Sent: Wednesday, May 22, 2013 9:43 PM
> To: dtor at mail.ru; dmitry.torokhov at gmail.com
> Cc: linux-input at vger.kernel.org; DL-SHA-WorkGroupLinux; linux-arm-kernel at lists.infradead.org; Binghua Duan; Xianglong Du; Barry Song
> Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR SiRFprimaII PWRC
>
> From: Binghua Duan <Binghua.Duan at csr.com>
>
> there is an embedded PWRC(power controller) in SiRFprimaII and SiRFatlasVI,
> we have an ONKEY button which can generate interrupt to IRQ controller.
> in a typical user scenarios, at the runtime, if users touch the key, we put
> system to s2ram status.
>
> Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
> Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  drivers/input/misc/Kconfig         |  10 +++
>  drivers/input/misc/Makefile        |   1 +
>  drivers/input/misc/sirfsoc_onkey.c | 176 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 187 insertions(+)
>  create mode 100644 drivers/input/misc/sirfsoc_onkey.c
>
> diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
> index bb698e1..1d91d1b 100644
> --- a/drivers/input/misc/Kconfig
> +++ b/drivers/input/misc/Kconfig
> @@ -637,4 +637,14 @@ config INPUT_XEN_KBDDEV_FRONTEND
>           To compile this driver as a module, choose M here: the
>           module will be called xen-kbdfront.
>
> +config INPUT_SIRFSOC_ONKEY
> +       bool "CSR SiRFSoC power on/off/suspend key support"
> +       depends on ARCH_SIRF
> +       default y
> +       help
> +         Say Y here if you want to support for the SiRFSoC power on/off/suspend key
> +         in Linux, after you press the onkey, system will suspend.
> +
> +         If unsure, say N.
> +
>  endif
> diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
> index d7fc17f..1d66f03 100644
> --- a/drivers/input/misc/Makefile
> +++ b/drivers/input/misc/Makefile
> @@ -60,3 +60,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS)      += wistron_btns.o
>  obj-$(CONFIG_INPUT_WM831X_ON)          += wm831x-on.o
>  obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND)        += xen-kbdfront.o
>  obj-$(CONFIG_INPUT_YEALINK)            += yealink.o
> +obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)      += sirfsoc_onkey.o
> diff --git a/drivers/input/misc/sirfsoc_onkey.c b/drivers/input/misc/sirfsoc_onkey.c
> new file mode 100644
> index 0000000..3e48db9
> --- /dev/null
> +++ b/drivers/input/misc/sirfsoc_onkey.c
> @@ -0,0 +1,176 @@
> +/*
> + * Power key driver for SiRF PrimaII
> + *
> + * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/platform_device.h>
> +#include <linux/input.h>
> +#include <linux/rtc/sirfsoc_rtciobrg.h>
> +#include <linux/of.h>
> +
> +struct sirfsoc_pwrc_drvdata {
> +       u32                     pwrc_base;
> +       int                     irq;
> +       struct input_dev        *input;
> +};
> +
> +#define PWRC_ON_KEY_BIT                        (1 << 0)
> +
> +#define PWRC_INT_STATUS                        0xc
> +#define PWRC_INT_MASK                  0x10
> +
> +static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
> +{
> +       struct sirfsoc_pwrc_drvdata *pwrcdrv =
> +                       (struct sirfsoc_pwrc_drvdata *)dev_id;
> +       u32 int_status;
> +       int_status = sirfsoc_rtc_iobrg_readl(
> +                       pwrcdrv->pwrc_base + PWRC_INT_STATUS);
> +       sirfsoc_rtc_iobrg_writel(int_status & (~PWRC_ON_KEY_BIT),
> +                       pwrcdrv->pwrc_base + PWRC_INT_STATUS);
> +
> +       /*
> +        * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
> +        * to queue a SUSPEND APM event
> +        */
> +       input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
> +       input_sync(pwrcdrv->input);
> +
> +       /*
> +        * Todo: report KEY_POWER event for Android platforms, Android PowerManager
> +        * will handle the suspend and powerdown/hibernation
> +        */
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static const struct of_device_id sirfsoc_pwrc_of_match[] = {
> +       { .compatible = "sirf,prima2-pwrc" },
> +       {},
> +}
> +MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
> +
> +static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> +{
> +       int ret;
> +       struct sirfsoc_pwrc_drvdata *pwrcdrv = NULL;
> +       struct device_node *np = pdev->dev.of_node;
> +
> +       pwrcdrv = devm_kzalloc(&pdev->dev,
> +               sizeof(struct sirfsoc_pwrc_drvdata), GFP_KERNEL);
> +       if (!pwrcdrv) {
> +               dev_info(&pdev->dev, "kzalloc fail!\n");
> +               return -ENOMEM;
> +       }
> +
> +       /*
> +        * we can't use of_iomap because pwrc is not mapped in memory, the so-called base
> +        * address is only offset in rtciobrg
> +        */
> +       ret = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
>
> Possible mem leak here  - not freeing pwrcdrv

no. there is no mem leak here. devm_ means device management resources.

>
> +       if (ret) {
> +               dev_err(&pdev->dev, "unable to find base address of pwrc node in dtb\n");
> +               return ret;
> +       }
> +
> +       pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
> +       if (!pwrcdrv->input)
> +               return -ENOMEM;
> +
> +       pwrcdrv->input->name = "sirfsoc pwrckey";
> +       pwrcdrv->input->phys = "pwrc/input0";
> +
> +       platform_set_drvdata(pdev, pwrcdrv);
> +
> +       pwrcdrv->irq = platform_get_irq(pdev, 0);
> +       ret = devm_request_irq(&pdev->dev, pwrcdrv->irq,
> +                       sirfsoc_pwrc_isr, IRQF_SHARED,
> +                       "sirfsoc_pwrc_int", pwrcdrv);
> +
> +       sirfsoc_rtc_iobrg_writel(
> +               sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK)
> +               | PWRC_ON_KEY_BIT, pwrcdrv->pwrc_base + PWRC_INT_MASK);
>
> Enabling the MASK for an interrupt should only come after it has been successfully claimed? Else we might be leaving and interrupt enabled without being able to handle it?

here moving ahead of request_irq and placing here both work. as there
is another gate in irq controller.

>
> Possible mem leak here not freeing any allocated devices/memory/irq.
> I suggest all the error handling be collated at the end of this function for various stages and error handling be done there.

and we don't need to free devm_irq and devm_mem as well.

> Please have a look at https://www.kernel.org/doc/Documentation/input/input-programming.txt
>
> +       if (ret) {
> +               dev_err(&pdev->dev, "pwrc: Unable to claim irq %d; error %d\n",
> +                       pwrcdrv->irq, ret);
> +               return ret;
> +       }
> +
> +       pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
> +       set_bit(KEY_POWER, pwrcdrv->input->keybit);
> +
> +       ret = input_register_device(pwrcdrv->input);
> +       if (ret) {
> +               dev_err(&pdev->dev,
> +                       "pwrc: Unable to register input device,error: %d\n",
> +                       ret);
> +               return ret;
> +       }
> +
> +       device_init_wakeup(&pdev->dev, 1);
> +
> +       return 0;
> +}
> +
> +static int sirfsoc_pwrc_remove(struct platform_device *pdev)
> +{
> +       device_init_wakeup(&pdev->dev, 0);
> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int pwrc_suspend(struct device *dev)
> +{
> +       return 0;
> +}
> +
> +static int pwrc_resume(struct device *dev)
> +{
> +       struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
> +
>
> Typically, the wake up interrupts would be ensured to be active while going to sleep/suspend.
> However, here at resume the interrupt mask is being set. Is it because, there are some caveats here?

xianglong, pls explain.

>
> +       /*
> +        * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
> +        * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
> +        */
> +       sirfsoc_rtc_iobrg_writel(
> +               sirfsoc_rtc_iobrg_readl(
> +               pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
> +               pwrcdrv->pwrc_base + PWRC_INT_MASK);
> +
> +       return 0;
> +}
> +
> +static const struct dev_pm_ops sirfsoc_pwrc_pm_ops = {
> +       .suspend = pwrc_suspend,
> +       .resume = pwrc_resume,
> +};
> +#endif
> +
> +static struct platform_driver sirfsoc_pwrc_driver = {
> +       .probe          = sirfsoc_pwrc_probe,
> +       .remove         = sirfsoc_pwrc_remove,
> +       .driver         = {
> +               .name   = "sirfsoc-pwrc",
> +               .owner  = THIS_MODULE,
> +#ifdef CONFIG_PM
> +               .pm     = &sirfsoc_pwrc_pm_ops,
> +#endif
> +               .of_match_table = of_match_ptr(sirfsoc_pwrc_of_match),
> +       }
> +};
> +
> +module_platform_driver(sirfsoc_pwrc_driver);
> +
> +MODULE_LICENSE("GPLv2");
> +MODULE_AUTHOR("Binghua Duan <Binghua.Duan at csr.com>, "
> +               "Xianglong Du <Xianglong.Du at csr.com>");
> +MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
> +MODULE_ALIAS("platform:sirfsoc-pwrc");
> --
> 1.8.2.3

-barry


From dmitry.torokhov at gmail.com  Thu May 23 12:26:57 2013
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Thu, 23 May 2013 09:26:57 -0700
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
References: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130523162657.GA15494@core.coreip.homeip.net>

Hi Barry,

Looks very good, just a few nits below.

On Thu, May 23, 2013 at 12:13:18AM +0800, Barry Song wrote:
> diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
> index d7fc17f..1d66f03 100644
> --- a/drivers/input/misc/Makefile
> +++ b/drivers/input/misc/Makefile
> @@ -60,3 +60,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS)	+= wistron_btns.o
>  obj-$(CONFIG_INPUT_WM831X_ON)		+= wm831x-on.o
>  obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND)	+= xen-kbdfront.o
>  obj-$(CONFIG_INPUT_YEALINK)		+= yealink.o
> +obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)	+= sirfsoc_onkey.o

Please try keeping it sorted.

> diff --git a/drivers/input/misc/sirfsoc_onkey.c b/drivers/input/misc/sirfsoc_onkey.c
> new file mode 100644
> index 0000000..3e48db9
> --- /dev/null
> +++ b/drivers/input/misc/sirfsoc_onkey.c
> @@ -0,0 +1,176 @@
> +/*
> + * Power key driver for SiRF PrimaII
> + *
> + * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/platform_device.h>
> +#include <linux/input.h>
> +#include <linux/rtc/sirfsoc_rtciobrg.h>
> +#include <linux/of.h>
> +
> +struct sirfsoc_pwrc_drvdata {
> +	u32			pwrc_base;
> +	int			irq;

Since you are using devm_ interfaces you don't really need to store irq
in the structure as far as I can see.

> +	struct input_dev	*input;
> +};
> +
> +#define PWRC_ON_KEY_BIT			(1 << 0)
> +
> +#define PWRC_INT_STATUS			0xc
> +#define PWRC_INT_MASK			0x10
> +
> +static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
> +{
> +	struct sirfsoc_pwrc_drvdata *pwrcdrv =
> +			(struct sirfsoc_pwrc_drvdata *)dev_id;
> +	u32 int_status;
> +	int_status = sirfsoc_rtc_iobrg_readl(
> +			pwrcdrv->pwrc_base + PWRC_INT_STATUS);
> +	sirfsoc_rtc_iobrg_writel(int_status & (~PWRC_ON_KEY_BIT),
> +			pwrcdrv->pwrc_base + PWRC_INT_STATUS);
> +
> +	/*
> +	 * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
> +	 * to queue a SUSPEND APM event
> +	 */
> +	input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
> +	input_sync(pwrcdrv->input);
> +
> +	/*
> +	 * Todo: report KEY_POWER event for Android platforms, Android PowerManager
> +	 * will handle the suspend and powerdown/hibernation
> +	 */
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static const struct of_device_id sirfsoc_pwrc_of_match[] = {
> +	{ .compatible = "sirf,prima2-pwrc" },
> +	{},
> +}
> +MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
> +
> +static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> +{
> +	int ret;
> +	struct sirfsoc_pwrc_drvdata *pwrcdrv = NULL;
> +	struct device_node *np = pdev->dev.of_node;
> +
> +	pwrcdrv = devm_kzalloc(&pdev->dev,
> +		sizeof(struct sirfsoc_pwrc_drvdata), GFP_KERNEL);
> +	if (!pwrcdrv) {
> +		dev_info(&pdev->dev, "kzalloc fail!\n");
> +		return -ENOMEM;
> +	}
> +
> +	/*
> +	 * we can't use of_iomap because pwrc is not mapped in memory, the so-called base
> +	 * address is only offset in rtciobrg
> +	 */
> +	ret = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to find base address of pwrc node in dtb\n");
> +		return ret;
> +	}
> +
> +	pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
> +	if (!pwrcdrv->input)
> +		return -ENOMEM;
> +
> +	pwrcdrv->input->name = "sirfsoc pwrckey";
> +	pwrcdrv->input->phys = "pwrc/input0";
> +
> +	platform_set_drvdata(pdev, pwrcdrv);
> +
> +	pwrcdrv->irq = platform_get_irq(pdev, 0);
> +	ret = devm_request_irq(&pdev->dev, pwrcdrv->irq,
> +			sirfsoc_pwrc_isr, IRQF_SHARED,
> +			"sirfsoc_pwrc_int", pwrcdrv);
> +
> +	sirfsoc_rtc_iobrg_writel(
> +		sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK)
> +		| PWRC_ON_KEY_BIT, pwrcdrv->pwrc_base + PWRC_INT_MASK);
> +	if (ret) {

Why do we check only after fiddling with registers?

> +		dev_err(&pdev->dev, "pwrc: Unable to claim irq %d; error %d\n",
> +			pwrcdrv->irq, ret);
> +		return ret;
> +	}
> +
> +	pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
> +	set_bit(KEY_POWER, pwrcdrv->input->keybit);
> +
> +	ret = input_register_device(pwrcdrv->input);
> +	if (ret) {
> +		dev_err(&pdev->dev,
> +			"pwrc: Unable to register input device,error: %d\n",
> +			ret);
> +		return ret;
> +	}
> +
> +	device_init_wakeup(&pdev->dev, 1);
> +
> +	return 0;
> +}
> +
> +static int sirfsoc_pwrc_remove(struct platform_device *pdev)
> +{
> +	device_init_wakeup(&pdev->dev, 0);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM

I think it should be CONFIG_PM_SLEEP as it resuyme handling does not
appear to make sense for runtime PM.

> +static int pwrc_suspend(struct device *dev)
> +{
> +	return 0;
> +}
> +
> +static int pwrc_resume(struct device *dev)
> +{
> +	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
> +
> +	/* 

Trailing whitespace.

> +	 * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
> +	 * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
> +	 */
> +	sirfsoc_rtc_iobrg_writel(
> +		sirfsoc_rtc_iobrg_readl(
> +		pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
> +		pwrcdrv->pwrc_base + PWRC_INT_MASK);
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops sirfsoc_pwrc_pm_ops = {
> +	.suspend = pwrc_suspend,
> +	.resume	= pwrc_resume,
> +};
> +#endif
> +

just say

static SIMPLE_DEV_PM_OPS(sirfsoc_pwrc_pm_ops, NULL, pwrc_resume);

> +static struct platform_driver sirfsoc_pwrc_driver = {
> +	.probe		= sirfsoc_pwrc_probe,
> +	.remove		= sirfsoc_pwrc_remove,
> +	.driver		= {
> +		.name	= "sirfsoc-pwrc",
> +		.owner	= THIS_MODULE,
> +#ifdef CONFIG_PM
> +		.pm	= &sirfsoc_pwrc_pm_ops,
> +#endif

and you do not need ifdef guard here.

> +		.of_match_table = of_match_ptr(sirfsoc_pwrc_of_match),
> +	}
> +};
> +
> +module_platform_driver(sirfsoc_pwrc_driver);
> +
> +MODULE_LICENSE("GPLv2");
> +MODULE_AUTHOR("Binghua Duan <Binghua.Duan at csr.com>, "
> +		"Xianglong Du <Xianglong.Du at csr.com>");
> +MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
> +MODULE_ALIAS("platform:sirfsoc-pwrc");


Thanks.

-- 
Dmitry


From dmitry.torokhov at gmail.com  Thu May 23 12:29:16 2013
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Thu, 23 May 2013 09:29:16 -0700
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>
References: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
 <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>
Message-ID: <20130523162916.GB15494@core.coreip.homeip.net>

Hi Madhvapathi,

On Thu, May 23, 2013 at 01:49:10PM +0000, Madhvapathi Sriram wrote:
> Possible mem leak here not freeing any allocated devices/memory/irq.
> I suggest all the error handling be collated at the end of this
> function for various stages and error handling be done there.
> Please have a look at
> https://www.kernel.org/doc/Documentation/input/input-programming.txt

Please note that the driver uses managed resources which get cleaned
automatically.

Also, could you please use a sane mailer that wraps long lines properly.

Thanks.

-- 
Dmitry


From jgunthorpe at obsidianresearch.com  Thu May 23 12:46:54 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 23 May 2013 10:46:54 -0600
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <20130523001353.GH31625@1wt.eu>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523001353.GH31625@1wt.eu>
Message-ID: <20130523164654.GA31281@obsidianresearch.com>

On Thu, May 23, 2013 at 02:13:53AM +0200, Willy Tarreau wrote:
> Hi Thomas,
> 
> On Wed, May 22, 2013 at 03:12:34PM +0200, Thomas Petazzoni wrote:
> > Bjorn, Jason, Andrew, Gregory,
> > 
> > You'll find in this patch series 4 small patches that make various
> > improvements to the Marvell PCIe driver.
> (...)
> 
> FWIW, these patches applied on top of your pcie-v10 tree have made
> my mini-pcie dual-nic appear for the first time on the mirabox. Till
> now I never knew if it was a hardware or software issue since the NIC
> does not appear in u-boot nor lspci, whatever the kernel versions,
> including the original Marvell one's. The NIC has two functions (one
> per controller) and no bridge, so it may be a side effect of your
> improvements (or maybe you fixed a bug).

There was some talk earlier that some buggy chips required their
device number to be 0. I'm guessing Thomas's change to ensure that
always happens by moving the device number of the internal device is
the root fix here?

Regards,
Jason


From kim.phillips at freescale.com  Thu May 23 12:46:54 2013
From: kim.phillips at freescale.com (Kim Phillips)
Date: Thu, 23 May 2013 11:46:54 -0500
Subject: [PATCH v7] arm: use built-in byte swap function
In-Reply-To: <1361661654.18110.102.camel@shinybook.infradead.org>
References: <20130129181046.GC25415@pd.tnic>
 <20130208191208.2ef3d78bda71aa7b44d00d7b@freescale.com>
 <alpine.LFD.2.02.1302082102380.6300@xanadu.home>
 <20130219203115.114eab79e8d2099c6306d921@freescale.com>
 <alpine.LFD.2.03.1302192151280.6419@syhkavp.arg>
 <1361356696.13482.269.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200835380.6419@syhkavp.arg>
 <1361367842.13482.279.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200905300.6419@syhkavp.arg>
 <1361372008.13482.280.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302201040460.6419@syhkavp.arg>
 <20130220214943.9b28a5b208da9f081387c55e@freescale.com>
 <alpine.LFD.2.03.1302202327370.6419@syhkavp.arg>
 <20130221005221.15279b1372501af12c1e4f32@freescale.com>
 <alpine.LFD.2.03.1302211134160.6419@syhkavp.arg>
 <20130221203327.6558f89277468f7ffffa6506@freescale.com>
 <alpine.LFD.2.03.1302212219100.6419@syhkavp.arg>
 <20130222194032.f7b44aefa5e2723d16767a1b@freescale.com>
 <1361661654.18110.102.camel@shinybook.infradead.org>
Message-ID: <20130523114654.1f273241725205c6703b2226@freescale.com>

Enable the compiler intrinsic for byte swapping on arch ARM.  This
allows the compiler to detect and be able to optimize out byte
swappings, and has a very modest benefit on vmlinux size (Linaro gcc
4.8):

   text	   data	    bss	    dec	    hex	filename
2840310	 123932	  61960	3026202	 2e2d1a	vmlinux-lart #orig
2840152	 123932	  61960	3026044	 2e2c7c	vmlinux-lart #builtin-bswap

6473120	 314840	5616016	12403976 bd4508	vmlinux-mxs #orig
6472586	 314848	5616016	12403450 bd42fa	vmlinux-mxs #builtin-bswap

7419872	 318372	 379556	8117800	 7bde28	vmlinux-imx_v6_v7 #orig
7419170	 318364	 379556	8117090	 7bdb62	vmlinux-imx_v6_v7 #builtin-bswap

Signed-off-by: Kim Phillips <kim.phillips at freescale.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
Acked-by: David Woodhouse <David.Woodhouse at intel.com>
---
resending as v6 appears to have fallen though the cracks.  Russell?

v7: rebased onto next-20130521, re-ran above vmlinux sizes with
    Linaro gcc 4.8, added Nicolas' Reviewed-by, and David's Acked-by.
v6 and prior version information:
    https://lkml.org/lkml/2013/2/22/475

 arch/arm/Kconfig                  |  1 +
 arch/arm/boot/compressed/Makefile | 15 +++++++++++----
 arch/arm/kernel/armksyms.c        |  4 ++++
 arch/arm/lib/Makefile             |  2 +-
 arch/arm/lib/bswapsdi2.S          | 36 ++++++++++++++++++++++++++++++++++++
 5 files changed, 53 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/lib/bswapsdi2.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a7fc5ea..c2fe04d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -63,6 +63,7 @@ config ARM
 	select OLD_SIGSUSPEND3
 	select OLD_SIGACTION
 	select HAVE_CONTEXT_TRACKING
+	select ARCH_USE_BUILTIN_BSWAP
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 198a4ad..bd8a176 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -112,12 +112,12 @@ endif
 
 targets       := vmlinux vmlinux.lds \
 		 piggy.$(suffix_y) piggy.$(suffix_y).o \
-		 lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S \
-		 font.o font.c head.o misc.o $(OBJS)
+		 lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S bswapsdi2.o \
+		 bswapsdi2.S font.o font.c head.o misc.o $(OBJS)
 
 # Make sure files are removed during clean
 extra-y       += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern piggy.lz4 \
-		 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs)
+		 lib1funcs.S ashldi3.S bswapsdi2.S $(libfdt) $(libfdt_hdrs)
 
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
@@ -159,6 +159,12 @@ ashldi3 = $(obj)/ashldi3.o
 $(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S
 	$(call cmd,shipped)
 
+# For __bswapsi2, __bswapdi2
+bswapsdi2 = $(obj)/bswapsdi2.o
+
+$(obj)/bswapsdi2.S: $(srctree)/arch/$(SRCARCH)/lib/bswapsdi2.S
+	$(call cmd,shipped)
+
 # We need to prevent any GOTOFF relocs being used with references
 # to symbols in the .bss section since we cannot relocate them
 # independently from the rest at run time.  This can be achieved by
@@ -180,7 +186,8 @@ if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" = "" ]; then \
 fi
 
 $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
-		$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) FORCE
+		$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) \
+		$(bswapsdi2) FORCE
 	@$(check_for_multiple_zreladdr)
 	$(call if_changed,ld)
 	@$(check_for_bad_syms)
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 60d3b73..ba578f7 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -35,6 +35,8 @@ extern void __ucmpdi2(void);
 extern void __udivsi3(void);
 extern void __umodsi3(void);
 extern void __do_div64(void);
+extern void __bswapsi2(void);
+extern void __bswapdi2(void);
 
 extern void __aeabi_idiv(void);
 extern void __aeabi_idivmod(void);
@@ -114,6 +116,8 @@ EXPORT_SYMBOL(__ucmpdi2);
 EXPORT_SYMBOL(__udivsi3);
 EXPORT_SYMBOL(__umodsi3);
 EXPORT_SYMBOL(__do_div64);
+EXPORT_SYMBOL(__bswapsi2);
+EXPORT_SYMBOL(__bswapdi2);
 
 #ifdef CONFIG_AEABI
 EXPORT_SYMBOL(__aeabi_idiv);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index af72969..5383df7 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -13,7 +13,7 @@ lib-y		:= backtrace.o changebit.o csumipv6.o csumpartial.o   \
 		   ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \
 		   ucmpdi2.o lib1funcs.o div64.o                      \
 		   io-readsb.o io-writesb.o io-readsl.o io-writesl.o  \
-		   call_with_stack.o
+		   call_with_stack.o bswapsdi2.o
 
 mmu-y	:= clear_user.o copy_page.o getuser.o putuser.o
 
diff --git a/arch/arm/lib/bswapsdi2.S b/arch/arm/lib/bswapsdi2.S
new file mode 100644
index 0000000..2ba43a0
--- /dev/null
+++ b/arch/arm/lib/bswapsdi2.S
@@ -0,0 +1,36 @@
+#include <linux/linkage.h>
+
+#if __LINUX_ARM_ARCH__ >= 6
+ENTRY(__bswapsi2)
+	rev	r0, r0
+	bx	lr
+ENDPROC(__bswapsi2)
+
+ENTRY(__bswapdi2)
+	rev	r3, r0
+	rev	r0, r1
+	mov	r1, r3
+	bx	lr
+ENDPROC(__bswapdi2)
+#else
+ENTRY(__bswapsi2)
+	eor     r3, r0, r0, ror #16
+	mov     r3, r3, lsr #8
+	bic     r3, r3, #0xff00
+	eor     r0, r3, r0, ror #8
+	mov     pc, lr
+ENDPROC(__bswapsi2)
+
+ENTRY(__bswapdi2)
+	mov     ip, r1
+	eor     r3, ip, ip, ror #16
+	eor     r1, r0, r0, ror #16
+	mov     r1, r1, lsr #8
+	mov     r3, r3, lsr #8
+	bic     r3, r3, #0xff00
+	bic     r1, r1, #0xff00
+	eor     r1, r1, r0, ror #8
+	eor     r0, r3, ip, ror #8
+	mov     pc, lr
+ENDPROC(__bswapdi2)
+#endif
-- 
1.8.1.5



From Madhvapathi.Sriram at csr.com  Thu May 23 12:53:38 2013
From: Madhvapathi.Sriram at csr.com (Madhvapathi Sriram)
Date: Thu, 23 May 2013 16:53:38 +0000
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <CAGsJ_4y6BwTpZpwYv0njvqYtp9Y0UU5qhVJhqG5X+8+Hy_LW8Q@mail.gmail.com>
References: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
 <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>,
 <CAGsJ_4y6BwTpZpwYv0njvqYtp9Y0UU5qhVJhqG5X+8+Hy_LW8Q@mail.gmail.com>
Message-ID: <AAD401B65941D44692B7183E6577180803A11BF4@banasiexm01.ASIA.ROOT.PRI>

Agreed Barry. Please ignore my comments on resources management below.

Best Regards,
Madhvapathi Sriram

________________________________________
From: Barry Song [21cnbao at gmail.com]
Sent: Thursday, May 23, 2013 9:47 PM
To: Madhvapathi Sriram
Cc: dtor at mail.ru; dmitry.torokhov at gmail.com; linux-input at vger.kernel.org; DL-SHA-WorkGroupLinux; linux-arm-kernel at lists.infradead.org; Binghua Duan; Xianglong Du; Barry Song
Subject: Re: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR SiRFprimaII PWRC

hi madhvapathi,
thanks for comments.

2013/5/23 Madhvapathi Sriram <Madhvapathi.Sriram at csr.com>:
> Comments inline.
> ________________________________________
> From: Barry Song [21cnbao at gmail.com]
> Sent: Wednesday, May 22, 2013 9:43 PM
> To: dtor at mail.ru; dmitry.torokhov at gmail.com
> Cc: linux-input at vger.kernel.org; DL-SHA-WorkGroupLinux; linux-arm-kernel at lists.infradead.org; Binghua Duan; Xianglong Du; Barry Song
> Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR SiRFprimaII PWRC
>
> From: Binghua Duan <Binghua.Duan at csr.com>
>
> there is an embedded PWRC(power controller) in SiRFprimaII and SiRFatlasVI,
> we have an ONKEY button which can generate interrupt to IRQ controller.
> in a typical user scenarios, at the runtime, if users touch the key, we put
> system to s2ram status.
>
> Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
> Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  drivers/input/misc/Kconfig         |  10 +++
>  drivers/input/misc/Makefile        |   1 +
>  drivers/input/misc/sirfsoc_onkey.c | 176 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 187 insertions(+)
>  create mode 100644 drivers/input/misc/sirfsoc_onkey.c
>
> diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
> index bb698e1..1d91d1b 100644
> --- a/drivers/input/misc/Kconfig
> +++ b/drivers/input/misc/Kconfig
> @@ -637,4 +637,14 @@ config INPUT_XEN_KBDDEV_FRONTEND
>           To compile this driver as a module, choose M here: the
>           module will be called xen-kbdfront.
>
> +config INPUT_SIRFSOC_ONKEY
> +       bool "CSR SiRFSoC power on/off/suspend key support"
> +       depends on ARCH_SIRF
> +       default y
> +       help
> +         Say Y here if you want to support for the SiRFSoC power on/off/suspend key
> +         in Linux, after you press the onkey, system will suspend.
> +
> +         If unsure, say N.
> +
>  endif
> diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
> index d7fc17f..1d66f03 100644
> --- a/drivers/input/misc/Makefile
> +++ b/drivers/input/misc/Makefile
> @@ -60,3 +60,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS)      += wistron_btns.o
>  obj-$(CONFIG_INPUT_WM831X_ON)          += wm831x-on.o
>  obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND)        += xen-kbdfront.o
>  obj-$(CONFIG_INPUT_YEALINK)            += yealink.o
> +obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)      += sirfsoc_onkey.o
> diff --git a/drivers/input/misc/sirfsoc_onkey.c b/drivers/input/misc/sirfsoc_onkey.c
> new file mode 100644
> index 0000000..3e48db9
> --- /dev/null
> +++ b/drivers/input/misc/sirfsoc_onkey.c
> @@ -0,0 +1,176 @@
> +/*
> + * Power key driver for SiRF PrimaII
> + *
> + * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/platform_device.h>
> +#include <linux/input.h>
> +#include <linux/rtc/sirfsoc_rtciobrg.h>
> +#include <linux/of.h>
> +
> +struct sirfsoc_pwrc_drvdata {
> +       u32                     pwrc_base;
> +       int                     irq;
> +       struct input_dev        *input;
> +};
> +
> +#define PWRC_ON_KEY_BIT                        (1 << 0)
> +
> +#define PWRC_INT_STATUS                        0xc
> +#define PWRC_INT_MASK                  0x10
> +
> +static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
> +{
> +       struct sirfsoc_pwrc_drvdata *pwrcdrv =
> +                       (struct sirfsoc_pwrc_drvdata *)dev_id;
> +       u32 int_status;
> +       int_status = sirfsoc_rtc_iobrg_readl(
> +                       pwrcdrv->pwrc_base + PWRC_INT_STATUS);
> +       sirfsoc_rtc_iobrg_writel(int_status & (~PWRC_ON_KEY_BIT),
> +                       pwrcdrv->pwrc_base + PWRC_INT_STATUS);
> +
> +       /*
> +        * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
> +        * to queue a SUSPEND APM event
> +        */
> +       input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
> +       input_sync(pwrcdrv->input);
> +
> +       /*
> +        * Todo: report KEY_POWER event for Android platforms, Android PowerManager
> +        * will handle the suspend and powerdown/hibernation
> +        */
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static const struct of_device_id sirfsoc_pwrc_of_match[] = {
> +       { .compatible = "sirf,prima2-pwrc" },
> +       {},
> +}
> +MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
> +
> +static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> +{
> +       int ret;
> +       struct sirfsoc_pwrc_drvdata *pwrcdrv = NULL;
> +       struct device_node *np = pdev->dev.of_node;
> +
> +       pwrcdrv = devm_kzalloc(&pdev->dev,
> +               sizeof(struct sirfsoc_pwrc_drvdata), GFP_KERNEL);
> +       if (!pwrcdrv) {
> +               dev_info(&pdev->dev, "kzalloc fail!\n");
> +               return -ENOMEM;
> +       }
> +
> +       /*
> +        * we can't use of_iomap because pwrc is not mapped in memory, the so-called base
> +        * address is only offset in rtciobrg
> +        */
> +       ret = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
>
> Possible mem leak here  - not freeing pwrcdrv

no. there is no mem leak here. devm_ means device management resources.

>
> +       if (ret) {
> +               dev_err(&pdev->dev, "unable to find base address of pwrc node in dtb\n");
> +               return ret;
> +       }
> +
> +       pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
> +       if (!pwrcdrv->input)
> +               return -ENOMEM;
> +
> +       pwrcdrv->input->name = "sirfsoc pwrckey";
> +       pwrcdrv->input->phys = "pwrc/input0";
> +
> +       platform_set_drvdata(pdev, pwrcdrv);
> +
> +       pwrcdrv->irq = platform_get_irq(pdev, 0);
> +       ret = devm_request_irq(&pdev->dev, pwrcdrv->irq,
> +                       sirfsoc_pwrc_isr, IRQF_SHARED,
> +                       "sirfsoc_pwrc_int", pwrcdrv);
> +
> +       sirfsoc_rtc_iobrg_writel(
> +               sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK)
> +               | PWRC_ON_KEY_BIT, pwrcdrv->pwrc_base + PWRC_INT_MASK);
>
> Enabling the MASK for an interrupt should only come after it has been successfully claimed? Else we might be leaving and interrupt enabled without being able to handle it?

here moving ahead of request_irq and placing here both work. as there
is another gate in irq controller.

>
> Possible mem leak here not freeing any allocated devices/memory/irq.
> I suggest all the error handling be collated at the end of this function for various stages and error handling be done there.

and we don't need to free devm_irq and devm_mem as well.

> Please have a look at https://www.kernel.org/doc/Documentation/input/input-programming.txt
>
> +       if (ret) {
> +               dev_err(&pdev->dev, "pwrc: Unable to claim irq %d; error %d\n",
> +                       pwrcdrv->irq, ret);
> +               return ret;
> +       }
> +
> +       pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
> +       set_bit(KEY_POWER, pwrcdrv->input->keybit);
> +
> +       ret = input_register_device(pwrcdrv->input);
> +       if (ret) {
> +               dev_err(&pdev->dev,
> +                       "pwrc: Unable to register input device,error: %d\n",
> +                       ret);
> +               return ret;
> +       }
> +
> +       device_init_wakeup(&pdev->dev, 1);
> +
> +       return 0;
> +}
> +
> +static int sirfsoc_pwrc_remove(struct platform_device *pdev)
> +{
> +       device_init_wakeup(&pdev->dev, 0);
> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int pwrc_suspend(struct device *dev)
> +{
> +       return 0;
> +}
> +
> +static int pwrc_resume(struct device *dev)
> +{
> +       struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
> +
>
> Typically, the wake up interrupts would be ensured to be active while going to sleep/suspend.
> However, here at resume the interrupt mask is being set. Is it because, there are some caveats here?

xianglong, pls explain.

>
> +       /*
> +        * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
> +        * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
> +        */
> +       sirfsoc_rtc_iobrg_writel(
> +               sirfsoc_rtc_iobrg_readl(
> +               pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
> +               pwrcdrv->pwrc_base + PWRC_INT_MASK);
> +
> +       return 0;
> +}
> +
> +static const struct dev_pm_ops sirfsoc_pwrc_pm_ops = {
> +       .suspend = pwrc_suspend,
> +       .resume = pwrc_resume,
> +};
> +#endif
> +
> +static struct platform_driver sirfsoc_pwrc_driver = {
> +       .probe          = sirfsoc_pwrc_probe,
> +       .remove         = sirfsoc_pwrc_remove,
> +       .driver         = {
> +               .name   = "sirfsoc-pwrc",
> +               .owner  = THIS_MODULE,
> +#ifdef CONFIG_PM
> +               .pm     = &sirfsoc_pwrc_pm_ops,
> +#endif
> +               .of_match_table = of_match_ptr(sirfsoc_pwrc_of_match),
> +       }
> +};
> +
> +module_platform_driver(sirfsoc_pwrc_driver);
> +
> +MODULE_LICENSE("GPLv2");
> +MODULE_AUTHOR("Binghua Duan <Binghua.Duan at csr.com>, "
> +               "Xianglong Du <Xianglong.Du at csr.com>");
> +MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
> +MODULE_ALIAS("platform:sirfsoc-pwrc");
> --
> 1.8.2.3

-barry


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From bhelgaas at google.com  Thu May 23 13:01:10 2013
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Thu, 23 May 2013 11:01:10 -0600
Subject: [PATCH v2 0/3] Marvell PCIe driver improvements
In-Reply-To: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <CAErSpo6ytq9Tzq_=KucZA+1=90t57QP5-Fw_dus2dXiXL5YKtg@mail.gmail.com>

On Thu, May 23, 2013 at 8:32 AM, Thomas Petazzoni
<thomas.petazzoni at free-electrons.com> wrote:
> Bjorn, Jason, Andrew, Gregory,
>
> Here is an updated version of the PCIe improvements.
>
> Changes since v1:
>
>  * Fix some typos in the comments of PATCH 2, noticed by Bjorn
>    Helgaas.
>
>  * Rework the two last patches (first one was fixing the capability
>    list, the other one the emulation of the devsel bits in the status
>    register), after the comments of Bjorn. In fact, it turns out that
>    the status register is composed of read-only bits for which we want
>    to emulate a value of zero, and the other bits are write-1-to-clear
>    bits that expose error conditions that we do not handle in the
>    emulated bridge. So, in summary, emulating a 0 status register on
>    reads, and ignoring writes to the status register is the simplest
>    solution. If we later on implement a capability list, we can use a
>    more clever emulation of the status register, but for the moment,
>    this simple solution is enough. Therefore, the two last patches are
>    now one single, simpler patch.
>
> I'd like those improvements to be kept separated from the original
> PCIe driver itself: while the PCIe driver has been around and reviewed
> for a long time, those improvements are newer. And I clearly do not
> want the PCIe driver to miss 3.11 because of any problem that could be
> found in those additional improvements.
>
> The main improvement being brought here is that the PCI-to-PCI bridge
> logic is fixed/extended to properly support physical PCIe bridges that
> are connected on a PCIe interface of a Marvell board. Without this
> improvement, only the devices connected directly to the PCIe
> interfaces of the board are properly enumerated. Any device that would
> sit beyond a physical bridge is not visible.
>
> Bjorn, with your Acked-by, could the Marvell maintainers include those
> patches in their branch, merged through arm-soc? They already have the
> Marvell PCIe driver itself, so I believe it makes sense to merge those
> improvements through the same path.
>
> Jason, those patches have been prepared on top of my marvell-pcie-v10
> branch, I hope that's ok for you. If you want me to rebase them on
> some other branch in which you have integrated the PCIe driver, don't
> hesitate to tell me to do so. That said, since those patches are only
> touching the driver itself and no other file, they should not cause
> any conflict with other changes.
>
> Thanks,
>
> Thomas
>
> Thomas Petazzoni (3):
>   pci: mvebu: no longer fake the slot location of downstream devices
>   pci: mvebu: allow the enumeration of devices beyond physical bridges
>   pci: mvebu: fix the emulation of the status register
>
>  drivers/pci/host/pci-mvebu.c |   55 +++++++++++++++++++++++++++++++++---------
>  1 file changed, 44 insertions(+), 11 deletions(-)

For all three:

Acked-by: Bjorn Helgaas <bhelgaas at google.com>

Feel free to merge these through the arm-soc tree or whatever makes
sense for you.  Nobody else is working on this file, so there
shouldn't be any conflicts.

Bjorn


From arnd at arndb.de  Thu May 23 13:01:21 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 19:01:21 +0200
Subject: [RFC V6 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <Pine.LNX.4.44L0.1305231034110.925-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305231034110.925-100000@iolanthe.rowland.org>
Message-ID: <201305231901.21632.arnd@arndb.de>

On Thursday 23 May 2013, Alan Stern wrote:
> On Thu, 23 May 2013, Manjunath Goudar wrote:

> Also, you left out one thing that should still be here.  What happened 
> to the part about changing
> 
> #if	!defined(PCI_DRIVER) &&		\
> 
> to
> 
> #if	!ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\
> 

This section of the driver is gone now since 86510bb248 "USB: OHCI: 
clarify Kconfig dependencies", so the change is no longer needed.

	Arnd


From steve.capper at linaro.org  Thu May 23 13:07:47 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:47 +0100
Subject: [PATCH 00/11] HugeTLB and THP support for ARM64.
Message-ID: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>

This series brings huge pages and transparent huge pages to ARM64.
The functionality is very similar to x86, and a lot of code that can
be used by both ARM64 and x86 is brought into mm to avoid the need
for code duplication.

One notable difference from x86 is that ARM64 supports normal pages
that are 64KB. When 64KB pages are enabled, huge page and
transparent huge pages are 512MB only, otherwise the sizes match
x86.

This series applies to 3.10-rc2.

I've tested this under the ARMv8 Fast model and the x86 code has
been tested in a KVM guest. libhugetlbfs was used for testing under
both architectures.

Changelog:
Patch:
   * pud_large usage replaced with pud_huge for general hugetlb
     code imported into mm.
   * comments tidied up for bit swap of PTE_FILE, PTE_PROT_NONE.

RFC v2:
   * PROT_NONE support added for HugeTLB and THP.
   * pmd_modify implementation fixed.
   * Superfluous huge dcache flushing code removed.
   * Simplified (and corrected) MAX_ORDER raise for THP && 64KB
     pages.
   * The MAX_ORDER check in huge_mm.h has been corrected.

---

Steve Capper (11):
  mm: hugetlb: Copy huge_pmd_share from x86 to mm.
  x86: mm: Remove x86 version of huge_pmd_share.
  mm: hugetlb: Copy general hugetlb code from x86 to mm.
  x86: mm: Remove general hugetlb code from x86.
  mm: thp: Correct the HPAGE_PMD_ORDER check.
  ARM64: mm: Restore memblock limit when map_mem finished.
  ARM64: mm: Make PAGE_NONE pages read only and no-execute.
  ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE bits.
  ARM64: mm: HugeTLB support.
  ARM64: mm: Raise MAX_ORDER for 64KB pages and THP.
  ARM64: mm: THP support.

 arch/arm64/Kconfig                     |  17 +++
 arch/arm64/include/asm/hugetlb.h       | 117 ++++++++++++++++++
 arch/arm64/include/asm/pgtable-hwdef.h |  12 ++
 arch/arm64/include/asm/pgtable.h       |  84 +++++++++++--
 arch/arm64/include/asm/tlb.h           |   6 +
 arch/arm64/include/asm/tlbflush.h      |   2 +
 arch/arm64/mm/Makefile                 |   1 +
 arch/arm64/mm/fault.c                  |  19 +--
 arch/arm64/mm/hugetlbpage.c            |  70 +++++++++++
 arch/arm64/mm/mmu.c                    |  19 ++-
 arch/x86/Kconfig                       |   6 +
 arch/x86/mm/hugetlbpage.c              | 187 ----------------------------
 include/linux/huge_mm.h                |   2 +-
 include/linux/hugetlb.h                |   4 +
 mm/hugetlb.c                           | 219 +++++++++++++++++++++++++++++++--
 15 files changed, 537 insertions(+), 228 deletions(-)
 create mode 100644 arch/arm64/include/asm/hugetlb.h
 create mode 100644 arch/arm64/mm/hugetlbpage.c

-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:51 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:51 +0100
Subject: [PATCH 04/11] x86: mm: Remove general hugetlb code from x86.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-5-git-send-email-steve.capper@linaro.org>

huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d have
already been copied over to mm.

This patch removes the x86 copies of these functions and activates
the general ones by enabling:
CONFIG_ARCH_WANT_GENERAL_HUGETLB

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/x86/Kconfig          |  3 +++
 arch/x86/mm/hugetlbpage.c | 67 -----------------------------------------------
 2 files changed, 3 insertions(+), 67 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 476f786..191c4e3 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -210,6 +210,9 @@ config ARCH_SUSPEND_POSSIBLE
 config ARCH_WANT_HUGE_PMD_SHARE
 	def_bool y
 
+config ARCH_WANT_GENERAL_HUGETLB
+	def_bool y
+
 config ZONE_DMA32
 	bool
 	default X86_64
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index 7e522a3..7e73e8c 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -16,49 +16,6 @@
 #include <asm/tlbflush.h>
 #include <asm/pgalloc.h>
 
-pte_t *huge_pte_alloc(struct mm_struct *mm,
-			unsigned long addr, unsigned long sz)
-{
-	pgd_t *pgd;
-	pud_t *pud;
-	pte_t *pte = NULL;
-
-	pgd = pgd_offset(mm, addr);
-	pud = pud_alloc(mm, pgd, addr);
-	if (pud) {
-		if (sz == PUD_SIZE) {
-			pte = (pte_t *)pud;
-		} else {
-			BUG_ON(sz != PMD_SIZE);
-			if (pud_none(*pud))
-				pte = huge_pmd_share(mm, addr, pud);
-			else
-				pte = (pte_t *)pmd_alloc(mm, pud, addr);
-		}
-	}
-	BUG_ON(pte && !pte_none(*pte) && !pte_huge(*pte));
-
-	return pte;
-}
-
-pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
-{
-	pgd_t *pgd;
-	pud_t *pud;
-	pmd_t *pmd = NULL;
-
-	pgd = pgd_offset(mm, addr);
-	if (pgd_present(*pgd)) {
-		pud = pud_offset(pgd, addr);
-		if (pud_present(*pud)) {
-			if (pud_large(*pud))
-				return (pte_t *)pud;
-			pmd = pmd_offset(pud, addr);
-		}
-	}
-	return (pte_t *) pmd;
-}
-
 #if 0	/* This is just for testing */
 struct page *
 follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
@@ -120,30 +77,6 @@ int pud_huge(pud_t pud)
 	return !!(pud_val(pud) & _PAGE_PSE);
 }
 
-struct page *
-follow_huge_pmd(struct mm_struct *mm, unsigned long address,
-		pmd_t *pmd, int write)
-{
-	struct page *page;
-
-	page = pte_page(*(pte_t *)pmd);
-	if (page)
-		page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
-	return page;
-}
-
-struct page *
-follow_huge_pud(struct mm_struct *mm, unsigned long address,
-		pud_t *pud, int write)
-{
-	struct page *page;
-
-	page = pte_page(*(pte_t *)pud);
-	if (page)
-		page += ((address & ~PUD_MASK) >> PAGE_SHIFT);
-	return page;
-}
-
 #endif
 
 /* x86_64 also uses this file */
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:49 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:49 +0100
Subject: [PATCH 02/11] x86: mm: Remove x86 version of huge_pmd_share.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-3-git-send-email-steve.capper@linaro.org>

The huge_pmd_share code has been copied over to mm/hugetlb.c to
make it accessible to other architectures.

Remove the x86 copy of the huge_pmd_share code and enable the
ARCH_WANT_HUGE_PMD_SHARE config flag. That way we reference the
general one.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/x86/Kconfig          |   3 ++
 arch/x86/mm/hugetlbpage.c | 120 ----------------------------------------------
 2 files changed, 3 insertions(+), 120 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 685692c..476f786 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -207,6 +207,9 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
 	def_bool y
 
+config ARCH_WANT_HUGE_PMD_SHARE
+	def_bool y
+
 config ZONE_DMA32
 	bool
 	default X86_64
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index ae1aa71..7e522a3 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -16,126 +16,6 @@
 #include <asm/tlbflush.h>
 #include <asm/pgalloc.h>
 
-static unsigned long page_table_shareable(struct vm_area_struct *svma,
-				struct vm_area_struct *vma,
-				unsigned long addr, pgoff_t idx)
-{
-	unsigned long saddr = ((idx - svma->vm_pgoff) << PAGE_SHIFT) +
-				svma->vm_start;
-	unsigned long sbase = saddr & PUD_MASK;
-	unsigned long s_end = sbase + PUD_SIZE;
-
-	/* Allow segments to share if only one is marked locked */
-	unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED;
-	unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED;
-
-	/*
-	 * match the virtual addresses, permission and the alignment of the
-	 * page table page.
-	 */
-	if (pmd_index(addr) != pmd_index(saddr) ||
-	    vm_flags != svm_flags ||
-	    sbase < svma->vm_start || svma->vm_end < s_end)
-		return 0;
-
-	return saddr;
-}
-
-static int vma_shareable(struct vm_area_struct *vma, unsigned long addr)
-{
-	unsigned long base = addr & PUD_MASK;
-	unsigned long end = base + PUD_SIZE;
-
-	/*
-	 * check on proper vm_flags and page table alignment
-	 */
-	if (vma->vm_flags & VM_MAYSHARE &&
-	    vma->vm_start <= base && end <= vma->vm_end)
-		return 1;
-	return 0;
-}
-
-/*
- * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
- * and returns the corresponding pte. While this is not necessary for the
- * !shared pmd case because we can allocate the pmd later as well, it makes the
- * code much cleaner. pmd allocation is essential for the shared case because
- * pud has to be populated inside the same i_mmap_mutex section - otherwise
- * racing tasks could either miss the sharing (see huge_pte_offset) or select a
- * bad pmd for sharing.
- */
-static pte_t *
-huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
-{
-	struct vm_area_struct *vma = find_vma(mm, addr);
-	struct address_space *mapping = vma->vm_file->f_mapping;
-	pgoff_t idx = ((addr - vma->vm_start) >> PAGE_SHIFT) +
-			vma->vm_pgoff;
-	struct vm_area_struct *svma;
-	unsigned long saddr;
-	pte_t *spte = NULL;
-	pte_t *pte;
-
-	if (!vma_shareable(vma, addr))
-		return (pte_t *)pmd_alloc(mm, pud, addr);
-
-	mutex_lock(&mapping->i_mmap_mutex);
-	vma_interval_tree_foreach(svma, &mapping->i_mmap, idx, idx) {
-		if (svma == vma)
-			continue;
-
-		saddr = page_table_shareable(svma, vma, addr, idx);
-		if (saddr) {
-			spte = huge_pte_offset(svma->vm_mm, saddr);
-			if (spte) {
-				get_page(virt_to_page(spte));
-				break;
-			}
-		}
-	}
-
-	if (!spte)
-		goto out;
-
-	spin_lock(&mm->page_table_lock);
-	if (pud_none(*pud))
-		pud_populate(mm, pud, (pmd_t *)((unsigned long)spte & PAGE_MASK));
-	else
-		put_page(virt_to_page(spte));
-	spin_unlock(&mm->page_table_lock);
-out:
-	pte = (pte_t *)pmd_alloc(mm, pud, addr);
-	mutex_unlock(&mapping->i_mmap_mutex);
-	return pte;
-}
-
-/*
- * unmap huge page backed by shared pte.
- *
- * Hugetlb pte page is ref counted at the time of mapping.  If pte is shared
- * indicated by page_count > 1, unmap is achieved by clearing pud and
- * decrementing the ref count. If count == 1, the pte page is not shared.
- *
- * called with vma->vm_mm->page_table_lock held.
- *
- * returns: 1 successfully unmapped a shared pte page
- *	    0 the underlying pte page is not shared, or it is the last user
- */
-int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
-{
-	pgd_t *pgd = pgd_offset(mm, *addr);
-	pud_t *pud = pud_offset(pgd, *addr);
-
-	BUG_ON(page_count(virt_to_page(ptep)) == 0);
-	if (page_count(virt_to_page(ptep)) == 1)
-		return 0;
-
-	pud_clear(pud);
-	put_page(virt_to_page(ptep));
-	*addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
-	return 1;
-}
-
 pte_t *huge_pte_alloc(struct mm_struct *mm,
 			unsigned long addr, unsigned long sz)
 {
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:52 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:52 +0100
Subject: [PATCH 05/11] mm: thp: Correct the HPAGE_PMD_ORDER check.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-6-git-send-email-steve.capper@linaro.org>

All Transparent Huge Pages are allocated by the buddy allocator.

A compile time check is in place that fails when the order of a
transparent huge page is too large to be allocated by the buddy
allocator. Unfortunately that compile time check passes when:
HPAGE_PMD_ORDER == MAX_ORDER
( which is incorrect as the buddy allocator can only allocate
memory of order strictly less than MAX_ORDER. )

This patch updates the compile time check to fail in the above
case.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 include/linux/huge_mm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h
index 528454c..26ee56c 100644
--- a/include/linux/huge_mm.h
+++ b/include/linux/huge_mm.h
@@ -123,7 +123,7 @@ extern void __split_huge_page_pmd(struct vm_area_struct *vma,
 	} while (0)
 extern void split_huge_page_pmd_mm(struct mm_struct *mm, unsigned long address,
 		pmd_t *pmd);
-#if HPAGE_PMD_ORDER > MAX_ORDER
+#if HPAGE_PMD_ORDER >= MAX_ORDER
 #error "hugepages can't be allocated by the buddy allocator"
 #endif
 extern int hugepage_madvise(struct vm_area_struct *vma,
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:54 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:54 +0100
Subject: [PATCH 07/11] ARM64: mm: Make PAGE_NONE pages read only and
 no-execute.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-8-git-send-email-steve.capper@linaro.org>

If we consider the following code sequence:

	my_pte = pte_modify(entry, myprot);
	x = pte_write(my_pte);
	y = pte_exec(my_pte);

If myprot comes from a PROT_NONE page, then x and y will both be
true which is undesireable behaviour.

This patch sets the no-execute and read-only bits for PAGE_NONE
such that the code above will return false for both x and y.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/include/asm/pgtable.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e333a24..77b09d6 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -66,7 +66,7 @@ extern pgprot_t pgprot_default;
 
 #define _MOD_PROT(p, b)		__pgprot_modify(p, 0, b)
 
-#define PAGE_NONE		__pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE)
+#define PAGE_NONE		__pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_RDONLY | PTE_PXN | PTE_UXN)
 #define PAGE_SHARED		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
 #define PAGE_COPY		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
@@ -76,7 +76,7 @@ extern pgprot_t pgprot_default;
 #define PAGE_KERNEL		_MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
 #define PAGE_KERNEL_EXEC	_MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
 
-#define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
+#define __PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_RDONLY | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
 #define __PAGE_COPY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:48 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:48 +0100
Subject: [PATCH 01/11] mm: hugetlb: Copy huge_pmd_share from x86 to mm.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-2-git-send-email-steve.capper@linaro.org>

Under x86, multiple puds can be made to reference the same bank of
huge pmds provided that they represent a full PUD_SIZE of shared
huge memory that is aligned to a PUD_SIZE boundary.

The code to share pmds does not require any architecture specific
knowledge other than the fact that pmds can be indexed, thus can
be beneficial to some other architectures.

This patch copies the huge pmd sharing (and unsharing) logic from
x86/ to mm/ and introduces a new config option to activate it:
CONFIG_ARCH_WANTS_HUGE_PMD_SHARE

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 include/linux/hugetlb.h |   4 ++
 mm/hugetlb.c            | 122 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 126 insertions(+)

diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 6b4890f..981546a 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -69,6 +69,10 @@ void hugetlb_unreserve_pages(struct inode *inode, long offset, long freed);
 int dequeue_hwpoisoned_huge_page(struct page *page);
 void copy_huge_page(struct page *dst, struct page *src);
 
+#ifdef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud);
+#endif
+
 extern unsigned long hugepages_treat_as_movable;
 extern const unsigned long hugetlb_zero, hugetlb_infinity;
 extern int sysctl_hugetlb_shm_group;
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index f8feeec..b0bfb29 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -3169,6 +3169,128 @@ void hugetlb_unreserve_pages(struct inode *inode, long offset, long freed)
 	hugetlb_acct_memory(h, -(chg - freed));
 }
 
+#ifdef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+static unsigned long page_table_shareable(struct vm_area_struct *svma,
+				struct vm_area_struct *vma,
+				unsigned long addr, pgoff_t idx)
+{
+	unsigned long saddr = ((idx - svma->vm_pgoff) << PAGE_SHIFT) +
+				svma->vm_start;
+	unsigned long sbase = saddr & PUD_MASK;
+	unsigned long s_end = sbase + PUD_SIZE;
+
+	/* Allow segments to share if only one is marked locked */
+	unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED;
+	unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED;
+
+	/*
+	 * match the virtual addresses, permission and the alignment of the
+	 * page table page.
+	 */
+	if (pmd_index(addr) != pmd_index(saddr) ||
+	    vm_flags != svm_flags ||
+	    sbase < svma->vm_start || svma->vm_end < s_end)
+		return 0;
+
+	return saddr;
+}
+
+static int vma_shareable(struct vm_area_struct *vma, unsigned long addr)
+{
+	unsigned long base = addr & PUD_MASK;
+	unsigned long end = base + PUD_SIZE;
+
+	/*
+	 * check on proper vm_flags and page table alignment
+	 */
+	if (vma->vm_flags & VM_MAYSHARE &&
+	    vma->vm_start <= base && end <= vma->vm_end)
+		return 1;
+	return 0;
+}
+
+/*
+ * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
+ * and returns the corresponding pte. While this is not necessary for the
+ * !shared pmd case because we can allocate the pmd later as well, it makes the
+ * code much cleaner. pmd allocation is essential for the shared case because
+ * pud has to be populated inside the same i_mmap_mutex section - otherwise
+ * racing tasks could either miss the sharing (see huge_pte_offset) or select a
+ * bad pmd for sharing.
+ */
+pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
+{
+	struct vm_area_struct *vma = find_vma(mm, addr);
+	struct address_space *mapping = vma->vm_file->f_mapping;
+	pgoff_t idx = ((addr - vma->vm_start) >> PAGE_SHIFT) +
+			vma->vm_pgoff;
+	struct vm_area_struct *svma;
+	unsigned long saddr;
+	pte_t *spte = NULL;
+	pte_t *pte;
+
+	if (!vma_shareable(vma, addr))
+		return (pte_t *)pmd_alloc(mm, pud, addr);
+
+	mutex_lock(&mapping->i_mmap_mutex);
+	vma_interval_tree_foreach(svma, &mapping->i_mmap, idx, idx) {
+		if (svma == vma)
+			continue;
+
+		saddr = page_table_shareable(svma, vma, addr, idx);
+		if (saddr) {
+			spte = huge_pte_offset(svma->vm_mm, saddr);
+			if (spte) {
+				get_page(virt_to_page(spte));
+				break;
+			}
+		}
+	}
+
+	if (!spte)
+		goto out;
+
+	spin_lock(&mm->page_table_lock);
+	if (pud_none(*pud))
+		pud_populate(mm, pud,
+				(pmd_t *)((unsigned long)spte & PAGE_MASK));
+	else
+		put_page(virt_to_page(spte));
+	spin_unlock(&mm->page_table_lock);
+out:
+	pte = (pte_t *)pmd_alloc(mm, pud, addr);
+	mutex_unlock(&mapping->i_mmap_mutex);
+	return pte;
+}
+
+/*
+ * unmap huge page backed by shared pte.
+ *
+ * Hugetlb pte page is ref counted at the time of mapping.  If pte is shared
+ * indicated by page_count > 1, unmap is achieved by clearing pud and
+ * decrementing the ref count. If count == 1, the pte page is not shared.
+ *
+ * called with vma->vm_mm->page_table_lock held.
+ *
+ * returns: 1 successfully unmapped a shared pte page
+ *	    0 the underlying pte page is not shared, or it is the last user
+ */
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+	pgd_t *pgd = pgd_offset(mm, *addr);
+	pud_t *pud = pud_offset(pgd, *addr);
+
+	BUG_ON(page_count(virt_to_page(ptep)) == 0);
+	if (page_count(virt_to_page(ptep)) == 1)
+		return 0;
+
+	pud_clear(pud);
+	put_page(virt_to_page(ptep));
+	*addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
+	return 1;
+}
+#endif /* CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
+
 #ifdef CONFIG_MEMORY_FAILURE
 
 /* Should be called in hugetlb_lock */
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:50 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:50 +0100
Subject: [PATCH 03/11] mm: hugetlb: Copy general hugetlb code from x86 to mm.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-4-git-send-email-steve.capper@linaro.org>

The huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d
functions in x86/mm/hugetlbpage.c do not rely on any architecture
specific knowledge other than the fact that pmds and puds can be
treated as huge ptes.

To allow other architectures to use this code (and reduce the need
for code duplication), this patch copies these functions into mm,
replaces the use of pud_large with pud_huge and provides a config
flag to activate them:
CONFIG_ARCH_WANT_GENERAL_HUGETLB

If CONFIG_ARCH_WANT_HUGE_PMD_SHARE is also active then the
huge_pmd_share code will be called by huge_pte_alloc (othewise we
call pmd_alloc and skip the sharing code).

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 mm/hugetlb.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 88 insertions(+), 9 deletions(-)

diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index b0bfb29..6321726 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -2931,15 +2931,6 @@ out_mutex:
 	return ret;
 }
 
-/* Can be overriden by architectures */
-__attribute__((weak)) struct page *
-follow_huge_pud(struct mm_struct *mm, unsigned long address,
-	       pud_t *pud, int write)
-{
-	BUG();
-	return NULL;
-}
-
 long follow_hugetlb_page(struct mm_struct *mm, struct vm_area_struct *vma,
 			 struct page **pages, struct vm_area_struct **vmas,
 			 unsigned long *position, unsigned long *nr_pages,
@@ -3289,8 +3280,96 @@ int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
 	*addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
 	return 1;
 }
+#define want_pmd_share()	(1)
+#else /* !CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
+pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
+{
+	return NULL;
+}
+#define want_pmd_share()	(0)
 #endif /* CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
 
+#ifdef CONFIG_ARCH_WANT_GENERAL_HUGETLB
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+			unsigned long addr, unsigned long sz)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pte_t *pte = NULL;
+
+	pgd = pgd_offset(mm, addr);
+	pud = pud_alloc(mm, pgd, addr);
+	if (pud) {
+		if (sz == PUD_SIZE) {
+			pte = (pte_t *)pud;
+		} else {
+			BUG_ON(sz != PMD_SIZE);
+			if (want_pmd_share() && pud_none(*pud))
+				pte = huge_pmd_share(mm, addr, pud);
+			else
+				pte = (pte_t *)pmd_alloc(mm, pud, addr);
+		}
+	}
+	BUG_ON(pte && !pte_none(*pte) && !pte_huge(*pte));
+
+	return pte;
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd = NULL;
+
+	pgd = pgd_offset(mm, addr);
+	if (pgd_present(*pgd)) {
+		pud = pud_offset(pgd, addr);
+		if (pud_present(*pud)) {
+			if (pud_huge(*pud))
+				return (pte_t *)pud;
+			pmd = pmd_offset(pud, addr);
+		}
+	}
+	return (pte_t *) pmd;
+}
+
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+		pmd_t *pmd, int write)
+{
+	struct page *page;
+
+	page = pte_page(*(pte_t *)pmd);
+	if (page)
+		page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
+	return page;
+}
+
+struct page *
+follow_huge_pud(struct mm_struct *mm, unsigned long address,
+		pud_t *pud, int write)
+{
+	struct page *page;
+
+	page = pte_page(*(pte_t *)pud);
+	if (page)
+		page += ((address & ~PUD_MASK) >> PAGE_SHIFT);
+	return page;
+}
+
+#else /* !CONFIG_ARCH_WANT_GENERAL_HUGETLB */
+
+/* Can be overriden by architectures */
+__attribute__((weak)) struct page *
+follow_huge_pud(struct mm_struct *mm, unsigned long address,
+	       pud_t *pud, int write)
+{
+	BUG();
+	return NULL;
+}
+
+#endif /* CONFIG_ARCH_WANT_GENERAL_HUGETLB */
+
 #ifdef CONFIG_MEMORY_FAILURE
 
 /* Should be called in hugetlb_lock */
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:53 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:53 +0100
Subject: [PATCH 06/11] ARM64: mm: Restore memblock limit when map_mem finished.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-7-git-send-email-steve.capper@linaro.org>

In paging_init the memblock limit is set to restrict any addresses
returned by early_alloc to fit within the initial direct kernel
mapping in swapper_pg_dir. This allows map_mem to allocate puds,
pmds and ptes from the initial direct kernel mapping.

The limit stays low after paging_init() though, meaning any
bootmem allocations will be from a restricted subset of memory.
Gigabyte huge pages, for instance, are normally allocated from
bootmem as their order (18) is too large for the default buddy
allocator (MAX_ORDER = 11).

This patch restores the memblock limit when map_mem has finished,
allowing gigabyte huge pages (and other objects) to be allocated
from all of bootmem.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/mm/mmu.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index eeecc9c..9fa027b 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -297,6 +297,16 @@ static void __init map_mem(void)
 {
 	struct memblock_region *reg;
 
+	/*
+	 * Temporarily limit the memblock range. We need to do this as
+	 * create_mapping requires puds, pmds and ptes to be allocated from
+	 * memory addressable from the initial direct kernel mapping.
+	 *
+	 * The initial direct kernel mapping, located at swapper_pg_dir,
+	 * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (aligned).
+	 */
+	memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
+
 	/* map all the memory banks */
 	for_each_memblock(memory, reg) {
 		phys_addr_t start = reg->base;
@@ -307,6 +317,9 @@ static void __init map_mem(void)
 
 		create_mapping(start, __phys_to_virt(start), end - start);
 	}
+
+	/* Limit no longer required. */
+	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 }
 
 /*
@@ -317,12 +330,6 @@ void __init paging_init(void)
 {
 	void *zero_page;
 
-	/*
-	 * Maximum PGDIR_SIZE addressable via the initial direct kernel
-	 * mapping in swapper_pg_dir.
-	 */
-	memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
-
 	init_mem_pgprot();
 	map_mem();
 
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:57 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:57 +0100
Subject: [PATCH 10/11] ARM64: mm: Raise MAX_ORDER for 64KB pages and THP.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-11-git-send-email-steve.capper@linaro.org>

The buddy allocator has a default MAX_ORDER of 11, which is too
low to allocate enough memory for 512MB Transparent HugePages if
our base page size is 64KB.

This patch introduces MAX_ZONE_ORDER and sets it to 14 when 64KB
pages are used in conjuction with THP, otherwise the default value
of 11 is used.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index cd6eca8..10607d6 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -191,6 +191,11 @@ config ARCH_WANT_HUGE_PMD_SHARE
 
 source "mm/Kconfig"
 
+config FORCE_MAX_ZONEORDER
+	int
+	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
+	default "11"
+
 endmenu
 
 menu "Boot options"
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:56 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:56 +0100
Subject: [PATCH 09/11] ARM64: mm: HugeTLB support.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-10-git-send-email-steve.capper@linaro.org>

Add huge page support to ARM64, different huge page sizes are
supported depending on the size of normal pages:

PAGE_SIZE is 4KB:
   2MB - (pmds) these can be allocated at any time.
1024MB - (puds) usually allocated on bootup with the command line
         with something like: hugepagesz=1G hugepages=6

PAGE_SIZE is 64KB:
 512MB - (pmds) usually allocated on bootup via command line.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
---
 arch/arm64/Kconfig                     |   9 +++
 arch/arm64/include/asm/hugetlb.h       | 117 +++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/pgtable-hwdef.h |   8 +++
 arch/arm64/include/asm/pgtable.h       |  13 +++-
 arch/arm64/mm/Makefile                 |   1 +
 arch/arm64/mm/fault.c                  |  19 ++----
 arch/arm64/mm/hugetlbpage.c            |  70 ++++++++++++++++++++
 7 files changed, 220 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm64/include/asm/hugetlb.h
 create mode 100644 arch/arm64/mm/hugetlbpage.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 56b3f6d..cd6eca8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,15 @@ config HW_PERF_EVENTS
 	  Enable hardware performance counter support for perf events. If
 	  disabled, perf events will use software events only.
 
+config SYS_SUPPORTS_HUGETLBFS
+	def_bool y
+
+config ARCH_WANT_GENERAL_HUGETLB
+	def_bool y
+
+config ARCH_WANT_HUGE_PMD_SHARE
+	def_bool y if !ARM64_64K_PAGES
+
 source "mm/Kconfig"
 
 endmenu
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
new file mode 100644
index 0000000..5b7ca8a
--- /dev/null
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm64/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_HUGETLB_H
+#define __ASM_HUGETLB_H
+
+#include <asm-generic/hugetlb.h>
+#include <asm/page.h>
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+	return *ptep;
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+				   pte_t *ptep, pte_t pte)
+{
+	set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+					 unsigned long addr, pte_t *ptep)
+{
+	ptep_clear_flush(vma, addr, ptep);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+					   unsigned long addr, pte_t *ptep)
+{
+	ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+					    unsigned long addr, pte_t *ptep)
+{
+	return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+					     unsigned long addr, pte_t *ptep,
+					     pte_t pte, int dirty)
+{
+	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+					  unsigned long addr, unsigned long end,
+					  unsigned long floor,
+					  unsigned long ceiling)
+{
+	free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+					 unsigned long addr, unsigned long len)
+{
+	return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+					 unsigned long addr, unsigned long len)
+{
+	struct hstate *h = hstate_file(file);
+	if (len & ~huge_page_mask(h))
+		return -EINVAL;
+	if (addr & ~huge_page_mask(h))
+		return -EINVAL;
+	return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+	return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+	return pte_wrprotect(pte);
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+	return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+	clear_bit(PG_dcache_clean, &page->flags);
+}
+
+#endif /* __ASM_HUGETLB_H */
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 75fd13d..e6e0a0d 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -25,12 +25,19 @@
 /*
  * Hardware page table definitions.
  *
+ * Level 1 descriptor (PUD).
+ */
+
+#define PUD_TABLE_BIT		(_AT(pgdval_t, 1) << 1)
+
+/*
  * Level 2 descriptor (PMD).
  */
 #define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
 
 /*
  * Section
@@ -53,6 +60,7 @@
 #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
 #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
 #define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
 #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 8867282..7476896 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -173,8 +173,17 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 /*
  * Huge pte definitions.
  */
-#define pte_huge(pte)		((pte_val(pte) & PTE_TYPE_MASK) == PTE_TYPE_HUGEPAGE)
-#define pte_mkhuge(pte)		(__pte((pte_val(pte) & ~PTE_TYPE_MASK) | PTE_TYPE_HUGEPAGE))
+#define pte_huge(pte)		(!(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+
+/*
+ * Hugetlb definitions.
+ */
+#define HUGE_MAX_HSTATE		2
+#define HPAGE_SHIFT		PMD_SHIFT
+#define HPAGE_SIZE		(_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
 
 #define __HAVE_ARCH_PTE_SPECIAL
 
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index 3140a2a..b51d364 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -2,3 +2,4 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
 				   cache.o copypage.o flush.o \
 				   ioremap.o mmap.o pgd.o mmu.o \
 				   context.o tlb.o proc.o
+obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 98af6e7..29bf387 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -364,17 +364,6 @@ static int __kprobes do_translation_fault(unsigned long addr,
 }
 
 /*
- * Some section permission faults need to be handled gracefully.  They can
- * happen due to a __{get,put}_user during an oops.
- */
-static int do_sect_fault(unsigned long addr, unsigned int esr,
-			 struct pt_regs *regs)
-{
-	do_bad_area(addr, esr, regs);
-	return 0;
-}
-
-/*
  * This abort handler always returns "fault".
  */
 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
@@ -397,12 +386,12 @@ static struct fault_info {
 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 2 translation fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved access flag fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 access flag fault"	},
 	{ do_bad,		SIGBUS,  0,		"reserved permission fault"	},
-	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
-	{ do_sect_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 permission fault"	},
 	{ do_bad,		SIGBUS,  0,		"synchronous external abort"	},
 	{ do_bad,		SIGBUS,  0,		"asynchronous external abort"	},
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
new file mode 100644
index 0000000..2fc8258
--- /dev/null
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -0,0 +1,70 @@
+/*
+ * arch/arm64/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * Based on arch/x86/mm/hugetlbpage.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+#ifndef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+	return 0;
+}
+#endif
+
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+			      int write)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+int pmd_huge(pmd_t pmd)
+{
+	return !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
+
+int pud_huge(pud_t pud)
+{
+	return !(pud_val(pud) & PUD_TABLE_BIT);
+}
+
+static __init int setup_hugepagesz(char *opt)
+{
+	unsigned long ps = memparse(opt, &opt);
+	if (ps == PMD_SIZE) {
+		hugetlb_add_hstate(PMD_SHIFT - PAGE_SHIFT);
+	} else if (ps == PUD_SIZE) {
+		hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT);
+	} else {
+		pr_err("hugepagesz: Unsupported page size %lu M\n", ps >> 20);
+		return 0;
+	}
+	return 1;
+}
+__setup("hugepagesz=", setup_hugepagesz);
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:58 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:58 +0100
Subject: [PATCH 11/11] ARM64: mm: THP support.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-12-git-send-email-steve.capper@linaro.org>

Bring Transparent HugePage support to ARM. The size of a
transparent huge page depends on the normal page size. A
transparent huge page is always represented as a pmd.

If PAGE_SIZE is 4KB, THPs are 2MB.
If PAGE_SIZE is 64KB, THPs are 512MB.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/Kconfig                     |  3 ++
 arch/arm64/include/asm/pgtable-hwdef.h |  4 +++
 arch/arm64/include/asm/pgtable.h       | 55 ++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/tlb.h           |  6 ++++
 arch/arm64/include/asm/tlbflush.h      |  2 ++
 5 files changed, 70 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 10607d6..308a556 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -189,6 +189,9 @@ config ARCH_WANT_GENERAL_HUGETLB
 config ARCH_WANT_HUGE_PMD_SHARE
 	def_bool y if !ARM64_64K_PAGES
 
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+	def_bool y
+
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index e6e0a0d..63c9d0d 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -42,6 +42,10 @@
 /*
  * Section
  */
+#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_PROT_NONE	(_AT(pmdval_t, 1) << 2)
+#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
+#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
 #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 7476896..33a0d31 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -188,6 +188,61 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 #define __HAVE_ARCH_PTE_SPECIAL
 
 /*
+ * Software PMD bits for THP
+ */
+
+#define PMD_SECT_DIRTY		(_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING	(_AT(pmdval_t, 1) << 57)
+
+/*
+ * THP definitions.
+ */
+#define pmd_young(pmd)		(pmd_val(pmd) & PMD_SECT_AF)
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)		(!(pmd_val(pmd) & PMD_SECT_RDONLY))
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)	(pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+
+PMD_BIT_FUNC(wrprotect,	|= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,	&= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+PMD_BIT_FUNC(mknotpresent, &= ~PMD_TYPE_MASK);
+
+#define pmd_mkhuge(pmd)		(__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+
+#define pmd_pfn(pmd)		(((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)	(__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)	pfn_pmd(page_to_pfn(page),prot)
+
+#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+	const pmdval_t mask = PMD_SECT_USER | PMD_SECT_PXN | PMD_SECT_UXN |
+			      PMD_SECT_RDONLY | PMD_SECT_PROT_NONE |
+			      PMD_SECT_VALID;
+	pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+	return pmd;
+}
+
+#define set_pmd_at(mm, addr, pmdp, pmd)	set_pmd(pmdp, pmd)
+
+static inline int has_transparent_hugepage(void)
+{
+	return 1;
+}
+
+/*
  * Mark the prot value as uncacheable and unbufferable.
  */
 #define pgprot_noncached(prot) \
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 654f096..46b3beb 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -187,4 +187,10 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 
 #define tlb_migrate_finish(mm)		do { } while (0)
 
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+	tlb_add_flush(tlb, addr);
+}
+
 #endif
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 122d632..8b48203 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -117,6 +117,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 	dsb();
 }
 
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
+
 #endif
 
 #endif
-- 
1.8.1.4



From steve.capper at linaro.org  Thu May 23 13:07:55 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Thu, 23 May 2013 18:07:55 +0100
Subject: [PATCH 08/11] ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE bits.
In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
Message-ID: <1369328878-11706-9-git-send-email-steve.capper@linaro.org>

Under ARM64, PTEs can be broadly categorised as follows:
   - Present and valid: Bit #0 is set. The PTE is valid and memory
     access to the region may fault.

   - Present and invalid: Bit #0 is clear and bit #1 is set.
     Represents present memory with PROT_NONE protection. The PTE
     is an invalid entry, and the user fault handler will raise a
     SIGSEGV.

   - Not present (file): Bits #0 and #1 are clear, bit #2 is set.
     Memory represented has been paged out. The PTE is an invalid
     entry, and the fault handler will try and re-populate the
     memory where necessary.

Huge PTEs are block descriptors that have bit #1 clear. If we wish
to represent PROT_NONE huge PTEs we then run into a problem as
there is no way to distinguish between regular and huge PTEs if we
set bit #1.

As huge PTEs are always present, the meaning of bits #1 and #2 can
be swapped for invalid PTEs. This patch swaps the PTE_FILE and
PTE_PROT_NONE constants, allowing us to represent PROT_NONE huge
PTEs.

Signed-off-by: Steve Capper <steve.capper at linaro.org>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/pgtable.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 77b09d6..8867282 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -25,8 +25,8 @@
  * Software defined PTE bits definition.
  */
 #define PTE_VALID		(_AT(pteval_t, 1) << 0)
-#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 1)	/* only when !PTE_VALID */
-#define PTE_FILE		(_AT(pteval_t, 1) << 2)	/* only when !pte_present() */
+#define PTE_FILE		(_AT(pteval_t, 1) << 1)	/* only when !pte_present() */
+#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 2)	/* only when !PTE_VALID */
 #define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
 #define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
 
@@ -281,8 +281,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 
 /*
  * Encode and decode a swap entry:
- *	bits 0-1:	present (must be zero)
- *	bit  2:		PTE_FILE
+ *	bits 0, 2:	present (must both be zero)
+ *	bit  1:		PTE_FILE
  *	bits 3-8:	swap type
  *	bits 9-63:	swap offset
  */
@@ -306,8 +306,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 
 /*
  * Encode and decode a file entry:
- *	bits 0-1:	present (must be zero)
- *	bit  2:		PTE_FILE
+ *	bits 0, 2:	present (must both be zero)
+ *	bit  1:		PTE_FILE
  *	bits 3-63:	file offset / PAGE_SIZE
  */
 #define pte_file(pte)		(pte_val(pte) & PTE_FILE)
-- 
1.8.1.4



From jgunthorpe at obsidianresearch.com  Thu May 23 13:11:12 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 23 May 2013 11:11:12 -0600
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130523160111.GP31290@titan.lakedaemon.net>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
Message-ID: <20130523171112.GB31281@obsidianresearch.com>

On Thu, May 23, 2013 at 12:01:11PM -0400, Jason Cooper wrote:
> > > +	/* Kirkwood resets some registers on gated clocks. Especially
> > > +	 * CLK125_BYPASS_EN must be cleared but is not available on
> > > +	 * all other SoCs/System Controllers using this driver.
> > > +	 */
> > > +	if (of_machine_is_compatible("marvell,kirkwood"))
> > > +		wrlp(mp, PORT_SERIAL_CONTROL1,
> > > +		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
> > 
> > of_machine_is_compatible seems heavy handed, I would expect this to be
> > based on the compatible string of the ethernet node itself, not the
> > machine??
> 
> Is there a model number variation between IP that needs this and IP that
> doesn't?  If not, I'm fine with of_machine_is_compatible().

Well the name 'mv643xx' is a family of system controller SOC's
from ages ago, it seems reasonble to continue the trend and label the
IP variations with the SOC name:

 compatible = "marvell,kirwood,ethernet", "marvell,mv643xx_eth"

Jason


From jason at lakedaemon.net  Thu May 23 13:23:39 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 13:23:39 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130523171112.GB31281@obsidianresearch.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
Message-ID: <20130523172339.GQ31290@titan.lakedaemon.net>

On Thu, May 23, 2013 at 11:11:12AM -0600, Jason Gunthorpe wrote:
> On Thu, May 23, 2013 at 12:01:11PM -0400, Jason Cooper wrote:
> > > > +	/* Kirkwood resets some registers on gated clocks. Especially
> > > > +	 * CLK125_BYPASS_EN must be cleared but is not available on
> > > > +	 * all other SoCs/System Controllers using this driver.
> > > > +	 */
> > > > +	if (of_machine_is_compatible("marvell,kirkwood"))
> > > > +		wrlp(mp, PORT_SERIAL_CONTROL1,
> > > > +		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
> > > 
> > > of_machine_is_compatible seems heavy handed, I would expect this to be
> > > based on the compatible string of the ethernet node itself, not the
> > > machine??
> > 
> > Is there a model number variation between IP that needs this and IP that
> > doesn't?  If not, I'm fine with of_machine_is_compatible().
> 
> Well the name 'mv643xx' is a family of system controller SOC's
> from ages ago, it seems reasonble to continue the trend and label the
> IP variations with the SOC name:
> 
>  compatible = "marvell,kirwood,ethernet", "marvell,mv643xx_eth"

Shouldn't it rather be

	compatible = "marvell,kirkwood-eth", "marvell,orion-eth";

I'm inclined to go with of_machine_is_compatible() since the only
concrete difference we know is that the tweak is needed on kirkwood and
nowhere else.

If we had an errata, or a datasheet saying specifically flavor X needs
this and none other does, then we could trigger on the ethernet node
compatible string or a boolean in the node.  But we don't have that...

thx,

Jason.


From jason at lakedaemon.net  Thu May 23 13:24:37 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 13:24:37 -0400
Subject: [PATCH v2 0/3] Marvell PCIe driver improvements
In-Reply-To: <CAErSpo6ytq9Tzq_=KucZA+1=90t57QP5-Fw_dus2dXiXL5YKtg@mail.gmail.com>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <CAErSpo6ytq9Tzq_=KucZA+1=90t57QP5-Fw_dus2dXiXL5YKtg@mail.gmail.com>
Message-ID: <20130523172437.GR31290@titan.lakedaemon.net>

On Thu, May 23, 2013 at 11:01:10AM -0600, Bjorn Helgaas wrote:
> On Thu, May 23, 2013 at 8:32 AM, Thomas Petazzoni
> <thomas.petazzoni at free-electrons.com> wrote:
> > Bjorn, Jason, Andrew, Gregory,
> >
> > Here is an updated version of the PCIe improvements.
> >
> > Changes since v1:
> >
> >  * Fix some typos in the comments of PATCH 2, noticed by Bjorn
> >    Helgaas.
> >
> >  * Rework the two last patches (first one was fixing the capability
> >    list, the other one the emulation of the devsel bits in the status
> >    register), after the comments of Bjorn. In fact, it turns out that
> >    the status register is composed of read-only bits for which we want
> >    to emulate a value of zero, and the other bits are write-1-to-clear
> >    bits that expose error conditions that we do not handle in the
> >    emulated bridge. So, in summary, emulating a 0 status register on
> >    reads, and ignoring writes to the status register is the simplest
> >    solution. If we later on implement a capability list, we can use a
> >    more clever emulation of the status register, but for the moment,
> >    this simple solution is enough. Therefore, the two last patches are
> >    now one single, simpler patch.
> >
> > I'd like those improvements to be kept separated from the original
> > PCIe driver itself: while the PCIe driver has been around and reviewed
> > for a long time, those improvements are newer. And I clearly do not
> > want the PCIe driver to miss 3.11 because of any problem that could be
> > found in those additional improvements.
> >
> > The main improvement being brought here is that the PCI-to-PCI bridge
> > logic is fixed/extended to properly support physical PCIe bridges that
> > are connected on a PCIe interface of a Marvell board. Without this
> > improvement, only the devices connected directly to the PCIe
> > interfaces of the board are properly enumerated. Any device that would
> > sit beyond a physical bridge is not visible.
> >
> > Bjorn, with your Acked-by, could the Marvell maintainers include those
> > patches in their branch, merged through arm-soc? They already have the
> > Marvell PCIe driver itself, so I believe it makes sense to merge those
> > improvements through the same path.
> >
> > Jason, those patches have been prepared on top of my marvell-pcie-v10
> > branch, I hope that's ok for you. If you want me to rebase them on
> > some other branch in which you have integrated the PCIe driver, don't
> > hesitate to tell me to do so. That said, since those patches are only
> > touching the driver itself and no other file, they should not cause
> > any conflict with other changes.
> >
> > Thanks,
> >
> > Thomas
> >
> > Thomas Petazzoni (3):
> >   pci: mvebu: no longer fake the slot location of downstream devices
> >   pci: mvebu: allow the enumeration of devices beyond physical bridges
> >   pci: mvebu: fix the emulation of the status register
> >
> >  drivers/pci/host/pci-mvebu.c |   55 +++++++++++++++++++++++++++++++++---------
> >  1 file changed, 44 insertions(+), 11 deletions(-)
> 
> For all three:
> 
> Acked-by: Bjorn Helgaas <bhelgaas at google.com>
> 
> Feel free to merge these through the arm-soc tree or whatever makes
> sense for you.  Nobody else is working on this file, so there
> shouldn't be any conflicts.

Thanks, Bjorn!

Jason.


From jgunthorpe at obsidianresearch.com  Thu May 23 13:27:54 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 23 May 2013 11:27:54 -0600
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523115321.660fa521@skate>
References: <201305221633.46705.arnd@arndb.de> <20130522170643.54a2b9d2@skate>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <20130522163557.GC27348@1wt.eu> <20130522184250.1d5f2f10@skate>
 <20130522164936.GE31290@titan.lakedaemon.net>
 <20130522185757.60091a66@skate>
 <20130522181953.GD12320@obsidianresearch.com>
 <20130523115321.660fa521@skate>
Message-ID: <20130523172754.GA2821@obsidianresearch.com>

On Thu, May 23, 2013 at 11:53:21AM +0200, Thomas Petazzoni wrote:

> This is not a problem, because the MBus Bridge Window {Base,Control}
> Register tell the CPU that memory accesses between addresses X and Y
> are for MBus windows, and the other accesses are for the DRAM.

Okay, I see, you are minimizing the size of the memory hole, sounds
good.

> > You can combine this idea with the CP15 signalling mechanism. Check
> > CP15 and use it to alter the DTB, similar to how ATAGs are used to
> > fixup the DTB. Don't relocate the registers.
> 
> Where would the code doing this would sit? Remember, this is a
> temporary solution that we want to get rid of after some time. So I've
> been very careful in this proposal to only touch mvebu-specific code.

Well, there are three elements here:
 1) Remove ARMADA_370_XP_REGS_PHYS_BASE and related (looks nearly done now)
 2) Adjust the FDT/DT before it is used based on CP15
 3) Support early printk

#1 looks like it is done when the mbus driver is merged, ie
   we will soon have full dynamic support for the internal regs base
#2 can be done in the machine's init_early, nothing will touch
   internal regs prior to init_early
#3 is for expert use, so the rules can be a bit different:
   - Patch the XP/370 specific early printk code to look in CP15
     to compute the base address
   - .. or rely on a CONFIG_XXX to set the serial base address
   - .. or parse the FDT to find the serial port, requiring
     that the developer has made the FDT match the bootloader.

So, I'm not sure what common code would need to be touched, do you see
something else?

Jason


From mturquette at linaro.org  Thu May 23 13:30:05 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 23 May 2013 10:30:05 -0700
Subject: [PATCH 1/2] ARM: imx6q: call of_clk_init() to register fixed rate
 clocks
In-Reply-To: <1369102324-3084-1-git-send-email-shawn.guo@linaro.org>
References: <1369102324-3084-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130523173005.6058.9635@quantum>

Quoting Shawn Guo (2013-05-20 19:12:03)
> As the fixed rate clocks are defined in device tree, we can just call
> of_clk_init() to register them.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Acked-by: Mike Turquette <mturquette at linaro.org>

Regards,
Mike

> ---
>  arch/arm/mach-imx/clk-imx6q.c |   19 +++++--------------
>  1 file changed, 5 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index a805911..1b883c7 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -276,21 +276,12 @@ int __init mx6q_clocks_init(void)
>         void __iomem *base;
>         int i, irq;
>  
> -       clk[dummy] = imx_clk_fixed("dummy", 0);
> +       of_clk_init(NULL);
>  
> -       /* retrieve the freqency of fixed clocks from device tree */
> -       for_each_compatible_node(np, NULL, "fixed-clock") {
> -               u32 rate;
> -               if (of_property_read_u32(np, "clock-frequency", &rate))
> -                       continue;
> -
> -               if (of_device_is_compatible(np, "fsl,imx-ckil"))
> -                       clk[ckil] = imx_clk_fixed("ckil", rate);
> -               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
> -                       clk[ckih] = imx_clk_fixed("ckih", rate);
> -               else if (of_device_is_compatible(np, "fsl,imx-osc"))
> -                       clk[osc] = imx_clk_fixed("osc", rate);
> -       }
> +       clk[dummy] = imx_clk_fixed("dummy", 0);
> +       clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
> +       clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
> +       clk[osc] = imx_obtain_fixed_clock("osc", 0);
>  
>         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
>         base = of_iomap(np, 0);
> -- 
> 1.7.9.5
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From linus.walleij at stericsson.com  Thu May 23 13:31:28 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:28 +0200
Subject: [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree
In-Reply-To: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369330288-14856-7-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the last of the U300 clocks to being probed from
the device tree.

Cc: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Hi Mike, I'm seeking an ACK on this to take it through the
ARM SoC tree.
---
 .../bindings/clock/ste-u300-syscon-clock.txt       | 23 ++++++++++++++++++++++
 arch/arm/boot/dts/ste-u300.dts                     |  9 +++++++--
 drivers/clk/clk-u300.c                             | 22 ++++++++++++++++-----
 3 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
index b6a30f5..7cafcb9 100644
--- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -55,3 +55,26 @@ gpio: gpio at c0016000 {
 	(...)
 	clocks = <&gpio_clk>;
 };
+
+
+Bindings for the MMC/SD card clock:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-mclk"
+- #clock-cells: must be <0>
+
+Optional properties:
+- clocks: parent clock(s)
+
+mmc_mclk: mmc_mclk {
+	#clock-cells = <0>;
+	compatible = "stericsson,u300-syscon-mclk";
+	clocks = <&mmc_pclk>;
+};
+
+mmcsd: mmcsd at c0001000 {
+	compatible = "arm,pl18x", "arm,primecell";
+	clocks = <&mmc_pclk>, <&mmc_mclk>;
+	clock-names = "apb_pclk", "mclk";
+	(...)
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index e83aafc..d5dd243 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -205,6 +205,11 @@
 			clock-id = <5>;
 			clocks = <&fast_clk>;
 		};
+		mmc_mclk: mmc_mclk {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-mclk";
+			clocks = <&mmc_pclk>;
+		};
 		spi_clk: spi_p_clk at 26M {
 			#clock-cells = <0>;
 			compatible = "stericsson,u300-syscon-clk";
@@ -433,8 +438,8 @@
 			reg = <0xc0001000 0x1000>;
 			interrupt-parent = <&vicb>;
 			interrupts = <6 7>;
-			clocks = <&mmc_pclk>;
-			clock-names = "apb_pclk";
+			clocks = <&mmc_pclk>, <&mmc_mclk>;
+			clock-names = "apb_pclk", "mclk";
 			max-frequency = <24000000>;
 			bus-width = <4>; // SD-card slot
 			mmc-cap-mmc-highspeed;
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 5f234d3..8774e05 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
 	return clk;
 }
 
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+	struct clk *clk = ERR_PTR(-EINVAL);
+	const char *clk_name = np->name;
+	const char *parent_name;
+
+	parent_name = of_clk_get_parent_name(np, 0);
+	clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
 static const __initconst struct of_device_id u300_clk_match[] = {
 	{
 		.compatible = "fixed-clock",
@@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
 		.compatible = "stericsson,u300-syscon-clk",
 		.data = of_u300_syscon_clk_init,
 	},
+	{
+		.compatible = "stericsson,u300-syscon-mclk",
+		.data = of_u300_syscon_mclk_init,
+	},
 };
 
+
 void __init u300_clk_init(void __iomem *base)
 {
 	u16 val;
-	struct clk *clk;
 
 	syscon_vbase = base;
 
@@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
 	writew(val, syscon_vbase + U300_SYSCON_PMCR);
 
 	of_clk_init(u300_clk_match);
-
-	/* Then this special MMC/SD clock */
-	clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
-	clk_register_clkdev(clk, NULL, "mmci");
 }
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May 23 13:31:24 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:24 +0200
Subject: [PATCH 2/6] ARM: u300: remove register definition file
In-Reply-To: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369330288-14856-3-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Now that the core file is the only one actually using any
of the base addresses, we can delete that header and move
the base address definitions into the one and only core
file.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c      | 113 +++++++++++++++++++++++++++-
 arch/arm/mach-u300/u300-regs.h | 165 -----------------------------------------
 2 files changed, 112 insertions(+), 166 deletions(-)
 delete mode 100644 arch/arm/mach-u300/u300-regs.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index bde6540..4db0b76 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -26,7 +26,118 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
-#include "u300-regs.h"
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE		0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE		0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE			(1 << 16)
+#define PLAT_NAND_ALE			(1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE		0xa0000000
+#define U300_AHB_PER_VIRT_BASE		0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE		0xc0000000
+#define U300_FAST_PER_VIRT_BASE		0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE		0xc0010000
+#define U300_SLOW_PER_VIRT_BASE		0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE		0xffff0000
+#define U300_BOOTROM_VIRT_BASE		0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE		0x2FFE0000
+
+/*
+ * AHB peripherals
+ */
+
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)
+
+/*
+ * FAST peripherals
+ */
+
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE			(U300_FAST_PER_PHYS_BASE+0x7000)
+
+/*
+ * SLOW peripherals
+ */
+
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE		(U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)
+
+/*
+ * REST peripherals
+ */
+
+/* ISP (image signal processor) */
+#define U300_ISP_BASE			(0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE			(0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE			(0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE			(0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE		(0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE			(0xd0000000)
 
 /*
  * SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
deleted file mode 100644
index 0320495..0000000
--- a/arch/arm/mach-u300/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE		0x80000000
-
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE		0x9f800000
-
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE			(1 << 16)
-#define PLAT_NAND_ALE			(1 << 17)
-
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE		0xa0000000
-#define U300_AHB_PER_VIRT_BASE		0xff010000
-
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE		0xc0000000
-#define U300_FAST_PER_VIRT_BASE		0xff020000
-
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE		0xc0010000
-#define U300_SLOW_PER_VIRT_BASE		0xff000000
-
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE		0xffff0000
-#define U300_BOOTROM_VIRT_BASE		0xffff0000
-
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE		0x2FFE0000
-
-/*
- * AHB peripherals
- */
-
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)
-
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)
-
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)
-
-
-/*
- * FAST peripherals
- */
-
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)
-
-/* MMC/SD controller */
-#define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)
-
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)
-
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)
-
-/* I2C0 controller */
-#define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)
-
-/* I2C1 controller */
-#define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)
-
-/* SPI controller */
-#define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)
-
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE			(U300_FAST_PER_PHYS_BASE+0x7000)
-
-/*
- * SLOW peripherals
- */
-
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE		(U300_SLOW_PER_PHYS_BASE)
-
-/* SYSCON */
-#define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-
-/* Watchdog */
-#define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)
-
-/* UART0 */
-#define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)
-
-/* APP side special timer */
-#define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-
-/* Keypad */
-#define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)
-
-/* GPIO */
-#define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)
-
-/* RTC */
-#define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
-
-/* Bus tracer */
-#define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)
-
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)
-
-/* Genric Timer */
-#define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)
-
-/* PPM */
-#define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)
-
-
-/*
- * REST peripherals
- */
-
-/* ISP (image signal processor) */
-#define U300_ISP_BASE			(0xA0008000)
-
-/* DMA Controller base */
-#define U300_DMAC_BASE			(0xC0020000)
-
-/* MSL Base */
-#define U300_MSL_BASE			(0xc0022000)
-
-/* APEX Base */
-#define U300_APEX_BASE			(0xc0030000)
-
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE		(0xc0080000)
-
-/* XGAM Base */
-#define U300_XGAM_BASE			(0xd0000000)
-
-#endif
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May 23 13:31:27 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:27 +0200
Subject: [PATCH 5/6] ARM: u300: move the gated system controller clocks to DT
In-Reply-To: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369330288-14856-6-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This moves the slow, fast, AHB bridge and "rest" clocks on
the U300 system controller over to registration from the
device tree.

Cc: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Hi Mike, I'm seeking an ACK to take this patch through the
ARM SoC tree.
---
 .../bindings/clock/ste-u300-syscon-clock.txt       |  57 ++++
 arch/arm/boot/dts/ste-u300.dts                     | 149 ++++++++++
 arch/arm/mach-u300/timer.c                         |   2 +-
 drivers/clk/clk-u300.c                             | 320 ++++++++++++++-------
 4 files changed, 418 insertions(+), 110 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 0000000..b6a30f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,57 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+
+Bindings for the gated system controller clocks:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+  0 = slow clock
+  1 = fast clock
+  2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+
+Optional properties:
+- clocks: parent clock(s)
+
+The available clocks per type are as follows:
+
+Type:  ID:   Clock:
+-------------------
+0      0     Slow peripheral bridge clock
+0      1     UART0 clock
+0      4     GPIO clock
+0      6     RTC clock
+0      7     Application timer clock
+0      8     Access timer clock
+
+1      0     Fast peripheral bridge clock
+1      1     I2C bus 0 clock
+1      2     I2C bus 1 clock
+1      5     MMC interface peripheral (silicon) clock
+1      6     SPI clock
+
+2      3     CPU clock
+2      4     DMA controller clock
+2      5     External Memory Interface (EMIF) clock
+2      6     NAND flask interface clock
+2      8     XGAM graphics engine clock
+2      9     Shared External Memory Interface (SEMI) clock
+2      10    AHB Subsystem Bridge clock
+2      12    Interrupt controller clock
+
+Example:
+
+gpio_clk: gpio_clk at 13M {
+	#clock-cells = <0>;
+	compatible = "stericsson,u300-syscon-clk";
+	clock-type = <0>; /* Slow */
+	clock-id = <4>;
+	clocks = <&slow_clk>;
+};
+
+gpio: gpio at c0016000 {
+	compatible = "stericsson,gpio-coh901";
+	(...)
+	clocks = <&gpio_clk>;
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index c51a8c7..e83aafc 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
 			compatible = "fixed-clock";
 			clock-frequency = <13000000>;
 		};
+		/* Slow bridge clocks under PLL13 */
+		slow_clk: slow_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <0>;
+			clocks = <&pll13>;
+		};
+		uart0_clk: uart0_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <1>;
+			clocks = <&slow_clk>;
+		};
+		gpio_clk: gpio_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <4>;
+			clocks = <&slow_clk>;
+		};
+		rtc_clk: rtc_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <6>;
+			clocks = <&slow_clk>;
+		};
+		apptimer_clk: app_tmr_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <7>;
+			clocks = <&slow_clk>;
+		};
+		acc_tmr_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <8>;
+			clocks = <&slow_clk>;
+		};
 		pll208: pll208 at 208M {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -55,6 +98,13 @@
 			clock-mult = <1>;
 			clocks = <&pll208>;
 		};
+		cpu_clk at 208M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <3>;
+			clocks = <&app208>;
+		};
 		app104: app_104_clk at 104M {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
 			clock-mult = <1>;
 			clocks = <&pll208>;
 		};
+		semi_clk at 104M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <9>;
+			clocks = <&app104>;
+		};
 		app52: app_52_clk at 52M {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
 			clock-mult = <1>;
 			clocks = <&pll208>;
 		};
+		/* AHB subsystem clocks */
+		ahb_clk: ahb_subsys_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <10>;
+			clocks = <&app52>;
+		};
+		intcon_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <12>;
+			clocks = <&ahb_clk>;
+		};
+		emif_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <5>;
+			clocks = <&ahb_clk>;
+		};
+		dmac_clk: dmac_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <4>;
+			clocks = <&app52>;
+		};
+		fsmc_clk: fsmc_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <6>;
+			clocks = <&app52>;
+		};
+		xgam_clk: xgam_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <8>;
+			clocks = <&app52>;
+		};
 		app26: app_26_clk at 26M {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
 			clock-mult = <1>;
 			clocks = <&app52>;
 		};
+		/* Fast bridge  clocks */
+		fast_clk: fast_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <0>;
+			clocks = <&app26>;
+		};
+		i2c0_clk: i2c0_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <1>;
+			clocks = <&fast_clk>;
+		};
+		i2c1_clk: i2c1_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <2>;
+			clocks = <&fast_clk>;
+		};
+		mmc_pclk: mmc_p_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <5>;
+			clocks = <&fast_clk>;
+		};
+		spi_clk: spi_p_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <6>;
+			clocks = <&fast_clk>;
+		};
 	};
 
 	timer: timer at c0014000 {
@@ -83,6 +219,7 @@
 		reg = <0xc0014000 0x1000>;
 		interrupt-parent = <&vica>;
 		interrupts = <24 25 26 27>;
+		clocks = <&apptimer_clk>;
 	};
 
 	gpio: gpio at c0016000 {
@@ -90,6 +227,7 @@
 		reg = <0xc0016000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <0 1 2 18 21 22 23>;
+		clocks = <&gpio_clk>;
 		interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
 				"gpio4", "gpio5", "gpio6";
 		interrupt-controller;
@@ -116,6 +254,7 @@
 		reg = <0xc0017000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <10>;
+		clocks = <&rtc_clk>;
 	};
 
 	dmac: dma-controller at c00020000 {
@@ -125,6 +264,7 @@
 		interrupts = <2>;
 		#dma-cells = <1>;
 		dma-channels = <40>;
+		clocks = <&dmac_clk>;
 	};
 
 	/* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
 			<0x80010000 0x4000>;	/* NAND Base CMD */
 		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
 		nand-skip-bbtscan;
+		clocks = <&fsmc_clk>;
 
 		partition at 0 {
 		label = "boot records";
@@ -158,6 +299,7 @@
 		reg = <0xc0004000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <8>;
+		clocks = <&i2c0_clk>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		ab3100: ab3100 at 0x48 {
@@ -235,6 +377,7 @@
 		reg = <0xc0005000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <9>;
+		clocks = <&i2c1_clk>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		fwcam0: fwcam at 0x10 {
@@ -270,6 +413,8 @@
 			reg = <0xc0013000 0x1000>;
 			interrupt-parent = <&vica>;
 			interrupts = <22>;
+			clocks = <&uart0_clk>, <&uart0_clk>;
+			clock-names = "apb_pclk", "uart0_clk";
 			dmas = <&dmac 17 &dmac 18>;
 			dma-names = "tx", "rx";
 		};
@@ -288,6 +433,8 @@
 			reg = <0xc0001000 0x1000>;
 			interrupt-parent = <&vicb>;
 			interrupts = <6 7>;
+			clocks = <&mmc_pclk>;
+			clock-names = "apb_pclk";
 			max-frequency = <24000000>;
 			bus-width = <4>; // SD-card slot
 			mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
 			reg = <0xc0006000 0x1000>;
 			interrupt-parent = <&vica>;
 			interrupts = <23>;
+			clocks = <&spi_clk>, <&spi_clk>;
+			clock-names = "apb_pclk", "spi_clk";
 			dmas = <&dmac 27 &dmac 28>;
 			dma-names = "tx", "rx";
 			#address-cells = <1>;
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e1c81d..390ae5f 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
 	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
 
 	/* Clock the interrupt controller */
-	clk = clk_get_sys("apptimer", NULL);
+	clk = of_clk_get(np, 0);
 	BUG_ON(IS_ERR(clk));
 	clk_prepare_enable(clk);
 	rate = clk_get_rate(clk);
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index bebd6c9..5f234d3 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
 	return clk;
 }
 
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+	u8 type;
+	u8 id;
+	bool hw_ctrld;
+	u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 3,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 4,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 5,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 6,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 8,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 9,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 10,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 12,
+		.hw_ctrld = false,
+		/* INTCON: cannot be enabled, just taken out of reset */
+		.clk_val = 0xFFFFU,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 0,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 1,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 2,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 5,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 6,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 0,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 1,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 4,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 6,
+		.hw_ctrld = true,
+		/* No clock enable register bit */
+		.clk_val = 0xFFFFU,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 7,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 8,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+	},
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+	struct clk *clk = ERR_PTR(-EINVAL);
+	const char *clk_name = np->name;
+	const char *parent_name;
+	void __iomem *res_reg;
+	void __iomem *en_reg;
+	u32 clk_type;
+	u32 clk_id;
+	int i;
+
+	if (of_property_read_u32(np, "clock-type", &clk_type)) {
+		pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+		       __func__, clk_name);
+		return;
+	}
+	if (of_property_read_u32(np, "clock-id", &clk_id)) {
+		pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+		       __func__, clk_name);
+		return;
+	}
+	parent_name = of_clk_get_parent_name(np, 0);
+
+	switch (clk_type) {
+	case U300_CLK_TYPE_SLOW:
+		res_reg = syscon_vbase + U300_SYSCON_RSR;
+		en_reg = syscon_vbase + U300_SYSCON_CESR;
+		break;
+	case U300_CLK_TYPE_FAST:
+		res_reg = syscon_vbase + U300_SYSCON_RFR;
+		en_reg = syscon_vbase + U300_SYSCON_CEFR;
+		break;
+	case U300_CLK_TYPE_REST:
+		res_reg = syscon_vbase + U300_SYSCON_RRR;
+		en_reg = syscon_vbase + U300_SYSCON_CERR;
+		break;
+	default:
+		pr_err("unknown clock type %x specified\n", clk_type);
+		return;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+		const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+		if (u3clk->type == clk_type && u3clk->id == clk_id)
+			clk = syscon_clk_register(NULL,
+						  clk_name, parent_name,
+						  0, u3clk->hw_ctrld,
+						  res_reg, u3clk->id,
+						  en_reg, u3clk->id,
+						  u3clk->clk_val);
+	}
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+		/*
+		 * Some few system clocks - device tree does not
+		 * represent clocks without a corresponding device node.
+		 * for now we add these three clocks here.
+		 */
+		if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+			clk_register_clkdev(clk, NULL, "pl172");
+		if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+			clk_register_clkdev(clk, NULL, "semi");
+		if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+			clk_register_clkdev(clk, NULL, "intcon");
+	}
+}
+
 /**
  * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
  * @hw: corresponding clock hardware entry
@@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
 		.compatible = "fixed-factor-clock",
 		.data = of_fixed_factor_clk_setup,
 	},
+	{
+		.compatible = "stericsson,u300-syscon-clk",
+		.data = of_u300_syscon_clk_init,
+	},
 };
 
 void __init u300_clk_init(void __iomem *base)
@@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
 
 	of_clk_init(u300_clk_match);
 
-	/* Directly on the AMBA interconnect */
-	clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 3,
-				  syscon_vbase + U300_SYSCON_CERR, 3,
-				  U300_SYSCON_SBCER_CPU_CLK_EN);
-	clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 4,
-				  syscon_vbase + U300_SYSCON_CERR, 4,
-				  U300_SYSCON_SBCER_DMAC_CLK_EN);
-	clk_register_clkdev(clk, NULL, "dma");
-	clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 6,
-				  syscon_vbase + U300_SYSCON_CERR, 6,
-				  U300_SYSCON_SBCER_NANDIF_CLK_EN);
-	clk_register_clkdev(clk, NULL, "fsmc-nand");
-	clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 8,
-				  syscon_vbase + U300_SYSCON_CERR, 8,
-				  U300_SYSCON_SBCER_XGAM_CLK_EN);
-	clk_register_clkdev(clk, NULL, "xgam");
-	clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 9,
-				  syscon_vbase + U300_SYSCON_CERR, 9,
-				  U300_SYSCON_SBCER_SEMI_CLK_EN);
-	clk_register_clkdev(clk, NULL, "semi");
-
-	/* AHB bridge clocks */
-	clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 10,
-				  syscon_vbase + U300_SYSCON_CERR, 10,
-				  U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
-	clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 12,
-				  syscon_vbase + U300_SYSCON_CERR, 12,
-				  /* Cannot be enabled, just taken out of reset */
-				  0xFFFFU);
-	clk_register_clkdev(clk, NULL, "intcon");
-	clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 5,
-				  syscon_vbase + U300_SYSCON_CERR, 5,
-				  U300_SYSCON_SBCER_EMIF_CLK_EN);
-	clk_register_clkdev(clk, NULL, "pl172");
-
-	/* FAST bridge clocks */
-	clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RFR, 0,
-				  syscon_vbase + U300_SYSCON_CEFR, 0,
-				  U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
-	clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 1,
-				  syscon_vbase + U300_SYSCON_CEFR, 1,
-				  U300_SYSCON_SBCER_I2C0_CLK_EN);
-	clk_register_clkdev(clk, NULL, "stu300.0");
-	clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 2,
-				  syscon_vbase + U300_SYSCON_CEFR, 2,
-				  U300_SYSCON_SBCER_I2C1_CLK_EN);
-	clk_register_clkdev(clk, NULL, "stu300.1");
-	clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 5,
-				  syscon_vbase + U300_SYSCON_CEFR, 5,
-				  U300_SYSCON_SBCER_MMC_CLK_EN);
-	clk_register_clkdev(clk, "apb_pclk", "mmci");
-	clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 6,
-				  syscon_vbase + U300_SYSCON_CEFR, 6,
-				  U300_SYSCON_SBCER_SPI_CLK_EN);
-	/* The SPI has no external clock for the outward bus, uses the pclk */
-	clk_register_clkdev(clk, NULL, "pl022");
-	clk_register_clkdev(clk, "apb_pclk", "pl022");
-
-	/* SLOW bridge clocks */
-	clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
-				  syscon_vbase + U300_SYSCON_RSR, 0,
-				  syscon_vbase + U300_SYSCON_CESR, 0,
-				  U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
-	clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 1,
-				  syscon_vbase + U300_SYSCON_CESR, 1,
-				  U300_SYSCON_SBCER_UART_CLK_EN);
-	/* Same clock is used for APB and outward bus */
-	clk_register_clkdev(clk, NULL, "uart0");
-	clk_register_clkdev(clk, "apb_pclk", "uart0");
-	clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 4,
-				  syscon_vbase + U300_SYSCON_CESR, 4,
-				  U300_SYSCON_SBCER_GPIO_CLK_EN);
-	clk_register_clkdev(clk, NULL, "u300-gpio");
-	clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 5,
-				  syscon_vbase + U300_SYSCON_CESR, 6,
-				  U300_SYSCON_SBCER_KEYPAD_CLK_EN);
-	clk_register_clkdev(clk, NULL, "coh901461-keypad");
-	clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RSR, 6,
-				  /* No clock enable register bit */
-				  NULL, 0, 0xFFFFU);
-	clk_register_clkdev(clk, NULL, "rtc-coh901331");
-	clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 7,
-				  syscon_vbase + U300_SYSCON_CESR, 7,
-				  U300_SYSCON_SBCER_APP_TMR_CLK_EN);
-	clk_register_clkdev(clk, NULL, "apptimer");
-	clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 8,
-				  syscon_vbase + U300_SYSCON_CESR, 8,
-				  U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
-	clk_register_clkdev(clk, NULL, "timer");
-
 	/* Then this special MMC/SD clock */
 	clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
 	clk_register_clkdev(clk, NULL, "mmci");
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May 23 13:31:26 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:26 +0200
Subject: [PATCH 4/6] i2c: stu300: do not request a specific clock name
In-Reply-To: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369330288-14856-5-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

We have used the default clock associated with the block
for a long time, only heuristics in the clock system has
made this work anyway. This needs to be done away with as
we start probing this driver and its clocks exclusively
from the device tree.

Cc: Wolfram Sang <wsa at the-dreams.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Hi Wolfram: seeking an ACK for this to take it through the
ARM SoC tree with the rest of my device tree clock patches
for U300.
---
 drivers/i2c/busses/i2c-stu300.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 1beaa05a..d1a6b20 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -868,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
 	struct resource *res;
 	int bus_nr;
 	int ret = 0;
-	char clk_name[] = "I2C0";
 
 	dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
 	if (!dev) {
@@ -877,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
 	}
 
 	bus_nr = pdev->id;
-	clk_name[3] += (char)bus_nr;
-	dev->clk = devm_clk_get(&pdev->dev, clk_name);
+	dev->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(dev->clk)) {
 		dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
 		return PTR_ERR(dev->clk);
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May 23 13:31:22 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:22 +0200
Subject: [PATCH 0/6] U300 device tree clocks
Message-ID: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The following patch set converts all the U300 clocks to be probed
from the device tree. We first move the syscon memory range to the
device tree, then we group the clocks under it.

This goes on top of the previous device tree and multiplatform
series for the U300.

Linus Walleij (6):
  ARM: u300: add syscon node
  ARM: u300: remove register definition file
  clk: move the U300 fixed and fixed-factor to DT
  i2c: stu300: do not request a specific clock name
  ARM: u300: move the gated system controller clocks to DT
  ARM: u300: convert MMC/SD clock to device tree

 Documentation/devicetree/bindings/arm/ste-u300.txt |  30 +-
 .../bindings/clock/ste-u300-syscon-clock.txt       |  80 +++++
 arch/arm/boot/dts/ste-u300.dts                     | 204 +++++++++++
 arch/arm/mach-u300/core.c                          | 135 +++++++-
 arch/arm/mach-u300/regulator.c                     |  21 +-
 arch/arm/mach-u300/timer.c                         |   2 +-
 arch/arm/mach-u300/u300-regs.h                     | 165 ---------
 drivers/clk/clk-u300.c                             | 375 +++++++++++++--------
 drivers/i2c/busses/i2c-stu300.c                    |   4 +-
 9 files changed, 702 insertions(+), 314 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
 delete mode 100644 arch/arm/mach-u300/u300-regs.h

-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May 23 13:31:23 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:23 +0200
Subject: [PATCH 1/6] ARM: u300: add syscon node
In-Reply-To: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369330288-14856-2-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds a device tree node for the U300 system controller
and remaps this dynamically instead of using hard-coded
virtual addresses. The board power set-up code is altered
to fetch a reference to the syscon using ampersand <&syscon>
notation. This way of passing a pointer to the syscon will
also be used by the clocks.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +++++++++++++++++++---
 arch/arm/boot/dts/ste-u300.dts                     |  6 +++++
 arch/arm/mach-u300/core.c                          | 22 +++++++++++++---
 arch/arm/mach-u300/regulator.c                     | 21 ++++++++++++---
 4 files changed, 69 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
index cd9001a..69b5ab0 100644
--- a/Documentation/devicetree/bindings/arm/ste-u300.txt
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -8,15 +8,39 @@ Required root node property:
 
 compatible="stericsson,u300";
 
+Required node: syscon
+This contains the system controller.
+- compatible: must be "stericsson,u300-syscon".
+- reg: the base address and size of the system controller.
+
 Boards with the U300 SoC include:
 
 S365 "Small Board U365":
 
 Required node: s365
+This contains the board-specific information.
+- compatible: must be "stericsson,s365".
+- vana15-supply: the regulator supplying the 1.5V to drive the
+  board.
+- syscon: a pointer to the syscon node so we can acccess the
+  syscon registers to set the board as self-powered.
 
 Example:
 
-s365 {
-	compatible = "stericsson,s365";
-	vana15-supply = <&ab3100_ldo_d_reg>;
+/ {
+	model = "ST-Ericsson U300";
+	compatible = "stericsson,u300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	s365 {
+		compatible = "stericsson,s365";
+		vana15-supply = <&ab3100_ldo_d_reg>;
+		syscon = <&syscon>;
+	};
+
+	syscon: syscon at c0011000 {
+		compatible = "stericsson,u300-syscon";
+		reg = <0xc0011000 0x1000>;
+	};
 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 35a2d58..0530095 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -27,6 +27,12 @@
 	s365 {
 		compatible = "stericsson,s365";
 		vana15-supply = <&ab3100_ldo_d_reg>;
+		syscon = <&syscon>;
+	};
+
+	syscon: syscon at c0011000 {
+		compatible = "stericsson,u300-syscon";
+		reg = <0xc0011000 0x1000>;
 	};
 
 	timer: timer at c0014000 {
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 9caf5ea..bde6540 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -18,6 +18,7 @@
 #include <linux/platform_data/pinctrl-coh901.h>
 #include <linux/platform_data/dma-coh901318.h>
 #include <linux/irqchip.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/clocksource.h>
 #include <linux/clk.h>
@@ -52,6 +53,8 @@
 #define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
 #define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
 
+static void __iomem *syscon_base;
+
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
  * only things we need are the areas where we find the timer, syscon and
@@ -205,7 +208,7 @@ static void __init u300_init_check_chip(void)
 	const char unknown[] = "UNKNOWN";
 
 	/* Read out and print chip ID */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+	val = readw(syscon_base + U300_SYSCON_CIDR);
 	/* This is in funky bigendian order... */
 	val = (val & 0xFFU) << 8 | (val >> 8);
 	chip = db_chips;
@@ -294,10 +297,21 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 
 static void __init u300_init_irq_dt(void)
 {
+	struct device_node *syscon;
 	struct clk *clk;
 
+	syscon = of_find_node_by_path("/syscon at c0011000");
+	if (!syscon) {
+		pr_crit("could not find syscon node\n");
+		return;
+	}
+	syscon_base = of_iomap(syscon, 0);
+	if (!syscon_base) {
+		pr_crit("could not remap syscon\n");
+		return;
+	}
 	/* initialize clocking early, we want to clock the INTCON */
-	u300_clk_init(U300_SYSCON_VBASE);
+	u300_clk_init(syscon_base);
 
 	/* Bootstrap EMIF and SEMI clocks */
 	clk = clk_get_sys("pl172", NULL);
@@ -330,9 +344,9 @@ static void __init u300_init_machine_dt(void)
 			u300_auxdata_lookup, NULL);
 
 	/* Enable SEMI self refresh */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+	val = readw(syscon_base + U300_SYSCON_SMCR) |
 		U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+	writew(val, syscon_base + U300_SYSCON_SMCR);
 }
 
 static const char * u300_board_compat[] = {
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 1cbe88c..273fceb 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -16,8 +16,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
+#include <linux/of_address.h>
 #include <linux/io.h>
-#include "u300-regs.h"
 
 /* Power Management Control 16bit (R/W) */
 #define U300_SYSCON_PMCR					(0x50)
@@ -57,10 +57,25 @@ void u300_pm_poweroff(void)
  */
 static int __init __u300_init_boardpower(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *syscon_np;
+	static void __iomem *syscon_base;
 	int err;
 	u32 val;
 
 	pr_info("U300: setting up board power\n");
+
+	syscon_np = of_parse_phandle(np, "syscon", 0);
+	if (!syscon_np) {
+		pr_crit("U300: no syscon node\n");
+		return -ENODEV;
+	}
+	syscon_base = of_iomap(syscon_np, 0);
+	if (!syscon_base) {
+		pr_crit("U300: could not remap syscon\n");
+		return -ENODEV;
+	}
+
 	main_power_15 = regulator_get(&pdev->dev, "vana15");
 
 	if (IS_ERR(main_power_15)) {
@@ -81,9 +96,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
 	 * the rest of the U300 power management is implemented.
 	 */
 	pr_info("U300: disable system controller pull-up\n");
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+	val = readw(syscon_base + U300_SYSCON_PMCR);
 	val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+	writew(val, syscon_base + U300_SYSCON_PMCR);
 
 	/* Register globally exported PM poweroff hook */
 	pm_power_off = u300_pm_poweroff;
-- 
1.7.11.3



From linus.walleij at stericsson.com  Thu May 23 13:31:25 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:31:25 +0200
Subject: [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT
In-Reply-To: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369330288-14856-4-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the fixed and fixed-factor clocks in the U300
platform to register themselves from the device tree.

Cc: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Hi Mike, seeking an ACK on this to take the series through
ARM SoC.
---
 arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/clk-u300.c         | 33 +++++++++++++------------------
 2 files changed, 57 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 0530095..c51a8c7 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -33,6 +33,49 @@
 	syscon: syscon at c0011000 {
 		compatible = "stericsson,u300-syscon";
 		reg = <0xc0011000 0x1000>;
+		clk32: app_32_clk at 32k {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+		pll13: pll13 at 13M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <13000000>;
+		};
+		pll208: pll208 at 208M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <208000000>;
+		};
+		app208: app_208_clk at 208M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&pll208>;
+		};
+		app104: app_104_clk at 104M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll208>;
+		};
+		app52: app_52_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <4>;
+			clock-mult = <1>;
+			clocks = <&pll208>;
+		};
+		app26: app_26_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&app52>;
+		};
 	};
 
 	timer: timer at c0014000 {
@@ -65,6 +108,7 @@
 		reg = <0xc0012000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <3>;
+		clocks = <&clk32>;
 	};
 
 	rtc: rtc at c0017000 {
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a41e42e..bebd6c9 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
+#include <linux/of.h>
 
 /* APP side SYSCON registers */
 /* CLK Control Register 16bit (R/W) */
@@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
 	return clk;
 }
 
+static const __initconst struct of_device_id u300_clk_match[] = {
+	{
+		.compatible = "fixed-clock",
+		.data = of_fixed_clk_setup,
+	},
+	{
+		.compatible = "fixed-factor-clock",
+		.data = of_fixed_factor_clk_setup,
+	},
+};
+
 void __init u300_clk_init(void __iomem *base)
 {
 	u16 val;
@@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
 	val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
 	writew(val, syscon_vbase + U300_SYSCON_PMCR);
 
-	/* These are always available (RTC and PLL13) */
-	clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
-				      CLK_IS_ROOT, 32768);
-	/* The watchdog sits directly on the 32 kHz clock */
-	clk_register_clkdev(clk, NULL, "coh901327_wdog");
-	clk = clk_register_fixed_rate(NULL, "pll13", NULL,
-				      CLK_IS_ROOT, 13000000);
-
-	/* These derive from PLL208 */
-	clk = clk_register_fixed_rate(NULL, "pll208", NULL,
-				      CLK_IS_ROOT, 208000000);
-	clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
-					0, 1, 1);
-	clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
-					0, 1, 2);
-	clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
-					0, 1, 4);
-	/* The 52 MHz is divided down to 26 MHz */
-	clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
-					0, 1, 2);
+	of_clk_init(u300_clk_match);
 
 	/* Directly on the AMBA interconnect */
 	clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
-- 
1.7.11.3



From s.hauer at pengutronix.de  Thu May 23 13:33:06 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 23 May 2013 19:33:06 +0200
Subject: [PATCH] ARM: dts: imx: fix clocks for cspi
In-Reply-To: <1369319290.379285076@f398.i.mail.ru>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
 <1369311059.366490908@f190.mail.ru>
 <20130523123642.GK32299@pengutronix.de>
 <1369319290.379285076@f398.i.mail.ru>
Message-ID: <20130523173306.GT32299@pengutronix.de>

On Thu, May 23, 2013 at 06:28:10PM +0400, Alexander Shiyan wrote:
> > On Thu, May 23, 2013 at 04:10:59PM +0400, Alexander Shiyan wrote:
> > > > > The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> > > > > 
> > > > > Signed-off-by: Jonas Andersson <jonas at microbit.se>
> > > > > ---
> > > > >  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
> > > > >  arch/arm/boot/dts/imx27.dtsi |  6 +++---
> > > > >  arch/arm/boot/dts/imx51.dtsi |  2 +-
> > > > >  arch/arm/boot/dts/imx53.dtsi |  2 +-
> > > > >  4 files changed, 11 insertions(+), 11 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> > > > > index d2550e0..7011539 100644
> > > > > --- a/arch/arm/boot/dts/imx25.dtsi
> > > > > +++ b/arch/arm/boot/dts/imx25.dtsi
> > > > > @@ -141,8 +141,8 @@
> > > > >  				#size-cells = <0>;
> > > > >  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
> > > > >  				reg = <0x43fa4000 0x4000>;
> > > > > -				clocks = <&clks 62>;
> > > > > -				clock-names = "ipg";
> > > > > +				clocks = <&clks 62>, <&clks 62>;
> > > > > +				clock-names = "ipg", "per";
> > > > >  				interrupts = <14>;
> > > > >  				status = "disabled";
> > > > >  			};
> > > 
> > > Sorry, typo.
> > > 
> > > > Why you do not use "dummy" clock for "per" here?
> > > 
> > > *for "ipg"
> > 
> > Because the same clock is used for the register clock and the baudrate
> > clock. You have to enable the ipg clock to access registers.
> 
> I am not see any "ipg" clock usage in the spi driver.

It's the register clock. The driver enables it in order to access the
registers.

> If "ipg" clock is
> a dependency for "per" clock, it should be registered in ccm as parent.

Look, the eCSPI unit has two clock inputs, one for accessing the
registers (ipg) and one for generating the SPI bit clock (per). Now the
CSPI unit only has a single clock input, so the 100% correct way would
be to specify only a single clock for this unit. However, since we
handle both units with the same driver the simplest way to cope with
it is to provide the very same clock twice, once for the register access
and once for generating the SPI bit clock.
And yes, we have to specify the real clock twice and can't replace one
with a dummy clock, because if we specify a dummy clock for the ipg
clock, then the driver couldn't access the registers even if it enabled
the clock. If we would replace the SPI bit clock with a dummy clock then
the device couldn't send data even if the driver enabled the bit clock.
(That of course only becomes relevant when the driver actually
en/disables the clocks during runtime and not only once during probe).

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From stern at rowland.harvard.edu  Thu May 23 13:37:38 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 23 May 2013 13:37:38 -0400 (EDT)
Subject: [RFC V6 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <201305231901.21632.arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305231335531.925-100000@iolanthe.rowland.org>

On Thu, 23 May 2013, Arnd Bergmann wrote:

> On Thursday 23 May 2013, Alan Stern wrote:
> > On Thu, 23 May 2013, Manjunath Goudar wrote:
> 
> > Also, you left out one thing that should still be here.  What happened 
> > to the part about changing
> > 
> > #if	!defined(PCI_DRIVER) &&		\
> > 
> > to
> > 
> > #if	!ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\
> > 
> 
> This section of the driver is gone now since 86510bb248 "USB: OHCI: 
> clarify Kconfig dependencies", so the change is no longer needed.

I don't know what tree you're referring to.  That commit is not present
in Greg's usb-linus or usb-next branches.  The usb-next branch is what 
I use for new development.

Alan Stern



From arnd at arndb.de  Thu May 23 13:39:42 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 19:39:42 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523164736.610fc55d@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305231612.42395.arnd@arndb.de> <20130523164736.610fc55d@skate>
Message-ID: <201305231939.42359.arnd@arndb.de>

On Thursday 23 May 2013, Thomas Petazzoni wrote:
> 
> On Thu, 23 May 2013 16:12:42 +0200, Arnd Bergmann wrote:
>
> > Well, the main reason I see now is that Marvell screwed it up by
> > having two incompatible versions of u-boot. Using a different base
> > address on new machines would have been no problem at all, but
> > supporting the same machine with different addresses depending on the
> > boot loader version is madness. As you say, it's too late to change
> > that now, so maybe the best solution is to make the registers always
> > get reassigned. 5 trick.
> 
> Not sure what you mean by '5 trick', and what I should understand from
> this :(

I have no idea myself how that got there, don't remember typing it.

Very odd.

> > > What do you mean by "we know what boot loader we have when we pass
> > > the devicetree" ?
> > > 
> > > The mere user of the kernel just does:
> > > 
> > > 	make ARCH=arm mvebu_defconfig
> > > 	make ARCH=arm CROSS_COMPILE=...
> > > 	cat arch/arm/boot/zImage
> > > arch/arm/boot/dts/armada-370-mirabox.dtb > zImage.mirabox ...
> > > prepare uImage ...
> > > 
> > > and he certainly doesn't want to understand the gory details of
> > > which internal register base address to chose depending on which
> > > bootloader version he is using. This is really asking normal users
> > > to have a too much intimate knowledge of the hardware details.
> > 
> > Right, appended device tree is a problem, but if a user does that, I
> > think we can rightfully expect them to know what they are doing.
> 
> Unfortunately, not really. Appended Device Tree is the only way to go
> for old bootloaders, and we don't want users of such bootloaders to
> have to modify their Device Tree to change the base address of the
> internal registers.

But then the old boot loaders surely wouldn't use the new address either.

> > I think we should consequently make sure we never get a production
> > u-boot for Mirabox or OpenBlocks that changes the internal register
> > address and also allows ATAGS based booting.
> 
> It is impossible to prevent that. U-Boot always supports ATAGs booting
> for ARM, and optionally Device Tree based booting.
> 
> And once again, you believe we have an enormous control over what is
> happening at the bootloader level. So when you say "we should
> consequently make sure ..", this is simply not possible: we have no
> control over this.

The control you have over it is to ensure that it's impossible to
boot an upstream kernel using a broken boot loader. This seems to have
worked rather well to get all Kirkwood/Orion5x/mv78xx0/Dove boards
to use an address that is different from the power-on default.

If we see Mirabox or OpenBlocks machines (or any new ones) get out
in the wild with different addresses and no DT support, that would
be rather unfortunate, but it's not the end of the world, we could
call add a trivial .dts file that includes the original one and puts
in the correct address into the ranges property.

> > Since you explained that we want to move the internal registers to get
> > more available memory, I think what you also want to do is to
> > dynamically reassign the internal register mapping when the mbus
> > driver gets loaded, just like all the other mbus mappings.
> 
> Ideally, it should be like this. Unfortunately, moving the internal
> register mapping is really a painful operation: you have to know where
> is the address to change the internal register base address (which
> itself changes when the internal register base address changes), and all
> code interacting with peripherals before the change of the address must
> be synchronized so that after the switch it uses the new address.

But you are proposing a patch set that does exactly this, so it's
clearly possible, right?

> Switching the internal registers address at runtime after a lot of
> things have booted is *painful* and we really don't want to do that.
> Sebastian Hesselbarth, who has worked on the topic, will confirm this.

It can still be done really early, e.g. from map_io(), since that is
run at a time when we have access to the DT and are not using any
devices other than the debug_ll code that is already a hack.

> We've gone through great lengths to find a solution that does not
> touch *any* ARM generic code (even though it would have been much
> simpler!). At least one Marvell maintainer (Andrew Lunn) is fine with
> this temporary solution, and since the issue is very SoC-specific, and
> completely self-contained in the SoC-specific code, would it be
> possible to be pragmatic and let us merge such a workaround?

Maybe you can put the hack into a separate board file that gets used
only for the two boards that need it and is enabled optionally?
The part that is really worrying about your patch is that you essentially
make an undocumented extension to the boot protocol to silently ignore
the information from the official interface and use a hardcoded value
instead, for all boards in that platform.

If you make a hack there, at least make it blatently obvious that
something is wrong when you work around it:

* allow the hack only for known broken machines (e.g. OpenBlocks
  with the internal registers at 0xf1), on all other machines
  trust the DT information.

* When you detect a mismatch between DT and the hardware setup
  as passed by the boot loader, print a fat warning.

* Fix it up by modifying the DT in memory to match the actual
  hardware configuration, not by making the hardware match the DT.

* If you ever want to get rid of the hack, put a time-bomb it in
  right away, like "BUG_ON(LINUX_VERSION_CODE > KERNEL_VERSION(3,14,0))"

	Arnd


From arnd at arndb.de  Thu May 23 13:42:18 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 19:42:18 +0200
Subject: [RFC V6 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <Pine.LNX.4.44L0.1305231335531.925-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305231335531.925-100000@iolanthe.rowland.org>
Message-ID: <201305231942.19172.arnd@arndb.de>

On Thursday 23 May 2013, Alan Stern wrote:
> > > 
> > 
> > This section of the driver is gone now since 86510bb248 "USB: OHCI: 
> > clarify Kconfig dependencies", so the change is no longer needed.
> 
> I don't know what tree you're referring to.  That commit is not present
> in Greg's usb-linus or usb-next branches.  The usb-next branch is what 
> I use for new development.

Sorry, my mistake. I had looked at a temporary tree based on linux-next,
and I thought that Greg had applied my patch and put it into usb-next,
but instead it's a patch I had sitting on the branch I used for build
testing. I have not yet submitted that one again, and I'm sure that
Manjunath doesn't have it on his machine, so your comment still applies.

	Arnd


From jason at lakedaemon.net  Thu May 23 13:42:34 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 13:42:34 -0400
Subject: [PATCH] ARM: mvebu: Fix bug in coherency fabric low level init
 function
In-Reply-To: <1369299242-16506-2-git-send-email-gregory.clement@free-electrons.com>
References: <1369299242-16506-1-git-send-email-gregory.clement@free-electrons.com>
 <1369299242-16506-2-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130523174234.GS31290@titan.lakedaemon.net>

On Thu, May 23, 2013 at 10:54:02AM +0200, Gregory CLEMENT wrote:
> From: Nadav Haklai <nadavh at marvell.com>
> 
> When adding CPU to the SMP group and enabling the coherency on this
> CPU we must protect the register access.
> The previous implementation claims to be atomic but doesn't provide
> any protection against parallel access to the coherency fabric control
> and configuration registers.
> 
> This patch fixes this by using the ldrex and strex mechanism.
> This method should be used in all accesses to those registers.
> 
> [gregory.clement at free-electrons.com: fixed the commit's topic]
> Signed-off-by: Nadav Haklai <nadavh at marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/mach-mvebu/coherency_ll.S | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)

Applied to mvebu/fixes

thx,

Jason.


From alexandre.belloni at free-electrons.com  Thu May 23 13:51:46 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Thu, 23 May 2013 19:51:46 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <1369322904.4142.36.camel@weser.hi.pengutronix.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <201305221305.09579.marex@denx.de> <201305230920.18200.jbe@pengutronix.de>
 <201305231648.17356.marex@denx.de>
 <1369322904.4142.36.camel@weser.hi.pengutronix.de>
Message-ID: <519E5732.1040800@free-electrons.com>

Hi,

On 23/05/2013 17:28, Lucas Stach wrote:
> Am Donnerstag, den 23.05.2013, 16:48 +0200 schrieb Marek Vasut:
>> Dear Juergen Beisert,
>>
>>> Hi Marek,
>>>
>>> Marek Vasut wrote:
>>>>>> i2c slowness is a different issue.
>>>>> Same happens here for my i.M23 based platform. It seems the PIO mode
>>>>> does not work, or at least not like it works on a i.MX28. Each short
>>>>> transfer needs about one second (without an error message) but does
>>>>> not send anything on the I2C lines.
>>>>>
>>>>> I need the following patches to make I2C master work within a 3.10-rc2
>>>>> kernel:
>>>>>
>>>>> Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C
>>>> I'm all for it, but then ... won't it be better if you actually fixed the
>>>> PIO and mixed-mode on MX23 instead of implementing such hack?
>>> If the PIO mode or my patch is a hack depends on the point of view: Lucas
>>> told me the PIO mode is *mentioned* but *not specified* in the
>>> i.MX23/i.MX28 datasheets.
>> The PIO works the same way DMA does -- set up bits and then pump data into the 
>> DATA register. 
>>> So, the PIO mode seems to depend on some undocumented status bits in the
>>> i.MX28 I2C controller implementation.
>> How would DMA work then if it used undocumented registers ? It's in the 
>> documentation, just read it or ask FSL ;-)
>>
> While the PIO mode might use the same controller mechanisms as the DMA
> mode, PIO mode is _not_ a documented mode of operation for the i.MX23.
>
> To quote the i.MX28 RM: "The I2C block on the i.MX28 supports a new PIO
> mode or soft-DMA mode.", which implies the PIO mode to be a new mode of
> operation not found on earlier i.MX SoCs.
> The doc is slightly fuzzy here as the i.MX23 RM in contrary states:
> "Short transmission (up to three bytes plus address) can be easily
> triggered using only PIO operations, i.e., no DMA setup required." But
> again it's not a documented mode of operation, i.MX23 doc only describes
> the DMA mode.
>
> So while we _might_ be able to get the PIO mode to work on the i.MX23
> there is nothing in the doc stating that it's even meant to work. Even
> while PIO and DMA mode use the same internal mechanisms, there's still
> plenty of opportunities of fail in there. After all PIO mode relies on
> reading a debug register in the course of normal operation.
>
> Only more extensive experimentation could show if we are in fact able to
> make it work, a first shot of using PIO mode on MX23 failed, so it might
> as well be that Juergens quick fix is correct and we have to disable PIO
> mode on MX23 altogether. That said please stop slapping the word "hack"
> over this patch until proven otherwise.

Still, Fabio and I have been experiencing the one second delay on
i.mx28. From my experience, it appeared between 3.7 and 3.9, see:
http://www.spinics.net/lists/linux-i2c/msg11985.html. I still didn't
take the time to investigate more yet but it confirms that PIO mode is
working on i.mx28 though with an annoying delay.

Regards,

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From rpimentel.silva at gmail.com  Thu May 23 13:53:57 2013
From: rpimentel.silva at gmail.com (Rogerio Pimentel)
Date: Thu, 23 May 2013 14:53:57 -0300
Subject: [PATCH 0/3] staging: fix parallel display regressions
In-Reply-To: <1368787839.4011.4.camel@pizza.hi.pengutronix.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
 <1368787839.4011.4.camel@pizza.hi.pengutronix.de>
Message-ID: <CAOkaPuVhTPNgWXWw_vPu28ZdPjRVYsrodaumptUQpp5NMz+rOA@mail.gmail.com>

On Fri, May 17, 2013 at 7:50 AM, Philipp Zabel <p.zabel at pengutronix.de> wrote:
> Hi Markus,
>
> Am Freitag, den 17.05.2013, 11:19 +0200 schrieb Markus Niebel:
>> From: Markus Niebel <Markus.Niebel at tqs.de>
>>
>> Support for VGA via TVE on iMX53 causes  regression, which prevents
>> parallel display from working. This series brings the parallel display
>> functionality back.
>>
>> Tested on a modified v3.9 with TQMa53 module and compile tested with
>> v3.10-rc1.
>>
>> Markus Niebel (3):
>>   staging: drm/imx: set correct sync pins for parallel display
>>   staging: drm/imx: fix spelling error for vsync flag config
>>   staging: drm/imx: revert vsync_cnt for di->id 1
>>
>>  drivers/staging/imx-drm/ipu-v3/ipu-di.c    |   13 +++++++++----
>>  drivers/staging/imx-drm/parallel-display.c |    4 ++--
>>  2 files changed, 11 insertions(+), 6 deletions(-)
>
> thank you for posting the patches! I can confirm that they fix the
> issues of incorrect signal generation on IPU display interface 1,
> caused by my TVE patch series.
>
> Tested-by: Philipp Zabel <p.zabel at pengutronix.de>
>
> regards
> Philipp
>

With these patches I was able to enable the parallel display on i.MX53 QSB.
It works.

Tested-by: Rogerio Pimentel <rogerio.pimentel at freescale.com>

Rgds
Rogerio Pimentel


From jgunthorpe at obsidianresearch.com  Thu May 23 13:53:57 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 23 May 2013 11:53:57 -0600
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130523172339.GQ31290@titan.lakedaemon.net>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
Message-ID: <20130523175357.GB2821@obsidianresearch.com>

On Thu, May 23, 2013 at 01:23:39PM -0400, Jason Cooper wrote:

> Shouldn't it rather be
> 
> 	compatible = "marvell,kirkwood-eth", "marvell,orion-eth";

Not sure about orion-eth?
 
> I'm inclined to go with of_machine_is_compatible() since the only
> concrete difference we know is that the tweak is needed on kirkwood and
> nowhere else.

But there is a larger problem here then just this one bit.

The PSC1 register must be set properly for the board layout, and today
we rely on the bootloader to set it. In fact, even with Sebastian's
change the ethernet port won't work without bootloader
intervention. The PortReset bit should also be cleared by the driver
(and it is only present on some variants of this IP block,
apparently).

We know that some Marvell SOC's wack the ethernet registers when they
clock gate, and the flip of Clk125Bypass is another symptom of this
general problem.

So, long term, the PSC1 must be fully set by the driver, based on DT
information describing the board (eg RGMII/MII/1000Base-X [SFP] Phy
type), and the layout of this register seems to vary on a SOC by SOC
basis.

Thus, I think it is appropriate to call this variant of the eth IP
'marvell,kirkwood-eth' which indicates that the register block follows
the kirkwood manual and the PSC1 register specifically has the
kirkwood layout.

The question is what other Marvell SOCs have the same PSC1 layout as
kirkwood?

Jason


From sboyd at codeaurora.org  Thu May 23 13:54:26 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 23 May 2013 10:54:26 -0700
Subject: [PATCH] ARM: avoid mis-detecting some V7 cores in the decompressor
In-Reply-To: <5193E424.9090605@codeaurora.org>
References: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
 <5193E424.9090605@codeaurora.org>
Message-ID: <519E57D2.3050000@codeaurora.org>

On 05/15/13 12:38, Stephen Boyd wrote:
> On 05/08/13 14:47, Stephen Boyd wrote:
>> From: Brian Swetland <swetland at google.com>
>>
>> Currently v7 CPUs with an MIDR that has no bits set in the range
>> [16:12] will be detected as old ARM CPUs with no caches and so
>> the cache will never be turned on during decompression. ARM's
>> Cortex chips have an 0xC in the range [16:12] so they never match
>> this entry, but Qualcomm's Scorpion and Krait processors never
>> set these bits to anything besides 0 so they always match.
>>
>> Skip this entry if we've compiled in support for v7 CPUs. This
>> allows kernel decompression to happen nearly instantly instead of
>> taking over 20 seconds.
>>
>> Signed-off-by: Brian Swetland <swetland at google.com>
>> [sboyd: Clarified and extended commit text]
>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
>> ---
> Ping?

Russell, shall I add this to the patch tracker?

>
>>  arch/arm/boot/compressed/head.S | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
>> index fe4d9c3..a236190 100644
>> --- a/arch/arm/boot/compressed/head.S
>> +++ b/arch/arm/boot/compressed/head.S
>> @@ -805,6 +805,8 @@ call_cache_fn:	adr	r12, proc_types
>>  		.align	2
>>  		.type	proc_types,#object
>>  proc_types:
>> +#if !defined(CONFIG_CPU_V7)
>> +		/* This collides with some V7 IDs, preventing correct detection */
>>  		.word	0x00000000		@ old ARM ID
>>  		.word	0x0000f000
>>  		mov	pc, lr
>> @@ -813,6 +815,7 @@ proc_types:
>>   THUMB(		nop				)
>>  		mov	pc, lr
>>   THUMB(		nop				)
>> +#endif
>>  
>>  		.word	0x41007000		@ ARM7/710
>>  		.word	0xfff8fe00
>


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From linus.walleij at stericsson.com  Thu May 23 13:59:53 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 23 May 2013 19:59:53 +0200
Subject: [PATCH 23/23 v2] ARM: u300: delete all static board data
Message-ID: <1369331993-28916-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

We have now transferred all the U300 peripherals to the device
tree, so we just select USE_OF, and delete all static board data,
then require that this platform shall be booted using the device
tree and nothing else.

This gets rid of the MMCI (PL180), PL022, and serial PL011
platform data entries and more.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Delete MORE static data! (Platform data and static DMA channel
  assignments for PL011, PL022, PL180...
---
 arch/arm/Kconfig               |   1 +
 arch/arm/mach-u300/Makefile    |   2 -
 arch/arm/mach-u300/core.c      | 548 +----------------------------------------
 arch/arm/mach-u300/i2c.c       | 285 ---------------------
 arch/arm/mach-u300/i2c.h       |  23 --
 arch/arm/mach-u300/regulator.c |  12 +-
 arch/arm/mach-u300/spi.c       | 102 --------
 arch/arm/mach-u300/spi.h       |  26 --
 arch/arm/mach-u300/timer.c     |  38 +--
 arch/arm/mach-u300/timer.h     |   2 -
 arch/arm/mach-u300/u300-gpio.h |  70 ------
 11 files changed, 22 insertions(+), 1087 deletions(-)
 delete mode 100644 arch/arm/mach-u300/i2c.c
 delete mode 100644 arch/arm/mach-u300/i2c.h
 delete mode 100644 arch/arm/mach-u300/spi.c
 delete mode 100644 arch/arm/mach-u300/spi.h
 delete mode 100644 arch/arm/mach-u300/timer.h
 delete mode 100644 arch/arm/mach-u300/u300-gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fbad333..2689643 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -827,6 +827,7 @@ config ARCH_U300
 	select GENERIC_CLOCKEVENTS
 	select HAVE_TCM
 	select SPARSE_IRQ
+	select USE_OF
 	help
 	  Support for ST-Ericsson U300 series mobile platforms.
 
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58..0f362b6 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,5 @@ obj-m		:=
 obj-n		:=
 obj-		:=
 
-obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
-obj-$(CONFIG_I2C_STU300)          += i2c.o
 obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 8f9e77a..13d4812 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -9,50 +9,20 @@
  * Author: Linus Walleij <linus.walleij at stericsson.com>
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/termios.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/amba/serial.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
 #include <linux/platform_data/pinctrl-coh901.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/irqchip/arm-vic.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/clocksource.h>
+#include <linux/clk.h>
 
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
+#include <mach/u300-regs.h>
 #include <mach/syscon.h>
-#include <mach/irqs.h>
-
-#include "timer.h"
-#include "spi.h"
-#include "i2c.h"
-#include "u300-gpio.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -87,287 +57,6 @@ static void __init u300_map_io(void)
 }
 
 /*
- * Declaration of devices found on the U300 board and
- * their respective memory locations.
- */
-
-static struct amba_pl011_data uart0_plat_data = {
-#ifdef CONFIG_COH901318
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_UART0_RX,
-	.dma_tx_param = (void *) U300_DMA_UART0_TX,
-#endif
-};
-
-/* Slow device at 0x3000 offset */
-static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
-	{ IRQ_U300_UART0 }, &uart0_plat_data);
-
-/* The U335 have an additional UART1 on the APP CPU */
-static struct amba_pl011_data uart1_plat_data = {
-#ifdef CONFIG_COH901318
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_UART1_RX,
-	.dma_tx_param = (void *) U300_DMA_UART1_TX,
-#endif
-};
-
-/* Fast device at 0x7000 offset */
-static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
-	{ IRQ_U300_UART1 }, &uart1_plat_data);
-
-/* AHB device at 0x4000 offset */
-static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
-
-/* Fast device at 0x6000 offset */
-static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
-	{ IRQ_U300_SPI }, NULL);
-
-/* Fast device at 0x1000 offset */
-#define U300_MMCSD_IRQS	{ IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
-
-static struct mmci_platform_data mmcsd_platform_data = {
-	/*
-	 * Do not set ocr_mask or voltage translation function,
-	 * we have a regulator we can control instead.
-	 */
-	.f_max = 24000000,
-	.gpio_wp = -1,
-	.gpio_cd = U300_GPIO_PIN_MMC_CD,
-	.cd_invert = true,
-	.capabilities = MMC_CAP_MMC_HIGHSPEED |
-	MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-	/* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-
-static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
-	U300_MMCSD_IRQS, &mmcsd_platform_data);
-
-/*
- * The order of device declaration may be important, since some devices
- * have dependencies on other devices being initialized first.
- */
-static struct amba_device *amba_devs[] __initdata = {
-	&uart0_device,
-	&uart1_device,
-	&pl022_device,
-	&pl172_device,
-	&mmcsd_device,
-};
-
-/* Here follows a list of all hw resources that the platform devices
- * allocate. Note, clock dependencies are not included
- */
-
-static struct resource gpio_resources[] = {
-	{
-		.start = U300_GPIO_BASE,
-		.end   = (U300_GPIO_BASE + SZ_4K - 1),
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "gpio0",
-		.start = IRQ_U300_GPIO_PORT0,
-		.end   = IRQ_U300_GPIO_PORT0,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio1",
-		.start = IRQ_U300_GPIO_PORT1,
-		.end   = IRQ_U300_GPIO_PORT1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio2",
-		.start = IRQ_U300_GPIO_PORT2,
-		.end   = IRQ_U300_GPIO_PORT2,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio3",
-		.start = IRQ_U300_GPIO_PORT3,
-		.end   = IRQ_U300_GPIO_PORT3,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio4",
-		.start = IRQ_U300_GPIO_PORT4,
-		.end   = IRQ_U300_GPIO_PORT4,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio5",
-		.start = IRQ_U300_GPIO_PORT5,
-		.end   = IRQ_U300_GPIO_PORT5,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio6",
-		.start = IRQ_U300_GPIO_PORT6,
-		.end   = IRQ_U300_GPIO_PORT6,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource keypad_resources[] = {
-	{
-		.start = U300_KEYPAD_BASE,
-		.end   = U300_KEYPAD_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "coh901461-press",
-		.start = IRQ_U300_KEYPAD_KEYBF,
-		.end   = IRQ_U300_KEYPAD_KEYBF,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "coh901461-release",
-		.start = IRQ_U300_KEYPAD_KEYBR,
-		.end   = IRQ_U300_KEYPAD_KEYBR,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource rtc_resources[] = {
-	{
-		.start = U300_RTC_BASE,
-		.end   = U300_RTC_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_RTC,
-		.end   = IRQ_U300_RTC,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-/*
- * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
- * but these are not yet used by the driver.
- */
-static struct resource fsmc_resources[] = {
-	{
-		.name  = "nand_addr",
-		.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
-		.end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "nand_cmd",
-		.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
-		.end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "nand_data",
-		.start = U300_NAND_CS0_PHYS_BASE,
-		.end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "fsmc_regs",
-		.start = U300_NAND_IF_PHYS_BASE,
-		.end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct resource i2c0_resources[] = {
-	{
-		.start = U300_I2C0_BASE,
-		.end   = U300_I2C0_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_I2C0,
-		.end   = IRQ_U300_I2C0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c1_resources[] = {
-	{
-		.start = U300_I2C1_BASE,
-		.end   = U300_I2C1_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_I2C1,
-		.end   = IRQ_U300_I2C1,
-		.flags = IORESOURCE_IRQ,
-	},
-
-};
-
-static struct resource wdog_resources[] = {
-	{
-		.start = U300_WDOG_BASE,
-		.end   = U300_WDOG_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_WDOG,
-		.end   = IRQ_U300_WDOG,
-		.flags = IORESOURCE_IRQ,
-	}
-};
-
-static struct resource dma_resource[] = {
-	{
-		.start = U300_DMAC_BASE,
-		.end = U300_DMAC_BASE + PAGE_SIZE - 1,
-		.flags =  IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_DMA,
-		.end = IRQ_U300_DMA,
-		.flags =  IORESOURCE_IRQ,
-	}
-};
-
-
-static struct resource pinctrl_resources[] = {
-	{
-		.start = U300_SYSCON_BASE,
-		.end   = U300_SYSCON_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device wdog_device = {
-	.name = "coh901327_wdog",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(wdog_resources),
-	.resource = wdog_resources,
-};
-
-static struct platform_device i2c0_device = {
-	.name = "stu300",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(i2c0_resources),
-	.resource = i2c0_resources,
-};
-
-static struct platform_device i2c1_device = {
-	.name = "stu300",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(i2c1_resources),
-	.resource = i2c1_resources,
-};
-
-static struct platform_device pinctrl_device = {
-	.name = "pinctrl-u300",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(pinctrl_resources),
-	.resource = pinctrl_resources,
-};
-
-/*
  * The different variants have a few different versions of the
  * GPIO block, with different number of ports.
  */
@@ -376,75 +65,6 @@ static struct u300_gpio_platform u300_gpio_plat = {
 	.gpio_base = 0,
 };
 
-static struct platform_device gpio_device = {
-	.name = "u300-gpio",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(gpio_resources),
-	.resource = gpio_resources,
-	.dev = {
-		.platform_data = &u300_gpio_plat,
-	},
-};
-
-static struct platform_device keypad_device = {
-	.name = "keypad",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(keypad_resources),
-	.resource = keypad_resources,
-};
-
-static struct platform_device rtc_device = {
-	.name = "rtc-coh901331",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(rtc_resources),
-	.resource = rtc_resources,
-};
-
-static struct mtd_partition u300_partitions[] = {
-	{
-		.name = "bootrecords",
-		.offset = 0,
-		.size = SZ_128K,
-	},
-	{
-		.name = "free",
-		.offset = SZ_128K,
-		.size = 8064 * SZ_1K,
-	},
-	{
-		.name = "platform",
-		.offset = 8192 * SZ_1K,
-		.size = 253952 * SZ_1K,
-	},
-};
-
-static struct fsmc_nand_platform_data nand_platform_data = {
-	.partitions = u300_partitions,
-	.nr_partitions = ARRAY_SIZE(u300_partitions),
-	.options = NAND_SKIP_BBTSCAN,
-	.width = FSMC_NAND_BW8,
-};
-
-static struct platform_device nand_device = {
-	.name = "fsmc-nand",
-	.id = -1,
-	.resource = fsmc_resources,
-	.num_resources = ARRAY_SIZE(fsmc_resources),
-	.dev = {
-		.platform_data = &nand_platform_data,
-	},
-};
-
-static struct platform_device dma_device = {
-	.name		= "coh901318",
-	.id		= -1,
-	.resource	= dma_resource,
-	.num_resources  = ARRAY_SIZE(dma_resource),
-	.dev = {
-		.coherent_dma_mask = ~0,
-	},
-};
-
 static unsigned long pin_pullup_conf[] = {
 	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 };
@@ -471,61 +91,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
 				    pin_highz_conf),
 };
 
-/*
- * Notice that AMBA devices are initialized before platform devices.
- *
- */
-static struct platform_device *platform_devs[] __initdata = {
-	&dma_device,
-	&i2c0_device,
-	&i2c1_device,
-	&keypad_device,
-	&rtc_device,
-	&pinctrl_device,
-	&gpio_device,
-	&nand_device,
-	&wdog_device,
-};
-
-/*
- * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
- * together so some interrupts are connected to the first one and some
- * to the second one.
- */
-static void __init u300_init_irq(void)
-{
-	u32 mask[2] = {0, 0};
-	struct clk *clk;
-	int i;
-
-	/* initialize clocking early, we want to clock the INTCON */
-	u300_clk_init(U300_SYSCON_VBASE);
-
-	/* Bootstrap EMIF and SEMI clocks */
-	clk = clk_get_sys("pl172", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_prepare_enable(clk);
-	clk = clk_get_sys("semi", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_prepare_enable(clk);
-
-	/* Clock the interrupt controller */
-	clk = clk_get_sys("intcon", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_prepare_enable(clk);
-
-	for (i = 0; i < U300_VIC_IRQS_END; i++)
-		set_bit(i, (unsigned long *) &mask[0]);
-	vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-		 mask[0], mask[0]);
-	vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
-		 mask[1], mask[1]);
-}
-
-
-/*
- * U300 platforms peripheral handling
- */
 struct db_chip {
 	u16 chipid;
 	const char *name;
@@ -604,74 +169,6 @@ static void __init u300_init_check_chip(void)
 	}
 }
 
-/*
- * Some devices and their resources require reserved physical memory from
- * the end of the available RAM. This function traverses the list of devices
- * and assigns actual addresses to these.
- */
-static void __init u300_assign_physmem(void)
-{
-	unsigned long curr_start = __pa(high_memory);
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
-		for (j = 0; j < platform_devs[i]->num_resources; j++) {
-			struct resource *const res =
-			  &platform_devs[i]->resource[j];
-
-			if (IORESOURCE_MEM == res->flags &&
-				     0 == res->start) {
-				res->start  = curr_start;
-				res->end   += curr_start;
-				curr_start += resource_size(res);
-
-				printk(KERN_INFO "core.c: Mapping RAM " \
-				       "%#x-%#x to device %s:%s\n",
-					res->start, res->end,
-				       platform_devs[i]->name, res->name);
-			}
-		}
-	}
-}
-
-static void __init u300_init_machine(void)
-{
-	int i;
-	u16 val;
-
-	/* Check what platform we run and print some status information */
-	u300_init_check_chip();
-
-	/* Initialize SPI device with some board specifics */
-	u300_spi_init(&pl022_device);
-
-	/* Register the AMBA devices in the AMBA bus abstraction layer */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-
-	u300_assign_physmem();
-
-	/* Initialize pinmuxing */
-	pinctrl_register_mappings(u300_pinmux_map,
-				  ARRAY_SIZE(u300_pinmux_map));
-
-	/* Register subdevices on the I2C buses */
-	u300_i2c_register_board_devices();
-
-	/* Register the platform devices */
-	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-
-	/* Register subdevices on the SPI bus */
-	u300_spi_register_board_devices();
-
-	/* Enable SEMI self refresh */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
-		U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
-}
-
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
@@ -692,35 +189,6 @@ static void u300_restart(char mode, const char *cmd)
 	while (1);
 }
 
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
-	/* Maintainer: Linus Walleij <linus.walleij at stericsson.com> */
-	.atag_offset	= 0x100,
-	.map_io		= u300_map_io,
-	.nr_irqs	= 0,
-	.init_irq	= u300_init_irq,
-	.init_time	= u300_timer_init,
-	.init_machine	= u300_init_machine,
-	.restart	= u300_restart,
-MACHINE_END
-
-#ifdef CONFIG_OF
-
-static struct pl022_ssp_controller spi_plat_data = {
-	/* If you have several SPI buses this varies, we have only bus 0 */
-	.bus_id = 0,
-	/*
-	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-	 * chip selects for SPI. (Same on U330, U335 and U365.)
-	 * TODO: make sure the GPIO driver can select these properly
-	 * and do padmuxing accordingly too.
-	 */
-	.num_chipselect = 3,
-	.enable_dma = 1,
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_SPI_RX,
-	.dma_tx_param = (void *) U300_DMA_SPI_TX,
-};
-
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
@@ -736,17 +204,17 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
 		"fsmc-nand", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
-		"uart0", &uart0_plat_data),
+		"uart0", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
-		"uart1", &uart1_plat_data),
+		"uart1", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
-		"pl022", &spi_plat_data),
+		"pl022", NULL),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
 		"stu300.0", NULL),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
 		"stu300.1", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
-		"mmci", &mmcsd_platform_data),
+		"mmci", NULL),
 	{ /* sentinel */ },
 };
 
@@ -780,8 +248,6 @@ static void __init u300_init_machine_dt(void)
 	/* Check what platform we run and print some status information */
 	u300_init_check_chip();
 
-	u300_assign_physmem();
-
 	/* Initialize pinmuxing */
 	pinctrl_register_mappings(u300_pinmux_map,
 				  ARRAY_SIZE(u300_pinmux_map));
@@ -808,5 +274,3 @@ DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
 	.restart	= u300_restart,
 	.dt_compat      = u300_board_compat,
 MACHINE_END
-
-#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
deleted file mode 100644
index 96800aa..0000000
--- a/arch/arm/mach-u300/i2c.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.c
- *
- * Copyright (C) 2009-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/mfd/ab3100.h>
-#include <linux/regulator/machine.h>
-#include <linux/amba/bus.h>
-#include <mach/irqs.h>
-
-/*
- * Initial settings of ab3100 registers.
- * Common for below LDO regulator settings are that
- * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
- * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
- */
-
-/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
-#define LDO_A_SETTING		0x16
-/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_C_SETTING		0x10
-/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
-#define LDO_D_SETTING		0x10
-/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_E_SETTING		0x10
-/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
-#define LDO_E_SLEEP_SETTING	0x00
-/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_F_SETTING		0xD0
-/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_G_SETTING		0x00
-/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
-#define LDO_H_SETTING		0x18
-/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_K_SETTING		0x00
-/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
-#define LDO_EXT_SETTING		0x00
-/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
-#define BUCK_SETTING	0x7D
-/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
-#define BUCK_SLEEP_SETTING	0xAC
-
-#ifdef CONFIG_AB3100_CORE
-static struct regulator_consumer_supply supply_ldo_c[] = {
-	{
-		.dev_name = "ab3100-codec",
-		.supply = "vaudio", /* Powers the codec */
-	},
-};
-
-/*
- * This one needs to be a supply so we can turn it off
- * in order to shut down the system.
- */
-static struct regulator_consumer_supply supply_ldo_d[] = {
-	{
-		.supply = "vana15", /* Powers the SoC (CPU etc) */
-	},
-};
-
-static struct regulator_consumer_supply supply_ldo_g[] = {
-	{
-		.dev_name = "mmci",
-		.supply = "vmmc", /* Powers MMC/SD card */
-	},
-};
-
-static struct regulator_consumer_supply supply_ldo_h[] = {
-	{
-		.dev_name = "xgam_pdi",
-		.supply = "vdisp", /* Powers camera, display etc */
-	},
-};
-
-static struct regulator_consumer_supply supply_ldo_k[] = {
-	{
-		.dev_name = "irda",
-		.supply = "vir", /* Power IrDA */
-	},
-};
-
-/*
- * This is a placeholder for whoever wish to use the
- * external power.
- */
-static struct regulator_consumer_supply supply_ldo_ext[] = {
-	{
-		.supply = "vext", /* External power */
-	},
-};
-
-/* Preset (hardware defined) voltages for these regulators */
-#define LDO_A_VOLTAGE 2750000
-#define LDO_C_VOLTAGE 2650000
-#define LDO_D_VOLTAGE 2650000
-
-static struct ab3100_platform_data ab3100_plf_data = {
-	.reg_constraints = {
-		/* LDO A routing and constraints */
-		{
-			.constraints = {
-				.name = "vrad",
-				.min_uV = LDO_A_VOLTAGE,
-				.max_uV = LDO_A_VOLTAGE,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-		/* LDO C routing and constraints */
-		{
-			.constraints = {
-				.min_uV = LDO_C_VOLTAGE,
-				.max_uV = LDO_C_VOLTAGE,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
-			.consumer_supplies = supply_ldo_c,
-		},
-		/* LDO D routing and constraints */
-		{
-			.constraints = {
-				.min_uV = LDO_D_VOLTAGE,
-				.max_uV = LDO_D_VOLTAGE,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-				/*
-				 * Actually this is boot_on but we need
-				 * to reference count it externally to
-				 * be able to shut down the system.
-				 */
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
-			.consumer_supplies = supply_ldo_d,
-		},
-		/* LDO E routing and constraints */
-		{
-			.constraints = {
-				.name = "vio",
-				.min_uV = 1800000,
-				.max_uV = 1800000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-		/* LDO F routing and constraints */
-		{
-			.constraints = {
-				.name = "vana25",
-				.min_uV = 2500000,
-				.max_uV = 2500000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-		/* LDO G routing and constraints */
-		{
-			.constraints = {
-				.min_uV = 1500000,
-				.max_uV = 2850000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
-			.consumer_supplies = supply_ldo_g,
-		},
-		/* LDO H routing and constraints */
-		{
-			.constraints = {
-				.min_uV = 1200000,
-				.max_uV = 2750000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
-			.consumer_supplies = supply_ldo_h,
-		},
-		/* LDO K routing and constraints */
-		{
-			.constraints = {
-				.min_uV = 1800000,
-				.max_uV = 2750000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
-			.consumer_supplies = supply_ldo_k,
-		},
-		/* External regulator interface. No fixed voltage specified.
-		 * If we knew the voltage of the external regulator and it
-		 * was connected on the board, we could add the (fixed)
-		 * voltage for it here.
-		 */
-		{
-			.constraints = {
-				.min_uV = 0,
-				.max_uV = 0,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
-			.consumer_supplies = supply_ldo_ext,
-		},
-		/* Buck converter routing and constraints */
-		{
-			.constraints = {
-				.name = "vcore",
-				.min_uV = 1200000,
-				.max_uV = 1800000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-	},
-	.reg_initvals = {
-		LDO_A_SETTING,
-		LDO_C_SETTING,
-		LDO_E_SETTING,
-		LDO_E_SLEEP_SETTING,
-		LDO_F_SETTING,
-		LDO_G_SETTING,
-		LDO_H_SETTING,
-		LDO_K_SETTING,
-		LDO_EXT_SETTING,
-		BUCK_SETTING,
-		BUCK_SLEEP_SETTING,
-		LDO_D_SETTING,
-	},
-};
-#endif
-
-static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
-#ifdef CONFIG_AB3100_CORE
-	{
-		.type = "ab3100",
-		.addr = 0x48,
-		.irq = IRQ_U300_IRQ0_EXT,
-		.platform_data = &ab3100_plf_data,
-	},
-#else
-	{ },
-#endif
-};
-
-static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-	{
-		.type = "fwcam",
-		.addr = 0x10,
-	},
-	{
-		.type = "fwcam",
-		.addr = 0x5d,
-	},
-};
-
-void __init u300_i2c_register_board_devices(void)
-{
-	i2c_register_board_info(0, bus0_i2c_board_info,
-				ARRAY_SIZE(bus0_i2c_board_info));
-	/*
-	 * This makes the core shut down all unused regulators
-	 * after all the initcalls have completed.
-	 */
-	regulator_has_full_constraints();
-	i2c_register_board_info(1, bus1_i2c_board_info,
-				ARRAY_SIZE(bus1_i2c_board_info));
-}
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
deleted file mode 100644
index 485c02e..0000000
--- a/arch/arm/mach-u300/i2c.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef MACH_U300_I2C_H
-#define MACH_U300_I2C_H
-
-#ifdef CONFIG_I2C_STU300
-void __init u300_i2c_register_board_devices(void);
-#else
-/* Compile out this stuff if no I2C adapter is available */
-static inline void __init u300_i2c_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 8a67dc6..bbda954 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -58,10 +58,7 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
 	u32 val;
 
 	pr_info("U300: setting up board power\n");
-	if (pdev)
-		main_power_15 = regulator_get(&pdev->dev, "vana15");
-	else
-		main_power_15 = regulator_get(NULL, "vana15");
+	main_power_15 = regulator_get(&pdev->dev, "vana15");
 
 	if (IS_ERR(main_power_15)) {
 		pr_err("could not get vana15");
@@ -114,11 +111,8 @@ static struct platform_driver s365_board_driver = {
  */
 static int __init u300_init_boardpower(void)
 {
-	if (of_have_populated_dt())
-		return platform_driver_probe(&s365_board_driver,
-					     s365_board_probe);
-	/* Only call this on non-DT boots */
-	return __u300_init_boardpower(NULL);
+	return platform_driver_probe(&s365_board_driver,
+				     s365_board_probe);
 }
 
 device_initcall(u300_init_boardpower);
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
deleted file mode 100644
index 9106982..0000000
--- a/arch/arm/mach-u300/spi.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.c
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/spi/spi.h>
-#include <linux/amba/pl022.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/err.h>
-
-/*
- * The following is for the actual devices on the SSP/SPI bus
- */
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-static void select_dummy_chip(u32 chipselect)
-{
-	pr_debug("CORE: %s called with CS=0x%x (%s)\n",
-		 __func__,
-		 chipselect,
-		 chipselect ? "unselect chip" : "select chip");
-	/*
-	 * Here you would write the chip select value to the GPIO pins if
-	 * this was a real chip (but this is a loopback dummy).
-	 */
-}
-
-struct pl022_config_chip dummy_chip_info = {
-	/* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
-	.com_mode = DMA_TRANSFER,
-	.iface = SSP_INTERFACE_MOTOROLA_SPI,
-	/* We can only act as master but SSP_SLAVE is possible in theory */
-	.hierarchy = SSP_MASTER,
-	/* 0 = drive TX even as slave, 1 = do not drive TX as slave */
-	.slave_tx_disable = 0,
-	.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
-	.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
-	.ctrl_len = SSP_BITS_12,
-	.wait_state = SSP_MWIRE_WAIT_ZERO,
-	.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-	/*
-	 * This is where you insert a call to a function to enable CS
-	 * (usually GPIO) for a certain chip.
-	 */
-	.cs_control = select_dummy_chip,
-};
-#endif
-
-static struct spi_board_info u300_spi_devices[] = {
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-	{
-		/* A dummy chip used for loopback tests */
-		.modalias       = "spi-dummy",
-		/* Really dummy, pass in additional chip config here */
-		.platform_data  = NULL,
-		/* This defines how the controller shall handle the device */
-		.controller_data = &dummy_chip_info,
-		/* .irq - no external IRQ routed from this device */
-		.max_speed_hz   = 1000000,
-		.bus_num        = 0, /* Only one bus on this chip */
-		.chip_select    = 0,
-		/* Means SPI_CS_HIGH, change if e.g low CS */
-		.mode           = SPI_MODE_1 | SPI_LOOP,
-	},
-#endif
-};
-
-static struct pl022_ssp_controller ssp_platform_data = {
-	/* If you have several SPI buses this varies, we have only bus 0 */
-	.bus_id = 0,
-	/*
-	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-	 * chip selects for SPI. (Same on U330, U335 and U365.)
-	 * TODO: make sure the GPIO driver can select these properly
-	 * and do padmuxing accordingly too.
-	 */
-	.num_chipselect = 3,
-#ifdef CONFIG_COH901318
-	.enable_dma = 1,
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_SPI_RX,
-	.dma_tx_param = (void *) U300_DMA_SPI_TX,
-#else
-	.enable_dma = 0,
-#endif
-};
-
-
-void __init u300_spi_init(struct amba_device *adev)
-{
-	adev->dev.platform_data = &ssp_platform_data;
-}
-
-void __init u300_spi_register_board_devices(void)
-{
-	/* Register any SPI devices */
-	spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
-}
diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h
deleted file mode 100644
index bd3d867..0000000
--- a/arch/arm/mach-u300/spi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#ifndef SPI_H
-#define SPI_H
-#include <linux/amba/bus.h>
-
-#ifdef CONFIG_SPI_PL022
-void __init u300_spi_init(struct amba_device *adev);
-void __init u300_spi_register_board_devices(void);
-#else
-/* Compile out SPI support if PL022 is not selected */
-static inline void __init u300_spi_init(struct amba_device *adev)
-{
-}
-static inline void __init u300_spi_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index df1e3b5..f3efef0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -30,8 +30,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include "timer.h"
-
 /*
  * APP side special timer registers
  * This timer contains four timers which can fire an interrupt each.
@@ -361,12 +359,22 @@ static struct delay_timer u300_delay_timer;
 /*
  * This sets up the system timers, clock source and clock event.
  */
-static void __init u300_timer_setup(void __iomem *base, int irq)
+static void __init u300_timer_init_of(struct device_node *np)
 {
+	struct resource irq_res;
+	int irq;
 	struct clk *clk;
 	unsigned long rate;
 
-	u300_timer_base = base;
+	u300_timer_base = of_iomap(np, 0);
+	if (!u300_timer_base)
+		panic("could not ioremap system timer\n");
+
+	/* Get the IRQ for the GP1 timer */
+	irq = of_irq_to_resource(np, 2, &irq_res);
+	if (irq <= 0)
+		panic("no IRQ for system timer\n");
+
 	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
 
 	/* Clock the interrupt controller */
@@ -433,27 +441,5 @@ static void __init u300_timer_setup(void __iomem *base, int irq)
 	 */
 }
 
-
-void __init u300_timer_init()
-{
-	u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
-}
-
-#ifdef CONFIG_OF
-
-static void __init u300_timer_init_of(struct device_node *np)
-{
-	void __iomem *base;
-	struct resource irq_res;
-	int irq;
-
-	base = of_iomap(np, 0);
-	/* Get the IRQ for the GP1 timer */
-	irq = of_irq_to_resource(np, 2, &irq_res);
-	u300_timer_setup(base, irq);
-}
-
 CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
 		       u300_timer_init_of);
-
-#endif
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index 7766dfa..0000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1,2 +0,0 @@
-extern void u300_timer_init(void);
-
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f5077..0000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Individual pin assignments for the B335/S335.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#define U300_GPIO_PIN_UART_RX		0
-#define U300_GPIO_PIN_UART_TX		1
-#define U300_GPIO_PIN_UART_CTS		2
-#define U300_GPIO_PIN_UART_RTS		3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY	4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05		5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD		6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07		7 /* Test point TP2430 */
-
-#define U300_GPIO_PIN_GPIO08		8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09		9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10		10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET	11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD		12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY	13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14		14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15		15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16		16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE		17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18		18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19		19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20		20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21		21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22		22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23		23 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO24		24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25		25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26		26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27		27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28		28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29		29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30		30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31		31 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO32		32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33		33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34		34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35		35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36		36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37		37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38		38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39		39 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO40		40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41		41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42		42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43		43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44		44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45		45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46		46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47		47 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO48		48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49		49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50		50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51		51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52		52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53		53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54		54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55		55 /* Unrouted */
-- 
1.7.11.3



From festevam at gmail.com  Thu May 23 14:00:35 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 23 May 2013 15:00:35 -0300
Subject: [PATCH 0/3] staging: fix parallel display regressions
In-Reply-To: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
References: <1368782393-9660-1-git-send-email-list-09_linuc_arm@tqsc.de>
Message-ID: <CAOMZO5AP24qMimaiOZoTJo0f2TJo3362kBHAH8jUmXdo0QVmhQ@mail.gmail.com>

Hi Markus,

On Fri, May 17, 2013 at 6:19 AM, Markus Niebel
<list-09_linuc_arm at tqsc.de> wrote:
> From: Markus Niebel <Markus.Niebel at tqs.de>
>
> Support for VGA via TVE on iMX53 causes  regression, which prevents
> parallel display from working. This series brings the parallel display
> functionality back.
>
> Tested on a modified v3.9 with TQMa53 module and compile tested with
> v3.10-rc1.
>
> Markus Niebel (3):
>   staging: drm/imx: set correct sync pins for parallel display
>   staging: drm/imx: fix spelling error for vsync flag config
>   staging: drm/imx: revert vsync_cnt for di->id 1
>
>  drivers/staging/imx-drm/ipu-v3/ipu-di.c    |   13 +++++++++----
>  drivers/staging/imx-drm/parallel-display.c |    4 ++--
>  2 files changed, 11 insertions(+), 6 deletions(-)

Greg Kroah-Hartman <gregkh at linuxfoundation.org> is the one that takes
the patches for staging drivers.

Could you resend your series with him in Cc and add the Tested-by from
Philipp and Rogerio?

Thanks,

Fabio Estevam


From w at 1wt.eu  Thu May 23 14:15:19 2013
From: w at 1wt.eu (Willy Tarreau)
Date: Thu, 23 May 2013 20:15:19 +0200
Subject: [PATCH] ARM: mvebu: Fix bug in coherency fabric low level init
 function
In-Reply-To: <1369299242-16506-2-git-send-email-gregory.clement@free-electrons.com>
References: <1369299242-16506-1-git-send-email-gregory.clement@free-electrons.com>
 <1369299242-16506-2-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130523181519.GF2680@1wt.eu>

Hi Gregory,

On Thu, May 23, 2013 at 10:54:02AM +0200, Gregory CLEMENT wrote:
> From: Nadav Haklai <nadavh at marvell.com>
> 
> When adding CPU to the SMP group and enabling the coherency on this
> CPU we must protect the register access.
> The previous implementation claims to be atomic but doesn't provide
> any protection against parallel access to the coherency fabric control
> and configuration registers.
> 
> This patch fixes this by using the ldrex and strex mechanism.
> This method should be used in all accesses to those registers.

I don't know how to tell whether the fix works since it's unclear
to me what issue it fixes, but at least I can say that it doesn't
break my armada370 on 3.10-rc2 + latest fixes from your dev branch.

Best regards,
Willy



From jason at lakedaemon.net  Thu May 23 14:26:22 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 14:26:22 -0400
Subject: [PATCH v2 0/3] Marvell PCIe driver improvements
In-Reply-To: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130523182622.GT31290@titan.lakedaemon.net>

On Thu, May 23, 2013 at 04:32:50PM +0200, Thomas Petazzoni wrote:
> Bjorn, Jason, Andrew, Gregory,
> 
> Here is an updated version of the PCIe improvements.
> 
> Changes since v1:
> 
>  * Fix some typos in the comments of PATCH 2, noticed by Bjorn
>    Helgaas.
> 
>  * Rework the two last patches (first one was fixing the capability
>    list, the other one the emulation of the devsel bits in the status
>    register), after the comments of Bjorn. In fact, it turns out that
>    the status register is composed of read-only bits for which we want
>    to emulate a value of zero, and the other bits are write-1-to-clear
>    bits that expose error conditions that we do not handle in the
>    emulated bridge. So, in summary, emulating a 0 status register on
>    reads, and ignoring writes to the status register is the simplest
>    solution. If we later on implement a capability list, we can use a
>    more clever emulation of the status register, but for the moment,
>    this simple solution is enough. Therefore, the two last patches are
>    now one single, simpler patch.
> 
> I'd like those improvements to be kept separated from the original
> PCIe driver itself: while the PCIe driver has been around and reviewed
> for a long time, those improvements are newer. And I clearly do not
> want the PCIe driver to miss 3.11 because of any problem that could be
> found in those additional improvements.
> 
> The main improvement being brought here is that the PCI-to-PCI bridge
> logic is fixed/extended to properly support physical PCIe bridges that
> are connected on a PCIe interface of a Marvell board. Without this
> improvement, only the devices connected directly to the PCIe
> interfaces of the board are properly enumerated. Any device that would
> sit beyond a physical bridge is not visible.
> 
> Bjorn, with your Acked-by, could the Marvell maintainers include those
> patches in their branch, merged through arm-soc? They already have the
> Marvell PCIe driver itself, so I believe it makes sense to merge those
> improvements through the same path.
> 
> Jason, those patches have been prepared on top of my marvell-pcie-v10
> branch, I hope that's ok for you. If you want me to rebase them on
> some other branch in which you have integrated the PCIe driver, don't
> hesitate to tell me to do so. That said, since those patches are only
> touching the driver itself and no other file, they should not cause
> any conflict with other changes.
> 
> Thanks,
> 
> Thomas
> 
> Thomas Petazzoni (3):
>   pci: mvebu: no longer fake the slot location of downstream devices
>   pci: mvebu: allow the enumeration of devices beyond physical bridges
>   pci: mvebu: fix the emulation of the status register
> 
>  drivers/pci/host/pci-mvebu.c |   55 +++++++++++++++++++++++++++++++++---------
>  1 file changed, 44 insertions(+), 11 deletions(-)

Whole series applied to mvebu/pcie_bridge with Bjorn's Ack.  The whole
pcie tree now looks like:

        /-mvebu/of_pci  /-mvebu/pcie
        |               |
+---+---+---+---+---+---+---+---+---+---+ mvebu/pcie_bridge
                        |
                        \---+---+---+---+ mvebu/pcie_kirkwood
(not to scale :) )

This is getting pretty hairy, do you intend on anything else for mvebu
pcie for this merge window?

thx,

Jason.


From jason at lakedaemon.net  Thu May 23 14:40:28 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 23 May 2013 14:40:28 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130523175357.GB2821@obsidianresearch.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
Message-ID: <20130523184028.GU31290@titan.lakedaemon.net>

On Thu, May 23, 2013 at 11:53:57AM -0600, Jason Gunthorpe wrote:
> On Thu, May 23, 2013 at 01:23:39PM -0400, Jason Cooper wrote:
> 
> > Shouldn't it rather be
> > 
> > 	compatible = "marvell,kirkwood-eth", "marvell,orion-eth";
> 
> Not sure about orion-eth?
>  
> > I'm inclined to go with of_machine_is_compatible() since the only
> > concrete difference we know is that the tweak is needed on kirkwood and
> > nowhere else.
> 
> But there is a larger problem here then just this one bit.
> 
> The PSC1 register must be set properly for the board layout, and today
> we rely on the bootloader to set it. In fact, even with Sebastian's
> change the ethernet port won't work without bootloader
> intervention. The PortReset bit should also be cleared by the driver
> (and it is only present on some variants of this IP block,
> apparently).
> 
> We know that some Marvell SOC's wack the ethernet registers when they
> clock gate, and the flip of Clk125Bypass is another symptom of this
> general problem.
> 
> So, long term, the PSC1 must be fully set by the driver, based on DT
> information describing the board (eg RGMII/MII/1000Base-X [SFP] Phy
> type), and the layout of this register seems to vary on a SOC by SOC
> basis.
> 
> Thus, I think it is appropriate to call this variant of the eth IP
> 'marvell,kirkwood-eth' which indicates that the register block follows
> the kirkwood manual and the PSC1 register specifically has the
> kirkwood layout.

Ok, so mv643xx_eth would match both "marvell,orion-eth" and
"marvell,kirkwood-eth", then write to PSC1 iff it sees a node matching
"marvell,kirkwood-eth".  I'm not too keen on that, however, the matching
of the machine doesn't look to good, either.

Perhaps a better answer is to add a boolean, "marvell,kirkwood_psc1" and
check for that?

Or, marvell,psc1_reset = <0xWWXXYYZZ>;

> The question is what other Marvell SOCs have the same PSC1 layout as
> kirkwood?

I think marvell,psc1_reset = <>; gives us the most flexibility in
accurately describing the hardware.

thx,

Jason.


From tony at atomide.com  Thu May 23 14:46:37 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 23 May 2013 11:46:37 -0700
Subject: [PATCH v2 5/5] ARM: dts: OMAP2+: use pinctrl constants
In-Reply-To: <1369323421-4180-6-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
 <1369323421-4180-6-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <20130523184636.GE13507@atomide.com>

* Florian Vaussard <florian.vaussard at epfl.ch> [130523 08:42]:
> index f39b237..b3cc896 100644
> --- a/arch/arm/boot/dts/omap2.dtsi
> +++ b/arch/arm/boot/dts/omap2.dtsi
> @@ -9,6 +9,7 @@
>   */
>  
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/omap.h>
>  
>  #include "skeleton.dtsi"
>  
> diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
> index 434288f..2518e6a 100644
> --- a/arch/arm/boot/dts/omap3-beagle.dts
> +++ b/arch/arm/boot/dts/omap3-beagle.dts
> @@ -81,18 +81,18 @@
>  
>  	hsusbb2_pins: pinmux_hsusbb2_pins {
>  		pinctrl-single,pins = <
> -			0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
> -			0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
> -			0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
> -			0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
> -			0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
> -			0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
> -			0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
> -			0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
> -			0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
> -			0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
> -			0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
> -			0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
> +			0x5c0 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk */
> +			0x5c2 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp */
> +			0x5c4 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir */
> +			0x5c6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt */
> +			0x5c8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 */
> +			0x5cA (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 */
> +			0x1a4 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 */
> +			0x1a6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 */
> +			0x1a8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 */
> +			0x1aa (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 */
> +			0x1ac (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 */
> +			0x1ae (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 */
>  		>;
>  	};
>  };

Nice!

While at it, can you lowercase the USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk
naming to usbb2_ulpittl_clk.usbb1_ulpiphy_clk? You can also leave out _MUXMODE
from these for consistency.

I wonder if we can leave out the OMAP_ prefix from the mux mode defines
here and just assume PIN_OUTPUT etc would not conflict with other SoC's
naming?

Regards,

Tony


From tony at atomide.com  Thu May 23 14:47:28 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 23 May 2013 11:47:28 -0700
Subject: [PATCH v2 2/5] ARM: dts: OMAP2+: use existing constants for GPIOs
In-Reply-To: <1369323421-4180-3-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
 <1369323421-4180-3-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <20130523184727.GF13507@atomide.com>

* Florian Vaussard <florian.vaussard at epfl.ch> [130523 08:42]:
> --- a/arch/arm/boot/dts/omap3-beagle-xm.dts
> +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
> @@ -29,13 +29,13 @@
>  
>  		heartbeat {
>  			label = "beagleboard::usr0";
> -			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
> +			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
>  			linux,default-trigger = "heartbeat";
>  		};
>  
>  		mmc {
>  			label = "beagleboard::usr1";
> -			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
> +			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
>  			linux,default-trigger = "mmc0";
>  		};
>  	};

Great yeah this is the way to go instead of the fixed numbering.
Thanks for doing this.

Regards,

Tony


From balbi at ti.com  Thu May 23 14:46:56 2013
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 May 2013 21:46:56 +0300
Subject: [PATCH 2/7] USB: gadget: atmel_usba: allow multi instance
In-Reply-To: <1369067160-3230-2-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
 <1369067160-3230-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20130523184656.GD19834@arwen.pp.htv.fi>

On Mon, May 20, 2013 at 06:25:55PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> drop static struct usba_udc the_udc
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  drivers/usb/gadget/atmel_usba_udc.c |   36 +++++++++++++++++------------------
>  1 file changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
> index d2ffd04..eea57a3 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/atmel_usba_udc.c
> @@ -27,9 +27,6 @@
>  
>  #include "atmel_usba_udc.h"
>  
> -
> -static struct usba_udc the_udc;
> -
>  #ifdef CONFIG_USB_GADGET_DEBUG_FS
>  #include <linux/debugfs.h>
>  #include <linux/uaccess.h>
> @@ -1013,16 +1010,13 @@ static void nop_release(struct device *dev)
>  
>  }
>  
> -static struct usba_udc the_udc = {
> -	.gadget	= {
> -		.ops		= &usba_udc_ops,
> -		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
> -		.max_speed	= USB_SPEED_HIGH,
> -		.name		= "atmel_usba_udc",
> -		.dev	= {
> -			.init_name	= "gadget",
> -			.release	= nop_release,
> -		},
> +struct usb_gadget usba_gadget_template = {
> +	.ops		= &usba_udc_ops,
> +	.max_speed	= USB_SPEED_HIGH,
> +	.name		= "atmel_usba_udc",
> +	.dev	= {
> +		.init_name	= "gadget",
> +		.release	= nop_release,
>  	},
>  };
>  
> @@ -1839,10 +1833,17 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  	struct usba_platform_data *pdata = pdev->dev.platform_data;
>  	struct resource *regs, *fifo;
>  	struct clk *pclk, *hclk;
> -	struct usba_udc *udc = &the_udc;
> +	struct usba_udc *udc;
>  	static struct usba_ep *usba_ep;
>  	int irq, ret, i;
>  
> +	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
> +	if (!udc)
> +		return -ENOMEM;
> +
> +	udc->gadget = usba_gadget_template;
> +	INIT_LIST_HEAD(&udc->gadget.ep_list);
> +
>  	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
>  	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
>  	if (!regs || !fifo || !pdata)
> @@ -1897,8 +1898,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  		goto err_alloc_ep;
>  
>  	udc->usba_ep = usba_ep;
> -
> -	the_udc.gadget.ep0 = &usba_ep[0].ep;
> +	udc->gadget.ep0 = &usba_ep[0].ep;
>  
>  	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
>  	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
> @@ -1907,7 +1907,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  	usba_ep[0].ep.ops = &usba_ep_ops;
>  	usba_ep[0].ep.name = pdata->ep[0].name;
>  	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
> -	usba_ep[0].udc = &the_udc;
> +	usba_ep[0].udc = udc;
>  	INIT_LIST_HEAD(&usba_ep[0].queue);
>  	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
>  	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
> @@ -1924,7 +1924,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  		ep->ep.ops = &usba_ep_ops;
>  		ep->ep.name = pdata->ep[i].name;
>  		ep->ep.maxpacket = pdata->ep[i].fifo_size;
> -		ep->udc = &the_udc;
> +		ep->udc = udc;
>  		INIT_LIST_HEAD(&ep->queue);
>  		ep->fifo_size = pdata->ep[i].fifo_size;
>  		ep->nr_banks = pdata->ep[i].nr_banks;
> -- 
> 1.7.10.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
balbi
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From balbi at ti.com  Thu May 23 14:47:15 2013
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 May 2013 21:47:15 +0300
Subject: [PATCH 1/7] USB: gadget: atmel_usba: move global struct usba_ep
 usba_ep to struct usba_udc
In-Reply-To: <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20130523184715.GE19834@arwen.pp.htv.fi>

On Mon, May 20, 2013 at 06:25:54PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> so we can have multiple usb gadget instance
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org

Acked-by: Felipe Balbi <balbi at ti.com>

-- 
balbi
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From balbi at ti.com  Thu May 23 14:47:47 2013
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 May 2013 21:47:47 +0300
Subject: [PATCH 3/7] USB: gadget: atmel_usba: add DT support
In-Reply-To: <1369067160-3230-3-git-send-email-plagnioj@jcrosoft.com>
References: <20130520162149.GC9937@game.jcrosoft.org>
 <1369067160-3230-1-git-send-email-plagnioj@jcrosoft.com>
 <1369067160-3230-3-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20130523184747.GF19834@arwen.pp.htv.fi>

On Mon, May 20, 2013 at 06:25:56PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Allow to compile the driver all the time if AT91 enabled.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org

Acked-by: Felipe Balbi <balbi at ti.com>

-- 
balbi
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From thomas.petazzoni at free-electrons.com  Thu May 23 14:53:48 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 20:53:48 +0200
Subject: [PATCH v2 0/3] Marvell PCIe driver improvements
In-Reply-To: <20130523182622.GT31290@titan.lakedaemon.net>
References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523182622.GT31290@titan.lakedaemon.net>
Message-ID: <20130523205348.54751fca@skate>

Dear Jason Cooper,

On Thu, 23 May 2013 14:26:22 -0400, Jason Cooper wrote:

> >  drivers/pci/host/pci-mvebu.c |   55 +++++++++++++++++++++++++++++++++---------
> >  1 file changed, 44 insertions(+), 11 deletions(-)
> 
> Whole series applied to mvebu/pcie_bridge with Bjorn's Ack.  The whole
> pcie tree now looks like:
> 
>         /-mvebu/of_pci  /-mvebu/pcie
>         |               |
> +---+---+---+---+---+---+---+---+---+---+ mvebu/pcie_bridge
>                         |
>                         \---+---+---+---+ mvebu/pcie_kirkwood
> (not to scale :) )

Nice diagram, I like it :-)

> This is getting pretty hairy, do you intend on anything else for mvebu
> pcie for this merge window?

No, nothing significant. There might be some minor additional fixes
that you can just stack into the mvebu/pcie_bridge branch, but I don't
have any such fixes sitting anywhere in my repo at this point.

I now intend to work on the MSI support, but since it requires a quite
significant work to properly expose the msi_chip from the IRQ
controller driver, I don't really think it will be ready in time for
3.11.

Thanks a lot for the quick merges. I'm really eager to see this PCIe
code that has been around for a long time finally merged.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From thomas.petazzoni at free-electrons.com  Thu May 23 14:57:26 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu, 23 May 2013 20:57:26 +0200
Subject: [PATCH 0/4] Marvell PCIe driver improvements
In-Reply-To: <20130523164654.GA31281@obsidianresearch.com>
References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523001353.GH31625@1wt.eu>
 <20130523164654.GA31281@obsidianresearch.com>
Message-ID: <20130523205726.05ba45bf@skate>

Dear Jason Gunthorpe,

On Thu, 23 May 2013 10:46:54 -0600, Jason Gunthorpe wrote:

> > FWIW, these patches applied on top of your pcie-v10 tree have made
> > my mini-pcie dual-nic appear for the first time on the mirabox. Till
> > now I never knew if it was a hardware or software issue since the NIC
> > does not appear in u-boot nor lspci, whatever the kernel versions,
> > including the original Marvell one's. The NIC has two functions (one
> > per controller) and no bridge, so it may be a side effect of your
> > improvements (or maybe you fixed a bug).
> 
> There was some talk earlier that some buggy chips required their
> device number to be 0. I'm guessing Thomas's change to ensure that
> always happens by moving the device number of the internal device is
> the root fix here?

You're correct. Off-list, I've sent to Willy a patch that applies on
top of those additional "bridge-related" fixes, but that reverts back
the slot number of the real PCIe device to be 1 instead of 0. And in
this case, the PCIe device that Willy is using is not detected.

So indeed, there are some PCIe devices who really want to receive
"configuration transactions" as slot 0.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linus.walleij at linaro.org  Thu May 23 15:00:51 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 May 2013 21:00:51 +0200
Subject: [PATCH v2] mmc: mmci: Allow MMCI to request channels with
 information acquired from DT
In-Reply-To: <20130424155547.GA4623@gmail.com>
References: <1366801122-13302-1-git-send-email-lee.jones@linaro.org>
 <20130424155547.GA4623@gmail.com>
Message-ID: <CACRpkdbr4Lm4NGHzX4TTq4fYwFahwC82fQSBg_V=SGVKkqFdUg@mail.gmail.com>

On Wed, Apr 24, 2013 at 5:55 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Currently, if DMA information isn't passed from platform data, then DMA
> will not be used. This patch allows DMA information obtained though Device
> Tree to be used as well.
>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: linux-mmc at vger.kernel.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I've now tested this v2 version with device tree on Nomadik and
U300 and it works like a charm.
Tested-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From jgunthorpe at obsidianresearch.com  Thu May 23 15:01:40 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 23 May 2013 13:01:40 -0600
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130523184028.GU31290@titan.lakedaemon.net>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
Message-ID: <20130523190140.GA4010@obsidianresearch.com>

On Thu, May 23, 2013 at 02:40:28PM -0400, Jason Cooper wrote:

> > But there is a larger problem here then just this one bit.
> > 
> > The PSC1 register must be set properly for the board layout, and today
> > we rely on the bootloader to set it. In fact, even with Sebastian's
> > change the ethernet port won't work without bootloader
> > intervention. The PortReset bit should also be cleared by the driver
> > (and it is only present on some variants of this IP block,
> > apparently).
> > 
> > We know that some Marvell SOC's wack the ethernet registers when they
> > clock gate, and the flip of Clk125Bypass is another symptom of this
> > general problem.
> > 
> > So, long term, the PSC1 must be fully set by the driver, based on DT
> > information describing the board (eg RGMII/MII/1000Base-X [SFP] Phy
> > type), and the layout of this register seems to vary on a SOC by SOC
> > basis.
> > 
> > Thus, I think it is appropriate to call this variant of the eth IP
> > 'marvell,kirkwood-eth' which indicates that the register block follows
> > the kirkwood manual and the PSC1 register specifically has the
> > kirkwood layout.
> 
> Ok, so mv643xx_eth would match both "marvell,orion-eth" and
> "marvell,kirkwood-eth", then write to PSC1 iff it sees a node matching
> "marvell,kirkwood-eth".  I'm not too keen on that, however, the matching
> of the machine doesn't look to good, either.

Why are you not keen on this? It seems like normal device driver
practice, that is what the data field of of_device_id is typically
used for..

There are more compatible strings than just kirkwood and orion in this
driver, the whole TX_BW_CONTROL_OLD_LAYOUT/TX_BW_CONTROL_NEW_LAYOUT
buisness (affecting PPC/MIPS) should also someday be captured with
compatible strings rather than auto-detection too..

> > The question is what other Marvell SOCs have the same PSC1 layout as
> > kirkwood?
> 
> I think marvell,psc1_reset = <>; gives us the most flexibility in
> accurately describing the hardware.

Agree, providing psc1_reset value is a good idea to setup the phy
modes. If all 'orion' SOCs have the PSC1 value then we don't need the
kirkwood differentiators, especially if things like the reset bit are
in the same place.

The same trick Sebastian used to capture the mac address could be used
to capture the PSC1 value from the bootloader.

Basically, I think any IP variants that have idential register layouts
can share a compatible string, otherwise different layouts need
different compatible strings, so the general format:

 compatible = "marvell,SOCNAME-eth", "marvell,<something>-eth";

Seems very sane to me. At least this way if we discover more changes
then the driver can match on the SOCNAME compatible string to find
them.

<someting> = orion for TX_BW_CONTROL_NEW_LAYOUT variants also seems
reasonable..

No idea what to call TX_BW_CONTROL_OLD_LAYOUT variants, or the PPC
variants, not important right now it seems.

(BTW, I wonder if the driver should ideally toggle PSC1 reset at some
point????)

Jason


From jgchunter at gmail.com  Thu May 23 15:02:05 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Thu, 23 May 2013 20:02:05 +0100
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com> <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
Message-ID: <519E67AD.6070702@gmail.com>


On 22/05/13 22:20, Aaro Koskinen wrote:
> On Tue, May 21, 2013 at 08:37:16PM +0100, Jon Hunter wrote:
>> On 21/05/13 18:39, Aaro Koskinen wrote:
>>> On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
>>>> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
>>>>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
>>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
>>>>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
>>>>>>>>
>>>>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
>>>>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
>>>>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
>>>>>>>>
>>>>>>>> The error is coming from regmap code. According to git bisect, it is
>>>>>>>> caused by:
>>>>>>>>
>>>>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
>>>>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
>>>>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
>>>>>>>>
>>>>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
>>>>>>>>
>>>>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
>>>>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
>>>>>>>
>>>>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
>>>>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
>>>>>>>
>>>>>>> For the -rc cycle, it might be possible to fix this by adding a
>>>>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
>>>>>>
>>>>>> The commit reverts cleanly if we also revert
>>>>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
>>>>>> service routine), which seems to be just some minor optimization. The
>>>>>> result is below, and with it 770 works again.
>>>>>
>>>>> Hmm in this case it seems that we should just fix it rather than go back
>>>>> to the old code, so let's take a look at that first.
>>>>
>>>> Does the following fix it for you or do we need to fix something else
>>>> there too?
>>>
>>> Thanks, that fixes Retu probe on 770.
>>
>> Sorry for not responding sooner, but I have been moving. 
>>
>> From looking at the code it appears that the regmap_add_irq_chip()
>> is failing in the retu driver. I am not sure if this will work, 
>> but have you tried making the following change to the retu driver 
>> so that it also uses irq_domain_add_linear() as well? Just a thought ...
> 
> This will trigger WARNING: at drivers/base/regmap/regmap-irq.c:514.

Sorry, there is another change needed. Can you try ...

diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
index a183098..9080cd6 100644
--- a/drivers/mfd/retu-mfd.c
+++ b/drivers/mfd/retu-mfd.c
@@ -267,14 +267,13 @@ static int retu_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
        if (ret < 0)
                return ret;
 
-       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, -1,
+       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, 0,
                                  rdat->irq_chip, &rdev->irq_data);
        if (ret < 0)
                return ret;
 
        ret = mfd_add_devices(rdev->dev, -1, rdat->children, rdat->nchildren,
-                             NULL, regmap_irq_chip_get_base(rdev->irq_data),
-                             NULL);
+                             NULL, 0, regmap_irq_get_domain(rdev->irq_data));
        if (ret < 0) {
                regmap_del_irq_chip(i2c->irq, rdev->irq_data);
                return ret;
 
> Also other drivers report GPIO IRQ issues later in the boot, e.g.
> 
> [    3.907928] genirq: Flags mismatch irq 0. 00000001 (serial wakeup) vs. 00002000 (RETU)
> [    3.923706] No interrupt for UART wake GPIO: 37

Looks like the gpio is just conflicting with the RETU driver.
 
> With Tony's patch (without any Retu modifications), the boot is clean. So
> I guess gpio-omap fix is needed.

Ideally it would be good if the RETU can use linear domains and then may be this
can be avoided.

Cheers
Jon


From linus.walleij at linaro.org  Thu May 23 15:34:22 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 May 2013 21:34:22 +0200
Subject: [GIT PULL] ux500 DMA40 device tree migration base
Message-ID: <CACRpkdZjr=48_GJxsoYgK7DFUqLs10x4o9yky3MzNR7vh24ogA@mail.gmail.com>

Hi ARM SoC folks,

here is a patch set that Lee has been chiseling out recently. I've
accumulated it in my ux500 tree and piled ACKs on the first 36
patches of the patch set. Basically that includes ACKs from
subsystem maintainers Vinod Koul and Herbert Xu for affected
parts.

We need to get this into Linux-next to proceed with further
migration on top of it. All have been circulated on the lists for
a while.

Please pull this into an apropriate ARM SoC branch for v3.11!

If we can get ACKs for the rest of the patches in Lee's set these
will arrive on top of this base as soon as they are ready.

Yours,
Linus Walleij

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-dma40-for-arm-soc

for you to fetch changes up to 95e4bf98520c9a92cd1b87d12c89e8c60c5fe2ca:

  ARM: ux500: Register Cryp and Hash platform drivers on Snowball
(2013-05-23 21:14:25 +0200)

----------------------------------------------------------------
This is a set of patches from Lee Jones to start converting
the ux500 to fetch DMA channels from the device tree:
- Full DT support and channel mapping in the DMA40 driver
- Dropping of platform data for migrated devices on the DT
  boot path.

----------------------------------------------------------------
Lee Jones (35):
      dmaengine: ste_dma40: Assign memcpy channels in the driver
      dmaengine: ste_dma40: Move default memcpy configs into the driver
      dmaengine: ste_dma40: Rectify incorrect configuration validation checking
      dmaengine: ste_dma40: Amalgamate DMA source and destination
channel numbers
      ARM: ux500: Strip out duplicate USB DMA configuration
      dmaengine: ste_dma40: Remove home-brew MAX() macro
      ARM: ux500: Remove unused 'data_width' attributes from SDI DMA configs
      ARM: ux500: Remove unused 'data_width' attributes from SSP DMA configs
      ARM: ux500: Remove unused 'data_width' attributes from UART DMA configs
      ARM: ux500: Remove superfluous 'psize' attribute from Audio platform data
      dmaengine: ste_dma40: Calculate number of logical channels from
physical ones
      dmaengine: ste_dma40: Remove 'always true' checking
      dmaengine: ste_dma40: Move rev error-check up to revision acquisition
      dmaengine: ste_dma40: Also report the number of logical channels
      dmaengine: ste_dma40: Allocate plat_data on declaration
      dmaengine: ste_dma40: Allow driver to be probe()able when DT is enabled
      dmaengine: ste_dma40: Supply full Device Tree parsing support
      ARM: ux500: Pass remnant platform data though to DMA40 driver
      dmaengine: ste_dma40: Separate Logical Global Interrupt Mask
(GIM) unmasking
      dmaengine: ste_dma40: Remove unnecessary call to d40_phy_cfg()
      dmaengine: ste_dma40: Don't configure runtime configurable setup
during allocate
      ARM: ux500: Stop passing UART's platform data for Device Tree boots
      dmaengine: ste_dma40: Only use addresses passed as configuration
information
      dmaengine: ste_dma40: Remove redundant address fetching function
      ARM: ux500: Remove DMA address look-up table
      dmaengine: ste_dma40: Correct copy/paste error
      ARM: ux500: Remove unnecessary attributes from DMA channel request pdata
      crypto: ux500/hash - Prepare clock before enabling it
      crypto: ux500/hash - Set DMA configuration though dma_slave_config()
      ARM: ux500: Stop passing Hash DMA channel config information though pdata
      crypto: ux500/cryp - Prepare clock before enabling it
      crypto: ux500/cryp - Set DMA configuration though dma_slave_config()
      ARM: ux500: Stop passing Cryp DMA channel config information though pdata
      crypto: ux500/[cryp|hash] - Show successful start-up in the bootlog
      ARM: ux500: Register Cryp and Hash platform drivers on Snowball

Linus Walleij (1):
      dmaengine: ste_dma40: Fix up static memcpy event lines

 .../devicetree/bindings/dma/ste-dma40.txt          |  62 ++++
 arch/arm/mach-ux500/board-mop500-audio.c           |  56 +---
 arch/arm/mach-ux500/board-mop500-sdi.c             |  40 +--
 arch/arm/mach-ux500/board-mop500.c                 |  63 +---
 arch/arm/mach-ux500/board-mop500.h                 |   1 +
 arch/arm/mach-ux500/cpu-db8500.c                   |  52 +--
 arch/arm/mach-ux500/devices-db8500.c               | 123 +------
 arch/arm/mach-ux500/ste-dma40-db8500.h             | 193 ++++-------
 arch/arm/mach-ux500/usb.c                          |  18 +-
 drivers/crypto/ux500/cryp/cryp.h                   |   7 +-
 drivers/crypto/ux500/cryp/cryp_core.c              |  31 +-
 drivers/crypto/ux500/hash/hash_alg.h               |   5 +-
 drivers/crypto/ux500/hash/hash_core.c              |  24 +-
 drivers/dma/ste_dma40.c                            | 366 ++++++++++++---------
 drivers/dma/ste_dma40_ll.c                         | 106 +++---
 drivers/dma/ste_dma40_ll.h                         |   3 +-
 include/linux/platform_data/dma-ste-dma40.h        |  20 +-
 17 files changed, 504 insertions(+), 666 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/ste-dma40.txt


From nico at fluxnic.net  Thu May 23 16:09:40 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 23 May 2013 16:09:40 -0400 (EDT)
Subject: [PATCH v7] arm: use built-in byte swap function
In-Reply-To: <20130523114654.1f273241725205c6703b2226@freescale.com>
References: <20130129181046.GC25415@pd.tnic>
 <alpine.LFD.2.02.1302082102380.6300@xanadu.home>
 <20130219203115.114eab79e8d2099c6306d921@freescale.com>
 <alpine.LFD.2.03.1302192151280.6419@syhkavp.arg>
 <1361356696.13482.269.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200835380.6419@syhkavp.arg>
 <1361367842.13482.279.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200905300.6419@syhkavp.arg>
 <1361372008.13482.280.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302201040460.6419@syhkavp.arg>
 <20130220214943.9b28a5b208da9f081387c55e@freescale.com>
 <alpine.LFD.2.03.1302202327370.6419@syhkavp.arg>
 <20130221005221.15279b1372501af12c1e4f32@freescale.com>
 <alpine.LFD.2.03.1302211134160.6419@syhkavp.arg>
 <20130221203327.6558f89277468f7ffffa6506@freescale.com>
 <alpine.LFD.2.03.1302212219100.6419@syhkavp.arg>
 <20130222194032.f7b44aefa5e2723d16767a1b@freescale.com>
 <1361661654.18110.102.camel@shinybook.infradead.org>
 <20130523114654.1f273241725205c6703b2226@freescale.com>
Message-ID: <alpine.LFD.2.03.1305231607060.1918@syhkavp.arg>

On Thu, 23 May 2013, Kim Phillips wrote:

> Enable the compiler intrinsic for byte swapping on arch ARM.  This
> allows the compiler to detect and be able to optimize out byte
> swappings, and has a very modest benefit on vmlinux size (Linaro gcc
> 4.8):
> 
>    text	   data	    bss	    dec	    hex	filename
> 2840310	 123932	  61960	3026202	 2e2d1a	vmlinux-lart #orig
> 2840152	 123932	  61960	3026044	 2e2c7c	vmlinux-lart #builtin-bswap
> 
> 6473120	 314840	5616016	12403976 bd4508	vmlinux-mxs #orig
> 6472586	 314848	5616016	12403450 bd42fa	vmlinux-mxs #builtin-bswap
> 
> 7419872	 318372	 379556	8117800	 7bde28	vmlinux-imx_v6_v7 #orig
> 7419170	 318364	 379556	8117090	 7bdb62	vmlinux-imx_v6_v7 #builtin-bswap
> 
> Signed-off-by: Kim Phillips <kim.phillips at freescale.com>
> Reviewed-by: Nicolas Pitre <nico at linaro.org>
> Acked-by: David Woodhouse <David.Woodhouse at intel.com>
> ---
> resending as v6 appears to have fallen though the cracks.  Russell?

Please send your patch to Russell's patch system:

http://www.arm.linux.org.uk/developer/patches/


Nicolas


From aaro.koskinen at iki.fi  Thu May 23 16:13:58 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Thu, 23 May 2013 23:13:58 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <519E67AD.6070702@gmail.com>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com>
 <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
Message-ID: <20130523201358.GI31836@blackmetal.musicnaut.iki.fi>

On Thu, May 23, 2013 at 08:02:05PM +0100, Jon Hunter wrote:
> On 22/05/13 22:20, Aaro Koskinen wrote:
> > On Tue, May 21, 2013 at 08:37:16PM +0100, Jon Hunter wrote:
> >> On 21/05/13 18:39, Aaro Koskinen wrote:
> >>> On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
> >>>> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
> >>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
> >>>>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> >>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> >>>>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> >>>>>>>>
> >>>>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> >>>>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> >>>>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> >>>>>>>>
> >>>>>>>> The error is coming from regmap code. According to git bisect, it is
> >>>>>>>> caused by:
> >>>>>>>>
> >>>>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> >>>>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
> >>>>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
> >>>>>>>>
> >>>>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
> >>>>>>>>
> >>>>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
> >>>>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
> >>>>>>>
> >>>>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
> >>>>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> >>>>>>>
> >>>>>>> For the -rc cycle, it might be possible to fix this by adding a
> >>>>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
> >>>>>>
> >>>>>> The commit reverts cleanly if we also revert
> >>>>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
> >>>>>> service routine), which seems to be just some minor optimization. The
> >>>>>> result is below, and with it 770 works again.
> >>>>>
> >>>>> Hmm in this case it seems that we should just fix it rather than go back
> >>>>> to the old code, so let's take a look at that first.
> >>>>
> >>>> Does the following fix it for you or do we need to fix something else
> >>>> there too?
> >>>
> >>> Thanks, that fixes Retu probe on 770.
> >>
> >> Sorry for not responding sooner, but I have been moving. 
> >>
> >> From looking at the code it appears that the regmap_add_irq_chip()
> >> is failing in the retu driver. I am not sure if this will work, 
> >> but have you tried making the following change to the retu driver 
> >> so that it also uses irq_domain_add_linear() as well? Just a thought ...
> > 
> > This will trigger WARNING: at drivers/base/regmap/regmap-irq.c:514.
> 
> Sorry, there is another change needed. Can you try ...

I will try this. However, I would also like to point out that Retu works
fine on N800/N810 (OMAP2). If the problem is in Retu, why only OMAP1
is affected?

A.

> diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
> index a183098..9080cd6 100644
> --- a/drivers/mfd/retu-mfd.c
> +++ b/drivers/mfd/retu-mfd.c
> @@ -267,14 +267,13 @@ static int retu_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
>         if (ret < 0)
>                 return ret;
>  
> -       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, -1,
> +       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, 0,
>                                   rdat->irq_chip, &rdev->irq_data);
>         if (ret < 0)
>                 return ret;
>  
>         ret = mfd_add_devices(rdev->dev, -1, rdat->children, rdat->nchildren,
> -                             NULL, regmap_irq_chip_get_base(rdev->irq_data),
> -                             NULL);
> +                             NULL, 0, regmap_irq_get_domain(rdev->irq_data));
>         if (ret < 0) {
>                 regmap_del_irq_chip(i2c->irq, rdev->irq_data);
>                 return ret;
>  
> > Also other drivers report GPIO IRQ issues later in the boot, e.g.
> > 
> > [    3.907928] genirq: Flags mismatch irq 0. 00000001 (serial wakeup) vs. 00002000 (RETU)
> > [    3.923706] No interrupt for UART wake GPIO: 37
> 
> Looks like the gpio is just conflicting with the RETU driver.
>  
> > With Tony's patch (without any Retu modifications), the boot is clean. So
> > I guess gpio-omap fix is needed.
> 
> Ideally it would be good if the RETU can use linear domains and then may be this
> can be avoided.
> 
> Cheers
> Jon


From geert at linux-m68k.org  Thu May 23 16:15:39 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 23 May 2013 22:15:39 +0200
Subject: [PATCH, RFC 19/22] staging/solo6x10: depend on CONFIG_FONTS
In-Reply-To: <1367507786-505303-20-git-send-email-arnd@arndb.de>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-20-git-send-email-arnd@arndb.de>
Message-ID: <CAMuHMdWrVCndJ=Cre5LUgTSyQMxn_XkHUCFa2qCz-ETUO+T-ug@mail.gmail.com>

On Thu, May 2, 2013 at 5:16 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> The new SOLO6X10 driver needs the built-in console fonts, specifically
> the VGA8x16 font and building it without console support results in
> a link error error.
>
> drivers/built-in.o: In function `solo_osd_print':
>  :(.text+0x7d3424): undefined reference to `find_font'
>
> This adds a dependency on the CONFIG_FONTS symbol and changes the
> console code to always build the base driver even if there are
> no specific fonts built-in.
>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Cc: Hans Verkuil <hans.verkuil at cisco.com>
> Cc: Mauro Carvalho Chehab <mchehab at infradead.org>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Sorry for only noticing this now, but CONFIG_FONTS is not about font support.
It's about allowing the user to override the default list of builtin fonts.
I know it's a bad name, but changing this would break make oldconfig.
Or is this allowed?

My fix for the solo6x10 build breakage is
http://marc.info/?l=linux-kernel&m=136861809223875

> ---
>  drivers/staging/media/solo6x10/Kconfig | 1 +
>  drivers/video/console/Makefile         | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/staging/media/solo6x10/Kconfig b/drivers/staging/media/solo6x10/Kconfig
> index ec32776..df6569b 100644
> --- a/drivers/staging/media/solo6x10/Kconfig
> +++ b/drivers/staging/media/solo6x10/Kconfig
> @@ -1,6 +1,7 @@
>  config SOLO6X10
>         tristate "Softlogic 6x10 MPEG codec cards"
>         depends on PCI && VIDEO_DEV && SND && I2C
> +       depends on FONTS
>         select VIDEOBUF2_DMA_SG
>         select VIDEOBUF2_DMA_CONTIG
>         select SND_PCM
> diff --git a/drivers/video/console/Makefile b/drivers/video/console/Makefile
> index a862e91..48da25c 100644
> --- a/drivers/video/console/Makefile
> +++ b/drivers/video/console/Makefile
> @@ -18,6 +18,8 @@ font-objs-$(CONFIG_FONT_MINI_4x6)  += font_mini_4x6.o
>
>  font-objs += $(font-objs-y)
>
> +obj-$(CONFIG_FONTS) += font.o
> +
>  # Each configuration option enables a list of files.
>
>  obj-$(CONFIG_DUMMY_CONSOLE)       += dummycon.o

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From linux at arm.linux.org.uk  Thu May 23 16:26:43 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 23 May 2013 21:26:43 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130523142301.10dbeff9@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305221735.11815.arnd@arndb.de> <20130522180842.7edcc3ee@skate>
 <201305222240.05124.arnd@arndb.de> <20130523142301.10dbeff9@skate>
Message-ID: <20130523202643.GQ18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 02:23:01PM +0200, Thomas Petazzoni wrote:
> But that's *not* the case. Neither the old nor the new bootloaders are
> changing the Device Tree in any way that allows us to know whether
> registers are mapped at 0xd0 and 0xf1.

Who provides this DT blob?  Is it already provided with the board, or
is it something which is provided by others?


From arnd at arndb.de  Thu May 23 16:40:03 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 22:40:03 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523202643.GQ18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523142301.10dbeff9@skate>
 <20130523202643.GQ18614@n2100.arm.linux.org.uk>
Message-ID: <201305232240.03959.arnd@arndb.de>

On Thursday 23 May 2013, Russell King - ARM Linux wrote:
> On Thu, May 23, 2013 at 02:23:01PM +0200, Thomas Petazzoni wrote:
> > But that's not the case. Neither the old nor the new bootloaders are
> > changing the Device Tree in any way that allows us to know whether
> > registers are mapped at 0xd0 and 0xf1.
> 
> Who provides this DT blob?  Is it already provided with the board, or
> is it something which is provided by others?

In theory, the board could provide the DT, but we would always be able
to provide an updated DT blob if necessary. In practice, the DT blob at
the moment is always shipped alongside the kernel, as some interfaces
(e.g. the mbus or pci in case of mvebu) are not final yet.

The boot loader has ways to modify that blob in memory, in order to
pass the information that traditionally is in the ATAGS and other things
like a board specific MAC address. It is straightforward for the bootloader
to update properties like the location of the internal registers, once
we have specified the binding for the mbus, but not until then.

For older boot loaders that only support ATAGS, the update of the DT
blob happens inside of the kernel in arch/arm/boot/compressed/atags_to_fdt.c
on the blob that is appended to the zImage.

	Arnd


From ard.biesheuvel at linaro.org  Thu May 23 16:47:57 2013
From: ard.biesheuvel at linaro.org (Ard Biesheuvel)
Date: Thu, 23 May 2013 22:47:57 +0200
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <alpine.LFD.2.03.1305231108500.1918@syhkavp.arg>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
 <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
 <20130523084126.GI18614@n2100.arm.linux.org.uk>
 <alpine.LFD.2.03.1305231108500.1918@syhkavp.arg>
Message-ID: <CAKv+Gu9FDprQtVitu5dojoWqY15s4ytOCxbFUjUnLsX8L92Zag@mail.gmail.com>

On 23 May 2013 17:23, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> On Thu, 23 May 2013, Russell King - ARM Linux wrote:
>
>> Secondly, it makes it too easy for people to start thinking that FP is
>> safe in the kernel.  It isn't - this will go horribly wrong if the VFP
>> hardware bounces an instruction to the support code.
>
> Hmmm. good point.  We probably should set a flag in kernel_vfp_begin()
> and BUG() if the support code is invoked while that flag is set.
>

Currently, the lazy restore is armed even in kernel mode, so it pulls
in the userland context if you issue NEON/VFP instructions in kernel
mode with the FP unit off. This is probably a side effect of the VFP
detection code relying on this code path as well.
As kernel_vfp_begin() disarms the lazy restore and takes care of
preserving the userland context itself, entering __und_svc because of
NEON/VFP instructions should only be allowed in this particular case,
i.e., VFP detection and all other instances should BUG() imho
(regardless of if we end up doing NEON in the kernel or not). Doing it
that way, I don't think there is a reason for keeping additional
flags.

>> Lastly, what happens if you sleep between kernel_vfp_start() and
>> kernel_vfp_end() ?  That's a context switch which will mess up your
>> VFP state.  I think you need to take a spinlock (not _bh nor _irqsave
>> versions) in here to ensure that people don't get the idea that they
>> _can_ sleep between these two.
>
> Isn't preemption off sufficient to flag that case?  The scheduler is
> very noisy when schedule() is called with preemption disabled.
>

That was my understanding as well.

-- 
Ard.


From nicolas.pitre at linaro.org  Thu May 23 16:57:49 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 23 May 2013 16:57:49 -0400 (EDT)
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <CAKv+Gu9FDprQtVitu5dojoWqY15s4ytOCxbFUjUnLsX8L92Zag@mail.gmail.com>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
 <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
 <20130523084126.GI18614@n2100.arm.linux.org.uk>
 <alpine.LFD.2.03.1305231108500.1918@syhkavp.arg>
 <CAKv+Gu9FDprQtVitu5dojoWqY15s4ytOCxbFUjUnLsX8L92Zag@mail.gmail.com>
Message-ID: <alpine.LFD.2.03.1305231654440.1918@syhkavp.arg>

On Thu, 23 May 2013, Ard Biesheuvel wrote:

> On 23 May 2013 17:23, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> > On Thu, 23 May 2013, Russell King - ARM Linux wrote:
> >
> >> Secondly, it makes it too easy for people to start thinking that FP is
> >> safe in the kernel.  It isn't - this will go horribly wrong if the VFP
> >> hardware bounces an instruction to the support code.
> >
> > Hmmm. good point.  We probably should set a flag in kernel_vfp_begin()
> > and BUG() if the support code is invoked while that flag is set.
> >
> 
> Currently, the lazy restore is armed even in kernel mode, so it pulls
> in the userland context if you issue NEON/VFP instructions in kernel
> mode with the FP unit off. This is probably a side effect of the VFP
> detection code relying on this code path as well.
> As kernel_vfp_begin() disarms the lazy restore and takes care of
> preserving the userland context itself, entering __und_svc because of
> NEON/VFP instructions should only be allowed in this particular case,
> i.e., VFP detection and all other instances should BUG() imho
> (regardless of if we end up doing NEON in the kernel or not). Doing it
> that way, I don't think there is a reason for keeping additional
> flags.

The concern is more about VFP instructions that could trigger an 
exception where support code is invoked to emulate that instruction.


Nicolas


From soren.brinkmann at xilinx.com  Thu May 23 17:33:01 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Thu, 23 May 2013 14:33:01 -0700
Subject: [PATCHv6 01/11] clockevents: Prefer CPU local devices over
 global devices
In-Reply-To: <1368473175-4841-2-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
 <1368473175-4841-2-git-send-email-sboyd@codeaurora.org>
Message-ID: <3a735301-0634-4c83-b0f6-3ecfa04675bf@DB8EHSMHS021.ehs.local>

On Mon, May 13, 2013 at 12:26:05PM -0700, Stephen Boyd wrote:
> On an SMP system with only one global clockevent and a dummy
> clockevent per CPU we run into problems. We want the dummy
> clockevents to be registered as the per CPU tick devices, but
> we can only achieve that if we register the dummy clockevents
> before the global clockevent or if we artificially inflate the
> rating of the dummy clockevents to be higher than the rating
> of the global clockevent. Failure to do so leads to boot
> hangs when the dummy timers are registered on all other CPUs
> besides the CPU that accepted the global clockevent as its tick
> device and there is no broadcast timer to poke the dummy
> devices.
> 
> If we're registering multiple clockevents and one clockevent is
> global and the other is local to a particular CPU we should
> choose to use the local clockevent regardless of the rating of
> the device. This way, if the clockevent is a dummy it will take
> the tick device duty as long as there isn't a higher rated tick
> device and any global clockevent will be bumped out into
> broadcast mode, fixing the problem described above.
> 
> Reported-by: Mark Rutland <mark.rutland at arm.com>
> Tested-by: Mark Rutland <mark.rutland at arm.com>
> Cc: John Stultz <john.stultz at linaro.org>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
Tested-by: S?ren Brinkmann <soren.brinkmann at xilinx.com>

I tested this on Zynq. Zynq uses the ARM twd timer as clockevent devices when
available. When I remove the twd nodes from DT the clockevent device is
a timer common to both CPUs. Without this patch this seems to stall the
second CPU resulting in the system to hang sooner or later.

[   65.360000] INFO: rcu_preempt detected stalls on CPUs/tasks:
[   65.360000]  1: (1 GPs behind) idle=56e/0/0 softirq=0/0 
[   65.360000]  (detected by 0, t=6502 jiffies, g=4294966997, c=4294966996, q=6844)
[   65.360000] Task dump for CPU 1:
[   65.360000] swapper/1       R running      0     0      1 0x00000000

With this patch everything looks fine.

	S?ren




From dinguyen at altera.com  Thu May 23 17:36:37 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 23 May 2013 16:36:37 -0500
Subject: [PATCHv3 1/6] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Message-ID: <1369345002-20002-1-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Moved "disabled" status to dtsi file
---
 arch/arm/boot/dts/socfpga.dtsi         |   18 ++++++++++++++++--
 arch/arm/boot/dts/socfpga_cyclone5.dts |   13 +++++++++++++
 arch/arm/boot/dts/socfpga_vt.dts       |    5 +++++
 3 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13..02bb425 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
 
 	aliases {
 		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		timer0 = &timer0;
@@ -238,13 +239,26 @@
 				};
 			};
 
-		gmac0: stmmac at ff700000 {
+		gmac0: ethernet at ff700000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff700000 0x2000>;
 			interrupts = <0 115 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			phy-mode = "gmii";
+			clocks = <&emac0_clk>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+		};
+
+		gmac1: ethernet at ff702000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+			reg = <0xff702000 0x2000>;
+			interrupts = <0 120 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+			clocks = <&emac1_clk>;
+			clock-names = "stmmaceth";
+			status = "disabled";
 		};
 
 		L2: l2-cache at fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958..973999d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
 	soc {
 		clkmgr at ffd04000 {
 			clocks {
@@ -41,6 +48,12 @@
 			};
 		};
 
+		ethernet at ff702000 {
+			phy-mode = "rgmii";
+			phy-addr = <0xffffffff>; /* probe for phy addr */
+			status = "okay";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d..d1ec0ca 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,11 @@
 			};
 		};
 
+		ethernet at ff700000 {
+			phy-mode = "gmii";
+			status = "okay";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 23 17:36:39 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 23 May 2013 16:36:39 -0500
Subject: [PATCHv3 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369345002-20002-3-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Mike Turquette <mturquette at linaro.org>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v3:
- Addressed comments from Pavel

v2:
- Fix space/indent errors
- Add streq for strcmp == 0
---
 drivers/clk/socfpga/clk.c |  194 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 185 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315..5bb848c 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,15 +24,17 @@
 #include <linux/of.h>
 
 /* Clock Manager offsets */
-#define CLKMGR_CTRL    0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL	0x0
+#define CLKMGR_BYPASS	0x4
+#define CLKMGR_L4SRC	0x70
+#define CLKMGR_PERPLL_SRC	0xAC
 
 /* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS		(1<<0)
+#define SDRAMPLL_BYPASS		(1<<1)
+#define SDRAMPLL_SRC_BYPASS	(1<<2)
+#define PERPLL_BYPASS		(1<<3)
+#define PERPLL_SRC_BYPASS	(1<<4)
 
 #define SOCFPGA_PLL_BG_PWRDWN		0
 #define SOCFPGA_PLL_EXT_ENA		1
@@ -41,6 +43,17 @@
 #define SOCFPGA_PLL_DIVF_SHIFT	3
 #define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT	16
+#define SOCFGPA_MAX_PARENTS	3
+
+#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
+#define SOCFPGA_NAND_CLK		"nand_clk"
+#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
+#define SOCFPGA_MMC_CLK			"mmc_clk"
+#define SOCFPGA_DB_CLK			"gpio_db_clk"
+
+#define div_mask(width)	((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -49,6 +62,9 @@ struct socfpga_clk {
 	char *parent_name;
 	char *clk_name;
 	u32 fixed_div;
+	void __iomem *div_reg;
+	u32 width;	/* only valid if div_reg != 0 */
+	u32 shift;	/* only valid if div_reg != 0 */
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 
 	socfpga_clk->hw.hw.init = &init;
 
-	if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
-			strcmp(clk_name, "sdram_pll")) {
+	if (streq(clk_name, "main_pll") ||
+		streq(clk_name, "periph_pll") ||
+		streq(clk_name, "sdram_pll")) {
 		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
 		clk_pll_ops.enable = clk_gate_ops.enable;
 		clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 	return clk;
 }
 
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+	u32 l4_src;
+	u32 perpll_src;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		return l4_src &= 0x1;
+	}
+	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		return !!(l4_src & 2);
+	}
+
+	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+		return perpll_src &= 0x3;
+	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+			return (perpll_src >> 2) & 3;
+
+	/* QSPI clock */
+	return (perpll_src >> 4) & 3;
+
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+	u32 src_reg;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x1;
+		src_reg |= parent;
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x2;
+		src_reg |= (parent << 1);
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+			src_reg &= ~0x3;
+			src_reg |= parent;
+		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+			src_reg &= ~0xC;
+			src_reg |= (parent << 2);
+		} else {/* QSPI clock */
+			src_reg &= ~0x30;
+			src_reg |= (parent << 4);
+		}
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	}
+
+	return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+	u32 div = 1, val;
+
+	if (socfpgaclk->fixed_div)
+		div = socfpgaclk->fixed_div;
+	else if (socfpgaclk->div_reg) {
+		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+		val &= div_mask(socfpgaclk->width);
+		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+			div = val + 1;
+		else
+			div = (1 << val);
+	}
+
+	return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+	.recalc_rate = socfpga_clk_recalc_rate,
+	.get_parent = socfpga_clk_get_parent,
+	.set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 clk_gate[2];
+	u32 div_reg[3];
+	u32 fixed_div;
+	struct clk *clk;
+	struct socfpga_clk *socfpga_clk;
+	const char *clk_name = node->name;
+	const char *parent_name[SOCFGPA_MAX_PARENTS];
+	struct clk_init_data init;
+	int rc;
+	int i = 0;
+
+	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+	if (WARN_ON(!socfpga_clk))
+		return;
+
+	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+	if (rc)
+		clk_gate[0] = 0;
+
+	if (clk_gate[0]) {
+		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+		socfpga_clk->hw.bit_idx = clk_gate[1];
+
+		gateclk_ops.enable = clk_gate_ops.enable;
+		gateclk_ops.disable = clk_gate_ops.disable;
+	}
+
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		socfpga_clk->fixed_div = 0;
+	else
+		socfpga_clk->fixed_div = fixed_div;
+
+	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+	if (!rc) {
+		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+		socfpga_clk->shift = div_reg[1];
+		socfpga_clk->width = div_reg[2];
+	} else {
+		socfpga_clk->div_reg = 0;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+			of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	init.parent_names = parent_name;
+	init.num_parents = i;
+	socfpga_clk->hw.hw.init = &init;
+
+	clk = clk_register(NULL, &socfpga_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(socfpga_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(rc))
+		return;
+}
+
 static void __init socfpga_pll_init(struct device_node *node)
 {
 	socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
 
+static void __init socfpga_gate_init(struct device_node *node)
+{
+	socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
 void __init socfpga_init_clocks(void)
 {
 	struct clk *clk;
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 23 17:36:38 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 23 May 2013 16:36:38 -0500
Subject: [PATCHv3 2/6] ARM: socfpga: dts: Add gate-clock bindings
In-Reply-To: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369345002-20002-2-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
the peripherals.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 .../devicetree/bindings/clock/altr_socfpga.txt     |    7 +
 arch/arm/boot/dts/socfpga.dtsi                     |  199 ++++++++++++++++++++
 2 files changed, 206 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index bd0c841..0045433 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -9,6 +9,9 @@ Required properties:
 	"altr,socfpga-pll-clock" - for a PLL clock
 	"altr,socfpga-perip-clock" - The peripheral clock divided from the
 		PLL clock.
+	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
 	either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+        and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+        and width.
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 02bb425..bee62a2 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -95,6 +95,12 @@
 						compatible = "fixed-clock";
 					};
 
+					f2s_periph_ref_clk: f2s_periph_ref_clk {
+						#clock-cells = <0>;
+						compatible = "fixed-clock";
+						clock-frequency = <10000000>;
+					};
+
 					main_pll: main_pll {
 						#address-cells = <1>;
 						#size-cells = <0>;
@@ -236,6 +242,199 @@
 							reg = <0xD4>;
 						};
 					};
+
+				mpu_periph_clk: mpu_periph_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <4>;
+					};
+
+				mpu_l2_ram_clk: mpu_l2_ram_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <2>;
+					};
+
+				l4_main_clk: l4_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					clk-gate = <0x60 0>;
+					};
+
+				l3_main_clk: l3_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					};
+
+				l3_mp_clk: l3_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 0 2>;
+					clk-gate = <0x60 1>;
+					};
+
+				l3_sp_clk: l3_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 2 2>;
+				};
+
+				l4_mp_clk: l4_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 4 3>;
+					clk-gate = <0x60 2>;
+					};
+
+				l4_sp_clk: l4_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 7 3>;
+					clk-gate = <0x60 3>;
+					};
+
+				dbg_at_clk: dbg_at_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 0 2>;
+					clk-gate = <0x60 4>;
+					};
+
+				dbg_clk: dbg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 2 2>;
+					clk-gate = <0x60 5>;
+					};
+
+				dbg_trace_clk: dbg_trace_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x6C 0 3>;
+					clk-gate = <0x60 6>;
+					};
+
+				dbg_timer_clk: dbg_timer_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					clk-gate = <0x60 7>;
+					};
+
+				cfg_clk: cfg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 8>;
+					};
+
+				s2f_user0_clk: s2f_user0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 9>;
+					};
+
+				emac_0_clk: emac_0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac0_clk>;
+					clk-gate = <0xa0 0>;
+					};
+
+				emac_1_clk: emac_1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac1_clk>;
+					clk-gate = <0xa0 1>;
+					};
+
+				usb_mp_clk: usb_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 2>;
+					div-reg = <0xa4 0 3>;
+					};
+
+				spi_m_clk: spi_m_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 3>;
+					div-reg = <0xa4 3 3>;
+					};
+
+				can0_clk: can0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 4>;
+					div-reg = <0xa4 6 3>;
+					};
+
+				can1_clk: can1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 5>;
+					div-reg = <0xa4 9 3>;
+					};
+
+				gpio_db_clk: gpio_db_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 6>;
+					div-reg = <0xa8 0 24>;
+					};
+
+				s2f_user1_clk: s2f_user1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&s2f_usr1_clk>;
+					clk-gate = <0xa0 7>;
+					};
+
+				sdmmc_clk: sdmmc_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 8>;
+					};
+
+				nand_x_clk: nand_x_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 9>;
+					};
+
+				nand_clk: nand_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 10>;
+					fixed-divider = <4>;
+					};
+
+				qspi_clk: qspi_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+					clk-gate = <0xa0 11>;
+					};
 				};
 			};
 
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 23 17:36:42 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 23 May 2013 16:36:42 -0500
Subject: [PATCHv3 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369345002-20002-6-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add platform specific functionality for the DW SD/MMC driver for
SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
can use this define.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Seungwon Jeon <tgih.jun at samsung.com>
CC: Jaehoon Chung <jh80.chung at samsung.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: linux-mmc at vger.kernel.org

v3:
- Addressed comments from Seugwon, Jaehoon, and Pavel
- Use clk_disable_unprepare/clk_prepare_enable

v2:
- Use syscon and regmap
- Avoid divide by zero
- Remove the need to set PWR_EN
---
 drivers/mmc/host/Kconfig          |    8 +++
 drivers/mmc/host/Makefile         |    1 +
 drivers/mmc/host/dw_mmc-exynos.c  |    2 -
 drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h         |    1 +
 5 files changed, 149 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9ab8f8d..1be2289 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Exynos4 and Exynos5 SoC's.
 
+config MMC_DW_SOCFPGA
+	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
+	depends on MMC_DW
+	select MMC_DW_PLTFM
+	help
+	  This selects support for Altera SoCFPGA specific extensions to the
+	  Synopsys DesignWare Memory Card Interface driver.
+
 config MMC_DW_PCI
 	tristate "Synopsys Designware MCI support on PCI bus"
 	depends on MMC_DW && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cd32280..67718c1 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
 obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
 obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
 obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
+obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
 obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
 obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..866edef 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -31,8 +31,6 @@
 					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
 					SDMMC_CLKSEL_CCLK_DIVIDER(z))
 
-#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
-
 #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
 
diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
new file mode 100644
index 0000000..3cc1afc
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -0,0 +1,139 @@
+/*
+ * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
+ *
+ *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Taken from dw_mmc-exynos.c
+ */
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
+#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
+	((((smplsel) & 0x38) << 3) | (((drvsel) & 0x7) << 0))
+
+/* SOCFPGA implementation specific driver private data */
+struct dw_mci_socfpga_priv_data {
+	u8	ciu_div; /* card interface unit divisor */
+	u32	hs_timing; /* bitmask for CIU clock phase shift */
+	struct regmap   *sysreg; /* regmap for system manager register */
+};
+
+static int dw_mci_socfpga_priv_init(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv;
+
+	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(host->dev, "mem alloc failed for private data\n");
+		return -ENOMEM;
+	}
+
+	host->priv = priv;
+
+	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+	if (IS_ERR(priv->sysreg)) {
+		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+		return PTR_ERR(priv->sysreg);
+	}
+
+	return 0;
+}
+
+static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	clk_disable_unprepare(host->ciu_clk);
+	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
+	clk_prepare_enable(host->ciu_clk);
+
+	host->bus_hz /= (priv->ciu_div + 1);
+	return 0;
+}
+
+static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
+		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+	struct device_node *np = host->dev->of_node;
+	u32 timing[2];
+	u32 div = 0;
+	int ret;
+
+	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
+	if (ret)
+		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
+	priv->ciu_div = div;
+
+	ret = of_property_read_u32_array(np,
+			"altr,dw-mshc-sdr-timing", timing, 2);
+	if (ret)
+		return ret;
+
+	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+	return 0;
+}
+
+static const struct dw_mci_drv_data socfpga_drv_data = {
+	.init			= dw_mci_socfpga_priv_init,
+	.setup_clock		= dw_mci_socfpga_setup_clock,
+	.prepare_command	= dw_mci_socfpga_prepare_command,
+	.parse_dt		= dw_mci_socfpga_parse_dt,
+};
+
+static const struct of_device_id dw_mci_socfpga_match[] = {
+	{ .compatible = "altr,socfpga-dw-mshc",
+			.data = &socfpga_drv_data, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
+
+int dw_mci_socfpga_probe(struct platform_device *pdev)
+{
+	const struct dw_mci_drv_data *drv_data;
+	const struct of_device_id *match;
+
+	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
+	drv_data = match->data;
+	return dw_mci_pltfm_register(pdev, drv_data);
+}
+
+static struct platform_driver dw_mci_socfpga_pltfm_driver = {
+	.probe		= dw_mci_socfpga_probe,
+	.remove		= __exit_p(dw_mci_pltfm_remove),
+	.driver		= {
+		.name		= "dwmmc_socfpga",
+		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
+		.pm		= &dw_mci_pltfm_pmops,
+	},
+};
+
+module_platform_driver(dw_mci_socfpga_pltfm_driver);
+
+MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:dwmmc-socfpga");
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0b74189..3700cb2 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 23 17:36:40 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 23 May 2013 16:36:40 -0500
Subject: [PATCHv3 4/6] ARM: socfpga: Add syscon to be part of socfpga
In-Reply-To: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369345002-20002-4-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

SOCFPGA has a system manager register block can be accessed by using
the syscon driver.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Cc: <linux at arm.linux.org.uk>
---
 arch/arm/mach-socfpga/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 566e804..07dff6f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -13,5 +13,6 @@ config ARCH_SOCFPGA
 	select GPIO_PL061 if GPIOLIB
 	select HAVE_ARM_SCU
 	select HAVE_SMP
+	select MFD_SYSCON
 	select SPARSE_IRQ
 	select USE_OF
-- 
1.7.9.5




From dinguyen at altera.com  Thu May 23 17:36:41 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 23 May 2013 16:36:41 -0500
Subject: [PATCHv3 5/6] ARM: socfpga: dts: Add support for SD/MMC
In-Reply-To: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369345002-20002-5-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for SD/MMC for SOCFPGA.
Add "syscon" to the "altr,sys-mgr" binding.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Add "syscon" to "altr,sys-mgr"
- Remove pwr-en field
---
 .../devicetree/bindings/mmc/socfpga-dw-mshc.txt    |   60 ++++++++++++++++++++
 arch/arm/boot/dts/socfpga.dtsi                     |   13 ++++-
 arch/arm/boot/dts/socfpga_cyclone5.dts             |   13 +++++
 arch/arm/boot/dts/socfpga_vt.dts                   |   12 ++++
 4 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
new file mode 100644
index 0000000..9d7062c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
@@ -0,0 +1,60 @@
+* Altera SOCFPGA specific extensions to the Synopsis Designware Mobile
+  Storage Host Controller
+
+Required Properties:
+
+* compatible: should be
+	- "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA
+	  specific extentions.
+
+* altr,dw-mshc-ciu-div: Specifies the divider value for the card interface
+  unit (ciu) clock. The value should be (n-1). For Altera's SOCFPGA, the divider
+  value is fixed at 3, which mean parent_clock/4.
+
+* altr,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
+  in transmit mode and CIU clock phase shift value in receive mode for single
+  data rate mode operation. Refer notes below for the order of the cells and the
+  valid values.
+
+  Notes for the sdr-timing values:
+
+    The order of the cells should be
+      - First Cell: CIU clock phase shift value for RX mode, smplsel bits in
+	the system manager SDMMC control group.
+      - Second Cell: CIU clock phase shift value for TX mode, drvsel bits in
+	the system manager SDMMC control group.
+
+    Valid values for SDR CIU clock timing for SOCFPGA:
+      - valid value for tx phase shift and rx phase shift is 0 to 7.
+
+Required properties for a slot:
+
+* bus-width: Data width for card slot. 4-bit or 8-bit data.
+
+Example:
+
+  The MSHC controller node can be split into two portions, SoC specific and
+  board specific portions as listed below.
+
+	dwmmc0 at ff704000 {
+		compatible = "altr,socfpga-dw-mshc";
+		reg = <0xff704000 0x1000>;
+		interrupts = <0 139 4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc0 at ff704000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x400>;
+		altr,dw-mshc-ciu-div = <3>;
+      		altr,dw-mshc-sdr-timing = <0 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+		};
+	};
+
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index bee62a2..dbf7f22 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -468,6 +468,17 @@
 			cache-level = <2>;
 		};
 
+		mmc: dwmmc0 at ff704000 {
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0xff704000 0x1000>;
+			interrupts = <0 139 4>;
+			fifo-depth = <0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+			clock-names = "biu", "ciu";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
@@ -521,7 +532,7 @@
 			};
 
 		sysmgr at ffd08000 {
-				compatible = "altr,sys-mgr";
+				compatible = "altr,sys-mgr", "syscon";
 				reg = <0xffd08000 0x4000>;
 			};
 	};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 973999d..1853cb1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -54,6 +54,19 @@
 			status = "okay";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <3>;
+			altr,dw-mshc-sdr-timing = <0 3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0ca..d93deb0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -46,6 +46,18 @@
 			status = "okay";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From arnd at arndb.de  Thu May 23 17:44:11 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 23:44:11 +0200
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <519A1BBB.2070903@st.com>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305171636.49627.arnd@arndb.de> <519A1BBB.2070903@st.com>
Message-ID: <201305232344.11974.arnd@arndb.de>

On Monday 20 May 2013, Srinivas KANDAGATLA wrote:
> On 17/05/13 15:36, Arnd Bergmann wrote:
>
> Some of the drivers like Ethernet already provide higher level
> interfaces via callbacks. We did implement such a callbacks per each SOC
> in non-DT case, and ended up having code duplicated for each SOC.
> 
> On the other hand using device trees to describe the HW
> configuration(sysconfs) made more sense and got rid of SOC specific
> callbacks.

I'm sure it's possible to reduce the duplication without going all
the way to describing every bit in DT.

> > For drivers that are essentially just wrappers around sysconf,
> > I would make them one driver per SoC and use a low-level interface
> > but still hardcode the offsets in the driver instead of using DT
> > to find the registers.
> > 
> > The pinctrl and reset drivers are examples of this.
> 
> In pinctrl bindings case, I think we could do better job by replacing
> the existing bindings of sysconfs for a group of banks with just two
> integer offsets. This would mean that, we can still use the a common
> driver across the SOCs.
>
> And w.r.t to reset, we are planning on using sysconf based
> reset-controller API sitting underneath the reset-controller subsystem.
> Passing the information from device trees would be much clear and
> flexible than adding new driver per/SOC.

Ok

> >> 2> The infrastructure should protect the claimed registers from
> >> over-writing by other drivers. We do this by claim-read/write-release
> >> style API.
> > 
> > I don't understand this part. Is it about atomicity of accesses to
> > 32-bit registers when you only want to change a bit? That is something
> > the regmap interface handles already.
> 
> I forget to mention a important point here, the protection is at bit
> level for the sysconfs. Some of sysconfs have bits shared across IPs, so
> protecting them while the IP is still using it is what we are trying to
> achieve with sysconf-claim/release apis.
> While it may be overkill, but In past it has found bugs and been helpful
> with a meaning full debug output.

Can you give an example of something that is shared across multiple IPs?

Are those always done in the way that you have e.g. the ethernet pinctrl
in the same register as the usb pinctrl, or could you have an ethernet
pinctrl setting mixed together with the usb clock setting for instance?

If the hardware has been designed in a sensible way rather than just
grown by randomly adding bits in open spaces, I would assume that it's
possible to have high-level interfaces built around ranges of registers
rather than arbitrary subsets of registers.

	Arnd


From arnd at arndb.de  Thu May 23 17:47:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 May 2013 23:47:46 +0200
Subject: [PATCH, RFC 19/22] staging/solo6x10: depend on CONFIG_FONTS
In-Reply-To: <CAMuHMdWrVCndJ=Cre5LUgTSyQMxn_XkHUCFa2qCz-ETUO+T-ug@mail.gmail.com>
References: <1367507786-505303-1-git-send-email-arnd@arndb.de>
 <1367507786-505303-20-git-send-email-arnd@arndb.de>
 <CAMuHMdWrVCndJ=Cre5LUgTSyQMxn_XkHUCFa2qCz-ETUO+T-ug@mail.gmail.com>
Message-ID: <201305232347.47080.arnd@arndb.de>

On Thursday 23 May 2013, Geert Uytterhoeven wrote:
> Sorry for only noticing this now, but CONFIG_FONTS is not about font support.
> It's about allowing the user to override the default list of builtin fonts.
> I know it's a bad name, but changing this would break make oldconfig.
> Or is this allowed?
> 
> My fix for the solo6x10 build breakage is
> http://marc.info/?l=linux-kernel&amp;m=136861809223875

Right, that sounds like a better solution.

	Arnd


From sebastian.hesselbarth at gmail.com  Thu May 23 18:40:26 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 24 May 2013 00:40:26 +0200
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130523184028.GU31290@titan.lakedaemon.net>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
Message-ID: <519E9ADA.3040204@gmail.com>

On 05/23/2013 08:40 PM, Jason Cooper wrote:
> On Thu, May 23, 2013 at 11:53:57AM -0600, Jason Gunthorpe wrote:
>> On Thu, May 23, 2013 at 01:23:39PM -0400, Jason Cooper wrote:
>>> Shouldn't it rather be
>>>
>>> 	compatible = "marvell,kirkwood-eth", "marvell,orion-eth";
>>
>> Not sure about orion-eth?

Jason, Jason,

sorry I didn't came back to this conversation earlier. I already
reworked the patch to rely on 
of_device_is_compatible(.."marvell,kirkwood-eth"..). This is a
kirkwood only thing as other Orions cannot do clock gating or
retain critcal register content (Dove). I will stick with orion-eth
for all other and maybe introduce new compatible strings (and new
fixes) as soon as issues surface.

>>> I'm inclined to go with of_machine_is_compatible() since the only
>>> concrete difference we know is that the tweak is needed on kirkwood and
>>> nowhere else.
>>
>> But there is a larger problem here then just this one bit.
>>
>> The PSC1 register must be set properly for the board layout, and today
>> we rely on the bootloader to set it. In fact, even with Sebastian's
>> change the ethernet port won't work without bootloader
>> intervention. The PortReset bit should also be cleared by the driver
>> (and it is only present on some variants of this IP block,
>> apparently).

Actually, fixing modular scenarios is only for the sake of multiarch
someday. I don't see the point in running current kernel without eth
compiled in _on a NAS SoC_ ;)

On Dockstar which I tested, clearing CLK125_BYPASS_EN to make it work
after clock gating, it might be a coincidence that bootloader's PSC1
setup matches reset value here - so please test the patch on other
Kirkwood boards also.

But, as long as no other issue arise, I will not start to modifiy
mv643xx_eth out of the blue. I has been working for ages and breaking
PPC is not my intention. There are other things David Miller already
requested to get fixed and honestly I even thought about a fresh start
for it. Maybe I'll come back to it when barebox gets it's driver
someday.

>> We know that some Marvell SOC's wack the ethernet registers when they
>> clock gate, and the flip of Clk125Bypass is another symptom of this
>> general problem.

Which SoCs except Kirkwood? I cannot reproduce any of this behavior on
Dove - and from what I can see from the FS of Orion5x or MV78x00 there
are no clock gating registers.

>> So, long term, the PSC1 must be fully set by the driver, based on DT
>> information describing the board (eg RGMII/MII/1000Base-X [SFP] Phy
>> type), and the layout of this register seems to vary on a SOC by SOC
>> basis.

Agree, but I tend to not go at it now. mv643xx_eth has never set up that
registers and actually it never connects anything else than GMII phy (or 
no phy at all). The latter is easy but the for the other, I like to
give up that brain-dead multi-device driver and stick with one device
for both shared and up to three ports. From what I can see from e.g.
ixgbe or any other multi-port eth drivers they all attach the network
device to a single (pci) device.

>> Thus, I think it is appropriate to call this variant of the eth IP
>> 'marvell,kirkwood-eth' which indicates that the register block follows
>> the kirkwood manual and the PSC1 register specifically has the
>> kirkwood layout.
>
> Ok, so mv643xx_eth would match both "marvell,orion-eth" and
> "marvell,kirkwood-eth", then write to PSC1 iff it sees a node matching
> "marvell,kirkwood-eth".  I'm not too keen on that, however, the matching
> of the machine doesn't look to good, either.

I didn't choose "marvell,mv643xx-eth" for two reasons
(a) The DT layout is slightly different with phy-handle instead of phy
and marvell prefixed properties. Choosing a compatible string that
matches any PPC compatible string will cause driver racing with sysdev
code to set up platform_data.

(b) I chose to name the controller "orion-eth" and the port
"orion-eth-port" .. PPC has "mv64360-eth" for the port and some 
"mv64360-eth-block" or "-group" for the controller. IMHO not intuitive,
but it just a name anyway.

> Perhaps a better answer is to add a boolean, "marvell,kirkwood_psc1" and
> check for that?
>
> Or, marvell,psc1_reset =<0xWWXXYYZZ>;

For the _long_ run: Exploit either already present phy properties for
MII and friends or introduce new marvell prefixed .. but not misuse DT
for register values here. Each SoC should setup mv643xx_eth properly,
but that should be based on a clean approach _and_ enough people willing
to test that.

I just have a Dockstar and Topkick which is running 24/7. I didn't even
check if only 6281 suffers from it or also 6282 or maybe only some
revisions of 6281. This patch is a fix, nothing more nothing
less. If you have Kirkwoods around, please test if it suffers from
loosing the MAC address and if it works after insmod with the fix
installed.

>> The question is what other Marvell SOCs have the same PSC1 layout as
>> kirkwood?
>
> I think marvell,psc1_reset =<>; gives us the most flexibility in
> accurately describing the hardware.

IMHO using that is just another workaround for a broken driver. We
could hack the whole register setup in DT as it would still accurately
describe HW. Don't get me wrong, but I don't like it.

Haven't checked how happy Linus Walleij is about pinctrl drivers with
reg values hacked in lately.

Sebastian



From plagnioj at jcrosoft.com  Thu May 23 18:59:16 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 00:59:16 +0200
Subject: [PATCH 1/1] ARM: at91: at91sam9n12: move external irq declatation to
 DT
Message-ID: <1369349956-22985-1-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9n12.dtsi |    1 +
 arch/arm/mach-at91/at91sam9n12.c   |    6 ------
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 566af32..d864f7a9 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -60,6 +60,7 @@
 				compatible = "atmel,at91rm9200-aic";
 				interrupt-controller;
 				reg = <0xfffff000 0x200>;
+				atmel,external-irqs = <31>;
 			};
 
 			ramc0: ramc at ffffe800 {
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 13cdbcd..c7d670d1 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -223,13 +223,7 @@ static void __init at91sam9n12_map_io(void)
 	at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
 }
 
-void __init at91sam9n12_initialize(void)
-{
-	at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
-}
-
 AT91_SOC_START(at91sam9n12)
 	.map_io = at91sam9n12_map_io,
 	.register_clocks = at91sam9n12_register_clocks,
-	.init = at91sam9n12_initialize,
 AT91_SOC_END
-- 
1.7.10.4



From wsa at the-dreams.de  Thu May 23 19:09:46 2013
From: wsa at the-dreams.de (Wolfram Sang)
Date: Fri, 24 May 2013 01:09:46 +0200
Subject: [PATCH 4/6] i2c: stu300: do not request a specific clock name
In-Reply-To: <1369330288-14856-5-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
 <1369330288-14856-5-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130523230943.GA3645@katana>

On Thu, May 23, 2013 at 07:31:26PM +0200, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> We have used the default clock associated with the block
> for a long time, only heuristics in the clock system has
> made this work anyway. This needs to be done away with as
> we start probing this driver and its clocks exclusively
> from the device tree.
> 
> Cc: Wolfram Sang <wsa at the-dreams.de>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Acked-by: Wolfram Sang <wsa at the-dreams.de>



From linux at arm.linux.org.uk  Thu May 23 19:09:11 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 00:09:11 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <201305232240.03959.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523142301.10dbeff9@skate>
 <20130523202643.GQ18614@n2100.arm.linux.org.uk>
 <201305232240.03959.arnd@arndb.de>
Message-ID: <20130523230911.GR18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 10:40:03PM +0200, Arnd Bergmann wrote:
> On Thursday 23 May 2013, Russell King - ARM Linux wrote:
> > On Thu, May 23, 2013 at 02:23:01PM +0200, Thomas Petazzoni wrote:
> > > But that's not the case. Neither the old nor the new bootloaders are
> > > changing the Device Tree in any way that allows us to know whether
> > > registers are mapped at 0xd0 and 0xf1.
> > 
> > Who provides this DT blob?  Is it already provided with the board, or
> > is it something which is provided by others?
> 
> In theory, the board could provide the DT, but we would always be able
> to provide an updated DT blob if necessary. In practice, the DT blob at
> the moment is always shipped alongside the kernel, as some interfaces
> (e.g. the mbus or pci in case of mvebu) are not final yet.
> 
> The boot loader has ways to modify that blob in memory, in order to
> pass the information that traditionally is in the ATAGS and other things
> like a board specific MAC address. It is straightforward for the bootloader
> to update properties like the location of the internal registers, once
> we have specified the binding for the mbus, but not until then.
> 
> For older boot loaders that only support ATAGS, the update of the DT
> blob happens inside of the kernel in arch/arm/boot/compressed/atags_to_fdt.c
> on the blob that is appended to the zImage.

*Sigh*

No, I'm not asking about the principle.  I'm asking _in this particular
problem case_ who provides the DT blob?

So the person to answer that question is Thomas or someone who is using
the boards concerned.


From linux at arm.linux.org.uk  Thu May 23 19:13:36 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 00:13:36 +0100
Subject: [PATCH v7] arm: use built-in byte swap function
In-Reply-To: <20130523114654.1f273241725205c6703b2226@freescale.com>
References: <alpine.LFD.2.03.1302201040460.6419@syhkavp.arg>
 <20130220214943.9b28a5b208da9f081387c55e@freescale.com>
 <alpine.LFD.2.03.1302202327370.6419@syhkavp.arg>
 <20130221005221.15279b1372501af12c1e4f32@freescale.com>
 <alpine.LFD.2.03.1302211134160.6419@syhkavp.arg>
 <20130221203327.6558f89277468f7ffffa6506@freescale.com>
 <alpine.LFD.2.03.1302212219100.6419@syhkavp.arg>
 <20130222194032.f7b44aefa5e2723d16767a1b@freescale.com>
 <1361661654.18110.102.camel@shinybook.infradead.org>
 <20130523114654.1f273241725205c6703b2226@freescale.com>
Message-ID: <20130523231336.GS18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 11:46:54AM -0500, Kim Phillips wrote:
> Enable the compiler intrinsic for byte swapping on arch ARM.  This
> allows the compiler to detect and be able to optimize out byte
> swappings, and has a very modest benefit on vmlinux size (Linaro gcc
> 4.8):
> 
>    text	   data	    bss	    dec	    hex	filename
> 2840310	 123932	  61960	3026202	 2e2d1a	vmlinux-lart #orig
> 2840152	 123932	  61960	3026044	 2e2c7c	vmlinux-lart #builtin-bswap
> 
> 6473120	 314840	5616016	12403976 bd4508	vmlinux-mxs #orig
> 6472586	 314848	5616016	12403450 bd42fa	vmlinux-mxs #builtin-bswap
> 
> 7419872	 318372	 379556	8117800	 7bde28	vmlinux-imx_v6_v7 #orig
> 7419170	 318364	 379556	8117090	 7bdb62	vmlinux-imx_v6_v7 #builtin-bswap
> 
> Signed-off-by: Kim Phillips <kim.phillips at freescale.com>
> Reviewed-by: Nicolas Pitre <nico at linaro.org>
> Acked-by: David Woodhouse <David.Woodhouse at intel.com>
> ---
> resending as v6 appears to have fallen though the cracks.  Russell?

Please put it in the patch system (otherwise I do drop patches.)


From linux at arm.linux.org.uk  Thu May 23 19:15:31 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 00:15:31 +0100
Subject: [PATCH] ARM: avoid mis-detecting some V7 cores in the decompressor
In-Reply-To: <519E57D2.3050000@codeaurora.org>
References: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
 <5193E424.9090605@codeaurora.org> <519E57D2.3050000@codeaurora.org>
Message-ID: <20130523231531.GT18614@n2100.arm.linux.org.uk>

On Thu, May 23, 2013 at 10:54:26AM -0700, Stephen Boyd wrote:
> On 05/15/13 12:38, Stephen Boyd wrote:
> > On 05/08/13 14:47, Stephen Boyd wrote:
> >> From: Brian Swetland <swetland at google.com>
> >>
> >> Currently v7 CPUs with an MIDR that has no bits set in the range
> >> [16:12] will be detected as old ARM CPUs with no caches and so
> >> the cache will never be turned on during decompression. ARM's
> >> Cortex chips have an 0xC in the range [16:12] so they never match
> >> this entry, but Qualcomm's Scorpion and Krait processors never
> >> set these bits to anything besides 0 so they always match.
> >>
> >> Skip this entry if we've compiled in support for v7 CPUs. This
> >> allows kernel decompression to happen nearly instantly instead of
> >> taking over 20 seconds.
> >>
> >> Signed-off-by: Brian Swetland <swetland at google.com>
> >> [sboyd: Clarified and extended commit text]
> >> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> >> ---
> > Ping?
> 
> Russell, shall I add this to the patch tracker?

Yes please.



From thomas.petazzoni at free-electrons.com  Thu May 23 19:17:24 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 01:17:24 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523230911.GR18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523142301.10dbeff9@skate>
 <20130523202643.GQ18614@n2100.arm.linux.org.uk>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
Message-ID: <20130524011724.515eac91@skate>

Russell,

On Fri, 24 May 2013 00:09:11 +0100, Russell King - ARM Linux wrote:

> No, I'm not asking about the principle.  I'm asking _in this particular
> problem case_ who provides the DT blob?
> 
> So the person to answer that question is Thomas or someone who is using
> the boards concerned.

The DTB is built from arch/arm/boot/dts/, together with the kernel
image itself. As far as I'm aware of, there is for the moment no plan
to "burn" the DTB on the board and therefore make the Device Tree
really separated from the kernel.

Does that answer your question? If not, do not hesitate to ask for
further details.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linux at arm.linux.org.uk  Thu May 23 19:40:24 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 00:40:24 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <20130524011724.515eac91@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523142301.10dbeff9@skate>
 <20130523202643.GQ18614@n2100.arm.linux.org.uk>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
 <20130524011724.515eac91@skate>
Message-ID: <20130523234024.GU18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 01:17:24AM +0200, Thomas Petazzoni wrote:
> Russell,
> 
> On Fri, 24 May 2013 00:09:11 +0100, Russell King - ARM Linux wrote:
> 
> > No, I'm not asking about the principle.  I'm asking _in this particular
> > problem case_ who provides the DT blob?
> > 
> > So the person to answer that question is Thomas or someone who is using
> > the boards concerned.
> 
> The DTB is built from arch/arm/boot/dts/, together with the kernel
> image itself. As far as I'm aware of, there is for the moment no plan
> to "burn" the DTB on the board and therefore make the Device Tree
> really separated from the kernel.

Right, so we're still in the position where we aren't dealing with
vendor provided DT blobs... this also means of course that the DT blob
isn't going to get updated by the boot loader depending on where it
decides to set the registers.

I suspect as far as the boot loaders on these boards go, the DT blob is
"just another file" to be loaded into memory by the boot loader, and it
is completely untouched by the boot loader.

Unfortunately, it also means that it's _completely_ our problem to select
the appropriate DT file for the boot loader behaviour, _or_ just not
bother with the problematical devices in DT and stick to "the old way"
of doing this if we can detect where they are.

For the latter, it really is not worth the effort of stuffing the DT file
full of definitions which are either (a) possibly wrong on the hardware
and (b) aren't being used because we're having to override them in the
kernel.

Another solution to this is to document the problem on a website, and
provide two DT blobs, and tell people to try one, if that fails to boot,
try the other, and only if that also fails to ask for help.  Yea, I know,
people don't bother reading websites though, it's loads easier to send
an email to a mailing list or someone else. :P


From festevam at gmail.com  Thu May 23 19:41:48 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 23 May 2013 20:41:48 -0300
Subject: [PATCH] ARM: imx: Enable mx6 solo-lite support
Message-ID: <1369352508-12177-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/imx_v6_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f..88e24ed 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -37,6 +37,7 @@ CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
-- 
1.8.1.2



From 21cnbao at gmail.com  Thu May 23 19:51:50 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 24 May 2013 07:51:50 +0800
Subject: [PATCH] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <AAD401B65941D44692B7183E6577180803A11BF4@banasiexm01.ASIA.ROOT.PRI>
References: <1369239198-11059-1-git-send-email-Baohua.Song@csr.com>
 <AAD401B65941D44692B7183E6577180803A11B7C@banasiexm01.ASIA.ROOT.PRI>
 <CAGsJ_4y6BwTpZpwYv0njvqYtp9Y0UU5qhVJhqG5X+8+Hy_LW8Q@mail.gmail.com>
 <AAD401B65941D44692B7183E6577180803A11BF4@banasiexm01.ASIA.ROOT.PRI>
Message-ID: <CAGsJ_4ytAZLxK6=AKpvpuaiE2ML0tOunG9dofO+HXToYhMUz4Q@mail.gmail.com>

2013/5/24 Madhvapathi Sriram <Madhvapathi.Sriram at csr.com>:
> Agreed Barry. Please ignore my comments on resources management below.
>

Madhvapathi, will you not top post and will you make your mail client
only send raw text without rich text and html? otherwise, your
comments might be looked as noise.

> Best Regards,
> Madhvapathi Sriram
>
-barry


From akpm at linux-foundation.org  Thu May 23 19:55:04 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Thu, 23 May 2013 16:55:04 -0700
Subject: [rtc-linux] [PATCH] rtc: max8998: Check for pdata presence
 before dereferencing
In-Reply-To: <1368630968-30460-1-git-send-email-t.figa@samsung.com>
References: <1368630968-30460-1-git-send-email-t.figa@samsung.com>
Message-ID: <20130523165504.364bebf5f999e4a12d51e176@linux-foundation.org>

On Wed, 15 May 2013 17:16:08 +0200 Tomasz Figa <t.figa at samsung.com> wrote:

> Currently the driver can crash with a NULL pointer dereference if no pdata
> is provided, despite of successful registration of MFD part. This patch
> fixes the problem by adding a NULL check before dereferencing the pdata
> pointer.
> 
> ...
>
> --- a/drivers/rtc/rtc-max8998.c
> +++ b/drivers/rtc/rtc-max8998.c
> @@ -285,7 +285,7 @@ static int max8998_rtc_probe(struct platform_device *pdev)
>  			info->irq, ret);
>  
>  	dev_info(&pdev->dev, "RTC CHIP NAME: %s\n", pdev->id_entry->name);
> -	if (pdata->rtc_delay) {
> +	if (pdata && pdata->rtc_delay) {
>  		info->lp3974_bug_workaround = true;
>  		dev_warn(&pdev->dev, "LP3974 with RTC REGERR option."
>  				" RTC updates will be extremely slow.\n");

Looking at your description I'm unable to determine which kernel
versions we should fix.  This is because the changelog didn't describe
the circumstances under which the bug triggers.

It's pretty simple: when fixing a bug, include a full description of
the bug!  As if you were sending a bug report, not a patch.


From marex at denx.de  Thu May 23 21:00:59 2013
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 May 2013 03:00:59 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <1369322904.4142.36.camel@weser.hi.pengutronix.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <201305231648.17356.marex@denx.de>
 <1369322904.4142.36.camel@weser.hi.pengutronix.de>
Message-ID: <201305240301.00137.marex@denx.de>

Dear Lucas Stach,

> Am Donnerstag, den 23.05.2013, 16:48 +0200 schrieb Marek Vasut:
> > Dear Juergen Beisert,
> > 
> > > Hi Marek,
> > > 
> > > Marek Vasut wrote:
> > > > > > i2c slowness is a different issue.
> > > > > 
> > > > > Same happens here for my i.M23 based platform. It seems the PIO
> > > > > mode does not work, or at least not like it works on a i.MX28.
> > > > > Each short transfer needs about one second (without an error
> > > > > message) but does not send anything on the I2C lines.
> > > > > 
> > > > > I need the following patches to make I2C master work within a
> > > > > 3.10-rc2 kernel:
> > > > > 
> > > > > Subject: [PATCH] I2C/MXS: distinguish i.MX23 and i.MX28 based I2C
> > > > 
> > > > I'm all for it, but then ... won't it be better if you actually fixed
> > > > the PIO and mixed-mode on MX23 instead of implementing such hack?
> > > 
> > > If the PIO mode or my patch is a hack depends on the point of view:
> > > Lucas told me the PIO mode is *mentioned* but *not specified* in the
> > > i.MX23/i.MX28 datasheets.
> > 
> > The PIO works the same way DMA does -- set up bits and then pump data
> > into the DATA register.
> > 
> > > So, the PIO mode seems to depend on some undocumented status bits in
> > > the i.MX28 I2C controller implementation.
> > 
> > How would DMA work then if it used undocumented registers ? It's in the
> > documentation, just read it or ask FSL ;-)
> 
> While the PIO mode might use the same controller mechanisms as the DMA
> mode, PIO mode is _not_ a documented mode of operation for the i.MX23.
> 
> To quote the i.MX28 RM: "The I2C block on the i.MX28 supports a new PIO
> mode or soft-DMA mode.", which implies the PIO mode to be a new mode of
> operation not found on earlier i.MX SoCs.
> The doc is slightly fuzzy here as the i.MX23 RM in contrary states:
> "Short transmission (up to three bytes plus address) can be easily
> triggered using only PIO operations, i.e., no DMA setup required." But
> again it's not a documented mode of operation, i.MX23 doc only describes
> the DMA mode.

I'm CCing a Amaury Pouly so he can comment on this stuff. He did some hardware 
digging.

> So while we _might_ be able to get the PIO mode to work on the i.MX23
> there is nothing in the doc stating that it's even meant to work. Even
> while PIO and DMA mode use the same internal mechanisms, there's still
> plenty of opportunities of fail in there. After all PIO mode relies on
> reading a debug register in the course of normal operation.

What's the problem with that ? The debug register contains status bits.

> Only more extensive experimentation could show if we are in fact able to
> make it work, a first shot of using PIO mode on MX23 failed, so it might
> as well be that Juergens quick fix is correct and we have to disable PIO
> mode on MX23 altogether. That said please stop slapping the word "hack"
> over this patch until proven otherwise.
> 
> Regards,
> Lucas

Best regards,
Marek Vasut


From jg1.han at samsung.com  Thu May 23 21:11:46 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Fri, 24 May 2013 10:11:46 +0900
Subject: [PATCH] clk: use platform_{get,set}_drvdata()
Message-ID: <000401ce581b$a9224600$fb66d200$@samsung.com>

Use the wrapper functions for getting and setting the driver data using
platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev,
so we can directly pass a struct platform_device.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
 drivers/clk/clk-twl6040.c |    4 ++--
 drivers/clk/clk-wm831x.c  |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c
index 3af729b..1ada79a 100644
--- a/drivers/clk/clk-twl6040.c
+++ b/drivers/clk/clk-twl6040.c
@@ -95,14 +95,14 @@ static int twl6040_clk_probe(struct platform_device *pdev)
 	if (IS_ERR(clkdata->clk))
 		return PTR_ERR(clkdata->clk);
 
-	dev_set_drvdata(&pdev->dev, clkdata);
+	platform_set_drvdata(pdev, clkdata);
 
 	return 0;
 }
 
 static int twl6040_clk_remove(struct platform_device *pdev)
 {
-	struct twl6040_clk *clkdata = dev_get_drvdata(&pdev->dev);
+	struct twl6040_clk *clkdata = platform_get_drvdata(pdev);
 
 	clk_unregister(clkdata->clk);
 
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 16ed068..0d3c04e 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -384,7 +384,7 @@ static int wm831x_clk_probe(struct platform_device *pdev)
 	if (IS_ERR(clkdata->clkout))
 		return PTR_ERR(clkdata->clkout);
 
-	dev_set_drvdata(&pdev->dev, clkdata);
+	platform_set_drvdata(pdev, clkdata);
 
 	return 0;
 }
-- 
1.7.10.4




From jh80.chung at samsung.com  Thu May 23 21:47:41 2013
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Fri, 24 May 2013 10:47:41 +0900
Subject: [PATCHv3 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1369345002-20002-6-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
 <1369345002-20002-6-git-send-email-dinguyen@altera.com>
Message-ID: <519EC6BD.3080202@samsung.com>

On 05/24/2013 06:36 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Seungwon Jeon <tgih.jun at samsung.com>
> CC: Jaehoon Chung <jh80.chung at samsung.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: linux-mmc at vger.kernel.org
> 
> v3:
> - Addressed comments from Seugwon, Jaehoon, and Pavel
> - Use clk_disable_unprepare/clk_prepare_enable
> 
> v2:
> - Use syscon and regmap
> - Avoid divide by zero
> - Remove the need to set PWR_EN
> ---
>  drivers/mmc/host/Kconfig          |    8 +++
>  drivers/mmc/host/Makefile         |    1 +
>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>  drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
>  drivers/mmc/host/dw_mmc.h         |    1 +
>  5 files changed, 149 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 9ab8f8d..1be2289 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>  
> +config MMC_DW_SOCFPGA
> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
> +	depends on MMC_DW
> +	select MMC_DW_PLTFM
> +	help
> +	  This selects support for Altera SoCFPGA specific extensions to the
> +	  Synopsys DesignWare Memory Card Interface driver.
> +
>  config MMC_DW_PCI
>  	tristate "Synopsys Designware MCI support on PCI bus"
>  	depends on MMC_DW && PCI
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index cd32280..67718c1 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index f013e7e..866edef 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -31,8 +31,6 @@
>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
>  
> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
> -
>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
>  
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> new file mode 100644
> index 0000000..3cc1afc
> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> @@ -0,0 +1,139 @@
> +/*
> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
> + *
> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> + *  Copyright (C) 2013 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Taken from dw_mmc-exynos.c
> + */
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/dw_mmc.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "dw_mmc.h"
> +#include "dw_mmc-pltfm.h"
> +
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
> +	((((smplsel) & 0x38) << 3) | (((drvsel) & 0x7) << 0))
Is it right? 0x38 is already shifted..
(((smplsel & 0x7) << 3) | ((drvsel & 0x7) << 0))
isn't?

Best Regards,
Jaehoon Chung
> +
> +/* SOCFPGA implementation specific driver private data */
> +struct dw_mci_socfpga_priv_data {
> +	u8	ciu_div; /* card interface unit divisor */
> +	u32	hs_timing; /* bitmask for CIU clock phase shift */
> +	struct regmap   *sysreg; /* regmap for system manager register */
> +};
> +
> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv;
> +
> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv) {
> +		dev_err(host->dev, "mem alloc failed for private data\n");
> +		return -ENOMEM;
> +	}
> +
> +	host->priv = priv;
> +
> +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +	if (IS_ERR(priv->sysreg)) {
> +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> +		return PTR_ERR(priv->sysreg);
> +	}
> +
> +	return 0;
> +}
> +
> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	clk_disable_unprepare(host->ciu_clk);
> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
> +	clk_prepare_enable(host->ciu_clk);
> +
> +	host->bus_hz /= (priv->ciu_div + 1);
> +	return 0;
> +}
> +
> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
> +}
> +
> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +	struct device_node *np = host->dev->of_node;
> +	u32 timing[2];
> +	u32 div = 0;
> +	int ret;
> +
> +	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> +	if (ret)
> +		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
> +	priv->ciu_div = div;
> +
> +	ret = of_property_read_u32_array(np,
> +			"altr,dw-mshc-sdr-timing", timing, 2);
> +	if (ret)
> +		return ret;
> +
> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> +	return 0;
> +}
> +
> +static const struct dw_mci_drv_data socfpga_drv_data = {
> +	.init			= dw_mci_socfpga_priv_init,
> +	.setup_clock		= dw_mci_socfpga_setup_clock,
> +	.prepare_command	= dw_mci_socfpga_prepare_command,
> +	.parse_dt		= dw_mci_socfpga_parse_dt,
> +};
> +
> +static const struct of_device_id dw_mci_socfpga_match[] = {
> +	{ .compatible = "altr,socfpga-dw-mshc",
> +			.data = &socfpga_drv_data, },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
> +
> +int dw_mci_socfpga_probe(struct platform_device *pdev)
> +{
> +	const struct dw_mci_drv_data *drv_data;
> +	const struct of_device_id *match;
> +
> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
> +	drv_data = match->data;
> +	return dw_mci_pltfm_register(pdev, drv_data);
> +}
> +
> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
> +	.probe		= dw_mci_socfpga_probe,
> +	.remove		= __exit_p(dw_mci_pltfm_remove),
> +	.driver		= {
> +		.name		= "dwmmc_socfpga",
> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
> +		.pm		= &dw_mci_pltfm_pmops,
> +	},
> +};
> +
> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
> +
> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:dwmmc-socfpga");
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 0b74189..3700cb2 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -111,6 +111,7 @@
>  #define SDMMC_INT_ERROR			0xbfc2
>  /* Command register defines */
>  #define SDMMC_CMD_START			BIT(31)
> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>  #define SDMMC_CMD_UPD_CLK		BIT(21)
> 



From dinh.linux at gmail.com  Thu May 23 21:59:41 2013
From: dinh.linux at gmail.com (Dinh Nguyen)
Date: Thu, 23 May 2013 20:59:41 -0500
Subject: [PATCHv3 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <519EC6BD.3080202@samsung.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
 <1369345002-20002-6-git-send-email-dinguyen@altera.com>
 <519EC6BD.3080202@samsung.com>
Message-ID: <519EC98D.5070707@gmail.com>

Hi Jaehoon,

On 05/23/2013 08:47 PM, Jaehoon Chung wrote:
> On 05/24/2013 06:36 AM, dinguyen at altera.com wrote:
>> From: Dinh Nguyen <dinguyen at altera.com>
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>> can use this define.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
>> CC: Seungwon Jeon <tgih.jun at samsung.com>
>> CC: Jaehoon Chung <jh80.chung at samsung.com>
>> CC: Arnd Bergmann <arnd at arndb.de>
>> CC: Olof Johansson <olof at lixom.net>
>> CC: Pavel Machek <pavel at denx.de>
>> CC: linux-mmc at vger.kernel.org
>>
>> v3:
>> - Addressed comments from Seugwon, Jaehoon, and Pavel
>> - Use clk_disable_unprepare/clk_prepare_enable
>>
>> v2:
>> - Use syscon and regmap
>> - Avoid divide by zero
>> - Remove the need to set PWR_EN
>> ---
>>  drivers/mmc/host/Kconfig          |    8 +++
>>  drivers/mmc/host/Makefile         |    1 +
>>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>>  drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
>>  drivers/mmc/host/dw_mmc.h         |    1 +
>>  5 files changed, 149 insertions(+), 2 deletions(-)
>>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
>>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 9ab8f8d..1be2289 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>>  
>> +config MMC_DW_SOCFPGA
>> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
>> +	depends on MMC_DW
>> +	select MMC_DW_PLTFM
>> +	help
>> +	  This selects support for Altera SoCFPGA specific extensions to the
>> +	  Synopsys DesignWare Memory Card Interface driver.
>> +
>>  config MMC_DW_PCI
>>  	tristate "Synopsys Designware MCI support on PCI bus"
>>  	depends on MMC_DW && PCI
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index cd32280..67718c1 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
>> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index f013e7e..866edef 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -31,8 +31,6 @@
>>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
>>  
>> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
>> -
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
>>  
>> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
>> new file mode 100644
>> index 0000000..3cc1afc
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> @@ -0,0 +1,139 @@
>> +/*
>> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
>> + *
>> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
>> + *  Copyright (C) 2013 Altera Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Taken from dw_mmc-exynos.c
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/mmc/host.h>
>> +#include <linux/mmc/dw_mmc.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include "dw_mmc.h"
>> +#include "dw_mmc-pltfm.h"
>> +
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
>> +	((((smplsel) & 0x38) << 3) | (((drvsel) & 0x7) << 0))
> Is it right? 0x38 is already shifted..
> (((smplsel & 0x7) << 3) | ((drvsel & 0x7) << 0))
> isn't?

Yes, you're right! Will fix..

thanks,
Dinh
> 
> Best Regards,
> Jaehoon Chung
>> +
>> +/* SOCFPGA implementation specific driver private data */
>> +struct dw_mci_socfpga_priv_data {
>> +	u8	ciu_div; /* card interface unit divisor */
>> +	u32	hs_timing; /* bitmask for CIU clock phase shift */
>> +	struct regmap   *sysreg; /* regmap for system manager register */
>> +};
>> +
>> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv;
>> +
>> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> +	if (!priv) {
>> +		dev_err(host->dev, "mem alloc failed for private data\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	host->priv = priv;
>> +
>> +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> +	if (IS_ERR(priv->sysreg)) {
>> +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
>> +		return PTR_ERR(priv->sysreg);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	clk_disable_unprepare(host->ciu_clk);
>> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
>> +	clk_prepare_enable(host->ciu_clk);
>> +
>> +	host->bus_hz /= (priv->ciu_div + 1);
>> +	return 0;
>> +}
>> +
>> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +
>> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
>> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> +}
>> +
>> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> +{
>> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
>> +	struct device_node *np = host->dev->of_node;
>> +	u32 timing[2];
>> +	u32 div = 0;
>> +	int ret;
>> +
>> +	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
>> +	if (ret)
>> +		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
>> +	priv->ciu_div = div;
>> +
>> +	ret = of_property_read_u32_array(np,
>> +			"altr,dw-mshc-sdr-timing", timing, 2);
>> +	if (ret)
>> +		return ret;
>> +
>> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
>> +	return 0;
>> +}
>> +
>> +static const struct dw_mci_drv_data socfpga_drv_data = {
>> +	.init			= dw_mci_socfpga_priv_init,
>> +	.setup_clock		= dw_mci_socfpga_setup_clock,
>> +	.prepare_command	= dw_mci_socfpga_prepare_command,
>> +	.parse_dt		= dw_mci_socfpga_parse_dt,
>> +};
>> +
>> +static const struct of_device_id dw_mci_socfpga_match[] = {
>> +	{ .compatible = "altr,socfpga-dw-mshc",
>> +			.data = &socfpga_drv_data, },
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
>> +
>> +int dw_mci_socfpga_probe(struct platform_device *pdev)
>> +{
>> +	const struct dw_mci_drv_data *drv_data;
>> +	const struct of_device_id *match;
>> +
>> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
>> +	drv_data = match->data;
>> +	return dw_mci_pltfm_register(pdev, drv_data);
>> +}
>> +
>> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
>> +	.probe		= dw_mci_socfpga_probe,
>> +	.remove		= __exit_p(dw_mci_pltfm_remove),
>> +	.driver		= {
>> +		.name		= "dwmmc_socfpga",
>> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
>> +		.pm		= &dw_mci_pltfm_pmops,
>> +	},
>> +};
>> +
>> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
>> +
>> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:dwmmc-socfpga");
>> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
>> index 0b74189..3700cb2 100644
>> --- a/drivers/mmc/host/dw_mmc.h
>> +++ b/drivers/mmc/host/dw_mmc.h
>> @@ -111,6 +111,7 @@
>>  #define SDMMC_INT_ERROR			0xbfc2
>>  /* Command register defines */
>>  #define SDMMC_CMD_START			BIT(31)
>> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>>  #define SDMMC_CMD_UPD_CLK		BIT(21)
>>
> 


From horms+renesas at verge.net.au  Thu May 23 22:06:24 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Fri, 24 May 2013 11:06:24 +0900
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
Message-ID: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>

Add SATA clock for r8a7790 SoC (for both device tree and usual cases).
Register SATA controller as a "late" platform device on r8a7790 SoC.

Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
Vladimir Barinov.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c |  4 ++++
 arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index b393592..3619a52 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -50,6 +50,7 @@
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
 
 #define MODEMR		0xE6160060
 #define SDCKCR		0xE6150074
@@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+	MSTP814,
 	MSTP721, MSTP720,
 	MSTP304,
 	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@@ -187,6 +189,7 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP814] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 15, 0), /* SATA1 */
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
 	[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
@@ -249,6 +252,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
 	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
 	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
+	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index ed7ee24..5a2a073 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
@@ -118,6 +119,25 @@ static inline void r8a7790_register_scif(int idx)
 				      sizeof(struct plat_sci_port));
 }
 
+static __init void r8a7790_register_sata1(void)
+{
+
+	struct resource res[] = {
+		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),
+		DEFINE_RES_IRQ(gic_iid(106)),
+	};
+
+	struct platform_device_info pdevinfo = {
+		.name = "sata_rcar",
+		.id = 1,
+		.res = res,
+		.num_res = ARRAY_SIZE(res),
+		.dma_mask = DMA_BIT_MASK(32),
+	};
+
+	platform_device_register_full(&pdevinfo);
+}
+
 static struct renesas_irqc_config irqc0_data = {
 	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 };
@@ -148,6 +168,7 @@ void __init r8a7790_add_standard_devices(void)
 	r8a7790_register_scif(SCIF0);
 	r8a7790_register_scif(SCIF1);
 	r8a7790_register_irqc(0);
+	r8a7790_register_sata1();
 }
 
 void __init r8a7790_timer_init(void)
-- 
1.8.2.1



From gang.chen at asianux.com  Thu May 23 22:13:35 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Fri, 24 May 2013 10:13:35 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <CAMuHMdUzcBuDupe4Fa6XieziGPMpPKC_k8X8gUUmDvLJ+Fe=Hg@mail.gmail.com>
References: <519DCBEF.3090208@asianux.com> <201305231259.43750.arnd@arndb.de>
 <20130523112401.GO18614@n2100.arm.linux.org.uk>
 <201305231409.02359.arnd@arndb.de>
 <20130523125033.GP18614@n2100.arm.linux.org.uk>
 <CAMuHMdUzcBuDupe4Fa6XieziGPMpPKC_k8X8gUUmDvLJ+Fe=Hg@mail.gmail.com>
Message-ID: <519ECCCF.8090909@asianux.com>

On 05/23/2013 10:10 PM, Geert Uytterhoeven wrote:
> On Thu, May 23, 2013 at 2:50 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
>> > On Thu, May 23, 2013 at 02:09:02PM +0200, Arnd Bergmann wrote:
>>> >> On Thursday 23 May 2013, Russell King - ARM Linux wrote:
>>>> >> > This is the problem you guys are missing - unreachable() means "we lose
>>>> >> > control of the CPU at this point".
>>> >>
>>> >> I'm absolutely aware of this. Again, the current behaviour of doing nothing
>>> >> at all isn't very different from undefined behavior when you get when you
>>> >> get to the end of a function returning a pointer without a "return" statement,
>>> >> or when you return from a function that has determined that it is not safe
>>> >> to continue.
>> >
>> > Running off the end of a function like that is a different kettle of fish.
>> > The execution path is still as the compiler intends - what isn't is that
>> > the data returned is likely to be random trash.
>> >
>> > That's _quite_ different from the CPU starting to execute the contents
>> > of a literal data pool.
> I agree it's best to e.g. trap and reboot.

After read the arch/*/include/asm/bug.h,

It seems panic() is not suitable for NOMMU platforms (only m68k use it,
also need CONFIG_BUG and CONFIG_SUN3 enabled).

And unreachable() is need followed with an asm inline instruction (arm,
x86, powerpc mips...).

And __builtin_trap() is "the mechanism used may vary from release to
release so should not rely on any particular implementation" (ref to
"http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html", used by m68k,
sparc, ia64).

I can not find any *trap*() and *unreachable*() in "include/asm-generic/"

I can not find any suitable implementation which 'generic' enough to add
in "include/asm-generic/" (and in fact, CONFIG_BUG itself is not
'generic' enough to be in "include/asm-generic/").


At last, I still suggest to delete CONFIG_BUG, so most of architectures
can skip this issue firstly.

Then for specific architectures, also can get 3 benefits:

a. the related maintainers can implement it as their own willing (not
need discus it with another platform maintainers again);

b. the related maintainers can free use the platform specific features
(which can not be used in "include/asm-generic/");

c. the related maintainers are more familiar their own architectures
demands and requirements.



----------- arch/m68k/include/asm/bug.h --------------------------------

  1 #ifndef _M68K_BUG_H
  2 #define _M68K_BUG_H
  3
  4 #ifdef CONFIG_MMU
  5 #ifdef CONFIG_BUG
  6 #ifdef CONFIG_DEBUG_BUGVERBOSE
  7 #ifndef CONFIG_SUN3
  8 #define BUG() do { \
  9         printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
 10         __builtin_trap(); \
 11 } while (0)
 12 #else
 13 #define BUG() do { \
 14         printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
 15         panic("BUG!"); \
 16 } while (0)
 17 #endif
 18 #else
 19 #define BUG() do { \
 20         __builtin_trap(); \
 21 } while (0)
 22 #endif
 23
 24 #define HAVE_ARCH_BUG
 25 #endif
 26 #endif /* CONFIG_MMU */
 27
 28 #include <asm-generic/bug.h>
 29
 30 #endif




Thanks.
-- 
Chen Gang

Asianux Corporation


From kuninori.morimoto.gx at renesas.com  Thu May 23 22:17:22 2013
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Thu, 23 May 2013 19:17:22 -0700 (PDT)
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>


Hi Simon

> Add SATA clock for r8a7790 SoC (for both device tree and usual cases).
> Register SATA controller as a "late" platform device on r8a7790 SoC.
> 
> Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
> Vladimir Barinov.
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---

> +	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
(snip)
> +static __init void r8a7790_register_sata1(void)
> +{
> +
> +	struct resource res[] = {
> +		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),
> +		DEFINE_RES_IRQ(gic_iid(106)),
> +	};
> +
> +	struct platform_device_info pdevinfo = {
> +		.name = "sata_rcar",
> +		.id = 1,
> +		.res = res,
> +		.num_res = ARRAY_SIZE(res),
> +		.dma_mask = DMA_BIT_MASK(32),
> +	};
> +
> +	platform_device_register_full(&pdevinfo);
> +}

This is a little bit strange for me.
Why you don't care SATA0 ?

Can you use like this ?

static __init void r8a7790_register_sata(int id);


BTW, we need to decide "driver registration function naming" ?
In r8a7778 case, it is using 

	r8a7778_add_xxx_device()
	r8a7778_add_xxx_devices()

but r8a7778_register_xxx seems nice naming :)

Best regards
---
Kuninori Morimoto


From kuninori.morimoto.gx at renesas.com  Thu May 23 22:21:17 2013
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Thu, 23 May 2013 19:21:17 -0700 (PDT)
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <877gip2k4l.wl%kuninori.morimoto.gx@renesas.com>


Hi Simon

> > +static __init void r8a7790_register_sata1(void)
> > +{
> > +
> > +	struct resource res[] = {
> > +		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),
> > +		DEFINE_RES_IRQ(gic_iid(106)),
> > +	};
> > +
> > +	struct platform_device_info pdevinfo = {
> > +		.name = "sata_rcar",
> > +		.id = 1,
> > +		.res = res,
> > +		.num_res = ARRAY_SIZE(res),
> > +		.dma_mask = DMA_BIT_MASK(32),
> > +	};
> > +
> > +	platform_device_register_full(&pdevinfo);
> > +}

This "using local variable" make sense.
It don't need "__initdata"


Best regards
---
Kuninori Morimoto


From b32955 at freescale.com  Thu May 23 22:41:53 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 10:41:53 +0800
Subject: [PATCH V2 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
In-Reply-To: <1369302906.444557883@f310.mail.ru>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369301996.738631947@f310.mail.ru> <519DE6D0.2040909@freescale.com>
 <1369302906.444557883@f310.mail.ru>
Message-ID: <519ED371.4060703@freescale.com>

? 2013?05?23? 17:55, Alexander Shiyan ??:
>>> How we should define CS1 pin in your example for second device?
>> But in the imx6q{dl}-sabreauto boards, we only have the NOR connected to
>> WEIM.
>> I do not need to worry about the second device.
> OK, but you add "weim-NOR" to the arch/arm/boot/dts/imx6q.dtsi, not
> in imx6qdl-sabreauto.dtsi, so you mean that this definition is generic.
> Should it be moved to imx6qdl-sabreauto.dtsi then?
okay. I will split out the CS pad to single pinctrl.

thanks for your review.

Huang Shijie



From b32955 at freescale.com  Thu May 23 22:42:53 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 10:42:53 +0800
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <20130523101921.GM18614@n2100.arm.linux.org.uk>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <1369296978-7669-2-git-send-email-b32955@freescale.com>
 <20130523101921.GM18614@n2100.arm.linux.org.uk>
Message-ID: <519ED3AD.6040403@freescale.com>

? 2013?05?23? 18:19, Russell King - ARM Linux ??:
> On Thu, May 23, 2013 at 04:16:13PM +0800, Huang Shijie wrote:
>> +	/* get the clock */
>> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
>> +	if (IS_ERR(weim->clk))
>> +		goto weim_err;
>> +
>> +	clk_prepare_enable(weim->clk);
> I notice people are getting lazy about this.  clk_prepare_enable() can
> return an error...
>
i will add the error check in next version.

thanks
Huang Shijie



From dhobsong at igel.co.jp  Thu May 23 22:52:22 2013
From: dhobsong at igel.co.jp (Damian Hobson-Garcia)
Date: Fri, 24 May 2013 11:52:22 +0900
Subject: [PATCH v2 0/4] dma-mapping: Define dma_{alloc,free}_attrs() for
 all archs
In-Reply-To: <20130523094709.GB16722@arm.com>
References: <1367290899-10410-1-git-send-email-dhobsong@igel.co.jp>
 <519C2F5D.8000809@igel.co.jp> <20130522094741.GE14322@arm.com>
 <519D8331.3060203@igel.co.jp> <20130523094709.GB16722@arm.com>
Message-ID: <519ED5E6.7040506@igel.co.jp>

On 2013/05/23 18:47, Catalin Marinas wrote:
> On Thu, May 23, 2013 at 03:47:13AM +0100, Damian Hobson-Garcia wrote:
>> Hi Catalin,
>> On 2013/05/22 18:47, Catalin Marinas wrote:
>>> On Wed, May 22, 2013 at 03:37:17AM +0100, Damian Hobson-Garcia wrote:
>>>> Hello,
>>>> On 2013/04/30 12:01, Damian Hobson-Garcia wrote:
>>>>> Most architectures that define CONFIG_HAVE_DMA=y, have implementations for
>>>>> both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
>>>>> not define CONFIG_HAVE_DMA also have both of these definitions provided by
>>>>> dma-mapping-broken.h.
>>>
>>> BTW, shouldn't this be called CONFIG_HAVE_DMA_ATTRS?
>>
>> CONFIG_HAVE_DMA_ATTRS is currently used to enable the functions to
>> set/get the DMA attribute values. Poking through the headers, it looks
>> like the struct dma_attrs is defined regardless of the
>> CONFIG_HAVE_DMA_ATTRS setting, so in that respect
>> we always seem to "have" DMA attributes (if we have DMA), but they may
>> not always be meaningful (ie. set to some value).
> 
> My point was about the commit log - grep'ing the kernel for
> CONFIG_HAVE_DMA did not return anything.
> 

Oh yes, my mistake.  It should be CONFIG_HAS_DMA instead of
CONFIG_HAVE_DMA.  I'll update it.

Damian


-- 
Damian Hobson-Garcia
IGEL Co.,Ltd
http://www.igel.co.jp


From horms at verge.net.au  Thu May 23 22:59:44 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 24 May 2013 11:59:44 +0900
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <20130524025940.GA10536@verge.net.au>

On Thu, May 23, 2013 at 07:17:22PM -0700, Kuninori Morimoto wrote:
> 
> Hi Simon
> 
> > Add SATA clock for r8a7790 SoC (for both device tree and usual cases).
> > Register SATA controller as a "late" platform device on r8a7790 SoC.
> > 
> > Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
> > Vladimir Barinov.
> > 
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > ---
> 
> > +	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
> (snip)
> > +static __init void r8a7790_register_sata1(void)
> > +{
> > +
> > +	struct resource res[] = {
> > +		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),
> > +		DEFINE_RES_IRQ(gic_iid(106)),
> > +	};
> > +
> > +	struct platform_device_info pdevinfo = {
> > +		.name = "sata_rcar",
> > +		.id = 1,
> > +		.res = res,
> > +		.num_res = ARRAY_SIZE(res),
> > +		.dma_mask = DMA_BIT_MASK(32),
> > +	};
> > +
> > +	platform_device_register_full(&pdevinfo);
> > +}
> 
> This is a little bit strange for me.
> Why you don't care SATA0 ?

Because the lager board only seems to expose SATA1 and I was
interested in something I could test.

I am happy to start caring about SATA0 if you think it is
a good idea.

> Can you use like this ?
> 
> static __init void r8a7790_register_sata(int id);

Sure, but I'm unsure how you want r8a7790_register_sata to handle id.

Is it just for the id field of struct platform_device_info pdevinfo?
Or also to switch between resources somehow?

> BTW, we need to decide "driver registration function naming" ?
> In r8a7778 case, it is using 
> 
> 	r8a7778_add_xxx_device()
> 	r8a7778_add_xxx_devices()
> 
> but r8a7778_register_xxx seems nice naming :)

I chose register as it seemed to be consistent with the
existing contents of r8a7790_add_standard_devices().


From kuninori.morimoto.gx at renesas.com  Thu May 23 23:11:05 2013
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Thu, 23 May 2013 20:11:05 -0700 (PDT)
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <20130524025940.GA10536@verge.net.au>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>
 <20130524025940.GA10536@verge.net.au>
Message-ID: <8761y92htl.wl%kuninori.morimoto.gx@renesas.com>


Hi Simon

> Because the lager board only seems to expose SATA1 and I was
> interested in something I could test.
> 
> I am happy to start caring about SATA0 if you think it is
> a good idea.

Caring both SATA0/1 are nice IMO :)

> > Can you use like this ?
> > 
> > static __init void r8a7790_register_sata(int id);
> 
> Sure, but I'm unsure how you want r8a7790_register_sata to handle id.
> 
> Is it just for the id field of struct platform_device_info pdevinfo?
> Or also to switch between resources somehow?

can you check r8a7778_sdhi_init(int id, xxx) ?
It is caring both id field and resources.

> > BTW, we need to decide "driver registration function naming" ?
> > In r8a7778 case, it is using 
> > 
> > 	r8a7778_add_xxx_device()
> > 	r8a7778_add_xxx_devices()
> > 
> > but r8a7778_register_xxx seems nice naming :)
> 
> I chose register as it seemed to be consistent with the
> existing contents of r8a7790_add_standard_devices().

OK, nice.

Do you think other chip (= r8a7778) should follow same naming?


Best regards
---
Kuninori Morimoto


From horms at verge.net.au  Thu May 23 23:44:20 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 24 May 2013 12:44:20 +0900
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <8761y92htl.wl%kuninori.morimoto.gx@renesas.com>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <878v352kb4.wl%kuninori.morimoto.gx@renesas.com>
 <20130524025940.GA10536@verge.net.au>
 <8761y92htl.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <20130524034418.GG10536@verge.net.au>

On Thu, May 23, 2013 at 08:11:05PM -0700, Kuninori Morimoto wrote:
> 
> Hi Simon
> 
> > Because the lager board only seems to expose SATA1 and I was
> > interested in something I could test.
> > 
> > I am happy to start caring about SATA0 if you think it is
> > a good idea.
> 
> Caring both SATA0/1 are nice IMO :)
> 
> > > Can you use like this ?
> > > 
> > > static __init void r8a7790_register_sata(int id);
> > 
> > Sure, but I'm unsure how you want r8a7790_register_sata to handle id.
> > 
> > Is it just for the id field of struct platform_device_info pdevinfo?
> > Or also to switch between resources somehow?
> 
> can you check r8a7778_sdhi_init(int id, xxx) ?
> It is caring both id field and resources.

Thanks, I will look at that.

> > > BTW, we need to decide "driver registration function naming" ?
> > > In r8a7778 case, it is using 
> > > 
> > > 	r8a7778_add_xxx_device()
> > > 	r8a7778_add_xxx_devices()
> > > 
> > > but r8a7778_register_xxx seems nice naming :)
> > 
> > I chose register as it seemed to be consistent with the
> > existing contents of r8a7790_add_standard_devices().
> 
> OK, nice.
> 
> Do you think other chip (= r8a7778) should follow same naming?

I think it is not so important.


From tgih.jun at samsung.com  Fri May 24 00:07:58 2013
From: tgih.jun at samsung.com (Seungwon Jeon)
Date: Fri, 24 May 2013 13:07:58 +0900
Subject: [PATCHv3 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1369345002-20002-6-git-send-email-dinguyen@altera.com>
References: <1369345002-20002-1-git-send-email-dinguyen@altera.com>
 <1369345002-20002-6-git-send-email-dinguyen@altera.com>
Message-ID: <001301ce5834$46f491e0$d4ddb5a0$%jun@samsung.com>

Just one minor comment below.

On 05/24/13, 6:37 AM, Dinh Nguyen wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> CC: Seungwon Jeon <tgih.jun at samsung.com>
> CC: Jaehoon Chung <jh80.chung at samsung.com>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> CC: Pavel Machek <pavel at denx.de>
> CC: linux-mmc at vger.kernel.org
> 
> v3:
> - Addressed comments from Seugwon, Jaehoon, and Pavel
> - Use clk_disable_unprepare/clk_prepare_enable
> 
> v2:
> - Use syscon and regmap
> - Avoid divide by zero
> - Remove the need to set PWR_EN
> ---
>  drivers/mmc/host/Kconfig          |    8 +++
>  drivers/mmc/host/Makefile         |    1 +
>  drivers/mmc/host/dw_mmc-exynos.c  |    2 -
>  drivers/mmc/host/dw_mmc-socfpga.c |  139 +++++++++++++++++++++++++++++++++++++
>  drivers/mmc/host/dw_mmc.h         |    1 +
>  5 files changed, 149 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 9ab8f8d..1be2289 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>  	  for platforms based on Exynos4 and Exynos5 SoC's.
> 
> +config MMC_DW_SOCFPGA
> +	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
> +	depends on MMC_DW
> +	select MMC_DW_PLTFM
> +	help
> +	  This selects support for Altera SoCFPGA specific extensions to the
> +	  Synopsys DesignWare Memory Card Interface driver.
> +
>  config MMC_DW_PCI
>  	tristate "Synopsys Designware MCI support on PCI bus"
>  	depends on MMC_DW && PCI
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index cd32280..67718c1 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
> +obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index f013e7e..866edef 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -31,8 +31,6 @@
>  					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
>  					SDMMC_CLKSEL_CCLK_DIVIDER(z))
> 
> -#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
> -
>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
> 
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> new file mode 100644
> index 0000000..3cc1afc
> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> @@ -0,0 +1,139 @@
> +/*
> + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
> + *
> + *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> + *  Copyright (C) 2013 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Taken from dw_mmc-exynos.c
> + */
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/dw_mmc.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "dw_mmc.h"
> +#include "dw_mmc-pltfm.h"
> +
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
> +	((((smplsel) & 0x38) << 3) | (((drvsel) & 0x7) << 0))
> +
> +/* SOCFPGA implementation specific driver private data */
> +struct dw_mci_socfpga_priv_data {
> +	u8	ciu_div; /* card interface unit divisor */
> +	u32	hs_timing; /* bitmask for CIU clock phase shift */
> +	struct regmap   *sysreg; /* regmap for system manager register */
> +};
> +
> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv;
> +
> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv) {
> +		dev_err(host->dev, "mem alloc failed for private data\n");
> +		return -ENOMEM;
> +	}
> +
> +	host->priv = priv;
> +
> +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +	if (IS_ERR(priv->sysreg)) {
> +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> +		return PTR_ERR(priv->sysreg);
> +	}
'host->priv = priv;' is expected here after all is done with success.

Thanks,
Seungwon Jeon

> +
> +	return 0;
> +}
> +
> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	clk_disable_unprepare(host->ciu_clk);
> +	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
> +	clk_prepare_enable(host->ciu_clk);
> +
> +	host->bus_hz /= (priv->ciu_div + 1);
> +	return 0;
> +}
> +
> +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> +	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
> +		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
> +}
> +
> +static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> +{
> +	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +	struct device_node *np = host->dev->of_node;
> +	u32 timing[2];
> +	u32 div = 0;
> +	int ret;
> +
> +	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> +	if (ret)
> +		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
> +	priv->ciu_div = div;
> +
> +	ret = of_property_read_u32_array(np,
> +			"altr,dw-mshc-sdr-timing", timing, 2);
> +	if (ret)
> +		return ret;
> +
> +	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> +	return 0;
> +}
> +
> +static const struct dw_mci_drv_data socfpga_drv_data = {
> +	.init			= dw_mci_socfpga_priv_init,
> +	.setup_clock		= dw_mci_socfpga_setup_clock,
> +	.prepare_command	= dw_mci_socfpga_prepare_command,
> +	.parse_dt		= dw_mci_socfpga_parse_dt,
> +};
> +
> +static const struct of_device_id dw_mci_socfpga_match[] = {
> +	{ .compatible = "altr,socfpga-dw-mshc",
> +			.data = &socfpga_drv_data, },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
> +
> +int dw_mci_socfpga_probe(struct platform_device *pdev)
> +{
> +	const struct dw_mci_drv_data *drv_data;
> +	const struct of_device_id *match;
> +
> +	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
> +	drv_data = match->data;
> +	return dw_mci_pltfm_register(pdev, drv_data);
> +}
> +
> +static struct platform_driver dw_mci_socfpga_pltfm_driver = {
> +	.probe		= dw_mci_socfpga_probe,
> +	.remove		= __exit_p(dw_mci_pltfm_remove),
> +	.driver		= {
> +		.name		= "dwmmc_socfpga",
> +		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
> +		.pm		= &dw_mci_pltfm_pmops,
> +	},
> +};
> +
> +module_platform_driver(dw_mci_socfpga_pltfm_driver);
> +
> +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:dwmmc-socfpga");
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 0b74189..3700cb2 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -111,6 +111,7 @@
>  #define SDMMC_INT_ERROR			0xbfc2
>  /* Command register defines */
>  #define SDMMC_CMD_START			BIT(31)
> +#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
>  #define SDMMC_CMD_CCS_EXP		BIT(23)
>  #define SDMMC_CMD_CEATA_RD		BIT(22)
>  #define SDMMC_CMD_UPD_CLK		BIT(21)
> --
> 1.7.9.5
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From shc_work at mail.ru  Fri May 24 00:16:42 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Fri, 24 May 2013 08:16:42 +0400
Subject: =?UTF-8?B?UmVbMl06IFtQQVRDSF0gQVJNOiBkdHM6IGlteDogZml4IGNsb2NrcyBmb3Ig?=
 =?UTF-8?B?Y3NwaQ==?=
In-Reply-To: <20130523173306.GT32299@pengutronix.de>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
 <1369319290.379285076@f398.i.mail.ru>
 <20130523173306.GT32299@pengutronix.de>
Message-ID: <1369369002.837105175@f322.mail.ru>

> > > On Thu, May 23, 2013 at 04:10:59PM +0400, Alexander Shiyan wrote:
> > > > > > The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> > > > > > 
> > > > > > Signed-off-by: Jonas Andersson <jonas at microbit.se>
> > > > > > ---
> > > > > >  arch/arm/boot/dts/imx25.dtsi | 12 ++++++------
> > > > > >  arch/arm/boot/dts/imx27.dtsi |  6 +++---
> > > > > >  arch/arm/boot/dts/imx51.dtsi |  2 +-
> > > > > >  arch/arm/boot/dts/imx53.dtsi |  2 +-
> > > > > >  4 files changed, 11 insertions(+), 11 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> > > > > > index d2550e0..7011539 100644
> > > > > > --- a/arch/arm/boot/dts/imx25.dtsi
> > > > > > +++ b/arch/arm/boot/dts/imx25.dtsi
> > > > > > @@ -141,8 +141,8 @@
> > > > > >  				#size-cells = <0>;
> > > > > >  				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
> > > > > >  				reg = <0x43fa4000 0x4000>;
> > > > > > -				clocks = <&clks 62>;
> > > > > > -				clock-names = "ipg";
> > > > > > +				clocks = <&clks 62>, <&clks 62>;
> > > > > > +				clock-names = "ipg", "per";
> > > > > >  				interrupts = <14>;
> > > > > >  				status = "disabled";
> > > > > >  			};
> > > > 
> > > > Sorry, typo.
> > > > 
> > > > > Why you do not use "dummy" clock for "per" here?
> > > > 
> > > > *for "ipg"
> > > 
> > > Because the same clock is used for the register clock and the baudrate
> > > clock. You have to enable the ipg clock to access registers.
> > 
> > I am not see any "ipg" clock usage in the spi driver.
> 
> It's the register clock. The driver enables it in order to access the
> registers.
> 
> > If "ipg" clock is
> > a dependency for "per" clock, it should be registered in ccm as parent.
> 
> Look, the eCSPI unit has two clock inputs, one for accessing the
> registers (ipg) and one for generating the SPI bit clock (per). Now the
> CSPI unit only has a single clock input, so the 100% correct way would
> be to specify only a single clock for this unit. However, since we
> handle both units with the same driver the simplest way to cope with
> it is to provide the very same clock twice, once for the register access
> and once for generating the SPI bit clock.
> And yes, we have to specify the real clock twice and can't replace one
> with a dummy clock, because if we specify a dummy clock for the ipg
> clock, then the driver couldn't access the registers even if it enabled
> the clock. If we would replace the SPI bit clock with a dummy clock then
> the device couldn't send data even if the driver enabled the bit clock.
> (That of course only becomes relevant when the driver actually
> en/disables the clocks during runtime and not only once during probe).

Well, I completely forgot about the clock for registers.
Everything looks right then.
However, it would be nice to add a few words about the clocks in the
Documentation/devicetree/bindings/spi/fsl-imx~spi.txt
Thanks for the clarification.

---

From gang.chen at asianux.com  Fri May 24 00:17:26 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Fri, 24 May 2013 12:17:26 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <519ECCCF.8090909@asianux.com>
References: <519DCBEF.3090208@asianux.com> <201305231259.43750.arnd@arndb.de>
 <20130523112401.GO18614@n2100.arm.linux.org.uk>
 <201305231409.02359.arnd@arndb.de>
 <20130523125033.GP18614@n2100.arm.linux.org.uk>
 <CAMuHMdUzcBuDupe4Fa6XieziGPMpPKC_k8X8gUUmDvLJ+Fe=Hg@mail.gmail.com>
 <519ECCCF.8090909@asianux.com>
Message-ID: <519EE9D6.9010707@asianux.com>

On 05/24/2013 10:13 AM, Chen Gang wrote:
> On 05/23/2013 10:10 PM, Geert Uytterhoeven wrote:
>> On Thu, May 23, 2013 at 2:50 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>>>> On Thu, May 23, 2013 at 02:09:02PM +0200, Arnd Bergmann wrote:
>>>>>> On Thursday 23 May 2013, Russell King - ARM Linux wrote:
>>>>>>>> This is the problem you guys are missing - unreachable() means "we lose
>>>>>>>> control of the CPU at this point".
>>>>>>
>>>>>> I'm absolutely aware of this. Again, the current behaviour of doing nothing
>>>>>> at all isn't very different from undefined behavior when you get when you
>>>>>> get to the end of a function returning a pointer without a "return" statement,
>>>>>> or when you return from a function that has determined that it is not safe
>>>>>> to continue.
>>>>
>>>> Running off the end of a function like that is a different kettle of fish.
>>>> The execution path is still as the compiler intends - what isn't is that
>>>> the data returned is likely to be random trash.
>>>>
>>>> That's _quite_ different from the CPU starting to execute the contents
>>>> of a literal data pool.
>> I agree it's best to e.g. trap and reboot.
> 

In fact: if enable CONFIG_BUG, but not enable HAVE_ARCH_BUG, the
default implementation is:

 47 #ifndef HAVE_ARCH_BUG
 48 #define BUG() do { \
 49         printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
 50         panic("BUG!"); \
 51 } while (0)
 52 #endif

So if we delete CONFIG_BUG, the default implementation will be almost
like panic(),  and in panic() itself, also calls printk() !!

So...

:-)



> After read the arch/*/include/asm/bug.h,
> 
> It seems panic() is not suitable for NOMMU platforms (only m68k use it,
> also need CONFIG_BUG and CONFIG_SUN3 enabled).
> 
> And unreachable() is need followed with an asm inline instruction (arm,
> x86, powerpc mips...).
> 
> And __builtin_trap() is "the mechanism used may vary from release to
> release so should not rely on any particular implementation" (ref to
> "http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html", used by m68k,
> sparc, ia64).
> 
> I can not find any *trap*() and *unreachable*() in "include/asm-generic/"
> 
> I can not find any suitable implementation which 'generic' enough to add
> in "include/asm-generic/" (and in fact, CONFIG_BUG itself is not
> 'generic' enough to be in "include/asm-generic/").
> 
> 
> At last, I still suggest to delete CONFIG_BUG, so most of architectures
> can skip this issue firstly.
> 
> Then for specific architectures, also can get 3 benefits:
> 
> a. the related maintainers can implement it as their own willing (not
> need discus it with another platform maintainers again);
> 
> b. the related maintainers can free use the platform specific features
> (which can not be used in "include/asm-generic/");
> 
> c. the related maintainers are more familiar their own architectures
> demands and requirements.
> 
> 
> 
> ----------- arch/m68k/include/asm/bug.h --------------------------------
> 
>   1 #ifndef _M68K_BUG_H
>   2 #define _M68K_BUG_H
>   3
>   4 #ifdef CONFIG_MMU
>   5 #ifdef CONFIG_BUG
>   6 #ifdef CONFIG_DEBUG_BUGVERBOSE
>   7 #ifndef CONFIG_SUN3
>   8 #define BUG() do { \
>   9         printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
>  10         __builtin_trap(); \
>  11 } while (0)
>  12 #else
>  13 #define BUG() do { \
>  14         printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
>  15         panic("BUG!"); \
>  16 } while (0)
>  17 #endif
>  18 #else
>  19 #define BUG() do { \
>  20         __builtin_trap(); \
>  21 } while (0)
>  22 #endif
>  23
>  24 #define HAVE_ARCH_BUG
>  25 #endif
>  26 #endif /* CONFIG_MMU */
>  27
>  28 #include <asm-generic/bug.h>
>  29
>  30 #endif
> 
> 
> 
> 
> Thanks.
> 


-- 
Chen Gang

Asianux Corporation


From shawn.guo at linaro.org  Fri May 24 01:21:24 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 May 2013 13:21:24 +0800
Subject: [PATCH] ARM: imx: Enable mx6 solo-lite support
In-Reply-To: <1369352508-12177-1-git-send-email-festevam@gmail.com>
References: <1369352508-12177-1-git-send-email-festevam@gmail.com>
Message-ID: <20130524052121.GD2704@S2101-09.ap.freescale.net>

On Thu, May 23, 2013 at 08:41:48PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

> ---
>  arch/arm/configs/imx_v6_v7_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index 6ec010f..88e24ed 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -37,6 +37,7 @@ CONFIG_MACH_IMX51_DT=y
>  CONFIG_MACH_EUKREA_CPUIMX51SD=y
>  CONFIG_SOC_IMX53=y
>  CONFIG_SOC_IMX6Q=y
> +CONFIG_SOC_IMX6SL=y
>  CONFIG_MXC_PWM=y
>  CONFIG_SMP=y
>  CONFIG_VMSPLIT_2G=y
> -- 
> 1.8.1.2
> 



From shawn.guo at linaro.org  Fri May 24 01:29:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 May 2013 13:29:05 +0800
Subject: [PATCH v2 0/2] dma: imx-sdma: add generic DMA device tree
 bindings support
In-Reply-To: <1366901008-7593-1-git-send-email-shawn.guo@linaro.org>
References: <1366901008-7593-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20130524052903.GE2704@S2101-09.ap.freescale.net>

Vinod,

On Thu, Apr 25, 2013 at 10:43:26PM +0800, Shawn Guo wrote:
> Changes since v1:
>  * Fix the example typo in bindings doc.  Thanks to Fabio.
> 
> Shawn Guo (2):
>   dma: imx: change enum definitions to macros
>   dma: imx-sdma: move to generic device tree bindings

Can you please apply these for 3.11?

Shawn



From vinod.koul at intel.com  Fri May 24 01:03:29 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Fri, 24 May 2013 10:33:29 +0530
Subject: [PATCH v2 0/2] dma: imx-sdma: add generic DMA device tree
 bindings support
In-Reply-To: <20130524052903.GE2704@S2101-09.ap.freescale.net>
References: <1366901008-7593-1-git-send-email-shawn.guo@linaro.org>
 <20130524052903.GE2704@S2101-09.ap.freescale.net>
Message-ID: <20130524050329.GN30200@intel.com>

On Fri, May 24, 2013 at 01:29:05PM +0800, Shawn Guo wrote:
> Vinod,
> 
> On Thu, Apr 25, 2013 at 10:43:26PM +0800, Shawn Guo wrote:
> > Changes since v1:
> >  * Fix the example typo in bindings doc.  Thanks to Fabio.
> > 
> > Shawn Guo (2):
> >   dma: imx: change enum definitions to macros
> >   dma: imx-sdma: move to generic device tree bindings
> 
> Can you please apply these for 3.11?
Sorry I was thinking that you will update the patchset based on Arnd last
comment on (ab)use of macro. Can you fix that & resend

--
~Vinod


From shawn.guo at linaro.org  Fri May 24 01:42:01 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 May 2013 13:42:01 +0800
Subject: [PATCH] ARM: dts: imx: fix clocks for cspi
In-Reply-To: <1369309085-31146-1-git-send-email-jonas@microbit.se>
References: <1369309085-31146-1-git-send-email-jonas@microbit.se>
Message-ID: <20130524054159.GF2704@S2101-09.ap.freescale.net>

On Thu, May 23, 2013 at 01:38:05PM +0200, Jonas Andersson wrote:
> The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor.
> 
> Signed-off-by: Jonas Andersson <jonas at microbit.se>

Applied, thanks.



From nicolas.pitre at linaro.org  Fri May 24 01:45:03 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:03 -0400
Subject: [PATCH 0/8] MCPM support for big.LITTLE Virtual Express RTSM
Message-ID: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>

This implements an MCPM backend for the Virtual Express b.L RTSM model.

This series was partially reviewed during previous posting of some
components in the past, but some new parts were added to improve
the whole thing.

Diffstat:

 Documentation/devicetree/bindings/arm/cci.txt   | 169 ++++++
 .../devicetree/bindings/arm/rtsm-dcscb.txt      |  19 +
 arch/arm/include/asm/cp15.h                     |  14 +
 arch/arm/mach-vexpress/Kconfig                  |   9 +
 arch/arm/mach-vexpress/Makefile                 |   1 +
 arch/arm/mach-vexpress/dcscb.c                  | 255 +++++++++
 arch/arm/mach-vexpress/dcscb_setup.S            |  38 ++
 drivers/bus/Kconfig                             |   7 +
 drivers/bus/Makefile                            |   2 +
 drivers/bus/arm-cci.c                           | 529 ++++++++++++++++++
 drivers/cpuidle/cpuidle-calxeda.c               |  14 +-
 include/linux/arm-cci.h                         |  61 ++
 12 files changed, 1105 insertions(+), 13 deletions(-)


From nicolas.pitre at linaro.org  Fri May 24 01:45:06 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:06 -0400
Subject: [PATCH 3/8] ARM: introduce common set_auxcr/get_auxcr functions
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-4-git-send-email-nicolas.pitre@linaro.org>

From: Rob Herring <rob.herring at calxeda.com>

Move the private set_auxcr/get_auxcr functions from
drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico at linaro.org>
Acked-by: Tony Lindgren <tony at atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/cp15.h       | 14 ++++++++++++++
 drivers/cpuidle/cpuidle-calxeda.c | 14 +-------------
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d..cedd372131 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val)
 	isb();
 }
 
+static inline unsigned int get_auxcr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val));
+	return val;
+}
+
+static inline void set_auxcr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
+	  : : "r" (val));
+	isb();
+}
+
 #ifndef CONFIG_SMP
 extern void adjust_cr(unsigned long mask, unsigned long set);
 #endif
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
index 223379169c..8a08e04c0e 100644
--- a/drivers/cpuidle/cpuidle-calxeda.c
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -37,19 +37,7 @@
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void *scu_base_addr;
 
-static inline unsigned int get_auxcr(void)
-{
-	unsigned int val;
-	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val) : : "cc");
-	return val;
-}
-
-static inline void set_auxcr(unsigned int val)
-{
-	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
-	  : : "r" (val) : "cc");
-	isb();
-}
+static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;
 
 static noinline void calxeda_idle_restore(void)
 {
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:05 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:05 -0400
Subject: [PATCH 2/8] drivers/bus: arm-cci: function to enable CCI ports from
 early boot code
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-3-git-send-email-nicolas.pitre@linaro.org>

This provides cci_enable_port_for_self().  This is the counterpart to
cci_disable_port_by_cpu(self).

This is meant to be called from the MCPM machine specific power_up_setup
callback code when the appropriate affinity level needs to be initialized.
The code therefore has to be position independent as the MMU is still off
and it cannot rely on any stack space.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 drivers/bus/arm-cci.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 109 insertions(+), 6 deletions(-)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index ea81fa4a28..c6ae6e7193 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -43,6 +43,7 @@ enum cci_ace_port_type {
 
 struct cci_ace_port {
 	void __iomem *base;
+	unsigned long phys;
 	enum cci_ace_port_type type;
 	struct device_node *dn;
 };
@@ -51,11 +52,13 @@ static struct cci_ace_port *ports;
 static unsigned int nb_cci_ports;
 
 static void __iomem *cci_ctrl_base;
+static unsigned long cci_ctrl_phys;
 
 struct cpu_port {
 	u64 mpidr;
 	u32 port;
 };
+
 /*
  * Use the port MSB as valid flag, shift can be made dynamic
  * by computing number of bits required for port indexes.
@@ -230,6 +233,98 @@ int notrace cci_disable_port_by_cpu(u64 mpidr)
 EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
 
 /**
+ * cci_enable_port_for_self() - function to enable a CCI port for calling CPU
+ *
+ * Enabling a CCI port for the calling CPU implies enabling the CCI
+ * port controlling that CPU cluster. Code enabling CPU CCI ports
+ * must make sure that the CPU running the code is the first active
+ * CPU in the cluster and all other CPUs are quiescent in a low power
+ * state  or waiting for this CPU to complete the CCI initialization.
+ *
+ * Because this is called when the MMU is still off and with no stack,
+ * the code must be position independent and ideally rely on callee
+ * clobbered registers only.  To achieve this we must code this function
+ * entirely in assembler.
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port look-up failure
+ */
+asmlinkage int __naked cci_enable_port_for_self(void)
+{
+	asm volatile ("\n"
+
+"	mrc	p15, 0, r0, c0, c0, 5	@ get MPIDR value \n"
+"	and	r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
+"	adr	r1, 5f \n"
+"	ldr	r2, [r1] \n"
+"	add	r1, r1, r2		@ &cpu_port \n"
+"	add	ip, r1, %[sizeof_cpu_port] \n"
+
+	/* Loop over the cpu_port array looking for a matching MPIDR */
+"1:	ldr	r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
+"	cmp	r2, r0 			@ compare MPIDR \n"
+"	bne	2f \n"
+
+	/* Found a match, now test port validity */
+"	ldr	r3, [r1, %[offsetof_cpu_port_port]] \n"
+"	tst	r3, #"__stringify(PORT_VALID)" \n"
+"	bne	3f \n"
+
+	/* no match, loop with the next cpu_port entry */
+"2:	add	r1, r1, %[sizeof_struct_cpu_port] \n"
+"	cmp	r1, ip			@ done? \n"
+"	blo	1b \n"
+"	mov	r0, #"__stringify(-ENODEV)" \n"
+"	bx	lr \n"
+
+	/* Use matched port index to look up the corresponding ports entry */
+"3:	bic	r3, r3, #"__stringify(PORT_VALID)" \n"
+"	adr	r0, 6f \n"
+"	ldmia	r0, {r1, r2} \n"
+"	sub	r1, r1, r0 		@ virt - phys \n"
+"	ldr	r0, [r0, r2] 		@ *(&ports) \n"
+"	mov	r2, %[sizeof_struct_ace_port] \n"
+"	mla	r0, r2, r3, r0		@ &ports[index] \n"
+"	sub	r0, r0, r1		@ virt_to_phys() \n"
+
+	/* Enable the CCI port */
+"	ldr	r0, [r0, %[offsetof_port_phys]] \n"
+"	mov	r3, #"__stringify(CCI_ENABLE_REQ)" \n"
+"	str	r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
+
+	/* poll the status reg for completion */
+"	adr	r1, 7f \n"
+"	ldr	r0, [r1] \n"
+"	ldr	r0, [r0, r1]		@ cci_ctrl_base \n"
+"4:	ldr	r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
+"	tst	r1, #1 \n"
+"	bne	4b \n"
+
+"	mov	r0, #0 \n"
+"	bx	lr \n"
+
+"	.align \n"
+"5:	.word	cpu_port - . \n"
+"6:	.word	. \n"
+"	.word	ports - 6b \n"
+"7:	.word	cci_ctrl_phys - . \n"
+	: :
+	[sizeof_cpu_port] "i" (sizeof(cpu_port)),
+#ifndef __ARMEB__
+	[offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
+#else
+	[offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
+#endif
+	[offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
+	[sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
+	[sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
+	[offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
+
+	unreachable();
+}
+
+/**
  * __cci_control_port_by_device() - function to control a CCI port by device
  *				    reference
  *
@@ -306,6 +401,7 @@ static int __init cci_probe(void)
 	struct cci_nb_ports const *cci_config;
 	int ret, i, nb_ace = 0, nb_ace_lite = 0;
 	struct device_node *np, *cp;
+	struct resource res;
 	const char *match_str;
 	bool is_ace;
 
@@ -323,9 +419,12 @@ static int __init cci_probe(void)
 	if (!ports)
 		return -ENOMEM;
 
-	cci_ctrl_base = of_iomap(np, 0);
-
-	if (!cci_ctrl_base) {
+	ret = of_address_to_resource(np, 0, &res);
+	if (!ret) {
+		cci_ctrl_base = ioremap(res.start, resource_size(&res));
+		cci_ctrl_phys =	res.start;
+	}
+	if (ret || !cci_ctrl_base) {
 		WARN(1, "unable to ioremap CCI ctrl\n");
 		ret = -ENXIO;
 		goto memalloc_err;
@@ -353,9 +452,12 @@ static int __init cci_probe(void)
 			continue;
 		}
 
-		ports[i].base = of_iomap(cp, 0);
-
-		if (!ports[i].base) {
+		ret = of_address_to_resource(cp, 0, &res);
+		if (!ret) {
+			ports[i].base = ioremap(res.start, resource_size(&res));
+			ports[i].phys = res.start;
+		}	
+		if (ret || !ports[i].base) {
 			WARN(1, "unable to ioremap CCI port %d\n", i);
 			continue;
 		}
@@ -382,6 +484,7 @@ static int __init cci_probe(void)
 	 * cluster power-up/power-down. Make sure it reaches main memory.
 	 */
 	sync_cache_w(&cci_ctrl_base);
+	sync_cache_w(&cci_ctrl_phys);
 	sync_cache_w(&ports);
 	sync_cache_w(&cpu_port);
 	__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:04 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:04 -0400
Subject: [PATCH 1/8] drivers: bus: add ARM CCI support
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-2-git-send-email-nicolas.pitre@linaro.org>

From: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>

On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.

This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.

Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.

CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.

Documentation describing the CCI DT bindings is provided with the patch.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 Documentation/devicetree/bindings/arm/cci.txt | 169 ++++++++++
 drivers/bus/Kconfig                           |   7 +
 drivers/bus/Makefile                          |   2 +
 drivers/bus/arm-cci.c                         | 426 ++++++++++++++++++++++++++
 include/linux/arm-cci.h                       |  61 ++++
 5 files changed, 665 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cci.txt
 create mode 100644 drivers/bus/arm-cci.c
 create mode 100644 include/linux/arm-cci.h

diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
new file mode 100644
index 0000000000..a132e26a1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -0,0 +1,169 @@
+=======================================================
+ARM CCI cache coherent interconnect binding description
+=======================================================
+
+ARM multi-cluster systems maintain intra-cluster coherency through a
+cache coherent interconnect (CCI) that is capable of monitoring bus
+transactions and manage coherency, TLB invalidations and memory barriers.
+
+It allows snooping and distributed virtual memory message broadcast across
+clusters, through memory mapped interface, with a global control register
+space and multiple sets of interface control registers, one per slave
+interface.
+
+Bindings for the CCI node follow the ePAPR standard, available from:
+
+www.power.org/documentation/epapr-version-1-1/
+
+with the addition of the bindings described in this document which are
+specific to ARM.
+
+* CCI interconnect node
+
+	Description: Describes a CCI cache coherent Interconnect component
+
+	Node name must be "cci".
+	Node's parent must be the root node /, and the address space visible
+	through the CCI interconnect is the same as the one seen from the
+	root node (ie from CPUs perspective as per DT standard).
+	Every CCI node has to define the following properties:
+
+	- compatible
+		Usage: required
+		Value type: <string>
+		Definition: must be set to
+			    "arm,cci-400"
+
+	- reg
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property. Specifies base physical
+			    address of CCI control registers common to all
+			    interfaces.
+
+	- ranges:
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property. Follow rules in the ePAPR for
+			    hierarchical bus addressing. CCI interfaces
+			    addresses refer to the parent node addressing
+			    scheme to declare their register bases.
+
+	CCI interconnect node can define the following child nodes:
+
+	- CCI control interface nodes
+
+		Node name must be "slave-if".
+		Parent node must be CCI interconnect node.
+
+		A CCI control interface node must contain the following
+		properties:
+
+		- compatible
+			Usage: required
+			Value type: <string>
+			Definition: must be set to
+				    "arm,cci-400-ctrl-if"
+
+		- interface-type:
+			Usage: required
+			Value type: <string>
+			Definition: must be set to one of {"ace", "ace-lite"}
+				    depending on the interface type the node
+				    represents.
+
+		- reg:
+			Usage: required
+			Value type: <prop-encoded-array>
+			Definition: the base address and size of the
+				    corresponding interface programming
+				    registers.
+
+* CCI interconnect bus masters
+
+	Description: masters in the device tree connected to a CCI port
+		     (inclusive of CPUs and their cpu nodes).
+
+	A CCI interconnect bus master node must contain the following
+	properties:
+
+	- cci-control-port:
+		Usage: required
+		Value type: <phandle>
+		Definition: a phandle containing the CCI control interface node
+			    the master is connected to.
+
+Example:
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		CPU0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			cci-control-port = <&cci_control1>;
+			reg = <0x0>;
+		};
+
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			cci-control-port = <&cci_control1>;
+			reg = <0x1>;
+		};
+
+		CPU2: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			cci-control-port = <&cci_control2>;
+			reg = <0x100>;
+		};
+
+		CPU3: cpu at 101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			cci-control-port = <&cci_control2>;
+			reg = <0x101>;
+		};
+
+	};
+
+	dma0: dma at 3000000 {
+		compatible = "arm,pl330", "arm,primecell";
+		cci-control-port = <&cci_control0>;
+		reg = <0x0 0x3000000 0x0 0x1000>;
+		interrupts = <10>;
+		#dma-cells = <1>;
+		#dma-channels = <8>;
+		#dma-requests = <32>;
+	};
+
+	cci at 2c090000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x2c090000 0 0x1000>;
+		ranges = <0x0 0x0 0x2c090000 0x6000>;
+
+		cci_control0: slave-if at 1000 {
+			interface-type = "ace-lite";
+			reg = <0x1000 0x1000>;
+		};
+
+		cci_control1: slave-if at 4000 {
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+
+		cci_control2: slave-if at 5000 {
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
+		};
+	};
+
+This CCI node corresponds to a CCI component whose control registers sits
+at address 0x000000002c090000.
+CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
+CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
+CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab915..5286e2d333 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -26,4 +26,11 @@ config OMAP_INTERCONNECT
 
 	help
 	  Driver to enable OMAP interconnect error handling driver.
+
+config ARM_CCI
+	bool "ARM CCI driver support"
+	depends on ARM
+	help
+	  Driver supporting the CCI cache coherent interconnect for ARM
+	  platforms.
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c120..670cea4438 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
 # Interconnect bus driver for OMAP SoCs.
 obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
+# CCI cache coherent interconnect for ARM platforms
+obj-$(CONFIG_ARM_CCI)		+= arm-cci.o
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
new file mode 100644
index 0000000000..ea81fa4a28
--- /dev/null
+++ b/drivers/bus/arm-cci.c
@@ -0,0 +1,426 @@
+/*
+ * CCI cache coherent interconnect driver
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+
+#define CCI_PORT_CTRL		0x0
+#define CCI_CTRL_STATUS		0xc
+
+#define CCI_ENABLE_SNOOP_REQ	0x1
+#define CCI_ENABLE_DVM_REQ	0x2
+#define CCI_ENABLE_REQ		(CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
+
+struct cci_nb_ports {
+	unsigned int nb_ace;
+	unsigned int nb_ace_lite;
+};
+
+enum cci_ace_port_type {
+	ACE_INVALID_PORT = 0x0,
+	ACE_PORT,
+	ACE_LITE_PORT,
+};
+
+struct cci_ace_port {
+	void __iomem *base;
+	enum cci_ace_port_type type;
+	struct device_node *dn;
+};
+
+static struct cci_ace_port *ports;
+static unsigned int nb_cci_ports;
+
+static void __iomem *cci_ctrl_base;
+
+struct cpu_port {
+	u64 mpidr;
+	u32 port;
+};
+/*
+ * Use the port MSB as valid flag, shift can be made dynamic
+ * by computing number of bits required for port indexes.
+ * Code disabling CCI cpu ports runs with D-cache invalidated
+ * and SCTLR bit clear so data accesses must be kept to a minimum
+ * to improve performance; for now shift is left static to
+ * avoid one more data access while disabling the CCI port.
+ */
+#define PORT_VALID_SHIFT	31
+#define PORT_VALID		(0x1 << PORT_VALID_SHIFT)
+
+static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
+{
+	port->port = PORT_VALID | index;
+	port->mpidr = mpidr;
+}
+
+static inline bool cpu_port_is_valid(struct cpu_port *port)
+{
+	return !!(port->port & PORT_VALID);
+}
+
+static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
+{
+	return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
+}
+
+static struct cpu_port cpu_port[NR_CPUS];
+
+/**
+ * __cci_ace_get_port - Function to retrieve the port index connected to
+ *			a cpu or device.
+ *
+ * @dn: device node of the device to look-up
+ * @type: port type
+ *
+ * Return value:
+ *	- CCI port index if success
+ *	- -ENODEV if failure
+ */
+static int __cci_ace_get_port(struct device_node *dn, int type)
+{
+	int i;
+	bool ace_match;
+	struct device_node *cci_portn;
+
+	cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
+	for (i = 0; i < nb_cci_ports; i++) {
+		ace_match = ports[i].type == type;
+		if (ace_match && cci_portn == ports[i].dn)
+			return i;
+	}
+	return -ENODEV;
+}
+
+int cci_ace_get_port(struct device_node *dn)
+{
+	return __cci_ace_get_port(dn, ACE_LITE_PORT);
+}
+EXPORT_SYMBOL_GPL(cci_ace_get_port);
+
+static void __init cci_ace_init_ports(void)
+{
+	int port, ac, cpu;
+	u64 hwid;
+	const u32 *cell;
+	struct device_node *cpun, *cpus;
+
+	cpus = of_find_node_by_path("/cpus");
+	if (WARN(!cpus, "Missing cpus node, bailing out\n"))
+		return;
+
+	if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
+		ac = of_n_addr_cells(cpus);
+
+	/*
+	 * Port index look-up speeds up the function disabling ports by CPU,
+	 * since the logical to port index mapping is done once and does
+	 * not change after system boot.
+	 * The stashed index array is initialized for all possible CPUs
+	 * at probe time.
+	 */
+	for_each_child_of_node(cpus, cpun) {
+		if (of_node_cmp(cpun->type, "cpu"))
+			continue;
+		cell = of_get_property(cpun, "reg", NULL);
+		if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
+			continue;
+
+		hwid = of_read_number(cell, ac);
+		cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
+
+		if (cpu < 0 || !cpu_possible(cpu))
+			continue;
+		port = __cci_ace_get_port(cpun, ACE_PORT);
+		if (port < 0)
+			continue;
+
+		init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
+	}
+
+	for_each_possible_cpu(cpu) {
+		WARN(!cpu_port_is_valid(&cpu_port[cpu]),
+			"CPU %u does not have an associated CCI port\n",
+			cpu);
+	}
+}
+/*
+ * Functions to enable/disable a CCI interconnect slave port
+ *
+ * They are called by low-level power management code to disable slave
+ * interfaces snoops and DVM broadcast.
+ * Since they may execute with cache data allocation disabled and
+ * after the caches have been cleaned and invalidated the functions provide
+ * no explicit locking since they may run with D-cache disabled, so normal
+ * cacheable kernel locks based on ldrex/strex may not work.
+ * Locking has to be provided by BSP implementations to ensure proper
+ * operations.
+ */
+
+/**
+ * cci_port_control() - function to control a CCI port
+ *
+ * @port: index of the port to setup
+ * @enable: if true enables the port, if false disables it
+ */
+static void notrace cci_port_control(unsigned int port, bool enable)
+{
+	void __iomem *base = ports[port].base;
+
+	writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
+	/*
+	 * This function is called from power down procedures
+	 * and must not execute any instruction that might
+	 * cause the processor to be put in a quiescent state
+	 * (eg wfi). Hence, cpu_relax() can not be added to this
+	 * read loop to optimize power, since it might hide possibly
+	 * disruptive operations.
+	 */
+	while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
+			;
+}
+
+/**
+ * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
+ *			       reference
+ *
+ * @mpidr: mpidr of the CPU whose CCI port should be disabled
+ *
+ * Disabling a CCI port for a CPU implies disabling the CCI port
+ * controlling that CPU cluster. Code disabling CPU CCI ports
+ * must make sure that the CPU running the code is the last active CPU
+ * in the cluster ie all other CPUs are quiescent in a low power state.
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port look-up failure
+ */
+int notrace cci_disable_port_by_cpu(u64 mpidr)
+{
+	int cpu;
+	bool is_valid;
+	for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
+		is_valid = cpu_port_is_valid(&cpu_port[cpu]);
+		if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
+			cci_port_control(cpu_port[cpu].port, false);
+			return 0;
+		}
+	}
+	return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
+
+/**
+ * __cci_control_port_by_device() - function to control a CCI port by device
+ *				    reference
+ *
+ * @dn: device node pointer of the device whose CCI port should be
+ *      controlled
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port look-up failure
+ */
+int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
+{
+	int port;
+
+	if (!dn)
+		return -ENODEV;
+
+	port = __cci_ace_get_port(dn, ACE_LITE_PORT);
+	if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
+				dn->full_name))
+		return -ENODEV;
+	cci_port_control(port, enable);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
+
+/**
+ * __cci_control_port_by_index() - function to control a CCI port by port index
+ *
+ * @port: port index previously retrieved with cci_ace_get_port()
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *	0 on success
+ *	-ENODEV on port index out of range
+ *	-EPERM if operation carried out on an ACE PORT
+ */
+int notrace __cci_control_port_by_index(u32 port, bool enable)
+{
+	if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
+		return -ENODEV;
+	/*
+	 * CCI control for ports connected to CPUS is extremely fragile
+	 * and must be made to go through a specific and controlled
+	 * interface (ie cci_disable_port_by_cpu(); control by general purpose
+	 * indexing is therefore disabled for ACE ports.
+	 */
+	if (ports[port].type == ACE_PORT)
+		return -EPERM;
+
+	cci_port_control(port, enable);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
+
+static const struct cci_nb_ports cci400_ports = {
+	.nb_ace = 2,
+	.nb_ace_lite = 3
+};
+
+static const struct of_device_id arm_cci_matches[] = {
+	{.compatible = "arm,cci-400", .data = &cci400_ports },
+	{},
+};
+
+static const struct of_device_id arm_cci_ctrl_if_matches[] = {
+	{.compatible = "arm,cci-400-ctrl-if", },
+	{},
+};
+
+static int __init cci_probe(void)
+{
+	struct cci_nb_ports const *cci_config;
+	int ret, i, nb_ace = 0, nb_ace_lite = 0;
+	struct device_node *np, *cp;
+	const char *match_str;
+	bool is_ace;
+
+	np = of_find_matching_node(NULL, arm_cci_matches);
+	if (!np)
+		return -ENODEV;
+
+	cci_config = of_match_node(arm_cci_matches, np)->data;
+	if (!cci_config)
+		return -ENODEV;
+
+	nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
+
+	ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
+	if (!ports)
+		return -ENOMEM;
+
+	cci_ctrl_base = of_iomap(np, 0);
+
+	if (!cci_ctrl_base) {
+		WARN(1, "unable to ioremap CCI ctrl\n");
+		ret = -ENXIO;
+		goto memalloc_err;
+	}
+
+	for_each_child_of_node(np, cp) {
+		if (!of_match_node(arm_cci_ctrl_if_matches, cp))
+			continue;
+
+		i = nb_ace + nb_ace_lite;
+
+		if (i >= nb_cci_ports)
+			break;
+
+		if (of_property_read_string(cp, "interface-type",
+					&match_str)) {
+			WARN(1, "node %s missing interface-type property\n",
+				  cp->full_name);
+			continue;
+		}
+		is_ace = strcmp(match_str, "ace") == 0;
+		if (!is_ace && strcmp(match_str, "ace-lite")) {
+			WARN(1, "node %s containing invalid interface-type property, skipping it\n",
+					cp->full_name);
+			continue;
+		}
+
+		ports[i].base = of_iomap(cp, 0);
+
+		if (!ports[i].base) {
+			WARN(1, "unable to ioremap CCI port %d\n", i);
+			continue;
+		}
+
+		if (is_ace) {
+			if (WARN_ON(nb_ace >= cci_config->nb_ace))
+				continue;
+			ports[i].type = ACE_PORT;
+			++nb_ace;
+		} else {
+			if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
+				continue;
+			ports[i].type = ACE_LITE_PORT;
+			++nb_ace_lite;
+		}
+		ports[i].dn = cp;
+	}
+
+	 /* initialize a stashed array of ACE ports to speed-up look-up */
+	cci_ace_init_ports();
+
+	/*
+	 * Multi-cluster systems may need this data when non-coherent, during
+	 * cluster power-up/power-down. Make sure it reaches main memory.
+	 */
+	sync_cache_w(&cci_ctrl_base);
+	sync_cache_w(&ports);
+	sync_cache_w(&cpu_port);
+	__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
+	pr_info("ARM CCI driver probed\n");
+	return 0;
+
+memalloc_err:
+
+	kfree(ports);
+	return ret;
+}
+
+static int cci_init_status = -EAGAIN;
+static DEFINE_MUTEX(cci_probing);
+
+static int __init cci_init(void)
+{
+	if (cci_init_status != -EAGAIN)
+		return cci_init_status;
+
+	mutex_lock(&cci_probing);
+	if (cci_init_status == -EAGAIN)
+		cci_init_status = cci_probe();
+	mutex_unlock(&cci_probing);
+	return cci_init_status;
+}
+
+/*
+ * To sort out early init calls ordering a helper function is provided to
+ * check if the CCI driver has beed initialized. Function check if the driver
+ * has been initialized, if not it calls the init function that probes
+ * the driver and updates the return value.
+ */
+bool __init cci_probed(void)
+{
+	return cci_init() == 0;
+}
+EXPORT_SYMBOL_GPL(cci_probed);
+
+early_initcall(cci_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ARM CCI support");
diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
new file mode 100644
index 0000000000..79d6edf446
--- /dev/null
+++ b/include/linux/arm-cci.h
@@ -0,0 +1,61 @@
+/*
+ * CCI cache coherent interconnect support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_ARM_CCI_H
+#define __LINUX_ARM_CCI_H
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct device_node;
+
+#ifdef CONFIG_ARM_CCI
+extern bool cci_probed(void);
+extern int cci_ace_get_port(struct device_node *dn);
+extern int cci_disable_port_by_cpu(u64 mpidr);
+extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
+extern int __cci_control_port_by_index(u32 port, bool enable);
+#else
+static inline bool cci_probed(void) { return false; }
+static inline int cci_ace_get_port(struct device_node *dn)
+{
+	return -ENODEV;
+}
+static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
+static inline int __cci_control_port_by_device(struct device_node *dn,
+					       bool enable)
+{
+	return -ENODEV;
+}
+static inline int __cci_control_port_by_index(u32 port, bool enable)
+{
+	return -ENODEV;
+}
+#endif
+#define cci_disable_port_by_device(dev) \
+	__cci_control_port_by_device(dev, false)
+#define cci_enable_port_by_device(dev) \
+	__cci_control_port_by_device(dev, true)
+#define cci_disable_port_by_index(dev) \
+	__cci_control_port_by_index(dev, false)
+#define cci_enable_port_by_index(dev) \
+	__cci_control_port_by_index(dev, true)
+
+#endif
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:07 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:07 -0400
Subject: [PATCH 4/8] ARM: vexpress: introduce DCSCB support
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-5-git-send-email-nicolas.pitre@linaro.org>

This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).

The cache coherency interconnect (CCI) is not handled yet.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 .../devicetree/bindings/arm/rtsm-dcscb.txt         |  19 +++
 arch/arm/mach-vexpress/Kconfig                     |   8 +
 arch/arm/mach-vexpress/Makefile                    |   1 +
 arch/arm/mach-vexpress/dcscb.c                     | 162 +++++++++++++++++++++
 4 files changed, 190 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
 create mode 100644 arch/arm/mach-vexpress/dcscb.c

diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
new file mode 100644
index 0000000000..3b8fbf3c00
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
@@ -0,0 +1,19 @@
+ARM Dual Cluster System Configuration Block
+-------------------------------------------
+
+The Dual Cluster System Configuration Block (DCSCB) provides basic
+functionality for controlling clocks, resets and configuration pins in
+the Dual Cluster System implemented by the Real-Time System Model (RTSM).
+
+Required properties:
+
+- compatible : should be "arm,rtsm,dcscb"
+
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	dcscb at 60000000 {
+		compatible = "arm,rtsm,dcscb";
+		reg = <0x60000000 0x1000>;
+	};
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 5907e10c37..2f46385c28 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -57,4 +57,12 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 
+config ARCH_VEXPRESS_DCSCB
+	bool "Dual Cluster System Control Block (DCSCB) support"
+	depends on MCPM
+	help
+	  Support for the Dual Cluster System Configuration Block (DCSCB).
+	  This is needed to provide CPU and cluster power management
+	  on RTSM implementing big.LITTLE.
+
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8b4d..518519f57a 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o
 obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
new file mode 100644
index 0000000000..38f042a6b2
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -0,0 +1,162 @@
+/*
+ * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
+ *
+ * Created by:	Nicolas Pitre, May 2012
+ * Copyright:	(C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/vexpress.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+
+#define RST_HOLD0	0x0
+#define RST_HOLD1	0x4
+#define SYS_SWRESET	0x8
+#define RST_STAT0	0xc
+#define RST_STAT1	0x10
+#define EAG_CFG_R	0x20
+#define EAG_CFG_W	0x24
+#define KFC_CFG_R	0x28
+#define KFC_CFG_W	0x2c
+#define DCS_CFG_R	0x30
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() while its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static void __iomem *dcscb_base;
+
+static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int rst_hold, cpumask = (1 << cpu);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	if (cpu >= 4 || cluster >= 2)
+		return -EINVAL;
+
+	/*
+	 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+	 * variant exists, we need to disable IRQs manually here.
+	 */
+	local_irq_disable();
+	arch_spin_lock(&dcscb_lock);
+
+	rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+	if (rst_hold & (1 << 8)) {
+		/* remove cluster reset and add individual CPU's reset */
+		rst_hold &= ~(1 << 8);
+		rst_hold |= 0xf;
+	}
+	rst_hold &= ~(cpumask | (cpumask << 4));
+	writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+
+	arch_spin_unlock(&dcscb_lock);
+	local_irq_enable();
+
+	return 0;
+}
+
+static void dcscb_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster, rst_hold, cpumask, last_man;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	cpumask = (1 << cpu);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= 4 || cluster >= 2);
+
+	arch_spin_lock(&dcscb_lock);
+	rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+	rst_hold |= cpumask;
+	if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf)
+		rst_hold |= (1 << 8);
+	writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+	arch_spin_unlock(&dcscb_lock);
+	last_man = (rst_hold & (1 << 8));
+
+	/*
+	 * Now let's clean our L1 cache and shut ourself down.
+	 * If we're the last CPU in this cluster then clean L2 too.
+	 */
+
+	/*
+	 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+	 * a preliminary flush here for those CPUs.  At least, that's
+	 * the theory -- without the extra flush, Linux explodes on
+	 * RTSM (to be investigated)..
+	 */
+	flush_cache_louis();
+	set_cr(get_cr() & ~CR_C);
+
+	if (!last_man) {
+		flush_cache_louis();
+	} else {
+		flush_cache_all();
+		outer_flush_all();
+	}
+
+	/* Disable local coherency by clearing the ACTLR "SMP" bit: */
+	set_auxcr(get_auxcr() & ~(1 << 6));
+
+	/* Now we are prepared for power-down, do it: */
+	dsb();
+	wfi();
+
+	/* Not dead at this point?  Let our caller cope. */
+}
+
+static const struct mcpm_platform_ops dcscb_power_ops = {
+	.power_up	= dcscb_power_up,
+	.power_down	= dcscb_power_down,
+};
+
+static int __init dcscb_init(void)
+{
+	struct device_node *node;
+	int ret;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
+	if (!node)
+		return -ENODEV;
+	dcscb_base = of_iomap(node, 0);
+	if (!dcscb_base)
+		return -EADDRNOTAVAIL;
+
+	ret = mcpm_platform_register(&dcscb_power_ops);
+	if (ret) {
+		iounmap(dcscb_base);
+		return ret;
+	}
+
+	/*
+	 * Future entries into the kernel can now go
+	 * through the cluster entry vectors.
+	 */
+	vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+
+	return 0;
+}
+
+early_initcall(dcscb_init);
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:09 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:09 -0400
Subject: [PATCH 6/8] ARM: vexpress/dcscb: do not hardcode number of CPUs per
 cluster
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-7-git-send-email-nicolas.pitre@linaro.org>

If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
shut down the initial cluster as the 0xf reset bit mask will never be
observed.  Let's construct this mask based on the provided information
in the DCSCB config register for the number of CPUs per cluster.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-vexpress/dcscb.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 98873b1c0f..b928b1f5eb 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -45,10 +45,12 @@ static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 
 static void __iomem *dcscb_base;
 static int dcscb_use_count[4][2];
+static int dcscb_mcpm_cpu_mask[2];
 
 static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 {
 	unsigned int rst_hold, cpumask = (1 << cpu);
+	unsigned int mcpm_mask = dcscb_mcpm_cpu_mask[cluster];
 
 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 	if (cpu >= 4 || cluster >= 2)
@@ -67,7 +69,7 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 		if (rst_hold & (1 << 8)) {
 			/* remove cluster reset and add individual CPU's reset */
 			rst_hold &= ~(1 << 8);
-			rst_hold |= 0xf;
+			rst_hold |= mcpm_mask;
 		}
 		rst_hold &= ~(cpumask | (cpumask << 4));
 		writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
@@ -91,13 +93,14 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 
 static void dcscb_power_down(void)
 {
-	unsigned int mpidr, cpu, cluster, rst_hold, cpumask;
+	unsigned int mpidr, cpu, cluster, rst_hold, cpumask, mcpm_mask;
 	bool last_man = false, skip_wfi = false;
 
 	mpidr = read_cpuid_mpidr();
 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 	cpumask = (1 << cpu);
+	mcpm_mask = dcscb_mcpm_cpu_mask[cluster];
 
 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 	BUG_ON(cpu >= 4 || cluster >= 2);
@@ -107,7 +110,7 @@ static void dcscb_power_down(void)
 	if (dcscb_use_count[cpu][cluster] == 0) {
 		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
 		rst_hold |= cpumask;
-		if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf) {
+		if (((rst_hold | (rst_hold >> 4)) & mcpm_mask) == mcpm_mask) {
 			rst_hold |= (1 << 8);
 			last_man = true;
 		}
@@ -177,6 +180,7 @@ static void __init dcscb_usage_count_init(void)
 static int __init dcscb_init(void)
 {
 	struct device_node *node;
+	unsigned int cfg;
 	int ret;
 
 	node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
@@ -185,7 +189,9 @@ static int __init dcscb_init(void)
 	dcscb_base = of_iomap(node, 0);
 	if (!dcscb_base)
 		return -EADDRNOTAVAIL;
-
+	cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
+	dcscb_mcpm_cpu_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
+	dcscb_mcpm_cpu_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
 	dcscb_usage_count_init();
 
 	ret = mcpm_platform_register(&dcscb_power_ops);
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:08 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:08 -0400
Subject: [PATCH 5/8] ARM: vexpress/dcscb: add CPU use counts to the power
 up/down API implementation
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-6-git-send-email-nicolas.pitre@linaro.org>

It is possible for a CPU to be told to power up before it managed
to power itself down.  Solve this race with a usage count to deal
with this possibility as mandated by the MCPM API definition.

Signed-off-by: nicolas Pitre <nico at linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-vexpress/dcscb.c | 74 +++++++++++++++++++++++++++++++++---------
 1 file changed, 59 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 38f042a6b2..98873b1c0f 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -44,6 +44,7 @@
 static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 
 static void __iomem *dcscb_base;
+static int dcscb_use_count[4][2];
 
 static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 {
@@ -60,14 +61,27 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 	local_irq_disable();
 	arch_spin_lock(&dcscb_lock);
 
-	rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
-	if (rst_hold & (1 << 8)) {
-		/* remove cluster reset and add individual CPU's reset */
-		rst_hold &= ~(1 << 8);
-		rst_hold |= 0xf;
+	dcscb_use_count[cpu][cluster]++;
+	if (dcscb_use_count[cpu][cluster] == 1) {
+		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+		if (rst_hold & (1 << 8)) {
+			/* remove cluster reset and add individual CPU's reset */
+			rst_hold &= ~(1 << 8);
+			rst_hold |= 0xf;
+		}
+		rst_hold &= ~(cpumask | (cpumask << 4));
+		writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+	} else if (dcscb_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
 	}
-	rst_hold &= ~(cpumask | (cpumask << 4));
-	writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
 
 	arch_spin_unlock(&dcscb_lock);
 	local_irq_enable();
@@ -77,7 +91,8 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 
 static void dcscb_power_down(void)
 {
-	unsigned int mpidr, cpu, cluster, rst_hold, cpumask, last_man;
+	unsigned int mpidr, cpu, cluster, rst_hold, cpumask;
+	bool last_man = false, skip_wfi = false;
 
 	mpidr = read_cpuid_mpidr();
 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
@@ -88,13 +103,26 @@ static void dcscb_power_down(void)
 	BUG_ON(cpu >= 4 || cluster >= 2);
 
 	arch_spin_lock(&dcscb_lock);
-	rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
-	rst_hold |= cpumask;
-	if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf)
-		rst_hold |= (1 << 8);
-	writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+	dcscb_use_count[cpu][cluster]--;
+	if (dcscb_use_count[cpu][cluster] == 0) {
+		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+		rst_hold |= cpumask;
+		if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf) {
+			rst_hold |= (1 << 8);
+			last_man = true;
+		}
+		writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+	} else if (dcscb_use_count[cpu][cluster] == 1) {
+		/*
+		 * A power_up request went ahead of us.
+		 * Even if we do not want to shut this CPU down,
+		 * the caller expects a certain state as if the WFI
+		 * was aborted.  So let's continue with cache cleaning.
+		 */
+		skip_wfi = true;
+	} else
+		BUG();
 	arch_spin_unlock(&dcscb_lock);
-	last_man = (rst_hold & (1 << 8));
 
 	/*
 	 * Now let's clean our L1 cache and shut ourself down.
@@ -122,7 +150,8 @@ static void dcscb_power_down(void)
 
 	/* Now we are prepared for power-down, do it: */
 	dsb();
-	wfi();
+	if (!skip_wfi)
+		wfi();
 
 	/* Not dead at this point?  Let our caller cope. */
 }
@@ -132,6 +161,19 @@ static const struct mcpm_platform_ops dcscb_power_ops = {
 	.power_down	= dcscb_power_down,
 };
 
+static void __init dcscb_usage_count_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= 4 || cluster >= 2);
+	dcscb_use_count[cpu][cluster] = 1;
+}
+
 static int __init dcscb_init(void)
 {
 	struct device_node *node;
@@ -144,6 +186,8 @@ static int __init dcscb_init(void)
 	if (!dcscb_base)
 		return -EADDRNOTAVAIL;
 
+	dcscb_usage_count_init();
+
 	ret = mcpm_platform_register(&dcscb_power_ops);
 	if (ret) {
 		iounmap(dcscb_base);
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:10 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:10 -0400
Subject: [PATCH 7/8] ARM: vexpress/dcscb: handle platform coherency exit/setup
 and CCI
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-8-git-send-email-nicolas.pitre@linaro.org>

From: Dave Martin <dave.martin at linaro.org>

Add the required code to properly handle race free platform coherency exit
to the DCSCB power down method.

The power_up_setup callback is used to enable the CCI interface for
the cluster being brought up.  This must be done in assembly before
the kernel environment is entered.

Thanks to Achin Gupta and Nicolas Pitre for their help and
contributions.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Signed-off-by: Nicolas Pitre <nico at linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-vexpress/Kconfig       |  1 +
 arch/arm/mach-vexpress/Makefile      |  2 +-
 arch/arm/mach-vexpress/dcscb.c       | 79 +++++++++++++++++++++++++++---------
 arch/arm/mach-vexpress/dcscb_setup.S | 38 +++++++++++++++++
 4 files changed, 100 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/mach-vexpress/dcscb_setup.S

diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 2f46385c28..b8bbabec63 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -60,6 +60,7 @@ config ARCH_VEXPRESS_CA9X4
 config ARCH_VEXPRESS_DCSCB
 	bool "Dual Cluster System Control Block (DCSCB) support"
 	depends on MCPM
+	select ARM_CCI
 	help
 	  Support for the Dual Cluster System Configuration Block (DCSCB).
 	  This is needed to provide CPU and cluster power management
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 518519f57a..48ba89a814 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -6,6 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
-obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o
+obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o	dcscb_setup.o
 obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index b928b1f5eb..1acc975360 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -16,6 +16,7 @@
 #include <linux/errno.h>
 #include <linux/of_address.h>
 #include <linux/vexpress.h>
+#include <linux/arm-cci.h>
 
 #include <asm/mcpm.h>
 #include <asm/proc-fns.h>
@@ -105,7 +106,10 @@ static void dcscb_power_down(void)
 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 	BUG_ON(cpu >= 4 || cluster >= 2);
 
+	__mcpm_cpu_going_down(cpu, cluster);
+
 	arch_spin_lock(&dcscb_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
 	dcscb_use_count[cpu][cluster]--;
 	if (dcscb_use_count[cpu][cluster] == 0) {
 		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
@@ -125,31 +129,59 @@ static void dcscb_power_down(void)
 		skip_wfi = true;
 	} else
 		BUG();
-	arch_spin_unlock(&dcscb_lock);
-
-	/*
-	 * Now let's clean our L1 cache and shut ourself down.
-	 * If we're the last CPU in this cluster then clean L2 too.
-	 */
 
-	/*
-	 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
-	 * a preliminary flush here for those CPUs.  At least, that's
-	 * the theory -- without the extra flush, Linux explodes on
-	 * RTSM (to be investigated)..
-	 */
-	flush_cache_louis();
-	set_cr(get_cr() & ~CR_C);
+	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+		arch_spin_unlock(&dcscb_lock);
 
-	if (!last_man) {
-		flush_cache_louis();
-	} else {
+		/*
+		 * Flush all cache levels for this cluster.
+		 *
+		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+		 * a preliminary flush here for those CPUs.  At least, that's
+		 * the theory -- without the extra flush, Linux explodes on
+		 * RTSM (to be investigated).
+		 */
+		flush_cache_all();
+		set_cr(get_cr() & ~CR_C);
 		flush_cache_all();
+
+		/*
+		 * This is a harmless no-op.  On platforms with a real
+		 * outer cache this might either be needed or not,
+		 * depending on where the outer cache sits.
+		 */
 		outer_flush_all();
+
+		/* Disable local coherency by clearing the ACTLR "SMP" bit: */
+		set_auxcr(get_auxcr() & ~(1 << 6));
+
+		/*
+		 * Disable cluster-level coherency by masking
+		 * incoming snoops and DVM messages:
+		 */
+		cci_disable_port_by_cpu(mpidr);
+
+		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+	} else {
+		arch_spin_unlock(&dcscb_lock);
+
+		/*
+		 * Flush the local CPU cache.
+		 *
+		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+		 * a preliminary flush here for those CPUs.  At least, that's
+		 * the theory -- without the extra flush, Linux explodes on
+		 * RTSM (to be investigated).
+		 */
+		flush_cache_louis();
+		set_cr(get_cr() & ~CR_C);
+		flush_cache_louis();
+
+		/* Disable local coherency by clearing the ACTLR "SMP" bit: */
+		set_auxcr(get_auxcr() & ~(1 << 6));
 	}
 
-	/* Disable local coherency by clearing the ACTLR "SMP" bit: */
-	set_auxcr(get_auxcr() & ~(1 << 6));
+	__mcpm_cpu_down(cpu, cluster);
 
 	/* Now we are prepared for power-down, do it: */
 	dsb();
@@ -177,12 +209,17 @@ static void __init dcscb_usage_count_init(void)
 	dcscb_use_count[cpu][cluster] = 1;
 }
 
+extern void dcscb_power_up_setup(unsigned int affinity_level);
+
 static int __init dcscb_init(void)
 {
 	struct device_node *node;
 	unsigned int cfg;
 	int ret;
 
+	if (!cci_probed())
+		return -ENODEV;
+
 	node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
 	if (!node)
 		return -ENODEV;
@@ -195,11 +232,15 @@ static int __init dcscb_init(void)
 	dcscb_usage_count_init();
 
 	ret = mcpm_platform_register(&dcscb_power_ops);
+	if (!ret)
+		ret = mcpm_sync_init(dcscb_power_up_setup);
 	if (ret) {
 		iounmap(dcscb_base);
 		return ret;
 	}
 
+	pr_info("VExpress DCSCB support installed\n");
+
 	/*
 	 * Future entries into the kernel can now go
 	 * through the cluster entry vectors.
diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S
new file mode 100644
index 0000000000..4bb7fbe0f6
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb_setup.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/include/asm/dcscb_setup.S
+ *
+ * Created by:  Dave Martin, 2012-06-22
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+
+ENTRY(dcscb_power_up_setup)
+
+	cmp	r0, #0			@ check affinity level
+	beq	2f
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
+ * already restores that.
+ *
+ * A15/A7 may not require explicit L2 invalidation on reset, dependent
+ * on hardware integration decisions.
+ * For now, this code assumes that L2 is either already invalidated,
+ * or invalidation is not required.
+ */
+
+	b	cci_enable_port_for_self
+
+2:	@ Implementation-specific local CPU setup operations should go here,
+	@ if any.  In this case, there is nothing to do.
+
+	bx	lr
+
+ENDPROC(dcscb_power_up_setup)
-- 
1.8.1.2



From nicolas.pitre at linaro.org  Fri May 24 01:45:11 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 24 May 2013 01:45:11 -0400
Subject: [PATCH 8/8] ARM: vexpress/dcscb: select multi-cluster SMP operations
In-Reply-To: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369374311-21260-9-git-send-email-nicolas.pitre@linaro.org>

When the DCSCB code is successfully probed and initialized, then the
generic MCPM SPM ops should be used as those operations need to be
arbitrated through the MCPM layer.

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 arch/arm/mach-vexpress/dcscb.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 1acc975360..ce3118dc05 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -239,6 +239,8 @@ static int __init dcscb_init(void)
 		return ret;
 	}
 
+	mcpm_smp_set_ops();
+
 	pr_info("VExpress DCSCB support installed\n");
 
 	/*
-- 
1.8.1.2



From shawn.guo at linaro.org  Fri May 24 01:53:41 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 May 2013 13:53:41 +0800
Subject: [PATCH v2 0/2] dma: imx-sdma: add generic DMA device tree
 bindings support
In-Reply-To: <20130524050329.GN30200@intel.com>
References: <1366901008-7593-1-git-send-email-shawn.guo@linaro.org>
 <20130524052903.GE2704@S2101-09.ap.freescale.net>
 <20130524050329.GN30200@intel.com>
Message-ID: <20130524055338.GG2704@S2101-09.ap.freescale.net>

On Fri, May 24, 2013 at 10:33:29AM +0530, Vinod Koul wrote:
> On Fri, May 24, 2013 at 01:29:05PM +0800, Shawn Guo wrote:
> > Vinod,
> > 
> > On Thu, Apr 25, 2013 at 10:43:26PM +0800, Shawn Guo wrote:
> > > Changes since v1:
> > >  * Fix the example typo in bindings doc.  Thanks to Fabio.
> > > 
> > > Shawn Guo (2):
> > >   dma: imx: change enum definitions to macros
> > >   dma: imx-sdma: move to generic device tree bindings
> > 
> > Can you please apply these for 3.11?
> Sorry I was thinking that you will update the patchset based on Arnd last
> comment on (ab)use of macro. Can you fix that & resend

I had a response [1] on that to explain why I think the macro is
being reasonably used there.

Shawn

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/233361/focus=233395



From ebiederm at xmission.com  Fri May 24 01:59:55 2013
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Thu, 23 May 2013 22:59:55 -0700
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <519DCBEF.3090208@asianux.com> (Chen Gang's message of "Thu, 23
 May 2013 15:57:35 +0800")
References: <519DCBEF.3090208@asianux.com>
Message-ID: <877gio3okk.fsf@xmission.com>

Chen Gang <gang.chen at asianux.com> writes:

> The crazy user can unset 'CONFIG_BUG' in menuconfig: "> General setup >
> Configure standard kernel features (expert users) > BUG() Support".
>
> But in fact, we always need it, and quite a few of architectures have
> already implemented it (e.g. alpha, arc, arm, avr32, blackfin, cris,
> frv, ia64, m68k, mips, mn10300, parisc, powerpc, s390, sh, sparc, x86).
>
> And kernel also already has prepared a default effective implementation
> for the architectures which is unwilling to implement it by themselves
> (e.g. arm64, c6x, h8300, hexagon, m32r, metag, microblaze, openrisc,
> score, tile, um, unicore32, xtensa).
>
> So need get rid of 'CONFIG_BUG', and let it always enabled everywhere.


This looks like the right way to handle this to me.  If the BUG
annotations are too big and not needed they should simply be deleted
from the code base.  Disabling CONFIG_BUG which removes the BUG
annotations from the binaries without modifying the source code seems
like the wrong approach.

Acked-by: "Eric W. Biederman" <ebiederm at xmission.com>


From vinod.koul at intel.com  Fri May 24 01:32:23 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Fri, 24 May 2013 11:02:23 +0530
Subject: [PATCH v2 0/2] dma: imx-sdma: add generic DMA device tree
 bindings support
In-Reply-To: <20130524055338.GG2704@S2101-09.ap.freescale.net>
References: <1366901008-7593-1-git-send-email-shawn.guo@linaro.org>
 <20130524052903.GE2704@S2101-09.ap.freescale.net>
 <20130524050329.GN30200@intel.com>
 <20130524055338.GG2704@S2101-09.ap.freescale.net>
Message-ID: <20130524053223.GQ30200@intel.com>

On Fri, May 24, 2013 at 01:53:41PM +0800, Shawn Guo wrote:
> On Fri, May 24, 2013 at 10:33:29AM +0530, Vinod Koul wrote:
> > On Fri, May 24, 2013 at 01:29:05PM +0800, Shawn Guo wrote:
> > > Vinod,
> > > 
> > > On Thu, Apr 25, 2013 at 10:43:26PM +0800, Shawn Guo wrote:
> > > > Changes since v1:
> > > >  * Fix the example typo in bindings doc.  Thanks to Fabio.
> > > > 
> > > > Shawn Guo (2):
> > > >   dma: imx: change enum definitions to macros
> > > >   dma: imx-sdma: move to generic device tree bindings
> > > 
> > > Can you please apply these for 3.11?
> > Sorry I was thinking that you will update the patchset based on Arnd last
> > comment on (ab)use of macro. Can you fix that & resend
> 
> I had a response [1] on that to explain why I think the macro is
> being reasonably used there.
I see the reason for this. Arnd replied to me only. I think an honest mistake.
Here are his comments


> > Looks fine to me, Arnd?
> 
> I still think that the move of the numbers to include/dt-bindings/dma/imx.h
> is abuse of the preprocessor infrastructure and should not be there.
> The actual binding looks fine though.
> 
> 	Arnd
> 
What I didnt realize that it was not on list and you havent seen it.

Can you fix this up and resend...


--
~Vinod
> 


From linus.walleij at linaro.org  Fri May 24 02:20:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 08:20:38 +0200
Subject: [PATCH 5/6] crypto: ux500/cryp - Enable DT probing of the driver
In-Reply-To: <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
 <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZHT0g_Agtug6jC3rU+DYKOpmwqZ9eQAkRGRw5Kj0wW4A@mail.gmail.com>

On Thu, May 16, 2013 at 1:27 PM, Lee Jones <lee.jones at linaro.org> wrote:

> By providing an OF match table with a suitable compatible string, we
> can ensure the ux500-crypt driver is probed by supplying an associated
> DT node in a given platform's Device Tree.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: linux-crypto at vger.kernel.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Herbert, can I have your ACK on patch 5 & 6 in this series to take it
through the ARM SoC tree?

Yours,
Linus Walleij


From herbert at gondor.apana.org.au  Fri May 24 02:21:10 2013
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Fri, 24 May 2013 14:21:10 +0800
Subject: [PATCH 5/6] crypto: ux500/cryp - Enable DT probing of the driver
In-Reply-To: <CACRpkdZHT0g_Agtug6jC3rU+DYKOpmwqZ9eQAkRGRw5Kj0wW4A@mail.gmail.com>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
 <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZHT0g_Agtug6jC3rU+DYKOpmwqZ9eQAkRGRw5Kj0wW4A@mail.gmail.com>
Message-ID: <20130524062110.GA32684@gondor.apana.org.au>

On Fri, May 24, 2013 at 08:20:38AM +0200, Linus Walleij wrote:
> On Thu, May 16, 2013 at 1:27 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > By providing an OF match table with a suitable compatible string, we
> > can ensure the ux500-crypt driver is probed by supplying an associated
> > DT node in a given platform's Device Tree.
> >
> > Cc: Herbert Xu <herbert at gondor.apana.org.au>
> > Cc: linux-crypto at vger.kernel.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Herbert, can I have your ACK on patch 5 & 6 in this series to take it
> through the ARM SoC tree?

Sure,

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>

Thanks,
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From linus.walleij at linaro.org  Fri May 24 02:26:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 08:26:04 +0200
Subject: [PATCH 5/6] crypto: ux500/cryp - Enable DT probing of the driver
In-Reply-To: <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
 <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbfCyUNevTWzW5JzPoOY83j2vPgcPNg_hU=SDMp1GX-0g@mail.gmail.com>

On Thu, May 16, 2013 at 1:27 PM, Lee Jones <lee.jones at linaro.org> wrote:

> By providing an OF match table with a suitable compatible string, we
> can ensure the ux500-crypt driver is probed by supplying an associated
> DT node in a given platform's Device Tree.
>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> Cc: linux-crypto at vger.kernel.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/crypto/ux500/cryp/cryp_core.c |    6 ++++++

W00t! No binding document?

OK I guess it's just reg, irq ... but still it's compulsory,
right?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 02:27:52 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 08:27:52 +0200
Subject: [PATCH 0/6] crypto: ux500/[cryp|hash] - Enable Device Tree
In-Reply-To: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdapJ4Y0fxHa_j0WaOtWEom3y+bv2aA3qVBnLBjHsB2tOA@mail.gmail.com>

On Thu, May 16, 2013 at 1:27 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch-set simply allows ux500-[cryp|hash] drivers to be probed
> when Snowball is running with Device Tree enabled.
>
> Linus,
>
> Feel free to split the DTS changes out into your ux500-devicetree branch.

I have tentatively applied 1, 2, 3 & 4 to my device tree branch.

5 & 6 need bindings and ACKs.

I can merge them through the ux500 devicetree branch as well I
think, they "should" be orthogonal to other (DMA-related) changes
AFAICT.

Yours,
Linus Walleij


From linus.walleij at stericsson.com  Fri May 24 02:48:42 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 24 May 2013 08:48:42 +0200
Subject: [PATCH] ARM: ux500: enable the crypto and hash on all dbx500
Message-ID: <1369378122-25897-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Commits:
"ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
"ARM: ux500: Add Device Tree nodes for the ux500 Hash device"

Added the crypto and hash devices conditionally, i.e. so as to
be turned on per-board by setting an "status" property on the
device from "disabled" to "okay" on each device.

This is wrong since this is an SoC feature, it is not board
dependent. It is the same ASIC under all circumstances and
functionality does not vary with board family.

This moves the enablement into the SoC file.

Cc: Lee Jones <lee.jones at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi  | 4 ----
 arch/arm/boot/dts/snowball.dts | 8 --------
 2 files changed, 12 deletions(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index f051963..cd5cd09 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -760,17 +760,13 @@
 			compatible = "stericsson,ux500-cryp";
 			reg = <0xa03cb000 0x1000>;
 			interrupts = <0 15 0x4>;
-
 			v-ape-supply = <&db8500_vape_reg>;
-			status = "disabled";
 		};
 
 		hash at a03c2000 {
 			compatible = "stericsson,ux500-hash";
 			reg = <0xa03c2000 0x1000>;
-
 			v-ape-supply = <&db8500_vape_reg>;
-			status = "disabled";
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index bda002f..e8219cc7 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -356,13 +356,5 @@
 				};
 			};
 		};
-
-		cryp at a03cb000 {
-			status = "okay";
-		};
-
-		hash at a03c2000 {
-			status = "okay";
-		};
 	};
 };
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 24 02:58:13 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 24 May 2013 08:58:13 +0200
Subject: [PATCH] ARM: ux500: update defconfig base
Message-ID: <1369378693-27184-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Update the defconfig removing/adding selections due to
Kconfig changes, and select some new hardware drivers that
have been matured in the tree. For example:

- CONFIG_NO_HZ and CONFIG_HIGH_RES_TIMERS come from the
  make oldconfig changes after the recent changes to
  how NOHZ is handled.
- The U5500 config option is now gone as the machine is
  deleted. So is the AB5500 driver.
- CPU_IDLE selected explicitly.
- LP5521 Kconfig has been moved around.
- AB8500 core is default-selected, as is the AB8500 USB
  transciever.
- The battery and charging management drivers for the
  AB8500 are not selected again.
- Select the crypto devices that have been shaped up
  to work properly.

Cc: Lee Jones <lee.jones at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/configs/u8500_defconfig | 28 ++++++++++------------------
 1 file changed, 10 insertions(+), 18 deletions(-)

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index acb62cf..da0614a 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -1,6 +1,7 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
@@ -9,10 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_U8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
-CONFIG_MACH_U5500=y
 CONFIG_MACH_UX500_DT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
@@ -20,6 +18,7 @@ CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_PM_RUNTIME=y
@@ -36,7 +35,6 @@ CONFIG_CAIF=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_AB8500_PWM=y
 CONFIG_SENSORS_BH1780=y
 CONFIG_NETDEVICES=y
 CONFIG_SMSC911X=y
@@ -60,42 +58,33 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_NOMADIK=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_STMPE=y
 CONFIG_GPIO_TC3589X=y
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_AB8500_BM is not set
-# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
-CONFIG_AB5500_CORE=y
-CONFIG_AB8500_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AB8500=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
-# CONFIG_HID_SUPPORT is not set
+CONFIG_REGULATOR_AB8500=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_UX500=y
 CONFIG_USB_PHY=y
+CONFIG_AB8500_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MUSB_HDRC=y
 CONFIG_USB_ETH=m
-CONFIG_AB8500_USB=y
 CONFIG_MMC=y
 CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_LM3530=y
-CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
@@ -115,7 +104,6 @@ CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CONFIGFS_FS=m
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
@@ -129,3 +117,7 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_DEV_UX500=y
+CONFIG_CRYPTO_DEV_UX500_CRYP=y
+CONFIG_CRYPTO_DEV_UX500_HASH=y
+CONFIG_CRYPTO_DEV_UX500_DEBUG=y
-- 
1.7.11.3



From b32955 at freescale.com  Fri May 24 03:16:53 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 15:16:53 +0800
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <201305231509.57651.arnd@arndb.de>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <201305231153.38111.arnd@arndb.de> <20130523115505.GG32299@pengutronix.de>
 <201305231509.57651.arnd@arndb.de>
Message-ID: <519F13E5.2040701@freescale.com>

? 2013?05?23? 21:09, Arnd Bergmann ??:
> OTOH, I agree that it would be nicer if the clk could remain turned
> off as long as no children are active. Can we do a clk_disable()
> after setting up the timings for the children and then expect those
> to actually start up the clk again when they need it?
>
> Or to take things further: would it make sense to represent WEIM
> itself as a clock driver and perform the settings for each child
> only when it sets up its own clk?
>
If the child's subsystem supports it, we can do it.

The mtd nand does support this feature, it has @select_chip() hook.
We can enable/disable the clock in the @select_chip().

But the mtd NOR does _not_ supports it.
Please read the /drivers/mtd/maps/physmap_of.c and 
/drivers/mtd/chips/cfi_cmd_set_xxx.c.
Of course, we can add the feature to NOR subsystem. But that's another 
issue.

So the weim should enable the clock all the time now.


> I guess it would also make sense to use of_platform_populate() instead
> of of_platform_device_create() when creating the children, so we actually
I tried the of_platform_populate(), but failed.

firstly, we should set the timing for the device _before_ we do the 
of_platform_populate().
and i rewrite the weim_parse_dt() to:
------------------------------------------------------------------------------------------
static void weim_parse_dt(struct platform_device *pdev)
{
     struct device_node *child;

     for_each_child_of_node(pdev->dev.of_node, child) {
         if (!child->name)
             continue;

         if (weim_timing_setup(pdev, child)) {
             dev_err(&pdev->dev, "%s set timing failed.\n",
                 child->full_name);
             continue;
         }

     }
     if (!of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev))
         dev_err(&pdev->dev, "%s device create failed.\n",
             child->full_name);
}
------------------------------------------------------------------------------------------

The system hang at :
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

## Booting kernel from Legacy Image at 10800000 ...
    Image Name:   Linux
    Image Type:   ARM Linux Kernel Image (uncompressed)
    Data Size:    4259851 Bytes =  4.1 MB
    Load Address: 10008000
    Entry Point:  10008000
    Verifying Checksum ... OK
    Loading Kernel Image ... OK
OK

Starting kernel ...
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++==



thanks
Huang Shijie






From Wenyou.Yang at atmel.com  Fri May 24 03:11:04 2013
From: Wenyou.Yang at atmel.com (Yang, Wenyou)
Date: Fri, 24 May 2013 07:11:04 +0000
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <20130522001457.GA18614@n2100.arm.linux.org.uk>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
Message-ID: <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>



> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: 2013?5?22? 8:15
> To: Yang, Wenyou
> Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> plagnioj at jcrosoft.com; Ferre, Nicolas; linux at maxim.org.za
> Subject: Re: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
> "MT_MEMORY_SO"
> 
> On Mon, May 20, 2013 at 09:06:19AM +0800, Wenyou Yang wrote:
> > Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
> 
> This needs more of a description.  Also, for a single patch, it's silly
> to send two mails, the first being a cover which has a little more
> information in it about the patch than the patch itself.
> 
> You need to explain _why_ you're making this change.  What I want to see
> is that you've thought about the implications of this - particularly that
> you know that strongly ordered memory does *not* imply any ordering with
> any other memory types.
> 
> In other words, I want to know that this change is not a bodge but there's
> a real reason behind it.
The story is: for sama5d3x with Cortex-A5 core, if not so, when copying code snippet to the internal SRAM, then jump to run this code, but fail to run.
So, refer to other code(such as omap4), do such change. I also test it on at91sam9 with 926ej-s core.
As what you said, I am digging it. Thank you very much.

Best Regards,
Wenyou Yang

From arnd at arndb.de  Fri May 24 03:15:27 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 09:15:27 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523230911.GR18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
Message-ID: <201305240915.27847.arnd@arndb.de>

On Friday 24 May 2013, Russell King - ARM Linux wrote:
> No, I'm not asking about the principle.  I'm asking _in this particular
> problem case_ who provides the DT blob?
> 
> So the person to answer that question is Thomas or someone who is using
> the boards concerned.

But there is no problem on those boards /yet/. So far, the two boards
always come with the known 0xd0 configuration that match the DTs
we have, independent of where they come from.

Thomas wants to be prepared for them to do something stupid, and he
anticipates that they are going to do it in a particular way, but
he says that he has no control over them, so it's all speculation
at this point, unless we do something stupid and change the dts
files in the kernel to no longer match the current hardware.

	Arnd


From s.hauer at pengutronix.de  Fri May 24 03:19:56 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 24 May 2013 09:19:56 +0200
Subject: [PATCH V2 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <519F13E5.2040701@freescale.com>
References: <1369296978-7669-1-git-send-email-b32955@freescale.com>
 <201305231153.38111.arnd@arndb.de>
 <20130523115505.GG32299@pengutronix.de>
 <201305231509.57651.arnd@arndb.de> <519F13E5.2040701@freescale.com>
Message-ID: <20130524071956.GY32299@pengutronix.de>

On Fri, May 24, 2013 at 03:16:53PM +0800, Huang Shijie wrote:
> ? 2013?05?23? 21:09, Arnd Bergmann ??:
> >OTOH, I agree that it would be nicer if the clk could remain turned
> >off as long as no children are active. Can we do a clk_disable()
> >after setting up the timings for the children and then expect those
> >to actually start up the clk again when they need it?
> >
> >Or to take things further: would it make sense to represent WEIM
> >itself as a clock driver and perform the settings for each child
> >only when it sets up its own clk?
> >
> If the child's subsystem supports it, we can do it.
> 
> The mtd nand does support this feature, it has @select_chip() hook.
> We can enable/disable the clock in the @select_chip().
> 
> But the mtd NOR does _not_ supports it.
> Please read the /drivers/mtd/maps/physmap_of.c and
> /drivers/mtd/chips/cfi_cmd_set_xxx.c.
> Of course, we can add the feature to NOR subsystem. But that's
> another issue.
> 
> So the weim should enable the clock all the time now.

Personally I'm fine with this, but you should not disable the clock when
the children are active, so either make sure

- the WEIM driver can't be unloaded, or
- the WEIM driver unregisters its children, or
- just leave the clock enabled.

> ------------------------------------------------------------------------------------------
> 
> The system hang at :
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 
> ## Booting kernel from Legacy Image at 10800000 ...
>    Image Name:   Linux
>    Image Type:   ARM Linux Kernel Image (uncompressed)
>    Data Size:    4259851 Bytes =  4.1 MB
>    Load Address: 10008000
>    Entry Point:  10008000
>    Verifying Checksum ... OK
>    Loading Kernel Image ... OK
> OK
> 
> Starting kernel ...
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++==

Use EARLY_PRINTK or move your driver init to a late_initcall to make it
initialize after the console.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From anish198519851985 at gmail.com  Fri May 24 03:22:40 2013
From: anish198519851985 at gmail.com (anish singh)
Date: Fri, 24 May 2013 12:52:40 +0530
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
Message-ID: <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>

On Fri, May 24, 2013 at 12:41 PM, Mylene Josserand
<Mylene.Josserand at navocap.com> wrote:
> Hi all,
>
>
> I am learning how i2c is working and I read that, to write in an i2c
> register, I need to use the function "i2c_smbus_write_byte_data".
Only in case your device is smbus compliant.

> I wanted to know how the message are handled by using this function. If
> I use this function to talk with 2 different i2d devices, how it will
> handle "message collision" ? should I have to add a kind of mutex on the
Message collision and detection is the job of i2c controller and if I am
not wrong you are writing a chip driver.
> access of the i2c bus ?
> Is it possible that the message destined for one device is sent to
> another one ? Or a "mix" of messages is impossible ?
It is not possible as the data contains the chip address which is
unique.7/10 bit mode addressing is used for addresses.
>
> I have read that this function "i2c_smbus_write_byte_data" uses
> "i2c_smbus_xfer" which uses "i2c_lock_adapter".
> In this function, there is a mutex so I thought that it will handle it
> but it says "Get exclusive access to an I2C bus segment". What is
> exactly an I2C segment ? Is it the device we are talking about ? Or is
> it the use of the i2c bus ?
Don't know what you are referring here.
>
> I will certainly have to create an i2c driver and I would like to know
> if this "collision" handling (if it is handled) is done in old kernel
> (2.6.32) or is it handled only in new kernel versions ?
AFAIK collision handling and detection was not supported till now
in linux kernel until recently but I think this patch is doing that.
I may be wrong but I didn't see collision handling in earlier linux
kernels.
http://thread.gmane.org/gmane.linux.kernel/1410276
>
> If you have any documentation on how the i2c messages are handled in
> case of different devices uses, it will help me a lot ! I will search in
> the kernel documentation but there is many files about i2c.
> And if you know a good i2c driver that I can use as an example to design
> mine, it will be great !
>
>
> Thank you in advance,
>
> --
> Myl?ne JOSSERAND
>
> _______________________________________________
> Kernelnewbies mailing list
> Kernelnewbies at kernelnewbies.org
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies


From jp.francois at cynove.com  Fri May 24 03:31:52 2013
From: jp.francois at cynove.com (jean-philippe francois)
Date: Fri, 24 May 2013 09:31:52 +0200
Subject: [PATCH 0/1] ARM: omap3: Fix regression in dpll4 child clock frequency
 setting.
Message-ID: <CAGGh5h2qtc4CdAeupzZBz2OPoqy3h3Tw8__fR1w1PBwd7vFeGw@mail.gmail.com>

Hi,

The following patch fixes a wrong container_of usage for omap3630.
CAM_MCLK is 216 MHz instead of the asked 172,8 MHz
Any user of this clock is affected. This is the case for instance if
CAM_XCLKA is used to provide clock for an external camera.

All sub clock of dpll4 that do not use a reset value as divider are
also affected.

Beyond wrong frequency setting, this is also a potential oops waiting
to bite any omap3isp user, since a wrong pointer is dereferenced, and
content of this pointer is used to do __raw_writel / __raw_readl.

Regards,
Jean-Philippe Fran?ois


From jp.francois at cynove.com  Fri May 24 03:33:05 2013
From: jp.francois at cynove.com (Jean-Philippe Francois)
Date: Fri, 24 May 2013 09:33:05 +0200
Subject: [PATCH 1/1] ARM : omap3 : fix wrong container_of in clock36xx.c
Message-ID: <1369380785-23374-1-git-send-email-jp.francois@cynove.com>

omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
have parent defined as clk_divider.
Fix the function to use clk_divider. 
Tested with  3.9 on dm3730.

Signed-off-by: Jean-Philippe Fran??ois <jp.francois at cynove.com>

Index: b/arch/arm/mach-omap2/clock36xx.c
===================================================================
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include "clock.h"
 #include "clock36xx.h"
-
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 /**
  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-	struct clk_hw_omap *parent;
+	struct clk_divider *parent;
 	struct clk_hw *parent_hw;
-	u32 dummy_v, orig_v, clksel_shift;
+	u32 dummy_v, orig_v;
 	int ret;
 
 	/* Clear PWRDN bit of HSDIVIDER */
 	ret = omap2_dflt_clk_enable(clk);
 
 	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-	parent = to_clk_hw_omap(parent_hw);
+	parent = to_clk_divider(parent_hw);
 
 	/* Restore the dividers */
 	if (!ret) {
-		clksel_shift = __ffs(parent->clksel_mask);
-		orig_v = __raw_readl(parent->clksel_reg);
+		orig_v = __raw_readl(parent->reg);
 		dummy_v = orig_v;
 
 		/* Write any other value different from the Read value */
-		dummy_v ^= (1 << clksel_shift);
-		__raw_writel(dummy_v, parent->clksel_reg);
+		dummy_v ^= (1 << parent->shift);
+		__raw_writel(dummy_v, parent->reg);
 
 		/* Write the original divider */
-		__raw_writel(orig_v, parent->clksel_reg);
+		__raw_writel(orig_v, parent->reg);
 	}
 
 	return ret;


From thomas.petazzoni at free-electrons.com  Fri May 24 03:43:13 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 09:43:13 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <201305240915.27847.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
 <201305240915.27847.arnd@arndb.de>
Message-ID: <20130524094313.669ab838@skate>

Dear Arnd Bergmann,

On Fri, 24 May 2013 09:15:27 +0200, Arnd Bergmann wrote:

> But there is no problem on those boards /yet/. So far, the two boards
> always come with the known 0xd0 configuration that match the DTs
> we have, independent of where they come from.
> 
> Thomas wants to be prepared for them to do something stupid, and he
> anticipates that they are going to do it in a particular way, but
> he says that he has no control over them, so it's all speculation
> at this point,

Speculation? The new bootloaders that change the address to 0xf1000000
are already shipping on all new Marvell evaluation platforms, they are
the ones currently available to Marvell customers for their
developments, and I'm running such a new bootloader on an evaluation
board.

I wouldn't call speculation something that I have in front of my eyes
today. But maybe we don't have the same definition of speculation.

> unless we do something stupid and change the dts
> files in the kernel to no longer match the current hardware.

You are again making the same mistake again. You make the association
between a given hardware platform and the location of the internal
registers, but this is completely false. Current OpenBlocks are shipped
with a old bootloader, but new OpenBlocks will most likely be shipped
with a new bootloader, or existing users of OpenBlocks may upgrade
their bootloader. So you can't make the assumption that OpenBlocks ==
old register address.

Again, we do *NOT* want to make this address configurable. All boards
should use 0xf1000000, and the kernel should assume that this a fixed
location for the internal registers.

All what we're trying to achieve here is to provide some temporary
workaround to help people using old bootloaders move smoothly to newer
bootloaders version without having a completely silent kernel at boot
time in the mean time.

So, while we are seeking for a workaround for a mistake of the past,
you are trying to force us to generalize the mechanism of customizing
the internal register address, which we do not want to do.

If all you're willing to accept is a very complex generalization of the
internal register base address handling, then I believe what we're
going to do is just move all Device Tree sources to use 0xf1, and we'll
tell users to upgrade their bootloader.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From khali at linux-fr.org  Fri May 24 03:44:07 2013
From: khali at linux-fr.org (Jean Delvare)
Date: Fri, 24 May 2013 09:44:07 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
Message-ID: <20130524094407.61d0ec42@endymion.delvare>

Hi Anish, Myl?ne,

On Fri, 24 May 2013 12:52:40 +0530, anish singh wrote:
> On Fri, May 24, 2013 at 12:41 PM, Mylene Josserand
> <Mylene.Josserand at navocap.com> wrote:
> > I have read that this function "i2c_smbus_write_byte_data" uses
> > "i2c_smbus_xfer" which uses "i2c_lock_adapter".
> > In this function, there is a mutex so I thought that it will handle it
> > but it says "Get exclusive access to an I2C bus segment". What is
> > exactly an I2C segment ? Is it the device we are talking about ? Or is
> > it the use of the i2c bus ?
> Don't know what you are referring here.

In the most simple case, your I2C bus has a single segment so "segment"
or "bus" mean the same thing.

It only starts mattering when I2C bus multiplexing comes into play.
Then your bus is split into segments, with one segment (trunk) between
the master (controller) and the multiplexer, and one or more segments
(branches) hanging off the multiplexer.

Take look at
https://i2c.wiki.kernel.org/index.php/I2C_bus_multiplexing
for a sample topology.

But anyway the comment in front of i2c_lock_adapter() is somewhat
misleading. If you read the code you'll see that it always locks the
whole bus tree, because it uses the root segment's mutex.

> > I will certainly have to create an i2c driver and I would like to know
> > if this "collision" handling (if it is handled) is done in old kernel
> > (2.6.32) or is it handled only in new kernel versions ?
> AFAIK collision handling and detection was not supported till now
> in linux kernel until recently but I think this patch is doing that.
> I may be wrong but I didn't see collision handling in earlier linux
> kernels.
> http://thread.gmane.org/gmane.linux.kernel/1410276

This is for a specific case. The general case is handled by the
per-adapter mutex for years now. 2.6.32 should be just fine in this
respect.

> > If you have any documentation on how the i2c messages are handled in
> > case of different devices uses, it will help me a lot ! I will search in
> > the kernel documentation but there is many files about i2c.
> > And if you know a good i2c driver that I can use as an example to design
> > mine, it will be great !

Best is to look at a driver for a device which is similar in
functionality to yours.

-- 
Jean Delvare


From linus.walleij at linaro.org  Fri May 24 03:44:55 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 09:44:55 +0200
Subject: [PATCH] ARM: ux500: Only configure wake-up reasons on ux500 based
 platforms
In-Reply-To: <1368702935-25599-1-git-send-email-lee.jones@linaro.org>
References: <1368702935-25599-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZjC7nFxsWkED6FvCOxdA1oQVuB+Tz8DZWM+iQDi6zjWA@mail.gmail.com>

On Thu, May 16, 2013 at 1:15 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Multiplatform calls all enabled platforms' initcalls. In the
> ux500_idle_init() initcall we call into the DBx500-PRCMU which in turn
> executes some ux500 specific register reads/writes. When running on
> some !ux500 platforms this ends up causing a kernel Oops. This patch
> ensures the PRCMU call is only invoked when running on ux500 based
> platforms.
>
> Reported-by: Rob Herring <rob.herring at calxeda.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied for ux500 fixes.

Hm, again and again I get so confused by this, don't you say
"wakeup CAUSE" rather than "wakeup REASON"?

Maybe I don't know the anglo saxon well enough...

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Fri May 24 03:46:16 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 08:46:16 +0100
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on
 Armada 370/XP
In-Reply-To: <201305240915.27847.arnd@arndb.de>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
 <201305240915.27847.arnd@arndb.de>
Message-ID: <20130524074616.GV18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 09:15:27AM +0200, Arnd Bergmann wrote:
> On Friday 24 May 2013, Russell King - ARM Linux wrote:
> > No, I'm not asking about the principle.  I'm asking _in this particular
> > problem case_ who provides the DT blob?
> > 
> > So the person to answer that question is Thomas or someone who is using
> > the boards concerned.
> 
> But there is no problem on those boards /yet/.

Wrong, again.  Thomas has already said there are boot loaders shipping
on boards which have the registers programmed to be at 0xf1xxxxxx _and_
there's boards with boot loaders programmed for 0xd0xxxxxx.

The problem is here TODAY.


From linus.walleij at linaro.org  Fri May 24 03:54:49 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 09:54:49 +0200
Subject: [PATCH v3 2/2] pinctrl: imx: add MVF600 support to imx pinctrl
 framework
In-Reply-To: <1368685224-17915-2-git-send-email-b35083@freescale.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <1368685224-17915-2-git-send-email-b35083@freescale.com>
Message-ID: <CACRpkdao66R2jNoJnJY65iHberorKLe2FXW6BJfDes1fvYmCVg@mail.gmail.com>

On Thu, May 16, 2013 at 8:20 AM, Jingchang Lu <b35083 at freescale.com> wrote:

> On some platforms such as MVF600, offset of mux and pad ctrl register
> may be zero, and the mux_mode and config_val are in one 32-bit register.
> This patch adds support to imx core pinctrl framework to handle these
> cases.
>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   add ZERO_OFFSET_VALID flag to handle register offset from zero on mvf600.
>   add SHARE_MUX_CONF_REG flag to handle mux mode and config value in one 32-bit
> register in mvf600.

Patch applied with Shawn's ACK, thanks!

Yours,
Linus Walleij


From ard.biesheuvel at linaro.org  Fri May 24 04:01:43 2013
From: ard.biesheuvel at linaro.org (Ard Biesheuvel)
Date: Fri, 24 May 2013 10:01:43 +0200
Subject: [PATCH 2/2] ARM: move VFP init to an earlier boot stage
In-Reply-To: <alpine.LFD.2.03.1305231654440.1918@syhkavp.arg>
References: <1369294104-3849-1-git-send-email-ard.biesheuvel@linaro.org>
 <1369294104-3849-2-git-send-email-ard.biesheuvel@linaro.org>
 <20130523084126.GI18614@n2100.arm.linux.org.uk>
 <alpine.LFD.2.03.1305231108500.1918@syhkavp.arg>
 <CAKv+Gu9FDprQtVitu5dojoWqY15s4ytOCxbFUjUnLsX8L92Zag@mail.gmail.com>
 <alpine.LFD.2.03.1305231654440.1918@syhkavp.arg>
Message-ID: <CAKv+Gu-O-ehYLp+yh5c=+d7NPOjqARRWLuidTgyNZP_DS2zaEw@mail.gmail.com>

On 23 May 2013 22:57, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> On Thu, 23 May 2013, Ard Biesheuvel wrote:
>> Currently, the lazy restore is armed even in kernel mode, so it pulls
>> in the userland context if you issue NEON/VFP instructions in kernel
>> mode with the FP unit off. This is probably a side effect of the VFP
>> detection code relying on this code path as well.
>> As kernel_vfp_begin() disarms the lazy restore and takes care of
>> preserving the userland context itself, entering __und_svc because of
>> NEON/VFP instructions should only be allowed in this particular case,
>> i.e., VFP detection and all other instances should BUG() imho
>> (regardless of if we end up doing NEON in the kernel or not). Doing it
>> that way, I don't think there is a reason for keeping additional
>> flags.
>
> The concern is more about VFP instructions that could trigger an
> exception where support code is invoked to emulate that instruction.
>

So perhaps that is where we should draw the line: I am not proposing
supporting arbitrary VFP code in the kernel, just NEON (which does not
bounce and hence does not require the support code). Maybe I should
rename to kernel_neon_begin/kernel_neon_end to reflect that?

Regards,
Ard.


From linus.walleij at linaro.org  Fri May 24 04:04:44 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 10:04:44 +0200
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
In-Reply-To: <519A8A57.9060007@wwwdotorg.org>
References: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
 <519A8A57.9060007@wwwdotorg.org>
Message-ID: <CACRpkdZieCmFnHCGUkv8EqcAtb3DA7dSZpimSdB4P81tZPJRoQ@mail.gmail.com>

On Mon, May 20, 2013 at 10:40 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:

> This seems fine on the surface, but I do have one question:
>
> I think the pinctrl lock serves a couple of purposes:
>
> 1) Basic protection for accesses to the pinctrldev_list itself.
>
> This patch seems just fine w.r.t. this point.
>
> 2) Preventing pinctrl drivers from being unregistered (and their modules
> unloaded) when some operation is being performed on/to them.

Prevention of module unloading of pin controllers has never
been working properly, as there is no way to release the
pinctrl handles taken by different drivers.

I think that is why most pin controller drivers are bool rather
than tristate.

Currently only pinctrl-single is tristate. Part of me want to
change that to bool, I think it only will work when using the
single with hogs (that will be properly free:ed when unloading
the driver).

Tony: is this really working with non-hogs?

If we really want to support loading/unloading of pin controllers
I think the mutex is the least of the problems, and we should
probably create a separate lock for handling that instead of
relying on the list lock in that case.

While it's probably possible to *unload* the driver properly
after some hacking like this, we get to the problem of
re-probing the driver and re-associating all pinctrl handles
(at that point floating in space with no driver back-end)
with the driver again.

I feel this needs to be driven by someone who actually
need to load/unload pinctrl modules.

Yours,
Linus Walleij


From thomas.petazzoni at free-electrons.com  Fri May 24 04:07:54 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 10:07:54 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130524074616.GV18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
 <201305240915.27847.arnd@arndb.de>
 <20130524074616.GV18614@n2100.arm.linux.org.uk>
Message-ID: <20130524100754.6b2d1bc9@skate>

Dear Russell King - ARM Linux,

On Fri, 24 May 2013 08:46:16 +0100, Russell King - ARM Linux wrote:

> Wrong, again.  Thomas has already said there are boot loaders shipping
> on boards which have the registers programmed to be at 0xf1xxxxxx _and_
> there's boards with boot loaders programmed for 0xd0xxxxxx.
> 
> The problem is here TODAY.

Right. And again, don't expect something like:

 * Board A = 0xd0xxxxxx
 * Board B = 0xf1xxxxxx

Depending on which bootloader, and which version of the bootloader you
run, on a given board, the kernel may be booted with 0xd0 or 0xf1.

And again, again. This 0xd0 was a mistake. We don't want to support
moving forward. The only thing we want to support is 0xf1, nothing else.

All the proposal is about a temporary workaround, just to make the
transition smoother.

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From l.stach at pengutronix.de  Fri May 24 04:08:07 2013
From: l.stach at pengutronix.de (Lucas Stach)
Date: Fri, 24 May 2013 10:08:07 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <519E5732.1040800@free-electrons.com>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <201305221305.09579.marex@denx.de> <201305230920.18200.jbe@pengutronix.de>
 <201305231648.17356.marex@denx.de>
 <1369322904.4142.36.camel@weser.hi.pengutronix.de>
 <519E5732.1040800@free-electrons.com>
Message-ID: <1369382887.4117.34.camel@weser.hi.pengutronix.de>

Am Donnerstag, den 23.05.2013, 19:51 +0200 schrieb Alexandre Belloni:
> Hi,
> 
[...]
> >
> > So while we _might_ be able to get the PIO mode to work on the i.MX23
> > there is nothing in the doc stating that it's even meant to work. Even
> > while PIO and DMA mode use the same internal mechanisms, there's still
> > plenty of opportunities of fail in there. After all PIO mode relies on
> > reading a debug register in the course of normal operation.
> >
> > Only more extensive experimentation could show if we are in fact able to
> > make it work, a first shot of using PIO mode on MX23 failed, so it might
> > as well be that Juergens quick fix is correct and we have to disable PIO
> > mode on MX23 altogether. That said please stop slapping the word "hack"
> > over this patch until proven otherwise.
> 
> Still, Fabio and I have been experiencing the one second delay on
> i.mx28. From my experience, it appeared between 3.7 and 3.9, see:
> http://www.spinics.net/lists/linux-i2c/msg11985.html. I still didn't
> take the time to investigate more yet but it confirms that PIO mode is
> working on i.mx28 though with an annoying delay.
> 

Just for the record: I know that PIO mode is functional on i.MX28
because I have it working on one of our customer boards. I am rather
much surprised it's still not working well for you, but haven't had a
chance to investigate yet. The i.MX28 RM explicitly describes how to
work with the PIO mode, so if it's not working this is bug somewhere.

This thread/patch is about a whole different problem, namely PIO mode
being non-functional on i.MX23. As the i.MX23 RM doesn't describe the
PIO mode, there is no indication that it's even meant to work on this
chip.

Regards,
Lucas
-- 
Pengutronix e.K.                           | Lucas Stach                 |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From maxime.ripard at free-electrons.com  Fri May 24 04:11:56 2013
From: maxime.ripard at free-electrons.com (maxime.ripard at free-electrons.com)
Date: Fri, 24 May 2013 10:11:56 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <201305231531.31376.jbe@pengutronix.de>
References: <519E03B0.1080006@digi.com> <20130523130039.GF8595@lukather>
 <201305231531.31376.jbe@pengutronix.de>
Message-ID: <20130524081156.GA3154@lukather>

Hi Juergen,

On Thu, May 23, 2013 at 03:31:31PM +0200, Juergen Beisert wrote:
> Hi Maxime,
> 
> maxime.ripard at free-electrons.com wrote:
> > On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> > > I'm using an i.MX28 based board with lcd connected with 18bits data bus.
> > > My platform uses 32 bits per pixel:
> > >
> > > 	mxsfb_pdata.default_bpp = 32;
> > > 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
> > >
> > > With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
> > > at HW_LCDIF_CTRL register in function mxsfb_set_par():
> > >
> > > 	case 32:
> > > 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
> > > 		ctrl |= CTRL_SET_WORD_LENGTH(3);
> > > 		switch (host->ld_intf_width) {
> > > 		case STMLCDIF_8BIT:
> > > 			dev_dbg(&host->pdev->dev,
> > > 					"Unsupported LCD bus width mapping\n");
> > > 			return -EINVAL;
> > > 		case STMLCDIF_16BIT:
> > > 		case STMLCDIF_18BIT:
> > > 			/* 24 bit to 18 bit mapping */
> > > 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> > > 					    *  each colour component
> > > 					    */
> > > 			break;
> > > 		case STMLCDIF_24BIT:
> > > 			/* real 24 bit */
> > > 			break;
> > > 		}
> > >
> > > According to the manual, this flag does:
> > > 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
> > > format, such that all RGB 888 data is contained in 24 bits.
> > > 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
> > > actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
> > > 2 bits in each byte do not contain any useful data, and should be
> > > dropped.
> > >
> > > The setting of this flag is producing bad colours with true colour
> > > images (i.e. the Linux penguin is displayed ok, but QT applications
> > > or images displayed with fbv are not).
> > > I believe the setting of this flag is not correct (after all, if my
> > > bpp is 32, then all 24bit colours are useful and dropping the upper
> > > 2 bits is a bad idea).
> > > If I don't set it, then true colour images are displayed correctly.
> > > The only problem is that the Linux penguin is displayed much darker
> > > than usual (correct colours, but darker). Perhaps the 224 colour
> > > format of this image justifies it?
> > >
> > > I noticed the cfa10049 platform also uses the same configuration (18
> > > bits data bus and 32bpp) and was wondering if true colour images are
> > > correctly displayed in this platform with this flag set (for example
> > > with fbv application [1]).
> >
> > I had the exact same problem, and suggested the exact same solution a
> > few weeks back.
> >
> > https://patchwork.kernel.org/patch/2470441/
> >
> > The conclusion of that discussion what that the userspace applications
> > were not honouring the bitfield correctly set by the mxsfb driver, and
> > as such, it was not a bug in the driver.
> >
> > While this is correct, I wonder, now that since we had that same problem
> > in a very short amount of time, if we couldn't set this behaviour
> > dependant of some (dt? kernel argument?) property so that one could
> > customise it anyway he want.
> >
> > Maxime
> 
> i.MX2[3|8]    LCD1       LCD2       LCD3
>               24bit      18bit      18bit
> --------------------------------------------
> LCD_D0         B0         B0         --
> LCD_D1         B1         B1         --
> LCD_D2         B2         B2         B0
> LCD_D3         B3         B3         B1
> LCD_D4         B4         B4         B2
> LCD_D5         B5         B5         B3
> LCD_D6         B6         G0         B4
> LCD_D7         B7         G1         B5
> 
> LCD_D8         G0         G2         --
> LCD_D9         G1         G3         --
> LCD_D10        G2         G4         G0
> LCD_D11        G3         G5         G1
> LCD_D12        G4         R0         G2
> LCD_D13        G5         R1         G3
> LCD_D14        G6         R2         G4
> LCD_D15        G7         R3         G5
> 
> LCD_D16        R0         R4         --
> LCD_D17        R1         R5         --
> LCD_D18        R2                    R0
> LCD_D19        R3                    R1
> LCD_D20        R4                    R2
> LCD_D21        R5                    R3
> LCD_D22        R6                    R4
> LCD_D23        R7                    R5
> 
> Is your display connected like LCD2 or LCD3? LCD3 must still handled like a 24 
> bit display shown in LCD1, while only the LCD2-case is the "24 bit to 18 bit 
> mapping" case.
> 
> At least my current tests with an i.MX23 and a connection like LCD2 are 
> working here with a Qt application. Qt honours the pixel bitfield 
> description. And I'm using the "bits-per-pixel = <32>" and "bus-width = <18>" 
> entries in the device tree.

I'm in the second case, so with the same setup that you have it seems.

Don't get me wrong, I was not saying that the driver was flawed or had a
bug, I understood very well your arguments when I first submitted the
patch. The problem is more for all the userspace applications that don't
honour the bitfield and just look at the color depth used to feed data
to the framebuffer.

I must admit that the ideal case should be that these applications
should be fixed, but it's not realistic.

About QT, let's not use it as an example, the issues I had were probably
some miscompilation on my side, and if you say that it works fine, then
I trust you.

This is also why I suggested a kernel argument to enable a different
"compatibility" mode when you have to deal with these kind of
applications on your system. the pixel bitfield should probably be
changed as well so that applications honouring it are not confused.

Hector's case looks like a different story though.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From linus.walleij at linaro.org  Fri May 24 04:17:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 10:17:12 +0200
Subject: [PATCH 0/3] ARM: ux500: Update defconfigs for MMC
In-Reply-To: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
References: <1369129576-28617-1-git-send-email-ulf.hansson@linaro.org>
Message-ID: <CACRpkda6WYLbNHuVW23mEtQeGfbOZobf_9izeSUppTRdrnv1ag@mail.gmail.com>

On Tue, May 21, 2013 at 11:46 AM, Ulf Hansson <ulf.hansson at linaro.org> wrote:

> This patchset updates the MMC defconfigs in the u8500|u300_defconfig.
>
> Ulf Hansson (3):
>   ARM: ux500: Enable MMC_UNSAFE_RESUME
>   ARM: ux500: Don't use MMC_CLKGATE
>   ARM: ux500: Disable MMC_BLOCK_BOUNCE

Could you please:
- Squash all three into one patch doing all three changes
- Make one patch for ux500 and one for u300

This is because I have different branches for ux500 and u300
so I don't want them to conflict... Doing 6 patches for this seems
a bit too much so 2 should do.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 04:23:14 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 10:23:14 +0200
Subject: [PATCH v4 01/21] sh-pfc: Remove support for platform data
In-Reply-To: <1369138482-5871-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369138482-5871-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <CACRpkdY+9cKqq+NbNhDpGfuJH2ZeO1QSKuzYWhE4rxqpENF_+A@mail.gmail.com>

On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
<laurent.pinchart+renesas at ideasonboard.com> wrote:

> Platform data isn't used, support can thus be removed.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From lee.jones at linaro.org  Fri May 24 04:24:28 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 09:24:28 +0100
Subject: [PATCH] ARM: ux500: Only configure wake-up reasons on ux500
 based platforms
In-Reply-To: <CACRpkdZjC7nFxsWkED6FvCOxdA1oQVuB+Tz8DZWM+iQDi6zjWA@mail.gmail.com>
References: <1368702935-25599-1-git-send-email-lee.jones@linaro.org>
 <CACRpkdZjC7nFxsWkED6FvCOxdA1oQVuB+Tz8DZWM+iQDi6zjWA@mail.gmail.com>
Message-ID: <20130524082428.GO22683@gmail.com>

On Fri, 24 May 2013, Linus Walleij wrote:

> On Thu, May 16, 2013 at 1:15 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > Multiplatform calls all enabled platforms' initcalls. In the
> > ux500_idle_init() initcall we call into the DBx500-PRCMU which in turn
> > executes some ux500 specific register reads/writes. When running on
> > some !ux500 platforms this ends up causing a kernel Oops. This patch
> > ensures the PRCMU call is only invoked when running on ux500 based
> > platforms.
> >
> > Reported-by: Rob Herring <rob.herring at calxeda.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Patch applied for ux500 fixes.
> 
> Hm, again and again I get so confused by this, don't you say
> "wakeup CAUSE" rather than "wakeup REASON"?
> 
> Maybe I don't know the anglo saxon well enough...

The words 'cause' and 'reason' are fairly synonymous and are
interchangeable in a great many situations. You have to be an English
literary Nazi to care enough to work out the semantics, which in case
you hadn't noticed, I'm not. :)

But, credit where credit's due, in this particular instance you are
correct. Feel free to fixup.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From nicolas.ferre at atmel.com  Fri May 24 04:26:41 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 May 2013 10:26:41 +0200
Subject: [PATCH 1/1] ARM: at91: at91sam9n12: move external irq declatation
 to DT
In-Reply-To: <1369349956-22985-1-git-send-email-plagnioj@jcrosoft.com>
References: <1369349956-22985-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <519F2441.4010000@atmel.com>

On 24/05/2013 00:59, Jean-Christophe PLAGNIOL-VILLARD :
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Stacked on at91-3.10-fixes. Thanks.


> ---
>   arch/arm/boot/dts/at91sam9n12.dtsi |    1 +
>   arch/arm/mach-at91/at91sam9n12.c   |    6 ------
>   2 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index 566af32..d864f7a9 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -60,6 +60,7 @@
>   				compatible = "atmel,at91rm9200-aic";
>   				interrupt-controller;
>   				reg = <0xfffff000 0x200>;
> +				atmel,external-irqs = <31>;
>   			};
>
>   			ramc0: ramc at ffffe800 {
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index 13cdbcd..c7d670d1 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -223,13 +223,7 @@ static void __init at91sam9n12_map_io(void)
>   	at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
>   }
>
> -void __init at91sam9n12_initialize(void)
> -{
> -	at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
> -}
> -
>   AT91_SOC_START(at91sam9n12)
>   	.map_io = at91sam9n12_map_io,
>   	.register_clocks = at91sam9n12_register_clocks,
> -	.init = at91sam9n12_initialize,
>   AT91_SOC_END
>


-- 
Nicolas Ferre


From lee.jones at linaro.org  Fri May 24 04:27:58 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 09:27:58 +0100
Subject: [PATCH] ARM: ux500: enable the crypto and hash on all dbx500
In-Reply-To: <1369378122-25897-1-git-send-email-linus.walleij@stericsson.com>
References: <1369378122-25897-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130524082758.GP22683@gmail.com>

On Fri, 24 May 2013, Linus Walleij wrote:

> From: Linus Walleij <linus.walleij at linaro.org>
> 
> Commits:
> "ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
> "ARM: ux500: Add Device Tree nodes for the ux500 Hash device"
> 
> Added the crypto and hash devices conditionally, i.e. so as to
> be turned on per-board by setting an "status" property on the
> device from "disabled" to "okay" on each device.
> 
> This is wrong since this is an SoC feature, it is not board
> dependent. It is the same ASIC under all circumstances and
> functionality does not vary with board family.
> 
> This moves the enablement into the SoC file.
> 
> Cc: Lee Jones <lee.jones at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/dbx5x0.dtsi  | 4 ----
>  arch/arm/boot/dts/snowball.dts | 8 --------
>  2 files changed, 12 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
> index f051963..cd5cd09 100644
> --- a/arch/arm/boot/dts/dbx5x0.dtsi
> +++ b/arch/arm/boot/dts/dbx5x0.dtsi
> @@ -760,17 +760,13 @@
>  			compatible = "stericsson,ux500-cryp";
>  			reg = <0xa03cb000 0x1000>;
>  			interrupts = <0 15 0x4>;
> -

Why do you insist on removing all line spacings from the DTS file?

I saw you removing them in between nodes too.

>  			v-ape-supply = <&db8500_vape_reg>;
> -			status = "disabled";
>  		};
>  
>  		hash at a03c2000 {
>  			compatible = "stericsson,ux500-hash";
>  			reg = <0xa03c2000 0x1000>;
> -
>  			v-ape-supply = <&db8500_vape_reg>;
> -			status = "disabled";
>  		};
>  	};
>  };
> diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
> index bda002f..e8219cc7 100644
> --- a/arch/arm/boot/dts/snowball.dts
> +++ b/arch/arm/boot/dts/snowball.dts
> @@ -356,13 +356,5 @@
>  				};
>  			};
>  		};
> -
> -		cryp at a03cb000 {
> -			status = "okay";
> -		};
> -
> -		hash at a03c2000 {
> -			status = "okay";
> -		};
>  	};
>  };

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Fri May 24 04:32:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 09:32:31 +0100
Subject: [PATCH 5/6] crypto: ux500/cryp - Enable DT probing of the driver
In-Reply-To: <CACRpkdZHT0g_Agtug6jC3rU+DYKOpmwqZ9eQAkRGRw5Kj0wW4A@mail.gmail.com>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
 <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZHT0g_Agtug6jC3rU+DYKOpmwqZ9eQAkRGRw5Kj0wW4A@mail.gmail.com>
Message-ID: <20130524083231.GQ22683@gmail.com>

On Fri, 24 May 2013, Linus Walleij wrote:

> On Thu, May 16, 2013 at 1:27 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > By providing an OF match table with a suitable compatible string, we
> > can ensure the ux500-crypt driver is probed by supplying an associated
> > DT node in a given platform's Device Tree.
> >
> > Cc: Herbert Xu <herbert at gondor.apana.org.au>
> > Cc: linux-crypto at vger.kernel.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Herbert, can I have your ACK on patch 5 & 6 in this series to take it
> through the ARM SoC tree?

Right, there are no bindings, so they don't need a document.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From nicolas.ferre at atmel.com  Fri May 24 04:51:50 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 May 2013 10:51:50 +0200
Subject: [PATCH] at91: sama5: fix incorrect PMC pcr div definition
In-Reply-To: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>
References: <1369304328-11442-1-git-send-email-josh.wu@atmel.com>
Message-ID: <519F2A26.3080907@atmel.com>

On 23/05/2013 12:18, Josh Wu :
>
> Signed-off-by: Josh Wu <josh.wu at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

And stacked on top of at91-3.10-fixes.

Thanks for catching this! Bye.

> ---
>   arch/arm/mach-at91/include/mach/at91_pmc.h |    6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
> index 31df120..2bd7f51 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> @@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base;
>   #define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command (read=0, write=1) */
>   #define		AT91_PMC_PCR_DIV(n)	((n)  <<  16)		/* Divisor Value */
>   #define			AT91_PMC_PCR_DIV0	0x0			/* Peripheral clock is MCK */
> -#define			AT91_PMC_PCR_DIV2	0x2			/* Peripheral clock is MCK/2 */
> -#define			AT91_PMC_PCR_DIV4	0x4			/* Peripheral clock is MCK/4 */
> -#define			AT91_PMC_PCR_DIV8	0x8			/* Peripheral clock is MCK/8 */
> +#define			AT91_PMC_PCR_DIV2	0x1			/* Peripheral clock is MCK/2 */
> +#define			AT91_PMC_PCR_DIV4	0x2			/* Peripheral clock is MCK/4 */
> +#define			AT91_PMC_PCR_DIV8	0x3			/* Peripheral clock is MCK/8 */
>   #define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
>
>   #endif
>


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Fri May 24 04:52:31 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 May 2013 10:52:31 +0200
Subject: [PATCH] ARM: at91/dt: fix macb pinctrl_macb_rmii_mii_alt
 definition
In-Reply-To: <1369324881-31428-1-git-send-email-b.brezillon@overkiz.com>
References: <1369324881-31428-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <519F2A4F.8080008@atmel.com>

On 23/05/2013 18:01, Boris BREZILLON :
> The PA24 pin is wrongly assigned to peripheral B.
> In the current config there is 2 ETX3 pins (PA11 and PA24) and
> no ETXER pin (PA22).
>
> Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>

Nice catch!

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

and stacked on at91-3.10-fixes and add the stable tag #3.8+

Thanks, bye.

> ---
>   arch/arm/boot/dts/at91sam9260.dtsi |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> index 70b5ccb..84c4bef 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -264,7 +264,7 @@
>   						atmel,pins =
>   							<0 10 0x2 0x0	/* PA10 periph B */
>   							 0 11 0x2 0x0	/* PA11 periph B */
> -							 0 24 0x2 0x0	/* PA24 periph B */
> +							 0 22 0x2 0x0	/* PA22 periph B */
>   							 0 25 0x2 0x0	/* PA25 periph B */
>   							 0 26 0x2 0x0	/* PA26 periph B */
>   							 0 27 0x2 0x0	/* PA27 periph B */
>


-- 
Nicolas Ferre


From linus.walleij at linaro.org  Fri May 24 04:52:42 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 10:52:42 +0200
Subject: [PATCH v4 02/21] sh-pfc: Add DT support
In-Reply-To: <1369138482-5871-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369138482-5871-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <CACRpkdZNv5AO48Bmquyr8mBQvgjBMCk3Ob8ngutSq8RV1HFT0w@mail.gmail.com>

On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
<laurent.pinchart+renesas at ideasonboard.com> wrote:

> Support device instantiation through the device tree. The compatible
> property is used to select the SoC pinmux information.
>
> Set the gpio_chip device field to the PFC device to enable automatic
> GPIO OF support.
>
> Cc: devicetree-discuss at lists.ozlabs.org
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
(...)

(Again I'm rather nervous about all the device tree binding reviewing being
dropped in the lap of Linux subsystem maintainers and then expecting them
to be good and OS-neutral... Not your fault though.)

> +Pin Configuration Node Properties:
> +
> +- renesas,pins : An array of strings, each string containing the name of a pin.
> +- renesas,groups : An array of strings, each string containing the name of a pin
> +  group.
> +
> +- renesas,function: A string containing the name of the function to mux to the
> +  pin group(s) specified by the renesas,groups property
> +
> +  Valid values for pin, group and function names can be found in the group and
> +  function arrays of the PFC data file corresponding to the SoC
> +  (drivers/pinctrl/sh-pfc/pfc-*.c)
> +
> +- renesas,pull-up: An integer representing the pull-up strength to be applied
> +  to all pins specified by the renesas,pins and renesas-groups properties.
> +  0 disables the pull-up, 1 enables it. Other values should not be used.

Then just use a boolean.

> +- renesas,pull-down: An integer representing the pull-down strength to be
> +  applied to all pins specified by the renesas,pins and renesas-groups
> +  properties. 0 disables the pull-down, 1 enables it. Other values should not
> +  be used.

Just use a boolean oneliner then.

But I prefer that you define something really generic in
Documentation/devicetree/bindings/pinconf.txt for anyone using
generic pin config, then reference that.

This way we can have a more general config binding for any system
using generic pin config, mapping to the configs we have in
<linux/pinctrl/pinconf-generic.h>

The upside is that we could move the pinconf generic parsing code
to drivers/pinctrl/pinconf-generic.c and thus avoid code duplication.

We have so far not tried much to standardize pinctrl bindings, but
this would be a good opportunity.

> +On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
> +node.
> +
> +Required Properties:
> +
> +  - gpio-controller: Marks the device node as a gpio controller.
> +
> +  - #gpio-cells: Should be 2. The first cell is the pin number and the second
> +    cell is used to specify optional parameters as bit flags. Only the GPIO
> +    active low flag (bit 0) is currently supported.


I suggest these properties shall be defined in an include file using that new
include hierarchy, since you're using pinconf generic.

include/dt-bindings/gpio/gpio.h
Referenced by <dt-bindings/gpio/gpio.h> in the .dts[i] files.

In Linux-next you find how tegra machines and the imx6sl DTs have
started to use this facility for symbolic names.

And for that you should reference
<dt-bindings/gpio/gpio.h>

Use the symbolic names GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW
here.

(...)
> +Example 2: A GPIO LED node that references a GPIO
> +
> +       leds {
> +               compatible = "gpio-leds";
> +               led1 {
> +                       gpios = <&pfc 20 1>; /* Active low */


#include <dt-bindings/gpio/gpio.h>
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;

(...)
> +Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
> +           for the MMCIF and SCIFA4 devices
> +
> +       &pfc {
> +               pinctrl-0 = <&scifa4_pins>;
> +               pinctrl-names = "default";
> +
> +               mmcif_pins: mmcif {
> +                       mux {
> +                               renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
> +                               renesas,function = "mmc0";
> +                       };
> +                       cfg {
> +                               renesas,groups = "mmc0_data8_0";
> +                               renesas,pins = "PORT279";
> +                               renesas,pull-up = <1>;

Just
renesas,pull-up;

Or go for the generic pinconf binding I'm suggesting.
Then I guess it'd be something like:

pinconf-bias-pull-up;

(Quite readable.)

(...)
> +++ b/drivers/pinctrl/sh-pfc/pinctrl.c
> +static const struct sh_pfc_config_param sh_pfc_config_params[] = {
> +       { "renesas,pull-up", PIN_CONFIG_BIAS_PULL_UP },
> +       { "renesas,pull-down", PIN_CONFIG_BIAS_PULL_DOWN },
> +};

So these should be checked as booleans instead:

> +       for (i = 0; i < ARRAY_SIZE(sh_pfc_config_params); ++i) {
> +               const struct sh_pfc_config_param *param =
> +                       &sh_pfc_config_params[i];
> +               unsigned long config;
> +               u32 val;
> +
> +               ret = of_property_read_u32(np, param->name, &val);

of_property_read_bool()

Though I much rather like this code added as helper lib
in pinconf-generic.c. Use drivers/pinctrl/pinconf.h for
API.

Yours,
Linus Walleij


From maxime.ripard at free-electrons.com  Fri May 24 04:53:33 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 10:53:33 +0200
Subject: [PATCH 2/2] ARM: sunxi: irqchip: Update the configuration
In-Reply-To: <1369385613-8166-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369385613-8166-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369385613-8166-2-git-send-email-maxime.ripard@free-electrons.com>

A10 and A13 have a different set of available interrupt sources, reflect
this in the documentation.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../interrupt-controller/allwinner,sun4i-ic.txt    | 87 +--------------------
 .../interrupt-controller/sunxi/sun4i-a10.txt       | 89 ++++++++++++++++++++++
 .../interrupt-controller/sunxi/sun5i-a13.txt       | 55 +++++++++++++
 3 files changed, 146 insertions(+), 85 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index e7f4dc1..57edb30 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -8,91 +8,8 @@ Required properties:
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source. The value shall be 1.
 
-The interrupt sources are as follows:
-
-0: ENMI
-1: UART0
-2: UART1
-3: UART2
-4: UART3
-5: IR0
-6: IR1
-7: I2C0
-8: I2C1
-9: I2C2
-10: SPI0
-11: SPI1
-12: SPI2
-13: SPDIF
-14: AC97
-15: TS
-16: I2S
-17: UART4
-18: UART5
-19: UART6
-20: UART7
-21: KEYPAD
-22: TIMER0
-23: TIMER1
-24: TIMER2
-25: TIMER3
-26: CAN
-27: DMA
-28: PIO
-29: TOUCH_PANEL
-30: AUDIO_CODEC
-31: LRADC
-32: SDMC0
-33: SDMC1
-34: SDMC2
-35: SDMC3
-36: MEMSTICK
-37: NAND
-38: USB0
-39: USB1
-40: USB2
-41: SCR
-42: CSI0
-43: CSI1
-44: LCDCTRL0
-45: LCDCTRL1
-46: MP
-47: DEFEBE0
-48: DEFEBE1
-49: PMU
-50: SPI3
-51: TZASC
-52: PATA
-53: VE
-54: SS
-55: EMAC
-56: SATA
-57: GPS
-58: HDMI
-59: TVE
-60: ACE
-61: TVD
-62: PS2_0
-63: PS2_1
-64: USB3
-65: USB4
-66: PLE_PFM
-67: TIMER4
-68: TIMER5
-69: GPU_GP
-70: GPU_GPMMU
-71: GPU_PP0
-72: GPU_PPMMU0
-73: GPU_PMU
-74: GPU_RSV0
-75: GPU_RSV1
-76: GPU_RSV2
-77: GPU_RSV3
-78: GPU_RSV4
-79: GPU_RSV5
-80: GPU_RSV6
-82: SYNC_TIMER0
-83: SYNC_TIMER1
+For the valid interrupt sources for your SoC, see the documentation in
+sunxi/<soc>.txt
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
new file mode 100644
index 0000000..76b98c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
@@ -0,0 +1,89 @@
+Allwinner A10 (sun4i) interrupt sources
+---------------------------------------
+
+The interrupt sources available for the Allwinner A10 SoC are the
+following one:
+
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: MMC0
+33: MMC1
+34: MMC2
+35: MMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
new file mode 100644
index 0000000..2ec3b5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
@@ -0,0 +1,55 @@
+Allwinner A13 (sun5i) interrupt sources
+---------------------------------------
+
+The interrupt sources available for the Allwinner A13 SoC are the
+following one:
+
+0: ENMI
+2: UART1
+4: UART3
+5: IR
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: MMC0
+33: MMC1
+34: MMC2
+37: NAND
+38: USB OTG
+39: USB EHCI
+40: USB OHCI
+42: CSI
+44: LCDCTRL
+47: DEFEBE
+49: PMU
+53: VE
+54: SS
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May 24 04:53:32 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 10:53:32 +0200
Subject: [PATCH 1/2] ARM: sunxi: Update datasheet documentation
Message-ID: <1369385613-8166-1-git-send-email-maxime.ripard@free-electrons.com>

We have access to more documentation now, especially the user manuals,
so add the links to them, and do so minor comestic changes while we're
at it.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 Documentation/arm/sunxi/README | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 87a1e8f..d9a372d 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -3,17 +3,22 @@ ARM Allwinner SoCs
 
 This document lists all the ARM Allwinner SoCs that are currently
 supported in mainline by the Linux kernel. This document will also
-provide links to documentation and or datasheet for these SoCs.
+provide links to documentation and/or datasheet for these SoCs.
 
 SunXi family
 ------------
+  Linux kernel mach directory: arch/arm/mach-sunxi
 
   Flavors:
-        Allwinner A10 (sun4i)
-                Datasheet       : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
+    * ARM Cortex-A8 based SoCs
+      - Allwinner A10 (sun4i)
+        + Datasheet
+	  http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
+	+ User Manual
+	  http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
 
-        Allwinner A13 (sun5i)
-                Datasheet       : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
-
-  Core: Cortex A8
-  Linux kernel mach directory: arch/arm/mach-sunxi
\ No newline at end of file
+      - Allwinner A13 (sun5i)
+        + Datasheet
+	  http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
+        + User Manual
+	  http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf
-- 
1.8.1.2



From Mylene.Josserand at navocap.com  Fri May 24 04:54:11 2013
From: Mylene.Josserand at navocap.com (Mylene Josserand)
Date: Fri, 24 May 2013 10:54:11 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <20130524094407.61d0ec42@endymion.delvare>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
Message-ID: <CA78C307B8F06747967D122FC656B15398644A@SERVEUR0.nvp.local>

Thanks, both of you, for your answers ! It helps me a lot to understand it !

Le 24/05/2013 09:22, anish singh a ?crit :
 > On Fri, May 24, 2013 at 12:41 PM, Mylene Josserand
 > <Mylene.Josserand at navocap.com>  wrote:
 >> Hi all,
 >>
 >>
 >> I am learning how i2c is working and I read that, to write in an i2c
 >> register, I need to use the function "i2c_smbus_write_byte_data".
 > Only in case your device is smbus compliant.

Ah okay ! And if there are not SMBus compliant, what function I will 
have to use ?
What is it doing if I use this function and that my device is not SMbus 
compliant ? I have some difficulties to understand the differences 
between SMbus and I2C :(


Le 24/05/2013 09:44, Jean Delvare a ?crit :
 > Hi Anish, Myl?ne,
 >
 > On Fri, 24 May 2013 12:52:40 +0530, anish singh wrote:
 >> On Fri, May 24, 2013 at 12:41 PM, Mylene Josserand
 >> <Mylene.Josserand at navocap.com>  wrote:
 >>> I have read that this function "i2c_smbus_write_byte_data" uses
 >>> "i2c_smbus_xfer" which uses "i2c_lock_adapter".
 >>> In this function, there is a mutex so I thought that it will handle it
 >>> but it says "Get exclusive access to an I2C bus segment". What is
 >>> exactly an I2C segment ? Is it the device we are talking about ? Or is
 >>> it the use of the i2c bus ?
 >> Don't know what you are referring here.
 >
 > In the most simple case, your I2C bus has a single segment so "segment"
 > or "bus" mean the same thing.
 >
 > It only starts mattering when I2C bus multiplexing comes into play.
 > Then your bus is split into segments, with one segment (trunk) between
 > the master (controller) and the multiplexer, and one or more segments
 > (branches) hanging off the multiplexer.
 >
 > Take look at
 > https://i2c.wiki.kernel.org/index.php/I2C_bus_multiplexing
 > for a sample topology.
 >
 > But anyway the comment in front of i2c_lock_adapter() is somewhat
 > misleading. If you read the code you'll see that it always locks the
 > whole bus tree, because it uses the root segment's mutex.


Thanks ! I understand now.
In my case, I have 2 segments but if I understand, the bus will not be 
used at the same time.


 >>> I will certainly have to create an i2c driver and I would like to know
 >>> if this "collision" handling (if it is handled) is done in old kernel
 >>> (2.6.32) or is it handled only in new kernel versions ?
 >> AFAIK collision handling and detection was not supported till now
 >> in linux kernel until recently but I think this patch is doing that.
 >> I may be wrong but I didn't see collision handling in earlier linux
 >> kernels.
 >> http://thread.gmane.org/gmane.linux.kernel/1410276
 >
 > This is for a specific case. The general case is handled by the
 > per-adapter mutex for years now. 2.6.32 should be just fine in this
 > respect.

Okay. So the mutex blocks the I2C bus. And is it locking the bus at the 
beginning of a message (so when a START is send) and unlocking it after 
the STOP ?
So a complete message will be sent to a same device (the one which 
address is in the data frame) ? A device can not receive a beginning of 
one message (so with his address) and the end of another message 
destined to another device [because of "collision"], for example ?


 >>> If you have any documentation on how the i2c messages are handled in
 >>> case of different devices uses, it will help me a lot ! I will 
search in
 >>> the kernel documentation but there is many files about i2c.
 >>> And if you know a good i2c driver that I can use as an example to 
design
 >>> mine, it will be great !
 >
 > Best is to look at a driver for a device which is similar in
 > functionality to yours.

I will search that, thanks for the advice.


-- 
Myl?ne JOSSERAND

From lee.jones at linaro.org  Fri May 24 04:54:51 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 09:54:51 +0100
Subject: [PATCH 0/6] ARM: ux500: Update configurations for SD/SDIO/(e)MMC
In-Reply-To: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <20130524085451.GU22683@gmail.com>

On Thu, 23 May 2013, Ulf Hansson wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
> 
> This patchset includes especially enablement for UHS-I SD cards, but
> also some cleanups and additional enabling of SD/SDIO/(e)MMC features.
> 
> These changes shall also be adapted to the corresponding DT files,
> but that is left as a separate task and outside this patchset.
> 
> Ulf Hansson (6):
>   ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices
>   ARM: ux500: Don't set plf ocr mask for SD/MMC device
>   ARM: ux500: Enable support for RPMB and Reliable Write for eMMC
>   ARM: ux500: Enable support for discard for MMC/SD
>   ARM: ux500: Set eMMC and WLAN card slot as non-removable
>   ARM: ux500: Enable support for UHS-I SD-cards
> 
>  arch/arm/mach-ux500/board-mop500-sdi.c |   34 +++++++++++++++++++++-----------
>  1 file changed, 22 insertions(+), 12 deletions(-)
> 

All patches look good to me, although you should probably try to use
the full 72 char limit per line in all of your commit messages.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Fri May 24 04:55:37 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 09:55:37 +0100
Subject: [PATCH 0/6] ARM: ux500: Update configurations for SD/SDIO/(e)MMC
In-Reply-To: <20130524085451.GU22683@gmail.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <20130524085451.GU22683@gmail.com>
Message-ID: <20130524085537.GV22683@gmail.com>

On Fri, 24 May 2013, Lee Jones wrote:

> On Thu, 23 May 2013, Ulf Hansson wrote:
> 
> > From: Ulf Hansson <ulf.hansson at linaro.org>
> > 
> > This patchset includes especially enablement for UHS-I SD cards, but
> > also some cleanups and additional enabling of SD/SDIO/(e)MMC features.
> > 
> > These changes shall also be adapted to the corresponding DT files,
> > but that is left as a separate task and outside this patchset.
> > 
> > Ulf Hansson (6):
> >   ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices
> >   ARM: ux500: Don't set plf ocr mask for SD/MMC device
> >   ARM: ux500: Enable support for RPMB and Reliable Write for eMMC
> >   ARM: ux500: Enable support for discard for MMC/SD
> >   ARM: ux500: Set eMMC and WLAN card slot as non-removable
> >   ARM: ux500: Enable support for UHS-I SD-cards
> > 
> >  arch/arm/mach-ux500/board-mop500-sdi.c |   34 +++++++++++++++++++++-----------
> >  1 file changed, 22 insertions(+), 12 deletions(-)
> > 
> 
> All patches look good to me, although you should probably try to use
> the full 72 char limit per line in all of your commit messages.

Whoops! In case you couldn't tell that was an:

Acked-by: Lee Jones <lee.jones at linaro.org>

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Fri May 24 04:55:53 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 10:55:53 +0200
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <CAAQ0ZWTBZ=10B+0Zc4iZmvrr0hzdBKf1mn1CzhJokWE44dxsoA@mail.gmail.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <20130520033207.GD25113@S2101-09.ap.freescale.net>
 <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>
 <B56CDBE15CE27145A4B77D2D24263E851CBBA4@039-SN1MPN1-003.039d.mgd.msft.net>
 <CAAQ0ZWTBZ=10B+0Zc4iZmvrr0hzdBKf1mn1CzhJokWE44dxsoA@mail.gmail.com>
Message-ID: <CACRpkdZ=67CWrPqFMU4FeES5OUyV5=Zz2fwy-GAMVHrNU6y6jA@mail.gmail.com>

On Wed, May 22, 2013 at 5:24 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On 21 May 2013 15:56, Lu Jingchang-B35083 <B35083 at freescale.com> wrote:
>> [Lu Jingchang-B35083]
>> I see you have Acked [PATCH v3 2/2] pinctrl: imx: add MVF600 support to imx pinctrl framework, do I need resend it as the first one. Thanks!
>
> Since LinusW hasn't applied it, you should just resend.

Now it appears I applied 2/2 but not 1/2 due to comments.

Are they orthogonal or do I need to pull the applied patch out again?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 04:59:50 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 10:59:50 +0200
Subject: [PATCH v4 15/21] ARM: shmobile: armadillo-reference: Move st1232
 reset GPIO to DT
In-Reply-To: <1369138482-5871-16-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369138482-5871-16-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <CACRpkdYUQjtmzFzQBES-bcjjT5iTTXifa2BQSusBzMdTCRtyiA@mail.gmail.com>

On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
<laurent.pinchart+renesas at ideasonboard.com> wrote:

> Reference the st1232 reset GPIO from the device tree and remove it from
> board code.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

> +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
> @@ -43,6 +43,7 @@
>                 interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
>                 pinctrl-0 = <&st1232_pins>;
>                 pinctrl-names = "default";
> +               gpios = <&pfc 166 1>;

Just as a random example this becomes:

gpios = <&pfc 166 GPIO_ACTIVE_LOW>;

Which is WAAAY more readable.

> +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
> @@ -158,7 +158,6 @@ clock_error:
>   */
>  static void __init eva_init(void)
>  {
> -
>         r8a7740_clock_init(MD_CK0 | MD_CK2);
>         eva_clock_init();
>
> @@ -171,12 +170,6 @@ static void __init eva_init(void)
>
>         r8a7740_add_standard_devices_dt();
>
> -       /*
> -        * Touchscreen
> -        * TODO: Move reset GPIO over to .dts when we can reference it
> -        */
> -       gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
> -

Not really my business but I guess the driver is already augmented to pick its
GPIO from the device tree in this case? And are you willingly breaking
non-DT boots or something?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 05:03:36 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 11:03:36 +0200
Subject: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to
 configure multiple pins of different modules
In-Reply-To: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
References: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
Message-ID: <CACRpkdZEsRaaE9dJLDNMzJZSLZ35pqS6XVj5KgCzJGG5nnvPQg@mail.gmail.com>

On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash
<prakash.pm at ti.com> wrote:

> Based function-mask and submask preoperties patch allocates and registers pins.
> Patch is fixes the issue reported and discussed here:
> http://www.spinics.net/lists/arm-kernel/msg235213.html

I'd like Tony to ACK this, and Haojian to have a look at it before applying.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 05:07:41 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 11:07:41 +0200
Subject: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific
 suspend/resume callbacks
In-Reply-To: <1368807872-2601-5-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-5-git-send-email-t.figa@samsung.com>
Message-ID: <CACRpkdY-d3YYLJoWydakbT7P4wnBAK2XL7X0Fs0EcNSFakpUDw@mail.gmail.com>

On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa <t.figa at samsung.com> wrote:

> SoC-specific driver might require additional save and restore of
> registers. This patch adds pair of SoC-specific callbacks per pinctrl
> device to account for this.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Patch applied for fixes.

Hm this is quite a lot of code for "fixes", can you confirm that
the system is really unusable without all these patches?

Yours,
Linus Walleij


From khali at linux-fr.org  Fri May 24 05:07:06 2013
From: khali at linux-fr.org (Jean Delvare)
Date: Fri, 24 May 2013 11:07:06 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <CA78C307B8F06747967D122FC656B15398644A@SERVEUR0.nvp.local>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
 <CA78C307B8F06747967D122FC656B15398644A@SERVEUR0.nvp.local>
Message-ID: <20130524110706.6052493e@endymion.delvare>

On Fri, 24 May 2013 10:54:11 +0200, Mylene Josserand wrote:
> Ah okay ! And if there are not SMBus compliant, what function I will
> have to use ?

i2c_transfer()

> What is it doing if I use this function and that my device is not SMbus 
> compliant ?

This would make no sense. Your device understands only specific message
formats, which should be documented in its datasheet. You have to use
exactly that in your driver. If the message format matches SMBus, you
can use the SMBus API, otherwise you must use i2c_transfer() instead.

> I have some difficulties to understand the differences 
> between SMbus and I2C :(

SMBus is a subset of I2C. With I2C you can have messages of any length
and any format, with no attached semantics. SMBus restricts the
possibilities to a few standardized messages formats with semantics. If
you'd just tell us what your device is, we would be able to tell you if
SMBus will work or if I2C will be needed.

> (...)
> In my case, I have 2 segments but if I understand, the bus will not be 
> used at the same time.

I can't comment on that without knowing the exact topology. In
particular, do you have two independent segments each with its own
controller, or are they interconnected in some way? I2C/SMBus is very
simple with basic topologies but can become difficult with complex ones.

> (...)
> Okay. So the mutex blocks the I2C bus. And is it locking the bus at the 
> beginning of a message (so when a START is send) and unlocking it after 
> the STOP ?

Yes.

> So a complete message will be sent to a same device (the one which 
> address is in the data frame) ? A device can not receive a beginning of 
> one message (so with his address) and the end of another message 
> destined to another device [because of "collision"], for example ?

No, this cannot happen.

-- 
Jean Delvare


From linus.walleij at linaro.org  Fri May 24 05:09:02 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 11:09:02 +0200
Subject: [PATCH 5/6] pinctrl: samsung: Allow per-bank SoC-specific private
 data
In-Reply-To: <1368807872-2601-6-git-send-email-t.figa@samsung.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-6-git-send-email-t.figa@samsung.com>
Message-ID: <CACRpkdZs=fWfi-9U5T-H+mLRJ1T6sn2Zb4UfurSkZYsqX_n9Zg@mail.gmail.com>

On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa <t.figa at samsung.com> wrote:

> This patch extends pin bank descriptor structure with SoC-specific
> private data field that allows SoC-specific drivers to store their own
> private data.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Patch applied for fixes.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 05:12:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 11:12:00 +0200
Subject: [PATCH v3 6/6] pinctrl: exynos: Handle suspend/resume of GPIO
 EINT registers
In-Reply-To: <3059629.yu4Ei1BXhd@amdc1227>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <4536937.hnhaYZLnaG@amdc1227>
 <CAD=FV=VYhBP+V6SQt5SkFZszdVxSJ6AZk-C-zx1Di-RZBYhGvw@mail.gmail.com>
 <3059629.yu4Ei1BXhd@amdc1227>
Message-ID: <CACRpkdbN4Nxg2VSr0bf+h4Y2U=CmX9mijdZz+=tom9V0-i-69g@mail.gmail.com>

On Wed, May 22, 2013 at 4:03 PM, Tomasz Figa <t.figa at samsung.com> wrote:

> Some GPIO EINT control registers needs to be preserved across
> suspend/resume cycle. This patch extends the driver to take care of
> this.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>
> Changes since v2:
>  - Fixed error path
> Changes since v1:
>  - Added optional debugging messages
>  - Added proper error path in initialization

v2 version applied for fixes.

Again confirm you must really have all this. It is not looking
good with diffstats like this for fixing regressions.

Yours,
Linus Walleij


From g.liakhovetski at gmx.de  Fri May 24 05:13:07 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 24 May 2013 11:13:07 +0200 (CEST)
Subject: [PATCH 2/2] ARM: shmobile: irqpin: map spurious interrupts in DT case
In-Reply-To: <Pine.LNX.4.64.1305241109530.1090@axis700.grange>
References: <Pine.LNX.4.64.1305241109530.1090@axis700.grange>
Message-ID: <Pine.LNX.4.64.1305241112210.1090@axis700.grange>

In the non-DT case all interrupts get mapped statically during probing,
therefore, if a spurious interrupt arrives, it can easily be mapped back
to hardware registers and bits and handled. In the DT case interrupts are
mapped only when a device, using that interrupt is instantiated from DT.
So, spurious interrupts occur unmapped and thus cannot be handled properly.
This patch fixes this by mapping such interrupts as they occur.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
---
 drivers/irqchip/irq-renesas-intc-irqpin.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index 82cec63..e62d76d 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -71,6 +71,7 @@ struct intc_irqpin_priv {
 	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
 	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
 	struct renesas_intc_irqpin_config config;
+	unsigned int min_irq;
 	unsigned int number_of_irqs;
 	struct platform_device *pdev;
 	struct irq_chip irq_chip;
@@ -274,6 +275,10 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
 	struct intc_irqpin_priv *p = i->p;
 	unsigned long bit;
 
+	if (!i->domain_irq)
+		/* unmapped: spurious IRQ, map it now */
+		irq_create_mapping(p->irq_domain, irq - p->min_irq);
+
 	intc_irqpin_dbg(i, "demux1");
 	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
 
@@ -372,6 +377,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
 		}
 	}
 
+	p->min_irq = INT_MAX;
 	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
 	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
 		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
@@ -380,6 +386,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
 
 		p->irq[k].p = p;
 		p->irq[k].requested_irq = irq->start;
+		if (p->min_irq > irq->start)
+			p->min_irq = irq->start;
 	}
 
 	p->number_of_irqs = k;
-- 
1.7.2.5



From g.liakhovetski at gmx.de  Fri May 24 05:13:03 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 24 May 2013 11:13:03 +0200 (CEST)
Subject: [PATCH 1/2] ARM: shmobile: irqpin: add a DT property to enable
 masking on parent
Message-ID: <Pine.LNX.4.64.1305241109530.1090@axis700.grange>

To disable spurious interrupts, that get triggered on certain hardware, the
irqpin driver masks them on the parent interrupt controller. To specify
such broken devices a .control_parent parameter can be provided in the
platform data. In the DT case we need a property, to do the same.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
---

These two patches simply split the earlier "ARM: shmobile: irqpin: fix 
handling of spurious interrupts in DT case" patch into two parts. 
Otherwise no change.

 .../interrupt-controller/renesas,intc-irqpin.txt   |    2 ++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    7 +++++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
index c6f09b7..152b10a 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -11,3 +11,5 @@ Optional properties:
   resource allocation properties
 - sense-bitfield-width: width of a single sense bitfield in the SENSE register,
   if different from the default 4 bits
+- control-parent: disable and enable interrupts on the parent interrupt
+  controller, needed for some broken implementations
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index 4aca1b2..82cec63 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -348,11 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev)
 	}
 
 	/* deal with driver instance configuration */
-	if (pdata)
+	if (pdata) {
 		memcpy(&p->config, pdata, sizeof(*pdata));
-	else
+	} else {
 		of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
 				     &p->config.sense_bitfield_width);
+		p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
+								 "control-parent");
+	}
 	if (!p->config.sense_bitfield_width)
 		p->config.sense_bitfield_width = 4; /* default to 4 bits */
 
-- 
1.7.2.5



From arnd at arndb.de  Fri May 24 05:16:58 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 11:16:58 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130524094313.669ab838@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201305240915.27847.arnd@arndb.de> <20130524094313.669ab838@skate>
Message-ID: <201305241116.59116.arnd@arndb.de>

On Friday 24 May 2013, Thomas Petazzoni wrote:
> On Fri, 24 May 2013 09:15:27 +0200, Arnd Bergmann wrote:
> 
> > But there is no problem on those boards /yet/. So far, the two boards
> > always come with the known 0xd0 configuration that match the DTs
> > we have, independent of where they come from.
> > 
> > Thomas wants to be prepared for them to do something stupid, and he
> > anticipates that they are going to do it in a particular way, but
> > he says that he has no control over them, so it's all speculation
> > at this point,
> 
> Speculation? The new bootloaders that change the address to 0xf1000000
> are already shipping on all new Marvell evaluation platforms, they are
> the ones currently available to Marvell customers for their
> developments, and I'm running such a new bootloader on an evaluation
> board.
> 
> I wouldn't call speculation something that I have in front of my eyes
> today. But maybe we don't have the same definition of speculation.

You said earlier yourself that you think the evaluation platforms are
under control because there are only small quantities of them and they
will eventually all move to the new address. I understand that Marvell
screwed up here (actually repeatedly it seems)

> > unless we do something stupid and change the dts
> > files in the kernel to no longer match the current hardware.
> 
> You are again making the same mistake again. You make the association
> between a given hardware platform and the location of the internal
> registers, but this is completely false. Current OpenBlocks are shipped
> with a old bootloader, but new OpenBlocks will most likely be shipped
> with a new bootloader, or existing users of OpenBlocks may upgrade
> their bootloader. So you can't make the assumption that OpenBlocks ==
> old register address.

That is what I meant with speculation: You don't actually know if
OpenBlocks are going to change their boot loader incompatibly, or
in case they do, whether they do it in the same way that Marvell
did or in a different way.

I think it's rather unlikely that a company that has shipped a ton
of machines would force an update on their users that breaks every
single kernel they have running today.

> Again, we do *NOT* want to make this address configurable. All boards
> should use 0xf1000000, and the kernel should assume that this a fixed
> location for the internal registers.

You also said that it didn't matter what you *want* because you have
no control over the boot loaders.

> All what we're trying to achieve here is to provide some temporary
> workaround to help people using old bootloaders move smoothly to newer
> bootloaders version without having a completely silent kernel at boot
> time in the mean time.

I understand that you are trying to do what's best here, but I fear
your workaround is going to make it much worse than it already is.

> So, while we are seeking for a workaround for a mistake of the past,
> you are trying to force us to generalize the mechanism of customizing
> the internal register address, which we do not want to do.

But your approach forces OpenBlocks and others to make the same mistake
that Marvell did by changing their boot loaders in a way that is not
backwards compatible and not detectable in a reliable way (see below).

> If all you're willing to accept is a very complex generalization of the
> internal register base address handling, then I believe what we're
> going to do is just move all Device Tree sources to use 0xf1, and we'll
> tell users to upgrade their bootloader.

Those are two options that would both be better than your current proposal,
but you can probably come up with others. The one thing you must not do
is override the address passed in the boot protocol for all boards based
on an arbitrary non-architecture register setting.

We know that boot loaders are broken all the time. Being able to describe
the breakage correctly in the device tree so the kernel can work around
it is our last line of defence, we have to trust that data.

In your patch, you are effectively encoding the policy that whatever we
find as the internal register address in the DT is meaningless and that
we instead use one of two hardcoded values depending on a bit that
Marvell (who are the ones that screwed this up before) tells you to use
as the interface. You also assume that by some magic you can introduce
the interface now and get everybody to do what you think they should in
the future (i.e. set the internal register to 0xf1 and enable that bit)
so you can remove that hack. I would call that rather optimistic.

What I would expect to see instead is:

* As the interface is now there, some board developers randomly mix
  boot loaders with 0xd0 and 0xf1 and rely on the kernel to use that
  bit for all eternity.

* some other board developers will get the updated u-boot from Marvell
  that sets the bit, but they revert the address back to 0xd0 because
  they want to keep running their old in-house kernels.

* some (slightly crazy) board developers will use their own boot loader
  with the 0xf1 address since Marvell is telling them to use that as
  the new default, but will not set the bit because their in-house kernel
  does not require it.

* at least one (rather crazy) board developers decides that neither 0xd0
  nor 0xf1 is the best base address for their uses and pick something
  completely different. They put the address into their DT following
  the binding and expect the kernel to handle that.

If any of the above happen, your hack will fail and you will have to
build additional hacks on top, instead of getting rid of it.

	Arnd


From t.figa at samsung.com  Fri May 24 05:20:06 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 24 May 2013 11:20:06 +0200
Subject: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific
 suspend/resume callbacks
In-Reply-To: <CACRpkdY-d3YYLJoWydakbT7P4wnBAK2XL7X0Fs0EcNSFakpUDw@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <1368807872-2601-5-git-send-email-t.figa@samsung.com>
 <CACRpkdY-d3YYLJoWydakbT7P4wnBAK2XL7X0Fs0EcNSFakpUDw@mail.gmail.com>
Message-ID: <22452279.DN7eJUzGA7@amdc1227>

Hi Linus,

On Friday 24 of May 2013 11:07:41 Linus Walleij wrote:
> On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa <t.figa at samsung.com> wrote:
> > SoC-specific driver might require additional save and restore of
> > registers. This patch adds pair of SoC-specific callbacks per pinctrl
> > device to account for this.
> > 
> > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> 
> Patch applied for fixes.

Thanks.

> Hm this is quite a lot of code for "fixes", can you confirm that
> the system is really unusable without all these patches?

Well, it is something that should have been already sent as a fix for 3.8, when 
this pin control driver was added, because since then suspend/resume has been 
broken on DT-enabled Exynos boards.

Without this, suspending the board and then trying to wake it up is rather 
unpredictable, leading usually to board reset, interrupt storm or at least 
some devices failing to resume.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics


From maxime.ripard at free-electrons.com  Fri May 24 05:23:08 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:08 +0200
Subject: [PATCHv3 RESEND 0/6] ARM: sunxi: Add support for A10 Ethernet
 controller
Message-ID: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

The Allwinner A10 SoC has an ethernet controller that seem to be specific to
Allwinner. This IP has no public documentation, so exact
details are quite sparse, and this code come from refactored Allwinner
code.

The rework to use NAPI is taking more time than expected, I'm still working
on it, but it could probably be sent as a follow-up patch.

Thanks,
Maxime

Changes from v2:
  - Split the MDIO controller to a separate driver and make use of standards
    device tree bindings
  - Fixed various minor things as suggested by Florian Fainelli
  - Added clock support now that we have a clock driver

Changes from v1:
  - Use phylib for the phy-related functions
  - Use an optional regulator to power up the phy
  - Rename the driver from Davicom Wemac to Allwinner EMAC, since it's the name
    mentionned in the datasheet, and we have no strong evidence of a
    relationship with Davicom
  - Fix various small things around the driver: add defines for undocumented
    values, fix documentation name and compatible example, etc.

Maxime Ripard (4):
  net: Add MDIO bus driver for the Allwinner EMAC
  ARM: sun4i: Add muxing options for the ethernet controller
  ARM: sunxi: Add EMAC controller node to sun4i DTSI
  ARM: sunxi: Add EMAC Controller to Hackberry dt

Stefan Roese (2):
  net: Add EMAC ethernet driver found on Allwinner A10 SoC's
  ARM: cubieboard: Enable ethernet (EMAC) support in dts

 .../bindings/net/allwinner,sun4i-emac.txt          |  22 +
 .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  15 +
 arch/arm/boot/dts/sun4i-a10-hackberry.dts          |  41 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  27 +
 drivers/net/ethernet/Kconfig                       |   1 +
 drivers/net/ethernet/Makefile                      |   1 +
 drivers/net/ethernet/allwinner/Kconfig             |  44 +
 drivers/net/ethernet/allwinner/Makefile            |   6 +
 drivers/net/ethernet/allwinner/sun4i-emac.c        | 960 +++++++++++++++++++++
 drivers/net/ethernet/allwinner/sun4i-emac.h        | 108 +++
 drivers/net/ethernet/allwinner/sun4i-mdio.c        | 191 ++++
 12 files changed, 1442 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
 create mode 100644 drivers/net/ethernet/allwinner/Kconfig
 create mode 100644 drivers/net/ethernet/allwinner/Makefile
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-mdio.c

-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May 24 05:23:10 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:10 +0200
Subject: [PATCHv3 2/6] net: Add MDIO bus driver for the Allwinner EMAC
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369387394-9453-3-git-send-email-maxime.ripard@free-electrons.com>

This patch adds a separate driver for the MDIO interface of the
Allwinner ethernet controllers.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +++
 drivers/net/ethernet/allwinner/Kconfig             |   8 +
 drivers/net/ethernet/allwinner/Makefile            |   1 +
 drivers/net/ethernet/allwinner/sun4i-mdio.c        | 191 +++++++++++++++++++++
 4 files changed, 226 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-mdio.c

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
new file mode 100644
index 0000000..00b9f9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
@@ -0,0 +1,26 @@
+* Allwinner A10 MDIO Ethernet Controller interface
+
+Required properties:
+- compatible: should be "allwinner,sun4i-mdio".
+- reg: address and length of the register set for the device.
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Example at the SoC level:
+mdio at 01c0b080 {
+	compatible = "allwinner,sun4i-mdio";
+	reg = <0x01c0b080 0x14>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+};
+
+And at the board level:
+
+mdio at 01c0b080 {
+	phy-supply = <&reg_emac_3v3>;
+
+	phy0: ethernet-phy at 0 {
+		reg = <0>;
+	};
+};
diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig
index 4220c9a..848b27a 100644
--- a/drivers/net/ethernet/allwinner/Kconfig
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -27,10 +27,18 @@ config SUN4I_EMAC
 	select NET_CORE
 	select MII
 	select REGULATOR_FIXED_VOLTAGE
+	select PHYLIB
         ---help---
           Support for Allwinner A10 EMAC ethernet driver.
 
           To compile this driver as a module, choose M here.  The module
           will be called sun4i-emac.
 
+config SUN4I_MDIO
+	tristate "Allwinner sun4i MDIO interface support"
+	---help---
+	  This driver supports the MDIO interface found in the network
+	  interface units of the Allwinner SoC that have an EMAC (A10,
+	  A12, A10s, etc.)
+
 endif # NET_VENDOR_ALLWINNER
diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile
index 03129f7..95eaa31 100644
--- a/drivers/net/ethernet/allwinner/Makefile
+++ b/drivers/net/ethernet/allwinner/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
+obj-$(CONFIG_SUN4I_MDIO) += sun4i-mdio.o
\ No newline at end of file
diff --git a/drivers/net/ethernet/allwinner/sun4i-mdio.c b/drivers/net/ethernet/allwinner/sun4i-mdio.c
new file mode 100644
index 0000000..00e432c
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sun4i-mdio.c
@@ -0,0 +1,191 @@
+/*
+ * Allwinner EMAC MDIO interface driver
+ *
+ * Copyright 2012-2013 Stefan Roese <sr at denx.de>
+ * Copyright 2013 Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997  Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#define EMAC_MAC_MCMD_REG	(0x00)
+#define EMAC_MAC_MADR_REG	(0x04)
+#define EMAC_MAC_MWTD_REG	(0x08)
+#define EMAC_MAC_MRDD_REG	(0x0c)
+#define EMAC_MAC_MIND_REG	(0x10)
+#define EMAC_MAC_SSRR_REG	(0x14)
+
+#define MDIO_TIMEOUT		(msecs_to_jiffies(100))
+
+struct sun4i_mdio_data {
+	void __iomem		*membase;
+	struct regulator	*regulator;
+};
+
+static int sun4i_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct sun4i_mdio_data *data = bus->priv;
+	unsigned long start_jiffies;
+	int value;
+
+	/* issue the phy address and reg */
+	writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
+	/* pull up the phy io line */
+	writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
+
+	/* Wait read complete */
+	start_jiffies = jiffies;
+	while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
+		if (time_after(start_jiffies,
+			       start_jiffies + MDIO_TIMEOUT))
+			return -ETIMEDOUT;
+		msleep(1);
+	}
+
+	/* push down the phy io line */
+	writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
+	/* and read data */
+	value = readl(data->membase + EMAC_MAC_MRDD_REG);
+
+	return value;
+}
+
+static int sun4i_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+			    u16 value)
+{
+	struct sun4i_mdio_data *data = bus->priv;
+	unsigned long start_jiffies;
+
+	/* issue the phy address and reg */
+	writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
+	/* pull up the phy io line */
+	writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
+
+	/* Wait read complete */
+	start_jiffies = jiffies;
+	while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
+		if (time_after(start_jiffies,
+			       start_jiffies + MDIO_TIMEOUT))
+			return -ETIMEDOUT;
+		msleep(1);
+	}
+
+	/* push down the phy io line */
+	writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
+	/* and write data */
+	writel(value, data->membase + EMAC_MAC_MWTD_REG);
+
+	return 0;
+}
+
+static int sun4i_mdio_reset(struct mii_bus *bus)
+{
+	return 0;
+}
+
+static int sun4i_mdio_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct mii_bus *bus;
+	struct sun4i_mdio_data *data;
+	int ret, i;
+
+	bus = mdiobus_alloc_size(sizeof(*data));
+	if (!bus)
+		return -ENOMEM;
+
+	bus->name = "sun4i_mii_bus";
+	bus->read = &sun4i_mdio_read;
+	bus->write = &sun4i_mdio_write;
+	bus->reset = &sun4i_mdio_reset;
+	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
+	bus->parent = &pdev->dev;
+
+	bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!bus->irq) {
+		ret = -ENOMEM;
+		goto err_out_free_mdiobus;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		bus->irq[i] = PHY_POLL;
+
+	data = bus->priv;
+	data->membase = of_iomap(np, 0);
+	if (!data->membase) {
+		ret = -ENOMEM;
+		goto err_out_free_mdio_irq;
+	}
+
+	data->regulator = devm_regulator_get(&pdev->dev, "phy");
+	if (IS_ERR(data->regulator)) {
+		if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+
+		dev_info(&pdev->dev, "no regulator found\n");
+	} else
+		regulator_enable(data->regulator);
+
+	ret = of_mdiobus_register(bus, np);
+	if (ret < 0)
+		goto err_out_disable_regulator;
+
+	platform_set_drvdata(pdev, bus);
+
+	return 0;
+
+err_out_disable_regulator:
+	regulator_disable(data->regulator);
+err_out_free_mdio_irq:
+	kfree(bus->irq);
+err_out_free_mdiobus:
+	mdiobus_free(bus);
+	return ret;
+}
+
+static int sun4i_mdio_remove(struct platform_device *pdev)
+{
+	struct mii_bus *bus = platform_get_drvdata(pdev);
+
+	mdiobus_unregister(bus);
+	kfree(bus->irq);
+	mdiobus_free(bus);
+
+	return 0;
+}
+
+static const struct of_device_id sun4i_mdio_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-mdio" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sun4i_mdio_dt_ids);
+
+static struct platform_driver sun4i_mdio_driver = {
+	.probe = sun4i_mdio_probe,
+	.remove = sun4i_mdio_remove,
+	.driver = {
+		.name = "sun4i-mdio",
+		.of_match_table = sun4i_mdio_dt_ids,
+	},
+};
+
+module_platform_driver(sun4i_mdio_driver);
+
+MODULE_DESCRIPTION("Allwinner EMAC MDIO interface driver");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com>");
+MODULE_LICENSE("GPL");
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May 24 05:23:09 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:09 +0200
Subject: [PATCHv3 1/6] net: Add EMAC ethernet driver found on Allwinner A10
 SoC's
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369387394-9453-2-git-send-email-maxime.ripard@free-electrons.com>

From: Stefan Roese <sr at denx.de>

The Allwinner A10 has an ethernet controller that seem to be developped
internally by them.

The exact feature set of this controller is unknown, since there is no
public documentation for this IP, and this driver is mostly the one
published by Allwinner that has been heavily cleaned up.

Signed-off-by: Stefan Roese <sr at denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../bindings/net/allwinner,sun4i-emac.txt          |  22 +
 drivers/net/ethernet/Kconfig                       |   1 +
 drivers/net/ethernet/Makefile                      |   1 +
 drivers/net/ethernet/allwinner/Kconfig             |  36 +
 drivers/net/ethernet/allwinner/Makefile            |   5 +
 drivers/net/ethernet/allwinner/sun4i-emac.c        | 960 +++++++++++++++++++++
 drivers/net/ethernet/allwinner/sun4i-emac.h        | 108 +++
 7 files changed, 1133 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
 create mode 100644 drivers/net/ethernet/allwinner/Kconfig
 create mode 100644 drivers/net/ethernet/allwinner/Makefile
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
new file mode 100644
index 0000000..b90bfcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
@@ -0,0 +1,22 @@
+* Allwinner EMAC ethernet controller
+
+Required properties:
+- compatible: should be "allwinner,sun4i-emac".
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+- phy: A phandle to a phy node defining the PHY address (as the reg
+  property, a single integer).
+- clocks: A phandle to the reference clock for this device
+
+Optional properties:
+- (local-)mac-address: mac address to be used by this driver
+
+Example:
+
+emac: ethernet at 01c0b000 {
+       compatible = "allwinner,sun4i-emac";
+       reg = <0x01c0b000 0x1000>;
+       interrupts = <55>;
+       clocks = <&ahb_gates 17>;
+       phy = <&phy0>;
+};
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index ed956e0..18fd6fb 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -20,6 +20,7 @@ config SUNGEM_PHY
 source "drivers/net/ethernet/3com/Kconfig"
 source "drivers/net/ethernet/adaptec/Kconfig"
 source "drivers/net/ethernet/aeroflex/Kconfig"
+source "drivers/net/ethernet/allwinner/Kconfig"
 source "drivers/net/ethernet/alteon/Kconfig"
 source "drivers/net/ethernet/amd/Kconfig"
 source "drivers/net/ethernet/apple/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 8268d85..009da27 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_VENDOR_3COM) += 3com/
 obj-$(CONFIG_NET_VENDOR_8390) += 8390/
 obj-$(CONFIG_NET_VENDOR_ADAPTEC) += adaptec/
 obj-$(CONFIG_GRETH) += aeroflex/
+obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig
new file mode 100644
index 0000000..4220c9a
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -0,0 +1,36 @@
+#
+# Allwinner device configuration
+#
+
+config NET_VENDOR_ALLWINNER
+       bool "Allwinner devices"
+       default y
+       depends on ARCH_SUNXI
+       ---help---
+         If you have a network (Ethernet) card belonging to this
+	 class, say Y and read the Ethernet-HOWTO, available from
+	 <http://www.tldp.org/docs.html#howto>.
+
+	 Note that the answer to this question doesn't directly
+	 affect the kernel: saying N will just cause the configurator
+	 to skip all the questions about Allwinner cards. If you say Y,
+	 you will be asked for your specific card in the following
+	 questions.
+
+if NET_VENDOR_ALLWINNER
+
+config SUN4I_EMAC
+        tristate "Allwinner A10 EMAC support"
+	depends on ARCH_SUNXI
+	depends on OF
+	select CRC32
+	select NET_CORE
+	select MII
+	select REGULATOR_FIXED_VOLTAGE
+        ---help---
+          Support for Allwinner A10 EMAC ethernet driver.
+
+          To compile this driver as a module, choose M here.  The module
+          will be called sun4i-emac.
+
+endif # NET_VENDOR_ALLWINNER
diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile
new file mode 100644
index 0000000..03129f7
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Allwinner device drivers.
+#
+
+obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
new file mode 100644
index 0000000..b411344
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
@@ -0,0 +1,960 @@
+/*
+ * Allwinner EMAC Fast Ethernet driver for Linux.
+ *
+ * Copyright 2012-2013 Stefan Roese <sr at denx.de>
+ * Copyright 2013 Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997  Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_mdio.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+
+#include "sun4i-emac.h"
+
+#define DRV_NAME		"sun4i-emac"
+#define DRV_VERSION		"1.02"
+
+#define EMAC_MAX_FRAME_LEN	0x0600
+
+/* Transmit timeout, default 5 seconds. */
+static int watchdog = 5000;
+module_param(watchdog, int, 0400);
+MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
+
+/* EMAC register address locking.
+ *
+ * The EMAC uses an address register to control where data written
+ * to the data register goes. This means that the address register
+ * must be preserved over interrupts or similar calls.
+ *
+ * During interrupt and other critical calls, a spinlock is used to
+ * protect the system, but the calls themselves save the address
+ * in the address register in case they are interrupting another
+ * access to the device.
+ *
+ * For general accesses a lock is provided so that calls which are
+ * allowed to sleep are serialised so that the address register does
+ * not need to be saved. This lock also serves to serialise access
+ * to the EEPROM and PHY access registers which are shared between
+ * these two devices.
+ */
+
+/* The driver supports the original EMACE, and now the two newer
+ * devices, EMACA and EMACB.
+ */
+
+struct emac_board_info {
+	struct clk		*clk;
+	struct device		*dev;
+	struct platform_device	*pdev;
+	spinlock_t		lock;
+	void __iomem		*membase;
+	u32			msg_enable;
+	struct net_device	*ndev;
+	struct sk_buff		*skb_last;
+	u16			tx_fifo_stat;
+
+	int			emacrx_completed_flag;
+
+	struct phy_device	*phy_dev;
+	struct device_node	*phy_node;
+	unsigned int		link;
+	unsigned int		speed;
+	unsigned int		duplex;
+
+	phy_interface_t		phy_interface;
+};
+
+static void emac_update_speed(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned int reg_val;
+
+	/* set EMAC SPEED, depend on PHY  */
+	reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
+	reg_val &= ~(0x1 << 8);
+	if (db->speed == SPEED_100)
+		reg_val |= 1 << 8;
+	writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
+}
+
+static void emac_update_duplex(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned int reg_val;
+
+	/* set duplex depend on phy */
+	reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
+	reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
+	if (db->duplex)
+		reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
+	writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
+}
+
+static void emac_handle_link_change(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	struct phy_device *phydev = db->phy_dev;
+	unsigned long flags;
+	int status_change = 0;
+
+	if (phydev->link) {
+		if (db->speed != phydev->speed) {
+			spin_lock_irqsave(&db->lock, flags);
+			db->speed = phydev->speed;
+			emac_update_speed(dev);
+			spin_unlock_irqrestore(&db->lock, flags);
+			status_change = 1;
+		}
+
+		if (db->duplex != phydev->duplex) {
+			spin_lock_irqsave(&db->lock, flags);
+			db->duplex = phydev->duplex;
+			emac_update_duplex(dev);
+			spin_unlock_irqrestore(&db->lock, flags);
+			status_change = 1;
+		}
+	}
+
+	if (phydev->link != db->link) {
+		if (!phydev->link) {
+			db->speed = 0;
+			db->duplex = -1;
+		}
+		db->link = phydev->link;
+
+		status_change = 1;
+	}
+
+	if (status_change)
+		phy_print_status(phydev);
+}
+
+static int emac_mdio_probe(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+
+	/* to-do: PHY interrupts are currently not supported */
+
+	/* attach the mac to the phy */
+	db->phy_dev = of_phy_connect(db->ndev, db->phy_node,
+				     &emac_handle_link_change, 0,
+				     db->phy_interface);
+	if (!db->phy_dev) {
+		netdev_err(db->ndev, "could not find the PHY\n");
+		return -ENODEV;
+	}
+
+	/* mask with MAC supported features */
+	db->phy_dev->supported &= PHY_BASIC_FEATURES;
+	db->phy_dev->advertising = db->phy_dev->supported;
+
+	db->link = 0;
+	db->speed = 0;
+	db->duplex = -1;
+
+	return 0;
+}
+
+static void emac_mdio_remove(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+
+	phy_disconnect(db->phy_dev);
+	db->phy_dev = NULL;
+}
+
+static void emac_reset(struct emac_board_info *db)
+{
+	dev_dbg(db->dev, "resetting device\n");
+
+	/* RESET device */
+	writel(0, db->membase + EMAC_CTL_REG);
+	udelay(200);
+	writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
+	udelay(200);
+}
+
+static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
+{
+	writesl(reg, data, round_up(count, 4) / 4);
+}
+
+static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
+{
+	readsl(reg, data, round_up(count, 4) / 4);
+}
+
+static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	struct emac_board_info *dm = netdev_priv(dev);
+	struct phy_device *phydev = dm->phy_dev;
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_mii_ioctl(phydev, rq, cmd);
+}
+
+/* ethtool ops */
+static void emac_get_drvinfo(struct net_device *dev,
+			      struct ethtool_drvinfo *info)
+{
+	strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME));
+	strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION));
+	strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
+}
+
+static int emac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+	struct emac_board_info *dm = netdev_priv(dev);
+	struct phy_device *phydev = dm->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int emac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+	struct emac_board_info *dm = netdev_priv(dev);
+	struct phy_device *phydev = dm->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static const struct ethtool_ops emac_ethtool_ops = {
+	.get_drvinfo	= emac_get_drvinfo,
+	.get_settings	= emac_get_settings,
+	.set_settings	= emac_set_settings,
+	.get_link	= ethtool_op_get_link,
+};
+
+unsigned int emac_setup(struct net_device *ndev)
+{
+	struct emac_board_info *db = netdev_priv(ndev);
+	unsigned int reg_val;
+
+	/* set up TX */
+	reg_val = readl(db->membase + EMAC_TX_MODE_REG);
+
+	writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
+		db->membase + EMAC_TX_MODE_REG);
+
+	/* set up RX */
+	reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+
+	writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
+		EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
+		EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
+		EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
+		db->membase + EMAC_RX_CTL_REG);
+
+	/* set MAC */
+	/* set MAC CTL0 */
+	reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
+	writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
+		EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
+		db->membase + EMAC_MAC_CTL0_REG);
+
+	/* set MAC CTL1 */
+	reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
+	reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
+	reg_val |= EMAC_MAC_CTL1_CRC_EN;
+	reg_val |= EMAC_MAC_CTL1_PAD_EN;
+	writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
+
+	/* set up IPGT */
+	writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
+
+	/* set up IPGR */
+	writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
+		db->membase + EMAC_MAC_IPGR_REG);
+
+	/* set up Collison window */
+	writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
+		db->membase + EMAC_MAC_CLRT_REG);
+
+	/* set up Max Frame Length */
+	writel(EMAC_MAX_FRAME_LEN,
+		db->membase + EMAC_MAC_MAXF_REG);
+
+	return 0;
+}
+
+unsigned int emac_powerup(struct net_device *ndev)
+{
+	struct emac_board_info *db = netdev_priv(ndev);
+	unsigned int reg_val;
+
+	/* initial EMAC */
+	/* flush RX FIFO */
+	reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+	reg_val |= 0x8;
+	writel(reg_val, db->membase + EMAC_RX_CTL_REG);
+	udelay(1);
+
+	/* initial MAC */
+	/* soft reset MAC */
+	reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
+	reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
+	writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
+
+	/* set MII clock */
+	reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
+	reg_val &= (~(0xf << 2));
+	reg_val |= (0xD << 2);
+	writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
+
+	/* clear RX counter */
+	writel(0x0, db->membase + EMAC_RX_FBC_REG);
+
+	/* disable all interrupt and clear interrupt status */
+	writel(0, db->membase + EMAC_INT_CTL_REG);
+	reg_val = readl(db->membase + EMAC_INT_STA_REG);
+	writel(reg_val, db->membase + EMAC_INT_STA_REG);
+
+	udelay(1);
+
+	/* set up EMAC */
+	emac_setup(ndev);
+
+	/* set mac_address to chip */
+	writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
+	       dev_addr[2], db->membase + EMAC_MAC_A1_REG);
+	writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
+	       dev_addr[5], db->membase + EMAC_MAC_A0_REG);
+
+	mdelay(1);
+
+	return 0;
+}
+
+static int emac_set_mac_address(struct net_device *dev, void *p)
+{
+	struct sockaddr *addr = p;
+	struct emac_board_info *db = netdev_priv(dev);
+
+	if (netif_running(dev))
+		return -EBUSY;
+
+	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
+
+	writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
+	       dev_addr[2], db->membase + EMAC_MAC_A1_REG);
+	writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
+	       dev_addr[5], db->membase + EMAC_MAC_A0_REG);
+
+	return 0;
+}
+
+/* Initialize emac board */
+static void emac_init_device(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned long flags;
+	unsigned int reg_val;
+
+	spin_lock_irqsave(&db->lock, flags);
+
+	emac_update_speed(dev);
+	emac_update_duplex(dev);
+
+	/* enable RX/TX */
+	reg_val = readl(db->membase + EMAC_CTL_REG);
+	writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
+		db->membase + EMAC_CTL_REG);
+
+	/* enable RX/TX0/RX Hlevel interrup */
+	reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+	reg_val |= (0xf << 0) | (0x01 << 8);
+	writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+
+	spin_unlock_irqrestore(&db->lock, flags);
+}
+
+/* Our watchdog timed out. Called by the networking layer */
+static void emac_timeout(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned long flags;
+
+	if (netif_msg_timer(db))
+		dev_err(db->dev, "tx time out.\n");
+
+	/* Save previous register address */
+	spin_lock_irqsave(&db->lock, flags);
+
+	netif_stop_queue(dev);
+	emac_reset(db);
+	emac_init_device(dev);
+	/* We can accept TX packets again */
+	dev->trans_start = jiffies;
+	netif_wake_queue(dev);
+
+	/* Restore previous register address */
+	spin_unlock_irqrestore(&db->lock, flags);
+}
+
+/* Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned long channel;
+	unsigned long flags;
+
+	channel = db->tx_fifo_stat & 3;
+	if (channel == 3)
+		return 1;
+
+	channel = (channel == 1 ? 1 : 0);
+
+	spin_lock_irqsave(&db->lock, flags);
+
+	writel(channel, db->membase + EMAC_TX_INS_REG);
+
+	emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
+			skb->data, skb->len);
+	dev->stats.tx_bytes += skb->len;
+
+	db->tx_fifo_stat |= 1 << channel;
+	/* TX control: First packet immediately send, second packet queue */
+	if (channel == 0) {
+		/* set TX len */
+		writel(skb->len, db->membase + EMAC_TX_PL0_REG);
+		/* start translate from fifo to phy */
+		writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
+		       db->membase + EMAC_TX_CTL0_REG);
+
+		/* save the time stamp */
+		dev->trans_start = jiffies;
+	} else if (channel == 1) {
+		/* set TX len */
+		writel(skb->len, db->membase + EMAC_TX_PL1_REG);
+		/* start translate from fifo to phy */
+		writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
+		       db->membase + EMAC_TX_CTL1_REG);
+
+		/* save the time stamp */
+		dev->trans_start = jiffies;
+	}
+
+	if ((db->tx_fifo_stat & 3) == 3) {
+		/* Second packet */
+		netif_stop_queue(dev);
+	}
+
+	spin_unlock_irqrestore(&db->lock, flags);
+
+	/* free this SKB */
+	dev_kfree_skb(skb);
+
+	return NETDEV_TX_OK;
+}
+
+/* EMAC interrupt handler
+ * receive the packet to upper layer, free the transmitted packet
+ */
+static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
+			  unsigned int tx_status)
+{
+	/* One packet sent complete */
+	db->tx_fifo_stat &= ~(tx_status & 3);
+	if (3 == (tx_status & 3))
+		dev->stats.tx_packets += 2;
+	else
+		dev->stats.tx_packets++;
+
+	if (netif_msg_tx_done(db))
+		dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
+
+	netif_wake_queue(dev);
+}
+
+/* Received a packet and pass to upper layer
+ */
+static void emac_rx(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	struct sk_buff *skb;
+	u8 *rdptr;
+	bool good_packet;
+	static int rxlen_last;
+	unsigned int reg_val;
+	u32 rxhdr, rxstatus, rxcount, rxlen;
+
+	/* Check packet ready or not */
+	while (1) {
+		/* race warning: the first packet might arrive with
+		 * the interrupts disabled, but the second will fix
+		 * it
+		 */
+		rxcount = readl(db->membase + EMAC_RX_FBC_REG);
+
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "RXCount: %x\n", rxcount);
+
+		if ((db->skb_last != NULL) && (rxlen_last > 0)) {
+			dev->stats.rx_bytes += rxlen_last;
+
+			/* Pass to upper layer */
+			db->skb_last->protocol = eth_type_trans(db->skb_last,
+								dev);
+			netif_rx(db->skb_last);
+			dev->stats.rx_packets++;
+			db->skb_last = NULL;
+			rxlen_last = 0;
+
+			reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+			reg_val &= ~EMAC_RX_CTL_DMA_EN;
+			writel(reg_val, db->membase + EMAC_RX_CTL_REG);
+		}
+
+		if (!rxcount) {
+			db->emacrx_completed_flag = 1;
+			reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+			reg_val |= (0xf << 0) | (0x01 << 8);
+			writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+
+			/* had one stuck? */
+			rxcount = readl(db->membase + EMAC_RX_FBC_REG);
+			if (!rxcount)
+				return;
+		}
+
+		reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "receive header: %x\n", reg_val);
+		if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
+			/* disable RX */
+			reg_val = readl(db->membase + EMAC_CTL_REG);
+			writel(reg_val & ~EMAC_CTL_RX_EN,
+			       db->membase + EMAC_CTL_REG);
+
+			/* Flush RX FIFO */
+			reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+			writel(reg_val | (1 << 3),
+			       db->membase + EMAC_RX_CTL_REG);
+
+			do {
+				reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+			} while (reg_val & (1 << 3));
+
+			/* enable RX */
+			reg_val = readl(db->membase + EMAC_CTL_REG);
+			writel(reg_val | EMAC_CTL_RX_EN,
+			       db->membase + EMAC_CTL_REG);
+			reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+			reg_val |= (0xf << 0) | (0x01 << 8);
+			writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+
+			db->emacrx_completed_flag = 1;
+
+			return;
+		}
+
+		/* A packet ready now  & Get status/length */
+		good_packet = true;
+
+		emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
+				&rxhdr, sizeof(rxhdr));
+
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
+
+		rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
+		rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
+
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "RX: status %02x, length %04x\n",
+				rxstatus, rxlen);
+
+		/* Packet Status check */
+		if (rxlen < 0x40) {
+			good_packet = false;
+			if (netif_msg_rx_err(db))
+				dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
+		}
+
+		if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
+			good_packet = false;
+
+			if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
+				if (netif_msg_rx_err(db))
+					dev_dbg(db->dev, "crc error\n");
+				dev->stats.rx_crc_errors++;
+			}
+
+			if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
+				if (netif_msg_rx_err(db))
+					dev_dbg(db->dev, "length error\n");
+				dev->stats.rx_length_errors++;
+			}
+		}
+
+		/* Move data from EMAC */
+		skb = dev_alloc_skb(rxlen + 4);
+		if (good_packet && skb) {
+			skb_reserve(skb, 2);
+			rdptr = (u8 *) skb_put(skb, rxlen - 4);
+
+			/* Read received packet from RX SRAM */
+			if (netif_msg_rx_status(db))
+				dev_dbg(db->dev, "RxLen %x\n", rxlen);
+
+			emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
+					rdptr, rxlen);
+			dev->stats.rx_bytes += rxlen;
+
+			/* Pass to upper layer */
+			skb->protocol = eth_type_trans(skb, dev);
+			netif_rx(skb);
+			dev->stats.rx_packets++;
+		}
+	}
+}
+
+static irqreturn_t emac_interrupt(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct emac_board_info *db = netdev_priv(dev);
+	int int_status;
+	unsigned long flags;
+	unsigned int reg_val;
+
+	/* A real interrupt coming */
+
+	/* holders of db->lock must always block IRQs */
+	spin_lock_irqsave(&db->lock, flags);
+
+	/* Disable all interrupts */
+	writel(0, db->membase + EMAC_INT_CTL_REG);
+
+	/* Got EMAC interrupt status */
+	/* Got ISR */
+	int_status = readl(db->membase + EMAC_INT_STA_REG);
+	/* Clear ISR status */
+	writel(int_status, db->membase + EMAC_INT_STA_REG);
+
+	if (netif_msg_intr(db))
+		dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
+
+	/* Received the coming packet */
+	if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
+		/* carrier lost */
+		db->emacrx_completed_flag = 0;
+		emac_rx(dev);
+	}
+
+	/* Transmit Interrupt check */
+	if (int_status & (0x01 | 0x02))
+		emac_tx_done(dev, db, int_status);
+
+	if (int_status & (0x04 | 0x08))
+		netdev_info(dev, " ab : %x\n", int_status);
+
+	/* Re-enable interrupt mask */
+	if (db->emacrx_completed_flag == 1) {
+		reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+		reg_val |= (0xf << 0) | (0x01 << 8);
+		writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+	}
+	spin_unlock_irqrestore(&db->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Used by netconsole
+ */
+static void emac_poll_controller(struct net_device *dev)
+{
+	disable_irq(dev->irq);
+	emac_interrupt(dev->irq, dev);
+	enable_irq(dev->irq);
+}
+#endif
+
+/*  Open the interface.
+ *  The interface is opened whenever "ifconfig" actives it.
+ */
+static int emac_open(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	int ret;
+
+	if (netif_msg_ifup(db))
+		dev_dbg(db->dev, "enabling %s\n", dev->name);
+
+	if (devm_request_irq(db->dev, dev->irq, &emac_interrupt,
+			     0, dev->name, dev))
+		return -EAGAIN;
+
+	/* Initialize EMAC board */
+	emac_reset(db);
+	emac_init_device(dev);
+
+	ret = emac_mdio_probe(dev);
+	if (ret < 0) {
+		netdev_err(dev, "cannot probe MDIO bus\n");
+		return ret;
+	}
+
+	phy_start(db->phy_dev);
+	netif_start_queue(dev);
+
+	return 0;
+}
+
+static void emac_shutdown(struct net_device *dev)
+{
+	unsigned int reg_val;
+	struct emac_board_info *db = netdev_priv(dev);
+
+	/* Disable all interrupt */
+	writel(0, db->membase + EMAC_INT_CTL_REG);
+
+	/* clear interupt status */
+	reg_val = readl(db->membase + EMAC_INT_STA_REG);
+	writel(reg_val, db->membase + EMAC_INT_STA_REG);
+
+	/* Disable RX/TX */
+	reg_val = readl(db->membase + EMAC_CTL_REG);
+	reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
+	writel(reg_val, db->membase + EMAC_CTL_REG);
+}
+
+/* Stop the interface.
+ * The interface is stopped when it is brought.
+ */
+static int emac_stop(struct net_device *ndev)
+{
+	struct emac_board_info *db = netdev_priv(ndev);
+
+	if (netif_msg_ifdown(db))
+		dev_dbg(db->dev, "shutting down %s\n", ndev->name);
+
+	netif_stop_queue(ndev);
+	netif_carrier_off(ndev);
+
+	phy_stop(db->phy_dev);
+
+	emac_mdio_remove(ndev);
+
+	emac_shutdown(ndev);
+
+	return 0;
+}
+
+static const struct net_device_ops emac_netdev_ops = {
+	.ndo_open		= emac_open,
+	.ndo_stop		= emac_stop,
+	.ndo_start_xmit		= emac_start_xmit,
+	.ndo_tx_timeout		= emac_timeout,
+	.ndo_do_ioctl		= emac_ioctl,
+	.ndo_change_mtu		= eth_change_mtu,
+	.ndo_validate_addr	= eth_validate_addr,
+	.ndo_set_mac_address	= emac_set_mac_address,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller	= emac_poll_controller,
+#endif
+};
+
+/* Search EMAC board, allocate space and register it
+ */
+static int emac_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct emac_board_info *db;
+	struct net_device *ndev;
+	int ret = 0;
+	const char *mac_addr;
+
+	ndev = alloc_etherdev(sizeof(struct emac_board_info));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		return -ENOMEM;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	db = netdev_priv(ndev);
+	memset(db, 0, sizeof(*db));
+
+	db->dev = &pdev->dev;
+	db->ndev = ndev;
+	db->pdev = pdev;
+
+	spin_lock_init(&db->lock);
+
+	db->membase = of_iomap(np, 0);
+	if (!db->membase) {
+		dev_err(&pdev->dev, "failed to remap registers\n");
+		return -ENOMEM;
+		goto out;
+	}
+
+	/* fill in parameters for net-dev structure */
+	ndev->base_addr = (unsigned long)db->membase;
+	ndev->irq = irq_of_parse_and_map(np, 0);
+	if (ndev->irq == -ENXIO) {
+		netdev_err(ndev, "No irq resource\n");
+		ret = ndev->irq;
+		goto out;
+	}
+
+	db->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(db->clk))
+		goto out;
+
+	clk_prepare_enable(db->clk);
+
+	db->phy_node = of_parse_phandle(np, "phy", 0);
+	if (!db->phy_node) {
+		dev_err(&pdev->dev, "no associated PHY\n");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Read MAC-address from DT */
+	mac_addr = of_get_mac_address(np);
+	if (mac_addr)
+		memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
+
+	/* Check if the MAC address is valid, if not get a random one */
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		eth_hw_addr_random(ndev);
+		dev_warn(&pdev->dev, "using random MAC address %pM\n",
+			 ndev->dev_addr);
+	}
+
+	db->emacrx_completed_flag = 1;
+	emac_powerup(ndev);
+	emac_reset(db);
+
+	ether_setup(ndev);
+
+	ndev->netdev_ops = &emac_netdev_ops;
+	ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
+	ndev->ethtool_ops = &emac_ethtool_ops;
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	ndev->poll_controller = &emac_poll_controller;
+#endif
+
+	platform_set_drvdata(pdev, ndev);
+
+	/* Carrier starts down, phylib will bring it up */
+	netif_carrier_off(ndev);
+
+	ret = register_netdev(ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "Registering netdev failed!\n");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
+		 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
+
+	return 0;
+
+out:
+	dev_err(db->dev, "not found (%d).\n", ret);
+
+	free_netdev(ndev);
+
+	return ret;
+}
+
+static int emac_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	unregister_netdev(ndev);
+	free_netdev(ndev);
+
+	dev_dbg(&pdev->dev, "released and freed device\n");
+	return 0;
+}
+
+static int emac_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(dev);
+
+	netif_carrier_off(ndev);
+	netif_device_detach(ndev);
+	emac_shutdown(ndev);
+
+	return 0;
+}
+
+static int emac_resume(struct platform_device *dev)
+{
+	struct net_device *ndev = platform_get_drvdata(dev);
+	struct emac_board_info *db = netdev_priv(ndev);
+
+	emac_reset(db);
+	emac_init_device(ndev);
+	netif_device_attach(ndev);
+
+	return 0;
+}
+
+static const struct of_device_id emac_of_match[] = {
+	{.compatible = "allwinner,sun4i-emac",},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, emac_of_match);
+
+static struct platform_driver emac_driver = {
+	.driver = {
+		.name = "sun4i-emac",
+		.of_match_table = emac_of_match,
+	},
+	.probe = emac_probe,
+	.remove = emac_remove,
+	.suspend = emac_suspend,
+	.resume = emac_resume,
+};
+
+module_platform_driver(emac_driver);
+
+MODULE_AUTHOR("Stefan Roese <sr at denx.de>");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com>");
+MODULE_DESCRIPTION("Allwinner A10 emac network driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.h b/drivers/net/ethernet/allwinner/sun4i-emac.h
new file mode 100644
index 0000000..38c72d9
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.h
@@ -0,0 +1,108 @@
+/*
+ * Allwinner EMAC Fast Ethernet driver for Linux.
+ *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ * Copyright 2013 Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997  Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _SUN4I_EMAC_H_
+#define _SUN4I_EMAC_H_
+
+#define EMAC_CTL_REG		(0x00)
+#define EMAC_CTL_RESET			(1 << 0)
+#define EMAC_CTL_TX_EN			(1 << 1)
+#define EMAC_CTL_RX_EN			(1 << 2)
+#define EMAC_TX_MODE_REG	(0x04)
+#define EMAC_TX_MODE_ABORTED_FRAME_EN	(1 << 0)
+#define EMAC_TX_MODE_DMA_EN		(1 << 1)
+#define EMAC_TX_FLOW_REG	(0x08)
+#define EMAC_TX_CTL0_REG	(0x0c)
+#define EMAC_TX_CTL1_REG	(0x10)
+#define EMAC_TX_INS_REG		(0x14)
+#define EMAC_TX_PL0_REG		(0x18)
+#define EMAC_TX_PL1_REG		(0x1c)
+#define EMAC_TX_STA_REG		(0x20)
+#define EMAC_TX_IO_DATA_REG	(0x24)
+#define EMAC_TX_IO_DATA1_REG	(0x28)
+#define EMAC_TX_TSVL0_REG	(0x2c)
+#define EMAC_TX_TSVH0_REG	(0x30)
+#define EMAC_TX_TSVL1_REG	(0x34)
+#define EMAC_TX_TSVH1_REG	(0x38)
+#define EMAC_RX_CTL_REG		(0x3c)
+#define EMAC_RX_CTL_AUTO_DRQ_EN		(1 << 1)
+#define EMAC_RX_CTL_DMA_EN		(1 << 2)
+#define EMAC_RX_CTL_PASS_ALL_EN		(1 << 4)
+#define EMAC_RX_CTL_PASS_CTL_EN		(1 << 5)
+#define EMAC_RX_CTL_PASS_CRC_ERR_EN	(1 << 6)
+#define EMAC_RX_CTL_PASS_LEN_ERR_EN	(1 << 7)
+#define EMAC_RX_CTL_PASS_LEN_OOR_EN	(1 << 8)
+#define EMAC_RX_CTL_ACCEPT_UNICAST_EN	(1 << 16)
+#define EMAC_RX_CTL_DA_FILTER_EN	(1 << 17)
+#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN	(1 << 20)
+#define EMAC_RX_CTL_HASH_FILTER_EN	(1 << 21)
+#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN	(1 << 22)
+#define EMAC_RX_CTL_SA_FILTER_EN	(1 << 24)
+#define EMAC_RX_CTL_SA_FILTER_INVERT_EN	(1 << 25)
+#define EMAC_RX_HASH0_REG	(0x40)
+#define EMAC_RX_HASH1_REG	(0x44)
+#define EMAC_RX_STA_REG		(0x48)
+#define EMAC_RX_IO_DATA_REG	(0x4c)
+#define EMAC_RX_IO_DATA_LEN(x)		(x & 0xffff)
+#define EMAC_RX_IO_DATA_STATUS(x)	((x >> 16) & 0xffff)
+#define EMAC_RX_IO_DATA_STATUS_CRC_ERR	(1 << 4)
+#define EMAC_RX_IO_DATA_STATUS_LEN_ERR	(3 << 5)
+#define EMAC_RX_IO_DATA_STATUS_OK	(1 << 7)
+#define EMAC_RX_FBC_REG		(0x50)
+#define EMAC_INT_CTL_REG	(0x54)
+#define EMAC_INT_STA_REG	(0x58)
+#define EMAC_MAC_CTL0_REG	(0x5c)
+#define EMAC_MAC_CTL0_RX_FLOW_CTL_EN	(1 << 2)
+#define EMAC_MAC_CTL0_TX_FLOW_CTL_EN	(1 << 3)
+#define EMAC_MAC_CTL0_SOFT_RESET	(1 << 15)
+#define EMAC_MAC_CTL1_REG	(0x60)
+#define EMAC_MAC_CTL1_DUPLEX_EN		(1 << 0)
+#define EMAC_MAC_CTL1_LEN_CHECK_EN	(1 << 1)
+#define EMAC_MAC_CTL1_HUGE_FRAME_EN	(1 << 2)
+#define EMAC_MAC_CTL1_DELAYED_CRC_EN	(1 << 3)
+#define EMAC_MAC_CTL1_CRC_EN		(1 << 4)
+#define EMAC_MAC_CTL1_PAD_EN		(1 << 5)
+#define EMAC_MAC_CTL1_PAD_CRC_EN	(1 << 6)
+#define EMAC_MAC_CTL1_AD_SHORT_FRAME_EN	(1 << 7)
+#define EMAC_MAC_CTL1_BACKOFF_DIS	(1 << 12)
+#define EMAC_MAC_IPGT_REG	(0x64)
+#define EMAC_MAC_IPGT_HALF_DUPLEX	(0x12)
+#define EMAC_MAC_IPGT_FULL_DUPLEX	(0x15)
+#define EMAC_MAC_IPGR_REG	(0x68)
+#define EMAC_MAC_IPGR_IPG1		(0x0c)
+#define EMAC_MAC_IPGR_IPG2		(0x12)
+#define EMAC_MAC_CLRT_REG	(0x6c)
+#define EMAC_MAC_CLRT_COLLISION_WINDOW	(0x37)
+#define EMAC_MAC_CLRT_RM		(0x0f)
+#define EMAC_MAC_MAXF_REG	(0x70)
+#define EMAC_MAC_SUPP_REG	(0x74)
+#define EMAC_MAC_TEST_REG	(0x78)
+#define EMAC_MAC_MCFG_REG	(0x7c)
+#define EMAC_MAC_A0_REG		(0x98)
+#define EMAC_MAC_A1_REG		(0x9c)
+#define EMAC_MAC_A2_REG		(0xa0)
+#define EMAC_SAFX_L_REG0	(0xa4)
+#define EMAC_SAFX_H_REG0	(0xa8)
+#define EMAC_SAFX_L_REG1	(0xac)
+#define EMAC_SAFX_H_REG1	(0xb0)
+#define EMAC_SAFX_L_REG2	(0xb4)
+#define EMAC_SAFX_H_REG2	(0xb8)
+#define EMAC_SAFX_L_REG3	(0xbc)
+#define EMAC_SAFX_H_REG3	(0xc0)
+
+#define EMAC_PHY_DUPLEX		(1 << 8)
+
+#define EMAC_EEPROM_MAGIC	(0x444d394b)
+#define EMAC_UNDOCUMENTED_MAGIC	(0x0143414d)
+#endif /* _SUN4I_EMAC_H_ */
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May 24 05:23:11 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:11 +0200
Subject: [PATCHv3 3/6] ARM: sun4i: Add muxing options for the ethernet
 controller
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369387394-9453-4-git-send-email-maxime.ripard@free-electrons.com>

The EMAC only has one pinset available for muxing, so hopefully, we
cover all cases.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..ff1f41f 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,17 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			emac_pins_a: emac0 at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA9", "PA10",
+						"PA11", "PA12", "PA13", "PA14",
+						"PA15", "PA16";
+				allwinner,function = "emac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May 24 05:23:12 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:12 +0200
Subject: [PATCHv3 4/6] ARM: sunxi: Add EMAC controller node to sun4i DTSI
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369387394-9453-5-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ff1f41f..983da33 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -163,6 +163,22 @@
 		reg = <0x01c20000 0x300000>;
 		ranges;
 
+		emac: ethernet at 01c0b000 {
+			compatible = "allwinner,sun4i-emac";
+			reg = <0x01c0b000 0x1000>;
+			interrupts = <55>;
+			clocks = <&ahb_gates 17>;
+			status = "disabled";
+		};
+
+		mdio at 01c0b080 {
+			compatible = "allwinner,sun4i-mdio";
+			reg = <0x01c0b080 0x14>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		intc: interrupt-controller at 01c20400 {
 			compatible = "allwinner,sun4i-ic";
 			reg = <0x01c20400 0x400>;
-- 
1.8.1.2



From t.figa at samsung.com  Fri May 24 05:23:23 2013
From: t.figa at samsung.com (Tomasz Figa)
Date: Fri, 24 May 2013 11:23:23 +0200
Subject: [PATCH v3 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT
 registers
In-Reply-To: <CACRpkdbN4Nxg2VSr0bf+h4Y2U=CmX9mijdZz+=tom9V0-i-69g@mail.gmail.com>
References: <1368807872-2601-1-git-send-email-t.figa@samsung.com>
 <3059629.yu4Ei1BXhd@amdc1227>
 <CACRpkdbN4Nxg2VSr0bf+h4Y2U=CmX9mijdZz+=tom9V0-i-69g@mail.gmail.com>
Message-ID: <2032031.lFyZLmqevW@amdc1227>

Hi Linus,

On Friday 24 of May 2013 11:12:00 Linus Walleij wrote:
> On Wed, May 22, 2013 at 4:03 PM, Tomasz Figa <t.figa at samsung.com> wrote:
> > Some GPIO EINT control registers needs to be preserved across
> > suspend/resume cycle. This patch extends the driver to take care of
> > this.
> > 
> > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> > 
> > Changes since v2:
> >  - Fixed error path
> > 
> > Changes since v1:
> >  - Added optional debugging messages
> >  - Added proper error path in initialization
> 
> v2 version applied for fixes.

I posted v3 two days ago. It fixes a stupid mistake in error path I made in a 
hurry and also addresses some suggestions from Doug.

> Again confirm you must really have all this. It is not looking
> good with diffstats like this for fixing regressions.

Yes. The whole series is necessary to have correct suspend/resume support of 
DT-enabled Exynos boards.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics


From maxime.ripard at free-electrons.com  Fri May 24 05:23:13 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:13 +0200
Subject: [PATCHv3 5/6] ARM: cubieboard: Enable ethernet (EMAC) support in dts
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369387394-9453-6-git-send-email-maxime.ripard@free-electrons.com>

From: Stefan Roese <sr at denx.de>

Signed-off-by: Stefan Roese <sr at denx.de>
---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..32d9b18 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -27,6 +27,21 @@
 	};
 
 	soc at 01c20000 {
+		emac: ethernet at 01c0b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&emac_pins_a>;
+			phy = <&phy0>;
+			status = "okay";
+		};
+
+		mdio at 01c0b080 {
+			status = "okay";
+
+			phy0: ethernet-phy at 0 {
+				reg = <0>;
+			};
+		};
+
 		pinctrl at 01c20800 {
 			led_pins_cubieboard: led_pins at 0 {
 				allwinner,pins = "PH20", "PH21";
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Fri May 24 05:23:14 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:23:14 +0200
Subject: [PATCHv3 6/6] ARM: sunxi: Add EMAC Controller to Hackberry dt
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369387394-9453-7-git-send-email-maxime.ripard@free-electrons.com>

The Hackberry has a PHY that needs to be powered up through a GPIO, so
we need to use a fixed regulator here.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10-hackberry.dts | 41 +++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b9efac1..3514b37 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -23,10 +23,51 @@
 	};
 
 	soc at 01c20000 {
+		emac: ethernet at 01c0b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&emac_pins_a>;
+			phy = <&phy0>;
+			status = "okay";
+		};
+
+		mdio at 01c0b080 {
+			phy-supply = <&reg_emac_3v3>;
+			status = "okay";
+
+			phy0: ethernet-phy at 0 {
+				reg = <0>;
+			};
+		};
+
+		pio: pinctrl at 01c20800 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&hackberry_hogs>;
+
+			hackberry_hogs: hogs at 0 {
+				allwinner,pins = "PH19";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+
 		uart0: serial at 01c28000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
 	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_emac_3v3: emac-3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "emac-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			enable-active-high;
+			gpio = <&pio 7 19 0>;
+		};
+	};
 };
-- 
1.8.1.2



From B35083 at freescale.com  Fri May 24 05:25:22 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Fri, 24 May 2013 09:25:22 +0000
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <CACRpkdZ=67CWrPqFMU4FeES5OUyV5=Zz2fwy-GAMVHrNU6y6jA@mail.gmail.com>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <20130520033207.GD25113@S2101-09.ap.freescale.net>
 <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>
 <B56CDBE15CE27145A4B77D2D24263E851CBBA4@039-SN1MPN1-003.039d.mgd.msft.net>
 <CAAQ0ZWTBZ=10B+0Zc4iZmvrr0hzdBKf1mn1CzhJokWE44dxsoA@mail.gmail.com>
 <CACRpkdZ=67CWrPqFMU4FeES5OUyV5=Zz2fwy-GAMVHrNU6y6jA@mail.gmail.com>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CC580@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Linus Walleij [mailto:linus.walleij at linaro.org]
>Sent: Friday, May 24, 2013 4:56 PM
>To: Shawn Guo
>Cc: Lu Jingchang-B35083; linux-arm-kernel; Sascha Hauer
>Subject: Re: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
>
>On Wed, May 22, 2013 at 5:24 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>> On 21 May 2013 15:56, Lu Jingchang-B35083 <B35083 at freescale.com> wrote:
>>> [Lu Jingchang-B35083]
>>> I see you have Acked [PATCH v3 2/2] pinctrl: imx: add MVF600 support to
>imx pinctrl framework, do I need resend it as the first one. Thanks!
>>
>> Since LinusW hasn't applied it, you should just resend.
>
>Now it appears I applied 2/2 but not 1/2 due to comments.
>
>Are they orthogonal or do I need to pull the applied patch out again?
>
[Lu Jingchang-B35083] 
Please pull the applied patch out again, I will resend the patch to keep the patch's sequence.
On the other hand I also have some minor update to the patch's description.
Thanks!





From florian at openwrt.org  Fri May 24 05:42:30 2013
From: florian at openwrt.org (Florian Fainelli)
Date: Fri, 24 May 2013 10:42:30 +0100
Subject: [PATCHv3 2/6] net: Add MDIO bus driver for the Allwinner EMAC
In-Reply-To: <1369387394-9453-3-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369387394-9453-3-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CAGVrzcbyXiKCKxtOAj0gnG8eCQag8_xvmd9dUKACCbfW-2HN9Q@mail.gmail.com>

Hello Maxime,

2013/5/24 Maxime Ripard <maxime.ripard at free-electrons.com>
>
> This patch adds a separate driver for the MDIO interface of the
> Allwinner ethernet controllers.
>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +++
>  drivers/net/ethernet/allwinner/Kconfig             |   8 +
>  drivers/net/ethernet/allwinner/Makefile            |   1 +
>  drivers/net/ethernet/allwinner/sun4i-mdio.c        | 191 +++++++++++++++++++++

Ok, so you probably followed Thomas's example here with mvneta/mvmdio,
but all other MDIO bus drivers live in drivers/net/phy. Unfortunately,
mvmdio lives in drivers/net/ethernet/marvell/mvmdio.c which I should
have noticed before. Whatever is good for you guys, but we should
probably start normalizing this now before more mdio drivers get
merged alongside their corresponding ethernet MAC users.


From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:38 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:38 +0200
Subject: [PATCH 01/21] arm: kirkwood: cloudbox: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-2-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-cloudbox.dts |   10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e..00c48d2 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -18,10 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-			pinctrl-0 = < &pmx_spi &pmx_uart0
-					&pmx_cloudbox_sata0 >;
-			pinctrl-names = "default";
-
 			pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
 				marvell,pins = "mpp15";
 				marvell,function = "sata0";
@@ -29,16 +25,22 @@
 		};
 
 		serial at 12000 {
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
 			clock-frequency = <166666667>;
 			status = "okay";
 		};
 
 		sata at 80000 {
+			pinctrl-0 = <&pmx_cloudbox_sata0>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <1>;
 		};
 
 		spi at 10600 {
+			pinctrl-0 = <&pmx_spi>;
+			pinctrl-names = "default";
 			status = "okay";
 
 			flash at 0 {
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:40 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:40 +0200
Subject: [PATCH 03/21] arm: kirkwood: dockstar: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-4-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-dockstar.dts |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6..7714742 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -18,11 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_usb_power_enable
-				      &pmx_led_green &pmx_led_orange >;
-			pinctrl-names = "default";
-
 			pmx_usb_power_enable: pmx-usb-power-enable {
 				marvell,pins = "mpp29";
 				marvell,function = "gpio";
@@ -62,6 +57,8 @@
 	};
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
+		pinctrl-names = "default";
 
 		health {
 			label = "status:green:health";
@@ -77,6 +74,8 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_usb_power_enable>;
+		pinctrl-names = "default";
 
 		usb_power: regulator at 1 {
 			compatible = "regulator-fixed";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:37 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:37 +0200
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
Message-ID: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

This series of patches has the goal of adding support for the Init
button on OpenBlocks A6, but takes this opportunity to do a little bit
of cleanup in the pinmux configurations of the various Kirkwood Device
Trees.

Until now, all pinmux configurations were "owned" by the pinctrl
driver, because back when they were introduced, the driver core was
not selecting the pinmux configuration, each driver had to do it
manually (and not all drivers were doing so). Now that the driver core
selects the default pinmux configuration when available, it makes
sense to associate the pinmux configuration to the particular device
it is related to.

It allows pinctrl to show nice informations in debugfs, which
associates a particular pin with the particular device using it:

# cat pinctrl/f1010000.pinctrl/pinmux-pins 
Pinmux settings per pin
Format: pin (name): mux_owner gpio_owner hog?
pin 0 (PIN0): f4000000.nand (GPIO UNCLAIMED) function nand group mpp0
pin 1 (PIN1): f4000000.nand (GPIO UNCLAIMED) function nand group mpp1
pin 2 (PIN2): f4000000.nand (GPIO UNCLAIMED) function nand group mpp2
pin 3 (PIN3): f4000000.nand (GPIO UNCLAIMED) function nand group mpp3
pin 4 (PIN4): f4000000.nand (GPIO UNCLAIMED) function nand group mpp4
pin 5 (PIN5): f4000000.nand (GPIO UNCLAIMED) function nand group mpp5
pin 6 (PIN6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 7 (PIN7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 8 (PIN8): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp8
pin 9 (PIN9): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp9
pin 10 (PIN10): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp10
pin 11 (PIN11): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp11
pin 12 (PIN12): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 13 (PIN13): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp13
pin 14 (PIN14): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp14
pin 15 (PIN15): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp15
pin 16 (PIN16): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp16
pin 17 (PIN17): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 18 (PIN18): f4000000.nand (GPIO UNCLAIMED) function nand group mpp18
pin 19 (PIN19): f4000000.nand (GPIO UNCLAIMED) function nand group mpp19
pin 20 (PIN20): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp20
pin 21 (PIN21): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp21
pin 22 (PIN22): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp22
pin 23 (PIN23): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp23
pin 24 (PIN24): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp24
pin 25 (PIN25): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp25
pin 26 (PIN26): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp26
pin 27 (PIN27): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp27
pin 28 (PIN28): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp28
pin 29 (PIN29): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp29
pin 30 (PIN30): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp30
pin 31 (PIN31): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp31
pin 32 (PIN32): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 33 (PIN33): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 34 (PIN34): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 35 (PIN35): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 36 (PIN36): f1011100.i2c (GPIO UNCLAIMED) function twsi1 group mpp36
pin 37 (PIN37): f1011100.i2c (GPIO UNCLAIMED) function twsi1 group mpp37
pin 38 (PIN38): gpio_keys.2 mvebu-gpio:38 function gpio group mpp38
pin 39 (PIN39): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 40 (PIN40): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43
pin 44 (PIN44): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 45 (PIN45): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 46 (PIN46): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 47 (PIN47): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 48 (PIN48): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 49 (PIN49): (MUX UNCLAIMED) (GPIO UNCLAIMED)

Without this patch set, all pins appear to be owned by
"f1010000.pinctrl".

Even though GPIO muxing is automatically done when a device driver
requests a GPIO, Andrew Lunn and I had agreed to make the pinmuxing
explicit, in order to have correct informations in debugfs. See our
discussion at
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-March/158190.html.

The last patch finally adds support for the init button of the
Plathome OpenBlocks A6 platform.

Best regards,

Thomas

Thomas Petazzoni (21):
  arm: kirkwood: cloudbox: affect pinmux configs to the right devices
  arm: kirkwood: dlink dns: affect pinmux configs to the right devices
  arm: kirkwood: dockstar: affect pinmux configs to the right devices
  arm: kirkwood: dreamplug: affect pinmux configs to the right devices
  arm: kirkwood: goflexnet: affect pinmux configs to the right devices
  arm: kirkwood: guruplug: affect pinmux configs to the right devices
  arm: kirkwood: ib62x0: affect pinmux configs to the right devices
  arm: kirkwood: iconnect: give meaningful names to pinmux configs
  arm: kirkwood: iconnect: affect pinmux configs to the right devices
  arm: kirkwood: iomega ix2-200: affect pinmux configs to the right
    devices
  arm: kirkwood: ns2: affect pinmux configs to the right devices
  arm: kirkwood: keymile: affect pinmux configs to the right devices
  arm: kirkwood: buffalo linkstation: affect pinmux configs to the
    right devices
  arm: kirkwood: mplcec4: affect pinmux configs to the right devices
  arm: kirkwood: readynas: affect pinmux configs to the right devices
  arm: kirkwood: nsa310: affect pinmux configs to the right devices
  arm: kirkwood: openblocks_a6: affect pinmux configs to the right
    devices
  arm: kirkwood: topkick: affect pinmux configs to the right devices
  arm: kirkwood: ts219: affect pinmux configs to the right devices
  arm: kirkwood: openblocks-a6: group pinmux configurations
  arm: kirkwood: openblocks-a6: add support for Init button

 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   10 +-
 arch/arm/boot/dts/kirkwood-dns320.dts              |    7 ++
 arch/arm/boot/dts/kirkwood-dns325.dts              |    5 +
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   32 +++---
 arch/arm/boot/dts/kirkwood-dockstar.dts            |    9 +-
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   11 +-
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   18 ++--
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    8 +-
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   17 +--
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   36 +++----
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   15 +--
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |    6 +-
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   22 ++--
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   23 +++--
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   22 ++--
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   10 +-
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-nsa310.dts              |   29 +++---
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |  108 ++++++--------------
 arch/arm/boot/dts/kirkwood-topkick.dts             |   51 ++++-----
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    8 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    8 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   10 ++
 27 files changed, 235 insertions(+), 240 deletions(-)

-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:39 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:39 +0200
Subject: [PATCH 02/21] arm: kirkwood: dlink dns: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-3-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-dns320.dts |    7 +++++++
 arch/arm/boot/dts/kirkwood-dns325.dts |    5 +++++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi |   32 +++++++++++++++++---------------
 3 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index c9c44b2..14d4cee 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -17,6 +17,11 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320
+			     &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+			     &pmx_led_white_usb>;
+		pinctrl-names = "default";
+
 		blue-power {
 			label = "dns320:blue:power";
 			gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
@@ -46,6 +51,8 @@
 		};
 
 		serial at 12100 {
+			pinctrl-0 = <&pmx_uart1>;
+			pinctrl-names = "default";
 			status = "okay";
 		};
 	};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index e4e4930..6387257 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -17,6 +17,11 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
+			     &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+			     &pmx_led_white_usb>;
+		pinctrl-names = "default";
+
 		white-power {
 			label = "dns325:white:power";
 			gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac0..0afe1d0 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -9,6 +9,10 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_power &pmx_button_unmount
+			     &pmx_button_reset>;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "Power button";
 			linux,code = <116>;
@@ -29,6 +33,8 @@
 	gpio_fan {
 		/* Fan: ADDA AD045HB-G73 40mm 6000rpm at 5v */
 		compatible = "gpio-fan";
+		pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
+		pinctrl-names = "default";
 		gpios = <&gpio1 14 1
 			 &gpio1 13 1>;
 		gpio-fan,speed-map = <0    0
@@ -38,27 +44,17 @@
 
 	gpio_poweroff {
 		compatible = "gpio-poweroff";
+		pinctrl-0 = <&pmx_power_off>;
+		pinctrl-names = "default";
 		gpios = <&gpio1 4 0>;
 	};
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
 
-			pinctrl-0 = < &pmx_nand &pmx_uart1
-				      &pmx_sata0 &pmx_sata1
-				      &pmx_led_power
-				      &pmx_led_red_right_hdd
-				      &pmx_led_red_left_hdd
-				      &pmx_led_red_usb_325
-				      &pmx_button_power
-				      &pmx_led_red_usb_320
-				      &pmx_power_off &pmx_power_back_on
-				      &pmx_power_sata0 &pmx_power_sata1
-				      &pmx_present_sata0 &pmx_present_sata1
-				      &pmx_led_white_usb &pmx_fan_tacho
-				      &pmx_fan_high_speed &pmx_fan_low_speed
-				      &pmx_button_unmount &pmx_button_reset
-				      &pmx_temp_alarm >;
+			pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
+				     &pmx_present_sata1 &pmx_fan_tacho
+				     &pmx_temp_alarm>;
 			pinctrl-names = "default";
 
 			pmx_sata0: pmx-sata0 {
@@ -147,11 +143,15 @@
 			};
 		};
 		sata at 80000 {
+			pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <2>;
 		};
 
 		nand at 3000000 {
+			pinctrl-0 = <&pmx_nand>;
+			pinctrl-names = "default";
 			status = "okay";
 			chip-delay = <35>;
 
@@ -192,6 +192,8 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+		pinctrl-names = "default";
 
 		sata0_power: regulator at 1 {
 			compatible = "regulator-fixed";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:41 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:41 +0200
Subject: [PATCH 04/21] arm: kirkwood: dreamplug: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-5-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-dreamplug.dts |   11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d..3744e07 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -18,12 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_spi
-				      &pmx_led_bluetooth &pmx_led_wifi
-				      &pmx_led_wifi_ap >;
-			pinctrl-names = "default";
-
 			pmx_led_bluetooth: pmx-led-bluetooth {
 				marvell,pins = "mpp47";
 				marvell,function = "gpio";
@@ -43,6 +37,8 @@
 
 		spi at 10600 {
 			status = "okay";
+			pinctrl-0 = <&pmx_spi>;
+			pinctrl-names = "default";
 
 			m25p40 at 0 {
 				#address-cells = <1>;
@@ -84,6 +80,9 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
+			     &pmx_led_wifi_ap >;
+		pinctrl-names = "default";
 
 		bluetooth {
 			label = "dreamplug:blue:bluetooth";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:43 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:43 +0200
Subject: [PATCH 06/21] arm: kirkwood: guruplug: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-7-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97d..df830d4 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -18,11 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
-				      &pmx_led_wmode_r &pmx_led_wmode_g >;
-			pinctrl-names = "default";
-
 			pmx_led_health_r: pmx-led-health-r {
 				marvell,pins = "mpp46";
 				marvell,function = "gpio";
@@ -77,6 +72,9 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+			      &pmx_led_wmode_r &pmx_led_wmode_g >;
+		pinctrl-names = "default";
 
 		health-r {
 			label = "guruplug:red:health";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:49 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:49 +0200
Subject: [PATCH 12/21] arm: kirkwood: keymile: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-13-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Note: not sure what the pmx_i2c_gpio_sda and pmx_i2c_gpio_scl pinmux
configurations are for. Certainly for an I2C bus bit-banged over
GPIOs, but I don't see where such an I2C bus is declared in the Device
Tree.
---
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd054..66b971b 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -18,9 +18,7 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
-				&pmx_i2c_gpio_scl >;
+			pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
 			pinctrl-names = "default";
 
 			pmx_i2c_gpio_sda: pmx-gpio-sda {
@@ -38,6 +36,8 @@
 		};
 
 		nand at 3000000 {
+			pinctrl-0 = <&pmx_nand>;
+			pinctrl-names = "default";
 			status = "ok";
 			chip-delay = <25>;
 		};
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:46 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:46 +0200
Subject: [PATCH 09/21] arm: kirkwood: iconnect: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-10-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-iconnect.dts |   16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 20c3ece..0275018 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -20,14 +20,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_button_reset &pmx_button_otb
-				      &pmx_led_level &pmx_led_power_blue
-				      &pmx_led_power_red &pmx_led_usb1
-				      &pmx_led_usb2 &pmx_led_usb3
-				      &pmx_led_usb4 &pmx_led_otb >;
-			pinctrl-names = "default";
-
 			pmx_button_reset: pmx-button-reset {
 				marvell,pins = "mpp12";
 				marvell,function = "gpio";
@@ -113,6 +105,11 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
+			      &pmx_led_power_red &pmx_led_usb1
+			      &pmx_led_usb2 &pmx_led_usb3
+			      &pmx_led_usb4 &pmx_led_otb >;
+		pinctrl-names = "default";
 
 		led-level {
 			label = "led_level";
@@ -154,6 +151,9 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "OTB Button";
 			linux,code = <133>;
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:42 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:42 +0200
Subject: [PATCH 05/21] arm: kirkwood: goflexnet: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-6-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-goflexnet.dts |   18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be..31caa64 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -18,15 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
-				      &pmx_led_left_cap_0 &pmx_led_left_cap_1
-				      &pmx_led_left_cap_2 &pmx_led_left_cap_3
-				      &pmx_led_right_cap_0 &pmx_led_right_cap_1
-				      &pmx_led_right_cap_2 &pmx_led_right_cap_3
-				    >;
-			pinctrl-names = "default";
-
 			pmx_usb_power_enable: pmx-usb-power-enable {
 				marvell,pins = "mpp29";
 				marvell,function = "gpio";
@@ -109,6 +100,13 @@
 	};
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_orange
+			      &pmx_led_left_cap_0 &pmx_led_left_cap_1
+			      &pmx_led_left_cap_2 &pmx_led_left_cap_3
+			      &pmx_led_right_cap_0 &pmx_led_right_cap_1
+			      &pmx_led_right_cap_2 &pmx_led_right_cap_3
+			    >;
+		pinctrl-names = "default";
 
 		health {
 			label = "status:green:health";
@@ -156,6 +154,8 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_usb_power_enable>;
+		pinctrl-names = "default";
 
 		usb_power: regulator at 1 {
 			compatible = "regulator-fixed";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:47 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:47 +0200
Subject: [PATCH 10/21] arm: kirkwood: iomega ix2-200: affect pinmux configs to
 the right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-11-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

Note that some of the LEDs pinmux configurations are kept in the
pinctrl node, because they are not used by the gpio-leds driver.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |   15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94..00a7bfe 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -18,12 +18,7 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_button_reset &pmx_button_power
-				      &pmx_led_backup &pmx_led_power
-				      &pmx_button_otb &pmx_led_rebuild
-				      &pmx_led_health
-				      &pmx_led_sata_brt_ctrl_1
+			pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
 				      &pmx_led_sata_brt_ctrl_2
 				      &pmx_led_backup_brt_ctrl_1
 				      &pmx_led_backup_brt_ctrl_2
@@ -151,6 +146,9 @@
 	};
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_backup &pmx_led_power
+			      &pmx_led_rebuild &pmx_led_health >;
+		pinctrl-names = "default";
 
 		power_led {
 			label = "status:white:power_led";
@@ -174,6 +172,11 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_reset &pmx_button_power
+			     &pmx_button_otb>;
+		pinctrl-names = "default";
+
+
 		Power {
 			label = "Power Button";
 			linux,code = <116>;
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:44 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:44 +0200
Subject: [PATCH 07/21] arm: kirkwood: ib62x0: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-8-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-ib62x0.dts |   17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1a..20c4b08 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -18,13 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_nand
-				      &pmx_led_os_red &pmx_power_off
-				      &pmx_led_os_green &pmx_led_usb_transfer
-				      &pmx_button_reset &pmx_button_usb_copy >;
-			pinctrl-names = "default";
-
 			pmx_led_os_red: pmx-led-os-red {
 				marvell,pins = "mpp22";
 				marvell,function = "gpio";
@@ -61,6 +54,8 @@
 
 		nand at 3000000 {
 			status = "okay";
+			pinctrl-0 = <&pmx_nand>;
+			pinctrl-names = "default";
 
 			partition at 0 {
 				label = "u-boot";
@@ -84,6 +79,9 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "USB Copy";
 			linux,code = <133>;
@@ -97,6 +95,9 @@
 	};
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
+			     &pmx_led_usb_transfer>;
+		pinctrl-names = "default";
 
 		green-os {
 			label = "ib62x0:green:os";
@@ -114,6 +115,8 @@
 	};
 	gpio_poweroff {
 		compatible = "gpio-poweroff";
+		pinctrl-0 = <&pmx_power_off>;
+		pinctrl-names = "default";
 		gpios = <&gpio0 24 0>;
 	};
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:45 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:45 +0200
Subject: [PATCH 08/21] arm: kirkwood: iconnect: give meaningful names to
 pinmux configs
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-9-git-send-email-thomas.petazzoni@free-electrons.com>

The Kirkwood iConnect Device Tree is currently using totally
meaningless names for the pinmux configuration: pmx_gpio_XY.

This patch fixes that by using some more meaningful names such as
pmx_button_power.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-iconnect.dts |   30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74..20c3ece 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -21,50 +21,50 @@
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
 
-			pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
-				      &pmx_gpio_41 &pmx_gpio_42
-				      &pmx_gpio_43 &pmx_gpio_44
-				      &pmx_gpio_45 &pmx_gpio_46
-				      &pmx_gpio_47 &pmx_gpio_48 >;
+			pinctrl-0 = < &pmx_button_reset &pmx_button_otb
+				      &pmx_led_level &pmx_led_power_blue
+				      &pmx_led_power_red &pmx_led_usb1
+				      &pmx_led_usb2 &pmx_led_usb3
+				      &pmx_led_usb4 &pmx_led_otb >;
 			pinctrl-names = "default";
 
-			pmx_gpio_12: pmx-gpio-12 {
+			pmx_button_reset: pmx-button-reset {
 				marvell,pins = "mpp12";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_35: pmx-gpio-35 {
+			pmx_button_otb: pmx-button-otb {
 				marvell,pins = "mpp35";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_41: pmx-gpio-41 {
+			pmx_led_level: pmx-led-level {
 				marvell,pins = "mpp41";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_42: pmx-gpio-42 {
+			pmx_led_power_blue: pmx-led-power-blue {
 				marvell,pins = "mpp42";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_43: pmx-gpio-43 {
+			pmx_led_power_red: pmx-power-red {
 				marvell,pins = "mpp43";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_44: pmx-gpio-44 {
+			pmx_led_usb1: pmx-led-usb1 {
 				marvell,pins = "mpp44";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_45: pmx-gpio-45 {
+			pmx_led_usb2: pmx-led-usb2 {
 				marvell,pins = "mpp45";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_46: pmx-gpio-46 {
+			pmx_led_usb3: pmx-led-usb3 {
 				marvell,pins = "mpp46";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_47: pmx-gpio-47 {
+			pmx_led_usb4: pmx-led-usb4 {
 				marvell,pins = "mpp47";
 				marvell,function = "gpio";
 			};
-			pmx_gpio_48: pmx-gpio-48 {
+			pmx_led_otb: pmx-led-otb {
 				marvell,pins = "mpp48";
 				marvell,function = "gpio";
 			};
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:48 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:48 +0200
Subject: [PATCH 11/21] arm: kirkwood: ns2: affect pinmux configs to the right
 devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-12-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-is2.dts         |    2 ++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi |   10 ++++++----
 arch/arm/boot/dts/kirkwood-ns2.dts         |    2 ++
 arch/arm/boot/dts/kirkwood-ns2lite.dts     |    2 ++
 arch/arm/boot/dts/kirkwood-ns2max.dts      |    2 ++
 arch/arm/boot/dts/kirkwood-ns2mini.dts     |    2 ++
 6 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0a..c3f036b 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -13,6 +13,8 @@
 
 	ocp at f1000000 {
 		sata at 80000 {
+			pinctrl-0 = <&pmx_ns2_sata0>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <1>;
 		};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd92..2afac04 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -8,10 +8,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-			pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
-					&pmx_ns2_sata0 &pmx_ns2_sata1>;
-			pinctrl-names = "default";
-
 			pmx_ns2_sata0: pmx-ns2-sata0 {
 				marvell,pins = "mpp21";
 				marvell,function = "sata0";
@@ -23,10 +19,14 @@
 		};
 
 		serial at 12000 {
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
 			status = "okay";
 		};
 
 		spi at 10600 {
+			pinctrl-0 = <&pmx_spi>;
+			pinctrl-names = "default";
 			status = "okay";
 
 			flash at 0 {
@@ -45,6 +45,8 @@
 		};
 
 		i2c at 11000 {
+			pinctrl-0 = <&pmx_twsi0>;
+			pinctrl-names = "default";
 			status = "okay";
 
 			eeprom at 50 {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf..b50e93d 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -13,6 +13,8 @@
 
 	ocp at f1000000 {
 		sata at 80000 {
+			pinctrl-0 = <&pmx_ns2_sata0>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <1>;
 		};
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4e..af8259f 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -13,6 +13,8 @@
 
 	ocp at f1000000 {
 		sata at 80000 {
+			pinctrl-0 = <&pmx_ns2_sata0>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <1>;
 		};
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6..85f24d2 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -13,6 +13,8 @@
 
 	ocp at f1000000 {
 		sata at 80000 {
+			pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <2>;
 		};
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab..329e530 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -14,6 +14,8 @@
 
 	ocp at f1000000 {
 		sata at 80000 {
+			pinctrl-0 = <&pmx_ns2_sata0>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <1>;
 		};
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:54 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:54 +0200
Subject: [PATCH 17/21] arm: kirkwood: openblocks_a6: affect pinmux configs to
 the right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-18-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts |   26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f724..a05b382 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -19,15 +19,21 @@
 	ocp at f1000000 {
 		serial at 12000 {
 			status = "ok";
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
 		};
 
 		serial at 12100 {
 			status = "ok";
+			pinctrl-0 = <&pmx_uart1>;
+			pinctrl-names = "default";
 		};
 
 		nand at 3000000 {
 			chip-delay = <25>;
 			status = "okay";
+			pinctrl-0 = <&pmx_nand>;
+			pinctrl-names = "default";
 
 			partition at 0 {
 				label = "uboot";
@@ -67,6 +73,8 @@
 
 		i2c at 11100 {
 			status = "okay";
+			pinctrl-0 = <&pmx_twsi1>;
+			pinctrl-names = "default";
 
 			s35390a: s35390a at 30 {
 				compatible = "s35390a";
@@ -75,16 +83,12 @@
 		};
 
 		pinctrl: pinctrl at 10000 {
-			pinctrl-0 = < &pmx_nand &pmx_uart0
-				&pmx_uart1 &pmx_twsi1
-				&pmx_dip_sw0 &pmx_dip_sw1
-				&pmx_dip_sw2 &pmx_dip_sw3
-				&pmx_gpio_0 &pmx_gpio_1
-				&pmx_gpio_2 &pmx_gpio_3
-				&pmx_gpio_4 &pmx_gpio_5
-				&pmx_gpio_6 &pmx_gpio_7
-				&pmx_led_red &pmx_led_green
-				&pmx_led_yellow >;
+			pinctrl-0 = <&pmx_dip_sw0 &pmx_dip_sw1
+				     &pmx_dip_sw2 &pmx_dip_sw3
+				     &pmx_gpio_0 &pmx_gpio_1
+				     &pmx_gpio_2 &pmx_gpio_3
+				     &pmx_gpio_4 &pmx_gpio_5
+				     &pmx_gpio_6 &pmx_gpio_7>;
 			pinctrl-names = "default";
 
 			pmx_uart0: pmx-uart0 {
@@ -193,6 +197,8 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_red &pmx_led_green &pmx_led_yellow>;
+		pinctrl-names = "default";
 
 		led-red {
 			label = "obsa6:red:stat";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:51 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:51 +0200
Subject: [PATCH 14/21] arm: kirkwood: mplcec4: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-15-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-mplcec4.dts |   23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..1ce1bc6 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -18,16 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_nand &pmx_uart0
-				      &pmx_led_health
-				      &pmx_sata0 &pmx_sata1
-				      &pmx_led_user1o
-				      &pmx_led_user1g &pmx_led_user0o
-				      &pmx_led_user0g &pmx_led_misc
-				    >;
-			pinctrl-names = "default";
-
 			pmx_led_health: pmx-led-health {
 				marvell,pins = "mpp7";
 				marvell,function = "gpo";
@@ -91,9 +81,13 @@
 
                 serial at 12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 nand at 3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         partition at 0 {
@@ -127,9 +121,10 @@
 		};
 
 		sata at 80000 {
+			pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+			pinctrl-names = "default";
 			nr-ports = <2>;
 			status = "okay";
-
 		};
 
 		mvsdio at 90000 {
@@ -143,6 +138,12 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_health
+			      &pmx_led_user1o
+			      &pmx_led_user1g &pmx_led_user0o
+			      &pmx_led_user0g &pmx_led_misc
+			    >;
+		pinctrl-names = "default";
 
 		health {
 			label = "status:green:health";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:53 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:53 +0200
Subject: [PATCH 16/21] arm: kirkwood: nsa310: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-17-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-nsa310.dts |   29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index a7412b9..79391ca 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -17,22 +17,7 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-			pinctrl-0 = < &pmx_led_esata_green
-				      &pmx_led_esata_red
-				      &pmx_led_usb_green
-				      &pmx_led_usb_red
-				      &pmx_usb_power_off
-				      &pmx_led_sys_green
-				      &pmx_led_sys_red
-				      &pmx_btn_reset
-				      &pmx_btn_copy
-				      &pmx_led_copy_green
-				      &pmx_led_copy_red
-				      &pmx_led_hdd_green
-				      &pmx_led_hdd_red
-				      &pmx_unknown
-				      &pmx_btn_power
-				      &pmx_pwr_off >;
+			pinctrl-0 = <&pmx_unknown>;
 			pinctrl-names = "default";
 
 			pmx_led_esata_green: pmx-led-esata-green {
@@ -182,6 +167,8 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
+		pinctrl-names = "default";
 
 		button at 1 {
 			label = "Power Button";
@@ -202,6 +189,12 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red
+			     &pmx_led_usb_green &pmx_led_usb_red
+			     &pmx_led_sys_green &pmx_led_sys_red
+			     &pmx_led_copy_green &pmx_led_copy_red
+			     &pmx_led_hdd_green &pmx_led_hdd_red>;
+		pinctrl-names = "default";
 
 		green-sys {
 			label = "nsa310:green:sys";
@@ -247,6 +240,8 @@
 
 	gpio_poweroff {
 		compatible = "gpio-poweroff";
+		pinctrl-0 = <&pmx_pwr_off>;
+		pinctrl-names = "default";
 		gpios = <&gpio1 16 0>;
 	};
 
@@ -254,6 +249,8 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_usb_power_off>;
+		pinctrl-names = "default";
 
 		usb0_power_off: regulator at 1 {
 			compatible = "regulator-fixed";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:56 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:56 +0200
Subject: [PATCH 19/21] arm: kirkwood: ts219: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-20-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-ts219-6281.dts |    8 ++++----
 arch/arm/boot/dts/kirkwood-ts219-6282.dts |    8 ++++----
 arch/arm/boot/dts/kirkwood-ts219.dtsi     |   10 ++++++++++
 3 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c83..a2a90c4 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -7,10 +7,7 @@
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
 
-			pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-				      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-				      &pmx_ram_size &pmx_reset_button
-				      &pmx_USB_copy_button &pmx_board_id>;
+			pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
 			pinctrl-names = "default";
 
 			pmx_ram_size: pmx-ram-size {
@@ -38,6 +35,9 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "USB Copy";
 			linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95d..a4554cb 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -7,10 +7,7 @@
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
 
-			pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-				      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-				      &pmx_ram_size &pmx_reset_button
-				      &pmx_USB_copy_button &pmx_board_id>;
+			pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
 			pinctrl-names = "default";
 
 			pmx_ram_size: pmx-ram-size {
@@ -38,6 +35,9 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "USB Copy";
 			linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..b9325d4 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -17,6 +17,8 @@
 		i2c at 11000 {
 			status = "okay";
 			clock-frequency = <400000>;
+			pinctrl-0 = <&pmx_twsi0>;
+			pinctrl-names = "default";
 
 			s35390a: s35390a at 30 {
 				compatible = "s35390a";
@@ -26,13 +28,19 @@
 		serial at 12000 {
 			clock-frequency = <200000000>;
 			status = "okay";
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
 		};
 		serial at 12100 {
 			clock-frequency = <200000000>;
 			status = "okay";
+			pinctrl-0 = <&pmx_uart1>;
+			pinctrl-names = "default";
 		};
 		spi at 10600 {
 			status = "okay";
+			pinctrl-0 = <&pmx_spi>;
+			pinctrl-names = "default";
 
 			m25p128 at 0 {
 				#address-cells = <1>;
@@ -71,6 +79,8 @@
 			};
 		};
 		sata at 80000 {
+			pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+			pinctrl-names = "default";
 			status = "okay";
 			nr-ports = <2>;
 		};
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:58 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:58 +0200
Subject: [PATCH 21/21] arm: kirkwood: openblocks-a6: add support for Init
 button
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-22-git-send-email-thomas.petazzoni@free-electrons.com>

The Kirkwood-based PlatHome OpenBlocks A6 board has an Init button
connected to MPP pin 38. This commit adds support for this button.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 56e3161..38dc851 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -151,4 +151,18 @@
 			gpios = <&gpio1 11 1>;
 		};
         };
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_gpio_init>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		button at 1 {
+			label = "Init Button";
+			linux,code = <116>;
+			gpios = <&gpio1 6 0>;
+		};
+	};
 };
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:50 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:50 +0200
Subject: [PATCH 13/21] arm: kirkwood: buffalo linkstation: affect pinmux
 configs to the right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-14-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-lsxl.dtsi |   22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4..4945eba 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -8,16 +8,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
-				      &pmx_fan_low &pmx_fan_high
-				      &pmx_led_function_red &pmx_led_alarm
-				      &pmx_led_info &pmx_led_power
-				      &pmx_fan_lock &pmx_button_function
-				      &pmx_power_switch &pmx_power_auto_switch
-				      &pmx_led_function_blue >;
-			pinctrl-names = "default";
-
 			pmx_power_hdd: pmx-power-hdd {
 				marvell,pins = "mpp10";
 				marvell,function = "gpo";
@@ -112,6 +102,10 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_function &pmx_power_switch
+			     &pmx_power_auto_switch>;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "Function Button";
 			linux,code = <357>;
@@ -133,6 +127,10 @@
 
 	gpio_leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+			     &pmx_led_info &pmx_led_power
+			     &pmx_led_function_blue>;
+		pinctrl-names = "default";
 
 		led at 1 {
 			label = "lsxl:blue:func";
@@ -163,6 +161,8 @@
 
 	gpio_fan {
 		compatible = "gpio-fan";
+		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+		pinctrl-names = "default";
 		gpios = <&gpio0 19 1
 		         &gpio0 18 1>;
 		gpio-fan,speed-map = <0    3
@@ -176,6 +176,8 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>;
+		pinctrl-names = "default";
 
 		usb_power: regulator at 1 {
 			compatible = "regulator-fixed";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:52 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:52 +0200
Subject: [PATCH 15/21] arm: kirkwood: readynas: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-16-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   22 +++++++++-----------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab..b79ea8c 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -18,18 +18,6 @@
 
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
-
-			pinctrl-0 = < &pmx_uart0
-				      &pmx_button_power
-				      &pmx_button_backup
-				      &pmx_button_reset
-				      &pmx_led_blue_power
-				      &pmx_led_blue_activity
-				      &pmx_led_blue_disk1
-				      &pmx_led_blue_disk2
-				      &pmx_led_blue_backup >;
-			pinctrl-names = "default";
-
 			pmx_button_power: pmx-button-power {
 				marvell,pins = "mpp47";
 				marvell,function = "gpio";
@@ -74,6 +62,8 @@
 		};
 
 		serial at 12000 {
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
 			status = "okay";
 		};
 
@@ -115,6 +105,10 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
+			      &pmx_led_blue_disk1 &pmx_led_blue_disk2
+			      &pmx_led_blue_backup >;
+		pinctrl-names = "default";
 
 		power_led {
 			label = "status:blue:power_led";
@@ -143,6 +137,10 @@
 		compatible = "gpio-keys";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_power &pmx_button_backup
+			     &pmx_button_reset>;
+		pinctrl-names = "default";
+
 		button at 1 {
 			label = "Power Button";
 			linux,code = <116>;     /* KEY_POWER */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:55 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:55 +0200
Subject: [PATCH 18/21] arm: kirkwood: topkick: affect pinmux configs to the
 right devices
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-19-git-send-email-thomas.petazzoni@free-electrons.com>

When the pinmux mechanism was added in Kirkwood, the device driver
core was not yet providing the possibility of attaching pinmux
configurations to all devices, drivers had to do it explicitly, and
not all drivers were doing this.

Now that the driver core does that in a generic way, it makes sense to
attach the pinmux configuration to their corresponding devices.

This allows the pinctrl subsystem to show in debugfs to which device
is related which pins, for example:

pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-topkick.dts |   51 ++++++++++++++++----------------
 1 file changed, 26 insertions(+), 25 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b..940b54f 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -19,18 +19,6 @@
 	ocp at f1000000 {
 		pinctrl: pinctrl at 10000 {
 			/*
-			 * GPIO LED layout
-			 *
-			 *       /-SYS_LED(2)
-			 *       |
-			 *       |   /-DISK_LED
-			 *       |   |
-			 *       |   |   /-WLAN_LED(2)
-			 *       |   |   |
-			 * [SW] [*] [*] [*]
-			 */
-
-			/*
 			 * Switch positions
 			 *
 			 *     /-SW_LEFT(2)
@@ -41,19 +29,8 @@
 			 *     |   |   |
 			 * PS [L] [I] [R] LEDS
 			 */
-			pinctrl-0 = < &pmx_led_disk_yellow
-				      &pmx_sata0_pwr_enable
-				      &pmx_led_sys_red
-				      &pmx_led_sys_blue
-				      &pmx_led_wifi_green
-				      &pmx_sw_left
-				      &pmx_sw_right
-				      &pmx_sw_idle
-				      &pmx_sw_left2
-				      &pmx_led_wifi_yellow
-				      &pmx_uart0
-				      &pmx_nand
-				      &pmx_twsi0 >;
+			pinctrl-0 = <&pmx_sw_left &pmx_sw_right
+				     &pmx_sw_idle &pmx_sw_left2>;
 			pinctrl-names = "default";
 
 			pmx_led_disk_yellow: pmx-led-disk-yellow {
@@ -109,10 +86,14 @@
 
 		serial at 12000 {
 			status = "ok";
+			pinctrl-0 = <&pmx_uart0>;
+			pinctrl-names = "default";
 		};
 
 		nand at 3000000 {
 			status = "okay";
+			pinctrl-0 = <&pmx_nand>;
+			pinctrl-names = "default";
 
 			partition at 0 {
 				label = "u-boot";
@@ -147,6 +128,8 @@
 
 		i2c at 11000 {
 			status = "ok";
+			pinctrl-0 = <&pmx_twsi0>;
+			pinctrl-names = "default";
 		};
 
 		mvsdio at 90000 {
@@ -158,7 +141,23 @@
 	};
 
 	gpio-leds {
+		/*
+		 * GPIO LED layout
+		 *
+		 *       /-SYS_LED(2)
+		 *       |
+		 *       |   /-DISK_LED
+		 *       |   |
+		 *       |   |   /-WLAN_LED(2)
+		 *       |   |   |
+		 * [SW] [*] [*] [*]
+		 */
+
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
+			     &pmx_led_sys_blue &pmx_led_wifi_green
+			     &pmx_led_wifi_yellow>;
+		pinctrl-names = "default";
 
 		disk {
 			label = "topkick:yellow:disk";
@@ -187,6 +186,8 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-0 = <&pmx_sata0_pwr_enable>;
+		pinctrl-names = "default";
 
 		sata0_power: regulator at 1 {
 			compatible = "regulator-fixed";
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri May 24 05:44:57 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 May 2013 11:44:57 +0200
Subject: [PATCH 20/21] arm: kirkwood: openblocks-a6: group pinmux
 configurations
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1369388699-25975-21-git-send-email-thomas.petazzoni@free-electrons.com>

Instead of having one separate pinmux configuration for each LED, for
each GPIO of the GPIO header, for each DIP switch, this patch groups
them together in configurations that make sense together: LEDs on one
side, GPIOs of the GPIO header on another side, and DIP switches on
yet another side.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts |   82 +++-----------------------
 1 file changed, 9 insertions(+), 73 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index a05b382..56e3161 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -83,12 +83,7 @@
 		};
 
 		pinctrl: pinctrl at 10000 {
-			pinctrl-0 = <&pmx_dip_sw0 &pmx_dip_sw1
-				     &pmx_dip_sw2 &pmx_dip_sw3
-				     &pmx_gpio_0 &pmx_gpio_1
-				     &pmx_gpio_2 &pmx_gpio_3
-				     &pmx_gpio_4 &pmx_gpio_5
-				     &pmx_gpio_6 &pmx_gpio_7>;
+			pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
 			pinctrl-names = "default";
 
 			pmx_uart0: pmx-uart0 {
@@ -108,63 +103,14 @@
 				marvell,function = "sysrst";
 			};
 
-			pmx_dip_sw0: pmx-dip-sw0 {
-				marvell,pins = "mpp20";
+			pmx_dip_switches: pmx-dip-switches {
+				marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23";
 				marvell,function = "gpio";
 			};
 
-			pmx_dip_sw1: pmx-dip-sw1 {
-				marvell,pins = "mpp21";
-				marvell,function = "gpio";
-			};
-
-			pmx_dip_sw2: pmx-dip-sw2 {
-				marvell,pins = "mpp22";
-				marvell,function = "gpio";
-			};
-
-			pmx_dip_sw3: pmx-dip-sw3 {
-				marvell,pins = "mpp23";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_0: pmx-gpio-0 {
-				marvell,pins = "mpp24";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_1: pmx-gpio-1 {
-				marvell,pins = "mpp25";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_2: pmx-gpio-2 {
-				marvell,pins = "mpp26";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_3: pmx-gpio-3 {
-				marvell,pins = "mpp27";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_4: pmx-gpio-4 {
-				marvell,pins = "mpp28";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_5: pmx-gpio-5 {
-				marvell,pins = "mpp29";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_6: pmx-gpio-6 {
-				marvell,pins = "mpp30";
-				marvell,function = "gpio";
-			};
-
-			pmx_gpio_7: pmx-gpio-7 {
-				marvell,pins = "mpp31";
+			pmx_gpio_header: pmx-gpio-header {
+				marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27",
+					       "mpp28", "mpp29", "mpp30", "mpp31";
 				marvell,function = "gpio";
 			};
 
@@ -178,18 +124,8 @@
 				marvell,function = "gpio";
 			};
 
-			pmx_led_red: pmx-led-red {
-				marvell,pins = "mpp41";
-				marvell,function = "gpio";
-			};
-
-			pmx_led_green: pmx-led-green {
-				marvell,pins = "mpp42";
-				marvell,function = "gpio";
-			};
-
-			pmx_led_yellow: pmx-led-yellow {
-				marvell,pins = "mpp43";
+			pmx_leds: pmx-leds {
+				marvell,pins = "mpp41", "mpp42", "mpp43";
 				marvell,function = "gpio";
 			};
 		};
@@ -197,7 +133,7 @@
 
 	gpio-leds {
 		compatible = "gpio-leds";
-		pinctrl-0 = <&pmx_led_red &pmx_led_green &pmx_led_yellow>;
+		pinctrl-0 = <&pmx_leds>;
 		pinctrl-names = "default";
 
 		led-red {
-- 
1.7.9.5



From magnus.damm at gmail.com  Fri May 24 05:47:24 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Fri, 24 May 2013 18:47:24 +0900
Subject: [PATCH v2] gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
Message-ID: <20130524094724.1510.80331.sendpatchset@w520>

From: Simon Horman <horms+renesas at verge.net.au>

As hardware support for this feature is not universal for all SoCs a flag,
has_both_edge_trigger, has been added to the platform data of the driver to
allow this feature to be enabled.

The motivation for this is to allow use of the gpio-keys driver on the
lager board which is based on the r8a7790 SoC. The V2 of this patch has been
fully exercised using that driver on that board.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
Signed-off-by: Magnus Damm <damm at opensource.se>
---

 Changes since V1:
 - Modified code to always set BOTHEDGE register if available
 - Set BOTHEDGE before IOINTSEL
 - Successfully tested triggering on both edges with SW2 on Lager

 drivers/gpio/gpio-rcar.c                |   26 +++++++++++++++++++++-----
 include/linux/platform_data/gpio-rcar.h |    1 +
 2 files changed, 22 insertions(+), 5 deletions(-)

--- 0001/drivers/gpio/gpio-rcar.c
+++ work/drivers/gpio/gpio-rcar.c	2013-05-24 18:39:54.000000000 +0900
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 						  unsigned int hwirq,
 						  bool active_high_rising_edge,
-						  bool level_trigger)
+						  bool level_trigger,
+						  bool both)
 {
 	unsigned long flags;
 
@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_i
 	/* Configure edge or level trigger in EDGLEVEL */
 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 
+	/* Select one edge or both edges in BOTHEDGE */
+	if (p->config.has_both_edge_trigger)
+		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
+
 	/* Select "Interrupt Input Mode" in IOINTSEL */
 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_LEVEL_HIGH:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+						      false);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+						      false);
 		break;
 	case IRQ_TYPE_EDGE_RISING:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+						      false);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+						      false);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		if (!p->config.has_both_edge_trigger)
+			return -EINVAL;
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+						      true);
 		break;
 	default:
 		return -EINVAL;
--- 0001/include/linux/platform_data/gpio-rcar.h
+++ work/include/linux/platform_data/gpio-rcar.h	2013-05-24 18:25:06.000000000 +0900
@@ -21,6 +21,7 @@ struct gpio_rcar_config {
 	unsigned int irq_base;
 	unsigned int number_of_pins;
 	const char *pctl_name;
+	unsigned has_both_edge_trigger:1;
 };
 
 #define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))


From Mylene.Josserand at navocap.com  Fri May 24 05:52:54 2013
From: Mylene.Josserand at navocap.com (Mylene Josserand)
Date: Fri, 24 May 2013 11:52:54 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <20130524110706.6052493e@endymion.delvare>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
 <CA78C307B8F06747967D122FC656B15398644A@SERVEUR0.nvp.local>
 <20130524110706.6052493e@endymion.delvare>
Message-ID: <CA78C307B8F06747967D122FC656B15398644B@SERVEUR0.nvp.local>

Le 24/05/2013 11:07, Jean Delvare a ?crit :
 > On Fri, 24 May 2013 10:54:11 +0200, Mylene Josserand wrote:
 >> Ah okay ! And if there are not SMBus compliant, what function I will
 >> have to use ?
 >
 > i2c_transfer()


Okay, logic name ;)


 >> What is it doing if I use this function and that my device is not SMbus
 >> compliant ?
 >
 > This would make no sense. Your device understands only specific message
 > formats, which should be documented in its datasheet. You have to use
 > exactly that in your driver. If the message format matches SMBus, you
 > can use the SMBus API, otherwise you must use i2c_transfer() instead.

Very interesting !
Right now, my company uses the "i2c_smbus_read/write_byte_data" 
functions to talk to devices through an application. On the datasheet of 
these devices, I search but did not seem to be SMBus compliant.
As it was a software which was using these functions, we thought that a 
driver (that I would write) should be better. And here I am ! I prefer 
to understand well the mechanism before coding anything and it is 
interesting !


 >> I have some difficulties to understand the differences
 >> between SMbus and I2C :(
 >
 > SMBus is a subset of I2C. With I2C you can have messages of any length
 > and any format, with no attached semantics. SMBus restricts the
 > possibilities to a few standardized messages formats with semantics. If
 > you'd just tell us what your device is, we would be able to tell you if
 > SMBus will work or if I2C will be needed.

Thanks for the explanation.
No problem, we have 2 devices used without drivers :
- an odometer PIC18F24201 : In the datasheet, there is a SMBus select 
bit but I don't know if it is SMBus compliant.
- an audio codec tlv320aic3204 : There is a driver for this device but 
for some reasons, we did not use it. Did not find a "SMBus compliant" in 
its datasheet.


 >> (...)
 >> In my case, I have 2 segments but if I understand, the bus will not be
 >> used at the same time.
 >
 > I can't comment on that without knowing the exact topology. In
 > particular, do you have two independent segments each with its own
 > controller, or are they interconnected in some way? I2C/SMBus is very
 > simple with basic topologies but can become difficult with complex ones.

Yes of course, I understand.
For that, I will ask to our "hardware guy".


 >> (...)
 >> Okay. So the mutex blocks the I2C bus. And is it locking the bus at the
 >> beginning of a message (so when a START is send) and unlocking it after
 >> the STOP ?
 >
 > Yes.
 >
 >> So a complete message will be sent to a same device (the one which
 >> address is in the data frame) ? A device can not receive a beginning of
 >> one message (so with his address) and the end of another message
 >> destined to another device [because of "collision"], for example ?
 >
 > No, this cannot happen.


Thanks a lot for your help !


-- 
Myl?ne JOSSERAND


From maxime.ripard at free-electrons.com  Fri May 24 05:58:19 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 11:58:19 +0200
Subject: [PATCH RESEND 0/5] Add I2C support for Allwinner SoCs
In-Reply-To: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130524095819.GB8785@lukather>

Hi Wolfram,

On Fri, May 03, 2013 at 11:17:44AM +0200, Maxime Ripard wrote:
> Hi,
> 
> This patchset adds support for the I2C controller found on most of the
> Allwinner SoCs, especially the already supported A10 and A13, and the
> yet to come A31.
> 
> It has been tested on a A13-Olinuxino.
> 
> Thanks,
> Maxime
> 
> Resent to fix Wolfram's email address.

Do you have comments on this driver?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From b.brezillon at overkiz.com  Fri May 24 06:05:56 2013
From: b.brezillon at overkiz.com (Boris BREZILLON)
Date: Fri, 24 May 2013 12:05:56 +0200
Subject: [PATCH] ARM: at91/dt: add pinctrl definition for at91 tc blocks
Message-ID: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>

Hello,

This patch adds pinctrl configs for at91 Timer Conter blocks.
These pin configs will be referenced by "atmel,tcb-pwm" devices to
setup pins as PWM output.

Best Regards,

Boris

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
---
 arch/arm/boot/dts/at91rm9200.dtsi  |   76 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9260.dtsi |   76 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi |   38 ++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |   76 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi |   76 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |   76 ++++++++++++++++++++++++++++++++++++
 6 files changed, 418 insertions(+)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..a90ec44 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -391,6 +391,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <0 13 0x2 0x0>;	/* PA13 periph B */
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <0 14 0x2 0x0>;	/* PA14 periph B */
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <0 15 0x2 0x0>;	/* PA15 periph B */
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <0 17 0x2 0x0>;	/* PA17 periph B */
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <0 19 0x2 0x0>;	/* PA19 periph B */
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <0 21 0x2 0x0>;	/* PA21 periph B */
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <0 18 0x2 0x0>;	/* PA18 periph B */
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <0 20 0x2 0x0>;	/* PA20 periph B */
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <0 22 0x2 0x0>;	/* PA22 periph B */
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <0 27 0x2 0x0>;	/* PA27 periph B */
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <0 28 0x2 0x0>;	/* PA28 periph B */
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <0 29 0x2 0x0>;	/* PA29 periph B */
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <1 6 0x2 0x0>;	/* PB6 periph B */
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <1 8 0x2 0x0>;	/* PB8 periph B */
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <1 10 0x2 0x0>;	/* PB10 periph B */
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <1 7 0x2 0x0>;	/* PB7 periph B */
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <1 9 0x2 0x0>;	/* PB9 periph B */
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <1 11 0x2 0x0>;	/* PB11 periph B */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..b2665b1 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -340,6 +340,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <0 25 0x1 0x0>;	/* PA25 periph A */
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <1 6 0x2 0x0>;	/* PB6 periph B */
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <1 7 0x2 0x0>;	/* PB7 periph B */
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <0 26 0x1 0x0>;	/* PA26 periph A */
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <0 27 0x1 0x0>;	/* PA27 periph A */
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <0 28 0x1 0x0>;	/* PA28 periph A */
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <2 9 0x2 0x0>;	/* PC9 periph B */
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <2 7 0x1 0x0>;	/* PC7 periph A */
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <2 6 0x1 0x0>;	/* PC6 periph A */
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <1 16 0x2 0x0>;	/* PB16 periph B */
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <1 17 0x2 0x0>;	/* PB17 periph B */
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <2 22 0x2 0x0>;	/* PC22 periph B */
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <1 0 0x2 0x0>;	/* PB0 periph B */
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <1 2 0x2 0x0>;	/* PB2 periph B */
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <1 3 0x2 0x0>;	/* PB3 periph B */
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <1 1 0x2 0x0>;	/* PB1 periph B */
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <1 18 0x2 0x0>;	/* PB18 periph B */
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <1 19 0x2 0x0>;	/* PB19 periph B */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab..82d2609 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -321,6 +321,44 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <1 28 0x2 0x0>;	/* PB28 periph B */
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <2 28 0x2 0x0>;	/* PC28 periph B */
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <0 15 0x1 0x0>;	/* PA15 periph A */
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <4 18 0x2 0x0>;	/* PE18 periph B */
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <4 8 0x2 0x0>;	/* PE8 periph B */
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <1 17 0x2 0x0>;	/* PB17 periph B */
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <4 19 0x2 0x0>;	/* PE19 periph B */
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <4 9 0x2 0x0>;	/* PE9 periph B */
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <1 18 0x2 0x0>;	/* PB18 periph B */
+					};
+				};
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a73..6ae0089 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -341,6 +341,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <3 23 0x1 0x0>;	/* PD23 periph A */
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <3 29 0x1 0x0>;	/* PD29 periph A */
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <2 10 0x2 0x0>;	/* PC10 periph B */
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <3 20 0x1 0x0>;	/* PD20 periph A */
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <3 21 0x1 0x0>;	/* PD21 periph A */
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <3 22 0x1 0x0>;	/* PD22 periph A */
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <3 30 0x1 0x0>;	/* PD30 periph A */
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <3 31 0x1 0x0>;	/* PD31 periph A */
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <0 26 0x2 0x0>;	/* PA26 periph B */
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <0 0 0x2 0x0>;	/* PA0 periph B */
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <0 3 0x2 0x0>;	/* PA3 periph B */
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <3 9 0x2 0x0>;	/* PD9 periph B */
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <0 1 0x2 0x0>;	/* PA1 periph B */
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <0 4 0x2 0x0>;	/* PA4 periph B */
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <3 7 0x2 0x0>;	/* PD7 periph B */
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <0 2 0x2 0x0>;	/* PA2 periph B */
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <0 5 0x2 0x0>;	/* PA5 periph B */
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <3 8 0x2 0x0>;	/* PD8 periph B */
+					};
+				};
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3de8e6d..c3ba293 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -282,6 +282,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <0 24 0x1 0x0>;	/* PA24 periph A */
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <0 25 0x1 0x0>;	/* PA25 periph A */
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <0 26 0x1 0x0>;	/* PA26 periph A */
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <0 21 0x1 0x0>;	/* PA21 periph A */
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <0 22 0x1 0x0>;	/* PA22 periph A */
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <0 23 0x1 0x0>;	/* PA23 periph A */
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <0 27 0x1 0x0>;	/* PA27 periph A */
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <0 28 0x1 0x0>;	/* PA28 periph A */
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <0 29 0x1 0x0>;	/* PA29 periph A */
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <2 4 0x3 0x0>;	/* PC4 periph C */
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <2 7 0x3 0x0>;	/* PC7 periph C */
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <2 14 0x3 0x0>;	/* PC14 periph C */
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <2 2 0x3 0x0>;	/* PC2 periph C */
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <2 5 0x3 0x0>;	/* PC5 periph C */
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <2 12 0x3 0x0>;	/* PC12 periph C */
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <2 3 0x3 0x0>;	/* PC3 periph C */
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <2 6 0x3 0x0>;	/* PC6 periph C */
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <2 13 0x3 0x0>;	/* PC13 periph C */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..bee58c6 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -411,6 +411,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <0 24 0x1 0x0>;	/* PA24 periph A */
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <0 25 0x1 0x0>;	/* PA25 periph A */
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <0 26 0x1 0x0>;	/* PA26 periph A */
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <0 21 0x1 0x0>;	/* PA21 periph A */
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <0 22 0x1 0x0>;	/* PA22 periph A */
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <0 23 0x1 0x0>;	/* PA23 periph A */
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <0 27 0x1 0x0>;	/* PA27 periph A */
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <0 28 0x1 0x0>;	/* PA28 periph A */
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <0 29 0x1 0x0>;	/* PA29 periph A */
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <2 4 0x3 0x0>;	/* PC4 periph C */
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <2 7 0x3 0x0>;	/* PC7 periph C */
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <2 14 0x3 0x0>;	/* PC14 periph C */
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <2 2 0x3 0x0>;	/* PC2 periph C */
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <2 5 0x3 0x0>;	/* PC5 periph C */
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <2 12 0x3 0x0>;	/* PC12 periph C */
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <2 3 0x3 0x0>;	/* PC3 periph C */
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <2 6 0x3 0x0>;	/* PC6 periph C */
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <2 13 0x3 0x0>;	/* PC13 periph C */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-- 
1.7.9.5



From maxime.ripard at free-electrons.com  Fri May 24 06:14:19 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 12:14:19 +0200
Subject: [PATCHv3 2/6] net: Add MDIO bus driver for the Allwinner EMAC
In-Reply-To: <CAGVrzcbyXiKCKxtOAj0gnG8eCQag8_xvmd9dUKACCbfW-2HN9Q@mail.gmail.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369387394-9453-3-git-send-email-maxime.ripard@free-electrons.com>
 <CAGVrzcbyXiKCKxtOAj0gnG8eCQag8_xvmd9dUKACCbfW-2HN9Q@mail.gmail.com>
Message-ID: <20130524101419.GC8785@lukather>

Hi Florian,

On Fri, May 24, 2013 at 10:42:30AM +0100, Florian Fainelli wrote:
> Hello Maxime,
> 
> 2013/5/24 Maxime Ripard <maxime.ripard at free-electrons.com>
> >
> > This patch adds a separate driver for the MDIO interface of the
> > Allwinner ethernet controllers.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> > ---
> >  .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +++
> >  drivers/net/ethernet/allwinner/Kconfig             |   8 +
> >  drivers/net/ethernet/allwinner/Makefile            |   1 +
> >  drivers/net/ethernet/allwinner/sun4i-mdio.c        | 191 +++++++++++++++++++++
> 
> Ok, so you probably followed Thomas's example here with mvneta/mvmdio,
> but all other MDIO bus drivers live in drivers/net/phy.

Indeed I shamelessly followed Thomas here.

> Unfortunately, mvmdio lives in drivers/net/ethernet/marvell/mvmdio.c
> which I should have noticed before. Whatever is good for you guys, but
> we should probably start normalizing this now before more mdio drivers
> get merged alongside their corresponding ethernet MAC users.

I'm fine with either way, just tell me where to put it and I'll happily
do so.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From b32955 at freescale.com  Fri May 24 05:59:18 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:18 +0800
Subject: [PATCH v3 0/6] ARM: imx6q{dl}: add the WEIM driver
Message-ID: <1369389564-13181-1-git-send-email-b32955@freescale.com>

This patch set adds a new driver for WEIM in the imx6q{dl}-sabreauto boards.

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, only the NOR is connected to WEIM.

v2 --> v3:
	[0] split the NOR pinctrl.
	[1] make the driver unloaded. change to bool type in Kconfig.
	[2] use the of_platform_populate().
	[3] remove the unused "interrupt" property from the Doc.
v1 --> v2:
	[0] remove used PADs.
	[1] fix the wrong pad values, (thanks Alison Chaiken)
	[2] remove the weim-cs-index.
	[3] add "fsl" for the weim-cs-timing.
	[4] remove the partitions info in the document.
	[5] rewrite the drivers(follow Sascha and Shawn's comments)


Huang Shijie (6):
  drivers: bus: add a new driver for WEIM
  ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
  ARM: dts: imx6qdl: add more information for WEIM
  ARM: dts: imx6q: add pinctrls for WEIM NOR
  ARM: dts: imx6dl: add pinctrls for WEIM NOR
  ARM: dts: imx6qdl: enable the WEIM NOR

 Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
 arch/arm/boot/dts/imx6dl-sabreauto.dts             |    9 +-
 arch/arm/boot/dts/imx6dl.dtsi                      |   60 +++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts              |    9 +-
 arch/arm/boot/dts/imx6q.dtsi                       |   61 +++++++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |   22 +++-
 arch/arm/boot/dts/imx6qdl.dtsi                     |    4 +-
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  139 ++++++++++++++++++++
 10 files changed, 360 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c




From b32955 at freescale.com  Fri May 24 05:59:20 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:20 +0800
Subject: [PATCH v3 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between SPI
 and WEIM
In-Reply-To: <1369389564-13181-1-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
Message-ID: <1369389564-13181-3-git-send-email-b32955@freescale.com>

In the imx6q-sabreauto and imx6dl-sabreauto boards,
the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
it is used as a data pin for the WEIM NOR.

In order to fix the conflict, this patch removes the pin from the hog,
and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto.

The SPI NOR selects this pinctrl_ecspi1_sabreauto when it is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl-sabreauto.dts   |    9 ++++++++-
 arch/arm/boot/dts/imx6q-sabreauto.dts    |    9 ++++++++-
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    2 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 60f3038..95da711 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -25,7 +25,14 @@
 			fsl,pins = <
 				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+			fsl,pins = <
+				MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 9fb3e99..09a7580 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -29,7 +29,14 @@
 			fsl,pins = <
 				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+			fsl,pins = <
+				MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d6baa51..a4466e6 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -20,7 +20,7 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio3 19 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
 	status = "disabled"; /* pin conflict with WEIM NOR */
 
 	flash: m25p80 at 0 {
-- 
1.7.1




From b32955 at freescale.com  Fri May 24 05:59:19 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:19 +0800
Subject: [PATCH v3 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369389564-13181-1-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
Message-ID: <1369389564-13181-2-git-send-email-b32955@freescale.com>

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.

This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  139 ++++++++++++++++++++
 4 files changed, 199 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c

diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644
index 0000000..e7a2950
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -0,0 +1,50 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+
+The term "wireless" does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+
+The actual devices are instantiated from the child nodes of a WEIM node.
+
+Required properties:
+
+ - compatible:		Should be set to "fsl,imx6q-weim"
+ - reg:			A resource specifier for the register space
+			(see the example below)
+ - clocks:		the clock, see the example below.
+ - #address-cells:	Must be set to 2 to allow memory address translation
+ - #size-cells:		Must be set to 1 to allow CS address passing
+ - ranges:		Must be set up to reflect the memory layout with four
+			integer values for each chip-select line in use:
+
+			   <cs-number> 0 <physical address of mapping> <size>
+
+Timing property for child nodes. It is mandatory, not optional.
+
+ - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
+			child node. We can get the CS index from the child
+			node's "reg" property. This property contains the values
+			for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
+			EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+
+Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
+
+	weim: weim at 021b8000 {
+		compatible = "fsl,imx6q-weim";
+		reg = <0x021b8000 0x4000>;
+		clocks = <&clks 196>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0x08000000 0x08000000>;
+
+		nor at 0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x02000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+
+			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
+					0x0000C000 0x1404a38e 0x00000000>;
+		};
+	};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab..46cd5bb 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,15 @@
 
 menu "Bus devices"
 
+config IMX_WEIM
+	bool "Freescale EIM DRIVER"
+	depends on ARCH_MXC
+	help
+	  Driver for i.MX6 WEIM controller.
+	  The WEIM(Wireless External Interface Module) works like a bus.
+	  You can attach many different devices on it, such as NOR, onenand.
+	  But now, we only support the Parallel NOR.
+
 config MVEBU_MBUS
 	bool
 	depends on PLAT_ORION
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c..436bbcc 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
new file mode 100644
index 0000000..aef865d
--- /dev/null
+++ b/drivers/bus/imx-weim.c
@@ -0,0 +1,139 @@
+/*
+ * EIM driver for Freescale's i.MX chips
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+
+struct imx_weim {
+	void __iomem *base;
+	struct clk *clk;
+};
+
+static const struct of_device_id weim_id_table[] = {
+	{ .compatible = "fsl,imx6q-weim", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, weim_id_table);
+
+#define CS_TIMING_LEN 6
+#define CS_REG_RANGE  0x18
+
+/* Parse and set the timing for this device. */
+static int
+weim_timing_setup(struct platform_device *pdev, struct device_node *np)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+	u32 value[CS_TIMING_LEN];
+	u32 cs_idx;
+	int ret;
+	int i;
+
+	/* get the CS index from this child node's "reg" property. */
+	ret = of_property_read_u32(np, "reg", &cs_idx);
+	if (ret)
+		return ret;
+
+	/* The weim has four chip selects. */
+	if (cs_idx > 3)
+		return -EINVAL;
+
+	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
+					value, CS_TIMING_LEN);
+	if (ret)
+		return ret;
+
+	/* set the timing for WEIM */
+	for (i = 0; i < CS_TIMING_LEN; i++)
+		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
+	return 0;
+}
+
+static void weim_parse_dt(struct platform_device *pdev)
+{
+	struct device_node *child;
+
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		if (!child->name)
+			continue;
+
+		if (weim_timing_setup(pdev, child)) {
+			dev_err(&pdev->dev, "%s set timing failed.\n",
+				child->full_name);
+			continue;
+		}
+	}
+
+	if (of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev) < 0)
+		dev_err(&pdev->dev, "%s fail to create devices.\n",
+			pdev->dev.of_node->full_name);
+}
+
+static int weim_probe(struct platform_device *pdev)
+{
+	struct imx_weim *weim;
+	struct resource *res;
+	int ret = -EINVAL;
+
+	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
+	if (!weim) {
+		ret = -ENOMEM;
+		goto weim_err;
+	}
+	platform_set_drvdata(pdev, weim);
+
+	/* get the resource */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	weim->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(weim->base)) {
+		ret = PTR_ERR(weim->base);
+		goto weim_err;
+	}
+
+	/* get the clock */
+	weim->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(weim->clk))
+		goto weim_err;
+
+	ret = clk_prepare_enable(weim->clk);
+	if (ret)
+		goto weim_err;
+
+	/* parse the device node */
+	weim_parse_dt(pdev);
+
+	dev_info(&pdev->dev, "WEIM driver registered.\n");
+	return 0;
+
+weim_err:
+	return ret;
+}
+
+static int weim_remove(struct platform_device *pdev)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(weim->clk);
+	return 0;
+}
+
+static struct platform_driver weim_driver = {
+	.driver = {
+		.name = "imx-weim",
+		.of_match_table = weim_id_table,
+	},
+	.probe   = weim_probe,
+	.remove  = weim_remove,
+};
+
+module_platform_driver(weim_driver);
+MODULE_AUTHOR("Freescale Semiconductor Inc.");
+MODULE_DESCRIPTION("i.MX EIM Controller Driver");
+MODULE_LICENSE("GPL");
-- 
1.7.1




From b32955 at freescale.com  Fri May 24 05:59:21 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:21 +0800
Subject: [PATCH v3 3/6] ARM: dts: imx6qdl: add more information for WEIM
In-Reply-To: <1369389564-13181-1-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
Message-ID: <1369389564-13181-4-git-send-email-b32955@freescale.com>

Add the clock and compatible information for the weim.
Also adds the weim label.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461c..f21d259 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -744,9 +744,11 @@
 				reg = <0x021b4000 0x4000>;
 			};
 
-			weim at 021b8000 {
+			weim: weim at 021b8000 {
+				compatible = "fsl,imx6q-weim";
 				reg = <0x021b8000 0x4000>;
 				interrupts = <0 14 0x04>;
+				clocks = <&clks 196>;
 			};
 
 			ocotp at 021bc000 {
-- 
1.7.1




From b32955 at freescale.com  Fri May 24 05:59:23 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:23 +0800
Subject: [PATCH v3 5/6] ARM: dts: imx6dl: add pinctrls for WEIM NOR
In-Reply-To: <1369389564-13181-1-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
Message-ID: <1369389564-13181-6-git-send-email-b32955@freescale.com>

Add two pinctrls for WEIM:
   one for the weim nor, another for the chipselect.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   60 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 4b13454..ddc8d61 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -183,6 +183,66 @@
 					};
 				};
 
+				weim {
+					pinctrl_weim_cs_0: weim_norgrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+							>;
+					};
+
+					pinctrl_weim_nor_1: weim_norgrp-2 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+
+							/* data */
+							MX6DL_PAD_EIM_D16__EIM_DATA16 0xb0b1
+							MX6DL_PAD_EIM_D17__EIM_DATA17 0xb0b1
+							MX6DL_PAD_EIM_D18__EIM_DATA18 0xb0b1
+							MX6DL_PAD_EIM_D19__EIM_DATA19 0xb0b1
+							MX6DL_PAD_EIM_D20__EIM_DATA20 0xb0b1
+							MX6DL_PAD_EIM_D21__EIM_DATA21 0xb0b1
+							MX6DL_PAD_EIM_D22__EIM_DATA22 0xb0b1
+							MX6DL_PAD_EIM_D23__EIM_DATA23 0xb0b1
+							MX6DL_PAD_EIM_D24__EIM_DATA24 0xb0b1
+							MX6DL_PAD_EIM_D25__EIM_DATA25 0xb0b1
+							MX6DL_PAD_EIM_D26__EIM_DATA26 0xb0b1
+							MX6DL_PAD_EIM_D27__EIM_DATA27 0xb0b1
+							MX6DL_PAD_EIM_D28__EIM_DATA28 0xb0b1
+							MX6DL_PAD_EIM_D29__EIM_DATA29 0xb0b1
+							MX6DL_PAD_EIM_D30__EIM_DATA30 0xb0b1
+							MX6DL_PAD_EIM_D31__EIM_DATA31 0xb0b1
+
+							/* address */
+							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 
 			};
 
-- 
1.7.1




From b32955 at freescale.com  Fri May 24 05:59:24 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:24 +0800
Subject: [PATCH v3 6/6] ARM: dts: imx6qdl: enable the WEIM NOR
In-Reply-To: <1369389564-13181-1-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
Message-ID: <1369389564-13181-7-git-send-email-b32955@freescale.com>

Enable the WEIM NOR for imx6q{dl} boards.

For the pin conflict with SPI NOR, its status is set to "disabled".

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index a4466e6..bb0f185 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -58,3 +58,23 @@
 	wp-gpios = <&gpio1 13 0>;
 	status = "okay";
 };
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs_0>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	status = "disabled"; /* pin conflict with SPI NOR */
+
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+
+		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
+				0x0000C000 0x1404a38e 0x00000000>;
+	};
+};
-- 
1.7.1




From b32955 at freescale.com  Fri May 24 05:59:22 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 24 May 2013 17:59:22 +0800
Subject: [PATCH v3 4/6] ARM: dts: imx6q: add pinctrls for WEIM NOR
In-Reply-To: <1369389564-13181-1-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
Message-ID: <1369389564-13181-5-git-send-email-b32955@freescale.com>

Add two pinctrls for WEIM:
   one for the weim nor, another for the chipselect.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   61 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..7c5bcf4 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -323,6 +323,67 @@
 						>;
 					};
 				};
+
+				weim {
+					pinctrl_weim_cs_0: weim_norgrp-1 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+							>;
+					};
+
+					pinctrl_weim_nor_1: weim_norgrp-2 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+
+							/* data */
+							MX6Q_PAD_EIM_D16__EIM_DATA16 0xb0b1
+							MX6Q_PAD_EIM_D17__EIM_DATA17 0xb0b1
+							MX6Q_PAD_EIM_D18__EIM_DATA18 0xb0b1
+							MX6Q_PAD_EIM_D19__EIM_DATA19 0xb0b1
+							MX6Q_PAD_EIM_D20__EIM_DATA20 0xb0b1
+							MX6Q_PAD_EIM_D21__EIM_DATA21 0xb0b1
+							MX6Q_PAD_EIM_D22__EIM_DATA22 0xb0b1
+							MX6Q_PAD_EIM_D23__EIM_DATA23 0xb0b1
+							MX6Q_PAD_EIM_D24__EIM_DATA24 0xb0b1
+							MX6Q_PAD_EIM_D25__EIM_DATA25 0xb0b1
+							MX6Q_PAD_EIM_D26__EIM_DATA26 0xb0b1
+							MX6Q_PAD_EIM_D27__EIM_DATA27 0xb0b1
+							MX6Q_PAD_EIM_D28__EIM_DATA28 0xb0b1
+							MX6Q_PAD_EIM_D29__EIM_DATA29 0xb0b1
+							MX6Q_PAD_EIM_D30__EIM_DATA30 0xb0b1
+							MX6Q_PAD_EIM_D31__EIM_DATA31 0xb0b1
+
+							/* address */
+							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 			};
 		};
 
-- 
1.7.1




From itooo at itooo.com  Fri May 24 06:25:48 2013
From: itooo at itooo.com (Greg)
Date: Fri, 24 May 2013 12:25:48 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130523234024.GU18614@n2100.arm.linux.org.uk>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130523142301.10dbeff9@skate>
 <20130523202643.GQ18614@n2100.arm.linux.org.uk>
 <201305232240.03959.arnd@arndb.de>
 <20130523230911.GR18614@n2100.arm.linux.org.uk>
 <20130524011724.515eac91@skate>
 <20130523234024.GU18614@n2100.arm.linux.org.uk>
Message-ID: <519F402C.9050801@itooo.com>

Le 24/05/2013 01:40, Russell King - ARM Linux a ?crit :
> On Fri, May 24, 2013 at 01:17:24AM +0200, Thomas Petazzoni wrote:
>> Russell,
>>
>> On Fri, 24 May 2013 00:09:11 +0100, Russell King - ARM Linux wrote:
>>
>>> No, I'm not asking about the principle.  I'm asking _in this particular
>>> problem case_ who provides the DT blob?
>>>
>>> So the person to answer that question is Thomas or someone who is using
>>> the boards concerned.
>> The DTB is built from arch/arm/boot/dts/, together with the kernel
>> image itself. As far as I'm aware of, there is for the moment no plan
>> to "burn" the DTB on the board and therefore make the Device Tree
>> really separated from the kernel.
> Right, so we're still in the position where we aren't dealing with
> vendor provided DT blobs... this also means of course that the DT blob
> isn't going to get updated by the boot loader depending on where it
> decides to set the registers.
>
> I suspect as far as the boot loaders on these boards go, the DT blob is
> "just another file" to be loaded into memory by the boot loader, and it
> is completely untouched by the boot loader.
>
Russell,

this is a little more complicated, the bootloader does touch the DT 
blob, for example it sets the MAC addresses of the network interfaces, I 
believe it also sets UART0 parameters. It does this silently if it 
founds entries it knows about in the DT blob.

I guess the good idea would have been to ask Marvell to also update an 
MBUS entry in the DT blob instead of doing the CP15 trick. This would 
not have solved the earlyprintk problem however.
I also guess this is not feasible anymore since it would imply to have 3 
different bootloader possibilities and 2 already is a pain to deal with.

Does this raise any new idea to someone ?

Cheers,

PS: I also got Marvell's confirmation, there is no way to avoid CPU hang 
when accessing an unmapped memory address, this triggers an external 
abort exception which is not recoverable in kernel mode.


From jbe at pengutronix.de  Fri May 24 06:28:33 2013
From: jbe at pengutronix.de (Juergen Beisert)
Date: Fri, 24 May 2013 12:28:33 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <519E3C40.4020405@digi.com>
References: <519E03B0.1080006@digi.com>
 <201305231531.31376.jbe@pengutronix.de> <519E3C40.4020405@digi.com>
Message-ID: <201305241228.34168.jbe@pengutronix.de>

Hector Palacios wrote:
> Hi Juergen,
>
> On 05/23/2013 03:31 PM, Juergen Beisert wrote:
> > Hi Maxime,
> >
> > maxime.ripard at free-electrons.com wrote:
> >> On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> >>> I'm using an i.MX28 based board with lcd connected with 18bits data
> >>> bus. My platform uses 32 bits per pixel:
> >>>
> >>> 	mxsfb_pdata.default_bpp = 32;
> >>> 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
> >>>
> >>> With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
> >>> at HW_LCDIF_CTRL register in function mxsfb_set_par():
> >>>
> >>> 	case 32:
> >>> 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
> >>> 		ctrl |= CTRL_SET_WORD_LENGTH(3);
> >>> 		switch (host->ld_intf_width) {
> >>> 		case STMLCDIF_8BIT:
> >>> 			dev_dbg(&host->pdev->dev,
> >>> 					"Unsupported LCD bus width mapping\n");
> >>> 			return -EINVAL;
> >>> 		case STMLCDIF_16BIT:
> >>> 		case STMLCDIF_18BIT:
> >>> 			/* 24 bit to 18 bit mapping */
> >>> 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> >>> 					    *  each colour component
> >>> 					    */
> >>> 			break;
> >>> 		case STMLCDIF_24BIT:
> >>> 			/* real 24 bit */
> >>> 			break;
> >>> 		}
> >>>
> >>> According to the manual, this flag does:
> >>> 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
> >>> format, such that all RGB 888 data is contained in 24 bits.
> >>> 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
> >>> actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
> >>> 2 bits in each byte do not contain any useful data, and should be
> >>> dropped.
> >>>
> >>> The setting of this flag is producing bad colours with true colour
> >>> images (i.e. the Linux penguin is displayed ok, but QT applications
> >>> or images displayed with fbv are not).
> >>> I believe the setting of this flag is not correct (after all, if my
> >>> bpp is 32, then all 24bit colours are useful and dropping the upper
> >>> 2 bits is a bad idea).
> >>> If I don't set it, then true colour images are displayed correctly.
> >>> The only problem is that the Linux penguin is displayed much darker
> >>> than usual (correct colours, but darker). Perhaps the 224 colour
> >>> format of this image justifies it?
> >>>
> >>> I noticed the cfa10049 platform also uses the same configuration (18
> >>> bits data bus and 32bpp) and was wondering if true colour images are
> >>> correctly displayed in this platform with this flag set (for example
> >>> with fbv application [1]).
> >>
> >> I had the exact same problem, and suggested the exact same solution a
> >> few weeks back.
> >>
> >> https://patchwork.kernel.org/patch/2470441/
> >>
> >> The conclusion of that discussion what that the userspace applications
> >> were not honouring the bitfield correctly set by the mxsfb driver, and
> >> as such, it was not a bug in the driver.
> >>
> >> While this is correct, I wonder, now that since we had that same problem
> >> in a very short amount of time, if we couldn't set this behaviour
> >> dependant of some (dt? kernel argument?) property so that one could
> >> customise it anyway he want.
> >>
> >> Maxime
> >
> > i.MX2[3|8]    LCD1       LCD2       LCD3
> >                24bit      18bit      18bit
> > --------------------------------------------
> > LCD_D0         B0         B0         --
> > LCD_D1         B1         B1         --
> > LCD_D2         B2         B2         B0
> > LCD_D3         B3         B3         B1
> > LCD_D4         B4         B4         B2
> > LCD_D5         B5         B5         B3
> > LCD_D6         B6         G0         B4
> > LCD_D7         B7         G1         B5
> >
> > LCD_D8         G0         G2         --
> > LCD_D9         G1         G3         --
> > LCD_D10        G2         G4         G0
> > LCD_D11        G3         G5         G1
> > LCD_D12        G4         R0         G2
> > LCD_D13        G5         R1         G3
> > LCD_D14        G6         R2         G4
> > LCD_D15        G7         R3         G5
> >
> > LCD_D16        R0         R4         --
> > LCD_D17        R1         R5         --
> > LCD_D18        R2                    R0
> > LCD_D19        R3                    R1
> > LCD_D20        R4                    R2
> > LCD_D21        R5                    R3
> > LCD_D22        R6                    R4
> > LCD_D23        R7                    R5
> >
> > Is your display connected like LCD2 or LCD3? LCD3 must still handled like
> > a 24 bit display shown in LCD1, while only the LCD2-case is the "24 bit
> > to 18 bit mapping" case.
> >
> > At least my current tests with an i.MX23 and a connection like LCD2 are
> > working here with a Qt application. Qt honours the pixel bitfield
> > description. And I'm using the "bits-per-pixel = <32>" and "bus-width =
> > <18>" entries in the device tree.
>
> I have a 24bit LCD display but my connection to it is done at 18bits data
> width. Represented below as LCD4.
> NOTE: In my LCD4 column, notation Rx/Gx/Bx represent the color bit in
> memory as well as the display data line.
> Since we use 32bpp each channel has 8 bits (R7..R0, etc.).
> I understand that you have an 18bit display and that your notation in LCD2
> column represents the display data lines, not the color bit indexes in
> memory.
>
> i.MX2[3|8]    LCD1       LCD2       LCD3	LCD4
>               24bit      18bit      18bit	24bit connected at 18bit
> -------------------------------------------------------
> LCD_D0         B0         B0         --		B2
> LCD_D1         B1         B1         --		B3
> LCD_D2         B2         B2         B0		B4
> LCD_D3         B3         B3         B1		B5
> LCD_D4         B4         B4         B2		B6
> LCD_D5         B5         B5         B3		B7
> LCD_D6         B6         G0         B4		G2
> LCD_D7         B7         G1         B5		G3
>
> LCD_D8         G0         G2         --		G4
> LCD_D9         G1         G3         --		G5
> LCD_D10        G2         G4         G0		G6
> LCD_D11        G3         G5         G1		G7
> LCD_D12        G4         R0         G2		R2
> LCD_D13        G5         R1         G3		R3
> LCD_D14        G6         R2         G4		R4
> LCD_D15        G7         R3         G5		R5
>
> LCD_D16        R0         R4         --		R6
> LCD_D17        R1         R5         --		R7
> LCD_D18        R2                    R0
> LCD_D19        R3                    R1
> LCD_D20        R4                    R2
> LCD_D21        R5                    R3
> LCD_D22        R6                    R4
> LCD_D23        R7                    R5
>
> For 32bpp (RGB888) and 18bit data bus I would expect the LCD controller to
> take the six *most significant* bits [7..2] from each color byte out to the
> LCD data bus (LCD_D17..D0) in the order depicted in my LCD4 column.
>
> I'm not sure what the DATA_FORMAT_24_BIT flag is doing, but dropping the
> two most significant bits of color in memory doesn't seem to be a good idea
> unless (maybe) color is in 18bpp. Previous kernels did not even touch this
> flag.
>
> Does the following patch make sense?
>
> diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
> index b1c1a80..bb0a4e1 100644
> --- a/drivers/video/mxsfb.c
> +++ b/drivers/video/mxsfb.c
> @@ -298,9 +298,6 @@ static int mxsfb_check_var(struct fb_var_screeninfo
> *var, break;
>                  case STMLCDIF_16BIT:
>                  case STMLCDIF_18BIT:
> -                       /* 24 bit to 18 bit mapping */
> -                       rgb = def_rgb666;
> -                       break;
>                  case STMLCDIF_24BIT:
>                          /* real 24 bit */
>                          rgb = def_rgb888;
> @@ -424,11 +421,6 @@ static int mxsfb_set_par(struct fb_info *fb_info)
>                          return -EINVAL;
>                  case STMLCDIF_16BIT:
>                  case STMLCDIF_18BIT:
> -                       /* 24 bit to 18 bit mapping */
> -                       ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> -                                           *  each colour component
> -                                           */
> -                       break;
>                  case STMLCDIF_24BIT:
>                          /* real 24 bit */
>                          break;
>
> The setting of def_rgb666 for a 32bpp color depth does not make sense to me
> because the color in memory is really rgb888.
>
> With this patch, my true color images are displayed ok and so does the
> penguin logo. I don't know however how other displays connections at 18bit
> will do.

Your 24 bit display is connected like a regular 18 bit display. So they should 
work in the same way with the same settings. You *must* always skip two data 
bits from the memory RGB888 to form a RGB666 value.

I just did some measurement here with my i.MX23 based hardware.

I'm using 32 bits per pixel and the 18 bit display interface (LCD_D[0..17]).

And surprise, surprise: the i.MX23 *always* maps the 24 bit input data to the 
18 bit interface. And what does the DATA_FORMAT_24_BIT aka. CTRL_DF24 do???
Just simple: it seems its meaning changes with the interface width. The 
documentation says:

  0 = all 24 bits are valid
  1 = drop upper 2 bits per byte

This text seems valid for a real 24 bit display (but I cannot test it). From 
my measurement its meaning changes when used with an 18 bit display to:

  0 = drop lower 2 bits per byte
  1 = drop upper 2 bits per byte

When this bit is 0:

      red     green    blue
   10000001|00001111|10001111 (memory layout)

   100000..|000011..|100011.. (at the display)

When this bit is 1:

      red     green    blue
   10000001|00001111|10001111 (memory layout)

   ..000001|..001111|..001111 (at the display)

Hope it does help you.

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From vikas.sajjan at linaro.org  Fri May 24 06:31:13 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 24 May 2013 16:01:13 +0530
Subject: [RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and
 PLL36XX for samsung SoCs
Message-ID: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>

This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
    for PLL35XX & PLL36XX and usues clk->base instead of clk->con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
    values for supported rates that needs to be changed for changing
    corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX

Is rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome tree.

Vikas Sajjan (2):
  clk: samsung: Add set_rate() clk_ops for PLL36XX
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk->base instead of directly using clk->con0 for
    PLL3XXX
  clk: samsung: Add support to register rate_table for PLL3XXX
  clk: samsung: Add set_rate() clk_ops for PLL35XX

 drivers/clk/samsung/clk-exynos4.c    |   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   29 +++-
 drivers/clk/samsung/clk-pll.c        |  243 ++++++++++++++++++++++++++++++----
 drivers/clk/samsung/clk-pll.h        |   27 +++-
 4 files changed, 272 insertions(+), 37 deletions(-)

-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 24 06:31:14 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 24 May 2013 16:01:14 +0530
Subject: [RESEND PATCH 1/5] clk: samsung: Use clk->base instead of directly
 using clk->con0 for PLL3xxx
In-Reply-To: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369391478-7665-2-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.

Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |   10 ++++---
 drivers/clk/samsung/clk-exynos5250.c |   14 ++++-----
 drivers/clk/samsung/clk-pll.c        |   54 ++++++++++++++++++----------------
 drivers/clk/samsung/clk-pll.h        |    4 +--
 4 files changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e6..cf7d4e7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -97,12 +97,14 @@
 #define GATE_IP_PERIL		0xc950
 #define E4210_GATE_IP_PERIR	0xc960
 #define GATE_BLOCK		0xc970
+#define E4X12_MPLL_LOCK		0x10008
 #define E4X12_MPLL_CON0		0x10108
 #define SRC_DMC			0x10200
 #define SRC_MASK_DMC		0x10300
 #define DIV_DMC0		0x10500
 #define DIV_DMC1		0x10504
 #define GATE_IP_DMC		0x10900
+#define APLL_LOCK		0x14000
 #define APLL_CON0		0x14100
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
@@ -1019,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
 					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-					reg_base + APLL_CON0);
+					reg_base + APLL_LOCK);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-					reg_base + E4X12_MPLL_CON0);
+					reg_base + E4X12_MPLL_LOCK);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + EPLL_CON0);
+					reg_base + EPLL_LOCK);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + VPLL_CON0);
+					reg_base + VPLL_LOCK);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..687b580 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ext_clk_match);
 
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-			reg_base + 0x100);
+			reg_base);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-			reg_base + 0x4100);
+			reg_base + 0x4000);
 	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
-			reg_base + 0x20110);
+			reg_base + 0x20010);
 	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
-			reg_base + 0x10150);
+			reg_base + 0x10050);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
-			reg_base + 0x10120);
+			reg_base + 0x10020);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10130);
+			reg_base + 0x10030);
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10140);
+			reg_base + 0x10040);
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..01f17cf 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -13,9 +13,24 @@
 #include "clk.h"
 #include "clk-pll.h"
 
+struct samsung_clk_pll {
+	struct clk_hw		hw;
+	const void __iomem	*base;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+#define pll_readl(pll, offset)						\
+		__raw_readl((void __iomem *)(pll->base + (offset)));
+#define pll_writel(pll, val, offset)					\
+		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
+
 /*
  * PLL35xx Clock Type
  */
+#define PLL35XX_LOCK_OFFSET             0x0
+#define PLL35XX_CON0_OFFSET             0x100
+#define PLL35XX_CON1_OFFSET             0x104
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -24,21 +39,14 @@
 #define PLL35XX_PDIV_SHIFT      (8)
 #define PLL35XX_SDIV_SHIFT      (0)
 
-struct samsung_clk_pll35xx {
-	struct clk_hw		hw;
-	const void __iomem	*con_reg;
-};
-
-#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
-
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
-	struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = pll_readl(pll, PLL35XX_CON0_OFFSET);
 	mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
 	pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
 	sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -54,9 +62,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *con_reg)
+			const char *pname, const void __iomem *base)
 {
-	struct samsung_clk_pll35xx *pll;
+	struct samsung_clk_pll *pll;
 	struct clk *clk;
 	struct clk_init_data init;
 
@@ -73,7 +81,7 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 	init.num_parents = 1;
 
 	pll->hw.init = &init;
-	pll->con_reg = con_reg;
+	pll->base = base;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
@@ -91,6 +99,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 /*
  * PLL36xx Clock Type
  */
+#define PLL36XX_LOCK_OFFSET             0x0
+#define PLL36XX_CON0_OFFSET             0x100
+#define PLL36XX_CON1_OFFSET             0x104
 
 #define PLL36XX_KDIV_MASK	(0xFFFF)
 #define PLL36XX_MDIV_MASK	(0x1FF)
@@ -100,22 +111,15 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_PDIV_SHIFT	(8)
 #define PLL36XX_SDIV_SHIFT	(0)
 
-struct samsung_clk_pll36xx {
-	struct clk_hw		hw;
-	const void __iomem	*con_reg;
-};
-
-#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
-
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
-	struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 4);
+	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -133,9 +137,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *con_reg)
+			const char *pname, const void __iomem *base)
 {
-	struct samsung_clk_pll36xx *pll;
+	struct samsung_clk_pll *pll;
 	struct clk *clk;
 	struct clk_init_data init;
 
@@ -152,7 +156,7 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 	init.num_parents = 1;
 
 	pll->hw.init = &init;
-	pll->con_reg = con_reg;
+	pll->base = base;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index f33786e..1329522 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,9 +25,9 @@ enum pll46xx_type {
 };
 
 extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *con_reg);
+			const char *pname, const void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *con_reg);
+			const char *pname, const void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll45xx_type type);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 24 06:31:15 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 24 May 2013 16:01:15 +0530
Subject: [RESEND PATCH 2/5] clk: samsung: Add support to register rate_table
 for PLL3xxx
In-Reply-To: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369391478-7665-3-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

This patch defines a common rate_table which will contain recommended p, m, s
and k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
It also sorts the rate table while registering the PLL rate table.
So that this sorted table can be used for making the searching of "required
rate" efficient.

Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
 drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
 drivers/clk/samsung/clk-pll.c        |   35 ++++++++++++++++++++++++++++++++--
 drivers/clk/samsung/clk-pll.h        |   27 ++++++++++++++++++++++++--
 4 files changed, 69 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index cf7d4e7..beff8a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
 					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-					reg_base + APLL_LOCK);
+					reg_base + APLL_LOCK, NULL, 0);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-					reg_base + E4X12_MPLL_LOCK);
+					reg_base + E4X12_MPLL_LOCK, NULL, 0);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + EPLL_LOCK);
+					reg_base + EPLL_LOCK, NULL, 0);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + VPLL_LOCK);
+					reg_base + VPLL_LOCK, NULL, 0);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ext_clk_match);
 
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-			reg_base);
+			reg_base, NULL, 0);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-			reg_base + 0x4000);
+			reg_base + 0x4000, NULL, 0);
 	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
-			reg_base + 0x20010);
+			reg_base + 0x20010, NULL, 0);
 	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
-			reg_base + 0x10050);
+			reg_base + 0x10050, NULL, 0);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
-			reg_base + 0x10020);
+			reg_base + 0x10020, NULL, 0);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10030);
+			reg_base + 0x10030, NULL, 0);
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10040);
+			reg_base + 0x10040, NULL, 0);
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 01f17cf..b8c0260 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,12 +10,15 @@
 */
 
 #include <linux/errno.h>
+#include <linux/sort.h>
 #include "clk.h"
 #include "clk-pll.h"
 
 struct samsung_clk_pll {
 	struct clk_hw		hw;
 	const void __iomem	*base;
+	struct samsung_pll_rate_table *rate_table;
+	unsigned int rate_count;
 };
 
 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -25,6 +28,14 @@ struct samsung_clk_pll {
 #define pll_writel(pll, val, offset)					\
 		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
 
+static int samsung_compare_rate(const void *_a, const void *_b)
+{
+	const struct samsung_pll_rate_table *a = _a;
+	const struct samsung_pll_rate_table *b = _b;
+
+	return a->rate - b->rate;
+}
+
 /*
  * PLL35xx Clock Type
  */
@@ -62,7 +73,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *base)
+			const char *pname, const void __iomem *base,
+			struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -82,6 +95,14 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 
 	pll->hw.init = &init;
 	pll->base = base;
+	pll->rate_table = rate_table;
+	pll->rate_count = rate_count;
+
+	if (pll->rate_table && pll->rate_count) {
+		sort(pll->rate_table, pll->rate_count,
+			sizeof(struct samsung_pll_rate_table),
+			samsung_compare_rate, NULL);
+	}
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
@@ -137,7 +158,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *base)
+			const char *pname, const void __iomem *base,
+			struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -157,6 +180,14 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 
 	pll->hw.init = &init;
 	pll->base = base;
+	pll->rate_table = rate_table;
+	pll->rate_count = rate_count;
+
+	if (pll->rate_table && pll->rate_count) {
+		sort(pll->rate_table, pll->rate_count,
+			sizeof(struct samsung_pll_rate_table),
+			samsung_compare_rate, NULL);
+	}
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 1329522..b5e12430 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -12,6 +12,25 @@
 #ifndef __SAMSUNG_CLK_PLL_H
 #define __SAMSUNG_CLK_PLL_H
 
+#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
+	{							\
+		.rate = _rate,					\
+		.pll_con0 = ((_m) << 16 | (_p) << 8 | (_s)),	\
+	}
+
+#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
+	{							\
+		.rate = _rate,					\
+		.pll_con0 = ((_m) << 16 | (_p) << 8 | (_s)),	\
+		.pll_con1 = _k,					\
+	}
+
+struct samsung_pll_rate_table {
+	unsigned  int rate;
+	u32 pll_con0;
+	u32 pll_con1;
+};
+
 enum pll45xx_type {
 	pll_4500,
 	pll_4502,
@@ -25,9 +44,13 @@ enum pll46xx_type {
 };
 
 extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *base);
+			const char *pname, const void __iomem *base,
+			struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count);
 extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *base);
+			const char *pname, const void __iomem *base,
+			struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count);
 extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll45xx_type type);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 24 06:31:16 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 24 May 2013 16:01:16 +0530
Subject: [RESEND PATCH 3/5] clk: samsung: Add set_rate() clk_ops for PLL35xx
In-Reply-To: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369391478-7665-4-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

Adds set_rate() and round_rate() clk_ops for PLL35xx

The round_rate() implemenation as of now is dummy, it returns the same rate
which is passed as input.

Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-pll.c |   95 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 94 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b8c0260..291cc9e 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -11,6 +11,7 @@
 
 #include <linux/errno.h>
 #include <linux/sort.h>
+#include <linux/bsearch.h>
 #include "clk.h"
 #include "clk-pll.h"
 
@@ -36,6 +37,21 @@ static int samsung_compare_rate(const void *_a, const void *_b)
 	return a->rate - b->rate;
 }
 
+static struct samsung_pll_rate_table *samsung_get_pll_settings(
+				struct samsung_clk_pll *pll, unsigned long rate)
+{
+	struct samsung_pll_rate_table req_rate, *tmp;
+
+	req_rate.rate = rate;
+	tmp = bsearch(&req_rate, pll->rate_table, pll->rate_count,
+			sizeof(struct samsung_pll_rate_table),
+			samsung_compare_rate);
+	if (tmp)
+		return tmp;
+
+	return NULL;
+}
+
 /*
  * PLL35xx Clock Type
  */
@@ -46,9 +62,15 @@ static int samsung_compare_rate(const void *_a, const void *_b)
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
 #define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_LOCK_STAT_MASK  (0x1)
 #define PLL35XX_MDIV_SHIFT      (16)
 #define PLL35XX_PDIV_SHIFT      (8)
 #define PLL35XX_SDIV_SHIFT      (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
+
+#define PLL35XX_MDIV(_tmp) ((_tmp) & (PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT))
+#define PLL35XX_PDIV(_tmp) ((_tmp) & (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT))
+#define PLL35XX_SDIV(_tmp) ((_tmp) & (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT))
 
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
@@ -68,8 +90,76 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
-static const struct clk_ops samsung_pll35xx_clk_ops = {
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+	if ((mdiv != PLL35XX_MDIV(pll_con)) || (pdiv != PLL35XX_PDIV(pll_con)))
+		return 1;
+	else
+		return 0;
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	struct samsung_pll_rate_table *rate;
+
+	u32 tmp, mdiv, pdiv, sdiv;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	mdiv = PLL35XX_MDIV(rate->pll_con0);
+	pdiv = PLL35XX_PDIV(rate->pll_con0);
+	sdiv = PLL35XX_SDIV(rate->pll_con0);
+
+	tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+	if (!(samsung_pll35xx_mp_change(mdiv, pdiv, tmp))) {
+		/* If only s change, change just s value only*/
+		tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
+		tmp |= sdiv;
+		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+	} else {
+		/* Set PLL lock time.
+		   Maximum lock time can be 270 * PDIV cycles */
+		pll_writel(pll, (pdiv >> PLL35XX_PDIV_SHIFT) * 270,
+				PLL35XX_LOCK_OFFSET);
+
+		/* Change PLL PMS values */
+		tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
+				(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
+				(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
+		tmp |= mdiv | pdiv | sdiv;
+		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+		/* wait_lock_time */
+		do {
+			cpu_relax();
+			tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+		} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
+				<< PLL35XX_LOCK_STAT_SHIFT)));
+	}
+
+	return 0;
+}
+
+static long samsung_pll35xx_round_rate(struct clk_hw *hw,
+			unsigned long drate, unsigned long *prate)
+{
+	/* Clock framework cries without this, so implemented dummy */
+	return drate;
+}
+
+static struct clk_ops samsung_pll35xx_clk_ops = {
 	.recalc_rate = samsung_pll35xx_recalc_rate,
+	.round_rate = samsung_pll35xx_round_rate,
+	.set_rate = samsung_pll35xx_set_rate,
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
@@ -102,6 +192,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 		sort(pll->rate_table, pll->rate_count,
 			sizeof(struct samsung_pll_rate_table),
 			samsung_compare_rate, NULL);
+	} else {
+		samsung_pll35xx_clk_ops.round_rate = NULL;
+		samsung_pll35xx_clk_ops.set_rate = NULL;
 	}
 
 	clk = clk_register(NULL, &pll->hw);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 24 06:31:17 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 24 May 2013 16:01:17 +0530
Subject: [RESEND PATCH 4/5] clk: samsung: Add set_rate() clk_ops for PLL36xx
In-Reply-To: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369391478-7665-5-git-send-email-vikas.sajjan@linaro.org>

This patch adds set_rate and round_rate clk_ops for PLL36xx
The round_rate() implementation as of now is dummy, it returns the same rate
which is passed as input.

Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
---
 drivers/clk/samsung/clk-pll.c |   67 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 291cc9e..55ff5fd 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -224,6 +224,13 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_MDIV_SHIFT	(16)
 #define PLL36XX_PDIV_SHIFT	(8)
 #define PLL36XX_SDIV_SHIFT	(0)
+#define PLL36XX_KDIV_SHIFT	(0)
+#define PLL36XX_LOCK_STAT_SHIFT (29)
+
+#define PLL36XX_MDIV(_tmp) ((_tmp) & (PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT))
+#define PLL36XX_PDIV(_tmp) ((_tmp) & (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT))
+#define PLL36XX_SDIV(_tmp) ((_tmp) & (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT))
+#define PLL36XX_KDIV(_tmp) ((_tmp) & (PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT))
 
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
@@ -246,8 +253,65 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
+static long samsung_pll36xx_round_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long *prate)
+{
+	/* retruns the same 'drate' whichs comes as input */
+	return drate;
+}
+
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 tmp, pll_con0, pll_con1, mdiv, pdiv, sdiv, kdiv;
+	struct samsung_pll_rate_table *rate;
+
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	mdiv = PLL36XX_MDIV(rate->pll_con0);
+	pdiv = PLL36XX_PDIV(rate->pll_con0);
+	sdiv = PLL36XX_SDIV(rate->pll_con0);
+	kdiv = PLL36XX_KDIV(rate->pll_con1);
+
+	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
+
+	pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
+
+	/* Set PLL lock time.
+	   Maximum lock time can be 3000 * PDIV cycles */
+	pll_writel(pll, ((pdiv >> PLL36XX_PDIV_SHIFT) * 3000),
+			PLL36XX_LOCK_OFFSET);
+
+	 /* Change PLL PMS values */
+	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
+			(PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
+			(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
+	pll_con0 |= mdiv | pdiv | sdiv;
+	pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+	pll_con1 |= kdiv;
+	pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+	/* wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
+
+	return 0;
+}
+
 static const struct clk_ops samsung_pll36xx_clk_ops = {
 	.recalc_rate = samsung_pll36xx_recalc_rate,
+	.set_rate = samsung_pll36xx_set_rate,
+	.round_rate = samsung_pll36xx_round_rate,
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -280,6 +344,9 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 		sort(pll->rate_table, pll->rate_count,
 			sizeof(struct samsung_pll_rate_table),
 			samsung_compare_rate, NULL);
+	} else {
+		samsung_pll35xx_clk_ops.round_rate = NULL;
+		samsung_pll35xx_clk_ops.set_rate = NULL;
 	}
 
 	clk = clk_register(NULL, &pll->hw);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 24 06:31:18 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 24 May 2013 16:01:18 +0530
Subject: [RESEND PATCH 5/5] clk: samsung: Add EPLL and VPLL freq table for
 exynos5250 SoC
In-Reply-To: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369391478-7665-6-git-send-email-vikas.sajjan@linaro.org>

Adds the EPLL and VPLL freq table for exynos5250 SoC.

Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |   19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ddf10ca..00d1fa6 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -469,6 +469,21 @@ static __initdata struct of_device_id ext_clk_match[] = {
 	{ },
 };
 
+static struct samsung_pll_rate_table vpll_tbl[] = {
+	PLL_36XX_RATE(70500000, 2, 94, 4, 0),
+};
+
+static struct samsung_pll_rate_table epll_tbl[] = {
+	PLL_36XX_RATE(192000000, 48, 3, 1, 0),
+	PLL_36XX_RATE(180000000, 45, 3, 1, 0),
+	PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+	PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+	PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+	PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+	PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+	PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
 /* register exynox5250 clocks */
 void __init exynos5250_clk_init(struct device_node *np)
 {
@@ -501,9 +516,9 @@ void __init exynos5250_clk_init(struct device_node *np)
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
 			reg_base + 0x10020, NULL, 0);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10030, NULL, 0);
+			reg_base + 0x10030, epll_tbl, ARRAY_SIZE(epll_tbl));
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10040, NULL, 0);
+			reg_base + 0x10040, vpll_tbl, ARRAY_SIZE(vpll_tbl));
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
-- 
1.7.9.5



From hector.palacios at digi.com  Fri May 24 06:43:01 2013
From: hector.palacios at digi.com (Hector Palacios)
Date: Fri, 24 May 2013 12:43:01 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <201305241228.34168.jbe@pengutronix.de>
References: <519E03B0.1080006@digi.com>
 <201305231531.31376.jbe@pengutronix.de> <519E3C40.4020405@digi.com>
 <201305241228.34168.jbe@pengutronix.de>
Message-ID: <519F4435.5010703@digi.com>

Hi Juergen,

On 05/24/2013 12:28 PM, Juergen Beisert wrote:
> Hector Palacios wrote:
>> Hi Juergen,
>>
>> On 05/23/2013 03:31 PM, Juergen Beisert wrote:
>>> Hi Maxime,
>>>
>>> maxime.ripard at free-electrons.com wrote:
>>>> On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
>>>>> I'm using an i.MX28 based board with lcd connected with 18bits data
>>>>> bus. My platform uses 32 bits per pixel:
>>>>>
>>>>> 	mxsfb_pdata.default_bpp = 32;
>>>>> 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
>>>>>
>>>>> With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
>>>>> at HW_LCDIF_CTRL register in function mxsfb_set_par():
>>>>>
>>>>> 	case 32:
>>>>> 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
>>>>> 		ctrl |= CTRL_SET_WORD_LENGTH(3);
>>>>> 		switch (host->ld_intf_width) {
>>>>> 		case STMLCDIF_8BIT:
>>>>> 			dev_dbg(&host->pdev->dev,
>>>>> 					"Unsupported LCD bus width mapping\n");
>>>>> 			return -EINVAL;
>>>>> 		case STMLCDIF_16BIT:
>>>>> 		case STMLCDIF_18BIT:
>>>>> 			/* 24 bit to 18 bit mapping */
>>>>> 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
>>>>> 					    *  each colour component
>>>>> 					    */
>>>>> 			break;
>>>>> 		case STMLCDIF_24BIT:
>>>>> 			/* real 24 bit */
>>>>> 			break;
>>>>> 		}
>>>>>
>>>>> According to the manual, this flag does:
>>>>> 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
>>>>> format, such that all RGB 888 data is contained in 24 bits.
>>>>> 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
>>>>> actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
>>>>> 2 bits in each byte do not contain any useful data, and should be
>>>>> dropped.
>>>>>
>>>>> The setting of this flag is producing bad colours with true colour
>>>>> images (i.e. the Linux penguin is displayed ok, but QT applications
>>>>> or images displayed with fbv are not).
>>>>> I believe the setting of this flag is not correct (after all, if my
>>>>> bpp is 32, then all 24bit colours are useful and dropping the upper
>>>>> 2 bits is a bad idea).
>>>>> If I don't set it, then true colour images are displayed correctly.
>>>>> The only problem is that the Linux penguin is displayed much darker
>>>>> than usual (correct colours, but darker). Perhaps the 224 colour
>>>>> format of this image justifies it?
>>>>>
>>>>> I noticed the cfa10049 platform also uses the same configuration (18
>>>>> bits data bus and 32bpp) and was wondering if true colour images are
>>>>> correctly displayed in this platform with this flag set (for example
>>>>> with fbv application [1]).
>>>>
>>>> I had the exact same problem, and suggested the exact same solution a
>>>> few weeks back.
>>>>
>>>> https://patchwork.kernel.org/patch/2470441/
>>>>
>>>> The conclusion of that discussion what that the userspace applications
>>>> were not honouring the bitfield correctly set by the mxsfb driver, and
>>>> as such, it was not a bug in the driver.
>>>>
>>>> While this is correct, I wonder, now that since we had that same problem
>>>> in a very short amount of time, if we couldn't set this behaviour
>>>> dependant of some (dt? kernel argument?) property so that one could
>>>> customise it anyway he want.
>>>>
>>>> Maxime
>>>
>>> i.MX2[3|8]    LCD1       LCD2       LCD3
>>>                 24bit      18bit      18bit
>>> --------------------------------------------
>>> LCD_D0         B0         B0         --
>>> LCD_D1         B1         B1         --
>>> LCD_D2         B2         B2         B0
>>> LCD_D3         B3         B3         B1
>>> LCD_D4         B4         B4         B2
>>> LCD_D5         B5         B5         B3
>>> LCD_D6         B6         G0         B4
>>> LCD_D7         B7         G1         B5
>>>
>>> LCD_D8         G0         G2         --
>>> LCD_D9         G1         G3         --
>>> LCD_D10        G2         G4         G0
>>> LCD_D11        G3         G5         G1
>>> LCD_D12        G4         R0         G2
>>> LCD_D13        G5         R1         G3
>>> LCD_D14        G6         R2         G4
>>> LCD_D15        G7         R3         G5
>>>
>>> LCD_D16        R0         R4         --
>>> LCD_D17        R1         R5         --
>>> LCD_D18        R2                    R0
>>> LCD_D19        R3                    R1
>>> LCD_D20        R4                    R2
>>> LCD_D21        R5                    R3
>>> LCD_D22        R6                    R4
>>> LCD_D23        R7                    R5
>>>
>>> Is your display connected like LCD2 or LCD3? LCD3 must still handled like
>>> a 24 bit display shown in LCD1, while only the LCD2-case is the "24 bit
>>> to 18 bit mapping" case.
>>>
>>> At least my current tests with an i.MX23 and a connection like LCD2 are
>>> working here with a Qt application. Qt honours the pixel bitfield
>>> description. And I'm using the "bits-per-pixel = <32>" and "bus-width =
>>> <18>" entries in the device tree.
>>
>> I have a 24bit LCD display but my connection to it is done at 18bits data
>> width. Represented below as LCD4.
>> NOTE: In my LCD4 column, notation Rx/Gx/Bx represent the color bit in
>> memory as well as the display data line.
>> Since we use 32bpp each channel has 8 bits (R7..R0, etc.).
>> I understand that you have an 18bit display and that your notation in LCD2
>> column represents the display data lines, not the color bit indexes in
>> memory.
>>
>> i.MX2[3|8]    LCD1       LCD2       LCD3	LCD4
>>                24bit      18bit      18bit	24bit connected at 18bit
>> -------------------------------------------------------
>> LCD_D0         B0         B0         --		B2
>> LCD_D1         B1         B1         --		B3
>> LCD_D2         B2         B2         B0		B4
>> LCD_D3         B3         B3         B1		B5
>> LCD_D4         B4         B4         B2		B6
>> LCD_D5         B5         B5         B3		B7
>> LCD_D6         B6         G0         B4		G2
>> LCD_D7         B7         G1         B5		G3
>>
>> LCD_D8         G0         G2         --		G4
>> LCD_D9         G1         G3         --		G5
>> LCD_D10        G2         G4         G0		G6
>> LCD_D11        G3         G5         G1		G7
>> LCD_D12        G4         R0         G2		R2
>> LCD_D13        G5         R1         G3		R3
>> LCD_D14        G6         R2         G4		R4
>> LCD_D15        G7         R3         G5		R5
>>
>> LCD_D16        R0         R4         --		R6
>> LCD_D17        R1         R5         --		R7
>> LCD_D18        R2                    R0
>> LCD_D19        R3                    R1
>> LCD_D20        R4                    R2
>> LCD_D21        R5                    R3
>> LCD_D22        R6                    R4
>> LCD_D23        R7                    R5
>>
>> For 32bpp (RGB888) and 18bit data bus I would expect the LCD controller to
>> take the six *most significant* bits [7..2] from each color byte out to the
>> LCD data bus (LCD_D17..D0) in the order depicted in my LCD4 column.
>>
>> I'm not sure what the DATA_FORMAT_24_BIT flag is doing, but dropping the
>> two most significant bits of color in memory doesn't seem to be a good idea
>> unless (maybe) color is in 18bpp. Previous kernels did not even touch this
>> flag.
>>
>> Does the following patch make sense?
>>
>> diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
>> index b1c1a80..bb0a4e1 100644
>> --- a/drivers/video/mxsfb.c
>> +++ b/drivers/video/mxsfb.c
>> @@ -298,9 +298,6 @@ static int mxsfb_check_var(struct fb_var_screeninfo
>> *var, break;
>>                   case STMLCDIF_16BIT:
>>                   case STMLCDIF_18BIT:
>> -                       /* 24 bit to 18 bit mapping */
>> -                       rgb = def_rgb666;
>> -                       break;
>>                   case STMLCDIF_24BIT:
>>                           /* real 24 bit */
>>                           rgb = def_rgb888;
>> @@ -424,11 +421,6 @@ static int mxsfb_set_par(struct fb_info *fb_info)
>>                           return -EINVAL;
>>                   case STMLCDIF_16BIT:
>>                   case STMLCDIF_18BIT:
>> -                       /* 24 bit to 18 bit mapping */
>> -                       ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
>> -                                           *  each colour component
>> -                                           */
>> -                       break;
>>                   case STMLCDIF_24BIT:
>>                           /* real 24 bit */
>>                           break;
>>
>> The setting of def_rgb666 for a 32bpp color depth does not make sense to me
>> because the color in memory is really rgb888.
>>
>> With this patch, my true color images are displayed ok and so does the
>> penguin logo. I don't know however how other displays connections at 18bit
>> will do.
>
> Your 24 bit display is connected like a regular 18 bit display. So they should
> work in the same way with the same settings. You *must* always skip two data
> bits from the memory RGB888 to form a RGB666 value.
>
> I just did some measurement here with my i.MX23 based hardware.
>
> I'm using 32 bits per pixel and the 18 bit display interface (LCD_D[0..17]).
>
> And surprise, surprise: the i.MX23 *always* maps the 24 bit input data to the
> 18 bit interface. And what does the DATA_FORMAT_24_BIT aka. CTRL_DF24 do???
> Just simple: it seems its meaning changes with the interface width. The
> documentation says:
>
>    0 = all 24 bits are valid
>    1 = drop upper 2 bits per byte
>
> This text seems valid for a real 24 bit display (but I cannot test it). From
> my measurement its meaning changes when used with an 18 bit display to:
>
>    0 = drop lower 2 bits per byte
>    1 = drop upper 2 bits per byte
>
> When this bit is 0:
>
>        red     green    blue
>     10000001|00001111|10001111 (memory layout)
>
>     100000..|000011..|100011.. (at the display)
>
> When this bit is 1:
>
>        red     green    blue
>     10000001|00001111|10001111 (memory layout)
>
>     ..000001|..001111|..001111 (at the display)

And how can the setting of this flag be useful?
In the example above, you had a red component of 0x81 (half way through the scale), 
which is converted to a 0x01 (almost black) at the display. Isn't this wrong?

This only looks right to me if you set a 18bpp but even in that case masking the upper 
bits isn't really needed at all.

Regards,
-- 
H?ctor Palacios


From arnd at arndb.de  Fri May 24 06:57:34 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 12:57:34 +0200
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
In-Reply-To: <20130524100754.6b2d1bc9@skate>
References: <1369132414-18959-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130524074616.GV18614@n2100.arm.linux.org.uk>
 <20130524100754.6b2d1bc9@skate>
Message-ID: <201305241257.34468.arnd@arndb.de>

On Friday 24 May 2013, Thomas Petazzoni wrote:
> On Fri, 24 May 2013 08:46:16 +0100, Russell King - ARM Linux wrote:
> 
> > Wrong, again.  Thomas has already said there are boot loaders shipping
> > on boards which have the registers programmed to be at 0xf1xxxxxx and
> > there's boards with boot loaders programmed for 0xd0xxxxxx.
> > 
> > The problem is here TODAY.

The problem so far only concerns the development boards if I understood
Thomas correctly, not the Mirabox/OpenBlocks systems that this thread was
about, if you read up how we got here.
 
> Right. And again, don't expect something like:
> 
>  * Board A = 0xd0xxxxxx
>  * Board B = 0xf1xxxxxx
> 
> Depending on which bootloader, and which version of the bootloader you
> run, on a given board, the kernel may be booted with 0xd0 or 0xf1.

This is fine, the only thing we have to ensure is that the device tree
correctly describes what the boot loader has set up:

* For development boards and any future products you said we can ignore
  the old boot loaders and happily put the new address in the device
  tree. This seems reasonable.
* For Mirabox/OpenBlocks, it's too late to change it now, as you say,
  so they should stay at 0xd0.
* If someone wants to update their OpenBlocks to a new boot loader that
  uses the 0xf1 address, that's also fine, as long as they ensure they
  have a matching device tree. This is possible because there are no
  boot loaders for those devices yet using the new address. If the
  device tree gets loaded by u-boot, it can update the address in both
  DT and in hardware. If it uses ATAGS, it has to assume it is booting
  an older kernel so it cannot reprogram the hardware.
* If they screw up and change the address without updating the DT in
  memory, the only reasonable option left is to have a different DT
  blob for the new u-boot version. Hopefully we can avoid that case.

> And again, again. This 0xd0 was a mistake. We don't want to support
> moving forward. The only thing we want to support is 0xf1, nothing else.
>
> All the proposal is about a temporary workaround, just to make the
> transition smoother.

The 0xd0 wasn't the only mistake, it was just one in a series of
mistakes, each trying to fix the previous one but making things
worse in the process. Changing the boot loader from one address to
another is a much more serious mistake and we should not encourage
that from spreading to other boards.

	Arnd


From anish198519851985 at gmail.com  Fri May 24 06:59:36 2013
From: anish198519851985 at gmail.com (anish singh)
Date: Fri, 24 May 2013 16:29:36 +0530
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <20130524094407.61d0ec42@endymion.delvare>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
Message-ID: <CAK7N6vqqG68c4vx1uBsNLF8zpSRQWwY5jERqjVYKE7NkEEzFSA@mail.gmail.com>

On Fri, May 24, 2013 at 1:14 PM, Jean Delvare <khali at linux-fr.org> wrote:
> Hi Anish, Myl?ne,
>
> On Fri, 24 May 2013 12:52:40 +0530, anish singh wrote:
>> On Fri, May 24, 2013 at 12:41 PM, Mylene Josserand
>> <Mylene.Josserand at navocap.com> wrote:
>> > I have read that this function "i2c_smbus_write_byte_data" uses
>> > "i2c_smbus_xfer" which uses "i2c_lock_adapter".
>> > In this function, there is a mutex so I thought that it will handle it
>> > but it says "Get exclusive access to an I2C bus segment". What is
>> > exactly an I2C segment ? Is it the device we are talking about ? Or is
>> > it the use of the i2c bus ?
>> Don't know what you are referring here.
>
> In the most simple case, your I2C bus has a single segment so "segment"
> or "bus" mean the same thing.
>
> It only starts mattering when I2C bus multiplexing comes into play.
> Then your bus is split into segments, with one segment (trunk) between
> the master (controller) and the multiplexer, and one or more segments
> (branches) hanging off the multiplexer.
>
> Take look at
> https://i2c.wiki.kernel.org/index.php/I2C_bus_multiplexing
> for a sample topology.
>
> But anyway the comment in front of i2c_lock_adapter() is somewhat
> misleading. If you read the code you'll see that it always locks the
> whole bus tree, because it uses the root segment's mutex.
>
>> > I will certainly have to create an i2c driver and I would like to know
>> > if this "collision" handling (if it is handled) is done in old kernel
>> > (2.6.32) or is it handled only in new kernel versions ?
>> AFAIK collision handling and detection was not supported till now
>> in linux kernel until recently but I think this patch is doing that.
>> I may be wrong but I didn't see collision handling in earlier linux
>> kernels.
>> http://thread.gmane.org/gmane.linux.kernel/1410276
>
> This is for a specific case. The general case is handled by the
> per-adapter mutex for years now. 2.6.32 should be just fine in this
> respect.
I may be mis-understanding here but when two client wants to
communicate with same master and at the same
time how does that happen?
In the thread I mentioned client pulls the line low indicating that
it wants to own the bus and waits for some time and then checks
if the line is still low or not.If it is still low then it owns the bus
and start transaction and if clients see otherwise it releases the
bus and tries again after some time.How is that handled in the
previous kernel?
>
>> > If you have any documentation on how the i2c messages are handled in
>> > case of different devices uses, it will help me a lot ! I will search in
>> > the kernel documentation but there is many files about i2c.
>> > And if you know a good i2c driver that I can use as an example to design
>> > mine, it will be great !
>
> Best is to look at a driver for a device which is similar in
> functionality to yours.
>
> --
> Jean Delvare


From catalin.marinas at arm.com  Fri May 24 06:59:58 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 11:59:58 +0100
Subject: [PATCH v2 1/4] ARM: mm: correct pte_same behaviour for LPAE.
In-Reply-To: <1369323080-9673-2-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
 <1369323080-9673-2-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524105958.GA18272@arm.com>

On Thu, May 23, 2013 at 04:31:17PM +0100, Steve Capper wrote:
> For 3 levels of paging the PTE_EXT_NG bit will be set for user
> address ptes that are written to a page table but not for ptes
> created with mk_pte.
> 
> This can cause some comparison tests made by pte_same to fail
> spuriously and lead to other problems.
> 
> To correct this behaviour, we mask off PTE_EXT_NG for any pte that
> is present before running the comparison.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> Reviewed-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Fri May 24 07:01:22 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:01:22 +0100
Subject: [PATCH v2 2/4] ARM: mm: Add support for flushing HugeTLB pages.
In-Reply-To: <1369323080-9673-3-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
 <1369323080-9673-3-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524110122.GB18272@arm.com>

On Thu, May 23, 2013 at 04:31:18PM +0100, Steve Capper wrote:
> On ARM we use the __flush_dcache_page function to flush the dcache
> of pages when needed; usually when the PG_dcache_clean bit is unset
> and we are setting a PTE.
> 
> A HugeTLB page is represented as a compound page consisting of an
> array of pages. Thus to flush the dcache of a HugeTLB page, one must
> flush more than a single page.
> 
> This patch modifies __flush_dcache_page such that all constituent
> pages of a HugeTLB page are flushed.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>
> Reviewed-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>


From jbe at pengutronix.de  Fri May 24 07:00:25 2013
From: jbe at pengutronix.de (Juergen Beisert)
Date: Fri, 24 May 2013 13:00:25 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <519F4435.5010703@digi.com>
References: <519E03B0.1080006@digi.com>
 <201305241228.34168.jbe@pengutronix.de> <519F4435.5010703@digi.com>
Message-ID: <201305241300.25461.jbe@pengutronix.de>

Hector Palacios wrote:
> Hi Juergen,
>
> On 05/24/2013 12:28 PM, Juergen Beisert wrote:
> > Hector Palacios wrote:
> >> Hi Juergen,
> >>
> >> On 05/23/2013 03:31 PM, Juergen Beisert wrote:
> >>> Hi Maxime,
> >>>
> >>> maxime.ripard at free-electrons.com wrote:
> >>>> On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> >>>>> I'm using an i.MX28 based board with lcd connected with 18bits data
> >>>>> bus. My platform uses 32 bits per pixel:
> >>>>>
> >>>>> 	mxsfb_pdata.default_bpp = 32;
> >>>>> 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
> >>>>>
> >>>>> With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
> >>>>> at HW_LCDIF_CTRL register in function mxsfb_set_par():
> >>>>>
> >>>>> 	case 32:
> >>>>> 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
> >>>>> 		ctrl |= CTRL_SET_WORD_LENGTH(3);
> >>>>> 		switch (host->ld_intf_width) {
> >>>>> 		case STMLCDIF_8BIT:
> >>>>> 			dev_dbg(&host->pdev->dev,
> >>>>> 					"Unsupported LCD bus width mapping\n");
> >>>>> 			return -EINVAL;
> >>>>> 		case STMLCDIF_16BIT:
> >>>>> 		case STMLCDIF_18BIT:
> >>>>> 			/* 24 bit to 18 bit mapping */
> >>>>> 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> >>>>> 					    *  each colour component
> >>>>> 					    */
> >>>>> 			break;
> >>>>> 		case STMLCDIF_24BIT:
> >>>>> 			/* real 24 bit */
> >>>>> 			break;
> >>>>> 		}
> >>>>>
> >>>>> According to the manual, this flag does:
> >>>>> 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
> >>>>> format, such that all RGB 888 data is contained in 24 bits.
> >>>>> 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
> >>>>> actually RGB 18 bpp, but there is 1 colour per byte, hence the upper
> >>>>> 2 bits in each byte do not contain any useful data, and should be
> >>>>> dropped.
> >>>>>
> >>>>> The setting of this flag is producing bad colours with true colour
> >>>>> images (i.e. the Linux penguin is displayed ok, but QT applications
> >>>>> or images displayed with fbv are not).
> >>>>> I believe the setting of this flag is not correct (after all, if my
> >>>>> bpp is 32, then all 24bit colours are useful and dropping the upper
> >>>>> 2 bits is a bad idea).
> >>>>> If I don't set it, then true colour images are displayed correctly.
> >>>>> The only problem is that the Linux penguin is displayed much darker
> >>>>> than usual (correct colours, but darker). Perhaps the 224 colour
> >>>>> format of this image justifies it?
> >>>>>
> >>>>> I noticed the cfa10049 platform also uses the same configuration (18
> >>>>> bits data bus and 32bpp) and was wondering if true colour images are
> >>>>> correctly displayed in this platform with this flag set (for example
> >>>>> with fbv application [1]).
> >>>>
> >>>> I had the exact same problem, and suggested the exact same solution a
> >>>> few weeks back.
> >>>>
> >>>> https://patchwork.kernel.org/patch/2470441/
> >>>>
> >>>> The conclusion of that discussion what that the userspace applications
> >>>> were not honouring the bitfield correctly set by the mxsfb driver, and
> >>>> as such, it was not a bug in the driver.
> >>>>
> >>>> While this is correct, I wonder, now that since we had that same
> >>>> problem in a very short amount of time, if we couldn't set this
> >>>> behaviour dependant of some (dt? kernel argument?) property so that
> >>>> one could customise it anyway he want.
> >>>>
> >>>> Maxime
> >>>
> >>> i.MX2[3|8]    LCD1       LCD2       LCD3
> >>>                 24bit      18bit      18bit
> >>> --------------------------------------------
> >>> LCD_D0         B0         B0         --
> >>> LCD_D1         B1         B1         --
> >>> LCD_D2         B2         B2         B0
> >>> LCD_D3         B3         B3         B1
> >>> LCD_D4         B4         B4         B2
> >>> LCD_D5         B5         B5         B3
> >>> LCD_D6         B6         G0         B4
> >>> LCD_D7         B7         G1         B5
> >>>
> >>> LCD_D8         G0         G2         --
> >>> LCD_D9         G1         G3         --
> >>> LCD_D10        G2         G4         G0
> >>> LCD_D11        G3         G5         G1
> >>> LCD_D12        G4         R0         G2
> >>> LCD_D13        G5         R1         G3
> >>> LCD_D14        G6         R2         G4
> >>> LCD_D15        G7         R3         G5
> >>>
> >>> LCD_D16        R0         R4         --
> >>> LCD_D17        R1         R5         --
> >>> LCD_D18        R2                    R0
> >>> LCD_D19        R3                    R1
> >>> LCD_D20        R4                    R2
> >>> LCD_D21        R5                    R3
> >>> LCD_D22        R6                    R4
> >>> LCD_D23        R7                    R5
> >>>
> >>> Is your display connected like LCD2 or LCD3? LCD3 must still handled
> >>> like a 24 bit display shown in LCD1, while only the LCD2-case is the
> >>> "24 bit to 18 bit mapping" case.
> >>>
> >>> At least my current tests with an i.MX23 and a connection like LCD2 are
> >>> working here with a Qt application. Qt honours the pixel bitfield
> >>> description. And I'm using the "bits-per-pixel = <32>" and "bus-width =
> >>> <18>" entries in the device tree.
> >>
> >> I have a 24bit LCD display but my connection to it is done at 18bits
> >> data width. Represented below as LCD4.
> >> NOTE: In my LCD4 column, notation Rx/Gx/Bx represent the color bit in
> >> memory as well as the display data line.
> >> Since we use 32bpp each channel has 8 bits (R7..R0, etc.).
> >> I understand that you have an 18bit display and that your notation in
> >> LCD2 column represents the display data lines, not the color bit indexes
> >> in memory.
> >>
> >> i.MX2[3|8]    LCD1       LCD2       LCD3	LCD4
> >>                24bit      18bit      18bit	24bit connected at 18bit
> >> -------------------------------------------------------
> >> LCD_D0         B0         B0         --		B2
> >> LCD_D1         B1         B1         --		B3
> >> LCD_D2         B2         B2         B0		B4
> >> LCD_D3         B3         B3         B1		B5
> >> LCD_D4         B4         B4         B2		B6
> >> LCD_D5         B5         B5         B3		B7
> >> LCD_D6         B6         G0         B4		G2
> >> LCD_D7         B7         G1         B5		G3
> >>
> >> LCD_D8         G0         G2         --		G4
> >> LCD_D9         G1         G3         --		G5
> >> LCD_D10        G2         G4         G0		G6
> >> LCD_D11        G3         G5         G1		G7
> >> LCD_D12        G4         R0         G2		R2
> >> LCD_D13        G5         R1         G3		R3
> >> LCD_D14        G6         R2         G4		R4
> >> LCD_D15        G7         R3         G5		R5
> >>
> >> LCD_D16        R0         R4         --		R6
> >> LCD_D17        R1         R5         --		R7
> >> LCD_D18        R2                    R0
> >> LCD_D19        R3                    R1
> >> LCD_D20        R4                    R2
> >> LCD_D21        R5                    R3
> >> LCD_D22        R6                    R4
> >> LCD_D23        R7                    R5
> >>
> >> For 32bpp (RGB888) and 18bit data bus I would expect the LCD controller
> >> to take the six *most significant* bits [7..2] from each color byte out
> >> to the LCD data bus (LCD_D17..D0) in the order depicted in my LCD4
> >> column.
> >>
> >> I'm not sure what the DATA_FORMAT_24_BIT flag is doing, but dropping the
> >> two most significant bits of color in memory doesn't seem to be a good
> >> idea unless (maybe) color is in 18bpp. Previous kernels did not even
> >> touch this flag.
> >>
> >> Does the following patch make sense?
> >>
> >> diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
> >> index b1c1a80..bb0a4e1 100644
> >> --- a/drivers/video/mxsfb.c
> >> +++ b/drivers/video/mxsfb.c
> >> @@ -298,9 +298,6 @@ static int mxsfb_check_var(struct fb_var_screeninfo
> >> *var, break;
> >>                   case STMLCDIF_16BIT:
> >>                   case STMLCDIF_18BIT:
> >> -                       /* 24 bit to 18 bit mapping */
> >> -                       rgb = def_rgb666;
> >> -                       break;
> >>                   case STMLCDIF_24BIT:
> >>                           /* real 24 bit */
> >>                           rgb = def_rgb888;
> >> @@ -424,11 +421,6 @@ static int mxsfb_set_par(struct fb_info *fb_info)
> >>                           return -EINVAL;
> >>                   case STMLCDIF_16BIT:
> >>                   case STMLCDIF_18BIT:
> >> -                       /* 24 bit to 18 bit mapping */
> >> -                       ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> >> -                                           *  each colour component
> >> -                                           */
> >> -                       break;
> >>                   case STMLCDIF_24BIT:
> >>                           /* real 24 bit */
> >>                           break;
> >>
> >> The setting of def_rgb666 for a 32bpp color depth does not make sense to
> >> me because the color in memory is really rgb888.
> >>
> >> With this patch, my true color images are displayed ok and so does the
> >> penguin logo. I don't know however how other displays connections at
> >> 18bit will do.
> >
> > Your 24 bit display is connected like a regular 18 bit display. So they
> > should work in the same way with the same settings. You *must* always
> > skip two data bits from the memory RGB888 to form a RGB666 value.
> >
> > I just did some measurement here with my i.MX23 based hardware.
> >
> > I'm using 32 bits per pixel and the 18 bit display interface
> > (LCD_D[0..17]).
> >
> > And surprise, surprise: the i.MX23 *always* maps the 24 bit input data to
> > the 18 bit interface. And what does the DATA_FORMAT_24_BIT aka. CTRL_DF24
> > do??? Just simple: it seems its meaning changes with the interface width.
> > The documentation says:
> >
> >    0 = all 24 bits are valid
> >    1 = drop upper 2 bits per byte
> >
> > This text seems valid for a real 24 bit display (but I cannot test it).
> > From my measurement its meaning changes when used with an 18 bit display
> > to:
> >
> >    0 = drop lower 2 bits per byte
> >    1 = drop upper 2 bits per byte
> >
> > When this bit is 0:
> >
> >        red     green    blue
> >     10000001|00001111|10001111 (memory layout)
> >
> >     100000..|000011..|100011.. (at the display)
> >
> > When this bit is 1:
> >
> >        red     green    blue
> >     10000001|00001111|10001111 (memory layout)
> >
> >     ..000001|..001111|..001111 (at the display)
>
> And how can the setting of this flag be useful?

Maybe with this measurement knowledge is isn't useful any more. When I wrote 
this code I just used the datasheet.

> In the example above, you had a red component of 0x81 (half way through the
> scale), which is converted to a 0x01 (almost black) at the display. Isn't
> this wrong?
>
> This only looks right to me if you set a 18bpp but even in that case
> masking the upper bits isn't really needed at all.

These bits should only show what is happen to the data. In both cases you must 
define a corresponding fb_bitfield description. Which means the currently 
existing def_rgb666 description is valid only when the DATA_FORMAT_24_BIT 
aka. CTRL_DF24 register bit is set.

And for the DATA_FORMAT_24_BIT aka. CTRL_DF24 register be cleared you *can* 
use the def_rgb888 or define a different def_rgb666_shift like this one:

static const struct fb_bitfield def_rgb666_shift[] = {
	[RED] = {
		.offset = 18,
		.length = 6,
	},
	[GREEN] = {
		.offset = 10,
		.length = 6,
	},
	[BLUE] = {
		.offset = 2,
		.length = 6,
	},
	[TRANSP] = {	/* no support for transparency */
		.length = 0,
	}
};

I'm not sure if it is of interest for a userland application to know if a 
display can handle 256 k or 16 M colours physically.
With the def_rgb888 in use *all* displays look like 16 M colour LCDs. With the 
def_rgb666 in use an 18 bit display really looks like an 18 bit display.

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From catalin.marinas at arm.com  Fri May 24 07:03:06 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:03:06 +0100
Subject: [PATCH v2 3/4] ARM: mm: HugeTLB support for LPAE systems.
In-Reply-To: <1369323080-9673-4-git-send-email-steve.capper@linaro.org>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
 <1369323080-9673-4-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524110306.GC18272@arm.com>

On Thu, May 23, 2013 at 04:31:19PM +0100, Steve Capper wrote:
> From: Catalin Marinas <catalin.marinas at arm.com>
> 
> This patch adds support for hugetlbfs based on the x86 implementation.

Can we not share the x86 code as you are proposing for arm64 already?

-- 
Catalin


From linus.walleij at linaro.org  Fri May 24 07:03:25 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 13:03:25 +0200
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <519E9ADA.3040204@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <519E9ADA.3040204@gmail.com>
Message-ID: <CACRpkdbsicPkPAiaQCOg2mQF2Ce2dg_K=BKqqx=FCdAH7Y+QBg@mail.gmail.com>

On Fri, May 24, 2013 at 12:40 AM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:
> On 05/23/2013 08:40 PM, Jason Cooper wrote:

>> I think marvell,psc1_reset =<>; gives us the most flexibility in
>> accurately describing the hardware.
>
>
> IMHO using that is just another workaround for a broken driver. We
> could hack the whole register setup in DT as it would still accurately
> describe HW. Don't get me wrong, but I don't like it.
>
> Haven't checked how happy Linus Walleij is about pinctrl drivers with
> reg values hacked in lately.

One of the things I've been ranting about lately is that Linux
subsystem maintainers have become de-facto device tree
standard commite chairs. :-(

So to the actual question:

In general I think we need to draw a line and define what we
mean with "describing the hardware" in a device tree.

We have some consensus:
- <reg> properties to describe regsiter BASE offset in physical
  memory and size.
- Resources like IRQ, DMA channel, regulator, GPIO pin control
  handles, are passed using <&ampersand> notation.

And so it goes on.

When it comes to defining different registers and their individual
bits and the meaning of these and/or default values, I personally
think that is making things harder for developers rather than
simplifying things. I know that pinctrl-single is anyway doing this
and I was talked into accepting it under circumstances where
developers are being passed opaque machine-generated
data that would otherwise be translated into unreadable header
files littering the kernel.

For a coder it is definately better if the *driver* know these
details, but whether that is possible seems to depend on things
like hardware development process.

IMO: if you want to go down that road, what you really want is not
ever more expressible device trees, but real open firmware,
or ACPI or UEFI that can interpret and run bytecode as some
"bios" for you. With DT coming from OF maybe this is a natural
progression of things, but one has to realize when we reach the
point where what we really want is a bios. Then your time is
likely better spent with Tianocore or something than with the
kernel.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri May 24 07:08:17 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 13:08:17 +0200
Subject: [PATCH v3 1/2] pinctrl: add MVF600 pinctrl driver
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CC580@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1368685224-17915-1-git-send-email-b35083@freescale.com>
 <20130520033207.GD25113@S2101-09.ap.freescale.net>
 <CAAQ0ZWSZeqOEceN-KmDS4_BT27_4xCYjfFMj8sHkEonOXaoF_g@mail.gmail.com>
 <B56CDBE15CE27145A4B77D2D24263E851CBBA4@039-SN1MPN1-003.039d.mgd.msft.net>
 <CAAQ0ZWTBZ=10B+0Zc4iZmvrr0hzdBKf1mn1CzhJokWE44dxsoA@mail.gmail.com>
 <CACRpkdZ=67CWrPqFMU4FeES5OUyV5=Zz2fwy-GAMVHrNU6y6jA@mail.gmail.com>
 <B56CDBE15CE27145A4B77D2D24263E851CC580@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <CACRpkdbghJBvtDy5irT-wsNqzbY2XquFKduUSzjV8tsUO_7eZA@mail.gmail.com>

On Fri, May 24, 2013 at 11:25 AM, Lu Jingchang-B35083
<B35083 at freescale.com> wrote:

>>Now it appears I applied 2/2 but not 1/2 due to comments.
>>
>>Are they orthogonal or do I need to pull the applied patch out again?
>>
> [Lu Jingchang-B35083]
> Please pull the applied patch out again, I will resend the patch to keep the patch's sequence.

OK.

Yours,
Linus Walleij


From catalin.marinas at arm.com  Fri May 24 07:11:52 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:11:52 +0100
Subject: [PATCH 01/11] mm: hugetlb: Copy huge_pmd_share from x86 to mm.
In-Reply-To: <1369328878-11706-2-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-2-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524111152.GD18272@arm.com>

On Thu, May 23, 2013 at 06:07:48PM +0100, Steve Capper wrote:
> Under x86, multiple puds can be made to reference the same bank of
> huge pmds provided that they represent a full PUD_SIZE of shared
> huge memory that is aligned to a PUD_SIZE boundary.
> 
> The code to share pmds does not require any architecture specific
> knowledge other than the fact that pmds can be indexed, thus can
> be beneficial to some other architectures.
> 
> This patch copies the huge pmd sharing (and unsharing) logic from
> x86/ to mm/ and introduces a new config option to activate it:
> CONFIG_ARCH_WANTS_HUGE_PMD_SHARE
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From linus.walleij at linaro.org  Fri May 24 07:13:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 13:13:58 +0200
Subject: [PATCH] ARM: ux500: enable the crypto and hash on all dbx500
In-Reply-To: <20130524082758.GP22683@gmail.com>
References: <1369378122-25897-1-git-send-email-linus.walleij@stericsson.com>
 <20130524082758.GP22683@gmail.com>
Message-ID: <CACRpkdb1CZKoaG6nNF-yBC3Eovoe3_0BHa6uO-OQkePDcrkamg@mail.gmail.com>

On Fri, May 24, 2013 at 10:27 AM, Lee Jones <lee.jones at linaro.org> wrote:
> On Fri, 24 May 2013, Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij at linaro.org>
>>
>> Commits:
>> "ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
>> "ARM: ux500: Add Device Tree nodes for the ux500 Hash device"
>>
>> Added the crypto and hash devices conditionally, i.e. so as to
>> be turned on per-board by setting an "status" property on the
>> device from "disabled" to "okay" on each device.
>>
>> This is wrong since this is an SoC feature, it is not board
>> dependent. It is the same ASIC under all circumstances and
>> functionality does not vary with board family.
>>
>> This moves the enablement into the SoC file.
>>
>> Cc: Lee Jones <lee.jones at linaro.org>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>> ---
>>  arch/arm/boot/dts/dbx5x0.dtsi  | 4 ----
>>  arch/arm/boot/dts/snowball.dts | 8 --------
>>  2 files changed, 12 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
>> index f051963..cd5cd09 100644
>> --- a/arch/arm/boot/dts/dbx5x0.dtsi
>> +++ b/arch/arm/boot/dts/dbx5x0.dtsi
>> @@ -760,17 +760,13 @@
>>                       compatible = "stericsson,ux500-cryp";
>>                       reg = <0xa03cb000 0x1000>;
>>                       interrupts = <0 15 0x4>;
>> -
>
> Why do you insist on removing all line spacings from the DTS file?
>
> I saw you removing them in between nodes too.

I was hit by a linespace when I was a child, since then I take
every opportunity for revenge.

If I keep the spacing, can I have your ACK?

Yours,
Linus Walleij


From catalin.marinas at arm.com  Fri May 24 07:13:59 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:13:59 +0100
Subject: [PATCH 02/11] x86: mm: Remove x86 version of huge_pmd_share.
In-Reply-To: <1369328878-11706-3-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-3-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524111359.GE18272@arm.com>

On Thu, May 23, 2013 at 06:07:49PM +0100, Steve Capper wrote:
> The huge_pmd_share code has been copied over to mm/hugetlb.c to
> make it accessible to other architectures.
> 
> Remove the x86 copy of the huge_pmd_share code and enable the
> ARCH_WANT_HUGE_PMD_SHARE config flag. That way we reference the
> general one.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Fri May 24 07:14:33 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:14:33 +0100
Subject: [PATCH 03/11] mm: hugetlb: Copy general hugetlb code from x86
 to mm.
In-Reply-To: <1369328878-11706-4-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-4-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524111433.GF18272@arm.com>

On Thu, May 23, 2013 at 06:07:50PM +0100, Steve Capper wrote:
> The huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d
> functions in x86/mm/hugetlbpage.c do not rely on any architecture
> specific knowledge other than the fact that pmds and puds can be
> treated as huge ptes.
> 
> To allow other architectures to use this code (and reduce the need
> for code duplication), this patch copies these functions into mm,
> replaces the use of pud_large with pud_huge and provides a config
> flag to activate them:
> CONFIG_ARCH_WANT_GENERAL_HUGETLB
> 
> If CONFIG_ARCH_WANT_HUGE_PMD_SHARE is also active then the
> huge_pmd_share code will be called by huge_pte_alloc (othewise we
> call pmd_alloc and skip the sharing code).
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Fri May 24 07:14:59 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:14:59 +0100
Subject: [PATCH 04/11] x86: mm: Remove general hugetlb code from x86.
In-Reply-To: <1369328878-11706-5-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-5-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524111459.GG18272@arm.com>

On Thu, May 23, 2013 at 06:07:51PM +0100, Steve Capper wrote:
> huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d have
> already been copied over to mm.
> 
> This patch removes the x86 copies of these functions and activates
> the general ones by enabling:
> CONFIG_ARCH_WANT_GENERAL_HUGETLB
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From linus.walleij at linaro.org  Fri May 24 07:16:42 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 13:16:42 +0200
Subject: [PATCH 5/6] crypto: ux500/cryp - Enable DT probing of the driver
In-Reply-To: <20130524083231.GQ22683@gmail.com>
References: <1368703646-26418-1-git-send-email-lee.jones@linaro.org>
 <1368703646-26418-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZHT0g_Agtug6jC3rU+DYKOpmwqZ9eQAkRGRw5Kj0wW4A@mail.gmail.com>
 <20130524083231.GQ22683@gmail.com>
Message-ID: <CACRpkdbek9PFXOwCVQ+PcSMMCZyD3gW+bC6PhyjSnB76zCiHmA@mail.gmail.com>

On Fri, May 24, 2013 at 10:32 AM, Lee Jones <lee.jones at linaro.org> wrote:
> On Fri, 24 May 2013, Linus Walleij wrote:
>> On Thu, May 16, 2013 at 1:27 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > By providing an OF match table with a suitable compatible string, we
>> > can ensure the ux500-crypt driver is probed by supplying an associated
>> > DT node in a given platform's Device Tree.
>> >
>> > Cc: Herbert Xu <herbert at gondor.apana.org.au>
>> > Cc: linux-crypto at vger.kernel.org
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> Herbert, can I have your ACK on patch 5 & 6 in this series to take it
>> through the ARM SoC tree?
>
> Right, there are no bindings, so they don't need a document.

Surely the requirement that the node must have <reg>,
<irqs> and <regulator> for the driver to even probe is a
binding?

The fact that the drivers/of/* core on Linux will auto-populate
platform devices with those properties is a pure Linux
pecularity, and the bindings are there for OS independence.

Whether we need to document it for such standard things
is another thing, hopefully Rob or someone can answer that?

Yours,
Linus Walleij


From catalin.marinas at arm.com  Fri May 24 07:18:16 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:18:16 +0100
Subject: [PATCH 03/11] mm: hugetlb: Copy general hugetlb code from x86
 to mm.
In-Reply-To: <1369328878-11706-4-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-4-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524111816.GH18272@arm.com>

On Thu, May 23, 2013 at 06:07:50PM +0100, Steve Capper wrote:
> The huge_pte_alloc, huge_pte_offset and follow_huge_p[mu]d
> functions in x86/mm/hugetlbpage.c do not rely on any architecture
> specific knowledge other than the fact that pmds and puds can be
> treated as huge ptes.
> 
> To allow other architectures to use this code (and reduce the need
> for code duplication), this patch copies these functions into mm,
> replaces the use of pud_large with pud_huge and provides a config
> flag to activate them:
> CONFIG_ARCH_WANT_GENERAL_HUGETLB

BTW, I think it's worth mentioning that pud_large is inline while
pud_huge is not.

-- 
Catalin


From catalin.marinas at arm.com  Fri May 24 07:18:42 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:18:42 +0100
Subject: [PATCH 05/11] mm: thp: Correct the HPAGE_PMD_ORDER check.
In-Reply-To: <1369328878-11706-6-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-6-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524111842.GI18272@arm.com>

On Thu, May 23, 2013 at 06:07:52PM +0100, Steve Capper wrote:
> All Transparent Huge Pages are allocated by the buddy allocator.
> 
> A compile time check is in place that fails when the order of a
> transparent huge page is too large to be allocated by the buddy
> allocator. Unfortunately that compile time check passes when:
> HPAGE_PMD_ORDER == MAX_ORDER
> ( which is incorrect as the buddy allocator can only allocate
> memory of order strictly less than MAX_ORDER. )
> 
> This patch updates the compile time check to fail in the above
> case.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From catalin.marinas at arm.com  Fri May 24 07:21:49 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:21:49 +0100
Subject: [PATCH 07/11] ARM64: mm: Make PAGE_NONE pages read only and
 no-execute.
In-Reply-To: <1369328878-11706-8-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-8-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524112149.GJ18272@arm.com>

On Thu, May 23, 2013 at 06:07:54PM +0100, Steve Capper wrote:
> If we consider the following code sequence:
> 
> 	my_pte = pte_modify(entry, myprot);
> 	x = pte_write(my_pte);
> 	y = pte_exec(my_pte);
> 
> If myprot comes from a PROT_NONE page, then x and y will both be
> true which is undesireable behaviour.
> 
> This patch sets the no-execute and read-only bits for PAGE_NONE
> such that the code above will return false for both x and y.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From lee.jones at linaro.org  Fri May 24 07:22:19 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 12:22:19 +0100
Subject: [PATCH] ARM: ux500: Provide supplies for AUX1, AUX2 and AUX3
Message-ID: <1369394539-3713-1-git-send-email-lee.jones@linaro.org>

This patch fixes a bug introduced in the v3.10 merge window.

The AB8500 External Regulator driver has recently landed upstream,
which registers each of the 3 external regulators located on the
AB8500. If these regulators are marked as 'always on', there is a
potential for power-loss. If they're not and are seemingly unused
the Regulator subsystem will attempt to disable them to save power.
This causes an issue for AUX1, AUX2 and AUX3 as they obtain their
power from EXT3. So we're specifying that here to prevent EXT3 from
being powered down.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-regulators.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 33c353b..d6b7c85 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -374,6 +374,7 @@ static struct ab8500_regulator_reg_init ab8500_reg_init[] = {
 static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
 	/* supplies to the display/camera */
 	[AB8500_LDO_AUX1] = {
+		.supply_regulator = "ab8500-ext-supply3",
 		.constraints = {
 			.name = "V-DISPLAY",
 			.min_uV = 2800000,
@@ -387,6 +388,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
 	},
 	/* supplies to the on-board eMMC */
 	[AB8500_LDO_AUX2] = {
+		.supply_regulator = "ab8500-ext-supply3",
 		.constraints = {
 			.name = "V-eMMC1",
 			.min_uV = 1100000,
@@ -402,6 +404,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
 	},
 	/* supply for VAUX3, supplies to SDcard slots */
 	[AB8500_LDO_AUX3] = {
+		.supply_regulator = "ab8500-ext-supply3",
 		.constraints = {
 			.name = "V-MMC-SD",
 			.min_uV = 1100000,
-- 
1.7.10.4



From linux at arm.linux.org.uk  Fri May 24 07:20:29 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 12:20:29 +0100
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
 <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
Message-ID: <20130524112029.GW18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> code snippet to the internal SRAM, then jump to run this code, but fail
> to run.

And that is where your mistake is - you forgot that you're working with
a CPU with harvard caches which will require some cache maintanence
between copying the code and executing it.

You want to look at flush_icache_range() rather than making this memory
strongly ordered.


From lee.jones at linaro.org  Fri May 24 07:23:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 12:23:33 +0100
Subject: [PATCH] regulator: ab8500-ext: Don't register without
 initialisation data
In-Reply-To: <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20130524112333.GW22683@gmail.com>

On Wed, 22 May 2013, Lee Jones wrote:

> This patch fixes a bug introduced in the v3.10 merge window.
> 
> Some platforms will not want external registers. Rather than setting up
> lots of different clauses in the core ab8500 regulator driver not to
> call ab8500-ext init() we just won't pass the initialisation data from
> platform code. This patch checks for it and if it's missing, we won't
> register the external regulators.
> 
> Cc: Mark Brown <broonie at kernel.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/regulator/ab8500-ext.c |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/regulator/ab8500-ext.c b/drivers/regulator/ab8500-ext.c
> index b4d4547..8421537 100644
> --- a/drivers/regulator/ab8500-ext.c
> +++ b/drivers/regulator/ab8500-ext.c
> @@ -334,6 +334,12 @@ int ab8500_ext_regulator_init(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> +	/* have any external regulators been specified? */
> +	if (pdata->num_ext_regulator == 0) {
> +		dev_warn(&pdev->dev, "Not using external regulators\n");
> +		return 0;
> +	}
> +
>  	/* make sure the platform data has the correct size */
>  	if (pdata->num_ext_regulator != ARRAY_SIZE(ab8500_ext_regulator_info)) {
>  		dev_err(&pdev->dev, "Configuration error: size mismatch.\n");

Okay drop this patch, I have a better solution.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From catalin.marinas at arm.com  Fri May 24 07:23:46 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 12:23:46 +0100
Subject: [PATCH 09/11] ARM64: mm: HugeTLB support.
In-Reply-To: <1369328878-11706-10-git-send-email-steve.capper@linaro.org>
References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org>
 <1369328878-11706-10-git-send-email-steve.capper@linaro.org>
Message-ID: <20130524112346.GK18272@arm.com>

On Thu, May 23, 2013 at 06:07:56PM +0100, Steve Capper wrote:
> Add huge page support to ARM64, different huge page sizes are
> supported depending on the size of normal pages:
> 
> PAGE_SIZE is 4KB:
>    2MB - (pmds) these can be allocated at any time.
> 1024MB - (puds) usually allocated on bootup with the command line
>          with something like: hugepagesz=1G hugepages=6
> 
> PAGE_SIZE is 64KB:
>  512MB - (pmds) usually allocated on bootup via command line.
> 
> Signed-off-by: Steve Capper <steve.capper at linaro.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From lee.jones at linaro.org  Fri May 24 07:25:24 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 12:25:24 +0100
Subject: [PATCH] ARM: ux500: Allow Snowball to pass its own regulator
 settings
In-Reply-To: <1369226853-16978-2-git-send-email-lee.jones@linaro.org>
References: <1369226853-16978-1-git-send-email-lee.jones@linaro.org>
 <1369226853-16978-2-git-send-email-lee.jones@linaro.org>
Message-ID: <20130524112524.GX22683@gmail.com>

On Wed, 22 May 2013, Lee Jones wrote:

> This patch fixes a bug introduced in the v3.10 merge window.
> 
> Currently the external regulator settings are passed though to the AB8500
> regulator driver regards of whether they can or should be used on any
> ux500 based platform. They are not applicable for the u8505 and when
> enabled, they turn off AUX2 which adversely affects the eMMC on Snowball.
> 
> The driver already knows that the external regulator settings are not
> appropriate for the u8505, however it's more difficult for driver code to
> distinguish between two different u8500 based platforms.
> 
> Using the new semantics, we can just not pass the external regulator
> initialisation values from platform code and the external regulator
> driver will know not to register them.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/board-mop500-regulators.c |    8 ++++++++
>  arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
>  arch/arm/mach-ux500/board-mop500.c            |    2 ++
>  3 files changed, 11 insertions(+)
> 
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
> index b34441b..7399e90 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.c
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.c
> @@ -996,6 +996,14 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
>  	.num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
>  };
>  
> +/* External regulators turn off VAUX2 when in use on Snowball. */
> +struct ab8500_regulator_platform_data snowball_regulator_plat_data = {
> +	.reg_init               = ab8500_reg_init,
> +	.num_reg_init           = ARRAY_SIZE(ab8500_reg_init),
> +	.regulator              = ab8500_regulators,
> +	.num_regulator          = ARRAY_SIZE(ab8500_regulators),
> +};
> +
>  struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
>  	.reg_init               = ab8505_reg_init,
>  	.num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
> index 039f513..6300e79 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.h
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.h
> @@ -16,6 +16,7 @@
>  
>  extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
>  extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
> +extern struct ab8500_regulator_platform_data snowball_regulator_plat_data;
>  extern struct regulator_init_data tps61052_regulator;
>  extern struct regulator_init_data gpio_en_3v3_regulator;
>  extern struct regulator_init_data sdi0_reg_init_data;
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index 0b018c4..2d609d4 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -615,6 +615,8 @@ static void __init snowball_init_machine(void)
>  	struct device *parent = NULL;
>  	int i;
>  
> +	ab8500_platdata.regulator = &snowball_regulator_plat_data;
> +
>  	platform_device_register(&db8500_prcmu_device);
>  
>  	sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;

Please drop this patch, I have sent a better solution.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linux at arm.linux.org.uk  Fri May 24 07:26:10 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 12:26:10 +0100
Subject: [GIT PULL] arm-soc: Xilinx zynq core - smp for v3.10
In-Reply-To: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
References: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
Message-ID: <20130524112610.GX18614@n2100.arm.linux.org.uk>

On Thu, Apr 04, 2013 at 09:47:09AM +0200, Michal Simek wrote:
> Hi Arnd and Olof,
>
> please pull the following smp support to your arm-soc tree.
>
> This branch is based on zynq/clksrc/cleanup parts because
> there are some dependencies on moving timer to generic location.
>
> I could based it on standard Linux tagged version but you will get
> several conflicts you will have to resolve.
> If you are OK to resolving these problems, please let me know
> I will create another branch with core-smp changes which are not based
> on zynq/clksrc/cleanup branch.

You might want to resolve this new warning:

arch/arm/mach-zynq/hotplug.c:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march= switch

found by lastnights OMAP4430 randconfig build.


From lee.jones at linaro.org  Fri May 24 07:26:27 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 12:26:27 +0100
Subject: [PATCH] ARM: ux500: regulators: Remove misleading comment
In-Reply-To: <1369227995-17142-1-git-send-email-lee.jones@linaro.org>
References: <1369227995-17142-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20130524112627.GY22683@gmail.com>

On Wed, 22 May 2013, Lee Jones wrote:

> This patch removes a comment which explains that the ab8505 platform
> uses the same initialisation settings as the ab8500. Well when this
> changed and the ab8505 started using its own set of initialisation
> values, someone forgot to remove it.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/board-mop500-regulators.c |    1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
> index 33c353b..b34441b 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.c
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.c
> @@ -996,7 +996,6 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
>  	.num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
>  };
>  
> -/* Use the AB8500 init settings for AB8505 as they are the same right now */
>  struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
>  	.reg_init               = ab8505_reg_init,
>  	.num_reg_init           = ARRAY_SIZE(ab8505_reg_init),

This patch still stands though.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Fri May 24 07:31:26 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 May 2013 12:31:26 +0100
Subject: [PATCH v2 3/4] ARM: cacheflush: don't round address range up to
 nearest page
In-Reply-To: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
References: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
Message-ID: <1369395087-30972-4-git-send-email-will.deacon@arm.com>

The flush_cache_user_range macro takes a pair of addresses describing
the start and end of the virtual address range to flush. Due to an
accidental oversight when flush_cache_range_user was introduced, the
address range was rounded up so that the start and end addresses were
page-aligned.

For historical reference, the interesting commits in history.git are:

10eacf1775e1 ("[ARM] Clean up ARM cache handling interfaces (part 1)")
71432e79b76b ("[ARM] Add flush_cache_user_page() for sys_cacheflush()")

This patch removes the alignment code, reducing the amount of flushing
required for ranges that are not an exact multiple of PAGE_SIZE.

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Jonathan Austin <jonathan.austin at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/cacheflush.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index bff7138..39c3faa 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -268,8 +268,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
  * Harvard caches are synchronised for the user space address range.
  * This is used for the ARM private sys_cacheflush system call.
  */
-#define flush_cache_user_range(start,end) \
-	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
+#define flush_cache_user_range(s,e)	__cpuc_coherent_user_range(s,e)
 
 /*
  * Perform necessary cache operations to ensure that data previously
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 24 07:31:27 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 May 2013 12:31:27 +0100
Subject: [PATCH v2 4/4] ARM: cacheflush: don't bother rounding to nearest vma
In-Reply-To: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
References: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
Message-ID: <1369395087-30972-5-git-send-email-will.deacon@arm.com>

do_cache_op finds the lowest VMA contained in the specified address
range and rounds the range to cover only the mapped addresses.

Since commit 4542b6a0fa6b ("ARM: 7365/1: drop unused parameter from
flush_cache_user_range") the VMA is not used for anything else in this
code and seeing as the low-level cache flushing routines return -EFAULT
if the address is not valid, there is no need for this range truncation.

This patch removes the VMA handling code from the cacheflushing syscall.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/traps.c | 17 ++---------------
 1 file changed, 2 insertions(+), 15 deletions(-)

diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 47092f2..9af88fd 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -548,24 +548,11 @@ static long do_cache_op_restart(struct restart_block *unused)
 static inline int
 do_cache_op(unsigned long start, unsigned long end, int flags)
 {
-	struct mm_struct *mm = current->active_mm;
-	struct vm_area_struct *vma;
-
 	if (end < start || flags)
 		return -EINVAL;
 
-	down_read(&mm->mmap_sem);
-	vma = find_vma(mm, start);
-	if (!vma || vma->vm_start >= end) {
-		up_read(&mm->mmap_sem);
-		return -EINVAL;
-	}
-
-	if (start < vma->vm_start)
-		start = vma->vm_start;
-	if (end > vma->vm_end)
-		end = vma->vm_end;
-	up_read(&mm->mmap_sem);
+	if (!access_ok(VERIFY_READ, start, end - start))
+		return -EFAULT;
 
 	return __do_cache_op(start, end);
 }
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 24 07:31:24 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 May 2013 12:31:24 +0100
Subject: [PATCH v2 1/4] ARM: entry: allow ARM-private syscalls to be restarted
In-Reply-To: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
References: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
Message-ID: <1369395087-30972-2-git-send-email-will.deacon@arm.com>

System calls will only be restarted after signal handling if they (a)
return an error code indicating that a restart is required and (b) have
`why' set to a non-zero value, to indicate that the signal interrupted
them.

This patch leaves `why' set to a non-zero value for ARM-private syscalls
, and only zeroes it for syscalls that are not implemented.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/entry-common.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a..8f38d24 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -437,10 +437,10 @@ local_restart:
 	ldrcc	pc, [tbl, scno, lsl #2]		@ call sys_* routine
 
 	add	r1, sp, #S_OFF
-2:	mov	why, #0				@ no longer a real syscall
 	cmp	scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)
 	eor	r0, scno, #__NR_SYSCALL_BASE	@ put OS number back
-	bcs	arm_syscall	
+	bcs	arm_syscall
+2:	mov	why, #0				@ no longer a real syscall
 	b	sys_ni_syscall			@ not private func
 ENDPROC(vector_swi)
 
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 24 07:31:25 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 May 2013 12:31:25 +0100
Subject: [PATCH v2 2/4] ARM: cacheflush: split user cache-flushing into
 interruptible chunks
In-Reply-To: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
References: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
Message-ID: <1369395087-30972-3-git-send-email-will.deacon@arm.com>

Flushing a large, non-faulting VMA from userspace can potentially result
in a long time spent flushing the cache line-by-line without preemption
occurring (in the case of CONFIG_PREEMPT=n).

Whilst this doesn't affect the stability of the system, it can certainly
affect the responsiveness and CPU availability for other tasks.

This patch splits up the user cacheflush code so that it flushes in
chunks of a page. After each chunk has been flushed, we may reschedule
if appropriate and, before processing the next chunk, we allow any
pending signals to be handled before resuming from where we left off.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/thread_info.h | 11 +++++++
 arch/arm/kernel/traps.c            | 63 +++++++++++++++++++++++++++++++++-----
 2 files changed, 66 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 1995d1a..5c3964b 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -43,6 +43,16 @@ struct cpu_context_save {
 	__u32	extra[2];		/* Xscale 'acc' register, etc */
 };
 
+struct arm_restart_block {
+	union {
+		/* For user cache flushing */
+		struct {
+			unsigned long start;
+			unsigned long end;
+		} cache;
+	};
+};
+
 /*
  * low level task data that entry.S needs immediate access to.
  * __switch_to() assumes cpu_context follows immediately after cpu_domain.
@@ -68,6 +78,7 @@ struct thread_info {
 	unsigned long		thumbee_state;	/* ThumbEE Handler Base register */
 #endif
 	struct restart_block	restart_block;
+	struct arm_restart_block	arm_restart_block;
 };
 
 #define INIT_THREAD_INFO(tsk)						\
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 18b32e8..47092f2 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -499,6 +499,52 @@ static int bad_syscall(int n, struct pt_regs *regs)
 	return regs->ARM_r0;
 }
 
+static long do_cache_op_restart(struct restart_block *);
+
+static inline int
+__do_cache_op(unsigned long start, unsigned long end)
+{
+	int ret;
+	unsigned long chunk = PAGE_SIZE;
+
+	do {
+		if (signal_pending(current)) {
+			struct thread_info *ti = current_thread_info();
+
+			ti->restart_block = (struct restart_block) {
+				.fn	= do_cache_op_restart,
+			};
+
+			ti->arm_restart_block = (struct arm_restart_block) {
+				.cache = {
+					.start	= start,
+					.end	= end,
+				},
+			};
+
+			return -ERESTART_RESTARTBLOCK;
+		}
+
+		ret = flush_cache_user_range(start, start + chunk);
+		if (ret)
+			return ret;
+
+		cond_resched();
+		start += chunk;
+	} while (start < end);
+
+	return 0;
+}
+
+static long do_cache_op_restart(struct restart_block *unused)
+{
+	struct arm_restart_block *restart_block;
+
+	restart_block = &current_thread_info()->arm_restart_block;
+	return __do_cache_op(restart_block->cache.start,
+			     restart_block->cache.end);
+}
+
 static inline int
 do_cache_op(unsigned long start, unsigned long end, int flags)
 {
@@ -510,17 +556,18 @@ do_cache_op(unsigned long start, unsigned long end, int flags)
 
 	down_read(&mm->mmap_sem);
 	vma = find_vma(mm, start);
-	if (vma && vma->vm_start < end) {
-		if (start < vma->vm_start)
-			start = vma->vm_start;
-		if (end > vma->vm_end)
-			end = vma->vm_end;
-
+	if (!vma || vma->vm_start >= end) {
 		up_read(&mm->mmap_sem);
-		return flush_cache_user_range(start, end);
+		return -EINVAL;
 	}
+
+	if (start < vma->vm_start)
+		start = vma->vm_start;
+	if (end > vma->vm_end)
+		end = vma->vm_end;
 	up_read(&mm->mmap_sem);
-	return -EINVAL;
+
+	return __do_cache_op(start, end);
 }
 
 /*
-- 
1.8.2.2



From will.deacon at arm.com  Fri May 24 07:31:23 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 May 2013 12:31:23 +0100
Subject: [PATCH v2 0/4] Optimise cache-flushing system call
Message-ID: <1369395087-30972-1-git-send-email-will.deacon@arm.com>

Hi guys,

This is a follow-on from the patches I originally posted here:

  http://lists.infradead.org/pipermail/linux-arm-kernel/2013-March/157810.html

but with some notable differences:

  - I've temporarily dropped the iovec system call while I try to work
    out a sane threshold value between flushing by line and nuking L1.

  - Added syscall restarting to address DoS issues raised by Catalin.

  - Added access_ok check now that vma searching code is removed.

  - Based on 3.10-rc2.

As per usual, all comments are welcome.

Cheers,

Will


Will Deacon (4):
  ARM: entry: allow ARM-private syscalls to be restarted
  ARM: cacheflush: split user cache-flushing into interruptible chunks
  ARM: cacheflush: don't round address range up to nearest page
  ARM: cacheflush: don't bother rounding to nearest vma

 arch/arm/include/asm/cacheflush.h  |  3 +-
 arch/arm/include/asm/thread_info.h | 11 +++++++
 arch/arm/kernel/entry-common.S     |  4 +--
 arch/arm/kernel/traps.c            | 64 +++++++++++++++++++++++++++++---------
 4 files changed, 63 insertions(+), 19 deletions(-)

-- 
1.8.2.2



From mark.rutland at arm.com  Fri May 24 07:36:05 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Fri, 24 May 2013 12:36:05 +0100
Subject: [PATCHv3 0/5] arm: arch_timer cleanups and niceties
Message-ID: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>

The following patches clean up some (harmless) fallout from the changes
in 3.9, and make the driver always use the virtual counter, eliminating
problems relating to choosing which counters to use (racy
initialisation, branches in hot paths).

The patches can also be found in my public git tree:
git://linux-arm.org/git/linux-mr.git clocks/arch-timer-cleanups

Russell, are you happy to take these for 3.11 if I send a pull request or drop
these in your patch system?

Since v1 [1]:
* Rebased to v3.10-rc1
* Fix up mach-shmobile's selection of ARCH_ARM_TIMER
Since v2: [2]:
* Added Simon Horman's ack for shmobile
* Clarified virtual timer CNTVOFF requirement per Christopher Covington's
  comments.

Thanks,
Mark.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-March/158604.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/168536.html

Marc Zyngier (2):
  ARM: hyp: initialize CNTVOFF to zero
  ARM: arch_timer: stop virtual timer when booted in HYP mode

Mark Rutland (3):
  ARM: KVM: arch_timers: zero CNTVOFF upon return to host
  clocksource: arch_timer: use virtual counters
  arm: fix up ARM_ARCH_TIMER selects

 arch/arm/include/asm/arch_timer.h    |  9 ---------
 arch/arm/kernel/hyp-stub.S           |  7 +++++++
 arch/arm/kvm/interrupts_head.S       |  4 ++++
 arch/arm/mach-exynos/Kconfig         |  2 +-
 arch/arm/mach-shmobile/Kconfig       |  4 ++--
 arch/arm/mach-tegra/Kconfig          |  2 +-
 arch/arm/mach-virt/Kconfig           |  2 +-
 arch/arm64/include/asm/arch_timer.h  | 10 ----------
 drivers/clocksource/arm_arch_timer.c | 23 +++++------------------
 include/clocksource/arm_arch_timer.h |  2 +-
 10 files changed, 22 insertions(+), 43 deletions(-)

-- 
1.8.1.1



From mark.rutland at arm.com  Fri May 24 07:36:06 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Fri, 24 May 2013 12:36:06 +0100
Subject: [PATCHv3 1/5] ARM: hyp: initialize CNTVOFF to zero
In-Reply-To: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
References: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1369395370-21358-2-git-send-email-mark.rutland@arm.com>

From: Marc Zyngier <Marc.Zyngier at arm.com>

In order to be able to use the virtual counter in a safe way,
make sure it is initialized to zero before dropping to SVC.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/kernel/hyp-stub.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 1315c4c..dbe2110 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -153,6 +153,8 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
 	mrc	p15, 4, r7, c14, c1, 0	@ CNTHCTL
 	orr	r7, r7, #3		@ PL1PCEN | PL1PCTEN
 	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
+	mov	r7, #0
+	mcrr	p15, 4, r7, r7, c14	@ CNTVOFF
 1:
 #endif
 
-- 
1.8.1.1



From mark.rutland at arm.com  Fri May 24 07:36:07 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Fri, 24 May 2013 12:36:07 +0100
Subject: [PATCHv3 2/5] ARM: KVM: arch_timers: zero CNTVOFF upon return to host
In-Reply-To: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
References: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1369395370-21358-3-git-send-email-mark.rutland@arm.com>

To use the virtual counters from the host, we need to ensure that
CNTVOFF doesn't change unexpectedly. When we change to a guest, we
replace the host's CNTVOFF, but we don't restore it when returning to
the host.

As the host sets CNTVOFF to zero, and never changes it, we can simply
zero CNTVOFF when returning to the host. This patch adds said zeroing to
the return to host path.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Marc Zyngier <marc.zyngier at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Christoffer Dall <cdall at cs.columbia.edu>
---
 arch/arm/kvm/interrupts_head.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 3c8f2f0..d43cfb5 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -497,6 +497,10 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 	add	r5, vcpu, r4
 	strd	r2, r3, [r5]
 
+	@ Ensure host CNTVCT == CNTPCT
+	mov	r2, #0
+	mcrr	p15, 4, r2, r2, c14	@ CNTVOFF
+
 1:
 #endif
 	@ Allow physical timer/counter access for the host
-- 
1.8.1.1



From mark.rutland at arm.com  Fri May 24 07:36:08 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Fri, 24 May 2013 12:36:08 +0100
Subject: [PATCHv3 3/5] clocksource: arch_timer: use virtual counters
In-Reply-To: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
References: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1369395370-21358-4-git-send-email-mark.rutland@arm.com>

Switching between reading the virtual or physical counters is
problematic, as some core code wants a view of time before we're fully
set up. Using a function pointer and switching the source after the
first read can make time appear to go backwards, and having a check in
the read function is an unfortunate block on what we want to be a fast
path.

Instead, this patch makes us always use the virtual counters. If we're a
guest, or don't have hyp mode, we'll use the virtual timers, and as such
don't care about CNTVOFF as long as it doesn't change in such a way as
to make time appear to travel backwards. As the guest will use the
virtual timers, a (potential) KVM host must use the physical timers
(which can wake up the host even if they fire while a guest is
executing), and hence a host must have CNTVOFF set to zero so as to have
a consistent view of time between the physical timers and virtual
counters.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
Acked-by: Marc Zyngier <marc.zyngier at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/include/asm/arch_timer.h    |  9 ---------
 arch/arm64/include/asm/arch_timer.h  | 10 ----------
 drivers/clocksource/arm_arch_timer.c | 23 +++++------------------
 include/clocksource/arm_arch_timer.h |  2 +-
 4 files changed, 6 insertions(+), 38 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7c1bfc0..accefe0 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void)
 	return val;
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-	u64 cval;
-
-	isb();
-	asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-	return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
 	u64 cval;
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index bf6ab242..d56ed11 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -110,16 +110,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
 	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-	u64 cval;
-
-	isb();
-	asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
-
-	return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
 	u64 cval;
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index a2b2541..053d846 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -186,27 +186,19 @@ u32 arch_timer_get_rate(void)
 	return arch_timer_rate;
 }
 
-/*
- * Some external users of arch_timer_read_counter (e.g. sched_clock) may try to
- * call it before it has been initialised. Rather than incur a performance
- * penalty checking for initialisation, provide a default implementation that
- * won't lead to time appearing to jump backwards.
- */
-static u64 arch_timer_read_zero(void)
+u64 arch_timer_read_counter(void)
 {
-	return 0;
+	return arch_counter_get_cntvct();
 }
 
-u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero;
-
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
-	return arch_timer_read_counter();
+	return arch_counter_get_cntvct();
 }
 
 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
 {
-	return arch_timer_read_counter();
+	return arch_counter_get_cntvct();
 }
 
 static struct clocksource clocksource_counter = {
@@ -287,7 +279,7 @@ static int __init arch_timer_register(void)
 	cyclecounter.mult = clocksource_counter.mult;
 	cyclecounter.shift = clocksource_counter.shift;
 	timecounter_init(&timecounter, &cyclecounter,
-			 arch_counter_get_cntpct());
+			 arch_counter_get_cntvct());
 
 	if (arch_timer_use_virtual) {
 		ppi = arch_timer_ppi[VIRT_PPI];
@@ -376,11 +368,6 @@ static void __init arch_timer_init(struct device_node *np)
 		}
 	}
 
-	if (arch_timer_use_virtual)
-		arch_timer_read_counter = arch_counter_get_cntvct;
-	else
-		arch_timer_read_counter = arch_counter_get_cntpct;
-
 	arch_timer_register();
 	arch_timer_arch_init();
 }
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index e6c9c4c..c463ce9 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -32,7 +32,7 @@
 #ifdef CONFIG_ARM_ARCH_TIMER
 
 extern u32 arch_timer_get_rate(void);
-extern u64 (*arch_timer_read_counter)(void);
+extern u64 arch_timer_read_counter(void);
 extern struct timecounter *arch_timer_get_timecounter(void);
 
 #else
-- 
1.8.1.1



From mark.rutland at arm.com  Fri May 24 07:36:09 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Fri, 24 May 2013 12:36:09 +0100
Subject: [PATCHv3 4/5] arm: fix up ARM_ARCH_TIMER selects
In-Reply-To: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
References: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1369395370-21358-5-git-send-email-mark.rutland@arm.com>

In 8a4da6e: "arm: arch_timer: move core to drivers/clocksource", the
selection of ARM_ARCH_TIMER was indirected via HAVE_ARM_ARCH_TIMER,
though mach-exynos's selection of ARM_ARCH_TIMER was missed, and since
then mach-shmobile, mach-tegra, and mach-virt have begun selecting
ARM_ARCH_TIMER. This can lead to architected timer support erroneously
appearing to not be selected in menuconfig.

This patch fixes up the Kconfigs for those platforms to select
HAVE_ARM_ARCH_TIMER.

Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Stephen Warren <swarren at nvidia.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Simon Horman <horms+renesas at verge.net.au>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/mach-exynos/Kconfig   | 2 +-
 arch/arm/mach-shmobile/Kconfig | 4 ++--
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-virt/Kconfig     | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d19edff..3c3f36a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -76,7 +76,7 @@ config SOC_EXYNOS5440
 	default y
 	depends on ARCH_EXYNOS5
 	select ARCH_HAS_OPP
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select AUTO_ZRELADDR
 	select PINCTRL
 	select PINCTRL_EXYNOS5440
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2..767a6c3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,7 +23,7 @@ config ARCH_R8A73A4
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
 	select CPU_V7
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
 
@@ -56,7 +56,7 @@ config ARCH_R8A7790
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
 	select CPU_V7
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select SH_CLK_CPG
 	select RENESAS_IRQC
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc..65c5ae6 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -60,7 +60,7 @@ config ARCH_TEGRA_3x_SOC
 
 config ARCH_TEGRA_114_SOC
 	bool "Enable support for Tegra114 family"
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select ARM_GIC
 	select ARM_L1_CACHE_SHIFT_6
 	select CPU_FREQ_TABLE if CPU_FREQ
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
index 8958f0d..081d469 100644
--- a/arch/arm/mach-virt/Kconfig
+++ b/arch/arm/mach-virt/Kconfig
@@ -2,7 +2,7 @@ config ARCH_VIRT
 	bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
-	select ARM_ARCH_TIMER
+	select HAVE_ARM_ARCH_TIMER
 	select ARM_PSCI
 	select HAVE_SMP
 	select CPU_V7
-- 
1.8.1.1



From mark.rutland at arm.com  Fri May 24 07:36:10 2013
From: mark.rutland at arm.com (Mark Rutland)
Date: Fri, 24 May 2013 12:36:10 +0100
Subject: [PATCHv3 5/5] ARM: arch_timer: stop virtual timer when booted in HYP
 mode
In-Reply-To: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
References: <1369395370-21358-1-git-send-email-mark.rutland@arm.com>
Message-ID: <1369395370-21358-6-git-send-email-mark.rutland@arm.com>

From: Marc Zyngier <Marc.Zyngier at arm.com>

When booting the kernel, a bootloader could have left the virtual
timer ticking away, potentially generating interrupts. This could
be troublesome if the user of the virtual timer is not careful
when enabling the interrupt.

In order to avoid any surprise, stop the virtual timer from
interrupting us when booted in HYP mode, as we'll use the physical
timer in this case.

Reported-by: Giridhar Maruthy <giridhar.m at samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/kernel/hyp-stub.S | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index dbe2110..4910232 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -155,6 +155,11 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
 	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
 	mov	r7, #0
 	mcrr	p15, 4, r7, r7, c14	@ CNTVOFF
+
+	@ Disable virtual timer in case it was counting
+	mrc	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
+	bic	r7, #1			@ Clear ENABLE
+	mcr	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
 1:
 #endif
 
-- 
1.8.1.1



From linux at arm.linux.org.uk  Fri May 24 07:59:17 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 12:59:17 +0100
Subject: [PATCH v2 4/4] ARM: cacheflush: don't bother rounding to
 nearest vma
In-Reply-To: <1369395087-30972-5-git-send-email-will.deacon@arm.com>
References: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
 <1369395087-30972-5-git-send-email-will.deacon@arm.com>
Message-ID: <20130524115917.GY18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 12:31:27PM +0100, Will Deacon wrote:
> do_cache_op finds the lowest VMA contained in the specified address
> range and rounds the range to cover only the mapped addresses.
> 
> Since commit 4542b6a0fa6b ("ARM: 7365/1: drop unused parameter from
> flush_cache_user_range") the VMA is not used for anything else in this
> code and seeing as the low-level cache flushing routines return -EFAULT
> if the address is not valid, there is no need for this range truncation.
> 
> This patch removes the VMA handling code from the cacheflushing syscall.

The only thing which access_ok() tells you is that the addresses are
_potentially_ valid user addresses.  That's not what the VMA check is
there for.

That check is there to make sure userspace doesn't do something idiotic,
and to keep the use of this API limited to specific actions such as self
modifying code, and not a general purpose cache flushing API covering
multiple VMAs.


From khali at linux-fr.org  Fri May 24 08:10:10 2013
From: khali at linux-fr.org (Jean Delvare)
Date: Fri, 24 May 2013 14:10:10 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <CAK7N6vqqG68c4vx1uBsNLF8zpSRQWwY5jERqjVYKE7NkEEzFSA@mail.gmail.com>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
 <CAK7N6vqqG68c4vx1uBsNLF8zpSRQWwY5jERqjVYKE7NkEEzFSA@mail.gmail.com>
Message-ID: <20130524141010.1b3590b4@endymion.delvare>

On Fri, 24 May 2013 16:29:36 +0530, anish singh wrote:
> On Fri, May 24, 2013 at 1:14 PM, Jean Delvare <khali at linux-fr.org> wrote:
> > On Fri, 24 May 2013 12:52:40 +0530, anish singh wrote:
> >> http://thread.gmane.org/gmane.linux.kernel/1410276
> >
> > This is for a specific case. The general case is handled by the
> > per-adapter mutex for years now. 2.6.32 should be just fine in this
> > respect.
>
> I may be mis-understanding here but when two client wants to
> communicate with same master and at the same
> time how does that happen?

In general clients (slaves in I2C terminology) do not initiate
transactions, it's the master's job.

> In the thread I mentioned client pulls the line low indicating that
> it wants to own the bus and waits for some time and then checks
> if the line is still low or not.If it is still low then it owns the bus
> and start transaction and if clients see otherwise it releases the
> bus and tries again after some time.How is that handled in the
> previous kernel?

That particular scenario is not handled by earlier kernels, but this is
a very special case. In most cases (including Myl?ne's as far as I can
see) it is not needed because there is a single master on the segment.
And even with multiple masters, I2C bus arbitration normally takes place
transparently. Only when the standard bus arbitration can't work for
some reason, the code you mentioned is needed.

-- 
Jean Delvare


From michal.simek at xilinx.com  Fri May 24 08:10:32 2013
From: michal.simek at xilinx.com (Michal Simek)
Date: Fri, 24 May 2013 14:10:32 +0200
Subject: [GIT PULL] arm-soc: Xilinx zynq core - smp for v3.10
In-Reply-To: <20130524112610.GX18614@n2100.arm.linux.org.uk>
References: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
 <20130524112610.GX18614@n2100.arm.linux.org.uk>
Message-ID: <744356bb-78fa-4592-97ef-0709fe65dbee@CH1EHSMHS025.ehs.local>

Hi Russell,

On 05/24/2013 01:26 PM, Russell King - ARM Linux wrote:
> On Thu, Apr 04, 2013 at 09:47:09AM +0200, Michal Simek wrote:
>> Hi Arnd and Olof,
>>
>> please pull the following smp support to your arm-soc tree.
>>
>> This branch is based on zynq/clksrc/cleanup parts because
>> there are some dependencies on moving timer to generic location.
>>
>> I could based it on standard Linux tagged version but you will get
>> several conflicts you will have to resolve.
>> If you are OK to resolving these problems, please let me know
>> I will create another branch with core-smp changes which are not based
>> on zynq/clksrc/cleanup branch.
> 
> You might want to resolve this new warning:
> 
> arch/arm/mach-zynq/hotplug.c:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march= switch
> 
> found by lastnights OMAP4430 randconfig build.

Do you have that randconfig file?
And can you please point me to the repo which is is used for this build?

Thanks,
Michal




From khali at linux-fr.org  Fri May 24 08:20:17 2013
From: khali at linux-fr.org (Jean Delvare)
Date: Fri, 24 May 2013 14:20:17 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <CA78C307B8F06747967D122FC656B15398644B@SERVEUR0.nvp.local>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
 <CA78C307B8F06747967D122FC656B15398644A@SERVEUR0.nvp.local>
 <20130524110706.6052493e@endymion.delvare>
 <CA78C307B8F06747967D122FC656B15398644B@SERVEUR0.nvp.local>
Message-ID: <20130524142017.52545a52@endymion.delvare>

On Fri, 24 May 2013 11:52:54 +0200, Mylene Josserand wrote:
> Right now, my company uses the "i2c_smbus_read/write_byte_data" 
> functions to talk to devices through an application. On the datasheet of 
> these devices, I search but did not seem to be SMBus compliant.
> As it was a software which was using these functions, we thought that a 
> driver (that I would write) should be better. And here I am ! I prefer 
> to understand well the mechanism before coding anything and it is 
> interesting !

If the application was using i2c_smbus_read/write_byte_data from
user-space, then a kernel driver would call the same functions. No
reason why this wouldn't work.

> (...)
> Thanks for the explanation.
> No problem, we have 2 devices used without drivers :
> - an odometer PIC18F24201 : In the datasheet, there is a SMBus select 
> bit but I don't know if it is SMBus compliant.

Couldn't find the datasheet for this one, unfortunately.

> - an audio codec tlv320aic3204 : There is a driver for this device but 
> for some reasons, we did not use it. Did not find a "SMBus compliant" in 
> its datasheet.

The tlv320aic32x4 driver uses i2c_master_send, which is a shortcut to
i2c_transfer. However it seems to only send 2 bytes on the bus at once,
the same could be achieved with i2c_smbus_write_byte_data if needed.

For completeness: a device might use transactions which are compliant
with SMBus without being formally "SMBus-compliant", because SMBus has
more constraints than just transaction types (I kept things simple
originally to not confuse you.) This may explain why it isn't mentioned
in the datasheet. Or just because the manufacturer did not care because
they target fully I2C-capable systems anyway.

What you have to look at is the transaction types. They are usually
described in the datasheet. Then compare with either the SMBus
specification or
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/i2c/smbus-protocol
and if they match then you can use the i2c_smbus_*() calls.

> (...)
> Thanks a lot for your help !

You're welcome.

-- 
Jean Delvare


From magnus.damm at gmail.com  Fri May 24 08:24:26 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Fri, 24 May 2013 21:24:26 +0900
Subject: [PATCH v4 15/21] ARM: shmobile: armadillo-reference: Move st1232
 reset GPIO to DT
In-Reply-To: <CACRpkdYUQjtmzFzQBES-bcjjT5iTTXifa2BQSusBzMdTCRtyiA@mail.gmail.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369138482-5871-16-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <CACRpkdYUQjtmzFzQBES-bcjjT5iTTXifa2BQSusBzMdTCRtyiA@mail.gmail.com>
Message-ID: <CANqRtoTVjBcsKVP=2jJ7ThC0gXuF-Xd-iByo7db53YhK1x+-wA@mail.gmail.com>

Hi Linus,

On Fri, May 24, 2013 at 5:59 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
> <laurent.pinchart+renesas at ideasonboard.com> wrote:
>
>> Reference the st1232 reset GPIO from the device tree and remove it from
>> board code.
>>
>> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>
>> +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
>> @@ -43,6 +43,7 @@
>>                 interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
>>                 pinctrl-0 = <&st1232_pins>;
>>                 pinctrl-names = "default";
>> +               gpios = <&pfc 166 1>;
>
> Just as a random example this becomes:
>
> gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
>
> Which is WAAAY more readable.

Yes, agreed, even grumpy me starts thinking this looks good. =)

>> +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
>> @@ -158,7 +158,6 @@ clock_error:
>>   */
>>  static void __init eva_init(void)
>>  {
>> -
>>         r8a7740_clock_init(MD_CK0 | MD_CK2);
>>         eva_clock_init();
>>
>> @@ -171,12 +170,6 @@ static void __init eva_init(void)
>>
>>         r8a7740_add_standard_devices_dt();
>>
>> -       /*
>> -        * Touchscreen
>> -        * TODO: Move reset GPIO over to .dts when we can reference it
>> -        */
>> -       gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
>> -
>
> Not really my business but I guess the driver is already augmented to pick its
> GPIO from the device tree in this case? And are you willingly breaking
> non-DT boots or something?

Regarding dependency handing of driver and board code, I believe
Laurent has us covered.

As for breaking non-DT boot, under mach-shmobile the code for DT
"-reference" board support is DT only so judging by the file name this
kind of change should be fine.

Thanks,

/ magnus


From linux at arm.linux.org.uk  Fri May 24 08:31:05 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 13:31:05 +0100
Subject: [GIT PULL] arm-soc: Xilinx zynq core - smp for v3.10
In-Reply-To: <744356bb-78fa-4592-97ef-0709fe65dbee@CH1EHSMHS025.ehs.local>
References: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
 <20130524112610.GX18614@n2100.arm.linux.org.uk>
 <744356bb-78fa-4592-97ef-0709fe65dbee@CH1EHSMHS025.ehs.local>
Message-ID: <20130524123105.GZ18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 02:10:32PM +0200, Michal Simek wrote:
> Hi Russell,
> 
> On 05/24/2013 01:26 PM, Russell King - ARM Linux wrote:
> > You might want to resolve this new warning:
> > 
> > arch/arm/mach-zynq/hotplug.c:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march= switch
> > 
> > found by lastnights OMAP4430 randconfig build.
> 
> Do you have that randconfig file?
> And can you please point me to the repo which is is used for this build?

Everything which is public is at:

http://www.home.arm.linux.org.uk/developer/build/

I don't make the build tree available because it changes too often and
I don't want _anyone_ to make the mistake of assuming that anything
which is in there is stable.  However, the above URL tells you how it's
generated.  As it is mainline+arm-soc+my tree (including some bits I'm
not publishing), it's pretty much publically available anyway.


From linux at arm.linux.org.uk  Fri May 24 08:31:32 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 13:31:32 +0100
Subject: [GIT PULL] arm-soc: Xilinx zynq core - smp for v3.10
In-Reply-To: <20130524123105.GZ18614@n2100.arm.linux.org.uk>
References: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
 <20130524112610.GX18614@n2100.arm.linux.org.uk>
 <744356bb-78fa-4592-97ef-0709fe65dbee@CH1EHSMHS025.ehs.local>
 <20130524123105.GZ18614@n2100.arm.linux.org.uk>
Message-ID: <20130524123132.GA13111@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 01:31:05PM +0100, Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 02:10:32PM +0200, Michal Simek wrote:
> > Hi Russell,
> > 
> > On 05/24/2013 01:26 PM, Russell King - ARM Linux wrote:
> > > You might want to resolve this new warning:
> > > 
> > > arch/arm/mach-zynq/hotplug.c:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march= switch
> > > 
> > > found by lastnights OMAP4430 randconfig build.
> > 
> > Do you have that randconfig file?
> > And can you please point me to the repo which is is used for this build?
> 
> Everything which is public is at:
> 
> http://www.home.arm.linux.org.uk/developer/build/

Err, drop the .home bit out of that.


From marcio at netopen.com.br  Fri May 24 08:35:46 2013
From: marcio at netopen.com.br (Marcio Campos de Lima)
Date: Fri, 24 May 2013 09:35:46 -0300
Subject: FW: Linux 2.6.39.4 in a AT91SAM9M10G45-EK 10 Mbytes dma buffer
 allocatiion
In-Reply-To: <CDC4E028.D8BC%marcio@netopen.com.br>
Message-ID: <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>




	
Hi
I am running Linux 2.6.39.4 in a AT91SAM9M10G45-EK platfarm. I need to
allocate 10 Mbytes dma buffer to capture an image from a CMOS sensor. The
board has 128Mbytes of total memory and 110 Mbytes of free memory. Can
anybody help me?
Thanks
MArcio

at mm/page_alloc.c:2033 __alloc_pages_nodemask+0x140/0x5f8)
ht????? = 19Modules linked
in:44;????????????????????????????????????????????? ?
????????????????????????????????????????????????????????????????????????????
?? ?
fmt.fmt.pix.[] (unwind_backtrace+0x0/0xe4) from [] (warn_sl)
pixelformat [] (warn_slowpath_common+0x4c/0x64) from [] (wa)
=30314742;??????????????????????????????????????????????????????????????????
?? ?
f[] (warn_slowpath_null+0x18/0x1c) from [] (__alloc_pages_n)
mt.fmt.pix.fiel[] (__alloc_pages_nodemask+0x140/0x5f8) from [d?????? =
c72b2[] (__dma_alloc+0x94/0x2d8) from [] (dma_all)
cc8?????????????????????????????????????????????????????????????????????????
?? ?
MARCIO[] (dma_alloc_coherent+0x54/0x60) from [] (vb2_dma_co)
: init_mmap: i[] (vb2_dma_contig_alloc+0x38/0xb4) from [] ()
nit?????????????????????????????????????????????????????????????????????????
?? ?
[] (vb2_reqbufs+0x3b4/0x750) from [] (soc_camera_reqbufs+0x)
[] (soc_camera_reqbufs+0xbc/0x134) from [] (__video_do_ioct)
[] (__video_do_ioctl+0x1de0/0x4a24) from [] (video_usercopy)
[] (video_usercopy+0x358/0x48c) from [] (v4l2_ioctl+0x68/0x)
[] (v4l2_ioctl+0x68/0x114) from [] (vfs_ioctl+0x20/0x3c)?? ?
[] (vfs_ioctl+0x20/0x3c) from [] (do_vfs_ioctl+0x520/0x578)?
[] (do_vfs_ioctl+0x520/0x578) from [] (sys_ioctl+0x34/0x54)?
[] (sys_ioctl+0x34/0x54) from [] (ret_fast_syscall+0x0/0x2c)
---[ end trace acfd933d374f6f12
]---?????????????????????????????????????????? ?
atmel_isi atmel_isi.0: dma_alloc_coherent of size 10077696
failed????????????? ?
MARCIO: __vb2_queue_alloc
ret=-12????????????????????????????????????????????? ?
MARCIO: __vb2_queue_alloc
q->num_buffers=0???????????????????????????????????? ?
MARCIO: vb2_reqbufs req->count=2 ret=0
num_buffers=1?????????????????????????? ?
MARCIO: vb2_reqbufs req->count=2 num_buffers=1
ret=0?????????????????????????? ?
MARCIO:vb2_reqbufs soc_camera_reqbufs ret=-12 icd->vb2_vidq=1?
p=1???????????? ?
MARCIO:soc_camera_reqbufs
ret=-12????????????????????????????????????????????? ?
VIDIOC_REQBUFS error 12, Out of memory
?
?
?

From g.liakhovetski at gmx.de  Fri May 24 08:35:42 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 24 May 2013 14:35:42 +0200 (CEST)
Subject: LVDS (LDB) driver for i.MX53 IPU
In-Reply-To: <20130310223241.GQ1906@pengutronix.de>
References: <5134DF0E.7010402@parkeon.com>
 <20130310223241.GQ1906@pengutronix.de>
Message-ID: <Pine.LNX.4.64.1305241431460.2226@axis700.grange>

Hi Sascha

On Sun, 10 Mar 2013, Sascha Hauer wrote:

> Hi Martin,
> 
> On Mon, Mar 04, 2013 at 06:51:10PM +0100, Martin Fuzzey wrote:
> > Hi Sascha,
> > 
> > I need to add LVDS support to your staging imx/drm driver.
> > 
> > First of all are there any patches floating around to do that? (a
> > search of the mailing list didn't turn up any).
> > 
> > From a hardware point of view it looks quite simple (just one
> > register to configure) but unfortunately that register is in the
> > IOMUXC region.
> > 
> > That means that if I write a new platform driver similar to
> > drivers/staging/imx-drm/parallel-display.c (with a new DT node
> > pointing to the reg) the request_resource() will fail since it will
> > already be claimed by the iomuxc driver.
> > 
> > The only solutions I can think of are:
> > 1) Add exported function to the iomuxc driver to get the register
> > or
> > 2) Directly ioremap() the address
> > 
> > Both of these sound horrible.
> > 
> > Do you have any suggestions?
> > 
> > I guess the generic question I'm asking is how to handle the case
> > where unrelated drivers require access to the same memory regions?
> 
> We have a driver for the ldb. Indeed the driver itself is trivial, but
> the integration is tricky. For accessing the register the syscon binding
> can be used. The clock is also a problem, also the mux to the IPU(s)
> 
> I'll talk with Philipp tomorrow and I think we can send you the current
> state then.

How's it looking in the meantime? Any plans to mainline it? Or would you 
be prepared to publish what you've got to try and see whether others can 
help you with this?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From monstr at monstr.eu  Fri May 24 08:37:24 2013
From: monstr at monstr.eu (Michal Simek)
Date: Fri, 24 May 2013 14:37:24 +0200
Subject: [GIT PULL] arm-soc: Xilinx zynq core - smp for v3.10
In-Reply-To: <20130524123132.GA13111@n2100.arm.linux.org.uk>
References: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
 <20130524112610.GX18614@n2100.arm.linux.org.uk>
 <744356bb-78fa-4592-97ef-0709fe65dbee@CH1EHSMHS025.ehs.local>
 <20130524123105.GZ18614@n2100.arm.linux.org.uk>
 <20130524123132.GA13111@n2100.arm.linux.org.uk>
Message-ID: <519F5F04.3030400@monstr.eu>

On 05/24/2013 02:31 PM, Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 01:31:05PM +0100, Russell King - ARM Linux wrote:
>> On Fri, May 24, 2013 at 02:10:32PM +0200, Michal Simek wrote:
>>> Hi Russell,
>>>
>>> On 05/24/2013 01:26 PM, Russell King - ARM Linux wrote:
>>>> You might want to resolve this new warning:
>>>>
>>>> arch/arm/mach-zynq/hotplug.c:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march= switch
>>>>
>>>> found by lastnights OMAP4430 randconfig build.
>>>
>>> Do you have that randconfig file?
>>> And can you please point me to the repo which is is used for this build?
>>
>> Everything which is public is at:
>>
>> http://www.home.arm.linux.org.uk/developer/build/
> 
> Err, drop the .home bit out of that.

Thanks that's everything what I need.
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From admin at triptheory.com  Fri May 24 08:30:12 2013
From: admin at triptheory.com (irianpxv86)
Date: Fri, 24 May 2013 15:30:12 +0300
Subject: =?iso-8859-5?B?tN7R4N7T3iDS4NXc1d3YIOHj4t7a?=
Message-ID: <2A7D77171539450F8937AEE77089EF24@yaoqosf>

??????????? ?????????????? ???? ????? ????? ???????? http://goo.gl/XlnaR?/iAnwuJwH


From dirk.behme at de.bosch.com  Fri May 24 08:44:58 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 24 May 2013 14:44:58 +0200
Subject: clock framework: Don't disable a clock already enabled by boot loader?
Message-ID: <519F60CA.6090302@de.bosch.com>

Hi,

we register a clock using clk_register_clkdev() etc already enabled by a 
boot loader. We are doing only the clk_register_clkdev(), but no 
clock_enable() etc on this clock.

With this, enable_count for this clock is zero, while in fact it's 
already on. I.e. the kernel doesn't know that it is on.

This results in

late_initcall(clk_disable_unused())

disabling this clock because the kernel thinks it's unused.

Is this the intended behavior? Is there a way to let the kernel know 
"the clock is enabled already, set enable_count != 0"? Or is the only 
way to do this correctly calling clock_enable() on an already enabled clock?

Many thanks and best regards

Dirk


From emilio at elopez.com.ar  Fri May 24 08:46:32 2013
From: emilio at elopez.com.ar (=?ISO-8859-1?Q?Emilio_L=F3pez?=)
Date: Fri, 24 May 2013 09:46:32 -0300
Subject: [PATCHv3 1/6] net: Add EMAC ethernet driver found on Allwinner
 A10 SoC's
In-Reply-To: <1369387394-9453-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369387394-9453-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <519F6128.9060608@elopez.com.ar>

El 24/05/13 06:23, Maxime Ripard escribi?:
> From: Stefan Roese <sr at denx.de>
> 
> The Allwinner A10 has an ethernet controller that seem to be developped
> internally by them.
> 
> The exact feature set of this controller is unknown, since there is no
> public documentation for this IP, and this driver is mostly the one
> published by Allwinner that has been heavily cleaned up.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---

(snip)

> +
> +config SUN4I_EMAC
> +        tristate "Allwinner A10 EMAC support"
> +	depends on ARCH_SUNXI
> +	depends on OF
> +	select CRC32
> +	select NET_CORE
> +	select MII
> +	select REGULATOR_FIXED_VOLTAGE
> +        ---help---
> +          Support for Allwinner A10 EMAC ethernet driver.
> +
> +          To compile this driver as a module, choose M here.  The module
> +          will be called sun4i-emac.
> +

You also need to select REGULATOR when you select REGULATOR_FIXED_VOLTAGE

I have attached a fixup patch you can use with git autosquash

Cheers,

Emilio
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From emilio at elopez.com.ar  Fri May 24 08:53:07 2013
From: emilio at elopez.com.ar (=?ISO-8859-1?Q?Emilio_L=F3pez?=)
Date: Fri, 24 May 2013 09:53:07 -0300
Subject: [PATCHv3 5/6] ARM: cubieboard: Enable ethernet (EMAC) support
 in dts
In-Reply-To: <1369387394-9453-6-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369387394-9453-6-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <519F62B3.8090302@elopez.com.ar>

Hi,

El 24/05/13 06:23, Maxime Ripard escribi?:
> From: Stefan Roese <sr at denx.de>
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> ---
>  arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> index b70fe0d..32d9b18 100644
> --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> @@ -27,6 +27,21 @@
>  	};
>  
>  	soc at 01c20000 {
> +		emac: ethernet at 01c0b000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&emac_pins_a>;
> +			phy = <&phy0>;
> +			status = "okay";
> +		};
> +
> +		mdio at 01c0b080 {
> +			status = "okay";
> +
> +			phy0: ethernet-phy at 0 {
> +				reg = <0>;
> +			};

During my testing I found out that I needed to use 1 as reg for the
driver to work. You can find a fixup patch enclosed that changes this;
it's possible that some extra changes may also be needed (s/phy0/phy1/
on the node?)

Cheers,

Emilio
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From lee.jones at linaro.org  Fri May 24 08:53:14 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 May 2013 13:53:14 +0100
Subject: [PATCH] ARM: ux500: enable the crypto and hash on all dbx500
In-Reply-To: <CACRpkdb1CZKoaG6nNF-yBC3Eovoe3_0BHa6uO-OQkePDcrkamg@mail.gmail.com>
References: <1369378122-25897-1-git-send-email-linus.walleij@stericsson.com>
 <20130524082758.GP22683@gmail.com>
 <CACRpkdb1CZKoaG6nNF-yBC3Eovoe3_0BHa6uO-OQkePDcrkamg@mail.gmail.com>
Message-ID: <20130524125314.GZ22683@gmail.com>

On Fri, 24 May 2013, Linus Walleij wrote:

> On Fri, May 24, 2013 at 10:27 AM, Lee Jones <lee.jones at linaro.org> wrote:
> > On Fri, 24 May 2013, Linus Walleij wrote:
> >> From: Linus Walleij <linus.walleij at linaro.org>
> >>
> >> Commits:
> >> "ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
> >> "ARM: ux500: Add Device Tree nodes for the ux500 Hash device"
> >>
> >> Added the crypto and hash devices conditionally, i.e. so as to
> >> be turned on per-board by setting an "status" property on the
> >> device from "disabled" to "okay" on each device.
> >>
> >> This is wrong since this is an SoC feature, it is not board
> >> dependent. It is the same ASIC under all circumstances and
> >> functionality does not vary with board family.
> >>
> >> This moves the enablement into the SoC file.
> >>
> >> Cc: Lee Jones <lee.jones at linaro.org>
> >> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> >> ---
> >>  arch/arm/boot/dts/dbx5x0.dtsi  | 4 ----
> >>  arch/arm/boot/dts/snowball.dts | 8 --------
> >>  2 files changed, 12 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
> >> index f051963..cd5cd09 100644
> >> --- a/arch/arm/boot/dts/dbx5x0.dtsi
> >> +++ b/arch/arm/boot/dts/dbx5x0.dtsi
> >> @@ -760,17 +760,13 @@
> >>                       compatible = "stericsson,ux500-cryp";
> >>                       reg = <0xa03cb000 0x1000>;
> >>                       interrupts = <0 15 0x4>;
> >> -
> >
> > Why do you insist on removing all line spacings from the DTS file?
> >
> > I saw you removing them in between nodes too.
> 
> I was hit by a linespace when I was a child, since then I take
> every opportunity for revenge.

:)

> If I keep the spacing, can I have your ACK?

You can.

For reference, I like a space separating all nodes too. :)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lorenzo.pieralisi at arm.com  Fri May 24 08:53:05 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 24 May 2013 13:53:05 +0100
Subject: [RFC PATCH 2/3] drivers: mfd: vexpress: add timeout API to vexpress
 config interface
In-Reply-To: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1369399986-15649-3-git-send-email-lorenzo.pieralisi@arm.com>

In case some transactions to the Serial Power Controller (SPC) are lost owing
to multiple operations handled at once by the M3 controller the OS needs to
rely on a configuration API that can time out so that failures do not result
in an unusable system.

This patch adds a timeout API to the vexpress config programming interface,
and refactors the existing read/write functions so that they can be reused
seamlessly on top of the newly defined API.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Achin Gupta <achin.gupta at arm.com>
Cc: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
Cc: Pawel Moll <pawel.moll at arm.com>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Jon Medhurst <tixy at linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
 drivers/mfd/vexpress-config.c | 26 +++++++---
 include/linux/vexpress.h      | 23 ++++++--
 2 files changed, 37 insertions(+), 12 deletions(-)

diff --git a/drivers/mfd/vexpress-config.c b/drivers/mfd/vexpress-config.c
index 1af2b0e..6f4aa5a 100644
--- a/drivers/mfd/vexpress-config.c
+++ b/drivers/mfd/vexpress-config.c
@@ -266,8 +266,18 @@ int vexpress_config_wait(struct vexpress_config_trans *trans)
 }
 EXPORT_SYMBOL(vexpress_config_wait);
 
-int vexpress_config_read(struct vexpress_config_func *func, int offset,
-		u32 *data)
+int vexpress_config_wait_timeout(struct vexpress_config_trans *trans,
+			long jiffies)
+{
+	int ret;
+	ret = wait_for_completion_timeout(&trans->completion, jiffies);
+
+	return ret ? trans->status : -ETIMEDOUT;
+}
+EXPORT_SYMBOL(vexpress_config_wait_timeout);
+
+int vexpress_config_read_timeout(struct vexpress_config_func *func, int offset,
+		u32 *data, long jiffies)
 {
 	struct vexpress_config_trans trans = {
 		.func = func,
@@ -279,14 +289,14 @@ int vexpress_config_read(struct vexpress_config_func *func, int offset,
 	int status = vexpress_config_schedule(&trans);
 
 	if (status == VEXPRESS_CONFIG_STATUS_WAIT)
-		status = vexpress_config_wait(&trans);
+		status = vexpress_config_wait_timeout(&trans, jiffies);
 
 	return status;
 }
-EXPORT_SYMBOL(vexpress_config_read);
+EXPORT_SYMBOL(vexpress_config_read_timeout);
 
-int vexpress_config_write(struct vexpress_config_func *func, int offset,
-		u32 data)
+int vexpress_config_write_timeout(struct vexpress_config_func *func,
+				  int offset, u32 data, long jiffies)
 {
 	struct vexpress_config_trans trans = {
 		.func = func,
@@ -298,8 +308,8 @@ int vexpress_config_write(struct vexpress_config_func *func, int offset,
 	int status = vexpress_config_schedule(&trans);
 
 	if (status == VEXPRESS_CONFIG_STATUS_WAIT)
-		status = vexpress_config_wait(&trans);
+		status = vexpress_config_wait_timeout(&trans, jiffies);
 
 	return status;
 }
-EXPORT_SYMBOL(vexpress_config_write);
+EXPORT_SYMBOL(vexpress_config_write_timeout);
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index 50368e0..e5015d8 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,6 +15,7 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
+#include <linux/sched.h>
 
 #define VEXPRESS_SITE_MB		0
 #define VEXPRESS_SITE_DB1		1
@@ -102,10 +103,24 @@ struct vexpress_config_func *__vexpress_config_func_get(
 void vexpress_config_func_put(struct vexpress_config_func *func);
 
 /* Both may sleep! */
-int vexpress_config_read(struct vexpress_config_func *func, int offset,
-		u32 *data);
-int vexpress_config_write(struct vexpress_config_func *func, int offset,
-		u32 data);
+int vexpress_config_read_timeout(struct vexpress_config_func *func, int offset,
+		u32 *data, long jiffies);
+int vexpress_config_write_timeout(struct vexpress_config_func *func,
+		int offset, u32 data, long jiffies);
+
+static inline int vexpress_config_read(struct vexpress_config_func *func,
+				 int offset, u32 *data)
+{
+	return vexpress_config_read_timeout(func, offset, data,
+					     MAX_SCHEDULE_TIMEOUT);
+}
+
+static inline int vexpress_config_write(struct vexpress_config_func *func,
+				 int offset, u32 data)
+{
+	return vexpress_config_write_timeout(func, offset, data,
+					     MAX_SCHEDULE_TIMEOUT);
+}
 
 /* Platform control */
 
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 24 08:53:03 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 24 May 2013 13:53:03 +0100
Subject: [RFC PATCH 0/3] drivers: mfd: Versatile Express SPC support
Message-ID: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>

This patch series introduces support for the Versatile Express Serial
Power Controller (SPC) present in ARM Versatile Express TC2 core tiles.
SPC driver is a fundamental component of TC2 power management and allows
to carry out C-state management and DVFS for A15 and A7 clusters.

First two patches provide changes required by SPC to comply with the
Versatile Express config API, third patch is the SPC driver implementation.

Code extensively exercised through CPUidle and CPUfreq power states and
operating point transitions.

Lorenzo Pieralisi (2):
  drivers: mfd: vexpress: add timeout API to vexpress config interface
  drivers: mfd: vexpress: add Serial Power Controller (SPC) support

Pawel Moll (1):
  drivers: mfd: refactor the vexpress config bridge API

 Documentation/devicetree/bindings/mfd/vexpress-spc.txt |  35 +
 drivers/mfd/Kconfig                                    |   7 +
 drivers/mfd/Makefile                                   |   1 +
 drivers/mfd/vexpress-config.c                          |  87 +-
 drivers/mfd/vexpress-spc.c                             | 626 ++++++++++
 drivers/mfd/vexpress-sysreg.c                          |   2 +-
 include/linux/vexpress.h                               |  82 +-
 7 files changed, 800 insertions(+), 40 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/vexpress-spc.txt
 create mode 100644 drivers/mfd/vexpress-spc.c

-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 24 08:53:04 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 24 May 2013 13:53:04 +0100
Subject: [RFC PATCH 1/3] drivers: mfd: refactor the vexpress config bridge API
In-Reply-To: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1369399986-15649-2-git-send-email-lorenzo.pieralisi@arm.com>

From: Pawel Moll <pawel.moll at arm.com>

The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates the bridge functions
requires an additional parameter allowing to request component specific
functions that need not be initialized through device tree bindings but
just using simple look-up and statically defined constants.

This patch introduces the necessary changes to the vexpress config layer
to cater for the new vexpress bridge interface requirements.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Achin Gupta <achin.gupta at arm.com>
Cc: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
Cc: Pawel Moll <pawel.moll at arm.com>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Jon Medhurst <tixy at linaro.org>
Signed-off-by: Pawel Moll <pawel.moll at arm.com>
---
 drivers/mfd/vexpress-config.c | 61 ++++++----
 drivers/mfd/vexpress-sysreg.c |  2 +-
 include/linux/vexpress.h      | 16 ++-
 3 files changed, 51 insertions(+), 28 deletions(-)

diff --git a/drivers/mfd/vexpress-config.c b/drivers/mfd/vexpress-config.c
index 84ce6b9..1af2b0e 100644
--- a/drivers/mfd/vexpress-config.c
+++ b/drivers/mfd/vexpress-config.c
@@ -86,29 +86,13 @@ void vexpress_config_bridge_unregister(struct vexpress_config_bridge *bridge)
 }
 EXPORT_SYMBOL(vexpress_config_bridge_unregister);
 
-
-struct vexpress_config_func {
-	struct vexpress_config_bridge *bridge;
-	void *func;
-};
-
-struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
-		struct device_node *node)
+static struct vexpress_config_bridge *
+		vexpress_config_bridge_find(struct device_node *node)
 {
-	struct device_node *bridge_node;
-	struct vexpress_config_func *func;
 	int i;
+	struct vexpress_config_bridge *res = NULL;
+	struct device_node *bridge_node = of_node_get(node);
 
-	if (WARN_ON(dev && node && dev->of_node != node))
-		return NULL;
-	if (dev && !node)
-		node = dev->of_node;
-
-	func = kzalloc(sizeof(*func), GFP_KERNEL);
-	if (!func)
-		return NULL;
-
-	bridge_node = of_node_get(node);
 	while (bridge_node) {
 		const __be32 *prop = of_get_property(bridge_node,
 				"arm,vexpress,config-bridge", NULL);
@@ -129,13 +113,46 @@ struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
 
 		if (test_bit(i, vexpress_config_bridges_map) &&
 				bridge->node == bridge_node) {
-			func->bridge = bridge;
-			func->func = bridge->info->func_get(dev, node);
+			res = bridge;
 			break;
 		}
 	}
 	mutex_unlock(&vexpress_config_bridges_mutex);
 
+	return res;
+}
+
+
+struct vexpress_config_func {
+	struct vexpress_config_bridge *bridge;
+	void *func;
+};
+
+struct vexpress_config_func *__vexpress_config_func_get(
+		struct vexpress_config_bridge *bridge,
+		struct device *dev,
+		struct device_node *node,
+		const char *id)
+{
+	struct vexpress_config_func *func;
+
+	if (WARN_ON(dev && node && dev->of_node != node))
+		return NULL;
+	if (dev && !node)
+		node = dev->of_node;
+
+	if (!bridge)
+		bridge = vexpress_config_bridge_find(node);
+	if (!bridge)
+		return NULL;
+
+	func = kzalloc(sizeof(*func), GFP_KERNEL);
+	if (!func)
+		return NULL;
+
+	func->bridge = bridge;
+	func->func = bridge->info->func_get(dev, node, id);
+
 	if (!func->func) {
 		of_node_put(node);
 		kfree(func);
diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c
index 96a020b..d2599aa 100644
--- a/drivers/mfd/vexpress-sysreg.c
+++ b/drivers/mfd/vexpress-sysreg.c
@@ -165,7 +165,7 @@ static u32 *vexpress_sysreg_config_data;
 static int vexpress_sysreg_config_tries;
 
 static void *vexpress_sysreg_config_func_get(struct device *dev,
-		struct device_node *node)
+		struct device_node *node, const char *id)
 {
 	struct vexpress_sysreg_config_func *config_func;
 	u32 site;
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index 6e7980d..50368e0 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -68,7 +68,8 @@
  */
 struct vexpress_config_bridge_info {
 	const char *name;
-	void *(*func_get)(struct device *dev, struct device_node *node);
+	void *(*func_get)(struct device *dev, struct device_node *node,
+			  const char *id);
 	void (*func_put)(void *func);
 	int (*func_exec)(void *func, int offset, bool write, u32 *data);
 };
@@ -87,12 +88,17 @@ void vexpress_config_complete(struct vexpress_config_bridge *bridge,
 
 struct vexpress_config_func;
 
-struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
-		struct device_node *node);
+struct vexpress_config_func *__vexpress_config_func_get(
+		struct vexpress_config_bridge *bridge,
+		struct device *dev,
+		struct device_node *node,
+		const char *id);
+#define vexpress_config_func_get(bridge, id) \
+		__vexpress_config_func_get(bridge, NULL, NULL, id)
 #define vexpress_config_func_get_by_dev(dev) \
-		__vexpress_config_func_get(dev, NULL)
+		__vexpress_config_func_get(NULL, dev, NULL, NULL)
 #define vexpress_config_func_get_by_node(node) \
-		__vexpress_config_func_get(NULL, node)
+		__vexpress_config_func_get(NULL, NULL, node, NULL)
 void vexpress_config_func_put(struct vexpress_config_func *func);
 
 /* Both may sleep! */
-- 
1.8.2.2




From lorenzo.pieralisi at arm.com  Fri May 24 08:53:06 2013
From: lorenzo.pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 24 May 2013 13:53:06 +0100
Subject: [RFC PATCH 3/3] drivers: mfd: vexpress: add Serial Power Controller
 (SPC) support
In-Reply-To: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>
References: <1369399986-15649-1-git-send-email-lorenzo.pieralisi@arm.com>
Message-ID: <1369399986-15649-4-git-send-email-lorenzo.pieralisi@arm.com>

The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC), contains several memory mapped registers to control among other things
low-power states, operating points and reset control.

This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.

The driver also provides a bridge interface through the vexpress config
infrastructure. Operations allowing to read/write operating points are
made to go via the same interface as configuration transactions so that
all requests to M3 are serialized.

Device tree bindings documentation for the SPC component are provided with
the patchset.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Pawel Moll <pawel.moll at arm.com>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Jon Medhurst <tixy at linaro.org>
Signed-off-by: Achin Gupta <achin.gupta at arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
---
 Documentation/devicetree/bindings/mfd/vexpress-spc.txt |  35 +
 drivers/mfd/Kconfig                                    |   7 +
 drivers/mfd/Makefile                                   |   1 +
 drivers/mfd/vexpress-spc.c                             | 626 ++++++++++
 include/linux/vexpress.h                               |  43 +
 5 files changed, 712 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/vexpress-spc.txt b/Documentation/devicetree/bindings/mfd/vexpress-spc.txt
new file mode 100644
index 0000000..1d71dc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/vexpress-spc.txt
@@ -0,0 +1,35 @@
+* ARM Versatile Express Serial Power Controller device tree bindings
+
+Latest ARM development boards implement a power management interface (serial
+power controller - SPC) that is capable of managing power/voltage and
+operating point transitions, through memory mapped registers interface.
+
+On testchips like TC2 it also provides a configuration interface that can
+be used to read/write values which cannot be read/written through simple
+memory mapped reads/writes.
+
+- spc node
+
+	- compatible:
+		Usage: required
+		Value type: <stringlist>
+		Definition: must be
+			    "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc"
+	- reg:
+		Usage: required
+		Value type: <prop-encode-array>
+		Definition: A standard property that specifies the base address
+			    and the size of the SPC address space
+	- interrupts:
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition:  SPC interrupt configuration. A standard property
+			     that follows ePAPR interrupts specifications
+
+Example:
+
+spc: spc at 7fff0000 {
+	compatible = "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc";
+	reg = <0 0x7FFF0000 0 0x1000>;
+	interrupts = <0 95 4>;
+};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d9aed15..b5259af 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1147,3 +1147,10 @@ config VEXPRESS_CONFIG
 	help
 	  Platform configuration infrastructure for the ARM Ltd.
 	  Versatile Express.
+
+config VEXPRESS_SPC
+	bool "Versatile Express SPC driver support"
+	depends on ARM
+	depends on VEXPRESS_CONFIG
+	help
+	  Serial Power Controller driver for ARM Ltd. test chips.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 718e94a..3a01203 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -153,5 +153,6 @@ obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
 obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
 obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o vexpress-sysreg.o
+obj-$(CONFIG_VEXPRESS_SPC)	+= vexpress-spc.o
 obj-$(CONFIG_MFD_RETU)		+= retu-mfd.o
 obj-$(CONFIG_MFD_AS3711)	+= as3711.o
diff --git a/drivers/mfd/vexpress-spc.c b/drivers/mfd/vexpress-spc.c
new file mode 100644
index 0000000..f78257a
--- /dev/null
+++ b/drivers/mfd/vexpress-spc.c
@@ -0,0 +1,626 @@
+/*
+ * Versatile Express Serial Power Controller (SPC) support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * Author(s): Sudeep KarkadaNagesha <sudeep.karkadanagesha at arm.com>
+ *            Achin Gupta           <achin.gupta at arm.com>
+ *            Lorenzo Pieralisi     <lorenzo.pieralisi at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/vexpress.h>
+
+#include <asm/cacheflush.h>
+
+#define SCC_CFGREG19		0x120
+#define SCC_CFGREG20		0x124
+#define A15_CONF		0x400
+#define A7_CONF			0x500
+#define SYS_INFO		0x700
+#define PERF_LVL_A15		0xB00
+#define PERF_REQ_A15		0xB04
+#define PERF_LVL_A7		0xB08
+#define PERF_REQ_A7		0xB0c
+#define SYS_CFGCTRL		0xB10
+#define SYS_CFGCTRL_REQ		0xB14
+#define PWC_STATUS		0xB18
+#define PWC_FLAG		0xB1c
+#define WAKE_INT_MASK		0xB24
+#define WAKE_INT_RAW		0xB28
+#define WAKE_INT_STAT		0xB2c
+#define A15_PWRDN_EN		0xB30
+#define A7_PWRDN_EN		0xB34
+#define A7_PWRDNACK		0xB54
+#define A15_BX_ADDR0		0xB68
+#define SYS_CFG_WDATA		0xB70
+#define SYS_CFG_RDATA		0xB74
+#define A7_BX_ADDR0		0xB78
+
+#define GBL_WAKEUP_INT_MSK	(0x3 << 10)
+
+#define CLKF_SHIFT		16
+#define CLKF_MASK		0x1FFF
+#define CLKR_SHIFT		0
+#define CLKR_MASK		0x3F
+#define CLKOD_SHIFT		8
+#define CLKOD_MASK		0xF
+
+#define OPP_FUNCTION		6
+#define OPP_BASE_DEVICE		0x300
+#define OPP_A15_OFFSET		0x4
+#define OPP_A7_OFFSET		0xc
+
+#define SYS_CFGCTRL_START	(1 << 31)
+#define SYS_CFGCTRL_WRITE	(1 << 30)
+#define SYS_CFGCTRL_FUNC(n)	(((n) & 0x3f) << 20)
+#define SYS_CFGCTRL_DEVICE(n)	(((n) & 0xfff) << 0)
+/*
+ * Even though the SPC takes max 3-5 ms to complete any OPP/SYS_CFGCTRL
+ * operation, the operation could start just before jiffie is about
+ * to be incremented. So setting timeout value of 20ms = 2jiffies at 100Hz
+ */
+#define TIME_OUT_US	20000
+
+#define MAX_OPPS	8
+#define MAX_CLUSTERS	2
+
+enum {
+	A15_OPP_STATUS		= 0,
+	A7_OPP_STATUS		= 1,
+	SYS_CFGCTRL_STATUS	= 2
+};
+
+#define STAT_COMPLETE(type)	((1 << 0) << (type << 2))
+#define STAT_ERR(type)		((1 << 1) << (type << 2))
+#define RESPONSE_MASK(type)	(STAT_COMPLETE(type) | STAT_ERR(type))
+
+struct vexpress_spc_drvdata {
+	void __iomem *baseaddr;
+	u32 a15_clusid;
+	int irq;
+	u32 cur_req_type;
+	u32 freqs[MAX_CLUSTERS][MAX_OPPS];
+	int freqs_cnt[MAX_CLUSTERS];
+};
+
+enum spc_func_type {
+	CONFIG_FUNC = 0,
+	PERF_FUNC   = 1,
+};
+
+struct vexpress_spc_func {
+	enum spc_func_type type;
+	u32 function;
+	u32 device;
+};
+
+static struct vexpress_spc_drvdata *info;
+static u32 *vexpress_spc_config_data;
+static struct vexpress_config_bridge *vexpress_spc_config_bridge;
+static struct vexpress_config_func *opp_func, *perf_func;
+
+static int vexpress_spc_load_result = -EAGAIN;
+static DEFINE_MUTEX(vexpress_spc_loading);
+
+static inline bool vexpress_spc_initialized(void)
+{
+	return vexpress_spc_load_result == 0;
+}
+
+/**
+ * vexpress_spc_write_resume_reg() - set the jump address used for warm boot
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @addr: physical resume address
+ */
+void vexpress_spc_write_resume_reg(u32 cluster, u32 cpu, u32 addr)
+{
+	void __iomem *baseaddr;
+
+	if (WARN_ON_ONCE(cluster >= MAX_CLUSTERS))
+		return;
+
+	if (cluster != info->a15_clusid)
+		baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
+	else
+		baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
+
+	writel_relaxed(addr, baseaddr);
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_write_resume_reg);
+
+/**
+ * vexpress_spc_get_nb_cpus() - get number of cpus in a cluster
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ *
+ * Return: number of cpus in the cluster
+ *         -EINVAL if cluster number invalid
+ */
+int vexpress_spc_get_nb_cpus(u32 cluster)
+{
+	u32 val;
+
+	if (WARN_ON_ONCE(cluster >= MAX_CLUSTERS))
+		return -EINVAL;
+
+	val = readl_relaxed(info->baseaddr + SYS_INFO);
+	val = (cluster != info->a15_clusid) ? (val >> 20) : (val >> 16);
+	return val & 0xf;
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_get_nb_cpus);
+
+/**
+ * vexpress_spc_get_performance - get current performance level of cluster
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @freq: pointer to the performance level to be assigned
+ *
+ * Return: 0 on success
+ *         < 0 on read error
+ */
+int vexpress_spc_get_performance(u32 cluster, u32 *freq)
+{
+	u32 perf_cfg_reg;
+	int perf, ret;
+
+	if (!vexpress_spc_initialized() || (cluster >= MAX_CLUSTERS))
+		return -EINVAL;
+
+	perf_cfg_reg = cluster != info->a15_clusid ? PERF_LVL_A7 : PERF_LVL_A15;
+	ret = vexpress_config_read_timeout(perf_func, perf_cfg_reg,
+				&perf, usecs_to_jiffies(TIME_OUT_US));
+
+	if (!ret)
+		*freq = info->freqs[cluster][perf];
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_get_performance);
+
+/**
+ * vexpress_spc_get_perf_index - get performance level corresponding to
+ *				 a frequency
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @freq: frequency to be looked-up
+ *
+ * Return: perf level index on success
+ *         -EINVAL on error
+ */
+static int vexpress_spc_find_perf_index(u32 cluster, u32 freq)
+{
+	int idx;
+
+	for (idx = 0; idx < info->freqs_cnt[cluster]; idx++)
+		if (info->freqs[cluster][idx] == freq)
+			break;
+	return (idx == info->freqs_cnt[cluster]) ? -EINVAL : idx;
+}
+
+/**
+ * vexpress_spc_set_performance - set current performance level of cluster
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @freq: performance level to be programmed
+ *
+ * Returns: 0 on success
+ *          < 0 on write error
+ */
+int vexpress_spc_set_performance(u32 cluster, u32 freq)
+{
+	int ret, perf, offset;
+
+	if (!vexpress_spc_initialized() || (cluster >= MAX_CLUSTERS))
+		return -EINVAL;
+
+	offset = (cluster != info->a15_clusid) ? PERF_LVL_A7 : PERF_LVL_A15;
+
+	perf = vexpress_spc_find_perf_index(cluster, freq);
+
+	if (perf < 0 || perf >= MAX_OPPS)
+		return -EINVAL;
+
+	ret = vexpress_config_write_timeout(perf_func, offset,
+			perf, usecs_to_jiffies(TIME_OUT_US));
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_set_performance);
+
+static void vexpress_spc_set_wake_intr(u32 mask)
+{
+	writel_relaxed(mask & VEXPRESS_SPC_WAKE_INTR_MASK,
+	       info->baseaddr + WAKE_INT_MASK);
+}
+
+static inline void reg_bitmask(u32 *reg, u32 mask, bool set)
+{
+	if (set)
+		*reg |= mask;
+	else
+		*reg &= ~mask;
+}
+
+/**
+ * vexpress_spc_set_global_wakeup_intr()
+ *
+ * Function to set/clear global wakeup IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @set: if true, global wake-up IRQs are set, if false they are cleared
+ *
+ */
+void vexpress_spc_set_global_wakeup_intr(bool set)
+{
+	u32 wake_int_mask_reg = 0;
+
+	wake_int_mask_reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+	reg_bitmask(&wake_int_mask_reg, GBL_WAKEUP_INT_MSK, set);
+	vexpress_spc_set_wake_intr(wake_int_mask_reg);
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_set_global_wakeup_intr);
+
+/**
+ * vexpress_spc_set_cpu_wakeup_irq()
+ *
+ * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @set: if true, wake-up IRQs are set, if false they are cleared
+ *
+ */
+void vexpress_spc_set_cpu_wakeup_irq(u32 cpu, u32 cluster, bool set)
+{
+	u32 mask = 0;
+	u32 wake_int_mask_reg = 0;
+
+	mask = 1 << cpu;
+	if (info->a15_clusid != cluster)
+		mask <<= 4;
+
+	wake_int_mask_reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+	reg_bitmask(&wake_int_mask_reg, mask, set);
+	vexpress_spc_set_wake_intr(wake_int_mask_reg);
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_set_cpu_wakeup_irq);
+
+/**
+ * vexpress_spc_powerdown_enable()
+ *
+ * Function to enable/disable cluster powerdown. Not protected by locking
+ * since it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @enable: if true enables powerdown, if false disables it
+ *
+ */
+void vexpress_spc_powerdown_enable(u32 cluster, bool enable)
+{
+	u32 pwdrn_reg = 0;
+
+	if (cluster >= MAX_CLUSTERS)
+		return;
+	pwdrn_reg = cluster != info->a15_clusid ? A7_PWRDN_EN : A15_PWRDN_EN;
+	writel_relaxed(enable, info->baseaddr + pwdrn_reg);
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_powerdown_enable);
+
+irqreturn_t vexpress_spc_irq_handler(int irq, void *data)
+{
+	int ret;
+	u32 status = readl_relaxed(info->baseaddr + PWC_STATUS);
+
+	if (!(status & RESPONSE_MASK(info->cur_req_type)))
+		return IRQ_NONE;
+
+	if ((status == STAT_COMPLETE(SYS_CFGCTRL_STATUS))
+			&& vexpress_spc_config_data) {
+		*vexpress_spc_config_data =
+				readl_relaxed(info->baseaddr + SYS_CFG_RDATA);
+		vexpress_spc_config_data = NULL;
+	}
+
+	ret = STAT_COMPLETE(info->cur_req_type) ? 0 : -EIO;
+	info->cur_req_type = 0;
+	vexpress_config_complete(vexpress_spc_config_bridge, ret);
+	return IRQ_HANDLED;
+}
+
+/**
+ * Based on the firmware documentation, this is always fixed to 20
+ * All the 4 OSC: A15 PLL0/1, A7 PLL0/1 must be programmed same
+ * values for both control and value registers.
+ * This function uses A15 PLL 0 registers to compute multiple factor
+ * F out = F in * (CLKF + 1) / ((CLKOD + 1) * (CLKR + 1))
+ */
+static inline int __get_mult_factor(void)
+{
+	int i_div, o_div, f_div;
+	u32 tmp;
+
+	tmp = readl(info->baseaddr + SCC_CFGREG19);
+	f_div = (tmp >> CLKF_SHIFT) & CLKF_MASK;
+
+	tmp = readl(info->baseaddr + SCC_CFGREG20);
+	o_div = (tmp >> CLKOD_SHIFT) & CLKOD_MASK;
+	i_div = (tmp >> CLKR_SHIFT) & CLKR_MASK;
+
+	return (f_div + 1) / ((o_div + 1) * (i_div + 1));
+}
+
+/**
+ * vexpress_spc_populate_opps() - initialize opp tables from microcontroller
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ *
+ * Return: 0 on success
+ *         < 0 on error
+ */
+static int vexpress_spc_populate_opps(u32 cluster)
+{
+	u32 data = 0, ret, i, offset;
+	int mult_fact = __get_mult_factor();
+
+	if (WARN_ON_ONCE(cluster >= MAX_CLUSTERS))
+		return -EINVAL;
+
+	offset = cluster != info->a15_clusid ? OPP_A7_OFFSET : OPP_A15_OFFSET;
+	for (i = 0; i < MAX_OPPS; i++) {
+		ret = vexpress_config_read_timeout(opp_func, i + offset,
+				&data, usecs_to_jiffies(TIME_OUT_US));
+		if (!ret)
+			info->freqs[cluster][i] = (data & 0xFFFFF) * mult_fact;
+		else
+			break;
+	}
+
+	info->freqs_cnt[cluster] = i;
+	return ret;
+}
+
+/**
+ * vexpress_spc_get_freq_table() - Retrieve a pointer to the frequency
+ *				   table for a given cluster
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @fptr: pointer to be initialized
+ * Return: operating points count on success
+ *         -EINVAL on pointer error
+ */
+int vexpress_spc_get_freq_table(u32 cluster, u32 **fptr)
+{
+	if (WARN_ON_ONCE(!fptr || cluster >= MAX_CLUSTERS))
+		return -EINVAL;
+	*fptr = info->freqs[cluster];
+	return info->freqs_cnt[cluster];
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_get_freq_table);
+
+static void *vexpress_spc_func_get(struct device *dev,
+		struct device_node *node, const char *id)
+{
+	struct vexpress_spc_func *spc_func;
+	u32 func_device[2];
+	int err = 0;
+
+	spc_func = kzalloc(sizeof(*spc_func), GFP_KERNEL);
+	if (!spc_func)
+		return NULL;
+
+	if (strcmp(id, "opp") == 0) {
+		spc_func->type = CONFIG_FUNC;
+		spc_func->function = OPP_FUNCTION;
+		spc_func->device = OPP_BASE_DEVICE;
+	} else if (strcmp(id, "perf") == 0) {
+		spc_func->type = PERF_FUNC;
+	} else if (node) {
+		of_node_get(node);
+		err = of_property_read_u32_array(node,
+				"arm,vexpress-sysreg,func", func_device,
+				ARRAY_SIZE(func_device));
+		of_node_put(node);
+		spc_func->type = CONFIG_FUNC;
+		spc_func->function = func_device[0];
+		spc_func->device = func_device[1];
+	}
+
+	if (WARN_ON(err)) {
+		kfree(spc_func);
+		return NULL;
+	}
+
+	pr_debug("func 0x%p = 0x%x, %d %d\n", spc_func,
+					     spc_func->function,
+					     spc_func->device,
+					     spc_func->type);
+
+	return spc_func;
+}
+
+static void vexpress_spc_func_put(void *func)
+{
+	kfree(func);
+}
+
+static int vexpress_spc_func_exec(void *func, int offset, bool write,
+				  u32 *data)
+{
+	struct vexpress_spc_func *spc_func = func;
+	u32 command;
+
+	/*
+	 * Setting and retrieval of operating points is not part of
+	 * DCC config interface. It was made to go through the same
+	 * code path so that requests to the M3 can be serialized
+	 * properly with config reads/writes through the common
+	 * vexpress config interface
+	 */
+	switch (spc_func->type) {
+	case PERF_FUNC:
+		if (write) {
+			info->cur_req_type = (offset == PERF_LVL_A15) ?
+					A15_OPP_STATUS : A7_OPP_STATUS;
+			writel_relaxed(*data, info->baseaddr + offset);
+			return VEXPRESS_CONFIG_STATUS_WAIT;
+		} else {
+			*data = readl_relaxed(info->baseaddr + offset);
+			return VEXPRESS_CONFIG_STATUS_DONE;
+		}
+	case CONFIG_FUNC:
+		info->cur_req_type = SYS_CFGCTRL_STATUS;
+
+		command = SYS_CFGCTRL_START;
+		command |= write ? SYS_CFGCTRL_WRITE : 0;
+		command |= SYS_CFGCTRL_FUNC(spc_func->function);
+		command |= SYS_CFGCTRL_DEVICE(spc_func->device + offset);
+
+		pr_debug("command %x\n", command);
+
+		if (!write)
+			vexpress_spc_config_data = data;
+		else
+			writel_relaxed(command, info->baseaddr + SYS_CFG_WDATA);
+		writel_relaxed(command, info->baseaddr + SYS_CFGCTRL);
+
+		return VEXPRESS_CONFIG_STATUS_WAIT;
+	default:
+		return -EINVAL;
+	}
+}
+
+struct vexpress_config_bridge_info vexpress_spc_config_bridge_info = {
+	.name = "vexpress-spc",
+	.func_get = vexpress_spc_func_get,
+	.func_put = vexpress_spc_func_put,
+	.func_exec = vexpress_spc_func_exec,
+};
+
+static const struct of_device_id vexpress_spc_ids[] __initconst = {
+	{ .compatible = "arm,vexpress-spc,v2p-ca15_a7" },
+	{ .compatible = "arm,vexpress-spc" },
+	{},
+};
+
+static int vexpress_spc_init(void)
+{
+	int ret;
+	struct device_node *node = of_find_matching_node(NULL,
+							 vexpress_spc_ids);
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		pr_err("%s: unable to allocate mem\n", __func__);
+		return -ENOMEM;
+	}
+
+	info->baseaddr = of_iomap(node, 0);
+	if (WARN_ON(!info->baseaddr)) {
+		ret = -ENXIO;
+		goto mem_free;
+	}
+
+	info->irq = irq_of_parse_and_map(node, 0);
+
+	if (WARN_ON(!info->irq)) {
+		ret = -ENXIO;
+		goto unmap;
+	}
+
+	readl_relaxed(info->baseaddr + PWC_STATUS);
+
+	ret = request_irq(info->irq, vexpress_spc_irq_handler,
+		IRQF_DISABLED | IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+		"arm-spc", info);
+
+	if (ret) {
+		pr_err("IRQ %d request failed\n", info->irq);
+		ret = -ENODEV;
+		goto unmap;
+	}
+
+	info->a15_clusid = readl_relaxed(info->baseaddr + A15_CONF) & 0xf;
+
+	vexpress_spc_config_bridge = vexpress_config_bridge_register(
+			node, &vexpress_spc_config_bridge_info);
+
+	if (WARN_ON(!vexpress_spc_config_bridge)) {
+		ret = -ENODEV;
+		goto unmap;
+	}
+
+	opp_func = vexpress_config_func_get(vexpress_spc_config_bridge, "opp");
+	perf_func =
+		vexpress_config_func_get(vexpress_spc_config_bridge, "perf");
+
+	if (!opp_func || !perf_func) {
+		ret = -ENODEV;
+		goto unmap;
+	}
+
+	if (vexpress_spc_populate_opps(0) || vexpress_spc_populate_opps(1)) {
+		if (info->irq)
+			free_irq(info->irq, info);
+		pr_err("failed to build OPP table\n");
+		ret = -ENODEV;
+		goto unmap;
+	}
+	/*
+	 * Multi-cluster systems may need this data when non-coherent, during
+	 * cluster power-up/power-down. Make sure it reaches main memory:
+	 */
+	sync_cache_w(info);
+	sync_cache_w(&info);
+	pr_info("vexpress-spc loaded at %p\n", info->baseaddr);
+	return 0;
+
+unmap:
+	iounmap(info->baseaddr);
+
+mem_free:
+	kfree(info);
+	return ret;
+}
+
+bool vexpress_spc_check_loaded(void)
+{
+	if (vexpress_spc_load_result != -EAGAIN)
+		return vexpress_spc_initialized();
+
+	mutex_lock(&vexpress_spc_loading);
+	if (vexpress_spc_load_result == -EAGAIN)
+		vexpress_spc_load_result = vexpress_spc_init();
+	mutex_unlock(&vexpress_spc_loading);
+	return vexpress_spc_initialized();
+}
+EXPORT_SYMBOL_GPL(vexpress_spc_check_loaded);
+
+static int __init vexpress_spc_early_init(void)
+{
+	vexpress_spc_check_loaded();
+	return vexpress_spc_load_result;
+}
+early_initcall(vexpress_spc_early_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Serial Power Controller (SPC) support");
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index e5015d8..15cc123 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -147,4 +147,47 @@ void vexpress_clk_of_register_spc(void);
 void vexpress_clk_init(void __iomem *sp810_base);
 void vexpress_clk_of_init(void);
 
+/* SPC */
+
+#define	VEXPRESS_SPC_WAKE_INTR_IRQ(cluster, cpu) \
+			(1 << (4 * (cluster) + (cpu)))
+#define	VEXPRESS_SPC_WAKE_INTR_FIQ(cluster, cpu) \
+			(1 << (7 * (cluster) + (cpu)))
+#define	VEXPRESS_SPC_WAKE_INTR_SWDOG		(1 << 10)
+#define	VEXPRESS_SPC_WAKE_INTR_GTIMER		(1 << 11)
+#define	VEXPRESS_SPC_WAKE_INTR_MASK		0xFFF
+
+#ifdef CONFIG_VEXPRESS_SPC
+extern bool vexpress_spc_check_loaded(void);
+extern void vexpress_spc_set_cpu_wakeup_irq(u32 cpu, u32 cluster, bool set);
+extern void vexpress_spc_set_global_wakeup_intr(bool set);
+extern int vexpress_spc_get_freq_table(u32 cluster, u32 **fptr);
+extern int vexpress_spc_get_performance(u32 cluster, u32 *freq);
+extern int vexpress_spc_set_performance(u32 cluster, u32 freq);
+extern void vexpress_spc_write_resume_reg(u32 cluster, u32 cpu, u32 addr);
+extern int vexpress_spc_get_nb_cpus(u32 cluster);
+extern void vexpress_spc_powerdown_enable(u32 cluster, bool enable);
+#else
+static inline bool vexpress_spc_check_loaded(void) { return false; }
+static inline void vexpress_spc_set_cpu_wakeup_irq(u32 cpu, u32 cluster,
+						   bool set) { }
+static inline void vexpress_spc_set_global_wakeup_intr(bool set) { }
+static inline int vexpress_spc_get_freq_table(u32 cluster, u32 **fptr)
+{
+	return -ENODEV;
+}
+static inline int vexpress_spc_get_performance(u32 cluster, u32 *freq)
+{
+	return -ENODEV;
+}
+static inline int vexpress_spc_set_performance(u32 cluster, u32 freq)
+{
+	return -ENODEV;
+}
+static inline void vexpress_spc_write_resume_reg(u32 cluster,
+						 u32 cpu, u32 addr) { }
+static inline int vexpress_spc_get_nb_cpus(u32 cluster) { return -ENODEV; }
+static inline void vexpress_spc_powerdown_enable(u32 cluster, bool enable) { }
+#endif
+
 #endif
-- 
1.8.2.2




From will.deacon at arm.com  Fri May 24 08:56:37 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 May 2013 13:56:37 +0100
Subject: [PATCH v2 4/4] ARM: cacheflush: don't bother rounding to nearest
 vma
In-Reply-To: <20130524115917.GY18614@n2100.arm.linux.org.uk>
References: <1369395087-30972-1-git-send-email-will.deacon@arm.com>
 <1369395087-30972-5-git-send-email-will.deacon@arm.com>
 <20130524115917.GY18614@n2100.arm.linux.org.uk>
Message-ID: <20130524125637.GD29963@mudshark.cambridge.arm.com>

On Fri, May 24, 2013 at 12:59:17PM +0100, Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 12:31:27PM +0100, Will Deacon wrote:
> > do_cache_op finds the lowest VMA contained in the specified address
> > range and rounds the range to cover only the mapped addresses.
> > 
> > Since commit 4542b6a0fa6b ("ARM: 7365/1: drop unused parameter from
> > flush_cache_user_range") the VMA is not used for anything else in this
> > code and seeing as the low-level cache flushing routines return -EFAULT
> > if the address is not valid, there is no need for this range truncation.
> > 
> > This patch removes the VMA handling code from the cacheflushing syscall.
> 
> The only thing which access_ok() tells you is that the addresses are
> _potentially_ valid user addresses.  That's not what the VMA check is
> there for.

Agreed, but it becomes necessary if we remove the vma check, since then
kernel addresses could be passed in unnoticed. The moment we get a fault,
we'll stop and return -EFAULT.

> That check is there to make sure userspace doesn't do something idiotic,
> and to keep the use of this API limited to specific actions such as self
> modifying code, and not a general purpose cache flushing API covering
> multiple VMAs.

Why make the distinction? You can already create single VMAs up to around
2GB and use the syscall in mainline today to flush that area by line. With
these patches we avoid touching mmap_sem, simplify the semantics of the
call, remove the possibility of DoS with non-preemptible kernels (which also
exists in mainline today) and measurably improve performance (~2%
improvement on a browser benchmark test).

If userspace does something idiotic, that should be fine as long as the
idiocy is confined to the task issuing the system call.

Will


From mst at redhat.com  Fri May 24 09:00:32 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Fri, 24 May 2013 16:00:32 +0300
Subject: [PATCH v2 07/10] powerpc: uaccess s/might_sleep/might_fault/
In-Reply-To: <201305221559.01806.arnd@arndb.de>
References: <cover.1368702323.git.mst@redhat.com>
 <2aa6c3da21a28120126732b5e0b4ecd6cba8ca3b.1368702323.git.mst@redhat.com>
 <201305221559.01806.arnd@arndb.de>
Message-ID: <20130524130032.GA10167@redhat.com>

On Wed, May 22, 2013 at 03:59:01PM +0200, Arnd Bergmann wrote:
> On Thursday 16 May 2013, Michael S. Tsirkin wrote:
> > @@ -178,7 +178,7 @@ do {                                                                \
> >         long __pu_err;                                          \
> >         __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
> >         if (!is_kernel_addr((unsigned long)__pu_addr))          \
> > -               might_sleep();                                  \
> > +               might_fault();                                  \
> >         __chk_user_ptr(ptr);                                    \
> >         __put_user_size((x), __pu_addr, (size), __pu_err);      \
> >         __pu_err;                                               \
> > 
> 
> Another observation:
> 
> 	if (!is_kernel_addr((unsigned long)__pu_addr))
> 		might_sleep();
> 
> is almost the same as
> 
> 	might_fault();
> 
> except that it does not call might_lock_read().
> 
> The version above may have been put there intentionally and correctly, but
> if you want to replace it with might_fault(), you should remove the
> "if ()" condition.
> 
> 	Arnd

Well not exactly. The non-inline might_fault checks the
current segment, not the address.
I'm guessing this is trying to do the same just without
pulling in segment_eq, but I'd like a confirmation
from more PPC maintainers.

Guys would you ack

- 	if (!is_kernel_addr((unsigned long)__pu_addr))
- 		might_fault();
+ 	might_fault();

on top of this patch?

Also, any volunteer to test this (not just test-build)?

-- 
MST


From rogerq at ti.com  Fri May 24 09:06:58 2013
From: rogerq at ti.com (Roger Quadros)
Date: Fri, 24 May 2013 16:06:58 +0300
Subject: [PATCH] ARM: OMAP2+: omap-usb-host: Fix memory leaks
Message-ID: <1369400818-31625-1-git-send-email-rogerq@ti.com>

Fix memory leaks in the error path.
Also, use platform_device_register_full() to allocate
the platform devices and set platform data.

Signed-off-by: Roger Quadros <rogerq at ti.com>
---
 arch/arm/mach-omap2/usb-host.c |  106 +++++++++++++++++++++-------------------
 1 files changed, 56 insertions(+), 50 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f..609b330 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 
 #include "soc.h"
 #include "omap_device.h"
@@ -560,7 +561,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 	struct regulator_init_data *reg_data;
 	struct fixed_voltage_config *config;
 	struct platform_device *pdev;
-	int ret;
+	struct platform_device_info pdevinfo;
+	int ret = -ENOMEM;
 
 	supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
 	if (!supplies)
@@ -571,7 +573,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 
 	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
 	if (!reg_data)
-		return -ENOMEM;
+		goto err_data;
 
 	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
 	reg_data->consumer_supplies = supplies;
@@ -580,39 +582,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
 			GFP_KERNEL);
 	if (!config)
-		return -ENOMEM;
+		goto err_config;
+
+	config->supply_name = kstrdup(name, GFP_KERNEL);
+	if (!config->supply_name)
+		goto err_supplyname;
 
-	config->supply_name = name;
 	config->gpio = gpio;
 	config->enable_high = polarity;
 	config->init_data = reg_data;
 
 	/* create a regulator device */
-	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-	if (!pdev)
-		return -ENOMEM;
+	memset(&pdevinfo, 0, sizeof(pdevinfo));
+	pdevinfo.name = reg_name;
+	pdevinfo.id = PLATFORM_DEVID_AUTO;
+	pdevinfo.data = config;
+	pdevinfo.size_data = sizeof(*config);
 
-	pdev->id = PLATFORM_DEVID_AUTO;
-	pdev->name = reg_name;
-	pdev->dev.platform_data = config;
+	pdev = platform_device_register_full(&pdevinfo);
+	if (IS_ERR(pdev)) {
+		ret = PTR_ERR(pdev);
+		pr_err("%s: Failed registering regulator %s for %s : %d\n",
+				__func__, name, dev_id, ret);
+		goto err_register;
+	}
 
-	ret = platform_device_register(pdev);
-	if (ret)
-		pr_err("%s: Failed registering regulator %s for %s\n",
-				__func__, name, dev_id);
+	return 0;
 
+err_register:
+	kfree(config->supply_name);
+err_supplyname:
+	kfree(config);
+err_config:
+	kfree(reg_data);
+err_data:
+	kfree(supplies);
 	return ret;
 }
 
+#define MAX_STR 20
+
 int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
 {
-	char *rail_name;
-	int i, len;
+	char rail_name[MAX_STR];
+	int i;
 	struct platform_device *pdev;
 	char *phy_id;
-
-	/* the phy_id will be something like "nop_usb_xceiv.1" */
-	len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
+	struct platform_device_info pdevinfo;
 
 	for (i = 0; i < num_phys; i++) {
 
@@ -627,25 +643,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
 			!gpio_is_valid(phy->vcc_gpio))
 			continue;
 
-		/* create a NOP PHY device */
-		pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-		if (!pdev)
-			return -ENOMEM;
-
-		pdev->id = phy->port;
-		pdev->name = nop_name;
-		pdev->dev.platform_data = phy->platform_data;
-
-		phy_id = kmalloc(len, GFP_KERNEL);
-		if (!phy_id)
+		phy_id = kmalloc(MAX_STR, GFP_KERNEL);
+		if (!phy_id) {
+			pr_err("%s: kmalloc() failed\n", __func__);
 			return -ENOMEM;
+		}
 
-		scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
-					pdev->id);
-
-		if (platform_device_register(pdev)) {
-			pr_err("%s: Failed to register device %s\n",
-				__func__,  phy_id);
+		/* create a NOP PHY device */
+		memset(&pdevinfo, 0, sizeof(pdevinfo));
+		pdevinfo.name = nop_name;
+		pdevinfo.id = phy->port;
+		pdevinfo.data = phy->platform_data;
+		pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data);
+
+		scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d",
+					phy->port);
+		pdev = platform_device_register_full(&pdevinfo);
+		if (IS_ERR(pdev)) {
+			pr_err("%s: Failed to register device %s : %ld\n",
+				__func__,  phy_id, PTR_ERR(pdev));
+			kfree(phy_id);
 			continue;
 		}
 
@@ -653,26 +670,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
 
 		/* Do we need RESET regulator ? */
 		if (gpio_is_valid(phy->reset_gpio)) {
-
-			rail_name = kmalloc(13, GFP_KERNEL);
-			if (!rail_name)
-				return -ENOMEM;
-
-			scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
-
+			scnprintf(rail_name, MAX_STR,
+					"hsusb%d_reset", phy->port);
 			usbhs_add_regulator(rail_name, phy_id, "reset",
 						phy->reset_gpio, 1);
 		}
 
 		/* Do we need VCC regulator ? */
 		if (gpio_is_valid(phy->vcc_gpio)) {
-
-			rail_name = kmalloc(13, GFP_KERNEL);
-			if (!rail_name)
-				return -ENOMEM;
-
-			scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
-
+			scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
 			usbhs_add_regulator(rail_name, phy_id, "vcc",
 					phy->vcc_gpio, phy->vcc_polarity);
 		}
-- 
1.7.4.1



From mst at redhat.com  Fri May 24 09:11:04 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Fri, 24 May 2013 16:11:04 +0300
Subject: [PATCH v2 07/10] powerpc: uaccess s/might_sleep/might_fault/
In-Reply-To: <20130524130032.GA10167@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <2aa6c3da21a28120126732b5e0b4ecd6cba8ca3b.1368702323.git.mst@redhat.com>
 <201305221559.01806.arnd@arndb.de>
 <20130524130032.GA10167@redhat.com>
Message-ID: <20130524131104.GA11462@redhat.com>

On Fri, May 24, 2013 at 04:00:32PM +0300, Michael S. Tsirkin wrote:
> On Wed, May 22, 2013 at 03:59:01PM +0200, Arnd Bergmann wrote:
> > On Thursday 16 May 2013, Michael S. Tsirkin wrote:
> > > @@ -178,7 +178,7 @@ do {                                                                \
> > >         long __pu_err;                                          \
> > >         __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
> > >         if (!is_kernel_addr((unsigned long)__pu_addr))          \
> > > -               might_sleep();                                  \
> > > +               might_fault();                                  \
> > >         __chk_user_ptr(ptr);                                    \
> > >         __put_user_size((x), __pu_addr, (size), __pu_err);      \
> > >         __pu_err;                                               \
> > > 
> > 
> > Another observation:
> > 
> > 	if (!is_kernel_addr((unsigned long)__pu_addr))
> > 		might_sleep();
> > 
> > is almost the same as
> > 
> > 	might_fault();
> > 
> > except that it does not call might_lock_read().
> > 
> > The version above may have been put there intentionally and correctly, but
> > if you want to replace it with might_fault(), you should remove the
> > "if ()" condition.
> > 
> > 	Arnd
> 
> Well not exactly. The non-inline might_fault checks the
> current segment, not the address.
> I'm guessing this is trying to do the same just without
> pulling in segment_eq, but I'd like a confirmation
> from more PPC maintainers.
> 
> Guys would you ack
> 
> - 	if (!is_kernel_addr((unsigned long)__pu_addr))
> - 		might_fault();
> + 	might_fault();
> 
> on top of this patch?

OK I spoke too fast: I found this:

    powerpc: Fix incorrect might_sleep in __get_user/__put_user on kernel addresses
    
    We have a case where __get_user and __put_user can validly be used
    on kernel addresses in interrupt context - namely, the alignment
    exception handler, as our get/put_unaligned just do a single access
    and rely on the alignment exception handler to fix things up in the
    rare cases where the cpu can't handle it in hardware.  Thus we can
    get alignment exceptions in the network stack at interrupt level.
    The alignment exception handler does a __get_user to read the
    instruction and blows up in might_sleep().
    
    Since a __get_user on a kernel address won't actually ever sleep,
    this makes the might_sleep conditional on the address being less
    than PAGE_OFFSET.
    
    Signed-off-by: Paul Mackerras <paulus at samba.org>

So this won't work, unless we add the is_kernel_addr check
to might_fault. That will become possible on top of this patchset
but let's consider this carefully, and make this a separate
patchset, OK?

> Also, any volunteer to test this (not just test-build)?
> 
> -- 
> MST


From mfuzzey at parkeon.com  Fri May 24 09:12:49 2013
From: mfuzzey at parkeon.com (Martin Fuzzey)
Date: Fri, 24 May 2013 15:12:49 +0200
Subject: LVDS (LDB) driver for i.MX53 IPU
In-Reply-To: <Pine.LNX.4.64.1305241431460.2226@axis700.grange>
References: <5134DF0E.7010402@parkeon.com>
 <20130310223241.GQ1906@pengutronix.de>
 <Pine.LNX.4.64.1305241431460.2226@axis700.grange>
Message-ID: <519F6751.7020706@parkeon.com>

Hi Guennadi,

On 24/05/13 14:35, Guennadi Liakhovetski wrote:
> Hi Sascha
>
> On Sun, 10 Mar 2013, Sascha Hauer wrote:
>
>>
>> We have a driver for the ldb. Indeed the driver itself is trivial, but
>> the integration is tricky. For accessing the register the syscon binding
>> can be used. The clock is also a problem, also the mux to the IPU(s)
>>
>> I'll talk with Philipp tomorrow and I think we can send you the current
>> state then.
> How's it looking in the meantime? Any plans to mainline it? Or would you
> be prepared to publish what you've got to try and see whether others can
> help you with this?
Philipp submitted them on March 28 "[PATCH v3 0/11] LVDS Display Bridge 
support for i.MX"
The drivers/staging parts don't seem to have been applied (not in 
linux/next at any rate)

I've added them to my local tree and they work fine (on i.MX53)

Martin


From fabio.baltieri at linaro.org  Fri May 24 09:28:13 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Fri, 24 May 2013 15:28:13 +0200
Subject: [PATCH] ARM: ux500: select SND_SOC_UX500 for ux500
Message-ID: <1369402093-27817-1-git-send-email-fabio.baltieri@linaro.org>

Enable ux500 specific ALSA SoC drivers by default on u8500_defconfig.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---

Hi Linus,

As I noticed that you just updated your ux500-defconfig branch, and the ux500
sound driver should be working fine in the next kernel, I'm sending a patch to
enable it by default.  This applies on top of your recent commit "ARM: ux500:
update defconfig base".

Thanks,
Fabio

 arch/arm/configs/u8500_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index da0614a..da353e0 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -69,6 +69,11 @@ CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_AB8500=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_UX500=y
+CONFIG_SND_SOC_UX500_MACH_MOP500=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_UX500=y
-- 
1.8.2



From arnd at arndb.de  Fri May 24 09:30:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 15:30:20 +0200
Subject: [PATCH v2 07/10] powerpc: uaccess s/might_sleep/might_fault/
In-Reply-To: <20130524131104.GA11462@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
 <20130524130032.GA10167@redhat.com> <20130524131104.GA11462@redhat.com>
Message-ID: <201305241530.20845.arnd@arndb.de>

On Friday 24 May 2013, Michael S. Tsirkin wrote:
> So this won't work, unless we add the is_kernel_addr check
> to might_fault. That will become possible on top of this patchset
> but let's consider this carefully, and make this a separate
> patchset, OK?

Yes, makes sense.

	Arnd


From jbe at pengutronix.de  Fri May 24 09:33:19 2013
From: jbe at pengutronix.de (Juergen Beisert)
Date: Fri, 24 May 2013 15:33:19 +0200
Subject: mxsfb: DATA_FORMAT_24_BIT flag outputs invalid colours
In-Reply-To: <201305241300.25461.jbe@pengutronix.de>
References: <519E03B0.1080006@digi.com> <519F4435.5010703@digi.com>
 <201305241300.25461.jbe@pengutronix.de>
Message-ID: <201305241533.19941.jbe@pengutronix.de>

Hi Hector,

Juergen Beisert wrote:
> Hector Palacios wrote:
> > On 05/24/2013 12:28 PM, Juergen Beisert wrote:
> > > Hector Palacios wrote:
> > >> On 05/23/2013 03:31 PM, Juergen Beisert wrote:
> > >>> maxime.ripard at free-electrons.com wrote:
> > >>>> On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> > >>>>> I'm using an i.MX28 based board with lcd connected with 18bits data
> > >>>>> bus. My platform uses 32 bits per pixel:
> > >>>>>
> > >>>>> 	mxsfb_pdata.default_bpp = 32;
> > >>>>> 	mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
> > >>>>>
> > >>>>> With these settings the mxsfb.c driver sets flag DATA_FORMAT_24_BIT
> > >>>>> at HW_LCDIF_CTRL register in function mxsfb_set_par():
> > >>>>>
> > >>>>> 	case 32:
> > >>>>> 		dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
> > >>>>> 		ctrl |= CTRL_SET_WORD_LENGTH(3);
> > >>>>> 		switch (host->ld_intf_width) {
> > >>>>> 		case STMLCDIF_8BIT:
> > >>>>> 			dev_dbg(&host->pdev->dev,
> > >>>>> 					"Unsupported LCD bus width mapping\n");
> > >>>>> 			return -EINVAL;
> > >>>>> 		case STMLCDIF_16BIT:
> > >>>>> 		case STMLCDIF_18BIT:
> > >>>>> 			/* 24 bit to 18 bit mapping */
> > >>>>> 			ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
> > >>>>> 					    *  each colour component
> > >>>>> 					    */
> > >>>>> 			break;
> > >>>>> 		case STMLCDIF_24BIT:
> > >>>>> 			/* real 24 bit */
> > >>>>> 			break;
> > >>>>> 		}
> > >>>>>
> > >>>>> According to the manual, this flag does:
> > >>>>> 	0x0: ALL_24_BITS_VALID: Data input to the block is in 24 bpp
> > >>>>> format, such that all RGB 888 data is contained in 24 bits.
> > >>>>> 	0x1: DROP_UPPER_2_BITS_PER_BYTE ? Data input to the block is
> > >>>>> actually RGB 18 bpp, but there is 1 colour per byte, hence the
> > >>>>> upper 2 bits in each byte do not contain any useful data, and
> > >>>>> should be dropped.
> > >>>>>
> > >>>>> The setting of this flag is producing bad colours with true colour
> > >>>>> images (i.e. the Linux penguin is displayed ok, but QT applications
> > >>>>> or images displayed with fbv are not).
> > >>>>> I believe the setting of this flag is not correct (after all, if my
> > >>>>> bpp is 32, then all 24bit colours are useful and dropping the upper
> > >>>>> 2 bits is a bad idea).
> > >>>>> If I don't set it, then true colour images are displayed correctly.
> > >>>>> The only problem is that the Linux penguin is displayed much darker
> > >>>>> than usual (correct colours, but darker). Perhaps the 224 colour
> > >>>>> format of this image justifies it?
> > >>>>>
> > >>>>> I noticed the cfa10049 platform also uses the same configuration
> > >>>>> (18 bits data bus and 32bpp) and was wondering if true colour
> > >>>>> images are correctly displayed in this platform with this flag set
> > >>>>> (for example with fbv application [1]).
> > >>>>
> > >>>> I had the exact same problem, and suggested the exact same solution
> > >>>> a few weeks back.
> > >>>>
> > >>>> https://patchwork.kernel.org/patch/2470441/
> > >>>>
> > >>>> The conclusion of that discussion what that the userspace
> > >>>> applications were not honouring the bitfield correctly set by the
> > >>>> mxsfb driver, and as such, it was not a bug in the driver.
> > >>>>
> > >>>> While this is correct, I wonder, now that since we had that same
> > >>>> problem in a very short amount of time, if we couldn't set this
> > >>>> behaviour dependant of some (dt? kernel argument?) property so that
> > >>>> one could customise it anyway he want.
> > >>>>
> > >>>> Maxime
> > >>>
> > >>> i.MX2[3|8]    LCD1       LCD2       LCD3
> > >>>                 24bit      18bit      18bit
> > >>> --------------------------------------------
> > >>> LCD_D0         B0         B0         --
> > >>> LCD_D1         B1         B1         --
> > >>> LCD_D2         B2         B2         B0
> > >>> LCD_D3         B3         B3         B1
> > >>> LCD_D4         B4         B4         B2
> > >>> LCD_D5         B5         B5         B3
> > >>> LCD_D6         B6         G0         B4
> > >>> LCD_D7         B7         G1         B5
> > >>>
> > >>> LCD_D8         G0         G2         --
> > >>> LCD_D9         G1         G3         --
> > >>> LCD_D10        G2         G4         G0
> > >>> LCD_D11        G3         G5         G1
> > >>> LCD_D12        G4         R0         G2
> > >>> LCD_D13        G5         R1         G3
> > >>> LCD_D14        G6         R2         G4
> > >>> LCD_D15        G7         R3         G5
> > >>>
> > >>> LCD_D16        R0         R4         --
> > >>> LCD_D17        R1         R5         --
> > >>> LCD_D18        R2                    R0
> > >>> LCD_D19        R3                    R1
> > >>> LCD_D20        R4                    R2
> > >>> LCD_D21        R5                    R3
> > >>> LCD_D22        R6                    R4
> > >>> LCD_D23        R7                    R5
> > >>>
> > >>> Is your display connected like LCD2 or LCD3? LCD3 must still handled
> > >>> like a 24 bit display shown in LCD1, while only the LCD2-case is the
> > >>> "24 bit to 18 bit mapping" case.
> > >>>
> > >>> At least my current tests with an i.MX23 and a connection like LCD2
> > >>> are working here with a Qt application. Qt honours the pixel bitfield
> > >>> description. And I'm using the "bits-per-pixel = <32>" and "bus-width
> > >>> = <18>" entries in the device tree.
> > >>
> > >> I have a 24bit LCD display but my connection to it is done at 18bits
> > >> data width. Represented below as LCD4.
> > >> NOTE: In my LCD4 column, notation Rx/Gx/Bx represent the color bit in
> > >> memory as well as the display data line.
> > >> Since we use 32bpp each channel has 8 bits (R7..R0, etc.).
> > >> I understand that you have an 18bit display and that your notation in
> > >> LCD2 column represents the display data lines, not the color bit
> > >> indexes in memory.
> > >>
> > >> i.MX2[3|8]    LCD1       LCD2       LCD3	LCD4
> > >>                24bit      18bit      18bit	24bit connected at 18bit
> > >> -------------------------------------------------------
> > >> LCD_D0         B0         B0         --		B2
> > >> LCD_D1         B1         B1         --		B3
> > >> LCD_D2         B2         B2         B0		B4
> > >> LCD_D3         B3         B3         B1		B5
> > >> LCD_D4         B4         B4         B2		B6
> > >> LCD_D5         B5         B5         B3		B7
> > >> LCD_D6         B6         G0         B4		G2
> > >> LCD_D7         B7         G1         B5		G3
> > >>
> > >> LCD_D8         G0         G2         --		G4
> > >> LCD_D9         G1         G3         --		G5
> > >> LCD_D10        G2         G4         G0		G6
> > >> LCD_D11        G3         G5         G1		G7
> > >> LCD_D12        G4         R0         G2		R2
> > >> LCD_D13        G5         R1         G3		R3
> > >> LCD_D14        G6         R2         G4		R4
> > >> LCD_D15        G7         R3         G5		R5
> > >>
> > >> LCD_D16        R0         R4         --		R6
> > >> LCD_D17        R1         R5         --		R7
> > >> LCD_D18        R2                    R0
> > >> LCD_D19        R3                    R1
> > >> LCD_D20        R4                    R2
> > >> LCD_D21        R5                    R3
> > >> LCD_D22        R6                    R4
> > >> LCD_D23        R7                    R5
> > >>
> > >> For 32bpp (RGB888) and 18bit data bus I would expect the LCD
> > >> controller to take the six *most significant* bits [7..2] from each
> > >> color byte out to the LCD data bus (LCD_D17..D0) in the order depicted
> > >> in my LCD4 column.
> > >>
> > >> I'm not sure what the DATA_FORMAT_24_BIT flag is doing, but dropping
> > >> the two most significant bits of color in memory doesn't seem to be a
> > >> good idea unless (maybe) color is in 18bpp. Previous kernels did not
> > >> even touch this flag.
> > >>
> > >> Does the following patch make sense?
> > >>
> > >> diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
> > >> index b1c1a80..bb0a4e1 100644
> > >> --- a/drivers/video/mxsfb.c
> > >> +++ b/drivers/video/mxsfb.c
> > >> @@ -298,9 +298,6 @@ static int mxsfb_check_var(struct
> > >> fb_var_screeninfo *var, break;
> > >>                   case STMLCDIF_16BIT:
> > >>                   case STMLCDIF_18BIT:
> > >> -                       /* 24 bit to 18 bit mapping */
> > >> -                       rgb = def_rgb666;
> > >> -                       break;
> > >>                   case STMLCDIF_24BIT:
> > >>                           /* real 24 bit */
> > >>                           rgb = def_rgb888;
> > >> @@ -424,11 +421,6 @@ static int mxsfb_set_par(struct fb_info *fb_info)
> > >>                           return -EINVAL;
> > >>                   case STMLCDIF_16BIT:
> > >>                   case STMLCDIF_18BIT:
> > >> -                       /* 24 bit to 18 bit mapping */
> > >> -                       ctrl |= CTRL_DF24; /* ignore the upper 2 bits
> > >> in -                                           *  each colour
> > >> component -                                           */
> > >> -                       break;
> > >>                   case STMLCDIF_24BIT:
> > >>                           /* real 24 bit */
> > >>                           break;
> > >>
> > >> The setting of def_rgb666 for a 32bpp color depth does not make sense
> > >> to me because the color in memory is really rgb888.
> > >>
> > >> With this patch, my true color images are displayed ok and so does the
> > >> penguin logo. I don't know however how other displays connections at
> > >> 18bit will do.
> > >
> > > Your 24 bit display is connected like a regular 18 bit display. So they
> > > should work in the same way with the same settings. You *must* always
> > > skip two data bits from the memory RGB888 to form a RGB666 value.
> > >
> > > I just did some measurement here with my i.MX23 based hardware.
> > >
> > > I'm using 32 bits per pixel and the 18 bit display interface
> > > (LCD_D[0..17]).
> > >
> > > And surprise, surprise: the i.MX23 *always* maps the 24 bit input data
> > > to the 18 bit interface. And what does the DATA_FORMAT_24_BIT aka.
> > > CTRL_DF24 do??? Just simple: it seems its meaning changes with the
> > > interface width. The documentation says:
> > >
> > >    0 = all 24 bits are valid
> > >    1 = drop upper 2 bits per byte
> > >
> > > This text seems valid for a real 24 bit display (but I cannot test it).
> > > From my measurement its meaning changes when used with an 18 bit
> > > display to:
> > >
> > >    0 = drop lower 2 bits per byte
> > >    1 = drop upper 2 bits per byte
> > >
> > > When this bit is 0:
> > >
> > >        red     green    blue
> > >     10000001|00001111|10001111 (memory layout)
> > >
> > >     100000..|000011..|100011.. (at the display)
> > >
> > > When this bit is 1:
> > >
> > >        red     green    blue
> > >     10000001|00001111|10001111 (memory layout)
> > >
> > >     ..000001|..001111|..001111 (at the display)
> >
> > And how can the setting of this flag be useful?
>
> Maybe with this measurement knowledge is isn't useful any more. When I
> wrote this code I just used the datasheet.
>
> > In the example above, you had a red component of 0x81 (half way through
> > the scale), which is converted to a 0x01 (almost black) at the display.
> > Isn't this wrong?
> >
> > This only looks right to me if you set a 18bpp but even in that case
> > masking the upper bits isn't really needed at all.
>
> These bits should only show what is happen to the data. In both cases you
> must define a corresponding fb_bitfield description. Which means the
> currently existing def_rgb666 description is valid only when the
> DATA_FORMAT_24_BIT aka. CTRL_DF24 register bit is set.
>
> And for the DATA_FORMAT_24_BIT aka. CTRL_DF24 register be cleared you *can*
> use the def_rgb888 or define a different def_rgb666_shift like this one:
>
> static const struct fb_bitfield def_rgb666_shift[] = {
> 	[RED] = {
> 		.offset = 18,
> 		.length = 6,
> 	},
> 	[GREEN] = {
> 		.offset = 10,
> 		.length = 6,
> 	},
> 	[BLUE] = {
> 		.offset = 2,
> 		.length = 6,
> 	},
> 	[TRANSP] = {	/* no support for transparency */
> 		.length = 0,
> 	}
> };
>
> I'm not sure if it is of interest for a userland application to know if a
> display can handle 256 k or 16 M colours physically.
> With the def_rgb888 in use *all* displays look like 16 M colour LCDs. With
> the def_rgb666 in use an 18 bit display really looks like an 18 bit
> display.

Someone told me, Qt5 cannot handle this special RGB666 mode (even not the 
def_rgb666_shift memory layout mentioned above). My test are based on Qt4. 
Qt5 needs a regular RGB888 mode, which should silently be converted 
internally to RGB666 in the hardware.

So, your patch to always use the RGB888 memory layout seems to be the right 
way to go.

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From marex at denx.de  Fri May 24 09:57:23 2013
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 May 2013 15:57:23 +0200
Subject: [PATCH 2/2] ARM: dts: imx28: Adjust i2c interrupt bindings
In-Reply-To: <1369382887.4117.34.camel@weser.hi.pengutronix.de>
References: <1368713639-21485-1-git-send-email-fabio.estevam@freescale.com>
 <519E5732.1040800@free-electrons.com>
 <1369382887.4117.34.camel@weser.hi.pengutronix.de>
Message-ID: <201305241557.23904.marex@denx.de>

Dear Lucas Stach,

> Am Donnerstag, den 23.05.2013, 19:51 +0200 schrieb Alexandre Belloni:
> > Hi,
> 
> [...]
> 
> > > So while we _might_ be able to get the PIO mode to work on the i.MX23
> > > there is nothing in the doc stating that it's even meant to work. Even
> > > while PIO and DMA mode use the same internal mechanisms, there's still
> > > plenty of opportunities of fail in there. After all PIO mode relies on
> > > reading a debug register in the course of normal operation.
> > > 
> > > Only more extensive experimentation could show if we are in fact able
> > > to make it work, a first shot of using PIO mode on MX23 failed, so it
> > > might as well be that Juergens quick fix is correct and we have to
> > > disable PIO mode on MX23 altogether. That said please stop slapping
> > > the word "hack" over this patch until proven otherwise.
> > 
> > Still, Fabio and I have been experiencing the one second delay on
> > i.mx28. From my experience, it appeared between 3.7 and 3.9, see:
> > http://www.spinics.net/lists/linux-i2c/msg11985.html. I still didn't
> > take the time to investigate more yet but it confirms that PIO mode is
> > working on i.mx28 though with an annoying delay.
> 
> Just for the record: I know that PIO mode is functional on i.MX28
> because I have it working on one of our customer boards. I am rather
> much surprised it's still not working well for you, but haven't had a
> chance to investigate yet. The i.MX28 RM explicitly describes how to
> work with the PIO mode, so if it's not working this is bug somewhere.

I won't be surprised if there was more than one. The RM describes something , 
but has many flaws. I'm sure you noticed that yourself.

> This thread/patch is about a whole different problem, namely PIO mode
> being non-functional on i.MX23. As the i.MX23 RM doesn't describe the
> PIO mode, there is no indication that it's even meant to work on this
> chip.

I'm not against the patch per-se, but can we not get the best of this and 
instead try some more to fix the PIO on MX23 so the MX23 users won't suffer 
performance degradation on already weak CPU?

Best regards,
Marek Vasut


From sergei.shtylyov at cogentembedded.com  Fri May 24 10:02:32 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Fri, 24 May 2013 18:02:32 +0400
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <519F72F8.1000204@cogentembedded.com>

Hello.

On 24-05-2013 6:06, Simon Horman wrote:

> Add SATA clock for r8a7790 SoC (for both device tree and usual cases).

     I don't see where you are adding clock for device tree case.

> Register SATA controller as a "late" platform device on r8a7790 SoC.

     Does R8A7790 have these "early" and "late" lists? I guess not.

> Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
> Vladimir Barinov.

> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>   arch/arm/mach-shmobile/clock-r8a7790.c |  4 ++++
>   arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++
>   2 files changed, 25 insertions(+)

> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> index b393592..3619a52 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
[...]
> @@ -249,6 +252,7 @@ static struct clk_lookup lookups[] = {
>   	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
>   	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
>   	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
> +	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
>   };
>
>   #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> index ed7ee24..5a2a073 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
[...]
> @@ -118,6 +119,25 @@ static inline void r8a7790_register_scif(int idx)
>   				      sizeof(struct plat_sci_port));
>   }
>
> +static __init void r8a7790_register_sata1(void)

    What's with SATA0?

> +{
> +
> +	struct resource res[] = {

    Non-static variable with an intializer? Won't this be a waste of 
code? Wouldn't it be better to have it static __initdata?

> +		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),

     2 megabytes? Won't it be a waste of memory?

> +		DEFINE_RES_IRQ(gic_iid(106)),
> +	};
> +
> +	struct platform_device_info pdevinfo = {

    Same comment about non-static initialized structure...

> +		.name = "sata_rcar",
> +		.id = 1,
> +		.res = res,
> +		.num_res = ARRAY_SIZE(res),
> +		.dma_mask = DMA_BIT_MASK(32),
> +	};
> +
> +	platform_device_register_full(&pdevinfo);
> +}
> +

WBR, Sergei



From plagnioj at jcrosoft.com  Fri May 24 10:03:22 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 16:03:22 +0200
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <20130524112029.GW18614@n2100.arm.linux.org.uk>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
 <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
 <20130524112029.GW18614@n2100.arm.linux.org.uk>
Message-ID: <20130524140322.GD24476@game.jcrosoft.org>

On 12:20 Fri 24 May     , Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> > code snippet to the internal SRAM, then jump to run this code, but fail
> > to run.
> 
> And that is where your mistake is - you forgot that you're working with
> a CPU with harvard caches which will require some cache maintanence
> between copying the code and executing it.
> 
> You want to look at flush_icache_range() rather than making this memory
> strongly ordered.

I understand your point but today we map a SRAM as MT_DEVICE

I do not think it's the best

Best Regards,
J.


From plagnioj at jcrosoft.com  Fri May 24 10:05:28 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 16:05:28 +0200
Subject: [PATCH] ARM: at91/dt: add pinctrl definition for at91 tc blocks
In-Reply-To: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>
References: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <20130524140528.GE24476@game.jcrosoft.org>

On 12:05 Fri 24 May     , Boris BREZILLON wrote:
> Hello,
> 
> This patch adds pinctrl configs for at91 Timer Conter blocks.
> These pin configs will be referenced by "atmel,tcb-pwm" devices to
> setup pins as PWM output.

you need to rebase on

a cleanup I did preset on our git tag at91-3.11-cleanup

As we announce Mandaotory for 3.11

as I introduce Macro fro DT

Best Regards,
J.


From nicolas.ferre at atmel.com  Fri May 24 10:12:31 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 May 2013 16:12:31 +0200
Subject: [PATCH] ARM: at91/dt: add pinctrl definition for at91 tc blocks
In-Reply-To: <20130524140528.GE24476@game.jcrosoft.org>
References: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>
 <20130524140528.GE24476@game.jcrosoft.org>
Message-ID: <519F754F.50908@atmel.com>

On 24/05/2013 16:05, Jean-Christophe PLAGNIOL-VILLARD :
> On 12:05 Fri 24 May     , Boris BREZILLON wrote:
>> Hello,
>>
>> This patch adds pinctrl configs for at91 Timer Conter blocks.
>> These pin configs will be referenced by "atmel,tcb-pwm" devices to
>> setup pins as PWM output.
>
> you need to rebase on
>
> a cleanup I did preset on our git tag at91-3.11-cleanup
>
> As we announce Mandaotory for 3.11
>
> as I introduce Macro fro DT

Boris, Hold on.

I may have the solution for you. Give me some time and we may have the 
automatic generation for updating your patch.

Bye,
-- 
Nicolas Ferre


From rogerio.pimentel at freescale.com  Fri May 24 10:09:30 2013
From: rogerio.pimentel at freescale.com (Rogerio Pimentel)
Date: Fri, 24 May 2013 11:09:30 -0300
Subject: [PATCH v3 1/2] ARM:dts:mx53qsb: Add support for parallel display
Message-ID: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>

Add support for CLAA WVGA display for i.MX53 QSB.

Signed-off-by: Rogerio Pimentel <rogerio.pimentel at freescale.com>
---
Changes since V2:
Added status = "disabled" by default to avoid conflict with other
displays like HDMI card.
 arch/arm/boot/dts/imx53-qsb.dts |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/imx53.dtsi    |   35 +++++++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index a885d37..8509db3 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -21,6 +21,33 @@
 		reg = <0x70000000 0x40000000>;
 	};
 
+	display at di0 {
+		compatible = "fsl,imx-parallel-display";
+		crtcs = <&ipu 0>;
+		interface-pix-fmt = "rgb565";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ipu_disp0_1>;
+		status = "disabled";
+		display-timings {
+			claawvga {
+				native-mode;
+				clock-frequency = <27000000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <40>;
+				hfront-porch = <60>;
+				vback-porch = <10>;
+				vfront-porch = <10>;
+				hsync-len = <20>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 2dbdc90..3a565ff 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -544,6 +544,41 @@
 					};
 				};
 
+				ipu_disp0 {
+					pinctrl_ipu_disp0_1: ipudisp0grp-1 {
+						fsl,pins = <
+						MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK	0x5
+						MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		0x5
+						MX53_PAD_DI0_PIN2__IPU_DI0_PIN2		0x5
+						MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 		0x5
+						MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		0x5
+						MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		0x5
+						MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		0x5
+						MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		0x5
+						MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		0x5
+						MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		0x5
+						MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		0x5
+						MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		0x5
+						MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		0x5
+						MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		0x5
+						MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		0x5
+						MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		0x5
+						MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		0x5
+						MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		0x5
+						MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		0x5
+						MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		0x5
+						MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		0x5
+						MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		0x5
+						MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		0x5
+						MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		0x5
+						MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		0x5
+						MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		0x5
+						MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		0x5
+						MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		0x5
+						>;
+					};
+				};
+
 				ipu_disp1 {
 					pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 						fsl,pins = <
-- 
1.7.10.4




From rogerio.pimentel at freescale.com  Fri May 24 10:09:31 2013
From: rogerio.pimentel at freescale.com (Rogerio Pimentel)
Date: Fri, 24 May 2013 11:09:31 -0300
Subject: [PATCH v3 2/2] ARM:imx_v6_v7_defconfig: enable parallel display
In-Reply-To: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>
References: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>
Message-ID: <1369404571-21356-2-git-send-email-rogerio.pimentel@freescale.com>

Enable paralell display by default

Signed-off-by: Rogerio Pimentel <rogerio.pimentel at freescale.com>
---
Changes since V2:
CONFIG_OF_VIDEOMODE doesn't need to be added on defconfig
 arch/arm/configs/imx_v6_v7_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f..7085c7a 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -208,6 +208,8 @@ CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
+CONFIG_DRM_IMX_FB_HELPER=y
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
-- 
1.7.10.4




From mst at redhat.com  Fri May 24 10:17:47 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Fri, 24 May 2013 17:17:47 +0300
Subject: [PATCH v3 02/11] arm64: uaccess s/might_sleep/might_fault/
In-Reply-To: <cover.1368702323.git.mst@redhat.com>
References: <cover.1368702323.git.mst@redhat.com>
Message-ID: <1369404522-12927-2-git-send-email-mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/uaccess.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 008f848..edb3d5c 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -166,7 +166,7 @@ do {									\
 
 #define get_user(x, ptr)						\
 ({									\
-	might_sleep();							\
+	might_fault();							\
 	access_ok(VERIFY_READ, (ptr), sizeof(*(ptr))) ?			\
 		__get_user((x), (ptr)) :				\
 		((x) = 0, -EFAULT);					\
@@ -227,7 +227,7 @@ do {									\
 
 #define put_user(x, ptr)						\
 ({									\
-	might_sleep();							\
+	might_fault();							\
 	access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) ?		\
 		__put_user((x), (ptr)) :				\
 		-EFAULT;						\
-- 
MST


From mst at redhat.com  Fri May 24 10:17:32 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Fri, 24 May 2013 17:17:32 +0300
Subject: [PATCH v3 00/11] uaccess: better might_sleep/might_fault behavior
Message-ID: <cover.1368702323.git.mst@redhat.com>

This improves the might_fault annotations used
by uaccess routines:

1. The only reason uaccess routines might sleep
   is if they fault. Make this explicit for
   all architectures.
2. a voluntary preempt point in uaccess functions
   means compiler can't inline them efficiently,
   this breaks assumptions that they are very
   fast and small that e.g. net code seems to make.
   remove this preempt point so behaviour
   matches what callers assume.
3. Accesses (e.g through socket ops) to kernel memory
   with KERNEL_DS like net/sunrpc does will never sleep.
   Remove an unconditinal might_sleep in the inline
   might_fault in kernel.h
   (used when PROVE_LOCKING is not set).
4. Accesses with pagefault_disable return EFAULT
   but won't cause caller to sleep.
   Check for that and avoid might_sleep when
   PROVE_LOCKING is set.

I'd like these changes to go in for 3.11:
besides a general benefit of improved
consistency and performance, I would also like them
for the vhost driver where we want to call socket ops
under a spinlock, and fall back on slower thread handler
on error.

Please review, and consider for 3.11.

If the changes look good, would sched maintainers
please consider merging them through sched/core because of the
interaction with the scheduler?

Note on arch code updates:
I tested x86_64 code.
Other architectures were build-tested.
I don't have cross-build environment for arm64, tile, microblaze and
mn10300 architectures. arm64 and tile got acks.
The arch changes look generally safe enough
but would appreciate review/acks from arch maintainers.
core changes naturally need acks from sched maintainers.

Version 1 of this change was titled
	x86: uaccess s/might_sleep/might_fault/

Changes from v2:
	add a patch removing a colunatry preempt point
	in uaccess functions when PREEMPT_VOLUNATRY is set.
		Addresses comments by Arnd Bergmann,
		and Peter Zijlstra.
	comment on future possible simplifications in the git log
		for the powerpc patch. Addresses a comment
		by Arnd Bergmann.
	
Changes from v1:
	add more architectures
	fix might_fault() scheduling differently depending
	on CONFIG_PROVE_LOCKING, as suggested by Ingo

Michael S. Tsirkin (11):
  asm-generic: uaccess s/might_sleep/might_fault/
  arm64: uaccess s/might_sleep/might_fault/
  frv: uaccess s/might_sleep/might_fault/
  m32r: uaccess s/might_sleep/might_fault/
  microblaze: uaccess s/might_sleep/might_fault/
  mn10300: uaccess s/might_sleep/might_fault/
  powerpc: uaccess s/might_sleep/might_fault/
  tile: uaccess s/might_sleep/might_fault/
  x86: uaccess s/might_sleep/might_fault/
  kernel: drop voluntary schedule from might_fault
  kernel: uaccess in atomic with pagefault_disable

 arch/arm64/include/asm/uaccess.h      |  4 ++--
 arch/frv/include/asm/uaccess.h        |  4 ++--
 arch/m32r/include/asm/uaccess.h       | 12 ++++++------
 arch/microblaze/include/asm/uaccess.h |  6 +++---
 arch/mn10300/include/asm/uaccess.h    |  4 ++--
 arch/powerpc/include/asm/uaccess.h    | 16 ++++++++--------
 arch/tile/include/asm/uaccess.h       |  2 +-
 arch/x86/include/asm/uaccess_64.h     |  2 +-
 include/asm-generic/uaccess.h         | 10 +++++-----
 include/linux/kernel.h                |  7 ++-----
 mm/memory.c                           | 10 +++++++---
 11 files changed, 39 insertions(+), 38 deletions(-)

-- 
MST


From b.brezillon at overkiz.com  Fri May 24 10:29:02 2013
From: b.brezillon at overkiz.com (boris brezillon)
Date: Fri, 24 May 2013 16:29:02 +0200
Subject: [PATCH] ARM: at91/dt: add pinctrl definition for at91 tc blocks
In-Reply-To: <519F754F.50908@atmel.com>
References: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>
 <20130524140528.GE24476@game.jcrosoft.org> <519F754F.50908@atmel.com>
Message-ID: <519F792E.8090109@overkiz.com>

On 24/05/2013 16:12, Nicolas Ferre wrote:
> On 24/05/2013 16:05, Jean-Christophe PLAGNIOL-VILLARD :
>> On 12:05 Fri 24 May     , Boris BREZILLON wrote:
>>> Hello,
>>>
>>> This patch adds pinctrl configs for at91 Timer Conter blocks.
>>> These pin configs will be referenced by "atmel,tcb-pwm" devices to
>>> setup pins as PWM output.
>>
>> you need to rebase on
>>
>> a cleanup I did preset on our git tag at91-3.11-cleanup
>>
>> As we announce Mandaotory for 3.11
>>
>> as I introduce Macro fro DT
Ok, I'll base my future dt patches (kizbox.dts) on this tag.
>
> Boris, Hold on.
>
> I may have the solution for you. Give me some time and we may have the 
> automatic generation for updating your patch.
Ok, thanks.
>
> Bye,



From james.hogan at imgtec.com  Fri May 24 11:22:31 2013
From: james.hogan at imgtec.com (James Hogan)
Date: Fri, 24 May 2013 16:22:31 +0100
Subject: [PATCH v3] pinctrl: move subsystem mutex to pinctrl_dev struct
In-Reply-To: <1366988907-13485-1-git-send-email-linus.walleij@stericsson.com>
References: <1366988907-13485-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAAG0J990rqDdG5WdOrVGqZ9tFgJmnmP18S=c6o9JNygTLHS6=g@mail.gmail.com>

On 26 April 2013 16:08, Linus Walleij <linus.walleij at stericsson.com> wrote:
> @@ -608,7 +610,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
>         bool found = false;
>         unsigned long config;
>
> -       mutex_lock(&pinctrl_mutex);
> +       mutex_lock(&pctldev->mutex);
>
>         /* Parse the pinctrl map and look for the elected pin/state */
>         for_each_maps(maps_node, i, map) {

This change causes an oops on v3.10-rc2 when you read pinconf-config
because pctldev is initialised to NULL and not set until inside the
loop. I considered initialising pctldev to s->private, but I'm
concerned that if pctldev is altered in the loop it could end up
unlocking a different mutex to the one it locked. If this debugfs file
isn't meant to be specific to a pinctrl device should it be in the
root pinctrl directory instead of in each pinctrl device's directory?

Cheers
James


From florian.meier at koalo.de  Fri May 24 11:32:35 2013
From: florian.meier at koalo.de (Florian Meier)
Date: Fri, 24 May 2013 17:32:35 +0200
Subject: [PATCH] ASoC: Add support for BCM2708
In-Reply-To: <519CFFDD.4080203@metafoo.de>
References: <519CD1CC.8070507@koalo.de>
	<519CFFDD.4080203@metafoo.de>
Message-ID: <CABDT8WxS+Aq_feGqhzUMK-=DkZsnOULrH_fd+j0OP0czGnFdAw@mail.gmail.com>

2013/5/22 Lars-Peter Clausen <lars at metafoo.de>
>
> On 05/22/2013 04:10 PM, Florian Meier wrote:
> [...]
> > diff --git a/sound/soc/bcm2708/bcm2708-i2s.c b/sound/soc/bcm2708/bcm2708-i2s.c
> > new file mode 100644
> > index 0000000..a8e995f
> > --- /dev/null
> > +++ b/sound/soc/bcm2708/bcm2708-i2s.c
> > @@ -0,0 +1,964 @@
> [...]
> > +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
> > +                            struct snd_soc_dai *dai)
> > +{
> > +     struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
> > +
> > [...]
> > +             } else {
> > +                     snd_pcm_hw_constraint_minmax(substream->runtime,
> > +                                     SNDRV_PCM_HW_PARAM_RATE,
> > +                                     first_runtime->rate,
> > +                                     first_runtime->rate);
> > +             }
>
> Setting the symmetric_rates lets the core take care of setting the proper
> constraints on the rate. It probably makes sense to also add a
> symmetric_formats since this isn't the only driver that has the requirement
> that the formats for playback and capture match.


You are right! I forgot to remove this after I found the symmetric_rates flag.
For symmetric_formats I will have a closer look into the ALSA sources.



> [...]
> > diff --git a/sound/soc/bcm2708/bcm2708-pcm.c b/sound/soc/bcm2708/bcm2708-pcm.c
> > new file mode 100644
> > index 0000000..4b3e688
> > --- /dev/null
> > +++ b/sound/soc/bcm2708/bcm2708-pcm.c
> > @@ -0,0 +1,303 @@
>
> I think you should be able to remove the bulk of this driver by using the
> generic PCM dmaengine driver.


As implied in the header of this file, I would really like to use the
generic PCM dmaengine driver,
but I would also like to maintain compatibility to the Raspberry Pi
downstream kernel.
Therefore, I have to wait until the downstream kernel migrates to the
new version.



> [...]
> > +
> > +#include "bcm2708-pcm.h"
> > +
> > +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
> > +     .info                   = SNDRV_PCM_INFO_MMAP |
> > +                               SNDRV_PCM_INFO_MMAP_VALID |
> > +                               SNDRV_PCM_INFO_INTERLEAVED |
> > +                               SNDRV_PCM_INFO_PAUSE |
> > +                               SNDRV_PCM_INFO_RESUME |
> > +                               SNDRV_PCM_INFO_JOINT_DUPLEX |
> > +                               SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
>
> I don't think you actually support the last one, and neither pause and
> resume are supported.

I will have a closer look at these flags. Thanks!


From dinguyen at altera.com  Fri May 24 11:41:15 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Fri, 24 May 2013 10:41:15 -0500
Subject: [PATCHv4 1/6] ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Message-ID: <1369410080-436-1-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Moved "disabled" status to dtsi file
---
 arch/arm/boot/dts/socfpga.dtsi         |   18 ++++++++++++++++--
 arch/arm/boot/dts/socfpga_cyclone5.dts |   13 +++++++++++++
 arch/arm/boot/dts/socfpga_vt.dts       |    5 +++++
 3 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13..02bb425 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
 
 	aliases {
 		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		timer0 = &timer0;
@@ -238,13 +239,26 @@
 				};
 			};
 
-		gmac0: stmmac at ff700000 {
+		gmac0: ethernet at ff700000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff700000 0x2000>;
 			interrupts = <0 115 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			phy-mode = "gmii";
+			clocks = <&emac0_clk>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+		};
+
+		gmac1: ethernet at ff702000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+			reg = <0xff702000 0x2000>;
+			interrupts = <0 120 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+			clocks = <&emac1_clk>;
+			clock-names = "stmmaceth";
+			status = "disabled";
 		};
 
 		L2: l2-cache at fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958..973999d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
 	soc {
 		clkmgr at ffd04000 {
 			clocks {
@@ -41,6 +48,12 @@
 			};
 		};
 
+		ethernet at ff702000 {
+			phy-mode = "rgmii";
+			phy-addr = <0xffffffff>; /* probe for phy addr */
+			status = "okay";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d..d1ec0ca 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,11 @@
 			};
 		};
 
+		ethernet at ff700000 {
+			phy-mode = "gmii";
+			status = "okay";
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Fri May 24 11:41:19 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Fri, 24 May 2013 10:41:19 -0500
Subject: [PATCHv4 5/6] ARM: socfpga: dts: Add support for SD/MMC
In-Reply-To: <1369410080-436-1-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369410080-436-5-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for SD/MMC for SOCFPGA.
Add "syscon" to the "altr,sys-mgr" binding.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v2:
- Add "syscon" to "altr,sys-mgr"
- Remove pwr-en field
---
 .../devicetree/bindings/mmc/socfpga-dw-mshc.txt    |   60 ++++++++++++++++++++
 arch/arm/boot/dts/socfpga.dtsi                     |   13 ++++-
 arch/arm/boot/dts/socfpga_cyclone5.dts             |   13 +++++
 arch/arm/boot/dts/socfpga_vt.dts                   |   12 ++++
 4 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
new file mode 100644
index 0000000..9d7062c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
@@ -0,0 +1,60 @@
+* Altera SOCFPGA specific extensions to the Synopsis Designware Mobile
+  Storage Host Controller
+
+Required Properties:
+
+* compatible: should be
+	- "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA
+	  specific extentions.
+
+* altr,dw-mshc-ciu-div: Specifies the divider value for the card interface
+  unit (ciu) clock. The value should be (n-1). For Altera's SOCFPGA, the divider
+  value is fixed at 3, which mean parent_clock/4.
+
+* altr,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
+  in transmit mode and CIU clock phase shift value in receive mode for single
+  data rate mode operation. Refer notes below for the order of the cells and the
+  valid values.
+
+  Notes for the sdr-timing values:
+
+    The order of the cells should be
+      - First Cell: CIU clock phase shift value for RX mode, smplsel bits in
+	the system manager SDMMC control group.
+      - Second Cell: CIU clock phase shift value for TX mode, drvsel bits in
+	the system manager SDMMC control group.
+
+    Valid values for SDR CIU clock timing for SOCFPGA:
+      - valid value for tx phase shift and rx phase shift is 0 to 7.
+
+Required properties for a slot:
+
+* bus-width: Data width for card slot. 4-bit or 8-bit data.
+
+Example:
+
+  The MSHC controller node can be split into two portions, SoC specific and
+  board specific portions as listed below.
+
+	dwmmc0 at ff704000 {
+		compatible = "altr,socfpga-dw-mshc";
+		reg = <0xff704000 0x1000>;
+		interrupts = <0 139 4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc0 at ff704000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x400>;
+		altr,dw-mshc-ciu-div = <3>;
+      		altr,dw-mshc-sdr-timing = <0 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+		};
+	};
+
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index bee62a2..dbf7f22 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -468,6 +468,17 @@
 			cache-level = <2>;
 		};
 
+		mmc: dwmmc0 at ff704000 {
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0xff704000 0x1000>;
+			interrupts = <0 139 4>;
+			fifo-depth = <0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+			clock-names = "biu", "ciu";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
@@ -521,7 +532,7 @@
 			};
 
 		sysmgr at ffd08000 {
-				compatible = "altr,sys-mgr";
+				compatible = "altr,sys-mgr", "syscon";
 				reg = <0xffd08000 0x4000>;
 			};
 	};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 973999d..1853cb1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -54,6 +54,19 @@
 			status = "okay";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <3>;
+			altr,dw-mshc-sdr-timing = <0 3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0ca..d93deb0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -46,6 +46,18 @@
 			status = "okay";
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+			altr,dw-mshc-ciu-div = <3>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		timer0 at ffc08000 {
 			clock-frequency = <7000000>;
 		};
-- 
1.7.9.5




From dinguyen at altera.com  Fri May 24 11:41:18 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Fri, 24 May 2013 10:41:18 -0500
Subject: [PATCHv4 4/6] ARM: socfpga: Add syscon to be part of socfpga
In-Reply-To: <1369410080-436-1-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369410080-436-4-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

SOCFPGA has a system manager register block can be accessed by using
the syscon driver.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Cc: <linux at arm.linux.org.uk>
---
 arch/arm/mach-socfpga/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 566e804..07dff6f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -13,5 +13,6 @@ config ARCH_SOCFPGA
 	select GPIO_PL061 if GPIOLIB
 	select HAVE_ARM_SCU
 	select HAVE_SMP
+	select MFD_SYSCON
 	select SPARSE_IRQ
 	select USE_OF
-- 
1.7.9.5




From dinguyen at altera.com  Fri May 24 11:41:16 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Fri, 24 May 2013 10:41:16 -0500
Subject: [PATCHv4 2/6] ARM: socfpga: dts: Add gate-clock bindings
In-Reply-To: <1369410080-436-1-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369410080-436-2-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
the peripherals.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>
---
 .../devicetree/bindings/clock/altr_socfpga.txt     |    7 +
 arch/arm/boot/dts/socfpga.dtsi                     |  199 ++++++++++++++++++++
 2 files changed, 206 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index bd0c841..0045433 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -9,6 +9,9 @@ Required properties:
 	"altr,socfpga-pll-clock" - for a PLL clock
 	"altr,socfpga-perip-clock" - The peripheral clock divided from the
 		PLL clock.
+	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
 	either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+        and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+        and width.
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 02bb425..bee62a2 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -95,6 +95,12 @@
 						compatible = "fixed-clock";
 					};
 
+					f2s_periph_ref_clk: f2s_periph_ref_clk {
+						#clock-cells = <0>;
+						compatible = "fixed-clock";
+						clock-frequency = <10000000>;
+					};
+
 					main_pll: main_pll {
 						#address-cells = <1>;
 						#size-cells = <0>;
@@ -236,6 +242,199 @@
 							reg = <0xD4>;
 						};
 					};
+
+				mpu_periph_clk: mpu_periph_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <4>;
+					};
+
+				mpu_l2_ram_clk: mpu_l2_ram_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mpuclk>;
+					fixed-divider = <2>;
+					};
+
+				l4_main_clk: l4_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					clk-gate = <0x60 0>;
+					};
+
+				l3_main_clk: l3_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					};
+
+				l3_mp_clk: l3_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 0 2>;
+					clk-gate = <0x60 1>;
+					};
+
+				l3_sp_clk: l3_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>;
+					div-reg = <0x64 2 2>;
+				};
+
+				l4_mp_clk: l4_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 4 3>;
+					clk-gate = <0x60 2>;
+					};
+
+				l4_sp_clk: l4_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&mainclk>, <&per_base_clk>;
+					div-reg = <0x64 7 3>;
+					clk-gate = <0x60 3>;
+					};
+
+				dbg_at_clk: dbg_at_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 0 2>;
+					clk-gate = <0x60 4>;
+					};
+
+				dbg_clk: dbg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x68 2 2>;
+					clk-gate = <0x60 5>;
+					};
+
+				dbg_trace_clk: dbg_trace_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					div-reg = <0x6C 0 3>;
+					clk-gate = <0x60 6>;
+					};
+
+				dbg_timer_clk: dbg_timer_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&dbg_base_clk>;
+					clk-gate = <0x60 7>;
+					};
+
+				cfg_clk: cfg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 8>;
+					};
+
+				s2f_user0_clk: s2f_user0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&cfg_s2f_usr0_clk>;
+					clk-gate = <0x60 9>;
+					};
+
+				emac_0_clk: emac_0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac0_clk>;
+					clk-gate = <0xa0 0>;
+					};
+
+				emac_1_clk: emac_1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&emac1_clk>;
+					clk-gate = <0xa0 1>;
+					};
+
+				usb_mp_clk: usb_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 2>;
+					div-reg = <0xa4 0 3>;
+					};
+
+				spi_m_clk: spi_m_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 3>;
+					div-reg = <0xa4 3 3>;
+					};
+
+				can0_clk: can0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 4>;
+					div-reg = <0xa4 6 3>;
+					};
+
+				can1_clk: can1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 5>;
+					div-reg = <0xa4 9 3>;
+					};
+
+				gpio_db_clk: gpio_db_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&per_base_clk>;
+					clk-gate = <0xa0 6>;
+					div-reg = <0xa8 0 24>;
+					};
+
+				s2f_user1_clk: s2f_user1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&s2f_usr1_clk>;
+					clk-gate = <0xa0 7>;
+					};
+
+				sdmmc_clk: sdmmc_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 8>;
+					};
+
+				nand_x_clk: nand_x_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 9>;
+					};
+
+				nand_clk: nand_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+					clk-gate = <0xa0 10>;
+					fixed-divider = <4>;
+					};
+
+				qspi_clk: qspi_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-gate-clk";
+					clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+					clk-gate = <0xa0 11>;
+					};
 				};
 			};
 
-- 
1.7.9.5




From dinguyen at altera.com  Fri May 24 11:41:17 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Fri, 24 May 2013 10:41:17 -0500
Subject: [PATCHv4 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1369410080-436-1-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369410080-436-3-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Reviewed-by: Pavel Machek <pavel at denx.de>
CC: Mike Turquette <mturquette at linaro.org>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
Cc: Pavel Machek <pavel at denx.de>
CC: <linux at arm.linux.org.uk>

v3:
- Addressed comments from Pavel

v2:
- Fix space/indent errors
- Add streq for strcmp == 0
---
 drivers/clk/socfpga/clk.c |  194 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 185 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315..5bb848c 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,15 +24,17 @@
 #include <linux/of.h>
 
 /* Clock Manager offsets */
-#define CLKMGR_CTRL    0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL	0x0
+#define CLKMGR_BYPASS	0x4
+#define CLKMGR_L4SRC	0x70
+#define CLKMGR_PERPLL_SRC	0xAC
 
 /* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS		(1<<0)
+#define SDRAMPLL_BYPASS		(1<<1)
+#define SDRAMPLL_SRC_BYPASS	(1<<2)
+#define PERPLL_BYPASS		(1<<3)
+#define PERPLL_SRC_BYPASS	(1<<4)
 
 #define SOCFPGA_PLL_BG_PWRDWN		0
 #define SOCFPGA_PLL_EXT_ENA		1
@@ -41,6 +43,17 @@
 #define SOCFPGA_PLL_DIVF_SHIFT	3
 #define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT	16
+#define SOCFGPA_MAX_PARENTS	3
+
+#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
+#define SOCFPGA_NAND_CLK		"nand_clk"
+#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
+#define SOCFPGA_MMC_CLK			"mmc_clk"
+#define SOCFPGA_DB_CLK			"gpio_db_clk"
+
+#define div_mask(width)	((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -49,6 +62,9 @@ struct socfpga_clk {
 	char *parent_name;
 	char *clk_name;
 	u32 fixed_div;
+	void __iomem *div_reg;
+	u32 width;	/* only valid if div_reg != 0 */
+	u32 shift;	/* only valid if div_reg != 0 */
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 
 	socfpga_clk->hw.hw.init = &init;
 
-	if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
-			strcmp(clk_name, "sdram_pll")) {
+	if (streq(clk_name, "main_pll") ||
+		streq(clk_name, "periph_pll") ||
+		streq(clk_name, "sdram_pll")) {
 		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
 		clk_pll_ops.enable = clk_gate_ops.enable;
 		clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 	return clk;
 }
 
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+	u32 l4_src;
+	u32 perpll_src;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		return l4_src &= 0x1;
+	}
+	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		return !!(l4_src & 2);
+	}
+
+	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+		return perpll_src &= 0x3;
+	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+			return (perpll_src >> 2) & 3;
+
+	/* QSPI clock */
+	return (perpll_src >> 4) & 3;
+
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+	u32 src_reg;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x1;
+		src_reg |= parent;
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x2;
+		src_reg |= (parent << 1);
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+			src_reg &= ~0x3;
+			src_reg |= parent;
+		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+			src_reg &= ~0xC;
+			src_reg |= (parent << 2);
+		} else {/* QSPI clock */
+			src_reg &= ~0x30;
+			src_reg |= (parent << 4);
+		}
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	}
+
+	return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+	u32 div = 1, val;
+
+	if (socfpgaclk->fixed_div)
+		div = socfpgaclk->fixed_div;
+	else if (socfpgaclk->div_reg) {
+		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+		val &= div_mask(socfpgaclk->width);
+		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+			div = val + 1;
+		else
+			div = (1 << val);
+	}
+
+	return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+	.recalc_rate = socfpga_clk_recalc_rate,
+	.get_parent = socfpga_clk_get_parent,
+	.set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 clk_gate[2];
+	u32 div_reg[3];
+	u32 fixed_div;
+	struct clk *clk;
+	struct socfpga_clk *socfpga_clk;
+	const char *clk_name = node->name;
+	const char *parent_name[SOCFGPA_MAX_PARENTS];
+	struct clk_init_data init;
+	int rc;
+	int i = 0;
+
+	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+	if (WARN_ON(!socfpga_clk))
+		return;
+
+	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+	if (rc)
+		clk_gate[0] = 0;
+
+	if (clk_gate[0]) {
+		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+		socfpga_clk->hw.bit_idx = clk_gate[1];
+
+		gateclk_ops.enable = clk_gate_ops.enable;
+		gateclk_ops.disable = clk_gate_ops.disable;
+	}
+
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		socfpga_clk->fixed_div = 0;
+	else
+		socfpga_clk->fixed_div = fixed_div;
+
+	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+	if (!rc) {
+		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+		socfpga_clk->shift = div_reg[1];
+		socfpga_clk->width = div_reg[2];
+	} else {
+		socfpga_clk->div_reg = 0;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+			of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	init.parent_names = parent_name;
+	init.num_parents = i;
+	socfpga_clk->hw.hw.init = &init;
+
+	clk = clk_register(NULL, &socfpga_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(socfpga_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(rc))
+		return;
+}
+
 static void __init socfpga_pll_init(struct device_node *node)
 {
 	socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
 
+static void __init socfpga_gate_init(struct device_node *node)
+{
+	socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
 void __init socfpga_init_clocks(void)
 {
 	struct clk *clk;
-- 
1.7.9.5




From dinguyen at altera.com  Fri May 24 11:41:20 2013
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Fri, 24 May 2013 10:41:20 -0500
Subject: [PATCHv4 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1369410080-436-1-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
Message-ID: <1369410080-436-6-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add platform specific functionality for the DW SD/MMC driver for
SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
can use this define.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
CC: Seungwon Jeon <tgih.jun at samsung.com>
CC: Jaehoon Chung <jh80.chung at samsung.com>
CC: Arnd Bergmann <arnd at arndb.de>
CC: Olof Johansson <olof at lixom.net>
CC: Pavel Machek <pavel at denx.de>
CC: linux-mmc at vger.kernel.org

v4:
- Fix up SYSMGR_SDMMC_CTRL_SET macro

v3:
- Addressed comments from Seugwon, Jaehoon, and Pavel
- Use clk_disable_unprepare/clk_prepare_enable

v2:
- Use syscon and regmap
- Avoid divide by zero
- Remove the need to set PWR_EN
---
 drivers/mmc/host/Kconfig          |    8 +++
 drivers/mmc/host/Makefile         |    1 +
 drivers/mmc/host/dw_mmc-exynos.c  |    2 -
 drivers/mmc/host/dw_mmc-socfpga.c |  138 +++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h         |    1 +
 5 files changed, 148 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9ab8f8d..1be2289 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -556,6 +556,14 @@ config MMC_DW_EXYNOS
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Exynos4 and Exynos5 SoC's.
 
+config MMC_DW_SOCFPGA
+	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
+	depends on MMC_DW
+	select MMC_DW_PLTFM
+	help
+	  This selects support for Altera SoCFPGA specific extensions to the
+	  Synopsys DesignWare Memory Card Interface driver.
+
 config MMC_DW_PCI
 	tristate "Synopsys Designware MCI support on PCI bus"
 	depends on MMC_DW && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cd32280..67718c1 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
 obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
 obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
 obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
+obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
 obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
 obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..866edef 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -31,8 +31,6 @@
 					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
 					SDMMC_CLKSEL_CCLK_DIVIDER(z))
 
-#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
-
 #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
 
diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
new file mode 100644
index 0000000..4c19fd8
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -0,0 +1,138 @@
+/*
+ * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver
+ *
+ *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Taken from dw_mmc-exynos.c
+ */
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
+#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
+	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
+/* SOCFPGA implementation specific driver private data */
+struct dw_mci_socfpga_priv_data {
+	u8	ciu_div; /* card interface unit divisor */
+	u32	hs_timing; /* bitmask for CIU clock phase shift */
+	struct regmap   *sysreg; /* regmap for system manager register */
+};
+
+static int dw_mci_socfpga_priv_init(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv;
+
+	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(host->dev, "mem alloc failed for private data\n");
+		return -ENOMEM;
+	}
+
+	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+	if (IS_ERR(priv->sysreg)) {
+		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+		return PTR_ERR(priv->sysreg);
+	}
+	host->priv = priv;
+
+	return 0;
+}
+
+static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	clk_disable_unprepare(host->ciu_clk);
+	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, priv->hs_timing);
+	clk_prepare_enable(host->ciu_clk);
+
+	host->bus_hz /= (priv->ciu_div + 1);
+	return 0;
+}
+
+static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+
+	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
+		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
+{
+	struct dw_mci_socfpga_priv_data *priv = host->priv;
+	struct device_node *np = host->dev->of_node;
+	u32 timing[2];
+	u32 div = 0;
+	int ret;
+
+	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
+	if (ret)
+		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
+	priv->ciu_div = div;
+
+	ret = of_property_read_u32_array(np,
+			"altr,dw-mshc-sdr-timing", timing, 2);
+	if (ret)
+		return ret;
+
+	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+	return 0;
+}
+
+static const struct dw_mci_drv_data socfpga_drv_data = {
+	.init			= dw_mci_socfpga_priv_init,
+	.setup_clock		= dw_mci_socfpga_setup_clock,
+	.prepare_command	= dw_mci_socfpga_prepare_command,
+	.parse_dt		= dw_mci_socfpga_parse_dt,
+};
+
+static const struct of_device_id dw_mci_socfpga_match[] = {
+	{ .compatible = "altr,socfpga-dw-mshc",
+			.data = &socfpga_drv_data, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
+
+int dw_mci_socfpga_probe(struct platform_device *pdev)
+{
+	const struct dw_mci_drv_data *drv_data;
+	const struct of_device_id *match;
+
+	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
+	drv_data = match->data;
+	return dw_mci_pltfm_register(pdev, drv_data);
+}
+
+static struct platform_driver dw_mci_socfpga_pltfm_driver = {
+	.probe		= dw_mci_socfpga_probe,
+	.remove		= __exit_p(dw_mci_pltfm_remove),
+	.driver		= {
+		.name		= "dwmmc_socfpga",
+		.of_match_table	= of_match_ptr(dw_mci_socfpga_match),
+		.pm		= &dw_mci_pltfm_pmops,
+	},
+};
+
+module_platform_driver(dw_mci_socfpga_pltfm_driver);
+
+MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:dwmmc-socfpga");
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0b74189..3700cb2 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
-- 
1.7.9.5




From nicolas.ferre at atmel.com  Fri May 24 11:42:31 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 May 2013 17:42:31 +0200
Subject: [GIT PULL] at91: fixes for 3.10 #2
Message-ID: <1369410151-7837-1-git-send-email-nicolas.ferre@atmel.com>

Arnd, Olof,

Second AT91 fixes pull-request for 3.10-rc. The PMC definition fix is the most
important of this batch.

Thanks, best regards,

The following changes since commit b7a8ca5173ef9aa55fa039d7c216426ff0b25a12:

  ARM: at91: rm9200 fix time support (2013-05-15 12:37:45 +0200)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-fixes

for you to fetch changes up to 144ea15e4fefbee14a7dcb05c7cd0822fda3ebf6:

  ARM: at91/sama5: fix incorrect PMC pcr div definition (2013-05-24 10:53:51 +0200)

----------------------------------------------------------------
One definition fix that can lead to mis-clock some
AT91 peripherals on SAMA5.
Two DT related fixes.

----------------------------------------------------------------
Boris BREZILLON (1):
      ARM: at91/dt: fix macb pinctrl_macb_rmii_mii_alt definition

Jean-Christophe PLAGNIOL-VILLARD (1):
      ARM: at91: at91sam9n12: move external irq declatation to DT

Josh Wu (1):
      ARM: at91/sama5: fix incorrect PMC pcr div definition

 arch/arm/boot/dts/at91sam9260.dtsi         | 2 +-
 arch/arm/boot/dts/at91sam9n12.dtsi         | 1 +
 arch/arm/mach-at91/at91sam9n12.c           | 6 ------
 arch/arm/mach-at91/include/mach/at91_pmc.h | 6 +++---
 4 files changed, 5 insertions(+), 10 deletions(-)

-- 
Nicolas Ferre


From javi.merino at arm.com  Fri May 24 11:43:56 2013
From: javi.merino at arm.com (Javi Merino)
Date: Fri, 24 May 2013 16:43:56 +0100
Subject: [PATCH] ARM: document the bigger pagetables needed for LPAE
Message-ID: <1369410236-22398-1-git-send-email-javi.merino@arm.com>

The Booting documentation assumes that the initial pagetables are
16KiB but since 1b6ba46 (ARM: LPAE: MMU setup for the 3-level page
table format) they are 20KiB for LPAE kernels.  Thus, the
recommendation to put atags or the dtb in the first 16KiB is wrong,
there's only 12KiB of space there in LPAE kernels, so update the
documentation accordingly.
---
 Documentation/arm/Booting |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting
index 0c1f475..f6f9cd8 100644
--- a/Documentation/arm/Booting
+++ b/Documentation/arm/Booting
@@ -105,7 +105,7 @@ The tagged list should be stored in system RAM.
 
 The tagged list must be placed in a region of memory where neither
 the kernel decompressor nor initrd 'bootp' program will overwrite
-it.  The recommended placement is in the first 16KiB of RAM.
+it.  The recommended placement is in the first 12KiB of RAM.
 
 4b. Setup the device tree
 -------------------------
@@ -120,7 +120,7 @@ tagged list.
 The boot loader must pass at a minimum the size and location of the
 system memory, and the root filesystem location.  The dtb must be
 placed in a region of memory where the kernel decompressor will not
-overwrite it.  The recommended placement is in the first 16KiB of RAM
+overwrite it.  The recommended placement is in the first 12KiB of RAM
 with the caveat that it may not be located at physical address 0 since
 the kernel interprets a value of 0 in r2 to mean neither a tagged list
 nor a dtb were passed.
@@ -137,8 +137,9 @@ then it is legal for the boot loader to call the zImage in flash
 directly.
 
 The zImage may also be placed in system RAM (at any location) and
-called there.  Note that the kernel uses 16K of RAM below the image
-to store page tables.  The recommended placement is 32KiB into RAM.
+called there.  Note that the kernel may use up to 20KiB of RAM below
+the image to store page tables.  The recommended placement is 32KiB
+into RAM.
 
 In either case, the following conditions must be met:
 
-- 
1.7.9.5




From swarren at wwwdotorg.org  Fri May 24 11:45:06 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 24 May 2013 09:45:06 -0600
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
In-Reply-To: <CACRpkdZieCmFnHCGUkv8EqcAtb3DA7dSZpimSdB4P81tZPJRoQ@mail.gmail.com>
References: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
 <519A8A57.9060007@wwwdotorg.org>
 <CACRpkdZieCmFnHCGUkv8EqcAtb3DA7dSZpimSdB4P81tZPJRoQ@mail.gmail.com>
Message-ID: <519F8B02.1080000@wwwdotorg.org>

On 05/24/2013 02:04 AM, Linus Walleij wrote:
> On Mon, May 20, 2013 at 10:40 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> 
>> This seems fine on the surface, but I do have one question:
>>
>> I think the pinctrl lock serves a couple of purposes:
>>
>> 1) Basic protection for accesses to the pinctrldev_list itself.
>>
>> This patch seems just fine w.r.t. this point.
>>
>> 2) Preventing pinctrl drivers from being unregistered (and their modules
>> unloaded) when some operation is being performed on/to them.
> 
> Prevention of module unloading of pin controllers has never
> been working properly, as there is no way to release the
> pinctrl handles taken by different drivers.
> 
> I think that is why most pin controller drivers are bool rather
> than tristate.

Once we get to multi-platform distro kernels, we will probably want all
the pinctrl drivers to be modules so only the correct one gets loaded
from an initrd. Hence, we'll want to move things to tristate rather than
away from it.

If we know the pinctrl subsystem doesn't yet work correctly with module
unloads, should we modify pinctrl_register() to simply take a lock on
the driver module and never drop it, so that we guarantee we don't try
to unload the module later? Or, is this effectively already in place?

In other words, I can accept that we know that we can't unload pinctrl
drivers, but given that, I think the kernel should make sure the user
/actually/ can't unload them.


From nicolas.ferre at atmel.com  Fri May 24 12:11:02 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 May 2013 18:11:02 +0200
Subject: [GIT PULL] at91: cleanup (pinctrl macros, defconfigs) for 3.11 #1
In-Reply-To: <1368799336-25226-1-git-send-email-nicolas.ferre@atmel.com>
References: <1368799336-25226-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <519F9116.8060109@atmel.com>

On 17/05/2013 16:02, Nicolas Ferre :
> Arnd, Olof,
>
> Here is the first AT91 cleanup pull-request for 3.11. I is dominated by a big
> update of DT files because of the move to macros in pinctrl. As we plan to
> make this "cleanup" series the base of all our work on AT91 for 3.11, we would
> like to see it appearing early in arm-soc and linux-next: this is why we send
> it to you right now.
>
> We have colected the Acked-by from Linus Walleij and we all think that it makes
> sense to merge this material through arm-soc tree:
> - is touches nearly nothing of pinctrl actual code (a header file)
> - all dtsi/dts modifications for 3.11 will need this as a codebase for avoiding
>    merging nightmare
>
> I hope that it is okay with you.
>
> Thanks, best regards,
>
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
>
>    Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
>
> are available in the git repository at:
>
>    git://github.com/at91linux/linux-at91.git tags/at91-cleanup

Arnd, Olof,

After having sent the second "fixes" pull-request to you, I want to warn 
you about merging conflicts concerning this "cleanup" pull-request for 3.11.

2 merging conflicts are appearing when placing the "cleanup" branch on 
top of the "fixes" material contained today in at91-fixes tag.
To address this, I have pushed a resolution branch on our usual git tree:

git://github.com/at91linux/linux-at91.git   at91-3.11-cleanup1+resolved

In case of any question, please let me know. If you want me to rebase 
the original tag that I've sent you, I can do it as well.

Thanks, best regards,

> for you to fetch changes up to b3f442b0eedbc20b5ce3f4a96530588d14901199:
>
>    ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)
>
> ----------------------------------------------------------------
> Big update with pinctrl by use of macros and
> header files. Increases readability and avoid
> typos.
> Update of AT91 defconfigs and merge of defconfigs for
> SoC look-alike:
> sam9260/9g20 and sam9261/9g10.
>
> ----------------------------------------------------------------
> Jean-Christophe PLAGNIOL-VILLARD (6):
>        ARM: at91: dt: use #include for all device trees
>        ARM: at91: dt: switch to standard GPIO flag defines.
>        ARM: at91: dt: add pinctrl pre-processor define
>        ARM: at91: dt: switch to pinctrl to pre-processor
>        ARM: at91: dt: switch to standard IRQ flag defines
>        ARM: at91: udpate defconfigs
>
>   arch/arm/boot/dts/aks-cdu.dts                      |  12 +-
>   arch/arm/boot/dts/animeo_ip.dts                    |  18 +-
>   arch/arm/boot/dts/at91-ariag25.dts                 |   6 +-
>   arch/arm/boot/dts/at91rm9200.dtsi                  | 207 ++++----
>   arch/arm/boot/dts/at91rm9200ek.dts                 |  10 +-
>   arch/arm/boot/dts/at91sam9260.dtsi                 | 215 ++++-----
>   arch/arm/boot/dts/at91sam9263.dtsi                 | 203 ++++----
>   arch/arm/boot/dts/at91sam9263ek.dts                |  24 +-
>   arch/arm/boot/dts/at91sam9g15.dtsi                 |   2 +-
>   arch/arm/boot/dts/at91sam9g15ek.dts                |   4 +-
>   arch/arm/boot/dts/at91sam9g20.dtsi                 |   2 +-
>   arch/arm/boot/dts/at91sam9g20ek.dts                |   6 +-
>   arch/arm/boot/dts/at91sam9g20ek_2mmc.dts           |  10 +-
>   arch/arm/boot/dts/at91sam9g20ek_common.dtsi        |  28 +-
>   arch/arm/boot/dts/at91sam9g25.dtsi                 |   2 +-
>   arch/arm/boot/dts/at91sam9g25ek.dts                |   4 +-
>   arch/arm/boot/dts/at91sam9g35.dtsi                 |   2 +-
>   arch/arm/boot/dts/at91sam9g35ek.dts                |   4 +-
>   arch/arm/boot/dts/at91sam9g45.dtsi                 | 213 ++++-----
>   arch/arm/boot/dts/at91sam9m10g45ek.dts             |  38 +-
>   arch/arm/boot/dts/at91sam9n12.dtsi                 | 141 +++---
>   arch/arm/boot/dts/at91sam9n12ek.dts                |  14 +-
>   arch/arm/boot/dts/at91sam9x25.dtsi                 |  22 +-
>   arch/arm/boot/dts/at91sam9x25ek.dts                |   4 +-
>   arch/arm/boot/dts/at91sam9x35.dtsi                 |   2 +-
>   arch/arm/boot/dts/at91sam9x35ek.dts                |   4 +-
>   arch/arm/boot/dts/at91sam9x5.dtsi                  | 279 +++++------
>   arch/arm/boot/dts/at91sam9x5cm.dtsi                |   8 +-
>   arch/arm/boot/dts/at91sam9x5ek.dtsi                |  14 +-
>   arch/arm/boot/dts/ethernut5.dts                    |   6 +-
>   arch/arm/boot/dts/evk-pro3.dts                     |   6 +-
>   arch/arm/boot/dts/ge863-pro3.dtsi                  |   2 +-
>   arch/arm/boot/dts/kizbox.dts                       |  16 +-
>   arch/arm/boot/dts/mpa1600.dts                      |   4 +-
>   arch/arm/boot/dts/pm9g45.dts                       |  22 +-
>   arch/arm/boot/dts/sama5d3.dtsi                     | 520 +++++++++++----------
>   arch/arm/boot/dts/sama5d31ek.dts                   |   6 +-
>   arch/arm/boot/dts/sama5d33ek.dts                   |   4 +-
>   arch/arm/boot/dts/sama5d34ek.dts                   |   6 +-
>   arch/arm/boot/dts/sama5d35ek.dts                   |   4 +-
>   arch/arm/boot/dts/sama5d3xcm.dtsi                  |   4 +-
>   arch/arm/boot/dts/sama5d3xdm.dtsi                  |   2 +-
>   arch/arm/boot/dts/sama5d3xmb.dtsi                  |  26 +-
>   arch/arm/boot/dts/tny_a9260.dts                    |   4 +-
>   arch/arm/boot/dts/tny_a9263.dts                    |   4 +-
>   arch/arm/boot/dts/tny_a9g20.dts                    |   4 +-
>   arch/arm/boot/dts/usb_a9260.dts                    |   4 +-
>   arch/arm/boot/dts/usb_a9260_common.dtsi            |   6 +-
>   arch/arm/boot/dts/usb_a9263.dts                    |   8 +-
>   arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi           |  22 +-
>   arch/arm/boot/dts/usb_a9g20.dts                    |   4 +-
>   arch/arm/configs/at91_dt_defconfig                 |  55 ++-
>   arch/arm/configs/at91rm9200_defconfig              | 218 ++-------
>   ...am9g20_defconfig => at91sam9260_9g20_defconfig} |  67 ++-
>   arch/arm/configs/at91sam9260_defconfig             |  91 ----
>   ...am9261_defconfig => at91sam9261_9g10_defconfig} |  19 +-
>   arch/arm/configs/at91sam9263_defconfig             |  39 +-
>   arch/arm/configs/at91sam9g45_defconfig             |  94 ++--
>   arch/arm/configs/sama5_defconfig                   |  35 +-
>   arch/arm/mach-at91/Kconfig.non_dt                  | 159 +++----
>   arch/arm/mach-at91/Makefile                        |   2 -
>   arch/arm/mach-at91/board-sam9261ek.c               |  28 +-
>   include/dt-bindings/pinctrl/at91.h                 |  35 ++
>   63 files changed, 1407 insertions(+), 1617 deletions(-)
>   rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
>   delete mode 100644 arch/arm/configs/at91sam9260_defconfig
>   rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)
>   create mode 100644 include/dt-bindings/pinctrl/at91.h
>


-- 
Nicolas Ferre


From srinivas.kandagatla at st.com  Fri May 24 12:06:38 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 24 May 2013 17:06:38 +0100
Subject: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs
In-Reply-To: <201305232344.11974.arnd@arndb.de>
References: <1368022187-1633-1-git-send-email-srinivas.kandagatla@st.com>
 <201305171636.49627.arnd@arndb.de> <519A1BBB.2070903@st.com>
 <201305232344.11974.arnd@arndb.de>
Message-ID: <519F900E.308@st.com>

On 23/05/13 22:44, Arnd Bergmann wrote:
Thankyou Arnd for extending this discussion.
> On Monday 20 May 2013, Srinivas KANDAGATLA wrote:
>> On 17/05/13 15:36, Arnd Bergmann wrote:
>>
>> On the other hand using device trees to describe the HW
>> configuration(sysconfs) made more sense and got rid of SOC specific
>> callbacks.
> 
> I'm sure it's possible to reduce the duplication without going all
> the way to describing every bit in DT.

Yes, I agree with you. I think just passing the offset information from
DT would enough in cases like Ethernet or USB where the sysconf
registers tend to be mostly standard. And the generic higher level
function should be able to do the rest.

>> I forget to mention a important point here, the protection is at bit
>> level for the sysconfs. Some of sysconfs have bits shared across IPs, so
>> protecting them while the IP is still using it is what we are trying to
>> achieve with sysconf-claim/release apis.
>> While it may be overkill, but In past it has found bugs and been helpful
>> with a meaning full debug output.
> 
> Can you give an example of something that is shared across multiple IPs?
> 
> Are those always done in the way that you have e.g. the ethernet pinctrl
> in the same register as the usb pinctrl, or could you have an ethernet
> pinctrl setting mixed together with the usb clock setting for instance?
> 
> If the hardware has been designed in a sensible way rather than just
> grown by randomly adding bits in open spaces, I would assume that it's
> possible to have high-level interfaces built around ranges of registers
> rather than arbitrary subsets of registers.

We have decided to go with using higher level functions as you
suggested, hopefully based on regmap with some helper functions on top
of it.

System configuration registers in the past used to very much shared
across IPs, However with the new chips they seems be mostly dedicated
registers for specific IP configurations.
As we have no plans to support very old chips, So I think I can move
this out bit level information from device tree and add a higher level
functions to be accessed by the drivers.

As an example the below sysconf register for a STi7105 chip(Very old
SOC) looks like:
SYSTEM_CONFIG7 Comms/Ethernet config control register

[31:28] RESERVED
[27] ENMII:
	1: MII mode 0: Reverse MII mode
[26:25] PHY_INTF_SELECT: Selects the type of Ethernet mode
	00: MII mode (Default)
	01: Reserved
	1x: Reserved
[23] GLOBAL_POWER_DOWN:
	1: Activate low power
[24] RESERVED
	0: Normal mode
[22] DAA_CONFIG_CTRL: DAA configuration control
[21] RESERVED
[20] MAC_SPEED_SEL:
	1: Indicates that the MAC is running at 100 Mbps speed
	0: Indicates that the MAC is running at 10 Mbps speed
[19] RESERVED
[18] RMII_MODE:
	1: RMII interface activated
	0: MII interface activated
[17] MIIM_DIO_SELECT:
	1: MIIM_DIO from external input, else from GMAC
	0: All MII pads in input mode
[16] ETHERNET_INTERFACE_ON:
	1: Ethernet on (pads enables controlled by MAC)
[15:13] RESERVED
[12] DAA_SERIAL_MODE: DAA serial interface mode select pin

[11] SC1_COND_VCC_ENABLE: Enables control of smart card VCC upon
bit in the PDES.
[10] SC_DETECT_VPP_POL:
	1: Output pin SC_NOT_SETVPP is inverted of PDES_SC_SETVPP
	0: Output pin SC_NOT_SETVPP is PDES_SC_SETVPP
[9] IRB_DATA_OUT_POL_OD: Selection of polarity of IRB output signal
routed as alternate function

...
...
Thanks,
srini

> 
> 	Arnd
> 
> 



From catalin.marinas at arm.com  Fri May 24 12:21:10 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 May 2013 17:21:10 +0100
Subject: [PATCH] ARM: document the bigger pagetables needed for LPAE
In-Reply-To: <1369410236-22398-1-git-send-email-javi.merino@arm.com>
References: <1369410236-22398-1-git-send-email-javi.merino@arm.com>
Message-ID: <20130524162109.GA22600@arm.com>

On Fri, May 24, 2013 at 04:43:56PM +0100, Javi Merino wrote:
> The Booting documentation assumes that the initial pagetables are
> 16KiB but since 1b6ba46 (ARM: LPAE: MMU setup for the 3-level page
> table format) they are 20KiB for LPAE kernels.  Thus, the
> recommendation to put atags or the dtb in the first 16KiB is wrong,
> there's only 12KiB of space there in LPAE kernels, so update the
> documentation accordingly.
> ---
>  Documentation/arm/Booting |    9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)

Missing Signed-off-by?

-- 
Catalin


From linux at arm.linux.org.uk  Fri May 24 12:40:56 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 17:40:56 +0100
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <20130524140322.GD24476@game.jcrosoft.org>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
 <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
 <20130524112029.GW18614@n2100.arm.linux.org.uk>
 <20130524140322.GD24476@game.jcrosoft.org>
Message-ID: <20130524164055.GA18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 04:03:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 12:20 Fri 24 May     , Russell King - ARM Linux wrote:
> > On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> > > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> > > code snippet to the internal SRAM, then jump to run this code, but fail
> > > to run.
> > 
> > And that is where your mistake is - you forgot that you're working with
> > a CPU with harvard caches which will require some cache maintanence
> > between copying the code and executing it.
> > 
> > You want to look at flush_icache_range() rather than making this memory
> > strongly ordered.
> 
> I understand your point but today we map a SRAM as MT_DEVICE

If you map SRAM as MT_DEVICE then you won't be able to execute code from
it.  It needs to be a normal memory mapping.


From jason at lakedaemon.net  Fri May 24 12:46:36 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 24 May 2013 12:46:36 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130523190140.GA4010@obsidianresearch.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <20130523190140.GA4010@obsidianresearch.com>
Message-ID: <20130524164636.GV31290@titan.lakedaemon.net>

On Thu, May 23, 2013 at 01:01:40PM -0600, Jason Gunthorpe wrote:
> On Thu, May 23, 2013 at 02:40:28PM -0400, Jason Cooper wrote:
> 
> > > But there is a larger problem here then just this one bit.
> > > 
> > > The PSC1 register must be set properly for the board layout, and today
> > > we rely on the bootloader to set it. In fact, even with Sebastian's
> > > change the ethernet port won't work without bootloader
> > > intervention. The PortReset bit should also be cleared by the driver
> > > (and it is only present on some variants of this IP block,
> > > apparently).
> > > 
> > > We know that some Marvell SOC's wack the ethernet registers when they
> > > clock gate, and the flip of Clk125Bypass is another symptom of this
> > > general problem.
> > > 
> > > So, long term, the PSC1 must be fully set by the driver, based on DT
> > > information describing the board (eg RGMII/MII/1000Base-X [SFP] Phy
> > > type), and the layout of this register seems to vary on a SOC by SOC
> > > basis.
> > > 
> > > Thus, I think it is appropriate to call this variant of the eth IP
> > > 'marvell,kirkwood-eth' which indicates that the register block follows
> > > the kirkwood manual and the PSC1 register specifically has the
> > > kirkwood layout.
> > 
> > Ok, so mv643xx_eth would match both "marvell,orion-eth" and
> > "marvell,kirkwood-eth", then write to PSC1 iff it sees a node matching
> > "marvell,kirkwood-eth".  I'm not too keen on that, however, the matching
> > of the machine doesn't look to good, either.
> 
> Why are you not keen on this? It seems like normal device driver
> practice, that is what the data field of of_device_id is typically
> used for..

I'm not keen on it because we don't have a document saying "All kirkwood
SoCs need PSC1 set to X after reset."  We know it, but have we tested
the 6282?

That being said, if "marvell,kirkwood-eth" is the best we can do for
now, I'm all for it.  I would just like to be reasonably certain that
the binding we are creating doesn't lock us into a difficult decision
later.

> There are more compatible strings than just kirkwood and orion in this
> driver, the whole TX_BW_CONTROL_OLD_LAYOUT/TX_BW_CONTROL_NEW_LAYOUT
> buisness (affecting PPC/MIPS) should also someday be captured with
> compatible strings rather than auto-detection too..

Agreed.

> > > The question is what other Marvell SOCs have the same PSC1 layout as
> > > kirkwood?
> > 
> > I think marvell,psc1_reset = <>; gives us the most flexibility in
> > accurately describing the hardware.
> 
> Agree, providing psc1_reset value is a good idea to setup the phy
> modes. If all 'orion' SOCs have the PSC1 value then we don't need the
> kirkwood differentiators, especially if things like the reset bit are
> in the same place.
> 
> The same trick Sebastian used to capture the mac address could be used
> to capture the PSC1 value from the bootloader.
> 
> Basically, I think any IP variants that have idential register layouts
> can share a compatible string, otherwise different layouts need
> different compatible strings, so the general format:
> 
>  compatible = "marvell,SOCNAME-eth", "marvell,<something>-eth";
> 
> Seems very sane to me. At least this way if we discover more changes
> then the driver can match on the SOCNAME compatible string to find
> them.

After glancing a LinusW's email, I'm thinking this isn't the correct
path.  I'll write more in my response to him.

thx,

Jason.


From jason at lakedaemon.net  Fri May 24 12:53:38 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 24 May 2013 12:53:38 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <519E9ADA.3040204@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <519E9ADA.3040204@gmail.com>
Message-ID: <20130524165338.GW31290@titan.lakedaemon.net>

On Fri, May 24, 2013 at 12:40:26AM +0200, Sebastian Hesselbarth wrote:
> On 05/23/2013 08:40 PM, Jason Cooper wrote:
> >On Thu, May 23, 2013 at 11:53:57AM -0600, Jason Gunthorpe wrote:
> >>On Thu, May 23, 2013 at 01:23:39PM -0400, Jason Cooper wrote:
> >>>Shouldn't it rather be
> >>>
> >>>	compatible = "marvell,kirkwood-eth", "marvell,orion-eth";
> >>
> >>Not sure about orion-eth?

Sorry, yep, one or the other.

> Jason, Jason,

For a second, I read this as "tsk tsk tsk..." ;-)

> sorry I didn't came back to this conversation earlier. I already
> reworked the patch to rely on
> of_device_is_compatible(.."marvell,kirkwood-eth"..). This is a
> kirkwood only thing as other Orions cannot do clock gating or
> retain critcal register content (Dove). I will stick with orion-eth
> for all other and maybe introduce new compatible strings (and new
> fixes) as soon as issues surface.

Okay, as I mentioned to Jason, I would like to test 6282 before we
settle on this path.  Other than that, I'm fine with it.

> >>>I'm inclined to go with of_machine_is_compatible() since the only
> >>>concrete difference we know is that the tweak is needed on kirkwood and
> >>>nowhere else.
> >>
> >>But there is a larger problem here then just this one bit.
> >>
> >>The PSC1 register must be set properly for the board layout, and today
> >>we rely on the bootloader to set it. In fact, even with Sebastian's
> >>change the ethernet port won't work without bootloader
> >>intervention. The PortReset bit should also be cleared by the driver
> >>(and it is only present on some variants of this IP block,
> >>apparently).
> 
> Actually, fixing modular scenarios is only for the sake of multiarch
> someday. I don't see the point in running current kernel without eth
> compiled in _on a NAS SoC_ ;)

Good point, but if the eth can be gated to save power, we shouldn't
limit the user's ability just because the SoC is primarily in NAS's.

thx,

Jason.


From andrew at lunn.ch  Fri May 24 12:53:15 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 24 May 2013 18:53:15 +0200
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130524164636.GV31290@titan.lakedaemon.net>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <20130523190140.GA4010@obsidianresearch.com>
 <20130524164636.GV31290@titan.lakedaemon.net>
Message-ID: <20130524165315.GX26249@lunn.ch>

> > Why are you not keen on this? It seems like normal device driver
> > practice, that is what the data field of of_device_id is typically
> > used for..
> 
> I'm not keen on it because we don't have a document saying "All kirkwood
> SoCs need PSC1 set to X after reset."  We know it, but have we tested
> the 6282?

6282 looses its MAC address, that much i know. I've no idea about
PSC1, but if its MAC address behaviour is the same as 6281, is expect
PSC1 is the same.

	Andrew


From linux at arm.linux.org.uk  Fri May 24 12:55:36 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 17:55:36 +0100
Subject: rmk is away
Message-ID: <20130524165536.GB18614@n2100.arm.linux.org.uk>

So, this weekend is a holiday weekend in the UK.

However, I will also be away next week.

What this will mean is that the nightly build system will be offline for
the duration I'm away, and it also means a *huge* pile of email on my
return.

I will _not_ be reading that email pile; I did that after I returned in
April, and it took a week (including weekends) solid of 14 hours a day
and effectively added that time to my absence, as I wasn't doing
*anything* at all other than reading email.

I'm *not* doing that again.  (I said that I wouldn't do it last time but
people whinged that it was a dereliction of my position - well this time,
tough, I'm doing what Linus et.al. do and drop their mailbox after
returning from a vacation.)

This is *not* negotiable.  The above is the quickest way for me to
"recover" from being away.

So, please hold off sending anything which you want a response from me on
until I return.

Let me repeat: I will _not_ be catching up with email.  Send stuff that
you want me to look at *after* Sunday 2nd June.  If you send it before,
I *will* ignore your email.  After all, it's only _four_ UK working days
away, surely you can wait four UK working days? :)


From plagnioj at jcrosoft.com  Fri May 24 12:52:54 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 18:52:54 +0200
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <20130524164055.GA18614@n2100.arm.linux.org.uk>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
 <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
 <20130524112029.GW18614@n2100.arm.linux.org.uk>
 <20130524140322.GD24476@game.jcrosoft.org>
 <20130524164055.GA18614@n2100.arm.linux.org.uk>
Message-ID: <20130524165254.GF24476@game.jcrosoft.org>

On 17:40 Fri 24 May     , Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 04:03:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 12:20 Fri 24 May     , Russell King - ARM Linux wrote:
> > > On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> > > > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> > > > code snippet to the internal SRAM, then jump to run this code, but fail
> > > > to run.
> > > 
> > > And that is where your mistake is - you forgot that you're working with
> > > a CPU with harvard caches which will require some cache maintanence
> > > between copying the code and executing it.
> > > 
> > > You want to look at flush_icache_range() rather than making this memory
> > > strongly ordered.
> > 
> > I understand your point but today we map a SRAM as MT_DEVICE
> 
> If you map SRAM as MT_DEVICE then you won't be able to execute code from
> it.  It needs to be a normal memory mapping.

Yeah that a bug on AT91, by luck it work on armv3/v4 with MT_DEVICE, I should
have spot it earlier when cleanning the at91 but did not

That's why Yang change the SRAM mapping as MT_MEMORY_SO

I agree the commit message need to be re-done

Best Regards,
J.


From linux at arm.linux.org.uk  Fri May 24 12:59:34 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 17:59:34 +0100
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <20130524165254.GF24476@game.jcrosoft.org>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
 <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
 <20130524112029.GW18614@n2100.arm.linux.org.uk>
 <20130524140322.GD24476@game.jcrosoft.org>
 <20130524164055.GA18614@n2100.arm.linux.org.uk>
 <20130524165254.GF24476@game.jcrosoft.org>
Message-ID: <20130524165934.GC18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 06:52:54PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:40 Fri 24 May     , Russell King - ARM Linux wrote:
> > On Fri, May 24, 2013 at 04:03:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 12:20 Fri 24 May     , Russell King - ARM Linux wrote:
> > > > On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> > > > > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> > > > > code snippet to the internal SRAM, then jump to run this code, but fail
> > > > > to run.
> > > > 
> > > > And that is where your mistake is - you forgot that you're working with
> > > > a CPU with harvard caches which will require some cache maintanence
> > > > between copying the code and executing it.
> > > > 
> > > > You want to look at flush_icache_range() rather than making this memory
> > > > strongly ordered.
> > > 
> > > I understand your point but today we map a SRAM as MT_DEVICE
> > 
> > If you map SRAM as MT_DEVICE then you won't be able to execute code from
> > it.  It needs to be a normal memory mapping.
> 
> Yeah that a bug on AT91, by luck it work on armv3/v4 with MT_DEVICE, I should
> have spot it earlier when cleanning the at91 but did not
> 
> That's why Yang change the SRAM mapping as MT_MEMORY_SO

I said "normal memory".  Strongly ordered is not "normal memory".


From jason at lakedaemon.net  Fri May 24 13:01:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 24 May 2013 13:01:25 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <CACRpkdbsicPkPAiaQCOg2mQF2Ce2dg_K=BKqqx=FCdAH7Y+QBg@mail.gmail.com>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <519E9ADA.3040204@gmail.com>
 <CACRpkdbsicPkPAiaQCOg2mQF2Ce2dg_K=BKqqx=FCdAH7Y+QBg@mail.gmail.com>
Message-ID: <20130524170125.GX31290@titan.lakedaemon.net>

On Fri, May 24, 2013 at 01:03:25PM +0200, Linus Walleij wrote:
> On Fri, May 24, 2013 at 12:40 AM, Sebastian Hesselbarth
> <sebastian.hesselbarth at gmail.com> wrote:
> > On 05/23/2013 08:40 PM, Jason Cooper wrote:
> 
> >> I think marvell,psc1_reset =<>; gives us the most flexibility in
> >> accurately describing the hardware.
> >
> >
> > IMHO using that is just another workaround for a broken driver. We
> > could hack the whole register setup in DT as it would still accurately
> > describe HW. Don't get me wrong, but I don't like it.
> >
> > Haven't checked how happy Linus Walleij is about pinctrl drivers with
> > reg values hacked in lately.
> 
> One of the things I've been ranting about lately is that Linux
> subsystem maintainers have become de-facto device tree
> standard commite chairs. :-(

This is the first I've heard this rant.  :(

To that end, I agree with you.  My frustration boiled down to trying to
predict the future, which is futile. :-P

For our scenario, once we can confirm our least popular kirkwood
variant, the 6282, behaves the same as we've seen so far, then
"marvell,kirkwood-eth" is fine by me.

> So to the actual question:
> 
> In general I think we need to draw a line and define what we
> mean with "describing the hardware" in a device tree.
> 
> We have some consensus:
> - <reg> properties to describe regsiter BASE offset in physical
>   memory and size.
> - Resources like IRQ, DMA channel, regulator, GPIO pin control
>   handles, are passed using <&ampersand> notation.
> 
> And so it goes on.
> 
> When it comes to defining different registers and their individual
> bits and the meaning of these and/or default values, I personally
> think that is making things harder for developers rather than
> simplifying things. I know that pinctrl-single is anyway doing this
> and I was talked into accepting it under circumstances where
> developers are being passed opaque machine-generated
> data that would otherwise be translated into unreadable header
> files littering the kernel.
> 
> For a coder it is definately better if the *driver* know these
> details, but whether that is possible seems to depend on things
> like hardware development process.

Agree.

> IMO: if you want to go down that road, what you really want is not
> ever more expressible device trees, but real open firmware,
> or ACPI or UEFI that can interpret and run bytecode as some
> "bios" for you. With DT coming from OF maybe this is a natural
> progression of things, but one has to realize when we reach the
> point where what we really want is a bios. Then your time is
> likely better spent with Tianocore or something than with the
> kernel.

shudder.  I like embedded systems because the *don't* have a bios.

thx,

Jason.


From jason at lakedaemon.net  Fri May 24 13:03:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 24 May 2013 13:03:35 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130524165315.GX26249@lunn.ch>
References: <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <20130523190140.GA4010@obsidianresearch.com>
 <20130524164636.GV31290@titan.lakedaemon.net>
 <20130524165315.GX26249@lunn.ch>
Message-ID: <20130524170335.GY31290@titan.lakedaemon.net>

On Fri, May 24, 2013 at 06:53:15PM +0200, Andrew Lunn wrote:
> > > Why are you not keen on this? It seems like normal device driver
> > > practice, that is what the data field of of_device_id is typically
> > > used for..
> > 
> > I'm not keen on it because we don't have a document saying "All kirkwood
> > SoCs need PSC1 set to X after reset."  We know it, but have we tested
> > the 6282?
> 
> 6282 looses its MAC address, that much i know. I've no idea about
> PSC1, but if its MAC address behaviour is the same as 6281, is expect
> PSC1 is the same.

Do you have a board set up for testing you could try Sebastian's
forthcoming series on (with "marvell,kirkwood-eth")?

thx,

Jason.


From arnd at arndb.de  Fri May 24 13:10:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 19:10:37 +0200
Subject: [PATCHv4 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1369410080-436-6-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <1369410080-436-6-git-send-email-dinguyen@altera.com>
Message-ID: <201305241910.37975.arnd@arndb.de>

On Friday 24 May 2013, dinguyen at altera.com wrote:
> 
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.

No objections to the patch, but you seem to be missing a  binding document,
which is mandatory to describe the properties you add.

It also seems odd to have this in the series for the ethernet driver.

	Arnd


From olof at lixom.net  Fri May 24 13:11:33 2013
From: olof at lixom.net (Olof Johansson)
Date: Fri, 24 May 2013 10:11:33 -0700
Subject: [GIT PULL] at91: fixes for 3.10 #2
In-Reply-To: <1369410151-7837-1-git-send-email-nicolas.ferre@atmel.com>
References: <1369410151-7837-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <CAOesGMjvKhVKZf9A70K7VzXikY902KVyKR==4ivnb-gxhyRCPQ@mail.gmail.com>

Hi,

I'll pull this for now, but...


> Jean-Christophe PLAGNIOL-VILLARD (1):
>       ARM: at91: at91sam9n12: move external irq declatation to DT

This one is not a fix. While OK this time, please stick to only
sending true fixes for 3.10 from here on out.


-Olof


From arnd at arndb.de  Fri May 24 13:12:53 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 19:12:53 +0200
Subject: [PATCHv4 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <201305241910.37975.arnd@arndb.de>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <1369410080-436-6-git-send-email-dinguyen@altera.com>
 <201305241910.37975.arnd@arndb.de>
Message-ID: <201305241912.53751.arnd@arndb.de>

On Friday 24 May 2013, Arnd Bergmann wrote:

> It also seems odd to have this in the series for the ethernet driver.

After I sent it I realized that your patches are actually for different
parts of the system, they were just all replies to the same first patch.

It's usually helpful to add a [PATCH 0/6] message that explains the
overall intention and who you expect to pick up the patches, to avoid
the confusion I had.

	Arnd


From linux at arm.linux.org.uk  Fri May 24 13:13:00 2013
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 May 2013 18:13:00 +0100
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130524170125.GX31290@titan.lakedaemon.net>
References: <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net> <519E9ADA.3040204@gmail.com>
 <CACRpkdbsicPkPAiaQCOg2mQF2Ce2dg_K=BKqqx=FCdAH7Y+QBg@mail.gmail.com>
 <20130524170125.GX31290@titan.lakedaemon.net>
Message-ID: <20130524171300.GD18614@n2100.arm.linux.org.uk>

On Fri, May 24, 2013 at 01:01:25PM -0400, Jason Cooper wrote:
> On Fri, May 24, 2013 at 01:03:25PM +0200, Linus Walleij wrote:
> > IMO: if you want to go down that road, what you really want is not
> > ever more expressible device trees, but real open firmware,
> > or ACPI or UEFI that can interpret and run bytecode as some
> > "bios" for you. With DT coming from OF maybe this is a natural
> > progression of things, but one has to realize when we reach the
> > point where what we really want is a bios. Then your time is
> > likely better spent with Tianocore or something than with the
> > kernel.
> 
> shudder.  I like embedded systems because the *don't* have a bios.

Then you're into scenarios like I have with my laptop, where - those
of you who check the nightly build results will have noticed - one
of my serial ports doesn't always exist.  That's because the ACPI data
in the BIOS is *wrong*.  It reports that it has been enabled when it
hasn't, and the disassembled byte code is at fault here.

The fix?  God knows.  As far as I'm concerned as a user, or even as an
OS developer, it's unfixable without getting the ACPI data structures
changed, and that's not something I can do.

Do you really want that on ARM?  Given the fiasco with the location of
the registers, are you sure you want to place more trust in that
direction?  Does it give you a warm fuzzy feeling to know that you
might have to work out some way to patch vendor supplied bytecode?


From plagnioj at jcrosoft.com  Fri May 24 13:11:44 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 19:11:44 +0200
Subject: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
 "MT_MEMORY_SO"
In-Reply-To: <20130524165934.GC18614@n2100.arm.linux.org.uk>
References: <1369011911-21282-1-git-send-email-wenyou.yang@atmel.com>
 <1369011979-21354-1-git-send-email-wenyou.yang@atmel.com>
 <20130522001457.GA18614@n2100.arm.linux.org.uk>
 <B256D81BAE5131468A838E5D7A243641687BB93C@penmbx01>
 <20130524112029.GW18614@n2100.arm.linux.org.uk>
 <20130524140322.GD24476@game.jcrosoft.org>
 <20130524164055.GA18614@n2100.arm.linux.org.uk>
 <20130524165254.GF24476@game.jcrosoft.org>
 <20130524165934.GC18614@n2100.arm.linux.org.uk>
Message-ID: <20130524171144.GG24476@game.jcrosoft.org>

On 17:59 Fri 24 May     , Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 06:52:54PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 17:40 Fri 24 May     , Russell King - ARM Linux wrote:
> > > On Fri, May 24, 2013 at 04:03:22PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > On 12:20 Fri 24 May     , Russell King - ARM Linux wrote:
> > > > > On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> > > > > > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> > > > > > code snippet to the internal SRAM, then jump to run this code, but fail
> > > > > > to run.
> > > > > 
> > > > > And that is where your mistake is - you forgot that you're working with
> > > > > a CPU with harvard caches which will require some cache maintanence
> > > > > between copying the code and executing it.
> > > > > 
> > > > > You want to look at flush_icache_range() rather than making this memory
> > > > > strongly ordered.
> > > > 
> > > > I understand your point but today we map a SRAM as MT_DEVICE
> > > 
> > > If you map SRAM as MT_DEVICE then you won't be able to execute code from
> > > it.  It needs to be a normal memory mapping.
> > 
> > Yeah that a bug on AT91, by luck it work on armv3/v4 with MT_DEVICE, I should
> > have spot it earlier when cleanning the at91 but did not
> > 
> > That's why Yang change the SRAM mapping as MT_MEMORY_SO
> 
> I said "normal memory".  Strongly ordered is not "normal memory".

yeah btw why omap map their SRAM as strongly orderered?

Best Regards,
J.


From plagnioj at jcrosoft.com  Fri May 24 13:17:09 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 19:17:09 +0200
Subject: [GIT PULL] at91: fixes for 3.10 #2
In-Reply-To: <CAOesGMjvKhVKZf9A70K7VzXikY902KVyKR==4ivnb-gxhyRCPQ@mail.gmail.com>
References: <1369410151-7837-1-git-send-email-nicolas.ferre@atmel.com>
 <CAOesGMjvKhVKZf9A70K7VzXikY902KVyKR==4ivnb-gxhyRCPQ@mail.gmail.com>
Message-ID: <20130524171709.GH24476@game.jcrosoft.org>

On 10:11 Fri 24 May     , Olof Johansson wrote:
> Hi,
> 
> I'll pull this for now, but...
> 
> 
> > Jean-Christophe PLAGNIOL-VILLARD (1):
> >       ARM: at91: at91sam9n12: move external irq declatation to DT
> 
> This one is not a fix. While OK this time, please stick to only
> sending true fixes for 3.10 from here on out.

it's as you must specify them via DT, the C code is not event use in case of
DT
I should have put fix in the commit

Best Regards,
J.
> 
> 
> -Olof
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From plagnioj at jcrosoft.com  Fri May 24 13:19:24 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 19:19:24 +0200
Subject: FW: Linux 2.6.39.4 in a AT91SAM9M10G45-EK 10 Mbytes dma buffer
 allocatiion
In-Reply-To: <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>
References: <CDC4E028.D8BC%marcio@netopen.com.br>
 <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>
Message-ID: <20130524171924.GI24476@game.jcrosoft.org>

On 09:35 Fri 24 May     , Marcio Campos de Lima wrote:
> 
> 
> 
> 	
> Hi
> I am running Linux 2.6.39.4 in a AT91SAM9M10G45-EK platfarm. I need to
> allocate 10 Mbytes dma buffer to capture an image from a CMOS sensor. The
> board has 128Mbytes of total memory and 110 Mbytes of free memory. Can
> anybody help me?
> Thanks
> MArcio

10MiB? why that much?

you can not allowcate thar much on dma_alloc_coherent you need to use CMA

Best Regards,
J.
> 
> at mm/page_alloc.c:2033 __alloc_pages_nodemask+0x140/0x5f8)
> ht????? = 19Modules linked
> in:44;????????????????????????????????????????????? ?
> ????????????????????????????????????????????????????????????????????????????
> ?? ?
> fmt.fmt.pix.[] (unwind_backtrace+0x0/0xe4) from [] (warn_sl)
> pixelformat [] (warn_slowpath_common+0x4c/0x64) from [] (wa)
> =30314742;??????????????????????????????????????????????????????????????????
> ?? ?
> f[] (warn_slowpath_null+0x18/0x1c) from [] (__alloc_pages_n)
> mt.fmt.pix.fiel[] (__alloc_pages_nodemask+0x140/0x5f8) from [d?????? =
> c72b2[] (__dma_alloc+0x94/0x2d8) from [] (dma_all)
> cc8?????????????????????????????????????????????????????????????????????????
> ?? ?
> MARCIO[] (dma_alloc_coherent+0x54/0x60) from [] (vb2_dma_co)
> : init_mmap: i[] (vb2_dma_contig_alloc+0x38/0xb4) from [] ()
> nit?????????????????????????????????????????????????????????????????????????
> ?? ?
> [] (vb2_reqbufs+0x3b4/0x750) from [] (soc_camera_reqbufs+0x)
> [] (soc_camera_reqbufs+0xbc/0x134) from [] (__video_do_ioct)
> [] (__video_do_ioctl+0x1de0/0x4a24) from [] (video_usercopy)
> [] (video_usercopy+0x358/0x48c) from [] (v4l2_ioctl+0x68/0x)
> [] (v4l2_ioctl+0x68/0x114) from [] (vfs_ioctl+0x20/0x3c)?? ?
> [] (vfs_ioctl+0x20/0x3c) from [] (do_vfs_ioctl+0x520/0x578)?
> [] (do_vfs_ioctl+0x520/0x578) from [] (sys_ioctl+0x34/0x54)?
> [] (sys_ioctl+0x34/0x54) from [] (ret_fast_syscall+0x0/0x2c)
> ---[ end trace acfd933d374f6f12
> ]---?????????????????????????????????????????? ?
> atmel_isi atmel_isi.0: dma_alloc_coherent of size 10077696
> failed????????????? ?
> MARCIO: __vb2_queue_alloc
> ret=-12????????????????????????????????????????????? ?
> MARCIO: __vb2_queue_alloc
> q->num_buffers=0???????????????????????????????????? ?
> MARCIO: vb2_reqbufs req->count=2 ret=0
> num_buffers=1?????????????????????????? ?
> MARCIO: vb2_reqbufs req->count=2 num_buffers=1
> ret=0?????????????????????????? ?
> MARCIO:vb2_reqbufs soc_camera_reqbufs ret=-12 icd->vb2_vidq=1?
> p=1???????????? ?
> MARCIO:soc_camera_reqbufs
> ret=-12????????????????????????????????????????????? ?
> VIDIOC_REQBUFS error 12, Out of memory
> ?
> ?
> ?
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From sebastian.hesselbarth at gmail.com  Fri May 24 13:25:11 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 24 May 2013 19:25:11 +0200
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130524171300.GD18614@n2100.arm.linux.org.uk>
References: <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net> <519E9ADA.3040204@gmail.com>
 <CACRpkdbsicPkPAiaQCOg2mQF2Ce2dg_K=BKqqx=FCdAH7Y+QBg@mail.gmail.com>
 <20130524170125.GX31290@titan.lakedaemon.net>
 <20130524171300.GD18614@n2100.arm.linux.org.uk>
Message-ID: <519FA277.3010802@gmail.com>

On 05/24/2013 07:13 PM, Russell King - ARM Linux wrote:
> Do you really want that on ARM?  Given the fiasco with the location of
> the registers, are you sure you want to place more trust in that
> direction?  Does it give you a warm fuzzy feeling to know that you
> might have to work out some way to patch vendor supplied bytecode?

Don't get me wrong. I want mv643xx_eth DT or even platform_data to
evolve to a fully self configured driver not depending on proper u-boot
setup at all.

But I don't want to go that road now and I wonder if it might be safer
for us (and PPC guys) if we start mv643xx_eth over from scratch one day.

For this patch set, I want a basic DT binding that works. Patching the
driver to play with kirkwood loosing the MAC and other important
registers is not my main concern here. If clearing that one bit doesn't
help for all kirkwood boards, I'd rather leave the non-gating
workaround.

mv643xx_eth not knowing DT for ARM is stalling last important bits for
Orion SoCs. I want this to go in first as with David another maintainer
is involved.

Sebastian


From olof at lixom.net  Fri May 24 13:25:43 2013
From: olof at lixom.net (Olof Johansson)
Date: Fri, 24 May 2013 10:25:43 -0700
Subject: [GIT PULL] at91: fixes for 3.10 #2
In-Reply-To: <20130524171709.GH24476@game.jcrosoft.org>
References: <1369410151-7837-1-git-send-email-nicolas.ferre@atmel.com>
 <CAOesGMjvKhVKZf9A70K7VzXikY902KVyKR==4ivnb-gxhyRCPQ@mail.gmail.com>
 <20130524171709.GH24476@game.jcrosoft.org>
Message-ID: <CAOesGMjOaWardKRq-8BM_v8JKx+-Vgzg6XRRL5E1FQTut_ePdQ@mail.gmail.com>

On Fri, May 24, 2013 at 10:17 AM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:
> On 10:11 Fri 24 May     , Olof Johansson wrote:
>> Hi,
>>
>> I'll pull this for now, but...
>>
>>
>> > Jean-Christophe PLAGNIOL-VILLARD (1):
>> >       ARM: at91: at91sam9n12: move external irq declatation to DT
>>
>> This one is not a fix. While OK this time, please stick to only
>> sending true fixes for 3.10 from here on out.
>
> it's as you must specify them via DT, the C code is not event use in case of
> DT
> I should have put fix in the commit
>

I don't understand.


-Olof


From jgunthorpe at obsidianresearch.com  Fri May 24 13:33:06 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Fri, 24 May 2013 11:33:06 -0600
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <20130524164636.GV31290@titan.lakedaemon.net>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <20130523190140.GA4010@obsidianresearch.com>
 <20130524164636.GV31290@titan.lakedaemon.net>
Message-ID: <20130524173306.GA30022@obsidianresearch.com>

On Fri, May 24, 2013 at 12:46:36PM -0400, Jason Cooper wrote:

> > Why are you not keen on this? It seems like normal device driver
> > practice, that is what the data field of of_device_id is typically
> > used for..
> 
> I'm not keen on it because we don't have a document saying "All kirkwood
> SoCs need PSC1 set to X after reset."  We know it, but have we tested
> the 6282?

I disagree. The manul is very clear how PSC1 must be set for proper
operation. Clk125BypassEn bit is used only for loopback testing, it
should never set for driver operation. Similarly PortReset must be
cleared for driver operation.

It is always safe for the driver to clear these bits, if it knows they
are available.  In fact, I would argue the driver should always clear
these bits so that the bootloader isn't relied on to do it. It doesn't
matter if the SOC errantly sets the bit or not, it can *always* be
safely cleared.

Further, I compared my 88F6282/88F6283 manual against the public
88F6180/88F619x/88F6281 spec and confirmed that the PSC1 layout is the
same.

So all of these SOC's can share a driver compatible string.

AFAICT the only reason the driver doesn't touch PSC1 today is because
the PSC1 was introduced in a later IP revision and its presence isn't
auto-detectable.

The last bit of the puzzle to get bootloader independence on kirkwood
is to encode the phy interface type (GMII/RGMII/BASE-X) in the DT so
the entire PSC1 can be set by the driver..

Jason


From plagnioj at jcrosoft.com  Fri May 24 13:30:08 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 19:30:08 +0200
Subject: [GIT PULL] at91: fixes for 3.10 #2
In-Reply-To: <CAOesGMjOaWardKRq-8BM_v8JKx+-Vgzg6XRRL5E1FQTut_ePdQ@mail.gmail.com>
References: <1369410151-7837-1-git-send-email-nicolas.ferre@atmel.com>
 <CAOesGMjvKhVKZf9A70K7VzXikY902KVyKR==4ivnb-gxhyRCPQ@mail.gmail.com>
 <20130524171709.GH24476@game.jcrosoft.org>
 <CAOesGMjOaWardKRq-8BM_v8JKx+-Vgzg6XRRL5E1FQTut_ePdQ@mail.gmail.com>
Message-ID: <20130524173008.GJ24476@game.jcrosoft.org>

On 10:25 Fri 24 May     , Olof Johansson wrote:
> On Fri, May 24, 2013 at 10:17 AM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> > On 10:11 Fri 24 May     , Olof Johansson wrote:
> >> Hi,
> >>
> >> I'll pull this for now, but...
> >>
> >>
> >> > Jean-Christophe PLAGNIOL-VILLARD (1):
> >> >       ARM: at91: at91sam9n12: move external irq declatation to DT
> >>
> >> This one is not a fix. While OK this time, please stick to only
> >> sending true fixes for 3.10 from here on out.
> >
> > it's as you must specify them via DT, the C code is not event use in case of
> > DT
> > I should have put fix in the commit
> >
> 
> I don't understand.

for DT SoC you must use dt to descrive the external irq on at91 now
the sam9n12 (dt-only soc) was not converted when we did it

this commit fix it

Best Regards,
J.


From marcio.lima54 at gmail.com  Fri May 24 13:35:24 2013
From: marcio.lima54 at gmail.com (Marcio Lima)
Date: Fri, 24 May 2013 14:35:24 -0300
Subject: Linux 2.6.39.4 in a AT91SAM9M10G45-EK 10 Mbytes dma buffer
 allocatiion
In-Reply-To: <20130524171924.GI24476@game.jcrosoft.org>
References: <CDC4E028.D8BC%marcio@netopen.com.br>
 <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>
 <20130524171924.GI24476@game.jcrosoft.org>
Message-ID: <B4BA7F79-E9E2-426C-9E7B-06E95A7E533C@netopen.com.br>

Thanks Jean

the image takes 10 Mbytes to be stored!

Regards
Marcio

Enviado via iPhone

Em 24/05/2013, ?s 14:19, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> escreveu:

> On 09:35 Fri 24 May     , Marcio Campos de Lima wrote:
>> 
>> 
>> 
>>    
>> Hi
>> I am running Linux 2.6.39.4 in a AT91SAM9M10G45-EK platfarm. I need to
>> allocate 10 Mbytes dma buffer to capture an image from a CMOS sensor. The
>> board has 128Mbytes of total memory and 110 Mbytes of free memory. Can
>> anybody help me?
>> Thanks
>> MArcio
> 
> 10MiB? why that much?
> 
> you can not allowcate thar much on dma_alloc_coherent you need to use CMA
> 
> Best Regards,
> J.
>> 
>> at mm/page_alloc.c:2033 __alloc_pages_nodemask+0x140/0x5f8)
>> ht      = 19Modules linked
>> in:44;                                               
>>                                                                             
>>     
>> fmt.fmt.pix.[] (unwind_backtrace+0x0/0xe4) from [] (warn_sl)
>> pixelformat [] (warn_slowpath_common+0x4c/0x64) from [] (wa)
>> =30314742;                                                                  
>>     
>> f[] (warn_slowpath_null+0x18/0x1c) from [] (__alloc_pages_n)
>> mt.fmt.pix.fiel[] (__alloc_pages_nodemask+0x140/0x5f8) from [d       =
>> c72b2[] (__dma_alloc+0x94/0x2d8) from [] (dma_all)
>> cc8                                                                         
>>     
>> MARCIO[] (dma_alloc_coherent+0x54/0x60) from [] (vb2_dma_co)
>> : init_mmap: i[] (vb2_dma_contig_alloc+0x38/0xb4) from [] ()
>> nit                                                                         
>>     
>> [] (vb2_reqbufs+0x3b4/0x750) from [] (soc_camera_reqbufs+0x)
>> [] (soc_camera_reqbufs+0xbc/0x134) from [] (__video_do_ioct)
>> [] (__video_do_ioctl+0x1de0/0x4a24) from [] (video_usercopy)
>> [] (video_usercopy+0x358/0x48c) from [] (v4l2_ioctl+0x68/0x)
>> [] (v4l2_ioctl+0x68/0x114) from [] (vfs_ioctl+0x20/0x3c)    
>> [] (vfs_ioctl+0x20/0x3c) from [] (do_vfs_ioctl+0x520/0x578) 
>> [] (do_vfs_ioctl+0x520/0x578) from [] (sys_ioctl+0x34/0x54) 
>> [] (sys_ioctl+0x34/0x54) from [] (ret_fast_syscall+0x0/0x2c)
>> ---[ end trace acfd933d374f6f12
>> ]---                                            
>> atmel_isi atmel_isi.0: dma_alloc_coherent of size 10077696
>> failed               
>> MARCIO: __vb2_queue_alloc
>> ret=-12                                               
>> MARCIO: __vb2_queue_alloc
>> q->num_buffers=0                                      
>> MARCIO: vb2_reqbufs req->count=2 ret=0
>> num_buffers=1                            
>> MARCIO: vb2_reqbufs req->count=2 num_buffers=1
>> ret=0                            
>> MARCIO:vb2_reqbufs soc_camera_reqbufs ret=-12 icd->vb2_vidq=1 
>> p=1              
>> MARCIO:soc_camera_reqbufs
>> ret=-12                                               
>> VIDIOC_REQBUFS error 12, Out of memory
>>  
>>  
>>  
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From plagnioj at jcrosoft.com  Fri May 24 13:37:55 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 25 May 2013 01:37:55 +0800
Subject: Linux 2.6.39.4 in a AT91SAM9M10G45-EK 10 Mbytes dma buffer
 allocatiion
In-Reply-To: <B4BA7F79-E9E2-426C-9E7B-06E95A7E533C@netopen.com.br>
References: <CDC4E028.D8BC%marcio@netopen.com.br>
 <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>
 <20130524171924.GI24476@game.jcrosoft.org>
 <B4BA7F79-E9E2-426C-9E7B-06E95A7E533C@netopen.com.br>
Message-ID: <190868DC-2348-4CD4-8EED-92457B010368@jcrosoft.com>


On May 25, 2013, at 1:35 AM, Marcio Lima <marcio.lima54 at gmail.com> wrote:

> Thanks Jean
> 
> the image takes 10 Mbytes to be stored!

what sensor do you use?

4Mpx?

Best Regards,
J.
> 
> Regards
> Marcio
> 
> Enviado via iPhone
> 
> Em 24/05/2013, ?s 14:19, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> escreveu:
> 
>> On 09:35 Fri 24 May     , Marcio Campos de Lima wrote:
>>> 
>>> 
>>> 
>>> 
>>> Hi
>>> I am running Linux 2.6.39.4 in a AT91SAM9M10G45-EK platfarm. I need to
>>> allocate 10 Mbytes dma buffer to capture an image from a CMOS sensor. The
>>> board has 128Mbytes of total memory and 110 Mbytes of free memory. Can
>>> anybody help me?
>>> Thanks
>>> MArcio
>> 
>> 10MiB? why that much?
>> 
>> you can not allowcate thar much on dma_alloc_coherent you need to use CMA
>> 
>> Best Regards,
>> J.
>>> 
>>> at mm/page_alloc.c:2033 __alloc_pages_nodemask+0x140/0x5f8)
>>> ht      = 19Modules linked
>>> in:44;                                               
>>> 
>>> 
>>> fmt.fmt.pix.[] (unwind_backtrace+0x0/0xe4) from [] (warn_sl)
>>> pixelformat [] (warn_slowpath_common+0x4c/0x64) from [] (wa)
>>> =30314742;                                                                  
>>> 
>>> f[] (warn_slowpath_null+0x18/0x1c) from [] (__alloc_pages_n)
>>> mt.fmt.pix.fiel[] (__alloc_pages_nodemask+0x140/0x5f8) from [d       =
>>> c72b2[] (__dma_alloc+0x94/0x2d8) from [] (dma_all)
>>> cc8                                                                         
>>> 
>>> MARCIO[] (dma_alloc_coherent+0x54/0x60) from [] (vb2_dma_co)
>>> : init_mmap: i[] (vb2_dma_contig_alloc+0x38/0xb4) from [] ()
>>> nit                                                                         
>>> 
>>> [] (vb2_reqbufs+0x3b4/0x750) from [] (soc_camera_reqbufs+0x)
>>> [] (soc_camera_reqbufs+0xbc/0x134) from [] (__video_do_ioct)
>>> [] (__video_do_ioctl+0x1de0/0x4a24) from [] (video_usercopy)
>>> [] (video_usercopy+0x358/0x48c) from [] (v4l2_ioctl+0x68/0x)
>>> [] (v4l2_ioctl+0x68/0x114) from [] (vfs_ioctl+0x20/0x3c)    
>>> [] (vfs_ioctl+0x20/0x3c) from [] (do_vfs_ioctl+0x520/0x578) 
>>> [] (do_vfs_ioctl+0x520/0x578) from [] (sys_ioctl+0x34/0x54) 
>>> [] (sys_ioctl+0x34/0x54) from [] (ret_fast_syscall+0x0/0x2c)
>>> ---[ end trace acfd933d374f6f12
>>> ]---                                            
>>> atmel_isi atmel_isi.0: dma_alloc_coherent of size 10077696
>>> failed               
>>> MARCIO: __vb2_queue_alloc
>>> ret=-12                                               
>>> MARCIO: __vb2_queue_alloc
>>> q->num_buffers=0                                      
>>> MARCIO: vb2_reqbufs req->count=2 ret=0
>>> num_buffers=1                            
>>> MARCIO: vb2_reqbufs req->count=2 num_buffers=1
>>> ret=0                            
>>> MARCIO:vb2_reqbufs soc_camera_reqbufs ret=-12 icd->vb2_vidq=1 
>>> p=1              
>>> MARCIO:soc_camera_reqbufs
>>> ret=-12                                               
>>> VIDIOC_REQBUFS error 12, Out of memory
>>> 
>>> 
>>> 
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> 
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From marcio.lima54 at gmail.com  Fri May 24 13:39:10 2013
From: marcio.lima54 at gmail.com (Marcio)
Date: Fri, 24 May 2013 14:39:10 -0300
Subject: Linux 2.6.39.4 in a AT91SAM9M10G45-EK 10 Mbytes dma buffer
 allocatiion
In-Reply-To: <190868DC-2348-4CD4-8EED-92457B010368@jcrosoft.com>
References: <CDC4E028.D8BC%marcio@netopen.com.br>
 <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>
 <20130524171924.GI24476@game.jcrosoft.org>
 <B4BA7F79-E9E2-426C-9E7B-06E95A7E533C@netopen.com.br>
 <190868DC-2348-4CD4-8EED-92457B010368@jcrosoft.com>
Message-ID: <C90FD1E5-B04D-4F36-B4D3-CEF672C6239F@gmail.com>

Aptina MTP031

Enviado via iPhone

Em 24/05/2013, ?s 14:37, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> escreveu:

> 
> On May 25, 2013, at 1:35 AM, Marcio Lima <marcio.lima54 at gmail.com> wrote:
> 
>> Thanks Jean
>> 
>> the image takes 10 Mbytes to be stored!
> 
> what sensor do you use?
> 
> 4Mpx?
> 
> Best Regards,
> J.
>> 
>> Regards
>> Marcio
>> 
>> Enviado via iPhone
>> 
>> Em 24/05/2013, ?s 14:19, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> escreveu:
>> 
>>> On 09:35 Fri 24 May     , Marcio Campos de Lima wrote:
>>>> 
>>>> 
>>>> 
>>>> 
>>>> Hi
>>>> I am running Linux 2.6.39.4 in a AT91SAM9M10G45-EK platfarm. I need to
>>>> allocate 10 Mbytes dma buffer to capture an image from a CMOS sensor. The
>>>> board has 128Mbytes of total memory and 110 Mbytes of free memory. Can
>>>> anybody help me?
>>>> Thanks
>>>> MArcio
>>> 
>>> 10MiB? why that much?
>>> 
>>> you can not allowcate thar much on dma_alloc_coherent you need to use CMA
>>> 
>>> Best Regards,
>>> J.
>>>> 
>>>> at mm/page_alloc.c:2033 __alloc_pages_nodemask+0x140/0x5f8)
>>>> ht      = 19Modules linked
>>>> in:44;                                               
>>>> 
>>>> 
>>>> fmt.fmt.pix.[] (unwind_backtrace+0x0/0xe4) from [] (warn_sl)
>>>> pixelformat [] (warn_slowpath_common+0x4c/0x64) from [] (wa)
>>>> =30314742;                                                                  
>>>> 
>>>> f[] (warn_slowpath_null+0x18/0x1c) from [] (__alloc_pages_n)
>>>> mt.fmt.pix.fiel[] (__alloc_pages_nodemask+0x140/0x5f8) from [d       =
>>>> c72b2[] (__dma_alloc+0x94/0x2d8) from [] (dma_all)
>>>> cc8                                                                         
>>>> 
>>>> MARCIO[] (dma_alloc_coherent+0x54/0x60) from [] (vb2_dma_co)
>>>> : init_mmap: i[] (vb2_dma_contig_alloc+0x38/0xb4) from [] ()
>>>> nit                                                                         
>>>> 
>>>> [] (vb2_reqbufs+0x3b4/0x750) from [] (soc_camera_reqbufs+0x)
>>>> [] (soc_camera_reqbufs+0xbc/0x134) from [] (__video_do_ioct)
>>>> [] (__video_do_ioctl+0x1de0/0x4a24) from [] (video_usercopy)
>>>> [] (video_usercopy+0x358/0x48c) from [] (v4l2_ioctl+0x68/0x)
>>>> [] (v4l2_ioctl+0x68/0x114) from [] (vfs_ioctl+0x20/0x3c)    
>>>> [] (vfs_ioctl+0x20/0x3c) from [] (do_vfs_ioctl+0x520/0x578) 
>>>> [] (do_vfs_ioctl+0x520/0x578) from [] (sys_ioctl+0x34/0x54) 
>>>> [] (sys_ioctl+0x34/0x54) from [] (ret_fast_syscall+0x0/0x2c)
>>>> ---[ end trace acfd933d374f6f12
>>>> ]---                                            
>>>> atmel_isi atmel_isi.0: dma_alloc_coherent of size 10077696
>>>> failed               
>>>> MARCIO: __vb2_queue_alloc
>>>> ret=-12                                               
>>>> MARCIO: __vb2_queue_alloc
>>>> q->num_buffers=0                                      
>>>> MARCIO: vb2_reqbufs req->count=2 ret=0
>>>> num_buffers=1                            
>>>> MARCIO: vb2_reqbufs req->count=2 num_buffers=1
>>>> ret=0                            
>>>> MARCIO:vb2_reqbufs soc_camera_reqbufs ret=-12 icd->vb2_vidq=1 
>>>> p=1              
>>>> MARCIO:soc_camera_reqbufs
>>>> ret=-12                                               
>>>> VIDIOC_REQBUFS error 12, Out of memory
>>>> 
>>>> 
>>>> 
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel at lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>> 
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From plagnioj at jcrosoft.com  Fri May 24 13:38:44 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 19:38:44 +0200
Subject: Linux 2.6.39.4 in a AT91SAM9M10G45-EK 10 Mbytes dma buffer
 allocatiion
In-Reply-To: <C90FD1E5-B04D-4F36-B4D3-CEF672C6239F@gmail.com>
References: <CDC4E028.D8BC%marcio@netopen.com.br>
 <28C11E1EA5C742E9834AC24685367AB5@nete52c00369ab>
 <20130524171924.GI24476@game.jcrosoft.org>
 <B4BA7F79-E9E2-426C-9E7B-06E95A7E533C@netopen.com.br>
 <190868DC-2348-4CD4-8EED-92457B010368@jcrosoft.com>
 <C90FD1E5-B04D-4F36-B4D3-CEF672C6239F@gmail.com>
Message-ID: <20130524173844.GK24476@game.jcrosoft.org>

On 14:39 Fri 24 May     , Marcio wrote:
> Aptina MTP031
the 9g45 can only be use up to 4Mpx on ISI you use a 5Mpx censor

Best Regards,
J.
> 
> Enviado via iPhone
> 
> Em 24/05/2013, ?s 14:37, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> escreveu:
> 
> > 
> > On May 25, 2013, at 1:35 AM, Marcio Lima <marcio.lima54 at gmail.com> wrote:
> > 
> >> Thanks Jean
> >> 
> >> the image takes 10 Mbytes to be stored!
> > 
> > what sensor do you use?
> > 
> > 4Mpx?
> > 
> > Best Regards,
> > J.
> >> 
> >> Regards
> >> Marcio
> >> 
> >> Enviado via iPhone
> >> 
> >> Em 24/05/2013, ?s 14:19, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> escreveu:
> >> 
> >>> On 09:35 Fri 24 May     , Marcio Campos de Lima wrote:
> >>>> 
> >>>> 
> >>>> 
> >>>> 
> >>>> Hi
> >>>> I am running Linux 2.6.39.4 in a AT91SAM9M10G45-EK platfarm. I need to
> >>>> allocate 10 Mbytes dma buffer to capture an image from a CMOS sensor. The
> >>>> board has 128Mbytes of total memory and 110 Mbytes of free memory. Can
> >>>> anybody help me?
> >>>> Thanks
> >>>> MArcio
> >>> 
> >>> 10MiB? why that much?
> >>> 
> >>> you can not allowcate thar much on dma_alloc_coherent you need to use CMA
> >>> 
> >>> Best Regards,
> >>> J.
> >>>> 
> >>>> at mm/page_alloc.c:2033 __alloc_pages_nodemask+0x140/0x5f8)
> >>>> ht      = 19Modules linked
> >>>> in:44;                                               
> >>>> 
> >>>> 
> >>>> fmt.fmt.pix.[] (unwind_backtrace+0x0/0xe4) from [] (warn_sl)
> >>>> pixelformat [] (warn_slowpath_common+0x4c/0x64) from [] (wa)
> >>>> =30314742;                                                                  
> >>>> 
> >>>> f[] (warn_slowpath_null+0x18/0x1c) from [] (__alloc_pages_n)
> >>>> mt.fmt.pix.fiel[] (__alloc_pages_nodemask+0x140/0x5f8) from [d       =
> >>>> c72b2[] (__dma_alloc+0x94/0x2d8) from [] (dma_all)
> >>>> cc8                                                                         
> >>>> 
> >>>> MARCIO[] (dma_alloc_coherent+0x54/0x60) from [] (vb2_dma_co)
> >>>> : init_mmap: i[] (vb2_dma_contig_alloc+0x38/0xb4) from [] ()
> >>>> nit                                                                         
> >>>> 
> >>>> [] (vb2_reqbufs+0x3b4/0x750) from [] (soc_camera_reqbufs+0x)
> >>>> [] (soc_camera_reqbufs+0xbc/0x134) from [] (__video_do_ioct)
> >>>> [] (__video_do_ioctl+0x1de0/0x4a24) from [] (video_usercopy)
> >>>> [] (video_usercopy+0x358/0x48c) from [] (v4l2_ioctl+0x68/0x)
> >>>> [] (v4l2_ioctl+0x68/0x114) from [] (vfs_ioctl+0x20/0x3c)    
> >>>> [] (vfs_ioctl+0x20/0x3c) from [] (do_vfs_ioctl+0x520/0x578) 
> >>>> [] (do_vfs_ioctl+0x520/0x578) from [] (sys_ioctl+0x34/0x54) 
> >>>> [] (sys_ioctl+0x34/0x54) from [] (ret_fast_syscall+0x0/0x2c)
> >>>> ---[ end trace acfd933d374f6f12
> >>>> ]---                                            
> >>>> atmel_isi atmel_isi.0: dma_alloc_coherent of size 10077696
> >>>> failed               
> >>>> MARCIO: __vb2_queue_alloc
> >>>> ret=-12                                               
> >>>> MARCIO: __vb2_queue_alloc
> >>>> q->num_buffers=0                                      
> >>>> MARCIO: vb2_reqbufs req->count=2 ret=0
> >>>> num_buffers=1                            
> >>>> MARCIO: vb2_reqbufs req->count=2 num_buffers=1
> >>>> ret=0                            
> >>>> MARCIO:vb2_reqbufs soc_camera_reqbufs ret=-12 icd->vb2_vidq=1 
> >>>> p=1              
> >>>> MARCIO:soc_camera_reqbufs
> >>>> ret=-12                                               
> >>>> VIDIOC_REQBUFS error 12, Out of memory
> >>>> 
> >>>> 
> >>>> 
> >>>> _______________________________________________
> >>>> linux-arm-kernel mailing list
> >>>> linux-arm-kernel at lists.infradead.org
> >>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>> 
> >>> _______________________________________________
> >>> linux-arm-kernel mailing list
> >>> linux-arm-kernel at lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 


From Alison_Chaiken at mentor.com  Fri May 24 13:51:42 2013
From: Alison_Chaiken at mentor.com (Chaiken, Alison)
Date: Fri, 24 May 2013 17:51:42 +0000
Subject: [PATCH v3 5/6] ARM: dts: imx6dl: add pinctrls for WEIM NOR
In-Reply-To: <1369389564-13181-6-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>,
 <1369389564-13181-6-git-send-email-b32955@freescale.com>
Message-ID: <60BA5429A0E1584BA3633194F6F993B5025754D1@NA-MBX-03.mgc.mentorg.com>

Huang Shijie, sorry for not catching this earlier, but based on my reading of Table 4-1 of Rev. 1 of IMX6DQRM, I would use the following:

  pinctrl_weim_nor_1: weim_norgrp-2 {
                                               fsl,pins = <

[ . . . ]
                                                       /* data */
                                                       MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
                                                       MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
                                                       MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
                                                       MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
                                                       MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
                                                       MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
                                                       MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
                                                       MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
                                                       MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
                                                       MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
                                                       MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
                                                       MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
                                                       MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
                                                       MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
                                                       MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
                                                       MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0

[ .  .  . ]

                                               >;
                                       }; 

In your patch, the address lines are set to 0xb0b1, which is correct, as hysteresis is disabled and SRE is fast for those lines.     However, for data lines, hysteresis is enabled and SRE is slow, so the 0x1b0b0 setting is more appropriate.   

-- 
Alison Chaiken
Mentor Embedded Software Division
alison_chaiken at mentor.com



From dinguyen at altera.com  Fri May 24 14:03:08 2013
From: dinguyen at altera.com (Dinh Nguyen)
Date: Fri, 24 May 2013 13:03:08 -0500
Subject: [PATCHv4 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <201305241912.53751.arnd@arndb.de>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <1369410080-436-6-git-send-email-dinguyen@altera.com>
 <201305241910.37975.arnd@arndb.de> <201305241912.53751.arnd@arndb.de>
Message-ID: <1369418588.9717.0.camel@linux-builds1>

Hi Arnd,

On Fri, 2013-05-24 at 19:12 +0200, Arnd Bergmann wrote:
> On Friday 24 May 2013, Arnd Bergmann wrote:
> 
> > It also seems odd to have this in the series for the ethernet driver.
> 
> After I sent it I realized that your patches are actually for different
> parts of the system, they were just all replies to the same first patch.
> 
> It's usually helpful to add a [PATCH 0/6] message that explains the
> overall intention and who you expect to pick up the patches, to avoid
> the confusion I had.

I apologize for that. Will make sure to include a [PATCH 0/6] message in
the future.

Dinh
> 
> 	Arnd
> 





From dave.martin at linaro.org  Fri May 24 14:23:50 2013
From: dave.martin at linaro.org (Dave Martin)
Date: Fri, 24 May 2013 19:23:50 +0100
Subject: [PATCH 2/8] drivers/bus: arm-cci: function to enable CCI ports
 from early boot code
In-Reply-To: <1369374311-21260-3-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-3-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <20130524182350.GA2511@linaro.org>

On Fri, May 24, 2013 at 01:45:05AM -0400, Nicolas Pitre wrote:
> This provides cci_enable_port_for_self().  This is the counterpart to
> cci_disable_port_by_cpu(self).
> 
> This is meant to be called from the MCPM machine specific power_up_setup
> callback code when the appropriate affinity level needs to be initialized.
> The code therefore has to be position independent as the MMU is still off
> and it cannot rely on any stack space.

This seems a fair starting point.  There may be some aspects that can be
optimised later.

Reviewed-by: Dave Martin <dave.martin at linaro.org>

> Signed-off-by: Nicolas Pitre <nico at linaro.org>
> ---
>  drivers/bus/arm-cci.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 109 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> index ea81fa4a28..c6ae6e7193 100644
> --- a/drivers/bus/arm-cci.c
> +++ b/drivers/bus/arm-cci.c
> @@ -43,6 +43,7 @@ enum cci_ace_port_type {
>  
>  struct cci_ace_port {
>  	void __iomem *base;
> +	unsigned long phys;
>  	enum cci_ace_port_type type;
>  	struct device_node *dn;
>  };
> @@ -51,11 +52,13 @@ static struct cci_ace_port *ports;
>  static unsigned int nb_cci_ports;
>  
>  static void __iomem *cci_ctrl_base;
> +static unsigned long cci_ctrl_phys;
>  
>  struct cpu_port {
>  	u64 mpidr;
>  	u32 port;
>  };
> +
>  /*
>   * Use the port MSB as valid flag, shift can be made dynamic
>   * by computing number of bits required for port indexes.
> @@ -230,6 +233,98 @@ int notrace cci_disable_port_by_cpu(u64 mpidr)
>  EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
>  
>  /**
> + * cci_enable_port_for_self() - function to enable a CCI port for calling CPU
> + *
> + * Enabling a CCI port for the calling CPU implies enabling the CCI
> + * port controlling that CPU cluster. Code enabling CPU CCI ports
> + * must make sure that the CPU running the code is the first active
> + * CPU in the cluster and all other CPUs are quiescent in a low power
> + * state  or waiting for this CPU to complete the CCI initialization.
> + *
> + * Because this is called when the MMU is still off and with no stack,
> + * the code must be position independent and ideally rely on callee
> + * clobbered registers only.  To achieve this we must code this function
> + * entirely in assembler.
> + *
> + * Return:
> + *	0 on success
> + *	-ENODEV on port look-up failure
> + */
> +asmlinkage int __naked cci_enable_port_for_self(void)
> +{
> +	asm volatile ("\n"
> +
> +"	mrc	p15, 0, r0, c0, c0, 5	@ get MPIDR value \n"
> +"	and	r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
> +"	adr	r1, 5f \n"
> +"	ldr	r2, [r1] \n"
> +"	add	r1, r1, r2		@ &cpu_port \n"
> +"	add	ip, r1, %[sizeof_cpu_port] \n"
> +
> +	/* Loop over the cpu_port array looking for a matching MPIDR */
> +"1:	ldr	r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
> +"	cmp	r2, r0 			@ compare MPIDR \n"
> +"	bne	2f \n"
> +
> +	/* Found a match, now test port validity */
> +"	ldr	r3, [r1, %[offsetof_cpu_port_port]] \n"
> +"	tst	r3, #"__stringify(PORT_VALID)" \n"
> +"	bne	3f \n"
> +
> +	/* no match, loop with the next cpu_port entry */
> +"2:	add	r1, r1, %[sizeof_struct_cpu_port] \n"
> +"	cmp	r1, ip			@ done? \n"
> +"	blo	1b \n"
> +"	mov	r0, #"__stringify(-ENODEV)" \n"
> +"	bx	lr \n"
> +
> +	/* Use matched port index to look up the corresponding ports entry */
> +"3:	bic	r3, r3, #"__stringify(PORT_VALID)" \n"
> +"	adr	r0, 6f \n"
> +"	ldmia	r0, {r1, r2} \n"
> +"	sub	r1, r1, r0 		@ virt - phys \n"
> +"	ldr	r0, [r0, r2] 		@ *(&ports) \n"
> +"	mov	r2, %[sizeof_struct_ace_port] \n"
> +"	mla	r0, r2, r3, r0		@ &ports[index] \n"
> +"	sub	r0, r0, r1		@ virt_to_phys() \n"
> +
> +	/* Enable the CCI port */
> +"	ldr	r0, [r0, %[offsetof_port_phys]] \n"
> +"	mov	r3, #"__stringify(CCI_ENABLE_REQ)" \n"
> +"	str	r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
> +
> +	/* poll the status reg for completion */
> +"	adr	r1, 7f \n"
> +"	ldr	r0, [r1] \n"
> +"	ldr	r0, [r0, r1]		@ cci_ctrl_base \n"
> +"4:	ldr	r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
> +"	tst	r1, #1 \n"
> +"	bne	4b \n"
> +
> +"	mov	r0, #0 \n"
> +"	bx	lr \n"
> +
> +"	.align \n"
> +"5:	.word	cpu_port - . \n"
> +"6:	.word	. \n"
> +"	.word	ports - 6b \n"
> +"7:	.word	cci_ctrl_phys - . \n"
> +	: :
> +	[sizeof_cpu_port] "i" (sizeof(cpu_port)),
> +#ifndef __ARMEB__
> +	[offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
> +#else
> +	[offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
> +#endif
> +	[offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
> +	[sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
> +	[sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
> +	[offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
> +
> +	unreachable();
> +}
> +
> +/**
>   * __cci_control_port_by_device() - function to control a CCI port by device
>   *				    reference
>   *
> @@ -306,6 +401,7 @@ static int __init cci_probe(void)
>  	struct cci_nb_ports const *cci_config;
>  	int ret, i, nb_ace = 0, nb_ace_lite = 0;
>  	struct device_node *np, *cp;
> +	struct resource res;
>  	const char *match_str;
>  	bool is_ace;
>  
> @@ -323,9 +419,12 @@ static int __init cci_probe(void)
>  	if (!ports)
>  		return -ENOMEM;
>  
> -	cci_ctrl_base = of_iomap(np, 0);
> -
> -	if (!cci_ctrl_base) {
> +	ret = of_address_to_resource(np, 0, &res);
> +	if (!ret) {
> +		cci_ctrl_base = ioremap(res.start, resource_size(&res));
> +		cci_ctrl_phys =	res.start;
> +	}
> +	if (ret || !cci_ctrl_base) {
>  		WARN(1, "unable to ioremap CCI ctrl\n");
>  		ret = -ENXIO;
>  		goto memalloc_err;
> @@ -353,9 +452,12 @@ static int __init cci_probe(void)
>  			continue;
>  		}
>  
> -		ports[i].base = of_iomap(cp, 0);
> -
> -		if (!ports[i].base) {
> +		ret = of_address_to_resource(cp, 0, &res);
> +		if (!ret) {
> +			ports[i].base = ioremap(res.start, resource_size(&res));
> +			ports[i].phys = res.start;
> +		}	
> +		if (ret || !ports[i].base) {
>  			WARN(1, "unable to ioremap CCI port %d\n", i);
>  			continue;
>  		}
> @@ -382,6 +484,7 @@ static int __init cci_probe(void)
>  	 * cluster power-up/power-down. Make sure it reaches main memory.
>  	 */
>  	sync_cache_w(&cci_ctrl_base);
> +	sync_cache_w(&cci_ctrl_phys);
>  	sync_cache_w(&ports);
>  	sync_cache_w(&cpu_port);
>  	__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
> -- 
> 1.8.1.2
> 


From jason at lakedaemon.net  Fri May 24 14:33:10 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 24 May 2013 14:33:10 -0400
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130524183310.GA31290@titan.lakedaemon.net>

On Fri, May 24, 2013 at 11:44:37AM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> This series of patches has the goal of adding support for the Init
> button on OpenBlocks A6, but takes this opportunity to do a little bit
> of cleanup in the pinmux configurations of the various Kirkwood Device
> Trees.
> 
> Until now, all pinmux configurations were "owned" by the pinctrl
> driver, because back when they were introduced, the driver core was
> not selecting the pinmux configuration, each driver had to do it
> manually (and not all drivers were doing so). Now that the driver core
> selects the default pinmux configuration when available, it makes
> sense to associate the pinmux configuration to the particular device
> it is related to.
> 
> It allows pinctrl to show nice informations in debugfs, which
> associates a particular pin with the particular device using it:
> 
> # cat pinctrl/f1010000.pinctrl/pinmux-pins 
> Pinmux settings per pin
> Format: pin (name): mux_owner gpio_owner hog?
> pin 0 (PIN0): f4000000.nand (GPIO UNCLAIMED) function nand group mpp0
> pin 1 (PIN1): f4000000.nand (GPIO UNCLAIMED) function nand group mpp1
> pin 2 (PIN2): f4000000.nand (GPIO UNCLAIMED) function nand group mpp2
> pin 3 (PIN3): f4000000.nand (GPIO UNCLAIMED) function nand group mpp3
> pin 4 (PIN4): f4000000.nand (GPIO UNCLAIMED) function nand group mpp4
> pin 5 (PIN5): f4000000.nand (GPIO UNCLAIMED) function nand group mpp5
> pin 6 (PIN6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 7 (PIN7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 8 (PIN8): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp8
> pin 9 (PIN9): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp9
> pin 10 (PIN10): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp10
> pin 11 (PIN11): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp11
> pin 12 (PIN12): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 13 (PIN13): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp13
> pin 14 (PIN14): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp14
> pin 15 (PIN15): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp15
> pin 16 (PIN16): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp16
> pin 17 (PIN17): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 18 (PIN18): f4000000.nand (GPIO UNCLAIMED) function nand group mpp18
> pin 19 (PIN19): f4000000.nand (GPIO UNCLAIMED) function nand group mpp19
> pin 20 (PIN20): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp20
> pin 21 (PIN21): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp21
> pin 22 (PIN22): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp22
> pin 23 (PIN23): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp23
> pin 24 (PIN24): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp24
> pin 25 (PIN25): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp25
> pin 26 (PIN26): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp26
> pin 27 (PIN27): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp27
> pin 28 (PIN28): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp28
> pin 29 (PIN29): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp29
> pin 30 (PIN30): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp30
> pin 31 (PIN31): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp31
> pin 32 (PIN32): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 33 (PIN33): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 34 (PIN34): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 35 (PIN35): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 36 (PIN36): f1011100.i2c (GPIO UNCLAIMED) function twsi1 group mpp36
> pin 37 (PIN37): f1011100.i2c (GPIO UNCLAIMED) function twsi1 group mpp37
> pin 38 (PIN38): gpio_keys.2 mvebu-gpio:38 function gpio group mpp38
> pin 39 (PIN39): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 40 (PIN40): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
> pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
> pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43
> pin 44 (PIN44): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 45 (PIN45): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 46 (PIN46): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 47 (PIN47): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 48 (PIN48): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 49 (PIN49): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> 
> Without this patch set, all pins appear to be owned by
> "f1010000.pinctrl".
> 
> Even though GPIO muxing is automatically done when a device driver
> requests a GPIO, Andrew Lunn and I had agreed to make the pinmuxing
> explicit, in order to have correct informations in debugfs. See our
> discussion at
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-March/158190.html.
> 
> The last patch finally adds support for the init button of the
> Plathome OpenBlocks A6 platform.
> 
> Best regards,
> 
> Thomas
> 
> Thomas Petazzoni (21):
>   arm: kirkwood: cloudbox: affect pinmux configs to the right devices
>   arm: kirkwood: dlink dns: affect pinmux configs to the right devices
>   arm: kirkwood: dockstar: affect pinmux configs to the right devices
>   arm: kirkwood: dreamplug: affect pinmux configs to the right devices
>   arm: kirkwood: goflexnet: affect pinmux configs to the right devices
>   arm: kirkwood: guruplug: affect pinmux configs to the right devices
>   arm: kirkwood: ib62x0: affect pinmux configs to the right devices
>   arm: kirkwood: iconnect: give meaningful names to pinmux configs
>   arm: kirkwood: iconnect: affect pinmux configs to the right devices
>   arm: kirkwood: iomega ix2-200: affect pinmux configs to the right
>     devices
>   arm: kirkwood: ns2: affect pinmux configs to the right devices
>   arm: kirkwood: keymile: affect pinmux configs to the right devices
>   arm: kirkwood: buffalo linkstation: affect pinmux configs to the
>     right devices
>   arm: kirkwood: mplcec4: affect pinmux configs to the right devices
>   arm: kirkwood: readynas: affect pinmux configs to the right devices
>   arm: kirkwood: nsa310: affect pinmux configs to the right devices
>   arm: kirkwood: openblocks_a6: affect pinmux configs to the right
>     devices
>   arm: kirkwood: topkick: affect pinmux configs to the right devices
>   arm: kirkwood: ts219: affect pinmux configs to the right devices
>   arm: kirkwood: openblocks-a6: group pinmux configurations
>   arm: kirkwood: openblocks-a6: add support for Init button
> 
>  arch/arm/boot/dts/kirkwood-cloudbox.dts            |   10 +-
>  arch/arm/boot/dts/kirkwood-dns320.dts              |    7 ++
>  arch/arm/boot/dts/kirkwood-dns325.dts              |    5 +
>  arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   32 +++---
>  arch/arm/boot/dts/kirkwood-dockstar.dts            |    9 +-
>  arch/arm/boot/dts/kirkwood-dreamplug.dts           |   11 +-
>  arch/arm/boot/dts/kirkwood-goflexnet.dts           |   18 ++--
>  .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    8 +-
>  arch/arm/boot/dts/kirkwood-ib62x0.dts              |   17 +--
>  arch/arm/boot/dts/kirkwood-iconnect.dts            |   36 +++----
>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   15 +--
>  arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
>  arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |    6 +-
>  arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   22 ++--
>  arch/arm/boot/dts/kirkwood-mplcec4.dts             |   23 +++--
>  .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   22 ++--
>  arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   10 +-
>  arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
>  arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
>  arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
>  arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
>  arch/arm/boot/dts/kirkwood-nsa310.dts              |   29 +++---
>  arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |  108 ++++++--------------
>  arch/arm/boot/dts/kirkwood-topkick.dts             |   51 ++++-----
>  arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    8 +-
>  arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    8 +-
>  arch/arm/boot/dts/kirkwood-ts219.dtsi              |   10 ++
>  27 files changed, 235 insertions(+), 240 deletions(-)

Whole series applied to mvebu/dt with one small change, s/affect/move/
on the Subjects.

thx,

Jason.


From dmurphy at ti.com  Fri May 24 14:56:55 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 24 May 2013 13:56:55 -0500
Subject: [PATCH v6] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <5196580D.1070209@ti.com>
References: <1368806552-8851-1-git-send-email-dmurphy@ti.com>
 <20130517161525.GA30014@kahuna> <5196580D.1070209@ti.com>
Message-ID: <519FB7F7.7080009@ti.com>

On 05/17/2013 11:17 AM, Dan Murphy wrote:
> On 05/17/2013 11:15 AM, Nishanth Menon wrote:
>> On 11:02-20130517, Dan Murphy wrote:
>>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>>> are different.
>>>
>>> A1-A3 = gpio_wk7
>>> ES = gpio_110
>>>
>>> There is no change to LED D2
>>>
>>> Abstract away the pinmux and the LED definitions for the two boards into
>>> the respective DTS files.
>>>
>>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
>>> ---
>>> Changes in this version:
>>> 	- review comments incorporated.
>>> Previous version of this patch was discussed in:
>>> 	https://patchwork.kernel.org/patch/2582771/
>> one minor nit,
>> $subject could do with space after the ':'
>> otherwise, it looks fine to me. Will suggest waiting for further
>> reviewers if they have an opinion prior to a new rev.
> Thanks NM I will queue up this change locally and await further review prior to sending v7.
>
>>>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>>>  arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>>>  2 files changed, 43 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> index 03bd60d..5fd59b3 100644
>>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> @@ -16,8 +16,13 @@
>>>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>>>  	};
>>>  
>>> -	leds {
>>> +	leds: leds {
>>>  		compatible = "gpio-leds";
>>> +		pinctrl-names = "default";
>>> +		pinctrl-0 = <
>>> +			&led_wkgpio_pins
>>> +		>;
>>> +
>>>  		heartbeat {
>>>  			label = "pandaboard::status1";
>>>  			gpios = <&gpio1 7 0>;
>>> @@ -137,6 +142,15 @@
>>>  	};
>>>  };
>>>  
>>> +&omap4_pmx_wkup {
>>> +	led_wkgpio_pins: pinmux_leds_wkpins {
>>> +		pinctrl-single,pins = <
>>> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
>>> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>>> +		>;
>>> +	};
>>> +};
>>> +
>>>  &i2c1 {
>>>  	pinctrl-names = "default";
>>>  	pinctrl-0 = <&i2c1_pins>;
>>> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
>>> index f1d8c21..c968a3b 100644
>>> --- a/arch/arm/boot/dts/omap4-panda-es.dts
>>> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
>>> @@ -34,3 +34,31 @@
>>>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>>>  		>;
>>>  };
>>> +
>>> +&omap4_pmx_core {
>>> +	led_gpio_pins: gpio_led_pmx {
>>> +		pinctrl-single,pins = <
>>> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
>>> +		>;
>>> +	};
>>> +};
>>> +
>>> +&led_wkgpio_pins {
>>> +	pinctrl-single,pins = <
>>> +		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>>> +	>;
>>> +};
>>> +
>>> +&leds {
>>> +	pinctrl-0 = <
>>> +		&led_gpio_pins
>>> +		&led_wkgpio_pins
>>> +	>;
>>> +
>>> +	heartbeat {
>>> +		gpios = <&gpio4 14 0>;
>>> +	};
>>> +	mmc {
>>> +		gpios = <&gpio1 8 0>;
>>> +	};
>>> +};
>
Any additional comments besides the headline?

If not I will post v7

-- 
------------------
Dan Murphy



From arnd at arndb.de  Fri May 24 14:58:34 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 May 2013 20:58:34 +0200
Subject: [PATCHv4 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <1369418588.9717.0.camel@linux-builds1>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <201305241912.53751.arnd@arndb.de> <1369418588.9717.0.camel@linux-builds1>
Message-ID: <201305242058.34332.arnd@arndb.de>

On Friday 24 May 2013, Dinh Nguyen wrote:
> I apologize for that. Will make sure to include a [PATCH 0/6] message in
> the future.

No worries, I actually saw now that my only other comment was also
wrong, as you have the binding I was looking for in patch 5/6.

	Arnd


From khilman at linaro.org  Fri May 24 15:28:22 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 24 May 2013 12:28:22 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin and
 msecure line
Message-ID: <1369423702-31501-1-git-send-email-khilman@linaro.org>

Earlier commits ensured proper muxing of pins related to proper
TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
OMAP4: TWL: mux sys_drm_msecure as output for PMIC).

However these only fixed legacy boot and not DT boot.  For DT boot,
the default mux values need to be set properly in DT.

Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
Applies on v3.10-rc2

 arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
 arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..a7a9bc0 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -59,6 +59,7 @@
 &omap4_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
+			&twl6030_pins
 			&twl6040_pins
 			&mcpdm_pins
 			&mcbsp1_pins
@@ -66,6 +67,13 @@
 			&tpd12s015_pins
 	>;
 
+	twl6030_pins: pinmux_twl6030_pins {
+		pinctrl-single,pins = <
+			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
+		>;
+	};
+
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
 			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd..5ad0c10 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -145,6 +145,7 @@
 &omap4_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
+			&twl6030_pins
 			&twl6040_pins
 			&mcpdm_pins
 			&dmic_pins
@@ -179,6 +180,13 @@
 		>;
 	};
 
+	twl6030_pins: pinmux_twl6030_pins {
+		pinctrl-single,pins = <
+			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
+		>;
+	};
+
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
 			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-- 
1.8.2



From maxime.ripard at free-electrons.com  Fri May 24 15:53:52 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 21:53:52 +0200
Subject: Allwinner sunXi Fixes for 3.10
Message-ID: <20130524195352.GA19644@lukather>

Hi Arnd, Olof,

Please pull this small pull request with the sunxi fixes for 3.10

Thanks!
Maxime

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://github.com/mripard/linux.git sunxi/fixes-for-3.10

for you to fetch changes up to 19a280a61b520febab0f2fde94f4bd50250377b2:

  ARM: sunxi: select ARCH_REQUIRE_GPIOLIB (2013-05-15 09:42:47 +0200)

----------------------------------------------------------------
Small set of fixes for 3.10:
  - Fix build breakage in pinctrl driver when no other architecture is selected
  - Fix Mini X-plus device tree build

----------------------------------------------------------------
Maxime Ripard (2):
      ARM: sunxi: Fix Mini X-plus device tree build
      ARM: sunxi: select ARCH_REQUIRE_GPIOLIB

 arch/arm/boot/dts/Makefile                 | 4 +++-
 arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 4 ++--
 arch/arm/mach-sunxi/Kconfig                | 1 +
 3 files changed, 6 insertions(+), 3 deletions(-)

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From festevam at gmail.com  Fri May 24 15:55:41 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 24 May 2013 16:55:41 -0300
Subject: [PATCH 1/2] ARM: imx: irq-common: Include header to avoid sparse
 warning
Message-ID: <1369425342-20153-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Fix the following sparse warning:

arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'mxc_set_irq_fiq' was not declared. Should it be static?

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/irq-common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index 4b34f52..0a920d1 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -18,6 +18,7 @@
 
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "irq-common.h"
 
-- 
1.8.1.2



From festevam at gmail.com  Fri May 24 15:55:42 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 24 May 2013 16:55:42 -0300
Subject: [PATCH 2/2] ARM: imx: clk: No need to initialize phandle struct
In-Reply-To: <1369425342-20153-1-git-send-email-festevam@gmail.com>
References: <1369425342-20153-1-git-send-email-festevam@gmail.com>
Message-ID: <1369425342-20153-2-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

commit 84344b43c (ARM: i.MX5: Allow DT clock providers) introduce the following
sparse warning:

arch/arm/mach-imx/clk.c:12:43: warning: Using plain integer as NULL pointer

There is no need to initialize phandle, so remove it.

Cc: Martin Fuzzey <mfuzzey at parkeon.com>
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 53e8788..55bc80a 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -9,7 +9,7 @@ DEFINE_SPINLOCK(imx_ccm_lock);
 
 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
 {
-	struct of_phandle_args phandle = {0};
+	struct of_phandle_args phandle;
 	struct clk *clk = ERR_PTR(-ENODEV);
 	char *path;
 
-- 
1.8.1.2



From plagnioj at jcrosoft.com  Fri May 24 15:55:25 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 21:55:25 +0200
Subject: [PATCH v2 0/4] mtd: atmel_nand: enable Nand Flash Controller
 (NFC) support
In-Reply-To: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
Message-ID: <20130524195525.GL24476@game.jcrosoft.org>

On 17:51 Fri 17 May     , Josh Wu wrote:
> This patch series enable NFC support for SAMA5 soc. It can send command,
> address cycles automaticly. Also when enable NFC sram, NFC will transfer
> data to sram. Which can save lots of cpu time.

can you give some stats please

and performance comparaisan NFS vs DMA

Best Regards,
J.
> 
> v1 --> v2:
>  1) rebase it with latest l2-mtd git tree: 
>     - remove useless nand commands (NAND_CMD_DEPLETE1, NAND_CMD_STATUS_ERRORx).
>     - adopt to the new nand write function's parameters. Add error message when
>       handle subpage write via nfc sram.
>  2) rewrite pmecc_enable function. Now I use exist NAND_ECC_READ/WRITE const
>     instead of using a new enum definition.
> 
> Josh Wu (4):
>   mtd: atmel_nand: replace pmecc enable code with one function.
>   mtd: atmel_nand: add Nand Flash Controller (NFC) support
>   mtd: atmel_nand: enable Nand Flash Controller (NFC) read data via
>     sram
>   mtd: atmel_nand: enable Nand Flash Controller (NFC) write via sram
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         |    4 +
>  drivers/mtd/nand/atmel_nand.c                      |  657 ++++++++++++++++++--
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++
>  3 files changed, 718 insertions(+), 49 deletions(-)
>  create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h
> 
> -- 
> 1.7.9.5
> 


From nm at ti.com  Fri May 24 16:09:54 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 24 May 2013 15:09:54 -0500
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <1369423702-31501-1-git-send-email-khilman@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
Message-ID: <20130524200954.GA2344@kahuna>

On 12:28-20130524, Kevin Hilman wrote:
> Earlier commits ensured proper muxing of pins related to proper
> TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
> sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
> OMAP4: TWL: mux sys_drm_msecure as output for PMIC).
> 
> However these only fixed legacy boot and not DT boot.  For DT boot,
> the default mux values need to be set properly in DT.
> 
> Cc: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Kevin Hilman <khilman at linaro.org>
> ---
> Applies on v3.10-rc2
> 
>  arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
>  arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 03bd60d..a7a9bc0 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -59,6 +59,7 @@
>  &omap4_pmx_core {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <
> +			&twl6030_pins
>  			&twl6040_pins
>  			&mcpdm_pins
>  			&mcbsp1_pins
> @@ -66,6 +67,13 @@
>  			&tpd12s015_pins
>  	>;
>  
> +	twl6030_pins: pinmux_twl6030_pins {
> +		pinctrl-single,pins = <
> +			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
I can understand this - IRQ request comes here.
verified on OMAP4460 Panda-ES.
# omapconf read 0x4A10019C
4118011B

> +			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
I do not understand this.
OMAP4460 TRM:
Register: CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ
omapconf read 0x4A31E054
010F010F

I do not understand this configuration. mux modes for 
FREF_CLK0_OUT_MUXMODE:
0x0: Select fref_clk0_out
0x1: Select fref_clk1_req
0x2: Reserved
0x3: Select gpio_wk6
0x5: Select sdmmc2_dat7
0x6: Select hw_dbg6
0x7: Select safe_mode

Why are we setting mode 0(clk out) here?
> +		>;
> +	};
> +
>  	twl6040_pins: pinmux_twl6040_pins {
>  		pinctrl-single,pins = <
>  			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> index a35d9cd..5ad0c10 100644
> --- a/arch/arm/boot/dts/omap4-sdp.dts
> +++ b/arch/arm/boot/dts/omap4-sdp.dts
> @@ -145,6 +145,7 @@
>  &omap4_pmx_core {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <
> +			&twl6030_pins
>  			&twl6040_pins
>  			&mcpdm_pins
>  			&dmic_pins
> @@ -179,6 +180,13 @@
>  		>;
>  	};
>  
> +	twl6030_pins: pinmux_twl6030_pins {
> +		pinctrl-single,pins = <
> +			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
> +			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
> +		>;
> +	};
> +
>  	twl6040_pins: pinmux_twl6040_pins {
>  		pinctrl-single,pins = <
>  			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
> -- 
> 1.8.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Regards,
Nishanth Menon


From maxime.ripard at free-electrons.com  Fri May 24 16:10:30 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 22:10:30 +0200
Subject: [PATCHv3 1/6] net: Add EMAC ethernet driver found on Allwinner
 A10 SoC's
In-Reply-To: <519F6128.9060608@elopez.com.ar>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369387394-9453-2-git-send-email-maxime.ripard@free-electrons.com>
 <519F6128.9060608@elopez.com.ar>
Message-ID: <20130524201030.GA17847@lukather>

Hi Emilio,

On Fri, May 24, 2013 at 09:46:32AM -0300, Emilio L?pez wrote:
> El 24/05/13 06:23, Maxime Ripard escribi?:
> > From: Stefan Roese <sr at denx.de>
> > 
> > The Allwinner A10 has an ethernet controller that seem to be developped
> > internally by them.
> > 
> > The exact feature set of this controller is unknown, since there is no
> > public documentation for this IP, and this driver is mostly the one
> > published by Allwinner that has been heavily cleaned up.
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> > ---
> 
> (snip)
> 
> > +
> > +config SUN4I_EMAC
> > +        tristate "Allwinner A10 EMAC support"
> > +	depends on ARCH_SUNXI
> > +	depends on OF
> > +	select CRC32
> > +	select NET_CORE
> > +	select MII
> > +	select REGULATOR_FIXED_VOLTAGE
> > +        ---help---
> > +          Support for Allwinner A10 EMAC ethernet driver.
> > +
> > +          To compile this driver as a module, choose M here.  The module
> > +          will be called sun4i-emac.
> > +
> 
> You also need to select REGULATOR when you select REGULATOR_FIXED_VOLTAGE

Actually, this should be in patch 2/6.

Thanks for noticing!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From plagnioj at jcrosoft.com  Fri May 24 16:09:47 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 22:09:47 +0200
Subject: [PATCH v2 2/4] mtd: atmel_nand: add Nand Flash Controller
 (NFC) support
In-Reply-To: <1368784308-7600-3-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-3-git-send-email-josh.wu@atmel.com>
Message-ID: <20130524200947.GM24476@game.jcrosoft.org>

On 17:51 Fri 17 May     , Josh Wu wrote:
> Nand Flash Controller (NFC) can handle automatic transfers, sending the
> commands and address cycles to the NAND Flash.
> 
> To use NFC in this driver, the user needs to set the address and size of
> NFC command registers, NFC registers (embedded in HSMC) and NFC SRAM in dts.
> Also user need to set up the HSMC irq, which use to check whether nfc
> command is finish or not.
> 
> This driver has been tested on SAMA5D3X-EK board with JFFS2, YAFFS,
> UBIFS and mtd-utils.
> 
> I put the part of the mtd_speedtest result here for your information.
> From the mtd_speedtest, we can see the NFC will reduce the %50 of cpu load
> when writing nand flash. No change when reading.
> In the meantime, the speed will be slow about %8.
> 
> - commands use to test:
>     #insmod /mnt/mtd_speedtest.ko dev=2 &
>     #top -n 30 -d 1 | grep speedtest
> 
> - test result:
> 
> Before the patch:
> =================================================
> mtd_speedtest: MTD device: 2
> mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
>   515   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  99% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: eraseblock write speed is 5768 KiB/s
> mtd_speedtest: testing eraseblock read speed
>   515   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: eraseblock read speed is 5932 KiB/s
> mtd_speedtest: testing page write speed
>   515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: page write speed is 5770 KiB/s
> mtd_speedtest: testing page read speed
>   515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
>   515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: page read speed is 5910 KiB/s
> 
> After the patch:
> =================================================
> mtd_speedtest: MTD device: 2
> mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
> mtd_speedtest: testing eraseblock write speed
>   509   495 root     D     1164   0%  49% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: eraseblock write speed is 5370 KiB/s
> mtd_speedtest: testing eraseblock read speed
>   509   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     R     1164   0%  95% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: eraseblock read speed is 5715 KiB/s
> mtd_speedtest: testing page write speed
>   509   495 root     D     1164   0%  48% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: page write speed is 5224 KiB/s
> mtd_speedtest: testing page read speed
>   509   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: page read speed is 5641 KiB/s
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> ---
> v1 --> v2:
>   remove the useless nand commands: NAND_CMD_STATUS_ERRORx, NAND_CMD_DEPLETE1.
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         |    3 +
>  drivers/mtd/nand/atmel_nand.c                      |  373 ++++++++++++++++++--
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++++
>  3 files changed, 454 insertions(+), 28 deletions(-)
>  create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index d555421..88e3313 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -6,6 +6,8 @@ Required properties:
>  	and hardware ECC controller if available.
>  	If the hardware ECC is PMECC, it should contain address and size for
>  	PMECC, PMECC Error Location controller and ROM which has lookup tables.
> +	If hardware supports Nand Flash Controller, it should contain address and
> +	size for NFC command registers, NFC registers and NFC Sram.
>  - atmel,nand-addr-offset : offset for the address latch.
>  - atmel,nand-cmd-offset : offset for the command latch.
>  - #address-cells, #size-cells : Must be present if the device has sub-nodes
> @@ -29,6 +31,7 @@ Optional properties:
>    sector size 1024.
>  - nand-bus-width : 8 or 16 bus width if not present 8
>  - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
> +- atmel,has-nfc: boolean to enable Nand Flash Controller(NFC).

yes but you need to update the compatible or check the IP support it too
as has-nfc will mean I have the nfs on the hardware but not enable it

the SoC dtsi will describe you have it but the board will decide to enable it or
not
>  
>  Examples:
>  nand0: nand at 40000000,0 {
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index f747791..48d7ee6 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -18,6 +18,9 @@
>   *  Add Programmable Multibit ECC support for various AT91 SoC
>   *     ? Copyright 2012 ATMEL, Hong Xu
>   *
> + *  Add Nand Flash Controller support for SAMA5 SoC
> + *     ? Copyright 2013 ATMEL, Josh Wu (josh.wu at atmel.com)
> + *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
> @@ -37,9 +40,11 @@
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
>  
> +#include <linux/delay.h>
>  #include <linux/dmaengine.h>
>  #include <linux/gpio.h>
>  #include <linux/io.h>
> +#include <linux/interrupt.h>
>  #include <linux/platform_data/atmel.h>
>  #include <linux/pinctrl/consumer.h>
>  
> @@ -58,6 +63,7 @@ module_param(on_flash_bbt, int, 0);
>  	__raw_writel((value), add + ATMEL_ECC_##reg)
>  
>  #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
> +#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
>  
>  /* oob layout for large page size
>   * bad block info is on bytes 0 and 1
> @@ -85,6 +91,13 @@ static struct nand_ecclayout atmel_oobinfo_small = {
>  	},
>  };
>  
> +struct atmel_nfc {
> +	void __iomem		*base_cmd_regs;
> +	void __iomem		*hsmc_regs;
> +	void __iomem		*sram_bank0;
> +	dma_addr_t		sram_bank0_phys;
> +};
> +
>  struct atmel_nand_host {
>  	struct nand_chip	nand_chip;
>  	struct mtd_info		mtd;
> @@ -93,10 +106,15 @@ struct atmel_nand_host {
>  	struct atmel_nand_data	board;
>  	struct device		*dev;
>  	void __iomem		*ecc;
> +	int			irq;
>  
>  	struct completion	comp;
>  	struct dma_chan		*dma_chan;
>  
> +	bool			has_nfc;
> +	struct atmel_nfc	nfc;
> +	struct completion	comp_nfc;
> +
>  	bool			has_pmecc;
>  	u8			pmecc_corr_cap;
>  	u16			pmecc_sector_size;
> @@ -1357,6 +1375,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
>  	board->det_pin = of_get_gpio(np, 2);
>  
>  	host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
> +	host->has_nfc = of_property_read_bool(np, "atmel,has-nfc");
>  
>  	if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
>  		return 0;	/* Not using PMECC */
> @@ -1469,6 +1488,275 @@ static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
>  	return 0;
>  }
>  
> +/* SMC interrupt service routine */
> +static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
> +{
> +	struct atmel_nand_host *host = dev_id;
> +	u32 status, mask, pending;
> +	irqreturn_t ret = IRQ_NONE;
> +
> +	status = nfc_readl(host->nfc.hsmc_regs, SR);
> +	mask = nfc_readl(host->nfc.hsmc_regs, IMR);
> +	pending = status & mask;
> +
> +	if (pending & ATMEL_HSMC_NFC_XFR_DONE) {
> +		complete(&host->comp_nfc);
> +		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_XFR_DONE);
> +		ret = IRQ_HANDLED;
> +	} else if (pending & ATMEL_HSMC_NFC_RB_EDGE) {
> +		complete(&host->comp_nfc);
> +		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_RB_EDGE);
> +		ret = IRQ_HANDLED;
> +	} else if (pending & ATMEL_HSMC_NFC_CMD_DONE) {
> +		complete(&host->comp_nfc);
> +		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_CMD_DONE);
> +		ret = IRQ_HANDLED;
> +	}

	put esle ret = IRQ_NONE less code
> +
> +	return ret;
> +}
> +
> +/* NFC(Nand Flash Controller) related functions */
> +static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
> +{
> +	unsigned long timeout;
> +	init_completion(&host->comp_nfc);
> +
> +	/* Enable interrupt that need to wait for */
> +	nfc_writel(host->nfc.hsmc_regs, IER, flag);
> +
> +	timeout = wait_for_completion_timeout(&host->comp_nfc,
> +			msecs_to_jiffies(NFC_TIME_OUT_MS));
> +	if (timeout)
> +		return 0;
> +
> +	/* Time out to wait for the interrupt */
> +	dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
> +	return -ETIMEDOUT;
> +}
> +
> +static int nfc_send_command(struct atmel_nand_host *host,
> +	unsigned int cmd, unsigned int addr, unsigned char cycle0)
> +{
> +	unsigned long timeout;
> +	dev_dbg(host->dev,
> +		"nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
> +		cmd, addr, cycle0);
> +
> +	timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
> +	while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc.base_cmd_regs)
> +			& NFCADDR_CMD_NFCBUSY) {
> +		if (time_after(jiffies, timeout)) {
> +			dev_err(host->dev,
> +				"Time out to wait CMD_NFCBUSY ready!\n");
> +			break;
			already timeout you still neeed to wait DONE?
> +		}
> +	}
> +	nfc_writel(host->nfc.hsmc_regs, CYCLE0, cycle0);
> +	nfc_cmd_addr1234_writel(cmd, addr, host->nfc.base_cmd_regs);
> +	return nfc_wait_interrupt(host, ATMEL_HSMC_NFC_CMD_DONE);
> +}
> +
> +static int nfc_device_ready(struct mtd_info *mtd)
> +{
> +	struct nand_chip *nand_chip = mtd->priv;
> +	struct atmel_nand_host *host = nand_chip->priv;
> +	if (!nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE))
> +		return 1;
> +	return 0;
> +}
> +
> +static void nfc_select_chip(struct mtd_info *mtd, int chip)
> +{
> +	struct nand_chip *nand_chip = mtd->priv;
> +	struct atmel_nand_host *host = nand_chip->priv;
> +
> +	if (chip == -1)
> +		nfc_writel(host->nfc.hsmc_regs, CTRL, ATMEL_HSMC_NFC_DISABLE);
> +	else
> +		nfc_writel(host->nfc.hsmc_regs, CTRL, ATMEL_HSMC_NFC_ENABLE);
> +}
> +
> +static int nfc_init(struct platform_device *pdev, struct mtd_info *mtd)
> +{
> +	struct nand_chip *nand_chip = mtd->priv;
> +	struct atmel_nand_host *host = nand_chip->priv;
> +	struct atmel_nfc *nfc = &host->nfc;
> +	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
> +
> +	nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 4);
> +	if (!nfc_cmd_regs)
> +		return -EINVAL;
> +
> +	nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 5);
> +	if (!nfc_hsmc_regs)
> +		return -EINVAL;
> +
> +	nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 6);
> +	if (!nfc_sram)
> +		return -EINVAL;
> +
> +	nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
> +	if (IS_ERR(nfc->base_cmd_regs))
> +		return PTR_ERR(nfc->base_cmd_regs);
> +
> +	nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
> +	if (IS_ERR(nfc->hsmc_regs))
> +		return PTR_ERR(nfc->hsmc_regs);
> +
> +	nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
> +	if (IS_ERR(nfc->sram_bank0))
> +		return PTR_ERR(nfc->sram_bank0);
> +
> +	nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
> +
> +	dev_info(host->dev, "Using NFC\n");
> +	return 0;
> +}
> +
> +static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
> +		unsigned int *addr1234, unsigned int *cycle0)
> +{
> +	struct nand_chip *chip = mtd->priv;
> +
> +	int acycle = 0;
> +	unsigned char addr_bytes[8];
> +	int index = 0, bit_shift;
> +
> +	BUG_ON(addr1234 == NULL || cycle0 == NULL);
> +
> +	*cycle0 = 0;
> +	*addr1234 = 0;
> +
> +	if (column != -1) {
> +		if (chip->options & NAND_BUSWIDTH_16)
> +			column >>= 1;
> +		addr_bytes[acycle++] = column & 0xff;
> +		if (mtd->writesize > 512)
> +			addr_bytes[acycle++] = (column >> 8) & 0xff;
> +	}
> +
> +	if (page_addr != -1) {
> +		addr_bytes[acycle++] = page_addr & 0xff;
> +		addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
> +		if (chip->chipsize > (128 << 20))
> +			addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
> +	}
> +
> +	if (acycle > 4)
> +		*cycle0 = addr_bytes[index++];
> +
> +	for (bit_shift = 0; index < acycle; bit_shift += 8)
> +		*addr1234 += addr_bytes[index++] << bit_shift;
> +
> +	return acycle << 19;	/* return acycle in cmd register */
> +}
> +
> +static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
> +				int column, int page_addr)
> +{
> +	struct nand_chip *chip = mtd->priv;
> +	struct atmel_nand_host *host = chip->priv;
> +	unsigned long timeout;
> +	unsigned int nfc_addr_cmd = 0;
> +
> +	unsigned int cmd1 = command << 2;
> +
> +	/* Set default settings: no cmd2, no addr cycle. read from nand */
> +	unsigned int cmd2 = 0;
> +	unsigned int vcmd2 = 0;
> +	int acycle = NFCADDR_CMD_ACYCLE_NONE;
> +	int csid = NFCADDR_CMD_CSID_3;
> +	int dataen = NFCADDR_CMD_DATADIS;
> +	int nfcwr = NFCADDR_CMD_NFCRD;
> +	unsigned int addr1234 = 0;
> +	unsigned int cycle0 = 0;
> +	bool do_addr = true;
> +
> +	dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
> +	     __func__, command, column, page_addr);
> +
> +	switch (command) {
> +	case NAND_CMD_RESET:
> +		nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
> +		nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
> +		udelay(chip->chip_delay);
> +
> +		nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
> +		timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
> +		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
> +			if (time_after(jiffies, timeout)) {
> +				dev_err(host->dev,
> +					"Time out to wait status ready!\n");
> +				break;
> +			}
> +		}
> +		return;
> +	case NAND_CMD_STATUS:
> +		do_addr = false;
> +		break;
> +	case NAND_CMD_PARAM:
> +	case NAND_CMD_READID:
> +		do_addr = false;
> +		acycle = NFCADDR_CMD_ACYCLE_1;
> +		if (column != -1)
> +			addr1234 = column;
> +		break;
> +	case NAND_CMD_RNDOUT:
> +		cmd2 = NAND_CMD_RNDOUTSTART << 10;
> +		vcmd2 = NFCADDR_CMD_VCMD2;
> +		break;
> +	case NAND_CMD_READ0:
> +	case NAND_CMD_READOOB:
> +		if (command == NAND_CMD_READOOB) {
> +			column += mtd->writesize;
> +			command = NAND_CMD_READ0; /* only READ0 is valid */
> +			cmd1 = command << 2;
> +		}
> +
> +		cmd2 = NAND_CMD_READSTART << 10;
> +		vcmd2 = NFCADDR_CMD_VCMD2;
> +		break;
> +	/* For prgramming command, the cmd need set to write enable */
> +	case NAND_CMD_PAGEPROG:
> +	case NAND_CMD_SEQIN:
> +	case NAND_CMD_RNDIN:
> +		nfcwr = NFCADDR_CMD_NFCWR;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	if (do_addr)
> +		acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
> +				&cycle0);
> +
> +	nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
> +	nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
> +
> +	/*
> +	 * Program and erase have their own busy handlers status, sequential
> +	 * in, and deplete1 need no delay.
> +	 */
> +	switch (command) {
> +	case NAND_CMD_CACHEDPROG:
> +	case NAND_CMD_PAGEPROG:
> +	case NAND_CMD_ERASE1:
> +	case NAND_CMD_ERASE2:
> +	case NAND_CMD_RNDIN:
> +	case NAND_CMD_STATUS:
> +	case NAND_CMD_RNDOUT:
> +	case NAND_CMD_SEQIN:
> +	case NAND_CMD_READID:
> +		return;
> +
> +	case NAND_CMD_READ0:
> +		/* fall through */
> +	default:
> +		nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE);
> +	}
> +}
> +
>  /*
>   * Probe for the NAND device.
>   */
> @@ -1479,7 +1767,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>  	struct nand_chip *nand_chip;
>  	struct resource *mem;
>  	struct mtd_part_parser_data ppdata = {};
> -	int res;
> +	int res, irq;
>  	struct pinctrl *pinctrl;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -1523,7 +1811,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>  	/* Set address of NAND IO lines */
>  	nand_chip->IO_ADDR_R = host->io_base;
>  	nand_chip->IO_ADDR_W = host->io_base;
> -	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
>  
>  	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
>  	if (IS_ERR(pinctrl)) {
> @@ -1532,41 +1819,69 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>  		goto err_ecc_ioremap;
>  	}
>  
> -	if (gpio_is_valid(host->board.rdy_pin)) {
> -		res = gpio_request(host->board.rdy_pin, "nand_rdy");
> -		if (res < 0) {
> -			dev_err(&pdev->dev,
> -				"can't request rdy gpio %d\n",
> -				host->board.rdy_pin);
> +	if (host->has_nfc) {
		split in 2 function

		nfs_init
> +		res = nfc_init(pdev, mtd);
> +		if (res)
> +			goto err_ecc_ioremap;
> +		nand_chip->select_chip = nfc_select_chip;
> +		nand_chip->dev_ready = nfc_device_ready;
> +		nand_chip->cmdfunc = nfc_nand_command;
> +
> +		/* Initialize the interrupt for NFC */
> +		irq = platform_get_irq(pdev, 0);
> +		if (irq < 0) {
> +			dev_err(host->dev, "Cannot get HSMC irq!\n");
>  			goto err_ecc_ioremap;
>  		}
>  
> -		res = gpio_direction_input(host->board.rdy_pin);
> -		if (res < 0) {
> -			dev_err(&pdev->dev,
> -				"can't request input direction rdy gpio %d\n",
> -				host->board.rdy_pin);
> +		res = request_irq(irq, hsmc_interrupt, 0, "hsmc", host);
		devm_request_irq
> +		if (res) {
> +			dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
> +				irq);
>  			goto err_ecc_ioremap;
>  		}
>  
> -		nand_chip->dev_ready = atmel_nand_device_ready;
> -	}
> +		host->irq = irq;
> +	} else {
		rest
> +		nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
> +
> +		if (gpio_is_valid(host->board.rdy_pin)) {
> +			res = gpio_request(host->board.rdy_pin, "nand_rdy");
> +			if (res < 0) {
> +				dev_err(&pdev->dev,
> +					"can't request rdy gpio %d\n",
> +					host->board.rdy_pin);
> +				goto err_ecc_ioremap;
> +			}
>  
> -	if (gpio_is_valid(host->board.enable_pin)) {
> -		res = gpio_request(host->board.enable_pin, "nand_enable");
> -		if (res < 0) {
> -			dev_err(&pdev->dev,
> -				"can't request enable gpio %d\n",
> -				host->board.enable_pin);
> -			goto err_ecc_ioremap;
> +			res = gpio_direction_input(host->board.rdy_pin);
> +			if (res < 0) {
> +				dev_err(&pdev->dev,
> +					"can't request input direction rdy gpio %d\n",
> +					host->board.rdy_pin);
> +				goto err_ecc_ioremap;
> +			}
> +
> +			nand_chip->dev_ready = atmel_nand_device_ready;
>  		}
>  
> -		res = gpio_direction_output(host->board.enable_pin, 1);
> -		if (res < 0) {
> -			dev_err(&pdev->dev,
> -				"can't request output direction enable gpio %d\n",
> -				host->board.enable_pin);
> -			goto err_ecc_ioremap;
> +		if (gpio_is_valid(host->board.enable_pin)) {
> +			res = gpio_request(host->board.enable_pin,
we need to use devm_ here too
and everywhere we can in this driver
> +				"nand_enable");
> +			if (res < 0) {
> +				dev_err(&pdev->dev,
> +					"can't request enable gpio %d\n",
> +					host->board.enable_pin);
> +				goto err_ecc_ioremap;
> +			}
> +
> +			res = gpio_direction_output(host->board.enable_pin, 1);
> +			if (res < 0) {
> +				dev_err(&pdev->dev,
> +					"can't request output direction enable gpio %d\n",
> +					host->board.enable_pin);
> +				goto err_ecc_ioremap;
> +			}
>  		}
>  	}
>  
> @@ -1682,6 +1997,8 @@ err_ecc_ioremap:
>  	iounmap(host->io_base);
>  err_nand_ioremap:
>  	kfree(host);
> +	if (host->irq)
> +		free_irq(host->irq, host);
>  	return res;
>  }
>  
> diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
> new file mode 100644
> index 0000000..ca124de
> --- /dev/null
> +++ b/drivers/mtd/nand/atmel_nand_nfc.h
> @@ -0,0 +1,106 @@
> +/*
> + * Atmel Nand Flash Controller (NFC) - System peripherals regsters.
> + * Based on SAMA5D3 datasheet.
> + *
> + * ? Copyright 2013 Atmel Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#ifndef ATMEL_NAND_NFC_H
> +#define ATMEL_NAND_NFC_H
> +
> +/*
> + * HSMC NFC registers
> + */
> +#define ATMEL_HSMC_NFC_CFG		0x00	/* NFC Configuration Register */
> +#define		ATMEL_HSMC_PAGESIZE_512		(0)
> +#define		ATMEL_HSMC_PAGESIZE_1024	(1)
> +#define		ATMEL_HSMC_PAGESIZE_2048	(2)
> +#define		ATMEL_HSMC_PAGESIZE_4096	(3)
> +#define		ATMEL_HSMC_PAGESIZE_8192	(4)
	keep the << 0
> +#define		ATMEL_HSMC_WSPARE		(1 << 8)
> +#define		ATMEL_HSMC_RSPARE		(1 << 9)
> +#define		ATMEL_HSMC_EDGE_CTRL_RISING	(0 << 12)
> +#define		ATMEL_HSMC_EDGE_CTRL_FALLING	(1 << 12)
> +#define		ATMEL_HSMC_RBEDGE		(1 << 13)
> +#define		ATMEL_HSMC_NFC_DTOCYC		(0xf << 16)
> +#define		ATMEL_HSMC_NFC_DTOMUL		(0x7 << 20)
> +#define		ATMEL_HSMC_NFC_SPARESIZE	(0x7f << 24)
> +
> +#define ATMEL_HSMC_NFC_CTRL		0x04	/* NFC Control Register */
> +#define		ATMEL_HSMC_NFC_ENABLE		(1 << 0)
> +#define		ATMEL_HSMC_NFC_DISABLE		(1 << 1)
> +
> +#define ATMEL_HSMC_NFC_SR		0x08	/* NFC Status Register */
> +#define		ATMEL_HSMC_NFC_STATUS		(1 << 0)
> +#define		ATMEL_HSMC_NFC_RB_RISE		(1 << 4)
> +#define		ATMEL_HSMC_NFC_RB_FALL		(1 << 5)
> +#define		ATMEL_HSMC_NFC_BUSY		(1 << 8)
> +#define		ATMEL_HSMC_NFC_WR		(1 << 11)
> +#define		ATMEL_HSMC_NFC_CSID		(7 << 12)
> +#define		ATMEL_HSMC_NFC_XFR_DONE		(1 << 16)
> +#define		ATMEL_HSMC_NFC_CMD_DONE		(1 << 17)
> +#define		ATMEL_HSMC_NFC_DTOE		(1 << 20)
> +#define		ATMEL_HSMC_NFC_UNDEF		(1 << 21)
> +#define		ATMEL_HSMC_NFC_AWB		(1 << 22)
> +#define		ATMEL_HSMC_NFC_ASE		(1 << 23)
> +#define		ATMEL_HSMC_NFC_RB_EDGE		(1 << 24)
> +
> +#define ATMEL_HSMC_NFC_IER		0x0c
> +#define ATMEL_HSMC_NFC_IDR		0x10
> +#define ATMEL_HSMC_NFC_IMR		0x14
> +#define ATMEL_HSMC_NFC_CYCLE0		0x18	/* NFC Address Cycle Zero */
> +#define		ATMEL_HSMC_NFC_ADDR_CYCLE0	(0xff)
> +
> +#define ATMEL_HSMC_NFC_BANK		0x1c	/* NFC Bank Register */
> +#define		ATMEL_HSMC_NFC_BANK0	(0 << 0)
> +#define		ATMEL_HSMC_NFC_BANK1	(1 << 0)
> +#define		NFC_SRAM_BANK_OFFSET	(0x1200)
> +
> +#define nfc_writel(addr, reg, value) \
> +	writel((value), (addr) + ATMEL_HSMC_NFC_##reg)
> +
> +#define nfc_readl(addr, reg) \
> +	readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
> +
> +/*
> + * NFC Address Command definitions
> + */
> +#define NFCADDR_CMD_CMD1	(0xff << 2)	/* Command for Cycle 1 */
> +#define NFCADDR_CMD_CMD2	(0xff << 10)	/* Command for Cycle 2 */
> +#define NFCADDR_CMD_VCMD2	(0x1 << 18)	/* Valid Cycle 2 Command */
> +#define NFCADDR_CMD_ACYCLE	(0x7 << 19)	/* Number of Address required */
> +#define   NFCADDR_CMD_ACYCLE_NONE	(0x0 << 19)
> +#define   NFCADDR_CMD_ACYCLE_1		(0x1 << 19)
> +#define   NFCADDR_CMD_ACYCLE_2		(0x2 << 19)
> +#define   NFCADDR_CMD_ACYCLE_3		(0x3 << 19)
> +#define   NFCADDR_CMD_ACYCLE_4		(0x4 << 19)
> +#define   NFCADDR_CMD_ACYCLE_5		(0x5 << 19)
> +#define NFCADDR_CMD_CSID	(0x7 << 22)	/* Chip Select Identifier */
> +#define   NFCADDR_CMD_CSID_0		(0x0 << 22)
> +#define   NFCADDR_CMD_CSID_1		(0x1 << 22)
> +#define   NFCADDR_CMD_CSID_2		(0x2 << 22)
> +#define   NFCADDR_CMD_CSID_3		(0x3 << 22)
> +#define   NFCADDR_CMD_CSID_4		(0x4 << 22)
> +#define   NFCADDR_CMD_CSID_5		(0x5 << 22)
> +#define   NFCADDR_CMD_CSID_6		(0x6 << 22)
> +#define   NFCADDR_CMD_CSID_7		(0x7 << 22)
> +#define NFCADDR_CMD_DATAEN	(0x1 << 25)	/* Data Transfer Enable */
> +#define NFCADDR_CMD_DATADIS	(0x0 << 25)	/* Data Transfer Disable */
> +#define NFCADDR_CMD_NFCRD	(0x0 << 26)	/* NFC Read Enable */
> +#define NFCADDR_CMD_NFCWR	(0x1 << 26)	/* NFC Write Enable */
> +#define NFCADDR_CMD_NFCBUSY	(0x1 << 27)	/* NFC Busy */
> +
> +#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \
> +	writel((addr1234), (cmd) + nfc_base)
> +
> +#define nfc_cmd_readl(bitstatus, nfc_base) \
> +	readl_relaxed((bitstatus) + nfc_base)
> +
> +#define NFC_TIME_OUT_MS		100
> +
> +#endif
> -- 
> 1.7.9.5
> 


From maxime.ripard at free-electrons.com  Fri May 24 16:15:39 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 24 May 2013 22:15:39 +0200
Subject: [PATCHv3 5/6] ARM: cubieboard: Enable ethernet (EMAC) support in
 dts
In-Reply-To: <519F62B3.8090302@elopez.com.ar>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369387394-9453-6-git-send-email-maxime.ripard@free-electrons.com>
 <519F62B3.8090302@elopez.com.ar>
Message-ID: <20130524201539.GB17847@lukather>

Hi Emilio,

On Fri, May 24, 2013 at 09:53:07AM -0300, Emilio L?pez wrote:
> Hi,
> 
> El 24/05/13 06:23, Maxime Ripard escribi?:
> > From: Stefan Roese <sr at denx.de>
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > ---
> >  arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> > index b70fe0d..32d9b18 100644
> > --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> > +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> > @@ -27,6 +27,21 @@
> >  	};
> >  
> >  	soc at 01c20000 {
> > +		emac: ethernet at 01c0b000 {
> > +			pinctrl-names = "default";
> > +			pinctrl-0 = <&emac_pins_a>;
> > +			phy = <&phy0>;
> > +			status = "okay";
> > +		};
> > +
> > +		mdio at 01c0b080 {
> > +			status = "okay";
> > +
> > +			phy0: ethernet-phy at 0 {
> > +				reg = <0>;
> > +			};
> 
> During my testing I found out that I needed to use 1 as reg for the
> driver to work. You can find a fixup patch enclosed that changes this;
> it's possible that some extra changes may also be needed (s/phy0/phy1/
> on the node?)

Merged, thanks for noticing!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From plagnioj at jcrosoft.com  Fri May 24 16:11:50 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 24 May 2013 22:11:50 +0200
Subject: [PATCH v2 4/4] mtd: atmel_nand: enable Nand Flash Controller
 (NFC) write via sram
In-Reply-To: <1368784308-7600-5-git-send-email-josh.wu@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-5-git-send-email-josh.wu@atmel.com>
Message-ID: <20130524201150.GN24476@game.jcrosoft.org>

On 17:51 Fri 17 May     , Josh Wu wrote:
> This patch enable writing nand flash via NFC SRAM. It will minimize the CPU
> overhead. The SRAM write only support ECC_NONE and ECC_HW with PMECC.
> 
> This driver has been tested on SAMA5D3X-EK with JFFS2, YAFFS2, UBIFS and
> mtd-utils.
> 
> Here is part of mtd_speedtest (writing test) result, compare with non-NFC
> writing, it reduces %65 cpu load with loss %12 speed.

we may want to enable only read on sram and not write as the write speed can
be critic on some system

Best Regards,
J.
> 
> - commands use to test:
>   # insmod /mnt/mtd_speedtest.ko dev=2 &
>   # top -n 30 -d 1 | grep speedtest
> 
> - test result:
> =================================================
> mtd_speedtest: MTD device: 2
> mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
> mtd_speedtest: testing eraseblock write speed
>   509   495 root     D     1164   0%   7% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%   8% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     R     1164   0%   5% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: eraseblock write speed is 5194 KiB/s
> mtd_speedtest: testing page write speed
>   509   495 root     D     1164   0%  32% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  27% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  25% insmod /mnt/mtd_speedtest.ko dev=2
>   509   495 root     D     1164   0%  30% insmod /mnt/mtd_speedtest.ko dev=2
> mtd_speedtest: page write speed is 5024 KiB/s
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> ---
> v1 --> v2:
>   use NAND_ECC_WRITE instead of use new defined pass to pmecc_enable().
>   report a error if use a partial page write via nfc sram.
> 
>  drivers/mtd/nand/atmel_nand.c |   94 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 90 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index c10cd71..4490bd6 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -99,6 +99,7 @@ struct atmel_nfc {
>  
>  	/* Point to the sram bank which include readed data via NFC */
>  	void __iomem		*data_in_sram;
> +	bool			will_write_sram;
>  };
>  
>  struct atmel_nand_host {
> @@ -218,6 +219,16 @@ static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
>  		*t++ = readl_relaxed(s++);
>  }
>  
> +static void memcpy32_toio(void __iomem *trg, const void *src, int size)
> +{
> +	int i;
> +	u32 __iomem *t = trg;
> +	const u32 *s = src;
> +
> +	for (i = 0; i < (size >> 2); i++)
> +		writel_relaxed(*s++, t++);
> +}
> +
>  /*
>   * Minimal-overhead PIO for data access.
>   */
> @@ -339,7 +350,11 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
>  		dma_dst_addr = phys_addr;
>  	} else {
>  		dma_src_addr = phys_addr;
> -		dma_dst_addr = host->io_phys;
> +
> +		if (host->use_nfc_sram)
> +			dma_dst_addr = nfc_sram_phys(host);
> +		else
> +			dma_dst_addr = host->io_phys;
>  	}
>  
>  	tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
> @@ -919,9 +934,10 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
>  	int i, j;
>  	unsigned long end_time;
>  
> -	pmecc_enable(host, NAND_ECC_WRITE);
> -
> -	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
> +	if (!host->use_nfc_sram) {
> +		pmecc_enable(host, NAND_ECC_WRITE);
> +		chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
> +	}
>  
>  	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
>  	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
> @@ -1805,6 +1821,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>  	case NAND_CMD_SEQIN:
>  	case NAND_CMD_RNDIN:
>  		nfcwr = NFCADDR_CMD_NFCWR;
> +		if (host->nfc.will_write_sram && command == NAND_CMD_SEQIN)
> +			dataen = NFCADDR_CMD_DATAEN;
>  		break;
>  	default:
>  		break;
> @@ -1849,6 +1867,68 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>  	}
>  }
>  
> +static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> +			uint32_t offset, int data_len, const uint8_t *buf,
> +			int oob_required, int page, int cached, int raw)
> +{
> +	int cfg, len;
> +	int status = 0;
> +	struct atmel_nand_host *host = chip->priv;
> +	void __iomem *sram = host->nfc.sram_bank0 + nfc_get_sram_off(host);
> +
> +	/* Subpage write is not supported */
> +	if (offset || (data_len < mtd->writesize))
> +		return -EINVAL;
> +
> +	cfg = nfc_readl(host->nfc.hsmc_regs, CFG);
> +	len = mtd->writesize;
> +
> +	if (unlikely(raw)) {
> +		len += mtd->oobsize;
> +		nfc_writel(host->nfc.hsmc_regs, CFG, cfg | ATMEL_HSMC_WSPARE);
> +	} else
> +		nfc_writel(host->nfc.hsmc_regs, CFG, cfg & ~ATMEL_HSMC_WSPARE);
> +
> +	/* Copy page data to sram that will write to nand via NFC */
> +	if (use_dma) {
> +		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
> +			/* Fall back to use cpu copy */
> +			memcpy32_toio(sram, buf, len);
> +	} else {
> +		memcpy32_toio(sram, buf, len);
> +	}
> +
> +	if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
> +		/*
> +		 * When use NFC sram, need set up PMECC before send
> +		 * NAND_CMD_SEQIN command. Since when the nand command
> +		 * is sent, nfc will do transfer from sram and nand.
> +		 */
> +		pmecc_enable(host, NAND_ECC_WRITE);
> +
> +	host->nfc.will_write_sram = true;
> +	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
> +	host->nfc.will_write_sram = false;
> +
> +	if (likely(!raw))
> +		/* Need to write ecc into oob */
> +		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
> +
> +	if (status < 0)
> +		return status;
> +
> +	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +	status = chip->waitfunc(mtd, chip);
> +
> +	if ((status & NAND_STATUS_FAIL) && (chip->errstat))
> +		status = chip->errstat(mtd, chip, FL_WRITING, status, page);
> +
> +	if (status & NAND_STATUS_FAIL)
> +		return -EIO;
> +
> +	return 0;
> +}
> +
>  static int nfc_sram_init(struct mtd_info *mtd)
>  {
>  	struct nand_chip *chip = mtd->priv;
> @@ -1887,10 +1967,16 @@ static int nfc_sram_init(struct mtd_info *mtd)
>  
>  	nfc_writel(host->nfc.hsmc_regs, CFG, cfg_nfc);
>  
> +	host->nfc.will_write_sram = false;
>  	nfc_set_sram_bank(host, 0);
>  
>  	dev_info(host->dev, "Using NFC Sram\n");
>  
> +	/* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
> +	if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
> +			chip->ecc.mode == NAND_ECC_NONE)
> +		chip->write_page = nfc_sram_write_page;
> +
>  	return 0;
>  }
>  
> -- 
> 1.7.9.5
> 


From olof at lixom.net  Fri May 24 16:31:41 2013
From: olof at lixom.net (Olof Johansson)
Date: Fri, 24 May 2013 13:31:41 -0700
Subject: Allwinner sunXi Fixes for 3.10
In-Reply-To: <20130524195352.GA19644@lukather>
References: <20130524195352.GA19644@lukather>
Message-ID: <CAOesGMgG-qkRkaH54AYzm=AsuP5F38mBNM_rpTbM+CqJW_ZwxA@mail.gmail.com>

On Fri, May 24, 2013 at 12:53 PM, Maxime Ripard
<maxime.ripard at free-electrons.com> wrote:
> Hi Arnd, Olof,
>
> Please pull this small pull request with the sunxi fixes for 3.10
>
> Thanks!
> Maxime
>
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
>
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
>
> are available in the git repository at:
>
>   git://github.com/mripard/linux.git sunxi/fixes-for-3.10

Pulled, but tags/sunxi-fixes-for-3.10 instead, as discussed on IRC.


-Olof


From nm at ti.com  Fri May 24 16:32:31 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 24 May 2013 15:32:31 -0500
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <20130524200954.GA2344@kahuna>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna>
Message-ID: <20130524203231.GA2555@kahuna>

On 15:09-20130524, Nishanth Menon wrote:
> On 12:28-20130524, Kevin Hilman wrote:
> > Earlier commits ensured proper muxing of pins related to proper
> > TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
> > sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
> > OMAP4: TWL: mux sys_drm_msecure as output for PMIC).
> > 
> > However these only fixed legacy boot and not DT boot.  For DT boot,
> > the default mux values need to be set properly in DT.
> > 
> > Cc: Tony Lindgren <tony at atomide.com>
> > Signed-off-by: Kevin Hilman <khilman at linaro.org>
> > ---
> > Applies on v3.10-rc2
> > 
> >  arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
> >  arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
> >  2 files changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> > index 03bd60d..a7a9bc0 100644
> > --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> > +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> > @@ -59,6 +59,7 @@
> >  &omap4_pmx_core {
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <
> > +			&twl6030_pins
> >  			&twl6040_pins
> >  			&mcpdm_pins
> >  			&mcbsp1_pins
> > @@ -66,6 +67,13 @@
> >  			&tpd12s015_pins
> >  	>;
> >  
> > +	twl6030_pins: pinmux_twl6030_pins {
> > +		pinctrl-single,pins = <
> > +			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
> I can understand this - IRQ request comes here.
> verified on OMAP4460 Panda-ES.
> # omapconf read 0x4A10019C
> 4118011B
> 
> > +			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
> I do not understand this.
> OMAP4460 TRM:
> Register: CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ
> omapconf read 0x4A31E054
> 010F010F
> 
> I do not understand this configuration. mux modes for 
> FREF_CLK0_OUT_MUXMODE:
> 0x0: Select fref_clk0_out
> 0x1: Select fref_clk1_req
> 0x2: Reserved
> 0x3: Select gpio_wk6
> 0x5: Select sdmmc2_dat7
> 0x6: Select hw_dbg6
> 0x7: Select safe_mode
> 
> Why are we setting mode 0(clk out) here?

I did a bit more research into this:
MSECURE line needs to be set for us to set anything with TWL6030 RTC.
PandaBoard ES(4460) = this is on OMAP PIN AD4
PandaBoard (4430) = this is on OMAP PIN AD2

translating this back,
PandaBoard ES OMAp4460 pin AD4:
FREF_CLK3_OUT/FREF_CLK2_REQ/SYS_SECURE_INDICATOR/GPIO_WK31/C2C_WAKEREQOUT/SDMMC2_DAT5/ATTILA_HW_DBG8/SAFE_MODE
This is at register 0x4A31E054(higher 16 bits) - however since we are GP device,
SYS_SECURE_INDICATOR(mode 2) is reserved.
PandaBoard OMAP4430 pin AD2:
FREF_CLK0_OUT/FREF_CLK1_REQ/SYS_DRM_MSECURE/GPIO_WK6/SDMMC2_DAT7/ATTILA_HW_DBG6/SAFE_MOD
This is at register 0x4A31E054(lower 16 bits) - however since we are GP device,
SYS_DRM_MSECURE(mode 2) is reserved.

To use RTC, we will have to use GPIO.
on pandaboard ES, we need GPIO31 and PandaBoard, 6.

Further the pinctrl offsets will vary as well between the same.

IMHO, we need GPIO support and pinmux appropritate to the same to allow
RTC to work.


> > +		>;
> > +	};
> > +
> >  	twl6040_pins: pinmux_twl6040_pins {
> >  		pinctrl-single,pins = <
> >  			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
> > diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> > index a35d9cd..5ad0c10 100644
> > --- a/arch/arm/boot/dts/omap4-sdp.dts
> > +++ b/arch/arm/boot/dts/omap4-sdp.dts
> > @@ -145,6 +145,7 @@
> >  &omap4_pmx_core {
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <
> > +			&twl6030_pins
> >  			&twl6040_pins
> >  			&mcpdm_pins
> >  			&dmic_pins
> > @@ -179,6 +180,13 @@
> >  		>;
> >  	};
> >  
> > +	twl6030_pins: pinmux_twl6030_pins {
> > +		pinctrl-single,pins = <
> > +			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
> > +			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
> > +		>;
> > +	};
> > +
> >  	twl6040_pins: pinmux_twl6040_pins {
> >  		pinctrl-single,pins = <
> >  			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
> > -- 
> > 1.8.2
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> -- 
> Regards,
> Nishanth Menon
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Regards,
Nishanth Menon


From linus.walleij at linaro.org  Fri May 24 17:13:29 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 May 2013 23:13:29 +0200
Subject: [PATCH] ARM: nomadik: move the pin configuration to DT
Message-ID: <1369430009-27214-1-git-send-email-linus.walleij@linaro.org>

This moves the pin configuration for the Nomadik over to the
device tree using Gabriel's bindings. Remove the auxdata
nailing down the name of the pin controller as this is no
longer necessary.

Cc: Gabriel Fernandez <gabriel.fernandez at st.com>
Cc: Patrice Chotard <patrice.chotard at st.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-nomadik-s8815.dts    | 41 +++++++++++++++
 arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 82 ++++++++++++++++++++++++++++++
 arch/arm/mach-nomadik/cpu-8815.c           | 51 -------------------
 3 files changed, 123 insertions(+), 51 deletions(-)

diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 666945a..638ec8d 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -14,6 +14,43 @@
 		bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
 	};
 
+	pinctrl {
+		/* Hog CD pins */
+		pinctrl-names = "default";
+		pinctrl-0 = <&cd_default_mode>;
+
+		mmcsd-cd {
+			cd_default_mode: cd_default {
+				cd_default_cfg1 {
+					/* CD input GPIO */
+					ste,pins = "GPIO111_H21";
+					ste,input = <0>;
+				};
+				cd_default_cfg2 {
+					/* CD GPIO biasing */
+					ste,pins = "GPIO112_J21";
+					ste,output = <0>;
+				};
+			};
+		};
+		user-led {
+			user_led_default_mode: user_led_default {
+				user_led_default_cfg {
+					ste,pins = "GPIO2_C5";
+					ste,output = <1>;
+				};
+			};
+		};
+		user-button {
+			user_button_default_mode: user_button_default {
+				user_button_default_cfg {
+					ste,pins = "GPIO3_A4";
+					ste,input = <0>;
+				};
+			};
+		};
+	};
+
 	/* Custom board node with GPIO pins to active etc */
 	usb-s8815 {
 		/* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
@@ -36,6 +73,8 @@
 			gpios = <&gpio0 2 0x1>;
 			default-state = "off";
 			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_led_default_mode>;
 		};
 	};
 
@@ -47,6 +86,8 @@
 			gpios = <&gpio0 3 0x1>;
 			linux,code = <1>; /* KEY_ESC */
 			gpio-key,wakeup;
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_button_default_mode>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 51a33e0..615da87 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -94,6 +94,75 @@
 
 	pinctrl {
 		compatible = "stericsson,nmk-pinctrl-stn8815";
+		/* Pin configurations */
+		uart0 {
+			uart0_default_mux: uart0_mux {
+				u0_default_mux {
+					ste,function = "u0";
+					ste,pins = "u0_a_1";
+				};
+			};
+		};
+		uart1 {
+			uart1_default_mux: uart1_mux {
+				u1_default_mux {
+					ste,function = "u1";
+					ste,pins = "u1_a_1";
+				};
+			};
+		};
+		mmcsd {
+			mmcsd_default_mux: mmcsd_mux {
+				mmcsd_default_mux {
+					ste,function = "mmcsd";
+					ste,pins = "mmcsd_a_1";
+				};
+			};
+			mmcsd_default_mode: mmcsd_default {
+				mmcsd_default_cfg1 {
+					/* MCCLK */
+					ste,pins = "GPIO8_B10";
+					ste,output = <0>;
+				};
+				mmcsd_default_cfg2 {
+					/* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
+					ste,pins = "GPIO10_C11", "GPIO15_A12",
+					"GPIO16_C13";
+					ste,output = <1>;
+				};
+				mmcsd_default_cfg3 {
+					/* MCCMD, MCDAT3-0, MCMSFBCLK */
+					ste,pins = "GPIO9_A10", "GPIO11_B11",
+					"GPIO12_A11", "GPIO13_C12",
+					"GPIO14_B12", "GPIO24_C15";
+					ste,input = <1>;
+				};
+			};
+		};
+		i2c0 {
+			i2c0_default_mode: i2c0_default {
+				i2c0_default_cfg {
+					ste,pins = "GPIO62_D3", "GPIO63_D2";
+					ste,input = <1>;
+				};
+			};
+		};
+		i2c1 {
+			i2c1_default_mode: i2c1_default {
+				i2c1_default_cfg {
+					ste,pins = "GPIO53_L4", "GPIO54_L3";
+					ste,input = <1>;
+				};
+			};
+		};
+		i2c2 {
+			i2c2_default_mode: i2c2_default {
+				i2c2_default_cfg {
+					ste,pins = "GPIO73_C21", "GPIO74_C20";
+					ste,input = <1>;
+				};
+			};
+		};
 	};
 
 	src: src at 101e0000 {
@@ -191,6 +260,8 @@
 			<&gpio1 30 0>; /* scl */
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_default_mode>;
 
 		stw4811 at 2d {
 			   compatible = "st,stw4811";
@@ -205,6 +276,8 @@
 			<&gpio1 21 0>; /* scl */
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1_default_mode>;
 
 		camera at 2d {
 			   compatible = "st,camera";
@@ -227,6 +300,9 @@
 			<&gpio2 9 0>; /* scl */
 		#address-cells = <1>;
 		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2_default_mode>;
+
 		stw4811 at 2d {
 			   compatible = "st,stw4811-usb";
 			   reg = <0x2d>;
@@ -260,6 +336,8 @@
 			interrupts = <12>;
 			clocks = <&clk48>, <&pclk>;
 			clock-names = "uartclk", "apb_pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_default_mux>;
 		};
 
 		uart1: uart at 101fb000 {
@@ -269,6 +347,8 @@
 			interrupts = <17>;
 			clocks = <&clk48>, <&pclk>;
 			clock-names = "uartclk", "apb_pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart1_default_mux>;
 		};
 
 		uart2: uart at 101f2000 {
@@ -310,6 +390,8 @@
 			mmc-cap-sd-highspeed;
 			cd-gpios = <&gpio3 15 0x1>;
 			cd-inverted;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
 		};
 	};
 };
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 8351617..89e2c03 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -27,8 +27,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/irqchip.h>
 #include <linux/platform_data/clk-nomadik.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-#include <linux/pinctrl/machine.h>
 #include <linux/clocksource.h>
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
@@ -91,52 +89,6 @@
 #define NOMADIK_L2CC_BASE	0x10210000	/* L2 Cache controller */
 #define NOMADIK_UART1_VBASE	0xF01FB000
 
-static unsigned long out_low[] = { PIN_OUTPUT_LOW };
-static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
-static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
-static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
-
-static struct pinctrl_map __initdata nhk8815_pinmap[] = {
-	PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
-	/* User LED on S8815 */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO2_C5", out_high),
-	/* User button on S8815 */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO3_A4", in_nopull),
-	/* Hog in MMC/SD card mux */
-	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
-	/* MCCLK */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
-	/* MCCMD */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
-	/* MCCMDDIR */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
-	/* MCDAT3-0 */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
-	/* MCDAT0DIR */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
-	/* MCDAT31DIR */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
-	/* MCMSFBCLK */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
-	/* CD input GPIO */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
-	/* CD bias drive */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
-	/* I2C0 */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup),
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup),
-	/* I2C1 */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup),
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup),
-	/* I2C2 */
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup),
-	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup),
-};
-
 /* This is needed for LL-debug/earlyprintk/debug-macro.S */
 static struct map_desc cpu8815_io_desc[] __initdata = {
 	{
@@ -284,8 +236,6 @@ device_initcall(cpu8815_mmcsd_init);
 
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
-		"pinctrl-stn8815", NULL),
 	OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
 		NULL, &cpu8815_nand_data),
 	OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
@@ -299,7 +249,6 @@ static void __init cpu8815_init_of(void)
 	/* At full speed latency must be >=2, so 0x249 in low bits */
 	l2x0_of_init(0x00730249, 0xfe000fff);
 #endif
-	pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
 	of_platform_populate(NULL, of_default_bus_match_table,
 			cpu8815_auxdata_lookup, NULL);
 }
-- 
1.8.1.4



From khilman at linaro.org  Fri May 24 17:19:00 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 24 May 2013 14:19:00 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <20130524203231.GA2555@kahuna> (Nishanth Menon's message of "Fri, 
 24 May 2013 15:32:31 -0500")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
Message-ID: <87obc0f54r.fsf@linaro.org>

Nishanth Menon <nm at ti.com> writes:

> On 15:09-20130524, Nishanth Menon wrote:
>> On 12:28-20130524, Kevin Hilman wrote:
>> > Earlier commits ensured proper muxing of pins related to proper
>> > TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
>> > sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
>> > OMAP4: TWL: mux sys_drm_msecure as output for PMIC).
>> > 
>> > However these only fixed legacy boot and not DT boot.  For DT boot,
>> > the default mux values need to be set properly in DT.
>> > 
>> > Cc: Tony Lindgren <tony at atomide.com>
>> > Signed-off-by: Kevin Hilman <khilman at linaro.org>
>> > ---
>> > Applies on v3.10-rc2
>> > 
>> >  arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
>> >  arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
>> >  2 files changed, 16 insertions(+)
>> > 
>> > diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> > index 03bd60d..a7a9bc0 100644
>> > --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>> > +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> > @@ -59,6 +59,7 @@
>> >  &omap4_pmx_core {
>> >  	pinctrl-names = "default";
>> >  	pinctrl-0 = <
>> > +			&twl6030_pins
>> >  			&twl6040_pins
>> >  			&mcpdm_pins
>> >  			&mcbsp1_pins
>> > @@ -66,6 +67,13 @@
>> >  			&tpd12s015_pins
>> >  	>;
>> >  
>> > +	twl6030_pins: pinmux_twl6030_pins {
>> > +		pinctrl-single,pins = <
>> > +			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
>> I can understand this - IRQ request comes here.
>> verified on OMAP4460 Panda-ES.
>> # omapconf read 0x4A10019C
>> 4118011B
>> 
>> > +			0x14 0x0	/* fref_clk0_out.sys_drm_msecure OUTPUT */
>> I do not understand this.
>> OMAP4460 TRM:
>> Register: CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ
>> omapconf read 0x4A31E054
>> 010F010F
>> 
>> I do not understand this configuration. mux modes for 
>> FREF_CLK0_OUT_MUXMODE:
>> 0x0: Select fref_clk0_out
>> 0x1: Select fref_clk1_req
>> 0x2: Reserved
>> 0x3: Select gpio_wk6
>> 0x5: Select sdmmc2_dat7
>> 0x6: Select hw_dbg6
>> 0x7: Select safe_mode
>> 
>> Why are we setting mode 0(clk out) here?
>
> I did a bit more research into this:
> MSECURE line needs to be set for us to set anything with TWL6030 RTC.

Yes, the commit referenced in the changelog described that in detail.

> PandaBoard ES(4460) = this is on OMAP PIN AD4
> PandaBoard (4430) = this is on OMAP PIN AD2
>
> translating this back,
> PandaBoard ES OMAp4460 pin AD4:
> FREF_CLK3_OUT/FREF_CLK2_REQ/SYS_SECURE_INDICATOR/GPIO_WK31/C2C_WAKEREQOUT/SDMMC2_DAT5/ATTILA_HW_DBG8/SAFE_MODE
> This is at register 0x4A31E054(higher 16 bits) - however since we are GP device,
> SYS_SECURE_INDICATOR(mode 2) is reserved.
> PandaBoard OMAP4430 pin AD2:
> FREF_CLK0_OUT/FREF_CLK1_REQ/SYS_DRM_MSECURE/GPIO_WK6/SDMMC2_DAT7/ATTILA_HW_DBG6/SAFE_MOD
> This is at register 0x4A31E054(lower 16 bits) - however since we are GP device,
> SYS_DRM_MSECURE(mode 2) is reserved.
>
> To use RTC, we will have to use GPIO.
> on pandaboard ES, we need GPIO31 and PandaBoard, 6.
>
> Further the pinctrl offsets will vary as well between the same.
>
> IMHO, we need GPIO support and pinmux appropritate to the same to allow
> RTC to work.

I don't follow at all what you're trying to say.  The current settings
are working fine and have been tested on both 4430/Panda and 4460/Panda-ES.

The goal of this patch is to make default mux settings for twl6030 for
DT boot match current legacy boot in mainline.

The commits referenced in the changelog setup some default muxing for
twl6030 (see changelogs referenced and mux calls in
twl-common.c:omap4_pmic_init())

Without those mux settings, RTC wakeup on legacy boot does not work
(tested on 4430/panda, 4460/Panda with recent u-boot v2013.04 where most
of the old mux setup is gone.)  With those settings, RTC wakeup works.

Yes, the TRM has some mode bits marked as reserved, but that doesn't
mean they don't work.  It just means the documentation is squirreled
away in the secure TRM addendum.

Kevin





From nm at ti.com  Fri May 24 17:25:24 2013
From: nm at ti.com (Nishanth Menon)
Date: Fri, 24 May 2013 16:25:24 -0500
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <87obc0f54r.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
Message-ID: <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>

On Fri, May 24, 2013 at 4:19 PM, Kevin Hilman <khilman at linaro.org> wrote:
> Nishanth Menon <nm at ti.com> writes:
>
>> On 15:09-20130524, Nishanth Menon wrote:
>>> On 12:28-20130524, Kevin Hilman wrote:
>>> > Earlier commits ensured proper muxing of pins related to proper
>>> > TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
>>> > sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
>>> > OMAP4: TWL: mux sys_drm_msecure as output for PMIC).
>>> >
>>> > However these only fixed legacy boot and not DT boot.  For DT boot,
>>> > the default mux values need to be set properly in DT.
>>> >
>>> > Cc: Tony Lindgren <tony at atomide.com>
>>> > Signed-off-by: Kevin Hilman <khilman at linaro.org>
>>> > ---
>>> > Applies on v3.10-rc2
>>> >
>>> >  arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
>>> >  arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
>>> >  2 files changed, 16 insertions(+)
>>> >
>>> > diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> > index 03bd60d..a7a9bc0 100644
>>> > --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> > +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>> > @@ -59,6 +59,7 @@
>>> >  &omap4_pmx_core {
>>> >    pinctrl-names = "default";
>>> >    pinctrl-0 = <
>>> > +                  &twl6030_pins
>>> >                    &twl6040_pins
>>> >                    &mcpdm_pins
>>> >                    &mcbsp1_pins
>>> > @@ -66,6 +67,13 @@
>>> >                    &tpd12s015_pins
>>> >    >;
>>> >
>>> > +  twl6030_pins: pinmux_twl6030_pins {
>>> > +          pinctrl-single,pins = <
>>> > +                  0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
>>> I can understand this - IRQ request comes here.
>>> verified on OMAP4460 Panda-ES.
>>> # omapconf read 0x4A10019C
>>> 4118011B
>>>
>>> > +                  0x14 0x0        /* fref_clk0_out.sys_drm_msecure OUTPUT */
>>> I do not understand this.
>>> OMAP4460 TRM:
>>> Register: CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ
>>> omapconf read 0x4A31E054
>>> 010F010F
>>>
>>> I do not understand this configuration. mux modes for
>>> FREF_CLK0_OUT_MUXMODE:
>>> 0x0: Select fref_clk0_out
>>> 0x1: Select fref_clk1_req
>>> 0x2: Reserved
>>> 0x3: Select gpio_wk6
>>> 0x5: Select sdmmc2_dat7
>>> 0x6: Select hw_dbg6
>>> 0x7: Select safe_mode
>>>
>>> Why are we setting mode 0(clk out) here?
>>
>> I did a bit more research into this:
>> MSECURE line needs to be set for us to set anything with TWL6030 RTC.
>
> Yes, the commit referenced in the changelog described that in detail.
>
>> PandaBoard ES(4460) = this is on OMAP PIN AD4
>> PandaBoard (4430) = this is on OMAP PIN AD2
>>
>> translating this back,
>> PandaBoard ES OMAp4460 pin AD4:
>> FREF_CLK3_OUT/FREF_CLK2_REQ/SYS_SECURE_INDICATOR/GPIO_WK31/C2C_WAKEREQOUT/SDMMC2_DAT5/ATTILA_HW_DBG8/SAFE_MODE
>> This is at register 0x4A31E054(higher 16 bits) - however since we are GP device,
>> SYS_SECURE_INDICATOR(mode 2) is reserved.
>> PandaBoard OMAP4430 pin AD2:
>> FREF_CLK0_OUT/FREF_CLK1_REQ/SYS_DRM_MSECURE/GPIO_WK6/SDMMC2_DAT7/ATTILA_HW_DBG6/SAFE_MOD
>> This is at register 0x4A31E054(lower 16 bits) - however since we are GP device,
>> SYS_DRM_MSECURE(mode 2) is reserved.
>>
>> To use RTC, we will have to use GPIO.
>> on pandaboard ES, we need GPIO31 and PandaBoard, 6.
>>
>> Further the pinctrl offsets will vary as well between the same.
>>
>> IMHO, we need GPIO support and pinmux appropritate to the same to allow
>> RTC to work.
>
> I don't follow at all what you're trying to say.  The current settings
> are working fine and have been tested on both 4430/Panda and 4460/Panda-ES.
>
> The goal of this patch is to make default mux settings for twl6030 for
> DT boot match current legacy boot in mainline.
>
> The commits referenced in the changelog setup some default muxing for
> twl6030 (see changelogs referenced and mux calls in
> twl-common.c:omap4_pmic_init())
>
> Without those mux settings, RTC wakeup on legacy boot does not work
> (tested on 4430/panda, 4460/Panda with recent u-boot v2013.04 where most
> of the old mux setup is gone.)  With those settings, RTC wakeup works.
>
> Yes, the TRM has some mode bits marked as reserved, but that doesn't
> mean they don't work.  It just means the documentation is squirreled
> away in the secure TRM addendum.
>
Actually 2 things:

a) patch seems to do the wrong thing for 4460 - 0x18 offset should
have been used instead of 0x14 which is correct for 4430?
b) yes, I understand,  the current settings we did worked, but the
mode(0) we are setting to is real weird - we are setting it up for
clk0 out - I cant even think why it is even working in the first place
:( - is it because we are pumping out sysclkout and as a result we are
lucky that msecure is being sampled at the right point by twl6030
allowing rtc access? either way, IMHO, the configuration is wrong.

Regards,
Nishanth Menon


From kgene.kim at gmail.com  Fri May 24 17:46:28 2013
From: kgene.kim at gmail.com (Kukjin Kim)
Date: Sat, 25 May 2013 06:46:28 +0900
Subject: [PATCH] ARM: SAMSUNG: devs: Add names to fimd0 IRQ resources
In-Reply-To: <1368630584-30147-1-git-send-email-t.figa@samsung.com>
References: <1368630584-30147-1-git-send-email-t.figa@samsung.com>
Message-ID: <519FDFB4.50402@gmail.com>

On 05/16/13 00:09, Tomasz Figa wrote:
> Since commit 1977e6d8 (drm/exynos: change the method for getting the
> interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
> named. This patch fixes probe failure in non-DT cases by adding
> appropriate resource names to fimd0 platform device.
>
> Signed-off-by: Tomasz Figa<t.figa at samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> ---
>   arch/arm/plat-samsung/devs.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index 30c2fe2..0f9c3f4 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
>   #ifdef CONFIG_S5P_DEV_FIMD0
>   static struct resource s5p_fimd0_resource[] = {
>   	[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
> -	[1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
> -	[2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
> -	[3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
> +	[1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
> +	[2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
> +	[3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
>   };
>
>   struct platform_device s5p_device_fimd0 = {

Applied into fixes.

Thanks.

- Kukjin


From kgene.kim at samsung.com  Fri May 24 17:46:46 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 25 May 2013 06:46:46 +0900
Subject: [PATCH] ARM: SAMSUNG: devs: Add names to fimd0 IRQ resources
In-Reply-To: <1368630584-30147-1-git-send-email-t.figa@samsung.com>
References: <1368630584-30147-1-git-send-email-t.figa@samsung.com>
Message-ID: <519FDFC6.9010802@samsung.com>

On 05/16/13 00:09, Tomasz Figa wrote:
> Since commit 1977e6d8 (drm/exynos: change the method for getting the
> interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
> named. This patch fixes probe failure in non-DT cases by adding
> appropriate resource names to fimd0 platform device.
>
> Signed-off-by: Tomasz Figa<t.figa at samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> ---
>   arch/arm/plat-samsung/devs.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index 30c2fe2..0f9c3f4 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
>   #ifdef CONFIG_S5P_DEV_FIMD0
>   static struct resource s5p_fimd0_resource[] = {
>   	[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
> -	[1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
> -	[2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
> -	[3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
> +	[1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
> +	[2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
> +	[3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
>   };
>
>   struct platform_device s5p_device_fimd0 = {

Applied into fixes.

Thanks.

- Kukjin


From oliver+list at schinagl.nl  Fri May 24 17:50:38 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Fri, 24 May 2013 23:50:38 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <5197B82F.8010809@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <51969EA9.1060602@free-electrons.com> <5197B82F.8010809@schinagl.nl>
Message-ID: <519FE0AE.2010102@schinagl.nl>

On 05/18/13 19:19, Oliver Schinagl wrote:
<snip>
>>> +
>>> +
>>> +/* We read the entire key, using a look up table. Returned is only the
>>> + * requested byte. This is of course slower then it could be and uses 4 times
>>> + * more reads as needed but keeps code a little simpler.
>>> + */
>>> +u8 sunxi_sid_read_byte(const int key)
>>> +{
>>> +	u32 sid_key;
>>> +	u8 ret;
>>> +
>>> +	ret = 0;
>>> +	if (likely((key <= SUNXI_SID_SIZE))) {
>>> +		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
>>> +		switch (key % 4) {
>>> +		case 0:
>>> +			ret = (sid_key >> 24) & 0xff;
>>> +			break;
>>> +		case 1:
>>> +			ret = (sid_key >> 16) & 0xff;
>>> +			break;
>>> +		case 2:
>>> +			ret = (sid_key >> 8) & 0xff;
>>> +			break;
>>> +		case 3:
>>> +			ret = sid_key & 0xff;
>>> +			break;
>>> +		}
>>> +	}
>>
>> Come on, you can do better. This lookup table is useless.
> I didn't want to depend on the fixed layout of memory, but consider it
> removed.
But i'm not smart enough :p

We can either use the look up table (which does have benefits as its 
potentially more future proof), or do some ((key >> 2) << 2) to 'drop' 
the LSB's that we want to ignore (unless there's some smarter way).

Personally, I think the LUT is a little cleaner and more readable, but I 
guess if you look at poor efficiency, the lut costs some memory, the 
left/right shift cost an additional >> 2 ... what you prefer.
>>
>> Also, why the first key is the one with the MSBs?
>> I'd expect that the key 0 is the one holding the LSBs.
> Strangely enough, they have swapped the MSB and LSB bytes. I double
> checked it with u-boot and yep, swapped. Though in the end, if we write
> stuff there and we read stuff from there, order doesn't matter? So what
> do we prefer. Have it so that it makes sense and ignore how u-boot reads
> it, or correct it and be consistent?
>
You had me confused and I was looking at this for a little while. 
Bit-ordering does not change, Byte endianness is a different story of 
course. As it is now, I decided to use Big endianess. So now a 32bit key 
looks like:
0x162367c7 and if we read one byte at a time, we get 0x16, 0x23, 0x67 
and 0xc7. I made a comment that data is read as Big endian. If it is 
important, for eeprom data, to be stored little endian, I'll obviously 
change it per request.



From khilman at linaro.org  Fri May 24 17:51:21 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 24 May 2013 14:51:21 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 (Nishanth Menon's message of "Fri, 24 May 2013 16:25:24 -0500")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
Message-ID: <87a9nkf3mu.fsf@linaro.org>

Nishanth Menon <nm at ti.com> writes:

> On Fri, May 24, 2013 at 4:19 PM, Kevin Hilman <khilman at linaro.org> wrote:
>> Nishanth Menon <nm at ti.com> writes:
>>
>>> On 15:09-20130524, Nishanth Menon wrote:
>>>> On 12:28-20130524, Kevin Hilman wrote:
>>>> > Earlier commits ensured proper muxing of pins related to proper
>>>> > TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
>>>> > sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
>>>> > OMAP4: TWL: mux sys_drm_msecure as output for PMIC).
>>>> >
>>>> > However these only fixed legacy boot and not DT boot.  For DT boot,
>>>> > the default mux values need to be set properly in DT.
>>>> >
>>>> > Cc: Tony Lindgren <tony at atomide.com>
>>>> > Signed-off-by: Kevin Hilman <khilman at linaro.org>
>>>> > ---
>>>> > Applies on v3.10-rc2
>>>> >
>>>> >  arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
>>>> >  arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
>>>> >  2 files changed, 16 insertions(+)
>>>> >
>>>> > diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> > index 03bd60d..a7a9bc0 100644
>>>> > --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> > +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> > @@ -59,6 +59,7 @@
>>>> >  &omap4_pmx_core {
>>>> >    pinctrl-names = "default";
>>>> >    pinctrl-0 = <
>>>> > +                  &twl6030_pins
>>>> >                    &twl6040_pins
>>>> >                    &mcpdm_pins
>>>> >                    &mcbsp1_pins
>>>> > @@ -66,6 +67,13 @@
>>>> >                    &tpd12s015_pins
>>>> >    >;
>>>> >
>>>> > +  twl6030_pins: pinmux_twl6030_pins {
>>>> > +          pinctrl-single,pins = <
>>>> > +                  0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
>>>> I can understand this - IRQ request comes here.
>>>> verified on OMAP4460 Panda-ES.
>>>> # omapconf read 0x4A10019C
>>>> 4118011B
>>>>
>>>> > +                  0x14 0x0        /* fref_clk0_out.sys_drm_msecure OUTPUT */
>>>> I do not understand this.
>>>> OMAP4460 TRM:
>>>> Register: CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ
>>>> omapconf read 0x4A31E054
>>>> 010F010F
>>>>
>>>> I do not understand this configuration. mux modes for
>>>> FREF_CLK0_OUT_MUXMODE:
>>>> 0x0: Select fref_clk0_out
>>>> 0x1: Select fref_clk1_req
>>>> 0x2: Reserved
>>>> 0x3: Select gpio_wk6
>>>> 0x5: Select sdmmc2_dat7
>>>> 0x6: Select hw_dbg6
>>>> 0x7: Select safe_mode
>>>>
>>>> Why are we setting mode 0(clk out) here?
>>>
>>> I did a bit more research into this:
>>> MSECURE line needs to be set for us to set anything with TWL6030 RTC.
>>
>> Yes, the commit referenced in the changelog described that in detail.
>>
>>> PandaBoard ES(4460) = this is on OMAP PIN AD4
>>> PandaBoard (4430) = this is on OMAP PIN AD2
>>>
>>> translating this back,
>>> PandaBoard ES OMAp4460 pin AD4:
>>> FREF_CLK3_OUT/FREF_CLK2_REQ/SYS_SECURE_INDICATOR/GPIO_WK31/C2C_WAKEREQOUT/SDMMC2_DAT5/ATTILA_HW_DBG8/SAFE_MODE
>>> This is at register 0x4A31E054(higher 16 bits) - however since we are GP device,
>>> SYS_SECURE_INDICATOR(mode 2) is reserved.
>>> PandaBoard OMAP4430 pin AD2:
>>> FREF_CLK0_OUT/FREF_CLK1_REQ/SYS_DRM_MSECURE/GPIO_WK6/SDMMC2_DAT7/ATTILA_HW_DBG6/SAFE_MOD
>>> This is at register 0x4A31E054(lower 16 bits) - however since we are GP device,
>>> SYS_DRM_MSECURE(mode 2) is reserved.
>>>
>>> To use RTC, we will have to use GPIO.
>>> on pandaboard ES, we need GPIO31 and PandaBoard, 6.
>>>
>>> Further the pinctrl offsets will vary as well between the same.
>>>
>>> IMHO, we need GPIO support and pinmux appropritate to the same to allow
>>> RTC to work.
>>
>> I don't follow at all what you're trying to say.  The current settings
>> are working fine and have been tested on both 4430/Panda and 4460/Panda-ES.
>>
>> The goal of this patch is to make default mux settings for twl6030 for
>> DT boot match current legacy boot in mainline.
>>
>> The commits referenced in the changelog setup some default muxing for
>> twl6030 (see changelogs referenced and mux calls in
>> twl-common.c:omap4_pmic_init())
>>
>> Without those mux settings, RTC wakeup on legacy boot does not work
>> (tested on 4430/panda, 4460/Panda with recent u-boot v2013.04 where most
>> of the old mux setup is gone.)  With those settings, RTC wakeup works.
>>
>> Yes, the TRM has some mode bits marked as reserved, but that doesn't
>> mean they don't work.  It just means the documentation is squirreled
>> away in the secure TRM addendum.
>>
> Actually 2 things:
>
> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
> have been used instead of 0x14 which is correct for 4430?

I see, thanks.  I'll double check the TRMs.

> b) yes, I understand,  the current settings we did worked, but the
> mode(0) we are setting to is real weird - we are setting it up for
> clk0 out - I cant even think why it is even working in the first place
> :( - is it because we are pumping out sysclkout and as a result we are
> lucky that msecure is being sampled at the right point by twl6030
> allowing rtc access? either way, IMHO, the configuration is wrong.

Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
for legacy mode, I just duplicated the settings u-boot was using.  Guess
it's a fluke that it works.

Yet another thing wrong with my patch:  the fref_clk0 pad is in the WKUP
padconf section, and I put it at offset 0x14 in the CORE section, which
is yet another wrong place.

Let me respin this after some more doc reading.

Thanks for the detailed review,

Kevin






From tomasz.figa at gmail.com  Fri May 24 17:55:03 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 24 May 2013 23:55:03 +0200
Subject: [RESEND PATCH 1/5] clk: samsung: Use clk->base instead of
 directly using clk->con0 for PLL3xxx
In-Reply-To: <1369391478-7665-2-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
 <1369391478-7665-2-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <4808417.0aThqqOIhP@flatron>

Hi,

On Friday 24 of May 2013 16:01:14 Vikas Sajjan wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
> 
> To factor out possible common code, this patch unifies the clk strutures
> used for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.
> 
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c    |   10 ++++---
>  drivers/clk/samsung/clk-exynos5250.c |   14 ++++-----
>  drivers/clk/samsung/clk-pll.c        |   54
> ++++++++++++++++++---------------- drivers/clk/samsung/clk-pll.h       
> |    4 +--
>  4 files changed, 44 insertions(+), 38 deletions(-)
> 

Whether this patch really allows to factor out any significant amount of 
common code is rather discussible, but generally looks fine.

Reviewed-by: Tomasz Figa <t.figa at samsung.com>

Best regards,
Tomasz



From kgene.kim at samsung.com  Fri May 24 18:01:45 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 25 May 2013 07:01:45 +0900
Subject: [PATCH] ARM: EXYNOS: add PM dependency to PM_GENERIC_DOMAINS
 for Exynos4210
In-Reply-To: <001a01ce5041$1b9ddd30$52d99790$@samsung.com>
References: <001a01ce5041$1b9ddd30$52d99790$@samsung.com>
Message-ID: <519FE349.7050208@samsung.com>

On 05/14/13 10:19, Jingoo Han wrote:
> PM_GENERIC_DOMAINS needs PM dependency.
>
> Fixed build warning as below:
>
> warning: (PLAT_S3C64XX&&  CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM)

If so, PLAT_S3C64XX should be fixed together.

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 2057853..c04c4ee 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C64XX
  	bool
  	depends on ARCH_S3C64XX
  	default y
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
  	select SAMSUNG_WAKEMASK
  	help
  	  Base platform code for any Samsung S3C64XX device

> warning: (PLAT_S3C64XX&&  CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM)
> arch/arm/kernel/return_address.c:63:2: warning: #warning "TODO: return_address should use unwind tables" [-Wcpp]
> drivers/base/power/domain.c: In function '__pm_genpd_add_device':
> drivers/base/power/domain.c:1422:2: error: implicit declaration of function 'genpd_acquire_lock'
> [-Werror=implicit-function-declaration]
> drivers/base/power/domain.c:1466:2: error: implicit declaration of function 'genpd_release_lock'
> [-Werror=implicit-function-declaration]
> drivers/base/power/domain.c: In function 'pm_genpd_add_subdomain':
> drivers/base/power/domain.c:1649:3: error: implicit declaration of function 'genpd_sd_counter_inc'
> [-Werror=implicit-function-declaration]
> drivers/base/power/domain.c: In function 'pm_genpd_remove_subdomain':
> drivers/base/power/domain.c:1721:4: error: implicit declaration of function 'genpd_sd_counter_dec'
> [-Werror=implicit-function-declaration]
> drivers/base/power/domain.c: In function 'pm_genpd_attach_cpuidle':
> drivers/base/power/domain.c:1887:2: error: implicit declaration of function 'genpd_recalc_cpu_exit_latency'
> [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
>
> Signed-off-by: Jingoo Han<jg1.han at samsung.com>
> ---
>   arch/arm/mach-exynos/Kconfig |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index d19edff..1f7ddb2 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -34,7 +34,7 @@ config CPU_EXYNOS4210
>   	default y
>   	depends on ARCH_EXYNOS4
>   	select ARM_CPU_SUSPEND if PM
> -	select PM_GENERIC_DOMAINS
> +	select PM_GENERIC_DOMAINS if PM
>   	select S5P_PM if PM
>   	select S5P_SLEEP if PM
>   	select SAMSUNG_DMADEV


From tomasz.figa at gmail.com  Fri May 24 18:04:45 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sat, 25 May 2013 00:04:45 +0200
Subject: [RESEND PATCH 2/5] clk: samsung: Add support to register
 rate_table for PLL3xxx
In-Reply-To: <1369391478-7665-3-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
 <1369391478-7665-3-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <2606875.QmniDqB8hY@flatron>

Hi,

Please see my comments inline.

On Friday 24 of May 2013 16:01:15 Vikas Sajjan wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
> 
> This patch defines a common rate_table which will contain recommended p,
> m, s and k values for supported rates that needs to be changed for
> changing corresponding PLL's rate.
> It also sorts the rate table while registering the PLL rate table.
> So that this sorted table can be used for making the searching of
> "required rate" efficient.
> 
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
>  drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
>  drivers/clk/samsung/clk-pll.c        |   35
> ++++++++++++++++++++++++++++++++-- drivers/clk/samsung/clk-pll.h       
> |   27 ++++++++++++++++++++++++-- 4 files changed, 69 insertions(+), 15
> deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos4.c
> b/drivers/clk/samsung/clk-exynos4.c index cf7d4e7..beff8a1 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node
> *np, enum exynos4_soc exynos4_so reg_base + VPLL_CON0, pll_4650c);
>  	} else {
>  		apll = samsung_clk_register_pll35xx("fout_apll", 
"fin_pll",
> -					reg_base + APLL_LOCK);
> +					reg_base + APLL_LOCK, NULL, 0);
>  		mpll = samsung_clk_register_pll35xx("fout_mpll", 
"fin_pll",
> -					reg_base + E4X12_MPLL_LOCK);
> +					reg_base + E4X12_MPLL_LOCK, NULL, 
0);
>  		epll = samsung_clk_register_pll36xx("fout_epll", 
"fin_pll",
> -					reg_base + EPLL_LOCK);
> +					reg_base + EPLL_LOCK, NULL, 0);
>  		vpll = samsung_clk_register_pll36xx("fout_vpll", 
"fin_pll",
> -					reg_base + VPLL_LOCK);
> +					reg_base + VPLL_LOCK, NULL, 0);
>  	}
> 
>  	samsung_clk_add_lookup(apll, fout_apll);
> diff --git a/drivers/clk/samsung/clk-exynos5250.c
> b/drivers/clk/samsung/clk-exynos5250.c index 687b580..ddf10ca 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node
> *np) ext_clk_match);
> 
>  	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
> -			reg_base);
> +			reg_base, NULL, 0);
>  	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
> -			reg_base + 0x4000);
> +			reg_base + 0x4000, NULL, 0);
>  	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
> -			reg_base + 0x20010);
> +			reg_base + 0x20010, NULL, 0);
>  	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
> -			reg_base + 0x10050);
> +			reg_base + 0x10050, NULL, 0);
>  	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
> -			reg_base + 0x10020);
> +			reg_base + 0x10020, NULL, 0);
>  	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
> -			reg_base + 0x10030);
> +			reg_base + 0x10030, NULL, 0);
>  	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
> -			reg_base + 0x10040);
> +			reg_base + 0x10040, NULL, 0);
> 
>  	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
>  			ARRAY_SIZE(exynos5250_fixed_rate_clks));
> diff --git a/drivers/clk/samsung/clk-pll.c
> b/drivers/clk/samsung/clk-pll.c index 01f17cf..b8c0260 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -10,12 +10,15 @@
>  */
> 
>  #include <linux/errno.h>
> +#include <linux/sort.h>
>  #include "clk.h"
>  #include "clk-pll.h"
> 
>  struct samsung_clk_pll {
>  	struct clk_hw		hw;
>  	const void __iomem	*base;
> +	struct samsung_pll_rate_table *rate_table;
> +	unsigned int rate_count;
>  };
> 
>  #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
> @@ -25,6 +28,14 @@ struct samsung_clk_pll {
>  #define pll_writel(pll, val, offset)					\
>  		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
> 
> +static int samsung_compare_rate(const void *_a, const void *_b)
> +{
> +	const struct samsung_pll_rate_table *a = _a;
> +	const struct samsung_pll_rate_table *b = _b;
> +
> +	return a->rate - b->rate;
> +}
> +
>  /*
>   * PLL35xx Clock Type
>   */
> @@ -62,7 +73,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops =
> { };
> 
>  struct clk * __init samsung_clk_register_pll35xx(const char *name,
> -			const char *pname, const void __iomem *base)
> +			const char *pname, const void __iomem *base,
> +			struct samsung_pll_rate_table *rate_table,
> +			const unsigned int rate_count)
>  {
>  	struct samsung_clk_pll *pll;
>  	struct clk *clk;
> @@ -82,6 +95,14 @@ struct clk * __init
> samsung_clk_register_pll35xx(const char *name,
> 
>  	pll->hw.init = &init;
>  	pll->base = base;
> +	pll->rate_table = rate_table;
> +	pll->rate_count = rate_count;
> +
> +	if (pll->rate_table && pll->rate_count) {

You seem to assume here that the exact set of rates is known at 
compilation time. In other words, you assume that all boards have the same 
PLL input (xtal) frequency.

We have similar patches available in our internal tree that work in a bit 
different way:

1) they assume that passed array is already sorted, which is a good 
assumption, because you have full control of this array - it's a part of 
the clock driver and if it's incorrect it's your fault - you don't deal 
with data input by user

2) passed array don't have defined rates, but rather only all the relevant 
PLL coefficients; the frequency for each entry is calculated at 
registration time, based on rate of parent clock

3) the table is NULL terminated, without the need to pass its size, but 
it's just a matter of preference

> +		sort(pll->rate_table, pll->rate_count,
> +			sizeof(struct samsung_pll_rate_table),
> +			samsung_compare_rate, NULL);
> +	}
> 
>  	clk = clk_register(NULL, &pll->hw);
>  	if (IS_ERR(clk)) {
> @@ -137,7 +158,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops
> = { };
> 
>  struct clk * __init samsung_clk_register_pll36xx(const char *name,
> -			const char *pname, const void __iomem *base)
> +			const char *pname, const void __iomem *base,
> +			struct samsung_pll_rate_table *rate_table,
> +			const unsigned int rate_count)
>  {
>  	struct samsung_clk_pll *pll;
>  	struct clk *clk;
> @@ -157,6 +180,14 @@ struct clk * __init
> samsung_clk_register_pll36xx(const char *name,
> 
>  	pll->hw.init = &init;
>  	pll->base = base;
> +	pll->rate_table = rate_table;
> +	pll->rate_count = rate_count;
> +
> +	if (pll->rate_table && pll->rate_count) {
> +		sort(pll->rate_table, pll->rate_count,
> +			sizeof(struct samsung_pll_rate_table),
> +			samsung_compare_rate, NULL);
> +	}
> 
>  	clk = clk_register(NULL, &pll->hw);
>  	if (IS_ERR(clk)) {
> diff --git a/drivers/clk/samsung/clk-pll.h
> b/drivers/clk/samsung/clk-pll.h index 1329522..b5e12430 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -12,6 +12,25 @@
>  #ifndef __SAMSUNG_CLK_PLL_H
>  #define __SAMSUNG_CLK_PLL_H
> 
> +#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
> +	{							\
> +		.rate = _rate,					\
> +		.pll_con0 = ((_m) << 16 | (_p) << 8 | (_s)),	\
> +	}
> +
> +#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
> +	{							\
> +		.rate = _rate,					\
> +		.pll_con0 = ((_m) << 16 | (_p) << 8 | (_s)),	\
> +		.pll_con1 = _k,					\
> +	}
> +
> +struct samsung_pll_rate_table {
> +	unsigned  int rate;
> +	u32 pll_con0;
> +	u32 pll_con1;

I don't like this struct. What about PLLs that don't have con0 or con1, 
but rather a completely weird register strukture like PLL_P_REG, 
PLL_M_REG, PLL_S_REG? The structure has generic name, which suggests that 
it should be able to handle any future Samsung PLLs as well.

I'd suggest storing all coefficients as separate fields of the struct, 
e.g.

struct samsung_pll_rate_table {
	unsigned  int rate;
	/* ... */
	unsigned int p;
	unsigned int m;
	unsigned int s;
	/* ... */
};

Best regards,
Tomasz

> +};
> +
>  enum pll45xx_type {
>  	pll_4500,
>  	pll_4502,
> @@ -25,9 +44,13 @@ enum pll46xx_type {
>  };
> 
>  extern struct clk * __init samsung_clk_register_pll35xx(const char
> *name, -			const char *pname, const void __iomem 
*base);
> +			const char *pname, const void __iomem *base,
> +			struct samsung_pll_rate_table *rate_table,
> +			const unsigned int rate_count);
>  extern struct clk * __init samsung_clk_register_pll36xx(const char
> *name, -			const char *pname, const void __iomem 
*base);
> +			const char *pname, const void __iomem *base,
> +			struct samsung_pll_rate_table *rate_table,
> +			const unsigned int rate_count);
>  extern struct clk * __init samsung_clk_register_pll45xx(const char
> *name, const char *pname, const void __iomem *con_reg,
>  			enum pll45xx_type type);


From sboyd at codeaurora.org  Fri May 24 18:05:39 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri, 24 May 2013 15:05:39 -0700
Subject: [PATCH] ARM: avoid mis-detecting some V7 cores in the decompressor
In-Reply-To: <20130523231531.GT18614@n2100.arm.linux.org.uk>
References: <1368049671-22879-1-git-send-email-sboyd@codeaurora.org>
 <5193E424.9090605@codeaurora.org> <519E57D2.3050000@codeaurora.org>
 <20130523231531.GT18614@n2100.arm.linux.org.uk>
Message-ID: <20130524220539.GB599@codeaurora.org>

On 05/24, Russell King - ARM Linux wrote:
> On Thu, May 23, 2013 at 10:54:26AM -0700, Stephen Boyd wrote:
> > On 05/15/13 12:38, Stephen Boyd wrote:
> > > On 05/08/13 14:47, Stephen Boyd wrote:
> > >> From: Brian Swetland <swetland at google.com>
> > >>
> > >> Currently v7 CPUs with an MIDR that has no bits set in the range
> > >> [16:12] will be detected as old ARM CPUs with no caches and so
> > >> the cache will never be turned on during decompression. ARM's
> > >> Cortex chips have an 0xC in the range [16:12] so they never match
> > >> this entry, but Qualcomm's Scorpion and Krait processors never
> > >> set these bits to anything besides 0 so they always match.
> > >>
> > >> Skip this entry if we've compiled in support for v7 CPUs. This
> > >> allows kernel decompression to happen nearly instantly instead of
> > >> taking over 20 seconds.
> > >>
> > >> Signed-off-by: Brian Swetland <swetland at google.com>
> > >> [sboyd: Clarified and extended commit text]
> > >> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> > >> ---
> > > Ping?
> > 
> > Russell, shall I add this to the patch tracker?
> 
> Yes please.
> 

Ok, thanks.

I've noticed another problem now that our caches are used. On MSM
we have TEXT_OFFSET set to at least 0x208000 if we've built-in
support for MSM8x60/8960. If I boot a kernel with the MSM code
built-in that requires the higher text offset, but I load my
compressed kernel below that address (such as 0x0) the
decompression fails.

This happens because the page tables are written into the
compressed data region before we relocate ourself to a higher
location.

Here's some ascii art to show the problem

We start off at 0x0

 0x000000 +---------+
          |         |
          | zImage  |
 0x208000 |---------| <- r4 (zreladdr)
          | zImage  |
 0x300000 +---------+ <- _edata

Then we run far enough to call cache_on which goes ahead and
calls __setup_mmu and sets up our page tables.

 0x008000 +---------+
          |         |
          | zImage  |
          |         |
 0x204000 |---------|
          |  pgdir  |
 0x208000 |---------| <- r4 (zreladdr)
          |         |
          | zImage  |
          |         |
 0x300000 +---------+ <- _edata

This is bad because we just wrote our page tables into the
compressed data. Nobody notices though and we finish relocating
ourselves and then we call decompress_kernel() which fails
randomly. (BTW, why does error() sit in a while loop forever? We
can't get any information about why the decompression failed if
we have debug_ll enabled. I had to patch the error() routine to
not while loop forever to get that print after do_decompress to
be useful.)

I see a few solutions.

 1) Relocate with caches off and then turn on caches after we're
    running in a location where we won't overwrite ourselves.

 2) Have temporary page tables for the relocation phase that live
    just below the location we're going to relocate to.

 3) Force bootloaders loading these types of images to load the
    zImage at least as high as the TEXT_OFFSET is compiled to.

I don't think we can convince everyone that #3 is ok to do. I'm
leaning towards #2 since we get all the benefits of the cache
during the relocation phase but #1 is the obviously simple fix.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From khilman at linaro.org  Fri May 24 18:15:41 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 24 May 2013 15:15:41 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <87a9nkf3mu.fsf@linaro.org> (Kevin Hilman's message of "Fri, 24
 May 2013 14:51:21 -0700")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org>
Message-ID: <87ppwgdnxu.fsf@linaro.org>

Kevin Hilman <khilman at linaro.org> writes:

> Nishanth Menon <nm at ti.com> writes:

[...]

>> Actually 2 things:
>>
>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>> have been used instead of 0x14 which is correct for 4430?
>
> I see, thanks.  I'll double check the TRMs.
>
>> b) yes, I understand,  the current settings we did worked, but the
>> mode(0) we are setting to is real weird - we are setting it up for
>> clk0 out - I cant even think why it is even working in the first place
>> :( - is it because we are pumping out sysclkout and as a result we are
>> lucky that msecure is being sampled at the right point by twl6030
>> allowing rtc access? either way, IMHO, the configuration is wrong.
>
> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
> for legacy mode, I just duplicated the settings u-boot was using.  Guess
> it's a fluke that it works.

Actually, for legacy mode, it's set correctly in mode 2.  This line:

	omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);

does the right thing based on the signal name.    But for DT boot, I
defintely screwed it up by setting it to mode (and putting it in the
wrong padconf section.)

Also, are you *really* sure about the offset difference between 4430 and
4460 here?  I don't have access to NDA docs anymore, so I cannot double
check this.

What I do know is that the legacy code is using 0x54 for both, and if I
simply comment out that 'sys_drm_msecure' line above, RTC wake stops
working (legacy boot) on both 4430 and 4460, so that seems like pretty
stront evidence that it's the same offset on both.

Kevin


From tomasz.figa at gmail.com  Fri May 24 18:19:11 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sat, 25 May 2013 00:19:11 +0200
Subject: [RESEND PATCH 3/5] clk: samsung: Add set_rate() clk_ops for
 PLL35xx
In-Reply-To: <1369391478-7665-4-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
 <1369391478-7665-4-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <2621811.AH1nnyyD7h@flatron>

Hi,

On Friday 24 of May 2013 16:01:16 Vikas Sajjan wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
> 
> Adds set_rate() and round_rate() clk_ops for PLL35xx
> 
> The round_rate() implemenation as of now is dummy, it returns the same
> rate which is passed as input.
> 
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-pll.c |   95
> ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 94
> insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c
> b/drivers/clk/samsung/clk-pll.c index b8c0260..291cc9e 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -11,6 +11,7 @@
> 
>  #include <linux/errno.h>
>  #include <linux/sort.h>
> +#include <linux/bsearch.h>
>  #include "clk.h"
>  #include "clk-pll.h"
> 
> @@ -36,6 +37,21 @@ static int samsung_compare_rate(const void *_a, const
> void *_b) return a->rate - b->rate;
>  }
> 
> +static struct samsung_pll_rate_table *samsung_get_pll_settings(
> +				struct samsung_clk_pll *pll, unsigned long 
rate)
> +{
> +	struct samsung_pll_rate_table req_rate, *tmp;
> +
> +	req_rate.rate = rate;
> +	tmp = bsearch(&req_rate, pll->rate_table, pll->rate_count,
> +			sizeof(struct samsung_pll_rate_table),
> +			samsung_compare_rate);

Binary search over < 10 entries? Isn't it a bit of overkill?

> +	if (tmp)
> +		return tmp;
> +
> +	return NULL;
> +}
> +
>  /*
>   * PLL35xx Clock Type
>   */
> @@ -46,9 +62,15 @@ static int samsung_compare_rate(const void *_a, const
> void *_b) #define PLL35XX_MDIV_MASK       (0x3FF)
>  #define PLL35XX_PDIV_MASK       (0x3F)
>  #define PLL35XX_SDIV_MASK       (0x7)
> +#define PLL35XX_LOCK_STAT_MASK  (0x1)
>  #define PLL35XX_MDIV_SHIFT      (16)
>  #define PLL35XX_PDIV_SHIFT      (8)
>  #define PLL35XX_SDIV_SHIFT      (0)
> +#define PLL35XX_LOCK_STAT_SHIFT (29)
> +
> +#define PLL35XX_MDIV(_tmp) ((_tmp) & (PLL35XX_MDIV_MASK <<
> PLL35XX_MDIV_SHIFT)) +#define PLL35XX_PDIV(_tmp) ((_tmp) &
> (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT)) +#define PLL35XX_SDIV(_tmp)
> ((_tmp) & (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT))
> 
>  static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
>  				unsigned long parent_rate)
> @@ -68,8 +90,76 @@ static unsigned long
> samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned
> long)fvco;
>  }
> 
> -static const struct clk_ops samsung_pll35xx_clk_ops = {
> +static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32
> pll_con) +{
> +	if ((mdiv != PLL35XX_MDIV(pll_con)) || (pdiv !=
> PLL35XX_PDIV(pll_con))) +		return 1;
> +	else
> +		return 0;
> +}
> +
> +static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long
> drate, +					unsigned long prate)
> +{
> +	struct samsung_clk_pll *pll = to_clk_pll(hw);
> +	struct samsung_pll_rate_table *rate;
> +
> +	u32 tmp, mdiv, pdiv, sdiv;
> +
> +	/* Get required rate settings from table */
> +	rate = samsung_get_pll_settings(pll, drate);
> +	if (!rate) {
> +		pr_err("%s: Invalid rate : %lu for pll clk %s\n", 
__func__,
> +			drate, __clk_get_name(hw->clk));
> +		return -EINVAL;
> +	}
> +
> +	mdiv = PLL35XX_MDIV(rate->pll_con0);
> +	pdiv = PLL35XX_PDIV(rate->pll_con0);
> +	sdiv = PLL35XX_SDIV(rate->pll_con0);

You wouldn't need to use those macros if all coefficients were stored as 
separate fields in the struct.

> +
> +	tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
> +
> +	if (!(samsung_pll35xx_mp_change(mdiv, pdiv, tmp))) {
> +		/* If only s change, change just s value only*/
> +		tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
> +		tmp |= sdiv;

This line is correct, but it looks like it wasn't, because:
a) the name suggests that it contains the raw value of S coefficient
b) it's real value is hidden between a macro, name of which suggests the 
same as in a) as well.

This makes the code hard to read.

> +		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
> +	} else {
> +		/* Set PLL lock time.
> +		   Maximum lock time can be 270 * PDIV cycles */
> +		pll_writel(pll, (pdiv >> PLL35XX_PDIV_SHIFT) * 270,
> +				PLL35XX_LOCK_OFFSET);

Hmm, magic constant in the code? Shouldn't it be defined as a macro?

> +
> +		/* Change PLL PMS values */
> +		tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
> +				(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) 
|
> +				(PLL35XX_SDIV_MASK << 
PLL35XX_SDIV_SHIFT));
> +		tmp |= mdiv | pdiv | sdiv;

This looks strange as well, even if it's correct.

> +		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
> +
> +		/* wait_lock_time */
> +		do {
> +			cpu_relax();
> +			tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
> +		} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
> +				<< PLL35XX_LOCK_STAT_SHIFT)));
> +	}
> +
> +	return 0;
> +}
> +
> +static long samsung_pll35xx_round_rate(struct clk_hw *hw,
> +			unsigned long drate, unsigned long *prate)
> +{
> +	/* Clock framework cries without this, so implemented dummy */

This is completely wrong. Have you tested this code or read how Common 
Clock Framework works?

clk_set_rate() first calls ->round_rate() to get a rate supported by the 
clock that is nearest and not higher than requested rate and only then it 
calls ->set_rate() with the rate returned by ->round_rate().

So the round_rate() callback must return the highest supported rate with 
parent clock at prate and not higher than drate.

> +	return drate;
> +}
> +
> +static struct clk_ops samsung_pll35xx_clk_ops = {
>  	.recalc_rate = samsung_pll35xx_recalc_rate,
> +	.round_rate = samsung_pll35xx_round_rate,
> +	.set_rate = samsung_pll35xx_set_rate,
>  };
> 
>  struct clk * __init samsung_clk_register_pll35xx(const char *name,
> @@ -102,6 +192,9 @@ struct clk * __init
> samsung_clk_register_pll35xx(const char *name, sort(pll->rate_table,
> pll->rate_count,
>  			sizeof(struct samsung_pll_rate_table),
>  			samsung_compare_rate, NULL);
> +	} else {
> +		samsung_pll35xx_clk_ops.round_rate = NULL;
> +		samsung_pll35xx_clk_ops.set_rate = NULL;

This is completely wrong. You are changing a static structure that is used 
for all instances of PLL35xx, not only the one being registered at the 
moment.

Best regards,
Tomasz

>  	}
> 
>  	clk = clk_register(NULL, &pll->hw);


From alexandre.belloni at free-electrons.com  Fri May 24 18:19:02 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Sat, 25 May 2013 00:19:02 +0200
Subject: [PATCH] ARM: at91: Fix link breakage when !CONFIG_PHY
Message-ID: <1369433942-12386-1-git-send-email-alexandre.belloni@free-electrons.com>

Fixes:
arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to
`phy_register_fixup_for_uid'

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 arch/arm/mach-at91/board-dt-sama5.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..f510381 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -38,6 +38,7 @@ static void __init at91_dt_init_irq(void)
 	of_irq_init(irq_of_match);
 }
 
+#ifdef CONFIG_PHY
 static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
 	int value;
@@ -59,12 +60,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 
 	return 0;
 }
+#endif
 
 static void __init sama5_dt_device_init(void)
 {
+#ifdef CONFIG_PHY
 	if (of_machine_is_compatible("atmel,sama5d3xcm"))
 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 			ksz9021rn_phy_fixup);
+#endif
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-- 
1.8.1.2



From tomasz.figa at gmail.com  Fri May 24 18:20:05 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sat, 25 May 2013 00:20:05 +0200
Subject: [RESEND PATCH 4/5] clk: samsung: Add set_rate() clk_ops for
 PLL36xx
In-Reply-To: <1369391478-7665-5-git-send-email-vikas.sajjan@linaro.org>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
 <1369391478-7665-5-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <2497806.WgtiTKYQrX@flatron>

Hi,

On Friday 24 of May 2013 16:01:17 Vikas Sajjan wrote:
> This patch adds set_rate and round_rate clk_ops for PLL36xx
> The round_rate() implementation as of now is dummy, it returns the same
> rate which is passed as input.
> 
> Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
> ---
>  drivers/clk/samsung/clk-pll.c |   67
> +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67
> insertions(+)
> 

I have exactly the same comments for this patch as for patch 3/5.

Best regards,
Tomasz



From olof at lixom.net  Fri May 24 18:54:08 2013
From: olof at lixom.net (Olof Johansson)
Date: Fri, 24 May 2013 15:54:08 -0700
Subject: [GIT PULL] ARM: SoC fixes for 3.10-rc
Message-ID: <20130524225408.GA11451@quad.lixom.net>

Hi Linus,


The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-for-linus

for you to fetch changes up to f4ae176c626311d6507c9a2d263657c4cc4e1667:

  Merge tag 'sunxi-fixes-for-3.10' of git://github.com/mripard/linux into fixes (2013-05-24 15:50:28 -0700)

----------------------------------------------------------------

ARM: SoC fixes for 3.10-rc

We didn't have any fixes sent up for -rc2, so this is a slightly larger
batch. A bit all over the place platform-wise; OMAP, at91, marvell,
renesas, sunxi, ux500, etc.

I tried to summarize highlights but there isn't a whole lot to point
out. Lots of little things fixed all over. A couple of defconfig updates
due to new/changing options.

----------------------------------------------------------------
Alexandre Courbot (1):
      ARM: tegra: defconfig fixes

Andrew Lunn (1):
      ARM: Orion: Remove redundant init_dma_coherent_pool_size()

Boris BREZILLON (1):
      ARM: at91/dt: fix macb pinctrl_macb_rmii_mii_alt definition

Dirk Behme (1):
      ARM i.MX6: correct MLB clock configuration

Emilio L?pez (1):
      ARM: ux500: select REGULATOR

Ezequiel Garcia (2):
      ARM: mvebu: Add a ranges entry to translate devbus childs
      ARM: mvebu: Fix ranges entry on XP GP board

Gregory CLEMENT (3):
      ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform
      ARM: plat-orion: Fix num_resources and id for ge10 and ge11
      ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node

Jean-Christophe PLAGNIOL-VILLARD (3):
      ARM: at91/trivial: fix model name for SAM9X25-EK
      ARM: at91: rm9200 fix time support
      ARM: at91: at91sam9n12: move external irq declatation to DT

Josh Wu (1):
      ARM: at91/sama5: fix incorrect PMC pcr div definition

Lee Jones (3):
      ARM: ux500: Remove duplicated assignment of ab8500_platdata
      ARM: ux500: Fix incorrect DEBUG UART virtual addresses
      ARM: ux500: Provide device enumeration number suffix for SMSC911x

Linus Walleij (1):
      ARM: nomadik: fix IRQ assignment for SMC ethernet

Lucas Stach (2):
      clk: tegra: remove USB from clk init table
      clk: tegra: add ac97 controller clock

Ludovic Desroches (1):
      ARM: at91: dts: request only spi cs-gpios used on sama5d3x cpu module

Martin Michlmayr (1):
      Kirkwood: Enable PCIe port 1 on QNAP TS-11x/TS-21x

Maxime Ripard (2):
      ARM: sunxi: Fix Mini X-plus device tree build
      ARM: sunxi: select ARCH_REQUIRE_GPIOLIB

Nicolas Ferre (1):
      ARM: at91/trivial: typo in GEM compatible string

Olof Johansson (10):
      Merge tag 'fixes-3.10-1' of git://git.infradead.org/users/jcooper/linux into fixes
      Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
      Merge tag 'omap-for-v3.10-rc1/fixes' of git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge tag 'fixes-3.10-2' of git://git.infradead.org/users/jcooper/linux into fixes
      Merge tag 'imx-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
      Merge tag 'ux500-arm-soc-v3.10-fixes' of git://git.kernel.org/.../linusw/linux-stericsson into fixes
      Merge tag 'omap-fixes-a-for-3.10-rc' of git://git.kernel.org/.../pjw/omap-pending into fixes
      Merge tag 'renesas-boards-marzen-fixes-for-v3.10' of git://git.kernel.org/.../horms/renesas into fixes
      Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
      Merge tag 'sunxi-fixes-for-3.10' of git://github.com/mripard/linux into fixes

Paul Walmsley (1):
      ARM: OMAP2+: Add missing CONFIG_ARCH_MULTI_V6=y to omap2plus_defconfig

Philipp Zabel (1):
      ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks

Rajendra Nayak (2):
      ARM: OMAP2+: hwmod: Fix sidle programming in _enable_sysc()/_idle_sysc()
      ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in active

Santosh Shilimkar (4):
      ARM: OMAP2+: hwmod-data: UART IP needs software control to manage sidle modes
      ARM: OMAP2+: serial: Remove the un-used slave idle hooks
      SERIAL: OMAP: Remove the slave idle handling from the driver
      ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis

Sebastian Hesselbarth (1):
      ARM: plat-orion: add missing ehci include to common.h

Shawn Guo (2):
      ARM: imx: replicate the diagnostic register of boot cpu into secondary cores
      ARM: imx: fix typo in gpu3d_shader_sels

Simon Horman (1):
      ARM: shmobile: marzen: Use error values in usb_power_*

Srinivas Kandagatla (1):
      ARM: vt8500: Add missing NULL terminator in dt_compat

Thomas Petazzoni (2):
      ARM: mvebu: do not duplicate the mpic alias
      arm: mvebu: fix the 'ranges' property to handle PCIe

Tony Lindgren (1):
      ARM: dts: Fix musb interrupt for device tree booting

Vaibhav Hiremath (1):
      ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock

Wei Yongjun (1):
      ARM: OMAP: fix error return code in omap1_system_dma_init()

jean-philippe francois (1):
      ARM: OMAP: fix __init section mismatch for _enable_preprogram

 Documentation/devicetree/bindings/net/macb.txt     |   2 +-
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/armada-370-xp.dtsi               |   3 +-
 arch/arm/boot/dts/armada-370.dtsi                  |   7 +-
 arch/arm/boot/dts/armada-xp-gp.dts                 |   3 +
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   |   3 +
 arch/arm/boot/dts/armada-xp.dtsi                   |   2 +-
 arch/arm/boot/dts/at91sam9260.dtsi                 |   2 +-
 arch/arm/boot/dts/at91sam9n12.dtsi                 |   1 +
 arch/arm/boot/dts/at91sam9x25ek.dts                |   2 +-
 arch/arm/boot/dts/omap3.dtsi                       |   2 +-
 arch/arm/boot/dts/sama5d3.dtsi                     |  12 +--
 arch/arm/boot/dts/sama5d3xcm.dtsi                  |   4 +
 arch/arm/boot/dts/ste-nomadik-s8815.dts            |  12 ++-
 arch/arm/boot/dts/sun4i-a10-mini-xplus.dts         |   4 +-
 arch/arm/configs/omap2plus_defconfig               |   1 +
 arch/arm/configs/tegra_defconfig                   |   3 +-
 arch/arm/include/debug/ux500.S                     |   6 +-
 arch/arm/mach-at91/at91rm9200_time.c               |   7 +-
 arch/arm/mach-at91/at91sam9n12.c                   |   6 --
 arch/arm/mach-at91/include/mach/at91_pmc.h         |   6 +-
 arch/arm/mach-imx/clk-imx6q.c                      |  11 +-
 arch/arm/mach-imx/headsmp.S                        |  12 +++
 arch/arm/mach-imx/platsmp.c                        |  14 +++
 arch/arm/mach-kirkwood/common.c                    |   6 --
 arch/arm/mach-kirkwood/ts219-setup.c               |   2 +-
 arch/arm/mach-mvebu/Kconfig                        |   1 +
 arch/arm/mach-mvebu/armada-370-xp.c                |   7 --
 arch/arm/mach-omap1/dma.c                          |   1 +
 arch/arm/mach-omap2/cclock33xx_data.c              |  26 ++++-
 arch/arm/mach-omap2/omap_hwmod.c                   | 113 +++++----------------
 arch/arm/mach-omap2/omap_hwmod.h                   |   7 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   3 +
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |   6 ++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   4 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   6 +-
 arch/arm/mach-omap2/serial.c                       |  31 ------
 arch/arm/mach-orion5x/common.c                     |   7 --
 arch/arm/mach-shmobile/board-marzen.c              |   6 +-
 arch/arm/mach-sunxi/Kconfig                        |   1 +
 arch/arm/mach-ux500/Kconfig                        |   1 +
 arch/arm/mach-ux500/board-mop500.c                 |   6 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |   6 +-
 arch/arm/mach-ux500/setup.h                        |   2 +-
 arch/arm/mach-vt8500/vt8500.c                      |   1 +
 arch/arm/plat-orion/common.c                       |  12 +--
 arch/arm/plat-orion/include/plat/common.h          |   1 +
 drivers/clk/tegra/clk-tegra20.c                    |  11 +-
 drivers/tty/serial/omap-serial.c                   |  23 -----
 include/linux/platform_data/serial-omap.h          |   2 -
 50 files changed, 185 insertions(+), 236 deletions(-)


From s.hauer at pengutronix.de  Fri May 24 19:00:21 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 25 May 2013 01:00:21 +0200
Subject: clock framework: Don't disable a clock already enabled by boot
 loader?
In-Reply-To: <519F60CA.6090302@de.bosch.com>
References: <519F60CA.6090302@de.bosch.com>
Message-ID: <20130524230021.GF31135@pengutronix.de>

Hi Dirk,

On Fri, May 24, 2013 at 02:44:58PM +0200, Dirk Behme wrote:
> Hi,
> 
> we register a clock using clk_register_clkdev() etc already enabled
> by a boot loader. We are doing only the clk_register_clkdev(), but
> no clock_enable() etc on this clock.
> 
> With this, enable_count for this clock is zero, while in fact it's
> already on. I.e. the kernel doesn't know that it is on.
> 
> This results in
> 
> late_initcall(clk_disable_unused())
> 
> disabling this clock because the kernel thinks it's unused.
> 
> Is this the intended behavior?

Yes, and it's great since after this point the hardware state is in sync
with the enable counter.

> Is there a way to let the kernel know
> "the clock is enabled already, set enable_count != 0"? Or is the
> only way to do this correctly calling clock_enable() on an already
> enabled clock?

You could set the CLK_IGNORE_UNUSED flag in the clock, but I suggest to
just clk_get/clk_enable the clock in the driver using it.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From kgene.kim at samsung.com  Fri May 24 19:25:15 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 25 May 2013 08:25:15 +0900
Subject: [GIT PULL] Samsung fixes-3 for v3.10
Message-ID: <519FF6DB.5040002@samsung.com>

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-fixes-3

for you to fetch changes up to 15f504f0c2038b9a0f1569c9ce34def61f0c65be:

   ARM: SAMSUNG: Add names to fimd0 IRQ resources (2013-05-25 06:49:43 
+0900)

----------------------------------------------------------------
Fixes following for v3.10
- to get usb2 working on the Chromebook with adding the
   usb phy node for usb2 on exynos5250
- supporting exynos4210 rev0 SoC
- exynos5440 restart applying only to powered-on domains
- drm-exynos probe failure with adding resource names to
   fimd0 platform device

----------------------------------------------------------------
Jungseok Lee (1):
       ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC

Tomasz Figa (2):
       ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
       ARM: SAMSUNG: Add names to fimd0 IRQ resources

Vivek Gautam (1):
       ARM: dts: Enabling samsung-usb2phy driver for exynos5250

  arch/arm/boot/dts/exynos5250.dtsi          | 15 ++++++++++++
  arch/arm/mach-exynos/Kconfig               |  3 ++-
  arch/arm/mach-exynos/common.c              | 39 
++++++++++++++++++++++++++++--
  arch/arm/mach-exynos/common.h              |  2 ++
  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++--
  arch/arm/plat-samsung/devs.c               |  6 ++---
  6 files changed, 61 insertions(+), 9 deletions(-)
The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-fixes-3

for you to fetch changes up to 15f504f0c2038b9a0f1569c9ce34def61f0c65be:

   ARM: SAMSUNG: Add names to fimd0 IRQ resources (2013-05-25 06:49:43 
+0900)

----------------------------------------------------------------
Fixes following for v3.10
- to get usb2 working on the Chromebook with adding the
   usb phy node for usb2 on exynos5250
- supporting exynos4210 rev0 SoC
- exynos5440 restart applying only to powered-on domains
- drm-exynos probe failure with adding resource names to
   fimd0 platform device

----------------------------------------------------------------
Jungseok Lee (1):
       ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC

Tomasz Figa (2):
       ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
       ARM: SAMSUNG: Add names to fimd0 IRQ resources

Vivek Gautam (1):
       ARM: dts: Enabling samsung-usb2phy driver for exynos5250

  arch/arm/boot/dts/exynos5250.dtsi          | 15 ++++++++++++
  arch/arm/mach-exynos/Kconfig               |  3 ++-
  arch/arm/mach-exynos/common.c              | 39 
++++++++++++++++++++++++++++--
  arch/arm/mach-exynos/common.h              |  2 ++
  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++--
  arch/arm/plat-samsung/devs.c               |  6 ++---
  6 files changed, 61 insertions(+), 9 deletions(-)


From horms at verge.net.au  Fri May 24 20:10:21 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 09:10:21 +0900
Subject: [PATCH v2] gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
In-Reply-To: <20130524094724.1510.80331.sendpatchset@w520>
References: <20130524094724.1510.80331.sendpatchset@w520>
Message-ID: <20130525001020.GC32093@verge.net.au>

On Fri, May 24, 2013 at 06:47:24PM +0900, Magnus Damm wrote:
> From: Simon Horman <horms+renesas at verge.net.au>
> 
> As hardware support for this feature is not universal for all SoCs a flag,
> has_both_edge_trigger, has been added to the platform data of the driver to
> allow this feature to be enabled.
> 
> The motivation for this is to allow use of the gpio-keys driver on the
> lager board which is based on the r8a7790 SoC. The V2 of this patch has been
> fully exercised using that driver on that board.
> 
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> Signed-off-by: Magnus Damm <damm at opensource.se>

Thanks, I will queue this up for v3.11 in the gpio-rcar branch.


From khilman at linaro.org  Fri May 24 20:24:21 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 24 May 2013 17:24:21 -0700
Subject: [PATCH v2] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
Message-ID: <1369441461-18888-1-git-send-email-khilman@linaro.org>

Earlier commits ensured proper muxing of pins related to proper
TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
OMAP4: TWL: mux sys_drm_msecure as output for PMIC).

However these only fixed legacy boot and not DT boot.  For DT boot,
the default mux values need to be set properly in DT.

Special thanks to Nishanth Menon for the review and catching some
major flaws in earlier versions.

Tested on OMAP4430/Panda and OMAP4460/Panda-ES.

Cc: Nishanth Menon <nm at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
Applies to v3.10-rc2

 arch/arm/boot/dts/omap4-panda-common.dtsi | 20 ++++++++++++++++++++
 arch/arm/boot/dts/omap4-sdp.dts           | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..eeb734e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -56,9 +56,23 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&twl6030_wkup_pins
+	>;
+
+	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+		pinctrl-single,pins = <
+			0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+		>;
+	};
+};
+
 &omap4_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
+			&twl6030_pins
 			&twl6040_pins
 			&mcpdm_pins
 			&mcbsp1_pins
@@ -66,6 +80,12 @@
 			&tpd12s015_pins
 	>;
 
+	twl6030_pins: pinmux_twl6030_pins {
+		pinctrl-single,pins = <
+			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+		>;
+	};
+
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
 			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd..98505a2 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -142,9 +142,23 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&twl6030_wkup_pins
+	>;
+
+	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+		pinctrl-single,pins = <
+			0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+		>;
+	};
+};
+
 &omap4_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
+			&twl6030_pins
 			&twl6040_pins
 			&mcpdm_pins
 			&dmic_pins
@@ -179,6 +193,12 @@
 		>;
 	};
 
+	twl6030_pins: pinmux_twl6030_pins {
+		pinctrl-single,pins = <
+			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+		>;
+	};
+
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
 			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-- 
1.8.2



From horms at verge.net.au  Fri May 24 20:39:50 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 09:39:50 +0900
Subject: [PATCH 1/2] ARM: shmobile: irqpin: add a DT property to enable
 masking on parent
In-Reply-To: <Pine.LNX.4.64.1305241109530.1090@axis700.grange>
References: <Pine.LNX.4.64.1305241109530.1090@axis700.grange>
Message-ID: <20130525003950.GA4476@verge.net.au>

On Fri, May 24, 2013 at 11:13:03AM +0200, Guennadi Liakhovetski wrote:
> To disable spurious interrupts, that get triggered on certain hardware, the
> irqpin driver masks them on the parent interrupt controller. To specify
> such broken devices a .control_parent parameter can be provided in the
> platform data. In the DT case we need a property, to do the same.
> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> ---
> 
> These two patches simply split the earlier "ARM: shmobile: irqpin: fix 
> handling of spurious interrupts in DT case" patch into two parts. 
> Otherwise no change.

Magnus,

could you please review this series?

> 
>  .../interrupt-controller/renesas,intc-irqpin.txt   |    2 ++
>  drivers/irqchip/irq-renesas-intc-irqpin.c          |    7 +++++--
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> index c6f09b7..152b10a 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> @@ -11,3 +11,5 @@ Optional properties:
>    resource allocation properties
>  - sense-bitfield-width: width of a single sense bitfield in the SENSE register,
>    if different from the default 4 bits
> +- control-parent: disable and enable interrupts on the parent interrupt
> +  controller, needed for some broken implementations
> diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
> index 4aca1b2..82cec63 100644
> --- a/drivers/irqchip/irq-renesas-intc-irqpin.c
> +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
> @@ -348,11 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev)
>  	}
>  
>  	/* deal with driver instance configuration */
> -	if (pdata)
> +	if (pdata) {
>  		memcpy(&p->config, pdata, sizeof(*pdata));
> -	else
> +	} else {
>  		of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
>  				     &p->config.sense_bitfield_width);
> +		p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
> +								 "control-parent");
> +	}
>  	if (!p->config.sense_bitfield_width)
>  		p->config.sense_bitfield_width = 4; /* default to 4 bits */
>  
> -- 
> 1.7.2.5
> 


From horms at verge.net.au  Fri May 24 20:59:08 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 09:59:08 +0900
Subject: [PATCH] ARM: shmobile: marzen: Use error values in usb_power_*
In-Reply-To: <519D217D.2060405@cogentembedded.com>
References: <1369205290-6272-1-git-send-email-horms+renesas@verge.net.au>
 <1369205290-6272-2-git-send-email-horms+renesas@verge.net.au>
 <519D217D.2060405@cogentembedded.com>
Message-ID: <20130525005908.GE4476@verge.net.au>

On Wed, May 22, 2013 at 11:50:21PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 05/22/2013 10:48 AM, Simon Horman wrote:
> 
> >This patch updates the marzen board code as if USB PHY isn't enabled
> >they phy will have a value set by ERR_PTR() rather than be NULL.
> >
> >Without this patch a NULL pointer dereference  and kernel panic
> >occurs on initialisation of USB on marzen.
> >
> >This resolves a regression introduced in 3.10-rc1 by
> >b7fa5c2aec5be083eb2719b405089703608e9bc6
> >("usb: phy: return -ENXIO when PHY layer isn't enabled").
> >
> >Tested-by: Nguyen Hong Ky <nh-ky at jinso.co.jp>
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >---
> >  arch/arm/mach-shmobile/board-marzen.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> >diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
> >index 9105285..b9594e9 100644
> >--- a/arch/arm/mach-shmobile/board-marzen.c
> >+++ b/arch/arm/mach-shmobile/board-marzen.c
> >@@ -212,8 +212,8 @@ static struct platform_device *marzen_devices[] __initdata = {
> >  static struct usb_phy *phy;
> >  static int usb_power_on(struct platform_device *pdev)
> >  {
> >-	if (!phy)
> >-		return -EIO;
> >+	if (IS_ERR(phy))
> 
>    And even before the mentioned commit the right check should have
> been IS_ERR_OR_NULL().

Yes, quite true.

> Thanks for finding/fixing this. Too bad I'll have to respin my USB
> patches now... :-)
> 
> WBR, Sergei
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From horms at verge.net.au  Fri May 24 21:01:02 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 10:01:02 +0900
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
 <20130522143204.GE32012@verge.net.au>
 <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
Message-ID: <20130525010102.GF4476@verge.net.au>

On Wed, May 22, 2013 at 07:22:59PM +0200, Guennadi Liakhovetski wrote:
> Hi Simon
> 
> On Wed, 22 May 2013, Simon Horman wrote:
> 
> > On Fri, May 17, 2013 at 03:00:23PM +0200, Guennadi Liakhovetski wrote:
> > > Hi Simon, Magnus
> > > 
> > > On Wed, 3 Apr 2013, Simon Horman wrote:
> > > 
> > > > From: Magnus Damm <damm at opensource.se>
> > > > 
> > > > Add LAN9220 support to the APE6EVM board using C and DT.
> > > > At this point the PFC driver lacks DT bindings so to
> > > > configure the PFC we use PINCTRL in C board code.
> > > > 
> > > > Signed-off-by: Magnus Damm <damm at opensource.se>
> > > > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > > > ---
> > > >  arch/arm/boot/dts/r8a73a4-ape6evm.dts  |   23 ++++++++++++++++++-
> > > >  arch/arm/mach-shmobile/board-ape6evm.c |   38 ++++++++++++++++++++++++++++++++
> > > >  2 files changed, 60 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > > index 833f703..f603c69 100644
> > > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > > @@ -16,7 +16,7 @@
> > > >  	compatible = "renesas,ape6evm", "renesas,r8a73a4";
> > > >  
> > > >  	chosen {
> > > > -		bootargs = "console=ttySC0,115200 ignore_loglevel";
> > > > +		bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
> > > >  	};
> > > >  
> > > >  	memory at 40000000 {
> > > > @@ -24,8 +24,29 @@
> > > >  		reg = <0 0x40000000 0 0x40000000>;
> > > >  	};
> > > >  
> > > > +	ape6evm_fixed_3v3: fixedregulator at 0 {
> > > > +		compatible = "regulator-fixed";
> > > > +		regulator-name = "3V3";
> > > > +		regulator-min-microvolt = <3300000>;
> > > > +		regulator-max-microvolt = <3300000>;
> > > > +		regulator-always-on;
> > > > +	};
> > > > +
> > > >  	lbsc {
> > > >  		#address-cells = <1>;
> > > >  		#size-cells = <1>;
> > > > +
> > > > +		ethernet at 8000000 {
> > > > +			compatible = "smsc,lan9118", "smsc,lan9115";
> > > > +			reg = <0x08000000 0x1000>;
> > > > +			interrupt-parent = <&irqc1>;
> > > > +			interrupts = <8 0x4>;
> > > > +			phy-mode = "mii";
> > > > +			reg-io-width = <4>;
> > > > +			smsc,irq-active-high;
> > > > +			smsc,irq-push-pull;
> > > > +			vdd33a-supply = <&ape6evm_fixed_3v3>;
> > > > +			vddvario-supply = <&ape6evm_fixed_3v3>;
> > > > +		};
> > > >  	};
> > > >  };
> > > 
> > > The above didn't work in my tests without this:
> > > 
> > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
> > > b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > index f603c69..4fb0102 100644
> > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > @@ -33,8 +33,10 @@
> > >  	};
> > >  
> > >  	lbsc {
> > > +		compatible = "simple-bus";
> > >  		#address-cells = <1>;
> > >  		#size-cells = <1>;
> > > +		ranges = <0 0 0 0x80000000>;
> > >  
> > >  		ethernet at 8000000 {
> > >  			compatible = "smsc,lan9118", "smsc,lan9115";
> > > 
> > 
> > Could you please post this as a formal patch and indicate
> > if you would like it included as a fix in v3.10 or not?
> 
> Can do that, sure, just thought maybe it would be better to fix the 
> original patch. Besides, I wasn't sure what the correct values for 
> "ranges" are, I just picked up something, that would be sufficient for 
> ethernet. But if more devices are added to it in the future, maybe 
> different ranges values would be needed. I think actually, lbsc should map 
> the 3 BSC areas, so, the correct property would be

I believe the original patches are past the point where they
can be updated.

With regards to the correct values, perhaps Magnus can help here?

> 
> +		ranges = <0 0 0 0x14000000>;
> 
> > Also, I am curious to know what your tests are.
> 
> Just booting with NFS root. I think, anything involving ethernet. Without 
> the "simple-bus" property the lbsc node doesn't get scanned, so, no device 
> is added. Without "ranges" addresses cannot be mapped correctly.

Ok, it sounds like it should be fixed for v3.10.


From horms at verge.net.au  Fri May 24 21:03:09 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 10:03:09 +0900
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <519F72F8.1000204@cogentembedded.com>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <519F72F8.1000204@cogentembedded.com>
Message-ID: <20130525010309.GG4476@verge.net.au>

On Fri, May 24, 2013 at 06:02:32PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 24-05-2013 6:06, Simon Horman wrote:
> 
> >Add SATA clock for r8a7790 SoC (for both device tree and usual cases).
> 
>     I don't see where you are adding clock for device tree case.
> 
> >Register SATA controller as a "late" platform device on r8a7790 SoC.
> 
>     Does R8A7790 have these "early" and "late" lists? I guess not.
> 
> >Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
> >Vladimir Barinov.
> 
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >---
> >  arch/arm/mach-shmobile/clock-r8a7790.c |  4 ++++
> >  arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++
> >  2 files changed, 25 insertions(+)
> 
> >diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> >index b393592..3619a52 100644
> >--- a/arch/arm/mach-shmobile/clock-r8a7790.c
> >+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> [...]
> >@@ -249,6 +252,7 @@ static struct clk_lookup lookups[] = {
> >  	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
> >  	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
> >  	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
> >+	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
> >  };
> >
> >  #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
> >diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> >index ed7ee24..5a2a073 100644
> >--- a/arch/arm/mach-shmobile/setup-r8a7790.c
> >+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> [...]
> >@@ -118,6 +119,25 @@ static inline void r8a7790_register_scif(int idx)
> >  				      sizeof(struct plat_sci_port));
> >  }
> >
> >+static __init void r8a7790_register_sata1(void)
> 
>    What's with SATA0?
> 
> >+{
> >+
> >+	struct resource res[] = {
> 
>    Non-static variable with an intializer? Won't this be a waste of
> code? Wouldn't it be better to have it static __initdata?

Sure, if you prefer that.

> 
> >+		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),
> 
>     2 megabytes? Won't it be a waste of memory?

2 megabytes is specified in the data sheet.
Do you think it is reasonable to use a smaller value?

> 
> >+		DEFINE_RES_IRQ(gic_iid(106)),
> >+	};
> >+
> >+	struct platform_device_info pdevinfo = {
> 
>    Same comment about non-static initialized structure...
> 
> >+		.name = "sata_rcar",
> >+		.id = 1,
> >+		.res = res,
> >+		.num_res = ARRAY_SIZE(res),
> >+		.dma_mask = DMA_BIT_MASK(32),
> >+	};
> >+
> >+	platform_device_register_full(&pdevinfo);
> >+}
> >+
> 
> WBR, Sergei
> 


From cdall at cs.columbia.edu  Fri May 24 21:12:00 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Fri, 24 May 2013 18:12:00 -0700
Subject: [v2] ARM: mm: Get rid of L_PTE_USER ref from PAGE_S2_DEVICE
Message-ID: <1369444320-28893-1-git-send-email-cdall@cs.columbia.edu>

THe L_PTE_USER actually has nothing to do with stage 2 mappings and the
L_PTE_S2_RDWR value sets the readable bit, which was what L_PTE_USER
was used for before proper handling of stage 2 memory defines.

Changelog:
 [v2]: Change default mappings to be r/w instead of r/o, as per Marc
       Zyngier's suggestion.

Cc: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>
---
 arch/arm/include/asm/pgtable.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262..8afc60c 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -97,7 +97,7 @@ extern pgprot_t		pgprot_s2_device;
 #define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_HYP)
 #define PAGE_HYP_DEVICE		_MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
 #define PAGE_S2			_MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
-#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)
 
 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
-- 
1.7.9.5



From cdall at cs.columbia.edu  Fri May 24 21:12:39 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Fri, 24 May 2013 18:12:39 -0700
Subject: [PATCH v2] ARM: mm: Get rid of L_PTE_USER ref from PAGE_S2_DEVICE
Message-ID: <1369444359-28962-1-git-send-email-cdall@cs.columbia.edu>

THe L_PTE_USER actually has nothing to do with stage 2 mappings and the
L_PTE_S2_RDWR value sets the readable bit, which was what L_PTE_USER
was used for before proper handling of stage 2 memory defines.

Changelog:
 [v2]: Change default mappings to be r/w instead of r/o, as per Marc
       Zyngier's suggestion.

Cc: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>
---
 arch/arm/include/asm/pgtable.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262..8afc60c 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -97,7 +97,7 @@ extern pgprot_t		pgprot_s2_device;
 #define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_HYP)
 #define PAGE_HYP_DEVICE		_MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
 #define PAGE_S2			_MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
-#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)
 
 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
-- 
1.7.9.5



From horms at verge.net.au  Fri May 24 21:24:34 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 10:24:34 +0900
Subject: [RFC/PATCH v2 0/2] R-Car GPIO DT bindings
In-Reply-To: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <20130525012434.GA24005@verge.net.au>

On Tue, May 21, 2013 at 01:40:04PM +0200, Laurent Pinchart wrote:
> Hello,
> 
> Here's the second version of the gpio-rcar driver DT bindings. I've tested the
> patches on the Marzen board (r8a7779).
> 
> Once again I'd appreciate feedback on the DT bindings. I'm particularly
> wondering whether getting the number of lines through the gpio-ranges property
> instead of using a dedicated #gpio-lines property as in v1 is a good idea.
> 
> Changes since v1:
> 
> - Initialize the gpiochip dev field at probe time.
> - Add the gpio-ranges property.
> - Remove the #gpio-lines property. The number of lines is now passed through
>   the gpio-ranges property.
> 
> Laurent Pinchart (2):
>   gpio-rcar: Make the platform data gpio_base field signed
>   gpio-rcar: Add DT support
> 
>  .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 52 +++++++++++++++++
>  drivers/gpio/gpio-rcar.c                           | 66 ++++++++++++++++++----
>  include/linux/platform_data/gpio-rcar.h            |  2 +-
>  3 files changed, 109 insertions(+), 11 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt

Hi Magnus,

could you please review these changes?


From horms at verge.net.au  Fri May 24 21:32:53 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 10:32:53 +0900
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: implement CPU clock scaling
 for CPUFreq
In-Reply-To: <Pine.LNX.4.64.1305211202380.2863@axis700.grange>
References: <Pine.LNX.4.64.1305211202380.2863@axis700.grange>
Message-ID: <20130525013252.GD24005@verge.net.au>

On Tue, May 21, 2013 at 12:09:53PM +0200, Guennadi Liakhovetski wrote:
> This patch adds support for the Z-clock on r8a7790 SoCs, which is driving
> the Cortex A15 core. Adding an "operating-points" property to the CPU0 DT
> node and a regulator, this patch allows platforms to use the generic
> cpufreq-cpu0 driver to use SoC's DVFS capabilities.
> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> ---
> 
> Since I cannot use the regulator, supplying the DVFS voltage to the CPU on 
> Lager, I only tested this patch without voltage adjustments, but that 
> shouldn't matter for this specific change. I did verify, using the 
> ondemand CPUFreq governor, that the frequency and the CPU performance 
> change, depending on CPU load.

Magnus,

could you please review this series?


From horms at verge.net.au  Fri May 24 21:34:45 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 10:34:45 +0900
Subject: [PATCH v2 1/2] ARM: shmobile: r8a7790: implement CPU clock
 scaling for CPUFreq
In-Reply-To: <Pine.LNX.4.64.1305211601180.2863@axis700.grange>
References: <Pine.LNX.4.64.1305211601180.2863@axis700.grange>
Message-ID: <20130525013445.GE24005@verge.net.au>

On Tue, May 21, 2013 at 04:07:46PM +0200, Guennadi Liakhovetski wrote:
> This patch adds support for the Z-clock on r8a7790 SoCs, which is driving
> the Cortex A15 core, and a "cpufreq-cpu0" platform device. Adding an
> "operating-points" property to the CPU0 DT node and a regulator, this
> patch allows platforms to use the generic cpufreq-cpu0 driver to use
> SoC's DVFS capabilities.
> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> ---
> 
> v2:
> 1. a typo in the r8a7790 datasheet confused me to implement kick-bit 
> handling wrongly, this is fixed in this version
> 2. patch 3 merged with this one
> 
> Same comments, as to v1 of this series, apply.

Magnus,

could you please review this series?

> 
>  arch/arm/mach-shmobile/Kconfig         |    2 +
>  arch/arm/mach-shmobile/clock-r8a7790.c |  129 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/setup-r8a7790.c |    1 +
>  3 files changed, 132 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
> index 0319cf9..97bc6cf 100644
> --- a/arch/arm/mach-shmobile/Kconfig
> +++ b/arch/arm/mach-shmobile/Kconfig
> @@ -60,6 +60,8 @@ config ARCH_R8A7790
>  	select ARM_ARCH_TIMER
>  	select SH_CLK_CPG
>  	select RENESAS_IRQC
> +	select ARCH_HAS_CPUFREQ
> +	select ARCH_HAS_OPP
>  
>  config ARCH_EMEV2
>  	bool "Emma Mobile EV2"
> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> index 53a13b4..0f2aa68 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> @@ -47,6 +47,9 @@
>  #define CPG_BASE 0xe6150000
>  #define CPG_LEN 0x1000
>  
> +#define FRQCRB   0xe6150004
> +#define FRQCRC   0xe61500e0
> +
>  #define SMSTPCR2 0xe6150138
>  #define SMSTPCR3 0xe615013c
>  #define SMSTPCR7 0xe615014c
> @@ -83,11 +86,132 @@ static struct clk main_clk = {
>   * clock ratio of these clock will be updated
>   * on r8a7790_clock_init()
>   */
> +SH_FIXED_RATIO_CLK_SET(pll0_clk,		main_clk,	1, 1);
>  SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
>  SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
>  SH_FIXED_RATIO_CLK_SET(lb_clk,			pll1_clk,	1, 1);
>  SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);
>  
> +/* If more clocks need to access FRQCRB, we'll have to lock eventually */
> +static int frqcr_kick_check(struct clk *clk)
> +{
> +	return ioread32(clk->mapped_reg) & BIT(31) ? -EBUSY : 0;
> +}
> +
> +static int frqcr_kick_do(struct clk *clk)
> +{
> +	int i;
> +
> +	/* set KICK bit in FRQCRB to update hardware setting, check success */
> +	iowrite32(ioread32(clk->mapped_reg) | BIT(31), clk->mapped_reg);
> +	for (i = 1000; i; i--)
> +		if (ioread32(clk->mapped_reg) & BIT(31))
> +			cpu_relax();
> +		else
> +			return 0;
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static int zclk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	void __iomem *frqcrc;
> +	int ret;
> +	unsigned long step, p_rate;
> +	u32 val;
> +
> +	if (!clk->parent || !__clk_get(clk->parent))
> +		return -ENODEV;
> +
> +	ret = frqcr_kick_check(clk);
> +	if (ret < 0)
> +		goto done;
> +
> +	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
> +
> +	p_rate = clk_get_rate(clk->parent);
> +	if (rate == p_rate) {
> +		val = 0;
> +	} else {
> +		step = DIV_ROUND_CLOSEST(p_rate, 32);
> +		val = 32 - rate / step;
> +	}
> +
> +	iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
> +		  (val << clk->enable_bit), frqcrc);
> +
> +	ret = frqcr_kick_do(clk);
> +
> +done:
> +	__clk_put(clk->parent);
> +	return ret;
> +}
> +
> +static long zclk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	/*
> +	 * theoretical rate = parent rate * multiplier / 32,
> +	 * where 1 <= multiplier <= 32. Therefore we should do
> +	 * multiplier = rate * 32 / parent rate
> +	 * rounded rate = parent rate * multiplier / 32.
> +	 * However, multiplication before division won't fit in 32 bits, so
> +	 * we sacrifice some precision by first dividing and then multiplying.
> +	 * To find the nearest divisor we calculate both and pick up the best
> +	 * one. This avoids 64-bit arithmetics.
> +	 */
> +	unsigned long step, mul_min, mul_max, rate_min, rate_max;
> +
> +	rate_max = clk_get_rate(clk->parent);
> +
> +	/* output freq <= parent */
> +	if (rate >= rate_max)
> +		return rate_max;
> +
> +	step = DIV_ROUND_CLOSEST(rate_max, 32);
> +	/* output freq >= parent / 32 */
> +	if (step >= rate)
> +		return step;
> +
> +	mul_min = rate / step;
> +	mul_max = DIV_ROUND_UP(rate, step);
> +	rate_min = step * mul_min;
> +	if (mul_max == mul_min)
> +		return rate_min;
> +
> +	rate_max = step * mul_max;
> +
> +	if (rate_max - rate <  rate - rate_min)
> +		return rate_max;
> +
> +	return rate_min;
> +}
> +
> +static unsigned long zclk_recalc(struct clk *clk)
> +{
> +	void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
> +	unsigned int max = clk->div_mask + 1;
> +	unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
> +			     clk->div_mask);
> +
> +	return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
> +		(max - val);
> +}
> +
> +static struct sh_clk_ops zclk_ops = {
> +	.recalc = zclk_recalc,
> +	.set_rate = zclk_set_rate,
> +	.round_rate = zclk_round_rate,
> +};
> +
> +static struct clk z_clk = {
> +	.parent = &pll0_clk,
> +	.div_mask = 0x1f,
> +	.enable_bit = 8,
> +	/* We'll need to access FRQCRB and FRQCRC */
> +	.enable_reg = (void __iomem *)FRQCRB,
> +	.ops = &zclk_ops,
> +};
> +
>  /* fixed ratio clock */
>  SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
>  SH_FIXED_RATIO_CLK_SET(cp_clk,			extal_clk,	1, 2);
> @@ -115,11 +239,13 @@ static struct clk *main_clks[] = {
>  	&extal_clk,
>  	&extal_div2_clk,
>  	&main_clk,
> +	&pll0_clk,
>  	&pll1_clk,
>  	&pll1_div2_clk,
>  	&pll3_clk,
>  	&lb_clk,
>  	&qspi_clk,
> +	&z_clk,
>  	&zg_clk,
>  	&zx_clk,
>  	&zs_clk,
> @@ -213,6 +339,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_CON_ID("pll1",		&pll1_clk),
>  	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),
>  	CLKDEV_CON_ID("pll3",		&pll3_clk),
> +	CLKDEV_DEV_ID("cpufreq-cpu0",	&z_clk),
>  	CLKDEV_CON_ID("zg",		&zg_clk),
>  	CLKDEV_CON_ID("zx",		&zx_clk),
>  	CLKDEV_CON_ID("zs",		&zs_clk),
> @@ -263,9 +390,11 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
>  };
>  
> +/* "/ 2" is a "fixed divider" - see the "PLL Multiplication Ratio" table */
>  #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
>  	extal_clk.rate	= e * 1000 * 1000;			\
>  	main_clk.parent	= m;					\
> +	SH_CLK_SET_RATIO(&pll0_clk_ratio, p0 / 2, 1);		\
>  	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);		\
>  	if (mode & MD(19))					\
>  		SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);	\
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> index eeef5f6..49c3166 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> @@ -166,6 +166,7 @@ void __init r8a7790_timer_init(void)
>  #ifdef CONFIG_USE_OF
>  void __init r8a7790_add_standard_devices_dt(void)
>  {
> +	platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
>  
> -- 
> 1.7.2.5
> 


From horms at verge.net.au  Fri May 24 21:53:36 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 10:53:36 +0900
Subject: [PATCH 1/2] ARM: shmobile: r8a7790: implement CPU clock scaling
 for CPUFreq
In-Reply-To: <20130525013252.GD24005@verge.net.au>
References: <Pine.LNX.4.64.1305211202380.2863@axis700.grange>
 <20130525013252.GD24005@verge.net.au>
Message-ID: <20130525015336.GK24005@verge.net.au>

On Sat, May 25, 2013 at 10:32:53AM +0900, Simon Horman wrote:
> On Tue, May 21, 2013 at 12:09:53PM +0200, Guennadi Liakhovetski wrote:
> > This patch adds support for the Z-clock on r8a7790 SoCs, which is driving
> > the Cortex A15 core. Adding an "operating-points" property to the CPU0 DT
> > node and a regulator, this patch allows platforms to use the generic
> > cpufreq-cpu0 driver to use SoC's DVFS capabilities.
> > 
> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> > ---
> > 
> > Since I cannot use the regulator, supplying the DVFS voltage to the CPU on 
> > Lager, I only tested this patch without voltage adjustments, but that 
> > shouldn't matter for this specific change. I did verify, using the 
> > ondemand CPUFreq governor, that the frequency and the CPU performance 
> > change, depending on CPU load.
> 
> Magnus,
> 
> could you please review this series?

I noticed there is a v2 of the series, could you review that instead?


From nico at fluxnic.net  Fri May 24 23:53:19 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 24 May 2013 23:53:19 -0400 (EDT)
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130523104303.GC16722@arm.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
Message-ID: <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>

On Thu, 23 May 2013, Catalin Marinas wrote:

> An issue is that for kunmap_atomic() && VIVT we flush the same page
> twice. I don't think we should remove the cache flushing in
> __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> don't work together).

VIVT and highmem do work together.  Highmem for ARM was in fact 
developed on such a platform.


Nicolas


From clbchenlibo.chen at huawei.com  Sat May 25 00:40:50 2013
From: clbchenlibo.chen at huawei.com (Libo Chen)
Date: Sat, 25 May 2013 12:40:50 +0800
Subject: [PATCH] module: use a macro instead of platform_driver_register
Message-ID: <51A040D2.20708@huawei.com>


I found a lot of mistakes using struct platform_driver without owner
so I make a macro instead of the function platform_driver_register.
It can set owner in it, then guys don`t care about module owner again.

Signed-off-by: Libo Chen <libo.chen at huawei.com>
---
 drivers/base/platform.c         |    8 +++++---
 include/linux/platform_device.h |    8 +++++++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 9eda842..ed75cf6 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -523,11 +523,13 @@ static void platform_drv_shutdown(struct device *_dev)
 }

 /**
- * platform_driver_register - register a driver for platform-level devices
+ * __platform_driver_register - register a driver for platform-level devices
  * @drv: platform driver structure
  */
-int platform_driver_register(struct platform_driver *drv)
+int __platform_driver_register(struct platform_driver *drv,
+				struct module *owner)
 {
+	drv->driver.owner = owner;
 	drv->driver.bus = &platform_bus_type;
 	if (drv->probe)
 		drv->driver.probe = platform_drv_probe;
@@ -538,7 +540,7 @@ int platform_driver_register(struct platform_driver *drv)

 	return driver_register(&drv->driver);
 }
-EXPORT_SYMBOL_GPL(platform_driver_register);
+EXPORT_SYMBOL_GPL(__platform_driver_register);

 /**
  * platform_driver_unregister - unregister a driver for platform-level devices
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 9abf1db..cd46ee5 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -180,7 +180,13 @@ struct platform_driver {
 	const struct platform_device_id *id_table;
 };

-extern int platform_driver_register(struct platform_driver *);
+/*
+ * use a macro to avoid include chaining to get THIS_MODULE
+ */
+#define platform_driver_register(drv) \
+	__platform_driver_register(drv, THIS_MODULE)
+extern int __platform_driver_register(struct platform_driver *,
+					struct module *);
 extern void platform_driver_unregister(struct platform_driver *);

 /* non-hotpluggable platform devices may use this so that probe() and
-- 
1.7.1




From horms at verge.net.au  Sat May 25 01:30:10 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 14:30:10 +0900
Subject: [PATCH v2] ARM: shmobile: BOCK-W: add Ether support
In-Reply-To: <201305170141.59791.sergei.shtylyov@cogentembedded.com>
References: <201305170141.59791.sergei.shtylyov@cogentembedded.com>
Message-ID: <20130525053007.GA9293@verge.net.au>

On Fri, May 17, 2013 at 01:41:59AM +0400, Sergei Shtylyov wrote:
> Register Ether device from bockw_init(), passing the platform data to it, adding
> only the RMII pin group to bockw_pinctrl_map[].  Although the LINK signal exists
> on the board, it's connected to the link/activity LED  output of the PHY, thus
> the link disappears and reappears after each packet. We'd be better off ignoring
> such signal and getting the link state from the PHY indirectly.
> 
> Also, Ether has pin conflict with VIN1, so the latter is not registered when the
> 'sh_eth' driver is enabled now.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> 
> ---
> The patch is atop of Simon's 'renesas.git' repo, 'renesas-next-20130515v2' tag
> and my recent yet unapplied patches.
> 
> Note that it's compile and run time dependent on the current Linus' tree. 
> 
> Changes from the original posting:
> - refreshed the patch.

Thanks, would it be possible for you to rebase it on top of
renesas-next-20130523.

renesas-next-20130523 is based on v3.10-rc2, so I think it should
have whatever dependencies that were in Linus's tree at the time
that you posted this patch.


From dirk.behme at gmail.com  Sat May 25 01:59:45 2013
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sat, 25 May 2013 07:59:45 +0200
Subject: clock framework: Don't disable a clock already enabled by boot
 loader?
In-Reply-To: <20130524230021.GF31135@pengutronix.de>
References: <519F60CA.6090302@de.bosch.com>
 <20130524230021.GF31135@pengutronix.de>
Message-ID: <51A05351.7000501@gmail.com>

Hi Sascha,

Am 25.05.2013 01:00, schrieb Sascha Hauer:
> Hi Dirk,
>
> On Fri, May 24, 2013 at 02:44:58PM +0200, Dirk Behme wrote:
>> Hi,
>>
>> we register a clock using clk_register_clkdev() etc already enabled
>> by a boot loader. We are doing only the clk_register_clkdev(), but
>> no clock_enable() etc on this clock.
>>
>> With this, enable_count for this clock is zero, while in fact it's
>> already on. I.e. the kernel doesn't know that it is on.
>>
>> This results in
>>
>> late_initcall(clk_disable_unused())
>>
>> disabling this clock because the kernel thinks it's unused.
>>
>> Is this the intended behavior?
>
> Yes, and it's great since after this point the hardware state is in sync
> with the enable counter.
>
>> Is there a way to let the kernel know
>> "the clock is enabled already, set enable_count != 0"? Or is the
>> only way to do this correctly calling clock_enable() on an already
>> enabled clock?
>
> You could set the CLK_IGNORE_UNUSED flag in the clock, but I suggest to
> just clk_get/clk_enable the clock in the driver using it.

Thanks for the fast answer! :)

Hmm, but what's the best way to set a flag in

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-imx/clk-imx6q.c

?

In mx6q_clocks_init() there doesn't seem to be an explicit interface 
to set the flags?

I'm not sure if

clk[xxx]->flags |= CLK_IGNORE_UNUSED;

is the way to go?

Best regards

Dirk



From horms+renesas at verge.net.au  Sat May 25 02:42:17 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 15:42:17 +0900
Subject: [GIT PULL] Renesas ARM sh73a0 SoC fix for v3.10 (repost)
Message-ID: <1369464138-21530-1-git-send-email-horms+renesas@verge.net.au>

[ Repost after hopefully resolving a local mail configuration problem ]

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-sh73a0-fixes-for-v3.10

for you to fetch changes up to 5f17a516534924d40e6e0a24dcfd06e397a68485:

  ARM: shmobile: sh73a0: Update CMT clockevent rating to 80 (2013-05-22 23:47:48 +0900)

----------------------------------------------------------------
Update CMT clock rating for sh73a0 SoC to resolve boot failure
on kzm9g-reference. This resolves a regression between v3.9 and v3.10-rc1.

----------------------------------------------------------------
Simon Horman (1):
      ARM: shmobile: sh73a0: Update CMT clockevent rating to 80

 arch/arm/mach-shmobile/setup-sh73a0.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


From horms+renesas at verge.net.au  Sat May 25 02:42:18 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 15:42:18 +0900
Subject: [PATCH] ARM: shmobile: sh73a0: Update CMT clockevent rating to 80
In-Reply-To: <1369464138-21530-1-git-send-email-horms+renesas@verge.net.au>
References: <1369464138-21530-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369464138-21530-2-git-send-email-horms+renesas@verge.net.au>

Update the CMT clockevent rating from 125 to 80.

This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
Avoid dummy clockevent being preferred over real").

The patch noted above reduces the rating of dummy clockevent from 400 to 100.
This patch reduces the rating of CMT so that it is once again less than that
of the dummy clockevent.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..9696f36 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
 	.name = "CMT10",
 	.channel_offset = 0x10,
 	.timer_bit = 0,
-	.clockevent_rating = 125,
+	.clockevent_rating = 80,
 	.clocksource_rating = 125,
 };
 
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sat May 25 02:45:00 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 15:45:00 +0900
Subject: [GIT PULL] Renesas ARM based SoC pinmux fix for v3.10 (repost)
Message-ID: <1369464301-22539-1-git-send-email-horms+renesas@verge.net.au>

[ Repost after hopefully resolving a local mail configuration problem ]

Hi Olof, Hi Arnd,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux-fixes2-for-v3.10

for you to fetch changes up to 16a31ebde0763580ed6891094249e1bd4a329be1:

  sh-pfc: r8a7779: Don't group USB OVC and PENC pins (2013-05-22 22:01:59 +0900)

----------------------------------------------------------------
Correction to USB OVC and PENC pin groupings on r8a7779 SoC.
This avoids conflicts when the USB_OVCn pins are used by another function.
This has been observed to be a problem in v3.10-rc1.

----------------------------------------------------------------
Laurent Pinchart (1):
      sh-pfc: r8a7779: Don't group USB OVC and PENC pins

 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   45 +++++++++++++++++++++++++++-------
 1 file changed, 36 insertions(+), 9 deletions(-)


From horms+renesas at verge.net.au  Sat May 25 02:45:01 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sat, 25 May 2013 15:45:01 +0900
Subject: [PATCH] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <1369464301-22539-1-git-send-email-horms+renesas@verge.net.au>
References: <1369464301-22539-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369464301-22539-2-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

The USB_OVCn pins are alternate options for USB over-current detection
when using a 3.3V USB interface. As they're not mandatory they can be
used independently of the USB PENC pins. Don't group the USB_OVCn and
PENC pins to avoid conflicts when the USB_OVCn pins are used by another
function.

Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   45 +++++++++++++++++++++++++++-------
 1 file changed, 36 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 791a671..8cd90e7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2357,27 +2357,48 @@ static const unsigned int sdhi3_wp_mux[] = {
 };
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
-	/* OVC */
-	150, 154,
+	/* PENC */
+	154,
 };
 static const unsigned int usb0_mux[] = {
-	USB_OVC0_MARK, USB_PENC0_MARK,
+	USB_PENC0_MARK,
+};
+static const unsigned int usb0_ovc_pins[] = {
+	/* USB_OVC */
+	150
+};
+static const unsigned int usb0_ovc_mux[] = {
+	USB_OVC0_MARK,
 };
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
-	/* OVC */
-	152, 155,
+	/* PENC */
+	155,
 };
 static const unsigned int usb1_mux[] = {
-	USB_OVC1_MARK, USB_PENC1_MARK,
+	USB_PENC1_MARK,
+};
+static const unsigned int usb1_ovc_pins[] = {
+	/* USB_OVC */
+	152,
+};
+static const unsigned int usb1_ovc_mux[] = {
+	USB_OVC1_MARK,
 };
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
-	/* OVC, PENC */
-	125, 156,
+	/* PENC */
+	156,
 };
 static const unsigned int usb2_mux[] = {
-	USB_OVC2_MARK, USB_PENC2_MARK,
+	USB_PENC2_MARK,
+};
+static const unsigned int usb2_ovc_pins[] = {
+	/* USB_OVC */
+	125,
+};
+static const unsigned int usb2_ovc_mux[] = {
+	USB_OVC2_MARK,
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
@@ -2501,8 +2522,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi3_cd),
 	SH_PFC_PIN_GROUP(sdhi3_wp),
 	SH_PFC_PIN_GROUP(usb0),
+	SH_PFC_PIN_GROUP(usb0_ovc),
 	SH_PFC_PIN_GROUP(usb1),
+	SH_PFC_PIN_GROUP(usb1_ovc),
 	SH_PFC_PIN_GROUP(usb2),
+	SH_PFC_PIN_GROUP(usb2_ovc),
 };
 
 static const char * const du0_groups[] = {
@@ -2683,14 +2707,17 @@ static const char * const sdhi3_groups[] = {
 
 static const char * const usb0_groups[] = {
 	"usb0",
+	"usb0_ovc",
 };
 
 static const char * const usb1_groups[] = {
 	"usb1",
+	"usb1_ovc",
 };
 
 static const char * const usb2_groups[] = {
 	"usb2",
+	"usb2_ovc",
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
-- 
1.7.10.4



From shawn.guo at linaro.org  Sat May 25 02:54:36 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 May 2013 14:54:36 +0800
Subject: clock framework: Don't disable a clock already enabled by boot
 loader?
In-Reply-To: <51A05351.7000501@gmail.com>
References: <519F60CA.6090302@de.bosch.com>
 <20130524230021.GF31135@pengutronix.de>
 <51A05351.7000501@gmail.com>
Message-ID: <20130525065434.GA7782@S2101-09.ap.freescale.net>

On Sat, May 25, 2013 at 07:59:45AM +0200, Dirk Behme wrote:
> Hmm, but what's the best way to set a flag in
> 
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-imx/clk-imx6q.c
> 
> ?
> 
> In mx6q_clocks_init() there doesn't seem to be an explicit interface
> to set the flags?
> 
> I'm not sure if
> 
> clk[xxx]->flags |= CLK_IGNORE_UNUSED;
> 
> is the way to go?
> 
Commit 1e43525 (clk: add clk_ignore_unused option to keep boot clocks
on) introduced an option "clk_ignore_unused" for bypassing
clk_disable_unused() call.

Shawn



From dirk.behme at gmail.com  Sat May 25 03:16:44 2013
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sat, 25 May 2013 09:16:44 +0200
Subject: clock framework: Don't disable a clock already enabled by boot
 loader?
In-Reply-To: <20130525065434.GA7782@S2101-09.ap.freescale.net>
References: <519F60CA.6090302@de.bosch.com>
 <20130524230021.GF31135@pengutronix.de> <51A05351.7000501@gmail.com>
 <20130525065434.GA7782@S2101-09.ap.freescale.net>
Message-ID: <51A0655C.4020309@gmail.com>

Am 25.05.2013 08:54, schrieb Shawn Guo:
> On Sat, May 25, 2013 at 07:59:45AM +0200, Dirk Behme wrote:
>> Hmm, but what's the best way to set a flag in
>>
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-imx/clk-imx6q.c
>>
>> ?
>>
>> In mx6q_clocks_init() there doesn't seem to be an explicit interface
>> to set the flags?
>>
>> I'm not sure if
>>
>> clk[xxx]->flags |= CLK_IGNORE_UNUSED;
>>
>> is the way to go?
>>
> Commit 1e43525 (clk: add clk_ignore_unused option to keep boot clocks
> on) introduced an option "clk_ignore_unused" for bypassing
> clk_disable_unused() call.

Yes, I know ;) But this is slightly different: In the end it disables 
the complete clk_disable_unused() call, i.e. for all unused clocks.

I'd like to set the flag CLK_IGNORE_UNUSED for just one clock. I.e. I 
want to set a flag for an i.MX6 clock, and I want to set it only for 
one clock.

What's the preferred way to do this?

Best regards

Dirk



From alexandre.belloni at free-electrons.com  Sat May 25 03:26:56 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Sat, 25 May 2013 09:26:56 +0200
Subject: [PATCH] ARM: at91: Fix link breakage when !CONFIG_PHY
In-Reply-To: <1369433942-12386-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369433942-12386-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <51A067C0.4040104@free-electrons.com>

Hi,

Scrap that, I'll send a v2.

Regards

On 25/05/2013 00:19, Alexandre Belloni wrote:
> Fixes:
> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> :(.text+0x1174): undefined reference to `mdiobus_write'
> :(.text+0x1188): undefined reference to `mdiobus_write'
> :(.text+0x119c): undefined reference to `mdiobus_write'
> :(.text+0x11b0): undefined reference to `mdiobus_write'
> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> :(.init.text+0x1e34): undefined reference to
> `phy_register_fixup_for_uid'
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
> ---
>  arch/arm/mach-at91/board-dt-sama5.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> index 705305e..f510381 100644
> --- a/arch/arm/mach-at91/board-dt-sama5.c
> +++ b/arch/arm/mach-at91/board-dt-sama5.c
> @@ -38,6 +38,7 @@ static void __init at91_dt_init_irq(void)
>  	of_irq_init(irq_of_match);
>  }
>  
> +#ifdef CONFIG_PHY
>  static int ksz9021rn_phy_fixup(struct phy_device *phy)
>  {
>  	int value;
> @@ -59,12 +60,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
>  
>  	return 0;
>  }
> +#endif
>  
>  static void __init sama5_dt_device_init(void)
>  {
> +#ifdef CONFIG_PHY
>  	if (of_machine_is_compatible("atmel,sama5d3xcm"))
>  		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
>  			ksz9021rn_phy_fixup);
> +#endif
>  
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From alexandre.belloni at free-electrons.com  Sat May 25 03:39:02 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Sat, 25 May 2013 09:39:02 +0200
Subject: [PATCH v2] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
Message-ID: <1369467542-25519-1-git-send-email-alexandre.belloni@free-electrons.com>

Fixes:
arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'

when CONFIG_PHYLIB is not selected.
---
Changes in v2:
	use IS_BUILTIN
	use CONFIG_PHYLIB and not CONFIG_PHY


 arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..e9ce541 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 #define GMII_ERCR	11
 #define GMII_ERDWR	12
 
-	/* Set delay values */
-	value = GMII_RCCPSR | 0x8000;
-	phy_write(phy, GMII_ERCR, value);
-	value = 0xF2F4;
-	phy_write(phy, GMII_ERDWR, value);
-	value = GMII_RRDPSR | 0x8000;
-	phy_write(phy, GMII_ERCR, value);
-	value = 0x2222;
-	phy_write(phy, GMII_ERDWR, value);
+	if (IS_BUILTIN(CONFIG_PHYLIB)) {
+		/* Set delay values */
+		value = GMII_RCCPSR | 0x8000;
+		phy_write(phy, GMII_ERCR, value);
+		value = 0xF2F4;
+		phy_write(phy, GMII_ERDWR, value);
+		value = GMII_RRDPSR | 0x8000;
+		phy_write(phy, GMII_ERCR, value);
+		value = 0x2222;
+		phy_write(phy, GMII_ERDWR, value);
+	}
 
 	return 0;
 }
 
 static void __init sama5_dt_device_init(void)
 {
-	if (of_machine_is_compatible("atmel,sama5d3xcm"))
+	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 			ksz9021rn_phy_fixup);
 
-- 
1.8.1.2



From linus.walleij at linaro.org  Sat May 25 05:09:54 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 25 May 2013 11:09:54 +0200
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
In-Reply-To: <519F8B02.1080000@wwwdotorg.org>
References: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
 <519A8A57.9060007@wwwdotorg.org>
 <CACRpkdZieCmFnHCGUkv8EqcAtb3DA7dSZpimSdB4P81tZPJRoQ@mail.gmail.com>
 <519F8B02.1080000@wwwdotorg.org>
Message-ID: <CACRpkdYxvBvYAnmp-p5WwB3QD0rd83qDcdg-BMhN7-2Jv8Oo_w@mail.gmail.com>

On Fri, May 24, 2013 at 5:45 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 05/24/2013 02:04 AM, Linus Walleij wrote:

>> Prevention of module unloading of pin controllers has never
>> been working properly, as there is no way to release the
>> pinctrl handles taken by different drivers.
>>
>> I think that is why most pin controller drivers are bool rather
>> than tristate.
>
> Once we get to multi-platform distro kernels, we will probably want all
> the pinctrl drivers to be modules so only the correct one gets loaded
> from an initrd. Hence, we'll want to move things to tristate rather than
> away from it.

OK ... As some kind of excuse I think the current situation is an
outgrowth of the fact that all the custom set-up used to be in machines
down in arch/arm/* and inevitably done at machine init.

> If we know the pinctrl subsystem doesn't yet work correctly with module
> unloads, should we modify pinctrl_register() to simply take a lock on
> the driver module and never drop it, so that we guarantee we don't try
> to unload the module later? Or, is this effectively already in place?

Hm, it won't happen with anything but pinctrl-single for sure.
But I know that Tony used it at one point, however I still
suspect that he was only using hogs.

We should maybe take the lock at the instant we instatiate a
pinctrl handle from something else than a hog, so as to mark
that we then have external dependencies that make unloading
impossible.

But it'd be even cooler to actually just iterate over the
pinctrl_list och handles and orphan them, and later recouple
them if a driver is loaded back in.

It can surely be done, but at the cost of introducing a state
lock in struct pinctrl and some pieces of hairy code in the
core.

Yours,
Linus Walleij


From maz at misterjones.org  Sat May 25 06:02:33 2013
From: maz at misterjones.org (Marc Zyngier)
Date: Sat, 25 May 2013 12:02:33 +0200
Subject: [PATCH v2] ARM: mm: Get rid of
 =?UTF-8?Q?L=5FPTE=5FUSER=20ref=20from?=
 =?UTF-8?Q?=20PAGE=5FS=32=5FDEVICE?=
In-Reply-To: <1369444359-28962-1-git-send-email-cdall@cs.columbia.edu>
References: <1369444359-28962-1-git-send-email-cdall@cs.columbia.edu>
Message-ID: <b727cb23668cb98294ef0a75b31b38e6@localhost>

On Fri, 24 May 2013 18:12:39 -0700, Christoffer Dall
<cdall at cs.columbia.edu> wrote:
> THe L_PTE_USER actually has nothing to do with stage 2 mappings and the
> L_PTE_S2_RDWR value sets the readable bit, which was what L_PTE_USER
> was used for before proper handling of stage 2 memory defines.
> 
> Changelog:
>  [v2]: Change default mappings to be r/w instead of r/o, as per Marc
>        Zyngier's suggestion.
> 
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>
> ---
>  arch/arm/include/asm/pgtable.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/pgtable.h
> b/arch/arm/include/asm/pgtable.h
> index 9bcd262..8afc60c 100644
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -97,7 +97,7 @@ extern pgprot_t		pgprot_s2_device;
>  #define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_HYP)
>  #define PAGE_HYP_DEVICE		_MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
>  #define PAGE_S2			_MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
> -#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_USER |
> L_PTE_S2_RDONLY)
> +#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)
>  
>  #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN
|
>  L_PTE_NONE)
>  #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)

Actually, there's a much better solution.

Just get rid of PAGE_S2_DEVICE altogether, as it is completely useless. We
never have to enforce a memory type in S2 that is stronger than the guest's
view. If the guest insists on doing something silly (mapping a device as
normal memory, for example), we really don't have to fix things for them.

See the patch I posted a while ago as part of my pending fixes series:
https://lists.cs.columbia.edu/pipermail/kvmarm/2013-May/005827.html

        M.
-- 
Who you jivin' with that Cosmik Debris?


From carlo.caione at gmail.com  Sat May 25 06:59:27 2013
From: carlo.caione at gmail.com (Carlo Caione)
Date: Sat, 25 May 2013 12:59:27 +0200
Subject: [PATCH v3] ARM: sunxi: New watchdog driver for Allwinner A10/A13
Message-ID: <1369479567-15104-1-git-send-email-carlo.caione@gmail.com>

This patch adds the driver for the watchdog found in the Allwinner A10 and
A13 SoCs. It has DT-support and uses the new watchdog framework.

Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
---
 drivers/watchdog/Kconfig     |  10 ++
 drivers/watchdog/Makefile    |   1 +
 drivers/watchdog/sunxi_wdt.c | 224 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 235 insertions(+)
 create mode 100644 drivers/watchdog/sunxi_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e89fc31..8ad2238 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -299,6 +299,16 @@ config ORION_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called orion_wdt.
 
+config SUNXI_WATCHDOG
+	tristate "Allwinner SoCs watchdog support"
+	depends on ARCH_SUNXI
+	select WATCHDOG_CORE
+	help
+	  Say Y here to include support for the watchdog timer
+	  in Allwinner SoCs.
+	  To compile this driver as a module, choose M here: the
+	  module will be called sunxi_wdt.
+
 config COH901327_WATCHDOG
 	bool "ST-Ericsson COH 901 327 watchdog"
 	depends on ARCH_U300
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a300b94..5012d5f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
 obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
 obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
+obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
 obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
 obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
new file mode 100644
index 0000000..270d41e
--- /dev/null
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -0,0 +1,224 @@
+/*
+ *      sunxi Watchdog Driver
+ *
+ *      Copyright (c) 2013 Carlo Caione <carlo.caione at gmail.com>
+ *                    2012 Henrik Nordstrom <henrik at henriknordstrom.net>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Based on xen_wdt.c
+ *      (c) Copyright 2010 Novell, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/watchdog.h>
+
+#define WDT_MAX_TIMEOUT         16
+#define WDT_MIN_TIMEOUT         1
+#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
+#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
+
+#define WDT_CTRL                0x00
+#define WDT_CTRL_RELOAD         ((1 << 0) | (0x0a57 << 1))
+
+#define WDT_MODE                0x04
+#define WDT_MODE_EN             (1 << 0)
+#define WDT_MODE_RST_EN         (1 << 1)
+
+#define DRV_NAME		"sunxi-wdt"
+#define DRV_VERSION		"1.0"
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+static int heartbeat = WDT_MAX_TIMEOUT;
+
+/*
+ * wdt_timeout_map maps the watchdog timer interval value in seconds to
+ * the value of the register WDT_MODE bit 3:6
+ *
+ * [timeout seconds] = register value
+ *
+ */
+
+static const int wdt_timeout_map[] = {
+	[1] = 0b0001,  /* 1s  */
+	[2] = 0b0010,  /* 2s  */
+	[3] = 0b0011,  /* 3s  */
+	[4] = 0b0100,  /* 4s  */
+	[5] = 0b0101,  /* 5s  */
+	[6] = 0b0110,  /* 6s  */
+	[8] = 0b0111,  /* 8s  */
+	[10] = 0b1000, /* 10s */
+	[12] = 0b1001, /* 12s */
+	[14] = 0b1010, /* 14s */
+	[16] = 0b1011, /* 16s */
+};
+
+static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	iowrite32(WDT_CTRL_RELOAD, wdt_base + WDT_CTRL);
+
+	return 0;
+}
+
+static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
+		unsigned int timeout)
+{
+	u32 reg;
+	int ret = 0;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout])) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	sunxi_wdt_dev->timeout = timeout;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg &= ~(WDT_TIMEOUT_MASK);
+	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	sunxi_wdt_ping(sunxi_wdt_dev);
+
+exit:
+	return ret;
+}
+
+static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	iowrite32(0, wdt_base + WDT_MODE);
+
+	return 0;
+}
+
+static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	int ret = 0;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
+	if (ret < 0)
+		goto exit;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+exit:
+	return ret;
+}
+
+static const struct watchdog_info sunxi_wdt_info = {
+	.identity	= DRV_NAME,
+	.options	= WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING |
+			  WDIOF_MAGICCLOSE,
+};
+
+static const struct watchdog_ops sunxi_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= sunxi_wdt_start,
+	.stop		= sunxi_wdt_stop,
+	.ping		= sunxi_wdt_ping,
+	.set_timeout	= sunxi_wdt_set_timeout,
+};
+
+static struct watchdog_device sunxi_wdt_dev = {
+	.info		= &sunxi_wdt_info,
+	.ops		= &sunxi_wdt_ops,
+	.timeout	= WDT_MAX_TIMEOUT,
+	.max_timeout	= WDT_MAX_TIMEOUT,
+	.min_timeout	= WDT_MIN_TIMEOUT,
+};
+
+static int __init sunxi_wdt_probe(struct platform_device *pdev)
+{
+	int err;
+	void __iomem *wdt_base;
+
+	wdt_base = of_iomap(pdev->dev.of_node, 0);
+	if (unlikely(!wdt_base)) {
+		err = -ENOMEM;
+		goto error_mem_out;
+	}
+
+	sunxi_wdt_dev.parent = &pdev->dev;
+	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
+	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
+
+	err = watchdog_register_device(&sunxi_wdt_dev);
+	if (unlikely(err))
+		goto error_wdt;
+
+	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
+
+	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
+			sunxi_wdt_dev.timeout, nowayout);
+	return 0;
+
+error_wdt:
+	iounmap(wdt_base);
+error_mem_out:
+	return err;
+}
+
+static int __exit sunxi_wdt_remove(struct platform_device *pdev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
+
+	sunxi_wdt_stop(&sunxi_wdt_dev);
+	watchdog_unregister_device(&sunxi_wdt_dev);
+	iounmap(wdt_base);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_wdt_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-wdt" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
+
+static struct platform_driver sunxi_wdt_driver = {
+	.probe		= sunxi_wdt_probe,
+	.remove		= sunxi_wdt_remove,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= DRV_NAME,
+		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
+	},
+};
+
+module_platform_driver(sunxi_wdt_driver);
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
+
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
+		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
+MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
+MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
+MODULE_VERSION(DRV_VERSION);
-- 
1.8.2.3



From dt.tangr at gmail.com  Sat May 25 07:08:01 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:01 +1000
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
Message-ID: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>

Changes between http://archive.arm.linux.org.uk/lurker/message/20130408.113343.585af217.en.html and v2:
* Added new drivers to support the irqchip and timers on older models.
* Added new device trees to support the other models.

Changes between v2 and v3:
* Clean up keypad driver
* Update copyright messages (2012->2013)
* Added clock driver
* Fix keypad support for classic models
* Fix nspire-classic-timer code to use updated CLOCKSOURCE_OF_DECLARE
* Change CLCD code to use panel capabilities
* Change UART clock to match APB speed
* Support for reset

Changes between v3 and v4:
* Remove redundant clock-names in device tree
* Re-enable bus access to some peripherals on bootup
* Clean up nspire-classic-timer code.
  - Implement a nspire_timer_set_mode function
  - Removed messy IO_MATCHx and CNTL_MATCHx macros
  - Timer starts disabled to begin with
  - Interrupt handling code return IRQ_NONE for spurious interrupts
  - Delete unnessecary shift
* Change clk-nspire to use compatible property to determine IO type
* Change device tree bindings to have appropriate vendor prefixes
* Added device tree binding documentation
* Fix incorrect register addresses for clocks
* Use more specific .caps for CLCD

Daniel Tang (6):
  arm: TI-Nspire platform code
  arm: TI-Nspire device trees
  clk: TI-Nspire clock drivers
  clocksource: TI-Nspire timer support
  input: TI-Nspire keypad support
  irqchip: TI-Nspire irqchip support

 .../devicetree/bindings/clock/nspire-clock.txt     |  24 ++
 .../devicetree/bindings/input/ti,nspire-keypad.txt |  60 ++++
 .../interrupt-controller/lsi,zevio-intc.txt        |  18 ++
 .../devicetree/bindings/timer/lsi,zevio-timer.txt  |  33 +++
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Kconfig.debug                             |  16 ++
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   3 +
 arch/arm/boot/dts/nspire-classic.dtsi              |  74 +++++
 arch/arm/boot/dts/nspire-clp.dts                   |  45 +++
 arch/arm/boot/dts/nspire-cx.dts                    | 112 ++++++++
 arch/arm/boot/dts/nspire-tp.dts                    |  44 +++
 arch/arm/boot/dts/nspire.dtsi                      | 175 ++++++++++++
 arch/arm/include/debug/nspire.S                    |  28 ++
 arch/arm/mach-nspire/Kconfig                       |  15 +
 arch/arm/mach-nspire/Makefile                      |   2 +
 arch/arm/mach-nspire/Makefile.boot                 |   0
 arch/arm/mach-nspire/clcd.c                        | 119 ++++++++
 arch/arm/mach-nspire/clcd.h                        |  14 +
 arch/arm/mach-nspire/mmio.h                        |  23 ++
 arch/arm/mach-nspire/nspire.c                      | 117 ++++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-nspire.c                           | 155 ++++++++++
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/zevio-timer.c                  | 231 +++++++++++++++
 drivers/input/keyboard/Kconfig                     |  10 +
 drivers/input/keyboard/Makefile                    |   1 +
 drivers/input/keyboard/nspire-keypad.c             | 315 +++++++++++++++++++++
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-zevio.c                        | 177 ++++++++++++
 31 files changed, 1818 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/nspire-clock.txt
 create mode 100644 Documentation/devicetree/bindings/input/ti,nspire-keypad.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt
 create mode 100644 Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt
 create mode 100644 arch/arm/boot/dts/nspire-classic.dtsi
 create mode 100644 arch/arm/boot/dts/nspire-clp.dts
 create mode 100644 arch/arm/boot/dts/nspire-cx.dts
 create mode 100644 arch/arm/boot/dts/nspire-tp.dts
 create mode 100644 arch/arm/boot/dts/nspire.dtsi
 create mode 100644 arch/arm/include/debug/nspire.S
 create mode 100644 arch/arm/mach-nspire/Kconfig
 create mode 100644 arch/arm/mach-nspire/Makefile
 create mode 100644 arch/arm/mach-nspire/Makefile.boot
 create mode 100644 arch/arm/mach-nspire/clcd.c
 create mode 100644 arch/arm/mach-nspire/clcd.h
 create mode 100644 arch/arm/mach-nspire/mmio.h
 create mode 100644 arch/arm/mach-nspire/nspire.c
 create mode 100644 drivers/clk/clk-nspire.c
 create mode 100644 drivers/clocksource/zevio-timer.c
 create mode 100644 drivers/input/keyboard/nspire-keypad.c
 create mode 100644 drivers/irqchip/irq-zevio.c

--
1.8.1.3



From dt.tangr at gmail.com  Sat May 25 07:08:02 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:02 +1000
Subject: [RFC PATCHv4 1/6] arm: TI-Nspire platform code
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1369480087-24786-2-git-send-email-dt.tangr@gmail.com>

Add initial platform support for the TI-Nspire series.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 arch/arm/Kconfig                   |   2 +
 arch/arm/Kconfig.debug             |  16 +++++
 arch/arm/Makefile                  |   1 +
 arch/arm/include/debug/nspire.S    |  28 +++++++++
 arch/arm/mach-nspire/Kconfig       |  15 +++++
 arch/arm/mach-nspire/Makefile      |   2 +
 arch/arm/mach-nspire/Makefile.boot |   0
 arch/arm/mach-nspire/clcd.c        | 119 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-nspire/clcd.h        |  14 +++++
 arch/arm/mach-nspire/mmio.h        |  23 +++++++
 arch/arm/mach-nspire/nspire.c      | 117 ++++++++++++++++++++++++++++++++++++
 11 files changed, 337 insertions(+)
 create mode 100644 arch/arm/include/debug/nspire.S
 create mode 100644 arch/arm/mach-nspire/Kconfig
 create mode 100644 arch/arm/mach-nspire/Makefile
 create mode 100644 arch/arm/mach-nspire/Makefile.boot
 create mode 100644 arch/arm/mach-nspire/clcd.c
 create mode 100644 arch/arm/mach-nspire/clcd.h
 create mode 100644 arch/arm/mach-nspire/mmio.h
 create mode 100644 arch/arm/mach-nspire/nspire.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..86a3ed9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -964,6 +964,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-nspire/Kconfig"
+
 source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908..fe07941 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -309,6 +309,20 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on MVEBU based platforms.
 
+	config DEBUG_NSPIRE_CLASSIC_UART
+		bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
+		depends on ARCH_NSPIRE
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on TI-NSPIRE classic models.
+
+	config DEBUG_NSPIRE_CX_UART
+		bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
+		depends on ARCH_NSPIRE
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on TI-NSPIRE CX models.
+
 	config DEBUG_NOMADIK_UART
 		bool "Kernel low-level debugging messages via NOMADIK UART"
 		depends on ARCH_NOMADIK
@@ -633,6 +647,8 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_IMX53_UART ||\
 				 DEBUG_IMX6Q_UART
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
+	default "debug/nspire.S" if 	DEBUG_NSPIRE_CX_UART || \
+					DEBUG_NSPIRE_CLASSIC_UART
 	default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
 	default "debug/nomadik.S" if DEBUG_NOMADIK_UART
 	default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1ba358b..b4615aa 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -164,6 +164,7 @@ machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_NETX)		+= netx
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
 machine-$(CONFIG_ARCH_OMAP1)		+= omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 0000000..886fd27
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
+/*
+ *	linux/arch/arm/include/debug/nspire.S
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE	   0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE	   0xfee20000
+
+.macro	addruart, rp, rv, tmp
+	ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE)		@ physical base address
+	ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE)		@ virtual base address
+.endm
+
+
+#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
+#include <asm/hardware/debug-pl01x.S>
+#endif
+
+#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
+#endif
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 0000000..a295b18
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_NSPIRE
+	bool "TI-NSPIRE based"
+	depends on ARCH_MULTI_V4_V5
+	depends on MMU
+	select CPU_ARM926T
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select SPARSE_IRQ
+	select ARM_AMBA
+	select ARM_VIC
+	select ARM_TIMER_SP804
+	select USE_OF
+	select CLKSRC_OF
+	help
+	  This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 0000000..1bec256
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
+obj-y				+= nspire.o
+obj-y				+= clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 0000000..abea126
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,119 @@
+/*
+ *	linux/arch/arm/mach-nspire/clcd.c
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/dma-mapping.h>
+
+static struct clcd_panel nspire_cx_lcd_panel = {
+	.mode		= {
+		.name		= "Color LCD",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.sync		= 0,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.pixclock	= 1,
+		.hsync_len	= 6,
+		.vsync_len	= 1,
+		.right_margin	= 50,
+		.left_margin	= 38,
+		.lower_margin	= 3,
+		.upper_margin	= 17,
+	},
+	.width		= 65, /* ~6.50 cm */
+	.height		= 49, /* ~4.87 cm */
+	.tim2		= TIM2_IPC,
+	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
+	.bpp		= 16,
+	.caps		= CLCD_CAP_565,
+};
+
+static struct clcd_panel nspire_classic_lcd_panel = {
+	.mode		= {
+		.name		= "Grayscale LCD",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.pixclock	= 1,
+		.hsync_len	= 6,
+		.vsync_len	= 1,
+		.right_margin	= 6,
+		.left_margin	= 6,
+	},
+	.width		= 71, /* 7.11cm */
+	.height		= 53, /* 5.33cm */
+	.tim2		= 0x80007d0,
+	.cntl		= CNTL_LCDMONO8,
+	.bpp		= 8,
+	.grayscale	= 1,
+	.caps		= CLCD_CAP_5551,
+};
+
+int nspire_clcd_setup(struct clcd_fb *fb)
+{
+	struct clcd_panel *panel;
+	size_t panel_size;
+	const char *type;
+	dma_addr_t dma;
+	int err;
+
+	BUG_ON(!fb->dev->dev.of_node);
+
+	err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
+	if (err) {
+		pr_err("CLCD: Could not find lcd-type property\n");
+		return err;
+	}
+
+	if (!strcmp(type, "cx")) {
+		panel = &nspire_cx_lcd_panel;
+	} else if (!strcmp(type, "classic")) {
+		panel = &nspire_classic_lcd_panel;
+	} else {
+		pr_err("CLCD: Unknown lcd-type %s\n", type);
+		return -EINVAL;
+	}
+
+	panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
+	panel_size = ALIGN(panel_size, PAGE_SIZE);
+
+	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+		panel_size, &dma, GFP_KERNEL);
+
+	if (!fb->fb.screen_base) {
+		pr_err("CLCD: unable to map framebuffer\n");
+		return -ENOMEM;
+	}
+
+	fb->fb.fix.smem_start = dma;
+	fb->fb.fix.smem_len = panel_size;
+	fb->panel = panel;
+
+	return 0;
+}
+
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+	return dma_mmap_writecombine(&fb->dev->dev, vma,
+		fb->fb.screen_base, fb->fb.fix.smem_start,
+		fb->fb.fix.smem_len);
+}
+
+void nspire_clcd_remove(struct clcd_fb *fb)
+{
+	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+		fb->fb.screen_base, fb->fb.fix.smem_start);
+}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 0000000..8c33d2c
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
+/*
+ *	linux/arch/arm/mach-nspire/clcd.h
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+int nspire_clcd_setup(struct clcd_fb *fb);
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
+void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 0000000..4de63fc
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,23 @@
+/*
+ *	linux/arch/arm/mach-nspire/mmio.h
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE	0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE	0xFEE20000
+
+#define NSPIRE_MISC_PHYS_BASE		0x900A0000
+#define NSPIRE_MISC_HWRESET		0x08
+
+#define NSPIRE_PWR_PHYS_BASE		0x900B0000
+#define NSPIRE_PWR_VIRT_BASE		0xFEEB0000
+#define NSPIRE_PWR_BUS_DISABLE1		0x18
+#define NSPIRE_PWR_BUS_DISABLE2		0x20
+
+#define NSPIRE_LCD_PHYS_BASE		0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 0000000..d26c46d
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,117 @@
+/*
+ *	linux/arch/arm/mach-nspire/nspire.c
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-vic.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/hardware/timer-sp.h>
+
+#include "mmio.h"
+#include "clcd.h"
+
+static const char *nspire_dt_match[] __initconst = {
+	"ti,nspire",
+	"ti,nspire-cx",
+	"ti,nspire-tp",
+	"ti,nspire-clp",
+	NULL,
+};
+
+static struct map_desc nspire_io_desc[] __initdata = {
+	{
+		.virtual	=  NSPIRE_EARLY_UART_VIRT_BASE,
+		.pfn		= __phys_to_pfn(NSPIRE_EARLY_UART_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	},
+	{
+		.virtual	=  NSPIRE_PWR_VIRT_BASE,
+		.pfn		= __phys_to_pfn(NSPIRE_PWR_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}
+};
+
+static void __init nspire_map_io(void)
+{
+	iotable_init(nspire_io_desc, ARRAY_SIZE(nspire_io_desc));
+}
+
+static struct clcd_board nspire_clcd_data = {
+	.name		= "LCD",
+	.caps		= CLCD_CAP_5551 | CLCD_CAP_565,
+	.check		= clcdfb_check,
+	.decode		= clcdfb_decode,
+	.setup		= nspire_clcd_setup,
+	.mmap		= nspire_clcd_mmap,
+	.remove		= nspire_clcd_remove,
+};
+
+
+static struct of_dev_auxdata nspire_auxdata[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
+			NULL, &nspire_clcd_data),
+	{ }
+};
+
+static void __init nspire_early_init(void)
+{
+	void __iomem *pwr = IOMEM(NSPIRE_PWR_VIRT_BASE);
+
+	/* Re-enable bus access to all peripherals */
+	writel(0, pwr + NSPIRE_PWR_BUS_DISABLE1);
+	writel(0, pwr + NSPIRE_PWR_BUS_DISABLE2);
+
+	pr_info("Re-enabled bus access to all peripherals\n");
+}
+
+static void __init nspire_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			nspire_auxdata, NULL);
+}
+
+static void __init nspire_init_time(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+static void nspire_restart(char mode, const char *cmd)
+{
+	void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
+	if (!base)
+		return;
+
+	writel(2, base + NSPIRE_MISC_HWRESET);
+}
+
+DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
+	.map_io		= nspire_map_io,
+	.init_irq	= irqchip_init,
+	.init_time	= nspire_init_time,
+	.init_machine	= nspire_init,
+	.init_early	= nspire_early_init,
+	.dt_compat	= nspire_dt_match,
+	.restart	= nspire_restart,
+MACHINE_END
-- 
1.8.1.3



From dt.tangr at gmail.com  Sat May 25 07:08:03 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:03 +1000
Subject: [RFC PATCHv4 2/6] arm: TI-Nspire device trees
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1369480087-24786-3-git-send-email-dt.tangr@gmail.com>

Include device trees for the TI-Nspire.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 arch/arm/boot/dts/Makefile                         |   3 +
 arch/arm/boot/dts/nspire-classic.dtsi              |  74 +++++++++
 arch/arm/boot/dts/nspire-clp.dts                   |  45 ++++++
 arch/arm/boot/dts/nspire-cx.dts                    | 112 +++++++++++++
 arch/arm/boot/dts/nspire-tp.dts                    |  44 ++++++
 arch/arm/boot/dts/nspire.dtsi                      | 175 +++++++++++++++++++++
 7 files changed, 454 insertions(+)
 create mode 100644 arch/arm/boot/dts/nspire-classic.dtsi
 create mode 100644 arch/arm/boot/dts/nspire-clp.dts
 create mode 100644 arch/arm/boot/dts/nspire-cx.dts
 create mode 100644 arch/arm/boot/dts/nspire-tp.dts
 create mode 100644 arch/arm/boot/dts/nspire.dtsi

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c43..b27b057 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -31,6 +31,7 @@ idt	Integrated Device Technologies, Inc.
 img	Imagination Technologies Ltd.
 intercontrol	Inter Control Group
 linux	Linux-specific binding
+lsi	LSI Corp. (LSI Logic)
 marvell	Marvell Technology Group Ltd.
 maxim	Maxim Integrated Products
 mosaixtech	Mosaix Technologies, Inc.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..5677d6c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx28-sps1.dtb \
 	imx28-tx28.dtb
 dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
+	nspire-tp.dtb \
+	nspire-clp.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	omap3430-sdp.dtb \
 	omap3-beagle.dtb \
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 0000000..9565199
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/boot/nspire-classic.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "nspire.dtsi"
+
+&lcd {
+	lcd-type = "classic";
+};
+
+&fast_timer {
+	/* compatible = "lsi,zevio-timer"; */
+	reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+};
+
+&uart {
+	compatible = "ns16550";
+	reg-shift = <2>;
+	reg-io-width = <4>;
+	clocks = <&apb_pclk>;
+	no-loopback-test;
+};
+
+&timer0 {
+	/* compatible = "lsi,zevio-timer"; */
+	reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+};
+
+&timer1 {
+	compatible = "lsi,zevio-timer";
+	reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+};
+
+&keypad {
+	active-low;
+
+};
+
+&base_clk {
+	compatible = "lsi,nspire-classic-clock";
+};
+
+&ahb_clk {
+	compatible = "lsi,nspire-classic-ahb-divider";
+};
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x10000000 0x2000000>; /* 32 MB */
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		intc: interrupt-controller at DC000000 {
+			compatible = "lsi,zevio-intc";
+			interrupt-controller;
+			reg = <0xDC000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+	};
+	chosen {
+		bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
+	};
+};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 0000000..3f9c8af
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/boot/nspire-clp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00020039
+	0x0004002c 	0x00050034 	0x00060015
+	0x0007000b 	0x0008002d 	0x01000033
+	0x0101004e 	0x01020011 	0x01030004
+	0x0104002f 	0x01050003 	0x01060016
+	0x01070002 	0x01080014 	0x02000062
+	0x0201000c 	0x0202001f 	0x02030007
+	0x02040013 	0x02050006 	0x02060010
+	0x02070005 	0x02080019 	0x03000027
+	0x03010037 	0x03020018 	0x0303000a
+	0x03040031 	0x03050009 	0x03060032
+	0x03070008 	0x03080026 	0x04000028
+	0x04010035 	0x04020025 	0x04040024
+	0x04060017 	0x04080023 	0x05000028
+	0x05020022 	0x0503001b 	0x05040021
+	0x0505001a 	0x05060012 	0x0507006f
+	0x05080020 	0x0509002a 	0x0601001c
+	0x0602002e 	0x06030068 	0x06040030
+	0x0605006d 	0x0606001e 	0x06070001
+	0x0608002b 	0x0609000f 	0x07000067
+	0x0702006a 	0x0704006c 	0x07060069
+	0x0707000e 	0x0708001d 	0x070a000d
+	>;
+};
+
+/ {
+	model = "TI-NSPIRE Clickpad";
+	compatible = "ti,nspire-clp";
+};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 0000000..64632ca
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/boot/nspire-cx.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire.dtsi"
+
+&lcd {
+	lcd-type = "cx";
+};
+
+&fast_timer {
+	/* compatible = "arm,sp804", "arm,primecell"; */
+};
+
+&uart {
+	compatible = "arm,pl011", "arm,primecell";
+
+	clocks = <&uart_clk>, <&apb_pclk>;
+	clock-names = "uart_clk", "apb_pclk";
+};
+
+&timer0 {
+	compatible = "arm,sp804", "arm,primecell";
+};
+
+&timer1 {
+	compatible = "arm,sp804", "arm,primecell";
+};
+
+&base_clk {
+	compatible = "lsi,nspire-cx-clock";
+};
+
+&ahb_clk {
+	compatible = "lsi,nspire-cx-ahb-divider";
+};
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
+
+/ {
+	model = "TI-NSPIRE CX";
+	compatible = "ti,nspire-cx";
+
+	memory {
+		device_type = "memory";
+		reg = <0x10000000 0x4000000>; /* 64 MB */
+	};
+
+	uart_clk: uart_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		intc: interrupt-controller at DC000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xDC000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		apb at 90000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			i2c at 90050000 {
+				compatible = "snps,designware-i2c";
+				reg = <0x90050000 0x1000>;
+				interrupts = <20>;
+			};
+		};
+	};
+	chosen {
+		bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
+	};
+};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 0000000..ab209a3
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
+/*
+ *  linux/arch/arm/boot/nspire-tp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
+
+/ {
+	model = "TI-NSPIRE Touchpad";
+	compatible = "ti,nspire-tp";
+};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 0000000..a22ffe6
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
+/*
+ *  linux/arch/arm/boot/nspire.dtsi
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	bootrom: bootrom at 00000000 {
+		reg = <0x00000000 0x80000>;
+	};
+
+	sram: sram at A4000000 {
+		device = "memory";
+		reg = <0xA4000000 0x20000>;
+	};
+
+	timer_clk: timer_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	base_clk: base_clk {
+		#clock-cells = <0>;
+		reg = <0x900B0024 0x4>;
+	};
+
+	ahb_clk: ahb_clk {
+		#clock-cells = <0>;
+		reg = <0x900B0024 0x4>;
+		clocks = <&base_clk>;
+	};
+
+	apb_pclk: apb_pclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <2>;
+		clock-mult = <1>;
+		clocks = <&ahb_clk>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		spi: spi at A9000000 {
+			reg = <0xA9000000 0x1000>;
+		};
+
+		usb0: usb at B0000000 {
+			reg = <0xB0000000 0x1000>;
+			interrupts = <8>;
+		};
+
+		usb1: usb at B4000000 {
+			reg = <0xB4000000 0x1000>;
+			interrupts = <9>;
+			status = "disabled";
+		};
+
+		lcd: lcd at C0000000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0xC0000000 0x1000>;
+			interrupts = <21>;
+
+			clocks = <&apb_pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		adc: adc at C4000000 {
+			reg = <0xC4000000 0x1000>;
+			interrupts = <11>;
+		};
+
+		tdes: crypto at C8010000 {
+			reg = <0xC8010000 0x1000>;
+		};
+
+		sha256: crypto at CC000000 {
+			reg = <0xCC000000 0x1000>;
+		};
+
+		apb at 90000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clock-ranges;
+			ranges;
+
+			gpio: gpio at 90000000 {
+				reg = <0x90000000 0x1000>;
+				interrupts = <7>;
+			};
+
+			fast_timer: timer at 90010000 {
+				reg = <0x90010000 0x1000>;
+				interrupts = <17>;
+			};
+
+			uart: serial at 90020000 {
+				reg = <0x90020000 0x1000>;
+				interrupts = <1>;
+			};
+
+			timer0: timer at 900C0000 {
+				reg = <0x900C0000 0x1000>;
+
+				clocks = <&timer_clk>;
+			};
+
+			timer1: timer at 900D0000 {
+				reg = <0x900D0000 0x1000>;
+				interrupts = <19>;
+
+				clocks = <&timer_clk>;
+			};
+
+			watchdog: watchdog at 90060000 {
+				compatible = "arm,amba-primecell";
+				reg = <0x90060000 0x1000>;
+				interrupts = <3>;
+			};
+
+			rtc: rtc at 90090000 {
+				reg = <0x90090000 0x1000>;
+				interrupts = <4>;
+			};
+
+			misc: misc at 900A0000 {
+				reg = <0x900A0000 0x1000>;
+			};
+
+			pwr: pwr at 900B0000 {
+				reg = <0x900B0000 0x1000>;
+				interrupts = <15>;
+			};
+
+			keypad: input at 900E0000 {
+				compatible = "ti,nspire-keypad";
+				reg = <0x900E0000 0x1000>;
+				interrupts = <16>;
+
+				scan-interval = <1000>;
+				row-delay = <200>;
+
+				clocks = <&apb_pclk>;
+			};
+
+			contrast: contrast at 900F0000 {
+				reg = <0x900F0000 0x1000>;
+			};
+
+			led: led at 90110000 {
+				reg = <0x90110000 0x1000>;
+			};
+		};
+	};
+};
--
1.8.1.3



From dt.tangr at gmail.com  Sat May 25 07:08:04 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:04 +1000
Subject: [RFC PATCHv4 3/6] clk: TI-Nspire clock drivers
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1369480087-24786-4-git-send-email-dt.tangr@gmail.com>

Add support for TI-Nspire clocks.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 .../devicetree/bindings/clock/nspire-clock.txt     |  24 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-nspire.c                           | 155 +++++++++++++++++++++
 3 files changed, 180 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/nspire-clock.txt
 create mode 100644 drivers/clk/clk-nspire.c

diff --git a/Documentation/devicetree/bindings/clock/nspire-clock.txt b/Documentation/devicetree/bindings/clock/nspire-clock.txt
new file mode 100644
index 0000000..7c3bc8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nspire-clock.txt
@@ -0,0 +1,24 @@
+TI-NSPIRE Clocks
+
+Required properties:
+- compatible: Valid compatible properties include:
+	"lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
+	"lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
+	"lsi,nspire-cx-clock" for the base clock in the CX model
+	"lsi,nspire-classic-clock" for the base clock in the older model
+
+- reg: Physical base address of the controller and length of memory mapped
+	region.
+
+Optional:
+- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
+	clock where it divides the rate from.
+
+Example:
+
+ahb_clk {
+	#clock-cells = <0>;
+	compatible = "lsi,nspire-cx-clock";
+	reg = <0x900B0000 0x4>;
+	clocks = <&base_clk>;
+};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..72ebbe1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
 obj-$(CONFIG_ARCH_NOMADIK)	+= clk-nomadik.o
 obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
+obj-$(CONFIG_ARCH_NSPIRE)	+= clk-nspire.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c
new file mode 100644
index 0000000..2546f7d
--- /dev/null
+++ b/drivers/clk/clk-nspire.c
@@ -0,0 +1,155 @@
+/*
+ *  linux/drivers/clk/clk-nspire.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define MHZ (1000 * 1000)
+
+#define BASE_CPU_SHIFT		1
+#define BASE_CPU_MASK		0x7F
+
+#define CPU_AHB_SHIFT		12
+#define CPU_AHB_MASK		0x07
+
+#define FIXED_BASE_SHIFT	8
+#define FIXED_BASE_MASK		0x01
+
+#define CLASSIC_BASE_SHIFT	16
+#define CLASSIC_BASE_MASK	0x1F
+
+#define CX_BASE_SHIFT		15
+#define CX_BASE_MASK		0x3F
+
+#define CX_UNKNOWN_SHIFT	21
+#define CX_UNKNOWN_MASK		0x03
+
+struct nspire_clk_info {
+	u32 base_clock;
+	u16 base_cpu_ratio;
+	u16 base_ahb_ratio;
+};
+
+
+#define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)
+static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk)
+{
+	if (EXTRACT(val, FIXED_BASE))
+		clk->base_clock = 48 * MHZ;
+	else
+		clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
+
+	clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN);
+	clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
+}
+
+static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk)
+{
+	if (EXTRACT(val, FIXED_BASE))
+		clk->base_clock = 27 * MHZ;
+	else
+		clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
+
+	clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2;
+	clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
+}
+#undef EXTRACT
+
+static void __init nspire_ahbdiv_setup(struct device_node *node,
+		void (*get_clkinfo)(u32, struct nspire_clk_info *))
+{
+	u32 val;
+	void __iomem *io;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct nspire_clk_info info;
+
+	io = of_iomap(node, 0);
+	if (!io)
+		return;
+	val = readl(io);
+	iounmap(io);
+
+	get_clkinfo(val, &info);
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+					1, info.base_ahb_ratio);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static void __init nspire_ahbdiv_setup_cx(struct device_node *node)
+{
+	nspire_ahbdiv_setup(node, nspire_clkinfo_cx);
+}
+
+static void __init nspire_ahbdiv_setup_classic(struct device_node *node)
+{
+	nspire_ahbdiv_setup(node, nspire_clkinfo_classic);
+}
+
+CLK_OF_DECLARE(nspire_ahbdiv_cx, "lsi,nspire-cx-ahb-divider",
+		nspire_ahbdiv_setup_cx);
+CLK_OF_DECLARE(nspire_ahbdiv_classic, "lsi,nspire-classic-ahb-divider",
+		nspire_ahbdiv_setup_classic);
+
+static void __init nspire_clk_setup(struct device_node *node,
+		void (*get_clkinfo)(u32, struct nspire_clk_info *))
+{
+	u32 val;
+	void __iomem *io;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	struct nspire_clk_info info;
+
+	io = of_iomap(node, 0);
+	if (!io)
+		return;
+	val = readl(io);
+	iounmap(io);
+
+	get_clkinfo(val, &info);
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT,
+			info.base_clock);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	else
+		return;
+
+	pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n",
+		info.base_clock / MHZ,
+		info.base_clock / info.base_cpu_ratio / MHZ,
+		info.base_clock / info.base_ahb_ratio / MHZ);
+}
+
+static void __init nspire_clk_setup_cx(struct device_node *node)
+{
+	nspire_clk_setup(node, nspire_clkinfo_cx);
+}
+
+static void __init nspire_clk_setup_classic(struct device_node *node)
+{
+	nspire_clk_setup(node, nspire_clkinfo_classic);
+}
+
+CLK_OF_DECLARE(nspire_clk_cx, "lsi,nspire-cx-clock", nspire_clk_setup_cx);
+CLK_OF_DECLARE(nspire_clk_classic, "lsi,nspire-classic-clock",
+		nspire_clk_setup_classic);
--
1.8.1.3



From dt.tangr at gmail.com  Sat May 25 07:08:05 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:05 +1000
Subject: [RFC PATCHv4 4/6] clocksource: TI-Nspire timer support
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1369480087-24786-5-git-send-email-dt.tangr@gmail.com>

Add clocksource and clockevent driver for the TI-Nspire.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 .../devicetree/bindings/timer/lsi,zevio-timer.txt  |  33 +++
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/zevio-timer.c                  | 231 +++++++++++++++++++++
 3 files changed, 265 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt
 create mode 100644 drivers/clocksource/zevio-timer.c

diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt
new file mode 100644
index 0000000..b2d07ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt
@@ -0,0 +1,33 @@
+TI-NSPIRE timer
+
+Required properties:
+
+- compatible : should be "lsi,zevio-timer".
+- reg : The physical base address and size of the timer (always first).
+- clocks: phandle to the source clock.
+
+Optional properties:
+
+- interrupts : The interrupt number of the first timer.
+- reg : The interrupt acknowledgement registers
+	(always after timer base address)
+
+If any of the optional properties are not given, the timer is added as a
+clock-source only.
+
+Example:
+
+timer {
+	compatible = "lsi,zevio-timer";
+	reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+	interrupts = <19>;
+	clocks = <&timer_clk>;
+};
+
+Example (no clock-events):
+
+timer {
+	compatible = "lsi,zevio-timer";
+	reg = <0x900D0000 0x1000>;
+	clocks = <&timer_clk>;
+};
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c7..293f86e 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
+obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o
 obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
 obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
diff --git a/drivers/clocksource/zevio-timer.c b/drivers/clocksource/zevio-timer.c
new file mode 100644
index 0000000..c6d7f03
--- /dev/null
+++ b/drivers/clocksource/zevio-timer.c
@@ -0,0 +1,231 @@
+/*
+ *  linux/drivers/clocksource/zevio-timer.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+
+#define IO_CURRENT_VAL	0x00
+#define IO_DIVIDER	0x04
+#define IO_CONTROL	0x08
+
+#define IO_TIMER1	0x00
+#define IO_TIMER2	0x0C
+
+#define IO_MATCH_BEGIN	0x18
+#define IO_MATCH(x)	(IO_MATCH_BEGIN + ((x)<<2))
+
+#define IO_INTR_STS	0x00
+#define IO_INTR_ACK	0x00
+#define IO_INTR_MSK	0x04
+
+#define CNTL_STOP_TIMER	(1<<4)
+#define CNTL_RUN_TIMER	(0<<4)
+
+#define CNTL_INC	(1<<3)
+#define CNTL_DEC	(0<<3)
+
+#define CNTL_TOZERO	0
+#define CNTL_MATCH(x)	((x) + 1)
+#define CNTL_FOREVER	7
+
+/* There are 6 match registers but we only use one. */
+#define TIMER_MATCH	0
+
+#define TIMER_INTR_MSK	(1<<(TIMER_MATCH))
+#define TIMER_INTR_ALL	0x3F
+
+struct zevio_timer {
+	void __iomem *base;
+	void __iomem *timer1, *timer2;
+	void __iomem *interrupt_regs;
+
+	int irqnr;
+
+	struct clk *clk;
+	struct clock_event_device clkevt;
+	struct irqaction clkevt_irq;
+
+	char clocksource_name[64];
+	char clockevent_name[64];
+};
+
+static int zevio_timer_set_event(unsigned long delta,
+		struct clock_event_device *dev)
+{
+	unsigned long flags;
+	struct zevio_timer *timer = container_of(dev,
+			struct zevio_timer,
+			clkevt);
+
+	local_irq_save(flags);
+
+	writel(delta, timer->timer1 + IO_CURRENT_VAL);
+	writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH),
+			timer->timer1 + IO_CONTROL);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static void zevio_timer_set_mode(enum clock_event_mode mode,
+		struct clock_event_device *dev)
+{
+	unsigned long flags;
+	struct zevio_timer *timer = container_of(dev,
+			struct zevio_timer,
+			clkevt);
+
+	local_irq_save(flags);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		/* Unsupported */
+		break;
+	case CLOCK_EVT_MODE_RESUME:
+	case CLOCK_EVT_MODE_ONESHOT:
+		/* Enable timer interrupts */
+		writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
+		writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
+		dev->mode = mode;
+		break;
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_UNUSED:
+		/* Disable timer interrupts */
+		writel(0, timer->interrupt_regs + IO_INTR_MSK);
+		writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
+		/* Stop timer */
+		writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+		dev->mode = mode;
+		break;
+	}
+
+	local_irq_restore(flags);
+}
+
+static irqreturn_t zevio_timer_interrupt(int irq, void *dev_id)
+{
+	struct zevio_timer *timer = dev_id;
+	u32 intr;
+
+	intr = readl(timer->interrupt_regs + IO_INTR_ACK);
+	if (!(intr & TIMER_INTR_MSK))
+		return IRQ_NONE;
+
+	writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK);
+	writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+
+	if (timer->clkevt.event_handler)
+		timer->clkevt.event_handler(&timer->clkevt);
+
+	return IRQ_HANDLED;
+}
+
+static int __init zevio_timer_add(struct device_node *node)
+{
+	struct zevio_timer *timer;
+	struct resource res;
+	int ret;
+
+	timer = kzalloc(sizeof(*timer), GFP_ATOMIC);
+	if (!timer)
+		return -ENOMEM;
+
+	timer->base = of_iomap(node, 0);
+	if (!timer->base) {
+		ret = -EINVAL;
+		goto error_free;
+	}
+	timer->timer1 = timer->base + IO_TIMER1;
+	timer->timer2 = timer->base + IO_TIMER2;
+
+	timer->clk = of_clk_get(node, 0);
+	if (IS_ERR(timer->clk)) {
+		ret = PTR_ERR(timer->clk);
+		pr_err("Timer clock not found! (error %d)\n", ret);
+		goto error_unmap;
+	}
+
+	timer->interrupt_regs = of_iomap(node, 1);
+	timer->irqnr = irq_of_parse_and_map(node, 0);
+
+	of_address_to_resource(node, 0, &res);
+	scnprintf(timer->clocksource_name, sizeof(timer->clocksource_name),
+			"%llx.%s_clocksource",
+			(unsigned long long)res.start, node->name);
+
+	scnprintf(timer->clockevent_name, sizeof(timer->clockevent_name),
+			"%llx.%s_clockevent",
+			(unsigned long long)res.start, node->name);
+
+	if (timer->interrupt_regs && timer->irqnr) {
+		timer->clkevt.name	= timer->clockevent_name;
+		timer->clkevt.set_next_event = zevio_timer_set_event;
+		timer->clkevt.set_mode	= zevio_timer_set_mode;
+		timer->clkevt.rating	= 200;
+		timer->clkevt.cpumask	= cpu_all_mask;
+		timer->clkevt.features	=
+			CLOCK_EVT_FEAT_ONESHOT;
+
+		writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+		writel(0, timer->timer1 + IO_DIVIDER);
+
+		/* Start with timer interrupts disabled */
+		writel(0, timer->interrupt_regs + IO_INTR_MSK);
+		writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
+
+		/* Interrupt to occur when timer value matches 0 */
+		writel(0, timer->base + IO_MATCH(TIMER_MATCH));
+
+		timer->clkevt_irq.name	= timer->clockevent_name;
+		timer->clkevt_irq.handler = zevio_timer_interrupt;
+		timer->clkevt_irq.dev_id = timer;
+		timer->clkevt_irq.flags	=
+			IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
+
+		setup_irq(timer->irqnr, &timer->clkevt_irq);
+
+		clockevents_config_and_register(&timer->clkevt,
+				clk_get_rate(timer->clk), 0x0001, 0xffff);
+		pr_info("Added %s as clockevent\n", timer->clockevent_name);
+	}
+
+	writel(CNTL_STOP_TIMER, timer->timer2 + IO_CONTROL);
+	writel(0, timer->timer2 + IO_CURRENT_VAL);
+	writel(0, timer->timer2 + IO_DIVIDER);
+	writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
+			timer->timer2 + IO_CONTROL);
+
+	clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
+			timer->clocksource_name,
+			clk_get_rate(timer->clk),
+			200, 16,
+			clocksource_mmio_readw_up);
+
+	pr_info("Added %s as clocksource\n", timer->clocksource_name);
+
+	return 0;
+error_unmap:
+	iounmap(timer->base);
+error_free:
+	kfree(timer);
+	return ret;
+}
+
+CLOCKSOURCE_OF_DECLARE(zevio_timer, "lsi,zevio-timer", zevio_timer_add);
--
1.8.1.3



From dt.tangr at gmail.com  Sat May 25 07:08:06 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:06 +1000
Subject: [RFC PATCHv4 5/6] input: TI-Nspire keypad support
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1369480087-24786-6-git-send-email-dt.tangr@gmail.com>

Add support for the built-in keypad on TI-Nspires.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 .../devicetree/bindings/input/ti,nspire-keypad.txt |  60 ++++
 drivers/input/keyboard/Kconfig                     |  10 +
 drivers/input/keyboard/Makefile                    |   1 +
 drivers/input/keyboard/nspire-keypad.c             | 315 +++++++++++++++++++++
 4 files changed, 386 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/ti,nspire-keypad.txt
 create mode 100644 drivers/input/keyboard/nspire-keypad.c

diff --git a/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt b/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt
new file mode 100644
index 0000000..f5b91c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt
@@ -0,0 +1,60 @@
+TI-NSPIRE Keypad
+
+Required properties:
+- compatible: Compatible property value should be "ti,nspire-keypad".
+
+- reg: Physical base address of the peripheral and length of memory mapped
+  region.
+
+- interrupts: The interrupt number for the peripheral.
+
+- scan-interval: How often to scan in us. Based on a APB speed of 33MHz, the
+	maximum delay time is ...us
+
+- row-delay: How long to wait before scanning each row.
+
+- clocks: The clock this peripheral is attached to.
+
+- keymap: The keymap to use
+	(see Documentation/devicetree/bindings/input/matrix-keymap.txt)
+
+Optional properties:
+- active-low: Specify that the keypad is active low (i.e. logical low signifies
+	a key press).
+
+Example:
+
+input {
+	compatible = "ti,nspire-keypad";
+	reg = <0x900E0000 0x1000>;
+	interrupts = <16>;
+
+	scan-interval = <1000>;
+	row-delay = <200>;
+
+	clocks = <&apb_pclk>;
+
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 62a2c0e..bdbda87 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -418,6 +418,16 @@ config KEYBOARD_NOMADIK
 	  To compile this driver as a module, choose M here: the
 	  module will be called nmk-ske-keypad.

+config KEYBOARD_NSPIRE
+	tristate "TI-NSPIRE builtin keyboard"
+	depends on ARCH_NSPIRE
+	select INPUT_MATRIXKMAP
+	help
+	  Say Y here if you want to use the builtin keypad on the TI-NSPIRE.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called nspire-keypad.
+
 config KEYBOARD_TEGRA
 	tristate "NVIDIA Tegra internal matrix keyboard controller support"
 	depends on ARCH_TEGRA && OF
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 0c43e8c..a699b61 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_KEYBOARD_MCS)		+= mcs_touchkey.o
 obj-$(CONFIG_KEYBOARD_MPR121)		+= mpr121_touchkey.o
 obj-$(CONFIG_KEYBOARD_NEWTON)		+= newtonkbd.o
 obj-$(CONFIG_KEYBOARD_NOMADIK)		+= nomadik-ske-keypad.o
+obj-$(CONFIG_KEYBOARD_NSPIRE)		+= nspire-keypad.o
 obj-$(CONFIG_KEYBOARD_OMAP)		+= omap-keypad.o
 obj-$(CONFIG_KEYBOARD_OMAP4)		+= omap4-keypad.o
 obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
diff --git a/drivers/input/keyboard/nspire-keypad.c b/drivers/input/keyboard/nspire-keypad.c
new file mode 100644
index 0000000..b922390
--- /dev/null
+++ b/drivers/input/keyboard/nspire-keypad.c
@@ -0,0 +1,315 @@
+/*
+ *  linux/drivers/input/keyboard/nspire-keypad.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/input/matrix_keypad.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#define KEYPAD_SCAN_MODE	0x00
+#define KEYPAD_CNTL		0x04
+#define KEYPAD_INT		0x08
+#define KEYPAD_INTMSK		0x0C
+
+#define KEYPAD_DATA		0x10
+#define KEYPAD_GPIO		0x30
+
+#define KEYPAD_UNKNOWN_INT	0x40
+#define KEYPAD_UNKNOWN_INT_STS	0x44
+
+#define KEYPAD_BITMASK_COLS	11
+#define KEYPAD_BITMASK_ROWS	8
+
+struct nspire_keypad {
+	spinlock_t lock;
+
+	void __iomem *reg_base;
+	int irq;
+	u32 int_mask;
+
+	struct input_dev *input;
+	struct clk *clk;
+
+	struct matrix_keymap_data *keymap;
+	int row_shift;
+
+	/* Maximum delay estimated assuming 33MHz APB */
+	u32 scan_interval;	/* In microseconds (~2000us max) */
+	u32 row_delay;		/* In microseconds (~500us max) */
+
+	bool active_low;
+};
+
+static inline void nspire_report_state(struct nspire_keypad *keypad,
+		int row, int col, unsigned int state)
+{
+	int code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+	unsigned short *keymap = keypad->input->keycode;
+
+	state = keypad->active_low ? !state : !!state;
+	input_report_key(keypad->input, keymap[code], state);
+}
+
+static irqreturn_t nspire_keypad_irq(int irq, void *dev_id)
+{
+	struct nspire_keypad *keypad = dev_id;
+	u32 int_sts;
+	u16 state[8];
+	int row, col;
+
+	int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask;
+
+	if (!int_sts)
+		return IRQ_NONE;
+
+	spin_lock(&keypad->lock);
+
+	memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state));
+
+	for (row = 0; row < KEYPAD_BITMASK_ROWS; row++) {
+		u16 bits = state[row];
+		for (col = 0; col < KEYPAD_BITMASK_COLS; col++)
+			nspire_report_state(keypad, row, col, bits & (1<<col));
+	}
+	input_sync(keypad->input);
+	writel(0x3, keypad->reg_base + KEYPAD_INT);
+
+	spin_unlock(&keypad->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int nspire_keypad_chip_init(struct nspire_keypad *keypad)
+{
+	unsigned long val = 0, cycles_per_us, delay_cycles, row_delay_cycles;
+
+	cycles_per_us = (clk_get_rate(keypad->clk) / 1000000);
+	if (cycles_per_us == 0)
+		cycles_per_us = 1;
+
+	delay_cycles = cycles_per_us * keypad->scan_interval;
+	WARN_ON(delay_cycles >= (1<<16)); /* Overflow */
+	delay_cycles &= 0xffff;
+
+	row_delay_cycles = cycles_per_us * keypad->row_delay;
+	WARN_ON(row_delay_cycles >= (1<<14)); /* Overflow */
+	row_delay_cycles &= 0x3fff;
+
+
+	val |= (3<<0); /* Set scan mode to 3 (continuous scan) */
+	val |= (row_delay_cycles<<2); /* Delay between scanning each row */
+	val |= (delay_cycles<<16); /* Delay between scans */
+	writel(val, keypad->reg_base + KEYPAD_SCAN_MODE);
+
+	val = (KEYPAD_BITMASK_ROWS & 0xff) | (KEYPAD_BITMASK_COLS & 0xff)<<8;
+	writel(val, keypad->reg_base + KEYPAD_CNTL);
+
+	/* Enable interrupts */
+	keypad->int_mask = (1<<1);
+	writel(keypad->int_mask, keypad->reg_base + 0xc);
+
+	/* Disable GPIO interrupts to prevent hanging on touchpad */
+	/* Possibly used to detect touchpad events */
+	writel(0, keypad->reg_base + KEYPAD_UNKNOWN_INT);
+	/* Acknowledge existing interrupts */
+	writel(~0, keypad->reg_base + KEYPAD_UNKNOWN_INT_STS);
+
+	return 0;
+}
+
+static int nspire_keypad_probe(struct platform_device *pdev)
+{
+	const struct device_node *of_node = pdev->dev.of_node;
+	struct nspire_keypad *keypad;
+	struct input_dev *input;
+	struct resource *res;
+	struct clk *clk;
+	int irq, error;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "failed to get keypad irq\n");
+		return -EINVAL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "missing platform resources\n");
+		return -EINVAL;
+	}
+
+	clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "unable to get clock\n");
+		return -EINVAL;
+	}
+
+	clk_prepare(clk);
+	error = clk_enable(clk);
+	if (error)
+		goto err_put_clk;
+
+	keypad = kzalloc(sizeof(struct nspire_keypad), GFP_KERNEL);
+	input = input_allocate_device();
+	if (!keypad || !input) {
+		dev_err(&pdev->dev, "failed to allocate keypad memory\n");
+		error = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	error = of_property_read_u32(of_node, "scan-interval",
+			&keypad->scan_interval);
+	if (error) {
+		dev_err(&pdev->dev, "failed to get scan-interval\n");
+		goto err_free_mem;
+	}
+
+	error = of_property_read_u32(of_node, "row-delay",
+			&keypad->row_delay);
+	if (error) {
+		dev_err(&pdev->dev, "failed to get row-delay\n");
+		goto err_free_mem;
+	}
+
+	keypad->active_low = of_property_read_bool(of_node,
+			"active-low");
+
+	keypad->keymap = NULL;
+
+	keypad->row_shift = get_count_order(KEYPAD_BITMASK_COLS);
+	keypad->irq = irq;
+	keypad->clk = clk;
+	keypad->input = input;
+	spin_lock_init(&keypad->lock);
+
+	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+		dev_err(&pdev->dev, "failed to request I/O memory\n");
+		error = -EBUSY;
+		goto err_free_mem;
+	}
+
+	keypad->reg_base = ioremap(res->start, resource_size(res));
+	if (!keypad->reg_base) {
+		dev_err(&pdev->dev, "failed to remap I/O memory\n");
+		error = -ENXIO;
+		goto err_free_mem_region;
+	}
+
+	input->id.bustype = BUS_HOST;
+	input->name = "nspire-keypad";
+	input->dev.parent = &pdev->dev;
+
+	set_bit(EV_KEY, input->evbit);
+	set_bit(EV_REP, input->evbit);
+
+	error = matrix_keypad_build_keymap(keypad->keymap, "keymap",
+			KEYPAD_BITMASK_ROWS, KEYPAD_BITMASK_COLS, NULL, input);
+	if (error) {
+		dev_err(&pdev->dev, "building keymap failed\n");
+		goto err_iounmap;
+	}
+
+	error = nspire_keypad_chip_init(keypad);
+	if (error) {
+		dev_err(&pdev->dev, "unable to init keypad hardware\n");
+		goto err_iounmap;
+	}
+
+	error = request_irq(keypad->irq, nspire_keypad_irq, 0,
+			"nspire_keypad", keypad);
+	if (error) {
+		dev_err(&pdev->dev, "allocate irq %d failed\n", keypad->irq);
+		goto err_iounmap;
+	}
+
+	error = input_register_device(input);
+	if (error) {
+		dev_err(&pdev->dev,
+				"unable to register input device: %d\n", error);
+		goto err_free_irq;
+	}
+
+	platform_set_drvdata(pdev, keypad);
+
+	dev_info(&pdev->dev, "TI-NSPIRE keypad at %#08x ("
+			"scan_interval=%uus,row_delay=%uus"
+			"%s)\n", res->start,
+			keypad->row_delay,
+			keypad->scan_interval,
+			keypad->active_low ? ",active_low" : "");
+
+	return 0;
+
+err_free_irq:
+	free_irq(keypad->irq, keypad);
+err_iounmap:
+	iounmap(keypad->reg_base);
+err_free_mem_region:
+	release_mem_region(res->start, resource_size(res));
+err_free_mem:
+	input_free_device(input);
+	kfree(keypad);
+
+	clk_disable(clk);
+err_put_clk:
+	clk_unprepare(clk);
+	clk_put(clk);
+	return error;
+}
+
+static int nspire_keypad_remove(struct platform_device *pdev)
+{
+	struct nspire_keypad *keypad = platform_get_drvdata(pdev);
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	free_irq(keypad->irq, keypad);
+
+	input_unregister_device(keypad->input);
+
+	iounmap(keypad->reg_base);
+	release_mem_region(res->start, resource_size(res));
+	kfree(keypad);
+
+	clk_disable(keypad->clk);
+	clk_unprepare(keypad->clk);
+	clk_put(keypad->clk);
+
+	return 0;
+}
+#ifdef CONFIG_OF
+static const struct of_device_id nspire_keypad_dt_match[] = {
+	{ .compatible = "ti,nspire-keypad" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, nspire_keypad_dt_match);
+#endif
+
+static struct platform_driver nspire_keypad_driver = {
+	.driver = {
+		.name = "nspire-keypad",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_match_ptr(nspire_keypad_dt_match),
+	},
+	.remove = nspire_keypad_remove,
+	.probe = nspire_keypad_probe,
+};
+
+module_platform_driver(nspire_keypad_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("TI-NSPIRE Keypad Driver");
--
1.8.1.3



From dt.tangr at gmail.com  Sat May 25 07:08:07 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Sat, 25 May 2013 21:08:07 +1000
Subject: [RFC PATCHv4 6/6] irqchip: TI-Nspire irqchip support
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <1369480087-24786-7-git-send-email-dt.tangr@gmail.com>

Add support for the interrupt controller on TI-Nspires.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 .../interrupt-controller/lsi,zevio-intc.txt        |  18 +++
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-zevio.c                        | 177 +++++++++++++++++++++
 3 files changed, 196 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt
 create mode 100644 drivers/irqchip/irq-zevio.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt
new file mode 100644
index 0000000..aee38e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt
@@ -0,0 +1,18 @@
+TI-NSPIRE interrupt controller
+
+Required properties:
+- compatible: Compatible property value should be "lsi,zevio-intc".
+
+- reg: Physical base address of the controller and length of memory mapped
+	region.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+Example:
+
+interrupt-controller {
+	compatible = "lsi,zevio-intc";
+	interrupt-controller;
+	reg = <0xDC000000 0x1000>;
+	#interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5..f313d14 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
 obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o
 obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
diff --git a/drivers/irqchip/irq-zevio.c b/drivers/irqchip/irq-zevio.c
new file mode 100644
index 0000000..3101c2a
--- /dev/null
+++ b/drivers/irqchip/irq-zevio.c
@@ -0,0 +1,177 @@
+/*
+ *  linux/drivers/irqchip/irq-nspire-classic.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+
+#include "irqchip.h"
+
+#define IO_STATUS	0x000
+#define IO_RAW_STATUS	0x004
+#define IO_ENABLE	0x008
+#define IO_DISABLE	0x00C
+#define IO_CURRENT	0x020
+#define IO_RESET	0x028
+#define IO_MAX_PRIOTY	0x02C
+
+#define IO_IRQ_BASE	0x000
+#define IO_FIQ_BASE	0x100
+
+#define IO_INVERT_SEL	0x200
+#define IO_STICKY_SEL	0x204
+#define IO_PRIORITY_SEL	0x300
+
+#define MAX_INTRS	32
+#define FIQ_START	MAX_INTRS
+
+
+static void __iomem *irq_io_base;
+static struct irq_domain *nspire_irq_domain;
+
+static void nspire_irq_ack(struct irq_data *irqd)
+{
+	void __iomem *base = irq_io_base;
+
+	if (irqd->hwirq < FIQ_START)
+		base += IO_IRQ_BASE;
+	else
+		base += IO_FIQ_BASE;
+
+	readl(base + IO_RESET);
+}
+
+static void nspire_irq_unmask(struct irq_data *irqd)
+{
+	void __iomem *base = irq_io_base;
+	int irqnr = irqd->hwirq;
+
+	if (irqnr < FIQ_START) {
+		base += IO_IRQ_BASE;
+	} else {
+		irqnr -= MAX_INTRS;
+		base += IO_FIQ_BASE;
+	}
+
+	writel((1<<irqnr), base + IO_ENABLE);
+}
+
+static void nspire_irq_mask(struct irq_data *irqd)
+{
+	void __iomem *base = irq_io_base;
+	int irqnr = irqd->hwirq;
+
+	if (irqnr < FIQ_START) {
+		base += IO_IRQ_BASE;
+	} else {
+		irqnr -= FIQ_START;
+		base += IO_FIQ_BASE;
+	}
+
+	writel((1<<irqnr), base + IO_DISABLE);
+}
+
+static struct irq_chip nspire_irq_chip = {
+	.name		= "nspire_irq",
+	.irq_ack	= nspire_irq_ack,
+	.irq_mask	= nspire_irq_mask,
+	.irq_unmask	= nspire_irq_unmask,
+};
+
+
+static int nspire_irq_map(struct irq_domain *dom, unsigned int virq,
+		irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &nspire_irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops nspire_irq_ops = {
+	.map = nspire_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static void init_base(void __iomem *base)
+{
+	/* Disable all interrupts */
+	writel(~0, base + IO_DISABLE);
+
+	/* Accept interrupts of all priorities */
+	writel(0xF, base + IO_MAX_PRIOTY);
+
+	/* Reset existing interrupts */
+	readl(base + IO_RESET);
+}
+
+static int process_base(void __iomem *base, struct pt_regs *regs)
+{
+	int irqnr;
+
+
+	if (!readl(base + IO_STATUS))
+		return 0;
+
+	irqnr = readl(base + IO_CURRENT);
+	irqnr = irq_find_mapping(nspire_irq_domain, irqnr);
+	handle_IRQ(irqnr, regs);
+
+	return 1;
+}
+
+asmlinkage void __exception_irq_entry nspire_handle_irq(struct pt_regs *regs)
+{
+	while (process_base(irq_io_base + IO_FIQ_BASE, regs))
+		;
+	while (process_base(irq_io_base + IO_IRQ_BASE, regs))
+		;
+}
+
+static int __init nspire_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	if (WARN_ON(irq_io_base))
+		return -EBUSY;
+
+	irq_io_base = of_iomap(node, 0);
+	BUG_ON(!irq_io_base);
+
+	/* Do not invert interrupt status bits */
+	writel(~0, irq_io_base + IO_INVERT_SEL);
+
+	/* Disable sticky interrupts */
+	writel(0, irq_io_base + IO_STICKY_SEL);
+
+	/* We don't use IRQ priorities. Set each IRQ to highest priority. */
+	memset_io(irq_io_base + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));
+
+	/* Init IRQ and FIQ */
+	init_base(irq_io_base + IO_IRQ_BASE);
+	init_base(irq_io_base + IO_FIQ_BASE);
+
+	nspire_irq_domain = irq_domain_add_linear(node, MAX_INTRS,
+						 &nspire_irq_ops, NULL);
+
+	BUG_ON(!nspire_irq_domain);
+
+	set_handle_irq(nspire_handle_irq);
+
+	pr_info("TI-NSPIRE classic IRQ controller\n");
+	return 0;
+}
+
+IRQCHIP_DECLARE(nspire_classic_irq, "lsi,zevio-intc", nspire_of_init);
--
1.8.1.3



From shawn.guo at linaro.org  Sat May 25 07:17:49 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 May 2013 19:17:49 +0800
Subject: clock framework: Don't disable a clock already enabled by boot
 loader?
In-Reply-To: <51A0655C.4020309@gmail.com>
References: <519F60CA.6090302@de.bosch.com>
 <20130524230021.GF31135@pengutronix.de>
 <51A05351.7000501@gmail.com>
 <20130525065434.GA7782@S2101-09.ap.freescale.net>
 <51A0655C.4020309@gmail.com>
Message-ID: <20130525111747.GC7782@S2101-09.ap.freescale.net>

On Sat, May 25, 2013 at 09:16:44AM +0200, Dirk Behme wrote:
> Yes, I know ;) But this is slightly different: In the end it
> disables the complete clk_disable_unused() call, i.e. for all unused
> clocks.
> 
> I'd like to set the flag CLK_IGNORE_UNUSED for just one clock. I.e.
> I want to set a flag for an i.MX6 clock, and I want to set it only
> for one clock.
> 
> What's the preferred way to do this?

I do not like the idea to set CLK_IGNORE_UNUSED in clock driver on clk
basis.  If the clk is needed by some driver, why cannot the driver
enable it using clk API?  Or if the clk is some fundamental one that
does not clearly belong to particular IP block and no driver wants to
manage it, we may want to not implement it in clock driver at all and
just leave it to bootloader to set it up for once.

Shawn



From tomasz.figa at gmail.com  Sat May 25 08:06:51 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sat, 25 May 2013 14:06:51 +0200
Subject: [PATCH 1/5] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <1367572669-24354-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
 <1367572669-24354-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <2868419.vHvm2rOVdd@flatron>

Hi Maxime,

Overall the driver looks good, just some minor nitpicks inline.

On Friday 03 of May 2013 11:17:45 Maxime Ripard wrote:
> This patch implements a basic driver for the I2C host driver found on
> the Allwinner A10, A13 and A31 SoCs.
> 
> Notable missing feature is 10-bit addressing.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
>  drivers/i2c/busses/Kconfig                         |  10 +
>  drivers/i2c/busses/Makefile                        |   1 +
>  drivers/i2c/busses/i2c-sunxi.c                     | 441
> +++++++++++++++++++++ 4 files changed, 471 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
>  create mode 100644 drivers/i2c/busses/i2c-sunxi.c
> 
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
> b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt new file mode
> 100644
> index 0000000..40c16d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
> @@ -0,0 +1,19 @@
> +Allwinner SoC I2C controller
> +
> +Required properties:
> +- compatible : Should be "allwinner,sun4i-i2c".
> +- reg: Should contain register location and length.
> +- interrupts: Should contain interrupt.
> +- clocks : The parent clock feeding the I2C controller.
> +
> +Recommended properties:
> +- clock-frequency : desired I2C bus clock frequency in Hz.
> +
> +Example:
> +i2c0: i2c at 01c2ac00 {
> +	compatible = "allwinner,sun4i-i2c";
> +	reg = <0x01c2ac00 0x400>;
> +	interrupts = <7>;
> +	clocks = <&apb1_gates 0>;
> +	clock-frequency = <100000>;
> +};
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index adfee98..327a49b 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -706,6 +706,16 @@ config I2C_STU300
>  	  This driver can also be built as a module. If so, the module
>  	  will be called i2c-stu300.
> 
> +config I2C_SUNXI
> +	tristate "Allwinner A1X I2C controller"
> +	depends on ARCH_SUNXI
> +	help
> +	  If you say yes to this option, support will be included for the
> +	  I2C controller embedded in Allwinner A1X SoCs.
> +
> +	  This driver can also be built as a module. If so, the module
> +	  will be called i2c-sunxi.
> +
>  config I2C_TEGRA
>  	tristate "NVIDIA Tegra internal I2C controller"
>  	depends on ARCH_TEGRA
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 8f4fc23..7225818 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
>  obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
>  obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
>  obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
> +obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
>  obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
>  obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
>  obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
> diff --git a/drivers/i2c/busses/i2c-sunxi.c
> b/drivers/i2c/busses/i2c-sunxi.c new file mode 100644
> index 0000000..f9f8bd4
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-sunxi.c
> @@ -0,0 +1,441 @@
> +/*
> + * Allwinner A1X SoCs i2c controller driver.
> + *
> + * Copyright (C) 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard at free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +
> +#define SUNXI_I2C_ADDR_REG		(0x00)
> +#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
> +#define SUNXI_I2C_XADDR_REG		(0x04)
> +#define SUNXI_I2C_DATA_REG		(0x08)
> +#define SUNXI_I2C_CNTR_REG		(0x0c)
> +#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
> +#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
> +#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
> +#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
> +#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
> +#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
> +#define SUNXI_I2C_STA_REG		(0x10)
> +#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
> +#define SUNXI_I2C_STA_START			(0x08)
> +#define SUNXI_I2C_STA_START_REPEAT		(0x10)
> +#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
> +#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
> +#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
> +#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
> +#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
> +#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
> +#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
> +#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
> +#define SUNXI_I2C_CCR_REG		(0x14)
> +#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
> +#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
> +#define SUNXI_I2C_SRST_REG		(0x18)
> +#define SUNXI_I2C_SRST_RESET			BIT(0)
> +#define SUNXI_I2C_EFR_REG		(0x1c)
> +#define SUNXI_I2C_LCR_REG		(0x20)
> +
> +#define SUNXI_I2C_DONE			BIT(0)
> +#define SUNXI_I2C_ERROR			BIT(1)
> +#define SUNXI_I2C_NAK			BIT(2)
> +#define SUNXI_I2C_BUS_ERROR		BIT(3)
> +
> +struct sunxi_i2c_dev {
> +	struct i2c_adapter	adapter;
> +	struct clk		*clk;
> +	struct device		*dev;
> +	struct completion	completion;
> +	unsigned int		irq;
> +	void __iomem		*membase;
> +
> +	struct i2c_msg		*msg_cur;
> +	u8			*msg_buf;
> +	size_t			msg_buf_remaining;
> +	unsigned int		msg_err;
> +};
> +
> +static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8
> value) +{
> +	writel(value, i2c_dev->membase + reg);
> +}
> +
> +static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
> +{
> +	return readl(i2c_dev->membase + reg);
> +}
> +
> +/*
> + * This is where all the magic happens. The I2C controller works as a
> + * state machine, each state being a step in the i2c protocol, with
> + * the controller sending an interrupt at each state transition.
> + *
> + * The state we're in is stored in a register, which leads to a pretty
> + * huge switch statement, all of this in the interrupt handler...
> + */
> +static irqreturn_t sunxi_i2c_handler(int irq, void *data)
> +{
> +	struct sunxi_i2c_dev *i2c_dev = (struct sunxi_i2c_dev *)data;
> +	u32 status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	u32 addr, val;
> +
> +	if (!(status & SUNXI_I2C_CNTR_INT_FLAG))
> +		return IRQ_NONE;
> +
> +	/* Read the current state we're in */
> +	status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_STA_REG);
> +
> +	switch (status & 0xff) {
> +	/* Start condition has been transmitted */
> +	case SUNXI_I2C_STA_START:
> +	/* A repeated start condition has been transmitted */
> +	case SUNXI_I2C_STA_START_REPEAT:
> +		addr = SUNXI_I2C_ADDR_ADDR(i2c_dev->msg_cur->addr);
> +
> +		if (i2c_dev->msg_cur->flags & I2C_M_RD)
> +			addr |= 1;
> +
> +		sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG, addr);
> +		break;
> +
> +	/*
> +	 * Address + Write bit have been transmitted, ACK has not been
> +	 * received.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_WADDR_NAK:
> +	/*
> +	 * Data byte has been transmitted, ACK has not been
> +	 * received
> +	 */
> +	case SUNXI_I2C_STA_MASTER_DATA_SENT_NAK:
> +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> +			goto out;
> +		}

A comment here that the fall-through is intentional would be nice.

> +
> +	/*
> +	 * Address + Write bit have been transmitted, ACK has been
> +	 * received
> +	 */
> +	case SUNXI_I2C_STA_MASTER_WADDR_ACK:
> +	/* Data byte has been transmitted, ACK has been received */
> +	case SUNXI_I2C_STA_MASTER_DATA_SENT_ACK:
> +		if (i2c_dev->msg_buf_remaining) {
> +			sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG,
> +					*i2c_dev->msg_buf);
> +			i2c_dev->msg_buf++;
> +			i2c_dev->msg_buf_remaining--;
> +			break;
> +		}
> +
> +		if (i2c_dev->msg_buf_remaining == 0) {
> +			i2c_dev->msg_err = SUNXI_I2C_DONE;
> +			goto out;
> +		}
> +
> +		break;
> +
> +	/*
> +	 * Address + Read bit have been transmitted, ACK has not been
> +	 * received
> +	 */
> +	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
> +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> +			goto out;
> +		}

Here as well.

> +
> +	/*
> +	 * Address + Read bit have been transmitted, ACK has been
> +	 * received
> +	 */
> +	case SUNXI_I2C_STA_MASTER_RADDR_ACK:
> +		/*
> +		 * We only need to send the ACK for the all the bytes
> +		 * but the last one
> +		 */
> +		if (i2c_dev->msg_buf_remaining > 1) {
> +			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +					val | SUNXI_I2C_CNTR_ASSERT_ACK);
> +		}
> +
> +		break;
> +
> +	/*
> +	 * Data byte has been received, ACK has not been
> +	 * transmitted
> +	 */
> +	case SUNXI_I2C_STA_MASTER_DATA_RECV_NAK:
> +		if (i2c_dev->msg_buf_remaining == 1) {
> +			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG);
> +			*i2c_dev->msg_buf = val & 0xff;
> +			i2c_dev->msg_buf_remaining--;
> +			i2c_dev->msg_err = SUNXI_I2C_DONE;
> +			goto out;
> +		}
> +
> +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> +			goto out;
> +		}

Ditto.

> +
> +	/* Data byte has been received, ACK has been transmitted */
> +	case SUNXI_I2C_STA_MASTER_DATA_RECV_ACK:
> +		val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG) & 0xff;
> +		*i2c_dev->msg_buf = val;
> +		i2c_dev->msg_buf++;
> +		i2c_dev->msg_buf_remaining--;
> +
> +		/* If there's only one byte left, disable the ACK */
> +		if (i2c_dev->msg_buf_remaining == 1) {
> +			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +					val & ~SUNXI_I2C_CNTR_ASSERT_ACK);
> +
> +		};
> +
> +		break;
> +
> +	case SUNXI_I2C_STA_BUS_ERROR:
> +		i2c_dev->msg_err = SUNXI_I2C_BUS_ERROR;
> +		goto out;
> +
> +	default:
> +		i2c_dev->msg_err = SUNXI_I2C_ERROR;
> +		goto out;
> +	}
> +
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			val & ~SUNXI_I2C_CNTR_INT_FLAG);
> +
> +	return IRQ_HANDLED;
> +
> +out:
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			val | SUNXI_I2C_CNTR_MASTER_STOP);
> +
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			val & ~SUNXI_I2C_CNTR_INT_FLAG);
> +
> +	complete(&i2c_dev->completion);
> +	return IRQ_HANDLED;
> +}
> +
> +static int sunxi_i2c_xfer_msg(struct sunxi_i2c_dev *i2c_dev,
> +			      struct i2c_msg *msg)
> +{
> +	int time_left;
> +	u32 val;
> +
> +	i2c_dev->msg_cur = msg;
> +	i2c_dev->msg_buf = msg->buf;
> +	i2c_dev->msg_buf_remaining = msg->len;
> +	i2c_dev->msg_err = 0;
> +	INIT_COMPLETION(i2c_dev->completion);
> +
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	val |= SUNXI_I2C_CNTR_MASTER_START;
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG, val);
> +
> +	time_left = wait_for_completion_timeout(&i2c_dev->completion,
> +						i2c_dev->adapter.timeout);
> +	if (!time_left) {
> +		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	if (likely(i2c_dev->msg_err == SUNXI_I2C_DONE))
> +		return 0;
> +
> +	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev-
>msg_err);
> +
> +	return -EIO;
> +}
> +
> +static int sunxi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
> *msgs, +			  int num)
> +{
> +	struct sunxi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> +	int i, ret;
> +
> +	for (i = 0; i < num; i++) {
> +		ret = sunxi_i2c_xfer_msg(i2c_dev, &msgs[i]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return i;
> +}
> +
> +static u32 sunxi_i2c_func(struct i2c_adapter *adap)
> +{
> +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm sunxi_i2c_algo = {
> +	.master_xfer	= sunxi_i2c_xfer,
> +	.functionality	= sunxi_i2c_func,
> +};
> +
> +static int sunxi_i2c_probe(struct platform_device *pdev)
> +{
> +	struct sunxi_i2c_dev *i2c_dev;
> +	struct device_node *np;
> +	u32 freq, div_m, div_n;
> +	int ret;
> +
> +	np = pdev->dev.of_node;
> +	if (!np)
> +		return -EINVAL;
> +
> +	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
> +	if (!i2c_dev)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, i2c_dev);
> +	i2c_dev->dev = &pdev->dev;
> +
> +	init_completion(&i2c_dev->completion);
> +
> +	i2c_dev->membase = of_iomap(np, 0);

What about calling platform_get_resource() and devm_ioremap_resource() 
here? This would make the mapping managed and eliminate the need to unmap 
it manually.

> +	if (!i2c_dev->membase)
> +		return -EADDRNOTAVAIL;
> +
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_SRST_REG, 
SUNXI_I2C_SRST_RESET);

Hmm, is it really correct to write to device registers before enabling its 
clock?

> +
> +	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(i2c_dev->clk)) {
> +		ret = PTR_ERR(i2c_dev->clk);
> +		goto out_iounmap;
> +	}
> +	clk_prepare_enable(i2c_dev->clk);
> +
> +	ret = of_property_read_u32(np, "clock-frequency", &freq);
> +	if (ret < 0) {
> +		dev_warn(&pdev->dev, "Could not read clock-frequency 
property\n");
> +		freq = 100000;
> +	}
> +
> +	/*
> +	 * Set the clock dividers. we don't need to be super smart
> +	 * here, the datasheet defines the value of the factors for
> +	 * the two supported frequencies, and only the M factor
> +	 * changes between 100kHz and 400kHz.
> +	 *
> +	 * The bus clock is generated from the parent clock with two
> +	 * different dividers. It is generated as such:
> +	 *     f0 = fclk / (2 ^ DIV_N)
> +	 *     fbus = f0 / (10 * (DIV_M + 1))
> +	 *
> +	 * With DIV_N being on 3 bits, and DIV_M on 4 bits.
> +	 * So DIV_N < 8, and DIV_M < 16.
> +	 *
> +	 * However, we can generate both the supported frequencies
> +	 * with f0 = 12MHz, and only change M to get back on our
> +	 * feet.
> +	 */
> +	div_n = ilog2(clk_get_rate(i2c_dev->clk) / 12000000);
> +	if (freq == 100000)
> +		div_m = 11;
> +	else if (freq == 400000)
> +		div_m = 2;
> +	else {
> +		dev_err(&pdev->dev, "Unsupported bus frequency\n");
> +		ret = -EINVAL;
> +		goto out_clk_dis;
> +	}
> +
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CCR_REG,
> +			SUNXI_I2C_CCR_DIV_N(div_n) | 
SUNXI_I2C_CCR_DIV_M(div_m));
> +
> +	i2c_dev->irq = irq_of_parse_and_map(np, 0);

IMHO platform_get_irq() would be enough here.

Best regards,
Tomasz

> +	if (!i2c_dev->irq) {
> +		dev_err(&pdev->dev, "No IRQ resource\n");
> +		ret = -ENODEV;
> +		goto out_clk_dis;
> +	}
> +	ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 
sunxi_i2c_handler,
> +			       IRQF_SHARED, dev_name(&pdev->dev), 
i2c_dev);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not request IRQ\n");
> +		goto out_clk_dis;
> +	}
> +
> +	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
> +
> +	i2c_dev->adapter.owner = THIS_MODULE;
> +	strlcpy(i2c_dev->adapter.name, "sunxi I2C adapter",
> +		sizeof(i2c_dev->adapter.name));
> +	i2c_dev->adapter.algo = &sunxi_i2c_algo;
> +	i2c_dev->adapter.dev.parent = &pdev->dev;
> +
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			SUNXI_I2C_CNTR_BUS_ENABLE | 
SUNXI_I2C_CNTR_INT_ENABLE);
> +
> +	ret = i2c_add_adapter(&i2c_dev->adapter);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to register i2c adapter\n");
> +		goto out_clk_dis;
> +	}
> +
> +	return 0;
> +
> +out_clk_dis:
> +	clk_disable_unprepare(i2c_dev->clk);
> +out_iounmap:
> +	iounmap(i2c_dev->membase);
> +	return ret;
> +}
> +
> +
> +static int sunxi_i2c_remove(struct platform_device *pdev)
> +{
> +	struct sunxi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
> +
> +	i2c_del_adapter(&i2c_dev->adapter);
> +	clk_disable_unprepare(i2c_dev->clk);
> +	iounmap(i2c_dev->membase);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sunxi_i2c_of_match[] = {
> +	{ .compatible = "allwinner,sun4i-i2c" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_i2c_of_match);
> +
> +static struct platform_driver sunxi_i2c_driver = {
> +	.probe		= sunxi_i2c_probe,
> +	.remove		= sunxi_i2c_remove,
> +	.driver		= {
> +		.name	= "i2c-sunxi",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = sunxi_i2c_of_match,
> +	},
> +};
> +module_platform_driver(sunxi_i2c_driver);
> +
> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com");
> +MODULE_DESCRIPTION("Allwinner A1X I2C bus adapter");
> +MODULE_LICENSE("GPL");


From maxime.ripard at free-electrons.com  Sat May 25 08:11:11 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sat, 25 May 2013 14:11:11 +0200
Subject: [PATCH v3] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <1369479567-15104-1-git-send-email-carlo.caione@gmail.com>
References: <1369479567-15104-1-git-send-email-carlo.caione@gmail.com>
Message-ID: <20130525121111.GC17847@lukather>

Hi Carlo,

On Sat, May 25, 2013 at 12:59:27PM +0200, Carlo Caione wrote:
> This patch adds the driver for the watchdog found in the Allwinner A10 and
> A13 SoCs. It has DT-support and uses the new watchdog framework.
> 
> Signed-off-by: Carlo Caione <carlo.caione at gmail.com>

It looks good to me.

Acked-by: Maxime Ripard <maxime.ripard at free-electrons.com>

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Sat May 25 08:22:08 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sat, 25 May 2013 14:22:08 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <519FE0AE.2010102@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <51969EA9.1060602@free-electrons.com>
 <5197B82F.8010809@schinagl.nl> <519FE0AE.2010102@schinagl.nl>
Message-ID: <20130525122208.GD17847@lukather>

Hi Oliver,

On Fri, May 24, 2013 at 11:50:38PM +0200, Oliver Schinagl wrote:
> On 05/18/13 19:19, Oliver Schinagl wrote:
> <snip>
> >>>+
> >>>+
> >>>+/* We read the entire key, using a look up table. Returned is only the
> >>>+ * requested byte. This is of course slower then it could be and uses 4 times
> >>>+ * more reads as needed but keeps code a little simpler.
> >>>+ */
> >>>+u8 sunxi_sid_read_byte(const int key)
> >>>+{
> >>>+	u32 sid_key;
> >>>+	u8 ret;
> >>>+
> >>>+	ret = 0;
> >>>+	if (likely((key <= SUNXI_SID_SIZE))) {
> >>>+		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
> >>>+		switch (key % 4) {
> >>>+		case 0:
> >>>+			ret = (sid_key >> 24) & 0xff;
> >>>+			break;
> >>>+		case 1:
> >>>+			ret = (sid_key >> 16) & 0xff;
> >>>+			break;
> >>>+		case 2:
> >>>+			ret = (sid_key >> 8) & 0xff;
> >>>+			break;
> >>>+		case 3:
> >>>+			ret = sid_key & 0xff;
> >>>+			break;
> >>>+		}
> >>>+	}
> >>
> >>Come on, you can do better. This lookup table is useless.
> >I didn't want to depend on the fixed layout of memory, but consider it
> >removed.
> But i'm not smart enough :p
> 
> We can either use the look up table (which does have benefits as its
> potentially more future proof), or do some ((key >> 2) << 2) to
> 'drop' the LSB's that we want to ignore (unless there's some smarter
> way).
> 
> Personally, I think the LUT is a little cleaner and more readable,
> but I guess if you look at poor efficiency, the lut costs some
> memory, the left/right shift cost an additional >> 2 ... what you
> prefer.

What about:

val = ioread32be(base + (key / 4));
val >>= (key % 4) * 8;
return val & 0xff;

No lookup table, no weird swich statement, and you get the endianness
conversion only when you need it.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From gregkh at linuxfoundation.org  Sat May 25 08:22:40 2013
From: gregkh at linuxfoundation.org (Greg KH)
Date: Sat, 25 May 2013 05:22:40 -0700
Subject: [PATCH] module: use a macro instead of platform_driver_register
In-Reply-To: <51A040D2.20708@huawei.com>
References: <51A040D2.20708@huawei.com>
Message-ID: <20130525122240.GC3746@kroah.com>

On Sat, May 25, 2013 at 12:40:50PM +0800, Libo Chen wrote:
> 
> I found a lot of mistakes using struct platform_driver without owner
> so I make a macro instead of the function platform_driver_register.
> It can set owner in it, then guys don`t care about module owner again.
> 
> Signed-off-by: Libo Chen <libo.chen at huawei.com>

Nice job, that's the better way to fix this, I'll queue it up for 3.11.

thanks,

greg k-h


From thomas.petazzoni at free-electrons.com  Sat May 25 09:36:18 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 25 May 2013 15:36:18 +0200
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
In-Reply-To: <20130524183310.GA31290@titan.lakedaemon.net>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130524183310.GA31290@titan.lakedaemon.net>
Message-ID: <20130525153618.3a4fbc7b@skate>

Dear Jason Cooper,

On Fri, 24 May 2013 14:33:10 -0400, Jason Cooper wrote:

> >  27 files changed, 235 insertions(+), 240 deletions(-)
> 
> Whole series applied to mvebu/dt with one small change, s/affect/move/
> on the Subjects.

Ok, thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From maxime.ripard at free-electrons.com  Sat May 25 11:21:09 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sat, 25 May 2013 17:21:09 +0200
Subject: [PATCH v3] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <1369479567-15104-1-git-send-email-carlo.caione@gmail.com>
References: <1369479567-15104-1-git-send-email-carlo.caione@gmail.com>
Message-ID: <20130525152109.GE17847@lukather>

Hi Carlo,

Just two minors things I was pointed to.

On Sat, May 25, 2013 at 12:59:27PM +0200, Carlo Caione wrote:
> This patch adds the driver for the watchdog found in the Allwinner A10 and
> A13 SoCs. It has DT-support and uses the new watchdog framework.
> 
> Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
> ---
>  drivers/watchdog/Kconfig     |  10 ++
>  drivers/watchdog/Makefile    |   1 +
>  drivers/watchdog/sunxi_wdt.c | 224 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 235 insertions(+)
>  create mode 100644 drivers/watchdog/sunxi_wdt.c
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index e89fc31..8ad2238 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -299,6 +299,16 @@ config ORION_WATCHDOG
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called orion_wdt.
>  
> +config SUNXI_WATCHDOG
> +	tristate "Allwinner SoCs watchdog support"
> +	depends on ARCH_SUNXI
> +	select WATCHDOG_CORE
> +	help
> +	  Say Y here to include support for the watchdog timer
> +	  in Allwinner SoCs.
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called sunxi_wdt.
> +
>  config COH901327_WATCHDOG
>  	bool "ST-Ericsson COH 901 327 watchdog"
>  	depends on ARCH_U300
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index a300b94..5012d5f 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
>  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
>  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
>  obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
> +obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
>  obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
>  obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
>  obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
> diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
> new file mode 100644
> index 0000000..270d41e
> --- /dev/null
> +++ b/drivers/watchdog/sunxi_wdt.c
> @@ -0,0 +1,224 @@
> +/*
> + *      sunxi Watchdog Driver
> + *
> + *      Copyright (c) 2013 Carlo Caione <carlo.caione at gmail.com>
> + *                    2012 Henrik Nordstrom <henrik at henriknordstrom.net>
> + *
> + *      This program is free software; you can redistribute it and/or
> + *      modify it under the terms of the GNU General Public License
> + *      as published by the Free Software Foundation; either version
> + *      2 of the License, or (at your option) any later version.
> + *
> + *      Based on xen_wdt.c
> + *      (c) Copyright 2010 Novell, Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +#include <linux/watchdog.h>
> +
> +#define WDT_MAX_TIMEOUT         16
> +#define WDT_MIN_TIMEOUT         1
> +#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
> +#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
> +
> +#define WDT_CTRL                0x00
> +#define WDT_CTRL_RELOAD         ((1 << 0) | (0x0a57 << 1))
> +
> +#define WDT_MODE                0x04
> +#define WDT_MODE_EN             (1 << 0)
> +#define WDT_MODE_RST_EN         (1 << 1)
> +
> +#define DRV_NAME		"sunxi-wdt"
> +#define DRV_VERSION		"1.0"
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +static int heartbeat = WDT_MAX_TIMEOUT;
> +
> +/*
> + * wdt_timeout_map maps the watchdog timer interval value in seconds to
> + * the value of the register WDT_MODE bit 3:6
> + *
> + * [timeout seconds] = register value
> + *
> + */
> +
> +static const int wdt_timeout_map[] = {
> +	[1] = 0b0001,  /* 1s  */
> +	[2] = 0b0010,  /* 2s  */
> +	[3] = 0b0011,  /* 3s  */
> +	[4] = 0b0100,  /* 4s  */
> +	[5] = 0b0101,  /* 5s  */
> +	[6] = 0b0110,  /* 6s  */
> +	[8] = 0b0111,  /* 8s  */
> +	[10] = 0b1000, /* 10s */
> +	[12] = 0b1001, /* 12s */
> +	[14] = 0b1010, /* 14s */
> +	[16] = 0b1011, /* 16s */
> +};
> +
> +static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	iowrite32(WDT_CTRL_RELOAD, wdt_base + WDT_CTRL);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
> +		unsigned int timeout)
> +{
> +	u32 reg;
> +	int ret = 0;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout])) {
> +		ret = -EINVAL;
> +		goto exit;
> +	}
> +
> +	sunxi_wdt_dev->timeout = timeout;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg &= ~(WDT_TIMEOUT_MASK);
> +	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	sunxi_wdt_ping(sunxi_wdt_dev);
> +
> +exit:
> +	return ret;
> +}
> +
> +static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	iowrite32(0, wdt_base + WDT_MODE);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	int ret = 0;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
> +	if (ret < 0)
> +		goto exit;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +exit:
> +	return ret;
> +}
> +
> +static const struct watchdog_info sunxi_wdt_info = {
> +	.identity	= DRV_NAME,
> +	.options	= WDIOF_SETTIMEOUT |
> +			  WDIOF_KEEPALIVEPING |
> +			  WDIOF_MAGICCLOSE,
> +};
> +
> +static const struct watchdog_ops sunxi_wdt_ops = {
> +	.owner		= THIS_MODULE,
> +	.start		= sunxi_wdt_start,
> +	.stop		= sunxi_wdt_stop,
> +	.ping		= sunxi_wdt_ping,
> +	.set_timeout	= sunxi_wdt_set_timeout,
> +};
> +
> +static struct watchdog_device sunxi_wdt_dev = {
> +	.info		= &sunxi_wdt_info,
> +	.ops		= &sunxi_wdt_ops,
> +	.timeout	= WDT_MAX_TIMEOUT,
> +	.max_timeout	= WDT_MAX_TIMEOUT,
> +	.min_timeout	= WDT_MIN_TIMEOUT,
> +};
> +
> +static int __init sunxi_wdt_probe(struct platform_device *pdev)
> +{
> +	int err;
> +	void __iomem *wdt_base;
> +
> +	wdt_base = of_iomap(pdev->dev.of_node, 0);

of_iomap won't request the memory region, you should use
devm_ioremap_resource that will call request_mem_region, while of_iomap
doesn't.

> +	if (unlikely(!wdt_base)) {
> +		err = -ENOMEM;
> +		goto error_mem_out;
> +	}
> +
> +	sunxi_wdt_dev.parent = &pdev->dev;
> +	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
> +	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
> +
> +	err = watchdog_register_device(&sunxi_wdt_dev);
> +	if (unlikely(err))
> +		goto error_wdt;
> +
> +	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
> +
> +	pr_info("Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
> +			sunxi_wdt_dev.timeout, nowayout);

You should use dev_info here.

> +	return 0;
> +
> +error_wdt:
> +	iounmap(wdt_base);
> +error_mem_out:
> +	return err;
> +}
> +
> +static int __exit sunxi_wdt_remove(struct platform_device *pdev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
> +
> +	sunxi_wdt_stop(&sunxi_wdt_dev);
> +	watchdog_unregister_device(&sunxi_wdt_dev);
> +	iounmap(wdt_base);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sunxi_wdt_dt_ids[] = {
> +	{ .compatible = "allwinner,sun4i-wdt" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
> +
> +static struct platform_driver sunxi_wdt_driver = {
> +	.probe		= sunxi_wdt_probe,
> +	.remove		= sunxi_wdt_remove,
> +	.driver		= {
> +		.owner		= THIS_MODULE,
> +		.name		= DRV_NAME,
> +		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
> +	},
> +};
> +
> +module_platform_driver(sunxi_wdt_driver);
> +
> +module_param(heartbeat, int, 0);
> +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
> +
> +module_param(nowayout, bool, 0);
> +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
> +		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
> +MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
> +MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
> +MODULE_VERSION(DRV_VERSION);
> -- 
> 1.8.2.3
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From maxime.ripard at free-electrons.com  Sat May 25 11:22:31 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sat, 25 May 2013 17:22:31 +0200
Subject: [PATCH 1/5] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <2868419.vHvm2rOVdd@flatron>
References: <1367572669-24354-1-git-send-email-maxime.ripard@free-electrons.com>
 <1367572669-24354-2-git-send-email-maxime.ripard@free-electrons.com>
 <2868419.vHvm2rOVdd@flatron>
Message-ID: <20130525152231.GF17847@lukather>

Hi Tomasz,

On Sat, May 25, 2013 at 02:06:51PM +0200, Tomasz Figa wrote:
> Hi Maxime,
> 
> Overall the driver looks good, just some minor nitpicks inline.

Thanks for the review!

I'll fix the comments you had and send a new version.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From carlo.caione at gmail.com  Sat May 25 12:28:17 2013
From: carlo.caione at gmail.com (Carlo Caione)
Date: Sat, 25 May 2013 18:28:17 +0200
Subject: [PATCH v4] ARM: sunxi: New watchdog driver for Allwinner A10/A13
Message-ID: <1369499297-855-1-git-send-email-carlo.caione@gmail.com>

This patch adds the driver for the watchdog found in the Allwinner A10 and
A13 SoCs. It has DT-support and uses the new watchdog framework.

Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
---
 drivers/watchdog/Kconfig     |  10 ++
 drivers/watchdog/Makefile    |   1 +
 drivers/watchdog/sunxi_wdt.c | 226 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 237 insertions(+)
 create mode 100644 drivers/watchdog/sunxi_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e89fc31..8ad2238 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -299,6 +299,16 @@ config ORION_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called orion_wdt.
 
+config SUNXI_WATCHDOG
+	tristate "Allwinner SoCs watchdog support"
+	depends on ARCH_SUNXI
+	select WATCHDOG_CORE
+	help
+	  Say Y here to include support for the watchdog timer
+	  in Allwinner SoCs.
+	  To compile this driver as a module, choose M here: the
+	  module will be called sunxi_wdt.
+
 config COH901327_WATCHDOG
 	bool "ST-Ericsson COH 901 327 watchdog"
 	depends on ARCH_U300
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a300b94..5012d5f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
 obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
 obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
+obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
 obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
 obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
new file mode 100644
index 0000000..57983c0
--- /dev/null
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -0,0 +1,226 @@
+/*
+ *      sunxi Watchdog Driver
+ *
+ *      Copyright (c) 2013 Carlo Caione
+ *                    2012 Henrik Nordstrom
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Based on xen_wdt.c
+ *      (c) Copyright 2010 Novell, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/watchdog.h>
+
+#define WDT_MAX_TIMEOUT         16
+#define WDT_MIN_TIMEOUT         1
+#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
+#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
+
+#define WDT_CTRL                0x00
+#define WDT_CTRL_RELOAD         ((1 << 0) | (0x0a57 << 1))
+
+#define WDT_MODE                0x04
+#define WDT_MODE_EN             (1 << 0)
+#define WDT_MODE_RST_EN         (1 << 1)
+
+#define DRV_NAME		"sunxi-wdt"
+#define DRV_VERSION		"1.0"
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+static int heartbeat = WDT_MAX_TIMEOUT;
+
+/*
+ * wdt_timeout_map maps the watchdog timer interval value in seconds to
+ * the value of the register WDT_MODE bit 3:6
+ *
+ * [timeout seconds] = register value
+ *
+ */
+
+static const int wdt_timeout_map[] = {
+	[1] = 0b0001,  /* 1s  */
+	[2] = 0b0010,  /* 2s  */
+	[3] = 0b0011,  /* 3s  */
+	[4] = 0b0100,  /* 4s  */
+	[5] = 0b0101,  /* 5s  */
+	[6] = 0b0110,  /* 6s  */
+	[8] = 0b0111,  /* 8s  */
+	[10] = 0b1000, /* 10s */
+	[12] = 0b1001, /* 12s */
+	[14] = 0b1010, /* 14s */
+	[16] = 0b1011, /* 16s */
+};
+
+static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	iowrite32(WDT_CTRL_RELOAD, wdt_base + WDT_CTRL);
+
+	return 0;
+}
+
+static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
+		unsigned int timeout)
+{
+	u32 reg;
+	int ret = 0;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout])) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	sunxi_wdt_dev->timeout = timeout;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg &= ~(WDT_TIMEOUT_MASK);
+	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+	sunxi_wdt_ping(sunxi_wdt_dev);
+
+exit:
+	return ret;
+}
+
+static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	iowrite32(0, wdt_base + WDT_MODE);
+
+	return 0;
+}
+
+static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
+{
+	u32 reg;
+	int ret = 0;
+	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
+
+	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
+	if (ret < 0)
+		goto exit;
+
+	reg = ioread32(wdt_base + WDT_MODE);
+	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
+	iowrite32(reg, wdt_base + WDT_MODE);
+
+exit:
+	return ret;
+}
+
+static const struct watchdog_info sunxi_wdt_info = {
+	.identity	= DRV_NAME,
+	.options	= WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING |
+			  WDIOF_MAGICCLOSE,
+};
+
+static const struct watchdog_ops sunxi_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= sunxi_wdt_start,
+	.stop		= sunxi_wdt_stop,
+	.ping		= sunxi_wdt_ping,
+	.set_timeout	= sunxi_wdt_set_timeout,
+};
+
+static struct watchdog_device sunxi_wdt_dev = {
+	.info		= &sunxi_wdt_info,
+	.ops		= &sunxi_wdt_ops,
+	.timeout	= WDT_MAX_TIMEOUT,
+	.max_timeout	= WDT_MAX_TIMEOUT,
+	.min_timeout	= WDT_MIN_TIMEOUT,
+};
+
+static int __init sunxi_wdt_probe(struct platform_device *pdev)
+{
+	int err;
+	struct resource *res;
+	void __iomem *wdt_base;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	wdt_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(wdt_base)) {
+		err = PTR_ERR(wdt_base);
+		goto error_mem_out;
+	}
+
+	sunxi_wdt_dev.parent = &pdev->dev;
+	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
+	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
+
+	err = watchdog_register_device(&sunxi_wdt_dev);
+	if (unlikely(err))
+		goto error_wdt;
+
+	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
+
+	dev_info(&pdev->dev, "Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
+			sunxi_wdt_dev.timeout, nowayout);
+	return 0;
+
+error_wdt:
+	iounmap(wdt_base);
+error_mem_out:
+	return err;
+}
+
+static int __exit sunxi_wdt_remove(struct platform_device *pdev)
+{
+	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
+
+	sunxi_wdt_stop(&sunxi_wdt_dev);
+	watchdog_unregister_device(&sunxi_wdt_dev);
+	iounmap(wdt_base);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_wdt_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-wdt" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
+
+static struct platform_driver sunxi_wdt_driver = {
+	.probe		= sunxi_wdt_probe,
+	.remove		= sunxi_wdt_remove,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= DRV_NAME,
+		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
+	},
+};
+
+module_platform_driver(sunxi_wdt_driver);
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
+
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
+		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
+MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
+MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
+MODULE_VERSION(DRV_VERSION);
-- 
1.8.2.3



From andrew at lunn.ch  Sat May 25 12:54:09 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 25 May 2013 18:54:09 +0200
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130525165409.GZ26249@lunn.ch>

On Fri, May 24, 2013 at 11:44:37AM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> This series of patches has the goal of adding support for the Init
> button on OpenBlocks A6, but takes this opportunity to do a little bit
> of cleanup in the pinmux configurations of the various Kirkwood Device
> Trees.
> 
> Until now, all pinmux configurations were "owned" by the pinctrl
> driver, because back when they were introduced, the driver core was
> not selecting the pinmux configuration, each driver had to do it
> manually (and not all drivers were doing so). Now that the driver core
> selects the default pinmux configuration when available, it makes
> sense to associate the pinmux configuration to the particular device
> it is related to.
> 
> It allows pinctrl to show nice informations in debugfs, which
> associates a particular pin with the particular device using it:
> 
> # cat pinctrl/f1010000.pinctrl/pinmux-pins 
> Pinmux settings per pin
> Format: pin (name): mux_owner gpio_owner hog?
> pin 0 (PIN0): f4000000.nand (GPIO UNCLAIMED) function nand group mpp0
> pin 1 (PIN1): f4000000.nand (GPIO UNCLAIMED) function nand group mpp1
> pin 2 (PIN2): f4000000.nand (GPIO UNCLAIMED) function nand group mpp2
> pin 3 (PIN3): f4000000.nand (GPIO UNCLAIMED) function nand group mpp3
> pin 4 (PIN4): f4000000.nand (GPIO UNCLAIMED) function nand group mpp4
> pin 5 (PIN5): f4000000.nand (GPIO UNCLAIMED) function nand group mpp5
> pin 6 (PIN6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 7 (PIN7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 8 (PIN8): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp8
> pin 9 (PIN9): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp9
> pin 10 (PIN10): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp10
> pin 11 (PIN11): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp11
> pin 12 (PIN12): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 13 (PIN13): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp13
> pin 14 (PIN14): f1012100.serial (GPIO UNCLAIMED) function uart1 group mpp14
> pin 15 (PIN15): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp15
> pin 16 (PIN16): f1012000.serial (GPIO UNCLAIMED) function uart0 group mpp16
> pin 17 (PIN17): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 18 (PIN18): f4000000.nand (GPIO UNCLAIMED) function nand group mpp18
> pin 19 (PIN19): f4000000.nand (GPIO UNCLAIMED) function nand group mpp19
> pin 20 (PIN20): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp20
> pin 21 (PIN21): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp21
> pin 22 (PIN22): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp22
> pin 23 (PIN23): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp23
> pin 24 (PIN24): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp24
> pin 25 (PIN25): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp25
> pin 26 (PIN26): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp26
> pin 27 (PIN27): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp27
> pin 28 (PIN28): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp28
> pin 29 (PIN29): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp29
> pin 30 (PIN30): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp30
> pin 31 (PIN31): f1010000.pinctrl (GPIO UNCLAIMED) (HOG) function gpio group mpp31
> pin 32 (PIN32): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 33 (PIN33): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 34 (PIN34): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 35 (PIN35): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 36 (PIN36): f1011100.i2c (GPIO UNCLAIMED) function twsi1 group mpp36
> pin 37 (PIN37): f1011100.i2c (GPIO UNCLAIMED) function twsi1 group mpp37
> pin 38 (PIN38): gpio_keys.2 mvebu-gpio:38 function gpio group mpp38
> pin 39 (PIN39): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 40 (PIN40): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 41 (PIN41): gpio-leds.1 mvebu-gpio:41 function gpio group mpp41
> pin 42 (PIN42): gpio-leds.1 mvebu-gpio:42 function gpio group mpp42
> pin 43 (PIN43): gpio-leds.1 mvebu-gpio:43 function gpio group mpp43
> pin 44 (PIN44): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 45 (PIN45): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 46 (PIN46): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 47 (PIN47): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 48 (PIN48): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> pin 49 (PIN49): (MUX UNCLAIMED) (GPIO UNCLAIMED)
> 
> Without this patch set, all pins appear to be owned by
> "f1010000.pinctrl".
> 
> Even though GPIO muxing is automatically done when a device driver
> requests a GPIO, Andrew Lunn and I had agreed to make the pinmuxing
> explicit, in order to have correct informations in debugfs. See our
> discussion at
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-March/158190.html.
> 
> The last patch finally adds support for the init button of the
> Plathome OpenBlocks A6 platform.
> 
> Best regards,
> 
> Thomas

Hi Thomas, Jason

You can add a

Tested-By: Andrew Lunn <andrew at lunn.ch>

to the topkick and ts219 patches, and a general 

Acked-by: Andrew Lunn <andrew at lunn.ch>

to the rest.

	 Andrew

> 
> Thomas Petazzoni (21):
>   arm: kirkwood: cloudbox: affect pinmux configs to the right devices
>   arm: kirkwood: dlink dns: affect pinmux configs to the right devices
>   arm: kirkwood: dockstar: affect pinmux configs to the right devices
>   arm: kirkwood: dreamplug: affect pinmux configs to the right devices
>   arm: kirkwood: goflexnet: affect pinmux configs to the right devices
>   arm: kirkwood: guruplug: affect pinmux configs to the right devices
>   arm: kirkwood: ib62x0: affect pinmux configs to the right devices
>   arm: kirkwood: iconnect: give meaningful names to pinmux configs
>   arm: kirkwood: iconnect: affect pinmux configs to the right devices
>   arm: kirkwood: iomega ix2-200: affect pinmux configs to the right
>     devices
>   arm: kirkwood: ns2: affect pinmux configs to the right devices
>   arm: kirkwood: keymile: affect pinmux configs to the right devices
>   arm: kirkwood: buffalo linkstation: affect pinmux configs to the
>     right devices
>   arm: kirkwood: mplcec4: affect pinmux configs to the right devices
>   arm: kirkwood: readynas: affect pinmux configs to the right devices
>   arm: kirkwood: nsa310: affect pinmux configs to the right devices
>   arm: kirkwood: openblocks_a6: affect pinmux configs to the right
>     devices
>   arm: kirkwood: topkick: affect pinmux configs to the right devices
>   arm: kirkwood: ts219: affect pinmux configs to the right devices
>   arm: kirkwood: openblocks-a6: group pinmux configurations
>   arm: kirkwood: openblocks-a6: add support for Init button
> 
>  arch/arm/boot/dts/kirkwood-cloudbox.dts            |   10 +-
>  arch/arm/boot/dts/kirkwood-dns320.dts              |    7 ++
>  arch/arm/boot/dts/kirkwood-dns325.dts              |    5 +
>  arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   32 +++---
>  arch/arm/boot/dts/kirkwood-dockstar.dts            |    9 +-
>  arch/arm/boot/dts/kirkwood-dreamplug.dts           |   11 +-
>  arch/arm/boot/dts/kirkwood-goflexnet.dts           |   18 ++--
>  .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |    8 +-
>  arch/arm/boot/dts/kirkwood-ib62x0.dts              |   17 +--
>  arch/arm/boot/dts/kirkwood-iconnect.dts            |   36 +++----
>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   15 +--
>  arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
>  arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |    6 +-
>  arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   22 ++--
>  arch/arm/boot/dts/kirkwood-mplcec4.dts             |   23 +++--
>  .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   22 ++--
>  arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   10 +-
>  arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
>  arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
>  arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
>  arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
>  arch/arm/boot/dts/kirkwood-nsa310.dts              |   29 +++---
>  arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |  108 ++++++--------------
>  arch/arm/boot/dts/kirkwood-topkick.dts             |   51 ++++-----
>  arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    8 +-
>  arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    8 +-
>  arch/arm/boot/dts/kirkwood-ts219.dtsi              |   10 ++
>  27 files changed, 235 insertions(+), 240 deletions(-)
> 
> -- 
> 1.7.9.5
> 


From prabhakar.csengg at gmail.com  Sat May 25 13:43:29 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Sat, 25 May 2013 23:13:29 +0530
Subject: [PATCH v2 1/4] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <1369503576-22271-2-git-send-email-prabhakar.csengg@gmail.com>
References: <1369503576-22271-1-git-send-email-prabhakar.csengg@gmail.com>
 <1369503576-22271-2-git-send-email-prabhakar.csengg@gmail.com>
Message-ID: <CA+V-a8sAXXq=gBO_uDsOS1MonXJan+mpBwo15tvp+wR40kAMKA@mail.gmail.com>

Hi Sekhar,

On Sat, May 25, 2013 at 11:09 PM, Prabhakar Lad
<prabhakar.csengg at gmail.com> wrote:
> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>
> remove init_enable from ths7303 pdata as it is being dropped
> from ths7303_platform_data.
>
Can you please ack this patch as I intend to take this patch via media
tree.

Regards,
--Prabhakar Lad


From festevam at gmail.com  Sat May 25 13:47:28 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Sat, 25 May 2013 14:47:28 -0300
Subject: [PATCH] ARM: mx6: Use the same sdma firmware name for all mx6 variants
Message-ID: <1369504048-19805-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

All the mx6 variants (quad, dual, solo and solo-lite) use the same sdma 
firmware, so drop the the suffix from the file name.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
 arch/arm/boot/dts/imx6sl.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461c..b6730cc 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -582,7 +582,7 @@
 				interrupts = <0 2 0x04>;
 				clocks = <&clks 155>, <&clks 155>;
 				clock-names = "ipg", "ahb";
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6.bin";
 			};
 		};
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c5e5da0..9596000 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -594,7 +594,7 @@
 				clocks = <&clks IMX6SL_CLK_SDMA>,
 					 <&clks IMX6SL_CLK_SDMA>;
 				clock-names = "ipg", "ahb";
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6.bin";
 			};
 
 			pxp: pxp at 020f0000 {
-- 
1.8.1.2



From sergei.shtylyov at cogentembedded.com  Sat May 25 14:08:35 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Sat, 25 May 2013 22:08:35 +0400
Subject: [PATCH v2] ARM: shmobile: BOCK-W: add Ether support
In-Reply-To: <20130525053007.GA9293@verge.net.au>
References: <201305170141.59791.sergei.shtylyov@cogentembedded.com>
 <20130525053007.GA9293@verge.net.au>
Message-ID: <51A0FE23.4090206@cogentembedded.com>

Hello.

On 25-05-2013 9:30, Simon Horman wrote:

>> Register Ether device from bockw_init(), passing the platform data to it, adding
>> only the RMII pin group to bockw_pinctrl_map[].  Although the LINK signal exists
>> on the board, it's connected to the link/activity LED  output of the PHY, thus
>> the link disappears and reappears after each packet. We'd be better off ignoring
>> such signal and getting the link state from the PHY indirectly.

>> Also, Ether has pin conflict with VIN1, so the latter is not registered when the
>> 'sh_eth' driver is enabled now.

>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>
>> ---
>> The patch is atop of Simon's 'renesas.git' repo, 'renesas-next-20130515v2' tag
>> and my recent yet unapplied patches.

>> Note that it's compile and run time dependent on the current Linus' tree.

>> Changes from the original posting:
>> - refreshed the patch.

> Thanks, would it be possible for you to rebase it on top of
> renesas-next-20130523.

    You mean to base it on this tag without any intervening patches (it 
is now on top of my patch series)? Anyway, I'll rebase my whole series 
on this tag as I have time (I'm now working with the SATA driver to try 
to add to it NCQ support and fixing errors I encounter on the way).

> renesas-next-20130523 is based on v3.10-rc2, so I think it should
> have whatever dependencies that were in Linus's tree at the time
> that you posted this patch.

     Yes, correct.

WBR, Sergei



From sergei.shtylyov at cogentembedded.com  Sat May 25 14:32:57 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Sat, 25 May 2013 22:32:57 +0400
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <20130525010309.GG4476@verge.net.au>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <519F72F8.1000204@cogentembedded.com> <20130525010309.GG4476@verge.net.au>
Message-ID: <51A103D9.4080600@cogentembedded.com>

Hello.

On 25-05-2013 5:03, Simon Horman wrote:

>>> Add SATA clock for r8a7790 SoC (for both device tree and usual cases).

>>      I don't see where you are adding clock for device tree case.

>>> Register SATA controller as a "late" platform device on r8a7790 SoC.

>>      Does R8A7790 have these "early" and "late" lists? I guess not.

>>> Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
>>> Vladimir Barinov.

>>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>>> ---
>>>   arch/arm/mach-shmobile/clock-r8a7790.c |  4 ++++
>>>   arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++
>>>   2 files changed, 25 insertions(+)

>>> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
>>> index b393592..3619a52 100644
>>> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
>>> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
>> [...]
>>> @@ -249,6 +252,7 @@ static struct clk_lookup lookups[] = {
>>>   	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
>>>   	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
>>>   	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
>>> +	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
>>>   };
>>>
>>>   #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
>>> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
>>> index ed7ee24..5a2a073 100644
>>> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
>>> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
>> [...]
>>> @@ -118,6 +119,25 @@ static inline void r8a7790_register_scif(int idx)
>>>   				      sizeof(struct plat_sci_port));
>>>   }

>>> +static __init void r8a7790_register_sata1(void)

>>     What's with SATA0?

>>> +{
>>> +
>>> +	struct resource res[] = {

>>     Non-static variable with an intializer? Won't this be a waste of
>> code? Wouldn't it be better to have it static __initdata?

> Sure, if you prefer that.

    I don't know exactly what gcc will generate for the intializers but 
expect nothing particularly good. The static intialized data should 
definitely take up less space.

>>
>>> +		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),

>>      2 megabytes? Won't it be a waste of memory?

> 2 megabytes is specified in the data sheet.
> Do you think it is reasonable to use a smaller value?

    We used 0x2000 for R8A7779 SATA device -- it should be enough to 
cover all the registers.

>>> +		DEFINE_RES_IRQ(gic_iid(106)),
>>> +	};
>>> +
>>> +	struct platform_device_info pdevinfo = {

>>     Same comment about non-static initialized structure...

>>> +		.name = "sata_rcar",
>>> +		.id = 1,
>>> +		.res = res,
>>> +		.num_res = ARRAY_SIZE(res),
>>> +		.dma_mask = DMA_BIT_MASK(32),
>>> +	};
>>> +
>>> +	platform_device_register_full(&pdevinfo);
>>> +}
>>> +

WBR, Sergei



From linux at roeck-us.net  Sat May 25 14:57:13 2013
From: linux at roeck-us.net (Guenter Roeck)
Date: Sat, 25 May 2013 11:57:13 -0700
Subject: [PATCH v4] ARM: sunxi: New watchdog driver for Allwinner A10/A13
In-Reply-To: <1369499297-855-1-git-send-email-carlo.caione@gmail.com>
References: <1369499297-855-1-git-send-email-carlo.caione@gmail.com>
Message-ID: <20130525185713.GA28062@roeck-us.net>

On Sat, May 25, 2013 at 06:28:17PM +0200, Carlo Caione wrote:
> This patch adds the driver for the watchdog found in the Allwinner A10 and
> A13 SoCs. It has DT-support and uses the new watchdog framework.
> 
> Signed-off-by: Carlo Caione <carlo.caione at gmail.com>
> ---
>  drivers/watchdog/Kconfig     |  10 ++
>  drivers/watchdog/Makefile    |   1 +
>  drivers/watchdog/sunxi_wdt.c | 226 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 237 insertions(+)
>  create mode 100644 drivers/watchdog/sunxi_wdt.c
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index e89fc31..8ad2238 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -299,6 +299,16 @@ config ORION_WATCHDOG
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called orion_wdt.
>  
> +config SUNXI_WATCHDOG
> +	tristate "Allwinner SoCs watchdog support"
> +	depends on ARCH_SUNXI
> +	select WATCHDOG_CORE
> +	help
> +	  Say Y here to include support for the watchdog timer
> +	  in Allwinner SoCs.
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called sunxi_wdt.
> +
>  config COH901327_WATCHDOG
>  	bool "ST-Ericsson COH 901 327 watchdog"
>  	depends on ARCH_U300
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index a300b94..5012d5f 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
>  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
>  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
>  obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
> +obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o
>  obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
>  obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
>  obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
> diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
> new file mode 100644
> index 0000000..57983c0
> --- /dev/null
> +++ b/drivers/watchdog/sunxi_wdt.c
> @@ -0,0 +1,226 @@
> +/*
> + *      sunxi Watchdog Driver
> + *
> + *      Copyright (c) 2013 Carlo Caione
> + *                    2012 Henrik Nordstrom
> + *
> + *      This program is free software; you can redistribute it and/or
> + *      modify it under the terms of the GNU General Public License
> + *      as published by the Free Software Foundation; either version
> + *      2 of the License, or (at your option) any later version.
> + *
> + *      Based on xen_wdt.c
> + *      (c) Copyright 2010 Novell, Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +#include <linux/watchdog.h>
> +
> +#define WDT_MAX_TIMEOUT         16
> +#define WDT_MIN_TIMEOUT         1
> +#define WDT_MODE_TIMEOUT(n)     ((n) << 3)
> +#define WDT_TIMEOUT_MASK        WDT_MODE_TIMEOUT(0x0F)
> +
> +#define WDT_CTRL                0x00
> +#define WDT_CTRL_RELOAD         ((1 << 0) | (0x0a57 << 1))
> +
> +#define WDT_MODE                0x04
> +#define WDT_MODE_EN             (1 << 0)
> +#define WDT_MODE_RST_EN         (1 << 1)
> +
> +#define DRV_NAME		"sunxi-wdt"
> +#define DRV_VERSION		"1.0"
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +static int heartbeat = WDT_MAX_TIMEOUT;
> +
> +/*
> + * wdt_timeout_map maps the watchdog timer interval value in seconds to
> + * the value of the register WDT_MODE bit 3:6
> + *
> + * [timeout seconds] = register value
> + *
> + */
> +
> +static const int wdt_timeout_map[] = {
> +	[1] = 0b0001,  /* 1s  */
> +	[2] = 0b0010,  /* 2s  */
> +	[3] = 0b0011,  /* 3s  */
> +	[4] = 0b0100,  /* 4s  */
> +	[5] = 0b0101,  /* 5s  */
> +	[6] = 0b0110,  /* 6s  */
> +	[8] = 0b0111,  /* 8s  */
> +	[10] = 0b1000, /* 10s */
> +	[12] = 0b1001, /* 12s */
> +	[14] = 0b1010, /* 14s */
> +	[16] = 0b1011, /* 16s */
> +};
> +
> +static int sunxi_wdt_ping(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	iowrite32(WDT_CTRL_RELOAD, wdt_base + WDT_CTRL);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_set_timeout(struct watchdog_device *sunxi_wdt_dev,
> +		unsigned int timeout)
> +{
> +	u32 reg;
> +	int ret = 0;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	if ((timeout > WDT_MAX_TIMEOUT) || (0 == wdt_timeout_map[timeout])) {

While understand I do that Yoda programming in fashion is, never accept I would.
Mantainer differently may think, though.
Extra ( ) only confusing for me is too and no value it adds.

But seriously, I think it is not a good idea to expect the user to find valid
timeouts. I think it would be much better to select the closest (larger) timeout
if there is no exact match.

> +		ret = -EINVAL;
> +		goto exit;
> +	}
> +
> +	sunxi_wdt_dev->timeout = timeout;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg &= ~(WDT_TIMEOUT_MASK);

Another unnecessary ( )

> +	reg |= WDT_MODE_TIMEOUT(wdt_timeout_map[sunxi_wdt_dev->timeout]);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +	sunxi_wdt_ping(sunxi_wdt_dev);
> +
> +exit:
> +	return ret;
> +}
> +
> +static int sunxi_wdt_stop(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	iowrite32(0, wdt_base + WDT_MODE);
> +
> +	return 0;
> +}
> +
> +static int sunxi_wdt_start(struct watchdog_device *sunxi_wdt_dev)
> +{
> +	u32 reg;
> +	int ret = 0;
> +	void __iomem *wdt_base = watchdog_get_drvdata(sunxi_wdt_dev);
> +
> +	ret = sunxi_wdt_set_timeout(sunxi_wdt_dev, sunxi_wdt_dev->timeout);
> +	if (ret < 0)
> +		goto exit;
> +
> +	reg = ioread32(wdt_base + WDT_MODE);
> +	reg |= (WDT_MODE_RST_EN | WDT_MODE_EN);
> +	iowrite32(reg, wdt_base + WDT_MODE);
> +
> +exit:
> +	return ret;
> +}
> +
> +static const struct watchdog_info sunxi_wdt_info = {
> +	.identity	= DRV_NAME,
> +	.options	= WDIOF_SETTIMEOUT |
> +			  WDIOF_KEEPALIVEPING |
> +			  WDIOF_MAGICCLOSE,
> +};
> +
> +static const struct watchdog_ops sunxi_wdt_ops = {
> +	.owner		= THIS_MODULE,
> +	.start		= sunxi_wdt_start,
> +	.stop		= sunxi_wdt_stop,
> +	.ping		= sunxi_wdt_ping,
> +	.set_timeout	= sunxi_wdt_set_timeout,
> +};
> +
> +static struct watchdog_device sunxi_wdt_dev = {
> +	.info		= &sunxi_wdt_info,
> +	.ops		= &sunxi_wdt_ops,
> +	.timeout	= WDT_MAX_TIMEOUT,
> +	.max_timeout	= WDT_MAX_TIMEOUT,
> +	.min_timeout	= WDT_MIN_TIMEOUT,
> +};
> +
Wonder what happens if one instantiates this driver twice ?

> +static int __init sunxi_wdt_probe(struct platform_device *pdev)
> +{
> +	int err;
> +	struct resource *res;
> +	void __iomem *wdt_base;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	wdt_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(wdt_base)) {
> +		err = PTR_ERR(wdt_base);
> +		goto error_mem_out;

Just return the error. No need for a goto to a return statement.

> +	}
> +
> +	sunxi_wdt_dev.parent = &pdev->dev;
> +	watchdog_init_timeout(&sunxi_wdt_dev, heartbeat, &pdev->dev);
> +	watchdog_set_nowayout(&sunxi_wdt_dev, nowayout);
> +
> +	err = watchdog_register_device(&sunxi_wdt_dev);
> +	if (unlikely(err))
> +		goto error_wdt;
> +
> +	watchdog_set_drvdata(&sunxi_wdt_dev, wdt_base);
> +
> +	dev_info(&pdev->dev, "Watchdog enabled (heartbeat=%d sec, nowayout=%d)",
> +			sunxi_wdt_dev.timeout, nowayout);
> +	return 0;
> +
> +error_wdt:
> +	iounmap(wdt_base);

This is no longer needed (and wrong). You'll notice that the entire error path
is no longer needed, which is the whole point of having devm_ functions.

> +error_mem_out:
> +	return err;
> +}
> +
> +static int __exit sunxi_wdt_remove(struct platform_device *pdev)
> +{
> +	void __iomem *wdt_base = watchdog_get_drvdata(&sunxi_wdt_dev);
> +

> +	sunxi_wdt_stop(&sunxi_wdt_dev);

Even if nowayout is true ? Wonder how other drivers handle this.

> +	watchdog_unregister_device(&sunxi_wdt_dev);
> +	iounmap(wdt_base);

Same as above.

> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sunxi_wdt_dt_ids[] = {
> +	{ .compatible = "allwinner,sun4i-wdt" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
> +
> +static struct platform_driver sunxi_wdt_driver = {
> +	.probe		= sunxi_wdt_probe,
> +	.remove		= sunxi_wdt_remove,
> +	.driver		= {
> +		.owner		= THIS_MODULE,
> +		.name		= DRV_NAME,
> +		.of_match_table	= of_match_ptr(sunxi_wdt_dt_ids)
> +	},
> +};
> +
> +module_platform_driver(sunxi_wdt_driver);
> +
> +module_param(heartbeat, int, 0);
> +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
> +
> +module_param(nowayout, bool, 0);
> +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
> +		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Carlo Caione <carlo.caione at gmail.com>");
> +MODULE_AUTHOR("Henrik Nordstrom <henrik at henriknordstrom.net>");
> +MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
> +MODULE_VERSION(DRV_VERSION);
> -- 
> 1.8.2.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From oliver+list at schinagl.nl  Sat May 25 15:25:51 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Sat, 25 May 2013 21:25:51 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <20130525122208.GD17847@lukather>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <51969EA9.1060602@free-electrons.com> <5197B82F.8010809@schinagl.nl>
 <519FE0AE.2010102@schinagl.nl> <20130525122208.GD17847@lukather>
Message-ID: <51A1103F.6000702@schinagl.nl>

On 05/25/13 14:22, Maxime Ripard wrote:
> Hi Oliver,
>
> On Fri, May 24, 2013 at 11:50:38PM +0200, Oliver Schinagl wrote:
>> On 05/18/13 19:19, Oliver Schinagl wrote:
>> <snip>
>>>>> +
>>>>> +
>>>>> +/* We read the entire key, using a look up table. Returned is only the
>>>>> + * requested byte. This is of course slower then it could be and uses 4 times
>>>>> + * more reads as needed but keeps code a little simpler.
>>>>> + */
>>>>> +u8 sunxi_sid_read_byte(const int key)
>>>>> +{
>>>>> +	u32 sid_key;
>>>>> +	u8 ret;
>>>>> +
>>>>> +	ret = 0;
>>>>> +	if (likely((key <= SUNXI_SID_SIZE))) {
>>>>> +		sid_key = ioread32(p->sid_base + keys_lut[key >> 2]);
>>>>> +		switch (key % 4) {
>>>>> +		case 0:
>>>>> +			ret = (sid_key >> 24) & 0xff;
>>>>> +			break;
>>>>> +		case 1:
>>>>> +			ret = (sid_key >> 16) & 0xff;
>>>>> +			break;
>>>>> +		case 2:
>>>>> +			ret = (sid_key >> 8) & 0xff;
>>>>> +			break;
>>>>> +		case 3:
>>>>> +			ret = sid_key & 0xff;
>>>>> +			break;
>>>>> +		}
>>>>> +	}
>>>>
>>>> Come on, you can do better. This lookup table is useless.
>>> I didn't want to depend on the fixed layout of memory, but consider it
>>> removed.
>> But i'm not smart enough :p
>>
>> We can either use the look up table (which does have benefits as its
>> potentially more future proof), or do some ((key >> 2) << 2) to
>> 'drop' the LSB's that we want to ignore (unless there's some smarter
>> way).
>>
>> Personally, I think the LUT is a little cleaner and more readable,
>> but I guess if you look at poor efficiency, the lut costs some
>> memory, the left/right shift cost an additional >> 2 ... what you
>> prefer.
>
> What about:
>
> val = ioread32be(base + (key / 4));
> val >>= (key % 4) * 8;
> return val & 0xff;
>
> No lookup table, no weird swich statement, and you get the endianness
> conversion only when you need it.
Ok I think I like the Endianess, ioread32be does the right thing then? 
I'll read up on that.
As for key / 4; how will that work without the lut?

Lets take byte 14 (out of the available 16). Byte 14 (0x0e) is located 
in SID_KEY3, so base + 0x0c. We need to write a whole 32bit word to keep 
with alignment, the registers go wakko if you do unaligned reads. So we 
need to read the entire 32 bits, then find our byte.

key / 4 for 14 yields 0x03. So we have base + 0x03, which is not what we 
want. We want base + 0x0c, which is either ((key >> 2) << 2)) Or, ((key 
/ 4) * 4)) which to me, are both equally confusing. So we either use the 
look up table, which is a little cleaner and is a bit more future proof 
if either a) there's more 'eeprom like' storage which can be combined 
herein or b) 'a' next version has non-continuing regions. Granted 
neither is something to worry about right now.

Turl already mentioned the calculated shift, instead of the switch. I 
agree to also like it better and have already rewritten that bit.


If I made a really stupid thinking mistake or my math is somehow wrong, 
feel free to point it out :) I don't mind manning up to my mistakes :)
>
> Maxime
>



From plagnioj at jcrosoft.com  Sat May 25 16:05:57 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 25 May 2013 22:05:57 +0200
Subject: [PATCH v2] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <1369467542-25519-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369467542-25519-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <20130525200557.GO24476@game.jcrosoft.org>

On 09:39 Sat 25 May     , Alexandre Belloni wrote:
> Fixes:
> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> :(.text+0x1174): undefined reference to `mdiobus_write'
> :(.text+0x1188): undefined reference to `mdiobus_write'
> :(.text+0x119c): undefined reference to `mdiobus_write'
> :(.text+0x11b0): undefined reference to `mdiobus_write'
> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
> 
> when CONFIG_PHYLIB is not selected.
> ---
> Changes in v2:
> 	use IS_BUILTIN
> 	use CONFIG_PHYLIB and not CONFIG_PHY
> 

I do not like this, I prefer we just drop the fixup by adding the dt support
to the micrel phy as done for broadcom

if !PHYLIB just add an inline declaration of 
phy_register_fixup_for_uid

so gcc will drop ksz9021rn_phy_fixup automatically

Best Regards,
J.
> 
>  arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
>  1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> index 705305e..e9ce541 100644
> --- a/arch/arm/mach-at91/board-dt-sama5.c
> +++ b/arch/arm/mach-at91/board-dt-sama5.c
> @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
>  #define GMII_ERCR	11
>  #define GMII_ERDWR	12
>  
> -	/* Set delay values */
> -	value = GMII_RCCPSR | 0x8000;
> -	phy_write(phy, GMII_ERCR, value);
> -	value = 0xF2F4;
> -	phy_write(phy, GMII_ERDWR, value);
> -	value = GMII_RRDPSR | 0x8000;
> -	phy_write(phy, GMII_ERCR, value);
> -	value = 0x2222;
> -	phy_write(phy, GMII_ERDWR, value);
> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
> +		/* Set delay values */
> +		value = GMII_RCCPSR | 0x8000;
> +		phy_write(phy, GMII_ERCR, value);
> +		value = 0xF2F4;
> +		phy_write(phy, GMII_ERDWR, value);
> +		value = GMII_RRDPSR | 0x8000;
> +		phy_write(phy, GMII_ERCR, value);
> +		value = 0x2222;
> +		phy_write(phy, GMII_ERDWR, value);
> +	}
>  
>  	return 0;
>  }
>  
>  static void __init sama5_dt_device_init(void)
>  {
> -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
> +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
>  		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
>  			ksz9021rn_phy_fixup);
>  
> -- 
> 1.8.1.2
> 


From adam at baker-net.org.uk  Sat May 25 17:32:04 2013
From: adam at baker-net.org.uk (Adam Baker)
Date: Sat, 25 May 2013 22:32:04 +0100
Subject: Kirkwood CPU Freq driver
Message-ID: <51A12DD4.9010907@baker-net.org.uk>

Hi,

I've been trying to test Andrew Lunn's work creating a CPU Idle driver 
for Kirkwood. The first problem I encountered was that somehow in 
merging the patch the ARCH_HAS_CPUFREQ line appears to have got lost in 
arch/arm/Kconfig so I put that back (this may not be an issue if you 
build a multiarch kernel but I was targetting just Kirkwood)

--- a/arch/arm/Kconfig	2013-05-24 19:45:59.000000000 +0100
+++ b/arch/arm/Kconfig	2013-05-17 19:58:21.000000000 +0100
@@ -567,6 +567,7 @@ config ARCH_DOVE

  config ARCH_KIRKWOOD
  	bool "Marvell Kirkwood"
+	select ARCH_HAS_CPUFREQ
  	select ARCH_REQUIRE_GPIOLIB
  	select CPU_FEROCEON
  	select GENERIC_CLOCKEVENTS

Then I saw that the driver needs a cpu definition and none of the 
kirkwood dts files provide one. I believe all kirkwood SoCs are 
uniprocessor so I created an entry in kirkwood.dtsi

--- a/arch/arm/boot/dts/kirkwood.dtsi	2013-05-19 22:57:07.000000000 +0100
+++ b/arch/arm/boot/dts/kirkwood.dtsi	2013-05-19 23:10:32.000000000 +0100
@@ -4,6 +4,18 @@
  	compatible = "marvell,kirkwood";
  	interrupt-parent = <&intc>;

+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+		      device_type = "cpu";
+		      compatible = "marvell,feroceon";
+		      clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
+		      clock-names = "cpu_clk", "ddrclk", "powersave";
+		};
+	};
+
  	aliases {
  	       gpio0 = &gpio0;
  	       gpio1 = &gpio1;

(Yes I know Thunderbird has mangled the wordwrap in the patch but as I'm 
only providing it as a description of what I did not to be applied I 
won't beat it into submission this time)

As nothing seems to depend upon it I went with the CPU compatible type 
as defined in Documentation/devicetree/bindings/arm/cpus.txt rather than 
the marvell,sheeva-88SV131 in 
Documentation/devicetree/bindings/arm/kirkwood.txt

I tried putting some debug code in kirkwood_cpufreq_probe() and it 
doesn't appear to be getting called.

Have I

a) misunderstood what kirkwood variants this driver is supposed to work with
b) manged my CPU definition so it doesn't work
or c) missed some other critical configuration step?

Many thanks

Adam


From horms at verge.net.au  Sat May 25 19:22:57 2013
From: horms at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 08:22:57 +0900
Subject: [PATCH v2] ARM: shmobile: BOCK-W: add Ether support
In-Reply-To: <51A0FE23.4090206@cogentembedded.com>
References: <201305170141.59791.sergei.shtylyov@cogentembedded.com>
 <20130525053007.GA9293@verge.net.au>
 <51A0FE23.4090206@cogentembedded.com>
Message-ID: <20130525232257.GA24131@verge.net.au>

On Sat, May 25, 2013 at 10:08:35PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 25-05-2013 9:30, Simon Horman wrote:
> 
> >>Register Ether device from bockw_init(), passing the platform data to it, adding
> >>only the RMII pin group to bockw_pinctrl_map[].  Although the LINK signal exists
> >>on the board, it's connected to the link/activity LED  output of the PHY, thus
> >>the link disappears and reappears after each packet. We'd be better off ignoring
> >>such signal and getting the link state from the PHY indirectly.
> 
> >>Also, Ether has pin conflict with VIN1, so the latter is not registered when the
> >>'sh_eth' driver is enabled now.
> 
> >>Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >>
> >>---
> >>The patch is atop of Simon's 'renesas.git' repo, 'renesas-next-20130515v2' tag
> >>and my recent yet unapplied patches.
> 
> >>Note that it's compile and run time dependent on the current Linus' tree.
> 
> >>Changes from the original posting:
> >>- refreshed the patch.
> 
> >Thanks, would it be possible for you to rebase it on top of
> >renesas-next-20130523.
> 
>    You mean to base it on this tag without any intervening patches
> (it is now on top of my patch series)? Anyway, I'll rebase my whole
> series on this tag as I have time (I'm now working with the SATA
> driver to try to add to it NCQ support and fixing errors I encounter
> on the way).

In general I would prefer for you to post patches that are based on my tree
without any intervening patches as it makes it significantly easier for me
to apply them.

> >renesas-next-20130523 is based on v3.10-rc2, so I think it should
> >have whatever dependencies that were in Linus's tree at the time
> >that you posted this patch.
> 
>     Yes, correct.
> 
> WBR, Sergei
> 


From sergei.shtylyov at cogentembedded.com  Sat May 25 19:40:17 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Sun, 26 May 2013 03:40:17 +0400
Subject: [PATCH v2] ARM: shmobile: BOCK-W: add Ether support
In-Reply-To: <20130525232257.GA24131@verge.net.au>
References: <201305170141.59791.sergei.shtylyov@cogentembedded.com>
 <20130525053007.GA9293@verge.net.au> <51A0FE23.4090206@cogentembedded.com>
 <20130525232257.GA24131@verge.net.au>
Message-ID: <51A14BE1.8050907@cogentembedded.com>

Hello.

On 05/26/2013 03:22 AM, Simon Horman wrote:

>>>> Register Ether device from bockw_init(), passing the platform data to it, adding
>>>> only the RMII pin group to bockw_pinctrl_map[].  Although the LINK signal exists
>>>> on the board, it's connected to the link/activity LED  output of the PHY, thus
>>>> the link disappears and reappears after each packet. We'd be better off ignoring
>>>> such signal and getting the link state from the PHY indirectly.
>>>> Also, Ether has pin conflict with VIN1, so the latter is not registered when the
>>>> 'sh_eth' driver is enabled now.
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>>>
>>>> ---
>>>> The patch is atop of Simon's 'renesas.git' repo, 'renesas-next-20130515v2' tag
>>>> and my recent yet unapplied patches.
>>>> Note that it's compile and run time dependent on the current Linus' tree.
>>>> Changes from the original posting:
>>>> - refreshed the patch.
>>> Thanks, would it be possible for you to rebase it on top of
>>> renesas-next-20130523.
>>     You mean to base it on this tag without any intervening patches
>> (it is now on top of my patch series)? Anyway, I'll rebase my whole
>> series on this tag as I have time (I'm now working with the SATA
>> driver to try to add to it NCQ support and fixing errors I encounter
>> on the way).
> In general I would prefer for you to post patches that are based on my tree
> without any intervening patches as it makes it significantly easier for me
> to apply them.

    It's just that I've accumulated a significant queue of patches pending
merge to you tree. I'll reshuffle the series, if you consider this patch
more urgent than USB/VIN stuff.

WBR, Sergei



From rob at landley.net  Sat May 25 20:27:52 2013
From: rob at landley.net (Rob Landley)
Date: Sat, 25 May 2013 19:27:52 -0500
Subject: [PATCH] ARM: document the bigger pagetables needed for LPAE
In-Reply-To: <1369410236-22398-1-git-send-email-javi.merino@arm.com> (from
 javi.merino@arm.com on Fri May 24 10:43:56 2013)
Message-ID: <1369528072.2776.26@driftwood>

On 05/24/2013 10:43:56 AM, Javi Merino wrote:
> The Booting documentation assumes that the initial pagetables are
> 16KiB but since 1b6ba46 (ARM: LPAE: MMU setup for the 3-level page
> table format) they are 20KiB for LPAE kernels.  Thus, the
> recommendation to put atags or the dtb in the first 16KiB is wrong,
> there's only 12KiB of space there in LPAE kernels, so update the
> documentation accordingly.
> ---
>  Documentation/arm/Booting |    9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)

Acked-by: Rob Landley <rob at landley.net>

With one comment:

> diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting
> index 0c1f475..f6f9cd8 100644
> --- a/Documentation/arm/Booting
> +++ b/Documentation/arm/Booting
> @@ -105,7 +105,7 @@ The tagged list should be stored in system RAM.
> 
>  The tagged list must be placed in a region of memory where neither
>  the kernel decompressor nor initrd 'bootp' program will overwrite
> -it.  The recommended placement is in the first 16KiB of RAM.
> +it.  The recommended placement is in the first 12KiB of RAM.
> 
>  4b. Setup the device tree
>  -------------------------
> @@ -120,7 +120,7 @@ tagged list.
>  The boot loader must pass at a minimum the size and location of the
>  system memory, and the root filesystem location.  The dtb must be
>  placed in a region of memory where the kernel decompressor will not
> -overwrite it.  The recommended placement is in the first 16KiB of RAM
> +overwrite it.  The recommended placement is in the first 12KiB of RAM
>  with the caveat that it may not be located at physical address 0  
> since
>  the kernel interprets a value of 0 in r2 to mean neither a tagged  
> list
>  nor a dtb were passed.
> @@ -137,8 +137,9 @@ then it is legal for the boot loader to call the  
> zImage in flash
>  directly.
> 
>  The zImage may also be placed in system RAM (at any location) and
> -called there.  Note that the kernel uses 16K of RAM below the image
> -to store page tables.  The recommended placement is 32KiB into RAM.
> +called there.  Note that the kernel may use up to 20KiB of RAM below
> +the image to store page tables.  The recommended placement is 32KiB
> +into RAM.

Now that we have three memory entires, possibly some sort of memory  
layout would be in order?

    0k-12k   boot data (tagged list or device tree)
   12k-32k   page tables
   32k-xxx   kernel image

Perhaps at the end of section 4's introduction? It's not quite obvious  
from the document...

Rob

From jason at lakedaemon.net  Sat May 25 21:19:51 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 25 May 2013 21:19:51 -0400
Subject: [PATCH 0/4] Power off drivers for QNAP and LSXL.
In-Reply-To: <20130123125328.GH1758@titan.lakedaemon.net>
References: <1356697512-3950-1-git-send-email-andrew@lunn.ch>
 <20130123125328.GH1758@titan.lakedaemon.net>
Message-ID: <20130526011951.GB31290@titan.lakedaemon.net>

On Wed, Jan 23, 2013 at 07:53:28AM -0500, Jason Cooper wrote:
> On Fri, Dec 28, 2012 at 01:25:08PM +0100, Andrew Lunn wrote:
> > This patchset contains two power off driver, moving existing code
> > out of mach-kirkwood into drivers/power/reset.
> > 
> > QNAP NAS boards have a microcontroller connected to a UART. Sending
> > the command to it turns the power off. There are Orion5x QNAP boards
> > which can later use this driver, once they are converted to DT.
> > 
> > Kirkwood Buffalo Linkstation LSXL devices power off by restarting and
> > letting the boot loader idle until the user hits a switch. There are
> > again Orion5x devices which could use this driver in the future, once
> > they are converted to DT. It also looks like some PXA devices could
> > use it.
> > 
> > Patches #1 and #3 are the drivers, and #2 and #4 make use of the
> > driver, removing C code and adding DT nodes.
> > 
> > The QNAP driver has been tested on a QNAP TS119+. The LSXL driver is
> > currently untested.
> > 
> > git://github.com/lunn/linux.git v3.8-rc1-qnap-poweroff
> > 
> > Andrew Lunn (4):
> >   Power: Reset: Driver to turn QNAP board power off.
> >   ARM: Kirkwood: Make use of the QNAP Power off driver.
> >   Power: Reset: Power off by restarting
> >   ARM: Kirkwood: Convert LSXL to restart-poweroff driver.
> > 
> >  .../bindings/power_supply/qnap-poweroff.txt        |   14 +++
> >  .../bindings/power_supply/restart-poweroff.txt     |    9 ++
> >  arch/arm/boot/dts/kirkwood-lsxl.dtsi               |    4 +
> >  arch/arm/boot/dts/kirkwood-ts219.dtsi              |    5 +
> >  arch/arm/mach-kirkwood/Kconfig                     |    2 +
> >  arch/arm/mach-kirkwood/board-lsxl.c                |   16 ---
> >  arch/arm/mach-kirkwood/board-ts219.c               |    3 -
> >  drivers/power/reset/Kconfig                        |   17 +++
> >  drivers/power/reset/Makefile                       |    2 +
> >  drivers/power/reset/qnap-poweroff.c                |  124 ++++++++++++++++++++
> >  drivers/power/reset/restart-poweroff.c             |   67 +++++++++++
> >  11 files changed, 244 insertions(+), 19 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt
> >  create mode 100644 Documentation/devicetree/bindings/power_supply/restart-poweroff.txt
> >  create mode 100644 drivers/power/reset/qnap-poweroff.c
> >  create mode 100644 drivers/power/reset/restart-poweroff.c
> 
> patches 2 and 4 applied to mvebu/dt with a dependency on:
> 
>   git://git.infradead.org/battery-2.6.git master
> 
> up to:
> 
>   ffd8f9a power/reset: Add a new driver implementing 'power off by restarting'
> 
> in order to pull in patches 1 and 3:
> 
>   ffd8f9a power/reset: Add a new driver implementing 'power off by restarting'
>   e8fc721 power/reset: Add a new driver to turn QNAP board power off

Yeah.... So thanks to Andrew for bringing this to my attention.
Somewhere along the line, I must've dropped patches 2 and 4.

Thankfully, patches 1 and 3 made it in, so I've just applied 2 and 4 to
mvebu/boards.

thx, and sorry for the delay.

Jason.


From davem at davemloft.net  Sun May 26 00:04:41 2013
From: davem at davemloft.net (David Miller)
Date: Sat, 25 May 2013 21:04:41 -0700 (PDT)
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address
 workaround on DT ethernet
In-Reply-To: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130525.210441.818472895703230779.davem@davemloft.net>

From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date: Wed, 22 May 2013 22:04:01 +0200

> +			memcpy((void *)p->value, reg, 6);

This cast is completely unnecessary, non-void to void pointer casts
are automatic.

If it is necessary, because p->value is const, then you are trying
to change something behind the OF layer's back and need to use
the appropriate interface to change the property contents.


From gang.chen at asianux.com  Sun May 26 00:43:22 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Sun, 26 May 2013 12:43:22 +0800
Subject: [PATCH v2] arch: configuration issue, random return value when disable
 'CONFIG_BUG'
In-Reply-To: <519EE9D6.9010707@asianux.com>
References: <519DCBEF.3090208@asianux.com> <201305231259.43750.arnd@arndb.de>
 <20130523112401.GO18614@n2100.arm.linux.org.uk>
 <201305231409.02359.arnd@arndb.de>
 <20130523125033.GP18614@n2100.arm.linux.org.uk>
 <CAMuHMdUzcBuDupe4Fa6XieziGPMpPKC_k8X8gUUmDvLJ+Fe=Hg@mail.gmail.com>
 <519ECCCF.8090909@asianux.com> <519EE9D6.9010707@asianux.com>
Message-ID: <51A192EA.4010607@asianux.com>


If user disable 'CONFIG_BUG' in menuconfig, many areas not only will
report compiling warnings, but also may return a random value from the
function when BUG().

In fact, most of architectures need always let 'CONFIG_BUG' enabled, so
'#ifdef CONFIG_BUG' is already not 'generic' enough in "include/asm-
generic/".

Also kernel has already provided the 'generic' implementation in
"include/asm-generic" when 'CONFIG_BUG' enabled. Even if we disable
'CONFIG_BUG', we also shall have to implement the BUG() in "include/asm-
generic", just like when 'CONFIG_BUG' enabled (at least, it is not the
minimal size implementation).

So need remove 'CONFIG_BUG', and let it always enabled everywhere, then
fix this issue.

The architectures which need their own architecture specific features
(e.g. minimal size implementation), can customize their own BUG() and
__WARN_TAINT() to give a better fix (e.g. use one inline asm code, then
followed by 'unreachable' function, or another more better fix ways).


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm/Kconfig          |    1 -
 arch/avr32/Kconfig        |    1 -
 arch/blackfin/Kconfig     |    1 -
 arch/h8300/Kconfig        |    1 -
 arch/hexagon/Kconfig      |    1 -
 arch/parisc/Kconfig       |    2 --
 arch/powerpc/Kconfig      |    1 -
 arch/s390/Kconfig         |    2 +-
 arch/sh/Kconfig           |    2 +-
 arch/um/Kconfig.common    |    1 -
 arch/x86/Kconfig          |    1 -
 include/asm-generic/bug.h |   29 -----------------------------
 init/Kconfig              |   10 ----------
 lib/Kconfig.debug         |    2 +-
 14 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a7fc5ea..ea4a146 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -265,7 +265,6 @@ config PHYS_OFFSET
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 source "init/Kconfig"
 
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index bdc3558..7c9005a 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -55,7 +55,6 @@ config GENERIC_CALIBRATE_DELAY
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 source "init/Kconfig"
 
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index a117652..637dc42 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -47,7 +47,6 @@ config GENERIC_CSUM
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 config ZONE_DMA
 	def_bool y
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 303e4f9..88848da 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -56,7 +56,6 @@ config GENERIC_CALIBRATE_DELAY
 
 config GENERIC_BUG
         bool
-        depends on BUG
 
 config TIME_LOW_RES
 	bool
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 33a9792..f50cc8f 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -84,7 +84,6 @@ config STACKTRACE_SUPPORT
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 
 menu "Machine selection"
 
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 6507dab..5de1f8c 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -10,7 +10,6 @@ config PARISC
 	select RTC_CLASS
 	select RTC_DRV_GENERIC
 	select INIT_ALL_POSSIBLE
-	select BUG
 	select HAVE_PERF_EVENTS
 	select GENERIC_ATOMIC64 if !64BIT
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -62,7 +61,6 @@ config ARCH_HAS_ILOG2_U64
 config GENERIC_BUG
 	bool
 	default y
-	depends on BUG
 
 config GENERIC_HWEIGHT
 	bool
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c33e3ad..34f4ca9 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -187,7 +187,6 @@ config AUDIT_ARCH
 config GENERIC_BUG
 	bool
 	default y
-	depends on BUG
 
 config SYS_SUPPORTS_APM_EMULATION
 	default y if PMAC_APM_EMU
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index da183c5..5d7b3db 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -29,7 +29,7 @@ config GENERIC_HWEIGHT
 	def_bool y
 
 config GENERIC_BUG
-	def_bool y if BUG
+	def_bool y
 
 config GENERIC_BUG_RELATIVE_POINTERS
 	def_bool y
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8c868cf..d555e7f 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -84,7 +84,7 @@ config RWSEM_XCHGADD_ALGORITHM
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG && SUPERH32
+	depends on SUPERH32
 
 config GENERIC_CSUM
 	def_bool y
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index bceee66..7aae42a 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -53,7 +53,6 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_BUG
 	bool
 	default y
-	depends on BUG
 
 config HZ
 	int
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 723e42e..a36e1b4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -166,7 +166,6 @@ config GENERIC_ISA_DMA
 
 config GENERIC_BUG
 	def_bool y
-	depends on BUG
 	select GENERIC_BUG_RELATIVE_POINTERS if X86_64
 
 config GENERIC_BUG_RELATIVE_POINTERS
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..5d50903 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -12,8 +12,6 @@
 #ifndef __ASSEMBLY__
 #include <linux/kernel.h>
 
-#ifdef CONFIG_BUG
-
 #ifdef CONFIG_GENERIC_BUG
 struct bug_entry {
 #ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
@@ -106,33 +104,6 @@ extern void warn_slowpath_null(const char *file, const int line);
 	unlikely(__ret_warn_on);					\
 })
 
-#else /* !CONFIG_BUG */
-#ifndef HAVE_ARCH_BUG
-#define BUG() do {} while(0)
-#endif
-
-#ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
-#endif
-
-#ifndef HAVE_ARCH_WARN_ON
-#define WARN_ON(condition) ({						\
-	int __ret_warn_on = !!(condition);				\
-	unlikely(__ret_warn_on);					\
-})
-#endif
-
-#ifndef WARN
-#define WARN(condition, format...) ({					\
-	int __ret_warn_on = !!(condition);				\
-	unlikely(__ret_warn_on);					\
-})
-#endif
-
-#define WARN_TAINT(condition, taint, format...) WARN_ON(condition)
-
-#endif
-
 #define WARN_ON_ONCE(condition)	({				\
 	static bool __section(.data.unlikely) __warned;		\
 	int __ret_warn_once = !!(condition);			\
diff --git a/init/Kconfig b/init/Kconfig
index 7fb26a6..bc1dd49 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1360,16 +1360,6 @@ config PRINTK
 	  very difficult to diagnose system problems, saying N here is
 	  strongly discouraged.
 
-config BUG
-	bool "BUG() support" if EXPERT
-	default y
-	help
-          Disabling this option eliminates support for BUG and WARN, reducing
-          the size of your kernel image and potentially quietly ignoring
-          numerous fatal conditions. You should only consider disabling this
-          option for embedded systems with no facilities for reporting errors.
-          Just say Y.
-
 config ELF_CORE
 	depends on COREDUMP
 	default y
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 566cf2b..54b3251 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -700,7 +700,7 @@ config HAVE_DEBUG_BUGVERBOSE
 
 config DEBUG_BUGVERBOSE
 	bool "Verbose BUG() reporting (adds 70K)" if DEBUG_KERNEL && EXPERT
-	depends on BUG && (GENERIC_BUG || HAVE_DEBUG_BUGVERBOSE)
+	depends on GENERIC_BUG || HAVE_DEBUG_BUGVERBOSE
 	default y
 	help
 	  Say Y here to make BUG() panics output the file name and line number
-- 
1.7.7.6



From dirk.behme at gmail.com  Sun May 26 01:38:37 2013
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sun, 26 May 2013 07:38:37 +0200
Subject: [PATCH v7] arm: use built-in byte swap function
In-Reply-To: <20130523114654.1f273241725205c6703b2226@freescale.com>
References: <20130129181046.GC25415@pd.tnic>
 <alpine.LFD.2.02.1302082102380.6300@xanadu.home>
 <20130219203115.114eab79e8d2099c6306d921@freescale.com>
 <alpine.LFD.2.03.1302192151280.6419@syhkavp.arg>
 <1361356696.13482.269.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200835380.6419@syhkavp.arg>
 <1361367842.13482.279.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200905300.6419@syhkavp.arg>
 <1361372008.13482.280.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302201040460.6419@syhkavp.arg>
 <20130220214943.9b28a5b208da9f081387c55e@freescale.com>
 <alpine.LFD.2.03.1302202327370.6419@syhkavp.arg>
 <20130221005221.15279b1372501af12c1e4f32@freescale.com>
 <alpine.LFD.2.03.1302211134160.6419@syhkavp.arg>
 <20130221203327.6558f89277468f7ffffa6506@freescale.com>
 <alpine.LFD.2.03.1302212219100.6419@syhkavp.arg>
 <20130222194032.f7b44aefa5e2723d16767a1b@freescale.com>
 <1361661654.18110.102.camel@shinybook.infradead.org>
 <20130523114654.1f273241725205c6703b2226@freescale.com>
Message-ID: <51A19FDD.9040403@gmail.com>

Am 23.05.2013 18:46, schrieb Kim Phillips:
> Enable the compiler intrinsic for byte swapping on arch ARM.  This
> allows the compiler to detect and be able to optimize out byte
> swappings, and has a very modest benefit on vmlinux size (Linaro gcc
> 4.8):

I'm no GCC tool chain expert, so I just have an understanding 
question: Could anyone kindly give a brief explanation (*) of what the 
advantage of this is on ARM?

http://comments.gmane.org/gmane.linux.kernel.cross-arch/16016

mentions "lwbrx/stwbrx on PowerPC, movbe on Atom". But for ARM?

I haven't understood yet why the __arch_swabXX() in 
arch/arm/include/asm/swab.h [1] aren't sufficient? How can this be 
done better? E.g. does anybody have a disassembly without/with this 
change to illustrate that?

Many thanks and best regards

Dirk

(*) or in case this already done provide a link. I couldn't find it in 
the discussion of this patch.

[1]

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/include/asm/swab.h




From gang.chen at asianux.com  Sun May 26 02:54:34 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Sun, 26 May 2013 14:54:34 +0800
Subject: [PATCH] arch: arm: mach-msm: using strlcpy instead of strncpy
Message-ID: <51A1B1AA.9090605@asianux.com>


For NULL terminated string, need always be sure of ended by zero.

Or the next 'ptr' in 'for' looping may cause issue.


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm/mach-msm/clock-debug.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index 4886404..b0fbdf1 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -104,7 +104,7 @@ int __init clock_debug_add(struct clk *clock)
 	if (!debugfs_base)
 		return -ENOMEM;
 
-	strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
+	strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp));
 	for (ptr = temp; *ptr; ptr++)
 		*ptr = tolower(*ptr);
 
-- 
1.7.7.6


From andrew at lunn.ch  Sun May 26 04:36:14 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 26 May 2013 10:36:14 +0200
Subject: Kirkwood CPU Freq driver
In-Reply-To: <51A12DD4.9010907@baker-net.org.uk>
References: <51A12DD4.9010907@baker-net.org.uk>
Message-ID: <20130526083614.GB26249@lunn.ch>

On Sat, May 25, 2013 at 10:32:04PM +0100, Adam Baker wrote:
> Hi,
> 
> I've been trying to test Andrew Lunn's work creating a CPU Idle
> driver for Kirkwood.

Hi Adam

Thanks for testing this. I must admit, i never tested it once the
first rc came out. I clearly should of, because its broken. It was a
three part patch series, and only part 1/3 made it in. Hence the
issues you are seeing.

Jason, please can you pick up:

https://patchwork.kernel.org/patch/2051401/
https://patchwork.kernel.org/patch/2080931/

	Andrew


From plagnioj at jcrosoft.com  Sun May 26 04:34:30 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 10:34:30 +0200
Subject: [GIT PULL] at91: USBA DT support for 3.11
Message-ID: <20130526083430.GP24476@game.jcrosoft.org>

Arnd, Olof

Second AT91 pull-request for 3.11

This add the DT support the USBA present in the most recents AT91 SoC
As agree with Arnd and Filipe we send the drivers via arm-soc

this is base on previous pull request at91-3.11-cleanup1+resolved

Best Regards,
J.

The following changes since commit 7a76f53b01685eda605fa15ccaa1ca90a7aa2c33:

  ARM: at91: udpate defconfigs (2013-05-24 18:02:06 +0200)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-3.11-dt-usba

for you to fetch changes up to e6a2ba4b6fc828917c66cd7ffafdfb7a889d7bee:

  ARM: at91: sam9m10g45ek add udc DT support (2013-05-26 16:35:55 +0800)

----------------------------------------------------------------
ARM: at91: dt: add USBA support

This patch serie finish to add the usb device support to dt for at91
with the usba support present on the last at91 generation since sam9g45

update driver & dt

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (7):
      USB: gadget: atmel_usba: move global struct usba_ep usba_ep to struct usba_udc
      USB: gadget: atmel_usba: allow multi instance
      USB: gadget: atmel_usba: add DT support
      ARM: at91: sam9x5 add udc DT support
      ARM: at91: sam9x5ek add udc DT support
      ARM: at91: sam9g45 add udc DT support
      ARM: at91: sam9m10g45ek add udc DT support

 Documentation/devicetree/bindings/usb/atmel-usb.txt |   82 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi                  |   62 +++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts              |    5 +++++
 arch/arm/boot/dts/at91sam9x5.dtsi                   |   62 +++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi                 |    5 +++++
 arch/arm/mach-at91/at91sam9g45.c                    |    2 ++
 arch/arm/mach-at91/at91sam9x5.c                     |    2 ++
 drivers/usb/gadget/Kconfig                          |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                 |  264 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----------------------------------------------------------------
 drivers/usb/gadget/atmel_usba_udc.h                 |    2 ++
 10 files changed, 407 insertions(+), 81 deletions(-)


From david.woodhouse at intel.com  Sun May 26 05:30:00 2013
From: david.woodhouse at intel.com (Woodhouse, David)
Date: Sun, 26 May 2013 09:30:00 +0000
Subject: [PATCH v7] arm: use built-in byte swap function
In-Reply-To: <51A19FDD.9040403@gmail.com>
References: <20130129181046.GC25415@pd.tnic>
 <alpine.LFD.2.02.1302082102380.6300@xanadu.home>
 <20130219203115.114eab79e8d2099c6306d921@freescale.com>
 <alpine.LFD.2.03.1302192151280.6419@syhkavp.arg>
 <1361356696.13482.269.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200835380.6419@syhkavp.arg>
 <1361367842.13482.279.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302200905300.6419@syhkavp.arg>
 <1361372008.13482.280.camel@i7.infradead.org>
 <alpine.LFD.2.03.1302201040460.6419@syhkavp.arg>
 <20130220214943.9b28a5b208da9f081387c55e@freescale.com>
 <alpine.LFD.2.03.1302202327370.6419@syhkavp.arg>
 <20130221005221.15279b1372501af12c1e4f32@freescale.com>
 <alpine.LFD.2.03.1302211134160.6419@syhkavp.arg>
 <20130221203327.6558f89277468f7ffffa6506@freescale.com>
 <alpine.LFD.2.03.1302212219100.6419@syhkavp.arg>
 <20130222194032.f7b44aefa5e2723d16767a1b@freescale.com>
 <1361661654.18110.102.camel@shinybook.infradead.org>
 <20130523114654.1f273241725205c6703b2226@freescale.com>
 <51A19FDD.9040403@gmail.com>
Message-ID: <1369560593.27719.67.camel@shinybook.infradead.org>

On Sun, 2013-05-26 at 07:38 +0200, Dirk Behme wrote:
> Am 23.05.2013 18:46, schrieb Kim Phillips:
> > Enable the compiler intrinsic for byte swapping on arch ARM.  This
> > allows the compiler to detect and be able to optimize out byte
> > swappings, and has a very modest benefit on vmlinux size (Linaro gcc
> > 4.8):
> 
> I'm no GCC tool chain expert, so I just have an understanding 
> question: Could anyone kindly give a brief explanation (*) of what the 
> advantage of this is on ARM?
> 
> http://comments.gmane.org/gmane.linux.kernel.cross-arch/16016
> 
> mentions "lwbrx/stwbrx on PowerPC, movbe on Atom". But for ARM?
> 
> I haven't understood yet why the __arch_swabXX() in 
> arch/arm/include/asm/swab.h [1] aren't sufficient? How can this be 
> done better? E.g. does anybody have a disassembly without/with this 
> change to illustrate that?

The point is just that the compiler gets to *see* what's happening.

See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55177 for a bunch of
examples of things that GCC ought to be able to optimise, even without
the CPU having load-and-swap instructions. Not that it always does;
hence the PR. But there are some that it does currently manage,
evidently.

You'll see this if you follow the link above, but as an example: imagine
a code sequence that goes load, swap, mask, swap, store.

With the swaps done by opaque inline asm, there's nothing the compiler
can do to optimise this. But if it *knows* what's going on, it can
optimise it into a single load, mask of a pre-byte-swapped constant, and
store.

Having said that, I can't actually answer your question ? I don't know
which optimisations the compiler *is* doing to provide the "modest
benefit" that Kim mentions; every class of optimisation I explicitly
checked for was missing. Again, hence the PR. But evidently it does
manage to get *something* right.

-- 
                Sent with Evolution's ActiveSync support.

David Woodhouse                            Open Source Technology Centre
David.Woodhouse at intel.com                              Intel Corporation



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From maxime.ripard at free-electrons.com  Sun May 26 05:35:03 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 11:35:03 +0200
Subject: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
In-Reply-To: <51A1103F.6000702@schinagl.nl>
References: <1368797744-13737-1-git-send-email-oliver+list@schinagl.nl>
 <1368797744-13737-2-git-send-email-oliver+list@schinagl.nl>
 <51969EA9.1060602@free-electrons.com>
 <5197B82F.8010809@schinagl.nl> <519FE0AE.2010102@schinagl.nl>
 <20130525122208.GD17847@lukather> <51A1103F.6000702@schinagl.nl>
Message-ID: <20130526093503.GH17847@lukather>

On Sat, May 25, 2013 at 09:25:51PM +0200, Oliver Schinagl wrote:
> On 05/25/13 14:22, Maxime Ripard wrote:
> >What about:
> >
> >val = ioread32be(base + (key / 4));
> >val >>= (key % 4) * 8;
> >return val & 0xff;
> >
> >No lookup table, no weird swich statement, and you get the endianness
> >conversion only when you need it.
> Ok I think I like the Endianess, ioread32be does the right thing
> then? I'll read up on that.
> As for key / 4; how will that work without the lut?
> 
> Lets take byte 14 (out of the available 16). Byte 14 (0x0e) is
> located in SID_KEY3, so base + 0x0c. We need to write a whole 32bit
> word to keep with alignment, the registers go wakko if you do
> unaligned reads. So we need to read the entire 32 bits, then find
> our byte.
> 
> key / 4 for 14 yields 0x03. So we have base + 0x03, which is not
> what we want. We want base + 0x0c, which is either ((key >> 2) <<
> 2)) Or, ((key / 4) * 4)) which to me, are both equally confusing.

The statement you make that 3 isn't the index you want depends on your
pointer type so it might be what you want, or might not.

If it's still not what you want, you can always use round_down(key, 4).

> So we either use the look up table, which is a little cleaner and is a
> bit more future proof if either a) there's more 'eeprom like'
> storage which can be combined herein or b) 'a' next version has
> non-continuing regions. Granted neither is something to worry about
> right now.

I don't see how it's cleaner (you have three indirections to get
the value that is actually used) or future proof (you have to extend
this lookup table every time you have a slightly larger size).

So I'm sorry but this lookup table holding only the index times 4 is
a non-sense, could we please stop arguing about this?

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From mpa at pengutronix.de  Sun May 26 05:53:21 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Sun, 26 May 2013 11:53:21 +0200
Subject: [PATCH v7 2/2] DMA: imx-dma: imxdma->dev used uninitialized
In-Reply-To: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
References: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369562001-11494-3-git-send-email-mpa@pengutronix.de>

imxdma->dev is used for dev_warn before it was set.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
Reviewed-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/dma/imx-dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 34c54cf..ff2aab9 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -1067,6 +1067,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	if (!imxdma)
 		return -ENOMEM;
 
+	imxdma->dev = &pdev->dev;
 	imxdma->devtype = pdev->id_entry->driver_data;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1171,7 +1172,6 @@ static int __init imxdma_probe(struct platform_device *pdev)
 			      &imxdma->dma_device.channels);
 	}
 
-	imxdma->dev = &pdev->dev;
 	imxdma->dma_device.dev = &pdev->dev;
 
 	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
-- 
1.8.2.1



From mpa at pengutronix.de  Sun May 26 05:53:20 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Sun, 26 May 2013 11:53:20 +0200
Subject: [PATCH v7 1/2] dma: imx-dma: Add oftree support
In-Reply-To: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
References: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369562001-11494-2-git-send-email-mpa@pengutronix.de>

Adding devicetree support for imx-dma driver. Use driver name for
function 'imx_dma_is_general_purpose' because the devicename for
devicetree initialized devices is different.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Shawn Guo <shawn.guo at linaro.org>
---

Notes:
    Changes in V6:
    - Style fixes in imxdma_xlate function, moved request assignment and removed
      unnecessary cast.
    
    Changes in V5:
    - Style fix
    - Documentation reference
    
    Changes in V4:
    - Directly use "imxdma_channel" as proposed by Arnd. This removes the
    allocation of imx_dma_data.
    - Simplify function imx_dma_is_general_purpose using driver names.
    
    Changes in V3:
    - Create a imxdma translate function to pass the device object into the
    filter function.
    
    Changes in V2:
    - Change the driver to use generic DMA DT bindings.
    - Add a imx-dma filter function that sets the dma request line in
      private data.

 .../devicetree/bindings/dma/fsl-imx-dma.txt        | 48 ++++++++++++++
 drivers/dma/imx-dma.c                              | 75 ++++++++++++++++++++++
 include/linux/platform_data/dma-imx.h              |  6 +-
 3 files changed, 125 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-imx-dma.txt

diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
new file mode 100644
index 0000000..2717ecb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
@@ -0,0 +1,48 @@
+* Freescale Direct Memory Access (DMA) Controller for i.MX
+
+This document will only describe differences to the generic DMA Controller and
+DMA request bindings as described in dma/dma.txt .
+
+* DMA controller
+
+Required properties:
+- compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
+- reg : Should contain DMA registers location and length
+- interrupts : First item should be DMA interrupt, second one is optional and
+    should contain DMA Error interrupt
+- #dma-cells : Has to be 1. imx-dma does not support anything else.
+
+Optional properties:
+- #dma-channels : Number of DMA channels supported. Should be 16.
+- #dma-requests : Number of DMA requests supported.
+
+Example:
+
+	dma: dma at 10001000 {
+		compatible = "fsl,imx27-dma";
+		reg = <0x10001000 0x1000>;
+		interrupts = <32 33>;
+		#dma-cells = <1>;
+		#dma-channels = <16>;
+	};
+
+
+* DMA client
+
+Clients have to specify the DMA requests with phandles in a list.
+
+Required properties:
+- dmas: List of one or more DMA request specifiers. One DMA request specifier
+    consists of a phandle to the DMA controller followed by the integer
+    specifiying the request line.
+- dma-names: List of string identifiers for the DMA requests. For the correct
+    names, have a look at the specific client driver.
+
+Example:
+
+	sdhci1: sdhci at 10013000 {
+		...
+		dmas = <&dma 7>;
+		dma-names = "rx-tx";
+		...
+	};
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index f285833..34c54cf 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -27,6 +27,8 @@
 #include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
 
 #include <asm/irq.h>
 #include <linux/platform_data/dma-imx.h>
@@ -186,6 +188,11 @@ struct imxdma_engine {
 	enum imx_dma_type		devtype;
 };
 
+struct imxdma_filter_data {
+	struct imxdma_engine	*imxdma;
+	int			 request;
+};
+
 static struct platform_device_id imx_dma_devtype[] = {
 	{
 		.name = "imx1-dma",
@@ -202,6 +209,22 @@ static struct platform_device_id imx_dma_devtype[] = {
 };
 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
 
+static const struct of_device_id imx_dma_of_dev_id[] = {
+	{
+		.compatible = "fsl,imx1-dma",
+		.data = &imx_dma_devtype[IMX1_DMA],
+	}, {
+		.compatible = "fsl,imx21-dma",
+		.data = &imx_dma_devtype[IMX21_DMA],
+	}, {
+		.compatible = "fsl,imx27-dma",
+		.data = &imx_dma_devtype[IMX27_DMA],
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
+
 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
 {
 	return imxdma->devtype == IMX1_DMA;
@@ -996,13 +1019,50 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 	spin_unlock_irqrestore(&imxdma->lock, flags);
 }
 
+static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
+{
+	struct imxdma_filter_data *fdata = param;
+	struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
+
+	if (chan->device->dev != fdata->imxdma->dev)
+		return false;
+
+	imxdma_chan->dma_request = fdata->request;
+	chan->private = NULL;
+
+	return true;
+}
+
+static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
+						struct of_dma *ofdma)
+{
+	int count = dma_spec->args_count;
+	struct imxdma_engine *imxdma = ofdma->of_dma_data;
+	struct imxdma_filter_data fdata = {
+		.imxdma = imxdma,
+	};
+
+	if (count != 1)
+		return NULL;
+
+	fdata.request = dma_spec->args[0];
+
+	return dma_request_channel(imxdma->dma_device.cap_mask,
+					imxdma_filter_fn, &fdata);
+}
+
 static int __init imxdma_probe(struct platform_device *pdev)
 	{
 	struct imxdma_engine *imxdma;
 	struct resource *res;
+	const struct of_device_id *of_id;
 	int ret, i;
 	int irq, irq_err;
 
+	of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
+	if (of_id)
+		pdev->id_entry = of_id->data;
+
 	imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
 	if (!imxdma)
 		return -ENOMEM;
@@ -1136,8 +1196,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		goto err;
 	}
 
+	if (pdev->dev.of_node) {
+		ret = of_dma_controller_register(pdev->dev.of_node,
+				imxdma_xlate, imxdma);
+		if (ret) {
+			dev_err(&pdev->dev, "unable to register of_dma_controller\n");
+			goto err_of_dma_controller;
+		}
+	}
+
 	return 0;
 
+err_of_dma_controller:
+	dma_async_device_unregister(&imxdma->dma_device);
 err:
 	clk_disable_unprepare(imxdma->dma_ipg);
 	clk_disable_unprepare(imxdma->dma_ahb);
@@ -1150,6 +1221,9 @@ static int imxdma_remove(struct platform_device *pdev)
 
         dma_async_device_unregister(&imxdma->dma_device);
 
+	if (pdev->dev.of_node)
+		of_dma_controller_free(pdev->dev.of_node);
+
 	clk_disable_unprepare(imxdma->dma_ipg);
 	clk_disable_unprepare(imxdma->dma_ahb);
 
@@ -1159,6 +1233,7 @@ static int imxdma_remove(struct platform_device *pdev)
 static struct platform_driver imxdma_driver = {
 	.driver		= {
 		.name	= "imx-dma",
+		.of_match_table = imx_dma_of_dev_id,
 	},
 	.id_table	= imx_dma_devtype,
 	.remove		= imxdma_remove,
diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h
index f6d30cc..beac6b8 100644
--- a/include/linux/platform_data/dma-imx.h
+++ b/include/linux/platform_data/dma-imx.h
@@ -60,10 +60,8 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
 
 static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
 {
-	return strstr(dev_name(chan->device->dev), "sdma") ||
-		!strcmp(dev_name(chan->device->dev), "imx1-dma") ||
-		!strcmp(dev_name(chan->device->dev), "imx21-dma") ||
-		!strcmp(dev_name(chan->device->dev), "imx27-dma");
+	return !strcmp(chan->device->dev->driver->name, "imx-sdma") ||
+		!strcmp(chan->device->dev->driver->name, "imx-dma");
 }
 
 #endif
-- 
1.8.2.1



From mpa at pengutronix.de  Sun May 26 05:53:19 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Sun, 26 May 2013 11:53:19 +0200
Subject: [PATCH v7 0/2] dma: imx-dma: OFTree support
Message-ID: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>

Hi,

this series adds support for the generic DMA DT bindings for imx-dma.

Regards,

Markus


Changes in v7:
 - rebased onto v3.10-rc2

Markus Pargmann (2):
      dma: imx-dma: Add oftree support
      DMA: imx-dma: imxdma->dev used uninitialized

 .../devicetree/bindings/dma/fsl-imx-dma.txt        | 48 ++++++++++++++
 drivers/dma/imx-dma.c                              | 77 +++++++++++++++++++++-
 include/linux/platform_data/dma-imx.h              |  6 +-
 3 files changed, 126 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-imx-dma.txt



From maxime.ripard at free-electrons.com  Sun May 26 06:20:39 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:39 +0200
Subject: [PATCHv2 3/6] ARM: sun4i: dt: Add i2c muxing options
In-Reply-To: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369563642-4390-4-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A10 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 311dcd4..63f6716 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Sun May 26 06:20:40 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:40 +0200
Subject: [PATCHv2 4/6] ARM: sun5i: dt: Add i2c muxing options
In-Reply-To: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369563642-4390-5-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A13 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 16df784..450b410 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -182,6 +182,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB15", "PB16";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB17", "PB18";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Sun May 26 06:20:36 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:36 +0200
Subject: [PATCHv2 0/6] Add I2C support for Allwinner SoCs
Message-ID: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

This patchset adds support for the I2C controller found on most of the
Allwinner SoCs, especially the already supported A10 and A13, and the
yet to come A31.

It has been tested on a A13-Olinuxino.

Thanks,
Maxime

Changes from v1:
  * Added comments to the switch statements to clarify when the fall through to
    the next case is made on purpose
  * Use devm_ioremap_resource instead of of_iomap
  * Moved the reset after enabling the clocks
  * Added Emilio Lopez' patch to add the available i2c controllers to the
    cubieboard

Emilio L?pez (1):
  ARM: sun4i: cubieboard: Enable the i2c controllers

Maxime Ripard (5):
  i2c: sunxi: Add Allwinner A1X i2c driver
  ARM: sunxi: dt: Add i2c controller nodes to the DTSI
  ARM: sun4i: dt: Add i2c muxing options
  ARM: sun5i: dt: Add i2c muxing options
  ARM: sun5i: olinuxino: Enable the i2c controllers

 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  12 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 455 +++++++++++++++++++++
 8 files changed, 611 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Sun May 26 06:20:38 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:38 +0200
Subject: [PATCHv2 2/6] ARM: sunxi: dt: Add i2c controller nodes to the DTSI
In-Reply-To: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369563642-4390-3-git-send-email-maxime.ripard@free-electrons.com>

The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..311dcd4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -292,5 +292,32 @@
 			clocks = <&apb1_gates 23>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..16df784 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -215,5 +215,32 @@
 			clocks = <&apb1_gates 19>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Sun May 26 06:20:37 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:37 +0200
Subject: [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>

This patch implements a basic driver for the I2C host driver found on
the Allwinner A10, A13 and A31 SoCs.

Notable missing feature is 10-bit addressing.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 455 +++++++++++++++++++++
 4 files changed, 485 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
new file mode 100644
index 0000000..40c16d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-i2c".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c at 01c2ac00 {
+	compatible = "allwinner,sun4i-i2c";
+	reg = <0x01c2ac00 0x400>;
+	interrupts = <7>;
+	clocks = <&apb1_gates 0>;
+	clock-frequency = <100000>;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 631736e..1df8ba1 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -706,6 +706,16 @@ config I2C_STU300
 	  This driver can also be built as a module. If so, the module
 	  will be called i2c-stu300.
 
+config I2C_SUNXI
+	tristate "Allwinner A1X I2C controller"
+	depends on ARCH_SUNXI
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controller embedded in Allwinner A1X SoCs.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called i2c-sunxi.
+
 config I2C_TEGRA
 	tristate "NVIDIA Tegra internal I2C controller"
 	depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..7225818 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
 obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
diff --git a/drivers/i2c/busses/i2c-sunxi.c b/drivers/i2c/busses/i2c-sunxi.c
new file mode 100644
index 0000000..5d93f26
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi.c
@@ -0,0 +1,455 @@
+/*
+ * Allwinner A1X SoCs i2c controller driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)
+
+struct sunxi_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct clk		*clk;
+	struct device		*dev;
+	struct completion	completion;
+	unsigned int		irq;
+	void __iomem		*membase;
+
+	struct i2c_msg		*msg_cur;
+	u8			*msg_buf;
+	size_t			msg_buf_remaining;
+	unsigned int		msg_err;
+};
+
+static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8 value)
+{
+	writel(value, i2c_dev->membase + reg);
+}
+
+static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
+{
+	return readl(i2c_dev->membase + reg);
+}
+
+/*
+ * This is where all the magic happens. The I2C controller works as a
+ * state machine, each state being a step in the i2c protocol, with
+ * the controller sending an interrupt at each state transition.
+ *
+ * The state we're in is stored in a register, which leads to a pretty
+ * huge switch statement, all of this in the interrupt handler...
+ */
+static irqreturn_t sunxi_i2c_handler(int irq, void *data)
+{
+	struct sunxi_i2c_dev *i2c_dev = (struct sunxi_i2c_dev *)data;
+	u32 status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	u32 addr, val;
+
+	if (!(status & SUNXI_I2C_CNTR_INT_FLAG))
+		return IRQ_NONE;
+
+	/* Read the current state we're in */
+	status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_STA_REG);
+
+	switch (status & 0xff) {
+	/* Start condition has been transmitted */
+	case SUNXI_I2C_STA_START:
+	/* A repeated start condition has been transmitted */
+	case SUNXI_I2C_STA_START_REPEAT:
+		addr = SUNXI_I2C_ADDR_ADDR(i2c_dev->msg_cur->addr);
+
+		if (i2c_dev->msg_cur->flags & I2C_M_RD)
+			addr |= 1;
+
+		sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG, addr);
+		break;
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has not been
+	 * received. It should be treated the same way than when a
+	 * data byte has been sent and no ACK has been received, and
+	 * we fall through to the next case in our switch.
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_NAK:
+	/*
+	 * Data byte has been transmitted, ACK has not been
+	 * received. If we don't care about the NAKs, we just treat
+	 * this case as if an ACK would have been received, and
+	 * we fall through to the next case in our switch.
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has been
+	 * received. In the I2C protocol sequence, we are in exactly
+	 * the same case than when we sent some data bytes and there
+	 * is still some data to be sent, and we fall through to the
+	 * next case in our switch.
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_ACK:
+	/* Data byte has been transmitted, ACK has been received */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_ACK:
+		if (i2c_dev->msg_buf_remaining) {
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG,
+					*i2c_dev->msg_buf);
+			i2c_dev->msg_buf++;
+			i2c_dev->msg_buf_remaining--;
+			break;
+		}
+
+		if (i2c_dev->msg_buf_remaining == 0) {
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		break;
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has not been
+	 * received. If we don't care about the NAKs, we just treat
+	 * this case as if an ACK would have been received, and fall
+	 * through to the next case.
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has been
+	 * received.
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_ACK:
+		/*
+		 * We only need to send the ACK for the all the bytes
+		 * but the last one
+		 */
+		if (i2c_dev->msg_buf_remaining > 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val | SUNXI_I2C_CNTR_ASSERT_ACK);
+		}
+
+		break;
+
+	/*
+	 * Data byte has been received, ACK has not been
+	 * transmitted. If we don't care about the NAK and that some
+	 * data have still to be received, we fall through to the next
+	 * case in our switch.
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_NAK:
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG);
+			*i2c_dev->msg_buf = val & 0xff;
+			i2c_dev->msg_buf_remaining--;
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/* Data byte has been received, ACK has been transmitted */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_ACK:
+		val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG) & 0xff;
+		*i2c_dev->msg_buf = val;
+		i2c_dev->msg_buf++;
+		i2c_dev->msg_buf_remaining--;
+
+		/* If there's only one byte left, disable the ACK */
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val & ~SUNXI_I2C_CNTR_ASSERT_ACK);
+
+		};
+
+		break;
+
+	case SUNXI_I2C_STA_BUS_ERROR:
+		i2c_dev->msg_err = SUNXI_I2C_BUS_ERROR;
+		goto out;
+
+	default:
+		i2c_dev->msg_err = SUNXI_I2C_ERROR;
+		goto out;
+	}
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	return IRQ_HANDLED;
+
+out:
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val | SUNXI_I2C_CNTR_MASTER_STOP);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	complete(&i2c_dev->completion);
+	return IRQ_HANDLED;
+}
+
+static int sunxi_i2c_xfer_msg(struct sunxi_i2c_dev *i2c_dev,
+			      struct i2c_msg *msg)
+{
+	int time_left;
+	u32 val;
+
+	i2c_dev->msg_cur = msg;
+	i2c_dev->msg_buf = msg->buf;
+	i2c_dev->msg_buf_remaining = msg->len;
+	i2c_dev->msg_err = 0;
+	INIT_COMPLETION(i2c_dev->completion);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	val |= SUNXI_I2C_CNTR_MASTER_START;
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG, val);
+
+	time_left = wait_for_completion_timeout(&i2c_dev->completion,
+						i2c_dev->adapter.timeout);
+	if (!time_left) {
+		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	if (likely(i2c_dev->msg_err == SUNXI_I2C_DONE))
+		return 0;
+
+	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
+
+	return -EIO;
+}
+
+static int sunxi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			  int num)
+{
+	struct sunxi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	int i, ret;
+
+	for (i = 0; i < num; i++) {
+		ret = sunxi_i2c_xfer_msg(i2c_dev, &msgs[i]);
+		if (ret)
+			return ret;
+	}
+
+	return i;
+}
+
+static u32 sunxi_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm sunxi_i2c_algo = {
+	.master_xfer	= sunxi_i2c_xfer,
+	.functionality	= sunxi_i2c_func,
+};
+
+static int sunxi_i2c_probe(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev;
+	struct device_node *np;
+	u32 freq, div_m, div_n;
+	struct resource res;
+	int ret;
+
+	np = pdev->dev.of_node;
+	if (!np)
+		return -EINVAL;
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, i2c_dev);
+	i2c_dev->dev = &pdev->dev;
+
+	init_completion(&i2c_dev->completion);
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret) {
+		dev_err(&pdev->dev, "could not get IO memory\n");
+		return ret;
+	}
+
+	i2c_dev->membase = devm_ioremap_resource(&pdev->dev, &res);
+	if (IS_ERR(i2c_dev->membase))
+		return PTR_ERR(i2c_dev->membase);
+
+	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(i2c_dev->clk))
+		return PTR_ERR(i2c_dev->clk);
+
+	clk_prepare_enable(i2c_dev->clk);
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_SRST_REG, SUNXI_I2C_SRST_RESET);
+
+	ret = of_property_read_u32(np, "clock-frequency", &freq);
+	if (ret < 0) {
+		dev_warn(&pdev->dev, "Could not read clock-frequency property\n");
+		freq = 100000;
+	}
+
+	/*
+	 * Set the clock dividers. we don't need to be super smart
+	 * here, the datasheet defines the value of the factors for
+	 * the two supported frequencies, and only the M factor
+	 * changes between 100kHz and 400kHz.
+	 *
+	 * The bus clock is generated from the parent clock with two
+	 * different dividers. It is generated as such:
+	 *     f0 = fclk / (2 ^ DIV_N)
+	 *     fbus = f0 / (10 * (DIV_M + 1))
+	 *
+	 * With DIV_N being on 3 bits, and DIV_M on 4 bits.
+	 * So DIV_N < 8, and DIV_M < 16.
+	 *
+	 * However, we can generate both the supported frequencies
+	 * with f0 = 12MHz, and only change M to get back on our
+	 * feet.
+	 */
+	div_n = ilog2(clk_get_rate(i2c_dev->clk) / 12000000);
+	if (freq == 100000)
+		div_m = 11;
+	else if (freq == 400000)
+		div_m = 2;
+	else {
+		dev_err(&pdev->dev, "Unsupported bus frequency\n");
+		ret = -EINVAL;
+		goto out_clk_dis;
+	}
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CCR_REG,
+			SUNXI_I2C_CCR_DIV_N(div_n) | SUNXI_I2C_CCR_DIV_M(div_m));
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "No IRQ resource\n");
+		ret = -ENODEV;
+		goto out_clk_dis;
+	}
+
+	ret = devm_request_irq(&pdev->dev, i2c_dev->irq, sunxi_i2c_handler,
+			       IRQF_SHARED, dev_name(&pdev->dev), i2c_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not request IRQ\n");
+		goto out_clk_dis;
+	}
+
+	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
+
+	i2c_dev->adapter.owner = THIS_MODULE;
+	strlcpy(i2c_dev->adapter.name, "sunxi I2C adapter",
+		sizeof(i2c_dev->adapter.name));
+	i2c_dev->adapter.algo = &sunxi_i2c_algo;
+	i2c_dev->adapter.dev.parent = &pdev->dev;
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			SUNXI_I2C_CNTR_BUS_ENABLE | SUNXI_I2C_CNTR_INT_ENABLE);
+
+	ret = i2c_add_adapter(&i2c_dev->adapter);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register i2c adapter\n");
+		goto out_clk_dis;
+	}
+
+	return 0;
+
+out_clk_dis:
+	clk_disable_unprepare(i2c_dev->clk);
+	return ret;
+}
+
+
+static int sunxi_i2c_remove(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+	clk_disable_unprepare(i2c_dev->clk);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_i2c_of_match[] = {
+	{ .compatible = "allwinner,sun4i-i2c" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sunxi_i2c_of_match);
+
+static struct platform_driver sunxi_i2c_driver = {
+	.probe		= sunxi_i2c_probe,
+	.remove		= sunxi_i2c_remove,
+	.driver		= {
+		.name	= "i2c-sunxi",
+		.owner	= THIS_MODULE,
+		.of_match_table = sunxi_i2c_of_match,
+	},
+};
+module_platform_driver(sunxi_i2c_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com");
+MODULE_DESCRIPTION("Allwinner A1X I2C bus adapter");
+MODULE_LICENSE("GPL");
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Sun May 26 06:20:41 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:41 +0200
Subject: [PATCHv2 5/6] ARM: sun5i: olinuxino: Enable the i2c controllers
In-Reply-To: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369563642-4390-6-git-send-email-maxime.ripard@free-electrons.com>

The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner
A13. Enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca5506..80497e3 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
 			pinctrl-0 = <&uart1_pins_b>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Sun May 26 06:20:42 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 12:20:42 +0200
Subject: [PATCHv2 6/6] ARM: sun4i: cubieboard: Enable the i2c controllers
In-Reply-To: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369563642-4390-7-git-send-email-maxime.ripard@free-electrons.com>

From: Emilio L?pez <emilio at elopez.com.ar>

The Cubieboard makes use of the first two i2c controllers found on the
Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1
is exposed on the board headers. This patch enables them in the device
tree.

Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..0e22a28 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -41,6 +41,18 @@
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.2.3



From gang.chen at asianux.com  Sun May 26 06:28:03 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Sun, 26 May 2013 18:28:03 +0800
Subject: [PATCH] arch: arm64: kernel: sprintf(), 'str' needs additional 1
 byte for failure processing
Message-ID: <51A1E3B3.4060901@asianux.com>


When failure occurs at the last looping cycle (when 'i == 0'), it will
print "bad PC value" instead of "(%08x) ", which needs additional 1
byte.

If not add 1 byte, the str will not be NUL terminated, and the next
printk() will cause issue.

Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/kernel/traps.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 61d7dd2..c2f68d2 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -100,7 +100,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
 {
 	unsigned long addr = instruction_pointer(regs);
 	mm_segment_t fs;
-	char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
+	char str[sizeof("00000000 ") * 5 + 2 + 1 + 1], *p = str;
 	int i;
 
 	/*
-- 
1.7.7.6


From mpa at pengutronix.de  Sun May 26 06:35:38 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Sun, 26 May 2013 12:35:38 +0200
Subject: [PATCH v6] video: imxfb: Add DT support
Message-ID: <1369564538-21835-1-git-send-email-mpa@pengutronix.de>

Add devicetree support for imx framebuffer driver. It uses the generic
display bindings and helper functions.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Mark Rutland <mark.rutland at arm.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---

Notes:
    Changed in v6:
    - Rebased onto v3.10-rc2
    - Dropped alpha support patch in this series
    
    Changed in v5:
    - Fix compatible property of the example
    - Rename property fsl,bpp to bits-per-pixel
    - Add selects for FB_MODE_HELPERS and VIDEOMODE_HELPERS to Kconfig FB_IMX
    
    Changes in v4:
    - Remove eukrea specific dmacr property.
    - Add optional dmacr property. If not present, the dmacr reset value is not
      changed.
    
    Changes in v3:
    - Fix returncodes of of_read_mode function and print error messages
    - Introduce a lower bound check for bits per pixel
    - Calculate correct bytes per pixel value before using it for the calculation of
    	memory size
    - Change DT property names
    
    Changes in v2:
    - Removed pwmr register property
    - Cleanup of devicetree binding documentation
    - Use default values for pwmr and lscr1

 .../devicetree/bindings/video/fsl,imx-fb.txt       |  51 ++++++
 drivers/video/Kconfig                              |   2 +
 drivers/video/imxfb.c                              | 194 +++++++++++++++++----
 3 files changed, 212 insertions(+), 35 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/video/fsl,imx-fb.txt

diff --git a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
new file mode 100644
index 0000000..46da08d
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
@@ -0,0 +1,51 @@
+Freescale imx21 Framebuffer
+
+This framebuffer driver supports devices imx1, imx21, imx25, and imx27.
+
+Required properties:
+- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : One interrupt of the fb dev
+
+Required nodes:
+- display: Phandle to a display node as described in
+	Documentation/devicetree/bindings/video/display-timing.txt
+	Additional, the display node has to define properties:
+	- bits-per-pixel: Bits per pixel
+	- fsl,pcr: LCDC PCR value
+
+Optional properties:
+- fsl,dmacr: DMA Control Register value. This is optional. By default, the
+	register is not modified as recommended by the datasheet.
+- fsl,lscr1: LCDC Sharp Configuration Register value.
+
+Example:
+
+	imxfb: fb at 10021000 {
+		compatible = "fsl,imx21-fb";
+		interrupts = <61>;
+		reg = <0x10021000 0x1000>;
+		display = <&display0>;
+	};
+
+	...
+
+	display0: display0 {
+		model = "Primeview-PD050VL1";
+		native-mode = <&timing_disp0>;
+		bits-per-pixel = <16>;
+		fsl,pcr = <0xf0c88080>;	/* non-standard but required */
+		display-timings {
+			timing_disp0: 640x480 {
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <112>;
+				hfront-porch = <36>;
+				hsync-len = <32>;
+				vback-porch = <33>;
+				vfront-porch = <33>;
+				vsync-len = <2>;
+				clock-frequency = <25000000>;
+			};
+		};
+	};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d71d60f..588af1d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -367,6 +367,8 @@ config FB_IMX
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
+	select FB_MODE_HELPERS
+	select VIDEOMODE_HELPERS
 
 config FB_CYBER2000
 	tristate "CyberPro 2000/2010/5000 support"
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index 0abf2bf..a2ed71d 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -31,6 +31,12 @@
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/math64.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+#include <video/videomode.h>
 
 #include <linux/platform_data/video-imxfb.h>
 
@@ -112,10 +118,11 @@
 #define LCDISR_EOF	(1<<1)
 #define LCDISR_BOF	(1<<0)
 
+#define IMXFB_LSCR1_DEFAULT 0x00120300
+
 /* Used fb-mode. Can be set on kernel command line, therefore file-static. */
 static const char *fb_mode;
 
-
 /*
  * These are the bitfields for each
  * display depth that we support.
@@ -187,6 +194,19 @@ static struct platform_device_id imxfb_devtype[] = {
 };
 MODULE_DEVICE_TABLE(platform, imxfb_devtype);
 
+static struct of_device_id imxfb_of_dev_id[] = {
+	{
+		.compatible = "fsl,imx1-fb",
+		.data = &imxfb_devtype[IMX1_FB],
+	}, {
+		.compatible = "fsl,imx21-fb",
+		.data = &imxfb_devtype[IMX21_FB],
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imxfb_of_dev_id);
+
 static inline int is_imx1_fb(struct imxfb_info *fbi)
 {
 	return fbi->devtype == IMX1_FB;
@@ -319,6 +339,9 @@ static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
 	struct imx_fb_videomode *m;
 	int i;
 
+	if (!fb_mode)
+		return &fbi->mode[0];
+
 	for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
 		if (!strcmp(m->mode.name, fb_mode))
 			return m;
@@ -474,6 +497,9 @@ static int imxfb_bl_update_status(struct backlight_device *bl)
 	struct imxfb_info *fbi = bl_get_data(bl);
 	int brightness = bl->props.brightness;
 
+	if (!fbi->pwmr)
+		return 0;
+
 	if (bl->props.power != FB_BLANK_UNBLANK)
 		brightness = 0;
 	if (bl->props.fb_blank != FB_BLANK_UNBLANK)
@@ -684,10 +710,14 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
 
 	writel(fbi->pcr, fbi->regs + LCDC_PCR);
 #ifndef PWMR_BACKLIGHT_AVAILABLE
-	writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
+	if (fbi->pwmr)
+		writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
 #endif
 	writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
-	writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
+
+	/* dmacr = 0 is no valid value, as we need DMA control marks. */
+	if (fbi->dmacr)
+		writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
 
 	return 0;
 }
@@ -723,13 +753,12 @@ static int imxfb_resume(struct platform_device *dev)
 #define imxfb_resume	NULL
 #endif
 
-static int __init imxfb_init_fbinfo(struct platform_device *pdev)
+static int imxfb_init_fbinfo(struct platform_device *pdev)
 {
 	struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
 	struct fb_info *info = dev_get_drvdata(&pdev->dev);
 	struct imxfb_info *fbi = info->par;
-	struct imx_fb_videomode *m;
-	int i;
+	struct device_node *np;
 
 	pr_debug("%s\n",__func__);
 
@@ -760,41 +789,95 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
 	info->fbops			= &imxfb_ops;
 	info->flags			= FBINFO_FLAG_DEFAULT |
 					  FBINFO_READS_FAST;
-	info->var.grayscale		= pdata->cmap_greyscale;
-	fbi->cmap_inverse		= pdata->cmap_inverse;
-	fbi->cmap_static		= pdata->cmap_static;
-	fbi->lscr1			= pdata->lscr1;
-	fbi->dmacr			= pdata->dmacr;
-	fbi->pwmr			= pdata->pwmr;
-	fbi->lcd_power			= pdata->lcd_power;
-	fbi->backlight_power		= pdata->backlight_power;
-
-	for (i = 0, m = &pdata->mode[0]; i < pdata->num_modes; i++, m++)
-		info->fix.smem_len = max_t(size_t, info->fix.smem_len,
-				m->mode.xres * m->mode.yres * m->bpp / 8);
+	if (pdata) {
+		info->var.grayscale		= pdata->cmap_greyscale;
+		fbi->cmap_inverse		= pdata->cmap_inverse;
+		fbi->cmap_static		= pdata->cmap_static;
+		fbi->lscr1			= pdata->lscr1;
+		fbi->dmacr			= pdata->dmacr;
+		fbi->pwmr			= pdata->pwmr;
+		fbi->lcd_power			= pdata->lcd_power;
+		fbi->backlight_power		= pdata->backlight_power;
+	} else {
+		np = pdev->dev.of_node;
+		info->var.grayscale = of_property_read_bool(np,
+						"cmap-greyscale");
+		fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse");
+		fbi->cmap_static = of_property_read_bool(np, "cmap-static");
+
+		fbi->lscr1 = IMXFB_LSCR1_DEFAULT;
+		of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1);
+
+		of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr);
+
+		/* These two function pointers could be used by some specific
+		 * platforms. */
+		fbi->lcd_power = NULL;
+		fbi->backlight_power = NULL;
+	}
+
+	return 0;
+}
+
+static int imxfb_of_read_mode(struct device *dev, struct device_node *np,
+		struct imx_fb_videomode *imxfb_mode)
+{
+	int ret;
+	struct fb_videomode *of_mode = &imxfb_mode->mode;
+	u32 bpp;
+	u32 pcr;
+
+	ret = of_property_read_string(np, "model", &of_mode->name);
+	if (ret)
+		of_mode->name = NULL;
+
+	ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE);
+	if (ret) {
+		dev_err(dev, "Failed to get videomode from DT\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "bits-per-pixel", &bpp);
+	ret |= of_property_read_u32(np, "fsl,pcr", &pcr);
+
+	if (ret) {
+		dev_err(dev, "Failed to read bpp and pcr from DT\n");
+		return -EINVAL;
+	}
+
+	if (bpp < 1 || bpp > 255) {
+		dev_err(dev, "Bits per pixel have to be between 1 and 255\n");
+		return -EINVAL;
+	}
+
+	imxfb_mode->bpp = bpp;
+	imxfb_mode->pcr = pcr;
 
 	return 0;
 }
 
-static int __init imxfb_probe(struct platform_device *pdev)
+static int imxfb_probe(struct platform_device *pdev)
 {
 	struct imxfb_info *fbi;
 	struct fb_info *info;
 	struct imx_fb_platform_data *pdata;
 	struct resource *res;
+	struct imx_fb_videomode *m;
+	const struct of_device_id *of_id;
 	int ret, i;
+	int bytes_per_pixel;
 
 	dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
 
+	of_id = of_match_device(imxfb_of_dev_id, &pdev->dev);
+	if (of_id)
+		pdev->id_entry = of_id->data;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res)
 		return -ENODEV;
 
 	pdata = pdev->dev.platform_data;
-	if (!pdata) {
-		dev_err(&pdev->dev,"No platform_data available\n");
-		return -ENOMEM;
-	}
 
 	info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
 	if (!info)
@@ -802,15 +885,55 @@ static int __init imxfb_probe(struct platform_device *pdev)
 
 	fbi = info->par;
 
-	if (!fb_mode)
-		fb_mode = pdata->mode[0].mode.name;
-
 	platform_set_drvdata(pdev, info);
 
 	ret = imxfb_init_fbinfo(pdev);
 	if (ret < 0)
 		goto failed_init;
 
+	if (pdata) {
+		if (!fb_mode)
+			fb_mode = pdata->mode[0].mode.name;
+
+		fbi->mode = pdata->mode;
+		fbi->num_modes = pdata->num_modes;
+	} else {
+		struct device_node *display_np;
+		fb_mode = NULL;
+
+		display_np = of_parse_phandle(pdev->dev.of_node, "display", 0);
+		if (!display_np) {
+			dev_err(&pdev->dev, "No display defined in devicetree\n");
+			ret = -EINVAL;
+			goto failed_of_parse;
+		}
+
+		/*
+		 * imxfb does not support more modes, we choose only the native
+		 * mode.
+		 */
+		fbi->num_modes = 1;
+
+		fbi->mode = devm_kzalloc(&pdev->dev,
+				sizeof(struct imx_fb_videomode), GFP_KERNEL);
+		if (!fbi->mode) {
+			ret = -ENOMEM;
+			goto failed_of_parse;
+		}
+
+		ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode);
+		if (ret)
+			goto failed_of_parse;
+	}
+
+	/* Calculate maximum bytes used per pixel. In most cases this should
+	 * be the same as m->bpp/8 */
+	m = &fbi->mode[0];
+	bytes_per_pixel = (m->bpp + 7) / 8;
+	for (i = 0; i < fbi->num_modes; i++, m++)
+		info->fix.smem_len = max_t(size_t, info->fix.smem_len,
+				m->mode.xres * m->mode.yres * bytes_per_pixel);
+
 	res = request_mem_region(res->start, resource_size(res),
 				DRIVER_NAME);
 	if (!res) {
@@ -843,7 +966,8 @@ static int __init imxfb_probe(struct platform_device *pdev)
 		goto failed_ioremap;
 	}
 
-	if (!pdata->fixed_screen_cpu) {
+	/* Seems not being used by anyone, so no support for oftree */
+	if (!pdata || !pdata->fixed_screen_cpu) {
 		fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
 		fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
 				fbi->map_size, &fbi->map_dma, GFP_KERNEL);
@@ -868,18 +992,16 @@ static int __init imxfb_probe(struct platform_device *pdev)
 		info->fix.smem_start = fbi->screen_dma;
 	}
 
-	if (pdata->init) {
+	if (pdata && pdata->init) {
 		ret = pdata->init(fbi->pdev);
 		if (ret)
 			goto failed_platform_init;
 	}
 
-	fbi->mode = pdata->mode;
-	fbi->num_modes = pdata->num_modes;
 
 	INIT_LIST_HEAD(&info->modelist);
-	for (i = 0; i < pdata->num_modes; i++)
-		fb_add_videomode(&pdata->mode[i].mode, &info->modelist);
+	for (i = 0; i < fbi->num_modes; i++)
+		fb_add_videomode(&fbi->mode[i].mode, &info->modelist);
 
 	/*
 	 * This makes sure that our colour bitfield
@@ -909,10 +1031,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
 failed_register:
 	fb_dealloc_cmap(&info->cmap);
 failed_cmap:
-	if (pdata->exit)
+	if (pdata && pdata->exit)
 		pdata->exit(fbi->pdev);
 failed_platform_init:
-	if (!pdata->fixed_screen_cpu)
+	if (pdata && !pdata->fixed_screen_cpu)
 		dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
 			fbi->map_dma);
 failed_map:
@@ -921,6 +1043,7 @@ failed_ioremap:
 failed_getclock:
 	release_mem_region(res->start, resource_size(res));
 failed_req:
+failed_of_parse:
 	kfree(info->pseudo_palette);
 failed_init:
 	platform_set_drvdata(pdev, NULL);
@@ -945,7 +1068,7 @@ static int imxfb_remove(struct platform_device *pdev)
 	unregister_framebuffer(info);
 
 	pdata = pdev->dev.platform_data;
-	if (pdata->exit)
+	if (pdata && pdata->exit)
 		pdata->exit(fbi->pdev);
 
 	fb_dealloc_cmap(&info->cmap);
@@ -974,6 +1097,7 @@ static struct platform_driver imxfb_driver = {
 	.shutdown	= imxfb_shutdown,
 	.driver		= {
 		.name	= DRIVER_NAME,
+		.of_match_table = imxfb_of_dev_id,
 	},
 	.id_table	= imxfb_devtype,
 };
-- 
1.8.2.1



From oliver+list at schinagl.nl  Sun May 26 06:53:30 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Sun, 26 May 2013 12:53:30 +0200
Subject: [linux-sunxi] [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c
 driver
In-Reply-To: <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <51A1E9AA.4000008@schinagl.nl>


Just replying because I want to understand certain choices you make, 
absolutely not questioning your code!

On 05/26/13 12:20, Maxime Ripard wrote:
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/completion.h>
You forgot to add #include <linux/bitops.h> for BIT()


> +
> +static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8 value)
> +{
> +	writel(value, i2c_dev->membase + reg);
Why writel? and why without (u32)value? I thought iowrite* where the 
preferred calls and in this case, wouldn't we want writeb since value is u8?

> +}
> +
> +static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
> +{
> +	return readl(i2c_dev->membase + reg);
And here, readl does match the return of u32, but aren't we always 
reading 8 bits since the TWI Data Register only uses the first 8 bits?
So wouldn't we want to return u8 and readb?

> +static int sunxi_i2c_probe(struct platform_device *pdev)
> +{
> +	struct sunxi_i2c_dev *i2c_dev;
> +	struct device_node *np;
> +	u32 freq, div_m, div_n;
> +	struct resource res;
I feel stupid for questioning this, since it only shows my lack of 
knowledge, but
If you declare all the memory here, isn't all the data lost after 
exiting the _probe function? we pass a pointer to this memory in the 
of_address_to_resource() function so that fills it, right?

Or does after devm_ioremap_resource it no longer matter, since that 
function got what it needed and useless after?

Just asking because of the wdt driver and possibly mine that you told us 
to change.



Sorry for asking (again) maybe very obvious things. Just trying to learn.

Oliver


From baruch at tkos.co.il  Sun May 26 08:12:46 2013
From: baruch at tkos.co.il (Baruch Siach)
Date: Sun, 26 May 2013 15:12:46 +0300
Subject: [PATCH 1/2] clocksource: dw_apb: remove unused header
Message-ID: <1369570367-994-1-git-send-email-baruch@tkos.co.il>

The time.h header seems not to be used by current code. Removing this include
allows the driver to build on other architecture that do not have this header.

Cc: Ingo Molnar <mingo at redhat.com>
Cc: Peter Zijlstra <peterz at infradead.org>
Cc: John Stultz <john.stultz at linaro.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Dinh Nguyen <dinguyen at altera.com>
Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 drivers/clocksource/dw_apb_timer_of.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index ab09ed3..5a61ebc 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -21,7 +21,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <asm/mach/time.h>
 #include <asm/sched_clock.h>
 
 static void timer_get_base_and_rate(struct device_node *np,
-- 
1.7.10.4



From baruch at tkos.co.il  Sun May 26 08:12:47 2013
From: baruch at tkos.co.il (Baruch Siach)
Date: Sun, 26 May 2013 15:12:47 +0300
Subject: [RFC PATCH 2/2] clocksource: dw_apb: allow build for architectures
 other than arm
Message-ID: <1369570367-994-2-git-send-email-baruch@tkos.co.il>

ARM is the only architecture providing sched_clock.h and setup_sched_clock().
Implement sched_clock() for use by other architectures.

Cc: Ingo Molnar <mingo at redhat.com>
Cc: Peter Zijlstra <peterz at infradead.org>
Cc: John Stultz <john.stultz at linaro.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Dinh Nguyen <dinguyen at altera.com>
Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/Kconfig                      |    1 +
 drivers/clocksource/Kconfig           |    3 +++
 drivers/clocksource/dw_apb_timer_of.c |   18 ++++++++++++++++++
 3 files changed, 22 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1cacda4..7489604 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -47,6 +47,7 @@ config ARM
 	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 	select HAVE_PERF_EVENTS
 	select HAVE_REGS_AND_STACK_ACCESS_API
+	select HAVE_SETUP_SCHED_CLOCK
 	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_UID16
 	select KTIME_SCALAR
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7..0fd6d13 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -1,3 +1,6 @@
+config HAVE_SETUP_SCHED_CLOCK
+	bool
+
 config CLKSRC_OF
 	bool
 
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 5a61ebc..9fdb4d3 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -21,7 +21,11 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
+#ifdef CONFIG_HAVE_SETUP_SCHED_CLOCK
 #include <asm/sched_clock.h>
+#else
+#include <linux/sched.h>
+#endif
 
 static void timer_get_base_and_rate(struct device_node *np,
 				    void __iomem **base, u32 *rate)
@@ -73,6 +77,9 @@ static void add_clocksource(struct device_node *source_timer)
 }
 
 static void __iomem *sched_io_base;
+#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
+static u64 sched_clock_mult __read_mostly;
+#endif
 
 static u32 read_sched_clock(void)
 {
@@ -97,7 +104,11 @@ static void init_sched_clock(void)
 	timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
 	of_node_put(sched_timer);
 
+#ifdef CONFIG_HAVE_SETUP_SCHED_CLOCK
 	setup_sched_clock(read_sched_clock, 32, rate);
+#else
+	sched_clock_mult = NSEC_PER_SEC / rate;
+#endif
 }
 
 static const struct of_device_id osctimer_ids[] __initconst = {
@@ -124,3 +135,10 @@ void __init dw_apb_timer_init(void)
 
 	init_sched_clock();
 }
+
+#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
+unsigned long long notrace sched_clock()
+{
+	return read_sched_clock() * sched_clock_mult;
+}
+#endif
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May 26 08:28:57 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 14:28:57 +0200
Subject: [PATCH 1/1] mmc: of_mmc_spi: fix card detect irq
Message-ID: <1369571337-9300-1-git-send-email-plagnioj@jcrosoft.com>

set missing irq type the IRQF_ONESHOT

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: stable <stable at vger.kernel.org> # 3.4+
Cc: linux-mmc at vger.kernel.org
---
 drivers/mmc/host/of_mmc_spi.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
index d720b5e..cfb2e61 100644
--- a/drivers/mmc/host/of_mmc_spi.c
+++ b/drivers/mmc/host/of_mmc_spi.c
@@ -74,8 +74,8 @@ static int of_mmc_spi_init(struct device *dev,
 {
 	struct of_mmc_spi *oms = to_of_mmc_spi(dev);
 
-	return request_threaded_irq(oms->detect_irq, NULL, irqhandler, 0,
-				    dev_name(dev), mmc);
+	return request_threaded_irq(oms->detect_irq, NULL, irqhandler,
+		IRQF_ONESHOT, dev_name(dev), mmc);
 }
 
 static void of_mmc_spi_exit(struct device *dev, void *mmc)
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:22 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:22 +0900
Subject: [GIT PULL] Renesas ARM based emev2 SoC updates for v3.11
Message-ID: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-emev2-for-v3.11

for you to fetch changes up to 94a6af856df56ed39bb59ebe17bfa2d10fb333f2:

  ARM: shmobile: emev2: Remove init_irq declaration in machine description (2013-05-22 21:42:03 +0900)

----------------------------------------------------------------
Renesas ARM based emev2 SoC updates for v3.11

Clean-up from Maxime Ripard to remove unnecessary init_irq declaration in
machine description.

----------------------------------------------------------------
Maxime Ripard (1):
      ARM: shmobile: emev2: Remove init_irq declaration in machine description

 arch/arm/mach-shmobile/setup-emev2.c |    2 --
 1 file changed, 2 deletions(-)


From horms+renesas at verge.net.au  Sun May 26 09:05:23 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:23 +0900
Subject: [PATCH] ARM: shmobile: emev2: Remove init_irq declaration in machine
 description
In-Reply-To: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573523-10980-2-git-send-email-horms+renesas@verge.net.au>

From: Maxime Ripard <maxime.ripard at free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-emev2.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 899a86c..66694e0 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,7 +20,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/gpio-em.h>
 #include <linux/of_platform.h>
@@ -454,7 +453,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
 	.smp		= smp_ops(emev2_smp_ops),
 	.init_early	= emev2_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= emev2_add_standard_devices_dt,
 	.dt_compat	= emev2_boards_compat_dt,
 MACHINE_END
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:51 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:51 +0900
Subject: [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11
Message-ID: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a73a4-for-v3.11

for you to fetch changes up to d7f17c1c0ddbd61ad24ae93ad9ec21fc223659ba:

  ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits (2013-05-26 20:17:43 +0900)

----------------------------------------------------------------
Renesas ARM based r8a73a0 SoC updates for v3.11

Clean-up from Maxime Ripard to remove unnecessary init_irq declaration in
machine description.

Clean-up from Magnus Damm to remove unused GIC CPU interface portions
of r8a73a4.dtsi

Increased clock coverage from Kuninori Morimoto.

----------------------------------------------------------------
Kuninori Morimoto (4):
      ARM: shmobile: r8a73a4: add main clock
      ARM: shmobile: r8a73a4: add pll clocks
      ARM: shmobile: r8a73a4: add div4 clocks
      ARM: shmobile: r8a73a4: add div6 clocks

Magnus Damm (1):
      ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits

Maxime Ripard (1):
      ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description

 arch/arm/boot/dts/r8a73a4.dtsi         |    6 -
 arch/arm/mach-shmobile/clock-r8a73a4.c |  375 ++++++++++++++++++++++++++++++--
 arch/arm/mach-shmobile/setup-r8a73a4.c |    2 -
 3 files changed, 359 insertions(+), 24 deletions(-)


From horms+renesas at verge.net.au  Sun May 26 09:05:54 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:54 +0900
Subject: [PATCH 3/6] ARM: shmobile: r8a73a4: add div4 clocks
In-Reply-To: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573557-11071-4-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

DIV4 clocks control each core clocks.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   45 ++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 2be592f..147314a 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -32,6 +32,8 @@
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR5 0xe6150144
 
+#define FRQCRA		0xE6150000
+#define FRQCRB		0xE6150004
 #define CKSCR		0xE61500C0
 #define PLLECR		0xE61500D0
 #define PLL1CR		0xE6150028
@@ -175,6 +177,46 @@ static struct clk *main_clks[] = {
 	&pll2h_clk,
 };
 
+/* DIV4 */
+static void div4_kick(struct clk *clk)
+{
+	unsigned long value;
+
+	/* set KICK bit in FRQCRB to update hardware setting */
+	value = ioread32(CPG_MAP(FRQCRB));
+	value |= (1 << 31);
+	iowrite32(value, CPG_MAP(FRQCRB));
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
+
+static struct clk_div_mult_table div4_div_mult_table = {
+	.divisors	= divisors,
+	.nr_divisors	= ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+	.div_mult_table	= &div4_div_mult_table,
+	.kick		= div4_kick,
+};
+
+enum {
+	DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+	DIV4_ZX, DIV4_ZS, DIV4_HP,
+	DIV4_NR };
+
+static struct clk div4_clks[DIV4_NR] = {
+	[DIV4_I]	= SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
+	[DIV4_M3]	= SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+	[DIV4_B]	= SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
+	[DIV4_M1]	= SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
+	[DIV4_M2]	= SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
+	[DIV4_ZX]	= SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
+	[DIV4_ZS]	= SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
+	[DIV4_HP]	= SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
+};
+
+/* MSTP */
 enum {
 	MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
 	MSTP522,
@@ -258,6 +300,9 @@ void __init r8a73a4_clock_init(void)
 		ret = clk_register(main_clks[k]);
 
 	if (!ret)
+		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+	if (!ret)
 		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:52 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:52 +0900
Subject: [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock
In-Reply-To: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573557-11071-2-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Almost all clock needs main clock which is basis clock on r8a73a4.
This patch adds it, and, set parent clock via CKSCR register.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   53 ++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00..42942b4 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,6 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define CPG_BASE 0xe6150000
@@ -31,6 +32,8 @@
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR5 0xe6150144
 
+#define CKSCR		0xE61500C0
+
 static struct clk_mapping cpg_mapping = {
 	.phys   = CPG_BASE,
 	.len    = CPG_LEN,
@@ -51,10 +54,32 @@ static struct clk extal2_clk = {
 	.mapping	= &cpg_mapping,
 };
 
+static struct sh_clk_ops followparent_clk_ops = {
+	.recalc	= followparent_recalc,
+};
+
+static struct clk main_clk = {
+	/* .parent will be set r8a73a4_clock_init */
+	.ops	= &followparent_clk_ops,
+};
+
+SH_CLK_RATIO(div2,	1, 2);
+SH_CLK_RATIO(div4,	1, 4);
+
+SH_FIXED_RATIO_CLK(main_div2_clk,	main_clk,		div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,	extal1_clk,		div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,	extal2_clk,		div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,	extal2_clk,		div4);
+
 static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,
+	&extal1_div2_clk,
 	&extal2_clk,
+	&extal2_div2_clk,
+	&extal2_div4_clk,
+	&main_clk,
+	&main_div2_clk,
 };
 
 enum {
@@ -74,6 +99,13 @@ static struct clk mstp_clks[MSTP_NR] = {
 };
 
 static struct clk_lookup lookups[] = {
+	/* main clock */
+	CLKDEV_CON_ID("extal1",			&extal1_clk),
+	CLKDEV_CON_ID("extal1_div2",		&extal1_div2_clk),
+	CLKDEV_CON_ID("extal2",			&extal2_clk),
+	CLKDEV_CON_ID("extal2_div2",		&extal2_div2_clk),
+	CLKDEV_CON_ID("extal2_div4",		&extal2_div4_clk),
+
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -90,6 +122,7 @@ void __init r8a73a4_clock_init(void)
 {
 	void __iomem *cpg_base, *reg;
 	int k, ret = 0;
+	u32 ckscr;
 
 	/* fix MPCLK to EXTAL2 for now.
 	 * this is needed until more detailed clock topology is supported
@@ -100,6 +133,26 @@ void __init r8a73a4_clock_init(void)
 	iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
 	iounmap(cpg_base);
 
+	reg = ioremap_nocache(CKSCR, PAGE_SIZE);
+	BUG_ON(!reg);
+	ckscr = ioread32(reg);
+	iounmap(reg);
+
+	switch ((ckscr >> 28) & 0x3) {
+	case 0:
+		main_clk.parent = &extal1_clk;
+		break;
+	case 1:
+		main_clk.parent = &extal1_div2_clk;
+		break;
+	case 2:
+		main_clk.parent = &extal2_clk;
+		break;
+	case 3:
+		main_clk.parent = &extal2_div2_clk;
+		break;
+	}
+
 	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 		ret = clk_register(main_clks[k]);
 
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:57 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:57 +0900
Subject: [PATCH 6/6] ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT
 bits
In-Reply-To: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573557-11071-7-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Remove unused GIC CPU interface DT bits for r8a73a4.

Signed-off-by: Magnus Damm <damm at opensource.se>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/r8a73a4.dtsi |    6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fde2a33..4ff2019 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -37,12 +37,6 @@
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
 		interrupts = <1 9 0xf04>;
-
-		gic-cpuif at 4 {
-			compatible = "arm,gic-cpuif";
-			cpuif-id = <4>;
-			cpu = <&cpu0>;
-		};
 	};
 
 	timer {
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:56 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:56 +0900
Subject: [PATCH 5/6] ARM: shmobile: r8a73a4: Remove init_irq declaration in
 machine description
In-Reply-To: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573557-11071-6-git-send-email-horms+renesas@verge.net.au>

From: Maxime Ripard <maxime.ripard at free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a73a4.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c5a75a7..0b78896 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
@@ -194,7 +193,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
-	.init_irq	= irqchip_init,
 	.init_machine	= r8a73a4_add_standard_devices_dt,
 	.init_time	= shmobile_timer_init,
 	.dt_compat	= r8a73a4_boards_compat_dt,
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:53 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:53 +0900
Subject: [PATCH 2/6] ARM: shmobile: r8a73a4: add pll clocks
In-Reply-To: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573557-11071-3-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

PLL clocks are basis clock for other clock.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a73a4.c |  101 ++++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 42942b4..2be592f 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -33,6 +33,14 @@
 #define SMSTPCR5 0xe6150144
 
 #define CKSCR		0xE61500C0
+#define PLLECR		0xE61500D0
+#define PLL1CR		0xE6150028
+#define PLL2CR		0xE615002C
+#define PLL2SCR		0xE61501F4
+#define PLL2HCR		0xE61501E4
+
+
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
 
 static struct clk_mapping cpg_mapping = {
 	.phys   = CPG_BASE,
@@ -71,6 +79,86 @@ SH_FIXED_RATIO_CLK(extal1_div2_clk,	extal1_clk,		div2);
 SH_FIXED_RATIO_CLK(extal2_div2_clk,	extal2_clk,		div2);
 SH_FIXED_RATIO_CLK(extal2_div4_clk,	extal2_clk,		div4);
 
+/*
+ *		PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+	[0] = &main_clk,
+	[1] = &main_div2_clk
+};
+
+static struct clk *pll_parent_main_extal[8] = {
+	[0] = &main_div2_clk,
+	[1] = &extal2_div2_clk,
+	[3] = &extal2_div4_clk,
+	[4] = &main_clk,
+	[5] = &extal2_clk,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+	unsigned long mult = 1;
+
+	if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+		mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+
+	return clk->parent->rate * mult;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 val;
+	int i, ret;
+
+	if (!clk->parent_table || !clk->parent_num)
+		return -EINVAL;
+
+	/* Search the parent */
+	for (i = 0; i < clk->parent_num; i++)
+		if (clk->parent_table[i] == parent)
+			break;
+
+	if (i == clk->parent_num)
+		return -ENODEV;
+
+	ret = clk_reparent(clk, parent);
+	if (ret < 0)
+		return ret;
+
+	val = ioread32(clk->mapped_reg) &
+		~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+	iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+
+	return 0;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+	.recalc		= pll_recalc,
+	.set_parent	= pll_set_parent,
+};
+
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)		\
+	static struct clk name = {			\
+		.ops		= &pll_clk_ops,		\
+		.flags		= CLK_ENABLE_ON_INIT,	\
+		.parent		= p,			\
+		.parent_table	= pt,			\
+		.parent_num	= ARRAY_SIZE(pt),	\
+		.src_width	= w,			\
+		.src_shift	= s,			\
+		.enable_reg	= (void __iomem *)reg,	\
+		.enable_bit	= e,			\
+		.mapping	= &cpg_mapping,		\
+	}
+
+PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
+PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
+PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
+PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
+
+SH_FIXED_RATIO_CLK(pll1_div2_clk,	pll1_clk,	div2);
+
 static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,
@@ -80,6 +168,11 @@ static struct clk *main_clks[] = {
 	&extal2_div4_clk,
 	&main_clk,
 	&main_div2_clk,
+	&pll1_clk,
+	&pll1_div2_clk,
+	&pll2_clk,
+	&pll2s_clk,
+	&pll2h_clk,
 };
 
 enum {
@@ -106,6 +199,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("extal2_div2",		&extal2_div2_clk),
 	CLKDEV_CON_ID("extal2_div4",		&extal2_div4_clk),
 
+	/* pll clock */
+	CLKDEV_CON_ID("pll1",			&pll1_clk),
+	CLKDEV_CON_ID("pll1_div2",		&pll1_div2_clk),
+	CLKDEV_CON_ID("pll2",			&pll2_clk),
+	CLKDEV_CON_ID("pll2s",			&pll2s_clk),
+	CLKDEV_CON_ID("pll2h",			&pll2h_clk),
+
+	/* MSTP */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Sun May 26 09:05:55 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:05:55 +0900
Subject: [PATCH 4/6] ARM: shmobile: r8a73a4: add div6 clocks
In-Reply-To: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573557-11071-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369573557-11071-5-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

DIV6 clocks control each core clocks.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a73a4.c |  182 ++++++++++++++++++++++++++++----
 1 file changed, 163 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 147314a..f6227bb 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -28,19 +28,34 @@
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
 
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR5 0xe6150144
 
 #define FRQCRA		0xE6150000
 #define FRQCRB		0xE6150004
-#define CKSCR		0xE61500C0
+#define VCLKCR1		0xE6150008
+#define VCLKCR2		0xE615000C
+#define VCLKCR3		0xE615001C
+#define VCLKCR4		0xE6150014
+#define VCLKCR5		0xE6150034
+#define ZBCKCR		0xE6150010
+#define SD0CKCR		0xE6150074
+#define SD1CKCR		0xE6150078
+#define SD2CKCR		0xE615007C
+#define MMC0CKCR	0xE6150240
+#define MMC1CKCR	0xE6150244
+#define FSIACKCR	0xE6150018
+#define FSIBCKCR	0xE6150090
+#define MPCKCR		0xe6150080
+#define SPUVCKCR	0xE6150094
+#define HSICKCR		0xE615026C
+#define M4CKCR		0xE6150098
 #define PLLECR		0xE61500D0
 #define PLL1CR		0xE6150028
 #define PLL2CR		0xE615002C
 #define PLL2SCR		0xE61501F4
 #define PLL2HCR		0xE61501E4
-
+#define CKSCR		0xE61500C0
 
 #define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
 
@@ -81,6 +96,13 @@ SH_FIXED_RATIO_CLK(extal1_div2_clk,	extal1_clk,		div2);
 SH_FIXED_RATIO_CLK(extal2_div2_clk,	extal2_clk,		div2);
 SH_FIXED_RATIO_CLK(extal2_div4_clk,	extal2_clk,		div4);
 
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
 /*
  *		PLL clocks
  */
@@ -170,6 +192,8 @@ static struct clk *main_clks[] = {
 	&extal2_div4_clk,
 	&main_clk,
 	&main_div2_clk,
+	&fsiack_clk,
+	&fsibck_clk,
 	&pll1_clk,
 	&pll1_div2_clk,
 	&pll2_clk,
@@ -216,6 +240,111 @@ static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_HP]	= SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 };
 
+enum {
+	DIV6_ZB,
+	DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+	DIV6_MMC0, DIV6_MMC1,
+	DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
+	DIV6_FSIA, DIV6_FSIB,
+	DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
+	DIV6_NR };
+
+static struct clk *div6_parents[8] = {
+	[0] = &pll1_div2_clk,
+	[1] = &pll2s_clk,
+	[3] = &extal2_clk,
+	[4] = &main_div2_clk,
+	[6] = &extalr_clk,
+};
+
+static struct clk *fsia_parents[4] = {
+	[0] = &pll1_div2_clk,
+	[1] = &pll2s_clk,
+	[2] = &fsiack_clk,
+};
+
+static struct clk *fsib_parents[4] = {
+	[0] = &pll1_div2_clk,
+	[1] = &pll2s_clk,
+	[2] = &fsibck_clk,
+};
+
+static struct clk *mp_parents[4] = {
+	[0] = &pll1_div2_clk,
+	[1] = &pll2s_clk,
+	[2] = &extal2_clk,
+	[3] = &extal2_clk,
+};
+
+static struct clk *m4_parents[2] = {
+	[0] = &pll2s_clk,
+};
+
+static struct clk *hsi_parents[4] = {
+	[0] = &pll2h_clk,
+	[1] = &pll1_div2_clk,
+	[3] = &pll2s_clk,
+};
+
+/*** FIXME ***
+ * SH_CLK_DIV6_EXT() macro doesn't care .mapping
+ * but, it is necessary on R-Car (= ioremap() base CPG)
+ * The difference between
+ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
+ * is only .mapping
+ */
+#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,			\
+			    _num_parents, _src_shift, _src_width)	\
+{									\
+	.enable_reg	= (void __iomem *)_reg,				\
+	.enable_bit	= 0, /* unused */				\
+	.flags		= _flags | CLK_MASK_DIV_ON_DISABLE,		\
+	.div_mask	= SH_CLK_DIV6_MSK,				\
+	.parent_table	= _parents,					\
+	.parent_num	= _num_parents,					\
+	.src_shift	= _src_shift,					\
+	.src_width	= _src_width,					\
+	.mapping	= &cpg_mapping,					\
+}
+
+static struct clk div6_clks[DIV6_NR] = {
+	[DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+				div6_parents, 2, 7, 1),
+	[DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
+				div6_parents, 2, 6, 2),
+	[DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
+				div6_parents, 2, 6, 2),
+	[DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
+				div6_parents, 2, 6, 2),
+	[DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
+				div6_parents, 2, 6, 2),
+	[DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
+				div6_parents, 2, 6, 2),
+	[DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
+				div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+	[DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
+				div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+	[DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
+				div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+	[DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
+				div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+	[DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
+				div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+	[DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
+				fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+	[DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
+				fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+	[DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
+				mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+	/* pll2s will be selected always for M4 */
+	[DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
+				m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
+	[DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
+				hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
+	[DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
+				mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+};
+
 /* MSTP */
 enum {
 	MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
@@ -224,12 +353,12 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
-	[MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
-	[MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
-	[MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
-	[MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
-	[MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
-	[MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
+	[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 4, 0), /* SCIFA0 */
+	[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 3, 0), /* SCIFA1 */
+	[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 6, 0), /* SCIFB0 */
+	[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 7, 0), /* SCIFB1 */
+	[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 16, 0), /* SCIFB2 */
+	[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 17, 0), /* SCIFB3 */
 	[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 };
 
@@ -240,6 +369,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("extal2",			&extal2_clk),
 	CLKDEV_CON_ID("extal2_div2",		&extal2_div2_clk),
 	CLKDEV_CON_ID("extal2_div4",		&extal2_div4_clk),
+	CLKDEV_CON_ID("fsiack",			&fsiack_clk),
+	CLKDEV_CON_ID("fsibck",			&fsibck_clk),
 
 	/* pll clock */
 	CLKDEV_CON_ID("pll1",			&pll1_clk),
@@ -248,6 +379,25 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("pll2s",			&pll2s_clk),
 	CLKDEV_CON_ID("pll2h",			&pll2h_clk),
 
+	/* DIV6 */
+	CLKDEV_CON_ID("zb",			&div6_clks[DIV6_ZB]),
+	CLKDEV_CON_ID("sdhi0",			&div6_clks[DIV6_SDHI0]),
+	CLKDEV_CON_ID("sdhi1",			&div6_clks[DIV6_SDHI1]),
+	CLKDEV_CON_ID("sdhi2",			&div6_clks[DIV6_SDHI2]),
+	CLKDEV_CON_ID("mmc0",			&div6_clks[DIV6_MMC0]),
+	CLKDEV_CON_ID("mmc1",			&div6_clks[DIV6_MMC1]),
+	CLKDEV_CON_ID("vck1",			&div6_clks[DIV6_VCK1]),
+	CLKDEV_CON_ID("vck2",			&div6_clks[DIV6_VCK2]),
+	CLKDEV_CON_ID("vck3",			&div6_clks[DIV6_VCK3]),
+	CLKDEV_CON_ID("vck4",			&div6_clks[DIV6_VCK4]),
+	CLKDEV_CON_ID("vck5",			&div6_clks[DIV6_VCK5]),
+	CLKDEV_CON_ID("fsia",			&div6_clks[DIV6_FSIA]),
+	CLKDEV_CON_ID("fsib",			&div6_clks[DIV6_FSIB]),
+	CLKDEV_CON_ID("mp",			&div6_clks[DIV6_MP]),
+	CLKDEV_CON_ID("m4",			&div6_clks[DIV6_M4]),
+	CLKDEV_CON_ID("hsi",			&div6_clks[DIV6_HSI]),
+	CLKDEV_CON_ID("spuv",			&div6_clks[DIV6_SPUV]),
+
 	/* MSTP */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
@@ -263,19 +413,10 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a73a4_clock_init(void)
 {
-	void __iomem *cpg_base, *reg;
+	void __iomem *reg;
 	int k, ret = 0;
 	u32 ckscr;
 
-	/* fix MPCLK to EXTAL2 for now.
-	 * this is needed until more detailed clock topology is supported
-	 */
-	cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
-	BUG_ON(!cpg_base);
-	reg = cpg_base + (MPCKCR - CPG_BASE);
-	iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
-	iounmap(cpg_base);
-
 	reg = ioremap_nocache(CKSCR, PAGE_SIZE);
 	BUG_ON(!reg);
 	ckscr = ioread32(reg);
@@ -303,6 +444,9 @@ void __init r8a73a4_clock_init(void)
 		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
 	if (!ret)
+		ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
+
+	if (!ret)
 		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-- 
1.7.10.4



From maxime.ripard at free-electrons.com  Sun May 26 09:21:20 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 15:21:20 +0200
Subject: [linux-sunxi] [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c
 driver
In-Reply-To: <51A1E9AA.4000008@schinagl.nl>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
 <51A1E9AA.4000008@schinagl.nl>
Message-ID: <20130526132120.GJ17847@lukather>

On Sun, May 26, 2013 at 12:53:30PM +0200, Oliver Schinagl wrote:
> 
> Just replying because I want to understand certain choices you make,
> absolutely not questioning your code!
> 
> On 05/26/13 12:20, Maxime Ripard wrote:
> >+ * warranty of any kind, whether express or implied.
> >+ */
> >+
> >+#include <linux/clk.h>
> >+#include <linux/completion.h>
> You forgot to add #include <linux/bitops.h> for BIT()

Ah, yes, thanks

> >+static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8 value)
> >+{
> >+	writel(value, i2c_dev->membase + reg);
> Why writel? and why without (u32)value? I thought iowrite* where the
> preferred calls and in this case, wouldn't we want writeb since
> value is u8?

You're right, value should be a u32 here, thanks for noticing.

For the iowrite* vs write*, there's no consensus, and as such no
preferred way. write* functions are doing an MMIO only access,
while iowrite functions can do MMIO and port I/O accesses.

Note that it doesn't change anything on ARM, since there's no port IO on
ARM.

> >+}
> >+
> >+static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
> >+{
> >+	return readl(i2c_dev->membase + reg);
> And here, readl does match the return of u32, but aren't we always
> reading 8 bits since the TWI Data Register only uses the first 8
> bits?
> So wouldn't we want to return u8 and readb?

They are meant to be general purpose accessors, so we shouldn't focus
only on the data register.

> 
> >+static int sunxi_i2c_probe(struct platform_device *pdev)
> >+{
> >+	struct sunxi_i2c_dev *i2c_dev;
> >+	struct device_node *np;
> >+	u32 freq, div_m, div_n;
> >+	struct resource res;
> I feel stupid for questioning this, since it only shows my lack of
> knowledge, but
> If you declare all the memory here, isn't all the data lost after
> exiting the _probe function? we pass a pointer to this memory in the
> of_address_to_resource() function so that fills it, right?
> 
> Or does after devm_ioremap_resource it no longer matter, since that
> function got what it needed and useless after?

The struct resource is only there to declare the base address and the
size of memory address. Once we have mapped it, we don't care about it
anymore.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From horms at verge.net.au  Sun May 26 09:25:17 2013
From: horms at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:25:17 +0900
Subject: [PATCH] ARM: mach-shmobile: r8a7790: add SATA support
In-Reply-To: <51A103D9.4080600@cogentembedded.com>
References: <1369361184-20862-1-git-send-email-horms+renesas@verge.net.au>
 <519F72F8.1000204@cogentembedded.com>
 <20130525010309.GG4476@verge.net.au>
 <51A103D9.4080600@cogentembedded.com>
Message-ID: <20130526132517.GF11134@verge.net.au>

On Sat, May 25, 2013 at 10:32:57PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 25-05-2013 5:03, Simon Horman wrote:
> 
> >>>Add SATA clock for r8a7790 SoC (for both device tree and usual cases).
> 
> >>     I don't see where you are adding clock for device tree case.
> 
> >>>Register SATA controller as a "late" platform device on r8a7790 SoC.
> 
> >>     Does R8A7790 have these "early" and "late" lists? I guess not.
> 
> >>>Based on "ARM: mach-shmobile: r8a7779: add SATA support" by
> >>>Vladimir Barinov.
> 
> >>>Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >>>---
> >>>  arch/arm/mach-shmobile/clock-r8a7790.c |  4 ++++
> >>>  arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++
> >>>  2 files changed, 25 insertions(+)
> 
> >>>diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> >>>index b393592..3619a52 100644
> >>>--- a/arch/arm/mach-shmobile/clock-r8a7790.c
> >>>+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> >>[...]
> >>>@@ -249,6 +252,7 @@ static struct clk_lookup lookups[] = {
> >>>  	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
> >>>  	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
> >>>  	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
> >>>+	CLKDEV_DEV_ID("sata_rcar.1", &mstp_clks[MSTP814]),
> >>>  };
> >>>
> >>>  #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
> >>>diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> >>>index ed7ee24..5a2a073 100644
> >>>--- a/arch/arm/mach-shmobile/setup-r8a7790.c
> >>>+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> >>[...]
> >>>@@ -118,6 +119,25 @@ static inline void r8a7790_register_scif(int idx)
> >>>  				      sizeof(struct plat_sci_port));
> >>>  }
> 
> >>>+static __init void r8a7790_register_sata1(void)
> 
> >>    What's with SATA0?
> 
> >>>+{
> >>>+
> >>>+	struct resource res[] = {
> 
> >>    Non-static variable with an intializer? Won't this be a waste of
> >>code? Wouldn't it be better to have it static __initdata?
> 
> >Sure, if you prefer that.
> 
>    I don't know exactly what gcc will generate for the intializers
> but expect nothing particularly good. The static intialized data
> should definitely take up less space.
> 
> >>
> >>>+		DEFINE_RES_MEM_NAMED(0xee300000, 0x200000, "rcar-sata"),
> 
> >>     2 megabytes? Won't it be a waste of memory?
> 
> >2 megabytes is specified in the data sheet.
> >Do you think it is reasonable to use a smaller value?
> 
>    We used 0x2000 for R8A7779 SATA device -- it should be enough to
> cover all the registers.

Thanks for your advice, I'll see about doing the same for r8a7790.

> >>>+		DEFINE_RES_IRQ(gic_iid(106)),
> >>>+	};
> >>>+
> >>>+	struct platform_device_info pdevinfo = {
> 
> >>    Same comment about non-static initialized structure...
> 
> >>>+		.name = "sata_rcar",
> >>>+		.id = 1,
> >>>+		.res = res,
> >>>+		.num_res = ARRAY_SIZE(res),
> >>>+		.dma_mask = DMA_BIT_MASK(32),
> >>>+	};
> >>>+
> >>>+	platform_device_register_full(&pdevinfo);
> >>>+}
> >>>+
> 
> WBR, Sergei
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From horms at verge.net.au  Sun May 26 09:33:34 2013
From: horms at verge.net.au (Simon Horman)
Date: Sun, 26 May 2013 22:33:34 +0900
Subject: [PATCH v2] ARM: shmobile: BOCK-W: add Ether support
In-Reply-To: <51A14BE1.8050907@cogentembedded.com>
References: <201305170141.59791.sergei.shtylyov@cogentembedded.com>
 <20130525053007.GA9293@verge.net.au>
 <51A0FE23.4090206@cogentembedded.com>
 <20130525232257.GA24131@verge.net.au>
 <51A14BE1.8050907@cogentembedded.com>
Message-ID: <20130526133334.GH11134@verge.net.au>

On Sun, May 26, 2013 at 03:40:17AM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 05/26/2013 03:22 AM, Simon Horman wrote:
> 
> >>>>Register Ether device from bockw_init(), passing the platform data to it, adding
> >>>>only the RMII pin group to bockw_pinctrl_map[].  Although the LINK signal exists
> >>>>on the board, it's connected to the link/activity LED  output of the PHY, thus
> >>>>the link disappears and reappears after each packet. We'd be better off ignoring
> >>>>such signal and getting the link state from the PHY indirectly.
> >>>>Also, Ether has pin conflict with VIN1, so the latter is not registered when the
> >>>>'sh_eth' driver is enabled now.
> >>>>Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >>>>
> >>>>---
> >>>>The patch is atop of Simon's 'renesas.git' repo, 'renesas-next-20130515v2' tag
> >>>>and my recent yet unapplied patches.
> >>>>Note that it's compile and run time dependent on the current Linus' tree.
> >>>>Changes from the original posting:
> >>>>- refreshed the patch.
> >>>Thanks, would it be possible for you to rebase it on top of
> >>>renesas-next-20130523.
> >>    You mean to base it on this tag without any intervening patches
> >>(it is now on top of my patch series)? Anyway, I'll rebase my whole
> >>series on this tag as I have time (I'm now working with the SATA
> >>driver to try to add to it NCQ support and fixing errors I encounter
> >>on the way).
> >In general I would prefer for you to post patches that are based on my tree
> >without any intervening patches as it makes it significantly easier for me
> >to apply them.
> 
>    It's just that I've accumulated a significant queue of patches pending
> merge to you tree. I'll reshuffle the series, if you consider this patch
> more urgent than USB/VIN stuff.

I'm happy for you to set the priorities for your patches as you see fit.


From liuj97 at gmail.com  Sun May 26 09:38:29 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Sun, 26 May 2013 21:38:29 +0800
Subject: [PATCH v8,
 part3 01/14] mm: change signature of free_reserved_area() to fix
 building warnings
In-Reply-To: <1369575522-26405-1-git-send-email-jiang.liu@huawei.com>
References: <1369575522-26405-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1369575522-26405-2-git-send-email-jiang.liu@huawei.com>

Change signature of free_reserved_area() according to Russell King's
suggestion to fix following build warnings:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
  free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
  ^
In file included from include/linux/mman.h:4:0,
                 from arch/arm/mm/init.c:15:
include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
 extern unsigned long free_reserved_area(unsigned long start, unsigned long end,

   mm/page_alloc.c: In function 'free_reserved_area':
>> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
   In file included from arch/mips/include/asm/page.h:49:0,
                    from include/linux/mmzone.h:20,
                    from include/linux/gfp.h:4,
                    from include/linux/mm.h:8,
                    from mm/page_alloc.c:18:
   arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
   mm/page_alloc.c: In function 'free_area_init_nodes':
   mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]

Also address some minor code review comments.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Reported-by: Arnd Bergmann <arnd at arndb.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-mm at kvack.org
---
 arch/alpha/kernel/sys_nautilus.c |  4 ++--
 arch/alpha/mm/init.c             |  2 +-
 arch/arc/mm/init.c               |  2 +-
 arch/arm/mm/init.c               |  2 +-
 arch/arm64/mm/init.c             |  2 +-
 arch/avr32/mm/init.c             |  2 +-
 arch/blackfin/mm/init.c          |  2 +-
 arch/c6x/mm/init.c               |  2 +-
 arch/frv/mm/init.c               |  2 +-
 arch/h8300/mm/init.c             |  2 +-
 arch/ia64/mm/init.c              |  3 +--
 arch/m32r/mm/init.c              |  2 +-
 arch/m68k/mm/init.c              |  2 +-
 arch/metag/mm/init.c             |  3 ++-
 arch/microblaze/mm/init.c        |  2 +-
 arch/mips/mm/init.c              |  3 ++-
 arch/mn10300/mm/init.c           |  3 ++-
 arch/openrisc/mm/init.c          |  2 +-
 arch/parisc/mm/init.c            |  3 ++-
 arch/powerpc/kernel/kvm.c        |  2 +-
 arch/powerpc/mm/mem.c            |  2 +-
 arch/s390/mm/init.c              |  3 ++-
 arch/score/mm/init.c             |  3 ++-
 arch/sh/mm/init.c                |  2 +-
 arch/sparc/mm/init_32.c          |  4 ++--
 arch/sparc/mm/init_64.c          |  4 ++--
 arch/um/kernel/mem.c             |  2 +-
 arch/unicore32/mm/init.c         |  2 +-
 arch/xtensa/mm/init.c            |  2 +-
 include/linux/mm.h               |  5 ++---
 mm/page_alloc.c                  | 19 ++++++++++---------
 31 files changed, 50 insertions(+), 45 deletions(-)

diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 1d4aabf..891bd27 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -238,8 +238,8 @@ nautilus_init_pci(void)
 	if (pci_mem < memtop)
 		memtop = pci_mem;
 	if (memtop > alpha_mv.min_mem_address) {
-		free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
-				   (unsigned long)__va(memtop), 0, NULL);
+		free_reserved_area(__va(alpha_mv.min_mem_address),
+				   __va(memtop), 0, NULL);
 		printk("nautilus_init_pci: %ldk freed\n",
 			(memtop - alpha_mv.min_mem_address) >> 10);
 	}
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 0ba85ee..d54848d 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -326,6 +326,6 @@ free_initmem(void)
 void
 free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 4a17736..dce02e4 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -152,7 +152,7 @@ void __init_refok free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc0..59d6f76 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -744,7 +744,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index f497ca7..6041e40 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -398,7 +398,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 	}
 }
 
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index e66e840..5a79fa0 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -154,6 +154,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 82d01a7..8e9eab2 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -133,7 +133,7 @@ void __init mem_init(void)
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
 #ifndef CONFIG_MPU
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 #endif
 }
 #endif
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
index a9fcd89..97914e5 100644
--- a/arch/c6x/mm/init.c
+++ b/arch/c6x/mm/init.c
@@ -77,7 +77,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index dee354f..a67f3a5 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -173,6 +173,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 } /* end free_initrd_mem() */
 #endif
diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c
index ff349d7..57e03c5 100644
--- a/arch/h8300/mm/init.c
+++ b/arch/h8300/mm/init.c
@@ -161,7 +161,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index d1fe4b4..da568c2 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -154,8 +154,7 @@ ia64_init_addr_space (void)
 void
 free_initmem (void)
 {
-	free_reserved_area((unsigned long)ia64_imva(__init_begin),
-			   (unsigned long)ia64_imva(__init_end),
+	free_reserved_area(ia64_imva(__init_begin), ia64_imva(__init_end),
 			   0, "unused kernel");
 }
 
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index ab4cbce..d80412d 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -191,6 +191,6 @@ void free_initmem(void)
  *======================================================================*/
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 1af2ca3..95de725 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -202,6 +202,6 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index d05b845..5e2238d 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -414,7 +414,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index b38ae3a..d7b8ada 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -235,7 +235,7 @@ void __init setup_memory(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 9b973e0..268f2a9 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -440,7 +440,8 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 5a8ace6..e19049d 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -152,6 +152,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index b3cbc67..ab11332 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -261,7 +261,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 1c96564..8fa4183 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -1101,6 +1101,7 @@ void flush_tlb_all(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, 0, "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end, 0,
+					    "initrd");
 }
 #endif
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 6782221..5e4830a 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -756,7 +756,7 @@ static __init void kvm_free_tmp(void)
 	end = (ulong)&kvm_tmp[ARRAY_SIZE(kvm_tmp)] & PAGE_MASK;
 
 	/* Free the tmp space we don't need */
-	free_reserved_area(start, end, 0, NULL);
+	free_reserved_area((void *)start, (void *)end, 0, NULL);
 }
 
 static int __init kvm_guest_init(void)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 0988a26..347c5b1 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -407,7 +407,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 89ebae4..0878c89 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -172,7 +172,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index d8f988a..3d79ecb 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -110,7 +110,8 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+			   "initrd");
 }
 #endif
 
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 20f9ead..b892a9b 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -505,7 +505,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index af472cf..d5f9c02 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -372,8 +372,8 @@ void free_initmem (void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index a717199..a54cdcd 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2124,8 +2124,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-					    "initrd");
+	num_physpages += free_reserved_area((void *)start, (void *)end,
+					    POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 9df292b..2aa7a24 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -244,7 +244,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	free_reserved_area(start, end, 0, "initrd");
+	free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 63df12d..220755c 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -486,7 +486,7 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index bba125b..4d658ef 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -214,7 +214,7 @@ extern int initrd_is_mapped;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (initrd_is_mapped)
-		free_reserved_area(start, end, 0, "initrd");
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 #endif
 
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e0c8528..771769f 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1307,7 +1307,7 @@ extern void free_initmem(void);
  * "poison" if it's non-zero.
  * Return pages freed into the buddy system.
  */
-extern unsigned long free_reserved_area(unsigned long start, unsigned long end,
+extern unsigned long free_reserved_area(void *start, void *end,
 					int poison, char *s);
 #ifdef	CONFIG_HIGHMEM
 /*
@@ -1351,8 +1351,7 @@ static inline unsigned long free_initmem_default(int poison)
 {
 	extern char __init_begin[], __init_end[];
 
-	return free_reserved_area(PAGE_ALIGN((unsigned long)&__init_begin) ,
-				  ((unsigned long)&__init_end) & PAGE_MASK,
+	return free_reserved_area(&__init_begin, &__init_end,
 				  poison, "unused kernel");
 }
 
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 7c39893..39f66e7 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5231,25 +5231,26 @@ early_param("movablecore", cmdline_parse_movablecore);
 
 #endif /* CONFIG_HAVE_MEMBLOCK_NODE_MAP */
 
-unsigned long free_reserved_area(unsigned long start, unsigned long end,
-				 int poison, char *s)
+unsigned long free_reserved_area(void *start, void *end, int poison, char *s)
 {
-	unsigned long pages, pos;
+	void *pos;
+	unsigned long pages = 0;
 
-	pos = start = PAGE_ALIGN(start);
-	end &= PAGE_MASK;
-	for (pages = 0; pos < end; pos += PAGE_SIZE, pages++) {
+	start = (void *)PAGE_ALIGN((unsigned long)start);
+	end = (void *)((unsigned long)end & PAGE_MASK);
+	for (pos = start; pos < end; pos += PAGE_SIZE, pages++) {
 		if (poison)
-			memset((void *)pos, poison, PAGE_SIZE);
-		free_reserved_page(virt_to_page((void *)pos));
+			memset(pos, poison, PAGE_SIZE);
+		free_reserved_page(virt_to_page(pos));
 	}
 
 	if (pages && s)
-		pr_info("Freeing %s memory: %ldK (%lx - %lx)\n",
+		pr_info("Freeing %s memory: %ldK (%p - %p)\n",
 			s, pages << (PAGE_SHIFT - 10), start, end);
 
 	return pages;
 }
+EXPORT_SYMBOL(free_reserved_area);
 
 #ifdef	CONFIG_HIGHMEM
 void free_highmem_page(struct page *page)
-- 
1.8.1.2



From liuj97 at gmail.com  Sun May 26 09:38:31 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Sun, 26 May 2013 21:38:31 +0800
Subject: [PATCH v8, part3 03/14] mm/ARM64: kill poison_init_mem()
In-Reply-To: <1369575522-26405-1-git-send-email-jiang.liu@huawei.com>
References: <1369575522-26405-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1369575522-26405-4-git-send-email-jiang.liu@huawei.com>

Use free_reserved_area() to poison initmem memory pages and kill
poison_init_mem() on ARM64.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm64/mm/init.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 997c634..a398eb9 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -197,14 +197,6 @@ void __init bootmem_init(void)
 	max_pfn = max_low_pfn = max;
 }
 
-/*
- * Poison init memory with an undefined instruction (0x0).
- */
-static inline void poison_init_mem(void *s, size_t count)
-{
-	memset(s, 0, count);
-}
-
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
 static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -386,8 +378,7 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-	poison_init_mem(__init_begin, __init_end - __init_begin);
-	free_initmem_default(-1);
+	free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -396,10 +387,8 @@ static int keep_initrd;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-	if (!keep_initrd) {
-		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-		free_reserved_area((void *)start, (void *)end, -1, "initrd");
-	}
+	if (!keep_initrd)
+		free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
-- 
1.8.1.2



From maxime.ripard at free-electrons.com  Sun May 26 10:16:59 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 16:16:59 +0200
Subject: [GIT PULL] ARM SoC cleanups for 3.11
Message-ID: <20130526141659.GA9394@lukather>

Hi Arnd, Olof,

Here the pull request with the cleanup patches that I sent a few weeks
ago about init_irq and map_io cleanups for platforms that were using the
generic functions for both these callbacks.

Please consider pulling it.

Thanks,
Maxime

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://github.com/mripard/linux.git tags/arm-soc-cleanups-for-3.11

for you to fetch changes up to 442f15083eb25229fb95820bced8bea70298a34b:

  ARM: sunxi: Remove the .map_io function declaration (2013-05-24 10:24:43 +0200)

----------------------------------------------------------------
Cleanups in various machine definitions
  - Patches to remove the .init_irq definition when using irqchip_init
  - Make the ARM core code call debug_ll_io_init when no map_io callback is
    declared
  - Remove the .map_io definition in the various machines using it

----------------------------------------------------------------
Maxime Ripard (10):
      ARM: nomadik: Remove init_irq declaration in machine description
      ARM: spear: Remove init_irq declaration in machine description
      ARM: sirf: Remove init_irq declaration in machine description
      ARM: vexpress: Remove init_irq declaration in machine description
      ARM: virt: Remove init_irq declaration in machine description
      ARM: vt8500: Remove init_irq declaration in machine description
      ARM: mmu: Call debug_ll_io_init if no map_io function is specified
      ARM: highbank: remove the .map_io declaration
      ARM: mxs: remove the .map_io declaration
      ARM: sunxi: Remove the .map_io function declaration

 arch/arm/mach-highbank/highbank.c |  1 -
 arch/arm/mach-mxs/mach-mxs.c      |  1 -
 arch/arm/mach-nomadik/cpu-8815.c  |  2 --
 arch/arm/mach-prima2/common.c     |  4 ----
 arch/arm/mach-spear/spear1310.c   |  2 --
 arch/arm/mach-spear/spear1340.c   |  2 --
 arch/arm/mach-spear/spear300.c    |  2 --
 arch/arm/mach-spear/spear310.c    |  2 --
 arch/arm/mach-spear/spear320.c    |  2 --
 arch/arm/mach-spear/spear6xx.c    |  2 --
 arch/arm/mach-sunxi/sunxi.c       | 17 -----------------
 arch/arm/mach-sunxi/sunxi.h       | 20 --------------------
 arch/arm/mach-vexpress/v2m.c      |  2 --
 arch/arm/mach-virt/virt.c         |  2 --
 arch/arm/mach-vt8500/vt8500.c     |  2 --
 arch/arm/mm/mmu.c                 |  2 ++
 16 files changed, 2 insertions(+), 63 deletions(-)
 delete mode 100644 arch/arm/mach-sunxi/sunxi.h

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From mst at redhat.com  Sun May 26 10:30:42 2013
From: mst at redhat.com (Michael S. Tsirkin)
Date: Sun, 26 May 2013 17:30:42 +0300
Subject: [PATCH v3-resend 02/11] arm64: uaccess s/might_sleep/might_fault/
In-Reply-To: <1369575487-26176-1-git-send-email-mst@redhat.com>
References: <1369575487-26176-1-git-send-email-mst@redhat.com>
Message-ID: <1369577426-26721-2-git-send-email-mst@redhat.com>

The only reason uaccess routines might sleep
is if they fault. Make this explicit.

Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/uaccess.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 008f848..edb3d5c 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -166,7 +166,7 @@ do {									\
 
 #define get_user(x, ptr)						\
 ({									\
-	might_sleep();							\
+	might_fault();							\
 	access_ok(VERIFY_READ, (ptr), sizeof(*(ptr))) ?			\
 		__get_user((x), (ptr)) :				\
 		((x) = 0, -EFAULT);					\
@@ -227,7 +227,7 @@ do {									\
 
 #define put_user(x, ptr)						\
 ({									\
-	might_sleep();							\
+	might_fault();							\
 	access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) ?		\
 		__put_user((x), (ptr)) :				\
 		-EFAULT;						\
-- 
MST


From tomasz.figa at gmail.com  Sun May 26 10:38:19 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 26 May 2013 16:38:19 +0200
Subject: [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <24460034.7lWPC5EJAp@flatron>

Hi Maxime,

On Sunday 26 of May 2013 12:20:37 Maxime Ripard wrote:
> This patch implements a basic driver for the I2C host driver found on
> the Allwinner A10, A13 and A31 SoCs.
> 
> Notable missing feature is 10-bit addressing.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
>  drivers/i2c/busses/Kconfig                         |  10 +
>  drivers/i2c/busses/Makefile                        |   1 +
>  drivers/i2c/busses/i2c-sunxi.c                     | 455
> +++++++++++++++++++++ 4 files changed, 485 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
>  create mode 100644 drivers/i2c/busses/i2c-sunxi.c
> 
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
> b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt new file mode
> 100644
> index 0000000..40c16d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
> @@ -0,0 +1,19 @@
> +Allwinner SoC I2C controller
> +
> +Required properties:
> +- compatible : Should be "allwinner,sun4i-i2c".
> +- reg: Should contain register location and length.
> +- interrupts: Should contain interrupt.
> +- clocks : The parent clock feeding the I2C controller.
> +
> +Recommended properties:
> +- clock-frequency : desired I2C bus clock frequency in Hz.
> +
> +Example:
> +i2c0: i2c at 01c2ac00 {
> +	compatible = "allwinner,sun4i-i2c";
> +	reg = <0x01c2ac00 0x400>;
> +	interrupts = <7>;
> +	clocks = <&apb1_gates 0>;
> +	clock-frequency = <100000>;
> +};
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 631736e..1df8ba1 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -706,6 +706,16 @@ config I2C_STU300
>  	  This driver can also be built as a module. If so, the module
>  	  will be called i2c-stu300.
> 
> +config I2C_SUNXI
> +	tristate "Allwinner A1X I2C controller"
> +	depends on ARCH_SUNXI
> +	help
> +	  If you say yes to this option, support will be included for the
> +	  I2C controller embedded in Allwinner A1X SoCs.
> +
> +	  This driver can also be built as a module. If so, the module
> +	  will be called i2c-sunxi.
> +
>  config I2C_TEGRA
>  	tristate "NVIDIA Tegra internal I2C controller"
>  	depends on ARCH_TEGRA
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 8f4fc23..7225818 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
>  obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
>  obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
>  obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
> +obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
>  obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
>  obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
>  obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
> diff --git a/drivers/i2c/busses/i2c-sunxi.c
> b/drivers/i2c/busses/i2c-sunxi.c new file mode 100644
> index 0000000..5d93f26
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-sunxi.c
> @@ -0,0 +1,455 @@
> +/*
> + * Allwinner A1X SoCs i2c controller driver.
> + *
> + * Copyright (C) 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard at free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +
> +#define SUNXI_I2C_ADDR_REG		(0x00)
> +#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
> +#define SUNXI_I2C_XADDR_REG		(0x04)
> +#define SUNXI_I2C_DATA_REG		(0x08)
> +#define SUNXI_I2C_CNTR_REG		(0x0c)
> +#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
> +#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
> +#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
> +#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
> +#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
> +#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
> +#define SUNXI_I2C_STA_REG		(0x10)
> +#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
> +#define SUNXI_I2C_STA_START			(0x08)
> +#define SUNXI_I2C_STA_START_REPEAT		(0x10)
> +#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
> +#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
> +#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
> +#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
> +#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
> +#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
> +#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
> +#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
> +#define SUNXI_I2C_CCR_REG		(0x14)
> +#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
> +#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
> +#define SUNXI_I2C_SRST_REG		(0x18)
> +#define SUNXI_I2C_SRST_RESET			BIT(0)
> +#define SUNXI_I2C_EFR_REG		(0x1c)
> +#define SUNXI_I2C_LCR_REG		(0x20)
> +
> +#define SUNXI_I2C_DONE			BIT(0)
> +#define SUNXI_I2C_ERROR			BIT(1)
> +#define SUNXI_I2C_NAK			BIT(2)
> +#define SUNXI_I2C_BUS_ERROR		BIT(3)
> +
> +struct sunxi_i2c_dev {
> +	struct i2c_adapter	adapter;
> +	struct clk		*clk;
> +	struct device		*dev;
> +	struct completion	completion;
> +	unsigned int		irq;
> +	void __iomem		*membase;
> +
> +	struct i2c_msg		*msg_cur;
> +	u8			*msg_buf;
> +	size_t			msg_buf_remaining;
> +	unsigned int		msg_err;
> +};
> +
> +static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8
> value) +{
> +	writel(value, i2c_dev->membase + reg);
> +}
> +
> +static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
> +{
> +	return readl(i2c_dev->membase + reg);
> +}
> +
> +/*
> + * This is where all the magic happens. The I2C controller works as a
> + * state machine, each state being a step in the i2c protocol, with
> + * the controller sending an interrupt at each state transition.
> + *
> + * The state we're in is stored in a register, which leads to a pretty
> + * huge switch statement, all of this in the interrupt handler...
> + */
> +static irqreturn_t sunxi_i2c_handler(int irq, void *data)
> +{
> +	struct sunxi_i2c_dev *i2c_dev = (struct sunxi_i2c_dev *)data;
> +	u32 status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	u32 addr, val;
> +
> +	if (!(status & SUNXI_I2C_CNTR_INT_FLAG))
> +		return IRQ_NONE;
> +
> +	/* Read the current state we're in */
> +	status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_STA_REG);
> +
> +	switch (status & 0xff) {
> +	/* Start condition has been transmitted */
> +	case SUNXI_I2C_STA_START:
> +	/* A repeated start condition has been transmitted */
> +	case SUNXI_I2C_STA_START_REPEAT:
> +		addr = SUNXI_I2C_ADDR_ADDR(i2c_dev->msg_cur->addr);
> +
> +		if (i2c_dev->msg_cur->flags & I2C_M_RD)
> +			addr |= 1;
> +
> +		sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG, addr);
> +		break;
> +
> +	/*
> +	 * Address + Write bit have been transmitted, ACK has not been
> +	 * received. It should be treated the same way than when a
> +	 * data byte has been sent and no ACK has been received, and
> +	 * we fall through to the next case in our switch.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_WADDR_NAK:
> +	/*
> +	 * Data byte has been transmitted, ACK has not been
> +	 * received. If we don't care about the NAKs, we just treat
> +	 * this case as if an ACK would have been received, and
> +	 * we fall through to the next case in our switch.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_DATA_SENT_NAK:
> +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> +			goto out;
> +		}
> +
> +	/*
> +	 * Address + Write bit have been transmitted, ACK has been
> +	 * received. In the I2C protocol sequence, we are in exactly
> +	 * the same case than when we sent some data bytes and there
> +	 * is still some data to be sent, and we fall through to the
> +	 * next case in our switch.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_WADDR_ACK:
> +	/* Data byte has been transmitted, ACK has been received */
> +	case SUNXI_I2C_STA_MASTER_DATA_SENT_ACK:
> +		if (i2c_dev->msg_buf_remaining) {
> +			sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG,
> +					*i2c_dev->msg_buf);
> +			i2c_dev->msg_buf++;
> +			i2c_dev->msg_buf_remaining--;
> +			break;
> +		}
> +
> +		if (i2c_dev->msg_buf_remaining == 0) {
> +			i2c_dev->msg_err = SUNXI_I2C_DONE;
> +			goto out;
> +		}
> +
> +		break;
> +
> +	/*
> +	 * Address + Read bit have been transmitted, ACK has not been
> +	 * received. If we don't care about the NAKs, we just treat
> +	 * this case as if an ACK would have been received, and fall
> +	 * through to the next case.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
> +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> +			goto out;
> +		}

I meant something more like:

+
+	/* Intentional fall through. */

This is enough to let the reader know that there is no break missing here 
and you can keep those nice short state descriptions from v1.

> +
> +	/*
> +	 * Address + Read bit have been transmitted, ACK has been
> +	 * received.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_RADDR_ACK:
> +		/*
> +		 * We only need to send the ACK for the all the bytes
> +		 * but the last one
> +		 */
> +		if (i2c_dev->msg_buf_remaining > 1) {
> +			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +					val | SUNXI_I2C_CNTR_ASSERT_ACK);
> +		}
> +
> +		break;
> +
> +	/*
> +	 * Data byte has been received, ACK has not been
> +	 * transmitted. If we don't care about the NAK and that some
> +	 * data have still to be received, we fall through to the next
> +	 * case in our switch.
> +	 */
> +	case SUNXI_I2C_STA_MASTER_DATA_RECV_NAK:
> +		if (i2c_dev->msg_buf_remaining == 1) {
> +			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG);
> +			*i2c_dev->msg_buf = val & 0xff;
> +			i2c_dev->msg_buf_remaining--;
> +			i2c_dev->msg_err = SUNXI_I2C_DONE;
> +			goto out;
> +		}
> +
> +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> +			goto out;
> +		}
> +
> +	/* Data byte has been received, ACK has been transmitted */
> +	case SUNXI_I2C_STA_MASTER_DATA_RECV_ACK:
> +		val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG) & 0xff;
> +		*i2c_dev->msg_buf = val;
> +		i2c_dev->msg_buf++;
> +		i2c_dev->msg_buf_remaining--;
> +
> +		/* If there's only one byte left, disable the ACK */
> +		if (i2c_dev->msg_buf_remaining == 1) {
> +			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +					val & ~SUNXI_I2C_CNTR_ASSERT_ACK);
> +
> +		};
> +
> +		break;
> +
> +	case SUNXI_I2C_STA_BUS_ERROR:
> +		i2c_dev->msg_err = SUNXI_I2C_BUS_ERROR;
> +		goto out;
> +
> +	default:
> +		i2c_dev->msg_err = SUNXI_I2C_ERROR;
> +		goto out;
> +	}
> +
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			val & ~SUNXI_I2C_CNTR_INT_FLAG);
> +
> +	return IRQ_HANDLED;
> +
> +out:
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			val | SUNXI_I2C_CNTR_MASTER_STOP);
> +
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			val & ~SUNXI_I2C_CNTR_INT_FLAG);
> +
> +	complete(&i2c_dev->completion);
> +	return IRQ_HANDLED;
> +}
> +
> +static int sunxi_i2c_xfer_msg(struct sunxi_i2c_dev *i2c_dev,
> +			      struct i2c_msg *msg)
> +{
> +	int time_left;
> +	u32 val;
> +
> +	i2c_dev->msg_cur = msg;
> +	i2c_dev->msg_buf = msg->buf;
> +	i2c_dev->msg_buf_remaining = msg->len;
> +	i2c_dev->msg_err = 0;
> +	INIT_COMPLETION(i2c_dev->completion);
> +
> +	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
> +	val |= SUNXI_I2C_CNTR_MASTER_START;
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG, val);
> +
> +	time_left = wait_for_completion_timeout(&i2c_dev->completion,
> +						i2c_dev->adapter.timeout);
> +	if (!time_left) {
> +		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	if (likely(i2c_dev->msg_err == SUNXI_I2C_DONE))
> +		return 0;
> +
> +	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev-
>msg_err);
> +
> +	return -EIO;
> +}
> +
> +static int sunxi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
> *msgs, +			  int num)
> +{
> +	struct sunxi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> +	int i, ret;
> +
> +	for (i = 0; i < num; i++) {
> +		ret = sunxi_i2c_xfer_msg(i2c_dev, &msgs[i]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return i;
> +}
> +
> +static u32 sunxi_i2c_func(struct i2c_adapter *adap)
> +{
> +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm sunxi_i2c_algo = {
> +	.master_xfer	= sunxi_i2c_xfer,
> +	.functionality	= sunxi_i2c_func,
> +};
> +
> +static int sunxi_i2c_probe(struct platform_device *pdev)
> +{
> +	struct sunxi_i2c_dev *i2c_dev;
> +	struct device_node *np;
> +	u32 freq, div_m, div_n;
> +	struct resource res;

	struct resource *res;

and then...

> +	int ret;
> +
> +	np = pdev->dev.of_node;
> +	if (!np)
> +		return -EINVAL;
> +
> +	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
> +	if (!i2c_dev)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, i2c_dev);
> +	i2c_dev->dev = &pdev->dev;
> +
> +	init_completion(&i2c_dev->completion);
> +
> +	ret = of_address_to_resource(np, 0, &res);
> +	if (ret) {
> +		dev_err(&pdev->dev, "could not get IO memory\n");
> +		return ret;
> +	}
> +
> +	i2c_dev->membase = devm_ioremap_resource(&pdev->dev, &res);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c_dev->membase = devm_ioremap_resource(&pdev->dev, res);

This way you can save yourself from parsing device tree again, one error 
check and few lines of code. Remember that of_platform_populate() creates 
all the resources of platform_devices based on reg and interrupts 
properties, so there is no point in wasting this effort in drivers by 
parsing them manually again.

> +	if (IS_ERR(i2c_dev->membase))
> +		return PTR_ERR(i2c_dev->membase);
> +
> +	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(i2c_dev->clk))
> +		return PTR_ERR(i2c_dev->clk);
> +
> +	clk_prepare_enable(i2c_dev->clk);
> +
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_SRST_REG, 
SUNXI_I2C_SRST_RESET);
> +
> +	ret = of_property_read_u32(np, "clock-frequency", &freq);
> +	if (ret < 0) {
> +		dev_warn(&pdev->dev, "Could not read clock-frequency 
property\n");
> +		freq = 100000;
> +	}
> +
> +	/*
> +	 * Set the clock dividers. we don't need to be super smart
> +	 * here, the datasheet defines the value of the factors for
> +	 * the two supported frequencies, and only the M factor
> +	 * changes between 100kHz and 400kHz.
> +	 *
> +	 * The bus clock is generated from the parent clock with two
> +	 * different dividers. It is generated as such:
> +	 *     f0 = fclk / (2 ^ DIV_N)
> +	 *     fbus = f0 / (10 * (DIV_M + 1))
> +	 *
> +	 * With DIV_N being on 3 bits, and DIV_M on 4 bits.
> +	 * So DIV_N < 8, and DIV_M < 16.
> +	 *
> +	 * However, we can generate both the supported frequencies
> +	 * with f0 = 12MHz, and only change M to get back on our
> +	 * feet.
> +	 */
> +	div_n = ilog2(clk_get_rate(i2c_dev->clk) / 12000000);
> +	if (freq == 100000)
> +		div_m = 11;
> +	else if (freq == 400000)
> +		div_m = 2;
> +	else {
> +		dev_err(&pdev->dev, "Unsupported bus frequency\n");
> +		ret = -EINVAL;
> +		goto out_clk_dis;
> +	}
> +
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CCR_REG,
> +			SUNXI_I2C_CCR_DIV_N(div_n) | 
SUNXI_I2C_CCR_DIV_M(div_m));
> +
> +	i2c_dev->irq = irq_of_parse_and_map(np, 0);

You don't have to go through all the parsing again here, because the 
interrupt property is already being parsed by of_platform_populate() 
creating all necessary MEM and IRQ resources.

As I suggested in review of v1, you can simply use

	i2c_dev->irq = platform_get_irq(pdev, 0);

which will just fetch the interrupt number from the resource set created 
by of_platform_populate(). Just remember to change irq field of i2c_dev to 
signed int and the following check to <= 0.

Best regards,
Tomasz

> +	if (!i2c_dev->irq) {
> +		dev_err(&pdev->dev, "No IRQ resource\n");
> +		ret = -ENODEV;
> +		goto out_clk_dis;
> +	}
> +
> +	ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 
sunxi_i2c_handler,
> +			       IRQF_SHARED, dev_name(&pdev->dev), 
i2c_dev);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not request IRQ\n");
> +		goto out_clk_dis;
> +	}
> +
> +	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
> +
> +	i2c_dev->adapter.owner = THIS_MODULE;
> +	strlcpy(i2c_dev->adapter.name, "sunxi I2C adapter",
> +		sizeof(i2c_dev->adapter.name));
> +	i2c_dev->adapter.algo = &sunxi_i2c_algo;
> +	i2c_dev->adapter.dev.parent = &pdev->dev;
> +
> +	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
> +			SUNXI_I2C_CNTR_BUS_ENABLE | 
SUNXI_I2C_CNTR_INT_ENABLE);
> +
> +	ret = i2c_add_adapter(&i2c_dev->adapter);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to register i2c adapter\n");
> +		goto out_clk_dis;
> +	}
> +
> +	return 0;
> +
> +out_clk_dis:
> +	clk_disable_unprepare(i2c_dev->clk);
> +	return ret;
> +}
> +
> +
> +static int sunxi_i2c_remove(struct platform_device *pdev)
> +{
> +	struct sunxi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
> +
> +	i2c_del_adapter(&i2c_dev->adapter);
> +	clk_disable_unprepare(i2c_dev->clk);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sunxi_i2c_of_match[] = {
> +	{ .compatible = "allwinner,sun4i-i2c" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_i2c_of_match);
> +
> +static struct platform_driver sunxi_i2c_driver = {
> +	.probe		= sunxi_i2c_probe,
> +	.remove		= sunxi_i2c_remove,
> +	.driver		= {
> +		.name	= "i2c-sunxi",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = sunxi_i2c_of_match,
> +	},
> +};
> +module_platform_driver(sunxi_i2c_driver);
> +
> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com");
> +MODULE_DESCRIPTION("Allwinner A1X I2C bus adapter");
> +MODULE_LICENSE("GPL");


From tomasz.figa at gmail.com  Sun May 26 10:44:43 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Sun, 26 May 2013 16:44:43 +0200
Subject: [linux-sunxi] [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c
 driver
In-Reply-To: <51A1E9AA.4000008@schinagl.nl>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
 <51A1E9AA.4000008@schinagl.nl>
Message-ID: <1781939.MrE9Xthq6W@flatron>

Hi Oliver,

On Sunday 26 of May 2013 12:53:30 Oliver Schinagl wrote:
> Just replying because I want to understand certain choices you make,
> absolutely not questioning your code!
> 
> On 05/26/13 12:20, Maxime Ripard wrote:
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/completion.h>
> 
> You forgot to add #include <linux/bitops.h> for BIT()
> 
> > +
> > +static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg,
> > u8 value) +{
> > +	writel(value, i2c_dev->membase + reg);
> 
> Why writel? and why without (u32)value? I thought iowrite* where the
> preferred calls and in this case, wouldn't we want writeb since value is
> u8?

Regs in ARM world are usually 32-bit wide and memory mapped, so you use 
writel for them. I believe it is the case here as well.

> > +}
> > +
> > +static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
> > +{
> > +	return readl(i2c_dev->membase + reg);
> 
> And here, readl does match the return of u32, but aren't we always
> reading 8 bits since the TWI Data Register only uses the first 8 bits?
> So wouldn't we want to return u8 and readb?
> 

Ditto. Even if only least significant 8 bits are used, the register is 32-
bit wide, so 32-bit accessor should be used. (Assuming that my previous 
comment holds true in case of this IP.)

> > +static int sunxi_i2c_probe(struct platform_device *pdev)
> > +{
> > +	struct sunxi_i2c_dev *i2c_dev;
> > +	struct device_node *np;
> > +	u32 freq, div_m, div_n;
> > +	struct resource res;
> 
> I feel stupid for questioning this, since it only shows my lack of
> knowledge, but
> If you declare all the memory here, isn't all the data lost after
> exiting the _probe function? we pass a pointer to this memory in the
> of_address_to_resource() function so that fills it, right?
> 
> Or does after devm_ioremap_resource it no longer matter, since that
> function got what it needed and useless after?
> 
> Just asking because of the wdt driver and possibly mine that you told us
> to change.

In this case struct resource is just used as a container to pass base 
address and size of area to be mapped to devm_ioremap_resource() in. It 
isn't used anymore after the function returns.

> Sorry for asking (again) maybe very obvious things. Just trying to
> learn.

No problem.

I can recommend you a great tool to browse through Linux sources:
http://lxr.free-electrons.com/source/lib/devres.c?a=arm#L107

It really helps looking up in code things that you aren't sure.

Best regards,
Tomasz



From upshead at nvr.ru  Sun May 26 09:49:39 2013
From: upshead at nvr.ru (musfhd)
Date: Sun, 26 May 2013 16:49:39 +0300
Subject: =?koi8-r?B?wsXa1dDSxd7Oz8Ug0sXbxc7YxSDEzNEgzMDC2cgg18Hb?=
 =?koi8-r?B?ycgg18/Q0s/TycvP1w==?=
Message-ID: <22306277.20130526172100@nvr.ru>

=D0=D2=C5=C4=CF=C2=D2=CF =D0=D2=CF=DB=D5 =CE=C1 =CE=C1=DB =D3=C1=CA=D4. =F7=
=C1=CD =D0=CF=CC=C0=C2=C9=D4=D3=D1 =D4=CF =D2=CF=D7=CE=CF =F7=D9 =CE=C1 =CE=
=C5=CD =D5=D7=C9=C4=C9=D4=C5. http://goo.gl/JzXkG?/EcOkY


From plagnioj at jcrosoft.com  Sun May 26 11:30:37 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 17:30:37 +0200
Subject: [PATCH 0/5] ARM: at91: Calao USB-A926x switch completyl to dt and
 drop board file
Message-ID: <20130526153037.GQ24476@game.jcrosoft.org>

Hi,

	The Follwing patch serie finish to swtich the Calao USB-A926x to DT
	and drop the board file.

	This is the first boards to be drop on at91

The following changes since commit 24577c1b3ebf3eab6465bb112a6265e87400163e:

  ARM: at91: dt: sam9260: add i2c gpio pinctrl (2013-05-26 16:56:39 +0800)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git j/for-3.11-calao-dt

for you to fetch changes up to c3ea1d2cc2f543ee0646a75890e1a7be5dd82c0b:

  ARM: at91: drop non DT: Calao USB-A96x (2013-05-26 23:32:23 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (5):
      ARM: at91: dt: usb-a9260: update shutdown controller
      ARM: at91: dt: usb-a9263: update shutdown controller
      ARM: at91: dt: usb-a9263: add dataflash support
      ARM: at91: dt: add Calao USB-A9G20 low power version
      ARM: at91: drop non DT: Calao USB-A96x

 arch/arm/boot/dts/Makefile                  |    1 +
 arch/arm/boot/dts/usb_a9260.dts             |    9 ++++++
 arch/arm/boot/dts/usb_a9263.dts             |   14 +++++++++
 arch/arm/boot/dts/usb_a9g20.dts             |   18 +----------
 arch/arm/boot/dts/usb_a9g20_common.dtsi     |   27 ++++++++++++++++
 arch/arm/boot/dts/usb_a9g20_lpw.dts         |   31 ++++++++++++++++++
 arch/arm/configs/at91_dt_defconfig          |    2 ++
 arch/arm/configs/at91sam9260_9g20_defconfig |    1 -
 arch/arm/configs/at91sam9263_defconfig      |    1 -
 arch/arm/mach-at91/Kconfig.non_dt           |   19 -----------
 arch/arm/mach-at91/Makefile                 |    3 --
 arch/arm/mach-at91/board-usb-a926x.c        |  384 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 12 files changed, 85 insertions(+), 425 deletions(-)
 create mode 100644 arch/arm/boot/dts/usb_a9g20_common.dtsi
 create mode 100644 arch/arm/boot/dts/usb_a9g20_lpw.dts
 delete mode 100644 arch/arm/mach-at91/board-usb-a926x.c

Best Regards,
J.


From plagnioj at jcrosoft.com  Sun May 26 11:33:39 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 17:33:39 +0200
Subject: [PATCH 3/5] ARM: at91: dt: usb-a9263: add dataflash support
In-Reply-To: <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130526153037.GQ24476@game.jcrosoft.org>
 <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369582421-25562-3-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: gregory hermant <gregory.hermant at calao-systems.com>
---
 arch/arm/boot/dts/usb_a9263.dts |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index e7eb9ae..290e603 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -47,6 +47,16 @@
 				status = "okay";
 			};
 
+			spi0: spi at fffa4000 {
+				cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+				mtd_dataflash at 0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					reg = <0>;
+					spi-max-frequency = <15000000>;
+				};
+			};
+
 			shdwc at fffffd10 {
 				atmel,wakeup-counter = <10>;
 				atmel,wakeup-rtt-timer;
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May 26 11:33:38 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 17:33:38 +0200
Subject: [PATCH 2/5] ARM: at91: dt: usb-a9263: update shutdown controller
In-Reply-To: <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130526153037.GQ24476@game.jcrosoft.org>
 <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369582421-25562-2-git-send-email-plagnioj@jcrosoft.com>

enable rtt and wakeup button (5 msec low)

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: gregory hermant <gregory.hermant at calao-systems.com>
---
 arch/arm/boot/dts/usb_a9263.dts |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index f8ec36c..e7eb9ae 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -47,6 +47,10 @@
 				status = "okay";
 			};
 
+			shdwc at fffffd10 {
+				atmel,wakeup-counter = <10>;
+				atmel,wakeup-rtt-timer;
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May 26 11:33:37 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 17:33:37 +0200
Subject: [PATCH 1/5] ARM: at91: dt: usb-a9260: update shutdown controller
In-Reply-To: <20130526153037.GQ24476@game.jcrosoft.org>
References: <20130526153037.GQ24476@game.jcrosoft.org>
Message-ID: <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>

enable rtt and wakeup button (5 msec low)

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: gregory hermant <gregory.hermant at calao-systems.com>
---
 arch/arm/boot/dts/usb_a9260.dts |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
index a604107..de0c24f 100644
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -20,4 +20,13 @@
 	memory {
 		reg = <0x20000000 0x4000000>;
 	};
+
+	ahb {
+		apb {
+			shdwc at fffffd10 {
+				atmel,wakeup-counter = <10>;
+				atmel,wakeup-rtt-timer;
+			};
+		};
+	};
 };
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May 26 11:33:40 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 17:33:40 +0200
Subject: [PATCH 4/5] ARM: at91: dt: add Calao USB-A9G20 low power version
In-Reply-To: <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130526153037.GQ24476@game.jcrosoft.org>
 <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369582421-25562-4-git-send-email-plagnioj@jcrosoft.com>

the low power version have a mmc-spi

eanble mmc-spi and RV3029C2 RTC in at91_dt_defconfig

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: gregory hermant <gregory.hermant at calao-systems.com>
---
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/usb_a9g20.dts                    |   18 +-----------
 .../dts/{usb_a9g20.dts => usb_a9g20_common.dtsi}   |    5 +---
 arch/arm/boot/dts/usb_a9g20_lpw.dts                |   31 ++++++++++++++++++++
 arch/arm/configs/at91_dt_defconfig                 |    2 ++
 5 files changed, 36 insertions(+), 21 deletions(-)
 copy arch/arm/boot/dts/{usb_a9g20.dts => usb_a9g20_common.dtsi} (81%)
 create mode 100644 arch/arm/boot/dts/usb_a9g20_lpw.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..f62d126 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
 dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
 # sam9g45
 dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index c979c06..ec77cf8 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -6,25 +6,9 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-#include "at91sam9g20.dtsi"
-#include "usb_a9260_common.dtsi"
+#include "usb_a9g20_common.dtsi"
 
 / {
 	model = "Calao USB A9G20";
 	compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
-
-	chosen {
-		bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
-	};
-
-	memory {
-		reg = <0x20000000 0x4000000>;
-	};
-
-	i2c at 0 {
-		rv3029c2 at 56 {
-			compatible = "rv3029c2";
-			reg = <0x56>;
-		};
-	};
 };
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20_common.dtsi
similarity index 81%
copy from arch/arm/boot/dts/usb_a9g20.dts
copy to arch/arm/boot/dts/usb_a9g20_common.dtsi
index c979c06..0b3b361 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi
@@ -5,14 +5,11 @@
  *
  * Licensed under GPLv2 or later.
  */
-/dts-v1/;
+
 #include "at91sam9g20.dtsi"
 #include "usb_a9260_common.dtsi"
 
 / {
-	model = "Calao USB A9G20";
-	compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
-
 	chosen {
 		bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
 	};
diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts
new file mode 100644
index 0000000..f8cb1b9
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_lpw.dts
@@ -0,0 +1,31 @@
+/*
+ * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board
+ *
+ *  Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "usb_a9g20_common.dtsi"
+
+/ {
+	model = "Calao USB A9G20 Low Power";
+	compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+	ahb {
+		apb {
+			spi1: spi at fffcc000 {
+				cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+				mmc-slot at 0 {
+					compatible = "mmc-spi-slot";
+					reg = <0>;
+					voltage-ranges = <3200 3400>;
+					spi-max-frequency = <25000000>;
+					interrupt-parent = <&pioC>;
+					interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index a8800d3..75fd842 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -161,6 +161,7 @@ CONFIG_USB_ATMEL_USBA=y
 CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -169,6 +170,7 @@ CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Sun May 26 11:33:41 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 26 May 2013 17:33:41 +0200
Subject: [PATCH 5/5] ARM: at91: drop non DT: Calao USB-A96x
In-Reply-To: <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130526153037.GQ24476@game.jcrosoft.org>
 <1369582421-25562-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1369582421-25562-5-git-send-email-plagnioj@jcrosoft.com>

as now we have full DT support of those board

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: gregory hermant <gregory.hermant at calao-systems.com>
---
 arch/arm/configs/at91sam9260_9g20_defconfig |    1 -
 arch/arm/configs/at91sam9263_defconfig      |    1 -
 arch/arm/mach-at91/Kconfig.non_dt           |   19 --
 arch/arm/mach-at91/Makefile                 |    3 -
 arch/arm/mach-at91/board-usb-a926x.c        |  384 ---------------------------
 5 files changed, 408 deletions(-)
 delete mode 100644 arch/arm/mach-at91/board-usb-a926x.c

diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index f50c404..69b6928 100644
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -15,7 +15,6 @@ CONFIG_MACH_AT91SAM9260EK=y
 CONFIG_MACH_CAM60=y
 CONFIG_MACH_SAM9_L9260=y
 CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_USB_A9260=y
 CONFIG_MACH_QIL_A9260=y
 CONFIG_MACH_CPU9260=y
 CONFIG_MACH_FLEXIBITY=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 9d72ab6..e4002636 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -15,7 +15,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
-CONFIG_MACH_USB_A9263=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 1a2abd8..6cd554a 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -183,12 +183,6 @@ config MACH_AFEB9260
 	  <svn://194.85.238.22/home/users/george/svn/arm9eb>
 	  <http://groups.google.com/group/arm9fpga-evolution-board>
 
-config MACH_USB_A9260
-	bool "CALAO USB-A9260"
-	help
-	  Select this if you are using a Calao Systems USB-A9260.
-	  <http://www.calao-systems.com>
-
 config MACH_QIL_A9260
 	bool "CALAO QIL-A9260 board"
 	help
@@ -264,13 +258,6 @@ config MACH_GSIA18S
 	  produced by GeoSIG Ltd company. This is an internet accelerograph.
 	  <http://www.geosig.com>
 
-config MACH_USB_A9G20
-	bool "CALAO USB-A9G20"
-	depends on ARCH_AT91SAM9G20
-	help
-	  Select this if you are using a Calao Systems USB-A9G20.
-	  <http://www.calao-systems.com>
-
 config MACH_SNAPPER_9260
 	bool "Bluewater Systems Snapper 9260/9G20 module"
 	help
@@ -316,12 +303,6 @@ config MACH_AT91SAM9263EK
 	  Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
 	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
 
-config MACH_USB_A9263
-	bool "CALAO USB-A9263"
-	help
-	  Select this if you are using a Calao Systems USB-A9263.
-	  <http://www.calao-systems.com>
-
 endif
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index f4a5f79..d07bcfa 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_MACH_RSI_EWS)	+= board-rsi-ews.o
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)	+= board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)	+= board-sam9-l9260.o
-obj-$(CONFIG_MACH_USB_A9260)	+= board-usb-a926x.o
 obj-$(CONFIG_MACH_QIL_A9260)	+= board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)	+= board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)	+= board-cpu9krea.o
@@ -65,7 +64,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
-obj-$(CONFIG_MACH_USB_A9263)	+= board-usb-a926x.o
 
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
@@ -78,7 +76,6 @@ obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20)	+= board-pcontrol-g20.o board-stamp9g20.o
 obj-$(CONFIG_MACH_GSIA18S)	+= board-gsia18s.o board-stamp9g20.o
-obj-$(CONFIG_MACH_USB_A9G20)	+= board-usb-a926x.o
 
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
deleted file mode 100644
index 2487d94..0000000
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-usb-a926x.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *  Copyright (C) 2007 Calao-systems
- *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/spi/mmc_spi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-
-#include "at91_aic.h"
-#include "at91_shdwc.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_init_early(void)
-{
-	/* Initialize processor: 12.00 MHz crystal */
-	at91_initialize(12000000);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-	.ports		= 2,
-	.vbus_pin	= {-EINVAL, -EINVAL},
-	.overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-	.vbus_pin	= AT91_PIN_PB11,
-	.pullup_pin	= -EINVAL,		/* pull-up driven by UDC */
-};
-
-static void __init ek_add_device_udc(void)
-{
-	if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-		ek_udc_data.vbus_pin = AT91_PIN_PC5;
-
-	at91_add_device_udc(&ek_udc_data);
-}
-
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4
-static int at91_mmc_spi_init(struct device *dev,
-	irqreturn_t (*detect_int)(int, void *), void *data)
-{
-	/* Configure Interrupt pin as input, no pull-up */
-	at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0);
-	return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int,
-		IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-		"mmc-spi-detect", data);
-}
-
-static void at91_mmc_spi_exit(struct device *dev, void *data)
-{
-	free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data);
-}
-
-static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
-	.init = at91_mmc_spi_init,
-	.exit = at91_mmc_spi_exit,
-	.detect_delay = 100, /* msecs */
-};
-#endif
-
-/*
- * SPI devices.
- */
-static struct spi_board_info usb_a9263_spi_devices[] = {
-	{	/* DataFlash chip */
-		.modalias	= "mtd_dataflash",
-		.chip_select	= 0,
-		.max_speed_hz	= 15 * 1000 * 1000,
-		.bus_num	= 0,
-	}
-};
-
-static struct spi_board_info usb_a9g20_spi_devices[] = {
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-	{
-		.modalias = "mmc_spi",
-		.max_speed_hz = 20000000,	/* max spi clock (SCK) speed in HZ */
-		.bus_num = 1,
-		.chip_select = 0,
-		.platform_data = &at91_mmc_spi_pdata,
-		.mode = SPI_MODE_3,
-	},
-#endif
-};
-
-static void __init ek_add_device_spi(void)
-{
-	if (machine_is_usb_a9263())
-		at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices));
-	else if (machine_is_usb_a9g20())
-		at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices));
-}
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-	.phy_irq_pin	= AT91_PIN_PE31,
-	.is_rmii	= 1,
-};
-
-static void __init ek_add_device_eth(void)
-{
-	if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-		ek_macb_data.phy_irq_pin = AT91_PIN_PA31;
-
-	at91_add_device_eth(&ek_macb_data);
-}
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-	{
-		.name	= "barebox",
-		.offset	= 0,
-		.size	= 3 * SZ_128K,
-	}, {
-		.name	= "bareboxenv",
-		.offset	= MTDPART_OFS_NXTBLK,
-		.size	= SZ_128K,
-	}, {
-		.name	= "bareboxenv2",
-		.offset	= MTDPART_OFS_NXTBLK,
-		.size	= SZ_128K,
-	}, {
-		.name	= "oftree",
-		.offset	= MTDPART_OFS_NXTBLK,
-		.size	= SZ_128K,
-	}, {
-		.name	= "kernel",
-		.offset	= MTDPART_OFS_NXTBLK,
-		.size	= 4 * SZ_1M,
-	}, {
-		.name	= "rootfs",
-		.offset	= MTDPART_OFS_NXTBLK,
-		.size	= 120 * SZ_1M,
-	}, {
-		.name	= "data",
-		.offset	= MTDPART_OFS_NXTBLK,
-		.size	= MTDPART_SIZ_FULL,
-	}
-};
-
-static struct atmel_nand_data __initdata ek_nand_data = {
-	.ale		= 21,
-	.cle		= 22,
-	.det_pin	= -EINVAL,
-	.rdy_pin	= AT91_PIN_PA22,
-	.enable_pin	= AT91_PIN_PD15,
-	.ecc_mode	= NAND_ECC_SOFT,
-	.on_flash_bbt	= 1,
-	.parts		= ek_nand_partition,
-	.num_parts	= ARRAY_SIZE(ek_nand_partition),
-};
-
-static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 1,
-	.ncs_write_setup	= 0,
-	.nwe_setup		= 1,
-
-	.ncs_read_pulse		= 3,
-	.nrd_pulse		= 3,
-	.ncs_write_pulse	= 3,
-	.nwe_pulse		= 3,
-
-	.read_cycle		= 5,
-	.write_cycle		= 5,
-
-	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-	.tdf_cycles		= 2,
-};
-
-static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 2,
-	.ncs_write_setup	= 0,
-	.nwe_setup		= 2,
-
-	.ncs_read_pulse		= 4,
-	.nrd_pulse		= 4,
-	.ncs_write_pulse	= 4,
-	.nwe_pulse		= 4,
-
-	.read_cycle		= 7,
-	.write_cycle		= 7,
-
-	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-	.tdf_cycles		= 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-	if (machine_is_usb_a9260() || machine_is_usb_a9g20()) {
-		ek_nand_data.rdy_pin	= AT91_PIN_PC13;
-		ek_nand_data.enable_pin	= AT91_PIN_PC14;
-	}
-
-	/* configure chip-select 3 (NAND) */
-	if (machine_is_usb_a9g20())
-		sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
-	else
-		sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
-
-	at91_add_device_nand(&ek_nand_data);
-}
-
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-	{	/* USER PUSH BUTTON */
-		.code		= KEY_ENTER,
-		.gpio		= AT91_PIN_PB10,
-		.active_low	= 1,
-		.desc		= "user_pb",
-		.wakeup		= 1,
-	}
-};
-
-static struct gpio_keys_platform_data ek_button_data = {
-	.buttons	= ek_buttons,
-	.nbuttons	= ARRAY_SIZE(ek_buttons),
-};
-
-static struct platform_device ek_button_device = {
-	.name		= "gpio-keys",
-	.id		= -1,
-	.num_resources	= 0,
-	.dev		= {
-		.platform_data	= &ek_button_data,
-	}
-};
-
-static void __init ek_add_device_buttons(void)
-{
-	at91_set_GPIO_periph(AT91_PIN_PB10, 1);	/* user push button, pull up enabled */
-	at91_set_deglitch(AT91_PIN_PB10, 1);
-
-	platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-	{	/* user_led (green) */
-		.name			= "user_led",
-		.gpio			= AT91_PIN_PB21,
-		.active_low		= 1,
-		.default_trigger	= "heartbeat",
-	}
-};
-
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("rv3029c2", 0x56),
-	},
-};
-
-static void __init ek_add_device_leds(void)
-{
-	if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-		ek_leds[0].active_low = 0;
-
-	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-
-static void __init ek_board_init(void)
-{
-	/* Serial */
-	/* DBGU on ttyS0. (Rx & Tx only) */
-	at91_register_uart(0, 0, 0);
-	at91_add_device_serial();
-	/* USB Host */
-	at91_add_device_usbh(&ek_usbh_data);
-	/* USB Device */
-	ek_add_device_udc();
-	/* SPI */
-	ek_add_device_spi();
-	/* Ethernet */
-	ek_add_device_eth();
-	/* NAND */
-	ek_add_device_nand();
-	/* Push Buttons */
-	ek_add_device_buttons();
-	/* LEDs */
-	ek_add_device_leds();
-
-	if (machine_is_usb_a9g20()) {
-		/* I2C */
-		at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-	} else {
-		/* I2C */
-		at91_add_device_i2c(NULL, 0);
-		/* shutdown controller, wakeup button (5 msec low) */
-		at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
-				| AT91_SHDW_WKMODE0_LOW
-				| AT91_SHDW_RTTWKEN);
-	}
-}
-
-MACHINE_START(USB_A9263, "CALAO USB_A9263")
-	/* Maintainer: calao-systems */
-	.init_time	= at91sam926x_pit_init,
-	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
-	.init_early	= ek_init_early,
-	.init_irq	= at91_init_irq_default,
-	.init_machine	= ek_board_init,
-MACHINE_END
-
-MACHINE_START(USB_A9260, "CALAO USB_A9260")
-	/* Maintainer: calao-systems */
-	.init_time	= at91sam926x_pit_init,
-	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
-	.init_early	= ek_init_early,
-	.init_irq	= at91_init_irq_default,
-	.init_machine	= ek_board_init,
-MACHINE_END
-
-MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
-	/* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
-	.init_time	= at91sam926x_pit_init,
-	.map_io		= at91_map_io,
-	.handle_irq	= at91_aic_handle_irq,
-	.init_early	= ek_init_early,
-	.init_irq	= at91_init_irq_default,
-	.init_machine	= ek_board_init,
-MACHINE_END
-- 
1.7.10.4



From liuj97 at gmail.com  Sun May 26 11:53:17 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Sun, 26 May 2013 23:53:17 +0800
Subject: [PATCH v3, part2 20/20] PCI,
 ARM: use hotplug-safe PCI bus iterators to walk PCI buses
In-Reply-To: <1369583597-3801-1-git-send-email-jiang.liu@huawei.com>
References: <1369583597-3801-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1369583597-3801-21-git-send-email-jiang.liu@huawei.com>

Enhance ARM architecture specific code to use new hotplug-safe PCI
bus iterators to walk PCI buses.

Change pcibios_report_status implementation so that it doesn't access
pci_root_buses global list. The pci_root_buses list will be scheduled
to be removed.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Bjorn Helgaas <bhelgaas at google.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/kernel/bios32.c           | 13 +------------
 arch/arm/mach-footbridge/dc21285.c | 12 +++++++++++-
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b2ed73c..50ebbe8 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -22,7 +22,7 @@ static int debug_pci;
  * We can't use pci_find_device() here since we are
  * called from interrupt context.
  */
-static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
+void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
 {
 	struct pci_dev *dev;
 
@@ -55,17 +55,6 @@ static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, in
 			pcibios_bus_report_status(dev->subordinate, status_mask, warn);
 }
 
-void pcibios_report_status(u_int status_mask, int warn)
-{
-	struct list_head *l;
-
-	list_for_each(l, &pci_root_buses) {
-		struct pci_bus *bus = pci_bus_b(l);
-
-		pcibios_bus_report_status(bus, status_mask, warn);
-	}
-}
-
 /*
  * We don't use this to fix the device, but initialisation of it.
  * It's not the correct use for this, but it works.
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index a7cd2cf..a0f1d01 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -35,7 +35,16 @@
 				  PCI_STATUS_PARITY) << 16)
 
 extern int setup_arm_irq(int, struct irqaction *);
-extern void pcibios_report_status(u_int status_mask, int warn);
+extern void pcibios_report_bus_status(struct pci_bus *bus, u_int status_mask,
+				      int warn);
+
+static struct pci_bus *dc21285_root_bus;
+
+static void pcibios_report_status(u_int status_mask, int warn)
+{
+	if (dc21285_root_bus)
+		pcibios_report_bus_status(dc21285_root_bus, status_mask, warn);
+}
 
 static unsigned long
 dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
@@ -376,5 +385,6 @@ void __init dc21285_preinit(void)
 
 void __init dc21285_postinit(void)
 {
+	dc21285_root_bus = pci_get_next_root_bus(NULL);
 	register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);
 }
-- 
1.8.1.2



From haojian.zhuang at linaro.org  Sun May 26 12:11:10 2013
From: haojian.zhuang at linaro.org (Haojian Zhuang)
Date: Mon, 27 May 2013 00:11:10 +0800
Subject: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to
 configure multiple pins of different modules
In-Reply-To: <CACRpkdZEsRaaE9dJLDNMzJZSLZ35pqS6XVj5KgCzJGG5nnvPQg@mail.gmail.com>
References: <1369145282-14419-1-git-send-email-prakash.pm@ti.com>
 <CACRpkdZEsRaaE9dJLDNMzJZSLZ35pqS6XVj5KgCzJGG5nnvPQg@mail.gmail.com>
Message-ID: <CAD6h2NTPp9BdxpjjQig1B-gVk+7PvxBvtUKi=kcbiUQeQ5wYjA@mail.gmail.com>

On 24 May 2013 17:03, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash
> <prakash.pm at ti.com> wrote:
>
>> Based function-mask and submask preoperties patch allocates and registers pins.
>> Patch is fixes the issue reported and discussed here:
>> http://www.spinics.net/lists/arm-kernel/msg235213.html
>
> I'd like Tony to ACK this, and Haojian to have a look at it before applying.
>
> Yours,
> Linus Walleij

I'll give feedback in the next week.

Regards
Haojian


From maxime.ripard at free-electrons.com  Sun May 26 13:00:11 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Sun, 26 May 2013 19:00:11 +0200
Subject: [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <24460034.7lWPC5EJAp@flatron>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
 <24460034.7lWPC5EJAp@flatron>
Message-ID: <20130526170011.GK17847@lukather>

On Sun, May 26, 2013 at 04:38:19PM +0200, Tomasz Figa wrote:
> On Sunday 26 of May 2013 12:20:37 Maxime Ripard wrote:
> > +	/*
> > +	 * Address + Read bit have been transmitted, ACK has not been
> > +	 * received. If we don't care about the NAKs, we just treat
> > +	 * this case as if an ACK would have been received, and fall
> > +	 * through to the next case.
> > +	 */
> > +	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
> > +		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
> > +			i2c_dev->msg_err = SUNXI_I2C_NAK;
> > +			goto out;
> > +		}
> 
> I meant something more like:
> 
> +
> +	/* Intentional fall through. */
> 
> This is enough to let the reader know that there is no break missing here 
> and you can keep those nice short state descriptions from v1.

Ok, I'll do it that way

[..]

> > +static int sunxi_i2c_probe(struct platform_device *pdev)
> > +{
> > +	struct sunxi_i2c_dev *i2c_dev;
> > +	struct device_node *np;
> > +	u32 freq, div_m, div_n;
> > +	struct resource res;
> 
> 	struct resource *res;
> 
> and then...
> 
> > +	int ret;
> > +
> > +	np = pdev->dev.of_node;
> > +	if (!np)
> > +		return -EINVAL;
> > +
> > +	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
> > +	if (!i2c_dev)
> > +		return -ENOMEM;
> > +	platform_set_drvdata(pdev, i2c_dev);
> > +	i2c_dev->dev = &pdev->dev;
> > +
> > +	init_completion(&i2c_dev->completion);
> > +
> > +	ret = of_address_to_resource(np, 0, &res);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "could not get IO memory\n");
> > +		return ret;
> > +	}
> > +
> > +	i2c_dev->membase = devm_ioremap_resource(&pdev->dev, &res);
> 
> 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 	i2c_dev->membase = devm_ioremap_resource(&pdev->dev, res);
> 
> This way you can save yourself from parsing device tree again, one error 
> check and few lines of code. Remember that of_platform_populate() creates 
> all the resources of platform_devices based on reg and interrupts 
> properties, so there is no point in wasting this effort in drivers by 
> parsing them manually again.

Ah, right, I didn't thought about the double dt parsing. I'll switch to
platform_get_resource and platform_get_irq as you suggested.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From cjb at laptop.org  Sun May 26 13:34:50 2013
From: cjb at laptop.org (Chris Ball)
Date: Sun, 26 May 2013 13:34:50 -0400
Subject: [PATCH] mmc: atmel-mci: convert to
 dma_request_slave_channel_compat()
In-Reply-To: <1368180314-13665-1-git-send-email-nicolas.ferre@atmel.com>
 (Nicolas Ferre's message of "Fri, 10 May 2013 12:05:14 +0200")
References: <517F7B6F.4070907@atmel.com>
 <1368180314-13665-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <871u8tmypx.fsf@octavius.laptop.org>

Hi Nicolas,

On Fri, May 10 2013, Nicolas Ferre wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Use generic DMA DT helper. Platforms booting with or without DT populated are
> both supported.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
> Hi Chris,
>
> This patch is part of a series by Ludovic and is adding the generic slave
> DMA request channel function, as we now have the support for DMA bindings.
>
> This is the only patch of the series that should go through your tree. And it
> seems that my little reminder didn't catch your attention in time for 3.10 merge
> window but I still hope that we can make it for 3.10-final... It is also true
> that we didn't put you in copy of the original message and that the subject
> line was somehow malformed ;-)
>
> Here is the Linux arm kernel patchwork reference of previous discussion:
> https://patchwork.kernel.org/patch/2463641/

Thanks, I'm sorry for the delay.  This is in mmc-next now, I'll send
it to Linus for the next -rc.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From nm at ti.com  Sun May 26 13:35:51 2013
From: nm at ti.com (Nishanth Menon)
Date: Sun, 26 May 2013 12:35:51 -0500
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <87ppwgdnxu.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <87ppwgdnxu.fsf@linaro.org>
Message-ID: <CAGo_u6ruWQwSB8Z0BRLda7HunTyr9mGpx4eMSGdQZkCxKxbHbg@mail.gmail.com>

On Fri, May 24, 2013 at 5:15 PM, Kevin Hilman <khilman at linaro.org> wrote:
> Kevin Hilman <khilman at linaro.org> writes:
>
>> Nishanth Menon <nm at ti.com> writes:
>
> [...]
>
>>> Actually 2 things:
>>>
>>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>>> have been used instead of 0x14 which is correct for 4430?
>>
>> I see, thanks.  I'll double check the TRMs.
>>
>>> b) yes, I understand,  the current settings we did worked, but the
>>> mode(0) we are setting to is real weird - we are setting it up for
>>> clk0 out - I cant even think why it is even working in the first place
>>> :( - is it because we are pumping out sysclkout and as a result we are
>>> lucky that msecure is being sampled at the right point by twl6030
>>> allowing rtc access? either way, IMHO, the configuration is wrong.
>>
>> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
>> for legacy mode, I just duplicated the settings u-boot was using.  Guess
>> it's a fluke that it works.
>
> Actually, for legacy mode, it's set correctly in mode 2.  This line:
>
>         omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
>
> does the right thing based on the signal name.    But for DT boot, I
> defintely screwed it up by setting it to mode (and putting it in the
> wrong padconf section.)
>
> Also, are you *really* sure about the offset difference between 4430 and
> 4460 here?  I don't have access to NDA docs anymore, so I cannot double
> check this.
>
> What I do know is that the legacy code is using 0x54 for both, and if I
> simply comment out that 'sys_drm_msecure' line above, RTC wake stops
> working (legacy boot) on both 4430 and 4460, so that seems like pretty
> stront evidence that it's the same offset on both.
Schematics are public for PandaBoard ES and PandaBoard - as you can
see from that the registers connected are definitely different.

The control pad information should be present in public TRM as well -
the "secure" angle was public, but in this case, it does not really
matter.

Regards,
Nishanth Menon


From jason at lakedaemon.net  Sun May 26 13:59:57 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 26 May 2013 13:59:57 -0400
Subject: [PATCH v3 2/3] arm: kirkwood: Instantiate cpufreq driver
In-Reply-To: <1359281244-31455-3-git-send-email-andrew@lunn.ch>
References: <1359281244-31455-1-git-send-email-andrew@lunn.ch>
 <1359281244-31455-3-git-send-email-andrew@lunn.ch>
Message-ID: <20130526175957.GD31290@titan.lakedaemon.net>

On Sun, Jan 27, 2013 at 11:07:23AM +0100, Andrew Lunn wrote:
> Register a platform driver structure for the cpufreq driver.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> ---
>  arch/arm/Kconfig                                  |    1 +
>  arch/arm/mach-kirkwood/board-dt.c                 |    3 ++-
>  arch/arm/mach-kirkwood/common.c                   |   23 +++++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h                   |    2 ++
>  arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    2 ++
>  5 files changed, 30 insertions(+), 1 deletion(-)

Thanks again to Andrew for digging this one up.  Applied to mvebu/soc

thx,

Jason.


From jason at lakedaemon.net  Sun May 26 14:02:29 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 26 May 2013 14:02:29 -0400
Subject: [PATCH v3 3/3] arm: kirkwood: Enable cpufreq and ondemand on
 kirkwood_defconfig
In-Reply-To: <1359281244-31455-4-git-send-email-andrew@lunn.ch>
References: <1359281244-31455-1-git-send-email-andrew@lunn.ch>
 <1359281244-31455-4-git-send-email-andrew@lunn.ch>
Message-ID: <20130526180229.GE31290@titan.lakedaemon.net>

On Sun, Jan 27, 2013 at 11:07:24AM +0100, Andrew Lunn wrote:
> Now that we have a cpufreq driver for kirkwood, enable it in
> kirkwood_defconfig and set the default governer to ondemand.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> ---
>  arch/arm/configs/kirkwood_defconfig |    3 +++
>  1 file changed, 3 insertions(+)

Applied to mvebu/defconfig

thx,

Jason.


From jason at lakedaemon.net  Sun May 26 14:05:13 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 26 May 2013 14:05:13 -0400
Subject: Kirkwood CPU Freq driver
In-Reply-To: <20130526083614.GB26249@lunn.ch>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
Message-ID: <20130526180513.GF31290@titan.lakedaemon.net>

On Sun, May 26, 2013 at 10:36:14AM +0200, Andrew Lunn wrote:
> On Sat, May 25, 2013 at 10:32:04PM +0100, Adam Baker wrote:
> > I've been trying to test Andrew Lunn's work creating a CPU Idle
> > driver for Kirkwood.
> 
> Thanks for testing this. I must admit, i never tested it once the
> first rc came out. I clearly should of, because its broken. It was a
> three part patch series, and only part 1/3 made it in. Hence the
> issues you are seeing.
> 
> Jason, please can you pick up:
> 
> https://patchwork.kernel.org/patch/2051401/
> https://patchwork.kernel.org/patch/2080931/

Yep, got them in now.  Sorry for the mix up.

thx,

Jason.


From pavel at denx.de  Sun May 26 14:11:16 2013
From: pavel at denx.de (Pavel Machek)
Date: Sun, 26 May 2013 20:11:16 +0200
Subject: [PATCHv4 6/6] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA
In-Reply-To: <201305242058.34332.arnd@arndb.de>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <201305241912.53751.arnd@arndb.de>
 <1369418588.9717.0.camel@linux-builds1>
 <201305242058.34332.arnd@arndb.de>
Message-ID: <20130526181116.GA16409@amd.pavel.ucw.cz>

On Fri 2013-05-24 20:58:34, Arnd Bergmann wrote:
> On Friday 24 May 2013, Dinh Nguyen wrote:
> > I apologize for that. Will make sure to include a [PATCH 0/6] message in
> > the future.
> 
> No worries, I actually saw now that my only other comment was also
> wrong, as you have the binding I was looking for in patch 5/6.

Could you take the series through your tree?

Patches 1,2,4,5/6 are mostly local to arch/arm, 3/6 is stuff Dinh is
listed as a maintainer for, and 6/6 is fairly socfpga-specific,
too. (I guess Dinh could add MAINTAINERs entry for that...).

Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From oliver+list at schinagl.nl  Sun May 26 15:01:53 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Sun, 26 May 2013 21:01:53 +0200
Subject: [linux-sunxi] [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c
 driver
In-Reply-To: <20130526132120.GJ17847@lukather>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
 <51A1E9AA.4000008@schinagl.nl> <20130526132120.GJ17847@lukather>
Message-ID: <51A25C21.2060700@schinagl.nl>

On 05/26/13 15:21, Maxime Ripard wrote:

>>> +static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u8 value)
>>> +{
>>> +	writel(value, i2c_dev->membase + reg);
>> Why writel? and why without (u32)value? I thought iowrite* where the
>> preferred calls and in this case, wouldn't we want writeb since
>> value is u8?
>
> You're right, value should be a u32 here, thanks for noticing.
>
> For the iowrite* vs write*, there's no consensus, and as such no
> preferred way. write* functions are doing an MMIO only access,
> while iowrite functions can do MMIO and port I/O accesses.
>
> Note that it doesn't change anything on ARM, since there's no port IO on
> ARM.
Ah I see, missinformation on my end. Sorry.

But why write 32 bits? The register is only 8 wide, with the rest being 
'reserved'. Then again, the register IS 32 bits wide and probably will 
haev 32 bits written to it? Correct?

>
>>> +}
>>> +
>>> +static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
>>> +{
>>> +	return readl(i2c_dev->membase + reg);
>> And here, readl does match the return of u32, but aren't we always
>> reading 8 bits since the TWI Data Register only uses the first 8
>> bits?
>> So wouldn't we want to return u8 and readb?
>
> They are meant to be general purpose accessors, so we shouldn't focus
> only on the data register.
Ah yes, of course.

>
>>
>>> +static int sunxi_i2c_probe(struct platform_device *pdev)
>>> +{
>>> +	struct sunxi_i2c_dev *i2c_dev;
>>> +	struct device_node *np;
>>> +	u32 freq, div_m, div_n;
>>> +	struct resource res;
>> I feel stupid for questioning this, since it only shows my lack of
>> knowledge, but
>> If you declare all the memory here, isn't all the data lost after
>> exiting the _probe function? we pass a pointer to this memory in the
>> of_address_to_resource() function so that fills it, right?
>>
>> Or does after devm_ioremap_resource it no longer matter, since that
>> function got what it needed and useless after?
>
> The struct resource is only there to declare the base address and the
> size of memory address. Once we have mapped it, we don't care about it
> anymore.
Thanks for clarifying that, I will adapt my driver to do the same.
>
> Maxime
>



From oliver+list at schinagl.nl  Sun May 26 15:05:09 2013
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Sun, 26 May 2013 21:05:09 +0200
Subject: [linux-sunxi] [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c
 driver
In-Reply-To: <1781939.MrE9Xthq6W@flatron>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
 <51A1E9AA.4000008@schinagl.nl> <1781939.MrE9Xthq6W@flatron>
Message-ID: <51A25CE5.4040901@schinagl.nl>

On 05/26/13 16:44, Tomasz Figa wrote:
> Hi Oliver,
>
> I can recommend you a great tool to browse through Linux sources:
> http://lxr.free-electrons.com/source/lib/devres.c?a=arm#L107
>
> It really helps looking up in code things that you aren't sure.
>
> Best regards,
> Tomasz
>
Yeah, I'm allready a heavy user of LXR ;) But sometimes there's just 
information overload and things become hard to follow. Especially when 
there's several ways to do something.

I would have hoped that a 'ldd4' would be available which has OF support 
written in. ldd3 lacks all that.


From aaro.koskinen at iki.fi  Sun May 26 15:07:10 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Sun, 26 May 2013 22:07:10 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <519E67AD.6070702@gmail.com>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com>
 <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
Message-ID: <20130526190710.GA3345@blackmetal.musicnaut.iki.fi>

On Thu, May 23, 2013 at 08:02:05PM +0100, Jon Hunter wrote:
> On 22/05/13 22:20, Aaro Koskinen wrote:
> > On Tue, May 21, 2013 at 08:37:16PM +0100, Jon Hunter wrote:
> >> On 21/05/13 18:39, Aaro Koskinen wrote:
> >>> On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
> >>>> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
> >>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
> >>>>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
> >>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
> >>>>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
> >>>>>>>>
> >>>>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
> >>>>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
> >>>>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
> >>>>>>>>
> >>>>>>>> The error is coming from regmap code. According to git bisect, it is
> >>>>>>>> caused by:
> >>>>>>>>
> >>>>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
> >>>>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
> >>>>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
> >>>>>>>>
> >>>>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
> >>>>>>>>
> >>>>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
> >>>>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
> >>>>>>>
> >>>>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
> >>>>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
> >>>>>>>
> >>>>>>> For the -rc cycle, it might be possible to fix this by adding a
> >>>>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
> >>>>>>
> >>>>>> The commit reverts cleanly if we also revert
> >>>>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
> >>>>>> service routine), which seems to be just some minor optimization. The
> >>>>>> result is below, and with it 770 works again.
> >>>>>
> >>>>> Hmm in this case it seems that we should just fix it rather than go back
> >>>>> to the old code, so let's take a look at that first.
> >>>>
> >>>> Does the following fix it for you or do we need to fix something else
> >>>> there too?
> >>>
> >>> Thanks, that fixes Retu probe on 770.
> >>
> >> Sorry for not responding sooner, but I have been moving. 
> >>
> >> From looking at the code it appears that the regmap_add_irq_chip()
> >> is failing in the retu driver. I am not sure if this will work, 
> >> but have you tried making the following change to the retu driver 
> >> so that it also uses irq_domain_add_linear() as well? Just a thought ...
> > 
> > This will trigger WARNING: at drivers/base/regmap/regmap-irq.c:514.
> 
> Sorry, there is another change needed. Can you try ...

I don't see much improvement with this. Although Retu probe succeeds,
genirq error logs are still there. Also none of the GPIO irqs used by
other drivers seem to be working at all, e.g. touchscreen.

A.

> diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
> index a183098..9080cd6 100644
> --- a/drivers/mfd/retu-mfd.c
> +++ b/drivers/mfd/retu-mfd.c
> @@ -267,14 +267,13 @@ static int retu_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
>         if (ret < 0)
>                 return ret;
>  
> -       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, -1,
> +       ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, 0,
>                                   rdat->irq_chip, &rdev->irq_data);
>         if (ret < 0)
>                 return ret;
>  
>         ret = mfd_add_devices(rdev->dev, -1, rdat->children, rdat->nchildren,
> -                             NULL, regmap_irq_chip_get_base(rdev->irq_data),
> -                             NULL);
> +                             NULL, 0, regmap_irq_get_domain(rdev->irq_data));
>         if (ret < 0) {
>                 regmap_del_irq_chip(i2c->irq, rdev->irq_data);
>                 return ret;
>  
> > Also other drivers report GPIO IRQ issues later in the boot, e.g.
> > 
> > [    3.907928] genirq: Flags mismatch irq 0. 00000001 (serial wakeup) vs. 00002000 (RETU)
> > [    3.923706] No interrupt for UART wake GPIO: 37
> 
> Looks like the gpio is just conflicting with the RETU driver.
>  
> > With Tony's patch (without any Retu modifications), the boot is clean. So
> > I guess gpio-omap fix is needed.
> 
> Ideally it would be good if the RETU can use linear domains and then may be this
> can be avoided.
> 
> Cheers
> Jon


From sergei.shtylyov at cogentembedded.com  Sun May 26 15:13:14 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Sun, 26 May 2013 23:13:14 +0400
Subject: [PATCH 1/1] mmc: of_mmc_spi: fix card detect irq
In-Reply-To: <1369571337-9300-1-git-send-email-plagnioj@jcrosoft.com>
References: <1369571337-9300-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <51A25ECA.2060001@cogentembedded.com>

Hello.

On 05/26/2013 04:28 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:

> set missing irq type the IRQF_ONESHOT
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: stable <stable at vger.kernel.org> # 3.4+
> Cc: linux-mmc at vger.kernel.org
> ---
>   drivers/mmc/host/of_mmc_spi.c |    4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
> index d720b5e..cfb2e61 100644
> --- a/drivers/mmc/host/of_mmc_spi.c
> +++ b/drivers/mmc/host/of_mmc_spi.c
> @@ -74,8 +74,8 @@ static int of_mmc_spi_init(struct device *dev,
>   {
>   	struct of_mmc_spi *oms = to_of_mmc_spi(dev);
>   
> -	return request_threaded_irq(oms->detect_irq, NULL, irqhandler, 0,
> -				    dev_name(dev), mmc);
> +	return request_threaded_irq(oms->detect_irq, NULL, irqhandler,
> +		IRQF_ONESHOT, dev_name(dev), mmc);

     Please don't change the indentation.

WBR, Sergei



From sebastian.hesselbarth at gmail.com  Sun May 26 16:06:58 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sun, 26 May 2013 22:06:58 +0200
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <20130525.210441.818472895703230779.davem@davemloft.net>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130525.210441.818472895703230779.davem@davemloft.net>
Message-ID: <51A26B62.4050009@gmail.com>

On 05/26/2013 06:04 AM, David Miller wrote:
> From: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> Date: Wed, 22 May 2013 22:04:01 +0200
>
>> +			memcpy((void *)p->value, reg, 6);
>
> This cast is completely unnecessary, non-void to void pointer casts
> are automatic.
>
> If it is necessary, because p->value is const, then you are trying
> to change something behind the OF layer's back and need to use
> the appropriate interface to change the property contents.

David,

good you mention it. I added Grant on Cc and will give a short
sum-up why I casted the const from property->value away here.

Maybe I overlooked the API for modifying the DT property but as
far as I've seen - there is no API for modifying it. And yes,
you are right, it is kind of an abuse of DT here.

As Kirkwoods loose their MAC address on clock gating, I was looking
for a place to store it early. (a) DT property "local-mac-address"
looked as a good place as it will allow the driver to find it without
any extra code. Of course, I am doing severaly sanity checks if it is
safe to overwrite it, i.e. no other MAC set, property is there, long
enough.

If Grant also NACKs modifying the DT we basically have two more options
left for Kirkwood: (b) have MAC stored early in two global arrays in
board init and reference that from mv643xx_eth or (c) leave the clock
ungated unconditionally on all Kirkwoods.

I can live with all three, just name it and I prepare a final patch set.

Sebastian


From linus.walleij at linaro.org  Sun May 26 16:32:45 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 26 May 2013 22:32:45 +0200
Subject: [GIT PULL] Nomadik clocks from device tree
In-Reply-To: <CACRpkdY8xqi04cf-SJ69QvHr8qB6itqvgxMyNk+=Xrtz2FGVaA@mail.gmail.com>
References: <CACRpkdY8xqi04cf-SJ69QvHr8qB6itqvgxMyNk+=Xrtz2FGVaA@mail.gmail.com>
Message-ID: <CACRpkdaKtxKS0=1UOKJPQWKShRm2nHsUWSK5M+qSR6duXfGrxw@mail.gmail.com>

Hi ARM SoC people,

I have accumulated more Nomadik patches so I'm reiterating this
pull request with two new patches on top.

Please pull them in for v3.11!

Yours,
Linus Walleij


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
tags/nomadik-dt-for-arm-soc

for you to fetch changes up to 49932f5ef13fa6a5a8bd71cf2f0b721d0e0b495d:

  ARM: nomadik: move the pin configuration to DT (2013-05-26 22:25:36 +0200)

----------------------------------------------------------------
Device tree patches for the Nomadik machine:
- Move clock registration to the device tree
- Support probing the MTU timer from the device tree
- Register user LED and user key in the device tree
- Update defconfig to account for user LED and user key
- Move pin control mappings to the device tree

----------------------------------------------------------------
Linus Walleij (4):
      ARM: nomadik: convert all clocks except timer to dt
      ARM: nomadik: register clocksource from device tree
      ARM: nomadik: add led and key for S8815
      ARM: nomadik: move the pin configuration to DT

Rabin Vincent (1):
      clocksource: nomadik-mtu: support of probe

 .../devicetree/bindings/arm/ste-nomadik.txt        |   5 +
 arch/arm/boot/dts/ste-nomadik-s8815.dts            |  63 +++++++++
 arch/arm/boot/dts/ste-nomadik-stn8815.dtsi         | 145 ++++++++++++++++++++-
 arch/arm/configs/nhk8815_defconfig                 |   6 +
 arch/arm/mach-nomadik/Kconfig                      |   1 +
 arch/arm/mach-nomadik/cpu-8815.c                   |  73 +----------
 drivers/clk/clk-nomadik.c                          |  41 +-----
 drivers/clocksource/nomadik-mtu.c                  |  70 ++++++++--
 8 files changed, 288 insertions(+), 116 deletions(-)


From broonie at kernel.org  Sat May 25 16:10:32 2013
From: broonie at kernel.org (Mark Brown)
Date: Sat, 25 May 2013 16:10:32 -0400
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <CAGsJ_4zVOF8-g=emEGgP3atxkWdxMaQQiVZrZkht_WueTriSnw@mail.gmail.com>
References: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
 <20130516093846.GA2927@katana>
 <CAGsJ_4zVOF8-g=emEGgP3atxkWdxMaQQiVZrZkht_WueTriSnw@mail.gmail.com>
Message-ID: <20130525201032.GD32043@sirena.org.uk>

On Thu, May 16, 2013 at 06:25:39PM +0800, Barry Song wrote:
> 2013/5/16 Wolfram Sang <wsa at the-dreams.de>:

> > What about deferred probing?

> deferred probing could work but could not work for automative.
> what we really want is that devices begin to work as early as
> possible. we want i2c clients like lcd, camera begin to show images as
> early as possible as an automative requirement.

Probe deferral should have at most a mimimal impact on the boot time -
it's pretty much just changing the order providing the probe functions
aren't excessively slow to defer.  If the probe functions are taking a
long time to defer that's probably what needs looking at.

If it really is probe deferral itself that's too slow then we ought to
be looking at improving that rather than boding around it.
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From arnd at arndb.de  Sun May 26 16:46:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 26 May 2013 22:46:12 +0200
Subject: [RFC PATCHv4 1/6] arm: TI-Nspire platform code
In-Reply-To: <1369480087-24786-2-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-2-git-send-email-dt.tangr@gmail.com>
Message-ID: <201305262246.12803.arnd@arndb.de>

On Saturday 25 May 2013, Daniel Tang wrote:

> +static struct map_desc nspire_io_desc[] __initdata = {
> +	{
> +		.virtual	=  NSPIRE_EARLY_UART_VIRT_BASE,
> +		.pfn		= __phys_to_pfn(NSPIRE_EARLY_UART_PHYS_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE
> +	},

You  can remove this now and call debug_ll_io_init() instead, so you can
remove the duplicate definitions of the base addresses.

> +	{
> +		.virtual	=  NSPIRE_PWR_VIRT_BASE,
> +		.pfn		= __phys_to_pfn(NSPIRE_PWR_PHYS_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE
> +	}
> +};

And I think this one can be replaced with a call to of_iomap:

> +static void __init nspire_early_init(void)
> +{
> +	void __iomem *pwr = IOMEM(NSPIRE_PWR_VIRT_BASE);
> +
> +	/* Re-enable bus access to all peripherals */
> +	writel(0, pwr + NSPIRE_PWR_BUS_DISABLE1);
> +	writel(0, pwr + NSPIRE_PWR_BUS_DISABLE2);
> +
> +	pr_info("Re-enabled bus access to all peripherals\n");
> +}

Since it seems to be used only in this one function.

> +DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
> +	.map_io		= nspire_map_io,
> +	.init_irq	= irqchip_init,
> +	.init_time	= nspire_init_time,
> +	.init_machine	= nspire_init,
> +	.init_early	= nspire_early_init,
> +	.dt_compat	= nspire_dt_match,
> +	.restart	= nspire_restart,
> +MACHINE_END

The reference to irqchip_init is now the default, so you can drop that too.
nspire_init_time is still needed right now, but I'd like to initialize the
clocks automatically soon, so that will go away in the future.

Please reorder the other callbacks in call order, same as the structure
definition.

	Arnd


From arnd at arndb.de  Sun May 26 17:23:29 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 26 May 2013 23:23:29 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
Message-ID: <201305262323.29519.arnd@arndb.de>

On Saturday 25 May 2013, Daniel Tang wrote:
> Changes between v3 and v4:
> * Remove redundant clock-names in device tree
> * Re-enable bus access to some peripherals on bootup
> * Clean up nspire-classic-timer code.
>   - Implement a nspire_timer_set_mode function
>   - Removed messy IO_MATCHx and CNTL_MATCHx macros
>   - Timer starts disabled to begin with
>   - Interrupt handling code return IRQ_NONE for spurious interrupts
>   - Delete unnessecary shift
> * Change clk-nspire to use compatible property to determine IO type
> * Change device tree bindings to have appropriate vendor prefixes
> * Added device tree binding documentation
> * Fix incorrect register addresses for clocks
> * Use more specific .caps for CLCD

Looks really good now. I have a few more comments for the first patch,
mostly for stuff that can be simplified based on stuff we merged in 3.10.

The one remaining bit that sticks out is the clcd platform data. As I
said before, I won't require you to convert that to DT in order to
get your code merged, but I'd also really like to see that happen,
as we will also need that to get rid of auxdata on the ARM reference
platforms (integrator, versatile, realview, vexpress).

Are you motivated to look into those after the base patch gets
merged into arm-soc?

One comment on the merge path: While we can put any of the patches
into the arm-soc tree, my preference is definitely for the clk,
clksource, irqchip and input drivers to go through the respective
maintainer trees. There are no dependencies to worry about, since
each patch can compile standalone, and we just need to make sure
they all get into 3.11 for your platform to work.

	Arnd


From R64188 at freescale.com  Sun May 26 21:27:04 2013
From: R64188 at freescale.com (Jin Zhengxiong-R64188)
Date: Mon, 27 May 2013 01:27:04 +0000
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <20130523025059.GB2704@S2101-09.ap.freescale.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
 <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
 <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>
 <20130523025059.GB2704@S2101-09.ap.freescale.net>
Message-ID: <13F8657A829DAB49A2A937FD6FC10F790B3D5056@039-SN2MPN1-012.039d.mgd.msft.net>

> On Wed, May 22, 2013 at 08:59:20AM +0000, Jin Zhengxiong-R64188 wrote:
> > [Jason Jin-R64188] For the lpuart itself, I do not think it will have
> different version IP.
> 
> You can never tell in 5 or 10 years.  Also no major version doesn't
> necessarily mean no minor updates or revise.
> 
> > The general name is sufficient and soc related name can introduce the
> minor difference. If the there are update version, we can name it
> lpuart2.0 or something like that.
> >
> 
> Yeah, if IP designers name it lpuart2.0, it surely works.  But from my
> experience on IMX, hardware guys are not always properly updating IP name.
> Then the version 2.0 becomes a versioning given by software people which
> is improper to be used in compatible string.
> 
[Jason Jin-R64188] We had some internal discussion on this. For the lpuart itself, as we cannot get the version information at run time from the version register and lpuart is not publicly versioned, we agree to use the SoC name for lpuart. 
However, if the version information can be got from the register at run time, or the version was publicly versioned. the general name still useful than the SoC name. 
on the other side, the SoC itself may also have new versions, So the SoC name is also not a perfect solution.

> >
> 
> Think about it from "compatibility" point of view.  It does not cause
> confusion but just help understand the compatible history.  Saying the
> same IP is reused on LS-1 SoC, I do not see a problem with putting the
> following compatible into LS-1 <soc>.dtsi under UART node, to tell that
> the UART block on LS-1 is completely compatible with the one used on
> MVF600.
> 
>   compatible = "fsl,ls1-uart", "fsl,mvf600-uart";
> 
[Jason Jin-R64188] We'll leverage this compatible strings for compatible history. Thanks.
By the way, we'll change the SoC name from mvf600 to vf610 to align the description in the document. 



From gang.chen at asianux.com  Sun May 26 21:42:27 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 09:42:27 +0800
Subject: [PATCH] arch: arm64: kernel: sprintf(), 'str' needs additional
 1 byte for failure processing
In-Reply-To: <51A1E3B3.4060901@asianux.com>
References: <51A1E3B3.4060901@asianux.com>
Message-ID: <51A2BA03.4030006@asianux.com>

On 05/26/2013 06:28 PM, Chen Gang wrote:
> 
> When failure occurs at the last looping cycle (when 'i == 0'), it will
> print "bad PC value" instead of "(%08x) ", which needs additional 1
> byte.
> 
> If not add 1 byte, the str will not be NUL terminated, and the next
> printk() will cause issue.
> 

Oh, I type incorrect contents. It should be "If not add 1 byte, it will
memory overflow"

I will send patch v2.

> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/kernel/traps.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> index 61d7dd2..c2f68d2 100644
> --- a/arch/arm64/kernel/traps.c
> +++ b/arch/arm64/kernel/traps.c
> @@ -100,7 +100,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
>  {
>  	unsigned long addr = instruction_pointer(regs);
>  	mm_segment_t fs;
> -	char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
> +	char str[sizeof("00000000 ") * 5 + 2 + 1 + 1], *p = str;
>  	int i;
>  
>  	/*
> 


-- 
Chen Gang

Asianux Corporation


From 21cnbao at gmail.com  Sun May 26 21:54:56 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Mon, 27 May 2013 09:54:56 +0800
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <20130525201032.GD32043@sirena.org.uk>
References: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
 <20130516093846.GA2927@katana>
 <CAGsJ_4zVOF8-g=emEGgP3atxkWdxMaQQiVZrZkht_WueTriSnw@mail.gmail.com>
 <20130525201032.GD32043@sirena.org.uk>
Message-ID: <CAGsJ_4y6SY6nNkbW+Yh8jx0WB4Pi9MO1W3xVZcrQcedGeD5ogQ@mail.gmail.com>

2013/5/26 Mark Brown <broonie at kernel.org>:
> On Thu, May 16, 2013 at 06:25:39PM +0800, Barry Song wrote:
>> 2013/5/16 Wolfram Sang <wsa at the-dreams.de>:
>
>> > What about deferred probing?
>
>> deferred probing could work but could not work for automative.
>> what we really want is that devices begin to work as early as
>> possible. we want i2c clients like lcd, camera begin to show images as
>> early as possible as an automative requirement.
>
> Probe deferral should have at most a mimimal impact on the boot time -
> it's pretty much just changing the order providing the probe functions
> aren't excessively slow to defer.  If the probe functions are taking a
> long time to defer that's probably what needs looking at.
>
> If it really is probe deferral itself that's too slow then we ought to
> be looking at improving that rather than boding around it.

Mark, the case is not that deferred probing is slow or not. deferred
probing is pretty good.
the case is that we want to i2c and media connected with i2c probed
earlier than other devices.
in auto infotainment devices, we actually do some hacking in kernel
that makes rear view work earlier than other device driver
initialization with a kernel thread which take care of backing-car
policy not only mechanism. that means, we make camera work to see
backview image even earlier than other drivers' initialization.
we don't want media deferred to wait for i2c. we want make some early
jobs ready earlier.

-barry


From gang.chen at asianux.com  Sun May 26 22:00:12 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 10:00:12 +0800
Subject: [PATCH v2] arch: arm64: kernel: sprintf(), 'str' needs additional
 1 byte for failure processing
In-Reply-To: <51A1E3B3.4060901@asianux.com>
References: <51A1E3B3.4060901@asianux.com>
Message-ID: <51A2BE2C.2000004@asianux.com>


When failure occurs at the last looping cycle (when 'i == 0'), it will
print "bad PC value" instead of "(%08x) ", which needs additional 1
byte.

If not add 1 byte, the 'str' may be memory overflow.


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm64/kernel/traps.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 61d7dd2..c2f68d2 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -100,7 +100,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
 {
 	unsigned long addr = instruction_pointer(regs);
 	mm_segment_t fs;
-	char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
+	char str[sizeof("00000000 ") * 5 + 2 + 1 + 1], *p = str;
 	int i;
 
 	/*
-- 
1.7.7.6




From jg1.han at samsung.com  Sun May 26 22:05:03 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Mon, 27 May 2013 11:05:03 +0900
Subject: [PATCH V2] ARM: EXYNOS: add PM dependency to PM_GENERIC_DOMAINS
Message-ID: <000501ce5a7e$9a2b4830$ce81d890$@samsung.com>

PM_GENERIC_DOMAINS needs PM dependency.

Fixed build warning as below:

warning: (PLAT_S3C64XX && CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM)
warning: (PLAT_S3C64XX && CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM)
arch/arm/kernel/return_address.c:63:2: warning: #warning "TODO: return_address should use unwind tables" [-Wcpp]
drivers/base/power/domain.c: In function '__pm_genpd_add_device':
drivers/base/power/domain.c:1422:2: error: implicit declaration of function 'genpd_acquire_lock'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c:1466:2: error: implicit declaration of function 'genpd_release_lock'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c: In function 'pm_genpd_add_subdomain':
drivers/base/power/domain.c:1649:3: error: implicit declaration of function 'genpd_sd_counter_inc'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c: In function 'pm_genpd_remove_subdomain':
drivers/base/power/domain.c:1721:4: error: implicit declaration of function 'genpd_sd_counter_dec'
[-Werror=implicit-function-declaration]
drivers/base/power/domain.c: In function 'pm_genpd_attach_cpuidle':
drivers/base/power/domain.c:1887:2: error: implicit declaration of function 'genpd_recalc_cpu_exit_latency'
[-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
Changes since v1:
- Fixed PLAT_S3C64XX together as Kukjin Kim mentioned

 arch/arm/mach-exynos/Kconfig  |    2 +-
 arch/arm/mach-s3c64xx/Kconfig |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6e77432..352e8d0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -34,7 +34,7 @@ config CPU_EXYNOS4210
 	default y
 	depends on ARCH_EXYNOS4
 	select ARM_CPU_SUSPEND if PM
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
 	select SAMSUNG_DMADEV
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 2057853..c04c4ee 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C64XX
 	bool
 	depends on ARCH_S3C64XX
 	default y
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	select SAMSUNG_WAKEMASK
 	help
 	  Base platform code for any Samsung S3C64XX device
-- 
1.7.2.5




From jh80.chung at samsung.com  Sun May 26 23:49:24 2013
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Mon, 27 May 2013 12:49:24 +0900
Subject: [PATCH v2] mmc: dwmmc: let device core setup the default pin
 configuration
In-Reply-To: <1364882999-31670-1-git-send-email-thomas.abraham@linaro.org>
References: <1364882999-31670-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <51A2D7C4.2060100@samsung.com>

Minor comment,
Maybe Seungwon mentioned the prefix use as "dw_mmc".

Best Regards,
Jaehoon Chung

On 04/02/2013 03:09 PM, Thomas Abraham wrote:
> With device core now able to setup the default pin configuration,
> the pin configuration code based on the deprecated Samsung specific
> gpio bindings is removed.
> 
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Reviewed-by: Doug Anderson <dianders at chromium.org>
> Tested-by: Doug Anderson <dianders at chromium.org>
> ---
> 
> Hi Doug, Seungwon,
> 
> I apologize for the delaying in following up on the review comment.
> The setup_bus callback support has been removed in this patch. I did
> intend to retain the support for setup_bus callback in the previous
> version of this patch since any new platform that might use this
> driver and need such a callback would have this callback ready for
> use. But it seems removing the setup_bus callback is preferred, so
> I am fine with it.
> 
> Thomas.
> 
>  drivers/mmc/host/dw_mmc-exynos.c |   38 --------------------------------------
>  drivers/mmc/host/dw_mmc.c        |   14 +-------------
>  drivers/mmc/host/dw_mmc.h        |    3 ---
>  3 files changed, 1 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index 72fd0f2..467d043 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -152,43 +152,6 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>  	return 0;
>  }
>  
> -static int dw_mci_exynos_setup_bus(struct dw_mci *host,
> -				struct device_node *slot_np, u8 bus_width)
> -{
> -	int idx, gpio, ret;
> -
> -	if (!slot_np)
> -		return -EINVAL;
> -
> -	/* cmd + clock + bus-width pins */
> -	for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
> -		gpio = of_get_gpio(slot_np, idx);
> -		if (!gpio_is_valid(gpio)) {
> -			dev_err(host->dev, "invalid gpio: %d\n", gpio);
> -			return -EINVAL;
> -		}
> -
> -		ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
> -		if (ret) {
> -			dev_err(host->dev, "gpio [%d] request failed\n", gpio);
> -			return -EBUSY;
> -		}
> -	}
> -
> -	if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
> -		return 0;
> -
> -	gpio = of_get_named_gpio(slot_np, "samsung,cd-pinmux-gpio", 0);
> -	if (gpio_is_valid(gpio)) {
> -		if (devm_gpio_request(host->dev, gpio, "dw-mci-cd"))
> -			dev_err(host->dev, "gpio [%d] request failed\n", gpio);
> -	} else {
> -		dev_info(host->dev, "cd gpio not available");
> -	}
> -
> -	return 0;
> -}
> -
>  /* Exynos5250 controller specific capabilities */
>  static unsigned long exynos5250_dwmmc_caps[4] = {
>  	MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
> @@ -205,7 +168,6 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
>  	.prepare_command	= dw_mci_exynos_prepare_command,
>  	.set_ios		= dw_mci_exynos_set_ios,
>  	.parse_dt		= dw_mci_exynos_parse_dt,
> -	.setup_bus		= dw_mci_exynos_setup_bus,
>  };
>  
>  static const struct of_device_id dw_mci_exynos_match[] = {
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 9834221..adb1b7d 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -1878,7 +1878,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
>  	struct mmc_host *mmc;
>  	struct dw_mci_slot *slot;
>  	const struct dw_mci_drv_data *drv_data = host->drv_data;
> -	int ctrl_id, ret;
> +	int ctrl_id;
>  	u8 bus_width;
>  
>  	mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
> @@ -1935,14 +1935,6 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
>  	else
>  		bus_width = 1;
>  
> -	if (drv_data && drv_data->setup_bus) {
> -		struct device_node *slot_np;
> -		slot_np = dw_mci_of_find_slot_node(host->dev, slot->id);
> -		ret = drv_data->setup_bus(host, slot_np, bus_width);
> -		if (ret)
> -			goto err_setup_bus;
> -	}
> -
>  	switch (bus_width) {
>  	case 8:
>  		mmc->caps |= MMC_CAP_8_BIT_DATA;
> @@ -2006,10 +1998,6 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
>  	queue_work(host->card_workqueue, &host->card_work);
>  
>  	return 0;
> -
> -err_setup_bus:
> -	mmc_free_host(mmc);
> -	return -EINVAL;
>  }
>  
>  static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 53b8fd9..0b74189 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -190,7 +190,6 @@ extern int dw_mci_resume(struct dw_mci *host);
>   * @prepare_command: handle CMD register extensions.
>   * @set_ios: handle bus specific extensions.
>   * @parse_dt: parse implementation specific device tree properties.
> - * @setup_bus: initialize io-interface
>   *
>   * Provide controller implementation specific extensions. The usage of this
>   * data structure is fully optional and usage of each member in this structure
> @@ -203,7 +202,5 @@ struct dw_mci_drv_data {
>  	void		(*prepare_command)(struct dw_mci *host, u32 *cmdr);
>  	void		(*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
>  	int		(*parse_dt)(struct dw_mci *host);
> -	int		(*setup_bus)(struct dw_mci *host,
> -				struct device_node *slot_np, u8 bus_width);
>  };
>  #endif /* _DW_MMC_H_ */
> 



From acourbot at nvidia.com  Sun May 26 23:53:41 2013
From: acourbot at nvidia.com (Alexandre Courbot)
Date: Mon, 27 May 2013 12:53:41 +0900
Subject: [PATCH v2] video: simplefb: add mode parsing function
Message-ID: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>

The naming scheme of simplefb's mode is precise enough to allow building
the mode structure from it instead of using a static list of modes. This
patch introduces a function that does this. In case exotic modes that
cannot be represented from their name alone are needed, the static list
of modes is still available as a backup.

It also changes the order in which colors are declared from MSB first to
the more standard LSB first.

Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
Changes from v1:
- amended documentation following Stephen's suggestion
- allow parsing of bitfields larger than 9 bits
- made it clear that the parsing order of bits is changed with respect
  to the original patch

Andrew, since this patch introduces a (small) change in the DT bindings,
could we try to merge it during the -rc cycle so we don't have to come
with a more complex solution in the future?

 .../bindings/video/simple-framebuffer.txt          | 12 +++-
 drivers/video/simplefb.c                           | 72 +++++++++++++++++++++-
 2 files changed, 80 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/simple-framebuffer.txt b/Documentation/devicetree/bindings/video/simple-framebuffer.txt
index 3ea4605..18d03e2 100644
--- a/Documentation/devicetree/bindings/video/simple-framebuffer.txt
+++ b/Documentation/devicetree/bindings/video/simple-framebuffer.txt
@@ -10,8 +10,16 @@ Required properties:
 - width: The width of the framebuffer in pixels.
 - height: The height of the framebuffer in pixels.
 - stride: The number of bytes in each line of the framebuffer.
-- format: The format of the framebuffer surface. Valid values are:
-  - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b).
+- format: The format of the framebuffer surface. Described as a sequence of
+	channel/num-bits pairs, where each pair describes how many bits are used
+	by a given color channel. Value channels are "r" (red), "g" (green),
+	"b" (blue), "a" (alpha) and "x" (unused). Channels are listed in bit
+	order, starting from the LSB. For instance, a format named "r5g6b5"
+	describes a 16-bit format where red is encoded in the 5 less significant
+	bits, green in the 6 following ones, and blue in the 5 last:
+				BBBBBGGG GGGRRRRR
+				^               ^
+			       MSB             LSB
 
 Example:
 
diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c
index e2e9e3e..1430752 100644
--- a/drivers/video/simplefb.c
+++ b/drivers/video/simplefb.c
@@ -21,6 +21,7 @@
  */
 
 #include <linux/errno.h>
+#include <linux/ctype.h>
 #include <linux/fb.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -82,8 +83,72 @@ struct simplefb_format {
 	struct fb_bitfield transp;
 };
 
+static struct simplefb_format *simplefb_parse_format(struct device *dev,
+						     const char *str)
+{
+	struct simplefb_format *format;
+	unsigned int offset = 0;
+	unsigned int i = 0;
+
+	format = devm_kzalloc(dev, sizeof(*format), GFP_KERNEL);
+	if (!format)
+		return ERR_PTR(-ENOMEM);
+
+	while (str[i] != 0) {
+		struct fb_bitfield *field = NULL;
+		int length = 0;
+
+		switch (str[i++]) {
+		case 'r':
+		case 'R':
+			field = &format->red;
+			break;
+		case 'g':
+		case 'G':
+			field = &format->green;
+			break;
+		case 'b':
+		case 'B':
+			field = &format->blue;
+			break;
+		case 'a':
+		case 'A':
+			field = &format->transp;
+			break;
+		case 'x':
+		case 'X':
+			break;
+		default:
+			goto error;
+		}
+
+		if (!isdigit(str[i]))
+			goto error;
+
+		while (isdigit(str[i])) {
+			length = length * 10 + (str[i++] - '0');
+		}
+
+		if (field) {
+			field->offset = offset;
+			field->length = length;
+		}
+
+		offset += length;
+	}
+
+	format->bits_per_pixel = (offset + 7) & ~0x7;
+	format->name = str;
+	return format;
+
+error:
+	dev_err(dev, "Invalid format string\n");
+	return ERR_PTR(-EINVAL);
+}
+
+/* if you use exotic modes that simplefb_parse_format cannot decode, you can
+   specify them here. */
 static struct simplefb_format simplefb_formats[] = {
-	{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0} },
 };
 
 struct simplefb_params {
@@ -131,7 +196,10 @@ static int simplefb_parse_dt(struct platform_device *pdev,
 		params->format = &simplefb_formats[i];
 		break;
 	}
-	if (!params->format) {
+	if (!params->format)
+		params->format = simplefb_parse_format(&pdev->dev, format);
+
+	if (IS_ERR(params->format)) {
 		dev_err(&pdev->dev, "Invalid format value\n");
 		return -EINVAL;
 	}
-- 
1.8.3



From dt.tangr at gmail.com  Sun May 26 22:23:02 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Mon, 27 May 2013 12:23:02 +1000
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <201305262323.29519.arnd@arndb.de>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
Message-ID: <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>


On 27/05/2013, at 7:23 AM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Saturday 25 May 2013, Daniel Tang wrote:
>> Changes between v3 and v4:
>> * Remove redundant clock-names in device tree
>> * Re-enable bus access to some peripherals on bootup
>> * Clean up nspire-classic-timer code.
>>  - Implement a nspire_timer_set_mode function
>>  - Removed messy IO_MATCHx and CNTL_MATCHx macros
>>  - Timer starts disabled to begin with
>>  - Interrupt handling code return IRQ_NONE for spurious interrupts
>>  - Delete unnessecary shift
>> * Change clk-nspire to use compatible property to determine IO type
>> * Change device tree bindings to have appropriate vendor prefixes
>> * Added device tree binding documentation
>> * Fix incorrect register addresses for clocks
>> * Use more specific .caps for CLCD
> 
> Looks really good now. I have a few more comments for the first patch,
> mostly for stuff that can be simplified based on stuff we merged in 3.10.
> 
> The one remaining bit that sticks out is the clcd platform data. As I
> said before, I won't require you to convert that to DT in order to
> get your code merged, but I'd also really like to see that happen,
> as we will also need that to get rid of auxdata on the ARM reference
> platforms (integrator, versatile, realview, vexpress).

How would you like me to convert the platform data to DT? AFAIK, the clcd driver isn't aware of DT so the only way is to use the AUXDATA right now.

> 
> Are you motivated to look into those after the base patch gets
> merged into arm-soc?

Of course.

> 
> One comment on the merge path: While we can put any of the patches
> into the arm-soc tree, my preference is definitely for the clk,
> clksource, irqchip and input drivers to go through the respective
> maintainer trees. There are no dependencies to worry about, since
> each patch can compile standalone, and we just need to make sure
> they all get into 3.11 for your platform to work.

Yeah that's totally fine.

> 
> 	Arnd

Cheers,
Daniel Tang

From dt.tangr at gmail.com  Mon May 27 00:07:05 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Mon, 27 May 2013 14:07:05 +1000
Subject: [RFC PATCHv4 1/6] arm: TI-Nspire platform code
In-Reply-To: <201305262246.12803.arnd@arndb.de>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-2-git-send-email-dt.tangr@gmail.com>
 <201305262246.12803.arnd@arndb.de>
Message-ID: <3ED6FFF2-89E2-4426-8DDC-10B4E6C79F26@gmail.com>


On 27/05/2013, at 6:46 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> 
> 
>> +	{
>> +		.virtual	=  NSPIRE_PWR_VIRT_BASE,
>> +		.pfn		= __phys_to_pfn(NSPIRE_PWR_PHYS_BASE),
>> +		.length		= SZ_4K,
>> +		.type		= MT_DEVICE
>> +	}
>> +};
> 
> And I think this one can be replaced with a call to of_iomap:

Does of_iomap work that early in the boot process?

Cheers,
Daniel Tang



From shawn.guo at linaro.org  Mon May 27 01:57:37 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 13:57:37 +0800
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <13F8657A829DAB49A2A937FD6FC10F790B3D5056@039-SN2MPN1-012.039d.mgd.msft.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
 <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
 <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>
 <20130523025059.GB2704@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3D5056@039-SN2MPN1-012.039d.mgd.msft.net>
Message-ID: <20130527055734.GD7782@S2101-09.ap.freescale.net>

On Mon, May 27, 2013 at 01:27:04AM +0000, Jin Zhengxiong-R64188 wrote:
> By the way, we'll change the SoC name from mvf600 to vf610 to align the description in the document. 
> 

Such product renaming in documents happen on IMX as well, but we do
not bother to churn the source tree (file, function renaming) to catch
up with it, as long as we know what it is.

For this mvf600 to vf610 renaming, if you want to catch up with it, you
will need to rename a bunch of files functions, compatibles in Jingchang's
series, and it's probably fine even though it's not really necessary
since they haven't been merged.  But for those which have been merged,
like fec compatible string, doing this will probably piss off
maintainers.  So I would suggest that we stick to name mvf600 in the
source tree, and just be aware of it's the equivalent of vf610.

Shawn



From yadi.brar01 at gmail.com  Mon May 27 02:35:06 2013
From: yadi.brar01 at gmail.com (Yadwinder Singh Brar)
Date: Mon, 27 May 2013 12:05:06 +0530
Subject: [RESEND PATCH 2/5] clk: samsung: Add support to register
 rate_table for PLL3xxx
In-Reply-To: <2606875.QmniDqB8hY@flatron>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
 <1369391478-7665-3-git-send-email-vikas.sajjan@linaro.org>
 <2606875.QmniDqB8hY@flatron>
Message-ID: <CAKew6eVTeybXi3xzYWQ8wufFybifdhjD0iTce-w5DbQ=WyPjdg@mail.gmail.com>

Hi Tomasz,

On Sat, May 25, 2013 at 3:34 AM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> Hi,
>
> Please see my comments inline.
>
> On Friday 24 of May 2013 16:01:15 Vikas Sajjan wrote:
>> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>>
>> This patch defines a common rate_table which will contain recommended p,
>> m, s and k values for supported rates that needs to be changed for
>> changing corresponding PLL's rate.
>> It also sorts the rate table while registering the PLL rate table.
>> So that this sorted table can be used for making the searching of
>> "required rate" efficient.
>>
>> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
>>  drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
>>  drivers/clk/samsung/clk-pll.c        |   35
>> ++++++++++++++++++++++++++++++++-- drivers/clk/samsung/clk-pll.h
>> |   27 ++++++++++++++++++++++++-- 4 files changed, 69 insertions(+), 15
>> deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos4.c
>> b/drivers/clk/samsung/clk-exynos4.c index cf7d4e7..beff8a1 100644
>> --- a/drivers/clk/samsung/clk-exynos4.c
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node
>> *np, enum exynos4_soc exynos4_so reg_base + VPLL_CON0, pll_4650c);
>>       } else {
>>               apll = samsung_clk_register_pll35xx("fout_apll",
> "fin_pll",
>> -                                     reg_base + APLL_LOCK);
>> +                                     reg_base + APLL_LOCK, NULL, 0);
>>               mpll = samsung_clk_register_pll35xx("fout_mpll",
> "fin_pll",
>> -                                     reg_base + E4X12_MPLL_LOCK);
>> +                                     reg_base + E4X12_MPLL_LOCK, NULL,
> 0);
>>               epll = samsung_clk_register_pll36xx("fout_epll",
> "fin_pll",
>> -                                     reg_base + EPLL_LOCK);
>> +                                     reg_base + EPLL_LOCK, NULL, 0);
>>               vpll = samsung_clk_register_pll36xx("fout_vpll",
> "fin_pll",
>> -                                     reg_base + VPLL_LOCK);
>> +                                     reg_base + VPLL_LOCK, NULL, 0);
>>       }
>>
>>       samsung_clk_add_lookup(apll, fout_apll);
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c
>> b/drivers/clk/samsung/clk-exynos5250.c index 687b580..ddf10ca 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node
>> *np) ext_clk_match);
>>
>>       apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
>> -                     reg_base);
>> +                     reg_base, NULL, 0);
>>       mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
>> -                     reg_base + 0x4000);
>> +                     reg_base + 0x4000, NULL, 0);
>>       bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
>> -                     reg_base + 0x20010);
>> +                     reg_base + 0x20010, NULL, 0);
>>       gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
>> -                     reg_base + 0x10050);
>> +                     reg_base + 0x10050, NULL, 0);
>>       cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
>> -                     reg_base + 0x10020);
>> +                     reg_base + 0x10020, NULL, 0);
>>       epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
>> -                     reg_base + 0x10030);
>> +                     reg_base + 0x10030, NULL, 0);
>>       vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
>> -                     reg_base + 0x10040);
>> +                     reg_base + 0x10040, NULL, 0);
>>
>>       samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
>>                       ARRAY_SIZE(exynos5250_fixed_rate_clks));
>> diff --git a/drivers/clk/samsung/clk-pll.c
>> b/drivers/clk/samsung/clk-pll.c index 01f17cf..b8c0260 100644
>> --- a/drivers/clk/samsung/clk-pll.c
>> +++ b/drivers/clk/samsung/clk-pll.c
>> @@ -10,12 +10,15 @@
>>  */
>>
>>  #include <linux/errno.h>
>> +#include <linux/sort.h>
>>  #include "clk.h"
>>  #include "clk-pll.h"
>>
>>  struct samsung_clk_pll {
>>       struct clk_hw           hw;
>>       const void __iomem      *base;
>> +     struct samsung_pll_rate_table *rate_table;
>> +     unsigned int rate_count;
>>  };
>>
>>  #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
>> @@ -25,6 +28,14 @@ struct samsung_clk_pll {
>>  #define pll_writel(pll, val, offset)                                 \
>>               __raw_writel(val, (void __iomem *)(pll->base + (offset)));
>>
>> +static int samsung_compare_rate(const void *_a, const void *_b)
>> +{
>> +     const struct samsung_pll_rate_table *a = _a;
>> +     const struct samsung_pll_rate_table *b = _b;
>> +
>> +     return a->rate - b->rate;
>> +}
>> +
>>  /*
>>   * PLL35xx Clock Type
>>   */
>> @@ -62,7 +73,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops =
>> { };
>>
>>  struct clk * __init samsung_clk_register_pll35xx(const char *name,
>> -                     const char *pname, const void __iomem *base)
>> +                     const char *pname, const void __iomem *base,
>> +                     struct samsung_pll_rate_table *rate_table,
>> +                     const unsigned int rate_count)
>>  {
>>       struct samsung_clk_pll *pll;
>>       struct clk *clk;
>> @@ -82,6 +95,14 @@ struct clk * __init
>> samsung_clk_register_pll35xx(const char *name,
>>
>>       pll->hw.init = &init;
>>       pll->base = base;
>> +     pll->rate_table = rate_table;
>> +     pll->rate_count = rate_count;
>> +
>> +     if (pll->rate_table && pll->rate_count) {
>
> You seem to assume here that the exact set of rates is known at
> compilation time. In other words, you assume that all boards have the same
> PLL input (xtal) frequency.
>

Hmm .. not exactly same. I assumed that while registering a particular PLL,
required rates and parent of that PLL will be known(as in existing scenarios).
So we can provide a table containing valid supported rates with
recommended p, m, s values while registering  a particular PLL instance.
That table can also be provided at compilation time or can be initialized
before registering PLL depending upon SoC and parent.

> We have similar patches available in our internal tree that work in a bit
> different way:
>
> 1) they assume that passed array is already sorted, which is a good
> assumption, because you have full control of this array - it's a part of
> the clock driver and if it's incorrect it's your fault - you don't deal
> with data input by user
>

but the sorting is just one time job and we will be on safer side.

> 2) passed array don't have defined rates, but rather only all the relevant
> PLL coefficients; the frequency for each entry is calculated at
> registration time, based on rate of parent clock
>
> 3) the table is NULL terminated, without the need to pass its size, but
> it's just a matter of preference
>
>> +             sort(pll->rate_table, pll->rate_count,
>> +                     sizeof(struct samsung_pll_rate_table),
>> +                     samsung_compare_rate, NULL);
>> +     }
>>
>>       clk = clk_register(NULL, &pll->hw);
>>       if (IS_ERR(clk)) {
>> @@ -137,7 +158,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops
>> = { };
>>
>>  struct clk * __init samsung_clk_register_pll36xx(const char *name,
>> -                     const char *pname, const void __iomem *base)
>> +                     const char *pname, const void __iomem *base,
>> +                     struct samsung_pll_rate_table *rate_table,
>> +                     const unsigned int rate_count)
>>  {
>>       struct samsung_clk_pll *pll;
>>       struct clk *clk;
>> @@ -157,6 +180,14 @@ struct clk * __init
>> samsung_clk_register_pll36xx(const char *name,
>>
>>       pll->hw.init = &init;
>>       pll->base = base;
>> +     pll->rate_table = rate_table;
>> +     pll->rate_count = rate_count;
>> +
>> +     if (pll->rate_table && pll->rate_count) {
>> +             sort(pll->rate_table, pll->rate_count,
>> +                     sizeof(struct samsung_pll_rate_table),
>> +                     samsung_compare_rate, NULL);
>> +     }
>>
>>       clk = clk_register(NULL, &pll->hw);
>>       if (IS_ERR(clk)) {
>> diff --git a/drivers/clk/samsung/clk-pll.h
>> b/drivers/clk/samsung/clk-pll.h index 1329522..b5e12430 100644
>> --- a/drivers/clk/samsung/clk-pll.h
>> +++ b/drivers/clk/samsung/clk-pll.h
>> @@ -12,6 +12,25 @@
>>  #ifndef __SAMSUNG_CLK_PLL_H
>>  #define __SAMSUNG_CLK_PLL_H
>>
>> +#define PLL_35XX_RATE(_rate, _m, _p, _s)                     \
>> +     {                                                       \
>> +             .rate = _rate,                                  \
>> +             .pll_con0 = ((_m) << 16 | (_p) << 8 | (_s)),    \
>> +     }
>> +
>> +#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)                 \
>> +     {                                                       \
>> +             .rate = _rate,                                  \
>> +             .pll_con0 = ((_m) << 16 | (_p) << 8 | (_s)),    \
>> +             .pll_con1 = _k,                                 \
>> +     }
>> +
>> +struct samsung_pll_rate_table {
>> +     unsigned  int rate;
>> +     u32 pll_con0;
>> +     u32 pll_con1;
>
> I don't like this struct. What about PLLs that don't have con0 or con1,
> but rather a completely weird register strukture like PLL_P_REG,
> PLL_M_REG, PLL_S_REG? The structure has generic name, which suggests that
> it should be able to handle any future Samsung PLLs as well.
>

We have derived  this struct looking at existing PLL3xxx and PLL4xxx registers.

> I'd suggest storing all coefficients as separate fields of the struct,
> e.g.
>
> struct samsung_pll_rate_table {
>         unsigned  int rate;
>         /* ... */
>         unsigned int p;
>         unsigned int m;
>         unsigned int s;
>         /* ... */
> };
>

Hmm .. it will fine, we can use it.

Regards,
Yadwinder

> Best regards,
> Tomasz
>
>> +};
>> +
>>  enum pll45xx_type {
>>       pll_4500,
>>       pll_4502,
>> @@ -25,9 +44,13 @@ enum pll46xx_type {
>>  };
>>
>>  extern struct clk * __init samsung_clk_register_pll35xx(const char
>> *name, -                      const char *pname, const void __iomem
> *base);
>> +                     const char *pname, const void __iomem *base,
>> +                     struct samsung_pll_rate_table *rate_table,
>> +                     const unsigned int rate_count);
>>  extern struct clk * __init samsung_clk_register_pll36xx(const char
>> *name, -                      const char *pname, const void __iomem
> *base);
>> +                     const char *pname, const void __iomem *base,
>> +                     struct samsung_pll_rate_table *rate_table,
>> +                     const unsigned int rate_count);
>>  extern struct clk * __init samsung_clk_register_pll45xx(const char
>> *name, const char *pname, const void __iomem *con_reg,
>>                       enum pll45xx_type type);


From shawn.guo at linaro.org  Mon May 27 02:34:49 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 14:34:49 +0800
Subject: [PATCH v3 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369389564-13181-2-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
 <1369389564-13181-2-git-send-email-b32955@freescale.com>
Message-ID: <20130527063448.GF7782@S2101-09.ap.freescale.net>

On Fri, May 24, 2013 at 05:59:19PM +0800, Huang Shijie wrote:
> +Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
> +
> +	weim: weim at 021b8000 {
> +		compatible = "fsl,imx6q-weim";
> +		reg = <0x021b8000 0x4000>;
> +		clocks = <&clks 196>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0x08000000 0x08000000>;
> +
> +		nor at 0,0 {
> +			compatible = "cfi-flash";
> +			reg = <0 0 0x02000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			bank-width = <2>;
> +
Nit: remove this unneeded blank line.
> +			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
> +					0x0000C000 0x1404a38e 0x00000000>;

Nit: please consistently use lower case for hex value.

Please update patch #6 as well.

Other than that,

Reviewed-by: Shawn Guo <shawn.guo at linaro.org>

> +		};
> +	};



From yadi.brar01 at gmail.com  Mon May 27 02:36:14 2013
From: yadi.brar01 at gmail.com (Yadwinder Singh Brar)
Date: Mon, 27 May 2013 12:06:14 +0530
Subject: [RESEND PATCH 3/5] clk: samsung: Add set_rate() clk_ops for
 PLL35xx
In-Reply-To: <2621811.AH1nnyyD7h@flatron>
References: <1369391478-7665-1-git-send-email-vikas.sajjan@linaro.org>
 <1369391478-7665-4-git-send-email-vikas.sajjan@linaro.org>
 <2621811.AH1nnyyD7h@flatron>
Message-ID: <CAKew6eWNE3ZTckWprxu=arRsVaq5ShmEHwDftNmHDy0u8w1i7A@mail.gmail.com>

On Sat, May 25, 2013 at 3:49 AM, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> Hi,
>
> On Friday 24 of May 2013 16:01:16 Vikas Sajjan wrote:
>> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>>
>> Adds set_rate() and round_rate() clk_ops for PLL35xx
>>
>> The round_rate() implemenation as of now is dummy, it returns the same
>> rate which is passed as input.
>>
>> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
>> ---
>>  drivers/clk/samsung/clk-pll.c |   95
>> ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 94
>> insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-pll.c
>> b/drivers/clk/samsung/clk-pll.c index b8c0260..291cc9e 100644
>> --- a/drivers/clk/samsung/clk-pll.c
>> +++ b/drivers/clk/samsung/clk-pll.c
>> @@ -11,6 +11,7 @@
>>
>>  #include <linux/errno.h>
>>  #include <linux/sort.h>
>> +#include <linux/bsearch.h>
>>  #include "clk.h"
>>  #include "clk-pll.h"
>>
>> @@ -36,6 +37,21 @@ static int samsung_compare_rate(const void *_a, const
>> void *_b) return a->rate - b->rate;
>>  }
>>
>> +static struct samsung_pll_rate_table *samsung_get_pll_settings(
>> +                             struct samsung_clk_pll *pll, unsigned long
> rate)
>> +{
>> +     struct samsung_pll_rate_table req_rate, *tmp;
>> +
>> +     req_rate.rate = rate;
>> +     tmp = bsearch(&req_rate, pll->rate_table, pll->rate_count,
>> +                     sizeof(struct samsung_pll_rate_table),
>> +                     samsung_compare_rate);
>
> Binary search over < 10 entries? Isn't it a bit of overkill?
>

Sorry, i couldn't see any over kill?  And it may NOT be always < 10.

>> +     if (tmp)
>> +             return tmp;
>> +
>> +     return NULL;
>> +}
>> +
>>  /*
>>   * PLL35xx Clock Type
>>   */
>> @@ -46,9 +62,15 @@ static int samsung_compare_rate(const void *_a, const
>> void *_b) #define PLL35XX_MDIV_MASK       (0x3FF)
>>  #define PLL35XX_PDIV_MASK       (0x3F)
>>  #define PLL35XX_SDIV_MASK       (0x7)
>> +#define PLL35XX_LOCK_STAT_MASK  (0x1)
>>  #define PLL35XX_MDIV_SHIFT      (16)
>>  #define PLL35XX_PDIV_SHIFT      (8)
>>  #define PLL35XX_SDIV_SHIFT      (0)
>> +#define PLL35XX_LOCK_STAT_SHIFT (29)
>> +
>> +#define PLL35XX_MDIV(_tmp) ((_tmp) & (PLL35XX_MDIV_MASK <<
>> PLL35XX_MDIV_SHIFT)) +#define PLL35XX_PDIV(_tmp) ((_tmp) &
>> (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT)) +#define PLL35XX_SDIV(_tmp)
>> ((_tmp) & (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT))
>>
>>  static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
>>                               unsigned long parent_rate)
>> @@ -68,8 +90,76 @@ static unsigned long
>> samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned
>> long)fvco;
>>  }
>>
>> -static const struct clk_ops samsung_pll35xx_clk_ops = {
>> +static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32
>> pll_con) +{
>> +     if ((mdiv != PLL35XX_MDIV(pll_con)) || (pdiv !=
>> PLL35XX_PDIV(pll_con))) +             return 1;
>> +     else
>> +             return 0;
>> +}
>> +
>> +static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long
>> drate, +                                      unsigned long prate)
>> +{
>> +     struct samsung_clk_pll *pll = to_clk_pll(hw);
>> +     struct samsung_pll_rate_table *rate;
>> +
>> +     u32 tmp, mdiv, pdiv, sdiv;
>> +
>> +     /* Get required rate settings from table */
>> +     rate = samsung_get_pll_settings(pll, drate);
>> +     if (!rate) {
>> +             pr_err("%s: Invalid rate : %lu for pll clk %s\n",
> __func__,
>> +                     drate, __clk_get_name(hw->clk));
>> +             return -EINVAL;
>> +     }
>> +
>> +     mdiv = PLL35XX_MDIV(rate->pll_con0);
>> +     pdiv = PLL35XX_PDIV(rate->pll_con0);
>> +     sdiv = PLL35XX_SDIV(rate->pll_con0);
>
> You wouldn't need to use those macros if all coefficients were stored as
> separate fields in the struct.
>

Agree, I will use that.

>> +
>> +     tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
>> +
>> +     if (!(samsung_pll35xx_mp_change(mdiv, pdiv, tmp))) {
>> +             /* If only s change, change just s value only*/
>> +             tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
>> +             tmp |= sdiv;
>
> This line is correct, but it looks like it wasn't, because:
> a) the name suggests that it contains the raw value of S coefficient
> b) it's real value is hidden between a macro, name of which suggests the
> same as in a) as well.
>
> This makes the code hard to read.
>

We can rename sdiv to sdiv_regval ?? , to improve readability.

>> +             pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
>> +     } else {
>> +             /* Set PLL lock time.
>> +                Maximum lock time can be 270 * PDIV cycles */
>> +             pll_writel(pll, (pdiv >> PLL35XX_PDIV_SHIFT) * 270,
>> +                             PLL35XX_LOCK_OFFSET);
>
> Hmm, magic constant in the code? Shouldn't it be defined as a macro?
>

Ya, I will define it.

>> +
>> +             /* Change PLL PMS values */
>> +             tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
>> +                             (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT)
> |
>> +                             (PLL35XX_SDIV_MASK <<
> PLL35XX_SDIV_SHIFT));
>> +             tmp |= mdiv | pdiv | sdiv;
>
> This looks strange as well, even if it's correct.
>
>> +             pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
>> +
>> +             /* wait_lock_time */
>> +             do {
>> +                     cpu_relax();
>> +                     tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
>> +             } while (!(tmp & (PLL35XX_LOCK_STAT_MASK
>> +                             << PLL35XX_LOCK_STAT_SHIFT)));
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static long samsung_pll35xx_round_rate(struct clk_hw *hw,
>> +                     unsigned long drate, unsigned long *prate)
>> +{
>> +     /* Clock framework cries without this, so implemented dummy */
>
> This is completely wrong. Have you tested this code or read how Common
> Clock Framework works?
>

As its mentioned in commit message, its just a dummy function to
make set_rate() work. We will implement it later in different patch.
In existing scenario users are requesting  valid rates provided
in table so it works fine with this dummy function.

> clk_set_rate() first calls ->round_rate() to get a rate supported by the
> clock that is nearest and not higher than requested rate and only then it
> calls ->set_rate() with the rate returned by ->round_rate().
>
> So the round_rate() callback must return the highest supported rate with
> parent clock at prate and not higher than drate.
>
>> +     return drate;
>> +}
>> +
>> +static struct clk_ops samsung_pll35xx_clk_ops = {
>>       .recalc_rate = samsung_pll35xx_recalc_rate,
>> +     .round_rate = samsung_pll35xx_round_rate,
>> +     .set_rate = samsung_pll35xx_set_rate,
>>  };
>>
>>  struct clk * __init samsung_clk_register_pll35xx(const char *name,
>> @@ -102,6 +192,9 @@ struct clk * __init
>> samsung_clk_register_pll35xx(const char *name, sort(pll->rate_table,
>> pll->rate_count,
>>                       sizeof(struct samsung_pll_rate_table),
>>                       samsung_compare_rate, NULL);
>> +     } else {
>> +             samsung_pll35xx_clk_ops.round_rate = NULL;
>> +             samsung_pll35xx_clk_ops.set_rate = NULL;
>
> This is completely wrong. You are changing a static structure that is used
> for all instances of PLL35xx, not only the one being registered at the
> moment.
>

Yes,  will rectify it.

> Best regards,
> Tomasz
>
>>       }
>>
>>       clk = clk_register(NULL, &pll->hw);

Thanks for review.

Regards,
Yadwinder


From shawn.guo at linaro.org  Mon May 27 02:48:15 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 14:48:15 +0800
Subject: [PATCH v3 4/6] ARM: dts: imx6q: add pinctrls for WEIM NOR
In-Reply-To: <1369389564-13181-5-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
 <1369389564-13181-5-git-send-email-b32955@freescale.com>
Message-ID: <20130527064813.GG7782@S2101-09.ap.freescale.net>

On Fri, May 24, 2013 at 05:59:22PM +0800, Huang Shijie wrote:
> Add two pinctrls for WEIM:
>    one for the weim nor, another for the chipselect.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   61 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 61 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..7c5bcf4 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -323,6 +323,67 @@
>  						>;
>  					};
>  				};
> +
> +				weim {
> +					pinctrl_weim_cs_0: weim_norgrp-1 {

To follow the naming pattern, the ones below are probably better.

pinctrl_weim_cs0_1: weimcs0grp-1

> +						fsl,pins = <
> +							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
> +							>;
Nit: fix the indention please.

> +					};
> +
> +					pinctrl_weim_nor_1: weim_norgrp-2 {

s/weim_norgrp-2/weimnorgrp-1

> +						fsl,pins = <
> +							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
> +							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
> +							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
> +
Nit: Remove this blank line.

> +							/* data */
> +							MX6Q_PAD_EIM_D16__EIM_DATA16 0xb0b1
> +							MX6Q_PAD_EIM_D17__EIM_DATA17 0xb0b1
> +							MX6Q_PAD_EIM_D18__EIM_DATA18 0xb0b1
> +							MX6Q_PAD_EIM_D19__EIM_DATA19 0xb0b1
> +							MX6Q_PAD_EIM_D20__EIM_DATA20 0xb0b1
> +							MX6Q_PAD_EIM_D21__EIM_DATA21 0xb0b1
> +							MX6Q_PAD_EIM_D22__EIM_DATA22 0xb0b1
> +							MX6Q_PAD_EIM_D23__EIM_DATA23 0xb0b1
> +							MX6Q_PAD_EIM_D24__EIM_DATA24 0xb0b1
> +							MX6Q_PAD_EIM_D25__EIM_DATA25 0xb0b1
> +							MX6Q_PAD_EIM_D26__EIM_DATA26 0xb0b1
> +							MX6Q_PAD_EIM_D27__EIM_DATA27 0xb0b1
> +							MX6Q_PAD_EIM_D28__EIM_DATA28 0xb0b1
> +							MX6Q_PAD_EIM_D29__EIM_DATA29 0xb0b1
> +							MX6Q_PAD_EIM_D30__EIM_DATA30 0xb0b1
> +							MX6Q_PAD_EIM_D31__EIM_DATA31 0xb0b1
> +
Ditto

Above comments apply on the next patch as well.

Shawn

> +							/* address */
> +							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
> +							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
> +							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
> +							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
> +							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
> +							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
> +							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
> +							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
> +							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
> +							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
> +							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
> +							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
> +							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
> +							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
> +							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
> +							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
> +							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
> +							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
> +							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
> +							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
> +							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
> +							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
> +							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
> +							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
> +						>;
> +					};
> +
> +				};
>  			};
>  		};
>  
> -- 
> 1.7.1
> 
> 



From arnd at arndb.de  Mon May 27 02:56:19 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 08:56:19 +0200
Subject: [RFC PATCHv4 1/6] arm: TI-Nspire platform code
In-Reply-To: <3ED6FFF2-89E2-4426-8DDC-10B4E6C79F26@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262246.12803.arnd@arndb.de>
 <3ED6FFF2-89E2-4426-8DDC-10B4E6C79F26@gmail.com>
Message-ID: <201305270856.19456.arnd@arndb.de>

On Monday 27 May 2013, Daniel Tang wrote:
> 
> On 27/05/2013, at 6:46 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > 
> > 
> >> +    {
> >> +            .virtual        =  NSPIRE_PWR_VIRT_BASE,
> >> +            .pfn            = __phys_to_pfn(NSPIRE_PWR_PHYS_BASE),
> >> +            .length         = SZ_4K,
> >> +            .type           = MT_DEVICE
> >> +    }
> >> +};
> > 
> > And I think this one can be replaced with a call to of_iomap:
> 
> Does of_iomap work that early in the boot process?

Not from map_io, but soon after. What is the fist place you
really need it?

	Arnd


From andriy.shevchenko at linux.intel.com  Mon May 27 03:11:07 2013
From: andriy.shevchenko at linux.intel.com (Andy Shevchenko)
Date: Mon, 27 May 2013 10:11:07 +0300
Subject: [PATCH] dmatest: do not allow to interrupt ongoing tests
In-Reply-To: <Pine.LNX.4.64.1305242353210.7187@axis700.grange>
References: <1369308593-3723-1-git-send-email-andriy.shevchenko@linux.intel.com>
 <Pine.LNX.4.64.1305242353210.7187@axis700.grange>
Message-ID: <1369638667.29283.197.camel@smile>

On Fri, 2013-05-24 at 23:55 +0200, Guennadi Liakhovetski wrote: 
> On Thu, 23 May 2013, Andy Shevchenko wrote:
> 
> > When user interrupts ongoing transfers the dmatest may end up with console
> > lockup, oops, or data mismatch. This patch prevents user to abort any ongoing
> > test.
> 
> Personally I would be against such a change. What about interrupting the 
> test with rmmod?
>  Is it still possible after this your patch or not? If not 
> - this doesn't seem like a good idea to me. Why don't we just fix those 
> bugs, that you're describing?

The behaviour of the module is returned to the same page by this patch
as it was before (w/o debugfs).

The user can interrupt tests by rmmod, but it will take time up to
timeout.

I appreciate if you can do a deeper analysis of what happened in
case Will reported.

-- 
Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Intel Finland Oy


From shawn.guo at linaro.org  Mon May 27 03:16:38 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 15:16:38 +0800
Subject: [PATCH 1/2] ARM: imx: irq-common: Include header to avoid sparse
 warning
In-Reply-To: <1369425342-20153-1-git-send-email-festevam@gmail.com>
References: <1369425342-20153-1-git-send-email-festevam@gmail.com>
Message-ID: <20130527071637.GL7782@S2101-09.ap.freescale.net>

On Fri, May 24, 2013 at 04:55:41PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Fix the following sparse warning:
> 
> arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'mxc_set_irq_fiq' was not declared. Should it be static?
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Both applied, thanks.



From pgaikwad at nvidia.com  Mon May 27 03:40:09 2013
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 27 May 2013 13:10:09 +0530
Subject: [PATCH v2] clk: tegra: Use common of_clk_init function
Message-ID: <1369640409-1981-1-git-send-email-pgaikwad@nvidia.com>

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---

Included initialization for T114 in V2.

---
 arch/arm/mach-tegra/common.c     |    4 ++--
 drivers/clk/tegra/clk-tegra114.c |    3 ++-
 drivers/clk/tegra/clk-tegra20.c  |    3 ++-
 drivers/clk/tegra/clk-tegra30.c  |    3 ++-
 drivers/clk/tegra/clk.c          |   12 ------------
 drivers/clk/tegra/clk.h          |   18 ------------------
 include/linux/clk/tegra.h        |    1 -
 7 files changed, 8 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..95ce2a0 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,7 +23,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irqchip.h>
-#include <linux/clk/tegra.h>
+#include <linux/clk-provider.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -59,7 +59,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-	tegra_clocks_init();
+	of_clk_init(NULL);
 	tegra_pmc_init();
 	tegra_init_irq();
 	irqchip_init();
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..e0ee077 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2030,7 +2030,7 @@ static void __init tegra114_clock_apply_init_table(void)
 	tegra_init_from_table(init_table, clks, clk_max);
 }
 
-void __init tegra114_clock_init(struct device_node *np)
+static void __init tegra114_clock_init(struct device_node *np)
 {
 	struct device_node *node;
 	int i;
@@ -2083,3 +2083,4 @@ void __init tegra114_clock_init(struct device_node *np)
 
 	tegra_cpu_car_ops = &tegra114_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 8292a00..a25e07c 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1282,7 +1282,7 @@ static const struct of_device_id pmc_match[] __initconst = {
 	{},
 };
 
-void __init tegra20_clock_init(struct device_node *np)
+static void __init tegra20_clock_init(struct device_node *np)
 {
 	int i;
 	struct device_node *node;
@@ -1334,3 +1334,4 @@ void __init tegra20_clock_init(struct device_node *np)
 
 	tegra_cpu_car_ops = &tegra20_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c6921f5..985ad69 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1953,7 +1953,7 @@ static const struct of_device_id pmc_match[] __initconst = {
 	{},
 };
 
-void __init tegra30_clock_init(struct device_node *np)
+static void __init tegra30_clock_init(struct device_node *np)
 {
 	struct device_node *node;
 	int i;
@@ -2004,3 +2004,4 @@ void __init tegra30_clock_init(struct device_node *np)
 
 	tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 923ca7e..86581ac 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -74,18 +74,6 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
 	}
 }
 
-static const struct of_device_id tegra_dt_clk_match[] = {
-	{ .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
-	{ .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
-	{ .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
-	{ }
-};
-
-void __init tegra_clocks_init(void)
-{
-	of_clk_init(tegra_dt_clk_match);
-}
-
 tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 
 void __init tegra_clocks_apply_init_table(void)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e056562..11278a8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -571,24 +571,6 @@ void tegra_init_from_table(struct tegra_clk_init_table *tbl,
 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 		struct clk *clks[], int clk_max);
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_clock_init(struct device_node *np);
-#else
-static inline void tegra20_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void tegra30_clock_init(struct device_node *np);
-#else
-static inline void tegra30_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void tegra114_clock_init(struct device_node *np);
-#else
-static inline void tegra114_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA114_SOC */
-
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 642789b..3670a4f 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -122,7 +122,6 @@ static inline void tegra_cpu_clock_resume(void)
 
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
-void tegra_clocks_init(void);
 void tegra_clocks_apply_init_table(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
-- 
1.7.4.1



From s.hauer at pengutronix.de  Mon May 27 03:44:00 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 May 2013 09:44:00 +0200
Subject: [PATCH v3 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369389564-13181-2-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
 <1369389564-13181-2-git-send-email-b32955@freescale.com>
Message-ID: <20130527074400.GD32299@pengutronix.de>

On Fri, May 24, 2013 at 05:59:19PM +0800, Huang Shijie wrote:
> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  Documentation/devicetree/bindings/bus/imx-weim.txt |   50 +++++++
>  drivers/bus/Kconfig                                |    9 ++
>  drivers/bus/Makefile                               |    1 +
>  drivers/bus/imx-weim.c                             |  139 ++++++++++++++++++++
>  4 files changed, 199 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
>  create mode 100644 drivers/bus/imx-weim.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
> new file mode 100644
> index 0000000..e7a2950
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
> @@ -0,0 +1,50 @@
> +Device tree bindings for i.MX Wireless External Interface Module (WEIM)
> +
> +The term "wireless" does not imply that the WEIM is literally an interface
> +without wires. It simply means that this module was originally designed for
> +wireless and mobile applications that use low-power technology.
> +
> +The actual devices are instantiated from the child nodes of a WEIM node.
> +
> +Required properties:
> +
> + - compatible:		Should be set to "fsl,imx6q-weim"
> + - reg:			A resource specifier for the register space
> +			(see the example below)
> + - clocks:		the clock, see the example below.
> + - #address-cells:	Must be set to 2 to allow memory address translation
> + - #size-cells:		Must be set to 1 to allow CS address passing
> + - ranges:		Must be set up to reflect the memory layout with four
> +			integer values for each chip-select line in use:
> +
> +			   <cs-number> 0 <physical address of mapping> <size>
> +
> +Timing property for child nodes. It is mandatory, not optional.
> +
> + - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
> +			child node. We can get the CS index from the child
> +			node's "reg" property. This property contains the values
> +			for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
> +			EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
> +
> +Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
> +
> +	weim: weim at 021b8000 {
> +		compatible = "fsl,imx6q-weim";
> +		reg = <0x021b8000 0x4000>;
> +		clocks = <&clks 196>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0x08000000 0x08000000>;
> +
> +		nor at 0,0 {
> +			compatible = "cfi-flash";
> +			reg = <0 0 0x02000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			bank-width = <2>;
> +
> +			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
> +					0x0000C000 0x1404a38e 0x00000000>;
> +		};
> +	};
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index b05ecab..46cd5bb 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -4,6 +4,15 @@
>  
>  menu "Bus devices"
>  
> +config IMX_WEIM
> +	bool "Freescale EIM DRIVER"
> +	depends on ARCH_MXC
> +	help
> +	  Driver for i.MX6 WEIM controller.
> +	  The WEIM(Wireless External Interface Module) works like a bus.
> +	  You can attach many different devices on it, such as NOR, onenand.
> +	  But now, we only support the Parallel NOR.
> +
>  config MVEBU_MBUS
>  	bool
>  	depends on PLAT_ORION
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index 3c7b53c..436bbcc 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -2,6 +2,7 @@
>  # Makefile for the bus drivers.
>  #
>  
> +obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
>  obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
>  obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
>  
> diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
> new file mode 100644
> index 0000000..aef865d
> --- /dev/null
> +++ b/drivers/bus/imx-weim.c
> @@ -0,0 +1,139 @@
> +/*
> + * EIM driver for Freescale's i.MX chips
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +
> +struct imx_weim {
> +	void __iomem *base;
> +	struct clk *clk;
> +};
> +
> +static const struct of_device_id weim_id_table[] = {
> +	{ .compatible = "fsl,imx6q-weim", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, weim_id_table);
> +
> +#define CS_TIMING_LEN 6
> +#define CS_REG_RANGE  0x18
> +
> +/* Parse and set the timing for this device. */
> +static int
> +weim_timing_setup(struct platform_device *pdev, struct device_node *np)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +	u32 value[CS_TIMING_LEN];
> +	u32 cs_idx;
> +	int ret;
> +	int i;
> +
> +	/* get the CS index from this child node's "reg" property. */
> +	ret = of_property_read_u32(np, "reg", &cs_idx);
> +	if (ret)
> +		return ret;
> +
> +	/* The weim has four chip selects. */
> +	if (cs_idx > 3)
> +		return -EINVAL;
> +
> +	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
> +					value, CS_TIMING_LEN);
> +	if (ret)
> +		return ret;
> +
> +	/* set the timing for WEIM */
> +	for (i = 0; i < CS_TIMING_LEN; i++)
> +		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
> +	return 0;
> +}
> +
> +static void weim_parse_dt(struct platform_device *pdev)
> +{
> +	struct device_node *child;
> +
> +	for_each_child_of_node(pdev->dev.of_node, child) {
> +		if (!child->name)
> +			continue;
> +
> +		if (weim_timing_setup(pdev, child)) {
> +			dev_err(&pdev->dev, "%s set timing failed.\n",
> +				child->full_name);
> +			continue;
> +		}

Since you know use of_platform_populate you can't skip erroneous devices
anymore, so you have to bail out.

> +	}
> +
> +	if (of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev) < 0)
> +		dev_err(&pdev->dev, "%s fail to create devices.\n",
> +			pdev->dev.of_node->full_name);
> +}
> +
> +static int weim_probe(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim;
> +	struct resource *res;
> +	int ret = -EINVAL;
> +
> +	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
> +	if (!weim) {
> +		ret = -ENOMEM;
> +		goto weim_err;
> +	}
> +	platform_set_drvdata(pdev, weim);
> +
> +	/* get the resource */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	weim->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(weim->base)) {
> +		ret = PTR_ERR(weim->base);
> +		goto weim_err;
> +	}
> +
> +	/* get the clock */
> +	weim->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(weim->clk))
> +		goto weim_err;
> +
> +	ret = clk_prepare_enable(weim->clk);
> +	if (ret)
> +		goto weim_err;
> +
> +	/* parse the device node */
> +	weim_parse_dt(pdev);
> +
> +	dev_info(&pdev->dev, "WEIM driver registered.\n");
> +	return 0;
> +
> +weim_err:
> +	return ret;
> +}
> +
> +static int weim_remove(struct platform_device *pdev)
> +{
> +	struct imx_weim *weim = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(weim->clk);

I'm running out of ideas how to explain this. Just drop this remove
function. You do not allow building this as module. If you did, then
your first job here would be to unregister your child devices. Then
afterwards you could disable the clock. If you just disable the clock
without unregistering your children then all you do is to make the
child devices nonfuntional.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon May 27 03:44:57 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 May 2013 09:44:57 +0200
Subject: [PATCH v3 6/6] ARM: dts: imx6qdl: enable the WEIM NOR
In-Reply-To: <1369389564-13181-7-git-send-email-b32955@freescale.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
 <1369389564-13181-7-git-send-email-b32955@freescale.com>
Message-ID: <20130527074457.GY20989@pengutronix.de>

In the subject: s/imx6qdl/imx6qdl-sabreauto/

Sascha

On Fri, May 24, 2013 at 05:59:24PM +0800, Huang Shijie wrote:
> Enable the WEIM NOR for imx6q{dl} boards.
> 
> For the pin conflict with SPI NOR, its status is set to "disabled".
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   20 ++++++++++++++++++++
>  1 files changed, 20 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index a4466e6..bb0f185 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -58,3 +58,23 @@
>  	wp-gpios = <&gpio1 13 0>;
>  	status = "okay";
>  };
> +
> +&weim {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs_0>;
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +	ranges = <0 0 0x08000000 0x08000000>;
> +	status = "disabled"; /* pin conflict with SPI NOR */
> +
> +	nor at 0,0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0 0x02000000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		bank-width = <2>;
> +
> +		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1C022000
> +				0x0000C000 0x1404a38e 0x00000000>;
> +	};
> +};
> -- 
> 1.7.1
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon May 27 03:49:37 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 May 2013 09:49:37 +0200
Subject: [PATCH v3 1/2] ARM:dts:mx53qsb: Add support for parallel display
In-Reply-To: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>
References: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>
Message-ID: <20130527074937.GE32299@pengutronix.de>

On Fri, May 24, 2013 at 11:09:30AM -0300, Rogerio Pimentel wrote:
> Add support for CLAA WVGA display for i.MX53 QSB.
> 
> Signed-off-by: Rogerio Pimentel <rogerio.pimentel at freescale.com>

Both:

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

> ---
> Changes since V2:
> Added status = "disabled" by default to avoid conflict with other
> displays like HDMI card.
>  arch/arm/boot/dts/imx53-qsb.dts |   27 +++++++++++++++++++++++++++
>  arch/arm/boot/dts/imx53.dtsi    |   35 +++++++++++++++++++++++++++++++++++
>  2 files changed, 62 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
> index a885d37..8509db3 100644
> --- a/arch/arm/boot/dts/imx53-qsb.dts
> +++ b/arch/arm/boot/dts/imx53-qsb.dts
> @@ -21,6 +21,33 @@
>  		reg = <0x70000000 0x40000000>;
>  	};
>  
> +	display at di0 {
> +		compatible = "fsl,imx-parallel-display";
> +		crtcs = <&ipu 0>;
> +		interface-pix-fmt = "rgb565";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ipu_disp0_1>;
> +		status = "disabled";
> +		display-timings {
> +			claawvga {
> +				native-mode;
> +				clock-frequency = <27000000>;
> +				hactive = <800>;
> +				vactive = <480>;
> +				hback-porch = <40>;
> +				hfront-porch = <60>;
> +				vback-porch = <10>;
> +				vfront-porch = <10>;
> +				hsync-len = <20>;
> +				vsync-len = <10>;
> +				hsync-active = <0>;
> +				vsync-active = <0>;
> +				de-active = <1>;
> +				pixelclk-active = <0>;
> +			};
> +		};
> +	};
> +
>  	gpio-keys {
>  		compatible = "gpio-keys";
>  
> diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> index 2dbdc90..3a565ff 100644
> --- a/arch/arm/boot/dts/imx53.dtsi
> +++ b/arch/arm/boot/dts/imx53.dtsi
> @@ -544,6 +544,41 @@
>  					};
>  				};
>  
> +				ipu_disp0 {
> +					pinctrl_ipu_disp0_1: ipudisp0grp-1 {
> +						fsl,pins = <
> +						MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK	0x5
> +						MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		0x5
> +						MX53_PAD_DI0_PIN2__IPU_DI0_PIN2		0x5
> +						MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 		0x5
> +						MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		0x5
> +						MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		0x5
> +						MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		0x5
> +						MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		0x5
> +						MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		0x5
> +						MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		0x5
> +						MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		0x5
> +						MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		0x5
> +						MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		0x5
> +						MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		0x5
> +						MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		0x5
> +						MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		0x5
> +						MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		0x5
> +						MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		0x5
> +						MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		0x5
> +						MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		0x5
> +						MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		0x5
> +						MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		0x5
> +						MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		0x5
> +						MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		0x5
> +						MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		0x5
> +						MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		0x5
> +						MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		0x5
> +						MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		0x5
> +						>;
> +					};
> +				};
> +
>  				ipu_disp1 {
>  					pinctrl_ipu_disp1_1: ipudisp1grp-1 {
>  						fsl,pins = <
> -- 
> 1.7.10.4
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From monstr at monstr.eu  Mon May 27 03:50:29 2013
From: monstr at monstr.eu (Michal Simek)
Date: Mon, 27 May 2013 09:50:29 +0200
Subject: [GIT PULL] arm-soc: Xilinx zynq clock changes for v3.11
Message-ID: <51A31045.1060406@monstr.eu>

Hi Arnd and Olof,

please pull the following changes to your arm-soc tree.
We haven't got any response from audience or clk maintainer
but we discussed these changes with him in several threads.
The major change is to have easy to going DT clock description
in one node and do not describe the whole clock tree in details
which none uses.

Thanks,
Michal


The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.xilinx.com/linux-xlnx.git tags/zynq-clk-for-3.11

for you to fetch changes up to 83d6e5996a34267e4402e6365c528bddd042ddf3:

  clk: zynq: Remove deprecated clock code (2013-05-27 09:21:49 +0200)

----------------------------------------------------------------
arm: Xilinx Zynq clock changes for v3.11

Change Xilinx Zynq DT clock description which
reflects logical abstraction of Zynq's clock tree.

- Refactor PLL driver
- Use new clock controller driver
- Change timer and uart drivers

----------------------------------------------------------------
Soren Brinkmann (4):
      clk: zynq: Factor out PLL driver
      clk: zynq: Add clock controller driver
      arm: zynq: Migrate platform to clock controller
      clk: zynq: Remove deprecated clock code

 Documentation/devicetree/bindings/clock/zynq-7000.txt | 123 ++++++++++++++-------
 arch/arm/boot/dts/zynq-7000.dtsi                      |  71 ++++--------
 arch/arm/boot/dts/zynq-zc702.dts                      |   4 -
 arch/arm/mach-zynq/slcr.c                             |   2 +-
 drivers/clk/Makefile                                  |   2 +-
 drivers/clk/clk-zynq.c                                | 378 --------------------------------------------------------------
 drivers/clk/zynq/Makefile                             |   3 +
 drivers/clk/zynq/clkc.c                               | 533 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/zynq/pll.c                                | 235 +++++++++++++++++++++++++++++++++++++++
 drivers/clocksource/cadence_ttc_timer.c               |  23 +++-
 drivers/tty/serial/xilinx_uartps.c                    |  85 +++++++++++---
 include/linux/clk/zynq.h                              |   8 +-
 12 files changed, 972 insertions(+), 495 deletions(-)
 delete mode 100644 drivers/clk/clk-zynq.c
 create mode 100644 drivers/clk/zynq/Makefile
 create mode 100644 drivers/clk/zynq/clkc.c
 create mode 100644 drivers/clk/zynq/pll.c

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From pgaikwad at nvidia.com  Mon May 27 03:54:39 2013
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 27 May 2013 13:24:39 +0530
Subject: [PATCH] clk: tegra: fix clk_out parents list
Message-ID: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>

Number of parents for clk_out_2 and clk_out_3 was incorrectly set
to clk_out1_parents. Even though it did not break anything since the
size was same better to fix.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |    4 ++--
 drivers/clk/tegra/clk-tegra30.c  |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index e0ee077..6d438bb 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1602,7 +1602,7 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_2 */
 	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out2_parents), 0,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_2_mux] = clk;
@@ -1614,7 +1614,7 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
 
 	/* clk_out_3 */
 	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out3_parents), 0,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
 			       &clk_out_lock);
 	clks[clk_out_3_mux] = clk;
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 985ad69..b62e140 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1223,7 +1223,7 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_2 */
 	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out2_parents), 0,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
 			       &clk_out_lock);
 	clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1234,7 +1234,7 @@ static void __init tegra30_pmc_clk_init(void)
 
 	/* clk_out_3 */
 	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-			       ARRAY_SIZE(clk_out1_parents), 0,
+			       ARRAY_SIZE(clk_out3_parents), 0,
 			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
 			       &clk_out_lock);
 	clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
-- 
1.7.4.1



From ludovic.desroches at atmel.com  Mon May 27 04:09:09 2013
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Mon, 27 May 2013 10:09:09 +0200
Subject: [PATCH v2] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <20130525200557.GO24476@game.jcrosoft.org>
References: <1369467542-25519-1-git-send-email-alexandre.belloni@free-electrons.com>
 <20130525200557.GO24476@game.jcrosoft.org>
Message-ID: <20130527080909.GB2919@ludovic.desroches@atmel.com>

On Sat, May 25, 2013 at 10:05:57PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 09:39 Sat 25 May     , Alexandre Belloni wrote:
> > Fixes:
> > arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> > :(.text+0x1174): undefined reference to `mdiobus_write'
> > :(.text+0x1188): undefined reference to `mdiobus_write'
> > :(.text+0x119c): undefined reference to `mdiobus_write'
> > :(.text+0x11b0): undefined reference to `mdiobus_write'
> > arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> > :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
> > 
> > when CONFIG_PHYLIB is not selected.

Signed-off-by missing.

Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>

> > ---
> > Changes in v2:
> > 	use IS_BUILTIN
> > 	use CONFIG_PHYLIB and not CONFIG_PHY
> > 
> 
> I do not like this, I prefer we just drop the fixup by adding the dt support
> to the micrel phy as done for broadcom
> 

Yes it will be a better solution but we don't have it. Even if we add dt
support for micrel phy it won't go into 3.10 so it has to be fixed before the
release.

> if !PHYLIB just add an inline declaration of 
> phy_register_fixup_for_uid
> 
> so gcc will drop ksz9021rn_phy_fixup automatically
> 
> Best Regards,
> J.
> > 
> >  arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
> >  1 file changed, 12 insertions(+), 10 deletions(-)
> > 
> > diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> > index 705305e..e9ce541 100644
> > --- a/arch/arm/mach-at91/board-dt-sama5.c
> > +++ b/arch/arm/mach-at91/board-dt-sama5.c
> > @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
> >  #define GMII_ERCR	11
> >  #define GMII_ERDWR	12
> >  
> > -	/* Set delay values */
> > -	value = GMII_RCCPSR | 0x8000;
> > -	phy_write(phy, GMII_ERCR, value);
> > -	value = 0xF2F4;
> > -	phy_write(phy, GMII_ERDWR, value);
> > -	value = GMII_RRDPSR | 0x8000;
> > -	phy_write(phy, GMII_ERCR, value);
> > -	value = 0x2222;
> > -	phy_write(phy, GMII_ERDWR, value);
> > +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
> > +		/* Set delay values */
> > +		value = GMII_RCCPSR | 0x8000;
> > +		phy_write(phy, GMII_ERCR, value);
> > +		value = 0xF2F4;
> > +		phy_write(phy, GMII_ERDWR, value);
> > +		value = GMII_RRDPSR | 0x8000;
> > +		phy_write(phy, GMII_ERCR, value);
> > +		value = 0x2222;
> > +		phy_write(phy, GMII_ERDWR, value);
> > +	}
> >  
> >  	return 0;
> >  }
> >  
> >  static void __init sama5_dt_device_init(void)
> >  {
> > -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
> > +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
> >  		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
> >  			ksz9021rn_phy_fixup);
> >  
> > -- 
> > 1.8.1.2
> > 
> --
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From list-09_linux_arm at tqsc.de  Mon May 27 04:19:08 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Mon, 27 May 2013 10:19:08 +0200
Subject: [PATCH RESEND v2 0/3] staging: fix parallel display regressions
Message-ID: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

Support for VGA via TVE on i.MX53 causes regressions, which prevents
parallel display from working. This series brings the parallel display
functionality back.

The updated series was tested with 3.10-rc2 on a TQMa53 module with
modified device tree.

Markus Niebel (3):
  staging: drm/imx: set correct sync pins for display
  staging: drm/imx: fix spelling error for vsync flag config
  staging: drm/imx: revert vsync_cnt for di->id 1

 drivers/staging/imx-drm/imx-drm-core.c  |    2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-di.c |   13 +++++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)

-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Mon May 27 04:19:10 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Mon, 27 May 2013 10:19:10 +0200
Subject: [PATCH RESEND v2 2/3] staging: drm/imx: fix spelling error for vsync
 flag config
In-Reply-To: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>
References: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>
Message-ID: <1369642751-15555-3-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

Have to check for vsync_pin instead of hsync_pin to set Vsync_pol.

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
Acked-by: Philipp Zabel <p.zabel at pengutronix.de>
Tested-by: Philipp Zabel <p.zabel at pengutronix.de>
Tested-by: Rogerio Pimentel <rpimentel.silva at gmail.com>
---
Resend:
  - add Tested-by for Philip and Rogerio
V2:
  - no changes in patch
  - add Acked-by from v1 of patch

 drivers/staging/imx-drm/ipu-v3/ipu-di.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index 19d777e..e7b9c98 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
@@ -614,11 +614,11 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 				di_gen |= DI_GEN_POLARITY_7;
 		}
 		if (sig->Vsync_pol) {
-			if (sig->hsync_pin == 3)
+			if (sig->vsync_pin == 3)
 				di_gen |= DI_GEN_POLARITY_3;
-			else if (sig->hsync_pin == 6)
+			else if (sig->vsync_pin == 6)
 				di_gen |= DI_GEN_POLARITY_6;
-			else if (sig->hsync_pin == 8)
+			else if (sig->vsync_pin == 8)
 				di_gen |= DI_GEN_POLARITY_8;
 		}
 	}
-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Mon May 27 04:19:09 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Mon, 27 May 2013 10:19:09 +0200
Subject: [PATCH RESEND v2 1/3] staging: drm/imx: set correct sync pins for
 display
In-Reply-To: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>
References: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>
Message-ID: <1369642751-15555-2-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

Have to call imx_drm_crtc_panel_format_pins in imx_drm_crtc_panel_format
with the correct pins instead of (0, 0) This enables configuration of
correct waveforms for vsync / hsync for parallel display, LDB (i.MX53 and
i.MX6) as well as HDMI and MIPI (i.MX6)

TODO: configure pins via device tree

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
---
V2:
  changed patch as suggested by Philipp Zabel. This will
  fix regressions for other interfaces, too
V1:
  Tested-by Philipp Zabel an Rogerio Pimentel

 drivers/staging/imx-drm/imx-drm-core.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 6455305..8c433fc 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -144,7 +144,7 @@ int imx_drm_crtc_panel_format(struct drm_crtc *crtc, u32 encoder_type,
 		u32 interface_pix_fmt)
 {
 	return imx_drm_crtc_panel_format_pins(crtc, encoder_type,
-					      interface_pix_fmt, 0, 0);
+					      interface_pix_fmt, 2, 3);
 }
 EXPORT_SYMBOL_GPL(imx_drm_crtc_panel_format);
 
-- 
1.7.9.5



From list-09_linux_arm at tqsc.de  Mon May 27 04:19:11 2013
From: list-09_linux_arm at tqsc.de (Markus Niebel)
Date: Mon, 27 May 2013 10:19:11 +0200
Subject: [PATCH RESEND v2 3/3] staging: drm/imx: revert vsync_cnt for di->id 1
In-Reply-To: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>
References: <1369642751-15555-1-git-send-email-list-09_linux_arm@tqsc.de>
Message-ID: <1369642751-15555-4-git-send-email-list-09_linux_arm@tqsc.de>

From: Markus Niebel <Markus.Niebel at tqs.de>

partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"

parallel display support / DVI needs the original setting to work

Signed-off-by: Markus Niebel <Markus.Niebel at tqs.de>
Acked-by: Philipp Zabel <p.zabel at pengutronix.de>
Tested-by: Philipp Zabel <p.zabel at pengutronix.de>
Tested-by: Rogerio Pimentel <rpimentel.silva at gmail.com>
---
Resend:
  - add Tested-by for Philip and Rogerio
V2:
  - no changes in patch
  - add Acked-by from v1 of patch

 drivers/staging/imx-drm/ipu-v3/ipu-di.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index e7b9c98..0b6806e 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
@@ -603,7 +603,12 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 		vsync_cnt = 3;
 		if (di->id == 1)
-			vsync_cnt = 6;
+			/*
+			 * TODO: change only for TVEv2, parallel display
+			 * uses pin 2 / 3
+			 */
+			if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
+				vsync_cnt = 6;
 
 		if (sig->Hsync_pol) {
 			if (sig->hsync_pin == 2)
-- 
1.7.9.5



From shawn.guo at linaro.org  Mon May 27 04:26:01 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 16:26:01 +0800
Subject: [PATCH v3 1/2] ARM:dts:mx53qsb: Add support for parallel display
In-Reply-To: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>
References: <1369404571-21356-1-git-send-email-rogerio.pimentel@freescale.com>
Message-ID: <20130527082559.GA19397@S2101-09.ap.freescale.net>

On Fri, May 24, 2013 at 11:09:30AM -0300, Rogerio Pimentel wrote:
> Add support for CLAA WVGA display for i.MX53 QSB.
> 
> Signed-off-by: Rogerio Pimentel <rogerio.pimentel at freescale.com>

Please put a space after ":" in subject, something like the below. 

ARM: dts: mx53qsb: ...

I fixed it this time.  Both applied, thanks.

Shawn



From shawn.guo at linaro.org  Mon May 27 04:30:35 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 16:30:35 +0800
Subject: [PATCH] ARM: mx6: Use the same sdma firmware name for all mx6
 variants
In-Reply-To: <1369504048-19805-1-git-send-email-festevam@gmail.com>
References: <1369504048-19805-1-git-send-email-festevam@gmail.com>
Message-ID: <20130527083034.GB19397@S2101-09.ap.freescale.net>

On Sat, May 25, 2013 at 02:47:28PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> All the mx6 variants (quad, dual, solo and solo-lite) use the same sdma 
> firmware, so drop the the suffix from the file name.

But you do not know if the next imx6 variant uses the same sdma
firmware.

The suffix should be taken as a compatible/version mark, and it should
be fine to use sdma-imx6q.bin on any other SoCs that use the same
firmware.

Shawn

> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
>  arch/arm/boot/dts/imx6sl.dtsi  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 42e461c..b6730cc 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -582,7 +582,7 @@
>  				interrupts = <0 2 0x04>;
>  				clocks = <&clks 155>, <&clks 155>;
>  				clock-names = "ipg", "ahb";
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
> +				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6.bin";
>  			};
>  		};
>  
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index c5e5da0..9596000 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -594,7 +594,7 @@
>  				clocks = <&clks IMX6SL_CLK_SDMA>,
>  					 <&clks IMX6SL_CLK_SDMA>;
>  				clock-names = "ipg", "ahb";
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
> +				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6.bin";
>  			};
>  
>  			pxp: pxp at 020f0000 {
> -- 
> 1.8.1.2
> 



From geert at linux-m68k.org  Mon May 27 04:36:16 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Mon, 27 May 2013 10:36:16 +0200
Subject: [PATCH] console/dummy: Move screen size selection from CPP to Kconfig
Message-ID: <1369643776-20516-1-git-send-email-geert@linux-m68k.org>

PA-RISC already handled the dummy console screen size selection in Kconfig,
so generalize this to other platforms.

ARM keeps on using screen_info, which is filled in by platform-specific
code, or from ATAGS.

Signed-off-by: Geert Uytterhoeven <geert at linux-m68k.org>
---
 drivers/video/console/Kconfig    |   16 ++++++++++------
 drivers/video/console/dummycon.c |    5 +----
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 8af6ad3..7bfe7e1 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -76,18 +76,22 @@ config DUMMY_CONSOLE
 
 config DUMMY_CONSOLE_COLUMNS
         int "Initial number of console screen columns"
-        depends on PARISC && DUMMY_CONSOLE
-        default "160"
+        depends on DUMMY_CONSOLE && !ARM
+        default 160 if PARISC
+        default 80
         help
-          The default value is 160, which should fit a 1280x1024 monitor.
+          On PA-RISC, the default value is 160, which should fit a 1280x1024
+          monitor.
           Select 80 if you use a 640x480 resolution by default.
 
 config DUMMY_CONSOLE_ROWS
         int "Initial number of console screen rows"
-        depends on PARISC && DUMMY_CONSOLE
-        default "64"
+        depends on DUMMY_CONSOLE && !ARM
+        default 64 if PARISC
+        default 25
         help
-          The default value is 64, which should fit a 1280x1024 monitor.
+          On PA-RISC, the default value is 64, which should fit a 1280x1024
+          monitor.
           Select 25 if you use a 640x480 resolution by default.
 
 config FRAMEBUFFER_CONSOLE
diff --git a/drivers/video/console/dummycon.c b/drivers/video/console/dummycon.c
index b63860f..6b1a5d1 100644
--- a/drivers/video/console/dummycon.c
+++ b/drivers/video/console/dummycon.c
@@ -20,13 +20,10 @@
 #if defined(__arm__)
 #define DUMMY_COLUMNS	screen_info.orig_video_cols
 #define DUMMY_ROWS	screen_info.orig_video_lines
-#elif defined(__hppa__)
+#else
 /* set by Kconfig. Use 80x25 for 640x480 and 160x64 for 1280x1024 */
 #define DUMMY_COLUMNS	CONFIG_DUMMY_CONSOLE_COLUMNS
 #define DUMMY_ROWS	CONFIG_DUMMY_CONSOLE_ROWS
-#else
-#define DUMMY_COLUMNS	80
-#define DUMMY_ROWS	25
 #endif
 
 static const char *dummycon_startup(void)
-- 
1.7.0.4



From gabriel.fernandez at st.com  Mon May 27 04:50:59 2013
From: gabriel.fernandez at st.com (Gabriel FERNANDEZ)
Date: Mon, 27 May 2013 10:50:59 +0200
Subject: [PATCH] ARM: nomadik: move the pin configuration to DT
In-Reply-To: <1369430009-27214-1-git-send-email-linus.walleij@linaro.org>
References: <1369430009-27214-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <89DE3898F574CE41BE193A4422852043021055325A12@SAFEX1MAIL2.st.com>



2013/5/27 Gabriel FERNANDEZ <gabriel.fernandez at st.com>:
>
>
> -----Original Message-----
> From: Linus Walleij [mailto:linus.walleij at linaro.org]
> Sent: Friday, May 24, 2013 11:13 PM
> To: linux-arm-kernel at lists.infradead.org
> Cc: Linus Walleij; Gabriel FERNANDEZ; Patrice CHOTARD
> Subject: [PATCH] ARM: nomadik: move the pin configuration to DT
>
> This moves the pin configuration for the Nomadik over to the device tree using Gabriel's bindings. Remove the auxdata nailing down the name of the pin controller as this is no longer necessary.
>
> Cc: Gabriel Fernandez <gabriel.fernandez at st.com>
> Cc: Patrice Chotard <patrice.chotard at st.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/ste-nomadik-s8815.dts    | 41 +++++++++++++++
>  arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 82 ++++++++++++++++++++++++++++++
>  arch/arm/mach-nomadik/cpu-8815.c           | 51 -------------------
>  3 files changed, 123 insertions(+), 51 deletions(-)
>
> diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
> index 666945a..638ec8d 100644
> --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
> +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
> @@ -14,6 +14,43 @@
>                 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
>         };
>
> +       pinctrl {
> +               /* Hog CD pins */
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&cd_default_mode>;
> +
> +               mmcsd-cd {
> +                       cd_default_mode: cd_default {
> +                               cd_default_cfg1 {
> +                                       /* CD input GPIO */
> +                                       ste,pins = "GPIO111_H21";
"GPIO111" instead of "GPIO111_H21"

> +                                       ste,input = <0>;
> +                               };
new line

> +                               cd_default_cfg2 {
> +                                       /* CD GPIO biasing */
> +                                       ste,pins = "GPIO112_J21";
> +                                       ste,output = <0>;
> +                               };
> +                       };
> +               };
> +               user-led {
> +                       user_led_default_mode: user_led_default {
> +                               user_led_default_cfg {
> +                                       ste,pins = "GPIO2_C5";
ditto for all ste,pins

> +                                       ste,output = <1>;
> +                               };
> +                       };
> +               };
> +               user-button {
> +                       user_button_default_mode: user_button_default {
> +                               user_button_default_cfg {
> +                                       ste,pins = "GPIO3_A4";
> +                                       ste,input = <0>;
> +                               };
> +                       };
> +               };
> +       };
> +
>         /* Custom board node with GPIO pins to active etc */
>         usb-s8815 {
>                 /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ @@ -36,6 +73,8 @@
>                         gpios = <&gpio0 2 0x1>;
>                         default-state = "off";
>                         linux,default-trigger = "heartbeat";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&user_led_default_mode>;
>                 };
>         };
>
> @@ -47,6 +86,8 @@
>                         gpios = <&gpio0 3 0x1>;
>                         linux,code = <1>; /* KEY_ESC */
>                         gpio-key,wakeup;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&user_button_default_mode>;
>                 };
>         };
>  };
> diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
> index 51a33e0..615da87 100644
> --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
> +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
> @@ -94,6 +94,75 @@
>
>         pinctrl {
>                 compatible = "stericsson,nmk-pinctrl-stn8815";
> +               /* Pin configurations */
> +               uart0 {
> +                       uart0_default_mux: uart0_mux {
> +                               u0_default_mux {
> +                                       ste,function = "u0";
> +                                       ste,pins = "u0_a_1";
> +                               };
> +                       };
> +               };
new line

> +               uart1 {
> +                       uart1_default_mux: uart1_mux {
> +                               u1_default_mux {
> +                                       ste,function = "u1";
> +                                       ste,pins = "u1_a_1";
> +                               };
> +                       };
> +               };
new line

> +               mmcsd {
> +                       mmcsd_default_mux: mmcsd_mux {
> +                               mmcsd_default_mux {
> +                                       ste,function = "mmcsd";
> +                                       ste,pins = "mmcsd_a_1";
> +                               };
> +                       };
newline

> +                       mmcsd_default_mode: mmcsd_default {
> +                               mmcsd_default_cfg1 {
> +                                       /* MCCLK */
> +                                       ste,pins = "GPIO8_B10";
> +                                       ste,output = <0>;
> +                               };
newline

> +                               mmcsd_default_cfg2 {
> +                                       /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
> +                                       ste,pins = "GPIO10_C11", "GPIO15_A12",
> +                                       "GPIO16_C13";
> +                                       ste,output = <1>;
> +                               };
newline

> +                               mmcsd_default_cfg3 {
> +                                       /* MCCMD, MCDAT3-0, MCMSFBCLK */
> +                                       ste,pins = "GPIO9_A10", "GPIO11_B11",
> +                                       "GPIO12_A11", "GPIO13_C12",
> +                                       "GPIO14_B12", "GPIO24_C15";
> +                                       ste,input = <1>;
> +                               };
> +                       };
> +               };
newline

> +               i2c0 {
> +                       i2c0_default_mode: i2c0_default {
> +                               i2c0_default_cfg {
> +                                       ste,pins = "GPIO62_D3", "GPIO63_D2";
> +                                       ste,input = <1>;
> +                               };
> +                       };
> +               };

newline

> +               i2c1 {
> +                       i2c1_default_mode: i2c1_default {
> +                               i2c1_default_cfg {
> +                                       ste,pins = "GPIO53_L4", "GPIO54_L3";
> +                                       ste,input = <1>;
> +                               };
> +                       };
> +               };
newline

> +               i2c2 {
> +                       i2c2_default_mode: i2c2_default {
> +                               i2c2_default_cfg {
> +                                       ste,pins = "GPIO73_C21", "GPIO74_C20";
> +                                       ste,input = <1>;
> +                               };
> +                       };
> +               };
>         };
>
>         src: src at 101e0000 {
> @@ -191,6 +260,8 @@
>                         <&gpio1 30 0>; /* scl */
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&i2c0_default_mode>;
>
>                 stw4811 at 2d {
>                            compatible = "st,stw4811";
> @@ -205,6 +276,8 @@
>                         <&gpio1 21 0>; /* scl */
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&i2c1_default_mode>;
>
>                 camera at 2d {
>                            compatible = "st,camera";
> @@ -227,6 +300,9 @@
>                         <&gpio2 9 0>; /* scl */
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&i2c2_default_mode>;
> +
>                 stw4811 at 2d {
>                            compatible = "st,stw4811-usb";
>                            reg = <0x2d>;
> @@ -260,6 +336,8 @@
>                         interrupts = <12>;
>                         clocks = <&clk48>, <&pclk>;
>                         clock-names = "uartclk", "apb_pclk";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&uart0_default_mux>;
>                 };
>
>                 uart1: uart at 101fb000 {
> @@ -269,6 +347,8 @@
>                         interrupts = <17>;
>                         clocks = <&clk48>, <&pclk>;
>                         clock-names = "uartclk", "apb_pclk";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&uart1_default_mux>;
>                 };
>
>                 uart2: uart at 101f2000 {
> @@ -310,6 +390,8 @@
>                         mmc-cap-sd-highspeed;
>                         cd-gpios = <&gpio3 15 0x1>;
>                         cd-inverted;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
>                 };
>         };
>  };
> diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
> index 8351617..89e2c03 100644
> --- a/arch/arm/mach-nomadik/cpu-8815.c
> +++ b/arch/arm/mach-nomadik/cpu-8815.c
> @@ -27,8 +27,6 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/irqchip.h>
>  #include <linux/platform_data/clk-nomadik.h>
> -#include <linux/platform_data/pinctrl-nomadik.h>
> -#include <linux/pinctrl/machine.h>
>  #include <linux/clocksource.h>
>  #include <linux/of_irq.h>
>  #include <linux/of_gpio.h>
> @@ -91,52 +89,6 @@
>  #define NOMADIK_L2CC_BASE      0x10210000      /* L2 Cache controller */
>  #define NOMADIK_UART1_VBASE    0xF01FB000
>
> -static unsigned long out_low[] = { PIN_OUTPUT_LOW }; -static unsigned long out_high[] = { PIN_OUTPUT_HIGH }; -static unsigned long in_nopull[] = { PIN_INPUT_NOPULL }; -static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
> -
> -static struct pinctrl_map __initdata nhk8815_pinmap[] = {
> -       PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
> -       PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
> -       /* User LED on S8815 */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO2_C5", out_high),
> -       /* User button on S8815 */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO3_A4", in_nopull),
> -       /* Hog in MMC/SD card mux */
> -       PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
> -       /* MCCLK */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
> -       /* MCCMD */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
> -       /* MCCMDDIR */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
> -       /* MCDAT3-0 */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
> -       /* MCDAT0DIR */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
> -       /* MCDAT31DIR */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
> -       /* MCMSFBCLK */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
> -       /* CD input GPIO */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
> -       /* CD bias drive */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
> -       /* I2C0 */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup),
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup),
> -       /* I2C1 */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup),
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup),
> -       /* I2C2 */
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup),
> -       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup),
> -};
> -
>  /* This is needed for LL-debug/earlyprintk/debug-macro.S */  static struct map_desc cpu8815_io_desc[] __initdata = {
>         {
> @@ -284,8 +236,6 @@ device_initcall(cpu8815_mmcsd_init);
>
>  /* These are mostly to get the right device names for the clock lookups */  static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
> -       OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
> -               "pinctrl-stn8815", NULL),
>         OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
>                 NULL, &cpu8815_nand_data),
>         OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE, @@ -299,7 +249,6 @@ static void __init cpu8815_init_of(void)
>         /* At full speed latency must be >=2, so 0x249 in low bits */
>         l2x0_of_init(0x00730249, 0xfe000fff);
>  #endif
> -       pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
>         of_platform_populate(NULL, of_default_bus_match_table,
>                         cpu8815_auxdata_lookup, NULL);
>  }
> --
> 1.8.1.4
>



From jonas at microbit.se  Mon May 27 04:52:45 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Mon, 27 May 2013 10:52:45 +0200
Subject: [PATCH] ARM: dts: imx53: add ecspi2 pinctrl
Message-ID: <1369644765-17189-1-git-send-email-jonas@microbit.se>

Add ecspi2 pinctrl.

Signed-off-by: Jonas Andersson <jonas at microbit.se>
---
 arch/arm/boot/dts/imx53.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 024616c..dd59ace 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -342,6 +342,16 @@
 					};
 				};
 
+				ecspi2 {
+					pinctrl_ecspi2_1: ecspi2grp-1 {
+						fsl,pins = <
+							MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
+							MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
+							MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
+						>;
+					};
+				};
+
 				esdhc1 {
 					pinctrl_esdhc1_1: esdhc1grp-1 {
 						fsl,pins = <
-- 
1.8.1.4



From jonas at microbit.se  Mon May 27 04:52:21 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Mon, 27 May 2013 10:52:21 +0200
Subject: [PATCH] ARM: dts: imx53: add cspi pinctrl
Message-ID: <1369644741-17153-1-git-send-email-jonas@microbit.se>

Add a group to the cspi pinctrl.

Signed-off-by: Jonas Andersson <jonas at microbit.se>
---
 arch/arm/boot/dts/imx53.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index eb83aa0..024616c 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -322,6 +322,14 @@
 							MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
 						>;
 					};
+
+					pinctrl_cspi_2: cspigrp-2 {
+						fsl,pins = <
+							MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
+							MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
+							MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
+						>;
+					};
 				};
 
 				ecspi1 {
-- 
1.8.1.4



From jonas at microbit.se  Mon May 27 04:52:54 2013
From: jonas at microbit.se (Jonas Andersson)
Date: Mon, 27 May 2013 10:52:54 +0200
Subject: [PATCH] ARM: dts: imx53: add fec pinctrl
Message-ID: <1369644774-17225-1-git-send-email-jonas@microbit.se>

Add a group to the fec pinctrl, for use with MII interface.

Signed-off-by: Jonas Andersson <jonas at microbit.se>
---
 arch/arm/boot/dts/imx53.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index dd59ace..d7d9270 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -284,6 +284,29 @@
 							MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 						>;
 					};
+
+					pinctrl_fec_2: fecgrp-2 {
+						fsl,pins = <
+							MX53_PAD_FEC_MDC__FEC_MDC	 0x80000000
+							MX53_PAD_FEC_MDIO__FEC_MDIO	 0x80000000
+							MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+							MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
+							MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
+							MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
+							MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
+							MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
+							MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
+							MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
+							MX53_PAD_KEY_ROW1__FEC_COL	 0x80000000
+							MX53_PAD_KEY_COL3__FEC_CRS	 0x80000000
+							MX53_PAD_KEY_COL2__FEC_RDATA_2	 0x80000000
+							MX53_PAD_KEY_COL0__FEC_RDATA_3	 0x80000000
+							MX53_PAD_KEY_COL1__FEC_RX_CLK	 0x80000000
+							MX53_PAD_KEY_ROW2__FEC_TDATA_2	 0x80000000
+							MX53_PAD_GPIO_19__FEC_TDATA_3	 0x80000000
+							MX53_PAD_KEY_ROW0__FEC_TX_ER	 0x80000000
+						>;
+					};
 				};
 
 				csi {
-- 
1.8.1.4



From horms+renesas at verge.net.au  Mon May 27 04:59:45 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:45 +0900
Subject: [PATCH 04/12] ARM: shmobile: r8a7740: Add DT name to clock list for
 CMT10
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-5-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

This adds temporarily the alternative device name to the clock list
that is used when booting via Device Tree setup.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 5bd8da0..8fc396a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -582,6 +582,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e6cc0000.sci",		&mstp_clks[MSTP230]),
 
 	CLKDEV_DEV_ID("sh_cmt.10",		&mstp_clks[MSTP329]),
+	CLKDEV_DEV_ID("e6138010.timer",		&mstp_clks[MSTP329]),
 	CLKDEV_DEV_ID("sh_fsi2",		&mstp_clks[MSTP328]),
 	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
 	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:44 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:44 +0900
Subject: [PATCH 03/12] ARM: shmobile: r8a7740: Add interim sh-eth device name
 to clocks list
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-4-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

When we use the ethernet device via DT setup, we need to add it
to a lookup list until this is properly handled later in a DT-only
fashion.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa..5bd8da0 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -592,6 +592,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_mmcif",		&mstp_clks[MSTP312]),
 	CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
 	CLKDEV_DEV_ID("sh-eth",			&mstp_clks[MSTP309]),
+	CLKDEV_DEV_ID("e9a00000.sh-eth",	&mstp_clks[MSTP309]),
 
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2",	&mstp_clks[MSTP415]),
 	CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:42 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:42 +0900
Subject: [PATCH 01/12] ARM: shmobile: remove ";
 " from SH_FIXED_RATIO_CLK*() macro
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-2-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Acked-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/clock.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac612..8902044 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,11 +24,11 @@ struct clk name = {			\
 }
 
 #define SH_FIXED_RATIO_CLK(name, p, r)		\
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)	\
 	SH_CLK_RATIO(name, m, d);		\
-	SH_FIXED_RATIO_CLK(name, p, name);
+	SH_FIXED_RATIO_CLK(name, p, name)
 
 #define SH_CLK_SET_RATIO(p, m, d)	\
 {			\
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:43 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:43 +0900
Subject: [PATCH 02/12] ARM: shmobile: r8a7740 pinmux platform device cleanup
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-3-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Use DEFINE_RES_MEM() and platform_device_register_simple()
to save a couple of lines of code.

Signed-off-by: Magnus Damm <damm at opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7740.c |   24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab..3a6b6fe 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
-	[0] = {
-		.start	= 0xe6050000,
-		.end	= 0xe6057fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0xe605800c,
-		.end	= 0xe605802b,
-		.flags	= IORESOURCE_MEM,
-	}
-};
-
-static struct platform_device r8a7740_pfc_device = {
-	.name		= "pfc-r8a7740",
-	.id		= -1,
-	.resource	= r8a7740_pfc_resources,
-	.num_resources	= ARRAY_SIZE(r8a7740_pfc_resources),
+static const struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xe6050000, 0x8000),
+	DEFINE_RES_MEM(0xe605800c, 0x0020),
 };
 
 void __init r8a7740_pinmux_init(void)
 {
-	platform_device_register(&r8a7740_pfc_device);
+	platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+					ARRAY_SIZE(pfc_resources));
 }
 
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:41 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:41 +0900
Subject: [GIT PULL] Renesas ARM based r8a7740 SoC updates for v3.11
Message-ID: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a7740-for-v3.11

for you to fetch changes up to 0a9e1c1eef2b050a16685952ce20575348b94d5c:

  ARM: shmobile: clock-r8a7740: add TPU PWM support (2013-05-27 17:45:27 +0900)

----------------------------------------------------------------
Renesas ARM based r8a7740 SoC updates for v3.11

* Clean-ups from Kuninori Morimoto, Magnus Damm and Laurent Pinchart.
* Extended clock coverage by Bastian Hecht.
* Support for initialising GIC from OF by Bastian Hecht.
* Support for reference DT initialisation by Bastian Hecht.
  This is used in conjunction with other changes initialise
  the Armadillo 800 eva board in DT as much as possible.
* Suspend to RAM and CPUIdle support by Bastian Hecht
* Build fix for fallout by Arnd Bergmann from suspend to RAM change.

----------------------------------------------------------------
Arnd Bergmann (1):
      ARM: shmobile: fix sleep-r8a7740.S miscompiles

Bastian Hecht (7):
      ARM: shmobile: r8a7740: Add interim sh-eth device name to clocks list
      ARM: shmobile: r8a7740: Add DT name to clock list for CMT10
      ARM: shmobile: r8a7740: Add I2C DT clock names
      ARM: shmobile: r8a7740: Add OF support to initialze the GIC
      ARM: shmobile: r8a7740: Prepare for reference DT setup
      ARM: shmobile: r8a7740: Add Suspend-To-RAM A3SM
      ARM: shmobile: r8a7740: Add CPUIdle

Kuninori Morimoto (1):
      ARM: shmobile: remove ";" from SH_FIXED_RATIO_CLK*() macro

Laurent Pinchart (2):
      ARM: shmobile: r8a7740: Make private clock arrays static
      ARM: shmobile: clock-r8a7740: add TPU PWM support

Magnus Damm (1):
      ARM: shmobile: r8a7740 pinmux platform device cleanup

 arch/arm/boot/dts/r8a7740.dtsi                |  117 ++++++++++++++++++
 arch/arm/mach-shmobile/Makefile               |    2 +-
 arch/arm/mach-shmobile/clock-r8a7740.c        |   12 +-
 arch/arm/mach-shmobile/cpuidle-r8a7740.c      |   62 ++++++++++
 arch/arm/mach-shmobile/include/mach/clock.h   |    4 +-
 arch/arm/mach-shmobile/include/mach/r8a7740.h |    7 ++
 arch/arm/mach-shmobile/intc-r8a7740.c         |   24 +++-
 arch/arm/mach-shmobile/pm-r8a7740.c           |  165 ++++++++++++++++++++++++-
 arch/arm/mach-shmobile/setup-r8a7740.c        |   78 +++++-------
 arch/arm/mach-shmobile/sleep-r8a7740.S        |   57 +++++++++
 10 files changed, 469 insertions(+), 59 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/cpuidle-r8a7740.c
 create mode 100644 arch/arm/mach-shmobile/sleep-r8a7740.S


From horms+renesas at verge.net.au  Mon May 27 05:00:05 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:05 +0900
Subject: [PATCH 1/2] ARM: shmobile: r8a7779: Add PCIe clocks
In-Reply-To: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645206-3682-2-git-send-email-horms+renesas@verge.net.au>

From: Phil Edworthy <Phil.Edworthy at renesas.com>

Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4..9daeb8c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-	MSTP115, MSTP114,
+	MSTP116, MSTP115, MSTP114,
 	MSTP103, MSTP101, MSTP100,
 	MSTP030,
 	MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+	[MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
 	[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
 	[MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
 	[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("peripheral_clk",	&clkp_clk),
 
 	/* MSTP32 clocks */
+	CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
 	CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
 	CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
 	CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:06 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:06 +0900
Subject: [PATCH 2/2] ARM: shmobile: r8A7779: fix Ether device name
In-Reply-To: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645206-3682-3-git-send-email-horms+renesas@verge.net.au>

From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

While recasting the commit "ARM: shmobile: R8A7779: add Ether support", I made a
typo in the platform device's name: used underscore instead of hyphen.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7779.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b3948..c14a69b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -443,7 +443,7 @@ void __init r8a7779_add_standard_devices(void)
 
 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
 {
-	platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+	platform_device_register_resndata(&platform_bus, "sh-eth", -1,
 					  ether_resources,
 					  ARRAY_SIZE(ether_resources),
 					  pdata, sizeof(*pdata));
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:47 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:47 +0900
Subject: [PATCH 06/12] ARM: shmobile: r8a7740: Add I2C DT clock names
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-7-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

Add clock association for i2c0 and i2c1 for the new DT names.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index a2a612f..b12c476 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -551,6 +551,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_tmu.4",		&mstp_clks[MSTP111]),
 	CLKDEV_DEV_ID("sh_tmu.5",		&mstp_clks[MSTP111]),
 	CLKDEV_DEV_ID("i2c-sh_mobile.0",	&mstp_clks[MSTP116]),
+	CLKDEV_DEV_ID("fff20000.i2c",		&mstp_clks[MSTP116]),
 	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",	&mstp_clks[MSTP117]),
 	CLKDEV_DEV_ID("sh_tmu.0",		&mstp_clks[MSTP125]),
 	CLKDEV_DEV_ID("sh_tmu.1",		&mstp_clks[MSTP125]),
@@ -585,6 +586,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e6138010.timer",		&mstp_clks[MSTP329]),
 	CLKDEV_DEV_ID("sh_fsi2",		&mstp_clks[MSTP328]),
 	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
+	CLKDEV_DEV_ID("e6c20000.i2c",		&mstp_clks[MSTP323]),
 	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0",	&mstp_clks[MSTP314]),
 	CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:52 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:52 +0900
Subject: [PATCH 11/12] ARM: shmobile: fix sleep-r8a7740.S miscompiles
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-12-git-send-email-horms+renesas@verge.net.au>

From: Arnd Bergmann <arnd at arndb.de>

The newly added sleep-r8a7740.S file in shmobile does not
actually build because of renamed symbols.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Bastian Hecht <hechtb+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/sleep-r8a7740.S |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/sleep-r8a7740.S b/arch/arm/mach-shmobile/sleep-r8a7740.S
index 435531b..982eacb 100644
--- a/arch/arm/mach-shmobile/sleep-r8a7740.S
+++ b/arch/arm/mach-shmobile/sleep-r8a7740.S
@@ -32,7 +32,7 @@ ENTRY(r8a7740_shutdown)
 wfi_loop:
 	bl	cpu_v7_do_idle
 	b wfi_loop
-ENDPROC(r8a7740)
+ENDPROC(r8a7740_shutdown)
 
 	.text
 ENTRY(v7_cpu_resume)
@@ -53,5 +53,5 @@ ENDPROC(v7_cpu_resume)
 ENTRY(r8a7740_resume)
 	ldr	pc, 1f
 1:	.long	v7_cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(r8a7740_resume_core_standby)
+ENDPROC(r8a7740_resume)
 #endif
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:46 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:46 +0900
Subject: [PATCH 05/12] ARM: shmobile: r8a7740: Make private clock arrays static
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-6-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as
non-static. Compiling support for both SoCs thus result in a symbol
redefinition. Fix it by defining the arrays as static.

To avoid further similar issues, also define the main_clks as static.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 8fc396a..a2a612f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
 static struct clk fsibck_clk = {
 };
 
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,
 	&extal2_clk,
@@ -317,7 +317,7 @@ enum {
 	DIV4_NR
 };
 
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_I]	= SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
 	[DIV4_ZG]	= SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
 	[DIV4_B]	= SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:48 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:48 +0900
Subject: [PATCH 07/12] ARM: shmobile: r8a7740: Add OF support to initialze the
 GIC
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-8-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

We add a variant to initalize the interrupt controller in case we describe
the GIC using the Device Tree and not platform data.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h |    1 +
 arch/arm/mach-shmobile/intc-r8a7740.c         |   24 ++++++++++++++++++------
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4..19c0423 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -534,6 +534,7 @@ enum {
 
 extern void r8a7740_meram_workaround(void);
 extern void r8a7740_init_irq(void);
+extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index b741c84..8871f77 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -20,19 +20,15 @@
 
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 
-void __init r8a7740_init_irq(void)
+static void __init r8a7740_init_irq_common(void)
 {
-	void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
-	void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
 	void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 	void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 	void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 
-	/* initialize the Generic Interrupt Controller PL390 r0p0 */
-	gic_init(0, 29, gic_dist_base, gic_cpu_base);
-
 	/* route signals to GIC */
 	iowrite32(0x0, pfc_inta_ctrl);
 
@@ -54,3 +50,19 @@ void __init r8a7740_init_irq(void)
 	iounmap(intc_msk_base);
 	iounmap(pfc_inta_ctrl);
 }
+
+void __init r8a7740_init_irq_of(void)
+{
+	irqchip_init();
+	r8a7740_init_irq_common();
+}
+
+void __init r8a7740_init_irq(void)
+{
+	void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
+	void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
+
+	/* initialize the Generic Interrupt Controller PL390 r0p0 */
+	gic_init(0, 29, gic_dist_base, gic_cpu_base);
+	r8a7740_init_irq_common();
+}
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:53 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:53 +0900
Subject: [PATCH 12/12] ARM: shmobile: clock-r8a7740: add TPU PWM support
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-13-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Tested-by: Simon Horman <horms at verge.net.au>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index b12c476..6ad4640 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -461,7 +461,7 @@ enum {
 
 	MSTP329, MSTP328, MSTP323, MSTP320,
 	MSTP314, MSTP313, MSTP312,
-	MSTP309,
+	MSTP309, MSTP304,
 
 	MSTP416, MSTP415, MSTP407, MSTP406,
 
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 13, 0), /* SDHI1 */
 	[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 12, 0), /* MMC */
 	[MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3,  9, 0), /* GEther */
+	[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP],	SMSTPCR3,  4, 0), /* TPU0 */
 
 	[MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR4, 16, 0), /* USBHOST */
 	[MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR4, 15, 0), /* SDHI2 */
@@ -596,6 +597,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
 	CLKDEV_DEV_ID("sh-eth",			&mstp_clks[MSTP309]),
 	CLKDEV_DEV_ID("e9a00000.sh-eth",	&mstp_clks[MSTP309]),
+	CLKDEV_DEV_ID("renesas_tpu_pwm",	&mstp_clks[MSTP304]),
 
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2",	&mstp_clks[MSTP415]),
 	CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:04 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:04 +0900
Subject: [GIT PULL] Renesas ARM based r8a7779 SoC updates for v3.11
Message-ID: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a7779-for-v3.11

for you to fetch changes up to b2616eaa65e3ef188ececacdacbd42ce8a778ed9:

  ARM: shmobile: r8A7779: fix Ether device name (2013-05-22 22:17:33 +0900)

----------------------------------------------------------------
Renesas ARM based r8a7740 SoC updates for v3.11

* Correct Ether device's platform device name. By Sergei Shtylyov.
* Add PCIe clocks. By Phil Edworthy.

----------------------------------------------------------------
Phil Edworthy (1):
      ARM: shmobile: r8a7779: Add PCIe clocks

Sergei Shtylyov (1):
      ARM: shmobile: r8A7779: fix Ether device name

 arch/arm/mach-shmobile/clock-r8a7779.c |    4 +++-
 arch/arm/mach-shmobile/setup-r8a7779.c |    2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)


From horms+renesas at verge.net.au  Mon May 27 04:59:51 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:51 +0900
Subject: [PATCH 10/12] ARM: shmobile: r8a7740: Add CPUIdle
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-11-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

We make use of the r8a7740 Suspend To Ram code to plug together a
CPUIdle driver.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-shmobile/Makefile               |    2 +-
 arch/arm/mach-shmobile/cpuidle-r8a7740.c      |   62 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/include/mach/r8a7740.h |    1 +
 arch/arm/mach-shmobile/pm-r8a7740.c           |    1 +
 4 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-shmobile/cpuidle-r8a7740.c

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 0568894..2852dcf 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -30,7 +30,7 @@ obj-$(CONFIG_SUSPEND)		+= suspend.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ARCH_SHMOBILE)	+= pm-rmobile.o
 obj-$(CONFIG_ARCH_SH7372)	+= pm-sh7372.o sleep-sh7372.o
-obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o sleep-r8a7740.o
+obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o sleep-r8a7740.o cpuidle-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
 obj-$(CONFIG_ARCH_SH73A0)	+= pm-sh73a0.o
 
diff --git a/arch/arm/mach-shmobile/cpuidle-r8a7740.c b/arch/arm/mach-shmobile/cpuidle-r8a7740.c
new file mode 100644
index 0000000..48c7a6c
--- /dev/null
+++ b/arch/arm/mach-shmobile/cpuidle-r8a7740.c
@@ -0,0 +1,62 @@
+/*
+ * CPUIdle code for SoC r8a7740
+ *
+ * Copyright (C) 2013 Bastian Hecht
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/cpuidle.h>
+#include <mach/common.h>
+#include <mach/r8a7740.h>
+
+#if defined(CONFIG_SUSPEND) && defined(CONFIG_CPU_IDLE)
+static int r8a7740_enter_a3sm_pll_on(struct cpuidle_device *dev,
+					struct cpuidle_driver *drv, int index)
+{
+	r8a7740_enter_a3sm_common(1);
+	return 1;
+}
+
+static int r8a7740_enter_a3sm_pll_off(struct cpuidle_device *dev,
+					struct cpuidle_driver *drv, int index)
+{
+	r8a7740_enter_a3sm_common(0);
+	return 2;
+}
+
+static struct cpuidle_driver r8a7740_cpuidle_driver = {
+	.name			= "r8a7740_cpuidle",
+	.owner			= THIS_MODULE,
+	.en_core_tk_irqen	= 1,
+	.state_count		= 3,
+	.safe_state_index	= 0, /* C1 */
+	.states[0] = ARM_CPUIDLE_WFI_STATE,
+	.states[1] = {
+		.name = "C2",
+		.desc = "A3SM PLL ON",
+		.exit_latency = 40,
+		.target_residency = 30 + 40,
+		.flags = CPUIDLE_FLAG_TIME_VALID,
+		.enter = r8a7740_enter_a3sm_pll_on,
+	},
+	.states[2] = {
+		.name = "C3",
+		.desc = "A3SM PLL OFF",
+		.exit_latency = 120,
+		.target_residency = 30 + 120,
+		.flags = CPUIDLE_FLAG_TIME_VALID,
+		.enter = r8a7740_enter_a3sm_pll_off,
+	},
+};
+
+void r8a7740_cpuidle_init(void)
+{
+	shmobile_cpuidle_set_driver(&r8a7740_cpuidle_driver);
+}
+#else
+void r8a7740_cpuidle_init(void) {}
+#endif
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 5cfe5d9..3b538e3 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -545,6 +545,7 @@ extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
 extern void r8a7740_resume(void);
 extern void r8a7740_shutdown(void);
+extern void r8a7740_cpuidle_init(void);
 extern void r8a7740_enter_a3sm_common(int);
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index fe3c867..2f196bd 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -237,4 +237,5 @@ static void r8a7740_suspend_init(void) {}
 void __init r8a7740_pm_init(void)
 {
 	r8a7740_suspend_init();
+	r8a7740_cpuidle_init();
 }
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:20 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:20 +0900
Subject: [PATCH 3/7] ARM: shmobile: r8a7790: add div6 clocks
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-4-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

DIV6 clocks control SD*/MMC* core clocks.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c |   34 ++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index c85e643..a481003 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -52,6 +52,12 @@
 
 #define MODEMR		0xE6160060
 #define SDCKCR		0xE6150074
+#define SD2CKCR		0xE6150078
+#define SD3CKCR		0xE615007C
+#define MMC0CKCR	0xE6150240
+#define MMC1CKCR	0xE6150244
+#define SSPCKCR		0xE6150248
+#define SSPRSCKCR	0xE615024C
 
 static struct clk_mapping cpg_mapping = {
 	.phys   = CPG_BASE,
@@ -154,6 +160,23 @@ struct clk div4_clks[DIV4_NR] = {
 	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
 };
 
+/* DIV6 clocks */
+enum {
+	DIV6_SD2, DIV6_SD3,
+	DIV6_MMC0, DIV6_MMC1,
+	DIV6_SSP, DIV6_SSPRS,
+	DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+	[DIV6_SD2]	= SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+	[DIV6_SD3]	= SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
+	[DIV6_MMC0]	= SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
+	[DIV6_MMC1]	= SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
+	[DIV6_SSP]	= SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
+	[DIV6_SSPRS]	= SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
+};
+
 /* MSTP */
 enum { MSTP721, MSTP720,
 	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
@@ -202,6 +225,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("sd0",		&div4_clks[DIV4_SD0]),
 	CLKDEV_CON_ID("sd1",		&div4_clks[DIV4_SD1]),
 
+	/* DIV6 */
+	CLKDEV_CON_ID("sd2",		&div6_clks[DIV6_SD2]),
+	CLKDEV_CON_ID("sd3",		&div6_clks[DIV6_SD3]),
+	CLKDEV_CON_ID("mmc0",		&div6_clks[DIV6_MMC0]),
+	CLKDEV_CON_ID("mmc1",		&div6_clks[DIV6_MMC1]),
+	CLKDEV_CON_ID("ssp",		&div6_clks[DIV6_SSP]),
+	CLKDEV_CON_ID("ssprs",		&div6_clks[DIV6_SSPRS]),
+
 	/* MSTP */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
@@ -265,6 +296,9 @@ void __init r8a7790_clock_init(void)
 		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
 	if (!ret)
+		ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+	if (!ret)
 		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:22 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:22 +0900
Subject: [PATCH 5/7] ARM: shmobile: r8a7790: Remove init_irq declaration in
 machine description
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-6-git-send-email-horms+renesas@verge.net.au>

From: Maxime Ripard <maxime.ripard at free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7790.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d5..2a7a276 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -19,7 +19,6 @@
  */
 
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
@@ -142,7 +141,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
-	.init_irq	= irqchip_init,
 	.init_machine	= r8a7790_add_standard_devices_dt,
 	.init_time	= r8a7790_timer_init,
 	.dt_compat	= r8a7790_boards_compat_dt,
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:49 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:49 +0900
Subject: [PATCH 08/12] ARM: shmobile: r8a7740: Prepare for reference DT setup
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-9-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

We need three steps to prepare for the new Armadillo reference DT board code:
 - Split the device list into r8a7740_early_devices used by the old platform
   data setup (board-armadillo.c) and r8a7740_devices_dt used by both
   setup variants.
 - Introduce new r8a7740_init_delay() to be more flexible about calling
   shmobile_setup_delay().
 - For the generic r8a7740 support, we switch to device tree setup for
   the GIC, the irqpin devices and the I2C controllers.

This is slightly similar to commit 3b00f9342623a5ebc
"ARM: shmobile: sh73a0: Do not use early devices with DT reference"

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/r8a7740.dtsi                |  117 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/include/mach/r8a7740.h |    2 +
 arch/arm/mach-shmobile/setup-r8a7740.c        |   54 ++++++------
 3 files changed, 148 insertions(+), 25 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35..25dc930 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -18,4 +18,121 @@
 			compatible = "arm,cortex-a9";
 		};
 	};
+
+	gic: interrupt-controller at c2800000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0xc2800000 0x1000>,
+		      <0xc2000000 0x1000>;
+	};
+
+	/* irqpin0: IRQ0 - IRQ7 */
+	irqpin0: irqpin at e6900000 {
+		compatible = "renesas,intc-irqpin";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0xe6900000 4>,
+			<0xe6900010 4>,
+			<0xe6900020 1>,
+			<0xe6900040 1>,
+			<0xe6900060 1>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4>;
+	};
+
+	/* irqpin1: IRQ8 - IRQ15 */
+	irqpin1: irqpin at e6900004 {
+		compatible = "renesas,intc-irqpin";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0xe6900004 4>,
+			<0xe6900014 4>,
+			<0xe6900024 1>,
+			<0xe6900044 1>,
+			<0xe6900064 1>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4>;
+	};
+
+	/* irqpin2: IRQ16 - IRQ23 */
+	irqpin2: irqpin at e6900008 {
+		compatible = "renesas,intc-irqpin";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0xe6900008 4>,
+			<0xe6900018 4>,
+			<0xe6900028 1>,
+			<0xe6900048 1>,
+			<0xe6900068 1>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4>;
+	};
+
+	/* irqpin3: IRQ24 - IRQ31 */
+	irqpin3: irqpin at e690000c {
+		compatible = "renesas,intc-irqpin";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0xe690000c 4>,
+			<0xe690001c 4>,
+			<0xe690002c 1>,
+			<0xe690004c 1>,
+			<0xe690006c 1>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4
+			      0 149 0x4>;
+	};
+
+	i2c0: i2c at fff20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xfff20000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 201 0x4
+			      0 202 0x4
+			      0 203 0x4
+			      0 204 0x4>;
+	};
+
+	i2c1: i2c at e6c20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xe6c20000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 70 0x4
+			      0 71 0x4
+			      0 72 0x4
+			      0 73 0x4>;
+	};
 };
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 19c0423..1cf6869 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -533,11 +533,13 @@ enum {
 };
 
 extern void r8a7740_meram_workaround(void);
+extern void r8a7740_init_delay(void);
 extern void r8a7740_init_irq(void);
 extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
+extern void r8a7740_add_standard_devices_dt(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 3a6b6fe..00c5a70 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -517,11 +517,7 @@ static struct platform_device ipmmu_device = {
 	.num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *r8a7740_early_devices[] __initdata = {
-	&irqpin0_device,
-	&irqpin1_device,
-	&irqpin2_device,
-	&irqpin3_device,
+static struct platform_device *r8a7740_devices_dt[] __initdata = {
 	&scif0_device,
 	&scif1_device,
 	&scif2_device,
@@ -532,6 +528,13 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
 	&scif7_device,
 	&scifb_device,
 	&cmt10_device,
+};
+
+static struct platform_device *r8a7740_early_devices[] __initdata = {
+	&irqpin0_device,
+	&irqpin1_device,
+	&irqpin2_device,
+	&irqpin3_device,
 	&tmu00_device,
 	&tmu01_device,
 	&tmu02_device,
@@ -951,6 +954,8 @@ void __init r8a7740_add_standard_devices(void)
 	/* add devices */
 	platform_add_devices(r8a7740_early_devices,
 			    ARRAY_SIZE(r8a7740_early_devices));
+	platform_add_devices(r8a7740_devices_dt,
+			    ARRAY_SIZE(r8a7740_devices_dt));
 	platform_add_devices(r8a7740_late_devices,
 			     ARRAY_SIZE(r8a7740_late_devices));
 
@@ -972,6 +977,8 @@ void __init r8a7740_add_early_devices(void)
 {
 	early_platform_add_devices(r8a7740_early_devices,
 				   ARRAY_SIZE(r8a7740_early_devices));
+	early_platform_add_devices(r8a7740_devices_dt,
+				   ARRAY_SIZE(r8a7740_devices_dt));
 
 	/* setup early console here as well */
 	shmobile_setup_console();
@@ -979,33 +986,29 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init r8a7740_add_early_devices_dt(void)
-{
-	shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-
-	early_platform_add_devices(r8a7740_early_devices,
-				   ARRAY_SIZE(r8a7740_early_devices));
-
-	/* setup early console here as well */
-	shmobile_setup_console();
-}
-
 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
 	{ }
 };
 
 void __init r8a7740_add_standard_devices_dt(void)
 {
-	/* clocks are setup late during boot in the case of DT */
-	r8a7740_clock_init(0);
-
-	platform_add_devices(r8a7740_early_devices,
-			    ARRAY_SIZE(r8a7740_early_devices));
-
+	platform_add_devices(r8a7740_devices_dt,
+			    ARRAY_SIZE(r8a7740_devices_dt));
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     r8a7740_auxdata_lookup, NULL);
 }
 
+void __init r8a7740_init_delay(void)
+{
+	shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+};
+
+static void __init r8a7740_generic_init(void)
+{
+	r8a7740_clock_init(0);
+	r8a7740_add_standard_devices_dt();
+}
+
 static const char *r8a7740_boards_compat_dt[] __initdata = {
 	"renesas,r8a7740",
 	NULL,
@@ -1013,9 +1016,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 	.map_io		= r8a7740_map_io,
-	.init_early	= r8a7740_add_early_devices_dt,
-	.init_irq	= r8a7740_init_irq,
-	.init_machine	= r8a7740_add_standard_devices_dt,
+	.init_early	= r8a7740_init_delay,
+	.init_irq	= r8a7740_init_irq_of,
+	.init_machine	= r8a7740_generic_init,
+	.init_time	= shmobile_timer_init,
 	.dt_compat	= r8a7740_boards_compat_dt,
 MACHINE_END
 
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:19 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:19 +0900
Subject: [PATCH 2/7] ARM: shmobile: r8a7790: add div4 clocks
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-3-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

DIV4 clocks control SD* core clocks.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 850e47f..c85e643 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -51,6 +51,7 @@
 #define SMSTPCR7 0xe615014c
 
 #define MODEMR		0xE6160060
+#define SDCKCR		0xE6150074
 
 static struct clk_mapping cpg_mapping = {
 	.phys   = CPG_BASE,
@@ -131,6 +132,29 @@ static struct clk *main_clks[] = {
 	&cp_clk,
 };
 
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+	.divisors = divisors,
+	.nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+	.div_mult_table = &div4_div_mult_table,
+};
+
+enum {
+	DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
+};
+
+struct clk div4_clks[DIV4_NR] = {
+	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+
+/* MSTP */
 enum { MSTP721, MSTP720,
 	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
@@ -173,6 +197,11 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("qspi",		&qspi_clk),
 	CLKDEV_CON_ID("cp",		&cp_clk),
 
+	/* DIV4 */
+	CLKDEV_CON_ID("sdh",		&div4_clks[DIV4_SDH]),
+	CLKDEV_CON_ID("sd0",		&div4_clks[DIV4_SD0]),
+	CLKDEV_CON_ID("sd1",		&div4_clks[DIV4_SD1]),
+
 	/* MSTP */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
@@ -233,6 +262,9 @@ void __init r8a7790_clock_init(void)
 		ret = clk_register(main_clks[k]);
 
 	if (!ret)
+		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+	if (!ret)
 		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 04:59:50 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 17:59:50 +0900
Subject: [PATCH 09/12] ARM: shmobile: r8a7740: Add Suspend-To-RAM A3SM
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645193-3595-10-git-send-email-horms+renesas@verge.net.au>

From: Bastian Hecht <hechtb at gmail.com>

We add 2 Suspend to RAM modes:
- A3SM PLL0 on/off:     Power domain A3SM that contains the ARM core
                        and the 2nd level cache with either PLL0 on
                        or off

As the suspend to memory mechanism we use A3SM PLL off. A3SM PLL on
is included here too, so CPUIdle can use both power down modes (not
included in this patch).

The setup of the SYSC regarding the external IRQs is taken from
pm-sh7372.c from Magnus Damm.

Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
---
 arch/arm/mach-shmobile/Makefile               |    2 +-
 arch/arm/mach-shmobile/include/mach/r8a7740.h |    3 +
 arch/arm/mach-shmobile/pm-r8a7740.c           |  164 ++++++++++++++++++++++++-
 arch/arm/mach-shmobile/sleep-r8a7740.S        |   57 +++++++++
 4 files changed, 222 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/sleep-r8a7740.S

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 068f1da..0568894 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -30,7 +30,7 @@ obj-$(CONFIG_SUSPEND)		+= suspend.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ARCH_SHMOBILE)	+= pm-rmobile.o
 obj-$(CONFIG_ARCH_SH7372)	+= pm-sh7372.o sleep-sh7372.o
-obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o
+obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o sleep-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
 obj-$(CONFIG_ARCH_SH73A0)	+= pm-sh73a0.o
 
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 1cf6869..5cfe5d9 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -543,6 +543,9 @@ extern void r8a7740_add_standard_devices_dt(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
+extern void r8a7740_resume(void);
+extern void r8a7740_shutdown(void);
+extern void r8a7740_enter_a3sm_common(int);
 
 #ifdef CONFIG_PM
 extern void __init r8a7740_init_pm_domains(void);
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index 40b87aa..fe3c867 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -8,10 +8,52 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#include <linux/bitrev.h>
 #include <linux/console.h>
+#include <linux/module.h>
 #include <linux/suspend.h>
+#include <linux/io.h>
+#include <asm/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <mach/pm-rmobile.h>
 #include <mach/common.h>
+#include <mach/r8a7740.h>
+
+/* CPGA */
+#define PLLC01STPCR	IOMEM(0xe61500c8)
+#define SYSTBCR		IOMEM(0xe6150024)
+
+/* SYSC */
+#define STBCHR		IOMEM(0xe6180000)
+#define STBCHRB		IOMEM(0xe6180040)
+#define SPDCR		IOMEM(0xe6180008)
+#define SBAR		IOMEM(0xe6180020)
+#define SRSTFR		IOMEM(0xe61800B4)
+#define WUPSMSK		IOMEM(0xe618002c)
+#define WUPSMSK2	IOMEM(0xe6180048)
+#define WUPSFAC		IOMEM(0xe6180098)
+#define IRQCR		IOMEM(0xe618022c)
+#define IRQCR2		IOMEM(0xe6180238)
+#define IRQCR3		IOMEM(0xe6180244)
+#define IRQCR4		IOMEM(0xe6180248)
+
+/* SRSTFR flags */
+#define RAMST		(1 << 19)
+#define RCLNKA		(1 << 7)
+#define RCPRES		(1 << 5)
+#define RCWD1		(1 << 4)
+#define RPF		(1 << 0)
+
+/* INTC */
+#define ICR1A		IOMEM(0xe6900000)
+#define ICR2A		IOMEM(0xe6900004)
+#define ICR3A		IOMEM(0xe6900008)
+#define ICR4A		IOMEM(0xe690000c)
+#define INTMSK00A	IOMEM(0xe6900040)
+#define INTMSK10A	IOMEM(0xe6900044)
+#define INTMSK20A	IOMEM(0xe6900048)
+#define INTMSK30A	IOMEM(0xe690004c)
 
 #ifdef CONFIG_PM
 static int r8a7740_pd_a4s_suspend(void)
@@ -58,13 +100,129 @@ void __init r8a7740_init_pm_domains(void)
 	rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
 	pm_genpd_add_subdomain_names("A4S", "A3SP");
 }
-
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_SUSPEND
+static void r8a7740_set_reset_vector(unsigned long address)
+{
+	__raw_writel(address, SBAR);
+}
+
+static void r8a7740_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
+{
+	u16 tmp, irqcr1, irqcr2;
+	int k;
+
+	irqcr1 = 0;
+	irqcr2 = 0;
+
+	/* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
+	for (k = 0; k <= 7; k++) {
+		tmp = (icr >> ((7 - k) * 4)) & 0xf;
+		irqcr1 |= (tmp & 0x03) << (k * 2);
+		irqcr2 |= (tmp >> 2) << (k * 2);
+	}
+
+	*irqcr1p = irqcr1;
+	*irqcr2p = irqcr2;
+}
+
+static void r8a7740_setup_sysc(unsigned long msk, unsigned long msk2)
+{
+	u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
+	unsigned long tmp;
+
+	/* read IRQ0A -> IRQ15A mask */
+	tmp = bitrev8(__raw_readb(INTMSK00A));
+	tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
+
+	/* setup WUPSMSK from clocks and external IRQ mask */
+	msk = (~msk & 0xc030000f) | (tmp << 4);
+	__raw_writel(msk, WUPSMSK);
+
+	/* propage level/edge trigger for external IRQ 0->15 */
+	r8a7740_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
+	r8a7740_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
+	__raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
+	__raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
+
+	/* read IRQ16A -> IRQ31A mask */
+	tmp = bitrev8(__raw_readb(INTMSK20A));
+	tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
+
+	/* setup WUPSMSK2 from clocks and external IRQ mask */
+	msk2 = (~msk2 & 0x00030000) | tmp;
+	__raw_writel(msk2, WUPSMSK2);
+
+	/* propage level/edge trigger for external IRQ 16->31 */
+	r8a7740_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
+	r8a7740_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
+	__raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
+	__raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
+}
+
+static void r8a7740_prepare_wakeup(void)
+{
+	/* clear all flags that lead to a cold boot */
+	__raw_writel(~(RAMST | RCLNKA | RCPRES | RCWD1 | RPF), SRSTFR);
+	/* indicate warm boot */
+	__raw_writel(0x80000000, STBCHRB);
+	/* clear other flags checked by internal ROM boot loader */
+	__raw_writel(0x00000000, STBCHR);
+}
+
+static int r8a7740_do_suspend(unsigned long unused)
+{
+	/*
+	 * cpu_suspend() guarantees that all data made it to the L2.
+	 * Flush it out now and disable the cache controller.
+	 */
+	outer_flush_all();
+	outer_disable();
+
+	r8a7740_shutdown();
+
+	return 0;
+}
+
+void r8a7740_enter_a3sm_common(int pllc0_on)
+{
+	u32 reg32;
+
+	if (pllc0_on)
+		__raw_writel(0, PLLC01STPCR);
+	else
+		__raw_writel(1 << 28, PLLC01STPCR);
+
+	r8a7740_set_reset_vector(__pa(r8a7740_resume));
+	r8a7740_prepare_wakeup();
+	r8a7740_setup_sysc(1 << 0, 0);
+
+	/* Activate delayed shutdown of A3SM */
+	reg32 = __raw_readl(SPDCR);
+	reg32 |= (1 << 31) | (1 << 12);
+	__raw_writel(reg32, SPDCR);
+
+	/* We activate CPU Core Standby as well here */
+	reg32 = __raw_readl(SYSTBCR);
+	reg32 |= (1 << 4);
+	__raw_writel(reg32, SYSTBCR);
+
+	/* Clear Wakeup Factors and do suspend */
+	reg32 = __raw_readl(WUPSFAC);
+	cpu_suspend(0, r8a7740_do_suspend);
+	outer_resume();
+	reg32 = __raw_readl(WUPSFAC);
+
+	/* Clear CPU Core Standby flag for other WFI instructions */
+	reg32 &= ~(1 << 4);
+	__raw_writel(reg32, SYSTBCR);
+
+}
+
 static int r8a7740_enter_suspend(suspend_state_t suspend_state)
 {
-	cpu_do_idle();
+	r8a7740_enter_a3sm_common(0);
 	return 0;
 }
 
@@ -74,7 +232,7 @@ static void r8a7740_suspend_init(void)
 }
 #else
 static void r8a7740_suspend_init(void) {}
-#endif
+#endif /* CONFIG_SUSPEND */
 
 void __init r8a7740_pm_init(void)
 {
diff --git a/arch/arm/mach-shmobile/sleep-r8a7740.S b/arch/arm/mach-shmobile/sleep-r8a7740.S
new file mode 100644
index 0000000..435531b
--- /dev/null
+++ b/arch/arm/mach-shmobile/sleep-r8a7740.S
@@ -0,0 +1,57 @@
+/*
+ * Low level sleep code for the SoC r8a7740
+ *
+ * Copyright (C) 2013 Bastian Hecht
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+
+#ifdef CONFIG_SUSPEND
+
+/* r8a7740_shutdown expects L2 to be flushed */
+	.text
+ENTRY(r8a7740_shutdown)
+	/*
+	 * Clear the SCTLR.C bit to prevent further data cache
+	 * allocation. Clearing SCTLR.C would make all the data accesses
+	 * strongly ordered and would not hit the cache.
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #(1 << 2)		@ Disable the C bit
+	mcr	p15, 0, r0, c1, c0, 0
+	isb
+
+	bl      v7_flush_dcache_all
+
+wfi_loop:
+	bl	cpu_v7_do_idle
+	b wfi_loop
+ENDPROC(r8a7740)
+
+	.text
+ENTRY(v7_cpu_resume)
+	bl	v7_invalidate_l1
+	b	cpu_resume
+ENDPROC(v7_cpu_resume)
+
+/*
+ * The entry point of a warm reboot, used by wakeup scenarios
+ *
+ * The CPU jumps in this case to (0xfffff000 & SBAR), so we need
+ * to align this function properly.
+ * We use a long jump into the text segment and use the physical
+ * address as the MMU is still turned off.
+ */
+	.align	12
+	.text
+ENTRY(r8a7740_resume)
+	ldr	pc, 1f
+1:	.long	v7_cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(r8a7740_resume_core_standby)
+#endif
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:42 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:42 +0900
Subject: [PATCH 2/2] ARM: shmobile: sh7372 pinmux platform device cleanup
In-Reply-To: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645242-3803-3-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Use DEFINE_RES_MEM() and platform_device_register_simple()
to save a couple of lines of code.

Signed-off-by: Magnus Damm <damm at opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh7372.c |   24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5502d62..c70a3cc 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -62,29 +62,15 @@ void __init sh7372_map_io(void)
 }
 
 /* PFC */
-static struct resource sh7372_pfc_resources[] = {
-	[0] = {
-		.start	= 0xe6050000,
-		.end	= 0xe6057fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0xe605800c,
-		.end	= 0xe6058027,
-		.flags	= IORESOURCE_MEM,
-	}
-};
-
-static struct platform_device sh7372_pfc_device = {
-	.name		= "pfc-sh7372",
-	.id		= -1,
-	.resource	= sh7372_pfc_resources,
-	.num_resources	= ARRAY_SIZE(sh7372_pfc_resources),
+static const struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xe6050000, 0x8000),
+	DEFINE_RES_MEM(0xe605800c, 0x001c),
 };
 
 void __init sh7372_pinmux_init(void)
 {
-	platform_device_register(&sh7372_pfc_device);
+	platform_device_register_simple("pfc-sh7372", -1, pfc_resources,
+					ARRAY_SIZE(pfc_resources));
 }
 
 /* SCIFA0 */
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:44 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:44 +0900
Subject: [GIT PULL] Renesas ARM based sh73a0 SoC updates for v3.11
Message-ID: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-sh73a0-for-v3.11

for you to fetch changes up to 8a6fca8ecd467a6255bda134d89fcda9ae1556ce:

  ARM: shmobile: sh73a0: div4 clocks must check the kick bit before changing rate (2013-05-25 09:57:10 +0900)

----------------------------------------------------------------
Renesas ARM based sh73a0 SoC updates for v3.11

* Change by Magnus Damm to use shmobile_setup_delay() when initialising
  the SoC using C-code, as was already the case when initialising the
  SoC using OF. This allows boot with TWD only.
* CPUFreq support by Guennadi Liakhovetski
* Clean-ups from Magnus Damm and Simon Horman to use DEFINE_RES_MEM()
* Clean-up from Maxime Ripard to remove unnecessary init_irq declaration in
  machine description.

----------------------------------------------------------------
Guennadi Liakhovetski (4):
      ARM: shmobile: sh73a0: add support for adjusting CPU frequency
      ARM: shmobile: sh73a0: add CPUFreq support
      ARM: shmobile: sh73a0: do not overwrite all div4 clock operations
      ARM: shmobile: sh73a0: div4 clocks must check the kick bit before changing rate

Magnus Damm (2):
      ARM: shmobile: sh73a0 pinmux platform device cleanup
      ARM: shmobile: sh73a0: Always use shmobile_setup_delay()

Maxime Ripard (1):
      ARM: shmobile: sh73a0: Remove init_irq declaration in machine description

Simon Horman (1):
      ARM: shmobile: sh73a0: Use DEFINE_RES_MEM*() everywhere

 arch/arm/mach-shmobile/Kconfig        |    2 +
 arch/arm/mach-shmobile/clock-sh73a0.c |  111 +++++++++++++++++++++++++++++-
 arch/arm/mach-shmobile/setup-sh73a0.c |  122 ++++++++-------------------------
 3 files changed, 141 insertions(+), 94 deletions(-)


From horms+renesas at verge.net.au  Mon May 27 05:00:18 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:18 +0900
Subject: [PATCH 1/7] ARM: shmobile: r8a7790: add main clock
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-2-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Almost all clock needs main clock which is basis clock on r8a7790.
This patch adds it, and, set its parent/ratio via MD pin.
It is based on v0.05 datasheet

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c |  161 +++++++++++++++++++++++++++++++-
 1 file changed, 156 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2..850e47f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,32 +22,113 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
+/*
+ *   MD		EXTAL		PLL0	PLL1	PLL3
+ * 14 13 19	(MHz)		*1	*1
+ *---------------------------------------------------
+ * 0  0  0	15 x 1		x172/2	x208/2	x106
+ * 0  0  1	15 x 1		x172/2	x208/2	x88
+ * 0  1  0	20 x 1		x130/2	x156/2	x80
+ * 0  1  1	20 x 1		x130/2	x156/2	x66
+ * 1  0  0	26 / 2		x200/2	x240/2	x122
+ * 1  0  1	26 / 2		x200/2	x240/2	x102
+ * 1  1  0	30 / 2		x172/2	x208/2	x106
+ * 1  1  1	30 / 2		x172/2	x208/2	x88
+ *
+ * *1 :	Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *	see "p1 / 2" on R8A7790_CLOCK_ROOT() below
+ */
+
+#define MD(nr)	(1 << nr)
+
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR7 0xe615014c
 
+#define MODEMR		0xE6160060
+
 static struct clk_mapping cpg_mapping = {
 	.phys   = CPG_BASE,
 	.len    = CPG_LEN,
 };
 
-static struct clk p_clk = {
-	.rate	= 65000000, /* shortcut for now */
+static struct clk extal_clk = {
+	/* .rate will be updated on r8a7790_clock_init() */
 	.mapping	= &cpg_mapping,
 };
 
-static struct clk mp_clk = {
-	.rate	= 52000000,  /* shortcut for now */
-	.mapping	= &cpg_mapping,
+static struct sh_clk_ops followparent_clk_ops = {
+	.recalc	= followparent_recalc,
 };
 
+static struct clk main_clk = {
+	/* .parent will be set r8a73a4_clock_init */
+	.ops	= &followparent_clk_ops,
+};
+
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7790_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
+SH_FIXED_RATIO_CLK_SET(lb_clk,			pll1_clk,	1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,			extal_clk,	1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,		pll1_clk,	1, 2);
+SH_FIXED_RATIO_CLK_SET(zg_clk,			pll1_clk,	1, 3);
+SH_FIXED_RATIO_CLK_SET(zx_clk,			pll1_clk,	1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,			pll1_clk,	1, 6);
+SH_FIXED_RATIO_CLK_SET(hp_clk,			pll1_clk,	1, 12);
+SH_FIXED_RATIO_CLK_SET(i_clk,			pll1_clk,	1, 2);
+SH_FIXED_RATIO_CLK_SET(b_clk,			pll1_clk,	1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,			pll1_clk,	1, 24);
+SH_FIXED_RATIO_CLK_SET(cl_clk,			pll1_clk,	1, 48);
+SH_FIXED_RATIO_CLK_SET(m2_clk,			pll1_clk,	1, 8);
+SH_FIXED_RATIO_CLK_SET(imp_clk,			pll1_clk,	1, 4);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,		pll1_clk,	1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(oscclk_clk,		pll1_clk,	1, (12 * 1024));
+
+SH_FIXED_RATIO_CLK_SET(zb3_clk,			pll3_clk,	1, 4);
+SH_FIXED_RATIO_CLK_SET(zb3d2_clk,		pll3_clk,	1, 8);
+SH_FIXED_RATIO_CLK_SET(ddr_clk,			pll3_clk,	1, 8);
+SH_FIXED_RATIO_CLK_SET(mp_clk,			pll1_div2_clk,	1, 15);
+
 static struct clk *main_clks[] = {
+	&extal_clk,
+	&extal_div2_clk,
+	&main_clk,
+	&pll1_clk,
+	&pll1_div2_clk,
+	&pll3_clk,
+	&lb_clk,
+	&qspi_clk,
+	&zg_clk,
+	&zx_clk,
+	&zs_clk,
+	&hp_clk,
+	&i_clk,
+	&b_clk,
 	&p_clk,
+	&cl_clk,
+	&m2_clk,
+	&imp_clk,
+	&rclk_clk,
+	&oscclk_clk,
+	&zb3_clk,
+	&zb3d2_clk,
+	&ddr_clk,
 	&mp_clk,
+	&cp_clk,
 };
 
 enum { MSTP721, MSTP720,
@@ -64,6 +145,35 @@ static struct clk mstp_clks[MSTP_NR] = {
 };
 
 static struct clk_lookup lookups[] = {
+
+	/* main clocks */
+	CLKDEV_CON_ID("extal",		&extal_clk),
+	CLKDEV_CON_ID("extal_div2",	&extal_div2_clk),
+	CLKDEV_CON_ID("main",		&main_clk),
+	CLKDEV_CON_ID("pll1",		&pll1_clk),
+	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),
+	CLKDEV_CON_ID("pll3",		&pll3_clk),
+	CLKDEV_CON_ID("zg",		&zg_clk),
+	CLKDEV_CON_ID("zx",		&zx_clk),
+	CLKDEV_CON_ID("zs",		&zs_clk),
+	CLKDEV_CON_ID("hp",		&hp_clk),
+	CLKDEV_CON_ID("i",		&i_clk),
+	CLKDEV_CON_ID("b",		&b_clk),
+	CLKDEV_CON_ID("lb",		&lb_clk),
+	CLKDEV_CON_ID("p",		&p_clk),
+	CLKDEV_CON_ID("cl",		&cl_clk),
+	CLKDEV_CON_ID("m2",		&m2_clk),
+	CLKDEV_CON_ID("imp",		&imp_clk),
+	CLKDEV_CON_ID("rclk",		&rclk_clk),
+	CLKDEV_CON_ID("oscclk",		&oscclk_clk),
+	CLKDEV_CON_ID("zb3",		&zb3_clk),
+	CLKDEV_CON_ID("zb3d2",		&zb3d2_clk),
+	CLKDEV_CON_ID("ddr",		&ddr_clk),
+	CLKDEV_CON_ID("mp",		&mp_clk),
+	CLKDEV_CON_ID("qspi",		&qspi_clk),
+	CLKDEV_CON_ID("cp",		&cp_clk),
+
+	/* MSTP */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -74,10 +184,51 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 };
 
+#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
+	extal_clk.rate	= e * 1000 * 1000;			\
+	main_clk.parent	= m;					\
+	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);		\
+	if (mode & MD(19))					\
+		SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);	\
+	else							\
+		SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
 void __init r8a7790_clock_init(void)
 {
+	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+	u32 mode;
 	int k, ret = 0;
 
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	switch (mode & (MD(14) | MD(13))) {
+	case 0:
+		R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+		break;
+	case MD(13):
+		R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+		break;
+	case MD(14):
+		R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+		break;
+	case MD(13) | MD(14):
+		R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+		break;
+	}
+
+	if (mode & (MD(18)))
+		SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
+	else
+		SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
+
+	if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+	else
+		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
 	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 		ret = clk_register(main_clks[k]);
 
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:50 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:50 +0900
Subject: [PATCH 6/8] ARM: shmobile: sh73a0: Always use shmobile_setup_delay()
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-7-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Break out the function sh73a0_init_delay() that now
gets called both for the C version of the code and
the DT -reference boards. This way we handle both
cases in the same way.

Allows us to boot with TWD only in the kernel configuration
for C board code. TWD is not yet enabled in the case of
DT -reference - this due to a dependency on CCF.

Signed-off-by: Magnus Damm <damm at opensource.se>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 9986515..8bb879f 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -915,11 +915,17 @@ void __init sh73a0_add_standard_devices(void)
 			    ARRAY_SIZE(sh73a0_late_devices));
 }
 
+void __init sh73a0_init_delay(void)
+{
+	shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 
 void __init sh73a0_earlytimer_init(void)
 {
+	sh73a0_init_delay();
 	sh73a0_clock_init();
 	shmobile_earlytimer_init();
 	sh73a0_register_twd();
@@ -938,11 +944,6 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init sh73a0_init_delay(void)
-{
-	shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-}
-
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
 	{},
 };
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:49 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:49 +0900
Subject: [PATCH 5/8] ARM: shmobile: sh73a0: Remove init_irq declaration in
 machine description
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-6-git-send-email-horms+renesas@verge.net.au>

From: Maxime Ripard <maxime.ripard at free-electrons.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index cd81832..9986515 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,7 +22,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -974,7 +973,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 	.map_io		= sh73a0_map_io,
 	.init_early	= sh73a0_init_delay,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= irqchip_init,
 	.init_machine	= sh73a0_add_standard_devices_dt,
 	.dt_compat	= sh73a0_boards_compat_dt,
 MACHINE_END
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:24 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:24 +0900
Subject: [PATCH 7/7] ARM: shmobile: clock-r8a7790: add TPU PWM support
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-8-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c |   11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bedd20c..b393592 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -48,6 +48,7 @@
 #define CPG_LEN 0x1000
 
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
 
 #define MODEMR		0xE6160060
@@ -178,11 +179,17 @@ static struct clk div6_clks[DIV6_NR] = {
 };
 
 /* MSTP */
-enum { MSTP721, MSTP720,
-	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
+enum {
+	MSTP721, MSTP720,
+	MSTP304,
+	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+	MSTP_NR
+};
+
 static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+	[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
 	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
 	[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
 	[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:21 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:21 +0900
Subject: [PATCH 4/7] ARM: shmobile: r8a7790: Make private clock arrays static
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-5-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as
non-static. Compiling support for both SoCs thus result in a symbol
redefinition. Fix it by defining the arrays as static.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index a481003..bedd20c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -154,7 +154,7 @@ enum {
 	DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
 };
 
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
 	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
 	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:41 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:41 +0900
Subject: [PATCH 1/2] ARM: shmobile: remove ";
 " from SH_FIXED_RATIO_CLK*() macro
In-Reply-To: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645242-3803-2-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Acked-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/clock.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac612..8902044 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,11 +24,11 @@ struct clk name = {			\
 }
 
 #define SH_FIXED_RATIO_CLK(name, p, r)		\
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)	\
 	SH_CLK_RATIO(name, m, d);		\
-	SH_FIXED_RATIO_CLK(name, p, name);
+	SH_FIXED_RATIO_CLK(name, p, name)
 
 #define SH_CLK_SET_RATIO(p, m, d)	\
 {			\
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:23 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:23 +0900
Subject: [PATCH 6/7] ARM: shmobile: Remove unused r8a7790 GIC CPU interface DT
 bits
In-Reply-To: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645224-3728-7-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Remove unused GIC CPU interface DT bits for r8a7790.

Signed-off-by: Magnus Damm <damm at opensource.se>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/boot/dts/r8a7790.dtsi |    6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7a17110..339d9b1 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -36,12 +36,6 @@
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
 		interrupts = <1 9 0xf04>;
-
-		gic-cpuif at 4 {
-			compatible = "arm,gic-cpuif";
-			cpuif-id = <4>;
-			cpu = <&cpu0>;
-		};
 	};
 
 	timer {
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:40 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:40 +0900
Subject: [GIT PULL] Renesas ARM based sh7372 SoC updates for v3.11
Message-ID: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-sh7372-for-v3.11

for you to fetch changes up to 98aaf628f866f530ce6829476e1c2ac98c9c4f60:

  ARM: shmobile: sh7372 pinmux platform device cleanup (2013-05-22 21:46:25 +0900)

----------------------------------------------------------------
Renesas ARM based sh7372 SoC updates for v3.11

* Clean-up from Magnus Damm to use DEFINE_RES_MEM() to slightly reduce code size
* Clean-up from Kuninori Morimoto to remove trailing ; from macros

----------------------------------------------------------------
Kuninori Morimoto (1):
      ARM: shmobile: remove ";" from SH_FIXED_RATIO_CLK*() macro

Magnus Damm (1):
      ARM: shmobile: sh7372 pinmux platform device cleanup

 arch/arm/mach-shmobile/include/mach/clock.h |    4 ++--
 arch/arm/mach-shmobile/setup-sh7372.c       |   24 +++++-------------------
 2 files changed, 7 insertions(+), 21 deletions(-)


From horms+renesas at verge.net.au  Mon May 27 05:00:17 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:17 +0900
Subject: [GIT PULL] Renesas ARM based r8a7790 SoC updates for v3.11
Message-ID: <1369645224-3728-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a7790-for-v3.11

for you to fetch changes up to 3318ce6ff5a5dbebe472103966a2c6d7d9542ec3:

  ARM: shmobile: clock-r8a7790: add TPU PWM support (2013-05-27 17:50:51 +0900)

----------------------------------------------------------------
Renesas ARM based r8a7790 SoC updates for v3.11

* Increased clock coverage by Kuninori Morimoto.
* TOU PWM clock support by Laurent Pinchart.
* Clean-up from Maxime Ripard to remove unnecessary init_irq declaration in
  machine description.
* Clean-up from Magnus Damm to remove unused GIC CPU interface portions
  of r8a7790.dtsi
* Clean-up from Laurent Pinchart to make clock arrays static

----------------------------------------------------------------
Kuninori Morimoto (3):
      ARM: shmobile: r8a7790: add main clock
      ARM: shmobile: r8a7790: add div4 clocks
      ARM: shmobile: r8a7790: add div6 clocks

Laurent Pinchart (2):
      ARM: shmobile: r8a7790: Make private clock arrays static
      ARM: shmobile: clock-r8a7790: add TPU PWM support

Magnus Damm (1):
      ARM: shmobile: Remove unused r8a7790 GIC CPU interface DT bits

Maxime Ripard (1):
      ARM: shmobile: r8a7790: Remove init_irq declaration in machine description

 arch/arm/boot/dts/r8a7790.dtsi         |    6 -
 arch/arm/mach-shmobile/clock-r8a7790.c |  238 +++++++++++++++++++++++++++++++-
 arch/arm/mach-shmobile/setup-r8a7790.c |    2 -
 3 files changed, 231 insertions(+), 15 deletions(-)


From horms+renesas at verge.net.au  Mon May 27 05:00:45 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:45 +0900
Subject: [PATCH 1/8] ARM: shmobile: sh73a0 pinmux platform device cleanup
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-2-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Use DEFINE_RES_MEM() and platform_device_register_simple()
to save a couple of lines of code.

Signed-off-by: Magnus Damm <damm at opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c |   25 ++++++-------------------
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..f8f4261 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -61,29 +61,16 @@ void __init sh73a0_map_io(void)
 	iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
 }
 
-static struct resource sh73a0_pfc_resources[] = {
-	[0] = {
-		.start	= 0xe6050000,
-		.end	= 0xe6057fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0xe605801c,
-		.end	= 0xe6058027,
-		.flags	= IORESOURCE_MEM,
-	}
-};
-
-static struct platform_device sh73a0_pfc_device = {
-	.name		= "pfc-sh73a0",
-	.id		= -1,
-	.resource	= sh73a0_pfc_resources,
-	.num_resources	= ARRAY_SIZE(sh73a0_pfc_resources),
+/* PFC */
+static const struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xe6050000, 0x8000),
+	DEFINE_RES_MEM(0xe605801c, 0x000c),
 };
 
 void __init sh73a0_pinmux_init(void)
 {
-	platform_device_register(&sh73a0_pfc_device);
+	platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
+					ARRAY_SIZE(pfc_resources));
 }
 
 static struct plat_sci_port scif0_platform_data = {
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:47 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:47 +0900
Subject: [PATCH 3/8] ARM: shmobile: sh73a0: add CPUFreq support
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-4-git-send-email-horms+renesas@verge.net.au>

From: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0.
Providing a regulator, a list of OPPs in DT, combined with a virtual
cpufreq-cpu0 platform device and a clock, attached to it is everything,
the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing
such CPUFreq support is kzm9g-reference.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/Kconfig        |    2 ++
 arch/arm/mach-shmobile/setup-sh73a0.c |    5 +++++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2..7cfb9d1 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -169,6 +169,8 @@ config MACH_KZM9D
 config MACH_KZM9G
 	bool "KZM-A9-GT board"
 	depends on ARCH_SH73A0
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_OPP
 	select ARCH_REQUIRE_GPIOLIB
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
 	select SND_SOC_AK4642 if SND_SIMPLE_CARD
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index f8f4261..88e6ea0 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -1003,6 +1003,8 @@ static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
 
 void __init sh73a0_add_standard_devices_dt(void)
 {
+	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
+
 	/* clocks are setup late during boot in the case of DT */
 	sh73a0_clock_init();
 
@@ -1010,6 +1012,9 @@ void __init sh73a0_add_standard_devices_dt(void)
 			     ARRAY_SIZE(sh73a0_devices_dt));
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     sh73a0_auxdata_lookup, NULL);
+
+	/* Instantiate cpufreq-cpu0 */
+	platform_device_register_full(&devinfo);
 }
 
 static const char *sh73a0_boards_compat_dt[] __initdata = {
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:48 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:48 +0900
Subject: [PATCH 4/8] ARM: shmobile: sh73a0: Use DEFINE_RES_MEM*() everywhere
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-5-git-send-email-horms+renesas@verge.net.au>

Convert code to use DEFINE_RES_MEM*() macros.
These macros were already used in this file,
this change makes their usage consistent throughout the file.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c |   79 ++++++---------------------------
 1 file changed, 13 insertions(+), 66 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 88e6ea0..cd81832 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -275,12 +275,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 
 static struct resource tmu00_resources[] = {
-	[0] = {
-		.name	= "TMU00",
-		.start	= 0xfff60008,
-		.end	= 0xfff60013,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
 	[1] = {
 		.start	= intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 		.flags	= IORESOURCE_IRQ,
@@ -305,12 +300,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 
 static struct resource tmu01_resources[] = {
-	[0] = {
-		.name	= "TMU01",
-		.start	= 0xfff60014,
-		.end	= 0xfff6001f,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
 	[1] = {
 		.start	= intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 		.flags	= IORESOURCE_IRQ,
@@ -328,12 +318,7 @@ static struct platform_device tmu01_device = {
 };
 
 static struct resource i2c0_resources[] = {
-	[0] = {
-		.name	= "IIC0",
-		.start	= 0xe6820000,
-		.end	= 0xe6820425 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
 	[1] = {
 		.start	= gic_spi(167),
 		.end	= gic_spi(170),
@@ -342,12 +327,7 @@ static struct resource i2c0_resources[] = {
 };
 
 static struct resource i2c1_resources[] = {
-	[0] = {
-		.name	= "IIC1",
-		.start	= 0xe6822000,
-		.end	= 0xe6822425 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
 	[1] = {
 		.start	= gic_spi(51),
 		.end	= gic_spi(54),
@@ -356,12 +336,7 @@ static struct resource i2c1_resources[] = {
 };
 
 static struct resource i2c2_resources[] = {
-	[0] = {
-		.name	= "IIC2",
-		.start	= 0xe6824000,
-		.end	= 0xe6824425 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
 	[1] = {
 		.start	= gic_spi(171),
 		.end	= gic_spi(174),
@@ -370,12 +345,7 @@ static struct resource i2c2_resources[] = {
 };
 
 static struct resource i2c3_resources[] = {
-	[0] = {
-		.name	= "IIC3",
-		.start	= 0xe6826000,
-		.end	= 0xe6826425 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
 	[1] = {
 		.start	= gic_spi(183),
 		.end	= gic_spi(186),
@@ -384,12 +354,7 @@ static struct resource i2c3_resources[] = {
 };
 
 static struct resource i2c4_resources[] = {
-	[0] = {
-		.name	= "IIC4",
-		.start	= 0xe6828000,
-		.end	= 0xe6828425 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	[0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
 	[1] = {
 		.start	= gic_spi(187),
 		.end	= gic_spi(190),
@@ -610,12 +575,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 };
 
 static struct resource sh73a0_dmae_resources[] = {
-	{
-		/* Registers including DMAOR and channels including DMARSx */
-		.start  = 0xfe000020,
-		.end    = 0xfe008a00 - 1,
-		.flags  = IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(0xfe000020, 0x89e0),
 	{
 		.name	= "error_irq",
 		.start  = gic_spi(129),
@@ -714,18 +674,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 
 /* Resource order important! */
 static struct resource sh73a0_mpdma_resources[] = {
-	{
-		/* Channel registers and DMAOR */
-		.start	= 0xec618020,
-		.end	= 0xec61828f,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		/* DMARSx */
-		.start	= 0xec619000,
-		.end	= 0xec61900b,
-		.flags	= IORESOURCE_MEM,
-	},
+	/* Channel registers and DMAOR */
+	DEFINE_RES_MEM(0xec618020, 0x270),
+	/* DMARSx */
+	DEFINE_RES_MEM(0xec619000, 0xc),
 	{
 		.name	= "error_irq",
 		.start	= gic_spi(181),
@@ -772,12 +724,7 @@ static struct platform_device pmu_device = {
 
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-	[0] = {
-		.name	= "IPMMU",
-		.start	= 0xfe951000,
-		.end	= 0xfe9510ff,
-		.flags	= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
 };
 
 static const char * const ipmmu_dev_names[] = {
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:46 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:46 +0900
Subject: [PATCH 2/8] ARM: shmobile: sh73a0: add support for adjusting CPU
 frequency
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-3-git-send-email-horms+renesas@verge.net.au>

From: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to
the CPU core and SGX. Lower CPU frequencies allow the use of lower supply
voltages and thus reduce power consumption.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-sh73a0.c |   95 ++++++++++++++++++++++++++++++++-
 1 file changed, 93 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa..acb9e09 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+	/*
+	 * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
+	 * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
+	 * 239.2MHz for VDD_DVFS=1.315V.
+	 */
 	[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
 	[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
 	[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,85 @@ static struct clk twd_clk = {
 	.ops = &twd_clk_ops,
 };
 
+static int (*div4_set_rate)(struct clk *clk, unsigned long rate);
+static unsigned long (*div4_recalc)(struct clk *clk);
+static long (*div4_round_rate)(struct clk *clk, unsigned long rate);
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret;
+
+	if (!clk->parent || !__clk_get(clk->parent))
+		return -ENODEV;
+
+	if (readl(FRQCRB) & (1 << 31))
+		return -EBUSY;
+
+	if (rate == clk_get_rate(clk->parent)) {
+		/* 1:1 - switch off divider */
+		__raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
+		/* nullify the divider to prepare for the next time */
+		ret = div4_set_rate(clk, rate / 2);
+		if (!ret)
+			ret = frqcr_kick();
+		if (ret > 0)
+			ret = 0;
+	} else {
+		/* Enable the divider */
+		__raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
+
+		ret = frqcr_kick();
+		if (ret >= 0)
+			/*
+			 * set the divider - call the DIV4 method, it will kick
+			 * FRQCRB too
+			 */
+			ret = div4_set_rate(clk, rate);
+		if (ret < 0)
+			goto esetrate;
+	}
+
+esetrate:
+	__clk_put(clk->parent);
+	return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long div_freq = div4_round_rate(clk, rate),
+		parent_freq = clk_get_rate(clk->parent);
+
+	if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
+		return parent_freq;
+
+	return div_freq;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+	/*
+	 * Must recalculate frequencies in case PLL0 has been changed, even if
+	 * the divisor is unused ATM!
+	 */
+	unsigned long div_freq = div4_recalc(clk);
+
+	if (__raw_readl(FRQCRB) & (1 << 28))
+		return div_freq;
+
+	return clk_get_rate(clk->parent);
+}
+
+static void zclk_extend(void)
+{
+	/* We extend the DIV4 clock with a 1:1 pass-through case */
+	div4_set_rate = div4_clks[DIV4_Z].ops->set_rate;
+	div4_round_rate = div4_clks[DIV4_Z].ops->round_rate;
+	div4_recalc = div4_clks[DIV4_Z].ops->recalc;
+	div4_clks[DIV4_Z].ops->set_rate = zclk_set_rate;
+	div4_clks[DIV4_Z].ops->round_rate = zclk_round_rate;
+	div4_clks[DIV4_Z].ops->recalc = zclk_recalc;
+}
+
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
 	DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
 	DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +534,7 @@ static struct clk *late_main_clks[] = {
 };
 
 enum { MSTP001,
-	MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
+	MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
 	MSTP219, MSTP218, MSTP217,
 	MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
 	MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +555,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
 	[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
 	[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+	[MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
 	[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
 	[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
 	[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +598,9 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("r_clk", &r_clk),
 	CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
 
+	/* DIV4 clocks */
+	CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
+
 	/* DIV6 clocks */
 	CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
 	CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +692,11 @@ void __init sh73a0_clock_init(void)
 	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 		ret = clk_register(main_clks[k]);
 
-	if (!ret)
+	if (!ret) {
 		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+		if (!ret)
+			zclk_extend();
+	}
 
 	if (!ret)
 		ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:00:52 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:52 +0900
Subject: [PATCH 8/8] ARM: shmobile: sh73a0: div4 clocks must check the kick
 bit before changing rate
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-9-git-send-email-horms+renesas@verge.net.au>

From: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

According to the datasheet, it is not allowed to change div4 clock rates
if an earlier rate change operation is still in progress, as indicated by
a set kick bit.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-sh73a0.c |   24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index d05cf90..d9fd033 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -257,7 +257,7 @@ static struct clk twd_clk = {
 	.ops = &twd_clk_ops,
 };
 
-static struct sh_clk_ops zclk_ops;
+static struct sh_clk_ops zclk_ops, kicker_ops;
 static const struct sh_clk_ops *div4_clk_ops;
 
 static int zclk_set_rate(struct clk *clk, unsigned long rate)
@@ -324,18 +324,32 @@ static unsigned long zclk_recalc(struct clk *clk)
 	return clk_get_rate(clk->parent);
 }
 
-static void zclk_extend(void)
+static int kicker_set_rate(struct clk *clk, unsigned long rate)
 {
-	div4_clk_ops = div4_clks[DIV4_Z].ops;
+	if (__raw_readl(FRQCRB) & (1 << 31))
+		return -EBUSY;
+
+	return div4_clk_ops->set_rate(clk, rate);
+}
+
+static void div4_clk_extend(void)
+{
+	int i;
+
+	div4_clk_ops = div4_clks[0].ops;
 
+	/* Add a kicker-busy check before changing the rate */
+	kicker_ops = *div4_clk_ops;
 	/* We extend the DIV4 clock with a 1:1 pass-through case */
 	zclk_ops = *div4_clk_ops;
 
+	kicker_ops.set_rate = kicker_set_rate;
 	zclk_ops.set_rate = zclk_set_rate;
 	zclk_ops.round_rate = zclk_round_rate;
 	zclk_ops.recalc = zclk_recalc;
 
-	div4_clks[DIV4_Z].ops = &zclk_ops;
+	for (i = 0; i < DIV4_NR; i++)
+		div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
 }
 
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
@@ -697,7 +711,7 @@ void __init sh73a0_clock_init(void)
 	if (!ret) {
 		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 		if (!ret)
-			zclk_extend();
+			div4_clk_extend();
 	}
 
 	if (!ret)
-- 
1.7.10.4



From s.hauer at pengutronix.de  Mon May 27 05:01:35 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 May 2013 11:01:35 +0200
Subject: [PATCH v7 1/2] dma: imx-dma: Add oftree support
In-Reply-To: <1369562001-11494-2-git-send-email-mpa@pengutronix.de>
References: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
 <1369562001-11494-2-git-send-email-mpa@pengutronix.de>
Message-ID: <20130527090135.GJ32299@pengutronix.de>

On Sun, May 26, 2013 at 11:53:20AM +0200, Markus Pargmann wrote:
> Adding devicetree support for imx-dma driver. Use driver name for
> function 'imx_dma_is_general_purpose' because the devicename for
> devicetree initialized devices is different.
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> Reviewed-by: Shawn Guo <shawn.guo at linaro.org>

I haven't followed the DMA bindings discussion closely, so I can't say
much to this, but from my POV:

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon May 27 05:06:36 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 May 2013 11:06:36 +0200
Subject: [PATCH v6] video: imxfb: Add DT support
In-Reply-To: <1369564538-21835-1-git-send-email-mpa@pengutronix.de>
References: <1369564538-21835-1-git-send-email-mpa@pengutronix.de>
Message-ID: <20130527090636.GM32299@pengutronix.de>

On Sun, May 26, 2013 at 12:35:38PM +0200, Markus Pargmann wrote:
> Add devicetree support for imx framebuffer driver. It uses the generic
> display bindings and helper functions.
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From yamagata at plathome.co.jp  Mon May 27 05:10:18 2013
From: yamagata at plathome.co.jp (yamagata at plathome.co.jp)
Date: Mon, 27 May 2013 18:10:18 +0900 (JST)
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
In-Reply-To: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20130527.181018.461275386.yamagata@plathome.co.jp>

Dear Mr. Petazzoni

> The last patch finally adds support for the init button of the
> Plathome OpenBlocks A6 platform.

I have checked the init button worked well with your three patches for
linux-3.10-rc3 and 3.9.4.

Tested-by: Atsushi Yamagata <yamagata at plathome.co.jp>

BEGIN--------
root at obsa6:~# evtest /dev/input/event0
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "gpio_keys.2" 
Supported events:
  Event type 0 (EV_SYN)
  Event type 1 (EV_KEY)
    Event code 116 (KEY_POWER)
Properties:
Testing ... (interrupt to exit)
Event: time 1369641859.652847, type 1 (EV_KEY), code 116 (KEY_POWER), value 1
Event: time 1369641859.652847, -------------- SYN_REPORT ------------
Event: time 1369641859.992842, type 1 (EV_KEY), code 116 (KEY_POWER), value 0
Event: time 1369641859.992842, -------------- SYN_REPORT ------------
Event: time 1369641860.582840, type 1 (EV_KEY), code 116 (KEY_POWER), value 1
Event: time 1369641860.582840, -------------- SYN_REPORT ------------
Event: time 1369641860.862840, type 1 (EV_KEY), code 116 (KEY_POWER), value 0
Event: time 1369641860.862840, -------------- SYN_REPORT ------------
Event: time 1369641861.332838, type 1 (EV_KEY), code 116 (KEY_POWER), value 1
Event: time 1369641861.332838, -------------- SYN_REPORT ------------
Event: time 1369641861.592839, type 1 (EV_KEY), code 116 (KEY_POWER), value 0
Event: time 1369641861.592839, -------------- SYN_REPORT ------------
^C
root at obsa6:~#
END--------

Best regards

Atsushi Yamagata
--- Atsushi Yamagata


From R64188 at freescale.com  Mon May 27 05:12:25 2013
From: R64188 at freescale.com (Jin Zhengxiong-R64188)
Date: Mon, 27 May 2013 09:12:25 +0000
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <20130527055734.GD7782@S2101-09.ap.freescale.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
 <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
 <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>
 <20130523025059.GB2704@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3D5056@039-SN2MPN1-012.039d.mgd.msft.net>
 <20130527055734.GD7782@S2101-09.ap.freescale.net>
Message-ID: <13F8657A829DAB49A2A937FD6FC10F790B3D644B@039-SN2MPN1-012.039d.mgd.msft.net>

> -----Original Message-----
> From: Shawn Guo [mailto:shawn.guo at linaro.org]
> Sent: Monday, May 27, 2013 1:58 PM
> To: Jin Zhengxiong-R64188
> Cc: grant.likely at linaro.org; Lu Jingchang-B35083; linux-
> serial at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> gregkh at linuxfoundation.org; s.hauer at pengutronix.de
> Subject: Re: [PATCH v3] tty: serial: add Freescale lpuart driver support
> 
> On Mon, May 27, 2013 at 01:27:04AM +0000, Jin Zhengxiong-R64188 wrote:
> > By the way, we'll change the SoC name from mvf600 to vf610 to align the
> description in the document.
> >
> 
> Such product renaming in documents happen on IMX as well, but we do not
> bother to churn the source tree (file, function renaming) to catch up
> with it, as long as we know what it is.
> 
> For this mvf600 to vf610 renaming, if you want to catch up with it, you
> will need to rename a bunch of files functions, compatibles in
> Jingchang's series, and it's probably fine even though it's not really
> necessary since they haven't been merged.  But for those which have been
> merged, like fec compatible string, doing this will probably piss off
> maintainers.  So I would suggest that we stick to name mvf600 in the
> source tree, and just be aware of it's the equivalent of vf610.
> 
> Shawn
[Jason Jin-R64188] I think we need to align with the document as it's posted at Freescale website, otherwise, the inconsistency will confuse the customer. 
please refer to:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=1&sr=5
http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID
As the development work is ahead of the formal name posted outside, we continued to use the name for upstreaming patches. Sorry for taking into the confusion. For those patches aren't merged, please help to review them based on the new SoC name.

For the merged FEC patch, we'd like to explain it to the maintainer, Or can we just keep the FEC compatible string as before("fsl, mvf600-fec")? And be aware of it's the equivalent of "fsl,vf610-fec"?

Jason



From horms at verge.net.au  Mon May 27 05:16:42 2013
From: horms at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:16:42 +0900
Subject: [GIT PULL] Renesas ARM based sh7372 SoC updates for v3.11
In-Reply-To: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645242-3803-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130527091642.GC3911@verge.net.au>

On Mon, May 27, 2013 at 06:00:40PM +0900, Simon Horman wrote:
> Hi Arnd, Hi Olof,
> 
> The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> 
>   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-sh7372-for-v3.11
> 
> for you to fetch changes up to 98aaf628f866f530ce6829476e1c2ac98c9c4f60:
> 
>   ARM: shmobile: sh7372 pinmux platform device cleanup (2013-05-22 21:46:25 +0900)

Please ignore this, it duplicates a patch that I have sent a separate pull
request for.


From thomas.petazzoni at free-electrons.com  Mon May 27 05:19:01 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 27 May 2013 11:19:01 +0200
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
In-Reply-To: <20130527.181018.461275386.yamagata@plathome.co.jp>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130527.181018.461275386.yamagata@plathome.co.jp>
Message-ID: <20130527111901.73fba8bf@skate>

Hello,

On Mon, 27 May 2013 18:10:18 +0900 (JST), yamagata at plathome.co.jp wrote:
> Dear Mr. Petazzoni
> 
> > The last patch finally adds support for the init button of the
> > Plathome OpenBlocks A6 platform.
> 
> I have checked the init button worked well with your three patches for
> linux-3.10-rc3 and 3.9.4.
> 
> Tested-by: Atsushi Yamagata <yamagata at plathome.co.jp>

Thanks for your testing!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From davem at davemloft.net  Mon May 27 05:23:39 2013
From: davem at davemloft.net (David Miller)
Date: Mon, 27 May 2013 02:23:39 -0700 (PDT)
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address
 workaround on DT ethernet
In-Reply-To: <51A26B62.4050009@gmail.com>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130525.210441.818472895703230779.davem@davemloft.net>
 <51A26B62.4050009@gmail.com>
Message-ID: <20130527.022339.791886107453761860.davem@davemloft.net>

From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date: Sun, 26 May 2013 22:06:58 +0200

> good you mention it. I added Grant on Cc and will give a short
> sum-up why I casted the const from property->value away here.
> 
> Maybe I overlooked the API for modifying the DT property but as
> far as I've seen - there is no API for modifying it. And yes,
> you are right, it is kind of an abuse of DT here.

Sparc has an of_set_property(), it needs to become generic.


From horms+renesas at verge.net.au  Mon May 27 05:00:51 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:00:51 +0900
Subject: [PATCH 7/8] ARM: shmobile: sh73a0: do not overwrite all div4 clock
 operations
In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369645252-3847-8-git-send-email-horms+renesas@verge.net.au>

From: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU
frequency" intended to replace some clock operations only for the Z-clock,
instead it replaced them for all div4 clocks, since all div4 clocks share
the same copy of clock operations. Fix this by using a separate clock
operations structure for Z-clock.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-sh73a0.c |   28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index acb9e09..d05cf90 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -257,9 +257,8 @@ static struct clk twd_clk = {
 	.ops = &twd_clk_ops,
 };
 
-static int (*div4_set_rate)(struct clk *clk, unsigned long rate);
-static unsigned long (*div4_recalc)(struct clk *clk);
-static long (*div4_round_rate)(struct clk *clk, unsigned long rate);
+static struct sh_clk_ops zclk_ops;
+static const struct sh_clk_ops *div4_clk_ops;
 
 static int zclk_set_rate(struct clk *clk, unsigned long rate)
 {
@@ -275,7 +274,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate)
 		/* 1:1 - switch off divider */
 		__raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
 		/* nullify the divider to prepare for the next time */
-		ret = div4_set_rate(clk, rate / 2);
+		ret = div4_clk_ops->set_rate(clk, rate / 2);
 		if (!ret)
 			ret = frqcr_kick();
 		if (ret > 0)
@@ -290,7 +289,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate)
 			 * set the divider - call the DIV4 method, it will kick
 			 * FRQCRB too
 			 */
-			ret = div4_set_rate(clk, rate);
+			ret = div4_clk_ops->set_rate(clk, rate);
 		if (ret < 0)
 			goto esetrate;
 	}
@@ -302,7 +301,7 @@ esetrate:
 
 static long zclk_round_rate(struct clk *clk, unsigned long rate)
 {
-	unsigned long div_freq = div4_round_rate(clk, rate),
+	unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
 		parent_freq = clk_get_rate(clk->parent);
 
 	if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
@@ -317,7 +316,7 @@ static unsigned long zclk_recalc(struct clk *clk)
 	 * Must recalculate frequencies in case PLL0 has been changed, even if
 	 * the divisor is unused ATM!
 	 */
-	unsigned long div_freq = div4_recalc(clk);
+	unsigned long div_freq = div4_clk_ops->recalc(clk);
 
 	if (__raw_readl(FRQCRB) & (1 << 28))
 		return div_freq;
@@ -327,13 +326,16 @@ static unsigned long zclk_recalc(struct clk *clk)
 
 static void zclk_extend(void)
 {
+	div4_clk_ops = div4_clks[DIV4_Z].ops;
+
 	/* We extend the DIV4 clock with a 1:1 pass-through case */
-	div4_set_rate = div4_clks[DIV4_Z].ops->set_rate;
-	div4_round_rate = div4_clks[DIV4_Z].ops->round_rate;
-	div4_recalc = div4_clks[DIV4_Z].ops->recalc;
-	div4_clks[DIV4_Z].ops->set_rate = zclk_set_rate;
-	div4_clks[DIV4_Z].ops->round_rate = zclk_round_rate;
-	div4_clks[DIV4_Z].ops->recalc = zclk_recalc;
+	zclk_ops = *div4_clk_ops;
+
+	zclk_ops.set_rate = zclk_set_rate;
+	zclk_ops.round_rate = zclk_round_rate;
+	zclk_ops.recalc = zclk_recalc;
+
+	div4_clks[DIV4_Z].ops = &zclk_ops;
 }
 
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
-- 
1.7.10.4



From benh at au1.ibm.com  Mon May 27 05:38:31 2013
From: benh at au1.ibm.com (Benjamin Herrenschmidt)
Date: Mon, 27 May 2013 19:38:31 +1000
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <51A26B62.4050009@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130525.210441.818472895703230779.davem@davemloft.net>
 <51A26B62.4050009@gmail.com>
Message-ID: <1369647511.3557.27.camel@pasglop>

On Sun, 2013-05-26 at 22:06 +0200, Sebastian Hesselbarth wrote:

> good you mention it. I added Grant on Cc and will give a short
> sum-up why I casted the const from property->value away here.
> 
> Maybe I overlooked the API for modifying the DT property but as
> far as I've seen - there is no API for modifying it. And yes,
> you are right, it is kind of an abuse of DT here.

of_update_property(). That also makes sure that any notifiers
is called and proc/device-tree is updated in the case where the property
is new.

> As Kirkwoods loose their MAC address on clock gating, I was looking
> for a place to store it early. (a) DT property "local-mac-address"
> looked as a good place as it will allow the driver to find it without
> any extra code. Of course, I am doing severaly sanity checks if it is
> safe to overwrite it, i.e. no other MAC set, property is there, long
> enough.
> 
> If Grant also NACKs modifying the DT we basically have two more options
> left for Kirkwood: (b) have MAC stored early in two global arrays in
> board init and reference that from mv643xx_eth or (c) leave the clock
> ungated unconditionally on all Kirkwoods.
> 
> I can live with all three, just name it and I prepare a final patch set.

No, putting it in the DT makes sense, just use the right accessor.

Cheers,
Ben.

> Sebastian
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/




From benh at kernel.crashing.org  Mon May 27 05:39:25 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Mon, 27 May 2013 19:39:25 +1000
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <20130527.022339.791886107453761860.davem@davemloft.net>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130525.210441.818472895703230779.davem@davemloft.net>
 <51A26B62.4050009@gmail.com>
 <20130527.022339.791886107453761860.davem@davemloft.net>
Message-ID: <1369647565.3557.28.camel@pasglop>

On Mon, 2013-05-27 at 02:23 -0700, David Miller wrote:
> Sparc has an of_set_property(), it needs to become generic.

There is an of_update_property(), we could change the name though, yours
is nicer :-)

Cheers,
Ben.




From josh.wu at atmel.com  Mon May 27 05:56:34 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Mon, 27 May 2013 17:56:34 +0800
Subject: [PATCH v2 2/4] mtd: atmel_nand: add Nand Flash Controller (NFC)
 support
In-Reply-To: <20130524200947.GM24476@game.jcrosoft.org>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-3-git-send-email-josh.wu@atmel.com>
 <20130524200947.GM24476@game.jcrosoft.org>
Message-ID: <51A32DD2.9040707@atmel.com>

Hi, Jean-Christophe PLAGNIOL-VILLARD

Thank you for your review comments. See my comment in below.

On 5/25/2013 4:09 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:51 Fri 17 May     , Josh Wu wrote:
>> Nand Flash Controller (NFC) can handle automatic transfers, sending the
>> commands and address cycles to the NAND Flash.
>>
>> To use NFC in this driver, the user needs to set the address and size of
>> NFC command registers, NFC registers (embedded in HSMC) and NFC SRAM in dts.
>> Also user need to set up the HSMC irq, which use to check whether nfc
>> command is finish or not.
>>
>> This driver has been tested on SAMA5D3X-EK board with JFFS2, YAFFS,
>> UBIFS and mtd-utils.
>>
>> I put the part of the mtd_speedtest result here for your information.
>>  From the mtd_speedtest, we can see the NFC will reduce the %50 of cpu load
>> when writing nand flash. No change when reading.
>> In the meantime, the speed will be slow about %8.
>>
>> - commands use to test:
>>      #insmod /mnt/mtd_speedtest.ko dev=2 &
>>      #top -n 30 -d 1 | grep speedtest
>>
>> - test result:
>>
>> Before the patch:
>> =================================================
>> mtd_speedtest: MTD device: 2
>> mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
>>    515   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  99% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: eraseblock write speed is 5768 KiB/s
>> mtd_speedtest: testing eraseblock read speed
>>    515   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: eraseblock read speed is 5932 KiB/s
>> mtd_speedtest: testing page write speed
>>    515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: page write speed is 5770 KiB/s
>> mtd_speedtest: testing page read speed
>>    515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
>>    515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: page read speed is 5910 KiB/s
>>
>> After the patch:
>> =================================================
>> mtd_speedtest: MTD device: 2
>> mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
>> mtd_speedtest: testing eraseblock write speed
>>    509   495 root     D     1164   0%  49% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: eraseblock write speed is 5370 KiB/s
>> mtd_speedtest: testing eraseblock read speed
>>    509   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     R     1164   0%  95% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: eraseblock read speed is 5715 KiB/s
>> mtd_speedtest: testing page write speed
>>    509   495 root     D     1164   0%  48% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: page write speed is 5224 KiB/s
>> mtd_speedtest: testing page read speed
>>    509   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: page read speed is 5641 KiB/s
>>
>> Signed-off-by: Josh Wu <josh.wu at atmel.com>
>> ---
>> v1 --> v2:
>>    remove the useless nand commands: NAND_CMD_STATUS_ERRORx, NAND_CMD_DEPLETE1.
>>
>>   .../devicetree/bindings/mtd/atmel-nand.txt         |    3 +
>>   drivers/mtd/nand/atmel_nand.c                      |  373 ++++++++++++++++++--
>>   drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++++
>>   3 files changed, 454 insertions(+), 28 deletions(-)
>>   create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
>> index d555421..88e3313 100644
>> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
>> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
>> @@ -6,6 +6,8 @@ Required properties:
>>   	and hardware ECC controller if available.
>>   	If the hardware ECC is PMECC, it should contain address and size for
>>   	PMECC, PMECC Error Location controller and ROM which has lookup tables.
>> +	If hardware supports Nand Flash Controller, it should contain address and
>> +	size for NFC command registers, NFC registers and NFC Sram.
>>   - atmel,nand-addr-offset : offset for the address latch.
>>   - atmel,nand-cmd-offset : offset for the command latch.
>>   - #address-cells, #size-cells : Must be present if the device has sub-nodes
>> @@ -29,6 +31,7 @@ Optional properties:
>>     sector size 1024.
>>   - nand-bus-width : 8 or 16 bus width if not present 8
>>   - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
>> +- atmel,has-nfc: boolean to enable Nand Flash Controller(NFC).
> yes but you need to update the compatible or check the IP support it too
> as has-nfc will mean I have the nfs on the hardware but not enable it
>
> the SoC dtsi will describe you have it but the board will decide to enable it or
> not

I can add some code to check whether is NFC supported by read SMC IP 
version. But I'm afraid
such code may not work for AVR arch.

Another way is just add a 'enable-nfc' compatible string. Which is for 
board to enable the NFC feature.

I'm prefer to the later one. What do you think?

>>   
>>   Examples:
>>   nand0: nand at 40000000,0 {
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index f747791..48d7ee6 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -18,6 +18,9 @@
>>    *  Add Programmable Multibit ECC support for various AT91 SoC
>>    *     ? Copyright 2012 ATMEL, Hong Xu
>>    *
>> + *  Add Nand Flash Controller support for SAMA5 SoC
>> + *     ? Copyright 2013 ATMEL, Josh Wu (josh.wu at atmel.com)
>> + *
>>    * This program is free software; you can redistribute it and/or modify
>>    * it under the terms of the GNU General Public License version 2 as
>>    * published by the Free Software Foundation.
>> @@ -37,9 +40,11 @@
>>   #include <linux/mtd/nand.h>
>>   #include <linux/mtd/partitions.h>
>>   
>> +#include <linux/delay.h>
>>   #include <linux/dmaengine.h>
>>   #include <linux/gpio.h>
>>   #include <linux/io.h>
>> +#include <linux/interrupt.h>
>>   #include <linux/platform_data/atmel.h>
>>   #include <linux/pinctrl/consumer.h>
>>   
>> @@ -58,6 +63,7 @@ module_param(on_flash_bbt, int, 0);
>>   	__raw_writel((value), add + ATMEL_ECC_##reg)
>>   
>>   #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
>> +#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
>>   
>>   /* oob layout for large page size
>>    * bad block info is on bytes 0 and 1
>> @@ -85,6 +91,13 @@ static struct nand_ecclayout atmel_oobinfo_small = {
>>   	},
>>   };
>>   
>> +struct atmel_nfc {
>> +	void __iomem		*base_cmd_regs;
>> +	void __iomem		*hsmc_regs;
>> +	void __iomem		*sram_bank0;
>> +	dma_addr_t		sram_bank0_phys;
>> +};
>> +
>>   struct atmel_nand_host {
>>   	struct nand_chip	nand_chip;
>>   	struct mtd_info		mtd;
>> @@ -93,10 +106,15 @@ struct atmel_nand_host {
>>   	struct atmel_nand_data	board;
>>   	struct device		*dev;
>>   	void __iomem		*ecc;
>> +	int			irq;
>>   
>>   	struct completion	comp;
>>   	struct dma_chan		*dma_chan;
>>   
>> +	bool			has_nfc;
>> +	struct atmel_nfc	nfc;
>> +	struct completion	comp_nfc;
>> +
>>   	bool			has_pmecc;
>>   	u8			pmecc_corr_cap;
>>   	u16			pmecc_sector_size;
>> @@ -1357,6 +1375,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
>>   	board->det_pin = of_get_gpio(np, 2);
>>   
>>   	host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
>> +	host->has_nfc = of_property_read_bool(np, "atmel,has-nfc");
>>   
>>   	if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
>>   		return 0;	/* Not using PMECC */
>> @@ -1469,6 +1488,275 @@ static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
>>   	return 0;
>>   }
>>   
>> +/* SMC interrupt service routine */
>> +static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
>> +{
>> +	struct atmel_nand_host *host = dev_id;
>> +	u32 status, mask, pending;
>> +	irqreturn_t ret = IRQ_NONE;
>> +
>> +	status = nfc_readl(host->nfc.hsmc_regs, SR);
>> +	mask = nfc_readl(host->nfc.hsmc_regs, IMR);
>> +	pending = status & mask;
>> +
>> +	if (pending & ATMEL_HSMC_NFC_XFR_DONE) {
>> +		complete(&host->comp_nfc);
>> +		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_XFR_DONE);
>> +		ret = IRQ_HANDLED;
>> +	} else if (pending & ATMEL_HSMC_NFC_RB_EDGE) {
>> +		complete(&host->comp_nfc);
>> +		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_RB_EDGE);
>> +		ret = IRQ_HANDLED;
>> +	} else if (pending & ATMEL_HSMC_NFC_CMD_DONE) {
>> +		complete(&host->comp_nfc);
>> +		nfc_writel(host->nfc.hsmc_regs, IDR, ATMEL_HSMC_NFC_CMD_DONE);
>> +		ret = IRQ_HANDLED;
>> +	}
> 	put esle ret = IRQ_NONE less code

right, I will do it in next version.

>> +
>> +	return ret;
>> +}
>> +
>> +/* NFC(Nand Flash Controller) related functions */
>> +static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
>> +{
>> +	unsigned long timeout;
>> +	init_completion(&host->comp_nfc);
>> +
>> +	/* Enable interrupt that need to wait for */
>> +	nfc_writel(host->nfc.hsmc_regs, IER, flag);
>> +
>> +	timeout = wait_for_completion_timeout(&host->comp_nfc,
>> +			msecs_to_jiffies(NFC_TIME_OUT_MS));
>> +	if (timeout)
>> +		return 0;
>> +
>> +	/* Time out to wait for the interrupt */
>> +	dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
>> +	return -ETIMEDOUT;
>> +}
>> +
>> +static int nfc_send_command(struct atmel_nand_host *host,
>> +	unsigned int cmd, unsigned int addr, unsigned char cycle0)
>> +{
>> +	unsigned long timeout;
>> +	dev_dbg(host->dev,
>> +		"nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
>> +		cmd, addr, cycle0);
>> +
>> +	timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
>> +	while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc.base_cmd_regs)
>> +			& NFCADDR_CMD_NFCBUSY) {
>> +		if (time_after(jiffies, timeout)) {
>> +			dev_err(host->dev,
>> +				"Time out to wait CMD_NFCBUSY ready!\n");
>> +			break;
> 			already timeout you still neeed to wait DONE?

ok. I will return timeout error in this case.

>> +		}
>> +	}
>> +	nfc_writel(host->nfc.hsmc_regs, CYCLE0, cycle0);
>> +	nfc_cmd_addr1234_writel(cmd, addr, host->nfc.base_cmd_regs);
>> +	return nfc_wait_interrupt(host, ATMEL_HSMC_NFC_CMD_DONE);
>> +}
>> +
>> +static int nfc_device_ready(struct mtd_info *mtd)
>> +{
>> +	struct nand_chip *nand_chip = mtd->priv;
>> +	struct atmel_nand_host *host = nand_chip->priv;
>> +	if (!nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE))
>> +		return 1;
>> +	return 0;
>> +}
>> +
>> +static void nfc_select_chip(struct mtd_info *mtd, int chip)
>> +{
>> +	struct nand_chip *nand_chip = mtd->priv;
>> +	struct atmel_nand_host *host = nand_chip->priv;
>> +
>> +	if (chip == -1)
>> +		nfc_writel(host->nfc.hsmc_regs, CTRL, ATMEL_HSMC_NFC_DISABLE);
>> +	else
>> +		nfc_writel(host->nfc.hsmc_regs, CTRL, ATMEL_HSMC_NFC_ENABLE);
>> +}
>> +
>> +static int nfc_init(struct platform_device *pdev, struct mtd_info *mtd)
>> +{
>> +	struct nand_chip *nand_chip = mtd->priv;
>> +	struct atmel_nand_host *host = nand_chip->priv;
>> +	struct atmel_nfc *nfc = &host->nfc;
>> +	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
>> +
>> +	nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 4);
>> +	if (!nfc_cmd_regs)
>> +		return -EINVAL;
>> +
>> +	nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 5);
>> +	if (!nfc_hsmc_regs)
>> +		return -EINVAL;
>> +
>> +	nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 6);
>> +	if (!nfc_sram)
>> +		return -EINVAL;
>> +
>> +	nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
>> +	if (IS_ERR(nfc->base_cmd_regs))
>> +		return PTR_ERR(nfc->base_cmd_regs);
>> +
>> +	nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
>> +	if (IS_ERR(nfc->hsmc_regs))
>> +		return PTR_ERR(nfc->hsmc_regs);
>> +
>> +	nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
>> +	if (IS_ERR(nfc->sram_bank0))
>> +		return PTR_ERR(nfc->sram_bank0);
>> +
>> +	nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
>> +
>> +	dev_info(host->dev, "Using NFC\n");
>> +	return 0;
>> +}
>> +
>> +static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
>> +		unsigned int *addr1234, unsigned int *cycle0)
>> +{
>> +	struct nand_chip *chip = mtd->priv;
>> +
>> +	int acycle = 0;
>> +	unsigned char addr_bytes[8];
>> +	int index = 0, bit_shift;
>> +
>> +	BUG_ON(addr1234 == NULL || cycle0 == NULL);
>> +
>> +	*cycle0 = 0;
>> +	*addr1234 = 0;
>> +
>> +	if (column != -1) {
>> +		if (chip->options & NAND_BUSWIDTH_16)
>> +			column >>= 1;
>> +		addr_bytes[acycle++] = column & 0xff;
>> +		if (mtd->writesize > 512)
>> +			addr_bytes[acycle++] = (column >> 8) & 0xff;
>> +	}
>> +
>> +	if (page_addr != -1) {
>> +		addr_bytes[acycle++] = page_addr & 0xff;
>> +		addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
>> +		if (chip->chipsize > (128 << 20))
>> +			addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
>> +	}
>> +
>> +	if (acycle > 4)
>> +		*cycle0 = addr_bytes[index++];
>> +
>> +	for (bit_shift = 0; index < acycle; bit_shift += 8)
>> +		*addr1234 += addr_bytes[index++] << bit_shift;
>> +
>> +	return acycle << 19;	/* return acycle in cmd register */
>> +}
>> +
>> +static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>> +				int column, int page_addr)
>> +{
>> +	struct nand_chip *chip = mtd->priv;
>> +	struct atmel_nand_host *host = chip->priv;
>> +	unsigned long timeout;
>> +	unsigned int nfc_addr_cmd = 0;
>> +
>> +	unsigned int cmd1 = command << 2;
>> +
>> +	/* Set default settings: no cmd2, no addr cycle. read from nand */
>> +	unsigned int cmd2 = 0;
>> +	unsigned int vcmd2 = 0;
>> +	int acycle = NFCADDR_CMD_ACYCLE_NONE;
>> +	int csid = NFCADDR_CMD_CSID_3;
>> +	int dataen = NFCADDR_CMD_DATADIS;
>> +	int nfcwr = NFCADDR_CMD_NFCRD;
>> +	unsigned int addr1234 = 0;
>> +	unsigned int cycle0 = 0;
>> +	bool do_addr = true;
>> +
>> +	dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
>> +	     __func__, command, column, page_addr);
>> +
>> +	switch (command) {
>> +	case NAND_CMD_RESET:
>> +		nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
>> +		nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
>> +		udelay(chip->chip_delay);
>> +
>> +		nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
>> +		timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
>> +		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
>> +			if (time_after(jiffies, timeout)) {
>> +				dev_err(host->dev,
>> +					"Time out to wait status ready!\n");
>> +				break;
>> +			}
>> +		}
>> +		return;
>> +	case NAND_CMD_STATUS:
>> +		do_addr = false;
>> +		break;
>> +	case NAND_CMD_PARAM:
>> +	case NAND_CMD_READID:
>> +		do_addr = false;
>> +		acycle = NFCADDR_CMD_ACYCLE_1;
>> +		if (column != -1)
>> +			addr1234 = column;
>> +		break;
>> +	case NAND_CMD_RNDOUT:
>> +		cmd2 = NAND_CMD_RNDOUTSTART << 10;
>> +		vcmd2 = NFCADDR_CMD_VCMD2;
>> +		break;
>> +	case NAND_CMD_READ0:
>> +	case NAND_CMD_READOOB:
>> +		if (command == NAND_CMD_READOOB) {
>> +			column += mtd->writesize;
>> +			command = NAND_CMD_READ0; /* only READ0 is valid */
>> +			cmd1 = command << 2;
>> +		}
>> +
>> +		cmd2 = NAND_CMD_READSTART << 10;
>> +		vcmd2 = NFCADDR_CMD_VCMD2;
>> +		break;
>> +	/* For prgramming command, the cmd need set to write enable */
>> +	case NAND_CMD_PAGEPROG:
>> +	case NAND_CMD_SEQIN:
>> +	case NAND_CMD_RNDIN:
>> +		nfcwr = NFCADDR_CMD_NFCWR;
>> +		break;
>> +	default:
>> +		break;
>> +	}
>> +
>> +	if (do_addr)
>> +		acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
>> +				&cycle0);
>> +
>> +	nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
>> +	nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
>> +
>> +	/*
>> +	 * Program and erase have their own busy handlers status, sequential
>> +	 * in, and deplete1 need no delay.
>> +	 */
>> +	switch (command) {
>> +	case NAND_CMD_CACHEDPROG:
>> +	case NAND_CMD_PAGEPROG:
>> +	case NAND_CMD_ERASE1:
>> +	case NAND_CMD_ERASE2:
>> +	case NAND_CMD_RNDIN:
>> +	case NAND_CMD_STATUS:
>> +	case NAND_CMD_RNDOUT:
>> +	case NAND_CMD_SEQIN:
>> +	case NAND_CMD_READID:
>> +		return;
>> +
>> +	case NAND_CMD_READ0:
>> +		/* fall through */
>> +	default:
>> +		nfc_wait_interrupt(host, ATMEL_HSMC_NFC_RB_EDGE);
>> +	}
>> +}
>> +
>>   /*
>>    * Probe for the NAND device.
>>    */
>> @@ -1479,7 +1767,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>>   	struct nand_chip *nand_chip;
>>   	struct resource *mem;
>>   	struct mtd_part_parser_data ppdata = {};
>> -	int res;
>> +	int res, irq;
>>   	struct pinctrl *pinctrl;
>>   
>>   	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> @@ -1523,7 +1811,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>>   	/* Set address of NAND IO lines */
>>   	nand_chip->IO_ADDR_R = host->io_base;
>>   	nand_chip->IO_ADDR_W = host->io_base;
>> -	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
>>   
>>   	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
>>   	if (IS_ERR(pinctrl)) {
>> @@ -1532,41 +1819,69 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>>   		goto err_ecc_ioremap;
>>   	}
>>   
>> -	if (gpio_is_valid(host->board.rdy_pin)) {
>> -		res = gpio_request(host->board.rdy_pin, "nand_rdy");
>> -		if (res < 0) {
>> -			dev_err(&pdev->dev,
>> -				"can't request rdy gpio %d\n",
>> -				host->board.rdy_pin);
>> +	if (host->has_nfc) {
> 		split in 2 function
>
> 		nfs_init

ok. I will add a function to do this.

>> +		res = nfc_init(pdev, mtd);
>> +		if (res)
>> +			goto err_ecc_ioremap;
>> +		nand_chip->select_chip = nfc_select_chip;
>> +		nand_chip->dev_ready = nfc_device_ready;
>> +		nand_chip->cmdfunc = nfc_nand_command;
>> +
>> +		/* Initialize the interrupt for NFC */
>> +		irq = platform_get_irq(pdev, 0);
>> +		if (irq < 0) {
>> +			dev_err(host->dev, "Cannot get HSMC irq!\n");
>>   			goto err_ecc_ioremap;
>>   		}
>>   
>> -		res = gpio_direction_input(host->board.rdy_pin);
>> -		if (res < 0) {
>> -			dev_err(&pdev->dev,
>> -				"can't request input direction rdy gpio %d\n",
>> -				host->board.rdy_pin);
>> +		res = request_irq(irq, hsmc_interrupt, 0, "hsmc", host);
> 		devm_request_irq

thank you to catch that. I'll fix it.

>> +		if (res) {
>> +			dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
>> +				irq);
>>   			goto err_ecc_ioremap;
>>   		}
>>   
>> -		nand_chip->dev_ready = atmel_nand_device_ready;
>> -	}
>> +		host->irq = irq;
>> +	} else {
> 		rest

I can't get this point.

>> +		nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
>> +
>> +		if (gpio_is_valid(host->board.rdy_pin)) {
>> +			res = gpio_request(host->board.rdy_pin, "nand_rdy");
>> +			if (res < 0) {
>> +				dev_err(&pdev->dev,
>> +					"can't request rdy gpio %d\n",
>> +					host->board.rdy_pin);
>> +				goto err_ecc_ioremap;
>> +			}
>>   
>> -	if (gpio_is_valid(host->board.enable_pin)) {
>> -		res = gpio_request(host->board.enable_pin, "nand_enable");
>> -		if (res < 0) {
>> -			dev_err(&pdev->dev,
>> -				"can't request enable gpio %d\n",
>> -				host->board.enable_pin);
>> -			goto err_ecc_ioremap;
>> +			res = gpio_direction_input(host->board.rdy_pin);
>> +			if (res < 0) {
>> +				dev_err(&pdev->dev,
>> +					"can't request input direction rdy gpio %d\n",
>> +					host->board.rdy_pin);
>> +				goto err_ecc_ioremap;
>> +			}
>> +
>> +			nand_chip->dev_ready = atmel_nand_device_ready;
>>   		}
>>   
>> -		res = gpio_direction_output(host->board.enable_pin, 1);
>> -		if (res < 0) {
>> -			dev_err(&pdev->dev,
>> -				"can't request output direction enable gpio %d\n",
>> -				host->board.enable_pin);
>> -			goto err_ecc_ioremap;
>> +		if (gpio_is_valid(host->board.enable_pin)) {
>> +			res = gpio_request(host->board.enable_pin,
> we need to use devm_ here too
> and everywhere we can in this driver

yes, but seems you already sent one patch to use devm_ for this driver.
https://patchwork.kernel.org/patch/1589071/
It is not merged in at91 tree yet.

So what do you think if I put that patch rebased and put it as one of 
this NFC series patches?

>> +				"nand_enable");
>> +			if (res < 0) {
>> +				dev_err(&pdev->dev,
>> +					"can't request enable gpio %d\n",
>> +					host->board.enable_pin);
>> +				goto err_ecc_ioremap;
>> +			}
>> +
>> +			res = gpio_direction_output(host->board.enable_pin, 1);
>> +			if (res < 0) {
>> +				dev_err(&pdev->dev,
>> +					"can't request output direction enable gpio %d\n",
>> +					host->board.enable_pin);
>> +				goto err_ecc_ioremap;
>> +			}
>>   		}
>>   	}
>>   
>> @@ -1682,6 +1997,8 @@ err_ecc_ioremap:
>>   	iounmap(host->io_base);
>>   err_nand_ioremap:
>>   	kfree(host);
>> +	if (host->irq)
>> +		free_irq(host->irq, host);
>>   	return res;
>>   }
>>   
>> diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
>> new file mode 100644
>> index 0000000..ca124de
>> --- /dev/null
>> +++ b/drivers/mtd/nand/atmel_nand_nfc.h
>> @@ -0,0 +1,106 @@
>> +/*
>> + * Atmel Nand Flash Controller (NFC) - System peripherals regsters.
>> + * Based on SAMA5D3 datasheet.
>> + *
>> + * ? Copyright 2013 Atmel Corporation.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +
>> +#ifndef ATMEL_NAND_NFC_H
>> +#define ATMEL_NAND_NFC_H
>> +
>> +/*
>> + * HSMC NFC registers
>> + */
>> +#define ATMEL_HSMC_NFC_CFG		0x00	/* NFC Configuration Register */
>> +#define		ATMEL_HSMC_PAGESIZE_512		(0)
>> +#define		ATMEL_HSMC_PAGESIZE_1024	(1)
>> +#define		ATMEL_HSMC_PAGESIZE_2048	(2)
>> +#define		ATMEL_HSMC_PAGESIZE_4096	(3)
>> +#define		ATMEL_HSMC_PAGESIZE_8192	(4)
> 	keep the << 0

ok. i'll fix it.

>> +#define		ATMEL_HSMC_WSPARE		(1 << 8)
>> +#define		ATMEL_HSMC_RSPARE		(1 << 9)
>> +#define		ATMEL_HSMC_EDGE_CTRL_RISING	(0 << 12)
>> +#define		ATMEL_HSMC_EDGE_CTRL_FALLING	(1 << 12)
>> +#define		ATMEL_HSMC_RBEDGE		(1 << 13)
>> +#define		ATMEL_HSMC_NFC_DTOCYC		(0xf << 16)
>> +#define		ATMEL_HSMC_NFC_DTOMUL		(0x7 << 20)
>> +#define		ATMEL_HSMC_NFC_SPARESIZE	(0x7f << 24)
>> +
>> +#define ATMEL_HSMC_NFC_CTRL		0x04	/* NFC Control Register */
>> +#define		ATMEL_HSMC_NFC_ENABLE		(1 << 0)
>> +#define		ATMEL_HSMC_NFC_DISABLE		(1 << 1)
>> +
>> +#define ATMEL_HSMC_NFC_SR		0x08	/* NFC Status Register */
>> +#define		ATMEL_HSMC_NFC_STATUS		(1 << 0)
>> +#define		ATMEL_HSMC_NFC_RB_RISE		(1 << 4)
>> +#define		ATMEL_HSMC_NFC_RB_FALL		(1 << 5)
>> +#define		ATMEL_HSMC_NFC_BUSY		(1 << 8)
>> +#define		ATMEL_HSMC_NFC_WR		(1 << 11)
>> +#define		ATMEL_HSMC_NFC_CSID		(7 << 12)
>> +#define		ATMEL_HSMC_NFC_XFR_DONE		(1 << 16)
>> +#define		ATMEL_HSMC_NFC_CMD_DONE		(1 << 17)
>> +#define		ATMEL_HSMC_NFC_DTOE		(1 << 20)
>> +#define		ATMEL_HSMC_NFC_UNDEF		(1 << 21)
>> +#define		ATMEL_HSMC_NFC_AWB		(1 << 22)
>> +#define		ATMEL_HSMC_NFC_ASE		(1 << 23)
>> +#define		ATMEL_HSMC_NFC_RB_EDGE		(1 << 24)
>> +
>> +#define ATMEL_HSMC_NFC_IER		0x0c
>> +#define ATMEL_HSMC_NFC_IDR		0x10
>> +#define ATMEL_HSMC_NFC_IMR		0x14
>> +#define ATMEL_HSMC_NFC_CYCLE0		0x18	/* NFC Address Cycle Zero */
>> +#define		ATMEL_HSMC_NFC_ADDR_CYCLE0	(0xff)
>> +
>> +#define ATMEL_HSMC_NFC_BANK		0x1c	/* NFC Bank Register */
>> +#define		ATMEL_HSMC_NFC_BANK0	(0 << 0)
>> +#define		ATMEL_HSMC_NFC_BANK1	(1 << 0)
>> +#define		NFC_SRAM_BANK_OFFSET	(0x1200)
>> +
>> +#define nfc_writel(addr, reg, value) \
>> +	writel((value), (addr) + ATMEL_HSMC_NFC_##reg)
>> +
>> +#define nfc_readl(addr, reg) \
>> +	readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
>> +
>> +/*
>> + * NFC Address Command definitions
>> + */
>> +#define NFCADDR_CMD_CMD1	(0xff << 2)	/* Command for Cycle 1 */
>> +#define NFCADDR_CMD_CMD2	(0xff << 10)	/* Command for Cycle 2 */
>> +#define NFCADDR_CMD_VCMD2	(0x1 << 18)	/* Valid Cycle 2 Command */
>> +#define NFCADDR_CMD_ACYCLE	(0x7 << 19)	/* Number of Address required */
>> +#define   NFCADDR_CMD_ACYCLE_NONE	(0x0 << 19)
>> +#define   NFCADDR_CMD_ACYCLE_1		(0x1 << 19)
>> +#define   NFCADDR_CMD_ACYCLE_2		(0x2 << 19)
>> +#define   NFCADDR_CMD_ACYCLE_3		(0x3 << 19)
>> +#define   NFCADDR_CMD_ACYCLE_4		(0x4 << 19)
>> +#define   NFCADDR_CMD_ACYCLE_5		(0x5 << 19)
>> +#define NFCADDR_CMD_CSID	(0x7 << 22)	/* Chip Select Identifier */
>> +#define   NFCADDR_CMD_CSID_0		(0x0 << 22)
>> +#define   NFCADDR_CMD_CSID_1		(0x1 << 22)
>> +#define   NFCADDR_CMD_CSID_2		(0x2 << 22)
>> +#define   NFCADDR_CMD_CSID_3		(0x3 << 22)
>> +#define   NFCADDR_CMD_CSID_4		(0x4 << 22)
>> +#define   NFCADDR_CMD_CSID_5		(0x5 << 22)
>> +#define   NFCADDR_CMD_CSID_6		(0x6 << 22)
>> +#define   NFCADDR_CMD_CSID_7		(0x7 << 22)
>> +#define NFCADDR_CMD_DATAEN	(0x1 << 25)	/* Data Transfer Enable */
>> +#define NFCADDR_CMD_DATADIS	(0x0 << 25)	/* Data Transfer Disable */
>> +#define NFCADDR_CMD_NFCRD	(0x0 << 26)	/* NFC Read Enable */
>> +#define NFCADDR_CMD_NFCWR	(0x1 << 26)	/* NFC Write Enable */
>> +#define NFCADDR_CMD_NFCBUSY	(0x1 << 27)	/* NFC Busy */
>> +
>> +#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \
>> +	writel((addr1234), (cmd) + nfc_base)
>> +
>> +#define nfc_cmd_readl(bitstatus, nfc_base) \
>> +	readl_relaxed((bitstatus) + nfc_base)
>> +
>> +#define NFC_TIME_OUT_MS		100
>> +
>> +#endif
>> -- 
>> 1.7.9.5
>>

Best Regards,
Josh Wu


From horms+renesas at verge.net.au  Mon May 27 05:59:25 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:25 +0900
Subject: [PATCH 1/9] ARM: shmobile: use do{ }while() on SH_CLK_SET_RATIO()
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-2-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

SH_CLK_SET_RATIO() will be trouble without this patch

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/clock.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac612..ce29720 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -31,9 +31,9 @@ static SH_FIXED_RATIO_CLKg(name, p, r);
 	SH_FIXED_RATIO_CLK(name, p, name);
 
 #define SH_CLK_SET_RATIO(p, m, d)	\
-{			\
+do {			\
 	(p)->mul = m;	\
 	(p)->div = d;	\
-}
+} while (0)
 
 #endif
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:28 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:28 +0900
Subject: [PATCH 4/9] ARM: shmobile: r8a7778: fix Ether device name
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-5-git-send-email-horms+renesas@verge.net.au>

From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

While recasting the commit "ARM: shmobile: R8A7778: add Ether support", I made a
typo in the platform device's name: used underscore instead of hyphen.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7778.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index d6ee521..45f0e45 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -96,7 +96,7 @@ static struct resource ether_resources[] = {
 
 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
 {
-	platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+	platform_device_register_resndata(&platform_bus, "sh-eth", -1,
 					  ether_resources,
 					  ARRAY_SIZE(ether_resources),
 					  pdata, sizeof(*pdata));
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:26 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:26 +0900
Subject: [PATCH 2/9] ARM: shmobile: add GPIO IRQ macro
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-3-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

R-Car series gpio_rcar driver can control GPIO IRQ today.
It needs base IRQ number for gpio_rcar_config :: .irq_base
This patch adds macro for GPIO IRQ.
This patch was tested on Bock-W board

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/irqs.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2..d241bfd 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE		2000
 #define irq_pin(nr)		((nr) + IRQPIN_BASE)
 
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE		2500
+#define GPIO_IRQ_BASE(x)	(_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)		(_GPIO_IRQ_BASE + (32 * x) + y)
+
 #endif /* __ASM_MACH_IRQS_H */
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:24 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:24 +0900
Subject: [GIT PULL] Renesas ARM based r8a7778 SoC updates for v3.11
Message-ID: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a7778-for-v3.11

for you to fetch changes up to 35019d7f4aba4c4ccece584b872a8ebcdd62e6fa:

  ARM: shmobile: r8a7778: correct model name in Kconfig (2013-05-27 18:22:42 +0900)

----------------------------------------------------------------
Renesas ARM based sh7778 SoC updates for v3.11

* Correction of model name in Kconfig by Sergei Shtylyov
* Registration of SDHI and PFC devices by Kuninori Morimoto
* Extended clock coverage by Kuninori Morimoto
* Correction of ethernet device's platform driver name by Sergei Shtylyov

----------------------------------------------------------------
Kuninori Morimoto (7):
      ARM: shmobile: use do{ }while() on SH_CLK_SET_RATIO()
      ARM: shmobile: add GPIO IRQ macro
      ARM: shmobile: r8a7778: fixup Ether setup code position
      ARM: shmobile: r8a7778: use fixed ratio clock
      ARM: shmobile: r8a7778: Register PFC device
      ARM: shmobile: r8a7778: add SDHI clock support
      ARM: shmobile: r8a7778: Register SDHI device

Sergei Shtylyov (2):
      ARM: shmobile: r8a7778: fix Ether device name
      ARM: shmobile: r8a7778: correct model name in Kconfig

 arch/arm/mach-shmobile/Kconfig                |    3 +-
 arch/arm/mach-shmobile/clock-r8a7778.c        |  156 ++++++++++++++++++++++---
 arch/arm/mach-shmobile/include/mach/clock.h   |    4 +-
 arch/arm/mach-shmobile/include/mach/irqs.h    |    5 +
 arch/arm/mach-shmobile/include/mach/r8a7778.h |    3 +
 arch/arm/mach-shmobile/setup-r8a7778.c        |   65 ++++++++---
 6 files changed, 206 insertions(+), 30 deletions(-)


From horms+renesas at verge.net.au  Mon May 27 05:59:27 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:27 +0900
Subject: [PATCH 3/9] ARM: shmobile: r8a7778: fixup Ether setup code position
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-4-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Ether setup code position was scattering.
This patch fixes it up

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7778.c |   28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a33..d6ee521 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -80,12 +80,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
 	.clocksource_rating	= 200,
 };
 
-/* Ether */
-static struct resource ether_resources[] = {
-	DEFINE_RES_MEM(0xfde00000, 0x400),
-	DEFINE_RES_IRQ(gic_iid(0x89)),
-};
-
 #define r8a7778_register_tmu(idx)			\
 	platform_device_register_resndata(		\
 		&platform_bus, "sh_tmu", idx,		\
@@ -94,6 +88,20 @@ static struct resource ether_resources[] = {
 		&sh_tmu##idx##_platform_data,		\
 		sizeof(sh_tmu##idx##_platform_data))
 
+/* Ether */
+static struct resource ether_resources[] = {
+	DEFINE_RES_MEM(0xfde00000, 0x400),
+	DEFINE_RES_IRQ(gic_iid(0x89)),
+};
+
+void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+	platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+					  ether_resources,
+					  ARRAY_SIZE(ether_resources),
+					  pdata, sizeof(*pdata));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
 	int i;
@@ -118,14 +126,6 @@ void __init r8a7778_add_standard_devices(void)
 	r8a7778_register_tmu(1);
 }
 
-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
-{
-	platform_device_register_resndata(&platform_bus, "sh_eth", -1,
-					  ether_resources,
-					  ARRAY_SIZE(ether_resources),
-					  pdata, sizeof(*pdata));
-}
-
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
 	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 	.sense_bitfield_width = 2,
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:33 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:33 +0900
Subject: [PATCH 9/9] ARM: shmobile: r8a7778: correct model name in Kconfig
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-10-git-send-email-horms+renesas@verge.net.au>

From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car
M1S which is a SH based SoC.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
[horms+renesas at verge.net.au: manually applied to soc-r8a7778 branch]
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 06da4d3..58eb689 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,7 @@ config ARCH_R8A7740
 	select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-	bool "R-Car M1 (R8A77780)"
+	bool "R-Car M1A (R8A77781)"
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select CPU_V7
 	select SH_CLK_CPG
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:41 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:41 +0900
Subject: [GIT PULL v2] Renesas ARM based sh7372 SoC updates for v3.11
Message-ID: <1369648782-8024-1-git-send-email-horms+renesas@verge.net.au>

Hi Arnd, Hi Olof,

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-sh7372-for-v3.11

for you to fetch changes up to 98a443fd3cb4460dd9bec09b3e1d602bc9efa93c:

  ARM: shmobile: sh7372 pinmux platform device cleanup (2013-05-27 18:18:22 +0900)

----------------------------------------------------------------
Renesas ARM based sh7372 SoC updates for v3.11

* Clean-up from Magnus Damm to use DEFINE_RES_MEM() to slightly reduce code size

----------------------------------------------------------------
Magnus Damm (1):
      ARM: shmobile: sh7372 pinmux platform device cleanup

 arch/arm/mach-shmobile/setup-sh7372.c |   24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)


From horms+renesas at verge.net.au  Mon May 27 05:59:42 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:42 +0900
Subject: [PATCH] ARM: shmobile: sh7372 pinmux platform device cleanup
In-Reply-To: <1369648782-8024-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648782-8024-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648782-8024-2-git-send-email-horms+renesas@verge.net.au>

From: Magnus Damm <damm at opensource.se>

Use DEFINE_RES_MEM() and platform_device_register_simple()
to save a couple of lines of code.

Signed-off-by: Magnus Damm <damm at opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh7372.c |   24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5502d62..c70a3cc 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -62,29 +62,15 @@ void __init sh7372_map_io(void)
 }
 
 /* PFC */
-static struct resource sh7372_pfc_resources[] = {
-	[0] = {
-		.start	= 0xe6050000,
-		.end	= 0xe6057fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0xe605800c,
-		.end	= 0xe6058027,
-		.flags	= IORESOURCE_MEM,
-	}
-};
-
-static struct platform_device sh7372_pfc_device = {
-	.name		= "pfc-sh7372",
-	.id		= -1,
-	.resource	= sh7372_pfc_resources,
-	.num_resources	= ARRAY_SIZE(sh7372_pfc_resources),
+static const struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xe6050000, 0x8000),
+	DEFINE_RES_MEM(0xe605800c, 0x001c),
 };
 
 void __init sh7372_pinmux_init(void)
 {
-	platform_device_register(&sh7372_pfc_device);
+	platform_device_register_simple("pfc-sh7372", -1, pfc_resources,
+					ARRAY_SIZE(pfc_resources));
 }
 
 /* SCIFA0 */
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:31 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:31 +0900
Subject: [PATCH 7/9] ARM: shmobile: r8a7778: add SDHI clock support
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-8-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7778.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 5cc271e..b251e4d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -103,12 +103,16 @@ static struct clk *main_clks[] = {
 };
 
 enum {
+	MSTP323, MSTP322, MSTP321,
 	MSTP114,
 	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 	MSTP016, MSTP015,
 	MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
+	[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
+	[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
 	[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
 	[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
@@ -122,6 +126,9 @@ static struct clk mstp_clks[MSTP_NR] = {
 
 static struct clk_lookup lookups[] = {
 	/* MSTP32 clocks */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
 	CLKDEV_DEV_ID("sh-eth",	&mstp_clks[MSTP114]), /* Ether */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:32 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:32 +0900
Subject: [PATCH 8/9] ARM: shmobile: r8a7778: Register SDHI device
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-9-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

This patch adds SDHI register function which needs id number (= 0/1/2)

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7778.h |    2 ++
 arch/arm/mach-shmobile/setup-r8a7778.c        |   24 ++++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 68053fc..ae65b45 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,6 +18,7 @@
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
 
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
 
 extern void r8a7778_add_standard_devices(void);
@@ -29,5 +30,6 @@ extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
 extern void r8a7778_pinmux_init(void);
+extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index d82954b..4c32784 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -115,6 +115,30 @@ void __init r8a7778_pinmux_init(void)
 		ARRAY_SIZE(pfc_resources));
 }
 
+/* SDHI */
+static struct resource sdhi_resources[] = {
+	/* SDHI0 */
+	DEFINE_RES_MEM(0xFFE4C000, 0x100),
+	DEFINE_RES_IRQ(gic_iid(0x77)),
+	/* SDHI1 */
+	DEFINE_RES_MEM(0xFFE4D000, 0x100),
+	DEFINE_RES_IRQ(gic_iid(0x78)),
+	/* SDHI2 */
+	DEFINE_RES_MEM(0xFFE4F000, 0x100),
+	DEFINE_RES_IRQ(gic_iid(0x76)),
+};
+
+void __init r8a7778_sdhi_init(int id,
+			      struct sh_mobile_sdhi_info *info)
+{
+	BUG_ON(id < 0 || id > 2);
+
+	platform_device_register_resndata(
+		&platform_bus, "sh_mobile_sdhi", id,
+		sdhi_resources + (2 * id), 2,
+		info, sizeof(*info));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
 	int i;
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:30 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:30 +0900
Subject: [PATCH 6/9] ARM: shmobile: r8a7778: Register PFC device
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-7-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/Kconfig                |    1 +
 arch/arm/mach-shmobile/include/mach/r8a7778.h |    1 +
 arch/arm/mach-shmobile/setup-r8a7778.c        |   13 +++++++++++++
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2..06da4d3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -37,6 +37,7 @@ config ARCH_R8A7740
 
 config ARCH_R8A7778
 	bool "R-Car M1 (R8A77780)"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select CPU_V7
 	select SH_CLK_CPG
 	select ARM_GIC
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e..68053fc 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -28,5 +28,6 @@ extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 45f0e45..d82954b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -102,6 +102,19 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
 					  pdata, sizeof(*pdata));
 }
 
+/* PFC */
+static struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+
+void __init r8a7778_pinmux_init(void)
+{
+	platform_device_register_simple(
+		"pfc-r8a7778", -1,
+		pfc_resources,
+		ARRAY_SIZE(pfc_resources));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
 	int i;
-- 
1.7.10.4



From horms+renesas at verge.net.au  Mon May 27 05:59:29 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Mon, 27 May 2013 18:59:29 +0900
Subject: [PATCH 5/9] ARM: shmobile: r8a7778: use fixed ratio clock
In-Reply-To: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369648773-7941-6-git-send-email-horms+renesas@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

R-Car M1 has many clocks, and it is possible to
read/use clock ratio of these clocks from FRQMRx.
But, these ratio are fixed value and
these are decided by MD pin status.

This patch reads MD pin status,
and used fixed ratio clock for other clocks.
It was tesed on bock-w board.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7778.c |  149 +++++++++++++++++++++++++++++---
 1 file changed, 136 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd68552..5cc271e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
+ *     19      18      12      11                      (HMz)   (MHz)   (MHz)
+ *----------------------------------------------------------------------------
+ *     1       0       0       0       x21     x21     38.00   800     800
+ *     1       0       0       1       x24     x24     33.33   800     800
+ *     1       0       1       0       x28     x28     28.50   800     800
+ *     1       0       1       1       x32     x32     25.00   800     800
+ *     1       1       0       1       x24     x21     33.33   800     700
+ *     1       1       1       0       x28     x21     28.50   800     600
+ *     1       1       1       1       x32     x24     25.00   800     600
+ */
+
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define MSTPCR0		IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
 #define MSTPCR4		IOMEM(0xffc80050)
 #define MSTPCR5		IOMEM(0xffc80054)
 #define MSTPCR6		IOMEM(0xffc80058)
+#define MODEMR		0xFFCC0020
+
+#define MD(nr)	BIT(nr)
 
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
@@ -47,14 +64,42 @@ static struct clk_mapping cpg_mapping = {
 	.len	= 0x80,
 };
 
-static struct clk clkp = {
-	.rate   = 62500000, /* FIXME: shortcut */
-	.flags  = CLK_ENABLE_ON_INIT,
+static struct clk extal_clk = {
+	/* .rate will be updated on r8a7778_clock_init() */
 	.mapping = &cpg_mapping,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7778_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(plla_clk,	extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(pllb_clk,	extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(i_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s1_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s3_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s4_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(b_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(out_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(p_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(g_clk,		plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(z_clk,		pllb_clk,  1, 1);
+
 static struct clk *main_clks[] = {
-	&clkp,
+	&extal_clk,
+	&plla_clk,
+	&pllb_clk,
+	&i_clk,
+	&s_clk,
+	&s1_clk,
+	&s3_clk,
+	&s4_clk,
+	&b_clk,
+	&out_clk,
+	&p_clk,
+	&g_clk,
+	&z_clk,
 };
 
 enum {
@@ -64,15 +109,15 @@ enum {
 	MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
-	[MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
-	[MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
-	[MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
-	[MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
-	[MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
-	[MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
-	[MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
-	[MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
-	[MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
+	[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+	[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
+	[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
+	[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
+	[MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
+	[MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
+	[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
+	[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
+	[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -90,8 +135,86 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7778_clock_init(void)
 {
+	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+	u32 mode;
 	int k, ret = 0;
 
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
+	case MD(19):
+		extal_clk.rate = 38000000;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	21, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	21, 1);
+		break;
+	case MD(19) | MD(11):
+		extal_clk.rate = 33333333;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	24, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	24, 1);
+		break;
+	case MD(19) | MD(12):
+		extal_clk.rate = 28500000;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	28, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	28, 1);
+		break;
+	case MD(19) | MD(12) | MD(11):
+		extal_clk.rate = 25000000;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	32, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	32, 1);
+		break;
+	case MD(19) | MD(18) | MD(11):
+		extal_clk.rate = 33333333;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	24, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	21, 1);
+		break;
+	case MD(19) | MD(18) | MD(12):
+		extal_clk.rate = 28500000;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	28, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	21, 1);
+		break;
+	case MD(19) | MD(18) | MD(12) | MD(11):
+		extal_clk.rate = 25000000;
+		SH_CLK_SET_RATIO(&plla_clk_ratio,	32, 1);
+		SH_CLK_SET_RATIO(&pllb_clk_ratio,	24, 1);
+		break;
+	default:
+		BUG();
+	}
+
+	if (mode & MD(1)) {
+		SH_CLK_SET_RATIO(&i_clk_ratio,	1, 1);
+		SH_CLK_SET_RATIO(&s_clk_ratio,	1, 3);
+		SH_CLK_SET_RATIO(&s1_clk_ratio,	1, 6);
+		SH_CLK_SET_RATIO(&s3_clk_ratio,	1, 4);
+		SH_CLK_SET_RATIO(&s4_clk_ratio,	1, 8);
+		SH_CLK_SET_RATIO(&p_clk_ratio,	1, 12);
+		SH_CLK_SET_RATIO(&g_clk_ratio,	1, 12);
+		if (mode & MD(2)) {
+			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 18);
+			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 18);
+		} else {
+			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 12);
+			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 12);
+		}
+	} else {
+		SH_CLK_SET_RATIO(&i_clk_ratio,	1, 1);
+		SH_CLK_SET_RATIO(&s_clk_ratio,	1, 4);
+		SH_CLK_SET_RATIO(&s1_clk_ratio,	1, 8);
+		SH_CLK_SET_RATIO(&s3_clk_ratio,	1, 4);
+		SH_CLK_SET_RATIO(&s4_clk_ratio,	1, 8);
+		SH_CLK_SET_RATIO(&p_clk_ratio,	1, 16);
+		SH_CLK_SET_RATIO(&g_clk_ratio,	1, 12);
+		if (mode & MD(2)) {
+			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 16);
+			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 16);
+		} else {
+			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 12);
+			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 12);
+		}
+	}
+
 	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 		ret = clk_register(main_clks[k]);
 
-- 
1.7.10.4



From josh.wu at atmel.com  Mon May 27 05:59:59 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Mon, 27 May 2013 17:59:59 +0800
Subject: [PATCH v2 0/4] mtd: atmel_nand: enable Nand Flash Controller
 (NFC) support
In-Reply-To: <20130524195525.GL24476@game.jcrosoft.org>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <20130524195525.GL24476@game.jcrosoft.org>
Message-ID: <51A32E9F.7090009@atmel.com>

On 5/25/2013 3:55 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:51 Fri 17 May     , Josh Wu wrote:
>> This patch series enable NFC support for SAMA5 soc. It can send command,
>> address cycles automaticly. Also when enable NFC sram, NFC will transfer
>> data to sram. Which can save lots of cpu time.
> can you give some stats please

I already have some test stats in the followed patches. Maybe I can put 
the summary here too.

>
> and performance comparaisan NFS vs DMA

OK. I will add the DMA test data.

Best Regards,
Josh Wu

>
> Best Regards,
> J.
>> v1 --> v2:
>>   1) rebase it with latest l2-mtd git tree:
>>      - remove useless nand commands (NAND_CMD_DEPLETE1, NAND_CMD_STATUS_ERRORx).
>>      - adopt to the new nand write function's parameters. Add error message when
>>        handle subpage write via nfc sram.
>>   2) rewrite pmecc_enable function. Now I use exist NAND_ECC_READ/WRITE const
>>      instead of using a new enum definition.
>>
>> Josh Wu (4):
>>    mtd: atmel_nand: replace pmecc enable code with one function.
>>    mtd: atmel_nand: add Nand Flash Controller (NFC) support
>>    mtd: atmel_nand: enable Nand Flash Controller (NFC) read data via
>>      sram
>>    mtd: atmel_nand: enable Nand Flash Controller (NFC) write via sram
>>
>>   .../devicetree/bindings/mtd/atmel-nand.txt         |    4 +
>>   drivers/mtd/nand/atmel_nand.c                      |  657 ++++++++++++++++++--
>>   drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++
>>   3 files changed, 718 insertions(+), 49 deletions(-)
>>   create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h
>>
>> -- 
>> 1.7.9.5
>>



From maxime.ripard at free-electrons.com  Mon May 27 06:00:40 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:40 +0200
Subject: [PATCHv3 3/6] ARM: sun4i: dt: Add i2c muxing options
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369648843-1640-4-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A10 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 311dcd4..63f6716 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Mon May 27 06:00:37 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:37 +0200
Subject: [PATCHv3 0/6] Add I2C support for Allwinner SoCs
Message-ID: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

This patchset adds support for the I2C controller found on most of the
Allwinner SoCs, especially the already supported A10 and A13, and the
yet to come A31.

It has been tested on a A13-Olinuxino.

Thanks,
Maxime

Changes from v2:
  * Slightly modified the switch comments again
  * Removed the of_* calls in favor of platform_get_* functions

Changes from v1:
  * Added comments to the switch statements to clarify when the fall through to
    the next case is made on purpose
  * Use devm_ioremap_resource instead of of_iomap
  * Moved the reset after enabling the clocks
  * Added Emilio Lopez' patch to add the available i2c controllers to the
    cubieboard

Emilio L?pez (1):
  ARM: sun4i: cubieboard: Enable the i2c controllers

Maxime Ripard (5):
  i2c: sunxi: Add Allwinner A1X i2c driver
  ARM: sunxi: dt: Add i2c controller nodes to the DTSI
  ARM: sun4i: dt: Add i2c muxing options
  ARM: sun5i: dt: Add i2c muxing options
  ARM: sun5i: olinuxino: Enable the i2c controllers

 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  12 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 444 +++++++++++++++++++++
 8 files changed, 600 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Mon May 27 06:00:41 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:41 +0200
Subject: [PATCHv3 4/6] ARM: sun5i: dt: Add i2c muxing options
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369648843-1640-5-git-send-email-maxime.ripard@free-electrons.com>

The i2c controller found on the Allwinner A13 has only one muxing option
available for each controller. Add them to the dtsi

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 16df784..450b410 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -182,6 +182,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB15", "PB16";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB17", "PB18";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Mon May 27 06:00:39 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:39 +0200
Subject: [PATCHv3 2/6] ARM: sunxi: dt: Add i2c controller nodes to the DTSI
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369648843-1640-3-git-send-email-maxime.ripard@free-electrons.com>

The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..311dcd4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -292,5 +292,32 @@
 			clocks = <&apb1_gates 23>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..16df784 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -215,5 +215,32 @@
 			clocks = <&apb1_gates 19>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Mon May 27 06:00:38 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:38 +0200
Subject: [PATCHv3 1/6] i2c: sunxi: Add Allwinner A1X i2c driver
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369648843-1640-2-git-send-email-maxime.ripard@free-electrons.com>

This patch implements a basic driver for the I2C host driver found on
the Allwinner A10, A13 and A31 SoCs.

Notable missing feature is 10-bit addressing.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 444 +++++++++++++++++++++
 4 files changed, 474 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
new file mode 100644
index 0000000..40c16d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-i2c".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c at 01c2ac00 {
+	compatible = "allwinner,sun4i-i2c";
+	reg = <0x01c2ac00 0x400>;
+	interrupts = <7>;
+	clocks = <&apb1_gates 0>;
+	clock-frequency = <100000>;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 631736e..1df8ba1 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -706,6 +706,16 @@ config I2C_STU300
 	  This driver can also be built as a module. If so, the module
 	  will be called i2c-stu300.
 
+config I2C_SUNXI
+	tristate "Allwinner A1X I2C controller"
+	depends on ARCH_SUNXI
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controller embedded in Allwinner A1X SoCs.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called i2c-sunxi.
+
 config I2C_TEGRA
 	tristate "NVIDIA Tegra internal I2C controller"
 	depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..7225818 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
 obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
diff --git a/drivers/i2c/busses/i2c-sunxi.c b/drivers/i2c/busses/i2c-sunxi.c
new file mode 100644
index 0000000..09e086a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi.c
@@ -0,0 +1,444 @@
+/*
+ * Allwinner A1X SoCs i2c controller driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)
+
+struct sunxi_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct clk		*clk;
+	struct device		*dev;
+	struct completion	completion;
+	int			irq;
+	void __iomem		*membase;
+
+	struct i2c_msg		*msg_cur;
+	u8			*msg_buf;
+	size_t			msg_buf_remaining;
+	unsigned int		msg_err;
+};
+
+static void sunxi_i2c_write(struct sunxi_i2c_dev *i2c_dev, u16 reg, u32 value)
+{
+	writel(value, i2c_dev->membase + reg);
+}
+
+static u32 sunxi_i2c_read(struct sunxi_i2c_dev *i2c_dev, u16 reg)
+{
+	return readl(i2c_dev->membase + reg);
+}
+
+/*
+ * This is where all the magic happens. The I2C controller works as a
+ * state machine, each state being a step in the i2c protocol, with
+ * the controller sending an interrupt at each state transition.
+ *
+ * The state we're in is stored in a register, which leads to a pretty
+ * huge switch statement, all of this in the interrupt handler...
+ */
+static irqreturn_t sunxi_i2c_handler(int irq, void *data)
+{
+	struct sunxi_i2c_dev *i2c_dev = (struct sunxi_i2c_dev *)data;
+	u32 status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	u32 addr, val;
+
+	if (!(status & SUNXI_I2C_CNTR_INT_FLAG))
+		return IRQ_NONE;
+
+	/* Read the current state we're in */
+	status = sunxi_i2c_read(i2c_dev, SUNXI_I2C_STA_REG);
+
+	switch (status & 0xff) {
+	/* Start condition has been transmitted */
+	case SUNXI_I2C_STA_START:
+	/* A repeated start condition has been transmitted */
+	case SUNXI_I2C_STA_START_REPEAT:
+		addr = SUNXI_I2C_ADDR_ADDR(i2c_dev->msg_cur->addr);
+
+		if (i2c_dev->msg_cur->flags & I2C_M_RD)
+			addr |= 1;
+
+		sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG, addr);
+		break;
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has not been
+	 * received.
+	 * Intentional fall through.
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_NAK:
+	/*
+	 * Data byte has been transmitted, ACK has not been
+	 * received.
+	 * Intentional fall through.
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Write bit have been transmitted, ACK has been
+	 * received.
+	 * Intentional fall through.
+	 */
+	case SUNXI_I2C_STA_MASTER_WADDR_ACK:
+	/* Data byte has been transmitted, ACK has been received */
+	case SUNXI_I2C_STA_MASTER_DATA_SENT_ACK:
+		if (i2c_dev->msg_buf_remaining) {
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_DATA_REG,
+					*i2c_dev->msg_buf);
+			i2c_dev->msg_buf++;
+			i2c_dev->msg_buf_remaining--;
+			break;
+		}
+
+		if (i2c_dev->msg_buf_remaining == 0) {
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		break;
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has not been
+	 * received.
+	 * Intentional fall through.
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_NAK:
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/*
+	 * Address + Read bit have been transmitted, ACK has been
+	 * received.
+	 */
+	case SUNXI_I2C_STA_MASTER_RADDR_ACK:
+		/*
+		 * We only need to send the ACK for the all the bytes
+		 * but the last one
+		 */
+		if (i2c_dev->msg_buf_remaining > 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val | SUNXI_I2C_CNTR_ASSERT_ACK);
+		}
+
+		break;
+
+	/*
+	 * Data byte has been received, ACK has not been
+	 * transmitted.
+	 * Intentional fall through.
+	 */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_NAK:
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG);
+			*i2c_dev->msg_buf = val & 0xff;
+			i2c_dev->msg_buf_remaining--;
+			i2c_dev->msg_err = SUNXI_I2C_DONE;
+			goto out;
+		}
+
+		if (!(i2c_dev->msg_cur->flags & I2C_M_IGNORE_NAK)) {
+			i2c_dev->msg_err = SUNXI_I2C_NAK;
+			goto out;
+		}
+
+	/* Data byte has been received, ACK has been transmitted */
+	case SUNXI_I2C_STA_MASTER_DATA_RECV_ACK:
+		val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_DATA_REG) & 0xff;
+		*i2c_dev->msg_buf = val;
+		i2c_dev->msg_buf++;
+		i2c_dev->msg_buf_remaining--;
+
+		/* If there's only one byte left, disable the ACK */
+		if (i2c_dev->msg_buf_remaining == 1) {
+			val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+			sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+					val & ~SUNXI_I2C_CNTR_ASSERT_ACK);
+
+		};
+
+		break;
+
+	case SUNXI_I2C_STA_BUS_ERROR:
+		i2c_dev->msg_err = SUNXI_I2C_BUS_ERROR;
+		goto out;
+
+	default:
+		i2c_dev->msg_err = SUNXI_I2C_ERROR;
+		goto out;
+	}
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	return IRQ_HANDLED;
+
+out:
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val | SUNXI_I2C_CNTR_MASTER_STOP);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			val & ~SUNXI_I2C_CNTR_INT_FLAG);
+
+	complete(&i2c_dev->completion);
+	return IRQ_HANDLED;
+}
+
+static int sunxi_i2c_xfer_msg(struct sunxi_i2c_dev *i2c_dev,
+			      struct i2c_msg *msg)
+{
+	int time_left;
+	u32 val;
+
+	i2c_dev->msg_cur = msg;
+	i2c_dev->msg_buf = msg->buf;
+	i2c_dev->msg_buf_remaining = msg->len;
+	i2c_dev->msg_err = 0;
+	INIT_COMPLETION(i2c_dev->completion);
+
+	val = sunxi_i2c_read(i2c_dev, SUNXI_I2C_CNTR_REG);
+	val |= SUNXI_I2C_CNTR_MASTER_START;
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG, val);
+
+	time_left = wait_for_completion_timeout(&i2c_dev->completion,
+						i2c_dev->adapter.timeout);
+	if (!time_left) {
+		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	if (likely(i2c_dev->msg_err == SUNXI_I2C_DONE))
+		return 0;
+
+	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
+
+	return -EIO;
+}
+
+static int sunxi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			  int num)
+{
+	struct sunxi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	int i, ret;
+
+	for (i = 0; i < num; i++) {
+		ret = sunxi_i2c_xfer_msg(i2c_dev, &msgs[i]);
+		if (ret)
+			return ret;
+	}
+
+	return i;
+}
+
+static u32 sunxi_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm sunxi_i2c_algo = {
+	.master_xfer	= sunxi_i2c_xfer,
+	.functionality	= sunxi_i2c_func,
+};
+
+static int sunxi_i2c_probe(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev;
+	struct device_node *np;
+	u32 freq, div_m, div_n;
+	struct resource *res;
+	int ret;
+
+	np = pdev->dev.of_node;
+	if (!np)
+		return -EINVAL;
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, i2c_dev);
+	i2c_dev->dev = &pdev->dev;
+
+	init_completion(&i2c_dev->completion);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	i2c_dev->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(i2c_dev->membase))
+		return PTR_ERR(i2c_dev->membase);
+
+	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(i2c_dev->clk))
+		return PTR_ERR(i2c_dev->clk);
+
+	clk_prepare_enable(i2c_dev->clk);
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_SRST_REG, SUNXI_I2C_SRST_RESET);
+
+	ret = of_property_read_u32(np, "clock-frequency", &freq);
+	if (ret < 0) {
+		dev_warn(&pdev->dev, "Could not read clock-frequency property\n");
+		freq = 100000;
+	}
+
+	/*
+	 * Set the clock dividers. we don't need to be super smart
+	 * here, the datasheet defines the value of the factors for
+	 * the two supported frequencies, and only the M factor
+	 * changes between 100kHz and 400kHz.
+	 *
+	 * The bus clock is generated from the parent clock with two
+	 * different dividers. It is generated as such:
+	 *     f0 = fclk / (2 ^ DIV_N)
+	 *     fbus = f0 / (10 * (DIV_M + 1))
+	 *
+	 * With DIV_N being on 3 bits, and DIV_M on 4 bits.
+	 * So DIV_N < 8, and DIV_M < 16.
+	 *
+	 * However, we can generate both the supported frequencies
+	 * with f0 = 12MHz, and only change M to get back on our
+	 * feet.
+	 */
+	div_n = ilog2(clk_get_rate(i2c_dev->clk) / 12000000);
+	if (freq == 100000)
+		div_m = 11;
+	else if (freq == 400000)
+		div_m = 2;
+	else {
+		dev_err(&pdev->dev, "Unsupported bus frequency\n");
+		ret = -EINVAL;
+		goto out_clk_dis;
+	}
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CCR_REG,
+			SUNXI_I2C_CCR_DIV_N(div_n) | SUNXI_I2C_CCR_DIV_M(div_m));
+
+	i2c_dev->irq = platform_get_irq(pdev, 0);
+	if (i2c_dev->irq < 0) {
+		dev_err(&pdev->dev, "No IRQ resource\n");
+		ret = i2c_dev->irq;
+		goto out_clk_dis;
+	}
+
+	ret = devm_request_irq(&pdev->dev, i2c_dev->irq, sunxi_i2c_handler,
+			       IRQF_SHARED, dev_name(&pdev->dev), i2c_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not request IRQ\n");
+		goto out_clk_dis;
+	}
+
+	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
+
+	i2c_dev->adapter.owner = THIS_MODULE;
+	strlcpy(i2c_dev->adapter.name, "sunxi I2C adapter",
+		sizeof(i2c_dev->adapter.name));
+	i2c_dev->adapter.algo = &sunxi_i2c_algo;
+	i2c_dev->adapter.dev.parent = &pdev->dev;
+
+	sunxi_i2c_write(i2c_dev, SUNXI_I2C_CNTR_REG,
+			SUNXI_I2C_CNTR_BUS_ENABLE | SUNXI_I2C_CNTR_INT_ENABLE);
+
+	ret = i2c_add_adapter(&i2c_dev->adapter);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register i2c adapter\n");
+		goto out_clk_dis;
+	}
+
+	return 0;
+
+out_clk_dis:
+	clk_disable_unprepare(i2c_dev->clk);
+	return ret;
+}
+
+
+static int sunxi_i2c_remove(struct platform_device *pdev)
+{
+	struct sunxi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+	clk_disable_unprepare(i2c_dev->clk);
+
+	return 0;
+}
+
+static const struct of_device_id sunxi_i2c_of_match[] = {
+	{ .compatible = "allwinner,sun4i-i2c" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sunxi_i2c_of_match);
+
+static struct platform_driver sunxi_i2c_driver = {
+	.probe		= sunxi_i2c_probe,
+	.remove		= sunxi_i2c_remove,
+	.driver		= {
+		.name	= "i2c-sunxi",
+		.owner	= THIS_MODULE,
+		.of_match_table = sunxi_i2c_of_match,
+	},
+};
+module_platform_driver(sunxi_i2c_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com");
+MODULE_DESCRIPTION("Allwinner A1X I2C bus adapter");
+MODULE_LICENSE("GPL");
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Mon May 27 06:00:42 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:42 +0200
Subject: [PATCHv3 5/6] ARM: sun5i: olinuxino: Enable the i2c controllers
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369648843-1640-6-git-send-email-maxime.ripard@free-electrons.com>

The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner
A13. Enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca5506..80497e3 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
 			pinctrl-0 = <&uart1_pins_b>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Mon May 27 06:00:43 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:00:43 +0200
Subject: [PATCHv3 6/6] ARM: sun4i: cubieboard: Enable the i2c controllers
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369648843-1640-7-git-send-email-maxime.ripard@free-electrons.com>

From: Emilio L?pez <emilio at elopez.com.ar>

The Cubieboard makes use of the first two i2c controllers found on the
Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1
is exposed on the board headers. This patch enables them in the device
tree.

Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..0e22a28 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -41,6 +41,18 @@
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.2.3



From gang.chen at asianux.com  Mon May 27 06:02:40 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 18:02:40 +0800
Subject: [PATCH v2] arm64: kernel: compiling issue,
 need delete read_current_timer().
In-Reply-To: <519B425D.4030806@asianux.com>
References: <5199C725.8050102@asianux.com>
 <168084c28e8ba5124c05553e97463172@localhost>
 <20130520095606.GH31359@mudshark.cambridge.arm.com>
 <519AF2DC.2040200@asianux.com>
 <20130521085325.GB10453@mudshark.cambridge.arm.com>
 <519B425D.4030806@asianux.com>
Message-ID: <51A32F40.1050309@asianux.com>

Hello Maintainers:

Please help check this patch whether OK, when you have time.

Thanks.

On 05/21/2013 05:46 PM, Chen Gang wrote:
> 
> Under arm64, we will calibrate the delay loop statically using a known
> timer frequency, so delete read_current_timer(), or it will cause
> compiling issue with allmodconfig.
> 
> The related error:
>   ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined!
>   ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined!
>   ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined!
>   ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/include/asm/timex.h |    6 +++---
>  arch/arm64/kernel/time.c       |    6 ------
>  2 files changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h
> index b24a31a..81a076e 100644
> --- a/arch/arm64/include/asm/timex.h
> +++ b/arch/arm64/include/asm/timex.h
> @@ -16,14 +16,14 @@
>  #ifndef __ASM_TIMEX_H
>  #define __ASM_TIMEX_H
>  
> +#include <asm/arch_timer.h>
> +
>  /*
>   * Use the current timer as a cycle counter since this is what we use for
>   * the delay loop.
>   */
> -#define get_cycles()	({ cycles_t c; read_current_timer(&c); c; })
> +#define get_cycles()	arch_counter_get_cntvct()
>  
>  #include <asm-generic/timex.h>
>  
> -#define ARCH_HAS_READ_CURRENT_TIMER
> -
>  #endif
> diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
> index a551f88..03dc371 100644
> --- a/arch/arm64/kernel/time.c
> +++ b/arch/arm64/kernel/time.c
> @@ -68,12 +68,6 @@ unsigned long long notrace sched_clock(void)
>  	return arch_timer_read_counter() * sched_clock_mult;
>  }
>  
> -int read_current_timer(unsigned long *timer_value)
> -{
> -	*timer_value = arch_timer_read_counter();
> -	return 0;
> -}
> -
>  void __init time_init(void)
>  {
>  	u32 arch_timer_rate;
> 


-- 
Chen Gang

Asianux Corporation


From maxime.ripard at free-electrons.com  Mon May 27 06:04:53 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Mon, 27 May 2013 12:04:53 +0200
Subject: [linux-sunxi] [PATCHv2 1/6] i2c: sunxi: Add Allwinner A1X i2c
 driver
In-Reply-To: <51A25C21.2060700@schinagl.nl>
References: <1369563642-4390-1-git-send-email-maxime.ripard@free-electrons.com>
 <1369563642-4390-2-git-send-email-maxime.ripard@free-electrons.com>
 <51A1E9AA.4000008@schinagl.nl> <20130526132120.GJ17847@lukather>
 <51A25C21.2060700@schinagl.nl>
Message-ID: <20130527100453.GM17847@lukather>

Hi Oliver,

On Sun, May 26, 2013 at 09:01:53PM +0200, Oliver Schinagl wrote:
> On 05/26/13 15:21, Maxime Ripard wrote:
> >For the iowrite* vs write*, there's no consensus, and as such no
> >preferred way. write* functions are doing an MMIO only access,
> >while iowrite functions can do MMIO and port I/O accesses.
> >
> >Note that it doesn't change anything on ARM, since there's no port IO on
> >ARM.
> Ah I see, missinformation on my end. Sorry.
> 
> But why write 32 bits? The register is only 8 wide, with the rest
> being 'reserved'. Then again, the register IS 32 bits wide and
> probably will haev 32 bits written to it? Correct?

Yes, the register is 32 bits wide. However, and I didn't noticed it at
first, that all the registers have the 3 upper bytes reserved.

But you'll end up writing a 32 bits value to a 32 bit register register
anyway, even if the relevant information is contained in the 8 first
bits.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From gang.chen at asianux.com  Mon May 27 06:04:21 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 18:04:21 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL(clear_page)'
In-Reply-To: <5199CCF9.4030305@asianux.com>
References: <5199CCF9.4030305@asianux.com>
Message-ID: <51A32FA5.3080200@asianux.com>

Hello Maintainers:

Please help check this patch whether OK, when you have time.


Thanks.

On 05/20/2013 03:12 PM, Chen Gang wrote:
> 
> Need 'EXPORT_SYMBOL(clear_page)' if building with allmodconfig.
> 
> The related errors:
>   ERROR: "clear_page" [fs/ocfs2/dlm/ocfs2_dlm.ko] undefined!
>   ERROR: "clear_page" [fs/ntfs/ntfs.ko] undefined!
>   ERROR: "clear_page" [fs/gfs2/gfs2.ko] undefined!
>   ERROR: "clear_page" [fs/fuse/fuse.ko] undefined!
>   ERROR: "clear_page" [fs/ext3/ext3.ko] undefined!
>   ERROR: "clear_page" [fs/ext2/ext2.ko] undefined!
>   ERROR: "clear_page" [fs/exofs/libore.ko] undefined!
>   ERROR: "clear_page" [fs/exofs/exofs.ko] undefined!
>   ERROR: "clear_page" [drivers/block/brd.ko] undefined!
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/kernel/arm64ksyms.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
> index 7df1aad..41b4f62 100644
> --- a/arch/arm64/kernel/arm64ksyms.c
> +++ b/arch/arm64/kernel/arm64ksyms.c
> @@ -34,6 +34,7 @@ EXPORT_SYMBOL(__strnlen_user);
>  EXPORT_SYMBOL(__strncpy_from_user);
>  
>  EXPORT_SYMBOL(copy_page);
> +EXPORT_SYMBOL(clear_page);
>  
>  EXPORT_SYMBOL(__copy_from_user);
>  EXPORT_SYMBOL(__copy_to_user);
> 


-- 
Chen Gang

Asianux Corporation


From gang.chen at asianux.com  Mon May 27 06:05:08 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 18:05:08 +0800
Subject: [PATCH] ARM: S5PV210: dependency issue, S5P_SLEEP is depend on
 ARM_CPU_SUSPEND
In-Reply-To: <5199E4AF.7040607@asianux.com>
References: <5199E4AF.7040607@asianux.com>
Message-ID: <51A32FD4.4000001@asianux.com>

Hello Maintainers:

Please help check this patch whether OK, when you have time.


Thanks.

On 05/20/2013 04:54 PM, Chen Gang wrote:
> 
> When randconfig with MMU for arm s5pv210 (and select all cpu type),
> need let S5P_SLEEP depend on ARM_CPU_SUSPEND, or will cause issue below:
> 
>   arch/arm/plat-samsung/built-in.o: In function `s3c_cpu_resume':
>   arch/arm/plat-samsung/s5p-sleep.S:83: undefined reference to `cpu_resume'
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm/plat-samsung/Kconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
> index f8ed2de..1d38541 100644
> --- a/arch/arm/plat-samsung/Kconfig
> +++ b/arch/arm/plat-samsung/Kconfig
> @@ -483,6 +483,7 @@ config S5P_PM
>  
>  config S5P_SLEEP
>  	bool
> +	select ARM_CPU_SUSPEND
>  	help
>  	  Internal config node to apply common S5P sleep management code.
>  	  Can be selected by S5P and newer SoCs with similar sleep procedure.
> 


-- 
Chen Gang

Asianux Corporation


From josh.wu at atmel.com  Mon May 27 06:01:42 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Mon, 27 May 2013 18:01:42 +0800
Subject: [PATCH v2 4/4] mtd: atmel_nand: enable Nand Flash Controller
 (NFC) write via sram
In-Reply-To: <20130524201150.GN24476@game.jcrosoft.org>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-5-git-send-email-josh.wu@atmel.com>
 <20130524201150.GN24476@game.jcrosoft.org>
Message-ID: <51A32F06.9040807@atmel.com>

On 5/25/2013 4:11 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:51 Fri 17 May     , Josh Wu wrote:
>> This patch enable writing nand flash via NFC SRAM. It will minimize the CPU
>> overhead. The SRAM write only support ECC_NONE and ECC_HW with PMECC.
>>
>> This driver has been tested on SAMA5D3X-EK with JFFS2, YAFFS2, UBIFS and
>> mtd-utils.
>>
>> Here is part of mtd_speedtest (writing test) result, compare with non-NFC
>> writing, it reduces %65 cpu load with loss %12 speed.
> we may want to enable only read on sram and not write as the write speed can
> be critic on some system

I will add one more option to allow user to choose to use NFC write via 
sram.

Best Regards,
Josh Wu

>
> Best Regards,
> J.
>> - commands use to test:
>>    # insmod /mnt/mtd_speedtest.ko dev=2 &
>>    # top -n 30 -d 1 | grep speedtest
>>
>> - test result:
>> =================================================
>> mtd_speedtest: MTD device: 2
>> mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
>> mtd_speedtest: testing eraseblock write speed
>>    509   495 root     D     1164   0%   7% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%   8% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     R     1164   0%   5% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: eraseblock write speed is 5194 KiB/s
>> mtd_speedtest: testing page write speed
>>    509   495 root     D     1164   0%  32% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  27% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  25% insmod /mnt/mtd_speedtest.ko dev=2
>>    509   495 root     D     1164   0%  30% insmod /mnt/mtd_speedtest.ko dev=2
>> mtd_speedtest: page write speed is 5024 KiB/s
>>
>> Signed-off-by: Josh Wu <josh.wu at atmel.com>
>> ---
>> v1 --> v2:
>>    use NAND_ECC_WRITE instead of use new defined pass to pmecc_enable().
>>    report a error if use a partial page write via nfc sram.
>>
>>   drivers/mtd/nand/atmel_nand.c |   94 +++++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 90 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index c10cd71..4490bd6 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -99,6 +99,7 @@ struct atmel_nfc {
>>   
>>   	/* Point to the sram bank which include readed data via NFC */
>>   	void __iomem		*data_in_sram;
>> +	bool			will_write_sram;
>>   };
>>   
>>   struct atmel_nand_host {
>> @@ -218,6 +219,16 @@ static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
>>   		*t++ = readl_relaxed(s++);
>>   }
>>   
>> +static void memcpy32_toio(void __iomem *trg, const void *src, int size)
>> +{
>> +	int i;
>> +	u32 __iomem *t = trg;
>> +	const u32 *s = src;
>> +
>> +	for (i = 0; i < (size >> 2); i++)
>> +		writel_relaxed(*s++, t++);
>> +}
>> +
>>   /*
>>    * Minimal-overhead PIO for data access.
>>    */
>> @@ -339,7 +350,11 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
>>   		dma_dst_addr = phys_addr;
>>   	} else {
>>   		dma_src_addr = phys_addr;
>> -		dma_dst_addr = host->io_phys;
>> +
>> +		if (host->use_nfc_sram)
>> +			dma_dst_addr = nfc_sram_phys(host);
>> +		else
>> +			dma_dst_addr = host->io_phys;
>>   	}
>>   
>>   	tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
>> @@ -919,9 +934,10 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
>>   	int i, j;
>>   	unsigned long end_time;
>>   
>> -	pmecc_enable(host, NAND_ECC_WRITE);
>> -
>> -	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
>> +	if (!host->use_nfc_sram) {
>> +		pmecc_enable(host, NAND_ECC_WRITE);
>> +		chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
>> +	}
>>   
>>   	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
>>   	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
>> @@ -1805,6 +1821,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>>   	case NAND_CMD_SEQIN:
>>   	case NAND_CMD_RNDIN:
>>   		nfcwr = NFCADDR_CMD_NFCWR;
>> +		if (host->nfc.will_write_sram && command == NAND_CMD_SEQIN)
>> +			dataen = NFCADDR_CMD_DATAEN;
>>   		break;
>>   	default:
>>   		break;
>> @@ -1849,6 +1867,68 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>>   	}
>>   }
>>   
>> +static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>> +			uint32_t offset, int data_len, const uint8_t *buf,
>> +			int oob_required, int page, int cached, int raw)
>> +{
>> +	int cfg, len;
>> +	int status = 0;
>> +	struct atmel_nand_host *host = chip->priv;
>> +	void __iomem *sram = host->nfc.sram_bank0 + nfc_get_sram_off(host);
>> +
>> +	/* Subpage write is not supported */
>> +	if (offset || (data_len < mtd->writesize))
>> +		return -EINVAL;
>> +
>> +	cfg = nfc_readl(host->nfc.hsmc_regs, CFG);
>> +	len = mtd->writesize;
>> +
>> +	if (unlikely(raw)) {
>> +		len += mtd->oobsize;
>> +		nfc_writel(host->nfc.hsmc_regs, CFG, cfg | ATMEL_HSMC_WSPARE);
>> +	} else
>> +		nfc_writel(host->nfc.hsmc_regs, CFG, cfg & ~ATMEL_HSMC_WSPARE);
>> +
>> +	/* Copy page data to sram that will write to nand via NFC */
>> +	if (use_dma) {
>> +		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
>> +			/* Fall back to use cpu copy */
>> +			memcpy32_toio(sram, buf, len);
>> +	} else {
>> +		memcpy32_toio(sram, buf, len);
>> +	}
>> +
>> +	if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
>> +		/*
>> +		 * When use NFC sram, need set up PMECC before send
>> +		 * NAND_CMD_SEQIN command. Since when the nand command
>> +		 * is sent, nfc will do transfer from sram and nand.
>> +		 */
>> +		pmecc_enable(host, NAND_ECC_WRITE);
>> +
>> +	host->nfc.will_write_sram = true;
>> +	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
>> +	host->nfc.will_write_sram = false;
>> +
>> +	if (likely(!raw))
>> +		/* Need to write ecc into oob */
>> +		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
>> +
>> +	if (status < 0)
>> +		return status;
>> +
>> +	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
>> +	status = chip->waitfunc(mtd, chip);
>> +
>> +	if ((status & NAND_STATUS_FAIL) && (chip->errstat))
>> +		status = chip->errstat(mtd, chip, FL_WRITING, status, page);
>> +
>> +	if (status & NAND_STATUS_FAIL)
>> +		return -EIO;
>> +
>> +	return 0;
>> +}
>> +
>>   static int nfc_sram_init(struct mtd_info *mtd)
>>   {
>>   	struct nand_chip *chip = mtd->priv;
>> @@ -1887,10 +1967,16 @@ static int nfc_sram_init(struct mtd_info *mtd)
>>   
>>   	nfc_writel(host->nfc.hsmc_regs, CFG, cfg_nfc);
>>   
>> +	host->nfc.will_write_sram = false;
>>   	nfc_set_sram_bank(host, 0);
>>   
>>   	dev_info(host->dev, "Using NFC Sram\n");
>>   
>> +	/* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
>> +	if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
>> +			chip->ecc.mode == NAND_ECC_NONE)
>> +		chip->write_page = nfc_sram_write_page;
>> +
>>   	return 0;
>>   }
>>   
>> -- 
>> 1.7.9.5
>>



From gang.chen at asianux.com  Mon May 27 06:09:51 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 18:09:51 +0800
Subject: [PATCH] arm64: kernel: compiling issue,
 need 'EXPORT_SYMBOL(clear_page)'
In-Reply-To: <51A32FA5.3080200@asianux.com>
References: <5199CCF9.4030305@asianux.com> <51A32FA5.3080200@asianux.com>
Message-ID: <51A330EF.50104@asianux.com>


Oh, thanks, it is already applied, just now.

It seems I need a little patience. :-)


Thanks

On 05/27/2013 06:04 PM, Chen Gang wrote:
> Hello Maintainers:
> 
> Please help check this patch whether OK, when you have time.
> 
> 
> Thanks.
> 
> On 05/20/2013 03:12 PM, Chen Gang wrote:
>>
>> Need 'EXPORT_SYMBOL(clear_page)' if building with allmodconfig.
>>
>> The related errors:
>>   ERROR: "clear_page" [fs/ocfs2/dlm/ocfs2_dlm.ko] undefined!
>>   ERROR: "clear_page" [fs/ntfs/ntfs.ko] undefined!
>>   ERROR: "clear_page" [fs/gfs2/gfs2.ko] undefined!
>>   ERROR: "clear_page" [fs/fuse/fuse.ko] undefined!
>>   ERROR: "clear_page" [fs/ext3/ext3.ko] undefined!
>>   ERROR: "clear_page" [fs/ext2/ext2.ko] undefined!
>>   ERROR: "clear_page" [fs/exofs/libore.ko] undefined!
>>   ERROR: "clear_page" [fs/exofs/exofs.ko] undefined!
>>   ERROR: "clear_page" [drivers/block/brd.ko] undefined!
>>
>>
>> Signed-off-by: Chen Gang <gang.chen at asianux.com>
>> ---
>>  arch/arm64/kernel/arm64ksyms.c |    1 +
>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
>> index 7df1aad..41b4f62 100644
>> --- a/arch/arm64/kernel/arm64ksyms.c
>> +++ b/arch/arm64/kernel/arm64ksyms.c
>> @@ -34,6 +34,7 @@ EXPORT_SYMBOL(__strnlen_user);
>>  EXPORT_SYMBOL(__strncpy_from_user);
>>  
>>  EXPORT_SYMBOL(copy_page);
>> +EXPORT_SYMBOL(clear_page);
>>  
>>  EXPORT_SYMBOL(__copy_from_user);
>>  EXPORT_SYMBOL(__copy_to_user);
>>
> 
> 


-- 
Chen Gang

Asianux Corporation


From kgene.kim at samsung.com  Mon May 27 06:12:11 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 May 2013 19:12:11 +0900
Subject: [PATCH] ARM: S5PV210: dependency issue,
 S5P_SLEEP is depend on ARM_CPU_SUSPEND
In-Reply-To: <51A32FD4.4000001@asianux.com>
References: <5199E4AF.7040607@asianux.com> <51A32FD4.4000001@asianux.com>
Message-ID: <158201ce5ac2$a7843de0$f68cb9a0$%kim@samsung.com>

Chen Gang wrote:
> 
> Hello Maintainers:
> 
Hi,

> Please help check this patch whether OK, when you have time.
> 
> 
> Thanks.
> 
> On 05/20/2013 04:54 PM, Chen Gang wrote:
> >
> > When randconfig with MMU for arm s5pv210 (and select all cpu type),
> > need let S5P_SLEEP depend on ARM_CPU_SUSPEND, or will cause issue below:
> >
> >   arch/arm/plat-samsung/built-in.o: In function `s3c_cpu_resume':
> >   arch/arm/plat-samsung/s5p-sleep.S:83: undefined reference to
> `cpu_resume'
> >
> >
> > Signed-off-by: Chen Gang <gang.chen at asianux.com>
> > ---
> >  arch/arm/plat-samsung/Kconfig |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-
> samsung/Kconfig
> > index f8ed2de..1d38541 100644
> > --- a/arch/arm/plat-samsung/Kconfig
> > +++ b/arch/arm/plat-samsung/Kconfig
> > @@ -483,6 +483,7 @@ config S5P_PM
> >
> >  config S5P_SLEEP
> >  	bool
> > +	select ARM_CPU_SUSPEND

Probably,

+	select ARM_CPU_SUSPEND if PM ?

selecting the S5P_SLEEP depends on PM though...

- Kukjin



From sebastian.hesselbarth at gmail.com  Mon May 27 06:24:07 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 27 May 2013 12:24:07 +0200
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <1369647565.3557.28.camel@pasglop>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130525.210441.818472895703230779.davem@davemloft.net>
 <51A26B62.4050009@gmail.com>
 <20130527.022339.791886107453761860.davem@davemloft.net>
 <1369647565.3557.28.camel@pasglop>
Message-ID: <51A33447.80305@gmail.com>

On 05/27/13 11:39, Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-27 at 02:23 -0700, David Miller wrote:
>> Sparc has an of_set_property(), it needs to become generic.
>
> There is an of_update_property(), we could change the name though, yours
> is nicer :-)

Ben, David,

I had a quick look at sparc's of_set_property. Nothing special except it
depends on OF_DYNAMIC at some place. Using of_update_property instead
should be the correct function to use. Thanks for the hint, I'll update
the patches accordingly and send v5 hopefully by today.

Sebastian



From arnd at arndb.de  Mon May 27 06:31:40 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 12:31:40 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
Message-ID: <201305271231.40693.arnd@arndb.de>

On Monday 27 May 2013, Daniel Tang wrote:
> > The one remaining bit that sticks out is the clcd platform data. As I
> > said before, I won't require you to convert that to DT in order to
> > get your code merged, but I'd also really like to see that happen,
> > as we will also need that to get rid of auxdata on the ARM reference
> > platforms (integrator, versatile, realview, vexpress).
> 
> How would you like me to convert the platform data to DT? AFAIK, the clcd
> driver isn't aware of DT so the only way is to use the AUXDATA right now.

Linus Walleij mentioned on IRC that Pawel Moll already posted a series
that adds DT support for clcd:

http://lists.freedesktop.org/archives/dri-devel/2013-April/037519.html

The series does a few more things, but you can probbly split out the
parts you need and base on that.

	Arnd


From arnd at arndb.de  Mon May 27 06:32:03 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 12:32:03 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
Message-ID: <201305271232.03644.arnd@arndb.de>

On Monday 27 May 2013, Daniel Tang wrote:
> > On Saturday 25 May 2013, Daniel Tang wrote:

> > The one remaining bit that sticks out is the clcd platform data. As I
> > said before, I won't require you to convert that to DT in order to
> > get your code merged, but I'd also really like to see that happen,
> > as we will also need that to get rid of auxdata on the ARM reference
> > platforms (integrator, versatile, realview, vexpress).
> 
> How would you like me to convert the platform data to DT? AFAIK, the
> clcd driver isn't aware of DT so the only way is to use the AUXDATA right now.

There are two basica approaches we could take:

a) add DT support to the clcd driver, using the of_get_videomode()
helper and any other properties that need to be added.

b) add a new KMS driver for this hardware that can be used as an
alternative to the existing one and that works with DT.

	Arnd


From alexandre.belloni at free-electrons.com  Mon May 27 06:37:15 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 12:37:15 +0200
Subject: [PATCH v2] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <20130527080909.GB2919@ludovic.desroches@atmel.com>
References: <1369467542-25519-1-git-send-email-alexandre.belloni@free-electrons.com>
 <20130525200557.GO24476@game.jcrosoft.org>
 <20130527080909.GB2919@ludovic.desroches@atmel.com>
Message-ID: <51A3375B.3090205@free-electrons.com>

On 27/05/2013 10:09, Ludovic Desroches wrote:
> On Sat, May 25, 2013 at 10:05:57PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 09:39 Sat 25 May     , Alexandre Belloni wrote:
>>> Fixes:
>>> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
>>> :(.text+0x1174): undefined reference to `mdiobus_write'
>>> :(.text+0x1188): undefined reference to `mdiobus_write'
>>> :(.text+0x119c): undefined reference to `mdiobus_write'
>>> :(.text+0x11b0): undefined reference to `mdiobus_write'
>>> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
>>> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
>>>
>>> when CONFIG_PHYLIB is not selected.
> Signed-off-by missing.
>
> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>

I'll send a v3...

>>> ---
>>> Changes in v2:
>>> 	use IS_BUILTIN
>>> 	use CONFIG_PHYLIB and not CONFIG_PHY
>>>
>> I do not like this, I prefer we just drop the fixup by adding the dt support
>> to the micrel phy as done for broadcom
>>
> Yes it will be a better solution but we don't have it. Even if we add dt
> support for micrel phy it won't go into 3.10 so it has to be fixed before the
> release.

The fixup is also done like that on i.mx6. I think we'll have to stick
to that for now.

>> if !PHYLIB just add an inline declaration of 
>> phy_register_fixup_for_uid
>>
>> so gcc will drop ksz9021rn_phy_fixup automatically

By using IS_BUILTIN, gcc is already optimizing out the offeding lines,
else you would still get the linking error.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From inki.dae at samsung.com  Mon May 27 06:38:24 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Mon, 27 May 2013 19:38:24 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
Message-ID: <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>

Hi all,

I have been removed previous branch and added new one with more cleanup.
This time, the fence helper doesn't include user side interfaces and cache
operation relevant codes anymore because not only we are not sure that
coupling those two things, synchronizing caches and buffer access between
CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is a
good idea yet but also existing codes for user side have problems with badly
behaved or crashing userspace. So this could be more discussed later.

The below is a new branch,
	
https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/?h=dma-f
ence-helper

And fence helper codes,
	
https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005

And example codes for device driver,
	
https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae

I think the time is not yet ripe for RFC posting: maybe existing dma fence
and reservation need more review and addition work. So I'd glad for somebody
giving other opinions and advices in advance before RFC posting.

Thanks,
Inki Dae



From plagnioj at jcrosoft.com  Mon May 27 06:26:03 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 27 May 2013 12:26:03 +0200
Subject: [PATCH v2 2/4] mtd: atmel_nand: add Nand Flash Controller
 (NFC) support
In-Reply-To: <51A32DD2.9040707@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-3-git-send-email-josh.wu@atmel.com>
 <20130524200947.GM24476@game.jcrosoft.org>
 <51A32DD2.9040707@atmel.com>
Message-ID: <20130527102603.GR24476@game.jcrosoft.org>

On 17:56 Mon 27 May     , Josh Wu wrote:
> Hi, Jean-Christophe PLAGNIOL-VILLARD
> 
> Thank you for your review comments. See my comment in below.
> 
> On 5/25/2013 4:09 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >On 17:51 Fri 17 May     , Josh Wu wrote:
> >>Nand Flash Controller (NFC) can handle automatic transfers, sending the
> >>commands and address cycles to the NAND Flash.
> >>
> >>To use NFC in this driver, the user needs to set the address and size of
> >>NFC command registers, NFC registers (embedded in HSMC) and NFC SRAM in dts.
> >>Also user need to set up the HSMC irq, which use to check whether nfc
> >>command is finish or not.
> >>
> >>This driver has been tested on SAMA5D3X-EK board with JFFS2, YAFFS,
> >>UBIFS and mtd-utils.
> >>
> >>I put the part of the mtd_speedtest result here for your information.
> >> From the mtd_speedtest, we can see the NFC will reduce the %50 of cpu load
> >>when writing nand flash. No change when reading.
> >>In the meantime, the speed will be slow about %8.
> >>
> >>- commands use to test:
> >>     #insmod /mnt/mtd_speedtest.ko dev=2 &
> >>     #top -n 30 -d 1 | grep speedtest
> >>
> >>- test result:
> >>
> >>Before the patch:
> >>=================================================
> >>mtd_speedtest: MTD device: 2
> >>mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
> >>   515   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  99% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: eraseblock write speed is 5768 KiB/s
> >>mtd_speedtest: testing eraseblock read speed
> >>   515   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: eraseblock read speed is 5932 KiB/s
> >>mtd_speedtest: testing page write speed
> >>   515   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  98% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: page write speed is 5770 KiB/s
> >>mtd_speedtest: testing page read speed
> >>   515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
> >>   515   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: page read speed is 5910 KiB/s
> >>
> >>After the patch:
> >>=================================================
> >>mtd_speedtest: MTD device: 2
> >>mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
> >>mtd_speedtest: testing eraseblock write speed
> >>   509   495 root     D     1164   0%  49% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: eraseblock write speed is 5370 KiB/s
> >>mtd_speedtest: testing eraseblock read speed
> >>   509   495 root     R     1164   0%  92% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     R     1164   0%  91% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     R     1164   0%  95% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: eraseblock read speed is 5715 KiB/s
> >>mtd_speedtest: testing page write speed
> >>   509   495 root     D     1164   0%  48% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     D     1164   0%  47% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     D     1164   0%  50% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: page write speed is 5224 KiB/s
> >>mtd_speedtest: testing page read speed
> >>   509   495 root     R     1164   0%  89% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     R     1164   0%  94% insmod /mnt/mtd_speedtest.ko dev=2
> >>   509   495 root     R     1164   0%  93% insmod /mnt/mtd_speedtest.ko dev=2
> >>mtd_speedtest: page read speed is 5641 KiB/s
> >>
> >>Signed-off-by: Josh Wu <josh.wu at atmel.com>
> >>---
> >>v1 --> v2:
> >>   remove the useless nand commands: NAND_CMD_STATUS_ERRORx, NAND_CMD_DEPLETE1.
> >>
> >>  .../devicetree/bindings/mtd/atmel-nand.txt         |    3 +
> >>  drivers/mtd/nand/atmel_nand.c                      |  373 ++++++++++++++++++--
> >>  drivers/mtd/nand/atmel_nand_nfc.h                  |  106 ++++++
> >>  3 files changed, 454 insertions(+), 28 deletions(-)
> >>  create mode 100644 drivers/mtd/nand/atmel_nand_nfc.h
> >>
> >>diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> >>index d555421..88e3313 100644
> >>--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> >>+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> >>@@ -6,6 +6,8 @@ Required properties:
> >>  	and hardware ECC controller if available.
> >>  	If the hardware ECC is PMECC, it should contain address and size for
> >>  	PMECC, PMECC Error Location controller and ROM which has lookup tables.
> >>+	If hardware supports Nand Flash Controller, it should contain address and
> >>+	size for NFC command registers, NFC registers and NFC Sram.
> >>  - atmel,nand-addr-offset : offset for the address latch.
> >>  - atmel,nand-cmd-offset : offset for the command latch.
> >>  - #address-cells, #size-cells : Must be present if the device has sub-nodes
> >>@@ -29,6 +31,7 @@ Optional properties:
> >>    sector size 1024.
> >>  - nand-bus-width : 8 or 16 bus width if not present 8
> >>  - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
> >>+- atmel,has-nfc: boolean to enable Nand Flash Controller(NFC).
> >yes but you need to update the compatible or check the IP support it too
> >as has-nfc will mean I have the nfs on the hardware but not enable it
> >
> >the SoC dtsi will describe you have it but the board will decide to enable it or
> >not
> 
> I can add some code to check whether is NFC supported by read SMC IP
> version. But I'm afraid
> such code may not work for AVR arch.
> 
> Another way is just add a 'enable-nfc' compatible string. Which is
> for board to enable the NFC feature.
> 
> I'm prefer to the later one. What do you think?

I do not like no 2

I like this

		nand0: nand at 60000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = < 0x60000000 0x01000000   /* EBI CS3 */
				0xffffc070 0x00000490   /* SMC PMECC regs */
				0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
				0x00100000 0x00100000   /* ROM code */
				>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand0_ale_cle>;
			atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
			status = "disabled";

			nfc at 70000000 {
				compatible = "atmel,sama5d3-nfc";
				reg = < 0x70000000 0x10000000   /* NFC Command Registers */
					0xffffc000 0x00000070   /* NFC HSMC regs */
					0x00200000 0x00100000   /* NFC SRAM banks */
				>;
			}
		};

so you can enable/disable it easly


> 
> >>  Examples:
> >>  nand0: nand at 40000000,0 {
> >>diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> >>index f747791..48d7ee6 100644
> >>--- a/drivers/mtd/nand/atmel_nand.c
> >>+++ b/drivers/mtd/nand/atmel_nand.c
> >>@@ -18,6 +18,9 @@
> >>   *  Add Programmable Multibit ECC support for various AT91 SoC
> >>   *     ? Copyright 2012 ATMEL, Hong Xu
> >>   *
> >>+ *  Add Nand Flash Controller support for SAMA5 SoC
> >>+ *     ? Copyright 2013 ATMEL, Josh Wu (josh.wu at atmel.com)
> >>+ *
> >>   * This program is free software; you can redistribute it and/or modify
> >>   * it under the terms of the GNU General Public License version 2 as
> >>   * published by the Free Software Foundation.
> >>@@ -37,9 +40,11 @@
> >>  #include <linux/mtd/nand.h>
> >>  #include <linux/mtd/partitions.h>
> >>+#include <linux/delay.h>
> >>  #include <linux/dmaengine.h>
> >>  #include <linux/gpio.h>
> >>  #include <linux/io.h>
> >>+#include <linux/interrupt.h>
> >>  #include <linux/platform_data/atmel.h>
> >>  #include <linux/pinctrl/consumer.h>
> >>@@ -58,6 +63,7 @@ module_param(on_flash_bbt, int, 0);
> >>  	__raw_writel((value), add + ATMEL_ECC_##reg)
> >>  #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
> >>+#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
> >>  /* oob layout for large page size
> >>   * bad block info is on bytes 0 and 1
> >>@@ -85,6 +91,13 @@ static struct nand_ecclayout atmel_oobinfo_small = {
> >>  	},
> >>  };
....
> >>+				dev_err(&pdev->dev,
> >>+					"can't request input direction rdy gpio %d\n",
> >>+					host->board.rdy_pin);
> >>+				goto err_ecc_ioremap;
> >>+			}
> >>+
> >>+			nand_chip->dev_ready = atmel_nand_device_ready;
> >>  		}
> >>-		res = gpio_direction_output(host->board.enable_pin, 1);
> >>-		if (res < 0) {
> >>-			dev_err(&pdev->dev,
> >>-				"can't request output direction enable gpio %d\n",
> >>-				host->board.enable_pin);
> >>-			goto err_ecc_ioremap;
> >>+		if (gpio_is_valid(host->board.enable_pin)) {
> >>+			res = gpio_request(host->board.enable_pin,
> >we need to use devm_ here too
> >and everywhere we can in this driver
> 
> yes, but seems you already sent one patch to use devm_ for this driver.
> https://patchwork.kernel.org/patch/1589071/
> It is not merged in at91 tree yet.
> 
> So what do you think if I put that patch rebased and put it as one
> of this NFC series patches?

yes do so

Best Regards,
J.


From linus.walleij at linaro.org  Mon May 27 06:41:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 12:41:04 +0200
Subject: [PATCH 7/7] Documentation: Update binding for Nomadik and DBx5x
 based platforms
In-Reply-To: <1369232581-18923-8-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYyZZSy4VgFc+Uo=5iAF++EPmHM0U2pHcLdkDZc=Xb_sQ@mail.gmail.com>

On Wed, May 22, 2013 at 4:23 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Change compatible string to something more standard.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
> index 9a2f3f4..c3d8a89 100644
> --- a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
> @@ -1,8 +1,8 @@
>  ST Ericsson Nomadik pinmux controller
>
>  Required properties:
> -- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
> -              "stericsson,nmk-pinctrl-stn8815"
> +- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
> +              "stericsson,stn8815-pinctrl"

OK...

>         pinctrl at 80157000 {
> -               compatible = "stericsson,nmk-pinctrl";
> +               compatible = "stericsson,u8500-pinctrl";

This does not look like a supported compatible string?

Yours,
Linus Walleij


From vinod.koul at intel.com  Mon May 27 06:03:57 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Mon, 27 May 2013 15:33:57 +0530
Subject: [PATCH v7 0/2] dma: imx-dma: OFTree support
In-Reply-To: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
References: <1369562001-11494-1-git-send-email-mpa@pengutronix.de>
Message-ID: <20130527100357.GA30200@intel.com>

On Sun, May 26, 2013 at 11:53:19AM +0200, Markus Pargmann wrote:
> Hi,
> 
> this series adds support for the generic DMA DT bindings for imx-dma.
> 
> Regards,
> 
> Markus
> 
> 
> Changes in v7:
>  - rebased onto v3.10-rc2
Applied thanks...

--
~Vinod
> 
> Markus Pargmann (2):
>       dma: imx-dma: Add oftree support
>       DMA: imx-dma: imxdma->dev used uninitialized
> 
>  .../devicetree/bindings/dma/fsl-imx-dma.txt        | 48 ++++++++++++++
>  drivers/dma/imx-dma.c                              | 77 +++++++++++++++++++++-
>  include/linux/platform_data/dma-imx.h              |  6 +-
>  3 files changed, 126 insertions(+), 5 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
> 


From linus.walleij at linaro.org  Mon May 27 06:43:24 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 12:43:24 +0200
Subject: [PATCH 0/7] ARM: ux500: Change naming convention for pinctrl
In-Reply-To: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYWVSriZZ5grQJ-9XM6JF2NjpeXiKrE1uCYU0KpVT80sg@mail.gmail.com>

On Wed, May 22, 2013 at 4:22 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Our naming convention started off sensibly, but with the addition of
> more supported platforms it's slipped a little. Most compatible strings
> standardise themselves with "<vendor>,<device_name>-<device_type>",
> which we had initially with "stericsson,nmk-pinctrl", but with more
> devices to support we now have a tail, so we are using
> "<vendor>,<driver_name>-<device_type>-<device_name>", which is
> unsuitable.
>
> This patch-set ensures the standard convention is used again.

I buy this. I have applied patches 1, 4 and 6 to the ux500-devicetree
branch. I will apply the remaining patches to the Nomadik branch
(which is in another tree).

There might be some trivial conflict in drivers/pinctrl/pinctrl-nomadik.c
as a result of this being split in two trees but it'll be manageable
I think (will be resolved in ARM SoC).

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 27 06:45:04 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 12:45:04 +0200
Subject: [PATCH v2] ARM: ux500: Apply other compatible name to the u8540
 DTS file
In-Reply-To: <20130522144957.GA18714@gmail.com>
References: <1369233402-19225-1-git-send-email-lee.jones@linaro.org>
 <20130522144957.GA18714@gmail.com>
Message-ID: <CACRpkda_mcNYB8iqE8Pvxp_pQZejGvdXQRxiL1QMO5vZcGgMhg@mail.gmail.com>

On Wed, May 22, 2013 at 4:49 PM, Lee Jones <lee.jones at linaro.org> wrote:

> ARM: ux500: Apply other compatible name to the u8540 DTS file
>
> Devices in board DTS files are usually searchable by multiple
> compatible strings. In this case the 8540 based SoC should be
> obtainable via the chipset [DB8540 & AB8540] name 'u8540' or
> the board name 'ccu8540'. It's already possible to obtain the
> Device Tree via its chipset name, this patch makes it possible
> to get it by its board name too.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Thanks!
Linus Walleij


From alexandre.belloni at free-electrons.com  Mon May 27 06:48:22 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 12:48:22 +0200
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
Message-ID: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>

Fixes:
arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'

when CONFIG_PHYLIB is not selected.

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
Changes in v3:
	added SoB
	added Acked-By

Changes in v2:
	use IS_BUILTIN
	use CONFIG_PHYLIB and not CONFIG_PHY

 arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..e9ce541 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 #define GMII_ERCR	11
 #define GMII_ERDWR	12
 
-	/* Set delay values */
-	value = GMII_RCCPSR | 0x8000;
-	phy_write(phy, GMII_ERCR, value);
-	value = 0xF2F4;
-	phy_write(phy, GMII_ERDWR, value);
-	value = GMII_RRDPSR | 0x8000;
-	phy_write(phy, GMII_ERCR, value);
-	value = 0x2222;
-	phy_write(phy, GMII_ERDWR, value);
+	if (IS_BUILTIN(CONFIG_PHYLIB)) {
+		/* Set delay values */
+		value = GMII_RCCPSR | 0x8000;
+		phy_write(phy, GMII_ERCR, value);
+		value = 0xF2F4;
+		phy_write(phy, GMII_ERDWR, value);
+		value = GMII_RRDPSR | 0x8000;
+		phy_write(phy, GMII_ERCR, value);
+		value = 0x2222;
+		phy_write(phy, GMII_ERDWR, value);
+	}
 
 	return 0;
 }
 
 static void __init sama5_dt_device_init(void)
 {
-	if (of_machine_is_compatible("atmel,sama5d3xcm"))
+	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 			ksz9021rn_phy_fixup);
 
-- 
1.8.1.2



From gang.chen at asianux.com  Mon May 27 06:49:55 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 18:49:55 +0800
Subject: [PATCH] ARM: S5PV210: dependency issue, S5P_SLEEP is depend on
 ARM_CPU_SUSPEND
In-Reply-To: <158201ce5ac2$a7843de0$f68cb9a0$%kim@samsung.com>
References: <5199E4AF.7040607@asianux.com> <51A32FD4.4000001@asianux.com>
 <158201ce5ac2$a7843de0$f68cb9a0$%kim@samsung.com>
Message-ID: <51A33A53.1050502@asianux.com>

On 05/27/2013 06:12 PM, Kukjin Kim wrote:
>>>  config S5P_SLEEP
>>> > >  	bool
>>> > > +	select ARM_CPU_SUSPEND
> Probably,
> 
> +	select ARM_CPU_SUSPEND if PM ?
> 
> selecting the S5P_SLEEP depends on PM though...

After reference another platform, they are really all "select
ARM_CPU_SUSPEND if PM", we'd really better to follow by to let readers
easy understanding.

I will send patch v2.


Thanks.
-- 
Chen Gang

Asianux Corporation


From linus.walleij at linaro.org  Mon May 27 06:53:14 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 12:53:14 +0200
Subject: [RFC PATCHv4 4/6] clocksource: TI-Nspire timer support
In-Reply-To: <1369480087-24786-5-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-5-git-send-email-dt.tangr@gmail.com>
Message-ID: <CACRpkda4Qe1e+dkcSgPLf5dcHASvOG=Y=Dvrnv=oGnon+FRzzg@mail.gmail.com>

On Sat, May 25, 2013 at 1:08 PM, Daniel Tang <dt.tangr at gmail.com> wrote:

> Add clocksource and clockevent driver for the TI-Nspire.
>
> Signed-off-by: Daniel Tang <dt.tangr at gmail.com>

This is *much* improved :-D

But:

> +++ b/drivers/clocksource/zevio-timer.c

> +static void zevio_timer_set_mode(enum clock_event_mode mode,
> +               struct clock_event_device *dev)
> +{
> +       unsigned long flags;
> +       struct zevio_timer *timer = container_of(dev,
> +                       struct zevio_timer,
> +                       clkevt);
> +
> +       local_irq_save(flags);
> +
> +       switch (mode) {
> +       case CLOCK_EVT_MODE_PERIODIC:
> +               /* Unsupported */
> +               break;
> +       case CLOCK_EVT_MODE_RESUME:
> +       case CLOCK_EVT_MODE_ONESHOT:
> +               /* Enable timer interrupts */
> +               writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
> +               writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
> +               dev->mode = mode;
> +               break;
> +       case CLOCK_EVT_MODE_SHUTDOWN:
> +       case CLOCK_EVT_MODE_UNUSED:
> +               /* Disable timer interrupts */
> +               writel(0, timer->interrupt_regs + IO_INTR_MSK);
> +               writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
> +               /* Stop timer */
> +               writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
> +               dev->mode = mode;
> +               break;
> +       }

Surely both the compiler and checkpatch is complaining that this
switch does not contain a default: clause?

If you fix this you can add my:
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From dt.tangr at gmail.com  Mon May 27 06:56:24 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Mon, 27 May 2013 20:56:24 +1000
Subject: [RFC PATCHv4 4/6] clocksource: TI-Nspire timer support
In-Reply-To: <CACRpkda4Qe1e+dkcSgPLf5dcHASvOG=Y=Dvrnv=oGnon+FRzzg@mail.gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-5-git-send-email-dt.tangr@gmail.com>
 <CACRpkda4Qe1e+dkcSgPLf5dcHASvOG=Y=Dvrnv=oGnon+FRzzg@mail.gmail.com>
Message-ID: <69E1F2A1-CD4C-4B16-8664-6010C7217B8B@gmail.com>


On 27/05/2013, at 8:53 PM, Linus Walleij <linus.walleij at linaro.org> wrote:

> On Sat, May 25, 2013 at 1:08 PM, Daniel Tang <dt.tangr at gmail.com> wrote:
> 
>> Add clocksource and clockevent driver for the TI-Nspire.
>> 
>> Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
> 
> This is *much* improved :-D

Awesome!

>> +               /* Disable timer interrupts */
>> +               writel(0, timer->interrupt_regs + IO_INTR_MSK);
>> +               writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
>> +               /* Stop timer */
>> +               writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
>> +               dev->mode = mode;
>> +               break;
>> +       }
> 
> Surely both the compiler and checkpatch is complaining that this
> switch does not contain a default: clause?

Neither in fact. checkpatch.pl gives me a all-clear.

But, I'll clean it up anyway - seems cleaner that way XD.

> 
> If you fix this you can add my:
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Yours,
> Linus Walleij

Cheers,
Daniel Tang

From gang.chen at asianux.com  Mon May 27 06:57:35 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Mon, 27 May 2013 18:57:35 +0800
Subject: [PATCH v2] arch: arm: plat-samsung: dependency, S5P_SLEEP depends
 on ARM_CPU_SUSPEND
In-Reply-To: <51A33A53.1050502@asianux.com>
References: <5199E4AF.7040607@asianux.com> <51A32FD4.4000001@asianux.com>
 <158201ce5ac2$a7843de0$f68cb9a0$%kim@samsung.com>
 <51A33A53.1050502@asianux.com>
Message-ID: <51A33C1F.3000804@asianux.com>


When randconfig with MMU for arm s5pv210 (and select all cpu type),
need let S5P_SLEEP depend on ARM_CPU_SUSPEND, or will cause issue below:

  arch/arm/plat-samsung/built-in.o: In function `s3c_cpu_resume':
  arch/arm/plat-samsung/s5p-sleep.S:83: undefined reference to `cpu_resume'


Signed-off-by: Chen Gang <gang.chen at asianux.com>
---
 arch/arm/plat-samsung/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de..b388d93 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -483,6 +483,7 @@ config S5P_PM
 
 config S5P_SLEEP
 	bool
+	select ARM_CPU_SUSPEND if PM
 	help
 	  Internal config node to apply common S5P sleep management code.
 	  Can be selected by S5P and newer SoCs with similar sleep procedure.
-- 
1.7.7.6


From daniel.lezcano at linaro.org  Mon May 27 07:03:31 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Mon, 27 May 2013 13:03:31 +0200
Subject: [PATCH 10/12] ARM: shmobile: r8a7740: Add CPUIdle
In-Reply-To: <1369645193-3595-11-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-11-git-send-email-horms+renesas@verge.net.au>
Message-ID: <51A33D83.905@linaro.org>

On 05/27/2013 10:59 AM, Simon Horman wrote:
> From: Bastian Hecht <hechtb at gmail.com>
> 
> We make use of the r8a7740 Suspend To Ram code to plug together a
> CPUIdle driver.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---

Shouldn't it go through Rafael's tree ? Or does the patch contains some
dependencies on a code only visible in the ARM tree ?

>  arch/arm/mach-shmobile/Makefile               |    2 +-
>  arch/arm/mach-shmobile/cpuidle-r8a7740.c      |   62 +++++++++++++++++++++++++
>  arch/arm/mach-shmobile/include/mach/r8a7740.h |    1 +
>  arch/arm/mach-shmobile/pm-r8a7740.c           |    1 +
>  4 files changed, 65 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-shmobile/cpuidle-r8a7740.c
> 
> diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
> index 0568894..2852dcf 100644
> --- a/arch/arm/mach-shmobile/Makefile
> +++ b/arch/arm/mach-shmobile/Makefile
> @@ -30,7 +30,7 @@ obj-$(CONFIG_SUSPEND)		+= suspend.o
>  obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
>  obj-$(CONFIG_ARCH_SHMOBILE)	+= pm-rmobile.o
>  obj-$(CONFIG_ARCH_SH7372)	+= pm-sh7372.o sleep-sh7372.o
> -obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o sleep-r8a7740.o
> +obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o sleep-r8a7740.o cpuidle-r8a7740.o
>  obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
>  obj-$(CONFIG_ARCH_SH73A0)	+= pm-sh73a0.o
>  
> diff --git a/arch/arm/mach-shmobile/cpuidle-r8a7740.c b/arch/arm/mach-shmobile/cpuidle-r8a7740.c
> new file mode 100644
> index 0000000..48c7a6c
> --- /dev/null
> +++ b/arch/arm/mach-shmobile/cpuidle-r8a7740.c
> @@ -0,0 +1,62 @@
> +/*
> + * CPUIdle code for SoC r8a7740
> + *
> + * Copyright (C) 2013 Bastian Hecht
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + */
> +#include <linux/cpuidle.h>
> +#include <linux/module.h>
> +#include <asm/cpuidle.h>
> +#include <mach/common.h>
> +#include <mach/r8a7740.h>
> +
> +#if defined(CONFIG_SUSPEND) && defined(CONFIG_CPU_IDLE)
> +static int r8a7740_enter_a3sm_pll_on(struct cpuidle_device *dev,
> +					struct cpuidle_driver *drv, int index)
> +{
> +	r8a7740_enter_a3sm_common(1);
> +	return 1;
> +}
> +
> +static int r8a7740_enter_a3sm_pll_off(struct cpuidle_device *dev,
> +					struct cpuidle_driver *drv, int index)
> +{
> +	r8a7740_enter_a3sm_common(0);
> +	return 2;
> +}
> +
> +static struct cpuidle_driver r8a7740_cpuidle_driver = {
> +	.name			= "r8a7740_cpuidle",
> +	.owner			= THIS_MODULE,
> +	.en_core_tk_irqen	= 1,
> +	.state_count		= 3,
> +	.safe_state_index	= 0, /* C1 */
> +	.states[0] = ARM_CPUIDLE_WFI_STATE,
> +	.states[1] = {
> +		.name = "C2",
> +		.desc = "A3SM PLL ON",
> +		.exit_latency = 40,
> +		.target_residency = 30 + 40,
> +		.flags = CPUIDLE_FLAG_TIME_VALID,
> +		.enter = r8a7740_enter_a3sm_pll_on,
> +	},
> +	.states[2] = {
> +		.name = "C3",
> +		.desc = "A3SM PLL OFF",
> +		.exit_latency = 120,
> +		.target_residency = 30 + 120,
> +		.flags = CPUIDLE_FLAG_TIME_VALID,
> +		.enter = r8a7740_enter_a3sm_pll_off,
> +	},
> +};
> +
> +void r8a7740_cpuidle_init(void)
> +{
> +	shmobile_cpuidle_set_driver(&r8a7740_cpuidle_driver);
> +}
> +#else
> +void r8a7740_cpuidle_init(void) {}
> +#endif
> diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
> index 5cfe5d9..3b538e3 100644
> --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
> +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
> @@ -545,6 +545,7 @@ extern void r8a7740_pinmux_init(void);
>  extern void r8a7740_pm_init(void);
>  extern void r8a7740_resume(void);
>  extern void r8a7740_shutdown(void);
> +extern void r8a7740_cpuidle_init(void);
>  extern void r8a7740_enter_a3sm_common(int);
>  
>  #ifdef CONFIG_PM
> diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
> index fe3c867..2f196bd 100644
> --- a/arch/arm/mach-shmobile/pm-r8a7740.c
> +++ b/arch/arm/mach-shmobile/pm-r8a7740.c
> @@ -237,4 +237,5 @@ static void r8a7740_suspend_init(void) {}
>  void __init r8a7740_pm_init(void)
>  {
>  	r8a7740_suspend_init();
> +	r8a7740_cpuidle_init();
>  }
> 


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog



From linus.walleij at linaro.org  Mon May 27 07:10:47 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:10:47 +0200
Subject: [PATCH 1/6] ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices
In-Reply-To: <1369314830-3727-2-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-2-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdYisqexALz8sKrLQsCHxn9Z8TeShXOdTTv_TUZudBByKg@mail.gmail.com>

On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> We are able to cope with an SDMMC clock of 100MHz so let's
> make use of the full frequency instead of the half.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Patch applied to my ux500-core changes tree.

Yours,
Linus Walleij


From florian.vaussard at epfl.ch  Mon May 27 07:11:11 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 13:11:11 +0200
Subject: [PATCH v2 5/5] ARM: dts: OMAP2+: use pinctrl constants
In-Reply-To: <20130523184636.GE13507@atomide.com>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
 <1369323421-4180-6-git-send-email-florian.vaussard@epfl.ch>
 <20130523184636.GE13507@atomide.com>
Message-ID: <51A33F4F.5010501@epfl.ch>

Hello Tony,

Thanks for your review.

On 05/23/2013 08:46 PM, Tony Lindgren wrote:
> * Florian Vaussard <florian.vaussard at epfl.ch> [130523 08:42]:
>> index f39b237..b3cc896 100644
>> --- a/arch/arm/boot/dts/omap2.dtsi
>> +++ b/arch/arm/boot/dts/omap2.dtsi
>> @@ -9,6 +9,7 @@
>>    */
>>
>>   #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/pinctrl/omap.h>
>>
>>   #include "skeleton.dtsi"
>>
>> diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
>> index 434288f..2518e6a 100644
>> --- a/arch/arm/boot/dts/omap3-beagle.dts
>> +++ b/arch/arm/boot/dts/omap3-beagle.dts
>> @@ -81,18 +81,18 @@
>>
>>   	hsusbb2_pins: pinmux_hsusbb2_pins {
>>   		pinctrl-single,pins = <
>> -			0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
>> -			0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
>> -			0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
>> -			0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
>> -			0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
>> -			0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
>> -			0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
>> -			0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
>> -			0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
>> -			0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
>> -			0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
>> -			0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
>> +			0x5c0 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk */
>> +			0x5c2 (OMAP_PIN_OUTPUT | OMAP_MUX_MODE3)		/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp */
>> +			0x5c4 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir */
>> +			0x5c6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt */
>> +			0x5c8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 */
>> +			0x5cA (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 */
>> +			0x1a4 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 */
>> +			0x1a6 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 */
>> +			0x1a8 (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 */
>> +			0x1aa (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 */
>> +			0x1ac (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 */
>> +			0x1ae (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE3)	/* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 */
>>   		>;
>>   	};
>>   };
>
> Nice!
>
> While at it, can you lowercase the USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk
> naming to usbb2_ulpittl_clk.usbb1_ulpiphy_clk? You can also leave out _MUXMODE
> from these for consistency.
>

Sure. I will send out a v3 ASAP.

> I wonder if we can leave out the OMAP_ prefix from the mux mode defines
> here and just assume PIN_OUTPUT etc would not conflict with other SoC's
> naming?
>

We can avoid conflicts as long as we do not include two headers from two 
different arch,
which should not happen if designed with care. I will do the change.

Regards,

Florian


From florian.vaussard at epfl.ch  Mon May 27 07:14:52 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 13:14:52 +0200
Subject: [PATCH v2 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <519E3D16.2090003@ti.com>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
 <519E3D16.2090003@ti.com>
Message-ID: <51A3402C.8090103@epfl.ch>

Hello Santosh,

Thank you for your review.

On 05/23/2013 06:00 PM, Santosh Shilimkar wrote:
> On Thursday 23 May 2013 11:36 AM, Florian Vaussard wrote:
>> Hello,
>>
>> Following a similar proposal by Stephen Warren for tegra [1], this series
>> makes use of the C preprocessor when compiling OMAP DT files, and
>> accomplishes some improvements to improve overall readability.
>>
>> Patch 1 is a preparation for the rest of the series.
>> Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
>> IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
>> it to simplify pinctrl DT.
>>
>> For all targets, the .dtb files were diff-tested before and after
>> applying the series to guarantee identity.
>>
>
>>
>> Florian Vaussard (5):
>>    ARM: dts: OMAP2+: use #include for all device trees
>>    ARM: dts: OMAP2+: use existing constants for GPIOs
>>    ARM: dts: OMAP4/5: use existing constants for IRQs
>>    ARM: dts: OMAP2+: header file for pinctrl constants
>>    ARM: dts: OMAP2+: use pinctrl constants
>>
> I just quickly scanned the series and patches looks
> good to my eyes. Its a nice clean-up to align OMAP
> dts files with others.
>
> FWIW,
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>

I will send a v3 with minor changes to address Tony's comments, with
your Ack if ok for you.

Regards,

Florian


From linus.walleij at stericsson.com  Mon May 27 07:19:29 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 27 May 2013 13:19:29 +0200
Subject: [PATCH] ARM: ux500: bump MMC/SD max frequency for DT boots
Message-ID: <1369653569-21855-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

In patch:
"ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices"
the max frequency for the MMC/SD/SDIO adapters was
increased from 50 to 100MHz. Do the same for the
device tree boot path.

Cc: Ulf Hansson <ulf.hansson at linaro.org>
Cc: Lee Jones <lee.jones at linaro.org>
Cc: Gabriel Fernandez <gabriel.fernandez.st at gmail.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ccu9540.dts     | 2 +-
 arch/arm/boot/dts/href.dtsi       | 8 ++++----
 arch/arm/boot/dts/hrefv60plus.dts | 8 ++++----
 arch/arm/boot/dts/snowball.dts    | 4 ++--
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
index c72d7aa..b657d71 100644
--- a/arch/arm/boot/dts/ccu9540.dts
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -52,7 +52,7 @@
 		// WLAN SDIO channel
 		sdi1_per2 at 80118000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <4>;
 
 			status = "okay";
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index e315429..567a18b 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -108,7 +108,7 @@
 		// External Micro SD slot
 		sdi0_per1 at 80126000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <4>;
 			mmc-cap-sd-highspeed;
 			mmc-cap-mmc-highspeed;
@@ -123,7 +123,7 @@
 		// WLAN SDIO channel
 		sdi1_per2 at 80118000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <4>;
 
 			status = "okay";
@@ -132,7 +132,7 @@
 		// PoP:ed eMMC
 		sdi2_per3 at 80005000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <8>;
 			mmc-cap-mmc-highspeed;
 
@@ -142,7 +142,7 @@
 		// On-board eMMC
 		sdi4_per2 at 80114000 {
 			arm,primecell-periphid = <0x10480180>;
-		        max-frequency = <50000000>;
+		        max-frequency = <100000000>;
 			bus-width = <8>;
 			mmc-cap-mmc-highspeed;
 			vmmc-supply = <&ab8500_ldo_aux2_reg>;
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 5dfc73a..26f33a6f 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -34,7 +34,7 @@
 		// External Micro SD slot
 		sdi0_per1 at 80126000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <4>;
 			mmc-cap-sd-highspeed;
 			mmc-cap-mmc-highspeed;
@@ -48,7 +48,7 @@
 		// WLAN SDIO channel
 		sdi1_per2 at 80118000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <4>;
 
 			status = "okay";
@@ -57,7 +57,7 @@
 		// PoP:ed eMMC
 		sdi2_per3 at 80005000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <8>;
 			mmc-cap-mmc-highspeed;
 
@@ -67,7 +67,7 @@
 		// On-board eMMC
 		sdi4_per2 at 80114000 {
 			arm,primecell-periphid = <0x10480180>;
-		        max-frequency = <50000000>;
+		        max-frequency = <100000000>;
 			bus-width = <8>;
 			mmc-cap-mmc-highspeed;
 			vmmc-supply = <&ab8500_ldo_aux2_reg>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index e8219cc7..829a65f 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -129,7 +129,7 @@
 		// External Micro SD slot
 		sdi0_per1 at 80126000 {
 			arm,primecell-periphid = <0x10480180>;
-			max-frequency = <50000000>;
+			max-frequency = <100000000>;
 			bus-width = <4>;
 			mmc-cap-mmc-highspeed;
 			vmmc-supply = <&ab8500_ldo_aux3_reg>;
@@ -144,7 +144,7 @@
 		// On-board eMMC
 		sdi4_per2 at 80114000 {
 			arm,primecell-periphid = <0x10480180>;
-		        max-frequency = <50000000>;
+		        max-frequency = <100000000>;
 			bus-width = <8>;
 			mmc-cap-mmc-highspeed;
 			vmmc-supply = <&ab8500_ldo_aux2_reg>;
-- 
1.7.11.3



From linus.walleij at linaro.org  Mon May 27 07:21:03 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:21:03 +0200
Subject: [PATCH 2/6] ARM: ux500: Don't set plf ocr mask for SD/MMC device
In-Reply-To: <1369314830-3727-3-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-3-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdahEueW1Wa6RgMgd48526Q-OkjmiqzW9SK_jF0b2NJGcg@mail.gmail.com>

On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> The mmci host driver overrides platform ocr mask when a vmmc regulator
> can be used. This is the case for sdi0(SD-card) and for sdi4(eMMC).
> Thus it is pointless of specifing these mask and why we do remove them.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

This rids some boot noise as well, thanks!
Patch applied for ux500-core.

Yours,
Linus Walleij


From ulf.hansson at linaro.org  Mon May 27 07:25:31 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Mon, 27 May 2013 13:25:31 +0200
Subject: [PATCH] ARM: ux500: bump MMC/SD max frequency for DT boots
In-Reply-To: <1369653569-21855-1-git-send-email-linus.walleij@stericsson.com>
References: <1369653569-21855-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAPDyKFpETu5mmN6Z0vOA=WVHp05EFoGCinXfZkbKYORcZrx+UQ@mail.gmail.com>

On 27 May 2013 13:19, Linus Walleij <linus.walleij at stericsson.com> wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
>
> In patch:
> "ARM: ux500: Enable 100MHz for SD/SDIO/MMC devices"
> the max frequency for the MMC/SD/SDIO adapters was
> increased from 50 to 100MHz. Do the same for the
> device tree boot path.
>
> Cc: Ulf Hansson <ulf.hansson at linaro.org>
> Cc: Lee Jones <lee.jones at linaro.org>
> Cc: Gabriel Fernandez <gabriel.fernandez.st at gmail.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/ccu9540.dts     | 2 +-
>  arch/arm/boot/dts/href.dtsi       | 8 ++++----
>  arch/arm/boot/dts/hrefv60plus.dts | 8 ++++----
>  arch/arm/boot/dts/snowball.dts    | 4 ++--
>  4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
> index c72d7aa..b657d71 100644
> --- a/arch/arm/boot/dts/ccu9540.dts
> +++ b/arch/arm/boot/dts/ccu9540.dts
> @@ -52,7 +52,7 @@
>                 // WLAN SDIO channel
>                 sdi1_per2 at 80118000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <4>;
>
>                         status = "okay";
> diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
> index e315429..567a18b 100644
> --- a/arch/arm/boot/dts/href.dtsi
> +++ b/arch/arm/boot/dts/href.dtsi
> @@ -108,7 +108,7 @@
>                 // External Micro SD slot
>                 sdi0_per1 at 80126000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <4>;
>                         mmc-cap-sd-highspeed;
>                         mmc-cap-mmc-highspeed;
> @@ -123,7 +123,7 @@
>                 // WLAN SDIO channel
>                 sdi1_per2 at 80118000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <4>;
>
>                         status = "okay";
> @@ -132,7 +132,7 @@
>                 // PoP:ed eMMC
>                 sdi2_per3 at 80005000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <8>;
>                         mmc-cap-mmc-highspeed;
>
> @@ -142,7 +142,7 @@
>                 // On-board eMMC
>                 sdi4_per2 at 80114000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <8>;
>                         mmc-cap-mmc-highspeed;
>                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
> diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
> index 5dfc73a..26f33a6f 100644
> --- a/arch/arm/boot/dts/hrefv60plus.dts
> +++ b/arch/arm/boot/dts/hrefv60plus.dts
> @@ -34,7 +34,7 @@
>                 // External Micro SD slot
>                 sdi0_per1 at 80126000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <4>;
>                         mmc-cap-sd-highspeed;
>                         mmc-cap-mmc-highspeed;
> @@ -48,7 +48,7 @@
>                 // WLAN SDIO channel
>                 sdi1_per2 at 80118000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <4>;
>
>                         status = "okay";
> @@ -57,7 +57,7 @@
>                 // PoP:ed eMMC
>                 sdi2_per3 at 80005000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <8>;
>                         mmc-cap-mmc-highspeed;
>
> @@ -67,7 +67,7 @@
>                 // On-board eMMC
>                 sdi4_per2 at 80114000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <8>;
>                         mmc-cap-mmc-highspeed;
>                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
> diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
> index e8219cc7..829a65f 100644
> --- a/arch/arm/boot/dts/snowball.dts
> +++ b/arch/arm/boot/dts/snowball.dts
> @@ -129,7 +129,7 @@
>                 // External Micro SD slot
>                 sdi0_per1 at 80126000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <4>;
>                         mmc-cap-mmc-highspeed;
>                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
> @@ -144,7 +144,7 @@
>                 // On-board eMMC
>                 sdi4_per2 at 80114000 {
>                         arm,primecell-periphid = <0x10480180>;
> -                       max-frequency = <50000000>;
> +                       max-frequency = <100000000>;
>                         bus-width = <8>;
>                         mmc-cap-mmc-highspeed;
>                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
> --
> 1.7.11.3
>

Acked-by: Ulf Hansson <ulf.hansson at linaro.org>


From plagnioj at jcrosoft.com  Mon May 27 07:26:47 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 27 May 2013 19:26:47 +0800
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <E0B30581-DD0A-46C5-B541-08F389F17018@jcrosoft.com>


On May 27, 2013, at 6:48 PM, Alexandre Belloni <alexandre.belloni at free-electrons.com> wrote:

> Fixes:
> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> :(.text+0x1174): undefined reference to `mdiobus_write'
> :(.text+0x1188): undefined reference to `mdiobus_write'
> :(.text+0x119c): undefined reference to `mdiobus_write'
> :(.text+0x11b0): undefined reference to `mdiobus_write'
> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
> 
> when CONFIG_PHYLIB is not selected.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>

no for this change

add an inline version of phy_register_fixup_for_uid

this will do the same for every platform

> ---
> Changes in v3:
> 	added SoB
> 	added Acked-By
> 
> Changes in v2:
> 	use IS_BUILTIN
> 	use CONFIG_PHYLIB and not CONFIG_PHY
> 
> arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> index 705305e..e9ce541 100644
> --- a/arch/arm/mach-at91/board-dt-sama5.c
> +++ b/arch/arm/mach-at91/board-dt-sama5.c
> @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
> #define GMII_ERCR	11
> #define GMII_ERDWR	12
> 
> -	/* Set delay values */
> -	value = GMII_RCCPSR | 0x8000;
> -	phy_write(phy, GMII_ERCR, value);
> -	value = 0xF2F4;
> -	phy_write(phy, GMII_ERDWR, value);
> -	value = GMII_RRDPSR | 0x8000;
> -	phy_write(phy, GMII_ERCR, value);
> -	value = 0x2222;
> -	phy_write(phy, GMII_ERDWR, value);
> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
> +		/* Set delay values */
> +		value = GMII_RCCPSR | 0x8000;
> +		phy_write(phy, GMII_ERCR, value);
> +		value = 0xF2F4;
> +		phy_write(phy, GMII_ERDWR, value);
> +		value = GMII_RRDPSR | 0x8000;
> +		phy_write(phy, GMII_ERCR, value);
> +		value = 0x2222;
> +		phy_write(phy, GMII_ERDWR, value);
> +	}
> 
> 	return 0;
> }
> 
> static void __init sama5_dt_device_init(void)
> {
> -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
> +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
> 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
> 			ksz9021rn_phy_fixup);
> 
> -- 
> 1.8.1.2
> 



From broonie at opensource.wolfsonmicro.com  Mon May 27 07:29:11 2013
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 May 2013 12:29:11 +0100
Subject: [PATCH] clk: use platform_{get,set}_drvdata()
In-Reply-To: <000401ce581b$a9224600$fb66d200$@samsung.com>
References: <000401ce581b$a9224600$fb66d200$@samsung.com>
Message-ID: <20130527112910.GD21462@opensource.wolfsonmicro.com>

On Fri, May 24, 2013 at 10:11:46AM +0900, Jingoo Han wrote:
> Use the wrapper functions for getting and setting the driver data using
> platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev,
> so we can directly pass a struct platform_device.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From linus.walleij at linaro.org  Mon May 27 07:30:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:30:31 +0200
Subject: [PATCH 3/6] ARM: ux500: Enable support for RPMB and Reliable
 Write for eMMC
In-Reply-To: <1369314830-3727-4-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-4-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdbcQNAUNYnHwLRm2f+LdRmQZY=U9PBk8CPPxONmQFtXmg@mail.gmail.com>

On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> By adding MMC_CAP_CMD23 for the eMMC devices, we can support RPMB
> and Reliable Write. Additionally it will mean CMD12 will not be sent
> to end a successful data transfer.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Patch applied to ux500-core, thanks,
but Houston, we have a problem:

I wanted to enable this also for the device tree boot
path. But currently there are no bindings to state in the
DT boot that CMD23 is supported.

Could you create another patch that:

- Add bindings to Documentation/devicetree/bindings/mmc/mmc.txt
  for indicating that a host controller supports CMD23
- Patch the ux500 DTS files to enable it.
- Write a patch to mmci.c to augment
  mmci_dt_populate_generic_pdata() to read the binding and
  augment the caps from the device tree.

There is also a complicated refactoring that need to happen any
of these days:

- Augment the MMC core and all drivers using DT boots to
  parse any standard caps from the device tree insteaf of
  putting code like mmci_dt_populate_generic_pdata() into
  every driver.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 27 07:32:15 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:32:15 +0200
Subject: [PATCH 4/6] ARM: ux500: Enable support for discard for MMC/SD
In-Reply-To: <1369314830-3727-5-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-5-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdaCgdkrke7wxCCScMBkn7eOxSyTV0dEXzF7eiEqYaE6pA@mail.gmail.com>

On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> By enabling MMC_CAP_ERASE for the SD/MMC devices the mmc block
> layer will now act on DISCARD requests.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Patch applied for ux500-core.

On the DT boot path this has the same problems and
comments as for patch 3: not supported on DT boots.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 27 07:34:09 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:34:09 +0200
Subject: [PATCH 5/6] ARM: ux500: Set eMMC and WLAN card slot as
 non-removable
In-Reply-To: <1369314830-3727-6-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-6-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdbyQwbhoVt0ZU6TBeBtUw7OZQtrNP28B060DJGs5jzDWw@mail.gmail.com>

On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> For several reasons, the mmc protocol layer expects devices
> being non-removable to use MMC_CAP_NONREMOVABLE, so then we
> adapt to this expectation.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Patch applied for ux500-core.

On the DT boot path this has the same problems and comments
as patches 3 & 4.

Yours,
Linus Walleij


From shawn.guo at linaro.org  Mon May 27 07:34:16 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 27 May 2013 19:34:16 +0800
Subject: [PATCH v3] tty: serial: add Freescale lpuart driver support
In-Reply-To: <13F8657A829DAB49A2A937FD6FC10F790B3D644B@039-SN2MPN1-012.039d.mgd.msft.net>
References: <1368685096-13177-1-git-send-email-b35083@freescale.com>
 <20130520030523.GB25113@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3CDB85@039-SN2MPN1-012.039d.mgd.msft.net>
 <CAAQ0ZWRz+byPKxMjDH3zKsc0u4bmkPO_1u6w2H4Z7nD0z8+9ig@mail.gmail.com>
 <13F8657A829DAB49A2A937FD6FC10F790B3CECEB@039-SN2MPN1-012.039d.mgd.msft.net>
 <20130523025059.GB2704@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3D5056@039-SN2MPN1-012.039d.mgd.msft.net>
 <20130527055734.GD7782@S2101-09.ap.freescale.net>
 <13F8657A829DAB49A2A937FD6FC10F790B3D644B@039-SN2MPN1-012.039d.mgd.msft.net>
Message-ID: <20130527113414.GA7737@S2101-09.ap.freescale.net>

On Mon, May 27, 2013 at 09:12:25AM +0000, Jin Zhengxiong-R64188 wrote:
> [Jason Jin-R64188] I think we need to align with the document as it's posted at Freescale website, otherwise, the inconsistency will confuse the customer. 
> please refer to:
> http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=1&sr=5
> http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID
> As the development work is ahead of the formal name posted outside, we continued to use the name for upstreaming patches. Sorry for taking into the confusion. For those patches aren't merged, please help to review them based on the new SoC name.
> 

Okay.

> For the merged FEC patch, we'd like to explain it to the maintainer, Or can we just keep the FEC compatible string as before("fsl, mvf600-fec")? And be aware of it's the equivalent of "fsl,vf610-fec"?
> 

I'm fine with either way.  But if you do want to change it, please
change it as early as possible.

Shawn



From linus.walleij at linaro.org  Mon May 27 07:35:40 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:35:40 +0200
Subject: [PATCH 6/6] ARM: ux500: Enable support for UHS-I SD-cards
In-Reply-To: <1369314830-3727-7-git-send-email-ulf.hansson@stericsson.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-7-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdaNLreLPfCRC6e=2kJ9NXMkNp_V_PEsirMFa+UvztHS5Q@mail.gmail.com>

On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> By setting the host capabilities MMC_CAP_UHS_SDR12|25 for
> the SD card device we enable support for UHS cards. The
> supported mode is SDR12 and SDR25.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Patch applied for ux500-core.

On the DT boot path this patch has the same problems
and comments as patches 3,4,5.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 27 07:37:37 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:37:37 +0200
Subject: [PATCH] ARM: ux500: Provide supplies for AUX1, AUX2 and AUX3
In-Reply-To: <1369394539-3713-1-git-send-email-lee.jones@linaro.org>
References: <1369394539-3713-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZGHNG0uG+vicpQEQ0y61bAM0FTg-wMrZ3SbsW2Owf0PA@mail.gmail.com>

On Fri, May 24, 2013 at 1:22 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch fixes a bug introduced in the v3.10 merge window.
>
> The AB8500 External Regulator driver has recently landed upstream,
> which registers each of the 3 external regulators located on the
> AB8500. If these regulators are marked as 'always on', there is a
> potential for power-loss. If they're not and are seemingly unused
> the Regulator subsystem will attempt to disable them to save power.
> This causes an issue for AUX1, AUX2 and AUX3 as they obtain their
> power from EXT3. So we're specifying that here to prevent EXT3 from
> being powered down.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied for ux500-fixes, thanks!

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon May 27 07:39:07 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:39:07 +0200
Subject: [PATCH] ARM: ux500: regulators: Remove misleading comment
In-Reply-To: <1369227995-17142-1-git-send-email-lee.jones@linaro.org>
References: <1369227995-17142-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYAd=X7rCj+Xs=cQ5CZf3-mpLpiGKjmfVZ+pC_QSq-+Kg@mail.gmail.com>

On Wed, May 22, 2013 at 3:06 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch removes a comment which explains that the ab8505 platform
> uses the same initialisation settings as the ab8500. Well when this
> changed and the ab8505 started using its own set of initialisation
> values, someone forgot to remove it.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied for ux500-core, thanks!

Yours,
Linus Walleij


From rickard.andersson at stericsson.com  Mon May 27 07:40:55 2013
From: rickard.andersson at stericsson.com (Rickard ANDERSSON)
Date: Mon, 27 May 2013 13:40:55 +0200
Subject: [PATCH V2 0/3] mmc: mmci: Support ap_sleep in cpuidle for ux500
In-Reply-To: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <C832F8F5D375BD43BFA11E82E0FE9FE0115A936A54@EXDCVYMBSTM005.EQ1STM.local>

Acked-by: Rickard Andersson <rickard.andersson at stericsson.com>

-----Original Message-----
From: Ulf HANSSON 
Sent: den 23 maj 2013 11:45
To: linux-arm-kernel at lists.infradead.org; Russell King
Cc: linux-mmc at vger.kernel.org; Chris Ball; Daniel Lezcano; Linus Walleij; Rickard ANDERSSON; Ulf Hansson
Subject: [PATCH V2 0/3] mmc: mmci: Support ap_sleep in cpuidle for ux500

From: Ulf Hansson <ulf.hansson at linaro.org>

To be able to enter ap_sleep state in cpuidle were the APE power domain regulator will be cut, a register save and restore mechanism needs to be implemented. This patchset adapts to these restrictions.

Ulf Hansson (3):
  mmc: mmci: Use optional sleep pinctrl state
  mmc: mmci: Adapt to register write restrictions
  mmc: mmci: Save and restore register context

 drivers/mmc/host/mmci.c |   75 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 76 insertions(+)

--
1.7.10



From linus.walleij at linaro.org  Mon May 27 07:44:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 13:44:38 +0200
Subject: [PATCH] ARM: ux500: select SND_SOC_UX500 for ux500
In-Reply-To: <1369402093-27817-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369402093-27817-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <CACRpkdbB7KjzUCf72gqN3ooiWYYkaaPrZUEDeG8HuLk3pTB72A@mail.gmail.com>

On Fri, May 24, 2013 at 3:28 PM, Fabio Baltieri
<fabio.baltieri at linaro.org> wrote:

> Enable ux500 specific ALSA SoC drivers by default on u8500_defconfig.
>
> Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>

Thanks, patch applied to my defconfig branch.

Now I can finally use the Snowball board to run sidplay.

Yours,
Linus Walleij


From benh at kernel.crashing.org  Mon May 27 07:50:04 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Mon, 27 May 2013 21:50:04 +1000
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <51A33447.80305@gmail.com>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130525.210441.818472895703230779.davem@davemloft.net>
 <51A26B62.4050009@gmail.com>
 <20130527.022339.791886107453761860.davem@davemloft.net>
 <1369647565.3557.28.camel@pasglop> <51A33447.80305@gmail.com>
Message-ID: <1369655404.3557.33.camel@pasglop>

On Mon, 2013-05-27 at 12:24 +0200, Sebastian Hesselbarth wrote:
> > There is an of_update_property(), we could change the name though,
> yours
> > is nicer :-)
> 
> Ben, David,
> 
> I had a quick look at sparc's of_set_property. Nothing special except
> it
> depends on OF_DYNAMIC at some place. Using of_update_property instead
> should be the correct function to use. Thanks for the hint, I'll
> update
> the patches accordingly and send v5 hopefully by today.

The only thing is that of_update_property() is a bit awkward to use,
requiring the caller to provide an allocated struct property with
associated allocated content. It also leaks the old property which
is annoying but we haven't sorted out how to deal with allocation
of properties and property content yet.

It would be handy to be able to just do something like

	of_set_property(node, name, ptr, len);

However, that wouldn't help much with the allocation/leak problem,
though at least it would be easier to use. It could also *try* to re-use
the current allocation if the new content is of smaller or equal size.

Cheers,
Ben.




From nicolas.ferre at atmel.com  Mon May 27 08:05:13 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 27 May 2013 14:05:13 +0200
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <51A34BF9.5000905@atmel.com>

On 27/05/2013 12:48, Alexandre Belloni :
> Fixes:
> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> :(.text+0x1174): undefined reference to `mdiobus_write'
> :(.text+0x1188): undefined reference to `mdiobus_write'
> :(.text+0x119c): undefined reference to `mdiobus_write'
> :(.text+0x11b0): undefined reference to `mdiobus_write'
> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
>
> when CONFIG_PHYLIB is not selected.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> ---
> Changes in v3:
> 	added SoB
> 	added Acked-By

A v3 is not needed simply for this. Thanks, anyway!

One question though: why not just add

         select PHYLIB

In Kconfig entry:

  config MACH_SAMA5_DT

?

(note that I like to play with everybody's nerves ;-))

Bye,

> Changes in v2:
> 	use IS_BUILTIN
> 	use CONFIG_PHYLIB and not CONFIG_PHY
>
>   arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
>   1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> index 705305e..e9ce541 100644
> --- a/arch/arm/mach-at91/board-dt-sama5.c
> +++ b/arch/arm/mach-at91/board-dt-sama5.c
> @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
>   #define GMII_ERCR	11
>   #define GMII_ERDWR	12
>
> -	/* Set delay values */
> -	value = GMII_RCCPSR | 0x8000;
> -	phy_write(phy, GMII_ERCR, value);
> -	value = 0xF2F4;
> -	phy_write(phy, GMII_ERDWR, value);
> -	value = GMII_RRDPSR | 0x8000;
> -	phy_write(phy, GMII_ERCR, value);
> -	value = 0x2222;
> -	phy_write(phy, GMII_ERDWR, value);
> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
> +		/* Set delay values */
> +		value = GMII_RCCPSR | 0x8000;
> +		phy_write(phy, GMII_ERCR, value);
> +		value = 0xF2F4;
> +		phy_write(phy, GMII_ERDWR, value);
> +		value = GMII_RRDPSR | 0x8000;
> +		phy_write(phy, GMII_ERCR, value);
> +		value = 0x2222;
> +		phy_write(phy, GMII_ERDWR, value);
> +	}
>
>   	return 0;
>   }
>
>   static void __init sama5_dt_device_init(void)
>   {
> -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
> +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
>   		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
>   			ksz9021rn_phy_fixup);
>
>


-- 
Nicolas Ferre


From jamie at jamieiles.com  Mon May 27 08:07:53 2013
From: jamie at jamieiles.com (Jamie Iles)
Date: Mon, 27 May 2013 13:07:53 +0100
Subject: [PATCH 1/2] clocksource: dw_apb: remove unused header
In-Reply-To: <1369570367-994-1-git-send-email-baruch@tkos.co.il>
References: <1369570367-994-1-git-send-email-baruch@tkos.co.il>
Message-ID: <20130527120753.GB3048@maple>

On Sun, May 26, 2013 at 03:12:46PM +0300, Baruch Siach wrote:
> The time.h header seems not to be used by current code. Removing this include
> allows the driver to build on other architecture that do not have this header.
> 
> Cc: Ingo Molnar <mingo at redhat.com>
> Cc: Peter Zijlstra <peterz at infradead.org>
> Cc: John Stultz <john.stultz at linaro.org>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>

Acked-by: Jamie Iles <jamie at jamieiles.com>


From fabio.baltieri at linaro.org  Mon May 27 08:16:27 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Mon, 27 May 2013 14:16:27 +0200
Subject: [PATCH] ARM: ux500: select SND_SOC_UX500 for ux500
In-Reply-To: <CACRpkdbB7KjzUCf72gqN3ooiWYYkaaPrZUEDeG8HuLk3pTB72A@mail.gmail.com>
References: <1369402093-27817-1-git-send-email-fabio.baltieri@linaro.org>
 <CACRpkdbB7KjzUCf72gqN3ooiWYYkaaPrZUEDeG8HuLk3pTB72A@mail.gmail.com>
Message-ID: <20130527121627.GA29935@balto.lan>

On Mon, May 27, 2013 at 01:44:38PM +0200, Linus Walleij wrote:
> On Fri, May 24, 2013 at 3:28 PM, Fabio Baltieri
> <fabio.baltieri at linaro.org> wrote:
> 
> > Enable ux500 specific ALSA SoC drivers by default on u8500_defconfig.
> >
> > Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> 
> Thanks, patch applied to my defconfig branch.
> 
> Now I can finally use the Snowball board to run sidplay.

Glad to be of help! :-)

Fabio

-- 
Fabio Baltieri


From broonie at kernel.org  Mon May 27 08:16:58 2013
From: broonie at kernel.org (Mark Brown)
Date: Mon, 27 May 2013 08:16:58 -0400
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <CAGsJ_4y6SY6nNkbW+Yh8jx0WB4Pi9MO1W3xVZcrQcedGeD5ogQ@mail.gmail.com>
References: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
 <20130516093846.GA2927@katana>
 <CAGsJ_4zVOF8-g=emEGgP3atxkWdxMaQQiVZrZkht_WueTriSnw@mail.gmail.com>
 <20130525201032.GD32043@sirena.org.uk>
 <CAGsJ_4y6SY6nNkbW+Yh8jx0WB4Pi9MO1W3xVZcrQcedGeD5ogQ@mail.gmail.com>
Message-ID: <20130527121658.GA3660@sirena.org.uk>

On Mon, May 27, 2013 at 09:54:56AM +0800, Barry Song wrote:

> Mark, the case is not that deferred probing is slow or not. deferred
> probing is pretty good.
> the case is that we want to i2c and media connected with i2c probed
> earlier than other devices.
> in auto infotainment devices, we actually do some hacking in kernel
> that makes rear view work earlier than other device driver
> initialization with a kernel thread which take care of backing-car
> policy not only mechanism. that means, we make camera work to see
> backview image even earlier than other drivers' initialization.
> we don't want media deferred to wait for i2c. we want make some early
> jobs ready earlier.

So this change makes no practical difference in mainline and exists to
support out of tree hacks for performance?  It doesn't seem like that
big a patch to carry along with the out of tree stuff...
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From manjunath.goudar at linaro.org  Mon May 27 08:25:47 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Mon, 27 May 2013 17:55:47 +0530
Subject: [RFC V7 PATCH 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>

This series of patches begins the process of splitting ohci-hcd up into
a core library module and independent pci driver modules.

Patch 1/3 prepares the way by exporting a few functions from ohci-hcd
and adding a new mechanism for platform-specific drivers to initialize
their hc_driver structures.  This deserves to be done in the core
because almost all of the entries in these structures are pure
boilerplate -- practically none of the drivers need to override more
than three of the standard core values.

Patch 2/3 is part of separating the ohci pci host controller
driver from ohci-hcd host code.
Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
and EXPORTed, this is part of the effort to move the ohci pci related
code to generic pci code.

Patch 3/3  separate out ohci-pci into independent driver modules. 


Manjunath Goudar (3):
  USB: OHCI: prepare to make ohci-hcd a library module
  USB: OHCI: Generic changes to make ohci-pci a separate driver
  USB: OHCI: make ohci-pci a separate driver

 drivers/usb/host/Kconfig      |    4 +-
 drivers/usb/host/Makefile     |    3 +
 drivers/usb/host/ohci-hcd.c   |  132 +++++++++++++++++++++++++----------
 drivers/usb/host/ohci-hub.c   |    1 -
 drivers/usb/host/ohci-pci.c   |  152 ++++++++++++-----------------------------
 drivers/usb/host/ohci-q.c     |    6 +-
 drivers/usb/host/ohci.h       |   17 +++++
 drivers/usb/host/pci-quirks.c |   13 ++++
 drivers/usb/host/pci-quirks.h |    2 +
 9 files changed, 181 insertions(+), 149 deletions(-)

-- 
1.7.9.5



From manjunath.goudar at linaro.org  Mon May 27 08:25:48 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Mon, 27 May 2013 17:55:48 +0530
Subject: [RFC V7 PATCH 1/3] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369657550-24101-2-git-send-email-manjunath.goudar@linaro.org>

This patch prepares ohci-hcd for being split up into a core
library and separate platform driver modules.  A generic
ohci_hc_driver structure is created, containing all the "standard"
values, and a new mechanism is added whereby a driver module can
specify a set of overrides to those values.  In addition the
ohci_restart(),ohci_suspend() and ohci_resume() routines need
to be EXPORTed for use by the drivers.

Added ohci_setip(() and ohci_start() routine for to start the generic
controller rather than each having its own idiosyncratic approach.
This allow to clean duplicated code in most of SOC driver

In V2:
 -ohci_hcd_init() ohci_run() and ohci_stop() are not made non-static.
 -Adds the ohci_setup() and ohci_start() routine.

In V3:
 -purpose of ohci_setup() and ohci_start() function description written in the patch
  description.
 -ohci_init() are not made non-static but now called beginning of the ohci_restart().
 -ohci_run() signature change reverted back.
 -unrelated changes removed.
 -duplicate comment line removed.
 -inline ohci_suspend() and ohci_resume() is not needed so removed from ohci.h file.

In V4:
 -ohci-init() EXPORTed because it is called by all bus glue modules.
 -ohci-setup() removed from 1/2 added into 2/2 patch.

In V5:
 -Again ohci_setup() is added and EXPORTed because to replace the ohci_init() from
  all bus glues.
 -ohci_init() is not made non-static function.

In V6:
  -ohci_init() call is removed from ohci_quirk_nec_worker(), because it is already called in ohci_restart().

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Acked-by: Alan Stern <stern at rowland.harvard.edu>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci-hcd.c |  103 +++++++++++++++++++++++++++++++++++++++----
 drivers/usb/host/ohci-hub.c |    1 -
 drivers/usb/host/ohci-pci.c |    7 ---
 drivers/usb/host/ohci.h     |   17 +++++++
 4 files changed, 111 insertions(+), 17 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9e6de95..13ebbb7 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -79,13 +79,7 @@ static const char	hcd_name [] = "ohci_hcd";
 #include "pci-quirks.h"
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
-static int ohci_init (struct ohci_hcd *ohci);
 static void ohci_stop (struct usb_hcd *hcd);
-
-#if defined(CONFIG_PM) || defined(CONFIG_PCI)
-static int ohci_restart (struct ohci_hcd *ohci);
-#endif
-
 #ifdef CONFIG_PCI
 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
 #else
@@ -768,6 +762,30 @@ retry:
 	return 0;
 }
 
+/* ohci_setup routine for generic controller initialization */
+
+int ohci_setup(struct usb_hcd *hcd)
+{
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
+
+	return ohci_init(ohci);
+}
+EXPORT_SYMBOL_GPL(ohci_setup);
+
+/* ohci_start routine for generic controller start of all OHCI bus glue */
+static int ohci_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
+	int	ret;
+
+	ret = ohci_run(ohci);
+	if (ret < 0) {
+		ohci_err(ohci, "can't start\n");
+		ohci_stop(hcd);
+	}
+	return ret;
+}
+
 /*-------------------------------------------------------------------------*/
 
 /* an interrupt happens */
@@ -949,12 +967,13 @@ static void ohci_stop (struct usb_hcd *hcd)
 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 
 /* must not be called from interrupt context */
-static int ohci_restart (struct ohci_hcd *ohci)
+int ohci_restart(struct ohci_hcd *ohci)
 {
 	int temp;
 	int i;
 	struct urb_priv *priv;
 
+	ohci_init(ohci);
 	spin_lock_irq(&ohci->lock);
 	ohci->rh_state = OHCI_RH_HALTED;
 
@@ -1008,12 +1027,13 @@ static int ohci_restart (struct ohci_hcd *ohci)
 	ohci_dbg(ohci, "restart complete\n");
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_restart);
 
 #endif
 
 #ifdef CONFIG_PM
 
-static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
 	unsigned long	flags;
@@ -1031,9 +1051,10 @@ static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_suspend);
 
 
-static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
+int ohci_resume(struct usb_hcd *hcd, bool hibernated)
 {
 	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	int			port;
@@ -1081,8 +1102,72 @@ static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_resume);
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Generic structure: This gets copied for platform drivers so that
+ * individual entries can be overridden as needed.
+ */
 
+static const struct hc_driver ohci_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "OHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	*/
+	.irq =                  ohci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/*
+	* basic lifecycle operations
+	*/
+	.reset =                ohci_setup,
+	.start =                ohci_start,
+	.stop =                 ohci_stop,
+	.shutdown =             ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	*/
+	.urb_enqueue =          ohci_urb_enqueue,
+	.urb_dequeue =          ohci_urb_dequeue,
+	.endpoint_disable =     ohci_endpoint_disable,
+
+	/*
+	* scheduling support
+	*/
+	.get_frame_number =     ohci_get_frame,
+
+	/*
+	* root hub support
+	*/
+	.hub_status_data =      ohci_hub_status_data,
+	.hub_control =          ohci_hub_control,
+#ifdef CONFIG_PM
+	.bus_suspend =          ohci_bus_suspend,
+	.bus_resume =           ohci_bus_resume,
 #endif
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+void ohci_init_driver(struct hc_driver *drv,
+		const struct ohci_driver_overrides *over)
+{
+	/* Copy the generic table to drv and then apply the overrides */
+	*drv = ohci_hc_driver;
+
+	drv->product_desc = over->product_desc;
+	drv->hcd_priv_size += over->extra_priv_size;
+	if (over->reset)
+		drv->reset = over->reset;
+}
+EXPORT_SYMBOL_GPL(ohci_init_driver);
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index 60ff422..2347ab8 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -176,7 +176,6 @@ __acquires(ohci->lock)
 	if (status == -EBUSY) {
 		if (!autostopped) {
 			spin_unlock_irq (&ohci->lock);
-			(void) ohci_init (ohci);
 			status = ohci_restart (ohci);
 
 			usb_root_hub_lost_power(hcd->self.root_hub);
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 951514e..2c27a5f 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -123,13 +123,6 @@ static void ohci_quirk_nec_worker(struct work_struct *work)
 	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
 	int status;
 
-	status = ohci_init(ohci);
-	if (status != 0) {
-		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
-			 "ohci_init", status);
-		return;
-	}
-
 	status = ohci_restart(ohci);
 	if (status != 0)
 		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index d329914..3b58482 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -718,3 +718,20 @@ static inline u32 roothub_status (struct ohci_hcd *hc)
 	{ return ohci_readl (hc, &hc->regs->roothub.status); }
 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+/* Declarations of things exported for use by ohci platform drivers */
+
+struct ohci_driver_overrides {
+	const char	*product_desc;
+	size_t		extra_priv_size;
+	int		(*reset)(struct usb_hcd *hcd);
+};
+
+extern void	ohci_init_driver(struct hc_driver *drv,
+				const struct ohci_driver_overrides *over);
+extern int	ohci_restart(struct ohci_hcd *ohci);
+extern int	ohci_setup(struct usb_hcd *hcd);
+#ifdef CONFIG_PM
+extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
+extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
+#endif
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Mon May 27 08:25:49 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Mon, 27 May 2013 17:55:49 +0530
Subject: [RFC V7 PATCH 2/3] USB: OHCI: Generic changes to make ohci-pci a
 separate driver
In-Reply-To: <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369657550-24101-3-git-send-email-manjunath.goudar@linaro.org>

Note that this changes is part of separating the ohci pci host controller
driver from ohci-hcd host code.
This contains :
     -Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
      and EXPORTed, this is part of the effort to move the ohci pci related
      code to generic pci code.
     -Passed "device" argument instead  of "ohci_hcd" in sb800_prefetch()
      function to avoid extra include file in pci-quirks.c.

V2:
     -Passed "device" argment instead of "pci_dev", then we use to_pci_dev()
      to get the "pci_dev" structure.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci-hcd.c   |    9 ---------
 drivers/usb/host/ohci-pci.c   |   13 -------------
 drivers/usb/host/ohci-q.c     |    6 ++++--
 drivers/usb/host/pci-quirks.c |   13 +++++++++++++
 drivers/usb/host/pci-quirks.h |    2 ++
 5 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 13ebbb7..82f586a 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -80,15 +80,6 @@ static const char	hcd_name [] = "ohci_hcd";
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
 static void ohci_stop (struct usb_hcd *hcd);
-#ifdef CONFIG_PCI
-static void sb800_prefetch(struct ohci_hcd *ohci, int on);
-#else
-static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	return;
-}
-#endif
-
 
 #include "ohci-hub.c"
 #include "ohci-dbg.c"
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 2c27a5f..c3fa936 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -168,19 +168,6 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
 	return 0;
 }
 
-static void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	struct pci_dev *pdev;
-	u16 misc;
-
-	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
-	pci_read_config_word(pdev, 0x50, &misc);
-	if (on == 0)
-		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
-	else
-		pci_write_config_word(pdev, 0x50, misc | 0x0300);
-}
-
 /* List of quirks for OHCI */
 static const struct pci_device_id ohci_pci_quirks[] = {
 	{
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 88731b7..df4a670 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -41,6 +41,7 @@ finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
 __releases(ohci->lock)
 __acquires(ohci->lock)
 {
+	 struct device *dev = ohci_to_hcd(ohci)->self.controller;
 	// ASSERT (urb->hcpriv != 0);
 
 	urb_free_priv (ohci, urb->hcpriv);
@@ -55,7 +56,7 @@ __acquires(ohci->lock)
 			if (quirk_amdiso(ohci))
 				usb_amd_quirk_pll_enable();
 			if (quirk_amdprefetch(ohci))
-				sb800_prefetch(ohci, 0);
+				sb800_prefetch(dev, 0);
 		}
 		break;
 	case PIPE_INTERRUPT:
@@ -580,6 +581,7 @@ static void td_submit_urb (
 	struct urb	*urb
 ) {
 	struct urb_priv	*urb_priv = urb->hcpriv;
+	struct device *dev = ohci_to_hcd(ohci)->self.controller;
 	dma_addr_t	data;
 	int		data_len = urb->transfer_buffer_length;
 	int		cnt = 0;
@@ -689,7 +691,7 @@ static void td_submit_urb (
 			if (quirk_amdiso(ohci))
 				usb_amd_quirk_pll_disable();
 			if (quirk_amdprefetch(ohci))
-				sb800_prefetch(ohci, 1);
+				sb800_prefetch(dev, 1);
 		}
 		periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 			&& ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 4c338ec..b9848e4 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -91,6 +91,19 @@ static struct amd_chipset_info {
 
 static DEFINE_SPINLOCK(amd_lock);
 
+void sb800_prefetch(struct device *dev, int on)
+{
+	u16 misc;
+	struct pci_dev *pdev = to_pci_dev(dev);
+
+	pci_read_config_word(pdev, 0x50, &misc);
+	if (on == 0)
+		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
+	else
+		pci_write_config_word(pdev, 0x50, misc | 0x0300);
+}
+EXPORT_SYMBOL_GPL(sb800_prefetch);
+
 int usb_amd_find_chipset_info(void)
 {
 	u8 rev = 0;
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h
index 7f69a39..4b8a209 100644
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -11,11 +11,13 @@ void usb_amd_quirk_pll_enable(void);
 bool usb_is_intel_switchable_xhci(struct pci_dev *pdev);
 void usb_enable_xhci_ports(struct pci_dev *xhci_pdev);
 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
+void sb800_prefetch(struct device *dev, int on);
 #else
 static inline void usb_amd_quirk_pll_disable(void) {}
 static inline void usb_amd_quirk_pll_enable(void) {}
 static inline void usb_amd_dev_put(void) {}
 static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {}
+static inline void sb800_prefetch(struct device *dev, int on) {}
 #endif  /* CONFIG_PCI */
 
 #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Mon May 27 08:25:50 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Mon, 27 May 2013 17:55:50 +0530
Subject: [RFC V7 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369657550-24101-4-git-send-email-manjunath.goudar@linaro.org>

This patch splits the PCI portion of ohci-hcd out into its
own separate driver module, called ohci-pci.

The major point of difficulty lies in ohci-pci's many vendor- and
device-specific workarounds.  Some of them have to be applied before
calling ohci_start() some after, which necessitates a fair amount of
code motion.  The other platform drivers require much smaller changes.

The complete sb800_prefetch() function moved to ohci-q.c,because its
only related to ohci-pci driver.

V2:
  - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
    and rest of the generic code is written in ohci_start of ohci-hcd.c file.
V3:
 - ohci_restart() has been called in ohci_pci_reset() function for to reset the ohci pci.

V4:
 -sb800_prefetch() moved to ohci-q.c,because its only related to ohci-pci.
 -no longer _creating_ CONFIG_USB_OHCI_PCI,creating CONFIG_USB_OHCI_HCD_PCI.
 -overrides renamed with pci_override,its giving proper meaning.

V5:
 -sb800_prefetch() moved to pci-quirks.c,because its only related to pci.

V6:
 -sb800_prefetch() function has been moved to pci-quirks.c made as separate patch in 2/3.
 -Most of the generic ohci pci changes moved in 2/3 patch,now this is complete  ohci-pci separation patch.

V7:
 -Unrelated include file has been removed from ohci.h file.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig    |    4 +-
 drivers/usb/host/Makefile   |    3 +
 drivers/usb/host/ohci-hcd.c |   20 +------
 drivers/usb/host/ohci-pci.c |  132 +++++++++++++++----------------------------
 4 files changed, 51 insertions(+), 108 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 64d7209..7e75387 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -377,7 +377,7 @@ config USB_FUSBH200_HCD
 	module will be called fusbh200-hcd.
 
 config USB_OHCI_HCD
-	tristate "OHCI HCD support"
+	tristate "OHCI HCD (USB 1.1) support"
 	depends on USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	depends on USB_ISP1301 || !ARCH_LPC32XX
@@ -446,7 +446,7 @@ config USB_OHCI_HCD_PPC_OF
 	default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE
 
 config USB_OHCI_HCD_PCI
-	bool "OHCI support for PCI-bus USB controllers"
+	tristate "OHCI support for PCI-bus USB controllers"
 	depends on PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
 	default y
 	select USB_OHCI_LITTLE_ENDIAN
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 661c558..2214ded 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -42,7 +42,10 @@ obj-$(CONFIG_USB_EHCI_TEGRA)    +=ehci-tegra.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
+
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+obj-$(CONFIG_USB_OHCI_HCD_PCI)	+= ohci-pci.o
+
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 82f586a..4a83031 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1166,11 +1166,6 @@ MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
 
-#ifdef CONFIG_PCI
-#include "ohci-pci.c"
-#define PCI_DRIVER		ohci_pci_driver
-#endif
-
 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
 #include "ohci-sa1111.c"
 #define SA1111_DRIVER		ohci_hcd_sa1111_driver
@@ -1266,7 +1261,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_platform_driver
 #endif
 
-#if	!defined(PCI_DRIVER) &&		\
+#if	!IS_ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
@@ -1341,12 +1336,6 @@ static int __init ohci_hcd_mod_init(void)
 		goto error_sa1111;
 #endif
 
-#ifdef PCI_DRIVER
-	retval = pci_register_driver(&PCI_DRIVER);
-	if (retval < 0)
-		goto error_pci;
-#endif
-
 #ifdef SM501_OHCI_DRIVER
 	retval = platform_driver_register(&SM501_OHCI_DRIVER);
 	if (retval < 0)
@@ -1440,10 +1429,6 @@ static int __init ohci_hcd_mod_init(void)
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
  error_sm501:
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
- error_pci:
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
  error_sa1111:
@@ -1508,9 +1493,6 @@ static void __exit ohci_hcd_mod_exit(void)
 #ifdef SM501_OHCI_DRIVER
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
 #endif
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index c3fa936..ea088c1 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -14,12 +14,19 @@
  * This file is licenced under the GPL.
  */
 
-#ifndef CONFIG_PCI
-#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
-#endif
-
-#include <linux/pci.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+#include "pci-quirks.h"
+
+#define DRIVER_DESC "OHCI PCI platform driver"
+
+static const char hcd_name[] = "ohci-pci";
 
 
 /*-------------------------------------------------------------------------*/
@@ -229,10 +236,10 @@ static const struct pci_device_id ohci_pci_quirks[] = {
 static int ohci_pci_reset (struct usb_hcd *hcd)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
+	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 	int ret = 0;
 
 	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 		const struct pci_device_id *quirk_id;
 
 		quirk_id = pci_match_id(ohci_pci_quirks, pdev);
@@ -242,94 +249,24 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
 			ret = quirk(hcd);
 		}
 	}
-	if (ret == 0) {
-		ohci_hcd_init (ohci);
-		return ohci_init (ohci);
-	}
-	return ret;
-}
-
-
-static int ohci_pci_start (struct usb_hcd *hcd)
-{
-	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
-	int		ret;
-
-#ifdef CONFIG_PM /* avoid warnings about unused pdev */
-	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
-
-		/* RWC may not be set for add-in PCI cards, since boot
-		 * firmware probably ignored them.  This transfers PCI
-		 * PM wakeup capabilities.
-		 */
-		if (device_can_wakeup(&pdev->dev))
-			ohci->hc_control |= OHCI_CTRL_RWC;
-	}
-#endif /* CONFIG_PM */
-
-	ret = ohci_run (ohci);
-	if (ret < 0) {
-		ohci_err (ohci, "can't start\n");
-		ohci_stop (hcd);
-	}
+	if (ret == 0)
+		ohci_setup(hcd);
+	/*
+	* After ohci setup RWC may not be set for add-in PCI cards.
+	* This transfers PCI PM wakeup capabilities.
+	*/
+	if (device_can_wakeup(&pdev->dev))
+		ohci->hc_control |= OHCI_CTRL_RWC;
 	return ret;
 }
 
+static struct hc_driver __read_mostly ohci_pci_hc_driver;
 
-/*-------------------------------------------------------------------------*/
-
-static const struct hc_driver ohci_pci_hc_driver = {
-	.description =		hcd_name,
-	.product_desc =		"OHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			ohci_irq,
-	.flags =		HCD_MEMORY | HCD_USB11,
-
-	/*
-	 * basic lifecycle operations
-	 */
+static const struct ohci_driver_overrides pci_overrides __initconst = {
+	.product_desc =		"OHCI PCI host controller",
 	.reset =		ohci_pci_reset,
-	.start =		ohci_pci_start,
-	.stop =			ohci_stop,
-	.shutdown =		ohci_shutdown,
-
-#ifdef	CONFIG_PM
-	.pci_suspend =		ohci_suspend,
-	.pci_resume =		ohci_resume,
-#endif
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		ohci_urb_enqueue,
-	.urb_dequeue =		ohci_urb_dequeue,
-	.endpoint_disable =	ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data =	ohci_hub_status_data,
-	.hub_control =		ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend =		ohci_bus_suspend,
-	.bus_resume =		ohci_bus_resume,
-#endif
-	.start_port_reset =	ohci_start_port_reset,
 };
 
-/*-------------------------------------------------------------------------*/
-
-
 static const struct pci_device_id pci_ids [] = { {
 	/* handle any USB OHCI controller */
 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
@@ -357,3 +294,24 @@ static struct pci_driver ohci_pci_driver = {
 	},
 #endif
 };
+
+static int __init ohci_pci_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_pci_hc_driver, &pci_overrides);
+	return pci_register_driver(&ohci_pci_driver);
+}
+module_init(ohci_pci_init);
+
+static void __exit ohci_pci_cleanup(void)
+{
+	pci_unregister_driver(&ohci_pci_driver);
+}
+module_exit(ohci_pci_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
-- 
1.7.9.5



From b-cousson at ti.com  Mon May 27 08:27:15 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Mon, 27 May 2013 14:27:15 +0200
Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output
 on SoC pad
In-Reply-To: <alpine.DEB.2.00.1305200246080.2656@utopia.booyaka.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83EC8C081@DBDE04.ent.ti.com>
 <alpine.DEB.2.00.1305200246080.2656@utopia.booyaka.com>
Message-ID: <51A35123.6040600@ti.com>

Salut Paul,

On 05/20/2013 04:47 AM, Paul Walmsley wrote:
> On Fri, 17 May 2013, Hiremath, Vaibhav wrote:
> 
>> Tony, Paul and Benoit,
>>
>> Any update on this series?
> 
> Most of the changes are DT-related, so it should probably go in via 
> Beno?t.  I'll ack the clock side, but have a comment on patch 2, to be 
> sent shortly.

I've tried to apply that patch, but unfortunately, it does depend on
that one:

https://patchwork.kernel.org/patch/2212081/

If you did not already pulled the first one I can take both with your
acked-by.
Otherwise, I can take only the DTS ones.

Is that OK?

Thanks,
Benoit




From tglx at linutronix.de  Mon May 27 08:28:39 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 27 May 2013 14:28:39 +0200 (CEST)
Subject: [RFC PATCHv4 4/6] clocksource: TI-Nspire timer support
In-Reply-To: <CACRpkda4Qe1e+dkcSgPLf5dcHASvOG=Y=Dvrnv=oGnon+FRzzg@mail.gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-5-git-send-email-dt.tangr@gmail.com>
 <CACRpkda4Qe1e+dkcSgPLf5dcHASvOG=Y=Dvrnv=oGnon+FRzzg@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1305271427320.4220@ionos>

On Mon, 27 May 2013, Linus Walleij wrote:
> > +static void zevio_timer_set_mode(enum clock_event_mode mode,
> > +               struct clock_event_device *dev)
> > +{
> > +       unsigned long flags;
> > +       struct zevio_timer *timer = container_of(dev,
> > +                       struct zevio_timer,
> > +                       clkevt);
> > +
> > +       local_irq_save(flags);
> > +
> > +       switch (mode) {
> > +       case CLOCK_EVT_MODE_PERIODIC:
> > +               /* Unsupported */
> > +               break;
> > +       case CLOCK_EVT_MODE_RESUME:
> > +       case CLOCK_EVT_MODE_ONESHOT:
> > +               /* Enable timer interrupts */
> > +               writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
> > +               writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
> > +               dev->mode = mode;
> > +               break;
> > +       case CLOCK_EVT_MODE_SHUTDOWN:
> > +       case CLOCK_EVT_MODE_UNUSED:
> > +               /* Disable timer interrupts */
> > +               writel(0, timer->interrupt_regs + IO_INTR_MSK);
> > +               writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
> > +               /* Stop timer */
> > +               writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
> > +               dev->mode = mode;
> > +               break;
> > +       }
> 
> Surely both the compiler and checkpatch is complaining that this
> switch does not contain a default: clause?

Well, if you have a switch with an enum, the compiler complains if you
do not have a case for each enum value and the above has all enum
values covered AFAICT. :)

Thanks,

	tglx



From ulf.hansson at stericsson.com  Mon May 27 08:30:15 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 May 2013 14:30:15 +0200
Subject: [PATCH] ARM: ux500: Update MMC configs for u8500 defconfig
Message-ID: <1369657815-16236-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Enable MMC_UNSAFE_RESUME to be accomplish a proper suspend/resume cycle
for SD/SDIO/(e)MMC.

ARMMMCI host driver supports clock gating through runtime PM, thus
MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
enabled, to skip unnecessary bounce buffer copying.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/configs/u8500_defconfig |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index da0614a..06aa294 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -78,7 +78,8 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MUSB_HDRC=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
-- 
1.7.10



From linus.walleij at linaro.org  Mon May 27 08:35:30 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 14:35:30 +0200
Subject: [PATCH] ARM: ux500: Update MMC configs for u8500 defconfig
In-Reply-To: <1369657815-16236-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369657815-16236-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdYqBR-azYEpSTCATuuSP99v+qy72PyMt6MoDwVF_qF0vw@mail.gmail.com>

On Mon, May 27, 2013 at 2:30 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> Enable MMC_UNSAFE_RESUME to be accomplish a proper suspend/resume cycle
> for SD/SDIO/(e)MMC.
>
> ARMMMCI host driver supports clock gating through runtime PM, thus
> MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
> means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
> enabled, to skip unnecessary bounce buffer copying.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Thanks, patch applied to my ux500-defconfig branch.

Yours,
Linus Walleij


From philippe.begnic.st at gmail.com  Mon May 27 08:41:28 2013
From: philippe.begnic.st at gmail.com (Philippe Begnic)
Date: Mon, 27 May 2013 14:41:28 +0200
Subject: [PATCH 0/4] clk, mfd: u8540 clock tree definition
Message-ID: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>

From: Philippe Begnic <philippe.begnic at st.com>

Create U8540 clock tree definitions for common clock framework

Philippe Begnic (4):
  clk: ux500: Pass clock base adresses in initcall for u8540 and u9540
  mfd: db8500: Update register definition for u8540 clock
  mfd: db8500: Update BML clock register for db8580
  clk: ux500: Clocks definition for u8540

 arch/arm/mach-ux500/cpu.c                 |    6 +-
 drivers/clk/ux500/u8540_clk.c             |  564 ++++++++++++++++++++++++++++-
 drivers/clk/ux500/u9540_clk.c             |    4 +-
 drivers/mfd/db8500-prcmu.c                |    1 +
 drivers/mfd/dbx500-prcmu-regs.h           |    1 +
 include/linux/mfd/abx500/ab8500-sysctrl.h |    4 +-
 include/linux/mfd/dbx500-prcmu.h          |   12 +
 include/linux/platform_data/clk-ux500.h   |    6 +-
 8 files changed, 587 insertions(+), 11 deletions(-)

-- 
1.7.9.5



From philippe.begnic.st at gmail.com  Mon May 27 08:41:29 2013
From: philippe.begnic.st at gmail.com (Philippe Begnic)
Date: Mon, 27 May 2013 14:41:29 +0200
Subject: [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for
 u8540 and u9540
In-Reply-To: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
Message-ID: <1369658492-31358-2-git-send-email-philippe.begnic.st@gmail.com>

From: Philippe Begnic <philippe.begnic at st.com>

Align on u8500 version, pass clock base address in clk_init functions
for u8540 and u9540.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Philippe Begnic <philippe.begnic at st.com>
---
 arch/arm/mach-ux500/cpu.c               |    6 ++++--
 drivers/clk/ux500/u8540_clk.c           |    4 ++--
 drivers/clk/ux500/u9540_clk.c           |    4 ++--
 include/linux/platform_data/clk-ux500.h |    6 ++++--
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index b6145ea..e6fb023 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -76,13 +76,15 @@ void __init ux500_init_irq(void)
 	} else if (cpu_is_u9540()) {
 		prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
 		ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
-		u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+		u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
 			       U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
 			       U8500_CLKRST6_BASE);
 	} else if (cpu_is_u8540()) {
 		prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
 		ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
-		u8540_clk_init();
+		u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+			       U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+			       U8500_CLKRST6_BASE);
 	}
 }
 
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
index 10adfd2..90f3c88 100644
--- a/drivers/clk/ux500/u8540_clk.c
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -12,10 +12,10 @@
 #include <linux/clk-provider.h>
 #include <linux/mfd/dbx500-prcmu.h>
 #include <linux/platform_data/clk-ux500.h>
-
 #include "clk.h"
 
-void u8540_clk_init(void)
+void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+		    u32 clkrst5_base, u32 clkrst6_base)
 {
 	/* register clocks here */
 }
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
index dbc0191..4479478 100644
--- a/drivers/clk/ux500/u9540_clk.c
+++ b/drivers/clk/ux500/u9540_clk.c
@@ -12,10 +12,10 @@
 #include <linux/clk-provider.h>
 #include <linux/mfd/dbx500-prcmu.h>
 #include <linux/platform_data/clk-ux500.h>
-
 #include "clk.h"
 
-void u9540_clk_init(void)
+void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+		    u32 clkrst5_base, u32 clkrst6_base)
 {
 	/* register clocks here */
 }
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
index 320d9c3..9d98f3a 100644
--- a/include/linux/platform_data/clk-ux500.h
+++ b/include/linux/platform_data/clk-ux500.h
@@ -12,7 +12,9 @@
 
 void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 		    u32 clkrst5_base, u32 clkrst6_base);
-void u9540_clk_init(void);
-void u8540_clk_init(void);
+void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+		    u32 clkrst5_base, u32 clkrst6_base);
+void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+		    u32 clkrst5_base, u32 clkrst6_base);
 
 #endif /* __CLK_UX500_H */
-- 
1.7.9.5



From ulf.hansson at stericsson.com  Mon May 27 08:41:55 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 May 2013 14:41:55 +0200
Subject: [PATCH] ARM: u300: Update MMC configs for u300 defconfig
Message-ID: <1369658515-18774-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Enable MMC_UNSAFE_RESUME to be accomplish a proper suspend/resume cycle
for SD/SDIO/(e)MMC.

ARMMMCI host driver supports clock gating through runtime PM, thus
MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
enabled, to skip unnecessary bounce buffer copying.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/configs/u300_defconfig |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index a5fa0d9..fd81a1b 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -49,7 +49,8 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
-- 
1.7.10



From philippe.begnic.st at gmail.com  Mon May 27 08:41:30 2013
From: philippe.begnic.st at gmail.com (Philippe Begnic)
Date: Mon, 27 May 2013 14:41:30 +0200
Subject: [PATCH 2/4] mfd: db8500: Update register definition for u8540 clock
In-Reply-To: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
Message-ID: <1369658492-31358-3-git-send-email-philippe.begnic.st@gmail.com>

From: Philippe Begnic <philippe.begnic at st.com>

PRCMU and ab8500 registers updated for u8540

Signed-off-by: Philippe Begnic <philippe.begnic at st.com>
---
 include/linux/mfd/abx500/ab8500-sysctrl.h |    4 ++--
 include/linux/mfd/dbx500-prcmu.h          |   11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 990bc93..adba89d 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -278,8 +278,8 @@ struct ab8500_sysctrl_platform_data {
 
 #define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 689e6a0..d0ba355 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -134,6 +134,10 @@ enum prcmu_clock {
 	PRCMU_SIACLK,
 	PRCMU_SVACLK,
 	PRCMU_ACLK,
+	PRCMU_HVACLK, /* Ux540 only */
+	PRCMU_G1CLK, /* Ux540 only */
+	PRCMU_SDMMCHCLK,
+	PRCMU_CAMCLK,
 	PRCMU_NUM_REG_CLOCKS,
 	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
 	PRCMU_CDCLK,
@@ -148,6 +152,13 @@ enum prcmu_clock {
 	PRCMU_DSI0ESCCLK,
 	PRCMU_DSI1ESCCLK,
 	PRCMU_DSI2ESCCLK,
+	/* LCD DSI PLL - Ux540 only */
+	PRCMU_PLLDSI_LCD,
+	PRCMU_DSI0CLK_LCD,
+	PRCMU_DSI1CLK_LCD,
+	PRCMU_DSI0ESCCLK_LCD,
+	PRCMU_DSI1ESCCLK_LCD,
+	PRCMU_DSI2ESCCLK_LCD,
 };
 
 /**
-- 
1.7.9.5



From philippe.begnic.st at gmail.com  Mon May 27 08:41:31 2013
From: philippe.begnic.st at gmail.com (Philippe Begnic)
Date: Mon, 27 May 2013 14:41:31 +0200
Subject: [PATCH 3/4] mfd: db8500: Update BML clock register for db8580
In-Reply-To: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
Message-ID: <1369658492-31358-4-git-send-email-philippe.begnic.st@gmail.com>

From: Philippe Begnic <philippe.begnic at st.com>

BML clock register address in DB8580 has changed.Defined a new address
under different name for DB8580.

Signed-off-by: Philippe Begnic <philippe.begnic at st.com>
---
 drivers/mfd/db8500-prcmu.c       |    1 +
 drivers/mfd/dbx500-prcmu-regs.h  |    1 +
 include/linux/mfd/dbx500-prcmu.h |    1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 66f8097..a292a1d 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -480,6 +480,7 @@ struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 	CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 	CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 	CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
+	CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
 	CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 	CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 	CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index d14836e..ca355dd 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -32,6 +32,7 @@
 #define PRCM_PER7CLK_MGT	(0x040)
 #define PRCM_LCDCLK_MGT		(0x044)
 #define PRCM_BMLCLK_MGT		(0x04C)
+#define PRCM_BML8580CLK_MGT	(0x108)
 #define PRCM_HSITXCLK_MGT	(0x050)
 #define PRCM_HSIRXCLK_MGT	(0x054)
 #define PRCM_HDMICLK_MGT	(0x058)
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index d0ba355..ca0790f 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -138,6 +138,7 @@ enum prcmu_clock {
 	PRCMU_G1CLK, /* Ux540 only */
 	PRCMU_SDMMCHCLK,
 	PRCMU_CAMCLK,
+	PRCMU_BML8580CLK,
 	PRCMU_NUM_REG_CLOCKS,
 	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
 	PRCMU_CDCLK,
-- 
1.7.9.5



From philippe.begnic.st at gmail.com  Mon May 27 08:41:32 2013
From: philippe.begnic.st at gmail.com (Philippe Begnic)
Date: Mon, 27 May 2013 14:41:32 +0200
Subject: [PATCH 4/4] clk: ux500: Clocks definition for u8540
In-Reply-To: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
Message-ID: <1369658492-31358-5-git-send-email-philippe.begnic.st@gmail.com>

From: Philippe Begnic <philippe.begnic at st.com>

First clocks definition version of PRCMU and PRCC clocks for u8540 platform

Signed-off-by: Philippe Begnic <philippe.begnic at st.com>
---
 drivers/clk/ux500/u8540_clk.c |  560 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 559 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
index 90f3c88..f262588 100644
--- a/drivers/clk/ux500/u8540_clk.c
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -17,5 +17,563 @@
 void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 		    u32 clkrst5_base, u32 clkrst6_base)
 {
-	/* register clocks here */
+	struct clk *clk;
+
+	/* Clock sources. */
+	/* Fixed ClockGen */
+	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "soc0_pll", NULL);
+
+	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "soc1_pll", NULL);
+
+	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "ddr_pll", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+				32768);
+	clk_register_clkdev(clk, "clk32k", NULL);
+	clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
+
+	clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+				38400000);
+
+	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "UART");
+
+	/* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
+	clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1",
+			PRCMU_MSP02CLK, 0);
+	clk_register_clkdev(clk, NULL, "MSP02");
+
+	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "MSP1");
+
+	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "I2C");
+
+	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "slim");
+
+	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH1");
+
+	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH2");
+
+	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH3");
+
+	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH5");
+
+	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH6");
+
+	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH7");
+
+	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "lcd");
+	clk_register_clkdev(clk, "lcd", "mcde");
+
+	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BML8580CLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "bml");
+
+	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "hdmi");
+	clk_register_clkdev(clk, "hdmi", "mcde");
+
+	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "apeat");
+
+	clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "apetrace");
+
+	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mcde");
+	clk_register_clkdev(clk, "mcde", "mcde");
+	clk_register_clkdev(clk, NULL, "dsilink.0");
+	clk_register_clkdev(clk, NULL, "dsilink.1");
+	clk_register_clkdev(clk, NULL, "dsilink.2");
+
+	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "ipi2");
+
+	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "dsialt");
+
+	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "dma40.0");
+
+	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "b2r2");
+	clk_register_clkdev(clk, NULL, "b2r2_core");
+	clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
+	clk_register_clkdev(clk, NULL, "b2r2_1_core");
+
+	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "tv");
+	clk_register_clkdev(clk, "tv", "mcde");
+
+	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "SSP");
+
+	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "rngclk");
+
+	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "uicc");
+
+	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mtu0");
+	clk_register_clkdev(clk, NULL, "mtu1");
+
+	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
+					PRCMU_SDMMCCLK, 100000000,
+					CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdmmc");
+
+	clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL,
+					PRCMU_SDMMCHCLK, 400000000,
+					CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdmmchclk");
+
+	clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "hva");
+
+	clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "g1");
+
+	clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilcd", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
+				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs2", "mcde");
+	clk_register_clkdev(clk, "hs_clk", "dsilink.2");
+
+	clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk",
+				PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilcd_pll", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
+				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs0", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll",
+				PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs0", "mcde");
+	clk_register_clkdev(clk, "hs_clk", "dsilink.0");
+
+	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
+				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs1", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll",
+				PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs1", "mcde");
+	clk_register_clkdev(clk, "hs_clk", "dsilink.1");
+
+	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
+				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "lp_clk", "dsilink.0");
+	clk_register_clkdev(clk, "dsilp0", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
+				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "lp_clk", "dsilink.1");
+	clk_register_clkdev(clk, "dsilp1", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
+				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "lp_clk", "dsilink.2");
+	clk_register_clkdev(clk, "dsilp2", "mcde");
+
+	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
+				PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "armss", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
+				CLK_IGNORE_UNUSED, 1, 2);
+	clk_register_clkdev(clk, NULL, "smp_twd");
+
+	/* PRCC P-clocks */
+	/* Peripheral 1 : PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
+				BIT(1), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart1");
+
+	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
+				BIT(2), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
+
+	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
+				BIT(3), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp0");
+	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp1");
+	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1");
+
+	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
+				BIT(5), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
+
+	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
+				BIT(7), 0);
+	clk_register_clkdev(clk, NULL, "spi3");
+
+	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
+				BIT(8), 0);
+	clk_register_clkdev(clk, "apb_pclk", "slimbus0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
+				BIT(9), 0);
+	clk_register_clkdev(clk, NULL, "gpio.0");
+	clk_register_clkdev(clk, NULL, "gpio.1");
+	clk_register_clkdev(clk, NULL, "gpioblock0");
+	clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
+				BIT(10), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
+
+	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
+				BIT(11), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp3");
+	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3");
+
+	/* Peripheral 2 : PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
+
+	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "spi2");
+
+	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
+				BIT(2), 0);
+	clk_register_clkdev(clk, NULL, "spi1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
+				BIT(3), 0);
+	clk_register_clkdev(clk, NULL, "pwl");
+
+	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi4");
+
+	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
+				BIT(5), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp2");
+	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2");
+
+	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi3");
+
+	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
+				BIT(8), 0);
+	clk_register_clkdev(clk, NULL, "spi0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
+				BIT(9), 0);
+	clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
+				BIT(10), 0);
+	clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
+				BIT(11), 0);
+	clk_register_clkdev(clk, NULL, "gpio.6");
+	clk_register_clkdev(clk, NULL, "gpio.7");
+	clk_register_clkdev(clk, NULL, "gpioblock1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
+				BIT(12), 0);
+	clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0");
+
+	/* Peripheral 3 : PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
+				BIT(0), 0);
+	clk_register_clkdev(clk, NULL, "fsmc");
+
+	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
+				BIT(1), 0);
+	clk_register_clkdev(clk, "apb_pclk", "ssp0");
+
+	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
+				BIT(2), 0);
+	clk_register_clkdev(clk, "apb_pclk", "ssp1");
+
+	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
+				BIT(3), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
+
+	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
+				BIT(5), 0);
+	clk_register_clkdev(clk, "apb_pclk", "ske");
+	clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
+
+	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi5");
+
+	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
+				BIT(8), 0);
+	clk_register_clkdev(clk, NULL, "gpio.2");
+	clk_register_clkdev(clk, NULL, "gpio.3");
+	clk_register_clkdev(clk, NULL, "gpio.4");
+	clk_register_clkdev(clk, NULL, "gpio.5");
+	clk_register_clkdev(clk, NULL, "gpioblock2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", clkrst3_base,
+				BIT(9), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5");
+
+	clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", clkrst3_base,
+				BIT(10), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6");
+
+	clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", clkrst3_base,
+				BIT(11), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart3");
+
+	clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", clkrst3_base,
+				BIT(12), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart4");
+
+	/* Peripheral 5 : PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "usb", "musb-ux500.0");
+	clk_register_clkdev(clk, "usbclk", "ab-iddet.0");
+
+	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "gpio.8");
+	clk_register_clkdev(clk, NULL, "gpioblock3");
+
+	/* Peripheral 6 : PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "apb_pclk", "rng");
+
+	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "cryp0");
+	clk_register_clkdev(clk, NULL, "cryp1");
+
+	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
+				BIT(2), 0);
+	clk_register_clkdev(clk, NULL, "hash0");
+
+	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
+				BIT(3), 0);
+	clk_register_clkdev(clk, NULL, "pka");
+
+	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
+				BIT(4), 0);
+	clk_register_clkdev(clk, NULL, "db8540-hash1");
+
+	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
+				BIT(5), 0);
+	clk_register_clkdev(clk, NULL, "cfgreg");
+
+	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "mtu0");
+
+	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "mtu1");
+
+	/*
+	 * PRCC K-clocks  ==> see table PRCC_PCKEN/PRCC_KCKEN
+	 * This differs from the internal implementation:
+	 * We don't use the PERPIH[n| clock as parent, since those _should_
+	 * only be used as parents for the P-clocks.
+	 * TODO: "parentjoin" with corresponding P-clocks for all K-clocks.
+	 */
+
+	/* Peripheral 1 : PRCC K-clocks */
+	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
+			clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart0");
+
+	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
+			clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart1");
+
+	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
+			clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.1");
+
+	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
+			clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp0");
+	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0");
+
+	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
+			clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp1");
+	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1");
+
+	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk",
+			clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi0");
+
+	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
+			clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.2");
+
+	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
+			clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "slimbus0");
+
+	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
+			clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.4");
+
+	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
+			clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp3");
+	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3");
+
+	/* Peripheral 2 : PRCC K-clocks */
+	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
+			clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.3");
+
+	clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k",
+			clkrst2_base, BIT(1), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "pwl");
+
+	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk",
+			clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi4");
+
+	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
+			clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp2");
+	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2");
+
+	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk",
+			clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi1");
+
+	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
+			clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi3");
+
+	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
+			clkrst2_base, BIT(6),
+			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+	clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
+			clkrst2_base, BIT(7),
+			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+	clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0");
+
+	/* Should only be 9540, but might be added for 85xx as well */
+	clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk",
+			clkrst2_base, BIT(9), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp4");
+	clk_register_clkdev(clk, "msp4", "ab85xx-codec.0");
+
+	/* Peripheral 3 : PRCC K-clocks */
+	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
+			clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "ssp0");
+
+	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
+			clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "ssp1");
+
+	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
+			clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.0");
+
+	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk",
+			clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi2");
+
+	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
+			clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "ske");
+	clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
+
+	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
+			clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart2");
+
+	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
+			clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi5");
+
+	clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk",
+			clkrst3_base, BIT(8), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.5");
+
+	clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk",
+			clkrst3_base, BIT(9), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.6");
+
+	clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk",
+			clkrst3_base, BIT(10), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart3");
+
+	clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk",
+			clkrst3_base, BIT(11), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart4");
+
+	/* Peripheral 6 : PRCC K-clocks */
+	clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk",
+			clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "rng");
 }
-- 
1.7.9.5



From plagnioj at jcrosoft.com  Mon May 27 08:43:38 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 27 May 2013 20:43:38 +0800
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <51A34BF9.5000905@atmel.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
 <51A34BF9.5000905@atmel.com>
Message-ID: <DB6D19D2-3060-4DF5-BCA5-CD52349FC5E1@jcrosoft.com>


On May 27, 2013, at 8:05 PM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:

> On 27/05/2013 12:48, Alexandre Belloni :
>> Fixes:
>> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
>> :(.text+0x1174): undefined reference to `mdiobus_write'
>> :(.text+0x1188): undefined reference to `mdiobus_write'
>> :(.text+0x119c): undefined reference to `mdiobus_write'
>> :(.text+0x11b0): undefined reference to `mdiobus_write'
>> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
>> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
>> 
>> when CONFIG_PHYLIB is not selected.
>> 
>> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
>> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>> ---
>> Changes in v3:
>> 	added SoB
>> 	added Acked-By
> 
> A v3 is not needed simply for this. Thanks, anyway!
> 
> One question though: why not just add
> 
>        select PHYLIB
> 
> In Kconfig entry:
> 
> config MACH_SAMA5_DT
> 
> ?
> 
> (note that I like to play with everybody's nerves ;-))
> 

I prefer this than the IS_BUILTIN


> Bye,
> 
>> Changes in v2:
>> 	use IS_BUILTIN
>> 	use CONFIG_PHYLIB and not CONFIG_PHY
>> 
>>  arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
>>  1 file changed, 12 insertions(+), 10 deletions(-)
>> 
>> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
>> index 705305e..e9ce541 100644
>> --- a/arch/arm/mach-at91/board-dt-sama5.c
>> +++ b/arch/arm/mach-at91/board-dt-sama5.c
>> @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
>>  #define GMII_ERCR	11
>>  #define GMII_ERDWR	12
>> 
>> -	/* Set delay values */
>> -	value = GMII_RCCPSR | 0x8000;
>> -	phy_write(phy, GMII_ERCR, value);
>> -	value = 0xF2F4;
>> -	phy_write(phy, GMII_ERDWR, value);
>> -	value = GMII_RRDPSR | 0x8000;
>> -	phy_write(phy, GMII_ERCR, value);
>> -	value = 0x2222;
>> -	phy_write(phy, GMII_ERDWR, value);
>> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
>> +		/* Set delay values */
>> +		value = GMII_RCCPSR | 0x8000;
>> +		phy_write(phy, GMII_ERCR, value);
>> +		value = 0xF2F4;
>> +		phy_write(phy, GMII_ERDWR, value);
>> +		value = GMII_RRDPSR | 0x8000;
>> +		phy_write(phy, GMII_ERCR, value);
>> +		value = 0x2222;
>> +		phy_write(phy, GMII_ERDWR, value);
>> +	}
>> 
>>  	return 0;
>>  }
>> 
>>  static void __init sama5_dt_device_init(void)
>>  {
>> -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
>> +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
>>  		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
>>  			ksz9021rn_phy_fixup);
>> 
>> 
> 
> 
> -- 
> Nicolas Ferre



From arnd at arndb.de  Mon May 27 08:42:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 14:42:12 +0200
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <51A34BF9.5000905@atmel.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
 <51A34BF9.5000905@atmel.com>
Message-ID: <6343931.uK9ItNlUFg@wuerfel>

On Monday 27 May 2013 14:05:13 Nicolas Ferre wrote:
> On 27/05/2013 12:48, Alexandre Belloni :
> A v3 is not needed simply for this. Thanks, anyway!
> 
> One question though: why not just add
> 
>          select PHYLIB
> 
> In Kconfig entry:
> 
>   config MACH_SAMA5_DT
> 
> ?
> 
> (note that I like to play with everybody's nerves ;-))

That would make it impossible to build a sama5 kernel without networking
support, which is probably not what you want.

Jean-Christophe's suggestion to add the inline helper is best. Aside from
that, please note that

> > diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
> > index 705305e..e9ce541 100644
> > --- a/arch/arm/mach-at91/board-dt-sama5.c
> > +++ b/arch/arm/mach-at91/board-dt-sama5.c
> > @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
> >   #define GMII_ERCR	11
> >   #define GMII_ERDWR	12
> >
> > -	/* Set delay values */
> > -	value = GMII_RCCPSR | 0x8000;
> > -	phy_write(phy, GMII_ERCR, value);
> > -	value = 0xF2F4;
> > -	phy_write(phy, GMII_ERDWR, value);
> > -	value = GMII_RRDPSR | 0x8000;
> > -	phy_write(phy, GMII_ERCR, value);
> > -	value = 0x2222;
> > -	phy_write(phy, GMII_ERDWR, value);
> > +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
> > +		/* Set delay values */
> > +		value = GMII_RCCPSR | 0x8000;
> > +		phy_write(phy, GMII_ERCR, value);
> > +		value = 0xF2F4;
> > +		phy_write(phy, GMII_ERDWR, value);
> > +		value = GMII_RRDPSR | 0x8000;
> > +		phy_write(phy, GMII_ERCR, value);
> > +		value = 0x2222;
> > +		phy_write(phy, GMII_ERDWR, value);
> > +	}
> >
> >   	return 0;
> >   }

This part of the patch is not actually needed if you

> >   static void __init sama5_dt_device_init(void)
> >   {
> > -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
> > +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
> >   		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
> >   			ksz9021rn_phy_fixup);

do this change, or the inline helper.

	Arnd


From manishv.b at ti.com  Mon May 27 08:45:35 2013
From: manishv.b at ti.com (Vishwanathrao Badarkhe, Manish)
Date: Mon, 27 May 2013 12:45:35 +0000
Subject: [PATCH] ARM: dts: omap2plus: remove interrupt-parent property
In-Reply-To: <A4887BF146CD57468F700B415D2F470158738C@DBDE01.ent.ti.com>
References: <1362996002-15552-1-git-send-email-manishv.b@ti.com>
 <A4887BF146CD57468F700B415D2F470158738C@DBDE01.ent.ti.com>
Message-ID: <A4887BF146CD57468F700B415D2F470159537D@DBDE04.ent.ti.com>

Hi Benoit,

Are there any review comments on this patch?
Could you please accept this patch if there are not any review comments?

Thanks and Regards
Manish Badarkhe

-----Original Message-----
From: Vishwanathrao Badarkhe, Manish 
Sent: Friday, April 12, 2013 12:20 PM
To: Vishwanathrao Badarkhe, Manish; devicetree-discuss at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; linux-omap at vger.kernel.org
Cc: tony at atomide.com; Cousson, Benoit; linux at arm.linux.org.uk
Subject: RE: [PATCH] ARM: dts: omap2plus: remove interrupt-parent property

Hi Benoit,
Are there any review comments on this patch? 
Could you please accept this patch if there are not any review comments?

Thanks
Manish Badarkhe

-----Original Message-----
From: Vishwanathrao Badarkhe, Manish 
Sent: Monday, March 11, 2013 3:30 PM
To: devicetree-discuss at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; linux-omap at vger.kernel.org
Cc: tony at atomide.com; Cousson, Benoit; linux at arm.linux.org.uk; Vishwanathrao Badarkhe, Manish
Subject: [PATCH] ARM: dts: omap2plus: remove interrupt-parent property

Removed interrupt-parent property from dts file as it is already
with root node in dtsi file.

Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b at ti.com>
---
:100644 100644 f624dc8... 36e839a... M	arch/arm/boot/dts/omap3-beagle.dts
:100644 100644 e8ba1c2... a5375fd... M	arch/arm/boot/dts/omap3-evm.dts
:100644 100644 4122efe... 389c9c7... M	arch/arm/boot/dts/omap4-panda.dts
:100644 100644 43e5258... cdf5dfd... M	arch/arm/boot/dts/omap4-sdp.dts
:100644 100644 6601e6a... 1d4a9d4... M	arch/arm/boot/dts/omap4-var-som.dts
 arch/arm/boot/dts/omap3-beagle.dts  |    1 -
 arch/arm/boot/dts/omap3-evm.dts     |    1 -
 arch/arm/boot/dts/omap4-panda.dts   |    2 --
 arch/arm/boot/dts/omap4-sdp.dts     |    2 --
 arch/arm/boot/dts/omap4-var-som.dts |    1 -
 5 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index f624dc8..36e839a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -46,7 +46,6 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
-		interrupt-parent = <&intc>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index e8ba1c2..a5375fd 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -34,7 +34,6 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
-		interrupt-parent = <&intc>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 4122efe..389c9c7 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -119,7 +119,6 @@
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
 		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
-		interrupt-parent = <&gic>;
 	};
 
 	twl6040: twl at 4b {
@@ -127,7 +126,6 @@
 		reg = <0x4b>;
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
 		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
-		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
 		vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 43e5258..cdf5dfd 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -221,7 +221,6 @@
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
 		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
-		interrupt-parent = <&gic>;
 	};
 
 	twl6040: twl at 4b {
@@ -229,7 +228,6 @@
 		reg = <0x4b>;
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
 		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
-		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
 		vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6601e6a..1d4a9d4 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -35,7 +35,6 @@
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
 		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
-		interrupt-parent = <&gic>;
 	};
 };
 
-- 
1.7.4.1



From alexandre.belloni at free-electrons.com  Mon May 27 08:46:52 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 14:46:52 +0200
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <51A34BF9.5000905@atmel.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
 <51A34BF9.5000905@atmel.com>
Message-ID: <51A355BC.6090309@free-electrons.com>

On 27/05/2013 14:05, Nicolas Ferre wrote:
> On 27/05/2013 12:48, Alexandre Belloni :
>> Fixes:
>> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
>> :(.text+0x1174): undefined reference to `mdiobus_write'
>> :(.text+0x1188): undefined reference to `mdiobus_write'
>> :(.text+0x119c): undefined reference to `mdiobus_write'
>> :(.text+0x11b0): undefined reference to `mdiobus_write'
>> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
>> :(.init.text+0x1e34): undefined reference to
>> `phy_register_fixup_for_uid'
>>
>> when CONFIG_PHYLIB is not selected.
>>
>> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
>> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>> ---
>> Changes in v3:
>>     added SoB
>>     added Acked-By
>
> A v3 is not needed simply for this. Thanks, anyway!
>

It was not much and I have to stop forgetting my SoB ;)

> One question though: why not just add
>
>         select PHYLIB
>
> In Kconfig entry:
>
>  config MACH_SAMA5_DT
>
> ?
>

That would simply mean that you have to enable NET when using a SAMA5
which is not what every user will want.

Regards,

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From arnd at arndb.de  Mon May 27 08:47:35 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 14:47:35 +0200
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <1369655404.3557.33.camel@pasglop>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <51A33447.80305@gmail.com> <1369655404.3557.33.camel@pasglop>
Message-ID: <2255648.0KEmXfjCx5@wuerfel>

On Monday 27 May 2013 21:50:04 Benjamin Herrenschmidt wrote:
> However, that wouldn't help much with the allocation/leak problem,
> though at least it would be easier to use. It could also *try* to re-use
> the current allocation if the new content is of smaller or equal size.

I thought that dtc tried to aggressively save space by folding identical
strings. If you tried to reuse a property that had its contents shared
with another one, you would get interesting results I guess.

	Arnd


From ulf.hansson at linaro.org  Mon May 27 08:49:03 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Mon, 27 May 2013 14:49:03 +0200
Subject: [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for
 u8540 and u9540
In-Reply-To: <1369658492-31358-2-git-send-email-philippe.begnic.st@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
 <1369658492-31358-2-git-send-email-philippe.begnic.st@gmail.com>
Message-ID: <CAPDyKFo1J5Dt-iMtfL=Gf4_5ooTuapDzVBwq9s6zFGY7O4TUfA@mail.gmail.com>

On 27 May 2013 14:41, Philippe Begnic <philippe.begnic.st at gmail.com> wrote:
> From: Philippe Begnic <philippe.begnic at st.com>
>
> Align on u8500 version, pass clock base address in clk_init functions
> for u8540 and u9540.
>
> Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
> Signed-off-by: Philippe Begnic <philippe.begnic at st.com>
> ---
>  arch/arm/mach-ux500/cpu.c               |    6 ++++--
>  drivers/clk/ux500/u8540_clk.c           |    4 ++--
>  drivers/clk/ux500/u9540_clk.c           |    4 ++--
>  include/linux/platform_data/clk-ux500.h |    6 ++++--
>  4 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
> index b6145ea..e6fb023 100644
> --- a/arch/arm/mach-ux500/cpu.c
> +++ b/arch/arm/mach-ux500/cpu.c
> @@ -76,13 +76,15 @@ void __init ux500_init_irq(void)
>         } else if (cpu_is_u9540()) {
>                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
>                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
> -               u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
> +               u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
>                                U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
>                                U8500_CLKRST6_BASE);
>         } else if (cpu_is_u8540()) {
>                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
>                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
> -               u8540_clk_init();
> +               u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
> +                              U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
> +                              U8500_CLKRST6_BASE);
>         }
>  }
>
> diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
> index 10adfd2..90f3c88 100644
> --- a/drivers/clk/ux500/u8540_clk.c
> +++ b/drivers/clk/ux500/u8540_clk.c
> @@ -12,10 +12,10 @@
>  #include <linux/clk-provider.h>
>  #include <linux/mfd/dbx500-prcmu.h>
>  #include <linux/platform_data/clk-ux500.h>
> -
>  #include "clk.h"
>
> -void u8540_clk_init(void)
> +void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
> +                   u32 clkrst5_base, u32 clkrst6_base)
>  {
>         /* register clocks here */
>  }
> diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
> index dbc0191..4479478 100644
> --- a/drivers/clk/ux500/u9540_clk.c
> +++ b/drivers/clk/ux500/u9540_clk.c
> @@ -12,10 +12,10 @@
>  #include <linux/clk-provider.h>
>  #include <linux/mfd/dbx500-prcmu.h>
>  #include <linux/platform_data/clk-ux500.h>
> -
>  #include "clk.h"
>
> -void u9540_clk_init(void)
> +void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
> +                   u32 clkrst5_base, u32 clkrst6_base)
>  {
>         /* register clocks here */
>  }
> diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
> index 320d9c3..9d98f3a 100644
> --- a/include/linux/platform_data/clk-ux500.h
> +++ b/include/linux/platform_data/clk-ux500.h
> @@ -12,7 +12,9 @@
>
>  void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
>                     u32 clkrst5_base, u32 clkrst6_base);
> -void u9540_clk_init(void);
> -void u8540_clk_init(void);
> +void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
> +                   u32 clkrst5_base, u32 clkrst6_base);
> +void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
> +                   u32 clkrst5_base, u32 clkrst6_base);
>
>  #endif /* __CLK_UX500_H */
> --
> 1.7.9.5
>

Reviewed-by: Ulf Hansson <ulf.hansson at linaro.org>


From alexandre.belloni at free-electrons.com  Mon May 27 08:50:42 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 14:50:42 +0200
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <E0B30581-DD0A-46C5-B541-08F389F17018@jcrosoft.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
 <E0B30581-DD0A-46C5-B541-08F389F17018@jcrosoft.com>
Message-ID: <51A356A2.4050502@free-electrons.com>

On 27/05/2013 13:26, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On May 27, 2013, at 6:48 PM, Alexandre Belloni <alexandre.belloni at free-electrons.com> wrote:
>
>> Fixes:
>> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
>> :(.text+0x1174): undefined reference to `mdiobus_write'
>> :(.text+0x1188): undefined reference to `mdiobus_write'
>> :(.text+0x119c): undefined reference to `mdiobus_write'
>> :(.text+0x11b0): undefined reference to `mdiobus_write'
>> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
>> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
>>
>> when CONFIG_PHYLIB is not selected.
>>
>> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
>> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> no for this change
>
> add an inline version of phy_register_fixup_for_uid
>
> this will do the same for every platform

I don't actually see the added value of doing that. Using IS_BUILTIN is
readable and ensure that you will definitely be able to link. The
functions will be optimized out and removed by gcc even when you have
CONFIG_PHYLIB=m.

>> ---
>> Changes in v3:
>> 	added SoB
>> 	added Acked-By
>>
>> Changes in v2:
>> 	use IS_BUILTIN
>> 	use CONFIG_PHYLIB and not CONFIG_PHY
>>
>> arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
>> 1 file changed, 12 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
>> index 705305e..e9ce541 100644
>> --- a/arch/arm/mach-at91/board-dt-sama5.c
>> +++ b/arch/arm/mach-at91/board-dt-sama5.c
>> @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
>> #define GMII_ERCR	11
>> #define GMII_ERDWR	12
>>
>> -	/* Set delay values */
>> -	value = GMII_RCCPSR | 0x8000;
>> -	phy_write(phy, GMII_ERCR, value);
>> -	value = 0xF2F4;
>> -	phy_write(phy, GMII_ERDWR, value);
>> -	value = GMII_RRDPSR | 0x8000;
>> -	phy_write(phy, GMII_ERCR, value);
>> -	value = 0x2222;
>> -	phy_write(phy, GMII_ERDWR, value);
>> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
>> +		/* Set delay values */
>> +		value = GMII_RCCPSR | 0x8000;
>> +		phy_write(phy, GMII_ERCR, value);
>> +		value = 0xF2F4;
>> +		phy_write(phy, GMII_ERDWR, value);
>> +		value = GMII_RRDPSR | 0x8000;
>> +		phy_write(phy, GMII_ERCR, value);
>> +		value = 0x2222;
>> +		phy_write(phy, GMII_ERDWR, value);
>> +	}
>>
>> 	return 0;
>> }
>>
>> static void __init sama5_dt_device_init(void)
>> {
>> -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
>> +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
>> 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
>> 			ksz9021rn_phy_fixup);
>>
>> -- 
>> 1.8.1.2
>>


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From plagnioj at jcrosoft.com  Mon May 27 08:59:14 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 27 May 2013 20:59:14 +0800
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <51A356A2.4050502@free-electrons.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
 <E0B30581-DD0A-46C5-B541-08F389F17018@jcrosoft.com>
 <51A356A2.4050502@free-electrons.com>
Message-ID: <8424D480-48DA-4094-AE68-6A6A66F8FE2B@jcrosoft.com>


On May 27, 2013, at 8:50 PM, Alexandre Belloni <alexandre.belloni at free-electrons.com> wrote:

> On 27/05/2013 13:26, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On May 27, 2013, at 6:48 PM, Alexandre Belloni <alexandre.belloni at free-electrons.com> wrote:
>> 
>>> Fixes:
>>> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
>>> :(.text+0x1174): undefined reference to `mdiobus_write'
>>> :(.text+0x1188): undefined reference to `mdiobus_write'
>>> :(.text+0x119c): undefined reference to `mdiobus_write'
>>> :(.text+0x11b0): undefined reference to `mdiobus_write'
>>> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
>>> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
>>> 
>>> when CONFIG_PHYLIB is not selected.
>>> 
>>> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
>>> Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>> no for this change
>> 
>> add an inline version of phy_register_fixup_for_uid
>> 
>> this will do the same for every platform
> 
> I don't actually see the added value of doing that. Using IS_BUILTIN is
> readable and ensure that you will definitely be able to link. The
> functions will be optimized out and removed by gcc even when you have
> CONFIG_PHYLIB=m.

no will not as you do ifdef CONFIG_PHYLIB and if CONFIG_PHYLIB=m the macro is defended

we do this all the time in the kernel

I add the IS_BUILTIN & co to be used when a simple inline is not sufficient

Best Regards,
J/
> 
>>> ---
>>> Changes in v3:
>>> 	added SoB
>>> 	added Acked-By
>>> 
>>> Changes in v2:
>>> 	use IS_BUILTIN
>>> 	use CONFIG_PHYLIB and not CONFIG_PHY
>>> 
>>> arch/arm/mach-at91/board-dt-sama5.c | 22 ++++++++++++----------
>>> 1 file changed, 12 insertions(+), 10 deletions(-)
>>> 
>>> diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
>>> index 705305e..e9ce541 100644
>>> --- a/arch/arm/mach-at91/board-dt-sama5.c
>>> +++ b/arch/arm/mach-at91/board-dt-sama5.c
>>> @@ -47,22 +47,24 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
>>> #define GMII_ERCR	11
>>> #define GMII_ERDWR	12
>>> 
>>> -	/* Set delay values */
>>> -	value = GMII_RCCPSR | 0x8000;
>>> -	phy_write(phy, GMII_ERCR, value);
>>> -	value = 0xF2F4;
>>> -	phy_write(phy, GMII_ERDWR, value);
>>> -	value = GMII_RRDPSR | 0x8000;
>>> -	phy_write(phy, GMII_ERCR, value);
>>> -	value = 0x2222;
>>> -	phy_write(phy, GMII_ERDWR, value);
>>> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
>>> +		/* Set delay values */
>>> +		value = GMII_RCCPSR | 0x8000;
>>> +		phy_write(phy, GMII_ERCR, value);
>>> +		value = 0xF2F4;
>>> +		phy_write(phy, GMII_ERDWR, value);
>>> +		value = GMII_RRDPSR | 0x8000;
>>> +		phy_write(phy, GMII_ERCR, value);
>>> +		value = 0x2222;
>>> +		phy_write(phy, GMII_ERDWR, value);
>>> +	}
>>> 
>>> 	return 0;
>>> }
>>> 
>>> static void __init sama5_dt_device_init(void)
>>> {
>>> -	if (of_machine_is_compatible("atmel,sama5d3xcm"))
>>> +	if (of_machine_is_compatible("atmel,sama5d3xcm") && IS_BUILTIN(CONFIG_PHYLIB))
>>> 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
>>> 			ksz9021rn_phy_fixup);
>>> 
>>> -- 
>>> 1.8.1.2
>>> 
> 
> 
> -- 
> Alexandre Belloni, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
> 



From Ganesh.Kumar at harman.com  Mon May 27 09:01:23 2013
From: Ganesh.Kumar at harman.com (Kumar, Ganesh)
Date: Mon, 27 May 2013 08:01:23 -0500
Subject: VDSO for arm 32bit
Message-ID: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>

Hi All,

? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is
no support for vdso for arm 32 bit.
I'm planning to port it to arm 32 bit, is there any work under progress?
would like to understand why the support for arm 32 bit is not there, any idea?

Thanks for your time.

Thanks,
GK


From ulf.hansson at stericsson.com  Mon May 27 09:16:06 2013
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 May 2013 15:16:06 +0200
Subject: [PATCH] ARM: nomadik: Update MMC defconfigs
Message-ID: <1369660566-18997-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Enable MMC_UNSAFE_RESUME to accomplish a proper suspend/resume cycle
for SD/SDIO/(e)MMC.

ARMMMCI host driver supports clock gating through runtime PM, thus
MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
enabled, to skip unnecessary bounce buffer copying.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/configs/nhk8815_defconfig |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index b01e763..606a080 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -94,7 +94,8 @@ CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
 # CONFIG_HWMON is not set
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
-- 
1.7.10



From viresh.kumar at linaro.org  Mon May 27 09:29:07 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Mon, 27 May 2013 18:59:07 +0530
Subject: [RFC V7 PATCH 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <CAKohpom1jofi9bBrJ54OmeP8M83FfHALN=khDx7iADPF3PvZwg@mail.gmail.com>

On 27 May 2013 17:55, Manjunath Goudar <manjunath.goudar at linaro.org> wrote:
> This series of patches begins the process of splitting ohci-hcd up into
> a core library module and independent pci driver modules.
>
> Patch 1/3 prepares the way by exporting a few functions from ohci-hcd
> and adding a new mechanism for platform-specific drivers to initialize
> their hc_driver structures.  This deserves to be done in the core
> because almost all of the entries in these structures are pure
> boilerplate -- practically none of the drivers need to override more
> than three of the standard core values.
>
> Patch 2/3 is part of separating the ohci pci host controller
> driver from ohci-hcd host code.
> Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
> and EXPORTed, this is part of the effort to move the ohci pci related
> code to generic pci code.
>
> Patch 3/3  separate out ohci-pci into independent driver modules.

You need to tell everybody what has changed from V6 to V7..


From ulf.hansson at linaro.org  Mon May 27 09:29:31 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Mon, 27 May 2013 15:29:31 +0200
Subject: [PATCH 3/6] ARM: ux500: Enable support for RPMB and Reliable
 Write for eMMC
In-Reply-To: <CACRpkdbcQNAUNYnHwLRm2f+LdRmQZY=U9PBk8CPPxONmQFtXmg@mail.gmail.com>
References: <1369314830-3727-1-git-send-email-ulf.hansson@stericsson.com>
 <1369314830-3727-4-git-send-email-ulf.hansson@stericsson.com>
 <CACRpkdbcQNAUNYnHwLRm2f+LdRmQZY=U9PBk8CPPxONmQFtXmg@mail.gmail.com>
Message-ID: <CAPDyKFqu=G6uz28wracu4VZ7DSy117j7oY9HGVsoRHO7eCn-HA@mail.gmail.com>

On 27 May 2013 13:30, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Thu, May 23, 2013 at 3:13 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:
>
>> From: Ulf Hansson <ulf.hansson at linaro.org>
>>
>> By adding MMC_CAP_CMD23 for the eMMC devices, we can support RPMB
>> and Reliable Write. Additionally it will mean CMD12 will not be sent
>> to end a successful data transfer.
>>
>> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
>
> Patch applied to ux500-core, thanks,
> but Houston, we have a problem:
>
> I wanted to enable this also for the device tree boot
> path. But currently there are no bindings to state in the
> DT boot that CMD23 is supported.

I should have realized that you were digging into this and should have
added such information in the commit msg/patch info. Sorry for that.
Anyway, I guess you see why I wanted to totally split the DT from
non-DT patches. :-)

>
> Could you create another patch that:
>
> - Add bindings to Documentation/devicetree/bindings/mmc/mmc.txt
>   for indicating that a host controller supports CMD23
> - Patch the ux500 DTS files to enable it.
> - Write a patch to mmci.c to augment
>   mmci_dt_populate_generic_pdata() to read the binding and
>   augment the caps from the device tree.
>
> There is also a complicated refactoring that need to happen any
> of these days:
>
> - Augment the MMC core and all drivers using DT boots to
>   parse any standard caps from the device tree insteaf of
>   putting code like mmci_dt_populate_generic_pdata() into
>   every driver.

Some parts of this is already done, the mmc common DT parse function
is called "mmc_of_parse". As of today it does not support CMD23 cap
though.
mmci should switch to use this function and drop the mmci specific dt function.

Kind regards
Ulf Hansson

>
> Yours,
> Linus Walleij


From linus.walleij at linaro.org  Mon May 27 09:34:30 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 15:34:30 +0200
Subject: [PATCH] ARM: u300: Update MMC configs for u300 defconfig
In-Reply-To: <1369658515-18774-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369658515-18774-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdYTrcfbB9qD5ZEvEKivuUo+YYWfTWVtvL092X-EOw1nBg@mail.gmail.com>

On Mon, May 27, 2013 at 2:41 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> Enable MMC_UNSAFE_RESUME to be accomplish a proper suspend/resume cycle
> for SD/SDIO/(e)MMC.
>
> ARMMMCI host driver supports clock gating through runtime PM, thus
> MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
> means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
> enabled, to skip unnecessary bounce buffer copying.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Thanks, patch applied to my u300 branch!

Yours,
Linus Walleij


From grant.likely at secretlab.ca  Mon May 27 09:38:54 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 27 May 2013 14:38:54 +0100
Subject: [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs()
 function
In-Reply-To: <20130503214629.397359626@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.397359626@linutronix.de>
Message-ID: <CACxGe6tyLY3+arq2iwTZWVJ73zOtAemstX-E98i=Mo3kNjqHRw@mail.gmail.com>

On Fri, May 3, 2013 at 10:50 PM, Thomas Gleixner <tglx at linutronix.de> wrote:
> From: Gerlando Falauto <gerlando.falauto at keymile.com>
>
> Since we already have an irq_data_get_chip_type() function which returns
> a pointer to irq_chip_type, use that instead of cur_regs().
>
> Signed-off-by: Gerlando Falauto <gerlando.falauto at keymile.com>
> Cc: Lennert Buytenhek <kernel at wantstofly.org>
> Cc: Simon Guinot <simon at sequanux.org>
> Cc: Joey Oravec <joravec at drewtech.com>
> Cc: Ben Dooks <ben-linux at fluff.org>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Holger Brunck <Holger.Brunck at keymile.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

g.


From grant.likely at secretlab.ca  Mon May 27 09:45:11 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 27 May 2013 14:45:11 +0100
Subject: [RFC patch 6/8] genirq: Split out code in generic chip
In-Reply-To: <20130503214629.741399680@linutronix.de>
References: <alpine.LFD.2.02.1305031514230.2886@ionos>
 <20130503212258.385818955@linutronix.de>
 <20130503214629.741399680@linutronix.de>
Message-ID: <CACxGe6tBxySNPrVCqtyLA5q1QcwnUyzScWsMsT7K-kku+9ZS=Q@mail.gmail.com>

On Fri, May 3, 2013 at 10:50 PM, Thomas Gleixner <tglx at linutronix.de> wrote:
> Preparatory patch for linear interrupt domains.
>
> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>

The first 6 are pretty straight forward. On patches 1-6:
Acked-by: Grant Likely <grant.likely at linaro.org>

I'm reading through 7 & 8 now.

g.


From linus.walleij at stericsson.com  Mon May 27 09:55:20 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 27 May 2013 15:55:20 +0200
Subject: [PATCH] pinctrl: pinconf: take the right mutex
Message-ID: <1369662920-31339-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The pinconf_dgb_config_print() takes the per-pincontroller
mutex, when what it wants to take is actually the pin maps
mutex.

Reported-by: James Hogan <james.hogan at imgtec.com>
Cc: Patrice Chotard <patrice.chotard at st.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinconf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index c67c37e..694c3ac 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -610,7 +610,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
 	bool found = false;
 	unsigned long config;
 
-	mutex_lock(&pctldev->mutex);
+	mutex_lock(&pinctrl_maps_mutex);
 
 	/* Parse the pinctrl map and look for the elected pin/state */
 	for_each_maps(maps_node, i, map) {
@@ -659,7 +659,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
 		confops->pin_config_config_dbg_show(pctldev, s, config);
 
 exit:
-	mutex_unlock(&pctldev->mutex);
+	mutex_unlock(&pinctrl_maps_mutex);
 
 	return 0;
 }
-- 
1.7.11.3



From mikpe at it.uu.se  Mon May 27 09:53:19 2013
From: mikpe at it.uu.se (Mikael Pettersson)
Date: Mon, 27 May 2013 15:53:19 +0200
Subject: VDSO for arm 32bit
In-Reply-To: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
Message-ID: <20899.25935.838288.45383@pilspetsen.it.uu.se>

Kumar, Ganesh writes:
 > Hi All,
 > 
 > ? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is
 > no support for vdso for arm 32 bit.
 > I'm planning to port it to arm 32 bit, is there any work under progress?
 > would like to understand why the support for arm 32 bit is not there, any idea?

32-bit ARM has a "kuser" page at a fixed virtual address, which exports a
few critical routines to user-space.  With that, a vdso is mostly redundant.


From linus.walleij at linaro.org  Mon May 27 09:57:13 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 May 2013 15:57:13 +0200
Subject: [PATCH v3] pinctrl: move subsystem mutex to pinctrl_dev struct
In-Reply-To: <CAAG0J990rqDdG5WdOrVGqZ9tFgJmnmP18S=c6o9JNygTLHS6=g@mail.gmail.com>
References: <1366988907-13485-1-git-send-email-linus.walleij@stericsson.com>
 <CAAG0J990rqDdG5WdOrVGqZ9tFgJmnmP18S=c6o9JNygTLHS6=g@mail.gmail.com>
Message-ID: <CACRpkda4s_Qq-R3wZ0BQSxLWm1udR4Or=h28QdEcwt6BnwEb7A@mail.gmail.com>

On Fri, May 24, 2013 at 5:22 PM, James Hogan <james.hogan at imgtec.com> wrote:
> On 26 April 2013 16:08, Linus Walleij <linus.walleij at stericsson.com> wrote:
>> @@ -608,7 +610,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
>>         bool found = false;
>>         unsigned long config;
>>
>> -       mutex_lock(&pinctrl_mutex);
>> +       mutex_lock(&pctldev->mutex);
>>
>>         /* Parse the pinctrl map and look for the elected pin/state */
>>         for_each_maps(maps_node, i, map) {
>
> This change causes an oops on v3.10-rc2 when you read pinconf-config
> because pctldev is initialised to NULL and not set until inside the
> loop.

It is taking the wrong mutex. The function right below it is
also iterating the maps, and then it shall take the maps
mutex and nothing else.

I just sent a patch fixing it up.

> If this debugfs file
> isn't meant to be specific to a pinctrl device should it be in the
> root pinctrl directory instead of in each pinctrl device's directory?

Yes. We need to fix this after this immediate fixup, for the next
merge window.

Yours,
Linus Walleij


From sergei.shtylyov at cogentembedded.com  Mon May 27 10:04:37 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 27 May 2013 18:04:37 +0400
Subject: [PATCH] ARM: shmobile: sh7372 pinmux platform device cleanup
In-Reply-To: <1369648782-8024-2-git-send-email-horms+renesas@verge.net.au>
References: <1369648782-8024-1-git-send-email-horms+renesas@verge.net.au>
 <1369648782-8024-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <51A367F5.5040500@cogentembedded.com>

Hello.

On 27-05-2013 13:59, Simon Horman wrote:

> From: Magnus Damm <damm at opensource.se>

> Use DEFINE_RES_MEM() and platform_device_register_simple()
> to save a couple of lines of code.

> Signed-off-by: Magnus Damm <damm at opensource.se>
> Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>   arch/arm/mach-shmobile/setup-sh7372.c |   24 +++++-------------------
>   1 file changed, 5 insertions(+), 19 deletions(-)

> diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
> index 5502d62..c70a3cc 100644
> --- a/arch/arm/mach-shmobile/setup-sh7372.c
> +++ b/arch/arm/mach-shmobile/setup-sh7372.c
> @@ -62,29 +62,15 @@ void __init sh7372_map_io(void)
[...]
> +static const struct resource pfc_resources[] = {

    This should have been annotated with __initdata... too late now, 
need another patch.

> +	DEFINE_RES_MEM(0xe6050000, 0x8000),
> +	DEFINE_RES_MEM(0xe605800c, 0x001c),
>   };
>
>   void __init sh7372_pinmux_init(void)
>   {
> -	platform_device_register(&sh7372_pfc_device);
> +	platform_device_register_simple("pfc-sh7372", -1, pfc_resources,
> +					ARRAY_SIZE(pfc_resources));
>   }

WBR, Sergei



From monstr at monstr.eu  Mon May 27 10:05:17 2013
From: monstr at monstr.eu (Michal Simek)
Date: Mon, 27 May 2013 16:05:17 +0200
Subject: [GIT PULL] arm-soc: Xilinx zynq core - smp for v3.10
In-Reply-To: <20130524112610.GX18614@n2100.arm.linux.org.uk>
References: <890ef3b8-f536-4b00-9bd8-5ea50de3bf51@DB8EHSMHS032.ehs.local>
 <20130524112610.GX18614@n2100.arm.linux.org.uk>
Message-ID: <51A3681D.1000107@monstr.eu>

Hi Russell,

On 05/24/2013 01:26 PM, Russell King - ARM Linux wrote:
> On Thu, Apr 04, 2013 at 09:47:09AM +0200, Michal Simek wrote:
>> Hi Arnd and Olof,
>>
>> please pull the following smp support to your arm-soc tree.
>>
>> This branch is based on zynq/clksrc/cleanup parts because
>> there are some dependencies on moving timer to generic location.
>>
>> I could based it on standard Linux tagged version but you will get
>> several conflicts you will have to resolve.
>> If you are OK to resolving these problems, please let me know
>> I will create another branch with core-smp changes which are not based
>> on zynq/clksrc/cleanup branch.
> 
> You might want to resolve this new warning:
> 
> arch/arm/mach-zynq/hotplug.c:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march= switch
> 
> found by lastnights OMAP4430 randconfig build.

I have looked at it. (I downloaded .config last week to have).
I have tried gcc 4.6.3 from kernel.org
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/
and also (Sourcery CodeBench Lite 2011.09-50) 4.6.1 toolchain
but I can't see this warning.

Which gcc version do you use?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From sergei.shtylyov at cogentembedded.com  Mon May 27 10:13:22 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 27 May 2013 18:13:22 +0400
Subject: [PATCH 1/8] ARM: shmobile: sh73a0 pinmux platform device cleanup
In-Reply-To: <1369645252-3847-2-git-send-email-horms+renesas@verge.net.au>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
 <1369645252-3847-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <51A36A02.9050200@cogentembedded.com>

Hello.

On 27-05-2013 13:00, Simon Horman wrote:

> From: Magnus Damm <damm at opensource.se>

> Use DEFINE_RES_MEM() and platform_device_register_simple()
> to save a couple of lines of code.

> Signed-off-by: Magnus Damm <damm at opensource.se>
> Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>   arch/arm/mach-shmobile/setup-sh73a0.c |   25 ++++++-------------------
>   1 file changed, 6 insertions(+), 19 deletions(-)

> diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> index fdf3894..f8f4261 100644
> --- a/arch/arm/mach-shmobile/setup-sh73a0.c
> +++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> @@ -61,29 +61,16 @@ void __init sh73a0_map_io(void)
[...]
> +/* PFC */
> +static const struct resource pfc_resources[] = {

    Should have been annotated as __initdata... too late, need another 
patch.

> +	DEFINE_RES_MEM(0xe6050000, 0x8000),
> +	DEFINE_RES_MEM(0xe605801c, 0x000c),
>   };
>
>   void __init sh73a0_pinmux_init(void)
>   {
> -	platform_device_register(&sh73a0_pfc_device);
> +	platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
> +					ARRAY_SIZE(pfc_resources));
>   }

WBR, Sergei



From plagnioj at jcrosoft.com  Mon May 27 10:13:06 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 27 May 2013 16:13:06 +0200
Subject: [PATCH 1/1] mmc: of_mmc_spi: fix card detect irq
In-Reply-To: <51A25ECA.2060001@cogentembedded.com>
References: <1369571337-9300-1-git-send-email-plagnioj@jcrosoft.com>
 <51A25ECA.2060001@cogentembedded.com>
Message-ID: <20130527141306.GS24476@game.jcrosoft.org>

On 23:13 Sun 26 May     , Sergei Shtylyov wrote:
> Hello.
> 
> On 05/26/2013 04:28 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> >set missing irq type the IRQF_ONESHOT
> >
> >Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >Cc: stable <stable at vger.kernel.org> # 3.4+
> >Cc: linux-mmc at vger.kernel.org
> >---
> >  drivers/mmc/host/of_mmc_spi.c |    4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
> >index d720b5e..cfb2e61 100644
> >--- a/drivers/mmc/host/of_mmc_spi.c
> >+++ b/drivers/mmc/host/of_mmc_spi.c
> >@@ -74,8 +74,8 @@ static int of_mmc_spi_init(struct device *dev,
> >  {
> >  	struct of_mmc_spi *oms = to_of_mmc_spi(dev);
> >-	return request_threaded_irq(oms->detect_irq, NULL, irqhandler, 0,
> >-				    dev_name(dev), mmc);
> >+	return request_threaded_irq(oms->detect_irq, NULL, irqhandler,
> >+		IRQF_ONESHOT, dev_name(dev), mmc);
> 
>     Please don't change the indentation.
too long > 80

Best Regards,
J.


From sanjay.rawat at linaro.org  Mon May 27 10:32:37 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:37 +0530
Subject: [PATCH 0/8] ARM: use cpu_do_idle for entering wfi mode
Message-ID: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>

With this patch set we make use of cpu_do_idle to enter WFI mode,
many platform are not clearing the data buffer before WFI or
directly using the address instead of opcode. For the rest its good
to have a common approach.

Sanjay Singh Rawat (8):
  ARM: EXYNOS: use generic cpu idle function for wfi
  ARM: RealView: use generic cpu idle function for wfi
  ARM: SPEAr: use generic cpu idle function for wfi
  ARM: vexpress: use generic cpu idle function for wfi
  ARM: zynq: use generic cpu idle function for wfi
  ARM: ux500: use generic cpu idle function for wfi
  ARM: msm: use generic cpu idle function for wfi
  ARM: PRIMA2: use generic cpu idle function for wfi

 arch/arm/mach-exynos/hotplug.c   |    9 ++-------
 arch/arm/mach-msm/hotplug.c      |    9 ++-------
 arch/arm/mach-prima2/hotplug.c   |    4 ++--
 arch/arm/mach-realview/hotplug.c |    9 ++-------
 arch/arm/mach-spear/hotplug.c    |    3 ++-
 arch/arm/mach-ux500/hotplug.c    |    5 +++--
 arch/arm/mach-vexpress/hotplug.c |    3 ++-
 arch/arm/mach-zynq/hotplug.c     |    4 ++--
 8 files changed, 17 insertions(+), 29 deletions(-)

-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:38 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:38 +0530
Subject: [PATCH 1/8] ARM: EXYNOS: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-2-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the WFI mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-exynos/hotplug.c |    9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index af90cfa..7fcedd8 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -98,13 +98,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 		if (cpu == 1)
 			__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
 
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
+		/* enter WFI mode */
+		cpu_do_idle();
 
 		if (pen_release == cpu_logical_map(cpu)) {
 			/*
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:39 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:39 +0530
Subject: [PATCH 2/8] ARM: RealView: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-3-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-realview/hotplug.c |    9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index ac22dd4..c42022b 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -59,13 +59,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 	 * code will have already disabled interrupts
 	 */
 	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
+		/* enter WFI mode */
+		cpu_do_idle();
 
 		if (pen_release == cpu_logical_map(cpu)) {
 			/*
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:40 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:40 +0530
Subject: [PATCH 3/8] ARM: SPEAr: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-4-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-spear/hotplug.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-spear/hotplug.c b/arch/arm/mach-spear/hotplug.c
index d97749c..6dbd3dc 100644
--- a/arch/arm/mach-spear/hotplug.c
+++ b/arch/arm/mach-spear/hotplug.c
@@ -55,7 +55,8 @@ static inline void cpu_leave_lowpower(void)
 static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
 {
 	for (;;) {
-		wfi();
+		/* enter WFI mode */
+		cpu_do_idle();
 
 		if (pen_release == cpu) {
 			/*
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:41 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:41 +0530
Subject: [PATCH 4/8] ARM: vexpress: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-5-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-vexpress/hotplug.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index f0ce6b8..b3dffc2 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -60,7 +60,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 	 * code will have already disabled interrupts
 	 */
 	for (;;) {
-		wfi();
+		/* enter WFI mode */
+		cpu_do_idle();
 
 		if (pen_release == cpu_logical_map(cpu)) {
 			/*
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:42 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:42 +0530
Subject: [PATCH 5/8] ARM: zynq: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-6-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-zynq/hotplug.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
index c89672b..ef0d65d 100644
--- a/arch/arm/mach-zynq/hotplug.c
+++ b/arch/arm/mach-zynq/hotplug.c
@@ -64,8 +64,8 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
 	 * code will have already disabled interrupts
 	 */
 	for (;;) {
-		dsb();
-		wfi();
+		/* enter WFI mode */
+		cpu_do_idle();
 
 		/*
 		 * Getting here, means that we have come out of WFI without
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:44 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:44 +0530
Subject: [PATCH 7/8] ARM: msm: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-8-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-msm/hotplug.c |    9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 326a872..1b03e5f 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -26,13 +26,8 @@ static inline void platform_do_lowpower(unsigned int cpu)
 {
 	/* Just enter wfi for now. TODO: Properly shut off the cpu. */
 	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm("wfi"
-		    :
-		    :
-		    : "memory", "cc");
+		/* enter WFI mode */
+		cpu_do_idle();
 
 		if (pen_release == cpu_logical_map(cpu)) {
 			/*
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:43 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:43 +0530
Subject: [PATCH 6/8] ARM: ux500: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-7-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-ux500/hotplug.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index 2bc00b0..f4ded92 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -25,8 +25,9 @@ void __ref ux500_cpu_die(unsigned int cpu)
 {
 	/* directly enter low power state, skipping secure registers */
 	for (;;) {
-		__asm__ __volatile__("dsb\n\t" "wfi\n\t"
-				: : : "memory");
+		/* enter WFI mode */
+		cpu_do_idle();
+
 		if (pen_release == cpu_logical_map(cpu)) {
 			/*
 			 * OK, proper wakeup, we're done
-- 
1.7.9.5



From sanjay.rawat at linaro.org  Mon May 27 10:32:45 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Mon, 27 May 2013 20:02:45 +0530
Subject: [PATCH 8/8] ARM: PRIMA2: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <1369665166-13049-9-git-send-email-sanjay.rawat@linaro.org>

use cpu_do_idle for entering the wfi mode.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-prima2/hotplug.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
index 0ab2f8b..68d2903 100644
--- a/arch/arm/mach-prima2/hotplug.c
+++ b/arch/arm/mach-prima2/hotplug.c
@@ -16,8 +16,8 @@ static inline void platform_do_lowpower(unsigned int cpu)
 {
 	/* we put the platform to just WFI */
 	for (;;) {
-		__asm__ __volatile__("dsb\n\t" "wfi\n\t"
-			: : : "memory");
+		cpu_do_idle();
+
 		if (pen_release == cpu_logical_map(cpu)) {
 			/*
 			 * OK, proper wakeup, we're done
-- 
1.7.9.5



From afzal at ti.com  Mon May 27 10:33:27 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:03:27 +0530
Subject: [PATCH v2 00/14] ARM: OMAP2+: AM43x initial support
Message-ID: <cover.1369658705.git.afzal@ti.com>

Hi,

This series adds initial support for AM43x based SoC's. To boot
AM43x, in addition to these patches, PRCM support is also needed,
which would be posted later as a separate series. DT sources doesn't
have "ti,hwmod" entry - this would be added along with PRCM support.

AM43x SoC's are based on ARM Cortex-A9 with one core. AM43x is similar
to AM335x in it's peripheral capabilities, except a few additional
ones, with many of the peripheral register mapping's similar. AM43x
has a sync timer, which is being used as clocksource. Clockevent used
is 1ms dmtimer.

SoC has PL310 L2 cache, support for it would be added later.

soc_is_am43xx() is introduced to handle AM43x specific details and
soc_is_am437x() is a subclass of it - first member of the class.

AM43x is currently in pre-silicon stage and currently there are no
public documents.

This has been tested on a pre-silicon platform that emulates AM43x SoC
with additional changes on top of this.

AM335x based board (AM335x EVM) has been verfied to boot as earlier
with this series.

Baseline: v3.10-rc3
Dependency: "ARM: OMAP3+: am33xx id: Add new am33xx specific function to check dev_feature"
		by Vaibhav Hiremath <hvaibhav at ti.com>

Regards
Afzal

v2: Major change - use SoC timer's outside of ARM instead of depending
	on ARM SMP local timer for clockevent/source.

Afzal Mohammed (13):
  ARM: OMAP2+: separate out OMAP4 restart
  ARM: OMAP2+: AM43x: Kconfig
  ARM: OMAP2+: AM43x: kbuild
  ARM: OMAP2+: AM43x: soc_is support
  ARM: OMAP2+: AM437x: SoC revision detection
  ARM: OMAP2+: AM43x: static mapping
  ARM: OMAP2+: AM43x: early init
  ARM: OMAP2+: AM43x: GP or HS ?
  ARM: OMAP2+: AM43x: basic dt support
  Documentation: dt: binding: omap: am43x timer
  Documentation: dt: binding: omap: am43x counter
  Documentation: dt: binding: serial: omap: am43x
  ARM: dts: AM43x: initial support

Sanjeev Premi (1):
  ARM: OMAP2+: AM43x: SRAM base and size

 .../devicetree/bindings/arm/omap/counter.txt       |  1 +
 .../devicetree/bindings/arm/omap/timer.txt         |  2 +
 .../devicetree/bindings/serial/omap_serial.txt     |  1 +
 arch/arm/boot/dts/am4372.dtsi                      | 66 ++++++++++++++++++++++
 arch/arm/mach-omap2/Kconfig                        | 10 ++++
 arch/arm/mach-omap2/Makefile                       |  8 +++
 arch/arm/mach-omap2/am33xx.h                       |  1 +
 arch/arm/mach-omap2/board-generic.c                | 16 ++++++
 arch/arm/mach-omap2/cm33xx.h                       |  2 +-
 arch/arm/mach-omap2/common.h                       |  1 +
 arch/arm/mach-omap2/id.c                           |  8 ++-
 arch/arm/mach-omap2/io.c                           | 18 +++++-
 arch/arm/mach-omap2/omap4-common.c                 | 16 ------
 arch/arm/mach-omap2/omap4-restart.c                | 27 +++++++++
 arch/arm/mach-omap2/soc.h                          | 23 ++++++++
 arch/arm/mach-omap2/sram.c                         |  3 +
 arch/arm/mach-omap2/timer.c                        |  2 +-
 17 files changed, 184 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/boot/dts/am4372.dtsi
 create mode 100644 arch/arm/mach-omap2/omap4-restart.c

-- 
1.7.12



From afzal at ti.com  Mon May 27 10:35:19 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:05:19 +0530
Subject: [PATCH v2 01/14] ARM: OMAP2+: separate out OMAP4 restart
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <5f0f6150bbb195bb338feaa2db45580301061635.1369658705.git.afzal@ti.com>

Separate out OMAP4 restart and have it similar to other platforms, in
a different file. Main motive is to reuse omap4-common on platforms
other than OMAP4, like AM43x, even if OMAP4 is deselected (otherwise
would have caused build breakage).

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/Makefile        |  2 ++
 arch/arm/mach-omap2/omap4-common.c  | 16 ----------------
 arch/arm/mach-omap2/omap4-restart.c | 27 +++++++++++++++++++++++++++
 3 files changed, 29 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/mach-omap2/omap4-restart.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..0fac8f4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -58,6 +58,8 @@ obj-$(CONFIG_SOC_OMAP2420)		+= omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)		+= omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)		+= am33xx-restart.o
 obj-$(CONFIG_ARCH_OMAP3)		+= omap3-restart.o
+obj-$(CONFIG_ARCH_OMAP4)		+= omap4-restart.o
+obj-$(CONFIG_SOC_OMAP5)			+= omap4-restart.o
 
 # Pin multiplexing
 obj-$(CONFIG_SOC_OMAP2420)		+= mux2420.o
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ff..38cd3a6 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -339,19 +339,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 	return 0;
 }
 #endif
-
-/**
- * omap44xx_restart - trigger a software restart of the SoC
- * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
- * @cmd: passed from the userspace program rebooting the system (if provided)
- *
- * Resets the SoC.  For @cmd, see the 'reboot' syscall in
- * kernel/sys.c.  No return value.
- */
-void omap44xx_restart(char mode, const char *cmd)
-{
-	/* XXX Should save 'cmd' into scratchpad for use after reboot */
-	omap4_prminst_global_warm_sw_reset(); /* never returns */
-	while (1);
-}
-
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
new file mode 100644
index 0000000..f90e02e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -0,0 +1,27 @@
+/*
+ * omap4-restart.c - Common to OMAP4 and OMAP5
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include "prminst44xx.h"
+
+/**
+ * omap44xx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void omap44xx_restart(char mode, const char *cmd)
+{
+	/* XXX Should save 'cmd' into scratchpad for use after reboot */
+	omap4_prminst_global_warm_sw_reset(); /* never returns */
+	while (1)
+		;
+}
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:35:31 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:05:31 +0530
Subject: [PATCH v2 02/14] ARM: OMAP2+: AM43x: Kconfig
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <7642e0c701680ea94a8cc84059ff19e500813bf1.1369658705.git.afzal@ti.com>

Kconfig for AM43x (Cortex A9) family of SoC's.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---

v2: Remove reliance on SMP, TWD, select MACH_OMAP_GENERIC

 arch/arm/mach-omap2/Kconfig | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..8f555f8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -149,6 +149,16 @@ config SOC_AM33XX
 	select MULTI_IRQ_HANDLER
 	select COMMON_CLK
 
+config SOC_AM43XX
+	bool "TI AM43x"
+	depends on ARCH_OMAP2PLUS
+	default y
+	select CPU_V7
+	select MULTI_IRQ_HANDLER
+	select ARM_GIC
+	select COMMON_CLK
+	select MACH_OMAP_GENERIC
+
 config OMAP_PACKAGE_ZAF
        bool
 
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:35:41 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:05:41 +0530
Subject: [PATCH v2 03/14] ARM: OMAP2+: AM43x: kbuild
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <4a5c2cf13c7985658cdf506fa30ff286e1c80c13.1369658705.git.afzal@ti.com>

Build pieces that could be reused for AM43x - GIC related, secure
related and common PRCM.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/Makefile | 6 ++++++
 arch/arm/mach-omap2/cm33xx.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0fac8f4..955b643 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
 obj-$(CONFIG_SOC_OMAP5)	 += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
@@ -38,6 +39,7 @@ omap-4-5-common				=  omap4-common.o omap-wakeupgen.o \
 					   sleep44xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common) $(smp-y)
 obj-$(CONFIG_SOC_OMAP5)			+= $(omap-4-5-common) $(smp-y)
+obj-$(CONFIG_SOC_AM43XX)		+= $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
@@ -112,6 +114,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= prm33xx.o cm33xx.o
+obj-$(CONFIG_SOC_AM43XX)		+= prm33xx.o cm33xx.o
 omap-prcm-4-5-common			=  cminst44xx.o cm44xx.o prm44xx.o \
 					   prcm_mpu44xx.o prminst44xx.o \
 					   vc44xx_data.o vp44xx_data.o
@@ -128,6 +131,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= voltagedomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)		+= $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)			+= $(voltagedomain-common)
 
 # OMAP powerdomain framework
@@ -142,6 +146,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)		+= powerdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)		+= $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)			+= $(powerdomain-common)
 
 # PRCM clockdomain control
@@ -157,6 +162,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)		+= clockdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)		+= $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)			+= $(clockdomain-common)
 
 # Clock framework
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 64f4baf..9d1f4fc 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
 					u16 clkctrl_offs);
 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:36:01 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:06:01 +0530
Subject: [PATCH v2 05/14] ARM: OMAP2+: AM437x: SoC revision detection
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <1aa201188d55a4fb5b4d039bff379207321de144.1369658705.git.afzal@ti.com>

Detect 437x SoC revision.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/id.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 44be835..c9c3f7d 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
 		cpu_name = "TI816X";
 	} else if (soc_is_am335x()) {
 		cpu_name =  "AM335X";
+	} else if (soc_is_am437x()) {
+		cpu_name =  "AM437x";
 	} else if (cpu_is_ti814x()) {
 		cpu_name = "TI814X";
 	} else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -443,6 +445,10 @@ void __init omap3xxx_check_revision(void)
 			break;
 		}
 		break;
+	case 0xb98c:
+		omap_revision = AM437X_REV_ES1_0;
+		cpu_rev = "1.0";
+		break;
 	case 0xb8f2:
 		switch (rev) {
 		case 0:
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:35:51 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:05:51 +0530
Subject: [PATCH v2 04/14] ARM: OMAP2+: AM43x: soc_is support
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <6bf3b1a4c215cc404262d107e69543b8d5ed005c.1369658705.git.afzal@ti.com>

soc_is support for AM43x family of SoC's. Only variant now is AM437x,
it is made as a subclass of AM43x.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/soc.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index fd4507b..f59fdcd 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -96,6 +96,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_AM43XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am43xx
+# endif
+#endif
+
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
  */
@@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
 IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
+IS_AM_CLASS(43xx, 0x43)
 
 IS_TI_CLASS(81xx, 0x81)
 
@@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543)
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
 IS_AM_SUBCLASS(335x, 0x335)
+IS_AM_SUBCLASS(437x, 0x437)
 
 #define cpu_is_omap24xx()		0
 #define cpu_is_omap242x()		0
@@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define soc_is_am35xx()			0
 #define soc_is_am33xx()			0
 #define soc_is_am335x()			0
+#define soc_is_am43xx()			0
+#define soc_is_am437x()			0
 #define cpu_is_omap44xx()		0
 #define cpu_is_omap443x()		0
 #define cpu_is_omap446x()		0
@@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define soc_is_am335x()		is_am335x()
 #endif
 
+#ifdef	CONFIG_SOC_AM43XX
+# undef soc_is_am43xx
+# undef soc_is_am437x
+# define soc_is_am43xx()		is_am43xx()
+# define soc_is_am437x()		is_am437x()
+#endif
+
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
@@ -398,6 +418,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_REV_ES2_0	(AM335X_CLASS | (0x1 << 8))
 #define AM335X_REV_ES2_1	(AM335X_CLASS | (0x2 << 8))
 
+#define AM437X_CLASS		0x43700000
+#define AM437X_REV_ES1_0	AM437X_CLASS
+
 #define OMAP443X_CLASS		0x44300044
 #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0	(OMAP443X_CLASS | (0x20 << 8))
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:36:13 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:06:13 +0530
Subject: [PATCH v2 06/14] ARM: OMAP2+: AM43x: static mapping
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <c58538b01232c0bc0ad342dd89204acdf6778aa7.1369658705.git.afzal@ti.com>

AM43x L4 WKUP/PER mappings are similar to AM335x, reuse.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/io.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 06a8946..3a81221 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static struct map_desc omapam33xx_io_desc[] __initdata = {
 	{
 		.virtual	= L4_34XX_VIRT,
@@ -318,7 +318,7 @@ void __init ti81xx_map_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 void __init am33xx_map_io(void)
 {
 	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:36:23 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:06:23 +0530
Subject: [PATCH v2 07/14] ARM: OMAP2+: AM43x: early init
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <82f3b2b672a45b971fd0bb34366a6af368015db0.1369658705.git.afzal@ti.com>

Minimal early init - PRCM initialization not yet taken care.

Control module is similar (base address, feature register etc.) as
that of AM335x, while PRCM base address is different. Instead of
adding a new header file for AM43x, PRCM base address is added in
AM335x header file as it is similar to it to a large extent.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/am33xx.h |  1 +
 arch/arm/mach-omap2/common.h |  1 +
 arch/arm/mach-omap2/io.c     | 14 ++++++++++++++
 3 files changed, 16 insertions(+)

diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 43296c1..5eef093 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,6 +21,7 @@
 #define AM33XX_SCM_BASE		0x44E10000
 #define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
 #define AM33XX_PRCM_BASE	0x44E00000
+#define AM43XX_PRCM_BASE	0x44DF0000
 #define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + 0x3FC)
 
 #endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..00f890e 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -96,6 +96,7 @@ void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void am33xx_init_early(void);
+void am43xx_init_early(void);
 void omap4430_init_early(void);
 void omap5_init_early(void);
 void omap3_init_late(void);	/* Do not use this one */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3a81221..f933f7f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -586,6 +586,20 @@ void __init am33xx_init_early(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_AM43XX
+void __init am43xx_init_early(void)
+{
+	omap2_set_globals_tap(AM335X_CLASS,
+			      AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
+	omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+				  NULL);
+	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
+	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+	omap3xxx_check_revision();
+	am33xx_check_features();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:36:33 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:06:33 +0530
Subject: [PATCH v2 08/14] ARM: OMAP2+: AM43x: GP or HS ?
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <7c2e50ddc9c6a3395147fbe1395985daf93abe8f.1369658705.git.afzal@ti.com>

Detect whether GP or HS, similar to the AM335x way.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/id.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index c9c3f7d..0c28ef6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
 
 	if (cpu_is_omap24xx()) {
 		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-	} else if (soc_is_am33xx()) {
+	} else if (soc_is_am33xx() || soc_is_am43xx()) {
 		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
 	} else if (cpu_is_omap34xx()) {
 		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:36:42 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:06:42 +0530
Subject: [PATCH v2 09/14] ARM: OMAP2+: AM43x: SRAM base and size
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <7dd913330dbe9f364b7b27e5fd02180ce2a584c0.1369658705.git.afzal@ti.com>

From: Sanjeev Premi <premi at ti.com>

This definition corresponds to the L3_OCMC0,
as in case of AM33XX.

Signed-off-by: Sanjeev Premi <premi at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/sram.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 0ff0f06..4bd0968 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -119,6 +119,9 @@ static void __init omap_detect_sram(void)
 		if (soc_is_am33xx()) {
 			omap_sram_start = AM33XX_SRAM_PA;
 			omap_sram_size = 0x10000; /* 64K */
+		} else if (soc_is_am43xx()) {
+			omap_sram_start = AM33XX_SRAM_PA;
+			omap_sram_size = SZ_256K;
 		} else if (cpu_is_omap34xx()) {
 			omap_sram_start = OMAP3_SRAM_PA;
 			omap_sram_size = 0x10000; /* 64K */
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:36:53 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:06:53 +0530
Subject: [PATCH v2 10/14] ARM: OMAP2+: AM43x: basic dt support
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <2a3357fbbd9f103aa55cf720f64f6313d5133040.1369658705.git.afzal@ti.com>

Describe minimal DT boot machine details for AM43x based SoC's. AM43x
SoC's are ARM Cortex-A9 based with one core. AM43x is similar to
AM335x w.r.t L4 PER/WKUP memory map. AM43x has a sync timer, here that
is being used as clocksource, while 1ms dmtimer as clockevent.

Signed-off-by: Ankur Kishore <a-kishore at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
---

v2: Rely on dmtimer & synctimer for clockevent/source, map peripheral
	memory as in AM335x

 arch/arm/mach-omap2/board-generic.c | 16 ++++++++++++++++
 arch/arm/mach-omap2/timer.c         |  2 +-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 88aa6b1..e5fbfed 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -185,3 +185,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
 	.restart	= omap44xx_restart,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_SOC_AM43XX
+static const char *am43_boards_compat[] __initdata = {
+	"ti,am43",
+	NULL,
+};
+
+DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
+	.map_io		= am33xx_map_io,
+	.init_early	= am43xx_init_early,
+	.init_irq	= omap_gic_of_init,
+	.init_machine	= omap_generic_init,
+	.init_time	= omap3_sync32k_timer_init,
+	.dt_compat	= am43_boards_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 8e0c390..5f148e7 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
 			2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
 			2, "timer_sys_ck", NULL);
 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:37:04 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:07:04 +0530
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>

AM43x timer bindings.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 Documentation/devicetree/bindings/arm/omap/timer.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
index d02e27c..70cb398 100644
--- a/Documentation/devicetree/bindings/arm/omap/timer.txt
+++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
@@ -14,6 +14,8 @@ Required properties:
 			ti,omap5430-timer (applicable to OMAP543x devices)
 			ti,am335x-timer	(applicable to AM335x devices)
 			ti,am335x-timer-1ms (applicable to AM335x devices)
+			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
+			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
 
 - reg:			Contains timer register address range (base address and
 			length).
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:37:14 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:07:14 +0530
Subject: [PATCH v2 12/14] Documentation: dt: binding: omap: am43x counter
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <755964dc45ae4f023540c05e5739fca87d0ea70b.1369658705.git.afzal@ti.com>

AM43x 32K counter binding.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 Documentation/devicetree/bindings/arm/omap/counter.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt
index 5bd8aa0..9c48dca 100644
--- a/Documentation/devicetree/bindings/arm/omap/counter.txt
+++ b/Documentation/devicetree/bindings/arm/omap/counter.txt
@@ -2,6 +2,7 @@ OMAP Counter-32K bindings
 
 Required properties:
 - compatible:	Must be "ti,omap-counter32k" for OMAP controllers
+		"ti,am4372-counter32k","ti,omap-counter32k" for AM43x counter
 - reg:		Contains timer register address range (base address and length)
 - ti,hwmods:	Name of the hwmod associated to the counter, which is typically
 		"counter_32k"
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:37:25 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:07:25 +0530
Subject: [PATCH v2 13/14] Documentation: dt: binding: serial: omap: am43x
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <c25bea2491ad5137ece8d924e5c20e46f6e2886b.1369658705.git.afzal@ti.com>

AM43x uart binding.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 Documentation/devicetree/bindings/serial/omap_serial.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
index 342eedd..f37fdda 100644
--- a/Documentation/devicetree/bindings/serial/omap_serial.txt
+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- compatible : "ti,am4372-uart","ti,omap2-uart" for AM43x controller
 - ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
 
 Optional properties:
-- 
1.7.12



From afzal at ti.com  Mon May 27 10:37:36 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Mon, 27 May 2013 20:07:36 +0530
Subject: [PATCH v2 14/14] ARM: dts: AM43x: initial support
In-Reply-To: <cover.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
Message-ID: <3790fa57fc4c69da12224fbcec17cd07c59771a0.1369658705.git.afzal@ti.com>

DT source (minimal) for AM4372 SoC to represent AM43x SoC's. Those
represented here are the minimal DT nodes necessary to get kernel
booting.

In DT nodes, "ti,hwmod" property has not been added, this would be
added along with PRCM support for AM43x.

Signed-off-by: Ankur Kishore <a-kishore at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
---

v2: Add gptimer 1ms, timer2, synctimer and remove twd local timer

 arch/arm/boot/dts/am4372.dtsi | 66 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/am4372.dtsi

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
new file mode 100644
index 0000000..1d58298
--- /dev/null
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Device Tree Source for AM4372 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "ti,am4372", "ti,am43";
+	interrupt-parent = <&gic>;
+
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+		};
+	};
+
+	gic: interrupt-controller at 48241000 {
+		compatible = "arm,cortex-a9-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x48241000 0x1000>,
+		      <0x48240100 0x0100>;
+	};
+
+	ocp {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart1: serial at 44e09000 {
+			compatible = "ti,am4372-uart","ti,omap2-uart";
+			reg = <0x44e09000 0x2000>;
+			interrupts = <0 72 0x4>;
+		};
+
+		timer1: timer at 44e31000 {
+			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
+			reg = <0x44e31000 0x400>;
+			interrupts = <0 67 0x4>;
+			ti,timer-alwon;
+		};
+
+		timer2: timer at 48040000  {
+			compatible = "ti,am4372-timer","ti,am335x-timer";
+			reg = <0x48040000  0x400>;
+			interrupts = <0 68 0x4>;
+		};
+
+		counter32k: counter at 44e86000 {
+			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+			reg = <0x44e86000 0x40>;
+		};
+	};
+};
-- 
1.7.12



From florian.vaussard at epfl.ch  Mon May 27 10:52:29 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 16:52:29 +0200
Subject: [PATCH v3 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
Message-ID: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

Following a similar proposal by Stephen Warren for tegra [1], this series
makes use of the C preprocessor when compiling OMAP DT files, and
accomplishes some improvements to improve overall readability.

Patch 1 is a preparation for the rest of the series.
Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
it to simplify pinctrl DT.

As for v2, the .dtb files were diff-tested before and after
applying the series to guarantee identity for all targets.

Best regards,

Florian

>From v2:
- Address Tony's comments (standardize comments, remove OMAP_ prefix)

>From v1:
- Remove duplicated fix
- Remove OMAP_GPIO macro
- Add pinctrl constants

Florian Vaussard (5):
  ARM: dts: OMAP2+: use #include for all device trees
  ARM: dts: OMAP2+: use existing constants for GPIOs
  ARM: dts: OMAP4/5: use existing constants for IRQs
  ARM: dts: OMAP2+: header file for pinctrl constants
  ARM: dts: OMAP2+: use pinctrl constants

 arch/arm/boot/dts/omap2.dtsi              |    5 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    8 +-
 arch/arm/boot/dts/omap3-beagle.dts        |   34 ++++----
 arch/arm/boot/dts/omap3-devkit8000.dts    |   10 +-
 arch/arm/boot/dts/omap3-evm.dts           |    6 +-
 arch/arm/boot/dts/omap3-igep.dtsi         |   36 ++++----
 arch/arm/boot/dts/omap3-igep0020.dts      |   10 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |   10 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 +-
 arch/arm/boot/dts/omap3-tobi.dts          |    4 +-
 arch/arm/boot/dts/omap3.dtsi              |    5 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 +-
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |   10 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   66 ++++++++--------
 arch/arm/boot/dts/omap4-panda-es.dts      |   10 +-
 arch/arm/boot/dts/omap4-panda.dts         |    4 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |  122 ++++++++++++++--------------
 arch/arm/boot/dts/omap4-var-som.dts       |    8 +-
 arch/arm/boot/dts/omap4.dtsi              |  118 ++++++++++++++-------------
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    6 +-
 arch/arm/boot/dts/omap5-evm.dts           |   92 +++++++++++-----------
 arch/arm/boot/dts/omap5.dtsi              |  126 +++++++++++++++--------------
 include/dt-bindings/pinctrl/omap.h        |   50 +++++++++++
 30 files changed, 416 insertions(+), 352 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/omap.h

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Mon May 27 10:52:33 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 16:52:33 +0200
Subject: [PATCH v3 4/5] ARM: dts: OMAP2+: header file for pinctrl constants
In-Reply-To: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369666354-29152-5-git-send-email-florian.vaussard@epfl.ch>

Most of the constants are taken from arch/arm/mach-omap2/mux.h.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 include/dt-bindings/pinctrl/omap.h |   50 ++++++++++++++++++++++++++++++++++++
 1 files changed, 50 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/omap.h

diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
new file mode 100644
index 0000000..370df3f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -0,0 +1,50 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA		(1 << 3)
+#define PULL_UP			(1 << 4)
+#define ALTELECTRICALSEL	(1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN		(1 << 8)
+#define OFF_EN			(1 << 9)
+#define OFFOUT_EN		(1 << 10)
+#define OFFOUT_VAL		(1 << 11)
+#define OFF_PULL_EN		(1 << 12)
+#define OFF_PULL_UP		(1 << 13)
+#define WAKEUP_EN		(1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT		0
+#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE		0
+#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
+
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Mon May 27 10:52:31 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 16:52:31 +0200
Subject: [PATCH v3 2/5] ARM: dts: OMAP2+: use existing constants for GPIOs
In-Reply-To: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369666354-29152-3-git-send-email-florian.vaussard@epfl.ch>

Use standard GPIO constants to enhance the readability of DT GPIOs.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 ++
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    6 +++---
 arch/arm/boot/dts/omap3-devkit8000.dts    |    6 +++---
 arch/arm/boot/dts/omap3-evm.dts           |    2 +-
 arch/arm/boot/dts/omap3-igep0020.dts      |    8 ++++----
 arch/arm/boot/dts/omap3-igep0030.dts      |    8 ++++----
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 ++
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-sdp.dts           |   16 ++++++++--------
 arch/arm/boot/dts/omap4.dtsi              |    2 ++
 arch/arm/boot/dts/omap5.dtsi              |    2 ++
 13 files changed, 36 insertions(+), 28 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index e6e4587..f39b237 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index e0ce823..1e580d9 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -29,13 +29,13 @@
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index fcac96a..434288f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -28,18 +28,18 @@
 		compatible = "gpio-leds";
 		pmu_stat {
 			label = "beagleboard::pmu_stat";
-			gpios = <&twl_gpio 19 0>; /* LEDB */
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 		};
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8d0f5e4..5be71b1 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -22,21 +22,21 @@
 
 		heartbeat {
 			label = "devkit8000::led1";
-			gpios = <&gpio6 26 0>;	/* 186 -> LED1 */
+			gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;	/* 186 -> LED1 */
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "devkit8000::led2";
-			gpios = <&gpio6 3 0>;	/* 163 -> LED2 */
+			gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;	/* 163 -> LED2 */
 			default-state = "on";
 			linux,default-trigger = "none";
 		};
 
 		usr {
 			label = "devkit8000::led3";
-			gpios = <&gpio6 4 0>;	/* 164 -> LED3 */
+			gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;	/* 164 -> LED3 */
 			default-state = "on";
 			linux,default-trigger = "usr";
                 };
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index d75759b..baa24bb 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -28,7 +28,7 @@
 		compatible = "gpio-leds";
 		ledb {
 			label = "omap3evm::ledb";
-			gpios = <&twl_gpio 19 0>; /* LEDB */
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 			linux,default-trigger = "default-on";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 2f96a5c..659e57c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -19,25 +19,25 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&gpio1 26 0>;
+			 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&gpio1 27 0>;
+			 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 28 0>;
+			 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 			 default-state = "off";
 		};
 
 		user2 {
 			label = "omap3:green:user1";
-			gpios = <&twl_gpio 19 1>;
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index f3a1bf0..8d3baef 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -19,25 +19,25 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&twl_gpio 13 1>;
+			 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&twl_gpio 18 1>; /* LEDA */
+			 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:green:user1";
-			 gpios = <&twl_gpio 19 1>; /* LEDB */
+			 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
 			 default-state = "off";
 		};
 
 		user2 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 16 1>;
+			 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 			 default-state = "off";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 5df894f..c7eebbf 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -20,7 +20,7 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "overo:red:gpio21";
-			gpios = <&gpio1 21 0>;
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7c7d494..aede64d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 63148d1..a3ef2bd 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -20,13 +20,13 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "pandaboard::status1";
-			gpios = <&gpio1 7 0>;
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "pandaboard::status2";
-			gpios = <&gpio1 8 0>;
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5edd08e..564d19b 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -41,42 +41,42 @@
 		compatible = "gpio-leds";
 		debug0 {
 			label = "omap4:green:debug0";
-			gpios = <&gpio2 29 0>; /* 61 */
+			gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
 		};
 
 		debug1 {
 			label = "omap4:green:debug1";
-			gpios = <&gpio1 30 0>; /* 30 */
+			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
 		};
 
 		debug2 {
 			label = "omap4:green:debug2";
-			gpios = <&gpio1 7 0>; /* 7 */
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
 		};
 
 		debug3 {
 			label = "omap4:green:debug3";
-			gpios = <&gpio1 8 0>; /* 8 */
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
 		};
 
 		debug4 {
 			label = "omap4:green:debug4";
-			gpios = <&gpio2 18 0>; /* 50 */
+			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
 		};
 
 		user1 {
 			label = "omap4:blue:user";
-			gpios = <&gpio6 9 0>; /* 169 */
+			gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
 		};
 
 		user2 {
 			label = "omap4:red:user";
-			gpios = <&gpio6 10 0>; /* 170 */
+			gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
 		};
 
 		user3 {
 			label = "omap4:green:user";
-			gpios = <&gpio5 11 0>; /* 139 */
+			gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 53d80aa..00f6ab9 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,6 +14,8 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e8e6653..d613bf5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -15,6 +15,8 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Mon May 27 10:52:30 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 16:52:30 +0200
Subject: [PATCH v3 1/5] ARM: dts: OMAP2+: use #include for all device trees
In-Reply-To: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369666354-29152-2-git-send-email-florian.vaussard@epfl.ch>

Replace /include/ by #include for OMAP2+ DT, in order to use the
C pre-processor, making use of #define features possible.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    4 ++--
 arch/arm/boot/dts/omap3-devkit8000.dts    |    4 ++--
 arch/arm/boot/dts/omap3-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap3-igep.dtsi         |    4 ++--
 arch/arm/boot/dts/omap3-igep0020.dts      |    2 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |    2 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 ++--
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 ++--
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-panda-es.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda.dts         |    4 ++--
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    2 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +++---
 arch/arm/boot/dts/omap4-var-som.dts       |    4 ++--
 arch/arm/boot/dts/omap4.dtsi              |    2 +-
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    2 +-
 arch/arm/boot/dts/omap5-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap5.dtsi              |    2 +-
 29 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..e6e4587 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee..224c08f 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 
 / {
 	model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285..c8f9c55 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc44..c535a5a 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..e0ce823 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard xM";
@@ -75,7 +75,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..fcac96a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard";
@@ -107,7 +107,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc..8d0f5e4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
 	model = "TimLL OMAP3 Devkit8000";
 	compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -80,7 +80,7 @@
 	status = "disabled";
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c20..d75759b 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -44,7 +44,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index f8fe3b7..54588b0 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	memory {
@@ -80,7 +80,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e2b9849..2f96a5c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEPv2";
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 9dc48d2..f3a1bf0 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEP COM Module";
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50..e112a42 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	pwmleds {
@@ -49,7 +49,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 /* i2c2 pins are used for gpio */
 &i2c2 {
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12d..5df894f 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 
 / {
 	model = "TI OMAP3 Gumstix Overo on Tobi";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..7c7d494 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap3430", "ti,omap3";
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43..2a725a0 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3430 SDP";
@@ -28,7 +28,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae..5355d61 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc..f8b3765 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0..f18fb5c 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..63148d1 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 PandaBoard";
@@ -164,7 +164,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c6f012e 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f..6189a8b 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ff..4f26355 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd..5edd08e 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 SDP board";
@@ -316,7 +316,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103..6593607 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 
 / {
 	model = "Variscite OMAP4 SOM";
@@ -39,7 +39,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..53d80aa 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,7 +14,7 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..a81f8df 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..41762c2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 982acd1..f5f55d1 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
+#include "omap5.dtsi"
+#include "samsung_k3pe0e000b.dtsi"
 
 / {
 	model = "TI OMAP5 EVM board";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..e8e6653 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -15,7 +15,7 @@
  */
 /memreserve/ 0x9d000000 0x03000000;
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	#address-cells = <1>;
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Mon May 27 10:52:34 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 16:52:34 +0200
Subject: [PATCH v3 5/5] ARM: dts: OMAP2+: use pinctrl constants
In-Reply-To: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369666354-29152-6-git-send-email-florian.vaussard@epfl.ch>

Using constants for pinctrl allows a better readability, and remove
redundancy with comments.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/boot/dts/omap2.dtsi              |    1 +
 arch/arm/boot/dts/omap3-beagle.dts        |   24 ++++----
 arch/arm/boot/dts/omap3-igep.dtsi         |   32 +++++-----
 arch/arm/boot/dts/omap3.dtsi              |    1 +
 arch/arm/boot/dts/omap4-panda-a4.dts      |    6 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   50 ++++++++--------
 arch/arm/boot/dts/omap4-panda-es.dts      |    6 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    6 +-
 arch/arm/boot/dts/omap4-sdp.dts           |   94 ++++++++++++++--------------
 arch/arm/boot/dts/omap4.dtsi              |    1 +
 arch/arm/boot/dts/omap5-evm.dts           |   88 +++++++++++++-------------
 arch/arm/boot/dts/omap5.dtsi              |    1 +
 12 files changed, 157 insertions(+), 153 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index f39b237..b3cc896 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 434288f..6d47c4b 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -81,18 +81,18 @@
 
 	hsusbb2_pins: pinmux_hsusbb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
-			0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
-			0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
-			0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
-			0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
-			0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
-			0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
-			0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
-			0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
-			0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
-			0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
-			0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
+			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
+			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
+			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
+			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
+			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
+			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
+			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
+			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
+			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
+			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
+			0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 54588b0..7b62b80 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -29,37 +29,37 @@
 &omap3_pmx_core {
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			0x152 0x100	/* uart1_rx.uart1_rx INPUT | MODE0 */
-			0x14c 0		/* uart1_tx.uart1_tx OUTPUT | MODE0 */
+			0x152 (PIN_INPUT | MUX_MODE0)		/* uart1_rx.uart1_rx */
+			0x14c (PIN_OUTPUT |MUX_MODE0)		/* uart1_tx.uart1_tx */
 		>;
 	};
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			0x14a 0x100	/* uart2_rx.uart2_rx INPUT | MODE0 */
-			0x148 0		/* uart2_tx.uart2_tx OUTPUT | MODE0 */
+			0x14a (PIN_INPUT | MUX_MODE0)		/* uart2_rx.uart2_rx */
+			0x148 (PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			0x16e 0x100	/* uart3_rx.uart3_rx INPUT | MODE0 */
-			0x170 0		/* uart3_tx.uart3_tx OUTPUT | MODE0 */
+			0x16e (PIN_INPUT | MUX_MODE0)		/* uart3_rx.uart3_rx */
+			0x170 (PIN_OUTPUT | MUX_MODE0)		/* uart3_tx.uart3_tx */
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			0x114 0x0118    /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
-			0x116 0x0118    /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
-			0x118 0x0118 	/* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
-			0x11a 0x0118	/* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
-			0x11c 0x0118	/* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
-			0x11e 0x0118	/* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
-			0x120 0x0100	/* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
-			0x122 0x0100	/* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
-			0x124 0x0100	/* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
-			0x126 0x0100	/* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
+			0x114 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			0x116 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
+			0x118 (PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat0.sdmmc1_dat0 */
+			0x11a (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
+			0x11c (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
+			0x11e (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
+			0x120 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat4.sdmmc1_dat4 */
+			0x122 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat5.sdmmc1_dat5 */
+			0x124 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat6.sdmmc1_dat6 */
+			0x126 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat7.sdmmc1_dat7 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index aede64d..813370d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index f18fb5c..133f1b7 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -13,8 +13,8 @@
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 16b03fd..548329e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -68,71 +68,71 @@
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-			0x160 0x100	/* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+			0xe0 (PIN_OUTPUT | MUX_MODE3)	/* hdq_sio.gpio_127 */
+			0x160 (PIN_INPUT | MUX_MODE0)	/* sys_nirq2.sys_nirq2 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0xc6 0x108	/* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-			0xc8 0x108	/* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-			0xca 0x118	/* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-			0xcc 0x108	/* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-			0xce 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+			0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_ul_data.abe_pdm_ul_data */
+			0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_dl_data.abe_pdm_dl_data */
+			0xca (PIN_INPUT_PULLUP   | MUX_MODE0)	/* abe_pdm_frame.abe_pdm_frame */
+			0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_lb_clk.abe_pdm_lb_clk */
+			0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0xbe 0x100	/* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-			0xc0 0x108	/* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-			0xc2 0x8		/* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-			0xc4 0x100	/* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+			0xbe (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+			0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dr.abe_mcbsp1_dr */
+			0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
+			0xc4 (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
 		>;
 	};
 
 	dss_hdmi_pins: pinmux_dss_hdmi_pins {
 		pinctrl-single,pins = <
-			0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-			0x5c 0x118	/* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-			0x5e 0x118	/* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+			0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+			0x5c (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_scl.hdmi_scl */
+			0x5e (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_sda.hdmi_sda */
 		>;
 	};
 
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
-			0x22 0x3	/* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-			0x48 0x3	/* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-			0x58 0x10b	/* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+			0x22 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_a17.gpio_41 */
+			0x48 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_nbe1.gpio_60 */
+			0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* hdmi_hpd.gpio_63 */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
+			0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-			0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+			0xea (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
+			0xec (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+			0xee (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
+			0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index c6f012e..5cfdf19 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -29,8 +29,8 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index 4f26355..aad5dda 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -10,8 +10,8 @@
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 509e27c..a10a91b 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -156,123 +156,123 @@
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			0xd8 0x118	/* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
-			0xda 0		/* uart2_rts.uart2_rts OUTPUT | MODE0 */
-			0xdc 0x118	/* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
-			0xde 0		/* uart2_tx.uart2_tx OUTPUT | MODE0 */
+			0xd8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_cts.uart2_cts */
+			0xda (PIN_OUTPUT | MUX_MODE0)		/* uart2_rts.uart2_rts */
+			0xdc (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_rx.uart2_rx */
+			0xde (PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			0x100 0x118	/* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
-			0x102 0		/* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
-			0x104 0x100	/* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
-			0x106 0		/* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart3_cts_rctx.uart3_cts_rctx */
+			0x102 (PIN_OUTPUT | MUX_MODE0)		/* uart3_rts_sd.uart3_rts_sd */
+			0x104 (PIN_INPUT | MUX_MODE0)		/* uart3_rx_irrx.uart3_rx_irrx */
+			0x106 (PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
 		>;
 	};
 
 	uart4_pins: pinmux_uart4_pins {
 		pinctrl-single,pins = <
-			0x11c 0x100	/* uart4_rx.uart4_rx INPUT | MODE0 */
-			0x11e 0		/* uart4_tx.uart4_tx OUTPUT | MODE0 */
+			0x11c (PIN_INPUT | MUX_MODE0)		/* uart4_rx.uart4_rx */
+			0x11e (PIN_OUTPUT | MUX_MODE0)		/* uart4_tx.uart4_tx */
 		>;
 	};
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-			0x160 0x100	/* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+			0xe0 (PIN_OUTPUT | MUX_MODE3)		/* hdq_sio.gpio_127 */
+			0x160 (PIN_INPUT | MUX_MODE0)		/* sys_nirq2.sys_nirq2 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0xc6 0x108	/* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-			0xc8 0x108	/* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-			0xca 0x118	/* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-			0xcc 0x108	/* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-			0xce 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+			0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_ul_data.abe_pdm_ul_data */
+			0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_dl_data.abe_pdm_dl_data */
+			0xca (PIN_INPUT_PULLUP | MUX_MODE0)	/* abe_pdm_frame.abe_pdm_frame */
+			0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_lb_clk.abe_pdm_lb_clk */
+			0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
 		>;
 	};
 
 	dmic_pins: pinmux_dmic_pins {
 		pinctrl-single,pins = <
-			0xd0 0		/* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
-			0xd2 0x100	/* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
-			0xd4 0x100	/* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
-			0xd6 0x100	/* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* abe_dmic_clk1.abe_dmic_clk1 */
+			0xd2 (PIN_INPUT | MUX_MODE0)		/* abe_dmic_din1.abe_dmic_din1 */
+			0xd4 (PIN_INPUT | MUX_MODE0)		/* abe_dmic_din2.abe_dmic_din2 */
+			0xd6 (PIN_INPUT | MUX_MODE0)		/* abe_dmic_din3.abe_dmic_din3 */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0xbe 0x100	/* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-			0xc0 0x108	/* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-			0xc2 0x8	/* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-			0xc4 0x100	/* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+			0xbe (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+			0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dr.abe_mcbsp1_dr */
+			0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
+			0xc4 (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
 		>;
 	};
 
 	mcbsp2_pins: pinmux_mcbsp2_pins {
 		pinctrl-single,pins = <
-			0xb6 0x100	/* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
-			0xb8 0x108	/* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
-			0xba 0x8	/* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-			0xbc 0x100	/* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+			0xb6 (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+			0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp2_dr.abe_mcbsp2_dr */
+			0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp2_dx.abe_mcbsp2_dx */
+			0xbc (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
 		>;
 	};
 
 	mcspi1_pins: pinmux_mcspi1_pins {
 		pinctrl-single,pins = <
-			0xf2 0x100	/*  mcspi1_clk.mcspi1_clk INPUT | MODE0 */
-			0xf4 0x100	/*  mcspi1_somi.mcspi1_somi INPUT | MODE0 */
-			0xf6 0x100	/*  mcspi1_simo.mcspi1_simo INPUT | MODE0 */
-			0xf8 0x100	/*  mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/
+			0xf2 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_clk.mcspi1_clk */
+			0xf4 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_somi.mcspi1_somi */
+			0xf6 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_simo.mcspi1_simo */
+			0xf8 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_cs0.mcspi1_cs0 */
 		>;
 	};
 
 	dss_hdmi_pins: pinmux_dss_hdmi_pins {
 		pinctrl-single,pins = <
-			0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-			0x5c 0x118	/* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-			0x5e 0x118	/* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+			0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+			0x5c (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_scl.hdmi_scl */
+			0x5e (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_sda.hdmi_sda */
 		>;
 	};
 
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
-			0x22 0x3	/* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-			0x48 0x3	/* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-			0x58 0x10b	/* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+			0x22 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_a17.gpio_41 */
+			0x48 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_nbe1.gpio_60 */
+			0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* hdmi_hpd.gpio_63 */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe4 0x118       /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
+			0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-			0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+			0xea (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
+			0xec (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+			0xee (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
+			0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d4304a2..ebf3108 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -16,6 +16,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index f5f55d1..22e9ee8 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -40,106 +40,106 @@
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0x18a 0x6	/* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
+			0x18a (PIN_OUTPUT | MUX_MODE6)	/* perslimbus2_clock.gpio5_145 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0x142 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
-			0x15c 0x108	/* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
-			0x15e 0x108	/* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
-			0x160 0x118	/* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
-			0x162 0x108	/* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
+			0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
+			0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_ul_data.abemcpdm_ul_data */
+			0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_dl_data.abemcpdm_dl_data */
+			0x160 (PIN_INPUT_PULLUP | MUX_MODE0)	/* abemcpdm_frame.abemcpdm_frame */
+			0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_lb_clk.abemcpdm_lb_clk */
 		>;
 	};
 
 	dmic_pins: pinmux_dmic_pins {
 		pinctrl-single,pins = <
-			0x144 0x100	/* abedmic_din1.abedmic_din1 INPUT | MODE0 */
-			0x146 0x100	/* abedmic_din2.abedmic_din2 INPUT | MODE0 */
-			0x148 0x100	/* abedmic_din3.abedmic_din3 INPUT | MODE0 */
-			0x14a 0		/* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
+			0x144 (PIN_INPUT | MUX_MODE0)		/* abedmic_din1.abedmic_din1 */
+			0x146 (PIN_INPUT | MUX_MODE0)		/* abedmic_din2.abedmic_din2 */
+			0x148 (PIN_INPUT | MUX_MODE0)		/* abedmic_din3.abedmic_din3 */
+			0x14a (PIN_OUTPUT | MUX_MODE0)		/* abedmic_clk1.abedmic_clk1 */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0x14c 0x101	/* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
-			0x14e 0x9	/* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
-			0x150 0x101	/* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
-			0x152 0x109	/* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
+			0x14c (PIN_INPUT | MUX_MODE1)		/* abedmic_clk2.abemcbsp1_fsx */
+			0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* abedmic_clk3.abemcbsp1_dx */
+			0x150 (PIN_INPUT | MUX_MODE1)		/* abeslimbus1_clock.abemcbsp1_clkx */
+			0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* abeslimbus1_data.abemcbsp1_dr */
 		>;
 	};
 
 	mcbsp2_pins: pinmux_mcbsp2_pins {
 		pinctrl-single,pins = <
-			0x154 0x108	/* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
-			0x156 0x8	/* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-			0x158 0x100	/* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
-			0x15a 0x100	/* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
+			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dr.abemcbsp2_dr */
+			0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dx.abemcbsp2_dx */
+			0x158 (PIN_INPUT | MUX_MODE0)		/* abemcbsp2_fsx.abemcbsp2_fsx */
+			0x15a (PIN_INPUT | MUX_MODE0)		/* abemcbsp2_clkx.abemcbsp2_clkx */
 		>;
 	};
 
-        i2c1_pins: pinmux_i2c1_pins {
-                pinctrl-single,pins = <
-                        0x1b2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0x1b4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
-                >;
-        };
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
+		>;
+	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			0x178 0x100        /* i2c2_scl INPUTENABLE | MODE0 */
-			0x17a 0x100        /* i2c2_sda INPUTENABLE | MODE0 */
+			0x178 (PIN_INPUT | MUX_MODE0)		/* i2c2_scl */
+			0x17a (PIN_INPUT | MUX_MODE0)		/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0x13a 0x100        /* i2c3_scl INPUTENABLE | MODE0 */
-			0x13c 0x100     /* i2c3_sda INPUTENABLE | MODE0 */
+			0x13a (PIN_INPUT | MUX_MODE0)		/* i2c3_scl */
+			0x13c (PIN_INPUT | MUX_MODE0)		/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xb8 0x100        /* i2c4_scl INPUTENABLE | MODE0 */
-			0xba 0x100     /* i2c4_sda INPUTENABLE | MODE0 */
+			0xb8 (PIN_INPUT | MUX_MODE0)		/* i2c4_scl */
+			0xba (PIN_INPUT | MUX_MODE0)		/* i2c4_sda */
 		>;
 	};
 
 	i2c5_pins: pinmux_i2c5_pins {
 		pinctrl-single,pins = <
-			0x184 0x100        /* i2c5_scl INPUTENABLE | MODE0 */
-			0x186 0x100     /* i2c5_sda INPUTENABLE | MODE0 */
+			0x184 (PIN_INPUT | MUX_MODE0)		/* i2c5_scl */
+			0x186 (PIN_INPUT | MUX_MODE0)		/* i2c5_sda */
 		>;
 	};
 
 	mcspi2_pins: pinmux_mcspi2_pins {
 		pinctrl-single,pins = <
-			0xbc 0x100	/*  MCSPI2_CLK INPUTENABLE | MODE0 */
-			0xbe 0x100	/*  MCSPI2_SIMO INPUTENABLE | MODE0 */
-			0xc0 0x118	/*  MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
-			0xc2 0x0	/*  MCSPI2_CS MODE0*/
+			0xbc (PIN_INPUT | MUX_MODE0)		/*  mcspi2_clk */
+			0xbe (PIN_INPUT | MUX_MODE0)		/*  mcspi2_simo */
+			0xc0 (PIN_INPUT_PULLUP | MUX_MODE0)	/*  mcspi2_somi */
+			0xc2 (PIN_OUTPUT | MUX_MODE0)		/*  mcspi2_cs */
 		>;
 	};
 
 	mcspi3_pins: pinmux_mcspi3_pins {
 		pinctrl-single,pins = <
-			0x78 0x101	/*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-			0x7a 0x101	/*  MCSPI2_CS INPUTENABLE | MODE1 */
-			0x7c 0x101	/*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-			0x7e 0x101	/*  MCSPI2_CLK INPUTENABLE | MODE1 */
+			0x78 (PIN_INPUT | MUX_MODE1)		/*  mcspi2_somi */
+			0x7a (PIN_INPUT | MUX_MODE1)		/*  mcspi2_cs */
+			0x7c (PIN_INPUT | MUX_MODE1)		/*  mcspi2_simo */
+			0x7e (PIN_INPUT | MUX_MODE1)		/*  mcspi2_clk */
 		>;
 	};
 
 	mcspi4_pins: pinmux_mcspi4_pins {
 		pinctrl-single,pins = <
-			0x164 0x101	/*  MCSPI2_CLK INPUTENABLE | MODE1 */
-			0x168 0x101	/*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-			0x16a 0x101	/*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-			0x16c 0x101	/*  MCSPI2_CS INPUTENABLE | MODE1 */
+			0x164 (PIN_INPUT | MUX_MODE1)		/*  mcspi2_clk */
+			0x168 (PIN_INPUT | MUX_MODE1)		/*  mcspi2_simo */
+			0x16a (PIN_INPUT | MUX_MODE1)		/*  mcspi2_somi */
+			0x16c (PIN_INPUT | MUX_MODE1)		/*  mcspi2_cs */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 061cf70..825ce300 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -17,6 +17,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Mon May 27 10:52:32 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Mon, 27 May 2013 16:52:32 +0200
Subject: [PATCH v3 3/5] ARM: dts: OMAP4/5: use existing constants for IRQs
In-Reply-To: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369666354-29152-4-git-send-email-florian.vaussard@epfl.ch>

Use the constants defined in include/dt-bindings/interrupt-controller/
to enhance readability.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +-
 arch/arm/boot/dts/omap4-var-som.dts       |    4 +-
 arch/arm/boot/dts/omap4.dtsi              |  113 ++++++++++++++-------------
 arch/arm/boot/dts/omap4460.dtsi           |    4 +-
 arch/arm/boot/dts/omap5.dtsi              |  121 +++++++++++++++--------------
 6 files changed, 129 insertions(+), 127 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index a3ef2bd..16b03fd 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -145,16 +145,16 @@
 
 	twl: twl at 48 {
 		reg = <0x48>;
-		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		/* IRQ# = 7 */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
 	twl6040: twl at 4b {
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
-		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		/* IRQ# = 119 */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 564d19b..509e27c 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -286,7 +286,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
@@ -294,7 +294,7 @@
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
@@ -375,7 +375,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <2 8>; /* gpio line 34, low triggered */
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34, low triggered */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6593607..135ba45 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -34,7 +34,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 };
@@ -68,7 +68,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <11 8>; /* gpio line 171, low triggered */
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171, low triggered */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 00f6ab9..d4304a2 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -15,6 +15,7 @@
 /memreserve/ 0x9d000000 0x03000000;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -58,7 +59,7 @@
 	local-timer at 0x48240600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x48240600 0x20>;
-		interrupts = <1 13 0x304>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	/*
@@ -99,8 +100,8 @@
 		reg = <0x44000000 0x1000>,
 		      <0x44800000 0x2000>,
 		      <0x45000000 0x1000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4a304000 {
 			compatible = "ti,omap-counter32k";
@@ -128,10 +129,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -140,7 +141,7 @@
 		gpio1: gpio at 4a310000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4a310000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -152,7 +153,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -163,7 +164,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -174,7 +175,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -185,7 +186,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -196,7 +197,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -209,7 +210,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -218,7 +219,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -226,7 +227,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -234,7 +235,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -242,7 +243,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -250,7 +251,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -259,7 +260,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -268,7 +269,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -277,7 +278,7 @@
 		i2c4: i2c at 48350000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48350000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -286,7 +287,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -306,7 +307,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -321,7 +322,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -333,7 +334,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -345,7 +346,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -356,7 +357,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -366,7 +367,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -376,7 +377,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -386,7 +387,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -396,7 +397,7 @@
 		wdt2: wdt at 4a314000 {
 			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 			reg = <0x4a314000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -405,7 +406,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -417,7 +418,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -428,7 +429,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -442,7 +443,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -456,7 +457,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -469,7 +470,7 @@
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */
 			reg-names = "mpu";
-			interrupts = <0 16 0x4>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp4";
@@ -481,7 +482,7 @@
 		keypad: keypad at 4a31c000 {
 			compatible = "ti,omap4-keypad";
 			reg = <0x4a31c000 0x80>;
-			interrupts = <0 120 0x4>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
 		};
@@ -489,7 +490,7 @@
 		emif1: emif at 4c000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4c000000 0x100>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif1";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -500,7 +501,7 @@
 		emif2: emif at 4d000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4d000000 0x100>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif2";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -525,7 +526,7 @@
 		timer1: timer at 4a318000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x4a318000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -533,21 +534,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -555,7 +556,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -564,7 +565,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 		};
@@ -573,7 +574,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -582,7 +583,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
@@ -591,7 +592,7 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
 		};
@@ -599,7 +600,7 @@
 		timer10: timer at 48086000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
 		};
@@ -607,7 +608,7 @@
 		timer11: timer at 48088000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -615,7 +616,7 @@
 		usbhstll: usbhstll at 4a062000 {
 			compatible = "ti,usbhs-tll";
 			reg = <0x4a062000 0x1000>;
-			interrupts = <0 78 0x4>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
 		};
 
@@ -631,14 +632,14 @@
 				compatible = "ti,ohci-omap3", "usb-ohci";
 				reg = <0x4a064800 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 76 0x4>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			usbhsehci: ehci at 4a064c00 {
 				compatible = "ti,ehci-omap", "usb-ehci";
 				reg = <0x4a064c00 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 77 0x4>;
+				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
 
@@ -653,7 +654,7 @@
 		usb_otg_hs: usb_otg_hs at 4a0ab000 {
 			compatible = "ti,omap4-musb";
 			reg = <0x4a0ab000 0x7ff>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 41762c2..19628b1 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -25,8 +25,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 54 0x4>,
-			     <0 55 0x4>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		ti,hwmods = "debugss";
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index d613bf5..061cf70 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -16,6 +16,7 @@
 /memreserve/ 0x9d000000 0x03000000;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -47,10 +48,10 @@
 	timer {
 		compatible = "arm,armv7-timer";
 		/* PPI secure/nonsecure IRQ, active low level-sensitive */
-		interrupts = <1 13 0x308>,
-			     <1 14 0x308>,
-			     <1 11 0x308>,
-			     <1 10 0x308>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <6144000>;
 	};
 
@@ -92,8 +93,8 @@
 		reg = <0x44000000 0x2000>,
 		      <0x44800000 0x3000>,
 		      <0x45000000 0x4000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
@@ -121,10 +122,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -133,7 +134,7 @@
 		gpio1: gpio at 4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -145,7 +146,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -156,7 +157,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -167,7 +168,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -178,7 +179,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -189,7 +190,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -200,7 +201,7 @@
 		gpio7: gpio at 48051000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48051000 0x200>;
-			interrupts = <0 35 0x4>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio7";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -211,7 +212,7 @@
 		gpio8: gpio at 48053000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48053000 0x200>;
-			interrupts = <0 121 0x4>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio8";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -224,7 +225,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -233,7 +234,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -242,7 +243,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -251,7 +252,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -260,7 +261,7 @@
 		i2c4: i2c at 4807a000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807a000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -269,7 +270,7 @@
 		i2c5: i2c at 4807c000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807c000 0x100>;
-			interrupts = <0 60 0x4>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c5";
@@ -278,7 +279,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -298,7 +299,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -313,7 +314,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -325,7 +326,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -337,7 +338,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -345,7 +346,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -353,7 +354,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -361,7 +362,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -369,7 +370,7 @@
 		uart5: serial at 48066000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48066000 0x100>;
-			interrupts = <0 105 0x4>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 		};
@@ -377,7 +378,7 @@
 		uart6: serial at 48068000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48068000 0x100>;
-			interrupts = <0 106 0x4>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 		};
@@ -385,7 +386,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -396,7 +397,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -406,7 +407,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -416,7 +417,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -426,7 +427,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -444,7 +445,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -456,7 +457,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -467,7 +468,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -481,7 +482,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -495,7 +496,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -507,7 +508,7 @@
 		timer1: timer at 4ae18000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4ae18000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -515,21 +516,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -537,7 +538,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -546,7 +547,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -556,7 +557,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -565,7 +566,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -574,21 +575,21 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 		};
 
 		timer10: timer at 48086000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 		};
 
 		timer11: timer at 48088000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -596,7 +597,7 @@
 		wdt2: wdt at 4ae14000 {
 			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 			reg = <0x4ae14000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -605,7 +606,7 @@
 			ti,hwmods	= "emif1";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4c000000 0x400>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -616,7 +617,7 @@
 			ti,hwmods	= "emif2";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4d000000 0x400>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -634,7 +635,7 @@
 			compatible = "ti,dwc3";
 			ti,hwmods = "usb_otg_ss";
 			reg = <0x4a020000 0x1000>;
-			interrupts = <0 93 4>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			utmi-mode = <2>;
@@ -642,7 +643,7 @@
 			dwc3 at 4a030000 {
 				compatible = "synopsys,dwc3";
 				reg = <0x4a030000 0x1000>;
-				interrupts = <0 92 4>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 				usb-phy = <&usb2_phy>, <&usb3_phy>;
 				tx-fifo-resize;
 			};
-- 
1.7.5.4



From stern at rowland.harvard.edu  Mon May 27 10:54:18 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Mon, 27 May 2013 10:54:18 -0400 (EDT)
Subject: [RFC V7 PATCH 1/3] USB: OHCI: prepare to make ohci-hcd a library
 module
In-Reply-To: <1369657550-24101-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305271050320.21231-100000@netrider.rowland.org>

On Mon, 27 May 2013, Manjunath Goudar wrote:

> This patch prepares ohci-hcd for being split up into a core
> library and separate platform driver modules.  A generic
> ohci_hc_driver structure is created, containing all the "standard"
> values, and a new mechanism is added whereby a driver module can
> specify a set of overrides to those values.  In addition the
> ohci_restart(),ohci_suspend() and ohci_resume() routines need
> to be EXPORTed for use by the drivers.
> 
> Added ohci_setip(() and ohci_start() routine for to start the generic
> controller rather than each having its own idiosyncratic approach.
> This allow to clean duplicated code in most of SOC driver
> 
> In V2:
>  -ohci_hcd_init() ohci_run() and ohci_stop() are not made non-static.
>  -Adds the ohci_setup() and ohci_start() routine.

There's one thing we forgot about:

> +/* ohci_setup routine for generic controller initialization */
> +
> +int ohci_setup(struct usb_hcd *hcd)
> +{
> +	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
> +
> +	return ohci_init(ohci);
> +}
> +EXPORT_SYMBOL_GPL(ohci_setup);

This routine needs to call ohci_hcd_init() before ohci_init().

Alan Stern



From stern at rowland.harvard.edu  Mon May 27 10:55:21 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Mon, 27 May 2013 10:55:21 -0400 (EDT)
Subject: [RFC V7 PATCH 2/3] USB: OHCI: Generic changes to make ohci-pci
 a separate driver
In-Reply-To: <1369657550-24101-3-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305271055020.21231-100000@netrider.rowland.org>

On Mon, 27 May 2013, Manjunath Goudar wrote:

> Note that this changes is part of separating the ohci pci host controller
> driver from ohci-hcd host code.
> This contains :
>      -Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
>       and EXPORTed, this is part of the effort to move the ohci pci related
>       code to generic pci code.
>      -Passed "device" argument instead  of "ohci_hcd" in sb800_prefetch()
>       function to avoid extra include file in pci-quirks.c.
> 
> V2:
>      -Passed "device" argment instead of "pci_dev", then we use to_pci_dev()
>       to get the "pci_dev" structure.

Acked-by: Alan Stern <stern at rowland.harvard.edu>



From thierry.reding at gmail.com  Mon May 27 10:55:57 2013
From: thierry.reding at gmail.com (Thierry Reding)
Date: Mon, 27 May 2013 16:55:57 +0200
Subject: [PATCH] clk: tegra: fix clk_out parents list
In-Reply-To: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>
References: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <20130527145557.GB9460@mithrandir>

On Mon, May 27, 2013 at 01:24:39PM +0530, Prashant Gaikwad wrote:
> Number of parents for clk_out_2 and clk_out_3 was incorrectly set
> to clk_out1_parents. Even though it did not break anything since the
> size was same better to fix.

This last part of the sentence is hard to understand, I think you meant:

	Even though it did not break anything since the size was the
	same, it should still be fixed.

Other than that:

Reviewed-by: Thierry Reding <thierry.reding at gmail.com>
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From stern at rowland.harvard.edu  Mon May 27 10:58:28 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Mon, 27 May 2013 10:58:28 -0400 (EDT)
Subject: [RFC V7 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369657550-24101-4-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305271056390.21231-100000@netrider.rowland.org>

On Mon, 27 May 2013, Manjunath Goudar wrote:

> This patch splits the PCI portion of ohci-hcd out into its
> own separate driver module, called ohci-pci.
> 
> The major point of difficulty lies in ohci-pci's many vendor- and
> device-specific workarounds.  Some of them have to be applied before
> calling ohci_start() some after, which necessitates a fair amount of
> code motion.  The other platform drivers require much smaller changes.
> 
> The complete sb800_prefetch() function moved to ohci-q.c,because its
> only related to ohci-pci driver.
> 
> V2:
>   - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
>     and rest of the generic code is written in ohci_start of ohci-hcd.c file.
> V3:
>  - ohci_restart() has been called in ohci_pci_reset() function for to reset the ohci pci.
> 
> V4:
>  -sb800_prefetch() moved to ohci-q.c,because its only related to ohci-pci.
>  -no longer _creating_ CONFIG_USB_OHCI_PCI,creating CONFIG_USB_OHCI_HCD_PCI.
>  -overrides renamed with pci_override,its giving proper meaning.
> 
> V5:
>  -sb800_prefetch() moved to pci-quirks.c,because its only related to pci.
> 
> V6:
>  -sb800_prefetch() function has been moved to pci-quirks.c made as separate patch in 2/3.
>  -Most of the generic ohci pci changes moved in 2/3 patch,now this is complete  ohci-pci separation patch.
> 
> V7:
>  -Unrelated include file has been removed from ohci.h file.

One tiny mistake still remains...

> @@ -242,94 +249,24 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
>  			ret = quirk(hcd);
>  		}
>  	}
> -	if (ret == 0) {
> -		ohci_hcd_init (ohci);
> -		return ohci_init (ohci);
> -	}

...

> +	if (ret == 0)
> +		ohci_setup(hcd);

This should say

		ret = ohci_setup(hcd);

so that errors in ohci_setup() won't be ignored.

> +	/*
> +	* After ohci setup RWC may not be set for add-in PCI cards.
> +	* This transfers PCI PM wakeup capabilities.
> +	*/
> +	if (device_can_wakeup(&pdev->dev))
> +		ohci->hc_control |= OHCI_CTRL_RWC;
>  	return ret;
>  }

Alan Stern



From arnd at arndb.de  Mon May 27 11:02:09 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 17:02:09 +0200
Subject: MUSB multiplatform work?
Message-ID: <201305271702.09203.arnd@arndb.de>

Hi Felipe,

We've gone through remaining work items for getting the ARM kernel
to full multiplatform support again, and MUSB came up. I'm sure you
have your own thoughts on this, but I'd like to know if there is
already a plan in place.

From what I can see, the driver in PIO mode should almost work
on multiple platforms, but there are a couple of compile-time
dependencies in it that need to be turned into run-time conditionals.
In particular the TUSB version seem sufficiently different that
it needs some extra work to be a true run-time option.

The DMA support as far as I can tell has never been intended to
be usable in a multiplatform setup, but that also seems doable.
Looking just at the #ifdef statements in the driver, I found
that the following things need to be addressed:

* abstract musb_write_fifo and musb_read_fifo into callbacks
* move fifo_mode setting into glue driver for runtime selection
* turn TUSB compile-time switches into run-time conditionals
* turn musb_ep_select into run-time switch
* make is_dma_capable/is_cppi_enabled/tusb_dma_omap run-time conditionals
* abtract dma_controller_create/destroy interface

Aside from this, a recent discussion with Maxime has brought up
that the Allwinner A1x platform (mach-sunxi) contains an MUSB variant
that is currently used with an independently implemented device driver,
see https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/drivers/usb/sun5i_usb
I wonder if you have any insight on how that can be integrated into
musb, or whether it is likely to be a compatible version to start with.

	Arnd


From thierry.reding at gmail.com  Mon May 27 11:10:07 2013
From: thierry.reding at gmail.com (Thierry Reding)
Date: Mon, 27 May 2013 17:10:07 +0200
Subject: [PATCH v2] clk: tegra: Use common of_clk_init function
In-Reply-To: <1369640409-1981-1-git-send-email-pgaikwad@nvidia.com>
References: <1369640409-1981-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <20130527151006.GC9460@mithrandir>

On Mon, May 27, 2013 at 01:10:09PM +0530, Prashant Gaikwad wrote:
> Use common of_clk_init() function for clocks initialization.
> 
> Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>

Reviewed-by: Thierry Reding <thierry.reding at gmail.com>
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From maarten.lankhorst at canonical.com  Mon May 27 11:23:00 2013
From: maarten.lankhorst at canonical.com (Maarten Lankhorst)
Date: Mon, 27 May 2013 17:23:00 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
Message-ID: <51A37A54.1040700@canonical.com>

Hey,

Op 27-05-13 12:38, Inki Dae schreef:
> Hi all,
>
> I have been removed previous branch and added new one with more cleanup.
> This time, the fence helper doesn't include user side interfaces and cache
> operation relevant codes anymore because not only we are not sure that
> coupling those two things, synchronizing caches and buffer access between
> CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is a
> good idea yet but also existing codes for user side have problems with badly
> behaved or crashing userspace. So this could be more discussed later.
>
> The below is a new branch,
> 	
> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/?h=dma-f
> ence-helper
>
> And fence helper codes,
> 	
> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
> h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
>
> And example codes for device driver,
> 	
> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
> h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
>
> I think the time is not yet ripe for RFC posting: maybe existing dma fence
> and reservation need more review and addition work. So I'd glad for somebody
> giving other opinions and advices in advance before RFC posting.
>
NAK.

For examples for how to handle locking properly, see Documentation/ww-mutex-design.txt in my recent tree.
I could list what I believe is wrong with your implementation, but real problem is that the approach you're taking is wrong.

~Maarten


From 21cnbao at gmail.com  Mon May 27 11:36:14 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Mon, 27 May 2013 23:36:14 +0800
Subject: [PATCH] i2c: sirf: move driver init from module_init to
 subsys_initcall
In-Reply-To: <20130527121658.GA3660@sirena.org.uk>
References: <1368672607-5536-1-git-send-email-Baohua.Song@csr.com>
 <20130516093846.GA2927@katana>
 <CAGsJ_4zVOF8-g=emEGgP3atxkWdxMaQQiVZrZkht_WueTriSnw@mail.gmail.com>
 <20130525201032.GD32043@sirena.org.uk>
 <CAGsJ_4y6SY6nNkbW+Yh8jx0WB4Pi9MO1W3xVZcrQcedGeD5ogQ@mail.gmail.com>
 <20130527121658.GA3660@sirena.org.uk>
Message-ID: <CAGsJ_4w867BhFvVze5BNaYheW75pMcOGhscz3wSZiia-neP59w@mail.gmail.com>

2013/5/27 Mark Brown <broonie at kernel.org>:
> On Mon, May 27, 2013 at 09:54:56AM +0800, Barry Song wrote:
>
>> Mark, the case is not that deferred probing is slow or not. deferred
>> probing is pretty good.
>> the case is that we want to i2c and media connected with i2c probed
>> earlier than other devices.
>> in auto infotainment devices, we actually do some hacking in kernel
>> that makes rear view work earlier than other device driver
>> initialization with a kernel thread which take care of backing-car
>> policy not only mechanism. that means, we make camera work to see
>> backview image even earlier than other drivers' initialization.
>> we don't want media deferred to wait for i2c. we want make some early
>> jobs ready earlier.
>
> So this change makes no practical difference in mainline and exists to
> support out of tree hacks for performance?  It doesn't seem like that
> big a patch to carry along with the out of tree stuff...

yes. but i don't think we are easy to make those out-of-mainline hacks
 be in mainline. but this patch is both ok to mainline and local tree.
making local tree and mainline same as many as possible decreases our
maintaince efforts totally.

-barry


From valentin.longchamp at keymile.com  Mon May 27 11:40:32 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Mon, 27 May 2013 17:40:32 +0200
Subject: [PATCH v2] ARM: kirkwood: refactor dtsi to largest common nodes
Message-ID: <1369669232-24041-1-git-send-email-valentin.longchamp@keymile.com>

Some kirkwood variants (for instance present in the prestera SoCs) do
not have all the peripherals whose nodes are declared in
kirkwood.dtsi. These missing peripherals are SATA, SDIO, and RTC.

As discussed in [1], to avoid that these missing peripherals get
initialized which could result in system hangs when accessing
undocumented/not present HW registers, their corresponding OF nodes
should not get declared at all for some kirkwood variants.

The corresponding OF nodes of these peripherals thus are moved from
kirkwood.dtsi to the kirkwood-628x.dtsi files so that they still are
initialized for these variants where they are present.

[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/167154.html

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
---

Changes in v2:
	- include kirkwood-6281.dtsi in kirkwood-nsa310.dts

 arch/arm/boot/dts/kirkwood-6281.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-6282.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-nsa310.dts |  1 +
 arch/arm/boot/dts/kirkwood.dtsi       | 24 ------------------------
 4 files changed, 49 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65..29f831e 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,29 @@
 				marvell,function = "sdio";
 			};
 		};
+
+		rtc at 10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			status = "disabled";
+		};
+
+		mvsdio at 90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e4..a1c2c05 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,30 @@
 			};
 		};
 
+		rtc at 10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			status = "disabled";
+		};
+
+		mvsdio at 90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			status = "disabled";
+		};
+
 		thermal at 10078 {
 			compatible = "marvell,kirkwood-thermal";
 			reg = <0x10078 0x4>;
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index a7412b9..4197fa0 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 
 / {
 	model = "ZyXEL NSA310";
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..39f497e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -71,13 +71,6 @@
 			status = "disabled";
 		};
 
-		rtc at 10300 {
-			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
-			reg = <0x10300 0x20>;
-			interrupts = <53>;
-			clocks = <&gate_clk 7>;
-		};
-
 		spi at 10600 {
 			compatible = "marvell,orion-spi";
 			#address-cells = <1>;
@@ -151,15 +144,6 @@
 			status = "okay";
 		};
 
-		sata at 80000 {
-			compatible = "marvell,orion-sata";
-			reg = <0x80000 0x5000>;
-			interrupts = <21>;
-			clocks = <&gate_clk 14>, <&gate_clk 15>;
-			clock-names = "0", "1";
-			status = "disabled";
-		};
-
 		nand at 3000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -194,13 +178,5 @@
 			clocks = <&gate_clk 17>;
 			status = "okay";
 		};
-
-		mvsdio at 90000 {
-			compatible = "marvell,orion-sdio";
-			reg = <0x90000 0x200>;
-			interrupts = <28>;
-			clocks = <&gate_clk 4>;
-			status = "disabled";
-		};
 	};
 };
-- 
1.8.0.1



From jason at lakedaemon.net  Mon May 27 11:41:13 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 27 May 2013 11:41:13 -0400
Subject: [PATCH 00/21] ARM: kirkwood: improve pinmux configs in Device Tree
In-Reply-To: <20130527.181018.461275386.yamagata@plathome.co.jp>
References: <1369388699-25975-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20130527.181018.461275386.yamagata@plathome.co.jp>
Message-ID: <20130527154113.GG31290@titan.lakedaemon.net>

All,

On Mon, May 27, 2013 at 06:10:18PM +0900, yamagata at plathome.co.jp wrote:
> > The last patch finally adds support for the init button of the
> > Plathome OpenBlocks A6 platform.
> 
> I have checked the init button worked well with your three patches for
> linux-3.10-rc3 and 3.9.4.
> 
> Tested-by: Atsushi Yamagata <yamagata at plathome.co.jp>

Added the above to the relevant patches, as well as Andrew's Ack's and
his Tested-by's on topkick and ts219.

FYI: mvebu/dt has been rebased *after* tags/dt-3.11-2.  Actually, I
rebased after '0e99b15 arm: mvebu: enable two USB interfaces on the
Armada XP GP board'.  The important thing is that what was rebased is
*not* in arm-soc, nor has a pending PR for arm-soc.

thx,

Jason.


From robdclark at gmail.com  Mon May 27 11:47:54 2013
From: robdclark at gmail.com (Rob Clark)
Date: Mon, 27 May 2013 11:47:54 -0400
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
Message-ID: <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>

On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
> Hi all,
>
> I have been removed previous branch and added new one with more cleanup.
> This time, the fence helper doesn't include user side interfaces and cache
> operation relevant codes anymore because not only we are not sure that
> coupling those two things, synchronizing caches and buffer access between
> CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is a
> good idea yet but also existing codes for user side have problems with badly
> behaved or crashing userspace. So this could be more discussed later.
>
> The below is a new branch,
>
> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/?h=dma-f
> ence-helper
>
> And fence helper codes,
>
> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
> h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
>
> And example codes for device driver,
>
> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
> h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
>
> I think the time is not yet ripe for RFC posting: maybe existing dma fence
> and reservation need more review and addition work. So I'd glad for somebody
> giving other opinions and advices in advance before RFC posting.

thoughts from a *really* quick, pre-coffee, first look:
* any sort of helper to simplify single-buffer sort of use-cases (v4l)
probably wouldn't want to bake in assumption that seqno_fence is used.
* I guess g2d is probably not actually a simple use case, since I
expect you can submit blits involving multiple buffers :-P
* otherwise, you probably don't want to depend on dmabuf, which is why
reservation/fence is split out the way it is..  you want to be able to
use a single reservation/fence mechanism within your driver without
having to care about which buffers are exported to dmabuf's and which
are not.  Creating a dmabuf for every GEM bo is too heavyweight.

I'm not entirely sure if reservation/fence could/should be made any
simpler for multi-buffer users.  Probably the best thing to do is just
get reservation/fence rolled out in a few drivers and see if some
common patterns emerge.

BR,
-R

>
> Thanks,
> Inki Dae
>


From valentin.longchamp at keymile.com  Mon May 27 11:55:26 2013
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Mon, 27 May 2013 17:55:26 +0200
Subject: [PATCH] ARM: kirkwood: add i2c-gpio controller for km_kirkwood
Message-ID: <1369670126-27284-1-git-send-email-valentin.longchamp@keymile.com>

This controller is used to access the reset management FPGA of the
km_kirkwood boards.

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
---
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd054..64ee738 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -42,4 +42,11 @@
 			chip-delay = <25>;
 		};
 	};
+
+	i2c at 0 {
+		compatible = "i2c-gpio";
+		gpios = < &gpio0 8 0		/* sda */
+			&gpio0 9 0 >;		/* scl */
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+	};
 };
-- 
1.8.0.1



From daniel at ffwll.ch  Mon May 27 12:02:17 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Mon, 27 May 2013 18:02:17 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
Message-ID: <CAKMK7uG1T-w=rVfORzdSk9LWN_aXqqCiG87UdhjutfbS=rpzbg@mail.gmail.com>

On Mon, May 27, 2013 at 5:47 PM, Rob Clark <robdclark at gmail.com> wrote:
> On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
>> Hi all,
>>
>> I have been removed previous branch and added new one with more cleanup.
>> This time, the fence helper doesn't include user side interfaces and cache
>> operation relevant codes anymore because not only we are not sure that
>> coupling those two things, synchronizing caches and buffer access between
>> CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is a
>> good idea yet but also existing codes for user side have problems with badly
>> behaved or crashing userspace. So this could be more discussed later.
>>
>> The below is a new branch,
>>
>> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/?h=dma-f
>> ence-helper
>>
>> And fence helper codes,
>>
>> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
>> h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
>>
>> And example codes for device driver,
>>
>> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git/commit/?
>> h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
>>
>> I think the time is not yet ripe for RFC posting: maybe existing dma fence
>> and reservation need more review and addition work. So I'd glad for somebody
>> giving other opinions and advices in advance before RFC posting.
>
> thoughts from a *really* quick, pre-coffee, first look:
> * any sort of helper to simplify single-buffer sort of use-cases (v4l)
> probably wouldn't want to bake in assumption that seqno_fence is used.

Yeah, which is why Maarten&I discussed ideas already for what needs to
be improved in the current dma-buf interface code to make this Just
Work. At least as long as a driver doesn't want to add new fences,
which would be especially useful for all kinds of gpu access.

> * I guess g2d is probably not actually a simple use case, since I
> expect you can submit blits involving multiple buffers :-P

Yeah, on a quick read the current fence helper code seems to be a bit
limited in scope.

> * otherwise, you probably don't want to depend on dmabuf, which is why
> reservation/fence is split out the way it is..  you want to be able to
> use a single reservation/fence mechanism within your driver without
> having to care about which buffers are exported to dmabuf's and which
> are not.  Creating a dmabuf for every GEM bo is too heavyweight.

That's pretty much the reason that reservations are free-standing from
dma_bufs. The idea is to embed them into the gem/ttm/v4l buffer
object. Maarten also has some helpers to keep track of multi-buffer
ww_mutex locking and fence attaching in his reservation helpers, but I
think we should wait with those until we have drivers using them.

For now I think the priority should be to get the basic stuff in and
ttm as the first user established. Then we can go nuts later on.

> I'm not entirely sure if reservation/fence could/should be made any
> simpler for multi-buffer users.  Probably the best thing to do is just
> get reservation/fence rolled out in a few drivers and see if some
> common patterns emerge.

I think we can make the 1 buffer per dma op (i.e. 1:1
dma_buf->reservation : fence mapping) work fairly simple in dma_buf
with maybe a dma_buf_attachment_start_dma/end_dma helpers. But there's
also still the open that currently there's no way to flush cpu caches
for dma access without unmapping the attachement (or resorting to
trick which might not work), so we have a few gaping holes in the
interface already anyway.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From alexandre.belloni at free-electrons.com  Mon May 27 12:04:17 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 18:04:17 +0200
Subject: [PATCH v3] ARM: at91: Fix link breakage when !CONFIG_PHYLIB
In-Reply-To: <8424D480-48DA-4094-AE68-6A6A66F8FE2B@jcrosoft.com>
References: <1369651702-9207-1-git-send-email-alexandre.belloni@free-electrons.com>
 <E0B30581-DD0A-46C5-B541-08F389F17018@jcrosoft.com>
 <51A356A2.4050502@free-electrons.com>
 <8424D480-48DA-4094-AE68-6A6A66F8FE2B@jcrosoft.com>
Message-ID: <51A38401.5000103@free-electrons.com>

On 27/05/2013 14:59, Jean-Christophe PLAGNIOL-VILLARD wrote:
>
> no will not as you do ifdef CONFIG_PHYLIB and if CONFIG_PHYLIB=m the macro is defended
>
> we do this all the time in the kernel
>
> I add the IS_BUILTIN & co to be used when a simple inline is not sufficient

Ok, it took me a while to understand what you were trying to explain.
I'm sending a patch set now. I don't believe it will be taken in for
3.10 though.

Regards,

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From jason at lakedaemon.net  Mon May 27 12:18:56 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 27 May 2013 12:18:56 -0400
Subject: [PATCH v2] ARM: kirkwood: refactor dtsi to largest common nodes
In-Reply-To: <1369669232-24041-1-git-send-email-valentin.longchamp@keymile.com>
References: <1369669232-24041-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <20130527161856.GI31290@titan.lakedaemon.net>

On Mon, May 27, 2013 at 05:40:32PM +0200, Valentin Longchamp wrote:
> Some kirkwood variants (for instance present in the prestera SoCs) do
> not have all the peripherals whose nodes are declared in
> kirkwood.dtsi. These missing peripherals are SATA, SDIO, and RTC.
> 
> As discussed in [1], to avoid that these missing peripherals get
> initialized which could result in system hangs when accessing
> undocumented/not present HW registers, their corresponding OF nodes
> should not get declared at all for some kirkwood variants.
> 
> The corresponding OF nodes of these peripherals thus are moved from
> kirkwood.dtsi to the kirkwood-628x.dtsi files so that they still are
> initialized for these variants where they are present.
> 
> [1]
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/167154.html
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
> ---
> 
> Changes in v2:
> 	- include kirkwood-6281.dtsi in kirkwood-nsa310.dts
> 
>  arch/arm/boot/dts/kirkwood-6281.dtsi  | 24 ++++++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-6282.dtsi  | 24 ++++++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-nsa310.dts |  1 +
>  arch/arm/boot/dts/kirkwood.dtsi       | 24 ------------------------
>  4 files changed, 49 insertions(+), 24 deletions(-)

Applied to mvebu/dt and fixed up to incorporate the mvsdio changes.  New
version attached.

thx,

Jason.

---->8-----
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65..0ed2f56 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,33 @@
 				marvell,function = "sdio";
 			};
 		};
+
+		rtc at 10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			status = "disabled";
+		};
+
+		mvsdio at 90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			bus-width = <4>;
+			cap-sdio-irq;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e4..69b760d 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,34 @@
 			};
 		};
 
+		rtc at 10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			status = "disabled";
+		};
+
+		mvsdio at 90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			bus-width = <4>;
+			cap-sdio-irq;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			status = "disabled";
+		};
+
 		thermal at 10078 {
 			compatible = "marvell,kirkwood-thermal";
 			reg = <0x10078 0x4>;
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 79391ca..089024a 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 
 / {
 	model = "ZyXEL NSA310";
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 56e3161..38dc851 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -151,4 +151,18 @@
 			gpios = <&gpio1 11 1>;
 		};
         };
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_gpio_init>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		button at 1 {
+			label = "Init Button";
+			linux,code = <116>;
+			gpios = <&gpio1 6 0>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index e2a28db..39f497e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -71,13 +71,6 @@
 			status = "disabled";
 		};
 
-		rtc at 10300 {
-			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
-			reg = <0x10300 0x20>;
-			interrupts = <53>;
-			clocks = <&gate_clk 7>;
-		};
-
 		spi at 10600 {
 			compatible = "marvell,orion-spi";
 			#address-cells = <1>;
@@ -151,15 +144,6 @@
 			status = "okay";
 		};
 
-		sata at 80000 {
-			compatible = "marvell,orion-sata";
-			reg = <0x80000 0x5000>;
-			interrupts = <21>;
-			clocks = <&gate_clk 14>, <&gate_clk 15>;
-			clock-names = "0", "1";
-			status = "disabled";
-		};
-
 		nand at 3000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -194,17 +178,5 @@
 			clocks = <&gate_clk 17>;
 			status = "okay";
 		};
-
-		mvsdio at 90000 {
-			compatible = "marvell,orion-sdio";
-			reg = <0x90000 0x200>;
-			interrupts = <28>;
-			clocks = <&gate_clk 4>;
-			bus-width = <4>;
-			cap-sdio-irq;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			status = "disabled";
-		};
 	};
 };


From alexandre.belloni at free-electrons.com  Mon May 27 12:18:43 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 18:18:43 +0200
Subject: [PATCH 2/3] arm: mxs: don't check for CONFIG_PHYLIB as builtin
In-Reply-To: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <1369671524-14797-3-git-send-email-alexandre.belloni@free-electrons.com>

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..91c2bd2 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -273,9 +273,8 @@ static void __init apx4devkit_init(void)
 {
 	enable_clk_enet_out();
 
-	if (IS_BUILTIN(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
-					   apx4devkit_phy_fixup);
+	phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
+			apx4devkit_phy_fixup);
 }
 
 #define ENET0_MDC__GPIO_4_0	MXS_GPIO_NR(4, 0)
-- 
1.8.1.2



From alexandre.belloni at free-electrons.com  Mon May 27 12:18:41 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 18:18:41 +0200
Subject: [PATCH 0/3] net: phy: prevent linking breakage
Message-ID: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>

There is a linking issue when using phy_register_fixup{,_for_uid,_for_id} and
CONFIG_PHYLIB is not a builtin:

arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'

This has been solved for arch/arm/mach-mxs/ and arch/arm/mach-imx/ by testing
IS_BUILTIN(CONFIG_PHYLIB) before calling the functions.

The first patch is an attempt at solving that issue globally.

The following patches remove the unnecessary IS_BUILTIN(CONFIG_PHYLIB) checks.

Quickly greping into the code shows that the issue may arise in:

arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/arm/mach-davinci/board-dm644x-evm.c
arch/arm/mach-orion5x/dns323-setup.c
arch/arm/mach-at91/board-dt-sama5.c

Alexandre Belloni (3):
  net: phy: prevent linking breakage
  arm: mxs: don't check for CONFIG_PHYLIB as builtin
  arm: imx: don't check for CONFIG_PHYLIB as builtin

 arch/arm/mach-imx/mach-imx6q.c | 23 ++++++++++-------------
 arch/arm/mach-mxs/mach-mxs.c   |  5 ++---
 drivers/net/phy/phy_device.c   |  6 ++++++
 include/linux/phy.h            | 12 ++++++++++++
 4 files changed, 30 insertions(+), 16 deletions(-)

-- 
1.8.1.2



From alexandre.belloni at free-electrons.com  Mon May 27 12:18:42 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 18:18:42 +0200
Subject: [PATCH 1/3] net: phy: prevent linking breakage
In-Reply-To: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <1369671524-14797-2-git-send-email-alexandre.belloni@free-electrons.com>

phy_register_fixup{,_for_uid,_for_id} are called from arch/, quite
often, there is no protection to check whether CONFIG_PHYLIB=y which is
the only case where this would work. Having phylib as a module or not
compiled at all will result in that kind of linking failure:

arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 drivers/net/phy/phy_device.c |  6 ++++++
 include/linux/phy.h          | 12 ++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 3657b4a..df36367 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -64,6 +64,11 @@ static int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
 			     u32 flags, phy_interface_t interface);
 
 /*
+ *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
+ *  work unless phylib is compiled in the kernel.
+ */
+#ifdef CONFIG_PHYLIB
+/*
  * Creates a new phy_fixup and adds it to the list
  * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID)
  * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
@@ -109,6 +114,7 @@ int phy_register_fixup_for_id(const char *bus_id,
 	return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
 }
 EXPORT_SYMBOL(phy_register_fixup_for_id);
+#endif /* CONFIG_PHYLIB */
 
 /*
  * Returns 1 if fixup matches phydev in bus_id and phy_uid.
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 9e11039..3f998a6 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -556,12 +556,24 @@ int phy_start_interrupts(struct phy_device *phydev);
 void phy_print_status(struct phy_device *phydev);
 void phy_device_free(struct phy_device *phydev);
 
+/*
+ *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
+ *  work unless phylib is compiled in the kernel.
+ *  Defining stubs allows to prevent linking errors.
+ */
+#ifdef CONFIG_PHYLIB
 int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
 		int (*run)(struct phy_device *));
 int phy_register_fixup_for_id(const char *bus_id,
 		int (*run)(struct phy_device *));
 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
 		int (*run)(struct phy_device *));
+#else
+#define phy_register_fixup(a, b, c, d) do { } while (0)
+#define phy_register_fixup_for_id(a, b) do { } while (0)
+#define phy_register_fixup_for_uid(a, b, c) do { } while (0)
+#endif /* CONFIG_PHYLIB */
+
 int phy_scan_fixups(struct phy_device *phydev);
 
 int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
-- 
1.8.1.2



From alexandre.belloni at free-electrons.com  Mon May 27 12:18:44 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 18:18:44 +0200
Subject: [PATCH 3/3] arm: imx: don't check for CONFIG_PHYLIB as builtin
In-Reply-To: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <1369671524-14797-4-git-send-email-alexandre.belloni@free-electrons.com>

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 arch/arm/mach-imx/mach-imx6q.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..91c3cfb 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -99,16 +99,14 @@ soft:
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
-	if (IS_BUILTIN(CONFIG_PHYLIB)) {
-		/* min rx data delay */
-		phy_write(phydev, 0x0b, 0x8105);
-		phy_write(phydev, 0x0c, 0x0000);
-
-		/* max rx/tx clock delay, min rx/tx control delay */
-		phy_write(phydev, 0x0b, 0x8104);
-		phy_write(phydev, 0x0c, 0xf0f0);
-		phy_write(phydev, 0x0b, 0x104);
-	}
+	/* min rx data delay */
+	phy_write(phydev, 0x0b, 0x8105);
+	phy_write(phydev, 0x0c, 0x0000);
+
+	/* max rx/tx clock delay, min rx/tx control delay */
+	phy_write(phydev, 0x0b, 0x8104);
+	phy_write(phydev, 0x0c, 0xf0f0);
+	phy_write(phydev, 0x0b, 0x104);
 
 	return 0;
 }
@@ -139,9 +137,8 @@ put_clk:
 
 static void __init imx6q_sabrelite_init(void)
 {
-	if (IS_BUILTIN(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-				ksz9021rn_phy_fixup);
+	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+			ksz9021rn_phy_fixup);
 	imx6q_sabrelite_cko1_setup();
 }
 
-- 
1.8.1.2



From jason at lakedaemon.net  Mon May 27 12:20:33 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 27 May 2013 12:20:33 -0400
Subject: [PATCH] ARM: kirkwood: add i2c-gpio controller for km_kirkwood
In-Reply-To: <1369670126-27284-1-git-send-email-valentin.longchamp@keymile.com>
References: <1369670126-27284-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <20130527162033.GJ31290@titan.lakedaemon.net>

On Mon, May 27, 2013 at 05:55:26PM +0200, Valentin Longchamp wrote:
> This controller is used to access the reset management FPGA of the
> km_kirkwood boards.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
> ---
>  arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 7 +++++++
>  1 file changed, 7 insertions(+)

Applied to mvebu/dt

thx,

Jason.


From festevam at gmail.com  Mon May 27 12:25:24 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 27 May 2013 13:25:24 -0300
Subject: [PATCH v4 8/8] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <1361878774-6382-9-git-send-email-p.zabel@pengutronix.de>
References: <1361878774-6382-1-git-send-email-p.zabel@pengutronix.de>
 <1361878774-6382-9-git-send-email-p.zabel@pengutronix.de>
Message-ID: <CAOMZO5BJ7h=_cqSUG6X25SHTMe5ym1_nToj5P_PMR9bxN+B2Ow@mail.gmail.com>

On Tue, Feb 26, 2013 at 8:39 AM, Philipp Zabel <p.zabel at pengutronix.de> wrote:
> This driver implements a reset controller device that toggles gpios
> connected to reset pins of peripheral ICs. The delay between assertion
> and de-assertion of the reset signal can be configured.
>
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>

Looks good and it is a very useful binding.

Will anyone apply this?

Thanks,

Fabio Estevam


From s.hauer at pengutronix.de  Mon May 27 12:39:13 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 May 2013 18:39:13 +0200
Subject: [PATCH 1/3] net: phy: prevent linking breakage
In-Reply-To: <1369671524-14797-2-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
 <1369671524-14797-2-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <20130527163913.GO32299@pengutronix.de>

On Mon, May 27, 2013 at 06:18:42PM +0200, Alexandre Belloni wrote:
> phy_register_fixup{,_for_uid,_for_id} are called from arch/, quite
> often, there is no protection to check whether CONFIG_PHYLIB=y which is
> the only case where this would work. Having phylib as a module or not
> compiled at all will result in that kind of linking failure:
> 
> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> :(.text+0x1174): undefined reference to `mdiobus_write'
> :(.text+0x1188): undefined reference to `mdiobus_write'
> :(.text+0x119c): undefined reference to `mdiobus_write'
> :(.text+0x11b0): undefined reference to `mdiobus_write'
> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
> ---
>  drivers/net/phy/phy_device.c |  6 ++++++
>  include/linux/phy.h          | 12 ++++++++++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
> index 3657b4a..df36367 100644
> --- a/drivers/net/phy/phy_device.c
> +++ b/drivers/net/phy/phy_device.c
> @@ -64,6 +64,11 @@ static int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
>  			     u32 flags, phy_interface_t interface);
>  
>  /*
> + *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
> + *  work unless phylib is compiled in the kernel.
> + */
> +#ifdef CONFIG_PHYLIB
> +/*
>   * Creates a new phy_fixup and adds it to the list
>   * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID)
>   * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
> @@ -109,6 +114,7 @@ int phy_register_fixup_for_id(const char *bus_id,
>  	return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
>  }
>  EXPORT_SYMBOL(phy_register_fixup_for_id);
> +#endif /* CONFIG_PHYLIB */
>  
>  /*
>   * Returns 1 if fixup matches phydev in bus_id and phy_uid.
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index 9e11039..3f998a6 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -556,12 +556,24 @@ int phy_start_interrupts(struct phy_device *phydev);
>  void phy_print_status(struct phy_device *phydev);
>  void phy_device_free(struct phy_device *phydev);
>  
> +/*
> + *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
> + *  work unless phylib is compiled in the kernel.
> + *  Defining stubs allows to prevent linking errors.
> + */
> +#ifdef CONFIG_PHYLIB
>  int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
>  		int (*run)(struct phy_device *));
>  int phy_register_fixup_for_id(const char *bus_id,
>  		int (*run)(struct phy_device *));
>  int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
>  		int (*run)(struct phy_device *));
> +#else
> +#define phy_register_fixup(a, b, c, d) do { } while (0)
> +#define phy_register_fixup_for_id(a, b) do { } while (0)
> +#define phy_register_fixup_for_uid(a, b, c) do { } while (0)

Use static inline functions here. This breaks if someone does result
checking on the functions which then expands to ret = do {} while (0);
Also we still have type safety for !CONFIG_PHYLIB.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alexandre.belloni at free-electrons.com  Mon May 27 13:37:26 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Mon, 27 May 2013 19:37:26 +0200
Subject: [PATCH 1/3] net: phy: prevent linking breakage
In-Reply-To: <20130527163913.GO32299@pengutronix.de>
References: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
 <1369671524-14797-2-git-send-email-alexandre.belloni@free-electrons.com>
 <20130527163913.GO32299@pengutronix.de>
Message-ID: <51A399D6.8030000@free-electrons.com>

On 27/05/2013 18:39, Sascha Hauer wrote:
> On Mon, May 27, 2013 at 06:18:42PM +0200, Alexandre Belloni wrote:
>> phy_register_fixup{,_for_uid,_for_id} are called from arch/, quite
>> often, there is no protection to check whether CONFIG_PHYLIB=y which is
>> the only case where this would work. Having phylib as a module or not
>> compiled at all will result in that kind of linking failure:
>>
>> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
>> :(.text+0x1174): undefined reference to `mdiobus_write'
>> :(.text+0x1188): undefined reference to `mdiobus_write'
>> :(.text+0x119c): undefined reference to `mdiobus_write'
>> :(.text+0x11b0): undefined reference to `mdiobus_write'
>> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
>> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
>>
>> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
>> ---
>>  drivers/net/phy/phy_device.c |  6 ++++++
>>  include/linux/phy.h          | 12 ++++++++++++
>>  2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
>> index 3657b4a..df36367 100644
>> --- a/drivers/net/phy/phy_device.c
>> +++ b/drivers/net/phy/phy_device.c
>> @@ -64,6 +64,11 @@ static int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
>>  			     u32 flags, phy_interface_t interface);
>>  
>>  /*
>> + *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
>> + *  work unless phylib is compiled in the kernel.
>> + */
>> +#ifdef CONFIG_PHYLIB
>> +/*
>>   * Creates a new phy_fixup and adds it to the list
>>   * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID)
>>   * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
>> @@ -109,6 +114,7 @@ int phy_register_fixup_for_id(const char *bus_id,
>>  	return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
>>  }
>>  EXPORT_SYMBOL(phy_register_fixup_for_id);
>> +#endif /* CONFIG_PHYLIB */
>>  
>>  /*
>>   * Returns 1 if fixup matches phydev in bus_id and phy_uid.
>> diff --git a/include/linux/phy.h b/include/linux/phy.h
>> index 9e11039..3f998a6 100644
>> --- a/include/linux/phy.h
>> +++ b/include/linux/phy.h
>> @@ -556,12 +556,24 @@ int phy_start_interrupts(struct phy_device *phydev);
>>  void phy_print_status(struct phy_device *phydev);
>>  void phy_device_free(struct phy_device *phydev);
>>  
>> +/*
>> + *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
>> + *  work unless phylib is compiled in the kernel.
>> + *  Defining stubs allows to prevent linking errors.
>> + */
>> +#ifdef CONFIG_PHYLIB
>>  int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
>>  		int (*run)(struct phy_device *));
>>  int phy_register_fixup_for_id(const char *bus_id,
>>  		int (*run)(struct phy_device *));
>>  int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
>>  		int (*run)(struct phy_device *));
>> +#else
>> +#define phy_register_fixup(a, b, c, d) do { } while (0)
>> +#define phy_register_fixup_for_id(a, b) do { } while (0)
>> +#define phy_register_fixup_for_uid(a, b, c) do { } while (0)
> Use static inline functions here. This breaks if someone does result
> checking on the functions which then expands to ret = do {} while (0);
> Also we still have type safety for !CONFIG_PHYLIB.

Right, I tried that first but forgot static so I had issues with
redefinition of the functions. I even played with __weak at some point...

I'll wait a bit for comments before sending v2.

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From sergei.shtylyov at cogentembedded.com  Mon May 27 14:02:00 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Mon, 27 May 2013 22:02:00 +0400
Subject: [PATCH 1/1] mmc: of_mmc_spi: fix card detect irq
In-Reply-To: <20130527141306.GS24476@game.jcrosoft.org>
References: <1369571337-9300-1-git-send-email-plagnioj@jcrosoft.com>
 <51A25ECA.2060001@cogentembedded.com>
 <20130527141306.GS24476@game.jcrosoft.org>
Message-ID: <51A39F98.4010904@cogentembedded.com>

Hello.

On 27-05-2013 18:13, Jean-Christophe PLAGNIOL-VILLARD wrote:

>>> set missing irq type the IRQF_ONESHOT

>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>> Cc: stable <stable at vger.kernel.org> # 3.4+
>>> Cc: linux-mmc at vger.kernel.org
>>> ---
>>>   drivers/mmc/host/of_mmc_spi.c |    4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)

>>> diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
>>> index d720b5e..cfb2e61 100644
>>> --- a/drivers/mmc/host/of_mmc_spi.c
>>> +++ b/drivers/mmc/host/of_mmc_spi.c
>>> @@ -74,8 +74,8 @@ static int of_mmc_spi_init(struct device *dev,
>>>   {
>>>   	struct of_mmc_spi *oms = to_of_mmc_spi(dev);
>>> -	return request_threaded_irq(oms->detect_irq, NULL, irqhandler, 0,
>>> -				    dev_name(dev), mmc);
>>> +	return request_threaded_irq(oms->detect_irq, NULL, irqhandler,
>>> +		IRQF_ONESHOT, dev_name(dev), mmc);

>>      Please don't change the indentation.

> too long > 80

     Reflow it then into several lines.

> Best Regards,
> J.

WBR, Sergei




From dh.herrmann at gmail.com  Mon May 27 14:22:21 2013
From: dh.herrmann at gmail.com (David Herrmann)
Date: Mon, 27 May 2013 20:22:21 +0200
Subject: [PATCH v2] video: simplefb: add mode parsing function
In-Reply-To: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>
References: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>
Message-ID: <CANq1E4Qa6g-zrA6o_u3w6mpVcUk8-ZPPR+edu6EXgpk-kGQULQ@mail.gmail.com>

Hi

On Mon, May 27, 2013 at 5:53 AM, Alexandre Courbot <acourbot at nvidia.com> wrote:
> The naming scheme of simplefb's mode is precise enough to allow building
> the mode structure from it instead of using a static list of modes. This
> patch introduces a function that does this. In case exotic modes that
> cannot be represented from their name alone are needed, the static list
> of modes is still available as a backup.
>
> It also changes the order in which colors are declared from MSB first to
> the more standard LSB first.
>
> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
> ---
> Changes from v1:
> - amended documentation following Stephen's suggestion
> - allow parsing of bitfields larger than 9 bits
> - made it clear that the parsing order of bits is changed with respect
>   to the original patch
>
> Andrew, since this patch introduces a (small) change in the DT bindings,
> could we try to merge it during the -rc cycle so we don't have to come
> with a more complex solution in the future?
>
>  .../bindings/video/simple-framebuffer.txt          | 12 +++-
>  drivers/video/simplefb.c                           | 72 +++++++++++++++++++++-
>  2 files changed, 80 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/video/simple-framebuffer.txt b/Documentation/devicetree/bindings/video/simple-framebuffer.txt
> index 3ea4605..18d03e2 100644
> --- a/Documentation/devicetree/bindings/video/simple-framebuffer.txt
> +++ b/Documentation/devicetree/bindings/video/simple-framebuffer.txt
> @@ -10,8 +10,16 @@ Required properties:
>  - width: The width of the framebuffer in pixels.
>  - height: The height of the framebuffer in pixels.
>  - stride: The number of bytes in each line of the framebuffer.
> -- format: The format of the framebuffer surface. Valid values are:
> -  - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b).
> +- format: The format of the framebuffer surface. Described as a sequence of
> +       channel/num-bits pairs, where each pair describes how many bits are used
> +       by a given color channel. Value channels are "r" (red), "g" (green),
> +       "b" (blue), "a" (alpha) and "x" (unused). Channels are listed in bit
> +       order, starting from the LSB. For instance, a format named "r5g6b5"
> +       describes a 16-bit format where red is encoded in the 5 less significant
> +       bits, green in the 6 following ones, and blue in the 5 last:
> +                               BBBBBGGG GGGRRRRR
> +                               ^               ^
> +                              MSB             LSB

Is there a specific reason why we need arbitrary RGB formats? I have a
KMS/DRM driver based on dvbe that can provide the exact same
functionality as this fbdev driver (including an fbdev
backwards-compat layer). However, DRM does not allow arbitrary formats
but rather provides a huge list of supported formats.

If we apply this patch it will get very hard to support this with a
KMS driver. So any reason why we cannot use the DRM FOURCC constants
instead?

The dvbe proposal is available here: (also see the two following patches)
  http://lkml.indiana.edu/hypermail/linux/kernel/1302.2/00274.html

it provides a simple DRM driver that uses VESA / VBE. I am currently
trying to rework it to "SimpleDRM" which can support arbitrary
firmware framebuffers.

Cheers
David

>  Example:
>
> diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c
> index e2e9e3e..1430752 100644
> --- a/drivers/video/simplefb.c
> +++ b/drivers/video/simplefb.c
> @@ -21,6 +21,7 @@
>   */
>
>  #include <linux/errno.h>
> +#include <linux/ctype.h>
>  #include <linux/fb.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> @@ -82,8 +83,72 @@ struct simplefb_format {
>         struct fb_bitfield transp;
>  };
>
> +static struct simplefb_format *simplefb_parse_format(struct device *dev,
> +                                                    const char *str)
> +{
> +       struct simplefb_format *format;
> +       unsigned int offset = 0;
> +       unsigned int i = 0;
> +
> +       format = devm_kzalloc(dev, sizeof(*format), GFP_KERNEL);
> +       if (!format)
> +               return ERR_PTR(-ENOMEM);
> +
> +       while (str[i] != 0) {
> +               struct fb_bitfield *field = NULL;
> +               int length = 0;
> +
> +               switch (str[i++]) {
> +               case 'r':
> +               case 'R':
> +                       field = &format->red;
> +                       break;
> +               case 'g':
> +               case 'G':
> +                       field = &format->green;
> +                       break;
> +               case 'b':
> +               case 'B':
> +                       field = &format->blue;
> +                       break;
> +               case 'a':
> +               case 'A':
> +                       field = &format->transp;
> +                       break;
> +               case 'x':
> +               case 'X':
> +                       break;
> +               default:
> +                       goto error;
> +               }
> +
> +               if (!isdigit(str[i]))
> +                       goto error;
> +
> +               while (isdigit(str[i])) {
> +                       length = length * 10 + (str[i++] - '0');
> +               }
> +
> +               if (field) {
> +                       field->offset = offset;
> +                       field->length = length;
> +               }
> +
> +               offset += length;
> +       }
> +
> +       format->bits_per_pixel = (offset + 7) & ~0x7;
> +       format->name = str;
> +       return format;
> +
> +error:
> +       dev_err(dev, "Invalid format string\n");
> +       return ERR_PTR(-EINVAL);
> +}
> +
> +/* if you use exotic modes that simplefb_parse_format cannot decode, you can
> +   specify them here. */
>  static struct simplefb_format simplefb_formats[] = {
> -       { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0} },
>  };
>
>  struct simplefb_params {
> @@ -131,7 +196,10 @@ static int simplefb_parse_dt(struct platform_device *pdev,
>                 params->format = &simplefb_formats[i];
>                 break;
>         }
> -       if (!params->format) {
> +       if (!params->format)
> +               params->format = simplefb_parse_format(&pdev->dev, format);
> +
> +       if (IS_ERR(params->format)) {
>                 dev_err(&pdev->dev, "Invalid format value\n");
>                 return -EINVAL;
>         }
> --
> 1.8.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From jason at lakedaemon.net  Mon May 27 14:54:36 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 27 May 2013 14:54:36 -0400
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 3)
Message-ID: <20130527185436.GN31290@titan.lakedaemon.net>


The following changes since commit 489e138eec96f529c5e8d4cd3ea45882ecdbf5ca:

  ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node (2013-05-20 17:44:54 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-3

for you to fetch changes up to 6484ae0dcd6d45c3a3ab0442cb44fc1dddc53aec:

  ARM: mvebu: Fix bug in coherency fabric low level init function (2013-05-23 17:35:51 +0000)

----------------------------------------------------------------
mvebu fixes for v3.10 round 3

 - mvebu
    - fix register area length for sata and ethernet
    - fix bug in coherency fabric low level init

 - kirkwood
    - fix crash from pcie double init

----------------------------------------------------------------
Andrew Lunn (1):
      ARM: Kirkwood: TS219: Fix crash by double PCIe instantiation

Nadav Haklai (1):
      ARM: mvebu: Fix bug in coherency fabric low level init function

Thomas Petazzoni (2):
      arm: mvebu: fix length of SATA registers area in .dtsi
      arm: mvebu: fix length of Ethernet registers area in .dtsi

 arch/arm/boot/dts/armada-370-xp.dtsi     |  6 +++---
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |  2 +-
 arch/arm/boot/dts/armada-xp.dtsi         |  2 +-
 arch/arm/mach-kirkwood/board-ts219.c     | 10 ----------
 arch/arm/mach-mvebu/coherency_ll.S       | 16 +++++++++++-----
 5 files changed, 16 insertions(+), 20 deletions(-)


From tomasz.figa at gmail.com  Mon May 27 15:17:27 2013
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Mon, 27 May 2013 21:17:27 +0200
Subject: [PATCHv3 0/6] Add I2C support for Allwinner SoCs
In-Reply-To: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <2987322.J4qAl07e8R@flatron>

Hi Maxime,

On Monday 27 of May 2013 12:00:37 Maxime Ripard wrote:
> Hi,
> 
> This patchset adds support for the I2C controller found on most of the
> Allwinner SoCs, especially the already supported A10 and A13, and the
> yet to come A31.
> 
> It has been tested on a A13-Olinuxino.
> 
> Thanks,
> Maxime
> 
> Changes from v2:
>   * Slightly modified the switch comments again
>   * Removed the of_* calls in favor of platform_get_* functions
> 
> Changes from v1:
>   * Added comments to the switch statements to clarify when the fall
> through to the next case is made on purpose
>   * Use devm_ioremap_resource instead of of_iomap
>   * Moved the reset after enabling the clocks
>   * Added Emilio Lopez' patch to add the available i2c controllers to
> the cubieboard
> 
> Emilio L?pez (1):
>   ARM: sun4i: cubieboard: Enable the i2c controllers
> 
> Maxime Ripard (5):
>   i2c: sunxi: Add Allwinner A1X i2c driver
>   ARM: sunxi: dt: Add i2c controller nodes to the DTSI
>   ARM: sun4i: dt: Add i2c muxing options
>   ARM: sun5i: dt: Add i2c muxing options
>   ARM: sun5i: olinuxino: Enable the i2c controllers
> 
>  .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
>  arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  12 +
>  arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
>  arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
>  arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
>  drivers/i2c/busses/Kconfig                         |  10 +
>  drivers/i2c/busses/Makefile                        |   1 +
>  drivers/i2c/busses/i2c-sunxi.c                     | 444
> +++++++++++++++++++++ 8 files changed, 600 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
>  create mode 100644 drivers/i2c/busses/i2c-sunxi.c

All the patches look good to me.

Reviewed-by: Tomasz Figa <tomasz.figa at gmail.com>

Best regards,
Tomasz



From cdall at cs.columbia.edu  Mon May 27 15:58:04 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 12:58:04 -0700
Subject: [PATCH v2] ARM: mm: Get rid of L_PTE_USER ref from PAGE_S2_DEVICE
In-Reply-To: <b727cb23668cb98294ef0a75b31b38e6@localhost>
References: <1369444359-28962-1-git-send-email-cdall@cs.columbia.edu>
 <b727cb23668cb98294ef0a75b31b38e6@localhost>
Message-ID: <CAEDV+g+ME+Sx2MKp_4ePjUsSpj+EaAxF4v9z-K1SM5bdD6txaQ@mail.gmail.com>

On Sat, May 25, 2013 at 3:02 AM, Marc Zyngier <maz at misterjones.org> wrote:
> On Fri, 24 May 2013 18:12:39 -0700, Christoffer Dall
> <cdall at cs.columbia.edu> wrote:
>> THe L_PTE_USER actually has nothing to do with stage 2 mappings and the
>> L_PTE_S2_RDWR value sets the readable bit, which was what L_PTE_USER
>> was used for before proper handling of stage 2 memory defines.
>>
>> Changelog:
>>  [v2]: Change default mappings to be r/w instead of r/o, as per Marc
>>        Zyngier's suggestion.
>>
>> Cc: Marc Zyngier <marc.zyngier at arm.com>
>> Signed-off-by: Christoffer Dall <cdall at cs.columbia.edu>
>> ---
>>  arch/arm/include/asm/pgtable.h |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/include/asm/pgtable.h
>> b/arch/arm/include/asm/pgtable.h
>> index 9bcd262..8afc60c 100644
>> --- a/arch/arm/include/asm/pgtable.h
>> +++ b/arch/arm/include/asm/pgtable.h
>> @@ -97,7 +97,7 @@ extern pgprot_t             pgprot_s2_device;
>>  #define PAGE_HYP             _MOD_PROT(pgprot_kernel, L_PTE_HYP)
>>  #define PAGE_HYP_DEVICE              _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
>>  #define PAGE_S2                      _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
>> -#define PAGE_S2_DEVICE               _MOD_PROT(pgprot_s2_device, L_PTE_USER |
>> L_PTE_S2_RDONLY)
>> +#define PAGE_S2_DEVICE               _MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)
>>
>>  #define __PAGE_NONE          __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN
> |
>>  L_PTE_NONE)
>>  #define __PAGE_SHARED                __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
>
> Actually, there's a much better solution.
>
> Just get rid of PAGE_S2_DEVICE altogether, as it is completely useless. We
> never have to enforce a memory type in S2 that is stronger than the guest's
> view. If the guest insists on doing something silly (mapping a device as
> normal memory, for example), we really don't have to fix things for them.
>
> See the patch I posted a while ago as part of my pending fixes series:
> https://lists.cs.columbia.edu/pipermail/kvmarm/2013-May/005827.html
>
yeah duh, I'll reply to that one.


From cdall at cs.columbia.edu  Mon May 27 16:01:43 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 13:01:43 -0700
Subject: [PATCH v3 7/7] ARM: KVM: drop use of PAGE_S2_DEVICE
In-Reply-To: <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>
Message-ID: <CAEDV+gJeeQUOOLjFpkvoPk7e=csjmvvefhdp1miiWtosABwW6Q@mail.gmail.com>

On Tue, May 14, 2013 at 4:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> At the moment, when mapping a device into Stage-2 for a guest,
> we override whatever the guest uses by forcing a device memory
> type in Stage-2.
>
> While this is not exactly wrong, this isn't really the "spirit" of
> the architecture. The hardware shouldn't have to cope for a broken
> guest mapping to a device as normal memory.
>

So I'm trying to think of a scenario where this feature in the
architecture would actually be useful, and it sounds like from you
guys that it's only useful to properly run a broken guest.

Are we 100% sure that a malicious guest can't leverage this to break
isolation? I'm thinking something along the lines of writing to a
device (for example the gic virtual cpu interface) with a cached
mapping. If such a write is in fact written back to cache, and not
evicted from the cache before a later time, where a different VM is
running, can't that adversely affect the other VM?

Probably this can never happen, but I wasn't able to convince myself
of this from going through the ARM ARM...?

> As such, let's get rid of the memory type overrides, and map
> everything as PAGE_S2 in Stage-2. This simplifies the code and
> let the guest do its own thing, whether it is stupid or not.
>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/pgtable.h | 2 --
>  arch/arm/kvm/mmu.c             | 2 +-
>  arch/arm/mm/mmu.c              | 6 ++----
>  3 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
> index 9bcd262..c3410a8 100644
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -81,7 +81,6 @@ extern pgprot_t               pgprot_user;
>  extern pgprot_t                pgprot_kernel;
>  extern pgprot_t                pgprot_hyp_device;
>  extern pgprot_t                pgprot_s2;
> -extern pgprot_t                pgprot_s2_device;
>
>  #define _MOD_PROT(p, b)        __pgprot(pgprot_val(p) | (b))
>
> @@ -97,7 +96,6 @@ extern pgprot_t               pgprot_s2_device;
>  #define PAGE_HYP               _MOD_PROT(pgprot_kernel, L_PTE_HYP)
>  #define PAGE_HYP_DEVICE                _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
>  #define PAGE_S2                        _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
> -#define PAGE_S2_DEVICE         _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
>
>  #define __PAGE_NONE            __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
>  #define __PAGE_SHARED          __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 693d16c..f2a8416 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -495,7 +495,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
>         pfn = __phys_to_pfn(pa);
>
>         for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
> -               pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
> +               pte_t pte = pfn_pte(pfn, PAGE_S2);
>                 kvm_set_s2pte_writable(&pte);
>
>                 ret = mmu_topup_memory_cache(&cache, 2, 2);
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index e0d8565..bc001f5 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -60,7 +60,6 @@ pgprot_t pgprot_user;
>  pgprot_t pgprot_kernel;
>  pgprot_t pgprot_hyp_device;
>  pgprot_t pgprot_s2;
> -pgprot_t pgprot_s2_device;
>
>  EXPORT_SYMBOL(pgprot_user);
>  EXPORT_SYMBOL(pgprot_kernel);
> @@ -343,7 +342,7 @@ static void __init build_mem_type_table(void)
>         struct cachepolicy *cp;
>         unsigned int cr = get_cr();
>         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
> -       pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
> +       pteval_t hyp_device_pgprot, s2_pgprot;
>         int cpu_arch = cpu_architecture();
>         int i;
>
> @@ -456,7 +455,7 @@ static void __init build_mem_type_table(void)
>         cp = &cache_policies[cachepolicy];
>         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
>         s2_pgprot = cp->pte_s2;
> -       hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
> +       hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
>
>         /*
>          * ARMv6 and above have extended page tables.
> @@ -536,7 +535,6 @@ static void __init build_mem_type_table(void)
>         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
>                                  L_PTE_DIRTY | kern_pgprot);
>         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
> -       pgprot_s2_device  = __pgprot(s2_device_pgprot);
>         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
>
>         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
> --
> 1.8.2.3
>
>


From davem at davemloft.net  Mon May 27 16:18:57 2013
From: davem at davemloft.net (David Miller)
Date: Mon, 27 May 2013 13:18:57 -0700 (PDT)
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address
 workaround on DT ethernet
In-Reply-To: <1369655404.3557.33.camel@pasglop>
References: <1369647565.3557.28.camel@pasglop> <51A33447.80305@gmail.com>
 <1369655404.3557.33.camel@pasglop>
Message-ID: <20130527.131857.945196320286011406.davem@davemloft.net>

From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Date: Mon, 27 May 2013 21:50:04 +1000

> It would be handy to be able to just do something like
> 
> 	of_set_property(node, name, ptr, len);
> 
> However, that wouldn't help much with the allocation/leak problem,
> though at least it would be easier to use. It could also *try* to re-use
> the current allocation if the new content is of smaller or equal size.

And this is so much better of an interface because it allows the
OF implementation to decide how to deal with memory allocation
and freeing.


From arnd at arndb.de  Mon May 27 16:38:08 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 27 May 2013 22:38:08 +0200
Subject: [RFC V7 PATCH 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369657550-24101-4-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369657550-24101-1-git-send-email-manjunath.goudar@linaro.org>
 <1369657550-24101-4-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <201305272238.08984.arnd@arndb.de>

On Monday 27 May 2013, Manjunath Goudar wrote:
> This patch splits the PCI portion of ohci-hcd out into its
> own separate driver module, called ohci-pci.
> 
> The major point of difficulty lies in ohci-pci's many vendor- and
> device-specific workarounds.  Some of them have to be applied before
> calling ohci_start() some after, which necessitates a fair amount of
> code motion.  The other platform drivers require much smaller changes.
> 
> The complete sb800_prefetch() function moved to ohci-q.c,because its
> only related to ohci-pci driver.

I just gave this a little test run in qemu and on my server.

> @@ -446,7 +446,7 @@ config USB_OHCI_HCD_PPC_OF
>         default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE
>  
>  config USB_OHCI_HCD_PCI
> -       bool "OHCI support for PCI-bus USB controllers"
> +       tristate "OHCI support for PCI-bus USB controllers"
>         depends on PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
>         default y
>         select USB_OHCI_LITTLE_ENDIAN

There is a preexisting bug in this symbol: USB_OHCI_HCD_PCI was previously
unused, and has a bogus 'depends' line, which causes it to not be selectable
on anything but PPC.

You have to change this to only 'depends on PCI'.

>  	}
> -	if (ret == 0) {
> -		ohci_hcd_init (ohci);
> -		return ohci_init (ohci);
> -	}
> -	return ret;
> -}

I found that the call to ohci_hcd_init() that is removed here is not getting
added in any other place, which caused a NULL pointer dereference the first
time we actually try to use the driver.

Adding the call back into the new ohci_setup function makes it work again.

Please fold the patch below into your patch, unless Alan discovers something
wrong with it.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f948e8f..eef6dc5 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -454,7 +454,7 @@ config USB_OHCI_HCD_PPC_OF
 
 config USB_OHCI_HCD_PCI
 	tristate "OHCI support for PCI-bus USB controllers"
-	depends on PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
+	depends on PCI
 	default y
 	select USB_OHCI_CORE
 	select USB_OHCI_LITTLE_ENDIAN
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 3da8c3a..5601139 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -763,6 +763,8 @@ int ohci_setup(struct usb_hcd *hcd)
 {
 	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 
+	ohci_hcd_init(ohci);
+
 	return ohci_init(ohci);
 }
 EXPORT_SYMBOL_GPL(ohci_setup);
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index ea088c1..3133354 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -250,7 +250,7 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
 		}
 	}
 	if (ret == 0)
-		ohci_setup(hcd);
+		ret = ohci_setup(hcd);
 	/*
 	* After ohci setup RWC may not be set for add-in PCI cards.
 	* This transfers PCI PM wakeup capabilities.



From gmbnomis at gmail.com  Mon May 27 17:42:45 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 27 May 2013 23:42:45 +0200
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130523104303.GC16722@arm.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
Message-ID: <20130527214245.GB517@schnuecks.de>

Hi Catalin,

On Thu, May 23, 2013 at 11:43:03AM +0100, Catalin Marinas wrote:
> On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > it needs to handle are kernel mapped only.  However, for example when doing
> > direct I/O, pages with user space mappings may occur.
> > 
> > Thus, continue to do lazy flushing if there are no user space mappings.
> > Otherwise, flush the kernel cache lines directly.
> > 
> > Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> > Cc: Catalin Marinas <catalin.marinas at arm.com>
> > Cc: Russell King <linux at arm.linux.org.uk>
> 
> An issue is that for kunmap_atomic() && VIVT we flush the same page
> twice. I don't think we should remove the cache flushing in
> __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> don't work together). Flushing the VIVT cache on kunmap is essential
> since we just lose the alias after that.

Not sure if I am missing something here. From our previous
discussion:

> > > > We probably should reuse it in flush_kernel_dcache_page() to flush
> > > > the kernel mapping. (The last else clause looks strange though)
> > > 
> > > I think it makes sense to reuse this logic in
> > > flush_kernel_dcache_page(). If the page is already mapped with kmap,
> > > then kmap_high_get() should return the actual address. If it was mapped
> > > with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
> > > clause and the additional kmap_atomic(). The cache_is_vipt() check is
> > > useful because kunmap_atomic() would flush VIVT caches anyway.


As you say, this logic does not flush on VIVT if the page was mapped
via kmap_atomic() (and kmap_atomic() could not reuse an existing
mapping via kmap_high_get())

kmap_atomic() tries to reuse an existing mapping and only allocates a
new dedicated kmap if it finds none.  Consequently, __kunmap_atomic()
only flushes in the latter case (because we lose the alias).

Thus, no double flushing should occur here. If kunmap_atomic() will
flush, __flush_kernel_dcache_page() will not and vice versa.

> > +void flush_kernel_dcache_page(struct page *page)
> > +{
> > +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> 
> So you could add the ((cache_is_vivt() || cache_is_vipt_aliasing()) &&
> !PageHighMem(page)) check back (as it was prior to commit f8b63c184,
> actually reverting it) and the mapping tests as a possible optimisation.
> But in this case there is no need to split __flush_dcache_page() in two
> since we don't care about the PageHighMem() case.
> 
> And we need to fix kunmap() with VIVT to flush the cache as well (in
> case anyone uses highmem on VIVT hardware).

I still think your previous comment that we need to handle the
highmem case as well was right and reusing the respective part of
__flush_dcache_page() does the right thing.

But as said, perhaps I am missing something here.

- Simon 


From benh at kernel.crashing.org  Mon May 27 17:48:04 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Tue, 28 May 2013 07:48:04 +1000
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <20130527.131857.945196320286011406.davem@davemloft.net>
References: <1369647565.3557.28.camel@pasglop> <51A33447.80305@gmail.com>
 <1369655404.3557.33.camel@pasglop>
 <20130527.131857.945196320286011406.davem@davemloft.net>
Message-ID: <1369691284.3557.34.camel@pasglop>

On Mon, 2013-05-27 at 13:18 -0700, David Miller wrote:
> From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Date: Mon, 27 May 2013 21:50:04 +1000
> 
> > It would be handy to be able to just do something like
> > 
> >       of_set_property(node, name, ptr, len);
> > 
> > However, that wouldn't help much with the allocation/leak problem,
> > though at least it would be easier to use. It could also *try* to re-use
> > the current allocation if the new content is of smaller or equal size.
> 
> And this is so much better of an interface because it allows the
> OF implementation to decide how to deal with memory allocation
> and freeing.

Absolutely, I'm not arguing that point.

Cheers,
Ben.




From benh at kernel.crashing.org  Mon May 27 17:50:06 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Tue, 28 May 2013 07:50:06 +1000
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <2255648.0KEmXfjCx5@wuerfel>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <51A33447.80305@gmail.com> <1369655404.3557.33.camel@pasglop>
 <2255648.0KEmXfjCx5@wuerfel>
Message-ID: <1369691406.3557.35.camel@pasglop>

On Mon, 2013-05-27 at 14:47 +0200, Arnd Bergmann wrote:
> On Monday 27 May 2013 21:50:04 Benjamin Herrenschmidt wrote:
> > However, that wouldn't help much with the allocation/leak problem,
> > though at least it would be easier to use. It could also *try* to re-use
> > the current allocation if the new content is of smaller or equal size.
> 
> I thought that dtc tried to aggressively save space by folding identical
> strings. If you tried to reuse a property that had its contents shared
> with another one, you would get interesting results I guess.

It used to be only property names, unless that has changed in recent
dtc. But that's a good point, we probably want a flag in struct property
like we have for nodes, indicating whether it comes from the original
fdt data pool or not.

Cheers,
Ben.




From arno at natisbad.org  Mon May 27 18:02:29 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Tue, 28 May 2013 00:02:29 +0200
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
Message-ID: <cover.1369687670.git.arno@natisbad.org>

Hi,

This series adds support for GMT G762/G763. This work is based on a
basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
NAS. Updates have been performed to run on recent kernels. Support has
been completed and additional features added: ability to configure
various characteristics from .dts file, better initialization, alarms
and error reporting support, gear mode, polarity, fan pulse per
revolution, fan startup voltage control. The following detailed
datasheet has been used as a basis for this work:

  http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf

The patch was developed for and tested against the GMT G762 fan
controller used in a Netgear ReadyNAS Duo v2 (kirkwood 88F6282-based
NAS). This is the main reason for the device tree bindings provided in
first patch. The driver also support init via board file. The patches
are against current ARM tree; tell me if you need me to rebase it
against something else. Patch 2 and 3 provides documentation for the
driver and DT bindings, respectively.

I think most of the comments provided on v0 and v1 have been taken into
account. A detailed list of changes is provided below.

Nonetheless, some remarks made during previous review need some specific
feedback:

 Full speed mode: I started looking how I could emulate full speed mode
 (i.e. sysfs value 0 for "pwm_enable") but I found no easy way to do it
 w/o making things quite complex because the feature is orthogonal to
 fan loop mode (closed or open). This would imply setting *both*
 G762_REG_SET_CNT and G762_REG_SET_OUT registers (respectively for
 closed-loop and open-loop) to their max value (so that a loop mode
 change does not reset full speed), and also keep an internal flag to
 record the fact we are in full speed mode instead of reading current
 mode (PWM or DC) from the device register value. I took a look at some
 other drivers (w83793.c, w83l786ng.c, etc) to see how those emulate the
 feature and they just do not. What do you think?

 Support for board init code: in order to support setting hardware
 characteristics via board init file, I provided a (static const)
 init structure with all the fields of struct g762_platform_data set to
 a specific value (G762_DEFAULT_NO_OVERLOAD). The structure can be used in
 a board init file to initialize a local structure for which specific
 fields can then be given meaningful values. Those which are not
 overloaded will not be pushed to the chip. This is in sync with the
 common policy for hwmon drivers not to change the device configuration
 by default. If you see a more proper way to do it - other than the
 static const struct - I'd be happy to make the change.
 
 Setting mode before fan target value: Guenter, you made a remark about
 the undesirable context to have to set the mode (closed-loop) before 
 setting the fan target. I can change the code and accept the fan target
 value in all cases but this will have no impact before the mode is
 set to closed-loop. At the moment, the user gets a feedback it should
 set the mode before using fan1_target (i.e. invalid value). What do you
 think?

Comments welcome,

Cheers,

a+

Changes since v1
    Changed author
    removed bad tabs
    Provide datasheet link w/o fud in g762 documentation
    removed documentation for removed fan_gear_mode sysfs entry
    removed tested-by from patch
    removed FSF address in header file
    removed useless include of <linux/slab.h>
    removed useless parenthesis against HZ in define
    use spaces around binary operators
    use i2c_smbus_{read,write}_byte_data() instead of g762_{read,write}_value()
    use return value of i2c_smbus_write_byte_data()
    use true for initializing boolean
    removed useless blank lines
    do not enforce single return point rule where less readable
    use dev_err() and dev_dbg() instead of dev_info() when it makes sense
    remove leading '&' for function passed as pointers
    allow passing parameter via platform_data struct for non-DT enabled boards
    set data->valid to false when config is modified
    s/linear/DC/ for mode (g762 datasheet uses linear)
    more tests on rpm_from_cnt() and cnt_from_rpm() formula
    dont overload     

Changes since v0
    removed forward declaration 
    use bool for valid field instead of bit field.
    protect macro args
    fixed typo in subject line
    Added mention for G763 support in Kconfig
    fixed typo in driver name in Kconfig
    do not use DRVNAME in i2c_device_id g762_id[] 
    Following discussions, kept DEVICE_ATTR (i.e. no switch to SENSOR_DEVICE_ATTR)
    removed useless casts when flipping bit values
    Sanity check user input value (e.g. to prevent 256 to silenty become 0)
    Added extra lines for multi line comments when needed
    removed various testing knobs
    make removed knobs available via DT
    passed checkpatch script on the patch
    removed useless lock protection againt clk setting
    moved all setter at the beginning of the file
    removed bad (u16) casts in g762_write_value() calls


Arnaud Ebalard (3):
  Add support for GMT G762/G763 PWM fan controller
  Add documentation for g762 driver
  Add DT bindings documentation for g762 driver

 Documentation/devicetree/bindings/hwmon/g762.txt |   57 ++
 Documentation/hwmon/g762                         |   64 ++
 drivers/hwmon/Kconfig                            |   10 +
 drivers/hwmon/Makefile                           |    1 +
 drivers/hwmon/g762.c                             | 1012 ++++++++++++++++++++++
 include/linux/platform_data/g762.h               |   54 ++
 6 files changed, 1198 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/g762.txt
 create mode 100644 Documentation/hwmon/g762
 create mode 100644 drivers/hwmon/g762.c
 create mode 100644 include/linux/platform_data/g762.h

-- 
1.7.10.4



From arno at natisbad.org  Mon May 27 18:03:14 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Tue, 28 May 2013 00:03:14 +0200
Subject: [PATCHv2 1/3] Add support for GMT G762/G763 PWM fan controller
In-Reply-To: <cover.1369687670.git.arno@natisbad.org>
References: <cover.1369687670.git.arno@natisbad.org>
Message-ID: <b44f55c4194f6cd8c94f8a3d63ad5c8bd1d1cfe0.1369687670.git.arno@natisbad.org>


Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
---
 drivers/hwmon/Kconfig              |   10 +
 drivers/hwmon/Makefile             |    1 +
 drivers/hwmon/g762.c               | 1012 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/g762.h |   54 ++
 4 files changed, 1077 insertions(+)
 create mode 100644 drivers/hwmon/g762.c
 create mode 100644 include/linux/platform_data/g762.h

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 0428e8a..142bdf8 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -456,6 +456,16 @@ config SENSORS_G760A
 	  This driver can also be built as a module.  If so, the module
 	  will be called g760a.
 
+config SENSORS_G762
+	tristate "GMT G762 and G763"
+	depends on I2C
+	help
+	  If you say yes here you get support for Global Mixed-mode
+	  Technology Inc G762 and G763 fan speed PWM controller chips.
+
+	  This driver can also be built as a module.  If so, the module
+	  will be called g762.
+
 config SENSORS_GL518SM
 	tristate "Genesys Logic GL518SM"
 	depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d17d3e6..4f0fb52 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SENSORS_F75375S)	+= f75375s.o
 obj-$(CONFIG_SENSORS_FAM15H_POWER) += fam15h_power.o
 obj-$(CONFIG_SENSORS_FSCHMD)	+= fschmd.o
 obj-$(CONFIG_SENSORS_G760A)	+= g760a.o
+obj-$(CONFIG_SENSORS_G762)	+= g762.o
 obj-$(CONFIG_SENSORS_GL518SM)	+= gl518sm.o
 obj-$(CONFIG_SENSORS_GL520SM)	+= gl520sm.o
 obj-$(CONFIG_SENSORS_GPIO_FAN)	+= gpio-fan.o
diff --git a/drivers/hwmon/g762.c b/drivers/hwmon/g762.c
new file mode 100644
index 0000000..d21ec24
--- /dev/null
+++ b/drivers/hwmon/g762.c
@@ -0,0 +1,1012 @@
+/*
+ * g762 - Driver for the Global Mixed-mode Technology Inc. fan speed
+ *        PWM controller chips from G762 family, i.e. G762 and G763
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno at natisbad.org>
+ *
+ * This work is based on a basic version for 2.6.31 kernel developed
+ * by Olivier Mouchet for LaCie. Updates and correction have been
+ * performed to run on recent kernels. Additional features, like the
+ * ability to configure various characteristics via .dts file, have
+ * been added. Detailed datasheet on which this development is based
+ * is available here:
+ *
+ *  http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf
+ *
+ * Headers from previous developments have been kept below:
+ *
+ * Copyright (c) 2009 LaCie
+ *
+ * Author: Olivier Mouchet <olivier.mouchet at gmail.com>
+ *
+ * based on g760a code written by Herbert Valerio Riedel <hvr at gnu.org>
+ * Copyright (C) 2007  Herbert Valerio Riedel <hvr at gnu.org>
+ *
+ * g762: minimal datasheet available at:
+ *       http://www.gmt.com.tw/product/datasheet/EDS-762_3.pdf
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_data/g762.h>
+
+#define DRVNAME "g762"
+
+static const struct i2c_device_id g762_id[] = {
+	{ "g762", 0 },
+	{ "g763", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, g762_id);
+
+enum g762_regs {
+	G762_REG_SET_CNT  = 0x00,
+	G762_REG_ACT_CNT  = 0x01,
+	G762_REG_FAN_STA  = 0x02,
+	G762_REG_SET_OUT  = 0x03,
+	G762_REG_FAN_CMD1 = 0x04,
+	G762_REG_FAN_CMD2 = 0x05,
+};
+
+/* Config register bits */
+#define G762_REG_FAN_CMD1_DET_FAN_FAIL  0x80 /* enable fan_fail signal */
+#define G762_REG_FAN_CMD1_DET_FAN_OOC   0x40 /* enable fan_out_of_control */
+#define G762_REG_FAN_CMD1_OUT_MODE      0x20 /* out mode, PWM or DC */
+#define G762_REG_FAN_CMD1_FAN_MODE      0x10 /* fan mode: closed/open loop */
+#define G762_REG_FAN_CMD1_CLK_DIV_ID1   0x08 /* clock divisor value */
+#define G762_REG_FAN_CMD1_CLK_DIV_ID0   0x04
+#define G762_REG_FAN_CMD1_PWM_POLARITY  0x02 /* PWM polarity */
+#define G762_REG_FAN_CMD1_PULSE_PER_REV 0x01 /* pulse per fan revolution */
+
+#define G762_REG_FAN_CMD2_GEAR_MODE_1   0x08 /* fan gear mode */
+#define G762_REG_FAN_CMD2_GEAR_MODE_0   0x04
+#define G762_REG_FAN_CMD2_FAN_STARTV_1  0x02 /* fan startup voltage */
+#define G762_REG_FAN_CMD2_FAN_STARTV_0  0x01
+
+#define G762_REG_FAN_STA_FAIL           0x02 /* fan fail */
+#define G762_REG_FAN_STA_OOC            0x01 /* fan out of control */
+
+/* config register values */
+#define OUT_MODE_PWM            1
+#define OUT_MODE_DC             0
+
+#define FAN_MODE_CLOSED_LOOP    2
+#define FAN_MODE_OPEN_LOOP      1
+
+/* register data is read (and cached) at most once per second */
+#define G762_UPDATE_INTERVAL    HZ
+
+/*
+ * extract pulse count per fan revolution value (2 or 4) from given
+ * FAN_CMD1 register value
+ */
+#define PULSE_FROM_REG(reg) \
+	((((reg) & G762_REG_FAN_CMD1_PULSE_PER_REV)+1) << 1)
+
+/*
+ * extract fan clock divisor (1, 2, 4 or 8) from given FAN_CMD1
+ * register value
+ */
+#define CLKDIV_FROM_REG(reg) \
+	(1 << (((reg) & (G762_REG_FAN_CMD1_CLK_DIV_ID0 |	\
+			 G762_REG_FAN_CMD1_CLK_DIV_ID1)) >> 2))
+
+/*
+ * extract fan gear mode multiplier value (0, 2 or 4) from given
+ * FAN_CMD2 register value
+ */
+#define GEARMULT_FROM_REG(reg) \
+	(1 << (((reg) & (G762_REG_FAN_CMD2_GEAR_MODE_0 |	\
+			 G762_REG_FAN_CMD2_GEAR_MODE_1)) >> 2))
+
+struct g762_data {
+	struct i2c_client *client;
+	struct device *hwmon_dev;
+
+	/* update mutex */
+	struct mutex update_lock;
+
+	/* board specific parameters. */
+	u32 clk;
+
+	/* g762 register cache */
+	bool valid;
+	unsigned long last_updated; /* in jiffies */
+
+	u8 set_cnt;  /* controls fan rotation speed in closed-loop mode */
+	u8 act_cnt;  /* provides access to current fan RPM value */
+	u8 fan_sta;  /* bit 0: set when actual fan speed is more than
+		      *        25% outside requested fan speed
+		      * bit 1: set when no transition occurs on fan
+		      *        pin for 0.7s
+		      */
+	u8 set_out;  /* controls fan rotation speed in open-loop mode */
+	u8 fan_cmd1; /*   0: FG_PLS_ID0 FG pulses count per revolution
+		      *      0: 2 counts per revolution
+		      *      1: 4 counts per revolution
+		      *   1: PWM_POLARITY 1: negative_duty
+		      *                   0: positive_duty
+		      * 2,3: [FG_CLOCK_ID0, FG_CLK_ID1]
+		      *         00: Divide fan clock by 1
+		      *         01: Divide fan clock by 2
+		      *         10: Divide fan clock by 4
+		      *         11: Divide fan clock by 8
+		      *   4: FAN_MODE 1:closed-loop, 0:open-loop
+		      *   5: OUT_MODE 1:PWM, 0:DC
+		      *   6: DET_FAN_OOC enable "fan ooc" status
+		      *   7: DET_FAN_FAIL enable "fan fail" status
+		      */
+	u8 fan_cmd2; /* 0,1: FAN_STARTV 0,1,2,3 -> 0,32,64,96 dac_code
+		      * 2,3: FG_GEAR_MODE
+		      *         00: multiplier = 1
+		      *         01: multiplier = 2
+		      *         10: multiplier = 4
+		      *   4: Mask ALERT# (g763 only)
+		      */
+};
+
+/*
+ * sysfs PWM interface uses value from 0 to 255 when g762 FAN_SET_CNT register
+ * uses values from 255 (off) to 0 (full speed). Note that FAN_SET_OUT register
+ * uses values from 0 (off) to 255 (full speed), i.e. does not need translation.
+ */
+#define PWM_FROM_CNT(cnt)       (0xff - (cnt))
+#define PWM_TO_CNT(pwm)         (0xff - (pwm))
+
+/*
+ * Convert count value from fan controller registers (FAN_SET_CNT/FAN_ACT_CNT)
+ * into fan speed RPM value. Note that the datasheet documents a basic formula.
+ * Influence of additional parameters (fan clock divisor, fan gear mode) have
+ * been infered from examples in the datasheet and tests.
+ */
+static inline unsigned int rpm_from_cnt(u8 cnt, u32 clk, u16 p,
+					u8 clk_div, u8 gear_mult)
+{
+	if (cnt == 0xff)  /* cnt to 255 stops the fan */
+		return 0;
+
+	return (clk*30*gear_mult)/((cnt ? cnt : 1)*p*clk_div);
+}
+
+/* Convert fan RPM value from sysfs into count value for fan controller register
+ * (FAN_SET_CNT). */
+static inline unsigned char cnt_from_rpm(u32 rpm, u32 clk, u16 p,
+					 u8 clk_div, u8 gear_mult)
+{
+	if (!rpm)         /* to stop the fan, set cnt to 255 */
+		return 0xff;
+
+	return clamp_val(((clk*30*gear_mult)/(rpm*p*clk_div)), 0, 255);
+}
+
+/* helper to grab and cache data, at most one time per second */
+static struct g762_data *g762_update_client(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = i2c_get_clientdata(client);
+
+	mutex_lock(&data->update_lock);
+	if (time_before(jiffies, data->last_updated + G762_UPDATE_INTERVAL) &&
+	    likely(data->valid))
+		goto out;
+
+	data->set_cnt =  i2c_smbus_read_byte_data(client, G762_REG_SET_CNT);
+	data->act_cnt =  i2c_smbus_read_byte_data(client, G762_REG_ACT_CNT);
+	data->fan_sta =  i2c_smbus_read_byte_data(client, G762_REG_FAN_STA);
+	data->set_out =  i2c_smbus_read_byte_data(client, G762_REG_SET_OUT);
+	data->fan_cmd1 = i2c_smbus_read_byte_data(client, G762_REG_FAN_CMD1);
+	data->fan_cmd2 = i2c_smbus_read_byte_data(client, G762_REG_FAN_CMD2);
+
+	data->last_updated = jiffies;
+	data->valid = true;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return data;
+}
+
+/*
+ * helpers for passing hardware characteristics via DT. Some of those
+ * are also used by sysfs handlers (write functions) later in the file.
+ */
+
+/* Set pwm mode. Accepts either 0 (PWM mode) or 1 (DC mode) */
+static int do_set_pwm_mode(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case OUT_MODE_PWM:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_OUT_MODE;
+		break;
+	case OUT_MODE_DC:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_OUT_MODE;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/*
+ * Set reference clock. Accepted values are between 0 and 0xffffff.
+ * Note that this is a characteristics of the system but an internal
+ * parameter, i.e. value is not passed to the device.
+ */
+static int do_set_pwm_freq(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = i2c_get_clientdata(client);
+
+	if (val > 0xffffff)
+		return -EINVAL;
+
+	data->clk = val;
+
+	return 0;
+}
+
+/* Set fan clock divisor. Accepted values are 1, 2, 4 and 8. */
+static int do_set_fan_div(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case 1:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_CLK_DIV_ID0;
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_CLK_DIV_ID1;
+		break;
+	case 2:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_CLK_DIV_ID0;
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_CLK_DIV_ID1;
+		break;
+	case 4:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_CLK_DIV_ID0;
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_CLK_DIV_ID1;
+		break;
+	case 8:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_CLK_DIV_ID0;
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_CLK_DIV_ID1;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Set fan gear mode. Accepted values are either 0, 1 or 2. */
+static int do_set_fan_gear_mode(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case 0:
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_GEAR_MODE_0;
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_GEAR_MODE_1;
+		break;
+	case 1:
+		data->fan_cmd2 |=  G762_REG_FAN_CMD2_GEAR_MODE_0;
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_GEAR_MODE_1;
+		break;
+	case 2:
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_GEAR_MODE_0;
+		data->fan_cmd2 |=  G762_REG_FAN_CMD2_GEAR_MODE_1;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD2,
+					data->fan_cmd2);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Set pulse per revolution value. Accepts either 2 or 4. */
+static int do_set_fan_pulses(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case 2:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_PULSE_PER_REV;
+		break;
+	case 4:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_PULSE_PER_REV;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Set fan mode. Accepts either 1 (open-loop) or 2 (closed-loop). */
+static int do_set_pwm_enable(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case FAN_MODE_OPEN_LOOP:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_FAN_MODE;
+		break;
+	case FAN_MODE_CLOSED_LOOP:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_FAN_MODE;
+		break;
+	default:
+		goto out;
+	}
+
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Set PWM polarity (0 for negative duty, 1 for positive duty) */
+static int do_set_pwm_polarity(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case 0: /* i.e. negative duty */
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_PWM_POLARITY;
+		break;
+	case 1: /* i.e. positive duty */
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_PWM_POLARITY;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/*
+ * Set pwm value. Accepted values are between 0 (stops the fan) and 255 (full
+ * speed). Note that the chip register used for setting the value depends on
+ * current fan mode of the device (closed or open-loop).
+ */
+static int do_set_pwm(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret;
+	u8 reg;
+
+	if (val > 255)
+		return -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	if (data->fan_cmd1 & G762_REG_FAN_CMD1_FAN_MODE) { /* closed-loop */
+		val = PWM_TO_CNT(val);
+		data->set_cnt = val;
+		reg = G762_REG_SET_CNT;
+	} else {                                           /* open-loop */
+		data->set_out = val;
+		reg = G762_REG_SET_OUT;
+	}
+	ret = i2c_smbus_write_byte_data(client, reg, (u8)val);
+	data->valid = false;
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Set fan RPM value. This only makes sense in closed-loop mode. */
+static int do_set_fan_target(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	if (data->fan_cmd1 & G762_REG_FAN_CMD1_FAN_MODE) { /* closed-loop */
+		data->set_cnt = cnt_from_rpm(val, data->clk,
+					     PULSE_FROM_REG(data->fan_cmd1),
+					     CLKDIV_FROM_REG(data->fan_cmd1),
+					     GEARMULT_FROM_REG(data->fan_cmd2));
+		ret = i2c_smbus_write_byte_data(client, G762_REG_SET_CNT,
+						data->set_cnt);
+		data->valid = false;
+	}
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Enable/disable fan failure detection. Accepted values are 1 and 0. */
+static int do_fan_failure_detection_toggle(struct device *dev,
+					   unsigned long enable)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (enable) {
+	case 0:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_DET_FAN_FAIL;
+		break;
+	case 1:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_DET_FAN_FAIL;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Enable/disable fan out of control detection. Accepted values are 1 and 0 */
+static int do_fan_ooc_detection_toggle(struct device *dev, unsigned int enable)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (enable) {
+	case 0:
+		data->fan_cmd1 &= ~G762_REG_FAN_CMD1_DET_FAN_OOC;
+		break;
+	case 1:
+		data->fan_cmd1 |=  G762_REG_FAN_CMD1_DET_FAN_OOC;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/* Set fan startup voltage. Accepted values are either 0, 1, 2 or 3. */
+static int do_set_fan_startv(struct device *dev, unsigned long val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct g762_data *data = g762_update_client(dev);
+	int ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	switch (val) {
+	case 0:
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_FAN_STARTV_0;
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_FAN_STARTV_1;
+		data->valid = false;
+		break;
+	case 1:
+		data->fan_cmd2 |=  G762_REG_FAN_CMD2_FAN_STARTV_0;
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_FAN_STARTV_1;
+		data->valid = false;
+		break;
+	case 2:
+		data->fan_cmd2 &= ~G762_REG_FAN_CMD2_FAN_STARTV_0;
+		data->fan_cmd2 |=  G762_REG_FAN_CMD2_FAN_STARTV_1;
+		data->valid = false;
+		break;
+	case 3:
+		data->fan_cmd2 |=  G762_REG_FAN_CMD2_FAN_STARTV_0;
+		data->fan_cmd2 |=  G762_REG_FAN_CMD2_FAN_STARTV_1;
+		data->valid = false;
+		break;
+	default:
+		goto out;
+	}
+	ret = i2c_smbus_write_byte_data(client, G762_REG_FAN_CMD2,
+					data->fan_cmd2);
+	data->valid = false;
+ out:
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+/*
+ * Configuration-related definitions
+ */
+
+static inline void g762_platform_data_init(struct g762_platform_data *pdata)
+{
+	*pdata = G762_DEFAULT_PDATA;
+}
+
+static inline int g762_one_prop_commit(struct i2c_client *client,
+				       u32 pval, const char *pname,
+				       int (*psetter)(struct device *dev,
+						      unsigned long val))
+{
+	int ret = 0;
+
+	if ((pval != G762_DEFAULT_NO_OVERLOAD) &&
+	    (*psetter)(&client->dev, pval)) {
+		dev_err(&client->dev, "unable to set %s (%d)\n", pname, pval);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int g762_platform_data_commit(struct i2c_client *client,
+				     struct g762_platform_data *pdata)
+{
+	int ret = 0;
+
+	if (g762_one_prop_commit(client, pdata->fan_startv,
+				 "fan_startv", do_set_fan_startv) ||
+	    g762_one_prop_commit(client, pdata->fan_div,
+				 "fan_div", do_set_fan_div) ||
+	    g762_one_prop_commit(client, pdata->fan_pulses,
+				 "fan_pulses", do_set_fan_pulses) ||
+	    g762_one_prop_commit(client, pdata->pwm_freq,
+				 "pwm_freq", do_set_pwm_freq) ||
+	    g762_one_prop_commit(client, pdata->fan_gear_mode,
+				 "fan_gear_mode", do_set_fan_gear_mode) ||
+	    g762_one_prop_commit(client, pdata->pwm_polarity,
+				 "pwm_polarity", do_set_pwm_polarity) ||
+	    g762_one_prop_commit(client, pdata->pwm_mode,
+				 "pwm_mode", do_set_pwm_mode) ||
+	    g762_one_prop_commit(client, pdata->pwm_enable,
+				 "pwm_enable", do_set_pwm_enable) ||
+	    g762_one_prop_commit(client, pdata->fan_target,
+				 "fan_target", do_set_fan_target)) {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/*
+ * Helpers to import hardware characteristics from .dts file and overload
+ * default platform data values.
+ */
+
+#ifdef CONFIG_OF
+static struct of_device_id g762_dt_match[] = {
+	{ .compatible = "gmt,g762" },
+	{ .compatible = "gmt,g763" },
+	{ },
+};
+
+static inline void g762_of_import_one_prop(struct i2c_client *client,
+					   u32 *dest, const char *pname)
+{
+	const __be32 *prop;
+	int len;
+
+	prop = of_get_property(client->dev.of_node, pname, &len);
+	if (prop && len == sizeof(u32)) {
+		*dest = be32_to_cpu(prop[0]);
+		dev_dbg(&client->dev, "found %s (%d)\n", pname, *dest);
+	}
+}
+
+static void g762_platform_data_of_overload(struct i2c_client *client,
+					   struct g762_platform_data *pdata)
+{
+	if (!client->dev.of_node)
+		return;
+
+	g762_of_import_one_prop(client, &pdata->fan_gear_mode, "fan_gear_mode");
+	g762_of_import_one_prop(client, &pdata->pwm_polarity, "pwm_polarity");
+	g762_of_import_one_prop(client, &pdata->fan_startv, "fan_startv");
+	g762_of_import_one_prop(client, &pdata->pwm_freq, "pwm_freq");
+	g762_of_import_one_prop(client, &pdata->fan_div, "fan_div");
+	g762_of_import_one_prop(client, &pdata->fan_pulses, "fan_pulses");
+	g762_of_import_one_prop(client, &pdata->pwm_mode, "pwm_mode");
+	g762_of_import_one_prop(client, &pdata->fan_target, "fan_target");
+	g762_of_import_one_prop(client, &pdata->pwm_enable, "pwm_enable");
+}
+#else
+static void g762_platform_data_of_overload(struct i2c_client *client,
+				    struct g762_platform_data *pdata) { }
+#endif
+
+/*
+ * helper to overload driver parameters from board init file for those
+ * not already converted to device tree
+ */
+static void g762_platform_data_overload(struct i2c_client *client,
+					struct g762_platform_data *pdata)
+{
+	struct g762_platform_data *opdata = client->dev.platform_data;
+
+	if (opdata)
+		*pdata = *opdata;
+}
+
+/*
+ * sysfs attributes
+ */
+
+/*
+ * Read function for fan1_input sysfs file. Return current fan RPM value, or
+ * 0 if fan is out of control. The function is available in both closed and
+ * open-loop mode.
+ */
+static ssize_t get_fan_rpm(struct device *dev, struct device_attribute *da,
+			   char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+	unsigned int rpm = 0;
+
+	mutex_lock(&data->update_lock);
+	/* reverse logic: fan out of control reporting is enabled low */
+	if (data->fan_sta & G762_REG_FAN_STA_OOC) {
+		rpm = rpm_from_cnt(data->act_cnt, data->clk,
+				   PULSE_FROM_REG(data->fan_cmd1),
+				   CLKDIV_FROM_REG(data->fan_cmd1),
+				   GEARMULT_FROM_REG(data->fan_cmd2));
+	}
+	mutex_unlock(&data->update_lock);
+
+	return sprintf(buf, "%u\n", rpm);
+}
+
+/*
+ * Read and write functions for pwm1_mode sysfs file. Get and set fan speed
+ * control mode i.e. PWM (1) or DC (0).
+ */
+static ssize_t get_pwm_mode(struct device *dev, struct device_attribute *da,
+			    char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+
+	return sprintf(buf, "%d\n",
+		       !!(data->fan_cmd1 & G762_REG_FAN_CMD1_OUT_MODE));
+}
+
+static ssize_t set_pwm_mode(struct device *dev, struct device_attribute *da,
+			    const char *buf, size_t count)
+{
+	unsigned long val;
+
+	if (kstrtoul(buf, 10, &val) || do_set_pwm_mode(dev, val))
+		return -EINVAL;
+
+	return count;
+}
+
+/*
+ * Read and write functions for fan1_div sysfs file. Get and set fan
+ * controller prescaler value
+ */
+static ssize_t get_fan_div(struct device *dev,
+			       struct device_attribute *da, char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+
+	return sprintf(buf, "%d\n", CLKDIV_FROM_REG(data->fan_cmd1));
+}
+
+static ssize_t set_fan_div(struct device *dev,
+			       struct device_attribute *da,
+			       const char *buf, size_t count)
+{
+	unsigned long val;
+
+	if (kstrtoul(buf, 10, &val) || do_set_fan_div(dev, val))
+		return -EINVAL;
+
+	return count;
+}
+
+/*
+ * Read and write functions for pwm1_enable. Get and set the fan speed control
+ * mode (i.e. closed or open-loop).
+ *
+ * Following documentation about hwmon's sysfs interface, a pwm1_enable node
+ * should accept followings:
+ *
+ *  0 : no fan speed control (i.e. fan at full speed)
+ *  1 : manual fan speed control enabled (use pwm[1-*]) (open-loop)
+ *  2+: automatic fan speed control enabled (use fan[1-*]_target) (closed-loop)
+ *
+ * but we do not accept 0 as "no-control" mode is not supported by g762,
+ * -EINVAL is returned in this case.
+ */
+static ssize_t get_pwm_enable(struct device *dev,
+			      struct device_attribute *da, char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+
+	return sprintf(buf, "%d\n",
+		       (!!(data->fan_cmd1 & G762_REG_FAN_CMD1_FAN_MODE)) + 1);
+}
+
+static ssize_t set_pwm_enable(struct device *dev,
+			      struct device_attribute *da,
+			      const char *buf, size_t count)
+{
+	unsigned long val;
+
+	if (kstrtoul(buf, 10, &val) || do_set_pwm_enable(dev, val))
+		return -EINVAL;
+
+	return count;
+}
+
+/*
+ * Read and write functions for pwm1 sysfs file. Get and set the fan speed
+ * in both open and closed-loop mode. Speed is given as a relative value
+ * between 0 and 255, where 255 is maximum speed. Note that due to rounding
+ * errors it is possible that you don't read back exactly the value you have
+ * set.
+ */
+static ssize_t get_pwm(struct device *dev, struct device_attribute *da,
+		       char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+	int val;
+
+	mutex_lock(&data->update_lock);
+	if (data->fan_cmd1 & G762_REG_FAN_CMD1_FAN_MODE) { /* closed-loop */
+		val = PWM_FROM_CNT(data->set_cnt);
+	} else {                                           /* open-loop */
+		val = data->set_out;
+	}
+	mutex_unlock(&data->update_lock);
+
+	return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t set_pwm(struct device *dev, struct device_attribute *da,
+		       const char *buf, size_t count)
+{
+	unsigned long val;
+
+	if (kstrtoul(buf, 10, &val) || do_set_pwm(dev, val))
+		return -EINVAL;
+
+	return count;
+}
+
+/*
+ * Read and write function for fan1_target sysfs file. Get/set the fan speed in
+ * closed-loop mode. Speed is given as a RPM value; then the chip will regulate
+ * the fan speed using pulses from fan tachometer. The functions both return
+ * -EINVAL when called in open-loop mode.
+ *
+ * Refer to rpm_from_cnt() implementation above to get info about count number
+ * calculation.
+ *
+ * Also note that due to rounding errors it is possible that you don't read
+ * back exactly the value you have set.
+ */
+static ssize_t get_fan_target(struct device *dev, struct device_attribute *da,
+			      char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+	unsigned int rpm;
+	ssize_t ret = -EINVAL;
+
+	mutex_lock(&data->update_lock);
+	if (data->fan_cmd1 & G762_REG_FAN_CMD1_FAN_MODE) { /* closed-loop */
+		rpm = rpm_from_cnt(data->set_cnt, data->clk,
+				   PULSE_FROM_REG(data->fan_cmd1),
+				   CLKDIV_FROM_REG(data->fan_cmd1),
+				   GEARMULT_FROM_REG(data->fan_cmd2));
+		ret = sprintf(buf, "%u\n", rpm);
+	}
+	mutex_unlock(&data->update_lock);
+
+	return ret;
+}
+
+static ssize_t set_fan_target(struct device *dev, struct device_attribute *da,
+			      const char *buf, size_t count)
+{
+	unsigned long val;
+
+	if (kstrtoul(buf, 10, &val) || do_set_fan_target(dev, val))
+		return -EINVAL;
+
+	return count;
+}
+
+/* read function for fan1_fault sysfs file. */
+static ssize_t get_fan_failure(struct device *dev, struct device_attribute *da,
+			       char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+
+	return sprintf(buf, "%u\n", !!(data->fan_sta & G762_REG_FAN_STA_FAIL));
+}
+
+/*
+ * read function for fan1_alarm sysfs file. Note that OOC confition is
+ * enabled low
+ */
+static ssize_t get_fan_ooc(struct device *dev, struct device_attribute *da,
+			   char *buf)
+{
+	struct g762_data *data = g762_update_client(dev);
+
+	return sprintf(buf, "%u\n", !(data->fan_sta & G762_REG_FAN_STA_OOC));
+}
+
+static DEVICE_ATTR(pwm1, S_IWUSR | S_IRUGO, get_pwm, set_pwm);
+static DEVICE_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, get_pwm_mode, set_pwm_mode);
+static DEVICE_ATTR(pwm1_enable, S_IWUSR | S_IRUGO,
+		   get_pwm_enable, set_pwm_enable);
+static DEVICE_ATTR(fan1_input, S_IRUGO, get_fan_rpm, NULL);
+static DEVICE_ATTR(fan1_alarm, S_IRUGO, get_fan_ooc, NULL);
+static DEVICE_ATTR(fan1_fault, S_IRUGO, get_fan_failure, NULL);
+static DEVICE_ATTR(fan1_target, S_IWUSR | S_IRUGO,
+		   get_fan_target, set_fan_target);
+static DEVICE_ATTR(fan1_div, S_IWUSR | S_IRUGO, get_fan_div, set_fan_div);
+
+/* Driver data */
+static struct attribute *g762_attributes[] = {
+	&dev_attr_fan1_input.attr,
+	&dev_attr_fan1_alarm.attr,
+	&dev_attr_fan1_fault.attr,
+	&dev_attr_fan1_target.attr,
+	&dev_attr_fan1_div.attr,
+	&dev_attr_pwm1.attr,
+	&dev_attr_pwm1_mode.attr,
+	&dev_attr_pwm1_enable.attr,
+	NULL
+};
+
+static const struct attribute_group g762_group = {
+	.attrs = g762_attributes,
+};
+
+static int g762_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	struct g762_data *data;
+	struct g762_platform_data pdata;
+	int err;
+
+	if (!i2c_check_functionality(client->adapter,
+				     I2C_FUNC_SMBUS_BYTE_DATA))
+		return -ENODEV;
+
+	data = devm_kzalloc(&client->dev, sizeof(struct g762_data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	i2c_set_clientdata(client, data);
+
+	data->client = client;
+	mutex_init(&data->update_lock);
+
+	/* Enable fan protection and fan fail detection by default */
+	do_fan_ooc_detection_toggle(&client->dev, 1);
+	do_fan_failure_detection_toggle(&client->dev, 1);
+
+	/*
+	 * Set default configuration values before passing the structure
+	 * first to overload routine used by boards non converted to DT and
+	 * then to OF helper (to overload them using those provided by .dts
+	 * file, if any). Final result is then commited.
+	 */
+	g762_platform_data_init(&pdata);
+	g762_platform_data_overload(client, &pdata);
+	g762_platform_data_of_overload(client, &pdata);
+	err = g762_platform_data_commit(client, &pdata);
+	if (err)
+		return err;
+
+	/* Register sysfs hooks */
+	err = sysfs_create_group(&client->dev.kobj, &g762_group);
+	if (err)
+		return err;
+
+	data->hwmon_dev = (struct device *)hwmon_device_register(&client->dev);
+	if (IS_ERR(data->hwmon_dev)) {
+		err = PTR_ERR(data->hwmon_dev);
+		goto err_out;
+	}
+
+	return 0;
+
+ err_out:
+	sysfs_remove_group(&client->dev.kobj, &g762_group);
+	return err;
+}
+
+static int g762_remove(struct i2c_client *client)
+{
+	struct g762_data *data = i2c_get_clientdata(client);
+
+	hwmon_device_unregister(data->hwmon_dev);
+	sysfs_remove_group(&client->dev.kobj, &g762_group);
+
+	return 0;
+}
+
+static struct i2c_driver g762_driver = {
+	.driver = {
+		.name = DRVNAME,
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(g762_dt_match),
+	},
+	.probe	  = g762_probe,
+	.remove	  = g762_remove,
+	.id_table = g762_id,
+};
+
+module_i2c_driver(g762_driver);
+
+MODULE_AUTHOR("Arnaud EBALARD <arno at natisbad.org>");
+MODULE_DESCRIPTION("GMT G762/G763 driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/platform_data/g762.h b/include/linux/platform_data/g762.h
new file mode 100644
index 0000000..29e3934
--- /dev/null
+++ b/include/linux/platform_data/g762.h
@@ -0,0 +1,54 @@
+/*
+ * Platform data structure for g762 fan controller driver
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno at natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __LINUX_PLATFORM_DATA_G762_H__
+#define __LINUX_PLATFORM_DATA_G762_H__
+
+#define G762_DEFAULT_NO_OVERLOAD 0xffffffff
+
+struct g762_platform_data {
+	u32 fan_startv;
+	u32 fan_gear_mode;
+	u32 fan_div;
+	u32 fan_pulses;
+	u32 fan_target;
+	u32 pwm_polarity;
+	u32 pwm_enable;
+	u32 pwm_freq;
+	u32 pwm_mode;
+};
+
+/* When filling a g762_platform_data structure to be passed during platform
+ * init to the driver, it needs to be initialized to the following default
+ * value before changing specific fields. This is needed to avoid a sparse
+ * initialization to have current values replaced by 0 */
+
+static const struct g762_platform_data G762_DEFAULT_PDATA = {
+	.fan_startv = G762_DEFAULT_NO_OVERLOAD,
+	.fan_gear_mode = G762_DEFAULT_NO_OVERLOAD,
+	.fan_div = G762_DEFAULT_NO_OVERLOAD,
+	.fan_pulses = G762_DEFAULT_NO_OVERLOAD,
+	.fan_target = G762_DEFAULT_NO_OVERLOAD,
+	.pwm_polarity = G762_DEFAULT_NO_OVERLOAD,
+	.pwm_enable = G762_DEFAULT_NO_OVERLOAD,
+	.pwm_freq = G762_DEFAULT_NO_OVERLOAD,
+	.pwm_mode = G762_DEFAULT_NO_OVERLOAD,
+};
+
+#endif /* __LINUX_PLATFORM_DATA_G762_H__ */
-- 
1.7.10.4



From arno at natisbad.org  Mon May 27 18:03:28 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Tue, 28 May 2013 00:03:28 +0200
Subject: [PATCHv2 2/3] Add documentation for g762 driver
In-Reply-To: <cover.1369687670.git.arno@natisbad.org>
References: <cover.1369687670.git.arno@natisbad.org>
Message-ID: <9e9904e9e0aed280afe547445bb471ba0229aa9e.1369687670.git.arno@natisbad.org>


Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
---
 Documentation/hwmon/g762 |   64 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/hwmon/g762

diff --git a/Documentation/hwmon/g762 b/Documentation/hwmon/g762
new file mode 100644
index 0000000..b749fe1
--- /dev/null
+++ b/Documentation/hwmon/g762
@@ -0,0 +1,64 @@
+Kernel driver g762
+==================
+
+The GMT G762 Fan Speed PWM Controller is connected directly to a fan
+and performs closed-loop or open-loop control of the fan speed. Two
+modes - PWM or DC - are supported by the device.
+
+For additional information, a detailed datasheet is available at
+http://natisbad.org/NAS/ref/GMT_EDS-762_763-080710-0.2.pdf. sysfs
+bindings are described in Documentation/hwmon/sysfs-interface.
+
+The following entries are available to the user in a subdirectory of
+/sys/bus/i2c/drivers/g762/ to control the operation of the device.
+This can be done manually using the following entries but is usually
+done via a userland daemon like fancontrol.
+
+Note that those entries do not provide ways to setup the specific
+hardware characteristics of the system (reference clock, pulses per
+fan revolution, ...); Those can be modified via devicetree bindings
+documented in Documentation/devicetree/bindings/hwmon/g762.txt.
+
+
+  fan1_target: set desired fan speed. This only makes sense in closed-loop
+            fan speed control (i.e. when pwm1_enable is set to 2).
+
+  fan1_input: provide current fan rotation value in RPM as reported by
+            the fan to the device.
+
+  fan1_div: fan clock divisor. Supported value are 1, 2, 4 and 8.
+
+  fan1_fault: reports fan failure, i.e. no transition on fan gear pin for
+            about 0.7s (if the fan is not voluntarily set off).
+
+  fan1_alarm: in closed-loop control mode, if fan RPM value is 25% out
+            of the programmed value for over 6 seconds 'fan1_alarm' is
+            set to 1.
+
+  pwm1_enable: set current fan speed control mode i.e. 1 for manual fan
+            speed control (open-loop) via pwm1 described below, 2 for
+            automatic fan speed control (closed-loop) via fan1_target
+            above (pwm1 is also usable).
+
+  pwm1_mode: set or get fan driving mode: 1 for PWM mode, 0 for DC mode.
+
+  pwm1: get or set PWM fan control value. This is an integer value
+            between 0 and 255. 0 stops the fan, 255 makes it run at
+            full speed. Note that the fan speed control mode (open vs
+            closed-loop) must be set prior via pwm1_enable prior to
+            passing a value via pwm1.
+
+
+Both in PWM mode ('pwm1_mode' set to 1) and DC mode ('pwm1_mode' set to 0),
+when current fan speed control mode is open-loop ('pwm1_enable' set to 1),
+the fan speed is programmed by setting a value between 0 and 255 via 'pwm1'
+entry (0 stops the fan, 255 makes it run at full speed). In closed-loop mode
+('pwm1_enable' set to 2), the expected rotation speed in RPM can be passed to
+the chip via 'fan1_target'. In closed-loop mode, the target speed is compared
+with current speed (available via 'fan1_input') by the device and a feedback
+is performed to match that target value. The fan speed value is computed
+based on the parameters associated with the physical characteristics of the
+system: a reference clock source frequency, a number of pulses per fan
+revolution, etc.
+
+Note that the driver will update its values at most once per second.
-- 
1.7.10.4



From arno at natisbad.org  Mon May 27 18:03:41 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Tue, 28 May 2013 00:03:41 +0200
Subject: [PATCHv2 3/3] Add DT bindings documentation for g762 driver
In-Reply-To: <cover.1369687670.git.arno@natisbad.org>
References: <cover.1369687670.git.arno@natisbad.org>
Message-ID: <eab66cea9ff30d44b82fc3ec6aee2bdb928a9cae.1369687670.git.arno@natisbad.org>


Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
---
 Documentation/devicetree/bindings/hwmon/g762.txt |   57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/g762.txt

diff --git a/Documentation/devicetree/bindings/hwmon/g762.txt b/Documentation/devicetree/bindings/hwmon/g762.txt
new file mode 100644
index 0000000..f7ac01a
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/g762.txt
@@ -0,0 +1,57 @@
+GMT G762/G763 PWM Fan controller
+
+Required node properties:
+
+ - "compatible": must be either "gmt,g762" or "gmt,g763"
+ - "reg": I2C bus address of the device
+
+Optional properties:
+
+ - "pwm_mode": fan driving mode. 1 for PWM mode, 0 for linear.
+
+ - "pwm_enable": fan speed control. 1 for open-loop, 2 for closed-loop.
+
+ - "pwm_freq": reference clock frequency for PWM mode in Hz.
+
+ - "fan_pulses": number of pulses per fan revolution. Supported values
+               are 2 and 4.
+
+ - "fan_div": fan clock frequency divisor value. Supported values are 1,
+               2, 4 and 8. Default is 1.
+
+ - "fan_target": initial target fan speed in RPM. Only works in closed-loop
+               fan speed control, i.e. when pwm_enable has already been set
+               to 2.
+
+ - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3.
+               The higher the more.
+
+ - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty)
+               and 1 (negative duty).
+
+ - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2.
+
+If an optional property is not set in .dts file, then current value is kept
+unmodified (e.g. u-boot installed value).
+
+
+Additional information on operational parameters for the device is available
+in Documentation/hwmon/g762. A detailed datasheet for the device is available
+at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.
+
+Example g762 node:
+
+   g762: g762 at 3e {
+	compatible = "gmt,g762";
+	reg = <0x3e>;
+	pwm_mode = <1>;      /* closed-loop control */
+	pwm_enable = <2>;    /* PWM mode */
+	pwm_freq = <8192>;   /* PWM reference clock freq */
+	fan_pulses = <2>;    /* 2 pulses per rev */
+	fan_div = <2>;       /* fan clock divisor */
+	fan_target = <2000>; /* target fan speed at 2000 RPM */
+	fan_gear_mode = <0>; /* chip default */
+	fan_startv = <1>;    /* chip default */
+	pwm_polarity = <0>;  /* chip default */
+   };
+
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon May 27 18:12:46 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 28 May 2013 00:12:46 +0200
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address workaround
 on DT ethernet
In-Reply-To: <1369691406.3557.35.camel@pasglop>
References: <1369253042-15082-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <51A33447.80305@gmail.com> <1369655404.3557.33.camel@pasglop>
 <2255648.0KEmXfjCx5@wuerfel> <1369691406.3557.35.camel@pasglop>
Message-ID: <51A3DA5E.6080501@gmail.com>

On 05/27/2013 11:50 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-27 at 14:47 +0200, Arnd Bergmann wrote:
>> On Monday 27 May 2013 21:50:04 Benjamin Herrenschmidt wrote:
>>> However, that wouldn't help much with the allocation/leak problem,
>>> though at least it would be easier to use. It could also *try* to re-use
>>> the current allocation if the new content is of smaller or equal size.
>>
>> I thought that dtc tried to aggressively save space by folding identical
>> strings. If you tried to reuse a property that had its contents shared
>> with another one, you would get interesting results I guess.
>
> It used to be only property names, unless that has changed in recent
> dtc. But that's a good point, we probably want a flag in struct property
> like we have for nodes, indicating whether it comes from the original
> fdt data pool or not.

But isn't that what current sparc implementation of of_set_property does
when it marks the property as dynamic?

Anyway, this definitely exceeds my knowledge of OF API for sure, so what
do I do about the MAC workaround now?

Prepare the patch with global arrays and switch to some of_set_property
as soon as it is available?

Sebastian



From arnd at arndb.de  Mon May 27 18:15:15 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 00:15:15 +0200
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
In-Reply-To: <cover.1369687670.git.arno@natisbad.org>
References: <cover.1369687670.git.arno@natisbad.org>
Message-ID: <152190814.eApXVbVBPA@wuerfel>

On Tuesday 28 May 2013 00:02:29 Arnaud Ebalard wrote:
> 
> This series adds support for GMT G762/G763. This work is based on a
> basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
> NAS. Updates have been performed to run on recent kernels. Support has
> been completed and additional features added: ability to configure
> various characteristics from .dts file, better initialization, alarms
> and error reporting support, gear mode, polarity, fan pulse per
> revolution, fan startup voltage control.

I wonder if this could be split into two separate drivers, one for
the pwm subsystem, and one for a hardware-independent fan controller
based on the pwm interfaces.

	Arnd


From davem at davemloft.net  Mon May 27 18:17:44 2013
From: davem at davemloft.net (David Miller)
Date: Mon, 27 May 2013 15:17:44 -0700 (PDT)
Subject: [PATCH 1/2] ARM: kirkwood: proper retain MAC address
 workaround on DT ethernet
In-Reply-To: <1369691406.3557.35.camel@pasglop>
References: <1369655404.3557.33.camel@pasglop> <2255648.0KEmXfjCx5@wuerfel>
 <1369691406.3557.35.camel@pasglop>
Message-ID: <20130527.151744.1526437556583356156.davem@davemloft.net>

From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Date: Tue, 28 May 2013 07:50:06 +1000

> On Mon, 2013-05-27 at 14:47 +0200, Arnd Bergmann wrote:
>> On Monday 27 May 2013 21:50:04 Benjamin Herrenschmidt wrote:
>> > However, that wouldn't help much with the allocation/leak problem,
>> > though at least it would be easier to use. It could also *try* to re-use
>> > the current allocation if the new content is of smaller or equal size.
>> 
>> I thought that dtc tried to aggressively save space by folding identical
>> strings. If you tried to reuse a property that had its contents shared
>> with another one, you would get interesting results I guess.
> 
> It used to be only property names, unless that has changed in recent
> dtc. But that's a good point, we probably want a flag in struct property
> like we have for nodes, indicating whether it comes from the original
> fdt data pool or not.

This is similar to what the "OF_IS_DYNAMIC()" thing on sparc
indicates.


From f.fainelli at gmail.com  Mon May 27 18:20:05 2013
From: f.fainelli at gmail.com (Florian Fainelli)
Date: Tue, 28 May 2013 00:20:05 +0200
Subject: [PATCH 1/3] net: phy: prevent linking breakage
In-Reply-To: <51A399D6.8030000@free-electrons.com>
References: <1369671524-14797-1-git-send-email-alexandre.belloni@free-electrons.com>
 <1369671524-14797-2-git-send-email-alexandre.belloni@free-electrons.com>
 <20130527163913.GO32299@pengutronix.de>
 <51A399D6.8030000@free-electrons.com>
Message-ID: <201305272320.08296.f.fainelli@gmail.com>

Hi,

Le 27 mai 2013 19:38, "Alexandre Belloni" <alexandre.belloni at free-
electrons.com> a ?crit :

[snip]

> >> +/*
> >> + *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this 
won't
> >> + *  work unless phylib is compiled in the kernel.
> >> + *  Defining stubs allows to prevent linking errors.
> >> + */
> >> +#ifdef CONFIG_PHYLIB
> >>  int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
> >>              int (*run)(struct phy_device *));
> >>  int phy_register_fixup_for_id(const char *bus_id,
> >>              int (*run)(struct phy_device *));
> >>  int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
> >>              int (*run)(struct phy_device *));
> >> +#else
> >> +#define phy_register_fixup(a, b, c, d) do { } while (0)
> >> +#define phy_register_fixup_for_id(a, b) do { } while (0)
> >> +#define phy_register_fixup_for_uid(a, b, c) do { } while (0)
> > Use static inline functions here. This breaks if someone does result
> > checking on the functions which then expands to ret = do {} while (0);
> > Also we still have
> Right, I tried that first but forgot static so I had issues with
> redefinition of the functions. I even played with __weak at some point...

You might even want to make these static inlines as mentionned earlier, and 
return something like -ENOTSUPP so that someone using these in board code and 
wondering why they do not work gets a chance to enable CONIFG_PHYLIB.
--
Florian


From festevam at gmail.com  Mon May 27 20:52:21 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 27 May 2013 21:52:21 -0300
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <20130514023142.GA16250@S2101-09.ap.freescale.net>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <20130304031716.GC30431@S2101-09.ap.freescale.net>
 <CAOMZO5Ai-msRVeAqQFiRhfAxkb2DMTYJvTcYihBhFt6GMCFwPQ@mail.gmail.com>
 <20130323135608.GG6281@S2101-09.ap.freescale.net>
 <CAOMZO5BvT3CUhPECTQZQq_Q2YEqMJzmXPL5pj-3Qmq35jnvm1A@mail.gmail.com>
 <20130324141758.GH6281@S2101-09.ap.freescale.net>
 <CAOMZO5AeJUtyRC1BoAUiFihbjKtLMC2WBjaUXW0x+RE+QHYPnA@mail.gmail.com>
 <20130514023142.GA16250@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5DRuKrECnYDtZ0wOK6_vpW95Cwc3xf7LT+VT_B7eV3gug@mail.gmail.com>

Hi Shawn,

On Mon, May 13, 2013 at 11:31 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Have you tested it against v3.10-rc1?  The issue is still there in my
> testing.

I am not able to see the issue on 3.10-rc2.

What are the exact steps to trigger the problem? Do you see it consistently?


From dhobsong at igel.co.jp  Mon May 27 21:36:46 2013
From: dhobsong at igel.co.jp (Damian Hobson-Garcia)
Date: Tue, 28 May 2013 10:36:46 +0900
Subject: [PATCH v3 0/3] dma-mapping: Define dma_{alloc,
 free}_attrs() for all archs
Message-ID: <1369705006-16298-1-git-send-email-dhobsong@igel.co.jp>

Most architectures that define CONFIG_HAS_DMA=y, have implementations for
both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
not define CONFIG_HAS_DMA also have both of these definitions provided by
dma-mapping-broken.h.

Provide a default definition for the archs that define CONFIG_HAS_DMA=y,
but have no implementation for dma_{alloc,free}_attrs(). 

As I don't have hardware for any of these systems, the patches are only
compile-tested where I could (arm64, s390) and untested for the archs
where I couldn't find a readily available prebuilt cross-compiler (c6x).

Changes from v2
---------------
Correct commit log. CONFIG_HAVE_DMA should be CONFIG_HAS_DMA.
Remove parisc from the patch series as it has already been merged.

Changes from v1
---------------
arm64, s390:
 * Since these archs are using dma_ops, pass appropirate value for attrs to 
   dma_ops->alloc().
 * Indicate that these patches are compile teseted only (I don't have hardware)

c6x:
 * Indicate that this patch is untested (I don't have a cross compiler)

Cheers,
Damian

Damian Hobson-Garcia (3):
  arm64: Provide default implementation for dma_{alloc,free}_attrs
  c6x: Provide default implementation for dma_{alloc,free}_attrs
  s390: Provide default implementation for dma_{alloc,free}_attrs

 arch/arm64/include/asm/dma-mapping.h |   17 +++++++++++------
 arch/c6x/include/asm/dma-mapping.h   |    3 +++
 arch/s390/include/asm/dma-mapping.h  |   17 +++++++++++------
 3 files changed, 25 insertions(+), 12 deletions(-)

-- 
1.7.9.5



From dhobsong at igel.co.jp  Mon May 27 21:37:14 2013
From: dhobsong at igel.co.jp (Damian Hobson-Garcia)
Date: Tue, 28 May 2013 10:37:14 +0900
Subject: [PATCH v3 1/3] arm64: Provide default implementation for dma_{alloc,
 free}_attrs
Message-ID: <1369705034-16341-1-git-send-email-dhobsong@igel.co.jp>

Most architectures that define CONFIG_HAS_DMA, have implementations for
both dma_alloc_attrs() and dma_free_attrs().  All achitectures that do
not define CONFIG_HAS_DMA also have both of these definitions provided by
dma-mapping-broken.h.

Add default implementations for these functions on arm64.

Signed-off-by: Damian Hobson-Garcia <dhobsong at igel.co.jp>
---

 arch/arm64/include/asm/dma-mapping.h |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h
index 9947768..6ff7b8d 100644
--- a/arch/arm64/include/asm/dma-mapping.h
+++ b/arch/arm64/include/asm/dma-mapping.h
@@ -81,8 +81,12 @@ static inline void dma_mark_clean(void *addr, size_t size)
 {
 }
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flags)
+#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)
+#define dma_free_coherent(d, s, h, f) dma_free_attrs(d, s, h, f, NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				       dma_addr_t *dma_handle, gfp_t flags,
+				       struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 	void *vaddr;
@@ -90,13 +94,14 @@ static inline void *dma_alloc_coherent(struct device *dev, size_t size,
 	if (dma_alloc_from_coherent(dev, size, dma_handle, &vaddr))
 		return vaddr;
 
-	vaddr = ops->alloc(dev, size, dma_handle, flags, NULL);
+	vaddr = ops->alloc(dev, size, dma_handle, flags, attrs);
 	debug_dma_alloc_coherent(dev, size, *dma_handle, vaddr);
 	return vaddr;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dev_addr)
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				     void *vaddr, dma_addr_t dev_addr,
+				     struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
@@ -104,7 +109,7 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 		return;
 
 	debug_dma_free_coherent(dev, size, vaddr, dev_addr);
-	ops->free(dev, size, vaddr, dev_addr, NULL);
+	ops->free(dev, size, vaddr, dev_addr, attrs);
 }
 
 /*
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon May 27 21:43:50 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 May 2013 09:43:50 +0800
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <CAOMZO5DRuKrECnYDtZ0wOK6_vpW95Cwc3xf7LT+VT_B7eV3gug@mail.gmail.com>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <20130304031716.GC30431@S2101-09.ap.freescale.net>
 <CAOMZO5Ai-msRVeAqQFiRhfAxkb2DMTYJvTcYihBhFt6GMCFwPQ@mail.gmail.com>
 <20130323135608.GG6281@S2101-09.ap.freescale.net>
 <CAOMZO5BvT3CUhPECTQZQq_Q2YEqMJzmXPL5pj-3Qmq35jnvm1A@mail.gmail.com>
 <20130324141758.GH6281@S2101-09.ap.freescale.net>
 <CAOMZO5AeJUtyRC1BoAUiFihbjKtLMC2WBjaUXW0x+RE+QHYPnA@mail.gmail.com>
 <20130514023142.GA16250@S2101-09.ap.freescale.net>
 <CAOMZO5DRuKrECnYDtZ0wOK6_vpW95Cwc3xf7LT+VT_B7eV3gug@mail.gmail.com>
Message-ID: <20130528014348.GA19608@S2101-09.ap.freescale.net>

On Mon, May 27, 2013 at 09:52:21PM -0300, Fabio Estevam wrote:
> Hi Shawn,
> 
> On Mon, May 13, 2013 at 11:31 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > Have you tested it against v3.10-rc1?  The issue is still there in my
> > testing.
> 
> I am not able to see the issue on 3.10-rc2.
> 
My imx/dt branch is currently basing on v3.10-rc1, and I do not care if
it works on v3.10-rc2.  I have tested this patch enough on different
bases, and I'm not going to test it again and again to find a base which
happens to work.  I do not feel comfortable to merge this patch if it
only works on particular base.  Who knows if it will break again with
another random patches merged in.  There is some issue, and we need to
find the root cause of it instead of ignoring it by finding some random
base which hides it.

> What are the exact steps to trigger the problem? Do you see it consistently?

Before I answer your questions, can I ask if you have tried to reproduce
it on v3.10-rc1?

Shawn



From cdall at cs.columbia.edu  Mon May 27 21:53:46 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 18:53:46 -0700
Subject: [PATCH v3 1/7] ARM: KVM: be more thorough when invalidating TLBs
In-Reply-To: <1368529900-22572-2-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528015346.GA16071@ubuntu>

On Tue, May 14, 2013 at 12:11:34PM +0100, Marc Zyngier wrote:
> The KVM/ARM MMU code doesn't take care of invalidating TLBs before
> freeing a {pte,pmd} table. This could cause problems if the page
> is reallocated and then speculated into by another CPU.
> 
> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/kvm/mmu.c | 41 ++++++++++++++++++++++++++---------------
>  1 file changed, 26 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 9657065..84ba67b 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -43,7 +43,14 @@ static phys_addr_t hyp_idmap_vector;
>  
>  static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
>  {
> -	kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
> +	/*
> +	 * This function also gets called when dealing with HYP page
> +	 * tables. As HYP doesn't have an associated struct kvm (and
> +	 * the HYP page tables are fairly static), we don't do
> +	 * anything there.
> +	 */
> +	if (kvm)
> +		kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
>  }
>  
>  static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
> @@ -78,18 +85,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
>  	return p;
>  }
>  
> -static void clear_pud_entry(pud_t *pud)
> +static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
>  {
>  	pmd_t *pmd_table = pmd_offset(pud, 0);
>  	pud_clear(pud);
> +	kvm_tlb_flush_vmid_ipa(kvm, addr);
>  	pmd_free(NULL, pmd_table);
>  	put_page(virt_to_page(pud));
>  }
>  
> -static void clear_pmd_entry(pmd_t *pmd)
> +static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
>  {
>  	pte_t *pte_table = pte_offset_kernel(pmd, 0);
>  	pmd_clear(pmd);
> +	kvm_tlb_flush_vmid_ipa(kvm, addr);
>  	pte_free_kernel(NULL, pte_table);
>  	put_page(virt_to_page(pmd));
>  }
> @@ -100,11 +109,12 @@ static bool pmd_empty(pmd_t *pmd)
>  	return page_count(pmd_page) == 1;
>  }
>  
> -static void clear_pte_entry(pte_t *pte)
> +static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
>  {
>  	if (pte_present(*pte)) {
>  		kvm_set_pte(pte, __pte(0));
>  		put_page(virt_to_page(pte));
> +		kvm_tlb_flush_vmid_ipa(kvm, addr);
>  	}
>  }
>  
> @@ -114,7 +124,8 @@ static bool pte_empty(pte_t *pte)
>  	return page_count(pte_page) == 1;
>  }
>  
> -static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
> +static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
> +			unsigned long long start, u64 size)
>  {
>  	pgd_t *pgd;
>  	pud_t *pud;
> @@ -138,15 +149,15 @@ static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
>  		}
>  
>  		pte = pte_offset_kernel(pmd, addr);
> -		clear_pte_entry(pte);
> +		clear_pte_entry(kvm, pte, addr);
>  		range = PAGE_SIZE;
>  
>  		/* If we emptied the pte, walk back up the ladder */
>  		if (pte_empty(pte)) {
> -			clear_pmd_entry(pmd);
> +			clear_pmd_entry(kvm, pmd, addr);
>  			range = PMD_SIZE;
>  			if (pmd_empty(pmd)) {
> -				clear_pud_entry(pud);
> +				clear_pud_entry(kvm, pud, addr);
>  				range = PUD_SIZE;
>  			}
>  		}
> @@ -165,14 +176,14 @@ void free_boot_hyp_pgd(void)
>  	mutex_lock(&kvm_hyp_pgd_mutex);
>  
>  	if (boot_hyp_pgd) {
> -		unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
> -		unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
> +		unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
> +		unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
>  		kfree(boot_hyp_pgd);
>  		boot_hyp_pgd = NULL;
>  	}
>  
>  	if (hyp_pgd)
> -		unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
> +		unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
>  
>  	kfree(init_bounce_page);
>  	init_bounce_page = NULL;
> @@ -200,9 +211,10 @@ void free_hyp_pgds(void)
>  
>  	if (hyp_pgd) {
>  		for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
> -			unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
> +			unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
>  		for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
> -			unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
> +			unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
> +
>  		kfree(hyp_pgd);
>  		hyp_pgd = NULL;
>  	}
> @@ -393,7 +405,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
>   */
>  static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
>  {
> -	unmap_range(kvm->arch.pgd, start, size);
> +	unmap_range(kvm, kvm->arch.pgd, start, size);
>  }
>  
>  /**
> @@ -675,7 +687,6 @@ static void handle_hva_to_gpa(struct kvm *kvm,
>  static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
>  {
>  	unmap_stage2_range(kvm, gpa, PAGE_SIZE);
> -	kvm_tlb_flush_vmid_ipa(kvm, gpa);
>  }
>  
>  int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
> -- 
> 1.8.2.3
> 
> 
I think this could optimized by rewriting the handle_hva_to_gpa function
to use unmap_stage2_range for an actual range, but that funciton should
be rewritten to be generic for KVM anyhow.  I'll add it to my todo list.

I'll apply this patch and send it further upstream for an -rc release.

Thanks,
-Chritoffer


From cdall at cs.columbia.edu  Mon May 27 21:54:42 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 18:54:42 -0700
Subject: [PATCH v3 2/7] ARM: KVM: remove dead prototype for
 __kvm_tlb_flush_vmid
In-Reply-To: <1368529900-22572-3-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-3-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528015442.GB16071@ubuntu>

On Tue, May 14, 2013 at 12:11:35PM +0100, Marc Zyngier wrote:
> __kvm_tlb_flush_vmid has been renamed to __kvm_tlb_flush_vmid_ipa,
> and the old prototype should have been removed when the code was
> modified.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_asm.h | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
> index 18d5032..6ae3d2a 100644
> --- a/arch/arm/include/asm/kvm_asm.h
> +++ b/arch/arm/include/asm/kvm_asm.h
> @@ -72,8 +72,6 @@ extern char __kvm_hyp_vector[];
>  extern char __kvm_hyp_code_start[];
>  extern char __kvm_hyp_code_end[];
>  
> -extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
> -
>  extern void __kvm_flush_vm_context(void);
>  extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
>  
> -- 
> 1.8.2.3

Applied, thanks.
-Christoffer


From cdall at cs.columbia.edu  Mon May 27 22:10:02 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 19:10:02 -0700
Subject: [PATCH v3 3/7] ARM: KVM: relax cache maintainance when building
 page tables
In-Reply-To: <1368529900-22572-4-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-4-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528021002.GC16071@ubuntu>

On Tue, May 14, 2013 at 12:11:36PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required if running on a SMP capable platform
> (the HW PTW can snoop other cpus' L1).
> 
> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> a no-op for SMP ARMv7.
> 
> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_mmu.h | 17 +++++++++++------
>  arch/arm/kvm/mmu.c             |  7 ++++---
>  2 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
> index 472ac70..8c03c96 100644
> --- a/arch/arm/include/asm/kvm_mmu.h
> +++ b/arch/arm/include/asm/kvm_mmu.h
> @@ -65,11 +65,6 @@ void kvm_clear_hyp_idmap(void);
>  static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
>  {
>  	pte_val(*pte) = new_pte;
> -	/*
> -	 * flush_pmd_entry just takes a void pointer and cleans the necessary
> -	 * cache entries, so we can reuse the function for ptes.
> -	 */
> -	flush_pmd_entry(pte);
>  }
>  
>  static inline bool kvm_is_write_fault(unsigned long hsr)
> @@ -83,9 +78,19 @@ static inline bool kvm_is_write_fault(unsigned long hsr)
>  		return true;
>  }
>  
> +static inline void kvm_clean_dcache_area(void *addr, size_t size)
> +{
> +	clean_dcache_area(addr, size);
> +}
> +
> +static inline void kvm_clean_pte_entry(pte_t *pte)
> +{
> +	kvm_clean_dcache_area(pte, sizeof(*pte));
> +}
> +
>  static inline void kvm_clean_pgd(pgd_t *pgd)
>  {
> -	clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
> +	kvm_clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
>  }
>  
>  static inline void kvm_clean_pmd_entry(pmd_t *pmd)
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 84ba67b..451bad3 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -113,6 +113,7 @@ static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
>  {
>  	if (pte_present(*pte)) {
>  		kvm_set_pte(pte, __pte(0));
> +		kvm_clean_pte_entry(pte);
>  		put_page(virt_to_page(pte));
>  		kvm_tlb_flush_vmid_ipa(kvm, addr);
>  	}
> @@ -234,9 +235,10 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
>  		pte = pte_offset_kernel(pmd, addr);
>  		kvm_set_pte(pte, pfn_pte(pfn, prot));
>  		get_page(virt_to_page(pte));
> -		kvm_flush_dcache_to_poc(pte, sizeof(*pte));
>  		pfn++;
>  	} while (addr += PAGE_SIZE, addr != end);
> +
> +	kvm_clean_dcache_area((void *)start, end - start);
>  }
>  
>  static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
> @@ -261,7 +263,6 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
>  			}
>  			pmd_populate_kernel(NULL, pmd, pte);
>  			get_page(virt_to_page(pmd));
> -			kvm_flush_dcache_to_poc(pmd, sizeof(*pmd));
>  		}
>  
>  		next = pmd_addr_end(addr, end);
> @@ -299,7 +300,6 @@ static int __create_hyp_mappings(pgd_t *pgdp,
>  			}
>  			pud_populate(NULL, pud, pmd);
>  			get_page(virt_to_page(pud));
> -			kvm_flush_dcache_to_poc(pud, sizeof(*pud));
>  		}
>  
>  		next = pgd_addr_end(addr, end);
> @@ -469,6 +469,7 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
>  	/* Create 2nd stage page table mapping - Level 3 */
>  	old_pte = *pte;
>  	kvm_set_pte(pte, *new_pte);
> +	kvm_clean_pte_entry(pte);
>  	if (pte_present(old_pte))
>  		kvm_tlb_flush_vmid_ipa(kvm, addr);
>  	else
> -- 
> 1.8.2.3
> 
> 
I don't care for this change, you have three places where you call
kvm_set_pte and immediately follow with kvm_clean_pte_entry now, just to
optimize the uncommon case only relevant when creating new VMs, and at
the same time do things differently from the rest of the kernel with
set_pte functions (yes, I know it's a static in this file, but that
doesn't mean that readers of this file wouldn't make that association).
The next function that calls kvm_set_pte must now also remember to call
the clean functions, bah.

I think the kvm_clean_pte_entry should just be called from within
kvm_set_pte.

-Christoffer


From cdall at cs.columbia.edu  Mon May 27 22:11:21 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 19:11:21 -0700
Subject: [PATCH v3 4/7] ARM: KVM: use phys_addr_t instead of unsigned
 long long for HYP PGDs
In-Reply-To: <1368529900-22572-5-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-5-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528021121.GD16071@ubuntu>

On Tue, May 14, 2013 at 12:11:37PM +0100, Marc Zyngier wrote:
> HYP PGDs are passed around as phys_addr_t, except just before calling
> into the hypervisor init code, where they are cast to a rather weird
> unsigned long long.
> 
> Just keep them around as phys_addr_t, which is what makes the most
> sense.
> 
> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_host.h | 4 ++--
>  arch/arm/kvm/arm.c              | 8 ++++----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
> index 57cb786..ff49193 100644
> --- a/arch/arm/include/asm/kvm_host.h
> +++ b/arch/arm/include/asm/kvm_host.h
> @@ -190,8 +190,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
>  int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
>  		int exception_index);
>  
> -static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
> -				       unsigned long long pgd_ptr,
> +static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
> +				       phys_addr_t pgd_ptr,
>  				       unsigned long hyp_stack_ptr,
>  				       unsigned long vector_ptr)
>  {
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 37d216d..327a1fb 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -789,8 +789,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
>  
>  static void cpu_init_hyp_mode(void *dummy)
>  {
> -	unsigned long long boot_pgd_ptr;
> -	unsigned long long pgd_ptr;
> +	phys_addr_t boot_pgd_ptr;
> +	phys_addr_t pgd_ptr;
>  	unsigned long hyp_stack_ptr;
>  	unsigned long stack_page;
>  	unsigned long vector_ptr;
> @@ -798,8 +798,8 @@ static void cpu_init_hyp_mode(void *dummy)
>  	/* Switch from the HYP stub to our own HYP init vector */
>  	__hyp_set_vectors(kvm_get_idmap_vector());
>  
> -	boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
> -	pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
> +	boot_pgd_ptr = kvm_mmu_get_boot_httbr();
> +	pgd_ptr = kvm_mmu_get_httbr();
>  	stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
>  	hyp_stack_ptr = stack_page + PAGE_SIZE;
>  	vector_ptr = (unsigned long)__kvm_hyp_vector;
> -- 
> 1.8.2.3
> 
> 
Applied, thanks.

-Christoffer


From cdall at cs.columbia.edu  Mon May 27 22:11:57 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 19:11:57 -0700
Subject: [PATCH v3 5/7] ARM: KVM: don't special case PC when doing an MMIO
In-Reply-To: <1368529900-22572-6-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-6-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528021157.GE16071@ubuntu>

On Tue, May 14, 2013 at 12:11:38PM +0100, Marc Zyngier wrote:
> Admitedly, reading a MMIO register to load PC is very weird.
> Writing PC to a MMIO register is probably even worse. But
> the architecture doesn't forbid any of these, and injecting
> a Prefetch Abort is the wrong thing to do anyway.
> 
> Remove this check altogether, and let the adventurous guest
> wander into LaLaLand if they feel compelled to do so.
> 
> Reported-by: Catalin Marinas <catalin.marinas at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_emulate.h | 5 -----
>  arch/arm/kvm/mmio.c                | 6 ------
>  2 files changed, 11 deletions(-)
> 
> diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
> index 82b4bab..a464e8d 100644
> --- a/arch/arm/include/asm/kvm_emulate.h
> +++ b/arch/arm/include/asm/kvm_emulate.h
> @@ -65,11 +65,6 @@ static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
>  	return cpsr_mode > USR_MODE;;
>  }
>  
> -static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
> -{
> -	return reg == 15;
> -}
> -
>  static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
>  {
>  	return vcpu->arch.fault.hsr;
> diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
> index 72a12f2..b8e06b7 100644
> --- a/arch/arm/kvm/mmio.c
> +++ b/arch/arm/kvm/mmio.c
> @@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
>  	sign_extend = kvm_vcpu_dabt_issext(vcpu);
>  	rt = kvm_vcpu_dabt_get_rd(vcpu);
>  
> -	if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
> -		/* IO memory trying to read/write pc */
> -		kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
> -		return 1;
> -	}
> -
>  	mmio->is_write = is_write;
>  	mmio->phys_addr = fault_ipa;
>  	mmio->len = len;
> -- 
> 1.8.2.3
> 
> 
Applied, thanks.
-Christoffer


From cdall at cs.columbia.edu  Mon May 27 22:12:38 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 19:12:38 -0700
Subject: [PATCH v3 6/7] ARM: KVM: get rid of S2_PGD_SIZE
In-Reply-To: <1368529900-22572-7-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-7-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528021238.GF16071@ubuntu>

On Tue, May 14, 2013 at 12:11:39PM +0100, Marc Zyngier wrote:
> S2_PGD_SIZE defines the number of pages used by a stage-2 PGD
> and is unused, except for a VM_BUG_ON check that missuses the
> define.
> 
> As the check is very unlikely to ever triggered except in
> circumstances where KVM is the least of our worries, just kill
> both the define and the VM_BUG_ON check.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_arm.h | 1 -
>  arch/arm/kvm/mmu.c             | 3 ---
>  2 files changed, 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
> index 124623e..64e9696 100644
> --- a/arch/arm/include/asm/kvm_arm.h
> +++ b/arch/arm/include/asm/kvm_arm.h
> @@ -135,7 +135,6 @@
>  #define KVM_PHYS_MASK	(KVM_PHYS_SIZE - 1ULL)
>  #define PTRS_PER_S2_PGD	(1ULL << (KVM_PHYS_SHIFT - 30))
>  #define S2_PGD_ORDER	get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
> -#define S2_PGD_SIZE	(1 << S2_PGD_ORDER)
>  
>  /* Virtualization Translation Control Register (VTCR) bits */
>  #define VTCR_SH0	(3 << 12)
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 451bad3..693d16c 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -382,9 +382,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
>  	if (!pgd)
>  		return -ENOMEM;
>  
> -	/* stage-2 pgd must be aligned to its size */
> -	VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
> -
>  	memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
>  	kvm_clean_pgd(pgd);
>  	kvm->arch.pgd = pgd;
> -- 
> 1.8.2.3
> 
> 
Applied, thanks.
-Christoffer


From cdall at cs.columbia.edu  Mon May 27 22:15:28 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Mon, 27 May 2013 19:15:28 -0700
Subject: [PATCH v3 6/7] ARM: KVM: get rid of S2_PGD_SIZE
In-Reply-To: <1368529900-22572-7-git-send-email-marc.zyngier@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-7-git-send-email-marc.zyngier@arm.com>
Message-ID: <20130528021528.GG16071@ubuntu>

On Tue, May 14, 2013 at 12:11:39PM +0100, Marc Zyngier wrote:
> S2_PGD_SIZE defines the number of pages used by a stage-2 PGD
> and is unused, except for a VM_BUG_ON check that missuses the
> define.
> 
> As the check is very unlikely to ever triggered except in
> circumstances where KVM is the least of our worries, just kill
> both the define and the VM_BUG_ON check.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>  arch/arm/include/asm/kvm_arm.h | 1 -
>  arch/arm/kvm/mmu.c             | 3 ---
>  2 files changed, 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
> index 124623e..64e9696 100644
> --- a/arch/arm/include/asm/kvm_arm.h
> +++ b/arch/arm/include/asm/kvm_arm.h
> @@ -135,7 +135,6 @@
>  #define KVM_PHYS_MASK	(KVM_PHYS_SIZE - 1ULL)
>  #define PTRS_PER_S2_PGD	(1ULL << (KVM_PHYS_SHIFT - 30))
>  #define S2_PGD_ORDER	get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
> -#define S2_PGD_SIZE	(1 << S2_PGD_ORDER)
>  
>  /* Virtualization Translation Control Register (VTCR) bits */
>  #define VTCR_SH0	(3 << 12)
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 451bad3..693d16c 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -382,9 +382,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
>  	if (!pgd)
>  		return -ENOMEM;
>  
> -	/* stage-2 pgd must be aligned to its size */
> -	VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
> -
>  	memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
>  	kvm_clean_pgd(pgd);
>  	kvm->arch.pgd = pgd;
> -- 
> 1.8.2.3
> 
> 
Thanks for spotting this, applied.

-Christoffer


From haojian.zhuang at gmail.com  Mon May 27 22:21:42 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 May 2013 10:21:42 +0800
Subject: [PATCH v2 0/5] ARM: mmp: move irq driver into irqchip
Message-ID: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>

Changelog:
v2:
1. Avoid to include <mach/irqs.h>. Move the head file into
   include/linux/irqchip directory.
2. Avoid to include <mach/pm-pxa910.h> & <mach/pm-mmp2.h>.



From haojian.zhuang at gmail.com  Mon May 27 22:21:43 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 May 2013 10:21:43 +0800
Subject: [PATCH v2 1/5] irqchip: move mmp irq driver
In-Reply-To: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1369707707-30295-2-git-send-email-haojian.zhuang@gmail.com>

Move irq-mmp driver from mach-mmp directory into irqchip directory.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-mmp/Makefile                           | 2 +-
 arch/arm/mach-mmp/common.h                           | 1 -
 arch/arm/mach-mmp/include/mach/pxa168.h              | 1 +
 arch/arm/mach-mmp/include/mach/pxa910.h              | 1 +
 arch/arm/mach-mmp/pxa910.c                           | 1 +
 drivers/irqchip/Makefile                             | 1 +
 arch/arm/mach-mmp/irq.c => drivers/irqchip/irq-mmp.c | 2 --
 7 files changed, 5 insertions(+), 4 deletions(-)
 rename arch/arm/mach-mmp/irq.c => drivers/irqchip/irq-mmp.c (99%)

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 095c155..9b702a1 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y				+= common.o devices.o time.o irq.o
+obj-y				+= common.o devices.o time.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)	+= pxa168.o
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..9c1c9be 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -2,7 +2,6 @@
 
 extern void timer_init(int irq);
 
-extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
 extern void __init pxa168_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df2..e01dc2a 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -2,6 +2,7 @@
 #define __ASM_MACH_PXA168_H
 
 extern void pxa168_timer_init(void);
+extern void __init icu_init_irq(void);
 extern void __init pxa168_init_irq(void);
 extern void pxa168_restart(char, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index b914afa..9225320 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -2,6 +2,7 @@
 #define __ASM_MACH_PXA910_H
 
 extern void pxa910_timer_init(void);
+extern void __init icu_init_irq(void);
 extern void __init pxa910_init_irq(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index ce6393a..a586742 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -23,6 +23,7 @@
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
+#include <mach/pxa910.h>
 
 #include "common.h"
 
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5..542d47e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
+obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
 obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
diff --git a/arch/arm/mach-mmp/irq.c b/drivers/irqchip/irq-mmp.c
similarity index 99%
rename from arch/arm/mach-mmp/irq.c
rename to drivers/irqchip/irq-mmp.c
index 3c71246..dab6def 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -30,8 +30,6 @@
 #include <mach/pm-pxa910.h>
 #endif
 
-#include "common.h"
-
 #define MAX_ICU_NR		16
 
 struct icu_chip_data {
-- 
1.8.1.2



From haojian.zhuang at gmail.com  Mon May 27 22:21:44 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 May 2013 10:21:44 +0800
Subject: [PATCH v2 2/5] irqchip: mmp: support irqchip
In-Reply-To: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1369707707-30295-3-git-send-email-haojian.zhuang@gmail.com>

Support IRQCHIP on irq-mmp driver.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-mmp/mmp-dt.c  |  10 +--
 arch/arm/mach-mmp/mmp2-dt.c |   9 +-
 drivers/irqchip/irq-mmp.c   | 208 ++++++++++++++++++++++----------------------
 3 files changed, 109 insertions(+), 118 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index b37915d..aaca3c8 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -9,17 +9,13 @@
  *  publishhed by the Free Software Foundation.
  */
 
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
-extern void __init mmp_dt_irq_init(void);
 extern void __init mmp_dt_init_timer(void);
 
 static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
@@ -64,7 +60,7 @@ static const char *mmp_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
 	.map_io		= mmp_map_io,
-	.init_irq	= mmp_dt_irq_init,
+	.init_irq	= irqchip_init,
 	.init_time	= mmp_dt_init_timer,
 	.init_machine	= pxa168_dt_init,
 	.dt_compat	= mmp_dt_board_compat,
@@ -72,7 +68,7 @@ MACHINE_END
 
 DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
 	.map_io		= mmp_map_io,
-	.init_irq	= mmp_dt_irq_init,
+	.init_irq	= irqchip_init,
 	.init_time	= mmp_dt_init_timer,
 	.init_machine	= pxa910_dt_init,
 	.dt_compat	= mmp_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 4ac2567..d12231d 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -10,18 +10,13 @@
  */
 
 #include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
-#include <mach/regs-apbc.h>
 
 #include "common.h"
 
-extern void __init mmp_dt_irq_init(void);
 extern void __init mmp_dt_init_timer(void);
 
 static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
@@ -49,7 +44,7 @@ static const char *mmp2_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
 	.map_io		= mmp_map_io,
-	.init_irq	= mmp_dt_irq_init,
+	.init_irq	= irqchip_init,
 	.init_time	= mmp_dt_init_timer,
 	.init_machine	= mmp2_dt_init,
 	.dt_compat	= mmp2_dt_board_compat,
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index dab6def..2f088ba 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -30,6 +30,8 @@
 #include <mach/pm-pxa910.h>
 #endif
 
+#include "irqchip.h"
+
 #define MAX_ICU_NR		16
 
 struct icu_chip_data {
@@ -324,138 +326,136 @@ void __init mmp2_init_icu(void)
 }
 
 #ifdef CONFIG_OF
-static const struct of_device_id intc_ids[] __initconst = {
-	{ .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
-	{ .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
-	{}
-};
-
-static const struct of_device_id mmp_mux_irq_match[] __initconst = {
-	{ .compatible = "mrvl,mmp2-mux-intc" },
-	{}
-};
-
-int __init mmp2_mux_init(struct device_node *parent)
+static int __init mmp_init_bases(struct device_node *node)
 {
-	struct device_node *node;
-	const struct of_device_id *of_id;
-	struct resource res;
-	int i, irq_base, ret, irq;
-	u32 nr_irqs, mfp_irq;
-
-	node = parent;
-	max_icu_nr = 1;
-	for (i = 1; i < MAX_ICU_NR; i++) {
-		node = of_find_matching_node(node, mmp_mux_irq_match);
-		if (!node)
-			break;
-		of_id = of_match_node(&mmp_mux_irq_match[0], node);
-		ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
-					   &nr_irqs);
-		if (ret) {
-			pr_err("Not found mrvl,intc-nr-irqs property\n");
-			ret = -EINVAL;
-			goto err;
-		}
-		ret = of_address_to_resource(node, 0, &res);
-		if (ret < 0) {
-			pr_err("Not found reg property\n");
-			ret = -EINVAL;
-			goto err;
-		}
-		icu_data[i].reg_status = mmp_icu_base + res.start;
-		ret = of_address_to_resource(node, 1, &res);
-		if (ret < 0) {
-			pr_err("Not found reg property\n");
-			ret = -EINVAL;
-			goto err;
-		}
-		icu_data[i].reg_mask = mmp_icu_base + res.start;
-		icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
-		if (!icu_data[i].cascade_irq) {
-			ret = -EINVAL;
-			goto err;
-		}
-
-		irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
-		if (irq_base < 0) {
-			pr_err("Failed to allocate IRQ numbers for mux intc\n");
-			ret = irq_base;
-			goto err;
-		}
-		if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
-					  &mfp_irq)) {
-			icu_data[i].clr_mfp_irq_base = irq_base;
-			icu_data[i].clr_mfp_hwirq = mfp_irq;
-		}
-		irq_set_chained_handler(icu_data[i].cascade_irq,
-					icu_mux_irq_demux);
-		icu_data[i].nr_irqs = nr_irqs;
-		icu_data[i].virq_base = irq_base;
-		icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
-							   irq_base, 0,
-							   &mmp_irq_domain_ops,
-							   &icu_data[i]);
-		for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
-			icu_mask_irq(irq_get_irq_data(irq));
-	}
-	max_icu_nr = i;
-	return 0;
-err:
-	of_node_put(node);
-	max_icu_nr = i;
-	return ret;
-}
-
-void __init mmp_dt_irq_init(void)
-{
-	struct device_node *node;
-	const struct of_device_id *of_id;
-	struct mmp_intc_conf *conf;
-	int nr_irqs, irq_base, ret, irq;
-
-	node = of_find_matching_node(NULL, intc_ids);
-	if (!node) {
-		pr_err("Failed to find interrupt controller in arch-mmp\n");
-		return;
-	}
-	of_id = of_match_node(intc_ids, node);
-	conf = of_id->data;
+	int ret, nr_irqs, irq, irq_base;
 
 	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
 	if (ret) {
 		pr_err("Not found mrvl,intc-nr-irqs property\n");
-		return;
+		return ret;
 	}
 
 	mmp_icu_base = of_iomap(node, 0);
 	if (!mmp_icu_base) {
 		pr_err("Failed to get interrupt controller register\n");
-		return;
+		return -ENOMEM;
 	}
 
 	irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
 	if (irq_base < 0) {
 		pr_err("Failed to allocate IRQ numbers\n");
+		ret = irq_base;
 		goto err;
 	} else if (irq_base != NR_IRQS_LEGACY) {
 		pr_err("ICU's irqbase should be started from 0\n");
+		ret = -EINVAL;
 		goto err;
 	}
-	icu_data[0].conf_enable = conf->conf_enable;
-	icu_data[0].conf_disable = conf->conf_disable;
-	icu_data[0].conf_mask = conf->conf_mask;
 	icu_data[0].nr_irqs = nr_irqs;
 	icu_data[0].virq_base = 0;
 	icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
 						   &mmp_irq_domain_ops,
 						   &icu_data[0]);
-	irq_set_default_host(icu_data[0].domain);
 	for (irq = 0; irq < nr_irqs; irq++)
 		icu_mask_irq(irq_get_irq_data(irq));
-	mmp2_mux_init(node);
-	return;
+	return 0;
 err:
 	iounmap(mmp_icu_base);
+	return ret;
+}
+
+static int __init mmp_of_init(struct device_node *node,
+			      struct device_node *parent)
+{
+	int ret;
+
+	ret = mmp_init_bases(node);
+	if (ret < 0)
+		return ret;
+
+	icu_data[0].conf_enable = mmp_conf.conf_enable;
+	icu_data[0].conf_disable = mmp_conf.conf_disable;
+	icu_data[0].conf_mask = mmp_conf.conf_mask;
+	irq_set_default_host(icu_data[0].domain);
+	max_icu_nr = 1;
+	return 0;
+}
+
+static int __init mmp2_of_init(struct device_node *node,
+			       struct device_node *parent)
+{
+	int ret;
+
+	ret = mmp_init_bases(node);
+	if (ret < 0)
+		return ret;
+
+	icu_data[0].conf_enable = mmp2_conf.conf_enable;
+	icu_data[0].conf_disable = mmp2_conf.conf_disable;
+	icu_data[0].conf_mask = mmp2_conf.conf_mask;
+	irq_set_default_host(icu_data[0].domain);
+	max_icu_nr = 1;
+	return 0;
+}
+
+static int __init mmp2_mux_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	struct resource res;
+	int i, irq_base, ret, irq;
+	u32 nr_irqs, mfp_irq;
+
+	if (!parent)
+		return -ENODEV;
+
+	i = max_icu_nr;
+	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
+				   &nr_irqs);
+	if (ret) {
+		pr_err("Not found mrvl,intc-nr-irqs property\n");
+		return -EINVAL;
+	}
+	ret = of_address_to_resource(node, 0, &res);
+	if (ret < 0) {
+		pr_err("Not found reg property\n");
+		return -EINVAL;
+	}
+	icu_data[i].reg_status = mmp_icu_base + res.start;
+	ret = of_address_to_resource(node, 1, &res);
+	if (ret < 0) {
+		pr_err("Not found reg property\n");
+		return -EINVAL;
+	}
+	icu_data[i].reg_mask = mmp_icu_base + res.start;
+	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
+	if (!icu_data[i].cascade_irq)
+		return -EINVAL;
+
+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+	if (irq_base < 0) {
+		pr_err("Failed to allocate IRQ numbers for mux intc\n");
+		return irq_base;
+	}
+	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
+				  &mfp_irq)) {
+		icu_data[i].clr_mfp_irq_base = irq_base;
+		icu_data[i].clr_mfp_hwirq = mfp_irq;
+	}
+	irq_set_chained_handler(icu_data[i].cascade_irq,
+				icu_mux_irq_demux);
+	icu_data[i].nr_irqs = nr_irqs;
+	icu_data[i].virq_base = irq_base;
+	icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
+						   irq_base, 0,
+						   &mmp_irq_domain_ops,
+						   &icu_data[i]);
+	for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+		icu_mask_irq(irq_get_irq_data(irq));
+	max_icu_nr++;
+	return 0;
 }
+IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
+IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
+IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
 #endif
-- 
1.8.1.2



From haojian.zhuang at gmail.com  Mon May 27 22:21:45 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 May 2013 10:21:45 +0800
Subject: [PATCH v2 3/5] irqchip: mmp: support MULTI_IRQ_HANDLER
In-Reply-To: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1369707707-30295-4-git-send-email-haojian.zhuang@gmail.com>

Support CONFIG_MULTI_IRQ_HANDLER in ARCH_MMP. So remove entry-macro.S.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/Kconfig                             |  1 +
 arch/arm/mach-mmp/include/mach/entry-macro.S | 26 -----------------
 drivers/irqchip/irq-mmp.c                    | 42 +++++++++++++++++++++++++++-
 3 files changed, 42 insertions(+), 27 deletions(-)
 delete mode 100644 arch/arm/mach-mmp/include/mach/entry-macro.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..b8ba50b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -550,6 +550,7 @@ config ARCH_MMP
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PXA
 	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
 	select NEED_MACH_GPIO_H
 	select PINCTRL
 	select PLAT_PXA
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
deleted file mode 100644
index bd152e2..0000000
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/irq.h>
-#include <mach/regs-icu.h>
-
-	.macro	get_irqnr_preamble, base, tmp
-	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
-	and	\tmp, \tmp, #0xff00
-	cmp	\tmp, #0x5800
-	ldr	\base, =mmp_icu_base
-	ldr	\base, [\base, #0]
-	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register
-	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register
-	.endm
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	ldr	\tmp, [\base, #0]
-	and	\irqnr, \tmp, #0x3f
-	tst	\tmp, #(1 << 6)
-	.endm
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 2f088ba..f54ebca 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -21,6 +21,9 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
 #include <mach/irqs.h>
 
 #ifdef CONFIG_CPU_MMP2
@@ -34,6 +37,13 @@
 
 #define MAX_ICU_NR		16
 
+#define PJ1_INT_SEL		0x10c
+#define PJ4_INT_SEL		0x104
+
+/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
+#define SEL_INT_PENDING		(1 << 6)
+#define SEL_INT_NUM_MASK	0x3f
+
 struct icu_chip_data {
 	int			nr_irqs;
 	unsigned int		virq_base;
@@ -54,7 +64,7 @@ struct mmp_intc_conf {
 	unsigned int	conf_mask;
 };
 
-void __iomem *mmp_icu_base;
+static void __iomem *mmp_icu_base;
 static struct icu_chip_data icu_data[MAX_ICU_NR];
 static int max_icu_nr;
 
@@ -193,6 +203,32 @@ static struct mmp_intc_conf mmp2_conf = {
 	.conf_mask	= 0x7f,
 };
 
+static asmlinkage void __exception_irq_entry
+mmp_handle_irq(struct pt_regs *regs)
+{
+	int irq, hwirq;
+
+	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
+	if (!(hwirq & SEL_INT_PENDING))
+		return;
+	hwirq &= SEL_INT_NUM_MASK;
+	irq = irq_find_mapping(icu_data[0].domain, hwirq);
+	handle_IRQ(irq, regs);
+}
+
+static asmlinkage void __exception_irq_entry
+mmp2_handle_irq(struct pt_regs *regs)
+{
+	int irq, hwirq;
+
+	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
+	if (!(hwirq & SEL_INT_PENDING))
+		return;
+	hwirq &= SEL_INT_NUM_MASK;
+	irq = irq_find_mapping(icu_data[0].domain, hwirq);
+	handle_IRQ(irq, regs);
+}
+
 /* MMP (ARMv5) */
 void __init icu_init_irq(void)
 {
@@ -214,6 +250,7 @@ void __init icu_init_irq(void)
 		set_irq_flags(irq, IRQF_VALID);
 	}
 	irq_set_default_host(icu_data[0].domain);
+	set_handle_irq(mmp_handle_irq);
 #ifdef CONFIG_CPU_PXA910
 	icu_irq_chip.irq_set_wake = pxa910_set_wake;
 #endif
@@ -320,6 +357,7 @@ void __init mmp2_init_icu(void)
 		set_irq_flags(irq, IRQF_VALID);
 	}
 	irq_set_default_host(icu_data[0].domain);
+	set_handle_irq(mmp2_handle_irq);
 #ifdef CONFIG_CPU_MMP2
 	icu_irq_chip.irq_set_wake = mmp2_set_wake;
 #endif
@@ -378,6 +416,7 @@ static int __init mmp_of_init(struct device_node *node,
 	icu_data[0].conf_disable = mmp_conf.conf_disable;
 	icu_data[0].conf_mask = mmp_conf.conf_mask;
 	irq_set_default_host(icu_data[0].domain);
+	set_handle_irq(mmp_handle_irq);
 	max_icu_nr = 1;
 	return 0;
 }
@@ -395,6 +434,7 @@ static int __init mmp2_of_init(struct device_node *node,
 	icu_data[0].conf_disable = mmp2_conf.conf_disable;
 	icu_data[0].conf_mask = mmp2_conf.conf_mask;
 	irq_set_default_host(icu_data[0].domain);
+	set_handle_irq(mmp2_handle_irq);
 	max_icu_nr = 1;
 	return 0;
 }
-- 
1.8.1.2



From haojian.zhuang at gmail.com  Mon May 27 22:21:46 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 May 2013 10:21:46 +0800
Subject: [PATCH v2 4/5] ARM: mmp: move irqs head file
In-Reply-To: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1369707707-30295-5-git-send-email-haojian.zhuang@gmail.com>

Since irq-mmp driver includes <mach/irqs.h>, it blocks the multiple
platform build. So move the head file into include/linux/irqchip/
directory.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-mmp/aspenite.c                                         | 2 +-
 arch/arm/mach-mmp/avengers_lite.c                                    | 2 +-
 arch/arm/mach-mmp/brownstone.c                                       | 2 +-
 arch/arm/mach-mmp/devices.c                                          | 2 +-
 arch/arm/mach-mmp/flint.c                                            | 2 +-
 arch/arm/mach-mmp/gplugd.c                                           | 2 +-
 arch/arm/mach-mmp/jasper.c                                           | 2 +-
 arch/arm/mach-mmp/mmp2.c                                             | 2 +-
 arch/arm/mach-mmp/pm-mmp2.c                                          | 2 +-
 arch/arm/mach-mmp/pm-pxa910.c                                        | 2 +-
 arch/arm/mach-mmp/pxa168.c                                           | 2 +-
 arch/arm/mach-mmp/pxa910.c                                           | 2 +-
 arch/arm/mach-mmp/tavorevb.c                                         | 2 +-
 arch/arm/mach-mmp/teton_bga.c                                        | 2 +-
 arch/arm/mach-mmp/time.c                                             | 2 +-
 arch/arm/mach-mmp/ttc_dkb.c                                          | 2 +-
 drivers/gpio/gpio-pxa.c                                              | 3 +--
 drivers/irqchip/irq-mmp.c                                            | 3 +--
 arch/arm/mach-mmp/include/mach/irqs.h => include/linux/irqchip/mmp.h | 0
 19 files changed, 18 insertions(+), 20 deletions(-)
 rename arch/arm/mach-mmp/include/mach/irqs.h => include/linux/irqchip/mmp.h (100%)

diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 5b660ec..e850fc0 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -11,6 +11,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/init.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/smc91x.h>
@@ -25,7 +26,6 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa168.h>
 #include <mach/pxa168.h>
-#include <mach/irqs.h>
 #include <video/pxa168fb.h>
 #include <linux/input.h>
 #include <linux/platform_data/keypad-pxa27x.h>
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index a451a0f..c2c5b09 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/kernel.h>
 #include <linux/gpio-pxa.h>
 #include <linux/platform_device.h>
@@ -20,7 +21,6 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa168.h>
 #include <mach/pxa168.h>
-#include <mach/irqs.h>
 
 
 #include "common.h"
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index ac25544..41941b6 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/gpio-pxa.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
@@ -25,7 +26,6 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-mmp2.h>
 #include <mach/mmp2.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index dd2d8b1..bbb0aa0 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -7,12 +7,12 @@
  */
 
 #include <linux/init.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/delay.h>
 
 #include <asm/irq.h>
-#include <mach/irqs.h>
 #include <mach/devices.h>
 #include <mach/cputype.h>
 #include <mach/regs-usb.h>
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index 6291c33..0c733f5 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/smc91x.h>
 #include <linux/io.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
@@ -24,7 +25,6 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-mmp2.h>
 #include <mach/mmp2.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index d81b247..87b884f 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -9,6 +9,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
@@ -16,7 +17,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/irqs.h>
 #include <mach/pxa168.h>
 #include <mach/mfp-pxa168.h>
 
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 0e9e5c0..68dc03b 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -15,12 +15,12 @@
 #include <linux/gpio-pxa.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
 #include <linux/mfd/max8925.h>
 #include <linux/interrupt.h>
 
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/addr-map.h>
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c7592f1..08245c7 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 
 #include <asm/hardware/cache-tauros2.h>
@@ -21,7 +22,6 @@
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/cputype.h>
-#include <mach/irqs.h>
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c
index 461a191..7646829 100644
--- a/arch/arm/mach-mmp/pm-mmp2.c
+++ b/arch/arm/mach-mmp/pm-mmp2.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/suspend.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <asm/mach-types.h>
@@ -23,7 +24,6 @@
 #include <mach/addr-map.h>
 #include <mach/pm-mmp2.h>
 #include <mach/regs-icu.h>
-#include <mach/irqs.h>
 
 int mmp2_set_wake(struct irq_data *d, unsigned int on)
 {
diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c
index 48981ca..e919539 100644
--- a/arch/arm/mach-mmp/pm-pxa910.c
+++ b/arch/arm/mach-mmp/pm-pxa910.c
@@ -17,13 +17,13 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mmp.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/cputype.h>
 #include <mach/addr-map.h>
 #include <mach/pm-pxa910.h>
 #include <mach/regs-icu.h>
-#include <mach/irqs.h>
 
 int pxa910_set_wake(struct irq_data *data, unsigned int on)
 {
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3..8da96de 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/list.h>
 #include <linux/io.h>
 #include <linux/clk.h>
@@ -22,7 +23,6 @@
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
-#include <mach/irqs.h>
 #include <mach/dma.h>
 #include <mach/devices.h>
 #include <mach/mfp.h>
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index a586742..4ce3e16 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 
 #include <asm/hardware/cache-tauros2.h>
@@ -19,7 +20,6 @@
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/cputype.h>
-#include <mach/irqs.h>
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index cdfc9bf..d3bb3a7 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/init.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/smc91x.h>
@@ -19,7 +20,6 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index e4d95b4..a88a2ff 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -18,6 +18,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/input.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_data/keypad-pxa27x.h>
 #include <linux/i2c.h>
 
@@ -27,7 +28,6 @@
 #include <mach/mfp-pxa168.h>
 #include <mach/pxa168.h>
 #include <mach/teton_bga.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 86a18b3..891b9da 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,6 +25,7 @@
 
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -33,7 +34,6 @@
 #include <mach/addr-map.h>
 #include <mach/regs-timers.h>
 #include <mach/regs-apbc.h>
-#include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <asm/mach/time.h>
 
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 8483906..39db088 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,6 +15,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
@@ -29,7 +30,6 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
-#include <mach/irqs.h>
 #include <mach/regs-usb.h>
 
 #include "common.h"
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index df2199d..cb8f31f 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -20,6 +20,7 @@
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -27,8 +28,6 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
-
 /*
  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
  * one set of registers. The register offsets are organized below:
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index f54ebca..90fe265 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/irqdomain.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
@@ -24,8 +25,6 @@
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 
-#include <mach/irqs.h>
-
 #ifdef CONFIG_CPU_MMP2
 #include <mach/pm-mmp2.h>
 #endif
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/include/linux/irqchip/mmp.h
similarity index 100%
rename from arch/arm/mach-mmp/include/mach/irqs.h
rename to include/linux/irqchip/mmp.h
-- 
1.8.1.2



From haojian.zhuang at gmail.com  Mon May 27 22:21:47 2013
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 May 2013 10:21:47 +0800
Subject: [PATCH v2 5/5] ARM: mmp: avoid to include head file in mach-mmp
In-Reply-To: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1369707707-30295-6-git-send-email-haojian.zhuang@gmail.com>

pxa910_set_wake() & mmp2_set_wake() are both declared in head files
of arch/arm/mach-mmp/include/mach directory. If we include these
head files in irq-mmp driver, it blocks the multiplatform build.

So adjust the code.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-mmp/mmp2.c    |  3 +++
 arch/arm/mach-mmp/pxa910.c  |  3 +++
 drivers/irqchip/irq-mmp.c   | 15 +--------------
 include/linux/irqchip/mmp.h |  2 ++
 4 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 08245c7..2e5ce13 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 
@@ -26,6 +27,7 @@
 #include <mach/mfp.h>
 #include <mach/devices.h>
 #include <mach/mmp2.h>
+#include <mach/pm-mmp2.h>
 
 #include "common.h"
 
@@ -94,6 +96,7 @@ void mmp2_clear_pmic_int(void)
 void __init mmp2_init_irq(void)
 {
 	mmp2_init_icu();
+	icu_irq_chip.irq_set_wake = mmp2_set_wake;
 }
 
 static int __init mmp2_init(void)
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 4ce3e16..78b6e22 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 
@@ -23,6 +24,7 @@
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
+#include <mach/pm-pxa910.h>
 #include <mach/pxa910.h>
 
 #include "common.h"
@@ -80,6 +82,7 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
 void __init pxa910_init_irq(void)
 {
 	icu_init_irq();
+	icu_irq_chip.irq_set_wake = pxa910_set_wake;
 }
 
 static int __init pxa910_init(void)
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 90fe265..b2ec91a 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -25,13 +25,6 @@
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 
-#ifdef CONFIG_CPU_MMP2
-#include <mach/pm-mmp2.h>
-#endif
-#ifdef CONFIG_CPU_PXA910
-#include <mach/pm-pxa910.h>
-#endif
-
 #include "irqchip.h"
 
 #define MAX_ICU_NR		16
@@ -131,7 +124,7 @@ static void icu_unmask_irq(struct irq_data *d)
 	}
 }
 
-static struct irq_chip icu_irq_chip = {
+struct irq_chip icu_irq_chip = {
 	.name		= "icu_irq",
 	.irq_mask	= icu_mask_irq,
 	.irq_mask_ack	= icu_mask_ack_irq,
@@ -250,9 +243,6 @@ void __init icu_init_irq(void)
 	}
 	irq_set_default_host(icu_data[0].domain);
 	set_handle_irq(mmp_handle_irq);
-#ifdef CONFIG_CPU_PXA910
-	icu_irq_chip.irq_set_wake = pxa910_set_wake;
-#endif
 }
 
 /* MMP2 (ARMv7) */
@@ -357,9 +347,6 @@ void __init mmp2_init_icu(void)
 	}
 	irq_set_default_host(icu_data[0].domain);
 	set_handle_irq(mmp2_handle_irq);
-#ifdef CONFIG_CPU_MMP2
-	icu_irq_chip.irq_set_wake = mmp2_set_wake;
-#endif
 }
 
 #ifdef CONFIG_OF
diff --git a/include/linux/irqchip/mmp.h b/include/linux/irqchip/mmp.h
index fb492a5..98558b7 100644
--- a/include/linux/irqchip/mmp.h
+++ b/include/linux/irqchip/mmp.h
@@ -236,4 +236,6 @@
 #define IRQ_BOARD_START			(IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
 #define MMP_NR_IRQS			IRQ_BOARD_START
 
+extern struct irq_chip icu_irq_chip;
+
 #endif /* __ASM_MACH_IRQS_H */
-- 
1.8.1.2



From olof at lixom.net  Mon May 27 22:28:40 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 19:28:40 -0700
Subject: [GIT PULL] Renesas ARM and SH based SoC pinmux fixes for v3.10 #2
In-Reply-To: <1369461157-19256-1-git-send-email-horms+renesas@verge.net.au>
References: <1369461157-19256-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528022840.GA13532@quad.lixom.net>

On Sat, May 25, 2013 at 02:52:36PM +0900, Simon Horman wrote:
> Hi Arnd, Hi Olof,
> 
> The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> 
>   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux-fixes2-for-v3.10

Hi Simon,

For fixes, especially if you have only one per branch, please just
send one pull so we don't get a crazy number of merge changesets in the
history. We don't split them into categories during -rcs.


-Olof


From gnurou at gmail.com  Mon May 27 22:31:22 2013
From: gnurou at gmail.com (Alexandre Courbot)
Date: Tue, 28 May 2013 11:31:22 +0900
Subject: [PATCH v2] video: simplefb: add mode parsing function
In-Reply-To: <CANq1E4Qa6g-zrA6o_u3w6mpVcUk8-ZPPR+edu6EXgpk-kGQULQ@mail.gmail.com>
References: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>
 <CANq1E4Qa6g-zrA6o_u3w6mpVcUk8-ZPPR+edu6EXgpk-kGQULQ@mail.gmail.com>
Message-ID: <CAAVeFuJssMGNi=7gtxHjgaS9s+VTkfBme+T68=Zf7Ech2+hMQw@mail.gmail.com>

Hi David,

On Tue, May 28, 2013 at 3:22 AM, David Herrmann <dh.herrmann at gmail.com> wrote:
> If we apply this patch it will get very hard to support this with a
> KMS driver. So any reason why we cannot use the DRM FOURCC constants
> instead?

I don't see any. Maybe Stephen can confirm.

> The dvbe proposal is available here: (also see the two following patches)
>   http://lkml.indiana.edu/hypermail/linux/kernel/1302.2/00274.html
>
> it provides a simple DRM driver that uses VESA / VBE. I am currently
> trying to rework it to "SimpleDRM" which can support arbitrary
> firmware framebuffers.

Ok. I am personally fine with using FOURCC codes for describing video
modes. Maybe we can just drop this patch if it gets in your way.

Alex.


From olof at lixom.net  Mon May 27 22:31:58 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 19:31:58 -0700
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 3)
In-Reply-To: <20130527185436.GN31290@titan.lakedaemon.net>
References: <20130527185436.GN31290@titan.lakedaemon.net>
Message-ID: <20130528023158.GB13532@quad.lixom.net>

Hi,

On Mon, May 27, 2013 at 02:54:36PM -0400, Jason Cooper wrote:

> Thomas Petazzoni (2):
>       arm: mvebu: fix length of SATA registers area in .dtsi
>       arm: mvebu: fix length of Ethernet registers area in .dtsi

Is this an actual regression in 3.10?

I can understand having to fix this before the static mapping is removed,
but if it's still there for 3.10, then it makes more sense to queue these
fixes for 3.11 (we tend to collect a "fixes-non-critical" that is merged
before any other branches in the next merge window).


-Olof


From olof at lixom.net  Mon May 27 22:45:40 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 19:45:40 -0700
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
 <20130522143204.GE32012@verge.net.au>
 <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
Message-ID: <20130528024540.GC13532@quad.lixom.net>

Hi,

Sorry, a bit behind on email and just discovered this.

On Wed, May 22, 2013 at 07:22:59PM +0200, Guennadi Liakhovetski wrote:

> > > The above didn't work in my tests without this:
> > > 
> > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
> > > b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > index f603c69..4fb0102 100644
> > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > @@ -33,8 +33,10 @@
> > >  	};
> > >  
> > >  	lbsc {
> > > +		compatible = "simple-bus";
> > >  		#address-cells = <1>;
> > >  		#size-cells = <1>;
> > > +		ranges = <0 0 0 0x80000000>;
> > >  
> > >  		ethernet at 8000000 {
> > >  			compatible = "smsc,lan9118", "smsc,lan9115";
> > > 
> > 
> > Could you please post this as a formal patch and indicate
> > if you would like it included as a fix in v3.10 or not?
> 
> Can do that, sure, just thought maybe it would be better to fix the 
> original patch. Besides, I wasn't sure what the correct values for 
> "ranges" are, I just picked up something, that would be sufficient for 
> ethernet. But if more devices are added to it in the future, maybe 
> different ranges values would be needed. I think actually, lbsc should map 
> the 3 BSC areas, so, the correct property would be
> 
> +		ranges = <0 0 0 0x14000000>;
> 
> > Also, I am curious to know what your tests are.
> 
> Just booting with NFS root. I think, anything involving ethernet. Without 
> the "simple-bus" property the lbsc node doesn't get scanned, so, no device 
> is added. Without "ranges" addresses cannot be mapped correctly.

Since it's a flat mapping you can just specify an empty "ranges" property, no
need to actually define contents.

For more info, see http://devicetree.org/Device_Tree_Usage#Ranges_.28Address_Translation.29


-Olof


From inki.dae at samsung.com  Mon May 27 22:49:29 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 28 May 2013 11:49:29 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <51A37A54.1040700@canonical.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <51A37A54.1040700@canonical.com>
Message-ID: <005601ce5b4d$f95e0160$ec1a0420$%dae@samsung.com>



> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
> Sent: Tuesday, May 28, 2013 12:23 AM
> To: Inki Dae
> Cc: 'Daniel Vetter'; 'Rob Clark'; 'linux-fbdev'; 'YoungJun Cho'; 'Kyungmin
> Park'; 'myungjoo.ham'; 'DRI mailing list'; linux-arm-
> kernel at lists.infradead.org; linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> Hey,
> 
> Op 27-05-13 12:38, Inki Dae schreef:
> > Hi all,
> >
> > I have been removed previous branch and added new one with more cleanup.
> > This time, the fence helper doesn't include user side interfaces and
> cache
> > operation relevant codes anymore because not only we are not sure that
> > coupling those two things, synchronizing caches and buffer access
> between
> > CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is
> a
> > good idea yet but also existing codes for user side have problems with
> badly
> > behaved or crashing userspace. So this could be more discussed later.
> >
> > The below is a new branch,
> >
> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/?h=dma-f
> > ence-helper
> >
> > And fence helper codes,
> >
> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/commit/?
> > h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
> >
> > And example codes for device driver,
> >
> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/commit/?
> > h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
> >
> > I think the time is not yet ripe for RFC posting: maybe existing dma
> fence
> > and reservation need more review and addition work. So I'd glad for
> somebody
> > giving other opinions and advices in advance before RFC posting.
> >
> NAK.
> 
> For examples for how to handle locking properly, see Documentation/ww-
> mutex-design.txt in my recent tree.
> I could list what I believe is wrong with your implementation, but real
> problem is that the approach you're taking is wrong.

I just removed ticket stubs to show my approach you guys as simple as
possible, and I just wanted to show that we could use buffer synchronization
mechanism without ticket stubs.

Question, WW-Mutexes could be used for all devices? I guess this has
dependence on x86 gpu: gpu has VRAM and it means different memory domain.
And could you tell my why shared fence should have only eight objects? I
think we could need more than eight objects for read access. Anyway I think
I don't surely understand yet so there might be my missing point.

Thanks,
Inki Dae

> 

> ~Maarten



From 21cnbao at gmail.com  Mon May 27 22:47:38 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 28 May 2013 10:47:38 +0800
Subject: [PATCH v2] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
Message-ID: <1369709258-14529-1-git-send-email-Baohua.Song@csr.com>

From: Binghua Duan <Binghua.Duan at csr.com>

there is an embedded PWRC(power controller) in SiRFprimaII and SiRFatlasVI,
we have an ONKEY button which can generate interrupt to IRQ controller.
in a typical user scenarios, at the runtime, if users touch the key, we put
system to s2ram status.

Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
Signed-off-by: Xianglong Du <Xianglong.Du at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2: cleanup according to Dmitry's comments

 drivers/input/misc/Kconfig         |  10 +++
 drivers/input/misc/Makefile        |   1 +
 drivers/input/misc/sirfsoc-onkey.c | 163 +++++++++++++++++++++++++++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 drivers/input/misc/sirfsoc-onkey.c

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index bb698e1..1d91d1b 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -637,4 +637,14 @@ config INPUT_XEN_KBDDEV_FRONTEND
 	  To compile this driver as a module, choose M here: the
 	  module will be called xen-kbdfront.
 
+config INPUT_SIRFSOC_ONKEY
+	bool "CSR SiRFSoC power on/off/suspend key support"
+	depends on ARCH_SIRF
+	default y
+	help
+	  Say Y here if you want to support for the SiRFSoC power on/off/suspend key
+	  in Linux, after you press the onkey, system will suspend.
+
+	  If unsure, say N.
+
 endif
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index d7fc17f..829de43 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_INPUT_RB532_BUTTON)	+= rb532_button.o
 obj-$(CONFIG_INPUT_RETU_PWRBUTTON)	+= retu-pwrbutton.o
 obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER)	+= rotary_encoder.o
 obj-$(CONFIG_INPUT_SGI_BTNS)		+= sgi_btns.o
+obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)	+= sirfsoc-onkey.o
 obj-$(CONFIG_INPUT_SPARCSPKR)		+= sparcspkr.o
 obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON)	+= twl4030-pwrbutton.o
 obj-$(CONFIG_INPUT_TWL4030_VIBRA)	+= twl4030-vibra.o
diff --git a/drivers/input/misc/sirfsoc-onkey.c b/drivers/input/misc/sirfsoc-onkey.c
new file mode 100644
index 0000000..a4aee61
--- /dev/null
+++ b/drivers/input/misc/sirfsoc-onkey.c
@@ -0,0 +1,163 @@
+/*
+ * Power key driver for SiRF PrimaII
+ *
+ * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/rtc/sirfsoc_rtciobrg.h>
+#include <linux/of.h>
+
+struct sirfsoc_pwrc_drvdata {
+	u32			pwrc_base;
+	struct input_dev	*input;
+};
+
+#define PWRC_ON_KEY_BIT			(1 << 0)
+
+#define PWRC_INT_STATUS			0xc
+#define PWRC_INT_MASK			0x10
+
+static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
+{
+	struct sirfsoc_pwrc_drvdata *pwrcdrv =
+			(struct sirfsoc_pwrc_drvdata *)dev_id;
+	u32 int_status;
+	int_status = sirfsoc_rtc_iobrg_readl(
+			pwrcdrv->pwrc_base + PWRC_INT_STATUS);
+	sirfsoc_rtc_iobrg_writel(int_status & (~PWRC_ON_KEY_BIT),
+			pwrcdrv->pwrc_base + PWRC_INT_STATUS);
+
+	/*
+	 * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
+	 * to queue a SUSPEND APM event
+	 */
+	input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
+	input_sync(pwrcdrv->input);
+
+	/*
+	 * Todo: report KEY_POWER event for Android platforms, Android PowerManager
+	 * will handle the suspend and powerdown/hibernation
+	 */
+
+	return IRQ_HANDLED;
+}
+
+static const struct of_device_id sirfsoc_pwrc_of_match[] = {
+	{ .compatible = "sirf,prima2-pwrc" },
+	{},
+}
+MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
+
+static int sirfsoc_pwrc_probe(struct platform_device *pdev)
+{
+	int ret, irq;
+	struct sirfsoc_pwrc_drvdata *pwrcdrv = NULL;
+	struct device_node *np = pdev->dev.of_node;
+
+	pwrcdrv = devm_kzalloc(&pdev->dev,
+		sizeof(struct sirfsoc_pwrc_drvdata), GFP_KERNEL);
+	if (!pwrcdrv) {
+		dev_info(&pdev->dev, "kzalloc fail!\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * we can't use of_iomap because pwrc is not mapped in memory, the so-called base
+	 * address is only offset in rtciobrg
+	 */
+	ret = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to find base address of pwrc node in dtb\n");
+		return ret;
+	}
+
+	pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
+	if (!pwrcdrv->input)
+		return -ENOMEM;
+
+	pwrcdrv->input->name = "sirfsoc pwrckey";
+	pwrcdrv->input->phys = "pwrc/input0";
+
+	platform_set_drvdata(pdev, pwrcdrv);
+
+	irq = platform_get_irq(pdev, 0);
+	ret = devm_request_irq(&pdev->dev, irq,
+			sirfsoc_pwrc_isr, IRQF_SHARED,
+			"sirfsoc_pwrc_int", pwrcdrv);
+	if (ret) {
+		dev_err(&pdev->dev, "pwrc: Unable to claim irq %d; error %d\n",
+			irq, ret);
+		return ret;
+	}
+
+	sirfsoc_rtc_iobrg_writel(
+		sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK)
+		| PWRC_ON_KEY_BIT, pwrcdrv->pwrc_base + PWRC_INT_MASK);
+
+	pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
+	set_bit(KEY_POWER, pwrcdrv->input->keybit);
+
+	ret = input_register_device(pwrcdrv->input);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"pwrc: Unable to register input device,error: %d\n",
+			ret);
+		return ret;
+	}
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	return 0;
+}
+
+static int sirfsoc_pwrc_remove(struct platform_device *pdev)
+{
+	device_init_wakeup(&pdev->dev, 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int pwrc_resume(struct device *dev)
+{
+	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
+	/*
+	 * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
+	 * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
+	 */
+	sirfsoc_rtc_iobrg_writel(
+		sirfsoc_rtc_iobrg_readl(
+		pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
+		pwrcdrv->pwrc_base + PWRC_INT_MASK);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(sirfsoc_pwrc_pm_ops, NULL, pwrc_resume);
+
+static struct platform_driver sirfsoc_pwrc_driver = {
+	.probe		= sirfsoc_pwrc_probe,
+	.remove		= sirfsoc_pwrc_remove,
+	.driver		= {
+		.name	= "sirfsoc-pwrc",
+		.owner	= THIS_MODULE,
+		.pm	= &sirfsoc_pwrc_pm_ops,
+		.of_match_table = of_match_ptr(sirfsoc_pwrc_of_match),
+	}
+};
+
+module_platform_driver(sirfsoc_pwrc_driver);
+
+MODULE_LICENSE("GPLv2");
+MODULE_AUTHOR("Binghua Duan <Binghua.Duan at csr.com>, Xianglong Du <Xianglong.Du at csr.com>");
+MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
+MODULE_ALIAS("platform:sirfsoc-pwrc");
-- 
1.8.2.3



From olof at lixom.net  Mon May 27 22:52:57 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 19:52:57 -0700
Subject: [GIT PULL] Samsung fixes-3 for v3.10
In-Reply-To: <519FF6DB.5040002@samsung.com>
References: <519FF6DB.5040002@samsung.com>
Message-ID: <CAOesGMjEESQ1a6V3AC2RqGQTwk++Zq2FwZVQT0C=ToP1gTwR3w@mail.gmail.com>

On Fri, May 24, 2013 at 4:25 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
>
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
>
> are available in the git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> tags/samsung-fixes-3
>
> for you to fetch changes up to 15f504f0c2038b9a0f1569c9ce34def61f0c65be:
>
>   ARM: SAMSUNG: Add names to fimd0 IRQ resources (2013-05-25 06:49:43 +0900)
>
> ----------------------------------------------------------------
> Fixes following for v3.10
> - to get usb2 working on the Chromebook with adding the
>   usb phy node for usb2 on exynos5250
> - supporting exynos4210 rev0 SoC
> - exynos5440 restart applying only to powered-on domains
> - drm-exynos probe failure with adding resource names to
>   fimd0 platform device

Pulled, thanks.

-Olof


From Baohua.Song at csr.com  Mon May 27 23:06:26 2013
From: Baohua.Song at csr.com (Barry Song)
Date: Tue, 28 May 2013 11:06:26 +0800
Subject: [PATCH] arm: prima2: move to generic reset controller driver framework
Message-ID: <1369710386-23303-1-git-send-email-Baohua.Song@csr.com>

this moves to generic IP module reset framework, and make other drivers
use common device_reset() API.

Cc: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/boot/dts/atlas6.dtsi |  3 +-
 arch/arm/boot/dts/marco.dtsi  |  3 +-
 arch/arm/boot/dts/prima2.dtsi |  3 +-
 arch/arm/mach-prima2/rstc.c   | 71 ++++++++++++++++++++++++++-----------------
 4 files changed, 49 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 7d1a279..ffe5203 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -56,9 +56,10 @@
 				#clock-cells = <1>;
 			};
 
-			reset-controller at 88010000 {
+			rstc: reset-controller at 88010000 {
 				compatible = "sirf,prima2-rstc";
 				reg = <0x88010000 0x1000>;
+				#reset-cells = <1>;
 			};
 
 			rsc-controller at 88020000 {
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
index 1579c34..0c9647d 100644
--- a/arch/arm/boot/dts/marco.dtsi
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -58,9 +58,10 @@
 			#size-cells = <1>;
 			ranges = <0xc2000000 0xc2000000 0x1000000>;
 
-			reset-controller at c2000000 {
+			rstc: reset-controller at c2000000 {
 				compatible = "sirf,marco-rstc";
 				reg = <0xc2000000 0x10000>;
+				#reset-cells = <1>;
 			};
 		};
 
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..5ecf1f9 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -65,9 +65,10 @@
 				#clock-cells = <1>;
 			};
 
-			reset-controller at 88010000 {
+			rstc: reset-controller at 88010000 {
 				compatible = "sirf,prima2-rstc";
 				reg = <0x88010000 0x1000>;
+				#reset-cells = <1>;
 			};
 
 			rsc-controller at 88020000 {
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..a4d77eb 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,44 +13,24 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reset-controller.h>
+
+#define SIRFSOC_RSTBIT_NUM	64
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
 
-static struct of_device_id rstc_ids[]  = {
-	{ .compatible = "sirf,prima2-rstc" },
-	{ .compatible = "sirf,marco-rstc" },
-	{},
-};
-
-static int __init sirfsoc_of_rstc_init(void)
-{
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, rstc_ids);
-	if (!np)
-		panic("unable to find compatible rstc node in dtb\n");
-
-	sirfsoc_rstc_base = of_iomap(np, 0);
-	if (!sirfsoc_rstc_base)
-		panic("unable to map rstc cpu registers\n");
-
-	of_node_put(np);
-
-	return 0;
-}
-early_initcall(sirfsoc_of_rstc_init);
-
-int sirfsoc_reset_device(struct device *dev)
+static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
+					unsigned long sw_reset_idx)
 {
-	u32 reset_bit;
+	u32 reset_bit = sw_reset_idx;
 
-	if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
+	if (reset_bit >= SIRFSOC_RSTBIT_NUM)
 		return -EINVAL;
 
 	mutex_lock(&rstc_lock);
 
-	if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
+	if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
 		/*
 		 * Writing 1 to this bit resets corresponding block. Writing 0 to this
 		 * bit de-asserts reset signal of the corresponding block.
@@ -80,6 +60,41 @@ int sirfsoc_reset_device(struct device *dev)
 	return 0;
 }
 
+static struct reset_control_ops sirfsoc_rstc_ops = {
+	.reset = sirfsoc_reset_module,
+};
+
+static struct reset_controller_dev sirfsoc_reset_controller = {
+	.ops = &sirfsoc_rstc_ops,
+	.nr_resets = SIRFSOC_RSTBIT_NUM,
+};
+
+static struct of_device_id rstc_ids[]  = {
+	{ .compatible = "sirf,prima2-rstc" },
+	{ .compatible = "sirf,marco-rstc" },
+	{},
+};
+
+static int __init sirfsoc_of_rstc_init(void)
+{
+	struct device_node *np = of_find_matching_node(NULL, rstc_ids);
+	if (!np)
+		goto out;
+
+	sirfsoc_rstc_base = of_iomap(np, 0);
+	if (!sirfsoc_rstc_base)
+		panic("unable to map rstc cpu registers\n");
+
+	sirfsoc_reset_controller.of_node = np;
+
+	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+		reset_controller_register(&sirfsoc_reset_controller);
+
+out:
+	return 0;
+}
+arch_initcall(sirfsoc_of_rstc_init);
+
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
 void sirfsoc_restart(char mode, const char *cmd)
-- 
1.8.2.3



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From nico at fluxnic.net  Mon May 27 23:10:56 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 27 May 2013 23:10:56 -0400 (EDT)
Subject: VDSO for arm 32bit
In-Reply-To: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
Message-ID: <alpine.LFD.2.03.1305272307340.1918@syhkavp.arg>

On Mon, 27 May 2013, Kumar, Ganesh wrote:

> Hi All,
> 
> ? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is
> no support for vdso for arm 32 bit.
> I'm planning to port it to arm 32 bit, is there any work under progress?
> would like to understand why the support for arm 32 bit is not there, any idea?

Please have a look at Documentation/arm/kernel_user_helpers.txt.


Nicolas

From olof at lixom.net  Mon May 27 23:13:20 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:13:20 -0700
Subject: [GIT PULL] ux500 DMA40 device tree migration base
In-Reply-To: <CACRpkdZjr=48_GJxsoYgK7DFUqLs10x4o9yky3MzNR7vh24ogA@mail.gmail.com>
References: <CACRpkdZjr=48_GJxsoYgK7DFUqLs10x4o9yky3MzNR7vh24ogA@mail.gmail.com>
Message-ID: <20130528031320.GD13532@quad.lixom.net>

On Thu, May 23, 2013 at 09:34:22PM +0200, Linus Walleij wrote:
> Hi ARM SoC folks,
> 
> here is a patch set that Lee has been chiseling out recently. I've
> accumulated it in my ux500 tree and piled ACKs on the first 36
> patches of the patch set. Basically that includes ACKs from
> subsystem maintainers Vinod Koul and Herbert Xu for affected
> parts.
> 
> We need to get this into Linux-next to proceed with further
> migration on top of it. All have been circulated on the lists for
> a while.
> 
> Please pull this into an apropriate ARM SoC branch for v3.11!
> 
> If we can get ACKs for the rest of the patches in Lee's set these
> will arrive on top of this base as soon as they are ready.
> 
> Yours,
> Linus Walleij
> 
> The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> 
>   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
> tags/ux500-dma40-for-arm-soc

Thanks, pulled into next/drivers.

I see the conversions have been made the brute-force way instead of keeping
backwards compatibility and cleaning up drivers before removing no longer
needed board code. That should be fine, as long as you don't introduce too
crazy dependencies (and conflicts) in the code you're talking about adding on
top. 


-Olof


From olof at lixom.net  Mon May 27 23:18:26 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:18:26 -0700
Subject: [GIT PULL] Renesas ARM based emev2 SoC updates for v3.11
In-Reply-To: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>
References: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528031826.GE13532@quad.lixom.net>

On Sun, May 26, 2013 at 10:05:22PM +0900, Simon Horman wrote:
> Hi Arnd, Hi Olof,
> 
> The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> 
>   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-emev2-for-v3.11
> 
> for you to fetch changes up to 94a6af856df56ed39bb59ebe17bfa2d10fb333f2:
> 
>   ARM: shmobile: emev2: Remove init_irq declaration in machine description (2013-05-22 21:42:03 +0900)

Hi,

You could have grouped all of the SoC updates into one branch instead of
sending them up SoC by SoC to us. Either way works, just letting you know
there's no need to keep them separate if that's easier.

Also, the changes from Maxime could all have gone into one cleanup branch
together instead of with the SoC code.

Anyway, no harm done, I've pulled this branch (and will pull the others as
well) into our next/soc branch.


Thanks,

-Olof


From olof at lixom.net  Mon May 27 23:29:48 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:29:48 -0700
Subject: [PATCH 04/12] ARM: shmobile: r8a7740: Add DT name to clock list
 for CMT10
In-Reply-To: <1369645193-3595-5-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-5-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528032948.GF13532@quad.lixom.net>

Hi,

On Mon, May 27, 2013 at 05:59:45PM +0900, Simon Horman wrote:
> From: Bastian Hecht <hechtb at gmail.com>
> 
> This adds temporarily the alternative device name to the clock list
> that is used when booting via Device Tree setup.

> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/clock-r8a7740.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
> index 5bd8da0..8fc396a 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7740.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7740.c
> @@ -582,6 +582,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("e6cc0000.sci",		&mstp_clks[MSTP230]),
>  
>  	CLKDEV_DEV_ID("sh_cmt.10",		&mstp_clks[MSTP329]),
> +	CLKDEV_DEV_ID("e6138010.timer",		&mstp_clks[MSTP329]),
>  	CLKDEV_DEV_ID("sh_fsi2",		&mstp_clks[MSTP328]),
>  	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
>  	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
> -- 
> 1.7.10.4
> 

Usually this is instead handled by adding entries to OF_DEV_AUXDATA() to rename
the device in the board file. Would you mind doing that instead?


Thanks,

-Olof


From olof at lixom.net  Mon May 27 23:30:27 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:30:27 -0700
Subject: [PATCH 06/12] ARM: shmobile: r8a7740: Add I2C DT clock names
In-Reply-To: <1369645193-3595-7-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-7-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528033027.GG13532@quad.lixom.net>

Hi,

On Mon, May 27, 2013 at 05:59:47PM +0900, Simon Horman wrote:
> From: Bastian Hecht <hechtb at gmail.com>
> 
> Add clock association for i2c0 and i2c1 for the new DT names.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/clock-r8a7740.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
> index a2a612f..b12c476 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7740.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7740.c
> @@ -551,6 +551,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh_tmu.4",		&mstp_clks[MSTP111]),
>  	CLKDEV_DEV_ID("sh_tmu.5",		&mstp_clks[MSTP111]),
>  	CLKDEV_DEV_ID("i2c-sh_mobile.0",	&mstp_clks[MSTP116]),
> +	CLKDEV_DEV_ID("fff20000.i2c",		&mstp_clks[MSTP116]),
>  	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",	&mstp_clks[MSTP117]),
>  	CLKDEV_DEV_ID("sh_tmu.0",		&mstp_clks[MSTP125]),
>  	CLKDEV_DEV_ID("sh_tmu.1",		&mstp_clks[MSTP125]),
> @@ -585,6 +586,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("e6138010.timer",		&mstp_clks[MSTP329]),
>  	CLKDEV_DEV_ID("sh_fsi2",		&mstp_clks[MSTP328]),
>  	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
> +	CLKDEV_DEV_ID("e6c20000.i2c",		&mstp_clks[MSTP323]),
>  	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
>  	CLKDEV_DEV_ID("sh_mobile_sdhi.0",	&mstp_clks[MSTP314]),
>  	CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
> -- 

Same here w.r.t. OF_DEV_AUXDATA().


-Olof


From olof at lixom.net  Mon May 27 23:36:06 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:36:06 -0700
Subject: [PATCH 07/12] ARM: shmobile: r8a7740: Add OF support to
 initialze the GIC
In-Reply-To: <1369645193-3595-8-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-8-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528033606.GH13532@quad.lixom.net>

Hi,

On Mon, May 27, 2013 at 05:59:48PM +0900, Simon Horman wrote:
> From: Bastian Hecht <hechtb at gmail.com>
> 
> We add a variant to initalize the interrupt controller in case we describe
> the GIC using the Device Tree and not platform data.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/include/mach/r8a7740.h |    1 +
>  arch/arm/mach-shmobile/intc-r8a7740.c         |   24 ++++++++++++++++++------
>  2 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
> index abdc4d4..19c0423 100644
> --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
> +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
> @@ -534,6 +534,7 @@ enum {
>  
>  extern void r8a7740_meram_workaround(void);
>  extern void r8a7740_init_irq(void);
> +extern void r8a7740_init_irq_of(void);
>  extern void r8a7740_map_io(void);
>  extern void r8a7740_add_early_devices(void);
>  extern void r8a7740_add_standard_devices(void);

This is not a comment on this patch per se, but this header file should
probably be directly under the mach directory instead of under include/mach.

In particular, if/when the shmobile platforms get converted to
multiplatform, the header file has to move. And I see that most of these
functions are only used locally in that directory anyway.

It'd be nice to see some of that addressed by 3.12 or so, if you have a chance.


-Olof


From olof at lixom.net  Mon May 27 23:50:19 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:50:19 -0700
Subject: [PATCH 09/12] ARM: shmobile: r8a7740: Add Suspend-To-RAM A3SM
In-Reply-To: <1369645193-3595-10-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-10-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528035019.GI13532@quad.lixom.net>

Hi,

On Mon, May 27, 2013 at 05:59:50PM +0900, Simon Horman wrote:
> From: Bastian Hecht <hechtb at gmail.com>
> 
> We add 2 Suspend to RAM modes:
> - A3SM PLL0 on/off:     Power domain A3SM that contains the ARM core
>                         and the 2nd level cache with either PLL0 on
>                         or off
> 
> As the suspend to memory mechanism we use A3SM PLL off. A3SM PLL on
> is included here too, so CPUIdle can use both power down modes (not
> included in this patch).
> 
> The setup of the SYSC regarding the external IRQs is taken from
> pm-sh7372.c from Magnus Damm.
> 
> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>

Missing S-o-b from you, Simon?

> +	.text
> +ENTRY(v7_cpu_resume)
> +	bl	v7_invalidate_l1
> +	b	cpu_resume
> +ENDPROC(v7_cpu_resume)

This is a global namespace so it'll conflict with i.MX whenever
you multiplatform enable shmobile. Might want to pick a more
unique name.


-Olof


From olof at lixom.net  Mon May 27 23:54:46 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:54:46 -0700
Subject: [PATCH 10/12] ARM: shmobile: r8a7740: Add CPUIdle
In-Reply-To: <51A33D83.905@linaro.org>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-11-git-send-email-horms+renesas@verge.net.au>
 <51A33D83.905@linaro.org>
Message-ID: <20130528035446.GJ13532@quad.lixom.net>

On Mon, May 27, 2013 at 01:03:31PM +0200, Daniel Lezcano wrote:
> On 05/27/2013 10:59 AM, Simon Horman wrote:
> > From: Bastian Hecht <hechtb at gmail.com>
> > 
> > We make use of the r8a7740 Suspend To Ram code to plug together a
> > CPUIdle driver.
> > 
> > Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> > Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> > ---
> 
> Shouldn't it go through Rafael's tree ? Or does the patch contains some
> dependencies on a code only visible in the ARM tree ?

Missing S-o-b from Simon. But this patch clearly builds on the preceding
one in the series, so merging them independently might not make much
sense. Getting an ack from Rafael would be nice though.

I was going to say that it should probably go under drivers/cpuidle as
well, but that just seems silly -- there is practically no code to share
with any other platform in this small driver, AND there's not really
any subsystem-internal data exposed. So it might just make more sense
to keep it under arch/arm instead.

Likewise, looking at the kirkwood and calxeda drivers under drivers/cpuidle,
I'm wondering why we thought it was a good idea to merge them there, besides
getting caught up in the "nothing can live under arch/arm any more" frenzy.


-Olof


From inki.dae at samsung.com  Mon May 27 23:56:57 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 28 May 2013 12:56:57 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
Message-ID: <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>



> -----Original Message-----
> From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
> owner at vger.kernel.org] On Behalf Of Rob Clark
> Sent: Tuesday, May 28, 2013 12:48 AM
> To: Inki Dae
> Cc: Maarten Lankhorst; Daniel Vetter; linux-fbdev; YoungJun Cho; Kyungmin
> Park; myungjoo.ham; DRI mailing list;
linux-arm-kernel at lists.infradead.org;
> linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
> > Hi all,
> >
> > I have been removed previous branch and added new one with more cleanup.
> > This time, the fence helper doesn't include user side interfaces and
> cache
> > operation relevant codes anymore because not only we are not sure that
> > coupling those two things, synchronizing caches and buffer access
> between
> > CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is
> a
> > good idea yet but also existing codes for user side have problems with
> badly
> > behaved or crashing userspace. So this could be more discussed later.
> >
> > The below is a new branch,
> >
> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/?h=dma-f
> > ence-helper
> >
> > And fence helper codes,
> >
> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/commit/?
> > h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
> >
> > And example codes for device driver,
> >
> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/commit/?
> > h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
> >
> > I think the time is not yet ripe for RFC posting: maybe existing dma
> fence
> > and reservation need more review and addition work. So I'd glad for
> somebody
> > giving other opinions and advices in advance before RFC posting.
> 
> thoughts from a *really* quick, pre-coffee, first look:
> * any sort of helper to simplify single-buffer sort of use-cases (v4l)
> probably wouldn't want to bake in assumption that seqno_fence is used.
> * I guess g2d is probably not actually a simple use case, since I
> expect you can submit blits involving multiple buffers :-P

I don't think so. One and more buffers can be used: seqno_fence also has
only one buffer. Actually, we have already applied this approach to most
devices; multimedia, gpu and display controller. And this approach shows
more performance; reduced power consumption against traditional way. And g2d
example is just to show you how to apply my approach to device driver.

> * otherwise, you probably don't want to depend on dmabuf, which is why
> reservation/fence is split out the way it is..  you want to be able to
> use a single reservation/fence mechanism within your driver without
> having to care about which buffers are exported to dmabuf's and which
> are not.  Creating a dmabuf for every GEM bo is too heavyweight.

Right. But I think we should dealt with this separately. Actually, we are
trying to use reservation for gpu pipe line synchronization such as sgx sync
object and this approach is used without dmabuf. In order words, some device
can use only reservation for such pipe line synchronization and at the same
time, fence helper or similar thing with dmabuf for buffer synchronization.

> 
> I'm not entirely sure if reservation/fence could/should be made any
> simpler for multi-buffer users.  Probably the best thing to do is just
> get reservation/fence rolled out in a few drivers and see if some
> common patterns emerge.
> 
> BR,
> -R
> 
> >
> > Thanks,
> > Inki Dae
> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From olof at lixom.net  Mon May 27 23:58:48 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:58:48 -0700
Subject: [GIT PULL] Renesas ARM based r8a7740 SoC updates for v3.11
In-Reply-To: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528035848.GK13532@quad.lixom.net>

Hi Simon,

On Mon, May 27, 2013 at 05:59:41PM +0900, Simon Horman wrote:
> Hi Arnd, Hi Olof,
> 
> The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> 
>   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a7740-for-v3.11
> 
> for you to fetch changes up to 0a9e1c1eef2b050a16685952ce20575348b94d5c:
> 
>   ARM: shmobile: clock-r8a7740: add TPU PWM support (2013-05-27 17:45:27 +0900)
> 
> ----------------------------------------------------------------
> Renesas ARM based r8a7740 SoC updates for v3.11
> 
> * Clean-ups from Kuninori Morimoto, Magnus Damm and Laurent Pinchart.
> * Extended clock coverage by Bastian Hecht.
> * Support for initialising GIC from OF by Bastian Hecht.
> * Support for reference DT initialisation by Bastian Hecht.
>   This is used in conjunction with other changes initialise
>   the Armadillo 800 eva board in DT as much as possible.
> * Suspend to RAM and CPUIdle support by Bastian Hecht
> * Build fix for fallout by Arnd Bergmann from suspend to RAM change.

So, looking at this branch, I think you need to reorganize your patches a bit.
You seem to have fallen back to the case of only sorting patches by what
Renesas SoC they are for, while they are clearly of different kinds such that
we would prefer to see them sorted differently for arm-soc.

For example, the fix from Arnd should go in a shared shmobile fixes branch,
ideally. Some of the DT initialization should maybe go in a separate
(shmobile-shared) DT branch. Clock, suspend/resume and other patches can go in
a shared SoC branch across all of shmobile though.

Care to respin? I had a handful of comments on the patches as well, and I'll
continue to look at some of the other ones.

Since you'll have to respin, we might as well see the reshuffling into shared
shmobile branches, so I'll drop the three merges I had already done of
SoC-specific branches. I'll follow up on the ones I claimed to have merged.
None had been pushed out anyway.


Regards,

-Olof


From olof at lixom.net  Mon May 27 23:59:43 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 20:59:43 -0700
Subject: [GIT PULL] Renesas ARM based emev2 SoC updates for v3.11
In-Reply-To: <20130528031826.GE13532@quad.lixom.net>
References: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>
 <20130528031826.GE13532@quad.lixom.net>
Message-ID: <CAOesGMi+LYx3TUyVgiVajr-mp8q4fNdj6LtK1bYN50stn1AZpw@mail.gmail.com>

Hi,


On Mon, May 27, 2013 at 8:18 PM, Olof Johansson <olof at lixom.net> wrote:
> On Sun, May 26, 2013 at 10:05:22PM +0900, Simon Horman wrote:
>> Hi Arnd, Hi Olof,
>>
>> The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
>>
>>   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
>>
>> are available in the git repository at:
>>
>>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-emev2-for-v3.11
>>
>> for you to fetch changes up to 94a6af856df56ed39bb59ebe17bfa2d10fb333f2:
>>
>>   ARM: shmobile: emev2: Remove init_irq declaration in machine description (2013-05-22 21:42:03 +0900)
>
> Hi,
>
> You could have grouped all of the SoC updates into one branch instead of
> sending them up SoC by SoC to us. Either way works, just letting you know
> there's no need to keep them separate if that's easier.
>
> Also, the changes from Maxime could all have gone into one cleanup branch
> together instead of with the SoC code.
>
> Anyway, no harm done, I've pulled this branch (and will pull the others as
> well) into our next/soc branch.

Based on the comments on the r8a7740 pull request, I've held off
merging this after all.


-Olof


From olof at lixom.net  Tue May 28 00:00:43 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 21:00:43 -0700
Subject: [PATCH 2/2] ARM: shmobile: r8A7779: fix Ether device name
In-Reply-To: <1369645206-3682-3-git-send-email-horms+renesas@verge.net.au>
References: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
 <1369645206-3682-3-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528040043.GL13532@quad.lixom.net>

Hi,


On Mon, May 27, 2013 at 06:00:06PM +0900, Simon Horman wrote:
> From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> 
> While recasting the commit "ARM: shmobile: R8A7779: add Ether support", I made a
> typo in the platform device's name: used underscore instead of hyphen.

Minor nit: if this has been merged, then including the SHA is useful too.


-Olof


From olof at lixom.net  Tue May 28 00:02:43 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 21:02:43 -0700
Subject: [PATCH 1/8] ARM: shmobile: sh73a0 pinmux platform device cleanup
In-Reply-To: <51A36A02.9050200@cogentembedded.com>
References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au>
 <1369645252-3847-2-git-send-email-horms+renesas@verge.net.au>
 <51A36A02.9050200@cogentembedded.com>
Message-ID: <20130528040243.GM13532@quad.lixom.net>

On Mon, May 27, 2013 at 06:13:22PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 27-05-2013 13:00, Simon Horman wrote:
> 
> >From: Magnus Damm <damm at opensource.se>
> 
> >Use DEFINE_RES_MEM() and platform_device_register_simple()
> >to save a couple of lines of code.
> 
> >Signed-off-by: Magnus Damm <damm at opensource.se>
> >Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> >Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >---
> >  arch/arm/mach-shmobile/setup-sh73a0.c |   25 ++++++-------------------
> >  1 file changed, 6 insertions(+), 19 deletions(-)
> 
> >diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
> >index fdf3894..f8f4261 100644
> >--- a/arch/arm/mach-shmobile/setup-sh73a0.c
> >+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
> >@@ -61,29 +61,16 @@ void __init sh73a0_map_io(void)
> [...]
> >+/* PFC */
> >+static const struct resource pfc_resources[] = {
> 
>    Should have been annotated as __initdata... too late, need
> another patch.

See comments on other patches/pull requests, I think there's time to revisit
this. I.e. I'll hold off on pulling this based on the other feedback.


-Olof


From inki.dae at samsung.com  Tue May 28 00:04:33 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 28 May 2013 13:04:33 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAKMK7uG1T-w=rVfORzdSk9LWN_aXqqCiG87UdhjutfbS=rpzbg@mail.gmail.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <CAKMK7uG1T-w=rVfORzdSk9LWN_aXqqCiG87UdhjutfbS=rpzbg@mail.gmail.com>
Message-ID: <005801ce5b58$76008bc0$6201a340$%dae@samsung.com>



> -----Original Message-----
> From: daniel.vetter at ffwll.ch [mailto:daniel.vetter at ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Tuesday, May 28, 2013 1:02 AM
> To: Rob Clark
> Cc: Inki Dae; Maarten Lankhorst; linux-fbdev; YoungJun Cho; Kyungmin Park;
> myungjoo.ham; DRI mailing list; linux-arm-kernel at lists.infradead.org;
> linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Mon, May 27, 2013 at 5:47 PM, Rob Clark <robdclark at gmail.com> wrote:
> > On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
> >> Hi all,
> >>
> >> I have been removed previous branch and added new one with more
cleanup.
> >> This time, the fence helper doesn't include user side interfaces and
> cache
> >> operation relevant codes anymore because not only we are not sure that
> >> coupling those two things, synchronizing caches and buffer access
> between
> >> CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side
> is a
> >> good idea yet but also existing codes for user side have problems with
> badly
> >> behaved or crashing userspace. So this could be more discussed later.
> >>
> >> The below is a new branch,
> >>
> >> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/?h=dma-f
> >> ence-helper
> >>
> >> And fence helper codes,
> >>
> >> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/commit/?
> >> h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
> >>
> >> And example codes for device driver,
> >>
> >> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> exynos.git/commit/?
> >> h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
> >>
> >> I think the time is not yet ripe for RFC posting: maybe existing dma
> fence
> >> and reservation need more review and addition work. So I'd glad for
> somebody
> >> giving other opinions and advices in advance before RFC posting.
> >
> > thoughts from a *really* quick, pre-coffee, first look:
> > * any sort of helper to simplify single-buffer sort of use-cases (v4l)
> > probably wouldn't want to bake in assumption that seqno_fence is used.
> 
> Yeah, which is why Maarten&I discussed ideas already for what needs to
> be improved in the current dma-buf interface code to make this Just
> Work. At least as long as a driver doesn't want to add new fences,
> which would be especially useful for all kinds of gpu access.
> 
> > * I guess g2d is probably not actually a simple use case, since I
> > expect you can submit blits involving multiple buffers :-P
> 
> Yeah, on a quick read the current fence helper code seems to be a bit
> limited in scope.
> 
> > * otherwise, you probably don't want to depend on dmabuf, which is why
> > reservation/fence is split out the way it is..  you want to be able to
> > use a single reservation/fence mechanism within your driver without
> > having to care about which buffers are exported to dmabuf's and which
> > are not.  Creating a dmabuf for every GEM bo is too heavyweight.
> 
> That's pretty much the reason that reservations are free-standing from
> dma_bufs. The idea is to embed them into the gem/ttm/v4l buffer
> object. Maarten also has some helpers to keep track of multi-buffer
> ww_mutex locking and fence attaching in his reservation helpers, but I
> think we should wait with those until we have drivers using them.
> 
> For now I think the priority should be to get the basic stuff in and
> ttm as the first user established. Then we can go nuts later on.
> 
> > I'm not entirely sure if reservation/fence could/should be made any
> > simpler for multi-buffer users.  Probably the best thing to do is just
> > get reservation/fence rolled out in a few drivers and see if some
> > common patterns emerge.
> 
> I think we can make the 1 buffer per dma op (i.e. 1:1
> dma_buf->reservation : fence mapping) work fairly simple in dma_buf
> with maybe a dma_buf_attachment_start_dma/end_dma helpers. But there's
> also still the open that currently there's no way to flush cpu caches
> for dma access without unmapping the attachement (or resorting to


That was what I tried adding user interfaces to dmabuf: coupling
synchronizing caches and buffer access between CPU and CPU, CPU and DMA, and
DMA and DMA with fences in kernel side. We need something to do between
mapping and unmapping attachment.

> trick which might not work), so we have a few gaping holes in the
> interface already anyway.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



From olof at lixom.net  Tue May 28 00:07:29 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 21:07:29 -0700
Subject: [PATCH 2/9] ARM: shmobile: add GPIO IRQ macro
In-Reply-To: <1369648773-7941-3-git-send-email-horms+renesas@verge.net.au>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
 <1369648773-7941-3-git-send-email-horms+renesas@verge.net.au>
Message-ID: <20130528040729.GN13532@quad.lixom.net>

On Mon, May 27, 2013 at 06:59:26PM +0900, Simon Horman wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> 
> R-Car series gpio_rcar driver can control GPIO IRQ today.
> It needs base IRQ number for gpio_rcar_config :: .irq_base
> This patch adds macro for GPIO IRQ.
> This patch was tested on Bock-W board
> 
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/include/mach/irqs.h |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
> index b2074e2..d241bfd 100644
> --- a/arch/arm/mach-shmobile/include/mach/irqs.h
> +++ b/arch/arm/mach-shmobile/include/mach/irqs.h
> @@ -16,4 +16,9 @@
>  #define IRQPIN_BASE		2000
>  #define irq_pin(nr)		((nr) + IRQPIN_BASE)
>  
> +/* GPIO IRQ */
> +#define _GPIO_IRQ_BASE		2500
> +#define GPIO_IRQ_BASE(x)	(_GPIO_IRQ_BASE + (32 * x))
> +#define GPIO_IRQ(x, y)		(_GPIO_IRQ_BASE + (32 * x) + y)
> +
>  #endif /* __ASM_MACH_IRQS_H */

Hmm. It'd be real nice to see some effort on moving this over to sparse
irq instead. That'll be needed for full device tree conversion anyway. And
with that, the static irq bases will be gone, so drivers and some of
the platform code will need to be adjusted accordingly.


-Olof


From swarren at wwwdotorg.org  Tue May 28 00:13:09 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 27 May 2013 22:13:09 -0600
Subject: [PATCH v2] video: simplefb: add mode parsing function
In-Reply-To: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>
References: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>
Message-ID: <51A42ED5.2060104@wwwdotorg.org>

On 05/26/2013 09:53 PM, Alexandre Courbot wrote:
> The naming scheme of simplefb's mode is precise enough to allow building
> the mode structure from it instead of using a static list of modes. This
> patch introduces a function that does this. In case exotic modes that
> cannot be represented from their name alone are needed, the static list
> of modes is still available as a backup.
> 
> It also changes the order in which colors are declared from MSB first to
> the more standard LSB first.
> 
> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
> ---
> Changes from v1:
> - amended documentation following Stephen's suggestion
> - allow parsing of bitfields larger than 9 bits
> - made it clear that the parsing order of bits is changed with respect
>   to the original patch
> 
> Andrew, since this patch introduces a (small) change in the DT bindings,
> could we try to merge it during the -rc cycle so we don't have to come
> with a more complex solution in the future?

So, I think we shouldn't change the DT binding at all now. The original
driver is now merged for 3.10, and I think it's far too late to take
code that implements new features for 3.10. This means that we couldn't
merge this patch until 3.11. However, by then, we shouldn't be changing
the DT binding in incompatible ways. Olof has already published some
U-Boot binaries that use the current binding, and on IRC indicated he'd
prefer not to change the binding because of that.

As such, we should either:

a) Just add new entries into the format array that already exists in the
driver. Given David's response, this might be simplest.

b) Extend the DT binding in a 100% backwards-compatible way, which would
mean defaulting the bit-order to match the existing 1 format, and adding
a new Boolean property to indicate that the format string is specified
in the other order.


From olof at lixom.net  Tue May 28 00:22:03 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 21:22:03 -0700
Subject: [GIT PULL] Nomadik clocks from device tree
In-Reply-To: <CACRpkdaKtxKS0=1UOKJPQWKShRm2nHsUWSK5M+qSR6duXfGrxw@mail.gmail.com>
References: <CACRpkdY8xqi04cf-SJ69QvHr8qB6itqvgxMyNk+=Xrtz2FGVaA@mail.gmail.com>
 <CACRpkdaKtxKS0=1UOKJPQWKShRm2nHsUWSK5M+qSR6duXfGrxw@mail.gmail.com>
Message-ID: <20130528042203.GO13532@quad.lixom.net>

On Sun, May 26, 2013 at 10:32:45PM +0200, Linus Walleij wrote:
> Hi ARM SoC people,
> 
> I have accumulated more Nomadik patches so I'm reiterating this
> pull request with two new patches on top.
> 
> Please pull them in for v3.11!

Hi,

I get a merge conflict on this branch with "ARM: nomadik: fix IRQ
assignment for SMC ethernet" from 3.10-rc2.  Fixed it up.

Also:

> Rabin Vincent (1):
>       clocksource: nomadik-mtu: support of probe

Hmm, you're not the first one I've caught having missed to add S-o-b
lines on patches today. Please pay attention to it in the future.

Merged into next/dt for 3.11.


-Olof


From marex at denx.de  Tue May 28 00:56:27 2013
From: marex at denx.de (Marek Vasut)
Date: Tue, 28 May 2013 06:56:27 +0200
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <20130528014348.GA19608@S2101-09.ap.freescale.net>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <CAOMZO5DRuKrECnYDtZ0wOK6_vpW95Cwc3xf7LT+VT_B7eV3gug@mail.gmail.com>
 <20130528014348.GA19608@S2101-09.ap.freescale.net>
Message-ID: <201305280656.27472.marex@denx.de>

Dear Shawn Guo,

> On Mon, May 27, 2013 at 09:52:21PM -0300, Fabio Estevam wrote:
> > Hi Shawn,
> > 
> > On Mon, May 13, 2013 at 11:31 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > > Have you tested it against v3.10-rc1?  The issue is still there in my
> > > testing.
> > 
> > I am not able to see the issue on 3.10-rc2.
> 
> My imx/dt branch is currently basing on v3.10-rc1, and I do not care if
> it works on v3.10-rc2.  I have tested this patch enough on different
> bases, and I'm not going to test it again and again to find a base which
> happens to work.  I do not feel comfortable to merge this patch if it
> only works on particular base.  Who knows if it will break again with
> another random patches merged in.  There is some issue, and we need to
> find the root cause of it instead of ignoring it by finding some random
> base which hides it.
> 
> > What are the exact steps to trigger the problem? Do you see it
> > consistently?
> 
> Before I answer your questions, can I ask if you have tried to reproduce
> it on v3.10-rc1?

What is the problem you observe?

Best regards,
Marek Vasut


From gnurou at gmail.com  Tue May 28 00:57:51 2013
From: gnurou at gmail.com (Alexandre Courbot)
Date: Tue, 28 May 2013 13:57:51 +0900
Subject: [PATCH v2] video: simplefb: add mode parsing function
In-Reply-To: <51A42ED5.2060104@wwwdotorg.org>
References: <1369626821-28494-1-git-send-email-acourbot@nvidia.com>
 <51A42ED5.2060104@wwwdotorg.org>
Message-ID: <CAAVeFuLYe6xuzV4Y_r8GXoPWd8n3fn=jyp06hRTJVE-t1pf9eg@mail.gmail.com>

On Tue, May 28, 2013 at 1:13 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 05/26/2013 09:53 PM, Alexandre Courbot wrote:
>> The naming scheme of simplefb's mode is precise enough to allow building
>> the mode structure from it instead of using a static list of modes. This
>> patch introduces a function that does this. In case exotic modes that
>> cannot be represented from their name alone are needed, the static list
>> of modes is still available as a backup.
>>
>> It also changes the order in which colors are declared from MSB first to
>> the more standard LSB first.
>>
>> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
>> ---
>> Changes from v1:
>> - amended documentation following Stephen's suggestion
>> - allow parsing of bitfields larger than 9 bits
>> - made it clear that the parsing order of bits is changed with respect
>>   to the original patch
>>
>> Andrew, since this patch introduces a (small) change in the DT bindings,
>> could we try to merge it during the -rc cycle so we don't have to come
>> with a more complex solution in the future?
>
> So, I think we shouldn't change the DT binding at all now. The original
> driver is now merged for 3.10, and I think it's far too late to take
> code that implements new features for 3.10. This means that we couldn't
> merge this patch until 3.11. However, by then, we shouldn't be changing
> the DT binding in incompatible ways. Olof has already published some
> U-Boot binaries that use the current binding, and on IRC indicated he'd
> prefer not to change the binding because of that.
>
> As such, we should either:
>
> a) Just add new entries into the format array that already exists in the
> driver. Given David's response, this might be simplest.
>
> b) Extend the DT binding in a 100% backwards-compatible way, which would
> mean defaulting the bit-order to match the existing 1 format, and adding
> a new Boolean property to indicate that the format string is specified
> in the other order.

a) is definitely simpler, so let's do that and drop this patch. Sorry
about the noise.

Alex.


From kishon at ti.com  Tue May 28 01:18:02 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Tue, 28 May 2013 10:48:02 +0530
Subject: [RFC PATCH 1/4] arm: omap: Add phy binding info for musb in plat
 data
In-Reply-To: <1368796954-3499-1-git-send-email-kishon@ti.com>
References: <1368796954-3499-1-git-send-email-kishon@ti.com>
Message-ID: <51A43E0A.8090201@ti.com>

Hi Tony,

On Friday 17 May 2013 06:52 PM, Kishon Vijay Abraham I wrote:
> In order for controllers to get PHY in case of non dt boot, the phy
> binding information (phy label) should be added in the platform
> data of the controller.

This series would be needed to get MUSB working in OMAP3 boards for 
non-dt boot case. Do you think this is good enough to go in this rc cycle?

Thanks
Kishon


From horms at verge.net.au  Tue May 28 01:27:44 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 May 2013 14:27:44 +0900
Subject: [GIT PULL] Renesas ARM based emev2 SoC updates for v3.11
In-Reply-To: <20130528031826.GE13532@quad.lixom.net>
References: <1369573523-10980-1-git-send-email-horms+renesas@verge.net.au>
 <20130528031826.GE13532@quad.lixom.net>
Message-ID: <20130528052744.GA25005@verge.net.au>

On Mon, May 27, 2013 at 08:18:26PM -0700, Olof Johansson wrote:
> On Sun, May 26, 2013 at 10:05:22PM +0900, Simon Horman wrote:
> > Hi Arnd, Hi Olof,
> > 
> > The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> > 
> >   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-emev2-for-v3.11
> > 
> > for you to fetch changes up to 94a6af856df56ed39bb59ebe17bfa2d10fb333f2:
> > 
> >   ARM: shmobile: emev2: Remove init_irq declaration in machine description (2013-05-22 21:42:03 +0900)
> 
> Hi,
> 
> You could have grouped all of the SoC updates into one branch instead of
> sending them up SoC by SoC to us. Either way works, just letting you know
> there's no need to keep them separate if that's easier.

Thanks, I think it would have been easier to merge each of the soc-branches
into a single branch and send a single request. I will do so in future.

> Also, the changes from Maxime could all have gone into one cleanup branch
> together instead of with the SoC code.

Sorry, I missed that somehow.

> Anyway, no harm done, I've pulled this branch (and will pull the others as
> well) into our next/soc branch.

Thanks!


From horms at verge.net.au  Tue May 28 01:29:00 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 May 2013 14:29:00 +0900
Subject: [PATCH 09/12] ARM: shmobile: r8a7740: Add Suspend-To-RAM A3SM
In-Reply-To: <20130528035019.GI13532@quad.lixom.net>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-10-git-send-email-horms+renesas@verge.net.au>
 <20130528035019.GI13532@quad.lixom.net>
Message-ID: <20130528052900.GB25005@verge.net.au>

On Mon, May 27, 2013 at 08:50:19PM -0700, Olof Johansson wrote:
> Hi,
> 
> On Mon, May 27, 2013 at 05:59:50PM +0900, Simon Horman wrote:
> > From: Bastian Hecht <hechtb at gmail.com>
> > 
> > We add 2 Suspend to RAM modes:
> > - A3SM PLL0 on/off:     Power domain A3SM that contains the ARM core
> >                         and the 2nd level cache with either PLL0 on
> >                         or off
> > 
> > As the suspend to memory mechanism we use A3SM PLL off. A3SM PLL on
> > is included here too, so CPUIdle can use both power down modes (not
> > included in this patch).
> > 
> > The setup of the SYSC regarding the external IRQs is taken from
> > pm-sh7372.c from Magnus Damm.
> > 
> > Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> 
> Missing S-o-b from you, Simon?

Oops sorry about that.

> > +	.text
> > +ENTRY(v7_cpu_resume)
> > +	bl	v7_invalidate_l1
> > +	b	cpu_resume
> > +ENDPROC(v7_cpu_resume)
> 
> This is a global namespace so it'll conflict with i.MX whenever
> you multiplatform enable shmobile. Might want to pick a more
> unique name.

Bastian, could you suggest an alternate name?


From horms at verge.net.au  Tue May 28 01:29:44 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 May 2013 14:29:44 +0900
Subject: [PATCH 04/12] ARM: shmobile: r8a7740: Add DT name to clock list
 for CMT10
In-Reply-To: <20130528032948.GF13532@quad.lixom.net>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-5-git-send-email-horms+renesas@verge.net.au>
 <20130528032948.GF13532@quad.lixom.net>
Message-ID: <20130528052944.GC25005@verge.net.au>

On Mon, May 27, 2013 at 08:29:48PM -0700, Olof Johansson wrote:
> Hi,
> 
> On Mon, May 27, 2013 at 05:59:45PM +0900, Simon Horman wrote:
> > From: Bastian Hecht <hechtb at gmail.com>
> > 
> > This adds temporarily the alternative device name to the clock list
> > that is used when booting via Device Tree setup.
> 
> > 
> > Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > ---
> >  arch/arm/mach-shmobile/clock-r8a7740.c |    1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
> > index 5bd8da0..8fc396a 100644
> > --- a/arch/arm/mach-shmobile/clock-r8a7740.c
> > +++ b/arch/arm/mach-shmobile/clock-r8a7740.c
> > @@ -582,6 +582,7 @@ static struct clk_lookup lookups[] = {
> >  	CLKDEV_DEV_ID("e6cc0000.sci",		&mstp_clks[MSTP230]),
> >  
> >  	CLKDEV_DEV_ID("sh_cmt.10",		&mstp_clks[MSTP329]),
> > +	CLKDEV_DEV_ID("e6138010.timer",		&mstp_clks[MSTP329]),
> >  	CLKDEV_DEV_ID("sh_fsi2",		&mstp_clks[MSTP328]),
> >  	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
> >  	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
> > -- 
> > 1.7.10.4
> > 
> 
> Usually this is instead handled by adding entries to OF_DEV_AUXDATA() to
> rename the device in the board file. Would you mind doing that instead?

Magnus has indicated in the past that he prefers this method over
using OF_DEV_AUXDATA() and the above is consistent with other
shmobile code.


From horms at verge.net.au  Tue May 28 01:33:08 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 May 2013 14:33:08 +0900
Subject: [GIT PULL] Renesas ARM based r8a7740 SoC updates for v3.11
In-Reply-To: <20130528035848.GK13532@quad.lixom.net>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <20130528035848.GK13532@quad.lixom.net>
Message-ID: <20130528053308.GD25005@verge.net.au>

On Mon, May 27, 2013 at 08:58:48PM -0700, Olof Johansson wrote:
> Hi Simon,
> 
> On Mon, May 27, 2013 at 05:59:41PM +0900, Simon Horman wrote:
> > Hi Arnd, Hi Olof,
> > 
> > The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> > 
> >   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a7740-for-v3.11
> > 
> > for you to fetch changes up to 0a9e1c1eef2b050a16685952ce20575348b94d5c:
> > 
> >   ARM: shmobile: clock-r8a7740: add TPU PWM support (2013-05-27 17:45:27 +0900)
> > 
> > ----------------------------------------------------------------
> > Renesas ARM based r8a7740 SoC updates for v3.11
> > 
> > * Clean-ups from Kuninori Morimoto, Magnus Damm and Laurent Pinchart.
> > * Extended clock coverage by Bastian Hecht.
> > * Support for initialising GIC from OF by Bastian Hecht.
> > * Support for reference DT initialisation by Bastian Hecht.
> >   This is used in conjunction with other changes initialise
> >   the Armadillo 800 eva board in DT as much as possible.
> > * Suspend to RAM and CPUIdle support by Bastian Hecht
> > * Build fix for fallout by Arnd Bergmann from suspend to RAM change.
> 
> So, looking at this branch, I think you need to reorganize your patches a bit.
> You seem to have fallen back to the case of only sorting patches by what
> Renesas SoC they are for, while they are clearly of different kinds such that
> we would prefer to see them sorted differently for arm-soc.
> 
> For example, the fix from Arnd should go in a shared shmobile fixes branch,
> ideally. Some of the DT initialization should maybe go in a separate
> (shmobile-shared) DT branch. Clock, suspend/resume and other patches can go in
> a shared SoC branch across all of shmobile though.
> 
> Care to respin? I had a handful of comments on the patches as well, and I'll
> continue to look at some of the other ones.
> 
> Since you'll have to respin, we might as well see the reshuffling into shared
> shmobile branches, so I'll drop the three merges I had already done of
> SoC-specific branches. I'll follow up on the ones I claimed to have merged.
> None had been pushed out anyway.

Sure, I will re-spin and try to re-arange my branches as you describe above.


From horms at verge.net.au  Tue May 28 01:37:01 2013
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 May 2013 14:37:01 +0900
Subject: [GIT PULL] Renesas ARM and SH based SoC pinmux fixes for v3.10 #2
In-Reply-To: <20130528022840.GA13532@quad.lixom.net>
References: <1369461157-19256-1-git-send-email-horms+renesas@verge.net.au>
 <20130528022840.GA13532@quad.lixom.net>
Message-ID: <20130528053701.GE25005@verge.net.au>

On Mon, May 27, 2013 at 07:28:40PM -0700, Olof Johansson wrote:
> On Sat, May 25, 2013 at 02:52:36PM +0900, Simon Horman wrote:
> > Hi Arnd, Hi Olof,
> > 
> > The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> > 
> >   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux-fixes2-for-v3.10
> 
> Hi Simon,
> 
> For fixes, especially if you have only one per branch, please just
> send one pull so we don't get a crazy number of merge changesets in the
> history. We don't split them into categories during -rcs.

Understood. I'll just use a fixes branch from now on.


From olof at lixom.net  Tue May 28 01:47:01 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 22:47:01 -0700
Subject: [GIT PULL] at91: cleanup (pinctrl macros, defconfigs) for 3.11 #1
In-Reply-To: <519F9116.8060109@atmel.com>
References: <1368799336-25226-1-git-send-email-nicolas.ferre@atmel.com>
 <519F9116.8060109@atmel.com>
Message-ID: <20130528054701.GB18476@quad.lixom.net>

On Fri, May 24, 2013 at 06:11:02PM +0200, Nicolas Ferre wrote:
> On 17/05/2013 16:02, Nicolas Ferre :
> >Arnd, Olof,
> >
> >Here is the first AT91 cleanup pull-request for 3.11. I is dominated by a big
> >update of DT files because of the move to macros in pinctrl. As we plan to
> >make this "cleanup" series the base of all our work on AT91 for 3.11, we would
> >like to see it appearing early in arm-soc and linux-next: this is why we send
> >it to you right now.
> >
> >We have colected the Acked-by from Linus Walleij and we all think that it makes
> >sense to merge this material through arm-soc tree:
> >- is touches nearly nothing of pinctrl actual code (a header file)
> >- all dtsi/dts modifications for 3.11 will need this as a codebase for avoiding
> >   merging nightmare
> >
> >I hope that it is okay with you.
> >
> >Thanks, best regards,
> >
> >The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> >
> >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> >
> >are available in the git repository at:
> >
> >   git://github.com/at91linux/linux-at91.git tags/at91-cleanup
> 
> Arnd, Olof,
> 
> After having sent the second "fixes" pull-request to you, I want to
> warn you about merging conflicts concerning this "cleanup"
> pull-request for 3.11.
> 
> 2 merging conflicts are appearing when placing the "cleanup" branch
> on top of the "fixes" material contained today in at91-fixes tag.
> To address this, I have pushed a resolution branch on our usual git tree:
> 
> git://github.com/at91linux/linux-at91.git   at91-3.11-cleanup1+resolved
> 
> In case of any question, please let me know. If you want me to
> rebase the original tag that I've sent you, I can do it as well.

Hi,

Thanks, not a big deal for us to resolve so that's ok.

Pulled in the branch. Some comments below:


> >----------------------------------------------------------------
> >Big update with pinctrl by use of macros and
> >header files. Increases readability and avoid
> >typos.
> >Update of AT91 defconfigs and merge of defconfigs for
> >SoC look-alike:
> >sam9260/9g20 and sam9261/9g10.

This is hard to follow, please structure them better in the future.

> >----------------------------------------------------------------
> >Jean-Christophe PLAGNIOL-VILLARD (6):
> >       ARM: at91: dt: use #include for all device trees
> >       ARM: at91: dt: switch to standard GPIO flag defines.
> >       ARM: at91: dt: add pinctrl pre-processor define
> >       ARM: at91: dt: switch to pinctrl to pre-processor
> >       ARM: at91: dt: switch to standard IRQ flag defines
> >       ARM: at91: udpate defconfigs

Typo in the patch subject, please keep an eye on these in the future.

> >  arch/arm/configs/at91_dt_defconfig                 |  55 ++-
> >  arch/arm/configs/at91rm9200_defconfig              | 218 ++-------
> >  ...am9g20_defconfig => at91sam9260_9g20_defconfig} |  67 ++-
> >  arch/arm/configs/at91sam9260_defconfig             |  91 ----
> >  ...am9261_defconfig => at91sam9261_9g10_defconfig} |  19 +-
> >  arch/arm/configs/at91sam9263_defconfig             |  39 +-
> >  arch/arm/configs/at91sam9g45_defconfig             |  94 ++--
> >  arch/arm/configs/sama5_defconfig                   |  35 +-
> >  arch/arm/mach-at91/Kconfig.non_dt                  | 159 +++----
> >  arch/arm/mach-at91/Makefile                        |   2 -
> >  arch/arm/mach-at91/board-sam9261ek.c               |  28 +-
> >  include/dt-bindings/pinctrl/at91.h                 |  35 ++
> >  63 files changed, 1407 insertions(+), 1617 deletions(-)
> >  rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
> >  delete mode 100644 arch/arm/configs/at91sam9260_defconfig
> >  rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)
> >  create mode 100644 include/dt-bindings/pinctrl/at91.h

Good to see consolidation, it'd be awesome if there could be even more.


-Olof


From b32955 at freescale.com  Tue May 28 01:51:49 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 13:51:49 +0800
Subject: [PATCH v3 5/6] ARM: dts: imx6dl: add pinctrls for WEIM NOR
In-Reply-To: <60BA5429A0E1584BA3633194F6F993B5025754D1@NA-MBX-03.mgc.mentorg.com>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>,
 <1369389564-13181-6-git-send-email-b32955@freescale.com>
 <60BA5429A0E1584BA3633194F6F993B5025754D1@NA-MBX-03.mgc.mentorg.com>
Message-ID: <51A445F5.4050206@freescale.com>

? 2013?05?25? 01:51, Chaiken, Alison ??:
> n your patch, the address lines are set to 0xb0b1, which is correct, as hysteresis is disabled and SRE is fast for those lines.     However, for data lines, hysteresis is enabled and SRE is slow, so the 0x1b0b0 setting is more appropriate.
0xb0b1 is the legacy value from the BSP code. But i agree that 0x1b0b0 
is better.
I will use it in next version.

thanks
Huang Shijie





From magnus.damm at gmail.com  Tue May 28 01:53:04 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Tue, 28 May 2013 14:53:04 +0900
Subject: [PATCH 2/9] ARM: shmobile: add GPIO IRQ macro
In-Reply-To: <20130528040729.GN13532@quad.lixom.net>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
 <1369648773-7941-3-git-send-email-horms+renesas@verge.net.au>
 <20130528040729.GN13532@quad.lixom.net>
Message-ID: <CANqRtoTUyaqfK3Droq3EuMZy-p2gzzTtcSTp=wiSM-3j0f4+Dg@mail.gmail.com>

Hi Olof,

On Tue, May 28, 2013 at 1:07 PM, Olof Johansson <olof at lixom.net> wrote:
> On Mon, May 27, 2013 at 06:59:26PM +0900, Simon Horman wrote:
>> From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
>>
>> R-Car series gpio_rcar driver can control GPIO IRQ today.
>> It needs base IRQ number for gpio_rcar_config :: .irq_base
>> This patch adds macro for GPIO IRQ.
>> This patch was tested on Bock-W board
>>
>> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>> ---
>>  arch/arm/mach-shmobile/include/mach/irqs.h |    5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
>> index b2074e2..d241bfd 100644
>> --- a/arch/arm/mach-shmobile/include/mach/irqs.h
>> +++ b/arch/arm/mach-shmobile/include/mach/irqs.h
>> @@ -16,4 +16,9 @@
>>  #define IRQPIN_BASE          2000
>>  #define irq_pin(nr)          ((nr) + IRQPIN_BASE)
>>
>> +/* GPIO IRQ */
>> +#define _GPIO_IRQ_BASE               2500
>> +#define GPIO_IRQ_BASE(x)     (_GPIO_IRQ_BASE + (32 * x))
>> +#define GPIO_IRQ(x, y)               (_GPIO_IRQ_BASE + (32 * x) + y)
>> +
>>  #endif /* __ASM_MACH_IRQS_H */
>
> Hmm. It'd be real nice to see some effort on moving this over to sparse
> irq instead. That'll be needed for full device tree conversion anyway. And
> with that, the static irq bases will be gone, so drivers and some of
> the platform code will need to be adjusted accordingly.

I believe we've been doing sparse IRQ for ages, this is just to make
non-DT stuff more readable.

Or was there some particular other interface you wanted us to use for
non-DT board code?

Cheers,

/ magnus


From b32955 at freescale.com  Tue May 28 02:02:51 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:02:51 +0800
Subject: [PATCH v3 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <20130527074400.GD32299@pengutronix.de>
References: <1369389564-13181-1-git-send-email-b32955@freescale.com>
 <1369389564-13181-2-git-send-email-b32955@freescale.com>
 <20130527074400.GD32299@pengutronix.de>
Message-ID: <51A4488B.7020405@freescale.com>

? 2013?05?27? 15:44, Sascha Hauer ??:
> I'm running out of ideas how to explain this. Just drop this remove
> function. You do not allow building this as module. If you did, then
ok.

thanks
Huang Shijie



From daniel.lezcano at linaro.org  Tue May 28 02:08:41 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 28 May 2013 08:08:41 +0200
Subject: [PATCH 10/12] ARM: shmobile: r8a7740: Add CPUIdle
In-Reply-To: <20130528035446.GJ13532@quad.lixom.net>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-11-git-send-email-horms+renesas@verge.net.au>
 <51A33D83.905@linaro.org> <20130528035446.GJ13532@quad.lixom.net>
Message-ID: <51A449E9.5020508@linaro.org>

On 05/28/2013 05:54 AM, Olof Johansson wrote:
> On Mon, May 27, 2013 at 01:03:31PM +0200, Daniel Lezcano wrote:
>> On 05/27/2013 10:59 AM, Simon Horman wrote:
>>> From: Bastian Hecht <hechtb at gmail.com>
>>>
>>> We make use of the r8a7740 Suspend To Ram code to plug together a
>>> CPUIdle driver.
>>>
>>> Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
>>> Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>
>>> ---
>>
>> Shouldn't it go through Rafael's tree ? Or does the patch contains some
>> dependencies on a code only visible in the ARM tree ?
> 
> Missing S-o-b from Simon. But this patch clearly builds on the preceding
> one in the series, so merging them independently might not make much
> sense. Getting an ack from Rafael would be nice though.

I was not suggesting to put the driver in the drivers/cpuidle directory
but to merge the driver through Rafael's tree as we decided some weeks
ago [1]. Although having the drivers all over the place does not help to
consolidate the code, so moving them little by little to drivers/cpuidle
makes sense but this is part of another work.

> I was going to say that it should probably go under drivers/cpuidle as
> well, but that just seems silly -- there is practically no code to share
> with any other platform in this small driver, AND there's not really
> any subsystem-internal data exposed. So it might just make more sense
> to keep it under arch/arm instead.
> 
> Likewise, looking at the kirkwood and calxeda drivers under drivers/cpuidle,
> I'm wondering why we thought it was a good idea to merge them there, besides
> getting caught up in the "nothing can live under arch/arm any more" frenzy.

Having the drivers in the drivers/cpuidle directory like drivers/cpufreq
will help to keep a consistency with the code and a single entry point
for upstream and review.

Thanks.
  -- Daniel

[1] https://patchwork.kernel.org/patch/2492841/

-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From Ganesh.Kumar at harman.com  Tue May 28 02:13:11 2013
From: Ganesh.Kumar at harman.com (Kumar, Ganesh)
Date: Tue, 28 May 2013 01:13:11 -0500
Subject: VDSO for arm 32bit
In-Reply-To: <alpine.LFD.2.03.1305272307340.1918@syhkavp.arg>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <alpine.LFD.2.03.1305272307340.1918@syhkavp.arg>
Message-ID: <634BB1CFA60ED14386C17849392C3EB202E52C9E0A@HICGWSEX01.ad.harman.com>


> Please have a look at Documentation/arm/kernel_user_helpers.txt.

Thanks Nicolas, will start with that and look into the code further.
So the kuser helper are not yet utilized to get the gettimeofday 
as of now on arm32,is my understanding correct?
I'm a newbie in this area and trying to get a fair understanding 
on the topic.


From olof at lixom.net  Tue May 28 02:18:28 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 23:18:28 -0700
Subject: [PATCH 2/9] ARM: shmobile: add GPIO IRQ macro
In-Reply-To: <CANqRtoTUyaqfK3Droq3EuMZy-p2gzzTtcSTp=wiSM-3j0f4+Dg@mail.gmail.com>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
 <1369648773-7941-3-git-send-email-horms+renesas@verge.net.au>
 <20130528040729.GN13532@quad.lixom.net>
 <CANqRtoTUyaqfK3Droq3EuMZy-p2gzzTtcSTp=wiSM-3j0f4+Dg@mail.gmail.com>
Message-ID: <20130528061828.GA20031@quad.lixom.net>

On Tue, May 28, 2013 at 02:53:04PM +0900, Magnus Damm wrote:
> Hi Olof,
> 
> On Tue, May 28, 2013 at 1:07 PM, Olof Johansson <olof at lixom.net> wrote:
> > On Mon, May 27, 2013 at 06:59:26PM +0900, Simon Horman wrote:
> >> From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> >>
> >> R-Car series gpio_rcar driver can control GPIO IRQ today.
> >> It needs base IRQ number for gpio_rcar_config :: .irq_base
> >> This patch adds macro for GPIO IRQ.
> >> This patch was tested on Bock-W board
> >>
> >> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> >> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >> ---
> >>  arch/arm/mach-shmobile/include/mach/irqs.h |    5 +++++
> >>  1 file changed, 5 insertions(+)
> >>
> >> diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
> >> index b2074e2..d241bfd 100644
> >> --- a/arch/arm/mach-shmobile/include/mach/irqs.h
> >> +++ b/arch/arm/mach-shmobile/include/mach/irqs.h
> >> @@ -16,4 +16,9 @@
> >>  #define IRQPIN_BASE          2000
> >>  #define irq_pin(nr)          ((nr) + IRQPIN_BASE)
> >>
> >> +/* GPIO IRQ */
> >> +#define _GPIO_IRQ_BASE               2500
> >> +#define GPIO_IRQ_BASE(x)     (_GPIO_IRQ_BASE + (32 * x))
> >> +#define GPIO_IRQ(x, y)               (_GPIO_IRQ_BASE + (32 * x) + y)
> >> +
> >>  #endif /* __ASM_MACH_IRQS_H */
> >
> > Hmm. It'd be real nice to see some effort on moving this over to sparse
> > irq instead. That'll be needed for full device tree conversion anyway. And
> > with that, the static irq bases will be gone, so drivers and some of
> > the platform code will need to be adjusted accordingly.
> 
> I believe we've been doing sparse IRQ for ages, this is just to make
> non-DT stuff more readable.
> 
> Or was there some particular other interface you wanted us to use for
> non-DT board code?

Sorry, terminology confusion on my side. Most other platforms sorted
this out when they moved to sparse irq, removing most hardcoded interrupt
numbers at the same time and handling it through DT. But since shmobile
still has a ways to go on DT conversion things are a bit different.

Either way, once things have been converted fully to DT, most of these
static numberings can/should be possible to remove.


-Olof


From shawn.guo at linaro.org  Tue May 28 02:22:32 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 May 2013 14:22:32 +0800
Subject: [PATCH] thermal: cpu_cooling: fix 'descend' check in get_property()
Message-ID: <1369722152-9732-1-git-send-email-shawn.guo@linaro.org>

The variable 'descend' is initialized as -1 in function get_property(),
and will never get any chance to be updated by the following code.

	if (freq != CPUFREQ_ENTRY_INVALID && descend != -1)
		descend = !!(freq > table[i].frequency);

This makes function get_property() return the wrong frequency for given
cooling level if the frequency table is sorted in ascending.  Fix it
by correcting the 'descend' check in if-condition to 'descend == -1'.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/thermal/cpu_cooling.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
index c94bf2e..82e15db 100644
--- a/drivers/thermal/cpu_cooling.c
+++ b/drivers/thermal/cpu_cooling.c
@@ -167,7 +167,7 @@ static int get_property(unsigned int cpu, unsigned long input,
 			continue;
 
 		/* get the frequency order */
-		if (freq != CPUFREQ_ENTRY_INVALID && descend != -1)
+		if (freq != CPUFREQ_ENTRY_INVALID && descend == -1)
 			descend = !!(freq > table[i].frequency);
 
 		freq = table[i].frequency;
-- 
1.7.9.5




From olof at lixom.net  Tue May 28 02:22:46 2013
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 May 2013 23:22:46 -0700
Subject: [PATCH 04/12] ARM: shmobile: r8a7740: Add DT name to clock list
 for CMT10
In-Reply-To: <20130528052944.GC25005@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-5-git-send-email-horms+renesas@verge.net.au>
 <20130528032948.GF13532@quad.lixom.net>
 <20130528052944.GC25005@verge.net.au>
Message-ID: <20130528062246.GB20031@quad.lixom.net>

On Tue, May 28, 2013 at 02:29:44PM +0900, Simon Horman wrote:
> On Mon, May 27, 2013 at 08:29:48PM -0700, Olof Johansson wrote:
> > Hi,
> > 
> > On Mon, May 27, 2013 at 05:59:45PM +0900, Simon Horman wrote:
> > > From: Bastian Hecht <hechtb at gmail.com>
> > > 
> > > This adds temporarily the alternative device name to the clock list
> > > that is used when booting via Device Tree setup.
> > 
> > > 
> > > Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
> > > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > > ---
> > >  arch/arm/mach-shmobile/clock-r8a7740.c |    1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
> > > index 5bd8da0..8fc396a 100644
> > > --- a/arch/arm/mach-shmobile/clock-r8a7740.c
> > > +++ b/arch/arm/mach-shmobile/clock-r8a7740.c
> > > @@ -582,6 +582,7 @@ static struct clk_lookup lookups[] = {
> > >  	CLKDEV_DEV_ID("e6cc0000.sci",		&mstp_clks[MSTP230]),
> > >  
> > >  	CLKDEV_DEV_ID("sh_cmt.10",		&mstp_clks[MSTP329]),
> > > +	CLKDEV_DEV_ID("e6138010.timer",		&mstp_clks[MSTP329]),
> > >  	CLKDEV_DEV_ID("sh_fsi2",		&mstp_clks[MSTP328]),
> > >  	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
> > >  	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
> > > -- 
> > > 1.7.10.4
> > > 
> > 
> > Usually this is instead handled by adding entries to OF_DEV_AUXDATA() to
> > rename the device in the board file. Would you mind doing that instead?
> 
> Magnus has indicated in the past that he prefers this method over
> using OF_DEV_AUXDATA() and the above is consistent with other
> shmobile code.

Ho hum. That's 180 degrees opposite to how we've been doing it on all
other ARM platforms. :)

Once you guys have clock bindings for device tree, the aliases should be
possible to remove. That's where having them as auxdata is useful, since it's
just one place and it's also obvious just what clocks and what drivers need
aliases on device tree.

Where are you guys at on your plans for getting DT_based clock going? That will
sort of indicate just how temporary these clock alaises will be. I'm guessing
we'll be living with them for a while though?


-Olof


From afzal at ti.com  Tue May 28 02:24:48 2013
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 28 May 2013 11:54:48 +0530
Subject: [PATCH] ARM: OMAP2+: timer: initialize before using oh_name
Message-ID: <1369722288-15592-1-git-send-email-afzal@ti.com>

of_property_read_string_index(...,&oh_name) in omap_dm_timer_init_one
does not alter the value of 'oh_name' even if the relevant function
fails and as 'oh_name' in stack may have a non-zero value, it would
be misunderstood by timer code that DT has specified "ti,hwmod"
property for timer. 'oh_name' in this scenario would be a junk value,
this would result in module not being enabled by hwmod API's for
timer, and in turn crash.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f8b23b8..8e0c390 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -220,7 +220,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 					 int posted)
 {
 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
-	const char *oh_name;
+	const char *oh_name = NULL;
 	struct device_node *np;
 	struct omap_hwmod *oh;
 	struct resource irq, mem;
-- 
1.7.12



From shawn.guo at linaro.org  Tue May 28 02:27:13 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 May 2013 14:27:13 +0800
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <201305280656.27472.marex@denx.de>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <CAOMZO5DRuKrECnYDtZ0wOK6_vpW95Cwc3xf7LT+VT_B7eV3gug@mail.gmail.com>
 <20130528014348.GA19608@S2101-09.ap.freescale.net>
 <201305280656.27472.marex@denx.de>
Message-ID: <20130528062711.GB19608@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 06:56:27AM +0200, Marek Vasut wrote:
> What is the problem you observe?
> 
The audio playback gives silent output.

Shawn



From kishon at ti.com  Tue May 28 02:35:45 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Tue, 28 May 2013 12:05:45 +0530
Subject: [PATCH v6 0/9] Generic PHY Framework
In-Reply-To: <519AFF95.9060002@ti.com>
References: <1367229812-30574-1-git-send-email-kishon@ti.com>
 <519AFF95.9060002@ti.com>
Message-ID: <51A45041.2030105@ti.com>

Hi,

On Tuesday 21 May 2013 10:31 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 29 April 2013 03:33 PM, Kishon Vijay Abraham I wrote:
>> Added a generic PHY framework that provides a set of APIs for the PHY
>> drivers
>> to create/destroy a PHY and APIs for the PHY users to obtain a
>> reference to
>> the PHY with or without using phandle.
>>
>> This framework will be of use only to devices that uses external PHY (PHY
>> functionality is not embedded within the controller).
>>
>> The intention of creating this framework is to bring the phy drivers
>> spread
>> all over the Linux kernel to drivers/phy to increase code re-use and to
>> increase code maintainability.
>>
>> Comments to make PHY as bus wasn't done because PHY devices can be
>> part of
>> other bus and making a same device attached to multiple bus leads to bad
>> design.
>>
>> If the PHY driver has to send notification on connect/disconnect, the PHY
>> driver should make use of the extcon framework. Using this susbsystem
>> to use extcon framwork will have to be analysed.
>>
>> Making omap-usb2 and twl4030 to use this framework is provided as a
>> sample.
>>
>> This patch series is developed on linux-next tree.
>
> Any comments on this patch series?

Ping..

This series is needed for usb3 phy/sata phy and can also be used by 
certain video phys. I think it's important to get this in.

Thanks
Kishon


From b32955 at freescale.com  Tue May 28 02:20:06 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:06 +0800
Subject: [PATCH v4 0/6] ARM: imx6q{dl}: add the WEIM driver
Message-ID: <1369722012-6915-1-git-send-email-b32955@freescale.com>

This patch set adds a new driver for WEIM in the imx6q{dl}-sabreauto boards.

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, only the NOR is connected to WEIM.

v3 --> v4:
	[0] use a more proper pad value for the data pins.
	[1] remove the weim_remove() hook.
	[2] remove the blank line.
	[3] use the lower case for the hex value.
	[4] add returne value for weim_parse_dt().
	[5] rename the pinctrls.

v2 --> v3:
	[0] split the NOR pinctrl.
	[1] make the driver unloaded. change to bool type in Kconfig.
	[2] use the of_platform_populate().
	[3] remove the unused "interrupt" property from the Doc.
v1 --> v2:
	[0] remove used PADs.
	[1] fix the wrong pad values, (thanks Alison Chaiken)
	[2] remove the weim-cs-index.
	[3] add "fsl" for the weim-cs-timing.
	[4] remove the partitions info in the document.
	[5] rewrite the drivers(follow Sascha and Shawn's comments)


Huang Shijie (6):
  drivers: bus: add a new driver for WEIM
  ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
  ARM: dts: imx6qdl: add more information for WEIM
  ARM: dts: imx6q: add pinctrls for WEIM NOR
  ARM: dts: imx6dl: add pinctrls for WEIM NOR
  ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR

 Documentation/devicetree/bindings/bus/imx-weim.txt |   49 +++++++
 arch/arm/boot/dts/imx6dl-sabreauto.dts             |    9 +-
 arch/arm/boot/dts/imx6dl.dtsi                      |   58 ++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts              |    9 +-
 arch/arm/boot/dts/imx6q.dtsi                       |   59 +++++++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |   21 +++-
 arch/arm/boot/dts/imx6qdl.dtsi                     |    4 +-
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  138 ++++++++++++++++++++
 10 files changed, 353 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c




From b32955 at freescale.com  Tue May 28 02:20:08 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:08 +0800
Subject: [PATCH v4 2/6] ARM: dts: imx6q{dl}: fix the pin conflict between SPI
 and WEIM
In-Reply-To: <1369722012-6915-1-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
Message-ID: <1369722012-6915-3-git-send-email-b32955@freescale.com>

In the imx6q-sabreauto and imx6dl-sabreauto boards,
the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
it is used as a data pin for the WEIM NOR.

In order to fix the conflict, this patch removes the pin from the hog,
and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto.

The SPI NOR selects this pinctrl_ecspi1_sabreauto when it is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl-sabreauto.dts   |    9 ++++++++-
 arch/arm/boot/dts/imx6q-sabreauto.dts    |    9 ++++++++-
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    2 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 60f3038..95da711 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -25,7 +25,14 @@
 			fsl,pins = <
 				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+			fsl,pins = <
+				MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 9fb3e99..09a7580 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -29,7 +29,14 @@
 			fsl,pins = <
 				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
+			>;
+		};
+	};
+
+	ecspi1 {
+		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+			fsl,pins = <
+				MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d6baa51..a4466e6 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -20,7 +20,7 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio3 19 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
 	status = "disabled"; /* pin conflict with WEIM NOR */
 
 	flash: m25p80 at 0 {
-- 
1.7.1




From b32955 at freescale.com  Tue May 28 02:20:07 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:07 +0800
Subject: [PATCH v4 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369722012-6915-1-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
Message-ID: <1369722012-6915-2-git-send-email-b32955@freescale.com>

The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.

This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabled.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 Documentation/devicetree/bindings/bus/imx-weim.txt |   49 +++++++
 drivers/bus/Kconfig                                |    9 ++
 drivers/bus/Makefile                               |    1 +
 drivers/bus/imx-weim.c                             |  138 ++++++++++++++++++++
 4 files changed, 197 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
 create mode 100644 drivers/bus/imx-weim.c

diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644
index 0000000..cedc2a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -0,0 +1,49 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+
+The term "wireless" does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+
+The actual devices are instantiated from the child nodes of a WEIM node.
+
+Required properties:
+
+ - compatible:		Should be set to "fsl,imx6q-weim"
+ - reg:			A resource specifier for the register space
+			(see the example below)
+ - clocks:		the clock, see the example below.
+ - #address-cells:	Must be set to 2 to allow memory address translation
+ - #size-cells:		Must be set to 1 to allow CS address passing
+ - ranges:		Must be set up to reflect the memory layout with four
+			integer values for each chip-select line in use:
+
+			   <cs-number> 0 <physical address of mapping> <size>
+
+Timing property for child nodes. It is mandatory, not optional.
+
+ - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the
+			child node. We can get the CS index from the child
+			node's "reg" property. This property contains the values
+			for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
+			EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+
+Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
+
+	weim: weim at 021b8000 {
+		compatible = "fsl,imx6q-weim";
+		reg = <0x021b8000 0x4000>;
+		clocks = <&clks 196>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0x08000000 0x08000000>;
+
+		nor at 0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x02000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+					0x0000c000 0x1404a38e 0x00000000>;
+		};
+	};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab..46cd5bb 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,15 @@
 
 menu "Bus devices"
 
+config IMX_WEIM
+	bool "Freescale EIM DRIVER"
+	depends on ARCH_MXC
+	help
+	  Driver for i.MX6 WEIM controller.
+	  The WEIM(Wireless External Interface Module) works like a bus.
+	  You can attach many different devices on it, such as NOR, onenand.
+	  But now, we only support the Parallel NOR.
+
 config MVEBU_MBUS
 	bool
 	depends on PLAT_ORION
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c..436bbcc 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
new file mode 100644
index 0000000..349f14e
--- /dev/null
+++ b/drivers/bus/imx-weim.c
@@ -0,0 +1,138 @@
+/*
+ * EIM driver for Freescale's i.MX chips
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+
+struct imx_weim {
+	void __iomem *base;
+	struct clk *clk;
+};
+
+static const struct of_device_id weim_id_table[] = {
+	{ .compatible = "fsl,imx6q-weim", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, weim_id_table);
+
+#define CS_TIMING_LEN 6
+#define CS_REG_RANGE  0x18
+
+/* Parse and set the timing for this device. */
+static int
+weim_timing_setup(struct platform_device *pdev, struct device_node *np)
+{
+	struct imx_weim *weim = platform_get_drvdata(pdev);
+	u32 value[CS_TIMING_LEN];
+	u32 cs_idx;
+	int ret;
+	int i;
+
+	/* get the CS index from this child node's "reg" property. */
+	ret = of_property_read_u32(np, "reg", &cs_idx);
+	if (ret)
+		return ret;
+
+	/* The weim has four chip selects. */
+	if (cs_idx > 3)
+		return -EINVAL;
+
+	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
+					value, CS_TIMING_LEN);
+	if (ret)
+		return ret;
+
+	/* set the timing for WEIM */
+	for (i = 0; i < CS_TIMING_LEN; i++)
+		writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
+	return 0;
+}
+
+static int weim_parse_dt(struct platform_device *pdev)
+{
+	struct device_node *child;
+	int ret;
+
+	for_each_child_of_node(pdev->dev.of_node, child) {
+		if (!child->name)
+			continue;
+
+		ret = weim_timing_setup(pdev, child);
+		if (ret) {
+			dev_err(&pdev->dev, "%s set timing failed.\n",
+				child->full_name);
+			return ret;
+		}
+	}
+
+	ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+	if (ret)
+		dev_err(&pdev->dev, "%s fail to create devices.\n",
+			pdev->dev.of_node->full_name);
+	return ret;
+}
+
+static int weim_probe(struct platform_device *pdev)
+{
+	struct imx_weim *weim;
+	struct resource *res;
+	int ret = -EINVAL;
+
+	weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
+	if (!weim) {
+		ret = -ENOMEM;
+		goto weim_err;
+	}
+	platform_set_drvdata(pdev, weim);
+
+	/* get the resource */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	weim->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(weim->base)) {
+		ret = PTR_ERR(weim->base);
+		goto weim_err;
+	}
+
+	/* get the clock */
+	weim->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(weim->clk))
+		goto weim_err;
+
+	ret = clk_prepare_enable(weim->clk);
+	if (ret)
+		goto weim_err;
+
+	/* parse the device node */
+	ret = weim_parse_dt(pdev);
+	if (ret) {
+		clk_disable_unprepare(weim->clk);
+		goto weim_err;
+	}
+
+	dev_info(&pdev->dev, "WEIM driver registered.\n");
+	return 0;
+
+weim_err:
+	return ret;
+}
+
+static struct platform_driver weim_driver = {
+	.driver = {
+		.name = "imx-weim",
+		.of_match_table = weim_id_table,
+	},
+	.probe   = weim_probe,
+};
+
+module_platform_driver(weim_driver);
+MODULE_AUTHOR("Freescale Semiconductor Inc.");
+MODULE_DESCRIPTION("i.MX EIM Controller Driver");
+MODULE_LICENSE("GPL");
-- 
1.7.1




From b32955 at freescale.com  Tue May 28 02:20:09 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:09 +0800
Subject: [PATCH v4 3/6] ARM: dts: imx6qdl: add more information for WEIM
In-Reply-To: <1369722012-6915-1-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
Message-ID: <1369722012-6915-4-git-send-email-b32955@freescale.com>

Add the clock and compatible information for the weim.
Also adds the weim label.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461c..f21d259 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -744,9 +744,11 @@
 				reg = <0x021b4000 0x4000>;
 			};
 
-			weim at 021b8000 {
+			weim: weim at 021b8000 {
+				compatible = "fsl,imx6q-weim";
 				reg = <0x021b8000 0x4000>;
 				interrupts = <0 14 0x04>;
+				clocks = <&clks 196>;
 			};
 
 			ocotp at 021bc000 {
-- 
1.7.1




From b32955 at freescale.com  Tue May 28 02:20:10 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:10 +0800
Subject: [PATCH v4 4/6] ARM: dts: imx6q: add pinctrls for WEIM NOR
In-Reply-To: <1369722012-6915-1-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
Message-ID: <1369722012-6915-5-git-send-email-b32955@freescale.com>

Add two pinctrls for WEIM:
   one for the weim nor, another for the chipselect.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   59 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 59 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..d79455d 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -323,6 +323,65 @@
 						>;
 					};
 				};
+
+				weim {
+					pinctrl_weim_cs0_1: weim_cs0grp-1 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+						>;
+					};
+
+					pinctrl_weim_nor_1: weimnorgrp-1 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+							/* data */
+							MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+							MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+							MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+							MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+							MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+							MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+							MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+							MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+							MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+							MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+							MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+							MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+							MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+							MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+							MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+							MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+							/* address */
+							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 			};
 		};
 
-- 
1.7.1




From b32955 at freescale.com  Tue May 28 02:20:11 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:11 +0800
Subject: [PATCH v4 5/6] ARM: dts: imx6dl: add pinctrls for WEIM NOR
In-Reply-To: <1369722012-6915-1-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
Message-ID: <1369722012-6915-6-git-send-email-b32955@freescale.com>

Add two pinctrls for WEIM:
   one for the weim nor, another for the chipselect.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   58 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 58 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 4b13454..2ecbcbc 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -183,6 +183,64 @@
 					};
 				};
 
+				weim {
+					pinctrl_weim_cs0_1: weim_cs0grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+						>;
+					};
+
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+							/* data */
+							MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+							MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+							MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+							MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+							MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+							MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+							MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+							MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+							MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+							MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+							MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+							MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+							MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+							MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+							MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+							MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+							/* address */
+							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 
 			};
 
-- 
1.7.1




From b32955 at freescale.com  Tue May 28 02:20:12 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 28 May 2013 14:20:12 +0800
Subject: [PATCH v4 6/6] ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
In-Reply-To: <1369722012-6915-1-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
Message-ID: <1369722012-6915-7-git-send-email-b32955@freescale.com>

Enable the WEIM NOR for imx6q{dl}-sabreauto boards.

For the pin conflict with SPI NOR, its status is set to "disabled".

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index a4466e6..e994011 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -58,3 +58,22 @@
 	wp-gpios = <&gpio1 13 0>;
 	status = "okay";
 };
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	status = "disabled"; /* pin conflict with SPI NOR */
+
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+				0x0000c000 0x1404a38e 0x00000000>;
+	};
+};
-- 
1.7.1




From s.hauer at pengutronix.de  Tue May 28 02:43:27 2013
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 May 2013 08:43:27 +0200
Subject: [PATCH v4 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369722012-6915-2-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
 <1369722012-6915-2-git-send-email-b32955@freescale.com>
Message-ID: <20130528064327.GT32299@pengutronix.de>

On Tue, May 28, 2013 at 02:20:07PM +0800, Huang Shijie wrote:
> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Looks good to me now. Thanks for working on this.

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From rui.zhang at intel.com  Tue May 28 02:48:16 2013
From: rui.zhang at intel.com (Zhang Rui)
Date: Tue, 28 May 2013 14:48:16 +0800
Subject: [PATCH] thermal: cpu_cooling: fix 'descend' check in
 get_property()
In-Reply-To: <1369722152-9732-1-git-send-email-shawn.guo@linaro.org>
References: <1369722152-9732-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1369723696.2083.44.camel@rzhang1-mobl4>

On Tue, 2013-05-28 at 14:22 +0800, Shawn Guo wrote:
> The variable 'descend' is initialized as -1 in function get_property(),
> and will never get any chance to be updated by the following code.
> 
> 	if (freq != CPUFREQ_ENTRY_INVALID && descend != -1)
> 		descend = !!(freq > table[i].frequency);
> 
> This makes function get_property() return the wrong frequency for given
> cooling level if the frequency table is sorted in ascending.  Fix it
> by correcting the 'descend' check in if-condition to 'descend == -1'.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

good catch!
patch applied to thermal -next.

thanks,
rui
> ---
>  drivers/thermal/cpu_cooling.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
> index c94bf2e..82e15db 100644
> --- a/drivers/thermal/cpu_cooling.c
> +++ b/drivers/thermal/cpu_cooling.c
> @@ -167,7 +167,7 @@ static int get_property(unsigned int cpu, unsigned long input,
>  			continue;
>  
>  		/* get the frequency order */
> -		if (freq != CPUFREQ_ENTRY_INVALID && descend != -1)
> +		if (freq != CPUFREQ_ENTRY_INVALID && descend == -1)
>  			descend = !!(freq > table[i].frequency);
>  
>  		freq = table[i].frequency;




From shawn.guo at linaro.org  Tue May 28 02:50:48 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 May 2013 14:50:48 +0800
Subject: [PATCH v4 1/6] drivers: bus: add a new driver for WEIM
In-Reply-To: <1369722012-6915-2-git-send-email-b32955@freescale.com>
References: <1369722012-6915-1-git-send-email-b32955@freescale.com>
 <1369722012-6915-2-git-send-email-b32955@freescale.com>
Message-ID: <20130528065047.GC19608@S2101-09.ap.freescale.net>

Hi Arnd,

On Tue, May 28, 2013 at 02:20:07PM +0800, Huang Shijie wrote:
> The WEIM(Wireless External Interface Module) works like a bus.
> You can attach many different devices on it, such as NOR, onenand.
> 
> In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
> 
> This patch also adds the devicetree binding document.
> The driver only works when the devicetree is enabled.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  Documentation/devicetree/bindings/bus/imx-weim.txt |   49 +++++++
>  drivers/bus/Kconfig                                |    9 ++
>  drivers/bus/Makefile                               |    1 +
>  drivers/bus/imx-weim.c                             |  138 ++++++++++++++++++++

What's the general merge path for drivers/bus/ ones?  It's not clear to
me who is collecting those drivers/bus/ patches.

Shawn

>  4 files changed, 197 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt
>  create mode 100644 drivers/bus/imx-weim.c



From shawn.guo at linaro.org  Tue May 28 02:55:48 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 May 2013 14:55:48 +0800
Subject: [PATCH] thermal: step_wise: cdev only needs update on a new target
 state
Message-ID: <1369724148-15087-1-git-send-email-shawn.guo@linaro.org>

The cooling device only needs update on a new target state.  Since we
already check old target in thermal_zone_trip_update(), we can do one
more check to see if it's a new target state.  If not, we can reasonably
save some uncecesary code execution.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/thermal/step_wise.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/thermal/step_wise.c b/drivers/thermal/step_wise.c
index 4d4ddae..0afbd86 100644
--- a/drivers/thermal/step_wise.c
+++ b/drivers/thermal/step_wise.c
@@ -133,6 +133,9 @@ static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip)
 		old_target = instance->target;
 		instance->target = get_target_state(instance, trend, throttle);
 
+		if (old_target == instance->target)
+			continue;
+
 		/* Activate a passive thermal instance */
 		if (old_target == THERMAL_NO_TARGET &&
 			instance->target != THERMAL_NO_TARGET)
-- 
1.7.9.5




From yegorslists at googlemail.com  Tue May 28 03:21:01 2013
From: yegorslists at googlemail.com (yegorslists at googlemail.com)
Date: Tue, 28 May 2013 09:21:01 +0200
Subject: [PATCH v2] usb: musb: fix clock naming
Message-ID: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>

From: Yegor Yefremov <yegorslists at googlemail.com>

'ick' was changed to 'hsotgusb_ick'
'fck' was changed to 'hsotgusb_fck'

Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
---
v2: CC linux-usb mailing list

 drivers/usb/musb/am35x.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index 2231850..92b5b23 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -477,14 +477,14 @@ static int am35x_probe(struct platform_device *pdev)
 		goto err1;
 	}
 
-	phy_clk = clk_get(&pdev->dev, "fck");
+	phy_clk = clk_get(&pdev->dev, "hsotgusb_ick");
 	if (IS_ERR(phy_clk)) {
 		dev_err(&pdev->dev, "failed to get PHY clock\n");
 		ret = PTR_ERR(phy_clk);
 		goto err3;
 	}
 
-	clk = clk_get(&pdev->dev, "ick");
+	clk = clk_get(&pdev->dev, "hsotgusb_fck");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
 		ret = PTR_ERR(clk);
-- 
1.7.7



From maarten.lankhorst at canonical.com  Tue May 28 03:23:08 2013
From: maarten.lankhorst at canonical.com (Maarten Lankhorst)
Date: Tue, 28 May 2013 09:23:08 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <005601ce5b4d$f95e0160$ec1a0420$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <51A37A54.1040700@canonical.com>
 <005601ce5b4d$f95e0160$ec1a0420$%dae@samsung.com>
Message-ID: <51A45B5C.6030407@canonical.com>

Hey,

Op 28-05-13 04:49, Inki Dae schreef:
>
>> -----Original Message-----
>> From: Maarten Lankhorst [mailto:maarten.lankhorst at canonical.com]
>> Sent: Tuesday, May 28, 2013 12:23 AM
>> To: Inki Dae
>> Cc: 'Daniel Vetter'; 'Rob Clark'; 'linux-fbdev'; 'YoungJun Cho'; 'Kyungmin
>> Park'; 'myungjoo.ham'; 'DRI mailing list'; linux-arm-
>> kernel at lists.infradead.org; linux-media at vger.kernel.org
>> Subject: Re: Introduce a new helper framework for buffer synchronization
>>
>> Hey,
>>
>> Op 27-05-13 12:38, Inki Dae schreef:
>>> Hi all,
>>>
>>> I have been removed previous branch and added new one with more cleanup.
>>> This time, the fence helper doesn't include user side interfaces and
>> cache
>>> operation relevant codes anymore because not only we are not sure that
>>> coupling those two things, synchronizing caches and buffer access
>> between
>>> CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is
>> a
>>> good idea yet but also existing codes for user side have problems with
>> badly
>>> behaved or crashing userspace. So this could be more discussed later.
>>>
>>> The below is a new branch,
>>>
>>> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
>> exynos.git/?h=dma-f
>>> ence-helper
>>>
>>> And fence helper codes,
>>>
>>> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
>> exynos.git/commit/?
>>> h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
>>>
>>> And example codes for device driver,
>>>
>>> https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
>> exynos.git/commit/?
>>> h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
>>>
>>> I think the time is not yet ripe for RFC posting: maybe existing dma
>> fence
>>> and reservation need more review and addition work. So I'd glad for
>> somebody
>>> giving other opinions and advices in advance before RFC posting.
>>>
>> NAK.
>>
>> For examples for how to handle locking properly, see Documentation/ww-
>> mutex-design.txt in my recent tree.
>> I could list what I believe is wrong with your implementation, but real
>> problem is that the approach you're taking is wrong.
> I just removed ticket stubs to show my approach you guys as simple as
> possible, and I just wanted to show that we could use buffer synchronization
> mechanism without ticket stubs.
The tickets have been removed in favor of a ww_context. Moving it in as a base primitive
allows more locking abuse to be detected, and makes some other things easier too.

> Question, WW-Mutexes could be used for all devices? I guess this has
> dependence on x86 gpu: gpu has VRAM and it means different memory domain.
> And could you tell my why shared fence should have only eight objects? I
> think we could need more than eight objects for read access. Anyway I think
> I don't surely understand yet so there might be my missing point.
Yes, ww mutexes are not limited in any way to x86. They're a locking mechanism.
When you acquired the ww mutexes for all buffer objects, all it does is say at
that point in time you have exclusively acquired the locks of all bo's.

After locking everything you can read the fence pointers safely, queue waits, and set a
new fence pointer on all reservation_objects. You only need a single fence
on all those objects, so 8 is plenty. Nonetheless this was a limitation of my
earlier design, and I'll dynamically allocate fence_shared in the future.

~Maarten



From linus.walleij at stericsson.com  Tue May 28 03:33:33 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 28 May 2013 09:33:33 +0200
Subject: [PATCH] ARM: ux500: add ABx500 pinctrl tables
Message-ID: <1369726413-18676-1-git-send-email-linus.walleij@stericsson.com>

From: Patrice Chotard <patrice.chotard at st.com>

This adds pin control tables for the ABx500 (AB8500 and
AB8505) PMIC, which also happens to act as a multimedia
pin expander on the ux500 platforms.

Cc: Lee Jones <lee.jones at linaro.org>
Signed-off-by: Patrice Chotard <patrice.chotard at st.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-pins.c | 262 ++++++++++++++++++++++++++++++++
 1 file changed, 262 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 3f92308..6086062 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -9,6 +9,7 @@
 #include <linux/bug.h>
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 
 #include <asm/mach-types.h>
@@ -34,6 +35,11 @@ BIAS(in_pd, PIN_INPUT_PULLDOWN);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+
+BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
+BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
+BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
+
 /* These also force them into GPIO mode */
 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
@@ -97,6 +103,252 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
 #define DB8500_PIN_STATE(pin, conf, dev, state) \
 	PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 
+#define AB8500_MUX_HOG(group, func) \
+	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_HOG(pin, conf) \
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
+
+#define AB8500_MUX_STATE(group, func, dev, state) \
+	PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_STATE(pin, conf, dev, state) \
+	PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
+
+#define AB8505_MUX_HOG(group, func) \
+	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_HOG(pin, conf) \
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
+
+#define AB8505_MUX_STATE(group, func, dev, state) \
+	PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_STATE(pin, conf, dev, state) \
+	PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
+
+static struct pinctrl_map __initdata ab8500_pinmap[] = {
+	/* Sysclkreq2 */
+	AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
+	AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
+	/* sysclkreq2 disable, mux in gpio configured in input pulldown */
+	AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
+	AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
+
+	/* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+	AB8500_MUX_HOG("gpio2_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO2_T9", in_pd),
+
+	/* Sysclkreq4 */
+	AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+	AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+	/* sysclkreq4 disable, mux in gpio configured in input pulldown */
+	AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+	AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+
+	/* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
+	AB8500_MUX_HOG("gpio4_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO4_W2", in_pd),
+
+	/*
+	 * pins 6,7,8 and 9 are muxed in YCBCR0123
+	 * configured in INPUT PULL UP
+	 */
+	AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
+	AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
+	AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
+	AB8500_PIN_HOG("GPIO8_W18", in_nopull),
+	AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
+
+	/*
+	 * pins 10,11,12 and 13 are muxed in GPIO
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("gpio10_d_1", "gpio"),
+	AB8500_PIN_HOG("GPIO10_U17", in_pd),
+
+	AB8500_MUX_HOG("gpio11_d_1", "gpio"),
+	AB8500_PIN_HOG("GPIO11_AA18", in_pd),
+
+	AB8500_MUX_HOG("gpio12_d_1", "gpio"),
+	AB8500_PIN_HOG("GPIO12_U16", in_pd),
+
+	AB8500_MUX_HOG("gpio13_d_1", "gpio"),
+	AB8500_PIN_HOG("GPIO13_W17", in_pd),
+
+	/*
+	 * pins 14,15 are muxed in PWM1 and PWM2
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
+	AB8500_PIN_HOG("GPIO14_F14", in_pd),
+
+	AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
+	AB8500_PIN_HOG("GPIO15_B17", in_pd),
+
+	/*
+	 * pins 16 is muxed in GPIO
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("gpio16_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO14_F14", in_pd),
+
+	/*
+	 * pins 17,18,19 and 20 are muxed in AUDIO interface 1
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("adi1_d_1", "adi1"),
+	AB8500_PIN_HOG("GPIO17_P5", in_pd),
+	AB8500_PIN_HOG("GPIO18_R5", in_pd),
+	AB8500_PIN_HOG("GPIO19_U5", in_pd),
+	AB8500_PIN_HOG("GPIO20_T5", in_pd),
+
+	/*
+	 * pins 21,22 and 23 are muxed in USB UICC
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
+	AB8500_PIN_HOG("GPIO21_H19", in_pd),
+	AB8500_PIN_HOG("GPIO22_G20", in_pd),
+	AB8500_PIN_HOG("GPIO23_G19", in_pd),
+
+	/*
+	 * pins 24,25 are muxed in GPIO
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("gpio24_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO24_T14", in_pd),
+
+	AB8500_MUX_HOG("gpio25_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO25_R16", in_pd),
+
+	/*
+	 * pins 26 is muxed in GPIO
+	 * configured in OUTPUT LOW
+	 */
+	AB8500_MUX_HOG("gpio26_d_1", "gpio"),
+	AB8500_PIN_HOG("GPIO26_M16", out_lo),
+
+	/*
+	 * pins 27,28 are muxed in DMIC12
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("dmic12_d_1", "dmic"),
+	AB8500_PIN_HOG("GPIO27_J6", in_pd),
+	AB8500_PIN_HOG("GPIO28_K6", in_pd),
+
+	/*
+	 * pins 29,30 are muxed in DMIC34
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("dmic34_d_1", "dmic"),
+	AB8500_PIN_HOG("GPIO29_G6", in_pd),
+	AB8500_PIN_HOG("GPIO30_H6", in_pd),
+
+	/*
+	 * pins 31,32 are muxed in DMIC56
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("dmic56_d_1", "dmic"),
+	AB8500_PIN_HOG("GPIO31_F5", in_pd),
+	AB8500_PIN_HOG("GPIO32_G5", in_pd),
+
+	/*
+	 * pins 34 is muxed in EXTCPENA
+	 * configured INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
+	AB8500_PIN_HOG("GPIO34_R17", in_pd),
+
+	/*
+	 * pins 35 is muxed in GPIO
+	 * configured in OUTPUT LOW
+	 */
+	AB8500_MUX_HOG("gpio35_d_1", "gpio"),
+	AB8500_PIN_HOG("GPIO35_W15", in_pd),
+
+	/*
+	 * pins 36,37,38 and 39 are muxed in GPIO
+	 * configured in INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("gpio36_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO36_A17", in_pd),
+
+	AB8500_MUX_HOG("gpio37_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO37_E15", in_pd),
+
+	AB8500_MUX_HOG("gpio38_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO38_C17", in_pd),
+
+	AB8500_MUX_HOG("gpio39_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO39_E16", in_pd),
+
+	/*
+	 * pins 40 and 41 are muxed in MODCSLSDA
+	 * configured INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
+	AB8500_PIN_HOG("GPIO40_T19", in_pd),
+	AB8500_PIN_HOG("GPIO41_U19", in_pd),
+
+	/*
+	 * pins 42 is muxed in GPIO
+	 * configured INPUT PULL DOWN
+	 */
+	AB8500_MUX_HOG("gpio42_a_1", "gpio"),
+	AB8500_PIN_HOG("GPIO42_U2", in_pd),
+};
+
+static struct pinctrl_map __initdata ab8505_pinmap[] = {
+	/* Sysclkreq2 */
+	AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+	AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+	/* sysclkreq2 disable, mux in gpio configured in input pulldown */
+	AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+	AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+
+	/* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+	AB8505_MUX_HOG("gpio2_a_1", "gpio"),
+	AB8505_PIN_HOG("GPIO2_R5", in_pd),
+
+	/* Sysclkreq4 */
+	AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
+	AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
+	/* sysclkreq4 disable, mux in gpio configured in input pulldown */
+	AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
+	AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
+
+	AB8505_MUX_HOG("gpio10_d_1", "gpio"),
+	AB8505_PIN_HOG("GPIO10_B16", in_pd),
+
+	AB8505_MUX_HOG("gpio11_d_1", "gpio"),
+	AB8505_PIN_HOG("GPIO11_B17", in_pd),
+
+	AB8505_MUX_HOG("gpio13_d_1", "gpio"),
+	AB8505_PIN_HOG("GPIO13_D17", in_nopull),
+
+	AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
+	AB8505_PIN_HOG("GPIO14_C16", in_pd),
+
+	AB8505_MUX_HOG("adi2_d_1", "adi2"),
+	AB8505_PIN_HOG("GPIO17_P2", in_pd),
+	AB8505_PIN_HOG("GPIO18_N3", in_pd),
+	AB8505_PIN_HOG("GPIO19_T1", in_pd),
+	AB8505_PIN_HOG("GPIO20_P3", in_pd),
+
+	AB8505_MUX_HOG("gpio34_a_1", "gpio"),
+	AB8505_PIN_HOG("GPIO34_H14", in_pd),
+
+	AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
+	AB8505_PIN_HOG("GPIO40_J15", in_pd),
+	AB8505_PIN_HOG("GPIO41_J14", in_pd),
+
+	AB8505_MUX_HOG("gpio50_d_1", "gpio"),
+	AB8505_PIN_HOG("GPIO50_L4", in_nopull),
+
+	AB8505_MUX_HOG("resethw_d_1", "resethw"),
+	AB8505_PIN_HOG("GPIO52_D16", in_pd),
+
+	AB8505_MUX_HOG("service_d_1", "service"),
+	AB8505_PIN_HOG("GPIO53_D15", in_pd),
+};
+
 /* Pin control settings */
 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 	/*
@@ -816,6 +1068,12 @@ void __init mop500_pinmaps_init(void)
 	pinctrl_register_mappings(mop500_pinmap,
 				  ARRAY_SIZE(mop500_pinmap));
 	mop500_href_family_pinmaps_init();
+	if (machine_is_u8520())
+		pinctrl_register_mappings(ab8505_pinmap,
+					  ARRAY_SIZE(ab8505_pinmap));
+	else
+		pinctrl_register_mappings(ab8500_pinmap,
+					  ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init snowball_pinmaps_init(void)
@@ -826,6 +1084,8 @@ void __init snowball_pinmaps_init(void)
 				  ARRAY_SIZE(snowball_pinmap));
 	pinctrl_register_mappings(u8500_pinmap,
 				  ARRAY_SIZE(u8500_pinmap));
+	pinctrl_register_mappings(ab8500_pinmap,
+				  ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init hrefv60_pinmaps_init(void)
@@ -835,4 +1095,6 @@ void __init hrefv60_pinmaps_init(void)
 	pinctrl_register_mappings(hrefv60_pinmap,
 				  ARRAY_SIZE(hrefv60_pinmap));
 	mop500_href_family_pinmaps_init();
+	pinctrl_register_mappings(ab8500_pinmap,
+				  ARRAY_SIZE(ab8500_pinmap));
 }
-- 
1.7.11.3



From clbchenlibo.chen at huawei.com  Tue May 28 03:42:53 2013
From: clbchenlibo.chen at huawei.com (Libo Chen)
Date: Tue, 28 May 2013 15:42:53 +0800
Subject: [PATCH] module: use a macro instead of platform_driver_register
In-Reply-To: <20130525122240.GC3746@kroah.com>
References: <51A040D2.20708@huawei.com> <20130525122240.GC3746@kroah.com>
Message-ID: <51A45FFD.8050200@huawei.com>

On 2013/5/25 20:22, Greg KH wrote:
> On Sat, May 25, 2013 at 12:40:50PM +0800, Libo Chen wrote:
>>
>> I found a lot of mistakes using struct platform_driver without owner
>> so I make a macro instead of the function platform_driver_register.
>> It can set owner in it, then guys don`t care about module owner again.
>>
>> Signed-off-by: Libo Chen <libo.chen at huawei.com>
> 
> Nice job, that's the better way to fix this, I'll queue it up for 3.11.
> 

Thank Gu, Thomas, David and yours suggestions!

Regards

Libo

> thanks,
> 
> greg k-h
> 
> .
> 




From Ganesh.Kumar at harman.com  Tue May 28 03:48:33 2013
From: Ganesh.Kumar at harman.com (Kumar, Ganesh)
Date: Tue, 28 May 2013 02:48:33 -0500
Subject: VDSO for arm 32bit
In-Reply-To: <20899.25935.838288.45383@pilspetsen.it.uu.se>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
Message-ID: <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>

Hi Mikel,

Kumar, Ganesh writes:
 > Hi All,
 >
 > ? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is  > no support for vdso for arm 32 bit.
 > I'm planning to port it to arm 32 bit, is there any work under progress?
 > would like to understand why the support for arm 32 bit is not there, any idea?

> 32-bit ARM has a "kuser" page at a fixed virtual address, which exports a few critical routines to user-space.  With that, a vdso is mostly redundant.

  Thanks for the info, my main idea is to get the gettimeofday exported through the kuser helper,tried looking at the sources
but I could not find anything related to that seems done in the mainline kernel tree for arm cortex, am I missing something here?
I plan to do that if its not available yet, right now I've started with the kernel doc for the kuser, any pointers further
to get the gettimeofday up and running using the kuser, Thanks in advance for your time.

--GK


From dmitry.torokhov at gmail.com  Tue May 28 03:58:09 2013
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Tue, 28 May 2013 00:58:09 -0700
Subject: [PATCH v2] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <1369709258-14529-1-git-send-email-Baohua.Song@csr.com>
References: <1369709258-14529-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130528075808.GA19496@core.coreip.homeip.net>

Hi Barry,

On Tue, May 28, 2013 at 10:47:38AM +0800, Barry Song wrote:
> +	/*
> +	 * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
> +	 * to queue a SUSPEND APM event
> +	 */
> +	input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
> +	input_sync(pwrcdrv->input);
> +
> +	/*
> +	 * Todo: report KEY_POWER event for Android platforms, Android PowerManager
> +	 * will handle the suspend and powerdown/hibernation
> +	 */
> +
...

> +
> +	pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
> +	set_bit(KEY_POWER, pwrcdrv->input->keybit);

Why are we setting up KEY_POWER if we do not send this event?

Thanks.

-- 
Dmitry


From 21cnbao at gmail.com  Tue May 28 04:07:46 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 28 May 2013 16:07:46 +0800
Subject: [PATCH v2] input: sirfsoc_pwrc: add onkey input driver for CSR
 SiRFprimaII PWRC
In-Reply-To: <20130528075808.GA19496@core.coreip.homeip.net>
References: <1369709258-14529-1-git-send-email-Baohua.Song@csr.com>
 <20130528075808.GA19496@core.coreip.homeip.net>
Message-ID: <CAGsJ_4zY0+O6fP2bKLy__U_+-ZsWQXwZ8JXYMpRmtVe6zihfDQ@mail.gmail.com>

2013/5/28 Dmitry Torokhov <dmitry.torokhov at gmail.com>:
> Hi Barry,
>
> On Tue, May 28, 2013 at 10:47:38AM +0800, Barry Song wrote:
>> +     /*
>> +      * For a typical Linux system, we report KEY_SUSPEND to trigger apm-power.c
>> +      * to queue a SUSPEND APM event
>> +      */
>> +     input_event(pwrcdrv->input, EV_PWR, KEY_SUSPEND, 1);
>> +     input_sync(pwrcdrv->input);
>> +
>> +     /*
>> +      * Todo: report KEY_POWER event for Android platforms, Android PowerManager
>> +      * will handle the suspend and powerdown/hibernation
>> +      */
>> +
> ...
>
>> +
>> +     pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR) | BIT_MASK(EV_KEY);
>> +     set_bit(KEY_POWER, pwrcdrv->input->keybit);
>
> Why are we setting up KEY_POWER if we do not send this event?

For Android products, we send KEY_POWER to let Android PM trigger
SUSPEND. that is left to be done.

>
> Thanks.
>
> --
> Dmitry

-barry


From nicolas.ferre at atmel.com  Tue May 28 04:08:40 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 28 May 2013 10:08:40 +0200
Subject: [PATCH 3/3 v3] net/macb: Try to optimize struct macb layout
In-Reply-To: <AE90C24D6B3A694183C094C60CF0A2F6026B723A@saturn3.aculab.com>
References: <cover.1368608928.git.nicolas.ferre@atmel.com>
 <d0bc206ace3baaf681e111ba07c4d0b576839bb4.1368608928.git.nicolas.ferre@atmel.com>
 <AE90C24D6B3A694183C094C60CF0A2F6026B723A@saturn3.aculab.com>
Message-ID: <51A46608.2020906@atmel.com>

On 15/05/2013 11:37, David Laight :
>> From: Havard Skinnemoen <havard at skinnemoen.net>
>
>> Move the NAPI struct below that since it is used
>> from the interrupt handler. This field is also marked as
>> ___cacheline_aligned_in_smp.
>
> Is that a good idea if the cache line size is 256 bytes?
> Indeed is that ever sane - except for a few special structures
> that really need it, and are guaranteed to be allocated
> with that much alignment.

I do not know if that was really needed, it was a recommendation by Ben.
(previous email here:
https://patchwork.kernel.org/patch/1887101/
)

Anyway, it seems that this patch needs more work whereas the others of 
the series are not commented.

So maybe, I can resend patches 1, 2 for making this big enhancement go 
forward (as it is in review process for quite a long time...).
David, do you want me to resend or can you retrieve these v3 patches in 
patchwork?

Best regards,
-- 
Nicolas Ferre


From mingo at kernel.org  Tue May 28 04:19:10 2013
From: mingo at kernel.org (Ingo Molnar)
Date: Tue, 28 May 2013 10:19:10 +0200
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <20130523100409.GK18614@n2100.arm.linux.org.uk>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
Message-ID: <20130528081910.GA29557@gmail.com>


* Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> So, if you want to use this, then you should update the CONFIG_BUG text 
> to include a warning to this effect:
> 
>      Warning: if CONFIG_BUG is turned off, and control flow reaches
>      a BUG(), the system behaviour will be undefined.
> 
> so that people can make an informed choice about this, because at the
> moment:
> 
>           Disabling this option eliminates support for BUG and WARN, reducing
>           the size of your kernel image and potentially quietly ignoring
>           numerous fatal conditions. You should only consider disabling this
>           option for embedded systems with no facilities for reporting errors.
>           Just say Y.
> 
> will become completely misleading.  Turning this option off will _not_ 
> result in "quietly ignoring numerous fatal conditions".

I'm fine with adding your text as a clarification - but I think 'quietly 
ignoring fatal conditions' very much implies an undefined outcome if that 
unexpected condition does occur: the code might crash, it might corrupt 
memory or it might do some other unexpected thing.

There are many other places that do a BUG_ON() of a NULL pointer or so, or 
of a zero refcount, or a not held lock - and turning the BUG_ON() off 
makes the code unpredictable _anyway_ - even if the compiler does not 
notice an uninitialized variable.

So pretty much any weakening of BUG_ON() _will_ make the kernel more 
unpredictable.

> And I come back to one of my previous arguments - is it not better to 
> panic() if we hit one of these conditions so that the system can try to 
> do a panic-reboot rather than continue blindly into the unknown?

It will often continue blindly into the unknown even if the compiler is 
happy ...

The only difference is that it's "unpredictable" in a way not visible from 
the C code: the code won't necessarily fall through the BUG() when hitting 
that condition - although in practice it probably will.

So I think the same principle applies to it as to any other debugging 
code: it's fine to be able to turn debugging off. It's a performance 
versus kernel robustness/determinism trade-off.

Thanks,

	Ingo


From larsi at wh2.tu-dresden.de  Tue May 28 04:24:57 2013
From: larsi at wh2.tu-dresden.de (Lars Poeschel)
Date: Tue, 28 May 2013 10:24:57 +0200
Subject: [PATCH] dts: am33xx: Correct properties on gpmc node
Message-ID: <1369729497-11897-1-git-send-email-larsi@wh2.tu-dresden.de>

From: Lars Poeschel <poeschel at lemonage.de>

The gpmc driver is actually looking for "gpmc,num-cs" and
"gpmc,num-waitpins" properties in DT. The binding doc also states
this.
Correct the properties in the dts to provide the right values for the
gpmc driver.

Signed-off-by: Lars Poeschel <poeschel at lemonage.de>
---
 arch/arm/boot/dts/am33xx.dtsi |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b..8e1248f 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -409,8 +409,8 @@
 			ti,hwmods = "gpmc";
 			reg = <0x50000000 0x2000>;
 			interrupts = <100>;
-			num-cs = <7>;
-			num-waitpins = <2>;
+			gpmc,num-cs = <7>;
+			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
 			status = "disabled";
-- 
1.7.10.4



From prakash.pm at ti.com  Tue May 28 04:28:01 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 28 May 2013 13:58:01 +0530
Subject: [PATCH v2 0/5] ARM: davinci: fix UART clock enabling
Message-ID: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>

Patch series addresses below issues:
1) Do clk_get on dev_id when there is single clock for a module
2) Fix garbled UART log with DT kernel on da850-evm.
3) Cleanup of serila platform code.

Applies on top of v3.9-rc9 of Linus's.
Tested on da850-evm. Able to see proper bootup log and console on UART2.

Since v1:
Change names of platform data names appropriately.
Added 5/5: platform code cleanup.

Manjunathappa, Prakash (5):
  ARM: davinci: uart: move to devid based clk_get
  ARM: davinci: da850: override device name of UART in DT kernel
  ARM: davinci: da850: do not specify clock_frequency for UART DT node
  ARM: davinci: da8xx: remove da8xx_uart_clk_enable
  ARM: davinci: serial: platform code cleanup

 arch/arm/boot/dts/da850.dtsi                   |    3 -
 arch/arm/mach-davinci/board-da830-evm.c        |    6 +--
 arch/arm/mach-davinci/board-da850-evm.c        |    6 +--
 arch/arm/mach-davinci/board-dm355-evm.c        |    6 +--
 arch/arm/mach-davinci/board-dm355-leopard.c    |    6 +--
 arch/arm/mach-davinci/board-dm365-evm.c        |    6 +--
 arch/arm/mach-davinci/board-dm644x-evm.c       |    6 +--
 arch/arm/mach-davinci/board-dm646x-evm.c       |    6 +--
 arch/arm/mach-davinci/board-mityomapl138.c     |    6 +--
 arch/arm/mach-davinci/board-neuros-osd2.c      |    6 +--
 arch/arm/mach-davinci/board-omapl138-hawk.c    |    6 +--
 arch/arm/mach-davinci/board-sffsdr.c           |    7 +--
 arch/arm/mach-davinci/da830.c                  |    7 +--
 arch/arm/mach-davinci/da850.c                  |    7 +--
 arch/arm/mach-davinci/da8xx-dt.c               |   11 +----
 arch/arm/mach-davinci/devices-da8xx.c          |   41 +++++++++++++-----
 arch/arm/mach-davinci/devices-tnetv107x.c      |   36 +++++++++++-----
 arch/arm/mach-davinci/dm355.c                  |   48 ++++++++++++++-------
 arch/arm/mach-davinci/dm365.c                  |   36 ++++++++++------
 arch/arm/mach-davinci/dm644x.c                 |   48 ++++++++++++++-------
 arch/arm/mach-davinci/dm646x.c                 |   47 ++++++++++++++-------
 arch/arm/mach-davinci/include/mach/common.h    |    1 -
 arch/arm/mach-davinci/include/mach/da8xx.h     |    2 +-
 arch/arm/mach-davinci/include/mach/serial.h    |   14 ++++---
 arch/arm/mach-davinci/include/mach/tnetv107x.h |    3 +-
 arch/arm/mach-davinci/serial.c                 |   54 +++++++++---------------
 arch/arm/mach-davinci/tnetv107x.c              |    8 ++--
 27 files changed, 227 insertions(+), 206 deletions(-)

-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 28 04:28:02 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 28 May 2013 13:58:02 +0530
Subject: [PATCH v2 1/5] ARM: davinci: uart: move to devid based clk_get
In-Reply-To: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
References: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369729686-6595-2-git-send-email-prakash.pm@ti.com>

For modules having single clock, clk_get should be done with dev_id.
But current davinci implementation handles multiple instances
of the UART devices with single platform_device_register. Hence clk_get
is based on con_id rather than dev_id, this is not correct. Do
platform_device_register for each instance and clk_get on dev_id.

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
 arch/arm/mach-davinci/da830.c                  |    8 ++--
 arch/arm/mach-davinci/da850.c                  |    8 ++--
 arch/arm/mach-davinci/devices-da8xx.c          |   41 ++++++++++++++------
 arch/arm/mach-davinci/devices-tnetv107x.c      |   34 ++++++++++++-----
 arch/arm/mach-davinci/dm355.c                  |   49 ++++++++++++++++--------
 arch/arm/mach-davinci/dm365.c                  |   37 +++++++++++-------
 arch/arm/mach-davinci/dm644x.c                 |   49 ++++++++++++++++--------
 arch/arm/mach-davinci/dm646x.c                 |   48 ++++++++++++++++-------
 arch/arm/mach-davinci/include/mach/da8xx.h     |    2 +-
 arch/arm/mach-davinci/include/mach/serial.h    |    4 ++
 arch/arm/mach-davinci/include/mach/tnetv107x.h |    2 +-
 arch/arm/mach-davinci/serial.c                 |   19 ++++++---
 arch/arm/mach-davinci/tnetv107x.c              |    8 ++--
 13 files changed, 205 insertions(+), 104 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index abbaf02..a3ffd52 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -395,9 +395,9 @@ static struct clk_lookup da830_clks[] = {
 	CLK(NULL,		"tptc0",	&tptc0_clk),
 	CLK(NULL,		"tptc1",	&tptc1_clk),
 	CLK("da830-mmc.0",	NULL,		&mmcsd_clk),
-	CLK(NULL,		"uart0",	&uart0_clk),
-	CLK(NULL,		"uart1",	&uart1_clk),
-	CLK(NULL,		"uart2",	&uart2_clk),
+	CLK("serial8250.0",	NULL,		&uart0_clk),
+	CLK("serial8250.1",	NULL,		&uart1_clk),
+	CLK("serial8250.2",	NULL,		&uart2_clk),
 	CLK("spi_davinci.0",	NULL,		&spi0_clk),
 	CLK("spi_davinci.1",	NULL,		&spi1_clk),
 	CLK(NULL,		"ecap0",	&ecap0_clk),
@@ -1199,7 +1199,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 128,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
-	.serial_dev		= &da8xx_serial_device,
+	.serial_dev		= da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
 };
 
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4d69338..7ce691c 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -451,9 +451,9 @@ static struct clk_lookup da850_clks[] = {
 	CLK(NULL,		"tpcc1",	&tpcc1_clk),
 	CLK(NULL,		"tptc2",	&tptc2_clk),
 	CLK("pruss_uio",	"pruss",	&pruss_clk),
-	CLK(NULL,		"uart0",	&uart0_clk),
-	CLK(NULL,		"uart1",	&uart1_clk),
-	CLK(NULL,		"uart2",	&uart2_clk),
+	CLK("serial8250.0",	NULL,		&uart0_clk),
+	CLK("serial8250.1",	NULL,		&uart1_clk),
+	CLK("serial8250.2",	NULL,		&uart2_clk),
 	CLK(NULL,		"aintc",	&aintc_clk),
 	CLK(NULL,		"gpio",		&gpio_clk),
 	CLK("i2c_davinci.2",	NULL,		&i2c1_clk),
@@ -1301,7 +1301,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 144,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
-	.serial_dev		= &da8xx_serial_device,
+	.serial_dev		= da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
 	.sram_dma		= DA8XX_SHARED_RAM_BASE,
 	.sram_len		= SZ_128K,
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf57252..e243d97 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -67,7 +67,7 @@
 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
 
-static struct plat_serial8250_port da8xx_serial_pdata[] = {
+static struct plat_serial8250_port da8xx_serial0_pdata[] = {
 	{
 		.mapbase	= DA8XX_UART0_BASE,
 		.irq		= IRQ_DA8XX_UARTINT0,
@@ -75,7 +75,9 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
 					UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port da8xx_serial1_pdata[] = {
 	{
 		.mapbase	= DA8XX_UART1_BASE,
 		.irq		= IRQ_DA8XX_UARTINT1,
@@ -83,7 +85,9 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
 					UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port da8xx_serial2_pdata[] = {
 	{
 		.mapbase	= DA8XX_UART2_BASE,
 		.irq		= IRQ_DA8XX_UARTINT2,
@@ -91,18 +95,31 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
 					UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
-	{
-		.flags	= 0,
-	},
+	}
 };
 
-struct platform_device da8xx_serial_device = {
-	.name	= "serial8250",
-	.id	= PLAT8250_DEV_PLATFORM,
-	.dev	= {
-		.platform_data	= da8xx_serial_pdata,
+struct platform_device da8xx_serial_device[] = {
+	{
+		.name	= "serial8250",
+		.id	= PLAT8250_DEV_PLATFORM,
+		.dev	= {
+			.platform_data	= da8xx_serial0_pdata
+		}
 	},
+	{
+		.name	= "serial8250",
+		.id	= PLAT8250_DEV_PLATFORM1,
+		.dev	= {
+			.platform_data	= da8xx_serial1_pdata
+		}
+	},
+	{
+		.name	= "serial8250",
+		.id	= PLAT8250_DEV_PLATFORM2,
+		.dev	= {
+			.platform_data	= da8xx_serial2_pdata
+		}
+	}
 };
 
 static const s8 da8xx_queue_tc_mapping[][2] = {
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index cfb194d..35e5594 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -126,7 +126,7 @@ static struct platform_device edma_device = {
 	.dev.platform_data = tnetv107x_edma_info,
 };
 
-static struct plat_serial8250_port serial_data[] = {
+static struct plat_serial8250_port serial0_platform_data[] = {
 	{
 		.mapbase	= TNETV107X_UART0_BASE,
 		.irq		= IRQ_TNETV107X_UART0,
@@ -135,7 +135,9 @@ static struct plat_serial8250_port serial_data[] = {
 		.type		= PORT_AR7,
 		.iotype		= UPIO_MEM32,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port serial1_platform_data[] = {
 	{
 		.mapbase	= TNETV107X_UART1_BASE,
 		.irq		= IRQ_TNETV107X_UART1,
@@ -144,7 +146,9 @@ static struct plat_serial8250_port serial_data[] = {
 		.type		= PORT_AR7,
 		.iotype		= UPIO_MEM32,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port serial2_platform_data[] = {
 	{
 		.mapbase	= TNETV107X_UART2_BASE,
 		.irq		= IRQ_TNETV107X_UART2,
@@ -153,16 +157,26 @@ static struct plat_serial8250_port serial_data[] = {
 		.type		= PORT_AR7,
 		.iotype		= UPIO_MEM32,
 		.regshift	= 2,
+	}
+};
+
+
+struct platform_device tnetv107x_serial_device[] = {
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM,
+		.dev.platform_data	= serial0_platform_data
 	},
 	{
-		.flags	= 0,
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM1,
+		.dev.platform_data	= serial1_platform_data
 	},
-};
-
-struct platform_device tnetv107x_serial_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev.platform_data	= serial_data,
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM2,
+		.dev.platform_data	= serial2_platform_data
+	}
 };
 
 static struct resource mmc0_resources[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a11034a..a7ef0e3 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -357,9 +357,9 @@ static struct clk_lookup dm355_clks[] = {
 	CLK(NULL, "clkout3", &clkout3_clk),
 	CLK(NULL, "arm", &arm_clk),
 	CLK(NULL, "mjcp", &mjcp_clk),
-	CLK(NULL, "uart0", &uart0_clk),
-	CLK(NULL, "uart1", &uart1_clk),
-	CLK(NULL, "uart2", &uart2_clk),
+	CLK("serial8250.0", NULL, &uart0_clk),
+	CLK("serial8250.1", NULL, &uart1_clk),
+	CLK("serial8250.2", NULL, &uart2_clk),
 	CLK("i2c_davinci.1", NULL, &i2c_clk),
 	CLK("davinci-mcbsp.0", NULL, &asp0_clk),
 	CLK("davinci-mcbsp.1", NULL, &asp1_clk),
@@ -922,7 +922,7 @@ static struct davinci_timer_info dm355_timer_info = {
 	.clocksource_id	= T0_TOP,
 };
 
-static struct plat_serial8250_port dm355_serial_platform_data[] = {
+static struct plat_serial8250_port dm355_serial0_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART0_BASE,
 		.irq		= IRQ_UARTINT0,
@@ -930,7 +930,9 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm355_serial1_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART1_BASE,
 		.irq		= IRQ_UARTINT1,
@@ -938,7 +940,9 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm355_serial2_platform_data[] = {
 	{
 		.mapbase	= DM355_UART2_BASE,
 		.irq		= IRQ_DM355_UARTINT2,
@@ -946,18 +950,31 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
-	{
-		.flags		= 0
-	},
+	}
 };
 
-static struct platform_device dm355_serial_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev			= {
-		.platform_data	= dm355_serial_platform_data,
+static struct platform_device dm355_serial_device[] = {
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM,
+		.dev			= {
+			.platform_data	= dm355_serial0_platform_data
+		}
 	},
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM1,
+		.dev			= {
+			.platform_data	= dm355_serial1_platform_data
+		}
+	},
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM2,
+		.dev			= {
+			.platform_data	= dm355_serial2_platform_data
+		}
+	}
 };
 
 static struct davinci_soc_info davinci_soc_info_dm355 = {
@@ -981,7 +998,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
-	.serial_dev		= &dm355_serial_device,
+	.serial_dev		= dm355_serial_device,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 40fa4fe..abeac28 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -455,8 +455,8 @@ static struct clk_lookup dm365_clks[] = {
 	CLK("vpss", "master", &vpss_master_clk),
 	CLK("vpss", "slave", &vpss_slave_clk),
 	CLK(NULL, "arm", &arm_clk),
-	CLK(NULL, "uart0", &uart0_clk),
-	CLK(NULL, "uart1", &uart1_clk),
+	CLK("serial8250.0", NULL, &uart0_clk),
+	CLK("serial8250.1", NULL, &uart1_clk),
 	CLK("i2c_davinci.1", NULL, &i2c_clk),
 	CLK("da830-mmc.0", NULL, &mmcsd0_clk),
 	CLK("da830-mmc.1", NULL, &mmcsd1_clk),
@@ -1041,7 +1041,7 @@ static struct davinci_timer_info dm365_timer_info = {
 
 #define DM365_UART1_BASE	(IO_PHYS + 0x106000)
 
-static struct plat_serial8250_port dm365_serial_platform_data[] = {
+static struct plat_serial8250_port dm365_serial0_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART0_BASE,
 		.irq		= IRQ_UARTINT0,
@@ -1049,7 +1049,9 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm365_serial1_platform_data[] = {
 	{
 		.mapbase	= DM365_UART1_BASE,
 		.irq		= IRQ_UARTINT1,
@@ -1057,20 +1059,27 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
-	{
-		.flags		= 0
-	},
+	}
 };
 
-static struct platform_device dm365_serial_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev			= {
-		.platform_data	= dm365_serial_platform_data,
+static struct platform_device dm365_serial_device[] = {
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM,
+		.dev			= {
+			.platform_data	= dm365_serial0_platform_data
+		}
 	},
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM1,
+		.dev			= {
+			.platform_data	= dm365_serial1_platform_data
+		}
+	}
 };
 
+
 static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.io_desc		= dm365_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm365_io_desc),
@@ -1093,7 +1102,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM365_GPIO0,
 	.gpio_unbanked		= 8,	/* really 16 ... skip muxed GPIOs */
-	.serial_dev		= &dm365_serial_device,
+	.serial_dev		= dm365_serial_device,
 	.emac_pdata		= &dm365_emac_pdata,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4d37d3e..cc68266 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -303,9 +303,9 @@ static struct clk_lookup dm644x_clks[] = {
 	CLK("vpss", "master", &vpss_master_clk),
 	CLK("vpss", "slave", &vpss_slave_clk),
 	CLK(NULL, "arm", &arm_clk),
-	CLK(NULL, "uart0", &uart0_clk),
-	CLK(NULL, "uart1", &uart1_clk),
-	CLK(NULL, "uart2", &uart2_clk),
+	CLK("serial8250.0", NULL, &uart0_clk),
+	CLK("serial8250.1", NULL, &uart1_clk),
+	CLK("serial8250.2", NULL, &uart2_clk),
 	CLK("davinci_emac.1", NULL, &emac_clk),
 	CLK("i2c_davinci.1", NULL, &i2c_clk),
 	CLK("palm_bk3710", NULL, &ide_clk),
@@ -813,7 +813,7 @@ static struct davinci_timer_info dm644x_timer_info = {
 	.clocksource_id	= T0_TOP,
 };
 
-static struct plat_serial8250_port dm644x_serial_platform_data[] = {
+static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART0_BASE,
 		.irq		= IRQ_UARTINT0,
@@ -821,7 +821,9 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART1_BASE,
 		.irq		= IRQ_UARTINT1,
@@ -829,7 +831,9 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART2_BASE,
 		.irq		= IRQ_UARTINT2,
@@ -837,18 +841,31 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
-	},
-	{
-		.flags		= 0
-	},
+	}
 };
 
-static struct platform_device dm644x_serial_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev			= {
-		.platform_data	= dm644x_serial_platform_data,
+static struct platform_device dm644x_serial_device[] = {
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM,
+		.dev			= {
+			.platform_data	= dm644x_serial0_platform_data
+		}
 	},
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM1,
+		.dev			= {
+			.platform_data	= dm644x_serial1_platform_data
+		}
+	},
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM2,
+		.dev			= {
+			.platform_data	= dm644x_serial2_platform_data
+		}
+	}
 };
 
 static struct davinci_soc_info davinci_soc_info_dm644x = {
@@ -872,7 +889,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 71,
 	.gpio_irq		= IRQ_GPIOBNK0,
-	.serial_dev		= &dm644x_serial_device,
+	.serial_dev		= dm644x_serial_device,
 	.emac_pdata		= &dm644x_emac_pdata,
 	.sram_dma		= 0x00008000,
 	.sram_len		= SZ_16K,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index ac7b431..1fec246 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -342,9 +342,9 @@ static struct clk_lookup dm646x_clks[] = {
 	CLK(NULL, "edma_tc1", &edma_tc1_clk),
 	CLK(NULL, "edma_tc2", &edma_tc2_clk),
 	CLK(NULL, "edma_tc3", &edma_tc3_clk),
-	CLK(NULL, "uart0", &uart0_clk),
-	CLK(NULL, "uart1", &uart1_clk),
-	CLK(NULL, "uart2", &uart2_clk),
+	CLK("serial8250.0", NULL, &uart0_clk),
+	CLK("serial8250.1", NULL, &uart1_clk),
+	CLK("serial8250.2", NULL, &uart2_clk),
 	CLK("i2c_davinci.1", NULL, &i2c_clk),
 	CLK(NULL, "gpio", &gpio_clk),
 	CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
@@ -790,7 +790,7 @@ static struct davinci_timer_info dm646x_timer_info = {
 	.clocksource_id	= T0_TOP,
 };
 
-static struct plat_serial8250_port dm646x_serial_platform_data[] = {
+static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART0_BASE,
 		.irq		= IRQ_UARTINT0,
@@ -798,7 +798,9 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM32,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART1_BASE,
 		.irq		= IRQ_UARTINT1,
@@ -806,7 +808,9 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM32,
 		.regshift	= 2,
-	},
+	}
+};
+static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART2_BASE,
 		.irq		= IRQ_DM646X_UARTINT2,
@@ -814,19 +818,33 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM32,
 		.regshift	= 2,
+	}
+};
+
+static struct platform_device dm646x_serial_device[] = {
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM,
+		.dev			= {
+			.platform_data	= dm646x_serial0_platform_data
+		}
 	},
 	{
-		.flags		= 0
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM1,
+		.dev			= {
+			.platform_data	= dm646x_serial1_platform_data
+		}
 	},
+	{
+		.name			= "serial8250",
+		.id			= PLAT8250_DEV_PLATFORM2,
+		.dev			= {
+			.platform_data	= dm646x_serial2_platform_data
+		}
+	}
 };
 
-static struct platform_device dm646x_serial_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev			= {
-		.platform_data	= dm646x_serial_platform_data,
-	},
-};
 
 static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.io_desc		= dm646x_io_desc,
@@ -849,7 +867,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 43, /* Only 33 usable */
 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
-	.serial_dev		= &dm646x_serial_device,
+	.serial_dev		= dm646x_serial_device,
 	.emac_pdata		= &dm646x_emac_pdata,
 	.sram_dma		= 0x10010000,
 	.sram_len		= SZ_32K,
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9ea..71aa7d0 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -110,7 +110,7 @@ void da8xx_restart(char mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
-extern struct platform_device da8xx_serial_device;
+extern struct platform_device da8xx_serial_device[];
 extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 62ad300..34d9877 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -44,6 +44,10 @@ struct davinci_uart_config {
 
 extern int davinci_serial_init(struct davinci_uart_config *);
 extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
+extern struct platform_device dm365_serial_device[];
+extern struct platform_device dm355_serial_device[];
+extern struct platform_device dm644x_serial_device[];
+extern struct platform_device dm646x_serial_device[];
 #endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02..07948a5 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -49,7 +49,7 @@ struct tnetv107x_device_info {
 };
 
 extern struct platform_device tnetv107x_wdt_device;
-extern struct platform_device tnetv107x_serial_device;
+extern struct platform_device tnetv107x_serial_device[];
 
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index f262581..57e6150 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -76,7 +76,7 @@ int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
 	char name[16];
 	struct clk *clk;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct device *dev = &soc_info->serial_dev->dev;
+	struct device *dev = &soc_info->serial_dev[instance].dev;
 
 	sprintf(name, "uart%d", instance);
 	clk = clk_get(dev, name);
@@ -96,19 +96,25 @@ int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
 
 int __init davinci_serial_init(struct davinci_uart_config *info)
 {
-	int i, ret;
+	int i, ret = 0;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct device *dev = &soc_info->serial_dev->dev;
-	struct plat_serial8250_port *p = dev->platform_data;
+	struct device *dev;
+	struct plat_serial8250_port *p;
 
 	/*
 	 * Make sure the serial ports are muxed on at this point.
 	 * You have to mux them off in device drivers later on if not needed.
 	 */
-	for (i = 0; p->flags; i++, p++) {
+	for (i = 0; soc_info->serial_dev[i].dev.platform_data != NULL; i++) {
+		dev = &soc_info->serial_dev[i].dev;
+		p = dev->platform_data;
 		if (!(info->enabled_uarts & (1 << i)))
 			continue;
 
+		ret = platform_device_register(&soc_info->serial_dev[i]);
+		if (ret)
+			continue;
+
 		ret = davinci_serial_setup_clk(i, &p->uartclk);
 		if (ret)
 			continue;
@@ -125,6 +131,5 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 		if (p->membase && p->type != PORT_AR7)
 			davinci_serial_reset(p);
 	}
-
-	return platform_device_register(soc_info->serial_dev);
+	return ret;
 }
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d..d8a9516 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -263,7 +263,7 @@ static struct clk_lookup clks[] = {
 	CLK(NULL,		"clk_chipcfg",		&clk_chipcfg),
 	CLK("tnetv107x-ts.0",	NULL,			&clk_tsc),
 	CLK(NULL,		"clk_rom",		&clk_rom),
-	CLK(NULL,		"uart2",		&clk_uart2),
+	CLK("serial8250.2",     NULL,			&clk_uart2),
 	CLK(NULL,		"clk_pktsec",		&clk_pktsec),
 	CLK("tnetv107x-rng.0",	NULL,			&clk_rng),
 	CLK("tnetv107x-pka.0",	NULL,			&clk_pka),
@@ -273,8 +273,8 @@ static struct clk_lookup clks[] = {
 	CLK(NULL,		"clk_gpio",		&clk_gpio),
 	CLK(NULL,		"clk_mdio",		&clk_mdio),
 	CLK("dm6441-mmc.0",	NULL,			&clk_sdio0),
-	CLK(NULL,		"uart0",		&clk_uart0),
-	CLK(NULL,		"uart1",		&clk_uart1),
+	CLK("serial8250.0",	NULL,			&clk_uart0),
+	CLK("serial8250.1",	NULL,			&clk_uart1),
 	CLK(NULL,		"timer0",		&clk_timer0),
 	CLK(NULL,		"timer1",		&clk_timer1),
 	CLK("tnetv107x_wdt.0",	NULL,			&clk_wdt_arm),
@@ -756,7 +756,7 @@ static struct davinci_soc_info tnetv107x_soc_info = {
 	.gpio_type		= GPIO_TYPE_TNETV107X,
 	.gpio_num		= TNETV107X_N_GPIO,
 	.timer_info		= &timer_info,
-	.serial_dev		= &tnetv107x_serial_device,
+	.serial_dev		= tnetv107x_serial_device,
 };
 
 void __init tnetv107x_init(void)
-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 28 04:28:03 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 28 May 2013 13:58:03 +0530
Subject: [PATCH v2 2/5] ARM: davinci: da850: override device name of UART in
 DT kernel
In-Reply-To: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
References: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369729686-6595-3-git-send-email-prakash.pm@ti.com>

Populate OF_DEV_AUXDATA with desired device name so as to prevent
clk_get failures.

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
 arch/arm/mach-davinci/da8xx-dt.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 961aea8..e429945 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -47,6 +47,9 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL),
 	OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL),
 	OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL),
+	OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL),
+	OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL),
+	OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL),
 	{}
 };
 
-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 28 04:28:04 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 28 May 2013 13:58:04 +0530
Subject: [PATCH v2 3/5] ARM: davinci: da850: do not specify clock_frequency
 for UART DT node
In-Reply-To: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
References: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369729686-6595-4-git-send-email-prakash.pm@ti.com>

DT kernel on da850-evm comes up with garbled UART logs. This is because
of mismatch in actual module clock rate and rate specified(clock-frequency)
in DT blob. kernel should not assume or depend on bootloaders clock
configuration, instead let it find the clock rate at runtime.

Issue discussed here before arriving on this implementation:
"ARM: davinci: da850 evm: update clock rate for UART 1/2 DT nodes"
https://patchwork.kernel.org/patch/2162271/

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
 arch/arm/boot/dts/da850.dtsi |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2c88313..4d43046 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -129,7 +129,6 @@
 		serial0: serial at 1c42000 {
 			compatible = "ns16550a";
 			reg = <0x42000 0x100>;
-			clock-frequency = <150000000>;
 			reg-shift = <2>;
 			interrupts = <25>;
 			status = "disabled";
@@ -137,7 +136,6 @@
 		serial1: serial at 1d0c000 {
 			compatible = "ns16550a";
 			reg = <0x10c000 0x100>;
-			clock-frequency = <150000000>;
 			reg-shift = <2>;
 			interrupts = <53>;
 			status = "disabled";
@@ -145,7 +143,6 @@
 		serial2: serial at 1d0d000 {
 			compatible = "ns16550a";
 			reg = <0x10d000 0x100>;
-			clock-frequency = <150000000>;
 			reg-shift = <2>;
 			interrupts = <61>;
 			status = "disabled";
-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 28 04:28:05 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 28 May 2013 13:58:05 +0530
Subject: [PATCH v2 4/5] ARM: davinci: da8xx: remove da8xx_uart_clk_enable
In-Reply-To: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
References: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369729686-6595-5-git-send-email-prakash.pm@ti.com>

Serial clocks are enabled from of_platform_serial_setup:of_serial.c,
so remove davinci_serial_setup_clk from here.

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
 arch/arm/mach-davinci/da8xx-dt.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index e429945..9683cbd 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -20,13 +20,6 @@
 
 #define DA8XX_NUM_UARTS	3
 
-static void __init da8xx_uart_clk_enable(void)
-{
-	int i;
-	for (i = 0; i < DA8XX_NUM_UARTS; i++)
-		davinci_serial_setup_clk(i, NULL);
-}
-
 static struct of_device_id da8xx_irq_match[] __initdata = {
 	{ .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
 	{ }
@@ -60,7 +53,6 @@ static void __init da850_init_machine(void)
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     da850_auxdata_lookup, NULL);
 
-	da8xx_uart_clk_enable();
 }
 
 static const char *da850_boards_compat[] __initdata = {
-- 
1.7.4.1



From prakash.pm at ti.com  Tue May 28 04:28:06 2013
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 28 May 2013 13:58:06 +0530
Subject: [PATCH v2 5/5] ARM: davinci: serial: platform code cleanup
In-Reply-To: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
References: <1369729686-6595-1-git-send-email-prakash.pm@ti.com>
Message-ID: <1369729686-6595-6-git-send-email-prakash.pm@ti.com>

1) "struct davinci_uart_config" is introduced to specify
   UART ports brought out or enabled on the board. But
   none of the boards use them for that purpose, so clean
   it up.
2) Have pointer to platform device as a argument for
   davinci_serial_init(), no need of serial_dev in
   struct soc_info now.
3) No need of davinci_serial_setup_clk(), not called from
   multiple places, hence reduce function call overhead.

Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
Suggested-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/board-da830-evm.c        |    6 +---
 arch/arm/mach-davinci/board-da850-evm.c        |    6 +---
 arch/arm/mach-davinci/board-dm355-evm.c        |    6 +---
 arch/arm/mach-davinci/board-dm355-leopard.c    |    6 +---
 arch/arm/mach-davinci/board-dm365-evm.c        |    6 +---
 arch/arm/mach-davinci/board-dm644x-evm.c       |    6 +---
 arch/arm/mach-davinci/board-dm646x-evm.c       |    6 +---
 arch/arm/mach-davinci/board-mityomapl138.c     |    6 +---
 arch/arm/mach-davinci/board-neuros-osd2.c      |    6 +---
 arch/arm/mach-davinci/board-omapl138-hawk.c    |    6 +---
 arch/arm/mach-davinci/board-sffsdr.c           |    7 +---
 arch/arm/mach-davinci/da830.c                  |    1 -
 arch/arm/mach-davinci/da850.c                  |    1 -
 arch/arm/mach-davinci/devices-tnetv107x.c      |    2 +-
 arch/arm/mach-davinci/dm355.c                  |    3 +-
 arch/arm/mach-davinci/dm365.c                  |    3 +-
 arch/arm/mach-davinci/dm644x.c                 |    3 +-
 arch/arm/mach-davinci/dm646x.c                 |    3 +-
 arch/arm/mach-davinci/include/mach/common.h    |    1 -
 arch/arm/mach-davinci/include/mach/serial.h    |   10 ++---
 arch/arm/mach-davinci/include/mach/tnetv107x.h |    1 -
 arch/arm/mach-davinci/serial.c                 |   47 +++++++-----------------
 22 files changed, 35 insertions(+), 107 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 1332de8..c4bdc0a 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -185,10 +185,6 @@ static __init void da830_evm_usb_init(void)
 			   __func__, ret);
 }
 
-static struct davinci_uart_config da830_evm_uart_config __initdata = {
-	.enabled_uarts = 0x7,
-};
-
 static const short da830_evm_mcasp1_pins[] = {
 	DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
 	DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
@@ -630,7 +626,7 @@ static __init void da830_evm_init(void)
 		pr_warning("da830_evm_init: watchdog registration failed: %d\n",
 				ret);
 
-	davinci_serial_init(&da830_evm_uart_config);
+	davinci_serial_init(da8xx_serial_device);
 	i2c_register_board_info(1, da830_evm_i2c_devices,
 			ARRAY_SIZE(da830_evm_i2c_devices));
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 8a24b6c..9ac76ee 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -746,10 +746,6 @@ static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
 	.bus_delay	= 0,	/* usec */
 };
 
-static struct davinci_uart_config da850_evm_uart_config __initdata = {
-	.enabled_uarts = 0x7,
-};
-
 /* davinci da850 evm audio machine driver */
 static u8 da850_iis_serializer_direction[] = {
 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
@@ -1495,7 +1491,7 @@ static __init void da850_evm_init(void)
 				__func__, ret);
 	}
 
-	davinci_serial_init(&da850_evm_uart_config);
+	davinci_serial_init(da8xx_serial_device);
 
 	i2c_register_board_info(1, da850_evm_i2c_devices,
 			ARRAY_SIZE(da850_evm_i2c_devices));
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index c2a0a67..42b23a3 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -314,10 +314,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
 	&davinci_nand_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 static void __init dm355_evm_map_io(void)
 {
 	dm355_init();
@@ -393,7 +389,7 @@ static __init void dm355_evm_init(void)
 	platform_add_devices(davinci_evm_devices,
 			     ARRAY_SIZE(davinci_evm_devices));
 	evm_init_i2c();
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm355_serial_device);
 
 	/* NOTE:  NAND flash timings set by the UBL are slower than
 	 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index dff4ddc..d9eb1c9 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -172,10 +172,6 @@ static struct platform_device *davinci_leopard_devices[] __initdata = {
 	&davinci_nand_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 static void __init dm355_leopard_map_io(void)
 {
 	dm355_init();
@@ -251,7 +247,7 @@ static __init void dm355_leopard_init(void)
 	platform_add_devices(davinci_leopard_devices,
 			     ARRAY_SIZE(davinci_leopard_devices));
 	leopard_init_i2c();
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm355_serial_device);
 
 	/* NOTE:  NAND flash timings set by the UBL are slower than
 	 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index fd38c8d..5f1ec9d 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -719,10 +719,6 @@ fail:
 	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 }
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 static void __init dm365_evm_map_io(void)
 {
 	dm365_init();
@@ -749,7 +745,7 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
 static __init void dm365_evm_init(void)
 {
 	evm_init_i2c();
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm365_serial_device);
 
 	dm365evm_emac_configure();
 	dm365evm_mmc_configure();
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index a33686a..462812b 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -726,10 +726,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
 	&rtc_dev,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 static void __init
 davinci_evm_map_io(void)
 {
@@ -791,7 +787,7 @@ static __init void davinci_evm_init(void)
 	davinci_setup_mmc(0, &dm6446evm_mmc_config);
 	dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
 
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm644x_serial_device);
 	dm644x_init_asp(&dm644x_evm_snd_data);
 
 	/* irlml6401 switches over 1A, in under 8 msec */
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index fbb8e5a..734cc02 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -749,10 +749,6 @@ static void __init davinci_map_io(void)
 	cdce_clk_init();
 }
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 #define DM646X_EVM_PHY_ID		"davinci_mdio-0:01"
 /*
  * The following EDMA channels/slots are not being used by drivers (for
@@ -792,7 +788,7 @@ static __init void evm_init(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
 	evm_init_i2c();
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm646x_serial_device);
 	dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
 	dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
 
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 9549d53..cd0f587 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -434,10 +434,6 @@ static void __init mityomapl138_setup_nand(void)
 				 ARRAY_SIZE(mityomapl138_devices));
 }
 
-static struct davinci_uart_config mityomapl138_uart_config __initdata = {
-	.enabled_uarts = 0x7,
-};
-
 static const short mityomap_mii_pins[] = {
 	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
@@ -517,7 +513,7 @@ static void __init mityomapl138_init(void)
 	if (ret)
 		pr_warning("watchdog registration failed: %d\n", ret);
 
-	davinci_serial_init(&mityomapl138_uart_config);
+	davinci_serial_init(da8xx_serial_device);
 
 	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 	if (ret)
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 2bc112a..8e156e0 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -153,10 +153,6 @@ static struct platform_device *davinci_ntosd2_devices[] __initdata = {
 	&ntosd2_leds_dev,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 static void __init davinci_ntosd2_map_io(void)
 {
 	dm644x_init();
@@ -197,7 +193,7 @@ static __init void davinci_ntosd2_init(void)
 	platform_add_devices(davinci_ntosd2_devices,
 				ARRAY_SIZE(davinci_ntosd2_devices));
 
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm644x_serial_device);
 	dm644x_init_asp(&dm644x_ntosd2_snd_data);
 
 	soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index b8c20de..ab98c75 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -286,15 +286,11 @@ usb11_setup_oc_fail:
 	gpio_free(DA850_USB1_VBUS_PIN);
 }
 
-static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
-	.enabled_uarts = 0x7,
-};
-
 static __init void omapl138_hawk_init(void)
 {
 	int ret;
 
-	davinci_serial_init(&omapl138_hawk_uart_config);
+	davinci_serial_init(da8xx_serial_device);
 
 	omapl138_hawk_config_emac();
 
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 739be7e..96ca11b 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -44,6 +44,7 @@
 #include "davinci.h"
 
 #define SFFSDR_PHY_ID		"davinci_mdio-0:01"
+
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
 	/* U-Boot Environment: Block 0
 	 * UBL:                Block 1
@@ -125,10 +126,6 @@ static struct platform_device *davinci_sffsdr_devices[] __initdata = {
 	&davinci_sffsdr_nandflash_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-	.enabled_uarts = (1 << 0),
-};
-
 static void __init davinci_sffsdr_map_io(void)
 {
 	dm644x_init();
@@ -141,7 +138,7 @@ static __init void davinci_sffsdr_init(void)
 	platform_add_devices(davinci_sffsdr_devices,
 			     ARRAY_SIZE(davinci_sffsdr_devices));
 	sffsdr_init_i2c();
-	davinci_serial_init(&uart_config);
+	davinci_serial_init(dm644x_serial_device);
 	soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
 	davinci_setup_usb(0, 0); /* We support only peripheral mode. */
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index a3ffd52..111613b 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1199,7 +1199,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 128,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
-	.serial_dev		= da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
 };
 
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 7ce691c..b1d56e5 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1301,7 +1301,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 144,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
-	.serial_dev		= da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
 	.sram_dma		= DA8XX_SHARED_RAM_BASE,
 	.sram_len		= SZ_128K,
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 35e5594..549cfad 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -399,7 +399,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 	platform_device_register(&tsc_device);
 
 	if (info->serial_config)
-		davinci_serial_init(info->serial_config);
+		davinci_serial_init(tnetv107x_serial_device);
 
 	for (i = 0; i < 2; i++)
 		if (info->mmc_config[i]) {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a7ef0e3..006d5aa 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -953,7 +953,7 @@ static struct plat_serial8250_port dm355_serial2_platform_data[] = {
 	}
 };
 
-static struct platform_device dm355_serial_device[] = {
+struct platform_device dm355_serial_device[] = {
 	{
 		.name			= "serial8250",
 		.id			= PLAT8250_DEV_PLATFORM,
@@ -998,7 +998,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
-	.serial_dev		= dm355_serial_device,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index abeac28..a8c4c95 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1062,7 +1062,7 @@ static struct plat_serial8250_port dm365_serial1_platform_data[] = {
 	}
 };
 
-static struct platform_device dm365_serial_device[] = {
+struct platform_device dm365_serial_device[] = {
 	{
 		.name			= "serial8250",
 		.id			= PLAT8250_DEV_PLATFORM,
@@ -1102,7 +1102,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM365_GPIO0,
 	.gpio_unbanked		= 8,	/* really 16 ... skip muxed GPIOs */
-	.serial_dev		= dm365_serial_device,
 	.emac_pdata		= &dm365_emac_pdata,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index cc68266..f4da786 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -844,7 +844,7 @@ static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
 	}
 };
 
-static struct platform_device dm644x_serial_device[] = {
+struct platform_device dm644x_serial_device[] = {
 	{
 		.name			= "serial8250",
 		.id			= PLAT8250_DEV_PLATFORM,
@@ -889,7 +889,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 71,
 	.gpio_irq		= IRQ_GPIOBNK0,
-	.serial_dev		= dm644x_serial_device,
 	.emac_pdata		= &dm644x_emac_pdata,
 	.sram_dma		= 0x00008000,
 	.sram_len		= SZ_16K,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 1fec246..72cc683 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -821,7 +821,7 @@ static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
 	}
 };
 
-static struct platform_device dm646x_serial_device[] = {
+struct platform_device dm646x_serial_device[] = {
 	{
 		.name			= "serial8250",
 		.id			= PLAT8250_DEV_PLATFORM,
@@ -867,7 +867,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 43, /* Only 33 usable */
 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
-	.serial_dev		= dm646x_serial_device,
 	.emac_pdata		= &dm646x_emac_pdata,
 	.sram_dma		= 0x10010000,
 	.sram_len		= SZ_32K,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77..7f5a2e9 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -71,7 +71,6 @@ struct davinci_soc_info {
 	unsigned			gpio_unbanked;
 	struct davinci_gpio_controller	*gpio_ctlrs;
 	int				gpio_ctlrs_num;
-	struct platform_device		*serial_dev;
 	struct emac_platform_data	*emac_pdata;
 	dma_addr_t			sram_dma;
 	unsigned			sram_len;
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 34d9877..c7303d0 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,6 +15,8 @@
 
 #include <mach/hardware.h>
 
+#include <linux/platform_device.h>
+
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
@@ -37,13 +39,9 @@
 #define UART_DM646X_SCR_TX_WATERMARK	0x08
 
 #ifndef __ASSEMBLY__
-struct davinci_uart_config {
-	/* Bit field of UARTs present; bit 0 --> UART0 */
-	unsigned int enabled_uarts;
-};
 
-extern int davinci_serial_init(struct davinci_uart_config *);
-extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
+extern int davinci_serial_init(struct platform_device *);
+
 extern struct platform_device dm365_serial_device[];
 extern struct platform_device dm355_serial_device[];
 extern struct platform_device dm644x_serial_device[];
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 07948a5..c68c7a9 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -41,7 +41,6 @@
 #include <mach/serial.h>
 
 struct tnetv107x_device_info {
-	struct davinci_uart_config	*serial_config;
 	struct davinci_mmc_config	*mmc_config[2];  /* 2 controllers */
 	struct davinci_nand_pdata	*nand_config[4]; /* 4 chipsels */
 	struct matrix_keypad_platform_data *keypad_config;
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 57e6150..5e93a73 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -70,54 +70,35 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
 				 UART_DM646X_SCR_TX_WATERMARK);
 }
 
-/* Enable UART clock and obtain its rate */
-int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
-{
-	char name[16];
-	struct clk *clk;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct device *dev = &soc_info->serial_dev[instance].dev;
-
-	sprintf(name, "uart%d", instance);
-	clk = clk_get(dev, name);
-	if (IS_ERR(clk)) {
-		pr_err("%s:%d: failed to get UART%d clock\n",
-					__func__, __LINE__, instance);
-		return PTR_ERR(clk);
-	}
-
-	clk_prepare_enable(clk);
-
-	if (rate)
-		*rate = clk_get_rate(clk);
-
-	return 0;
-}
-
-int __init davinci_serial_init(struct davinci_uart_config *info)
+int __init davinci_serial_init(struct platform_device *serial_dev)
 {
 	int i, ret = 0;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	struct device *dev;
 	struct plat_serial8250_port *p;
+	struct clk *clk;
 
 	/*
 	 * Make sure the serial ports are muxed on at this point.
 	 * You have to mux them off in device drivers later on if not needed.
 	 */
-	for (i = 0; soc_info->serial_dev[i].dev.platform_data != NULL; i++) {
-		dev = &soc_info->serial_dev[i].dev;
+	for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
+		dev = &serial_dev[i].dev;
 		p = dev->platform_data;
-		if (!(info->enabled_uarts & (1 << i)))
-			continue;
 
-		ret = platform_device_register(&soc_info->serial_dev[i]);
+		ret = platform_device_register(&serial_dev[i]);
 		if (ret)
 			continue;
 
-		ret = davinci_serial_setup_clk(i, &p->uartclk);
-		if (ret)
+		clk = clk_get(dev, NULL);
+		if (IS_ERR(clk)) {
+			pr_err("%s:%d: failed to get UART%d clock\n",
+			       __func__, __LINE__, i);
 			continue;
+		}
+
+		clk_prepare_enable(clk);
+
+		p->uartclk = clk_get_rate(clk);
 
 		if (!p->membase && p->mapbase) {
 			p->membase = ioremap(p->mapbase, SZ_4K);
-- 
1.7.4.1



From florian.vaussard at epfl.ch  Tue May 28 04:41:20 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Tue, 28 May 2013 10:41:20 +0200
Subject: [PATCH v3 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <51A46DB0.5020508@epfl.ch>


On 05/27/2013 04:52 PM, Florian Vaussard wrote:
> Hello,
>
> Following a similar proposal by Stephen Warren for tegra [1], this series
> makes use of the C preprocessor when compiling OMAP DT files, and
> accomplishes some improvements to improve overall readability.
>

I realized that I should also address am* devices. I will wait for comments
on this version, then post a v4. Sorry for the noise.

Regards,

Florian


From steve.capper at linaro.org  Tue May 28 04:59:35 2013
From: steve.capper at linaro.org (Steve Capper)
Date: Tue, 28 May 2013 09:59:35 +0100
Subject: [PATCH v2 3/4] ARM: mm: HugeTLB support for LPAE systems.
In-Reply-To: <20130524110306.GC18272@arm.com>
References: <1369323080-9673-1-git-send-email-steve.capper@linaro.org>
 <1369323080-9673-4-git-send-email-steve.capper@linaro.org>
 <20130524110306.GC18272@arm.com>
Message-ID: <20130528085934.GA15590@linaro.org>

On Fri, May 22, 2013 at 12:03:06PM +0100, Catalin Marinas wrote:
> On Thu, May 23, 2013 at 04:31:19PM +0100, Steve Capper wrote:
> > From: Catalin Marinas <catalin.marinas at arm.com>
> > 
> > This patch adds support for hugetlbfs based on the x86 implementation.
> 
> Can we not share the x86 code as you are proposing for arm64 already?
>

Yes, we can. I didn't want one patch set dependent on another so opted to
make the ARMv7 one self-contained for now. I was planning on changing this
with a future patch.

Cheers,
-- 
Steve
 
> -- 
> Catalin


From weiyj.lk at gmail.com  Tue May 28 05:06:15 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Tue, 28 May 2013 17:06:15 +0800
Subject: [PATCH -next] dmaengine: ste_dma40: fix error return code in
 d40_probe()
Message-ID: <CAPgLHd-Mw4MQwS8=p9+ZBHHehH7B-Hs49BqiUMrq-aV_5M4pQQ@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

In many of the error handling case, the return value 'ret' not set
and 0 will be return from d40_probe() even if error, but we should
return a negative error code instead in those error handling case.
This patch fixed them, and also removed useless variable 'err'.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 drivers/dma/ste_dma40.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 71bf4ec..cbf9c62 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3474,7 +3474,6 @@ failure:
 
 static int __init d40_probe(struct platform_device *pdev)
 {
-	int err;
 	int ret = -ENOENT;
 	struct d40_base *base;
 	struct resource *res = NULL;
@@ -3576,6 +3575,7 @@ static int __init d40_probe(struct platform_device *pdev)
 		if (IS_ERR(base->lcpa_regulator)) {
 			d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
 			base->lcpa_regulator = NULL;
+			ret = PTR_ERR(base->lcpa_regulator);
 			goto failure;
 		}
 
@@ -3590,13 +3590,13 @@ static int __init d40_probe(struct platform_device *pdev)
 	}
 
 	base->initialized = true;
-	err = d40_dmaengine_init(base, num_reserved_chans);
-	if (err)
+	ret = d40_dmaengine_init(base, num_reserved_chans);
+	if (ret)
 		goto failure;
 
 	base->dev->dma_parms = &base->dma_parms;
-	err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
-	if (err) {
+	ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
+	if (ret) {
 		d40_err(&pdev->dev, "Failed to set dma max seg size\n");
 		goto failure;
 	}



From weiyj.lk at gmail.com  Tue May 28 05:07:54 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Tue, 28 May 2013 17:07:54 +0800
Subject: [PATCH -next] dmaengine: ste_dma40: add missing iounmap() on error in
 d40_probe()
Message-ID: <CAPgLHd9kMzZ_ZY6zm0MZ+P6dHq73i_GdCsxhpUOt-V9nf08tWA@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Add the missing iounmap() before return from d40_probe()
in the error handling case.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 drivers/dma/ste_dma40.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 71bf4ec..018c2f7 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3612,6 +3612,8 @@ failure:
 			kmem_cache_destroy(base->desc_slab);
 		if (base->virtbase)
 			iounmap(base->virtbase);
+		if (base->lcpa_base)
+			iounmap(base->lcpa_base);
 
 		if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
 			iounmap(base->lcla_pool.base);



From lee.jones at linaro.org  Tue May 28 05:21:33 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 28 May 2013 10:21:33 +0100
Subject: [PATCH] ARM: ux500: add ABx500 pinctrl tables
In-Reply-To: <1369726413-18676-1-git-send-email-linus.walleij@stericsson.com>
References: <1369726413-18676-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130528092133.GE22683@gmail.com>

On Tue, 28 May 2013, Linus Walleij wrote:

> From: Patrice Chotard <patrice.chotard at st.com>
> 
> This adds pin control tables for the ABx500 (AB8500 and
> AB8505) PMIC, which also happens to act as a multimedia
> pin expander on the ux500 platforms.
> 
> Cc: Lee Jones <lee.jones at linaro.org>
> Signed-off-by: Patrice Chotard <patrice.chotard at st.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/mach-ux500/board-mop500-pins.c | 262 ++++++++++++++++++++++++++++++++

Patch looks good to me. I don't see anything untoward:

Acked-by: Lee Jones <lee.jones at linaro.org>

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Tue May 28 05:23:13 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 28 May 2013 10:23:13 +0100
Subject: VDSO for arm 32bit
In-Reply-To: <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
Message-ID: <20130528092313.GA10474@mudshark.cambridge.arm.com>

On Tue, May 28, 2013 at 08:48:33AM +0100, Kumar, Ganesh wrote:
> Hi Mikel,
> 
> Kumar, Ganesh writes:
>  > Hi All,
>  >
>  > ? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is  > no support for vdso for arm 32 bit.
>  > I'm planning to port it to arm 32 bit, is there any work under progress?
>  > would like to understand why the support for arm 32 bit is not there, any idea?
> 
> > 32-bit ARM has a "kuser" page at a fixed virtual address, which exports a few critical routines to user-space.  With that, a vdso is mostly redundant.
> 
>   Thanks for the info, my main idea is to get the gettimeofday exported through the kuser helper,tried looking at the sources
> but I could not find anything related to that seems done in the mainline kernel tree for arm cortex, am I missing something here?
> I plan to do that if its not available yet, right now I've started with the kernel doc for the kuser, any pointers further
> to get the gettimeofday up and running using the kuser, Thanks in advance for your time.

Be careful here. I had a crack at a gtod implementation for the vectors page
in the past, but decided to drop it because it quickly became a maintenance
nightmare. Since the layout of the vectors page must be fixed (as userspace
jumps to the absolute addresses for the helpers), having large, complicated
functions (which gtod does become as you quickly start using the stack to
store all of the shared state with the kernel) means that you can quickly
back yourself into a corner where the layout of the code cannot change
without breaking the ABI.

On top of that, new clock types are added more often than you might think
(not to mention bug fixes in the implementation itself), and you end up in
a horrible situation where you'd end up deprecating one implementation and
adding gettimeofday2 or something equally nasty at a different offset.

Maybe this can be solved by adding loads of padding between the different
functions and hoping for the best, but I think a better solution would be to
try and add something which is actually a vdso but preserves the function
offsets of the current helpers, thus preserving the ABI. That could then
replace the vectors page and newer C libraries could make use of the vdso
functionality. Of course, that's a lot more work and people might have
objections to the approach.

Finally, I assume you're only interested in the co-processor backed
architected timers for this? I know some people were toying with exposing
memory-mapped timers to userspace, but that really scares me.

Will


From lee.jones at linaro.org  Tue May 28 05:28:41 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 28 May 2013 10:28:41 +0100
Subject: [GIT PULL] ux500 DMA40 device tree migration base
In-Reply-To: <20130528031320.GD13532@quad.lixom.net>
References: <CACRpkdZjr=48_GJxsoYgK7DFUqLs10x4o9yky3MzNR7vh24ogA@mail.gmail.com>
 <20130528031320.GD13532@quad.lixom.net>
Message-ID: <20130528092841.GG22683@gmail.com>

On Mon, 27 May 2013, Olof Johansson wrote:

> On Thu, May 23, 2013 at 09:34:22PM +0200, Linus Walleij wrote:
> > Hi ARM SoC folks,
> > 
> > here is a patch set that Lee has been chiseling out recently. I've
> > accumulated it in my ux500 tree and piled ACKs on the first 36
> > patches of the patch set. Basically that includes ACKs from
> > subsystem maintainers Vinod Koul and Herbert Xu for affected
> > parts.
> > 
> > We need to get this into Linux-next to proceed with further
> > migration on top of it. All have been circulated on the lists for
> > a while.
> > 
> > Please pull this into an apropriate ARM SoC branch for v3.11!
> > 
> > If we can get ACKs for the rest of the patches in Lee's set these
> > will arrive on top of this base as soon as they are ready.
> > 
> > Yours,
> > Linus Walleij
> > 
> > The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> > 
> >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
> > tags/ux500-dma40-for-arm-soc
> 
> Thanks, pulled into next/drivers.
> 
> I see the conversions have been made the brute-force way instead of keeping
> backwards compatibility and cleaning up drivers before removing no longer
> needed board code. That should be fine, as long as you don't introduce too
> crazy dependencies (and conflicts) in the code you're talking about adding on
> top. 

It's not as bad as you make it sound. The platform devices which we
converted over were either already converted (mmci, amba-pl011), not
used (crypt, hash, musb) or broken (mop500-asoc). So it really should
be no big deal.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Tue May 28 05:38:15 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 28 May 2013 10:38:15 +0100
Subject: [PATCH 7/7] Documentation: Update binding for Nomadik and DBx5x
 based platforms
In-Reply-To: <CACRpkdYyZZSy4VgFc+Uo=5iAF++EPmHM0U2pHcLdkDZc=Xb_sQ@mail.gmail.com>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdYyZZSy4VgFc+Uo=5iAF++EPmHM0U2pHcLdkDZc=Xb_sQ@mail.gmail.com>
Message-ID: <20130528093815.GH22683@gmail.com>

> >  Required properties:
> > -- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
> > -              "stericsson,nmk-pinctrl-stn8815"
> > +- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
> > +              "stericsson,stn8815-pinctrl"
> 
> OK...
> 
> >         pinctrl at 80157000 {
> > -               compatible = "stericsson,nmk-pinctrl";
> > +               compatible = "stericsson,u8500-pinctrl";
> 
> This does not look like a supported compatible string?

Do you still think this, or did you change you mind?

If so, what makes you think it? How does it differ from:

compatible = "arm,cortex-a9-twd-timer";
compatible = "arm,rtc-pl031";
compatible = "stericsson,db8500-gpio",
compatible = "stericsson,db8500-musb",
compatible = "stericsson,db8500-dma40",
compatible = "stericsson,db8500-prcmu";
compatible = "stericsson,db8500-prcmu-timer-4";
compatible = "stericsson,db8500-thermal";
compatible = "stericsson,db8500-prcmu-regulator";



-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From jacmet at sunsite.dk  Tue May 28 05:50:40 2013
From: jacmet at sunsite.dk (Peter Korsgaard)
Date: Tue, 28 May 2013 11:50:40 +0200
Subject: [PATCH] dts: am33xx: Correct properties on gpmc node
In-Reply-To: <1369729497-11897-1-git-send-email-larsi@wh2.tu-dresden.de> (Lars
 Poeschel's message of "Tue, 28 May 2013 10:24:57 +0200")
References: <1369729497-11897-1-git-send-email-larsi@wh2.tu-dresden.de>
Message-ID: <87mwrfbfgv.fsf@dell.be.48ers.dk>

>>>>> "Lars" == Lars Poeschel <larsi at wh2.tu-dresden.de> writes:

 Lars> From: Lars Poeschel <poeschel at lemonage.de>
 Lars> The gpmc driver is actually looking for "gpmc,num-cs" and
 Lars> "gpmc,num-waitpins" properties in DT. The binding doc also states
 Lars> this.
 Lars> Correct the properties in the dts to provide the right values for the
 Lars> gpmc driver.

 Lars> Signed-off-by: Lars Poeschel <poeschel at lemonage.de>

Acked-by: Peter Korsgaard <jacmet at sunsite.dk>

-- 
Bye, Peter Korsgaard


From padma.v at samsung.com  Tue May 28 05:54:01 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 15:24:01 +0530
Subject: [PATCH V2] ARM: dts: Correct the base address of pinctrl_3 on
 Exynos5250
Message-ID: <1369734841-9900-1-git-send-email-padma.v@samsung.com>

This patch corrects the base address of pinctrl_3 on Exynos5250
platform.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
Changes since V1:
	- Added platform name in the subject line.

 arch/arm/boot/dts/exynos5250-pinctrl.dtsi |    2 +-
 arch/arm/boot/dts/exynos5250.dtsi         |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb..ded558b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -763,7 +763,7 @@
 		};
 	};
 
-	pinctrl at 03680000 {
+	pinctrl at 03860000 {
 		gpz: gpz {
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 7154e3d..e9bfd13 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -169,9 +169,9 @@
 		interrupts = <0 50 0>;
 	};
 
-	pinctrl_3: pinctrl at 03680000 {
+	pinctrl_3: pinctrl at 03860000 {
 		compatible = "samsung,exynos5250-pinctrl";
-		reg = <0x0368000 0x1000>;
+		reg = <0x03860000 0x1000>;
 		interrupts = <0 47 0>;
 	};
 
-- 
1.7.4.4



From viresh.kumar at linaro.org  Tue May 28 05:55:16 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Tue, 28 May 2013 15:25:16 +0530
Subject: [PATCH 3/8] ARM: SPEAr: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-4-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
 <1369665166-13049-4-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <CAKohpo=dVM_gd31h3sG0d0_hKcCfaHLtwfF3RXL453bE9K+L2A@mail.gmail.com>

On 27 May 2013 20:02, Sanjay Singh Rawat <sanjay.rawat at linaro.org> wrote:
> use cpu_do_idle for entering the wfi mode.
>
> Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
> ---
>  arch/arm/mach-spear/hotplug.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-spear/hotplug.c b/arch/arm/mach-spear/hotplug.c
> index d97749c..6dbd3dc 100644
> --- a/arch/arm/mach-spear/hotplug.c
> +++ b/arch/arm/mach-spear/hotplug.c
> @@ -55,7 +55,8 @@ static inline void cpu_leave_lowpower(void)
>  static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
>  {
>         for (;;) {
> -               wfi();
> +               /* enter WFI mode */
> +               cpu_do_idle();
>
>                 if (pen_release == cpu) {

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>


From catalin.marinas at arm.com  Tue May 28 05:55:28 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 28 May 2013 10:55:28 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
Message-ID: <20130528095528.GA14329@arm.com>

On Sat, May 25, 2013 at 04:53:19AM +0100, Nicolas Pitre wrote:
> On Thu, 23 May 2013, Catalin Marinas wrote:
> 
> > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > twice. I don't think we should remove the cache flushing in
> > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > don't work together).
> 
> VIVT and highmem do work together.  Highmem for ARM was in fact 
> developed on such a platform.

Thanks for confirming. Do you remember why kunmap() doesn't (need to)
flush the cache alias (for VIVT)? Or if it does, where?

-- 
Catalin


From b35083 at freescale.com  Tue May 28 05:12:23 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:12:23 +0800
Subject: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts support
In-Reply-To: <1369732343-2982-1-git-send-email-b35083@freescale.com>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
Message-ID: <1369732343-2982-5-git-send-email-b35083@freescale.com>

Add initial Freescale Vybrid VF610 Tower board support
with uart and fec enabled.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  Follow internal suggestions to name the soc name as VF610.
  Remove node of QuadSPI, I2C, SAI, and sound until driver accepted.
v3:
  Split DTS support to SoC and board patches.
  Sort node by alphabet order of labels.

 arch/arm/boot/dts/Makefile      |  3 ++-
 arch/arm/boot/dts/vf610-twr.dts | 57 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/vf610-twr.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ca3f3fc..2042803 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -126,7 +126,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
 	imx6q-sbc6x.dtb \
-	imx6sl-evk.dtb
+	imx6sl-evk.dtb \
+	vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx23-olinuxino.dtb \
 	imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
new file mode 100644
index 0000000..b3905f5
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+	model = "VF610 Tower Board";
+	compatible = "fsl,vf610-twr", "fsl,vf610";
+
+	chosen {
+		bootargs = "console=ttyLP1,115200";
+	};
+
+	memory {
+		reg = <0x80000000 0x8000000>;
+	};
+
+	clocks {
+		audio_ext {
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
+		enet_ext {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
+};
+
+&fec0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec0_1>;
+	status = "okay";
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1_1>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
-- 
1.8.0




From b35083 at freescale.com  Tue May 28 05:12:20 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:12:20 +0800
Subject: [PATCH v4 1/4] ARM: imx: add VF610 clock support
In-Reply-To: <1369732343-2982-1-git-send-email-b35083@freescale.com>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
Message-ID: <1369732343-2982-2-git-send-email-b35083@freescale.com>

Add clock support for Vybrid VF610. It uses dtc macro support to
define all clock IDs in vf610-clock.h to keep clock IDs coherence
between kernel and DT.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  Follow internal suggestions to name the soc name as VF610.
  Use common of_clk_init() call to initialize clocks.
v3:
  Split one big arch support patch to small patches.
  Use DTC macro support to define these clock IDs.
  Remove unused #include header lines.
  Name clocks close to reference manual.
v2:
  Add more clks definitions.

 .../devicetree/bindings/clock/vf610-clock.txt      |  26 ++
 arch/arm/mach-imx/clk-vf610.c                      | 319 +++++++++++++++++++++
 include/dt-bindings/clock/vf610-clock.h            | 163 +++++++++++
 3 files changed, 508 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/vf610-clock.txt
 create mode 100644 arch/arm/mach-imx/clk-vf610.c
 create mode 100644 include/dt-bindings/clock/vf610-clock.h

diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
new file mode 100644
index 0000000..c80863d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt
@@ -0,0 +1,26 @@
+* Clock bindings for Freescale Vybrid VF610 SOC
+
+Required properties:
+- compatible: Should be "fsl,vf610-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
+for the full list of VF610 clock IDs.
+
+Examples:
+
+clks: ccm at 4006b000 {
+	compatible = "fsl,vf610-ccm";
+	reg = <0x4006b000 0x1000>;
+	#clock-cells = <1>;
+};
+
+uart1: serial at 40028000 {
+	compatible = "fsl,vf610-uart";
+	reg = <0x40028000 0x1000>;
+	interrupts = <0 62 0x04>;
+	clocks = <&clks VF610_CLK_UART1>;
+	clock-names = "ipg";
+};
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
new file mode 100644
index 0000000..d617c0b
--- /dev/null
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <dt-bindings/clock/vf610-clock.h>
+
+#include "clk.h"
+
+#define CCM_CCR			(ccm_base + 0x00)
+#define CCM_CSR			(ccm_base + 0x04)
+#define CCM_CCSR		(ccm_base + 0x08)
+#define CCM_CACRR		(ccm_base + 0x0c)
+#define CCM_CSCMR1		(ccm_base + 0x10)
+#define CCM_CSCDR1		(ccm_base + 0x14)
+#define CCM_CSCDR2		(ccm_base + 0x18)
+#define CCM_CSCDR3		(ccm_base + 0x1c)
+#define CCM_CSCMR2		(ccm_base + 0x20)
+#define CCM_CSCDR4		(ccm_base + 0x24)
+#define CCM_CLPCR		(ccm_base + 0x2c)
+#define CCM_CISR		(ccm_base + 0x30)
+#define CCM_CIMR		(ccm_base + 0x34)
+#define CCM_CGPR		(ccm_base + 0x3c)
+#define CCM_CCGR0		(ccm_base + 0x40)
+#define CCM_CCGR1		(ccm_base + 0x44)
+#define CCM_CCGR2		(ccm_base + 0x48)
+#define CCM_CCGR3		(ccm_base + 0x4c)
+#define CCM_CCGR4		(ccm_base + 0x50)
+#define CCM_CCGR5		(ccm_base + 0x54)
+#define CCM_CCGR6		(ccm_base + 0x58)
+#define CCM_CCGR7		(ccm_base + 0x5c)
+#define CCM_CCGR8		(ccm_base + 0x60)
+#define CCM_CCGR9		(ccm_base + 0x64)
+#define CCM_CCGR10		(ccm_base + 0x68)
+#define CCM_CCGR11		(ccm_base + 0x6c)
+#define CCM_CMEOR0		(ccm_base + 0x70)
+#define CCM_CMEOR1		(ccm_base + 0x74)
+#define CCM_CMEOR2		(ccm_base + 0x78)
+#define CCM_CMEOR3		(ccm_base + 0x7c)
+#define CCM_CMEOR4		(ccm_base + 0x80)
+#define CCM_CMEOR5		(ccm_base + 0x84)
+#define CCM_CPPDSR		(ccm_base + 0x88)
+#define CCM_CCOWR		(ccm_base + 0x8c)
+#define CCM_CCPGR0		(ccm_base + 0x90)
+#define CCM_CCPGR1		(ccm_base + 0x94)
+#define CCM_CCPGR2		(ccm_base + 0x98)
+#define CCM_CCPGR3		(ccm_base + 0x9c)
+
+#define CCM_CCGRx_CGn(n)	((n) * 2)
+
+#define PFD_PLL1_BASE		(anatop_base + 0x2b0)
+#define PFD_PLL2_BASE		(anatop_base + 0x100)
+#define PFD_PLL3_BASE		(anatop_base + 0xf0)
+
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+
+/* sources for multiplexer clocks, this is used multiple times */
+static const char const *fast_sels[]	= { "firc", "fxosc", };
+static const char const *slow_sels[]	= { "sirc_32k", "sxosc", };
+static const char const *pll1_sels[]	= { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char const *pll2_sels[]	= { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char const *sys_sels[]	= { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char const *ddr_sels[]	= { "pll2_pfd2", "sys_sel", };
+static const char const *rmii_sels[]	= { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char const *enet_ts_sels[]	= { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char const *esai_sels[]	= { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *sai_sels[]	= { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *nfc_sels[]	= { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char const *qspi_sels[]	= { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char const *esdhc_sels[]	= { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char const *dcu_sels[]	= { "pll1_pfd2", "pll3_main", };
+static const char const *gpu_sels[]	= { "pll2_pfd2", "pll3_pfd2", };
+static const char const *vadc_sels[]	= { "pll6_main_div", "pll3_main_div", "pll3_main", };
+/* FTM counter clock source, not module clock */
+static const char const *ftm_ext_sels[]	= {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char const *ftm_fix_sels[]	= { "sxosc", "ipg_bus", };
+
+static struct clk_div_table pll4_main_div_table[] = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 6 },
+	{ .val = 3, .div = 8 },
+	{ .val = 4, .div = 10 },
+	{ .val = 5, .div = 12 },
+	{ .val = 6, .div = 14 },
+	{ .val = 7, .div = 16 },
+	{ }
+};
+
+static struct clk *clk[VF610_CLK_END];
+static struct clk_onecell_data clk_data;
+
+static void __init vf610_clocks_init(struct device_node *ccm_node)
+{
+	struct device_node *np;
+
+	clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+	clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
+	clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
+	clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
+
+	clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
+	clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
+	clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
+	clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+
+	clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
+	anatop_base = of_iomap(np, 0);
+	BUG_ON(!anatop_base);
+
+	np = ccm_node;
+	ccm_base = of_iomap(np, 0);
+	BUG_ON(!ccm_base);
+
+	clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
+	clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
+
+	clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
+	clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
+	clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
+	clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
+	clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
+
+	clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
+	clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
+	clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
+	clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
+	clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
+
+	clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
+	clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
+	clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
+	clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
+	clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
+
+	clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
+	/* Enet pll: fixed 50Mhz */
+	clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
+	/* pll6: default 960Mhz */
+	clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+	clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
+	clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
+	clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
+	clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
+	clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
+	clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
+	clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
+
+	clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
+	clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
+	clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+
+	clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
+	clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+
+	clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
+	clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
+	clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
+	clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
+	clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
+	clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
+
+	clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
+	clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
+	clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
+	clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
+	clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
+	clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
+
+	clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
+	clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+	clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
+	clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
+	clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
+	clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
+
+	clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
+
+	clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
+	clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
+	clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
+
+	clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
+	clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
+
+	clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
+	clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
+	clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
+	clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
+
+	clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
+
+	clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
+	clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
+	clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
+	clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
+
+	clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
+	clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
+	clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
+	clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
+
+	/*
+	 * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
+	 * selectable clock sources, both use a common enable bit
+	 * in CCM_CSCDR1, selecting "dummy" clock as parent of
+	 * "ftm0_ext_fix" make it serve only for enable/disable.
+	 */
+	clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
+	clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
+	clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
+	clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
+	clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
+	clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
+	clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
+	clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
+	clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
+	clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
+	clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
+	clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
+
+	/* ftm(n)_clk are FTM module operation clock */
+	clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
+	clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
+
+	clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
+	clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
+	clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
+	clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
+	clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
+	clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
+	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+
+	clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
+	clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
+	clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
+	clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
+
+	clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
+	clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
+	clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
+	clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
+
+	clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
+	clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
+	clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
+	clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
+
+	clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
+	clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
+	clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
+	clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
+
+	clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
+	clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
+	clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
+	clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
+
+	clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
+	clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
+	clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
+	clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
+	clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
+
+	clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
+	clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
+	clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
+
+	clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
+	clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
+	clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
+	clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
+	clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
+
+	clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
+	clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
+	clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
+	clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
+
+	clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
+
+	clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
+	clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+
+	clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
+	clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
+	clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
+	clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
+
+	clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
+	clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
+	clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
+	clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
+
+	clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
+	clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
+	clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
+	clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
+
+	/* Add the clocks to provider list */
+	clk_data.clks = clk;
+	clk_data.clk_num = ARRAY_SIZE(clk);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 0000000..15e997f
--- /dev/null
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_VF610_H
+#define __DT_BINDINGS_CLOCK_VF610_H
+
+#define VF610_CLK_DUMMY			0
+#define VF610_CLK_SIRC_128K		1
+#define VF610_CLK_SIRC_32K		2
+#define VF610_CLK_FIRC			3
+#define VF610_CLK_SXOSC			4
+#define VF610_CLK_FXOSC			5
+#define VF610_CLK_FXOSC_HALF		6
+#define VF610_CLK_SLOW_CLK_SEL		7
+#define VF610_CLK_FASK_CLK_SEL		8
+#define VF610_CLK_AUDIO_EXT		9
+#define VF610_CLK_ENET_EXT		10
+#define VF610_CLK_PLL1_MAIN		11
+#define VF610_CLK_PLL1_PFD1		12
+#define VF610_CLK_PLL1_PFD2		13
+#define VF610_CLK_PLL1_PFD3		14
+#define VF610_CLK_PLL1_PFD4		15
+#define VF610_CLK_PLL2_MAIN		16
+#define VF610_CLK_PLL2_PFD1		17
+#define VF610_CLK_PLL2_PFD2		18
+#define VF610_CLK_PLL2_PFD3		19
+#define VF610_CLK_PLL2_PFD4		20
+#define VF610_CLK_PLL3_MAIN		21
+#define VF610_CLK_PLL3_PFD1		22
+#define VF610_CLK_PLL3_PFD2		23
+#define VF610_CLK_PLL3_PFD3		24
+#define VF610_CLK_PLL3_PFD4		25
+#define VF610_CLK_PLL4_MAIN		26
+#define VF610_CLK_PLL5_MAIN		27
+#define VF610_CLK_PLL6_MAIN		28
+#define VF610_CLK_PLL3_MAIN_DIV		29
+#define VF610_CLK_PLL4_MAIN_DIV		30
+#define VF610_CLK_PLL6_MAIN_DIV		31
+#define VF610_CLK_PLL1_PFD_SEL		32
+#define VF610_CLK_PLL2_PFD_SEL		33
+#define VF610_CLK_SYS_SEL		34
+#define VF610_CLK_DDR_SEL		35
+#define VF610_CLK_SYS_BUS		36
+#define VF610_CLK_PLATFORM_BUS		37
+#define VF610_CLK_IPG_BUS		38
+#define VF610_CLK_UART0			39
+#define VF610_CLK_UART1			40
+#define VF610_CLK_UART2			41
+#define VF610_CLK_UART3			42
+#define VF610_CLK_UART4			43
+#define VF610_CLK_UART5			44
+#define VF610_CLK_PIT			45
+#define VF610_CLK_I2C0			46
+#define VF610_CLK_I2C1			47
+#define VF610_CLK_I2C2			48
+#define VF610_CLK_I2C3			49
+#define VF610_CLK_FTM0_EXT_SEL		50
+#define VF610_CLK_FTM0_FIX_SEL		51
+#define VF610_CLK_FTM0_EXT_FIX_EN	52
+#define VF610_CLK_FTM1_EXT_SEL		53
+#define VF610_CLK_FTM1_FIX_SEL		54
+#define VF610_CLK_FTM1_EXT_FIX_EN	55
+#define VF610_CLK_FTM2_EXT_SEL		56
+#define VF610_CLK_FTM2_FIX_SEL		57
+#define VF610_CLK_FTM2_EXT_FIX_EN	58
+#define VF610_CLK_FTM3_EXT_SEL		59
+#define VF610_CLK_FTM3_FIX_SEL		60
+#define VF610_CLK_FTM3_EXT_FIX_EN	61
+#define VF610_CLK_FTM0			62
+#define VF610_CLK_FTM1			63
+#define VF610_CLK_FTM2			64
+#define VF610_CLK_FTM3			65
+#define VF610_CLK_ENET_50M		66
+#define VF610_CLK_ENET_25M		67
+#define VF610_CLK_ENET_SEL		68
+#define VF610_CLK_ENET			69
+#define VF610_CLK_ENET_TS_SEL		70
+#define VF610_CLK_ENET_TS		71
+#define VF610_CLK_DSPI0			72
+#define VF610_CLK_DSPI1			73
+#define VF610_CLK_DSPI2			74
+#define VF610_CLK_DSPI3			75
+#define VF610_CLK_WDT			76
+#define VF610_CLK_ESDHC0_SEL		77
+#define VF610_CLK_ESDHC0_EN		78
+#define VF610_CLK_ESDHC0_DIV		79
+#define VF610_CLK_ESDHC0		80
+#define VF610_CLK_ESDHC1_SEL		81
+#define VF610_CLK_ESDHC1_EN		82
+#define VF610_CLK_ESDHC1_DIV		83
+#define VF610_CLK_ESDHC1		84
+#define VF610_CLK_DCU0_SEL		85
+#define VF610_CLK_DCU0_EN		86
+#define VF610_CLK_DCU0_DIV		87
+#define VF610_CLK_DCU0			88
+#define VF610_CLK_DCU1_SEL		89
+#define VF610_CLK_DCU1_EN		90
+#define VF610_CLK_DCU1_DIV		91
+#define VF610_CLK_DCU1			92
+#define VF610_CLK_ESAI_SEL		93
+#define VF610_CLK_ESAI_EN		94
+#define VF610_CLK_ESAI_DIV		95
+#define VF610_CLK_ESAI			96
+#define VF610_CLK_SAI0_SEL		97
+#define VF610_CLK_SAI0_EN		98
+#define VF610_CLK_SAI0_DIV		99
+#define VF610_CLK_SAI0			100
+#define VF610_CLK_SAI1_SEL		101
+#define VF610_CLK_SAI1_EN		102
+#define VF610_CLK_SAI1_DIV		103
+#define VF610_CLK_SAI1			104
+#define VF610_CLK_SAI2_SEL		105
+#define VF610_CLK_SAI2_EN		106
+#define VF610_CLK_SAI2_DIV		107
+#define VF610_CLK_SAI2			108
+#define VF610_CLK_SAI3_SEL		109
+#define VF610_CLK_SAI3_EN		110
+#define VF610_CLK_SAI3_DIV		111
+#define VF610_CLK_SAI3			112
+#define VF610_CLK_USBC0			113
+#define VF610_CLK_USBC1			114
+#define VF610_CLK_QSPI0_SEL		115
+#define VF610_CLK_QSPI0_EN		116
+#define VF610_CLK_QSPI0_X4_DIV		117
+#define VF610_CLK_QSPI0_X2_DIV		118
+#define VF610_CLK_QSPI0_X1_DIV		119
+#define VF610_CLK_QSPI1_SEL		120
+#define VF610_CLK_QSPI1_EN		121
+#define VF610_CLK_QSPI1_X4_DIV		122
+#define VF610_CLK_QSPI1_X2_DIV		123
+#define VF610_CLK_QSPI1_X1_DIV		124
+#define VF610_CLK_QSPI0			125
+#define VF610_CLK_QSPI1			126
+#define VF610_CLK_NFC_SEL		127
+#define VF610_CLK_NFC_EN		128
+#define VF610_CLK_NFC_PRE_DIV		129
+#define VF610_CLK_NFC_FRAC_DIV		130
+#define VF610_CLK_NFC_INV		131
+#define VF610_CLK_NFC			132
+#define VF610_CLK_VADC_SEL		133
+#define VF610_CLK_VADC_EN		134
+#define VF610_CLK_VADC_DIV		135
+#define VF610_CLK_VADC_DIV_HALF		136
+#define VF610_CLK_VADC			137
+#define VF610_CLK_ADC0			138
+#define VF610_CLK_ADC1			139
+#define VF610_CLK_DAC0			140
+#define VF610_CLK_DAC1			141
+#define VF610_CLK_FLEXCAN0		142
+#define VF610_CLK_FLEXCAN1		143
+#define VF610_CLK_ASRC			144
+#define VF610_CLK_GPU_SEL		145
+#define VF610_CLK_GPU_EN		146
+#define VF610_CLK_GPU2D			147
+#define VF610_CLK_END			148
+
+#endif /* __DT_BINDINGS_CLOCK_VF610_H */
-- 
1.8.0




From b35083 at freescale.com  Tue May 28 05:12:22 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:12:22 +0800
Subject: [PATCH v4 3/4] ARM: dts: add SoC level device tree source for VF610
In-Reply-To: <1369732343-2982-1-git-send-email-b35083@freescale.com>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
Message-ID: <1369732343-2982-4-git-send-email-b35083@freescale.com>

Add SoC level device tree source for Freescale Vybrid VF610.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  Follow internal suggestions to name the soc name as VF610.
  Name lpuart device compatible string to "fsl,vf610-lpuart".
  Remove "fsl,mvf-fec" compatible string.
v3:
  Define mvf600 pinfunc ID as <mux_reg input_reg mux_mode input_val>.
  Clean up code.
v2:
  Add pinctrl support based on IMX new pinctrl framework.

 arch/arm/boot/dts/vf610-pinfunc.h | 810 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/vf610.dtsi      | 464 ++++++++++++++++++++++
 2 files changed, 1274 insertions(+)
 create mode 100644 arch/arm/boot/dts/vf610-pinfunc.h
 create mode 100644 arch/arm/boot/dts/vf610.dtsi

diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h
new file mode 100644
index 0000000..1ee681f
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-pinfunc.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_VF610_PINFUNC_H
+#define __DTS_VF610_PINFUNC_H
+
+/*
+ * The pin function ID for VF610 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+
+#define ALT0	0x0
+#define ALT1	0x1
+#define ALT2	0x2
+#define ALT3	0x3
+#define ALT4	0x4
+#define ALT5	0x5
+#define ALT6	0x6
+#define ALT7	0x7
+
+
+#define VF610_PAD_PTA6__GPIO_0			0x000 0x000 ALT0 0x0
+#define VF610_PAD_PTA6__RMII_CLKOUT		0x000 0x000 ALT1 0x0
+#define VF610_PAD_PTA6__RMII_CLKIN		0x000 0x2F0 ALT2 0x0
+#define VF610_PAD_PTA6__DCU1_TCON11		0x000 0x000 ALT4 0x0
+#define VF610_PAD_PTA6__DCU1_R2			0x000 0x000 ALT7 0x0
+#define VF610_PAD_PTA8__GPIO_1			0x004 0x000 ALT0 0x0
+#define VF610_PAD_PTA8__TCLK			0x004 0x000 ALT1 0x0
+#define VF610_PAD_PTA8__DCU0_R0			0x004 0x000 ALT4 0x0
+#define VF610_PAD_PTA8__MLB_CLK			0x004 0x354 ALT7 0x0
+#define VF610_PAD_PTA9__GPIO_2			0x008 0x000 ALT0 0x0
+#define VF610_PAD_PTA9__TDI			0x008 0x000 ALT1 0x0
+#define VF610_PAD_PTA9__RMII_CLKOUT		0x008 0x000 ALT2 0x0
+#define VF610_PAD_PTA9__RMII_CLKIN		0x008 0x2F0 ALT3 0x1
+#define VF610_PAD_PTA9__DCU0_R1			0x008 0x000 ALT4 0x0
+#define VF610_PAD_PTA9__WDOG_B			0x008 0x000 ALT6 0x0
+#define VF610_PAD_PTA10__GPIO_3			0x00C 0x000 ALT0 0x0
+#define VF610_PAD_PTA10__TDO			0x00C 0x000 ALT1 0x0
+#define VF610_PAD_PTA10__EXT_AUDIO_MCLK		0x00C 0x2EC ALT2 0x0
+#define VF610_PAD_PTA10__DCU0_G0		0x00C 0x000 ALT4 0x0
+#define VF610_PAD_PTA10__ENET_TS_CLKIN		0x00C 0x2F4 ALT6 0x0
+#define VF610_PAD_PTA10__MLB_SIGNAL		0x00C 0x35C ALT7 0x0
+#define VF610_PAD_PTA11__GPIO_4			0x010 0x000 ALT0 0x0
+#define VF610_PAD_PTA11__TMS			0x010 0x000 ALT1 0x0
+#define VF610_PAD_PTA11__DCU0_G1		0x010 0x000 ALT4 0x0
+#define VF610_PAD_PTA11__MLB_DATA		0x010 0x358 ALT7 0x0
+#define VF610_PAD_PTA12__GPIO_5			0x014 0x000 ALT0 0x0
+#define VF610_PAD_PTA12__TRACECK		0x014 0x000 ALT1 0x0
+#define VF610_PAD_PTA12__EXT_AUDIO_MCLK		0x014 0x2EC ALT2 0x1
+#define VF610_PAD_PTA12__VIU_DATA13		0x014 0x000 ALT6 0x0
+#define VF610_PAD_PTA12__I2C0_SCL		0x014 0x33C ALT7 0x0
+#define VF610_PAD_PTA16__GPIO_6			0x018 0x000 ALT0 0x0
+#define VF610_PAD_PTA16__TRACED0		0x018 0x000 ALT1 0x0
+#define VF610_PAD_PTA16__USB0_VBUS_EN		0x018 0x000 ALT2 0x0
+#define VF610_PAD_PTA16__ADC1_SE0		0x018 0x000 ALT3 0x0
+#define VF610_PAD_PTA16__LCD29			0x018 0x000 ALT4 0x0
+#define VF610_PAD_PTA16__SAI2_TX_BCLK		0x018 0x370 ALT5 0x0
+#define VF610_PAD_PTA16__VIU_DATA14		0x018 0x000 ALT6 0x0
+#define VF610_PAD_PTA16__I2C0_SDA		0x018 0x340 ALT7 0x0
+#define VF610_PAD_PTA17__GPIO_7			0x01C 0x000 ALT0 0x0
+#define VF610_PAD_PTA17__TRACED1		0x01C 0x000 ALT1 0x0
+#define VF610_PAD_PTA17__USB0_VBUS_OC		0x01C 0x000 ALT2 0x0
+#define VF610_PAD_PTA17__ADC1_SE1		0x01C 0x000 ALT3 0x0
+#define VF610_PAD_PTA17__LCD30			0x01C 0x000 ALT4 0x0
+#define VF610_PAD_PTA17__USB0_SOF_PULSE		0x01C 0x000 ALT5 0x0
+#define VF610_PAD_PTA17__VIU_DATA15		0x01C 0x000 ALT6 0x0
+#define VF610_PAD_PTA17__I2C1_SCL		0x01C 0x344 ALT7 0x0
+#define VF610_PAD_PTA18__GPIO_8			0x020 0x000 ALT0 0x0
+#define VF610_PAD_PTA18__TRACED2		0x020 0x000 ALT1 0x0
+#define VF610_PAD_PTA18__ADC0_SE0		0x020 0x000 ALT2 0x0
+#define VF610_PAD_PTA18__FTM1_QD_PHA		0x020 0x334 ALT3 0x0
+#define VF610_PAD_PTA18__LCD31			0x020 0x000 ALT4 0x0
+#define VF610_PAD_PTA18__SAI2_TX_DATA		0x020 0x000 ALT5 0x0
+#define VF610_PAD_PTA18__VIU_DATA16		0x020 0x000 ALT6 0x0
+#define VF610_PAD_PTA18__I2C1_SDA		0x020 0x348 ALT7 0x0
+#define VF610_PAD_PTA19__GPIO_9			0x024 0x000 ALT0 0x0
+#define VF610_PAD_PTA19__TRACED3		0x024 0x000 ALT1 0x0
+#define VF610_PAD_PTA19__ADC0_SE1		0x024 0x000 ALT2 0x0
+#define VF610_PAD_PTA19__FTM1_QD_PHB		0x024 0x338 ALT3 0x0
+#define VF610_PAD_PTA19__LCD32			0x024 0x000 ALT4 0x0
+#define VF610_PAD_PTA19__SAI2_TX_SYNC		0x024 0x000 ALT5 0x0
+#define VF610_PAD_PTA19__VIU_DATA17		0x024 0x000 ALT6 0x0
+#define VF610_PAD_PTA19__QSPI1_A_QSCK		0x024 0x374 ALT7 0x0
+#define VF610_PAD_PTA20__GPIO_10		0x028 0x000 ALT0 0x0
+#define VF610_PAD_PTA20__TRACED4		0x028 0x000 ALT1 0x0
+#define VF610_PAD_PTA20__LCD33			0x028 0x000 ALT4 0x0
+#define VF610_PAD_PTA20__UART3_TX		0x028 0x394 ALT6 0x0
+#define VF610_PAD_PTA20__DCU1_HSYNC		0x028 0x000 ALT7 0x0
+#define VF610_PAD_PTA21__GPIO_11		0x02C 0x000 ALT0 0x0
+#define VF610_PAD_PTA21__TRACED5		0x02C 0x000 ALT1 0x0
+#define VF610_PAD_PTA21__SAI2_RX_BCLK		0x02C 0x364 ALT5 0x0
+#define VF610_PAD_PTA21__UART3_RX		0x02C 0x390 ALT6 0x0
+#define VF610_PAD_PTA21__DCU1_VSYNC		0x02C 0x000 ALT7 0x0
+#define VF610_PAD_PTA22__GPIO_12		0x030 0x000 ALT0 0x0
+#define VF610_PAD_PTA22__TRACED6		0x030 0x000 ALT1 0x0
+#define VF610_PAD_PTA22__SAI2_RX_DATA		0x030 0x368 ALT5 0x0
+#define VF610_PAD_PTA22__I2C2_SCL		0x030 0x34C ALT6 0x0
+#define VF610_PAD_PTA22__DCU1_TAG		0x030 0x000 ALT7 0x0
+#define VF610_PAD_PTA23__GPIO_13		0x034 0x000 ALT0 0x0
+#define VF610_PAD_PTA23__TRACED7		0x034 0x000 ALT1 0x0
+#define VF610_PAD_PTA23__SAI2_RX_SYNC		0x034 0x36C ALT5 0x0
+#define VF610_PAD_PTA23__I2C2_SDA		0x034 0x350 ALT6 0x0
+#define VF610_PAD_PTA23__DCU1_DE		0x034 0x000 ALT7 0x0
+#define VF610_PAD_PTA24__GPIO_14		0x038 0x000 ALT0 0x0
+#define VF610_PAD_PTA24__TRACED8		0x038 0x000 ALT1 0x0
+#define VF610_PAD_PTA24__USB1_VBUS_EN		0x038 0x000 ALT2 0x0
+#define VF610_PAD_PTA24__ESDHC1_CLK		0x038 0x000 ALT5 0x0
+#define VF610_PAD_PTA24__DCU1_TCON4		0x038 0x000 ALT6 0x0
+#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL	0x038 0x000 ALT7 0x0
+#define VF610_PAD_PTA25__GPIO_15		0x03C 0x000 ALT0 0x0
+#define VF610_PAD_PTA25__TRACED9		0x03C 0x000 ALT1 0x0
+#define VF610_PAD_PTA25__USB1_VBUS_OC		0x03C 0x000 ALT2 0x0
+#define VF610_PAD_PTA25__ESDHC1_CMD		0x03C 0x000 ALT5 0x0
+#define VF610_PAD_PTA25__DCU1_TCON5		0x03C 0x000 ALT6 0x0
+#define VF610_PAD_PTA26__GPIO_16		0x040 0x000 ALT0 0x0
+#define VF610_PAD_PTA26__TRACED10		0x040 0x000 ALT1 0x0
+#define VF610_PAD_PTA26__SAI3_TX_BCLK		0x040 0x000 ALT2 0x0
+#define VF610_PAD_PTA26__ESDHC1_DAT0		0x040 0x000 ALT5 0x0
+#define VF610_PAD_PTA26__DCU1_TCON6		0x040 0x000 ALT6 0x0
+#define VF610_PAD_PTA27__GPIO_17		0x044 0x000 ALT0 0x0
+#define VF610_PAD_PTA27__TRACED11		0x044 0x000 ALT1 0x0
+#define VF610_PAD_PTA27__SAI3_RX_BCLK		0x044 0x000 ALT2 0x0
+#define VF610_PAD_PTA27__ESDHC1_DAT1		0x044 0x000 ALT5 0x0
+#define VF610_PAD_PTA27__DCU1_TCON7		0x044 0x000 ALT6 0x0
+#define VF610_PAD_PTA28__GPIO_18		0x048 0x000 ALT0 0x0
+#define VF610_PAD_PTA28__TRACED12		0x048 0x000 ALT1 0x0
+#define VF610_PAD_PTA28__SAI3_RX_DATA		0x048 0x000 ALT2 0x0
+#define VF610_PAD_PTA28__ENET1_1588_TMR0	0x048 0x000 ALT3 0x0
+#define VF610_PAD_PTA28__UART4_TX		0x048 0x000 ALT4 0x0
+#define VF610_PAD_PTA28__ESDHC1_DATA2		0x048 0x000 ALT5 0x0
+#define VF610_PAD_PTA28__DCU1_TCON8		0x048 0x000 ALT6 0x0
+#define VF610_PAD_PTA29__GPIO_19		0x04C 0x000 ALT0 0x0
+#define VF610_PAD_PTA29__TRACED13		0x04C 0x000 ALT1 0x0
+#define VF610_PAD_PTA29__SAI3_TX_DATA		0x04C 0x000 ALT2 0x0
+#define VF610_PAD_PTA29__ENET1_1588_TMR1	0x04C 0x000 ALT3 0x0
+#define VF610_PAD_PTA29__UART4_RX		0x04C 0x000 ALT4 0x0
+#define VF610_PAD_PTA29__ESDHC1_DAT3		0x04C 0x000 ALT5 0x0
+#define VF610_PAD_PTA29__DCU1_TCON9		0x04C 0x000 ALT6 0x0
+#define VF610_PAD_PTA30__GPIO_20		0x050 0x000 ALT0 0x0
+#define VF610_PAD_PTA30__TRACED14		0x050 0x000 ALT1 0x0
+#define VF610_PAD_PTA30__SAI3_RX_SYNC		0x050 0x000 ALT2 0x0
+#define VF610_PAD_PTA30__ENET1_1588_TMR2	0x050 0x000 ALT3 0x0
+#define VF610_PAD_PTA30__UART4_RTS		0x050 0x000 ALT4 0x0
+#define VF610_PAD_PTA30__I2C3_SCL		0x050 0x000 ALT5 0x0
+#define VF610_PAD_PTA30__UART3_TX		0x050 0x394 ALT7 0x1
+#define VF610_PAD_PTA31__GPIO_21		0x054 0x000 ALT0 0x0
+#define VF610_PAD_PTA31__TRACED15		0x054 0x000 ALT1 0x0
+#define VF610_PAD_PTA31__SAI3_TX_SYNC		0x054 0x000 ALT2 0x0
+#define VF610_PAD_PTA31__ENET1_1588_TMR3	0x054 0x000 ALT3 0x0
+#define VF610_PAD_PTA31__UART4_CTS		0x054 0x000 ALT4 0x0
+#define VF610_PAD_PTA31__I2C3_SDA		0x054 0x000 ALT5 0x0
+#define VF610_PAD_PTA31__UART3_RX		0x054 0x390 ALT7 0x1
+#define VF610_PAD_PTB0__GPIO_22			0x058 0x000 ALT0 0x0
+#define VF610_PAD_PTB0__FTM0_CH0		0x058 0x000 ALT1 0x0
+#define VF610_PAD_PTB0__ADC0_SE2		0x058 0x000 ALT2 0x0
+#define VF610_PAD_PTB0__TRACE_CTL		0x058 0x000 ALT3 0x0
+#define VF610_PAD_PTB0__LCD34			0x058 0x000 ALT4 0x0
+#define VF610_PAD_PTB0__SAI2_RX_BCLK		0x058 0x364 ALT5 0x1
+#define VF610_PAD_PTB0__VIU_DATA18		0x058 0x000 ALT6 0x0
+#define VF610_PAD_PTB0__QSPI1_A_QPCS0		0x058 0x000 ALT7 0x0
+#define VF610_PAD_PTB1__GPIO_23			0x05C 0x000 ALT0 0x0
+#define VF610_PAD_PTB1__FTM0_CH1		0x05C 0x000 ALT1 0x0
+#define VF610_PAD_PTB1__ADC0_SE3		0x05C 0x000 ALT2 0x0
+#define VF610_PAD_PTB1__SRC_RCON30		0x05C 0x000 ALT3 0x0
+#define VF610_PAD_PTB1__LCD35			0x05C 0x000 ALT4 0x0
+#define VF610_PAD_PTB1__SAI2_RX_DATA		0x05C 0x368 ALT5 0x1
+#define VF610_PAD_PTB1__VIU_DATA19		0x05C 0x000 ALT6 0x0
+#define VF610_PAD_PTB1__QSPI1_A_DATA3		0x05C 0x000 ALT7 0x0
+#define VF610_PAD_PTB2__GPIO_24			0x060 0x000 ALT0 0x0
+#define VF610_PAD_PTB2__FTM0_CH2		0x060 0x000 ALT1 0x0
+#define VF610_PAD_PTB2__ADC1_SE2		0x060 0x000 ALT2 0x0
+#define VF610_PAD_PTB2__SRC_RCON31		0x060 0x000 ALT3 0x0
+#define VF610_PAD_PTB2__LCD36			0x060 0x000 ALT4 0x0
+#define VF610_PAD_PTB2__SAI2_RX_SYNC		0x060 0x36C ALT5 0x1
+#define VF610_PAD_PTB2__VIDEO_IN0_DATA20	0x060 0x000 ALT6 0x0
+#define VF610_PAD_PTB2__QSPI1_A_DATA2		0x060 0x000 ALT7 0x0
+#define VF610_PAD_PTB3__GPIO_25			0x064 0x000 ALT0 0x0
+#define VF610_PAD_PTB3__FTM0_CH3		0x064 0x000 ALT1 0x0
+#define VF610_PAD_PTB3__ADC1_SE3		0x064 0x000 ALT2 0x0
+#define VF610_PAD_PTB3__PDB_EXTRIG		0x064 0x000 ALT3 0x0
+#define VF610_PAD_PTB3__LCD37			0x064 0x000 ALT4 0x0
+#define VF610_PAD_PTB3__VIU_DATA21		0x064 0x000 ALT6 0x0
+#define VF610_PAD_PTB3__QSPI1_A_DATA1		0x064 0x000 ALT7 0x0
+#define VF610_PAD_PTB4__GPIO_26			0x068 0x000 ALT0 0x0
+#define VF610_PAD_PTB4__FTM0_CH4		0x068 0x000 ALT1 0x0
+#define VF610_PAD_PTB4__UART1_TX		0x068 0x380 ALT2 0x0
+#define VF610_PAD_PTB4__ADC0_SE4		0x068 0x000 ALT3 0x0
+#define VF610_PAD_PTB4__LCD38			0x068 0x000 ALT4 0x0
+#define VF610_PAD_PTB4__VIU_FID			0x068 0x3A8 ALT5 0x0
+#define VF610_PAD_PTB4__VIU_DATA22		0x068 0x000 ALT6 0x0
+#define VF610_PAD_PTB4__QSPI1_A_DATA0		0x068 0x000 ALT7 0x0
+#define VF610_PAD_PTB5__GPIO_27			0x06C 0x000 ALT0 0x0
+#define VF610_PAD_PTB5__FTM0_CH5		0x06C 0x000 ALT1 0x0
+#define VF610_PAD_PTB5__UART1_RX		0x06C 0x37C ALT2 0x0
+#define VF610_PAD_PTB5__ADC1_SE4		0x06C 0x000 ALT3 0x0
+#define VF610_PAD_PTB5__LCD39			0x06C 0x000 ALT4 0x0
+#define VF610_PAD_PTB5__VIU_DE			0x06C 0x3A4 ALT5 0x0
+#define VF610_PAD_PTB5__QSPI1_A_DQS		0x06C 0x000 ALT7 0x0
+#define VF610_PAD_PTB6__GPIO_28			0x070 0x000 ALT0 0x0
+#define VF610_PAD_PTB6__FTM0_CH6		0x070 0x000 ALT1 0x0
+#define VF610_PAD_PTB6__UART1_RTS		0x070 0x000 ALT2 0x0
+#define VF610_PAD_PTB6__QSPI0_QPCS1_A		0x070 0x000 ALT3 0x0
+#define VF610_PAD_PTB6__LCD_LCD40		0x070 0x000 ALT4 0x0
+#define VF610_PAD_PTB6__FB_CLKOUT		0x070 0x000 ALT5 0x0
+#define VF610_PAD_PTB6__VIU_HSYNC		0x070 0x000 ALT6 0x0
+#define VF610_PAD_PTB6__UART2_TX		0x070 0x38C ALT7 0x0
+#define VF610_PAD_PTB7__GPIO_29			0x074 0x000 ALT0 0x0
+#define VF610_PAD_PTB7__FTM0_CH7		0x074 0x000 ALT1 0x0
+#define VF610_PAD_PTB7__UART1_CTS		0x074 0x378 ALT2 0x0
+#define VF610_PAD_PTB7__QSPI0_B_QPCS1		0x074 0x000 ALT3 0x0
+#define VF610_PAD_PTB7__LCD41			0x074 0x000 ALT4 0x0
+#define VF610_PAD_PTB7__VIU_VSYNC		0x074 0x000 ALT6 0x0
+#define VF610_PAD_PTB7__UART2_RX		0x074 0x388 ALT7 0x0
+#define VF610_PAD_PTB8__GPIO_30			0x078 0x000 ALT0 0x0
+#define VF610_PAD_PTB8__FTM1_CH0		0x078 0x32C ALT1 0x0
+#define VF610_PAD_PTB8__FTM1_QD_PHA		0x078 0x334 ALT3 0x1
+#define VF610_PAD_PTB8__VIU_DE			0x078 0x3A4 ALT5 0x1
+#define VF610_PAD_PTB8__DCU1_R6			0x078 0x000 ALT7 0x0
+#define VF610_PAD_PTB9__GPIO_31			0x07C 0x000 ALT0 0x0
+#define VF610_PAD_PTB9__FTM1_CH1		0x07C 0x330 ALT1 0x0
+#define VF610_PAD_PTB9__FTM1_QD_PHB		0x07C 0x338 ALT3 0x1
+#define VF610_PAD_PTB9__DCU1_R7			0x07C 0x000 ALT7 0x0
+#define VF610_PAD_PTB10__GPIO_32		0x080 0x000 ALT0 0x0
+#define VF610_PAD_PTB10__UART0_TX		0x080 0x000 ALT1 0x0
+#define VF610_PAD_PTB10__DCU0_TCON4		0x080 0x000 ALT4 0x0
+#define VF610_PAD_PTB10__VIU_DE			0x080 0x3A4 ALT5 0x2
+#define VF610_PAD_PTB10__CKO1			0x080 0x000 ALT6 0x0
+#define VF610_PAD_PTB10__ENET_TS_CLKIN		0x080 0x2F4 ALT7 0x1
+#define VF610_PAD_PTB11__GPIO_33		0x084 0x000 ALT0 0x0
+#define VF610_PAD_PTB11__UART0_RX		0x084 0x000 ALT1 0x0
+#define VF610_PAD_PTB11__DCU0_TCON5		0x084 0x000 ALT4 0x0
+#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B	0x084 0x000 ALT5 0x0
+#define VF610_PAD_PTB11__CKO2			0x084 0x000 ALT6 0x0
+#define VF610_PAD_PTB11_ENET0_1588_TMR0		0x084 0x304 ALT7 0x0
+#define VF610_PAD_PTB12__GPIO_34		0x088 0x000 ALT0 0x0
+#define VF610_PAD_PTB12__UART0_RTS		0x088 0x000 ALT1 0x0
+#define VF610_PAD_PTB12__DSPI0_CS5		0x088 0x000 ALT3 0x0
+#define VF610_PAD_PTB12__DCU0_TCON6		0x088 0x000 ALT4 0x0
+#define VF610_PAD_PTB12__FB_AD1			0x088 0x000 ALT5 0x0
+#define VF610_PAD_PTB12__NMI			0x088 0x000 ALT6 0x0
+#define VF610_PAD_PTB12__ENET0_1588_TMR1	0x088 0x308 ALT7 0x0
+#define VF610_PAD_PTB13__GPIO_35		0x08C 0x000 ALT0 0x0
+#define VF610_PAD_PTB13__UART0_CTS		0x08C 0x000 ALT1 0x0
+#define VF610_PAD_PTB13__DSPI0_CS4		0x08C 0x000 ALT3 0x0
+#define VF610_PAD_PTB13__DCU0_TCON7		0x08C 0x000 ALT4 0x0
+#define VF610_PAD_PTB13__FB_AD0			0x08C 0x000 ALT5 0x0
+#define VF610_PAD_PTB13__TRACE_CTL		0x08C 0x000 ALT6 0x0
+#define VF610_PAD_PTB14__GPIO_36		0x090 0x000 ALT0 0x0
+#define VF610_PAD_PTB14__CAN0_RX		0x090 0x000 ALT1 0x0
+#define VF610_PAD_PTB14__I2C0_SCL		0x090 0x33C ALT2 0x1
+#define VF610_PAD_PTB14__DCU0_TCON8		0x090 0x000 ALT4 0x0
+#define VF610_PAD_PTB14__DCU1_PCLK		0x090 0x000 ALT7 0x0
+#define VF610_PAD_PTB15__GPIO_37		0x094 0x000 ALT0 0x0
+#define VF610_PAD_PTB15__CAN0_TX		0x094 0x000 ALT1 0x0
+#define VF610_PAD_PTB15__I2C0_SDA		0x094 0x340 ALT2 0x1
+#define VF610_PAD_PTB15__DCU0_TCON9		0x094 0x000 ALT4 0x0
+#define VF610_PAD_PTB15__VIU_PIX_CLK		0x094 0x3AC ALT7 0x0
+#define VF610_PAD_PTB16__GPIO_38		0x098 0x000 ALT0 0x0
+#define VF610_PAD_PTB16__CAN1_RX		0x098 0x000 ALT1 0x0
+#define VF610_PAD_PTB16__I2C1_SCL		0x098 0x344 ALT2 0x1
+#define VF610_PAD_PTB16__DCU0_TCON10		0x098 0x000 ALT4 0x0
+#define VF610_PAD_PTB17__GPIO_39		0x09C 0x000 ALT0 0x0
+#define VF610_PAD_PTB17__CAN1_TX		0x09C 0x000 ALT1 0x0
+#define VF610_PAD_PTB17__I2C1_SDA		0x09C 0x348 ALT2 0x1
+#define VF610_PAD_PTB17__DCU0_TCON11		0x09C 0x000 ALT4 0x0
+#define VF610_PAD_PTB18__GPIO_40		0x0A0 0x000 ALT0 0x0
+#define VF610_PAD_PTB18__DSPI0_CS1		0x0A0 0x000 ALT1 0x0
+#define VF610_PAD_PTB18__EXT_AUDIO_MCLK		0x0A0 0x2EC ALT2 0x2
+#define VF610_PAD_PTB18__VIU_DATA9		0x0A0 0x000 ALT6 0x0
+#define VF610_PAD_PTB19__GPIO_41		0x0A4 0x000 ALT0 0x0
+#define VF610_PAD_PTB19__DSPI0_CS0		0x0A4 0x000 ALT1 0x0
+#define VF610_PAD_PTB19__VIU_DATA10		0x0A4 0x000 ALT6 0x0
+#define VF610_PAD_PTB20__GPIO_42		0x0A8 0x000 ALT0 0x0
+#define VF610_PAD_PTB20__DSPI0_SIN		0x0A8 0x000 ALT1 0x0
+#define VF610_PAD_PTB20__LCD42			0x0A8 0x000 ALT4 0x0
+#define VF610_PAD_PTB20__VIU_DATA11		0x0A8 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__GPIO_43		0x0AC 0x000 ALT0 0x0
+#define VF610_PAD_PTB21__DSPI0_SOUT		0x0AC 0x000 ALT1 0x0
+#define VF610_PAD_PTB21__LCD43			0x0AC 0x000 ALT4 0x0
+#define VF610_PAD_PTB21__VIU_DATA12		0x0AC 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__DCU1_PCLK		0x0AC 0x000 ALT7 0x0
+#define VF610_PAD_PTB22__GPIO_44		0x0B0 0x000 ALT0 0x0
+#define VF610_PAD_PTB22__DSPI0_SCK		0x0B0 0x000 ALT1 0x0
+#define VF610_PAD_PTB22__VLCD			0x0B0 0x000 ALT4 0x0
+#define VF610_PAD_PTB22__VIU_FID		0x0B0 0x3A8 ALT5 0x1
+#define VF610_PAD_PTC0__GPIO_45			0x0B4 0x000 ALT0 0x0
+#define VF610_PAD_PTC0__ENET_RMII0_MDC		0x0B4 0x000 ALT1 0x0
+#define VF610_PAD_PTC0__FTM1_CH0		0x0B4 0x32C ALT2 0x1
+#define VF610_PAD_PTC0__DSPI0_CS3		0x0B4 0x000 ALT3 0x0
+#define VF610_PAD_PTC0__ESAI_SCKT		0x0B4 0x310 ALT4 0x0
+#define VF610_PAD_PTC0__ESDHC0_CLK		0x0B4 0x000 ALT5 0x0
+#define VF610_PAD_PTC0__VIU_DATA0		0x0B4 0x000 ALT6 0x0
+#define VF610_PAD_PTC0__SRC_RCON18		0x0B4 0x398 ALT7 0x0
+#define VF610_PAD_PTC1__GPIO_46			0x0B8 0x000 ALT0 0x0
+#define VF610_PAD_PTC1__ENET_RMII0_MDIO		0x0B8 0x000 ALT1 0x0
+#define VF610_PAD_PTC1__FTM1_CH1		0x0B8 0x330 ALT2 0x1
+#define VF610_PAD_PTC1__DSPI0_CS2		0x0B8 0x000 ALT3 0x0
+#define VF610_PAD_PTC1__ESAI_FST		0x0B8 0x30C ALT4 0x0
+#define VF610_PAD_PTC1__ESDHC0_CMD		0x0B8 0x000 ALT5 0x0
+#define VF610_PAD_PTC1__VIU_DATA1		0x0B8 0x000 ALT6 0x0
+#define VF610_PAD_PTC1__SRC_RCON19		0x0B8 0x39C ALT7 0x0
+#define VF610_PAD_PTC2__GPIO_47			0x0BC 0x000 ALT0 0x0
+#define VF610_PAD_PTC2__ENET_RMII0_CRS		0x0BC 0x000 ALT1 0x0
+#define VF610_PAD_PTC2__UART1_TX		0x0BC 0x380 ALT2 0x1
+#define VF610_PAD_PTC2__ESAI_SDO0		0x0BC 0x314 ALT4 0x0
+#define VF610_PAD_PTC2__ESDHC0_DAT0		0x0BC 0x000 ALT5 0x0
+#define VF610_PAD_PTC2__VIU_DATA2		0x0BC 0x000 ALT6 0x0
+#define VF610_PAD_PTC2__SRC_RCON20		0x0BC 0x3A0 ALT7 0x0
+#define VF610_PAD_PTC3__GPIO_48			0x0C0 0x000 ALT0 0x0
+#define VF610_PAD_PTC3__ENET_RMII0_RXD1		0x0C0 0x000 ALT1 0x0
+#define VF610_PAD_PTC3__UART1_RX		0x0C0 0x37C ALT2 0x1
+#define VF610_PAD_PTC3__ESAI_SDO1		0x0C0 0x318 ALT4 0x0
+#define VF610_PAD_PTC3__ESDHC0_DAT1		0x0C0 0x000 ALT5 0x0
+#define VF610_PAD_PTC3__VIU_DATA3		0x0C0 0x000 ALT6 0x0
+#define VF610_PAD_PTC3__DCU0_R0			0x0C0 0x000 ALT7 0x0
+#define VF610_PAD_PTC4__GPIO_49			0x0C4 0x000 ALT0 0x0
+#define VF610_PAD_PTC4__ENET_RMII0_RXD0		0x0C4 0x000 ALT1 0x0
+#define VF610_PAD_PTC4__UART1_RTS		0x0C4 0x000 ALT2 0x0
+#define VF610_PAD_PTC4__DSPI1_CS1		0x0C4 0x000 ALT3 0x0
+#define VF610_PAD_PTC4__ESAI_SDO2		0x0C4 0x31C ALT4 0x0
+#define VF610_PAD_PTC4__ESDHC0_DAT2		0x0C4 0x000 ALT5 0x0
+#define VF610_PAD_PTC4__VIU_DATA4		0x0C4 0x000 ALT6 0x0
+#define VF610_PAD_PTC4__DCU0_R1			0x0C4 0x000 ALT7 0x0
+#define VF610_PAD_PTC5__GPIO_50			0x0C8 0x000 ALT0 0x0
+#define VF610_PAD_PTC5__ENET_RMII0_RXER		0x0C8 0x000 ALT1 0x0
+#define VF610_PAD_PTC5__UART1_CTS		0x0C8 0x378 ALT2 0x1
+#define VF610_PAD_PTC5__DSPI1_CS0		0x0C8 0x300 ALT3 0x0
+#define VF610_PAD_PTC5__ESAI_SDO3		0x0C8 0x320 ALT4 0x0
+#define VF610_PAD_PTC5__ESDHC0_DAT3		0x0C8 0x000 ALT5 0x0
+#define VF610_PAD_PTC5__VIU_DATA5		0x0C8 0x000 ALT6 0x0
+#define VF610_PAD_PTC5__DCU0_G0			0x0C8 0x000 ALT7 0x0
+#define VF610_PAD_PTC6__GPIO_51			0x0CC 0x000 ALT0 0x0
+#define VF610_PAD_PTC6__ENET_RMII0_TXD1		0x0CC 0x000 ALT1 0x0
+#define VF610_PAD_PTC6__DSPI1_SIN		0x0CC 0x2FC ALT3 0x0
+#define VF610_PAD_PTC6__ESAI_SDI0		0x0CC 0x328 ALT4 0x0
+#define VF610_PAD_PTC6__ESDHC0_WP		0x0CC 0x000 ALT5 0x0
+#define VF610_PAD_PTC6__VIU_DATA6		0x0CC 0x000 ALT6 0x0
+#define VF610_PAD_PTC6__DCU0_G1			0x0CC 0x000 ALT7 0x0
+#define VF610_PAD_PTC7__GPIO_52			0x0D0 0x000 ALT0 0x0
+#define VF610_PAD_PTC7__ENET_RMII0_TXD0		0x0D0 0x000 ALT1 0x0
+#define VF610_PAD_PTC7__DSPI1_SOUT		0x0D0 0x000 ALT3 0x0
+#define VF610_PAD_PTC7__ESAI_SDI1		0x0D0 0x324 ALT4 0x0
+#define VF610_PAD_PTC7__VIU_DATA7		0x0D0 0x000 ALT6 0x0
+#define VF610_PAD_PTC7__DCU0_B0			0x0D0 0x000 ALT7 0x0
+#define VF610_PAD_PTC8__GPIO_53			0x0D4 0x000 ALT0 0x0
+#define VF610_PAD_PTC8__ENET_RMII0_TXEN		0x0D4 0x000 ALT1 0x0
+#define VF610_PAD_PTC8__DSPI1_SCK		0x0D4 0x2F8 ALT3 0x0
+#define VF610_PAD_PTC8__VIU_DATA8		0x0D4 0x000 ALT6 0x0
+#define VF610_PAD_PTC8__DCU0_B1			0x0D4 0x000 ALT7 0x0
+#define VF610_PAD_PTC9__GPIO_54			0x0D8 0x000 ALT0 0x0
+#define VF610_PAD_PTC9__ENET_RMII1_MDC		0x0D8 0x000 ALT1 0x0
+#define VF610_PAD_PTC9__ESAI_SCKT		0x0D8 0x310 ALT3 0x1
+#define VF610_PAD_PTC9__MLB_CLK			0x0D8 0x354 ALT6 0x1
+#define VF610_PAD_PTC9__DEBUG_OUT0		0x0D8 0x000 ALT7 0x0
+#define VF610_PAD_PTC10__GPIO_55		0x0DC 0x000 ALT0 0x0
+#define VF610_PAD_PTC10__ENET_RMII1_MDIO	0x0DC 0x000 ALT1 0x0
+#define VF610_PAD_PTC10__ESAI_FST		0x0DC 0x30C ALT3 0x1
+#define VF610_PAD_PTC10__MLB_SIGNAL		0x0DC 0x35C ALT6 0x1
+#define VF610_PAD_PTC10__DEBUG_OUT1		0x0DC 0x000 ALT7 0x0
+#define VF610_PAD_PTC11__GPIO_56		0x0E0 0x000 ALT0 0x0
+#define VF610_PAD_PTC11__ENET_RMII1_CRS		0x0E0 0x000 ALT1 0x0
+#define VF610_PAD_PTC11__ESAI_SDO0		0x0E0 0x314 ALT3 0x1
+#define VF610_PAD_PTC11__MLB_DATA		0x0E0 0x358 ALT6 0x1
+#define VF610_PAD_PTC11__DEBUG_OUT		0x0E0 0x000 ALT7 0x0
+#define VF610_PAD_PTC12__GPIO_57		0x0E4 0x000 ALT0 0x0
+#define VF610_PAD_PTC12__ENET_RMII_RXD1		0x0E4 0x000 ALT1 0x0
+#define VF610_PAD_PTC12__ESAI_SDO1		0x0E4 0x318 ALT3 0x1
+#define VF610_PAD_PTC12__SAI2_TX_BCLK		0x0E4 0x370 ALT5 0x1
+#define VF610_PAD_PTC12__DEBUG_OUT3		0x0E4 0x000 ALT7 0x0
+#define VF610_PAD_PTC13__GPIO_58		0x0E8 0x000 ALT0 0x0
+#define VF610_PAD_PTC13__ENET_RMII1_RXD0	0x0E8 0x000 ALT1 0x0
+#define VF610_PAD_PTC13__ESAI_SDO2		0x0E8 0x31C ALT3 0x1
+#define VF610_PAD_PTC13__SAI2_RX_BCLK		0x0E8 0x364 ALT5 0x2
+#define VF610_PAD_PTC13__DEBUG_OUT4		0x0E8 0x000 ALT7 0x0
+#define VF610_PAD_PTC14__GPIO_59		0x0EC 0x000 ALT0 0x0
+#define VF610_PAD_PTC14__ENET_RMII1_RXER	0x0EC 0x000 ALT1 0x0
+#define VF610_PAD_PTC14__ESAI_SDO3		0x0EC 0x320 ALT3 0x1
+#define VF610_PAD_PTC14__UART5_TX		0x0EC 0x000 ALT4 0x0
+#define VF610_PAD_PTC14__SAI2_RX_DATA		0x0EC 0x368 ALT5 0x2
+#define VF610_PAD_PTC14__ADC0_SE6		0x0EC 0x000 ALT6 0x0
+#define VF610_PAD_PTC14__DEBUG_OUT5		0x0EC 0x000 ALT7 0x0
+#define VF610_PAD_PTC15__GPIO_60		0x0F0 0x000 ALT0 0x0
+#define VF610_PAD_PTC15__ENET_RMII1_TXD1	0x0F0 0x000 ALT1 0x0
+#define VF610_PAD_PTC15__ESAI_SDI0		0x0F0 0x328 ALT3 0x1
+#define VF610_PAD_PTC15__UART5_RX		0x0F0 0x000 ALT4 0x0
+#define VF610_PAD_PTC15__SAI2_TX_DATA		0x0F0 0x000 ALT5 0x0
+#define VF610_PAD_PTC15__ADC0_SE7		0x0F0 0x000 ALT6 0x0
+#define VF610_PAD_PTC15__DEBUG_OUT6		0x0F0 0x000 ALT7 0x0
+#define VF610_PAD_PTC16__GPIO_61		0x0F4 0x000 ALT0 0x0
+#define VF610_PAD_PTC16__ENET_RMII1_TXD0	0x0F4 0x000 ALT1 0x0
+#define VF610_PAD_PTC16__ESAI_SDI1		0x0F4 0x324 ALT3 0x1
+#define VF610_PAD_PTC16__UART5_RTS		0x0F4 0x000 ALT4 0x0
+#define VF610_PAD_PTC16__SAI2_RX_SYNC		0x0F4 0x36C ALT5 0x2
+#define VF610_PAD_PTC16__ADC1_SE6		0x0F4 0x000 ALT6 0x0
+#define VF610_PAD_PTC16__DEBUG_OUT7		0x0F4 0x000 ALT7 0x0
+#define VF610_PAD_PTC17__GPIO_62		0x0F8 0x000 ALT0 0x0
+#define VF610_PAD_PTC17__ENET_RMII1_TXEN	0x0F8 0x000 ALT1 0x0
+#define VF610_PAD_PTC17__ADC1_SE7		0x0F8 0x000 ALT3 0x0
+#define VF610_PAD_PTC17__UART5_CTS		0x0F8 0x000 ALT4 0x0
+#define VF610_PAD_PTC17__SAI2_TX_SYNC		0x0F8 0x374 ALT5 0x1
+#define VF610_PAD_PTC17__USB1_SOF_PULSE		0x0F8 0x000 ALT6 0x0
+#define VF610_PAD_PTC17__DEBUG_OUT8		0x0F8 0x000 ALT7 0x0
+#define VF610_PAD_PTD31__GPIO_63		0x0FC 0x000 ALT0 0x0
+#define VF610_PAD_PTD31__FB_AD31		0x0FC 0x000 ALT1 0x0
+#define VF610_PAD_PTD31__NF_IO15		0x0FC 0x000 ALT2 0x0
+#define VF610_PAD_PTD31__FTM3_CH0		0x0FC 0x000 ALT4 0x0
+#define VF610_PAD_PTD31__DSPI2_CS1		0x0FC 0x000 ALT5 0x0
+#define VF610_PAD_PTD31__DEBUG_OUT9		0x0FC 0x000 ALT7 0x0
+#define VF610_PAD_PTD30__GPIO_64		0x100 0x000 ALT0 0x0
+#define VF610_PAD_PTD30__FB_AD30		0x100 0x000 ALT1 0x0
+#define VF610_PAD_PTD30__NF_IO14		0x100 0x000 ALT2 0x0
+#define VF610_PAD_PTD30__FTM3_CH1		0x100 0x000 ALT4 0x0
+#define VF610_PAD_PTD30__DSPI2_CS0		0x100 0x000 ALT5 0x0
+#define VF610_PAD_PTD30__DEBUG_OUT10		0x100 0x000 ALT7 0x0
+#define VF610_PAD_PTD29__GPIO_65		0x104 0x000 ALT0 0x0
+#define VF610_PAD_PTD29__FB_AD29		0x104 0x000 ALT1 0x0
+#define VF610_PAD_PTD29__NF_IO13		0x104 0x000 ALT2 0x0
+#define VF610_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
+#define VF610_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
+#define VF610_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
+#define VF610_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
+#define VF610_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
+#define VF610_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1
+#define VF610_PAD_PTD28__FTM3_CH3		0x108 0x000 ALT4 0x0
+#define VF610_PAD_PTD28__DSPI2_SOUT		0x108 0x000 ALT5 0x0
+#define VF610_PAD_PTD28__DEBUG_OUT12		0x108 0x000 ALT7 0x0
+#define VF610_PAD_PTD27__GPIO_67		0x10C 0x000 ALT0 0x0
+#define VF610_PAD_PTD27__FB_AD27		0x10C 0x000 ALT1 0x0
+#define VF610_PAD_PTD27__NF_IO11		0x10C 0x000 ALT2 0x0
+#define VF610_PAD_PTD27__I2C2_SDA		0x10C 0x350 ALT3 0x1
+#define VF610_PAD_PTD27__FTM3_CH4		0x10C 0x000 ALT4 0x0
+#define VF610_PAD_PTD27__DSPI2_SCK		0x10C 0x000 ALT5 0x0
+#define VF610_PAD_PTD27__DEBUG_OUT13		0x10C 0x000 ALT7 0x0
+#define VF610_PAD_PTD26__GPIO_68		0x110 0x000 ALT0 0x0
+#define VF610_PAD_PTD26__FB_AD26		0x110 0x000 ALT1 0x0
+#define VF610_PAD_PTD26__NF_IO10		0x110 0x000 ALT2 0x0
+#define VF610_PAD_PTD26__FTM3_CH5		0x110 0x000 ALT4 0x0
+#define VF610_PAD_PTD26__ESDHC1_WP		0x110 0x000 ALT5 0x0
+#define VF610_PAD_PTD26__DEBUG_OUT14		0x110 0x000 ALT7 0x0
+#define VF610_PAD_PTD25__GPIO_69		0x114 0x000 ALT0 0x0
+#define VF610_PAD_PTD25__FB_AD25		0x114 0x000 ALT1 0x0
+#define VF610_PAD_PTD25__NF_IO9			0x114 0x000 ALT2 0x0
+#define VF610_PAD_PTD25__FTM3_CH6		0x114 0x000 ALT4 0x0
+#define VF610_PAD_PTD25__DEBUG_OUT15		0x114 0x000 ALT7 0x0
+#define VF610_PAD_PTD24__GPIO_70		0x118 0x000 ALT0 0x0
+#define VF610_PAD_PTD24__FB_AD24		0x118 0x000 ALT1 0x0
+#define VF610_PAD_PTD24__NF_IO8			0x118 0x000 ALT2 0x0
+#define VF610_PAD_PTD24__FTM3_CH7		0x118 0x000 ALT4 0x0
+#define VF610_PAD_PTD24__DEBUG_OUT16		0x118 0x000 ALT7 0x0
+#define VF610_PAD_PTD23__GPIO_71		0x11C 0x000 ALT0 0x0
+#define VF610_PAD_PTD23__FB_AD23		0x11C 0x000 ALT1 0x0
+#define VF610_PAD_PTD23__NF_IO7			0x11C 0x000 ALT2 0x0
+#define VF610_PAD_PTD23__FTM2_CH0		0x11C 0x000 ALT3 0x0
+#define VF610_PAD_PTD23__ENET0_1588_TMR0	0x11C 0x304 ALT4 0x1
+#define VF610_PAD_PTD23__ESDHC0_DAT4		0x11C 0x000 ALT5 0x0
+#define VF610_PAD_PTD23__UART2_TX		0x11C 0x38C ALT6 0x1
+#define VF610_PAD_PTD23__DCU1_R3		0x11C 0x000 ALT7 0x0
+#define VF610_PAD_PTD22__GPIO_72		0x120 0x000 ALT0 0x0
+#define VF610_PAD_PTD22__FB_AD22		0x120 0x000 ALT1 0x0
+#define VF610_PAD_PTD22__NF_IO6			0x120 0x000 ALT2 0x0
+#define VF610_PAD_PTD22__FTM2_CH1		0x120 0x000 ALT3 0x0
+#define VF610_PAD_PTD22__ENET0_1588_TMR1	0x120 0x308 ALT4 0x1
+#define VF610_PAD_PTD22__ESDHC0_DAT5		0x120 0x000 ALT5 0x0
+#define VF610_PAD_PTD22__UART2_RX		0x120 0x388 ALT6 0x1
+#define VF610_PAD_PTD22__DCU1_R4		0x120 0x000 ALT7 0x0
+#define VF610_PAD_PTD21__GPIO_73		0x124 0x000 ALT0 0x0
+#define VF610_PAD_PTD21__FB_AD21		0x124 0x000 ALT1 0x0
+#define VF610_PAD_PTD21__NF_IO5			0x124 0x000 ALT2 0x0
+#define VF610_PAD_PTD21__ENET0_1588_TMR2	0x124 0x000 ALT4 0x0
+#define VF610_PAD_PTD21__ESDHC0_DAT6		0x124 0x000 ALT5 0x0
+#define VF610_PAD_PTD21__UART2_RTS		0x124 0x000 ALT6 0x0
+#define VF610_PAD_PTD21__DCU1_R5		0x124 0x000 ALT7 0x0
+#define VF610_PAD_PTD20__GPIO_74		0x128 0x000 ALT0 0x0
+#define VF610_PAD_PTD20__FB_AD20		0x128 0x000 ALT1 0x0
+#define VF610_PAD_PTD20__NF_IO4			0x128 0x000 ALT2 0x0
+#define VF610_PAD_PTD20__ENET0_1588_TMR3	0x128 0x000 ALT4 0x0
+#define VF610_PAD_PTD20__ESDHC0_DAT7		0x128 0x000 ALT5 0x0
+#define VF610_PAD_PTD20__UART2_CTS		0x128 0x384 ALT6 0x0
+#define VF610_PAD_PTD20__DCU1_R0		0x128 0x000 ALT7 0x0
+#define VF610_PAD_PTD19__GPIO_75		0x12C 0x000 ALT0 0x0
+#define VF610_PAD_PTD19__FB_AD19		0x12C 0x000 ALT1 0x0
+#define VF610_PAD_PTD19__NF_IO3			0x12C 0x000 ALT2 0x0
+#define VF610_PAD_PTD19__ESAI_SCKR		0x12C 0x000 ALT3 0x0
+#define VF610_PAD_PTD19__I2C0_SCL		0x12C 0x33C ALT4 0x2
+#define VF610_PAD_PTD19__FTM2_QD_PHA		0x12C 0x000 ALT5 0x0
+#define VF610_PAD_PTD19__DCU1_R1		0x12C 0x000 ALT7 0x0
+#define VF610_PAD_PTD18__GPIO_76		0x130 0x000 ALT0 0x0
+#define VF610_PAD_PTD18__FB_AD18		0x130 0x000 ALT1 0x0
+#define VF610_PAD_PTD18__NF_IO2			0x130 0x000 ALT2 0x0
+#define VF610_PAD_PTD18__ESAI_FSR		0x130 0x000 ALT3 0x0
+#define VF610_PAD_PTD18__I2C0_SDA		0x130 0x340 ALT4 0x2
+#define VF610_PAD_PTD18__FTM2_QD_PHB		0x130 0x000 ALT5 0x0
+#define VF610_PAD_PTD18__DCU1_G0		0x130 0x000 ALT7 0x0
+#define VF610_PAD_PTD17__GPIO_77		0x134 0x000 ALT0 0x0
+#define VF610_PAD_PTD17__FB_AD17		0x134 0x000 ALT1 0x0
+#define VF610_PAD_PTD17__NF_IO1			0x134 0x000 ALT2 0x0
+#define VF610_PAD_PTD17__ESAI_HCKR		0x134 0x000 ALT3 0x0
+#define VF610_PAD_PTD17__I2C1_SCL		0x134 0x344 ALT4 0x2
+#define VF610_PAD_PTD17__DCU1_G1		0x134 0x000 ALT7 0x0
+#define VF610_PAD_PTD16__GPIO_78		0x138 0x000 ALT0 0x0
+#define VF610_PAD_PTD16__FB_AD16		0x138 0x000 ALT1 0x0
+#define VF610_PAD_PTD16__NF_IO0			0x138 0x000 ALT2 0x0
+#define VF610_PAD_PTD16__ESAI_HCKT		0x138 0x000 ALT3 0x0
+#define VF610_PAD_PTD16__I2C1_SDA		0x138 0x348 ALT4 0x2
+#define VF610_PAD_PTD16__DCU1_G2		0x138 0x000 ALT7 0x0
+#define VF610_PAD_PTD0__GPIO_79			0x13C 0x000 ALT0 0x0
+#define VF610_PAD_PTD0__QSPI0_A_QSCK		0x13C 0x000 ALT1 0x0
+#define VF610_PAD_PTD0__UART2_TX		0x13C 0x38C ALT2 0x2
+#define VF610_PAD_PTD0__FB_AD15			0x13C 0x000 ALT4 0x0
+#define VF610_PAD_PTD0__SPDIF_EXTCLK		0x13C 0x000 ALT5 0x0
+#define VF610_PAD_PTD0__DEBUG_OUT17		0x13C 0x000 ALT7 0x0
+#define VF610_PAD_PTD1__GPIO_80			0x140 0x000 ALT0 0x0
+#define VF610_PAD_PTD1__QSPI0_A_CS0		0x140 0x000 ALT1 0x0
+#define VF610_PAD_PTD1__UART2_RX		0x140 0x388 ALT2 0x2
+#define VF610_PAD_PTD1__FB_AD14			0x140 0x000 ALT4 0x0
+#define VF610_PAD_PTD1__SPDIF_IN1		0x140 0x000 ALT5 0x0
+#define VF610_PAD_PTD1__DEBUG_OUT18		0x140 0x000 ALT7 0x0
+#define VF610_PAD_PTD2__GPIO_81			0x144 0x000 ALT0 0x0
+#define VF610_PAD_PTD2__QSPI0_A_DATA3		0x144 0x000 ALT1 0x0
+#define VF610_PAD_PTD2__UART2_RTS		0x144 0x000 ALT2 0x0
+#define VF610_PAD_PTD2__DSPI1_CS3		0x144 0x000 ALT3 0x0
+#define VF610_PAD_PTD2__FB_AD13			0x144 0x000 ALT4 0x0
+#define VF610_PAD_PTD2__SPDIF_OUT1		0x144 0x000 ALT5 0x0
+#define VF610_PAD_PTD2__DEBUG_OUT19		0x144 0x000 ALT7 0x0
+#define VF610_PAD_PTD3__GPIO_82			0x148 0x000 ALT0 0x0
+#define VF610_PAD_PTD3__QSPI0_A_DATA2		0x148 0x000 ALT1 0x0
+#define VF610_PAD_PTD3__UART2_CTS		0x148 0x384 ALT2 0x1
+#define VF610_PAD_PTD3__DSPI1_CS2		0x148 0x000 ALT3 0x0
+#define VF610_PAD_PTD3__FB_AD12			0x148 0x000 ALT4 0x0
+#define VF610_PAD_PTD3__SPDIF_PLOCK		0x148 0x000 ALT5 0x0
+#define VF610_PAD_PTD3__DEBUG_OUT20		0x148 0x000 ALT7 0x0
+#define VF610_PAD_PTD4__GPIO_83			0x14C 0x000 ALT0 0x0
+#define VF610_PAD_PTD4__QSPI0_A_DATA1		0x14C 0x000 ALT1 0x0
+#define VF610_PAD_PTD4__DSPI1_CS1		0x14C 0x000 ALT3 0x0
+#define VF610_PAD_PTD4__FB_AD11			0x14C 0x000 ALT4 0x0
+#define VF610_PAD_PTD4__SPDIF_SRCLK		0x14C 0x000 ALT5 0x0
+#define VF610_PAD_PTD4__DEBUG_OUT21		0x14C 0x000 ALT7 0x0
+#define VF610_PAD_PTD5__GPIO_84			0x150 0x000 ALT0 0x0
+#define VF610_PAD_PTD5__QSPI0_A_DATA0		0x150 0x000 ALT1 0x0
+#define VF610_PAD_PTD5__DSPI1_CS0		0x150 0x300 ALT3 0x1
+#define VF610_PAD_PTD5__FB_AD10			0x150 0x000 ALT4 0x0
+#define VF610_PAD_PTD5__DEBUG_OUT22		0x150 0x000 ALT7 0x0
+#define VF610_PAD_PTD6__GPIO_85			0x154 0x000 ALT0 0x0
+#define VF610_PAD_PTD6__QSPI1_A_DQS		0x154 0x000 ALT1 0x0
+#define VF610_PAD_PTD6__DSPI1_SIN		0x154 0x2FC ALT3 0x1
+#define VF610_PAD_PTD6__FB_AD9			0x154 0x000 ALT4 0x0
+#define VF610_PAD_PTD6__DEBUG_OUT23		0x154 0x000 ALT7 0x0
+#define VF610_PAD_PTD7__GPIO_86			0x158 0x000 ALT0 0x0
+#define VF610_PAD_PTD7__QSPI0_B_QSCK		0x158 0x000 ALT1 0x0
+#define VF610_PAD_PTD7__DSPI1_SOUT		0x158 0x000 ALT3 0x0
+#define VF610_PAD_PTD7__FB_AD8			0x158 0x000 ALT4 0x0
+#define VF610_PAD_PTD7__DEBUG_OUT24		0x158 0x000 ALT7 0x0
+#define VF610_PAD_PTD8__GPIO_87			0x15C 0x000 ALT0 0x0
+#define VF610_PAD_PTD8__QSPI0_B_CS0		0x15C 0x000 ALT1 0x0
+#define VF610_PAD_PTD8__FB_CLKOUT		0x15C 0x000 ALT2 0x0
+#define VF610_PAD_PTD8__DSPI1_SCK		0x15C 0x2F8 ALT3 0x1
+#define VF610_PAD_PTD8__FB_AD7			0x15C 0x000 ALT4 0x0
+#define VF610_PAD_PTD8__DEBUG_OUT25		0x15C 0x000 ALT7 0x0
+#define VF610_PAD_PTD9__GPIO_88			0x160 0x000 ALT0 0x0
+#define VF610_PAD_PTD9__QSPI0_B_DATA3		0x160 0x000 ALT1 0x0
+#define VF610_PAD_PTD9__DSPI3_CS1		0x160 0x000 ALT2 0x0
+#define VF610_PAD_PTD9__FB_AD6			0x160 0x000 ALT4 0x0
+#define VF610_PAD_PTD9__SAI1_TX_SYNC		0x160 0x360 ALT6 0x0
+#define VF610_PAD_PTD9__DCU1_B0			0x160 0x000 ALT7 0x0
+#define VF610_PAD_PTD10__GPIO_89		0x164 0x000 ALT0 0x0
+#define VF610_PAD_PTD10__QSPI0_B_DATA2		0x164 0x000 ALT1 0x0
+#define VF610_PAD_PTD10__DSPI3_CS0		0x164 0x000 ALT2 0x0
+#define VF610_PAD_PTD10__FB_AD5			0x164 0x000 ALT4 0x0
+#define VF610_PAD_PTD10__DCU1_B1		0x164 0x000 ALT7 0x0
+#define VF610_PAD_PTD11__GPIO_90		0x168 0x000 ALT0 0x0
+#define VF610_PAD_PTD11__QSPI0_B_DATA1		0x168 0x000 ALT1 0x0
+#define VF610_PAD_PTD11__DSPI3_SIN		0x168 0x000 ALT2 0x0
+#define VF610_PAD_PTD11__FB_AD4			0x168 0x000 ALT4 0x0
+#define VF610_PAD_PTD11__DEBUG_OUT26		0x168 0x000 ALT7 0x0
+#define VF610_PAD_PTD12__GPIO_91		0x16C 0x000 ALT0 0x0
+#define VF610_PAD_PTD12__QSPI0_B_DATA0		0x16C 0x000 ALT1 0x0
+#define VF610_PAD_PTD12__DSPI3_SOUT		0x16C 0x000 ALT2 0x0
+#define VF610_PAD_PTD12__FB_AD3			0x16C 0x000 ALT4 0x0
+#define VF610_PAD_PTD12__DEBUG_OUT27		0x16C 0x000 ALT7 0x0
+#define VF610_PAD_PTD13__GPIO_92		0x170 0x000 ALT0 0x0
+#define VF610_PAD_PTD13__QSPI0_B_DQS		0x170 0x000 ALT1 0x0
+#define VF610_PAD_PTD13__DSPI3_SCK		0x170 0x000 ALT2 0x0
+#define VF610_PAD_PTD13__FB_AD2			0x170 0x000 ALT4 0x0
+#define VF610_PAD_PTD13__DEBUG_OUT28		0x170 0x000 ALT7 0x0
+#define VF610_PAD_PTB23__GPIO_93		0x174 0x000 ALT0 0x0
+#define VF610_PAD_PTB23__SAI0_TX_BCLK		0x174 0x000 ALT1 0x0
+#define VF610_PAD_PTB23__UART1_TX		0x174 0x380 ALT2 0x2
+#define VF610_PAD_PTB23__SRC_RCON18		0x174 0x398 ALT3 0x1
+#define VF610_PAD_PTB23__FB_MUXED_ALE		0x174 0x000 ALT4 0x0
+#define VF610_PAD_PTB23__FB_TS_B		0x174 0x000 ALT5 0x0
+#define VF610_PAD_PTB23__UART3_RTS		0x174 0x000 ALT6 0x0
+#define VF610_PAD_PTB23__DCU1_G3		0x174 0x000 ALT7 0x0
+#define VF610_PAD_PTB24__GPIO_94		0x178 0x000 ALT0 0x0
+#define VF610_PAD_PTB24__SAI0_RX_BCLK		0x178 0x000 ALT1 0x0
+#define VF610_PAD_PTB24__UART1_RX		0x178 0x37C ALT2 0x2
+#define VF610_PAD_PTB24__SRC_RCON19		0x178 0x39C ALT3 0x1
+#define VF610_PAD_PTB24__FB_MUXED_TSIZ0		0x178 0x000 ALT4 0x0
+#define VF610_PAD_PTB24__NF_WE_B		0x178 0x000 ALT5 0x0
+#define VF610_PAD_PTB24__UART3_CTS		0x178 0x000 ALT6 0x0
+#define VF610_PAD_PTB24__DCU1_G4		0x178 0x000 ALT7 0x0
+#define VF610_PAD_PTB25__GPIO_95		0x17C 0x000 ALT0 0x0
+#define VF610_PAD_PTB25__SAI0_RX_DATA		0x17C 0x000 ALT1 0x0
+#define VF610_PAD_PTB25__UART1_RTS		0x17C 0x000 ALT2 0x0
+#define VF610_PAD_PTB25__SRC_RCON20		0x17C 0x3A0 ALT3 0x1
+#define VF610_PAD_PTB25__FB_CS1_B		0x17C 0x000 ALT4 0x0
+#define VF610_PAD_PTB25__NF_CE0_B		0x17C 0x000 ALT5 0x0
+#define VF610_PAD_PTB25__DCU1_G5		0x17C 0x000 ALT7 0x0
+#define VF610_PAD_PTB26__GPIO_96		0x180 0x000 ALT0 0x0
+#define VF610_PAD_PTB26__SAI0_TX_DATA		0x180 0x000 ALT1 0x0
+#define VF610_PAD_PTB26__UART1_CTS		0x180 0x378 ALT2 0x2
+#define VF610_PAD_PTB26__SRC_RCON21		0x180 0x000 ALT3 0x0
+#define VF610_PAD_PTB26__FB_CS0_B		0x180 0x000 ALT4 0x0
+#define VF610_PAD_PTB26__NF_CE1_B		0x180 0x000 ALT5 0x0
+#define VF610_PAD_PTB26__DCU1_G6		0x180 0x000 ALT7 0x0
+#define VF610_PAD_PTB27__GPIO_97		0x184 0x000 ALT0 0x0
+#define VF610_PAD_PTB27__SAI0_RX_SYNC		0x184 0x000 ALT1 0x0
+#define VF610_PAD_PTB27__SRC_RCON22		0x184 0x000 ALT3 0x0
+#define VF610_PAD_PTB27__FB_OE_B		0x184 0x000 ALT4 0x0
+#define VF610_PAD_PTB27__FB_MUXED_TBST_B	0x184 0x000 ALT5 0x0
+#define VF610_PAD_PTB27__NF_RE_B		0x184 0x000 ALT6 0x0
+#define VF610_PAD_PTB27__DCU1_G7		0x184 0x000 ALT7 0x0
+#define VF610_PAD_PTB28__GPIO_98		0x188 0x000 ALT0 0x0
+#define VF610_PAD_PTB28__SAI0_TX_SYNC		0x188 0x000 ALT1 0x0
+#define VF610_PAD_PTB28__SRC_RCON23		0x188 0x000 ALT3 0x0
+#define VF610_PAD_PTB28__FB_RW_B		0x188 0x000 ALT4 0x0
+#define VF610_PAD_PTB28__DCU1_B6		0x188 0x000 ALT7 0x0
+#define VF610_PAD_PTC26__GPIO_99		0x18C 0x000 ALT0 0x0
+#define VF610_PAD_PTC26__SAI1_TX_BCLK		0x18C 0x000 ALT1 0x0
+#define VF610_PAD_PTC26__DSPI0_CS5		0x18C 0x000 ALT2 0x0
+#define VF610_PAD_PTC26__SRC_RCON24		0x18C 0x000 ALT3 0x0
+#define VF610_PAD_PTC26__FB_TA_B		0x18C 0x000 ALT4 0x0
+#define VF610_PAD_PTC26__NF_RB_B		0x18C 0x000 ALT5 0x0
+#define VF610_PAD_PTC26__DCU1_B7		0x18C 0x000 ALT7 0x0
+#define VF610_PAD_PTC27__GPIO_100		0x190 0x000 ALT0 0x0
+#define VF610_PAD_PTC27__SAI1_RX_BCLK		0x190 0x000 ALT1 0x0
+#define VF610_PAD_PTC27__DSPI0_CS4		0x190 0x000 ALT2 0x0
+#define VF610_PAD_PTC27__SRC_RCON25		0x190 0x000 ALT3 0x0
+#define VF610_PAD_PTC27__FB_BE3_B		0x190 0x000 ALT4 0x0
+#define VF610_PAD_PTC27__FB_CS3_B		0x190 0x000 ALT5 0x0
+#define VF610_PAD_PTC27__NF_ALE			0x190 0x000 ALT6 0x0
+#define VF610_PAD_PTC27__DCU1_B2		0x190 0x000 ALT7 0x0
+#define VF610_PAD_PTC28__GPIO_101		0x194 0x000 ALT0 0x0
+#define VF610_PAD_PTC28__SAI1_RX_DATA		0x194 0x000 ALT1 0x0
+#define VF610_PAD_PTC28__DSPI0_CS3		0x194 0x000 ALT2 0x0
+#define VF610_PAD_PTC28__SRC_RCON26		0x194 0x000 ALT3 0x0
+#define VF610_PAD_PTC28__FB_BE2_B		0x194 0x000 ALT4 0x0
+#define VF610_PAD_PTC28__FB_CS2_B		0x194 0x000 ALT5 0x0
+#define VF610_PAD_PTC28__NF_CLE			0x194 0x000 ALT6 0x0
+#define VF610_PAD_PTC28__DCU1_B3		0x194 0x000 ALT7 0x0
+#define VF610_PAD_PTC29__GPIO_102		0x198 0x000 ALT0 0x0
+#define VF610_PAD_PTC29__SAI1_TX_DATA		0x198 0x000 ALT1 0x0
+#define VF610_PAD_PTC29__DSPI0_CS2		0x198 0x000 ALT2 0x0
+#define VF610_PAD_PTC29__SRC_RCON27		0x198 0x000 ALT3 0x0
+#define VF610_PAD_PTC29__FB_BE1_B		0x198 0x000 ALT4 0x0
+#define VF610_PAD_PTC29__FB_MUXED_TSIZE1	0x198 0x000 ALT5 0x0
+#define VF610_PAD_PTC29__DCU1_B4		0x198 0x000 ALT7 0x0
+#define VF610_PAD_PTC30__GPIO_103		0x19C 0x000 ALT0 0x0
+#define VF610_PAD_PTC30__SAI1_RX_SYNC		0x19C 0x000 ALT1 0x0
+#define VF610_PAD_PTC30__DSPI1_CS2		0x19C 0x000 ALT2 0x0
+#define VF610_PAD_PTC30__SRC_RCON28		0x19C 0x000 ALT3 0x0
+#define VF610_PAD_PTC30__FB_MUXED_BE0_B		0x19C 0x000 ALT4 0x0
+#define VF610_PAD_PTC30__FB_TSIZ0		0x19C 0x000 ALT5 0x0
+#define VF610_PAD_PTC30__ADC0_SE5		0x19C 0x000 ALT6 0x0
+#define VF610_PAD_PTC30__DCU1_B5		0x19C 0x000 ALT7 0x0
+#define VF610_PAD_PTC31__GPIO_104		0x1A0 0x000 ALT0 0x0
+#define VF610_PAD_PTC31__SAI1_TX_SYNC		0x1A0 0x360 ALT1 0x1
+#define VF610_PAD_PTC31__SRC_RCON29		0x1A0 0x000 ALT3 0x0
+#define VF610_PAD_PTC31__ADC1_SE5		0x1A0 0x000 ALT6 0x0
+#define VF610_PAD_PTC31__DCU1_B6		0x1A0 0x000 ALT7 0x0
+#define VF610_PAD_PTE0__GPIO_105		0x1A4 0x000 ALT0 0x0
+#define VF610_PAD_PTE0__DCU0_HSYNC		0x1A4 0x000 ALT1 0x0
+#define VF610_PAD_PTE0__SRC_BMODE1		0x1A4 0x000 ALT2 0x0
+#define VF610_PAD_PTE0__LCD0			0x1A4 0x000 ALT4 0x0
+#define VF610_PAD_PTE0__DEBUG_OUT29		0x1A4 0x000 ALT7 0x0
+#define VF610_PAD_PTE1__GPIO_106		0x1A8 0x000 ALT0 0x0
+#define VF610_PAD_PTE1__DCU0_VSYNC		0x1A8 0x000 ALT1 0x0
+#define VF610_PAD_PTE1__SRC_BMODE0		0x1A8 0x000 ALT2 0x0
+#define VF610_PAD_PTE1__LCD1			0x1A8 0x000 ALT4 0x0
+#define VF610_PAD_PTE1__DEBUG_OUT30		0x1A8 0x000 ALT7 0x0
+#define VF610_PAD_PTE2__GPIO_107		0x1AC 0x000 ALT0 0x0
+#define VF610_PAD_PTE2__DCU0_PCLK		0x1AC 0x000 ALT1 0x0
+#define VF610_PAD_PTE2__LCD2			0x1AC 0x000 ALT4 0x0
+#define VF610_PAD_PTE2__DEBUG_OUT31		0x1AC 0x000 ALT7 0x0
+#define VF610_PAD_PTE3__GPIO_108		0x1B0 0x000 ALT0 0x0
+#define VF610_PAD_PTE3__DCU0_TAG		0x1B0 0x000 ALT1 0x0
+#define VF610_PAD_PTE3__LCD3			0x1B0 0x000 ALT4 0x0
+#define VF610_PAD_PTE3__DEBUG_OUT32		0x1B0 0x000 ALT7 0x0
+#define VF610_PAD_PTE4__GPIO_109		0x1B4 0x000 ALT0 0x0
+#define VF610_PAD_PTE4__DCU0_DE			0x1B4 0x000 ALT1 0x0
+#define VF610_PAD_PTE4__LCD4			0x1B4 0x000 ALT4 0x0
+#define VF610_PAD_PTE4__DEBUG_OUT33		0x1B4 0x000 ALT7 0x0
+#define VF610_PAD_PTE5__GPIO_110		0x1B8 0x000 ALT0 0x0
+#define VF610_PAD_PTE5__DCU0_R0			0x1B8 0x000 ALT1 0x0
+#define VF610_PAD_PTE5__LCD5			0x1B8 0x000 ALT4 0x0
+#define VF610_PAD_PTE5__DEBUG_OUT34		0x1B8 0x000 ALT7 0x0
+#define VF610_PAD_PTE6__GPIO_111		0x1BC 0x000 ALT0 0x0
+#define VF610_PAD_PTE6__DCU0_R1			0x1BC 0x000 ALT1 0x0
+#define VF610_PAD_PTE6__LCD6			0x1BC 0x000 ALT4 0x0
+#define VF610_PAD_PTE6__DEBUG_OUT35		0x1BC 0x000 ALT7 0x0
+#define VF610_PAD_PTE7__GPIO_112		0x1C0 0x000 ALT0 0x0
+#define VF610_PAD_PTE7__DCU0_R2			0x1C0 0x000 ALT1 0x0
+#define VF610_PAD_PTE7__SRC_RCON0		0x1C0 0x000 ALT3 0x0
+#define VF610_PAD_PTE7__LCD7			0x1C0 0x000 ALT4 0x0
+#define VF610_PAD_PTE7__DEBUG_OUT36		0x1C0 0x000 ALT7 0x0
+#define VF610_PAD_PTE8__GPIO_113		0x1C4 0x000 ALT0 0x0
+#define VF610_PAD_PTE8__DCU0_R3			0x1C4 0x000 ALT1 0x0
+#define VF610_PAD_PTE8__SRC_RCON1		0x1C4 0x000 ALT3 0x0
+#define VF610_PAD_PTE8__LCD8			0x1C4 0x000 ALT4 0x0
+#define VF610_PAD_PTE8__DEBUG_OUT37		0x1C4 0x000 ALT7 0x0
+#define VF610_PAD_PTE9__GPIO_114		0x1C8 0x000 ALT0 0x0
+#define VF610_PAD_PTE9__DCU0_R4			0x1C8 0x000 ALT1 0x0
+#define VF610_PAD_PTE9__SRC_RCON2		0x1C8 0x000 ALT3 0x0
+#define VF610_PAD_PTE9__LCD9			0x1C8 0x000 ALT4 0x0
+#define VF610_PAD_PTE9__DEBUG_OUT38		0x1C8 0x000 ALT7 0x0
+#define VF610_PAD_PTE10__GPIO_115		0x1CC 0x000 ALT0 0x0
+#define VF610_PAD_PTE10__DCU0_R5		0x1CC 0x000 ALT1 0x0
+#define VF610_PAD_PTE10__SRC_RCON3		0x1CC 0x000 ALT3 0x0
+#define VF610_PAD_PTE10__LCD10			0x1CC 0x000 ALT4 0x0
+#define VF610_PAD_PTE10__DEBUG_OUT39		0x1CC 0x000 ALT7 0x0
+#define VF610_PAD_PTE11__GPIO_116		0x1D0 0x000 ALT0 0x0
+#define VF610_PAD_PTE11__DCU0_R6		0x1D0 0x000 ALT1 0x0
+#define VF610_PAD_PTE11__SRC_RCON4		0x1D0 0x000 ALT3 0x0
+#define VF610_PAD_PTE11__LCD11			0x1D0 0x000 ALT4 0x0
+#define VF610_PAD_PTE11__DEBUG_OUT40		0x1D0 0x000 ALT7 0x0
+#define VF610_PAD_PTE12__GPIO_117		0x1D4 0x000 ALT0 0x0
+#define VF610_PAD_PTE12__DCU0_R7		0x1D4 0x000 ALT1 0x0
+#define VF610_PAD_PTE12__DSPI1_CS3		0x1D4 0x000 ALT2 0x0
+#define VF610_PAD_PTE12__SRC_RCON5		0x1D4 0x000 ALT3 0x0
+#define VF610_PAD_PTE12__LCD12			0x1D4 0x000 ALT4 0x0
+#define VF610_PAD_PTE12__LPT_ALT0		0x1D4 0x000 ALT7 0x0
+#define VF610_PAD_PTE13__GPIO_118		0x1D8 0x000 ALT0 0x0
+#define VF610_PAD_PTE13__DCU0_G0		0x1D8 0x000 ALT1 0x0
+#define VF610_PAD_PTE13__LCD13			0x1D8 0x000 ALT4 0x0
+#define VF610_PAD_PTE13__DEBUG_OUT41		0x1D8 0x000 ALT7 0x0
+#define VF610_PAD_PTE14__GPIO_119		0x1DC 0x000 ALT0 0x0
+#define VF610_PAD_PTE14__DCU0_G1		0x1DC 0x000 ALT1 0x0
+#define VF610_PAD_PTE14__LCD14			0x1DC 0x000 ALT4 0x0
+#define VF610_PAD_PTE14__DEBUG_OUT42		0x1DC 0x000 ALT7 0x0
+#define VF610_PAD_PTE15__GPIO_120		0x1E0 0x000 ALT0 0x0
+#define VF610_PAD_PTE15__DCU0_G2		0x1E0 0x000 ALT1 0x0
+#define VF610_PAD_PTE15__SRC_RCON6		0x1E0 0x000 ALT3 0x0
+#define VF610_PAD_PTE15__LCD15			0x1E0 0x000 ALT4 0x0
+#define VF610_PAD_PTE15__DEBUG_OUT43		0x1E0 0x000 ALT7 0x0
+#define VF610_PAD_PTE16__GPIO_121		0x1E4 0x000 ALT0 0x0
+#define VF610_PAD_PTE16__DCU0_G3		0x1E4 0x000 ALT1 0x0
+#define VF610_PAD_PTE16__SRC_RCON7		0x1E4 0x000 ALT3 0x0
+#define VF610_PAD_PTE16__LCD16			0x1E4 0x000 ALT4 0x0
+#define VF610_PAD_PTE17__GPIO_122		0x1E8 0x000 ALT0 0x0
+#define VF610_PAD_PTE17__DCU0_G4		0x1E8 0x000 ALT1 0x0
+#define VF610_PAD_PTE17__SRC_RCON8		0x1E8 0x000 ALT3 0x0
+#define VF610_PAD_PTE17__LCD17			0x1E8 0x000 ALT4 0x0
+#define VF610_PAD_PTE18__GPIO_123		0x1EC 0x000 ALT0 0x0
+#define VF610_PAD_PTE18__DCU0_G5		0x1EC 0x000 ALT1 0x0
+#define VF610_PAD_PTE18__SRC_RCON9		0x1EC 0x000 ALT3 0x0
+#define VF610_PAD_PTE18__LCD18			0x1EC 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__GPIO_124		0x1F0 0x000 ALT0 0x0
+#define VF610_PAD_PTE19__DCU0_G6		0x1F0 0x000 ALT1 0x0
+#define VF610_PAD_PTE19__SRC_RCON10		0x1F0 0x000 ALT3 0x0
+#define VF610_PAD_PTE19__LCD19			0x1F0 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__I2C0_SCL		0x1F0 0x33C ALT5 0x3
+#define VF610_PAD_PTE20__GPIO_125		0x1F4 0x000 ALT0 0x0
+#define VF610_PAD_PTE20__DCU0_G7		0x1F4 0x000 ALT1 0x0
+#define VF610_PAD_PTE20__SRC_RCON11		0x1F4 0x000 ALT3 0x0
+#define VF610_PAD_PTE20__LCD20			0x1F4 0x000 ALT4 0x0
+#define VF610_PAD_PTE20__I2C0_SDA		0x1F4 0x340 ALT5 0x3
+#define VF610_PAD_PTE20__EWM_IN			0x1F4 0x000 ALT7 0x0
+#define VF610_PAD_PTE21__GPIO_126		0x1F8 0x000 ALT0 0x0
+#define VF610_PAD_PTE21__DCU0_B0		0x1F8 0x000 ALT1 0x0
+#define VF610_PAD_PTE21__LCD21			0x1F8 0x000 ALT4 0x0
+#define VF610_PAD_PTE22__GPIO_127		0x1FC 0x000 ALT0 0x0
+#define VF610_PAD_PTE22__DCU0_B1		0x1FC 0x000 ALT1 0x0
+#define VF610_PAD_PTE22__LCD22			0x1FC 0x000 ALT4 0x0
+#define VF610_PAD_PTE23__GPIO_128		0x200 0x000 ALT0 0x0
+#define VF610_PAD_PTE23__DCU0_B2		0x200 0x000 ALT1 0x0
+#define VF610_PAD_PTE23__SRC_RCON12		0x200 0x000 ALT3 0x0
+#define VF610_PAD_PTE23__LCD23			0x200 0x000 ALT4 0x0
+#define VF610_PAD_PTE24__GPIO_129		0x204 0x000 ALT0 0x0
+#define VF610_PAD_PTE24__DCU0_B3		0x204 0x000 ALT1 0x0
+#define VF610_PAD_PTE24__SRC_RCON13		0x204 0x000 ALT3 0x0
+#define VF610_PAD_PTE24__LCD24			0x204 0x000 ALT4 0x0
+#define VF610_PAD_PTE25__GPIO_130		0x208 0x000 ALT0 0x0
+#define VF610_PAD_PTE25__DCU0_B4		0x208 0x000 ALT1 0x0
+#define VF610_PAD_PTE25__SRC_RCON14		0x208 0x000 ALT3 0x0
+#define VF610_PAD_PTE25__LCD25			0x208 0x000 ALT4 0x0
+#define VF610_PAD_PTE26__GPIO_131		0x20C 0x000 ALT0 0x0
+#define VF610_PAD_PTE26__DCU0_B5		0x20C 0x000 ALT1 0x0
+#define VF610_PAD_PTE26__SRC_RCON15		0x20C 0x000 ALT3 0x0
+#define VF610_PAD_PTE26__LCD26			0x20C 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__GPIO_132		0x210 0x000 ALT0 0x0
+#define VF610_PAD_PTE27__DCU0_B6		0x210 0x000 ALT1 0x0
+#define VF610_PAD_PTE27__SRC_RCON16		0x210 0x000 ALT3 0x0
+#define VF610_PAD_PTE27__LCD27			0x210 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__I2C1_SCL		0x210 0x344 ALT5 0x3
+#define VF610_PAD_PTE28__GPIO_133		0x214 0x000 ALT0 0x0
+#define VF610_PAD_PTE28__DCU0_B7		0x214 0x000 ALT1 0x0
+#define VF610_PAD_PTE28__SRC_RCON17		0x214 0x000 ALT3 0x0
+#define VF610_PAD_PTE28__LCD28			0x214 0x000 ALT4 0x0
+#define VF610_PAD_PTE28__I2C1_SDA		0x214 0x348 ALT5 0x3
+#define VF610_PAD_PTE28__EWM_OUT		0x214 0x000 ALT7 0x0
+#define VF610_PAD_PTA7__GPIO_134		0x218 0x000 ALT0 0x0
+#define VF610_PAD_PTA7__VIU_PIX_CLK		0x218 0x3AC ALT1 0x1
+
+#endif
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
new file mode 100644
index 0000000..7b6a46c
--- /dev/null
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -0,0 +1,464 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton.dtsi"
+#include "vf610-pinfunc.h"
+#include <dt-bindings/clock/vf610-clock.h>
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a5";
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sxosc {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		fxosc {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		aips0: aips-bus at 40000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-parent = <&intc>;
+			reg = <0x40000000 0x70000>;
+			ranges;
+
+			intc: interrupt-controller at 40002000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				reg = <0x40003000 0x1000>,
+				      <0x40002100 0x100>;
+			};
+
+			L2: l2-cache at 40006000 {
+				compatible = "arm,pl310-cache";
+				reg = <0x40006000 0x1000>;
+				cache-unified;
+				cache-level = <2>;
+				arm,data-latency = <1 1 1>;
+				arm,tag-latency = <2 2 2>;
+			};
+
+			uart0: serial at 40027000 {
+				compatible = "fsl,vf610-lpuart";
+				reg = <0x40027000 0x1000>;
+				interrupts = <0 61 0x00>;
+				clocks = <&clks VF610_CLK_UART0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart1: serial at 40028000 {
+				compatible = "fsl,vf610-lpuart";
+				reg = <0x40028000 0x1000>;
+				interrupts = <0 62 0x04>;
+				clocks = <&clks VF610_CLK_UART1>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart2: serial at 40029000 {
+				compatible = "fsl,vf610-lpuart";
+				reg = <0x40029000 0x1000>;
+				interrupts = <0 63 0x04>;
+				clocks = <&clks VF610_CLK_UART2>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart3: serial at 4002a000 {
+				compatible = "fsl,vf610-lpuart";
+				reg = <0x4002a000 0x1000>;
+				interrupts = <0 64 0x04>;
+				clocks = <&clks VF610_CLK_UART3>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			sai2: sai at 40031000 {
+				compatible = "fsl,vf610-sai";
+				reg = <0x40031000 0x1000>;
+				interrupts = <0 86 0x04>;
+				clocks = <&clks VF610_CLK_SAI2>;
+				clock-names = "sai";
+				status = "disabled";
+			};
+
+			pit: pit at 40037000 {
+				compatible = "fsl,vf610-pit";
+				reg = <0x40037000 0x1000>;
+				interrupts = <0 39 0x04>;
+				clocks = <&clks VF610_CLK_PIT>;
+				clock-names = "pit";
+			};
+
+			wdog at 4003e000 {
+				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
+				reg = <0x4003e000 0x1000>;
+				clocks = <&clks VF610_CLK_WDT>;
+				clock-names = "wdog";
+			};
+
+			qspi0: quadspi at 40044000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-qspi";
+				reg = <0x40044000 0x1000>;
+				interrupts = <0 24 0x04>;
+				clocks = <&clks VF610_CLK_QSPI0_EN>,
+					<&clks VF610_CLK_QSPI0>;
+				clock-names = "qspi_en", "qspi";
+				status = "disabled";
+			};
+
+			iomuxc: iomuxc at 40048000 {
+				compatible = "fsl,vf610-iomuxc";
+				reg = <0x40048000 0x1000>;
+				#gpio-range-cells = <2>;
+
+				/* functions and groups pins */
+
+				dcu0 {
+					pinctrl_dcu0_1: dcu0grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTB8__GPIO_30		0x42
+						VF610_PAD_PTE0__DCU0_HSYNC	0x42
+						VF610_PAD_PTE1__DCU0_VSYNC	0x42
+						VF610_PAD_PTE2__DCU0_PCLK	0x42
+						VF610_PAD_PTE4__DCU0_DE		0x42
+						VF610_PAD_PTE5__DCU0_R0		0x42
+						VF610_PAD_PTE6__DCU0_R1		0x42
+						VF610_PAD_PTE7__DCU0_R2		0x42
+						VF610_PAD_PTE8__DCU0_R3		0x42
+						VF610_PAD_PTE9__DCU0_R4		0x42
+						VF610_PAD_PTE10__DCU0_R5	0x42
+						VF610_PAD_PTE11__DCU0_R6	0x42
+						VF610_PAD_PTE12__DCU0_R7	0x42
+						VF610_PAD_PTE13__DCU0_G0	0x42
+						VF610_PAD_PTE14__DCU0_G1	0x42
+						VF610_PAD_PTE15__DCU0_G2	0x42
+						VF610_PAD_PTE16__DCU0_G3	0x42
+						VF610_PAD_PTE17__DCU0_G4	0x42
+						VF610_PAD_PTE18__DCU0_G5	0x42
+						VF610_PAD_PTE19__DCU0_G6	0x42
+						VF610_PAD_PTE20__DCU0_G7	0x42
+						VF610_PAD_PTE21__DCU0_B0	0x42
+						VF610_PAD_PTE22__DCU0_B1	0x42
+						VF610_PAD_PTE23__DCU0_B2	0x42
+						VF610_PAD_PTE24__DCU0_B3	0x42
+						VF610_PAD_PTE25__DCU0_B4	0x42
+						VF610_PAD_PTE26__DCU0_B5	0x42
+						VF610_PAD_PTE27__DCU0_B6	0x42
+						VF610_PAD_PTE28__DCU0_B7	0x42
+						>;
+					};
+				};
+
+				dspi0 {
+					pinctrl_dspi0_1: dspi0grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTB19__DSPI0_CS0	0x1182
+						VF610_PAD_PTB20__DSPI0_SIN	0x1181
+						VF610_PAD_PTB21__DSPI0_SOUT	0x1182
+						VF610_PAD_PTB22__DSPI0_SCK	0x1182
+						>;
+					};
+				};
+
+				esdhc1 {
+					pinctrl_esdhc1_1: esdhc1grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
+						VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
+						VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
+						VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
+						VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
+						VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
+						VF610_PAD_PTA7__GPIO_134	0x219d
+						>;
+					};
+				};
+
+				fec0 {
+					pinctrl_fec0_1: fec0grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTA6__RMII_CLKIN	0x30d1
+						VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d3
+						VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d1
+						VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
+						VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
+						VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
+						VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
+						VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
+						VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
+						VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
+						>;
+					};
+				};
+
+				fec1 {
+					pinctrl_fec1_1: fec1grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
+						VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
+						VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
+						VF610_PAD_PTC12__ENET_RMII_RXD1		0x30d1
+						VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
+						VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
+						VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
+						VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
+						VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
+						>;
+					};
+				};
+
+				i2c0 {
+					pinctrl_i2c0_1: i2c0grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTB14__I2C0_SCL	0x30d3
+						VF610_PAD_PTB15__I2C0_SDA	0x30d3
+						>;
+					};
+				};
+
+				pwm0 {
+					pinctrl_pwm0_1: pwm0grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTB0__FTM0_CH0	0x1582
+						VF610_PAD_PTB1__FTM0_CH1	0x1582
+						VF610_PAD_PTB2__FTM0_CH2	0x1582
+						VF610_PAD_PTB3__FTM0_CH3	0x1582
+						VF610_PAD_PTB6__FTM0_CH6	0x1582
+						VF610_PAD_PTB7__FTM0_CH7	0x1582
+						>;
+					};
+				};
+
+				qspi0 {
+					pinctrl_qspi0_1: qspi0grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTD0__QSPI0_A_QSCK	0x307b
+						VF610_PAD_PTD1__QSPI0_A_CS0	0x307f
+						VF610_PAD_PTD2__QSPI0_A_DATA3	0x3073
+						VF610_PAD_PTD3__QSPI0_A_DATA2	0x3073
+						VF610_PAD_PTD4__QSPI0_A_DATA1	0x3073
+						VF610_PAD_PTD5__QSPI0_A_DATA0	0x307b
+						VF610_PAD_PTD7__QSPI0_B_QSCK	0x307b
+						VF610_PAD_PTD8__QSPI0_B_CS0	0x307f
+						VF610_PAD_PTD9__QSPI0_B_DATA3	0x3073
+						VF610_PAD_PTD10__QSPI0_B_DATA2	0x3073
+						VF610_PAD_PTD11__QSPI0_B_DATA1	0x3073
+						VF610_PAD_PTD12__QSPI0_B_DATA0	0x307b
+						>;
+					};
+				};
+
+				sai2 {
+					pinctrl_sai2_1: sai2grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTA16__SAI2_TX_BCLK	0x02ed
+						VF610_PAD_PTA18__SAI2_TX_DATA	0x02ee
+						VF610_PAD_PTA19__SAI2_TX_SYNC	0x02ed
+						VF610_PAD_PTA21__SAI2_RX_BCLK	0x02ed
+						VF610_PAD_PTA22__SAI2_RX_DATA	0x02ed
+						VF610_PAD_PTA23__SAI2_RX_SYNC	0x02ed
+						VF610_PAD_PTB18__EXT_AUDIO_MCLK	0x02ed
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp_1 {
+						fsl,pins = <
+						VF610_PAD_PTB4__UART1_TX	0x21a2
+						VF610_PAD_PTB5__UART1_RX	0x21a1
+						>;
+					};
+				};
+
+				usbvbus {
+					pinctrl_usbvbus_1: usbvbusgrp_1 {
+						fsl,pins = <
+						VF610_PAD_PTA24__USB1_VBUS_EN	0x219c
+						VF610_PAD_PTA16__USB0_VBUS_EN	0x219c
+						>;
+					};
+				};
+
+			};
+
+			gpio1: gpio at 40049000 {
+				compatible = "fsl,vf610-gpio";
+				reg = <0x40049000 0x1000 0x400ff000 0x40>;
+				interrupts = <0 107 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 32>;
+			};
+
+			gpio2: gpio at 4004a000 {
+				compatible = "fsl,vf610-gpio";
+				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+				interrupts = <0 108 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 32 32>;
+			};
+
+			gpio3: gpio at 4004b000 {
+				compatible = "fsl,vf610-gpio";
+				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+				interrupts = <0 109 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 64 32>;
+			};
+
+			gpio4: gpio at 4004c000 {
+				compatible = "fsl,vf610-gpio";
+				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+				interrupts = <0 110 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 96 32>;
+			};
+
+			gpio5: gpio at 4004d000 {
+				compatible = "fsl,vf610-gpio";
+				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+				interrupts = <0 111 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 128 7>;
+			};
+
+			anatop at 40050000 {
+				compatible = "fsl,vf610-anatop";
+				reg = <0x40050000 0x1000>;
+			};
+
+			i2c0: i2c at 40066000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x40066000 0x1000>;
+				interrupts =<0 71 0x04>;
+				clocks = <&clks VF610_CLK_I2C0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			clks: ccm at 4006b000 {
+				compatible = "fsl,vf610-ccm";
+				reg = <0x4006b000 0x1000>;
+				#clock-cells = <1>;
+			};
+		};
+
+		aips1: aips-bus at 40080000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40080000 0x80000>;
+			ranges;
+
+			uart4: serial at 400a9000 {
+				compatible = "fsl,vf610-lpuart";
+				reg = <0x400a9000 0x1000>;
+				interrupts = <0 65 0x04>;
+				clocks = <&clks VF610_CLK_UART4>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			uart5: serial at 400aa000 {
+				compatible = "fsl,vf610-lpuart";
+				reg = <0x400aa000 0x1000>;
+				interrupts = <0 66 0x04>;
+				clocks = <&clks VF610_CLK_UART5>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			fec0: ethernet at 400d0000 {
+				compatible = "fsl,mvf600-fec";
+				reg = <0x400d0000 0x1000>;
+				interrupts = <0 78 0x04>;
+				clocks = <&clks VF610_CLK_ENET>,
+					<&clks VF610_CLK_ENET>,
+					<&clks VF610_CLK_ENET>;
+				clock-names = "ipg", "ahb", "ptp";
+				status = "disabled";
+			};
+
+			fec1: ethernet at 400d1000 {
+				compatible = "fsl,mvf600-fec";
+				reg = <0x400d1000 0x1000>;
+				interrupts = <0 79 0x04>;
+				clocks = <&clks VF610_CLK_ENET>,
+					<&clks VF610_CLK_ENET>,
+					<&clks VF610_CLK_ENET>;
+				clock-names = "ipg", "ahb", "ptp";
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.8.0




From b35083 at freescale.com  Tue May 28 05:12:19 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:12:19 +0800
Subject: [PATCH v4 0/4] Add initial Freescale Vybrid VF610 support
Message-ID: <1369732343-2982-1-git-send-email-b35083@freescale.com>

  Vybird VF610 is a heterogeneous dual-core eMPU using ARM Cortex-A5 and
Cortex-M4 cores. The kernel is implemented on the Cortex-A5 core.
  This SoC shares some IPs with I.MX serials, such as FEC, ESDHC, WATCHDOG,
I2C, ASRC and ESAI, this SOC also shares some IPs with ColdFire platform,
such as eDMA and DSPI, and this SOC have its own IPs such as PIT, SAI, UART,
QuadSPI and DCU.
  More documents for this soc can be found at:
  http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=1&sr=5
  http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID

changes in v4:
	Follow internal suggestions to name the soc name as VF610.
	Use common of_clk_init() call to initialize clocks.
	Name lpuart device compatible string to "fsl,vf610-lpuart".
	Remove "fsl,mvf-fec" compatible string.
	Remove node of QuadSPI, I2C, SAI, and sound until driver accepted.
changes in v3:
	Split one big arch support patch to small patches.
	Use DTC macro support to define these clock IDs.
	Remove unused #include header lines.
	Name clocks close to reference manual.
	Use common mxc restart function.
	Define mvf600 pinfunc ID as <mux_reg input_reg mux_mode input_val>.
	Sort dts node by alphabet order of labels.
changes in v2:
	Add more clks definitions.
	Add pinctrl support based on IMX new pinctrl framework.

Jingchang Lu (4):
  ARM: imx: add VF610 clock support
  ARM: imx: add initial support for VF610
  ARM: dts: add SoC level device tree source for VF610
  ARM: dts: add initial VF610 Tower board dts support

Documentation/devicetree/bindings/clock/vf610-clock.txt |  26 ++
 arch/arm/boot/dts/Makefile                              |   3 +-
 arch/arm/boot/dts/vf610-pinfunc.h                       | 810 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/vf610-twr.dts                         |  57 +++
 arch/arm/boot/dts/vf610.dtsi                            | 464 +++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                               |  15 +
 arch/arm/mach-imx/Makefile                              |   2 +
 arch/arm/mach-imx/clk-vf610.c                           | 319 ++++++++++++++
 arch/arm/mach-imx/mach-vf610.c                          |  48 +++
 include/dt-bindings/clock/vf610-clock.h                 | 163 ++++++++
 10 files changed, 1906 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/vf610-clock.txt
 create mode 100644 arch/arm/boot/dts/vf610-pinfunc.h
 create mode 100644 arch/arm/boot/dts/vf610-twr.dts
 create mode 100644 arch/arm/boot/dts/vf610.dtsi
 create mode 100644 arch/arm/mach-imx/clk-vf610.c
 create mode 100644 arch/arm/mach-imx/mach-vf610.c
 create mode 100644 include/dt-bindings/clock/vf610-clock.h




From b35083 at freescale.com  Tue May 28 05:12:21 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:12:21 +0800
Subject: [PATCH v4 2/4] ARM: imx: add initial support for VF610
In-Reply-To: <1369732343-2982-1-git-send-email-b35083@freescale.com>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
Message-ID: <1369732343-2982-3-git-send-email-b35083@freescale.com>

Add initial support for Freescale Vybrid VF610 SoC.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  Follow internal suggestions to name the soc name as VF610.
  Use of_clk_init() call initilizing clocks.
v3:
  Split one big arch support patch into small patches.
  Remove unused #include header lines.
  Use common mxc restart function.

 arch/arm/mach-imx/Kconfig      | 15 +++++++++++++
 arch/arm/mach-imx/Makefile     |  2 ++
 arch/arm/mach-imx/mach-vf610.c | 48 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 65 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-vf610.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a402248..b7eddbd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -835,6 +835,21 @@ config SOC_IMX6SL
 	help
 	  This enables support for Freescale i.MX6 SoloLite processor.
 
+config SOC_VF610
+	bool "Vybrid Family VF610 support"
+	select CPU_V7
+	select ARM_GIC
+	select CLKSRC_OF
+	select PINCTRL
+	select PINCTRL_VF610
+	select VF_PIT_TIMER
+	select PL310_ERRATA_588369 if CACHE_PL310
+	select PL310_ERRATA_727915 if CACHE_PL310
+	select PL310_ERRATA_769419 if CACHE_PL310
+
+	help
+	  This enable support for Freescale Vybrid VF610 processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 2a4754d..054f039 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -112,4 +112,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
+obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
new file mode 100644
index 0000000..709fac3
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "common.h"
+
+static void __init vf610_init_machine(void)
+{
+	mxc_arch_reset_init_dt();
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init vf610_init_irq(void)
+{
+	l2x0_of_init(0, ~0UL);
+	irqchip_init();
+}
+
+static void __init vf610_init_time(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+static const char *vf610_dt_compat[] __initdata = {
+	"fsl,vf610",
+	NULL,
+};
+
+DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
+	.init_irq	= vf610_init_irq,
+	.init_time	= vf610_init_time,
+	.init_machine   = vf610_init_machine,
+	.dt_compat	= vf610_dt_compat,
+	.restart	= mxc_restart,
+MACHINE_END
-- 
1.8.0




From padma.v at samsung.com  Tue May 28 06:02:54 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 15:32:54 +0530
Subject: [PATCH V3 0/4] clk: Samsung: audss: Register audio subsytem clocks
 using common clk framework
Message-ID: <1369735378-10003-1-git-send-email-padma.v@samsung.com>

Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem
has a internal clock controller which controls i2s0 and pcm0 clocks. This patch
series adds the Samsung audio subsytem clock to the common clock framework and
provides the I2S controllers clock information in the dtsi file.

This patch series is made based on Kukjin Kim for-next branch

Changes since V2:
	- Removed s5pv210 compatible name from driver as it is
	  not yet supported which is different from Exynos series
	  audio subsystem clock conroller.
	- Removed clkdev lookup support and added alias names in
	  the i2s0 controller node.
Changes since V1:
        - Reworked on all review comments by Sylwester Nawrocki
        - Added a header file for all clock indexes as requested by Sylwester
        - Added different compatible names for s5pv210, exynos4 and exynos5
        - Registered the pcm clocks with common clock framework

Padmavathi Venna (4):
  ARM: samsung: use #include for all device trees
  clk: samsung: register audio subsystem clocks using common clock
    framework
  ARM: dts: add Exynos audio subsystem clock controller node
  ARM: dts: add clock provider information for i2s controllers in
    Exynos5250

 .../bindings/clock/clk-samsung-audss.txt           |   64 ++++++++++
 arch/arm/boot/dts/exynos4.dtsi                     |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts            |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts          |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts             |    2 +-
 arch/arm/boot/dts/exynos4210-universal_c210.dts    |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi                  |    4 +-
 arch/arm/boot/dts/exynos4212.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts           |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts            |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts          |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi                  |    4 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250.dtsi                  |   23 +++-
 arch/arm/boot/dts/exynos5440-sd5v1.dts             |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts          |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi                  |    2 +-
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |    2 +-
 arch/arm/boot/dts/s3c2416.dtsi                     |    4 +-
 arch/arm/boot/dts/s3c24xx.dtsi                     |    2 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-samsung-audss.c            |  133 ++++++++++++++++++++
 include/dt-bindings/clk/samsung-audss-clk.h        |   25 ++++
 26 files changed, 269 insertions(+), 27 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
 create mode 100644 drivers/clk/samsung/clk-samsung-audss.c
 create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h

-- 
1.7.4.4



From padma.v at samsung.com  Tue May 28 06:02:55 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 15:32:55 +0530
Subject: [PATCH V3 1/4] ARM: samsung: use #include for all device trees
In-Reply-To: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
References: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
Message-ID: <1369735378-10003-2-git-send-email-padma.v@samsung.com>

Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 arch/arm/boot/dts/exynos4.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts         |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts       |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts          |    2 +-
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos4212.dtsi               |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts        |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts         |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts       |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi               |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts        |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts           |    4 ++--
 arch/arm/boot/dts/exynos5250.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos5440-sd5v1.dts          |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts       |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi               |    2 +-
 arch/arm/boot/dts/s3c2416-smdk2416.dts          |    2 +-
 arch/arm/boot/dts/s3c2416.dtsi                  |    4 ++--
 arch/arm/boot/dts/s3c24xx.dtsi                  |    2 +-
 22 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..75c2756 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..7bb8d48 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Hardkernel ODROID-X board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..df097b5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index c52b01f..1e816fa 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Samsung SMDK evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389..e743e67 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7..8896bb5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76..8e27120 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792..f2a025e 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb..fd711e2 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "exynos5250.dtsi"
+#include "cros5250-common.dtsi"
 
 / {
 	model = "Google Snow";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9dfc6de..bccda67 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "skeleton.dtsi"
+#include "exynos5250-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos5250";
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b5..5e84c5f 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SD5v1 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..2fd6646 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..13b40b3 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,exynos5440";
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index ad1dd09..59594cf 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "s3c2416.dtsi"
+#include "s3c2416.dtsi"
 
 / {
 	model = "SMDK2416";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6809324..e6555bd 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "s3c24xx.dtsi"
-/include/ "s3c2416-pinctrl.dtsi"
+#include "s3c24xx.dtsi"
+#include "s3c2416-pinctrl.dtsi"
 
 / {
 	model = "Samsung S3C2416 SoC";
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
index cab46ff..2d1d7dc 100644
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,s3c24xx";
-- 
1.7.4.4



From padma.v at samsung.com  Tue May 28 06:02:56 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 15:32:56 +0530
Subject: [PATCH V3 2/4] clk: samsung: register audio subsystem clocks using
 common clock framework
In-Reply-To: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
References: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
Message-ID: <1369735378-10003-3-git-send-email-padma.v@samsung.com>

Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 .../bindings/clock/clk-samsung-audss.txt           |   64 ++++++++++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-samsung-audss.c            |  133 ++++++++++++++++++++
 include/dt-bindings/clk/samsung-audss-clk.h        |   25 ++++
 4 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
 create mode 100644 drivers/clk/samsung/clk-samsung-audss.c
 create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h

diff --git a/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
new file mode 100644
index 0000000..07a7ed4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
+  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock           ID      SoC (if specific)
+-----------------------------------------------
+
+mout_audss      0
+mout_i2s        1
+dout_srp        2
+dout_bus        3
+dout_i2s        4
+srp_clk         5
+i2s_bus         6
+sclk_i2s        7
+pcm_bus         8
+sclk_pcm        9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller at 3810000 {
+	compatible = "samsung,exynos5250-audss-clock";
+	reg = <0x03810000 0x0C>;
+	#clock-cells = <1>;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+i2s0: i2s at 03830000 {
+	compatible = "samsung,i2s-v5";
+	reg = <0x03830000 0x100>;
+	dmas = <&pdma0 10
+		&pdma0 9
+		&pdma0 8>;
+	dma-names = "tx", "rx", "tx-sec";
+	clocks = <&clock_audss SAMSUNG_I2S_BUS>,
+		<&clock_audss SAMSUNG_I2S_BUS>,
+		<&clock_audss SAMSUNG_SCLK_I2S>,
+		<&clock_audss SAMSUNG_MOUT_AUDSS>,
+		<&clock_audss SAMSUNG_MOUT_I2S>;
+	clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
+	"mout_audss", "mout_i2s";
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..5425fa8 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
+obj-$(CONFIG_PLAT_SAMSUNG)	+= clk-samsung-audss.o
diff --git a/drivers/clk/samsung/clk-samsung-audss.c b/drivers/clk/samsung/clk-samsung-audss.c
new file mode 100644
index 0000000..534cdef
--- /dev/null
+++ b/drivers/clk/samsung/clk-samsung-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clk/samsung-audss-clk.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+	{ASS_CLK_SRC,  0},
+	{ASS_CLK_DIV,  0},
+	{ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+
+#ifdef CONFIG_PM_SLEEP
+static int samsung_audss_clk_suspend(void)
+{
+	int i;
+
+	for (i = 0; i < 3; i++)
+		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+	return 0;
+}
+
+static void samsung_audss_clk_resume(void)
+{
+	int i;
+
+	for (i = 0; i < 3; i++)
+		writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops samsung_audss_clk_syscore_ops = {
+	.suspend	= samsung_audss_clk_suspend,
+	.resume		= samsung_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* register samsung_audss clocks */
+void __init samsung_audss_clk_init(struct device_node *np)
+{
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: failed to map audss registers\n", __func__);
+		return;
+	}
+
+	clk_table = kzalloc(sizeof(struct clk *) * SAMSUNG_AUDSS_MAX_CLKS,
+				GFP_KERNEL);
+	if (!clk_table) {
+		pr_err("%s: could not allocate clk lookup table\n", __func__);
+		return;
+	}
+
+	clk_data.clks = clk_table;
+	clk_data.clk_num = SAMSUNG_AUDSS_MAX_CLKS;
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	clk_table[SAMSUNG_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+				mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
+				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
+	clk_table[SAMSUNG_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+				mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
+				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+
+	clk_table[SAMSUNG_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+				"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
+				0, &lock);
+
+	clk_table[SAMSUNG_DOUT_BUS] = clk_register_divider(NULL, "dout_bus",
+				"dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0,
+				&lock);
+
+	clk_table[SAMSUNG_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
+				&lock);
+
+	clk_table[SAMSUNG_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+				"dout_srp", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+	clk_table[SAMSUNG_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+				"dout_bus", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 2, 0, &lock);
+
+	clk_table[SAMSUNG_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+				"dout_i2s", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 3, 0, &lock);
+
+	clk_table[SAMSUNG_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+				 "sclk_pcm", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 4, 0, &lock);
+
+	clk_table[SAMSUNG_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+				"div_pcm0", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 5, 0, &lock);
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&samsung_audss_clk_syscore_ops);
+#endif
+
+	pr_info("Exynos: Audss: clock setup completed\n");
+}
+CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
+		samsung_audss_clk_init);
+CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
+		samsung_audss_clk_init);
diff --git a/include/dt-bindings/clk/samsung-audss-clk.h b/include/dt-bindings/clk/samsung-audss-clk.h
new file mode 100644
index 0000000..d335555
--- /dev/null
+++ b/include/dt-bindings/clk/samsung-audss-clk.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and samsung audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SAMSUNG_AUDSS_H
+#define _DT_BINDINGS_CLK_SAMSUNG_AUDSS_H
+
+#define SAMSUNG_MOUT_AUDSS	0
+#define SAMSUNG_MOUT_I2S	1
+#define SAMSUNG_DOUT_SRP	2
+#define SAMSUNG_DOUT_BUS	3
+#define SAMSUNG_DOUT_I2S	4
+#define SAMSUNG_SRP_CLK		5
+#define SAMSUNG_I2S_BUS		6
+#define SAMSUNG_SCLK_I2S	7
+#define SAMSUNG_PCM_BUS		8
+#define SAMSUNG_SCLK_PCM	9
+
+#define SAMSUNG_AUDSS_MAX_CLKS	10
+
+#endif
-- 
1.7.4.4



From padma.v at samsung.com  Tue May 28 06:02:58 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 15:32:58 +0530
Subject: [PATCH V3 4/4] ARM: dts: add clock provider information for i2s
 controllers in Exynos5250
In-Reply-To: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
References: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
Message-ID: <1369735378-10003-5-git-send-email-padma.v@samsung.com>

Add clock lookup information for i2s controllers on exynos5250 SoC.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 388983e..7154e3d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
 #include "skeleton.dtsi"
 #include "exynos5250-pinctrl.dtsi"
 
+#include <dt-bindings/clk/samsung-audss-clk.h>
+
 / {
 	compatible = "samsung,exynos5250";
 	interrupt-parent = <&gic>;
@@ -457,6 +459,13 @@
 			&pdma0 9
 			&pdma0 8>;
 		dma-names = "tx", "rx", "tx-sec";
+		clocks = <&clock_audss SAMSUNG_I2S_BUS>,
+			<&clock_audss SAMSUNG_I2S_BUS>,
+			<&clock_audss SAMSUNG_SCLK_I2S>,
+			<&clock_audss SAMSUNG_MOUT_AUDSS>,
+			<&clock_audss SAMSUNG_MOUT_I2S>;
+		clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
+				"mout_audss", "mout_i2s";
 		samsung,supports-6ch;
 		samsung,supports-rstclr;
 		samsung,supports-secdai;
@@ -471,6 +480,8 @@
 		dmas = <&pdma1 12
 			&pdma1 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 307>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_bus>;
 	};
@@ -481,6 +492,8 @@
 		dmas = <&pdma0 12
 			&pdma0 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 308>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s2_bus>;
 	};
-- 
1.7.4.4



From padma.v at samsung.com  Tue May 28 06:02:57 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 15:32:57 +0530
Subject: [PATCH V3 3/4] ARM: dts: add Exynos audio subsystem clock controller
 node
In-Reply-To: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
References: <1369735378-10003-1-git-send-email-padma.v@samsung.com>
Message-ID: <1369735378-10003-4-git-send-email-padma.v@samsung.com>

Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index bccda67..388983e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
 		#clock-cells = <1>;
 	};
 
+	clock_audss: audss-clock-controller at 3810000 {
+		compatible = "samsung,exynos5250-audss-clock";
+		reg = <0x03810000 0x0C>;
+		#clock-cells = <1>;
+	};
+
 	gic:interrupt-controller at 10481000 {
 		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
-- 
1.7.4.4



From b35083 at freescale.com  Tue May 28 05:21:39 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:21:39 +0800
Subject: [PATCH v5] clocksource: add Freescale Vybrid pit timer support
Message-ID: <1369732899-17142-1-git-send-email-b35083@freescale.com>

Add Freescale Vybrid Family period interrupt timer support.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v5:
 Follow internal suggestions to name the SoC family as VF.
 Add comment for min and max clockevent delta.
 Add clockevent device irq initialization.
 Remove IRQF_DISABLED flag.
v4:
  Use family name names driver and symbol instead of SoC name.
  Remove redundant code.
  Use BUG_ON instead of WARN_ON.
  Add necessory comment information.
v3:
  Move the pit driver adding from arch to drivers/clocksource.
v2:
  Use CLOCKSOURCE_OF_DECLARE init pit timer.
  Add ONESHOT mode support.

 drivers/clocksource/Kconfig        |   5 +
 drivers/clocksource/Makefile       |   1 +
 drivers/clocksource/vf_pit_timer.c | 194 +++++++++++++++++++++++++++++++++++++
 3 files changed, 200 insertions(+)
 create mode 100644 drivers/clocksource/vf_pit_timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f151c6c..0a04257 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
 	  Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
 	  for all devicetree enabled platforms. This driver will be
 	  needed only on systems that do not have the Exynos MCT available.
+
+config VF_PIT_TIMER
+	bool
+	help
+	  Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c7..36a9ac1 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
 obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
+obj-$(CONFIG_VF_PIT_TIMER)	+= vf_pit_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
new file mode 100644
index 0000000..598399d
--- /dev/null
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/sched_clock.h>
+
+/*
+ * Each pit takes 0x10 Bytes register space
+ */
+#define PITMCR		0x00
+#define PIT0_OFFSET	0x100
+#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
+#define PITLDVAL	0x00
+#define PITCVAL		0x04
+#define PITTCTRL	0x08
+#define PITTFLG		0x0c
+
+#define PITMCR_MDIS	(0x1 << 1)
+
+#define PITTCTRL_TEN	(0x1 << 0)
+#define PITTCTRL_TIE	(0x1 << 1)
+#define PITCTRL_CHN	(0x1 << 2)
+
+#define PITTFLG_TIF	0x1
+
+static void __iomem *clksrc_base;
+static void __iomem *clkevt_base;
+static unsigned long cycle_per_jiffy;
+
+static inline void pit_timer_enable(void)
+{
+	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_timer_disable(void)
+{
+	__raw_writel(0, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_acknowledge(void)
+{
+	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+}
+
+static unsigned int pit_read_sched_clock(void)
+{
+	return __raw_readl(clksrc_base + PITCVAL);
+}
+
+static int __init pit_clocksource_init(unsigned long rate)
+{
+	/* set the max load value and start the clock source counter */
+	__raw_writel(0, clksrc_base + PITTCTRL);
+	__raw_writel(~0UL, clksrc_base + PITLDVAL);
+	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
+
+	setup_sched_clock(pit_read_sched_clock, 32, rate);
+	return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
+			300, 32, clocksource_mmio_readl_down);
+}
+
+static int pit_set_next_event(unsigned long delta,
+				struct clock_event_device *unused)
+{
+	/*
+	 * set a new value to PITLDVAL register will not restart the timer,
+	 * to abort the current cycle and start a timer period with the new
+	 * value, the timer must be disabled and enabled again.
+	 * and the PITLAVAL should be set to delta minus one according to pit
+	 * hardware requirement.
+	 */
+	pit_timer_disable();
+	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
+	pit_timer_enable();
+
+	return 0;
+}
+
+static void pit_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		pit_set_next_event(cycle_per_jiffy, evt);
+		break;
+	default:
+		break;
+	}
+}
+
+static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	pit_irq_acknowledge();
+
+	/*
+	 * pit hardware doesn't support oneshot, it will generate an interrupt
+	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,
+	 * and start the counter again. So software need to disable the timer
+	 * to stop the counter loop in ONESHOT mode.
+	 */
+	if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
+		pit_timer_disable();
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_pit = {
+	.name		= "VF pit timer",
+	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode	= pit_set_mode,
+	.set_next_event	= pit_set_next_event,
+	.rating		= 300,
+};
+
+static struct irqaction pit_timer_irq = {
+	.name		= "VF pit timer",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= pit_timer_interrupt,
+	.dev_id		= &clockevent_pit,
+};
+
+static int __init pit_clockevent_init(unsigned long rate, int irq)
+{
+	__raw_writel(0, clkevt_base + PITTCTRL);
+	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+
+	BUG_ON(setup_irq(irq, &pit_timer_irq));
+
+	clockevent_pit.cpumask = cpumask_of(0);
+	clockevent_pit.irq = irq;
+	/*
+	 * The value for the LDVAL register trigger is calculated as:
+	 * LDVAL trigger = (period / clock period) - 1
+	 * The pit is a 32-bit down count timer, when the conter value
+	 * reaches 0, it will generate an interrupt, thus the minimal
+	 * LDVAL trigger value is 1. And then the min_delta is
+	 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
+	 */
+	clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
+
+	return 0;
+}
+
+static void __init pit_timer_init(struct device_node *np)
+{
+	struct clk *pit_clk;
+	void __iomem *timer_base;
+	unsigned long clk_rate;
+	int irq;
+
+	timer_base = of_iomap(np, 0);
+	BUG_ON(!timer_base);
+
+	/*
+	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
+	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
+	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
+	 */
+	clksrc_base = timer_base + PITn_OFFSET(2);
+	clkevt_base = timer_base + PITn_OFFSET(3);
+
+	irq = irq_of_parse_and_map(np, 0);
+	BUG_ON(irq <= 0);
+
+	pit_clk = of_clk_get(np, 0);
+	BUG_ON(IS_ERR(pit_clk));
+
+	BUG_ON(clk_prepare_enable(pit_clk));
+
+	clk_rate = clk_get_rate(pit_clk);
+	cycle_per_jiffy = clk_rate / (HZ);
+
+	/* enable the pit module */
+	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
+
+	BUG_ON(pit_clocksource_init(clk_rate));
+
+	pit_clockevent_init(clk_rate, irq);
+}
+CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
-- 
1.8.0




From b35083 at freescale.com  Tue May 28 05:26:01 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:26:01 +0800
Subject: [PATCH v4] tty: serial: add Freescale lpuart driver support
Message-ID: <1369733161-19168-1-git-send-email-b35083@freescale.com>

Add Freescale lpuart driver support. The lpuart device
can be found on Vybrid VF610 and Layerscape LS-1 SoCs.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  Change Vybrid VF610 SoC compatible string to "fsl,vf610-lpuart"
v3:
  Change the uart driver name from mvf to lpuart for further share between SoCs.
  Add bind doc in Documentation/devicetree/bindings/tty/serial.
  Remove unused #include header lines.
  Clean up code.
V2:
  Remove unused variables and clean up the code.
  Based on the comments for last version.

 .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
 drivers/tty/serial/Kconfig                         |  14 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/fsl_lpuart.c                    | 916 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 5 files changed, 948 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
 create mode 100644 drivers/tty/serial/fsl_lpuart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
new file mode 100644
index 0000000..5cad58c
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
@@ -0,0 +1,14 @@
+* Freescale Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
+
+Required properties:
+- compatible : Should be "fsl,<soc>-lpuart"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain uart interrupt
+
+Example:
+
+uart0: serial at 40027000 {
+	       compatible = "fsl,vf610-lpuart";
+	       reg = <0x40027000 0x1000>;
+	       interrupts = <0 61 0x00>;
+       };
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..0841125 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1484,6 +1484,20 @@ config SERIAL_RP2_NR_UARTS
 	  If multiple cards are present, the default limit of 32 ports may
 	  need to be increased.
 
+config SERIAL_FSL_LPUART
+	bool "Freescale Lpuart serial port support"
+	select SERIAL_CORE
+	help
+	  Support for the on-chip LPUARTs on some Freescale SOCs.
+
+config SERIAL_FSL_LPUART_CONSOLE
+	bool "Console on Freescale LPUART serial port"
+	depends on SERIAL_FSL_LPUART
+	select SERIAL_CORE_CONSOLE
+	help
+	  If you have enabled the lpuart serial port on the Freescale SoCs,
+	  you can make it the console by answering Y to this option.
+
 endmenu
 
 endif # TTY
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index eedfec4..cf650f0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
 obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
 obj-$(CONFIG_SERIAL_ARC)	+= arc_uart.o
 obj-$(CONFIG_SERIAL_RP2)	+= rp2.o
+obj-$(CONFIG_SERIAL_FSL_LPUART)	+= fsl_lpuart.o
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
new file mode 100644
index 0000000..e6c5c7c
--- /dev/null
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -0,0 +1,916 @@
+/*
+ *  Freescale lpuart ports driver
+ *
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/of_device.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/pinctrl/consumer.h>
+
+/* All registers are 8-bit width */
+#define UARTBDH			0x00
+#define UARTBDL			0x01
+#define UARTCR1			0x02
+#define UARTCR2			0x03
+#define UARTSR1			0x04
+#define UARTCR3			0x06
+#define UARTDR			0x07
+#define UARTCR4			0x0a
+#define UARTCR5			0x0b
+#define UARTMODEM		0x0d
+#define UARTPFIFO		0x10
+#define UARTCFIFO		0x11
+#define UARTSFIFO		0x12
+#define UARTTWFIFO		0x13
+#define UARTTCFIFO		0x14
+#define UARTRWFIFO		0x15
+
+#define UARTBDH_LBKDIE		0x80
+#define UARTBDH_RXEDGIE		0x40
+#define UARTBDH_SBR_MASK	0x1f
+
+#define UARTCR1_LOOPS		0x80
+#define UARTCR1_RSRC		0x20
+#define UARTCR1_M		0x10
+#define UARTCR1_WAKE		0x08
+#define UARTCR1_ILT		0x04
+#define UARTCR1_PE		0x02
+#define UARTCR1_PT		0x01
+
+#define UARTCR2_TIE		0x80
+#define UARTCR2_TCIE		0x40
+#define UARTCR2_RIE		0x20
+#define UARTCR2_ILIE		0x10
+#define UARTCR2_TE		0x08
+#define UARTCR2_RE		0x04
+#define UARTCR2_RWU		0x02
+#define UARTCR2_SBK		0x01
+
+#define UARTSR1_TDRE		0x80
+#define UARTSR1_TC		0x40
+#define UARTSR1_RDRF		0x20
+#define UARTSR1_IDLE		0x10
+#define UARTSR1_OR		0x08
+#define UARTSR1_NF		0x04
+#define UARTSR1_FE		0x02
+#define UARTSR1_PE		0x01
+
+#define UARTCR3_R8		0x80
+#define UARTCR3_T8		0x40
+#define UARTCR3_TXDIR		0x20
+#define UARTCR3_TXINV		0x10
+#define UARTCR3_ORIE		0x08
+#define UARTCR3_NEIE		0x04
+#define UARTCR3_FEIE		0x02
+#define UARTCR3_PEIE		0x01
+
+#define UARTCR4_MAEN1		0x80
+#define UARTCR4_MAEN2		0x40
+#define UARTCR4_M10		0x20
+#define UARTCR4_BRFA_MASK	0x1f
+#define UARTCR4_BRFA_OFF	0
+
+#define UARTCR5_TDMAS		0x80
+#define UARTCR5_RDMAS		0x20
+
+#define UARTMODEM_RXRTSE	0x08
+#define UARTMODEM_TXRTSPOL	0x04
+#define UARTMODEM_TXRTSE	0x02
+#define UARTMODEM_TXCTSE	0x01
+
+#define UARTPFIFO_TXFE		0x80
+#define UARTPFIFO_FIFOSIZE_MASK	0x7
+#define UARTPFIFO_TXSIZE_OFF	4
+#define UARTPFIFO_RXFE		0x08
+#define UARTPFIFO_RXSIZE_OFF	0
+
+#define UARTCFIFO_TXFLUSH	0x80
+#define UARTCFIFO_RXFLUSH	0x40
+#define UARTCFIFO_RXOFE		0x04
+#define UARTCFIFO_TXOFE		0x02
+#define UARTCFIFO_RXUFE		0x01
+
+#define UARTSFIFO_TXEMPT	0x80
+#define UARTSFIFO_RXEMPT	0x40
+#define UARTSFIFO_RXOF		0x04
+#define UARTSFIFO_TXOF		0x02
+#define UARTSFIFO_RXUF		0x01
+
+#define DRIVER_NAME	"LP-uart"
+#define DEV_NAME	"ttyLP"
+#define UART_NR		6
+
+struct lpuart_port {
+	struct uart_port	port;
+	struct clk		*clk;
+	unsigned int		tx_fifo_size;
+	unsigned int		rx_fifo_size;
+};
+
+static struct of_device_id lpuart_uart_dt_ids[] = {
+	{
+		.compatible = "fsl,vf610-lpuart",
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lpuart_uart_dt_ids);
+
+static void lpuart_stop_tx(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + UARTCR2);
+	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
+	writeb(temp, sport->port.membase + UARTCR2);
+}
+
+static void lpuart_stop_rx(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + UARTCR2);
+	writeb(temp & ~UARTCR2_RE, sport->port.membase + UARTCR2);
+}
+
+static void lpuart_enable_ms(struct uart_port *port)
+{
+}
+
+static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
+{
+	struct circ_buf *xmit = &sport->port.state->xmit;
+
+	while (!uart_circ_empty(xmit) &&
+	(readb(sport->port.membase + UARTTCFIFO) < sport->tx_fifo_size)) {
+		writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		sport->port.icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+	if (uart_circ_empty(xmit))
+		lpuart_stop_tx(&sport->port);
+}
+
+static void lpuart_start_tx(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	unsigned char temp;
+
+	temp = readb(sport->port.membase + UARTCR2);
+	writeb(temp | UARTCR2_TIE,
+			sport->port.membase + UARTCR2);
+
+	if (readb(sport->port.membase + UARTSR1) & UARTSR1_TDRE)
+		lpuart_transmit_buffer(sport);
+}
+
+static irqreturn_t lpuart_txint(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	struct circ_buf *xmit = &sport->port.state->xmit;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+	if (sport->port.x_char) {
+		writeb(sport->port.x_char, sport->port.membase + UARTDR);
+		goto out;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
+		lpuart_stop_tx(&sport->port);
+		goto out;
+	}
+
+	lpuart_transmit_buffer(sport);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_rxint(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	unsigned int flg, ignored = 0;
+	struct tty_port *port = &sport->port.state->port;
+	unsigned long flags;
+	unsigned char r8, rx, sr;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	while (!(readb(sport->port.membase + UARTSFIFO) &
+				UARTSFIFO_RXEMPT)) {
+		flg = TTY_NORMAL;
+		sport->port.icount.rx++;
+
+		/*  To clear the FE, OR, NF, FE, PE flags when set,
+		 *  read SR1 then read DR
+		 */
+		sr = readb(sport->port.membase + UARTSR1);
+
+		r8 = readb(sport->port.membase + UARTCR3) & UARTCR3_R8;
+		rx = readb(sport->port.membase + UARTDR);
+
+		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
+			continue;
+		if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
+			if (sr & UARTSR1_PE)
+				sport->port.icount.parity++;
+			else if (sr & UARTSR1_FE)
+				sport->port.icount.frame++;
+			if (sr & UARTSR1_OR)
+				sport->port.icount.overrun++;
+
+			if (sr & sport->port.ignore_status_mask) {
+				if (++ignored > 100)
+					goto out;
+				continue;
+			}
+
+			sr &= sport->port.read_status_mask;
+
+			if (sr & UARTSR1_PE)
+				flg = TTY_PARITY;
+			else if (sr & UARTSR1_FE)
+				flg = TTY_FRAME;
+			if (sr & UARTSR1_OR)
+				flg = TTY_OVERRUN;
+
+#ifdef SUPPORT_SYSRQ
+			sport->port.sysrq = 0;
+#endif
+		}
+
+		tty_insert_flip_char(port, rx, flg);
+	}
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+
+	tty_flip_buffer_push(port);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_int(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	unsigned int sts;
+
+	sts = readb(sport->port.membase + UARTSR1);
+
+	if (sts & UARTSR1_RDRF)
+		lpuart_rxint(irq, dev_id);
+
+	if (sts & UARTSR1_TDRE &&
+		!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
+		lpuart_txint(irq, dev_id);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Return TIOCSER_TEMT when transmitter is not busy.
+ */
+static unsigned int lpuart_tx_empty(struct uart_port *port)
+{
+
+	return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
+		TIOCSER_TEMT : 0;
+}
+
+static unsigned int lpuart_get_mctrl(struct uart_port *port)
+{
+	unsigned int tmp = 0;
+	unsigned char reg;
+
+	reg = readb(port->membase + UARTMODEM);
+	if (reg & UARTMODEM_TXCTSE)
+		tmp |= TIOCM_CTS;
+
+	if (reg & UARTMODEM_RXRTSE)
+		tmp |= TIOCM_RTS;
+
+	return tmp;
+}
+
+static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	unsigned long temp;
+
+	temp = readb(port->membase + UARTMODEM) &
+			~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+	if (mctrl & TIOCM_RTS)
+		temp |= UARTMODEM_RXRTSE;
+	if (mctrl & TIOCM_CTS)
+		temp |= UARTMODEM_TXCTSE;
+
+	writeb(temp, port->membase + UARTMODEM);
+}
+
+static void lpuart_break_ctl(struct uart_port *port, int break_state)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
+
+	if (break_state != 0)
+		temp |= UARTCR2_SBK;
+
+	writeb(temp, port->membase + UARTCR2);
+
+}
+
+static void lpuart_setup_watermark(struct lpuart_port *sport)
+{
+	unsigned char val, old_cr2, cr2;
+
+	/* set receiver/transmitter trigger level. */
+	old_cr2 = cr2 = readb(sport->port.membase + UARTCR2);
+	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
+			UARTCR2_RIE | UARTCR2_RE);
+	writeb(cr2, sport->port.membase + UARTCR2);
+
+	writeb(2, sport->port.membase + UARTTWFIFO);
+	writeb(1, sport->port.membase + UARTRWFIFO);
+
+	/* determine FIFO size and enable */
+	val = readb(sport->port.membase + UARTPFIFO);
+
+	sport->tx_fifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
+		UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	sport->rx_fifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
+		UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
+			sport->port.membase + UARTPFIFO);
+
+	/* Flush the Tx and Rx FIFO to a known state */
+	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
+			sport->port.membase + UARTCFIFO);
+
+	/* restore CR2 */
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+
+}
+
+static int lpuart_startup(struct uart_port *port)
+{
+	struct lpuart_port *sport = (struct lpuart_port *)port;
+	int retval;
+	unsigned long flags, temp;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	lpuart_setup_watermark(sport);
+
+	temp = readb(sport->port.membase + UARTCR2);
+	writeb(temp & ~UARTCR2_RIE, sport->port.membase + UARTCR2);
+
+	/* clear and enable interrupts */
+	temp = readb(sport->port.membase + UARTCR2);
+	temp |= UARTCR2_RIE | UARTCR2_TIE;
+	writeb(temp, sport->port.membase + UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	/*
+	 * request the IRQ
+	 */
+	retval = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
+				DRIVER_NAME, sport);
+	if (retval)
+		return retval;
+
+	return 0;
+}
+
+static void lpuart_shutdown(struct uart_port *port)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned char temp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	temp = readb(port->membase + UARTCR2);
+	temp &= ~(UARTCR2_TE | UARTCR2_RE);
+	writeb(temp, port->membase + UARTCR2);
+	/*
+	 * Disable all interrupts
+	 */
+	temp = readb(port->membase + UARTCR2);
+	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+	writeb(temp, port->membase + UARTCR2);
+	spin_unlock_irqrestore(&port->lock, flags);
+	/*
+	 * Free the irq
+	 */
+	devm_free_irq(port->dev, port->irq, sport);
+}
+
+static void
+lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
+		   struct ktermios *old)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned long flags;
+	unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+	unsigned int  baud;
+	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+	unsigned int sbr, brfa;
+
+	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
+	old_cr2 = readb(sport->port.membase + UARTCR2);
+	cr4 = readb(sport->port.membase + UARTCR4);
+	bdh = readb(sport->port.membase + UARTBDH);
+	modem = readb(sport->port.membase + UARTMODEM);
+
+	/*
+	 * We only support CS8 and CS7, and for CS7 must enable PE.
+	 * supported mode:
+	 *  - (7,e/o,1)
+	 *  - (8,n,1)
+	 *  - (8,m/s,1)
+	 *  - (8,e/o,1)
+	 */
+	while ((termios->c_cflag & CSIZE) != CS8 &&
+		(termios->c_cflag & CSIZE) != CS7) {
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= old_csize;
+		old_csize = CS8;
+	}
+
+	if ((termios->c_cflag & CSIZE) == CS8 ||
+		(termios->c_cflag & CSIZE) == CS7)
+		cr1 = old_cr1 & ~UARTCR1_M;
+
+	if (termios->c_cflag & CMSPAR) {
+		if ((termios->c_cflag & CSIZE) != CS8) {
+			termios->c_cflag &= ~CSIZE;
+			termios->c_cflag |= CS8;
+		}
+		cr1 |= UARTCR1_M;
+	}
+
+	if (termios->c_cflag & CRTSCTS) {
+		modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+	} else {
+		termios->c_cflag &= ~CRTSCTS;
+		modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		termios->c_cflag &= ~CSTOPB;
+
+	/* parity must enable when CS7 to match 8-bits format */
+	if ((termios->c_cflag & CSIZE) == CS7)
+		termios->c_cflag |= PARENB;
+
+	if ((termios->c_cflag & PARENB)) {
+		if (termios->c_cflag & CMSPAR) {
+			cr1 &= ~UARTCR1_PE;
+			cr1 |= UARTCR1_M;
+		} else {
+			cr1 |= UARTCR1_PE;
+			if ((termios->c_cflag & CSIZE) == CS8)
+				cr1 |= UARTCR1_M;
+			if (termios->c_cflag & PARODD)
+				cr1 |= UARTCR1_PT;
+			else
+				cr1 &= ~UARTCR1_PT;
+		}
+	}
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	sport->port.read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		sport->port.read_status_mask |=
+					(UARTSR1_FE | UARTSR1_PE);
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		sport->port.read_status_mask |= UARTSR1_FE;
+
+	/*
+	 * Characters to ignore
+	 */
+	sport->port.ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		sport->port.ignore_status_mask |= UARTSR1_PE;
+	if (termios->c_iflag & IGNBRK) {
+		sport->port.ignore_status_mask |= UARTSR1_FE;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			sport->port.ignore_status_mask |= UARTSR1_OR;
+	}
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/* wait transmit engin complete */
+	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+		barrier();
+
+	writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
+			sport->port.membase + UARTCR2);
+
+	/* disable transmit and receive */
+	sbr = sport->port.uartclk / (16 * baud);
+	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
+
+	bdh &= ~UARTBDH_SBR_MASK;
+	bdh |= (sbr >> 8) & 0x1F;
+
+	cr4 &= ~UARTCR4_BRFA_MASK;
+	brfa &= UARTCR4_BRFA_MASK;
+	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
+	writeb(bdh, sport->port.membase + UARTBDH);
+	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
+	writeb(cr1, sport->port.membase + UARTCR1);
+	writeb(modem, sport->port.membase + UARTMODEM);
+
+	/* restore control register */
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
+static const char *lpuart_type(struct uart_port *port)
+{
+	return "FSL_LPUART";
+}
+
+static void lpuart_release_port(struct uart_port *port)
+{
+	/* Nothing to do */
+}
+
+static int lpuart_request_port(struct uart_port *port)
+{
+	return  0;
+}
+/*
+ * Configure/autoconfigure the port.
+ */
+static void lpuart_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE)
+		port->type = PORT_LPUART;
+}
+
+static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
+		ret = -EINVAL;
+	if (port->irq != ser->irq)
+		ret = -EINVAL;
+	if (ser->io_type != UPIO_MEM)
+		ret = -EINVAL;
+	if (port->uartclk / 16 != ser->baud_base)
+		ret = -EINVAL;
+	if (port->iobase != ser->port)
+		ret = -EINVAL;
+	if (ser->hub6 != 0)
+		ret = -EINVAL;
+	return ret;
+}
+
+static struct uart_ops lpuart_pops = {
+	.tx_empty	= lpuart_tx_empty,
+	.set_mctrl	= lpuart_set_mctrl,
+	.get_mctrl	= lpuart_get_mctrl,
+	.stop_tx	= lpuart_stop_tx,
+	.start_tx	= lpuart_start_tx,
+	.stop_rx	= lpuart_stop_rx,
+	.enable_ms	= lpuart_enable_ms,
+	.break_ctl	= lpuart_break_ctl,
+	.startup	= lpuart_startup,
+	.shutdown	= lpuart_shutdown,
+	.set_termios	= lpuart_set_termios,
+	.type		= lpuart_type,
+	.request_port	= lpuart_request_port,
+	.release_port	= lpuart_release_port,
+	.config_port	= lpuart_config_port,
+	.verify_port	= lpuart_verify_port,
+};
+
+static struct lpuart_port *lpuart_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
+static void lpuart_console_putchar(struct uart_port *port, int ch)
+{
+	while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
+		barrier();
+
+	writeb(ch, port->membase + UARTDR);
+}
+
+static void
+lpuart_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct lpuart_port *sport = lpuart_ports[co->index];
+	unsigned int  old_cr2, cr2;
+
+	/*
+	 * First, save CR2 and then disable interrupts
+	 */
+	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
+
+	cr2 |= (UARTCR2_TE |  UARTCR2_RE);
+	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+
+	writeb(cr2, sport->port.membase + UARTCR2);
+
+	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
+
+	/*
+	 * wait for transmitter finish complete and restore CR2
+	 */
+	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+		barrier();
+
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+}
+
+/*
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+lpuart_console_get_options(struct lpuart_port *sport, int *baud,
+			   int *parity, int *bits)
+{
+	unsigned char cr, bdh, bdl, brfa;
+	unsigned int sbr, uartclk;
+	unsigned int baud_raw;
+
+	cr = readb(sport->port.membase + UARTCR2);
+	cr &= UARTCR2_TE | UARTCR2_RE;
+	if (!cr)
+		return;
+
+	/* ok, the port was enabled */
+
+	cr = readb(sport->port.membase + UARTCR1);
+
+	*parity = 'n';
+	if (cr & UARTCR1_PE) {
+		if (cr & UARTCR1_PT)
+			*parity = 'o';
+		else
+			*parity = 'e';
+	}
+
+	if (cr & UARTCR1_M)
+		*bits = 9;
+	else
+		*bits = 8;
+
+	bdh = readb(sport->port.membase + UARTBDH);
+	bdh &= UARTBDH_SBR_MASK;
+	bdl = readb(sport->port.membase + UARTBDL);
+	sbr = bdh;
+	sbr <<= 8;
+	sbr |= bdl;
+	brfa = readb(sport->port.membase + UARTCR4);
+	brfa &= UARTCR4_BRFA_MASK;
+
+	uartclk = clk_get_rate(sport->clk);
+	/*
+	 * Baud = mod_clk/(16*(sbr[13]+(brfa)/32)
+	 */
+	baud_raw = uartclk / (16 * (sbr + brfa / 32));
+
+	if (*baud != baud_raw)
+		printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+				"from %d to %d\n", baud_raw, *baud);
+}
+
+static int __init lpuart_console_setup(struct console *co, char *options)
+{
+	struct lpuart_port *sport;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
+		co->index = 0;
+	sport = lpuart_ports[co->index];
+
+	if (sport == NULL)
+		return -ENODEV;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		lpuart_console_get_options(sport, &baud, &parity, &bits);
+
+	lpuart_setup_watermark(sport);
+
+	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver lpuart_reg;
+static struct console lpuart_console = {
+	.name		= DEV_NAME,
+	.write		= lpuart_console_write,
+	.device		= uart_console_device,
+	.setup		= lpuart_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &lpuart_reg,
+};
+
+#define LPUART_CONSOLE	(&lpuart_console)
+#else
+#define LPUART_CONSOLE	NULL
+#endif
+
+static struct uart_driver lpuart_reg = {
+	.owner		= THIS_MODULE,
+	.driver_name	= DRIVER_NAME,
+	.dev_name	= DEV_NAME,
+	.nr		= ARRAY_SIZE(lpuart_ports),
+	.cons		= LPUART_CONSOLE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int lpuart_uart_suspend(struct device *dev)
+{
+	struct lpuart_port *sport = dev_get_drvdata(dev);
+
+	uart_suspend_port(&lpuart_reg, &sport->port);
+
+	return 0;
+}
+
+static int lpuart_uart_resume(struct device *dev)
+{
+	struct lpuart_port *sport = dev_get_drvdata(dev);
+
+	uart_resume_port(&lpuart_reg, &sport->port);
+
+	return 0;
+}
+#endif
+
+static int lpuart_uart_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct lpuart_port *sport;
+	void __iomem *base;
+	struct resource *res;
+	int ret;
+
+	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+	if (!sport)
+		return -ENOMEM;
+
+	pdev->dev.coherent_dma_mask = 0;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!base)
+		return -ENOMEM;
+
+	sport->port.dev = &pdev->dev;
+	sport->port.mapbase = res->start;
+	sport->port.membase = base;
+	sport->port.type = PORT_LPUART;
+	sport->port.iotype = UPIO_MEM;
+	sport->port.irq = platform_get_irq(pdev, 0);
+	sport->port.ops = &lpuart_pops;
+	sport->port.flags = UPF_BOOT_AUTOCONF;
+
+	sport->clk = devm_clk_get(&pdev->dev, "ipg");
+	if (IS_ERR(sport->clk)) {
+		ret = PTR_ERR(sport->clk);
+		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+		return ret;
+	}
+
+	clk_prepare_enable(sport->clk);
+
+	sport->port.uartclk = clk_get_rate(sport->clk);
+
+	lpuart_ports[sport->port.line] = sport;
+
+	platform_set_drvdata(pdev, &sport->port);
+
+	ret = uart_add_one_port(&lpuart_reg, &sport->port);
+
+	if (ret) {
+		clk_disable_unprepare(sport->clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int lpuart_uart_remove(struct platform_device *pdev)
+{
+	struct lpuart_port *sport = platform_get_drvdata(pdev);
+
+	uart_remove_one_port(&lpuart_reg, &sport->port);
+
+	clk_disable_unprepare(sport->clk);
+
+	return 0;
+}
+
+static const struct dev_pm_ops lpuart_uart_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(lpuart_uart_suspend, lpuart_uart_resume)
+};
+
+static struct platform_driver lpuart_uart_driver = {
+	.probe		= lpuart_uart_probe,
+	.remove		= lpuart_uart_remove,
+	.driver		= {
+		.name	= "lpuart-uart",
+		.owner	= THIS_MODULE,
+		.of_match_table = lpuart_uart_dt_ids,
+		.pm	= &lpuart_uart_pm_ops,
+	},
+};
+
+static int __init lpuart_serial_init(void)
+{
+	int ret;
+
+	pr_info("serial: Freescale lpuart driver\n");
+
+	ret = uart_register_driver(&lpuart_reg);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&lpuart_uart_driver);
+	if (ret)
+		uart_unregister_driver(&lpuart_reg);
+
+	return 0;
+}
+
+static void __exit lpuart_serial_exit(void)
+{
+	platform_driver_unregister(&lpuart_uart_driver);
+	uart_unregister_driver(&lpuart_reg);
+}
+
+module_init(lpuart_serial_init);
+module_exit(lpuart_serial_exit);
+
+MODULE_DESCRIPTION("Freescale LPUART serial driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 74c2bf7..df84fa2 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -226,4 +226,7 @@
 /* Rocketport EXPRESS/INFINITY */
 #define PORT_RP2	102
 
+/* Freescale lp-uart */
+#define PORT_LPUART	103
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
1.8.0




From marc.zyngier at arm.com  Tue May 28 06:11:26 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 28 May 2013 11:11:26 +0100
Subject: [PATCH v3 7/7] ARM: KVM: drop use of PAGE_S2_DEVICE
In-Reply-To: <CAEDV+gJeeQUOOLjFpkvoPk7e=csjmvvefhdp1miiWtosABwW6Q@mail.gmail.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>
 <CAEDV+gJeeQUOOLjFpkvoPk7e=csjmvvefhdp1miiWtosABwW6Q@mail.gmail.com>
Message-ID: <51A482CE.1090509@arm.com>

On 27/05/13 21:01, Christoffer Dall wrote:
> On Tue, May 14, 2013 at 4:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> At the moment, when mapping a device into Stage-2 for a guest,
>> we override whatever the guest uses by forcing a device memory
>> type in Stage-2.
>>
>> While this is not exactly wrong, this isn't really the "spirit" of
>> the architecture. The hardware shouldn't have to cope for a broken
>> guest mapping to a device as normal memory.
>>
> 
> So I'm trying to think of a scenario where this feature in the
> architecture would actually be useful, and it sounds like from you
> guys that it's only useful to properly run a broken guest.
> 
> Are we 100% sure that a malicious guest can't leverage this to break
> isolation? I'm thinking something along the lines of writing to a
> device (for example the gic virtual cpu interface) with a cached
> mapping. If such a write is in fact written back to cache, and not
> evicted from the cache before a later time, where a different VM is
> running, can't that adversely affect the other VM?
> 
> Probably this can never happen, but I wasn't able to convince myself
> of this from going through the ARM ARM...?

I think you definitely have a point here, and I completely missed that
case. A shared device (like the GIC virtual CPU interface) must be
forced to a device memory type, otherwise we cannot ensure strict
isolation of guests.

I'll drop this patch from my series and add PAGE_S2_DEVICE back to the
arm64 port.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From arno at natisbad.org  Tue May 28 06:15:04 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Tue, 28 May 2013 12:15:04 +0200
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
References: <cover.1369687670.git.arno@natisbad.org>
 <152190814.eApXVbVBPA@wuerfel>
Message-ID: <87li6z2yxj.fsf@natisbad.org>

Hi Arnd,

Arnd Bergmann <arnd at arndb.de> writes:

> On Tuesday 28 May 2013 00:02:29 Arnaud Ebalard wrote:
>> 
>> This series adds support for GMT G762/G763. This work is based on a
>> basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
>> NAS. Updates have been performed to run on recent kernels. Support has
>> been completed and additional features added: ability to configure
>> various characteristics from .dts file, better initialization, alarms
>> and error reporting support, gear mode, polarity, fan pulse per
>> revolution, fan startup voltage control.
>
> I wonder if this could be split into two separate drivers, one for
> the pwm subsystem, and one for a hardware-independent fan controller
> based on the pwm interfaces.

To be honest, I wouldn't even know how to start in order to do that.
Additionally, it would be worth the effort if other drivers could be
easily refactored using this idea. I'll let hwmon people provide some
feedback and try and comply with their directions (based on the cpu
cycle I can spend on this).

Cheers,

a+


From b35083 at freescale.com  Tue May 28 05:32:07 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:32:07 +0800
Subject: [PATCH RESEND v3 1/2] pinctrl: imx: add VF610 support to imx pinctrl
 framework
Message-ID: <1369733528-25926-1-git-send-email-b35083@freescale.com>

On some platforms such as VF610, offset of mux and pad ctrl register
may be zero, and the mux_mode and config_val are in one 32-bit register.
This patch adds support to imx core pinctrl framework to handle these
cases.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v3:
  Add ZERO_OFFSET_VALID flag to handle register offset from zero on Vybrid vf610.
  Add SHARE_MUX_CONF_REG flag to handle mux mode and config value in one 32-bit
register on Vybrid vf610.

 drivers/pinctrl/pinctrl-imx.c | 53 ++++++++++++++++++++++++++++++++++---------
 drivers/pinctrl/pinctrl-imx.h |  4 ++++
 2 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4fcfff92..57a4eb0 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -221,13 +221,21 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 		pin_id = pins[i];
 		pin_reg = &info->pin_regs[pin_id];
 
-		if (!pin_reg->mux_reg) {
+		if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
 			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
 				info->pins[pin_id].name);
 			return -EINVAL;
 		}
 
-		writel(mux[i], ipctl->base + pin_reg->mux_reg);
+		if (info->flags & SHARE_MUX_CONF_REG) {
+			u32 reg;
+			reg = readl(ipctl->base + pin_reg->mux_reg);
+			reg &= ~(0x7 << 20);
+			reg |= (mux[i] << 20);
+			writel(reg, ipctl->base + pin_reg->mux_reg);
+		} else {
+			writel(mux[i], ipctl->base + pin_reg->mux_reg);
+		}
 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 			pin_reg->mux_reg, mux[i]);
 
@@ -287,7 +295,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 
-	if (!pin_reg->conf_reg) {
+	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
 		dev_err(info->dev, "Pin(%s) does not support config function\n",
 			info->pins[pin_id].name);
 		return -EINVAL;
@@ -295,6 +303,9 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
+	if (info->flags & SHARE_MUX_CONF_REG)
+		*config &= 0xffff;
+
 	return 0;
 }
 
@@ -305,7 +316,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 
-	if (!pin_reg->conf_reg) {
+	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
 		dev_err(info->dev, "Pin(%s) does not support config function\n",
 			info->pins[pin_id].name);
 		return -EINVAL;
@@ -314,7 +325,15 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 		info->pins[pin_id].name);
 
-	writel(config, ipctl->base + pin_reg->conf_reg);
+	if (info->flags & SHARE_MUX_CONF_REG) {
+		u32 reg;
+		reg = readl(ipctl->base + pin_reg->conf_reg);
+		reg &= ~0xffff;
+		reg |= config;
+		writel(reg, ipctl->base + pin_reg->conf_reg);
+	} else {
+		writel(config, ipctl->base + pin_reg->conf_reg);
+	}
 	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 		pin_reg->conf_reg, config);
 
@@ -381,19 +400,24 @@ static struct pinctrl_desc imx_pinctrl_desc = {
  * 1 u32 CONFIG, so 24 types in total for each pin.
  */
 #define FSL_PIN_SIZE 24
+#define SHARE_FSL_PIN_SIZE 20
 
 static int imx_pinctrl_parse_groups(struct device_node *np,
 				    struct imx_pin_group *grp,
 				    struct imx_pinctrl_soc_info *info,
 				    u32 index)
 {
-	int size;
+	int size, pin_size;
 	const __be32 *list;
 	int i;
 	u32 config;
 
 	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 
+	if (info->flags & SHARE_MUX_CONF_REG)
+		pin_size = SHARE_FSL_PIN_SIZE;
+	else
+		pin_size = FSL_PIN_SIZE;
 	/* Initialise group */
 	grp->name = np->name;
 
@@ -403,12 +427,12 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 	 */
 	list = of_get_property(np, "fsl,pins", &size);
 	/* we do not check return since it's safe node passed down */
-	if (!size || size % FSL_PIN_SIZE) {
+	if (!size || size % pin_size) {
 		dev_err(info->dev, "Invalid fsl,pins property\n");
 		return -EINVAL;
 	}
 
-	grp->npins = size / FSL_PIN_SIZE;
+	grp->npins = size / pin_size;
 	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 				GFP_KERNEL);
 	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
@@ -421,10 +445,17 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 				GFP_KERNEL);
 	for (i = 0; i < grp->npins; i++) {
 		u32 mux_reg = be32_to_cpu(*list++);
-		u32 conf_reg = be32_to_cpu(*list++);
-		unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
-		struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+		u32 conf_reg;
+		unsigned int pin_id;
+		struct imx_pin_reg *pin_reg;
 
+		if (info->flags & SHARE_MUX_CONF_REG)
+			conf_reg = mux_reg;
+		else
+			conf_reg = be32_to_cpu(*list++);
+
+		pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+		pin_reg = &info->pin_regs[pin_id];
 		grp->pins[i] = pin_id;
 		pin_reg->mux_reg = mux_reg;
 		pin_reg->conf_reg = conf_reg;
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
index 607ef54..bcedd99 100644
--- a/drivers/pinctrl/pinctrl-imx.h
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -74,8 +74,12 @@ struct imx_pinctrl_soc_info {
 	unsigned int ngroups;
 	struct imx_pmx_func *functions;
 	unsigned int nfunctions;
+	unsigned int flags;
 };
 
+#define ZERO_OFFSET_VALID	0x1
+#define SHARE_MUX_CONF_REG	0x2
+
 #define NO_MUX		0x0
 #define NO_PAD		0x0
 
-- 
1.8.0




From b35083 at freescale.com  Tue May 28 05:32:08 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Tue, 28 May 2013 17:32:08 +0800
Subject: [PATCH v4 2/2] pinctrl: add VF610 pinctrl driver
In-Reply-To: <1369733528-25926-1-git-send-email-b35083@freescale.com>
References: <1369733528-25926-1-git-send-email-b35083@freescale.com>
Message-ID: <1369733528-25926-2-git-send-email-b35083@freescale.com>

Adds Freescale Vybrid VF610 pin controller
driver to IMX common pinctrl driver framework.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
v4:
  Fix document error.
  Fix code style error.
  Follow internal suggestions to name the soc name as VF610. 
v3:
  Clean up code.
  Update binding document according recommendation.
v2:
  Update the driver according to the IMX new pinctrl framework.

 .../bindings/pinctrl/fsl,vf610-pinctrl.txt         |  41 +++
 drivers/pinctrl/Kconfig                            |   8 +
 drivers/pinctrl/Makefile                           |   1 +
 drivers/pinctrl/pinctrl-vf610.c                    | 338 +++++++++++++++++++++
 4 files changed, 388 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-vf610.c

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
new file mode 100644
index 0000000..ddcdeb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
@@ -0,0 +1,41 @@
+Freescale Vybrid VF610 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,vf610-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
+  a pin working on a specific function, CONFIG is the pad setting value
+  such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
+  datasheet for the valid pad config settings.
+
+CONFIG bits definition:
+PAD_CTL_SPEED_LOW		(1 << 12)
+PAD_CTL_SPEED_MED		(2 << 12)
+PAD_CTL_SPEED_HIGH		(3 << 12)
+PAD_CTL_SRE_FAST		(1 << 11)
+PAD_CTL_SRE_SLOW		(0 << 11)
+PAD_CTL_ODE			(1 << 10)
+PAD_CTL_HYS			(1 << 9)
+PAD_CTL_DSE_DISABLE		(0 << 6)
+PAD_CTL_DSE_150ohm		(1 << 6)
+PAD_CTL_DSE_75ohm		(2 << 6)
+PAD_CTL_DSE_50ohm		(3 << 6)
+PAD_CTL_DSE_37ohm		(4 << 6)
+PAD_CTL_DSE_30ohm		(5 << 6)
+PAD_CTL_DSE_25ohm		(6 << 6)
+PAD_CTL_DSE_20ohm		(7 << 6)
+PAD_CTL_PUS_100K_DOWN		(0 << 4)
+PAD_CTL_PUS_47K_UP		(1 << 4)
+PAD_CTL_PUS_100K_UP		(2 << 4)
+PAD_CTL_PUS_22K_UP		(3 << 4)
+PAD_CTL_PKE			(1 << 3)
+PAD_CTL_PUE			(1 << 2)
+PAD_CTL_OBE_ENABLE		(1 << 1)
+PAD_CTL_IBE_ENABLE		(1 << 0)
+PAD_CTL_OBE_IBE_ENABLE		(3 << 0)
+
+Please refer to vf610-pinfunc.h in device tree source folder
+for all available PIN_FUNC_ID for Vybrid VF610.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 526a5d0..5259d40 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -108,6 +108,14 @@ config PINCTRL_IMX6SL
 	help
 	  Say Y here to enable the imx6sl pinctrl driver
 
+config PINCTRL_VF610
+	bool "Freescale Vybrid VF610 pinctrl driver"
+	depends on OF
+	depends on SOC_VF610
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
+
 config PINCTRL_LANTIQ
 	bool
 	depends on LANTIQ
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c18149a..3b26e3c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_S3C24XX)	+= pinctrl-s3c24xx.o
 obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
+obj-$(CONFIG_PINCTRL_VF610)	+= pinctrl-vf610.o
 
 obj-$(CONFIG_PLAT_ORION)        += mvebu/
 obj-$(CONFIG_ARCH_SHMOBILE)	+= sh-pfc/
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c
new file mode 100644
index 0000000..68a970b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-vf610.c
@@ -0,0 +1,338 @@
+/*
+ * VF610 pinctrl driver based on imx pinmux and pinconf core
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum vf610_pads {
+	VF610_PAD_PTA6 = 0,
+	VF610_PAD_PTA8 = 1,
+	VF610_PAD_PTA9 = 2,
+	VF610_PAD_PTA10 = 3,
+	VF610_PAD_PTA11 = 4,
+	VF610_PAD_PTA12 = 5,
+	VF610_PAD_PTA16 = 6,
+	VF610_PAD_PTA17 = 7,
+	VF610_PAD_PTA18 = 8,
+	VF610_PAD_PTA19 = 9,
+	VF610_PAD_PTA20 = 10,
+	VF610_PAD_PTA21 = 11,
+	VF610_PAD_PTA22 = 12,
+	VF610_PAD_PTA23 = 13,
+	VF610_PAD_PTA24 = 14,
+	VF610_PAD_PTA25 = 15,
+	VF610_PAD_PTA26 = 16,
+	VF610_PAD_PTA27 = 17,
+	VF610_PAD_PTA28 = 18,
+	VF610_PAD_PTA29 = 19,
+	VF610_PAD_PTA30 = 20,
+	VF610_PAD_PTA31 = 21,
+	VF610_PAD_PTB0 = 22,
+	VF610_PAD_PTB1 = 23,
+	VF610_PAD_PTB2 = 24,
+	VF610_PAD_PTB3 = 25,
+	VF610_PAD_PTB4 = 26,
+	VF610_PAD_PTB5 = 27,
+	VF610_PAD_PTB6 = 28,
+	VF610_PAD_PTB7 = 29,
+	VF610_PAD_PTB8 = 30,
+	VF610_PAD_PTB9 = 31,
+	VF610_PAD_PTB10 = 32,
+	VF610_PAD_PTB11 = 33,
+	VF610_PAD_PTB12 = 34,
+	VF610_PAD_PTB13 = 35,
+	VF610_PAD_PTB14 = 36,
+	VF610_PAD_PTB15 = 37,
+	VF610_PAD_PTB16 = 38,
+	VF610_PAD_PTB17 = 39,
+	VF610_PAD_PTB18 = 40,
+	VF610_PAD_PTB19 = 41,
+	VF610_PAD_PTB20 = 42,
+	VF610_PAD_PTB21 = 43,
+	VF610_PAD_PTB22 = 44,
+	VF610_PAD_PTC0 = 45,
+	VF610_PAD_PTC1 = 46,
+	VF610_PAD_PTC2 = 47,
+	VF610_PAD_PTC3 = 48,
+	VF610_PAD_PTC4 = 49,
+	VF610_PAD_PTC5 = 50,
+	VF610_PAD_PTC6 = 51,
+	VF610_PAD_PTC7 = 52,
+	VF610_PAD_PTC8 = 53,
+	VF610_PAD_PTC9 = 54,
+	VF610_PAD_PTC10 = 55,
+	VF610_PAD_PTC11 = 56,
+	VF610_PAD_PTC12 = 57,
+	VF610_PAD_PTC13 = 58,
+	VF610_PAD_PTC14 = 59,
+	VF610_PAD_PTC15 = 60,
+	VF610_PAD_PTC16 = 61,
+	VF610_PAD_PTC17 = 62,
+	VF610_PAD_PTD31 = 63,
+	VF610_PAD_PTD30 = 64,
+	VF610_PAD_PTD29 = 65,
+	VF610_PAD_PTD28 = 66,
+	VF610_PAD_PTD27 = 67,
+	VF610_PAD_PTD26 = 68,
+	VF610_PAD_PTD25 = 69,
+	VF610_PAD_PTD24 = 70,
+	VF610_PAD_PTD23 = 71,
+	VF610_PAD_PTD22 = 72,
+	VF610_PAD_PTD21 = 73,
+	VF610_PAD_PTD20 = 74,
+	VF610_PAD_PTD19 = 75,
+	VF610_PAD_PTD18 = 76,
+	VF610_PAD_PTD17 = 77,
+	VF610_PAD_PTD16 = 78,
+	VF610_PAD_PTD0 = 79,
+	VF610_PAD_PTD1 = 80,
+	VF610_PAD_PTD2 = 81,
+	VF610_PAD_PTD3 = 82,
+	VF610_PAD_PTD4 = 83,
+	VF610_PAD_PTD5 = 84,
+	VF610_PAD_PTD6 = 85,
+	VF610_PAD_PTD7 = 86,
+	VF610_PAD_PTD8 = 87,
+	VF610_PAD_PTD9 = 88,
+	VF610_PAD_PTD10 = 89,
+	VF610_PAD_PTD11 = 90,
+	VF610_PAD_PTD12 = 91,
+	VF610_PAD_PTD13 = 92,
+	VF610_PAD_PTB23 = 93,
+	VF610_PAD_PTB24 = 94,
+	VF610_PAD_PTB25 = 95,
+	VF610_PAD_PTB26 = 96,
+	VF610_PAD_PTB27 = 97,
+	VF610_PAD_PTB28 = 98,
+	VF610_PAD_PTC26 = 99,
+	VF610_PAD_PTC27 = 100,
+	VF610_PAD_PTC28 = 101,
+	VF610_PAD_PTC29 = 102,
+	VF610_PAD_PTC30 = 103,
+	VF610_PAD_PTC31 = 104,
+	VF610_PAD_PTE0 = 105,
+	VF610_PAD_PTE1 = 106,
+	VF610_PAD_PTE2 = 107,
+	VF610_PAD_PTE3 = 108,
+	VF610_PAD_PTE4 = 109,
+	VF610_PAD_PTE5 = 110,
+	VF610_PAD_PTE6 = 111,
+	VF610_PAD_PTE7 = 112,
+	VF610_PAD_PTE8 = 113,
+	VF610_PAD_PTE9 = 114,
+	VF610_PAD_PTE10 = 115,
+	VF610_PAD_PTE11 = 116,
+	VF610_PAD_PTE12 = 117,
+	VF610_PAD_PTE13 = 118,
+	VF610_PAD_PTE14 = 119,
+	VF610_PAD_PTE15 = 120,
+	VF610_PAD_PTE16 = 121,
+	VF610_PAD_PTE17 = 122,
+	VF610_PAD_PTE18 = 123,
+	VF610_PAD_PTE19 = 124,
+	VF610_PAD_PTE20 = 125,
+	VF610_PAD_PTE21 = 126,
+	VF610_PAD_PTE22 = 127,
+	VF610_PAD_PTE23 = 128,
+	VF610_PAD_PTE24 = 129,
+	VF610_PAD_PTE25 = 130,
+	VF610_PAD_PTE26 = 131,
+	VF610_PAD_PTE27 = 132,
+	VF610_PAD_PTE28 = 133,
+	VF610_PAD_PTA7 = 134,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
+	IMX_PINCTRL_PIN(VF610_PAD_PTA6),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA8),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA9),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA10),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA11),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA12),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA16),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA17),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA18),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA19),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA20),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA21),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA22),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA23),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA24),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA25),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA26),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA27),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA28),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA29),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA30),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA31),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB0),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB1),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB2),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB3),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB4),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB5),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB6),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB7),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB8),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB9),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB10),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB11),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB12),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB13),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB14),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB15),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB16),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB17),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB18),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB19),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB20),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB21),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB22),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC0),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC1),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC2),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC3),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC4),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC5),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC6),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC7),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC8),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC9),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC10),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC11),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC12),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC13),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC14),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC15),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC16),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC17),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD31),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD30),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD29),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD28),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD27),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD26),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD25),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD24),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD23),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD22),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD21),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD20),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD19),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD18),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD17),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD16),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD0),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD1),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD2),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD3),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD4),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD5),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD6),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD7),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD8),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD9),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD10),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD11),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD12),
+	IMX_PINCTRL_PIN(VF610_PAD_PTD13),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB23),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB24),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB25),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB26),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB27),
+	IMX_PINCTRL_PIN(VF610_PAD_PTB28),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC26),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC27),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC28),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC29),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC30),
+	IMX_PINCTRL_PIN(VF610_PAD_PTC31),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE0),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE1),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE2),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE3),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE4),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE5),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE6),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE7),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE8),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE9),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE10),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE11),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE12),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE13),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE14),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE15),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE16),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE17),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE18),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE19),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE20),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE21),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE22),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE23),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE24),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE25),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE26),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE27),
+	IMX_PINCTRL_PIN(VF610_PAD_PTE28),
+	IMX_PINCTRL_PIN(VF610_PAD_PTA7),
+};
+
+static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
+	.pins = vf610_pinctrl_pads,
+	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
+	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
+};
+
+static struct of_device_id vf610_pinctrl_of_match[] = {
+	{ .compatible = "fsl,vf610-iomuxc", },
+	{ /* sentinel */ }
+};
+
+static int vf610_pinctrl_probe(struct platform_device *pdev)
+{
+	return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
+}
+
+static struct platform_driver vf610_pinctrl_driver = {
+	.driver = {
+		.name = "vf610-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(vf610_pinctrl_of_match),
+	},
+	.probe = vf610_pinctrl_probe,
+	.remove = imx_pinctrl_remove,
+};
+
+static int __init vf610_pinctrl_init(void)
+{
+	return platform_driver_register(&vf610_pinctrl_driver);
+}
+arch_initcall(vf610_pinctrl_init);
+
+static void __exit vf610_pinctrl_exit(void)
+{
+	platform_driver_unregister(&vf610_pinctrl_driver);
+}
+module_exit(vf610_pinctrl_exit);
+
+MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.0




From ming.lei at canonical.com  Tue May 28 06:18:53 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Tue, 28 May 2013 18:18:53 +0800
Subject: [Bug] ARM 'perf' regression by commit a43cb95d5
In-Reply-To: <20130517155936.GQ23112@mudshark.cambridge.arm.com>
References: <CACVXFVPjo2dQpYPpqZS8GC8UPNzB5HLURpYm6-g1FOBbSUjDyA@mail.gmail.com>
 <20130517085530.GB22992@mudshark.cambridge.arm.com>
 <CACVXFVPEBXat3bPPuHzV535=xLoRMFd03Kjzp=NUF5E3KCq2=g@mail.gmail.com>
 <20130517093616.GC23112@mudshark.cambridge.arm.com>
 <CACVXFVP56EJb0BZ+w6hVAukQ-mN0e0Jn_GLw3XqXQqMwVGfNdA@mail.gmail.com>
 <20130517095423.GD23112@mudshark.cambridge.arm.com>
 <CACVXFVPJyKrOBk+JjsfCi+aQ8snQ7PsEJVuOnuTkrWBYEnvDtA@mail.gmail.com>
 <20130517155936.GQ23112@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVM6Yn99HeNknG3GybuM=_PWchqa2dNKcv=j+fiib0z4ug@mail.gmail.com>

On Fri, May 17, 2013 at 11:59 PM, Will Deacon <will.deacon at arm.com> wrote:
>
> Ok, I tried to reproduce this on my TC2 with 3.10-rc1 and perf top looks
> fine. I also tried loading your spi-altera module and it made no difference.
>
> I'm using a fairly old perf tool (reports its version as 3.5.5).

It isn't related with perf tool.

Finally, looks the problem disappeared after upgrading gcc to "gcc version
4.7.3 (Sourcery CodeBench Lite 2013.05-24)" from "gcc version 4.5.1
(Sourcery G++ Lite 2010.09-50)", so it should be caused by compiler.


Thanks,
--
Ming Lei


From catalin.marinas at arm.com  Tue May 28 06:20:01 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 28 May 2013 11:20:01 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130527214245.GB517@schnuecks.de>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <20130527214245.GB517@schnuecks.de>
Message-ID: <20130528102001.GB14329@arm.com>

On Mon, May 27, 2013 at 10:42:45PM +0100, Simon Baatz wrote:
> On Thu, May 23, 2013 at 11:43:03AM +0100, Catalin Marinas wrote:
> > On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > > it needs to handle are kernel mapped only.  However, for example when doing
> > > direct I/O, pages with user space mappings may occur.
> > > 
> > > Thus, continue to do lazy flushing if there are no user space mappings.
> > > Otherwise, flush the kernel cache lines directly.
> > > 
> > > Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> > > Cc: Catalin Marinas <catalin.marinas at arm.com>
> > > Cc: Russell King <linux at arm.linux.org.uk>
> > 
> > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > twice. I don't think we should remove the cache flushing in
> > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > don't work together). Flushing the VIVT cache on kunmap is essential
> > since we just lose the alias after that.
> 
> Not sure if I am missing something here. From our previous
> discussion:
> 
> > > > > We probably should reuse it in flush_kernel_dcache_page() to flush
> > > > > the kernel mapping. (The last else clause looks strange though)
> > > > 
> > > > I think it makes sense to reuse this logic in
> > > > flush_kernel_dcache_page(). If the page is already mapped with kmap,
> > > > then kmap_high_get() should return the actual address. If it was mapped
> > > > with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
> > > > clause and the additional kmap_atomic(). The cache_is_vipt() check is
> > > > useful because kunmap_atomic() would flush VIVT caches anyway.

I think the context was that page_address() is not always valid after
kmap_atomic(), so reusing the same logic would make sense.

But the key point I try to understand is why kunmap() does not need to
flush the VIVT cache. If it does need to, then we can simplify your
patch.

> As you say, this logic does not flush on VIVT if the page was mapped
> via kmap_atomic() (and kmap_atomic() could not reuse an existing
> mapping via kmap_high_get())
> 
> kmap_atomic() tries to reuse an existing mapping and only allocates a
> new dedicated kmap if it finds none.  Consequently, __kunmap_atomic()
> only flushes in the latter case (because we lose the alias).
> 
> Thus, no double flushing should occur here. If kunmap_atomic() will
> flush, __flush_kernel_dcache_page() will not and vice versa.

That's correct for the current code. Let's wait for some insight from
Nico or Russell on whether kunmap() needs to lush the VIVT cache as
well. If it doesn't need to, then my original comment made sense.

-- 
Catalin


From gang.chen at asianux.com  Tue May 28 06:25:44 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 28 May 2013 18:25:44 +0800
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <20130528081910.GA29557@gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
 <20130528081910.GA29557@gmail.com>
Message-ID: <51A48628.9030105@asianux.com>

On 05/28/2013 04:19 PM, Ingo Molnar wrote:
>> > And I come back to one of my previous arguments - is it not better to 
>> > panic() if we hit one of these conditions so that the system can try to 
>> > do a panic-reboot rather than continue blindly into the unknown?
> It will often continue blindly into the unknown even if the compiler is 
> happy ...
> 

For Server, it is necessary to always enable CONFIG_BUG and call panic()

When analyzing core dump or KDB trap, we have to assume that the kernel
has already "continued blindly", but lucky, we can get the core dump or
KDB trap finally (sometimes, we really even can not get core dump or KDB
trap).


For PC, it is useless to disable CONFIG_BUG

The PC memory has already large enough to skip the minimal size
optimization. And its speed is also high enough to skip the speed
improvement by minimal size optimization.


For Embedded system, some of architectures may disable CONFIG_BUG.

Embedded system are widely used in many area, so the requirement of each
architectures for BUG() may be different,

  some may need reboot as quickly as possible for urgent processing;
  some may need dead looping in BUG() for avoid user amazing;
    (if auto-reboot, users feel out of control, don't know what happens)
  some may still need panic() just like Server requirements.
  others may not care about it, just implement it as minimal size.



> The only difference is that i

t's "unpredictable" in a way not visible from
> the C code: the code won't necessarily fall through the BUG() when hitting 
> that condition - although in practice it probably will.
> 
> So I think the same principle applies to it as to any other debugging 
> code: it's fine to be able to turn debugging off. It's a performance 
> versus kernel robustness/determinism trade-off.

'minimal size' for BUG() is belongs to some of Embedded system specific
features, it is not 'generic' enough to be in "include/asm-generic/".

If we still provide the "disable CONFIG_BUG", some of 'crazy users'
(e.g. randconfig) may make 'noise' to most of architectures.

So we need not provide "disable CONFIG_BUG" features for all platforms,
since most of architectures need not support it, and the architecture
which really need minimal size, can implement it by itself as a
architecture specific feature.



Thanks.
-- 
Chen Gang

Asianux Corporation


From padma.v at samsung.com  Tue May 28 06:35:22 2013
From: padma.v at samsung.com (Padmavathi Venna)
Date: Tue, 28 May 2013 16:05:22 +0530
Subject: [PATCH] ARM: dts: wm8994: Add wm8994 regulator support on smdk5250.
Message-ID: <1369737322-10907-1-git-send-email-padma.v@samsung.com>

This patch adds the required regulator supplies and properties
for wm8994 codec on smdk5250 board.

Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   53 +++++++++++++++++++++++++++-
 1 files changed, 51 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f2a025e..42fc79e 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -37,6 +37,46 @@
 		};
 	};
 
+	avdd2:fixed-regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd2-supply";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	cpvdd:fixed-regulator at 1 {
+		compatible = "regulator-fixed";
+		regulator-name = "cpvdd-supply";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	dbvdd:fixed-regulator at 2 {
+		compatible = "regulator-fixed";
+		regulator-name = "dbvdd-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	spkvdd1:fixed-regulator at 3 {
+		compatible = "regulator-fixed";
+		regulator-name = "spkvdd1-supply";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	spkvdd2:fixed-regulator at 4 {
+		compatible = "regulator-fixed";
+		regulator-name = "spkvdd2-supply";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
 	i2c at 12C70000 {
 		samsung,i2c-sda-delay = <100>;
 		samsung,i2c-max-bus-freq = <20000>;
@@ -47,8 +87,17 @@
 		};
 
 		wm8994: wm8994 at 1a {
-			 compatible = "wlf,wm8994";
-			 reg = <0x1a>;
+			compatible = "wlf,wm8994";
+			reg = <0x1a>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			AVDD2-supply = <&avdd2>;
+			CPVDD-supply = <&cpvdd>;
+			DBVDD-supply = <&dbvdd>;
+			SPKVDD1-supply = <&spkvdd1>;
+			SPKVDD2-supply = <&spkvdd2>;
 		};
 	};
 
-- 
1.7.4.4



From daniel at ffwll.ch  Tue May 28 06:32:30 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Tue, 28 May 2013 12:32:30 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
References: <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
Message-ID: <20130528103229.GB15743@phenom.ffwll.local>

On Tue, May 28, 2013 at 12:56:57PM +0900, Inki Dae wrote:
> 
> 
> > -----Original Message-----
> > From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
> > owner at vger.kernel.org] On Behalf Of Rob Clark
> > Sent: Tuesday, May 28, 2013 12:48 AM
> > To: Inki Dae
> > Cc: Maarten Lankhorst; Daniel Vetter; linux-fbdev; YoungJun Cho; Kyungmin
> > Park; myungjoo.ham; DRI mailing list;
> linux-arm-kernel at lists.infradead.org;
> > linux-media at vger.kernel.org
> > Subject: Re: Introduce a new helper framework for buffer synchronization
> > 
> > On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
> > > Hi all,
> > >
> > > I have been removed previous branch and added new one with more cleanup.
> > > This time, the fence helper doesn't include user side interfaces and
> > cache
> > > operation relevant codes anymore because not only we are not sure that
> > > coupling those two things, synchronizing caches and buffer access
> > between
> > > CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is
> > a
> > > good idea yet but also existing codes for user side have problems with
> > badly
> > > behaved or crashing userspace. So this could be more discussed later.
> > >
> > > The below is a new branch,
> > >
> > > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> > exynos.git/?h=dma-f
> > > ence-helper
> > >
> > > And fence helper codes,
> > >
> > > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> > exynos.git/commit/?
> > > h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
> > >
> > > And example codes for device driver,
> > >
> > > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> > exynos.git/commit/?
> > > h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
> > >
> > > I think the time is not yet ripe for RFC posting: maybe existing dma
> > fence
> > > and reservation need more review and addition work. So I'd glad for
> > somebody
> > > giving other opinions and advices in advance before RFC posting.
> > 
> > thoughts from a *really* quick, pre-coffee, first look:
> > * any sort of helper to simplify single-buffer sort of use-cases (v4l)
> > probably wouldn't want to bake in assumption that seqno_fence is used.
> > * I guess g2d is probably not actually a simple use case, since I
> > expect you can submit blits involving multiple buffers :-P
> 
> I don't think so. One and more buffers can be used: seqno_fence also has
> only one buffer. Actually, we have already applied this approach to most
> devices; multimedia, gpu and display controller. And this approach shows
> more performance; reduced power consumption against traditional way. And g2d
> example is just to show you how to apply my approach to device driver.

Note that seqno_fence is an implementation pattern for a certain type of
direct hw->hw synchronization which uses a shared dma_buf to exchange the
sync cookie. The dma_buf attached to the seqno_fence has _nothing_ to do
with the dma_buf the fence actually coordinates access to.

I think that confusing is a large reason for why Maarten&I don't
understand what you want to achieve with your fence helpers. Currently
they're using the seqno_fence, but totally not in a way the seqno_fence
was meant to be used.

Note that with the current code there is only a pointer from dma_bufs to
the fence. The fence itself has _no_ pointer to the dma_buf it syncs. This
shouldn't be a problem since the fence fastpath for already signalled
fences is completely barrier&lock free (it's just a load+bit-test), and
fences are meant to be embedded into whatever dma tracking structure you
already have, so no overhead there. The only ugly part is the fence
refcounting, but I don't think we can drop that.

Note that you completely reinvent this part of Maarten's fence patches by
adding new r/w_complete completions to the reservation object, which
completely replaces the fence stuff.

Also note that a list of reservation entries is again meant to be used
only when submitting the dma to the gpu. With your patches you seem to
hang onto that list until dma completes. This has the ugly side-effect
that you need to allocate these reservation entries with kmalloc, whereas
if you just use them in the execbuf ioctl to construct the dma you can
usually embed it into something else you need already anyway. At least
i915 and ttm based drivers can work that way.

Furthermore fences are specifically constructed as frankenstein-monsters
between completion/waitqueues and callbacks. All the different use-cases
need the different aspects:
- busy/idle checks and bo retiring need the completion semantics
- callbacks (in interrupt context) are used for hybrid hw->irq handler->hw
  sync approaches

> 
> > * otherwise, you probably don't want to depend on dmabuf, which is why
> > reservation/fence is split out the way it is..  you want to be able to
> > use a single reservation/fence mechanism within your driver without
> > having to care about which buffers are exported to dmabuf's and which
> > are not.  Creating a dmabuf for every GEM bo is too heavyweight.
> 
> Right. But I think we should dealt with this separately. Actually, we are
> trying to use reservation for gpu pipe line synchronization such as sgx sync
> object and this approach is used without dmabuf. In order words, some device
> can use only reservation for such pipe line synchronization and at the same
> time, fence helper or similar thing with dmabuf for buffer synchronization.

I think a quick overview of the different pieces would be in order.

- ww_mutex: This is just the locking primite which allows you to grab
  multiple mutexes without the need to check for ordering (and so fear
  deadlocks).

- fence: This is just a fancy kind of completion with a bit of support for
  hw->hw completion events. The fences themselve have no tie-in with
  buffers, ww_mutexes or anything else.

- reservation: This ties together an object (doesn't need to be a buffer,
  could be any other gpu resource - see the drm/vmwgfx driver if you want
  your mind blown) with fences. Note that there's no connection the other
  way round, i.e. with the current patches you can't see which
  reservations are using which fences. Also note that other objects than
  reservations could point at fences, e.g. when the provide
  shared/exclusive semantics are not good enough for your needs.

  The ww_mutex in the reservation is simply the (fancy) lock which
  protects each reservation. The reason we need something fancy is that
  you need to lock all objects which are synced by the same fence
  toghether, otherwise you can race and construct deadlocks in the hw->hw
  sync part of fences.

- dma_buf integration: This is simply a pointer to the reservation object
  of the underlying buffer object. We need a pointer here since otherwise
  you can construct deadlocks between dma_buf objects and native buffer
  objects.

The crux is also that dma_buf integration comes last - before you can do
that you need to have your driver converted over to use
ww_mutexes/fences/reservations.

I hope that helps to unconfuse things a bit and help you understand the
different pieces of the fence/reservation/ww_mutex patches floating
around.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From will.deacon at arm.com  Tue May 28 06:42:50 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 28 May 2013 11:42:50 +0100
Subject: [PATCH v2] arch: arm64: kernel: sprintf(), 'str' needs
 additional 1 byte for failure processing
In-Reply-To: <51A2BE2C.2000004@asianux.com>
References: <51A1E3B3.4060901@asianux.com>
 <51A2BE2C.2000004@asianux.com>
Message-ID: <20130528104250.GE10474@mudshark.cambridge.arm.com>

Hello,

On Mon, May 27, 2013 at 03:00:12AM +0100, Chen Gang wrote:
> 
> When failure occurs at the last looping cycle (when 'i == 0'), it will
> print "bad PC value" instead of "(%08x) ", which needs additional 1
> byte.
> 
> If not add 1 byte, the 'str' may be memory overflow.
> 
> 
> Signed-off-by: Chen Gang <gang.chen at asianux.com>
> ---
>  arch/arm64/kernel/traps.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> index 61d7dd2..c2f68d2 100644
> --- a/arch/arm64/kernel/traps.c
> +++ b/arch/arm64/kernel/traps.c
> @@ -100,7 +100,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
>  {
>  	unsigned long addr = instruction_pointer(regs);
>  	mm_segment_t fs;
> -	char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
> +	char str[sizeof("00000000 ") * 5 + 2 + 1 + 1], *p = str;
>  	int i;

Whilst this code is difficult to follow, I don't think it's incorrect.
The size of the str array is:

	sizeof("00000000 ") = 8 ('0's) + 1 (space) + 1 (NUL) = 10 bytes
	*5 = 50 bytes
	+2 (for the two brackets when i == 0) = 52 bytes
	+1 (this is for the "bad PC value") = 53 bytes

In the worst case (when the PC is bad) we print:

	"%08x " x4 = (8 + 1 + 1) *4 = 40 bytes
	"bad PC value" = 12 + 1 = 13 bytes

so again, 53 bytes.

... or have I missed a character somewhere?

Will


From ratbert.chuang at gmail.com  Tue May 28 06:48:20 2013
From: ratbert.chuang at gmail.com (Po-Yu Chuang)
Date: Tue, 28 May 2013 18:48:20 +0800
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
Message-ID: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>

This bug was introduced in commit e651eab0.
Some v4/v5 platforms failed to boot due to this.

Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
---
 arch/arm/mm/mmu.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e0d8565..19a43f8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
 			unsigned long end, phys_addr_t phys,
 			const struct mem_type *type)
 {
+	pmd_t *p = pmd;
+
 #ifndef CONFIG_ARM_LPAE
 	/*
 	 * In classic MMU format, puds and pmds are folded in to
@@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
 		phys += SECTION_SIZE;
 	} while (pmd++, addr += SECTION_SIZE, addr != end);
 
-	flush_pmd_entry(pmd);
+	flush_pmd_entry(p);
 }
 
 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
-- 
1.7.9.5



From javi.merino at arm.com  Tue May 28 06:49:52 2013
From: javi.merino at arm.com (Javi Merino)
Date: Tue, 28 May 2013 11:49:52 +0100
Subject: [PATCH] ARM: document the bigger pagetables needed for LPAE
In-Reply-To: <1369528072.2776.26@driftwood>
References: <1369410236-22398-1-git-send-email-javi.merino@arm.com>
 <1369528072.2776.26@driftwood>
Message-ID: <20130528104952.GD2776@e102654-lin.cambridge.arm.com>

On Sun, May 26, 2013 at 01:27:52AM +0100, Rob Landley wrote:
> On 05/24/2013 10:43:56 AM, Javi Merino wrote:
> > The Booting documentation assumes that the initial pagetables are
> > 16KiB but since 1b6ba46 (ARM: LPAE: MMU setup for the 3-level page
> > table format) they are 20KiB for LPAE kernels.  Thus, the
> > recommendation to put atags or the dtb in the first 16KiB is wrong,
> > there's only 12KiB of space there in LPAE kernels, so update the
> > documentation accordingly.
> > ---
> >  Documentation/arm/Booting |    9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> Acked-by: Rob Landley <rob at landley.net>

Thanks.  As Catalin pointed out, I'm missing my SoB.

> With one comment:
> 
> > diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting
> > index 0c1f475..f6f9cd8 100644
> > --- a/Documentation/arm/Booting
> > +++ b/Documentation/arm/Booting
> > @@ -105,7 +105,7 @@ The tagged list should be stored in system RAM.
> > 
> >  The tagged list must be placed in a region of memory where neither
> >  the kernel decompressor nor initrd 'bootp' program will overwrite
> > -it.  The recommended placement is in the first 16KiB of RAM.
> > +it.  The recommended placement is in the first 12KiB of RAM.
> > 
> >  4b. Setup the device tree
> >  -------------------------
> > @@ -120,7 +120,7 @@ tagged list.
> >  The boot loader must pass at a minimum the size and location of the
> >  system memory, and the root filesystem location.  The dtb must be
> >  placed in a region of memory where the kernel decompressor will not
> > -overwrite it.  The recommended placement is in the first 16KiB of RAM
> > +overwrite it.  The recommended placement is in the first 12KiB of RAM
> >  with the caveat that it may not be located at physical address 0  
> > since
> >  the kernel interprets a value of 0 in r2 to mean neither a tagged  
> > list
> >  nor a dtb were passed.
> > @@ -137,8 +137,9 @@ then it is legal for the boot loader to call the  
> > zImage in flash
> >  directly.
> > 
> >  The zImage may also be placed in system RAM (at any location) and
> > -called there.  Note that the kernel uses 16K of RAM below the image
> > -to store page tables.  The recommended placement is 32KiB into RAM.
> > +called there.  Note that the kernel may use up to 20KiB of RAM below
> > +the image to store page tables.  The recommended placement is 32KiB
> > +into RAM.
> 
> Now that we have three memory entires, possibly some sort of memory  
> layout would be in order?
> 
>     0k-12k   boot data (tagged list or device tree)
>    12k-32k   page tables
>    32k-xxx   kernel image
> 
> Perhaps at the end of section 4's introduction? It's not quite obvious  
> from the document...

Sounds like a good idea, I'll add it and send a v2.

Cheers,
Javi



From pawel.moll at arm.com  Tue May 28 06:52:52 2013
From: pawel.moll at arm.com (Pawel Moll)
Date: Tue, 28 May 2013 11:52:52 +0100
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <201305271231.40693.arnd@arndb.de>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
 <201305271231.40693.arnd@arndb.de>
Message-ID: <1369738372.3148.7.camel@hornet>

On Mon, 2013-05-27 at 11:31 +0100, Arnd Bergmann wrote:
> On Monday 27 May 2013, Daniel Tang wrote:
> > > The one remaining bit that sticks out is the clcd platform data. As I
> > > said before, I won't require you to convert that to DT in order to
> > > get your code merged, but I'd also really like to see that happen,
> > > as we will also need that to get rid of auxdata on the ARM reference
> > > platforms (integrator, versatile, realview, vexpress).
> > 
> > How would you like me to convert the platform data to DT? AFAIK, the clcd
> > driver isn't aware of DT so the only way is to use the AUXDATA right now.
> 
> Linus Walleij mentioned on IRC that Pawel Moll already posted a series
> that adds DT support for clcd:
> 
> http://lists.freedesktop.org/archives/dri-devel/2013-April/037519.html
> 
> The series does a few more things, but you can probbly split out the
> parts you need and base on that.

The main "issue" with the series is its dependency on Laurent Pinchart's
Common Display Framework (or rather on the progress of its upstreaming).
I'm planning to discuss this in details in during the Linaro Connect in
Dublin, but generally, if it's not getting merged in the next window,
I'll spin the series to use the standard video modes bindings instead of
CDF. This will make me hurt on Versatile Express, but should work for
others.

Pawe?




From pawel.moll at arm.com  Tue May 28 06:54:41 2013
From: pawel.moll at arm.com (Pawel Moll)
Date: Tue, 28 May 2013 11:54:41 +0100
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <201305271232.03644.arnd@arndb.de>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
 <201305271232.03644.arnd@arndb.de>
Message-ID: <1369738481.3148.9.camel@hornet>

On Mon, 2013-05-27 at 11:32 +0100, Arnd Bergmann wrote:
> b) add a new KMS driver for this hardware that can be used as an
> alternative to the existing one and that works with DT.

There are people working on this, just trying to jump through some legal
hoops to post a RFC. Once this is done we'll be in an interesting
position of two amba_bus drivers "competing" for the same amba_bus
device, which I'm not sure how to deal with right now...

Pawe?




From plagnioj at jcrosoft.com  Tue May 28 07:02:04 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 28 May 2013 13:02:04 +0200
Subject: [GIT PULL] at91: cleanup (pinctrl macros, defconfigs) for 3.11 #1
In-Reply-To: <20130528054701.GB18476@quad.lixom.net>
References: <1368799336-25226-1-git-send-email-nicolas.ferre@atmel.com>
 <519F9116.8060109@atmel.com>
 <20130528054701.GB18476@quad.lixom.net>
Message-ID: <20130528110204.GT24476@game.jcrosoft.org>

On 22:47 Mon 27 May     , Olof Johansson wrote:
> On Fri, May 24, 2013 at 06:11:02PM +0200, Nicolas Ferre wrote:
> > On 17/05/2013 16:02, Nicolas Ferre :
> > >Arnd, Olof,
> > >
> > >Here is the first AT91 cleanup pull-request for 3.11. I is dominated by a big
> > >update of DT files because of the move to macros in pinctrl. As we plan to
> > >make this "cleanup" series the base of all our work on AT91 for 3.11, we would
> > >like to see it appearing early in arm-soc and linux-next: this is why we send
> > >it to you right now.
> > >
> > >We have colected the Acked-by from Linus Walleij and we all think that it makes
> > >sense to merge this material through arm-soc tree:
> > >- is touches nearly nothing of pinctrl actual code (a header file)
> > >- all dtsi/dts modifications for 3.11 will need this as a codebase for avoiding
> > >   merging nightmare
> > >
> > >I hope that it is okay with you.
> > >
> > >Thanks, best regards,
> > >
> > >The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> > >
> > >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> > >
> > >are available in the git repository at:
> > >
> > >   git://github.com/at91linux/linux-at91.git tags/at91-cleanup
> > 
> > Arnd, Olof,
> > 
> > After having sent the second "fixes" pull-request to you, I want to
> > warn you about merging conflicts concerning this "cleanup"
> > pull-request for 3.11.
> > 
> > 2 merging conflicts are appearing when placing the "cleanup" branch
> > on top of the "fixes" material contained today in at91-fixes tag.
> > To address this, I have pushed a resolution branch on our usual git tree:
> > 
> > git://github.com/at91linux/linux-at91.git   at91-3.11-cleanup1+resolved
> > 
> > In case of any question, please let me know. If you want me to
> > rebase the original tag that I've sent you, I can do it as well.
> 
> Hi,
> 
> Thanks, not a big deal for us to resolve so that's ok.
> 
> Pulled in the branch. Some comments below:
> 
> 
> > >----------------------------------------------------------------
> > >Big update with pinctrl by use of macros and
> > >header files. Increases readability and avoid
> > >typos.
> > >Update of AT91 defconfigs and merge of defconfigs for
> > >SoC look-alike:
> > >sam9260/9g20 and sam9261/9g10.
> 
> This is hard to follow, please structure them better in the future.
> 
> > >----------------------------------------------------------------
> > >Jean-Christophe PLAGNIOL-VILLARD (6):
> > >       ARM: at91: dt: use #include for all device trees
> > >       ARM: at91: dt: switch to standard GPIO flag defines.
> > >       ARM: at91: dt: add pinctrl pre-processor define
> > >       ARM: at91: dt: switch to pinctrl to pre-processor
> > >       ARM: at91: dt: switch to standard IRQ flag defines
> > >       ARM: at91: udpate defconfigs
> 
> Typo in the patch subject, please keep an eye on these in the future.
> 
> > >  arch/arm/configs/at91_dt_defconfig                 |  55 ++-
> > >  arch/arm/configs/at91rm9200_defconfig              | 218 ++-------
> > >  ...am9g20_defconfig => at91sam9260_9g20_defconfig} |  67 ++-
> > >  arch/arm/configs/at91sam9260_defconfig             |  91 ----
> > >  ...am9261_defconfig => at91sam9261_9g10_defconfig} |  19 +-
> > >  arch/arm/configs/at91sam9263_defconfig             |  39 +-
> > >  arch/arm/configs/at91sam9g45_defconfig             |  94 ++--
> > >  arch/arm/configs/sama5_defconfig                   |  35 +-
> > >  arch/arm/mach-at91/Kconfig.non_dt                  | 159 +++----
> > >  arch/arm/mach-at91/Makefile                        |   2 -
> > >  arch/arm/mach-at91/board-sam9261ek.c               |  28 +-
> > >  include/dt-bindings/pinctrl/at91.h                 |  35 ++
> > >  63 files changed, 1407 insertions(+), 1617 deletions(-)
> > >  rename arch/arm/configs/{at91sam9g20_defconfig => at91sam9260_9g20_defconfig} (67%)
> > >  delete mode 100644 arch/arm/configs/at91sam9260_defconfig
> > >  rename arch/arm/configs/{at91sam9261_defconfig => at91sam9261_9g10_defconfig} (91%)
> > >  create mode 100644 include/dt-bindings/pinctrl/at91.h
> 
> Good to see consolidation, it'd be awesome if there could be even more.

more are on the way but on non-dt board and SoC device file no consolidation
work are done as we simply work on the DT support to drop them

recently I send the first non-dt board removal patch serie for the Calao
USB-A926x

More will come but as soon as we have finish the dt drivers support
few critical driver are missing but on the way as lcdc, hlcdc, rtc, etc...

but all the new SoC and board are DT only

Best Regards,
J.


From daniel.lezcano at linaro.org  Tue May 28 07:10:16 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 28 May 2013 13:10:16 +0200
Subject: [PATCH v5] clocksource: add Freescale Vybrid pit timer support
In-Reply-To: <1369732899-17142-1-git-send-email-b35083@freescale.com>
References: <1369732899-17142-1-git-send-email-b35083@freescale.com>
Message-ID: <51A49098.4000607@linaro.org>

On 05/28/2013 11:21 AM, Jingchang Lu wrote:
> Add Freescale Vybrid Family period interrupt timer support.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---

Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>

> v5:
>  Follow internal suggestions to name the SoC family as VF.
>  Add comment for min and max clockevent delta.
>  Add clockevent device irq initialization.
>  Remove IRQF_DISABLED flag.
> v4:
>   Use family name names driver and symbol instead of SoC name.
>   Remove redundant code.
>   Use BUG_ON instead of WARN_ON.
>   Add necessory comment information.
> v3:
>   Move the pit driver adding from arch to drivers/clocksource.
> v2:
>   Use CLOCKSOURCE_OF_DECLARE init pit timer.
>   Add ONESHOT mode support.
> 
>  drivers/clocksource/Kconfig        |   5 +
>  drivers/clocksource/Makefile       |   1 +
>  drivers/clocksource/vf_pit_timer.c | 194 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 200 insertions(+)
>  create mode 100644 drivers/clocksource/vf_pit_timer.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index f151c6c..0a04257 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
>  	  Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
>  	  for all devicetree enabled platforms. This driver will be
>  	  needed only on systems that do not have the Exynos MCT available.
> +
> +config VF_PIT_TIMER
> +	bool
> +	help
> +	  Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 8d979c7..36a9ac1 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
>  obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
>  obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
>  obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
> +obj-$(CONFIG_VF_PIT_TIMER)	+= vf_pit_timer.o
>  
>  obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
>  obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
> diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
> new file mode 100644
> index 0000000..598399d
> --- /dev/null
> +++ b/drivers/clocksource/vf_pit_timer.c
> @@ -0,0 +1,194 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/clockchips.h>
> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <asm/sched_clock.h>
> +
> +/*
> + * Each pit takes 0x10 Bytes register space
> + */
> +#define PITMCR		0x00
> +#define PIT0_OFFSET	0x100
> +#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
> +#define PITLDVAL	0x00
> +#define PITCVAL		0x04
> +#define PITTCTRL	0x08
> +#define PITTFLG		0x0c
> +
> +#define PITMCR_MDIS	(0x1 << 1)
> +
> +#define PITTCTRL_TEN	(0x1 << 0)
> +#define PITTCTRL_TIE	(0x1 << 1)
> +#define PITCTRL_CHN	(0x1 << 2)
> +
> +#define PITTFLG_TIF	0x1
> +
> +static void __iomem *clksrc_base;
> +static void __iomem *clkevt_base;
> +static unsigned long cycle_per_jiffy;
> +
> +static inline void pit_timer_enable(void)
> +{
> +	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_timer_disable(void)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_acknowledge(void)
> +{
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +}
> +
> +static unsigned int pit_read_sched_clock(void)
> +{
> +	return __raw_readl(clksrc_base + PITCVAL);
> +}
> +
> +static int __init pit_clocksource_init(unsigned long rate)
> +{
> +	/* set the max load value and start the clock source counter */
> +	__raw_writel(0, clksrc_base + PITTCTRL);
> +	__raw_writel(~0UL, clksrc_base + PITLDVAL);
> +	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
> +
> +	setup_sched_clock(pit_read_sched_clock, 32, rate);
> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
> +			300, 32, clocksource_mmio_readl_down);
> +}
> +
> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	/*
> +	 * set a new value to PITLDVAL register will not restart the timer,
> +	 * to abort the current cycle and start a timer period with the new
> +	 * value, the timer must be disabled and enabled again.
> +	 * and the PITLAVAL should be set to delta minus one according to pit
> +	 * hardware requirement.
> +	 */
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_timer_enable();
> +
> +	return 0;
> +}
> +
> +static void pit_set_mode(enum clock_event_mode mode,
> +				struct clock_event_device *evt)
> +{
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		pit_set_next_event(cycle_per_jiffy, evt);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = dev_id;
> +
> +	pit_irq_acknowledge();
> +
> +	/*
> +	 * pit hardware doesn't support oneshot, it will generate an interrupt
> +	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,
> +	 * and start the counter again. So software need to disable the timer
> +	 * to stop the counter loop in ONESHOT mode.
> +	 */
> +	if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
> +		pit_timer_disable();
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct clock_event_device clockevent_pit = {
> +	.name		= "VF pit timer",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= pit_set_mode,
> +	.set_next_event	= pit_set_next_event,
> +	.rating		= 300,
> +};
> +
> +static struct irqaction pit_timer_irq = {
> +	.name		= "VF pit timer",
> +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= pit_timer_interrupt,
> +	.dev_id		= &clockevent_pit,
> +};
> +
> +static int __init pit_clockevent_init(unsigned long rate, int irq)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +
> +	BUG_ON(setup_irq(irq, &pit_timer_irq));
> +
> +	clockevent_pit.cpumask = cpumask_of(0);
> +	clockevent_pit.irq = irq;
> +	/*
> +	 * The value for the LDVAL register trigger is calculated as:
> +	 * LDVAL trigger = (period / clock period) - 1
> +	 * The pit is a 32-bit down count timer, when the conter value
> +	 * reaches 0, it will generate an interrupt, thus the minimal
> +	 * LDVAL trigger value is 1. And then the min_delta is
> +	 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
> +	 */
> +	clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
> +
> +	return 0;
> +}
> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	unsigned long clk_rate;
> +	int irq;
> +
> +	timer_base = of_iomap(np, 0);
> +	BUG_ON(!timer_base);
> +
> +	/*
> +	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
> +	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
> +	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
> +	 */
> +	clksrc_base = timer_base + PITn_OFFSET(2);
> +	clkevt_base = timer_base + PITn_OFFSET(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +	BUG_ON(irq <= 0);
> +
> +	pit_clk = of_clk_get(np, 0);
> +	BUG_ON(IS_ERR(pit_clk));
> +
> +	BUG_ON(clk_prepare_enable(pit_clk));
> +
> +	clk_rate = clk_get_rate(pit_clk);
> +	cycle_per_jiffy = clk_rate / (HZ);
> +
> +	/* enable the pit module */
> +	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
> +
> +	BUG_ON(pit_clocksource_init(clk_rate));
> +
> +	pit_clockevent_init(clk_rate, irq);
> +}
> +CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
> 


-- 
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From plagnioj at jcrosoft.com  Tue May 28 07:09:27 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 28 May 2013 13:09:27 +0200
Subject: [PATCH v6] video: imxfb: Add DT support
In-Reply-To: <1369564538-21835-1-git-send-email-mpa@pengutronix.de>
References: <1369564538-21835-1-git-send-email-mpa@pengutronix.de>
Message-ID: <20130528110927.GA23653@game.jcrosoft.org>

On 12:35 Sun 26 May     , Markus Pargmann wrote:
> Add devicetree support for imx framebuffer driver. It uses the generic
> display bindings and helper functions.
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Applied thanks

Best Regards,
J.
> ---
> 
> Notes:
>     Changed in v6:
>     - Rebased onto v3.10-rc2
>     - Dropped alpha support patch in this series
>     
>     Changed in v5:
>     - Fix compatible property of the example
>     - Rename property fsl,bpp to bits-per-pixel
>     - Add selects for FB_MODE_HELPERS and VIDEOMODE_HELPERS to Kconfig FB_IMX
>     
>     Changes in v4:
>     - Remove eukrea specific dmacr property.
>     - Add optional dmacr property. If not present, the dmacr reset value is not
>       changed.
>     
>     Changes in v3:
>     - Fix returncodes of of_read_mode function and print error messages
>     - Introduce a lower bound check for bits per pixel
>     - Calculate correct bytes per pixel value before using it for the calculation of
>     	memory size
>     - Change DT property names
>     
>     Changes in v2:
>     - Removed pwmr register property
>     - Cleanup of devicetree binding documentation
>     - Use default values for pwmr and lscr1
> 
>  .../devicetree/bindings/video/fsl,imx-fb.txt       |  51 ++++++
>  drivers/video/Kconfig                              |   2 +
>  drivers/video/imxfb.c                              | 194 +++++++++++++++++----
>  3 files changed, 212 insertions(+), 35 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/video/fsl,imx-fb.txt
> 
> diff --git a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
> new file mode 100644
> index 0000000..46da08d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
> @@ -0,0 +1,51 @@
> +Freescale imx21 Framebuffer
> +
> +This framebuffer driver supports devices imx1, imx21, imx25, and imx27.
> +
> +Required properties:
> +- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
> +- reg : Should contain 1 register ranges(address and length)
> +- interrupts : One interrupt of the fb dev
> +
> +Required nodes:
> +- display: Phandle to a display node as described in
> +	Documentation/devicetree/bindings/video/display-timing.txt
> +	Additional, the display node has to define properties:
> +	- bits-per-pixel: Bits per pixel
> +	- fsl,pcr: LCDC PCR value
> +
> +Optional properties:
> +- fsl,dmacr: DMA Control Register value. This is optional. By default, the
> +	register is not modified as recommended by the datasheet.
> +- fsl,lscr1: LCDC Sharp Configuration Register value.
> +
> +Example:
> +
> +	imxfb: fb at 10021000 {
> +		compatible = "fsl,imx21-fb";
> +		interrupts = <61>;
> +		reg = <0x10021000 0x1000>;
> +		display = <&display0>;
> +	};
> +
> +	...
> +
> +	display0: display0 {
> +		model = "Primeview-PD050VL1";
> +		native-mode = <&timing_disp0>;
> +		bits-per-pixel = <16>;
> +		fsl,pcr = <0xf0c88080>;	/* non-standard but required */
> +		display-timings {
> +			timing_disp0: 640x480 {
> +				hactive = <640>;
> +				vactive = <480>;
> +				hback-porch = <112>;
> +				hfront-porch = <36>;
> +				hsync-len = <32>;
> +				vback-porch = <33>;
> +				vfront-porch = <33>;
> +				vsync-len = <2>;
> +				clock-frequency = <25000000>;
> +			};
> +		};
> +	};
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index d71d60f..588af1d 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -367,6 +367,8 @@ config FB_IMX
>  	select FB_CFB_FILLRECT
>  	select FB_CFB_COPYAREA
>  	select FB_CFB_IMAGEBLIT
> +	select FB_MODE_HELPERS
> +	select VIDEOMODE_HELPERS
>  
>  config FB_CYBER2000
>  	tristate "CyberPro 2000/2010/5000 support"
> diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
> index 0abf2bf..a2ed71d 100644
> --- a/drivers/video/imxfb.c
> +++ b/drivers/video/imxfb.c
> @@ -31,6 +31,12 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/io.h>
>  #include <linux/math64.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +
> +#include <video/of_display_timing.h>
> +#include <video/of_videomode.h>
> +#include <video/videomode.h>
>  
>  #include <linux/platform_data/video-imxfb.h>
>  
> @@ -112,10 +118,11 @@
>  #define LCDISR_EOF	(1<<1)
>  #define LCDISR_BOF	(1<<0)
>  
> +#define IMXFB_LSCR1_DEFAULT 0x00120300
> +
>  /* Used fb-mode. Can be set on kernel command line, therefore file-static. */
>  static const char *fb_mode;
>  
> -
>  /*
>   * These are the bitfields for each
>   * display depth that we support.
> @@ -187,6 +194,19 @@ static struct platform_device_id imxfb_devtype[] = {
>  };
>  MODULE_DEVICE_TABLE(platform, imxfb_devtype);
>  
> +static struct of_device_id imxfb_of_dev_id[] = {
> +	{
> +		.compatible = "fsl,imx1-fb",
> +		.data = &imxfb_devtype[IMX1_FB],
> +	}, {
> +		.compatible = "fsl,imx21-fb",
> +		.data = &imxfb_devtype[IMX21_FB],
> +	}, {
> +		/* sentinel */
> +	}
> +};
> +MODULE_DEVICE_TABLE(of, imxfb_of_dev_id);
> +
>  static inline int is_imx1_fb(struct imxfb_info *fbi)
>  {
>  	return fbi->devtype == IMX1_FB;
> @@ -319,6 +339,9 @@ static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
>  	struct imx_fb_videomode *m;
>  	int i;
>  
> +	if (!fb_mode)
> +		return &fbi->mode[0];
> +
>  	for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
>  		if (!strcmp(m->mode.name, fb_mode))
>  			return m;
> @@ -474,6 +497,9 @@ static int imxfb_bl_update_status(struct backlight_device *bl)
>  	struct imxfb_info *fbi = bl_get_data(bl);
>  	int brightness = bl->props.brightness;
>  
> +	if (!fbi->pwmr)
> +		return 0;
> +
>  	if (bl->props.power != FB_BLANK_UNBLANK)
>  		brightness = 0;
>  	if (bl->props.fb_blank != FB_BLANK_UNBLANK)
> @@ -684,10 +710,14 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
>  
>  	writel(fbi->pcr, fbi->regs + LCDC_PCR);
>  #ifndef PWMR_BACKLIGHT_AVAILABLE
> -	writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
> +	if (fbi->pwmr)
> +		writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
>  #endif
>  	writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
> -	writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
> +
> +	/* dmacr = 0 is no valid value, as we need DMA control marks. */
> +	if (fbi->dmacr)
> +		writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
>  
>  	return 0;
>  }
> @@ -723,13 +753,12 @@ static int imxfb_resume(struct platform_device *dev)
>  #define imxfb_resume	NULL
>  #endif
>  
> -static int __init imxfb_init_fbinfo(struct platform_device *pdev)
> +static int imxfb_init_fbinfo(struct platform_device *pdev)
>  {
>  	struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
>  	struct fb_info *info = dev_get_drvdata(&pdev->dev);
>  	struct imxfb_info *fbi = info->par;
> -	struct imx_fb_videomode *m;
> -	int i;
> +	struct device_node *np;
>  
>  	pr_debug("%s\n",__func__);
>  
> @@ -760,41 +789,95 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
>  	info->fbops			= &imxfb_ops;
>  	info->flags			= FBINFO_FLAG_DEFAULT |
>  					  FBINFO_READS_FAST;
> -	info->var.grayscale		= pdata->cmap_greyscale;
> -	fbi->cmap_inverse		= pdata->cmap_inverse;
> -	fbi->cmap_static		= pdata->cmap_static;
> -	fbi->lscr1			= pdata->lscr1;
> -	fbi->dmacr			= pdata->dmacr;
> -	fbi->pwmr			= pdata->pwmr;
> -	fbi->lcd_power			= pdata->lcd_power;
> -	fbi->backlight_power		= pdata->backlight_power;
> -
> -	for (i = 0, m = &pdata->mode[0]; i < pdata->num_modes; i++, m++)
> -		info->fix.smem_len = max_t(size_t, info->fix.smem_len,
> -				m->mode.xres * m->mode.yres * m->bpp / 8);
> +	if (pdata) {
> +		info->var.grayscale		= pdata->cmap_greyscale;
> +		fbi->cmap_inverse		= pdata->cmap_inverse;
> +		fbi->cmap_static		= pdata->cmap_static;
> +		fbi->lscr1			= pdata->lscr1;
> +		fbi->dmacr			= pdata->dmacr;
> +		fbi->pwmr			= pdata->pwmr;
> +		fbi->lcd_power			= pdata->lcd_power;
> +		fbi->backlight_power		= pdata->backlight_power;
> +	} else {
> +		np = pdev->dev.of_node;
> +		info->var.grayscale = of_property_read_bool(np,
> +						"cmap-greyscale");
> +		fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse");
> +		fbi->cmap_static = of_property_read_bool(np, "cmap-static");
> +
> +		fbi->lscr1 = IMXFB_LSCR1_DEFAULT;
> +		of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1);
> +
> +		of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr);
> +
> +		/* These two function pointers could be used by some specific
> +		 * platforms. */
> +		fbi->lcd_power = NULL;
> +		fbi->backlight_power = NULL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int imxfb_of_read_mode(struct device *dev, struct device_node *np,
> +		struct imx_fb_videomode *imxfb_mode)
> +{
> +	int ret;
> +	struct fb_videomode *of_mode = &imxfb_mode->mode;
> +	u32 bpp;
> +	u32 pcr;
> +
> +	ret = of_property_read_string(np, "model", &of_mode->name);
> +	if (ret)
> +		of_mode->name = NULL;
> +
> +	ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE);
> +	if (ret) {
> +		dev_err(dev, "Failed to get videomode from DT\n");
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(np, "bits-per-pixel", &bpp);
> +	ret |= of_property_read_u32(np, "fsl,pcr", &pcr);
> +
> +	if (ret) {
> +		dev_err(dev, "Failed to read bpp and pcr from DT\n");
> +		return -EINVAL;
> +	}
> +
> +	if (bpp < 1 || bpp > 255) {
> +		dev_err(dev, "Bits per pixel have to be between 1 and 255\n");
> +		return -EINVAL;
> +	}
> +
> +	imxfb_mode->bpp = bpp;
> +	imxfb_mode->pcr = pcr;
>  
>  	return 0;
>  }
>  
> -static int __init imxfb_probe(struct platform_device *pdev)
> +static int imxfb_probe(struct platform_device *pdev)
>  {
>  	struct imxfb_info *fbi;
>  	struct fb_info *info;
>  	struct imx_fb_platform_data *pdata;
>  	struct resource *res;
> +	struct imx_fb_videomode *m;
> +	const struct of_device_id *of_id;
>  	int ret, i;
> +	int bytes_per_pixel;
>  
>  	dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
>  
> +	of_id = of_match_device(imxfb_of_dev_id, &pdev->dev);
> +	if (of_id)
> +		pdev->id_entry = of_id->data;
> +
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (!res)
>  		return -ENODEV;
>  
>  	pdata = pdev->dev.platform_data;
> -	if (!pdata) {
> -		dev_err(&pdev->dev,"No platform_data available\n");
> -		return -ENOMEM;
> -	}
>  
>  	info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
>  	if (!info)
> @@ -802,15 +885,55 @@ static int __init imxfb_probe(struct platform_device *pdev)
>  
>  	fbi = info->par;
>  
> -	if (!fb_mode)
> -		fb_mode = pdata->mode[0].mode.name;
> -
>  	platform_set_drvdata(pdev, info);
>  
>  	ret = imxfb_init_fbinfo(pdev);
>  	if (ret < 0)
>  		goto failed_init;
>  
> +	if (pdata) {
> +		if (!fb_mode)
> +			fb_mode = pdata->mode[0].mode.name;
> +
> +		fbi->mode = pdata->mode;
> +		fbi->num_modes = pdata->num_modes;
> +	} else {
> +		struct device_node *display_np;
> +		fb_mode = NULL;
> +
> +		display_np = of_parse_phandle(pdev->dev.of_node, "display", 0);
> +		if (!display_np) {
> +			dev_err(&pdev->dev, "No display defined in devicetree\n");
> +			ret = -EINVAL;
> +			goto failed_of_parse;
> +		}
> +
> +		/*
> +		 * imxfb does not support more modes, we choose only the native
> +		 * mode.
> +		 */
> +		fbi->num_modes = 1;
> +
> +		fbi->mode = devm_kzalloc(&pdev->dev,
> +				sizeof(struct imx_fb_videomode), GFP_KERNEL);
> +		if (!fbi->mode) {
> +			ret = -ENOMEM;
> +			goto failed_of_parse;
> +		}
> +
> +		ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode);
> +		if (ret)
> +			goto failed_of_parse;
> +	}
> +
> +	/* Calculate maximum bytes used per pixel. In most cases this should
> +	 * be the same as m->bpp/8 */
> +	m = &fbi->mode[0];
> +	bytes_per_pixel = (m->bpp + 7) / 8;
> +	for (i = 0; i < fbi->num_modes; i++, m++)
> +		info->fix.smem_len = max_t(size_t, info->fix.smem_len,
> +				m->mode.xres * m->mode.yres * bytes_per_pixel);
> +
>  	res = request_mem_region(res->start, resource_size(res),
>  				DRIVER_NAME);
>  	if (!res) {
> @@ -843,7 +966,8 @@ static int __init imxfb_probe(struct platform_device *pdev)
>  		goto failed_ioremap;
>  	}
>  
> -	if (!pdata->fixed_screen_cpu) {
> +	/* Seems not being used by anyone, so no support for oftree */
> +	if (!pdata || !pdata->fixed_screen_cpu) {
>  		fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
>  		fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
>  				fbi->map_size, &fbi->map_dma, GFP_KERNEL);
> @@ -868,18 +992,16 @@ static int __init imxfb_probe(struct platform_device *pdev)
>  		info->fix.smem_start = fbi->screen_dma;
>  	}
>  
> -	if (pdata->init) {
> +	if (pdata && pdata->init) {
>  		ret = pdata->init(fbi->pdev);
>  		if (ret)
>  			goto failed_platform_init;
>  	}
>  
> -	fbi->mode = pdata->mode;
> -	fbi->num_modes = pdata->num_modes;
>  
>  	INIT_LIST_HEAD(&info->modelist);
> -	for (i = 0; i < pdata->num_modes; i++)
> -		fb_add_videomode(&pdata->mode[i].mode, &info->modelist);
> +	for (i = 0; i < fbi->num_modes; i++)
> +		fb_add_videomode(&fbi->mode[i].mode, &info->modelist);
>  
>  	/*
>  	 * This makes sure that our colour bitfield
> @@ -909,10 +1031,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
>  failed_register:
>  	fb_dealloc_cmap(&info->cmap);
>  failed_cmap:
> -	if (pdata->exit)
> +	if (pdata && pdata->exit)
>  		pdata->exit(fbi->pdev);
>  failed_platform_init:
> -	if (!pdata->fixed_screen_cpu)
> +	if (pdata && !pdata->fixed_screen_cpu)
>  		dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
>  			fbi->map_dma);
>  failed_map:
> @@ -921,6 +1043,7 @@ failed_ioremap:
>  failed_getclock:
>  	release_mem_region(res->start, resource_size(res));
>  failed_req:
> +failed_of_parse:
>  	kfree(info->pseudo_palette);
>  failed_init:
>  	platform_set_drvdata(pdev, NULL);
> @@ -945,7 +1068,7 @@ static int imxfb_remove(struct platform_device *pdev)
>  	unregister_framebuffer(info);
>  
>  	pdata = pdev->dev.platform_data;
> -	if (pdata->exit)
> +	if (pdata && pdata->exit)
>  		pdata->exit(fbi->pdev);
>  
>  	fb_dealloc_cmap(&info->cmap);
> @@ -974,6 +1097,7 @@ static struct platform_driver imxfb_driver = {
>  	.shutdown	= imxfb_shutdown,
>  	.driver		= {
>  		.name	= DRIVER_NAME,
> +		.of_match_table = imxfb_of_dev_id,
>  	},
>  	.id_table	= imxfb_devtype,
>  };
> -- 
> 1.8.2.1
> 


From thierry.reding at gmail.com  Tue May 28 07:19:23 2013
From: thierry.reding at gmail.com (Thierry Reding)
Date: Tue, 28 May 2013 13:19:23 +0200
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
In-Reply-To: <87li6z2yxj.fsf@natisbad.org>
References: <cover.1369687670.git.arno@natisbad.org>
 <152190814.eApXVbVBPA@wuerfel> <87li6z2yxj.fsf@natisbad.org>
Message-ID: <20130528111921.GD11547@mithrandir>

On Tue, May 28, 2013 at 12:15:04PM +0200, Arnaud Ebalard wrote:
> Hi Arnd,
> 
> Arnd Bergmann <arnd at arndb.de> writes:
> 
> > On Tuesday 28 May 2013 00:02:29 Arnaud Ebalard wrote:
> >> 
> >> This series adds support for GMT G762/G763. This work is based on a
> >> basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
> >> NAS. Updates have been performed to run on recent kernels. Support has
> >> been completed and additional features added: ability to configure
> >> various characteristics from .dts file, better initialization, alarms
> >> and error reporting support, gear mode, polarity, fan pulse per
> >> revolution, fan startup voltage control.
> >
> > I wonder if this could be split into two separate drivers, one for
> > the pwm subsystem, and one for a hardware-independent fan controller
> > based on the pwm interfaces.
> 
> To be honest, I wouldn't even know how to start in order to do that.
> Additionally, it would be worth the effort if other drivers could be
> easily refactored using this idea. I'll let hwmon people provide some
> feedback and try and comply with their directions (based on the cpu
> cycle I can spend on this).

What Arnd proposes doesn't sounds like a very good idea. PWM-controlled
fans should be able to work just fine using a generic driver that uses
the PWM framework, similar to the PWM backlight and LED drivers.

Thierry
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From stefano.stabellini at eu.citrix.com  Tue May 28 07:08:59 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 12:08:59 +0100
Subject: [GIT PULL for 3.11] arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305281205500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305281205500.4799@kaball.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305281208010.4799@kaball.uk.xensource.com>

Sorry for the noise, I have seen now that you pulled
3.10-rc2-psci-ops-11-tag into "devel-stable".

Thanks,

Stefano


On Tue, 28 May 2013, Stefano Stabellini wrote:
> ping?
> 
> 
> On Tue, 21 May 2013, Stefano Stabellini wrote:
> > Russell,
> > please pull (based on v3.10-rc2):
> > 
> > git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git 3.10-rc2-psci-ops-11-tag
> > 
> > 
> > It contains the generic PSCI patch and the smp_init patch that we
> > discussed so much about.
> > I think it would be helpful for other people if you could create a
> > stable branch with these patches so that SoC devs can base their work on
> > it.
> > 
> > 
> > Jon Medhurst (1):
> >       ARM: Enable selection of SMP operations at boot time
> > 
> > Stefano Stabellini (1):
> >       arm: introduce psci_smp_ops
> > 
> >  arch/arm/include/asm/mach/arch.h |    5 ++
> >  arch/arm/include/asm/psci.h      |    9 ++++
> >  arch/arm/kernel/Makefile         |    5 ++-
> >  arch/arm/kernel/psci.c           |    7 +--
> >  arch/arm/kernel/psci_smp.c       |   84 ++++++++++++++++++++++++++++++++++++++
> >  arch/arm/kernel/setup.c          |    9 ++++-
> >  arch/arm/mach-virt/Makefile      |    1 -
> >  arch/arm/mach-virt/platsmp.c     |   50 ----------------------
> >  arch/arm/mach-virt/virt.c        |    3 -
> >  9 files changed, 113 insertions(+), 60 deletions(-)
> >  create mode 100644 arch/arm/kernel/psci_smp.c
> >  delete mode 100644 arch/arm/mach-virt/platsmp.c
> > 
> 


From stefano.stabellini at eu.citrix.com  Tue May 28 07:05:58 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 12:05:58 +0100
Subject: [GIT PULL for 3.11] arm: introduce psci_smp_ops
In-Reply-To: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305211522120.4799@kaball.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305281205500.4799@kaball.uk.xensource.com>

ping?


On Tue, 21 May 2013, Stefano Stabellini wrote:
> Russell,
> please pull (based on v3.10-rc2):
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git 3.10-rc2-psci-ops-11-tag
> 
> 
> It contains the generic PSCI patch and the smp_init patch that we
> discussed so much about.
> I think it would be helpful for other people if you could create a
> stable branch with these patches so that SoC devs can base their work on
> it.
> 
> 
> Jon Medhurst (1):
>       ARM: Enable selection of SMP operations at boot time
> 
> Stefano Stabellini (1):
>       arm: introduce psci_smp_ops
> 
>  arch/arm/include/asm/mach/arch.h |    5 ++
>  arch/arm/include/asm/psci.h      |    9 ++++
>  arch/arm/kernel/Makefile         |    5 ++-
>  arch/arm/kernel/psci.c           |    7 +--
>  arch/arm/kernel/psci_smp.c       |   84 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/kernel/setup.c          |    9 ++++-
>  arch/arm/mach-virt/Makefile      |    1 -
>  arch/arm/mach-virt/platsmp.c     |   50 ----------------------
>  arch/arm/mach-virt/virt.c        |    3 -
>  9 files changed, 113 insertions(+), 60 deletions(-)
>  create mode 100644 arch/arm/kernel/psci_smp.c
>  delete mode 100644 arch/arm/mach-virt/platsmp.c
> 


From gang.chen at asianux.com  Tue May 28 07:21:01 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Tue, 28 May 2013 19:21:01 +0800
Subject: [PATCH v2] arch: arm64: kernel: sprintf(), 'str' needs additional
 1 byte for failure processing
In-Reply-To: <20130528104250.GE10474@mudshark.cambridge.arm.com>
References: <51A1E3B3.4060901@asianux.com> <51A2BE2C.2000004@asianux.com>
 <20130528104250.GE10474@mudshark.cambridge.arm.com>
Message-ID: <51A4931D.9090209@asianux.com>

On 05/28/2013 06:42 PM, Will Deacon wrote:
> Hello,
> 
> On Mon, May 27, 2013 at 03:00:12AM +0100, Chen Gang wrote:
>> > 
>> > When failure occurs at the last looping cycle (when 'i == 0'), it will
>> > print "bad PC value" instead of "(%08x) ", which needs additional 1
>> > byte.
>> > 
>> > If not add 1 byte, the 'str' may be memory overflow.
>> > 
>> > 
>> > Signed-off-by: Chen Gang <gang.chen at asianux.com>
>> > ---
>> >  arch/arm64/kernel/traps.c |    2 +-
>> >  1 files changed, 1 insertions(+), 1 deletions(-)
>> > 
>> > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
>> > index 61d7dd2..c2f68d2 100644
>> > --- a/arch/arm64/kernel/traps.c
>> > +++ b/arch/arm64/kernel/traps.c
>> > @@ -100,7 +100,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
>> >  {
>> >  	unsigned long addr = instruction_pointer(regs);
>> >  	mm_segment_t fs;
>> > -	char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
>> > +	char str[sizeof("00000000 ") * 5 + 2 + 1 + 1], *p = str;
>> >  	int i;
> Whilst this code is difficult to follow, I don't think it's incorrect.
> The size of the str array is:
> 
> 	sizeof("00000000 ") = 8 ('0's) + 1 (space) + 1 (NUL) = 10 bytes

Oh, it is my fault, I miss the "1 (NUL)".

> 	*5 = 50 bytes
> 	+2 (for the two brackets when i == 0) = 52 bytes
> 	+1 (this is for the "bad PC value") = 53 bytes
> 
> In the worst case (when the PC is bad) we print:
> 
> 	"%08x " x4 = (8 + 1 + 1) *4 = 40 bytes

Actually, it is 36 bytes, for sprintf() return the length excluding NUL.

  (although, we still need notice the last NUL)


> 	"bad PC value" = 12 + 1 = 13 bytes
> 
> so again, 53 bytes.
>

So again, 49 bytes. ;-)


> .. or have I missed a character somewhere?
> 

NO, I missed characters, but you 'find' more characters. :-)


All together, this patch is incorrect, original implementation will not
cause issue.


Thanks
-- 
Chen Gang

Asianux Corporation


From alexandre.belloni at free-electrons.com  Tue May 28 07:43:20 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Tue, 28 May 2013 13:43:20 +0200
Subject: [PATCHv2 0/3] net: phy: prevent linking breakage
Message-ID: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>

There is a linking issue when using phy_register_fixup{,_for_uid,_for_id} and
CONFIG_PHYLIB is not a builtin:

arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'

This has been solved for arch/arm/mach-mxs/ and arch/arm/mach-imx/ by testing
IS_BUILTIN(CONFIG_PHYLIB) before calling the functions.

The first patch is an attempt at solving that issue globally.

The following patches remove the unnecessary IS_BUILTIN(CONFIG_PHYLIB) checks.

Quickly greping into the code shows that the issue may arise in:

arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/arm/mach-davinci/board-dm644x-evm.c
arch/arm/mach-orion5x/dns323-setup.c
arch/arm/mach-at91/board-dt-sama5.c

Changes in v2:
 - indentation fixes
 - use static inline function instead of defines and return -ENOTSUPP

Alexandre Belloni (3):
  net: phy: prevent linking breakage
  arm: mxs: don't check for CONFIG_PHYLIB as builtin
  arm: imx: don't check for CONFIG_PHYLIB as builtin

 arch/arm/mach-imx/mach-imx6q.c | 23 ++++++++++-------------
 arch/arm/mach-mxs/mach-mxs.c   |  5 ++---
 drivers/net/phy/phy_device.c   |  6 ++++++
 include/linux/phy.h            | 26 ++++++++++++++++++++++++++
 4 files changed, 44 insertions(+), 16 deletions(-)

-- 
1.8.1.2



From alexandre.belloni at free-electrons.com  Tue May 28 07:43:21 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Tue, 28 May 2013 13:43:21 +0200
Subject: [PATCHv2 1/3] net: phy: prevent linking breakage
In-Reply-To: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <1369741403-25315-2-git-send-email-alexandre.belloni@free-electrons.com>

phy_register_fixup{,_for_uid,_for_id} are called from arch/, quite
often, there is no protection to check whether CONFIG_PHYLIB=y which is
the only case where this would work. Having phylib as a module or not
compiled at all will result in that kind of linking failure:

arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
:(.text+0x1174): undefined reference to `mdiobus_write'
:(.text+0x1188): undefined reference to `mdiobus_write'
:(.text+0x119c): undefined reference to `mdiobus_write'
:(.text+0x11b0): undefined reference to `mdiobus_write'
arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
:(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 drivers/net/phy/phy_device.c |  6 ++++++
 include/linux/phy.h          | 33 ++++++++++++++++++++++++++++++---
 2 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 3657b4a..df36367 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -64,6 +64,11 @@ static int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
 			     u32 flags, phy_interface_t interface);
 
 /*
+ *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
+ *  work unless phylib is compiled in the kernel.
+ */
+#ifdef CONFIG_PHYLIB
+/*
  * Creates a new phy_fixup and adds it to the list
  * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID)
  * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
@@ -109,6 +114,7 @@ int phy_register_fixup_for_id(const char *bus_id,
 	return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
 }
 EXPORT_SYMBOL(phy_register_fixup_for_id);
+#endif /* CONFIG_PHYLIB */
 
 /*
  * Returns 1 if fixup matches phydev in bus_id and phy_uid.
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 9e11039..2cc3383 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -556,12 +556,39 @@ int phy_start_interrupts(struct phy_device *phydev);
 void phy_print_status(struct phy_device *phydev);
 void phy_device_free(struct phy_device *phydev);
 
+/*
+ *  phy_register_fixup{,_for_uid,_for_id} are called from arch/ so this won't
+ *  work unless phylib is compiled in the kernel.
+ *  Defining stubs allows to prevent linking errors.
+ */
+#ifdef CONFIG_PHYLIB
 int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
-		int (*run)(struct phy_device *));
+		       int (*run)(struct phy_device *));
 int phy_register_fixup_for_id(const char *bus_id,
-		int (*run)(struct phy_device *));
+			      int (*run)(struct phy_device *));
 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
-		int (*run)(struct phy_device *));
+			       int (*run)(struct phy_device *));
+#else
+static inline int phy_register_fixup(const char *bus_id, u32 phy_uid,
+				     u32 phy_uid_mask,
+				     int (*run)(struct phy_device *))
+{
+	return -ENOTSUPP;
+}
+
+static inline int phy_register_fixup_for_id(const char *bus_id,
+					    int (*run)(struct phy_device *))
+{
+	return -ENOTSUPP;
+}
+
+static inline int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
+					     int (*run)(struct phy_device *))
+{
+	return -ENOTSUPP;
+}
+#endif /* CONFIG_PHYLIB */
+
 int phy_scan_fixups(struct phy_device *phydev);
 
 int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
-- 
1.8.1.2



From alexandre.belloni at free-electrons.com  Tue May 28 07:43:22 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Tue, 28 May 2013 13:43:22 +0200
Subject: [PATCHv2 2/3] arm: mxs: don't check for CONFIG_PHYLIB as builtin
In-Reply-To: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <1369741403-25315-3-git-send-email-alexandre.belloni@free-electrons.com>

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b64..2dad553 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -273,9 +273,8 @@ static void __init apx4devkit_init(void)
 {
 	enable_clk_enet_out();
 
-	if (IS_BUILTIN(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
-					   apx4devkit_phy_fixup);
+	phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
+				   apx4devkit_phy_fixup);
 }
 
 #define ENET0_MDC__GPIO_4_0	MXS_GPIO_NR(4, 0)
-- 
1.8.1.2



From alexandre.belloni at free-electrons.com  Tue May 28 07:43:23 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Tue, 28 May 2013 13:43:23 +0200
Subject: [PATCHv2 3/3] arm: imx: don't check for CONFIG_PHYLIB as builtin
In-Reply-To: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <1369741403-25315-4-git-send-email-alexandre.belloni@free-electrons.com>

Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>
---
 arch/arm/mach-imx/mach-imx6q.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..9094849 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -99,16 +99,14 @@ soft:
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
-	if (IS_BUILTIN(CONFIG_PHYLIB)) {
-		/* min rx data delay */
-		phy_write(phydev, 0x0b, 0x8105);
-		phy_write(phydev, 0x0c, 0x0000);
-
-		/* max rx/tx clock delay, min rx/tx control delay */
-		phy_write(phydev, 0x0b, 0x8104);
-		phy_write(phydev, 0x0c, 0xf0f0);
-		phy_write(phydev, 0x0b, 0x104);
-	}
+	/* min rx data delay */
+	phy_write(phydev, 0x0b, 0x8105);
+	phy_write(phydev, 0x0c, 0x0000);
+
+	/* max rx/tx clock delay, min rx/tx control delay */
+	phy_write(phydev, 0x0b, 0x8104);
+	phy_write(phydev, 0x0c, 0xf0f0);
+	phy_write(phydev, 0x0b, 0x104);
 
 	return 0;
 }
@@ -139,9 +137,8 @@ put_clk:
 
 static void __init imx6q_sabrelite_init(void)
 {
-	if (IS_BUILTIN(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-				ksz9021rn_phy_fixup);
+	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+				   ksz9021rn_phy_fixup);
 	imx6q_sabrelite_cko1_setup();
 }
 
-- 
1.8.1.2



From aida.mynzhasova at skitlab.ru  Tue May 28 07:46:17 2013
From: aida.mynzhasova at skitlab.ru (Aida Mynzhasova)
Date: Tue, 28 May 2013 15:46:17 +0400
Subject: [PATCH] ARM: OMAP: fix IVA2 module base address
Message-ID: <1369741577-21984-1-git-send-email-aida.mynzhasova@skitlab.ru>

This patch corrects the base address of IVA2 module on omap3430.

Signed-off-by: Aida Mynzhasova <aida.mynzhasova at skitlab.ru>
---
 arch/arm/mach-omap2/prcm-common.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c7d355f..d5ec044 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -37,7 +37,7 @@
 #define OMAP2430_MDM_MOD				0xc00
 
 /* IVA2 module is < base on 3430 */
-#define OMAP3430_IVA2_MOD				-0x800
+#define OMAP3430_IVA2_MOD				0x800
 #define OMAP3430ES2_SGX_MOD				GFX_MOD
 #define OMAP3430_CCR_MOD				PLL_MOD
 #define OMAP3430_DSS_MOD				0x600
-- 
1.7.10.4



From jason at lakedaemon.net  Tue May 28 07:52:30 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 07:52:30 -0400
Subject: [GIT PULL] ARM: mvebu: fixes for v3.10 (round 3)
In-Reply-To: <20130528023158.GB13532@quad.lixom.net>
References: <20130527185436.GN31290@titan.lakedaemon.net>
 <20130528023158.GB13532@quad.lixom.net>
Message-ID: <20130528115230.GQ31290@titan.lakedaemon.net>

On Mon, May 27, 2013 at 07:31:58PM -0700, Olof Johansson wrote:
> Hi,
> 
> On Mon, May 27, 2013 at 02:54:36PM -0400, Jason Cooper wrote:
> 
> > Thomas Petazzoni (2):
> >       arm: mvebu: fix length of SATA registers area in .dtsi
> >       arm: mvebu: fix length of Ethernet registers area in .dtsi
> 
> Is this an actual regression in 3.10?

Nope, it's just wrong.  :)

> I can understand having to fix this before the static mapping is removed,
> but if it's still there for 3.10, then it makes more sense to queue these
> fixes for 3.11 (we tend to collect a "fixes-non-critical" that is merged
> before any other branches in the next merge window).

ok, please drop this PR, I'll rework this and submit fresh ones.

thx,

Jason.


From fabio.estevam at freescale.com  Tue May 28 08:04:30 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Tue, 28 May 2013 09:04:30 -0300
Subject: [PATCH] ARM: dt: Use the 'model' field for printing the hardware
 revision
Message-ID: <1369742670-16305-1-git-send-email-fabio.estevam@freescale.com>

When booting a device tree kernel, we get the following output from 
'cat /proc/cpuinfo': 

$ cat /proc/cpuinfo 
processor       : 0
model name      : ARMv7 Processor rev 5 (v7l)
BogoMIPS        : 531.66
Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls 
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x2
CPU part        : 0xc08
CPU revision    : 5

Hardware        : Freescale i.MX51 (Device Tree Support)
Revision        : 0000
Serial          : 0000000000000000

The Hardware line does not really describe the hardware type, as it is reading
the information from the dt 'machine' field.

In the dt case, read the 'model' field instead, so that we can have a better
description output as follows:

Hardware        : Freescale i.MX51 Babbage Board

The hardware output string is unchanged for the non-dt kernel case.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/include/asm/mach/arch.h |  1 +
 arch/arm/kernel/devtree.c        | 15 ++++++++-------
 arch/arm/kernel/setup.c          |  7 ++++++-
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..113d4af 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -23,6 +23,7 @@ struct smp_operations;
 struct machine_desc {
 	unsigned int		nr;		/* architecture number	*/
 	const char		*name;		/* architecture name	*/
+	const char		*model;		/* architectute model */
 	unsigned long		atag_offset;	/* tagged list (relative) */
 	const char *const 	*dt_compat;	/* array of device tree
 						 * 'compatible' strings	*/
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..90d541a 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -178,7 +178,6 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
 	struct machine_desc *mdesc, *mdesc_best = NULL;
 	unsigned int score, mdesc_score = ~1;
 	unsigned long dt_root;
-	const char *model;
 
 #ifdef CONFIG_ARCH_MULTIPLATFORM
 	DT_MACHINE_START(GENERIC_DT, "Generic DT based system")
@@ -224,12 +223,14 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
 		dump_machine_table(); /* does not return */
 	}
 
-	model = of_get_flat_dt_prop(dt_root, "model", NULL);
-	if (!model)
-		model = of_get_flat_dt_prop(dt_root, "compatible", NULL);
-	if (!model)
-		model = "<unknown>";
-	pr_info("Machine: %s, model: %s\n", mdesc_best->name, model);
+	mdesc_best->model = of_get_flat_dt_prop(dt_root, "model", NULL);
+	if (!mdesc_best->model)
+		mdesc_best->model = of_get_flat_dt_prop(dt_root, "compatible",
+							NULL);
+	if (!mdesc_best->model)
+		mdesc_best->model = "<unknown>";
+	pr_info("Machine: %s, model: %s\n", mdesc_best->name,
+		mdesc_best->model);
 
 	/* Retrieve various information from the /chosen node */
 	of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 79e8d2f..d22f24b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -137,6 +137,7 @@ EXPORT_SYMBOL(elf_platform);
 
 static const char *cpu_name;
 static const char *machine_name;
+static const char *model_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
 struct machine_desc *machine_desc __initdata;
 
@@ -786,6 +787,7 @@ void __init setup_arch(char **cmdline_p)
 		mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
 	machine_desc = mdesc;
 	machine_name = mdesc->name;
+	model_name = mdesc->model;
 
 	setup_dma_zone(mdesc);
 
@@ -950,7 +952,10 @@ static int c_show(struct seq_file *m, void *v)
 		seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
 	}
 
-	seq_printf(m, "Hardware\t: %s\n", machine_name);
+	if (model_name)
+		seq_printf(m, "Hardware\t: %s\n", model_name);
+	else
+		seq_printf(m, "Hardware\t: %s\n", machine_name);
 	seq_printf(m, "Revision\t: %04x\n", system_rev);
 	seq_printf(m, "Serial\t\t: %08x%08x\n",
 		   system_serial_high, system_serial_low);
-- 
1.8.1.2




From u.kleine-koenig at pengutronix.de  Tue May 28 08:15:07 2013
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 28 May 2013 14:15:07 +0200
Subject: [PATCH] ARM: dt: Use the 'model' field for printing the hardware
 revision
In-Reply-To: <1369742670-16305-1-git-send-email-fabio.estevam@freescale.com>
References: <1369742670-16305-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20130528121506.GL11166@pengutronix.de>

On Tue, May 28, 2013 at 09:04:30AM -0300, Fabio Estevam wrote:
> When booting a device tree kernel, we get the following output from 
> 'cat /proc/cpuinfo': 
> 
> $ cat /proc/cpuinfo 
> processor       : 0
> model name      : ARMv7 Processor rev 5 (v7l)
> BogoMIPS        : 531.66
> Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls 
> CPU implementer : 0x41
> CPU architecture: 7
> CPU variant     : 0x2
> CPU part        : 0xc08
> CPU revision    : 5
> 
> Hardware        : Freescale i.MX51 (Device Tree Support)
> Revision        : 0000
> Serial          : 0000000000000000
> 
> The Hardware line does not really describe the hardware type, as it is reading
> the information from the dt 'machine' field.
> 
> In the dt case, read the 'model' field instead, so that we can have a better
> description output as follows:
> 
> Hardware        : Freescale i.MX51 Babbage Board
> 
> The hardware output string is unchanged for the non-dt kernel case.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/include/asm/mach/arch.h |  1 +
>  arch/arm/kernel/devtree.c        | 15 ++++++++-------
>  arch/arm/kernel/setup.c          |  7 ++++++-
>  3 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
> index 308ad7d..113d4af 100644
> --- a/arch/arm/include/asm/mach/arch.h
> +++ b/arch/arm/include/asm/mach/arch.h
> @@ -23,6 +23,7 @@ struct smp_operations;
>  struct machine_desc {
>  	unsigned int		nr;		/* architecture number	*/
>  	const char		*name;		/* architecture name	*/
> +	const char		*model;		/* architectute model */
s/architectute/architecture/

Is it really needed to add a new field here? Alternatively overwrite
name or do something like:

	if (this_is_a_device_tree_machine)
		seq_printf(m, "Hardware\t: %s\n", get_model_from_dt());
	else
		seq_printf(m, "Hardware\t: %s\n", machine_name);
		
Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From j.courtoux at gmail.com  Tue May 28 08:19:21 2013
From: j.courtoux at gmail.com (jo)
Date: Tue, 28 May 2013 14:19:21 +0200
Subject: In driver's A request_threaded_irq, call a driver's B irq_handler_t
 function.
Message-ID: <51A4A0C9.8080300@gmail.com>

In my project i need to call a driver name B when irq is wake up by 
driver A. So driver A is listening on GPIO and in probe 
request_threaded_irq. In this request_threaded_irq i need to call my 
specific function thread_fn which is in the driver A. Is it possible 
because I've try with pointers and other stuff but nothing work. On 
compile I've got error, or on my board driver doesn't work.
Driver work if all part of two driver are in one driver, but i need to 
use a generic driver A to use with driver B and in a near future a driver C.




From daniel.lezcano at linaro.org  Tue May 28 08:23:00 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 28 May 2013 14:23:00 +0200
Subject: [PATCH] cpuidle: improve governor Kconfig options
In-Reply-To: <1578834.dvFIpyCvrt@vostro.rjw.lan>
References: <1369688458-9114-1-git-send-email-daniel.lezcano@linaro.org>
 <1578834.dvFIpyCvrt@vostro.rjw.lan>
Message-ID: <51A4A1A4.1070008@linaro.org>

On 05/28/2013 01:46 PM, Rafael J. Wysocki wrote:
> On Monday, May 27, 2013 11:00:58 PM Daniel Lezcano wrote:
>> Each governor is suitable for different kernel configurations: the menu
>> governor suits better for a tickless system, while the ladder governor fits
>> better for a periodic timer tick system.
>>
>> The Kconfig does not allow to [un]select a governor, thus both are compiled in
>> the kernel but the init order makes the menu governor to be the last one to be
>> registered, so becoming the default. The only way to switch back to the ladder
>> governor is to enable the sysfs governor switch in the kernel command line.
>>
>> Because it seems nobody complained about this, the menu governor is used by
>> default most of the time on the system, having both governors is not really
>> necessary on a tickless system but there isn't a config option to disable one
>> or another governor.
>>
>> Create a submenu for cpuidle and add a label for each governor, so we can see
>> the option in the menu config and enable/disable it.
>>
>> The governors will be enabled depending on the CONFIG_NO_HZ option:
>>  - If CONFIG_NO_HZ is set, then the menu governor is selected and the ladder
>>    governor is optional, defaulting to 'no'
> 
> Why not defaulting to 'yes'?  That'd be backwards compatible, wouldn't it?

Yes, that wouldn't be backward compatible but who wants the ladder
governor which is less efficient with a tickless system ?

>>  - If CONFIG_NO_HZ is not set, then the ladder governor is selected and the
>>    menu governor is optional, defaulting to 'no'
> 
> Are you sure this is not going to introduce regressions with CONFIG_NO_HZ
> unset?

Yes, a system configured with a periodic tick will use the ladder
instead of the menu governor (which is less efficient on this
configuration).

Currently the default is the menu governor with a periodic tick system
because both governors are compiled in and the init order makes the menu
governor to be enabled instead of the 'ladder'.

We can set both to 'yes' by default but in this case, I suggest to add
in the code a 'preferred' governor depending on tickless or not, so the
right governor is chosen at boot time depending on CONFIG_NO_HZ.

Otherwise, I am not sure people running servers (with a periodic tick)
will change their kernel command line option to enable the sysfs
governor switch to change the governor to ladder, neither they are aware
ladder is better for their system.

I am open to any suggestion.

Thanks
  -- Daniel

-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From linux at roeck-us.net  Tue May 28 08:29:40 2013
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 28 May 2013 05:29:40 -0700
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
In-Reply-To: <20130528111921.GD11547@mithrandir>
References: <cover.1369687670.git.arno@natisbad.org>
 <152190814.eApXVbVBPA@wuerfel> <87li6z2yxj.fsf@natisbad.org>
 <20130528111921.GD11547@mithrandir>
Message-ID: <20130528122940.GA29012@roeck-us.net>

On Tue, May 28, 2013 at 01:19:23PM +0200, Thierry Reding wrote:
> On Tue, May 28, 2013 at 12:15:04PM +0200, Arnaud Ebalard wrote:
> > Hi Arnd,
> > 
> > Arnd Bergmann <arnd at arndb.de> writes:
> > 
> > > On Tuesday 28 May 2013 00:02:29 Arnaud Ebalard wrote:
> > >> 
> > >> This series adds support for GMT G762/G763. This work is based on a
> > >> basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
> > >> NAS. Updates have been performed to run on recent kernels. Support has
> > >> been completed and additional features added: ability to configure
> > >> various characteristics from .dts file, better initialization, alarms
> > >> and error reporting support, gear mode, polarity, fan pulse per
> > >> revolution, fan startup voltage control.
> > >
> > > I wonder if this could be split into two separate drivers, one for
> > > the pwm subsystem, and one for a hardware-independent fan controller
> > > based on the pwm interfaces.
> > 
> > To be honest, I wouldn't even know how to start in order to do that.
> > Additionally, it would be worth the effort if other drivers could be
> > easily refactored using this idea. I'll let hwmon people provide some
> > feedback and try and comply with their directions (based on the cpu
> > cycle I can spend on this).
> 
> What Arnd proposes doesn't sounds like a very good idea. PWM-controlled
> fans should be able to work just fine using a generic driver that uses
> the PWM framework, similar to the PWM backlight and LED drivers.
> 
Isn't that exactly what Arnd proposed ?

Guenter


From rjw at sisk.pl  Tue May 28 08:42:55 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Tue, 28 May 2013 14:42:55 +0200
Subject: [PATCH] cpuidle: improve governor Kconfig options
In-Reply-To: <51A4A1A4.1070008@linaro.org>
References: <1369688458-9114-1-git-send-email-daniel.lezcano@linaro.org>
 <1578834.dvFIpyCvrt@vostro.rjw.lan> <51A4A1A4.1070008@linaro.org>
Message-ID: <5938372.bcA6BTeOGP@vostro.rjw.lan>

On Tuesday, May 28, 2013 02:23:00 PM Daniel Lezcano wrote:
> On 05/28/2013 01:46 PM, Rafael J. Wysocki wrote:
> > On Monday, May 27, 2013 11:00:58 PM Daniel Lezcano wrote:
> >> Each governor is suitable for different kernel configurations: the menu
> >> governor suits better for a tickless system, while the ladder governor fits
> >> better for a periodic timer tick system.
> >>
> >> The Kconfig does not allow to [un]select a governor, thus both are compiled in
> >> the kernel but the init order makes the menu governor to be the last one to be
> >> registered, so becoming the default. The only way to switch back to the ladder
> >> governor is to enable the sysfs governor switch in the kernel command line.
> >>
> >> Because it seems nobody complained about this, the menu governor is used by
> >> default most of the time on the system, having both governors is not really
> >> necessary on a tickless system but there isn't a config option to disable one
> >> or another governor.
> >>
> >> Create a submenu for cpuidle and add a label for each governor, so we can see
> >> the option in the menu config and enable/disable it.
> >>
> >> The governors will be enabled depending on the CONFIG_NO_HZ option:
> >>  - If CONFIG_NO_HZ is set, then the menu governor is selected and the ladder
> >>    governor is optional, defaulting to 'no'
> > 
> > Why not defaulting to 'yes'?  That'd be backwards compatible, wouldn't it?
> 
> Yes, that wouldn't be backward compatible but who wants the ladder
> governor which is less efficient with a tickless system ?

I don't know and this isn't the right question to ask I think.

You need to ask who uses the ladder governor with CONFIG_NO_HZ and you need to
avoid making changes that aren't backwards compatible if you don't know the
answer (which I'm pretty sure is the case).

I'd prefer to default to 'yes' to start with and then to change the
default to 'no' after a couple of cycles, possibly.

> >>  - If CONFIG_NO_HZ is not set, then the ladder governor is selected and the
> >>    menu governor is optional, defaulting to 'no'
> > 
> > Are you sure this is not going to introduce regressions with CONFIG_NO_HZ
> > unset?
> 
> Yes, a system configured with a periodic tick will use the ladder
> instead of the menu governor (which is less efficient on this
> configuration).

Well, "less efficient" meaning what exactly?  Less power-efficient or less
efficient performance-wise?

> Currently the default is the menu governor with a periodic tick system
> because both governors are compiled in and the init order makes the menu
> governor to be enabled instead of the 'ladder'.

I understand that.

> We can set both to 'yes' by default but in this case, I suggest to add
> in the code a 'preferred' governor depending on tickless or not, so the
> right governor is chosen at boot time depending on CONFIG_NO_HZ.
> 
> Otherwise, I am not sure people running servers (with a periodic tick)
> will change their kernel command line option to enable the sysfs
> governor switch to change the governor to ladder, neither they are aware
> ladder is better for their system.
> 
> I am open to any suggestion.

I think the change to make the governor preference depend on CONFIG_NO_HZ
kind of makes sense.  However, I'd default to 'yes' for both governors in both
configurations to start with (which basically means that the ordering will now
depend on CONFIG_NO_HZ).

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From festevam at gmail.com  Tue May 28 08:57:20 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 28 May 2013 09:57:20 -0300
Subject: [PATCH] ARM: dt: Use the 'model' field for printing the hardware
 revision
In-Reply-To: <20130528121506.GL11166@pengutronix.de>
References: <1369742670-16305-1-git-send-email-fabio.estevam@freescale.com>
 <20130528121506.GL11166@pengutronix.de>
Message-ID: <CAOMZO5D6dM6+a7mgRy8KgPrSxu0GYXw8VvzqVVQTAVRt+TVb-g@mail.gmail.com>

Hi Uwe,

On Tue, May 28, 2013 at 9:15 AM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:

>>  struct machine_desc {
>>       unsigned int            nr;             /* architecture number  */
>>       const char              *name;          /* architecture name    */
>> +     const char              *model;         /* architectute model */
> s/architectute/architecture/

Thanks for reviewing it. Will fix in v2.

>
> Is it really needed to add a new field here? Alternatively overwrite
> name or do something like:
>
>         if (this_is_a_device_tree_machine)
>                 seq_printf(m, "Hardware\t: %s\n", get_model_from_dt());
>         else
>                 seq_printf(m, "Hardware\t: %s\n", machine_name);

I was not able to find a good trick that provides me the
'this_is_a_device_tree_machine' information inside the c_show()
function, so I ended up adding a the model inside machine_desc struct.

Regards,

Fabio Estevam


From plagnioj at jcrosoft.com  Tue May 28 09:01:49 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 28 May 2013 21:01:49 +0800
Subject: [PATCH] ARM: dt: Use the 'model' field for printing the hardware
 revision
In-Reply-To: <CAOMZO5D6dM6+a7mgRy8KgPrSxu0GYXw8VvzqVVQTAVRt+TVb-g@mail.gmail.com>
References: <1369742670-16305-1-git-send-email-fabio.estevam@freescale.com>
 <20130528121506.GL11166@pengutronix.de>
 <CAOMZO5D6dM6+a7mgRy8KgPrSxu0GYXw8VvzqVVQTAVRt+TVb-g@mail.gmail.com>
Message-ID: <AC44A003-DDC4-4EB6-A67B-97F69426764F@jcrosoft.com>


On May 28, 2013, at 8:57 PM, Fabio Estevam <festevam at gmail.com> wrote:

> Hi Uwe,
> 
> On Tue, May 28, 2013 at 9:15 AM, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
> 
>>> struct machine_desc {
>>>      unsigned int            nr;             /* architecture number  */
>>>      const char              *name;          /* architecture name    */
>>> +     const char              *model;         /* architectute model */
>> s/architectute/architecture/
> 
> Thanks for reviewing it. Will fix in v2.
> 
>> 
>> Is it really needed to add a new field here? Alternatively overwrite
>> name or do something like:
>> 
>>        if (this_is_a_device_tree_machine)
>>                seq_printf(m, "Hardware\t: %s\n", get_model_from_dt());
>>        else
>>                seq_printf(m, "Hardware\t: %s\n", machine_name);

> I was not able to find a good trick that provides me the
> 'this_is_a_device_tree_machine' information inside the c_show()
> function, so I ended up adding a the model inside machine_desc struct.
> 

if the dt is present means this is a dt machine
or the machine_id

Best Regards,
J.

> Regards,
> 
> Fabio Estevam
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From manjunath.goudar at linaro.org  Tue May 28 09:04:48 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue, 28 May 2013 18:34:48 +0530
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>

This series of patches begins the process of splitting ohci-hcd up into
a core library module and independent pci driver modules.

Patch 1/3 prepares the way by exporting a few functions from ohci-hcd
and adding a new mechanism for platform-specific drivers to initialize
their hc_driver structures.  This deserves to be done in the core
because almost all of the entries in these structures are pure
boilerplate -- practically none of the drivers need to override more
than three of the standard core values.

Change from V7 to V8
ohci_hcd_init() is called by ohci_setup() to make generic ohci 
initialization in all ohci drivers.

Patch 2/3 is part of separating the ohci pci host controller
driver from ohci-hcd host code.
Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
and EXPORTed, this is part of the effort to move the ohci pci related
code to generic pci code.

Change from V7 to V8
no change.

Patch 3/3  separate out ohci-pci into independent driver modules.

Change from V7 to V8
USB_OHCI_HCD_PCI symbol no longer dependence on STB03xxx, PPC_MPC52xx and         
USB_OHCI_HCD_PPC_OF that's what removed.

Manjunath Goudar (3):
  USB: OHCI: prepare to make ohci-hcd a library module
  USB: OHCI: Generic changes to make ohci-pci a separate driver
  USB: OHCI: make ohci-pci a separate driver

 drivers/usb/host/Kconfig      |    6 +-
 drivers/usb/host/Makefile     |    3 +
 drivers/usb/host/ohci-hcd.c   |  134 ++++++++++++++++++++++++++----------
 drivers/usb/host/ohci-hub.c   |    1 -
 drivers/usb/host/ohci-pci.c   |  151 ++++++++++++-----------------------------
 drivers/usb/host/ohci-q.c     |    6 +-
 drivers/usb/host/ohci.h       |   17 +++++
 drivers/usb/host/pci-quirks.c |   13 ++++
 drivers/usb/host/pci-quirks.h |    2 +
 9 files changed, 184 insertions(+), 149 deletions(-)

-- 
1.7.9.5



From manjunath.goudar at linaro.org  Tue May 28 09:04:49 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue, 28 May 2013 18:34:49 +0530
Subject: [PATCH V8 1/3] USB: OHCI: prepare to make ohci-hcd a library module
In-Reply-To: <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369746291-21788-2-git-send-email-manjunath.goudar@linaro.org>

This patch prepares ohci-hcd for being split up into a core
library and separate platform driver modules.  A generic
ohci_hc_driver structure is created, containing all the "standard"
values, and a new mechanism is added whereby a driver module can
specify a set of overrides to those values.  In addition the
ohci_restart(),ohci_suspend() and ohci_resume() routines need
to be EXPORTed for use by the drivers.

Added ohci_setip(() and ohci_start() routine for to start the generic
controller rather than each having its own idiosyncratic approach.
This allow to clean duplicated code in most of SOC driver

In V2:
 -ohci_hcd_init() ohci_run() and ohci_stop() are not made non-static.
 -Adds the ohci_setup() and ohci_start() routine.

In V3:
 -purpose of ohci_setup() and ohci_start() function description written in the patch
  description.
 -ohci_init() are not made non-static but now called beginning of the ohci_restart().
 -ohci_run() signature change reverted back.
 -unrelated changes removed.
 -duplicate comment line removed.
 -inline ohci_suspend() and ohci_resume() is not needed so removed from ohci.h file.

In V4:
 -ohci-init() EXPORTed because it is called by all bus glue modules.
 -ohci-setup() removed from 1/2 added into 2/2 patch.

In V5:
 -Again ohci_setup() is added and EXPORTed because to replace the ohci_init() from
  all bus glues.
 -ohci_init() is not made non-static function.

In V6:
  -ohci_init() call is removed from ohci_quirk_nec_worker(), because it is already called in ohci_restart().

In V8:
  -ohci_hcd_init() is called by ohci_setup() to make generic ohci initialization in all ohci drivers.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Acked-by: Alan Stern <stern at rowland.harvard.edu>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci-hcd.c |  105 +++++++++++++++++++++++++++++++++++++++----
 drivers/usb/host/ohci-hub.c |    1 -
 drivers/usb/host/ohci-pci.c |    7 ---
 drivers/usb/host/ohci.h     |   17 +++++++
 4 files changed, 113 insertions(+), 17 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9e6de95..2815359 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -79,13 +79,7 @@ static const char	hcd_name [] = "ohci_hcd";
 #include "pci-quirks.h"
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
-static int ohci_init (struct ohci_hcd *ohci);
 static void ohci_stop (struct usb_hcd *hcd);
-
-#if defined(CONFIG_PM) || defined(CONFIG_PCI)
-static int ohci_restart (struct ohci_hcd *ohci);
-#endif
-
 #ifdef CONFIG_PCI
 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
 #else
@@ -768,6 +762,32 @@ retry:
 	return 0;
 }
 
+/* ohci_setup routine for generic controller initialization */
+
+int ohci_setup(struct usb_hcd *hcd)
+{
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
+
+	ohci_hcd_init(ohci);
+	
+	return ohci_init(ohci);
+}
+EXPORT_SYMBOL_GPL(ohci_setup);
+
+/* ohci_start routine for generic controller start of all OHCI bus glue */
+static int ohci_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
+	int	ret;
+
+	ret = ohci_run(ohci);
+	if (ret < 0) {
+		ohci_err(ohci, "can't start\n");
+		ohci_stop(hcd);
+	}
+	return ret;
+}
+
 /*-------------------------------------------------------------------------*/
 
 /* an interrupt happens */
@@ -949,12 +969,13 @@ static void ohci_stop (struct usb_hcd *hcd)
 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 
 /* must not be called from interrupt context */
-static int ohci_restart (struct ohci_hcd *ohci)
+int ohci_restart(struct ohci_hcd *ohci)
 {
 	int temp;
 	int i;
 	struct urb_priv *priv;
 
+	ohci_init(ohci);
 	spin_lock_irq(&ohci->lock);
 	ohci->rh_state = OHCI_RH_HALTED;
 
@@ -1008,12 +1029,13 @@ static int ohci_restart (struct ohci_hcd *ohci)
 	ohci_dbg(ohci, "restart complete\n");
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_restart);
 
 #endif
 
 #ifdef CONFIG_PM
 
-static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
 	unsigned long	flags;
@@ -1031,9 +1053,10 @@ static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_suspend);
 
 
-static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
+int ohci_resume(struct usb_hcd *hcd, bool hibernated)
 {
 	struct ohci_hcd		*ohci = hcd_to_ohci(hcd);
 	int			port;
@@ -1081,8 +1104,72 @@ static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ohci_resume);
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Generic structure: This gets copied for platform drivers so that
+ * individual entries can be overridden as needed.
+ */
 
+static const struct hc_driver ohci_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "OHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	*/
+	.irq =                  ohci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/*
+	* basic lifecycle operations
+	*/
+	.reset =                ohci_setup,
+	.start =                ohci_start,
+	.stop =                 ohci_stop,
+	.shutdown =             ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	*/
+	.urb_enqueue =          ohci_urb_enqueue,
+	.urb_dequeue =          ohci_urb_dequeue,
+	.endpoint_disable =     ohci_endpoint_disable,
+
+	/*
+	* scheduling support
+	*/
+	.get_frame_number =     ohci_get_frame,
+
+	/*
+	* root hub support
+	*/
+	.hub_status_data =      ohci_hub_status_data,
+	.hub_control =          ohci_hub_control,
+#ifdef CONFIG_PM
+	.bus_suspend =          ohci_bus_suspend,
+	.bus_resume =           ohci_bus_resume,
 #endif
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+void ohci_init_driver(struct hc_driver *drv,
+		const struct ohci_driver_overrides *over)
+{
+	/* Copy the generic table to drv and then apply the overrides */
+	*drv = ohci_hc_driver;
+
+	drv->product_desc = over->product_desc;
+	drv->hcd_priv_size += over->extra_priv_size;
+	if (over->reset)
+		drv->reset = over->reset;
+}
+EXPORT_SYMBOL_GPL(ohci_init_driver);
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index 60ff422..2347ab8 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -176,7 +176,6 @@ __acquires(ohci->lock)
 	if (status == -EBUSY) {
 		if (!autostopped) {
 			spin_unlock_irq (&ohci->lock);
-			(void) ohci_init (ohci);
 			status = ohci_restart (ohci);
 
 			usb_root_hub_lost_power(hcd->self.root_hub);
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 951514e..2c27a5f 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -123,13 +123,6 @@ static void ohci_quirk_nec_worker(struct work_struct *work)
 	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
 	int status;
 
-	status = ohci_init(ohci);
-	if (status != 0) {
-		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
-			 "ohci_init", status);
-		return;
-	}
-
 	status = ohci_restart(ohci);
 	if (status != 0)
 		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index d329914..3b58482 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -718,3 +718,20 @@ static inline u32 roothub_status (struct ohci_hcd *hc)
 	{ return ohci_readl (hc, &hc->regs->roothub.status); }
 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+/* Declarations of things exported for use by ohci platform drivers */
+
+struct ohci_driver_overrides {
+	const char	*product_desc;
+	size_t		extra_priv_size;
+	int		(*reset)(struct usb_hcd *hcd);
+};
+
+extern void	ohci_init_driver(struct hc_driver *drv,
+				const struct ohci_driver_overrides *over);
+extern int	ohci_restart(struct ohci_hcd *ohci);
+extern int	ohci_setup(struct usb_hcd *hcd);
+#ifdef CONFIG_PM
+extern int	ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
+extern int	ohci_resume(struct usb_hcd *hcd, bool hibernated);
+#endif
-- 
1.7.9.5



From will.deacon at arm.com  Tue May 28 09:05:02 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 28 May 2013 14:05:02 +0100
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
Message-ID: <20130528130502.GA28971@mudshark.cambridge.arm.com>

On Tue, May 28, 2013 at 11:48:20AM +0100, Po-Yu Chuang wrote:
> This bug was introduced in commit e651eab0.
> Some v4/v5 platforms failed to boot due to this.
> 
> Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
> ---
>  arch/arm/mm/mmu.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index e0d8565..19a43f8 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
>  			unsigned long end, phys_addr_t phys,
>  			const struct mem_type *type)
>  {
> +	pmd_t *p = pmd;
> +
>  #ifndef CONFIG_ARM_LPAE
>  	/*
>  	 * In classic MMU format, puds and pmds are folded in to
> @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
>  		phys += SECTION_SIZE;
>  	} while (pmd++, addr += SECTION_SIZE, addr != end);
>  
> -	flush_pmd_entry(pmd);
> +	flush_pmd_entry(p);

Wait, shouldn't this flush be *inside* the loop anyway? Otherwise we just
flush the cacheline containing the first pmd. The flushing code could also
flush to PoU instead of PoC for UP ARMv7, but that's an unrelated optimisation.

Will


From manjunath.goudar at linaro.org  Tue May 28 09:04:51 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue, 28 May 2013 18:34:51 +0530
Subject: [PATCH V8 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369746291-21788-4-git-send-email-manjunath.goudar@linaro.org>

This patch splits the PCI portion of ohci-hcd out into its
own separate driver module, called ohci-pci.

The major point of difficulty lies in ohci-pci's many vendor- and
device-specific workarounds.  Some of them have to be applied before
calling ohci_start() some after, which necessitates a fair amount of
code motion.  The other platform drivers require much smaller changes.

The complete sb800_prefetch() function moved to ohci-q.c,because its
only related to ohci-pci driver.

USB_OHCI_HCD_PCI symbol no longer dependence on STB03xxx, PPC_MPC52xx and
USB_OHCI_HCD_PPC_OF that's what removed.

V2:
  - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
    and rest of the generic code is written in ohci_start of ohci-hcd.c file.
V3:
 - ohci_restart() has been called in ohci_pci_reset() function for to reset the ohci pci.

V4:
 -sb800_prefetch() moved to ohci-q.c,because its only related to ohci-pci.
 -no longer _creating_ CONFIG_USB_OHCI_PCI,creating CONFIG_USB_OHCI_HCD_PCI.
 -overrides renamed with pci_override,its giving proper meaning.

V5:
 -sb800_prefetch() moved to pci-quirks.c,because its only related to pci.

V6:
 -sb800_prefetch() function has been moved to pci-quirks.c made as separate patch in 2/3.
 -Most of the generic ohci pci changes moved in 2/3 patch,now this is complete  ohci-pci separation patch.

V7:
 -Unrelated include file has been removed from ohci.h file.

V8:
 -USB_OHCI_HCD_PCI symbol does not dependence on STB03xxx, PPC_MPC52xx and USB_OHCI_HCD_PPC_OF.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig    |    6 +-
 drivers/usb/host/Makefile   |    3 +
 drivers/usb/host/ohci-hcd.c |   20 +------
 drivers/usb/host/ohci-pci.c |  131 +++++++++++++++----------------------------
 4 files changed, 52 insertions(+), 108 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 64d7209..a0a2f3a 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -377,7 +377,7 @@ config USB_FUSBH200_HCD
 	module will be called fusbh200-hcd.
 
 config USB_OHCI_HCD
-	tristate "OHCI HCD support"
+	tristate "OHCI HCD (USB 1.1) support"
 	depends on USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	depends on USB_ISP1301 || !ARCH_LPC32XX
@@ -446,8 +446,8 @@ config USB_OHCI_HCD_PPC_OF
 	default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE
 
 config USB_OHCI_HCD_PCI
-	bool "OHCI support for PCI-bus USB controllers"
-	depends on PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF)
+	tristate "OHCI support for PCI-bus USB controllers"
+	depends on PCI
 	default y
 	select USB_OHCI_LITTLE_ENDIAN
 	---help---
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 661c558..2214ded 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -42,7 +42,10 @@ obj-$(CONFIG_USB_EHCI_TEGRA)    +=ehci-tegra.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
+
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
+obj-$(CONFIG_USB_OHCI_HCD_PCI)	+= ohci-pci.o
+
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci-hcd.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 194ae4a..237be7c 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1168,11 +1168,6 @@ MODULE_AUTHOR (DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE ("GPL");
 
-#ifdef CONFIG_PCI
-#include "ohci-pci.c"
-#define PCI_DRIVER		ohci_pci_driver
-#endif
-
 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
 #include "ohci-sa1111.c"
 #define SA1111_DRIVER		ohci_hcd_sa1111_driver
@@ -1268,7 +1263,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_platform_driver
 #endif
 
-#if	!defined(PCI_DRIVER) &&		\
+#if	!IS_ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
@@ -1343,12 +1338,6 @@ static int __init ohci_hcd_mod_init(void)
 		goto error_sa1111;
 #endif
 
-#ifdef PCI_DRIVER
-	retval = pci_register_driver(&PCI_DRIVER);
-	if (retval < 0)
-		goto error_pci;
-#endif
-
 #ifdef SM501_OHCI_DRIVER
 	retval = platform_driver_register(&SM501_OHCI_DRIVER);
 	if (retval < 0)
@@ -1442,10 +1431,6 @@ static int __init ohci_hcd_mod_init(void)
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
  error_sm501:
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
- error_pci:
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
  error_sa1111:
@@ -1510,9 +1495,6 @@ static void __exit ohci_hcd_mod_exit(void)
 #ifdef SM501_OHCI_DRIVER
 	platform_driver_unregister(&SM501_OHCI_DRIVER);
 #endif
-#ifdef PCI_DRIVER
-	pci_unregister_driver(&PCI_DRIVER);
-#endif
 #ifdef SA1111_DRIVER
 	sa1111_driver_unregister(&SA1111_DRIVER);
 #endif
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index c3fa936..08613e2 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -14,12 +14,19 @@
  * This file is licenced under the GPL.
  */
 
-#ifndef CONFIG_PCI
-#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
-#endif
-
-#include <linux/pci.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+#include "pci-quirks.h"
+
+#define DRIVER_DESC "OHCI PCI platform driver"
+
+static const char hcd_name[] = "ohci-pci";
 
 
 /*-------------------------------------------------------------------------*/
@@ -229,10 +236,10 @@ static const struct pci_device_id ohci_pci_quirks[] = {
 static int ohci_pci_reset (struct usb_hcd *hcd)
 {
 	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
+	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 	int ret = 0;
 
 	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 		const struct pci_device_id *quirk_id;
 
 		quirk_id = pci_match_id(ohci_pci_quirks, pdev);
@@ -242,94 +249,25 @@ static int ohci_pci_reset (struct usb_hcd *hcd)
 			ret = quirk(hcd);
 		}
 	}
-	if (ret == 0) {
-		ohci_hcd_init (ohci);
-		return ohci_init (ohci);
-	}
-	return ret;
-}
-
-
-static int ohci_pci_start (struct usb_hcd *hcd)
-{
-	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
-	int		ret;
-
-#ifdef CONFIG_PM /* avoid warnings about unused pdev */
-	if (hcd->self.controller) {
-		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
-
-		/* RWC may not be set for add-in PCI cards, since boot
-		 * firmware probably ignored them.  This transfers PCI
-		 * PM wakeup capabilities.
-		 */
-		if (device_can_wakeup(&pdev->dev))
-			ohci->hc_control |= OHCI_CTRL_RWC;
-	}
-#endif /* CONFIG_PM */
 
-	ret = ohci_run (ohci);
-	if (ret < 0) {
-		ohci_err (ohci, "can't start\n");
-		ohci_stop (hcd);
-	}
+	if (ret == 0)
+		ret = ohci_setup(hcd);
+	/*
+	* After ohci setup RWC may not be set for add-in PCI cards.
+	* This transfers PCI PM wakeup capabilities.
+	*/
+	if (device_can_wakeup(&pdev->dev))
+		ohci->hc_control |= OHCI_CTRL_RWC;
 	return ret;
 }
 
+static struct hc_driver __read_mostly ohci_pci_hc_driver;
 
-/*-------------------------------------------------------------------------*/
-
-static const struct hc_driver ohci_pci_hc_driver = {
-	.description =		hcd_name,
-	.product_desc =		"OHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			ohci_irq,
-	.flags =		HCD_MEMORY | HCD_USB11,
-
-	/*
-	 * basic lifecycle operations
-	 */
+static const struct ohci_driver_overrides pci_overrides __initconst = {
+	.product_desc =		"OHCI PCI host controller",
 	.reset =		ohci_pci_reset,
-	.start =		ohci_pci_start,
-	.stop =			ohci_stop,
-	.shutdown =		ohci_shutdown,
-
-#ifdef	CONFIG_PM
-	.pci_suspend =		ohci_suspend,
-	.pci_resume =		ohci_resume,
-#endif
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		ohci_urb_enqueue,
-	.urb_dequeue =		ohci_urb_dequeue,
-	.endpoint_disable =	ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data =	ohci_hub_status_data,
-	.hub_control =		ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend =		ohci_bus_suspend,
-	.bus_resume =		ohci_bus_resume,
-#endif
-	.start_port_reset =	ohci_start_port_reset,
 };
 
-/*-------------------------------------------------------------------------*/
-
-
 static const struct pci_device_id pci_ids [] = { {
 	/* handle any USB OHCI controller */
 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
@@ -357,3 +295,24 @@ static struct pci_driver ohci_pci_driver = {
 	},
 #endif
 };
+
+static int __init ohci_pci_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_pci_hc_driver, &pci_overrides);
+	return pci_register_driver(&ohci_pci_driver);
+}
+module_init(ohci_pci_init);
+
+static void __exit ohci_pci_cleanup(void)
+{
+	pci_unregister_driver(&ohci_pci_driver);
+}
+module_exit(ohci_pci_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
-- 
1.7.9.5



From festevam at gmail.com  Tue May 28 09:08:57 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 28 May 2013 10:08:57 -0300
Subject: [PATCH] ARM: dt: Use the 'model' field for printing the hardware
 revision
In-Reply-To: <AC44A003-DDC4-4EB6-A67B-97F69426764F@jcrosoft.com>
References: <1369742670-16305-1-git-send-email-fabio.estevam@freescale.com>
 <20130528121506.GL11166@pengutronix.de>
 <CAOMZO5D6dM6+a7mgRy8KgPrSxu0GYXw8VvzqVVQTAVRt+TVb-g@mail.gmail.com>
 <AC44A003-DDC4-4EB6-A67B-97F69426764F@jcrosoft.com>
Message-ID: <CAOMZO5Cs4dVrTU=01i2L4m9xdpwfT-E_vUvAsWGqzbBezaLB0g@mail.gmail.com>

On Tue, May 28, 2013 at 10:01 AM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> if the dt is present means this is a dt machine
> or the machine_id

Sorry, I cannot understand what you mean here. How does this relate to
the patch?


From manjunath.goudar at linaro.org  Tue May 28 09:04:50 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Tue, 28 May 2013 18:34:50 +0530
Subject: [PATCH V8 2/3] USB: OHCI: Generic changes to make ohci-pci a separate
 driver
In-Reply-To: <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369746291-21788-3-git-send-email-manjunath.goudar@linaro.org>

Note that this changes is part of separating the ohci pci host controller
driver from ohci-hcd host code.
This contains :
     -Moved sb800_prefetch() function from ohci-pci.c to pci-quirks.c file
      and EXPORTed, this is part of the effort to move the ohci pci related
      code to generic pci code.
     -Passed "device" argument instead  of "ohci_hcd" in sb800_prefetch()
      function to avoid extra include file in pci-quirks.c.

V2:
     -Passed "device" argment instead of "pci_dev", then we use to_pci_dev()
      to get the "pci_dev" structure.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Acked-by: Alan Stern <stern at rowland.harvard.edu>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci-hcd.c   |    9 ---------
 drivers/usb/host/ohci-pci.c   |   13 -------------
 drivers/usb/host/ohci-q.c     |    6 ++++--
 drivers/usb/host/pci-quirks.c |   13 +++++++++++++
 drivers/usb/host/pci-quirks.h |    2 ++
 5 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 2815359..194ae4a 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -80,15 +80,6 @@ static const char	hcd_name [] = "ohci_hcd";
 
 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
 static void ohci_stop (struct usb_hcd *hcd);
-#ifdef CONFIG_PCI
-static void sb800_prefetch(struct ohci_hcd *ohci, int on);
-#else
-static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	return;
-}
-#endif
-
 
 #include "ohci-hub.c"
 #include "ohci-dbg.c"
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 2c27a5f..c3fa936 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -168,19 +168,6 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
 	return 0;
 }
 
-static void sb800_prefetch(struct ohci_hcd *ohci, int on)
-{
-	struct pci_dev *pdev;
-	u16 misc;
-
-	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
-	pci_read_config_word(pdev, 0x50, &misc);
-	if (on == 0)
-		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
-	else
-		pci_write_config_word(pdev, 0x50, misc | 0x0300);
-}
-
 /* List of quirks for OHCI */
 static const struct pci_device_id ohci_pci_quirks[] = {
 	{
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 88731b7..df4a670 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -41,6 +41,7 @@ finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
 __releases(ohci->lock)
 __acquires(ohci->lock)
 {
+	 struct device *dev = ohci_to_hcd(ohci)->self.controller;
 	// ASSERT (urb->hcpriv != 0);
 
 	urb_free_priv (ohci, urb->hcpriv);
@@ -55,7 +56,7 @@ __acquires(ohci->lock)
 			if (quirk_amdiso(ohci))
 				usb_amd_quirk_pll_enable();
 			if (quirk_amdprefetch(ohci))
-				sb800_prefetch(ohci, 0);
+				sb800_prefetch(dev, 0);
 		}
 		break;
 	case PIPE_INTERRUPT:
@@ -580,6 +581,7 @@ static void td_submit_urb (
 	struct urb	*urb
 ) {
 	struct urb_priv	*urb_priv = urb->hcpriv;
+	struct device *dev = ohci_to_hcd(ohci)->self.controller;
 	dma_addr_t	data;
 	int		data_len = urb->transfer_buffer_length;
 	int		cnt = 0;
@@ -689,7 +691,7 @@ static void td_submit_urb (
 			if (quirk_amdiso(ohci))
 				usb_amd_quirk_pll_disable();
 			if (quirk_amdprefetch(ohci))
-				sb800_prefetch(ohci, 1);
+				sb800_prefetch(dev, 1);
 		}
 		periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 			&& ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 4c338ec..b9848e4 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -91,6 +91,19 @@ static struct amd_chipset_info {
 
 static DEFINE_SPINLOCK(amd_lock);
 
+void sb800_prefetch(struct device *dev, int on)
+{
+	u16 misc;
+	struct pci_dev *pdev = to_pci_dev(dev);
+
+	pci_read_config_word(pdev, 0x50, &misc);
+	if (on == 0)
+		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
+	else
+		pci_write_config_word(pdev, 0x50, misc | 0x0300);
+}
+EXPORT_SYMBOL_GPL(sb800_prefetch);
+
 int usb_amd_find_chipset_info(void)
 {
 	u8 rev = 0;
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h
index 7f69a39..4b8a209 100644
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -11,11 +11,13 @@ void usb_amd_quirk_pll_enable(void);
 bool usb_is_intel_switchable_xhci(struct pci_dev *pdev);
 void usb_enable_xhci_ports(struct pci_dev *xhci_pdev);
 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
+void sb800_prefetch(struct device *dev, int on);
 #else
 static inline void usb_amd_quirk_pll_disable(void) {}
 static inline void usb_amd_quirk_pll_enable(void) {}
 static inline void usb_amd_dev_put(void) {}
 static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {}
+static inline void sb800_prefetch(struct device *dev, int on) {}
 #endif  /* CONFIG_PCI */
 
 #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
-- 
1.7.9.5



From fabio.estevam at freescale.com  Tue May 28 09:16:29 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Tue, 28 May 2013 10:16:29 -0300
Subject: [PATCH v2] ARM: dt: Use the 'model' field for printing the hardware
 revision
Message-ID: <1369746989-19470-1-git-send-email-fabio.estevam@freescale.com>

When booting a device tree kernel, we get the following output from 
'cat /proc/cpuinfo': 

$ cat /proc/cpuinfo 
processor       : 0
model name      : ARMv7 Processor rev 5 (v7l)
BogoMIPS        : 531.66
Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls 
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x2
CPU part        : 0xc08
CPU revision    : 5

Hardware        : Freescale i.MX51 (Device Tree Support)
Revision        : 0000
Serial          : 0000000000000000

The Hardware line does not really describe the hardware type, as it is reading
the information from the dt 'machine' field.

In the dt case, read the 'model' field instead, so that we can have a better
description output as follows:

Hardware        : Freescale i.MX51 Babbage Board

The hardware output string is unchanged for the non-dt kernel case.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Changes since v1:
- Fix typo in 'architecture'
 arch/arm/include/asm/mach/arch.h |  1 +
 arch/arm/kernel/devtree.c        | 15 ++++++++-------
 arch/arm/kernel/setup.c          |  7 ++++++-
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d..113d4af 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -23,6 +23,7 @@ struct smp_operations;
 struct machine_desc {
 	unsigned int		nr;		/* architecture number	*/
 	const char		*name;		/* architecture name	*/
+	const char		*model;		/* architecture model */
 	unsigned long		atag_offset;	/* tagged list (relative) */
 	const char *const 	*dt_compat;	/* array of device tree
 						 * 'compatible' strings	*/
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..90d541a 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -178,7 +178,6 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
 	struct machine_desc *mdesc, *mdesc_best = NULL;
 	unsigned int score, mdesc_score = ~1;
 	unsigned long dt_root;
-	const char *model;
 
 #ifdef CONFIG_ARCH_MULTIPLATFORM
 	DT_MACHINE_START(GENERIC_DT, "Generic DT based system")
@@ -224,12 +223,14 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
 		dump_machine_table(); /* does not return */
 	}
 
-	model = of_get_flat_dt_prop(dt_root, "model", NULL);
-	if (!model)
-		model = of_get_flat_dt_prop(dt_root, "compatible", NULL);
-	if (!model)
-		model = "<unknown>";
-	pr_info("Machine: %s, model: %s\n", mdesc_best->name, model);
+	mdesc_best->model = of_get_flat_dt_prop(dt_root, "model", NULL);
+	if (!mdesc_best->model)
+		mdesc_best->model = of_get_flat_dt_prop(dt_root, "compatible",
+							NULL);
+	if (!mdesc_best->model)
+		mdesc_best->model = "<unknown>";
+	pr_info("Machine: %s, model: %s\n", mdesc_best->name,
+		mdesc_best->model);
 
 	/* Retrieve various information from the /chosen node */
 	of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 79e8d2f..d22f24b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -137,6 +137,7 @@ EXPORT_SYMBOL(elf_platform);
 
 static const char *cpu_name;
 static const char *machine_name;
+static const char *model_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
 struct machine_desc *machine_desc __initdata;
 
@@ -786,6 +787,7 @@ void __init setup_arch(char **cmdline_p)
 		mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
 	machine_desc = mdesc;
 	machine_name = mdesc->name;
+	model_name = mdesc->model;
 
 	setup_dma_zone(mdesc);
 
@@ -950,7 +952,10 @@ static int c_show(struct seq_file *m, void *v)
 		seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
 	}
 
-	seq_printf(m, "Hardware\t: %s\n", machine_name);
+	if (model_name)
+		seq_printf(m, "Hardware\t: %s\n", model_name);
+	else
+		seq_printf(m, "Hardware\t: %s\n", machine_name);
 	seq_printf(m, "Revision\t: %04x\n", system_rev);
 	seq_printf(m, "Serial\t\t: %08x%08x\n",
 		   system_serial_high, system_serial_low);
-- 
1.8.1.2




From daniel.lezcano at linaro.org  Tue May 28 09:23:37 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 28 May 2013 15:23:37 +0200
Subject: [PATCH] cpuidle: improve governor Kconfig options
In-Reply-To: <5938372.bcA6BTeOGP@vostro.rjw.lan>
References: <1369688458-9114-1-git-send-email-daniel.lezcano@linaro.org>
 <1578834.dvFIpyCvrt@vostro.rjw.lan> <51A4A1A4.1070008@linaro.org>
 <5938372.bcA6BTeOGP@vostro.rjw.lan>
Message-ID: <51A4AFD9.3020109@linaro.org>

On 05/28/2013 02:42 PM, Rafael J. Wysocki wrote:
> On Tuesday, May 28, 2013 02:23:00 PM Daniel Lezcano wrote:
>> On 05/28/2013 01:46 PM, Rafael J. Wysocki wrote:
>>> On Monday, May 27, 2013 11:00:58 PM Daniel Lezcano wrote:
>>>> Each governor is suitable for different kernel configurations: the menu
>>>> governor suits better for a tickless system, while the ladder governor fits
>>>> better for a periodic timer tick system.
>>>>
>>>> The Kconfig does not allow to [un]select a governor, thus both are compiled in
>>>> the kernel but the init order makes the menu governor to be the last one to be
>>>> registered, so becoming the default. The only way to switch back to the ladder
>>>> governor is to enable the sysfs governor switch in the kernel command line.
>>>>
>>>> Because it seems nobody complained about this, the menu governor is used by
>>>> default most of the time on the system, having both governors is not really
>>>> necessary on a tickless system but there isn't a config option to disable one
>>>> or another governor.
>>>>
>>>> Create a submenu for cpuidle and add a label for each governor, so we can see
>>>> the option in the menu config and enable/disable it.
>>>>
>>>> The governors will be enabled depending on the CONFIG_NO_HZ option:
>>>>  - If CONFIG_NO_HZ is set, then the menu governor is selected and the ladder
>>>>    governor is optional, defaulting to 'no'
>>>
>>> Why not defaulting to 'yes'?  That'd be backwards compatible, wouldn't it?
>>
>> Yes, that wouldn't be backward compatible but who wants the ladder
>> governor which is less efficient with a tickless system ?
> 
> I don't know and this isn't the right question to ask I think.
> 
> You need to ask who uses the ladder governor with CONFIG_NO_HZ and you need to
> avoid making changes that aren't backwards compatible if you don't know the
> answer (which I'm pretty sure is the case).
> 
> I'd prefer to default to 'yes' to start with and then to change the
> default to 'no' after a couple of cycles, possibly.
> 
>>>>  - If CONFIG_NO_HZ is not set, then the ladder governor is selected and the
>>>>    menu governor is optional, defaulting to 'no'
>>>
>>> Are you sure this is not going to introduce regressions with CONFIG_NO_HZ
>>> unset?
>>
>> Yes, a system configured with a periodic tick will use the ladder
>> instead of the menu governor (which is less efficient on this
>> configuration).
> 
> Well, "less efficient" meaning what exactly?  Less power-efficient or less
> efficient performance-wise?

less power efficient.

>> Currently the default is the menu governor with a periodic tick system
>> because both governors are compiled in and the init order makes the menu
>> governor to be enabled instead of the 'ladder'.
> 
> I understand that.
> 
>> We can set both to 'yes' by default but in this case, I suggest to add
>> in the code a 'preferred' governor depending on tickless or not, so the
>> right governor is chosen at boot time depending on CONFIG_NO_HZ.
>>
>> Otherwise, I am not sure people running servers (with a periodic tick)
>> will change their kernel command line option to enable the sysfs
>> governor switch to change the governor to ladder, neither they are aware
>> ladder is better for their system.
>>
>> I am open to any suggestion.
> 
> I think the change to make the governor preference depend on CONFIG_NO_HZ
> kind of makes sense.  However, I'd default to 'yes' for both governors in both
> configurations to start with (which basically means that the ordering will now
> depend on CONFIG_NO_HZ).

Ok, no problem. I will respin the patch.

Thanks for the review

  -- Daniel


-- 
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From catalin.marinas at arm.com  Tue May 28 09:43:37 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 28 May 2013 14:43:37 +0100
Subject: [PATCH v8, part3 03/14] mm/ARM64: kill poison_init_mem()
In-Reply-To: <1369575522-26405-4-git-send-email-jiang.liu@huawei.com>
References: <1369575522-26405-1-git-send-email-jiang.liu@huawei.com>
 <1369575522-26405-4-git-send-email-jiang.liu@huawei.com>
Message-ID: <20130528134336.GA15546@arm.com>

On Sun, May 26, 2013 at 02:38:31PM +0100, Jiang Liu wrote:
> Use free_reserved_area() to poison initmem memory pages and kill
> poison_init_mem() on ARM64.
> 
> Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From thierry.reding at gmail.com  Tue May 28 09:47:49 2013
From: thierry.reding at gmail.com (Thierry Reding)
Date: Tue, 28 May 2013 15:47:49 +0200
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
In-Reply-To: <20130528122940.GA29012@roeck-us.net>
References: <cover.1369687670.git.arno@natisbad.org>
 <152190814.eApXVbVBPA@wuerfel> <87li6z2yxj.fsf@natisbad.org>
 <20130528111921.GD11547@mithrandir>
 <20130528122940.GA29012@roeck-us.net>
Message-ID: <20130528134734.GA12585@mithrandir>

On Tue, May 28, 2013 at 05:29:40AM -0700, Guenter Roeck wrote:
> On Tue, May 28, 2013 at 01:19:23PM +0200, Thierry Reding wrote:
> > On Tue, May 28, 2013 at 12:15:04PM +0200, Arnaud Ebalard wrote:
> > > Hi Arnd,
> > > 
> > > Arnd Bergmann <arnd at arndb.de> writes:
> > > 
> > > > On Tuesday 28 May 2013 00:02:29 Arnaud Ebalard wrote:
> > > >> 
> > > >> This series adds support for GMT G762/G763. This work is based on a
> > > >> basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
> > > >> NAS. Updates have been performed to run on recent kernels. Support has
> > > >> been completed and additional features added: ability to configure
> > > >> various characteristics from .dts file, better initialization, alarms
> > > >> and error reporting support, gear mode, polarity, fan pulse per
> > > >> revolution, fan startup voltage control.
> > > >
> > > > I wonder if this could be split into two separate drivers, one for
> > > > the pwm subsystem, and one for a hardware-independent fan controller
> > > > based on the pwm interfaces.
> > > 
> > > To be honest, I wouldn't even know how to start in order to do that.
> > > Additionally, it would be worth the effort if other drivers could be
> > > easily refactored using this idea. I'll let hwmon people provide some
> > > feedback and try and comply with their directions (based on the cpu
> > > cycle I can spend on this).
> > 
> > What Arnd proposes doesn't sounds like a very good idea. PWM-controlled
> > fans should be able to work just fine using a generic driver that uses
> > the PWM framework, similar to the PWM backlight and LED drivers.
> > 
> Isn't that exactly what Arnd proposed ?

Oh, right. I meant to say: "What Arnd proposes sounds like a very good
idea." =) Sorry for the confusion.

Thierry
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From robdclark at gmail.com  Tue May 28 09:48:43 2013
From: robdclark at gmail.com (Rob Clark)
Date: Tue, 28 May 2013 09:48:43 -0400
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
Message-ID: <CAF6AEGv6E38bwszcFV3sV3yMPjD9BkLM4asEscJ8Jt5z+duxTQ@mail.gmail.com>

On Mon, May 27, 2013 at 11:56 PM, Inki Dae <inki.dae at samsung.com> wrote:
>
>
>> -----Original Message-----
>> From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
>> owner at vger.kernel.org] On Behalf Of Rob Clark
>> Sent: Tuesday, May 28, 2013 12:48 AM
>> To: Inki Dae
>> Cc: Maarten Lankhorst; Daniel Vetter; linux-fbdev; YoungJun Cho; Kyungmin
>> Park; myungjoo.ham; DRI mailing list;
> linux-arm-kernel at lists.infradead.org;
>> linux-media at vger.kernel.org
>> Subject: Re: Introduce a new helper framework for buffer synchronization
>>
>> On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
>> > Hi all,
>> >
>> > I have been removed previous branch and added new one with more cleanup.
>> > This time, the fence helper doesn't include user side interfaces and
>> cache
>> > operation relevant codes anymore because not only we are not sure that
>> > coupling those two things, synchronizing caches and buffer access
>> between
>> > CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side is
>> a
>> > good idea yet but also existing codes for user side have problems with
>> badly
>> > behaved or crashing userspace. So this could be more discussed later.
>> >
>> > The below is a new branch,
>> >
>> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
>> exynos.git/?h=dma-f
>> > ence-helper
>> >
>> > And fence helper codes,
>> >
>> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
>> exynos.git/commit/?
>> > h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
>> >
>> > And example codes for device driver,
>> >
>> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
>> exynos.git/commit/?
>> > h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
>> >
>> > I think the time is not yet ripe for RFC posting: maybe existing dma
>> fence
>> > and reservation need more review and addition work. So I'd glad for
>> somebody
>> > giving other opinions and advices in advance before RFC posting.
>>
>> thoughts from a *really* quick, pre-coffee, first look:
>> * any sort of helper to simplify single-buffer sort of use-cases (v4l)
>> probably wouldn't want to bake in assumption that seqno_fence is used.
>> * I guess g2d is probably not actually a simple use case, since I
>> expect you can submit blits involving multiple buffers :-P
>
> I don't think so. One and more buffers can be used: seqno_fence also has
> only one buffer. Actually, we have already applied this approach to most
> devices; multimedia, gpu and display controller. And this approach shows
> more performance; reduced power consumption against traditional way. And g2d
> example is just to show you how to apply my approach to device driver.

no, you need the ww-mutex / reservation stuff any time you have
multiple independent devices (or rings/contexts for hw that can
support multiple contexts) which can do operations with multiple
buffers.  So you could conceivably hit this w/ gpu + g2d if multiple
buffers where shared between the two.  vram migration and such
'desktop stuff' might make the problem worse, but just because you
don't have vram doesn't mean you don't have a problem with multiple
buffers.

>> * otherwise, you probably don't want to depend on dmabuf, which is why
>> reservation/fence is split out the way it is..  you want to be able to
>> use a single reservation/fence mechanism within your driver without
>> having to care about which buffers are exported to dmabuf's and which
>> are not.  Creating a dmabuf for every GEM bo is too heavyweight.
>
> Right. But I think we should dealt with this separately. Actually, we are
> trying to use reservation for gpu pipe line synchronization such as sgx sync
> object and this approach is used without dmabuf. In order words, some device
> can use only reservation for such pipe line synchronization and at the same
> time, fence helper or similar thing with dmabuf for buffer synchronization.

it is probably easier to approach from the reverse direction.. ie, get
reservation/synchronization right first, and then dmabuf.  (Well, that
isn't really a problem because Maarten's reservation/fence patches
support dmabuf from the beginning.)

BR,
-R

>>
>> I'm not entirely sure if reservation/fence could/should be made any
>> simpler for multi-buffer users.  Probably the best thing to do is just
>> get reservation/fence rolled out in a few drivers and see if some
>> common patterns emerge.
>>
>> BR,
>> -R
>>
>> >
>> > Thanks,
>> > Inki Dae
>> >
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From r.sricharan at ti.com  Tue May 28 10:03:36 2013
From: r.sricharan at ti.com (Sricharan R)
Date: Tue, 28 May 2013 19:33:36 +0530
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <20130528130502.GA28971@mudshark.cambridge.arm.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com>
Message-ID: <51A4B938.7080708@ti.com>

On Tuesday 28 May 2013 06:35 PM, Will Deacon wrote:
> On Tue, May 28, 2013 at 11:48:20AM +0100, Po-Yu Chuang wrote:
>> This bug was introduced in commit e651eab0.
>> Some v4/v5 platforms failed to boot due to this.
>>
>> Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
>> ---
>>  arch/arm/mm/mmu.c |    4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>> index e0d8565..19a43f8 100644
>> --- a/arch/arm/mm/mmu.c
>> +++ b/arch/arm/mm/mmu.c
>> @@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
>>  			unsigned long end, phys_addr_t phys,
>>  			const struct mem_type *type)
>>  {
>> +	pmd_t *p = pmd;
>> +
>>  #ifndef CONFIG_ARM_LPAE
>>  	/*
>>  	 * In classic MMU format, puds and pmds are folded in to
>> @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
>>  		phys += SECTION_SIZE;
>>  	} while (pmd++, addr += SECTION_SIZE, addr != end);
>>  
>> -	flush_pmd_entry(pmd);
>> +	flush_pmd_entry(p);
> Wait, shouldn't this flush be *inside* the loop anyway? Otherwise we just
> flush the cacheline containing the first pmd. The flushing code could also
> flush to PoU instead of PoC for UP ARMv7, but that's an unrelated optimisation.
   I think in LPAE this loop iterates once and non LPAE twice.
   So both the entries should be contained in same cache line right ?

Regards,
 Sricharan


From will.deacon at arm.com  Tue May 28 10:07:06 2013
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 28 May 2013 15:07:06 +0100
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <51A4B938.7080708@ti.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com>
 <51A4B938.7080708@ti.com>
Message-ID: <20130528140705.GE28971@mudshark.cambridge.arm.com>

On Tue, May 28, 2013 at 03:03:36PM +0100, Sricharan R wrote:
> On Tuesday 28 May 2013 06:35 PM, Will Deacon wrote:
> > On Tue, May 28, 2013 at 11:48:20AM +0100, Po-Yu Chuang wrote:
> >> This bug was introduced in commit e651eab0.
> >> Some v4/v5 platforms failed to boot due to this.
> >>
> >> Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
> >> ---
> >>  arch/arm/mm/mmu.c |    4 +++-
> >>  1 file changed, 3 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> >> index e0d8565..19a43f8 100644
> >> --- a/arch/arm/mm/mmu.c
> >> +++ b/arch/arm/mm/mmu.c
> >> @@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
> >>  			unsigned long end, phys_addr_t phys,
> >>  			const struct mem_type *type)
> >>  {
> >> +	pmd_t *p = pmd;
> >> +
> >>  #ifndef CONFIG_ARM_LPAE
> >>  	/*
> >>  	 * In classic MMU format, puds and pmds are folded in to
> >> @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
> >>  		phys += SECTION_SIZE;
> >>  	} while (pmd++, addr += SECTION_SIZE, addr != end);
> >>  
> >> -	flush_pmd_entry(pmd);
> >> +	flush_pmd_entry(p);
> > Wait, shouldn't this flush be *inside* the loop anyway? Otherwise we just
> > flush the cacheline containing the first pmd. The flushing code could also
> > flush to PoU instead of PoC for UP ARMv7, but that's an unrelated optimisation.
>    I think in LPAE this loop iterates once and non LPAE twice.
>    So both the entries should be contained in same cache line right ?

Dunno, are there any guarantees about alignment of the starting pmd? Even
so, the function takes the range as parameters, so I don't think we
should tailor it to the caller. It may explain why this hasn't come up
sooner though.

Will


From cdall at cs.columbia.edu  Tue May 28 10:16:14 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Tue, 28 May 2013 07:16:14 -0700
Subject: [PATCH v3 7/7] ARM: KVM: drop use of PAGE_S2_DEVICE
In-Reply-To: <51A482CE.1090509@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>
 <CAEDV+gJeeQUOOLjFpkvoPk7e=csjmvvefhdp1miiWtosABwW6Q@mail.gmail.com>
 <51A482CE.1090509@arm.com>
Message-ID: <CAEDV+gJSM4EpGNV=fN+i6s2K9z6taMzmuNjVf_KyvTUvPaZAwg@mail.gmail.com>

On Tue, May 28, 2013 at 3:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> On 27/05/13 21:01, Christoffer Dall wrote:
>> On Tue, May 14, 2013 at 4:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>>> At the moment, when mapping a device into Stage-2 for a guest,
>>> we override whatever the guest uses by forcing a device memory
>>> type in Stage-2.
>>>
>>> While this is not exactly wrong, this isn't really the "spirit" of
>>> the architecture. The hardware shouldn't have to cope for a broken
>>> guest mapping to a device as normal memory.
>>>
>>
>> So I'm trying to think of a scenario where this feature in the
>> architecture would actually be useful, and it sounds like from you
>> guys that it's only useful to properly run a broken guest.
>>
>> Are we 100% sure that a malicious guest can't leverage this to break
>> isolation? I'm thinking something along the lines of writing to a
>> device (for example the gic virtual cpu interface) with a cached
>> mapping. If such a write is in fact written back to cache, and not
>> evicted from the cache before a later time, where a different VM is
>> running, can't that adversely affect the other VM?
>>
>> Probably this can never happen, but I wasn't able to convince myself
>> of this from going through the ARM ARM...?
>
> I think you definitely have a point here, and I completely missed that
> case. A shared device (like the GIC virtual CPU interface) must be
> forced to a device memory type, otherwise we cannot ensure strict
> isolation of guests.
>
> I'll drop this patch from my series and add PAGE_S2_DEVICE back to the
> arm64 port.
>
We still need to get rid of the USER bit in the definition, and since
that's a purely arch/arm/* patch I assume it should go through RMK's
tree. Will you ack the other patch?

Thanks,
-Christoffer


From linus.walleij at linaro.org  Tue May 28 10:16:57 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 28 May 2013 16:16:57 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <1369738481.3148.9.camel@hornet>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
 <201305271232.03644.arnd@arndb.de> <1369738481.3148.9.camel@hornet>
Message-ID: <CACRpkdaQfaPQdJ1SDN--JDqcrXs8p6=FaDN+4KtKZF6nLtOvvw@mail.gmail.com>

On Tue, May 28, 2013 at 12:54 PM, Pawel Moll <pawel.moll at arm.com> wrote:
> On Mon, 2013-05-27 at 11:32 +0100, Arnd Bergmann wrote:
>> b) add a new KMS driver for this hardware that can be used as an
>> alternative to the existing one and that works with DT.
>
> There are people working on this, just trying to jump through some legal
> hoops to post a RFC. Once this is done we'll be in an interesting
> position of two amba_bus drivers "competing" for the same amba_bus
> device, which I'm not sure how to deal with right now...

Make them mutually exclusive in Kconfig?

Yours,
Linus Walleij


From broonie at kernel.org  Tue May 28 10:19:24 2013
From: broonie at kernel.org (Mark Brown)
Date: Tue, 28 May 2013 10:19:24 -0400
Subject: [PATCH] ARM: dts: wm8994: Add wm8994 regulator support on
 smdk5250.
In-Reply-To: <1369737322-10907-1-git-send-email-padma.v@samsung.com>
References: <1369737322-10907-1-git-send-email-padma.v@samsung.com>
Message-ID: <20130528141924.GH3660@sirena.org.uk>

On Tue, May 28, 2013 at 04:05:22PM +0530, Padmavathi Venna wrote:

> +	avdd2:fixed-regulator at 0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "avdd2-supply";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +		regulator-always-on;
> +	};

> +	cpvdd:fixed-regulator at 1 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "cpvdd-supply";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +		regulator-always-on;
> +	};

Several of these look like the same supply (especially the speaker ones)
so it seems like it'd be sensible to define a single regulator for each
of them.  Not much practical difference but it might be neater.

> +
> +	dbvdd:fixed-regulator at 2 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "dbvdd-supply";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +
> +	spkvdd1:fixed-regulator at 3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "spkvdd1-supply";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-always-on;
> +	};
> +
> +	spkvdd2:fixed-regulator at 4 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "spkvdd2-supply";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-always-on;
> +	};
> +
>  	i2c at 12C70000 {
>  		samsung,i2c-sda-delay = <100>;
>  		samsung,i2c-max-bus-freq = <20000>;
> @@ -47,8 +87,17 @@
>  		};
>  
>  		wm8994: wm8994 at 1a {
> -			 compatible = "wlf,wm8994";
> -			 reg = <0x1a>;
> +			compatible = "wlf,wm8994";
> +			reg = <0x1a>;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			AVDD2-supply = <&avdd2>;
> +			CPVDD-supply = <&cpvdd>;
> +			DBVDD-supply = <&dbvdd>;
> +			SPKVDD1-supply = <&spkvdd1>;
> +			SPKVDD2-supply = <&spkvdd2>;
>  		};
>  	};
>  
> -- 
> 1.7.4.4
> 
> 
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From linus.walleij at linaro.org  Tue May 28 10:20:50 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 28 May 2013 16:20:50 +0200
Subject: [PATCH] ARM: nomadik: Update MMC defconfigs
In-Reply-To: <1369660566-18997-1-git-send-email-ulf.hansson@stericsson.com>
References: <1369660566-18997-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdZ=fX0NLbumOVUDVHPJsYSAFwbT7WNLGhurhPybYnPxGQ@mail.gmail.com>

On Mon, May 27, 2013 at 3:16 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> Enable MMC_UNSAFE_RESUME to accomplish a proper suspend/resume cycle
> for SD/SDIO/(e)MMC.
>
> ARMMMCI host driver supports clock gating through runtime PM, thus
> MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
> means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
> enabled, to skip unnecessary bounce buffer copying.
>
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Patch applied to my Nomadik defconfig branch.

Yours,
Linus Walleij


From pawel.moll at arm.com  Tue May 28 10:21:04 2013
From: pawel.moll at arm.com (Pawel Moll)
Date: Tue, 28 May 2013 15:21:04 +0100
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <CACRpkdaQfaPQdJ1SDN--JDqcrXs8p6=FaDN+4KtKZF6nLtOvvw@mail.gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
 <201305271232.03644.arnd@arndb.de>	<1369738481.3148.9.camel@hornet>
 <CACRpkdaQfaPQdJ1SDN--JDqcrXs8p6=FaDN+4KtKZF6nLtOvvw@mail.gmail.com>
Message-ID: <1369750864.2939.1.camel@hornet>

On Tue, 2013-05-28 at 15:16 +0100, Linus Walleij wrote:
> On Tue, May 28, 2013 at 12:54 PM, Pawel Moll <pawel.moll at arm.com> wrote:
> > On Mon, 2013-05-27 at 11:32 +0100, Arnd Bergmann wrote:
> >> b) add a new KMS driver for this hardware that can be used as an
> >> alternative to the existing one and that works with DT.
> >
> > There are people working on this, just trying to jump through some legal
> > hoops to post a RFC. Once this is done we'll be in an interesting
> > position of two amba_bus drivers "competing" for the same amba_bus
> > device, which I'm not sure how to deal with right now...
> 
> Make them mutually exclusive in Kconfig?

Certainly an option.

I wouldn't mind having both compiled as modules and loading one or the
other, but it wouldn't fly with "=y"...

Pawe?




From marc.zyngier at arm.com  Tue May 28 10:25:11 2013
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 28 May 2013 15:25:11 +0100
Subject: [PATCH v3 7/7] ARM: KVM: drop use of PAGE_S2_DEVICE
In-Reply-To: <CAEDV+gJSM4EpGNV=fN+i6s2K9z6taMzmuNjVf_KyvTUvPaZAwg@mail.gmail.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>
 <CAEDV+gJeeQUOOLjFpkvoPk7e=csjmvvefhdp1miiWtosABwW6Q@mail.gmail.com>
 <51A482CE.1090509@arm.com>
 <CAEDV+gJSM4EpGNV=fN+i6s2K9z6taMzmuNjVf_KyvTUvPaZAwg@mail.gmail.com>
Message-ID: <51A4BE47.7080009@arm.com>

On 28/05/13 15:16, Christoffer Dall wrote:
> On Tue, May 28, 2013 at 3:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> On 27/05/13 21:01, Christoffer Dall wrote:
>>> On Tue, May 14, 2013 at 4:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>>>> At the moment, when mapping a device into Stage-2 for a guest,
>>>> we override whatever the guest uses by forcing a device memory
>>>> type in Stage-2.
>>>>
>>>> While this is not exactly wrong, this isn't really the "spirit" of
>>>> the architecture. The hardware shouldn't have to cope for a broken
>>>> guest mapping to a device as normal memory.
>>>>
>>>
>>> So I'm trying to think of a scenario where this feature in the
>>> architecture would actually be useful, and it sounds like from you
>>> guys that it's only useful to properly run a broken guest.
>>>
>>> Are we 100% sure that a malicious guest can't leverage this to break
>>> isolation? I'm thinking something along the lines of writing to a
>>> device (for example the gic virtual cpu interface) with a cached
>>> mapping. If such a write is in fact written back to cache, and not
>>> evicted from the cache before a later time, where a different VM is
>>> running, can't that adversely affect the other VM?
>>>
>>> Probably this can never happen, but I wasn't able to convince myself
>>> of this from going through the ARM ARM...?
>>
>> I think you definitely have a point here, and I completely missed that
>> case. A shared device (like the GIC virtual CPU interface) must be
>> forced to a device memory type, otherwise we cannot ensure strict
>> isolation of guests.
>>
>> I'll drop this patch from my series and add PAGE_S2_DEVICE back to the
>> arm64 port.
>>
> We still need to get rid of the USER bit in the definition, and since
> that's a purely arch/arm/* patch I assume it should go through RMK's
> tree. Will you ack the other patch?

Sure. Just also drop the call to kvm_set_s2pte_writable in
kvm_phys_addr_ioremap, which is not required now that PAGE_S2_DEVICE
implies RW. With that, you can add my Ack.


	M.
-- 
Jazz is not dead. It just smells funny...



From linus.walleij at linaro.org  Tue May 28 10:25:55 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 28 May 2013 16:25:55 +0200
Subject: [PATCH 3/7] ARM: ux500: Standardise Pinctrl compatible string for
 Nomadik based platforms
In-Reply-To: <1369232581-18923-4-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ8vf0sQuhonTpUoB7vV=UgmY1hiJwhDEphnCxH=MXK1w@mail.gmail.com>

On Wed, May 22, 2013 at 4:22 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-nomadik/cpu-8815.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
> index 59f6ff5..316fe82 100644
> --- a/arch/arm/mach-nomadik/cpu-8815.c
> +++ b/arch/arm/mach-nomadik/cpu-8815.c
> @@ -288,7 +288,7 @@ static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
>                 "gpio.2", NULL),
>         OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
>                 "gpio.3", NULL),
> -       OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
> +       OF_DEV_AUXDATA("stericsson,stn8815-pinctrl", 0,
>                 "pinctrl-stn8815", NULL),
>         OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
>                 "uart0", NULL),

I've dropped this platform data in the HEAD (now also in ARM SoC)
after moving the pinctrl configuration to the DTS, so this no longer
applies.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 28 10:26:29 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 28 May 2013 16:26:29 +0200
Subject: [PATCH 2/7] ARM: ux500: Standardise Nomadik STN8815 based Pinctrl
 compat string in the DTS
In-Reply-To: <1369232581-18923-3-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZESAfnaekrppYm7OFoH6m6V2H7=FbyxmfPtYw5o2p15g@mail.gmail.com>

On Wed, May 22, 2013 at 4:22 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my nomadik-dt branch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue May 28 10:27:37 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 28 May 2013 16:27:37 +0200
Subject: [PATCH 5/7] pinctrl/nomadik: Standardise Pinctrl compat string
 for Nomadik based platforms
In-Reply-To: <1369232581-18923-6-git-send-email-lee.jones@linaro.org>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbuuDkxfw0GytUJ6i5mnX7v5is+-DxvQqUfQze9mtV3ww@mail.gmail.com>

On Wed, May 22, 2013 at 4:22 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my nomadik-dt branch.

Yours,
Linus Walleij


From cdall at cs.columbia.edu  Tue May 28 10:29:44 2013
From: cdall at cs.columbia.edu (Christoffer Dall)
Date: Tue, 28 May 2013 07:29:44 -0700
Subject: [PATCH v3 7/7] ARM: KVM: drop use of PAGE_S2_DEVICE
In-Reply-To: <51A4BE47.7080009@arm.com>
References: <1368529900-22572-1-git-send-email-marc.zyngier@arm.com>
 <1368529900-22572-8-git-send-email-marc.zyngier@arm.com>
 <CAEDV+gJeeQUOOLjFpkvoPk7e=csjmvvefhdp1miiWtosABwW6Q@mail.gmail.com>
 <51A482CE.1090509@arm.com>
 <CAEDV+gJSM4EpGNV=fN+i6s2K9z6taMzmuNjVf_KyvTUvPaZAwg@mail.gmail.com>
 <51A4BE47.7080009@arm.com>
Message-ID: <CAEDV+gJfVRu6zfc7ikd1ngDyhZA5jROg0i6Kj5WZXSVag6_xCA@mail.gmail.com>

cool, thanks.

On Tue, May 28, 2013 at 7:25 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> On 28/05/13 15:16, Christoffer Dall wrote:
>> On Tue, May 28, 2013 at 3:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>>> On 27/05/13 21:01, Christoffer Dall wrote:
>>>> On Tue, May 14, 2013 at 4:11 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>>>>> At the moment, when mapping a device into Stage-2 for a guest,
>>>>> we override whatever the guest uses by forcing a device memory
>>>>> type in Stage-2.
>>>>>
>>>>> While this is not exactly wrong, this isn't really the "spirit" of
>>>>> the architecture. The hardware shouldn't have to cope for a broken
>>>>> guest mapping to a device as normal memory.
>>>>>
>>>>
>>>> So I'm trying to think of a scenario where this feature in the
>>>> architecture would actually be useful, and it sounds like from you
>>>> guys that it's only useful to properly run a broken guest.
>>>>
>>>> Are we 100% sure that a malicious guest can't leverage this to break
>>>> isolation? I'm thinking something along the lines of writing to a
>>>> device (for example the gic virtual cpu interface) with a cached
>>>> mapping. If such a write is in fact written back to cache, and not
>>>> evicted from the cache before a later time, where a different VM is
>>>> running, can't that adversely affect the other VM?
>>>>
>>>> Probably this can never happen, but I wasn't able to convince myself
>>>> of this from going through the ARM ARM...?
>>>
>>> I think you definitely have a point here, and I completely missed that
>>> case. A shared device (like the GIC virtual CPU interface) must be
>>> forced to a device memory type, otherwise we cannot ensure strict
>>> isolation of guests.
>>>
>>> I'll drop this patch from my series and add PAGE_S2_DEVICE back to the
>>> arm64 port.
>>>
>> We still need to get rid of the USER bit in the definition, and since
>> that's a purely arch/arm/* patch I assume it should go through RMK's
>> tree. Will you ack the other patch?
>
> Sure. Just also drop the call to kvm_set_s2pte_writable in
> kvm_phys_addr_ioremap, which is not required now that PAGE_S2_DEVICE
> implies RW. With that, you can add my Ack.
>
>
>         M.
> --
> Jazz is not dead. It just smells funny...
>


From khilman at linaro.org  Tue May 28 10:30:05 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 28 May 2013 07:30:05 -0700
Subject: [PATCH] ARM: OMAP: fix IVA2 module base address
In-Reply-To: <1369741577-21984-1-git-send-email-aida.mynzhasova@skitlab.ru>
 (Aida Mynzhasova's message of "Tue, 28 May 2013 15:46:17 +0400")
References: <1369741577-21984-1-git-send-email-aida.mynzhasova@skitlab.ru>
Message-ID: <87bo7vdvo2.fsf@linaro.org>

Aida Mynzhasova <aida.mynzhasova at skitlab.ru> writes:

> This patch corrects the base address of IVA2 module on omap3430.
>
> Signed-off-by: Aida Mynzhasova <aida.mynzhasova at skitlab.ru>

I know it looks a bit weird to have a negative offset like this, but
it's actually correct.  These offsets are used relative to
prm_base (on 34xx, it's OMAP3430_PRM_BASE defined in omap34xx.h).
So I suggest you double check the values there, and cross reference to
the "PRCM Register Manual" section of the TRM (last section of the PRCM
chapter.)

Thanks,

Kevin

> ---
>  arch/arm/mach-omap2/prcm-common.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
> index c7d355f..d5ec044 100644
> --- a/arch/arm/mach-omap2/prcm-common.h
> +++ b/arch/arm/mach-omap2/prcm-common.h
> @@ -37,7 +37,7 @@
>  #define OMAP2430_MDM_MOD				0xc00
>  
>  /* IVA2 module is < base on 3430 */
> -#define OMAP3430_IVA2_MOD				-0x800
> +#define OMAP3430_IVA2_MOD				0x800
>  #define OMAP3430ES2_SGX_MOD				GFX_MOD
>  #define OMAP3430_CCR_MOD				PLL_MOD
>  #define OMAP3430_DSS_MOD				0x600


From inki.dae at samsung.com  Tue May 28 10:43:50 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 28 May 2013 23:43:50 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <20130528103229.GB15743@phenom.ffwll.local>
References: <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
 <20130528103229.GB15743@phenom.ffwll.local>
Message-ID: <00d801ce5bb1$c48f2ea0$4dad8be0$%dae@samsung.com>


Hi Daniel,

Thank you so much. And so very useful.:) Sorry but could be give me more
comments to the below my comments? There are still things making me
confusing.:(


> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Tuesday, May 28, 2013 7:33 PM
> To: Inki Dae
> Cc: 'Rob Clark'; 'Maarten Lankhorst'; 'Daniel Vetter'; 'linux-fbdev';
> 'YoungJun Cho'; 'Kyungmin Park'; 'myungjoo.ham'; 'DRI mailing list';
> linux-arm-kernel at lists.infradead.org; linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Tue, May 28, 2013 at 12:56:57PM +0900, Inki Dae wrote:
> >
> >
> > > -----Original Message-----
> > > From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
> > > owner at vger.kernel.org] On Behalf Of Rob Clark
> > > Sent: Tuesday, May 28, 2013 12:48 AM
> > > To: Inki Dae
> > > Cc: Maarten Lankhorst; Daniel Vetter; linux-fbdev; YoungJun Cho;
> Kyungmin
> > > Park; myungjoo.ham; DRI mailing list;
> > linux-arm-kernel at lists.infradead.org;
> > > linux-media at vger.kernel.org
> > > Subject: Re: Introduce a new helper framework for buffer
> synchronization
> > >
> > > On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com>
wrote:
> > > > Hi all,
> > > >
> > > > I have been removed previous branch and added new one with more
> cleanup.
> > > > This time, the fence helper doesn't include user side interfaces and
> > > cache
> > > > operation relevant codes anymore because not only we are not sure
> that
> > > > coupling those two things, synchronizing caches and buffer access
> > > between
> > > > CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel
> side is
> > > a
> > > > good idea yet but also existing codes for user side have problems
> with
> > > badly
> > > > behaved or crashing userspace. So this could be more discussed
later.
> > > >
> > > > The below is a new branch,
> > > >
> > > > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> > > exynos.git/?h=dma-f
> > > > ence-helper
> > > >
> > > > And fence helper codes,
> > > >
> > > > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> > > exynos.git/commit/?
> > > > h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
> > > >
> > > > And example codes for device driver,
> > > >
> > > > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> > > exynos.git/commit/?
> > > > h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
> > > >
> > > > I think the time is not yet ripe for RFC posting: maybe existing dma
> > > fence
> > > > and reservation need more review and addition work. So I'd glad for
> > > somebody
> > > > giving other opinions and advices in advance before RFC posting.
> > >
> > > thoughts from a *really* quick, pre-coffee, first look:
> > > * any sort of helper to simplify single-buffer sort of use-cases (v4l)
> > > probably wouldn't want to bake in assumption that seqno_fence is used.
> > > * I guess g2d is probably not actually a simple use case, since I
> > > expect you can submit blits involving multiple buffers :-P
> >
> > I don't think so. One and more buffers can be used: seqno_fence also has
> > only one buffer. Actually, we have already applied this approach to most
> > devices; multimedia, gpu and display controller. And this approach shows
> > more performance; reduced power consumption against traditional way. And
> g2d
> > example is just to show you how to apply my approach to device driver.
> 
> Note that seqno_fence is an implementation pattern for a certain type of
> direct hw->hw synchronization which uses a shared dma_buf to exchange the
> sync cookie.

I'm afraid that I don't understand hw->hw synchronization. hw->hw
synchronization means that device has a hardware feature which supports
buffer synchronization hardware internally? And what is the sync cookie?

> The dma_buf attached to the seqno_fence has _nothing_ to do
> with the dma_buf the fence actually coordinates access to.
> 
> I think that confusing is a large reason for why Maarten&I don't
> understand what you want to achieve with your fence helpers. Currently
> they're using the seqno_fence, but totally not in a way the seqno_fence
> was meant to be used.
> 
> Note that with the current code there is only a pointer from dma_bufs to
> the fence. The fence itself has _no_ pointer to the dma_buf it syncs. This
> shouldn't be a problem since the fence fastpath for already signalled
> fences is completely barrier&lock free (it's just a load+bit-test), and
> fences are meant to be embedded into whatever dma tracking structure you
> already have, so no overhead there. The only ugly part is the fence
> refcounting, but I don't think we can drop that.

The below is the proposed way,
dma device has to create a fence before accessing a shared buffer, and then
check if there are other dma which are accessing the shared buffer; if exist
then the dma device should be blocked, and then  it sets the fence to
reservation object of the shared buffer. And then the dma begins access to
the shared buffer. And finally, the dma signals its own fence so that other
blocked can be waked up. However, if there was another dma blocked before
signaling then another dma can access invalid fence object after waked up
because the fence object can be released after signaling. So I made another
dma takes a one reference before blocked. And I think origin version also
takes a reference at ticket_commit(). Is there wrong point in proposed way?

> 
> Note that you completely reinvent this part of Maarten's fence patches by
> adding new r/w_complete completions to the reservation object, which
> completely replaces the fence stuff.
> 
> Also note that a list of reservation entries is again meant to be used
> only when submitting the dma to the gpu. With your patches you seem to
> hang onto that list until dma completes.

Yeah, that is for prevent a dma from accessing a shared buffer while the
other is accessing the shared buffer. Maybe this way means software
synchronization. And your saying seems that there is another mechanism for
dealing with such thing. Could you give me more comments for it? is there
really another mechanism?

> This has the ugly side-effect
> that you need to allocate these reservation entries with kmalloc, whereas
> if you just use them in the execbuf ioctl to construct the dma you can
> usually embed it into something else you need already anyway. At least
> i915 and ttm based drivers can work that way.
> 

Maybe there is my misunderstanding but I thought now dma fence and relevant
stubs tend to depend on Desktop world, especially x86 gpu. So I thought we
need a little bit customizing the dma fence for embedded system.

> Furthermore fences are specifically constructed as frankenstein-monsters
> between completion/waitqueues and callbacks. All the different use-cases
> need the different aspects:
> - busy/idle checks and bo retiring need the completion semantics
> - callbacks (in interrupt context) are used for hybrid hw->irq handler->hw
>   sync approaches
> 
> >
> > > * otherwise, you probably don't want to depend on dmabuf, which is why
> > > reservation/fence is split out the way it is..  you want to be able to
> > > use a single reservation/fence mechanism within your driver without
> > > having to care about which buffers are exported to dmabuf's and which
> > > are not.  Creating a dmabuf for every GEM bo is too heavyweight.
> >
> > Right. But I think we should dealt with this separately. Actually, we
> are
> > trying to use reservation for gpu pipe line synchronization such as sgx
> sync
> > object and this approach is used without dmabuf. In order words, some
> device
> > can use only reservation for such pipe line synchronization and at the
> same
> > time, fence helper or similar thing with dmabuf for buffer
> synchronization.
> 
> I think a quick overview of the different pieces would be in order.
> 
> - ww_mutex: This is just the locking primite which allows you to grab
>   multiple mutexes without the need to check for ordering (and so fear
>   deadlocks).

Should ww_mutex be necessarily used for embedded system? I'm not sure that
there are any cases we have to use this feature like x86 gpu. That is also
why I removed ticket stubs from existing reservation framework.

> 
> - fence: This is just a fancy kind of completion with a bit of support for
>   hw->hw completion events.

hw->hw completion event means completion of dma operation? Otherwise,
hardware buffer synchronization feature? If the latter, how fence can be
used for embedded system which has no hardware feature for buffer
synchronization? Actually, that made me confusing at initial work.

> The fences themselve have no tie-in with
>   buffers, ww_mutexes or anything else.
> 
> - reservation: This ties together an object (doesn't need to be a buffer,
>   could be any other gpu resource - see the drm/vmwgfx driver if you want
>   your mind blown) with fences. Note that there's no connection the other
>   way round, i.e. with the current patches you can't see which
>   reservations are using which fences. Also note that other objects than
>   reservations could point at fences, e.g. when the provide
>   shared/exclusive semantics are not good enough for your needs.
> 
>   The ww_mutex in the reservation is simply the (fancy) lock which
>   protects each reservation. The reason we need something fancy is that
>   you need to lock all objects which are synced by the same fence
>   toghether, otherwise you can race and construct deadlocks in the hw->hw
>   sync part of fences.
> 
> - dma_buf integration: This is simply a pointer to the reservation object
>   of the underlying buffer object. We need a pointer here since otherwise
>   you can construct deadlocks between dma_buf objects and native buffer
>   objects.
> 
> The crux is also that dma_buf integration comes last - before you can do
> that you need to have your driver converted over to use
> ww_mutexes/fences/reservations.
> 
> I hope that helps to unconfuse things a bit and help you understand the
> different pieces of the fence/reservation/ww_mutex patches floating
> around.

Thank you again.:) 

Thanks,
Inki Dae

> 
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



From linus.walleij at linaro.org  Tue May 28 10:43:54 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 28 May 2013 16:43:54 +0200
Subject: [PATCH] ARM: nomadik: update defconfig base
Message-ID: <1369752234-27653-1-git-send-email-linus.walleij@linaro.org>

Update the Nomadik defconfig enabling:
- GPIO keyboard input
- Regulators
- LED class driver
- LED heartbeat trigger

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/configs/nhk8815_defconfig | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 606a080..e4cb5a4 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -48,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_TESTS=m
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND_ECC_SMC=y
 CONFIG_MTD_NAND=y
@@ -81,6 +80,7 @@ CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -93,10 +93,16 @@ CONFIG_I2C_GPIO=y
 CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
 # CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
-- 
1.8.1.4



From mpa at pengutronix.de  Tue May 28 10:47:48 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:48 +0200
Subject: [PATCH v6 00/10] ASoC: fsl-ssi: ac97-slave support
Message-ID: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>

Hi,

This series adds DT support for phycore-ac97. Beside ac97 support, the series
adds imx-pcm-fiq and generic DMA bindings to fsl-ssi.

Regards,

Markus

Changes in v6:
 - Rebased onto 3.10-rc3 with Shawn's pcm cleanup patches
 - Setup of reset functions moved to phycore-ac97.c

Changes in v5:
 - Pass of_node via parent device to imx-pcm-dma.

Changes in v4:
 - phycore-ac97 uses the iomux functions based on audmux phandle now.
 - fsl-ssi imx-pcm-fiq got some new comments about problems with imx-ssi and
   incompatible codecs

Changes in v3:
 - Rebased onto pcm dma cleanup patches
 - A lot of cleanups for the fsl-ssi ac97 integration
 - Some small changes which are listed in the notes of the patches.

Markus Pargmann (10):
      ASoC: phycore-ac97: Add DT support
      ASoC: imx-pcm-dma: DT support
      ASoC: imx-pcm-fiq: Introduce pcm-fiq-params
      ASoC: fsl-ssi: Add support for imx-pcm-fiq
      ASoC: fsl-ssi: Use generic DMA bindings if possible
      ARM: imx: Export ac97 reset functions
      ASoC: fsl-ssi: imx ac97 support
      ASoC: fsl: Kconfig: Use fsl-ssi for phycore-ac97
      ASoC: fsl: Move fsl-ssi binding doc to sound/
      ASoC: fsl: Update fsl-ssi binding doc

 .../{powerpc/fsl/ssi.txt => sound/fsl,ssi.txt}     |  10 +
 .../bindings/sound/phytec,phycore-ac97.txt         |  14 +
 arch/arm/mach-imx/mach-pca100.c                    |   7 +-
 arch/arm/mach-imx/mach-pcm043.c                    |   7 +-
 sound/soc/fsl/Kconfig                              |   2 +-
 sound/soc/fsl/fsl_ssi.c                            | 441 +++++++++++++++++----
 sound/soc/fsl/fsl_ssi.h                            |   7 +
 sound/soc/fsl/imx-pcm-dma.c                        |   1 -
 sound/soc/fsl/imx-pcm-fiq.c                        |  18 +-
 sound/soc/fsl/imx-pcm.h                            |  12 +-
 sound/soc/fsl/imx-ssi.c                            |   7 +-
 sound/soc/fsl/imx-ssi.h                            |   1 +
 sound/soc/fsl/phycore-ac97.c                       | 241 +++++++++--
 13 files changed, 643 insertions(+), 125 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc/fsl/ssi.txt => sound/fsl,ssi.txt} (88%)
 create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt




From mpa at pengutronix.de  Tue May 28 10:47:58 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:58 +0200
Subject: [PATCH v6 10/10] ASoC: fsl: Update fsl-ssi binding doc
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-11-git-send-email-mpa@pengutronix.de>

Update the fsl-ssi bindings. DMA is no required property anymore and
uses the generic DMA bindings. imx-fiq is a new alternative to DMA

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v4:
     - Add a comment about hardware bugs for imx-pcm-fiq
    
    Changes in v3:
     - In previous versions, I removed fsl,playback-dma and capture-dma. But they
       are still in use by fsl_dma.c, so I added them again.

 Documentation/devicetree/bindings/sound/fsl,ssi.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
index 5ff76c9..0375ee0 100644
--- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
@@ -43,10 +43,20 @@ Required properties:
                     together.  This would still allow different sample sizes,
                     but not different sample rates.
 
+Note that either dmas, dma-names or fsl,imx-fiq are required.
+
 Optional properties:
 - codec-handle:     Phandle to a 'codec' node that defines an audio
                     codec connected to this SSI.  This node is typically
                     a child of an I2C or other control node.
+- dmas:		    Generic dma devicetree binding as described in
+		    Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names:	    Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
+		    is not defined.
+- fsl,imx-fiq:	    Bool property. Use imx-pcm-fiq instead of imx-pcm-dma.
+  		    Only necessary for some boards with incompatible
+		    codec. imx-pcm-fiq will manually filter some data from
+		    the codec. It is a workaround for a hardware bug.
 
 Child 'codec' node required properties:
 - compatible:       Compatible list, contains the name of the codec
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:55 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:55 +0200
Subject: [PATCH v6 07/10] ASoC: fsl-ssi: imx ac97 support
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-8-git-send-email-mpa@pengutronix.de>

This patch copies some parts from imx-ssi to support AC97 on
imx27-pca100 and imx35-pcm043. This is a implementation of the
ac97-slave mode.

For ac97, the registers have to be setup earlier than for other ssi
modes because there is some communication with the external device
before actual streaming. So this patch introduces a fsl_ssi_setup
function to setup the registers at different times.

To seperate board specific ac97 reset functions, ac97 read/write
functions are exported. The reset functions are set by other drivers.

This patch was tested with imx27-pca100.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v6:
     - ac97 reset functions are not provided by fsl-ssi code anymore. They were
       moved to board specific code like phycore-ac97. Therefore ac97 read/write
       functions are exported and a helper function to set the soc_ac97_ops reset
       functions was created.
    
    Changes in v3:
     - Cleanup ac97 code by adding a fsl_ssi_setup function for initial register
       setup. For ac97 the registers have to be setup earlier than in normal
       mode.

 sound/soc/fsl/fsl_ssi.c | 362 ++++++++++++++++++++++++++++++++++++++----------
 sound/soc/fsl/fsl_ssi.h |   7 +
 2 files changed, 297 insertions(+), 72 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index be2a98b..8c58e0e 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -141,6 +141,7 @@ struct fsl_ssi_private {
 
 	bool new_binding;
 	bool ssi_on_imx;
+	bool imx_ac97;
 	bool use_dma;
 	struct clk *clk;
 	struct snd_dmaengine_dai_dma_data dma_params_tx;
@@ -320,6 +321,124 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	return ret;
 }
 
+static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
+{
+	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+	u8 i2s_mode;
+	u8 wm;
+	int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
+
+	if (ssi_private->imx_ac97)
+		i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
+	else
+		i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
+
+	/*
+	 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
+	 * to be disabled before updating the registers we set here.
+	 */
+	write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
+
+	/*
+	 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
+	 * enable the transmit and receive FIFO.
+	 *
+	 * FIXME: Little-endian samples require a different shift dir
+	 */
+	write_ssi_mask(&ssi->scr,
+		CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
+		CCSR_SSI_SCR_TFR_CLK_DIS |
+		i2s_mode |
+		(synchronous ? CCSR_SSI_SCR_SYN : 0));
+
+	write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
+		 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
+
+	write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
+		 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
+	/*
+	 * The DC and PM bits are only used if the SSI is the clock master.
+	 */
+
+	/*
+	 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
+	 * use FIFO 1. We program the transmit water to signal a DMA transfer
+	 * if there are only two (or fewer) elements left in the FIFO. Two
+	 * elements equals one frame (left channel, right channel). This value,
+	 * however, depends on the depth of the transmit buffer.
+	 *
+	 * We set the watermark on the same level as the DMA burstsize.  For
+	 * fiq it is probably better to use the biggest possible watermark
+	 * size.
+	 */
+	if (ssi_private->use_dma)
+		wm = ssi_private->fifo_depth - 2;
+	else
+		wm = ssi_private->fifo_depth;
+
+	write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
+		CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
+		&ssi->sfcsr);
+
+	/*
+	 * For non-ac97 setups, we keep the SSI disabled because if we enable
+	 * it, then the DMA controller will start. It's not supposed to start
+	 * until the SCR.TE (or SCR.RE) bit is set, but it does anyway. The DMA
+	 * controller will transfer one "BWC" of data (i.e. the amount of data
+	 * that the MR.BWC bits are set to). The reason this is bad is because
+	 * at this point, the PCM driver has not finished initializing the DMA
+	 * controller.
+	 */
+
+
+	/*
+	 * For ac97 interrupts are enabled with the startup of the substream
+	 * because it is also running without an active substream. Normally SSI
+	 * is only enabled when there is a substream.
+	 */
+	if (!ssi_private->imx_ac97) {
+		/* Enable the interrupts and DMA requests */
+		if (ssi_private->use_dma)
+			write_ssi(SIER_FLAGS, &ssi->sier);
+		else
+			write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
+					CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
+	} else {
+		/*
+		 * Setup the clock control register
+		 */
+		write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
+				&ssi->stccr);
+		write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
+				&ssi->srccr);
+
+		/*
+		 * Enable AC97 mode and startup the SSI
+		 */
+		write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
+				&ssi->sacnt);
+		write_ssi(0xff, &ssi->saccdis);
+		write_ssi(0x300, &ssi->saccen);
+
+		/*
+		 * Enable SSI
+		 */
+		write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
+		write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
+
+		/*
+		 * Enable Transmit and Receive
+		 */
+		write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
+	}
+
+	return 0;
+}
+
+
 /**
  * fsl_ssi_startup: create a new substream
  *
@@ -341,75 +460,14 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 	 * and initialize the SSI registers.
 	 */
 	if (!ssi_private->first_stream) {
-		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
-
 		ssi_private->first_stream = substream;
 
 		/*
-		 * Section 16.5 of the MPC8610 reference manual says that the
-		 * SSI needs to be disabled before updating the registers we set
-		 * here.
-		 */
-		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
-
-		/*
-		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
-		 * Also enable the transmit and receive FIFO.
-		 *
-		 * FIXME: Little-endian samples require a different shift dir
-		 */
-		write_ssi_mask(&ssi->scr,
-			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
-			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
-			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
-
-		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
-			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
-
-		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
-			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
-
-		/*
-		 * The DC and PM bits are only used if the SSI is the clock
-		 * master.
-		 */
-
-		/* Enable the interrupts and DMA requests */
-		if (ssi_private->use_dma)
-			write_ssi(SIER_FLAGS, &ssi->sier);
-		else
-			write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
-					CCSR_SSI_SIER_RIE |
-					CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
-
-		/*
-		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
-		 * don't use FIFO 1.  We program the transmit water to signal a
-		 * DMA transfer if there are only two (or fewer) elements left
-		 * in the FIFO.  Two elements equals one frame (left channel,
-		 * right channel).  This value, however, depends on the depth of
-		 * the transmit buffer.
-		 *
-		 * We program the receive FIFO to notify us if at least two
-		 * elements (one frame) have been written to the FIFO.  We could
-		 * make this value larger (and maybe we should), but this way
-		 * data will be written to memory as soon as it's available.
-		 */
-		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
-			&ssi->sfcsr);
-
-		/*
-		 * We keep the SSI disabled because if we enable it, then the
-		 * DMA controller will start.  It's not supposed to start until
-		 * the SCR.TE (or SCR.RE) bit is set, but it does anyway.  The
-		 * DMA controller will transfer one "BWC" of data (i.e. the
-		 * amount of data that the MR.BWC bits are set to).  The reason
-		 * this is bad is because at this point, the PCM driver has not
-		 * finished initializing the DMA controller.
+		 * fsl_ssi_setup was already called by ac97_init earlier if
+		 * the driver is in ac97 mode.
 		 */
+		if (!ssi_private->imx_ac97)
+			fsl_ssi_setup(ssi_private);
 	} else {
 		if (synchronous) {
 			struct snd_pcm_runtime *first_runtime =
@@ -564,8 +622,9 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 
 	/*
 	 * If this is the last active substream, disable the SSI.
+	 * If AC97 is active, we don't want to disable SSI.
 	 */
-	if (!ssi_private->first_stream) {
+	if (!ssi_private->first_stream && !ssi_private->imx_ac97) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
 		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
@@ -614,6 +673,147 @@ static const struct snd_soc_component_driver fsl_ssi_component = {
 	.name		= "fsl-ssi",
 };
 
+/**
+ * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
+ *
+ * This function is called by ALSA to start, stop, pause, and resume the
+ * transfer of data.
+ */
+static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
+			   struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
+					CCSR_SSI_SIER_TFE0_EN);
+		else
+			write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
+					CCSR_SSI_SIER_TFE0_EN, 0);
+		else
+			write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN, 0);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
+	else
+		write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
+	.startup	= fsl_ssi_startup,
+	.shutdown	= fsl_ssi_shutdown,
+	.trigger	= fsl_ssi_ac97_trigger,
+};
+
+static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
+	.ac97_control = 1,
+	.playback = {
+		.stream_name = "AC97 Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_8000_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	},
+	.capture = {
+		.stream_name = "AC97 Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	},
+	.ops = &fsl_ssi_ac97_dai_ops,
+};
+
+
+static struct fsl_ssi_private *fsl_ac97_data;
+
+static void fsl_ssi_ac97_init(void)
+{
+	fsl_ssi_setup(fsl_ac97_data);
+}
+
+void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+		unsigned short val)
+{
+	struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
+	unsigned int lreg;
+	unsigned int lval;
+
+	if (reg > 0x7f)
+		return;
+
+
+	lreg = reg <<  12;
+	write_ssi(lreg, &ssi->sacadd);
+
+	lval = val << 4;
+	write_ssi(lval , &ssi->sacdat);
+
+	write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
+			CCSR_SSI_SACNT_WR);
+	udelay(100);
+}
+EXPORT_SYMBOL(fsl_ssi_ac97_write);
+
+unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
+		unsigned short reg)
+{
+	struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
+
+	unsigned short val = -1;
+	unsigned int lreg;
+
+	lreg = (reg & 0x7f) <<  12 ;
+	write_ssi(lreg, &ssi->sacadd);
+	write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
+			CCSR_SSI_SACNT_RD);
+
+	udelay(100);
+
+	val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
+
+	return val;
+}
+EXPORT_SYMBOL(fsl_ssi_ac97_read);
+
+struct snd_ac97_bus_ops soc_ac97_ops = {
+	.read		= fsl_ssi_ac97_read,
+	.write		= fsl_ssi_ac97_write,
+};
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+/*
+ * ac97 reset and warm_reset functions are setup by board specific drivers.
+ * ssi does not have any knowledge about the used board.
+ */
+void fsl_ssi_ac97_set_reset(void (*ac97_reset)(struct snd_ac97 *ac97),
+		void (*ac97_warm_reset)(struct snd_ac97 *ac97))
+{
+	soc_ac97_ops.reset = ac97_reset;
+	soc_ac97_ops.warm_reset = ac97_warm_reset;
+}
+EXPORT_SYMBOL(fsl_ssi_ac97_set_reset);
+
 /* Show the statistics of a flag only if its interrupt is enabled.  The
  * compiler will optimze this code to a no-op if the interrupt is not
  * enabled.
@@ -690,6 +890,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	struct resource res;
 	char name[64];
 	bool shared;
+	bool ac97 = false;
 
 	/* SSIs that are not connected on the board should have a
 	 *      status = "disabled"
@@ -700,7 +901,13 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
-	if (!sprop || strcmp(sprop, "i2s-slave")) {
+	if (!sprop) {
+		dev_err(&pdev->dev, "fsl,mode property is necessary\n");
+		return -EINVAL;
+	}
+	if (!strcmp(sprop, "ac97-slave")) {
+		ac97 = true;
+	} else if (strcmp(sprop, "i2s-slave")) {
 		dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
 		return -ENODEV;
 	}
@@ -716,13 +923,21 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 
 	strcpy(ssi_private->name, p);
 
-	/* Initialize this copy of the CPU DAI driver structure */
-	memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
-	       sizeof(fsl_ssi_dai_template));
-	ssi_private->cpu_dai_drv.name = ssi_private->name;
-
 	ssi_private->use_dma = !of_property_read_bool(np, "fsl,imx-fiq");
 
+	if (ac97) {
+		memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
+				sizeof(fsl_ssi_ac97_dai));
+
+		fsl_ac97_data = ssi_private;
+		ssi_private->imx_ac97 = true;
+	} else {
+		/* Initialize this copy of the CPU DAI driver structure */
+		memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
+		       sizeof(fsl_ssi_dai_template));
+	}
+	ssi_private->cpu_dai_drv.name = ssi_private->name;
+
 	/* Get the addresses and IRQ */
 	ret = of_address_to_resource(np, 0, &res);
 	if (ret) {
@@ -902,6 +1117,9 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 done:
+	if (ssi_private->imx_ac97)
+		fsl_ssi_ac97_init();
+
 	return 0;
 
 error_dai:
diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h
index e6b9a69..87004ae 100644
--- a/sound/soc/fsl/fsl_ssi.h
+++ b/sound/soc/fsl/fsl_ssi.h
@@ -206,3 +206,10 @@ struct ccsr_ssi {
 
 #endif
 
+
+void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+		unsigned short val);
+unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
+		unsigned short reg);
+void fsl_ssi_ac97_set_reset(void (*ac97_reset)(struct snd_ac97 *ac97),
+		void (*ac97_warm_reset)(struct snd_ac97 *ac97));
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:50 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:50 +0200
Subject: [PATCH v6 02/10] ASoC: imx-pcm-dma: DT support
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-3-git-send-email-mpa@pengutronix.de>

This patch removes the NO_DT flag. The pdev pointer may have a proper
of_node with the dmas property, so we can use it to request DMA
channels.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v6:
     - After rebasing onto Shawn's imx-pcm cleanups, this patch just consists of
       removing the NO_DT flag.
    
    Changes in v5:
     - Use dev.parent pointer to get the of_node.

 sound/soc/fsl/imx-pcm-dma.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sound/soc/fsl/imx-pcm-dma.c b/sound/soc/fsl/imx-pcm-dma.c
index fde4d2e..f323ce0 100644
--- a/sound/soc/fsl/imx-pcm-dma.c
+++ b/sound/soc/fsl/imx-pcm-dma.c
@@ -64,7 +64,6 @@ int imx_pcm_dma_init(struct platform_device *pdev)
 {
 	return snd_dmaengine_pcm_register(&pdev->dev, &imx_dmaengine_pcm_config,
 		SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
-		SND_DMAENGINE_PCM_FLAG_NO_DT |
 		SND_DMAENGINE_PCM_FLAG_COMPAT);
 }
 EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:53 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:53 +0200
Subject: [PATCH v6 05/10] ASoC: fsl-ssi: Use generic DMA bindings if possible
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-6-git-send-email-mpa@pengutronix.de>

There may be some platforms using fsl-ssi that do not have a DMA driver
with generic DMA bindings. So this patch adds support for the generic
DMA bindings, while still accepting the old "fsl,dma-events" property if
"dmas" is not found.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v5:
     - Not passing of_node now, instead setting the parent device
    
    Changes in v4:
     - Change TODO comment to a FIXME, to remove the old dma-events property as soon
       as all dma drivers support the generic DMA bindings.

 sound/soc/fsl/fsl_ssi.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index cf20d6d..be2a98b 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -795,15 +795,19 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 			&ssi_private->filter_data_tx;
 		ssi_private->dma_params_rx.filter_data =
 			&ssi_private->filter_data_rx;
-		/*
-		 * TODO: This is a temporary solution and should be changed
-		 * to use generic DMA binding later when the helplers get in.
-		 */
-		ret = of_property_read_u32_array(pdev->dev.of_node,
+		if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
+				ssi_private->use_dma) {
+			/*
+			 * FIXME: This is a temporary solution until all
+			 * necessary dma drivers support the generic dma
+			 * bindings.
+			 */
+			ret = of_property_read_u32_array(pdev->dev.of_node,
 					"fsl,ssi-dma-events", dma_events, 2);
-		if (ret && !ssi_private->use_dma) {
-			dev_err(&pdev->dev, "could not get dma events\n");
-			goto error_clk;
+			if (ret && ssi_private->use_dma) {
+				dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
+				goto error_clk;
+			}
 		}
 
 		shared = of_device_is_compatible(of_get_parent(np),
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:56 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:56 +0200
Subject: [PATCH v6 08/10] ASoC: fsl: Kconfig: Use fsl-ssi for phycore-ac97
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-9-git-send-email-mpa@pengutronix.de>

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 sound/soc/fsl/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 7860cc2..8528466 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -148,7 +148,7 @@ config SND_SOC_PHYCORE_AC97
 	select SND_SOC_WM9712
 	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
+	select SND_SOC_FSL_SSI
 	help
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:51 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:51 +0200
Subject: [PATCH v6 03/10] ASoC: imx-pcm-fiq: Introduce pcm-fiq-params
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-4-git-send-email-mpa@pengutronix.de>

Cleaner parameter passing for imx-pcm-fiq. Create a seperated fiq-params
struct to pass all arguments.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v6:
     - After rebasing onto Shawn's imx-pcm cleanups, the imx_pcm_fiq_params are now
       passed as function arguments instead of platform driver data.
    
    Changes in v3:
     - Using snd_dmaengine_dai_dma_data for dma_params after rebasing onto
       dmaengine cleanups.

 sound/soc/fsl/imx-pcm-fiq.c | 18 ++++++++++--------
 sound/soc/fsl/imx-pcm.h     | 12 +++++++++++-
 sound/soc/fsl/imx-ssi.c     |  7 ++++++-
 sound/soc/fsl/imx-ssi.h     |  1 +
 4 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
index 310d902..3b2ba99 100644
--- a/sound/soc/fsl/imx-pcm-fiq.c
+++ b/sound/soc/fsl/imx-pcm-fiq.c
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 
 #include <sound/core.h>
+#include <sound/dmaengine_pcm.h>
 #include <sound/initval.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -32,6 +33,7 @@
 #include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "imx-ssi.h"
+#include "imx-pcm.h"
 
 struct imx_pcm_runtime_data {
 	unsigned int period;
@@ -366,9 +368,9 @@ static struct snd_soc_platform_driver imx_soc_platform_fiq = {
 	.pcm_free	= imx_pcm_fiq_free,
 };
 
-int imx_pcm_fiq_init(struct platform_device *pdev)
+int imx_pcm_fiq_init(struct platform_device *pdev,
+		struct imx_pcm_fiq_params *params)
 {
-	struct imx_ssi *ssi = platform_get_drvdata(pdev);
 	int ret;
 
 	ret = claim_fiq(&fh);
@@ -377,15 +379,15 @@ int imx_pcm_fiq_init(struct platform_device *pdev)
 		return ret;
 	}
 
-	mxc_set_irq_fiq(ssi->irq, 1);
-	ssi_irq = ssi->irq;
+	mxc_set_irq_fiq(params->irq, 1);
+	ssi_irq = params->irq;
 
-	imx_pcm_fiq = ssi->irq;
+	imx_pcm_fiq = params->irq;
 
-	imx_ssi_fiq_base = (unsigned long)ssi->base;
+	imx_ssi_fiq_base = (unsigned long)params->base;
 
-	ssi->dma_params_tx.maxburst = 4;
-	ssi->dma_params_rx.maxburst = 6;
+	params->dma_params_tx->maxburst = 4;
+	params->dma_params_rx->maxburst = 6;
 
 	ret = snd_soc_register_platform(&pdev->dev, &imx_soc_platform_fiq);
 	if (ret)
diff --git a/sound/soc/fsl/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
index 67f656c..9695ed0 100644
--- a/sound/soc/fsl/imx-pcm.h
+++ b/sound/soc/fsl/imx-pcm.h
@@ -32,6 +32,15 @@ imx_pcm_dma_params_init_data(struct imx_dma_data *dma_data,
 		dma_data->peripheral_type = IMX_DMATYPE_SSI;
 }
 
+struct imx_pcm_fiq_params {
+	int irq;
+	void __iomem *base;
+
+	/* Pointer to original ssi driver to setup tx rx sizes */
+	struct snd_dmaengine_dai_dma_data *dma_params_rx;
+	struct snd_dmaengine_dai_dma_data *dma_params_tx;
+};
+
 #ifdef CONFIG_SND_SOC_IMX_PCM_DMA
 int imx_pcm_dma_init(struct platform_device *pdev);
 void imx_pcm_dma_exit(struct platform_device *pdev);
@@ -47,7 +56,8 @@ static inline void imx_pcm_dma_exit(struct platform_device *pdev)
 #endif
 
 #ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
-int imx_pcm_fiq_init(struct platform_device *pdev);
+int imx_pcm_fiq_init(struct platform_device *pdev,
+		struct imx_pcm_fiq_params *params);
 void imx_pcm_fiq_exit(struct platform_device *pdev);
 #else
 static inline int imx_pcm_fiq_init(struct platform_device *pdev)
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index a8362be..16ae16d 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -590,7 +590,12 @@ static int imx_ssi_probe(struct platform_device *pdev)
 		goto failed_register;
 	}
 
-	ret = imx_pcm_fiq_init(pdev);
+	ssi->fiq_params.irq = ssi->irq;
+	ssi->fiq_params.base = ssi->base;
+	ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
+	ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
+
+	ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
 	if (ret)
 		goto failed_pcm_fiq;
 
diff --git a/sound/soc/fsl/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
index d5003ce..fb1616b 100644
--- a/sound/soc/fsl/imx-ssi.h
+++ b/sound/soc/fsl/imx-ssi.h
@@ -209,6 +209,7 @@ struct imx_ssi {
 	struct snd_dmaengine_dai_dma_data dma_params_tx;
 	struct imx_dma_data filter_data_tx;
 	struct imx_dma_data filter_data_rx;
+	struct imx_pcm_fiq_params fiq_params;
 
 	int enabled;
 };
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:52 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:52 +0200
Subject: [PATCH v6 04/10] ASoC: fsl-ssi: Add support for imx-pcm-fiq
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-5-git-send-email-mpa@pengutronix.de>

Add support for non-dma pcm for imx platforms with imx-pcm-fiq support.
Instead of imx-pcm-audio, in this case imx-pcm-fiq-audio device is added
and the SIER flags are set differently.

We need imx-pcm-fiq for some boards that use an incompatible codec.
imx-pcm-fiq handles those codecs differently and allows to operate with
them. DMA is not possible because some data sent by the codecs, e.g.
wm9712, is not in the datastream. Also some data is mixed up in the
fifos, so that we need to sort them out manually.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v4:
     - Add a comment about the reason why we add a imx-pcm-fiq device.
     - Change commit message to include information about the usage of imx-pcm-fiq
    
    Changes in v3:
     - Rename bool "dma" to "use_dma"

 sound/soc/fsl/fsl_ssi.c | 77 +++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 65 insertions(+), 12 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2f2d837..cf20d6d 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -8,6 +8,26 @@
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
+ *
+ *
+ * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
+ *
+ * The i.MX SSI core has some nasty limitations in AC97 mode. While most
+ * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
+ * one FIFO which combines all valid receive slots. We cannot even select
+ * which slots we want to receive. The WM9712 with which this driver
+ * was developed with always sends GPIO status data in slot 12 which
+ * we receive in our (PCM-) data stream. The only chance we have is to
+ * manually skip this data in the FIQ handler. With sampling rates different
+ * from 48000Hz not every frame has valid receive data, so the ratio
+ * between pcm data and GPIO status data changes. Our FIQ handler is not
+ * able to handle this, hence this driver only works with 48000Hz sampling
+ * rate.
+ * Reading and writing AC97 registers is another challenge. The core
+ * provides us status bits when the read register is updated with *another*
+ * value. When we read the same register two times (and the register still
+ * contains the same value) these status bits are not set. We work
+ * around this by not polling these bits but only wait a fixed delay.
  */
 
 #include <linux/init.h>
@@ -121,11 +141,13 @@ struct fsl_ssi_private {
 
 	bool new_binding;
 	bool ssi_on_imx;
+	bool use_dma;
 	struct clk *clk;
 	struct snd_dmaengine_dai_dma_data dma_params_tx;
 	struct snd_dmaengine_dai_dma_data dma_params_rx;
 	struct imx_dma_data filter_data_tx;
 	struct imx_dma_data filter_data_rx;
+	struct imx_pcm_fiq_params fiq_params;
 
 	struct {
 		unsigned int rfrc;
@@ -355,7 +377,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		write_ssi(SIER_FLAGS, &ssi->sier);
+		if (ssi_private->use_dma)
+			write_ssi(SIER_FLAGS, &ssi->sier);
+		else
+			write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
+					CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -549,7 +576,7 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
 {
 	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
 
-	if (ssi_private->ssi_on_imx) {
+	if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
 		dai->playback_dma_data = &ssi_private->dma_params_tx;
 		dai->capture_dma_data = &ssi_private->dma_params_rx;
 	}
@@ -694,6 +721,8 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	       sizeof(fsl_ssi_dai_template));
 	ssi_private->cpu_dai_drv.name = ssi_private->name;
 
+	ssi_private->use_dma = !of_property_read_bool(np, "fsl,imx-fiq");
+
 	/* Get the addresses and IRQ */
 	ret = of_address_to_resource(np, 0, &res);
 	if (ret) {
@@ -715,12 +744,15 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 		goto error_iomap;
 	}
 
-	/* The 'name' should not have any slashes in it. */
-	ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
-			  ssi_private);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
-		goto error_irqmap;
+	if (ssi_private->use_dma) {
+		/* The 'name' should not have any slashes in it. */
+		ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0,
+				ssi_private->name, ssi_private);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "could not claim irq %u\n",
+					ssi_private->irq);
+			goto error_irqmap;
+		}
 	}
 
 	/* Are the RX and the TX clocks locked? */
@@ -769,7 +801,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 		 */
 		ret = of_property_read_u32_array(pdev->dev.of_node,
 					"fsl,ssi-dma-events", dma_events, 2);
-		if (ret) {
+		if (ret && !ssi_private->use_dma) {
 			dev_err(&pdev->dev, "could not get dma events\n");
 			goto error_clk;
 		}
@@ -808,9 +840,30 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 	if (ssi_private->ssi_on_imx) {
-		ret = imx_pcm_dma_init(pdev);
-		if (ret)
-			goto error_dev;
+		if (!ssi_private->use_dma) {
+
+			/*
+			 * Some boards use an incompatible codec. To get it
+			 * working, we are using imx-fiq-pcm-audio, that
+			 * can handle those codecs. DMA is not possible in this
+			 * situation.
+			 */
+
+			ssi_private->fiq_params.irq = ssi_private->irq;
+			ssi_private->fiq_params.base = ssi_private->ssi;
+			ssi_private->fiq_params.dma_params_rx =
+				&ssi_private->dma_params_rx;
+			ssi_private->fiq_params.dma_params_tx =
+				&ssi_private->dma_params_tx;
+
+			ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
+			if (ret)
+				goto error_dev;
+		} else {
+			ret = imx_pcm_dma_init(pdev);
+			if (ret)
+				goto error_dev;
+		}
 	}
 
 	/*
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:57 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:57 +0200
Subject: [PATCH v6 09/10] ASoC: fsl: Move fsl-ssi binding doc to sound/
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-10-git-send-email-mpa@pengutronix.de>

fsl-ssi was located in powerpc/fsl/ssi.txt. This is no powerpc specific
device, so it should be moved to sound/ as it connects to differen audio
codecs.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 .../devicetree/bindings/powerpc/fsl/ssi.txt        | 73 ----------------------
 .../devicetree/bindings/sound/fsl,ssi.txt          | 73 ++++++++++++++++++++++
 2 files changed, 73 insertions(+), 73 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ssi.txt
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,ssi.txt

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt b/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt
deleted file mode 100644
index 5ff76c9..0000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-Freescale Synchronous Serial Interface
-
-The SSI is a serial device that communicates with audio codecs.  It can
-be programmed in AC97, I2S, left-justified, or right-justified modes.
-
-Required properties:
-- compatible:       Compatible list, contains "fsl,ssi".
-- cell-index:       The SSI, <0> = SSI1, <1> = SSI2, and so on.
-- reg:              Offset and length of the register set for the device.
-- interrupts:       <a b> where a is the interrupt number and b is a
-                    field that represents an encoding of the sense and
-                    level information for the interrupt.  This should be
-                    encoded based on the information in section 2)
-                    depending on the type of interrupt controller you
-                    have.
-- interrupt-parent: The phandle for the interrupt controller that
-                    services interrupts for this device.
-- fsl,mode:         The operating mode for the SSI interface.
-                    "i2s-slave" - I2S mode, SSI is clock slave
-                    "i2s-master" - I2S mode, SSI is clock master
-                    "lj-slave" - left-justified mode, SSI is clock slave
-                    "lj-master" - l.j. mode, SSI is clock master
-                    "rj-slave" - right-justified mode, SSI is clock slave
-                    "rj-master" - r.j., SSI is clock master
-                    "ac97-slave" - AC97 mode, SSI is clock slave
-                    "ac97-master" - AC97 mode, SSI is clock master
-- fsl,playback-dma: Phandle to a node for the DMA channel to use for
-                    playback of audio.  This is typically dictated by SOC
-                    design.  See the notes below.
-- fsl,capture-dma:  Phandle to a node for the DMA channel to use for
-                    capture (recording) of audio.  This is typically dictated
-                    by SOC design.  See the notes below.
-- fsl,fifo-depth:   The number of elements in the transmit and receive FIFOs.
-                    This number is the maximum allowed value for SFCSR[TFWM0].
-- fsl,ssi-asynchronous:
-                    If specified, the SSI is to be programmed in asynchronous
-                    mode.  In this mode, pins SRCK, STCK, SRFS, and STFS must
-                    all be connected to valid signals.  In synchronous mode,
-                    SRCK and SRFS are ignored.  Asynchronous mode allows
-                    playback and capture to use different sample sizes and
-                    sample rates.  Some drivers may require that SRCK and STCK
-                    be connected together, and SRFS and STFS be connected
-                    together.  This would still allow different sample sizes,
-                    but not different sample rates.
-
-Optional properties:
-- codec-handle:     Phandle to a 'codec' node that defines an audio
-                    codec connected to this SSI.  This node is typically
-                    a child of an I2C or other control node.
-
-Child 'codec' node required properties:
-- compatible:       Compatible list, contains the name of the codec
-
-Child 'codec' node optional properties:
-- clock-frequency:  The frequency of the input clock, which typically comes
-                    from an on-board dedicated oscillator.
-
-Notes on fsl,playback-dma and fsl,capture-dma:
-
-On SOCs that have an SSI, specific DMA channels are hard-wired for playback
-and capture.  On the MPC8610, for example, SSI1 must use DMA channel 0 for
-playback and DMA channel 1 for capture.  SSI2 must use DMA channel 2 for
-playback and DMA channel 3 for capture.  The developer can choose which
-DMA controller to use, but the channels themselves are hard-wired.  The
-purpose of these two properties is to represent this hardware design.
-
-The device tree nodes for the DMA channels that are referenced by
-"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
-"fsl,ssi-dma-channel".  The SOC-specific compatible string (e.g.
-"fsl,mpc8610-dma-channel") can remain.  If these nodes are left as
-"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
-drivers (fsldma) will attempt to use them, and it will conflict with the
-sound drivers.
diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
new file mode 100644
index 0000000..5ff76c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
@@ -0,0 +1,73 @@
+Freescale Synchronous Serial Interface
+
+The SSI is a serial device that communicates with audio codecs.  It can
+be programmed in AC97, I2S, left-justified, or right-justified modes.
+
+Required properties:
+- compatible:       Compatible list, contains "fsl,ssi".
+- cell-index:       The SSI, <0> = SSI1, <1> = SSI2, and so on.
+- reg:              Offset and length of the register set for the device.
+- interrupts:       <a b> where a is the interrupt number and b is a
+                    field that represents an encoding of the sense and
+                    level information for the interrupt.  This should be
+                    encoded based on the information in section 2)
+                    depending on the type of interrupt controller you
+                    have.
+- interrupt-parent: The phandle for the interrupt controller that
+                    services interrupts for this device.
+- fsl,mode:         The operating mode for the SSI interface.
+                    "i2s-slave" - I2S mode, SSI is clock slave
+                    "i2s-master" - I2S mode, SSI is clock master
+                    "lj-slave" - left-justified mode, SSI is clock slave
+                    "lj-master" - l.j. mode, SSI is clock master
+                    "rj-slave" - right-justified mode, SSI is clock slave
+                    "rj-master" - r.j., SSI is clock master
+                    "ac97-slave" - AC97 mode, SSI is clock slave
+                    "ac97-master" - AC97 mode, SSI is clock master
+- fsl,playback-dma: Phandle to a node for the DMA channel to use for
+                    playback of audio.  This is typically dictated by SOC
+                    design.  See the notes below.
+- fsl,capture-dma:  Phandle to a node for the DMA channel to use for
+                    capture (recording) of audio.  This is typically dictated
+                    by SOC design.  See the notes below.
+- fsl,fifo-depth:   The number of elements in the transmit and receive FIFOs.
+                    This number is the maximum allowed value for SFCSR[TFWM0].
+- fsl,ssi-asynchronous:
+                    If specified, the SSI is to be programmed in asynchronous
+                    mode.  In this mode, pins SRCK, STCK, SRFS, and STFS must
+                    all be connected to valid signals.  In synchronous mode,
+                    SRCK and SRFS are ignored.  Asynchronous mode allows
+                    playback and capture to use different sample sizes and
+                    sample rates.  Some drivers may require that SRCK and STCK
+                    be connected together, and SRFS and STFS be connected
+                    together.  This would still allow different sample sizes,
+                    but not different sample rates.
+
+Optional properties:
+- codec-handle:     Phandle to a 'codec' node that defines an audio
+                    codec connected to this SSI.  This node is typically
+                    a child of an I2C or other control node.
+
+Child 'codec' node required properties:
+- compatible:       Compatible list, contains the name of the codec
+
+Child 'codec' node optional properties:
+- clock-frequency:  The frequency of the input clock, which typically comes
+                    from an on-board dedicated oscillator.
+
+Notes on fsl,playback-dma and fsl,capture-dma:
+
+On SOCs that have an SSI, specific DMA channels are hard-wired for playback
+and capture.  On the MPC8610, for example, SSI1 must use DMA channel 0 for
+playback and DMA channel 1 for capture.  SSI2 must use DMA channel 2 for
+playback and DMA channel 3 for capture.  The developer can choose which
+DMA controller to use, but the channels themselves are hard-wired.  The
+purpose of these two properties is to represent this hardware design.
+
+The device tree nodes for the DMA channels that are referenced by
+"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
+"fsl,ssi-dma-channel".  The SOC-specific compatible string (e.g.
+"fsl,mpc8610-dma-channel") can remain.  If these nodes are left as
+"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
+drivers (fsldma) will attempt to use them, and it will conflict with the
+sound drivers.
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:49 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:49 +0200
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-2-git-send-email-mpa@pengutronix.de>

Add devicetree support for this audio soc fabric driver.

platform_of_node and cpu_of_node are set according to the fsl,audmux
phandle.

This patch adds handling of ac97 reset functions according to fsl ac97
support. They are setup from here to avoid board specific code in the
generic fsl-ssi driver.

This patch changes the handling of pca100 boards from non-DT to DT only.
pcm043 is still handled without DT.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v6:
     - phycore-ac97 now manages the ac97 reset functions of the boards using
       this combination of ssi-codec.
     - Removed preprocessor ifs for DT, non-DT distinction. pcm043 is now
       non-DT only and pca100 DT only.
    
    Changes in v4:
     - New property phytec,audmux to check which audmux setup should be
       executed. Checking for fsl,imx21-audmux and fsl,imx31-audmux.
    
    Changes in v3:
     - Add some more information in the commit message.
    
    Changes in v2:
     - Simplify the driver, by combining audmux port configurations. The
       audmux driver actually knows on which platform he is running and
       will return the appropriate error code if we use functions for
       another platform. So we don't need to have the knowledge about it
       in phycore-ac97 and can try both functions. This removes the need
       of different compatibilities and renames it to phycore-ac97.
     - Use a phandle for the cpu_dai link.
     - Add devicetree binding documentation.
     - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
    
    Changes in v2:
     - Simplify the driver, by combining audmux port configurations. The
       audmux driver actually knows on which platform he is running and
       will return the appropriate error code if we use functions for
       another platform. So we don't need to have the knowledge about it
       in phycore-ac97 and can try both functions. This removes the need
       of different compatibilities and renames it to imx27-ac97.
     - Use a phandle for the cpu_dai link.
     - Add devicetree binding documentation.
     - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi

 .../bindings/sound/phytec,phycore-ac97.txt         |  14 ++
 sound/soc/fsl/phycore-ac97.c                       | 241 ++++++++++++++++++---
 2 files changed, 229 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt

diff --git a/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
new file mode 100644
index 0000000..41201ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
@@ -0,0 +1,14 @@
+Phytec phycore AC97
+
+Required properties:
+- compatible: "phytec,phycore-ac97"
+- phytec,ssi: A phandle to the ssi device that is connected to ac97.
+- phytec,audmux: A phandle to the audmux device.
+
+Example:
+
+sound {
+	compatible = "phytec,phycore-ac97";
+	phytec,ssi = <&ssi1>;
+	phytec,audmux = <&audmux>;
+};
diff --git a/sound/soc/fsl/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
index ae403c2..bf2c600 100644
--- a/sound/soc/fsl/phycore-ac97.c
+++ b/sound/soc/fsl/phycore-ac97.c
@@ -20,8 +20,14 @@
 #include <asm/mach-types.h>
 
 #include "imx-audmux.h"
+#include "fsl_ssi.h"
+
+#define DRV_NAME "phycore-audio-fabric"
 
 static struct snd_soc_card imx_phycore;
+static struct device_node *phycore_dai_cpu_node;
+static void (*phycore_ac97_reset) (struct snd_ac97 *ac97);
+static void (*phycore_ac97_warm_reset)(struct snd_ac97 *ac97);
 
 static struct snd_soc_ops imx_phycore_hifi_ops = {
 };
@@ -32,12 +38,12 @@ static struct snd_soc_dai_link imx_phycore_dai_ac97[] = {
 		.stream_name	= "HiFi",
 		.codec_dai_name		= "wm9712-hifi",
 		.codec_name	= "wm9712-codec",
-		.cpu_dai_name	= "imx-ssi.0",
-		.platform_name	= "imx-ssi.0",
 		.ops		= &imx_phycore_hifi_ops,
 	},
 };
 
+static const char phycore_ac97_plat_name[] = "imx-ssi.0";
+
 static struct snd_soc_card imx_phycore = {
 	.name		= "PhyCORE-ac97-audio",
 	.owner		= THIS_MODULE,
@@ -45,40 +51,52 @@ static struct snd_soc_card imx_phycore = {
 	.num_links	= ARRAY_SIZE(imx_phycore_dai_ac97),
 };
 
-static struct platform_device *imx_phycore_snd_ac97_device;
+static void phycore_ac97_imx21_audmux(void)
+{
+	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V1_PCR_TFCSEL(3) |
+		IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+		IMX_AUDMUX_V1_PCR_RXDSEL(3));
+	imx_audmux_v1_configure_port(3,
+		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V1_PCR_TFCSEL(0) |
+		IMX_AUDMUX_V1_PCR_TFSDIR |
+		IMX_AUDMUX_V1_PCR_RXDSEL(0));
+}
+
+static void phycore_ac97_imx31_audmux(void)
+{
+	imx_audmux_v2_configure_port(3,
+		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V2_PTCR_TFSEL(0) |
+		IMX_AUDMUX_V2_PTCR_TFSDIR,
+		IMX_AUDMUX_V2_PDCR_RXDSEL(0));
+	imx_audmux_v2_configure_port(0,
+		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V2_PTCR_TCSEL(3) |
+		IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+		IMX_AUDMUX_V2_PDCR_RXDSEL(3));
+}
+
 static struct platform_device *imx_phycore_snd_device;
 
+static struct platform_device *imx_phycore_snd_ac97_device;
+
 static int __init imx_phycore_init(void)
 {
 	int ret;
 
-	if (machine_is_pca100()) {
-		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V1_PCR_TFCSEL(3) |
-			IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-			IMX_AUDMUX_V1_PCR_RXDSEL(3));
-		imx_audmux_v1_configure_port(3,
-			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V1_PCR_TFCSEL(0) |
-			IMX_AUDMUX_V1_PCR_TFSDIR |
-			IMX_AUDMUX_V1_PCR_RXDSEL(0));
-	} else if (machine_is_pcm043()) {
-		imx_audmux_v2_configure_port(3,
-			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V2_PTCR_TFSEL(0) |
-			IMX_AUDMUX_V2_PTCR_TFSDIR,
-			IMX_AUDMUX_V2_PDCR_RXDSEL(0));
-		imx_audmux_v2_configure_port(0,
-			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V2_PTCR_TCSEL(3) |
-			IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-			IMX_AUDMUX_V2_PDCR_RXDSEL(3));
+	if (machine_is_pcm043()) {
+		phycore_ac97_imx31_audmux();
 	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
 	}
 
+	imx_phycore_dai_ac97[0].cpu_dai_name = phycore_ac97_plat_name;
+	imx_phycore_dai_ac97[0].platform_name = phycore_ac97_plat_name;
+
 	imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
 	if (!imx_phycore_snd_ac97_device)
 		return -ENOMEM;
@@ -108,18 +126,189 @@ fail2:
 	platform_device_del(imx_phycore_snd_ac97_device);
 fail1:
 	platform_device_put(imx_phycore_snd_ac97_device);
+	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
+	imx_phycore_dai_ac97[0].platform_name = NULL;
 	return ret;
 }
 
 static void __exit imx_phycore_exit(void)
 {
+	if (!machine_is_pcm043())
+		return;
+
 	platform_device_unregister(imx_phycore_snd_device);
 	platform_device_unregister(imx_phycore_snd_ac97_device);
+
+	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
+	imx_phycore_dai_ac97[0].platform_name = NULL;
 }
 
 late_initcall(imx_phycore_init);
 module_exit(imx_phycore_exit);
 
+
+static const struct of_device_id imx_phycore_ac97_of_dev_id[] = {
+	{
+		.compatible = "phytec,phycore-ac97",
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx_phycore_ac97_of_dev_id);
+
+
+/*
+ * Pointer to AC97 reset functions for specific boards
+ */
+#if IS_ENABLED(CONFIG_MACH_PCA100)
+extern void pca100_ac97_cold_reset(struct snd_ac97 *ac97);
+extern void pca100_ac97_warm_reset(struct snd_ac97 *ac97);
+#else
+void pca100_ac97_cold_reset(struct snd_ac97 *ac97) { }
+void pca100_ac97_warm_reset(struct snd_ac97 *ac97) { }
+#endif
+
+#if IS_ENABLED(CONFIG_MACH_PCM043)
+extern void pcm043_ac97_cold_reset(struct snd_ac97 *ac97);
+extern void pcm043_ac97_warm_reset(struct snd_ac97 *ac97);
+#else
+void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { }
+void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { }
+#endif
+
+static void phycore_soc_ac97_reset(struct snd_ac97 *ac97)
+{
+	if (phycore_ac97_reset)
+		phycore_ac97_reset(ac97);
+	/* First read sometimes fails, do a dummy read */
+	fsl_ssi_ac97_read(ac97, 0);
+}
+
+static void phycore_soc_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+	if (phycore_ac97_warm_reset)
+		phycore_ac97_warm_reset(ac97);
+
+	/* First read sometimes fails, do a dummy read */
+	fsl_ssi_ac97_read(ac97, 0);
+}
+
+static int phycore_ac97_setup_devices(struct platform_device *pdev)
+{
+	int ret;
+
+	imx_phycore_snd_device = platform_device_alloc("wm9712-codec", -1);
+	if (!imx_phycore_snd_device)
+		return -ENOMEM;
+
+	ret = platform_device_add(imx_phycore_snd_device);
+	if (ret) {
+		dev_err(&pdev->dev, "ASoC: Platform device allocation failed\n");
+		goto fail1;
+	}
+
+	ret = snd_soc_register_card(&imx_phycore);
+	if (ret) {
+		dev_err(&pdev->dev, "ASoC: soc card registration failed\n");
+		goto fail2;
+	}
+	return 0;
+
+fail2:
+	platform_device_del(imx_phycore_snd_device);
+fail1:
+	platform_device_put(imx_phycore_snd_device);
+	return ret;
+}
+
+static int imx_phycore_ac97_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct device_node *ssi_np;
+	struct device_node *audmux_np;
+	const char *sprop;
+	const char *p;
+
+	imx_phycore.dev = &pdev->dev;
+
+	audmux_np = of_parse_phandle(pdev->dev.of_node, "phytec,audmux", 0);
+	if (!audmux_np) {
+		dev_err(&pdev->dev, "Failed to parse phytec,audmux phandle\n");
+		return -EINVAL;
+	}
+
+	if (of_device_is_compatible(audmux_np, "fsl,imx21-audmux")) {
+		phycore_ac97_imx21_audmux();
+	} else if (of_device_is_compatible(audmux_np, "fsl,imx31-audmux")) {
+		phycore_ac97_imx31_audmux();
+	} else {
+		dev_err(&pdev->dev, "Unknown audmux, failed to setup audmux\n");
+		of_node_put(audmux_np);
+		return -EINVAL;
+	}
+	of_node_put(audmux_np);
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "phytec,ssi", 0);
+	if (!ssi_np) {
+		dev_err(&pdev->dev, "No valid ssi phandle found\n");
+		return -EINVAL;
+	}
+
+	imx_phycore_dai_ac97[0].cpu_of_node = ssi_np;
+	imx_phycore_dai_ac97[0].platform_of_node = ssi_np;
+	phycore_dai_cpu_node = ssi_np;
+
+	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
+	p = strrchr(sprop, ',');
+	if (p)
+		sprop = p + 1;
+
+	if (!strcmp(sprop, "imx27-pca100")) {
+		phycore_ac97_reset = pca100_ac97_cold_reset;
+		phycore_ac97_warm_reset = pca100_ac97_warm_reset;
+	} else if (!strcmp(sprop, "imx35-pcm043")) {
+		phycore_ac97_reset = pcm043_ac97_cold_reset;
+		phycore_ac97_warm_reset = pcm043_ac97_warm_reset;
+	} else {
+		dev_err(&pdev->dev, "Failed to set AC97 reset functions, unknown board.\n");
+		return -EINVAL;
+	}
+
+	fsl_ssi_ac97_set_reset(phycore_soc_ac97_reset,
+			phycore_soc_ac97_warm_reset);
+
+	ret = phycore_ac97_setup_devices(pdev);
+	if (ret)
+		of_node_put(phycore_dai_cpu_node);
+
+	return ret;
+}
+
+static int imx_phycore_ac97_remove(struct platform_device *pdev)
+{
+	of_node_put(phycore_dai_cpu_node);
+	phycore_dai_cpu_node = NULL;
+
+	platform_device_unregister(imx_phycore_snd_device);
+
+	phycore_ac97_reset = NULL;
+	phycore_ac97_warm_reset = NULL;
+
+	return 0;
+}
+
+static struct platform_driver imx_phycore_ac97_driver = {
+	.probe		= imx_phycore_ac97_probe,
+	.remove		= imx_phycore_ac97_remove,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table = imx_phycore_ac97_of_dev_id,
+	},
+};
+
+module_platform_driver(imx_phycore_ac97_driver);
+
 MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
-MODULE_DESCRIPTION("PhyCORE ALSA SoC driver");
+MODULE_DESCRIPTION(DRV_NAME ": PhyCORE ALSA SoC fabric driver");
 MODULE_LICENSE("GPL");
-- 
1.8.2.1



From mpa at pengutronix.de  Tue May 28 10:47:54 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 16:47:54 +0200
Subject: [PATCH v6 06/10] ARM: imx: Export ac97 reset functions
In-Reply-To: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369752478-30260-7-git-send-email-mpa@pengutronix.de>

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 arch/arm/mach-imx/mach-pca100.c | 7 +++++--
 arch/arm/mach-imx/mach-pcm043.c | 7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb..68badf8 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -22,6 +22,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/dma-mapping.h>
+#include <linux/export.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
 #include <linux/irq.h>
@@ -208,7 +209,7 @@ static const struct spi_imx_master pca100_spi0_data __initconst = {
 	.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
 
-static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
+void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
 {
 	mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
 	gpio_set_value(GPIO_PORTC + 20, 1);
@@ -217,8 +218,9 @@ static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
 	mxc_gpio_mode(PC20_PF_SSI1_FS);
 	msleep(2);
 }
+EXPORT_SYMBOL(pca100_ac97_warm_reset);
 
-static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
+void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
 {
 	mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);  /* FS */
 	gpio_set_value(GPIO_PORTC + 20, 0);
@@ -232,6 +234,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
 	mxc_gpio_mode(PC22_PF_SSI1_TXD);
 	msleep(2);
 }
+EXPORT_SYMBOL(pca100_ac97_cold_reset);
 
 static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
 	.ac97_reset		= pca100_ac97_cold_reset,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 8ed533f..4f318ca 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -27,6 +27,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
+#include <linux/export.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -217,7 +218,7 @@ static iomux_v3_cfg_t pcm043_pads[] = {
 #define SD1_GPIO_WP	IMX_GPIO_NR(2, 23)
 #define SD1_GPIO_CD	IMX_GPIO_NR(2, 24)
 
-static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
+void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 {
 	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
@@ -239,8 +240,9 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 	gpio_free(AC97_GPIO_TXFS);
 	mxc_iomux_v3_setup_pad(txfs);
 }
+EXPORT_SYMBOL(pcm043_ac97_warm_reset);
 
-static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
+void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
 {
 	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
@@ -286,6 +288,7 @@ err1:
 		printk("%s failed with %d\n", __func__, ret);
 	mdelay(1);
 }
+EXPORT_SYMBOL(pcm043_ac97_cold_reset);
 
 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
 	.ac97_reset = pcm043_ac97_cold_reset,
-- 
1.8.2.1



From inki.dae at samsung.com  Tue May 28 10:50:16 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Tue, 28 May 2013 23:50:16 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAF6AEGv6E38bwszcFV3sV3yMPjD9BkLM4asEscJ8Jt5z+duxTQ@mail.gmail.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
 <"CAF6AEGv6E38bwszcFV3sV3yMPjD9BkLM4 asEscJ8Jt5z+duxTQ"@mail.gmail.com>
Message-ID: <00de01ce5bb2$aa7c6b30$ff754190$%dae@samsung.com>



> -----Original Message-----
> From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
> owner at vger.kernel.org] On Behalf Of Rob Clark
> Sent: Tuesday, May 28, 2013 10:49 PM
> To: Inki Dae
> Cc: Maarten Lankhorst; Daniel Vetter; linux-fbdev; YoungJun Cho; Kyungmin
> Park; myungjoo.ham; DRI mailing list;
linux-arm-kernel at lists.infradead.org;
> linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Mon, May 27, 2013 at 11:56 PM, Inki Dae <inki.dae at samsung.com> wrote:
> >
> >
> >> -----Original Message-----
> >> From: linux-fbdev-owner at vger.kernel.org [mailto:linux-fbdev-
> >> owner at vger.kernel.org] On Behalf Of Rob Clark
> >> Sent: Tuesday, May 28, 2013 12:48 AM
> >> To: Inki Dae
> >> Cc: Maarten Lankhorst; Daniel Vetter; linux-fbdev; YoungJun Cho;
> Kyungmin
> >> Park; myungjoo.ham; DRI mailing list;
> > linux-arm-kernel at lists.infradead.org;
> >> linux-media at vger.kernel.org
> >> Subject: Re: Introduce a new helper framework for buffer
> synchronization
> >>
> >> On Mon, May 27, 2013 at 6:38 AM, Inki Dae <inki.dae at samsung.com> wrote:
> >> > Hi all,
> >> >
> >> > I have been removed previous branch and added new one with more
> cleanup.
> >> > This time, the fence helper doesn't include user side interfaces and
> >> cache
> >> > operation relevant codes anymore because not only we are not sure
> that
> >> > coupling those two things, synchronizing caches and buffer access
> >> between
> >> > CPU and CPU, CPU and DMA, and DMA and DMA with fences, in kernel side
> is
> >> a
> >> > good idea yet but also existing codes for user side have problems
> with
> >> badly
> >> > behaved or crashing userspace. So this could be more discussed later.
> >> >
> >> > The below is a new branch,
> >> >
> >> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> >> exynos.git/?h=dma-f
> >> > ence-helper
> >> >
> >> > And fence helper codes,
> >> >
> >> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> >> exynos.git/commit/?
> >> > h=dma-fence-helper&id=adcbc0fe7e285ce866e5816e5e21443dcce01005
> >> >
> >> > And example codes for device driver,
> >> >
> >> > https://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-
> >> exynos.git/commit/?
> >> > h=dma-fence-helper&id=d2ce7af23835789602a99d0ccef1f53cdd5caaae
> >> >
> >> > I think the time is not yet ripe for RFC posting: maybe existing dma
> >> fence
> >> > and reservation need more review and addition work. So I'd glad for
> >> somebody
> >> > giving other opinions and advices in advance before RFC posting.
> >>
> >> thoughts from a *really* quick, pre-coffee, first look:
> >> * any sort of helper to simplify single-buffer sort of use-cases (v4l)
> >> probably wouldn't want to bake in assumption that seqno_fence is used.
> >> * I guess g2d is probably not actually a simple use case, since I
> >> expect you can submit blits involving multiple buffers :-P
> >
> > I don't think so. One and more buffers can be used: seqno_fence also has
> > only one buffer. Actually, we have already applied this approach to most
> > devices; multimedia, gpu and display controller. And this approach shows
> > more performance; reduced power consumption against traditional way. And
> g2d
> > example is just to show you how to apply my approach to device driver.
> 
> no, you need the ww-mutex / reservation stuff any time you have
> multiple independent devices (or rings/contexts for hw that can
> support multiple contexts) which can do operations with multiple
> buffers.

I think I already used reservation stuff any time in that way except
ww-mutex. And I'm not sure that embedded system really needs ww-mutex. If
there is any case, 
could you tell me the case? I really need more advice and understanding :)

Thanks,
Inki Dae

  So you could conceivably hit this w/ gpu + g2d if multiple
> buffers where shared between the two.  vram migration and such
> 'desktop stuff' might make the problem worse, but just because you
> don't have vram doesn't mean you don't have a problem with multiple
> buffers.
> 
> >> * otherwise, you probably don't want to depend on dmabuf, which is why
> >> reservation/fence is split out the way it is..  you want to be able to
> >> use a single reservation/fence mechanism within your driver without
> >> having to care about which buffers are exported to dmabuf's and which
> >> are not.  Creating a dmabuf for every GEM bo is too heavyweight.
> >
> > Right. But I think we should dealt with this separately. Actually, we
> are
> > trying to use reservation for gpu pipe line synchronization such as sgx
> sync
> > object and this approach is used without dmabuf. In order words, some
> device
> > can use only reservation for such pipe line synchronization and at the
> same
> > time, fence helper or similar thing with dmabuf for buffer
> synchronization.
> 
> it is probably easier to approach from the reverse direction.. ie, get
> reservation/synchronization right first, and then dmabuf.  (Well, that
> isn't really a problem because Maarten's reservation/fence patches
> support dmabuf from the beginning.)
> 
> BR,
> -R
> 
> >>
> >> I'm not entirely sure if reservation/fence could/should be made any
> >> simpler for multi-buffer users.  Probably the best thing to do is just
> >> get reservation/fence rolled out in a few drivers and see if some
> >> common patterns emerge.
> >>
> >> BR,
> >> -R
> >>
> >> >
> >> > Thanks,
> >> > Inki Dae
> >> >
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe linux-fbdev"
> in
> >> the body of a message to majordomo at vger.kernel.org
> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From arnd at arndb.de  Tue May 28 10:52:55 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 16:52:55 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <1369750864.2939.1.camel@hornet>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <CACRpkdaQfaPQdJ1SDN--JDqcrXs8p6=FaDN+4KtKZF6nLtOvvw@mail.gmail.com>
 <1369750864.2939.1.camel@hornet>
Message-ID: <3950519.8yj1SQodNQ@wuerfel>

On Tuesday 28 May 2013 15:21:04 Pawel Moll wrote:
> On Tue, 2013-05-28 at 15:16 +0100, Linus Walleij wrote:
> > On Tue, May 28, 2013 at 12:54 PM, Pawel Moll <pawel.moll at arm.com> wrote:
> > > On Mon, 2013-05-27 at 11:32 +0100, Arnd Bergmann wrote:
> > >> b) add a new KMS driver for this hardware that can be used as an
> > >> alternative to the existing one and that works with DT.
> > >
> > > There are people working on this, just trying to jump through some legal
> > > hoops to post a RFC. Once this is done we'll be in an interesting
> > > position of two amba_bus drivers "competing" for the same amba_bus
> > > device, which I'm not sure how to deal with right now...
> > 
> > Make them mutually exclusive in Kconfig?
> 
> Certainly an option.
> 
> I wouldn't mind having both compiled as modules and loading one or the
> other, but it wouldn't fly with "=y"...

It's a bit ugly but I think you can express that in Kconfig like this:

config FB_ARMCLCD
        tristate "ARM PrimeCell PL110 support"
        depends on FB && ARM && ARM_AMBA
	depends on KMS_ARMCLCD != 'y'
	depends on 'm' if KMS_ARMCLCD

	Arnd


From arnd at arndb.de  Tue May 28 10:49:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 16:49:20 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <20130528081910.GA29557@gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
 <20130528081910.GA29557@gmail.com>
Message-ID: <2827337.zlCzuksfVM@wuerfel>

On Tuesday 28 May 2013 10:19:10 Ingo Molnar wrote:
> 
> * Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> 
> > So, if you want to use this, then you should update the CONFIG_BUG text 
> > to include a warning to this effect:
> > 
> >      Warning: if CONFIG_BUG is turned off, and control flow reaches
> >      a BUG(), the system behaviour will be undefined.
> > 
> > so that people can make an informed choice about this, because at the
> > moment:
> > 
> >           Disabling this option eliminates support for BUG and WARN, reducing
> >           the size of your kernel image and potentially quietly ignoring
> >           numerous fatal conditions. You should only consider disabling this
> >           option for embedded systems with no facilities for reporting errors.
> >           Just say Y.
> > 
> > will become completely misleading.  Turning this option off will _not_ 
> > result in "quietly ignoring numerous fatal conditions".
> 
> I'm fine with adding your text as a clarification - but I think 'quietly 
> ignoring fatal conditions' very much implies an undefined outcome if that 
> unexpected condition does occur: the code might crash, it might corrupt 
> memory or it might do some other unexpected thing.
> 
> There are many other places that do a BUG_ON() of a NULL pointer or so, or 
> of a zero refcount, or a not held lock - and turning the BUG_ON() off 
> makes the code unpredictable _anyway_ - even if the compiler does not 
> notice an uninitialized variable.
> 
> So pretty much any weakening of BUG_ON() _will_ make the kernel more 
> unpredictable.

FWIW, I've run some size analyis using the ARM 'multi_v7_defconfig'
and gcc-4.8, using various definitions for BUG() and BUG_ON(), to
see how big the size improvement actually gets

1. Baseline: normal bug plus CONFIG_BUG_VERBOSE
   text    data     bss     dec     hex filename
3743196  224396  206812 4174404  3fb244 vmlinux-bugverbose

2. disabling CONFIG_BUG_VERBOSE, saving 0.6%
3716920  224380  206812 4148112  3f4b90 vmlinux-nobugverbose

3. #define BUG() panic(__func__), #define BUG_ON(c) if(c) BUG(), saving 1.0%
3701076  224384  206812 4132272  3f0db0 vmlinux-bug-panicfunc

3. #define BUG() panic(__func__), #define BUG_ON(c) if(c) BUG(), saving 1.5%
3678884  224400  206812 4110096  3eb710 vmlinux-bug-panic

4. #define BUG() unreachable(), saving 2.1%
3652636  224384  206812 4083832  3e5078 vmlinux-bug-unreachable

5. as 4, plus #define BUG_ON(c) if(c) unreachable(), saving 2.2%
3651108  224380  206812 4082300  3e4a7c vmlinux-bugon-unreachable

6. #define BUG() do{}while(0), saving 2.1%
3654264  224380  206812 4085456  3e56d0 vmlinux-nobug

7. as 6, plus #define BUG_ON if(0 && (c)) unreachable, saving 2.2%
3648392  223996  206748 4079136  3e3e20 vmlinux-no-bugon

8. my patch below, saving 1.8%
3666532  224380  206812 4097724  3e86bc obj-tmp/vmlinux

The gain of doing unreachable and letting the code run off whereever
is minimal compared to the current state of doing nothing, but it
avoids the warnings.

Same test using x86_defconfig:

1. CONFIG_BUG=y, CONFIG_BUGVERBOSE=n
10797859        1395648 1175552 13369059         cbfee3 vmlinux-x86-bug

2. CONFIG_BUG=n, saves 1.0%
10658553        1395584 1175552 13229689         c9de79 vmlinux-x86-nobug

3. with my patch, saves 0.8%
10684186        1395584 1175552 13255322         ca429a vmlinux-x86-archbug

Getting 1-2% savings in kernel size seems absolutely worth keeping the
option, but 0.2-0.4% left for getting reproducible behavior also seems
worthwhile. The result in the patch below.

This basically loses any of the BUG() reporting, but leaves the
logic to trap and kill the task in place when CONFIG_BUG is disabled.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index 7af5c6c..f25e638 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -3,8 +3,6 @@
 
 #include <linux/linkage.h>
 
-#ifdef CONFIG_BUG
-
 /*
  * Use a suitable undefined instruction to use for ARM/Thumb2 bug handling.
  * We need to be careful not to conflict with those used by other modules and
@@ -51,10 +50,10 @@ do {								\
 	asm volatile(BUG_INSTR_TYPE #__value);			\
 	unreachable();						\
 } while (0)
 #endif  /* CONFIG_DEBUG_BUGVERBOSE */
 
 #define HAVE_ARCH_BUG
-#endif  /* CONFIG_BUG */
+#define HAVE_ARCH_BUG_ON
 
 #include <asm-generic/bug.h>
 
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 2f03ff0..ba38ebb 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_X86_BUG_H
 #define _ASM_X86_BUG_H
 
-#ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
 
 #ifdef CONFIG_DEBUG_BUGVERBOSE
@@ -33,8 +32,6 @@ do {								\
 } while (0)
 #endif
 
-#endif /* !CONFIG_BUG */
-
 #include <asm-generic/bug.h>
 
 #endif /* _ASM_X86_BUG_H */
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..bbd2872 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -112,12 +112,13 @@ extern void warn_slowpath_null(const char *file, const int line);
 #endif
 
 #ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
+#define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while(0)
 #endif
 
 #ifndef HAVE_ARCH_WARN_ON
 #define WARN_ON(condition) ({						\
 	int __ret_warn_on = !!(condition);				\
+	(void)__ret_warn_on;						\
 	unlikely(__ret_warn_on);					\
 })
 #endif
@@ -125,6 +126,8 @@ extern void warn_slowpath_null(const char *file, const int line);
 #ifndef WARN
 #define WARN(condition, format...) ({					\
 	int __ret_warn_on = !!(condition);				\
+	if (0 && (__ret_warn_on))					\
+		printk(format);						\
 	unlikely(__ret_warn_on);					\
 })
 #endif




From broonie at kernel.org  Tue May 28 10:56:03 2013
From: broonie at kernel.org (Mark Brown)
Date: Tue, 28 May 2013 15:56:03 +0100
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
Message-ID: <20130528145603.GR21462@opensource.wolfsonmicro.com>

On Tue, May 28, 2013 at 04:47:49PM +0200, Markus Pargmann wrote:
> Add devicetree support for this audio soc fabric driver.

What is an "audio soc fabric driver"?


From jason at lakedaemon.net  Tue May 28 10:56:22 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 10:56:22 -0400
Subject: [GIT PULL v2] ARM: mvebu: fixes for v3.10 (round 3)
In-Reply-To: <20130527185436.GN31290@titan.lakedaemon.net>
References: <20130527185436.GN31290@titan.lakedaemon.net>
Message-ID: <20130528145622.GS31290@titan.lakedaemon.net>

Olof,

Updated to move two non-critical patches to mvebu/fixes-non-critical


The following changes since commit 489e138eec96f529c5e8d4cd3ea45882ecdbf5ca:

  ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node (2013-05-20 17:44:54 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/fixes-3.10-3

for you to fetch changes up to b60b61d41220c8d34e2c62a748bc78bc5d40585e:

  ARM: mvebu: Fix bug in coherency fabric low level init function (2013-05-28 14:50:08 +0000)

----------------------------------------------------------------
mvebu fixes for v3.10 round 3

 - mvebu
    - fix bug in coherency fabric low level init

 - kirkwood
    - fix crash from pcie double init

----------------------------------------------------------------
Andrew Lunn (1):
      ARM: Kirkwood: TS219: Fix crash by double PCIe instantiation

Nadav Haklai (1):
      ARM: mvebu: Fix bug in coherency fabric low level init function

 arch/arm/mach-kirkwood/board-ts219.c | 10 ----------
 arch/arm/mach-mvebu/coherency_ll.S   | 16 +++++++++++-----
 2 files changed, 11 insertions(+), 15 deletions(-)


From mpa at pengutronix.de  Tue May 28 11:00:57 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Tue, 28 May 2013 17:00:57 +0200
Subject: [PATCH] ARM: mxs: icoll: Fix interrupts gpio bank 0
Message-ID: <1369753257-11091-1-git-send-email-mpa@pengutronix.de>

The mxs interrupt controller does not support polling for interrupts,
but the driver still does it, which is a relict from
pre-MULTI_IRQ_HANDLER times.

The existing code assumes that 0x7f means no interrupt, but this value
is an actually valid irq number, namely gpio bank 0's irq. This results
in the driver not detecting when irq 0x7f is active which makes the
machine effectively dead lock.

This patch removes the interrupt poll loop and allows usage of gpio0
interrupt without an infinite loop.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
Cc: stable at vger.kernel.org
---
 drivers/irqchip/irq-mxs.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
index 29889bb..63b3d4e 100644
--- a/drivers/irqchip/irq-mxs.c
+++ b/drivers/irqchip/irq-mxs.c
@@ -76,16 +76,10 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 {
 	u32 irqnr;
 
-	do {
-		irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
-		if (irqnr != 0x7f) {
-			__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
-			irqnr = irq_find_mapping(icoll_domain, irqnr);
-			handle_IRQ(irqnr, regs);
-			continue;
-		}
-		break;
-	} while (1);
+	irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
+	__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+	irqnr = irq_find_mapping(icoll_domain, irqnr);
+	handle_IRQ(irqnr, regs);
 }
 
 static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
-- 
1.8.2.rc2



From p.zabel at pengutronix.de  Tue May 28 11:05:46 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Tue, 28 May 2013 17:05:46 +0200
Subject: [PATCH v4 8/8] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <CAOMZO5BJ7h=_cqSUG6X25SHTMe5ym1_nToj5P_PMR9bxN+B2Ow@mail.gmail.com>
References: <1361878774-6382-1-git-send-email-p.zabel@pengutronix.de>
 <1361878774-6382-9-git-send-email-p.zabel@pengutronix.de>
 <CAOMZO5BJ7h=_cqSUG6X25SHTMe5ym1_nToj5P_PMR9bxN+B2Ow@mail.gmail.com>
Message-ID: <1369753546.4000.4.camel@pizza.hi.pengutronix.de>

Hi Fabio,

Am Montag, den 27.05.2013, 13:25 -0300 schrieb Fabio Estevam:
> On Tue, Feb 26, 2013 at 8:39 AM, Philipp Zabel <p.zabel at pengutronix.de> wrote:
> > This driver implements a reset controller device that toggles gpios
> > connected to reset pins of peripheral ICs. The delay between assertion
> > and de-assertion of the reset signal can be configured.
> >
> > Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> 
> Looks good and it is a very useful binding.
> 
> Will anyone apply this?

I have tried to address Olof's concerns by making the gpio-reset driver
only handle a single gpio per device.

I'll send a new patch for review.

regards
Philipp



From p.zabel at pengutronix.de  Tue May 28 11:06:15 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Tue, 28 May 2013 17:06:15 +0200
Subject: [PATCH v7] reset: Add driver for gpio-controlled reset pins
Message-ID: <1369753575-9818-1-git-send-email-p.zabel@pengutronix.de>

This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
Changes since v6:
 - Switched to a single gpio per gpio-reset device, as Olof suggested.
   This should make the device tree binding more straightforward.
 - Changed reset delay property to reset-delay-us.
---
 .../devicetree/bindings/reset/gpio-reset.txt       |  35 +++++
 drivers/reset/Kconfig                              |  11 ++
 drivers/reset/Makefile                             |   1 +
 drivers/reset/gpio-reset.c                         | 171 +++++++++++++++++++++
 4 files changed, 218 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/gpio-reset.txt
 create mode 100644 drivers/reset/gpio-reset.c

diff --git a/Documentation/devicetree/bindings/reset/gpio-reset.txt b/Documentation/devicetree/bindings/reset/gpio-reset.txt
new file mode 100644
index 0000000..6f7476b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/gpio-reset.txt
@@ -0,0 +1,35 @@
+GPIO reset controller
+=====================
+
+A GPIO reset controller controls a single GPIO that is connected to the reset
+pin of a peripheral IC. Please also refer to reset.txt in this directory for
+common reset controller binding usage.
+
+Required properties:
+- compatible: Should be "gpio-reset"
+- reset-gpios: A gpio used as reset line. The gpio specifier for this property
+               depends on the gpio controller that provides the gpio.
+- #reset-cells: 0, see below
+
+Optional properties:
+- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for
+                  this duration to reset.
+- initially-in-reset: boolean. If not set, the initial state should be a
+                      deasserted reset line. If this property exists, the
+                      reset line should be kept in reset.
+
+example:
+
+sii902x_reset: gpio-reset {
+	compatible = "gpio-reset";
+	reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <10000>;
+	initially-in-reset;
+	#reset-cells = <0>;
+};
+
+/* Device with nRESET pin connected to GPIO5_0 */
+sii902x at 39 {
+	/* ... */
+	resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */
+};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..1a862df 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,14 @@ menuconfig RESET_CONTROLLER
 	  via GPIOs or SoC-internal reset controller modules.
 
 	  If unsure, say no.
+
+if RESET_CONTROLLER
+
+config RESET_GPIO
+	tristate "GPIO reset controller support"
+	depends on GPIOLIB && OF
+	help
+	  This driver provides support for reset lines that are controlled
+	  directly by GPIOs.
+
+endif
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f..b854f20 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_RESET_CONTROLLER) += core.o
+obj-$(CONFIG_RESET_GPIO) += gpio-reset.o
diff --git a/drivers/reset/gpio-reset.c b/drivers/reset/gpio-reset.c
new file mode 100644
index 0000000..7faea09
--- /dev/null
+++ b/drivers/reset/gpio-reset.c
@@ -0,0 +1,169 @@
+/*
+ * GPIO Reset Controller driver
+ *
+ * Copyright 2013 Philipp Zabel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+
+struct gpio_reset_data {
+	struct reset_controller_dev rcdev;
+	unsigned int gpio;
+	bool active_low;
+	u32 delay_us;
+};
+
+static void __gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
+{
+	struct gpio_reset_data *drvdata = container_of(rcdev,
+			struct gpio_reset_data, rcdev);
+	int value = asserted;
+
+	if (drvdata->active_low)
+		value = !value;
+
+	gpio_set_value(drvdata->gpio, value);
+}
+
+static int gpio_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct gpio_reset_data *drvdata = container_of(rcdev,
+			struct gpio_reset_data, rcdev);
+
+	if (drvdata->delay_us < 0)
+		return -ENOSYS;
+
+	__gpio_reset_set(rcdev, 1);
+	udelay(drvdata->delay_us);
+	__gpio_reset_set(rcdev, 0);
+
+	return 0;
+}
+
+static int gpio_reset_assert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	__gpio_reset_set(rcdev, 1);
+
+	return 0;
+}
+
+static int gpio_reset_deassert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	__gpio_reset_set(rcdev, 0);
+
+	return 0;
+}
+
+static struct reset_control_ops gpio_reset_ops = {
+	.reset = gpio_reset,
+	.assert = gpio_reset_assert,
+	.deassert = gpio_reset_deassert,
+};
+
+static int of_gpio_reset_xlate(struct reset_controller_dev *rcdev,
+			       const struct of_phandle_args *reset_spec)
+{
+	if (WARN_ON(reset_spec->args_count != 0))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int gpio_reset_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct gpio_reset_data *drvdata;
+	enum of_gpio_flags flags;
+	unsigned long gpio_flags;
+	bool initially_in_reset;
+	int ret;
+
+	drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
+	if (drvdata == NULL)
+		return -ENOMEM;
+
+	if (of_gpio_named_count(np, "reset-gpios") != 1)
+		return -EINVAL;
+
+	drvdata->gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &flags);
+	if (drvdata->gpio == -EPROBE_DEFER) {
+		return drvdata->gpio;
+	} else if (!gpio_is_valid(drvdata->gpio)) {
+		dev_err(&pdev->dev, "invalid reset gpio: %d\n", drvdata->gpio);
+		return drvdata->gpio;
+	}
+
+	drvdata->active_low = flags & OF_GPIO_ACTIVE_LOW;
+
+	ret = of_property_read_u32(np, "reset-delay-us", &drvdata->delay_us);
+	if (ret < 0)
+		return ret;
+
+	initially_in_reset = of_property_read_bool(np, "initially-in-reset");
+	if (drvdata->active_low ^ initially_in_reset)
+		gpio_flags = GPIOF_OUT_INIT_HIGH;
+	else
+		gpio_flags = GPIOF_OUT_INIT_LOW;
+
+	ret = devm_gpio_request_one(&pdev->dev, drvdata->gpio, gpio_flags, NULL);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to request gpio %d: %d\n",
+			drvdata->gpio, ret);
+		return ret;
+	}
+
+	drvdata->rcdev.of_node = np;
+	drvdata->rcdev.owner = THIS_MODULE;
+	drvdata->rcdev.nr_resets = 1;
+	drvdata->rcdev.ops = &gpio_reset_ops;
+	drvdata->rcdev.of_xlate = of_gpio_reset_xlate;
+	reset_controller_register(&drvdata->rcdev);
+
+	platform_set_drvdata(pdev, drvdata);
+
+	return 0;
+}
+
+static int gpio_reset_remove(struct platform_device *pdev)
+{
+	struct gpio_reset_data *drvdata = platform_get_drvdata(pdev);
+
+	reset_controller_unregister(&drvdata->rcdev);
+
+	return 0;
+}
+
+static struct of_device_id gpio_reset_dt_ids[] = {
+	{ .compatible = "gpio-reset" },
+	{ }
+};
+
+static struct platform_driver gpio_reset_driver = {
+	.probe = gpio_reset_probe,
+	.remove = gpio_reset_remove,
+	.driver = {
+		.name = "gpio-reset",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(gpio_reset_dt_ids),
+	},
+};
+
+module_platform_driver(gpio_reset_driver);
+
+MODULE_AUTHOR("Philipp Zabel <p.zabel at pengutronix.de>");
+MODULE_DESCRIPTION("gpio reset controller");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:gpio-reset");
+MODULE_DEVICE_TABLE(of, gpio_reset_dt_ids);
-- 
1.8.2.rc2



From hpa at zytor.com  Tue May 28 10:55:32 2013
From: hpa at zytor.com (H. Peter Anvin)
Date: Tue, 28 May 2013 07:55:32 -0700
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <20130528081910.GA29557@gmail.com>
References: <519DCBEF.3090208@asianux.com>
 <20130523090534.GJ18614@n2100.arm.linux.org.uk>
 <CAMuHMdWez-j1Maa3BD7ucmzv0_zFJnChERQiHFmkCaZUzG0_AA@mail.gmail.com>
 <201305231139.38233.arnd@arndb.de>
 <20130523100409.GK18614@n2100.arm.linux.org.uk>
 <20130528081910.GA29557@gmail.com>
Message-ID: <51A4C564.4040301@zytor.com>

On 05/28/2013 01:19 AM, Ingo Molnar wrote:
> 
> So I think the same principle applies to it as to any other debugging 
> code: it's fine to be able to turn debugging off. It's a performance 
> versus kernel robustness/determinism trade-off.
> 

I suspect, rather, that BUG() should turn into a trap (or jump to a
death routine) under any circumstances.  The one thing that can be
omitted for small configurations are the annotations, which only serve
to output a more human-readable error message.

	-hpa




From swarren at wwwdotorg.org  Tue May 28 11:07:58 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 09:07:58 -0600
Subject: [PATCH v2 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <51A4C84E.4070005@wwwdotorg.org>

On 05/23/2013 09:36 AM, Florian Vaussard wrote:
> Hello,
> 
> Following a similar proposal by Stephen Warren for tegra [1], this series
> makes use of the C preprocessor when compiling OMAP DT files, and
> accomplishes some improvements to improve overall readability.
> 
> Patch 1 is a preparation for the rest of the series.
> Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
> IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
> it to simplify pinctrl DT.
> 
> For all targets, the .dtb files were diff-tested before and after
> applying the series to guarantee identity.

The series briefly,

Reviewed-by: Stephen Warren <swarren at nvidia.com>


From andy.shevchenko at gmail.com  Tue May 28 11:10:26 2013
From: andy.shevchenko at gmail.com (Andy Shevchenko)
Date: Tue, 28 May 2013 18:10:26 +0300
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <3950519.8yj1SQodNQ@wuerfel>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <CACRpkdaQfaPQdJ1SDN--JDqcrXs8p6=FaDN+4KtKZF6nLtOvvw@mail.gmail.com>
 <1369750864.2939.1.camel@hornet> <3950519.8yj1SQodNQ@wuerfel>
Message-ID: <CAHp75Vern=-6KjfjsC+Y6N9H+yhb7eGC_Ui1Uf+8Y3069fqNow@mail.gmail.com>

On Tue, May 28, 2013 at 5:52 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>         depends on KMS_ARMCLCD != 'y'
>         depends on 'm' if KMS_ARMCLCD

Those two above could be one actually.

Just my 2 cents.

--
With Best Regards,
Andy Shevchenko


From florian.vaussard at epfl.ch  Tue May 28 11:13:21 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Tue, 28 May 2013 17:13:21 +0200
Subject: [PATCH v2 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <51A4C84E.4070005@wwwdotorg.org>
References: <1369323421-4180-1-git-send-email-florian.vaussard@epfl.ch>
 <51A4C84E.4070005@wwwdotorg.org>
Message-ID: <51A4C991.6050502@epfl.ch>

On 05/28/2013 05:07 PM, Stephen Warren wrote:
> On 05/23/2013 09:36 AM, Florian Vaussard wrote:
>> Hello,
>>
>> Following a similar proposal by Stephen Warren for tegra [1], this series
>> makes use of the C preprocessor when compiling OMAP DT files, and
>> accomplishes some improvements to improve overall readability.
>>
>> Patch 1 is a preparation for the rest of the series.
>> Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
>> IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
>> it to simplify pinctrl DT.
>>
>> For all targets, the .dtb files were diff-tested before and after
>> applying the series to guarantee identity.
>
> The series briefly,
>
> Reviewed-by: Stephen Warren <swarren at nvidia.com>
>

Thank you. FYI, I posted a v3 addressing Tony's comments [1].

Regards,

Florian

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/98320


From swarren at wwwdotorg.org  Tue May 28 11:14:02 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 09:14:02 -0600
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
In-Reply-To: <CACRpkdYxvBvYAnmp-p5WwB3QD0rd83qDcdg-BMhN7-2Jv8Oo_w@mail.gmail.com>
References: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
 <519A8A57.9060007@wwwdotorg.org>
 <CACRpkdZieCmFnHCGUkv8EqcAtb3DA7dSZpimSdB4P81tZPJRoQ@mail.gmail.com>
 <519F8B02.1080000@wwwdotorg.org>
 <CACRpkdYxvBvYAnmp-p5WwB3QD0rd83qDcdg-BMhN7-2Jv8Oo_w@mail.gmail.com>
Message-ID: <51A4C9BA.40903@wwwdotorg.org>

On 05/25/2013 03:09 AM, Linus Walleij wrote:
> On Fri, May 24, 2013 at 5:45 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>> On 05/24/2013 02:04 AM, Linus Walleij wrote:
> 
>>> Prevention of module unloading of pin controllers has never
>>> been working properly, as there is no way to release the
>>> pinctrl handles taken by different drivers.
>>>
>>> I think that is why most pin controller drivers are bool rather
>>> than tristate.
>>
>> Once we get to multi-platform distro kernels, we will probably want all
>> the pinctrl drivers to be modules so only the correct one gets loaded
>> from an initrd. Hence, we'll want to move things to tristate rather than
>> away from it.
> 
> OK ... As some kind of excuse I think the current situation is an
> outgrowth of the fact that all the custom set-up used to be in machines
> down in arch/arm/* and inevitably done at machine init.
> 
>> If we know the pinctrl subsystem doesn't yet work correctly with module
>> unloads, should we modify pinctrl_register() to simply take a lock on
>> the driver module and never drop it, so that we guarantee we don't try
>> to unload the module later? Or, is this effectively already in place?
> 
> Hm, it won't happen with anything but pinctrl-single for sure.
> But I know that Tony used it at one point, however I still
> suspect that he was only using hogs.
> 
> We should maybe take the lock at the instant we instatiate a
> pinctrl handle from something else than a hog, so as to mark
> that we then have external dependencies that make unloading
> impossible.

Yes.

> But it'd be even cooler to actually just iterate over the
> pinctrl_list och handles and orphan them, and later recouple
> them if a driver is loaded back in.

Hmm. What happens if the client driver wants to select a different state
while the pinctrl driver itself isn't loaded? I'm not sure how workable
that is. I think the only way to make it work would be to cache enough
information in the struct pinctrl that it could be activated even if the
driver wasn't loaded. That seems a little scary.

I'd be fine if there was a requirement to unload all drives that were
clients of the pinctrl driver before you could unload the pinctrl
driver, just like any other driver/subsystem. This would work fine at
least for testing with just hogs, which while not great for full-system
testing would surely be fine at least when first developing the pinctrl
driver.


From swarren at wwwdotorg.org  Tue May 28 11:16:14 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 09:16:14 -0600
Subject: [PATCH] clk: tegra: fix clk_out parents list
In-Reply-To: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>
References: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <51A4CA3E.9080608@wwwdotorg.org>

On 05/27/2013 01:54 AM, Prashant Gaikwad wrote:
> Number of parents for clk_out_2 and clk_out_3 was incorrectly set
> to clk_out1_parents. Even though it did not break anything since the
> size was same better to fix.

Acked-by: Stephen Warren <swarren at nvidia.com>


From swarren at wwwdotorg.org  Tue May 28 11:16:58 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 09:16:58 -0600
Subject: [PATCH v2] clk: tegra: Use common of_clk_init function
In-Reply-To: <1369640409-1981-1-git-send-email-pgaikwad@nvidia.com>
References: <1369640409-1981-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <51A4CA6A.8090103@wwwdotorg.org>

On 05/27/2013 01:40 AM, Prashant Gaikwad wrote:
> Use common of_clk_init() function for clocks initialization.

Acked-by: Stephen Warren <swarren at nvidia.com>


From thomas.petazzoni at free-electrons.com  Tue May 28 11:17:45 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 May 2013 17:17:45 +0200
Subject: [PATCH] arm: omap2: fix AM33xx hwmod infos for UART2
Message-ID: <1369754265-27712-1-git-send-email-thomas.petazzoni@free-electrons.com>

The UART2 hwmod structure is pointing to the EDMA channels of UART1,
which doesn't look right. This patch fixes this by making the UART2
hwmod structure to a new structure that lists the EDMA channels to be
used by the UART2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 01d8f32..9113251 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2006,6 +2006,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
 	},
 };
 
+/* uart2 */
+static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
+	{ .name = "tx",	.dma_req = 28, },
+	{ .name = "rx",	.dma_req = 29, },
+	{ .dma_req = -1 }
+};
+
 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
 	{ .irq = 73 + OMAP_INTC_START, },
 	{ .irq = -1 },
@@ -2016,7 +2023,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.mpu_irqs	= am33xx_uart2_irqs,
-	.sdma_reqs	= uart1_edma_reqs,
+	.sdma_reqs	= uart2_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-- 
1.7.9.5



From stern at rowland.harvard.edu  Tue May 28 11:27:13 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Tue, 28 May 2013 11:27:13 -0400 (EDT)
Subject: [PATCH V8 3/3] USB: OHCI: make ohci-pci a separate driver
In-Reply-To: <1369746291-21788-4-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305281126340.1030-100000@iolanthe.rowland.org>

On Tue, 28 May 2013, Manjunath Goudar wrote:

> This patch splits the PCI portion of ohci-hcd out into its
> own separate driver module, called ohci-pci.
> 
> The major point of difficulty lies in ohci-pci's many vendor- and
> device-specific workarounds.  Some of them have to be applied before
> calling ohci_start() some after, which necessitates a fair amount of
> code motion.  The other platform drivers require much smaller changes.
> 
> The complete sb800_prefetch() function moved to ohci-q.c,because its
> only related to ohci-pci driver.
> 
> USB_OHCI_HCD_PCI symbol no longer dependence on STB03xxx, PPC_MPC52xx and
> USB_OHCI_HCD_PPC_OF that's what removed.
> 
> V2:
>   - few specific content of pci related code in ohci_pci_start function has been moved to ohci_pci_reset
>     and rest of the generic code is written in ohci_start of ohci-hcd.c file.
> V3:
>  - ohci_restart() has been called in ohci_pci_reset() function for to reset the ohci pci.
> 
> V4:
>  -sb800_prefetch() moved to ohci-q.c,because its only related to ohci-pci.
>  -no longer _creating_ CONFIG_USB_OHCI_PCI,creating CONFIG_USB_OHCI_HCD_PCI.
>  -overrides renamed with pci_override,its giving proper meaning.
> 
> V5:
>  -sb800_prefetch() moved to pci-quirks.c,because its only related to pci.
> 
> V6:
>  -sb800_prefetch() function has been moved to pci-quirks.c made as separate patch in 2/3.
>  -Most of the generic ohci pci changes moved in 2/3 patch,now this is complete  ohci-pci separation patch.
> 
> V7:
>  -Unrelated include file has been removed from ohci.h file.
> 
> V8:
>  -USB_OHCI_HCD_PCI symbol does not dependence on STB03xxx, PPC_MPC52xx and USB_OHCI_HCD_PPC_OF.

Acked-by: Alan Stern <stern at rowland.harvard.edu>



From jason at lakedaemon.net  Tue May 28 11:40:47 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 11:40:47 -0400
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130528154047.GT31290@titan.lakedaemon.net>

Thomas, Sebastian,

In order to avoid losing changes between this series and mvebu/pcie,
I've rebased this series on top of mvebu/pcie and incorporated the
correct conflict resolution into this series.  See below...

On Sat, May 11, 2013 at 03:08:00AM +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
> 
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
> 
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
> 
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> 
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> 
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
> 
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
> 
> Sebastian Hesselbarth (10):
>   clk: mvebu: introduce per-clock-gate flags

I updated armada_370_gating_descr[] and armada_xp_gating_descr[] to
incorporate Thomas' pcie changes.

>   clk: mvebu: add common clock functions for core clk and clk gating
>   clk: mvebu: add Dove SoC-centric clock init
>   clk: mvebu: add Kirkwood SoC-centric clock init

>   clk: mvebu: add Armada 370 SoC-centric clock init
>   clk: mvebu: add Armada XP SoC-centric clock init

I then migrated the changes above to these two commits.

>   ARM: dove: move DT boards to SoC-centric clock init
>   ARM: kirkwood: move DT boards to SoC-centric clock init
>   ARM: mvebu: move DT boards to SoC-centric clock init

>   clk: mvebu: desintegrate obsolete file

Obviously, the diffstat changed slightly here.

I'm posting the revised version as replies to patches 1, 5 and 6. Please
let me know if I messed it up.  I'd like to send the PR for these
shortly.

thx,

Jason.


From linux at roeck-us.net  Tue May 28 11:42:12 2013
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 28 May 2013 08:42:12 -0700
Subject: [PATCHv2 0/3] Add G762/G763 PWM fan controller
In-Reply-To: <20130528134734.GA12585@mithrandir>
References: <cover.1369687670.git.arno@natisbad.org>
 <152190814.eApXVbVBPA@wuerfel> <87li6z2yxj.fsf@natisbad.org>
 <20130528111921.GD11547@mithrandir>
 <20130528122940.GA29012@roeck-us.net>
 <20130528134734.GA12585@mithrandir>
Message-ID: <20130528154212.GB21891@roeck-us.net>

On Tue, May 28, 2013 at 03:47:49PM +0200, Thierry Reding wrote:
> On Tue, May 28, 2013 at 05:29:40AM -0700, Guenter Roeck wrote:
> > On Tue, May 28, 2013 at 01:19:23PM +0200, Thierry Reding wrote:
> > > On Tue, May 28, 2013 at 12:15:04PM +0200, Arnaud Ebalard wrote:
> > > > Hi Arnd,
> > > > 
> > > > Arnd Bergmann <arnd at arndb.de> writes:
> > > > 
> > > > > On Tuesday 28 May 2013 00:02:29 Arnaud Ebalard wrote:
> > > > >> 
> > > > >> This series adds support for GMT G762/G763. This work is based on a
> > > > >> basic version for 2.6.31 kernel developed Olivier Mouchet for LaCie
> > > > >> NAS. Updates have been performed to run on recent kernels. Support has
> > > > >> been completed and additional features added: ability to configure
> > > > >> various characteristics from .dts file, better initialization, alarms
> > > > >> and error reporting support, gear mode, polarity, fan pulse per
> > > > >> revolution, fan startup voltage control.
> > > > >
> > > > > I wonder if this could be split into two separate drivers, one for
> > > > > the pwm subsystem, and one for a hardware-independent fan controller
> > > > > based on the pwm interfaces.
> > > > 
> > > > To be honest, I wouldn't even know how to start in order to do that.
> > > > Additionally, it would be worth the effort if other drivers could be
> > > > easily refactored using this idea. I'll let hwmon people provide some
> > > > feedback and try and comply with their directions (based on the cpu
> > > > cycle I can spend on this).
> > > 
> > > What Arnd proposes doesn't sounds like a very good idea. PWM-controlled
> > > fans should be able to work just fine using a generic driver that uses
> > > the PWM framework, similar to the PWM backlight and LED drivers.
> > > 
> > Isn't that exactly what Arnd proposed ?
> 
> Oh, right. I meant to say: "What Arnd proposes sounds like a very good
> idea." =) Sorry for the confusion.
> 
I looked into it, and frankly I don't know how to make it work either. The chip
is dedicated to fan control and supports both linear and pwm mode. Both modes
are controlled differently. The available configuration options are very fan
control specific.

While I agree that a generic fan control driver for pwm chips would be great,
problem here is that this is not a generic pwm controller. 

Thanks,
Guenter


From jason at lakedaemon.net  Tue May 28 11:44:09 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 11:44:09 -0400
Subject: [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags
In-Reply-To: <1368234490-31416-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368234490-31416-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130528154409.GU31290@titan.lakedaemon.net>

Sebastian, Thomas,

On Sat, May 11, 2013 at 03:08:01AM +0200, Sebastian Hesselbarth wrote:
> Clock gates found on MVEBU SoCs get registered by a common function.
> To allow specific SoCs to provide tweaks introduce flags to the clock
> gate descriptor instead of filling up the common function SoC specific
> tweaks.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  drivers/clk/mvebu/clk-gating-ctrl.c |  153 +++++++++++++++++------------------
>  1 file changed, 72 insertions(+), 81 deletions(-)

Here's the revised version after rebasing onto mvebu/pcie:

--->8-------

commit 12f8ebff609dc9378a8c121e195ccf6984d5e5c6
Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date:   Sat May 11 03:08:01 2013 +0200

    clk: mvebu: introduce per-clock-gate flags
    
    Clock gates found on MVEBU SoCs get registered by a common function.
    To allow specific SoCs to provide tweaks introduce flags to the clock
    gate descriptor instead of filling up the common function SoC specific
    tweaks.
    
    Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
    Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 2f03723..1df6c4e 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
 	const char *name;
 	const char *parent;
 	int bit_idx;
+	unsigned long flags;
 };
 
 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
 	}
 
 	for (n = 0; n < ctrl->num_gates; n++) {
-		u8 flags = 0;
 		const char *parent =
 			(descr[n].parent) ? descr[n].parent : default_parent;
-
-		/*
-		 * On Armada 370, the DDR clock is a special case: it
-		 * isn't taken by any driver, but should anyway be
-		 * kept enabled, so we mark it as IGNORE_UNUSED for
-		 * now.
-		 */
-		if (!strcmp(descr[n].name, "ddr"))
-			flags |= CLK_IGNORE_UNUSED;
-
 		ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
-				   flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+					descr[n].flags, base, descr[n].bit_idx,
+					0, &ctrl->lock);
 		WARN_ON(IS_ERR(ctrl->gates[n]));
 	}
 	of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,99 +105,99 @@ static void __init mvebu_clk_gating_setup(
 
 #ifdef CONFIG_MACH_ARMADA_370
 static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
-	{ "audio", NULL, 0 },
-	{ "pex0_en", NULL, 1 },
-	{ "pex1_en", NULL,  2 },
-	{ "ge1", NULL, 3 },
-	{ "ge0", NULL, 4 },
-	{ "pex0", "pex0_en", 5 },
-	{ "pex1", "pex1_en", 9 },
-	{ "sata0", NULL, 15 },
-	{ "sdio", NULL, 17 },
-	{ "tdm", NULL, 25 },
-	{ "ddr", NULL, 28 },
-	{ "sata1", NULL, 30 },
+	{ "audio", NULL, 0, 0 },
+	{ "pex0_en", NULL, 1, 0 },
+	{ "pex1_en", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex0", "pex0_en", 5, 0 },
+	{ "pex1", "pex1_en", 9, 0 },
+	{ "sata0", NULL, 15, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+	{ "sata1", NULL, 30, 0 },
 	{ }
 };
 #endif
 
 #ifdef CONFIG_MACH_ARMADA_XP
 static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
-	{ "audio", NULL, 0 },
-	{ "ge3", NULL, 1 },
-	{ "ge2", NULL,  2 },
-	{ "ge1", NULL, 3 },
-	{ "ge0", NULL, 4 },
-	{ "pex00", NULL, 5 },
-	{ "pex01", NULL, 6 },
-	{ "pex02", NULL, 7 },
-	{ "pex03", NULL, 8 },
-	{ "pex10", NULL, 9 },
-	{ "pex11", NULL, 10 },
-	{ "pex12", NULL, 11 },
-	{ "pex13", NULL, 12 },
-	{ "bp", NULL, 13 },
-	{ "sata0lnk", NULL, 14 },
-	{ "sata0", "sata0lnk", 15 },
-	{ "lcd", NULL, 16 },
-	{ "sdio", NULL, 17 },
-	{ "usb0", NULL, 18 },
-	{ "usb1", NULL, 19 },
-	{ "usb2", NULL, 20 },
-	{ "xor0", NULL, 22 },
-	{ "crypto", NULL, 23 },
-	{ "tdm", NULL, 25 },
-	{ "pex20", NULL, 26 },
-	{ "pex30", NULL, 27 },
-	{ "xor1", NULL, 28 },
-	{ "sata1lnk", NULL, 29 },
-	{ "sata1", "sata1lnk", 30 },
+	{ "audio", NULL, 0, 0 },
+	{ "ge3", NULL, 1, 0 },
+	{ "ge2", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex00", NULL, 5, 0 },
+	{ "pex01", NULL, 6, 0 },
+	{ "pex02", NULL, 7, 0 },
+	{ "pex03", NULL, 8, 0 },
+	{ "pex10", NULL, 9, 0 },
+	{ "pex11", NULL, 10, 0 },
+	{ "pex12", NULL, 11, 0 },
+	{ "pex13", NULL, 12, 0 },
+	{ "bp", NULL, 13, 0 },
+	{ "sata0lnk", NULL, 14, 0 },
+	{ "sata0", "sata0lnk", 15, 0 },
+	{ "lcd", NULL, 16, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "usb0", NULL, 18, 0 },
+	{ "usb1", NULL, 19, 0 },
+	{ "usb2", NULL, 20, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ "crypto", NULL, 23, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "pex20", NULL, 26, 0 },
+	{ "pex30", NULL, 27, 0 },
+	{ "xor1", NULL, 28, 0 },
+	{ "sata1lnk", NULL, 29, 0 },
+	{ "sata1", "sata1lnk", 30, 0 },
 	{ }
 };
 #endif
 
 #ifdef CONFIG_ARCH_DOVE
 static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
-	{ "usb0", NULL, 0 },
-	{ "usb1", NULL, 1 },
-	{ "ge", "gephy", 2 },
-	{ "sata", NULL, 3 },
-	{ "pex0", NULL, 4 },
-	{ "pex1", NULL, 5 },
-	{ "sdio0", NULL, 8 },
-	{ "sdio1", NULL, 9 },
-	{ "nand", NULL, 10 },
-	{ "camera", NULL, 11 },
-	{ "i2s0", NULL, 12 },
-	{ "i2s1", NULL, 13 },
-	{ "crypto", NULL, 15 },
-	{ "ac97", NULL, 21 },
-	{ "pdma", NULL, 22 },
-	{ "xor0", NULL, 23 },
-	{ "xor1", NULL, 24 },
-	{ "gephy", NULL, 30 },
+	{ "usb0", NULL, 0, 0 },
+	{ "usb1", NULL, 1, 0 },
+	{ "ge", "gephy", 2, 0 },
+	{ "sata", NULL, 3, 0 },
+	{ "pex0", NULL, 4, 0 },
+	{ "pex1", NULL, 5, 0 },
+	{ "sdio0", NULL, 8, 0 },
+	{ "sdio1", NULL, 9, 0 },
+	{ "nand", NULL, 10, 0 },
+	{ "camera", NULL, 11, 0 },
+	{ "i2s0", NULL, 12, 0 },
+	{ "i2s1", NULL, 13, 0 },
+	{ "crypto", NULL, 15, 0 },
+	{ "ac97", NULL, 21, 0 },
+	{ "pdma", NULL, 22, 0 },
+	{ "xor0", NULL, 23, 0 },
+	{ "xor1", NULL, 24, 0 },
+	{ "gephy", NULL, 30, 0 },
 	{ }
 };
 #endif
 
 #ifdef CONFIG_ARCH_KIRKWOOD
 static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
-	{ "ge0", NULL, 0 },
-	{ "pex0", NULL, 2 },
-	{ "usb0", NULL, 3 },
-	{ "sdio", NULL, 4 },
-	{ "tsu", NULL, 5 },
-	{ "runit", NULL, 7 },
-	{ "xor0", NULL, 8 },
-	{ "audio", NULL, 9 },
-	{ "powersave", "cpuclk", 11 },
-	{ "sata0", NULL, 14 },
-	{ "sata1", NULL, 15 },
-	{ "xor1", NULL, 16 },
-	{ "crypto", NULL, 17 },
-	{ "pex1", NULL, 18 },
-	{ "ge1", NULL, 19 },
-	{ "tdm", NULL, 20 },
+	{ "ge0", NULL, 0, 0 },
+	{ "pex0", NULL, 2, 0 },
+	{ "usb0", NULL, 3, 0 },
+	{ "sdio", NULL, 4, 0 },
+	{ "tsu", NULL, 5, 0 },
+	{ "runit", NULL, 7, 0 },
+	{ "xor0", NULL, 8, 0 },
+	{ "audio", NULL, 9, 0 },
+	{ "powersave", "cpuclk", 11, 0 },
+	{ "sata0", NULL, 14, 0 },
+	{ "sata1", NULL, 15, 0 },
+	{ "xor1", NULL, 16, 0 },
+	{ "crypto", NULL, 17, 0 },
+	{ "pex1", NULL, 18, 0 },
+	{ "ge1", NULL, 19, 0 },
+	{ "tdm", NULL, 20, 0 },
 	{ }
 };
 #endif


From arnd at arndb.de  Tue May 28 11:43:52 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 17:43:52 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <51A4C564.4040301@zytor.com>
References: <519DCBEF.3090208@asianux.com> <20130528081910.GA29557@gmail.com>
 <51A4C564.4040301@zytor.com>
Message-ID: <201305281743.52649.arnd@arndb.de>

On Tuesday 28 May 2013, H. Peter Anvin wrote:
> On 05/28/2013 01:19 AM, Ingo Molnar wrote:
> > 
> > So I think the same principle applies to it as to any other debugging 
> > code: it's fine to be able to turn debugging off. It's a performance 
> > versus kernel robustness/determinism trade-off.
> > 
> 
> I suspect, rather, that BUG() should turn into a trap (or jump to a
> death routine) under any circumstances.  The one thing that can be
> omitted for small configurations are the annotations, which only serve
> to output a more human-readable error message.

Right, that is what the patch I just posted does.

On a related note, I found that WARN_ON() can no longer be compiled
out since there is already code that relies on the side-effects of
the condition. I assume that was an intentional change I missed,
since it used to be defined so that you could remove it completely.

	Arnd


From jason at lakedaemon.net  Tue May 28 11:46:56 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 11:46:56 -0400
Subject: [PATCH 05/10] clk: mvebu: add Armada 370 SoC-centric clock init
In-Reply-To: <1368234490-31416-6-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368234490-31416-6-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130528154656.GV31290@titan.lakedaemon.net>

Sebastian, Thomas,

On Sat, May 11, 2013 at 03:08:05AM +0200, Sebastian Hesselbarth wrote:
> This is moving core clock and clock gating init for Armada 370 to
> its own file and adds a Kconfig option. Also init functions are added
> and declared so they get called on of_clk_init.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  drivers/clk/mvebu/Kconfig      |    5 ++
>  drivers/clk/mvebu/Makefile     |    1 +
>  drivers/clk/mvebu/armada-370.c |  176 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 182 insertions(+)
>  create mode 100644 drivers/clk/mvebu/armada-370.c

Here's the revised version after rebasing onto mvebu/pcie:

---->8------

commit 1bc2c25c3cacce0965d38f3ae2ab7571dffa1b6e
Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date:   Sat May 11 03:08:05 2013 +0200

    clk: mvebu: add Armada 370 SoC-centric clock init
    
    This is moving core clock and clock gating init for Armada 370 to
    its own file and adds a Kconfig option. Also init functions are added
    and declared so they get called on of_clk_init.
    
    Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
    Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 211695c..1daf61e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -10,6 +10,11 @@ config MVEBU_CLK_GATING
 config MVEBU_CLK_COMMON
 	bool
 
+config ARMADA_370_CLK
+	bool
+	select MVEBU_CLK_COMMON
+	select MVEBU_CLK_CPU
+
 config DOVE_CLK
 	bool
 	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 97d1ab0..367b72c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_MVEBU_CLK_CORE) 	+= clk.o clk-core.o
 obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
 
+obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 0000000..079960e
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL				0	/* Low part [0:31] */
+#define	 SARL_A370_PCLK_FREQ_OPT	11
+#define	 SARL_A370_PCLK_FREQ_OPT_MASK	0xF
+#define	 SARL_A370_FAB_FREQ_OPT		15
+#define	 SARL_A370_FAB_FREQ_OPT_MASK	0x1F
+#define	 SARL_A370_TCLK_FREQ_OPT	20
+#define	 SARL_A370_TCLK_FREQ_OPT_MASK	0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+	{ .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+	{ .id = A370_CPU_TO_HCLK, .name = "hclk" },
+	{ .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+	16600000,
+	20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+	u8 tclk_freq_select = 0;
+
+	tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+			    SARL_A370_TCLK_FREQ_OPT_MASK);
+	return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+	400000000,
+	533000000,
+	667000000,
+	800000000,
+	1000000000,
+	1067000000,
+	1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+	u32 cpu_freq;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+			   SARL_A370_PCLK_FREQ_OPT_MASK);
+	if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+		pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+		cpu_freq = 0;
+	} else
+		cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+	return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 2}, {2, 2},
+	{1, 2}, {1, 2}, {1, 1}, {2, 3},
+	{0, 1}, {1, 2}, {2, 4}, {0, 1},
+	{1, 2}, {0, 1}, {0, 1}, {2, 2},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 6}, {2, 3},
+	{1, 3}, {1, 4}, {1, 2}, {2, 6},
+	{0, 1}, {1, 6}, {2, 10}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 2},
+	{2, 6}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 3}, {2, 3},
+	{1, 3}, {1, 2}, {1, 2}, {2, 6},
+	{0, 1}, {1, 3}, {2, 5}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+		SARL_A370_FAB_FREQ_OPT_MASK);
+
+	switch (id) {
+	case A370_CPU_TO_NBCLK:
+		*mult = a370_nbclk_ratios[opt][0];
+		*div = a370_nbclk_ratios[opt][1];
+		break;
+	case A370_CPU_TO_HCLK:
+		*mult = a370_hclk_ratios[opt][0];
+		*div = a370_hclk_ratios[opt][1];
+		break;
+	case A370_CPU_TO_DRAMCLK:
+		*mult = a370_dramclk_ratios[opt][0];
+		*div = a370_dramclk_ratios[opt][1];
+		break;
+	}
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+	.get_tclk_freq = a370_get_tclk_freq,
+	.get_cpu_freq = a370_get_cpu_freq,
+	.get_clk_ratio = a370_get_clk_ratio,
+	.ratios = a370_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+	       a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+	{ "audio", NULL, 0, 0 },
+	{ "pex0_en", NULL, 1, 0 },
+	{ "pex1_en", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex0", "pex0_en", 5, 0 },
+	{ "pex1", "pex1_en", 9, 0 },
+	{ "sata0", NULL, 15, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+	{ "sata1", NULL, 30, 0 },
+	{ }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+	       a370_clk_gating_init);


From jason at lakedaemon.net  Tue May 28 11:48:28 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 11:48:28 -0400
Subject: [PATCH 06/10] clk: mvebu: add Armada XP SoC-centric clock init
In-Reply-To: <1368234490-31416-7-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1368234490-31416-7-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130528154828.GW31290@titan.lakedaemon.net>

Sebastian, Thomas,

On Sat, May 11, 2013 at 03:08:06AM +0200, Sebastian Hesselbarth wrote:
> This is moving core clock and clock gating init for Armada XP to
> its own file and adds a Kconfig option. Also init functions are added
> and declared so they get called on of_clk_init.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  drivers/clk/mvebu/Kconfig     |    5 +
>  drivers/clk/mvebu/Makefile    |    1 +
>  drivers/clk/mvebu/armada-xp.c |  204 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 210 insertions(+)
>  create mode 100644 drivers/clk/mvebu/armada-xp.c

Here's the revised version after rebasing onto mvebu/pcie:

---->8------

commit b45bfc9e9893cf1dc80f5eef6b25d66713fbfeb5
Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date:   Sat May 11 03:08:06 2013 +0200

    clk: mvebu: add Armada XP SoC-centric clock init
    
    This is moving core clock and clock gating init for Armada XP to
    its own file and adds a Kconfig option. Also init functions are added
    and declared so they get called on of_clk_init.
    
    Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
    Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 1daf61e..8740d34 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -15,6 +15,11 @@ config ARMADA_370_CLK
 	select MVEBU_CLK_COMMON
 	select MVEBU_CLK_CPU
 
+config ARMADA_XP_CLK
+	bool
+	select MVEBU_CLK_COMMON
+	select MVEBU_CLK_CPU
+
 config DOVE_CLK
 	bool
 	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 367b72c..13f3d22 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MVEBU_CLK_CPU) 	+= clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_GATING) 	+= clk-gating-ctrl.o
 
 obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 0000000..13b62ce
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,210 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL				0	/* Low part [0:31] */
+#define	 SARL_AXP_PCLK_FREQ_OPT		21
+#define	 SARL_AXP_PCLK_FREQ_OPT_MASK	0x7
+#define	 SARL_AXP_FAB_FREQ_OPT		24
+#define	 SARL_AXP_FAB_FREQ_OPT_MASK	0xF
+#define SARH				4	/* High part [32:63] */
+#define	 SARH_AXP_PCLK_FREQ_OPT		(52-32)
+#define	 SARH_AXP_PCLK_FREQ_OPT_MASK	0x1
+#define	 SARH_AXP_PCLK_FREQ_OPT_SHIFT	3
+#define	 SARH_AXP_FAB_FREQ_OPT		(51-32)
+#define	 SARH_AXP_FAB_FREQ_OPT_MASK	0x1
+#define	 SARH_AXP_FAB_FREQ_OPT_SHIFT	4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+	{ .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+	{ .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+	{ .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+	return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+	1000000000,
+	1066000000,
+	1200000000,
+	1333000000,
+	1500000000,
+	1666000000,
+	1800000000,
+	2000000000,
+	667000000,
+	0,
+	800000000,
+	1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+	u32 cpu_freq;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+			   SARL_AXP_PCLK_FREQ_OPT_MASK);
+	/*
+	 * The upper bit is not contiguous to the other ones and
+	 * located in the high part of the SAR registers
+	 */
+	cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+	     SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+	if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+		pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+		cpu_freq = 0;
+	} else
+		cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+	return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 2}, {2, 2},
+	{1, 2}, {1, 2}, {1, 1}, {2, 3},
+	{0, 1}, {1, 2}, {2, 4}, {0, 1},
+	{1, 2}, {0, 1}, {0, 1}, {2, 2},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 6}, {2, 3},
+	{1, 3}, {1, 4}, {1, 2}, {2, 6},
+	{0, 1}, {1, 6}, {2, 10}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 2},
+	{2, 6}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+	{0, 1}, {1, 2}, {2, 3}, {2, 3},
+	{1, 3}, {1, 2}, {1, 2}, {2, 6},
+	{0, 1}, {1, 3}, {2, 5}, {0, 1},
+	{1, 4}, {0, 1}, {0, 1}, {2, 5},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{2, 3}, {0, 1}, {0, 1}, {0, 1},
+	{0, 1}, {0, 1}, {0, 1}, {1, 1},
+	{0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+	      SARL_AXP_FAB_FREQ_OPT_MASK);
+	/*
+	 * The upper bit is not contiguous to the other ones and
+	 * located in the high part of the SAR registers
+	 */
+	opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+		 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+	switch (id) {
+	case AXP_CPU_TO_NBCLK:
+		*mult = axp_nbclk_ratios[opt][0];
+		*div = axp_nbclk_ratios[opt][1];
+		break;
+	case AXP_CPU_TO_HCLK:
+		*mult = axp_hclk_ratios[opt][0];
+		*div = axp_hclk_ratios[opt][1];
+		break;
+	case AXP_CPU_TO_DRAMCLK:
+		*mult = axp_dramclk_ratios[opt][0];
+		*div = axp_dramclk_ratios[opt][1];
+		break;
+	}
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+	.get_tclk_freq = axp_get_tclk_freq,
+	.get_cpu_freq = axp_get_cpu_freq,
+	.get_clk_ratio = axp_get_clk_ratio,
+	.ratios = axp_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+	       axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+	{ "audio", NULL, 0, 0 },
+	{ "ge3", NULL, 1, 0 },
+	{ "ge2", NULL,  2, 0 },
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex00", NULL, 5, 0 },
+	{ "pex01", NULL, 6, 0 },
+	{ "pex02", NULL, 7, 0 },
+	{ "pex03", NULL, 8, 0 },
+	{ "pex10", NULL, 9, 0 },
+	{ "pex11", NULL, 10, 0 },
+	{ "pex12", NULL, 11, 0 },
+	{ "pex13", NULL, 12, 0 },
+	{ "bp", NULL, 13, 0 },
+	{ "sata0lnk", NULL, 14, 0 },
+	{ "sata0", "sata0lnk", 15, 0 },
+	{ "lcd", NULL, 16, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "usb0", NULL, 18, 0 },
+	{ "usb1", NULL, 19, 0 },
+	{ "usb2", NULL, 20, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ "crypto", NULL, 23, 0 },
+	{ "tdm", NULL, 25, 0 },
+	{ "pex20", NULL, 26, 0 },
+	{ "pex30", NULL, 27, 0 },
+	{ "xor1", NULL, 28, 0 },
+	{ "sata1lnk", NULL, 29, 0 },
+	{ "sata1", "sata1lnk", 30, 0 },
+	{ }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+	       axp_clk_gating_init);


From catalin.marinas at arm.com  Tue May 28 11:50:57 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 28 May 2013 16:50:57 +0100
Subject: [RFC] arm64: Add support to pass earlyprintk argument via
 device tree
In-Reply-To: <1369219713-18590-1-git-send-email-pranavkumar@linaro.org>
References: <1369219713-18590-1-git-send-email-pranavkumar@linaro.org>
Message-ID: <20130528155056.GE17912@arm.com>

On Wed, May 22, 2013 at 11:48:33AM +0100, Pranavkumar Sawargaonkar wrote:
> This patch adds support for defining and passing earlyprintk
> related information i.e. device and address information via
> device tree by adding it inside "chosen" node.
> 
> This will help user to just specify "earlyprintk" from bootargs
> without actually knowing the address and device to enable
> earlyprintk.
> 
> Mechanism:
> 
> One can just append earlyprintk=device-type,address (same as we pass
> through command line) in "/chosen" node to notify kernel which is the
> earlyprintk device and what is its address.

I think the idea is good but I would like to see some comments from
people more familiar with the DT.

> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -60,6 +60,9 @@ EXPORT_SYMBOL(processor_id);
>  unsigned int elf_hwcap __read_mostly;
>  EXPORT_SYMBOL_GPL(elf_hwcap);
>  
> +char *earlyprintk_dt_args;
> +EXPORT_SYMBOL_GPL(earlyprintk_dt_args);

Why exporting it? Would you expect this to be used from modules?

-- 
Catalin


From thomas.petazzoni at free-electrons.com  Tue May 28 11:53:43 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 May 2013 17:53:43 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130528154047.GT31290@titan.lakedaemon.net>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130528154047.GT31290@titan.lakedaemon.net>
Message-ID: <20130528175343.77c6353d@skate>

Dear Jason Cooper,

On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:

> In order to avoid losing changes between this series and mvebu/pcie,
> I've rebased this series on top of mvebu/pcie and incorporated the
> correct conflict resolution into this series.  See below...

Thanks!

> I'm posting the revised version as replies to patches 1, 5 and 6. Please
> let me know if I messed it up.  I'd like to send the PR for these
> shortly.

I had a quick look, and it looks good to me. Let me know to which
branch you've pushed this, and the merge order to follow to "rebuild"
something that works, and I'll try to find some time to test it for
real on hardware.

Thanks again!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sebastian.hesselbarth at gmail.com  Tue May 28 11:58:08 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 28 May 2013 17:58:08 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130528175343.77c6353d@skate>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130528154047.GT31290@titan.lakedaemon.net> <20130528175343.77c6353d@skate>
Message-ID: <51A4D410.6030307@gmail.com>

On 05/28/13 17:53, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
>> I'm posting the revised version as replies to patches 1, 5 and 6. Please
>> let me know if I messed it up.  I'd like to send the PR for these
>> shortly.
>
> I had a quick look, and it looks good to me. Let me know to which
> branch you've pushed this, and the merge order to follow to "rebuild"
> something that works, and I'll try to find some time to test it for
> real on hardware.

I also had a visual check of the files, especially clock_gating_descr.
Didn't find a typo. I will also compile and run on Dove and Kirkwood,
but I guess it should be fine.

Thanks for the effort!

Sebastian



From catalin.marinas at arm.com  Tue May 28 12:04:40 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 28 May 2013 17:04:40 +0100
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <20130528130502.GA28971@mudshark.cambridge.arm.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com>
Message-ID: <20130528160440.GF17912@arm.com>

On Tue, May 28, 2013 at 02:05:02PM +0100, Will Deacon wrote:
> On Tue, May 28, 2013 at 11:48:20AM +0100, Po-Yu Chuang wrote:
> > This bug was introduced in commit e651eab0.
> > Some v4/v5 platforms failed to boot due to this.
> > 
> > Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
> > ---
> >  arch/arm/mm/mmu.c |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> > index e0d8565..19a43f8 100644
> > --- a/arch/arm/mm/mmu.c
> > +++ b/arch/arm/mm/mmu.c
> > @@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
> >  			unsigned long end, phys_addr_t phys,
> >  			const struct mem_type *type)
> >  {
> > +	pmd_t *p = pmd;
> > +
> >  #ifndef CONFIG_ARM_LPAE
> >  	/*
> >  	 * In classic MMU format, puds and pmds are folded in to
> > @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
> >  		phys += SECTION_SIZE;
> >  	} while (pmd++, addr += SECTION_SIZE, addr != end);
> >  
> > -	flush_pmd_entry(pmd);
> > +	flush_pmd_entry(p);
> 
> Wait, shouldn't this flush be *inside* the loop anyway? Otherwise we just
> flush the cacheline containing the first pmd. The flushing code could also
> flush to PoU instead of PoC for UP ARMv7, but that's an unrelated optimisation.

With LPAE, map_init_section() is called once per section from
alloc_init_pmd(). The loop is there for classic MMU to allow setting two
pmd entries (maximum) and flush_pmd_entry() takes care of both (it
flushes a full cache line anyway).

-- 
Catalin


From hpa at zytor.com  Tue May 28 12:06:48 2013
From: hpa at zytor.com (H. Peter Anvin)
Date: Tue, 28 May 2013 09:06:48 -0700
Subject: [PATCH] arch: configuration, deleting 'CONFIG_BUG' since always
 need it.
In-Reply-To: <201305281743.52649.arnd@arndb.de>
References: <519DCBEF.3090208@asianux.com> <20130528081910.GA29557@gmail.com>
 <51A4C564.4040301@zytor.com> <201305281743.52649.arnd@arndb.de>
Message-ID: <51A4D618.3080208@zytor.com>

On 05/28/2013 08:43 AM, Arnd Bergmann wrote:
> 
> Right, that is what the patch I just posted does.
> 
> On a related note, I found that WARN_ON() can no longer be compiled
> out since there is already code that relies on the side-effects of
> the condition. I assume that was an intentional change I missed,
> since it used to be defined so that you could remove it completely.
> 

It is possible to define WARN_ON() as:

#define WARN_ON(x) ((void)(x))

... which preserves side effects.

	-hpa



From andy.shevchenko at gmail.com  Tue May 28 12:18:51 2013
From: andy.shevchenko at gmail.com (Andy Shevchenko)
Date: Tue, 28 May 2013 19:18:51 +0300
Subject: [PATCH -next] dmaengine: ste_dma40: fix error return code in
 d40_probe()
In-Reply-To: <CAPgLHd-Mw4MQwS8=p9+ZBHHehH7B-Hs49BqiUMrq-aV_5M4pQQ@mail.gmail.com>
References: <CAPgLHd-Mw4MQwS8=p9+ZBHHehH7B-Hs49BqiUMrq-aV_5M4pQQ@mail.gmail.com>
Message-ID: <CAHp75VfQwv1gCNX2iactEEMJxLgdcbnivebB5f-hSKYHcN8fOw@mail.gmail.com>

Have you check the ux500-dma40 branch?

https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-stericsson.git/log/?h=ux500-dma40

On Tue, May 28, 2013 at 12:06 PM, Wei Yongjun <weiyj.lk at gmail.com> wrote:
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>
> In many of the error handling case, the return value 'ret' not set
> and 0 will be return from d40_probe() even if error, but we should
> return a negative error code instead in those error handling case.
> This patch fixed them, and also removed useless variable 'err'.
>
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> ---
>  drivers/dma/ste_dma40.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 71bf4ec..cbf9c62 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -3474,7 +3474,6 @@ failure:
>
>  static int __init d40_probe(struct platform_device *pdev)
>  {
> -       int err;
>         int ret = -ENOENT;
>         struct d40_base *base;
>         struct resource *res = NULL;
> @@ -3576,6 +3575,7 @@ static int __init d40_probe(struct platform_device *pdev)
>                 if (IS_ERR(base->lcpa_regulator)) {
>                         d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
>                         base->lcpa_regulator = NULL;
> +                       ret = PTR_ERR(base->lcpa_regulator);
>                         goto failure;
>                 }
>
> @@ -3590,13 +3590,13 @@ static int __init d40_probe(struct platform_device *pdev)
>         }
>
>         base->initialized = true;
> -       err = d40_dmaengine_init(base, num_reserved_chans);
> -       if (err)
> +       ret = d40_dmaengine_init(base, num_reserved_chans);
> +       if (ret)
>                 goto failure;
>
>         base->dev->dma_parms = &base->dma_parms;
> -       err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
> -       if (err) {
> +       ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
> +       if (ret) {
>                 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
>                 goto failure;
>         }
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/



-- 
With Best Regards,
Andy Shevchenko


From balbi at ti.com  Tue May 28 12:24:15 2013
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 28 May 2013 19:24:15 +0300
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <Pine.LNX.4.44L0.1305131012090.1389-100000@iolanthe.rowland.org>
References: <1368424303-10629-5-git-send-email-chao.xie@marvell.com>
 <Pine.LNX.4.44L0.1305131012090.1389-100000@iolanthe.rowland.org>
Message-ID: <20130528162415.GA28253@arwen.pp.htv.fi>

Hi,

On Mon, May 13, 2013 at 10:13:44AM -0400, Alan Stern wrote:
> On Mon, 13 May 2013, Chao Xie wrote:
> 
> > Originaly, ehci driver will call the callbacks in platform data
> > for PHY initialization and shut down.
> > With PHY driver, it will call the APIs provided by PHY driver
> > for PHY initialization and shutdown. It removes the callbacks
> > in platform data, and at same time it removes one block in the
> > way of enabling device tree for ehci driver.
> 
> I wonder if this is the sort of thing that should be handled in 
> ehci-hcd.c rather than in all the different platform glue drivers.
> 
> Felipe, what do you think?  Are the required actions now sufficiently 
> generic that a single source file can take care of them?

Sorry for the delay, was on business trip and now on vacations. Anyway,
I agree with you. Our PHY layer should be generic enough that it should
be usable by ehci-hcd itself. If we have any missing method, let's add
it generically.

cheers

ps: dropping this from my queue for now.

-- 
balbi
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From balbi at ti.com  Tue May 28 12:27:15 2013
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 28 May 2013 19:27:15 +0300
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
Message-ID: <20130528162715.GB28253@arwen.pp.htv.fi>

Hi,

On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > For all ux500 based platforms the maximum number of end-points are used.
> > Move this knowledge into the driver so we can relinquish the burden from
> > platform data. This also removes quite a bit of complexity from the driver
> > and will aid us when we come to enable the driver for Device Tree.
> >
> > Cc: Felipe Balbi <balbi at ti.com>
> > Cc: linux-usb at vger.kernel.org
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> I guess this stuff is dependent on the stuff Fabio has recently sent to
> Felipe for the ux500 musb DMA so these musb patches should
> primarily go through his tree.
> 
> It seems like the later changes to the platform code
> (arch/arm/mach-ux500) may be sufficiently orthogonal
> so it can be done out-of-order?
> 
> I can't merge any of this without Felipes ACKs in any
> case.

Do you want to take this yourself ? I haven't fully read the series yet,
but seems like this depends on the rest of the series. If you want to
take it, let me know I can ack the patches as soon as I'm done
reviewing.

-- 
balbi
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From balbi at ti.com  Tue May 28 12:35:48 2013
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 28 May 2013 19:35:48 +0300
Subject: MUSB multiplatform work?
In-Reply-To: <201305271702.09203.arnd@arndb.de>
References: <201305271702.09203.arnd@arndb.de>
Message-ID: <20130528163548.GC28253@arwen.pp.htv.fi>

Hi,

On Mon, May 27, 2013 at 05:02:09PM +0200, Arnd Bergmann wrote:
> Hi Felipe,
> 
> We've gone through remaining work items for getting the ARM kernel
> to full multiplatform support again, and MUSB came up. I'm sure you
> have your own thoughts on this, but I'd like to know if there is
> already a plan in place.
> 
> From what I can see, the driver in PIO mode should almost work
> on multiple platforms, but there are a couple of compile-time
> dependencies in it that need to be turned into run-time conditionals.
> In particular the TUSB version seem sufficiently different that
> it needs some extra work to be a true run-time option.

yeah, TUSB layer is quite messy, all the others should be doable though.

> The DMA support as far as I can tell has never been intended to
> be usable in a multiplatform setup, but that also seems doable.

we're looking into dmaengine for that but will take a lot of work to
have something usable.

> Looking just at the #ifdef statements in the driver, I found
> that the following things need to be addressed:
> 
> * abstract musb_write_fifo and musb_read_fifo into callbacks
> * move fifo_mode setting into glue driver for runtime selection

for the fifo mode, I'd rather detect the size of the internal fifo and
configure it dynamically based on that plus number of endpoints
configured in the IP.

> * turn TUSB compile-time switches into run-time conditionals
> * turn musb_ep_select into run-time switch
> * make is_dma_capable/is_cppi_enabled/tusb_dma_omap run-time conditionals

those can be remove, actually. Back at Nokia we did a huge cleanup on
the DMA programming part, it can be very simple with no ifdefs at all,
just needs someone to put the work and test on all platforms.

> * abtract dma_controller_create/destroy interface
> 
> Aside from this, a recent discussion with Maxime has brought up
> that the Allwinner A1x platform (mach-sunxi) contains an MUSB variant
> that is currently used with an independently implemented device driver,
> see https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/drivers/usb/sun5i_usb
> I wonder if you have any insight on how that can be integrated into
> musb, or whether it is likely to be a compatible version to start with.

just write a glue layer, should be as easy as that :-)

-- 
balbi
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From lee.jones at linaro.org  Tue May 28 12:48:03 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 28 May 2013 17:48:03 +0100
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <20130528162715.GB28253@arwen.pp.htv.fi>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
 <20130528162715.GB28253@arwen.pp.htv.fi>
Message-ID: <20130528164803.GA3012@gmail.com>

Hi Felipe

> > > For all ux500 based platforms the maximum number of end-points are used.
> > > Move this knowledge into the driver so we can relinquish the burden from
> > > platform data. This also removes quite a bit of complexity from the driver
> > > and will aid us when we come to enable the driver for Device Tree.
> > >
> > > Cc: Felipe Balbi <balbi at ti.com>
> > > Cc: linux-usb at vger.kernel.org
> > > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > > Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > 
> > I guess this stuff is dependent on the stuff Fabio has recently sent to
> > Felipe for the ux500 musb DMA so these musb patches should
> > primarily go through his tree.
> > 
> > It seems like the later changes to the platform code
> > (arch/arm/mach-ux500) may be sufficiently orthogonal
> > so it can be done out-of-order?
> > 
> > I can't merge any of this without Felipes ACKs in any
> > case.
> 
> Do you want to take this yourself ? I haven't fully read the series yet,
> but seems like this depends on the rest of the series. If you want to
> take it, let me know I can ack the patches as soon as I'm done
> reviewing.

Yes that would be ideal, if you wouldn't mind.

Kind regards,
Lee

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From daniel at ffwll.ch  Tue May 28 12:49:45 2013
From: daniel at ffwll.ch (Daniel Vetter)
Date: Tue, 28 May 2013 18:49:45 +0200
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <00de01ce5bb2$aa7c6b30$ff754190$%dae@samsung.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
 <CAF6AEGv6E38bwszcFV3sV3yMPjD9BkLM4asEscJ8Jt5z+duxTQ@mail.gmail.com>
 <00de01ce5bb2$aa7c6b30$ff754190$%dae@samsung.com>
Message-ID: <CAKMK7uHf0G4-3YU6mouUTf4n50Q+viNAA13BzSLDWjPNWLwJVQ@mail.gmail.com>

On Tue, May 28, 2013 at 4:50 PM, Inki Dae <inki.dae at samsung.com> wrote:
> I think I already used reservation stuff any time in that way except
> ww-mutex. And I'm not sure that embedded system really needs ww-mutex. If
> there is any case,
> could you tell me the case? I really need more advice and understanding :)

If you have only one driver, you can get away without ww_mutex.
drm/i915 does it, all buffer state is protected by dev->struct_mutex.
But as soon as you have multiple drivers sharing buffers with dma_buf
things will blow up.

Yep, current prime is broken and can lead to deadlocks.

In practice it doesn't (yet) matter since only the X server does the
sharing dance, and that one's single-threaded. Now you can claim that
since you have all buffers pinned in embedded gfx anyway, you don't
care. But both in desktop gfx and embedded gfx the real fun starts
once you put fences into the mix and link them up with buffers, then
every command submission risks that deadlock. Furthermore you can get
unlucky and construct a circle of fences waiting on each another (only
though if the fence singalling fires off the next batchbuffer
asynchronously).

To prevent such deadlocks you _absolutely_ need to lock _all_ buffers
that take part in a command submission at once. To do that you either
need a global lock (ugh) or ww_mutexes.

So ww_mutexes are the fundamental ingredient of all this, if you don't
see why you need them then everything piled on top is broken. I think
until you've understood why exactly we need ww_mutexes there's not
much point in discussing the finer issues of fences, reservation
objects and how to integrate it with dma_bufs exactly.

I'll try to clarify the motivating example in the ww_mutex
documentation a bit, but I dunno how else I could explain this ...

Yours, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


From pranavkumar at linaro.org  Tue May 28 12:52:53 2013
From: pranavkumar at linaro.org (Pranavkumar Sawargaonkar)
Date: Tue, 28 May 2013 22:22:53 +0530
Subject: [RFC] arm64: Add support to pass earlyprintk argument via device
 tree
In-Reply-To: <20130528155056.GE17912@arm.com>
References: <1369219713-18590-1-git-send-email-pranavkumar@linaro.org>
 <20130528155056.GE17912@arm.com>
Message-ID: <CAAHg+HixA9v=f4gEEU9nJShXYowD1TUBF8QcXoQvF=jXmBn1KA@mail.gmail.com>

Hi Catalin,

On 28 May 2013 21:20, Catalin Marinas <catalin.marinas at arm.com> wrote:
> On Wed, May 22, 2013 at 11:48:33AM +0100, Pranavkumar Sawargaonkar wrote:
>> This patch adds support for defining and passing earlyprintk
>> related information i.e. device and address information via
>> device tree by adding it inside "chosen" node.
>>
>> This will help user to just specify "earlyprintk" from bootargs
>> without actually knowing the address and device to enable
>> earlyprintk.
>>
>> Mechanism:
>>
>> One can just append earlyprintk=device-type,address (same as we pass
>> through command line) in "/chosen" node to notify kernel which is the
>> earlyprintk device and what is its address.
>
> I think the idea is good but I would like to see some comments from
> people more familiar with the DT.
>
>> --- a/arch/arm64/kernel/setup.c
>> +++ b/arch/arm64/kernel/setup.c
>> @@ -60,6 +60,9 @@ EXPORT_SYMBOL(processor_id);
>>  unsigned int elf_hwcap __read_mostly;
>>  EXPORT_SYMBOL_GPL(elf_hwcap);
>>
>> +char *earlyprintk_dt_args;
>> +EXPORT_SYMBOL_GPL(earlyprintk_dt_args);
>
> Why exporting it? Would you expect this to be used from modules?

Actually i will remove it, it is not really going to be used by modules.
Also i have externed this variable(char *earlyprintk_dt_arg ) in
early_pritnk.c file
just because of not finding proper header file, really like to move
that to some header...


>
> --
> Catalin

Thanks,
Pranav


From jason at lakedaemon.net  Tue May 28 12:54:01 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 12:54:01 -0400
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130528175343.77c6353d@skate>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130528154047.GT31290@titan.lakedaemon.net>
 <20130528175343.77c6353d@skate>
Message-ID: <20130528165401.GX31290@titan.lakedaemon.net>

On Tue, May 28, 2013 at 05:53:43PM +0200, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> > I'm posting the revised version as replies to patches 1, 5 and 6. Please
> > let me know if I messed it up.  I'd like to send the PR for these
> > shortly.
> 
> I had a quick look, and it looks good to me. Let me know to which
> branch you've pushed this, and the merge order to follow to "rebuild"
> something that works, and I'll try to find some time to test it for
> real on hardware.

$ git checkout v3.10-rc3
$ git merge mvebu/of_pci
$ git merge mvebu/pcie
$ git merge mvebu/seb_clk

test away!

thx,

Jason.


From catalin.marinas at arm.com  Tue May 28 13:02:19 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 28 May 2013 18:02:19 +0100
Subject: [PATCH] arm64: compiling issue for allmodconfig, need
 "asm/parport.h" by "drivers/parport/parport_pc.c"
In-Reply-To: <519C7484.9020709@asianux.com>
References: <5177551D.8090007@asianux.com> <20130424082237.GA23397@arm.com>
 <5177B1F0.10106@asianux.com>
 <20130424102327.GF21850@mudshark.cambridge.arm.com>
 <5177BAD0.9000500@asianux.com> <20130424110511.GK23397@arm.com>
 <5199A453.4080402@asianux.com> <20130521131734.GD27002@arm.com>
 <519C1539.10908@asianux.com> <519C7484.9020709@asianux.com>
Message-ID: <20130528170219.GI17912@arm.com>

On Wed, May 22, 2013 at 08:32:20AM +0100, Chen Gang wrote:
> On 05/22/2013 08:45 AM, Chen Gang wrote:
> > On 05/21/2013 09:17 PM, Catalin Marinas wrote:
> >> On Mon, May 20, 2013 at 05:19:31AM +0100, Chen Gang wrote:
> >>>
> >>> Need add the default file in 'asm/Kbuild' just like arm has done.
> >>>
> >>> The build command is:
> >>>   make EXTRA_CFLAGS=-W ARCH=arm64 allmodconfig
> >>>   make EXTRA_CFLAGS=-W ARCH=arm64 menuconfig
> >>>     set "aarch64-linux-gnu-" as cross compiling prefix.
> >>>   make EXTRA_CFLAGS=-W ARCH=arm64
> >>>
> >>> The related error:
> >>>   drivers/parport/parport_pc.c:67:25: fatal error: asm/parport.h: No such file or directory
> >>
> >> As I don't see when we'd need this driver, you can probably change the
> >> Kconfig entry (similar to the VGA_CONSOLE one).
> >>
> 
> After check the Kconfig in drivers, we can find quite a few using long
> list args which related with ARCH.
> 
> And they are not only depend on ARCHs, but also depend on another
> things (e.g. VGA_CONSOL also depend on !4xx && !8xx, and another
> combinations).

Given this dependency is on the negation of that symbol, you just remove
it and have a "depends on HAVE_VGA_CONSOLE". The few architectures that
need it will have to define it (X86, ARM with a few configurations).

> We also can find another long list for depend on, but not related with
> ARCH.
> 
> They seems not quit difficult for reading (in fact, if we separate them
> into pieces and let them spread into another areas, the reader will not
> see the whole dependency clearly)
> 
> For fixing bug, better as local as possible, as independent as possible,
> it will be OK if only add !ARM64 for PARPORT_PC depend on, and it has
> no any negative effect. But if we define CONFIG_HAVE_*, we have to let
> it related with multiple platforms.
> 
> For design: if can bear current design, better not to touch it, I think
> current design is still sustainable, and not complex for understanding,
> so not need redesign.

We usually clean some of these as we hit them, otherwise people forget
about the clean-up later ;).

-- 
Catalin


From swarren at wwwdotorg.org  Tue May 28 13:15:25 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 11:15:25 -0600
Subject: [GIT PULL] ARM: tegra: DT-related fixes needed by the USB tree
In-Reply-To: <1368831045-19105-1-git-send-email-swarren@wwwdotorg.org>
References: <1368831045-19105-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <51A4E62D.7020206@wwwdotorg.org>

On 05/17/2013 04:50 PM, Stephen Warren wrote:
> Felipe, (and Alan, Greg),
> 
> These are the changes from the Tegra tree that need to be merged
> before the Tegra USB driver patches 4-8 from Venu can be applied. Recall
> that we had previously agreed on this approach for v3.9, but Venu's
> patches didn't end up being ready until now, unfortunately. I note
> that Venu's patches affect both the Tegra USB and PHY drivers.

Felipe, do you know when you plan to pull this into the USB tree, and
apply Venu's patches? Thanks.


From arnd at arndb.de  Tue May 28 13:20:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 19:20:37 +0200
Subject: [PATCH] arch: configuration,
 deleting 'CONFIG_BUG' since always need it.
In-Reply-To: <51A4D618.3080208@zytor.com>
References: <519DCBEF.3090208@asianux.com> <201305281743.52649.arnd@arndb.de>
 <51A4D618.3080208@zytor.com>
Message-ID: <201305281920.37452.arnd@arndb.de>

On Tuesday 28 May 2013, H. Peter Anvin wrote:
> On 05/28/2013 08:43 AM, Arnd Bergmann wrote:
> > 
> > Right, that is what the patch I just posted does.
> > 
> > On a related note, I found that WARN_ON() can no longer be compiled
> > out since there is already code that relies on the side-effects of
> > the condition. I assume that was an intentional change I missed,
> > since it used to be defined so that you could remove it completely.
> > 
> 
> It is possible to define WARN_ON() as:
> 
> #define WARN_ON(x) ((void)(x))
> 
> ... which preserves side effects.

Yes, actually the return value has to be maintained as well.
The current (!CONFIG_BUG) default implementation is

#define WARN_ON(condition) ({                                           \
        int __ret_warn_on = !!(condition);                              \
        unlikely(__ret_warn_on);                                        \
})

which seems fine.

#define WARN_ON(condition) unlikely(!!(condition))

is probably just as good.

	Arnd


From swarren at wwwdotorg.org  Tue May 28 13:26:12 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 11:26:12 -0600
Subject: [PATCH] ARM: tegra: rebuild tegra_defconfig
Message-ID: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

This simply rebuilds tegra_defconfig on top of next-20130520. As such, it
should introduce no changes; simply moving entries around due to Kconfig
ordering changes. The apparent exceptions are:

AUTO_ZRELADDR: Selected by ARM multi-platform support.
MTD_CHAR: Removed in Kconfig.

This should make it easier to create future defconfig patches on top of
linux-next, since all the extraneous diffs have been removed. It also
makes it more likely that once 3.12 comes around, this defconfig will
already match what's required there.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/configs/tegra_defconfig |   14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 4dbcd9f..e45fe32 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -21,8 +21,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_TEGRA=y
 CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
@@ -36,7 +36,6 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -81,7 +80,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_CMA=y
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -105,8 +103,8 @@ CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TEGRA=y
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_TEGRA=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
@@ -134,11 +132,11 @@ CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
-CONFIG_MFD_TPS6586X=y
-CONFIG_MFD_TPS65910=y
 CONFIG_MFD_MAX8907=y
-CONFIG_MFD_TPS65090=y
 CONFIG_MFD_PALMAS=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
@@ -211,7 +209,6 @@ CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
-CONFIG_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
@@ -221,6 +218,7 @@ CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_AK8975=y
 CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
-- 
1.7.10.4



From arnd at arndb.de  Tue May 28 13:26:47 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 19:26:47 +0200
Subject: [PATCH v2 2/5] irqchip: mmp: support irqchip
In-Reply-To: <1369707707-30295-3-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
 <1369707707-30295-3-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <201305281926.47790.arnd@arndb.de>

On Tuesday 28 May 2013, Haojian Zhuang wrote:
>         icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
>                                                    &mmp_irq_domain_ops,
>                                                    &icu_data[0]);

Is there anything stopping you from converting to the linear domain now?

> +IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
> +IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
> +IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);

Please put each line directly after the function it refers to,
similar to how we do it for EXPORT_SYMBOL.

	Arnd


From arnd at arndb.de  Tue May 28 13:32:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 28 May 2013 19:32:44 +0200
Subject: [PATCH v2 4/5] ARM: mmp: move irqs head file
In-Reply-To: <1369707707-30295-5-git-send-email-haojian.zhuang@gmail.com>
References: <1369707707-30295-1-git-send-email-haojian.zhuang@gmail.com>
 <1369707707-30295-5-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <201305281932.44663.arnd@arndb.de>

On Tuesday 28 May 2013, Haojian Zhuang wrote:
> Since irq-mmp driver includes <mach/irqs.h>, it blocks the multiple
> platform build. So move the head file into include/linux/irqchip/
> directory.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>

I disagree with simply moving the file. Let's check first what is actually
needed from it.

>  arch/arm/mach-mmp/aspenite.c                                         | 2 +-
>  arch/arm/mach-mmp/avengers_lite.c                                    | 2 +-
>  arch/arm/mach-mmp/brownstone.c                                       | 2 +-
>  arch/arm/mach-mmp/devices.c                                          | 2 +-
>  arch/arm/mach-mmp/flint.c                                            | 2 +-
>  arch/arm/mach-mmp/gplugd.c                                           | 2 +-
>  arch/arm/mach-mmp/jasper.c                                           | 2 +-
>  arch/arm/mach-mmp/mmp2.c                                             | 2 +-
>  arch/arm/mach-mmp/pm-mmp2.c                                          | 2 +-
>  arch/arm/mach-mmp/pm-pxa910.c                                        | 2 +-
>  arch/arm/mach-mmp/pxa168.c                                           | 2 +-
>  arch/arm/mach-mmp/pxa910.c                                           | 2 +-
>  arch/arm/mach-mmp/tavorevb.c                                         | 2 +-
>  arch/arm/mach-mmp/teton_bga.c                                        | 2 +-
>  arch/arm/mach-mmp/time.c                                             | 2 +-
>  arch/arm/mach-mmp/ttc_dkb.c                                          | 2 +-
>  drivers/gpio/gpio-pxa.c                                              | 3 +--
>  drivers/irqchip/irq-mmp.c                                            | 3 +--
>  arch/arm/mach-mmp/include/mach/irqs.h => include/linux/irqchip/mmp.h | 0
>  19 files changed, 18 insertions(+), 20 deletions(-)
>  rename arch/arm/mach-mmp/include/mach/irqs.h => include/linux/irqchip/mmp.h (100%)

My guess is that the long list of IRQ numbers is only needed for legacy
board files. That list would better be put into arch/arm/mach-mmp/irqs.h.

Try to move as much as you can from the include/linux/irqchip/mmp.h
file into that new header. Some constants (e.g irq base numbers
and mmio addresses) can be passed into the icu_init_irq/mmp2_init_icu
functions as arguments so you don't need them in the global header.

	Arnd


From balbi at ti.com  Tue May 28 13:36:37 2013
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 28 May 2013 20:36:37 +0300
Subject: [PATCH v2] usb: musb: fix clock naming
In-Reply-To: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>
References: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>
Message-ID: <20130528173637.GE15794@arwen.pp.htv.fi>

On Tue, May 28, 2013 at 09:21:01AM +0200, yegorslists at googlemail.com wrote:
> From: Yegor Yefremov <yegorslists at googlemail.com>
> 
> 'ick' was changed to 'hsotgusb_ick'
> 'fck' was changed to 'hsotgusb_fck'
> 
> Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
> Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>

NAK. Fix your clock data.

-- 
balbi
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From swarren at wwwdotorg.org  Tue May 28 13:43:51 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 11:43:51 -0600
Subject: [PATCH] ARM: tegra: add audio-related nodes to Tegra114 DT
Message-ID: <1369763031-13687-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Add nodes for the Tegra114 AHUB and I2S controllers.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   71 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 2eab52e..4ce77ba 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -327,6 +327,77 @@
 		nvidia,ahb = <&ahb>;
 	};
 
+	ahub {
+		compatible = "nvidia,tegra114-ahub";
+		reg = <0x70080000 0x200>,
+		      <0x70080200 0x100>,
+		      <0x70081000 0x200>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
+			<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
+			<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
+			<&apbdma 29>;
+		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+			 <&tegra_car TEGRA114_CLK_APBIF>,
+			 <&tegra_car TEGRA114_CLK_I2S0>,
+			 <&tegra_car TEGRA114_CLK_I2S1>,
+			 <&tegra_car TEGRA114_CLK_I2S2>,
+			 <&tegra_car TEGRA114_CLK_I2S3>,
+			 <&tegra_car TEGRA114_CLK_I2S4>,
+			 <&tegra_car TEGRA114_CLK_DAM0>,
+			 <&tegra_car TEGRA114_CLK_DAM1>,
+			 <&tegra_car TEGRA114_CLK_DAM2>,
+			 <&tegra_car TEGRA114_CLK_SPDIF_IN>,
+			 <&tegra_car TEGRA114_CLK_AMX>,
+			 <&tegra_car TEGRA114_CLK_ADX>;
+		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif_in", "amx", "adx";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		tegra_i2s0: i2s at 70080300 {
+			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+			reg = <0x70080300 0x100>;
+			nvidia,ahub-cif-ids = <4 4>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+			status = "disabled";
+		};
+
+		tegra_i2s1: i2s at 70080400 {
+			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+			reg = <0x70080400 0x100>;
+			nvidia,ahub-cif-ids = <5 5>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+			status = "disabled";
+		};
+
+		tegra_i2s2: i2s at 70080500 {
+			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+			reg = <0x70080500 0x100>;
+			nvidia,ahub-cif-ids = <6 6>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+			status = "disabled";
+		};
+
+		tegra_i2s3: i2s at 70080600 {
+			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+			reg = <0x70080600 0x100>;
+			nvidia,ahub-cif-ids = <7 7>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+			status = "disabled";
+		};
+
+		tegra_i2s4: i2s at 70080700 {
+			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+			reg = <0x70080700 0x100>;
+			nvidia,ahub-cif-ids = <8 8>;
+			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+			status = "disabled";
+		};
+	};
+
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-- 
1.7.10.4



From balbi at ti.com  Tue May 28 13:47:04 2013
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 28 May 2013 20:47:04 +0300
Subject: [GIT PULL] ARM: tegra: DT-related fixes needed by the USB tree
In-Reply-To: <51A4E62D.7020206@wwwdotorg.org>
References: <1368831045-19105-1-git-send-email-swarren@wwwdotorg.org>
 <51A4E62D.7020206@wwwdotorg.org>
Message-ID: <20130528174704.GH15794@arwen.pp.htv.fi>

On Tue, May 28, 2013 at 11:15:25AM -0600, Stephen Warren wrote:
> On 05/17/2013 04:50 PM, Stephen Warren wrote:
> > Felipe, (and Alan, Greg),
> > 
> > These are the changes from the Tegra tree that need to be merged
> > before the Tegra USB driver patches 4-8 from Venu can be applied. Recall
> > that we had previously agreed on this approach for v3.9, but Venu's
> > patches didn't end up being ready until now, unfortunately. I note
> > that Venu's patches affect both the Tegra USB and PHY drivers.
> 
> Felipe, do you know when you plan to pull this into the USB tree, and
> apply Venu's patches? Thanks.

got 35 commits testing right now. This pull is in my list for tomorrow.

sorry for the delay, have been on a trip for the last 3 weeks and now
I'm catching up with emails during my vacations (next 2 weeks).

-- 
balbi
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From nico at fluxnic.net  Tue May 28 13:52:27 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 28 May 2013 13:52:27 -0400 (EDT)
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130528095528.GA14329@arm.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
 <20130528095528.GA14329@arm.com>
Message-ID: <alpine.LFD.2.03.1305281340240.1918@syhkavp.arg>

On Tue, 28 May 2013, Catalin Marinas wrote:

> On Sat, May 25, 2013 at 04:53:19AM +0100, Nicolas Pitre wrote:
> > On Thu, 23 May 2013, Catalin Marinas wrote:
> > 
> > > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > > twice. I don't think we should remove the cache flushing in
> > > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > > don't work together).
> > 
> > VIVT and highmem do work together.  Highmem for ARM was in fact 
> > developed on such a platform.
> 
> Thanks for confirming. Do you remember why kunmap() doesn't (need to)
> flush the cache alias (for VIVT)? Or if it does, where?

kunmap() calls kunmap_high() which actually does not unmap anything but 
only decrement a use count.  The page is kept around in case it is 
kmap()'d again, in which case the kmap() will be almost free and the 
page still warm.

It is only when the kmap() for a new page runs out of free pkmap  
entries that the unused but still mapped pages are unmapped.  This 
unmapping is done in flush_all_zero_pkmaps() where all the unused pages 
are all unmapped at once.  The cache for all those pages is flushed with 
flush_cache_kmaps() which on ARM maps to flush_cache_all() when the 
cache is VIVT.


Nicolas


From stefano.stabellini at eu.citrix.com  Tue May 28 13:53:24 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 18:53:24 +0100
Subject: [PATCH v4 0/4] xen/arm: CONFIG_PARAVIRT and stolen ticks
 accounting
Message-ID: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>

Hi all,
this patch series introduces stolen ticks accounting for Xen on ARM.
Stolen ticks are clocksource ticks that have been "stolen" from the cpu,
typically because Linux is running in a virtual machine and the vcpu has
been descheduled.
To account for these ticks we introduce CONFIG_PARAVIRT and pv_time_ops
so that we can make use of:

kernel/sched/cputime.c:steal_account_process_tick



Stefano Stabellini (4):
      xen: move xen_setup_runstate_info and get_runstate_snapshot to drivers/xen/time.c
      kernel: missing include in cputime.c
      arm: introduce CONFIG_PARAVIRT, PARAVIRT_TIME_ACCOUNTING and pv_time_ops
      xen/arm: account for stolen ticks

 arch/arm/Kconfig                |   20 +++++++++
 arch/arm/include/asm/paravirt.h |   19 ++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   25 +++++++++++
 arch/arm/xen/enlighten.c        |   21 +++++++++
 arch/ia64/xen/time.c            |   48 +++------------------
 arch/x86/xen/time.c             |   76 +--------------------------------
 drivers/xen/Makefile            |    2 +-
 drivers/xen/time.c              |   91 +++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h           |    5 ++
 kernel/sched/cputime.c          |    1 +
 11 files changed, 191 insertions(+), 118 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c
 create mode 100644 drivers/xen/time.c


git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_4

Cheers,

Stefano


From stefano.stabellini at eu.citrix.com  Tue May 28 13:54:30 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 18:54:30 +0100
Subject: [PATCH v4 2/4] kernel: missing include in cputime.c
In-Reply-To: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
Message-ID: <1369763672-12919-2-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: mingo at redhat.com
CC: peterz at infradead.org
---
 kernel/sched/cputime.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
index cc2dc3ee..a5d1a9b 100644
--- a/kernel/sched/cputime.c
+++ b/kernel/sched/cputime.c
@@ -5,6 +5,7 @@
 #include <linux/static_key.h>
 #include <linux/context_tracking.h>
 #include "sched.h"
+#include <asm/paravirt.h>
 
 
 #ifdef CONFIG_IRQ_TIME_ACCOUNTING
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Tue May 28 13:54:32 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 18:54:32 +0100
Subject: [PATCH v4 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
Message-ID: <1369763672-12919-4-git-send-email-stefano.stabellini@eu.citrix.com>

Register the runstate_memory_area with the hypervisor.
Use pv_time_ops.steal_clock to account for stolen ticks.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>


Changes in v4:
- don't use paravirt_steal_rq_enabled: we do not support retrieving
stolen ticks for vcpus other than one we are running on.

Changes in v3:
- use BUG_ON and smp_processor_id.
---
 arch/arm/xen/enlighten.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 13609e0..49839d8 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -14,7 +14,10 @@
 #include <xen/xen-ops.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <asm/arch_timer.h>
 #include <asm/system_misc.h>
+#include <asm/paravirt.h>
+#include <linux/jump_label.h>
 #include <linux/interrupt.h>
 #include <linux/irqreturn.h>
 #include <linux/module.h>
@@ -152,6 +155,19 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
 }
 EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 
+unsigned long long xen_stolen_accounting(int cpu)
+{
+	struct vcpu_runstate_info state;
+
+	BUG_ON(cpu != smp_processor_id());
+
+	xen_get_runstate_snapshot(&state);
+
+	WARN_ON(state.state != RUNSTATE_running);
+
+	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
+}
+
 static void __init xen_percpu_init(void *unused)
 {
 	struct vcpu_register_vcpu_info info;
@@ -169,6 +185,8 @@ static void __init xen_percpu_init(void *unused)
 	BUG_ON(err);
 	per_cpu(xen_vcpu, cpu) = vcpup;
 
+	xen_setup_runstate_info(cpu);
+
 	enable_percpu_irq(xen_events_irq, 0);
 }
 
@@ -300,6 +318,9 @@ static int __init xen_init_events(void)
 
 	on_each_cpu(xen_percpu_init, NULL, 0);
 
+	pv_time_ops.steal_clock = xen_stolen_accounting;
+	static_key_slow_inc(&paravirt_steal_enabled);
+
 	return 0;
 }
 postcore_initcall(xen_init_events);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Tue May 28 13:54:29 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 18:54:29 +0100
Subject: [PATCH v4 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
Message-ID: <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell at citrix.com>
CC: konrad.wilk at oracle.com

Changes in v2:
- leave do_stolen_accounting in arch/x86/xen/time.c;
- use the new common functions in arch/ia64/xen/time.c.
---
 arch/ia64/xen/time.c  |   48 +++----------------------
 arch/x86/xen/time.c   |   76 +----------------------------------------
 drivers/xen/Makefile  |    2 +-
 drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h |    5 +++
 5 files changed, 104 insertions(+), 118 deletions(-)
 create mode 100644 drivers/xen/time.c

diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
index 1f8244a..79a0b8c 100644
--- a/arch/ia64/xen/time.c
+++ b/arch/ia64/xen/time.c
@@ -34,53 +34,17 @@
 
 #include "../kernel/fsyscall_gtod_data.h"
 
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
 static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
 static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
 
 /* taken from i386/kernel/time-xen.c */
 static void xen_init_missing_ticks_accounting(int cpu)
 {
-	struct vcpu_register_runstate_memory_area area;
-	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
-	int rc;
+	xen_setup_runstate_info(&runstate);
 
-	memset(runstate, 0, sizeof(*runstate));
-
-	area.addr.v = runstate;
-	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
-				&area);
-	WARN_ON(rc && rc != -ENOSYS);
-
-	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
-	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
-					    + runstate->time[RUNSTATE_offline];
-}
-
-/*
- * Runstate accounting
- */
-/* stolen from arch/x86/xen/time.c */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = state->state_entry_time;
-		rmb();
-		*res = *state;
-		rmb();
-	} while (state->state_entry_time != state_time);
+	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
+	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
+					    + runstate.time[RUNSTATE_offline];
 }
 
 #define NS_PER_TICK (1000000000LL/HZ)
@@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
 	struct vcpu_runstate_info runstate;
 	struct task_struct *p = current;
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	/*
 	 * Check for vcpu migration effect
@@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
 	 */
 	now = ia64_native_sched_clock();
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	WARN_ON(runstate.state != RUNSTATE_running);
 
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 3d88bfd..c0ca15e 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -30,9 +30,6 @@
 #define TIMER_SLOP	100000
 #define NS_PER_TICK	(1000000000LL / HZ)
 
-/* runstate info updated by Xen */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
-
 /* snapshots of runstate info */
 static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 
@@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 static DEFINE_PER_CPU(u64, xen_residual_stolen);
 static DEFINE_PER_CPU(u64, xen_residual_blocked);
 
-/* return an consistent snapshot of 64-bit time/counter value */
-static u64 get64(const u64 *p)
-{
-	u64 ret;
-
-	if (BITS_PER_LONG < 64) {
-		u32 *p32 = (u32 *)p;
-		u32 h, l;
-
-		/*
-		 * Read high then low, and then make sure high is
-		 * still the same; this will only loop if low wraps
-		 * and carries into high.
-		 * XXX some clean way to make this endian-proof?
-		 */
-		do {
-			h = p32[1];
-			barrier();
-			l = p32[0];
-			barrier();
-		} while (p32[1] != h);
-
-		ret = (((u64)h) << 32) | l;
-	} else
-		ret = *p;
-
-	return ret;
-}
-
-/*
- * Runstate accounting
- */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = get64(&state->state_entry_time);
-		barrier();
-		*res = *state;
-		barrier();
-	} while (get64(&state->state_entry_time) != state_time);
-}
-
-/* return true when a vcpu could run but has no real cpu to run on */
-bool xen_vcpu_stolen(int vcpu)
-{
-	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
-}
-
-void xen_setup_runstate_info(int cpu)
-{
-	struct vcpu_register_runstate_memory_area area;
-
-	area.addr.v = &per_cpu(xen_runstate, cpu);
-
-	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
-			       cpu, &area))
-		BUG();
-}
-
 static void do_stolen_accounting(void)
 {
 	struct vcpu_runstate_info state;
@@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
 	s64 blocked, runnable, offline, stolen;
 	cputime_t ticks;
 
-	get_runstate_snapshot(&state);
+	xen_get_runstate_snapshot(&state);
 
 	WARN_ON(state.state != RUNSTATE_running);
 
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index eabd0ee..2bf461a 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -3,7 +3,7 @@ obj-y	+= manage.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 endif
 obj-$(CONFIG_X86)			+= fallback.o
-obj-y	+= grant-table.o features.o events.o balloon.o
+obj-y	+= grant-table.o features.o events.o balloon.o time.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
diff --git a/drivers/xen/time.c b/drivers/xen/time.c
new file mode 100644
index 0000000..c2e39d3
--- /dev/null
+++ b/drivers/xen/time.c
@@ -0,0 +1,91 @@
+/*
+ * Xen stolen ticks accounting.
+ */
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/math64.h>
+#include <linux/gfp.h>
+
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+
+#include <xen/events.h>
+#include <xen/features.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/vcpu.h>
+#include <xen/xen-ops.h>
+
+/* runstate info updated by Xen */
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
+
+/* return an consistent snapshot of 64-bit time/counter value */
+static u64 get64(const u64 *p)
+{
+	u64 ret;
+
+	if (BITS_PER_LONG < 64) {
+		u32 *p32 = (u32 *)p;
+		u32 h, l;
+
+		/*
+		 * Read high then low, and then make sure high is
+		 * still the same; this will only loop if low wraps
+		 * and carries into high.
+		 * XXX some clean way to make this endian-proof?
+		 */
+		do {
+			h = p32[1];
+			barrier();
+			l = p32[0];
+			barrier();
+		} while (p32[1] != h);
+
+		ret = (((u64)h) << 32) | l;
+	} else
+		ret = *p;
+
+	return ret;
+}
+
+/*
+ * Runstate accounting
+ */
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
+{
+	u64 state_time;
+	struct vcpu_runstate_info *state;
+
+	BUG_ON(preemptible());
+
+	state = &__get_cpu_var(xen_runstate);
+
+	/*
+	 * The runstate info is always updated by the hypervisor on
+	 * the current CPU, so there's no need to use anything
+	 * stronger than a compiler barrier when fetching it.
+	 */
+	do {
+		state_time = get64(&state->state_entry_time);
+		barrier();
+		*res = *state;
+		barrier();
+	} while (get64(&state->state_entry_time) != state_time);
+}
+
+/* return true when a vcpu could run but has no real cpu to run on */
+bool xen_vcpu_stolen(int vcpu)
+{
+	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
+}
+
+void xen_setup_runstate_info(int cpu)
+{
+	struct vcpu_register_runstate_memory_area area;
+
+	area.addr.v = &per_cpu(xen_runstate, cpu);
+
+	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
+			       cpu, &area))
+		BUG();
+}
+
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index d6fe062..4fd4e47 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -3,6 +3,7 @@
 
 #include <linux/percpu.h>
 #include <asm/xen/interface.h>
+#include <xen/interface/vcpu.h>
 
 DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
 
@@ -16,6 +17,10 @@ void xen_mm_unpin_all(void);
 void xen_timer_resume(void);
 void xen_arch_resume(void);
 
+bool xen_vcpu_stolen(int vcpu);
+void xen_setup_runstate_info(int cpu);
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res);
+
 int xen_setup_shutdown_event(void);
 
 extern unsigned long *xen_contiguous_bitmap;
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Tue May 28 13:54:31 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Tue, 28 May 2013 18:54:31 +0100
Subject: [PATCH v4 3/4] arm: introduce CONFIG_PARAVIRT,
 PARAVIRT_TIME_ACCOUNTING and pv_time_ops
In-Reply-To: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
Message-ID: <1369763672-12919-3-git-send-email-stefano.stabellini@eu.citrix.com>

Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.

The only paravirt interface supported is pv_time_ops.steal_clock, so no
runtime pvops patching needed.

This allows us to make use of steal_account_process_tick for stolen
ticks accounting.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: linux at arm.linux.org.uk
CC: will.deacon at arm.com
CC: nico at linaro.org
CC: marc.zyngier at arm.com
CC: cov at codeaurora.org
CC: arnd at arndb.de
CC: olof at lixom.net

Changes in v3:
- improve commit description and Kconfig help text;
- no need to initialize pv_time_ops;
- add PARAVIRT_TIME_ACCOUNTING.
---
 arch/arm/Kconfig                |   20 ++++++++++++++++++++
 arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   25 +++++++++++++++++++++++++
 4 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..5621a02 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1786,12 +1786,32 @@ config XEN_DOM0
 	def_bool y
 	depends on XEN
 
+config PARAVIRT
+	bool "Enable paravirtualization code"
+	---help---
+	  This changes the kernel so it can modify itself when it is run
+	  under a hypervisor, potentially improving performance significantly
+	  over full virtualization.
+
+config PARAVIRT_TIME_ACCOUNTING
+	bool "Paravirtual steal time accounting"
+	select PARAVIRT
+	default n
+	---help---
+	  Select this option to enable fine granularity task steal time
+	  accounting. Time spent executing other tasks in parallel with
+	  the current vCPU is discounted from the vCPU power. To account for
+	  that, there can be a small performance impact.
+
+	  If in doubt, say N here.
+
 config XEN
 	bool "Xen guest support on ARM (EXPERIMENTAL)"
 	depends on ARM && AEABI && OF
 	depends on CPU_V7 && !CPU_V6
 	depends on !GENERIC_ATOMIC64
 	select ARM_PSCI
+	select PARAVIRT
 	help
 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
diff --git a/arch/arm/include/asm/paravirt.h b/arch/arm/include/asm/paravirt.h
new file mode 100644
index 0000000..3b95bc6
--- /dev/null
+++ b/arch/arm/include/asm/paravirt.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_PARAVIRT_H
+#define _ASM_ARM_PARAVIRT_H
+
+struct static_key;
+extern struct static_key paravirt_steal_enabled;
+extern struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops {
+	unsigned long long (*steal_clock)(int cpu);
+};
+extern struct pv_time_ops pv_time_ops;
+
+static inline u64 paravirt_steal_clock(int cpu)
+{
+	return pv_time_ops.steal_clock(cpu);
+}
+
+
+#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..d911db6 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 ifneq ($(CONFIG_ARCH_EBSA110),y)
   obj-y		+= io.o
 endif
+obj-$(CONFIG_PARAVIRT)	+= paravirt.o
 
 head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
diff --git a/arch/arm/kernel/paravirt.c b/arch/arm/kernel/paravirt.c
new file mode 100644
index 0000000..53f371e
--- /dev/null
+++ b/arch/arm/kernel/paravirt.c
@@ -0,0 +1,25 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 Citrix Systems
+ *
+ * Author: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
+ */
+
+#include <linux/export.h>
+#include <linux/jump_label.h>
+#include <linux/types.h>
+#include <asm/paravirt.h>
+
+struct static_key paravirt_steal_enabled;
+struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops pv_time_ops;
+EXPORT_SYMBOL_GPL(pv_time_ops);
-- 
1.7.2.5



From jason at lakedaemon.net  Tue May 28 14:02:27 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:02:27 -0400
Subject: [PATCH 2/2] net: mv643xx_eth: proper initialization for
 Kirkwood SoCs
In-Reply-To: <20130524173306.GA30022@obsidianresearch.com>
References: <1369253042-15082-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130522201607.GA18823@obsidianresearch.com>
 <20130523160111.GP31290@titan.lakedaemon.net>
 <20130523171112.GB31281@obsidianresearch.com>
 <20130523172339.GQ31290@titan.lakedaemon.net>
 <20130523175357.GB2821@obsidianresearch.com>
 <20130523184028.GU31290@titan.lakedaemon.net>
 <20130523190140.GA4010@obsidianresearch.com>
 <20130524164636.GV31290@titan.lakedaemon.net>
 <20130524173306.GA30022@obsidianresearch.com>
Message-ID: <20130528180227.GY31290@titan.lakedaemon.net>

Jason,

Sorry, I meant to get back to this earlier and it slipped off of my
plate. :(

On Fri, May 24, 2013 at 11:33:06AM -0600, Jason Gunthorpe wrote:
> On Fri, May 24, 2013 at 12:46:36PM -0400, Jason Cooper wrote:
> 
> > > Why are you not keen on this? It seems like normal device driver
> > > practice, that is what the data field of of_device_id is typically
> > > used for..
> > 
> > I'm not keen on it because we don't have a document saying "All kirkwood
> > SoCs need PSC1 set to X after reset."  We know it, but have we tested
> > the 6282?
> 
> I disagree. The manul is very clear how PSC1 must be set for proper
> operation. Clk125BypassEn bit is used only for loopback testing, it
> should never set for driver operation. Similarly PortReset must be
> cleared for driver operation.
> 
> It is always safe for the driver to clear these bits, if it knows they
> are available.  In fact, I would argue the driver should always clear
> these bits so that the bootloader isn't relied on to do it. It doesn't
> matter if the SOC errantly sets the bit or not, it can *always* be
> safely cleared.

Great!

> Further, I compared my 88F6282/88F6283 manual against the public
> 88F6180/88F619x/88F6281 spec and confirmed that the PSC1 layout is the
> same.

Even better.

> So all of these SOC's can share a driver compatible string.

Ok, "marvell,kirkwood-eth" works for me then.  I think Sebastian already
has patches for that.

> AFAICT the only reason the driver doesn't touch PSC1 today is because
> the PSC1 was introduced in a later IP revision and its presence isn't
> auto-detectable.

Makes sense.

> The last bit of the puzzle to get bootloader independence on kirkwood
> is to encode the phy interface type (GMII/RGMII/BASE-X) in the DT so
> the entire PSC1 can be set by the driver..

Hmm, let's work on that separately, and later.  I've snowballed this
attempt enough ;-)

Thanks for digging into this for us,

Jason.


From swarren at wwwdotorg.org  Tue May 28 14:14:41 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 12:14:41 -0600
Subject: [PATCH V2] ARM: tegra: add cpu_disable for hotplug
Message-ID: <1369764881-20520-1-git-send-email-swarren@wwwdotorg.org>

From: Joseph Lo <josephl at nvidia.com>

The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
support that. Adding a Tegra specific cpu_disable function for it.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
[swarren: adjusted the switch statement to be future-proof]
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/common.h  |    1 +
 arch/arm/mach-tegra/hotplug.c |   11 +++++++++++
 arch/arm/mach-tegra/platsmp.c |    1 +
 3 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 5900cc4..32f8eb3 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops;
 
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d07f152..a52c10e 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -46,6 +46,17 @@ void __ref tegra_cpu_die(unsigned int cpu)
 	BUG();
 }
 
+int tegra_cpu_disable(unsigned int cpu)
+{
+	switch (tegra_chip_id) {
+	case TEGRA20:
+	case TEGRA30:
+		return cpu == 0 ? -EPERM : 0;
+	default:
+		return 0;
+	}
+}
+
 void __init tegra_hotplug_init(void)
 {
 	if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 554aedc..24db4ac 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -196,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= tegra_cpu_kill,
 	.cpu_die		= tegra_cpu_die,
+	.cpu_disable		= tegra_cpu_disable,
 #endif
 };
-- 
1.7.10.4



From konrad.wilk at oracle.com  Tue May 28 14:15:15 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 28 May 2013 14:15:15 -0400
Subject: [PATCH v4 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
 <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20130528181515.GB27718@phenom.dumpdata.com>

On Tue, May 28, 2013 at 06:54:29PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> Acked-by: Ian Campbell <ian.campbell at citrix.com>
> CC: konrad.wilk at oracle.com
> 
> Changes in v2:
> - leave do_stolen_accounting in arch/x86/xen/time.c;
> - use the new common functions in arch/ia64/xen/time.c.

So you also modify the function.

> ---
>  arch/ia64/xen/time.c  |   48 +++----------------------
>  arch/x86/xen/time.c   |   76 +----------------------------------------
>  drivers/xen/Makefile  |    2 +-
>  drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
>  include/xen/xen-ops.h |    5 +++
>  5 files changed, 104 insertions(+), 118 deletions(-)
>  create mode 100644 drivers/xen/time.c
> 
> diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
> index 1f8244a..79a0b8c 100644
> --- a/arch/ia64/xen/time.c
> +++ b/arch/ia64/xen/time.c
> @@ -34,53 +34,17 @@
>  
>  #include "../kernel/fsyscall_gtod_data.h"
>  
> -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
>  static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
>  static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
>  
>  /* taken from i386/kernel/time-xen.c */
>  static void xen_init_missing_ticks_accounting(int cpu)
>  {
> -	struct vcpu_register_runstate_memory_area area;
> -	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
> -	int rc;
> +	xen_setup_runstate_info(&runstate);
>  
> -	memset(runstate, 0, sizeof(*runstate));
> -
> -	area.addr.v = runstate;
> -	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> -				&area);
> -	WARN_ON(rc && rc != -ENOSYS);
> -
> -	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
> -	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
> -					    + runstate->time[RUNSTATE_offline];
> -}
> -
> -/*
> - * Runstate accounting
> - */
> -/* stolen from arch/x86/xen/time.c */
> -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> -{
> -	u64 state_time;
> -	struct vcpu_runstate_info *state;
> -
> -	BUG_ON(preemptible());
> -
> -	state = &__get_cpu_var(xen_runstate);
> -
> -	/*
> -	 * The runstate info is always updated by the hypervisor on
> -	 * the current CPU, so there's no need to use anything
> -	 * stronger than a compiler barrier when fetching it.
> -	 */
> -	do {
> -		state_time = state->state_entry_time;
> -		rmb();
> -		*res = *state;
> -		rmb();
> -	} while (state->state_entry_time != state_time);
> +	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
> +	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
> +					    + runstate.time[RUNSTATE_offline];
>  }
>  
>  #define NS_PER_TICK (1000000000LL/HZ)
> @@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
>  	struct vcpu_runstate_info runstate;
>  	struct task_struct *p = current;
>  
> -	get_runstate_snapshot(&runstate);
> +	xen_get_runstate_snapshot(&runstate);
>  
>  	/*
>  	 * Check for vcpu migration effect
> @@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
>  	 */
>  	now = ia64_native_sched_clock();
>  
> -	get_runstate_snapshot(&runstate);
> +	xen_get_runstate_snapshot(&runstate);
>  
>  	WARN_ON(runstate.state != RUNSTATE_running);
>  
> diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
> index 3d88bfd..c0ca15e 100644
> --- a/arch/x86/xen/time.c
> +++ b/arch/x86/xen/time.c
> @@ -30,9 +30,6 @@
>  #define TIMER_SLOP	100000
>  #define NS_PER_TICK	(1000000000LL / HZ)
>  
> -/* runstate info updated by Xen */
> -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> -
>  /* snapshots of runstate info */
>  static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
>  
> @@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
>  static DEFINE_PER_CPU(u64, xen_residual_stolen);
>  static DEFINE_PER_CPU(u64, xen_residual_blocked);
>  
> -/* return an consistent snapshot of 64-bit time/counter value */
> -static u64 get64(const u64 *p)
> -{
> -	u64 ret;
> -
> -	if (BITS_PER_LONG < 64) {
> -		u32 *p32 = (u32 *)p;
> -		u32 h, l;
> -
> -		/*
> -		 * Read high then low, and then make sure high is
> -		 * still the same; this will only loop if low wraps
> -		 * and carries into high.
> -		 * XXX some clean way to make this endian-proof?
> -		 */
> -		do {
> -			h = p32[1];
> -			barrier();
> -			l = p32[0];
> -			barrier();
> -		} while (p32[1] != h);
> -
> -		ret = (((u64)h) << 32) | l;
> -	} else
> -		ret = *p;
> -
> -	return ret;
> -}
> -
> -/*
> - * Runstate accounting
> - */
> -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> -{
> -	u64 state_time;
> -	struct vcpu_runstate_info *state;
> -
> -	BUG_ON(preemptible());
> -
> -	state = &__get_cpu_var(xen_runstate);
> -
> -	/*
> -	 * The runstate info is always updated by the hypervisor on
> -	 * the current CPU, so there's no need to use anything
> -	 * stronger than a compiler barrier when fetching it.
> -	 */
> -	do {
> -		state_time = get64(&state->state_entry_time);
> -		barrier();
> -		*res = *state;
> -		barrier();
> -	} while (get64(&state->state_entry_time) != state_time);
> -}
> -
> -/* return true when a vcpu could run but has no real cpu to run on */
> -bool xen_vcpu_stolen(int vcpu)
> -{
> -	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> -}
> -
> -void xen_setup_runstate_info(int cpu)
> -{
> -	struct vcpu_register_runstate_memory_area area;
> -
> -	area.addr.v = &per_cpu(xen_runstate, cpu);
> -
> -	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> -			       cpu, &area))
> -		BUG();
> -}
> -
>  static void do_stolen_accounting(void)
>  {
>  	struct vcpu_runstate_info state;
> @@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
>  	s64 blocked, runnable, offline, stolen;
>  	cputime_t ticks;
>  
> -	get_runstate_snapshot(&state);
> +	xen_get_runstate_snapshot(&state);
>  
>  	WARN_ON(state.state != RUNSTATE_running);
>  
> diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
> index eabd0ee..2bf461a 100644
> --- a/drivers/xen/Makefile
> +++ b/drivers/xen/Makefile
> @@ -3,7 +3,7 @@ obj-y	+= manage.o
>  obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
>  endif
>  obj-$(CONFIG_X86)			+= fallback.o
> -obj-y	+= grant-table.o features.o events.o balloon.o
> +obj-y	+= grant-table.o features.o events.o balloon.o time.o
>  obj-y	+= xenbus/
>  
>  nostackp := $(call cc-option, -fno-stack-protector)
> diff --git a/drivers/xen/time.c b/drivers/xen/time.c
> new file mode 100644
> index 0000000..c2e39d3
> --- /dev/null
> +++ b/drivers/xen/time.c
> @@ -0,0 +1,91 @@
> +/*
> + * Xen stolen ticks accounting.
> + */
> +#include <linux/kernel.h>
> +#include <linux/kernel_stat.h>
> +#include <linux/math64.h>
> +#include <linux/gfp.h>
> +
> +#include <asm/xen/hypervisor.h>
> +#include <asm/xen/hypercall.h>
> +
> +#include <xen/events.h>
> +#include <xen/features.h>
> +#include <xen/interface/xen.h>
> +#include <xen/interface/vcpu.h>
> +#include <xen/xen-ops.h>
> +
> +/* runstate info updated by Xen */
> +static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> +
> +/* return an consistent snapshot of 64-bit time/counter value */
> +static u64 get64(const u64 *p)
> +{
> +	u64 ret;
> +
> +	if (BITS_PER_LONG < 64) {
> +		u32 *p32 = (u32 *)p;
> +		u32 h, l;
> +
> +		/*
> +		 * Read high then low, and then make sure high is
> +		 * still the same; this will only loop if low wraps
> +		 * and carries into high.
> +		 * XXX some clean way to make this endian-proof?
> +		 */
> +		do {
> +			h = p32[1];
> +			barrier();
> +			l = p32[0];
> +			barrier();
> +		} while (p32[1] != h);
> +
> +		ret = (((u64)h) << 32) | l;
> +	} else
> +		ret = *p;
> +
> +	return ret;
> +}
> +
> +/*
> + * Runstate accounting
> + */
> +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
> +{
> +	u64 state_time;
> +	struct vcpu_runstate_info *state;
> +
> +	BUG_ON(preemptible());
> +
> +	state = &__get_cpu_var(xen_runstate);
> +
> +	/*
> +	 * The runstate info is always updated by the hypervisor on
> +	 * the current CPU, so there's no need to use anything
> +	 * stronger than a compiler barrier when fetching it.
> +	 */
> +	do {
> +		state_time = get64(&state->state_entry_time);
> +		barrier();
> +		*res = *state;
> +		barrier();
> +	} while (get64(&state->state_entry_time) != state_time);
> +}
> +
> +/* return true when a vcpu could run but has no real cpu to run on */
> +bool xen_vcpu_stolen(int vcpu)
> +{
> +	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> +}
> +
> +void xen_setup_runstate_info(int cpu)
> +{
> +	struct vcpu_register_runstate_memory_area area;
> +
> +	area.addr.v = &per_cpu(xen_runstate, cpu);
> +
> +	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> +			       cpu, &area))
> +		BUG();

The original code did:

-       rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
-                               &area);
-       WARN_ON(rc && rc != -ENOSYS);
-
Any reason not to do this?

> +}
> +
> diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
> index d6fe062..4fd4e47 100644
> --- a/include/xen/xen-ops.h
> +++ b/include/xen/xen-ops.h
> @@ -3,6 +3,7 @@
>  
>  #include <linux/percpu.h>
>  #include <asm/xen/interface.h>
> +#include <xen/interface/vcpu.h>
>  
>  DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
>  
> @@ -16,6 +17,10 @@ void xen_mm_unpin_all(void);
>  void xen_timer_resume(void);
>  void xen_arch_resume(void);
>  
> +bool xen_vcpu_stolen(int vcpu);
> +void xen_setup_runstate_info(int cpu);
> +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res);
> +
>  int xen_setup_shutdown_event(void);
>  
>  extern unsigned long *xen_contiguous_bitmap;
> -- 
> 1.7.2.5
> 


From nico at fluxnic.net  Tue May 28 14:19:00 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 28 May 2013 14:19:00 -0400 (EDT)
Subject: VDSO for arm 32bit
In-Reply-To: <20130528092313.GA10474@mudshark.cambridge.arm.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305281415040.1918@syhkavp.arg>

On Tue, 28 May 2013, Will Deacon wrote:

> On Tue, May 28, 2013 at 08:48:33AM +0100, Kumar, Ganesh wrote:
> > Hi Mikel,
> > 
> > Kumar, Ganesh writes:
> >  > Hi All,
> >  >
> >  > ? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is  > no support for vdso for arm 32 bit.
> >  > I'm planning to port it to arm 32 bit, is there any work under progress?
> >  > would like to understand why the support for arm 32 bit is not there, any idea?
> > 
> > > 32-bit ARM has a "kuser" page at a fixed virtual address, which exports a few critical routines to user-space.  With that, a vdso is mostly redundant.
> > 
> >   Thanks for the info, my main idea is to get the gettimeofday exported through the kuser helper,tried looking at the sources
> > but I could not find anything related to that seems done in the mainline kernel tree for arm cortex, am I missing something here?
> > I plan to do that if its not available yet, right now I've started with the kernel doc for the kuser, any pointers further
> > to get the gettimeofday up and running using the kuser, Thanks in advance for your time.
> 
> Be careful here. I had a crack at a gtod implementation for the vectors page
> in the past, but decided to drop it because it quickly became a maintenance
> nightmare. Since the layout of the vectors page must be fixed (as userspace
> jumps to the absolute addresses for the helpers), having large, complicated
> functions (which gtod does become as you quickly start using the stack to
> store all of the shared state with the kernel) means that you can quickly
> back yourself into a corner where the layout of the code cannot change
> without breaking the ABI.

Note that only the entry point is fixed.  The layout of the code is not.  
So you may well branch anywhere else within the vector page if the code 
is more complex than a few instructions.

> On top of that, new clock types are added more often than you might think
> (not to mention bug fixes in the implementation itself), and you end up in
> a horrible situation where you'd end up deprecating one implementation and
> adding gettimeofday2 or something equally nasty at a different offset.

That is equally valid for a vdso.


Nicolas

From adrienverge at gmail.com  Tue May 28 14:29:09 2013
From: adrienverge at gmail.com (=?UTF-8?Q?Adrien_Verg=C3=A9?=)
Date: Tue, 28 May 2013 14:29:09 -0400
Subject: [PATCH] ARM: omap2plus_defconfig: enable USB_PHY and NOP_USB_XCEIV
Message-ID: <CANsc=4W8cW3jQs8yN_j8DZyEo7GkMejNc4Vw65A4iW+GuasBaw@mail.gmail.com>

On OMAP2+ platforms, USB support needs physical layer signalling and
the NOP USB Transceiver driver since v3.10. This patch enables USB_PHY
and NOP_USB_XCEIV in omap2plus_defconfig. These two are harmless to
the kernel stability, and useful since they are required for USB and
Ethernet (over USB) support.

We do not enable USB_EHCI_HCD here because all features aren't fully
supported yet.

This patch applies to Linux 3.10-rc3.

Cc: Roger Quadros <rogerq at ti.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Felipe Balbi <balbi at ti.com>
Signed-off-by: Adrien Verg? <adrienverge at gmail.com>
---
 arch/arm/configs/omap2plus_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/omap2plus_defconfig
b/arch/arm/configs/omap2plus_defconfig
index abbe319..2ac0ffb 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -210,6 +210,8 @@ CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_TEST=y
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG=y
 CONFIG_USB_GADGET_DEBUG_FILES=y
-- 
1.7.10.4


From jason at lakedaemon.net  Tue May 28 14:31:10 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:31:10 -0400
Subject: [GIT PULL] ARM: mvebu: fixes-non-critical for v3.11
Message-ID: <20130528183110.GZ31290@titan.lakedaemon.net>

Olof,

As asked, these were pulled out of mvebu/fixes.


The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:

  Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/fixes-non-3.11-1

for you to fetch changes up to cf8088c5cac6ce20d914b9131533844b9291a054:

  arm: mvebu: fix length of Ethernet registers area in .dtsi (2013-05-28 14:48:28 +0000)

----------------------------------------------------------------
mvebu fixes non-critical for v3.11 (round 1)

 - mvebu
    - fix register area length in dtsi for ethernet and sata

----------------------------------------------------------------
Thomas Petazzoni (2):
      arm: mvebu: fix length of SATA registers area in .dtsi
      arm: mvebu: fix length of Ethernet registers area in .dtsi

 arch/arm/boot/dts/armada-370-xp.dtsi     | 6 +++---
 arch/arm/boot/dts/armada-xp-mv78460.dtsi | 2 +-
 arch/arm/boot/dts/armada-xp.dtsi         | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)


From jason at lakedaemon.net  Tue May 28 14:34:22 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:34:22 -0400
Subject: [GIT PULL] ARM: mvebu: cleanup for v3.11 (round 3 cumulative)
Message-ID: <20130528183422.GA31290@titan.lakedaemon.net>

Olof,

This is the latest for cleanup, and the summary includes everything so
far for this window.


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/cleanup-3.11-3

for you to fetch changes up to c589f9b4b51317cfc530812fe90a9895bd51430e:

  arm: mvebu: mark functions of armada-370-xp.c as static (2013-05-21 13:44:32 +0000)

----------------------------------------------------------------
mvebu cleanup for v3.11 (round 3)

 - mvebu
    - mark functions in armada-370-xp.c as static

----------------------------------------------------------------
Andrew Lunn (1):
      ARM: Orion: Remove redundant init_dma_coherent_pool_size()

Maxime Ripard (1):
      ARM: mvebu: Remove init_irq declaration in machine description

Thomas Petazzoni (1):
      arm: mvebu: mark functions of armada-370-xp.c as static

 arch/arm/mach-kirkwood/common.c     |  6 ------
 arch/arm/mach-mvebu/armada-370-xp.c | 15 +++------------
 arch/arm/mach-orion5x/common.c      |  7 -------
 3 files changed, 3 insertions(+), 25 deletions(-)


From jason at lakedaemon.net  Tue May 28 14:36:17 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:36:17 -0400
Subject: [GIT PULL] ARM: mvebu: soc changes for v3.11 (round 2 cumulative)
Message-ID: <20130528183617.GB31290@titan.lakedaemon.net>

Olof,

summary is cumulative.


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/soc-3.11-2

for you to fetch changes up to efde309297a08e32d89e4a96c4051e86dcd50b45:

  arm: kirkwood: Instantiate cpufreq driver (2013-05-26 17:56:24 +0000)

----------------------------------------------------------------
mvebu soc changes for v3.11 (round 2)

 - kirkwood
    - use the cpufreq driver

----------------------------------------------------------------
Andrew Lunn (1):
      arm: kirkwood: Instantiate cpufreq driver

Thomas Petazzoni (1):
      arm: kirkwood: use the default of match table

 arch/arm/Kconfig                                  |  1 +
 arch/arm/mach-kirkwood/board-dt.c                 |  9 +++------
 arch/arm/mach-kirkwood/common.c                   | 23 +++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h                   |  2 ++
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |  2 ++
 5 files changed, 31 insertions(+), 6 deletions(-)


From jason at lakedaemon.net  Tue May 28 14:38:22 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:38:22 -0400
Subject: [GIT PULL] ARM: mvebu: boards for v3.11 (round 2 cumulative)
Message-ID: <20130528183822.GC31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/boards-3.11-2

for you to fetch changes up to 391a16c7783a64309dc930c6d454372d7a8beb12:

  ARM: Kirkwood: Convert LSXL to restart-poweroff driver. (2013-05-26 01:12:34 +0000)

----------------------------------------------------------------
mvebu board changes for v3.11 (round 2)

 - kirkwood
    - QNAP use power-off driver
    - LSXL use restart-poweroff driver

----------------------------------------------------------------
Andrew Lunn (2):
      ARM: Kirkwood: Make use of the QNAP Power off driver.
      ARM: Kirkwood: Convert LSXL to restart-poweroff driver.

Simon Baatz (1):
      ARM: Kirkwood: add DT support for Sheevaplug and Sheevaplug eSATA

 arch/arm/boot/dts/kirkwood-lsxl.dtsi      |  4 ++++
 arch/arm/boot/dts/kirkwood-ts219.dtsi     |  5 +++++
 arch/arm/mach-kirkwood/Kconfig            |  9 +++++++++
 arch/arm/mach-kirkwood/Makefile           |  1 +
 arch/arm/mach-kirkwood/board-dt.c         |  4 ++++
 arch/arm/mach-kirkwood/board-lsxl.c       | 16 ----------------
 arch/arm/mach-kirkwood/board-sheevaplug.c | 27 +++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-ts219.c      |  3 ---
 arch/arm/mach-kirkwood/common.h           |  5 +++++
 9 files changed, 55 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-kirkwood/board-sheevaplug.c


From khilman at linaro.org  Tue May 28 14:33:15 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 28 May 2013 11:33:15 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <CAGo_u6ruWQwSB8Z0BRLda7HunTyr9mGpx4eMSGdQZkCxKxbHbg@mail.gmail.com>
 (Nishanth Menon's message of "Sun, 26 May 2013 12:35:51 -0500")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <87ppwgdnxu.fsf@linaro.org>
 <CAGo_u6ruWQwSB8Z0BRLda7HunTyr9mGpx4eMSGdQZkCxKxbHbg@mail.gmail.com>
Message-ID: <87a9nfc5uc.fsf@linaro.org>

Nishanth Menon <nm at ti.com> writes:

> On Fri, May 24, 2013 at 5:15 PM, Kevin Hilman <khilman at linaro.org> wrote:
>> Kevin Hilman <khilman at linaro.org> writes:
>>
>>> Nishanth Menon <nm at ti.com> writes:
>>
>> [...]
>>
>>>> Actually 2 things:
>>>>
>>>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>>>> have been used instead of 0x14 which is correct for 4430?
>>>
>>> I see, thanks.  I'll double check the TRMs.
>>>
>>>> b) yes, I understand,  the current settings we did worked, but the
>>>> mode(0) we are setting to is real weird - we are setting it up for
>>>> clk0 out - I cant even think why it is even working in the first place
>>>> :( - is it because we are pumping out sysclkout and as a result we are
>>>> lucky that msecure is being sampled at the right point by twl6030
>>>> allowing rtc access? either way, IMHO, the configuration is wrong.
>>>
>>> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
>>> for legacy mode, I just duplicated the settings u-boot was using.  Guess
>>> it's a fluke that it works.
>>
>> Actually, for legacy mode, it's set correctly in mode 2.  This line:
>>
>>         omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
>>
>> does the right thing based on the signal name.    But for DT boot, I
>> defintely screwed it up by setting it to mode (and putting it in the
>> wrong padconf section.)
>>
>> Also, are you *really* sure about the offset difference between 4430 and
>> 4460 here?  I don't have access to NDA docs anymore, so I cannot double
>> check this.
>>
>> What I do know is that the legacy code is using 0x54 for both, and if I
>> simply comment out that 'sys_drm_msecure' line above, RTC wake stops
>> working (legacy boot) on both 4430 and 4460, so that seems like pretty
>> stront evidence that it's the same offset on both.
> Schematics are public for PandaBoard ES and PandaBoard - as you can
> see from that the registers connected are definitely different.

What I see from both schematics is that SYS_DRM_MSECURE is available on
a few different pads, but on both 4430 and 4460, one of the places is in
mode 2 of FREF_CLK0_OUT, which is at offset 0x54 on both SoCs.

Based on that reading, and the fact that not correctly muxing that pad
to mode 2 on *both* 4430 and 4460 makes the RTC work, I'm rather
convinced that the offset should be the same for 4430 and 4460.

What am I missing?

Kevin


From jason at lakedaemon.net  Tue May 28 14:40:35 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:40:35 -0400
Subject: [GIT PULL] ARM: mvebu: defconfig changes for v3.11 (round 3
 cumulative)
Message-ID: <20130528184035.GD31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/defconfig-3.11-3

for you to fetch changes up to 3f4c6f43c73fc42f99f58d54e6425a06df89213f:

  arm: kirkwood: Enable cpufreq and ondemand on kirkwood_defconfig (2013-05-26 18:01:03 +0000)

----------------------------------------------------------------
mvebu defconfig changes for v3.11 (round 3)

 - kirkwood
    - enable cpufreq and ondemand governor

----------------------------------------------------------------
Andrew Lunn (2):
      ARM: Kirkwood: Enable USB 3.0 in kirkwood_defconfig
      arm: kirkwood: Enable cpufreq and ondemand on kirkwood_defconfig

Ezequiel Garcia (1):
      ARM: mvebu: Add support for USB storage class in mvebu_defconfig

Jason Cooper (1):
      ARM: kirkwood: enable Sheevaplug DT in defconfig

Thomas Petazzoni (2):
      arm: mvebu: update defconfig with PCI and USB support
      arm: kirkwood: update defconfig with PCIe driver and board updates

 arch/arm/configs/kirkwood_defconfig | 10 +++++++---
 arch/arm/configs/mvebu_defconfig    |  4 ++++
 2 files changed, 11 insertions(+), 3 deletions(-)


From jgchunter at gmail.com  Tue May 28 14:41:54 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Tue, 28 May 2013 19:41:54 +0100
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130523201358.GI31836@blackmetal.musicnaut.iki.fi>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com> <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
 <20130523201358.GI31836@blackmetal.musicnaut.iki.fi>
Message-ID: <51A4FA72.2070402@gmail.com>


On 23/05/13 21:13, Aaro Koskinen wrote:
> On Thu, May 23, 2013 at 08:02:05PM +0100, Jon Hunter wrote:
>> On 22/05/13 22:20, Aaro Koskinen wrote:
>>> On Tue, May 21, 2013 at 08:37:16PM +0100, Jon Hunter wrote:
>>>> On 21/05/13 18:39, Aaro Koskinen wrote:
>>>>> On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
>>>>>> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
>>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
>>>>>>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
>>>>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
>>>>>>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
>>>>>>>>>>
>>>>>>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
>>>>>>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
>>>>>>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
>>>>>>>>>>
>>>>>>>>>> The error is coming from regmap code. According to git bisect, it is
>>>>>>>>>> caused by:
>>>>>>>>>>
>>>>>>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
>>>>>>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
>>>>>>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
>>>>>>>>>>
>>>>>>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
>>>>>>>>>>
>>>>>>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
>>>>>>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
>>>>>>>>>
>>>>>>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
>>>>>>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
>>>>>>>>>
>>>>>>>>> For the -rc cycle, it might be possible to fix this by adding a
>>>>>>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
>>>>>>>>
>>>>>>>> The commit reverts cleanly if we also revert
>>>>>>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
>>>>>>>> service routine), which seems to be just some minor optimization. The
>>>>>>>> result is below, and with it 770 works again.
>>>>>>>
>>>>>>> Hmm in this case it seems that we should just fix it rather than go back
>>>>>>> to the old code, so let's take a look at that first.
>>>>>>
>>>>>> Does the following fix it for you or do we need to fix something else
>>>>>> there too?
>>>>>
>>>>> Thanks, that fixes Retu probe on 770.
>>>>
>>>> Sorry for not responding sooner, but I have been moving. 
>>>>
>>>> From looking at the code it appears that the regmap_add_irq_chip()
>>>> is failing in the retu driver. I am not sure if this will work, 
>>>> but have you tried making the following change to the retu driver 
>>>> so that it also uses irq_domain_add_linear() as well? Just a thought ...
>>>
>>> This will trigger WARNING: at drivers/base/regmap/regmap-irq.c:514.
>>
>> Sorry, there is another change needed. Can you try ...
> 
> I will try this. However, I would also like to point out that Retu works
> fine on N800/N810 (OMAP2). If the problem is in Retu, why only OMAP1
> is affected?

The problem is not with retu or the gpio driver per-se, its just that
now they are conflicting because the way the irq domains are being
allocated. So probably just getting lucky on the n8xx. I had tested on
omap1-4 and had not seen any problems, but none of my boards used the
retu driver.

Cheers
Jon


From jason at lakedaemon.net  Tue May 28 14:42:18 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 14:42:18 -0400
Subject: [GIT PULL] ARM: mvebu: dt changes for v3.11 (round 3 cumulative)
Message-ID: <20130528184218.GE31290@titan.lakedaemon.net>


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/dt-3.11-3

for you to fetch changes up to 9196024a989ace933d6b17e0a56c847d02d81240:

  arm: kirkwood: openblocks-a6: add support for Init button (2013-05-27 15:35:04 +0000)

----------------------------------------------------------------
mvebu dt changes for v3.11 (round 3)

 - mvebu
    - enable two usb interfaces on Armada XP-GP

 - kirkwood
    - move pinmux configs to their individual devices
    - group the pinmux configs on OpenBlocks A6
    - add the Init button for the OpenBlocks A6

----------------------------------------------------------------
Ezequiel Garcia (1):
      ARM: mvebu: Add support for NOR flash device on Armada XP-DB board

Sebastian Hesselbarth (1):
      ARM: dove: add si5351 clock driver to CuBox DT

Simon Baatz (2):
      ARM: mvebu: Use standard MMC binding for all users of mvsdio
      ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug

Thomas Petazzoni (23):
      arm: mvebu: enable the third USB interface on OpenBlocks AX3
      arm: mvebu: enable two USB interfaces on the Armada XP GP board
      arm: kirkwood: cloudbox: move pinmux configs to the right devices
      arm: kirkwood: dlink dns: move pinmux configs to the right devices
      arm: kirkwood: dockstar: move pinmux configs to the right devices
      arm: kirkwood: dreamplug: move pinmux configs to the right devices
      arm: kirkwood: goflexnet: move pinmux configs to the right devices
      arm: kirkwood: guruplug: move pinmux configs to the right devices
      arm: kirkwood: ib62x0: move pinmux configs to the right devices
      arm: kirkwood: iconnect: give meaningful names to pinmux configs
      arm: kirkwood: iconnect: move pinmux configs to the right devices
      arm: kirkwood: iomega ix2-200: move pinmux configs to the right devices
      arm: kirkwood: ns2: move pinmux configs to the right devices
      arm: kirkwood: keymile: move pinmux configs to the right devices
      arm: kirkwood: buffalo linkstation: move pinmux configs to the right devices
      arm: kirkwood: mplcec4: move pinmux configs to the right devices
      arm: kirkwood: readynas: move pinmux configs to the right devices
      arm: kirkwood: nsa310: move pinmux configs to the right devices
      arm: kirkwood: openblocks_a6: move pinmux configs to the right devices
      arm: kirkwood: topkick: move pinmux configs to the right devices
      arm: kirkwood: ts219: move pinmux configs to the right devices
      arm: kirkwood: openblocks-a6: group pinmux configurations
      arm: kirkwood: openblocks-a6: add support for Init button

 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/armada-370-db.dts                |   1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |   1 +
 arch/arm/boot/dts/armada-370-rd.dts                |   1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |   4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |  33 +++++++
 arch/arm/boot/dts/armada-xp-gp.dts                 |  10 ++
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   |   9 ++
 arch/arm/boot/dts/dove-cubox.dts                   |  51 +++++++++-
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |  10 +-
 arch/arm/boot/dts/kirkwood-dns320.dts              |   7 ++
 arch/arm/boot/dts/kirkwood-dns325.dts              |   5 +
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |  32 +++---
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   9 +-
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |  12 +--
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |  18 ++--
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |  10 +-
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |  17 ++--
 arch/arm/boot/dts/kirkwood-iconnect.dts            |  36 +++----
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |  15 +--
 arch/arm/boot/dts/kirkwood-is2.dts                 |   2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   6 +-
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |  22 +++--
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |  25 ++---
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |  22 ++---
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |  10 +-
 arch/arm/boot/dts/kirkwood-ns2.dts                 |   2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |   2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |   2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |   2 +
 arch/arm/boot/dts/kirkwood-nsa310.dts              |  29 +++---
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       | 108 ++++++---------------
 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi  |  97 ++++++++++++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts    |  40 ++++++++
 arch/arm/boot/dts/kirkwood-sheevaplug.dts          |  45 +++++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |  52 +++++-----
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |   8 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |   8 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |  10 ++
 arch/arm/boot/dts/kirkwood.dtsi                    |   4 +
 40 files changed, 537 insertions(+), 242 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-sheevaplug.dts


From jgchunter at gmail.com  Tue May 28 14:42:41 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Tue, 28 May 2013 19:42:41 +0100
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130526190710.GA3345@blackmetal.musicnaut.iki.fi>
References: <20130513205302.GA3157@blackmetal.musicnaut.iki.fi>
 <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com> <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
 <20130526190710.GA3345@blackmetal.musicnaut.iki.fi>
Message-ID: <51A4FAA1.5060504@gmail.com>


On 26/05/13 20:07, Aaro Koskinen wrote:
> On Thu, May 23, 2013 at 08:02:05PM +0100, Jon Hunter wrote:
>> On 22/05/13 22:20, Aaro Koskinen wrote:
>>> On Tue, May 21, 2013 at 08:37:16PM +0100, Jon Hunter wrote:
>>>> On 21/05/13 18:39, Aaro Koskinen wrote:
>>>>> On Mon, May 20, 2013 at 10:46:21AM -0700, Tony Lindgren wrote:
>>>>>> * Tony Lindgren <tony at atomide.com> [130516 14:50]:
>>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130516 14:05]:
>>>>>>>> On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
>>>>>>>>> * Aaro Koskinen <aaro.koskinen at iki.fi> [130513 13:58]:
>>>>>>>>>> I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
>>>>>>>>>>
>>>>>>>>>> [    2.264221] retu-mfd 2-0001: Retu v3.2 found
>>>>>>>>>> [    2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
>>>>>>>>>> [    2.300140] retu-mfd: probe of 2-0001 failed with error -12
>>>>>>>>>>
>>>>>>>>>> The error is coming from regmap code. According to git bisect, it is
>>>>>>>>>> caused by:
>>>>>>>>>>
>>>>>>>>>> 	commit ede4d7a5b9835510fd1f724367f68d2fa4128453
>>>>>>>>>> 	Author: Jon Hunter <jon-hunter at ti.com>
>>>>>>>>>> 	Date:   Fri Mar 1 11:22:47 2013 -0600
>>>>>>>>>>
>>>>>>>>>> 	    gpio/omap: convert gpio irq domain to linear mapping
>>>>>>>>>>
>>>>>>>>>> The commit does not anymore revert cleanly, and I haven't yet tried
>>>>>>>>>> crafting a manual revert, so any fix proposals/ideas are welcome...
>>>>>>>>>
>>>>>>>>> Hmm this might be a bit trickier to fix. Obviously the real solution
>>>>>>>>> is to convert omap1 to SPARSE_IRQ like we did for omap2+.
>>>>>>>>>
>>>>>>>>> For the -rc cycle, it might be possible to fix this by adding a
>>>>>>>>> different irq_to_gpio() and gpio_to_irq() functions for omap1.
>>>>>>>>
>>>>>>>> The commit reverts cleanly if we also revert
>>>>>>>> 3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
>>>>>>>> service routine), which seems to be just some minor optimization. The
>>>>>>>> result is below, and with it 770 works again.
>>>>>>>
>>>>>>> Hmm in this case it seems that we should just fix it rather than go back
>>>>>>> to the old code, so let's take a look at that first.
>>>>>>
>>>>>> Does the following fix it for you or do we need to fix something else
>>>>>> there too?
>>>>>
>>>>> Thanks, that fixes Retu probe on 770.
>>>>
>>>> Sorry for not responding sooner, but I have been moving. 
>>>>
>>>> From looking at the code it appears that the regmap_add_irq_chip()
>>>> is failing in the retu driver. I am not sure if this will work, 
>>>> but have you tried making the following change to the retu driver 
>>>> so that it also uses irq_domain_add_linear() as well? Just a thought ...
>>>
>>> This will trigger WARNING: at drivers/base/regmap/regmap-irq.c:514.
>>
>> Sorry, there is another change needed. Can you try ...
> 
> I don't see much improvement with this. Although Retu probe succeeds,
> genirq error logs are still there. Also none of the GPIO irqs used by
> other drivers seem to be working at all, e.g. touchscreen.

Care to share the log?

Jon


From r.sricharan at ti.com  Tue May 28 14:48:40 2013
From: r.sricharan at ti.com (Sricharan R)
Date: Wed, 29 May 2013 00:18:40 +0530
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <20130528140705.GE28971@mudshark.cambridge.arm.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com> <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com>
Message-ID: <51A4FC08.3060906@ti.com>

On Tuesday 28 May 2013 07:37 PM, Will Deacon wrote:
> On Tue, May 28, 2013 at 03:03:36PM +0100, Sricharan R wrote:
>> On Tuesday 28 May 2013 06:35 PM, Will Deacon wrote:
>>> On Tue, May 28, 2013 at 11:48:20AM +0100, Po-Yu Chuang wrote:
>>>> This bug was introduced in commit e651eab0.
>>>> Some v4/v5 platforms failed to boot due to this.
>>>>
>>>> Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
>>>> ---
>>>>  arch/arm/mm/mmu.c |    4 +++-
>>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>>>> index e0d8565..19a43f8 100644
>>>> --- a/arch/arm/mm/mmu.c
>>>> +++ b/arch/arm/mm/mmu.c
>>>> @@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
>>>>  			unsigned long end, phys_addr_t phys,
>>>>  			const struct mem_type *type)
>>>>  {
>>>> +	pmd_t *p = pmd;
>>>> +
>>>>  #ifndef CONFIG_ARM_LPAE
>>>>  	/*
>>>>  	 * In classic MMU format, puds and pmds are folded in to
>>>> @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
>>>>  		phys += SECTION_SIZE;
>>>>  	} while (pmd++, addr += SECTION_SIZE, addr != end);
>>>>  
>>>> -	flush_pmd_entry(pmd);
>>>> +	flush_pmd_entry(p);
>>> Wait, shouldn't this flush be *inside* the loop anyway? Otherwise we just
>>> flush the cacheline containing the first pmd. The flushing code could also
>>> flush to PoU instead of PoC for UP ARMv7, but that's an unrelated optimisation.
>>    I think in LPAE this loop iterates once and non LPAE twice.
>>    So both the entries should be contained in same cache line right ?
> Dunno, are there any guarantees about alignment of the starting pmd? Even
> so, the function takes the range as parameters, so I don't think we
> should tailor it to the caller. It may explain why this hasn't come up
> sooner though.
>
> Will
 
 This function is not exposed outside. And the ranges passed to this is going
to not more than 2 entries in any case. If we put the flush inside the loop,
then we will end up doing an extra flush for the same line. Regarding the
alignment, I think if the pgd base is aligned, then rest should be fine.
Will have to check this.

Regards,
 Sricharan




From nico at fluxnic.net  Tue May 28 14:50:18 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 28 May 2013 14:50:18 -0400 (EDT)
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130528102001.GB14329@arm.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com> <20130527214245.GB517@schnuecks.de>
 <20130528102001.GB14329@arm.com>
Message-ID: <alpine.LFD.2.03.1305281423510.1918@syhkavp.arg>

On Tue, 28 May 2013, Catalin Marinas wrote:

> On Mon, May 27, 2013 at 10:42:45PM +0100, Simon Baatz wrote:
> > On Thu, May 23, 2013 at 11:43:03AM +0100, Catalin Marinas wrote:
> > > On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > > > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > > > it needs to handle are kernel mapped only.  However, for example when doing
> > > > direct I/O, pages with user space mappings may occur.
> > > > 
> > > > Thus, continue to do lazy flushing if there are no user space mappings.
> > > > Otherwise, flush the kernel cache lines directly.
> > > > 
> > > > Signed-off-by: Simon Baatz <gmbnomis at gmail.com>
> > > > Cc: Catalin Marinas <catalin.marinas at arm.com>
> > > > Cc: Russell King <linux at arm.linux.org.uk>
> > > 
> > > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > > twice. I don't think we should remove the cache flushing in
> > > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > > don't work together). Flushing the VIVT cache on kunmap is essential
> > > since we just lose the alias after that.
> > 
> > Not sure if I am missing something here. From our previous
> > discussion:
> > 
> > > > > > We probably should reuse it in flush_kernel_dcache_page() to flush
> > > > > > the kernel mapping. (The last else clause looks strange though)
> > > > > 
> > > > > I think it makes sense to reuse this logic in
> > > > > flush_kernel_dcache_page(). If the page is already mapped with kmap,
> > > > > then kmap_high_get() should return the actual address. If it was mapped
> > > > > with kmap_atomic, kmap_high_get() would return NULL, hence the 'else'
> > > > > clause and the additional kmap_atomic(). The cache_is_vipt() check is
> > > > > useful because kunmap_atomic() would flush VIVT caches anyway.
> 
> I think the context was that page_address() is not always valid after
> kmap_atomic(), so reusing the same logic would make sense.

Following my explanation of kunmap()... remember that kunmap()'d pages 
are not actually unmaped right away.  So the only thing that 
kmap_high_get() does is to look for such a mapping and pin it with an 
increased use count if it exists, or return NULL if there is no such 
mapping.  In the former case page_address() is valid, in the second case 
it is NULL.  Yet, after kunmap_atomic() (or kunmap() as well) you never 
know when page_address() might suddenly return NULL if it returned an 
address unless you pin the page down with kmap_high_get().

> But the key point I try to understand is why kunmap() does not need to
> flush the VIVT cache. If it does need to, then we can simplify your
> patch.

It does not and should not for performance reasons.

> > As you say, this logic does not flush on VIVT if the page was mapped
> > via kmap_atomic() (and kmap_atomic() could not reuse an existing
> > mapping via kmap_high_get())
> > 
> > kmap_atomic() tries to reuse an existing mapping and only allocates a
> > new dedicated kmap if it finds none.  Consequently, __kunmap_atomic()
> > only flushes in the latter case (because we lose the alias).

That is exact.

> > 
> > Thus, no double flushing should occur here. If kunmap_atomic() will
> > flush, __flush_kernel_dcache_page() will not and vice versa.
> 
> That's correct for the current code. Let's wait for some insight from
> Nico or Russell on whether kunmap() needs to lush the VIVT cache as
> well. If it doesn't need to, then my original comment made sense.

I hope I've been able to shed some light on the way highmem caching 
works.  I'm not sure I fully understand what the patch in this thread 
does though, but I've never fully grokked the subtleties behind 
flush_dcache_page either.


Nicolas


From davidb at codeaurora.org  Tue May 28 14:50:41 2013
From: davidb at codeaurora.org (David Brown)
Date: Tue, 28 May 2013 11:50:41 -0700
Subject: [PATCH 7/8] ARM: msm: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-8-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
 <1369665166-13049-8-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <20130528185039.GA11236@davidb.org>

On Mon, May 27, 2013 at 08:02:44PM +0530, Sanjay Singh Rawat wrote:
> use cpu_do_idle for entering the wfi mode.
> 
> Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
> ---
>  arch/arm/mach-msm/hotplug.c |    9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)

Acked-by: David Brown <davidb at codeaurora.org>

-- 
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From marex at denx.de  Tue May 28 14:29:55 2013
From: marex at denx.de (Marek Vasut)
Date: Tue, 28 May 2013 20:29:55 +0200
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <20130528062711.GB19608@S2101-09.ap.freescale.net>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <201305280656.27472.marex@denx.de>
 <20130528062711.GB19608@S2101-09.ap.freescale.net>
Message-ID: <201305282029.55905.marex@denx.de>

Dear Shawn Guo,

> On Tue, May 28, 2013 at 06:56:27AM +0200, Marek Vasut wrote:
> > What is the problem you observe?
> 
> The audio playback gives silent output.

You mean like nothing? Zilch? Not even a loud pop on the start/stop of playback?

I have no issues with audio + touchscreen on m28evk since like 3.7 or so (even 
before I pushed the driver mainline), so this is weird. Do you have your 
speakers connected to LineOut or Speaker output from the SGTL5000 ? In case of 
LineOut, is your on-board amplifier on ?

Best regards,
Marek Vasut


From sebastian.hesselbarth at gmail.com  Tue May 28 16:01:19 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 28 May 2013 22:01:19 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130528165401.GX31290@titan.lakedaemon.net>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130528154047.GT31290@titan.lakedaemon.net> <20130528175343.77c6353d@skate>
 <20130528165401.GX31290@titan.lakedaemon.net>
Message-ID: <51A50D0F.5010909@gmail.com>

On 05/28/2013 06:54 PM, Jason Cooper wrote:
>> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
>>> I'm posting the revised version as replies to patches 1, 5 and 6. Please
>>> let me know if I messed it up.  I'd like to send the PR for these
>>> shortly.
>
> $ git checkout v3.10-rc3
> $ git merge mvebu/of_pci
> $ git merge mvebu/pcie
> $ git merge mvebu/seb_clk

After manually resolving a merge conflict in arch/arm/mach-mvebu/Kconfig
I can see no obvious regression on neither Dove nor Kirkwood.

Sebastian


From jason at lakedaemon.net  Tue May 28 16:03:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 16:03:25 -0400
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <51A50D0F.5010909@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130528154047.GT31290@titan.lakedaemon.net>
 <20130528175343.77c6353d@skate>
 <20130528165401.GX31290@titan.lakedaemon.net>
 <51A50D0F.5010909@gmail.com>
Message-ID: <20130528200325.GF31290@titan.lakedaemon.net>

On Tue, May 28, 2013 at 10:01:19PM +0200, Sebastian Hesselbarth wrote:
> On 05/28/2013 06:54 PM, Jason Cooper wrote:
> >>On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> >>>I'm posting the revised version as replies to patches 1, 5 and 6. Please
> >>>let me know if I messed it up.  I'd like to send the PR for these
> >>>shortly.
> >
> >$ git checkout v3.10-rc3
> >$ git merge mvebu/of_pci
> >$ git merge mvebu/pcie
> >$ git merge mvebu/seb_clk
> 
> After manually resolving a merge conflict in arch/arm/mach-mvebu/Kconfig
> I can see no obvious regression on neither Dove nor Kirkwood.

Great, thanks, Sebastian!

Jason.


From davem at davemloft.net  Tue May 28 16:09:20 2013
From: davem at davemloft.net (David Miller)
Date: Tue, 28 May 2013 13:09:20 -0700 (PDT)
Subject: [PATCHv2 1/3] net: phy: prevent linking breakage
In-Reply-To: <1369741403-25315-2-git-send-email-alexandre.belloni@free-electrons.com>
References: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
 <1369741403-25315-2-git-send-email-alexandre.belloni@free-electrons.com>
Message-ID: <20130528.130920.1604291112518863799.davem@davemloft.net>

From: Alexandre Belloni <alexandre.belloni at free-electrons.com>
Date: Tue, 28 May 2013 13:43:21 +0200

> phy_register_fixup{,_for_uid,_for_id} are called from arch/, quite
> often, there is no protection to check whether CONFIG_PHYLIB=y which is
> the only case where this would work. Having phylib as a module or not
> compiled at all will result in that kind of linking failure:
> 
> arch/arm/mach-at91/built-in.o: In function `ksz9021rn_phy_fixup':
> :(.text+0x1174): undefined reference to `mdiobus_write'
> :(.text+0x1188): undefined reference to `mdiobus_write'
> :(.text+0x119c): undefined reference to `mdiobus_write'
> :(.text+0x11b0): undefined reference to `mdiobus_write'
> arch/arm/mach-at91/built-in.o: In function `sama5_dt_device_init':
> :(.init.text+0x1e34): undefined reference to `phy_register_fixup_for_uid'
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni at free-electrons.com>

This is the wrong way to go about this.

If the arch code absolutely requires CONFIG_PHYLIB=y then express that
dependency in the arch Kconfig.  The arch code in question should not
be compiled at all if CONFIG_PHYLIB has an incompatible setting.


From arnd at linaro.org  Tue May 28 16:11:28 2013
From: arnd at linaro.org (Arnd Bergmann)
Date: Tue, 28 May 2013 22:11:28 +0200
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
References: <1365746856-7772-2-git-send-email-manjunath.goudar@linaro.org>
 <1369746291-21788-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <201305282211.28563.arnd@linaro.org>

On Tuesday 28 May 2013, Manjunath Goudar wrote:
> This series of patches begins the process of splitting ohci-hcd up into
> a core library module and independent pci driver modules.
> 

Seems to basically work now, but I'm getting run-time errors after
loading the driver, with patch 1/3 applied:

[15916.438452] input: Logitech USB-PS/2 Optical Mouse as /devices/pci0000:00/0000:00:12.0/usb3/3-1/3-1:1.0/input/input26
[15916.438584] hid-generic 0003:046D:C050.0017: input,hidraw0: USB HID v1.10 Mouse [Logitech USB-PS/2 Optical Mouse] on usb-0000:00:12.0-1/input0
[15917.465597] usb 3-3: new full-speed USB device number 3 using ohci-pci
[15917.636712] usb 3-3: New USB device found, idVendor=0ccd, idProduct=0077
[15917.636717] usb 3-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[15917.636721] usb 3-3: Product: USB PnP Sound Device
[15917.636724] usb 3-3: Manufacturer: C-Media Electronics Inc.      
[15917.812827] input: C-Media Electronics Inc.       USB PnP Sound Device as /devices/pci0000:00/0000:00:12.0/usb3/3-3/3-3:1.3/input/input27
[15917.812919] hid-generic 0003:0CCD:0077.0018: input,hidraw1: USB HID v1.00 Device [C-Media Electronics Inc.       USB PnP Sound Device] on usb-0000:00:12.0-3/input3
[15918.789906] cannot submit urb (err = -18)
[15918.790163] cannot submit urb (err = -18)
[15918.842095] usb 7-1: new full-speed USB device number 2 using ohci-pci
[15919.883135] cannot submit urb (err = -18)
[15919.883604] cannot submit urb (err = -18)
[15919.883613] cannot submit urb (err = -18)
[15919.883616] cannot submit urb (err = -18)
[15919.883619] cannot submit urb (err = -18)
[15919.883623] cannot submit urb (err = -18)
[15919.883626] cannot submit urb (err = -18)
[15919.883629] cannot submit urb (err = -18)
[15919.883632] cannot submit urb (err = -18)
[15919.883639] delay: estimated 354, actual 1
[15919.883644] cannot submit urb (err = -18)
[15919.883647] delay: estimated 353, actual 0
[15919.883651] cannot submit urb (err = -18)

	Arnd


From jason at lakedaemon.net  Tue May 28 16:21:40 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 16:21:40 -0400
Subject: [GIT PULL 1/5] of/pci dependency for mvebu/arm-soc (resend)
Message-ID: <20130528202140.GG31290@titan.lakedaemon.net>

Olof,

This is a resend of the previous PR.  For mvebu/of_pci it is the exact
same.


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/of_pci-3.11

for you to fetch changes up to 4e23d3f505e8acfeac7cc33d4113fbb5a25c3090:

  of/pci: Add of_pci_parse_bus_range() function (2013-05-19 20:30:10 +0000)

----------------------------------------------------------------
of/pci changes for v3.11

 - parse DT ranges property
 - add of_pci_get_devfn()
 - add of_pci_parse_bus_range()

Note:
 - mvebu/pcie will depend on this branch
 - work by LinusW and possibly Arnd will depend on this branch

----------------------------------------------------------------
Andrew Murray (1):
      of/pci: Provide support for parsing PCI DT ranges property

Thierry Reding (2):
      of/pci: Add of_pci_get_devfn() function
      of/pci: Add of_pci_parse_bus_range() function

 drivers/of/address.c       | 67 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/of/of_pci.c        | 59 ++++++++++++++++++++++++++++++++++++----
 include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++
 include/linux/of_pci.h     |  2 ++
 4 files changed, 171 insertions(+), 5 deletions(-)


From john.stultz at linaro.org  Tue May 28 16:24:17 2013
From: john.stultz at linaro.org (John Stultz)
Date: Tue, 28 May 2013 13:24:17 -0700
Subject: [RFC PATCH 2/2] clocksource: dw_apb: allow build for architectures
 other than arm
In-Reply-To: <1369570367-994-2-git-send-email-baruch@tkos.co.il>
References: <1369570367-994-2-git-send-email-baruch@tkos.co.il>
Message-ID: <51A51271.2070506@linaro.org>

On 05/26/2013 05:12 AM, Baruch Siach wrote:
> ARM is the only architecture providing sched_clock.h and setup_sched_clock().
> Implement sched_clock() for use by other architectures.
>
> Cc: Ingo Molnar <mingo at redhat.com>
> Cc: Peter Zijlstra <peterz at infradead.org>
> Cc: John Stultz <john.stultz at linaro.org>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>
> Cc: Dinh Nguyen <dinguyen at altera.com>
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> ---
>   arch/arm/Kconfig                      |    1 +
>   drivers/clocksource/Kconfig           |    3 +++
>   drivers/clocksource/dw_apb_timer_of.c |   18 ++++++++++++++++++
>   3 files changed, 22 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1cacda4..7489604 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -47,6 +47,7 @@ config ARM
>   	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
>   	select HAVE_PERF_EVENTS
>   	select HAVE_REGS_AND_STACK_ACCESS_API
> +	select HAVE_SETUP_SCHED_CLOCK
>   	select HAVE_SYSCALL_TRACEPOINTS
>   	select HAVE_UID16
>   	select KTIME_SCALAR
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index e507ab7..0fd6d13 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -1,3 +1,6 @@
> +config HAVE_SETUP_SCHED_CLOCK
> +	bool
> +
>   config CLKSRC_OF
>   	bool
>   
> diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
> index 5a61ebc..9fdb4d3 100644
> --- a/drivers/clocksource/dw_apb_timer_of.c
> +++ b/drivers/clocksource/dw_apb_timer_of.c
> @@ -21,7 +21,11 @@
>   #include <linux/of_address.h>
>   #include <linux/of_irq.h>
>   
> +#ifdef CONFIG_HAVE_SETUP_SCHED_CLOCK
>   #include <asm/sched_clock.h>
> +#else
> +#include <linux/sched.h>
> +#endif
>   
>   static void timer_get_base_and_rate(struct device_node *np,
>   				    void __iomem **base, u32 *rate)
> @@ -73,6 +77,9 @@ static void add_clocksource(struct device_node *source_timer)
>   }
>   
>   static void __iomem *sched_io_base;
> +#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
> +static u64 sched_clock_mult __read_mostly;
> +#endif
>   
>   static u32 read_sched_clock(void)
>   {
> @@ -97,7 +104,11 @@ static void init_sched_clock(void)
>   	timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
>   	of_node_put(sched_timer);
>   
> +#ifdef CONFIG_HAVE_SETUP_SCHED_CLOCK
>   	setup_sched_clock(read_sched_clock, 32, rate);
> +#else
> +	sched_clock_mult = NSEC_PER_SEC / rate;
> +#endif
>   }

Can you rework this to not use #ifdefs within the function? They make it 
annoying to read the code.

Instead maybe have a local setup_sched_clock() function that sets the 
mult value for the !CONFIG_HAVE_SETUP_SCHED_CLOCK case?

>   
>   static const struct of_device_id osctimer_ids[] __initconst = {
> @@ -124,3 +135,10 @@ void __init dw_apb_timer_init(void)
>   
>   	init_sched_clock();
>   }
> +
> +#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
> +unsigned long long notrace sched_clock()
> +{
> +	return read_sched_clock() * sched_clock_mult;
> +}
> +#endif

Also, can you try to condense the number of #ifndef 
CONFIG_HAVE_SETUP_SCHED_CLOCK checks to one, and consolidate the needed 
functions all in that one conditional?

thanks
-john



From jason at lakedaemon.net  Tue May 28 16:24:33 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 16:24:33 -0400
Subject: [GIT PULL 2/5] ARM: mvebu: pcie driver for v3.11 (round 2 cumulative)
In-Reply-To: <20130528202140.GG31290@titan.lakedaemon.net>
References: <20130528202140.GG31290@titan.lakedaemon.net>
Message-ID: <20130528202433.GH31290@titan.lakedaemon.net>


The following changes since commit 4e23d3f505e8acfeac7cc33d4113fbb5a25c3090:

  of/pci: Add of_pci_parse_bus_range() function (2013-05-19 20:30:10 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/pcie-3.11-2

for you to fetch changes up to 3d9939c92efdd4ced672b94994959ca71b141cb8:

  pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)

----------------------------------------------------------------
mvebu pcie driver for v3.11 (round 2, bugfix)

 - mvebu pcie
    - fix return value check in mvebu_pcie_probe()

depends
 - mvebu/of_pci

----------------------------------------------------------------
Thomas Petazzoni (4):
      clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
      clk: mvebu: add more PCIe clocks for Armada XP
      pci: PCIe driver for Marvell Armada 370/XP systems
      arm: mvebu: PCIe support is now available on mvebu

Wei Yongjun (1):
      pci: mvebu: fix return value check in mvebu_pcie_probe()

 .../devicetree/bindings/pci/mvebu-pci.txt          | 220 ++++++
 arch/arm/mach-mvebu/Kconfig                        |   2 +
 drivers/clk/mvebu/clk-gating-ctrl.c                |  18 +-
 drivers/pci/Kconfig                                |   2 +
 drivers/pci/Makefile                               |   3 +
 drivers/pci/host/Kconfig                           |   8 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pci-mvebu.c                       | 880 +++++++++++++++++++++
 8 files changed, 1128 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
 create mode 100644 drivers/pci/host/Kconfig
 create mode 100644 drivers/pci/host/Makefile
 create mode 100644 drivers/pci/host/pci-mvebu.c


From jason at lakedaemon.net  Tue May 28 16:26:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 16:26:32 -0400
Subject: [GIT PULL 3/5] ARM: kirkwood: pcie driver for v3.11
In-Reply-To: <20130528202433.GH31290@titan.lakedaemon.net>
References: <20130528202140.GG31290@titan.lakedaemon.net>
 <20130528202433.GH31290@titan.lakedaemon.net>
Message-ID: <20130528202632.GI31290@titan.lakedaemon.net>


The following changes since commit 3d9939c92efdd4ced672b94994959ca71b141cb8:

  pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/pcie_kw-3.11

for you to fetch changes up to 0d0632f523fa040b307688ae421a1debf79af2d7:

  arm: kirkwood: convert db-88f6281/db-88f6282 to the Device Tree (2013-05-27 16:02:13 +0000)

----------------------------------------------------------------
mvebu pcie driver (kirkwood) for v3.11

 - kirkwood
    - enable pcie driver
    - migrate boards over to pcie dt init

depends
 - mvebu/pcie
    - mvebu/of_pci

----------------------------------------------------------------
Thomas Petazzoni (8):
      pci: mvebu: enable driver usage on Kirkwood
      arm: kirkwood: move PCIe window init to legacy driver
      arm: kirkwood: add SoC-level Device Tree data for PCIe interfaces
      arm: kirkwood: convert Iomega Iconnect to use DT for the PCIe interface
      arm: kirkwood: convert MPL CEC4 to use DT for the PCIe interface
      arm: kirkwood: convert ZyXEL NSA310 to use DT for the PCIe interface
      arm: kirkwood: convert QNAP TS219 to use DT for the PCIe interface
      arm: kirkwood: convert db-88f6281/db-88f6282 to the Device Tree

 .../devicetree/bindings/pci/mvebu-pci.txt          |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/kirkwood-6281.dtsi               |  31 ++++++
 arch/arm/boot/dts/kirkwood-6282.dtsi               |  48 +++++++++
 arch/arm/boot/dts/kirkwood-db-88f6281.dts          |  30 ++++++
 arch/arm/boot/dts/kirkwood-db-88f6282.dts          |  34 +++++++
 arch/arm/boot/dts/kirkwood-db.dtsi                 |  89 +++++++++++++++++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   8 ++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   8 ++
 arch/arm/boot/dts/kirkwood-nsa310.dts              |   8 ++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |   3 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |   3 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   9 +-
 arch/arm/boot/dts/kirkwood.dtsi                    |   1 +
 arch/arm/mach-kirkwood/Kconfig                     |  21 ++--
 arch/arm/mach-kirkwood/Makefile                    |   3 +-
 arch/arm/mach-kirkwood/board-db88f628x-bp.c        |  24 +++++
 arch/arm/mach-kirkwood/board-dt.c                  |   6 ++
 arch/arm/mach-kirkwood/board-iconnect.c            |   8 --
 arch/arm/mach-kirkwood/board-mplcec4.c             |   1 -
 arch/arm/mach-kirkwood/board-nsa310.c              |  25 -----
 arch/arm/mach-kirkwood/board-ts219.c               |  10 --
 arch/arm/mach-kirkwood/common.c                    |  24 -----
 arch/arm/mach-kirkwood/common.h                    |   6 ++
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        | 108 ---------------------
 arch/arm/mach-kirkwood/pcie.c                      |  22 +++++
 drivers/pci/host/Kconfig                           |   2 +-
 drivers/pci/host/pci-mvebu.c                       |   1 +
 28 files changed, 339 insertions(+), 197 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6281.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6282.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-db.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-db88f628x-bp.c
 delete mode 100644 arch/arm/mach-kirkwood/board-nsa310.c
 delete mode 100644 arch/arm/mach-kirkwood/db88f6281-bp-setup.c


From jason at lakedaemon.net  Tue May 28 16:28:28 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 16:28:28 -0400
Subject: [GIT PULL 4/5] ARM: mvebu: pcie bridge enhancements for v3.11
In-Reply-To: <20130528202433.GH31290@titan.lakedaemon.net>
References: <20130528202140.GG31290@titan.lakedaemon.net>
 <20130528202433.GH31290@titan.lakedaemon.net>
Message-ID: <20130528202828.GJ31290@titan.lakedaemon.net>


The following changes since commit 3d9939c92efdd4ced672b94994959ca71b141cb8:

  pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/pcie_bridge-3.11

for you to fetch changes up to 6eb237c41acc1cf00b3b1176ad4a0ed3f221d630:

  pci: mvebu: fix the emulation of the status register (2013-05-27 16:01:15 +0000)

----------------------------------------------------------------
mvebu pcie driver (bridge) for v3.11

 - mvebu
    - allow enumeration of devices beyond physical bridges
    - remove faking the slot location
    - fix status register emulation

depends
 - mvebu/pcie
    -mvebu/of_pci

----------------------------------------------------------------
Thomas Petazzoni (3):
      pci: mvebu: no longer fake the slot location of downstream devices
      pci: mvebu: allow the enumeration of devices beyond physical bridges
      pci: mvebu: fix the emulation of the status register

 drivers/pci/host/pci-mvebu.c | 55 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 44 insertions(+), 11 deletions(-)


From jason at lakedaemon.net  Tue May 28 16:30:21 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 16:30:21 -0400
Subject: [GIT PULL 5/5] ARM: mvebu: clock SoC reorg for v3.11
In-Reply-To: <20130528202433.GH31290@titan.lakedaemon.net>
References: <20130528202140.GG31290@titan.lakedaemon.net>
 <20130528202433.GH31290@titan.lakedaemon.net>
Message-ID: <20130528203021.GK31290@titan.lakedaemon.net>


The following changes since commit 3d9939c92efdd4ced672b94994959ca71b141cb8:

  pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/seb_clk-3.11

for you to fetch changes up to 279f759aac0990402407d97b21475677f499f4ac:

  clk: mvebu: desintegrate obsolete file (2013-05-28 15:18:37 +0000)

----------------------------------------------------------------
mvebu clock restructuring for v3.11

 - clk: mvebu
    - reorganize by SoC to remove built up #ifdefs
    - add clk flags per clock gate

Note: this branch only depends on mvebu/pcie in order to prevent managing a
tricky modify/remove file merge conflict.  By rebasing on mvebu/pcie, we are
able to build the resolution into the patch series.  The change is small, and
has been tested by the respective authors.

depends:
 - mvebu/pcie
    - mvebu/of_pci

----------------------------------------------------------------
Sebastian Hesselbarth (10):
      clk: mvebu: introduce per-clock-gate flags
      clk: mvebu: add common clock functions for core clk and clk gating
      clk: mvebu: add Dove SoC-centric clock init
      clk: mvebu: add Kirkwood SoC-centric clock init
      clk: mvebu: add Armada 370 SoC-centric clock init
      clk: mvebu: add Armada XP SoC-centric clock init
      ARM: dove: move DT boards to SoC-centric clock init
      ARM: kirkwood: move DT boards to SoC-centric clock init
      ARM: mvebu: move DT boards to SoC-centric clock init
      clk: mvebu: desintegrate obsolete file

 arch/arm/mach-dove/Kconfig          |   3 +-
 arch/arm/mach-dove/board-dt.c       |   3 +-
 arch/arm/mach-dove/common.c         |   1 -
 arch/arm/mach-kirkwood/Kconfig      |   3 +-
 arch/arm/mach-kirkwood/board-dt.c   |   3 +-
 arch/arm/mach-mvebu/Kconfig         |   5 +-
 arch/arm/mach-mvebu/armada-370-xp.c |   4 +-
 drivers/clk/mvebu/Kconfig           |  25 +-
 drivers/clk/mvebu/Makefile          |   8 +-
 drivers/clk/mvebu/armada-370.c      | 176 ++++++++++
 drivers/clk/mvebu/armada-xp.c       | 210 +++++++++++
 drivers/clk/mvebu/clk-core.c        | 675 ------------------------------------
 drivers/clk/mvebu/clk-core.h        |  18 -
 drivers/clk/mvebu/clk-gating-ctrl.c | 256 --------------
 drivers/clk/mvebu/clk-gating-ctrl.h |  22 --
 drivers/clk/mvebu/clk.c             |  23 --
 drivers/clk/mvebu/common.c          | 163 +++++++++
 drivers/clk/mvebu/common.h          |  48 +++
 drivers/clk/mvebu/dove.c            | 194 +++++++++++
 drivers/clk/mvebu/kirkwood.c        | 247 +++++++++++++
 include/linux/clk/mvebu.h           |  22 --
 21 files changed, 1072 insertions(+), 1037 deletions(-)
 create mode 100644 drivers/clk/mvebu/armada-370.c
 create mode 100644 drivers/clk/mvebu/armada-xp.c
 delete mode 100644 drivers/clk/mvebu/clk-core.c
 delete mode 100644 drivers/clk/mvebu/clk-core.h
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
 delete mode 100644 drivers/clk/mvebu/clk.c
 create mode 100644 drivers/clk/mvebu/common.c
 create mode 100644 drivers/clk/mvebu/common.h
 create mode 100644 drivers/clk/mvebu/dove.c
 create mode 100644 drivers/clk/mvebu/kirkwood.c
 delete mode 100644 include/linux/clk/mvebu.h


From john.stultz at linaro.org  Tue May 28 16:34:19 2013
From: john.stultz at linaro.org (John Stultz)
Date: Tue, 28 May 2013 13:34:19 -0700
Subject: [PATCH 1/2] clocksource: dw_apb: remove unused header
In-Reply-To: <1369570367-994-1-git-send-email-baruch@tkos.co.il>
References: <1369570367-994-1-git-send-email-baruch@tkos.co.il>
Message-ID: <51A514CB.7090808@linaro.org>

On 05/26/2013 05:12 AM, Baruch Siach wrote:
> The time.h header seems not to be used by current code. Removing this include
> allows the driver to build on other architecture that do not have this header.
>
> Cc: Ingo Molnar <mingo at redhat.com>
> Cc: Peter Zijlstra <peterz at infradead.org>
> Cc: John Stultz <john.stultz at linaro.org>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>
> Cc: Dinh Nguyen <dinguyen at altera.com>
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> ---
I've gone ahead and queued this for 3.11

thanks
-john



From nicolas.pitre at linaro.org  Tue May 28 16:59:13 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 28 May 2013 16:59:13 -0400 (EDT)
Subject: [PATCH] ARM: fix kernel decompressor compilation error with
 CONFIG_DEBUG_SEMIHOSTING
Message-ID: <alpine.LFD.2.03.1305281654120.1918@syhkavp.arg>


... and add semihosting output support to the decompressor while at it.

Signed-off-by: Nicolas Pitre <nico at linaro.org>

diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6e8382d5b7..5392ee6333 100644
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -1,6 +1,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#ifndef CONFIG_DEBUG_SEMIHOSTING
+
 #include CONFIG_DEBUG_LL_INCLUDE
 
 ENTRY(putc)
@@ -10,3 +12,29 @@ ENTRY(putc)
 	busyuart r3, r1
 	mov	 pc, lr
 ENDPROC(putc)
+
+#else
+
+ENTRY(putc)
+	adr	r1, 1f
+	ldmia	r1, {r2, r3}
+	add	r2, r2, r1
+	ldr	r1, [r2, r3]
+	strb	r0, [r1]
+	mov	r0, #0x03		@ SYS_WRITEC
+   ARM(	svc	#0x123456	)
+ THUMB(	svc	#0xab		)
+	mov	pc, lr
+	.align	2
+1:	.word	_GLOBAL_OFFSET_TABLE_ - .
+	.word	semi_writec_buf(GOT)
+ENDPROC(putc)
+
+	.bss
+	.global	semi_writec_buf
+	.type   semi_writec_buf, %object
+semi_writec_buf:
+	.space	4
+	.size	semi_writec_buf, 4
+
+#endif


From rjw at sisk.pl  Tue May 28 17:26:44 2013
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Tue, 28 May 2013 23:26:44 +0200
Subject: [PATCH] cpuidle: improve governor Kconfig options
In-Reply-To: <51A4AFD9.3020109@linaro.org>
References: <1369688458-9114-1-git-send-email-daniel.lezcano@linaro.org>
 <5938372.bcA6BTeOGP@vostro.rjw.lan> <51A4AFD9.3020109@linaro.org>
Message-ID: <1687661.MEWgzcOBGL@vostro.rjw.lan>

On Tuesday, May 28, 2013 03:23:37 PM Daniel Lezcano wrote:
> On 05/28/2013 02:42 PM, Rafael J. Wysocki wrote:
> > On Tuesday, May 28, 2013 02:23:00 PM Daniel Lezcano wrote:
> >> On 05/28/2013 01:46 PM, Rafael J. Wysocki wrote:
> >>> On Monday, May 27, 2013 11:00:58 PM Daniel Lezcano wrote:
> >>>> Each governor is suitable for different kernel configurations: the menu
> >>>> governor suits better for a tickless system, while the ladder governor fits
> >>>> better for a periodic timer tick system.
> >>>>
> >>>> The Kconfig does not allow to [un]select a governor, thus both are compiled in
> >>>> the kernel but the init order makes the menu governor to be the last one to be
> >>>> registered, so becoming the default. The only way to switch back to the ladder
> >>>> governor is to enable the sysfs governor switch in the kernel command line.
> >>>>
> >>>> Because it seems nobody complained about this, the menu governor is used by
> >>>> default most of the time on the system, having both governors is not really
> >>>> necessary on a tickless system but there isn't a config option to disable one
> >>>> or another governor.
> >>>>
> >>>> Create a submenu for cpuidle and add a label for each governor, so we can see
> >>>> the option in the menu config and enable/disable it.
> >>>>
> >>>> The governors will be enabled depending on the CONFIG_NO_HZ option:
> >>>>  - If CONFIG_NO_HZ is set, then the menu governor is selected and the ladder
> >>>>    governor is optional, defaulting to 'no'
> >>>
> >>> Why not defaulting to 'yes'?  That'd be backwards compatible, wouldn't it?
> >>
> >> Yes, that wouldn't be backward compatible but who wants the ladder
> >> governor which is less efficient with a tickless system ?
> > 
> > I don't know and this isn't the right question to ask I think.
> > 
> > You need to ask who uses the ladder governor with CONFIG_NO_HZ and you need to
> > avoid making changes that aren't backwards compatible if you don't know the
> > answer (which I'm pretty sure is the case).
> > 
> > I'd prefer to default to 'yes' to start with and then to change the
> > default to 'no' after a couple of cycles, possibly.
> > 
> >>>>  - If CONFIG_NO_HZ is not set, then the ladder governor is selected and the
> >>>>    menu governor is optional, defaulting to 'no'
> >>>
> >>> Are you sure this is not going to introduce regressions with CONFIG_NO_HZ
> >>> unset?
> >>
> >> Yes, a system configured with a periodic tick will use the ladder
> >> instead of the menu governor (which is less efficient on this
> >> configuration).
> > 
> > Well, "less efficient" meaning what exactly?  Less power-efficient or less
> > efficient performance-wise?
> 
> less power efficient.

I thought so, but that's really important, because some people *do* care about
performance.  In the context of changes like this one we always need to talk
about both power and performance.  For example, when you're saying that
changing something may lead to better energy saving behavior, you should also
say what the impact of that change on performance is going to be.

Thanks,
Rafael


-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.


From hechtb at gmail.com  Tue May 28 17:20:34 2013
From: hechtb at gmail.com (Bastian Hecht)
Date: Tue, 28 May 2013 23:20:34 +0200
Subject: [PATCH 09/12] ARM: shmobile: r8a7740: Add Suspend-To-RAM A3SM
In-Reply-To: <20130528052900.GB25005@verge.net.au>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-10-git-send-email-horms+renesas@verge.net.au>
 <20130528035019.GI13532@quad.lixom.net>
 <20130528052900.GB25005@verge.net.au>
Message-ID: <CABYn4syN6_RdQ4M7vQvCQTLaf9DGtwBNxZ5E-qJfnW0j43oOVw@mail.gmail.com>

2013/5/28 Simon Horman <horms at verge.net.au>:
> On Mon, May 27, 2013 at 08:50:19PM -0700, Olof Johansson wrote:
>> Hi,
>>
>> On Mon, May 27, 2013 at 05:59:50PM +0900, Simon Horman wrote:
>> > From: Bastian Hecht <hechtb at gmail.com>
>> >
>> > We add 2 Suspend to RAM modes:
>> > - A3SM PLL0 on/off:     Power domain A3SM that contains the ARM core
>> >                         and the 2nd level cache with either PLL0 on
>> >                         or off
>> >
>> > As the suspend to memory mechanism we use A3SM PLL off. A3SM PLL on
>> > is included here too, so CPUIdle can use both power down modes (not
>> > included in this patch).
>> >
>> > The setup of the SYSC regarding the external IRQs is taken from
>> > pm-sh7372.c from Magnus Damm.
>> >
>> > Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
>>
>> Missing S-o-b from you, Simon?
>
> Oops sorry about that.
>
>> > +   .text
>> > +ENTRY(v7_cpu_resume)
>> > +   bl      v7_invalidate_l1
>> > +   b       cpu_resume
>> > +ENDPROC(v7_cpu_resume)
>>
>> This is a global namespace so it'll conflict with i.MX whenever
>> you multiplatform enable shmobile. Might want to pick a more
>> unique name.
>
> Bastian, could you suggest an alternate name?

It should really be a temporary thing, as this should be handled in
the generic ARM code. So how about:

r8a7740_cpu_resume()

Cheers,

 Bastian


From jgchunter at gmail.com  Tue May 28 17:20:44 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Tue, 28 May 2013 22:20:44 +0100
Subject: [PATCH] ARM: OMAP2+: timer: initialize before using oh_name
In-Reply-To: <1369722288-15592-1-git-send-email-afzal@ti.com>
References: <1369722288-15592-1-git-send-email-afzal@ti.com>
Message-ID: <51A51FAC.5090606@gmail.com>


On 28/05/13 07:24, Afzal Mohammed wrote:
> of_property_read_string_index(...,&oh_name) in omap_dm_timer_init_one
> does not alter the value of 'oh_name' even if the relevant function
> fails and as 'oh_name' in stack may have a non-zero value, it would
> be misunderstood by timer code that DT has specified "ti,hwmod"
> property for timer. 'oh_name' in this scenario would be a junk value,
> this would result in module not being enabled by hwmod API's for
> timer, and in turn crash.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
>  arch/arm/mach-omap2/timer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index f8b23b8..8e0c390 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -220,7 +220,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
>  					 int posted)
>  {
>  	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
> -	const char *oh_name;
> +	const char *oh_name = NULL;
>  	struct device_node *np;
>  	struct omap_hwmod *oh;
>  	struct resource irq, mem;

Thanks!

Acked-by: Jon Hunter <jgchunter at gmail.com>

Cheers
Jon



From jgchunter at gmail.com  Tue May 28 17:25:09 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Tue, 28 May 2013 22:25:09 +0100
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
Message-ID: <51A520B5.8040803@gmail.com>


On 27/05/13 15:37, Afzal Mohammed wrote:
> AM43x timer bindings.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
>  Documentation/devicetree/bindings/arm/omap/timer.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
> index d02e27c..70cb398 100644
> --- a/Documentation/devicetree/bindings/arm/omap/timer.txt
> +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
> @@ -14,6 +14,8 @@ Required properties:
>  			ti,omap5430-timer (applicable to OMAP543x devices)
>  			ti,am335x-timer	(applicable to AM335x devices)
>  			ti,am335x-timer-1ms (applicable to AM335x devices)
> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
>  
>  - reg:			Contains timer register address range (base address and
>  			length).

If you are adding more compatibility strings, then this implies that the
AM43x timers are not 100% compatible with any other device listed (such
as am335x or any omap device). That's fine but you should state that in
the changelog. If the AM43x timer registers are 100% compatible with
existing devices you should not add these.

Jon



From jgchunter at gmail.com  Tue May 28 17:26:05 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Tue, 28 May 2013 22:26:05 +0100
Subject: [PATCH v2 12/14] Documentation: dt: binding: omap: am43x counter
In-Reply-To: <755964dc45ae4f023540c05e5739fca87d0ea70b.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <755964dc45ae4f023540c05e5739fca87d0ea70b.1369658705.git.afzal@ti.com>
Message-ID: <51A520ED.9070106@gmail.com>


On 27/05/13 15:37, Afzal Mohammed wrote:
> AM43x 32K counter binding.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
>  Documentation/devicetree/bindings/arm/omap/counter.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt
> index 5bd8aa0..9c48dca 100644
> --- a/Documentation/devicetree/bindings/arm/omap/counter.txt
> +++ b/Documentation/devicetree/bindings/arm/omap/counter.txt
> @@ -2,6 +2,7 @@ OMAP Counter-32K bindings
>  
>  Required properties:
>  - compatible:	Must be "ti,omap-counter32k" for OMAP controllers
> +		"ti,am4372-counter32k","ti,omap-counter32k" for AM43x counter
>  - reg:		Contains timer register address range (base address and length)
>  - ti,hwmods:	Name of the hwmod associated to the counter, which is typically
>  		"counter_32k"

Changelog should state why this is needed.

Jon



From swarren at wwwdotorg.org  Tue May 28 17:30:29 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 15:30:29 -0600
Subject: [PATCH] ARM: tegra: rebuild tegra_defconfig
In-Reply-To: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>
References: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <51A521F5.2010206@wwwdotorg.org>

On 05/28/2013 11:26 AM, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> This simply rebuilds tegra_defconfig on top of next-20130520. As such, it
> should introduce no changes; simply moving entries around due to Kconfig
> ordering changes. The apparent exceptions are:
> 
> AUTO_ZRELADDR: Selected by ARM multi-platform support.
> MTD_CHAR: Removed in Kconfig.
> 
> This should make it easier to create future defconfig patches on top of
> linux-next, since all the extraneous diffs have been removed. It also
> makes it more likely that once 3.12 comes around, this defconfig will
> already match what's required there.

I've applied this (squashed it into) Tegra's for-3.11/defconfig branch.


From swarren at wwwdotorg.org  Tue May 28 17:31:09 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 15:31:09 -0600
Subject: [PATCH] ARM: tegra: add audio-related nodes to Tegra114 DT
In-Reply-To: <1369763031-13687-1-git-send-email-swarren@wwwdotorg.org>
References: <1369763031-13687-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <51A5221D.60201@wwwdotorg.org>

On 05/28/2013 11:43 AM, Stephen Warren wrote:
> Add nodes for the Tegra114 AHUB and I2S controllers.

I have applied this to Tegra's for-3.11/dt branch.


From swarren at wwwdotorg.org  Tue May 28 17:31:34 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 15:31:34 -0600
Subject: [PATCH V2] ARM: tegra: add cpu_disable for hotplug
In-Reply-To: <1369764881-20520-1-git-send-email-swarren@wwwdotorg.org>
References: <1369764881-20520-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <51A52236.5030001@wwwdotorg.org>

On 05/28/2013 12:14 PM, Stephen Warren wrote:
> From: Joseph Lo <josephl at nvidia.com>
> 
> The Tegra114 could hotplug the CPU0, but the common cpu_disable didn't
> support that. Adding a Tegra specific cpu_disable function for it.
> 
> Signed-off-by: Joseph Lo <josephl at nvidia.com>
> [swarren: adjusted the switch statement to be future-proof]
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

I have applied this to Tegra's for-3.11/soc branch.


From linux at baker-net.org.uk  Tue May 28 17:36:13 2013
From: linux at baker-net.org.uk (Adam Baker)
Date: Tue, 28 May 2013 22:36:13 +0100
Subject: Kirkwood CPU Freq driver
In-Reply-To: <20130526180513.GF31290@titan.lakedaemon.net>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
 <20130526180513.GF31290@titan.lakedaemon.net>
Message-ID: <51A5234D.9030100@baker-net.org.uk>

On 26/05/13 19:05, Jason Cooper wrote:
> On Sun, May 26, 2013 at 10:36:14AM +0200, Andrew Lunn wrote:
>> On Sat, May 25, 2013 at 10:32:04PM +0100, Adam Baker wrote:
>>> I've been trying to test Andrew Lunn's work creating a CPU Idle
>>> driver for Kirkwood.
>>
>> Thanks for testing this. I must admit, i never tested it once the
>> first rc came out. I clearly should of, because its broken. It was a
>> three part patch series, and only part 1/3 made it in. Hence the
>> issues you are seeing.
>>
>> Jason, please can you pick up:
>>
>> https://patchwork.kernel.org/patch/2051401/
>> https://patchwork.kernel.org/patch/2080931/
>
> Yep, got them in now.  Sorry for the mix up.
>

I've now tested with the first of these patches applied and the changes 
from the second added to my .config

To get it to work I had to follow the instructions in the Documentation 
to add the cpus entry to kirkwood.dtsi so I'll post that as a patch in a 
day or two but after doing that I have a working cpufreq driver.

Measuring the power consumption of my NAS server I observed a slight 
reduction in power consumption when the clock rate was reduced. I 
haven't yet measured for long enough to get an accurate measurement but 
it looks like maybe 1/4 W power saving.

Feel free to add

Tested-by: Adam Baker <linux at baker-net.org.uk>

Regards

Adam



From daniel.lezcano at linaro.org  Tue May 28 17:39:28 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 28 May 2013 23:39:28 +0200
Subject: [PATCH] cpuidle: improve governor Kconfig options
In-Reply-To: <1687661.MEWgzcOBGL@vostro.rjw.lan>
References: <1369688458-9114-1-git-send-email-daniel.lezcano@linaro.org>
 <5938372.bcA6BTeOGP@vostro.rjw.lan> <51A4AFD9.3020109@linaro.org>
 <1687661.MEWgzcOBGL@vostro.rjw.lan>
Message-ID: <51A52410.8090608@linaro.org>

On 05/28/2013 11:26 PM, Rafael J. Wysocki wrote:
> On Tuesday, May 28, 2013 03:23:37 PM Daniel Lezcano wrote:
>> On 05/28/2013 02:42 PM, Rafael J. Wysocki wrote:
>>> On Tuesday, May 28, 2013 02:23:00 PM Daniel Lezcano wrote:
>>>> On 05/28/2013 01:46 PM, Rafael J. Wysocki wrote:
>>>>> On Monday, May 27, 2013 11:00:58 PM Daniel Lezcano wrote:
>>>>>> Each governor is suitable for different kernel configurations: the menu
>>>>>> governor suits better for a tickless system, while the ladder governor fits
>>>>>> better for a periodic timer tick system.
>>>>>>
>>>>>> The Kconfig does not allow to [un]select a governor, thus both are compiled in
>>>>>> the kernel but the init order makes the menu governor to be the last one to be
>>>>>> registered, so becoming the default. The only way to switch back to the ladder
>>>>>> governor is to enable the sysfs governor switch in the kernel command line.
>>>>>>
>>>>>> Because it seems nobody complained about this, the menu governor is used by
>>>>>> default most of the time on the system, having both governors is not really
>>>>>> necessary on a tickless system but there isn't a config option to disable one
>>>>>> or another governor.
>>>>>>
>>>>>> Create a submenu for cpuidle and add a label for each governor, so we can see
>>>>>> the option in the menu config and enable/disable it.
>>>>>>
>>>>>> The governors will be enabled depending on the CONFIG_NO_HZ option:
>>>>>>  - If CONFIG_NO_HZ is set, then the menu governor is selected and the ladder
>>>>>>    governor is optional, defaulting to 'no'
>>>>>
>>>>> Why not defaulting to 'yes'?  That'd be backwards compatible, wouldn't it?
>>>>
>>>> Yes, that wouldn't be backward compatible but who wants the ladder
>>>> governor which is less efficient with a tickless system ?
>>>
>>> I don't know and this isn't the right question to ask I think.
>>>
>>> You need to ask who uses the ladder governor with CONFIG_NO_HZ and you need to
>>> avoid making changes that aren't backwards compatible if you don't know the
>>> answer (which I'm pretty sure is the case).
>>>
>>> I'd prefer to default to 'yes' to start with and then to change the
>>> default to 'no' after a couple of cycles, possibly.
>>>
>>>>>>  - If CONFIG_NO_HZ is not set, then the ladder governor is selected and the
>>>>>>    menu governor is optional, defaulting to 'no'
>>>>>
>>>>> Are you sure this is not going to introduce regressions with CONFIG_NO_HZ
>>>>> unset?
>>>>
>>>> Yes, a system configured with a periodic tick will use the ladder
>>>> instead of the menu governor (which is less efficient on this
>>>> configuration).
>>>
>>> Well, "less efficient" meaning what exactly?  Less power-efficient or less
>>> efficient performance-wise?
>>
>> less power efficient.
> 
> I thought so, but that's really important, because some people *do* care about
> performance.  In the context of changes like this one we always need to talk
> about both power and performance.  For example, when you're saying that
> changing something may lead to better energy saving behavior, you should also
> say what the impact of that change on performance is going to be

I fully agree with you but with this very specific case, when the
cpuidle is enabled in the system, it is to have the best trade-off
between performance and power saving. Using the ladder governor on a
tickless system is not power efficient and the performance is not
significantly improved. If the governor is too agressive in power saving
and impacts the performance the pm_qos will guarantee the needed
performance.

Desktop will use tickless system because they want power saving, thus
cpuidle and the menu governor is the best trade-off.

Server will want more responsiveness and will use a periodic timer tick
system, the cpuidle and the ladder suits better.

The pm_qos will ensure a latency for both governors.

But again I agree 100% with you and keeping the old behavior makes sense
until we sort this out clearly in the next cycles.

Thanks
  -- Daniel

-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From andrew at lunn.ch  Tue May 28 17:51:26 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 28 May 2013 23:51:26 +0200
Subject: Kirkwood CPU Freq driver
In-Reply-To: <51A5234D.9030100@baker-net.org.uk>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
 <20130526180513.GF31290@titan.lakedaemon.net>
 <51A5234D.9030100@baker-net.org.uk>
Message-ID: <20130528215126.GF7678@lunn.ch>

On Tue, May 28, 2013 at 10:36:13PM +0100, Adam Baker wrote:
> On 26/05/13 19:05, Jason Cooper wrote:
> >On Sun, May 26, 2013 at 10:36:14AM +0200, Andrew Lunn wrote:
> >>On Sat, May 25, 2013 at 10:32:04PM +0100, Adam Baker wrote:
> >>>I've been trying to test Andrew Lunn's work creating a CPU Idle
> >>>driver for Kirkwood.
> >>
> >>Thanks for testing this. I must admit, i never tested it once the
> >>first rc came out. I clearly should of, because its broken. It was a
> >>three part patch series, and only part 1/3 made it in. Hence the
> >>issues you are seeing.
> >>
> >>Jason, please can you pick up:
> >>
> >>https://patchwork.kernel.org/patch/2051401/
> >>https://patchwork.kernel.org/patch/2080931/
> >
> >Yep, got them in now.  Sorry for the mix up.
> >
> 
> I've now tested with the first of these patches applied and the
> changes from the second added to my .config
> 
> To get it to work I had to follow the instructions in the
> Documentation to add the cpus entry to kirkwood.dtsi so I'll post
> that as a patch in a day or two but after doing that I have a
> working cpufreq driver.

Great that you got it working. Something must of changed in the
generic code, since originally a cpu node was not required.

The clocks are not needed in node, so please don't list them.

> Measuring the power consumption of my NAS server I observed a slight
> reduction in power consumption when the clock rate was reduced. I
> haven't yet measured for long enough to get an accurate measurement
> but it looks like maybe 1/4 W power saving.

I don't have a killawatt meter etc, so i had no idea how much power it
actually saves.  Thanks for the figure.

	 Andrew


From swarren at wwwdotorg.org  Tue May 28 18:05:10 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 May 2013 16:05:10 -0600
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <51A520B5.8040803@gmail.com>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com>
Message-ID: <51A52A16.1040204@wwwdotorg.org>

On 05/28/2013 03:25 PM, Jon Hunter wrote:
> 
> On 27/05/13 15:37, Afzal Mohammed wrote:
>> AM43x timer bindings.
>>
>> Signed-off-by: Afzal Mohammed <afzal at ti.com>
>> ---
>>  Documentation/devicetree/bindings/arm/omap/timer.txt | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
>> index d02e27c..70cb398 100644
>> --- a/Documentation/devicetree/bindings/arm/omap/timer.txt
>> +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
>> @@ -14,6 +14,8 @@ Required properties:
>>  			ti,omap5430-timer (applicable to OMAP543x devices)
>>  			ti,am335x-timer	(applicable to AM335x devices)
>>  			ti,am335x-timer-1ms (applicable to AM335x devices)
>> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
>> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
>>  
>>  - reg:			Contains timer register address range (base address and
>>  			length).
> 
> If you are adding more compatibility strings, then this implies that the
> AM43x timers are not 100% compatible with any other device listed (such
> as am335x or any omap device). That's fine but you should state that in
> the changelog. If the AM43x timer registers are 100% compatible with
> existing devices you should not add these.

I'm not sure that's true; .dts files should always include a compatible
value that describes the most specific model of the HW, plus any
baseline compatible value that the HW is compatible with. This allows
any required quirks/fixes/... to be applied for the specific HW model
later even if nobody knows right now they'll be needed. Hence, defining
new compatible values doesn't necessarily mean incompatible HW.



From arno at natisbad.org  Tue May 28 18:15:09 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Wed, 29 May 2013 00:15:09 +0200
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use DT for
 the PCIe interface
Message-ID: <8738t6ycnm.fsf@natisbad.org>

Hi Jason and Thomas,

Thomas, I am following your work on PCIe support for a .dts file I am
working on for (Armada 370-based) Netgear ReadyNAS 102 and noticed your
set of patches to convert kirkwood-based boards to use it in order to
simplify/remove board specific code.

Jason, I gave your associated branch (jcooper/mvebu-next/pcie) a try
with following patch applied and can confirm USB 3.0 host controller
(connected to PCIe bus) is usable on Netgear ReadyNAS *Duo v2*
(88f6282-based brother of the 102).

Note that I had to s/of_pci_range_parser()/of_pci_range_parser_init()/
in drivers/pci/host/pci-mvebu.c to compile the kernel (this may already
have been fixed already):

CHK     kernel/config_data.h
drivers/pci/host/pci-mvebu.c: In function ?mvebu_pcie_probe?:
drivers/pci/host/pci-mvebu.c:742:2: error: implicit declaration of function ?of_pci_range_parser? [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[3]: *** [drivers/pci/host/pci-mvebu.o] Error 1
make[2]: *** [drivers/pci/host] Error 2
make[1]: *** [drivers/pci] Error 2
make[1]: *** Waiting for unfinished jobs....

Can one of you take the patch below into account? Or 

Cheers,

a+

Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
---
 arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts |    8 ++++++++
 arch/arm/mach-kirkwood/board-readynas.c                |    1 -
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab..f9706da 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -111,6 +111,14 @@
 			status = "okay";
 			nr-ports = <2>;
 		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				 status = "okay";
+			};
+		};
 	};
 
 	gpio-leds {
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20..341b82d 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
 void __init netgear_readynas_init(void)
 {
 	kirkwood_ge00_init(&netgear_readynas_ge00_data);
-	kirkwood_pcie_init(KW_PCIE0);
 }
-- 
1.7.10.4




From thomas.petazzoni at free-electrons.com  Tue May 28 18:20:53 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 29 May 2013 00:20:53 +0200
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use
 DT for the PCIe interface
In-Reply-To: <8738t6ycnm.fsf@natisbad.org>
References: <8738t6ycnm.fsf@natisbad.org>
Message-ID: <20130529002053.4b8ceb86@skate>

Dear Arnaud Ebalard,

On Wed, 29 May 2013 00:15:09 +0200, Arnaud Ebalard wrote:

> Thomas, I am following your work on PCIe support for a .dts file I am
> working on for (Armada 370-based) Netgear ReadyNAS 102 and noticed your
> set of patches to convert kirkwood-based boards to use it in order to
> simplify/remove board specific code.

Nice!

> Jason, I gave your associated branch (jcooper/mvebu-next/pcie) a try
> with following patch applied and can confirm USB 3.0 host controller
> (connected to PCIe bus) is usable on Netgear ReadyNAS *Duo v2*
> (88f6282-based brother of the 102).
> 
> Note that I had to s/of_pci_range_parser()/of_pci_range_parser_init()/
> in drivers/pci/host/pci-mvebu.c to compile the kernel (this may already
> have been fixed already):
> 
> CHK     kernel/config_data.h
> drivers/pci/host/pci-mvebu.c: In function ?mvebu_pcie_probe?:
> drivers/pci/host/pci-mvebu.c:742:2: error: implicit declaration of function ?of_pci_range_parser? [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors

You're probably not using the latest mvebu/pcie branch from jcooper. In
his branch, I see:

+       if (of_pci_range_parser_init(&parser, np))
+               return -EINVAL;

Which should do the right thing.

Could you check that you're running on top of the latest
jcooper/mvebu/pcie branch? Thanks!

> Can one of you take the patch below into account? Or 

You should probably resend your patch with a proper description. Your
description now includes a lot information about unrelated things (the
Armada 370 board you're working on, the build failure you had, etc.).

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sylvester.nawrocki at gmail.com  Tue May 28 18:37:29 2013
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Wed, 29 May 2013 00:37:29 +0200
Subject: [PATCH v6 1/9] drivers: phy: add generic PHY framework
In-Reply-To: <1367229812-30574-2-git-send-email-kishon@ti.com>
References: <1367229812-30574-1-git-send-email-kishon@ti.com>
 <1367229812-30574-2-git-send-email-kishon@ti.com>
Message-ID: <51A531A9.4030800@gmail.com>

Hi Kishon,

On 04/29/2013 12:03 PM, Kishon Vijay Abraham I wrote:
> The PHY framework provides a set of APIs for the PHY drivers to
> create/destroy a PHY and APIs for the PHY users to obtain a reference to the
> PHY with or without using phandle. For dt-boot, the PHY drivers should
> also register *PHY provider* with the framework.
>
> PHY drivers should create the PHY by passing id and ops like init, exit,
> power_on and power_off. This framework is also pm runtime enabled.
>
> The documentation for the generic PHY framework is added in
> Documentation/phy.txt and the documentation for dt binding can be found at
> Documentation/devicetree/bindings/phy/phy-bindings.txt
>
> Signed-off-by: Kishon Vijay Abraham I<kishon at ti.com>

Thanks for working on this. For the record, I plan to give this a try
in the end of this week, with my simple MIPI CSI/DSI PHY driver. I might
have some more comments then. For now just couple of remarks after
reading the documentation.

> ---
>   .../devicetree/bindings/phy/phy-bindings.txt       |   66 +++
>   Documentation/phy.txt                              |  123 +++++
>   MAINTAINERS                                        |    7 +
>   drivers/Kconfig                                    |    2 +
>   drivers/Makefile                                   |    2 +
>   drivers/phy/Kconfig                                |   13 +
>   drivers/phy/Makefile                               |    5 +
>   drivers/phy/phy-core.c                             |  539 ++++++++++++++++++++
>   include/linux/phy/phy.h                            |  248 +++++++++
>   9 files changed, 1005 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/phy-bindings.txt
>   create mode 100644 Documentation/phy.txt
>   create mode 100644 drivers/phy/Kconfig
>   create mode 100644 drivers/phy/Makefile
>   create mode 100644 drivers/phy/phy-core.c
>   create mode 100644 include/linux/phy/phy.h
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-bindings.txt b/Documentation/devicetree/bindings/phy/phy-bindings.txt
> new file mode 100644
> index 0000000..8ae844f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt
> @@ -0,0 +1,66 @@
> +This document explains only the device tree data binding. For general
> +information about PHY subsystem refer to Documentation/phy.txt
> +
> +PHY device node
> +===============
> +
> +Required Properties:
> +#phy-cells:	Number of cells in a PHY specifier;  The meaning of all those
> +		cells is defined by the binding for the phy node. The PHY
> +		provider can use the values in cells to find the appropriate
> +		PHY.
> +
> +For example:
> +
> +phys: phy {
> +    compatible = "xxx";
> +    reg =<...>;
> +    .
> +    .
> +    #phy-cells =<1>;
> +    .
> +    .
> +};
> +
> +That node describes an IP block (PHY provider) that implements 2 different PHYs.
> +In order to differentiate between these 2 PHYs, an additonal specifier should be
> +given while trying to get a reference to it.
> +
> +PHY user node
> +=============
> +
> +Required Properties:
> +phys : the phandle for the PHY device (used by the PHY subsystem)
> +phy-names : the names of the PHY corresponding to the PHYs present in the
> +	    *phys* phandle
> +
> +Example 1:
> +usb1: usb_otg_ss at xxx {
> +    compatible = "xxx";
> +    reg =<xxx>;
> +    .
> +    .
> +    phys =<&usb2_phy>,<&usb3_phy>;
> +    phy-names = "usb2phy", "usb3phy";
> +    .
> +    .
> +};
> +
> +This node represents a controller that uses two PHYs, one for usb2 and one for
> +usb3.
> +
> +Example 2:
> +usb2: usb_otg_ss at xxx {
> +    compatible = "xxx";
> +    reg =<xxx>;
> +    .
> +    .
> +    phys =<&phys 1>;
> +    phy-names = "usbphy";
> +    .
> +    .
> +};
> +
> +This node represents a controller that uses one of the PHYs of the PHY provider
> +device defined previously. Note that the phy handle has an additional specifier
> +"1" to differentiate between the two PHYs.
> diff --git a/Documentation/phy.txt b/Documentation/phy.txt
> new file mode 100644
> index 0000000..408d25f
> --- /dev/null
> +++ b/Documentation/phy.txt
> @@ -0,0 +1,123 @@
> +			    PHY SUBSYSTEM
> +		  Kishon Vijay Abraham I<kishon at ti.com>
> +
> +This document explains the Generic PHY Framework along with the APIs provided,
> +and how-to-use.
> +
> +1. Introduction
> +
> +*PHY* is the abbreviation for physical layer. It is used to connect a device
> +to the physical medium e.g., the USB controller has a PHY to provide functions
> +such as serialization, de-serialization, encoding, decoding and is responsible
> +for obtaining the required data transmission rate. Note that some USB
> +controller has PHY functionality embedded into it and others use an external

"Note that some USB
controllers have PHY functionality embedded into them..." ?

> +PHY. Other peripherals that uses a PHY include Wireless LAN, Ethernet,

s/uses/use ?

> +SATA etc.
> +
> +The intention of creating this framework is to bring the phy drivers spread

s/phy/PHY ?

> +all over the Linux kernel to drivers/phy to increase code re-use and for
> +better code maintainability.
> +
> +This framework will be of use only to devices that uses external PHY (PHY

s/that uses/that use ?

> +functionality is not embedded within the controller).
> +
> +2. Registering/UnRegistering the PHY provider

s/UnRegistering/Unregistering ?

> +
> +PHY provider refers to an entity that implements one or more PHY instances.
> +For the simple case where the PHY provider implements only a single instance of
> +the PHY, the framework provides its own implementation of of_xlate in
> +of_phy_simple_xlate. If the PHY provider implements multiple instances, it
> +should provide it's own implementation of of_xlate. of_xlate is used only for

s/it's/its

> +dt boot case.
> +
> +struct phy_provider *of_phy_provider_register(struct device *dev,
> +	struct module *owner, struct phy * (*of_xlate)(struct device *dev,
> +	struct of_phandle_args *args));
> +struct phy_provider *devm_of_phy_provider_register(struct device *dev,
> +	struct module *owner, struct phy * (*of_xlate)(struct device *dev,
> +	struct of_phandle_args *args))
> +
> +of_phy_provider_register and devm_of_phy_provider_register can be used to
> +register the phy_provider and it takes device, owner and of_xlate as
> +arguments. For the dt boot case, all PHY providers should use one of the above
> +2 APIs to register the PHY provider.
> +
> +void devm_of_phy_provider_unregister(struct device *dev,
> +	struct phy_provider *phy_provider);
> +void of_phy_provider_unregister(struct phy_provider *phy_provider);
> +
> +devm_of_phy_provider_unregister and of_phy_provider_unregister can be used to
> +unregister the PHY.
> +
> +3. Creating the PHY
> +
> +The PHY driver should create the PHY in order for other peripheral controllers
> +to make use of it. The PHY framework provides 2 APIs to create the PHY.
> +
> +struct phy *phy_create(struct device *dev, int id, const struct phy_ops *ops,
> +	void *priv);
> +struct phy *devm_phy_create(struct device *dev, int id,
> +	const struct phy_ops *ops, void *priv);
> +
> +The PHY drivers can use one of the above 2 APIs to create the PHY by passing
> +the device pointer, id, phy ops and a driver data.
> +phy_ops is a set of function pointers for performing PHY operations such as
> +init, exit, power_on and power_off.
> +
> +4. Getting a reference to the PHY
> +
> +Before the controller can make use of the PHY, it has to get a reference to
> +it. This framework provides the following APIs to get a reference to the PHY.
> +
> +struct phy *phy_get(struct device *dev, const char *string);
> +struct phy *devm_phy_get(struct device *dev, const char *string);
> +
> +phy_get and devm_phy_get can be used to get the PHY. In the case of dt boot,
> +the string arguments should contain the phy name as given in the dt data and
> +in the case of non-dt boot, it should contain the device name of the PHY.

How about allowing null strings ? At least it seems not difficult for dt 
boot.
But there would have been some asymmetry, for non-dt an error would have to
be returned when the passed string is null.

> +The only difference between the two APIs is that devm_phy_get associates the
> +device with the PHY using devres on successful PHY get. On driver detach,
> +release function is invoked on the the devres data and devres data is freed.
> +
> +5. Releasing a reference to the PHY
> +
> +When the controller no longer needs the PHY, it has to release the reference
> +to the PHY it has obtained using the APIs mentioned in the above section. The
> +PHY framework provides 2 APIS to release a reference to the PHY.

APIs ?

> +void phy_put(struct phy *phy);
> +void devm_phy_put(struct device *dev, struct phy *phy);
> +
> +Both these APIs are used to release a reference to the PHY and devm_phy_put
> +destroys the devres associated with this PHY.
> +
> +6. Destroying the PHY
> +
> +When the driver that created the PHY is unloaded, it should destroy the PHY it
> +created using one of the following 2 APIs.
> +
> +void phy_destroy(struct phy *phy);
> +void devm_phy_destroy(struct device *dev, struct phy *phy);
> +
> +Both these APIs destroys the PHY and devm_phy_destroy destroys the devres

s/APIs destroys/APIs destroy ?

> +associated with this PHY.
> +
> +7. PM Runtime
> +
> +This subsystem is pm runtime enabled. So while creating the PHY,
> +pm_runtime_enable of the phy device created by this subsystem is called and
> +while destroying the PHY, pm_runtime_disable is called. Note that the phy
> +device created by this subsystem will be a child of the device that calls
> +phy_create (PHY provider device).
> +
> +During phy_init, the clocks are enabled by calling get_sync and the clocks are

I think, if you mean pm_runtime_get_sync(), it should be said precisely 
here.

> +disable by calling put_sync during phy_exit. get_sync of the phy_device

Ditto.

s/disable/disabled

> +created by this susbsystem will invoke get_sync of PHY provider device because

s/susbsystem/subsystem

> +of parent-child relationship. For all other pm operations, there are exported
> +APIs like phy_pm_runtime_get, phy_pm_runtime_get_sync, phy_pm_runtime_put,
> +phy_pm_runtime_put_sync, phy_pm_runtime_allow and phy_pm_runtime_forbid.
> +
> +8. DeviceTree Binding
> +
> +The documentation for PHY dt binding can be found @
> +Documentation/devicetree/bindings/phy/phy-bindings.txt

> +/**
> + * phy_release() - release the phy
> + * @dev: the dev member within phy
> + *
> + * when the last reference to the device is removed; it is called

s/when/When
s/removed;/removed ?

> + * from the embedded kobject as release method.
> + */

> +/**
> + * struct phy - represent the phy device

s/represent/represents ?

> + * @dev: phy device
> + * @id: id of the phy
> + * @ops: function pointers for performing phy operations
> + */
> +struct phy {
> +	struct device		dev;
> +	int			id;
> +	const struct phy_ops	*ops;
> +};
> +
> +/**
> + * struct phy_provider - represent the phy provider

s/represent/represents ?

> + * @dev: phy provider device
> + * @owner: the module owner having of_xlate
> + * @of_xlate: function pointer to obtain phy instance from phy pointer
> + * @list: to maintain a linked list of PHY provider

s/provider/providers ?

> + */
> +struct phy_provider {
> +	struct device		*dev;
> +	struct module		*owner;
> +	struct list_head	list;
> +	struct phy * (*of_xlate)(struct device *dev,
> +		struct of_phandle_args *args);
> +};

Regards,
Sylwester


From jason at lakedaemon.net  Tue May 28 18:38:17 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 18:38:17 -0400
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use
 DT for the PCIe interface
In-Reply-To: <20130529002053.4b8ceb86@skate>
References: <8738t6ycnm.fsf@natisbad.org>
 <20130529002053.4b8ceb86@skate>
Message-ID: <20130528223817.GL31290@titan.lakedaemon.net>

On Wed, May 29, 2013 at 12:20:53AM +0200, Thomas Petazzoni wrote:
> On Wed, 29 May 2013 00:15:09 +0200, Arnaud Ebalard wrote:
> > Jason, I gave your associated branch (jcooper/mvebu-next/pcie) a try
> > with following patch applied and can confirm USB 3.0 host controller
> > (connected to PCIe bus) is usable on Netgear ReadyNAS *Duo v2*
> > (88f6282-based brother of the 102).
> > 
> > Note that I had to s/of_pci_range_parser()/of_pci_range_parser_init()/
> > in drivers/pci/host/pci-mvebu.c to compile the kernel (this may already
> > have been fixed already):
> > 
> > CHK     kernel/config_data.h
> > drivers/pci/host/pci-mvebu.c: In function ?mvebu_pcie_probe?:
> > drivers/pci/host/pci-mvebu.c:742:2: error: implicit declaration of function ?of_pci_range_parser? [-Werror=implicit-function-declaration]
> > cc1: some warnings being treated as errors
> 
> You're probably not using the latest mvebu/pcie branch from jcooper. In
> his branch, I see:
> 
> +       if (of_pci_range_parser_init(&parser, np))
> +               return -EINVAL;
> 
> Which should do the right thing.
> 
> Could you check that you're running on top of the latest
> jcooper/mvebu/pcie branch? Thanks!

Actually, you want jcooper/mvebu/pcie_kirkwood.  I split out the
kirkwood driver so that if it causes a build breakage and gets dropped,
mvebu/pcie can still go in.

> > Can one of you take the patch below into account? Or 
> 
> You should probably resend your patch with a proper description. Your
> description now includes a lot information about unrelated things (the
> Armada 370 board you're working on, the build failure you had, etc.).

That stuff can go below the '---' in the future.  Don't stress about it,
though.  I'll clean it up when I apply it if needed.

thx,

Jason.


From khilman at linaro.org  Tue May 28 18:57:01 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 28 May 2013 15:57:01 -0700
Subject: build failure: linux-next: ARM/SH-mobile defconfigs: kota2, marzen
Message-ID: <87txlmaf2a.fsf@linaro.org>

Hello,

Both kota2_defconfig and marzen_defconfig started failing in the most
recnet linux-next (next-20130527) but were successful in the previous
build (next-20130523).

Both fail wit this error:

drivers/built-in.o: In function `sh_mobile_sdhi_probe':
/work/kernel/next/drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to `shdma_chan_filter'
make[1]: *** [vmlinux] Error 1
make[1]: Target `_all' not remade because of errors.

Full build logs are available here:

  https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=kota2_defconfig,label=kernel_cloud/54/console
  https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=marzen_defconfig,label=kernel_cloud/54/console

Kevin



From khilman at linaro.org  Tue May 28 18:57:52 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 28 May 2013 15:57:52 -0700
Subject: build failure: linux-next: ARM defconfig: u8500
Message-ID: <CAGa+x87czosA=tWh1KRTSSqMyLckMHwNP7hrRXdokaLsSaaikA@mail.gmail.com>

Hello,

u8500_defconfig started failing to build in linux next (next-20130527)
but was previously building (next-20130523.)  The build failure looks
like a failed merge attempt:

/work/kernel/next/drivers/pinctrl/pinctrl-abx500.c: In function
'abx500_gpio_probe':
/work/kernel/next/drivers/pinctrl/pinctrl-abx500.c:898:1: error:
expected expression before '<<' token
/work/kernel/next/drivers/pinctrl/pinctrl-abx500.c:900:21: error:
'struct abx500_pinctrl' has no member named 'lock'
/work/kernel/next/drivers/pinctrl/pinctrl-abx500.c:901:1: error:
expected expression before '==' token
/work/kernel/next/drivers/pinctrl/pinctrl-abx500.c:904:1: error:
expected expression before '>>' token
make[3]: *** [drivers/pinctrl/pinctrl-abx500.o] Error 1

Full build log available here:
  https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=u8500_defconfig,label=kernel_cloud/54/console

Kevin


From olof at lixom.net  Tue May 28 19:17:40 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 16:17:40 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <5191AA89.6010901@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
Message-ID: <20130528231740.GA28879@quad.lixom.net>

On Tue, May 14, 2013 at 08:37:53AM +0530, Tushar Behera wrote:
> On 05/14/2013 05:36 AM, Kevin Hilman wrote:
> > Tushar Behera <tushar.behera at linaro.org> writes:
> > 
> >> It updates following drivers for EXYNOS based DT platform.
> >>
> >> * S5M8767 driver
> >> * MAX8997 driver
> >> * MMC SDHCI driver
> >>
> >> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
> > 
> > I tested this using v3.10-rc1 on Arndale, but still don't get any
> > support for the wired network.  Do you know if this is a Kconfig issue,
> > or a missing driver?
> > 
> > I suspect it may be related to the various "unable to find transceiver
> > of type USB2 PHY" messages I'm seeing?
> > 
> 
> Yes, right. The missing USB-PHY components are one of the issues (they
> were there in linux-next when I last tested).
> 
> Also, on Arndale board, we need to reset the USB hub during EHCI
> initialization (a couple of those patches are required, which I am not
> sure if we would be able to upstream).
> 
> I am collecting a minimal set of patches that would enable USB and wired
> network on Arndale with 3.10-rc1 kernel. Once done, I will let you know.

Hi Tushar,

Got an update on what these patches are yet?


-Olof



From olof at lixom.net  Tue May 28 19:24:15 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 16:24:15 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <CAOesGMjirb0h4kZ1hB9=1JnDV+azTEG=_6RR9v000xbMsvuv2Q@mail.gmail.com>

Hi,

On Thu, May 9, 2013 at 11:49 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
> It updates following drivers for EXYNOS based DT platform.
>
> * S5M8767 driver
> * MAX8997 driver
> * MMC SDHCI driver
>
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>

I didn't see any movement from Kukjin on this, so I have (tentatively)
applied this together with my base defconfig update to the fixes
branch of arm-soc. I'll take it out in case he protests, but it's very
useful since the simplefb driver has landed in 3.10-rc3.


-Olof


From khilman at linaro.org  Tue May 28 19:46:16 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Tue, 28 May 2013 16:46:16 -0700
Subject: build failure: linux-next: ARM defconfig: u8500
In-Reply-To: <CAGa+x87czosA=tWh1KRTSSqMyLckMHwNP7hrRXdokaLsSaaikA@mail.gmail.com>
References: <CAGa+x87czosA=tWh1KRTSSqMyLckMHwNP7hrRXdokaLsSaaikA@mail.gmail.com>
Message-ID: <CAGa+x84p1pVuFm_MuQVTCJq_50NTsjKtWUFAbQ0W_=beOcA55A@mail.gmail.com>

On Tue, May 28, 2013 at 3:57 PM, Kevin Hilman <khilman at linaro.org> wrote:

> u8500_defconfig started failing to build in linux next (next-20130527)
> but was previously building (next-20130523.)

My apologies, it appears this one is already fixed in next-20130528.
/me updates automated build to not be a full day behind linux-next.

Kevin


From kgene.kim at samsung.com  Tue May 28 20:07:09 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 29 May 2013 09:07:09 +0900
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <CAOesGMjirb0h4kZ1hB9=1JnDV+azTEG=_6RR9v000xbMsvuv2Q@mail.gmail.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <CAOesGMjirb0h4kZ1hB9=1JnDV+azTEG=_6RR9v000xbMsvuv2Q@mail.gmail.com>
Message-ID: <17ec01ce5c00$76384e40$62a8eac0$%kim@samsung.com>

Olof Johansson wrote:
> 
> Hi,
> 
> On Thu, May 9, 2013 at 11:49 PM, Tushar Behera <tushar.behera at linaro.org>
> wrote:
> > It updates following drivers for EXYNOS based DT platform.
> >
> > * S5M8767 driver
> > * MAX8997 driver
> > * MMC SDHCI driver
> >
> > Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
> 
> I didn't see any movement from Kukjin on this, so I have (tentatively)
> applied this together with my base defconfig update to the fixes
> branch of arm-soc. I'll take it out in case he protests, but it's very
> useful since the simplefb driver has landed in 3.10-rc3.
> 
I'm fine on this, so please go ahead with my ack if you want,

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks for your gentle reminder :-)

- Kukjin



From kgene.kim at samsung.com  Tue May 28 20:28:01 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 29 May 2013 09:28:01 +0900
Subject: Single zImage and A15/LPAE
In-Reply-To: <20121009141736.GB2122@linaro.org>
References: <50735B75.8070109@wwwdotorg.org>
 <alpine.LFD.2.02.1210082201470.16518@xanadu.home> <2043931.InXdkgrjkp@wuerfel>
 <20121009141736.GB2122@linaro.org>
Message-ID: <180001ce5c03$60cbcf70$22636e50$%kim@samsung.com>

Dave Martin wrote:
> On Tue, Oct 09, 2012 at 07:51:02AM +0000, Arnd Bergmann wrote:
> > On Monday 08 October 2012 22:18:24 Nicolas Pitre wrote:
> > > On Mon, 8 Oct 2012, Stephen Warren wrote:
> > >
> > > > I'm curious what the single-zImage story is for Cortex A15 CPUs with
> > > > LPAE extensions; IIRC, LPAE entails a different page table format
> and so
> > > > isn't going to co-exist in the same zImage as non-LPAE
> > >
> > > LPAE vs non LPAE is an even more invasive change than ARMv6+ vs pre
> > > ARMv6 support.  So no, I don't think we'll ever support LPAE and non
> > > LPAE configs in the same kernel binary.
> > >
> > > > (although doesn't x86 support that now; I though separate
> > > > LPAE/non-LPAE kernels went away there?)
> > >
> > > I don't think so.  At least Ubuntu apparently still carries a PAE and
> > > non PAE kernel packages.  Fedora doesn't, probably because they
> decided
> > > not to support non PAE capable machines anymore.  We certainly cannot
> > > make this choice on ARM yet.
> >
> > Fedora 18 still has both PAE and non-PAE kernels. I would really hope
> > they could give up the PAE version in favor of a 64 bit kernel in
> > the 32 bit distro, but it seems none of the big distros trust the
> > compat code enough yet. On x86, the number of 32 bit machines still
> > running with more than 3GB of RAM installed should be very marginal
> > now, most people running the PAE kernel actually have 64 bit capable
> > CPUs and have some legacy 32 bit applications that are easier to
> > run with a 32 bit user space.
> >
> > Maybe we get to the same point on ARM in some 10 years, but for
> > the forseeable future, Cortex-a15 machines with lots of RAM will
> > be very real and we need to have separate kernels for those.
> 
> In the medium term we could work around this with a fat kernel in
> principle (i.e., bundle a non-LPAE single kernel together with an LPAE
> one and choose the right one at boot time).  This can be solved outside
> the kernel if necessary.
> 
> This is not great, but the general feeling seems to be that combining
> LPAE and non-LPAE in the same kernel is just not going to be worth the
> pain (either in code or runtime impacts).
> 
> For AArch64, we obviously have a different kernel binary anyway.
> 
(+ Olof, Russell)

Just note, I found this in my old mail-box...

So I think, as a result, we need to support separate kernel binary for LPAE
and non-LPAE and you guys don't hold a different view about it.

Current SSDK5440 and SD5v1 boards which are reference boards for EXYNOS5440
has over 4GB memory as a default and that's why I'm writing this e-mail. It
means I should keep separated kernel to support exynos5440 and other exynos
SoCs.

If you have any concerns about that, please let me know.

- Kukjin



From olof at lixom.net  Tue May 28 20:34:30 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 17:34:30 -0700
Subject: Booting mainline kernels on Samsung ARM-based Chromebooks
Message-ID: <CAOesGMgrT8fCRcnJYP=tcr4Szp5B6NtQxsQeb6pEv24edHLYFw@mail.gmail.com>

Just a quick note that as of v3.10-rc4 (or -rc3 + arm-soc fixes
branch) there should be enough pieces in mainline to boot a Chromebook
to a useful state without out-of-tree patches.

For more info, see:

https://plus.google.com/u/0/109993695638569781190/posts/bQpzEGG15G8

There's plenty of stuff not working yet, but it'll come up with
simplefb, keyboard, trackpad and USB 2.0 for now.


-Olof


From kgene.kim at samsung.com  Tue May 28 20:41:28 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 29 May 2013 09:41:28 +0900
Subject: Booting mainline kernels on Samsung ARM-based Chromebooks
In-Reply-To: <CAOesGMgrT8fCRcnJYP=tcr4Szp5B6NtQxsQeb6pEv24edHLYFw@mail.gmail.com>
References: <CAOesGMgrT8fCRcnJYP=tcr4Szp5B6NtQxsQeb6pEv24edHLYFw@mail.gmail.com>
Message-ID: <180101ce5c05$41d82800$c5887800$%kim@samsung.com>

Olof Johansson wrote:
> 
> Just a quick note that as of v3.10-rc4 (or -rc3 + arm-soc fixes
> branch) there should be enough pieces in mainline to boot a Chromebook
> to a useful state without out-of-tree patches.
> 
Sounds great. Yeah, we wanted to support mass product without any other
patches and its first product using Samsung SoC is Samsung ARM-based
Chromebook.

Thanks for many guys' effort and time.

- Kukjin

> For more info, see:
> 
> https://plus.google.com/u/0/109993695638569781190/posts/bQpzEGG15G8
> 
> There's plenty of stuff not working yet, but it'll come up with
> simplefb, keyboard, trackpad and USB 2.0 for now.



From olof at lixom.net  Tue May 28 20:56:11 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 17:56:11 -0700
Subject: [GIT PULL] ARM: Exynos fixes for 3.10-rc
Message-ID: <20130529005611.GA17319@quad.lixom.net>

Hi Linus,

The following changes since commit f4ae176c626311d6507c9a2d263657c4cc4e1667:

  Merge tag 'sunxi-fixes-for-3.10' of git://github.com/mripard/linux into fixes (2013-05-24 15:50:28 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-for-linus

for you to fetch changes up to da9d0fbf5e9aa47492a19588bd0efd18d6d172e0:

  ARM: exynos: defconfig update (2013-05-28 17:21:41 -0700)

----------------------------------------------------------------
ARM: Exynos fixes for 3.10-rc

Here's a shorter set of fixes for 3.10, all for Samsung Exynos platforms.

It also includes a defconfig update so that exynos_defconfig provides
a meaningful set of drivers to boot an unmodified kernel on the Samsung
ARM-based Chromebooks.

----------------------------------------------------------------
Jungseok Lee (1):
      ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC

Olof Johansson (2):
      Merge tag 'samsung-fixes-3' of git://git.kernel.org/.../kgene/linux-samsung into fixes
      ARM: exynos: defconfig update

Tomasz Figa (2):
      ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
      ARM: SAMSUNG: Add names to fimd0 IRQ resources

Vivek Gautam (1):
      ARM: dts: Enabling samsung-usb2phy driver for exynos5250

 arch/arm/boot/dts/exynos5250.dtsi          | 15 +++++++++
 arch/arm/configs/exynos_defconfig          | 54 +++++++++++++++++++++++++-----
 arch/arm/mach-exynos/Kconfig               |  3 +-
 arch/arm/mach-exynos/common.c              | 39 +++++++++++++++++++--
 arch/arm/mach-exynos/common.h              |  2 ++
 arch/arm/mach-exynos/mach-universal_c210.c |  5 ++-
 arch/arm/plat-samsung/devs.c               |  6 ++--
 7 files changed, 107 insertions(+), 17 deletions(-)


From jason at lakedaemon.net  Tue May 28 20:58:25 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 May 2013 20:58:25 -0400
Subject: Kirkwood CPU Freq driver
In-Reply-To: <51A5234D.9030100@baker-net.org.uk>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
 <20130526180513.GF31290@titan.lakedaemon.net>
 <51A5234D.9030100@baker-net.org.uk>
Message-ID: <20130529005825.GM31290@titan.lakedaemon.net>

On Tue, May 28, 2013 at 10:36:13PM +0100, Adam Baker wrote:
> On 26/05/13 19:05, Jason Cooper wrote:
> >On Sun, May 26, 2013 at 10:36:14AM +0200, Andrew Lunn wrote:
> >>On Sat, May 25, 2013 at 10:32:04PM +0100, Adam Baker wrote:
> >>>I've been trying to test Andrew Lunn's work creating a CPU Idle
> >>>driver for Kirkwood.
> >>
> >>Thanks for testing this. I must admit, i never tested it once the
> >>first rc came out. I clearly should of, because its broken. It was a
> >>three part patch series, and only part 1/3 made it in. Hence the
> >>issues you are seeing.
> >>
> >>Jason, please can you pick up:
> >>
> >>https://patchwork.kernel.org/patch/2051401/
> >>https://patchwork.kernel.org/patch/2080931/
> >
> >Yep, got them in now.  Sorry for the mix up.
> >
> 
> I've now tested with the first of these patches applied and the
> changes from the second added to my .config
> 
> To get it to work I had to follow the instructions in the
> Documentation to add the cpus entry to kirkwood.dtsi so I'll post
> that as a patch in a day or two but after doing that I have a
> working cpufreq driver.
> 
> Measuring the power consumption of my NAS server I observed a slight
> reduction in power consumption when the clock rate was reduced. I
> haven't yet measured for long enough to get an accurate measurement
> but it looks like maybe 1/4 W power saving.
> 
> Feel free to add
> 
> Tested-by: Adam Baker <linux at baker-net.org.uk>

I apologize, but I won't be able to add this.  I'm using a new work
flow, and took the patches in too quickly (well, they had been on the
list a while... :-P)  I should've let them sit in my tree for a few more
days before sending the pull request to arm-soc.  If I had done that, I
could've gone in and added the Tested-by:.  I'll be more careful in the
future.

When you submit v2 of your DT change, please add the Tested-by to that.

Thanks again for testing, we do appreciate the effort.

thx,

Jason.


From jg1.han at samsung.com  Tue May 28 21:07:16 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 29 May 2013 10:07:16 +0900
Subject: Booting mainline kernels on Samsung ARM-based Chromebooks
In-Reply-To: <CAOesGMgrT8fCRcnJYP=tcr4Szp5B6NtQxsQeb6pEv24edHLYFw@mail.gmail.com>
References: <CAOesGMgrT8fCRcnJYP=tcr4Szp5B6NtQxsQeb6pEv24edHLYFw@mail.gmail.com>
Message-ID: <001901ce5c08$dc248e00$946daa00$@samsung.com>

On Wednesday, May 29, 2013 9:35 AM, Olof Johansson wrote:
> 
> Just a quick note that as of v3.10-rc4 (or -rc3 + arm-soc fixes
> branch) there should be enough pieces in mainline to boot a Chromebook
> to a useful state without out-of-tree patches.
> 
> For more info, see:
> 
> https://plus.google.com/u/0/109993695638569781190/posts/bQpzEGG15G8

Oh, great!

As Kukjin Kim mentioned, we have wanted to support mass product
without out-of-tree patches. Also, I have gone the extra mile
to do this.

> 
> There's plenty of stuff not working yet, but it'll come up with
> simplefb, keyboard, trackpad and USB 2.0 for now.

I will look at the patches about simplefb, USB 2.0, and so on.
If possible, I will review it.
Good luck.

Best regards,
Jingoo Han

> 
> 
> -Olof
> --




From csd at broadcom.com  Tue May 28 21:13:34 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 28 May 2013 18:13:34 -0700
Subject: [PATCH V3 1/3] mmc: Add size for caller in init+register
Message-ID: <1369790016-13270-1-git-send-email-csd@broadcom.com>

Add a param to allow users of sdhci_pltfm to allocate private space
in calls to sdhci_pltfm_init+sdhci_pltfm_register. This is implemented
in the same way as sdhci does for its users.
 None of the users have been migrated yet and are passing in zero to
retain their private allocation.

- todo: migrate clients to using allocation this way
- todo: remove priv variable once migration is complete

Also removed unused variable in sdhci_pltfm_init fn

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index d49bc95..0584a1c 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -148,7 +148,7 @@ static int bcm2835_sdhci_probe(struct platform_device *pdev)
 	struct sdhci_pltfm_host *pltfm_host;
 	int ret;
 
-	host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata);
+	host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata, 0);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 
diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c
index 8ebb6b6..f2cc266 100644
--- a/drivers/mmc/host/sdhci-cns3xxx.c
+++ b/drivers/mmc/host/sdhci-cns3xxx.c
@@ -96,7 +96,7 @@ static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
 
 static int sdhci_cns3xxx_probe(struct platform_device *pdev)
 {
-	return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata);
+	return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
 }
 
 static int sdhci_cns3xxx_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c
index 15e7803..8424839 100644
--- a/drivers/mmc/host/sdhci-dove.c
+++ b/drivers/mmc/host/sdhci-dove.c
@@ -130,7 +130,7 @@ static int sdhci_dove_probe(struct platform_device *pdev)
 		gpio_direction_input(priv->gpio_cd);
 	}
 
-	host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata);
+	host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata, 0);
 	if (IS_ERR(host)) {
 		ret = PTR_ERR(host);
 		goto err_sdhci_pltfm_init;
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 67d6dde..9a1e6fa 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -470,7 +470,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 	int err;
 	struct pltfm_imx_data *imx_data;
 
-	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
+	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 5e68adc..37e668f 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -262,7 +262,7 @@ static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
 
 static int sdhci_esdhc_probe(struct platform_device *pdev)
 {
-	return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
+	return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata, 0);
 }
 
 static int sdhci_esdhc_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/sdhci-of-hlwd.c b/drivers/mmc/host/sdhci-of-hlwd.c
index 200a6a9..57c514a 100644
--- a/drivers/mmc/host/sdhci-of-hlwd.c
+++ b/drivers/mmc/host/sdhci-of-hlwd.c
@@ -68,7 +68,7 @@ static const struct sdhci_pltfm_data sdhci_hlwd_pdata = {
 
 static int sdhci_hlwd_probe(struct platform_device *pdev)
 {
-	return sdhci_pltfm_register(pdev, &sdhci_hlwd_pdata);
+	return sdhci_pltfm_register(pdev, &sdhci_hlwd_pdata, 0);
 }
 
 static int sdhci_hlwd_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index cd0f1f6..38e38a5 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -115,10 +115,10 @@ void sdhci_get_of_property(struct platform_device *pdev) {}
 EXPORT_SYMBOL_GPL(sdhci_get_of_property);
 
 struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
-				    const struct sdhci_pltfm_data *pdata)
+				    const struct sdhci_pltfm_data *pdata,
+				    size_t priv_size)
 {
 	struct sdhci_host *host;
-	struct sdhci_pltfm_host *pltfm_host;
 	struct device_node *np = pdev->dev.of_node;
 	struct resource *iomem;
 	int ret;
@@ -134,17 +134,17 @@ struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
 
 	/* Some PCI-based MFD need the parent here */
 	if (pdev->dev.parent != &platform_bus && !np)
-		host = sdhci_alloc_host(pdev->dev.parent, sizeof(*pltfm_host));
+		host = sdhci_alloc_host(pdev->dev.parent,
+			sizeof(struct sdhci_pltfm_host) + priv_size);
 	else
-		host = sdhci_alloc_host(&pdev->dev, sizeof(*pltfm_host));
+		host = sdhci_alloc_host(&pdev->dev,
+			sizeof(struct sdhci_pltfm_host) + priv_size);
 
 	if (IS_ERR(host)) {
 		ret = PTR_ERR(host);
 		goto err;
 	}
 
-	pltfm_host = sdhci_priv(host);
-
 	host->hw_name = dev_name(&pdev->dev);
 	if (pdata && pdata->ops)
 		host->ops = pdata->ops;
@@ -202,12 +202,13 @@ void sdhci_pltfm_free(struct platform_device *pdev)
 EXPORT_SYMBOL_GPL(sdhci_pltfm_free);
 
 int sdhci_pltfm_register(struct platform_device *pdev,
-			 const struct sdhci_pltfm_data *pdata)
+			const struct sdhci_pltfm_data *pdata,
+			size_t priv_size)
 {
 	struct sdhci_host *host;
 	int ret = 0;
 
-	host = sdhci_pltfm_init(pdev, pdata);
+	host = sdhci_pltfm_init(pdev, pdata, priv_size);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index 1210ed1..ed4a85d 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -27,6 +27,8 @@ struct sdhci_pltfm_host {
 	/* migrate from sdhci_of_host */
 	unsigned int clock;
 	u16 xfer_mode_shadow;
+
+	unsigned long private[0] ____cacheline_aligned;
 };
 
 #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
@@ -91,15 +93,22 @@ static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
 extern void sdhci_get_of_property(struct platform_device *pdev);
 
 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
-					  const struct sdhci_pltfm_data *pdata);
+					  const struct sdhci_pltfm_data *pdata,
+					  size_t priv_size);
 extern void sdhci_pltfm_free(struct platform_device *pdev);
 
 extern int sdhci_pltfm_register(struct platform_device *pdev,
-				const struct sdhci_pltfm_data *pdata);
+				const struct sdhci_pltfm_data *pdata,
+				size_t priv_size);
 extern int sdhci_pltfm_unregister(struct platform_device *pdev);
 
 extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
 
+static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
+{
+	return (void *)host->private;
+}
+
 #ifdef CONFIG_PM
 extern const struct dev_pm_ops sdhci_pltfm_pmops;
 #define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops)
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
index 6a3f702..1cf093f 100644
--- a/drivers/mmc/host/sdhci-pxav2.c
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -175,7 +175,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
 	if (!pxa)
 		return -ENOMEM;
 
-	host = sdhci_pltfm_init(pdev, NULL);
+	host = sdhci_pltfm_init(pdev, NULL, 0);
 	if (IS_ERR(host)) {
 		kfree(pxa);
 		return PTR_ERR(host);
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 1ae358e..9124104 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -230,7 +230,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 	if (!pxa)
 		return -ENOMEM;
 
-	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata);
+	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
 	if (IS_ERR(host)) {
 		kfree(pxa);
 		return PTR_ERR(host);
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index e0dba74..c8b0582 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -231,7 +231,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 		return -EINVAL;
 	soc_data = match->data;
 
-	host = sdhci_pltfm_init(pdev, soc_data->pdata);
+	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 	pltfm_host = sdhci_priv(host);
-- 
1.7.10.4




From csd at broadcom.com  Tue May 28 21:13:36 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 28 May 2013 18:13:36 -0700
Subject: [PATCH V3 3/3] ARM: mmc: bcm281xx SDHCI driver (dt mods)
In-Reply-To: <1369790016-13270-1-git-send-email-csd@broadcom.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
Message-ID: <1369790016-13270-3-git-send-email-csd@broadcom.com>

Add SDHCI bindings for the Broadcom 281xx SoCs.

Changes from V2:
 - Documentation cleanups

Changes from V1:
 - split original patch into 2, one for driver and this one for dt

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
new file mode 100644
index 0000000..094ae01
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
@@ -0,0 +1,16 @@
+Broadcom BCM281xx SDHCI
+
+This file documents differences between the core properties in mmc.txt
+and the properties present in the bcm281xx SDHCI
+
+Required properties:
+- compatible : Should be "bcm,kona-sdhci"
+
+Example:
+
+sdio2: sdio at 0x3f1a0000 {
+	compatible = "bcm,kona-sdhci";
+	reg = <0x3f1a0000 0x10000>;
+	interrupts = <0x0 74 0x4>;
+};
+
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067c..9ae3404 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -27,4 +27,21 @@
 		status = "okay";
 	};
 
+	sdio0: sdio at 0x3f180000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		non-removable;
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c..39de6e2 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -60,4 +60,32 @@
 		clock-frequency = <32768>;
 	};
 
+	sdio0: sdio at 0x3f180000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f180000 0x10000>;
+		interrupts = <0x0 77 0x4>;
+		status = "disabled";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f190000 0x10000>;
+		interrupts = <0x0 76 0x4>;
+		status = "disabled";
+	};
+
+	sdio2: sdio at 0x3f1a0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1a0000 0x10000>;
+		interrupts = <0x0 74 0x4>;
+		status = "disabled";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1b0000 0x10000>;
+		interrupts = <0x0 73 0x4>;
+		status = "disabled";
+	};
+
 };
-- 
1.7.10.4




From csd at broadcom.com  Tue May 28 21:13:35 2013
From: csd at broadcom.com (Christian Daudt)
Date: Tue, 28 May 2013 18:13:35 -0700
Subject: [PATCH V3 2/3] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1369790016-13270-1-git-send-email-csd@broadcom.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
Message-ID: <1369790016-13270-2-git-send-email-csd@broadcom.com>

Add SDHCI driver for the Broadcom 281xx SoCs. Also
add bindings for it into bcm281xx dts files.
Still missing:
 - power managemement

Changes from V2:
 - Structure cleanups
 - init space from sdhci_pltfm_init
 - replace spinlock_irqsave with mutex on sd_card_emulate
 - Reduce init_74_clocks delay and document it

Changes from V1:
 - split DT into separate patch
 - use gpio_is_valid instead of direct test
 - switch pr_debug calls to dev_dbg
 - use of_property_read_bool

Signed-off-by: Christian Daudt <csd at broadcom.com>

diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index e3bf2d6..65edf6d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9ab8f8d..2455a35 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -249,6 +249,17 @@ config MMC_SDHCI_S3C_DMA
 
 	  YMMV.
 
+config MMC_SDHCI_BCM_KONA
+	tristate "SDHCI support on Broadcom KONA platform"
+	depends on ARCH_BCM
+	select MMC_SDHCI_PLTFM
+	help
+	  This selects the Broadcom Kona Secure Digital Host Controller
+	  Interface(SDHCI) support.
+	  This is used in Broadcom mobile SoCs.
+
+	  If you have a controller with this interface, say Y or M here.
+
 config MMC_SDHCI_BCM2835
 	tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
 	depends on ARCH_BCM2835
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cd32280..cd4c845 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)		+= sdhci-dove.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
+obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
new file mode 100644
index 0000000..1cba006
--- /dev/null
+++ b/drivers/mmc/host/sdhci-bcm-kona.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/highmem.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/version.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci.h"
+
+#define SDHCI_SOFT_RESET			0x01000000
+#define KONA_SDHOST_CORECTRL			0x8000
+#define KONA_SDHOST_CD_PINCTRL			0x00000008
+#define KONA_SDHOST_STOP_HCLK			0x00000004
+#define KONA_SDHOST_RESET			0x00000002
+#define KONA_SDHOST_EN				0x00000001
+
+#define KONA_SDHOST_CORESTAT			0x8004
+#define KONA_SDHOST_WP				0x00000002
+#define KONA_SDHOST_CD_SW			0x00000001
+
+#define KONA_SDHOST_COREIMR			0x8008
+#define KONA_SDHOST_IP				0x00000001
+
+#define KONA_SDHOST_COREISR			0x800C
+#define KONA_SDHOST_COREIMSR			0x8010
+#define KONA_SDHOST_COREDBG1			0x8014
+#define KONA_SDHOST_COREGPO_MASK		0x8018
+
+#define SD_DETECT_GPIO_DEBOUNCE_128MS		128
+
+#define KONA_MMC_AUTOSUSPEND_DELAY		(50)
+
+struct sdhci_bcm_kona_dev {
+	struct clk	*peri_clk;
+	struct clk	*sleep_clk;
+
+	struct mutex	write_lock; /* protect back to back writes */
+	unsigned int	max_freq;
+	int		is_8bit;
+	int		irq;
+	int		cd_gpio;
+	int		wp_gpio;
+	int		non_removable;
+};
+
+
+static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
+{
+	unsigned int val;
+	unsigned long timeout;
+
+	/* This timeout should be sufficent for core to reset */
+	timeout = jiffies + msecs_to_jiffies(100);
+
+	/* reset the host using the top level reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_RESET;
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
+		if (time_is_before_jiffies(timeout)) {
+			pr_err("Error: sd host is stuck in reset!!!\n");
+			return -EFAULT;
+		}
+	}
+
+	/* bring the host out of reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val &= ~KONA_SDHOST_RESET;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	mdelay(1);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	return 0;
+}
+
+static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
+{
+	unsigned int val;
+
+	/* enable the interrupt from the IP core */
+	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
+	val |= KONA_SDHOST_IP;
+	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
+
+	/* Enable the AHB clock gating module to the host */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_EN;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	mdelay(1);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+}
+
+/*
+ * Software emulation of the SD card insertion/removal. Set insert=1 for insert
+ * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
+ * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
+ * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
+ */
+static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
+{
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
+	u32 val;
+	unsigned long flags;
+
+	/*
+	 * Back-to-Back register write needs a delay of min 10uS.
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 * We keep 20uS
+	 */
+	mutex_lock(&kona_dev->write_lock);
+	udelay(20);
+	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
+
+	if (insert) {
+		if (gpio_is_valid(kona_dev->wp_gpio)) {
+			int wp_status = gpio_get_value(kona_dev->wp_gpio);
+
+			if (wp_status)
+				val |= KONA_SDHOST_WP;
+			else
+				val &= ~KONA_SDHOST_WP;
+		}
+
+		val |= KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	} else {
+		val &= ~KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	}
+	mutex_unlock(&kona_dev->write_lock);
+
+	return 0;
+}
+
+/*
+ * SD card detection interrupt handler
+ */
+static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *h)
+{
+	struct sdhci_host *host = h;
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
+
+	if (gpio_get_value_cansleep(kona_dev->cd_gpio) == 0) {
+		dev_dbg(mmc_dev(host->mmc),
+			"card inserted\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 1);
+	} else {
+		dev_dbg(mmc_dev(host->mmc),
+			"card removed\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Get the base clock. Use central clock source for now. Not sure if different
+ * clock speed to each dev is allowed
+ */
+static unsigned int sdhci_bcm_kona_get_max_clk(struct sdhci_host *host)
+{
+	struct sdhci_bcm_kona_dev *kona_dev;
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	kona_dev = sdhci_pltfm_priv(pltfm_priv);
+
+	return kona_dev->max_freq;
+}
+
+static unsigned int sdhci_bcm_kona_get_timeout_clock(struct sdhci_host *host)
+{
+	return sdhci_bcm_kona_get_max_clk(host);
+}
+
+static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
+				u8 power_mode)
+{
+	/*
+	 *  JEDEC and SD spec specify supplying 74 continuous clocks to
+	 * device after power up. With minimum bus (100KHz) that
+	 * that translates to 740us
+	 */
+	if (power_mode != MMC_POWER_OFF)
+		udelay(740);
+}
+
+static struct sdhci_ops sdhci_bcm_kona_ops = {
+	.get_max_clock = sdhci_bcm_kona_get_max_clk,
+	.get_timeout_clock = sdhci_bcm_kona_get_timeout_clock,
+	.platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
+};
+
+static struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
+	.ops    = &sdhci_bcm_kona_ops,
+	.quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
+		SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
+		SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
+		SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+static const struct of_device_id sdhci_bcm_kona_of_match[] __initdata = {
+	{ .compatible = "bcm,kona-sdhci"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
+
+static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sdhci_bcm_kona_dev *kona_dev = NULL;
+	struct sdhci_pltfm_host *pltfm_priv;
+	struct device *dev = &pdev->dev;
+	struct sdhci_host *host;
+	int ret;
+	unsigned int irq;
+	u32 temp;
+
+	ret = 0;
+
+	host = sdhci_pltfm_init(pdev, &sdhci_pltfm_data_kona,
+			sizeof(*kona_dev));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
+
+	pltfm_priv = sdhci_priv(host);
+
+	kona_dev = sdhci_pltfm_priv(pltfm_priv);
+	mutex_init(&kona_dev->write_lock);
+
+	kona_dev->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
+	kona_dev->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
+	if (of_property_read_bool(np, "non-removable"))
+		kona_dev->non_removable = 1;
+
+	if (of_property_read_u32(np, "bus-width", &temp) == 0 && temp == 8)
+		kona_dev->is_8bit = 1;
+
+	if (of_property_read_u32(np, "max-frequency", &kona_dev->max_freq)) {
+		dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
+		ret = -ENXIO;
+		goto err_pltfm_free;
+	}
+
+	dev_dbg(dev, "non-removable=%c\n",
+		(kona_dev->non_removable) ? 'Y' : 'N');
+	dev_dbg(dev, "cd_gpio %d, wp_gpio %d\n", kona_dev->cd_gpio,
+		kona_dev->wp_gpio);
+
+	if (kona_dev->non_removable) {
+		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+	}
+
+	dev_dbg(dev, "is_8bit=%c\n", (kona_dev->is_8bit) ? 'Y' : 'N');
+	if (kona_dev->is_8bit)
+		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+	ret = sdhci_bcm_kona_sd_reset(host);
+	if (ret)
+		goto err_pltfm_free;
+
+	sdhci_bcm_kona_sd_init(host);
+
+	ret = sdhci_add_host(host);
+	if (ret) {
+		dev_err(dev, "Failed sdhci_add_host\n");
+		goto err_reset;
+	}
+
+	/* if device is eMMC, emulate card insert right here */
+	if (kona_dev->non_removable) {
+		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
+		if (ret) {
+			dev_err(dev,
+				"unable to emulate card insertion\n");
+			goto err_remove_host;
+		}
+	} else if (gpio_is_valid(kona_dev->cd_gpio)) {
+		ret = devm_gpio_request(dev, kona_dev->cd_gpio, "sdio cd");
+		if (ret < 0) {
+			dev_err(mmc_dev(host->mmc),
+				"Unable to request GPIO pin %d\n",
+				kona_dev->cd_gpio);
+			goto err_remove_host;
+		}
+
+		gpio_direction_input(kona_dev->cd_gpio);
+
+		/* Set debounce for SD Card detect to maximum value (128ms)
+		 *
+		 * NOTE-1: If gpio_set_debounce() returns error we still
+		 * continue with the default debounce value set. Another reason
+		 * for doing this is that on rhea-ray boards the SD Detect GPIO
+		 * is on GPIO Expander and gpio_set_debounce() will return error
+		 * and if we return error from here, then probe() would fail and
+		 * SD detection would always fail.
+		 *
+		 * NOTE-2: We also give a msleep() of the "debounce" time here
+		 * so that we give enough time for the debounce to stabilize
+		 * before we read the gpio value in gpio_get_value_cansleep().
+		 */
+		ret = gpio_set_debounce(kona_dev->cd_gpio,
+				(SD_DETECT_GPIO_DEBOUNCE_128MS * 1000));
+		if (ret < 0) {
+			dev_err(mmc_dev(host->mmc),
+				"%s: gpio set debounce failed."
+				"default debounce value assumed\n", __func__);
+		}
+
+		/* Sleep for 128ms to allow debounce to stabilize */
+		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
+		/* request irq for cd_gpio after the gpio debounce is
+		 * stabilized, otherwise, some bogus gpio interrupts might be
+		 * triggered.
+		 */
+		irq = gpio_to_irq(kona_dev->cd_gpio);
+		ret = devm_request_threaded_irq(dev,
+				irq,
+				NULL,
+				sdhci_bcm_kona_pltfm_cd_interrupt,
+				IRQF_TRIGGER_FALLING|
+				IRQF_TRIGGER_RISING |
+				IRQF_ONESHOT |
+				IRQF_NO_SUSPEND, "sdio cd", host);
+		if (ret) {
+			dev_err(mmc_dev(host->mmc),
+				"Failed irq %d request for gpio=%d ret=%d\n",
+				gpio_to_irq(kona_dev->cd_gpio),
+				kona_dev->cd_gpio, ret);
+			goto err_remove_host;
+		}
+		if (gpio_is_valid(kona_dev->wp_gpio)) {
+			ret = devm_gpio_request(dev,
+				kona_dev->wp_gpio, "sdio wp");
+			if (ret < 0) {
+				dev_err(&pdev->dev,
+					"Unable to request WP pin %d\n",
+					kona_dev->wp_gpio);
+				kona_dev->wp_gpio = -1;
+			} else {
+				gpio_direction_input(kona_dev->wp_gpio);
+			}
+		}
+
+		/*
+		 * Since the card detection GPIO interrupt is configured to be
+		 * edge sensitive, check the initial GPIO value here, emulate
+		 * only if the card is present
+		 */
+		if (gpio_get_value_cansleep(kona_dev->cd_gpio) == 0)
+			sdhci_bcm_kona_sd_card_emulate(host, 1);
+	}
+
+	dev_dbg(dev, "initialized properly\n");
+	return 0;
+
+err_remove_host:
+	sdhci_remove_host(host, 0);
+
+err_reset:
+	sdhci_bcm_kona_sd_reset(host);
+
+err_pltfm_free:
+	sdhci_pltfm_free(pdev);
+
+	dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
+	return ret;
+}
+
+static int __exit sdhci_bcm_kona_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	int dead;
+	u32 scratch;
+
+	dead = 0;
+	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
+	if (scratch == (u32)-1)
+		dead = 1;
+	sdhci_remove_host(host, dead);
+
+	sdhci_free_host(host);
+
+	return 0;
+}
+
+static struct platform_driver sdhci_bcm_kona_driver = {
+	.driver		= {
+		.name	= "sdhci-kona",
+		.owner	= THIS_MODULE,
+		.pm	= SDHCI_PLTFM_PMOPS,
+		.of_match_table = of_match_ptr(sdhci_bcm_kona_of_match),
+	},
+	.probe		= sdhci_bcm_kona_probe,
+	.remove		= __exit_p(sdhci_bcm_kona_remove),
+};
+module_platform_driver(sdhci_bcm_kona_driver);
+
+MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
+MODULE_AUTHOR("Broadcom");
+MODULE_LICENSE("GPL v2");
+
-- 
1.7.10.4




From nicolas.pitre at linaro.org  Tue May 28 21:54:04 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 28 May 2013 21:54:04 -0400 (EDT)
Subject: Single zImage and A15/LPAE
In-Reply-To: <180001ce5c03$60cbcf70$22636e50$%kim@samsung.com>
References: <50735B75.8070109@wwwdotorg.org>
 <alpine.LFD.2.02.1210082201470.16518@xanadu.home>
 <2043931.InXdkgrjkp@wuerfel> <20121009141736.GB2122@linaro.org>
 <180001ce5c03$60cbcf70$22636e50$%kim@samsung.com>
Message-ID: <alpine.LFD.2.03.1305282148560.1918@syhkavp.arg>

On Wed, 29 May 2013, Kukjin Kim wrote:

> Dave Martin wrote:
> > On Tue, Oct 09, 2012 at 07:51:02AM +0000, Arnd Bergmann wrote:
> > > On Monday 08 October 2012 22:18:24 Nicolas Pitre wrote:
> > > > On Mon, 8 Oct 2012, Stephen Warren wrote:
> > > >
> > > > > I'm curious what the single-zImage story is for Cortex A15 CPUs with
> > > > > LPAE extensions; IIRC, LPAE entails a different page table format
> > and so
> > > > > isn't going to co-exist in the same zImage as non-LPAE
> > > >
> > > > LPAE vs non LPAE is an even more invasive change than ARMv6+ vs pre
> > > > ARMv6 support.  So no, I don't think we'll ever support LPAE and non
> > > > LPAE configs in the same kernel binary.
> > > >
> > > > > (although doesn't x86 support that now; I though separate
> > > > > LPAE/non-LPAE kernels went away there?)
> > > >
> > > > I don't think so.  At least Ubuntu apparently still carries a PAE and
> > > > non PAE kernel packages.  Fedora doesn't, probably because they
> > decided
> > > > not to support non PAE capable machines anymore.  We certainly cannot
> > > > make this choice on ARM yet.
> > >
> > > Fedora 18 still has both PAE and non-PAE kernels. I would really hope
> > > they could give up the PAE version in favor of a 64 bit kernel in
> > > the 32 bit distro, but it seems none of the big distros trust the
> > > compat code enough yet. On x86, the number of 32 bit machines still
> > > running with more than 3GB of RAM installed should be very marginal
> > > now, most people running the PAE kernel actually have 64 bit capable
> > > CPUs and have some legacy 32 bit applications that are easier to
> > > run with a 32 bit user space.
> > >
> > > Maybe we get to the same point on ARM in some 10 years, but for
> > > the forseeable future, Cortex-a15 machines with lots of RAM will
> > > be very real and we need to have separate kernels for those.
> > 
> > In the medium term we could work around this with a fat kernel in
> > principle (i.e., bundle a non-LPAE single kernel together with an LPAE
> > one and choose the right one at boot time).  This can be solved outside
> > the kernel if necessary.
> > 
> > This is not great, but the general feeling seems to be that combining
> > LPAE and non-LPAE in the same kernel is just not going to be worth the
> > pain (either in code or runtime impacts).
> > 
> > For AArch64, we obviously have a different kernel binary anyway.
> > 
> (+ Olof, Russell)
> 
> Just note, I found this in my old mail-box...
> 
> So I think, as a result, we need to support separate kernel binary for LPAE
> and non-LPAE and you guys don't hold a different view about it.

LPAE and non-LPAE configurations will most likely never be supported 
together in the same kernel binary.  The runtime cost would simply be 
too high to be worth it.

> Current SSDK5440 and SD5v1 boards which are reference boards for EXYNOS5440
> has over 4GB memory as a default and that's why I'm writing this e-mail. It
> means I should keep separated kernel to support exynos5440 and other exynos
> SoCs.

They could all be supported together but with less than 4GB of memory.


Nicolas


From shawn.guo at linaro.org  Tue May 28 22:00:23 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 10:00:23 +0800
Subject: [PATCH 1/3] ARM: dts: imx28-evk: Enable touchscreen support
In-Reply-To: <201305282029.55905.marex@denx.de>
References: <1360337803-19858-1-git-send-email-festevam@gmail.com>
 <201305280656.27472.marex@denx.de>
 <20130528062711.GB19608@S2101-09.ap.freescale.net>
 <201305282029.55905.marex@denx.de>
Message-ID: <20130529020021.GA370@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 08:29:55PM +0200, Marek Vasut wrote:
> Dear Shawn Guo,
> 
> > On Tue, May 28, 2013 at 06:56:27AM +0200, Marek Vasut wrote:
> > > What is the problem you observe?
> > 
> > The audio playback gives silent output.
> 
> You mean like nothing? Zilch? Not even a loud pop on the start/stop of playback?
> 
Nothing.

> I have no issues with audio + touchscreen on m28evk since like 3.7 or so (even 
> before I pushed the driver mainline), so this is weird. Do you have your 
> speakers connected to LineOut or Speaker output from the SGTL5000 ? In case of 
> LineOut, is your on-board amplifier on ?
> 
Only headphone.

Shawn



From olof at lixom.net  Tue May 28 22:02:48 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 19:02:48 -0700
Subject: Single zImage and A15/LPAE
In-Reply-To: <alpine.LFD.2.03.1305282148560.1918@syhkavp.arg>
References: <50735B75.8070109@wwwdotorg.org>
 <alpine.LFD.2.02.1210082201470.16518@xanadu.home>
 <2043931.InXdkgrjkp@wuerfel> <20121009141736.GB2122@linaro.org>
 <180001ce5c03$60cbcf70$22636e50$%kim@samsung.com>
 <alpine.LFD.2.03.1305282148560.1918@syhkavp.arg>
Message-ID: <CAOesGMh+XHueA0UtnAzYTkysqdLqs93Bp31KJKsqVBa-LkiQbQ@mail.gmail.com>

On Tue, May 28, 2013 at 6:54 PM, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> On Wed, 29 May 2013, Kukjin Kim wrote:
>> (+ Olof, Russell)
>>
>> Just note, I found this in my old mail-box...
>>
>> So I think, as a result, we need to support separate kernel binary for LPAE
>> and non-LPAE and you guys don't hold a different view about it.
>
> LPAE and non-LPAE configurations will most likely never be supported
> together in the same kernel binary.  The runtime cost would simply be
> too high to be worth it.
>
>> Current SSDK5440 and SD5v1 boards which are reference boards for EXYNOS5440
>> has over 4GB memory as a default and that's why I'm writing this e-mail. It
>> means I should keep separated kernel to support exynos5440 and other exynos
>> SoCs.
>
> They could all be supported together but with less than 4GB of memory.

Or the other way around, the other EXYNOS5 CPUs could all enable LPAE
even if they have less than 4GB of memory -- but not EXYNOS4, of
course.

However, instead of forking off and duplicating otherwise
near-identical defconfigs, I suggest just getting your developers used
to passing in CONFIG_LPAE=y on the build command line instead (or in
their local configs for their products, of course). That way there's
less duplication and no need to enable drivers in two places, etc.



-Olof


From olof at lixom.net  Tue May 28 22:04:01 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 19:04:01 -0700
Subject: Single zImage and A15/LPAE
In-Reply-To: <CAOesGMh+XHueA0UtnAzYTkysqdLqs93Bp31KJKsqVBa-LkiQbQ@mail.gmail.com>
References: <50735B75.8070109@wwwdotorg.org>
 <alpine.LFD.2.02.1210082201470.16518@xanadu.home>
 <2043931.InXdkgrjkp@wuerfel> <20121009141736.GB2122@linaro.org>
 <180001ce5c03$60cbcf70$22636e50$%kim@samsung.com>
 <alpine.LFD.2.03.1305282148560.1918@syhkavp.arg>
 <CAOesGMh+XHueA0UtnAzYTkysqdLqs93Bp31KJKsqVBa-LkiQbQ@mail.gmail.com>
Message-ID: <CAOesGMgwOUn_gLryFVA3SfeJZziUUMW1Qt_m0QckePtT18cqSg@mail.gmail.com>

On Tue, May 28, 2013 at 7:02 PM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, May 28, 2013 at 6:54 PM, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
>> On Wed, 29 May 2013, Kukjin Kim wrote:
>>> (+ Olof, Russell)
>>>
>>> Just note, I found this in my old mail-box...
>>>
>>> So I think, as a result, we need to support separate kernel binary for LPAE
>>> and non-LPAE and you guys don't hold a different view about it.
>>
>> LPAE and non-LPAE configurations will most likely never be supported
>> together in the same kernel binary.  The runtime cost would simply be
>> too high to be worth it.
>>
>>> Current SSDK5440 and SD5v1 boards which are reference boards for EXYNOS5440
>>> has over 4GB memory as a default and that's why I'm writing this e-mail. It
>>> means I should keep separated kernel to support exynos5440 and other exynos
>>> SoCs.
>>
>> They could all be supported together but with less than 4GB of memory.
>
> Or the other way around, the other EXYNOS5 CPUs could all enable LPAE
> even if they have less than 4GB of memory -- but not EXYNOS4, of
> course.
>
> However, instead of forking off and duplicating otherwise
> near-identical defconfigs, I suggest just getting your developers used
> to passing in CONFIG_LPAE=y on the build command line instead (or in
> their local configs for their products, of course). That way there's
> less duplication and no need to enable drivers in two places, etc.

Nevermind, I'm smoking crack, that doesn't seem to actually work.
(Besides, it's CONFIG_ARM_LPAE).


-Olof


From gang.chen at asianux.com  Tue May 28 22:06:14 2013
From: gang.chen at asianux.com (Chen Gang)
Date: Wed, 29 May 2013 10:06:14 +0800
Subject: [PATCH] arm64: compiling issue for allmodconfig,
 need "asm/parport.h" by "drivers/parport/parport_pc.c"
In-Reply-To: <20130528170219.GI17912@arm.com>
References: <5177551D.8090007@asianux.com> <20130424082237.GA23397@arm.com>
 <5177B1F0.10106@asianux.com>
 <20130424102327.GF21850@mudshark.cambridge.arm.com>
 <5177BAD0.9000500@asianux.com> <20130424110511.GK23397@arm.com>
 <5199A453.4080402@asianux.com> <20130521131734.GD27002@arm.com>
 <519C1539.10908@asianux.com> <519C7484.9020709@asianux.com>
 <20130528170219.GI17912@arm.com>
Message-ID: <51A56296.1090404@asianux.com>

On 05/29/2013 01:02 AM, Catalin Marinas wrote:
>> > 
>> > After check the Kconfig in drivers, we can find quite a few using long
>> > list args which related with ARCH.
>> > 
>> > And they are not only depend on ARCHs, but also depend on another
>> > things (e.g. VGA_CONSOL also depend on !4xx && !8xx, and another
>> > combinations).
> Given this dependency is on the negation of that symbol, you just remove
> it and have a "depends on HAVE_VGA_CONSOLE". The few architectures that
> need it will have to define it (X86, ARM with a few configurations).
> 

it is "depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV &&
!SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE
|| ARCH_INTEGRATOR || ARCH_NETWINDER)"

So, not only x86, ARM, but also s390, xtensa, alpha, cris, h8300, ia64,
mips... (at least, we do not know, they whether need it or not).


>> > We also can find another long list for depend on, but not related with
>> > ARCH.
>> > 
>> > They seems not quit difficult for reading (in fact, if we separate them
>> > into pieces and let them spread into another areas, the reader will not
>> > see the whole dependency clearly)
>> > 
>> > For fixing bug, better as local as possible, as independent as possible,
>> > it will be OK if only add !ARM64 for PARPORT_PC depend on, and it has
>> > no any negative effect. But if we define CONFIG_HAVE_*, we have to let
>> > it related with multiple platforms.
>> > 
>> > For design: if can bear current design, better not to touch it, I think
>> > current design is still sustainable, and not complex for understanding,
>> > so not need redesign.
> We usually clean some of these as we hit them, otherwise people forget
> about the clean-up later ;).

In fact, I have sent another configuration modification about disabling
CONFIG_BUG. it is in discussing...

We are sure most of architectures do not need CONFIG_BUG, but for
VGA_CONSOLE, we can not be sure most of architectures do not need it.

For CONFIG_BUG issue, it will make noisy for most of architectures, but
for VGA_CONSOLE issue, at least now, it is only effect with arm64.

For CONFIG_BUG issue, it seems we can not provide a satisfied fixing if
not get rid of it, but for VGA_CONSOLE issue, at least we have a
complete fixing way for it.


And now for CONFIG_BUG issue, it is still continuing discussing, and it
seems that can not get a result quickly.

So for VGA_CONSOLE... ;-)


Thanks.
-- 
Chen Gang

Asianux Corporation


From ratbert.chuang at gmail.com  Tue May 28 22:14:58 2013
From: ratbert.chuang at gmail.com (Po-Yu Chuang)
Date: Wed, 29 May 2013 10:14:58 +0800
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <51A4FC08.3060906@ti.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com> <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com> <51A4FC08.3060906@ti.com>
Message-ID: <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>

On Wed, May 29, 2013 at 2:48 AM, Sricharan R <r.sricharan at ti.com> wrote:
>
> On Tuesday 28 May 2013 07:37 PM, Will Deacon wrote:
> > On Tue, May 28, 2013 at 03:03:36PM +0100, Sricharan R wrote:
> >> On Tuesday 28 May 2013 06:35 PM, Will Deacon wrote:
> >>> On Tue, May 28, 2013 at 11:48:20AM +0100, Po-Yu Chuang wrote:
> >>>> This bug was introduced in commit e651eab0.
> >>>> Some v4/v5 platforms failed to boot due to this.
> >>>>
> >>>> Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
> >>>> ---
> >>>>  arch/arm/mm/mmu.c |    4 +++-
> >>>>  1 file changed, 3 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> >>>> index e0d8565..19a43f8 100644
> >>>> --- a/arch/arm/mm/mmu.c
> >>>> +++ b/arch/arm/mm/mmu.c
> >>>> @@ -620,6 +620,8 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
> >>>>                    unsigned long end, phys_addr_t phys,
> >>>>                    const struct mem_type *type)
> >>>>  {
> >>>> +  pmd_t *p = pmd;
> >>>> +
> >>>>  #ifndef CONFIG_ARM_LPAE
> >>>>    /*
> >>>>     * In classic MMU format, puds and pmds are folded in to
> >>>> @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
> >>>>            phys += SECTION_SIZE;
> >>>>    } while (pmd++, addr += SECTION_SIZE, addr != end);
> >>>>
> >>>> -  flush_pmd_entry(pmd);
> >>>> +  flush_pmd_entry(p);
> >>> Wait, shouldn't this flush be *inside* the loop anyway? Otherwise we just
> >>> flush the cacheline containing the first pmd. The flushing code could also
> >>> flush to PoU instead of PoC for UP ARMv7, but that's an unrelated optimisation.
> >>    I think in LPAE this loop iterates once and non LPAE twice.
> >>    So both the entries should be contained in same cache line right ?
> > Dunno, are there any guarantees about alignment of the starting pmd? Even
> > so, the function takes the range as parameters, so I don't think we
> > should tailor it to the caller. It may explain why this hasn't come up
> > sooner though.
> >
> > Will
>
>  This function is not exposed outside. And the ranges passed to this is going
> to not more than 2 entries in any case. If we put the flush inside the loop,
> then we will end up doing an extra flush for the same line. Regarding the
> alignment, I think if the pgd base is aligned, then rest should be fine.
> Will have to check this.
>
> Regards,
>  Sricharan
>

Hi ,

Catalin and Sricharan,
Thanks for your explanation.

Will,
I guess nobody noticed this because the MMU of later v7 processors
fetches page table
from D-cache. It even doesn't need to clean pmd to PoU.

Regards,
Po-Yu


From inki.dae at samsung.com  Tue May 28 22:21:37 2013
From: inki.dae at samsung.com (Inki Dae)
Date: Wed, 29 May 2013 11:21:37 +0900
Subject: Introduce a new helper framework for buffer synchronization
In-Reply-To: <CAKMK7uHf0G4-3YU6mouUTf4n50Q+viNAA13BzSLDWjPNWLwJVQ@mail.gmail.com>
References: <CAAQKjZP=iOmHRpHZCbZD3v_RKUFSn0eM_WVZZvhe7F9g3eTmPA@mail.gmail.com>
 <CAF6AEGuDih-NR-VZCmQfqbvCOxjxreZRPGfhCyL12FQ1Qd616Q@mail.gmail.com>
 <006a01ce504e$0de3b0e0$29ab12a0$%dae@samsung.com>
 <CAF6AEGv2FiKMUpb5s4zHPdj4uVxnQWdVJWL-i1mOOZRxBvMZ4Q@mail.gmail.com>
 <00cf01ce512b$bacc5540$3064ffc0$%dae@samsung.com>
 <CAF6AEGuBexKUpTwm9cjGjkxCTKgEaDhAakeP0RN=rtLS6Qy=Mg@mail.gmail.com>
 <CAAQKjZP37koEPob6yqpn-WxxTh3+O=twyvRzDiEhVJTD8BxQzw@mail.gmail.com>
 <20130520211304.GV12292@phenom.ffwll.local>
 <20130520213033.GW12292@phenom.ffwll.local>
 <032701ce55f1$3e9ba4b0$bbd2ee10$%dae@samsung.com>
 <20130521074441.GZ12292@phenom.ffwll.local>
 <033a01ce5604$c32bd250$498376f0$%dae@samsung.com>
 <CAKMK7uHtk+A7CDZH3qHt+F3H_fdSsWwt-bEPn-N0919oOE+Jkg@mail.gmail.com>
 <012801ce57ba$a5a87fa0$f0f97ee0$%dae@samsung.com>
 <014501ce5ac6$511a8500$f34f8f00$%dae@samsung.com>
 <CAF6AEGvGv539Ktdeg03n783nD+HofDamcJCLX93rzzKGOCV8_Q@mail.gmail.com>
 <005701ce5b57$667c7d40$337577c0$%dae@samsung.com>
 <"CAF6AEGv6E38bwszcFV3sV3yMPjD9BkLM4 asEscJ8Jt5z+duxTQ"@mail.gmail.com>
 <00de01ce5bb2$aa7c6b30$ff754190$%dae@samsung.com>
 <CAKMK7uHf0G4-3YU6mouUTf4n50Q+viNAA13BzSLDWjPNWLwJVQ@mail.gmail.com>
Message-ID: <003c01ce5c13$3f2e8370$bd8b8a50$%dae@samsung.com>



> -----Original Message-----
> From: daniel.vetter at ffwll.ch [mailto:daniel.vetter at ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, May 29, 2013 1:50 AM
> To: Inki Dae
> Cc: Rob Clark; Maarten Lankhorst; linux-fbdev; YoungJun Cho; Kyungmin
Park;
> myungjoo.ham; DRI mailing list; linux-arm-kernel at lists.infradead.org;
> linux-media at vger.kernel.org
> Subject: Re: Introduce a new helper framework for buffer synchronization
> 
> On Tue, May 28, 2013 at 4:50 PM, Inki Dae <inki.dae at samsung.com> wrote:
> > I think I already used reservation stuff any time in that way except
> > ww-mutex. And I'm not sure that embedded system really needs ww-mutex.
> If
> > there is any case,
> > could you tell me the case? I really need more advice and
> understanding :)
> 
> If you have only one driver, you can get away without ww_mutex.
> drm/i915 does it, all buffer state is protected by dev->struct_mutex.
> But as soon as you have multiple drivers sharing buffers with dma_buf
> things will blow up.
> 
> Yep, current prime is broken and can lead to deadlocks.
> 
> In practice it doesn't (yet) matter since only the X server does the
> sharing dance, and that one's single-threaded. Now you can claim that
> since you have all buffers pinned in embedded gfx anyway, you don't
> care. But both in desktop gfx and embedded gfx the real fun starts
> once you put fences into the mix and link them up with buffers, then
> every command submission risks that deadlock. Furthermore you can get
> unlucky and construct a circle of fences waiting on each another (only
> though if the fence singalling fires off the next batchbuffer
> asynchronously).

In our case, we haven't ever experienced deadlock yet but there is still
possible to face with deadlock in case that a process is sharing two buffer
with another process like below,
	Process A committed buffer A and  waits for buffer B,
	Process B committed buffer B and waits for buffer A

That is deadlock and it seems that you say we can resolve deadlock issue
with ww-mutexes. And it seems that we can replace our block-wakeup mechanism
with mutex lock for more performance.

> 
> To prevent such deadlocks you _absolutely_ need to lock _all_ buffers
> that take part in a command submission at once. To do that you either
> need a global lock (ugh) or ww_mutexes.
> 
> So ww_mutexes are the fundamental ingredient of all this, if you don't
> see why you need them then everything piled on top is broken. I think
> until you've understood why exactly we need ww_mutexes there's not
> much point in discussing the finer issues of fences, reservation
> objects and how to integrate it with dma_bufs exactly.
> 
> I'll try to clarify the motivating example in the ww_mutex
> documentation a bit, but I dunno how else I could explain this ...
> 

I don't really want for you waste your time on me. I will trying to apply
ww-mutexes (v4) to the proposed framework for more understanding.

Thanks for your advices.:) 
Inki Dae

> Yours, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



From grant.likely at linaro.org  Tue May 28 22:22:49 2013
From: grant.likely at linaro.org (Grant Likely)
Date: Wed, 29 May 2013 03:22:49 +0100
Subject: [patch 7/8] genirq: generic chip: Add linear irq domain support
In-Reply-To: <20130506142539.450634298@linutronix.de>
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
 <20130506142539.450634298@linutronix.de>
Message-ID: <20130529022249.DE5ED3E14F1@localhost>

On Mon, 06 May 2013 14:30:27 -0000, Thomas Gleixner <tglx at linutronix.de> wrote:
> Provide infrastructure for irq chip implementations which work on
> linear irq domains.
> 
> - Interface to allocate multiple generic chips which are associated to
>   the irq domain.
> 
> - Interface to get the generic chip pointer for a particular hardware
>   interrupt in the domain.
> 
> - irq domain mapping function to install the chip for a particular
>   interrupt.
> 
> Note: This lacks a removal function for now, but this is a draft patch
> the ARM folks to work on.
> 
> [ Sebastian Hesselbarth: Mask cache and pointer math fixups ]
> 
> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>

Hi Thomas,

Acked-by: Grant Likely <grant.likely at linaro.org>

But I have some comments below...

> ---
>  include/linux/irq.h       |   30 +++++++
>  include/linux/irqdomain.h |   12 ++
>  kernel/irq/generic-chip.c |  187 ++++++++++++++++++++++++++++++++++++++++++++--
>  kernel/irq/irqdomain.c    |    6 -
>  4 files changed, 223 insertions(+), 12 deletions(-)
> 
> Index: linux-2.6/include/linux/irq.h
> ===================================================================
> --- linux-2.6.orig/include/linux/irq.h
> +++ linux-2.6/include/linux/irq.h
> @@ -678,6 +678,8 @@ struct irq_chip_type {
>   * @wake_active:	Interrupt is marked as an wakeup from suspend source
>   * @num_ct:		Number of available irq_chip_type instances (usually 1)
>   * @private:		Private data for non generic chip callbacks
> + * @installed:		bitfield to denote installed interrupts
> + * @domain:		irq domain pointer
>   * @list:		List head for keeping track of instances
>   * @chip_types:		Array of interrupt irq_chip_types
>   *
> @@ -699,6 +701,8 @@ struct irq_chip_generic {
>  	u32			wake_active;
>  	unsigned int		num_ct;
>  	void			*private;
> +	unsigned long		installed;

This is probably something that the irqdomain should be keeping track of
internally, but that's an issue for a separate patch series.

[...]
> +struct irq_domain_ops irq_generic_chip_ops = {
> +	.map = irq_map_generic_chip,
> +	.xlate = irq_domain_xlate_onecell,

As discussed on IRC, should use onetwocell here for greater
compatibility with existing bindings.

Cheers,
g.


From shawn.guo at linaro.org  Tue May 28 22:54:30 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 10:54:30 +0800
Subject: [PATCH v5] clocksource: add Freescale Vybrid pit timer support
In-Reply-To: <1369732899-17142-1-git-send-email-b35083@freescale.com>
References: <1369732899-17142-1-git-send-email-b35083@freescale.com>
Message-ID: <20130529025428.GE370@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 05:21:39PM +0800, Jingchang Lu wrote:
> Add Freescale Vybrid Family period interrupt timer support.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>



From horms at verge.net.au  Tue May 28 22:05:51 2013
From: horms at verge.net.au (Simon Horman)
Date: Wed, 29 May 2013 11:05:51 +0900
Subject: build failure: linux-next: ARM/SH-mobile defconfigs: kota2, marzen
In-Reply-To: <87txlmaf2a.fsf@linaro.org>
References: <87txlmaf2a.fsf@linaro.org>
Message-ID: <20130529020550.GC16836@verge.net.au>

On Tue, May 28, 2013 at 03:57:01PM -0700, Kevin Hilman wrote:
> Hello,
> 
> Both kota2_defconfig and marzen_defconfig started failing in the most
> recnet linux-next (next-20130527) but were successful in the previous
> build (next-20130523).
> 
> Both fail wit this error:
> 
> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> /work/kernel/next/drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to `shdma_chan_filter'
> make[1]: *** [vmlinux] Error 1
> make[1]: Target `_all' not remade because of errors.
> 
> Full build logs are available here:
> 
>   https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=kota2_defconfig,label=kernel_cloud/54/console
>   https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=marzen_defconfig,label=kernel_cloud/54/console
> 
> Kevin

Hi Kevin,

thanks for bringing that to my attention.
I'll fix it up.


From zhangwm at marvell.com  Tue May 28 23:10:41 2013
From: zhangwm at marvell.com (Neil Zhang)
Date: Wed, 29 May 2013 11:10:41 +0800
Subject: [PATCH] bring up pxa988 with DT
Message-ID: <1369797042-22174-1-git-send-email-zhangwm@marvell.com>

This patch is supposed to bring up pxa988 SMP.
will change to use CLOCKSOURCE later.

Neil Zhang (1):
  ARM: mmp: bring up pxa988 with device tree support

 arch/arm/boot/dts/pxa988-dkb.dts          |   36 ++++++
 arch/arm/boot/dts/pxa988.dtsi             |  189 +++++++++++++++++++++++++++++
 arch/arm/mach-mmp/Kconfig                 |   27 ++++
 arch/arm/mach-mmp/Makefile                |    2 +
 arch/arm/mach-mmp/common.c                |   11 ++-
 arch/arm/mach-mmp/common.h                |    2 +
 arch/arm/mach-mmp/headsmp.S               |  104 ++++++++++++++++
 arch/arm/mach-mmp/include/mach/addr-map.h |    6 +
 arch/arm/mach-mmp/mmpx-dt.c               |   74 +++++++++++
 arch/arm/mach-mmp/platsmp.c               |  163 +++++++++++++++++++++++++
 arch/arm/mach-mmp/reset.c                 |   66 ++++++++++
 arch/arm/mach-mmp/reset.h                 |   29 +++++
 drivers/clk/mmp/Makefile                  |    1 +
 13 files changed, 709 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/pxa988-dkb.dts
 create mode 100644 arch/arm/boot/dts/pxa988.dtsi
 create mode 100644 arch/arm/mach-mmp/headsmp.S
 create mode 100644 arch/arm/mach-mmp/mmpx-dt.c
 create mode 100644 arch/arm/mach-mmp/platsmp.c
 create mode 100644 arch/arm/mach-mmp/reset.c
 create mode 100644 arch/arm/mach-mmp/reset.h

-- 
1.7.4.1



From zhangwm at marvell.com  Tue May 28 23:10:42 2013
From: zhangwm at marvell.com (Neil Zhang)
Date: Wed, 29 May 2013 11:10:42 +0800
Subject: [PATCH] ARM: mmp: bring up pxa988 with device tree support
In-Reply-To: <1369797042-22174-1-git-send-email-zhangwm@marvell.com>
References: <1369797042-22174-1-git-send-email-zhangwm@marvell.com>
Message-ID: <1369797042-22174-2-git-send-email-zhangwm@marvell.com>

bring up pxa988 with device tree support.

Change-Id: I6fc869b7d5ff8dc6e4eb0042a89429200f7a9fb1
Signed-off-by: Neil Zhang <zhangwm at marvell.com>
Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/boot/dts/pxa988-dkb.dts          |   36 ++++++
 arch/arm/boot/dts/pxa988.dtsi             |  189 +++++++++++++++++++++++++++++
 arch/arm/mach-mmp/Kconfig                 |   27 ++++
 arch/arm/mach-mmp/Makefile                |    2 +
 arch/arm/mach-mmp/common.c                |   11 ++-
 arch/arm/mach-mmp/common.h                |    2 +
 arch/arm/mach-mmp/headsmp.S               |  104 ++++++++++++++++
 arch/arm/mach-mmp/include/mach/addr-map.h |    6 +
 arch/arm/mach-mmp/mmpx-dt.c               |   74 +++++++++++
 arch/arm/mach-mmp/platsmp.c               |  163 +++++++++++++++++++++++++
 arch/arm/mach-mmp/reset.c                 |   66 ++++++++++
 arch/arm/mach-mmp/reset.h                 |   29 +++++
 drivers/clk/mmp/Makefile                  |    1 +
 13 files changed, 709 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/pxa988-dkb.dts
 create mode 100644 arch/arm/boot/dts/pxa988.dtsi
 create mode 100644 arch/arm/mach-mmp/headsmp.S
 create mode 100644 arch/arm/mach-mmp/mmpx-dt.c
 create mode 100644 arch/arm/mach-mmp/platsmp.c
 create mode 100644 arch/arm/mach-mmp/reset.c
 create mode 100644 arch/arm/mach-mmp/reset.h

diff --git a/arch/arm/boot/dts/pxa988-dkb.dts b/arch/arm/boot/dts/pxa988-dkb.dts
new file mode 100644
index 0000000..2cee3ed
--- /dev/null
+++ b/arch/arm/boot/dts/pxa988-dkb.dts
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa988.dtsi"
+
+/ {
+	model = "Marvell PXA988 DKB Development Board";
+	compatible = "mrvl,pxa988-dkb", "mrvl,pxa988";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc {
+		apb at d4000000 {
+			uart1: uart at d4017000 {
+				status = "okay";
+			};
+
+			rtc: rtc at d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa988.dtsi b/arch/arm/boot/dts/pxa988.dtsi
new file mode 100644
index 0000000..567d33d
--- /dev/null
+++ b/arch/arm/boot/dts/pxa988.dtsi
@@ -0,0 +1,189 @@
+/*
+ *  Copyright (C) 2013 Marvell Technology Group Ltd.
+ *  Author: Chao Xie <chao.xie at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+		};
+	};
+
+	gic: interrupt-controller at d1dfe100 {
+		compatible = "arm,cortex-a9-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0xd1dff000 0x1000>,
+		      <0xd1dfe100 0x0100>;
+	};
+
+	L2: l2-cache-controller at d1dfb000 {
+		compatible = "arm,pl310-cache";
+		reg = <0xd1dfb000 0x1000>;
+		arm,data-latency = <2 1 1>;
+		arm,tag-latency = <2 1 1>;
+		arm,pwr-dynamic-clk-gating;
+		arm,pwr-standby-mode;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	local-timer at d1dfe600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0xd1dfe600 0x20>;
+		interrupts = <1 13 0x304>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		axi at d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: wakeupgen at d4282000 {
+				compatible = "mrvl,mmp-intc";
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-wakeup = <0x114 0x3
+						    0x144 0x3>;
+			};
+
+		};
+
+		apb at d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer0: timer at d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <0 13 0x4>;
+			};
+
+			uart1: uart at d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <0 27 0x4>;
+				status = "disabled";
+			};
+
+			uart2: uart at d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <0 28 0x4>;
+				status = "disabled";
+			};
+
+			uart3: uart at d4036000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4036000 0x1000>;
+				interrupts = <0 59 0x4>;
+				status = "disabled";
+			};
+
+			gpio at d4019000 {
+				compatible = "marvell,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio at d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio at d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio at d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio at d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+			};
+
+			twsi1: i2c at d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xd4011000 0x1000>;
+				interrupts = <0 7 0x4>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c at d4037000 {
+				compatible = "mrvl,mmp-twsi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xd4037000 0x1000>;
+				interrupts = <0 54 0x4>;
+				status = "disabled";
+			};
+
+			rtc: rtc at d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <0 5 0x4>,<0 6 0x4>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				status = "disabled";
+			};
+			pmx: pinmux at d401e000 {
+				compatible = "pinconf-single";
+				reg = <0xd401e000 0x330>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				#gpio-range-cells = <3>;
+				ranges;
+
+				pinctrl-single,register-width = <32>;
+				pinctrl-single,function-mask = <7>;
+
+				range: gpio-range {
+					#pinctrl-single,gpio-range-cells = <3>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index ebdda83..0955191 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -107,6 +107,16 @@ config MACH_MMP2_DT
 	  Include support for Marvell MMP2 based platforms using
 	  the device tree.
 
+config MACH_MMPX_DT
+	bool "Support no-PJ/PJ4(ARMv7) platforms from device tree"
+	depends on !CPU_MOHAWK && !CPU_PJ4
+	select CPU_PXA988
+	select USE_OF
+	select PINCTRL
+	select PINCTRL_SINGLE
+	help
+	  Include support for Marvell MMP2 based platforms using
+	  the device tree.
 endmenu
 
 config CPU_PXA168
@@ -123,6 +133,23 @@ config CPU_PXA910
 	help
 	  Select code specific to PXA910
 
+config CPU_PXA988
+	bool
+	select CPU_V7
+	select ARM_GIC
+	select HAVE_SMP
+	select HAVE_ARM_SCU
+	select LOCAL_TIMERS
+	select HAVE_ARM_TWD
+	select COMMON_CLK
+	select CLKSRC_OF
+	select MIGHT_HAVE_CACHE_L2X0
+	help
+	  Say 'Y' here if you want to support the Marvell pxa988-base
+	  platforms.
+	  PXA988 is an SoC with dual-core Cotex-A9 and comunication
+	  processor, code name "Emei".
+
 config CPU_MMP2
 	bool
 	select COMMON_CLK
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 095c155..e572786 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -8,6 +8,7 @@ obj-y				+= common.o devices.o time.o irq.o
 obj-$(CONFIG_CPU_PXA168)	+= pxa168.o
 obj-$(CONFIG_CPU_PXA910)	+= pxa910.o
 obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o
+obj-$(CONFIG_CPU_PXA988)        += platsmp.o headsmp.o reset.o
 
 ifeq ($(CONFIG_COMMON_CLK), )
 obj-y				+= clock.o
@@ -31,5 +32,6 @@ obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
 obj-$(CONFIG_MACH_MMP2_DT)	+= mmp2-dt.o
+obj-$(CONFIG_MACH_MMPX_DT)	+= mmpx-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..0c621bc 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -11,6 +11,10 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -36,7 +40,12 @@ static struct map_desc standard_io_desc[] __initdata = {
 		.virtual	= (unsigned long)AXI_VIRT_BASE,
 		.length		= AXI_PHYS_SIZE,
 		.type		= MT_DEVICE,
-	},
+	}, {
+		.pfn		= __phys_to_pfn(MMP_CORE_PERIPH_PHYS_BASE),
+		.virtual	= (unsigned long)MMP_CORE_PERIPH_VIRT_BASE,
+		.length		= MMP_CORE_PERIPH_PHYS_SIZE,
+		.type		= MT_DEVICE,
+	}
 };
 
 void __init mmp_map_io(void)
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..ea0225f 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,5 +1,7 @@
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
+extern struct smp_operations mmp_smp_ops;
+
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
diff --git a/arch/arm/mach-mmp/headsmp.S b/arch/arm/mach-mmp/headsmp.S
new file mode 100644
index 0000000..2b6177e
--- /dev/null
+++ b/arch/arm/mach-mmp/headsmp.S
@@ -0,0 +1,104 @@
+/*
+ * linux/arch/arm/mach-mmp/headsmp.S
+ *
+ * Copyright (C) 2012 Marvell, Inc.
+ *
+ * Author: Neil Zhang <zhangwm at marvell.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+#include <asm/cache.h>
+#include <asm/assembler.h>
+#include <mach/addr-map.h>
+
+	__CPUINIT
+
+/*
+ * Marvell specific entry point for secondary CPUs.
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate for secondary core, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.
+ */
+	.align L1_CACHE_SHIFT
+
+
+/*
+ * PXA specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(mmp_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	bl	v7_invalidate_l1
+	b	secondary_startup
+ENDPROC(mmp_secondary_startup)
+
+	.align	2
+1:	.long	.
+	.long	pen_release
+
+
+/*
+ * Note: The following code is located into the .data section. This is to
+ *       allow sw_reset_flag and cpu_plugin_handler to be accessed with a
+ *       relative load while we can't rely on any MMU translation.
+ *       Reference from: arch/arm/kernel/sleep.S
+ */
+
+	.data
+	.align
+
+/*
+ * ROM code jumps to this function while waking up from CPU
+ * OFF or software reset state. Physical address of the function is
+ * stored at CA9_WARM_RESET_VECTOR while system is bring up.
+ */
+ENTRY(mmp_cpu_reset_entry)
+	adr	r1, mmp_entry_vectors
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15		@ fetch CPUID
+1:
+	ldr	r2, [r1, r0, lsl #2]    @ get the handler addr for this core
+	cmp	r2, #0
+	movne	pc, r2			@ jump to the handler
+	beq	1b
+ENDPROC(mmp_cpu_reset_entry)
+
+	/* Point to the address that save handlers for each core */
+	.global mmp_entry_vectors
+mmp_entry_vectors:
+	.rept   CONFIG_NR_CPUS
+        .long   0                               @ preserve stack phys ptr here
+	.endr
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
index f88a44c..092005b 100644
--- a/arch/arm/mach-mmp/include/mach/addr-map.h
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -25,6 +25,10 @@
 #define AXI_VIRT_BASE		IOMEM(0xfe200000)
 #define AXI_PHYS_SIZE		0x00200000
 
+#define MMP_CORE_PERIPH_PHYS_BASE	0xd1dfe000
+#define MMP_CORE_PERIPH_VIRT_BASE	IOMEM(0xfe400000)
+#define MMP_CORE_PERIPH_PHYS_SIZE	0x00002000
+
 /* Static Memory Controller - Chip Select 0 and 1 */
 #define SMC_CS0_PHYS_BASE	0x80000000
 #define SMC_CS0_PHYS_SIZE	0x10000000
@@ -43,4 +47,6 @@
 #define CIU_VIRT_BASE		(AXI_VIRT_BASE + 0x82c00)
 #define CIU_REG(x)		(CIU_VIRT_BASE + (x))
 
+#define SCU_VIRT_BASE		(MMP_CORE_PERIPH_VIRT_BASE)
+
 #endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/mmpx-dt.c b/arch/arm/mach-mmp/mmpx-dt.c
new file mode 100644
index 0000000..2ebd057
--- /dev/null
+++ b/arch/arm/mach-mmp/mmpx-dt.c
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmpx-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/regs-apbc.h>
+
+#include "common.h"
+
+/* PXA988 */
+static const struct of_dev_auxdata pxa988_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+void __init pxa988_dt_init_timer(void)
+{
+	extern void __init mmp_dt_init_timer(void);
+	/*
+	 * Is is a SOC timer, and will be used for broadcasting
+	 * when local timers are disabled.
+	 */
+	mmp_dt_init_timer();
+
+	clocksource_of_init();
+}
+
+static void __init pxa988_dt_init_machine(void)
+{
+	l2x0_of_init(0x30800000, 0xFE7FFFFF);
+
+	pxa910_clk_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     pxa988_auxdata_lookup, NULL);
+}
+
+static const char *pxa988_dt_board_compat[] __initdata = {
+	"mrvl,pxa988-dkb",
+	NULL,
+};
+
+DT_MACHINE_START(PXA988_DT, "Marvell PXA988 (Device Tree Support)")
+	.smp		= smp_ops(mmp_smp_ops),
+	.map_io		= mmp_map_io,
+	.init_irq	= irqchip_init,
+	.init_time	= pxa988_dt_init_timer,
+	.init_machine	= pxa988_dt_init_machine,
+	.dt_compat	= pxa988_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/platsmp.c b/arch/arm/mach-mmp/platsmp.c
new file mode 100644
index 0000000..5aafde9
--- /dev/null
+++ b/arch/arm/mach-mmp/platsmp.c
@@ -0,0 +1,163 @@
+/*
+ *  linux/arch/arm/mach-mmp/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/mach-types.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+
+#include <mach/irqs.h>
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "reset.h"
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void __cpuinit write_pen_release(int val)
+{
+	pen_release = val;
+	smp_wmb();
+	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+#ifdef CONFIG_HAVE_ARM_SCU
+static void __iomem *scu_get_base_addr(void)
+{
+	return SCU_VIRT_BASE;
+}
+#endif
+
+static inline unsigned int get_core_count(void)
+{
+	u32 ret = 1;
+#ifdef CONFIG_HAVE_ARM_SCU
+	ret = scu_get_core_count(scu_get_base_addr());
+#endif
+
+	return ret;
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __cpuinit mmp_secondary_init(unsigned int cpu)
+{
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+static int __cpuinit mmp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Avoid timer calibration on slave cpus. Use the value calibrated
+	 * on master cpu. Referenced from tegra3
+	 */
+	preset_lpj = loops_per_jiffy;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	write_pen_release(cpu);
+
+	/* reset the cpu, let it branch to the kernel entry */
+	mmp_cpu_power_up(cpu);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init mmp_smp_init_cpus(void)
+{
+	unsigned int i, ncores = get_core_count();
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+static void __init mmp_smp_prepare_cpus(unsigned int max_cpus)
+{
+	int i;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+#ifdef CONFIG_HAVE_ARM_SCU
+	scu_enable(scu_get_base_addr());
+#endif
+
+	mmp_entry_vector_init();
+}
+
+struct smp_operations mmp_smp_ops __initdata = {
+	.smp_init_cpus		= mmp_smp_init_cpus,
+	.smp_prepare_cpus	= mmp_smp_prepare_cpus,
+	.smp_secondary_init	= mmp_secondary_init,
+	.smp_boot_secondary	= mmp_boot_secondary,
+};
diff --git a/arch/arm/mach-mmp/reset.c b/arch/arm/mach-mmp/reset.c
new file mode 100644
index 0000000..b47e400
--- /dev/null
+++ b/arch/arm/mach-mmp/reset.c
@@ -0,0 +1,66 @@
+/*
+ * linux/arch/arm/mach-mmp/reset.c
+ *
+ * Author:	Neil Zhang <zhangwm at marvell.com>
+ * Copyright:	(C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/smp.h>
+
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+
+#include <mach/addr-map.h>
+
+#include "reset.h"
+
+#define PMU_CC2_AP			APMU_REG(0x0100)
+#define CIU_CA9_WARM_RESET_VECTOR	CIU_REG(0x00d8)
+
+/*
+ * This function is called from boot_secondary to bootup the secondary cpu.
+ */
+void mmp_cpu_power_up(u32 cpu)
+{
+	u32 tmp;
+
+	BUG_ON(cpu == 0);
+
+	tmp = readl(PMU_CC2_AP);
+	if (tmp & CPU_CORE_RST(cpu)) {
+		/* Release secondary core from reset */
+		tmp &= ~(CPU_CORE_RST(cpu)
+			| CPU_DBG_RST(cpu) | CPU_WDOG_RST(cpu));
+		writel(tmp, PMU_CC2_AP);
+	}
+}
+
+void mmp_set_entry_vector(u32 cpu, u32 addr)
+{
+	BUG_ON(cpu >= CONFIG_NR_CPUS);
+
+	mmp_entry_vectors[cpu] = addr;
+	smp_wmb();
+	__cpuc_flush_dcache_area((void *)&mmp_entry_vectors[cpu],
+				sizeof(mmp_entry_vectors[cpu]));
+	outer_clean_range(__pa(&mmp_entry_vectors[cpu]),
+				__pa(&mmp_entry_vectors[cpu + 1]));
+}
+
+void __init mmp_entry_vector_init(void)
+{
+	int cpu;
+
+	/* We will reset from DDR directly by default */
+	writel(__pa(mmp_cpu_reset_entry), CIU_CA9_WARM_RESET_VECTOR);
+
+	for (cpu = 1; cpu < CONFIG_NR_CPUS; cpu++)
+		mmp_set_entry_vector(cpu, __pa(mmp_secondary_startup));
+}
diff --git a/arch/arm/mach-mmp/reset.h b/arch/arm/mach-mmp/reset.h
new file mode 100644
index 0000000..78d5486
--- /dev/null
+++ b/arch/arm/mach-mmp/reset.h
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/reset.h
+ *
+ * Author:	Neil Zhang <zhangwm at marvell.com>
+ * Copyright:	(C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __RESET_PXA988_H__
+#define __RESET_PXA988_H__
+
+#define CPU_CORE_RST(n)	(1 << ((n) * 4 + 16))
+#define CPU_DBG_RST(n)	(1 << ((n) * 4 + 18))
+#define CPU_WDOG_RST(n)	(1 << ((n) * 4 + 19))
+
+extern u32 mmp_entry_vectors[CONFIG_NR_CPUS];
+
+void mmp_secondary_startup(void);
+void mmp_cpu_reset_entry(void);
+
+void mmp_cpu_power_up(u32 cpu);
+void mmp_set_entry_vector(u32 cpu, u32 addr);
+void __init mmp_entry_vector_init(void);
+
+#endif /* __RESET_PXA988_H__ */
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 392d780..59a3f9f7 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -7,3 +7,4 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
 obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
+obj-$(CONFIG_CPU_PXA988) += clk-pxa910.o
-- 
1.7.4.1



From shawn.guo at linaro.org  Tue May 28 23:49:15 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 11:49:15 +0800
Subject: [PATCH v4] tty: serial: add Freescale lpuart driver support
In-Reply-To: <1369733161-19168-1-git-send-email-b35083@freescale.com>
References: <1369733161-19168-1-git-send-email-b35083@freescale.com>
Message-ID: <20130529034913.GF370@S2101-09.ap.freescale.net>

Most of the comments are coding style related.
 
On Tue, May 28, 2013 at 05:26:01PM +0800, Jingchang Lu wrote:
> Add Freescale lpuart driver support. The lpuart device
> can be found on Vybrid VF610 and Layerscape LS-1 SoCs.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v4:
>   Change Vybrid VF610 SoC compatible string to "fsl,vf610-lpuart"
> v3:
>   Change the uart driver name from mvf to lpuart for further share between SoCs.
>   Add bind doc in Documentation/devicetree/bindings/tty/serial.
>   Remove unused #include header lines.
>   Clean up code.
> V2:
>   Remove unused variables and clean up the code.
>   Based on the comments for last version.
> 
>  .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
>  drivers/tty/serial/Kconfig                         |  14 +
>  drivers/tty/serial/Makefile                        |   1 +
>  drivers/tty/serial/fsl_lpuart.c                    | 916 +++++++++++++++++++++
>  include/uapi/linux/serial_core.h                   |   3 +
>  5 files changed, 948 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
>  create mode 100644 drivers/tty/serial/fsl_lpuart.c
> 
> diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
> new file mode 100644
> index 0000000..5cad58c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
> @@ -0,0 +1,14 @@
> +* Freescale Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
> +
> +Required properties:
> +- compatible : Should be "fsl,<soc>-lpuart"
> +- reg : Address and length of the register set for the device
> +- interrupts : Should contain uart interrupt
> +
> +Example:
> +
> +uart0: serial at 40027000 {
> +	       compatible = "fsl,vf610-lpuart";
> +	       reg = <0x40027000 0x1000>;
> +	       interrupts = <0 61 0x00>;
> +       };
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 7e7006f..0841125 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1484,6 +1484,20 @@ config SERIAL_RP2_NR_UARTS
>  	  If multiple cards are present, the default limit of 32 ports may
>  	  need to be increased.
>  
> +config SERIAL_FSL_LPUART
> +	bool "Freescale Lpuart serial port support"
> +	select SERIAL_CORE
> +	help
> +	  Support for the on-chip LPUARTs on some Freescale SOCs.
> +
> +config SERIAL_FSL_LPUART_CONSOLE
> +	bool "Console on Freescale LPUART serial port"
> +	depends on SERIAL_FSL_LPUART
> +	select SERIAL_CORE_CONSOLE
> +	help
> +	  If you have enabled the lpuart serial port on the Freescale SoCs,
> +	  you can make it the console by answering Y to this option.
> +
I have seen LPUART, Lpuart and lpuart in bool prompt and help text.  Can
you make them consistent?  Or you have some convention on your mind that
which one should be used in which case?

>  endmenu
>  
>  endif # TTY
> diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
> index eedfec4..cf650f0 100644
> --- a/drivers/tty/serial/Makefile
> +++ b/drivers/tty/serial/Makefile
> @@ -85,3 +85,4 @@ obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
>  obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
>  obj-$(CONFIG_SERIAL_ARC)	+= arc_uart.o
>  obj-$(CONFIG_SERIAL_RP2)	+= rp2.o
> +obj-$(CONFIG_SERIAL_FSL_LPUART)	+= fsl_lpuart.o
> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
> new file mode 100644
> index 0000000..e6c5c7c
> --- /dev/null
> +++ b/drivers/tty/serial/fsl_lpuart.c
> @@ -0,0 +1,916 @@
> +/*
> + *  Freescale lpuart ports driver
> + *
> + *  Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
> +#define SUPPORT_SYSRQ
> +#endif
> +
> +#include <linux/module.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/clk.h>
> +#include <linux/of_device.h>
> +#include <linux/console.h>
> +#include <linux/tty.h>
> +#include <linux/tty_flip.h>
> +#include <linux/serial_core.h>
> +#include <linux/pinctrl/consumer.h>

This header is not needed.

> +
> +/* All registers are 8-bit width */
> +#define UARTBDH			0x00
> +#define UARTBDL			0x01
> +#define UARTCR1			0x02
> +#define UARTCR2			0x03
> +#define UARTSR1			0x04
> +#define UARTCR3			0x06
> +#define UARTDR			0x07
> +#define UARTCR4			0x0a
> +#define UARTCR5			0x0b
> +#define UARTMODEM		0x0d
> +#define UARTPFIFO		0x10
> +#define UARTCFIFO		0x11
> +#define UARTSFIFO		0x12
> +#define UARTTWFIFO		0x13
> +#define UARTTCFIFO		0x14
> +#define UARTRWFIFO		0x15
> +
> +#define UARTBDH_LBKDIE		0x80
> +#define UARTBDH_RXEDGIE		0x40
> +#define UARTBDH_SBR_MASK	0x1f
> +
> +#define UARTCR1_LOOPS		0x80
> +#define UARTCR1_RSRC		0x20
> +#define UARTCR1_M		0x10
> +#define UARTCR1_WAKE		0x08
> +#define UARTCR1_ILT		0x04
> +#define UARTCR1_PE		0x02
> +#define UARTCR1_PT		0x01
> +
> +#define UARTCR2_TIE		0x80
> +#define UARTCR2_TCIE		0x40
> +#define UARTCR2_RIE		0x20
> +#define UARTCR2_ILIE		0x10
> +#define UARTCR2_TE		0x08
> +#define UARTCR2_RE		0x04
> +#define UARTCR2_RWU		0x02
> +#define UARTCR2_SBK		0x01
> +
> +#define UARTSR1_TDRE		0x80
> +#define UARTSR1_TC		0x40
> +#define UARTSR1_RDRF		0x20
> +#define UARTSR1_IDLE		0x10
> +#define UARTSR1_OR		0x08
> +#define UARTSR1_NF		0x04
> +#define UARTSR1_FE		0x02
> +#define UARTSR1_PE		0x01
> +
> +#define UARTCR3_R8		0x80
> +#define UARTCR3_T8		0x40
> +#define UARTCR3_TXDIR		0x20
> +#define UARTCR3_TXINV		0x10
> +#define UARTCR3_ORIE		0x08
> +#define UARTCR3_NEIE		0x04
> +#define UARTCR3_FEIE		0x02
> +#define UARTCR3_PEIE		0x01
> +
> +#define UARTCR4_MAEN1		0x80
> +#define UARTCR4_MAEN2		0x40
> +#define UARTCR4_M10		0x20
> +#define UARTCR4_BRFA_MASK	0x1f
> +#define UARTCR4_BRFA_OFF	0
> +
> +#define UARTCR5_TDMAS		0x80
> +#define UARTCR5_RDMAS		0x20
> +
> +#define UARTMODEM_RXRTSE	0x08
> +#define UARTMODEM_TXRTSPOL	0x04
> +#define UARTMODEM_TXRTSE	0x02
> +#define UARTMODEM_TXCTSE	0x01
> +
> +#define UARTPFIFO_TXFE		0x80
> +#define UARTPFIFO_FIFOSIZE_MASK	0x7
> +#define UARTPFIFO_TXSIZE_OFF	4
> +#define UARTPFIFO_RXFE		0x08
> +#define UARTPFIFO_RXSIZE_OFF	0
> +
> +#define UARTCFIFO_TXFLUSH	0x80
> +#define UARTCFIFO_RXFLUSH	0x40
> +#define UARTCFIFO_RXOFE		0x04
> +#define UARTCFIFO_TXOFE		0x02
> +#define UARTCFIFO_RXUFE		0x01
> +
> +#define UARTSFIFO_TXEMPT	0x80
> +#define UARTSFIFO_RXEMPT	0x40
> +#define UARTSFIFO_RXOF		0x04
> +#define UARTSFIFO_TXOF		0x02
> +#define UARTSFIFO_RXUF		0x01
> +
> +#define DRIVER_NAME	"LP-uart"
> +#define DEV_NAME	"ttyLP"
> +#define UART_NR		6
> +
> +struct lpuart_port {
> +	struct uart_port	port;
> +	struct clk		*clk;
> +	unsigned int		tx_fifo_size;
> +	unsigned int		rx_fifo_size;
> +};
> +
> +static struct of_device_id lpuart_uart_dt_ids[] = {
> +	{
> +		.compatible = "fsl,vf610-lpuart",
> +	},
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, lpuart_uart_dt_ids);
> +
> +static void lpuart_stop_tx(struct uart_port *port)
> +{
> +	struct lpuart_port *sport = (struct lpuart_port *)port;
> +	unsigned char temp;
> +
> +	temp = readb(sport->port.membase + UARTCR2);
> +	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
> +	writeb(temp, sport->port.membase + UARTCR2);
> +}
> +
> +static void lpuart_stop_rx(struct uart_port *port)
> +{
> +	struct lpuart_port *sport = (struct lpuart_port *)port;
> +	unsigned char temp;
> +
> +	temp = readb(sport->port.membase + UARTCR2);
> +	writeb(temp & ~UARTCR2_RE, sport->port.membase + UARTCR2);
> +}
> +
> +static void lpuart_enable_ms(struct uart_port *port)
> +{
> +}
> +
> +static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
> +{
> +	struct circ_buf *xmit = &sport->port.state->xmit;
> +
> +	while (!uart_circ_empty(xmit) &&
> +	(readb(sport->port.membase + UARTTCFIFO) < sport->tx_fifo_size)) {

Fix the indentation please.

> +		writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
> +		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
> +		sport->port.icount.tx++;
> +	}
> +
> +	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
> +		uart_write_wakeup(&sport->port);
> +
> +	if (uart_circ_empty(xmit))
> +		lpuart_stop_tx(&sport->port);
> +}
> +
> +static void lpuart_start_tx(struct uart_port *port)
> +{
> +	struct lpuart_port *sport = (struct lpuart_port *)port;
> +	unsigned char temp;
> +
> +	temp = readb(sport->port.membase + UARTCR2);
> +	writeb(temp | UARTCR2_TIE,
> +			sport->port.membase + UARTCR2);
> +
> +	if (readb(sport->port.membase + UARTSR1) & UARTSR1_TDRE)
> +		lpuart_transmit_buffer(sport);
> +}
> +
> +static irqreturn_t lpuart_txint(int irq, void *dev_id)
> +{
> +	struct lpuart_port *sport = dev_id;
> +	struct circ_buf *xmit = &sport->port.state->xmit;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&sport->port.lock, flags);
> +	if (sport->port.x_char) {
> +		writeb(sport->port.x_char, sport->port.membase + UARTDR);
> +		goto out;
> +	}
> +
> +	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
> +		lpuart_stop_tx(&sport->port);
> +		goto out;
> +	}
> +
> +	lpuart_transmit_buffer(sport);
> +
> +	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
> +		uart_write_wakeup(&sport->port);
> +
> +out:
> +	spin_unlock_irqrestore(&sport->port.lock, flags);
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t lpuart_rxint(int irq, void *dev_id)
> +{
> +	struct lpuart_port *sport = dev_id;
> +	unsigned int flg, ignored = 0;
> +	struct tty_port *port = &sport->port.state->port;
> +	unsigned long flags;
> +	unsigned char r8, rx, sr;
> +
> +	spin_lock_irqsave(&sport->port.lock, flags);
> +
> +	while (!(readb(sport->port.membase + UARTSFIFO) &
> +				UARTSFIFO_RXEMPT)) {
> +		flg = TTY_NORMAL;
> +		sport->port.icount.rx++;
> +
> +		/*  To clear the FE, OR, NF, FE, PE flags when set,
> +		 *  read SR1 then read DR
> +		 */

		/*
		 * multiple lines comment
		 * bla bla
		 */

> +		sr = readb(sport->port.membase + UARTSR1);
> +
> +		r8 = readb(sport->port.membase + UARTCR3) & UARTCR3_R8;
> +		rx = readb(sport->port.membase + UARTDR);
> +
> +		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
> +			continue;
> +		if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
> +			if (sr & UARTSR1_PE)
> +				sport->port.icount.parity++;
> +			else if (sr & UARTSR1_FE)
> +				sport->port.icount.frame++;
> +			if (sr & UARTSR1_OR)
> +				sport->port.icount.overrun++;
> +
> +			if (sr & sport->port.ignore_status_mask) {
> +				if (++ignored > 100)
> +					goto out;
> +				continue;
> +			}
> +
> +			sr &= sport->port.read_status_mask;
> +
> +			if (sr & UARTSR1_PE)
> +				flg = TTY_PARITY;
> +			else if (sr & UARTSR1_FE)
> +				flg = TTY_FRAME;
> +			if (sr & UARTSR1_OR)
> +				flg = TTY_OVERRUN;
> +
> +#ifdef SUPPORT_SYSRQ
> +			sport->port.sysrq = 0;
> +#endif
> +		}
> +
> +		tty_insert_flip_char(port, rx, flg);
> +	}
> +
> +out:
> +	spin_unlock_irqrestore(&sport->port.lock, flags);
> +
> +	tty_flip_buffer_push(port);
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t lpuart_int(int irq, void *dev_id)
> +{
> +	struct lpuart_port *sport = dev_id;
> +	unsigned int sts;
> +
> +	sts = readb(sport->port.membase + UARTSR1);
> +
> +	if (sts & UARTSR1_RDRF)
> +		lpuart_rxint(irq, dev_id);
> +
> +	if (sts & UARTSR1_TDRE &&
> +		!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
> +		lpuart_txint(irq, dev_id);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/*
> + * Return TIOCSER_TEMT when transmitter is not busy.
> + */
> +static unsigned int lpuart_tx_empty(struct uart_port *port)
> +{
> +
Remove the blank line.

> +	return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
> +		TIOCSER_TEMT : 0;
> +}
> +
> +static unsigned int lpuart_get_mctrl(struct uart_port *port)
> +{
> +	unsigned int tmp = 0;
> +	unsigned char reg;
> +
> +	reg = readb(port->membase + UARTMODEM);
> +	if (reg & UARTMODEM_TXCTSE)
> +		tmp |= TIOCM_CTS;
> +
> +	if (reg & UARTMODEM_RXRTSE)
> +		tmp |= TIOCM_RTS;
> +
> +	return tmp;
> +}
> +
> +static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
> +{
> +	unsigned long temp;
> +
> +	temp = readb(port->membase + UARTMODEM) &
> +			~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
> +
> +	if (mctrl & TIOCM_RTS)
> +		temp |= UARTMODEM_RXRTSE;
> +	if (mctrl & TIOCM_CTS)
> +		temp |= UARTMODEM_TXCTSE;
> +
> +	writeb(temp, port->membase + UARTMODEM);
> +}
> +
> +static void lpuart_break_ctl(struct uart_port *port, int break_state)
> +{
> +	unsigned char temp;
> +
> +	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
> +
> +	if (break_state != 0)
> +		temp |= UARTCR2_SBK;
> +
> +	writeb(temp, port->membase + UARTCR2);
> +
ditto

> +}
> +
> +static void lpuart_setup_watermark(struct lpuart_port *sport)
> +{
> +	unsigned char val, old_cr2, cr2;
> +
> +	/* set receiver/transmitter trigger level. */
> +	old_cr2 = cr2 = readb(sport->port.membase + UARTCR2);
> +	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
> +			UARTCR2_RIE | UARTCR2_RE);
> +	writeb(cr2, sport->port.membase + UARTCR2);
> +
> +	writeb(2, sport->port.membase + UARTTWFIFO);
> +	writeb(1, sport->port.membase + UARTRWFIFO);
> +
> +	/* determine FIFO size and enable */
> +	val = readb(sport->port.membase + UARTPFIFO);
> +
> +	sport->tx_fifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
> +		UARTPFIFO_FIFOSIZE_MASK) + 1);
> +
> +	sport->rx_fifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
> +		UARTPFIFO_FIFOSIZE_MASK) + 1);
> +
> +	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
> +			sport->port.membase + UARTPFIFO);
> +
> +	/* Flush the Tx and Rx FIFO to a known state */
> +	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
> +			sport->port.membase + UARTCFIFO);
> +
> +	/* restore CR2 */
> +	writeb(old_cr2, sport->port.membase + UARTCR2);
> +
ditto

> +}
> +
> +static int lpuart_startup(struct uart_port *port)
> +{
> +	struct lpuart_port *sport = (struct lpuart_port *)port;
> +	int retval;
> +	unsigned long flags, temp;
> +
> +	spin_lock_irqsave(&sport->port.lock, flags);
> +
> +	lpuart_setup_watermark(sport);
> +
> +	temp = readb(sport->port.membase + UARTCR2);
> +	writeb(temp & ~UARTCR2_RIE, sport->port.membase + UARTCR2);
> +
> +	/* clear and enable interrupts */
> +	temp = readb(sport->port.membase + UARTCR2);
> +	temp |= UARTCR2_RIE | UARTCR2_TIE;
> +	writeb(temp, sport->port.membase + UARTCR2);
> +
> +	spin_unlock_irqrestore(&sport->port.lock, flags);
> +	/*
> +	 * request the IRQ
> +	 */
The comment is pretty useless.

> +	retval = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
> +				DRIVER_NAME, sport);
> +	if (retval)
> +		return retval;
> +
> +	return 0;
> +}
> +
> +static void lpuart_shutdown(struct uart_port *port)
> +{
> +	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
> +	unsigned char temp;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&port->lock, flags);
> +	temp = readb(port->membase + UARTCR2);
> +	temp &= ~(UARTCR2_TE | UARTCR2_RE);
> +	writeb(temp, port->membase + UARTCR2);
> +	/*
> +	 * Disable all interrupts
> +	 */
> +	temp = readb(port->membase + UARTCR2);
> +	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
> +	writeb(temp, port->membase + UARTCR2);
> +	spin_unlock_irqrestore(&port->lock, flags);
> +	/*
> +	 * Free the irq
> +	 */
ditto

> +	devm_free_irq(port->dev, port->irq, sport);
> +}
> +
> +static void
> +lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
> +		   struct ktermios *old)
> +{
> +	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
> +	unsigned long flags;
> +	unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
> +	unsigned int  baud;
> +	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
> +	unsigned int sbr, brfa;
> +
> +	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
> +	old_cr2 = readb(sport->port.membase + UARTCR2);
> +	cr4 = readb(sport->port.membase + UARTCR4);
> +	bdh = readb(sport->port.membase + UARTBDH);
> +	modem = readb(sport->port.membase + UARTMODEM);
> +
> +	/*
> +	 * We only support CS8 and CS7, and for CS7 must enable PE.
> +	 * supported mode:
> +	 *  - (7,e/o,1)
> +	 *  - (8,n,1)
> +	 *  - (8,m/s,1)
> +	 *  - (8,e/o,1)
> +	 */
> +	while ((termios->c_cflag & CSIZE) != CS8 &&
> +		(termios->c_cflag & CSIZE) != CS7) {
> +		termios->c_cflag &= ~CSIZE;
> +		termios->c_cflag |= old_csize;
> +		old_csize = CS8;
> +	}
> +
> +	if ((termios->c_cflag & CSIZE) == CS8 ||
> +		(termios->c_cflag & CSIZE) == CS7)
> +		cr1 = old_cr1 & ~UARTCR1_M;
> +
> +	if (termios->c_cflag & CMSPAR) {
> +		if ((termios->c_cflag & CSIZE) != CS8) {
> +			termios->c_cflag &= ~CSIZE;
> +			termios->c_cflag |= CS8;
> +		}
> +		cr1 |= UARTCR1_M;
> +	}
> +
> +	if (termios->c_cflag & CRTSCTS) {
> +		modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
> +
Remove it.

> +	} else {
> +		termios->c_cflag &= ~CRTSCTS;
> +		modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
> +	}
> +
> +	if (termios->c_cflag & CSTOPB)
> +		termios->c_cflag &= ~CSTOPB;
> +
> +	/* parity must enable when CS7 to match 8-bits format */
> +	if ((termios->c_cflag & CSIZE) == CS7)
> +		termios->c_cflag |= PARENB;
> +
> +	if ((termios->c_cflag & PARENB)) {
> +		if (termios->c_cflag & CMSPAR) {
> +			cr1 &= ~UARTCR1_PE;
> +			cr1 |= UARTCR1_M;
> +		} else {
> +			cr1 |= UARTCR1_PE;
> +			if ((termios->c_cflag & CSIZE) == CS8)
> +				cr1 |= UARTCR1_M;
> +			if (termios->c_cflag & PARODD)
> +				cr1 |= UARTCR1_PT;
> +			else
> +				cr1 &= ~UARTCR1_PT;
> +		}
> +	}
> +
> +	/*
> +	 * Ask the core to calculate the divisor for us.
> +	 */
> +	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
> +
> +	spin_lock_irqsave(&sport->port.lock, flags);
> +
> +	sport->port.read_status_mask = 0;
> +	if (termios->c_iflag & INPCK)
> +		sport->port.read_status_mask |=
> +					(UARTSR1_FE | UARTSR1_PE);
> +	if (termios->c_iflag & (BRKINT | PARMRK))
> +		sport->port.read_status_mask |= UARTSR1_FE;
> +
> +	/*
> +	 * Characters to ignore
> +	 */
> +	sport->port.ignore_status_mask = 0;
> +	if (termios->c_iflag & IGNPAR)
> +		sport->port.ignore_status_mask |= UARTSR1_PE;
> +	if (termios->c_iflag & IGNBRK) {
> +		sport->port.ignore_status_mask |= UARTSR1_FE;
> +		/*
> +		 * If we're ignoring parity and break indicators,
> +		 * ignore overruns too (for real raw support).
> +		 */
> +		if (termios->c_iflag & IGNPAR)
> +			sport->port.ignore_status_mask |= UARTSR1_OR;
> +	}
> +
> +	/*
> +	 * Update the per-port timeout.
> +	 */
> +	uart_update_timeout(port, termios->c_cflag, baud);
> +
> +	/* wait transmit engin complete */
> +	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
> +		barrier();
> +
> +	writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
> +			sport->port.membase + UARTCR2);
> +
> +	/* disable transmit and receive */
> +	sbr = sport->port.uartclk / (16 * baud);
> +	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
> +
> +	bdh &= ~UARTBDH_SBR_MASK;
> +	bdh |= (sbr >> 8) & 0x1F;
> +
> +	cr4 &= ~UARTCR4_BRFA_MASK;
> +	brfa &= UARTCR4_BRFA_MASK;
> +	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
> +	writeb(bdh, sport->port.membase + UARTBDH);
> +	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
> +	writeb(cr1, sport->port.membase + UARTCR1);
> +	writeb(modem, sport->port.membase + UARTMODEM);
> +
> +	/* restore control register */
> +	writeb(old_cr2, sport->port.membase + UARTCR2);
> +
> +	spin_unlock_irqrestore(&sport->port.lock, flags);
> +}
> +
> +static const char *lpuart_type(struct uart_port *port)
> +{
> +	return "FSL_LPUART";
> +}
> +
> +static void lpuart_release_port(struct uart_port *port)
> +{
> +	/* Nothing to do */
> +}
> +
> +static int lpuart_request_port(struct uart_port *port)
> +{
> +	return  0;
> +}

Add a blank line here.

> +/*
> + * Configure/autoconfigure the port.
> + */
> +static void lpuart_config_port(struct uart_port *port, int flags)
> +{
> +	if (flags & UART_CONFIG_TYPE)
> +		port->type = PORT_LPUART;
> +}
> +
> +static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
> +{
> +	int ret = 0;
> +
> +	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
> +		ret = -EINVAL;
> +	if (port->irq != ser->irq)
> +		ret = -EINVAL;
> +	if (ser->io_type != UPIO_MEM)
> +		ret = -EINVAL;
> +	if (port->uartclk / 16 != ser->baud_base)
> +		ret = -EINVAL;
> +	if (port->iobase != ser->port)
> +		ret = -EINVAL;
> +	if (ser->hub6 != 0)
> +		ret = -EINVAL;
> +	return ret;
> +}
> +
> +static struct uart_ops lpuart_pops = {
> +	.tx_empty	= lpuart_tx_empty,
> +	.set_mctrl	= lpuart_set_mctrl,
> +	.get_mctrl	= lpuart_get_mctrl,
> +	.stop_tx	= lpuart_stop_tx,
> +	.start_tx	= lpuart_start_tx,
> +	.stop_rx	= lpuart_stop_rx,
> +	.enable_ms	= lpuart_enable_ms,
> +	.break_ctl	= lpuart_break_ctl,
> +	.startup	= lpuart_startup,
> +	.shutdown	= lpuart_shutdown,
> +	.set_termios	= lpuart_set_termios,
> +	.type		= lpuart_type,
> +	.request_port	= lpuart_request_port,
> +	.release_port	= lpuart_release_port,
> +	.config_port	= lpuart_config_port,
> +	.verify_port	= lpuart_verify_port,
> +};
> +
> +static struct lpuart_port *lpuart_ports[UART_NR];
> +
> +#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
> +static void lpuart_console_putchar(struct uart_port *port, int ch)
> +{
> +	while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
> +		barrier();
> +
> +	writeb(ch, port->membase + UARTDR);
> +}
> +
> +static void
> +lpuart_console_write(struct console *co, const char *s, unsigned int count)
> +{
> +	struct lpuart_port *sport = lpuart_ports[co->index];
> +	unsigned int  old_cr2, cr2;
> +
> +	/*
> +	 * First, save CR2 and then disable interrupts
> +	 */
> +	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
> +
> +	cr2 |= (UARTCR2_TE |  UARTCR2_RE);
> +	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
> +
> +	writeb(cr2, sport->port.membase + UARTCR2);
> +
> +	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
> +
> +	/*
> +	 * wait for transmitter finish complete and restore CR2
> +	 */
> +	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
> +		barrier();
> +
> +	writeb(old_cr2, sport->port.membase + UARTCR2);
> +}
> +
> +/*
> + * If the port was already initialised (eg, by a boot loader),
> + * try to determine the current setup.
> + */
> +static void __init
> +lpuart_console_get_options(struct lpuart_port *sport, int *baud,
> +			   int *parity, int *bits)
> +{
> +	unsigned char cr, bdh, bdl, brfa;
> +	unsigned int sbr, uartclk;
> +	unsigned int baud_raw;
> +
> +	cr = readb(sport->port.membase + UARTCR2);
> +	cr &= UARTCR2_TE | UARTCR2_RE;
> +	if (!cr)
> +		return;
> +
> +	/* ok, the port was enabled */
> +
> +	cr = readb(sport->port.membase + UARTCR1);
> +
> +	*parity = 'n';
> +	if (cr & UARTCR1_PE) {
> +		if (cr & UARTCR1_PT)
> +			*parity = 'o';
> +		else
> +			*parity = 'e';
> +	}
> +
> +	if (cr & UARTCR1_M)
> +		*bits = 9;
> +	else
> +		*bits = 8;
> +
> +	bdh = readb(sport->port.membase + UARTBDH);
> +	bdh &= UARTBDH_SBR_MASK;
> +	bdl = readb(sport->port.membase + UARTBDL);
> +	sbr = bdh;
> +	sbr <<= 8;
> +	sbr |= bdl;
> +	brfa = readb(sport->port.membase + UARTCR4);
> +	brfa &= UARTCR4_BRFA_MASK;
> +
> +	uartclk = clk_get_rate(sport->clk);
> +	/*
> +	 * Baud = mod_clk/(16*(sbr[13]+(brfa)/32)
> +	 */
> +	baud_raw = uartclk / (16 * (sbr + brfa / 32));
> +
> +	if (*baud != baud_raw)
> +		printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
> +				"from %d to %d\n", baud_raw, *baud);
> +}
> +
> +static int __init lpuart_console_setup(struct console *co, char *options)
> +{
> +	struct lpuart_port *sport;
> +	int baud = 115200;
> +	int bits = 8;
> +	int parity = 'n';
> +	int flow = 'n';
> +
> +	/*
> +	 * Check whether an invalid uart number has been specified, and
> +	 * if so, search for the first available port that does have
> +	 * console support.
> +	 */
> +	if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
> +		co->index = 0;
> +	sport = lpuart_ports[co->index];
> +
> +	if (sport == NULL)
> +		return -ENODEV;
> +
> +	if (options)
> +		uart_parse_options(options, &baud, &parity, &bits, &flow);
> +	else
> +		lpuart_console_get_options(sport, &baud, &parity, &bits);
> +
> +	lpuart_setup_watermark(sport);
> +
> +	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
> +}
> +
> +static struct uart_driver lpuart_reg;
> +static struct console lpuart_console = {
> +	.name		= DEV_NAME,
> +	.write		= lpuart_console_write,
> +	.device		= uart_console_device,
> +	.setup		= lpuart_console_setup,
> +	.flags		= CON_PRINTBUFFER,
> +	.index		= -1,
> +	.data		= &lpuart_reg,
> +};
> +
> +#define LPUART_CONSOLE	(&lpuart_console)
> +#else
> +#define LPUART_CONSOLE	NULL
> +#endif
> +
> +static struct uart_driver lpuart_reg = {
> +	.owner		= THIS_MODULE,
> +	.driver_name	= DRIVER_NAME,
> +	.dev_name	= DEV_NAME,
> +	.nr		= ARRAY_SIZE(lpuart_ports),
> +	.cons		= LPUART_CONSOLE,
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int lpuart_uart_suspend(struct device *dev)
> +{
> +	struct lpuart_port *sport = dev_get_drvdata(dev);
> +
> +	uart_suspend_port(&lpuart_reg, &sport->port);
> +
> +	return 0;
> +}
> +
> +static int lpuart_uart_resume(struct device *dev)
> +{
> +	struct lpuart_port *sport = dev_get_drvdata(dev);
> +
> +	uart_resume_port(&lpuart_reg, &sport->port);
> +
> +	return 0;
> +}
> +#endif

I would suggest you move them right above lpuart_uart_pm_ops.

> +
> +static int lpuart_uart_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct lpuart_port *sport;
> +	void __iomem *base;
> +	struct resource *res;
> +	int ret;
> +
> +	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
> +	if (!sport)
> +		return -ENOMEM;
> +
> +	pdev->dev.coherent_dma_mask = 0;
> +
> +	ret = of_alias_get_id(np, "serial");
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
> +		return ret;
> +	}
> +	sport->port.line = ret;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -ENODEV;
> +
> +	base = devm_request_and_ioremap(&pdev->dev, res);
> +	if (!base)
> +		return -ENOMEM;

See kerneldoc of devm_ioremap_resource() to get a better way of doing this.

> +
> +	sport->port.dev = &pdev->dev;
> +	sport->port.mapbase = res->start;
> +	sport->port.membase = base;
> +	sport->port.type = PORT_LPUART;
> +	sport->port.iotype = UPIO_MEM;
> +	sport->port.irq = platform_get_irq(pdev, 0);
> +	sport->port.ops = &lpuart_pops;
> +	sport->port.flags = UPF_BOOT_AUTOCONF;
> +
> +	sport->clk = devm_clk_get(&pdev->dev, "ipg");
> +	if (IS_ERR(sport->clk)) {
> +		ret = PTR_ERR(sport->clk);
> +		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	clk_prepare_enable(sport->clk);

Check return?

> +
> +	sport->port.uartclk = clk_get_rate(sport->clk);
> +
> +	lpuart_ports[sport->port.line] = sport;
> +
> +	platform_set_drvdata(pdev, &sport->port);
> +
> +	ret = uart_add_one_port(&lpuart_reg, &sport->port);
> +
The blank line is unnecessary.

> +	if (ret) {
> +		clk_disable_unprepare(sport->clk);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int lpuart_uart_remove(struct platform_device *pdev)
> +{
> +	struct lpuart_port *sport = platform_get_drvdata(pdev);
> +
> +	uart_remove_one_port(&lpuart_reg, &sport->port);
> +
> +	clk_disable_unprepare(sport->clk);
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops lpuart_uart_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(lpuart_uart_suspend, lpuart_uart_resume)
> +};

SIMPLE_DEV_PM_OPS could help a little bit if you like.

> +
> +static struct platform_driver lpuart_uart_driver = {
> +	.probe		= lpuart_uart_probe,
> +	.remove		= lpuart_uart_remove,
> +	.driver		= {
> +		.name	= "lpuart-uart",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = lpuart_uart_dt_ids,
> +		.pm	= &lpuart_uart_pm_ops,
> +	},
> +};
> +
> +static int __init lpuart_serial_init(void)
> +{
> +	int ret;
> +
> +	pr_info("serial: Freescale lpuart driver\n");
> +
> +	ret = uart_register_driver(&lpuart_reg);
> +	if (ret)
> +		return ret;
> +
> +	ret = platform_driver_register(&lpuart_uart_driver);
> +	if (ret)
> +		uart_unregister_driver(&lpuart_reg);
> +
> +	return 0;
> +}
> +
> +static void __exit lpuart_serial_exit(void)
> +{
> +	platform_driver_unregister(&lpuart_uart_driver);
> +	uart_unregister_driver(&lpuart_reg);
> +}
> +
> +module_init(lpuart_serial_init);
> +module_exit(lpuart_serial_exit);

I think you can call uart_register_driver and uart_unregister_driver in
.probe and .remove hook, and then you can simply use
module_platform_driver for lpuart_uart_driver.

Shawn

> +
> +MODULE_DESCRIPTION("Freescale LPUART serial driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
> index 74c2bf7..df84fa2 100644
> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -226,4 +226,7 @@
>  /* Rocketport EXPRESS/INFINITY */
>  #define PORT_RP2	102
>  
> +/* Freescale lp-uart */
> +#define PORT_LPUART	103
> +
>  #endif /* _UAPILINUX_SERIAL_CORE_H */
> -- 
> 1.8.0
> 
> 



From xiechao.mail at gmail.com  Tue May 28 23:58:01 2013
From: xiechao.mail at gmail.com (Chao Xie)
Date: Wed, 29 May 2013 11:58:01 +0800
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <20130528162415.GA28253@arwen.pp.htv.fi>
References: <1368424303-10629-5-git-send-email-chao.xie@marvell.com>
 <Pine.LNX.4.44L0.1305131012090.1389-100000@iolanthe.rowland.org>
 <20130528162415.GA28253@arwen.pp.htv.fi>
Message-ID: <CADApbegejeoxc4TmjvsPse=54durFym2cfDRdg9RviDZJ2HAFg@mail.gmail.com>

On Wed, May 29, 2013 at 12:24 AM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, May 13, 2013 at 10:13:44AM -0400, Alan Stern wrote:
>> On Mon, 13 May 2013, Chao Xie wrote:
>>
>> > Originaly, ehci driver will call the callbacks in platform data
>> > for PHY initialization and shut down.
>> > With PHY driver, it will call the APIs provided by PHY driver
>> > for PHY initialization and shutdown. It removes the callbacks
>> > in platform data, and at same time it removes one block in the
>> > way of enabling device tree for ehci driver.
>>
>> I wonder if this is the sort of thing that should be handled in
>> ehci-hcd.c rather than in all the different platform glue drivers.
>>
>> Felipe, what do you think?  Are the required actions now sufficiently
>> generic that a single source file can take care of them?
>
> Sorry for the delay, was on business trip and now on vacations. Anyway,
> I agree with you. Our PHY layer should be generic enough that it should
> be usable by ehci-hcd itself. If we have any missing method, let's add
> it generically.
>
So what are your idea about making the PHY layer more generic? How
ehci-hcd will make use of PHY layer?

> cheers
>
> ps: dropping this from my queue for now.
>
> --
> balbi


From tushar.behera at linaro.org  Tue May 28 23:59:53 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 May 2013 09:29:53 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <20130528231740.GA28879@quad.lixom.net>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net>
Message-ID: <51A57D39.8030506@linaro.org>

On 05/29/2013 04:47 AM, Olof Johansson wrote:
> On Tue, May 14, 2013 at 08:37:53AM +0530, Tushar Behera wrote:
>> On 05/14/2013 05:36 AM, Kevin Hilman wrote:
>>> Tushar Behera <tushar.behera at linaro.org> writes:
>>>
>>>> It updates following drivers for EXYNOS based DT platform.
>>>>
>>>> * S5M8767 driver
>>>> * MAX8997 driver
>>>> * MMC SDHCI driver
>>>>
>>>> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
>>>
>>> I tested this using v3.10-rc1 on Arndale, but still don't get any
>>> support for the wired network.  Do you know if this is a Kconfig issue,
>>> or a missing driver?
>>>
>>> I suspect it may be related to the various "unable to find transceiver
>>> of type USB2 PHY" messages I'm seeing?
>>>
>>
>> Yes, right. The missing USB-PHY components are one of the issues (they
>> were there in linux-next when I last tested).
>>
>> Also, on Arndale board, we need to reset the USB hub during EHCI
>> initialization (a couple of those patches are required, which I am not
>> sure if we would be able to upstream).
>>
>> I am collecting a minimal set of patches that would enable USB and wired
>> network on Arndale with 3.10-rc1 kernel. Once done, I will let you know.
> 
> Hi Tushar,
> 
> Got an update on what these patches are yet?
> 
> 
> -Olof
> 

The patches are at [1]. There are a total of 6 patches on top of
v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
(c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
(e, f) are required to reset the hub during EHCI initialization.

a. ARM: exynos: defconfig update
b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
e. usb: ehci-s5p: add the HSIC port initialization
f. ARM: dts: Add USB gpio entries for Arndale board

I am not sure whether such kind of board-specific patches (e, f) are
appreciated in the drivers. But that is all we need to get USB and
Ethernet to work on v3.10-rc3 kernel.

[1] git://git.linaro.org/landing-teams/working/samsung/kernel.git
(upstream/arndale-usb)

-- 
Tushar Behera


From Ganesh.Kumar at harman.com  Wed May 29 00:00:09 2013
From: Ganesh.Kumar at harman.com (Kumar, Ganesh)
Date: Tue, 28 May 2013 23:00:09 -0500
Subject: VDSO for arm 32bit
In-Reply-To: <20130528092313.GA10474@mudshark.cambridge.arm.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
Message-ID: <634BB1CFA60ED14386C17849392C3EB202E52CA407@HICGWSEX01.ad.harman.com>

On Tue, May 28, 2013 at 08:48:33AM +0100, Kumar, Ganesh wrote:
> Hi Mikel,
> 
> Kumar, Ganesh writes:
>  > Hi All,
>  >
>  > ? I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is  > no support for vdso for arm 32 bit.
>  > I'm planning to port it to arm 32 bit, is there any work under progress?
>  > would like to understand why the support for arm 32 bit is not there, any idea?
> 
> > 32-bit ARM has a "kuser" page at a fixed virtual address, which exports a few critical routines to user-space.  With that, a vdso is mostly redundant.
> 
>   Thanks for the info, my main idea is to get the gettimeofday 
> exported through the kuser helper,tried looking at the sources but I could not find anything related to that seems done in the mainline kernel tree for arm cortex, am I missing something here?
> I plan to do that if its not available yet, right now I've started 
> with the kernel doc for the kuser, any pointers further to get the gettimeofday up and running using the kuser, Thanks in advance for your time.

>>>Be careful here. I had a crack at a gtod implementation for the vectors page in the past, but decided to drop it because it quickly became a maintenance nightmare. Since the layout of >>>the vectors page must be fixed (as userspace jumps to the absolute addresses for the helpers), having large, complicated functions (which gtod does become as you quickly start using >>>the stack to store all of the shared state with the kernel) means that you can quickly back yourself into a corner where the layout of the code cannot change without breaking the ABI.
>>>On top of that, new clock types are added more often than you might think (not to mention bug fixes in the implementation itself), and you end up in a horrible situation where you'd >>>end up deprecating one implementation and adding gettimeofday2 or something equally nasty at a different offset.

>>>Maybe this can be solved by adding loads of padding between the different functions and hoping for the best, but I think a better solution would be to try and add something which is >>>actually a vdso but preserves the function offsets of the current helpers, thus preserving the ABI. That could then replace the vectors page and newer C libraries could make use of >>>the vdso functionality. Of course, that's a lot more work and people might have objections to the approach.

   Hmm, it doesn't seem to be quite straight forward, but thanks for the inputs and caution.
Now that I got a direction, I'm planning to proceed as below:
1. As a first step, get the implementation up and running using the kuser helper (understand the situation and plan to limit my implementation for the ARM Cortex's arch timer clock type)
    On the user land, does this approach needs a change to the libc, kindly confirm. I read the kernel documentation for kuser helper, it gave a nice overview of 
    how things can be done, but not so clear on how actually the helper functions can be called from the user land (the big picture), does it needs a tweak in the libc in order to enable     
    the new helper functions defined.

2. Plan to get it up through the VDSO, study in progress. One question here, was the vdso implementation for 32 bit is not available only because of the frequent addition in new clock types or there is any strong reason or something I need to take care about, kindly clarify.
   I'll start looking into the arm64 vdso code as a starting point, is there anything else I can refer/read to get going? kindly help. 

>>> Finally, I assume you're only interested in the co-processor backed architected timers for this?

   Yes, correct. 

>>> I know some people were toying with exposing memory-mapped timers to userspace, but >>> that really scares me.

   Just curious, what are the side effects of exposing the memory-mapped timers to user space.

Will

GK


From dt.tangr at gmail.com  Wed May 29 01:18:03 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Wed, 29 May 2013 15:18:03 +1000
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <201305271231.40693.arnd@arndb.de>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305262323.29519.arnd@arndb.de>
 <30BA4666-664F-4DA4-A1D5-C2B8AA63C6AB@gmail.com>
 <201305271231.40693.arnd@arndb.de>
Message-ID: <146FF7AD-650E-4706-B9E1-53C2693D1D0D@gmail.com>


On 27/05/2013, at 8:31 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Monday 27 May 2013, Daniel Tang wrote:
>>> The one remaining bit that sticks out is the clcd platform data. As I
>>> said before, I won't require you to convert that to DT in order to
>>> get your code merged, but I'd also really like to see that happen,
>>> as we will also need that to get rid of auxdata on the ARM reference
>>> platforms (integrator, versatile, realview, vexpress).
>> 
>> How would you like me to convert the platform data to DT? AFAIK, the clcd
>> driver isn't aware of DT so the only way is to use the AUXDATA right now.
> 
> Linus Walleij mentioned on IRC that Pawel Moll already posted a series
> that adds DT support for clcd:
> 
> http://lists.freedesktop.org/archives/dri-devel/2013-April/037519.html
> 
> The series does a few more things, but you can probbly split out the
> parts you need and base on that.

Would it be fine if I waited until CLCD DT patch gets into mainline instead?

> 
> 	Arnd

Cheers,
Daniel Tang


From dt.tangr at gmail.com  Wed May 29 01:14:41 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Wed, 29 May 2013 15:14:41 +1000
Subject: [RFC PATCHv4 1/6] arm: TI-Nspire platform code
In-Reply-To: <201305271715.02385.arnd@arndb.de>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305270856.19456.arnd@arndb.de>
 <CAPnH9dnA22C3ZS9jgJNytnmKM_8Vfk7OxNRB1Mg03=q7KhHZBA@mail.gmail.com>
 <201305271715.02385.arnd@arndb.de>
Message-ID: <10704A21-6BEC-42DC-BB1E-88A0E87D288B@gmail.com>


On 28/05/2013, at 1:15 AM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Monday 27 May 2013, Daniel Tang wrote:
>> Before any peripheral is accessed. I.e. before the clocksource and irqchip
>> drivers.
> 
> The irqchip comes first, and by that time, you can actually call
> of_iomap().
> 
>> The write to the port is supposed to ensure all mmio peripherals can be
>> accessed. Without it, access to certain peripherals will result in
>> undefined reads or ignored writes.
>> 
>> On second thoughts, would this actually be the job of the boot loader?
> 
> Doing it in the boot loader would certainly simplify things. I wonder
> about the dynamic aspects of power management though: It might be
> better to expose the individual bits of this register through a proper
> driver. The boot loader can start out enabling everything, but then
> you turn off everything that is not needed when that driver gets
> loaded.

That's the idea for the long term.

For now though, I'll probably just let the bootloader enable everything and work on a proper driver for power management later.

> 
> I'm still not sure what the register actually does: Does it
> control reset lines, clock signals, voltage regulators or something
> else? These things all have their own subsystems, and then there
> is also the power domain framework.

To be perfectly honest, I'm not too sure. The documentation for the TI-Nspire is all gathered from reverse engineering and all it says is that register "disables bus access to peripherals".

> 
> 	Arnd

Cheers,
Daniel Tang

From hvaibhav at ti.com  Wed May 29 01:22:23 2013
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 29 May 2013 05:22:23 +0000
Subject: [PATCH] arm: omap2: fix AM33xx hwmod infos for UART2
In-Reply-To: <1369754265-27712-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1369754265-27712-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EC965EB@DBDE04.ent.ti.com>

> -----Original Message-----
> From: Thomas Petazzoni [mailto:thomas.petazzoni at free-electrons.com]
> Sent: Tuesday, May 28, 2013 8:48 PM
> To: Tony Lindgren
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Hiremath, Vaibhav; Paul Walmsley
> Subject: [PATCH] arm: omap2: fix AM33xx hwmod infos for UART2
> 
> The UART2 hwmod structure is pointing to the EDMA channels of UART1,
> which doesn't look right. This patch fixes this by making the UART2
> hwmod structure to a new structure that lists the EDMA channels to be
> used by the UART2.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |    9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 01d8f32..9113251 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -2006,6 +2006,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
>  	},
>  };
> 
> +/* uart2 */
> +static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
> +	{ .name = "tx",	.dma_req = 28, },
> +	{ .name = "rx",	.dma_req = 29, },
> +	{ .dma_req = -1 }
> +};
> +
>  static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
>  	{ .irq = 73 + OMAP_INTC_START, },
>  	{ .irq = -1 },
> @@ -2016,7 +2023,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
>  	.class		= &uart_class,
>  	.clkdm_name	= "l4ls_clkdm",
>  	.mpu_irqs	= am33xx_uart2_irqs,
> -	.sdma_reqs	= uart1_edma_reqs,
> +	.sdma_reqs	= uart2_edma_reqs,
>  	.main_clk	= "dpll_per_m2_div4_ck",
>  	.prcm		= {
>  		.omap4	= {

Good catch.

Acked-by: Vaibhav Hiremath <hvaibhav at ti.com>

Thanks,
Vaibhav


From jgq516 at gmail.com  Wed May 29 01:25:14 2013
From: jgq516 at gmail.com (jgq516 at gmail.com)
Date: Wed, 29 May 2013 13:25:14 +0800
Subject: ftrace calltrace when boot through kexec
Message-ID: <51A5913A.5030302@gmail.com>

Hello,

When I reboot a preempt_rt 3.4 kernel with cortex a15 tc2 board thru 
kexec, I got below calltrace appeared:

------------[ cut here ]------------
WARNING: at kernel/trace/ftrace.c:1584 ftrace_bug+0x1e0/0x224()
Modules linked in:
[<c0017e14>] (unwind_backtrace+0x0/0x104) from [<c062a468>] 
(dump_stack+0x20/0x24)
[<c062a468>] (dump_stack+0x20/0x24) from [<c00265a4>] 
(warn_slowpath_common+0x64/0x74)
[<c00265a4>] (warn_slowpath_common+0x64/0x74) from [<c00265e0>] 
(warn_slowpath_null+0x2c/0x34)
[<c00265e0>] (warn_slowpath_null+0x2c/0x34) from [<c00bf70c>] 
(ftrace_bug+0x1e0/0x224)
[<c00bf70c>] (ftrace_bug+0x1e0/0x224) from [<c00c03b4>] 
(ftrace_process_locs+0x880/0x930)
[<c00c03b4>] (ftrace_process_locs+0x880/0x930) from [<c082d018>] 
(ftrace_init+0xb4/0x194)
[<c082d018>] (ftrace_init+0xb4/0x194) from [<c081e8c4>] 
(start_kernel+0x338/0x348)
[<c081e8c4>] (start_kernel+0x338/0x348) from [<80008054>] (0x80008054)
---[ end trace af5b256dd27bb7ab ]---
ftrace failed to modify [<c0022b88>] platform_cpu_kill+0x10/0x1c
  actual: 00:40:bd:e8

Add notrace before platform_cpu_kill can workaround this calltrace, but 
it is weird that this problem can't
reproduce in another cortex-a9 (xilinx-zynq) board, could someone give 
some hints about this? Thanks.

Regards,
Xiao




From olof at lixom.net  Wed May 29 01:31:41 2013
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 May 2013 22:31:41 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <51A57D39.8030506@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net>
 <51A57D39.8030506@linaro.org>
Message-ID: <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>

On Tue, May 28, 2013 at 8:59 PM, Tushar Behera <tushar.behera at linaro.org> wrote:

> The patches are at [1].

FWIW, a cgit/gitweb link is easier to follow when you're reading an
email. Anyway, found the patches.

> There are a total of 6 patches on top of
> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
> (c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
> (e, f) are required to reset the hub during EHCI initialization.

Huh, I thought you said that (c) wasn't needed when I posted the
defconfig update. It'd be nice to see the code fixed to handle this
case instead of Linaro carrying a patch like this though. I.e. make it
able to deselect the uart, or make it tied to DEBUG_LL like on other
platforms instead of having a separate config for this.

> a. ARM: exynos: defconfig update
> b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
> c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
> d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
> e. usb: ehci-s5p: add the HSIC port initialization
> f. ARM: dts: Add USB gpio entries for Arndale board
>
> I am not sure whether such kind of board-specific patches (e, f) are
> appreciated in the drivers. But that is all we need to get USB and
> Ethernet to work on v3.10-rc3 kernel.

I've come across a similar situation with wifi reset sequence on the
chromebook. On the product kernel we added some code to the board file
to deal with it, but if we keep doing that things will grow out of
hand.

I don't know if it'll be unpopular, but I think it's time to start a
drivers/platform/arm for these kind of things, and have those drivers
probe on the system compatible value, similar to how x86 does it (with
DMI tables). At least that's my plan for approaching the wifi
reset/power-on sequence on the Chromebook. I hope to have patches in
not all that long...

Likewise, the hub reset/enable code doesn't have to go with the USB
driver, right? I.e. if you cycle reset/enable on the hub after the
host and phy is configured, you'll still have a working setup?


-Olof


From kishon at ti.com  Wed May 29 01:38:46 2013
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Wed, 29 May 2013 11:08:46 +0530
Subject: [PATCH v6 1/9] drivers: phy: add generic PHY framework
In-Reply-To: <51A531A9.4030800@gmail.com>
References: <1367229812-30574-1-git-send-email-kishon@ti.com>
 <1367229812-30574-2-git-send-email-kishon@ti.com>
 <51A531A9.4030800@gmail.com>
Message-ID: <51A59466.6090504@ti.com>

Hi,

On Wednesday 29 May 2013 04:07 AM, Sylwester Nawrocki wrote:
> Hi Kishon,
>
> On 04/29/2013 12:03 PM, Kishon Vijay Abraham I wrote:
>> The PHY framework provides a set of APIs for the PHY drivers to
>> create/destroy a PHY and APIs for the PHY users to obtain a reference
>> to the
>> PHY with or without using phandle. For dt-boot, the PHY drivers should
>> also register *PHY provider* with the framework.
>>
>> PHY drivers should create the PHY by passing id and ops like init, exit,
>> power_on and power_off. This framework is also pm runtime enabled.
>>
>> The documentation for the generic PHY framework is added in
>> Documentation/phy.txt and the documentation for dt binding can be
>> found at
>> Documentation/devicetree/bindings/phy/phy-bindings.txt
>>
>> Signed-off-by: Kishon Vijay Abraham I<kishon at ti.com>
>
> Thanks for working on this. For the record, I plan to give this a try
> in the end of this week, with my simple MIPI CSI/DSI PHY driver. I might
> have some more comments then. For now just couple of remarks after
> reading the documentation.

Thanks for reviewing. I'll wait for your comments before posting the 
next version.

Thanks
Kishon


From monstr at monstr.eu  Wed May 29 01:39:18 2013
From: monstr at monstr.eu (Michal Simek)
Date: Wed, 29 May 2013 07:39:18 +0200
Subject: [PATCH 5/8] ARM: zynq: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-6-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
 <1369665166-13049-6-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <51A59486.4040901@monstr.eu>

On 05/27/2013 04:32 PM, Sanjay Singh Rawat wrote:
> use cpu_do_idle for entering the wfi mode.
> 
> Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
> ---
>  arch/arm/mach-zynq/hotplug.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
> index c89672b..ef0d65d 100644
> --- a/arch/arm/mach-zynq/hotplug.c
> +++ b/arch/arm/mach-zynq/hotplug.c
> @@ -64,8 +64,8 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
>  	 * code will have already disabled interrupts
>  	 */
>  	for (;;) {
> -		dsb();
> -		wfi();
> +		/* enter WFI mode */
> +		cpu_do_idle();
>  
>  		/*
>  		 * Getting here, means that we have come out of WFI without
> 

Applied to zynq/cleanup branch.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From gilles.chanteperdrix at xenomai.org  Wed May 29 01:55:12 2013
From: gilles.chanteperdrix at xenomai.org (Gilles Chanteperdrix)
Date: Wed, 29 May 2013 07:55:12 +0200
Subject: VDSO for arm 32bit
In-Reply-To: <20130528092313.GA10474@mudshark.cambridge.arm.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
Message-ID: <51A59840.3060801@xenomai.org>

On 05/28/2013 11:23 AM, Will Deacon wrote:

> On Tue, May 28, 2013 at 08:48:33AM +0100, Kumar, Ganesh wrote:
>> Hi Mikel,
>>
>> Kumar, Ganesh writes:
>>  > Hi All,
>>  >
>>  >   I'm working on OMAP5 on greg's LTS kernel 3.4.25, but I see there is  > no support for vdso for arm 32 bit.
>>  > I'm planning to port it to arm 32 bit, is there any work under progress?
>>  > would like to understand why the support for arm 32 bit is not there, any idea?
>>
>>> 32-bit ARM has a "kuser" page at a fixed virtual address, which exports a few critical routines to user-space.  With that, a vdso is mostly redundant.
>>
>>   Thanks for the info, my main idea is to get the gettimeofday exported through the kuser helper,tried looking at the sources
>> but I could not find anything related to that seems done in the mainline kernel tree for arm cortex, am I missing something here?
>> I plan to do that if its not available yet, right now I've started with the kernel doc for the kuser, any pointers further
>> to get the gettimeofday up and running using the kuser, Thanks in advance for your time.
> 
> Be careful here. I had a crack at a gtod implementation for the vectors page
> in the past, but decided to drop it because it quickly became a maintenance
> nightmare. Since the layout of the vectors page must be fixed (as userspace
> jumps to the absolute addresses for the helpers), having large, complicated
> functions (which gtod does become as you quickly start using the stack to
> store all of the shared state with the kernel) means that you can quickly
> back yourself into a corner where the layout of the code cannot change
> without breaking the ABI.
> 
> On top of that, new clock types are added more often than you might think
> (not to mention bug fixes in the implementation itself), and you end up in
> a horrible situation where you'd end up deprecating one implementation and
> adding gettimeofday2 or something equally nasty at a different offset.
> 
> Maybe this can be solved by adding loads of padding between the different
> functions and hoping for the best, but I think a better solution would be to
> try and add something which is actually a vdso but preserves the function
> offsets of the current helpers, thus preserving the ABI. That could then
> replace the vectors page and newer C libraries could make use of the vdso
> functionality. Of course, that's a lot more work and people might have
> objections to the approach.
> 
> Finally, I assume you're only interested in the co-processor backed
> architected timers for this? I know some people were toying with exposing
> memory-mapped timers to userspace, but that really scares me.


Hi,

We have been doing this for some time with Xenomai on ARM. What we do is
that:
- the function to read the clocksource is in the kuser area, at a fixed
address, its precise implementation (depending on the clocksource type)
is copied to the vector page when the clocksource is chosen, it expects
the user-space virtual address of the MMIO register in r0;
- for MMIO registers, the library maps the register with /dev/mem;
- the data to handle gettimeofday (so namely, the contents of the
"struct timekeeper" structure) are copied to the equivalent of a vdso.

Regards.

-- 
                                                                Gilles.


From shawn.guo at linaro.org  Wed May 29 02:06:59 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 14:06:59 +0800
Subject: [PATCH v4 2/2] pinctrl: add VF610 pinctrl driver
In-Reply-To: <1369733528-25926-2-git-send-email-b35083@freescale.com>
References: <1369733528-25926-1-git-send-email-b35083@freescale.com>
 <1369733528-25926-2-git-send-email-b35083@freescale.com>
Message-ID: <20130529060658.GH370@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 05:32:08PM +0800, Jingchang Lu wrote:
> Adds Freescale Vybrid VF610 pin controller
> driver to IMX common pinctrl driver framework.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>



From shawn.guo at linaro.org  Wed May 29 02:06:02 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 14:06:02 +0800
Subject: [PATCH RESEND v3 1/2] pinctrl: imx: add VF610 support to imx
 pinctrl framework
In-Reply-To: <1369733528-25926-1-git-send-email-b35083@freescale.com>
References: <1369733528-25926-1-git-send-email-b35083@freescale.com>
Message-ID: <20130529060600.GG370@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 05:32:07PM +0800, Jingchang Lu wrote:
> On some platforms such as VF610, offset of mux and pad ctrl register
> may be zero, and the mux_mode and config_val are in one 32-bit register.
> This patch adds support to imx core pinctrl framework to handle these
> cases.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>



From g.liakhovetski at gmx.de  Wed May 29 02:26:33 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 29 May 2013 08:26:33 +0200 (CEST)
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <20130528024540.GC13532@quad.lixom.net>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
 <20130522143204.GE32012@verge.net.au>
 <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
 <20130528024540.GC13532@quad.lixom.net>
Message-ID: <Pine.LNX.4.64.1305290819190.14157@axis700.grange>

Hi Olof

On Mon, 27 May 2013, Olof Johansson wrote:

> Hi,
> 
> Sorry, a bit behind on email and just discovered this.
> 
> On Wed, May 22, 2013 at 07:22:59PM +0200, Guennadi Liakhovetski wrote:
> 
> > > > The above didn't work in my tests without this:
> > > > 
> > > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
> > > > b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > > index f603c69..4fb0102 100644
> > > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> > > > @@ -33,8 +33,10 @@
> > > >  	};
> > > >  
> > > >  	lbsc {
> > > > +		compatible = "simple-bus";
> > > >  		#address-cells = <1>;
> > > >  		#size-cells = <1>;
> > > > +		ranges = <0 0 0 0x80000000>;
> > > >  
> > > >  		ethernet at 8000000 {
> > > >  			compatible = "smsc,lan9118", "smsc,lan9115";
> > > > 
> > > 
> > > Could you please post this as a formal patch and indicate
> > > if you would like it included as a fix in v3.10 or not?
> > 
> > Can do that, sure, just thought maybe it would be better to fix the 
> > original patch. Besides, I wasn't sure what the correct values for 
> > "ranges" are, I just picked up something, that would be sufficient for 
> > ethernet. But if more devices are added to it in the future, maybe 
> > different ranges values would be needed. I think actually, lbsc should map 
> > the 3 BSC areas, so, the correct property would be
> > 
> > +		ranges = <0 0 0 0x14000000>;
> > 
> > > Also, I am curious to know what your tests are.
> > 
> > Just booting with NFS root. I think, anything involving ethernet. Without 
> > the "simple-bus" property the lbsc node doesn't get scanned, so, no device 
> > is added. Without "ranges" addresses cannot be mapped correctly.
> 
> Since it's a flat mapping you can just specify an empty "ranges" property, no
> need to actually define contents.

Yes, I knew about that, but does this also hold for busses with different 
#address-cells properties, i.e. between 64- and 32-bit busses?

> For more info, see http://devicetree.org/Device_Tree_Usage#Ranges_.28Address_Translation.29

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From shc_work at mail.ru  Wed May 29 02:42:22 2013
From: shc_work at mail.ru (Alexander Shiyan)
Date: Wed, 29 May 2013 10:42:22 +0400
Subject: [PATCH] SPI: Unify simple platform data for some controllers
Message-ID: <1369809742-4220-1-git-send-email-shc_work@mail.ru>

This patch unifies simple pdata for some SPI controllers where only
array of GPIOs is used for define chipselects.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-imx/devices/devices-common.h      |  4 ++--
 arch/arm/mach-imx/devices/platform-spi_imx.c    |  2 +-
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c    |  2 +-
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c  |  2 +-
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c  |  2 +-
 arch/arm/mach-imx/hardware.h                    | 11 ++++++++++
 arch/arm/mach-imx/mach-cpuimx51sd.c             |  2 +-
 arch/arm/mach-imx/mach-mx27_3ds.c               |  4 ++--
 arch/arm/mach-imx/mach-mx31_3ds.c               |  4 ++--
 arch/arm/mach-imx/mach-mx31lilly.c              |  4 ++--
 arch/arm/mach-imx/mach-mx31lite.c               |  2 +-
 arch/arm/mach-imx/mach-mx31moboard.c            |  4 ++--
 arch/arm/mach-imx/mach-mx51_babbage.c           |  2 +-
 arch/arm/mach-imx/mach-pca100.c                 |  2 +-
 arch/arm/mach-imx/mach-pcm037_eet.c             |  2 +-
 arch/arm/mach-imx/mach-pcm038.c                 |  2 +-
 arch/arm/mach-imx/mx31lite-db.c                 |  2 +-
 drivers/spi/spi-clps711x.c                      |  4 ++--
 drivers/spi/spi-imx.c                           |  4 ++--
 include/linux/platform_data/spi-clps711x.h      | 21 -------------------
 include/linux/platform_data/spi-generic-pdata.h | 14 +++++++++++++
 include/linux/platform_data/spi-imx.h           | 27 -------------------------
 22 files changed, 50 insertions(+), 73 deletions(-)
 delete mode 100644 include/linux/platform_data/spi-clps711x.h
 create mode 100644 include/linux/platform_data/spi-generic-pdata.h
 delete mode 100644 include/linux/platform_data/spi-imx.h

diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 453e20b..2f32b79 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -328,7 +328,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
 		const struct imx_sdhci_esdhc_imx_data *data,
 		const struct esdhc_platform_data *pdata);
 
-#include <linux/platform_data/spi-imx.h>
+#include <linux/platform_data/spi-generic-pdata.h>
 struct imx_spi_imx_data {
 	const char *devid;
 	int id;
@@ -338,7 +338,7 @@ struct imx_spi_imx_data {
 };
 struct platform_device *__init imx_add_spi_imx(
 		const struct imx_spi_imx_data *data,
-		const struct spi_imx_master *pdata);
+		const struct spi_generic_pdata *pdata);
 
 struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
 					int irq, int irq_err);
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 8880bcb..f33a49f 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -108,7 +108,7 @@ const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
 
 struct platform_device *__init imx_add_spi_imx(
 		const struct imx_spi_imx_data *data,
-		const struct spi_imx_master *pdata)
+		const struct spi_generic_pdata *pdata)
 {
 	struct resource res[] = {
 		{
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index b2f08bf..40d7c7c 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -273,7 +273,7 @@ static struct spi_board_info __maybe_unused
 
 static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
 
-static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
+static const struct spi_generic_pdata eukrea_mbimx27_spi0_data __initconst = {
 	.chipselect	= eukrea_mbimx27_spi_cs,
 	.num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
 };
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index e2b70f4c..ab65190 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -258,7 +258,7 @@ static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
 
 static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
 
-static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
+static const struct spi_generic_pdata eukrea_mbimxsd25_spi0_data __initconst = {
 	.chipselect     = eukrea_mbimxsd25_spi_cs,
 	.num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
 };
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 5a2d5ef..e6ffb7d 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -264,7 +264,7 @@ static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = {
 
 static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
 
-static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = {
+static const struct spi_generic_pdata eukrea_mbimxsd35_spi0_data __initconst = {
 	.chipselect     = eukrea_mbimxsd35_spi_cs,
 	.num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs),
 };
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index a3b0b04..d3b5a59 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -125,4 +125,15 @@
 /* range e.g. GPIO_1_5 is gpio 5 under linux */
 #define IMX_GPIO_NR(bank, nr)		(((bank) - 1) * 32 + (nr))
 
+/* Macro for using internal CSPI chipselects. Normally you */
+/* want to use gpio based chip selects as the CSPI module tries to be */
+/* intelligent about when to assert the chipselect: The CSPI module */
+/* deasserts the chipselect once it runs out of input data. The other */
+/* problem that it is not possible to mix between high active and low */
+/* active chipselects on one single bus using the internal chipselects. */
+/* Unfortunately Freescale decided to put some chipselects on dedicated */
+/* pins which are not usable as gpios, so we have to support the internal */
+/* chipselects. */
+#define MXC_SPI_CS(no)			((no) - 32)
+
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9b5ddf5..7950151 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -264,7 +264,7 @@ static int cpuimx51sd_spi1_cs[] = {
 	CAN_NCS,
 };
 
-static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
+static const struct spi_generic_pdata cpuimx51sd_ecspi1_pdata __initconst = {
 	.chipselect	= cpuimx51sd_spi1_cs,
 	.num_chipselect	= ARRAY_SIZE(cpuimx51sd_spi1_cs),
 };
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 25b3e4c..2e7cf1c 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -357,14 +357,14 @@ static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
 /* SPI */
 static int spi1_chipselect[] = {SPI1_SS0};
 
-static const struct spi_imx_master spi1_pdata __initconst = {
+static const struct spi_generic_pdata spi1_pdata __initconst = {
 	.chipselect	= spi1_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi1_chipselect),
 };
 
 static int spi2_chipselect[] = {SPI2_SS0};
 
-static const struct spi_imx_master spi2_pdata __initconst = {
+static const struct spi_generic_pdata spi2_pdata __initconst = {
 	.chipselect	= spi2_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi2_chipselect),
 };
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 1ed9161..2ac1974 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -510,7 +510,7 @@ static int spi0_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static const struct spi_imx_master spi0_pdata __initconst = {
+static const struct spi_generic_pdata spi0_pdata __initconst = {
 	.chipselect	= spi0_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi0_internal_chipselect),
 };
@@ -520,7 +520,7 @@ static int spi1_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static const struct spi_imx_master spi1_pdata __initconst = {
+static const struct spi_generic_pdata spi1_pdata __initconst = {
 	.chipselect	= spi1_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
 };
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 832b1e2..426f14a 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -211,12 +211,12 @@ static int spi_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static const struct spi_imx_master spi0_pdata __initconst = {
+static const struct spi_generic_pdata spi0_pdata __initconst = {
 	.chipselect = spi_internal_chipselect,
 	.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static const struct spi_imx_master spi1_pdata __initconst = {
+static const struct spi_generic_pdata spi1_pdata __initconst = {
 	.chipselect = spi_internal_chipselect,
 	.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index bea0729..12f1479 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -106,7 +106,7 @@ static int spi_internal_chipselect[] = {
 	MXC_SPI_CS(0),
 };
 
-static const struct spi_imx_master spi1_pdata __initconst = {
+static const struct spi_generic_pdata spi1_pdata __initconst = {
 	.chipselect	= spi_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi_internal_chipselect),
 };
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index dae4cd7..cf03cc6 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -168,7 +168,7 @@ static int moboard_spi1_cs[] = {
 	MXC_SPI_CS(2),
 };
 
-static const struct spi_imx_master moboard_spi1_pdata __initconst = {
+static const struct spi_generic_pdata moboard_spi1_pdata __initconst = {
 	.chipselect	= moboard_spi1_cs,
 	.num_chipselect	= ARRAY_SIZE(moboard_spi1_cs),
 };
@@ -316,7 +316,7 @@ static int moboard_spi2_cs[] = {
 	MXC_SPI_CS(1),
 };
 
-static const struct spi_imx_master moboard_spi2_pdata __initconst = {
+static const struct spi_generic_pdata moboard_spi2_pdata __initconst = {
 	.chipselect	= moboard_spi2_cs,
 	.num_chipselect	= ARRAY_SIZE(moboard_spi2_cs),
 };
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index f3d264a..a01c76a 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -336,7 +336,7 @@ static int mx51_babbage_spi_cs[] = {
 	BABBAGE_ECSPI1_CS1,
 };
 
-static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
+static const struct spi_generic_pdata mx51_babbage_spi_pdata __initconst = {
 	.chipselect     = mx51_babbage_spi_cs,
 	.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
 };
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb..47580c4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -203,7 +203,7 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
 
 static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
-static const struct spi_imx_master pca100_spi0_data __initconst = {
+static const struct spi_generic_pdata pca100_spi0_data __initconst = {
 	.chipselect	= pca100_spi_cs,
 	.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index 8fd8255..3a6cbcd 100644
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -58,7 +58,7 @@ static struct spi_board_info pcm037_spi_dev[] = {
 /* Platform Data for MXC CSPI */
 static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
 
-static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
+static const struct spi_generic_pdata pcm037_spi1_pdata __initconst = {
 	.chipselect = pcm037_spi1_cs,
 	.num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
 };
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index e805ac2..8c034d8 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -204,7 +204,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
 
 static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
 
-static const struct spi_imx_master pcm038_spi0_data __initconst = {
+static const struct spi_generic_pdata pcm038_spi0_data __initconst = {
 	.chipselect = pcm038_spi_cs,
 	.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
 };
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 5a160b7..4b5f3b1 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -154,7 +154,7 @@ static int spi_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static const struct spi_imx_master spi0_pdata __initconst = {
+static const struct spi_generic_pdata spi0_pdata __initconst = {
 	.chipselect	= spi_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi_internal_chipselect),
 };
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 6859a02..0cd0f00 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -18,7 +18,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
-#include <linux/platform_data/spi-clps711x.h>
+#include <linux/platform_data/spi-generic-pdata.h>
 
 #include <mach/hardware.h>
 
@@ -168,7 +168,7 @@ static int spi_clps711x_probe(struct platform_device *pdev)
 	int i, ret;
 	struct spi_master *master;
 	struct spi_clps711x_data *hw;
-	struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
+	struct spi_generic_pdata *pdata = dev_get_platdata(&pdev->dev);
 
 	if (!pdata) {
 		dev_err(&pdev->dev, "No platform data supplied\n");
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 1e99b57..ad93086 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -38,7 +38,7 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 
-#include <linux/platform_data/spi-imx.h>
+#include <linux/platform_data/spi-generic-pdata.h>
 
 #define DRIVER_NAME "spi_imx"
 
@@ -754,7 +754,7 @@ static int spi_imx_probe(struct platform_device *pdev)
 	struct device_node *np = pdev->dev.of_node;
 	const struct of_device_id *of_id =
 			of_match_device(spi_imx_dt_ids, &pdev->dev);
-	struct spi_imx_master *mxc_platform_info =
+	struct spi_generic_pdata *mxc_platform_info =
 			dev_get_platdata(&pdev->dev);
 	struct spi_master *master;
 	struct spi_imx_data *spi_imx;
diff --git a/include/linux/platform_data/spi-clps711x.h b/include/linux/platform_data/spi-clps711x.h
deleted file mode 100644
index 301956e..0000000
--- a/include/linux/platform_data/spi-clps711x.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  CLPS711X SPI bus driver definitions
- *
- *  Copyright (C) 2012 Alexander Shiyan <shc_work at mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef ____LINUX_PLATFORM_DATA_SPI_CLPS711X_H
-#define ____LINUX_PLATFORM_DATA_SPI_CLPS711X_H
-
-/* Board specific platform_data */
-struct spi_clps711x_pdata {
-	int *chipselect;	/* Array of GPIO-numbers */
-	int num_chipselect;	/* Total count of GPIOs */
-};
-
-#endif
diff --git a/include/linux/platform_data/spi-generic-pdata.h b/include/linux/platform_data/spi-generic-pdata.h
new file mode 100644
index 0000000..6c45a55
--- /dev/null
+++ b/include/linux/platform_data/spi-generic-pdata.h
@@ -0,0 +1,14 @@
+#ifndef _LINUX_PLATFORM_DATA_SPI_GENERIC_PDATA_H
+#define _LINUX_PLATFORM_DATA_SPI_GENERIC_PDATA_H
+
+/*
+ * struct spi_generic_pdata - device.platform_data for SPI controller devices.
+ * @chipselect: Array of chipselects for this master.
+ * @num_chipselect: ARRAY_SIZE(chipselect)
+ */
+struct spi_generic_pdata {
+	int	*chipselect;
+	int	num_chipselect;
+};
+
+#endif
diff --git a/include/linux/platform_data/spi-imx.h b/include/linux/platform_data/spi-imx.h
deleted file mode 100644
index 08be445..0000000
--- a/include/linux/platform_data/spi-imx.h
+++ /dev/null
@@ -1,27 +0,0 @@
-
-#ifndef __MACH_SPI_H_
-#define __MACH_SPI_H_
-
-/*
- * struct spi_imx_master - device.platform_data for SPI controller devices.
- * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio
- *              pins, numbers < 0 mean internal CSPI chipselects according
- *              to MXC_SPI_CS(). Normally you want to use gpio based chip
- *              selects as the CSPI module tries to be intelligent about
- *              when to assert the chipselect: The CSPI module deasserts the
- *              chipselect once it runs out of input data. The other problem
- *              is that it is not possible to mix between high active and low
- *              active chipselects on one single bus using the internal
- *              chipselects. Unfortunately Freescale decided to put some
- *              chipselects on dedicated pins which are not usable as gpios,
- *              so we have to support the internal chipselects.
- * @num_chipselect: ARRAY_SIZE(chipselect)
- */
-struct spi_imx_master {
-	int	*chipselect;
-	int	num_chipselect;
-};
-
-#define MXC_SPI_CS(no)	((no) - 32)
-
-#endif /* __MACH_SPI_H_*/
-- 
1.8.1.5



From mturquette at linaro.org  Wed May 29 02:47:15 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 28 May 2013 23:47:15 -0700
Subject: [PATCH 0/2] clk: add of_clk_provider stubs to enable clk-si5351
 on non OF
In-Reply-To: <1367369910-20402-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1367369910-20402-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130529064715.6058.43702@quantum>

Quoting Sebastian Hesselbarth (2013-04-30 17:58:27)
> Enabling drivers that provide clocks on DT on platforms that don't have
> CONFIG_OF set fails due to compilation errors. This patch set first adds
> some stubs for of_clk_provider functions if CONFIG_OF is not set. Second
> it allows those platforms to build and use clk-si5351 i2c clock driver
> by removing the dependency on CONFIG_OF.
> 
> The above approach has been suggested by Arnd Bergmann and replaces the
> corresponding Kconfig patch for clk-si5351 posted earlier. It has been
> compile tested with allmodconfig on x86_64 for post v3.9.
> 
> Sebastian Hesselbarth (2):
>   clk: add non CONFIG_OF routines for clk-provider
>   clk: si5351: Allow to build without CONFIG_OF
> 

Both are taken into clk-next.

Thanks,
Mike

>  drivers/clk/Kconfig          |    1 -
>  include/linux/clk-provider.h |   47 +++++++++++++++++++++++++++++++++++-------
>  2 files changed, 39 insertions(+), 9 deletions(-)
> ---
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Andrew Morton <akpm at linux-foundation.org>
> Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Daniel Mack <zonque at gmail.com>
> Cc: Lars-Peter Clausen <lars at metafoo.de>
> Cc: Guenter Roeck <linux at roeck-us.net>
> Cc: Marek Belisko <marek.belisko at streamunlimited.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> -- 
> 1.7.10.4


From mturquette at linaro.org  Wed May 29 02:51:19 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 28 May 2013 23:51:19 -0700
Subject: [RFT][PATCH 1/2] clk: wm831x: Fix update wrong register for
 enable/disable FLL
In-Reply-To: <1367422261.8160.1.camel@phoenix>
References: <1367422261.8160.1.camel@phoenix>
Message-ID: <20130529065119.6058.68188@quantum>

Quoting Axel Lin (2013-05-01 08:31:01)
> According to the datasheet, FLL Enable is controlled by
> R16530 (4092h) FLL Control1
>         BIT 0: FLL Enable
>                 0 = Disable
>                 1 = Enable
> 
> Thus the code should update WM831X_FLL_CONTROL_1 register rather than
> WM831X_FLL_CONTROL_2 register.
> 
> Also fixes a trivial typo in dev_crit message.
> 
> Signed-off-by: Axel Lin <axel.lin at ingics.com>

Pulled both into clk-next.

Thanks,
Mike

> ---
>  drivers/clk/clk-wm831x.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
> index 16ed068..4bdf0b0 100644
> --- a/drivers/clk/clk-wm831x.c
> +++ b/drivers/clk/clk-wm831x.c
> @@ -97,7 +97,7 @@ static int wm831x_fll_prepare(struct clk_hw *hw)
>         struct wm831x *wm831x = clkdata->wm831x;
>         int ret;
>  
> -       ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
> +       ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
>                               WM831X_FLL_ENA, WM831X_FLL_ENA);
>         if (ret != 0)
>                 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
> @@ -114,9 +114,9 @@ static void wm831x_fll_unprepare(struct clk_hw *hw)
>         struct wm831x *wm831x = clkdata->wm831x;
>         int ret;
>  
> -       ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
> +       ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
>         if (ret != 0)
> -               dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
> +               dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
>  }
>  
>  static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
> -- 
> 1.8.1.2


From B35083 at freescale.com  Wed May 29 02:57:43 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Wed, 29 May 2013 06:57:43 +0000
Subject: [PATCH v4] tty: serial: add Freescale lpuart driver support
In-Reply-To: <20130529034913.GF370@S2101-09.ap.freescale.net>
References: <1369733161-19168-1-git-send-email-b35083@freescale.com>
 <20130529034913.GF370@S2101-09.ap.freescale.net>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CDEFB@039-SN1MPN1-003.039d.mgd.msft.net>



>> +static int __init lpuart_serial_init(void) {
>> +	int ret;
>> +
>> +	pr_info("serial: Freescale lpuart driver\n");
>> +
>> +	ret = uart_register_driver(&lpuart_reg);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = platform_driver_register(&lpuart_uart_driver);
>> +	if (ret)
>> +		uart_unregister_driver(&lpuart_reg);
>> +
>> +	return 0;
>> +}
>> +
>> +static void __exit lpuart_serial_exit(void) {
>> +	platform_driver_unregister(&lpuart_uart_driver);
>> +	uart_unregister_driver(&lpuart_reg);
>> +}
>> +
>> +module_init(lpuart_serial_init);
>> +module_exit(lpuart_serial_exit);
>
>I think you can call uart_register_driver and uart_unregister_driver
>in .probe and .remove hook, and then you can simply use
>module_platform_driver for lpuart_uart_driver.
[Lu Jingchang-B35083] 
  For multiple dts uart nodes, each node will call .probe once. If the uart_register_driver is called from .probe without any conditioning check, it will then be called more than once, but the uart_register_deiver can only register the same uart driver once. So I think current arrangement will be more reasonable. Thanks!




From mturquette at linaro.org  Wed May 29 03:18:09 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 00:18:09 -0700
Subject: [Patch 3/3] clk: Avoid re-parenting orphan clk's having invalid
 parent index.
In-Reply-To: <1367475929-32166-4-git-send-email-ambresh@ti.com>
References: <1367475929-32166-1-git-send-email-ambresh@ti.com>
 <1367475929-32166-4-git-send-email-ambresh@ti.com>
Message-ID: <20130529071809.6058.24017@quantum>

Quoting Ambresh K (2013-05-01 23:25:29)
> From: Ambresh K <ambresh at ti.com>
> 
> Add orhan clk nodes having invalid parent index to list and use
> the list to skip re-parenting orphan clk having invalid parents.
> 
> Signed-off-by: Ambresh K <ambresh at ti.com>
> ---
>  drivers/clk/clk.c |   21 +++++++++++++++++++--
>  1 files changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index f4d2c73..54d2aa3 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -32,6 +32,7 @@ static int enable_refcnt;
>  
>  static HLIST_HEAD(clk_root_list);
>  static HLIST_HEAD(clk_orphan_list);
> +static HLIST_HEAD(clk_orphan_invalid_parent);

Why not re-use the clk_orphan_list?  Having an invalid value programmed
into the hardware for selecting a parent essetially orphans a clock
from a software point of view.  Is there a specific need for the new
list?

Regards,
Mike

>  static LIST_HEAD(clk_notifier_list);
>  
>  /***           locking             ***/
> @@ -1532,8 +1533,8 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
>   */
>  int __clk_init(struct device *dev, struct clk *clk)
>  {
> -       int i, ret = 0;
> -       struct clk *orphan;
> +       int i, ret = 0, skip = 0;
> +       struct clk *orphan, *has_invalid_parent;
>         struct hlist_node *tmp2;
>  
>         if (!clk)
> @@ -1639,11 +1640,27 @@ int __clk_init(struct device *dev, struct clk *clk)
>                 if (!strcmp(clk->name, orphan->name))
>                         continue;
>  
> +               /* Skip iteration if orphan has invalid parent */
> +               hlist_for_each_entry(has_invalid_parent,
> +                               &clk_orphan_invalid_parent, child_node) {
> +                       if (!strcmp(orphan->name, has_invalid_parent->name)) {
> +                               skip = 1;
> +                               break;
> +                       }
> +               }
> +
> +               if (skip) {
> +                       skip = 0;
> +                       continue;
> +               }
> +
>                 if (orphan->ops->get_parent) {
>                         i = orphan->ops->get_parent(orphan->hw);
>                         if (i < 0) {
>                                 pr_err("%s: orphan clk(%s) invalid parent\n",
>                                                 __func__, orphan->name);
> +                               hlist_add_head(&orphan->child_node,
> +                                               &clk_orphan_invalid_parent);
>                                 continue;
>                         }
>                         if (!strcmp(clk->name, orphan->parent_names[i]))
> -- 
> 1.7.4.1


From mturquette at linaro.org  Wed May 29 03:21:18 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 00:21:18 -0700
Subject: [Patch 1/3] clk: fix clk_mux_get_parent return's signed value
In-Reply-To: <1367475929-32166-2-git-send-email-ambresh@ti.com>
References: <1367475929-32166-1-git-send-email-ambresh@ti.com>
 <1367475929-32166-2-git-send-email-ambresh@ti.com>
Message-ID: <20130529072118.6058.14433@quantum>

Quoting Ambresh K (2013-05-01 23:25:27)
> From: Ambresh K <ambresh at ti.com>
> 
> If for some reason, the value read from clksel field return
> erroneous due to HW bug or improper configuration, then
> clk_mux_get_parent should return appropriate error's.
> 

clksel is an omap-centric term.  How about:

"clk_mux_get_parent should return an error if the value read from the
register is erroneous."

The general approach looks good to me.  Can you submit a V2 which
removes all of the clksel-isms and updates definitions for .get_parent
functions to avoid the warnings you mentioned in the cover letter?  You
might find cocinelle useful for that last task.

Regards,
Mike

> Currently if the value read is greater than the number of
> available parents clk_mux_get_parent return's signed error
> which will result in NULL pointer dereferencing in the
> calling functions.
> 
> Signed-off-by: Ambresh K <ambresh at ti.com>
> ---
>  drivers/clk/clk-mux.c        |    2 +-
>  drivers/clk/clk.c            |   12 +++++++++++-
>  include/linux/clk-provider.h |    4 ++--
>  3 files changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 25b1734..be0857e 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -29,7 +29,7 @@
>  
>  #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
>  
> -static u8 clk_mux_get_parent(struct clk_hw *hw)
> +static int clk_mux_get_parent(struct clk_hw *hw)
>  {
>         struct clk_mux *mux = to_clk_mux(hw);
>         int num_parents = __clk_get_num_parents(hw->clk);
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 934cfd1..c187321 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1281,7 +1281,7 @@ EXPORT_SYMBOL_GPL(clk_get_parent);
>  static struct clk *__clk_init_parent(struct clk *clk)
>  {
>         struct clk *ret = NULL;
> -       u8 index;
> +       int index;
>  
>         /* handle the trivial cases */
>  
> @@ -1309,6 +1309,11 @@ static struct clk *__clk_init_parent(struct clk *clk)
>          */
>  
>         index = clk->ops->get_parent(clk->hw);
> +       if (index < 0) {
> +               pr_err("%s: clk(%s) invalid parent clk_sel index(%d)\n",
> +                               __func__, clk->name, index);
> +               goto out;
> +       }
>  
>         if (!clk->parents)
>                 clk->parents =
> @@ -1632,6 +1637,11 @@ int __clk_init(struct device *dev, struct clk *clk)
>         hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
>                 if (orphan->ops->get_parent) {
>                         i = orphan->ops->get_parent(orphan->hw);
> +                       if (i < 0) {
> +                               pr_err("%s: orphan clk(%s) invalid parent\n",
> +                                               __func__, orphan->name);
> +                               continue;
> +                       }
>                         if (!strcmp(clk->name, orphan->parent_names[i]))
>                                 __clk_reparent(orphan, clk);
>                         continue;
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 1186098..96337a1 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -80,7 +80,7 @@ struct clk_hw;
>   *             supported by the clock.
>   *
>   * @get_parent:        Queries the hardware to determine the parent of a clock.  The
> - *             return value is a u8 which specifies the index corresponding to
> + *             return value which specifies the index corresponding to
>   *             the parent clock.  This index can be applied to either the
>   *             .parent_names or .parents arrays.  In short, this function
>   *             translates the parent value read from hardware into an array
> @@ -127,7 +127,7 @@ struct clk_ops {
>         long            (*round_rate)(struct clk_hw *hw, unsigned long,
>                                         unsigned long *);
>         int             (*set_parent)(struct clk_hw *hw, u8 index);
> -       u8              (*get_parent)(struct clk_hw *hw);
> +       int             (*get_parent)(struct clk_hw *hw);
>         int             (*set_rate)(struct clk_hw *hw, unsigned long,
>                                     unsigned long);
>         void            (*init)(struct clk_hw *hw);
> -- 
> 1.7.4.1


From shawn.guo at linaro.org  Wed May 29 03:26:05 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 15:26:05 +0800
Subject: [PATCH v4] tty: serial: add Freescale lpuart driver support
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CDEFB@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1369733161-19168-1-git-send-email-b35083@freescale.com>
 <20130529034913.GF370@S2101-09.ap.freescale.net>
 <B56CDBE15CE27145A4B77D2D24263E851CDEFB@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <20130529072603.GI370@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 06:57:43AM +0000, Lu Jingchang-B35083 wrote:
> [Lu Jingchang-B35083] 
>   For multiple dts uart nodes, each node will call .probe once. If the uart_register_driver is called from .probe without any conditioning check, it will then be called more than once, but the uart_register_deiver can only register the same uart driver once. So I think current arrangement will be more reasonable. Thanks!
> 

It shouldn't be too hard to add a check for that.  But if you like to
stay with the current one, okay, I'm fine.

Shawn



From maxime.ripard at free-electrons.com  Wed May 29 03:34:51 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 29 May 2013 09:34:51 +0200
Subject: [PATCHv3 0/6] Add I2C support for Allwinner SoCs
In-Reply-To: <2987322.J4qAl07e8R@flatron>
References: <1369648843-1640-1-git-send-email-maxime.ripard@free-electrons.com>
 <2987322.J4qAl07e8R@flatron>
Message-ID: <20130529073451.GA3293@lukather>

Hi Thomas,

On Mon, May 27, 2013 at 09:17:27PM +0200, Tomasz Figa wrote:
> All the patches look good to me.
> 
> Reviewed-by: Tomasz Figa <tomasz.figa at gmail.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From thomas.petazzoni at free-electrons.com  Wed May 29 03:42:36 2013
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Wed, 29 May 2013 09:42:36 +0200
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use
 DT for the PCIe interface
In-Reply-To: <20130528223817.GL31290@titan.lakedaemon.net>
References: <8738t6ycnm.fsf@natisbad.org> <20130529002053.4b8ceb86@skate>
 <20130528223817.GL31290@titan.lakedaemon.net>
Message-ID: <20130529094236.619bd698@skate>

Dear Jason Cooper,

On Tue, 28 May 2013 18:38:17 -0400, Jason Cooper wrote:

> > Could you check that you're running on top of the latest
> > jcooper/mvebu/pcie branch? Thanks!
> 
> Actually, you want jcooper/mvebu/pcie_kirkwood.  I split out the
> kirkwood driver so that if it causes a build breakage and gets dropped,
> mvebu/pcie can still go in.

There's not really a "kirkwood" driver for PCIe. The pcie-kirkwood
stuff is really all about adding the right Device Tree informations,
and switching from a legacy-style probing to a DT-style probing.

That said, I definitely agree with the idea of having that as a
separate branch.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From maxime.ripard at free-electrons.com  Wed May 29 03:50:44 2013
From: maxime.ripard at free-electrons.com (maxime.ripard at free-electrons.com)
Date: Wed, 29 May 2013 09:50:44 +0200
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
Message-ID: <20130529075044.GC3293@lukather>

Hi,

On Wed, May 29, 2013 at 07:11:30AM +0000, Chen Peter-B29397 wrote:
>  
> > Hello,
> > 
> > Am I right in assuming that the MXS USB on-the-go port does not currently
> > support the
> > device (gadget) functionality?
> > Anybody out there working on that?
> > 
> 
> As far as I know, Maxime Ripard may already let the chipidea durl-role function
> work ok at mx28. It may need my chipidea otg patch
> 
> https://github.com/hzpeterchen/linux-usb.git

Indeed, I've been using the patchset "Add tested id switch and vbus
connect detect support for Chipidea" from Peter for quite some time on
top of 3.9 and it works like a charm for the gadget mode on an MX28
platform.

BTW, Peter, I've seen that these patches are still not merged in 3.10,
is there a reason for that? do you plan on sending a version rebased on
top of 3.10 some time in the future? I tried to do the rebasing myself,
but the chipidea driver seems to have changed quite heavily, which makes
the process quite difficult when you don't know what you're doing :)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From mturquette at linaro.org  Wed May 29 03:51:26 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 00:51:26 -0700
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing
 is done
In-Reply-To: <519461BB.3010209@codeaurora.org>
References: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
 <519461BB.3010209@codeaurora.org>
Message-ID: <20130529075126.6058.58923@quantum>

Quoting Saravana Kannan (2013-05-15 21:34:03)
> On 05/09/2013 11:35 AM, Saravana Kannan wrote:
> > With deferred probing, late_initcall() is too soon to declare a clock as
> > unused. Wait for deferred probing to finish before declaring a clock as
> > unused. Since deferred probing is done in late_initcall(), do the unused
> > check to late_initcall_sync.
> >
> > Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> > ---
> >   drivers/clk/clk.c |    2 +-
> >   1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index fe4055f..5ecb64c 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -534,7 +534,7 @@ static int clk_disable_unused(void)
> >
> >       return 0;
> >   }
> > -late_initcall(clk_disable_unused);
> > +late_initcall_sync(clk_disable_unused);
> >
> >   /***    helper functions   ***/
> 
> Mike,
> 
> Thoughts? Picking it up? Removing the existing auto-disable code (I 
> think they are still useful)?
> 

Hi Saravana,

I've taken this into clk-next for testing.

Regards,
Mike

> -Saravana
> 
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation


From arnd at arndb.de  Wed May 29 03:56:00 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 09:56 +0200
Subject: [PATCH] SPI: Unify simple platform data for some controllers
In-Reply-To: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
Message-ID: <1743419.NY2Q01i8Iq@wuerfel>

On Wednesday 29 May 2013 10:42:22 Alexander Shiyan wrote:
> This patch unifies simple pdata for some SPI controllers where only
> array of GPIOs is used for define chipselects.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Wouldn't it be better to kill off the platform_data for these drivers
and pass the gpio number through spi->controller_data as the
spi_gpio driver does?

	Arnd


From arnd at arndb.de  Wed May 29 03:58:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 09:58:13 +0200
Subject: [RFC PATCHv4 1/6] arm: TI-Nspire platform code
In-Reply-To: <10704A21-6BEC-42DC-BB1E-88A0E87D288B@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305271715.02385.arnd@arndb.de>
 <10704A21-6BEC-42DC-BB1E-88A0E87D288B@gmail.com>
Message-ID: <1659233.o2ovIRIt66@wuerfel>

On Wednesday 29 May 2013 15:14:41 Daniel Tang wrote:
> 
> That's the idea for the long term.
> 
> For now though, I'll probably just let the bootloader enable 
> everything and work on a proper driver for power management later.

Ok, sounds good.

	Arnd


From laurent.pinchart at ideasonboard.com  Wed May 29 04:01:05 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 29 May 2013 10:01:05 +0200
Subject: [PATCH v4 02/21] sh-pfc: Add DT support
In-Reply-To: <CACRpkdZNv5AO48Bmquyr8mBQvgjBMCk3Ob8ngutSq8RV1HFT0w@mail.gmail.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369138482-5871-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <CACRpkdZNv5AO48Bmquyr8mBQvgjBMCk3Ob8ngutSq8RV1HFT0w@mail.gmail.com>
Message-ID: <1544149.k900vg9Sxe@avalon>

Hi Linus,

Thanks for the review.

On Friday 24 May 2013 10:52:42 Linus Walleij wrote:
> On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart wrote:
> > Support device instantiation through the device tree. The compatible
> > property is used to select the SoC pinmux information.
> > 
> > Set the gpio_chip device field to the PFC device to enable automatic
> > GPIO OF support.
> > 
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> 
> (...)
> 
> (Again I'm rather nervous about all the device tree binding reviewing being
> dropped in the lap of Linux subsystem maintainers and then expecting them
> to be good and OS-neutral... Not your fault though.)

I agree with you. I'm open to review from other OS vendors :-)

> > +Pin Configuration Node Properties:
> > +
> > +- renesas,pins : An array of strings, each string containing the name of
> > +  a pin.
> > +- renesas,groups : An array of strings, each string containing the name
> > +  of a pin group.
> > +
> > +- renesas,function: A string containing the name of the function to mux
> > +  to the pin group(s) specified by the renesas,groups property
> > +
> > +  Valid values for pin, group and function names can be found in the
> > +  group and function arrays of the PFC data file corresponding to the
> > +  SoC (drivers/pinctrl/sh-pfc/pfc-*.c)
> > +
> > +- renesas,pull-up: An integer representing the pull-up strength to be
> > +  applied to all pins specified by the renesas,pins and renesas-groups
> > +  properties. 0 disables the pull-up, 1 enables it. Other values should
> > + not be used.
>
> Then just use a boolean.

I meant that other values should not be used for now. Future revisions of the 
GPIO core might allow controlling the pull-up strength, hence the integer 
property. Same for the pull-down property. This is especially true if we 
device to implement generic pinconf bindings.

> > +- renesas,pull-down: An integer representing the pull-down strength to be
> > +  applied to all pins specified by the renesas,pins and renesas-groups
> > +  properties. 0 disables the pull-down, 1 enables it. Other values should
> > +  not be used.
> 
> Just use a boolean oneliner then.
> 
> But I prefer that you define something really generic in
> Documentation/devicetree/bindings/pinconf.txt for anyone using
> generic pin config, then reference that.
> 
> This way we can have a more general config binding for any system
> using generic pin config, mapping to the configs we have in
> <linux/pinctrl/pinconf-generic.h>
> 
> The upside is that we could move the pinconf generic parsing code
> to drivers/pinctrl/pinconf-generic.c and thus avoid code duplication.
> 
> We have so far not tried much to standardize pinctrl bindings, but
> this would be a good opportunity.

I agree. I'll reply to the "[PATCH v2 6/9] pinctrl-tz1090: add TZ1090 pinctrl 
driver" mail thread to further discuss the pinconf generic bindings.

> > +On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO
> > +controller node.
> > +
> > +Required Properties:
> > +
> > +  - gpio-controller: Marks the device node as a gpio controller.
> > +
> > +  - #gpio-cells: Should be 2. The first cell is the pin number and the
> > +    second cell is used to specify optional parameters as bit flags.
> > +    Only the GPIO active low flag (bit 0) is currently supported.
> 
> I suggest these properties shall be defined in an include file using that
> new include hierarchy, since you're using pinconf generic.
> 
> include/dt-bindings/gpio/gpio.h
> Referenced by <dt-bindings/gpio/gpio.h> in the .dts[i] files.

Agreed, I'll fix that.

> In Linux-next you find how tegra machines and the imx6sl DTs have
> started to use this facility for symbolic names.
> 
> And for that you should reference
> <dt-bindings/gpio/gpio.h>
> 
> Use the symbolic names GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW
> here.
> 
> (...)
> 
> > +Example 2: A GPIO LED node that references a GPIO
> > +
> > +       leds {
> > +               compatible = "gpio-leds";
> > +               led1 {
> > +                       gpios = <&pfc 20 1>; /* Active low */
> 
> #include <dt-bindings/gpio/gpio.h>
> gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
> 
> (...)
> 
> > +Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin
> > control maps +           for the MMCIF and SCIFA4 devices
> > +
> > +       &pfc {
> > +               pinctrl-0 = <&scifa4_pins>;
> > +               pinctrl-names = "default";
> > +
> > +               mmcif_pins: mmcif {
> > +                       mux {
> > +                               renesas,groups = "mmc0_data8_0",
> > "mmc0_ctrl_0"; +                               renesas,function = "mmc0";
> > +                       };
> > +                       cfg {
> > +                               renesas,groups = "mmc0_data8_0";
> > +                               renesas,pins = "PORT279";
> > +                               renesas,pull-up = <1>;
> 
> Just
> renesas,pull-up;
> 
> Or go for the generic pinconf binding I'm suggesting.
> Then I guess it'd be something like:
> 
> pinconf-bias-pull-up;
> 
> (Quite readable.)
> 
> (...)
> 
> > +++ b/drivers/pinctrl/sh-pfc/pinctrl.c
> > +static const struct sh_pfc_config_param sh_pfc_config_params[] = {
> > +       { "renesas,pull-up", PIN_CONFIG_BIAS_PULL_UP },
> > +       { "renesas,pull-down", PIN_CONFIG_BIAS_PULL_DOWN },
> > +};
> 
> So these should be checked as booleans instead:
>
> > +       for (i = 0; i < ARRAY_SIZE(sh_pfc_config_params); ++i) {
> > +               const struct sh_pfc_config_param *param =
> > +                       &sh_pfc_config_params[i];
> > +               unsigned long config;
> > +               u32 val;
> > +
> > +               ret = of_property_read_u32(np, param->name, &val);
> 
> of_property_read_bool()
> 
> Though I much rather like this code added as helper lib in pinconf-
> generic.c. Use drivers/pinctrl/pinconf.h for API.

-- 
Regards,

Laurent Pinchart


From laurent.pinchart at ideasonboard.com  Wed May 29 04:01:43 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Wed, 29 May 2013 10:01:43 +0200
Subject: [PATCH v4 15/21] ARM: shmobile: armadillo-reference: Move st1232
 reset GPIO to DT
In-Reply-To: <CACRpkdYUQjtmzFzQBES-bcjjT5iTTXifa2BQSusBzMdTCRtyiA@mail.gmail.com>
References: <1369138482-5871-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369138482-5871-16-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <CACRpkdYUQjtmzFzQBES-bcjjT5iTTXifa2BQSusBzMdTCRtyiA@mail.gmail.com>
Message-ID: <7726129.eAP65oL724@avalon>

Hi Linus,

Thanks for the review.

On Friday 24 May 2013 10:59:50 Linus Walleij wrote:
> On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart wrote:
> > Reference the st1232 reset GPIO from the device tree and remove it from
> > board code.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> > 
> > +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
> > @@ -43,6 +43,7 @@
> > 
> >                 interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
> >                 pinctrl-0 = <&st1232_pins>;
> >                 pinctrl-names = "default";
> > 
> > +               gpios = <&pfc 166 1>;
> 
> Just as a random example this becomes:
> 
> gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
> 
> Which is WAAAY more readable.

As stated in my reply to your other e-mail, I'll switch to symbolic constants.

> > +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
> > 
> > @@ -158,7 +158,6 @@ clock_error:
> >   */
> >  static void __init eva_init(void)
> >  {
> > -
> >         r8a7740_clock_init(MD_CK0 | MD_CK2);
> >         eva_clock_init();
> > 
> > @@ -171,12 +170,6 @@ static void __init eva_init(void)
> > 
> >         r8a7740_add_standard_devices_dt();
> > 
> > -       /*
> > -        * Touchscreen
> > -        * TODO: Move reset GPIO over to .dts when we can reference it
> > -        */
> > -       gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
> > -
> 
> Not really my business but I guess the driver is already augmented to pick
> its GPIO from the device tree in this case?

Yes it is.

> And are you willingly breaking non-DT boots or something?

The armadillo-reference board doesn't support non-DT boot.

-- 
Regards,

Laurent Pinchart


From afzal at ti.com  Wed May 29 04:06:39 2013
From: afzal at ti.com (Mohammed, Afzal)
Date: Wed, 29 May 2013 08:06:39 +0000
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <51A52A16.1040204@wwwdotorg.org>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>

Hi Jon,

On Wed, May 29, 2013 at 03:35:10, Stephen Warren wrote:
> On 05/28/2013 03:25 PM, Jon Hunter wrote:

> >>  			ti,am335x-timer	(applicable to AM335x devices)
> >>  			ti,am335x-timer-1ms (applicable to AM335x devices)
> >> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
> >> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one

> > If you are adding more compatibility strings, then this implies that the
> > AM43x timers are not 100% compatible with any other device listed (such
> > as am335x or any omap device). That's fine but you should state that in
> > the changelog. If the AM43x timer registers are 100% compatible with
> > existing devices you should not add these.
> 
> I'm not sure that's true; .dts files should always include a compatible
> value that describes the most specific model of the HW, plus any
> baseline compatible value that the HW is compatible with. This allows
> any required quirks/fixes/... to be applied for the specific HW model
> later even if nobody knows right now they'll be needed. Hence, defining
> new compatible values doesn't necessarily mean incompatible HW.

Stephen took words out of my finger ;)
 
Some explanations,

1. first compatible should be exact device [A], followed by compatible
model (if one)
2. Minor effort in getting DT right the first time may help prevent
difficult effort later modifying it (if a necessity comes), considering
the fact that DT sources has  to move out of Kernel at some point of
time. And DT is not supposed to be modified, which may cause difficulty
for the users (I had been a minor victim of this during rebase).

As we both were in GPMC land earlier, an example,

If my memory is right, GPMC IP in am335x is rev 6, and IP has 8 chip
select, but one is not pinned out. Now assume that same IP is integrated
in another SoC (probably OMAP4 has rev 6). Here if we use same compatible
for both, driver cannot handle it properly (w/o knowledge about platform).
But if exact compatible is mentioned, without modifying DT (which should
be considered as a firmware) just by modifying Kernel, deciding based on
compatible would help achieve what is required.

Regards
Afzal

[A] http://devicetree.org/Device_Tree_Usage#Understanding_the_compatible_Property

From afzal at ti.com  Wed May 29 04:08:06 2013
From: afzal at ti.com (Mohammed, Afzal)
Date: Wed, 29 May 2013 08:08:06 +0000
Subject: [PATCH v2 12/14] Documentation: dt: binding: omap: am43x counter
In-Reply-To: <51A520ED.9070106@gmail.com>
References: <cover.1369658705.git.afzal@ti.com>
 <755964dc45ae4f023540c05e5739fca87d0ea70b.1369658705.git.afzal@ti.com>
 <51A520ED.9070106@gmail.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93EAFB056@DBDE04.ent.ti.com>

Hi Jon,

On Wed, May 29, 2013 at 02:56:05, Jon Hunter wrote:

> Changelog should state why this is needed.

Please see my reply on 11/14 thread.

Regards
Afzal

From B29397 at freescale.com  Wed May 29 04:07:55 2013
From: B29397 at freescale.com (Chen Peter-B29397)
Date: Wed, 29 May 2013 08:07:55 +0000
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <20130529075044.GC3293@lukather>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529075044.GC3293@lukather>
Message-ID: <F281D0F91ED19E4D8E63A7504E8A649803E8A4D0@039-SN2MPN1-021.039d.mgd.msft.net>


 
> 
> Indeed, I've been using the patchset "Add tested id switch and vbus
> connect detect support for Chipidea" from Peter for quite some time on
> top of 3.9 and it works like a charm for the gadget mode on an MX28
> platform.
> 
> BTW, Peter, I've seen that these patches are still not merged in 3.10,
> is there a reason for that? do you plan on sending a version rebased on
> top of 3.10 some time in the future? I tried to do the rebasing myself,
> but the chipidea driver seems to have changed quite heavily, which makes
> the process quite difficult when you don't know what you're doing :)
> 

I can spend few bandwidth on upstream work recently, I may have more
bandwidth after June 15th. 

Currently, we still have no conclusion for chipidea core driver's coming work,
like Device tree support, how to identify if the controller is OTG supported.

Best regards,
Peter




From jan.glauber at gmail.com  Wed May 29 04:10:07 2013
From: jan.glauber at gmail.com (Jan Glauber)
Date: Wed, 29 May 2013 10:10:07 +0200
Subject: ARM hibernation / suspend-to-disk
Message-ID: <20130529081005.GA25561@hal>

Hi list,

what's the status of suspend-to-disk on ARM? The most recent discussion I
found is:
http://lists.linuxfoundation.org/pipermail/linux-pm/2012-November/034997.html

with no replies at all. Is anyone still working on that? Anyone got it running?

I tried the patch above (on top of LTS 3.4) and got stuck forever, the last
thing on the console was:

root at omap5:/sys/power# echo disk > state
[ 2015.641540] PM: Syncing filesystems ... done.
[ 2015.666870] PM: Preallocating image memory... done (allocated 16957 pages)
[ 2016.062011] PM: Allocated 67828 kbytes in 0.38 seconds (178.49 MB/s)

Any hint how to debug that?

thanks,
Jan


From alexandre.belloni at free-electrons.com  Wed May 29 04:21:26 2013
From: alexandre.belloni at free-electrons.com (Alexandre Belloni)
Date: Wed, 29 May 2013 10:21:26 +0200
Subject: [PATCHv2 1/3] net: phy: prevent linking breakage
In-Reply-To: <20130528.130920.1604291112518863799.davem@davemloft.net>
References: <1369741403-25315-1-git-send-email-alexandre.belloni@free-electrons.com>
 <1369741403-25315-2-git-send-email-alexandre.belloni@free-electrons.com>
 <20130528.130920.1604291112518863799.davem@davemloft.net>
Message-ID: <51A5BA86.3070609@free-electrons.com>

Hi,

On 28/05/2013 22:09, David Miller wrote:
>
> This is the wrong way to go about this.
>
> If the arch code absolutely requires CONFIG_PHYLIB=y then express that
> dependency in the arch Kconfig.  The arch code in question should not
> be compiled at all if CONFIG_PHYLIB has an incompatible setting.
But that is making it impossible to compile a kernel without any network
stack for those platforms or we are going back to either enclosing the
calls to phy_register_fixup{,_for_uid,_for_id} with #ifdef CONFIG_PHYLIB
or if(IS_BUILTIN(CONFIG_PHYLIB)). And as you can see, it is quite error
prone and is done only done for 2 platforms on a total of 6. I believe
fixing that in phy.h is more foolproof.

Regards,

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com



From tglx at linutronix.de  Wed May 29 04:23:18 2013
From: tglx at linutronix.de (Thomas Gleixner)
Date: Wed, 29 May 2013 10:23:18 +0200 (CEST)
Subject: [patch 7/8] genirq: generic chip: Add linear irq domain
 support
In-Reply-To: <20130529022249.DE5ED3E14F1@localhost>
References: <20130503212258.385818955@linutronix.de>
 <20130506142348.321859745@linutronix.de>
 <20130506142539.450634298@linutronix.de>
 <20130529022249.DE5ED3E14F1@localhost>
Message-ID: <alpine.LFD.2.02.1305291019450.2995@ionos>

On Wed, 29 May 2013, Grant Likely wrote:
> > --- linux-2.6.orig/include/linux/irq.h
> > +++ linux-2.6/include/linux/irq.h
> > @@ -678,6 +678,8 @@ struct irq_chip_type {
> >   * @wake_active:	Interrupt is marked as an wakeup from suspend source
> >   * @num_ct:		Number of available irq_chip_type instances (usually 1)
> >   * @private:		Private data for non generic chip callbacks
> > + * @installed:		bitfield to denote installed interrupts
> > + * @domain:		irq domain pointer
> >   * @list:		List head for keeping track of instances
> >   * @chip_types:		Array of interrupt irq_chip_types
> >   *
> > @@ -699,6 +701,8 @@ struct irq_chip_generic {
> >  	u32			wake_active;
> >  	unsigned int		num_ct;
> >  	void			*private;
> > +	unsigned long		installed;
> 
> This is probably something that the irqdomain should be keeping track of
> internally, but that's an issue for a separate patch series.

Ok. I just need access to that information, so I can figure out if
it's the first irq of the chip which gets mapped. I need this for
initializing the mask cache.
 
> [...]
> > +struct irq_domain_ops irq_generic_chip_ops = {
> > +	.map = irq_map_generic_chip,
> > +	.xlate = irq_domain_xlate_onecell,
> 
> As discussed on IRC, should use onetwocell here for greater
> compatibility with existing bindings.

Changed that.

Thanks,

	tglx


From viresh.kumar at linaro.org  Wed May 29 04:25:26 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Wed, 29 May 2013 13:55:26 +0530
Subject: [linux-pm] ARM hibernation / suspend-to-disk
In-Reply-To: <20130529081005.GA25561@hal>
References: <20130529081005.GA25561@hal>
Message-ID: <CAKohpomgf4QZ=71JNYztBZTjcqqZw5MK69dR==Thay7yz5q1jg@mail.gmail.com>

On 29 May 2013 13:40, Jan Glauber <jan.glauber at gmail.com> wrote:
> what's the status of suspend-to-disk on ARM? The most recent discussion I
> found is:
> http://lists.linuxfoundation.org/pipermail/linux-pm/2012-November/034997.html
>
> with no replies at all. Is anyone still working on that? Anyone got it running?
>
> I tried the patch above (on top of LTS 3.4) and got stuck forever, the last
> thing on the console was:
>
> root at omap5:/sys/power# echo disk > state
> [ 2015.641540] PM: Syncing filesystems ... done.
> [ 2015.666870] PM: Preallocating image memory... done (allocated 16957 pages)
> [ 2016.062011] PM: Allocated 67828 kbytes in 0.38 seconds (178.49 MB/s)
>
> Any hint how to debug that?

I know it is still broken and I had discussion with Kevin in past
regarding that. See below.

On 13 March 2013 22:57, Kevin Hilman <khilman at linaro.org> wrote:
> Viresh Kumar <viresh.kumar at linaro.org> writes:
>
>> Hi Guys,
>>
>> As discussed during connect about "HIBERNATION support for ARM platforms",
>> this is my last mail on this, almost a year back, where i tried my best to get
>> relevant answer from Amit.
>>
>> Probably he missed all my mails then, but this might be a good starting point
>> for this discussion as i did some testing on hibernation earlier.
>>
>> https://lkml.org/lkml/2012/2/6/8
>
> I think the reason that ARM sub-arches are not setting things up is
> because ARM has never supported hibernation in mainline.
>
> The most recent patch to add basic support[1] references the various
> discussions on what is needed and still missing.
>
> Kevin
>
> [1] http://marc.info/?l=linux-omap&m=135292458209355&w=2


From b-cousson at ti.com  Wed May 29 04:39:18 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 10:39:18 +0200
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
 <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>
Message-ID: <51A5BEB6.6070809@ti.com>

Hi Afzal,

On 05/29/2013 10:06 AM, Mohammed, Afzal wrote:
> Hi Jon,
> 
> On Wed, May 29, 2013 at 03:35:10, Stephen Warren wrote:
>> On 05/28/2013 03:25 PM, Jon Hunter wrote:
> 
>>>>  			ti,am335x-timer	(applicable to AM335x devices)
>>>>  			ti,am335x-timer-1ms (applicable to AM335x devices)
>>>> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
>>>> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
> 
>>> If you are adding more compatibility strings, then this implies that the
>>> AM43x timers are not 100% compatible with any other device listed (such
>>> as am335x or any omap device). That's fine but you should state that in
>>> the changelog. If the AM43x timer registers are 100% compatible with
>>> existing devices you should not add these.
>>
>> I'm not sure that's true; .dts files should always include a compatible
>> value that describes the most specific model of the HW, plus any
>> baseline compatible value that the HW is compatible with. This allows
>> any required quirks/fixes/... to be applied for the specific HW model
>> later even if nobody knows right now they'll be needed. Hence, defining
>> new compatible values doesn't necessarily mean incompatible HW.
> 
> Stephen took words out of my finger ;)
>  
> Some explanations,I don;t 
> 
> 1. first compatible should be exact device [A], followed by compatible
> model (if one)
> 2. Minor effort in getting DT right the first time may help prevent
> difficult effort later modifying it (if a necessity comes), considering
> the fact that DT sources has  to move out of Kernel at some point of
> time. And DT is not supposed to be modified, which may cause difficulty
> for the users (I had been a minor victim of this during rebase).
> 
> As we both were in GPMC land earlier, an example,
> 
> If my memory is right, GPMC IP in am335x is rev 6, and IP has 8 chip
> select, but one is not pinned out. Now assume that same IP is integrated
> in another SoC (probably OMAP4 has rev 6). Here if we use same compatible
> for both, driver cannot handle it properly (w/o knowledge about platform).
> But if exact compatible is mentioned, without modifying DT (which should
> be considered as a firmware) just by modifying Kernel, deciding based on
> compatible would help achieve what is required.

That's true for the DTS itself, but here your are changing the binding
documentation which is supposed to reflect the driver "interface" in the
Device Tree model description.

Since the driver does not support any new compatible string, you should
not update the binding.

The driver and the binding will have to be changed the day you will have
to update the driver to handle a bug / feature specific to that revision
(ti,am4372-timer).

Since this series does not seems to update the driver, you should not
update the bindings.

Regards,
Benoit




From grygorii.strashko at ti.com  Wed May 29 04:36:29 2013
From: grygorii.strashko at ti.com (Grygorii Strashko)
Date: Wed, 29 May 2013 11:36:29 +0300
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ
 pin and msecure line
In-Reply-To: <87a9nfc5uc.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <87ppwgdnxu.fsf@linaro.org>
 <CAGo_u6ruWQwSB8Z0BRLda7HunTyr9mGpx4eMSGdQZkCxKxbHbg@mail.gmail.com>
 <87a9nfc5uc.fsf@linaro.org>
Message-ID: <51A5BE0D.7030609@ti.com>

On 05/28/2013 09:33 PM, Kevin Hilman wrote:
> Nishanth Menon <nm at ti.com> writes:
>
>> On Fri, May 24, 2013 at 5:15 PM, Kevin Hilman <khilman at linaro.org> wrote:
>>> Kevin Hilman <khilman at linaro.org> writes:
>>>
>>>> Nishanth Menon <nm at ti.com> writes:
>>> [...]
>>>
>>>>> Actually 2 things:
>>>>>
>>>>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>>>>> have been used instead of 0x14 which is correct for 4430?
>>>> I see, thanks.  I'll double check the TRMs.
>>>>
>>>>> b) yes, I understand,  the current settings we did worked, but the
>>>>> mode(0) we are setting to is real weird - we are setting it up for
>>>>> clk0 out - I cant even think why it is even working in the first place
>>>>> :( - is it because we are pumping out sysclkout and as a result we are
>>>>> lucky that msecure is being sampled at the right point by twl6030
>>>>> allowing rtc access? either way, IMHO, the configuration is wrong.
>>>> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
>>>> for legacy mode, I just duplicated the settings u-boot was using.  Guess
>>>> it's a fluke that it works.
>>> Actually, for legacy mode, it's set correctly in mode 2.  This line:
>>>
>>>          omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
>>>
>>> does the right thing based on the signal name.    But for DT boot, I
>>> defintely screwed it up by setting it to mode (and putting it in the
>>> wrong padconf section.)
>>>
>>> Also, are you *really* sure about the offset difference between 4430 and
>>> 4460 here?  I don't have access to NDA docs anymore, so I cannot double
>>> check this.
>>>
>>> What I do know is that the legacy code is using 0x54 for both, and if I
>>> simply comment out that 'sys_drm_msecure' line above, RTC wake stops
>>> working (legacy boot) on both 4430 and 4460, so that seems like pretty
>>> stront evidence that it's the same offset on both.
>> Schematics are public for PandaBoard ES and PandaBoard - as you can
>> see from that the registers connected are definitely different.
> What I see from both schematics is that SYS_DRM_MSECURE is available on
> a few different pads, but on both 4430 and 4460, one of the places is in
> mode 2 of FREF_CLK0_OUT, which is at offset 0x54 on both SoCs.
>
> Based on that reading, and the fact that not correctly muxing that pad
> to mode 2 on *both* 4430 and 4460 makes the RTC work, I'm rather
> convinced that the offset should be the same for 4430 and 4460.
>
> What am I missing?
Hi Kevin,

I've rechecked it too.

According to:
Panda ES: 
http://pandaboard.org/sites/default/files/board_reference/ES/750-2170-002-sch_revb.pdf
Panda: 
http://pandaboard.org/sites/default/files/board_reference/pandaboard-a/panda-a-schematic.pdf

AD2 (FREF_CLK0_OUT) is used for on both boards as H_SYS_DRM_MSEC - so, 
valid offset is 0x14
CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ lowest 16 bit

FYI: in Android K3.0 and K3.4 this pin configured to "gpio_wk6" as following
     omap_mux_init_signal("fref_clk0_out.gpio_wk6", OMAP_PIN_OUTPUT);
     gpio_request(6, "msecure");
     gpio_direction_output(6, 1);

http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=262669aebf4af4044a25e8292f0e27986e18445a


Regards,
Grygorii

>
> Kevin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From b-cousson at ti.com  Wed May 29 04:46:32 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 10:46:32 +0200
Subject: [PATCH v3 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <51A46DB0.5020508@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
 <51A46DB0.5020508@epfl.ch>
Message-ID: <51A5C068.9040308@ti.com>

Salut Florian,

On 05/28/2013 10:41 AM, Florian Vaussard wrote:
> 
> On 05/27/2013 04:52 PM, Florian Vaussard wrote:
>> Hello,
>>
>> Following a similar proposal by Stephen Warren for tegra [1], this series
>> makes use of the C preprocessor when compiling OMAP DT files, and
>> accomplishes some improvements to improve overall readability.

Thanks for that nice cleanup.

> I realized that I should also address am* devices. I will wait for comments
> on this version, then post a v4. Sorry for the noise.

That's up to you, but I can anyway already pulled that series. That AM*
patches can go later.

Thanks,
Benoit



From richard.weinberger at gmail.com  Wed May 29 04:46:42 2013
From: richard.weinberger at gmail.com (richard -rw- weinberger)
Date: Wed, 29 May 2013 10:46:42 +0200
Subject: A bug about system call on ARM
In-Reply-To: <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
Message-ID: <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>

On Wed, May 29, 2013 at 10:24 AM, Wang, Yalin <Yalin.Wang at sonymobile.com> wrote:
> Hi
>
> I have download the latest linux kernel code  3.9.4
> And Compare with  3.4.0 kernel .
>
> It seems there is no change for this part ,
> So it will still happen .
> Does anyone know who is responsible for  arm arch part kernel code ?

See MAINTAINERS file.
CC'ing linux-arm-kernel at lists.infradead.org

>
> Thanks
>
>
> -----Original Message-----
> From: Wang, Yalin
> Sent: Wednesday, May 29, 2013 3:38 PM
> To: 'richard -rw- weinberger'
> Cc: linux-arch at vger.kernel.org; linux-kernel at vger.kernel.org
> Subject: RE: A bug about system call on ARM
>
> Hi  Richard,
>
> Thanks for your reply ,
> I will make a check for this .
>
>
> -----Original Message-----
> From: richard -rw- weinberger [mailto:richard.weinberger at gmail.com]
> Sent: Wednesday, May 29, 2013 3:35 PM
> To: Wang, Yalin
> Cc: linux-arch at vger.kernel.org; linux-kernel at vger.kernel.org
> Subject: Re: A bug about system call on ARM
>
> Hi!
>
> On Wed, May 29, 2013 at 8:52 AM, Wang, Yalin <Yalin.Wang at sonymobile.com> wrote:
>> Hi  all,
>>
>> I am a new comer to this mailing list , I am happy to join this
>> community .
>>
>> I have a bug reported from our android phones which is caused by  the system call .
>> It seems like kernel bugs from my view .
>
> Is this a unmodified Linux kernel from kernel.org? In other works, no (half broken) board support package from your hardware vendor?
> Did you try a more recent kernel? (At least 3.4.47).
> Maybe your problem is already known and fixed...
>
>> Crash in  file  arch\arm\kernel\ entry-common.S
>>
>> /***************************************************************/
>>
>> ENTRY(vector_swi)
>>         sub     sp, sp, #S_FRAME_SIZE
>>         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
>>  ARM(   add     r8, sp, #S_PC           )
>>  ARM(   stmdb   r8, {sp, lr}^           )       @ Calling sp, lr
>>  THUMB( mov     r8, sp                  )
>>  THUMB( store_user_sp_lr r8, r10, S_SP  )       @ calling sp, lr
>>         mrs     r8, spsr                        @ called from non-FIQ mode, so ok.
>>         str     lr, [sp, #S_PC]                 @ Save calling PC
>>         str     r8, [sp, #S_PSR]                @ Save CPSR
>>         str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
>>         zero_fp
>>
>>         /*
>>          * Get the system call number.
>>          */
>>
>> #if defined(CONFIG_OABI_COMPAT)
>>
>>         /*
>>          * If we have CONFIG_OABI_COMPAT then we need to look at the swi
>>          * value to determine if it is an EABI or an old ABI call.
>>          */
>> #ifdef CONFIG_ARM_THUMB
>>         tst     r8, #PSR_T_BIT
>>         movne   r10, #0                         @ no thumb OABI emulation
>>         ldreq   r10, [lr, #-4]                  @ get SWI instruction          // crash at this instruction, when get SWI instruction
>> #else
>>         ldr     r10, [lr, #-4]                  @ get SWI instruction
>>   A710( and     ip, r10, #0x0f000000            @ check for SWI         )
>>   A710( teq     ip, #0x0f000000                                         )
>>   A710( bne     .Larm710bug                                             )
>> #endif
>> #ifdef CONFIG_CPU_ENDIAN_BE8
>>         rev     r10, r10                        @ little endian instruction
>> #endif
>>
>> /*********************************************************************
>> ******************************/
>>
>> Then reason why it will crash when get SWI instruction is maybe This
>> page is clear to aged by kernel, But this MMU fault happpened in
>> kernel, So the kernel do_page_fault function will not clear this page
>> to young, So that  will crash .
>>
>> It should poll this page to make it present or the fault should be
>> handled by fixup section , Anyway, this place should not crash by kernel .
>>
>> The kernel version I used  is  3.4.0
>> I have add the kernel log and the call stack recovered  by trace32
>> tools Pls have a look at it .
>>
>>
>> Thanks .
>>
>>
>>
>> Sony Mobile Communications
>> Tel: +86 10 5966 9819
>> Phone: 18610323092
>> Address: No.16 Guangshun South Street, Chaoyang, Beijing, P.R.C.
>>
>> sonymobile.com
>>
>>
>>
>
>
>
> --
> Thanks,
> //richard
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/



--
Thanks,
//richard


From shc_work at mail.ru  Wed May 29 04:49:13 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Wed, 29 May 2013 12:49:13 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSF0gU1BJOiBVbmlmeSBzaW1wbGUgcGxhdGZvcm0gZGF0YSBm?=
 =?UTF-8?B?b3Igc29tZSBjb250cm9sbGVycw==?=
In-Reply-To: <1743419.NY2Q01i8Iq@wuerfel>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <1743419.NY2Q01i8Iq@wuerfel>
Message-ID: <1369817353.993218858@f175.mail.ru>

> On Wednesday 29 May 2013 10:42:22 Alexander Shiyan wrote:
> > This patch unifies simple pdata for some SPI controllers where only
> > array of GPIOs is used for define chipselects.
> > 
> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> 
> Wouldn't it be better to kill off the platform_data for these drivers
> and pass the gpio number through spi->controller_data as the
> spi_gpio driver does?

Interesting way. Just one question remains, for using not-dt variant,
how  we should specify num_chipselect parameter for master?
I see only way for specify maximum constant in the driver.

---

From tushar.behera at linaro.org  Wed May 29 04:50:53 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 May 2013 14:20:53 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
Message-ID: <51A5C16D.20408@linaro.org>

On 05/29/2013 11:01 AM, Olof Johansson wrote:
> On Tue, May 28, 2013 at 8:59 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
> 
>> The patches are at [1].
> 
> FWIW, a cgit/gitweb link is easier to follow when you're reading an
> email. Anyway, found the patches.
> 
>> There are a total of 6 patches on top of
>> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
>> (c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
>> (e, f) are required to reset the hub during EHCI initialization.
> 
> Huh, I thought you said that (c) wasn't needed when I posted the
> defconfig update. It'd be nice to see the code fixed to handle this
> case instead of Linaro carrying a patch like this though. I.e. make it
> able to deselect the uart, or make it tied to DEBUG_LL like on other
> platforms instead of having a separate config for this.
> 

It would be good to free up the dependency on the correct UART port for
the board to boot. Without that, there would always be boards that don't
boot with default mainline defconfig file even though all other
components are in place.

>> a. ARM: exynos: defconfig update
>> b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
>> c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
>> d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
>> e. usb: ehci-s5p: add the HSIC port initialization
>> f. ARM: dts: Add USB gpio entries for Arndale board
>>
>> I am not sure whether such kind of board-specific patches (e, f) are
>> appreciated in the drivers. But that is all we need to get USB and
>> Ethernet to work on v3.10-rc3 kernel.
> 
> I've come across a similar situation with wifi reset sequence on the
> chromebook. On the product kernel we added some code to the board file
> to deal with it, but if we keep doing that things will grow out of
> hand.
> 
> I don't know if it'll be unpopular, but I think it's time to start a
> drivers/platform/arm for these kind of things, and have those drivers
> probe on the system compatible value, similar to how x86 does it (with
> DMI tables). At least that's my plan for approaching the wifi
> reset/power-on sequence on the Chromebook. I hope to have patches in
> not all that long...
> 
> Likewise, the hub reset/enable code doesn't have to go with the USB
> driver, right? I.e. if you cycle reset/enable on the hub after the
> host and phy is configured, you'll still have a working setup?
> 

Right, hub reset/enable code need not be tied up with USB driver. As per
your suggestion regarding drivers/platform/arm, I implemented an Arndale
specific driver [2] in drivers/platform/arm and verified USB and
ethernet to be working.

[2]
https://git.linaro.org/gitweb?p=landing-teams/working/samsung/kernel.git;a=shortlog;h=refs/heads/upstream/arndale-usb-2

> 
> -Olof
> 


-- 
Tushar Behera


From b-cousson at ti.com  Wed May 29 04:53:07 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 10:53:07 +0200
Subject: [PATCH v2 14/14] ARM: dts: AM43x: initial support
In-Reply-To: <3790fa57fc4c69da12224fbcec17cd07c59771a0.1369658705.git.afzal@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <3790fa57fc4c69da12224fbcec17cd07c59771a0.1369658705.git.afzal@ti.com>
Message-ID: <51A5C1F3.2070605@ti.com>

+ Florian

Hi Afzal,

On 05/27/2013 04:37 PM, Afzal Mohammed wrote:
> DT source (minimal) for AM4372 SoC to represent AM43x SoC's. Those
> represented here are the minimal DT nodes necessary to get kernel
> booting.
> 
> In DT nodes, "ti,hwmod" property has not been added, this would be
> added along with PRCM support for AM43x.
> 
> Signed-off-by: Ankur Kishore <a-kishore at ti.com>
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
> 
> v2: Add gptimer 1ms, timer2, synctimer and remove twd local timer
> 
>  arch/arm/boot/dts/am4372.dtsi | 66 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 arch/arm/boot/dts/am4372.dtsi
> 
> diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
> new file mode 100644
> index 0000000..1d58298
> --- /dev/null
> +++ b/arch/arm/boot/dts/am4372.dtsi
> @@ -0,0 +1,66 @@
> +/*
> + * Device Tree Source for AM4372 SoC
> + *
> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2.  This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +/include/ "skeleton.dtsi"

You can now use the C preprocessor statement instead of this one.
Florian already started doing the change [1].

Beside that detail, that patch looks good to me.
I'll pull it separately of the series.

Regards,
Benoit

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/98320

> +
> +/ {
> +	compatible = "ti,am4372", "ti,am43";
> +	interrupt-parent = <&gic>;
> +
> +
> +	aliases {
> +		serial0 = &uart1;
> +	};
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,cortex-a9";
> +		};
> +	};
> +
> +	gic: interrupt-controller at 48241000 {
> +		compatible = "arm,cortex-a9-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0x48241000 0x1000>,
> +		      <0x48240100 0x0100>;
> +	};
> +
> +	ocp {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		uart1: serial at 44e09000 {
> +			compatible = "ti,am4372-uart","ti,omap2-uart";
> +			reg = <0x44e09000 0x2000>;
> +			interrupts = <0 72 0x4>;
> +		};
> +
> +		timer1: timer at 44e31000 {
> +			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
> +			reg = <0x44e31000 0x400>;
> +			interrupts = <0 67 0x4>;
> +			ti,timer-alwon;
> +		};
> +
> +		timer2: timer at 48040000  {
> +			compatible = "ti,am4372-timer","ti,am335x-timer";
> +			reg = <0x48040000  0x400>;
> +			interrupts = <0 68 0x4>;
> +		};
> +
> +		counter32k: counter at 44e86000 {
> +			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
> +			reg = <0x44e86000 0x40>;
> +		};
> +	};
> +};
> 



From florian.vaussard at epfl.ch  Wed May 29 04:53:18 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 29 May 2013 10:53:18 +0200
Subject: [PATCH v3 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <51A5C068.9040308@ti.com>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
 <51A46DB0.5020508@epfl.ch> <51A5C068.9040308@ti.com>
Message-ID: <51A5C1FE.6020404@epfl.ch>

Hello Benoit,

On 05/29/2013 10:46 AM, Benoit Cousson wrote:
> Salut Florian,
>
> On 05/28/2013 10:41 AM, Florian Vaussard wrote:
>>
>> On 05/27/2013 04:52 PM, Florian Vaussard wrote:
>>> Hello,
>>>
>>> Following a similar proposal by Stephen Warren for tegra [1], this series
>>> makes use of the C preprocessor when compiling OMAP DT files, and
>>> accomplishes some improvements to improve overall readability.
>
> Thanks for that nice cleanup.
>
>> I realized that I should also address am* devices. I will wait for comments
>> on this version, then post a v4. Sorry for the noise.
>
> That's up to you, but I can anyway already pulled that series. That AM*
> patches can go later.
>

I saw in your for_3.11/dts branch that you have a couple of patches 
declaring
new pinctrl bindings, so I should base my series of this branch to address
these patches as well. So I will send a v4 anyway in the coming days.

Thanks,

Florian


From will.deacon at arm.com  Wed May 29 04:54:27 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 09:54:27 +0100
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com>
 <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com>
 <51A4FC08.3060906@ti.com>
 <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>
Message-ID: <20130529085426.GA13095@mudshark.cambridge.arm.com>

On Wed, May 29, 2013 at 03:14:58AM +0100, Po-Yu Chuang wrote:
> Will,
> I guess nobody noticed this because the MMU of later v7 processors
> fetches page table
> from D-cache. It even doesn't need to clean pmd to PoU.

It does if it's UP. The walker is only guaranteed to read from L1 if you
have the multiprocessing extensions.

As for this function, looks like it's ok because it has precisely one
caller, so it might be worth prefixing it with some underscores to make it
clear that nobody else should be calling it!

Will


From florian.vaussard at epfl.ch  Wed May 29 04:57:18 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Wed, 29 May 2013 10:57:18 +0200
Subject: [PATCH v2 14/14] ARM: dts: AM43x: initial support
In-Reply-To: <51A5C1F3.2070605@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <3790fa57fc4c69da12224fbcec17cd07c59771a0.1369658705.git.afzal@ti.com>
 <51A5C1F3.2070605@ti.com>
Message-ID: <51A5C2EE.4060607@epfl.ch>

Hello,

On 05/29/2013 10:53 AM, Benoit Cousson wrote:
> + Florian
>
> Hi Afzal,
>
> On 05/27/2013 04:37 PM, Afzal Mohammed wrote:
>> DT source (minimal) for AM4372 SoC to represent AM43x SoC's. Those
>> represented here are the minimal DT nodes necessary to get kernel
>> booting.
>>
>> In DT nodes, "ti,hwmod" property has not been added, this would be
>> added along with PRCM support for AM43x.
>>
>> Signed-off-by: Ankur Kishore <a-kishore at ti.com>
>> Signed-off-by: Afzal Mohammed <afzal at ti.com>
>> ---
>>
>> v2: Add gptimer 1ms, timer2, synctimer and remove twd local timer
>>
>>   arch/arm/boot/dts/am4372.dtsi | 66 +++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 66 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/am4372.dtsi
>>
>> diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
>> new file mode 100644
>> index 0000000..1d58298
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/am4372.dtsi
>> @@ -0,0 +1,66 @@
>> +/*
>> + * Device Tree Source for AM4372 SoC
>> + *
>> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
>> + *
>> + * This file is licensed under the terms of the GNU General Public License
>> + * version 2.  This program is licensed "as is" without any warranty of any
>> + * kind, whether express or implied.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>
> You can now use the C preprocessor statement instead of this one.
> Florian already started doing the change [1].
>
> Beside that detail, that patch looks good to me.
> I'll pull it separately of the series.
>

If you pull the patch in your branch, I can take care of the changes 
when I rebase
my series. This will allow me to clean the 'interrupts' statements below 
as well.

Regards,

Florian

> Regards,
> Benoit
>
> [1] http://thread.gmane.org/gmane.linux.ports.arm.omap/98320
>
>> +
>> +/ {
>> +	compatible = "ti,am4372", "ti,am43";
>> +	interrupt-parent = <&gic>;
>> +
>> +
>> +	aliases {
>> +		serial0 = &uart1;
>> +	};
>> +
>> +	cpus {
>> +		cpu at 0 {
>> +			compatible = "arm,cortex-a9";
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller at 48241000 {
>> +		compatible = "arm,cortex-a9-gic";
>> +		interrupt-controller;
>> +		#interrupt-cells = <3>;
>> +		reg = <0x48241000 0x1000>,
>> +		      <0x48240100 0x0100>;
>> +	};
>> +
>> +	ocp {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		uart1: serial at 44e09000 {
>> +			compatible = "ti,am4372-uart","ti,omap2-uart";
>> +			reg = <0x44e09000 0x2000>;
>> +			interrupts = <0 72 0x4>;
>> +		};
>> +
>> +		timer1: timer at 44e31000 {
>> +			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
>> +			reg = <0x44e31000 0x400>;
>> +			interrupts = <0 67 0x4>;
>> +			ti,timer-alwon;
>> +		};
>> +
>> +		timer2: timer at 48040000  {
>> +			compatible = "ti,am4372-timer","ti,am335x-timer";
>> +			reg = <0x48040000  0x400>;
>> +			interrupts = <0 68 0x4>;
>> +		};
>> +
>> +		counter32k: counter at 44e86000 {
>> +			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
>> +			reg = <0x44e86000 0x40>;
>> +		};
>> +	};
>> +};
>>
>


From b-cousson at ti.com  Wed May 29 05:04:43 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 11:04:43 +0200
Subject: [PATCH v3 0/5] ARM: dts: OMAP2+: use preprocessor for device trees
In-Reply-To: <51A5C1FE.6020404@epfl.ch>
References: <1369666354-29152-1-git-send-email-florian.vaussard@epfl.ch>
 <51A46DB0.5020508@epfl.ch> <51A5C068.9040308@ti.com>
 <51A5C1FE.6020404@epfl.ch>
Message-ID: <51A5C4AB.2060209@ti.com>

On 05/29/2013 10:53 AM, Florian Vaussard wrote:
> Hello Benoit,
> 
> On 05/29/2013 10:46 AM, Benoit Cousson wrote:
>> Salut Florian,
>>
>> On 05/28/2013 10:41 AM, Florian Vaussard wrote:
>>>
>>> On 05/27/2013 04:52 PM, Florian Vaussard wrote:
>>>> Hello,
>>>>
>>>> Following a similar proposal by Stephen Warren for tegra [1], this
>>>> series
>>>> makes use of the C preprocessor when compiling OMAP DT files, and
>>>> accomplishes some improvements to improve overall readability.
>>
>> Thanks for that nice cleanup.
>>
>>> I realized that I should also address am* devices. I will wait for
>>> comments
>>> on this version, then post a v4. Sorry for the noise.
>>
>> That's up to you, but I can anyway already pulled that series. That AM*
>> patches can go later.
>>
> 
> I saw in your for_3.11/dts branch that you have a couple of patches
> declaring
> new pinctrl bindings, so I should base my series of this branch to address
> these patches as well. So I will send a v4 anyway in the coming days.

OK, no problem. I'll wait for the update.

Regards,
Benoit



From b-cousson at ti.com  Wed May 29 05:05:53 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 11:05:53 +0200
Subject: [PATCH v2 14/14] ARM: dts: AM43x: initial support
In-Reply-To: <51A5C2EE.4060607@epfl.ch>
References: <cover.1369658705.git.afzal@ti.com>
 <3790fa57fc4c69da12224fbcec17cd07c59771a0.1369658705.git.afzal@ti.com>
 <51A5C1F3.2070605@ti.com> <51A5C2EE.4060607@epfl.ch>
Message-ID: <51A5C4F1.3010809@ti.com>

On 05/29/2013 10:57 AM, Florian Vaussard wrote:
> Hello,
> 
> On 05/29/2013 10:53 AM, Benoit Cousson wrote:
>> + Florian
>>
>> Hi Afzal,
>>
>> On 05/27/2013 04:37 PM, Afzal Mohammed wrote:
>>> DT source (minimal) for AM4372 SoC to represent AM43x SoC's. Those
>>> represented here are the minimal DT nodes necessary to get kernel
>>> booting.
>>>
>>> In DT nodes, "ti,hwmod" property has not been added, this would be
>>> added along with PRCM support for AM43x.
>>>
>>> Signed-off-by: Ankur Kishore <a-kishore at ti.com>
>>> Signed-off-by: Afzal Mohammed <afzal at ti.com>
>>> ---
>>>
>>> v2: Add gptimer 1ms, timer2, synctimer and remove twd local timer
>>>
>>>   arch/arm/boot/dts/am4372.dtsi | 66
>>> +++++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 66 insertions(+)
>>>   create mode 100644 arch/arm/boot/dts/am4372.dtsi
>>>
>>> diff --git a/arch/arm/boot/dts/am4372.dtsi
>>> b/arch/arm/boot/dts/am4372.dtsi
>>> new file mode 100644
>>> index 0000000..1d58298
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/am4372.dtsi
>>> @@ -0,0 +1,66 @@
>>> +/*
>>> + * Device Tree Source for AM4372 SoC
>>> + *
>>> + * Copyright (C) 2013 Texas Instruments Incorporated -
>>> http://www.ti.com/
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public
>>> License
>>> + * version 2.  This program is licensed "as is" without any warranty
>>> of any
>>> + * kind, whether express or implied.
>>> + */
>>> +
>>> +/include/ "skeleton.dtsi"
>>
>> You can now use the C preprocessor statement instead of this one.
>> Florian already started doing the change [1].
>>
>> Beside that detail, that patch looks good to me.
>> I'll pull it separately of the series.
>>
> 
> If you pull the patch in your branch, I can take care of the changes
> when I rebase
> my series. This will allow me to clean the 'interrupts' statements below
> as well.

Ooops, thanks, I missed that one.

Thanks,
Benoit

> 
> Regards,
> 
> Florian
> 
>> Regards,
>> Benoit
>>
>> [1] http://thread.gmane.org/gmane.linux.ports.arm.omap/98320
>>
>>> +
>>> +/ {
>>> +    compatible = "ti,am4372", "ti,am43";
>>> +    interrupt-parent = <&gic>;
>>> +
>>> +
>>> +    aliases {
>>> +        serial0 = &uart1;
>>> +    };
>>> +
>>> +    cpus {
>>> +        cpu at 0 {
>>> +            compatible = "arm,cortex-a9";
>>> +        };
>>> +    };
>>> +
>>> +    gic: interrupt-controller at 48241000 {
>>> +        compatible = "arm,cortex-a9-gic";
>>> +        interrupt-controller;
>>> +        #interrupt-cells = <3>;
>>> +        reg = <0x48241000 0x1000>,
>>> +              <0x48240100 0x0100>;
>>> +    };
>>> +
>>> +    ocp {
>>> +        compatible = "simple-bus";
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        ranges;
>>> +
>>> +        uart1: serial at 44e09000 {
>>> +            compatible = "ti,am4372-uart","ti,omap2-uart";
>>> +            reg = <0x44e09000 0x2000>;
>>> +            interrupts = <0 72 0x4>;
>>> +        };
>>> +
>>> +        timer1: timer at 44e31000 {
>>> +            compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
>>> +            reg = <0x44e31000 0x400>;
>>> +            interrupts = <0 67 0x4>;
>>> +            ti,timer-alwon;
>>> +        };
>>> +
>>> +        timer2: timer at 48040000  {
>>> +            compatible = "ti,am4372-timer","ti,am335x-timer";
>>> +            reg = <0x48040000  0x400>;
>>> +            interrupts = <0 68 0x4>;
>>> +        };
>>> +
>>> +        counter32k: counter at 44e86000 {
>>> +            compatible = "ti,am4372-counter32k","ti,omap-counter32k";
>>> +            reg = <0x44e86000 0x40>;
>>> +        };
>>> +    };
>>> +};
>>>
>>



From will.deacon at arm.com  Wed May 29 05:08:50 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 10:08:50 +0100
Subject: VDSO for arm 32bit
In-Reply-To: <alpine.LFD.2.03.1305281415040.1918@syhkavp.arg>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
 <alpine.LFD.2.03.1305281415040.1918@syhkavp.arg>
Message-ID: <20130529090850.GB13095@mudshark.cambridge.arm.com>

On Tue, May 28, 2013 at 07:19:00PM +0100, Nicolas Pitre wrote:
> On Tue, 28 May 2013, Will Deacon wrote:
> > Be careful here. I had a crack at a gtod implementation for the vectors page
> > in the past, but decided to drop it because it quickly became a maintenance
> > nightmare. Since the layout of the vectors page must be fixed (as userspace
> > jumps to the absolute addresses for the helpers), having large, complicated
> > functions (which gtod does become as you quickly start using the stack to
> > store all of the shared state with the kernel) means that you can quickly
> > back yourself into a corner where the layout of the code cannot change
> > without breaking the ABI.
> 
> Note that only the entry point is fixed.  The layout of the code is not.  
> So you may well branch anywhere else within the vector page if the code 
> is more complex than a few instructions.

Sure, it may be possible simply to have branches in the kuser slots and then
reserve a chunk at the other end of the vectors page where the actual
implementation can go.

> > On top of that, new clock types are added more often than you might think
> > (not to mention bug fixes in the implementation itself), and you end up in
> > a horrible situation where you'd end up deprecating one implementation and
> > adding gettimeofday2 or something equally nasty at a different offset.
> 
> That is equally valid for a vdso.

Sorry, I wasn't clear. My point was that you can change the layout of a vdso
without breaking anything, since the dynamic loader resolves the entry
points. It relates back to what I said above -- you need to be careful about
how you lay the stuff out in memory.

Perhaps the gtod code won't end up being that big. It's around ~500 bytes on
arm64, but that's without any stack usage. Come to think of it, is there any
reason why we can't just map an additional vectors page after the one we
currently have?

Will


From m.szyprowski at samsung.com  Wed May 29 05:16:14 2013
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 29 May 2013 11:16:14 +0200
Subject: [PATCH] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
In-Reply-To: <120501ce5752$6daef380$490cda80$%kim@samsung.com>
References: <1368630484-29939-1-git-send-email-t.figa@samsung.com>
 <1623377.nVo7nUcid2@flatron> <120501ce5752$6daef380$490cda80$%kim@samsung.com>
Message-ID: <51A5C75E.7090006@samsung.com>

Hello,

On 5/23/2013 3:11 AM, Kukjin Kim wrote:
> Kukjin Kim wrote:
> >
> > Tomasz Figa wrote:
> > >
> > > Hi Kukjin,
> > >
> > Hi,
> >
> > > On Wednesday 15 of May 2013 17:08:04 Tomasz Figa wrote:
> > > > This patch extends exynos_init_time() function to handle Exynos4210
> > rev0
> > > > SoC, which differs in availability of system timers and needs
> > different
> > > > clocksource initialization.
> > > >
> > > > This makes it possible to use exynos_init_time() function as init_time
> > > > callback for all Exynos-based boards, including Universal_C210, which
> > > > originally had to use samsung_timer_init().
> > > >
> > > > Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> > > > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > > > ---
> > > >  arch/arm/mach-exynos/Kconfig               |  3 ++-
> > > >  arch/arm/mach-exynos/common.c              | 30
> > > > +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h
> > > >   |  2 ++
> > > >  arch/arm/mach-exynos/mach-universal_c210.c |  5 ++---
> > > >  4 files changed, 35 insertions(+), 5 deletions(-)
> > >
> > > Could you pick this patch to your fixes branch?
> > >
> > Yeah, I will after looking at.
> >
> > > This is a fix of a regression in handling Exynos4210 rev0 SoC (e.g.
> > > Universal C210 board) introduced by patches merged to 3.10.
> > >
> > OK, I see but I didn't review yet and I  will within a couple of days ;-)
> >
> OK, looks fine, this will be sent to upstream during -rc for v3.10.
>
> But, Tomasz, as you know, non-DT supporting files will be gone away in
> v3.11, just note.

This patch is needed to get REV0 4210 based board working both in DT and 
non-DT
modes.

Best regards
-- 
Marek Szyprowski
Samsung R&D Institute Poland




From will.deacon at arm.com  Wed May 29 05:24:21 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 10:24:21 +0100
Subject: VDSO for arm 32bit
In-Reply-To: <634BB1CFA60ED14386C17849392C3EB202E52CA407@HICGWSEX01.ad.harman.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
 <634BB1CFA60ED14386C17849392C3EB202E52CA407@HICGWSEX01.ad.harman.com>
Message-ID: <20130529092421.GC13095@mudshark.cambridge.arm.com>

On Wed, May 29, 2013 at 05:00:09AM +0100, Kumar, Ganesh wrote:
>    Hmm, it doesn't seem to be quite straight forward, but thanks for the
>    inputs and caution.  Now that I got a direction, I'm planning to
>    proceed as below: 1. As a first step, get the implementation up and
>    running using the kuser helper (understand the situation and plan to
>    limit my implementation for the ARM Cortex's arch timer clock type) On
>    the user land, does this approach needs a change to the libc, kindly
>    confirm. I read the kernel documentation for kuser helper, it gave a
>    nice overview of how things can be done, but not so clear on how
>    actually the helper functions can be called from the user land (the big
>    picture), does it needs a tweak in the libc in order to enable     the
>    new helper functions defined.

Yes, libc would need updating to direct the various clock system calls via
the vectors page if the kernel is recent enough. Your implementation will
need to fall back to issuing the system call if the arch timer isn't the
current clocksource.

> 2. Plan to get it up through the VDSO, study in progress. One question
> here, was the vdso implementation for 32 bit is not available only because
> of the frequent addition in new clock types or there is any strong reason
> or something I need to take care about, kindly clarify.  I'll start
> looking into the arm64 vdso code as a starting point, is there anything
> else I can refer/read to get going? kindly help. 

This might not be needed after the feedback from Nicolas.

> >>> I know some people were toying with exposing memory-mapped timers to
> >>> userspace, but >>> that really scares me.
> 
>    Just curious, what are the side effects of exposing the memory-mapped
>    timers to user space.

Just that you need to be careful about what you expose and how do you expose
it. For example, control registers may lie in the same page as the actual
counter, and you don't want userspace having access to that if possible.

You'd probably also need to copy code into place, since there are many timer
implementations that could be used.

Will


From jg1.han at samsung.com  Wed May 29 05:33:01 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 29 May 2013 18:33:01 +0900
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <51A5C16D.20408@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 <51A5C16D.20408@linaro.org>
Message-ID: <000001ce5c4f$839f4cb0$8adde610$@samsung.com>

On Wednesday, May 29, 2013 5:51 PM, Tushar Behera:
> On 05/29/2013 11:01 AM, Olof Johansson wrote:
> > On Tue, May 28, 2013 at 8:59 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
> >
> >> The patches are at [1].
> >
> > FWIW, a cgit/gitweb link is easier to follow when you're reading an
> > email. Anyway, found the patches.
> >
> >> There are a total of 6 patches on top of
> >> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
> >> (c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
> >> (e, f) are required to reset the hub during EHCI initialization.
> >
> > Huh, I thought you said that (c) wasn't needed when I posted the
> > defconfig update. It'd be nice to see the code fixed to handle this
> > case instead of Linaro carrying a patch like this though. I.e. make it
> > able to deselect the uart, or make it tied to DEBUG_LL like on other
> > platforms instead of having a separate config for this.
> >
> 
> It would be good to free up the dependency on the correct UART port for
> the board to boot. Without that, there would always be boards that don't
> boot with default mainline defconfig file even though all other
> components are in place.
> 
> >> a. ARM: exynos: defconfig update
> >> b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
> >> c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
> >> d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
> >> e. usb: ehci-s5p: add the HSIC port initialization
> >> f. ARM: dts: Add USB gpio entries for Arndale board
> >>
> >> I am not sure whether such kind of board-specific patches (e, f) are
> >> appreciated in the drivers. But that is all we need to get USB and
> >> Ethernet to work on v3.10-rc3 kernel.
> >
> > I've come across a similar situation with wifi reset sequence on the
> > chromebook. On the product kernel we added some code to the board file
> > to deal with it, but if we keep doing that things will grow out of
> > hand.
> >
> > I don't know if it'll be unpopular, but I think it's time to start a
> > drivers/platform/arm for these kind of things, and have those drivers
> > probe on the system compatible value, similar to how x86 does it (with
> > DMI tables). At least that's my plan for approaching the wifi
> > reset/power-on sequence on the Chromebook. I hope to have patches in
> > not all that long...
> >
> > Likewise, the hub reset/enable code doesn't have to go with the USB
> > driver, right? I.e. if you cycle reset/enable on the hub after the
> > host and phy is configured, you'll still have a working setup?
> >
> 
> Right, hub reset/enable code need not be tied up with USB driver. As per
> your suggestion regarding drivers/platform/arm, I implemented an Arndale
> specific driver [2] in drivers/platform/arm and verified USB and
> ethernet to be working.

CC'ed Thomas Abraham, Vivek Gautam

I think so.

I looked at Arndale board Schematics.
'Hub chip' on Arndale board needs hub reset/enable code.
'HUB_RESET' and 'HUB_CONNECT' pins are used to reset 'Hub chip'
on Arndale board, not Exynos EHCI controller. So, Exynos EHCI driver
does not need to consider this hub reset/enable code.

If there is a driver for this 'Hub chip', 'Hub chip' driver maybe
consider this.

However, Olof Johansson mentioned, 'drivers/platform/arm/board_arndale.c'
would be a good alternative.

> 
> [2]
> https://git.linaro.org/gitweb?p=landing-
> teams/working/samsung/kernel.git;a=shortlog;h=refs/heads/upstream/arndale-usb-2

It looks good.

Best regards,
Jingoo Han

> 
> >
> > -Olof
> >
> 
> 
> --
> Tushar Behera
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From ratbert.chuang at gmail.com  Wed May 29 05:34:01 2013
From: ratbert.chuang at gmail.com (Po-Yu Chuang)
Date: Wed, 29 May 2013 17:34:01 +0800
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <20130529085426.GA13095@mudshark.cambridge.arm.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com> <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com> <51A4FC08.3060906@ti.com>
 <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>
 <20130529085426.GA13095@mudshark.cambridge.arm.com>
Message-ID: <CANutaR_8jNDzPeyJ8PLZPS=yiZ8Ywmk08dR9vLcB2CpxuJac3A@mail.gmail.com>

Hi Will,

On Wed, May 29, 2013 at 4:54 PM, Will Deacon <will.deacon at arm.com> wrote:
> On Wed, May 29, 2013 at 03:14:58AM +0100, Po-Yu Chuang wrote:
>> Will,
>> I guess nobody noticed this because the MMU of later v7 processors
>> fetches page table
>> from D-cache. It even doesn't need to clean pmd to PoU.
>
> It does if it's UP. The walker is only guaranteed to read from L1 if you
> have the multiprocessing extensions.

Ya, I see.

>
> As for this function, looks like it's ok because it has precisely one
> caller, so it might be worth prefixing it with some underscores to make it
> clear that nobody else should be calling it!

I am fine with that.
Should I create a new patch?

Regards,
Po-Yu


From jlu at pengutronix.de  Wed May 29 05:36:04 2013
From: jlu at pengutronix.de (Jan =?ISO-8859-1?Q?L=FCbbe?=)
Date: Wed, 29 May 2013 11:36:04 +0200
Subject: [PATCH v2] usb: musb: fix clock naming
In-Reply-To: <20130528173637.GE15794@arwen.pp.htv.fi>
References: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>
 <20130528173637.GE15794@arwen.pp.htv.fi>
Message-ID: <1369820164.6673.55.camel@polaris.local>

On Tue, 2013-05-28 at 20:36 +0300, Felipe Balbi wrote: 
> On Tue, May 28, 2013 at 09:21:01AM +0200, yegorslists at googlemail.com wrote:
> > From: Yegor Yefremov <yegorslists at googlemail.com>
> > 
> > 'ick' was changed to 'hsotgusb_ick'
> > 'fck' was changed to 'hsotgusb_fck'
> > 
> > Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
> > Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
> 
> NAK. Fix your clock data.

Yegor, I'm not sure how my signed-off-by got here. It seems that you
picked the patch up from this thread:
http://marc.info/?l=linux-omap&m=134390141101734

Note that my mail contains no signed-off-by and the change is described
as a work around.

Regards,
Jan


From b-cousson at ti.com  Wed May 29 05:36:48 2013
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 29 May 2013 11:36:48 +0200
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ
 pin and msecure line
In-Reply-To: <87a9nfc5uc.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <87ppwgdnxu.fsf@linaro.org>
 <CAGo_u6ruWQwSB8Z0BRLda7HunTyr9mGpx4eMSGdQZkCxKxbHbg@mail.gmail.com>
 <87a9nfc5uc.fsf@linaro.org>
Message-ID: <51A5CC30.4010707@ti.com>

Salut Kevin,

On 5/28/2013 8:33 PM, Kevin Hilman wrote:
> Nishanth Menon <nm at ti.com> writes:
>
>> On Fri, May 24, 2013 at 5:15 PM, Kevin Hilman <khilman at linaro.org> wrote:
>>> Kevin Hilman <khilman at linaro.org> writes:
>>>
>>>> Nishanth Menon <nm at ti.com> writes:
>>>
>>> [...]
>>>
>>>>> Actually 2 things:
>>>>>
>>>>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>>>>> have been used instead of 0x14 which is correct for 4430?
>>>>
>>>> I see, thanks.  I'll double check the TRMs.
>>>>
>>>>> b) yes, I understand,  the current settings we did worked, but the
>>>>> mode(0) we are setting to is real weird - we are setting it up for
>>>>> clk0 out - I cant even think why it is even working in the first place
>>>>> :( - is it because we are pumping out sysclkout and as a result we are
>>>>> lucky that msecure is being sampled at the right point by twl6030
>>>>> allowing rtc access? either way, IMHO, the configuration is wrong.
>>>>
>>>> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
>>>> for legacy mode, I just duplicated the settings u-boot was using.  Guess
>>>> it's a fluke that it works.
>>>
>>> Actually, for legacy mode, it's set correctly in mode 2.  This line:
>>>
>>>          omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
>>>
>>> does the right thing based on the signal name.    But for DT boot, I
>>> defintely screwed it up by setting it to mode (and putting it in the
>>> wrong padconf section.)
>>>
>>> Also, are you *really* sure about the offset difference between 4430 and
>>> 4460 here?  I don't have access to NDA docs anymore, so I cannot double
>>> check this.
>>>
>>> What I do know is that the legacy code is using 0x54 for both, and if I
>>> simply comment out that 'sys_drm_msecure' line above, RTC wake stops
>>> working (legacy boot) on both 4430 and 4460, so that seems like pretty
>>> stront evidence that it's the same offset on both.
>> Schematics are public for PandaBoard ES and PandaBoard - as you can
>> see from that the registers connected are definitely different.
>
> What I see from both schematics is that SYS_DRM_MSECURE is available on
> a few different pads, but on both 4430 and 4460, one of the places is in
> mode 2 of FREF_CLK0_OUT, which is at offset 0x54 on both SoCs.
>
> Based on that reading, and the fact that not correctly muxing that pad
> to mode 2 on *both* 4430 and 4460 makes the RTC work, I'm rather
> convinced that the offset should be the same for 4430 and 4460.
>
> What am I missing?

I've just checked both specs and schematics and in the two cases the 
exact same ball (AD2) is connected to the exact same signal 
(mod2=sys_drm_msecure) and the registers offset inside the 
control_module are the same as well.

Nishanth,
AD4 ball in both cases is used for USBB1_PHY_REFCLK signal.

Thanks,
Benoit



From b-cousson at ti.com  Wed May 29 05:38:45 2013
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 29 May 2013 11:38:45 +0200
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ
 pin and msecure line
In-Reply-To: <87a9nkf3mu.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org>
Message-ID: <51A5CCA5.7000700@ti.com>

On 5/24/2013 11:51 PM, Kevin Hilman wrote:
> Nishanth Menon <nm at ti.com> writes:
>
>> On Fri, May 24, 2013 at 4:19 PM, Kevin Hilman <khilman at linaro.org> wrote:
>>> Nishanth Menon <nm at ti.com> writes:
>>>
>>>> On 15:09-20130524, Nishanth Menon wrote:
>>>>> On 12:28-20130524, Kevin Hilman wrote:
>>>>>> Earlier commits ensured proper muxing of pins related to proper
>>>>>> TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
>>>>>> sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
>>>>>> OMAP4: TWL: mux sys_drm_msecure as output for PMIC).
>>>>>>
>>>>>> However these only fixed legacy boot and not DT boot.  For DT boot,
>>>>>> the default mux values need to be set properly in DT.
>>>>>>
>>>>>> Cc: Tony Lindgren <tony at atomide.com>
>>>>>> Signed-off-by: Kevin Hilman <khilman at linaro.org>
>>>>>> ---
>>>>>> Applies on v3.10-rc2
>>>>>>
>>>>>>   arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++
>>>>>>   arch/arm/boot/dts/omap4-sdp.dts           | 8 ++++++++
>>>>>>   2 files changed, 16 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>>>> index 03bd60d..a7a9bc0 100644
>>>>>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>>>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>>>> @@ -59,6 +59,7 @@
>>>>>>   &omap4_pmx_core {
>>>>>>     pinctrl-names = "default";
>>>>>>     pinctrl-0 = <
>>>>>> +                  &twl6030_pins
>>>>>>                     &twl6040_pins
>>>>>>                     &mcpdm_pins
>>>>>>                     &mcbsp1_pins
>>>>>> @@ -66,6 +67,13 @@
>>>>>>                     &tpd12s015_pins
>>>>>>     >;
>>>>>>
>>>>>> +  twl6030_pins: pinmux_twl6030_pins {
>>>>>> +          pinctrl-single,pins = <
>>>>>> +                  0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
>>>>> I can understand this - IRQ request comes here.
>>>>> verified on OMAP4460 Panda-ES.
>>>>> # omapconf read 0x4A10019C
>>>>> 4118011B
>>>>>
>>>>>> +                  0x14 0x0        /* fref_clk0_out.sys_drm_msecure OUTPUT */
>>>>> I do not understand this.
>>>>> OMAP4460 TRM:
>>>>> Register: CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ
>>>>> omapconf read 0x4A31E054
>>>>> 010F010F
>>>>>
>>>>> I do not understand this configuration. mux modes for
>>>>> FREF_CLK0_OUT_MUXMODE:
>>>>> 0x0: Select fref_clk0_out
>>>>> 0x1: Select fref_clk1_req
>>>>> 0x2: Reserved
>>>>> 0x3: Select gpio_wk6
>>>>> 0x5: Select sdmmc2_dat7
>>>>> 0x6: Select hw_dbg6
>>>>> 0x7: Select safe_mode
>>>>>
>>>>> Why are we setting mode 0(clk out) here?
>>>>
>>>> I did a bit more research into this:
>>>> MSECURE line needs to be set for us to set anything with TWL6030 RTC.
>>>
>>> Yes, the commit referenced in the changelog described that in detail.
>>>
>>>> PandaBoard ES(4460) = this is on OMAP PIN AD4
>>>> PandaBoard (4430) = this is on OMAP PIN AD2
>>>>
>>>> translating this back,
>>>> PandaBoard ES OMAp4460 pin AD4:
>>>> FREF_CLK3_OUT/FREF_CLK2_REQ/SYS_SECURE_INDICATOR/GPIO_WK31/C2C_WAKEREQOUT/SDMMC2_DAT5/ATTILA_HW_DBG8/SAFE_MODE
>>>> This is at register 0x4A31E054(higher 16 bits) - however since we are GP device,
>>>> SYS_SECURE_INDICATOR(mode 2) is reserved.
>>>> PandaBoard OMAP4430 pin AD2:
>>>> FREF_CLK0_OUT/FREF_CLK1_REQ/SYS_DRM_MSECURE/GPIO_WK6/SDMMC2_DAT7/ATTILA_HW_DBG6/SAFE_MOD
>>>> This is at register 0x4A31E054(lower 16 bits) - however since we are GP device,
>>>> SYS_DRM_MSECURE(mode 2) is reserved.
>>>>
>>>> To use RTC, we will have to use GPIO.
>>>> on pandaboard ES, we need GPIO31 and PandaBoard, 6.
>>>>
>>>> Further the pinctrl offsets will vary as well between the same.
>>>>
>>>> IMHO, we need GPIO support and pinmux appropritate to the same to allow
>>>> RTC to work.
>>>
>>> I don't follow at all what you're trying to say.  The current settings
>>> are working fine and have been tested on both 4430/Panda and 4460/Panda-ES.
>>>
>>> The goal of this patch is to make default mux settings for twl6030 for
>>> DT boot match current legacy boot in mainline.
>>>
>>> The commits referenced in the changelog setup some default muxing for
>>> twl6030 (see changelogs referenced and mux calls in
>>> twl-common.c:omap4_pmic_init())
>>>
>>> Without those mux settings, RTC wakeup on legacy boot does not work
>>> (tested on 4430/panda, 4460/Panda with recent u-boot v2013.04 where most
>>> of the old mux setup is gone.)  With those settings, RTC wakeup works.
>>>
>>> Yes, the TRM has some mode bits marked as reserved, but that doesn't
>>> mean they don't work.  It just means the documentation is squirreled
>>> away in the secure TRM addendum.
>>>
>> Actually 2 things:
>>
>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>> have been used instead of 0x14 which is correct for 4430?
>
> I see, thanks.  I'll double check the TRMs.
>
>> b) yes, I understand,  the current settings we did worked, but the
>> mode(0) we are setting to is real weird - we are setting it up for
>> clk0 out - I cant even think why it is even working in the first place
>> :( - is it because we are pumping out sysclkout and as a result we are
>> lucky that msecure is being sampled at the right point by twl6030
>> allowing rtc access? either way, IMHO, the configuration is wrong.
>
> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
> for legacy mode, I just duplicated the settings u-boot was using.  Guess
> it's a fluke that it works.
>
> Yet another thing wrong with my patch:  the fref_clk0 pad is in the WKUP
> padconf section, and I put it at offset 0x14 in the CORE section, which
> is yet another wrong place.
>
> Let me respin this after some more doc reading.

Did you re-spin it already?

Beside that mode0 typo, it looks good to me.

Thanks,
Benoit


From b-cousson at ti.com  Wed May 29 05:40:10 2013
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 29 May 2013 11:40:10 +0200
Subject: [PATCH v6] ARM:dts:omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <519FB7F7.7080009@ti.com>
References: <1368806552-8851-1-git-send-email-dmurphy@ti.com>
 <20130517161525.GA30014@kahuna> <5196580D.1070209@ti.com>
 <519FB7F7.7080009@ti.com>
Message-ID: <51A5CCFA.2010209@ti.com>

Hi Dan,

On 5/24/2013 8:56 PM, Dan Murphy wrote:
> On 05/17/2013 11:17 AM, Dan Murphy wrote:
>> On 05/17/2013 11:15 AM, Nishanth Menon wrote:
>>> On 11:02-20130517, Dan Murphy wrote:
>>>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>>>> are different.
>>>>
>>>> A1-A3 = gpio_wk7
>>>> ES = gpio_110
>>>>
>>>> There is no change to LED D2
>>>>
>>>> Abstract away the pinmux and the LED definitions for the two boards into
>>>> the respective DTS files.
>>>>
>>>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
>>>> ---
>>>> Changes in this version:
>>>> 	- review comments incorporated.
>>>> Previous version of this patch was discussed in:
>>>> 	https://patchwork.kernel.org/patch/2582771/
>>> one minor nit,
>>> $subject could do with space after the ':'
>>> otherwise, it looks fine to me. Will suggest waiting for further
>>> reviewers if they have an opinion prior to a new rev.
>> Thanks NM I will queue up this change locally and await further review prior to sending v7.
>>
>>>>   arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>>>>   arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>>>>   2 files changed, 43 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> index 03bd60d..5fd59b3 100644
>>>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>>>> @@ -16,8 +16,13 @@
>>>>   		reg = <0x80000000 0x40000000>; /* 1 GB */
>>>>   	};
>>>>
>>>> -	leds {
>>>> +	leds: leds {
>>>>   		compatible = "gpio-leds";
>>>> +		pinctrl-names = "default";
>>>> +		pinctrl-0 = <
>>>> +			&led_wkgpio_pins
>>>> +		>;
>>>> +
>>>>   		heartbeat {
>>>>   			label = "pandaboard::status1";
>>>>   			gpios = <&gpio1 7 0>;
>>>> @@ -137,6 +142,15 @@
>>>>   	};
>>>>   };
>>>>
>>>> +&omap4_pmx_wkup {
>>>> +	led_wkgpio_pins: pinmux_leds_wkpins {
>>>> +		pinctrl-single,pins = <
>>>> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
>>>> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>>>> +		>;
>>>> +	};
>>>> +};
>>>> +
>>>>   &i2c1 {
>>>>   	pinctrl-names = "default";
>>>>   	pinctrl-0 = <&i2c1_pins>;
>>>> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
>>>> index f1d8c21..c968a3b 100644
>>>> --- a/arch/arm/boot/dts/omap4-panda-es.dts
>>>> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
>>>> @@ -34,3 +34,31 @@
>>>>   		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>>>>   		>;
>>>>   };
>>>> +
>>>> +&omap4_pmx_core {
>>>> +	led_gpio_pins: gpio_led_pmx {
>>>> +		pinctrl-single,pins = <
>>>> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
>>>> +		>;
>>>> +	};
>>>> +};
>>>> +
>>>> +&led_wkgpio_pins {
>>>> +	pinctrl-single,pins = <
>>>> +		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
>>>> +	>;
>>>> +};
>>>> +
>>>> +&leds {
>>>> +	pinctrl-0 = <
>>>> +		&led_gpio_pins
>>>> +		&led_wkgpio_pins
>>>> +	>;
>>>> +
>>>> +	heartbeat {
>>>> +		gpios = <&gpio4 14 0>;
>>>> +	};
>>>> +	mmc {
>>>> +		gpios = <&gpio1 8 0>;
>>>> +	};
>>>> +};
>>
> Any additional comments besides the headline?
>
> If not I will post v7

Sorry for the delay.

Go ahead and I'll take it in my dts branch for 3.11.

Thanks,
Benoit



From jg1.han at samsung.com  Wed May 29 05:47:29 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 29 May 2013 18:47:29 +0900
Subject: [PATCH 1/2] ARM: dts: Add USB Host nodes to Exynos4210
Message-ID: <000101ce5c51$887309f0$99591dd0$@samsung.com>

Add device nodes for USB Host EHCI and OHCI controllers to Exynos4210.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
Tested on Exynos4210.

 arch/arm/boot/dts/exynos4210.dtsi |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..3c173c7 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -117,6 +117,24 @@
 		status = "disabled";
 	};
 
+	usb at 12580000 {
+		compatible = "samsung,exynos4210-ehci";
+		reg = <0x12580000 0x100>;
+		interrupts = <0 70 0>;
+
+		clocks = <&clock 304>;
+		clock-names = "usbhost";
+	};
+
+	usb at 12590000 {
+		compatible = "samsung,exynos4210-ohci";
+		reg = <0x12590000 0x100>;
+		interrupts = <0 70 0>;
+
+		clocks = <&clock 304>;
+		clock-names = "usbhost";
+	};
+
 	g2d at 12800000 {
 		compatible = "samsung,s5pv210-g2d";
 		reg = <0x12800000 0x1000>;
-- 
1.7.10.4




From jg1.han at samsung.com  Wed May 29 05:48:12 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 29 May 2013 18:48:12 +0900
Subject: [PATCH 2/2] ARM: dts: Add USB PHY node to Exynos4210
Message-ID: <000201ce5c51$a261d530$e7257f90$@samsung.com>

Add device node for USB 2.0 PHY controller to Exynos4210.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
Tested on Exynos4210.

 arch/arm/boot/dts/exynos4210.dtsi |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 3c173c7..bec6637 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -135,6 +135,20 @@
 		clock-names = "usbhost";
 	};
 
+	usb2_phy: usbphy at 125b0000 {
+		compatible = "samsung,exynos4210-usb2phy";
+		reg = <0x125b0000 0x100>;
+		clocks = <&clock 2>, <&clock 305>;
+		clock-names = "xusbxti", "usb_device";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usbphy-sys {
+			reg = <0x10020704 0x8>;
+		};
+	};
+
 	g2d at 12800000 {
 		compatible = "samsung,s5pv210-g2d";
 		reg = <0x12800000 0x1000>;
-- 
1.7.10.4




From will.deacon at arm.com  Wed May 29 05:48:27 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 10:48:27 +0100
Subject: A bug about system call on ARM
In-Reply-To: <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
Message-ID: <20130529094826.GD13095@mudshark.cambridge.arm.com>

Hello,

On Wed, May 29, 2013 at 09:46:42AM +0100, richard -rw- weinberger wrote:
> On Wed, May 29, 2013 at 10:24 AM, Wang, Yalin <Yalin.Wang at sonymobile.com> wrote:
> > I have download the latest linux kernel code  3.9.4
> > And Compare with  3.4.0 kernel .
> >
> > It seems there is no change for this part ,
> > So it will still happen .
> > Does anyone know who is responsible for  arm arch part kernel code ?
> 
> See MAINTAINERS file.
> CC'ing linux-arm-kernel at lists.infradead.org

Cheers for adding us to CC.

> >> #ifdef CONFIG_ARM_THUMB
> >>         tst     r8, #PSR_T_BIT
> >>         movne   r10, #0                         @ no thumb OABI emulation
> >>         ldreq   r10, [lr, #-4]                  @ get SWI instruction          // crash at this instruction, when get SWI instruction

Do you have the panic log please? Also, which SoC are you using and how are
you reproducing this?

> >>         ldr     r10, [lr, #-4]                  @ get SWI instruction
> >>   A710( and     ip, r10, #0x0f000000            @ check for SWI         )
> >>   A710( teq     ip, #0x0f000000                                         )
> >>   A710( bne     .Larm710bug                                             )
> >> #endif
> >> #ifdef CONFIG_CPU_ENDIAN_BE8
> >>         rev     r10, r10                        @ little endian instruction
> >> #endif
> >>
> >> /*********************************************************************
> >> ******************************/
> >>
> >> Then reason why it will crash when get SWI instruction is maybe This
> >> page is clear to aged by kernel, But this MMU fault happpened in
> >> kernel, So the kernel do_page_fault function will not clear this page
> >> to young, So that  will crash .

Sounds like we might need some USER annotations around the instruction
loads, but we should also rework the code so that we re-enable interrupts
first.

Will


From yegorslists at googlemail.com  Wed May 29 05:51:54 2013
From: yegorslists at googlemail.com (Yegor Yefremov)
Date: Wed, 29 May 2013 11:51:54 +0200
Subject: [PATCH v2] usb: musb: fix clock naming
In-Reply-To: <1369820164.6673.55.camel@polaris.local>
References: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>
 <20130528173637.GE15794@arwen.pp.htv.fi>
 <1369820164.6673.55.camel@polaris.local>
Message-ID: <CAGm1_kt2UzOf1o6yGVaifqJpU0hySdW+gzsdSw_qsO9vG_UZ1w@mail.gmail.com>

On Wed, May 29, 2013 at 11:36 AM, Jan L?bbe <jlu at pengutronix.de> wrote:
> On Tue, 2013-05-28 at 20:36 +0300, Felipe Balbi wrote:
>> On Tue, May 28, 2013 at 09:21:01AM +0200, yegorslists at googlemail.com wrote:
>> > From: Yegor Yefremov <yegorslists at googlemail.com>
>> >
>> > 'ick' was changed to 'hsotgusb_ick'
>> > 'fck' was changed to 'hsotgusb_fck'
>> >
>> > Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
>> > Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
>>
>> NAK. Fix your clock data.
>
> Yegor, I'm not sure how my signed-off-by got here. It seems that you
> picked the patch up from this thread:
> http://marc.info/?l=linux-omap&m=134390141101734
>
> Note that my mail contains no signed-off-by and the change is described
> as a work around.

I'll remove your SoB, when I post the next version. I just added it,
because you provided the fix. Will contact you next time first. Have
you worked on this SoC lately? Any pending patches?

Yegor


From afzal at ti.com  Wed May 29 05:58:06 2013
From: afzal at ti.com (Mohammed, Afzal)
Date: Wed, 29 May 2013 09:58:06 +0000
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <51A5BEB6.6070809@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
 <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>
 <51A5BEB6.6070809@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93EAFB174@DBDE04.ent.ti.com>

Hi Benoit,

On Wed, May 29, 2013 at 14:09:18, Cousson, Benoit wrote:
> On 05/29/2013 10:06 AM, Mohammed, Afzal wrote:
> > On Wed, May 29, 2013 at 03:35:10, Stephen Warren wrote:
> >> On 05/28/2013 03:25 PM, Jon Hunter wrote:

> >>> If you are adding more compatibility strings, then this implies that the
> >>> AM43x timers are not 100% compatible with any other device listed (such
> >>> as am335x or any omap device). That's fine but you should state that in
> >>> the changelog. If the AM43x timer registers are 100% compatible with
> >>> existing devices you should not add these.
> >>
> >> I'm not sure that's true; .dts files should always include a compatible
> >> value that describes the most specific model of the HW, plus any
> >> baseline compatible value that the HW is compatible with. This allows
> >> any required quirks/fixes/... to be applied for the specific HW model
> >> later even if nobody knows right now they'll be needed. Hence, defining
> >> new compatible values doesn't necessarily mean incompatible HW.
> > 
> > Stephen took words out of my finger ;)
> >  
> > Some explanations,I don;t 
> > 
> > 1. first compatible should be exact device [A], followed by compatible
> > model (if one)
> > 2. Minor effort in getting DT right the first time may help prevent
> > difficult effort later modifying it (if a necessity comes), considering
> > the fact that DT sources has  to move out of Kernel at some point of
> > time. And DT is not supposed to be modified, which may cause difficulty
> > for the users (I had been a minor victim of this during rebase).
> > 
> > As we both were in GPMC land earlier, an example,
> > 
> > If my memory is right, GPMC IP in am335x is rev 6, and IP has 8 chip
> > select, but one is not pinned out. Now assume that same IP is integrated
> > in another SoC (probably OMAP4 has rev 6). Here if we use same compatible
> > for both, driver cannot handle it properly (w/o knowledge about platform).
> > But if exact compatible is mentioned, without modifying DT (which should
> > be considered as a firmware) just by modifying Kernel, deciding based on
> > compatible would help achieve what is required.
> 
> That's true for the DTS itself, but here your are changing the binding
> documentation which is supposed to reflect the driver "interface" in the
> Device Tree model description.
> 
> Since the driver does not support any new compatible string, you should
> not update the binding.

I have a different opinion: Binding documentation is to be considered an
entity that is not a part of the Kernel, but currently is a part of the
Kernel for want of a better place. And binding is to be considered OS
agnostic being ignorant of any piece of software (driver here). Binding has
the authority to allow its usage in DT sources.

> The driver and the binding will have to be changed the day you will have
> to update the driver to handle a bug / feature specific to that revision
> (ti,am4372-timer).
> 
> Since this series does not seems to update the driver, you should not
> update the bindings.

I believe that updating binding is a prerequisite for making a new
DTS change, hence binding was updated first, then DTS. 

Regards
Afzal


From yegorslists at googlemail.com  Wed May 29 06:06:52 2013
From: yegorslists at googlemail.com (Yegor Yefremov)
Date: Wed, 29 May 2013 12:06:52 +0200
Subject: [PATCH v2] usb: musb: fix clock naming
In-Reply-To: <20130528173637.GE15794@arwen.pp.htv.fi>
References: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>
 <20130528173637.GE15794@arwen.pp.htv.fi>
Message-ID: <CAGm1_ks7Y8n1xKA=qiCCFcxgydRiyeJS08A8TPnbnEEmkJxVyg@mail.gmail.com>

On Tue, May 28, 2013 at 7:36 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Tue, May 28, 2013 at 09:21:01AM +0200, yegorslists at googlemail.com wrote:
>> From: Yegor Yefremov <yegorslists at googlemail.com>
>>
>> 'ick' was changed to 'hsotgusb_ick'
>> 'fck' was changed to 'hsotgusb_fck'
>>
>> Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
>> Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
>
> NAK. Fix your clock data.

Do you mean here arch/arm/mach-omap2/cclock3xxx_data.c?

Yegor


From jagarwal at nvidia.com  Wed May 29 06:10:17 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Wed, 29 May 2013 15:40:17 +0530
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
Message-ID: <C79B248886DD134989C8FF6B096A91AB91B616BE9B@BGMAIL01.nvidia.com>

> > > So, if I apply this series, I do see the PCIe bridge and Ethernet
> > > device get enumerated, but I don't see the USB3 controller get
> > > enumerated. I believe that is a PCIe device behind the same bridge
> > > on the
> > same Tegra PCIe port.
> > > Shouldn't this device show up?
> > I have also reproduced this problem. I see somehow no non-
> > prefetchable memory is assigned to any of pcie devices.
> > Probably that is the reason for USB3 (pci 0000:04:00.0) not getting
> > enumerated since it uses only non-prefetchable memory.
> 
> 1. Bus4(on which usb3 device resides) always return 0xffffffff from it's
> config space. which means device is not present?
> 2. That's why it is not assigned any resources and hence no usb3 probe
> happens.
> 3. But same bus does return valid info like vendor/device id etc from it's
> config space in downstream kernel and hence usb3 probe does happen.
> 
> Thierry, Stephen,
> 4. Any idea why bus4 should return 0xffffffff values in upstream kernel?
> Anything missing?
> 5. Also, how config space of all pcie devices are mapped? I mean if I change
> the config space offset in dts file, then also I find correct vendor/device id
> etc for bus0/device0/fun0.
>     So how this mapping happens that even after changing the config space
> offset in PCIe address space, it always finds correct vendor/device id.

 Any idea on this?


From mgr at pengutronix.de  Wed May 29 06:13:32 2013
From: mgr at pengutronix.de (Michael Grzeschik)
Date: Wed, 29 May 2013 12:13:32 +0200
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <F281D0F91ED19E4D8E63A7504E8A649803E8A4D0@039-SN2MPN1-021.039d.mgd.msft.net>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529075044.GC3293@lukather>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A4D0@039-SN2MPN1-021.039d.mgd.msft.net>
Message-ID: <20130529101332.GC7356@pengutronix.de>

Hi,

On Wed, May 29, 2013 at 08:07:55AM +0000, Chen Peter-B29397 wrote:
> 
>  
> > 
> > Indeed, I've been using the patchset "Add tested id switch and vbus
> > connect detect support for Chipidea" from Peter for quite some time on
> > top of 3.9 and it works like a charm for the gadget mode on an MX28
> > platform.
> > 
> > BTW, Peter, I've seen that these patches are still not merged in 3.10,
> > is there a reason for that? do you plan on sending a version rebased on
> > top of 3.10 some time in the future? I tried to do the rebasing myself,
> > but the chipidea driver seems to have changed quite heavily, which makes
> > the process quite difficult when you don't know what you're doing :)
> > 

we already have Peter's patches on v3.10-rc3 [1].

> I can spend few bandwidth on upstream work recently, I may have more
> bandwidth after June 15th. 
> 
> Currently, we still have no conclusion for chipidea core driver's coming work,
> like Device tree support, how to identify if the controller is OTG supported.

Yes, the next important step is getting the of propertys "dr_mode" and
"phy_type" properly used in the chipidea core.

[1] http://git.pengutronix.de/?p=mgr/linux.git;a=summary -> v3.10/topic/usb-peterchen

Regards,
Michael

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jason at lakedaemon.net  Wed May 29 06:14:28 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 06:14:28 -0400
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use
 DT for the PCIe interface
In-Reply-To: <20130529094236.619bd698@skate>
References: <8738t6ycnm.fsf@natisbad.org> <20130529002053.4b8ceb86@skate>
 <20130528223817.GL31290@titan.lakedaemon.net>
 <20130529094236.619bd698@skate>
Message-ID: <20130529101428.GN31290@titan.lakedaemon.net>

On Wed, May 29, 2013 at 09:42:36AM +0200, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 18:38:17 -0400, Jason Cooper wrote:
> 
> > > Could you check that you're running on top of the latest
> > > jcooper/mvebu/pcie branch? Thanks!
> > 
> > Actually, you want jcooper/mvebu/pcie_kirkwood.  I split out the
> > kirkwood driver so that if it causes a build breakage and gets dropped,
> > mvebu/pcie can still go in.
> 
> There's not really a "kirkwood" driver for PCIe. The pcie-kirkwood
> stuff is really all about adding the right Device Tree informations,
> and switching from a legacy-style probing to a DT-style probing.

Agreed.  Bad word choice on my part.  It was late/early, too much/too
little coffee. ;-)

You still need mvebu/pcie_kirkwood for:

  005625f pci: mvebu: enable driver usage on Kirkwood

thx,

Jason.


From gregory.clement at free-electrons.com  Wed May 29 06:16:55 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 May 2013 12:16:55 +0200
Subject: [PATCH 0/3] ARM: PJ4B: fixes for 3.10-rc
Message-ID: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>

Hello,

This path set allows to fix some errata for PJ4B CPus.

Without the first one, the Armada 370 based board can't boot anymore
since 3.10-rc1 and the commit "ARM: 7691/1: mm: kill unused
TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead" . So this one
really need to be appplied on 3.10-rc.

It should be a good thing to apply the others on the 3.10-rc, even we
didn't observe yet a problem related to these errata, they may happen.

Note that currently PJ4B is a symbol for 2 different CPU:

- the one used in Armada 370 is a PJ4B
- the ones used in Armada XP are actually PJ4B-MP

So I planed to introduce a new symbol PJ4B-MP but for 3.11 as it is
not related to a critical fix. Awaiting this new symbol I made the
errata depends on ARMADA_370 or ARMADA_XP in the Kconfig.

I will resent this series once Russell will come back next week, but I
would like to have a first feedback on this series.

Thanks,

Lior Amsalem (3):
  ARM PJ4B: Add support for errata 4742
  ARM PJ4B: Add support for errata 6124
  ARM PJ4B: Add support for errata 4611

 arch/arm/Kconfig                | 36 ++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++
 arch/arm/mm/cache-v7.S          |  8 ++++++++
 arch/arm/mm/copypage-v6.c       | 11 +++++++++++
 arch/arm/mm/proc-macros.S       | 13 +++++++++++++
 arch/arm/mm/proc-v7-2level.S    |  4 ++++
 arch/arm/mm/proc-v7-3level.S    |  4 ++++
 arch/arm/mm/proc-v7.S           |  7 +++++++
 8 files changed, 113 insertions(+)

-- 
1.8.1.2



From gregory.clement at free-electrons.com  Wed May 29 06:16:56 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 May 2013 12:16:56 +0200
Subject: [PATCH 1/3] ARM PJ4B: Add support for errata 4742
In-Reply-To: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1369822618-26797-2-git-send-email-gregory.clement@free-electrons.com>

From: Lior Amsalem <alior at marvell.com>

This commit fix the regression on Armada 370 (the kernal hang during
boot) introduced by the commit: "ARM: 7691/1: mm: kill unused
TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead".

When coming out of either a Wait for Interrupt (WFI) or a Wait for
Event (WFE) IDLE states, a specific timing sensitivity exists between
the retiring WFI/WFE instructions and the newly issued subsequent
instructions. This sensitivity can result in a CPU hang scenario.  The
workaround is to insert either a Data Synchronization Barrier (DSB) or
Data Memory Barrier (DMB) command immediately after the WFI/WFE
instruction

[gregory.clement at free-electrons.com:add errata description in changelog]
[gregory.clement at free-electrons.com:make this errata depend on Aramda
370]
Signed-off-by: Lior Amsalem <alior at marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig      | 12 ++++++++++++
 arch/arm/mm/proc-v7.S |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..745781f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1087,6 +1087,18 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config PJ4B_ERRATA_4742
+        bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
+        depends on CPU_PJ4B && MACH_ARMADA_370
+        help
+          When coming out of either a Wait for Interrupt (WFI) or a Wait for Event
+	  (WFE) IDLE states, a specific timing sensitivity exists between the retiring
+	  WFI/WFE instructions and the newly issued subsequent instructions.
+	  This sensitivity can result in a CPU hang scenario.
+          Workaround:
+	  The software must insert either a Data Synchronization Barrier (DSB)
+	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction
+
 config ARM_ERRATA_326103
 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 	depends on CPU_V6
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 2c73a73..f872432 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -71,6 +71,9 @@ ENDPROC(cpu_v7_reset)
 ENTRY(cpu_v7_do_idle)
 	dsb					@ WFI may enter a low-power mode
 	wfi
+#ifdef CONFIG_PJ4B_ERRATA_4742
+        mcr     p15, 0, r0, c7, c10, 4          @barrier
+#endif
 	mov	pc, lr
 ENDPROC(cpu_v7_do_idle)
 
-- 
1.8.1.2



From gregory.clement at free-electrons.com  Wed May 29 06:16:57 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 May 2013 12:16:57 +0200
Subject: [PATCH 2/3] ARM PJ4B: Add support for errata 6124
In-Reply-To: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1369822618-26797-3-git-send-email-gregory.clement@free-electrons.com>

From: Lior Amsalem <alior at marvell.com>

A rare timing scenario exists where a clean operation occurs, followed
by an additional store operation. If a matching snoop also occurs, it
is possible for the write-back from the original clean operation and
the intervention from the snoop to race, which could result in data
corruption.
Replacing all clean cache maintenance operations with Clean &
Invalidate operation to avoid the issue

[gregory.clement at free-electrons.com:add errata description in changelog]
[gregory.clement at free-electrons.com: make this errata depend on Aramda
XP]
Signed-off-by: Lior Amsalem <alior at marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig                | 13 +++++++++++++
 arch/arm/include/asm/tlbflush.h |  8 ++++++++
 arch/arm/mm/cache-v7.S          |  8 ++++++++
 arch/arm/mm/proc-v7-2level.S    |  4 ++++
 arch/arm/mm/proc-v7-3level.S    |  4 ++++
 arch/arm/mm/proc-v7.S           |  4 ++++
 6 files changed, 41 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 745781f..48cdbea 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1099,6 +1099,19 @@ config PJ4B_ERRATA_4742
 	  The software must insert either a Data Synchronization Barrier (DSB)
 	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction
 
+config PJ4B_ERRATA_6124
+        bool "PJ4B Errata 6124: Multiple writebacks can be issued in a rare timing scenario associated with a clean operation and an incoming snoop"
+        depends on CPU_PJ4B && MACH_ARMADA_XP
+        help
+	  A rare timing scenario exists where a clean operation occurs, followed
+	  by an additional store operation. If a matching snoop also occurs, it
+	  is possible for the write-back from the original clean operation and
+	  the intervention from the snoop to race, which could result in data
+	  corruption.
+	  Workaround:
+	  Replacing all clean cache maintenance operations with
+	  Clean & Invalidate operation will avoid the issue
+
 config ARM_ERRATA_326103
 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 	depends on CPU_V6
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d1..e3a8064 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -475,7 +475,11 @@ static inline void flush_pmd_entry(void *pmd)
 {
 	const unsigned int __tlb_flag = __cpu_tlb_flags;
 
+#ifdef CONFIG_PJ4B_ERRATA_6124
+	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
+#else
 	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
+#endif
 	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
 
 	if (tlb_flag(TLB_WB))
@@ -486,7 +490,11 @@ static inline void clean_pmd_entry(void *pmd)
 {
 	const unsigned int __tlb_flag = __cpu_tlb_flags;
 
+#ifdef CONFIG_PJ4B_ERRATA_6124
+	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
+#else
 	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
+#endif
 	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
 }
 
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 15451ee..d353649 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -270,7 +270,11 @@ ENTRY(v7_coherent_user_range)
 	ALT_UP(W(nop))
 #endif
 1:
+#ifdef CONFIG_PJ4B_ERRATA_6124
+ USER(	mcr	p15, 0, r12, c7, c14, 1	)	@ clean & invalidate D line to the point of unification
+#else
  USER(	mcr	p15, 0, r12, c7, c11, 1	)	@ clean D line to the point of unification
+#endif
 	add	r12, r12, r2
 	cmp	r12, r1
 	blo	1b
@@ -378,7 +382,11 @@ v7_dma_clean_range:
 	ALT_UP(W(nop))
 #endif
 1:
+#ifdef CONFIG_PJ4B_ERRATA_6124
+	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line to the point of unification
+#else
 	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
+#endif
 	add	r0, r0, r2
 	cmp	r0, r1
 	blo	1b
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 9704097..0999fd3 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -111,8 +111,12 @@ ENTRY(cpu_v7_set_pte_ext)
  THUMB(	add	r0, r0, #2048 )
  THUMB(	str	r3, [r0] )
 	ALT_SMP(mov	pc,lr)
+#ifdef CONFIG_PJ4B_ERRATA_6124
+	ALT_UP (mcr	p15, 0, r0, c7, c14, 1)		@ flush_pte by clean & invalidate D entry
+#else
 	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
 #endif
+#endif
 	mov	pc, lr
 ENDPROC(cpu_v7_set_pte_ext)
 
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 363027e..7a917ff 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -74,8 +74,12 @@ ENTRY(cpu_v7_set_pte_ext)
 	orreq	r2, #L_PTE_RDONLY
 1:	strd	r2, r3, [r0]
 	ALT_SMP(mov	pc, lr)
+#ifdef CONFIG_PJ4B_ERRATA_6124
+	ALT_UP (mcr	p15, 0, r0, c7, c14, 1)		@ flush_pte by clean & invalidate D entry
+#else
 	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
 #endif
+#endif
 	mov	pc, lr
 ENDPROC(cpu_v7_set_pte_ext)
 
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f872432..b86d688 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -81,7 +81,11 @@ ENTRY(cpu_v7_dcache_clean_area)
 	ALT_SMP(mov	pc, lr)			@ MP extensions imply L1 PTW
 	ALT_UP(W(nop))
 	dcache_line_size r2, r3
+#ifdef CONFIG_PJ4B_ERRATA_6124
+1:	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D entry
+#else
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+#endif
 	add	r0, r0, r2
 	subs	r1, r1, r2
 	bhi	1b
-- 
1.8.1.2



From gregory.clement at free-electrons.com  Wed May 29 06:16:58 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 May 2013 12:16:58 +0200
Subject: [PATCH 3/3] ARM PJ4B: Add support for errata 4611
In-Reply-To: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1369822618-26797-4-git-send-email-gregory.clement@free-electrons.com>

From: Lior Amsalem <alior at marvell.com>

A CP15 clean operation can result in a dead lock state if it is hit by
an incoming snoop event. the fiw to this issue is the following:
before any CP15 clean type operation in Cache Coherency mode, issue a
Data Memory Barrier (DMB) or a Data Synchronization Barrier (DSB)
instruction.

[gregory.clement at free-electrons.com:add errata description in changelog]
[gregory.clement at free-electrons.com:make this errata depend on Aramda
370]
Signed-off-by: Lior Amsalem <alior at marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig                | 11 +++++++++++
 arch/arm/include/asm/tlbflush.h | 22 ++++++++++++++++++++++
 arch/arm/mm/copypage-v6.c       | 11 +++++++++++
 arch/arm/mm/proc-macros.S       | 13 +++++++++++++
 4 files changed, 57 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 48cdbea..05c13f9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1087,6 +1087,17 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config PJ4B_ERRATA_4611
+        bool "PJ4B Errata 4611: A Deadlock can Occur if a CP15 Clean/Clean and Invalidate Operation is Hit By a Snoop Event"
+        depends on CPU_PJ4B && MACH_ARMADA_370
+        help
+          A CP15 clean operation can result in a dead lock state if it is hit by
+          an incoming snoop event.
+          Workaround:
+	  Before any CP15 clean type operation in Cache Coherency mode, issue
+          a Data Memory Barrier (DMB) or a Data Synchronization Barrier (DSB)
+          instruction.
+
 config PJ4B_ERRATA_4742
         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
         depends on CPU_PJ4B && MACH_ARMADA_370
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index e3a8064..112f778 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -475,11 +475,22 @@ static inline void flush_pmd_entry(void *pmd)
 {
 	const unsigned int __tlb_flag = __cpu_tlb_flags;
 
+#ifdef CONFIG_PJ4B_ERRATA_4611
+	unsigned long flags;
+	raw_local_irq_save(flags);
+	dmb();
+#endif
+
 #ifdef CONFIG_PJ4B_ERRATA_6124
 	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
 #else
 	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
 #endif
+
+#ifdef CONFIG_PJ4B_ERRATA_4611
+	raw_local_irq_restore(flags);
+#endif
+
 	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
 
 	if (tlb_flag(TLB_WB))
@@ -490,11 +501,22 @@ static inline void clean_pmd_entry(void *pmd)
 {
 	const unsigned int __tlb_flag = __cpu_tlb_flags;
 
+#ifdef CONFIG_PJ4B_ERRATA_4611
+	unsigned long flags;
+	raw_local_irq_save(flags);
+	dmb();
+#endif
+
 #ifdef CONFIG_PJ4B_ERRATA_6124
 	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
 #else
 	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
 #endif
+
+#ifdef CONFIG_PJ4B_ERRATA_4611
+	raw_local_irq_restore(flags);
+#endif
+
 	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
 }
 
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index b9bcc9d..20b69ad 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -59,11 +59,22 @@ static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long
  */
 static void discard_old_kernel_data(void *kto)
 {
+#ifdef CONFIG_PJ4B_ERRATA_4611
+        unsigned long flags;
+
+        raw_local_irq_save(flags);
+        dmb();
+#endif
+
 	__asm__("mcrr	p15, 0, %1, %0, c6	@ 0xec401f06"
 	   :
 	   : "r" (kto),
 	     "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
 	   : "cc");
+
+#ifdef CONFIG_PJ4B_ERRATA_4611
+        raw_local_irq_restore(flags);
+#endif
 }
 
 /*
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index f9a0aa7..ca81291 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -178,7 +178,20 @@
 #endif
 
 	str	r3, [r0]
+
+#ifdef CONFIG_PJ4B_ERRATA_4611
+	mrs     r2, cpsr
+	orr     r3, r2, #PSR_F_BIT | PSR_I_BIT
+	msr     cpsr_c, r3                      @ Disable interrupts
+	dmb                                     @ ensure ordering with previous memory accesses
+#endif
+
 	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
+
+#ifdef CONFIG_PJ4B_ERRATA_4611
+	msr     cpsr_c, r2                      @ Restore interrupts
+	mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+#endif
 	.endm
 
 
-- 
1.8.1.2



From Mylene.Josserand at navocap.com  Wed May 29 06:17:58 2013
From: Mylene.Josserand at navocap.com (Mylene Josserand)
Date: Wed, 29 May 2013 12:17:58 +0200
Subject: [I2C] informations + advice about messages handling
In-Reply-To: <20130524142017.52545a52@endymion.delvare>
References: <CA78C307B8F06747967D122FC656B153986448@SERVEUR0.nvp.local>
 <CAK7N6vpg6QUAKODKO2Msr4+GTASLDpA2cG1teQV3yiwt7D4SSw@mail.gmail.com>
 <20130524094407.61d0ec42@endymion.delvare>
 <CA78C307B8F06747967D122FC656B15398644A@SERVEUR0.nvp.local>
 <20130524110706.6052493e@endymion.delvare>
 <CA78C307B8F06747967D122FC656B15398644B@SERVEUR0.nvp.local>
 <20130524142017.52545a52@endymion.delvare>
Message-ID: <CA78C307B8F06747967D122FC656B15398645D@SERVEUR0.nvp.local>

Hi Jean,

Le 24/05/2013 14:20, Jean Delvare a ?crit :
> On Fri, 24 May 2013 11:52:54 +0200, Mylene Josserand wrote:
>> - an audio codec tlv320aic3204 : There is a driver for this device but
>> for some reasons, we did not use it. Did not find a "SMBus compliant" in
>> its datasheet.
>
> The tlv320aic32x4 driver uses i2c_master_send, which is a shortcut to
> i2c_transfer. However it seems to only send 2 bytes on the bus at once,
> the same could be achieved with i2c_smbus_write_byte_data if needed.

Okay, thanks to have looked at it !

>
> For completeness: a device might use transactions which are compliant
> with SMBus without being formally "SMBus-compliant", because SMBus has
> more constraints than just transaction types (I kept things simple
> originally to not confuse you.) This may explain why it isn't mentioned
> in the datasheet. Or just because the manufacturer did not care because
> they target fully I2C-capable systems anyway.
>
> What you have to look at is the transaction types. They are usually
> described in the datasheet. Then compare with either the SMBus
> specification or
> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/i2c/smbus-protocol
> and if they match then you can use the i2c_smbus_*() calls.


I have checked the PIC18F24201 according to your advice and, of what I 
have seen, it can handle the SMBus protocol.

Thank you for the explanation and trying to keep it simple for me :)


-- 
Myl?ne JOSSERAND


From catalin.marinas at arm.com  Wed May 29 06:37:28 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 29 May 2013 11:37:28 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <alpine.LFD.2.03.1305281340240.1918@syhkavp.arg>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
 <20130528095528.GA14329@arm.com>
 <alpine.LFD.2.03.1305281340240.1918@syhkavp.arg>
Message-ID: <20130529103728.GG17767@MacBook-Pro.local>

On Tue, May 28, 2013 at 06:52:27PM +0100, Nicolas Pitre wrote:
> On Tue, 28 May 2013, Catalin Marinas wrote:
> 
> > On Sat, May 25, 2013 at 04:53:19AM +0100, Nicolas Pitre wrote:
> > > On Thu, 23 May 2013, Catalin Marinas wrote:
> > > 
> > > > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > > > twice. I don't think we should remove the cache flushing in
> > > > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > > > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > > > don't work together).
> > > 
> > > VIVT and highmem do work together.  Highmem for ARM was in fact 
> > > developed on such a platform.
> > 
> > Thanks for confirming. Do you remember why kunmap() doesn't (need to)
> > flush the cache alias (for VIVT)? Or if it does, where?
> 
> kunmap() calls kunmap_high() which actually does not unmap anything but 
> only decrement a use count.  The page is kept around in case it is 
> kmap()'d again, in which case the kmap() will be almost free and the 
> page still warm.
> 
> It is only when the kmap() for a new page runs out of free pkmap  
> entries that the unused but still mapped pages are unmapped.  This 
> unmapping is done in flush_all_zero_pkmaps() where all the unused pages 
> are all unmapped at once.  The cache for all those pages is flushed with 
> flush_cache_kmaps() which on ARM maps to flush_cache_all() when the 
> cache is VIVT.

Thanks for clarification Nico. So if kmap_high_get() returns NULL, there
are no high aliases left in the cache.

-- 
Catalin


From viresh.kumar at linaro.org  Wed May 29 06:40:43 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Wed, 29 May 2013 16:10:43 +0530
Subject: [PATCH] cpufreq: MAINTAINERS: Add git tree path for ARM specific
 updates
Message-ID: <aab5b5dc92b960e81e8fd1975eba81234a4ecac8.1369817795.git.viresh.kumar@linaro.org>

To reduce cpufreq maintenance load on Rafael, ARM specific patches would be
Applied by me now. Rafael will pull in these changes from time to time (at
rc's). Additionally I would be sending him pull request for every merge window
and rc's (for fixes).

Web interface of my tree is present here:

https://git.linaro.org/gitweb?p=people/vireshk/linux.git;a=summary

Branch names would be: cpufreq-next and cpufreq-fixes.

Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fd3a495..50c81bd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2216,6 +2216,7 @@ L:	cpufreq at vger.kernel.org
 L:	linux-pm at vger.kernel.org
 S:	Maintained
 T:	git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
+T:	git://git.linaro.org/people/vireshk/linux.git (For ARM Updates)
 F:	drivers/cpufreq/
 F:	include/linux/cpufreq.h
 
-- 
1.7.12.rc2.18.g61b472e



From joe at perches.com  Wed May 29 06:47:02 2013
From: joe at perches.com (Joe Perches)
Date: Wed, 29 May 2013 03:47:02 -0700
Subject: [PATCH] cpufreq: MAINTAINERS: Add git tree path for ARM
 specific updates
In-Reply-To: <aab5b5dc92b960e81e8fd1975eba81234a4ecac8.1369817795.git.viresh.kumar@linaro.org>
References: <aab5b5dc92b960e81e8fd1975eba81234a4ecac8.1369817795.git.viresh.kumar@linaro.org>
Message-ID: <1369824422.22004.101.camel@joe-AO722>

On Wed, 2013-05-29 at 16:10 +0530, Viresh Kumar wrote:
> ARM specific patches would be
> Applied by me now. Rafael will pull in these changes from time to time (at
> rc's).
[]
> diff --git a/MAINTAINERS b/MAINTAINERS
[]
> @@ -2216,6 +2216,7 @@ L:	cpufreq at vger.kernel.org
[]
>  T:	git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
> +T:	git://git.linaro.org/people/vireshk/linux.git (For ARM Updates)

please prefix these with git

T:	git git://git.etc...

Every other T: git entry does.



From tixy at linaro.org  Wed May 29 06:48:24 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Wed, 29 May 2013 11:48:24 +0100
Subject: [PATCH 8/8] ARM: vexpress/dcscb: select multi-cluster SMP
 operations
In-Reply-To: <1369374311-21260-9-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-9-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369824504.3715.23.camel@linaro1.home>

On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> When the DCSCB code is successfully probed and initialized, then the
> generic MCPM SPM ops should be used as those operations need to be
> arbitrated through the MCPM layer.
> 
> Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
> ---
>  arch/arm/mach-vexpress/dcscb.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> index 1acc975360..ce3118dc05 100644
> --- a/arch/arm/mach-vexpress/dcscb.c
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -239,6 +239,8 @@ static int __init dcscb_init(void)
>  		return ret;
>  	}
>  
> +	mcpm_smp_set_ops();
> +

This is going to change the platform's smp_ops after setup_arch() has
already set them, is that OK and not too late?

I ask, because for me, RTSM doesn't boot the secondary CPUs if we rely
on this change to set the smp_ops, but having a hook in setup_arch() to
select instead of the standard vexpress ops does work.

I haven't investigated this more fully yet.
 
-- 
Tixy



From viresh.kumar at linaro.org  Wed May 29 06:54:55 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Wed, 29 May 2013 16:24:55 +0530
Subject: [PATCH] cpufreq: MAINTAINERS: Add git tree path for ARM specific
 updates
In-Reply-To: <1369824422.22004.101.camel@joe-AO722>
References: <aab5b5dc92b960e81e8fd1975eba81234a4ecac8.1369817795.git.viresh.kumar@linaro.org>
 <1369824422.22004.101.camel@joe-AO722>
Message-ID: <CAKohpomz4qOmhy-VRb2n0CY7YOr0vP3EGo88iXBhm2MzsJ8rrw@mail.gmail.com>

On 29 May 2013 16:17, Joe Perches <joe at perches.com> wrote:
> On Wed, 2013-05-29 at 16:10 +0530, Viresh Kumar wrote:
>> ARM specific patches would be
>> Applied by me now. Rafael will pull in these changes from time to time (at
>> rc's).
> []
>> diff --git a/MAINTAINERS b/MAINTAINERS
> []
>> @@ -2216,6 +2216,7 @@ L:      cpufreq at vger.kernel.org
> []
>>  T:   git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
>> +T:   git://git.linaro.org/people/vireshk/linux.git (For ARM Updates)
>
> please prefix these with git
>
> T:      git git://git.etc...
>
> Every other T: git entry does.
>

Thanks for reporting it.. below commit must be fixing it..
@Rafael: attached for you to apply.

----------x-------------------x------------------

From: Viresh Kumar <viresh.kumar at linaro.org>
Date: Wed, 29 May 2013 12:23:14 +0530
Subject: [PATCH] cpufreq: MAINTAINERS: Add git tree path for ARM specific
 updates

To reduce cpufreq maintenance load on Rafael, ARM specific patches would be
Applied by me now. Rafael will pull in these changes from time to time (at
rc's). Additionally I would be sending him pull request for every merge window
and rc's (for fixes).

Web interface of my tree is present here:

https://git.linaro.org/gitweb?p=people/vireshk/linux.git;a=summary

Branch names would be: cpufreq-next and cpufreq-fixes.

This also prefixes tree path with "git ".

Signed-off-by: Viresh Kumar <viresh.kumar at linaro.org>
---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fd3a495..92a6624 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2215,7 +2215,8 @@ M:	Viresh Kumar <viresh.kumar at linaro.org>
 L:	cpufreq at vger.kernel.org
 L:	linux-pm at vger.kernel.org
 S:	Maintained
-T:	git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
+T:	git git://git.linaro.org/people/vireshk/linux.git (For ARM Updates)
 F:	drivers/cpufreq/
 F:	include/linux/cpufreq.h
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From jason at lakedaemon.net  Wed May 29 07:03:44 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 07:03:44 -0400
Subject: [PATCH 0/3] ARM: PJ4B: fixes for 3.10-rc
In-Reply-To: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130529110344.GP31290@titan.lakedaemon.net>

Gregory,

On Wed, May 29, 2013 at 12:16:55PM +0200, Gregory CLEMENT wrote:
> Without the first one, the Armada 370 based board can't boot anymore
> since 3.10-rc1 and the commit "ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead" . So this one
> really need to be appplied on 3.10-rc.
> 
> It should be a good thing to apply the others on the 3.10-rc, even we
> didn't observe yet a problem related to these errata, they may happen.

Since Linus in encouraging smaller -rc's, we should probably just submit
the first patch to rmk's patch tracker for v3.10.  The other two should
be considered 'fixes-non-critical' for v3.11.

thx,

Jason.


From stefano.stabellini at eu.citrix.com  Wed May 29 07:03:26 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 29 May 2013 12:03:26 +0100
Subject: [PATCH v4 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <20130528181515.GB27718@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
 <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130528181515.GB27718@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1305291159220.4799@kaball.uk.xensource.com>

On Tue, 28 May 2013, Konrad Rzeszutek Wilk wrote:
> On Tue, May 28, 2013 at 06:54:29PM +0100, Stefano Stabellini wrote:
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > Acked-by: Ian Campbell <ian.campbell at citrix.com>
> > CC: konrad.wilk at oracle.com
> > 
> > Changes in v2:
> > - leave do_stolen_accounting in arch/x86/xen/time.c;
> > - use the new common functions in arch/ia64/xen/time.c.
> 
> So you also modify the function.

do_stolen_accounting? Just enought to call the new common function
xen_get_runstate_snapshot instead of the old x86 specific
get_runstate_snapshot.


> > ---
> >  arch/ia64/xen/time.c  |   48 +++----------------------
> >  arch/x86/xen/time.c   |   76 +----------------------------------------
> >  drivers/xen/Makefile  |    2 +-
> >  drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
> >  include/xen/xen-ops.h |    5 +++
> >  5 files changed, 104 insertions(+), 118 deletions(-)
> >  create mode 100644 drivers/xen/time.c
> > 
> > diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
> > index 1f8244a..79a0b8c 100644
> > --- a/arch/ia64/xen/time.c
> > +++ b/arch/ia64/xen/time.c
> > @@ -34,53 +34,17 @@
> >  
> >  #include "../kernel/fsyscall_gtod_data.h"
> >  
> > -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> >  static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
> >  static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
> >  
> >  /* taken from i386/kernel/time-xen.c */
> >  static void xen_init_missing_ticks_accounting(int cpu)
> >  {
> > -	struct vcpu_register_runstate_memory_area area;
> > -	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
> > -	int rc;
> > +	xen_setup_runstate_info(&runstate);
> >  
> > -	memset(runstate, 0, sizeof(*runstate));
> > -
> > -	area.addr.v = runstate;
> > -	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> > -				&area);
> > -	WARN_ON(rc && rc != -ENOSYS);
> > -
> > -	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
> > -	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
> > -					    + runstate->time[RUNSTATE_offline];
> > -}
> > -
> > -/*
> > - * Runstate accounting
> > - */
> > -/* stolen from arch/x86/xen/time.c */
> > -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> > -{
> > -	u64 state_time;
> > -	struct vcpu_runstate_info *state;
> > -
> > -	BUG_ON(preemptible());
> > -
> > -	state = &__get_cpu_var(xen_runstate);
> > -
> > -	/*
> > -	 * The runstate info is always updated by the hypervisor on
> > -	 * the current CPU, so there's no need to use anything
> > -	 * stronger than a compiler barrier when fetching it.
> > -	 */
> > -	do {
> > -		state_time = state->state_entry_time;
> > -		rmb();
> > -		*res = *state;
> > -		rmb();
> > -	} while (state->state_entry_time != state_time);
> > +	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
> > +	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
> > +					    + runstate.time[RUNSTATE_offline];
> >  }
> >  
> >  #define NS_PER_TICK (1000000000LL/HZ)
> > @@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
> >  	struct vcpu_runstate_info runstate;
> >  	struct task_struct *p = current;
> >  
> > -	get_runstate_snapshot(&runstate);
> > +	xen_get_runstate_snapshot(&runstate);
> >  
> >  	/*
> >  	 * Check for vcpu migration effect
> > @@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
> >  	 */
> >  	now = ia64_native_sched_clock();
> >  
> > -	get_runstate_snapshot(&runstate);
> > +	xen_get_runstate_snapshot(&runstate);
> >  
> >  	WARN_ON(runstate.state != RUNSTATE_running);
> >  
> > diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
> > index 3d88bfd..c0ca15e 100644
> > --- a/arch/x86/xen/time.c
> > +++ b/arch/x86/xen/time.c
> > @@ -30,9 +30,6 @@
> >  #define TIMER_SLOP	100000
> >  #define NS_PER_TICK	(1000000000LL / HZ)
> >  
> > -/* runstate info updated by Xen */
> > -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > -
> >  /* snapshots of runstate info */
> >  static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
> >  
> > @@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
> >  static DEFINE_PER_CPU(u64, xen_residual_stolen);
> >  static DEFINE_PER_CPU(u64, xen_residual_blocked);
> >  
> > -/* return an consistent snapshot of 64-bit time/counter value */
> > -static u64 get64(const u64 *p)
> > -{
> > -	u64 ret;
> > -
> > -	if (BITS_PER_LONG < 64) {
> > -		u32 *p32 = (u32 *)p;
> > -		u32 h, l;
> > -
> > -		/*
> > -		 * Read high then low, and then make sure high is
> > -		 * still the same; this will only loop if low wraps
> > -		 * and carries into high.
> > -		 * XXX some clean way to make this endian-proof?
> > -		 */
> > -		do {
> > -			h = p32[1];
> > -			barrier();
> > -			l = p32[0];
> > -			barrier();
> > -		} while (p32[1] != h);
> > -
> > -		ret = (((u64)h) << 32) | l;
> > -	} else
> > -		ret = *p;
> > -
> > -	return ret;
> > -}
> > -
> > -/*
> > - * Runstate accounting
> > - */
> > -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> > -{
> > -	u64 state_time;
> > -	struct vcpu_runstate_info *state;
> > -
> > -	BUG_ON(preemptible());
> > -
> > -	state = &__get_cpu_var(xen_runstate);
> > -
> > -	/*
> > -	 * The runstate info is always updated by the hypervisor on
> > -	 * the current CPU, so there's no need to use anything
> > -	 * stronger than a compiler barrier when fetching it.
> > -	 */
> > -	do {
> > -		state_time = get64(&state->state_entry_time);
> > -		barrier();
> > -		*res = *state;
> > -		barrier();
> > -	} while (get64(&state->state_entry_time) != state_time);
> > -}
> > -
> > -/* return true when a vcpu could run but has no real cpu to run on */
> > -bool xen_vcpu_stolen(int vcpu)
> > -{
> > -	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> > -}
> > -
> > -void xen_setup_runstate_info(int cpu)
> > -{
> > -	struct vcpu_register_runstate_memory_area area;
> > -
> > -	area.addr.v = &per_cpu(xen_runstate, cpu);
> > -
> > -	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > -			       cpu, &area))
> > -		BUG();
> > -}
> > -
> >  static void do_stolen_accounting(void)
> >  {
> >  	struct vcpu_runstate_info state;
> > @@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
> >  	s64 blocked, runnable, offline, stolen;
> >  	cputime_t ticks;
> >  
> > -	get_runstate_snapshot(&state);
> > +	xen_get_runstate_snapshot(&state);
> >  
> >  	WARN_ON(state.state != RUNSTATE_running);
> >  
> > diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
> > index eabd0ee..2bf461a 100644
> > --- a/drivers/xen/Makefile
> > +++ b/drivers/xen/Makefile
> > @@ -3,7 +3,7 @@ obj-y	+= manage.o
> >  obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
> >  endif
> >  obj-$(CONFIG_X86)			+= fallback.o
> > -obj-y	+= grant-table.o features.o events.o balloon.o
> > +obj-y	+= grant-table.o features.o events.o balloon.o time.o
> >  obj-y	+= xenbus/
> >  
> >  nostackp := $(call cc-option, -fno-stack-protector)
> > diff --git a/drivers/xen/time.c b/drivers/xen/time.c
> > new file mode 100644
> > index 0000000..c2e39d3
> > --- /dev/null
> > +++ b/drivers/xen/time.c
> > @@ -0,0 +1,91 @@
> > +/*
> > + * Xen stolen ticks accounting.
> > + */
> > +#include <linux/kernel.h>
> > +#include <linux/kernel_stat.h>
> > +#include <linux/math64.h>
> > +#include <linux/gfp.h>
> > +
> > +#include <asm/xen/hypervisor.h>
> > +#include <asm/xen/hypercall.h>
> > +
> > +#include <xen/events.h>
> > +#include <xen/features.h>
> > +#include <xen/interface/xen.h>
> > +#include <xen/interface/vcpu.h>
> > +#include <xen/xen-ops.h>
> > +
> > +/* runstate info updated by Xen */
> > +static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > +
> > +/* return an consistent snapshot of 64-bit time/counter value */
> > +static u64 get64(const u64 *p)
> > +{
> > +	u64 ret;
> > +
> > +	if (BITS_PER_LONG < 64) {
> > +		u32 *p32 = (u32 *)p;
> > +		u32 h, l;
> > +
> > +		/*
> > +		 * Read high then low, and then make sure high is
> > +		 * still the same; this will only loop if low wraps
> > +		 * and carries into high.
> > +		 * XXX some clean way to make this endian-proof?
> > +		 */
> > +		do {
> > +			h = p32[1];
> > +			barrier();
> > +			l = p32[0];
> > +			barrier();
> > +		} while (p32[1] != h);
> > +
> > +		ret = (((u64)h) << 32) | l;
> > +	} else
> > +		ret = *p;
> > +
> > +	return ret;
> > +}
> > +
> > +/*
> > + * Runstate accounting
> > + */
> > +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
> > +{
> > +	u64 state_time;
> > +	struct vcpu_runstate_info *state;
> > +
> > +	BUG_ON(preemptible());
> > +
> > +	state = &__get_cpu_var(xen_runstate);
> > +
> > +	/*
> > +	 * The runstate info is always updated by the hypervisor on
> > +	 * the current CPU, so there's no need to use anything
> > +	 * stronger than a compiler barrier when fetching it.
> > +	 */
> > +	do {
> > +		state_time = get64(&state->state_entry_time);
> > +		barrier();
> > +		*res = *state;
> > +		barrier();
> > +	} while (get64(&state->state_entry_time) != state_time);
> > +}
> > +
> > +/* return true when a vcpu could run but has no real cpu to run on */
> > +bool xen_vcpu_stolen(int vcpu)
> > +{
> > +	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> > +}
> > +
> > +void xen_setup_runstate_info(int cpu)
> > +{
> > +	struct vcpu_register_runstate_memory_area area;
> > +
> > +	area.addr.v = &per_cpu(xen_runstate, cpu);
> > +
> > +	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > +			       cpu, &area))
> > +		BUG();
> 
> The original code did:
> 
> -       rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> -                               &area);
> -       WARN_ON(rc && rc != -ENOSYS);
> -
> Any reason not to do this?

The original x86 code just BUGs out: I took that version over the ia64
version.


From will.deacon at arm.com  Wed May 29 07:03:59 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 12:03:59 +0100
Subject: [PATCH 1/3] ARM PJ4B: Add support for errata 4742
In-Reply-To: <1369822618-26797-2-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <1369822618-26797-2-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130529110359.GE13095@mudshark.cambridge.arm.com>

Hi Gregory,

On Wed, May 29, 2013 at 11:16:56AM +0100, Gregory CLEMENT wrote:
> From: Lior Amsalem <alior at marvell.com>
> 
> This commit fix the regression on Armada 370 (the kernal hang during
> boot) introduced by the commit: "ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead".
> 
> When coming out of either a Wait for Interrupt (WFI) or a Wait for
> Event (WFE) IDLE states, a specific timing sensitivity exists between
> the retiring WFI/WFE instructions and the newly issued subsequent
> instructions. This sensitivity can result in a CPU hang scenario.  The
> workaround is to insert either a Data Synchronization Barrier (DSB) or
> Data Memory Barrier (DMB) command immediately after the WFI/WFE
> instruction

Thanks for chasing this up! I have no idea why the patch you mentioned
triggered this though.

> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 2c73a73..f872432 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -71,6 +71,9 @@ ENDPROC(cpu_v7_reset)
>  ENTRY(cpu_v7_do_idle)
>  	dsb					@ WFI may enter a low-power mode
>  	wfi
> +#ifdef CONFIG_PJ4B_ERRATA_4742
> +        mcr     p15, 0, r0, c7, c10, 4          @barrier
> +#endif

Is the cp15 encoding required here, or can you just use `dsb'?

Will


From catalin.marinas at arm.com  Wed May 29 07:05:09 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 29 May 2013 12:05:09 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <20130529110508.GH17767@MacBook-Pro.local>

On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> it needs to handle are kernel mapped only.  However, for example when doing
> direct I/O, pages with user space mappings may occur.

After Nico's clarification, I think the original commit introducing this
function was also incomplete (commit 73be1591 - [ARM] 5545/2: add
flush_kernel_dcache_page() for ARM) since it ignores highmem pages and
their flushing could be deferred for a long time.

For my understanding (if I re-read this tread) - basically code like
this should not leave the user mapping inconsistent:

kmap()
...
flush_kernel_dcache_page()
kunmap()

If we use the atomic variants, we get the cache flushing automatically
but the kunmap_high() does not flush the cache immediately, so we need
to handle it in flush_kernel_dcache_page().

> Thus, continue to do lazy flushing if there are no user space mappings.
> Otherwise, flush the kernel cache lines directly.
...
>  /*
> + * Ensure cache coherency for kernel mapping of this page.
> + *
> + * If the page only exists in the page cache and there are no user
> + * space mappings, this is a no-op since the page was already marked
> + * dirty at creation.  Otherwise, we need to flush the dirty kernel
> + * cache lines directly.
> + */
> +void flush_kernel_dcache_page(struct page *page)
> +{
> +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> +		struct address_space *mapping;
> +
> +		mapping = page_mapping(page);
> +
> +		if (!mapping || mapping_mapped(mapping))
> +			__flush_kernel_dcache_page(page);
> +	}
> +}

BTW, does the mapping check optimise anything for the
flush_kernel_dcache_page() uses? Would we have a mapping anyway (or
anonymous page) in most cases?

Otherwise the patch looks good.

-- 
Catalin


From shawn.guo at linaro.org  Wed May 29 07:16:07 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 19:16:07 +0800
Subject: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts support
In-Reply-To: <1369732343-2982-5-git-send-email-b35083@freescale.com>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
 <1369732343-2982-5-git-send-email-b35083@freescale.com>
Message-ID: <20130529111605.GA25053@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 05:12:23PM +0800, Jingchang Lu wrote:
> +&fec0 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec0_1>;
> +	status = "okay";
> +};

I'm wondering if fec works fine on your side.  The kernel seems to halt
on the repeated phy messages below here when I boot the kernel with NFS.

Shawn

fec 400d0000.ethernet eth0: Freescale FEC PHY driver [Generic PHY]
(mii_bus:phy_addr=400d0000.etherne:00, irq=-1)
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
fec 400d1000.ethernet eth1: Freescale FEC PHY driver [Generic PHY]
(mii_bus:phy_addr=400d0000.etherne:01, irq=-1)
IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
libphy: 400d0000.etherne:01 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
Sending DHCP requests ., OK
IP-Config: Got DHCP answer from 192.168.1.1, my address is 192.168.1.102
IP-Config: Complete:
     device=eth0, hwaddr=00:04:9f:02:19:38, ipaddr=192.168.1.102,
mask=255.255.255.0, gw=192.168.1.1
     host=192.168.1.102, domain=domain, nis-domain=(none)
     bootserver=0.0.0.0, rootserver=192.168.1.100, rootpath=, mtu=576
     nameserver0=61.177.7.1, nameserver1=221.228.255.1
ALSA device list:
  No soundcards found.
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
...



From will.deacon at arm.com  Wed May 29 07:16:33 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 12:16:33 +0100
Subject: [PATCH 2/3] ARM PJ4B: Add support for errata 6124
In-Reply-To: <1369822618-26797-3-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <1369822618-26797-3-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130529111633.GF13095@mudshark.cambridge.arm.com>

On Wed, May 29, 2013 at 11:16:57AM +0100, Gregory CLEMENT wrote:
> From: Lior Amsalem <alior at marvell.com>
> 
> A rare timing scenario exists where a clean operation occurs, followed
> by an additional store operation. If a matching snoop also occurs, it
> is possible for the write-back from the original clean operation and
> the intervention from the snoop to race, which could result in data
> corruption.
> Replacing all clean cache maintenance operations with Clean &
> Invalidate operation to avoid the issue

Curious: do you not have a chicken bit for this? Upgrading clean to clean &
invalidate is a pretty common thing to do and is even architected with the
virtualisation extensions.

> [gregory.clement at free-electrons.com:add errata description in changelog]
> [gregory.clement at free-electrons.com: make this errata depend on Aramda
> XP]
> Signed-off-by: Lior Amsalem <alior at marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/Kconfig                | 13 +++++++++++++
>  arch/arm/include/asm/tlbflush.h |  8 ++++++++
>  arch/arm/mm/cache-v7.S          |  8 ++++++++
>  arch/arm/mm/proc-v7-2level.S    |  4 ++++
>  arch/arm/mm/proc-v7-3level.S    |  4 ++++
>  arch/arm/mm/proc-v7.S           |  4 ++++
>  6 files changed, 41 insertions(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 745781f..48cdbea 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1099,6 +1099,19 @@ config PJ4B_ERRATA_4742
>  	  The software must insert either a Data Synchronization Barrier (DSB)
>  	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction
>  
> +config PJ4B_ERRATA_6124
> +        bool "PJ4B Errata 6124: Multiple writebacks can be issued in a rare timing scenario associated with a clean operation and an incoming snoop"
> +        depends on CPU_PJ4B && MACH_ARMADA_XP
> +        help
> +	  A rare timing scenario exists where a clean operation occurs, followed
> +	  by an additional store operation. If a matching snoop also occurs, it
> +	  is possible for the write-back from the original clean operation and
> +	  the intervention from the snoop to race, which could result in data
> +	  corruption.
> +	  Workaround:
> +	  Replacing all clean cache maintenance operations with
> +	  Clean & Invalidate operation will avoid the issue
> +
>  config ARM_ERRATA_326103
>  	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
>  	depends on CPU_V6
> diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
> index a3625d1..e3a8064 100644
> --- a/arch/arm/include/asm/tlbflush.h
> +++ b/arch/arm/include/asm/tlbflush.h
> @@ -475,7 +475,11 @@ static inline void flush_pmd_entry(void *pmd)
>  {
>  	const unsigned int __tlb_flag = __cpu_tlb_flags;
>  
> +#ifdef CONFIG_PJ4B_ERRATA_6124
> +	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);

Can you elaborate on the comment please?

> +#else
>  	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
> +#endif
>  	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
>  
>  	if (tlb_flag(TLB_WB))
> @@ -486,7 +490,11 @@ static inline void clean_pmd_entry(void *pmd)
>  {
>  	const unsigned int __tlb_flag = __cpu_tlb_flags;
>  
> +#ifdef CONFIG_PJ4B_ERRATA_6124
> +	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);

and here.

> +#else
>  	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
> +#endif
>  	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
>  }
>  
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index 15451ee..d353649 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -270,7 +270,11 @@ ENTRY(v7_coherent_user_range)
>  	ALT_UP(W(nop))
>  #endif
>  1:
> +#ifdef CONFIG_PJ4B_ERRATA_6124
> + USER(	mcr	p15, 0, r12, c7, c14, 1	)	@ clean & invalidate D line to the point of unification

This flushes to the point of coherency (there is no PoU clean & inv).

> +#else
>   USER(	mcr	p15, 0, r12, c7, c11, 1	)	@ clean D line to the point of unification
> +#endif
>  	add	r12, r12, r2
>  	cmp	r12, r1
>  	blo	1b
> @@ -378,7 +382,11 @@ v7_dma_clean_range:
>  	ALT_UP(W(nop))
>  #endif
>  1:
> +#ifdef CONFIG_PJ4B_ERRATA_6124
> +	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line to the point of unification

Similarly, although I don't understand why you care about the erratum for
dma_clean_range. There should be no pending stores to the buffer, otherwise
you risk corruption anyway (from the device's point of view).

> +#else
>  	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
> +#endif
>  	add	r0, r0, r2
>  	cmp	r0, r1
>  	blo	1b
> diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
> index 9704097..0999fd3 100644
> --- a/arch/arm/mm/proc-v7-2level.S
> +++ b/arch/arm/mm/proc-v7-2level.S
> @@ -111,8 +111,12 @@ ENTRY(cpu_v7_set_pte_ext)
>   THUMB(	add	r0, r0, #2048 )
>   THUMB(	str	r3, [r0] )
>  	ALT_SMP(mov	pc,lr)
> +#ifdef CONFIG_PJ4B_ERRATA_6124
> +	ALT_UP (mcr	p15, 0, r0, c7, c14, 1)		@ flush_pte by clean & invalidate D entry

The use of `by' is a bit confusing, since you can also do maintenance by
set/way.

> +#else
>  	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
>  #endif
> +#endif
>  	mov	pc, lr
>  ENDPROC(cpu_v7_set_pte_ext)
>  
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 363027e..7a917ff 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -74,8 +74,12 @@ ENTRY(cpu_v7_set_pte_ext)
>  	orreq	r2, #L_PTE_RDONLY
>  1:	strd	r2, r3, [r0]
>  	ALT_SMP(mov	pc, lr)
> +#ifdef CONFIG_PJ4B_ERRATA_6124
> +	ALT_UP (mcr	p15, 0, r0, c7, c14, 1)		@ flush_pte by clean & invalidate D entry
> +#else
>  	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
>  #endif
> +#endif
>  	mov	pc, lr
>  ENDPROC(cpu_v7_set_pte_ext)
>  
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index f872432..b86d688 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -81,7 +81,11 @@ ENTRY(cpu_v7_dcache_clean_area)
>  	ALT_SMP(mov	pc, lr)			@ MP extensions imply L1 PTW
>  	ALT_UP(W(nop))
>  	dcache_line_size r2, r3

You could move the 1: label here.

> +#ifdef CONFIG_PJ4B_ERRATA_6124
> +1:	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D entry
> +#else
>  1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
> +#endif

Will


From broonie at kernel.org  Wed May 29 07:20:02 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 29 May 2013 12:20:02 +0100
Subject: [PATCH] SPI: Unify simple platform data for some controllers
In-Reply-To: <1369817353.993218858@f175.mail.ru>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <1743419.NY2Q01i8Iq@wuerfel> <1369817353.993218858@f175.mail.ru>
Message-ID: <20130529112002.GS3660@sirena.org.uk>

On Wed, May 29, 2013 at 12:49:13PM +0400, Alexander Shiyan wrote:
> > On Wednesday 29 May 2013 10:42:22 Alexander Shiyan wrote:

> > Wouldn't it be better to kill off the platform_data for these drivers
> > and pass the gpio number through spi->controller_data as the
> > spi_gpio driver does?

> Interesting way. Just one question remains, for using not-dt variant,
> how  we should specify num_chipselect parameter for master?
> I see only way for specify maximum constant in the driver.

We should fix that to be dynamic, having a fixed number is not sensible
when GPIOs are usable for chip select.  We probably also want to make
GPIO chip select support a standard thing that's available with every
driver rather than something the driver has to know about but that's a
separate bit of work.
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From dmurphy at ti.com  Wed May 29 07:20:27 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Wed, 29 May 2013 06:20:27 -0500
Subject: [PATCH v7] ARM: dts: omap4-panda: Update the LED support for the
 panda DTS
Message-ID: <1369826427-31963-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/

 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..5fd59b3 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <
+			&led_wkgpio_pins
+		>;
+
 		heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 0>;
@@ -137,6 +142,15 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
+			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c968a3b 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
 		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
 		>;
 };
+
+&omap4_pmx_core {
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
+&led_wkgpio_pins {
+	pinctrl-single,pins = <
+		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
+	>;
+};
+
+&leds {
+	pinctrl-0 = <
+		&led_gpio_pins
+		&led_wkgpio_pins
+	>;
+
+	heartbeat {
+		gpios = <&gpio4 14 0>;
+	};
+	mmc {
+		gpios = <&gpio1 8 0>;
+	};
+};
-- 
1.7.5.4



From will.deacon at arm.com  Wed May 29 07:22:07 2013
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 May 2013 12:22:07 +0100
Subject: [PATCH 3/3] ARM PJ4B: Add support for errata 4611
In-Reply-To: <1369822618-26797-4-git-send-email-gregory.clement@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <1369822618-26797-4-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20130529112207.GG13095@mudshark.cambridge.arm.com>

On Wed, May 29, 2013 at 11:16:58AM +0100, Gregory CLEMENT wrote:
> From: Lior Amsalem <alior at marvell.com>
> 
> A CP15 clean operation can result in a dead lock state if it is hit by
> an incoming snoop event. the fiw to this issue is the following:

s/fiw/fix/

> before any CP15 clean type operation in Cache Coherency mode, issue a
> Data Memory Barrier (DMB) or a Data Synchronization Barrier (DSB)
> instruction.

Could you combine this with #6124, so we don't have back-to-back ifdefs all
over the place? Also, there are more clean operations than you have
described here, so why haven't you have to touch them all?

> [gregory.clement at free-electrons.com:add errata description in changelog]
> [gregory.clement at free-electrons.com:make this errata depend on Aramda
> 370]
> Signed-off-by: Lior Amsalem <alior at marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> ---
>  arch/arm/Kconfig                | 11 +++++++++++
>  arch/arm/include/asm/tlbflush.h | 22 ++++++++++++++++++++++
>  arch/arm/mm/copypage-v6.c       | 11 +++++++++++
>  arch/arm/mm/proc-macros.S       | 13 +++++++++++++
>  4 files changed, 57 insertions(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 48cdbea..05c13f9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1087,6 +1087,17 @@ if !MMU
>  source "arch/arm/Kconfig-nommu"
>  endif
>  
> +config PJ4B_ERRATA_4611
> +        bool "PJ4B Errata 4611: A Deadlock can Occur if a CP15 Clean/Clean and Invalidate Operation is Hit By a Snoop Event"
> +        depends on CPU_PJ4B && MACH_ARMADA_370
> +        help
> +          A CP15 clean operation can result in a dead lock state if it is hit by
> +          an incoming snoop event.
> +          Workaround:
> +	  Before any CP15 clean type operation in Cache Coherency mode, issue
> +          a Data Memory Barrier (DMB) or a Data Synchronization Barrier (DSB)
> +          instruction.
> +
>  config PJ4B_ERRATA_4742
>          bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
>          depends on CPU_PJ4B && MACH_ARMADA_370
> diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
> index e3a8064..112f778 100644
> --- a/arch/arm/include/asm/tlbflush.h
> +++ b/arch/arm/include/asm/tlbflush.h
> @@ -475,11 +475,22 @@ static inline void flush_pmd_entry(void *pmd)
>  {
>  	const unsigned int __tlb_flag = __cpu_tlb_flags;
>  
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +	unsigned long flags;
> +	raw_local_irq_save(flags);
> +	dmb();
> +#endif
> +
>  #ifdef CONFIG_PJ4B_ERRATA_6124
>  	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
>  #else
>  	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
>  #endif
> +
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +	raw_local_irq_restore(flags);
> +#endif

Eeek. Why do you have to disable interrupts during this? Again, are there no
chicken bits to save you?

>  	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
>  
>  	if (tlb_flag(TLB_WB))
> @@ -490,11 +501,22 @@ static inline void clean_pmd_entry(void *pmd)
>  {
>  	const unsigned int __tlb_flag = __cpu_tlb_flags;
>  
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +	unsigned long flags;
> +	raw_local_irq_save(flags);
> +	dmb();
> +#endif
> +
>  #ifdef CONFIG_PJ4B_ERRATA_6124
>  	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
>  #else
>  	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
>  #endif
> +
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +	raw_local_irq_restore(flags);
> +#endif
> +
>  	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
>  }
>  
> diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
> index b9bcc9d..20b69ad 100644
> --- a/arch/arm/mm/copypage-v6.c
> +++ b/arch/arm/mm/copypage-v6.c
> @@ -59,11 +59,22 @@ static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long
>   */
>  static void discard_old_kernel_data(void *kto)
>  {
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +        unsigned long flags;
> +
> +        raw_local_irq_save(flags);
> +        dmb();
> +#endif
> +
>  	__asm__("mcrr	p15, 0, %1, %0, c6	@ 0xec401f06"
>  	   :
>  	   : "r" (kto),
>  	     "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
>  	   : "cc");
> +
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +        raw_local_irq_restore(flags);
> +#endif

Do you actually have an aliasing vipt cache? If not, you don't care about
this function.

> diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
> index f9a0aa7..ca81291 100644
> --- a/arch/arm/mm/proc-macros.S
> +++ b/arch/arm/mm/proc-macros.S
> @@ -178,7 +178,20 @@
>  #endif
>  
>  	str	r3, [r0]
> +
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +	mrs     r2, cpsr
> +	orr     r3, r2, #PSR_F_BIT | PSR_I_BIT
> +	msr     cpsr_c, r3                      @ Disable interrupts
> +	dmb                                     @ ensure ordering with previous memory accesses
> +#endif
> +
>  	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
> +
> +#ifdef CONFIG_PJ4B_ERRATA_4611
> +	msr     cpsr_c, r2                      @ Restore interrupts
> +	mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
> +#endif

This could be a dsb.

Will


From jason at lakedaemon.net  Wed May 29 07:48:46 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 07:48:46 -0400
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use
 DT for the PCIe interface
In-Reply-To: <8738t6ycnm.fsf@natisbad.org>
References: <8738t6ycnm.fsf@natisbad.org>
Message-ID: <20130529114846.GQ31290@titan.lakedaemon.net>

On Wed, May 29, 2013 at 12:15:09AM +0200, Arnaud Ebalard wrote:
> Hi Jason and Thomas,
> 
> Thomas, I am following your work on PCIe support for a .dts file I am
> working on for (Armada 370-based) Netgear ReadyNAS 102 and noticed your
> set of patches to convert kirkwood-based boards to use it in order to
> simplify/remove board specific code.
> 
> Jason, I gave your associated branch (jcooper/mvebu-next/pcie) a try
> with following patch applied and can confirm USB 3.0 host controller
> (connected to PCIe bus) is usable on Netgear ReadyNAS *Duo v2*
> (88f6282-based brother of the 102).
> 
> Note that I had to s/of_pci_range_parser()/of_pci_range_parser_init()/
> in drivers/pci/host/pci-mvebu.c to compile the kernel (this may already
> have been fixed already):
> 
> CHK     kernel/config_data.h
> drivers/pci/host/pci-mvebu.c: In function ?mvebu_pcie_probe?:
> drivers/pci/host/pci-mvebu.c:742:2: error: implicit declaration of function ?of_pci_range_parser? [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
> make[3]: *** [drivers/pci/host/pci-mvebu.o] Error 1
> make[2]: *** [drivers/pci/host] Error 2
> make[1]: *** [drivers/pci] Error 2
> make[1]: *** Waiting for unfinished jobs....
> 
> Can one of you take the patch below into account? Or 
> 
> Cheers,
> 
> a+
> 
> Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
> ---
>  arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts |    8 ++++++++
>  arch/arm/mach-kirkwood/board-readynas.c                |    1 -
>  2 files changed, 8 insertions(+), 1 deletion(-)

Hey, I had a little time to kill, so I went ahead and fixed this up.
Let me know if this looks ok.  I've applied it to mvebu/pcie_kirkwood,
so you should just be able to pull that and test it.  I'll push it up to
arm-soc in a week or so.

thx,

Jason.

---->8-----
commit 6bd98481ab346964344e05a041f35ff83cb3d00c
Author: Arnaud Ebalard <arno at natisbad.org>
Date:   Wed May 29 11:37:52 2013 +0000

    arm: kirkwood: NETGEAR ReadyNAS Duo v2 init PCIe via DT
    
    Now that the mvebu-pcie driver is in place and enabled for kirkwood,
    convert to initializing PCIe via devicetree.
    
    Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
    Signed-off-by: Jason Cooper <jason at lakedaemon.net>

diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab..0f852b4 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -111,6 +111,14 @@
 			status = "okay";
 			nr-ports = <2>;
 		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
 	};
 
 	gpio-leds {
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20..341b82d 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
 void __init netgear_readynas_init(void)
 {
 	kirkwood_ge00_init(&netgear_readynas_ge00_data);
-	kirkwood_pcie_init(KW_PCIE0);
 }


From linus.walleij at linaro.org  Wed May 29 07:57:33 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 13:57:33 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <20130528162715.GB28253@arwen.pp.htv.fi>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <CACRpkdYjjDp+7hzGtAchyy3+5Vxc8jK5THGCETkAO_V9Hj9Ssw@mail.gmail.com>
 <20130528162715.GB28253@arwen.pp.htv.fi>
Message-ID: <CACRpkdZn14Gn-YEeHJHre6Sr4JU-xjOeLFgM8OjX7M5qnKudTg@mail.gmail.com>

On Tue, May 28, 2013 at 6:27 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:

>> I can't merge any of this without Felipes ACKs in any
>> case.
>
> Do you want to take this yourself ? I haven't fully read the series yet,
> but seems like this depends on the rest of the series. If you want to
> take it, let me know I can ack the patches as soon as I'm done
> reviewing.

Yes please. They are dependent on a stash of patches that that
has recently landed in the ARM SoC tree, so currently they need
to follow those through the same tree, which is where I funnel
all the ux500 stuff.

Yours,
Linus Walleij


From ulf.hansson at linaro.org  Wed May 29 08:01:54 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 29 May 2013 14:01:54 +0200
Subject: [PATCH V3 1/3] mmc: Add size for caller in init+register
In-Reply-To: <1369790016-13270-1-git-send-email-csd@broadcom.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
Message-ID: <CAPDyKFoPO0KTfW_i1EP8urSUT+U8yEaafrE2HdN2mmEkYCZm-w@mail.gmail.com>

On 29 May 2013 03:13, Christian Daudt <csd at broadcom.com> wrote:
> Add a param to allow users of sdhci_pltfm to allocate private space
> in calls to sdhci_pltfm_init+sdhci_pltfm_register. This is implemented
> in the same way as sdhci does for its users.
>  None of the users have been migrated yet and are passing in zero to
> retain their private allocation.
>
> - todo: migrate clients to using allocation this way
> - todo: remove priv variable once migration is complete
>
> Also removed unused variable in sdhci_pltfm_init fn
>
> Signed-off-by: Christian Daudt <csd at broadcom.com>

Hi Christian,

Sorry if being a bit picky, do you mind using "mmc: sdhci" as the
prefix for the heading of this patch?

>
> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
> index d49bc95..0584a1c 100644
> --- a/drivers/mmc/host/sdhci-bcm2835.c
> +++ b/drivers/mmc/host/sdhci-bcm2835.c
> @@ -148,7 +148,7 @@ static int bcm2835_sdhci_probe(struct platform_device *pdev)
>         struct sdhci_pltfm_host *pltfm_host;
>         int ret;
>
> -       host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata);
> +       host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata, 0);
>         if (IS_ERR(host))
>                 return PTR_ERR(host);
>
> diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c
> index 8ebb6b6..f2cc266 100644
> --- a/drivers/mmc/host/sdhci-cns3xxx.c
> +++ b/drivers/mmc/host/sdhci-cns3xxx.c
> @@ -96,7 +96,7 @@ static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
>
>  static int sdhci_cns3xxx_probe(struct platform_device *pdev)
>  {
> -       return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata);
> +       return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
>  }
>
>  static int sdhci_cns3xxx_remove(struct platform_device *pdev)
> diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c
> index 15e7803..8424839 100644
> --- a/drivers/mmc/host/sdhci-dove.c
> +++ b/drivers/mmc/host/sdhci-dove.c
> @@ -130,7 +130,7 @@ static int sdhci_dove_probe(struct platform_device *pdev)
>                 gpio_direction_input(priv->gpio_cd);
>         }
>
> -       host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata);
> +       host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata, 0);
>         if (IS_ERR(host)) {
>                 ret = PTR_ERR(host);
>                 goto err_sdhci_pltfm_init;
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 67d6dde..9a1e6fa 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -470,7 +470,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>         int err;
>         struct pltfm_imx_data *imx_data;
>
> -       host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
> +       host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
>         if (IS_ERR(host))
>                 return PTR_ERR(host);
>
> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
> index 5e68adc..37e668f 100644
> --- a/drivers/mmc/host/sdhci-of-esdhc.c
> +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> @@ -262,7 +262,7 @@ static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
>
>  static int sdhci_esdhc_probe(struct platform_device *pdev)
>  {
> -       return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
> +       return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata, 0);
>  }
>
>  static int sdhci_esdhc_remove(struct platform_device *pdev)
> diff --git a/drivers/mmc/host/sdhci-of-hlwd.c b/drivers/mmc/host/sdhci-of-hlwd.c
> index 200a6a9..57c514a 100644
> --- a/drivers/mmc/host/sdhci-of-hlwd.c
> +++ b/drivers/mmc/host/sdhci-of-hlwd.c
> @@ -68,7 +68,7 @@ static const struct sdhci_pltfm_data sdhci_hlwd_pdata = {
>
>  static int sdhci_hlwd_probe(struct platform_device *pdev)
>  {
> -       return sdhci_pltfm_register(pdev, &sdhci_hlwd_pdata);
> +       return sdhci_pltfm_register(pdev, &sdhci_hlwd_pdata, 0);
>  }
>
>  static int sdhci_hlwd_remove(struct platform_device *pdev)
> diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
> index cd0f1f6..38e38a5 100644
> --- a/drivers/mmc/host/sdhci-pltfm.c
> +++ b/drivers/mmc/host/sdhci-pltfm.c
> @@ -115,10 +115,10 @@ void sdhci_get_of_property(struct platform_device *pdev) {}
>  EXPORT_SYMBOL_GPL(sdhci_get_of_property);
>
>  struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
> -                                   const struct sdhci_pltfm_data *pdata)
> +                                   const struct sdhci_pltfm_data *pdata,
> +                                   size_t priv_size)
>  {
>         struct sdhci_host *host;
> -       struct sdhci_pltfm_host *pltfm_host;
>         struct device_node *np = pdev->dev.of_node;
>         struct resource *iomem;
>         int ret;
> @@ -134,17 +134,17 @@ struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
>
>         /* Some PCI-based MFD need the parent here */
>         if (pdev->dev.parent != &platform_bus && !np)
> -               host = sdhci_alloc_host(pdev->dev.parent, sizeof(*pltfm_host));
> +               host = sdhci_alloc_host(pdev->dev.parent,
> +                       sizeof(struct sdhci_pltfm_host) + priv_size);
>         else
> -               host = sdhci_alloc_host(&pdev->dev, sizeof(*pltfm_host));
> +               host = sdhci_alloc_host(&pdev->dev,
> +                       sizeof(struct sdhci_pltfm_host) + priv_size);
>
>         if (IS_ERR(host)) {
>                 ret = PTR_ERR(host);
>                 goto err;
>         }
>
> -       pltfm_host = sdhci_priv(host);
> -
>         host->hw_name = dev_name(&pdev->dev);
>         if (pdata && pdata->ops)
>                 host->ops = pdata->ops;
> @@ -202,12 +202,13 @@ void sdhci_pltfm_free(struct platform_device *pdev)
>  EXPORT_SYMBOL_GPL(sdhci_pltfm_free);
>
>  int sdhci_pltfm_register(struct platform_device *pdev,
> -                        const struct sdhci_pltfm_data *pdata)
> +                       const struct sdhci_pltfm_data *pdata,
> +                       size_t priv_size)
>  {
>         struct sdhci_host *host;
>         int ret = 0;
>
> -       host = sdhci_pltfm_init(pdev, pdata);
> +       host = sdhci_pltfm_init(pdev, pdata, priv_size);
>         if (IS_ERR(host))
>                 return PTR_ERR(host);
>
> diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
> index 1210ed1..ed4a85d 100644
> --- a/drivers/mmc/host/sdhci-pltfm.h
> +++ b/drivers/mmc/host/sdhci-pltfm.h
> @@ -27,6 +27,8 @@ struct sdhci_pltfm_host {
>         /* migrate from sdhci_of_host */
>         unsigned int clock;
>         u16 xfer_mode_shadow;
> +
> +       unsigned long private[0] ____cacheline_aligned;

Why do you need this to be "____cacheline_aligned"?

>  };
>
>  #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
> @@ -91,15 +93,22 @@ static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
>  extern void sdhci_get_of_property(struct platform_device *pdev);
>
>  extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
> -                                         const struct sdhci_pltfm_data *pdata);
> +                                         const struct sdhci_pltfm_data *pdata,
> +                                         size_t priv_size);
>  extern void sdhci_pltfm_free(struct platform_device *pdev);
>
>  extern int sdhci_pltfm_register(struct platform_device *pdev,
> -                               const struct sdhci_pltfm_data *pdata);
> +                               const struct sdhci_pltfm_data *pdata,
> +                               size_t priv_size);
>  extern int sdhci_pltfm_unregister(struct platform_device *pdev);
>
>  extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
>
> +static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
> +{
> +       return (void *)host->private;
> +}
> +
>  #ifdef CONFIG_PM
>  extern const struct dev_pm_ops sdhci_pltfm_pmops;
>  #define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops)
> diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
> index 6a3f702..1cf093f 100644
> --- a/drivers/mmc/host/sdhci-pxav2.c
> +++ b/drivers/mmc/host/sdhci-pxav2.c
> @@ -175,7 +175,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
>         if (!pxa)
>                 return -ENOMEM;
>
> -       host = sdhci_pltfm_init(pdev, NULL);
> +       host = sdhci_pltfm_init(pdev, NULL, 0);
>         if (IS_ERR(host)) {
>                 kfree(pxa);
>                 return PTR_ERR(host);
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 1ae358e..9124104 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -230,7 +230,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>         if (!pxa)
>                 return -ENOMEM;
>
> -       host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata);
> +       host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
>         if (IS_ERR(host)) {
>                 kfree(pxa);
>                 return PTR_ERR(host);
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index e0dba74..c8b0582 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -231,7 +231,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
>                 return -EINVAL;
>         soc_data = match->data;
>
> -       host = sdhci_pltfm_init(pdev, soc_data->pdata);
> +       host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
>         if (IS_ERR(host))
>                 return PTR_ERR(host);
>         pltfm_host = sdhci_priv(host);
> --
> 1.7.10.4
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Kind regards
Ulf Hansson


From tushar.behera at linaro.org  Wed May 29 08:03:03 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 May 2013 17:33:03 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
Message-ID: <51A5EE77.6040503@linaro.org>

On 05/29/2013 11:01 AM, Olof Johansson wrote:
>> There are a total of 6 patches on top of
>> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
>> (c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
>> (e, f) are required to reset the hub during EHCI initialization.
> 
> Huh, I thought you said that (c) wasn't needed when I posted the
> defconfig update. It'd be nice to see the code fixed to handle this
> case instead of Linaro carrying a patch like this though. I.e. make it
> able to deselect the uart, or make it tied to DEBUG_LL like on other
> platforms instead of having a separate config for this.
> 

I am working on this approach so that we can consolidate both the UART
port macros together and tie them to DEBUG_LL. I would post the patch
tomorrow.

>> a. ARM: exynos: defconfig update
>> b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
>> c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
>> d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
>> e. usb: ehci-s5p: add the HSIC port initialization
>> f. ARM: dts: Add USB gpio entries for Arndale board


-- 
Tushar Behera


From linus.walleij at linaro.org  Wed May 29 08:04:18 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 14:04:18 +0200
Subject: build failure: linux-next: ARM defconfig: u8500
In-Reply-To: <CAGa+x84p1pVuFm_MuQVTCJq_50NTsjKtWUFAbQ0W_=beOcA55A@mail.gmail.com>
References: <CAGa+x87czosA=tWh1KRTSSqMyLckMHwNP7hrRXdokaLsSaaikA@mail.gmail.com>
 <CAGa+x84p1pVuFm_MuQVTCJq_50NTsjKtWUFAbQ0W_=beOcA55A@mail.gmail.com>
Message-ID: <CACRpkdZ1mRyhvnqaiNGQkprt_WEUdpz5+N09s3hB=GjJme73vw@mail.gmail.com>

On Wed, May 29, 2013 at 1:46 AM, Kevin Hilman <khilman at linaro.org> wrote:
> On Tue, May 28, 2013 at 3:57 PM, Kevin Hilman <khilman at linaro.org> wrote:
>
>> u8500_defconfig started failing to build in linux next (next-20130527)
>> but was previously building (next-20130523.)
>
> My apologies, it appears this one is already fixed in next-20130528.
> /me updates automated build to not be a full day behind linux-next.

My fault for screwing it up one day though. :-/

This was beacuse of a double conflict in this file, and
me missing to fix the second conflict...

Linus


From tixy at linaro.org  Wed May 29 08:11:25 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Wed, 29 May 2013 13:11:25 +0100
Subject: [PATCH 1/8] drivers: bus: add ARM CCI support
In-Reply-To: <1369374311-21260-2-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-2-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369829485.3715.46.camel@linaro1.home>

On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
[...]
> +	cci at 2c090000 {
> +		compatible = "arm,cci-400";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x0 0x2c090000 0 0x1000>;
> +		ranges = <0x0 0x0 0x2c090000 0x6000>;
> +
> +		cci_control0: slave-if at 1000 {
> +			interface-type = "ace-lite";
> +			reg = <0x1000 0x1000>;
> +		};
> +
> +		cci_control1: slave-if at 4000 {
> +			interface-type = "ace";
> +			reg = <0x4000 0x1000>;
> +		};
> +
> +		cci_control2: slave-if at 5000 {
> +			interface-type = "ace";
> +			reg = <0x5000 0x1000>;
> +		};
> +	};

The above examples of slave-if nodes are missing the required
compatible = "arm,cci-400-ctrl-if";

-- 
Tixy



From maxime.ripard at free-electrons.com  Wed May 29 08:19:16 2013
From: maxime.ripard at free-electrons.com (maxime.ripard at free-electrons.com)
Date: Wed, 29 May 2013 14:19:16 +0200
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <20130529101332.GC7356@pengutronix.de>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529075044.GC3293@lukather>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A4D0@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529101332.GC7356@pengutronix.de>
Message-ID: <20130529121916.GF3293@lukather>

Hi Michael,

On Wed, May 29, 2013 at 12:13:32PM +0200, Michael Grzeschik wrote:
> Hi,
> 
> On Wed, May 29, 2013 at 08:07:55AM +0000, Chen Peter-B29397 wrote:
> > 
> >  
> > > 
> > > Indeed, I've been using the patchset "Add tested id switch and vbus
> > > connect detect support for Chipidea" from Peter for quite some time on
> > > top of 3.9 and it works like a charm for the gadget mode on an MX28
> > > platform.
> > > 
> > > BTW, Peter, I've seen that these patches are still not merged in 3.10,
> > > is there a reason for that? do you plan on sending a version rebased on
> > > top of 3.10 some time in the future? I tried to do the rebasing myself,
> > > but the chipidea driver seems to have changed quite heavily, which makes
> > > the process quite difficult when you don't know what you're doing :)
> > > 
> 
> we already have Peter's patches on v3.10-rc3 [1].

Wow, great, thanks!

> > I can spend few bandwidth on upstream work recently, I may have more
> > bandwidth after June 15th. 
> > 
> > Currently, we still have no conclusion for chipidea core driver's coming work,
> > like Device tree support, how to identify if the controller is OTG supported.
> 
> Yes, the next important step is getting the of propertys "dr_mode" and
> "phy_type" properly used in the chipidea core.

I totally admit lacking some context here, but how does the device tree
move prevent from merging these patches? Do they have any shortcomings?
I've been using them with DT for quite some time and it seems to be
working pretty well if you ask me...

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From tixy at linaro.org  Wed May 29 08:29:41 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Wed, 29 May 2013 13:29:41 +0100
Subject: [PATCH 7/8] ARM: vexpress/dcscb: handle platform coherency
 exit/setup and CCI
In-Reply-To: <1369374311-21260-8-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-8-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369830581.3715.50.camel@linaro1.home>

On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> From: Dave Martin <dave.martin at linaro.org>
> 
> Add the required code to properly handle race free platform coherency exit
> to the DCSCB power down method.
> 
> The power_up_setup callback is used to enable the CCI interface for
> the cluster being brought up.  This must be done in assembly before
> the kernel environment is entered.
> 
> Thanks to Achin Gupta and Nicolas Pitre for their help and
> contributions.
> 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>
> Signed-off-by: Nicolas Pitre <nico at linaro.org>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Pawel Moll <pawel.moll at arm.com>
> ---
>  arch/arm/mach-vexpress/Kconfig       |  1 +
>  arch/arm/mach-vexpress/Makefile      |  2 +-
>  arch/arm/mach-vexpress/dcscb.c       | 79 +++++++++++++++++++++++++++---------
>  arch/arm/mach-vexpress/dcscb_setup.S | 38 +++++++++++++++++
>  4 files changed, 100 insertions(+), 20 deletions(-)
>  create mode 100644 arch/arm/mach-vexpress/dcscb_setup.S
> 
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 2f46385c28..b8bbabec63 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -60,6 +60,7 @@ config ARCH_VEXPRESS_CA9X4
>  config ARCH_VEXPRESS_DCSCB
>  	bool "Dual Cluster System Control Block (DCSCB) support"
>  	depends on MCPM
> +	select ARM_CCI
>  	help
>  	  Support for the Dual Cluster System Configuration Block (DCSCB).
>  	  This is needed to provide CPU and cluster power management
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 518519f57a..48ba89a814 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -6,6 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>  
>  obj-y					:= v2m.o
>  obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
> -obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o
> +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o	dcscb_setup.o
>  obj-$(CONFIG_SMP)			+= platsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> index b928b1f5eb..1acc975360 100644
> --- a/arch/arm/mach-vexpress/dcscb.c
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -16,6 +16,7 @@
>  #include <linux/errno.h>
>  #include <linux/of_address.h>
>  #include <linux/vexpress.h>
> +#include <linux/arm-cci.h>
>  
>  #include <asm/mcpm.h>
>  #include <asm/proc-fns.h>
> @@ -105,7 +106,10 @@ static void dcscb_power_down(void)
>  	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
>  	BUG_ON(cpu >= 4 || cluster >= 2);
>  
> +	__mcpm_cpu_going_down(cpu, cluster);
> +
>  	arch_spin_lock(&dcscb_lock);
> +	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
>  	dcscb_use_count[cpu][cluster]--;
>  	if (dcscb_use_count[cpu][cluster] == 0) {
>  		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> @@ -125,31 +129,59 @@ static void dcscb_power_down(void)
>  		skip_wfi = true;
>  	} else
>  		BUG();
> -	arch_spin_unlock(&dcscb_lock);
> -
> -	/*
> -	 * Now let's clean our L1 cache and shut ourself down.
> -	 * If we're the last CPU in this cluster then clean L2 too.
> -	 */
>  
> -	/*
> -	 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> -	 * a preliminary flush here for those CPUs.  At least, that's
> -	 * the theory -- without the extra flush, Linux explodes on
> -	 * RTSM (to be investigated)..
> -	 */
> -	flush_cache_louis();
> -	set_cr(get_cr() & ~CR_C);
> +	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
> +		arch_spin_unlock(&dcscb_lock);
>  
> -	if (!last_man) {
> -		flush_cache_louis();
> -	} else {
> +		/*
> +		 * Flush all cache levels for this cluster.
> +		 *
> +		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> +		 * a preliminary flush here for those CPUs.  At least, that's
> +		 * the theory -- without the extra flush, Linux explodes on
> +		 * RTSM (to be investigated).
> +		 */
> +		flush_cache_all();
> +		set_cr(get_cr() & ~CR_C);
>  		flush_cache_all();
> +
> +		/*
> +		 * This is a harmless no-op.  On platforms with a real
> +		 * outer cache this might either be needed or not,
> +		 * depending on where the outer cache sits.
> +		 */
>  		outer_flush_all();
> +
> +		/* Disable local coherency by clearing the ACTLR "SMP" bit: */
> +		set_auxcr(get_auxcr() & ~(1 << 6));
> +
> +		/*
> +		 * Disable cluster-level coherency by masking
> +		 * incoming snoops and DVM messages:
> +		 */
> +		cci_disable_port_by_cpu(mpidr);
> +
> +		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> +	} else {
> +		arch_spin_unlock(&dcscb_lock);
> +
> +		/*
> +		 * Flush the local CPU cache.
> +		 *
> +		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> +		 * a preliminary flush here for those CPUs.  At least, that's
> +		 * the theory -- without the extra flush, Linux explodes on
> +		 * RTSM (to be investigated).
> +		 */
> +		flush_cache_louis();
> +		set_cr(get_cr() & ~CR_C);
> +		flush_cache_louis();
> +
> +		/* Disable local coherency by clearing the ACTLR "SMP" bit: */
> +		set_auxcr(get_auxcr() & ~(1 << 6));
>  	}
>  
> -	/* Disable local coherency by clearing the ACTLR "SMP" bit: */
> -	set_auxcr(get_auxcr() & ~(1 << 6));
> +	__mcpm_cpu_down(cpu, cluster);
>  
>  	/* Now we are prepared for power-down, do it: */
>  	dsb();
> @@ -177,12 +209,17 @@ static void __init dcscb_usage_count_init(void)
>  	dcscb_use_count[cpu][cluster] = 1;
>  }
>  
> +extern void dcscb_power_up_setup(unsigned int affinity_level);
> +
>  static int __init dcscb_init(void)
>  {
>  	struct device_node *node;
>  	unsigned int cfg;
>  	int ret;
>  
> +	if (!cci_probed())
> +		return -ENODEV;
> +

I can't see where cci_probed() is defined, this seems to be the only
occurrence in this patch set.


>  	node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
>  	if (!node)
>  		return -ENODEV;
> @@ -195,11 +232,15 @@ static int __init dcscb_init(void)
>  	dcscb_usage_count_init();
>  
>  	ret = mcpm_platform_register(&dcscb_power_ops);
> +	if (!ret)
> +		ret = mcpm_sync_init(dcscb_power_up_setup);
>  	if (ret) {
>  		iounmap(dcscb_base);
>  		return ret;
>  	}
>  
> +	pr_info("VExpress DCSCB support installed\n");
> +
>  	/*
>  	 * Future entries into the kernel can now go
>  	 * through the cluster entry vectors.
> diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S
> new file mode 100644
> index 0000000000..4bb7fbe0f6
> --- /dev/null
> +++ b/arch/arm/mach-vexpress/dcscb_setup.S
> @@ -0,0 +1,38 @@
> +/*
> + * arch/arm/include/asm/dcscb_setup.S
> + *
> + * Created by:  Dave Martin, 2012-06-22
> + * Copyright:   (C) 2012-2013  Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +
> +
> +ENTRY(dcscb_power_up_setup)
> +
> +	cmp	r0, #0			@ check affinity level
> +	beq	2f
> +
> +/*
> + * Enable cluster-level coherency, in preparation for turning on the MMU.
> + * The ACTLR SMP bit does not need to be set here, because cpu_resume()
> + * already restores that.
> + *
> + * A15/A7 may not require explicit L2 invalidation on reset, dependent
> + * on hardware integration decisions.
> + * For now, this code assumes that L2 is either already invalidated,
> + * or invalidation is not required.
> + */
> +
> +	b	cci_enable_port_for_self
> +
> +2:	@ Implementation-specific local CPU setup operations should go here,
> +	@ if any.  In this case, there is nothing to do.
> +
> +	bx	lr
> +
> +ENDPROC(dcscb_power_up_setup)

-- 
Tixy




From mgr at pengutronix.de  Wed May 29 08:41:08 2013
From: mgr at pengutronix.de (Michael Grzeschik)
Date: Wed, 29 May 2013 14:41:08 +0200
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <20130529121916.GF3293@lukather>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529075044.GC3293@lukather>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A4D0@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529101332.GC7356@pengutronix.de>
 <20130529121916.GF3293@lukather>
Message-ID: <20130529124108.GA415@pengutronix.de>

On Wed, May 29, 2013 at 02:19:16PM +0200, maxime.ripard at free-electrons.com wrote:
> Hi Michael,
> 
> On Wed, May 29, 2013 at 12:13:32PM +0200, Michael Grzeschik wrote:
> > Hi,
> > 
> > On Wed, May 29, 2013 at 08:07:55AM +0000, Chen Peter-B29397 wrote:
> > > 
> > >  
> > > > 
> > > > Indeed, I've been using the patchset "Add tested id switch and vbus
> > > > connect detect support for Chipidea" from Peter for quite some time on
> > > > top of 3.9 and it works like a charm for the gadget mode on an MX28
> > > > platform.
> > > > 
> > > > BTW, Peter, I've seen that these patches are still not merged in 3.10,
> > > > is there a reason for that? do you plan on sending a version rebased on
> > > > top of 3.10 some time in the future? I tried to do the rebasing myself,
> > > > but the chipidea driver seems to have changed quite heavily, which makes
> > > > the process quite difficult when you don't know what you're doing :)
> > > > 
> > 
> > we already have Peter's patches on v3.10-rc3 [1].
> 
> Wow, great, thanks!
> 
> > > I can spend few bandwidth on upstream work recently, I may have more
> > > bandwidth after June 15th. 
> > > 
> > > Currently, we still have no conclusion for chipidea core driver's coming work,
> > > like Device tree support, how to identify if the controller is OTG supported.
> > 
> > Yes, the next important step is getting the of propertys "dr_mode" and
> > "phy_type" properly used in the chipidea core.
> 
> I totally admit lacking some context here, but how does the device tree
> move prevent from merging these patches? Do they have any shortcomings?
> I've been using them with DT for quite some time and it seems to be
> working pretty well if you ask me...

Peters patches need some more care, as they are not cleanly sperated.
One patch e.g. adds an delayed worker to handle the otg events. Another
one above that patch is removing the worker afterwards.
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Wed May 29 08:46:27 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 14:46:27 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <146FF7AD-650E-4706-B9E1-53C2693D1D0D@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305271231.40693.arnd@arndb.de>
 <146FF7AD-650E-4706-B9E1-53C2693D1D0D@gmail.com>
Message-ID: <201305291446.28169.arnd@arndb.de>

On Wednesday 29 May 2013, Daniel Tang wrote:
> On 27/05/2013, at 8:31 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> 
> > On Monday 27 May 2013, Daniel Tang wrote:
> >>> The one remaining bit that sticks out is the clcd platform data. As I
> >>> said before, I won't require you to convert that to DT in order to
> >>> get your code merged, but I'd also really like to see that happen,
> >>> as we will also need that to get rid of auxdata on the ARM reference
> >>> platforms (integrator, versatile, realview, vexpress).
> >> 
> >> How would you like me to convert the platform data to DT? AFAIK, the clcd
> >> driver isn't aware of DT so the only way is to use the AUXDATA right now.
> > 
> > Linus Walleij mentioned on IRC that Pawel Moll already posted a series
> > that adds DT support for clcd:
> > 
> > http://lists.freedesktop.org/archives/dri-devel/2013-April/037519.html
> > 
> > The series does a few more things, but you can probbly split out the
> > parts you need and base on that.
> 
> Would it be fine if I waited until CLCD DT patch gets into mainline instead?

Yes, you can do that too, I was only asking whether you were interested
in helping out here.

	Arnd


From jayakumar.lkml at gmail.com  Wed May 29 08:52:43 2013
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Wed, 29 May 2013 20:52:43 +0800
Subject: Debugging sporadic kernel panics/oops or full hangs
Message-ID: <CADqH6VwjThkxCKB=CdAt-qQkssAAbh+xD8_brJe2ThC_B1dzag@mail.gmail.com>

Hi Linux Arm friends,

I'm experiencing some odd behavior on a custom imx508 board running a
vendor derived 2.6.35 (I realize that's frightfully old, but I have to
live with it until I get some time to try to port top of tree to
this). What I was seeing was sudden panics/oops or just complete hangs
(no oops on serial console).

For example, I did:

while (/bin/true) ; do cat /proc/meminfo ; done

and after about 7 mins of running, I suddenly got on oops. I
powercycle, repeat the test, after about 15 mins, another oops, repeat
again, full hang, no oops message. Other times the same board runs the
same test for 3 hours without any trouble.

I ran mtest in uboot for 2 hours and no crash. I then ran memtester in
userspace on the same kernel, memtester 60M, and that too didn't hang
after 2 hours. I'll repeat those tests again just to make sure that
consistently succeeds.

I don't have JTAG setup yet. I'm also going to try turning off various
kernel subsystems (CONFIG_USB, DVFS, etc) to see if that improves
stability in any way. I'd appreciate any advice or suggestions on how
I could debug this further.

Thanks,
jaya

Oops #1:
Unable to handle kernel paging request at virtual address 02a87009
pgd = 80004000
[02a87009] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT
last sysfs file: /sys/kernel/uevent_seqnum
Modules linked in:
CPU: 0    Not tainted  (2.6.35.3-899-g9b1a262-gabe3cff-dirty #42)
PC is at vt_console_print+0x8c/0x314
LR is at tasklet_action+0x70/0xb4
pc : [<80220008>]    lr : [<800676ec>]    psr: 20000113
sp : 8057bf10  ip : 8006767c  fp : 00000000
r10: 80599938  r9 : 0000000a  r8 : 00000103
r7 : 00000000  r6 : 00000000  r5 : 80599b00  r4 : 805d9c80
r3 : 80220000  r2 : 02a87001  r1 : 00000014  r0 : 9f0e3800
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 8f4e0019  DAC: 00000017
Process swapper (pid: 0, stack limit = 0x8057a2e8)
Stack: (0x8057bf10 to 0x8057c000)
bf00:                                     8057a000 00000001 00000018 805d9c80
bf20: 00000103 80067c94 00000000 00000040 9f336100 00000006 8059bf6c 0000001f
bf40: 00000000 00000001 00000002 00000001 8057a000 0000001f 00000000 80067d60
bf60: 0000001f 80033070 ffffffff a0800000 00000001 80033a8c 8058ae1c 030f3003
bf80: 00000001 00000000 8057a000 8057ea40 805d0d04 8057ea38 70029310 412fc085
bfa0: 0000001f 00000000 00000003 8057bfc0 80034a84 80034a88 60000013 ffffffff
bfc0: 8057a000 80034f6c 805dca60 8002aaf0 8057eae0 80008960 800084e8 00000bac
bfe0: 70000100 8002aaf0 10c53c7d 805d0dd0 8002aaec 70008034 00000000 00000000
[<80220008>] (vt_console_print+0x8c/0x314) from [<00000001>] (0x1)
Code: e353003e 8a000094 e3a01014 e0222391 (e5922008)
---[ end trace 55692addfbf1a0c1 ]---
Kernel panic - not syncing: Fatal exception in interrupt
[<800384ac>] (unwind_backtrace+0x0/0xf0) from [<80425964>] (panic+0x6c/0xe0)
[<80425964>] (panic+0x6c/0xe0) from [<80037388>] (die+0x2b4/0x304)
[<80037388>] (die+0x2b4/0x304) from [<80039328>] (__do_kernel_fault+0x64/0x84)
[<80039328>] (__do_kernel_fault+0x64/0x84) from [<80039508>]
(do_page_fault+0x1c0/0x1d4)
[<80039508>] (do_page_fault+0x1c0/0x1d4) from [<800332b8>]
(do_DataAbort+0x34/0x94)
[<800332b8>] (do_DataAbort+0x34/0x94) from [<80033a2c>] (__dabt_svc+0x4c/0x60)
Exception stack(0x8057bec8 to 0x8057bf10)
bec0:                   9f0e3800 00000014 02a87001 80220000 805d9c80 80599b00
bee0: 00000000 00000000 00000103 0000000a 80599938 00000000 8006767c 8057bf10
bf00: 800676ec 80220008 20000113 ffffffff
[<80033a2c>] (__dabt_svc+0x4c/0x60) from [<80220008>]
(vt_console_print+0x8c/0x314)
[<80220008>] (vt_console_print+0x8c/0x314) from [<00000001>] (0x1)


Oops #2:
Bad mode in data abort handler detected
Internal error: Oops - bad mode: 0 [#1] PREEMPT
last sysfs file: /sys/kernel/uevent_seqnum
Modules linked in:
CPU: 0    Not tainted  (2.6.35.3-899-g9b1a262-gabe3cff-dirty #42)
PC is at 0xffff03a0
LR is at __dabt_svc+0x40/0x60
pc : [<ffff03a0>]    lr : [<80033a20>]    psr: 2000019b
sp : 8057be60  ip : 805db388  fp : 00000000
r10: 0000001f  r9 : 8057a000  r8 : 00000001
r7 : 0000001f  r6 : 805ed40c  r5 : 8057bedc  r4 : ffffffff
r3 : a0000193  r2 : 8022accc  r1 : 00000817  r0 : 805d0d58
Flags: nzCv  IRQs off  FIQs on  Mode UND_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 8f500019  DAC: 00000017
Process swapper (pid: 0, stack limit = 0x8057a2e8)
Stack: (0x8057be60 to 0x8057c000)
be60: 805d0d58 00000817 8022accc a0000193 ffffffff 8057bedc 805ed40c 0000001f
be80: 00000001 8057a000 0000001f 00000000 805db388 8057be60 80033a20 ffff03a0
bea0: 2000019b ffffffff 00000001 00000604 a0000193 00000000 80585d68 9f0e3800
bec0: 805ed40c 0000001f 00000001 8057a000 0000001f 00000000 805db388 8022c1b8
bee0: 00000001 8022accc a0000193 ffffffff 00000000 80585d68 00000001 0000001f
bf00: 805db388 8057bef4 80585d68 80585d68 00001000 80585d68 00000100 8022cbe0
bf20: 0000001f 00002201 00001000 00002040 9f336100 00000000 00000000 8008ffe8
bf40: 8059bf6c 0000001f 9f336100 00000002 00000001 800920b0 0000001f 00000000
bf60: 00000001 8003306c ffffffff a0800000 00000001 80033a8c 8058ae1c 030f3003
bf80: 00000001 00000000 8057a000 8057ea40 805d0d04 8057ea38 70029310 412fc085
bfa0: 0000001f 00000000 00000003 8057bfc0 80034a84 80034a88 60000013 ffffffff
bfc0: 8057a000 80034f6c 805dca60 8002aaf0 8057eae0 80008960 800084e8 00000bac
bfe0: 70000100 8002aaf0 10c53c7d 805d0dd0 8002aaec 70008034 00000000 00000000
[<80033a20>] (__dabt_svc+0x40/0x60) from [<ffff03a0>] (0xffff03a0)
Code: e2200008 e16ff000 e20ee00f e1a0000d (e79fe10e)
---[ end trace b0cff94de1b66f81 ]---
Kernel panic - not syncing: Fatal exception in interrupt
[<800384ac>] (unwind_backtrace+0x0/0xf0) from [<80425964>] (panic+0x6c/0xe0)
[<80425964>] (panic+0x6c/0xe0) from [<80037388>] (die+0x2b4/0x304)
[<80037388>] (die+0x2b4/0x304) from [<80037414>] (bad_mode+0x3c/0x5c)
[<80037414>] (bad_mode+0x3c/0x5c) from [<80033a20>] (__dabt_svc+0x40/0x60)
[<80033a20>] (__dabt_svc+0x40/0x60) from [<ffff03a0>] (0xffff03a0)


From gregory.clement at free-electrons.com  Wed May 29 08:57:10 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 May 2013 14:57:10 +0200
Subject: [PATCH 3/3] ARM PJ4B: Add support for errata 4611
In-Reply-To: <20130529112207.GG13095@mudshark.cambridge.arm.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <1369822618-26797-4-git-send-email-gregory.clement@free-electrons.com>
 <20130529112207.GG13095@mudshark.cambridge.arm.com>
Message-ID: <51A5FB26.4090000@free-electrons.com>

Hi Will,

On 05/29/2013 01:22 PM, Will Deacon wrote:
> On Wed, May 29, 2013 at 11:16:58AM +0100, Gregory CLEMENT wrote:
>> From: Lior Amsalem <alior at marvell.com>
>>
>> A CP15 clean operation can result in a dead lock state if it is hit by
>> an incoming snoop event. the fiw to this issue is the following:
> 
> s/fiw/fix/
> 
>> before any CP15 clean type operation in Cache Coherency mode, issue a
>> Data Memory Barrier (DMB) or a Data Synchronization Barrier (DSB)
>> instruction.
> 
> Could you combine this with #6124, so we don't have back-to-back ifdefs all
> over the place? Also, there are more clean operations than you have
> described here, so why haven't you have to touch them all?

For the first point, unfortunately it is not possible as they are
errata for different CPUs. If finally the 2 last patches won't be
merged in 3.10, then I will add a new patch before them, to introduce
the PJ4B-MP which is the CPU used by the Armada XP whereas the
Armada 370 uses the PJ4B.

For the second point and the other CPU specific questions you raised
in the other emails, I am waiting for answer from Marvell engineers.

Thanks for your review

> 
>> [gregory.clement at free-electrons.com:add errata description in changelog]
>> [gregory.clement at free-electrons.com:make this errata depend on Aramda
>> 370]
>> Signed-off-by: Lior Amsalem <alior at marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
>> ---
>>  arch/arm/Kconfig                | 11 +++++++++++
>>  arch/arm/include/asm/tlbflush.h | 22 ++++++++++++++++++++++
>>  arch/arm/mm/copypage-v6.c       | 11 +++++++++++
>>  arch/arm/mm/proc-macros.S       | 13 +++++++++++++
>>  4 files changed, 57 insertions(+)
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 48cdbea..05c13f9 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -1087,6 +1087,17 @@ if !MMU
>>  source "arch/arm/Kconfig-nommu"
>>  endif
>>  
>> +config PJ4B_ERRATA_4611
>> +        bool "PJ4B Errata 4611: A Deadlock can Occur if a CP15 Clean/Clean and Invalidate Operation is Hit By a Snoop Event"
>> +        depends on CPU_PJ4B && MACH_ARMADA_370
>> +        help
>> +          A CP15 clean operation can result in a dead lock state if it is hit by
>> +          an incoming snoop event.
>> +          Workaround:
>> +	  Before any CP15 clean type operation in Cache Coherency mode, issue
>> +          a Data Memory Barrier (DMB) or a Data Synchronization Barrier (DSB)
>> +          instruction.
>> +
>>  config PJ4B_ERRATA_4742
>>          bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
>>          depends on CPU_PJ4B && MACH_ARMADA_370
>> diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
>> index e3a8064..112f778 100644
>> --- a/arch/arm/include/asm/tlbflush.h
>> +++ b/arch/arm/include/asm/tlbflush.h
>> @@ -475,11 +475,22 @@ static inline void flush_pmd_entry(void *pmd)
>>  {
>>  	const unsigned int __tlb_flag = __cpu_tlb_flags;
>>  
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +	unsigned long flags;
>> +	raw_local_irq_save(flags);
>> +	dmb();
>> +#endif
>> +
>>  #ifdef CONFIG_PJ4B_ERRATA_6124
>>  	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
>>  #else
>>  	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
>>  #endif
>> +
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +	raw_local_irq_restore(flags);
>> +#endif
> 
> Eeek. Why do you have to disable interrupts during this? Again, are there no
> chicken bits to save you?
> 
>>  	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
>>  
>>  	if (tlb_flag(TLB_WB))
>> @@ -490,11 +501,22 @@ static inline void clean_pmd_entry(void *pmd)
>>  {
>>  	const unsigned int __tlb_flag = __cpu_tlb_flags;
>>  
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +	unsigned long flags;
>> +	raw_local_irq_save(flags);
>> +	dmb();
>> +#endif
>> +
>>  #ifdef CONFIG_PJ4B_ERRATA_6124
>>  	tlb_op(TLB_DCLEAN, "c7, c14, 1	@ flush_pmd", pmd);
>>  #else
>>  	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
>>  #endif
>> +
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +	raw_local_irq_restore(flags);
>> +#endif
>> +
>>  	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
>>  }
>>  
>> diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
>> index b9bcc9d..20b69ad 100644
>> --- a/arch/arm/mm/copypage-v6.c
>> +++ b/arch/arm/mm/copypage-v6.c
>> @@ -59,11 +59,22 @@ static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long
>>   */
>>  static void discard_old_kernel_data(void *kto)
>>  {
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +        unsigned long flags;
>> +
>> +        raw_local_irq_save(flags);
>> +        dmb();
>> +#endif
>> +
>>  	__asm__("mcrr	p15, 0, %1, %0, c6	@ 0xec401f06"
>>  	   :
>>  	   : "r" (kto),
>>  	     "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
>>  	   : "cc");
>> +
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +        raw_local_irq_restore(flags);
>> +#endif
> 
> Do you actually have an aliasing vipt cache? If not, you don't care about
> this function.
> 
>> diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
>> index f9a0aa7..ca81291 100644
>> --- a/arch/arm/mm/proc-macros.S
>> +++ b/arch/arm/mm/proc-macros.S
>> @@ -178,7 +178,20 @@
>>  #endif
>>  
>>  	str	r3, [r0]
>> +
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +	mrs     r2, cpsr
>> +	orr     r3, r2, #PSR_F_BIT | PSR_I_BIT
>> +	msr     cpsr_c, r3                      @ Disable interrupts
>> +	dmb                                     @ ensure ordering with previous memory accesses
>> +#endif
>> +
>>  	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
>> +
>> +#ifdef CONFIG_PJ4B_ERRATA_4611
>> +	msr     cpsr_c, r2                      @ Restore interrupts
>> +	mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
>> +#endif
> 
> This could be a dsb.
> 
> Will
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From arnd at arndb.de  Wed May 29 09:01:05 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 15:01:05 +0200
Subject: Single zImage and A15/LPAE
In-Reply-To: <CAOesGMh+XHueA0UtnAzYTkysqdLqs93Bp31KJKsqVBa-LkiQbQ@mail.gmail.com>
References: <50735B75.8070109@wwwdotorg.org>
 <alpine.LFD.2.03.1305282148560.1918@syhkavp.arg>
 <CAOesGMh+XHueA0UtnAzYTkysqdLqs93Bp31KJKsqVBa-LkiQbQ@mail.gmail.com>
Message-ID: <2274563.opVbLLPT1p@wuerfel>

On Tuesday 28 May 2013 19:02:48 Olof Johansson wrote:
> On Tue, May 28, 2013 at 6:54 PM, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> > On Wed, 29 May 2013, Kukjin Kim wrote:
> >> (+ Olof, Russell)
> >>
> >> Just note, I found this in my old mail-box...
> >>
> >> So I think, as a result, we need to support separate kernel binary for LPAE
> >> and non-LPAE and you guys don't hold a different view about it.
> >
> > LPAE and non-LPAE configurations will most likely never be supported
> > together in the same kernel binary.  The runtime cost would simply be
> > too high to be worth it.
> >
> >> Current SSDK5440 and SD5v1 boards which are reference boards for EXYNOS5440
> >> has over 4GB memory as a default and that's why I'm writing this e-mail. It
> >> means I should keep separated kernel to support exynos5440 and other exynos
> >> SoCs.
> >
> > They could all be supported together but with less than 4GB of memory.
> 
> Or the other way around, the other EXYNOS5 CPUs could all enable LPAE
> even if they have less than 4GB of memory -- but not EXYNOS4, of
> course.

The one bug I see is that it's currently possible to build a kernel
for a Cortex-A5/A8/A9, Scorpion or PJ4 platform with LPAE enabled,
which obviously cannot work.

I think to do this right, we need to treat ARMv7+LPAE as a separate
architecture level, just like we treat ARMv6, ARMv7 as separate
compatible architectures. BTW, is there an official name for that
architecture?

If we introduce a new CONFIG_ARCH_MULTI_V7_LPAE option, that should
be used instead of CONFIG_ARCH_MULTI_V7 for platforms that can be
built as part of CONFIG_ARCH_MULTIPLATFORM and with LPAE support.
The default multi_v7_defconfig should enable all both
ARCH_MULTI_V7 and ARCH_MULTI_V7_LPAE, so we get e.g. OMAP4/OMAP5
adn Exynos4/Exynos5 in one kernel, but when you want to enable
LPAE, you have to disable ARCH_MULTI_V7 and only get OMAP5
and Exynos5 out of those.

	Arnd


From arnd at arndb.de  Wed May 29 09:11:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 15:11:37 +0200
Subject: [PATCH 3/3] ARM PJ4B: Add support for errata 4611
In-Reply-To: <51A5FB26.4090000@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <20130529112207.GG13095@mudshark.cambridge.arm.com>
 <51A5FB26.4090000@free-electrons.com>
Message-ID: <4523769.Zp7B72tmfz@wuerfel>

On Wednesday 29 May 2013 14:57:10 Gregory CLEMENT wrote:
> 
> For the first point, unfortunately it is not possible as they are
> errata for different CPUs. If finally the 2 last patches won't be
> merged in 3.10, then I will add a new patch before them, to introduce
> the PJ4B-MP which is the CPU used by the Armada XP whereas the
> Armada 370 uses the PJ4B.
> 
> For the second point and the other CPU specific questions you raised
> in the other emails, I am waiting for answer from Marvell engineers.

I've been confused by the various CPU types before. If you have
any information that's not yet in the excellent
Documentation/arm/Marvell/README file that Thomas added, could you
put it in there?

In particular, I'd like to understand what variants of PJ4 there
are, and maybe you can list their cpuid part numbers.

	Arnd


From shawn.guo at linaro.org  Wed May 29 09:12:35 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 21:12:35 +0800
Subject: [PATCH v6 07/10] ASoC: fsl-ssi: imx ac97 support
In-Reply-To: <1369752478-30260-8-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-8-git-send-email-mpa@pengutronix.de>
Message-ID: <20130529131233.GA29528@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 04:47:55PM +0200, Markus Pargmann wrote:
> +struct snd_ac97_bus_ops soc_ac97_ops = {
> +	.read		= fsl_ssi_ac97_read,
> +	.write		= fsl_ssi_ac97_write,
> +};
> +EXPORT_SYMBOL_GPL(soc_ac97_ops);

I'm seeing the following compile error.

  LD      sound/soc/fsl/built-in.o
sound/soc/fsl/snd-soc-imx-ssi.o: In function `__crc_soc_ac97_ops':
imx-ssi.c:(*ABS*+0xd390d3c4): multiple definition of `__crc_soc_ac97_ops'
sound/soc/fsl/snd-soc-imx-ssi.o:(.data+0x168): multiple definition of `soc_ac97_ops'
sound/soc/fsl/snd-soc-fsl-ssi.o:(.data+0x0): first defined here
make[4]: *** [sound/soc/fsl/built-in.o] Error 1

Shawn



From arnd at arndb.de  Wed May 29 09:26:34 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 15:26:34 +0200
Subject: [PATCH] SPI: Unify simple platform data for some controllers
In-Reply-To: <20130529112002.GS3660@sirena.org.uk>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <1369817353.993218858@f175.mail.ru> <20130529112002.GS3660@sirena.org.uk>
Message-ID: <201305291526.35099.arnd@arndb.de>

On Wednesday 29 May 2013, Mark Brown wrote:
> On Wed, May 29, 2013 at 12:49:13PM +0400, Alexander Shiyan wrote:
> > > On Wednesday 29 May 2013 10:42:22 Alexander Shiyan wrote:
> 
> > > Wouldn't it be better to kill off the platform_data for these drivers
> > > and pass the gpio number through spi->controller_data as the
> > > spi_gpio driver does?
> 
> > Interesting way. Just one question remains, for using not-dt variant,
> > how  we should specify num_chipselect parameter for master?
> > I see only way for specify maximum constant in the driver.
> 
> We should fix that to be dynamic, having a fixed number is not sensible
> when GPIOs are usable for chip select. 

Agreed (not that I have much of a say on this matter).

> We probably also want to make
> GPIO chip select support a standard thing that's available with every
> driver rather than something the driver has to know about but that's a
> separate bit of work.

That actually seems simpler than doing it in just one driver: if
we add a cs_gpio field to spi_board_info, spi_new_device could
just copy that information into the new spi_device instead of
taking it from master->cs_gpios.

	Arnd


From gregory.clement at free-electrons.com  Wed May 29 09:27:31 2013
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 May 2013 15:27:31 +0200
Subject: [PATCH 3/3] ARM PJ4B: Add support for errata 4611
In-Reply-To: <4523769.Zp7B72tmfz@wuerfel>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <20130529112207.GG13095@mudshark.cambridge.arm.com>
 <51A5FB26.4090000@free-electrons.com> <4523769.Zp7B72tmfz@wuerfel>
Message-ID: <51A60243.3000800@free-electrons.com>

On 05/29/2013 03:11 PM, Arnd Bergmann wrote:
> On Wednesday 29 May 2013 14:57:10 Gregory CLEMENT wrote:
>>
>> For the first point, unfortunately it is not possible as they are
>> errata for different CPUs. If finally the 2 last patches won't be
>> merged in 3.10, then I will add a new patch before them, to introduce
>> the PJ4B-MP which is the CPU used by the Armada XP whereas the
>> Armada 370 uses the PJ4B.
>>
>> For the second point and the other CPU specific questions you raised
>> in the other emails, I am waiting for answer from Marvell engineers.
> 
> I've been confused by the various CPU types before. If you have
> any information that's not yet in the excellent
> Documentation/arm/Marvell/README file that Thomas added, could you
> put it in there?
> 
> In particular, I'd like to understand what variants of PJ4 there
> are, and maybe you can list their cpuid part numbers.

OK I will see what kind of information I can gather and which ones I can
add to the Documentation/arm/Marvell/README file.

My current understanding is that there are at least 3 kind of CPU:
PJ4, PJ4B and PJ4B-MP and all of them belongs to the Sheeva family.

> 
> 	Arnd
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From arnd at arndb.de  Wed May 29 09:33:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 15:33:13 +0200
Subject: [PATCH 3/3] ARM PJ4B: Add support for errata 4611
In-Reply-To: <51A60243.3000800@free-electrons.com>
References: <1369822618-26797-1-git-send-email-gregory.clement@free-electrons.com>
 <4523769.Zp7B72tmfz@wuerfel> <51A60243.3000800@free-electrons.com>
Message-ID: <2479964.1Q22eHuH4J@wuerfel>

On Wednesday 29 May 2013 15:27:31 Gregory CLEMENT wrote:
> OK I will see what kind of information I can gather and which ones I can
> add to the Documentation/arm/Marvell/README file.
> 
> My current understanding is that there are at least 3 kind of CPU:
> PJ4, PJ4B and PJ4B-MP and all of them belongs to the Sheeva family.

Ok. So I guess PJ4B adds LPAE support, and PJ4B-MP adds SMP support,
right? Do either of them support hypervisor mode?

Regarding the errata: are those needed for production-level chips,
or just for prototypes?

	Arnd


From b-cousson at ti.com  Wed May 29 09:35:35 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 15:35:35 +0200
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93EAFB174@DBDE04.ent.ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
 <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>
 <51A5BEB6.6070809@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A93EAFB174@DBDE04.ent.ti.com>
Message-ID: <51A60427.6010409@ti.com>

On 05/29/2013 11:58 AM, Mohammed, Afzal wrote:
> Hi Benoit,
> 
> On Wed, May 29, 2013 at 14:09:18, Cousson, Benoit wrote:
>> On 05/29/2013 10:06 AM, Mohammed, Afzal wrote:
>>> On Wed, May 29, 2013 at 03:35:10, Stephen Warren wrote:
>>>> On 05/28/2013 03:25 PM, Jon Hunter wrote:
> 
>>>>> If you are adding more compatibility strings, then this implies that the
>>>>> AM43x timers are not 100% compatible with any other device listed (such
>>>>> as am335x or any omap device). That's fine but you should state that in
>>>>> the changelog. If the AM43x timer registers are 100% compatible with
>>>>> existing devices you should not add these.
>>>>
>>>> I'm not sure that's true; .dts files should always include a compatible
>>>> value that describes the most specific model of the HW, plus any
>>>> baseline compatible value that the HW is compatible with. This allows
>>>> any required quirks/fixes/... to be applied for the specific HW model
>>>> later even if nobody knows right now they'll be needed. Hence, defining
>>>> new compatible values doesn't necessarily mean incompatible HW.
>>>
>>> Stephen took words out of my finger ;)
>>>  
>>> Some explanations,I don;t 
>>>
>>> 1. first compatible should be exact device [A], followed by compatible
>>> model (if one)
>>> 2. Minor effort in getting DT right the first time may help prevent
>>> difficult effort later modifying it (if a necessity comes), considering
>>> the fact that DT sources has  to move out of Kernel at some point of
>>> time. And DT is not supposed to be modified, which may cause difficulty
>>> for the users (I had been a minor victim of this during rebase).
>>>
>>> As we both were in GPMC land earlier, an example,
>>>
>>> If my memory is right, GPMC IP in am335x is rev 6, and IP has 8 chip
>>> select, but one is not pinned out. Now assume that same IP is integrated
>>> in another SoC (probably OMAP4 has rev 6). Here if we use same compatible
>>> for both, driver cannot handle it properly (w/o knowledge about platform).
>>> But if exact compatible is mentioned, without modifying DT (which should
>>> be considered as a firmware) just by modifying Kernel, deciding based on
>>> compatible would help achieve what is required.
>>
>> That's true for the DTS itself, but here your are changing the binding
>> documentation which is supposed to reflect the driver "interface" in the
>> Device Tree model description.
>>
>> Since the driver does not support any new compatible string, you should
>> not update the binding.
> 
> I have a different opinion: Binding documentation is to be considered an
> entity that is not a part of the Kernel, but currently is a part of the
> Kernel for want of a better place. And binding is to be considered OS
> agnostic being ignorant of any piece of software (driver here).

OK, that part is correct, but instead of driver I should have said HW
device. The binding is supposed to identify a specific HW device
revision or family if some HW registers are there to identify the version.

> Binding has the authority to allow its usage in DT sources.

And in this case, you do not introduce any new revision.

There is no point to update the binding each time we add a new SoC
variant that will contain the exact same IP.

I think it will mainly confuse the user that will wonder what is
different in that version compare to the previous one, moreover we can
end up with hundred of entries for the exact same IP for nothing.

The real problem is due to the introduction of the SoC name in the
device compatible name. That does introduced a SoC level information
that is mostly irrelevant at device level. I can understand why it was
done for practical aspect when the IP version is not well identified,
but that can lead to this proliferation of new pointless bindings.

>> The driver and the binding will have to be changed the day you will have
>> to update the driver to handle a bug / feature specific to that revision
>> (ti,am4372-timer).
>>
>> Since this series does not seems to update the driver, you should not
>> update the bindings.
> 
> I believe that updating binding is a prerequisite for making a new
> DTS change, hence binding was updated first, then DTS.

I don't think so, as soon as you still use at least one documented
compatible binding in the DTS description.

It is not anyway really armless, it just adds much more confusion that
real useful information for my point of view.

Regards,
Benoit



From vikas.sajjan at linaro.org  Wed May 29 09:37:52 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Wed, 29 May 2013 19:07:52 +0530
Subject: [PATCH v2 0/5] Add generic set_rate clk_ops for PLL35xx and PLL36xx
 for samsung SoCs
Message-ID: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>

This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
    for PLL35xx & PLL36xx and usues clk->base instead of clk->con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
    values for supported rates that needs to be changed for changing
    corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35xx and PLL36xx

changes since v1:
	- removed sorting and bsearch
	- modified the definition of struct "samsung_pll_rate_table"
	- added generic round_rate()
	- rectified the ops assignment for "rate table passed as NULL"
	  during PLL registration

Is rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome tree.

Vikas Sajjan (2):
  clk: samsung: Add set_rate() clk_ops for PLL36xx
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk->base instead of directly using clk->con0 for
    PLL3xxx
  clk: samsung: Add support to register rate_table for PLL3xxx
  clk: samsung: Add set_rate() clk_ops for PLL35xx

 drivers/clk/samsung/clk-exynos4.c    |   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   30 +++--
 drivers/clk/samsung/clk-pll.c        |  226 ++++++++++++++++++++++++++++++----
 drivers/clk/samsung/clk-pll.h        |   33 ++++-
 4 files changed, 260 insertions(+), 39 deletions(-)

-- 
1.7.9.5



From vikas.sajjan at linaro.org  Wed May 29 09:37:53 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Wed, 29 May 2013 19:07:53 +0530
Subject: [PATCH v2 1/5] clk: samsung: Use clk->base instead of directly using
 clk->con0 for PLL3xxx
In-Reply-To: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369834677-20312-2-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.

Reviewed-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |   10 ++++---
 drivers/clk/samsung/clk-exynos5250.c |   14 ++++-----
 drivers/clk/samsung/clk-pll.c        |   54 ++++++++++++++++++----------------
 drivers/clk/samsung/clk-pll.h        |    4 +--
 4 files changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e6..cf7d4e7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -97,12 +97,14 @@
 #define GATE_IP_PERIL		0xc950
 #define E4210_GATE_IP_PERIR	0xc960
 #define GATE_BLOCK		0xc970
+#define E4X12_MPLL_LOCK		0x10008
 #define E4X12_MPLL_CON0		0x10108
 #define SRC_DMC			0x10200
 #define SRC_MASK_DMC		0x10300
 #define DIV_DMC0		0x10500
 #define DIV_DMC1		0x10504
 #define GATE_IP_DMC		0x10900
+#define APLL_LOCK		0x14000
 #define APLL_CON0		0x14100
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
@@ -1019,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
 					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-					reg_base + APLL_CON0);
+					reg_base + APLL_LOCK);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-					reg_base + E4X12_MPLL_CON0);
+					reg_base + E4X12_MPLL_LOCK);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + EPLL_CON0);
+					reg_base + EPLL_LOCK);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + VPLL_CON0);
+					reg_base + VPLL_LOCK);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..687b580 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ext_clk_match);
 
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-			reg_base + 0x100);
+			reg_base);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-			reg_base + 0x4100);
+			reg_base + 0x4000);
 	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
-			reg_base + 0x20110);
+			reg_base + 0x20010);
 	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
-			reg_base + 0x10150);
+			reg_base + 0x10050);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
-			reg_base + 0x10120);
+			reg_base + 0x10020);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10130);
+			reg_base + 0x10030);
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10140);
+			reg_base + 0x10040);
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..01f17cf 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -13,9 +13,24 @@
 #include "clk.h"
 #include "clk-pll.h"
 
+struct samsung_clk_pll {
+	struct clk_hw		hw;
+	const void __iomem	*base;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+#define pll_readl(pll, offset)						\
+		__raw_readl((void __iomem *)(pll->base + (offset)));
+#define pll_writel(pll, val, offset)					\
+		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
+
 /*
  * PLL35xx Clock Type
  */
+#define PLL35XX_LOCK_OFFSET             0x0
+#define PLL35XX_CON0_OFFSET             0x100
+#define PLL35XX_CON1_OFFSET             0x104
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -24,21 +39,14 @@
 #define PLL35XX_PDIV_SHIFT      (8)
 #define PLL35XX_SDIV_SHIFT      (0)
 
-struct samsung_clk_pll35xx {
-	struct clk_hw		hw;
-	const void __iomem	*con_reg;
-};
-
-#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
-
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
-	struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = pll_readl(pll, PLL35XX_CON0_OFFSET);
 	mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
 	pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
 	sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -54,9 +62,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *con_reg)
+			const char *pname, const void __iomem *base)
 {
-	struct samsung_clk_pll35xx *pll;
+	struct samsung_clk_pll *pll;
 	struct clk *clk;
 	struct clk_init_data init;
 
@@ -73,7 +81,7 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 	init.num_parents = 1;
 
 	pll->hw.init = &init;
-	pll->con_reg = con_reg;
+	pll->base = base;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
@@ -91,6 +99,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 /*
  * PLL36xx Clock Type
  */
+#define PLL36XX_LOCK_OFFSET             0x0
+#define PLL36XX_CON0_OFFSET             0x100
+#define PLL36XX_CON1_OFFSET             0x104
 
 #define PLL36XX_KDIV_MASK	(0xFFFF)
 #define PLL36XX_MDIV_MASK	(0x1FF)
@@ -100,22 +111,15 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_PDIV_SHIFT	(8)
 #define PLL36XX_SDIV_SHIFT	(0)
 
-struct samsung_clk_pll36xx {
-	struct clk_hw		hw;
-	const void __iomem	*con_reg;
-};
-
-#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
-
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
-	struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 4);
+	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -133,9 +137,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *con_reg)
+			const char *pname, const void __iomem *base)
 {
-	struct samsung_clk_pll36xx *pll;
+	struct samsung_clk_pll *pll;
 	struct clk *clk;
 	struct clk_init_data init;
 
@@ -152,7 +156,7 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 	init.num_parents = 1;
 
 	pll->hw.init = &init;
-	pll->con_reg = con_reg;
+	pll->base = base;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index f33786e..1329522 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,9 +25,9 @@ enum pll46xx_type {
 };
 
 extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *con_reg);
+			const char *pname, const void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *con_reg);
+			const char *pname, const void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll45xx_type type);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Wed May 29 09:37:54 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Wed, 29 May 2013 19:07:54 +0530
Subject: [PATCH v2 2/5] clk: samsung: Add support to register rate_table for
 PLL3xxx
In-Reply-To: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369834677-20312-3-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.

Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
 drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
 drivers/clk/samsung/clk-pll.c        |   14 ++++++++++++--
 drivers/clk/samsung/clk-pll.h        |   33 +++++++++++++++++++++++++++++++--
 4 files changed, 54 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index cf7d4e7..beff8a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
 					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-					reg_base + APLL_LOCK);
+					reg_base + APLL_LOCK, NULL, 0);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-					reg_base + E4X12_MPLL_LOCK);
+					reg_base + E4X12_MPLL_LOCK, NULL, 0);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + EPLL_LOCK);
+					reg_base + EPLL_LOCK, NULL, 0);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + VPLL_LOCK);
+					reg_base + VPLL_LOCK, NULL, 0);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ext_clk_match);
 
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-			reg_base);
+			reg_base, NULL, 0);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-			reg_base + 0x4000);
+			reg_base + 0x4000, NULL, 0);
 	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
-			reg_base + 0x20010);
+			reg_base + 0x20010, NULL, 0);
 	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
-			reg_base + 0x10050);
+			reg_base + 0x10050, NULL, 0);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
-			reg_base + 0x10020);
+			reg_base + 0x10020, NULL, 0);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10030);
+			reg_base + 0x10030, NULL, 0);
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10040);
+			reg_base + 0x10040, NULL, 0);
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 01f17cf..4b3b3f5 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -16,6 +16,8 @@
 struct samsung_clk_pll {
 	struct clk_hw		hw;
 	const void __iomem	*base;
+	const struct samsung_pll_rate_table *rate_table;
+	unsigned int rate_count;
 };
 
 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *base)
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -82,6 +86,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 
 	pll->hw.init = &init;
 	pll->base = base;
+	pll->rate_table = rate_table;
+	pll->rate_count = rate_count;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
@@ -137,7 +143,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *base)
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -157,6 +165,8 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 
 	pll->hw.init = &init;
 	pll->base = base;
+	pll->rate_table = rate_table;
+	pll->rate_count = rate_count;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 1329522..a7c0f5a 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -12,6 +12,31 @@
 #ifndef __SAMSUNG_CLK_PLL_H
 #define __SAMSUNG_CLK_PLL_H
 
+#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
+	{							\
+		.rate	=	(_rate),				\
+		.mdiv	=	(_m),				\
+		.pdiv	=	(_p),				\
+		.sdiv	=	(_s),				\
+	}
+
+#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
+	{							\
+		.rate	=	(_rate),				\
+		.mdiv	=	(_m),				\
+		.pdiv	=	(_p),				\
+		.sdiv	=	(_s),				\
+		.kdiv	=	(_k),				\
+	}
+
+struct samsung_pll_rate_table {
+	unsigned  int rate;
+	unsigned int pdiv;
+	unsigned int mdiv;
+	unsigned int sdiv;
+	unsigned int kdiv;
+};
+
 enum pll45xx_type {
 	pll_4500,
 	pll_4502,
@@ -25,9 +50,13 @@ enum pll46xx_type {
 };
 
 extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *base);
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count);
 extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *base);
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count);
 extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll45xx_type type);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Wed May 29 09:37:55 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Wed, 29 May 2013 19:07:55 +0530
Subject: [PATCH v2 3/5] clk: samsung: Add set_rate() clk_ops for PLL35xx
In-Reply-To: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369834677-20312-4-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

This patch add set_rate() and round_rate() for PLL35xx

Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-pll.c |  103 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4b3b3f5..1fba7ef 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -27,6 +27,36 @@ struct samsung_clk_pll {
 #define pll_writel(pll, val, offset)					\
 		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
 
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+				struct samsung_clk_pll *pll, unsigned long rate)
+{
+	const struct samsung_pll_rate_table  *rate_table = pll->rate_table;
+	int i;
+
+	for (i = 0; i < pll->rate_count; i++) {
+		if (rate == rate_table[i].rate)
+			return &rate_table[i];
+	}
+
+	return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+			unsigned long drate, unsigned long *prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+	int i;
+
+	/* Assumming rate_table is in descending order */
+	for (i = 0; i < pll->rate_count; i++) {
+		if (drate >= rate_table[i].rate)
+			return rate_table[i].rate;
+	}
+
+	/* return minimum supported value */
+	return rate_table[i - 1].rate;
+}
 /*
  * PLL35xx Clock Type
  */
@@ -34,12 +64,17 @@ struct samsung_clk_pll {
 #define PLL35XX_CON0_OFFSET             0x100
 #define PLL35XX_CON1_OFFSET             0x104
 
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR	270
+
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
 #define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_LOCK_STAT_MASK  (0x1)
 #define PLL35XX_MDIV_SHIFT      (16)
 #define PLL35XX_PDIV_SHIFT      (8)
 #define PLL35XX_SDIV_SHIFT      (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
 
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
@@ -59,8 +94,70 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+	if ((mdiv != ((pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK)) ||
+		(pdiv != ((pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK)))
+		return 1;
+	else
+		return 0;
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate;
+	u32 tmp;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+	if (!(samsung_pll35xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+		/* If only s change, change just s value only*/
+		tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
+		tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
+		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+	} else {
+		/* Set PLL lock time. */
+		pll_writel(pll, rate->pdiv * PLL35XX_LOCK_FACTOR,
+				PLL35XX_LOCK_OFFSET);
+
+		/* Change PLL PMS values */
+		tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
+				(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
+				(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
+		tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
+				(rate->pdiv << PLL35XX_PDIV_SHIFT) |
+				(rate->sdiv << PLL35XX_SDIV_SHIFT);
+		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+		/* wait_lock_time */
+		do {
+			cpu_relax();
+			tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+		} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
+				<< PLL35XX_LOCK_STAT_SHIFT)));
+	}
+
+	return 0;
+}
+
 static const struct clk_ops samsung_pll35xx_clk_ops = {
 	.recalc_rate = samsung_pll35xx_recalc_rate,
+	.round_rate = samsung_pll_round_rate,
+	.set_rate = samsung_pll35xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll35xx_clk_min_ops = {
+	.recalc_rate = samsung_pll35xx_recalc_rate,
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
@@ -79,11 +176,15 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 	}
 
 	init.name = name;
-	init.ops = &samsung_pll35xx_clk_ops;
 	init.flags = CLK_GET_RATE_NOCACHE;
 	init.parent_names = &pname;
 	init.num_parents = 1;
 
+	if (rate_table && rate_count)
+		init.ops = &samsung_pll35xx_clk_ops;
+	else
+		init.ops = &samsung_pll35xx_clk_min_ops;
+
 	pll->hw.init = &init;
 	pll->base = base;
 	pll->rate_table = rate_table;
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Wed May 29 09:37:56 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Wed, 29 May 2013 19:07:56 +0530
Subject: [PATCH v2 4/5] clk: samsung: Add set_rate() clk_ops for PLL36xx
In-Reply-To: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369834677-20312-5-git-send-email-vikas.sajjan@linaro.org>

This patch adds set_rate and round_rate clk_ops for PLL36xx

Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
---
 drivers/clk/samsung/clk-pll.c |   59 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 1fba7ef..3872161 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -210,6 +210,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_CON0_OFFSET             0x100
 #define PLL36XX_CON1_OFFSET             0x104
 
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR	3000
+
 #define PLL36XX_KDIV_MASK	(0xFFFF)
 #define PLL36XX_MDIV_MASK	(0x1FF)
 #define PLL36XX_PDIV_MASK	(0x3F)
@@ -217,6 +220,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_MDIV_SHIFT	(16)
 #define PLL36XX_PDIV_SHIFT	(8)
 #define PLL36XX_SDIV_SHIFT	(0)
+#define PLL36XX_KDIV_SHIFT	(0)
+#define PLL36XX_LOCK_STAT_SHIFT (29)
 
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
@@ -239,8 +244,57 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 tmp, pll_con0, pll_con1;
+	const struct samsung_pll_rate_table *rate;
+
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
+
+	/* Set PLL lock time. */
+	pll_writel(pll, (rate->pdiv * PLL36XX_LOCK_FACTOR),
+			PLL36XX_LOCK_OFFSET);
+
+	 /* Change PLL PMS values */
+	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
+			(PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
+			(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
+	pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
+			(rate->pdiv << PLL36XX_PDIV_SHIFT) |
+			(rate->sdiv << PLL36XX_SDIV_SHIFT);
+	pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+	pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
+	pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
+	pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+	/* wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
+
+	return 0;
+}
+
 static const struct clk_ops samsung_pll36xx_clk_ops = {
 	.recalc_rate = samsung_pll36xx_recalc_rate,
+	.set_rate = samsung_pll36xx_set_rate,
+	.round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+	.recalc_rate = samsung_pll36xx_recalc_rate,
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -264,6 +318,11 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 	init.parent_names = &pname;
 	init.num_parents = 1;
 
+	if (rate_table && rate_count)
+		init.ops = &samsung_pll36xx_clk_ops;
+	else
+		init.ops = &samsung_pll36xx_clk_min_ops;
+
 	pll->hw.init = &init;
 	pll->base = base;
 	pll->rate_table = rate_table;
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Wed May 29 09:37:57 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Wed, 29 May 2013 19:07:57 +0530
Subject: [PATCH v2 5/5] clk: samsung: Add EPLL and VPLL freq table for
 exynos5250 SoC
In-Reply-To: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1369834677-20312-6-git-send-email-vikas.sajjan@linaro.org>

Adds the EPLL and VPLL freq table for exynos5250 SoC.

Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |   20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ddf10ca..bf61091 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -469,6 +469,22 @@ static __initdata struct of_device_id ext_clk_match[] = {
 	{ },
 };
 
+static const struct samsung_pll_rate_table vpll_tbl[] = {
+	PLL_36XX_RATE(70500000, 94, 2, 4, 0),
+};
+
+static const struct samsung_pll_rate_table epll_tbl[] = {
+	/* sorted in descending order */
+	PLL_36XX_RATE(192000000, 48, 3, 1, 0),
+	PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+	PLL_36XX_RATE(180000000, 45, 3, 1, 0),
+	PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+	PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+	PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+	PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+	PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
 /* register exynox5250 clocks */
 void __init exynos5250_clk_init(struct device_node *np)
 {
@@ -501,9 +517,9 @@ void __init exynos5250_clk_init(struct device_node *np)
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
 			reg_base + 0x10020, NULL, 0);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10030, NULL, 0);
+			reg_base + 0x10030, epll_tbl, ARRAY_SIZE(epll_tbl));
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10040, NULL, 0);
+			reg_base + 0x10040, vpll_tbl, ARRAY_SIZE(vpll_tbl));
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
-- 
1.7.9.5



From tixy at linaro.org  Wed May 29 09:42:17 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Wed, 29 May 2013 14:42:17 +0100
Subject: [PATCH 3/8] ARM: introduce common set_auxcr/get_auxcr functions
In-Reply-To: <1369374311-21260-4-git-send-email-nicolas.pitre@linaro.org>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-4-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1369834937.3715.64.camel@linaro1.home>

On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Move the private set_auxcr/get_auxcr functions from
> drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Signed-off-by: Nicolas Pitre <nico at linaro.org>
> Acked-by: Tony Lindgren <tony at atomide.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Reviewed-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/include/asm/cp15.h       | 14 ++++++++++++++
>  drivers/cpuidle/cpuidle-calxeda.c | 14 +-------------
>  2 files changed, 15 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
> index 1f3262e99d..cedd372131 100644
> --- a/arch/arm/include/asm/cp15.h
> +++ b/arch/arm/include/asm/cp15.h
> @@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val)
>  	isb();
>  }
>  
> +static inline unsigned int get_auxcr(void)
> +{
> +	unsigned int val;
> +	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val));
> +	return val;
> +}
> +
> +static inline void set_auxcr(unsigned int val)
> +{
> +	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
> +	  : : "r" (val));
> +	isb();
> +}
> +
>  #ifndef CONFIG_SMP
>  extern void adjust_cr(unsigned long mask, unsigned long set);
>  #endif
> diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
> index 223379169c..8a08e04c0e 100644
> --- a/drivers/cpuidle/cpuidle-calxeda.c
> +++ b/drivers/cpuidle/cpuidle-calxeda.c
> @@ -37,19 +37,7 @@
>  extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
>  extern void *scu_base_addr;
>  
> -static inline unsigned int get_auxcr(void)
> -{
> -	unsigned int val;
> -	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val) : : "cc");
> -	return val;
> -}
> -
> -static inline void set_auxcr(unsigned int val)
> -{
> -	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
> -	  : : "r" (val) : "cc");
> -	isb();
> -}
> +static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;

The added line above looks like a merge error to me.

>  static noinline void calxeda_idle_restore(void)
>  {

-- 
Tixy



From shawn.guo at linaro.org  Wed May 29 09:53:45 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 21:53:45 +0800
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
Message-ID: <20130529135342.GB29528@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 04:47:49PM +0200, Markus Pargmann wrote:
> Add devicetree support for this audio soc fabric driver.
> 
> platform_of_node and cpu_of_node are set according to the fsl,audmux
> phandle.
> 
> This patch adds handling of ac97 reset functions according to fsl ac97
> support. They are setup from here to avoid board specific code in the
> generic fsl-ssi driver.
> 
> This patch changes the handling of pca100 boards from non-DT to DT only.
> pcm043 is still handled without DT.
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> ---
> 
> Notes:
>     Changes in v6:
>      - phycore-ac97 now manages the ac97 reset functions of the boards using
>        this combination of ssi-codec.
>      - Removed preprocessor ifs for DT, non-DT distinction. pcm043 is now
>        non-DT only and pca100 DT only.
>     
>     Changes in v4:
>      - New property phytec,audmux to check which audmux setup should be
>        executed. Checking for fsl,imx21-audmux and fsl,imx31-audmux.
>     
>     Changes in v3:
>      - Add some more information in the commit message.
>     
>     Changes in v2:
>      - Simplify the driver, by combining audmux port configurations. The
>        audmux driver actually knows on which platform he is running and
>        will return the appropriate error code if we use functions for
>        another platform. So we don't need to have the knowledge about it
>        in phycore-ac97 and can try both functions. This removes the need
>        of different compatibilities and renames it to phycore-ac97.
>      - Use a phandle for the cpu_dai link.
>      - Add devicetree binding documentation.
>      - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
>     
>     Changes in v2:
>      - Simplify the driver, by combining audmux port configurations. The
>        audmux driver actually knows on which platform he is running and
>        will return the appropriate error code if we use functions for
>        another platform. So we don't need to have the knowledge about it
>        in phycore-ac97 and can try both functions. This removes the need
>        of different compatibilities and renames it to imx27-ac97.
>      - Use a phandle for the cpu_dai link.
>      - Add devicetree binding documentation.
>      - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
> 
>  .../bindings/sound/phytec,phycore-ac97.txt         |  14 ++
>  sound/soc/fsl/phycore-ac97.c                       | 241 ++++++++++++++++++---
>  2 files changed, 229 insertions(+), 26 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
> 
> diff --git a/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
> new file mode 100644
> index 0000000..41201ff
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
> @@ -0,0 +1,14 @@
> +Phytec phycore AC97
> +
> +Required properties:
> +- compatible: "phytec,phycore-ac97"
> +- phytec,ssi: A phandle to the ssi device that is connected to ac97.
> +- phytec,audmux: A phandle to the audmux device.
> +
> +Example:
> +
> +sound {
> +	compatible = "phytec,phycore-ac97";
> +	phytec,ssi = <&ssi1>;
> +	phytec,audmux = <&audmux>;
> +};
> diff --git a/sound/soc/fsl/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
> index ae403c2..bf2c600 100644
> --- a/sound/soc/fsl/phycore-ac97.c
> +++ b/sound/soc/fsl/phycore-ac97.c
> @@ -20,8 +20,14 @@
>  #include <asm/mach-types.h>
>  
>  #include "imx-audmux.h"
> +#include "fsl_ssi.h"
> +
> +#define DRV_NAME "phycore-audio-fabric"
>  
>  static struct snd_soc_card imx_phycore;
> +static struct device_node *phycore_dai_cpu_node;
> +static void (*phycore_ac97_reset) (struct snd_ac97 *ac97);
> +static void (*phycore_ac97_warm_reset)(struct snd_ac97 *ac97);
>  
>  static struct snd_soc_ops imx_phycore_hifi_ops = {
>  };
> @@ -32,12 +38,12 @@ static struct snd_soc_dai_link imx_phycore_dai_ac97[] = {
>  		.stream_name	= "HiFi",
>  		.codec_dai_name		= "wm9712-hifi",
>  		.codec_name	= "wm9712-codec",
> -		.cpu_dai_name	= "imx-ssi.0",
> -		.platform_name	= "imx-ssi.0",

I do not think these and phycore_ac97_plat_name changes are necessary,
since of_node will always take precedence over name in match.

>  		.ops		= &imx_phycore_hifi_ops,
>  	},
>  };
>  
> +static const char phycore_ac97_plat_name[] = "imx-ssi.0";
> +
>  static struct snd_soc_card imx_phycore = {
>  	.name		= "PhyCORE-ac97-audio",
>  	.owner		= THIS_MODULE,
> @@ -45,40 +51,52 @@ static struct snd_soc_card imx_phycore = {
>  	.num_links	= ARRAY_SIZE(imx_phycore_dai_ac97),
>  };
>  
> -static struct platform_device *imx_phycore_snd_ac97_device;
> +static void phycore_ac97_imx21_audmux(void)
> +{
> +	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
> +		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> +		IMX_AUDMUX_V1_PCR_TFCSEL(3) |
> +		IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
> +		IMX_AUDMUX_V1_PCR_RXDSEL(3));
> +	imx_audmux_v1_configure_port(3,
> +		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> +		IMX_AUDMUX_V1_PCR_TFCSEL(0) |
> +		IMX_AUDMUX_V1_PCR_TFSDIR |
> +		IMX_AUDMUX_V1_PCR_RXDSEL(0));
> +}
> +
> +static void phycore_ac97_imx31_audmux(void)
> +{
> +	imx_audmux_v2_configure_port(3,
> +		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> +		IMX_AUDMUX_V2_PTCR_TFSEL(0) |
> +		IMX_AUDMUX_V2_PTCR_TFSDIR,
> +		IMX_AUDMUX_V2_PDCR_RXDSEL(0));
> +	imx_audmux_v2_configure_port(0,
> +		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> +		IMX_AUDMUX_V2_PTCR_TCSEL(3) |
> +		IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
> +		IMX_AUDMUX_V2_PDCR_RXDSEL(3));
> +}
> +
>  static struct platform_device *imx_phycore_snd_device;
>  
> +static struct platform_device *imx_phycore_snd_ac97_device;
> +
>  static int __init imx_phycore_init(void)
>  {
>  	int ret;
>  
> -	if (machine_is_pca100()) {
> -		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
> -			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> -			IMX_AUDMUX_V1_PCR_TFCSEL(3) |
> -			IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
> -			IMX_AUDMUX_V1_PCR_RXDSEL(3));
> -		imx_audmux_v1_configure_port(3,
> -			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> -			IMX_AUDMUX_V1_PCR_TFCSEL(0) |
> -			IMX_AUDMUX_V1_PCR_TFSDIR |
> -			IMX_AUDMUX_V1_PCR_RXDSEL(0));
> -	} else if (machine_is_pcm043()) {
> -		imx_audmux_v2_configure_port(3,
> -			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> -			IMX_AUDMUX_V2_PTCR_TFSEL(0) |
> -			IMX_AUDMUX_V2_PTCR_TFSDIR,
> -			IMX_AUDMUX_V2_PDCR_RXDSEL(0));
> -		imx_audmux_v2_configure_port(0,
> -			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> -			IMX_AUDMUX_V2_PTCR_TCSEL(3) |
> -			IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
> -			IMX_AUDMUX_V2_PDCR_RXDSEL(3));
> +	if (machine_is_pcm043()) {
> +		phycore_ac97_imx31_audmux();
>  	} else {
>  		/* return happy. We might run on a totally different machine */
>  		return 0;
>  	}
>  
> +	imx_phycore_dai_ac97[0].cpu_dai_name = phycore_ac97_plat_name;
> +	imx_phycore_dai_ac97[0].platform_name = phycore_ac97_plat_name;
> +
>  	imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
>  	if (!imx_phycore_snd_ac97_device)
>  		return -ENOMEM;
> @@ -108,18 +126,189 @@ fail2:
>  	platform_device_del(imx_phycore_snd_ac97_device);
>  fail1:
>  	platform_device_put(imx_phycore_snd_ac97_device);
> +	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
> +	imx_phycore_dai_ac97[0].platform_name = NULL;
>  	return ret;
>  }
>  
>  static void __exit imx_phycore_exit(void)
>  {
> +	if (!machine_is_pcm043())
> +		return;
> +
>  	platform_device_unregister(imx_phycore_snd_device);
>  	platform_device_unregister(imx_phycore_snd_ac97_device);
> +
> +	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
> +	imx_phycore_dai_ac97[0].platform_name = NULL;
>  }
>  
>  late_initcall(imx_phycore_init);
>  module_exit(imx_phycore_exit);
>  
> +
> +static const struct of_device_id imx_phycore_ac97_of_dev_id[] = {
> +	{
> +		.compatible = "phytec,phycore-ac97",
> +	}, {
> +		/* sentinel */
> +	}
> +};
> +MODULE_DEVICE_TABLE(of, imx_phycore_ac97_of_dev_id);
> +
> +
> +/*
> + * Pointer to AC97 reset functions for specific boards
> + */
> +#if IS_ENABLED(CONFIG_MACH_PCA100)
> +extern void pca100_ac97_cold_reset(struct snd_ac97 *ac97);
> +extern void pca100_ac97_warm_reset(struct snd_ac97 *ac97);
> +#else
> +void pca100_ac97_cold_reset(struct snd_ac97 *ac97) { }
> +void pca100_ac97_warm_reset(struct snd_ac97 *ac97) { }

static?

> +#endif
> +
> +#if IS_ENABLED(CONFIG_MACH_PCM043)
> +extern void pcm043_ac97_cold_reset(struct snd_ac97 *ac97);
> +extern void pcm043_ac97_warm_reset(struct snd_ac97 *ac97);
> +#else
> +void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { }
> +void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { }
> +#endif
> +
> +static void phycore_soc_ac97_reset(struct snd_ac97 *ac97)
> +{
> +	if (phycore_ac97_reset)
> +		phycore_ac97_reset(ac97);
> +	/* First read sometimes fails, do a dummy read */
> +	fsl_ssi_ac97_read(ac97, 0);

This function is unavailable until patch #7, right?

> +}
> +
> +static void phycore_soc_ac97_warm_reset(struct snd_ac97 *ac97)
> +{
> +	if (phycore_ac97_warm_reset)
> +		phycore_ac97_warm_reset(ac97);
> +
> +	/* First read sometimes fails, do a dummy read */
> +	fsl_ssi_ac97_read(ac97, 0);
> +}
> +
> +static int phycore_ac97_setup_devices(struct platform_device *pdev)
> +{
> +	int ret;
> +
> +	imx_phycore_snd_device = platform_device_alloc("wm9712-codec", -1);
> +	if (!imx_phycore_snd_device)
> +		return -ENOMEM;
> +
> +	ret = platform_device_add(imx_phycore_snd_device);
> +	if (ret) {
> +		dev_err(&pdev->dev, "ASoC: Platform device allocation failed\n");
> +		goto fail1;
> +	}
> +
> +	ret = snd_soc_register_card(&imx_phycore);
> +	if (ret) {
> +		dev_err(&pdev->dev, "ASoC: soc card registration failed\n");
> +		goto fail2;
> +	}
> +	return 0;
> +
> +fail2:
> +	platform_device_del(imx_phycore_snd_device);
> +fail1:
> +	platform_device_put(imx_phycore_snd_device);
> +	return ret;
> +}
> +
> +static int imx_phycore_ac97_probe(struct platform_device *pdev)
> +{
> +	int ret;
> +	struct device_node *ssi_np;
> +	struct device_node *audmux_np;
> +	const char *sprop;
> +	const char *p;
> +
> +	imx_phycore.dev = &pdev->dev;
> +
> +	audmux_np = of_parse_phandle(pdev->dev.of_node, "phytec,audmux", 0);
> +	if (!audmux_np) {
> +		dev_err(&pdev->dev, "Failed to parse phytec,audmux phandle\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_device_is_compatible(audmux_np, "fsl,imx21-audmux")) {
> +		phycore_ac97_imx21_audmux();
> +	} else if (of_device_is_compatible(audmux_np, "fsl,imx31-audmux")) {
> +		phycore_ac97_imx31_audmux();
> +	} else {
> +		dev_err(&pdev->dev, "Unknown audmux, failed to setup audmux\n");
> +		of_node_put(audmux_np);
> +		return -EINVAL;
> +	}
> +	of_node_put(audmux_np);
> +
> +	ssi_np = of_parse_phandle(pdev->dev.of_node, "phytec,ssi", 0);
> +	if (!ssi_np) {
> +		dev_err(&pdev->dev, "No valid ssi phandle found\n");
> +		return -EINVAL;
> +	}
> +
> +	imx_phycore_dai_ac97[0].cpu_of_node = ssi_np;
> +	imx_phycore_dai_ac97[0].platform_of_node = ssi_np;
> +	phycore_dai_cpu_node = ssi_np;
> +
> +	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
> +	p = strrchr(sprop, ',');
> +	if (p)
> +		sprop = p + 1;
> +
> +	if (!strcmp(sprop, "imx27-pca100")) {

Since this is a phycore/phytec specific ASoC-machine driver, what's the
problem with matching the machine compatible string by simply calling
of_machine_is_compatible()?

> +		phycore_ac97_reset = pca100_ac97_cold_reset;
> +		phycore_ac97_warm_reset = pca100_ac97_warm_reset;
> +	} else if (!strcmp(sprop, "imx35-pcm043")) {
> +		phycore_ac97_reset = pcm043_ac97_cold_reset;
> +		phycore_ac97_warm_reset = pcm043_ac97_warm_reset;
> +	} else {
> +		dev_err(&pdev->dev, "Failed to set AC97 reset functions, unknown board.\n");
> +		return -EINVAL;
> +	}
> +
> +	fsl_ssi_ac97_set_reset(phycore_soc_ac97_reset,
> +			phycore_soc_ac97_warm_reset);
> +
> +	ret = phycore_ac97_setup_devices(pdev);
> +	if (ret)
> +		of_node_put(phycore_dai_cpu_node);
> +
> +	return ret;
> +}
> +
> +static int imx_phycore_ac97_remove(struct platform_device *pdev)
> +{
> +	of_node_put(phycore_dai_cpu_node);
> +	phycore_dai_cpu_node = NULL;
> +
> +	platform_device_unregister(imx_phycore_snd_device);

snd_soc_unregister_card() call is missing?

Shawn

> +
> +	phycore_ac97_reset = NULL;
> +	phycore_ac97_warm_reset = NULL;
> +
> +	return 0;
> +}
> +
> +static struct platform_driver imx_phycore_ac97_driver = {
> +	.probe		= imx_phycore_ac97_probe,
> +	.remove		= imx_phycore_ac97_remove,
> +	.driver		= {
> +		.name	= DRV_NAME,
> +		.owner	= THIS_MODULE,
> +		.of_match_table = imx_phycore_ac97_of_dev_id,
> +	},
> +};
> +
> +module_platform_driver(imx_phycore_ac97_driver);
> +
>  MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
> -MODULE_DESCRIPTION("PhyCORE ALSA SoC driver");
> +MODULE_DESCRIPTION(DRV_NAME ": PhyCORE ALSA SoC fabric driver");
>  MODULE_LICENSE("GPL");
> -- 
> 1.8.2.1
> 



From grant.likely at linaro.org  Wed May 29 09:55:57 2013
From: grant.likely at linaro.org (Grant Likely)
Date: Wed, 29 May 2013 14:55:57 +0100
Subject: [RFC] arm: Update Booting document for FDT placement and reserved map
Message-ID: <1369835757-16371-1-git-send-email-grant.likely@linaro.org>

The Booting document isn't very clear about what a bootloader is
required to do when booting with an FDT. First, the placement of the FDT
isn't as strict as the document suggests. It can actually appear
anywhere in RAM and the decompressor will relocated if it absolutely
needs to (but it is better if it doesn't have to).

Second, the bootloader is expected to update the reserved map if there
are any memory regions that are hands-off for the firmware. While this
has always been the case, such as when an initrd is provided, it became
more obvious when starting to work with UEFI. UEFI may provide
additional data to the OS like a block of SMBIOS tables, but if those
regions aren't described in the reserved map then the kernel will
happily reclaim that memory for it's own purposes.

It is possible in the future when the kernel is able to parse UEFI
memory maps directly that we'll relax the requirement for UEFI
regions, but it is safe and pragmatic to be strict about it now, and it
really doesn't cause any new hardship. The existing UEFI LinuxLoader
already update the FDT reserved map.

Signed-off-by: Grant Likely <grant.likely at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Nicolas Pitre <nico at linaro.org>
Cc: Leif Lindholm <leif.lindholm at linaro.org>
Cc: Olivier Martin <olivier.martin at arm.com>
Cc: Marc Zyngier <marc.zyngier at arm.com>
---

In this patch I've stated that the initrd doesn't need to be included in
the reserved map. However, should this be changed? Right now the
decompressor doesn't actually look at the reserved map when
decompressing and moving things around. If I'm reading the code
correctly it is possible that the decompressor will overwrite the initrd
if it gets placed too close to the kernel.

So, my question is this; would it be better to require (or strongly
recommend) the initrd be included in the reserved map and make the
zImage wrapper aware of mem regions that is must not touch. Or should I
leave well enough alone because in practical terms it's working fine
as-is?

 Documentation/arm/Booting | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting
index 0c1f475..1ea5020 100644
--- a/Documentation/arm/Booting
+++ b/Documentation/arm/Booting
@@ -118,13 +118,28 @@ physical address to determine if a dtb has been passed instead of a
 tagged list.
 
 The boot loader must pass at a minimum the size and location of the
-system memory, and the root filesystem location.  The dtb must be
+system memory, and the root filesystem location.  The dtb should be
 placed in a region of memory where the kernel decompressor will not
-overwrite it.  The recommended placement is in the first 16KiB of RAM
-with the caveat that it may not be located at physical address 0 since
-the kernel interprets a value of 0 in r2 to mean neither a tagged list
+overwrite it. The decompressor will relocate an inconveniently placed
+DTB, but it is better if it doesn't have to. The recommended placement
+is either in the first 16KiB of RAM with the caveat that it may not be
+located at physical address 0[1], or several megabytes past the end of the
+kernel image.
+
+[1] the kernel interprets a value of 0 in r2 to mean neither a tagged list
 nor a dtb were passed.
 
+The boot loader must also ensure that the FDT reserve memory map covers
+all areas of main memory that must not be overwritten. This includes
+firmware runtime support data[2], fixed framebuffers and DMA buffers.
+However the initrd does not need to be included as the kernel already
+knows how to protect the initrd location.
+
+[2] In particular when booting from UEFI the OS loader is expected to retrieve the
+UEFI memory map and add all UEFI runtime memory regions to the reserved
+map. This include UEFI runtime services, SMBIOS tables and ACPI tables
+if they exist.
+
 5. Calling the kernel image
 ---------------------------
 
-- 
1.8.1.2



From marvin24 at gmx.de  Wed May 29 09:38:40 2013
From: marvin24 at gmx.de (Marc Dietrich)
Date: Wed, 29 May 2013 15:38:40 +0200
Subject: [PATCH] ARM: tegra: rebuild tegra_defconfig
In-Reply-To: <51A521F5.2010206@wwwdotorg.org>
References: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>
 <51A521F5.2010206@wwwdotorg.org>
Message-ID: <2234363.J239kID5LN@fb07-iapwap2.physik.uni-giessen.de>

Am Dienstag, 28. Mai 2013, 15:30:29 schrieb Stephen Warren:
> On 05/28/2013 11:26 AM, Stephen Warren wrote:
> > From: Stephen Warren <swarren at nvidia.com>
> > 
> > This simply rebuilds tegra_defconfig on top of next-20130520. As such, it
> > should introduce no changes; simply moving entries around due to Kconfig
> > ordering changes. The apparent exceptions are:
> > 
> > AUTO_ZRELADDR: Selected by ARM multi-platform support.
> > MTD_CHAR: Removed in Kconfig.
> > 
> > This should make it easier to create future defconfig patches on top of
> > linux-next, since all the extraneous diffs have been removed. It also
> > makes it more likely that once 3.12 comes around, this defconfig will
> > already match what's required there.
> 
> I've applied this (squashed it into) Tegra's for-3.11/defconfig branch.

wouldn't it make more sense to apply such a patch just before the merge window 
closes (or better after some release candidate)? This way we would have a 
better chance to have a zero diff between defconfig and tegra_defconfig, e.g. 
not like 3.10 is now.

Marc


From liuj97 at gmail.com  Wed May 29 09:57:32 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed, 29 May 2013 21:57:32 +0800
Subject: [PATCH v6,
 part4 14/41] mm/ARM64: prepare for removing num_physpages and
 simplify mem_init()
In-Reply-To: <1369835879-23553-1-git-send-email-jiang.liu@huawei.com>
References: <1369835879-23553-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1369835879-23553-15-git-send-email-jiang.liu@huawei.com>

Prepare for removing num_physpages and simplify mem_init().

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm64/mm/init.c | 48 +++---------------------------------------------
 1 file changed, 3 insertions(+), 45 deletions(-)

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 93de98a..b16c778 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -272,59 +272,17 @@ static void __init free_unused_memmap(void)
  */
 void __init mem_init(void)
 {
-	unsigned long reserved_pages, free_pages;
-	struct memblock_region *reg;
-
 	arm64_swiotlb_init();
 
 	max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
-	/* this will put all unused low memory onto the freelists */
 	free_unused_memmap();
 #endif
-
+	/* this will put all unused low memory onto the freelists */
 	free_all_bootmem();
 
-	reserved_pages = free_pages = 0;
-
-	for_each_memblock(memory, reg) {
-		unsigned int pfn1, pfn2;
-		struct page *page, *end;
-
-		pfn1 = __phys_to_pfn(reg->base);
-		pfn2 = pfn1 + __phys_to_pfn(reg->size);
-
-		page = pfn_to_page(pfn1);
-		end  = pfn_to_page(pfn2 - 1) + 1;
-
-		do {
-			if (PageReserved(page))
-				reserved_pages++;
-			else if (!page_count(page))
-				free_pages++;
-			page++;
-		} while (page < end);
-	}
-
-	/*
-	 * Since our memory may not be contiguous, calculate the real number
-	 * of pages we have in this system.
-	 */
-	pr_info("Memory:");
-	num_physpages = 0;
-	for_each_memblock(memory, reg) {
-		unsigned long pages = memblock_region_memory_end_pfn(reg) -
-			memblock_region_memory_base_pfn(reg);
-		num_physpages += pages;
-		printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-	}
-	printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-	pr_notice("Memory: %luk/%luk available, %luk reserved\n",
-		  nr_free_pages() << (PAGE_SHIFT-10),
-		  free_pages << (PAGE_SHIFT-10),
-		  reserved_pages << (PAGE_SHIFT-10));
+	mem_init_print_info();
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -366,7 +324,7 @@ void __init mem_init(void)
 	BUILD_BUG_ON(TASK_SIZE_64			> MODULES_VADDR);
 	BUG_ON(TASK_SIZE_64				> MODULES_VADDR);
 
-	if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+	if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
 		extern int sysctl_overcommit_memory;
 		/*
 		 * On a machine this small we won't get anywhere without
-- 
1.8.1.2



From liuj97 at gmail.com  Wed May 29 09:57:31 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed, 29 May 2013 21:57:31 +0800
Subject: [PATCH v6,
 part4 13/41] mm/ARM: prepare for removing num_physpages and simplify
 mem_init()
In-Reply-To: <1369835879-23553-1-git-send-email-jiang.liu@huawei.com>
References: <1369835879-23553-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1369835879-23553-14-git-send-email-jiang.liu@huawei.com>

Prepare for removing num_physpages and simplify mem_init().

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mm/init.c | 47 ++---------------------------------------------
 1 file changed, 2 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 4ca7c1a..59c18b8 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -582,9 +582,6 @@ static void __init free_highpages(void)
  */
 void __init mem_init(void)
 {
-	unsigned long reserved_pages, free_pages;
-	struct memblock_region *reg;
-	int i;
 #ifdef CONFIG_HAVE_TCM
 	/* These pointers are filled in on TCM detection */
 	extern u32 dtcm_end;
@@ -604,47 +601,7 @@ void __init mem_init(void)
 
 	free_highpages();
 
-	reserved_pages = free_pages = 0;
-
-	for_each_bank(i, &meminfo) {
-		struct membank *bank = &meminfo.bank[i];
-		unsigned int pfn1, pfn2;
-		struct page *page, *end;
-
-		pfn1 = bank_pfn_start(bank);
-		pfn2 = bank_pfn_end(bank);
-
-		page = pfn_to_page(pfn1);
-		end  = pfn_to_page(pfn2 - 1) + 1;
-
-		do {
-			if (PageReserved(page))
-				reserved_pages++;
-			else if (!page_count(page))
-				free_pages++;
-			page++;
-		} while (page < end);
-	}
-
-	/*
-	 * Since our memory may not be contiguous, calculate the
-	 * real number of pages we have in this system
-	 */
-	printk(KERN_INFO "Memory:");
-	num_physpages = 0;
-	for_each_memblock(memory, reg) {
-		unsigned long pages = memblock_region_memory_end_pfn(reg) -
-			memblock_region_memory_base_pfn(reg);
-		num_physpages += pages;
-		printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-	}
-	printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-	printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
-		nr_free_pages() << (PAGE_SHIFT-10),
-		free_pages << (PAGE_SHIFT-10),
-		reserved_pages << (PAGE_SHIFT-10),
-		totalhigh_pages << (PAGE_SHIFT-10));
+	mem_init_print_info(NULL);
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -710,7 +667,7 @@ void __init mem_init(void)
 	BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE	> PAGE_OFFSET);
 #endif
 
-	if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+	if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
 		extern int sysctl_overcommit_memory;
 		/*
 		 * On a machine this small we won't get
-- 
1.8.1.2



From nico at fluxnic.net  Wed May 29 10:01:40 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 29 May 2013 10:01:40 -0400 (EDT)
Subject: VDSO for arm 32bit
In-Reply-To: <20130529090850.GB13095@mudshark.cambridge.arm.com>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
 <alpine.LFD.2.03.1305281415040.1918@syhkavp.arg>
 <20130529090850.GB13095@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305290955390.1918@syhkavp.arg>

On Wed, 29 May 2013, Will Deacon wrote:

> On Tue, May 28, 2013 at 07:19:00PM +0100, Nicolas Pitre wrote:
> > On Tue, 28 May 2013, Will Deacon wrote:
> > > Be careful here. I had a crack at a gtod implementation for the vectors page
> > > in the past, but decided to drop it because it quickly became a maintenance
> > > nightmare. Since the layout of the vectors page must be fixed (as userspace
> > > jumps to the absolute addresses for the helpers), having large, complicated
> > > functions (which gtod does become as you quickly start using the stack to
> > > store all of the shared state with the kernel) means that you can quickly
> > > back yourself into a corner where the layout of the code cannot change
> > > without breaking the ABI.
> > 
> > Note that only the entry point is fixed.  The layout of the code is not.  
> > So you may well branch anywhere else within the vector page if the code 
> > is more complex than a few instructions.
> 
> Sure, it may be possible simply to have branches in the kuser slots and then
> reserve a chunk at the other end of the vectors page where the actual
> implementation can go.
> 
> > > On top of that, new clock types are added more often than you might think
> > > (not to mention bug fixes in the implementation itself), and you end up in
> > > a horrible situation where you'd end up deprecating one implementation and
> > > adding gettimeofday2 or something equally nasty at a different offset.
> > 
> > That is equally valid for a vdso.
> 
> Sorry, I wasn't clear. My point was that you can change the layout of a vdso
> without breaking anything, since the dynamic loader resolves the entry
> points. It relates back to what I said above -- you need to be careful about
> how you lay the stuff out in memory.
> 
> Perhaps the gtod code won't end up being that big. It's around ~500 bytes on
> arm64, but that's without any stack usage.

That's still fairly large.

> Come to think of it, is there any
> reason why we can't just map an additional vectors page after the one we
> currently have?

That certainly can be done if necessary.  Some copy_page implementations 
do use some of the address space above the vector page for temporary 
page mapping so some care not to create conflicts would be required.


Nicolas


From khilman at linaro.org  Wed May 29 10:03:27 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 29 May 2013 07:03:27 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <51A5CCA5.7000700@ti.com> (Benoit Cousson's message of "Wed, 29
 May 2013 11:38:45 +0200")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <51A5CCA5.7000700@ti.com>
Message-ID: <87ehcpano0.fsf@linaro.org>

"Cousson, Benoit" <b-cousson at ti.com> writes:

[...]

>>
>> Let me respin this after some more doc reading.
>
> Did you re-spin it already?

Yes, v2 is here.  

http://marc.info/?l=linux-omap&m=136944147521955&w=2

It also needed a rework because the fref_clk0_out pin is also in the
wkup section of the padconf, not core.

Kevin


From arnd at arndb.de  Wed May 29 10:17:31 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 16:17:31 +0200
Subject: [PATCH V3 1/3] mmc: Add size for caller in init+register
In-Reply-To: <1369790016-13270-1-git-send-email-csd@broadcom.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
Message-ID: <201305291617.31983.arnd@arndb.de>

On Wednesday 29 May 2013, Christian Daudt wrote:
> Add a param to allow users of sdhci_pltfm to allocate private space
> in calls to sdhci_pltfm_init+sdhci_pltfm_register. This is implemented
> in the same way as sdhci does for its users.
>  None of the users have been migrated yet and are passing in zero to
> retain their private allocation.
> 
> - todo: migrate clients to using allocation this way
> - todo: remove priv variable once migration is complete
> 
> Also removed unused variable in sdhci_pltfm_init fn
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed May 29 10:19:28 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 16:19:28 +0200
Subject: [PATCH V3 1/3] mmc: Add size for caller in init+register
In-Reply-To: <CAPDyKFoPO0KTfW_i1EP8urSUT+U8yEaafrE2HdN2mmEkYCZm-w@mail.gmail.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
 <CAPDyKFoPO0KTfW_i1EP8urSUT+U8yEaafrE2HdN2mmEkYCZm-w@mail.gmail.com>
Message-ID: <201305291619.28396.arnd@arndb.de>

On Wednesday 29 May 2013, Ulf Hansson wrote:
> > diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
> > index 1210ed1..ed4a85d 100644
> > --- a/drivers/mmc/host/sdhci-pltfm.h
> > +++ b/drivers/mmc/host/sdhci-pltfm.h
> > @@ -27,6 +27,8 @@ struct sdhci_pltfm_host {
> >         /* migrate from sdhci_of_host */
> >         unsigned int clock;
> >         u16 xfer_mode_shadow;
> > +
> > +       unsigned long private[0] ____cacheline_aligned;
> 
> Why do you need this to be "____cacheline_aligned"?

This is common practice for additional members in data structures
like this. The reason is that we append a structure which
may have larger alignment requirements than 'unsigned long'.

The kmalloc function generally returns a cache line aligned
object, so this provides the same alignment that we get
with a separate allocation.

	Arnd


From ulf.hansson at linaro.org  Wed May 29 10:25:29 2013
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 29 May 2013 16:25:29 +0200
Subject: [PATCH V3 1/3] mmc: Add size for caller in init+register
In-Reply-To: <201305291619.28396.arnd@arndb.de>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
 <CAPDyKFoPO0KTfW_i1EP8urSUT+U8yEaafrE2HdN2mmEkYCZm-w@mail.gmail.com>
 <201305291619.28396.arnd@arndb.de>
Message-ID: <CAPDyKFqQCWdtwOVS2qoD0_k6ZW9NU=30kjEd4mQUesecmutqpg@mail.gmail.com>

On 29 May 2013 16:19, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 29 May 2013, Ulf Hansson wrote:
>> > diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
>> > index 1210ed1..ed4a85d 100644
>> > --- a/drivers/mmc/host/sdhci-pltfm.h
>> > +++ b/drivers/mmc/host/sdhci-pltfm.h
>> > @@ -27,6 +27,8 @@ struct sdhci_pltfm_host {
>> >         /* migrate from sdhci_of_host */
>> >         unsigned int clock;
>> >         u16 xfer_mode_shadow;
>> > +
>> > +       unsigned long private[0] ____cacheline_aligned;
>>
>> Why do you need this to be "____cacheline_aligned"?
>
> This is common practice for additional members in data structures
> like this. The reason is that we append a structure which
> may have larger alignment requirements than 'unsigned long'.
>
> The kmalloc function generally returns a cache line aligned
> object, so this provides the same alignment that we get
> with a separate allocation.
>
>         Arnd
>

Arnd, thanks for the explanation!

Reviewed-by: Ulf Hansson <ulf.hansson at linaro.org>

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
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From javi.merino at arm.com  Wed May 29 10:25:42 2013
From: javi.merino at arm.com (Javi Merino)
Date: Wed, 29 May 2013 15:25:42 +0100
Subject: [PATCH 7/8] ARM: vexpress/dcscb: handle platform coherency
 exit/setup and CCI
In-Reply-To: <1369830581.3715.50.camel@linaro1.home>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-8-git-send-email-nicolas.pitre@linaro.org>
 <1369830581.3715.50.camel@linaro1.home>
Message-ID: <20130529142541.GB2919@e102654-lin.cambridge.arm.com>

On Wed, May 29, 2013 at 01:29:41PM +0100, Jon Medhurst (Tixy) wrote:
> On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> > From: Dave Martin <dave.martin at linaro.org>
> > 
> > Add the required code to properly handle race free platform coherency exit
> > to the DCSCB power down method.
> > 
> > The power_up_setup callback is used to enable the CCI interface for
> > the cluster being brought up.  This must be done in assembly before
> > the kernel environment is entered.
> > 
> > Thanks to Achin Gupta and Nicolas Pitre for their help and
> > contributions.
> > 
> > Signed-off-by: Dave Martin <dave.martin at linaro.org>
> > Signed-off-by: Nicolas Pitre <nico at linaro.org>
> > Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > Acked-by: Pawel Moll <pawel.moll at arm.com>
> > ---
> >  arch/arm/mach-vexpress/Kconfig       |  1 +
> >  arch/arm/mach-vexpress/Makefile      |  2 +-
> >  arch/arm/mach-vexpress/dcscb.c       | 79 +++++++++++++++++++++++++++---------
> >  arch/arm/mach-vexpress/dcscb_setup.S | 38 +++++++++++++++++
> >  4 files changed, 100 insertions(+), 20 deletions(-)
> >  create mode 100644 arch/arm/mach-vexpress/dcscb_setup.S
> > 
> > diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> > index 2f46385c28..b8bbabec63 100644
> > --- a/arch/arm/mach-vexpress/Kconfig
> > +++ b/arch/arm/mach-vexpress/Kconfig
> > @@ -60,6 +60,7 @@ config ARCH_VEXPRESS_CA9X4
> >  config ARCH_VEXPRESS_DCSCB
> >  	bool "Dual Cluster System Control Block (DCSCB) support"
> >  	depends on MCPM
> > +	select ARM_CCI
> >  	help
> >  	  Support for the Dual Cluster System Configuration Block (DCSCB).
> >  	  This is needed to provide CPU and cluster power management
> > diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> > index 518519f57a..48ba89a814 100644
> > --- a/arch/arm/mach-vexpress/Makefile
> > +++ b/arch/arm/mach-vexpress/Makefile
> > @@ -6,6 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
> >  
> >  obj-y					:= v2m.o
> >  obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
> > -obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o
> > +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o	dcscb_setup.o
> >  obj-$(CONFIG_SMP)			+= platsmp.o
> >  obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
> > diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> > index b928b1f5eb..1acc975360 100644
> > --- a/arch/arm/mach-vexpress/dcscb.c
> > +++ b/arch/arm/mach-vexpress/dcscb.c
> > @@ -16,6 +16,7 @@
> >  #include <linux/errno.h>
> >  #include <linux/of_address.h>
> >  #include <linux/vexpress.h>
> > +#include <linux/arm-cci.h>
> >  
> >  #include <asm/mcpm.h>
> >  #include <asm/proc-fns.h>
> > @@ -105,7 +106,10 @@ static void dcscb_power_down(void)
> >  	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> >  	BUG_ON(cpu >= 4 || cluster >= 2);
> >  
> > +	__mcpm_cpu_going_down(cpu, cluster);
> > +
> >  	arch_spin_lock(&dcscb_lock);
> > +	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
> >  	dcscb_use_count[cpu][cluster]--;
> >  	if (dcscb_use_count[cpu][cluster] == 0) {
> >  		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> > @@ -125,31 +129,59 @@ static void dcscb_power_down(void)
> >  		skip_wfi = true;
> >  	} else
> >  		BUG();
> > -	arch_spin_unlock(&dcscb_lock);
> > -
> > -	/*
> > -	 * Now let's clean our L1 cache and shut ourself down.
> > -	 * If we're the last CPU in this cluster then clean L2 too.
> > -	 */
> >  
> > -	/*
> > -	 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> > -	 * a preliminary flush here for those CPUs.  At least, that's
> > -	 * the theory -- without the extra flush, Linux explodes on
> > -	 * RTSM (to be investigated)..
> > -	 */
> > -	flush_cache_louis();
> > -	set_cr(get_cr() & ~CR_C);
> > +	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
> > +		arch_spin_unlock(&dcscb_lock);
> >  
> > -	if (!last_man) {
> > -		flush_cache_louis();
> > -	} else {
> > +		/*
> > +		 * Flush all cache levels for this cluster.
> > +		 *
> > +		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> > +		 * a preliminary flush here for those CPUs.  At least, that's
> > +		 * the theory -- without the extra flush, Linux explodes on
> > +		 * RTSM (to be investigated).
> > +		 */
> > +		flush_cache_all();
> > +		set_cr(get_cr() & ~CR_C);
> >  		flush_cache_all();
> > +
> > +		/*
> > +		 * This is a harmless no-op.  On platforms with a real
> > +		 * outer cache this might either be needed or not,
> > +		 * depending on where the outer cache sits.
> > +		 */
> >  		outer_flush_all();
> > +
> > +		/* Disable local coherency by clearing the ACTLR "SMP" bit: */
> > +		set_auxcr(get_auxcr() & ~(1 << 6));
> > +
> > +		/*
> > +		 * Disable cluster-level coherency by masking
> > +		 * incoming snoops and DVM messages:
> > +		 */
> > +		cci_disable_port_by_cpu(mpidr);
> > +
> > +		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> > +	} else {
> > +		arch_spin_unlock(&dcscb_lock);
> > +
> > +		/*
> > +		 * Flush the local CPU cache.
> > +		 *
> > +		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> > +		 * a preliminary flush here for those CPUs.  At least, that's
> > +		 * the theory -- without the extra flush, Linux explodes on
> > +		 * RTSM (to be investigated).
> > +		 */
> > +		flush_cache_louis();
> > +		set_cr(get_cr() & ~CR_C);
> > +		flush_cache_louis();
> > +
> > +		/* Disable local coherency by clearing the ACTLR "SMP" bit: */
> > +		set_auxcr(get_auxcr() & ~(1 << 6));
> >  	}
> >  
> > -	/* Disable local coherency by clearing the ACTLR "SMP" bit: */
> > -	set_auxcr(get_auxcr() & ~(1 << 6));
> > +	__mcpm_cpu_down(cpu, cluster);
> >  
> >  	/* Now we are prepared for power-down, do it: */
> >  	dsb();
> > @@ -177,12 +209,17 @@ static void __init dcscb_usage_count_init(void)
> >  	dcscb_use_count[cpu][cluster] = 1;
> >  }
> >  
> > +extern void dcscb_power_up_setup(unsigned int affinity_level);
> > +
> >  static int __init dcscb_init(void)
> >  {
> >  	struct device_node *node;
> >  	unsigned int cfg;
> >  	int ret;
> >  
> > +	if (!cci_probed())
> > +		return -ENODEV;
> > +
> 
> I can't see where cci_probed() is defined, this seems to be the only
> occurrence in this patch set.

cci_probed() is defined in patch 1 of these series, in
include/linux/arm-cci.h and drivers/bus/arm-cci.c

Cheers,
Javi



From shawn.guo at linaro.org  Wed May 29 10:26:50 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 22:26:50 +0800
Subject: [PATCH v6 03/10] ASoC: imx-pcm-fiq: Introduce pcm-fiq-params
In-Reply-To: <1369752478-30260-4-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-4-git-send-email-mpa@pengutronix.de>
Message-ID: <20130529142648.GC29528@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 04:47:51PM +0200, Markus Pargmann wrote:
> @@ -47,7 +56,8 @@ static inline void imx_pcm_dma_exit(struct platform_device *pdev)
>  #endif
>  
>  #ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
> -int imx_pcm_fiq_init(struct platform_device *pdev);
> +int imx_pcm_fiq_init(struct platform_device *pdev,
> +		struct imx_pcm_fiq_params *params);
>  void imx_pcm_fiq_exit(struct platform_device *pdev);
>  #else
>  static inline int imx_pcm_fiq_init(struct platform_device *pdev)

This one also needs update with a new parameter.

Shawn



From arnd at arndb.de  Wed May 29 10:27:20 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 16:27:20 +0200
Subject: [PATCH V3 3/3] ARM: mmc: bcm281xx SDHCI driver (dt mods)
In-Reply-To: <1369790016-13270-3-git-send-email-csd@broadcom.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
 <1369790016-13270-3-git-send-email-csd@broadcom.com>
Message-ID: <201305291627.20984.arnd@arndb.de>

On Wednesday 29 May 2013, Christian Daudt wrote:
> +       sdio0: sdio at 0x3f180000 {
> +               max-frequency = <48000000>;
> +               status = "okay";
> +       };
> +

On a general note, there is no need to duplicate both the label and the
name here, one of the two is enough. The easiest way to write this
in a board file is

&sdio {
	max-frequency = <48000000>;
	status = "okay";
};

Your version is not wrong though, so

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed May 29 10:25:36 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 16:25:36 +0200
Subject: [PATCH V3 2/3] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1369790016-13270-2-git-send-email-csd@broadcom.com>
References: <1369790016-13270-1-git-send-email-csd@broadcom.com>
 <1369790016-13270-2-git-send-email-csd@broadcom.com>
Message-ID: <201305291625.37068.arnd@arndb.de>

On Wednesday 29 May 2013, Christian Daudt wrote:
> +static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
> +{

> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	mdelay(1);
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);

This is now called always without spinlocks held and interrupts enabled,
so it should really be msleep() not mdelay().

> +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
> +{
> +	unsigned int val;
> +
> +	/* enable the interrupt from the IP core */
> +	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
> +	val |= KONA_SDHOST_IP;
> +	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
> +
> +	/* Enable the AHB clock gating module to the host */
> +	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
> +	val |= KONA_SDHOST_EN;
> +
> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	mdelay(1);
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
> +}

Same here.

Looks good aside from that.

	Arnd


From khilman at linaro.org  Wed May 29 10:30:14 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 29 May 2013 07:30:14 -0700
Subject: build failure: linux-next: ARM/SH-mobile defconfigs: kota2, marzen
In-Reply-To: <20130529020550.GC16836@verge.net.au> (Simon Horman's message of
 "Wed, 29 May 2013 11:05:51 +0900")
References: <87txlmaf2a.fsf@linaro.org> <20130529020550.GC16836@verge.net.au>
Message-ID: <877gihamfd.fsf@linaro.org>

Simon Horman <horms at verge.net.au> writes:

> On Tue, May 28, 2013 at 03:57:01PM -0700, Kevin Hilman wrote:
>> Hello,
>> 
>> Both kota2_defconfig and marzen_defconfig started failing in the most
>> recnet linux-next (next-20130527) but were successful in the previous
>> build (next-20130523).
>> 
>> Both fail wit this error:
>> 
>> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
>> /work/kernel/next/drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to `shdma_chan_filter'
>> make[1]: *** [vmlinux] Error 1
>> make[1]: Target `_all' not remade because of errors.
>> 
>> Full build logs are available here:
>> 
>>   https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=kota2_defconfig,label=kernel_cloud/54/console
>>   https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=marzen_defconfig,label=kernel_cloud/54/console
>> 
>> Kevin
>
> Hi Kevin,
>
> thanks for bringing that to my attention.
> I'll fix it up.

I imagine it's the same issue, but in updating the list of defconfigs to
build, I noticed this same error in bockw_defconfig:

https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=bockw_defconfig,label=kernel_cloud/60/console

Kevin



From richard.genoud at gmail.com  Wed May 29 10:36:11 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 29 May 2013 16:36:11 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>

2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> Today we mix pdata and drivers data in the struct atmel_lcdfb_info
> Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: linux-fbdev at vger.kernel.org
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Andrew Morton <akpm at linux-foundation.org>
> Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> ---
>  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
>  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
>  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
>  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
>  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
>  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
>  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
>  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
>  arch/arm/mach-at91/board.h                  |    4 +-
>  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
>  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
>  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
>  arch/avr32/boards/atstk1000/setup.c         |    2 +-
>  arch/avr32/boards/favr-32/setup.c           |    2 +-
>  arch/avr32/boards/hammerhead/setup.c        |    2 +-
>  arch/avr32/boards/merisc/display.c          |    2 +-
>  arch/avr32/boards/mimc200/setup.c           |    4 +-
>  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
>  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
>  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
>  include/video/atmel_lcdc.h                  |   24 +------
>  21 files changed, 109 insertions(+), 101 deletions(-)
>
[snip]
> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> index c1a2914..98733cd4 100644
> --- a/drivers/video/atmel_lcdfb.c
> +++ b/drivers/video/atmel_lcdfb.c
> @@ -20,12 +20,45 @@
>  #include <linux/gfp.h>
>  #include <linux/module.h>
>  #include <linux/platform_data/atmel.h>
> +#include <video/of_display_timing.h>
>
>  #include <mach/cpu.h>
>  #include <asm/gpio.h>
>
>  #include <video/atmel_lcdc.h>
>
> +struct atmel_lcdfb_config {
> +       bool have_alt_pixclock;
> +       bool have_hozval;
> +       bool have_intensity_bit;
> +};
> +
> + /* LCD Controller info data structure, stored in device platform_data */
> +struct atmel_lcdfb_info {
> +       spinlock_t              lock;
> +       struct fb_info          *info;
> +       void __iomem            *mmio;
> +       int                     irq_base;
> +       struct work_struct      task;
> +
> +       unsigned int            smem_len;
> +       struct platform_device  *pdev;
> +       struct clk              *bus_clk;
> +       struct clk              *lcdc_clk;
> +
> +       struct backlight_device *backlight;
> +       u8                      bl_power;
> +       bool                    lcdcon_pol_negative;
I think lcdcon_pol_negative should be part of pdata, because it really
depends on how the PWM is wired on the board.


Regards,
Richard.


From nico at fluxnic.net  Wed May 29 10:39:04 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 29 May 2013 10:39:04 -0400 (EDT)
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130529103728.GG17767@MacBook-Pro.local>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
 <20130528095528.GA14329@arm.com>
 <alpine.LFD.2.03.1305281340240.1918@syhkavp.arg>
 <20130529103728.GG17767@MacBook-Pro.local>
Message-ID: <alpine.LFD.2.03.1305291038220.1918@syhkavp.arg>

On Wed, 29 May 2013, Catalin Marinas wrote:

> On Tue, May 28, 2013 at 06:52:27PM +0100, Nicolas Pitre wrote:
> > On Tue, 28 May 2013, Catalin Marinas wrote:
> > 
> > > On Sat, May 25, 2013 at 04:53:19AM +0100, Nicolas Pitre wrote:
> > > > On Thu, 23 May 2013, Catalin Marinas wrote:
> > > > 
> > > > > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > > > > twice. I don't think we should remove the cache flushing in
> > > > > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > > > > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > > > > don't work together).
> > > > 
> > > > VIVT and highmem do work together.  Highmem for ARM was in fact 
> > > > developed on such a platform.
> > > 
> > > Thanks for confirming. Do you remember why kunmap() doesn't (need to)
> > > flush the cache alias (for VIVT)? Or if it does, where?
> > 
> > kunmap() calls kunmap_high() which actually does not unmap anything but 
> > only decrement a use count.  The page is kept around in case it is 
> > kmap()'d again, in which case the kmap() will be almost free and the 
> > page still warm.
> > 
> > It is only when the kmap() for a new page runs out of free pkmap  
> > entries that the unused but still mapped pages are unmapped.  This 
> > unmapping is done in flush_all_zero_pkmaps() where all the unused pages 
> > are all unmapped at once.  The cache for all those pages is flushed with 
> > flush_cache_kmaps() which on ARM maps to flush_cache_all() when the 
> > cache is VIVT.
> 
> Thanks for clarification Nico. So if kmap_high_get() returns NULL, there
> are no high aliases left in the cache.

Exact.


Nicolas


From shawn.guo at linaro.org  Wed May 29 10:42:58 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 22:42:58 +0800
Subject: [PATCH] ARM: mxs: icoll: Fix interrupts gpio bank 0
In-Reply-To: <1369753257-11091-1-git-send-email-mpa@pengutronix.de>
References: <1369753257-11091-1-git-send-email-mpa@pengutronix.de>
Message-ID: <20130529144256.GD29528@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 05:00:57PM +0200, Markus Pargmann wrote:
> The mxs interrupt controller does not support polling for interrupts,
> but the driver still does it, which is a relict from
> pre-MULTI_IRQ_HANDLER times.
> 
> The existing code assumes that 0x7f means no interrupt, but this value
> is an actually valid irq number, namely gpio bank 0's irq. This results
> in the driver not detecting when irq 0x7f is active which makes the
> machine effectively dead lock.
> 
> This patch removes the interrupt poll loop and allows usage of gpio0
> interrupt without an infinite loop.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> Cc: stable at vger.kernel.org

Thomas, can you please help handle the fix?  If yes, here is my ack.

Acked-by: Shawn Guo <shawn.guo at linaro.org>

Otherwise, I can send it through arm-soc tree if you're fine with it.

Shawn

> ---
>  drivers/irqchip/irq-mxs.c | 14 ++++----------
>  1 file changed, 4 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
> index 29889bb..63b3d4e 100644
> --- a/drivers/irqchip/irq-mxs.c
> +++ b/drivers/irqchip/irq-mxs.c
> @@ -76,16 +76,10 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
>  {
>  	u32 irqnr;
>  
> -	do {
> -		irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
> -		if (irqnr != 0x7f) {
> -			__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
> -			irqnr = irq_find_mapping(icoll_domain, irqnr);
> -			handle_IRQ(irqnr, regs);
> -			continue;
> -		}
> -		break;
> -	} while (1);
> +	irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
> +	__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
> +	irqnr = irq_find_mapping(icoll_domain, irqnr);
> +	handle_IRQ(irqnr, regs);
>  }
>  
>  static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
> -- 
> 1.8.2.rc2
> 



From nicolas.pitre at linaro.org  Wed May 29 10:49:33 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 29 May 2013 10:49:33 -0400 (EDT)
Subject: [PATCH 1/8] drivers: bus: add ARM CCI support
In-Reply-To: <1369829485.3715.46.camel@linaro1.home>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-2-git-send-email-nicolas.pitre@linaro.org>
 <1369829485.3715.46.camel@linaro1.home>
Message-ID: <alpine.LFD.2.03.1305291049000.1918@syhkavp.arg>

On Wed, 29 May 2013, Jon Medhurst (Tixy) wrote:

> On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> [...]
> > diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
> [...]
> > +	cci at 2c090000 {
> > +		compatible = "arm,cci-400";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x0 0x2c090000 0 0x1000>;
> > +		ranges = <0x0 0x0 0x2c090000 0x6000>;
> > +
> > +		cci_control0: slave-if at 1000 {
> > +			interface-type = "ace-lite";
> > +			reg = <0x1000 0x1000>;
> > +		};
> > +
> > +		cci_control1: slave-if at 4000 {
> > +			interface-type = "ace";
> > +			reg = <0x4000 0x1000>;
> > +		};
> > +
> > +		cci_control2: slave-if at 5000 {
> > +			interface-type = "ace";
> > +			reg = <0x5000 0x1000>;
> > +		};
> > +	};
> 
> The above examples of slave-if nodes are missing the required
> compatible = "arm,cci-400-ctrl-if";

Indeed.  I'll fix that.


Nicolas


From broonie at kernel.org  Wed May 29 10:49:09 2013
From: broonie at kernel.org (Mark Brown)
Date: Wed, 29 May 2013 15:49:09 +0100
Subject: [PATCH] SPI: Unify simple platform data for some controllers
In-Reply-To: <201305291526.35099.arnd@arndb.de>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <1369817353.993218858@f175.mail.ru>
 <20130529112002.GS3660@sirena.org.uk>
 <201305291526.35099.arnd@arndb.de>
Message-ID: <20130529144909.GT3660@sirena.org.uk>

On Wed, May 29, 2013 at 03:26:34PM +0200, Arnd Bergmann wrote:
> On Wednesday 29 May 2013, Mark Brown wrote:

> > We probably also want to make
> > GPIO chip select support a standard thing that's available with every
> > driver rather than something the driver has to know about but that's a
> > separate bit of work.

> That actually seems simpler than doing it in just one driver: if
> we add a cs_gpio field to spi_board_info, spi_new_device could
> just copy that information into the new spi_device instead of
> taking it from master->cs_gpios.

Yeah, that bit of it is fine and straightforward.  It's slightly more
work to factor the chip select handling out so that we can implement the
handling at the appropriate moments in the flow due to the fact that
it's embedded in the message transfer functions but totally doable.
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From eduardo.valentin at ti.com  Wed May 29 10:11:00 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 29 May 2013 10:11:00 -0400
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <5194D0AF.3010407@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com> <519488D3.5070003@ti.com>
 <5194D0AF.3010407@ti.com>
Message-ID: <51A60C74.4010307@ti.com>

Salut Monsieur Benoit,

On 16-05-2013 08:27, Eduardo Valentin wrote:
> On 16-05-2013 03:20, Benoit Cousson wrote:
>> Hi Eduardo,
>>

<cut>

>> We need to check.
>>
> 
> 
> Yeah, I also dont think this will work, because we will reparent the
> interrupt, setting to a different controller. That will break the TALERT
> signal already defined at GIC (check original patch).
> 
> I propose keeping the way I sent. Unless there is a way to set two
> different controllers to same device.
> 

Any idea on this patch? Shall we keep the way it is?


>> Regards,
>> Benoit
>>
>>
>>>> Where is the gpio controller phandle?
>>>>
>>>> Usually it looks like this:
>>>>
>>>> 	gpios = <&gpio1 8 0>;
>>>>
>>>>
>>>> Regards,
>>>> Benoit
>>>>
>>>>
>>>>
>>>
>>>
>>
>>
>>
> 
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin

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From b-cousson at ti.com  Wed May 29 10:19:42 2013
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 29 May 2013 16:19:42 +0200
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <51A60C74.4010307@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com> <519488D3.5070003@ti.com>
 <5194D0AF.3010407@ti.com> <51A60C74.4010307@ti.com>
Message-ID: <51A60E7E.2070905@ti.com>

Hi Eduardo,

On 5/29/2013 4:11 PM, Eduardo Valentin wrote:
> Salut Monsieur Benoit,
>
> On 16-05-2013 08:27, Eduardo Valentin wrote:
>> On 16-05-2013 03:20, Benoit Cousson wrote:
>>> Hi Eduardo,
>>>
>
> <cut>
>
>>> We need to check.
>>
>> Yeah, I also dont think this will work, because we will reparent the
>> interrupt, setting to a different controller. That will break the TALERT
>> signal already defined at GIC (check original patch).
>>
>> I propose keeping the way I sent. Unless there is a way to set two
>> different controllers to same device.
>>
>
> Any idea on this patch? Shall we keep the way it is?

Well since we cannot use directly interrupt, I think we need to use at 
least the proper gpio binding.

Thanks,
Benoit



From ming.lei at canonical.com  Wed May 29 10:56:56 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Wed, 29 May 2013 22:56:56 +0800
Subject: [PATCH V1] ARM: mm: lazy cache flushing on non-mapped pages
Message-ID: <1369839416-27817-1-git-send-email-ming.lei@canonical.com>

Currently flush_dcache_page() thinks pages as non-mapped if
mapping_mapped(mapping) return false. This approach is very
coase:
	- mmap on part of file may cause all pages backed on
	the file being thought as mmaped

	- file-backed pages aren't mapped into user space actually
	if the memory mmaped on the file isn't accessed

This patch uses page_mapped() to decide if the page has been
mapped.

>From the attached test code, I find there is much performance
improvement(>25%) when accessing page caches via read under this
situations, so memcpy benefits a lot from not flushing cache
under this situation.

No.   read time without the patch	No. read time with the patch
================================================================
No. 0, time  22615636 us		No. 0, time  22014717 us
No. 1, time  4387851 us 		No. 1, time  3113184 us
No. 2, time  4276535 us 		No. 2, time  3005244 us
No. 3, time  4259821 us 		No. 3, time  3001565 us
No. 4, time  4263811 us 		No. 4, time  3002748 us
No. 5, time  4258486 us 		No. 5, time  3004104 us
No. 6, time  4253009 us 		No. 6, time  3002188 us
No. 7, time  4262809 us 		No. 7, time  2998196 us
No. 8, time  4264525 us 		No. 8, time  3007255 us
No. 9, time  4267795 us 		No. 9, time  3005094 us

1), No.0. is to read the file from storage device, and others are
to read the file from page caches basically.
2), file size is 512M, and is on ext4 over usb mass storage.
3), the test is done on Pandaboard.

unsigned int  sum = 0;
unsigned long sum_val = 0;

static unsigned long tv_diff(struct timeval *tv1, struct timeval *tv2)
{
	return (tv2->tv_sec - tv1->tv_sec) * 1000000 +
		(tv2->tv_usec - tv1->tv_usec);
}

int main(int argc, char *argv[])
{
	char *mbuf, fbuf;
	int fd;
	int i;
	unsigned long page_size, size;
	struct stat stat;
	struct timeval t1, t2;
	unsigned char *rbuf = malloc(32 * page_size);

	if (!rbuf) {
		printf("	%s\n", "malloc failed");
		exit(-1);
	}

	page_size = getpagesize();
	fd = open(argv[1], O_RDWR);
	assert(fd >= 0);

	fstat(fd, &stat);
	size = stat.st_size;
	printf("%s: file %s, size %lu, page size %lu\n",
		argv[0],
		argv[1], size, page_size);

	gettimeofday(&t1, NULL);
	mbuf = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
	if (!mbuf) {
		printf("	%s\n", "mmap failed");
		exit(-1);
	}

	for (i = 0 ; i < size ; i += (page_size * 32)) {
		int rcnt;
		lseek(fd, i, SEEK_SET);
		rcnt = read(fd, rbuf, page_size * 32);
		if (rcnt != page_size * 32) {
			printf("%s: read faild\n", __func__);
			exit(-1);
		}
	}
	free(rbuf);
	munmap(mbuf, size);
	gettimeofday(&t2, NULL);
	printf("\tread mmaped time: %luus\n", tv_diff(&t1, &t2));

	close(fd);
}

Cc: Michel Lespinasse <walken at google.com>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Ming Lei <ming.lei at canonical.com>
---
V1:
	- take Catalin's suggestion to use page_mapped()

 arch/arm/mm/flush.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 0d473cc..008af99 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -286,8 +286,8 @@ void flush_dcache_page(struct page *page)
 
 	mapping = page_mapping(page);
 
-	if (!cache_ops_need_broadcast() &&
-	    mapping && !mapping_mapped(mapping))
+	if (!cache_ops_need_broadcast() && mapping &&
+		(!mapping_mapped(mapping) || !page_mapped(page)))
 		clear_bit(PG_dcache_clean, &page->flags);
 	else {
 		__flush_dcache_page(mapping, page);
-- 
1.7.9.5



From shawn.guo at linaro.org  Wed May 29 10:59:46 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 29 May 2013 22:59:46 +0800
Subject: [PATCH] ARM: fix kernel decompressor compilation error with
 CONFIG_DEBUG_SEMIHOSTING
In-Reply-To: <alpine.LFD.2.03.1305281654120.1918@syhkavp.arg>
References: <alpine.LFD.2.03.1305281654120.1918@syhkavp.arg>
Message-ID: <20130529145944.GE29528@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 04:59:13PM -0400, Nicolas Pitre wrote:
> 
> ... and add semihosting output support to the decompressor while at it.
> 
> Signed-off-by: Nicolas Pitre <nico at linaro.org>

Acked-by: Shawn Guo <shawn.guo at linaro.org>

Maybe include the error output in commit log.

  AS      arch/arm/boot/compressed/debug.o
arch/arm/boot/compressed/debug.S:4:33: fatal error: mach/debug-macro.S: No such file or directory
compilation terminated.
make[3]: *** [arch/arm/boot/compressed/debug.o] Error 1

Shawn

> 
> diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
> index 6e8382d5b7..5392ee6333 100644
> --- a/arch/arm/boot/compressed/debug.S
> +++ b/arch/arm/boot/compressed/debug.S
> @@ -1,6 +1,8 @@
>  #include <linux/linkage.h>
>  #include <asm/assembler.h>
>  
> +#ifndef CONFIG_DEBUG_SEMIHOSTING
> +
>  #include CONFIG_DEBUG_LL_INCLUDE
>  
>  ENTRY(putc)
> @@ -10,3 +12,29 @@ ENTRY(putc)
>  	busyuart r3, r1
>  	mov	 pc, lr
>  ENDPROC(putc)
> +
> +#else
> +
> +ENTRY(putc)
> +	adr	r1, 1f
> +	ldmia	r1, {r2, r3}
> +	add	r2, r2, r1
> +	ldr	r1, [r2, r3]
> +	strb	r0, [r1]
> +	mov	r0, #0x03		@ SYS_WRITEC
> +   ARM(	svc	#0x123456	)
> + THUMB(	svc	#0xab		)
> +	mov	pc, lr
> +	.align	2
> +1:	.word	_GLOBAL_OFFSET_TABLE_ - .
> +	.word	semi_writec_buf(GOT)
> +ENDPROC(putc)
> +
> +	.bss
> +	.global	semi_writec_buf
> +	.type   semi_writec_buf, %object
> +semi_writec_buf:
> +	.space	4
> +	.size	semi_writec_buf, 4
> +
> +#endif



From richard.genoud at gmail.com  Wed May 29 11:01:58 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 29 May 2013 17:01:58 +0200
Subject: [PATCH 4/8] video: atmel_lcdfb: add device tree suport
In-Reply-To: <1365692422-9565-4-git-send-email-plagnioj@jcrosoft.com>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <1365692422-9565-4-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACQ1gAhbnsrmCzdv0KNDMN153+0F_8cwNPZUz=SF8sKUPbty3g@mail.gmail.com>

2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> get display timings from device tree
> Use videomode helpers to get display timings and configurations from
> device tree
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: linux-fbdev at vger.kernel.org
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Andrew Morton <akpm at linux-foundation.org>
> ---
>  .../devicetree/bindings/video/atmel,lcdc.txt       |   75 ++++++
>  drivers/video/Kconfig                              |    2 +
>  drivers/video/atmel_lcdfb.c                        |  244 +++++++++++++++++---
>  3 files changed, 289 insertions(+), 32 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/video/atmel,lcdc.txt
>
> diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
> new file mode 100644
> index 0000000..1ec175e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
> @@ -0,0 +1,75 @@
> +Atmel LCDC Framebuffer
> +-----------------------------------------------------
> +
> +Required properties:
> +- compatible :
> +       "atmel,at91sam9261-lcdc" ,
> +       "atmel,at91sam9263-lcdc" ,
> +       "atmel,at91sam9g10-lcdc" ,
> +       "atmel,at91sam9g45-lcdc" ,
> +       "atmel,at91sam9g45es-lcdc" ,
> +       "atmel,at91sam9rl-lcdc" ,
> +       "atmel,at32ap-lcdc"
> +- reg : Should contain 1 register ranges(address and length)
> +- interrupts : framebuffer controller interrupt
> +- display: a phandle pointing to the display node
> +
> +Required nodes:
> +- display: a display node is required to initialize the lcd panel
> +       This should be in the board dts.
> +- default-mode: a videomode within the display with timing parameters
> +       as specified below.
> +
> +Example:
> +
> +       fb0: fb at 0x00500000 {
> +               compatible = "atmel,at91sam9g45-lcdc";
> +               reg = <0x00500000 0x1000>;
> +               interrupts = <23 3 0>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pinctrl_fb>;
> +               display = <&display0>;
> +               status = "okay";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +
> +       };
> +
> +Atmel LCDC Display
> +-----------------------------------------------------
> +Required properties (as per of_videomode_helper):
> +
> + - atmel,dmacon: dma controler configuration
> + - atmel,lcdcon2: lcd controler configuration
> + - atmel,guard-time: lcd guard time (Delay in frame periods)
> + - bits-per-pixel: lcd panel bit-depth.
> +
> +Optional properties (as per of_videomode_helper):
> + - atmel,lcdcon-backlight: enable backlight
> + - atmel,lcd-wiring-mode: lcd wiring mode "RGB" or "BRG"
> + - atmel,power-control-gpio: gpio to power on or off the LCD (as many as needed)
still on lcdcon_pol_negative, we can add something like that:
 - atmel,lcdcon-pwm-pulse-low: Output PWM pulses are low level (high
level if not set)

> +
> +Example:
> +       display0: display {
> +               bits-per-pixel = <32>;
> +               atmel,lcdcon-backlight;
> +               atmel,dmacon = <0x1>;
> +               atmel,lcdcon2 = <0x80008002>;
> +               atmel,guard-time = <9>;
> +               atmel,lcd-wiring-mode = <1>;
> +
> +               display-timings {
> +                       native-mode = <&timing0>;
> +                       timing0: timing0 {
> +                               clock-frequency = <9000000>;
> +                               hactive = <480>;
> +                               vactive = <272>;
> +                               hback-porch = <1>;
> +                               hfront-porch = <1>;
> +                               vback-porch = <40>;
> +                               vfront-porch = <1>;
> +                               hsync-len = <45>;
> +                               vsync-len = <1>;
> +                       };
> +               };
> +       };
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 4c1546f..0687482 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -1018,6 +1018,8 @@ config FB_ATMEL
>         select FB_CFB_FILLRECT
>         select FB_CFB_COPYAREA
>         select FB_CFB_IMAGEBLIT
> +       select FB_MODE_HELPERS
> +       select OF_VIDEOMODE
>         help
>           This enables support for the AT91/AT32 LCD Controller.
>
> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> index f67e226..4a31570 100644
> --- a/drivers/video/atmel_lcdfb.c
> +++ b/drivers/video/atmel_lcdfb.c
> @@ -20,7 +20,11 @@
>  #include <linux/gfp.h>
>  #include <linux/module.h>
>  #include <linux/platform_data/atmel.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
>  #include <video/of_display_timing.h>
> +#include <video/videomode.h>
>
>  #include <mach/cpu.h>
>  #include <asm/gpio.h>
> @@ -59,6 +63,13 @@ struct atmel_lcdfb_info {
>         struct atmel_lcdfb_config *config;
>  };
>
> +struct atmel_lcdfb_power_ctrl_gpio {
> +       int gpio;
> +       int active_low;
> +
> +       struct list_head list;
> +};
> +
>  #define lcdc_readl(sinfo, reg)         __raw_readl((sinfo)->mmio+(reg))
>  #define lcdc_writel(sinfo, reg, val)   __raw_writel((val), (sinfo)->mmio+(reg))
>
> @@ -945,16 +956,187 @@ static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
>         clk_disable(sinfo->lcdc_clk);
>  }
>
> +#ifdef CONFIG_OF
> +static const struct of_device_id atmel_lcdfb_dt_ids[] = {
> +       { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
> +       { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
> +       { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
> +       { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
> +       { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
> +       { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
> +       { .compatible = "atmel,at32ap-lcdc" , .data = &at32ap_config, },
> +       { /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmel_lcdfb_dt_ids);
> +
> +static const char *atmel_lcdfb_wiring_modes[] = {
> +       [ATMEL_LCDC_WIRING_BGR] = "BRG",
> +       [ATMEL_LCDC_WIRING_RGB] = "RGB",
> +};
> +
> +const int atmel_lcdfb_get_of_wiring_modes(struct device_node *np)
> +{
> +       const char *mode;
> +       int err, i;
> +
> +       err = of_property_read_string(np, "atmel,lcd-wiring-mode", &mode);
> +       if (err < 0)
> +               return ATMEL_LCDC_WIRING_BGR;
> +
> +       for (i = 0; i < ARRAY_SIZE(atmel_lcdfb_wiring_modes); i++)
> +               if (!strcasecmp(mode, atmel_lcdfb_wiring_modes[i]))
> +                       return i;
> +
> +       return -ENODEV;
> +}
> +
> +static void atmel_lcdfb_power_control_gpio(struct atmel_lcdfb_pdata *pdata, int on)
> +{
> +       struct atmel_lcdfb_power_ctrl_gpio *og;
> +
> +       list_for_each_entry(og, &pdata->pwr_gpios, list)
> +               gpio_set_value(og->gpio, on);
> +}
> +
> +static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo)
> +{
> +       struct fb_info *info = sinfo->info;
> +       struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
> +       struct fb_var_screeninfo *var = &info->var;
> +       struct device *dev = &sinfo->pdev->dev;
> +       struct device_node *np =dev->of_node;
> +       struct device_node *display_np;
> +       struct device_node *timings_np;
> +       struct display_timings *timings;
> +       enum of_gpio_flags flags;
> +       struct atmel_lcdfb_power_ctrl_gpio *og;
> +       bool is_gpio_power = false;
> +       int ret = -ENOENT;
> +       int i, gpio;
> +
> +       sinfo->config = (struct atmel_lcdfb_config*)
> +               of_match_device(atmel_lcdfb_dt_ids, dev)->data;
> +
> +       display_np = of_parse_phandle(np, "display", 0);
> +       if (!display_np) {
> +               dev_err(dev, "failed to find display phandle\n");
> +               return -ENOENT;
> +       }
> +
> +       ret = of_property_read_u32(display_np, "bits-per-pixel", &var->bits_per_pixel);
> +       if (ret < 0) {
> +               dev_err(dev, "failed to get property bits-per-pixel\n");
> +               goto put_display_node;
> +       }
> +
> +       ret = of_property_read_u32(display_np, "atmel,guard-time", &pdata->guard_time);
> +       if (ret < 0) {
> +               dev_err(dev, "failed to get property atmel,guard-time\n");
> +               goto put_display_node;
> +       }
> +
> +       ret = of_property_read_u32(display_np, "atmel,lcdcon2", &pdata->default_lcdcon2);
> +       if (ret < 0) {
> +               dev_err(dev, "failed to get property atmel,lcdcon2\n");
> +               goto put_display_node;
> +       }
> +
> +       ret = of_property_read_u32(display_np, "atmel,dmacon", &pdata->default_dmacon);
> +       if (ret < 0) {
> +               dev_err(dev, "failed to get property bits-per-pixel\n");
> +               goto put_display_node;
> +       }
> +
> +       ret = -ENOMEM;
> +       for (i = 0; i < of_gpio_named_count(display_np, "atmel,power-control-gpio"); i++) {
> +               gpio = of_get_named_gpio_flags(display_np, "atmel,power-control-gpio",
> +                                              i, &flags);
> +               if (gpio < 0)
> +                       continue;
> +
> +               og = devm_kzalloc(dev, sizeof(*og), GFP_KERNEL);
> +               if (!og)
> +                       goto put_display_node;
> +
> +               og->gpio = gpio;
> +               og->active_low = flags & OF_GPIO_ACTIVE_LOW;
> +               is_gpio_power = true;
> +               ret = devm_gpio_request(dev, gpio, "lcd-power-control-gpio");
> +               if (ret) {
> +                       dev_err(dev, "request gpio %d failed\n", gpio);
> +                       goto put_display_node;
> +               }
> +
> +               ret = gpio_direction_output(gpio, og->active_low);
> +               if (ret) {
> +                       dev_err(dev, "set direction output gpio %d failed\n", gpio);
> +                       goto put_display_node;
> +               }
> +       }
> +
> +       if (is_gpio_power)
> +               pdata->atmel_lcdfb_power_control = atmel_lcdfb_power_control_gpio;
> +
> +       ret = atmel_lcdfb_get_of_wiring_modes(display_np);
> +       if (ret < 0) {
> +               dev_err(dev, "invalid atmel,lcd-wiring-mode\n");
> +               goto put_display_node;
> +       }
> +       pdata->lcd_wiring_mode = ret;
> +
> +       pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight");

and here, something like:
pdata->lcdcon_pol_negative = of_property_read_bool(display_np,
"atmel,lcdcon-pwm-pulse-low");
would be nice


Regards,
Richard.


From b-cousson at ti.com  Wed May 29 10:23:37 2013
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 29 May 2013 16:23:37 +0200
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ
 pin and msecure line
In-Reply-To: <87ehcpano0.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <51A5CCA5.7000700@ti.com>
 <87ehcpano0.fsf@linaro.org>
Message-ID: <51A60F69.7050203@ti.com>

On 5/29/2013 4:03 PM, Kevin Hilman wrote:
> "Cousson, Benoit" <b-cousson at ti.com> writes:
>
> [...]
>
>>>
>>> Let me respin this after some more doc reading.
>>
>> Did you re-spin it already?
>
> Yes, v2 is here.
>
> http://marc.info/?l=linux-omap&m=136944147521955&w=2
>
> It also needed a rework because the fref_clk0_out pin is also in the
> wkup section of the padconf, not core.

OK, I'll wait for the v3 then :-)

Benoit



From liuj97 at gmail.com  Wed May 29 11:08:53 2013
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed, 29 May 2013 23:08:53 +0800
Subject: [PATCH, v2 2/5] mm/ARM: fix stale comment about VALID_PAGE()
In-Reply-To: <1369840136-1491-1-git-send-email-jiang.liu@huawei.com>
References: <1369840136-1491-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1369840136-1491-3-git-send-email-jiang.liu@huawei.com>

VALID_PAGE() has been removed from kernel long time ago,
so fix the comment.

Signed-off-by: Jiang Liu <jiang.liu at huawei.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Nicolas Pitre <nico at linaro.org>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/include/asm/memory.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 57870ab..0cd2a3d 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -260,12 +260,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 /*
  * Conversion between a struct page and a physical address.
  *
- * Note: when converting an unknown physical address to a
- * struct page, the resulting pointer must be validated
- * using VALID_PAGE().  It must return an invalid struct page
- * for any physical address not corresponding to a system
- * RAM address.
- *
  *  page_to_pfn(page)	convert a struct page * to a PFN number
  *  pfn_to_page(pfn)	convert a _valid_ PFN number to struct page *
  *
-- 
1.8.1.2



From catalin.marinas at arm.com  Wed May 29 11:15:55 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 29 May 2013 16:15:55 +0100
Subject: Single zImage and A15/LPAE
In-Reply-To: <2274563.opVbLLPT1p@wuerfel>
References: <50735B75.8070109@wwwdotorg.org>
 <alpine.LFD.2.03.1305282148560.1918@syhkavp.arg>
 <CAOesGMh+XHueA0UtnAzYTkysqdLqs93Bp31KJKsqVBa-LkiQbQ@mail.gmail.com>
 <2274563.opVbLLPT1p@wuerfel>
Message-ID: <20130529151555.GP17767@MacBook-Pro.local>

On Wed, May 29, 2013 at 02:01:05PM +0100, Arnd Bergmann wrote:
> On Tuesday 28 May 2013 19:02:48 Olof Johansson wrote:
> > On Tue, May 28, 2013 at 6:54 PM, Nicolas Pitre <nicolas.pitre at linaro.org> wrote:
> > > On Wed, 29 May 2013, Kukjin Kim wrote:
> > >> (+ Olof, Russell)
> > >>
> > >> Just note, I found this in my old mail-box...
> > >>
> > >> So I think, as a result, we need to support separate kernel binary for LPAE
> > >> and non-LPAE and you guys don't hold a different view about it.
> > >
> > > LPAE and non-LPAE configurations will most likely never be supported
> > > together in the same kernel binary.  The runtime cost would simply be
> > > too high to be worth it.
> > >
> > >> Current SSDK5440 and SD5v1 boards which are reference boards for EXYNOS5440
> > >> has over 4GB memory as a default and that's why I'm writing this e-mail. It
> > >> means I should keep separated kernel to support exynos5440 and other exynos
> > >> SoCs.
> > >
> > > They could all be supported together but with less than 4GB of memory.
> > 
> > Or the other way around, the other EXYNOS5 CPUs could all enable LPAE
> > even if they have less than 4GB of memory -- but not EXYNOS4, of
> > course.
> 
> The one bug I see is that it's currently possible to build a kernel
> for a Cortex-A5/A8/A9, Scorpion or PJ4 platform with LPAE enabled,
> which obviously cannot work.
> 
> I think to do this right, we need to treat ARMv7+LPAE as a separate
> architecture level, just like we treat ARMv6, ARMv7 as separate
> compatible architectures. BTW, is there an official name for that
> architecture?

The official is Large Physical Address Extension which is an extension
to ARMv7, so not a new architecture.

-- 
Catalin


From nicolas.pitre at linaro.org  Wed May 29 11:17:18 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 29 May 2013 11:17:18 -0400 (EDT)
Subject: [PATCH 8/8] ARM: vexpress/dcscb: select multi-cluster SMP
 operations
In-Reply-To: <1369824504.3715.23.camel@linaro1.home>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-9-git-send-email-nicolas.pitre@linaro.org>
 <1369824504.3715.23.camel@linaro1.home>
Message-ID: <alpine.LFD.2.03.1305291054150.1918@syhkavp.arg>

On Wed, 29 May 2013, Jon Medhurst (Tixy) wrote:

> On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> > When the DCSCB code is successfully probed and initialized, then the
> > generic MCPM SPM ops should be used as those operations need to be
> > arbitrated through the MCPM layer.
> > 
> > Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
> > ---
> >  arch/arm/mach-vexpress/dcscb.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> > index 1acc975360..ce3118dc05 100644
> > --- a/arch/arm/mach-vexpress/dcscb.c
> > +++ b/arch/arm/mach-vexpress/dcscb.c
> > @@ -239,6 +239,8 @@ static int __init dcscb_init(void)
> >  		return ret;
> >  	}
> >  
> > +	mcpm_smp_set_ops();
> > +
> 
> This is going to change the platform's smp_ops after setup_arch() has
> already set them, is that OK and not too late?

Well...  The only methods being invoked before the booting of secondary 
CPUs are smp_init_cpus and smp_prepare_cpus.  In the MCPM case they're 
both no-ops.

> I ask, because for me, RTSM doesn't boot the secondary CPUs if we rely
> on this change to set the smp_ops, but having a hook in setup_arch() to
> select instead of the standard vexpress ops does work.

Strange.  That works for me both ways.

I did it this way because the alternative probe for a CCI in unrelated 
code in order to install the MCPM ops and this really looks awkward.  
And it won't work if for example PSCI mode decides not to let Linux see 
the CCI.

Is there something in the default vexpress smp_init_cpus and 
smp_prepare_cpus code that could prevent booting through MCPM later on?


Nicolas


From aida.mynzhasova at skitlab.ru  Wed May 29 11:19:20 2013
From: aida.mynzhasova at skitlab.ru (Aida Mynzhasova)
Date: Wed, 29 May 2013 19:19:20 +0400
Subject: [PATCH] ARM: OMAP: fix IVA2 module base address
In-Reply-To: <87bo7vdvo2.fsf@linaro.org>
References: <1369741577-21984-1-git-send-email-aida.mynzhasova@skitlab.ru>
 <87bo7vdvo2.fsf@linaro.org>
Message-ID: <51A61C78.3020409@skitlab.ru>

On 28.05.2013 18:30, Kevin Hilman wrote:
> Aida Mynzhasova <aida.mynzhasova at skitlab.ru> writes:
>
>> This patch corrects the base address of IVA2 module on omap3430.
>>
>> Signed-off-by: Aida Mynzhasova <aida.mynzhasova at skitlab.ru>
>
> I know it looks a bit weird to have a negative offset like this, but
> it's actually correct.  These offsets are used relative to
> prm_base (on 34xx, it's OMAP3430_PRM_BASE defined in omap34xx.h).
> So I suggest you double check the values there, and cross reference to
> the "PRCM Register Manual" section of the TRM (last section of the PRCM
> chapter.)
>
> Thanks,
>
> Kevin
>

Ok, thanks for making it clear.

I thought that it can be a bug, because I made an attempt to run
Linux 3.10-rc3 kernel on Texas Instrument's DM816x evaluation module.
Without making any changes I faced with the kernel crush:

[    0.000000] Unhandled fault: external abort on non-linefetch (0x1028) 
at 0xfa17f8e4
[    0.000000] Internal error: : 1028 [#1] SMP ARM
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 
3.10.0-rc3-00001-g0e5443c-dirty #12
[    0.000000] task: c076fc50 ti: c0764000 task.ti: c0764000
[    0.000000] PC is at omap2_pwrdm_wait_transition+0x1c/0xac
[    0.000000] LR is at pwrdm_register_pwrdms+0x15c/0x1ac
[    0.000000] pc : [<c0031698>]    lr : [<c0036010>]    psr: 60000193
[    0.000000] sp : c0765f28  ip : c07bebe0  fp : 00000001
[    0.000000] r10: c07e6a90  r9 : 00000000  r8 : c07e6944
[    0.000000] r7 : c0754a50  r6 : c064f264  r5 : c0775298  r4 : c0773e9c
[    0.000000] r3 : fffff8e4  r2 : fa17f8e4  r1 : 00000004  r0 : c0775298
[    0.000000] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM 
Segment kernel
[    0.000000] Control: 10c5387d  Table: 80004019  DAC: 00000017
[    0.000000] Process swapper (pid: 0, stack limit = 0xc0764240)
[    0.000000] Stack: (0xc0765f28 to 0xc0766000)
[    0.000000] 5f20:                   c0773e9c c0775298 c064f264 
c0754a50 c0773ee4 c0036010
[    0.000000] 5f40: 35170034 81600134 c05125a8 fa180000 80000200 
c0771348 c07b1b48 c07475ac
[    0.000000] 5f60: c0771348 c07191fc c0647c40 c0711598 16c00000 
c0d24fb4 c06450ac c070c148
[    0.000000] 5f80: c0765f98 c0765f90 c0771134 c0765fdc 00000000 
00000000 00000000 00000000
[    0.000000] 5fa0: c0643878 00000001 00000000 c0748774 c0771134 
c076c880 413fc082 00000000
[    0.000000] 5fc0: 00000000 c07086fc 00000000 00000000 00000000 
00000000 00000000 c0748778
[    0.000000] 5fe0: 10c53c7d c076c910 c0748774 c0771134 80004059 
80008074 00000000 00000000
[    0.000000] [<c0031698>] (omap2_pwrdm_wait_transition+0x1c/0xac) from 
[<c0036010>] (pwrdm_register_pwrdms+0x15c/0x1ac)
[    0.000000] [<c0036010>] (pwrdm_register_pwrdms+0x15c/0x1ac) from 
[<c07191fc>] (omap3xxx_powerdomains_init+0x50/0x144)
[    0.000000] [<c07191fc>] (omap3xxx_powerdomains_init+0x50/0x144) from 
[<c0711598>] (ti81xx_init_early+0xcc/0x178)
[    0.000000] [<c0711598>] (ti81xx_init_early+0xcc/0x178) from 
[<c070c148>] (setup_arch+0x5ac/0x800)
[    0.000000] [<c070c148>] (setup_arch+0x5ac/0x800) from [<c07086fc>] 
(start_kernel+0x7c/0x330)
[    0.000000] [<c07086fc>] (start_kernel+0x7c/0x330) from [<80008074>] 
(0x80008074)
[    0.000000] Code: e1d030f8 e5982000 e28330e4 e0822003 (e5921000)
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---

So, I tried to find out what's wrong and explored the code of 
omap3xxx_powerdomains_init() call. It turned out that powerdomain 
initialization for ti81xx platform uses *powerdomains_omap3430_common[] 
structures, and when it tries to init iva2_pwrdm kernel crush occures. 
After applying my code changes the situation becomes a little bit 
better, and the kernel is able to continue it's loading (but still 
unable to load completely).

Anyway, maybe it can be a good idea to add new powerdomain structures 
for supporting ti81xx platform in mainline kernel. Actually I have 
already done some code changes for making current kernel bootable on 
DM816x EVM and I'm going to continue my work.

Thanks,

Aida



From swarren at wwwdotorg.org  Wed May 29 11:27:28 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 09:27:28 -0600
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <51A5BEB6.6070809@ti.com>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
 <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>
 <51A5BEB6.6070809@ti.com>
Message-ID: <51A61E60.4070708@wwwdotorg.org>

On 05/29/2013 02:39 AM, Benoit Cousson wrote:
> Hi Afzal,
> 
> On 05/29/2013 10:06 AM, Mohammed, Afzal wrote:
>> Hi Jon,
>>
>> On Wed, May 29, 2013 at 03:35:10, Stephen Warren wrote:
>>> On 05/28/2013 03:25 PM, Jon Hunter wrote:
>>
>>>>>  			ti,am335x-timer	(applicable to AM335x devices)
>>>>>  			ti,am335x-timer-1ms (applicable to AM335x devices)
>>>>> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
>>>>> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
>>
>>>> If you are adding more compatibility strings, then this implies that the
>>>> AM43x timers are not 100% compatible with any other device listed (such
>>>> as am335x or any omap device). That's fine but you should state that in
>>>> the changelog. If the AM43x timer registers are 100% compatible with
>>>> existing devices you should not add these.
>>>
>>> I'm not sure that's true; .dts files should always include a compatible
>>> value that describes the most specific model of the HW, plus any
>>> baseline compatible value that the HW is compatible with. This allows
>>> any required quirks/fixes/... to be applied for the specific HW model
>>> later even if nobody knows right now they'll be needed. Hence, defining
>>> new compatible values doesn't necessarily mean incompatible HW.
>>
>> Stephen took words out of my finger ;)
>>  
>> Some explanations,I don;t 
>>
>> 1. first compatible should be exact device [A], followed by compatible
>> model (if one)
>> 2. Minor effort in getting DT right the first time may help prevent
>> difficult effort later modifying it (if a necessity comes), considering
>> the fact that DT sources has  to move out of Kernel at some point of
>> time. And DT is not supposed to be modified, which may cause difficulty
>> for the users (I had been a minor victim of this during rebase).
>>
>> As we both were in GPMC land earlier, an example,
>>
>> If my memory is right, GPMC IP in am335x is rev 6, and IP has 8 chip
>> select, but one is not pinned out. Now assume that same IP is integrated
>> in another SoC (probably OMAP4 has rev 6). Here if we use same compatible
>> for both, driver cannot handle it properly (w/o knowledge about platform).
>> But if exact compatible is mentioned, without modifying DT (which should
>> be considered as a firmware) just by modifying Kernel, deciding based on
>> compatible would help achieve what is required.
> 
> That's true for the DTS itself, but here your are changing the binding
> documentation which is supposed to reflect the driver "interface" in the
> Device Tree model description.
> 
> Since the driver does not support any new compatible string, you should
> not update the binding.

I don't agree here; the DT binding should define all the required and/or
allowed values that must/should/can be present in the DT - the entire
legal schema. The set of all compatible values is included in that,
irrespective of whether a particular value actually (currently) defines
a different HW interface or not.


From nicolas.pitre at linaro.org  Wed May 29 11:28:59 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 29 May 2013 11:28:59 -0400 (EDT)
Subject: [PATCH 3/8] ARM: introduce common set_auxcr/get_auxcr
 functions
In-Reply-To: <1369834937.3715.64.camel@linaro1.home>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-4-git-send-email-nicolas.pitre@linaro.org>
 <1369834937.3715.64.camel@linaro1.home>
Message-ID: <alpine.LFD.2.03.1305291128180.1918@syhkavp.arg>

On Wed, 29 May 2013, Jon Medhurst (Tixy) wrote:

> On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> > From: Rob Herring <rob.herring at calxeda.com>
> > 
> > Move the private set_auxcr/get_auxcr functions from
> > drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
> > 
> > Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> > Cc: Russell King <linux at arm.linux.org.uk>
> > Signed-off-by: Nicolas Pitre <nico at linaro.org>
> > Acked-by: Tony Lindgren <tony at atomide.com>
> > Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > Reviewed-by: Will Deacon <will.deacon at arm.com>
> > ---
> >  arch/arm/include/asm/cp15.h       | 14 ++++++++++++++
> >  drivers/cpuidle/cpuidle-calxeda.c | 14 +-------------
> >  2 files changed, 15 insertions(+), 13 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
> > index 1f3262e99d..cedd372131 100644
> > --- a/arch/arm/include/asm/cp15.h
> > +++ b/arch/arm/include/asm/cp15.h
> > @@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val)
> >  	isb();
> >  }
> >  
> > +static inline unsigned int get_auxcr(void)
> > +{
> > +	unsigned int val;
> > +	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val));
> > +	return val;
> > +}
> > +
> > +static inline void set_auxcr(unsigned int val)
> > +{
> > +	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
> > +	  : : "r" (val));
> > +	isb();
> > +}
> > +
> >  #ifndef CONFIG_SMP
> >  extern void adjust_cr(unsigned long mask, unsigned long set);
> >  #endif
> > diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
> > index 223379169c..8a08e04c0e 100644
> > --- a/drivers/cpuidle/cpuidle-calxeda.c
> > +++ b/drivers/cpuidle/cpuidle-calxeda.c
> > @@ -37,19 +37,7 @@
> >  extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
> >  extern void *scu_base_addr;
> >  
> > -static inline unsigned int get_auxcr(void)
> > -{
> > -	unsigned int val;
> > -	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val) : : "cc");
> > -	return val;
> > -}
> > -
> > -static inline void set_auxcr(unsigned int val)
> > -{
> > -	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
> > -	  : : "r" (val) : "cc");
> > -	isb();
> > -}
> > +static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;
> 
> The added line above looks like a merge error to me.

Yep, good catch.


Nicolas


From swarren at wwwdotorg.org  Wed May 29 11:29:48 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 09:29:48 -0600
Subject: [PATCH] ARM: tegra: rebuild tegra_defconfig
In-Reply-To: <2234363.J239kID5LN@fb07-iapwap2.physik.uni-giessen.de>
References: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>
 <51A521F5.2010206@wwwdotorg.org>
 <2234363.J239kID5LN@fb07-iapwap2.physik.uni-giessen.de>
Message-ID: <51A61EEC.5040300@wwwdotorg.org>

On 05/29/2013 07:38 AM, Marc Dietrich wrote:
> Am Dienstag, 28. Mai 2013, 15:30:29 schrieb Stephen Warren:
>> On 05/28/2013 11:26 AM, Stephen Warren wrote:
>>> From: Stephen Warren <swarren at nvidia.com>
>>>
>>> This simply rebuilds tegra_defconfig on top of next-20130520. As such, it
>>> should introduce no changes; simply moving entries around due to Kconfig
>>> ordering changes. The apparent exceptions are:
>>>
>>> AUTO_ZRELADDR: Selected by ARM multi-platform support.
>>> MTD_CHAR: Removed in Kconfig.
>>>
>>> This should make it easier to create future defconfig patches on top of
>>> linux-next, since all the extraneous diffs have been removed. It also
>>> makes it more likely that once 3.12 comes around, this defconfig will
>>> already match what's required there.
>>
>> I've applied this (squashed it into) Tegra's for-3.11/defconfig branch.
> 
> wouldn't it make more sense to apply such a patch just before the merge window 
> closes (or better after some release candidate)?

Perhaps. It probably also depends a lot on when Kconfig changes get
applied in other areas as far as when it makes sense. I deferred it this
time around in order to pick up some tegra_defconfig changes that made
it into 3.10-rc3.

> This way we would have a 
> better chance to have a zero diff between defconfig and tegra_defconfig, e.g. 
> not like 3.10 is now.

I don't understand this; what is "defconfig" if not "tegra_defconfig"?


From swarren at wwwdotorg.org  Wed May 29 11:35:30 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 09:35:30 -0600
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <C79B248886DD134989C8FF6B096A91AB91B616BE9B@BGMAIL01.nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B616BE9B@BGMAIL01.nvidia.com>
Message-ID: <51A62042.7070304@wwwdotorg.org>

On 05/29/2013 04:10 AM, Jay Agarwal wrote:
>>>> So, if I apply this series, I do see the PCIe bridge and Ethernet
>>>> device get enumerated, but I don't see the USB3 controller get
>>>> enumerated. I believe that is a PCIe device behind the same bridge
>>>> on the
>>> same Tegra PCIe port.
>>>> Shouldn't this device show up?
>>> I have also reproduced this problem. I see somehow no non-
>>> prefetchable memory is assigned to any of pcie devices.
>>> Probably that is the reason for USB3 (pci 0000:04:00.0) not getting
>>> enumerated since it uses only non-prefetchable memory.
>>
>> 1. Bus4(on which usb3 device resides) always return 0xffffffff from it's
>> config space. which means device is not present?
>> 2. That's why it is not assigned any resources and hence no usb3 probe
>> happens.
>> 3. But same bus does return valid info like vendor/device id etc from it's
>> config space in downstream kernel and hence usb3 probe does happen.
>>
>> Thierry, Stephen,
>> 4. Any idea why bus4 should return 0xffffffff values in upstream kernel?
>> Anything missing?
>> 5. Also, how config space of all pcie devices are mapped? I mean if I change
>> the config space offset in dts file, then also I find correct vendor/device id
>> etc for bus0/device0/fun0.
>>     So how this mapping happens that even after changing the config space
>> offset in PCIe address space, it always finds correct vendor/device id.
> 
>  Any idea on this?

I did already reply the same day you sent the original email. My
response was:

Is there some reset/enable GPIO or regulator that needs to be programmed
to enable the PCIe USB3 controller? Take a look at the schematic. If you
can make it work by tweaking those GPIOs/... manually, then we can
ignore this issue and fix it up later, since it's not directly related
to the PCIe controller driver patches. It's more important to get the
Ethernet working than USB, I think.

To be honest though, I would expect you to be asking around inside
NVIDIA to determine the answer here. As the PCIe SW expert, I'd expect
you to drive this process. Try asking the Cardhu board and PCIe HW
experts within NVIDIA.

Did you make any progress on the issues with the Ethernet device?


From timur at tabi.org  Wed May 29 11:41:58 2013
From: timur at tabi.org (Timur Tabi)
Date: Wed, 29 May 2013 10:41:58 -0500
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <20130529135342.GB29528@S2101-09.ap.freescale.net>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
 <20130529135342.GB29528@S2101-09.ap.freescale.net>
Message-ID: <CAOZdJXVL2uP-qW=kydgS-t3C=C+6Cn9D3FWqbMuoK2c-EnckyA@mail.gmail.com>

On Wed, May 29, 2013 at 8:53 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>
>
> This function is unavailable until patch #7, right?


May I suggest that Markus run this script:

for i in 1 2 3 4 5 6 7 8 9
do
  git checkout HEAD^
  make
done

It's important that each commit in a patchset be compilable, otherwise
git-bisect will break.


From eduardo.valentin at ti.com  Wed May 29 11:42:35 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 29 May 2013 11:42:35 -0400
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <51A60E7E.2070905@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com> <519488D3.5070003@ti.com>
 <5194D0AF.3010407@ti.com> <51A60C74.4010307@ti.com> <51A60E7E.2070905@ti.com>
Message-ID: <51A621EB.5080805@ti.com>

On 29-05-2013 10:19, Cousson, Benoit wrote:
> Hi Eduardo,
> 
> On 5/29/2013 4:11 PM, Eduardo Valentin wrote:
>> Salut Monsieur Benoit,
>>
>> On 16-05-2013 08:27, Eduardo Valentin wrote:
>>> On 16-05-2013 03:20, Benoit Cousson wrote:
>>>> Hi Eduardo,
>>>>
>>
>> <cut>
>>
>>>> We need to check.
>>>
>>> Yeah, I also dont think this will work, because we will reparent the
>>> interrupt, setting to a different controller. That will break the TALERT
>>> signal already defined at GIC (check original patch).
>>>
>>> I propose keeping the way I sent. Unless there is a way to set two
>>> different controllers to same device.
>>>
>>
>> Any idea on this patch? Shall we keep the way it is?
> 
> Well since we cannot use directly interrupt, I think we need to use at
> least the proper gpio binding.
> 

hmm... OK. sounds reasonable. I will change the driver and resend this
one in one single series.

> Thanks,
> Benoit
> 
> 
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin

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From linus.walleij at linaro.org  Wed May 29 11:46:17 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 17:46:17 +0200
Subject: [PATCH -next] dmaengine: ste_dma40: add missing iounmap() on
 error in d40_probe()
In-Reply-To: <CAPgLHd9kMzZ_ZY6zm0MZ+P6dHq73i_GdCsxhpUOt-V9nf08tWA@mail.gmail.com>
References: <CAPgLHd9kMzZ_ZY6zm0MZ+P6dHq73i_GdCsxhpUOt-V9nf08tWA@mail.gmail.com>
Message-ID: <CACRpkdZpReWCaA7=-5xPfd9y5jDfP-P+5VqFCuo4Aa7LQ31Qhw@mail.gmail.com>

Hi Wei,

why does the patch subject say -next?

AFAICS the patch applies to Torvalds tree as well, and should probably
go in for fixes.

On Tue, May 28, 2013 at 11:07 AM, Wei Yongjun <weiyj.lk at gmail.com> wrote:

> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>
> Add the missing iounmap() before return from d40_probe()
> in the error handling case.
>
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

I guess Vinod should apply this... maybe it should even be marked
for stable.

Yours,
Linus Walleij


From konrad.wilk at oracle.com  Wed May 29 11:55:44 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 29 May 2013 11:55:44 -0400
Subject: [PATCH v4 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305291159220.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
 <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130528181515.GB27718@phenom.dumpdata.com>
 <alpine.DEB.2.02.1305291159220.4799@kaball.uk.xensource.com>
Message-ID: <20130529155544.GG23775@phenom.dumpdata.com>

On Wed, May 29, 2013 at 12:03:26PM +0100, Stefano Stabellini wrote:
> On Tue, 28 May 2013, Konrad Rzeszutek Wilk wrote:
> > On Tue, May 28, 2013 at 06:54:29PM +0100, Stefano Stabellini wrote:
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > Acked-by: Ian Campbell <ian.campbell at citrix.com>
> > > CC: konrad.wilk at oracle.com
> > > 
> > > Changes in v2:
> > > - leave do_stolen_accounting in arch/x86/xen/time.c;
> > > - use the new common functions in arch/ia64/xen/time.c.
> > 
> > So you also modify the function.
> 
> do_stolen_accounting? Just enought to call the new common function
> xen_get_runstate_snapshot instead of the old x86 specific
> get_runstate_snapshot.
> 
> 
> > > ---
> > >  arch/ia64/xen/time.c  |   48 +++----------------------
> > >  arch/x86/xen/time.c   |   76 +----------------------------------------
> > >  drivers/xen/Makefile  |    2 +-
> > >  drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
> > >  include/xen/xen-ops.h |    5 +++
> > >  5 files changed, 104 insertions(+), 118 deletions(-)
> > >  create mode 100644 drivers/xen/time.c
> > > 
> > > diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
> > > index 1f8244a..79a0b8c 100644
> > > --- a/arch/ia64/xen/time.c
> > > +++ b/arch/ia64/xen/time.c
> > > @@ -34,53 +34,17 @@
> > >  
> > >  #include "../kernel/fsyscall_gtod_data.h"
> > >  
> > > -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > >  static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
> > >  static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
> > >  
> > >  /* taken from i386/kernel/time-xen.c */
> > >  static void xen_init_missing_ticks_accounting(int cpu)
> > >  {
> > > -	struct vcpu_register_runstate_memory_area area;
> > > -	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
> > > -	int rc;
> > > +	xen_setup_runstate_info(&runstate);
> > >  
> > > -	memset(runstate, 0, sizeof(*runstate));
> > > -
> > > -	area.addr.v = runstate;
> > > -	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> > > -				&area);
> > > -	WARN_ON(rc && rc != -ENOSYS);
> > > -
> > > -	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
> > > -	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
> > > -					    + runstate->time[RUNSTATE_offline];
> > > -}
> > > -
> > > -/*
> > > - * Runstate accounting
> > > - */
> > > -/* stolen from arch/x86/xen/time.c */
> > > -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> > > -{
> > > -	u64 state_time;
> > > -	struct vcpu_runstate_info *state;
> > > -
> > > -	BUG_ON(preemptible());
> > > -
> > > -	state = &__get_cpu_var(xen_runstate);
> > > -
> > > -	/*
> > > -	 * The runstate info is always updated by the hypervisor on
> > > -	 * the current CPU, so there's no need to use anything
> > > -	 * stronger than a compiler barrier when fetching it.
> > > -	 */
> > > -	do {
> > > -		state_time = state->state_entry_time;
> > > -		rmb();
> > > -		*res = *state;
> > > -		rmb();
> > > -	} while (state->state_entry_time != state_time);
> > > +	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
> > > +	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
> > > +					    + runstate.time[RUNSTATE_offline];
> > >  }
> > >  
> > >  #define NS_PER_TICK (1000000000LL/HZ)
> > > @@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
> > >  	struct vcpu_runstate_info runstate;
> > >  	struct task_struct *p = current;
> > >  
> > > -	get_runstate_snapshot(&runstate);
> > > +	xen_get_runstate_snapshot(&runstate);
> > >  
> > >  	/*
> > >  	 * Check for vcpu migration effect
> > > @@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
> > >  	 */
> > >  	now = ia64_native_sched_clock();
> > >  
> > > -	get_runstate_snapshot(&runstate);
> > > +	xen_get_runstate_snapshot(&runstate);
> > >  
> > >  	WARN_ON(runstate.state != RUNSTATE_running);
> > >  
> > > diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
> > > index 3d88bfd..c0ca15e 100644
> > > --- a/arch/x86/xen/time.c
> > > +++ b/arch/x86/xen/time.c
> > > @@ -30,9 +30,6 @@
> > >  #define TIMER_SLOP	100000
> > >  #define NS_PER_TICK	(1000000000LL / HZ)
> > >  
> > > -/* runstate info updated by Xen */
> > > -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > > -
> > >  /* snapshots of runstate info */
> > >  static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
> > >  
> > > @@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
> > >  static DEFINE_PER_CPU(u64, xen_residual_stolen);
> > >  static DEFINE_PER_CPU(u64, xen_residual_blocked);
> > >  
> > > -/* return an consistent snapshot of 64-bit time/counter value */
> > > -static u64 get64(const u64 *p)
> > > -{
> > > -	u64 ret;
> > > -
> > > -	if (BITS_PER_LONG < 64) {
> > > -		u32 *p32 = (u32 *)p;
> > > -		u32 h, l;
> > > -
> > > -		/*
> > > -		 * Read high then low, and then make sure high is
> > > -		 * still the same; this will only loop if low wraps
> > > -		 * and carries into high.
> > > -		 * XXX some clean way to make this endian-proof?
> > > -		 */
> > > -		do {
> > > -			h = p32[1];
> > > -			barrier();
> > > -			l = p32[0];
> > > -			barrier();
> > > -		} while (p32[1] != h);
> > > -
> > > -		ret = (((u64)h) << 32) | l;
> > > -	} else
> > > -		ret = *p;
> > > -
> > > -	return ret;
> > > -}
> > > -
> > > -/*
> > > - * Runstate accounting
> > > - */
> > > -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> > > -{
> > > -	u64 state_time;
> > > -	struct vcpu_runstate_info *state;
> > > -
> > > -	BUG_ON(preemptible());
> > > -
> > > -	state = &__get_cpu_var(xen_runstate);
> > > -
> > > -	/*
> > > -	 * The runstate info is always updated by the hypervisor on
> > > -	 * the current CPU, so there's no need to use anything
> > > -	 * stronger than a compiler barrier when fetching it.
> > > -	 */
> > > -	do {
> > > -		state_time = get64(&state->state_entry_time);
> > > -		barrier();
> > > -		*res = *state;
> > > -		barrier();
> > > -	} while (get64(&state->state_entry_time) != state_time);
> > > -}
> > > -
> > > -/* return true when a vcpu could run but has no real cpu to run on */
> > > -bool xen_vcpu_stolen(int vcpu)
> > > -{
> > > -	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> > > -}
> > > -
> > > -void xen_setup_runstate_info(int cpu)
> > > -{
> > > -	struct vcpu_register_runstate_memory_area area;
> > > -
> > > -	area.addr.v = &per_cpu(xen_runstate, cpu);
> > > -
> > > -	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > > -			       cpu, &area))
> > > -		BUG();
> > > -}
> > > -
> > >  static void do_stolen_accounting(void)
> > >  {
> > >  	struct vcpu_runstate_info state;
> > > @@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
> > >  	s64 blocked, runnable, offline, stolen;
> > >  	cputime_t ticks;
> > >  
> > > -	get_runstate_snapshot(&state);
> > > +	xen_get_runstate_snapshot(&state);
> > >  
> > >  	WARN_ON(state.state != RUNSTATE_running);
> > >  
> > > diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
> > > index eabd0ee..2bf461a 100644
> > > --- a/drivers/xen/Makefile
> > > +++ b/drivers/xen/Makefile
> > > @@ -3,7 +3,7 @@ obj-y	+= manage.o
> > >  obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
> > >  endif
> > >  obj-$(CONFIG_X86)			+= fallback.o
> > > -obj-y	+= grant-table.o features.o events.o balloon.o
> > > +obj-y	+= grant-table.o features.o events.o balloon.o time.o
> > >  obj-y	+= xenbus/
> > >  
> > >  nostackp := $(call cc-option, -fno-stack-protector)
> > > diff --git a/drivers/xen/time.c b/drivers/xen/time.c
> > > new file mode 100644
> > > index 0000000..c2e39d3
> > > --- /dev/null
> > > +++ b/drivers/xen/time.c
> > > @@ -0,0 +1,91 @@
> > > +/*
> > > + * Xen stolen ticks accounting.
> > > + */
> > > +#include <linux/kernel.h>
> > > +#include <linux/kernel_stat.h>
> > > +#include <linux/math64.h>
> > > +#include <linux/gfp.h>
> > > +
> > > +#include <asm/xen/hypervisor.h>
> > > +#include <asm/xen/hypercall.h>
> > > +
> > > +#include <xen/events.h>
> > > +#include <xen/features.h>
> > > +#include <xen/interface/xen.h>
> > > +#include <xen/interface/vcpu.h>
> > > +#include <xen/xen-ops.h>
> > > +
> > > +/* runstate info updated by Xen */
> > > +static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > > +
> > > +/* return an consistent snapshot of 64-bit time/counter value */
> > > +static u64 get64(const u64 *p)
> > > +{
> > > +	u64 ret;
> > > +
> > > +	if (BITS_PER_LONG < 64) {
> > > +		u32 *p32 = (u32 *)p;
> > > +		u32 h, l;
> > > +
> > > +		/*
> > > +		 * Read high then low, and then make sure high is
> > > +		 * still the same; this will only loop if low wraps
> > > +		 * and carries into high.
> > > +		 * XXX some clean way to make this endian-proof?
> > > +		 */
> > > +		do {
> > > +			h = p32[1];
> > > +			barrier();
> > > +			l = p32[0];
> > > +			barrier();
> > > +		} while (p32[1] != h);
> > > +
> > > +		ret = (((u64)h) << 32) | l;
> > > +	} else
> > > +		ret = *p;
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +/*
> > > + * Runstate accounting
> > > + */
> > > +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
> > > +{
> > > +	u64 state_time;
> > > +	struct vcpu_runstate_info *state;
> > > +
> > > +	BUG_ON(preemptible());
> > > +
> > > +	state = &__get_cpu_var(xen_runstate);
> > > +
> > > +	/*
> > > +	 * The runstate info is always updated by the hypervisor on
> > > +	 * the current CPU, so there's no need to use anything
> > > +	 * stronger than a compiler barrier when fetching it.
> > > +	 */
> > > +	do {
> > > +		state_time = get64(&state->state_entry_time);
> > > +		barrier();
> > > +		*res = *state;
> > > +		barrier();
> > > +	} while (get64(&state->state_entry_time) != state_time);
> > > +}
> > > +
> > > +/* return true when a vcpu could run but has no real cpu to run on */
> > > +bool xen_vcpu_stolen(int vcpu)
> > > +{
> > > +	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> > > +}
> > > +
> > > +void xen_setup_runstate_info(int cpu)
> > > +{
> > > +	struct vcpu_register_runstate_memory_area area;
> > > +
> > > +	area.addr.v = &per_cpu(xen_runstate, cpu);
> > > +
> > > +	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > > +			       cpu, &area))
> > > +		BUG();
> > 
> > The original code did:
> > 
> > -       rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> > -                               &area);
> > -       WARN_ON(rc && rc != -ENOSYS);
> > -
> > Any reason not to do this?
> 
> The original x86 code just BUGs out: I took that version over the ia64
> version.

Ah, I see it now. OK, then this looks good to me.


From b-cousson at ti.com  Wed May 29 12:02:38 2013
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 29 May 2013 18:02:38 +0200
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ
 pin and msecure line
In-Reply-To: <CAGa+x85ZzfX400eEGmTGPzRiC21S83VRiHYj38cqsJLjDF3L7g@mail.gmail.com>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <51A5CCA5.7000700@ti.com>
 <87ehcpano0.fsf@linaro.org> <51A60F69.7050203@ti.com>
 <CAGa+x85ZzfX400eEGmTGPzRiC21S83VRiHYj38cqsJLjDF3L7g@mail.gmail.com>
Message-ID: <51A6269E.2090001@ti.com>

On 5/29/2013 5:29 PM, Kevin Hilman wrote:
>
> On May 29, 2013 8:06 AM, "Cousson, Benoit" <b-cousson at ti.com
> <mailto:b-cousson at ti.com>> wrote:
>  >
>  > On 5/29/2013 4:03 PM, Kevin Hilman wrote:
>  >>
>  >> "Cousson, Benoit" <b-cousson at ti.com <mailto:b-cousson at ti.com>> writes:
>  >>
>  >> [...]
>  >>
>  >>>>
>  >>>> Let me respin this after some more doc reading.
>  >>>
>  >>>
>  >>> Did you re-spin it already?
>  >>
>  >>
>  >> Yes, v2 is here.
>  >>
>  >> http://marc.info/?l=linux-omap&m=136944147521955&w=2
>  >>
>  >> It also needed a rework because the fref_clk0_out pin is also in the
>  >> wkup section of the padconf, not core.
>  >
>  >
>  > OK, I'll wait for the v3 then :-)
>  >
>
> Hmm, why? v2 has the wkup changes included.

Why? Because of my bad understanding of English :-)
I understood: It also needs a rework...

Sorry, I'll merge it.

Thanks,
Benoit



From nicolas.pitre at linaro.org  Wed May 29 12:06:44 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 29 May 2013 12:06:44 -0400 (EDT)
Subject: [PATCH] ARM: fix kernel decompressor compilation error with
 CONFIG_DEBUG_SEMIHOSTING
In-Reply-To: <20130529145944.GE29528@S2101-09.ap.freescale.net>
References: <alpine.LFD.2.03.1305281654120.1918@syhkavp.arg>
 <20130529145944.GE29528@S2101-09.ap.freescale.net>
Message-ID: <alpine.LFD.2.03.1305291205330.1918@syhkavp.arg>

On Wed, 29 May 2013, Shawn Guo wrote:

> On Tue, May 28, 2013 at 04:59:13PM -0400, Nicolas Pitre wrote:
> > 
> > ... and add semihosting output support to the decompressor while at it.
> > 
> > Signed-off-by: Nicolas Pitre <nico at linaro.org>
> 
> Acked-by: Shawn Guo <shawn.guo at linaro.org>

Thanks.

> Maybe include the error output in commit log.

Yes, and I've improved it as well.

Patch queued as 7737/1.


Nicolas


From khilman at linaro.org  Wed May 29 12:12:46 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 29 May 2013 09:12:46 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <51A5BE0D.7030609@ti.com> (Grygorii Strashko's message of "Wed,
 29 May 2013 11:36:29 +0300")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <87ppwgdnxu.fsf@linaro.org>
 <CAGo_u6ruWQwSB8Z0BRLda7HunTyr9mGpx4eMSGdQZkCxKxbHbg@mail.gmail.com>
 <87a9nfc5uc.fsf@linaro.org> <51A5BE0D.7030609@ti.com>
Message-ID: <87txll9341.fsf@linaro.org>

Grygorii Strashko <grygorii.strashko at ti.com> writes:

> On 05/28/2013 09:33 PM, Kevin Hilman wrote:
>> Nishanth Menon <nm at ti.com> writes:
>>
>>> On Fri, May 24, 2013 at 5:15 PM, Kevin Hilman <khilman at linaro.org> wrote:
>>>> Kevin Hilman <khilman at linaro.org> writes:
>>>>
>>>>> Nishanth Menon <nm at ti.com> writes:
>>>> [...]
>>>>
>>>>>> Actually 2 things:
>>>>>>
>>>>>> a) patch seems to do the wrong thing for 4460 - 0x18 offset should
>>>>>> have been used instead of 0x14 which is correct for 4430?
>>>>> I see, thanks.  I'll double check the TRMs.
>>>>>
>>>>>> b) yes, I understand,  the current settings we did worked, but the
>>>>>> mode(0) we are setting to is real weird - we are setting it up for
>>>>>> clk0 out - I cant even think why it is even working in the first place
>>>>>> :( - is it because we are pumping out sysclkout and as a result we are
>>>>>> lucky that msecure is being sampled at the right point by twl6030
>>>>>> allowing rtc access? either way, IMHO, the configuration is wrong.
>>>>> Ah, yes.  Mode zero is definitely wrong.   When I did the original patch
>>>>> for legacy mode, I just duplicated the settings u-boot was using.  Guess
>>>>> it's a fluke that it works.
>>>> Actually, for legacy mode, it's set correctly in mode 2.  This line:
>>>>
>>>>          omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
>>>>
>>>> does the right thing based on the signal name.    But for DT boot, I
>>>> defintely screwed it up by setting it to mode (and putting it in the
>>>> wrong padconf section.)
>>>>
>>>> Also, are you *really* sure about the offset difference between 4430 and
>>>> 4460 here?  I don't have access to NDA docs anymore, so I cannot double
>>>> check this.
>>>>
>>>> What I do know is that the legacy code is using 0x54 for both, and if I
>>>> simply comment out that 'sys_drm_msecure' line above, RTC wake stops
>>>> working (legacy boot) on both 4430 and 4460, so that seems like pretty
>>>> stront evidence that it's the same offset on both.
>>> Schematics are public for PandaBoard ES and PandaBoard - as you can
>>> see from that the registers connected are definitely different.
>> What I see from both schematics is that SYS_DRM_MSECURE is available on
>> a few different pads, but on both 4430 and 4460, one of the places is in
>> mode 2 of FREF_CLK0_OUT, which is at offset 0x54 on both SoCs.
>>
>> Based on that reading, and the fact that not correctly muxing that pad
>> to mode 2 on *both* 4430 and 4460 makes the RTC work, I'm rather
>> convinced that the offset should be the same for 4430 and 4460.
>>
>> What am I missing?
> Hi Kevin,
>
> I've rechecked it too.

Thanks for checking, I'll take this as an Acked-by.

Kevin


From khilman at linaro.org  Wed May 29 12:13:54 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 29 May 2013 09:13:54 -0700
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin
 and msecure line
In-Reply-To: <51A6269E.2090001@ti.com> (Benoit Cousson's message of "Wed, 29
 May 2013 18:02:38 +0200")
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <51A5CCA5.7000700@ti.com>
 <87ehcpano0.fsf@linaro.org> <51A60F69.7050203@ti.com>
 <CAGa+x85ZzfX400eEGmTGPzRiC21S83VRiHYj38cqsJLjDF3L7g@mail.gmail.com>
 <51A6269E.2090001@ti.com>
Message-ID: <87li6x9325.fsf@linaro.org>

"Cousson, Benoit" <b-cousson at ti.com> writes:

> On 5/29/2013 5:29 PM, Kevin Hilman wrote:
>>
>> On May 29, 2013 8:06 AM, "Cousson, Benoit" <b-cousson at ti.com
>> <mailto:b-cousson at ti.com>> wrote:
>>  >
>>  > On 5/29/2013 4:03 PM, Kevin Hilman wrote:
>>  >>
>>  >> "Cousson, Benoit" <b-cousson at ti.com <mailto:b-cousson at ti.com>> writes:
>>  >>
>>  >> [...]
>>  >>
>>  >>>>
>>  >>>> Let me respin this after some more doc reading.
>>  >>>
>>  >>>
>>  >>> Did you re-spin it already?
>>  >>
>>  >>
>>  >> Yes, v2 is here.
>>  >>
>>  >> http://marc.info/?l=linux-omap&m=136944147521955&w=2
>>  >>
>>  >> It also needed a rework because the fref_clk0_out pin is also in the
>>  >> wkup section of the padconf, not core.
>>  >
>>  >
>>  > OK, I'll wait for the v3 then :-)
>>  >
>>
>> Hmm, why? v2 has the wkup changes included.
>
> Why? Because of my bad understanding of English :-)
> I understood: It also needs a rework...

Re-reading, I wasn't terribly clear.  Sorry for the confusion.

> Sorry, I'll merge it.

I was hoping for an Ack from Nishanth since he had some questions about
it, but with the double checking from you and Grygorii, I think it
should go in for the -rc cycle.  (also, please add an Ack from Grygorii.)

Thanks,

Kevin


From stefano.stabellini at eu.citrix.com  Wed May 29 12:18:52 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 29 May 2013 17:18:52 +0100
Subject: [PATCH v4 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <20130529155544.GG23775@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
 <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130528181515.GB27718@phenom.dumpdata.com>
 <alpine.DEB.2.02.1305291159220.4799@kaball.uk.xensource.com>
 <20130529155544.GG23775@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1305291718430.4799@kaball.uk.xensource.com>

On Wed, 29 May 2013, Konrad Rzeszutek Wilk wrote:
> On Wed, May 29, 2013 at 12:03:26PM +0100, Stefano Stabellini wrote:
> > On Tue, 28 May 2013, Konrad Rzeszutek Wilk wrote:
> > > On Tue, May 28, 2013 at 06:54:29PM +0100, Stefano Stabellini wrote:
> > > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > > Acked-by: Ian Campbell <ian.campbell at citrix.com>
> > > > CC: konrad.wilk at oracle.com
> > > > 
> > > > Changes in v2:
> > > > - leave do_stolen_accounting in arch/x86/xen/time.c;
> > > > - use the new common functions in arch/ia64/xen/time.c.
> > > 
> > > So you also modify the function.
> > 
> > do_stolen_accounting? Just enought to call the new common function
> > xen_get_runstate_snapshot instead of the old x86 specific
> > get_runstate_snapshot.
> > 
> > 
> > > > ---
> > > >  arch/ia64/xen/time.c  |   48 +++----------------------
> > > >  arch/x86/xen/time.c   |   76 +----------------------------------------
> > > >  drivers/xen/Makefile  |    2 +-
> > > >  drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
> > > >  include/xen/xen-ops.h |    5 +++
> > > >  5 files changed, 104 insertions(+), 118 deletions(-)
> > > >  create mode 100644 drivers/xen/time.c
> > > > 
> > > > diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
> > > > index 1f8244a..79a0b8c 100644
> > > > --- a/arch/ia64/xen/time.c
> > > > +++ b/arch/ia64/xen/time.c
> > > > @@ -34,53 +34,17 @@
> > > >  
> > > >  #include "../kernel/fsyscall_gtod_data.h"
> > > >  
> > > > -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > > >  static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
> > > >  static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
> > > >  
> > > >  /* taken from i386/kernel/time-xen.c */
> > > >  static void xen_init_missing_ticks_accounting(int cpu)
> > > >  {
> > > > -	struct vcpu_register_runstate_memory_area area;
> > > > -	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
> > > > -	int rc;
> > > > +	xen_setup_runstate_info(&runstate);
> > > >  
> > > > -	memset(runstate, 0, sizeof(*runstate));
> > > > -
> > > > -	area.addr.v = runstate;
> > > > -	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> > > > -				&area);
> > > > -	WARN_ON(rc && rc != -ENOSYS);
> > > > -
> > > > -	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
> > > > -	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
> > > > -					    + runstate->time[RUNSTATE_offline];
> > > > -}
> > > > -
> > > > -/*
> > > > - * Runstate accounting
> > > > - */
> > > > -/* stolen from arch/x86/xen/time.c */
> > > > -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> > > > -{
> > > > -	u64 state_time;
> > > > -	struct vcpu_runstate_info *state;
> > > > -
> > > > -	BUG_ON(preemptible());
> > > > -
> > > > -	state = &__get_cpu_var(xen_runstate);
> > > > -
> > > > -	/*
> > > > -	 * The runstate info is always updated by the hypervisor on
> > > > -	 * the current CPU, so there's no need to use anything
> > > > -	 * stronger than a compiler barrier when fetching it.
> > > > -	 */
> > > > -	do {
> > > > -		state_time = state->state_entry_time;
> > > > -		rmb();
> > > > -		*res = *state;
> > > > -		rmb();
> > > > -	} while (state->state_entry_time != state_time);
> > > > +	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
> > > > +	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
> > > > +					    + runstate.time[RUNSTATE_offline];
> > > >  }
> > > >  
> > > >  #define NS_PER_TICK (1000000000LL/HZ)
> > > > @@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
> > > >  	struct vcpu_runstate_info runstate;
> > > >  	struct task_struct *p = current;
> > > >  
> > > > -	get_runstate_snapshot(&runstate);
> > > > +	xen_get_runstate_snapshot(&runstate);
> > > >  
> > > >  	/*
> > > >  	 * Check for vcpu migration effect
> > > > @@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
> > > >  	 */
> > > >  	now = ia64_native_sched_clock();
> > > >  
> > > > -	get_runstate_snapshot(&runstate);
> > > > +	xen_get_runstate_snapshot(&runstate);
> > > >  
> > > >  	WARN_ON(runstate.state != RUNSTATE_running);
> > > >  
> > > > diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
> > > > index 3d88bfd..c0ca15e 100644
> > > > --- a/arch/x86/xen/time.c
> > > > +++ b/arch/x86/xen/time.c
> > > > @@ -30,9 +30,6 @@
> > > >  #define TIMER_SLOP	100000
> > > >  #define NS_PER_TICK	(1000000000LL / HZ)
> > > >  
> > > > -/* runstate info updated by Xen */
> > > > -static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > > > -
> > > >  /* snapshots of runstate info */
> > > >  static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
> > > >  
> > > > @@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
> > > >  static DEFINE_PER_CPU(u64, xen_residual_stolen);
> > > >  static DEFINE_PER_CPU(u64, xen_residual_blocked);
> > > >  
> > > > -/* return an consistent snapshot of 64-bit time/counter value */
> > > > -static u64 get64(const u64 *p)
> > > > -{
> > > > -	u64 ret;
> > > > -
> > > > -	if (BITS_PER_LONG < 64) {
> > > > -		u32 *p32 = (u32 *)p;
> > > > -		u32 h, l;
> > > > -
> > > > -		/*
> > > > -		 * Read high then low, and then make sure high is
> > > > -		 * still the same; this will only loop if low wraps
> > > > -		 * and carries into high.
> > > > -		 * XXX some clean way to make this endian-proof?
> > > > -		 */
> > > > -		do {
> > > > -			h = p32[1];
> > > > -			barrier();
> > > > -			l = p32[0];
> > > > -			barrier();
> > > > -		} while (p32[1] != h);
> > > > -
> > > > -		ret = (((u64)h) << 32) | l;
> > > > -	} else
> > > > -		ret = *p;
> > > > -
> > > > -	return ret;
> > > > -}
> > > > -
> > > > -/*
> > > > - * Runstate accounting
> > > > - */
> > > > -static void get_runstate_snapshot(struct vcpu_runstate_info *res)
> > > > -{
> > > > -	u64 state_time;
> > > > -	struct vcpu_runstate_info *state;
> > > > -
> > > > -	BUG_ON(preemptible());
> > > > -
> > > > -	state = &__get_cpu_var(xen_runstate);
> > > > -
> > > > -	/*
> > > > -	 * The runstate info is always updated by the hypervisor on
> > > > -	 * the current CPU, so there's no need to use anything
> > > > -	 * stronger than a compiler barrier when fetching it.
> > > > -	 */
> > > > -	do {
> > > > -		state_time = get64(&state->state_entry_time);
> > > > -		barrier();
> > > > -		*res = *state;
> > > > -		barrier();
> > > > -	} while (get64(&state->state_entry_time) != state_time);
> > > > -}
> > > > -
> > > > -/* return true when a vcpu could run but has no real cpu to run on */
> > > > -bool xen_vcpu_stolen(int vcpu)
> > > > -{
> > > > -	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> > > > -}
> > > > -
> > > > -void xen_setup_runstate_info(int cpu)
> > > > -{
> > > > -	struct vcpu_register_runstate_memory_area area;
> > > > -
> > > > -	area.addr.v = &per_cpu(xen_runstate, cpu);
> > > > -
> > > > -	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > > > -			       cpu, &area))
> > > > -		BUG();
> > > > -}
> > > > -
> > > >  static void do_stolen_accounting(void)
> > > >  {
> > > >  	struct vcpu_runstate_info state;
> > > > @@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
> > > >  	s64 blocked, runnable, offline, stolen;
> > > >  	cputime_t ticks;
> > > >  
> > > > -	get_runstate_snapshot(&state);
> > > > +	xen_get_runstate_snapshot(&state);
> > > >  
> > > >  	WARN_ON(state.state != RUNSTATE_running);
> > > >  
> > > > diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
> > > > index eabd0ee..2bf461a 100644
> > > > --- a/drivers/xen/Makefile
> > > > +++ b/drivers/xen/Makefile
> > > > @@ -3,7 +3,7 @@ obj-y	+= manage.o
> > > >  obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
> > > >  endif
> > > >  obj-$(CONFIG_X86)			+= fallback.o
> > > > -obj-y	+= grant-table.o features.o events.o balloon.o
> > > > +obj-y	+= grant-table.o features.o events.o balloon.o time.o
> > > >  obj-y	+= xenbus/
> > > >  
> > > >  nostackp := $(call cc-option, -fno-stack-protector)
> > > > diff --git a/drivers/xen/time.c b/drivers/xen/time.c
> > > > new file mode 100644
> > > > index 0000000..c2e39d3
> > > > --- /dev/null
> > > > +++ b/drivers/xen/time.c
> > > > @@ -0,0 +1,91 @@
> > > > +/*
> > > > + * Xen stolen ticks accounting.
> > > > + */
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/kernel_stat.h>
> > > > +#include <linux/math64.h>
> > > > +#include <linux/gfp.h>
> > > > +
> > > > +#include <asm/xen/hypervisor.h>
> > > > +#include <asm/xen/hypercall.h>
> > > > +
> > > > +#include <xen/events.h>
> > > > +#include <xen/features.h>
> > > > +#include <xen/interface/xen.h>
> > > > +#include <xen/interface/vcpu.h>
> > > > +#include <xen/xen-ops.h>
> > > > +
> > > > +/* runstate info updated by Xen */
> > > > +static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
> > > > +
> > > > +/* return an consistent snapshot of 64-bit time/counter value */
> > > > +static u64 get64(const u64 *p)
> > > > +{
> > > > +	u64 ret;
> > > > +
> > > > +	if (BITS_PER_LONG < 64) {
> > > > +		u32 *p32 = (u32 *)p;
> > > > +		u32 h, l;
> > > > +
> > > > +		/*
> > > > +		 * Read high then low, and then make sure high is
> > > > +		 * still the same; this will only loop if low wraps
> > > > +		 * and carries into high.
> > > > +		 * XXX some clean way to make this endian-proof?
> > > > +		 */
> > > > +		do {
> > > > +			h = p32[1];
> > > > +			barrier();
> > > > +			l = p32[0];
> > > > +			barrier();
> > > > +		} while (p32[1] != h);
> > > > +
> > > > +		ret = (((u64)h) << 32) | l;
> > > > +	} else
> > > > +		ret = *p;
> > > > +
> > > > +	return ret;
> > > > +}
> > > > +
> > > > +/*
> > > > + * Runstate accounting
> > > > + */
> > > > +void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
> > > > +{
> > > > +	u64 state_time;
> > > > +	struct vcpu_runstate_info *state;
> > > > +
> > > > +	BUG_ON(preemptible());
> > > > +
> > > > +	state = &__get_cpu_var(xen_runstate);
> > > > +
> > > > +	/*
> > > > +	 * The runstate info is always updated by the hypervisor on
> > > > +	 * the current CPU, so there's no need to use anything
> > > > +	 * stronger than a compiler barrier when fetching it.
> > > > +	 */
> > > > +	do {
> > > > +		state_time = get64(&state->state_entry_time);
> > > > +		barrier();
> > > > +		*res = *state;
> > > > +		barrier();
> > > > +	} while (get64(&state->state_entry_time) != state_time);
> > > > +}
> > > > +
> > > > +/* return true when a vcpu could run but has no real cpu to run on */
> > > > +bool xen_vcpu_stolen(int vcpu)
> > > > +{
> > > > +	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
> > > > +}
> > > > +
> > > > +void xen_setup_runstate_info(int cpu)
> > > > +{
> > > > +	struct vcpu_register_runstate_memory_area area;
> > > > +
> > > > +	area.addr.v = &per_cpu(xen_runstate, cpu);
> > > > +
> > > > +	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > > > +			       cpu, &area))
> > > > +		BUG();
> > > 
> > > The original code did:
> > > 
> > > -       rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> > > -                               &area);
> > > -       WARN_ON(rc && rc != -ENOSYS);
> > > -
> > > Any reason not to do this?
> > 
> > The original x86 code just BUGs out: I took that version over the ia64
> > version.
> 
> Ah, I see it now. OK, then this looks good to me.
> 

Can I add your acked-by? ;-)


From stern at rowland.harvard.edu  Wed May 29 12:21:02 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Wed, 29 May 2013 12:21:02 -0400 (EDT)
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <201305282211.28563.arnd@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305291211160.885-100000@iolanthe.rowland.org>

On Tue, 28 May 2013, Arnd Bergmann wrote:

> Seems to basically work now, but I'm getting run-time errors after
> loading the driver, with patch 1/3 applied:
> 
> [15916.438452] input: Logitech USB-PS/2 Optical Mouse as /devices/pci0000:00/0000:00:12.0/usb3/3-1/3-1:1.0/input/input26
> [15916.438584] hid-generic 0003:046D:C050.0017: input,hidraw0: USB HID v1.10 Mouse [Logitech USB-PS/2 Optical Mouse] on usb-0000:00:12.0-1/input0
> [15917.465597] usb 3-3: new full-speed USB device number 3 using ohci-pci
> [15917.636712] usb 3-3: New USB device found, idVendor=0ccd, idProduct=0077
> [15917.636717] usb 3-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
> [15917.636721] usb 3-3: Product: USB PnP Sound Device
> [15917.636724] usb 3-3: Manufacturer: C-Media Electronics Inc.      
> [15917.812827] input: C-Media Electronics Inc.       USB PnP Sound Device as /devices/pci0000:00/0000:00:12.0/usb3/3-3/3-3:1.3/input/input27
> [15917.812919] hid-generic 0003:0CCD:0077.0018: input,hidraw1: USB HID v1.00 Device [C-Media Electronics Inc.       USB PnP Sound Device] on usb-0000:00:12.0-3/input3
> [15918.789906] cannot submit urb (err = -18)
> [15918.790163] cannot submit urb (err = -18)
> [15918.842095] usb 7-1: new full-speed USB device number 2 using ohci-pci
> [15919.883135] cannot submit urb (err = -18)
> [15919.883604] cannot submit urb (err = -18)
> [15919.883613] cannot submit urb (err = -18)
> [15919.883616] cannot submit urb (err = -18)
> [15919.883619] cannot submit urb (err = -18)

Those error messages are annoying; they don't use dev_err(), so they
don't include the device and driver names.  There's no way to know what
they refer to.  I rather suspect they come from the usbaudio driver.

When you ran this test, did you have commit 815fa7b91761 applied?

Does the same problem occur without Manjunath's changes?

Alan Stern



From linus.walleij at linaro.org  Wed May 29 12:28:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 18:28:26 +0200
Subject: [PATCH] pinctrl: sink pinctrldev_list_mutex
In-Reply-To: <51A4C9BA.40903@wwwdotorg.org>
References: <1368690525-32252-1-git-send-email-linus.walleij@stericsson.com>
 <519A8A57.9060007@wwwdotorg.org>
 <CACRpkdZieCmFnHCGUkv8EqcAtb3DA7dSZpimSdB4P81tZPJRoQ@mail.gmail.com>
 <519F8B02.1080000@wwwdotorg.org>
 <CACRpkdYxvBvYAnmp-p5WwB3QD0rd83qDcdg-BMhN7-2Jv8Oo_w@mail.gmail.com>
 <51A4C9BA.40903@wwwdotorg.org>
Message-ID: <CACRpkdaC54jJxfPiaEborfuozHCgvH6vMzsQT_6kJsM-=6fedQ@mail.gmail.com>

On Tue, May 28, 2013 at 5:14 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> [Me]
>> But it'd be even cooler to actually just iterate over the
>> pinctrl_list och handles and orphan them, and later recouple
>> them if a driver is loaded back in.
>
> Hmm. What happens if the client driver wants to select a different state
> while the pinctrl driver itself isn't loaded? I'm not sure how workable
> that is. I think the only way to make it work would be to cache enough
> information in the struct pinctrl that it could be activated even if the
> driver wasn't loaded. That seems a little scary.

Yes it looks like that would lead to a bit of scalability problem in the
struct pinctrl. If for nothing else than for the fact that it will eat
memory and such :-(

> I'd be fine if there was a requirement to unload all drives that were
> clients of the pinctrl driver before you could unload the pinctrl
> driver, just like any other driver/subsystem. This would work fine at
> least for testing with just hogs, which while not great for full-system
> testing would surely be fine at least when first developing the pinctrl
> driver.

Yes ... so if we call
get_device(pctldev->dev)/put_device(pctldev->dev)
for any successful pinctrl_get() which is not a hog,
we increase the refcount so that the device core will disallow
unloading of the driver.

Now I need to figure out how to do that.

Yours,
Linus Walleij


From nico at fluxnic.net  Wed May 29 12:32:50 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 29 May 2013 12:32:50 -0400 (EDT)
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <alpine.LFD.2.03.1305291038220.1918@syhkavp.arg>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
 <20130528095528.GA14329@arm.com>
 <alpine.LFD.2.03.1305281340240.1918@syhkavp.arg>
 <20130529103728.GG17767@MacBook-Pro.local>
 <alpine.LFD.2.03.1305291038220.1918@syhkavp.arg>
Message-ID: <alpine.LFD.2.03.1305291230160.1918@syhkavp.arg>

On Wed, 29 May 2013, Nicolas Pitre wrote:

> On Wed, 29 May 2013, Catalin Marinas wrote:
> 
> > On Tue, May 28, 2013 at 06:52:27PM +0100, Nicolas Pitre wrote:
> > > On Tue, 28 May 2013, Catalin Marinas wrote:
> > > 
> > > > On Sat, May 25, 2013 at 04:53:19AM +0100, Nicolas Pitre wrote:
> > > > > On Thu, 23 May 2013, Catalin Marinas wrote:
> > > > > 
> > > > > > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > > > > > twice. I don't think we should remove the cache flushing in
> > > > > > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > > > > > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > > > > > don't work together).
> > > > > 
> > > > > VIVT and highmem do work together.  Highmem for ARM was in fact 
> > > > > developed on such a platform.
> > > > 
> > > > Thanks for confirming. Do you remember why kunmap() doesn't (need to)
> > > > flush the cache alias (for VIVT)? Or if it does, where?
> > > 
> > > kunmap() calls kunmap_high() which actually does not unmap anything but 
> > > only decrement a use count.  The page is kept around in case it is 
> > > kmap()'d again, in which case the kmap() will be almost free and the 
> > > page still warm.
> > > 
> > > It is only when the kmap() for a new page runs out of free pkmap  
> > > entries that the unused but still mapped pages are unmapped.  This 
> > > unmapping is done in flush_all_zero_pkmaps() where all the unused pages 
> > > are all unmapped at once.  The cache for all those pages is flushed with 
> > > flush_cache_kmaps() which on ARM maps to flush_cache_all() when the 
> > > cache is VIVT.
> > 
> > Thanks for clarification Nico. So if kmap_high_get() returns NULL, there
> > are no high aliases left in the cache.
> 
> Exact.

Just to be clear, this is true for VIVT only.
Unmapped highmem pages can still be cached with VIPT.


Nicolas


From tixy at linaro.org  Wed May 29 12:37:01 2013
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Wed, 29 May 2013 17:37:01 +0100
Subject: [PATCH 8/8] ARM: vexpress/dcscb: select multi-cluster SMP
 operations
In-Reply-To: <alpine.LFD.2.03.1305291054150.1918@syhkavp.arg>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-9-git-send-email-nicolas.pitre@linaro.org>
 <1369824504.3715.23.camel@linaro1.home>
 <alpine.LFD.2.03.1305291054150.1918@syhkavp.arg>
Message-ID: <1369845421.3715.76.camel@linaro1.home>

On Wed, 2013-05-29 at 11:17 -0400, Nicolas Pitre wrote:
> On Wed, 29 May 2013, Jon Medhurst (Tixy) wrote:
> 
> > On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> > > When the DCSCB code is successfully probed and initialized, then the
> > > generic MCPM SPM ops should be used as those operations need to be
> > > arbitrated through the MCPM layer.
> > > 
> > > Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
> > > ---
> > >  arch/arm/mach-vexpress/dcscb.c | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> > > index 1acc975360..ce3118dc05 100644
> > > --- a/arch/arm/mach-vexpress/dcscb.c
> > > +++ b/arch/arm/mach-vexpress/dcscb.c
> > > @@ -239,6 +239,8 @@ static int __init dcscb_init(void)
> > >  		return ret;
> > >  	}
> > >  
> > > +	mcpm_smp_set_ops();
> > > +
> > 
> > This is going to change the platform's smp_ops after setup_arch() has
> > already set them, is that OK and not too late?
> 
> Well...  The only methods being invoked before the booting of secondary 
> CPUs are smp_init_cpus and smp_prepare_cpus.  In the MCPM case they're 
> both no-ops.
> 
> > I ask, because for me, RTSM doesn't boot the secondary CPUs if we rely
> > on this change to set the smp_ops, but having a hook in setup_arch() to
> > select instead of the standard vexpress ops does work.
> 
> Strange.  That works for me both ways.

Actually, this patch series works for me if I take it on it's own but
what should be the same changes in the IKS branch don't. I'll do more
investigation...

-- 
Tixy



From santosh.shilimkar at ti.com  Wed May 29 12:38:00 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:00 -0400
Subject: [PATCH 00/14] ARM: OMAP5: hwmod,
 prm/cm data files and updates for 3.11
Message-ID: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>

Tony, Paul,

Here is another attempt to send the SOC data files for OMAP5 based devices.
As aligned on list, I have dropped clock data from the series.
That means for the boot, one clock data patch needs to be applied.
It is available on my git tree in 'out_of_tree/omap5_clk_data' branch.

With OMAP5 and AM33XX support is DT only, respective hwmod files are cleaned
up to remove iospace information and un-used hwmod. For 3.11 since OMAP4
is also targeted as DT only, its hwmod data files is also cleaned up.
Diffstat looks something like below.

27 files changed, 9013 insertions(+), 2764 deletions(-)

One can easily notice that the OMAP5 SOC data has significantly come down
becasue of iospace and rest of the hwmod clean-up.

Thanks to Sricharan, Vaibhav Bedia, Vaibhav H, Rajendra and Benoit for the
patches and testing.

The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:

  Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux.git for_3.11/omap5_data_files

for you to fetch changes up to 86b6a6dd106973df7f0c097fcb252e9e54b2f971:

  ARM: OMAP4: hwmod data: Clean up the data file (2013-05-29 11:51:30 -0400)

----------------------------------------------------------------

Benoit Cousson (7):
  ARM: OMAP5: PRM: Add OMAP54XX register and bitfield files
  ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
  ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
  ARM: OMAP5: SCRM: Add OMAP54XX header file.
  ARM: OMAP5: clockdomain data: Add OMAP54XX data and update the header
  ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
  ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data

Santosh Shilimkar (5):
  ARM: OMAP4+: PRM: Move function prototypes to common header for
    re-use
  ARM: OMAP4+: CM: Move function prototypes to common header for re-use
  ARM: OMAP4+: PRCM MPU: Move function prototypes to common header for
    re-use
  ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
  ARM: OMAP5: Enable build and frameowrk initialisations

Sricharan R (1):
  ARM: OMAP4: hwmod data: Clean up the data file

Vaibhav Hiremath (1):
  ARM: AM33XX: hwmod data: irq, dma and addr info clean up

 arch/arm/mach-omap2/Makefile                  |    4 +
 arch/arm/mach-omap2/clockdomain.h             |    1 +
 arch/arm/mach-omap2/clockdomains54xx_data.c   |  464 +++++
 arch/arm/mach-omap2/cm-regbits-54xx.h         | 1737 ++++++++++++++++
 arch/arm/mach-omap2/cm1_44xx.h                |    7 +-
 arch/arm/mach-omap2/cm1_54xx.h                |  218 ++
 arch/arm/mach-omap2/cm2_44xx.h                |    7 +-
 arch/arm/mach-omap2/cm2_54xx.h                |  394 ++++
 arch/arm/mach-omap2/cm_44xx_54xx.h            |   36 +
 arch/arm/mach-omap2/io.c                      |    7 +
 arch/arm/mach-omap2/omap_hwmod.h              |    1 +
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c    | 1067 ----------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c    | 1661 +--------------
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c    | 2151 ++++++++++++++++++++
 arch/arm/mach-omap2/powerdomain.h             |    1 +
 arch/arm/mach-omap2/powerdomains54xx_data.c   |  331 +++
 arch/arm/mach-omap2/prcm44xx.h                |    6 +
 arch/arm/mach-omap2/prcm_mpu44xx.h            |   14 +-
 arch/arm/mach-omap2/prcm_mpu54xx.h            |   87 +
 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h      |   36 +
 arch/arm/mach-omap2/prm-regbits-54xx.h        | 2701 +++++++++++++++++++++++++
 arch/arm/mach-omap2/prm44xx.h                 |   33 +-
 arch/arm/mach-omap2/prm44xx_54xx.h            |   58 +
 arch/arm/mach-omap2/prm54xx.h                 |  421 ++++
 arch/arm/mach-omap2/scrm54xx.h                |  231 +++
 arch/arm/mach-omap2/voltage.h                 |    1 +
 arch/arm/mach-omap2/voltagedomains54xx_data.c |  102 +
 27 files changed, 9013 insertions(+), 2764 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clockdomains54xx_data.c
 create mode 100644 arch/arm/mach-omap2/cm-regbits-54xx.h
 create mode 100644 arch/arm/mach-omap2/cm1_54xx.h
 create mode 100644 arch/arm/mach-omap2/cm2_54xx.h
 create mode 100644 arch/arm/mach-omap2/cm_44xx_54xx.h
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_54xx_data.c
 create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c
 create mode 100644 arch/arm/mach-omap2/prcm_mpu54xx.h
 create mode 100644 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
 create mode 100644 arch/arm/mach-omap2/prm-regbits-54xx.h
 create mode 100644 arch/arm/mach-omap2/prm44xx_54xx.h
 create mode 100644 arch/arm/mach-omap2/prm54xx.h
 create mode 100644 arch/arm/mach-omap2/scrm54xx.h
 create mode 100644 arch/arm/mach-omap2/voltagedomains54xx_data.c

-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:01 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:01 -0400
Subject: [PATCH 01/14] ARM: OMAP4+: PRM: Move function prototypes to common
 header for re-use
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-2-git-send-email-santosh.shilimkar@ti.com>

OMAP5 reuses OMAP4 PRM IP block which lets us re-use PRM functions.
So move the function prototypes from prm44xx.h to prm44xx_54xx.h
header. The suggestion came from Paul Walmsley as part of the
OMAP5 data file review.

This is preparatory  patch to add OMAP5 PRM data file.

Cc: Paul Walmsley <paul at pwsan.com>

Acked-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/prm44xx.h      |   33 +-------------------
 arch/arm/mach-omap2/prm44xx_54xx.h |   58 ++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/mach-omap2/prm44xx_54xx.h

diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbd..7db2422 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
+#include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
 
@@ -744,36 +745,4 @@
 #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
 #define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
-/* OMAP4-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP4 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap4_prm_vcvp_read(u8 offset);
-extern void omap4_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-extern void omap44xx_prm_reconfigure_io_chain(void);
-
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-
-extern int __init omap44xx_prm_init(void);
-extern u32 omap44xx_prm_get_reset_sources(void);
-
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 0000000..7cd22ab
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
+/*
+ * OMAP44xx and 54xx PRM common functions
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* OMAP4/OMAP5-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP4/OMAP5 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap4_prm_vcvp_read(u8 offset);
+extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+extern int __init omap44xx_prm_init(void);
+extern u32 omap44xx_prm_get_reset_sources(void);
+
+#endif
+
+#endif
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:03 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:03 -0400
Subject: [PATCH 03/14] ARM: OMAP4+: CM: Move function prototypes to common
 header for re-use
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-4-git-send-email-santosh.shilimkar@ti.com>

OMAP5 reuses OMAP4 CM IP block which lets us re-use CM1/CM2 functions.
So move the function prototypes from cm1_44xx.h, cm2_44xx.h to
cm_prm44xx_54xx.h header. The suggestion came from Paul Walmsley
as part of the OMAP5 data file review.

This is preparatory  patch to add OMAP5 CM data file.

Cc: Paul Walmsley <paul at pwsan.com>

Acked-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/cm1_44xx.h     |    7 ++-----
 arch/arm/mach-omap2/cm2_44xx.h     |    7 ++-----
 arch/arm/mach-omap2/cm_44xx_54xx.h |   36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 40 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cm_44xx_54xx.h

diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc..5ae8fe3 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 
+#include "cm_44xx_54xx.h"
+
 /* CM1 base address */
 #define OMAP4430_CM1_BASE		0x4a004000
 
@@ -217,9 +219,4 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET		0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
 
-/* Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 #endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72d..ee5136d 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 
+#include "cm_44xx_54xx.h"
+
 /* CM2 base address */
 #define OMAP4430_CM2_BASE		0x4a008000
 
@@ -449,9 +451,4 @@
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
 
-/* Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 #endif
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 0000000..4154f86
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
+ *
+ * Copyright (C) 2009-201333 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
+
+/* CM1 Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* CM2 Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:05 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:05 -0400
Subject: [PATCH 05/14] ARM: OMAP4+: PRCM MPU: Move function prototypes to
 common header for re-use
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-6-git-send-email-santosh.shilimkar@ti.com>

OMAP5 reuses OMAP4 MPU PRCM IP block which lets us re-use functions.
So move the function prototypes from prcm_mpu44xx.h to prcm_mpu_44xx_54xx.h
header. The suggestion came from Paul Walmsley as part of the
OMAP5 data file review.

This is preparatory  patch to add OMAP5 MPU PRCM data file.

Cc: Paul Walmsley <paul at pwsan.com>

Acked-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/prcm_mpu44xx.h       |   14 +-----------
 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h |   36 ++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h

diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7b..059bd4f 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 
+#include "prcm_mpu_44xx_54xx.h"
 #include "common.h"
 
-# ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
-# endif
-
 #define OMAP4430_PRCM_MPU_BASE			0x48243000
 
 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)				\
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET		0x0018
 #define OMAP4430_CM_CPU1_CLKSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
-					    s16 idx);
-extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 0000000..ca149e7
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx PRCM MPU function prototypes
+ *
+ * Copyright (C) 2010, 2013 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+
+#ifndef __ASSEMBLER__
+extern void __iomem *prcm_mpu_base;
+
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+					    s16 idx);
+extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
+#endif
+
+#endif
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:06 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:06 -0400
Subject: [PATCH 06/14] ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-7-git-send-email-santosh.shilimkar@ti.com>

From: Benoit Cousson <b-cousson at ti.com>

Add the PRCM MPU registers for OMAP54XX platforms.

Cc: Paul Walmsley <paul at pwsan.com>

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/prcm44xx.h     |    6 +++
 arch/arm/mach-omap2/prcm_mpu54xx.h |   87 ++++++++++++++++++++++++++++++++++++
 2 files changed, 93 insertions(+)
 create mode 100644 arch/arm/mach-omap2/prcm_mpu54xx.h

diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb..f429cdd 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
 #define OMAP4430_SCRM_PARTITION			4
 #define OMAP4430_PRCM_MPU_PARTITION		5
 
+#define OMAP54XX_PRM_PARTITION			1
+#define OMAP54XX_CM_CORE_AON_PARTITION		2
+#define OMAP54XX_CM_CORE_PARTITION		3
+#define OMAP54XX_SCRM_PARTITION			4
+#define OMAP54XX_PRCM_MPU_PARTITION		5
+
 /*
  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
  * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 0000000..bc2ce32
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
+/*
+ * OMAP54xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+
+#include "prcm_mpu_44xx_54xx.h"
+#include "common.h"
+
+#define OMAP54XX_PRCM_MPU_BASE			0x48243000
+
+#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)				\
+	OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* PRCM_MPU instances */
+#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST	0x0000
+#define OMAP54XX_PRCM_MPU_DEVICE_INST		0x0200
+#define OMAP54XX_PRCM_MPU_PRM_C0_INST		0x0400
+#define OMAP54XX_PRCM_MPU_CM_C0_INST		0x0600
+#define OMAP54XX_PRCM_MPU_PRM_C1_INST		0x0800
+#define OMAP54XX_PRCM_MPU_CM_C1_INST		0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS	0x0000
+#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS	0x0000
+
+
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+
+/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
+#define OMAP54XX_REVISION_PRCM_MPU_OFFSET			0x0000
+
+/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
+#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET			0x0000
+#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET		0x0004
+#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET		0x0010
+#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET	0x0014
+
+/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
+#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET			0x0010
+#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET			0x0014
+#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET			0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
+#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET			0x0000
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET			0x0020
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL				OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
+
+/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
+#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET			0x0010
+#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET			0x0014
+#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET			0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
+#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET			0x0000
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET			0x0020
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL				OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
+
+#endif
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:07 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:07 -0400
Subject: [PATCH 07/14] ARM: OMAP5: SCRM: Add OMAP54XX header file.
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-8-git-send-email-santosh.shilimkar@ti.com>

From: Benoit Cousson <b-cousson at ti.com>

Adding the OMAP5 specific header for SCRM module.

Cc: Paul Walmsley <paul at pwsan.com>

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/scrm54xx.h |  231 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 231 insertions(+)
 create mode 100644 arch/arm/mach-omap2/scrm54xx.h

diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 0000000..57e86c8
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
+/*
+ * OMAP54XX SCRM registers and bitfields
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+
+#define OMAP5_SCRM_BASE		0x4ae0a000
+
+#define OMAP54XX_SCRM_REGADDR(reg)				\
+	OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
+
+/* SCRM */
+
+/* SCRM.SCRM register offsets */
+#define OMAP5_SCRM_REVISION_SCRM_OFFSET		0x0000
+#define OMAP5_SCRM_REVISION_SCRM		OMAP54XX_SCRM_REGADDR(0x0000)
+#define OMAP5_SCRM_CLKSETUPTIME_OFFSET		0x0100
+#define OMAP5_SCRM_CLKSETUPTIME			OMAP54XX_SCRM_REGADDR(0x0100)
+#define OMAP5_SCRM_PMICSETUPTIME_OFFSET		0x0104
+#define OMAP5_SCRM_PMICSETUPTIME		OMAP54XX_SCRM_REGADDR(0x0104)
+#define OMAP5_SCRM_ALTCLKSRC_OFFSET		0x0110
+#define OMAP5_SCRM_ALTCLKSRC			OMAP54XX_SCRM_REGADDR(0x0110)
+#define OMAP5_SCRM_MODEMCLKM_OFFSET		0x0118
+#define OMAP5_SCRM_MODEMCLKM			OMAP54XX_SCRM_REGADDR(0x0118)
+#define OMAP5_SCRM_D2DCLKM_OFFSET		0x011c
+#define OMAP5_SCRM_D2DCLKM			OMAP54XX_SCRM_REGADDR(0x011c)
+#define OMAP5_SCRM_EXTCLKREQ_OFFSET		0x0200
+#define OMAP5_SCRM_EXTCLKREQ			OMAP54XX_SCRM_REGADDR(0x0200)
+#define OMAP5_SCRM_ACCCLKREQ_OFFSET		0x0204
+#define OMAP5_SCRM_ACCCLKREQ			OMAP54XX_SCRM_REGADDR(0x0204)
+#define OMAP5_SCRM_PWRREQ_OFFSET		0x0208
+#define OMAP5_SCRM_PWRREQ			OMAP54XX_SCRM_REGADDR(0x0208)
+#define OMAP5_SCRM_AUXCLKREQ0_OFFSET		0x0210
+#define OMAP5_SCRM_AUXCLKREQ0			OMAP54XX_SCRM_REGADDR(0x0210)
+#define OMAP5_SCRM_AUXCLKREQ1_OFFSET		0x0214
+#define OMAP5_SCRM_AUXCLKREQ1			OMAP54XX_SCRM_REGADDR(0x0214)
+#define OMAP5_SCRM_AUXCLKREQ2_OFFSET		0x0218
+#define OMAP5_SCRM_AUXCLKREQ2			OMAP54XX_SCRM_REGADDR(0x0218)
+#define OMAP5_SCRM_AUXCLKREQ3_OFFSET		0x021c
+#define OMAP5_SCRM_AUXCLKREQ3			OMAP54XX_SCRM_REGADDR(0x021c)
+#define OMAP5_SCRM_AUXCLKREQ4_OFFSET		0x0220
+#define OMAP5_SCRM_AUXCLKREQ4			OMAP54XX_SCRM_REGADDR(0x0220)
+#define OMAP5_SCRM_AUXCLKREQ5_OFFSET		0x0224
+#define OMAP5_SCRM_AUXCLKREQ5			OMAP54XX_SCRM_REGADDR(0x0224)
+#define OMAP5_SCRM_D2DCLKREQ_OFFSET		0x0234
+#define OMAP5_SCRM_D2DCLKREQ			OMAP54XX_SCRM_REGADDR(0x0234)
+#define OMAP5_SCRM_AUXCLK0_OFFSET		0x0310
+#define OMAP5_SCRM_AUXCLK0			OMAP54XX_SCRM_REGADDR(0x0310)
+#define OMAP5_SCRM_AUXCLK1_OFFSET		0x0314
+#define OMAP5_SCRM_AUXCLK1			OMAP54XX_SCRM_REGADDR(0x0314)
+#define OMAP5_SCRM_AUXCLK2_OFFSET		0x0318
+#define OMAP5_SCRM_AUXCLK2			OMAP54XX_SCRM_REGADDR(0x0318)
+#define OMAP5_SCRM_AUXCLK3_OFFSET		0x031c
+#define OMAP5_SCRM_AUXCLK3			OMAP54XX_SCRM_REGADDR(0x031c)
+#define OMAP5_SCRM_AUXCLK4_OFFSET		0x0320
+#define OMAP5_SCRM_AUXCLK4			OMAP54XX_SCRM_REGADDR(0x0320)
+#define OMAP5_SCRM_AUXCLK5_OFFSET		0x0324
+#define OMAP5_SCRM_AUXCLK5			OMAP54XX_SCRM_REGADDR(0x0324)
+#define OMAP5_SCRM_RSTTIME_OFFSET		0x0400
+#define OMAP5_SCRM_RSTTIME			OMAP54XX_SCRM_REGADDR(0x0400)
+#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET		0x0418
+#define OMAP5_SCRM_MODEMRSTCTRL			OMAP54XX_SCRM_REGADDR(0x0418)
+#define OMAP5_SCRM_D2DRSTCTRL_OFFSET		0x041c
+#define OMAP5_SCRM_D2DRSTCTRL			OMAP54XX_SCRM_REGADDR(0x041c)
+#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET	0x0420
+#define OMAP5_SCRM_EXTPWRONRSTCTRL		OMAP54XX_SCRM_REGADDR(0x0420)
+#define OMAP5_SCRM_EXTWARMRSTST_OFFSET		0x0510
+#define OMAP5_SCRM_EXTWARMRSTST			OMAP54XX_SCRM_REGADDR(0x0510)
+#define OMAP5_SCRM_APEWARMRSTST_OFFSET		0x0514
+#define OMAP5_SCRM_APEWARMRSTST			OMAP54XX_SCRM_REGADDR(0x0514)
+#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET	0x0518
+#define OMAP5_SCRM_MODEMWARMRSTST		OMAP54XX_SCRM_REGADDR(0x0518)
+#define OMAP5_SCRM_D2DWARMRSTST_OFFSET		0x051c
+#define OMAP5_SCRM_D2DWARMRSTST			OMAP54XX_SCRM_REGADDR(0x051c)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5, D2DCLKREQ
+ */
+#define OMAP5_ACCURACY_SHIFT			1
+#define OMAP5_ACCURACY_WIDTH			0x1
+#define OMAP5_ACCURACY_MASK			(1 << 1)
+
+/* Used by APEWARMRSTST */
+#define OMAP5_APEWARMRSTST_SHIFT		1
+#define OMAP5_APEWARMRSTST_WIDTH		0x1
+#define OMAP5_APEWARMRSTST_MASK			(1 << 1)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_CLKDIV_SHIFT			16
+#define OMAP5_CLKDIV_WIDTH			0x4
+#define OMAP5_CLKDIV_MASK			(0xf << 16)
+
+/* Used by D2DCLKM, MODEMCLKM */
+#define OMAP5_CLK_32KHZ_SHIFT			0
+#define OMAP5_CLK_32KHZ_WIDTH			0x1
+#define OMAP5_CLK_32KHZ_MASK			(1 << 0)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_COLDRST_SHIFT			0
+#define OMAP5_COLDRST_WIDTH			0x1
+#define OMAP5_COLDRST_MASK			(1 << 0)
+
+/* Used by D2DWARMRSTST */
+#define OMAP5_D2DWARMRSTST_SHIFT		3
+#define OMAP5_D2DWARMRSTST_WIDTH		0x1
+#define OMAP5_D2DWARMRSTST_MASK			(1 << 3)
+
+/* Used by AUXCLK0 */
+#define OMAP5_DISABLECLK_SHIFT			9
+#define OMAP5_DISABLECLK_WIDTH			0x1
+#define OMAP5_DISABLECLK_MASK			(1 << 9)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_DOWNTIME_SHIFT			16
+#define OMAP5_DOWNTIME_WIDTH			0x6
+#define OMAP5_DOWNTIME_MASK			(0x3f << 16)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_ENABLE_SHIFT			8
+#define OMAP5_ENABLE_WIDTH			0x1
+#define OMAP5_ENABLE_MASK			(1 << 8)
+
+/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
+#define OMAP5_ENABLE_0_0_SHIFT			0
+#define OMAP5_ENABLE_0_0_WIDTH			0x1
+#define OMAP5_ENABLE_0_0_MASK			(1 << 0)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_EXT_SHIFT			3
+#define OMAP5_ENABLE_EXT_WIDTH			0x1
+#define OMAP5_ENABLE_EXT_MASK			(1 << 3)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_INT_SHIFT			2
+#define OMAP5_ENABLE_INT_WIDTH			0x1
+#define OMAP5_ENABLE_INT_MASK			(1 << 2)
+
+/* Used by EXTWARMRSTST */
+#define OMAP5_EXTWARMRSTST_SHIFT		0
+#define OMAP5_EXTWARMRSTST_WIDTH		0x1
+#define OMAP5_EXTWARMRSTST_MASK			(1 << 0)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5
+ */
+#define OMAP5_MAPPING_SHIFT			2
+#define OMAP5_MAPPING_WIDTH			0x3
+#define OMAP5_MAPPING_MASK			(0x7 << 2)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_MODE_SHIFT			0
+#define OMAP5_MODE_WIDTH			0x2
+#define OMAP5_MODE_MASK				(0x3 << 0)
+
+/* Used by MODEMWARMRSTST */
+#define OMAP5_MODEMWARMRSTST_SHIFT		2
+#define OMAP5_MODEMWARMRSTST_WIDTH		0x1
+#define OMAP5_MODEMWARMRSTST_MASK		(1 << 2)
+
+/*
+ * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
+ * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
+ * D2DCLKREQ, EXTCLKREQ, PWRREQ
+ */
+#define OMAP5_POLARITY_SHIFT			0
+#define OMAP5_POLARITY_WIDTH			0x1
+#define OMAP5_POLARITY_MASK			(1 << 0)
+
+/* Used by EXTPWRONRSTCTRL */
+#define OMAP5_PWRONRST_SHIFT			1
+#define OMAP5_PWRONRST_WIDTH			0x1
+#define OMAP5_PWRONRST_MASK			(1 << 1)
+
+/* Used by REVISION_SCRM */
+#define OMAP5_REV_SHIFT				0
+#define OMAP5_REV_WIDTH				0x8
+#define OMAP5_REV_MASK				(0xff << 0)
+
+/* Used by RSTTIME */
+#define OMAP5_RSTTIME_SHIFT			0
+#define OMAP5_RSTTIME_WIDTH			0x4
+#define OMAP5_RSTTIME_MASK			(0xf << 0)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_SETUPTIME_SHIFT			0
+#define OMAP5_SETUPTIME_WIDTH			0xc
+#define OMAP5_SETUPTIME_MASK			(0xfff << 0)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_SLEEPTIME_SHIFT			0
+#define OMAP5_SLEEPTIME_WIDTH			0x6
+#define OMAP5_SLEEPTIME_MASK			(0x3f << 0)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_SRCSELECT_SHIFT			1
+#define OMAP5_SRCSELECT_WIDTH			0x2
+#define OMAP5_SRCSELECT_MASK			(0x3 << 1)
+
+/* Used by D2DCLKM */
+#define OMAP5_SYSCLK_SHIFT			1
+#define OMAP5_SYSCLK_WIDTH			0x1
+#define OMAP5_SYSCLK_MASK			(1 << 1)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_WAKEUPTIME_SHIFT			16
+#define OMAP5_WAKEUPTIME_WIDTH			0x6
+#define OMAP5_WAKEUPTIME_MASK			(0x3f << 16)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_WARMRST_SHIFT			1
+#define OMAP5_WARMRST_WIDTH			0x1
+#define OMAP5_WARMRST_MASK			(1 << 1)
+
+#endif
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:11 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:11 -0400
Subject: [PATCH 11/14] ARM: OMAP5: voltagedomain data: Add OMAP5 voltage
 domain data
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-12-git-send-email-santosh.shilimkar@ti.com>

Add voltagedomain related data for OMAP54XX SOCs. OMAP4 OPP data is
used for now. OMAP5 OPP data will be added as part of OMAP5 DVFS
support.

Cc: Kevin Hilman <khilman at deeprootsystems.com>
Cc: Paul Walmsley <paul at pwsan.com>

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/voltage.h                 |    1 +
 arch/arm/mach-omap2/voltagedomains54xx_data.c |  102 +++++++++++++++++++++++++
 2 files changed, 103 insertions(+)
 create mode 100644 arch/arm/mach-omap2/voltagedomains54xx_data.c

diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f1..5998eed 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
 extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);
+extern void omap54xx_voltagedomains_init(void);
 
 struct voltagedomain *voltdm_lookup(const char *name);
 void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 0000000..72b8971
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,102 @@
+/*
+ * OMAP5 Voltage Management Routines
+ *
+ * Based on voltagedomains44xx_data.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include "common.h"
+
+#include "prm54xx.h"
+#include "voltage.h"
+#include "omap_opp_data.h"
+#include "vc.h"
+#include "vp.h"
+
+static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
+	.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
+	.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
+	.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+};
+
+static struct voltagedomain omap5_voltdm_mpu = {
+	.name = "mpu",
+	.scalable = true,
+	.read = omap4_prm_vcvp_read,
+	.write = omap4_prm_vcvp_write,
+	.rmw = omap4_prm_vcvp_rmw,
+	.vc = &omap4_vc_mpu,
+	.vfsm = &omap5_vdd_mpu_vfsm,
+	.vp = &omap4_vp_mpu,
+};
+
+static struct voltagedomain omap5_voltdm_mm = {
+	.name = "mm",
+	.scalable = true,
+	.read = omap4_prm_vcvp_read,
+	.write = omap4_prm_vcvp_write,
+	.rmw = omap4_prm_vcvp_rmw,
+	.vc = &omap4_vc_iva,
+	.vfsm = &omap5_vdd_mm_vfsm,
+	.vp = &omap4_vp_iva,
+};
+
+static struct voltagedomain omap5_voltdm_core = {
+	.name = "core",
+	.scalable = true,
+	.read = omap4_prm_vcvp_read,
+	.write = omap4_prm_vcvp_write,
+	.rmw = omap4_prm_vcvp_rmw,
+	.vc = &omap4_vc_core,
+	.vfsm = &omap5_vdd_core_vfsm,
+	.vp = &omap4_vp_core,
+};
+
+static struct voltagedomain omap5_voltdm_wkup = {
+	.name = "wkup",
+};
+
+static struct voltagedomain *voltagedomains_omap5[] __initdata = {
+	&omap5_voltdm_mpu,
+	&omap5_voltdm_mm,
+	&omap5_voltdm_core,
+	&omap5_voltdm_wkup,
+	NULL,
+};
+
+static const char *sys_clk_name __initdata = "sys_clkin";
+
+void __init omap54xx_voltagedomains_init(void)
+{
+	struct voltagedomain *voltdm;
+	int i;
+
+	/*
+	 * XXX Will depend on the process, validation, and binning
+	 * for the currently-running IC. Use OMAP4 data for time being.
+	 */
+#ifdef CONFIG_PM_OPP
+	omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
+	omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data;
+	omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
+#endif
+
+	for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
+		voltdm->sys_clk.name = sys_clk_name;
+
+	voltdm_init(voltagedomains_omap5);
+};
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:09 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:09 -0400
Subject: [PATCH 09/14] ARM: OMAP5: powerdomain data: Add OMAP54XX data and
 update the header
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-10-git-send-email-santosh.shilimkar@ti.com>

From: Benoit Cousson <b-cousson at ti.com>

Add the data file to describe all power domains inside the OMAP54XX soc.

Cc: Paul Walmsley <paul at pwsan.com>

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/powerdomain.h           |    1 +
 arch/arm/mach-omap2/powerdomains54xx_data.c |  331 +++++++++++++++++++++++++++
 2 files changed, 332 insertions(+)
 create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c

diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c360..3d82f50 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -253,6 +253,7 @@ extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
+extern void omap54xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 0000000..81f8a7c
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
+/*
+ * OMAP54XX Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm_mpu54xx.h"
+
+/* core_54xx_pwrdm: CORE power domain */
+static struct powerdomain core_54xx_pwrdm = {
+	.name		  = "core_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_CORE_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.banks		  = 5,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
+		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
+		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
+		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
+		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
+		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
+		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
+		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
+		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* abe_54xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_54xx_pwrdm = {
+	.name		  = "abe_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_ABE_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF,
+	.banks		  = 2,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* aessmem */
+		[1] = PWRSTS_OFF_RET,	/* periphmem */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* aessmem */
+		[1] = PWRSTS_OFF_RET,	/* periphmem */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_54xx_pwrdm = {
+	.name		  = "coreaon_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_COREAON_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_ON,
+};
+
+/* dss_54xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_54xx_pwrdm = {
+	.name		  = "dss_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_DSS_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* dss_mem */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* dss_mem */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_54xx_pwrdm = {
+	.name		  = "cpu0_pwrdm",
+	.voltdm		  = { .name = "mpu" },
+	.prcm_offs	  = OMAP54XX_PRCM_MPU_PRM_C0_INST,
+	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_ON,	/* cpu0_l1 */
+	},
+};
+
+/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_54xx_pwrdm = {
+	.name		  = "cpu1_pwrdm",
+	.voltdm		  = { .name = "mpu" },
+	.prcm_offs	  = OMAP54XX_PRCM_MPU_PRM_C1_INST,
+	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_ON,	/* cpu1_l1 */
+	},
+};
+
+/* emu_54xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_54xx_pwrdm = {
+	.name		  = "emu_pwrdm",
+	.voltdm		  = { .name = "wkup" },
+	.prcm_offs	  = OMAP54XX_PRM_EMU_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* emu_bank */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* emu_bank */
+	},
+};
+
+/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_54xx_pwrdm = {
+	.name		  = "mpu_pwrdm",
+	.voltdm		  = { .name = "mpu" },
+	.prcm_offs	  = OMAP54XX_PRM_MPU_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.banks		  = 2,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
+		[1] = PWRSTS_RET,	/* mpu_ram */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
+		[1] = PWRSTS_OFF_RET,	/* mpu_ram */
+	},
+};
+
+/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_54xx_pwrdm = {
+	.name		  = "custefuse_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_CUSTEFUSE_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp_54xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp_54xx_pwrdm = {
+	.name		  = "dsp_pwrdm",
+	.voltdm		  = { .name = "mm" },
+	.prcm_offs	  = OMAP54XX_PRM_DSP_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.banks		  = 3,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* dsp_edma */
+		[1] = PWRSTS_OFF_RET,	/* dsp_l1 */
+		[2] = PWRSTS_OFF_RET,	/* dsp_l2 */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* dsp_edma */
+		[1] = PWRSTS_OFF_RET,	/* dsp_l1 */
+		[2] = PWRSTS_OFF_RET,	/* dsp_l2 */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_54xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_54xx_pwrdm = {
+	.name		  = "cam_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_CAM_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* cam_mem */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* cam_mem */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
+static struct powerdomain l3init_54xx_pwrdm = {
+	.name		  = "l3init_pwrdm",
+	.voltdm		  = { .name = "core" },
+	.prcm_offs	  = OMAP54XX_PRM_L3INIT_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.banks		  = 2,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* l3init_bank1 */
+		[1] = PWRSTS_OFF_RET,	/* l3init_bank2 */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* l3init_bank1 */
+		[1] = PWRSTS_OFF_RET,	/* l3init_bank2 */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_54xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_54xx_pwrdm = {
+	.name		  = "gpu_pwrdm",
+	.voltdm		  = { .name = "mm" },
+	.prcm_offs	  = OMAP54XX_PRM_GPU_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_54xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_54xx_pwrdm = {
+	.name		  = "wkupaon_pwrdm",
+	.voltdm		  = { .name = "wkup" },
+	.prcm_offs	  = OMAP54XX_PRM_WKUPAON_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_ON,
+	.banks		  = 1,
+	.pwrsts_mem_ret	= {
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_ON,	/* wkup_bank */
+	},
+};
+
+/* iva_54xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_54xx_pwrdm = {
+	.name		  = "iva_pwrdm",
+	.voltdm		  = { .name = "mm" },
+	.prcm_offs	  = OMAP54XX_PRM_IVA_INST,
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF,
+	.banks		  = 4,
+	.pwrsts_mem_ret	= {
+		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
+		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
+		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
+		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
+	},
+	.pwrsts_mem_on	= {
+		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
+		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
+		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
+		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
+	},
+	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap54xx[] __initdata = {
+	&core_54xx_pwrdm,
+	&abe_54xx_pwrdm,
+	&coreaon_54xx_pwrdm,
+	&dss_54xx_pwrdm,
+	&cpu0_54xx_pwrdm,
+	&cpu1_54xx_pwrdm,
+	&emu_54xx_pwrdm,
+	&mpu_54xx_pwrdm,
+	&custefuse_54xx_pwrdm,
+	&dsp_54xx_pwrdm,
+	&cam_54xx_pwrdm,
+	&l3init_54xx_pwrdm,
+	&gpu_54xx_pwrdm,
+	&wkupaon_54xx_pwrdm,
+	&iva_54xx_pwrdm,
+	NULL
+};
+
+void __init omap54xx_powerdomains_init(void)
+{
+	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+	pwrdm_register_pwrdms(powerdomains_omap54xx);
+	pwrdm_complete_init();
+}
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:12 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:12 -0400
Subject: [PATCH 12/14] ARM: OMAP5: Enable build and frameowrk initialisations
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-13-git-send-email-santosh.shilimkar@ti.com>

Include the OMAP5 data files in build. Initialise the voltage, power,
clock domains.

Cc: Paul Walmsley <paul at pwsan.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/Makefile |    4 ++++
 arch/arm/mach-omap2/io.c     |    7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..27448ab 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -127,6 +127,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= voltagedomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(voltagedomain-common)
+obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
 
 # OMAP powerdomain framework
 powerdomain-common			+= powerdomain.o powerdomain-common.o
@@ -141,6 +142,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)		+= powerdomains33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5)			+= powerdomains54xx_data.o
 
 # PRCM clockdomain control
 clockdomain-common			+= clockdomain.o
@@ -156,6 +158,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)		+= clockdomains33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5)			+= clockdomains54xx_data.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clock-common) clock2xxx.o
@@ -198,6 +201,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
+obj-$(CONFIG_SOC_OMAP5)			+= omap_hwmod_54xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)			+= emu.o
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..a0cc2bb 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -631,7 +631,14 @@ void __init omap5_init_early(void)
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 	omap_prm_base_init();
 	omap_cm_base_init();
+	omap44xx_prm_init();
 	omap5xxx_check_revision();
+	omap54xx_voltagedomains_init();
+	omap54xx_powerdomains_init();
+	omap54xx_clockdomains_init();
+	omap54xx_hwmod_init();
+	omap_hwmod_init_postsetup();
+
 }
 #endif
 
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:08 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:08 -0400
Subject: [PATCH 08/14] ARM: OMAP5: clockdomain data: Add OMAP54XX data and
 update the header
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-9-git-send-email-santosh.shilimkar@ti.com>

From: Benoit Cousson <b-cousson at ti.com>

Add the data file to describe all clock domains inside the OMAP54XX soc.

Cc: Paul Walmsley <paul at pwsan.com>

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/clockdomain.h           |    1 +
 arch/arm/mach-omap2/clockdomains54xx_data.c |  464 +++++++++++++++++++++++++++
 2 files changed, 465 insertions(+)
 create mode 100644 arch/arm/mach-omap2/clockdomains54xx_data.c

diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da3765..daeecf1 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
+extern void __init omap54xx_clockdomains_init(void);
 
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 0000000..1a3c69d
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
+/*
+ * OMAP54XX Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+
+#include "cm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu54xx.h"
+
+/* Static Dependencies for OMAP4 Clock Domains */
+
+static struct clkdm_dep c2c_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3init_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l3main2_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "dss_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "ipu_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3init_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ .clkdm_name = "l4sec_clkdm" },
+	{ .clkdm_name = "wkupaon_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep dsp_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3init_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l3main2_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ .clkdm_name = "wkupaon_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3main2_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep ipu_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "dsp_clkdm" },
+	{ .clkdm_name = "dss_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "gpu_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3init_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l3main2_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ .clkdm_name = "l4sec_clkdm" },
+	{ .clkdm_name = "wkupaon_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ .clkdm_name = "l4sec_clkdm" },
+	{ .clkdm_name = "wkupaon_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3init_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l3main2_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+	{ .clkdm_name = "abe_clkdm" },
+	{ .clkdm_name = "dsp_clkdm" },
+	{ .clkdm_name = "dss_clkdm" },
+	{ .clkdm_name = "emif_clkdm" },
+	{ .clkdm_name = "gpu_clkdm" },
+	{ .clkdm_name = "ipu_clkdm" },
+	{ .clkdm_name = "iva_clkdm" },
+	{ .clkdm_name = "l3init_clkdm" },
+	{ .clkdm_name = "l3main1_clkdm" },
+	{ .clkdm_name = "l3main2_clkdm" },
+	{ .clkdm_name = "l4cfg_clkdm" },
+	{ .clkdm_name = "l4per_clkdm" },
+	{ .clkdm_name = "l4sec_clkdm" },
+	{ .clkdm_name = "wkupaon_clkdm" },
+	{ NULL },
+};
+
+static struct clockdomain l4sec_54xx_clkdm = {
+	.name		  = "l4sec_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
+	.dep_bit	  = OMAP54XX_L4SEC_STATDEP_SHIFT,
+	.wkdep_srcs	  = l4sec_wkup_sleep_deps,
+	.sleepdep_srcs	  = l4sec_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain iva_54xx_clkdm = {
+	.name		  = "iva_clkdm",
+	.pwrdm		  = { .name = "iva_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_IVA_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
+	.dep_bit	  = OMAP54XX_IVA_STATDEP_SHIFT,
+	.wkdep_srcs	  = iva_wkup_sleep_deps,
+	.sleepdep_srcs	  = iva_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mipiext_54xx_clkdm = {
+	.name		  = "mipiext_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
+	.wkdep_srcs	  = mipiext_wkup_sleep_deps,
+	.sleepdep_srcs	  = mipiext_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main2_54xx_clkdm = {
+	.name		  = "l3main2_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
+	.dep_bit	  = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main1_54xx_clkdm = {
+	.name		  = "l3main1_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+	.dep_bit	  = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_54xx_clkdm = {
+	.name		  = "custefuse_clkdm",
+	.pwrdm		  = { .name = "custefuse_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_54xx_clkdm = {
+	.name		  = "ipu_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
+	.dep_bit	  = OMAP54XX_IPU_STATDEP_SHIFT,
+	.wkdep_srcs	  = ipu_wkup_sleep_deps,
+	.sleepdep_srcs	  = ipu_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_54xx_clkdm = {
+	.name		  = "l4cfg_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
+	.dep_bit	  = OMAP54XX_L4CFG_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain abe_54xx_clkdm = {
+	.name		  = "abe_clkdm",
+	.pwrdm		  = { .name = "abe_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_AON_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_AON_ABE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
+	.dep_bit	  = OMAP54XX_ABE_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dss_54xx_clkdm = {
+	.name		  = "dss_clkdm",
+	.pwrdm		  = { .name = "dss_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_DSS_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
+	.dep_bit	  = OMAP54XX_DSS_STATDEP_SHIFT,
+	.wkdep_srcs	  = dss_wkup_sleep_deps,
+	.sleepdep_srcs	  = dss_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp_54xx_clkdm = {
+	.name		  = "dsp_clkdm",
+	.pwrdm		  = { .name = "dsp_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_AON_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_AON_DSP_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
+	.dep_bit	  = OMAP54XX_DSP_STATDEP_SHIFT,
+	.wkdep_srcs	  = dsp_wkup_sleep_deps,
+	.sleepdep_srcs	  = dsp_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain c2c_54xx_clkdm = {
+	.name		  = "c2c_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
+	.wkdep_srcs	  = c2c_wkup_sleep_deps,
+	.sleepdep_srcs	  = c2c_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l4per_54xx_clkdm = {
+	.name		  = "l4per_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
+	.dep_bit	  = OMAP54XX_L4PER_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_54xx_clkdm = {
+	.name		  = "gpu_clkdm",
+	.pwrdm		  = { .name = "gpu_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_GPU_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
+	.dep_bit	  = OMAP54XX_GPU_STATDEP_SHIFT,
+	.wkdep_srcs	  = gpu_wkup_sleep_deps,
+	.sleepdep_srcs	  = gpu_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_54xx_clkdm = {
+	.name		  = "wkupaon_clkdm",
+	.pwrdm		  = { .name = "wkupaon_pwrdm" },
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.cm_inst	  = OMAP54XX_PRM_WKUPAON_CM_INST,
+	.clkdm_offs	  = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+	.dep_bit	  = OMAP54XX_WKUPAON_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu0_54xx_clkdm = {
+	.name		  = "mpu0_clkdm",
+	.pwrdm		  = { .name = "cpu0_pwrdm" },
+	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
+	.cm_inst	  = OMAP54XX_PRCM_MPU_CM_C0_INST,
+	.clkdm_offs	  = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu1_54xx_clkdm = {
+	.name		  = "mpu1_clkdm",
+	.pwrdm		  = { .name = "cpu1_pwrdm" },
+	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
+	.cm_inst	  = OMAP54XX_PRCM_MPU_CM_C1_INST,
+	.clkdm_offs	  = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain coreaon_54xx_clkdm = {
+	.name		  = "coreaon_clkdm",
+	.pwrdm		  = { .name = "coreaon_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_COREAON_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu_54xx_clkdm = {
+	.name		  = "mpu_clkdm",
+	.pwrdm		  = { .name = "mpu_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_AON_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_AON_MPU_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+	.wkdep_srcs	  = mpu_wkup_sleep_deps,
+	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3init_54xx_clkdm = {
+	.name		  = "l3init_clkdm",
+	.pwrdm		  = { .name = "l3init_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_L3INIT_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+	.dep_bit	  = OMAP54XX_L3INIT_STATDEP_SHIFT,
+	.wkdep_srcs	  = l3init_wkup_sleep_deps,
+	.sleepdep_srcs	  = l3init_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dma_54xx_clkdm = {
+	.name		  = "dma_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
+	.wkdep_srcs	  = dma_wkup_sleep_deps,
+	.sleepdep_srcs	  = dma_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_54xx_clkdm = {
+	.name		  = "l3instr_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain emif_54xx_clkdm = {
+	.name		  = "emif_clkdm",
+	.pwrdm		  = { .name = "core_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
+	.dep_bit	  = OMAP54XX_EMIF_STATDEP_SHIFT,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_54xx_clkdm = {
+	.name		  = "emu_clkdm",
+	.pwrdm		  = { .name = "emu_pwrdm" },
+	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
+	.cm_inst	  = OMAP54XX_PRM_EMU_CM_INST,
+	.clkdm_offs	  = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
+	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain cam_54xx_clkdm = {
+	.name		  = "cam_clkdm",
+	.pwrdm		  = { .name = "cam_pwrdm" },
+	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
+	.cm_inst	  = OMAP54XX_CM_CORE_CAM_INST,
+	.clkdm_offs	  = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
+	.wkdep_srcs	  = cam_wkup_sleep_deps,
+	.sleepdep_srcs	  = cam_wkup_sleep_deps,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_omap54xx[] __initdata = {
+	&l4sec_54xx_clkdm,
+	&iva_54xx_clkdm,
+	&mipiext_54xx_clkdm,
+	&l3main2_54xx_clkdm,
+	&l3main1_54xx_clkdm,
+	&custefuse_54xx_clkdm,
+	&ipu_54xx_clkdm,
+	&l4cfg_54xx_clkdm,
+	&abe_54xx_clkdm,
+	&dss_54xx_clkdm,
+	&dsp_54xx_clkdm,
+	&c2c_54xx_clkdm,
+	&l4per_54xx_clkdm,
+	&gpu_54xx_clkdm,
+	&wkupaon_54xx_clkdm,
+	&mpu0_54xx_clkdm,
+	&mpu1_54xx_clkdm,
+	&coreaon_54xx_clkdm,
+	&mpu_54xx_clkdm,
+	&l3init_54xx_clkdm,
+	&dma_54xx_clkdm,
+	&l3instr_54xx_clkdm,
+	&emif_54xx_clkdm,
+	&emu_54xx_clkdm,
+	&cam_54xx_clkdm,
+	NULL
+};
+
+void __init omap54xx_clockdomains_init(void)
+{
+	clkdm_register_platform_funcs(&omap4_clkdm_operations);
+	clkdm_register_clkdms(clockdomains_omap54xx);
+	clkdm_complete_init();
+}
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:10 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:10 -0400
Subject: [PATCH 10/14] ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod
 data
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-11-git-send-email-santosh.shilimkar@ti.com>

From: Benoit Cousson <b-cousson at ti.com>

Adding the hwmod data for OMAP54xx SOCs.

Additional changes done on top of initial SOC data files.
- The IO resource information like dma request lines, irq number and
ocp address space can be populated via dt blob. So such data is stripped
from OMAP5 SOC hwmod data file.

- SDMA IO resource information is still kept since dmaengine work
is till ongoing. Once the legacy dma platform driver becomes obsolete,
SDMA io space information can be removed.

- The devices like dss, aess, usb which are missing the device tree bindings,
hwmod data is not added since OMAP5 is DT only build. When such devices add
the dt bindings, respective hwmod data can be added along with it.

With above update, we now need about ~2000 loc vs ~6000 loc with previous
version of the patch for OMAP5 hwmod data file. Ofcourse with addition of
few more drivers it can go upto ~2400 loc which is still better than the
earlier version.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.h           |    1 +
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2151 ++++++++++++++++++++++++++++
 2 files changed, 2152 insertions(+)
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_54xx_data.c

diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f5..aab33fd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 0000000..a538692
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2151 @@
+/*
+ * Hardware modules present on the OMAP54xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "prm54xx.h"
+#include "prm-regbits-54xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all OMAP5 interrupts external to MPUSS */
+#define OMAP54XX_IRQ_GIC_START	32
+
+/* Base offset for all OMAP5 dma requests */
+#define OMAP54XX_DMA_REQ_START	1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
+	.name	= "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod omap54xx_dmm_hwmod = {
+	.name		= "dmm",
+	.class		= &omap54xx_dmm_hwmod_class,
+	.clkdm_name	= "emif_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
+	.name	= "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod omap54xx_l3_instr_hwmod = {
+	.name		= "l3_instr",
+	.class		= &omap54xx_l3_hwmod_class,
+	.clkdm_name	= "l3instr_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/* l3_main_1 */
+static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
+	.name		= "l3_main_1",
+	.class		= &omap54xx_l3_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/* l3_main_2 */
+static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
+	.name		= "l3_main_2",
+	.class		= &omap54xx_l3_hwmod_class,
+	.clkdm_name	= "l3main2_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/* l3_main_3 */
+static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
+	.name		= "l3_main_3",
+	.class		= &omap54xx_l3_hwmod_class,
+	.clkdm_name	= "l3instr_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
+	.name	= "l4",
+};
+
+/* l4_abe */
+static struct omap_hwmod omap54xx_l4_abe_hwmod = {
+	.name		= "l4_abe",
+	.class		= &omap54xx_l4_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
+			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+		},
+	},
+};
+
+/* l4_cfg */
+static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
+	.name		= "l4_cfg",
+	.class		= &omap54xx_l4_hwmod_class,
+	.clkdm_name	= "l4cfg_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/* l4_per */
+static struct omap_hwmod omap54xx_l4_per_hwmod = {
+	.name		= "l4_per",
+	.class		= &omap54xx_l4_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/* l4_wkup */
+static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
+	.name		= "l4_wkup",
+	.class		= &omap54xx_l4_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
+	.name	= "mpu_bus",
+};
+
+/* mpu_private */
+static struct omap_hwmod omap54xx_mpu_private_hwmod = {
+	.name		= "mpu_private",
+	.class		= &omap54xx_mpu_bus_hwmod_class,
+	.clkdm_name	= "mpu_clkdm",
+	.prcm = {
+		.omap4 = {
+			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+		},
+	},
+};
+
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
+	.name	= "counter",
+	.sysc	= &omap54xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod omap54xx_counter_32k_hwmod = {
+	.name		= "counter_32k",
+	.class		= &omap54xx_counter_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.main_clk	= "wkupaon_iclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x002c,
+	.syss_offs	= 0x0028,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
+	.name	= "dma",
+	.sysc	= &omap54xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+	.lch_count	= 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
+	{ .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
+	{ .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
+	{ .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
+	{ .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap54xx_dma_system_hwmod = {
+	.name		= "dma_system",
+	.class		= &omap54xx_dma_hwmod_class,
+	.clkdm_name	= "dma_clkdm",
+	.mpu_irqs	= omap54xx_dma_system_irqs,
+	.main_clk	= "l3_iclk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+		},
+	},
+	.dev_attr	= &dma_dev_attr,
+};
+
+/*
+ * 'dmic' class
+ * digital microphone controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
+	.name	= "dmic",
+	.sysc	= &omap54xx_dmic_sysc,
+};
+
+/* dmic */
+static struct omap_hwmod omap54xx_dmic_hwmod = {
+	.name		= "dmic",
+	.class		= &omap54xx_dmic_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "dmic_gfclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'emif' class
+ * external memory interface no1 (wrapper)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
+	.rev_offs	= 0x0000,
+};
+
+static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
+	.name	= "emif",
+	.sysc	= &omap54xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod omap54xx_emif1_hwmod = {
+	.name		= "emif1",
+	.class		= &omap54xx_emif_hwmod_class,
+	.clkdm_name	= "emif_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.main_clk	= "dpll_core_h11x2_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/* emif2 */
+static struct omap_hwmod omap54xx_emif2_hwmod = {
+	.name		= "emif2",
+	.class		= &omap54xx_emif_hwmod_class,
+	.clkdm_name	= "emif_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.main_clk	= "dpll_core_h11x2_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0114,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
+	.name	= "gpio",
+	.sysc	= &omap54xx_gpio_sysc,
+	.rev	= 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+	.bank_width	= 32,
+	.dbck_flag	= true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio1_hwmod = {
+	.name		= "gpio1",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.main_clk	= "wkupaon_iclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio2_hwmod = {
+	.name		= "gpio2",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio3_hwmod = {
+	.name		= "gpio3",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio3_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio4_hwmod = {
+	.name		= "gpio4",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio4_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio5_hwmod = {
+	.name		= "gpio5",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio5_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio6_hwmod = {
+	.name		= "gpio6",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio6_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio7_hwmod = {
+	.name		= "gpio7",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio7_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio7_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio8_hwmod = {
+	.name		= "gpio8",
+	.class		= &omap54xx_gpio_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.main_clk	= "l4_root_clk_div",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= gpio8_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio8_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+};
+
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0090,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.clockact	= CLOCKACT_TEST_ICLK,
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
+	.name	= "i2c",
+	.sysc	= &omap54xx_i2c_sysc,
+	.reset	= &omap_i2c_reset,
+	.rev	= OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+	.flags	= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap54xx_i2c1_hwmod = {
+	.name		= "i2c1",
+	.class		= &omap54xx_i2c_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+	.main_clk	= "func_96m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod omap54xx_i2c2_hwmod = {
+	.name		= "i2c2",
+	.class		= &omap54xx_i2c_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+	.main_clk	= "func_96m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod omap54xx_i2c3_hwmod = {
+	.name		= "i2c3",
+	.class		= &omap54xx_i2c_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+	.main_clk	= "func_96m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod omap54xx_i2c4_hwmod = {
+	.name		= "i2c4",
+	.class		= &omap54xx_i2c_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+	.main_clk	= "func_96m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod omap54xx_i2c5_hwmod = {
+	.name		= "i2c5",
+	.class		= &omap54xx_i2c_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+	.main_clk	= "func_96m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &i2c_dev_attr,
+};
+
+/*
+ * 'kbd' class
+ * keyboard controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
+	.name	= "kbd",
+	.sysc	= &omap54xx_kbd_sysc,
+};
+
+/* kbd */
+static struct omap_hwmod omap54xx_kbd_hwmod = {
+	.name		= "kbd",
+	.class		= &omap54xx_kbd_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.main_clk	= "sys_32k_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
+	.sysc_offs	= 0x008c,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
+	.name	= "mcbsp",
+	.sysc	= &omap54xx_mcbsp_sysc,
+	.rev	= MCBSP_CONFIG_TYPE4,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
+	.name		= "mcbsp1",
+	.class		= &omap54xx_mcbsp_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "mcbsp1_gfclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcbsp1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp1_opt_clks),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
+	.name		= "mcbsp2",
+	.class		= &omap54xx_mcbsp_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "mcbsp2_gfclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcbsp2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp2_opt_clks),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
+	.name		= "mcbsp3",
+	.class		= &omap54xx_mcbsp_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "mcbsp3_gfclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcbsp3_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp3_opt_clks),
+};
+
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
+	.name	= "mcpdm",
+	.sysc	= &omap54xx_mcpdm_sysc,
+};
+
+/* mcpdm */
+static struct omap_hwmod omap54xx_mcpdm_hwmod = {
+	.name		= "mcpdm",
+	.class		= &omap54xx_mcpdm_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	/*
+	 * It's suspected that the McPDM requires an off-chip main
+	 * functional clock, controlled via I2C.  This IP block is
+	 * currently reset very early during boot, before I2C is
+	 * available, so it doesn't seem that we have any choice in
+	 * the kernel other than to avoid resetting it.  XXX This is
+	 * really a hardware issue workaround: every IP block should
+	 * be able to source its main functional clock from either
+	 * on-chip or off-chip sources.  McPDM seems to be the only
+	 * current exception.
+	 */
+
+	.flags		= HWMOD_EXT_OPT_MAIN_CLK,
+	.main_clk	= "pad_clks_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
+	.name	= "mcspi",
+	.sysc	= &omap54xx_mcspi_sysc,
+	.rev	= OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+	.num_chipselect	= 4,
+};
+
+static struct omap_hwmod omap54xx_mcspi1_hwmod = {
+	.name		= "mcspi1",
+	.class		= &omap54xx_mcspi_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+	.num_chipselect	= 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi2_hwmod = {
+	.name		= "mcspi2",
+	.class		= &omap54xx_mcspi_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+	.num_chipselect	= 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi3_hwmod = {
+	.name		= "mcspi3",
+	.class		= &omap54xx_mcspi_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+	.num_chipselect	= 1,
+};
+
+static struct omap_hwmod omap54xx_mcspi4_hwmod = {
+	.name		= "mcspi4",
+	.class		= &omap54xx_mcspi_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
+	.name	= "mmc",
+	.sysc	= &omap54xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+	{ .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap54xx_mmc1_hwmod = {
+	.name		= "mmc1",
+	.class		= &omap54xx_mmc_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.main_clk	= "mmc1_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mmc1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mmc1_opt_clks),
+	.dev_attr	= &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod omap54xx_mmc2_hwmod = {
+	.name		= "mmc2",
+	.class		= &omap54xx_mmc_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.main_clk	= "mmc2_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* mmc3 */
+static struct omap_hwmod omap54xx_mmc3_hwmod = {
+	.name		= "mmc3",
+	.class		= &omap54xx_mmc_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* mmc4 */
+static struct omap_hwmod omap54xx_mmc4_hwmod = {
+	.name		= "mmc4",
+	.class		= &omap54xx_mmc_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* mmc5 */
+static struct omap_hwmod omap54xx_mmc5_hwmod = {
+	.name		= "mmc5",
+	.class		= &omap54xx_mmc_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_96m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
+	.name	= "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod omap54xx_mpu_hwmod = {
+	.name		= "mpu",
+	.class		= &omap54xx_mpu_hwmod_class,
+	.clkdm_name	= "mpu_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.main_clk	= "dpll_mpu_m2_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+	.clockact	= CLOCKACT_TEST_ICLK,
+};
+
+static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
+	.name	= "timer",
+	.sysc	= &omap54xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
+	.name	= "timer",
+	.sysc	= &omap54xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap54xx_timer1_hwmod = {
+	.name		= "timer1",
+	.class		= &omap54xx_timer_1ms_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.main_clk	= "timer1_gfclk_mux",
+	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer2 */
+static struct omap_hwmod omap54xx_timer2_hwmod = {
+	.name		= "timer2",
+	.class		= &omap54xx_timer_1ms_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "timer2_gfclk_mux",
+	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer3 */
+static struct omap_hwmod omap54xx_timer3_hwmod = {
+	.name		= "timer3",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "timer3_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer4 */
+static struct omap_hwmod omap54xx_timer4_hwmod = {
+	.name		= "timer4",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "timer4_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer5 */
+static struct omap_hwmod omap54xx_timer5_hwmod = {
+	.name		= "timer5",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "timer5_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer6 */
+static struct omap_hwmod omap54xx_timer6_hwmod = {
+	.name		= "timer6",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "timer6_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer7 */
+static struct omap_hwmod omap54xx_timer7_hwmod = {
+	.name		= "timer7",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "timer7_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer8 */
+static struct omap_hwmod omap54xx_timer8_hwmod = {
+	.name		= "timer8",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.main_clk	= "timer8_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer9 */
+static struct omap_hwmod omap54xx_timer9_hwmod = {
+	.name		= "timer9",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "timer9_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer10 */
+static struct omap_hwmod omap54xx_timer10_hwmod = {
+	.name		= "timer10",
+	.class		= &omap54xx_timer_1ms_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "timer10_gfclk_mux",
+	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* timer11 */
+static struct omap_hwmod omap54xx_timer11_hwmod = {
+	.name		= "timer11",
+	.class		= &omap54xx_timer_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "timer11_gfclk_mux",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
+	.rev_offs	= 0x0050,
+	.sysc_offs	= 0x0054,
+	.syss_offs	= 0x0058,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
+	.name	= "uart",
+	.sysc	= &omap54xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap54xx_uart1_hwmod = {
+	.name		= "uart1",
+	.class		= &omap54xx_uart_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* uart2 */
+static struct omap_hwmod omap54xx_uart2_hwmod = {
+	.name		= "uart2",
+	.class		= &omap54xx_uart_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* uart3 */
+static struct omap_hwmod omap54xx_uart3_hwmod = {
+	.name		= "uart3",
+	.class		= &omap54xx_uart_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* uart4 */
+static struct omap_hwmod omap54xx_uart4_hwmod = {
+	.name		= "uart4",
+	.class		= &omap54xx_uart_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* uart5 */
+static struct omap_hwmod omap54xx_uart5_hwmod = {
+	.name		= "uart5",
+	.class		= &omap54xx_uart_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* uart6 */
+static struct omap_hwmod omap54xx_uart6_hwmod = {
+	.name		= "uart6",
+	.class		= &omap54xx_uart_hwmod_class,
+	.clkdm_name	= "l4per_clkdm",
+	.main_clk	= "func_48m_fclk",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'usb_otg_ss' class
+ * 2.0 super speed (usb_otg_ss) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
+	.name	= "usb_otg_ss",
+	.sysc	= &omap54xx_usb_otg_ss_sysc,
+};
+
+/* usb_otg_ss */
+static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
+	{ .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
+};
+
+static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
+	.name		= "usb_otg_ss",
+	.class		= &omap54xx_usb_otg_ss_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.main_clk	= "dpll_core_h13x2_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= usb_otg_ss_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_ss_opt_clks),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
+	.name		= "wd_timer",
+	.sysc		= &omap54xx_wd_timer_sysc,
+	.pre_shutdown	= &omap2_wd_timer_disable,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
+	.name		= "wd_timer2",
+	.class		= &omap54xx_wd_timer_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.main_clk	= "sys_32k_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
+	.master		= &omap54xx_l3_main_1_hwmod,
+	.slave		= &omap54xx_dmm_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
+	.master		= &omap54xx_l3_main_3_hwmod,
+	.slave		= &omap54xx_l3_instr_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
+	.master		= &omap54xx_l3_main_2_hwmod,
+	.slave		= &omap54xx_l3_main_1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_l3_main_1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
+	.master		= &omap54xx_mpu_hwmod,
+	.slave		= &omap54xx_l3_main_1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
+	.master		= &omap54xx_l3_main_1_hwmod,
+	.slave		= &omap54xx_l3_main_2_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_l3_main_2_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
+	.master		= &omap54xx_l3_main_1_hwmod,
+	.slave		= &omap54xx_l3_main_3_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
+	.master		= &omap54xx_l3_main_2_hwmod,
+	.slave		= &omap54xx_l3_main_3_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_l3_main_3_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
+	.master		= &omap54xx_l3_main_1_hwmod,
+	.slave		= &omap54xx_l4_abe_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
+	.master		= &omap54xx_mpu_hwmod,
+	.slave		= &omap54xx_l4_abe_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
+	.master		= &omap54xx_l3_main_1_hwmod,
+	.slave		= &omap54xx_l4_cfg_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
+	.master		= &omap54xx_l3_main_2_hwmod,
+	.slave		= &omap54xx_l4_per_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
+	.master		= &omap54xx_l3_main_1_hwmod,
+	.slave		= &omap54xx_l4_wkup_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
+	.master		= &omap54xx_mpu_hwmod,
+	.slave		= &omap54xx_mpu_private_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
+	.master		= &omap54xx_l4_wkup_hwmod,
+	.slave		= &omap54xx_counter_32k_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
+	{
+		.pa_start	= 0x4a056000,
+		.pa_end		= 0x4a056fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_dma_system_hwmod,
+	.clk		= "l4_root_clk_div",
+	.addr		= omap54xx_dma_system_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_dmic_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
+	.master		= &omap54xx_mpu_hwmod,
+	.slave		= &omap54xx_emif1_hwmod,
+	.clk		= "dpll_core_h11x2_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
+	.master		= &omap54xx_mpu_hwmod,
+	.slave		= &omap54xx_emif2_hwmod,
+	.clk		= "dpll_core_h11x2_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
+	.master		= &omap54xx_l4_wkup_hwmod,
+	.slave		= &omap54xx_gpio1_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio6_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio7_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_gpio8_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_i2c1_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_i2c2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_i2c3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_i2c4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_i2c5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
+	.master		= &omap54xx_l4_wkup_hwmod,
+	.slave		= &omap54xx_kbd_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_mcbsp1_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_mcbsp2_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_mcbsp3_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_mcpdm_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mcspi1_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mcspi2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mcspi3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mcspi4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mmc1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mmc2_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mmc3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mmc4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_mmc5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_mpu_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
+	.master		= &omap54xx_l4_wkup_hwmod,
+	.slave		= &omap54xx_timer1_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_timer2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_timer3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_timer4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_timer5_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_timer6_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_timer7_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
+	.master		= &omap54xx_l4_abe_hwmod,
+	.slave		= &omap54xx_timer8_hwmod,
+	.clk		= "abe_iclk",
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_timer9_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_timer10_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_timer11_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_uart1_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_uart2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_uart3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_uart4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_uart5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
+	.master		= &omap54xx_l4_per_hwmod,
+	.slave		= &omap54xx_uart6_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> usb_otg_ss */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_usb_otg_ss_hwmod,
+	.clk		= "dpll_core_h13x2_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
+	.master		= &omap54xx_l4_wkup_hwmod,
+	.slave		= &omap54xx_wd_timer2_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
+	&omap54xx_l3_main_1__dmm,
+	&omap54xx_l3_main_3__l3_instr,
+	&omap54xx_l3_main_2__l3_main_1,
+	&omap54xx_l4_cfg__l3_main_1,
+	&omap54xx_mpu__l3_main_1,
+	&omap54xx_l3_main_1__l3_main_2,
+	&omap54xx_l4_cfg__l3_main_2,
+	&omap54xx_l3_main_1__l3_main_3,
+	&omap54xx_l3_main_2__l3_main_3,
+	&omap54xx_l4_cfg__l3_main_3,
+	&omap54xx_l3_main_1__l4_abe,
+	&omap54xx_mpu__l4_abe,
+	&omap54xx_l3_main_1__l4_cfg,
+	&omap54xx_l3_main_2__l4_per,
+	&omap54xx_l3_main_1__l4_wkup,
+	&omap54xx_mpu__mpu_private,
+	&omap54xx_l4_wkup__counter_32k,
+	&omap54xx_l4_cfg__dma_system,
+	&omap54xx_l4_abe__dmic,
+	&omap54xx_mpu__emif1,
+	&omap54xx_mpu__emif2,
+	&omap54xx_l4_wkup__gpio1,
+	&omap54xx_l4_per__gpio2,
+	&omap54xx_l4_per__gpio3,
+	&omap54xx_l4_per__gpio4,
+	&omap54xx_l4_per__gpio5,
+	&omap54xx_l4_per__gpio6,
+	&omap54xx_l4_per__gpio7,
+	&omap54xx_l4_per__gpio8,
+	&omap54xx_l4_per__i2c1,
+	&omap54xx_l4_per__i2c2,
+	&omap54xx_l4_per__i2c3,
+	&omap54xx_l4_per__i2c4,
+	&omap54xx_l4_per__i2c5,
+	&omap54xx_l4_wkup__kbd,
+	&omap54xx_l4_abe__mcbsp1,
+	&omap54xx_l4_abe__mcbsp2,
+	&omap54xx_l4_abe__mcbsp3,
+	&omap54xx_l4_abe__mcpdm,
+	&omap54xx_l4_per__mcspi1,
+	&omap54xx_l4_per__mcspi2,
+	&omap54xx_l4_per__mcspi3,
+	&omap54xx_l4_per__mcspi4,
+	&omap54xx_l4_per__mmc1,
+	&omap54xx_l4_per__mmc2,
+	&omap54xx_l4_per__mmc3,
+	&omap54xx_l4_per__mmc4,
+	&omap54xx_l4_per__mmc5,
+	&omap54xx_l4_cfg__mpu,
+	&omap54xx_l4_wkup__timer1,
+	&omap54xx_l4_per__timer2,
+	&omap54xx_l4_per__timer3,
+	&omap54xx_l4_per__timer4,
+	&omap54xx_l4_abe__timer5,
+	&omap54xx_l4_abe__timer6,
+	&omap54xx_l4_abe__timer7,
+	&omap54xx_l4_abe__timer8,
+	&omap54xx_l4_per__timer9,
+	&omap54xx_l4_per__timer10,
+	&omap54xx_l4_per__timer11,
+	&omap54xx_l4_per__uart1,
+	&omap54xx_l4_per__uart2,
+	&omap54xx_l4_per__uart3,
+	&omap54xx_l4_per__uart4,
+	&omap54xx_l4_per__uart5,
+	&omap54xx_l4_per__uart6,
+	&omap54xx_l4_cfg__usb_otg_ss,
+	&omap54xx_l4_wkup__wd_timer2,
+	NULL,
+};
+
+int __init omap54xx_hwmod_init(void)
+{
+	omap_hwmod_init();
+	return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
+}
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:13 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:13 -0400
Subject: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-14-git-send-email-santosh.shilimkar@ti.com>

From: Vaibhav Hiremath <hvaibhav at ti.com>

AM33XX only supports DT boot mode and with addition of
extracting module resources like, irq, dma and address space
from DT block, so now we can remove duplicate information from
hwmod data file.

This patch cleanups-up/deletes,

     - All references to "omap_hwmod_irq_info" data.
     - All references to "omap_hwmod_dma_info" data.
     - References to "omap_hwmod_addr_space" of the modules
       for which DT node is available with required address
       space information.
     - For the modules where "sysc" field is not applicable,
       we don't need module address space, so remove them as well.
     - The hwmod like firewall etc which are not useful are also
       deleted.

This cleanup gets us around ~1100 LOC of negative diff.
Patch is boot tested on AM335x-EVM along with below modules -
	- Matrix-keypad
	- Volume up/down keys
	- Ethernet
	- RTC
	- WDT

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Sricharan R <r.sricharan at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1067 ----------------------------
 1 file changed, 1067 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc..3c7675a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -35,29 +35,6 @@
  */
 
 /*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
-	.name		= "emif_fw",
-};
-
-/* emif_fw */
-static struct omap_hwmod am33xx_emif_fw_hwmod = {
-	.name		= "emif_fw",
-	.class		= &am33xx_emif_fw_hwmod_class,
-	.clkdm_name	= "l4fw_clkdm",
-	.main_clk	= "l4fw_gclk",
-	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
-};
-
-/*
  * 'emif' class
  * instance(s): emif
  */
@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
 	.sysc		= &am33xx_emif_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
-	{ .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 /* emif */
 static struct omap_hwmod am33xx_emif_hwmod = {
 	.name		= "emif",
 	.class		= &am33xx_emif_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.mpu_irqs	= am33xx_emif_irqs,
 	.main_clk	= "dpll_ddr_m2_div2_ck",
 	.prcm		= {
 		.omap4	= {
@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
 	.name		= "l3",
 };
 
-/* l3_main (l3_fast) */
-static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
-	{ .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
-	{ .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_l3_main_hwmod = {
 	.name		= "l3_main",
 	.class		= &am33xx_l3_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.mpu_irqs	= am33xx_l3_main_irqs,
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
 	},
 };
 
-/* l4_fw */
-static struct omap_hwmod am33xx_l4_fw_hwmod = {
-	.name		= "l4_fw",
-	.class		= &am33xx_l4_hwmod_class,
-	.clkdm_name	= "l4fw_clkdm",
-	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
-};
-
 /*
  * 'mpu' class
  */
@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 	.name	= "mpu",
 };
 
-/* mpu */
-static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
-	{ .name = "emuint", .irq = 0 + OMAP_INTC_START, },
-	{ .name = "commtx", .irq = 1 + OMAP_INTC_START, },
-	{ .name = "commrx", .irq = 2 + OMAP_INTC_START, },
-	{ .name = "bench", .irq = 3 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_mpu_hwmod = {
 	.name		= "mpu",
 	.class		= &am33xx_mpu_hwmod_class,
 	.clkdm_name	= "mpu_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.mpu_irqs	= am33xx_mpu_irqs,
 	.main_clk	= "dpll_mpu_m2_ck",
 	.prcm		= {
 		.omap4	= {
@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
 	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 };
 
-static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
-	{ .name = "txev", .irq = 78 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 /* wkup_m3  */
 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 	.name		= "wkup_m3",
@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 	.clkdm_name	= "l4_wkup_aon_clkdm",
 	/* Keep hardreset asserted */
 	.flags		= HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
-	.mpu_irqs	= am33xx_wkup_m3_irqs,
 	.main_clk	= "dpll_core_m4_div2_ck",
 	.prcm		= {
 		.omap4	= {
@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 	{ .name = "pruss", .rst_shift = 1 },
 };
 
-static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
-	{ .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
-	{ .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
-	{ .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
-	{ .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
-	{ .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
-	{ .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
-	{ .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
-	{ .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 /* pru-icss */
 /* Pseudo hwmod for reset control purpose only */
 static struct omap_hwmod am33xx_pruss_hwmod = {
 	.name		= "pruss",
 	.class		= &am33xx_pruss_hwmod_class,
 	.clkdm_name	= "pruss_ocp_clkdm",
-	.mpu_irqs	= am33xx_pruss_irqs,
 	.main_clk	= "pruss_ocp_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 	{ .name = "gfx", .rst_shift = 0 },
 };
 
-static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
-	{ .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_gfx_hwmod = {
 	.name		= "gfx",
 	.class		= &am33xx_gfx_hwmod_class,
 	.clkdm_name	= "gfx_l3_clkdm",
-	.mpu_irqs	= am33xx_gfx_irqs,
 	.main_clk	= "gfx_fck_div_ck",
 	.prcm		= {
 		.omap4	= {
@@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 	.sysc		= &am33xx_adc_tsc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
-	{ .irq = 16 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 	.name		= "adc_tsc",
 	.class		= &am33xx_adc_tsc_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= am33xx_adc_tsc_irqs,
 	.main_clk	= "adc_tsc_fck",
 	.prcm		= {
 		.omap4	= {
@@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 	.sysc		= &am33xx_aes0_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-	{ .irq = 103 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 6, },
-	{ .name = "rx", .dma_req = 5, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_aes0_hwmod = {
 	.name		= "aes",
 	.class		= &am33xx_aes0_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
-	.mpu_irqs	= am33xx_aes0_irqs,
-	.sdma_reqs	= am33xx_aes0_edma_reqs,
 	.main_clk	= "aes0_fck",
 	.prcm		= {
 		.omap4	= {
@@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 	.sysc		= &am33xx_sha0_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-	{ .irq = 109 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
-	{ .name = "rx", .dma_req = 36, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_sha0_hwmod = {
 	.name		= "sham",
 	.class		= &am33xx_sha0_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
-	.mpu_irqs	= am33xx_sha0_irqs,
-	.sdma_reqs	= am33xx_sha0_edma_reqs,
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 };
 
 /* smartreflex0 */
-static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
-	{ .irq = 120 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 	.name		= "smartreflex0",
 	.class		= &am33xx_smartreflex_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= am33xx_smartreflex0_irqs,
 	.main_clk	= "smartreflex0_fck",
 	.prcm		= {
 		.omap4	= {
@@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 };
 
 /* smartreflex1 */
-static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
-	{ .irq = 121 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
 	.name		= "smartreflex1",
 	.class		= &am33xx_smartreflex_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= am33xx_smartreflex1_irqs,
 	.main_clk	= "smartreflex1_fck",
 	.prcm		= {
 		.omap4	= {
@@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
 	.name		= "control",
 };
 
-static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
-	{ .irq = 8 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_control_hwmod = {
 	.name		= "control",
 	.class		= &am33xx_control_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.mpu_irqs	= am33xx_control_irqs,
 	.main_clk	= "dpll_core_m4_div2_ck",
 	.prcm		= {
 		.omap4	= {
@@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 	.sysc		= &am33xx_cpgmac_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
-	{ .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
-	{ .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
-	{ .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
-	{ .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 	.name		= "cpgmac0",
 	.class		= &am33xx_cpgmac0_hwmod_class,
 	.clkdm_name	= "cpsw_125mhz_clkdm",
 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-	.mpu_irqs	= am33xx_cpgmac0_irqs,
 	.main_clk	= "cpsw_125mhz_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 };
 
 /* dcan0 */
-static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
-	{ .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
-	{ .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_dcan0_hwmod = {
 	.name		= "d_can0",
 	.class		= &am33xx_dcan_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_dcan0_irqs,
 	.main_clk	= "dcan0_fck",
 	.prcm		= {
 		.omap4	= {
@@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
 };
 
 /* dcan1 */
-static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
-	{ .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
-	{ .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
 static struct omap_hwmod am33xx_dcan1_hwmod = {
 	.name		= "d_can1",
 	.class		= &am33xx_dcan_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_dcan1_irqs,
 	.main_clk	= "dcan1_fck",
 	.prcm		= {
 		.omap4	= {
@@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 	.sysc		= &am33xx_elm_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
-	{ .irq = 4 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_elm_hwmod = {
 	.name		= "elm",
 	.class		= &am33xx_elm_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_elm_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
 };
 
 /* ecap0 */
-static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
-	{ .irq = 31 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ecap0_hwmod = {
 	.name		= "ecap0",
 	.class		= &am33xx_ecap_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ecap0_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
 /* eqep0 */
-static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
-	{ .irq = 79 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_eqep0_hwmod = {
 	.name		= "eqep0",
 	.class		= &am33xx_eqep_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_eqep0_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
 /* ehrpwm0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
-	{ .name = "int", .irq = 86 + OMAP_INTC_START, },
-	{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 	.name		= "ehrpwm0",
 	.class		= &am33xx_ehrpwm_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ehrpwm0_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
@@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
 };
 
 /* ecap1 */
-static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
-	{ .irq = 47 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ecap1_hwmod = {
 	.name		= "ecap1",
 	.class		= &am33xx_ecap_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ecap1_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
 /* eqep1 */
-static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
-	{ .irq = 88 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_eqep1_hwmod = {
 	.name		= "eqep1",
 	.class		= &am33xx_eqep_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_eqep1_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
 /* ehrpwm1 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
-	{ .name = "int", .irq = 87 + OMAP_INTC_START, },
-	{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 	.name		= "ehrpwm1",
 	.class		= &am33xx_ehrpwm_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ehrpwm1_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
@@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
 };
 
 /* ecap2 */
-static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
-	{ .irq = 61 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ecap2_hwmod = {
 	.name		= "ecap2",
 	.class		= &am33xx_ecap_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ecap2_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
 /* eqep2 */
-static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
-	{ .irq = 89 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_eqep2_hwmod = {
 	.name		= "eqep2",
 	.class		= &am33xx_eqep_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_eqep2_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
 /* ehrpwm2 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
-	{ .name = "int", .irq = 39 + OMAP_INTC_START, },
-	{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 	.name		= "ehrpwm2",
 	.class		= &am33xx_ehrpwm_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ehrpwm2_irqs,
 	.main_clk	= "l4ls_gclk",
 };
 
@@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio0_dbclk" },
 };
 
-static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
-	{ .irq = 96 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_gpio0_hwmod = {
 	.name		= "gpio1",
 	.class		= &am33xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= am33xx_gpio0_irqs,
 	.main_clk	= "dpll_core_m4_div2_ck",
 	.prcm		= {
 		.omap4	= {
@@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
 };
 
 /* gpio1 */
-static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
-	{ .irq = 98 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
 	.class		= &am33xx_gpio_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= am33xx_gpio1_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
-	{ .irq = 32 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
 	.class		= &am33xx_gpio_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= am33xx_gpio2_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
-	{ .irq = 62 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
 	.class		= &am33xx_gpio_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= am33xx_gpio3_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 	.sysc		= &gpmc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
-	{ .irq = 100 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_gpmc_hwmod = {
 	.name		= "gpmc",
 	.class		= &am33xx_gpmc_hwmod_class,
 	.clkdm_name	= "l3s_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.mpu_irqs	= am33xx_gpmc_irqs,
 	.main_clk	= "l3s_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 
 /* i2c1 */
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-	{ .irq = 70 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 0, },
-	{ .name = "rx", .dma_req = 0, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_i2c1_hwmod = {
 	.name		= "i2c1",
 	.class		= &i2c_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= i2c1_mpu_irqs,
-	.sdma_reqs	= i2c1_edma_reqs,
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 	.main_clk	= "dpll_per_m2_div4_wkupdm_ck",
 	.prcm		= {
@@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
 };
 
 /* i2c1 */
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-	{ .irq = 71 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 0, },
-	{ .name = "rx", .dma_req = 0, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_i2c2_hwmod = {
 	.name		= "i2c2",
 	.class		= &i2c_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= i2c2_mpu_irqs,
-	.sdma_reqs	= i2c2_edma_reqs,
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
@@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
 };
 
 /* i2c3 */
-static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 0, },
-	{ .name = "rx", .dma_req = 0, },
-	{ .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-	{ .irq = 30 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_i2c3_hwmod = {
 	.name		= "i2c3",
 	.class		= &i2c_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= i2c3_mpu_irqs,
-	.sdma_reqs	= i2c3_edma_reqs,
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
@@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
 	.sysc		= &lcdc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
-	{ .irq = 36 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_lcdc_hwmod = {
 	.name		= "lcdc",
 	.class		= &am33xx_lcdc_hwmod_class,
 	.clkdm_name	= "lcdc_clkdm",
-	.mpu_irqs	= am33xx_lcdc_irqs,
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.main_clk	= "lcd_gclk",
 	.prcm		= {
@@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 	.sysc	= &am33xx_mailbox_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
-	{ .irq = 77 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_mailbox_hwmod = {
 	.name		= "mailbox",
 	.class		= &am33xx_mailbox_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_mailbox_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm = {
 		.omap4 = {
@@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 };
 
 /* mcasp0 */
-static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
-	{ .name = "ax", .irq = 80 + OMAP_INTC_START, },
-	{ .name = "ar", .irq = 81 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 8, },
-	{ .name = "rx", .dma_req = 9, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_mcasp0_hwmod = {
 	.name		= "mcasp0",
 	.class		= &am33xx_mcasp_hwmod_class,
 	.clkdm_name	= "l3s_clkdm",
-	.mpu_irqs	= am33xx_mcasp0_irqs,
-	.sdma_reqs	= am33xx_mcasp0_edma_reqs,
 	.main_clk	= "mcasp0_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
 };
 
 /* mcasp1 */
-static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
-	{ .name = "ax", .irq = 82 + OMAP_INTC_START, },
-	{ .name = "ar", .irq = 83 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 10, },
-	{ .name = "rx", .dma_req = 11, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_mcasp1_hwmod = {
 	.name		= "mcasp1",
 	.class		= &am33xx_mcasp_hwmod_class,
 	.clkdm_name	= "l3s_clkdm",
-	.mpu_irqs	= am33xx_mcasp1_irqs,
-	.sdma_reqs	= am33xx_mcasp1_edma_reqs,
 	.main_clk	= "mcasp1_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 };
 
 /* mmc0 */
-static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
-	{ .irq = 64 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 24, },
-	{ .name = "rx", .dma_req = 25, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
 	.name		= "mmc1",
 	.class		= &am33xx_mmc_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_mmc0_irqs,
-	.sdma_reqs	= am33xx_mmc0_edma_reqs,
 	.main_clk	= "mmc_clk",
 	.prcm		= {
 		.omap4	= {
@@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
 };
 
 /* mmc1 */
-static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
-	{ .irq = 28 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 2, },
-	{ .name = "rx", .dma_req = 3, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
 	.name		= "mmc2",
 	.class		= &am33xx_mmc_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_mmc1_irqs,
-	.sdma_reqs	= am33xx_mmc1_edma_reqs,
 	.main_clk	= "mmc_clk",
 	.prcm		= {
 		.omap4	= {
@@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
 };
 
 /* mmc2 */
-static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
-	{ .irq = 29 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
-	{ .name = "tx", .dma_req = 64, },
-	{ .name = "rx", .dma_req = 65, },
-	{ .dma_req = -1 }
-};
-
 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
 	.name		= "mmc3",
 	.class		= &am33xx_mmc_hwmod_class,
 	.clkdm_name	= "l3s_clkdm",
-	.mpu_irqs	= am33xx_mmc2_irqs,
-	.sdma_reqs	= am33xx_mmc2_edma_reqs,
 	.main_clk	= "mmc_clk",
 	.prcm		= {
 		.omap4	= {
@@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 	.sysc		= &am33xx_rtc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
-	{ .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
-	{ .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_rtc_hwmod = {
 	.name		= "rtc",
 	.class		= &am33xx_rtc_hwmod_class,
 	.clkdm_name	= "l4_rtc_clkdm",
-	.mpu_irqs	= am33xx_rtc_irqs,
 	.main_clk	= "clk_32768_ck",
 	.prcm		= {
 		.omap4	= {
@@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
 };
 
 /* spi0 */
-static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
-	{ .irq = 65 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
-	{ .name = "rx0", .dma_req = 17 },
-	{ .name = "tx0", .dma_req = 16 },
-	{ .name = "rx1", .dma_req = 19 },
-	{ .name = "tx1", .dma_req = 18 },
-	{ .dma_req = -1 }
-};
-
 static struct omap2_mcspi_dev_attr mcspi_attrib = {
 	.num_chipselect	= 2,
 };
@@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
 	.name		= "spi0",
 	.class		= &am33xx_spi_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_spi0_irqs,
-	.sdma_reqs	= am33xx_mcspi0_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
 };
 
 /* spi1 */
-static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
-	{ .irq = 125 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
-	{ .name = "rx0", .dma_req = 43 },
-	{ .name = "tx0", .dma_req = 42 },
-	{ .name = "rx1", .dma_req = 45 },
-	{ .name = "tx1", .dma_req = 44 },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_spi1_hwmod = {
 	.name		= "spi1",
 	.class		= &am33xx_spi_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_spi1_irqs,
-	.sdma_reqs	= am33xx_mcspi1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 	.sysc		= &am33xx_timer1ms_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
-	{ .irq = 67 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer1_hwmod = {
 	.name		= "timer1",
 	.class		= &am33xx_timer1ms_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= am33xx_timer1_irqs,
 	.main_clk	= "timer1_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
-	{ .irq = 68 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer2_hwmod = {
 	.name		= "timer2",
 	.class		= &am33xx_timer_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_timer2_irqs,
 	.main_clk	= "timer2_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
-	{ .irq = 69 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer3_hwmod = {
 	.name		= "timer3",
 	.class		= &am33xx_timer_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_timer3_irqs,
 	.main_clk	= "timer3_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
-	{ .irq = 92 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer4_hwmod = {
 	.name		= "timer4",
 	.class		= &am33xx_timer_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_timer4_irqs,
 	.main_clk	= "timer4_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
-	{ .irq = 93 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer5_hwmod = {
 	.name		= "timer5",
 	.class		= &am33xx_timer_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_timer5_irqs,
 	.main_clk	= "timer5_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
-	{ .irq = 94 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer6_hwmod = {
 	.name		= "timer6",
 	.class		= &am33xx_timer_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_timer6_irqs,
 	.main_clk	= "timer6_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
-	{ .irq = 95 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer7_hwmod = {
 	.name		= "timer7",
 	.class		= &am33xx_timer_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_timer7_irqs,
 	.main_clk	= "timer7_fck",
 	.prcm		= {
 		.omap4	= {
@@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 	.name		= "tpcc",
 };
 
-static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
-	{ .name	= "edma0", .irq = 12 + OMAP_INTC_START, },
-	{ .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
-	{ .name	= "edma0_err", .irq = 14 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tpcc_hwmod = {
 	.name		= "tpcc",
 	.class		= &am33xx_tpcc_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
-	.mpu_irqs	= am33xx_tpcc_irqs,
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 };
 
 /* tptc0 */
-static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
-	{ .irq = 112 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tptc0_hwmod = {
 	.name		= "tptc0",
 	.class		= &am33xx_tptc_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
-	.mpu_irqs	= am33xx_tptc0_irqs,
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.main_clk	= "l3_gclk",
 	.prcm		= {
@@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
 };
 
 /* tptc1 */
-static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
-	{ .irq = 113 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tptc1_hwmod = {
 	.name		= "tptc1",
 	.class		= &am33xx_tptc_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
-	.mpu_irqs	= am33xx_tptc1_irqs,
 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 	.main_clk	= "l3_gclk",
 	.prcm		= {
@@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
 };
 
 /* tptc2 */
-static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
-	{ .irq = 114 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tptc2_hwmod = {
 	.name		= "tptc2",
 	.class		= &am33xx_tptc_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
-	.mpu_irqs	= am33xx_tptc2_irqs,
 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 	.main_clk	= "l3_gclk",
 	.prcm		= {
@@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = {
 };
 
 /* uart1 */
-static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
-	{ .name = "tx",	.dma_req = 26, },
-	{ .name = "rx",	.dma_req = 27, },
-	{ .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
-	{ .irq = 72 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart1_hwmod = {
 	.name		= "uart1",
 	.class		= &uart_class,
 	.clkdm_name	= "l4_wkup_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= am33xx_uart1_irqs,
-	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_wkupdm_ck",
 	.prcm		= {
 		.omap4	= {
@@ -2007,18 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
-	{ .irq = 73 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart2_hwmod = {
 	.name		= "uart2",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= am33xx_uart2_irqs,
-	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -2029,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
 };
 
 /* uart3 */
-static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
-	{ .name = "tx",	.dma_req = 30, },
-	{ .name = "rx",	.dma_req = 31, },
-	{ .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
-	{ .irq = 74 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart3_hwmod = {
 	.name		= "uart3",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= am33xx_uart3_irqs,
-	.sdma_reqs	= uart3_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -2056,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
-	{ .irq = 44 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart4_hwmod = {
 	.name		= "uart4",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= am33xx_uart4_irqs,
-	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -2077,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
-	{ .irq = 45 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart5_hwmod = {
 	.name		= "uart5",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= am33xx_uart5_irqs,
-	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -2098,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
 	},
 };
 
-static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
-	{ .irq = 46 + OMAP_INTC_START, },
-	{ .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart6_hwmod = {
 	.name		= "uart6",
 	.class		= &uart_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= am33xx_uart6_irqs,
-	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
@@ -2173,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
 	.sysc		= &am33xx_usbhsotg_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
-	{ .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
-	{ .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
-	{ .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
-	{ .irq = -1, },
-};
-
 static struct omap_hwmod am33xx_usbss_hwmod = {
 	.name		= "usb_otg_hs",
 	.class		= &am33xx_usbotg_class,
 	.clkdm_name	= "l3s_clkdm",
-	.mpu_irqs	= am33xx_usbss_mpu_irqs,
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.main_clk	= "usbotg_fck",
 	.prcm		= {
@@ -2200,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
  * Interfaces
  */
 
-/* l4 fw -> emif fw */
-static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
-	.master		= &am33xx_l4_fw_hwmod,
-	.slave		= &am33xx_emif_fw_hwmod,
-	.clk		= "l4fw_gclk",
-	.user		= OCP_USER_MPU,
-};
-
 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
 	{
 		.pa_start	= 0x4c000000,
@@ -2265,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3 s -> l4 fw */
-static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
-	.master		= &am33xx_l3_s_hwmod,
-	.slave		= &am33xx_l4_fw_hwmod,
-	.clk		= "l3s_gclk",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3 main -> l3 instr */
 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
 	.master		= &am33xx_l3_main_hwmod,
@@ -2322,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
 };
 
 /* l4 wkup -> wkup m3 */
-static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
-	{
-		.name		= "umem",
-		.pa_start	= 0x44d00000,
-		.pa_end		= 0x44d00000 + SZ_16K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{
-		.name		= "dmem",
-		.pa_start	= 0x44d80000,
-		.pa_end		= 0x44d80000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_wkup_m3_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_wkup_m3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 hs -> pru-icss */
-static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
-	{
-		.pa_start	= 0x4a300000,
-		.pa_end		= 0x4a300000 + SZ_512K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
 	.master		= &am33xx_l4_hs_hwmod,
 	.slave		= &am33xx_pruss_hwmod,
 	.clk		= "dpll_core_m4_ck",
-	.addr		= am33xx_pruss_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l3 main -> gfx */
-static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
-	{
-		.pa_start	= 0x56000000,
-		.pa_end		= 0x56000000 + SZ_16M - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
 	.master		= &am33xx_l3_main_hwmod,
 	.slave		= &am33xx_gfx_hwmod,
 	.clk		= "dpll_core_m4_ck",
-	.addr		= am33xx_gfx_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 wkup -> smartreflex0 */
-static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
-	{
-		.pa_start	= 0x44e37000,
-		.pa_end		= 0x44e37000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_smartreflex0_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_smartreflex0_addrs,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 wkup -> smartreflex1 */
-static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
-	{
-		.pa_start	= 0x44e39000,
-		.pa_end		= 0x44e39000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_smartreflex1_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_smartreflex1_addrs,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 wkup -> control */
-static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
-	{
-		.pa_start	= 0x44e10000,
-		.pa_end		= 0x44e10000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_control_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_control_addrs,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 wkup -> rtc */
-static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
-	{
-		.pa_start	= 0x44e3e000,
-		.pa_end		= 0x44e3e000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_rtc_hwmod,
 	.clk		= "clkdiv32k_ick",
-	.addr		= am33xx_rtc_addrs,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per/ls -> DCAN0 */
-static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
-	{
-		.pa_start	= 0x481CC000,
-		.pa_end		= 0x481CC000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_dcan0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_dcan0_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> DCAN1 */
-static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
-	{
-		.pa_start	= 0x481D0000,
-		.pa_end		= 0x481D0000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_dcan1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_dcan1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> GPIO2 */
-static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
-	{
-		.pa_start	= 0x4804C000,
-		.pa_end		= 0x4804C000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_gpio1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_gpio1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> gpio3 */
-static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
-	{
-		.pa_start	= 0x481AC000,
-		.pa_end		= 0x481AC000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_gpio2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_gpio2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> gpio4 */
-static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
-	{
-		.pa_start	= 0x481AE000,
-		.pa_end		= 0x481AE000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_gpio3_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_gpio3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 WKUP -> I2C1 */
-static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
-	{
-		.pa_start	= 0x44E0B000,
-		.pa_end		= 0x44E0B000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_i2c1_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_i2c1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* L4 WKUP -> GPIO1 */
-static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
-	{
-		.pa_start	= 0x44E07000,
-		.pa_end		= 0x44E07000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_gpio0_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_gpio0_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2598,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
-	/* cpsw ss */
-	{
-		.pa_start	= 0x4a100000,
-		.pa_end		= 0x4a100000 + SZ_2K - 1,
-	},
-	/* cpsw wr */
-	{
-		.pa_start	= 0x4a101200,
-		.pa_end		= 0x4a101200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
 	.master		= &am33xx_l4_hs_hwmod,
 	.slave		= &am33xx_cpgmac0_hwmod,
 	.clk		= "cpsw_125mhz_gclk",
-	.addr		= am33xx_cpgmac0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
-	{
-		.pa_start	= 0x4A101000,
-		.pa_end		= 0x4A101000 + SZ_256 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
 	.master		= &am33xx_cpgmac0_hwmod,
 	.slave		= &am33xx_mdio_hwmod,
-	.addr		= am33xx_mdio_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -2670,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
-	{
-		.pa_start	= 0x48300100,
-		.pa_end		= 0x48300100 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
 	.master		= &am33xx_epwmss0_hwmod,
 	.slave		= &am33xx_ecap0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ecap0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
-	{
-		.pa_start	= 0x48300180,
-		.pa_end		= 0x48300180 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
 	.master		= &am33xx_epwmss0_hwmod,
 	.slave		= &am33xx_eqep0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_eqep0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
-	{
-		.pa_start	= 0x48300200,
-		.pa_end		= 0x48300200 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
 	.master		= &am33xx_epwmss0_hwmod,
 	.slave		= &am33xx_ehrpwm0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ehrpwm0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -2736,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
-	{
-		.pa_start	= 0x48302100,
-		.pa_end		= 0x48302100 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
 	.master		= &am33xx_epwmss1_hwmod,
 	.slave		= &am33xx_ecap1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ecap1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
-	{
-		.pa_start	= 0x48302180,
-		.pa_end		= 0x48302180 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
 	.master		= &am33xx_epwmss1_hwmod,
 	.slave		= &am33xx_eqep1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_eqep1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
-	{
-		.pa_start	= 0x48302200,
-		.pa_end		= 0x48302200 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
 	.master		= &am33xx_epwmss1_hwmod,
 	.slave		= &am33xx_ehrpwm1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ehrpwm1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -2801,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
-	{
-		.pa_start	= 0x48304100,
-		.pa_end		= 0x48304100 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
 	.master		= &am33xx_epwmss2_hwmod,
 	.slave		= &am33xx_ecap2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ecap2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
-	{
-		.pa_start	= 0x48304180,
-		.pa_end		= 0x48304180 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
 	.master		= &am33xx_epwmss2_hwmod,
 	.slave		= &am33xx_eqep2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_eqep2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
-	{
-		.pa_start	= 0x48304200,
-		.pa_end		= 0x48304200 + SZ_128 - 1,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
 	.master		= &am33xx_epwmss2_hwmod,
 	.slave		= &am33xx_ehrpwm2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ehrpwm2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -2868,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
 };
 
 /* i2c2 */
-static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
-	{
-		.pa_start	= 0x4802A000,
-		.pa_end		= 0x4802A000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_i2c2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_i2c2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
-	{
-		.pa_start	= 0x4819C000,
-		.pa_end		= 0x4819C000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_i2c3_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_i2c3_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -2938,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
 };
 
 /* l4 ls -> spinlock */
-static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
-	{
-		.pa_start	= 0x480Ca000,
-		.pa_end		= 0x480Ca000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_spinlock_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_spinlock_addrs,
 	.user		= OCP_USER_MPU,
 };
 
@@ -2973,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
 	.user		= OCP_USER_MPU,
 };
 
-/* l3 s -> mcasp0 data */
-static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
-	{
-		.pa_start	= 0x46000000,
-		.pa_end		= 0x46000000 + SZ_4M - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
-	.master		= &am33xx_l3_s_hwmod,
-	.slave		= &am33xx_mcasp0_hwmod,
-	.clk		= "l3s_gclk",
-	.addr		= am33xx_mcasp0_data_addr_space,
-	.user		= OCP_USER_SDMA,
-};
-
 /* l4 ls -> mcasp1 */
 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
 	{
@@ -3009,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
 	.user		= OCP_USER_MPU,
 };
 
-/* l3 s -> mcasp1 data */
-static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
-	{
-		.pa_start	= 0x46400000,
-		.pa_end		= 0x46400000 + SZ_4M - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
-	.master		= &am33xx_l3_s_hwmod,
-	.slave		= &am33xx_mcasp1_hwmod,
-	.clk		= "l3s_gclk",
-	.addr		= am33xx_mcasp1_data_addr_space,
-	.user		= OCP_USER_SDMA,
-};
-
 /* l4 ls -> mmc0 */
 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
 	{
@@ -3082,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
 };
 
 /* l4 ls -> mcspi0 */
-static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
-	{
-		.pa_start	= 0x48030000,
-		.pa_end		= 0x48030000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_spi0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_mcspi0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 ls -> mcspi1 */
-static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
-	{
-		.pa_start	= 0x481A0000,
-		.pa_end		= 0x481A0000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_spi1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_mcspi1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 wkup -> timer1 */
-static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
-	{
-		.pa_start	= 0x44E31000,
-		.pa_end		= 0x44E31000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_timer1_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_timer1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per -> timer2 */
-static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
-	{
-		.pa_start	= 0x48040000,
-		.pa_end		= 0x48040000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_timer2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_timer2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per -> timer3 */
-static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
-	{
-		.pa_start	= 0x48042000,
-		.pa_end		= 0x48042000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_timer3_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_timer3_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per -> timer4 */
-static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
-	{
-		.pa_start	= 0x48044000,
-		.pa_end		= 0x48044000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_timer4_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_timer4_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per -> timer5 */
-static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
-	{
-		.pa_start	= 0x48046000,
-		.pa_end		= 0x48046000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_timer5_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_timer5_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per -> timer6 */
-static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
-	{
-		.pa_start	= 0x48048000,
-		.pa_end		= 0x48048000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_timer6_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_timer6_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 per -> timer7 */
-static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
-	{
-		.pa_start	= 0x4804A000,
-		.pa_end		= 0x4804A000 + SZ_1K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_timer7_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_timer7_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l3 main -> tpcc */
-static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
-	{
-		.pa_start	= 0x49000000,
-		.pa_end		= 0x49000000 + SZ_32K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
 	.master		= &am33xx_l3_main_hwmod,
 	.slave		= &am33xx_tpcc_hwmod,
 	.clk		= "l3_gclk",
-	.addr		= am33xx_tpcc_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -3316,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
 };
 
 /* l4 wkup -> uart1 */
-static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
-	{
-		.pa_start	= 0x44E09000,
-		.pa_end		= 0x44E09000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_uart1_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_uart1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 ls -> uart2 */
-static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
-	{
-		.pa_start	= 0x48022000,
-		.pa_end		= 0x48022000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_uart2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_uart2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 ls -> uart3 */
-static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
-	{
-		.pa_start	= 0x48024000,
-		.pa_end		= 0x48024000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_uart3_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_uart3_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 ls -> uart4 */
-static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
-	{
-		.pa_start	= 0x481A6000,
-		.pa_end		= 0x481A6000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_uart4_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_uart4_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 ls -> uart5 */
-static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
-	{
-		.pa_start	= 0x481A8000,
-		.pa_end		= 0x481A8000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_uart5_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_uart5_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 ls -> uart6 */
-static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
-	{
-		.pa_start	= 0x481aa000,
-		.pa_end		= 0x481aa000 + SZ_8K - 1,
-		.flags		= ADDR_TYPE_RT,
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
 	.master		= &am33xx_l4_ls_hwmod,
 	.slave		= &am33xx_uart6_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_uart6_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
 /* l4 wkup -> wd_timer1 */
-static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
-	{
-		.pa_start	= 0x44e35000,
-		.pa_end		= 0x44e35000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
 	.master		= &am33xx_l4_wkup_hwmod,
 	.slave		= &am33xx_wd_timer1_hwmod,
 	.clk		= "dpll_core_m4_div2_ck",
-	.addr		= am33xx_wd_timer1_addrs,
 	.user		= OCP_USER_MPU,
 };
 
 /* usbss */
 /* l3 s -> USBSS interface */
-static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
-	{
-		.name		= "usbss",
-		.pa_start	= 0x47400000,
-		.pa_end		= 0x47400000 + SZ_4K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{
-		.name		= "musb0",
-		.pa_start	= 0x47401000,
-		.pa_end		= 0x47401000 + SZ_2K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{
-		.name		= "musb1",
-		.pa_start	= 0x47401800,
-		.pa_end		= 0x47401800 + SZ_2K - 1,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
 	.master		= &am33xx_l3_s_hwmod,
 	.slave		= &am33xx_usbss_hwmod,
 	.clk		= "l3s_gclk",
-	.addr		= am33xx_usbss_addr_space,
 	.user		= OCP_USER_MPU,
 	.flags		= OCPIF_SWSUP_IDLE,
 };
@@ -3518,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 };
 
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
-	&am33xx_l4_fw__emif_fw,
 	&am33xx_l3_main__emif,
 	&am33xx_mpu__l3_main,
 	&am33xx_mpu__prcm,
 	&am33xx_l3_s__l4_ls,
 	&am33xx_l3_s__l4_wkup,
-	&am33xx_l3_s__l4_fw,
 	&am33xx_l3_main__l4_hs,
 	&am33xx_l3_main__l3_s,
 	&am33xx_l3_main__l3_instr,
@@ -3554,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_per__i2c3,
 	&am33xx_l4_per__mailbox,
 	&am33xx_l4_ls__mcasp0,
-	&am33xx_l3_s__mcasp0_data,
 	&am33xx_l4_ls__mcasp1,
-	&am33xx_l3_s__mcasp1_data,
 	&am33xx_l4_ls__mmc0,
 	&am33xx_l4_ls__mmc1,
 	&am33xx_l3_s__mmc2,
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:38:14 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:38:14 -0400
Subject: [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1369845494-30231-15-git-send-email-santosh.shilimkar@ti.com>

From: Sricharan R <r.sricharan at ti.com>

- The IO resource information like dma request lines, irq number and
  ocp address space can be populated via dt blob. So such data is stripped
  from OMAP4 SOC hwmod data file.

- The devices which are still missing the device tree bindings,
  address space entries are not removed yet. When such devices add
  the dt bindings, respective address space data can be deleted.

- Also other unnessecary hwmods like firewalls are removed as a part of this.

The above update, results in reduction of about ~1650 lines of code.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Sricharan R <r.sricharan at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1661 +---------------------------
 1 file changed, 19 insertions(+), 1642 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 848b6dc..36dbd63 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -52,27 +52,6 @@
  */
 
 /*
- * 'c2c_target_fw' class
- * instance(s): c2c_target_fw
- */
-static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
-	.name	= "c2c_target_fw",
-};
-
-/* c2c_target_fw */
-static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
-	.name		= "c2c_target_fw",
-	.class		= &omap44xx_c2c_target_fw_hwmod_class,
-	.clkdm_name	= "d2d_clkdm",
-	.prcm = {
-		.omap4 = {
-			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
-			.context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
-		},
-	},
-};
-
-/*
  * 'dmm' class
  * instance(s): dmm
  */
@@ -81,16 +60,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
 };
 
 /* dmm */
-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
-	{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_dmm_hwmod = {
 	.name		= "dmm",
 	.class		= &omap44xx_dmm_hwmod_class,
 	.clkdm_name	= "l3_emif_clkdm",
-	.mpu_irqs	= omap44xx_dmm_irqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
@@ -100,27 +73,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
 };
 
 /*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
-	.name	= "emif_fw",
-};
-
-/* emif_fw */
-static struct omap_hwmod omap44xx_emif_fw_hwmod = {
-	.name		= "emif_fw",
-	.class		= &omap44xx_emif_fw_hwmod_class,
-	.clkdm_name	= "l3_emif_clkdm",
-	.prcm = {
-		.omap4 = {
-			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
-			.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
-		},
-	},
-};
-
-/*
  * 'l3' class
  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  */
@@ -143,17 +95,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 };
 
 /* l3_main_1 */
-static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
-	{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 	.name		= "l3_main_1",
 	.class		= &omap44xx_l3_hwmod_class,
 	.clkdm_name	= "l3_1_clkdm",
-	.mpu_irqs	= omap44xx_l3_main_1_irqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
@@ -326,29 +271,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 };
 
 /* aess */
-static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
-	{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
-	{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
-	{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_aess_hwmod = {
 	.name		= "aess",
 	.class		= &omap44xx_aess_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_aess_irqs,
-	.sdma_reqs	= omap44xx_aess_sdma_reqs,
 	.main_clk	= "aess_fclk",
 	.prcm = {
 		.omap4 = {
@@ -371,22 +297,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 };
 
 /* c2c */
-static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
-	{ .irq = 88 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
-	{ .dma_req = 68 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_c2c_hwmod = {
 	.name		= "c2c",
 	.class		= &omap44xx_c2c_hwmod_class,
 	.clkdm_name	= "d2d_clkdm",
-	.mpu_irqs	= omap44xx_c2c_irqs,
-	.sdma_reqs	= omap44xx_c2c_sdma_reqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
@@ -449,16 +363,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 };
 
 /* ctrl_module_core */
-static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
-	{ .irq = 8 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 	.name		= "ctrl_module_core",
 	.class		= &omap44xx_ctrl_module_hwmod_class,
 	.clkdm_name	= "l4_cfg_clkdm",
-	.mpu_irqs	= omap44xx_ctrl_module_core_irqs,
 	.prcm = {
 		.omap4 = {
 			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
@@ -556,7 +464,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
 	.lch_count	= 32,
 };
 
-/* dma_system */
 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 	{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 	{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
@@ -565,6 +472,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 	{ .irq = -1 }
 };
 
+/* dma_system */
 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 	.name		= "dma_system",
 	.class		= &omap44xx_dma_hwmod_class,
@@ -601,22 +509,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 };
 
 /* dmic */
-static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
-	{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
-	{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_dmic_hwmod = {
 	.name		= "dmic",
 	.class		= &omap44xx_dmic_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_dmic_irqs,
-	.sdma_reqs	= omap44xx_dmic_sdma_reqs,
 	.main_clk	= "func_dmic_abe_gfclk",
 	.prcm = {
 		.omap4 = {
@@ -637,11 +533,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 };
 
 /* dsp */
-static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
-	{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 	{ .name = "dsp", .rst_shift = 0 },
 };
@@ -650,7 +541,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
 	.name		= "dsp",
 	.class		= &omap44xx_dsp_hwmod_class,
 	.clkdm_name	= "tesla_clkdm",
-	.mpu_irqs	= omap44xx_dsp_irqs,
 	.rst_lines	= omap44xx_dsp_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
 	.main_clk	= "dpll_iva_m4x2_ck",
@@ -728,16 +618,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 };
 
 /* dss_dispc */
-static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
-	{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
-	{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 	.manager_count		= 3,
 	.has_framedonetv_irq	= 1
@@ -747,8 +627,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 	.name		= "dss_dispc",
 	.class		= &omap44xx_dispc_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.mpu_irqs	= omap44xx_dss_dispc_irqs,
-	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
 	.main_clk	= "dss_dss_clk",
 	.prcm = {
 		.omap4 = {
@@ -781,16 +659,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 };
 
 /* dss_dsi1 */
-static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
-	{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
-	{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -799,8 +667,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 	.name		= "dss_dsi1",
 	.class		= &omap44xx_dsi_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.mpu_irqs	= omap44xx_dss_dsi1_irqs,
-	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
 	.main_clk	= "dss_dss_clk",
 	.prcm = {
 		.omap4 = {
@@ -813,16 +679,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 };
 
 /* dss_dsi2 */
-static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
-	{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
-	{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -831,8 +687,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 	.name		= "dss_dsi2",
 	.class		= &omap44xx_dsi_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.mpu_irqs	= omap44xx_dss_dsi2_irqs,
-	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
 	.main_clk	= "dss_dss_clk",
 	.prcm = {
 		.omap4 = {
@@ -865,16 +719,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 };
 
 /* dss_hdmi */
-static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
-	{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
-	{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -888,8 +732,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 	 * set idle mode by software.
 	 */
 	.flags		= HWMOD_SWSUP_SIDLE,
-	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
-	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
 	.main_clk	= "dss_48mhz_clk",
 	.prcm = {
 		.omap4 = {
@@ -922,11 +764,6 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 };
 
 /* dss_rfbi */
-static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
-	{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 	{ .role = "ick", .clk = "dss_fck" },
 };
@@ -935,7 +772,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap44xx_rfbi_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
 	.main_clk	= "dss_dss_clk",
 	.prcm = {
 		.omap4 = {
@@ -992,16 +828,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 };
 
 /* elm */
-static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
-	{ .irq = 4 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_elm_hwmod = {
 	.name		= "elm",
 	.class		= &omap44xx_elm_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_elm_irqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
@@ -1025,17 +855,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 };
 
 /* emif1 */
-static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
-	{ .irq = 110 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_emif1_hwmod = {
 	.name		= "emif1",
 	.class		= &omap44xx_emif_hwmod_class,
 	.clkdm_name	= "l3_emif_clkdm",
 	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-	.mpu_irqs	= omap44xx_emif1_irqs,
 	.main_clk	= "ddrphy_ck",
 	.prcm = {
 		.omap4 = {
@@ -1047,17 +871,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
 };
 
 /* emif2 */
-static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
-	{ .irq = 111 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_emif2_hwmod = {
 	.name		= "emif2",
 	.class		= &omap44xx_emif_hwmod_class,
 	.clkdm_name	= "l3_emif_clkdm",
 	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-	.mpu_irqs	= omap44xx_emif2_irqs,
 	.main_clk	= "ddrphy_ck",
 	.prcm = {
 		.omap4 = {
@@ -1098,16 +916,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 };
 
 /* fdif */
-static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
-	{ .irq = 69 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_fdif_hwmod = {
 	.name		= "fdif",
 	.class		= &omap44xx_fdif_hwmod_class,
 	.clkdm_name	= "iss_clkdm",
-	.mpu_irqs	= omap44xx_fdif_irqs,
 	.main_clk	= "fdif_fck",
 	.prcm = {
 		.omap4 = {
@@ -1148,11 +960,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 };
 
 /* gpio1 */
-static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
-	{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1161,7 +968,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
 	.name		= "gpio1",
 	.class		= &omap44xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= omap44xx_gpio1_irqs,
 	.main_clk	= "l4_wkup_clk_mux_ck",
 	.prcm = {
 		.omap4 = {
@@ -1176,11 +982,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
-	{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1190,7 +991,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
 	.class		= &omap44xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap44xx_gpio2_irqs,
 	.main_clk	= "l4_div_ck",
 	.prcm = {
 		.omap4 = {
@@ -1205,11 +1005,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
-	{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1219,7 +1014,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
 	.class		= &omap44xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap44xx_gpio3_irqs,
 	.main_clk	= "l4_div_ck",
 	.prcm = {
 		.omap4 = {
@@ -1234,11 +1028,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
 };
 
 /* gpio4 */
-static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
-	{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio4_dbclk" },
 };
@@ -1248,7 +1037,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
 	.class		= &omap44xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap44xx_gpio4_irqs,
 	.main_clk	= "l4_div_ck",
 	.prcm = {
 		.omap4 = {
@@ -1263,11 +1051,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
 };
 
 /* gpio5 */
-static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
-	{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio5_dbclk" },
 };
@@ -1277,7 +1060,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
 	.class		= &omap44xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap44xx_gpio5_irqs,
 	.main_clk	= "l4_div_ck",
 	.prcm = {
 		.omap4 = {
@@ -1292,11 +1074,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
 };
 
 /* gpio6 */
-static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
-	{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio6_dbclk" },
 };
@@ -1306,7 +1083,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
 	.class		= &omap44xx_gpio_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap44xx_gpio6_irqs,
 	.main_clk	= "l4_div_ck",
 	.prcm = {
 		.omap4 = {
@@ -1341,16 +1117,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 };
 
 /* gpmc */
-static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
-	{ .irq = 20 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
-	{ .dma_req = 3 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_gpmc_hwmod = {
 	.name		= "gpmc",
 	.class		= &omap44xx_gpmc_hwmod_class,
@@ -1364,8 +1130,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
 	 * HWMOD_INIT_NO_RESET should be removed ASAP.
 	 */
 	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-	.mpu_irqs	= omap44xx_gpmc_irqs,
-	.sdma_reqs	= omap44xx_gpmc_sdma_reqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
@@ -1396,16 +1160,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
 };
 
 /* gpu */
-static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
-	{ .irq = 21 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_gpu_hwmod = {
 	.name		= "gpu",
 	.class		= &omap44xx_gpu_hwmod_class,
 	.clkdm_name	= "l3_gfx_clkdm",
-	.mpu_irqs	= omap44xx_gpu_irqs,
 	.main_clk	= "sgx_clk_mux",
 	.prcm = {
 		.omap4 = {
@@ -1436,17 +1194,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
 };
 
 /* hdq1w */
-static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
-	{ .irq = 58 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
 	.name		= "hdq1w",
 	.class		= &omap44xx_hdq1w_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
-	.mpu_irqs	= omap44xx_hdq1w_irqs,
 	.main_clk	= "func_12m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -1482,18 +1234,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
 };
 
 /* hsi */
-static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
-	{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_hsi_hwmod = {
 	.name		= "hsi",
 	.class		= &omap44xx_hsi_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
-	.mpu_irqs	= omap44xx_hsi_irqs,
 	.main_clk	= "hsi_fck",
 	.prcm = {
 		.omap4 = {
@@ -1533,24 +1277,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 
 /* i2c1 */
-static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
-	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
 	.name		= "i2c1",
 	.class		= &omap44xx_i2c_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_i2c1_irqs,
-	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
 	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -1563,24 +1294,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
 };
 
 /* i2c2 */
-static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
-	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
 	.name		= "i2c2",
 	.class		= &omap44xx_i2c_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_i2c2_irqs,
-	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
 	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -1593,24 +1311,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
 };
 
 /* i2c3 */
-static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
-	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
 	.name		= "i2c3",
 	.class		= &omap44xx_i2c_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_i2c3_irqs,
-	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
 	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -1623,24 +1328,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
 };
 
 /* i2c4 */
-static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
-	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
 	.name		= "i2c4",
 	.class		= &omap44xx_i2c_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_i2c4_irqs,
-	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
 	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -1662,11 +1354,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
 };
 
 /* ipu */
-static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
-	{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
 	{ .name = "cpu0", .rst_shift = 0 },
 	{ .name = "cpu1", .rst_shift = 1 },
@@ -1676,7 +1363,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
 	.name		= "ipu",
 	.class		= &omap44xx_ipu_hwmod_class,
 	.clkdm_name	= "ducati_clkdm",
-	.mpu_irqs	= omap44xx_ipu_irqs,
 	.rst_lines	= omap44xx_ipu_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
 	.main_clk	= "ducati_clk_mux_ck",
@@ -1721,19 +1407,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 };
 
 /* iss */
-static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
-	{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
-	{ .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
-	{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
-	{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
-	{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
 	{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
 };
@@ -1742,8 +1415,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
 	.name		= "iss",
 	.class		= &omap44xx_iss_hwmod_class,
 	.clkdm_name	= "iss_clkdm",
-	.mpu_irqs	= omap44xx_iss_irqs,
-	.sdma_reqs	= omap44xx_iss_sdma_reqs,
 	.main_clk	= "ducati_clk_mux_ck",
 	.prcm = {
 		.omap4 = {
@@ -1766,13 +1437,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 };
 
 /* iva */
-static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
-	{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
 	{ .name = "seq0", .rst_shift = 0 },
 	{ .name = "seq1", .rst_shift = 1 },
@@ -1783,7 +1447,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
 	.name		= "iva",
 	.class		= &omap44xx_iva_hwmod_class,
 	.clkdm_name	= "ivahd_clkdm",
-	.mpu_irqs	= omap44xx_iva_irqs,
 	.rst_lines	= omap44xx_iva_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
 	.main_clk	= "dpll_iva_m5x2_ck",
@@ -1820,16 +1483,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
 };
 
 /* kbd */
-static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
-	{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_kbd_hwmod = {
 	.name		= "kbd",
 	.class		= &omap44xx_kbd_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= omap44xx_kbd_irqs,
 	.main_clk	= "sys_32k_ck",
 	.prcm = {
 		.omap4 = {
@@ -1861,16 +1518,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 };
 
 /* mailbox */
-static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
-	{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_mailbox_hwmod = {
 	.name		= "mailbox",
 	.class		= &omap44xx_mailbox_hwmod_class,
 	.clkdm_name	= "l4_cfg_clkdm",
-	.mpu_irqs	= omap44xx_mailbox_irqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
@@ -1903,24 +1554,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
 };
 
 /* mcasp */
-static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
-	{ .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
-	{ .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
-	{ .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mcasp_hwmod = {
 	.name		= "mcasp",
 	.class		= &omap44xx_mcasp_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_mcasp_irqs,
-	.sdma_reqs	= omap44xx_mcasp_sdma_reqs,
 	.main_clk	= "func_mcasp_abe_gfclk",
 	.prcm = {
 		.omap4 = {
@@ -1951,17 +1588,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 };
 
 /* mcbsp1 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
-	{ .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
 	{ .role = "pad_fck", .clk = "pad_clks_ck" },
 	{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
@@ -1971,8 +1597,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 	.name		= "mcbsp1",
 	.class		= &omap44xx_mcbsp_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_mcbsp1_irqs,
-	.sdma_reqs	= omap44xx_mcbsp1_sdma_reqs,
 	.main_clk	= "func_mcbsp1_gfclk",
 	.prcm = {
 		.omap4 = {
@@ -1986,17 +1610,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 };
 
 /* mcbsp2 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
-	{ .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
 	{ .role = "pad_fck", .clk = "pad_clks_ck" },
 	{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
@@ -2006,8 +1619,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 	.name		= "mcbsp2",
 	.class		= &omap44xx_mcbsp_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_mcbsp2_irqs,
-	.sdma_reqs	= omap44xx_mcbsp2_sdma_reqs,
 	.main_clk	= "func_mcbsp2_gfclk",
 	.prcm = {
 		.omap4 = {
@@ -2021,17 +1632,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 };
 
 /* mcbsp3 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
-	{ .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
 	{ .role = "pad_fck", .clk = "pad_clks_ck" },
 	{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
@@ -2041,8 +1641,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 	.name		= "mcbsp3",
 	.class		= &omap44xx_mcbsp_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_mcbsp3_irqs,
-	.sdma_reqs	= omap44xx_mcbsp3_sdma_reqs,
 	.main_clk	= "func_mcbsp3_gfclk",
 	.prcm = {
 		.omap4 = {
@@ -2056,17 +1654,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 };
 
 /* mcbsp4 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
-	{ .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
 	{ .role = "pad_fck", .clk = "pad_clks_ck" },
 	{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
@@ -2076,8 +1663,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
 	.name		= "mcbsp4",
 	.class		= &omap44xx_mcbsp_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mcbsp4_irqs,
-	.sdma_reqs	= omap44xx_mcbsp4_sdma_reqs,
 	.main_clk	= "per_mcbsp4_gfclk",
 	.prcm = {
 		.omap4 = {
@@ -2112,17 +1697,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
 };
 
 /* mcpdm */
-static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
-	{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
-	{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
-	{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
 	.name		= "mcpdm",
 	.class		= &omap44xx_mcpdm_hwmod_class,
@@ -2139,8 +1713,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
 	 * results 'slow motion' audio playback.
 	 */
 	.flags		= HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
-	.mpu_irqs	= omap44xx_mcpdm_irqs,
-	.sdma_reqs	= omap44xx_mcpdm_sdma_reqs,
 	.main_clk	= "pad_clks_ck",
 	.prcm = {
 		.omap4 = {
@@ -2174,23 +1746,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
 };
 
 /* mcspi1 */
-static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
-	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
-	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 /* mcspi1 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
 	.num_chipselect	= 4,
@@ -2200,8 +1755,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
 	.name		= "mcspi1",
 	.class		= &omap44xx_mcspi_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mcspi1_irqs,
-	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2214,19 +1767,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
 };
 
 /* mcspi2 */
-static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
-	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
-	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 /* mcspi2 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
 	.num_chipselect	= 2,
@@ -2236,8 +1776,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
 	.name		= "mcspi2",
 	.class		= &omap44xx_mcspi_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mcspi2_irqs,
-	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2250,19 +1788,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
 };
 
 /* mcspi3 */
-static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
-	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
-	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 /* mcspi3 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
 	.num_chipselect	= 2,
@@ -2272,8 +1797,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
 	.name		= "mcspi3",
 	.class		= &omap44xx_mcspi_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mcspi3_irqs,
-	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2286,17 +1809,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
 };
 
 /* mcspi4 */
-static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
-	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
-	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 /* mcspi4 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
 	.num_chipselect	= 1,
@@ -2306,8 +1818,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
 	.name		= "mcspi4",
 	.class		= &omap44xx_mcspi_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mcspi4_irqs,
-	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2342,17 +1852,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
 };
 
 /* mmc1 */
-static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
-	{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 /* mmc1 dev_attr */
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
 	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -2362,8 +1861,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 	.name		= "mmc1",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
-	.mpu_irqs	= omap44xx_mmc1_irqs,
-	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
 	.main_clk	= "hsmmc1_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2376,23 +1873,10 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 };
 
 /* mmc2 */
-static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
-	{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mmc2_hwmod = {
 	.name		= "mmc2",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
-	.mpu_irqs	= omap44xx_mmc2_irqs,
-	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
 	.main_clk	= "hsmmc2_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2404,23 +1888,10 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
 };
 
 /* mmc3 */
-static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
-	{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mmc3_hwmod = {
 	.name		= "mmc3",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mmc3_irqs,
-	.sdma_reqs	= omap44xx_mmc3_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2432,23 +1903,10 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
 };
 
 /* mmc4 */
-static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
-	{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mmc4_hwmod = {
 	.name		= "mmc4",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mmc4_irqs,
-	.sdma_reqs	= omap44xx_mmc4_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2460,23 +1918,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
 };
 
 /* mmc5 */
-static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
-	{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mmc5_hwmod = {
 	.name		= "mmc5",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_mmc5_irqs,
-	.sdma_reqs	= omap44xx_mmc5_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -2517,11 +1962,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
 };
 
 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
-	{ .irq = 100 + OMAP44XX_IRQ_GIC_START, },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
 	{ .name = "mmu_cache", .rst_shift = 2 },
 };
@@ -2548,7 +1988,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
 	.name		= "mmu_ipu",
 	.class		= &omap44xx_mmu_hwmod_class,
 	.clkdm_name	= "ducati_clkdm",
-	.mpu_irqs	= omap44xx_mmu_ipu_irqs,
 	.rst_lines	= omap44xx_mmu_ipu_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_ipu_resets),
 	.main_clk	= "ducati_clk_mux_ck",
@@ -2572,11 +2011,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
 };
 
 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
-	{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
 	{ .name = "mmu_cache", .rst_shift = 1 },
 };
@@ -2603,7 +2037,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
 	.name		= "mmu_dsp",
 	.class		= &omap44xx_mmu_hwmod_class,
 	.clkdm_name	= "tesla_clkdm",
-	.mpu_irqs	= omap44xx_mmu_dsp_irqs,
 	.rst_lines	= omap44xx_mmu_dsp_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_dsp_resets),
 	.main_clk	= "dpll_iva_m4x2_ck",
@@ -2628,21 +2061,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 };
 
 /* mpu */
-static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
-	{ .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_mpu_hwmod = {
 	.name		= "mpu",
 	.class		= &omap44xx_mpu_hwmod_class,
 	.clkdm_name	= "mpuss_clkdm",
 	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-	.mpu_irqs	= omap44xx_mpu_irqs,
 	.main_clk	= "dpll_mpu_m2_ck",
 	.prcm = {
 		.omap4 = {
@@ -2696,20 +2119,9 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
 };
 
 /* ocp2scp dev_attr */
-static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
-	{
-		.name		= "usb_phy",
-		.start		= 0x4a0ad080,
-		.end		= 0x4a0ae000,
-		.flags		= IORESOURCE_MEM,
-	},
-	{ }
-};
-
 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
 	{
 		.drv_name       = "omap-usb2",
-		.res		= omap44xx_usb_phy_and_pll_addrs,
 	},
 	{ }
 };
@@ -2788,11 +2200,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = {
 };
 
 /* prm */
-static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
-	{ .irq = 11 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 	{ .name = "rst_global_warm_sw", .rst_shift = 0 },
 	{ .name = "rst_global_cold_sw", .rst_shift = 1 },
@@ -2801,7 +2208,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 static struct omap_hwmod omap44xx_prm_hwmod = {
 	.name		= "prm",
 	.class		= &omap44xx_prcm_hwmod_class,
-	.mpu_irqs	= omap44xx_prm_irqs,
 	.rst_lines	= omap44xx_prm_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_prm_resets),
 };
@@ -2872,23 +2278,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
 };
 
 /* slimbus1 */
-static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
-	{ .irq = 97 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
-	{ .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
 	{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
 	{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
@@ -2900,8 +2289,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
 	.name		= "slimbus1",
 	.class		= &omap44xx_slimbus_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_slimbus1_irqs,
-	.sdma_reqs	= omap44xx_slimbus1_sdma_reqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
@@ -2914,23 +2301,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
 };
 
 /* slimbus2 */
-static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
-	{ .irq = 98 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
-	{ .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
-	{ .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
 	{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
 	{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
@@ -2941,8 +2311,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
 	.name		= "slimbus2",
 	.class		= &omap44xx_slimbus_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_slimbus2_irqs,
-	.sdma_reqs	= omap44xx_slimbus2_sdma_reqs,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
@@ -2985,16 +2353,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
 	.sensor_voltdm_name   = "core",
 };
 
-static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
-	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 	.name		= "smartreflex_core",
 	.class		= &omap44xx_smartreflex_hwmod_class,
 	.clkdm_name	= "l4_ao_clkdm",
-	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
 
 	.main_clk	= "smartreflex_core_fck",
 	.prcm = {
@@ -3012,16 +2374,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
 	.sensor_voltdm_name	= "iva",
 };
 
-static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
-	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 	.name		= "smartreflex_iva",
 	.class		= &omap44xx_smartreflex_hwmod_class,
 	.clkdm_name	= "l4_ao_clkdm",
-	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
 	.main_clk	= "smartreflex_iva_fck",
 	.prcm = {
 		.omap4 = {
@@ -3038,16 +2394,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
 	.sensor_voltdm_name	= "mpu",
 };
 
-static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
-	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 	.name		= "smartreflex_mpu",
 	.class		= &omap44xx_smartreflex_hwmod_class,
 	.clkdm_name	= "l4_ao_clkdm",
-	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
 	.main_clk	= "smartreflex_mpu_fck",
 	.prcm = {
 		.omap4 = {
@@ -3155,17 +2505,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 };
 
 /* timer1 */
-static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
-	{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer1_hwmod = {
 	.name		= "timer1",
 	.class		= &omap44xx_timer_1ms_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_timer1_irqs,
 	.main_clk	= "dmt1_clk_mux",
 	.prcm = {
 		.omap4 = {
@@ -3178,17 +2522,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
 };
 
 /* timer2 */
-static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
-	{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer2_hwmod = {
 	.name		= "timer2",
 	.class		= &omap44xx_timer_1ms_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_timer2_irqs,
 	.main_clk	= "cm2_dm2_mux",
 	.prcm = {
 		.omap4 = {
@@ -3200,16 +2538,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
 };
 
 /* timer3 */
-static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
-	{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer3_hwmod = {
 	.name		= "timer3",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_timer3_irqs,
 	.main_clk	= "cm2_dm3_mux",
 	.prcm = {
 		.omap4 = {
@@ -3221,16 +2553,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
 };
 
 /* timer4 */
-static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
-	{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer4_hwmod = {
 	.name		= "timer4",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_timer4_irqs,
 	.main_clk	= "cm2_dm4_mux",
 	.prcm = {
 		.omap4 = {
@@ -3242,16 +2568,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
 };
 
 /* timer5 */
-static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
-	{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer5_hwmod = {
 	.name		= "timer5",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_timer5_irqs,
 	.main_clk	= "timer5_sync_mux",
 	.prcm = {
 		.omap4 = {
@@ -3264,16 +2584,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
 };
 
 /* timer6 */
-static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
-	{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer6_hwmod = {
 	.name		= "timer6",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_timer6_irqs,
 	.main_clk	= "timer6_sync_mux",
 	.prcm = {
 		.omap4 = {
@@ -3286,16 +2600,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
 };
 
 /* timer7 */
-static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
-	{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer7_hwmod = {
 	.name		= "timer7",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_timer7_irqs,
 	.main_clk	= "timer7_sync_mux",
 	.prcm = {
 		.omap4 = {
@@ -3308,16 +2616,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
 };
 
 /* timer8 */
-static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
-	{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer8_hwmod = {
 	.name		= "timer8",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_timer8_irqs,
 	.main_clk	= "timer8_sync_mux",
 	.prcm = {
 		.omap4 = {
@@ -3330,16 +2632,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
 };
 
 /* timer9 */
-static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
-	{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer9_hwmod = {
 	.name		= "timer9",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_timer9_irqs,
 	.main_clk	= "cm2_dm9_mux",
 	.prcm = {
 		.omap4 = {
@@ -3352,17 +2648,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
 };
 
 /* timer10 */
-static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
-	{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer10_hwmod = {
 	.name		= "timer10",
 	.class		= &omap44xx_timer_1ms_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
-	.mpu_irqs	= omap44xx_timer10_irqs,
 	.main_clk	= "cm2_dm10_mux",
 	.prcm = {
 		.omap4 = {
@@ -3375,16 +2665,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
 };
 
 /* timer11 */
-static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
-	{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer11_hwmod = {
 	.name		= "timer11",
 	.class		= &omap44xx_timer_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
-	.mpu_irqs	= omap44xx_timer11_irqs,
 	.main_clk	= "cm2_dm11_mux",
 	.prcm = {
 		.omap4 = {
@@ -3419,24 +2703,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 };
 
 /* uart1 */
-static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
-	{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart1_hwmod = {
 	.name		= "uart1",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= omap44xx_uart1_irqs,
-	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -3448,24 +2719,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
 };
 
 /* uart2 */
-static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
-	{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart2_hwmod = {
 	.name		= "uart2",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= omap44xx_uart2_irqs,
-	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -3477,25 +2735,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
 };
 
 /* uart3 */
-static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
-	{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart3_hwmod = {
 	.name		= "uart3",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
 				HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= omap44xx_uart3_irqs,
-	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -3507,24 +2752,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
 };
 
 /* uart4 */
-static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
-	{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
-	{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
-	{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
-	{ .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart4_hwmod = {
 	.name		= "uart4",
 	.class		= &omap44xx_uart_hwmod_class,
 	.clkdm_name	= "l4_per_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE_ACT,
-	.mpu_irqs	= omap44xx_uart4_irqs,
-	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
 	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
@@ -3563,17 +2795,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
 };
 
 /* usb_host_fs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
-	{ .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
 	.name		= "usb_host_fs",
 	.class		= &omap44xx_usb_host_fs_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
-	.mpu_irqs	= omap44xx_usb_host_fs_irqs,
 	.main_clk	= "usb_host_fs_fck",
 	.prcm = {
 		.omap4 = {
@@ -3607,12 +2832,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
 };
 
 /* usb_host_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
-	{ .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
 	.name		= "usb_host_hs",
 	.class		= &omap44xx_usb_host_hs_hwmod_class,
@@ -3625,7 +2844,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
-	.mpu_irqs	= omap44xx_usb_host_hs_irqs,
 
 	/*
 	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3700,12 +2918,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
 };
 
 /* usb_otg_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
-	{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
-	{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
 	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
 };
@@ -3715,7 +2927,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
 	.class		= &omap44xx_usb_otg_hs_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
-	.mpu_irqs	= omap44xx_usb_otg_hs_irqs,
 	.main_clk	= "usb_otg_hs_ick",
 	.prcm = {
 		.omap4 = {
@@ -3749,16 +2960,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
 	.sysc	= &omap44xx_usb_tll_hs_sysc,
 };
 
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
-	{ .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
 	.name		= "usb_tll_hs",
 	.class		= &omap44xx_usb_tll_hs_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
-	.mpu_irqs	= omap44xx_usb_tll_hs_irqs,
 	.main_clk	= "usb_tll_hs_ick",
 	.prcm = {
 		.omap4 = {
@@ -3794,16 +2999,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 };
 
 /* wd_timer2 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
-	{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 	.name		= "wd_timer2",
 	.class		= &omap44xx_wd_timer_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.mpu_irqs	= omap44xx_wd_timer2_irqs,
 	.main_clk	= "sys_32k_ck",
 	.prcm = {
 		.omap4 = {
@@ -3815,16 +3014,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 };
 
 /* wd_timer3 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
-	{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
-	{ .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 	.name		= "wd_timer3",
 	.class		= &omap44xx_wd_timer_hwmod_class,
 	.clkdm_name	= "abe_clkdm",
-	.mpu_irqs	= omap44xx_wd_timer3_irqs,
 	.main_clk	= "sys_32k_ck",
 	.prcm = {
 		.omap4 = {
@@ -3840,32 +3033,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
  * interfaces
  */
 
-static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
-	{
-		.pa_start	= 0x4a204000,
-		.pa_end		= 0x4a2040ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
-/* c2c -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
-	.master		= &omap44xx_c2c_hwmod,
-	.slave		= &omap44xx_c2c_target_fw_hwmod,
-	.clk		= "div_core_ck",
-	.addr		= omap44xx_c2c_target_fw_addrs,
-	.user		= OCP_USER_MPU,
-};
-
-/* l4_cfg -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
-	.master		= &omap44xx_l4_cfg_hwmod,
-	.slave		= &omap44xx_c2c_target_fw_hwmod,
-	.clk		= "l4_div_ck",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main_1 -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
 	.master		= &omap44xx_l3_main_1_hwmod,
@@ -3874,55 +3041,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
-	{
-		.pa_start	= 0x4e000000,
-		.pa_end		= 0x4e0007ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* mpu -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 	.master		= &omap44xx_mpu_hwmod,
 	.slave		= &omap44xx_dmm_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_dmm_addrs,
-	.user		= OCP_USER_MPU,
-};
-
-/* c2c -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
-	.master		= &omap44xx_c2c_hwmod,
-	.slave		= &omap44xx_emif_fw_hwmod,
-	.clk		= "div_core_ck",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
-	.master		= &omap44xx_dmm_hwmod,
-	.slave		= &omap44xx_emif_fw_hwmod,
-	.clk		= "l3_div_ck",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
-	{
-		.pa_start	= 0x4a20c000,
-		.pa_end		= 0x4a20c0ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
-	.master		= &omap44xx_l4_cfg_hwmod,
-	.slave		= &omap44xx_emif_fw_hwmod,
-	.clk		= "l4_div_ck",
-	.addr		= omap44xx_emif_fw_addrs,
 	.user		= OCP_USER_MPU,
 };
 
@@ -3998,32 +3121,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
-	{
-		.pa_start	= 0x44000000,
-		.pa_end		= 0x44000fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 	.master		= &omap44xx_mpu_hwmod,
 	.slave		= &omap44xx_l3_main_1_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_l3_main_1_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-/* c2c_target_fw -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
-	.master		= &omap44xx_c2c_target_fw_hwmod,
-	.slave		= &omap44xx_l3_main_2_hwmod,
-	.clk		= "l3_div_ck",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* debugss -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
 	.master		= &omap44xx_debugss_hwmod,
@@ -4088,21 +3193,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
-	{
-		.pa_start	= 0x44800000,
-		.pa_end		= 0x44801fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l3_main_1 -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 	.master		= &omap44xx_l3_main_1_hwmod,
 	.slave		= &omap44xx_l3_main_2_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_l3_main_2_addrs,
 	.user		= OCP_USER_MPU,
 };
 
@@ -4138,21 +3233,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
-	{
-		.pa_start	= 0x45000000,
-		.pa_end		= 0x45000fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l3_main_1 -> l3_main_3 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 	.master		= &omap44xx_l3_main_1_hwmod,
 	.slave		= &omap44xx_l3_main_3_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_l3_main_3_addrs,
 	.user		= OCP_USER_MPU,
 };
 
@@ -4236,21 +3321,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
-	{
-		.pa_start	= 0x4a102000,
-		.pa_end		= 0x4a10207f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> ocp_wp_noc */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_ocp_wp_noc_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_ocp_wp_noc_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4340,21 +3415,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
-	{
-		.pa_start	= 0x4a304000,
-		.pa_end		= 0x4a30401f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> counter_32k */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_counter_32k_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_counter_32k_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4430,21 +3495,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
-	{
-		.pa_start	= 0x54160000,
-		.pa_end		= 0x54167fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l3_instr -> debugss */
 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
 	.master		= &omap44xx_l3_instr_hwmod,
 	.slave		= &omap44xx_debugss_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_debugss_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4466,41 +3521,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
-	{
-		.name		= "mpu",
-		.pa_start	= 0x4012e000,
-		.pa_end		= 0x4012e07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> dmic */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_dmic_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_dmic_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
-	{
-		.name		= "dma",
-		.pa_start	= 0x4902e000,
-		.pa_end		= 0x4902e07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> dmic (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_dmic_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_dmic_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
@@ -4798,42 +3831,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
-	{
-		.pa_start	= 0x4c000000,
-		.pa_end		= 0x4c0000ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
-/* emif_fw -> emif1 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
-	.master		= &omap44xx_emif_fw_hwmod,
-	.slave		= &omap44xx_emif1_hwmod,
-	.clk		= "l3_div_ck",
-	.addr		= omap44xx_emif1_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
-	{
-		.pa_start	= 0x4d000000,
-		.pa_end		= 0x4d0000ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
-/* emif_fw -> emif2 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
-	.master		= &omap44xx_emif_fw_hwmod,
-	.slave		= &omap44xx_emif2_hwmod,
-	.clk		= "l3_div_ck",
-	.addr		= omap44xx_emif2_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
 	{
 		.pa_start	= 0x4a10a000,
@@ -4852,129 +3849,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
-	{
-		.pa_start	= 0x4a310000,
-		.pa_end		= 0x4a3101ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_gpio1_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_gpio1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
-	{
-		.pa_start	= 0x48055000,
-		.pa_end		= 0x480551ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> gpio2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_gpio2_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_gpio2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
-	{
-		.pa_start	= 0x48057000,
-		.pa_end		= 0x480571ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> gpio3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_gpio3_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_gpio3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
-	{
-		.pa_start	= 0x48059000,
-		.pa_end		= 0x480591ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> gpio4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_gpio4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_gpio4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
-	{
-		.pa_start	= 0x4805b000,
-		.pa_end		= 0x4805b1ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> gpio5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_gpio5_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_gpio5_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
-	{
-		.pa_start	= 0x4805d000,
-		.pa_end		= 0x4805d1ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> gpio6 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_gpio6_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_gpio6_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
-	{
-		.pa_start	= 0x50000000,
-		.pa_end		= 0x500003ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l3_main_2 -> gpmc */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
 	.master		= &omap44xx_l3_main_2_hwmod,
 	.slave		= &omap44xx_gpmc_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_gpmc_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5032,75 +3959,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
-	{
-		.pa_start	= 0x48070000,
-		.pa_end		= 0x480700ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> i2c1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_i2c1_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_i2c1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
-	{
-		.pa_start	= 0x48072000,
-		.pa_end		= 0x480720ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> i2c2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_i2c2_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_i2c2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
-	{
-		.pa_start	= 0x48060000,
-		.pa_end		= 0x480600ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> i2c3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_i2c3_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_i2c3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
-	{
-		.pa_start	= 0x48350000,
-		.pa_end		= 0x483500ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> i2c4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_i2c4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_i2c4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5138,39 +4025,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
 	.user		= OCP_USER_IVA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
-	{
-		.pa_start	= 0x5a000000,
-		.pa_end		= 0x5a07ffff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l3_main_2 -> iva */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
 	.master		= &omap44xx_l3_main_2_hwmod,
 	.slave		= &omap44xx_iva_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_iva_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
-	{
-		.pa_start	= 0x4a31c000,
-		.pa_end		= 0x4a31c07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> kbd */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_kbd_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_kbd_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5228,335 +4095,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
-	{
-		.name		= "mpu",
-		.pa_start	= 0x40122000,
-		.pa_end		= 0x401220ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcbsp1_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcbsp1_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
-	{
-		.name		= "dma",
-		.pa_start	= 0x49022000,
-		.pa_end		= 0x490220ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcbsp1 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcbsp1_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcbsp1_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
-	{
-		.name		= "mpu",
-		.pa_start	= 0x40124000,
-		.pa_end		= 0x401240ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcbsp2_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcbsp2_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
-	{
-		.name		= "dma",
-		.pa_start	= 0x49024000,
-		.pa_end		= 0x490240ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcbsp2 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcbsp2_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcbsp2_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
-	{
-		.name		= "mpu",
-		.pa_start	= 0x40126000,
-		.pa_end		= 0x401260ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcbsp3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcbsp3_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcbsp3_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
-	{
-		.name		= "dma",
-		.pa_start	= 0x49026000,
-		.pa_end		= 0x490260ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcbsp3 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcbsp3_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcbsp3_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
-	{
-		.pa_start	= 0x48096000,
-		.pa_end		= 0x480960ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mcbsp4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mcbsp4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mcbsp4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
-	{
-		.name		= "mpu",
-		.pa_start	= 0x40132000,
-		.pa_end		= 0x4013207f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcpdm */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcpdm_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcpdm_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
-	{
-		.name		= "dma",
-		.pa_start	= 0x49032000,
-		.pa_end		= 0x4903207f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> mcpdm (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_mcpdm_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_mcpdm_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
-	{
-		.pa_start	= 0x48098000,
-		.pa_end		= 0x480981ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mcspi1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mcspi1_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mcspi1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
-	{
-		.pa_start	= 0x4809a000,
-		.pa_end		= 0x4809a1ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mcspi2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mcspi2_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mcspi2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
-	{
-		.pa_start	= 0x480b8000,
-		.pa_end		= 0x480b81ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mcspi3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mcspi3_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mcspi3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
-	{
-		.pa_start	= 0x480ba000,
-		.pa_end		= 0x480ba1ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mcspi4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mcspi4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mcspi4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
-	{
-		.pa_start	= 0x4809c000,
-		.pa_end		= 0x4809c3ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mmc1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mmc1_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mmc1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
-	{
-		.pa_start	= 0x480b4000,
-		.pa_end		= 0x480b43ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mmc2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mmc2_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mmc2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
-	{
-		.pa_start	= 0x480ad000,
-		.pa_end		= 0x480ad3ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mmc3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mmc3_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mmc3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
-	{
-		.pa_start	= 0x480d1000,
-		.pa_end		= 0x480d13ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mmc4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mmc4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mmc4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
-	{
-		.pa_start	= 0x480d5000,
-		.pa_end		= 0x480d53ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> mmc5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_mmc5_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_mmc5_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5568,111 +4247,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
-	{
-		.pa_start	= 0x4a0ad000,
-		.pa_end		= 0x4a0ad01f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_ocp2scp_usb_phy_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_ocp2scp_usb_phy_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
-	{
-		.pa_start	= 0x48243000,
-		.pa_end		= 0x48243fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* mpu_private -> prcm_mpu */
 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
 	.master		= &omap44xx_mpu_private_hwmod,
 	.slave		= &omap44xx_prcm_mpu_hwmod,
 	.clk		= "l3_div_ck",
-	.addr		= omap44xx_prcm_mpu_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
-	{
-		.pa_start	= 0x4a004000,
-		.pa_end		= 0x4a004fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> cm_core_aon */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_cm_core_aon_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_cm_core_aon_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
-	{
-		.pa_start	= 0x4a008000,
-		.pa_end		= 0x4a009fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> cm_core */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_cm_core_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_cm_core_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
-	{
-		.pa_start	= 0x4a306000,
-		.pa_end		= 0x4a307fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> prm */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_prm_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_prm_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
-	{
-		.pa_start	= 0x4a30a000,
-		.pa_end		= 0x4a30a7ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> scrm */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_scrm_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_scrm_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5810,447 +4429,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
-	{
-		.pa_start	= 0x4a318000,
-		.pa_end		= 0x4a31807f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_timer1_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_timer1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
-	{
-		.pa_start	= 0x48032000,
-		.pa_end		= 0x4803207f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> timer2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_timer2_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_timer2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
-	{
-		.pa_start	= 0x48034000,
-		.pa_end		= 0x4803407f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> timer3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_timer3_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_timer3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
-	{
-		.pa_start	= 0x48036000,
-		.pa_end		= 0x4803607f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> timer4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_timer4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_timer4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
-	{
-		.pa_start	= 0x40138000,
-		.pa_end		= 0x4013807f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer5_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer5_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
-	{
-		.pa_start	= 0x49038000,
-		.pa_end		= 0x4903807f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer5 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer5_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer5_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
-	{
-		.pa_start	= 0x4013a000,
-		.pa_end		= 0x4013a07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer6 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer6_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer6_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
-	{
-		.pa_start	= 0x4903a000,
-		.pa_end		= 0x4903a07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer6 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer6_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer6_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
-	{
-		.pa_start	= 0x4013c000,
-		.pa_end		= 0x4013c07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer7 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer7_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer7_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
-	{
-		.pa_start	= 0x4903c000,
-		.pa_end		= 0x4903c07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer7 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer7_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer7_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
-	{
-		.pa_start	= 0x4013e000,
-		.pa_end		= 0x4013e07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer8 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer8_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer8_addrs,
 	.user		= OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
-	{
-		.pa_start	= 0x4903e000,
-		.pa_end		= 0x4903e07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_abe -> timer8 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
 	.master		= &omap44xx_l4_abe_hwmod,
 	.slave		= &omap44xx_timer8_hwmod,
 	.clk		= "ocp_abe_iclk",
-	.addr		= omap44xx_timer8_dma_addrs,
 	.user		= OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
-	{
-		.pa_start	= 0x4803e000,
-		.pa_end		= 0x4803e07f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> timer9 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_timer9_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_timer9_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
-	{
-		.pa_start	= 0x48086000,
-		.pa_end		= 0x4808607f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> timer10 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_timer10_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_timer10_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
-	{
-		.pa_start	= 0x48088000,
-		.pa_end		= 0x4808807f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> timer11 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_timer11_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_timer11_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
-	{
-		.pa_start	= 0x4806a000,
-		.pa_end		= 0x4806a0ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> uart1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_uart1_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_uart1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
-	{
-		.pa_start	= 0x4806c000,
-		.pa_end		= 0x4806c0ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> uart2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_uart2_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_uart2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
-	{
-		.pa_start	= 0x48020000,
-		.pa_end		= 0x480200ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> uart3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_uart3_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_uart3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
-	{
-		.pa_start	= 0x4806e000,
-		.pa_end		= 0x4806e0ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_per -> uart4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
 	.master		= &omap44xx_l4_per_hwmod,
 	.slave		= &omap44xx_uart4_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_uart4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
-	{
-		.pa_start	= 0x4a0a9000,
-		.pa_end		= 0x4a0a93ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> usb_host_fs */
 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_usb_host_fs_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_usb_host_fs_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
-	{
-		.name		= "uhh",
-		.pa_start	= 0x4a064000,
-		.pa_end		= 0x4a0647ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{
-		.name		= "ohci",
-		.pa_start	= 0x4a064800,
-		.pa_end		= 0x4a064bff,
-	},
-	{
-		.name		= "ehci",
-		.pa_start	= 0x4a064c00,
-		.pa_end		= 0x4a064fff,
-	},
-	{}
-};
-
 /* l4_cfg -> usb_host_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_usb_host_hs_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_usb_host_hs_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
-	{
-		.pa_start	= 0x4a0ab000,
-		.pa_end		= 0x4a0ab7ff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> usb_otg_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_usb_otg_hs_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_usb_otg_hs_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
-	{
-		.name		= "tll",
-		.pa_start	= 0x4a062000,
-		.pa_end		= 0x4a063fff,
-		.flags		= ADDR_TYPE_RT
-	},
-	{}
-};
-
 /* l4_cfg -> usb_tll_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
 	.master		= &omap44xx_l4_cfg_hwmod,
 	.slave		= &omap44xx_usb_tll_hs_hwmod,
 	.clk		= "l4_div_ck",
-	.addr		= omap44xx_usb_tll_hs_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
-	{
-		.pa_start	= 0x4a314000,
-		.pa_end		= 0x4a31407f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
 	.master		= &omap44xx_l4_wkup_hwmod,
 	.slave		= &omap44xx_wd_timer2_hwmod,
 	.clk		= "l4_wkup_clk_mux_ck",
-	.addr		= omap44xx_wd_timer2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -6290,14 +4657,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
 	.user		= OCP_USER_SDMA,
 };
 
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
+	.master		= &omap44xx_mpu_hwmod,
+	.slave		= &omap44xx_emif1_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
+	.master		= &omap44xx_mpu_hwmod,
+	.slave		= &omap44xx_emif2_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
-	&omap44xx_c2c__c2c_target_fw,
-	&omap44xx_l4_cfg__c2c_target_fw,
 	&omap44xx_l3_main_1__dmm,
 	&omap44xx_mpu__dmm,
-	&omap44xx_c2c__emif_fw,
-	&omap44xx_dmm__emif_fw,
-	&omap44xx_l4_cfg__emif_fw,
 	&omap44xx_iva__l3_instr,
 	&omap44xx_l3_main_3__l3_instr,
 	&omap44xx_ocp_wp_noc__l3_instr,
@@ -6308,7 +4686,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mmc1__l3_main_1,
 	&omap44xx_mmc2__l3_main_1,
 	&omap44xx_mpu__l3_main_1,
-	&omap44xx_c2c_target_fw__l3_main_2,
 	&omap44xx_debugss__l3_main_2,
 	&omap44xx_dma_system__l3_main_2,
 	&omap44xx_fdif__l3_main_2,
@@ -6364,8 +4741,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l3_main_2__dss_venc,
 	&omap44xx_l4_per__dss_venc,
 	&omap44xx_l4_per__elm,
-	&omap44xx_emif_fw__emif1,
-	&omap44xx_emif_fw__emif2,
 	&omap44xx_l4_cfg__fdif,
 	&omap44xx_l4_wkup__gpio1,
 	&omap44xx_l4_per__gpio2,
@@ -6450,6 +4825,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_wkup__wd_timer2,
 	&omap44xx_l4_abe__wd_timer3,
 	&omap44xx_l4_abe__wd_timer3_dma,
+	&omap44xx_mpu__emif1,
+	&omap44xx_mpu__emif2,
 	NULL,
 };
 
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Wed May 29 12:41:47 2013
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 29 May 2013 12:41:47 -0400
Subject: [GIT PULL] ARM: OMAP5: hwmod, prm/cm data files and updates for
 3.10
In-Reply-To: <20130517172231.GW5600@atomide.com>
References: <1363768852-18125-1-git-send-email-santosh.shilimkar@ti.com>
 <20130401170539.GK10155@atomide.com> <515BA76D.3000302@ti.com>
 <alpine.DEB.2.00.1304031146230.2616@utopia.booyaka.com>
 <515D6020.2030103@ti.com> <20130404165208.GI10155@atomide.com>
 <515DB110.9000503@ti.com> <515F00B8.3000501@ti.com> <5195E380.4040103@ti.com>
 <20130517172231.GW5600@atomide.com>
Message-ID: <51A62FCB.601@ti.com>

On Friday 17 May 2013 01:22 PM, Tony Lindgren wrote:
> * Santosh Shilimkar <santosh.shilimkar at ti.com> [130517 01:02]:
>> Paul, Tony,
>>
>> On Friday 05 April 2013 10:20 PM, Santosh Shilimkar wrote:
>>> On Thursday 04 April 2013 10:27 PM, Santosh Shilimkar wrote:
>>>> On Thursday 04 April 2013 10:22 PM, Tony Lindgren wrote:
>>>>> * Santosh Shilimkar <santosh.shilimkar at ti.com> [130404 04:15]:
>>> [..]
>>>
>>>>> Can't we already trim the am33xx hwmod data after your patches for
>>>>> v3.10 as am33xx is already DT only? Unfortunately we cannot create
>>>>> negative diffstat in other ways for v3.10 merge window as we cannot
>>>>> make omap4 DT only just quite yet.
>>>>>
>>>> Yes we can and I can take a stab it tomorrow. The only thing is I
>>>> might need some support for testing but thats manageable. Will
>>>> take a stab at it tomorrow and if everything goes well, post a
>>>> patch for smae.
>>>>
>>> Patch for the AM33XX to trim is end of the email. Thanks to
>>> Sricharan and Pekon for patch and testing. Looping both
>>> Vaibhav's if they have any objection on the patch.
>>>
>>> Regards,
>>> Santosh
>>>
>>> From b95dd33fe59b8e77727eb3b1717d763bbf9a2893 Mon Sep 17 00:00:00 2001
>>> From: Sricharan R <r.sricharan at ti.com>
>>> Date: Fri, 5 Apr 2013 20:39:12 +0530
>>> Subject: [PATCH] ARM: AM33XX: hwmod data: Clean up the data file
>>>
>> For whatever reason, we again missed the merge window for the subject
>> series, I would like to know your plan on the subject series for
>> at least 3.11. Asking *well in advance* to avoid late merge related
>> discussions.
> 
> Yes, I think we should have now a omap5 hwmod data sized hole coming
> up with conversion of omap4 to be DT only. I'll post those patches
> today for the board file and legacy mux removal for omap4:
> 
> 12 files changed, 52 insertions(+), 3260 deletions(-)
> 
Cool.

> Those coupled with your am33xx hwmod cleanup patch and your omap4
> hwmod cleanup patch should allow us having the omap5 hwmod data
> without making the diffstats look too bad.
>  
>> Thanks to Vaibhav, AM33XX patch is tested and validated with some
>> updates considering upcoming PM support for AM33XX. So that
>> patch will be included in the series.
>>
>> Rajendra will follow up the patchset if there is some re-basing is
>> needed since I will away for few weeks because of travel. 
> 
> OK, well the omap4 hwmod clean-up patch depends on first dropping
> the above mentioned omap4 legacy files.
>  
Have posted the series which includes AM33XX and OMAP4 data
reduction patch as well.

regards,
Santosh



From b-cousson at ti.com  Wed May 29 12:48:12 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 29 May 2013 18:48:12 +0200
Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ
 pin and msecure line
In-Reply-To: <87li6x9325.fsf@linaro.org>
References: <1369423702-31501-1-git-send-email-khilman@linaro.org>
 <20130524200954.GA2344@kahuna> <20130524203231.GA2555@kahuna>
 <87obc0f54r.fsf@linaro.org>
 <CAGo_u6oz1v1J-6z5W-X7CsOmi+7SAMicz1LZTv0sVXhej1DJ2Q@mail.gmail.com>
 <87a9nkf3mu.fsf@linaro.org> <51A5CCA5.7000700@ti.com>
 <87ehcpano0.fsf@linaro.org> <51A60F69.7050203@ti.com>
 <CAGa+x85ZzfX400eEGmTGPzRiC21S83VRiHYj38cqsJLjDF3L7g@mail.gmail.com>
 <51A6269E.2090001@ti.com> <87li6x9325.fsf@linaro.org>
Message-ID: <51A6314C.1080803@ti.com>

On 05/29/2013 06:13 PM, Kevin Hilman wrote:
> "Cousson, Benoit" <b-cousson at ti.com> writes:
> 
>> On 5/29/2013 5:29 PM, Kevin Hilman wrote:
>>>
>>> On May 29, 2013 8:06 AM, "Cousson, Benoit" <b-cousson at ti.com
>>> <mailto:b-cousson at ti.com>> wrote:
>>>  >
>>>  > On 5/29/2013 4:03 PM, Kevin Hilman wrote:
>>>  >>
>>>  >> "Cousson, Benoit" <b-cousson at ti.com <mailto:b-cousson at ti.com>> writes:
>>>  >>
>>>  >> [...]
>>>  >>
>>>  >>>>
>>>  >>>> Let me respin this after some more doc reading.
>>>  >>>
>>>  >>>
>>>  >>> Did you re-spin it already?
>>>  >>
>>>  >>
>>>  >> Yes, v2 is here.
>>>  >>
>>>  >> http://marc.info/?l=linux-omap&m=136944147521955&w=2
>>>  >>
>>>  >> It also needed a rework because the fref_clk0_out pin is also in the
>>>  >> wkup section of the padconf, not core.
>>>  >
>>>  >
>>>  > OK, I'll wait for the v3 then :-)
>>>  >
>>>
>>> Hmm, why? v2 has the wkup changes included.
>>
>> Why? Because of my bad understanding of English :-)
>> I understood: It also needs a rework...
> 
> Re-reading, I wasn't terribly clear.  Sorry for the confusion.
> 
>> Sorry, I'll merge it.
> 
> I was hoping for an Ack from Nishanth since he had some questions about
> it, but with the double checking from you and Grygorii, I think it
> should go in for the -rc cycle.  (also, please add an Ack from Grygorii.)

OK, I'll push the fix to Tony ASAP.

Thanks,
Benoit



From nicolas.pitre at linaro.org  Wed May 29 12:59:06 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 29 May 2013 12:59:06 -0400 (EDT)
Subject: [PATCH 8/8] ARM: vexpress/dcscb: select multi-cluster SMP
 operations
In-Reply-To: <1369845421.3715.76.camel@linaro1.home>
References: <1369374311-21260-1-git-send-email-nicolas.pitre@linaro.org>
 <1369374311-21260-9-git-send-email-nicolas.pitre@linaro.org>
 <1369824504.3715.23.camel@linaro1.home>
 <alpine.LFD.2.03.1305291054150.1918@syhkavp.arg>
 <1369845421.3715.76.camel@linaro1.home>
Message-ID: <alpine.LFD.2.03.1305291250240.1918@syhkavp.arg>

On Wed, 29 May 2013, Jon Medhurst (Tixy) wrote:

> On Wed, 2013-05-29 at 11:17 -0400, Nicolas Pitre wrote:
> > On Wed, 29 May 2013, Jon Medhurst (Tixy) wrote:
> > 
> > > On Fri, 2013-05-24 at 01:45 -0400, Nicolas Pitre wrote:
> > > > When the DCSCB code is successfully probed and initialized, then the
> > > > generic MCPM SPM ops should be used as those operations need to be
> > > > arbitrated through the MCPM layer.
> > > > 
> > > > Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
> > > > ---
> > > >  arch/arm/mach-vexpress/dcscb.c | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > > 
> > > > diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> > > > index 1acc975360..ce3118dc05 100644
> > > > --- a/arch/arm/mach-vexpress/dcscb.c
> > > > +++ b/arch/arm/mach-vexpress/dcscb.c
> > > > @@ -239,6 +239,8 @@ static int __init dcscb_init(void)
> > > >  		return ret;
> > > >  	}
> > > >  
> > > > +	mcpm_smp_set_ops();
> > > > +
> > > 
> > > This is going to change the platform's smp_ops after setup_arch() has
> > > already set them, is that OK and not too late?
> > 
> > Well...  The only methods being invoked before the booting of secondary 
> > CPUs are smp_init_cpus and smp_prepare_cpus.  In the MCPM case they're 
> > both no-ops.
> > 
> > > I ask, because for me, RTSM doesn't boot the secondary CPUs if we rely
> > > on this change to set the smp_ops, but having a hook in setup_arch() to
> > > select instead of the standard vexpress ops does work.
> > 
> > Strange.  That works for me both ways.
> 
> Actually, this patch series works for me if I take it on it's own but
> what should be the same changes in the IKS branch don't. I'll do more
> investigation...

After a closer look, I noticed that I only have 5 out of 8 CPUs online.

So as I suspected, the default prepare_cpus method is not empty and 
causing problems here.  In this case, vexpress_smp_prepare_cpus() is 
calling vexpress_flags_set() sending any waiting CPU into 
versatile_secondary_startup where they'll stay forever (the MCPM code 
expects every new born to go through mcpm_entry_point).

I'll revert to the previous arrangement and we could revisit the 
awkwardness of it later.


Nicolas


From shc_work at mail.ru  Wed May 29 13:05:59 2013
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Wed, 29 May 2013 21:05:59 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSF0gU1BJOiBVbmlmeSBzaW1wbGUgcGxhdGZvcm0gZGF0YSBm?=
 =?UTF-8?B?b3Igc29tZSBjb250cm9sbGVycw==?=
In-Reply-To: <20130529144909.GT3660@sirena.org.uk>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <201305291526.35099.arnd@arndb.de>
 <20130529144909.GT3660@sirena.org.uk>
Message-ID: <1369847158.250798748@f433.i.mail.ru>

> On Wed, May 29, 2013 at 03:26:34PM +0200, Arnd Bergmann wrote:
> > On Wednesday 29 May 2013, Mark Brown wrote:
> 
> > > We probably also want to make
> > > GPIO chip select support a standard thing that's available with every
> > > driver rather than something the driver has to know about but that's a
> > > separate bit of work.
> 
> > That actually seems simpler than doing it in just one driver: if
> > we add a cs_gpio field to spi_board_info, spi_new_device could
> > just copy that information into the new spi_device instead of
> > taking it from master->cs_gpios.
> 
> Yeah, that bit of it is fine and straightforward.  It's slightly more
> work to factor the chip select handling out so that we can implement the
> handling at the appropriate moments in the flow due to the fact that
> it's embedded in the message transfer functions but totally doable.

Initial try to simplify i.MX SPI driver I will send in 5 min.
Patches is untested, so it is only RFC. Platform data still present in
driver but patch migrate driver to using dynamic counter of
chipselects for dt-case. Is it true way now? Comments are welcome.
Thanks.

---

From linus.walleij at stericsson.com  Wed May 29 13:19:49 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 29 May 2013 19:19:49 +0200
Subject: [PATCH] ARM: ux500: use symbolic names for interrupt flags
Message-ID: <1369847989-10017-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This switches to including <dt-bindings/interrupt-controller/irq.h>
and referencing the apropriate flags from there instead of
open-coding the flag numerals everywhere in the ux500 device
trees.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi  | 104 +++++++++++++++++++++--------------------
 arch/arm/boot/dts/href.dtsi    |   5 +-
 arch/arm/boot/dts/snowball.dts |   2 +-
 arch/arm/boot/dts/stuib.dtsi   |   4 +-
 4 files changed, 60 insertions(+), 55 deletions(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 663d3de..b4b542b 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -9,6 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "skeleton.dtsi"
 
 / {
@@ -31,33 +32,33 @@
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0xa0412000 0x1000>;
-			interrupts = <0 13 4>;
+			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 			cache-unified;
 			cache-level = <2>;
 		};
 
 		pmu {
 			compatible = "arm,cortex-a9-pmu";
-			interrupts = <0 7 0x4>;
+			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		timer at a0410600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xa0410600 0x20>;
-			interrupts = <1 13 0x304>;
+			interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
 		};
 
 		rtc at 80154000 {
 			compatible = "arm,rtc-pl031", "arm,primecell";
 			reg = <0x80154000 0x1000>;
-			interrupts = <0 18 0x4>;
+			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		gpio0: gpio at 8012e000 {
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8012e000 0x80>;
-			interrupts = <0 119 0x4>;
+			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -70,7 +71,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8012e080 0x80>;
-			interrupts = <0 120 0x4>;
+			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -83,7 +84,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e000 0x80>;
-			interrupts = <0 121 0x4>;
+			interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -96,7 +97,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e080 0x80>;
-			interrupts = <0 122 0x4>;
+			interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -109,7 +110,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e100 0x80>;
-			interrupts = <0 123 0x4>;
+			interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -122,7 +123,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e180 0x80>;
-			interrupts = <0 124 0x4>;
+			interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -135,7 +136,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8011e000 0x80>;
-			interrupts = <0 125 0x4>;
+			interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -148,7 +149,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8011e080 0x80>;
-			interrupts = <0 126 0x4>;
+			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -161,7 +162,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0xa03fe000 0x80>;
-			interrupts = <0 127 0x4>;
+			interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -179,7 +180,7 @@
 			compatible = "stericsson,db8500-musb",
 				"mentor,musb";
 			reg = <0xa03e0000 0x10000>;
-			interrupts = <0 23 0x4>;
+			interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
 
 			dr_mode = "otg";
@@ -215,7 +216,7 @@
 			compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 			reg = <0x801C0000 0x1000 0x40010000 0x800>;
 			reg-names = "base", "lcpa";
-			interrupts = <0 25 0x4>;
+			interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 
 			#dma-cells = <3>;
 			memcpy-channels = <56 57 58 59 60>;
@@ -225,7 +226,7 @@
 			compatible = "stericsson,db8500-prcmu";
 			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
-			interrupts = <0 47 0x4>;
+			interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			interrupt-controller;
@@ -240,7 +241,8 @@
 			thermal at 801573c0 {
 				compatible = "stericsson,db8500-thermal";
 				reg = <0x801573c0 0x40>;
-				interrupts = <21 0x4>, <22 0x4>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
+					     <22 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 				status = "disabled";
 			 };
@@ -354,21 +356,21 @@
 			ab8500 {
 				compatible = "stericsson,ab8500";
 				interrupt-parent = <&intc>;
-				interrupts = <0 40 0x4>;
+				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 
 				ab8500-rtc {
 					compatible = "stericsson,ab8500-rtc";
-					interrupts = <17 0x4
-					              18 0x4>;
+					interrupts = <17 IRQ_TYPE_LEVEL_HIGH
+						      18 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "60S", "ALARM";
 				};
 
 				ab8500-gpadc {
 					compatible = "stericsson,ab8500-gpadc";
-					interrupts = <32 0x4
-						      39 0x4>;
+					interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+						      39 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "HW_CONV_END", "SW_CONV_END";
 					vddadc-supply = <&ab8500_ldo_tvout_reg>;
 				};
@@ -401,13 +403,13 @@
 
 				ab8500_usb {
 					compatible = "stericsson,ab8500-usb";
-					interrupts = < 90 0x4
-						       96 0x4
-						       14 0x4
-						       15 0x4
-						       79 0x4
-						       74 0x4
-						       75 0x4>;
+					interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
+						       96 IRQ_TYPE_LEVEL_HIGH
+						       14 IRQ_TYPE_LEVEL_HIGH
+						       15 IRQ_TYPE_LEVEL_HIGH
+						       79 IRQ_TYPE_LEVEL_HIGH
+						       74 IRQ_TYPE_LEVEL_HIGH
+						       75 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "ID_WAKEUP_R",
 							  "ID_WAKEUP_F",
 							  "VBUS_DET_F",
@@ -422,8 +424,8 @@
 
 				ab8500-ponkey {
 					compatible = "stericsson,ab8500-poweron-key";
-					interrupts = <6 0x4
-						      7 0x4>;
+					interrupts = <6 IRQ_TYPE_LEVEL_HIGH
+						      7 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 				};
 
@@ -518,7 +520,7 @@
 		i2c at 80004000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80004000 0x1000>;
-			interrupts = <0 21 0x4>;
+			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 			arm,primecell-periphid = <0x180024>;
 
 			#address-cells = <1>;
@@ -531,7 +533,7 @@
 		i2c at 80122000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80122000 0x1000>;
-			interrupts = <0 22 0x4>;
+			interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 			arm,primecell-periphid = <0x180024>;
 
 			#address-cells = <1>;
@@ -544,7 +546,7 @@
 		i2c at 80128000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80128000 0x1000>;
-			interrupts = <0 55 0x4>;
+			interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 			arm,primecell-periphid = <0x180024>;
 
 			#address-cells = <1>;
@@ -557,7 +559,7 @@
 		i2c at 80110000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80110000 0x1000>;
-			interrupts = <0 12 0x4>;
+			interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
 			arm,primecell-periphid = <0x180024>;
 
 			#address-cells = <1>;
@@ -570,7 +572,7 @@
 		i2c at 8012a000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x8012a000 0x1000>;
-			interrupts = <0 51 0x4>;
+			interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 			arm,primecell-periphid = <0x180024>;
 
 			#address-cells = <1>;
@@ -583,7 +585,7 @@
 		ssp at 80002000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x80002000 0x1000>;
-			interrupts = <0 14 0x4>;
+			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -597,7 +599,7 @@
 		uart at 80120000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80120000 0x1000>;
-			interrupts = <0 11 0x4>;
+			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 			       <&dma 13 0 0x0>; /* Logical - MemToDev */
@@ -609,7 +611,7 @@
 		uart at 80121000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80121000 0x1000>;
-			interrupts = <0 19 0x4>;
+			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 			       <&dma 12 0 0x0>; /* Logical - MemToDev */
@@ -621,7 +623,7 @@
 		uart at 80007000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80007000 0x1000>;
-			interrupts = <0 26 0x4>;
+			interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
 			       <&dma 11 0 0x0>; /* Logical - MemToDev */
@@ -633,7 +635,7 @@
 		sdi0_per1 at 80126000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80126000 0x1000>;
-			interrupts = <0 60 0x4>;
+			interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
 			       <&dma 29 0 0x0>; /* Logical - MemToDev */
@@ -645,7 +647,7 @@
 		sdi1_per2 at 80118000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80118000 0x1000>;
-			interrupts = <0 50 0x4>;
+			interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
 			       <&dma 32 0 0x0>; /* Logical - MemToDev */
@@ -657,7 +659,7 @@
 		sdi2_per3 at 80005000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80005000 0x1000>;
-			interrupts = <0 41 0x4>;
+			interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
 			       <&dma 28 0 0x0>; /* Logical - MemToDev */
@@ -669,14 +671,14 @@
 		sdi3_per2 at 80119000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80119000 0x1000>;
-			interrupts = <0 59 0x4>;
+			interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
 		sdi4_per2 at 80114000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80114000 0x1000>;
-			interrupts = <0 99 0x4>;
+			interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
 			       <&dma 42 0 0x0>; /* Logical - MemToDev */
@@ -688,14 +690,14 @@
 		sdi5_per3 at 80008000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80008000 0x1000>;
-			interrupts = <0 100 0x4>;
+			interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
 		msp0: msp at 80123000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80123000 0x1000>;
-			interrupts = <0 31 0x4>;
+			interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 			status = "disabled";
 		};
@@ -703,7 +705,7 @@
 		msp1: msp at 80124000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80124000 0x1000>;
-			interrupts = <0 62 0x4>;
+			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 			status = "disabled";
 		};
@@ -712,7 +714,7 @@
 		msp2: msp at 80117000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80117000 0x1000>;
-			interrupts = <0 98 0x4>;
+			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 			status = "disabled";
 		};
@@ -720,7 +722,7 @@
 		msp3: msp at 80125000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80125000 0x1000>;
-			interrupts = <0 62 0x4>;
+			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 			status = "disabled";
 		};
@@ -759,7 +761,7 @@
 		cryp at a03cb000 {
 			compatible = "stericsson,ux500-cryp";
 			reg = <0xa03cb000 0x1000>;
-			interrupts = <0 15 0x4>;
+			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 
 			v-ape-supply = <&db8500_vape_reg>;
 		};
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index 2c21626..0485519 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -9,6 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "dbx5x0.dtsi"
 
 / {
@@ -45,14 +46,14 @@
 				compatible = "tc3589x";
 				reg = <0x42>;
 				interrupt-parent = <&gpio6>;
-				interrupts = <25 0x1>;
+				interrupts = <25 IRQ_TYPE_EDGE_RISING>;
 
 				interrupt-controller;
 				#interrupt-cells = <2>;
 
 				tc3589x_gpio: tc3589x_gpio {
 					compatible = "tc3589x-gpio";
-					interrupts = <0 0x1>;
+					interrupts = <0 IRQ_TYPE_EDGE_RISING>;
 
 					interrupt-controller;
 					#interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index c0a34a6..06982dd 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -105,7 +105,7 @@
 			ethernet at 0 {
 				compatible = "smsc,lan9115";
 				reg = <0 0x10000>;
-				interrupts = <12 0x1>;
+				interrupts = <12 IRQ_TYPE_EDGE_RISING>;
 				interrupt-parent = <&gpio4>;
 				vdd33a-supply = <&en_3v3_reg>;
 				vddvario-supply = <&db8500_vape_reg>;
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 0fdb259..b47b62a 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -9,13 +9,15 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
 	soc {
 		i2c at 80004000 {
 			stmpe1601: stmpe1601 at 40 {
 				compatible = "st,stmpe1601";
 				reg = <0x40>;
-				interrupts = <26 0x2>;
+				interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
 				interrupt-parent = <&gpio6>;
 				interrupt-controller;
 
-- 
1.7.11.3



From Russ.Dill at ti.com  Wed May 29 13:23:41 2013
From: Russ.Dill at ti.com (Russ Dill)
Date: Wed, 29 May 2013 10:23:41 -0700
Subject: ARM hibernation / suspend-to-disk
In-Reply-To: <20130529081005.GA25561@hal>
References: <20130529081005.GA25561@hal>
Message-ID: <51A6399D.4090606@ti.com>

On 05/29/2013 01:10 AM, Jan Glauber wrote:
> Hi list,
> 
> what's the status of suspend-to-disk on ARM? The most recent discussion I
> found is:
> http://lists.linuxfoundation.org/pipermail/linux-pm/2012-November/034997.html
> 
> with no replies at all. Is anyone still working on that? Anyone got it running?
> 
> I tried the patch above (on top of LTS 3.4) and got stuck forever, the last
> thing on the console was:
> 
> root at omap5:/sys/power# echo disk > state
> [ 2015.641540] PM: Syncing filesystems ... done.
> [ 2015.666870] PM: Preallocating image memory... done (allocated 16957 pages)
> [ 2016.062011] PM: Allocated 67828 kbytes in 0.38 seconds (178.49 MB/s)
> 
> Any hint how to debug that?
> 
> thanks,
> Jan
> 

Because of the nature of omap5 PM, you'd need omap5 specific support in
order for this to work. Specifically, there are a number of assumptions
about certain power domains never losing state. You can take a look at
the work I did to get this working on am335x here:

https://github.com/russdill/linux/commits/arm-hibernation-am33xx

For ARM hibernation support to get merged, there needs to be at least
one platform that supports it. the am335x code I have is not ready as it
still relies on PM patchsets that have not yet themselves been merged.


From marvin24 at gmx.de  Wed May 29 13:30:24 2013
From: marvin24 at gmx.de (Marc Dietrich)
Date: Wed, 29 May 2013 19:30:24 +0200
Subject: [PATCH] ARM: tegra: rebuild tegra_defconfig
In-Reply-To: <51A61EEC.5040300@wwwdotorg.org>
References: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>
 <2234363.J239kID5LN@fb07-iapwap2.physik.uni-giessen.de>
 <51A61EEC.5040300@wwwdotorg.org>
Message-ID: <7367180.OaP1fIIt8z@ax5200p>

On Wednesday 29 May 2013 09:29:48 Stephen Warren wrote:
> On 05/29/2013 07:38 AM, Marc Dietrich wrote:
> > Am Dienstag, 28. Mai 2013, 15:30:29 schrieb Stephen Warren:
> >> On 05/28/2013 11:26 AM, Stephen Warren wrote:
> >>> From: Stephen Warren <swarren at nvidia.com>
> >>> 
> >>> This simply rebuilds tegra_defconfig on top of next-20130520. As such,
> >>> it
> >>> should introduce no changes; simply moving entries around due to Kconfig
> >>> ordering changes. The apparent exceptions are:
> >>> 
> >>> AUTO_ZRELADDR: Selected by ARM multi-platform support.
> >>> MTD_CHAR: Removed in Kconfig.
> >>> 
> >>> This should make it easier to create future defconfig patches on top of
> >>> linux-next, since all the extraneous diffs have been removed. It also
> >>> makes it more likely that once 3.12 comes around, this defconfig will
> >>> already match what's required there.
> >> 
> >> I've applied this (squashed it into) Tegra's for-3.11/defconfig branch.
> > 
> > wouldn't it make more sense to apply such a patch just before the merge
> > window closes (or better after some release candidate)?
> 
> Perhaps. It probably also depends a lot on when Kconfig changes get
> applied in other areas as far as when it makes sense. I deferred it this
> time around in order to pick up some tegra_defconfig changes that made
> it into 3.10-rc3.

ok, nice.

> > This way we would have a
> > better chance to have a zero diff between defconfig and tegra_defconfig,
> > e.g. not like 3.10 is now.
> 
> I don't understand this; what is "defconfig" if not "tegra_defconfig"?

defconfig: make tegra_defconfig; make saveconfig

diff -u tegra_defconfig defconfig

Marc


From linus.walleij at stericsson.com  Wed May 29 13:32:22 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 29 May 2013 19:32:22 +0200
Subject: [PATCH] ARM: ux500: cut chip-select GPIOs from SSP device
Message-ID: <1369848742-10451-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

What GPIO pin is used with which device on the SSP/SPI bus
is as board-specific as it gets, so it does not belong here
in the core SoC file, and it is disabled so it doesn't hurt
to delete this.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index b4b542b..12f36d4 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -589,11 +589,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-
-			// Add one of these for each child device
-			cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
-				    &gpio6 22 0x4 &gpio7 0 0x4>;
-
 		};
 
 		uart at 80120000 {
-- 
1.7.11.3



From catalin.marinas at arm.com  Wed May 29 13:33:28 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 29 May 2013 18:33:28 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <alpine.LFD.2.03.1305291230160.1918@syhkavp.arg>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130523104303.GC16722@arm.com>
 <alpine.LFD.2.03.1305242350220.1918@syhkavp.arg>
 <20130528095528.GA14329@arm.com>
 <alpine.LFD.2.03.1305281340240.1918@syhkavp.arg>
 <20130529103728.GG17767@MacBook-Pro.local>
 <alpine.LFD.2.03.1305291038220.1918@syhkavp.arg>
 <alpine.LFD.2.03.1305291230160.1918@syhkavp.arg>
Message-ID: <20130529173328.GS17767@MacBook-Pro.local>

On Wed, May 29, 2013 at 05:32:50PM +0100, Nicolas Pitre wrote:
> On Wed, 29 May 2013, Nicolas Pitre wrote:
> 
> > On Wed, 29 May 2013, Catalin Marinas wrote:
> > 
> > > On Tue, May 28, 2013 at 06:52:27PM +0100, Nicolas Pitre wrote:
> > > > On Tue, 28 May 2013, Catalin Marinas wrote:
> > > > 
> > > > > On Sat, May 25, 2013 at 04:53:19AM +0100, Nicolas Pitre wrote:
> > > > > > On Thu, 23 May 2013, Catalin Marinas wrote:
> > > > > > 
> > > > > > > An issue is that for kunmap_atomic() && VIVT we flush the same page
> > > > > > > twice. I don't think we should remove the cache flushing in
> > > > > > > __kunmap_atomic() for VIVT since not all kunmap_atomic() calls require
> > > > > > > flush_kernel_dcache_page() (unless we just assume that highmem && vivt
> > > > > > > don't work together).
> > > > > > 
> > > > > > VIVT and highmem do work together.  Highmem for ARM was in fact 
> > > > > > developed on such a platform.
> > > > > 
> > > > > Thanks for confirming. Do you remember why kunmap() doesn't (need to)
> > > > > flush the cache alias (for VIVT)? Or if it does, where?
> > > > 
> > > > kunmap() calls kunmap_high() which actually does not unmap anything but 
> > > > only decrement a use count.  The page is kept around in case it is 
> > > > kmap()'d again, in which case the kmap() will be almost free and the 
> > > > page still warm.
> > > > 
> > > > It is only when the kmap() for a new page runs out of free pkmap  
> > > > entries that the unused but still mapped pages are unmapped.  This 
> > > > unmapping is done in flush_all_zero_pkmaps() where all the unused pages 
> > > > are all unmapped at once.  The cache for all those pages is flushed with 
> > > > flush_cache_kmaps() which on ARM maps to flush_cache_all() when the 
> > > > cache is VIVT.
> > > 
> > > Thanks for clarification Nico. So if kmap_high_get() returns NULL, there
> > > are no high aliases left in the cache.
> > 
> > Exact.
> 
> Just to be clear, this is true for VIVT only.
> Unmapped highmem pages can still be cached with VIPT.

Indeed.

-- 
Catalin


From balbi at ti.com  Wed May 29 13:37:15 2013
From: balbi at ti.com (Felipe Balbi)
Date: Wed, 29 May 2013 20:37:15 +0300
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <CADApbegejeoxc4TmjvsPse=54durFym2cfDRdg9RviDZJ2HAFg@mail.gmail.com>
References: <1368424303-10629-5-git-send-email-chao.xie@marvell.com>
 <Pine.LNX.4.44L0.1305131012090.1389-100000@iolanthe.rowland.org>
 <20130528162415.GA28253@arwen.pp.htv.fi>
 <CADApbegejeoxc4TmjvsPse=54durFym2cfDRdg9RviDZJ2HAFg@mail.gmail.com>
Message-ID: <20130529173715.GB21290@arwen.pp.htv.fi>

Hi,

On Wed, May 29, 2013 at 11:58:01AM +0800, Chao Xie wrote:
> On Wed, May 29, 2013 at 12:24 AM, Felipe Balbi <balbi at ti.com> wrote:
> > Hi,
> >
> > On Mon, May 13, 2013 at 10:13:44AM -0400, Alan Stern wrote:
> >> On Mon, 13 May 2013, Chao Xie wrote:
> >>
> >> > Originaly, ehci driver will call the callbacks in platform data
> >> > for PHY initialization and shut down.
> >> > With PHY driver, it will call the APIs provided by PHY driver
> >> > for PHY initialization and shutdown. It removes the callbacks
> >> > in platform data, and at same time it removes one block in the
> >> > way of enabling device tree for ehci driver.
> >>
> >> I wonder if this is the sort of thing that should be handled in
> >> ehci-hcd.c rather than in all the different platform glue drivers.
> >>
> >> Felipe, what do you think?  Are the required actions now sufficiently
> >> generic that a single source file can take care of them?
> >
> > Sorry for the delay, was on business trip and now on vacations. Anyway,
> > I agree with you. Our PHY layer should be generic enough that it should
> > be usable by ehci-hcd itself. If we have any missing method, let's add
> > it generically.
> >
> So what are your idea about making the PHY layer more generic? How
> ehci-hcd will make use of PHY layer?


on probe grab the phy and initialize it. On suspend/resume,
suspend/resume the PHY and so on. Whatever you were going to do on your
ehci glue, do it on generic ehci-hcd.

-- 
balbi
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From mturquette at linaro.org  Wed May 29 13:39:38 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 10:39:38 -0700
Subject: [PATCH] clk: add specified-rate clock
In-Reply-To: <1368189862-17119-1-git-send-email-james.hogan@imgtec.com>
References: <1368189862-17119-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130529173938.6058.96646@quantum>

Quoting James Hogan (2013-05-10 05:44:22)
> The frequency of some SoC's external oscillators (for example TZ1090's
> XTAL1) are configured by the board using pull-ups/pull-downs of
> configuration pins, the logic values of which are automatically latched
> on reset and available in an SoC register. Add a generic clock component
> and DT bindings to handle this.
> 
> It behaves similar to a fixed rate clock (read-only), except it needs
> information about a register field (reg, shift, width), and the
> clock-frequency is a mapping from register field values to clock
> frequencies.
> 

James,

Thanks for sending this!  It looks mostly good and is a useful clock
type to support.  Comments below.

<snip>
> diff --git a/Documentation/devicetree/bindings/clock/specified-clock.txt b/Documentation/devicetree/bindings/clock/specified-clock.txt
> new file mode 100644
> index 0000000..b36ccf9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/specified-clock.txt
> @@ -0,0 +1,39 @@
> +Binding for fixed-rate clock sources with readable configuration.
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible         : Shall be "specified-clock".
> +- #clock-cells       : From common clock binding; shall be set to 0.
> +- reg                : Address of configuration register.
> +- shift              : Shift of config value field in configuration register.
> +- width              : Width of config value field in configuration register.

It might be better to make this a mask instead of the width.  We have
already hit this issue with the mux table on Nvidia where arbitrary
masks are necessary.  Mask + shift probably helps future-proof us a bit.

The rest of the binding looks good.

<snip>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index e7f7fe9..1343179 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)        += clk-fixed-rate.o
>  obj-$(CONFIG_COMMON_CLK)       += clk-gate.o
>  obj-$(CONFIG_COMMON_CLK)       += clk-mux.o
>  obj-$(CONFIG_COMMON_CLK)       += clk-composite.o
> +obj-$(CONFIG_COMMON_CLK)       += clk-specified-rate.o

One thing that does occur to me is that this could potentially be
combined with the fixed-rate clock.  If the properties for a specified
rate existing in the DT data then this code applies, otherwise the
existing fixed-rate code is used.  I don't have a strong opinion about
combining the code, but something to consider.

<snip>
> +#ifdef CONFIG_OF
> +/**
> + * of_specified_clk_setup() - Setup function for specified fixed rate clock
> + */
> +void __init of_specified_clk_setup(struct device_node *node)
> +{
> +       struct clk *clk;
> +       const char *clk_name = node->name;
> +       u32 shift, width, rate;
> +       void __iomem *reg;
> +       int len, num_rates, i;
> +       struct property *prop;
> +       struct clk_specified_rate_entry *rates;
> +       const __be32 *p;
> +
> +       of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +       if (of_property_read_u32(node, "shift", &shift)) {
> +               pr_err("%s(%s): could not read shift property\n",
> +                      __func__, clk_name);
> +               return;
> +       }
> +
> +       if (of_property_read_u32(node, "width", &width)) {
> +               pr_err("%s(%s): could not read width property\n",
> +                      __func__, clk_name);
> +               return;
> +       }
> +
> +       reg = of_iomap(node, 0);
> +       if (!reg) {
> +               pr_err("%s(%s): of_iomap failed\n",
> +                      __func__, clk_name);
> +               return;
> +       }
> +
> +       /* check clock-frequency exists */
> +       prop = of_find_property(node, "clock-frequency", &len);
> +       if (!prop) {
> +               pr_err("%s(%s): could not find clock-frequency property\n",
> +                      __func__, clk_name);
> +               goto err_iounmap;
> +       }
> +
> +       if (len & (sizeof(u32)*2 - 1)) {
> +               pr_err("%s(%s): clock-frequency has invalid size of %d bytes\n",
> +                      __func__, clk_name, len);
> +               goto err_iounmap;
> +       }
> +       num_rates = len / (sizeof(*rates)*2);

This tripped me up for a few minutes.  I think it is a bit weird to
count bytes as a way to validate length and determine the number of
pairs.

I have written a binding for mux clocks which can have a table of
parents and the code below shows how I parsed the table:

+       u32 pair[2];
+
+       table_size = of_count_phandle_with_args(node, "table", "#clock-cells");
+
+       if (table_size < 1)
+               return NULL;
+
+       table = kzalloc(sizeof(struct clk_div_table) * table_size, GFP_KERNEL);
+       if (!table) {
+               pr_err("%s: unable to allocate memory for %s table\n", __func__, node->name);
+               return NULL;
+       }
+
+       for (i = 0; i < table_size; i++) {
+               if (!of_property_read_u32_array(node, "table", pair, ARRAY_SIZE(pair))) {
+                       table[i].val = pair[0];
+                       table[i].div = pair[1];
+               }
+       }

I'll be posting the mux-clock binding soon :-)

Regards,
Mike


From plagnioj at jcrosoft.com  Wed May 29 13:35:38 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 29 May 2013 19:35:38 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
Message-ID: <20130529173538.GC23899@game.jcrosoft.org>

On 16:36 Wed 29 May     , Richard Genoud wrote:
> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> > Today we mix pdata and drivers data in the struct atmel_lcdfb_info
> > Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
> >
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: linux-fbdev at vger.kernel.org
> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> > Cc: Andrew Morton <akpm at linux-foundation.org>
> > Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> > ---
> >  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
> >  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
> >  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
> >  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
> >  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
> >  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
> >  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
> >  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
> >  arch/arm/mach-at91/board.h                  |    4 +-
> >  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
> >  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
> >  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
> >  arch/avr32/boards/atstk1000/setup.c         |    2 +-
> >  arch/avr32/boards/favr-32/setup.c           |    2 +-
> >  arch/avr32/boards/hammerhead/setup.c        |    2 +-
> >  arch/avr32/boards/merisc/display.c          |    2 +-
> >  arch/avr32/boards/mimc200/setup.c           |    4 +-
> >  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
> >  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
> >  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
> >  include/video/atmel_lcdc.h                  |   24 +------
> >  21 files changed, 109 insertions(+), 101 deletions(-)
> >
> [snip]
> > diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> > index c1a2914..98733cd4 100644
> > --- a/drivers/video/atmel_lcdfb.c
> > +++ b/drivers/video/atmel_lcdfb.c
> > @@ -20,12 +20,45 @@
> >  #include <linux/gfp.h>
> >  #include <linux/module.h>
> >  #include <linux/platform_data/atmel.h>
> > +#include <video/of_display_timing.h>
> >
> >  #include <mach/cpu.h>
> >  #include <asm/gpio.h>
> >
> >  #include <video/atmel_lcdc.h>
> >
> > +struct atmel_lcdfb_config {
> > +       bool have_alt_pixclock;
> > +       bool have_hozval;
> > +       bool have_intensity_bit;
> > +};
> > +
> > + /* LCD Controller info data structure, stored in device platform_data */
> > +struct atmel_lcdfb_info {
> > +       spinlock_t              lock;
> > +       struct fb_info          *info;
> > +       void __iomem            *mmio;
> > +       int                     irq_base;
> > +       struct work_struct      task;
> > +
> > +       unsigned int            smem_len;
> > +       struct platform_device  *pdev;
> > +       struct clk              *bus_clk;
> > +       struct clk              *lcdc_clk;
> > +
> > +       struct backlight_device *backlight;
> > +       u8                      bl_power;
> > +       bool                    lcdcon_pol_negative;
> I think lcdcon_pol_negative should be part of pdata, because it really
> depends on how the PWM is wired on the board.
> 

maybe but no one mainline use it on any pdata for non-dt boars
so I did not want to expose it

Best Regatgards,
J.
> 
> Regards,
> Richard.


From swarren at wwwdotorg.org  Wed May 29 13:42:19 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 11:42:19 -0600
Subject: [PATCH] ARM: tegra: rebuild tegra_defconfig
In-Reply-To: <7367180.OaP1fIIt8z@ax5200p>
References: <1369761972-31986-1-git-send-email-swarren@wwwdotorg.org>
 <2234363.J239kID5LN@fb07-iapwap2.physik.uni-giessen.de>
 <51A61EEC.5040300@wwwdotorg.org> <7367180.OaP1fIIt8z@ax5200p>
Message-ID: <51A63DFB.3010206@wwwdotorg.org>

On 05/29/2013 11:30 AM, Marc Dietrich wrote:
> On Wednesday 29 May 2013 09:29:48 Stephen Warren wrote:
>> On 05/29/2013 07:38 AM, Marc Dietrich wrote:
>>> Am Dienstag, 28. Mai 2013, 15:30:29 schrieb Stephen Warren:
>>>> On 05/28/2013 11:26 AM, Stephen Warren wrote:
>>>>> From: Stephen Warren <swarren at nvidia.com>
>>>>>
>>>>> This simply rebuilds tegra_defconfig on top of next-20130520. As such,
>>>>> it
>>>>> should introduce no changes; simply moving entries around due to Kconfig
>>>>> ordering changes. The apparent exceptions are:
...
>>> This way we would have a
>>> better chance to have a zero diff between defconfig and tegra_defconfig,
>>> e.g. not like 3.10 is now.
>>
>> I don't understand this; what is "defconfig" if not "tegra_defconfig"?
> 
> defconfig: make tegra_defconfig; make saveconfig
> 
> diff -u tegra_defconfig defconfig

Oh right. Yes, if you do that in the for-3.11/defconfig branch itself,
there will be diffs.

That will always be true; that branch won't have any of the new
drivers/features that will be added in linux-next and the next mainline
kernel, so at the very least you'd end up removing some options doing that.

I expect most people editing defconfig will be doing it based on some
linux-next version rather than right on top of for-3.11/defconfig, so
they can pick up, enable, and test new drivers or features. If you run
the commands above in next-20130529, there should be a zero diff (unless
someone made some Kconfig changes between
next-20130528 and next-20130529 anyway).


From balbi at ti.com  Wed May 29 13:41:44 2013
From: balbi at ti.com (Felipe Balbi)
Date: Wed, 29 May 2013 20:41:44 +0300
Subject: [PATCH v2] usb: musb: fix clock naming
In-Reply-To: <CAGm1_ks7Y8n1xKA=qiCCFcxgydRiyeJS08A8TPnbnEEmkJxVyg@mail.gmail.com>
References: <1369725661-3114-1-git-send-email-yegorslists@googlemail.com>
 <20130528173637.GE15794@arwen.pp.htv.fi>
 <CAGm1_ks7Y8n1xKA=qiCCFcxgydRiyeJS08A8TPnbnEEmkJxVyg@mail.gmail.com>
Message-ID: <20130529174144.GE21290@arwen.pp.htv.fi>

On Wed, May 29, 2013 at 12:06:52PM +0200, Yegor Yefremov wrote:
> On Tue, May 28, 2013 at 7:36 PM, Felipe Balbi <balbi at ti.com> wrote:
> > On Tue, May 28, 2013 at 09:21:01AM +0200, yegorslists at googlemail.com wrote:
> >> From: Yegor Yefremov <yegorslists at googlemail.com>
> >>
> >> 'ick' was changed to 'hsotgusb_ick'
> >> 'fck' was changed to 'hsotgusb_fck'
> >>
> >> Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
> >> Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
> >
> > NAK. Fix your clock data.
> 
> Do you mean here arch/arm/mach-omap2/cclock3xxx_data.c?

yes

-- 
balbi
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From richard.genoud at gmail.com  Wed May 29 13:44:56 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 29 May 2013 19:44:56 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <20130529173538.GC23899@game.jcrosoft.org>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
Message-ID: <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>

2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> On 16:36 Wed 29 May     , Richard Genoud wrote:
>> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> > Today we mix pdata and drivers data in the struct atmel_lcdfb_info
>> > Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
>> >
>> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> > Cc: linux-fbdev at vger.kernel.org
>> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>> > Cc: Andrew Morton <akpm at linux-foundation.org>
>> > Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
>> > ---
>> >  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
>> >  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
>> >  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
>> >  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
>> >  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
>> >  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
>> >  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
>> >  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
>> >  arch/arm/mach-at91/board.h                  |    4 +-
>> >  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
>> >  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
>> >  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
>> >  arch/avr32/boards/atstk1000/setup.c         |    2 +-
>> >  arch/avr32/boards/favr-32/setup.c           |    2 +-
>> >  arch/avr32/boards/hammerhead/setup.c        |    2 +-
>> >  arch/avr32/boards/merisc/display.c          |    2 +-
>> >  arch/avr32/boards/mimc200/setup.c           |    4 +-
>> >  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
>> >  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
>> >  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
>> >  include/video/atmel_lcdc.h                  |   24 +------
>> >  21 files changed, 109 insertions(+), 101 deletions(-)
>> >
>> [snip]
>> > diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
>> > index c1a2914..98733cd4 100644
>> > --- a/drivers/video/atmel_lcdfb.c
>> > +++ b/drivers/video/atmel_lcdfb.c
>> > @@ -20,12 +20,45 @@
>> >  #include <linux/gfp.h>
>> >  #include <linux/module.h>
>> >  #include <linux/platform_data/atmel.h>
>> > +#include <video/of_display_timing.h>
>> >
>> >  #include <mach/cpu.h>
>> >  #include <asm/gpio.h>
>> >
>> >  #include <video/atmel_lcdc.h>
>> >
>> > +struct atmel_lcdfb_config {
>> > +       bool have_alt_pixclock;
>> > +       bool have_hozval;
>> > +       bool have_intensity_bit;
>> > +};
>> > +
>> > + /* LCD Controller info data structure, stored in device platform_data */
>> > +struct atmel_lcdfb_info {
>> > +       spinlock_t              lock;
>> > +       struct fb_info          *info;
>> > +       void __iomem            *mmio;
>> > +       int                     irq_base;
>> > +       struct work_struct      task;
>> > +
>> > +       unsigned int            smem_len;
>> > +       struct platform_device  *pdev;
>> > +       struct clk              *bus_clk;
>> > +       struct clk              *lcdc_clk;
>> > +
>> > +       struct backlight_device *backlight;
>> > +       u8                      bl_power;
>> > +       bool                    lcdcon_pol_negative;
>> I think lcdcon_pol_negative should be part of pdata, because it really
>> depends on how the PWM is wired on the board.
>>
>
> maybe but no one mainline use it on any pdata for non-dt boars
> so I did not want to expose it
Well, at least, I'm using it :)
(and I guess that Andreas is using it also, otherwise he wouldn't have
introduce it !)


Best regards,
Richard.


From dave.martin at linaro.org  Wed May 29 13:47:46 2013
From: dave.martin at linaro.org (Dave Martin)
Date: Wed, 29 May 2013 18:47:46 +0100
Subject: VDSO for arm 32bit
In-Reply-To: <alpine.LFD.2.03.1305290955390.1918@syhkavp.arg>
References: <634BB1CFA60ED14386C17849392C3EB202E52C9C0A@HICGWSEX01.ad.harman.com>
 <20899.25935.838288.45383@pilspetsen.it.uu.se>
 <634BB1CFA60ED14386C17849392C3EB202E52C9E87@HICGWSEX01.ad.harman.com>
 <20130528092313.GA10474@mudshark.cambridge.arm.com>
 <alpine.LFD.2.03.1305281415040.1918@syhkavp.arg>
 <20130529090850.GB13095@mudshark.cambridge.arm.com>
 <alpine.LFD.2.03.1305290955390.1918@syhkavp.arg>
Message-ID: <20130529174746.GA2224@linaro.org>

On Wed, May 29, 2013 at 10:01:40AM -0400, Nicolas Pitre wrote:
> On Wed, 29 May 2013, Will Deacon wrote:
> 
> > On Tue, May 28, 2013 at 07:19:00PM +0100, Nicolas Pitre wrote:
> > > On Tue, 28 May 2013, Will Deacon wrote:
> > > > Be careful here. I had a crack at a gtod implementation for the vectors page
> > > > in the past, but decided to drop it because it quickly became a maintenance
> > > > nightmare. Since the layout of the vectors page must be fixed (as userspace
> > > > jumps to the absolute addresses for the helpers), having large, complicated
> > > > functions (which gtod does become as you quickly start using the stack to
> > > > store all of the shared state with the kernel) means that you can quickly
> > > > back yourself into a corner where the layout of the code cannot change
> > > > without breaking the ABI.
> > > 
> > > Note that only the entry point is fixed.  The layout of the code is not.  
> > > So you may well branch anywhere else within the vector page if the code 
> > > is more complex than a few instructions.
> > 
> > Sure, it may be possible simply to have branches in the kuser slots and then
> > reserve a chunk at the other end of the vectors page where the actual
> > implementation can go.
> > 
> > > > On top of that, new clock types are added more often than you might think
> > > > (not to mention bug fixes in the implementation itself), and you end up in
> > > > a horrible situation where you'd end up deprecating one implementation and
> > > > adding gettimeofday2 or something equally nasty at a different offset.
> > > 
> > > That is equally valid for a vdso.
> > 
> > Sorry, I wasn't clear. My point was that you can change the layout of a vdso
> > without breaking anything, since the dynamic loader resolves the entry
> > points. It relates back to what I said above -- you need to be careful about
> > how you lay the stuff out in memory.
> > 
> > Perhaps the gtod code won't end up being that big. It's around ~500 bytes on
> > arm64, but that's without any stack usage.
> 
> That's still fairly large.
> 
> > Come to think of it, is there any
> > reason why we can't just map an additional vectors page after the one we
> > currently have?
> 
> That certainly can be done if necessary.  Some copy_page implementations 
> do use some of the address space above the vector page for temporary 
> page mapping so some care not to create conflicts would be required.

In theory, we could have a VDSO wrapping the vectors page.  This could allow
the existing kuser helpers to be looked up by ELF symbol as well as the well-
known address.  New functions don't necessarily need to have a well-known
address at all -- they might only be visible as ELF symbols, since there is
no need to offer a backwards-compatible ABI for new functions.

Alternatively, we could have a VDSO which is separate from the vectors
page, exporting only the new functionality, with the vectors page remaining
as before.

Whether or not adding a VDSO brings enough benefit to make it worthwhile
is a separate discussion, though.

Cheers
---Dave


From balbi at ti.com  Wed May 29 13:55:08 2013
From: balbi at ti.com (Felipe Balbi)
Date: Wed, 29 May 2013 20:55:08 +0300
Subject: [GIT PULL] ARM: tegra: DT-related fixes needed by the USB tree
In-Reply-To: <20130528174704.GH15794@arwen.pp.htv.fi>
References: <1368831045-19105-1-git-send-email-swarren@wwwdotorg.org>
 <51A4E62D.7020206@wwwdotorg.org>
 <20130528174704.GH15794@arwen.pp.htv.fi>
Message-ID: <20130529175508.GF21290@arwen.pp.htv.fi>

Hi,

On Tue, May 28, 2013 at 08:47:04PM +0300, Felipe Balbi wrote:
> On Tue, May 28, 2013 at 11:15:25AM -0600, Stephen Warren wrote:
> > On 05/17/2013 04:50 PM, Stephen Warren wrote:
> > > Felipe, (and Alan, Greg),
> > > 
> > > These are the changes from the Tegra tree that need to be merged
> > > before the Tegra USB driver patches 4-8 from Venu can be applied. Recall
> > > that we had previously agreed on this approach for v3.9, but Venu's
> > > patches didn't end up being ready until now, unfortunately. I note
> > > that Venu's patches affect both the Tegra USB and PHY drivers.
> > 
> > Felipe, do you know when you plan to pull this into the USB tree, and
> > apply Venu's patches? Thanks.
> 
> got 35 commits testing right now. This pull is in my list for tomorrow.
> 
> sorry for the delay, have been on a trip for the last 3 weeks and now
> I'm catching up with emails during my vacations (next 2 weeks).

the tag is not pushed to where you pointed me to. Please make sure to
git push it.

$ git fetch git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tag tegra-for-3.11-deps-for-usb
fatal: Couldn't find remote ref refs/tags/tegra-for-3.11-deps-for-usb

-- 
balbi
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From dianders at chromium.org  Wed May 29 13:58:02 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed, 29 May 2013 10:58:02 -0700
Subject: [PATCH v2 1/5] clk: samsung: Use clk->base instead of directly
 using clk->con0 for PLL3xxx
In-Reply-To: <1369834677-20312-2-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
 <1369834677-20312-2-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=XAc0R4gHrogYE3gAp5ANWFfo2UT0LCkhn3eVV0b5ukxQ@mail.gmail.com>

Vikas / Yadwinder,

On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>
> To factor out possible common code, this patch unifies the clk strutures used
> for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.
>
> Reviewed-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c    |   10 ++++---
>  drivers/clk/samsung/clk-exynos5250.c |   14 ++++-----
>  drivers/clk/samsung/clk-pll.c        |   54 ++++++++++++++++++----------------
>  drivers/clk/samsung/clk-pll.h        |    4 +--
>  4 files changed, 44 insertions(+), 38 deletions(-)

I've run with this patch atop our CCF backport on 3.8 on on
exynos5250-snow.  It works and looks good to me.  We're planning to
put this patch into our tree at
<https://gerrit.chromium.org/gerrit/#/c/56740>.

Reviewed-by: Doug Anderson <dianders at chromium.org>
Tested-by: Doug Anderson <dianders at chromium.org>


From mturquette at linaro.org  Wed May 29 13:58:27 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 10:58:27 -0700
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <51940CAF.6010808@codeaurora.org>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
 <51940CAF.6010808@codeaurora.org>
Message-ID: <20130529175827.6058.16653@quantum>

Quoting Stephen Boyd (2013-05-15 15:31:11)
> On 05/10/13 08:02, James Hogan wrote:
> > This adds a metag architecture specific clk-gate and clk-mux which
> > extends the generic ones to use global lock2 to protect the register
> > fields. It is common with metag to have an RTOS running on a different
> > thread or core with access to different bits in the same register (which
> > contain clock gate/switch bits for other clocks). Access to such
> > registers must be serialised with a global lock such as the one provided
> > by the metag architecture port in <asm/global_lock.h>
> >
> > RFC because despite extending the generic clocks there's still a bit of
> > duplicated code necessary. One alternative is to add special cases to
> > the generic clock components for when a global or callback function
> > based lock is desired instead of a spinlock, but I wasn't sure if that
> > sort of hack would really be appreciated in the generic drivers.
> >
> > Comments?
> 
> Can you please Cc the devicetree mailing list when proposing new bindings?
> 
> Your patchset brings up a question I've had which is if we should be
> putting the bits and register width information in devicetree at all. On
> the one hand it's nice to not have anything in C code, just iterate over
> nodes and register clocks. On the other hand, it's the first time I've
> seen anyone put the register interface into devicetree. From what I can
> tell, the regulator bindings have put at most the register base and
> physical properties like enable-time, max voltage, etc., but not what
> bits are needed to enable/disable a regulator. Also I thought I read
> somewhere that reg properties shouldn't overlap each other, so if you
> ever have two clocks living in the same register we're going to violate
> that.
> 

I've written bindings for the generic mux-clock, divider-clock, and I'm
working on a gate-clock (reusing some RFCs from a while back for
gate-clock).  All of these specify the base address as well as the
relevant bit fields.  To me this seems to intuitively describe the
hardware.  I'll post these bindings soon and let the bike shedding
begin.

Regards,
Mike

> -- 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> hosted by The Linux Foundation


From balbi at ti.com  Wed May 29 13:57:41 2013
From: balbi at ti.com (Felipe Balbi)
Date: Wed, 29 May 2013 20:57:41 +0300
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
Message-ID: <20130529175741.GG21290@arwen.pp.htv.fi>

On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
> 
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

for drivers/usb/musb

Acked-by: Felipe Balbi <balbi at ti.com>

-- 
balbi
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From konrad.wilk at oracle.com  Wed May 29 14:01:32 2013
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 29 May 2013 14:01:32 -0400
Subject: [PATCH v4 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305291718430.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
 <1369763672-12919-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130528181515.GB27718@phenom.dumpdata.com>
 <alpine.DEB.2.02.1305291159220.4799@kaball.uk.xensource.com>
 <20130529155544.GG23775@phenom.dumpdata.com>
 <alpine.DEB.2.02.1305291718430.4799@kaball.uk.xensource.com>
Message-ID: <20130529180132.GB10845@phenom.dumpdata.com>

> > > > > +void xen_setup_runstate_info(int cpu)
> > > > > +{
> > > > > +	struct vcpu_register_runstate_memory_area area;
> > > > > +
> > > > > +	area.addr.v = &per_cpu(xen_runstate, cpu);
> > > > > +
> > > > > +	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
> > > > > +			       cpu, &area))
> > > > > +		BUG();
> > > > 
> > > > The original code did:
> > > > 
> > > > -       rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
> > > > -                               &area);
> > > > -       WARN_ON(rc && rc != -ENOSYS);
> > > > -
> > > > Any reason not to do this?
> > > 
> > > The original x86 code just BUGs out: I took that version over the ia64
> > > version.
> > 
> > Ah, I see it now. OK, then this looks good to me.
> > 
> 
> Can I add your acked-by? ;-)

How about?

Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>


From swarren at wwwdotorg.org  Wed May 29 14:02:22 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 12:02:22 -0600
Subject: [GIT PULL] ARM: tegra: DT-related fixes needed by the USB tree
In-Reply-To: <20130529175508.GF21290@arwen.pp.htv.fi>
References: <1368831045-19105-1-git-send-email-swarren@wwwdotorg.org>
 <51A4E62D.7020206@wwwdotorg.org> <20130528174704.GH15794@arwen.pp.htv.fi>
 <20130529175508.GF21290@arwen.pp.htv.fi>
Message-ID: <51A642AE.1070905@wwwdotorg.org>

On 05/29/2013 11:55 AM, Felipe Balbi wrote:
> Hi,
> 
> On Tue, May 28, 2013 at 08:47:04PM +0300, Felipe Balbi wrote:
>> On Tue, May 28, 2013 at 11:15:25AM -0600, Stephen Warren wrote:
>>> On 05/17/2013 04:50 PM, Stephen Warren wrote:
>>>> Felipe, (and Alan, Greg),
>>>> 
>>>> These are the changes from the Tegra tree that need to be
>>>> merged before the Tegra USB driver patches 4-8 from Venu can
>>>> be applied. Recall that we had previously agreed on this
>>>> approach for v3.9, but Venu's patches didn't end up being
>>>> ready until now, unfortunately. I note that Venu's patches
>>>> affect both the Tegra USB and PHY drivers.
>>> 
>>> Felipe, do you know when you plan to pull this into the USB
>>> tree, and apply Venu's patches? Thanks.
>> 
>> got 35 commits testing right now. This pull is in my list for
>> tomorrow.
>> 
>> sorry for the delay, have been on a trip for the last 3 weeks and
>> now I'm catching up with emails during my vacations (next 2
>> weeks).
> 
> the tag is not pushed to where you pointed me to. Please make sure
> to git push it.
> 
> $ git fetch
> git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git
> tag tegra-for-3.11-deps-for-usb fatal: Couldn't find remote ref
> refs/tags/tegra-for-3.11-deps-for-usb

Sorry about that. I could have sworn I checked that, but obviously not.

Anyway, I've pushed it now, and the command you quoted above works for
me, so I think it's replicated out already.


From linus.walleij at linaro.org  Wed May 29 14:05:09 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 20:05:09 +0200
Subject: [RFC] arm: Update Booting document for FDT placement and reserved
 map
In-Reply-To: <1369835757-16371-1-git-send-email-grant.likely@linaro.org>
References: <1369835757-16371-1-git-send-email-grant.likely@linaro.org>
Message-ID: <CACRpkdatnyCsdJtf0g041k-1_jawfUhS83WSKzw6mWoP+5TKFQ@mail.gmail.com>

On Wed, May 29, 2013 at 3:55 PM, Grant Likely <grant.likely at linaro.org> wrote:

> In this patch I've stated that the initrd doesn't need to be included in
> the reserved map. However, should this be changed? Right now the
> decompressor doesn't actually look at the reserved map when
> decompressing and moving things around. If I'm reading the code
> correctly it is possible that the decompressor will overwrite the initrd
> if it gets placed too close to the kernel.

Maybe people aren't seeing this so much because anyone who
wants to place the ramfs close to the kernel (say because of
memory space constraints) is already using initramfs instead
of initrd?

Yours,
Linus Walleij


From arnd at arndb.de  Wed May 29 14:08:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 20:08:10 +0200
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <Pine.LNX.4.44L0.1305291211160.885-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305291211160.885-100000@iolanthe.rowland.org>
Message-ID: <3818608.3TBO8NnpYQ@wuerfel>

On Wednesday 29 May 2013 12:21:02 Alan Stern wrote:
> 
> Those error messages are annoying; they don't use dev_err(), so they
> don't include the device and driver names.  There's no way to know what
> they refer to.  I rather suspect they come from the usbaudio driver.

That makes sense. I have a usb audio device, and I don't actually recall
getting any sound from my speakers while testing it. I only checked
that the mouse was working and assumed that the usb-audio was driven
by ehci, but upon closer inspection, they are both on the same OHCI.

> When you ran this test, did you have commit 815fa7b91761 applied?

Yes.

> Does the same problem occur without Manjunath's changes?

No, it was introduced by the first patch, as I found later.

	Arnd


From cov at codeaurora.org  Wed May 29 14:09:23 2013
From: cov at codeaurora.org (Christopher Covington)
Date: Wed, 29 May 2013 14:09:23 -0400
Subject: [PATCH v4 3/4] arm: introduce CONFIG_PARAVIRT,
 PARAVIRT_TIME_ACCOUNTING and pv_time_ops
In-Reply-To: <1369763672-12919-3-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305281835080.4799@kaball.uk.xensource.com>
 <1369763672-12919-3-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <51A64453.5040005@codeaurora.org>

Hi Stefano,

On 05/28/2013 01:54 PM, Stefano Stabellini wrote:
> Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.
> 
> The only paravirt interface supported is pv_time_ops.steal_clock, so no
> runtime pvops patching needed.
> 
> This allows us to make use of steal_account_process_tick for stolen
> ticks accounting.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> CC: linux at arm.linux.org.uk
> CC: will.deacon at arm.com
> CC: nico at linaro.org
> CC: marc.zyngier at arm.com
> CC: cov at codeaurora.org
> CC: arnd at arndb.de
> CC: olof at lixom.net
> 
> Changes in v3:
> - improve commit description and Kconfig help text;
> - no need to initialize pv_time_ops;
> - add PARAVIRT_TIME_ACCOUNTING.

Looks good to me.

Acked-by: Christopher Covington <cov at codeaurora.org>

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.


From arnd at arndb.de  Wed May 29 14:10:05 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 20:10:05 +0200
Subject: [PATCH] SPI: Unify simple platform data for some controllers
In-Reply-To: <1369847158.250798748@f433.i.mail.ru>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <20130529144909.GT3660@sirena.org.uk> <1369847158.250798748@f433.i.mail.ru>
Message-ID: <1962597.10ArYKg8M9@wuerfel>

On Wednesday 29 May 2013 21:05:59 Alexander Shiyan wrote:
> > On Wed, May 29, 2013 at 03:26:34PM +0200, Arnd Bergmann wrote:
> > > On Wednesday 29 May 2013, Mark Brown wrote:
> > 
> > > > We probably also want to make
> > > > GPIO chip select support a standard thing that's available with every
> > > > driver rather than something the driver has to know about but that's a
> > > > separate bit of work.
> > 
> > > That actually seems simpler than doing it in just one driver: if
> > > we add a cs_gpio field to spi_board_info, spi_new_device could
> > > just copy that information into the new spi_device instead of
> > > taking it from master->cs_gpios.
> > 
> > Yeah, that bit of it is fine and straightforward.  It's slightly more
> > work to factor the chip select handling out so that we can implement the
> > handling at the appropriate moments in the flow due to the fact that
> > it's embedded in the message transfer functions but totally doable.
> 
> Initial try to simplify i.MX SPI driver I will send in 5 min.
> Patches is untested, so it is only RFC. Platform data still present in
> driver but patch migrate driver to using dynamic counter of
> chipselects for dt-case. Is it true way now? Comments are welcome.

The plan for i.MX is to move to DT-only in the long run, but
AFAIK a lot of people still rely on board files and they are
not trivial to convert without access to test hardware.

Any new i.MX hardware should certainly be DT-only.

Shawn can probably comment better on the time line.

	Arnd


From richard.genoud at gmail.com  Wed May 29 14:15:49 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 29 May 2013 20:15:49 +0200
Subject: [PATCHv3 RESEND 0/6] ARM: sunxi: Add support for A10 Ethernet
 controller
In-Reply-To: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <CACQ1gAgp6o8HqQcv=4cWoAZze3wtXHMX+g+7KvV-pnC2W5=iyg@mail.gmail.com>

2013/5/24 Maxime Ripard <maxime.ripard at free-electrons.com>:
> Hi,
>
> The Allwinner A10 SoC has an ethernet controller that seem to be specific to
> Allwinner. This IP has no public documentation, so exact
> details are quite sparse, and this code come from refactored Allwinner
> code.
>
> The rework to use NAPI is taking more time than expected, I'm still working
> on it, but it could probably be sent as a follow-up patch.
>
> Thanks,
> Maxime
>
> Changes from v2:
>   - Split the MDIO controller to a separate driver and make use of standards
>     device tree bindings
>   - Fixed various minor things as suggested by Florian Fainelli
>   - Added clock support now that we have a clock driver
>
> Changes from v1:
>   - Use phylib for the phy-related functions
>   - Use an optional regulator to power up the phy
>   - Rename the driver from Davicom Wemac to Allwinner EMAC, since it's the name
>     mentionned in the datasheet, and we have no strong evidence of a
>     relationship with Davicom
>   - Fix various small things around the driver: add defines for undocumented
>     values, fix documentation name and compatible example, etc.
>
> Maxime Ripard (4):
>   net: Add MDIO bus driver for the Allwinner EMAC
>   ARM: sun4i: Add muxing options for the ethernet controller
>   ARM: sunxi: Add EMAC controller node to sun4i DTSI
>   ARM: sunxi: Add EMAC Controller to Hackberry dt
>
> Stefan Roese (2):
>   net: Add EMAC ethernet driver found on Allwinner A10 SoC's
>   ARM: cubieboard: Enable ethernet (EMAC) support in dts
>
>  .../bindings/net/allwinner,sun4i-emac.txt          |  22 +
>  .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +
>  arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  15 +
>  arch/arm/boot/dts/sun4i-a10-hackberry.dts          |  41 +
>  arch/arm/boot/dts/sun4i-a10.dtsi                   |  27 +
>  drivers/net/ethernet/Kconfig                       |   1 +
>  drivers/net/ethernet/Makefile                      |   1 +
>  drivers/net/ethernet/allwinner/Kconfig             |  44 +
>  drivers/net/ethernet/allwinner/Makefile            |   6 +
>  drivers/net/ethernet/allwinner/sun4i-emac.c        | 960 +++++++++++++++++++++
>  drivers/net/ethernet/allwinner/sun4i-emac.h        | 108 +++
>  drivers/net/ethernet/allwinner/sun4i-mdio.c        | 191 ++++
>  12 files changed, 1442 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
>  create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
>  create mode 100644 drivers/net/ethernet/allwinner/Kconfig
>  create mode 100644 drivers/net/ethernet/allwinner/Makefile
>  create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
>  create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h
>  create mode 100644 drivers/net/ethernet/allwinner/sun4i-mdio.c
>
> --

I tested it successfully on cubieboard 1GB, on top of kernel 3.10-rc3,
nfsroot (debian wheezy)
I also added in sun4i-a10-cubieboard.dts
phy0: ethernet-phy at 0 {
 reg = <1>;
},
like Emilio suggested.

running an iperf, there's some good perfs !
iperf -s
------------------------------------------------------------
Server listening on TCP port 5001
TCP window size: 85.3 KByte (default)
------------------------------------------------------------
[  4] local 192.168.1.10 port 5001 connected with 192.168.1.232 port 38169
[ ID] Interval       Transfer     Bandwidth
[  4]  0.0-10.0 sec   112 MBytes  94.1 Mbits/sec

That's great ! with this patchset, we can now run a server with a
vanilla kernel ( who needs more that a serial port and ethernet,
really ? ;) )

Tested-by: Richard Genoud <richard.genoud at gmail.com>


From stern at rowland.harvard.edu  Wed May 29 14:16:56 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Wed, 29 May 2013 14:16:56 -0400 (EDT)
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <3818608.3TBO8NnpYQ@wuerfel>
Message-ID: <Pine.LNX.4.44L0.1305291415150.885-100000@iolanthe.rowland.org>

On Wed, 29 May 2013, Arnd Bergmann wrote:

> On Wednesday 29 May 2013 12:21:02 Alan Stern wrote:
> > 
> > Those error messages are annoying; they don't use dev_err(), so they
> > don't include the device and driver names.  There's no way to know what
> > they refer to.  I rather suspect they come from the usbaudio driver.
> 
> That makes sense. I have a usb audio device, and I don't actually recall
> getting any sound from my speakers while testing it. I only checked
> that the mouse was working and assumed that the usb-audio was driven
> by ehci, but upon closer inspection, they are both on the same OHCI.
> 
> > When you ran this test, did you have commit 815fa7b91761 applied?
> 
> Yes.
> 
> > Does the same problem occur without Manjunath's changes?
> 
> No, it was introduced by the first patch, as I found later.

I'll try to replicate your result.  I don't have my USB audio device 
here today, so it will have to wait until tomorrow.

Alan Stern



From khilman at linaro.org  Wed May 29 14:23:52 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 29 May 2013 11:23:52 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 (Olof Johansson's message of "Tue, 28 May 2013 22:31:41 -0700")
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
Message-ID: <87sj1563wn.fsf@linaro.org>

Olof Johansson <olof at lixom.net> writes:

> On Tue, May 28, 2013 at 8:59 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
>
>> The patches are at [1].
>
> FWIW, a cgit/gitweb link is easier to follow when you're reading an
> email. Anyway, found the patches.
>
>> There are a total of 6 patches on top of
>> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
>> (c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
>> (e, f) are required to reset the hub during EHCI initialization.
>
> Huh, I thought you said that (c) wasn't needed when I posted the
> defconfig update. It'd be nice to see the code fixed to handle this
> case instead of Linaro carrying a patch like this though. I.e. make it
> able to deselect the uart, or make it tied to DEBUG_LL like on other
> platforms instead of having a separate config for this.

I agree, that defconfig hack is awful to have to carry.

I also noticed that correct setting of CONFIG_S3C_LOWLEVEL_UART_PORT is
needed even without DEBUG_LL which seems broken.

Kevin



From linus.walleij at linaro.org  Wed May 29 14:27:59 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 20:27:59 +0200
Subject: [PATCH -next] dmaengine: ste_dma40: fix error return code in
 d40_probe()
In-Reply-To: <CAPgLHd-Mw4MQwS8=p9+ZBHHehH7B-Hs49BqiUMrq-aV_5M4pQQ@mail.gmail.com>
References: <CAPgLHd-Mw4MQwS8=p9+ZBHHehH7B-Hs49BqiUMrq-aV_5M4pQQ@mail.gmail.com>
Message-ID: <CACRpkdZH8jai84q6uwSRjMR+HCzohH-JMaKw1SCShYwgSKJYXQ@mail.gmail.com>

On Tue, May 28, 2013 at 11:06 AM, Wei Yongjun <weiyj.lk at gmail.com> wrote:

> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>
> In many of the error handling case, the return value 'ret' not set
> and 0 will be return from d40_probe() even if error, but we should
> return a negative error code instead in those error handling case.
> This patch fixed them, and also removed useless variable 'err'.
>
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Hm it seems it does not apply on my dma40 branch (the same
as mentioned by Andy):
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-stericsson.git/log/?h=ux500-dma40

I have already queued some 36 patches from this branch into
ARM SoC so it is in -next today (and conflicting with this patch).

Could you rebase it and get Vinod's ACK so I can queue it?

Also pls include Lee Jones on CC.

Yours,
Linus Walleij


From khilman at linaro.org  Wed May 29 14:34:07 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Wed, 29 May 2013 11:34:07 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <51A57D39.8030506@linaro.org> (Tushar Behera's message of "Wed,
 29 May 2013 09:29:53 +0530")
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
Message-ID: <87mwrd63fk.fsf@linaro.org>

Tushar Behera <tushar.behera at linaro.org> writes:

[...]

> The patches are at [1]. There are a total of 6 patches on top of
> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another patch
> (c) is just a defconfig hack to get Arndale booting. Remaining 2 patches
> (e, f) are required to reset the hub during EHCI initialization.
>
> a. ARM: exynos: defconfig update
> b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
> c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
> d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
> e. usb: ehci-s5p: add the HSIC port initialization
> f. ARM: dts: Add USB gpio entries for Arndale board
>
> I am not sure whether such kind of board-specific patches (e, f) are
> appreciated in the drivers. But that is all we need to get USB and
> Ethernet to work on v3.10-rc3 kernel.

I confirm that using v3.10-rc3 + these patches, the wired network is
working on Arndale.

Thanks,

Kevin


From linus.walleij at linaro.org  Wed May 29 14:36:42 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 20:36:42 +0200
Subject: [PATCH RESEND v3 1/2] pinctrl: imx: add VF610 support to imx
 pinctrl framework
In-Reply-To: <1369733528-25926-1-git-send-email-b35083@freescale.com>
References: <1369733528-25926-1-git-send-email-b35083@freescale.com>
Message-ID: <CACRpkdayEPreJKBUBK9abixN_M6O1QxGR2-ptErGXMcW4m+7bw@mail.gmail.com>

On Tue, May 28, 2013 at 11:32 AM, Jingchang Lu <b35083 at freescale.com> wrote:

> On some platforms such as VF610, offset of mux and pad ctrl register
> may be zero, and the mux_mode and config_val are in one 32-bit register.
> This patch adds support to imx core pinctrl framework to handle these
> cases.
>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v3:
>   Add ZERO_OFFSET_VALID flag to handle register offset from zero on Vybrid vf610.
>   Add SHARE_MUX_CONF_REG flag to handle mux mode and config value in one 32-bit
> register on Vybrid vf610.

Patch applied with Shawn's ACK.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Wed May 29 14:38:30 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 20:38:30 +0200
Subject: [PATCH v4 2/2] pinctrl: add VF610 pinctrl driver
In-Reply-To: <1369733528-25926-2-git-send-email-b35083@freescale.com>
References: <1369733528-25926-1-git-send-email-b35083@freescale.com>
 <1369733528-25926-2-git-send-email-b35083@freescale.com>
Message-ID: <CACRpkdaA-_RcgRxAa_0YQBoSBsUe-bPE-bd+bQBDrAQcxuS0BA@mail.gmail.com>

On Tue, May 28, 2013 at 11:32 AM, Jingchang Lu <b35083 at freescale.com> wrote:

> Adds Freescale Vybrid VF610 pin controller
> driver to IMX common pinctrl driver framework.
>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> v4:

Patch applied with Shawn's ACK.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Wed May 29 14:41:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 May 2013 20:41:26 +0200
Subject: [PATCH 7/7] Documentation: Update binding for Nomadik and DBx5x
 based platforms
In-Reply-To: <20130528093815.GH22683@gmail.com>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdYyZZSy4VgFc+Uo=5iAF++EPmHM0U2pHcLdkDZc=Xb_sQ@mail.gmail.com>
 <20130528093815.GH22683@gmail.com>
Message-ID: <CACRpkdYyZuReZEJCO6h8Ez3=7AmOm=JdT0_Gd+hDaGFnNJ8cGw@mail.gmail.com>

On Tue, May 28, 2013 at 11:38 AM, Lee Jones <lee.jones at linaro.org> wrote:
>> >  Required properties:
>> > -- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
>> > -              "stericsson,nmk-pinctrl-stn8815"
>> > +- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
>> > +              "stericsson,stn8815-pinctrl"
>>
>> OK...
>>
>> >         pinctrl at 80157000 {
>> > -               compatible = "stericsson,nmk-pinctrl";
>> > +               compatible = "stericsson,u8500-pinctrl";
>>
>> This does not look like a supported compatible string?
>
> Do you still think this, or did you change you mind?

Que? It is not among the listed compatible strings?

> If so, what makes you think it? How does it differ from:
>
> compatible = "arm,cortex-a9-twd-timer";
> compatible = "arm,rtc-pl031";
> compatible = "stericsson,db8500-gpio",
> compatible = "stericsson,db8500-musb",
> compatible = "stericsson,db8500-dma40",
> compatible = "stericsson,db8500-prcmu";
> compatible = "stericsson,db8500-prcmu-timer-4";
> compatible = "stericsson,db8500-thermal";
> compatible = "stericsson,db8500-prcmu-regulator";

It says u8500-pinctrl, not db8500-pinctrl.

Could it be that you're not actually seeing your own typo?

Yours,
Linus Walleij


From mturquette at linaro.org  Wed May 29 14:38:11 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 11:38:11 -0700
Subject: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks
In-Reply-To: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
References: <1368198127-1295-1-git-send-email-james.hogan@imgtec.com>
Message-ID: <20130529183811.6058.78627@quantum>

Quoting James Hogan (2013-05-10 08:02:02)
> This adds a metag architecture specific clk-gate and clk-mux which
> extends the generic ones to use global lock2 to protect the register
> fields. It is common with metag to have an RTOS running on a different
> thread or core with access to different bits in the same register (which
> contain clock gate/switch bits for other clocks). Access to such
> registers must be serialised with a global lock such as the one provided
> by the metag architecture port in <asm/global_lock.h>
> 
> RFC because despite extending the generic clocks there's still a bit of
> duplicated code necessary. One alternative is to add special cases to
> the generic clock components for when a global or callback function
> based lock is desired instead of a spinlock, but I wasn't sure if that
> sort of hack would really be appreciated in the generic drivers.
> 
> Comments?
> 

The general approach looks OK, but you've kind of created generic
mux-clock and gate-clock bindings in a metag-specific driver.  I would
prefer to have those functions exist in the generic drivers and your
driver re-use those.  I'll be posting bindings for those clocks by the
end of the week (they're on my github repo now for the curious).

Wrapping the generic clock types is an OK approach and is done by
several other drivers, so there is no problem there.

Regards,
Mike

> James Hogan (2):
>   clk: metag/clk-gate: add metag specific clock gate
>   clk: metag/clk-mux: add metag specific clk-mux
> 
>  .../bindings/clock/img,meta-gate-clock.txt         |  28 +++
>  .../bindings/clock/img,meta-mux-clock.txt          |  33 ++++
>  drivers/clk/Makefile                               |   1 +
>  drivers/clk/metag/Makefile                         |   3 +
>  drivers/clk/metag/clk-gate.c                       | 179 +++++++++++++++++
>  drivers/clk/metag/clk-mux.c                        | 211 +++++++++++++++++++++
>  6 files changed, 455 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/img,meta-gate-clock.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/img,meta-mux-clock.txt
>  create mode 100644 drivers/clk/metag/Makefile
>  create mode 100644 drivers/clk/metag/clk-gate.c
>  create mode 100644 drivers/clk/metag/clk-mux.c
> 
> -- 
> 1.8.1.2


From olof at lixom.net  Wed May 29 14:46:47 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed, 29 May 2013 11:46:47 -0700
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net>
 <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 <51A5C16D.20408@linaro.org>
 <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
Message-ID: <CAOesGMiYs6GfaWGWYB8cw_cJ6_RmmZTb4oPfXo1PYJT8-jdHzw@mail.gmail.com>

On Wed, May 29, 2013 at 2:33 AM, Jingoo Han <jg1.han at samsung.com> wrote:

> However, Olof Johansson mentioned, 'drivers/platform/arm/board_arndale.c'
> would be a good alternative.


Whoa. I didn't quite realize what I proposed, or rather, how what I
proposed could be perceived. I take it back. :)

We must _not_ introduce something that will be abused as a new home
for board file junk. If we do introduce a platform glue directory it
would need to be very limited in scope. Compare to what's in
drivers/platform/x86 today.


-Olof


From aaro.koskinen at iki.fi  Wed May 29 14:55:18 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Wed, 29 May 2013 21:55:18 +0300
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <51A4FAA1.5060504@gmail.com>
References: <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com>
 <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
 <20130526190710.GA3345@blackmetal.musicnaut.iki.fi>
 <51A4FAA1.5060504@gmail.com>
Message-ID: <20130529185518.GB3345@blackmetal.musicnaut.iki.fi>

Hi,

On Tue, May 28, 2013 at 07:42:41PM +0100, Jon Hunter wrote:
> Care to share the log?

Below are three logs from 3.10-rc3 / Nokia 770. I did not even compile
Retu this time, as it has nothing to do with GPIO IRQs being broken
on OMAP1.

1) broken vanilla 3.10-rc3: serial wakeup GPIO irq gets IRQ 0 and no
other GPIO IRQs seen in /proc/interrupts. genirq error logs seen in boot.

2) working 3.10-rc3 with Tony's fix <== this fix should be applied
(http://marc.info/?l=linux-arm-kernel&m=136907202628855&w=2). GPIO IRQs
are normal, e.g. touchscreen can be used.

3) .config used.

A.

--8<--

1) Broken, vanilla 3.10-rc3:

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.10.0-rc3-770_tiny (aaro at blackmetal) (gcc version 4.7.3 (GCC) ) #3 Wed May 29 21:28:04 EEST 2013
[    0.000000] Ignoring unrecognised tag 0x414f4d50
[    0.000000] OMAP1710
[    0.000000]  revision 8 handled as 16xx id: 8b5f702f03330200
[    0.000000] Clocks: ARM_SYSST: 0x1000 DPLL_CTL: 0x2a93 ARM_CKCTL: 0x050e
[    0.000000] Clocking rate (xtal/DPLL1/MPU): 12.0/252.0/252.0 MHz
[    0.000000] Kernel command line: mem=64M console=tty console=ttyS0,115200n8
[    0.000000] PID hash table entries: 256 (order: -2, 1024 bytes)
[    0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Memory: 64MB = 64MB total
[    0.000000] Memory: 60168k/60168k available, 5368k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc4800000 - 0xff000000   ( 936 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc01cbd5c   (1808 kB)
[    0.000000]       .init : 0xc01cc000 - 0xc04503bc   (2577 kB)
[    0.000000]       .data : 0xc0452000 - 0xc0478240   ( 153 kB)
[    0.000000]        .bss : 0xc0478240 - 0xc04a3d04   ( 175 kB)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS:368
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000000] console [tty0] enabled
[    0.002777] Calibrating delay loop... 125.33 BogoMIPS (lpj=626688)
[    0.090057] pid_max: default: 32768 minimum: 301
[    0.090942] Mount-cache hash table entries: 512
[    0.092956] CPU: Testing write buffer coherency: ok
[    0.093902] Setting up static identity map for 0xc018d540 - 0xc018d57c
[    0.096618] devtmpfs: initialized
[    0.106231] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.113677] omap_gpio omap_gpio.1: Could not get gpio dbck
[    0.114044] OMAP GPIO hardware version 1.1
[    0.114288] omap_gpio omap_gpio.2: Could not get gpio dbck
[    0.114746] omap_gpio omap_gpio.3: Could not get gpio dbck
[    0.115203] omap_gpio omap_gpio.4: Could not get gpio dbck
[    0.121490] MUX: initialized V6_USB0_TXD
[    0.121643] MUX: initialized W5_USB0_SE0
[    0.121734] MUX: initialized Y5_USB0_RCV
[    0.121826] MUX: initialized AA9_USB0_VP
[    0.121887] MUX: initialized R9_USB0_VM
[    0.122833] MUX: initialized W19_1610_MMC2_DATDIR1
[    0.126129] Clocking rate (xtal/DPLL1/MPU): 12.0/216.0/216.0 MHz
[    0.137847] OMAP DMA hardware version 1
[    0.138000] DMA capabilities: 0000000c:00000000:01ff:003f:007f
[    0.190521] bio: create slab <bio-0> at 0
[    0.315185] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[    0.320098] SCSI subsystem initialized
[    0.320465] omap_uwire omap_uwire: Runtime PM disabled, clock forced on.
[    0.322052] omap_uwire omap_uwire: master is unqueued, this is deprecated
[    0.326446] usbcore: registered new interface driver usbfs
[    0.327575] usbcore: registered new interface driver hub
[    0.328765] usbcore: registered new device driver usb
[    0.332427] Switching to clocksource 32k_counter
[    0.509490] OMAP OCPI interconnect driver loaded
[    1.194671] io scheduler noop registered (default)
[    1.233367] omapfb: lph8923 rev 92 LCD detected, 16 data lines
[    1.245727] omapfb: configured for panel lph8923
[    1.254882] omapfb: LCDC initialized
[    1.255157] omapfb omapfb: SoSSI version 1.21 initialized
[    1.255889] omapfb omapfb: : Epson HWA742 LCD controller rev 1 initialized (CNF pins 7)
[    1.256134] omapfb omapfb: HWA742: setting update mode to auto
[    1.334136] Console: switching to colour frame buffer device 100x30
[    1.370452] omapfb: Framebuffer initialized. Total vram 770048 planes 1
[    1.383117] omapfb: Pixclock 21940 kHz hfreq 24.9 kHz vfreq 51.0 Hz
[    1.428649] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.535339] serial8250.0: ttyS0 at MMIO 0xfffb0000 (irq = 46) is a ST16654
[    1.942626] console [ttyS0] enabled
[    2.024841] serial8250.0: ttyS1 at MMIO 0xfffb0800 (irq = 47) is a ST16654
[    2.094818] serial8250.0: ttyS2 at MMIO 0xfffb9800 (irq = 15) is a ST16654
[    2.184295] usbcore: registered new interface driver usb-storage
[    2.295166] mmci-omap mmci-omap.1: Runtime PM disabled, clock forced on.
[    2.314910] mmci-omap mmci-omap.1: Runtime PM disabled, clock forced on.
[    2.334442] omap-dma-engine omap-dma-engine: allocating channel for 54
[    2.353729] omap-dma-engine omap-dma-engine: allocating channel for 55
[    2.453918] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.473175] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.496093] mmci-omap mmci-omap.1: command timeout (CMD8)
[    2.515228] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.533538] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.551086] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.568450] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.586059] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.602905] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.619232] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.635070] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.651000] mmci-omap mmci-omap.1: command timeout (CMD1)
[    2.703674] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.718048] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.736267] mmci-omap mmci-omap.1: command timeout (CMD8)
[    2.749542] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.761718] usbcore: registered new interface driver usbhid
[    2.773590] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.785339] usbhid: USB HID core driver
[    2.796142] VFP support v0.3: not present
[    2.806823] genirq: Flags mismatch irq 0. 00000001 (serial wakeup) vs. 00000001 (serial wakeup)
[    2.822387] No interrupt for UART wake GPIO: 18
[    2.833953] genirq: Flags mismatch irq 0. 00000001 (serial wakeup) vs. 00000001 (serial wakeup)
[    2.850372] No interrupt for UART wake GPIO: 49
[    2.864074] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.958190] Freeing unused kernel memory: 2576K (c01cc000 - c0450000)
[    3.003692] mmci-omap mmci-omap.1: command timeout (CMD5)
[    3.019165] mmci-omap mmci-omap.1: command timeout (CMD55)
[    3.034576] mmci-omap mmci-omap.1: command timeout (CMD55)
[    3.050018] mmci-omap mmci-omap.1: command timeout (CMD55)
[    3.065429] mmci-omap mmci-omap.1: command timeout (CMD55)
[    3.081054] mmci-omap mmci-omap.1: command timeout (CMD1)
[    3.403076] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    3.419403] ohci ohci: OMAP OHCI
[    3.432556] ohci ohci: new USB bus registered, assigned bus number 1
[    3.449584] ohci ohci: irq 38, io mem 0xfffba000
[    3.554595] hub 1-0:1.0: USB hub found
[    3.569305] hub 1-0:1.0: 3 ports detected

# cat /proc/interrupts
           CPU0       
  0:          0      GPIO  serial wakeup
 19:          0       MPU  DMA
 20:          0       MPU  DMA
 21:          0       MPU  DMA
 22:          0       MPU  DMA
 23:          0       MPU  DMA
 24:          0       MPU  DMA
 25:        108       MPU  LCD DMA
 31:          0       MPU  lcdc
 38:          0       MPU  ohci_hcd:usb1
 46:          3       MPU  serial
 51:          0       MPU  sossi_match
 54:        361       MPU  32KHz timer
 74:         26       MPU  mmci-omap
 85:          0       MPU  DMA
 86:          0       MPU  DMA
 87:          0       MPU  DMA
 88:          0       MPU  DMA
 89:          0       MPU  DMA
 90:          0       MPU  DMA
 91:          0       MPU  DMA
 92:          0       MPU  DMA
 93:          0       MPU  DMA
 94:          0       MPU  DMA
Err:          0

--8<--

2) OK, 3.10-rc3 with Tony's patch:

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.10.0-rc3-770_tiny+ (aaro at blackmetal) (gcc version 4.7.3 (GCC) ) #4 Wed May 29 21:35:52 EEST 2013
[    0.000000] Ignoring unrecognised tag 0x414f4d50
[    0.000000] OMAP1710
[    0.000000]  revision 8 handled as 16xx id: 8b5f702f03330200
[    0.000000] Clocks: ARM_SYSST: 0x1000 DPLL_CTL: 0x2a93 ARM_CKCTL: 0x050e
[    0.000000] Clocking rate (xtal/DPLL1/MPU): 12.0/252.0/252.0 MHz
[    0.000000] Kernel command line: mem=64M console=tty console=ttyS0,115200n8
[    0.000000] PID hash table entries: 256 (order: -2, 1024 bytes)
[    0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Memory: 64MB = 64MB total
[    0.000000] Memory: 60168k/60168k available, 5368k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc4800000 - 0xff000000   ( 936 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc01cbd5c   (1808 kB)
[    0.000000]       .init : 0xc01cc000 - 0xc04503bc   (2577 kB)
[    0.000000]       .data : 0xc0452000 - 0xc0478240   ( 153 kB)
[    0.000000]        .bss : 0xc0478240 - 0xc04a3d04   ( 175 kB)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS:368
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000000] console [tty0] enabled
[    0.002807] Calibrating delay loop... 125.33 BogoMIPS (lpj=626688)
[    0.090087] pid_max: default: 32768 minimum: 301
[    0.090972] Mount-cache hash table entries: 512
[    0.092956] CPU: Testing write buffer coherency: ok
[    0.093963] Setting up static identity map for 0xc018d568 - 0xc018d5a4
[    0.096649] devtmpfs: initialized
[    0.106292] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.113555] omap_gpio omap_gpio.1: Could not get gpio dbck
[    0.113830] OMAP GPIO hardware version 1.1
[    0.114105] omap_gpio omap_gpio.2: Could not get gpio dbck
[    0.114471] omap_gpio omap_gpio.3: Could not get gpio dbck
[    0.114868] omap_gpio omap_gpio.4: Could not get gpio dbck
[    0.121002] MUX: initialized V6_USB0_TXD
[    0.121124] MUX: initialized W5_USB0_SE0
[    0.121215] MUX: initialized Y5_USB0_RCV
[    0.121307] MUX: initialized AA9_USB0_VP
[    0.121398] MUX: initialized R9_USB0_VM
[    0.122314] MUX: initialized W19_1610_MMC2_DATDIR1
[    0.125671] Clocking rate (xtal/DPLL1/MPU): 12.0/216.0/216.0 MHz
[    0.137451] OMAP DMA hardware version 1
[    0.137634] DMA capabilities: 0000000c:00000000:01ff:003f:007f
[    0.190155] bio: create slab <bio-0> at 0
[    0.315124] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[    0.320068] SCSI subsystem initialized
[    0.320434] omap_uwire omap_uwire: Runtime PM disabled, clock forced on.
[    0.322021] omap_uwire omap_uwire: master is unqueued, this is deprecated
[    0.326446] usbcore: registered new interface driver usbfs
[    0.327545] usbcore: registered new interface driver hub
[    0.328735] usbcore: registered new device driver usb
[    0.332397] Switching to clocksource 32k_counter
[    0.510131] OMAP OCPI interconnect driver loaded
[    1.171295] io scheduler noop registered (default)
[    1.243957] omapfb: lph8923 rev 92 LCD detected, 16 data lines
[    1.259704] omapfb: configured for panel lph8923
[    1.268859] omapfb: LCDC initialized
[    1.269134] omapfb omapfb: SoSSI version 1.21 initialized
[    1.269866] omapfb omapfb: : Epson HWA742 LCD controller rev 1 initialized (CNF pins 7)
[    1.270111] omapfb omapfb: HWA742: setting update mode to auto
[    1.331970] Console: switching to colour frame buffer device 100x30
[    1.369232] omapfb: Framebuffer initialized. Total vram 770048 planes 1
[    1.381774] omapfb: Pixclock 21940 kHz hfreq 24.9 kHz vfreq 51.0 Hz
[    1.435150] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.539184] serial8250.0: ttyS0 at MMIO 0xfffb0000 (irq = 46) is a ST16654
[    1.946960] console [ttyS0] enabled
[    2.024810] serial8250.0: ttyS1 at MMIO 0xfffb0800 (irq = 47) is a ST16654
[    2.104766] serial8250.0: ttyS2 at MMIO 0xfffb9800 (irq = 15) is a ST16654
[    2.194488] usbcore: registered new interface driver usb-storage
[    2.246032] ads7846 spi2.0: touchscreen, irq 174
[    2.266693] input: ADS7846 Touchscreen as /devices/platform/omap_uwire/spi_master/spi2/spi2.0/input/input0
[    2.375030] mmci-omap mmci-omap.1: Runtime PM disabled, clock forced on.
[    2.396148] mmci-omap mmci-omap.1: Runtime PM disabled, clock forced on.
[    2.417114] omap-dma-engine omap-dma-engine: allocating channel for 54
[    2.438018] omap-dma-engine omap-dma-engine: allocating channel for 55
[    2.533843] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.554290] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.578033] mmci-omap mmci-omap.1: command timeout (CMD8)
[    2.598144] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.617492] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.636322] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.654968] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.673553] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.691131] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.708160] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.724914] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.741607] mmci-omap mmci-omap.1: command timeout (CMD1)
[    2.774658] usbcore: registered new interface driver usbhid
[    2.789337] usbhid: USB HID core driver
[    2.802001] VFP support v0.3: not present
[    2.817016] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.845886] mmci-omap mmci-omap.1: command timeout (CMD52)
[    2.864868] mmci-omap mmci-omap.1: command timeout (CMD8)
[    2.879516] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.893280] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.906005] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.918121] mmci-omap mmci-omap.1: command timeout (CMD5)
[    2.930236] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.942077] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.954254] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.965942] mmci-omap mmci-omap.1: command timeout (CMD55)
[    2.977355] mmci-omap mmci-omap.1: command timeout (CMD1)
[    3.050811] Freeing unused kernel memory: 2576K (c01cc000 - c0450000)
[    3.415039] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    3.427734] ohci ohci: OMAP OHCI
[    3.437652] ohci ohci: new USB bus registered, assigned bus number 1
[    3.451171] ohci ohci: irq 38, io mem 0xfffba000
[    3.554595] hub 1-0:1.0: USB hub found
[    3.565643] hub 1-0:1.0: 3 ports detected

# cat /proc/interrupts
           CPU0       
 19:          0       MPU  DMA
 20:          0       MPU  DMA
 21:          0       MPU  DMA
 22:          0       MPU  DMA
 23:          0       MPU  DMA
 24:          0       MPU  DMA
 25:        322       MPU  LCD DMA
 31:          0       MPU  lcdc
 38:          0       MPU  ohci_hcd:usb1
 46:         96       MPU  serial
 51:          0       MPU  sossi_match
 54:        631       MPU  32KHz timer
 74:         26       MPU  mmci-omap
 85:          0       MPU  DMA
 86:          0       MPU  DMA
 87:          0       MPU  DMA
 88:          0       MPU  DMA
 89:          0       MPU  DMA
 90:          0       MPU  DMA
 91:          0       MPU  DMA
 92:          0       MPU  DMA
 93:          0       MPU  DMA
 94:          0       MPU  DMA
174:       1377      GPIO  ads7846
177:          0      GPIO  serial wakeup
196:          0      GPIO  serial wakeup
208:          0      GPIO  serial wakeup
Err:          0

--8<--

3) .config

#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.10.0-rc3 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_NEED_MACH_MEMORY_H=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y

#
# General setup
#
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION="-770_tiny"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
# CONFIG_KERNEL_GZIP is not set
CONFIG_KERNEL_LZMA=y
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_FHANDLE is not set
CONFIG_HAVE_GENERIC_HARDIRQS=y

#
# IRQ subsystem
#
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set

#
# RCU Subsystem
#
CONFIG_TINY_RCU=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_RCU_STALL_COMMON is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_NAMESPACES is not set
CONFIG_UIDGID_CONVERTED=y
# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_RD_GZIP is not set
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_HOTPLUG=y
CONFIG_EXPERT=y
# CONFIG_UID16 is not set
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_KALLSYMS is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_SHMEM is not set
# CONFIG_AIO is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
# CONFIG_PERF_EVENTS is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_JUMP_LABEL is not set
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y

#
# GCOV-based kernel profiling
#
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
# CONFIG_MODULE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_BLOCK=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_FREEZER is not set

#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_MULTIPLATFORM is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P64X0 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
CONFIG_ARCH_OMAP1=y
# CONFIG_GPIO_PCA953X is not set

#
# TI OMAP Common Features
#
CONFIG_ARCH_OMAP_OTG=y

#
# OMAP Feature Selections
#
# CONFIG_OMAP_RESET_CLOCKS is not set
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
CONFIG_OMAP_MUX_WARNINGS=y
# CONFIG_OMAP_MBOX_FWK is not set
# CONFIG_OMAP_MPU_TIMER is not set
CONFIG_OMAP_32K_TIMER=y
# CONFIG_OMAP_DM_TIMER is not set
CONFIG_OMAP_SERIAL_WAKE=y
CONFIG_OMAP_PM_NOOP=y

#
# TI OMAP1 specific features
#

#
# OMAP Core Type
#
# CONFIG_ARCH_OMAP730 is not set
# CONFIG_ARCH_OMAP850 is not set
# CONFIG_ARCH_OMAP15XX is not set
CONFIG_ARCH_OMAP16XX=y

#
# OMAP Board Type
#
# CONFIG_MACH_OMAP_INNOVATOR is not set
# CONFIG_MACH_OMAP_H2 is not set
# CONFIG_MACH_OMAP_H3 is not set
# CONFIG_MACH_OMAP_OSK is not set
CONFIG_MACH_NOKIA770=y
# CONFIG_MACH_OMAP_GENERIC is not set
CONFIG_ARCH_OMAP=y
# CONFIG_PLAT_SPEAR is not set

#
# Processor Type
#
# CONFIG_CPU_ARM925T is not set
CONFIG_CPU_ARM926T=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5TJ=y
CONFIG_CPU_PABRT_LEGACY=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_USE_DOMAINS=y

#
# Processor Features
#
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_ARM_THUMB is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_ARM_L1_CACHE_SHIFT=5
CONFIG_ARM_NR_BANKS=8

#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_ARCH_NR_GPIO=0
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_HAVE_ARCH_PFN_VALID=y
# CONFIG_HIGHMEM is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_CLEANCACHE is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_SECCOMP is not set
# CONFIG_CC_STACKPROTECTOR is not set

#
# Boot options
#
# CONFIG_USE_OF is not set
CONFIG_ATAGS=y
# CONFIG_DEPRECATED_PARAM_STRUCT is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M console=tty console=ttyS0,115200n8"
# CONFIG_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_CMDLINE_EXTEND=y
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
# CONFIG_CRASH_DUMP is not set
# CONFIG_AUTO_ZRELADDR is not set

#
# CPU Power Management
#

#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
# CONFIG_CPU_IDLE is not set
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_VFP=y

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_PM_RUNTIME is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_ARM_CPU_SUSPEND is not set
# CONFIG_NET is not set
CONFIG_HAVE_BPF_JIT=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
# CONFIG_DMA_SHARED_BUFFER is not set
# CONFIG_CMA is not set

#
# Bus devices
#
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set

#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_ATMEL_PWM is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ATMEL_SSC is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_BMP085_I2C is not set
# CONFIG_BMP085_SPI is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_SRAM is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set

#
# Altera FPGA firmware download module
#
# CONFIG_ALTERA_STAPL is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_W90X900 is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_INPUT_MISC is not set

#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_TRACE_SINK is not set
# CONFIG_DEVKMEM is not set

#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_EM is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_HVC_DCC is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
# CONFIG_I2C_CHARDEV is not set
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CBUS_GPIO=y
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_OMAP is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_OC_TINY is not set
CONFIG_SPI_OMAP_UWIRE=y
# CONFIG_SPI_PXA2XX_PCI is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set

#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set

#
# Qualcomm MSM SSBI bus support
#
# CONFIG_SSBI is not set
# CONFIG_HSI is not set

#
# PPS support
#
# CONFIG_PPS is not set

#
# PPS generators support
#

#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# CONFIG_PTP_1588_CLOCK_PCH is not set
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set

#
# Memory mapped GPIO drivers:
#
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_EM is not set
# CONFIG_GPIO_RCAR is not set
# CONFIG_GPIO_TS5500 is not set

#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SX150X is not set
# CONFIG_GPIO_ADP5588 is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_74X164 is not set

#
# AC97 GPIO expanders:
#

#
# MODULbus GPIO expanders:
#

#
# USB GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_POWER_AVS is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_CORE is not set
# CONFIG_WATCHDOG_NOWAYOUT is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
# CONFIG_OMAP_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y

#
# Broadcom specific AMBA
#
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set

#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_GOLDFISH is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_AUO_K190X is not set
CONFIG_FB_OMAP=y
CONFIG_FB_OMAP_LCDC_EXTERNAL=y
CONFIG_FB_OMAP_LCDC_HWA742=y
# CONFIG_FB_OMAP_MANUAL_UPDATE is not set
CONFIG_FB_OMAP_LCD_MIPID=y
# CONFIG_FB_OMAP_DMA_TUNE is not set
# CONFIG_EXYNOS_VIDEO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_SOUND is not set

#
# HID support
#
CONFIG_HID=y
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO_TPKBD is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_PS3REMOTE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# I2C HID support
#
# CONFIG_I2C_HID is not set
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB_ARCH_HAS_XHCI is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_OMAP1=y
# CONFIG_USB_OHCI_HCD_PLATFORM is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_CHIPIDEA is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_PHY is not set
# CONFIG_USB_GADGET is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
# CONFIG_MMC_CLKGATE is not set

#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SDHCI_PXAV3 is not set
# CONFIG_MMC_SDHCI_PXAV2 is not set
CONFIG_MMC_OMAP=y
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
# CONFIG_DW_DMAC is not set
# CONFIG_TIMB_DMA is not set
CONFIG_DMA_OMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VIRT_DRIVERS is not set

#
# Virtio drivers
#
# CONFIG_VIRTIO_MMIO is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_STAGING is not set
CONFIG_CLKDEV_LOOKUP=y

#
# Hardware Spinlock drivers
#
CONFIG_CLKSRC_MMIO=y
# CONFIG_MAILBOX is not set
# CONFIG_IOMMU_SUPPORT is not set

#
# Remoteproc drivers
#
# CONFIG_STE_MODEM_RPROC is not set

#
# Rpmsg drivers
#
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
# CONFIG_PWM is not set
# CONFIG_IPACK_BUS is not set
# CONFIG_RESET_CONTROLLER is not set

#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_FILE_LOCKING is not set
# CONFIG_FSNOTIFY is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_QUOTACTL is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set

#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=7
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set

#
# RCU Debugging
#
# CONFIG_SPARSE_RCU_POINTER is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_STRICT_DEVMEM is not set
# CONFIG_ARM_UNWIND is not set
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_LL is not set
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
# CONFIG_CRYPTO is not set
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
# CONFIG_XZ_DEC is not set
# CONFIG_XZ_DEC_BCJ is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
# CONFIG_VIRTUALIZATION is not set


From lee.jones at linaro.org  Wed May 29 15:01:39 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 29 May 2013 20:01:39 +0100
Subject: [PATCH 7/7] Documentation: Update binding for Nomadik and DBx5x
 based platforms
In-Reply-To: <CACRpkdYyZuReZEJCO6h8Ez3=7AmOm=JdT0_Gd+hDaGFnNJ8cGw@mail.gmail.com>
References: <1369232581-18923-1-git-send-email-lee.jones@linaro.org>
 <1369232581-18923-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdYyZZSy4VgFc+Uo=5iAF++EPmHM0U2pHcLdkDZc=Xb_sQ@mail.gmail.com>
 <20130528093815.GH22683@gmail.com>
 <CACRpkdYyZuReZEJCO6h8Ez3=7AmOm=JdT0_Gd+hDaGFnNJ8cGw@mail.gmail.com>
Message-ID: <20130529190139.GH3012@gmail.com>

On Wed, 29 May 2013, Linus Walleij wrote:

> On Tue, May 28, 2013 at 11:38 AM, Lee Jones <lee.jones at linaro.org> wrote:
> >> >  Required properties:
> >> > -- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
> >> > -              "stericsson,nmk-pinctrl-stn8815"
> >> > +- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
> >> > +              "stericsson,stn8815-pinctrl"
> >>
> >> OK...
> >>
> >> >         pinctrl at 80157000 {
> >> > -               compatible = "stericsson,nmk-pinctrl";
> >> > +               compatible = "stericsson,u8500-pinctrl";
> >>
> >> This does not look like a supported compatible string?
> >
> > Do you still think this, or did you change you mind?
> 
> Que? It is not among the listed compatible strings?
> 
> > If so, what makes you think it? How does it differ from:
> >
> > compatible = "arm,cortex-a9-twd-timer";
> > compatible = "arm,rtc-pl031";
> > compatible = "stericsson,db8500-gpio",
> > compatible = "stericsson,db8500-musb",
> > compatible = "stericsson,db8500-dma40",
> > compatible = "stericsson,db8500-prcmu";
> > compatible = "stericsson,db8500-prcmu-timer-4";
> > compatible = "stericsson,db8500-thermal";
> > compatible = "stericsson,db8500-prcmu-regulator";
> 
> It says u8500-pinctrl, not db8500-pinctrl.
> 
> Could it be that you're not actually seeing your own typo?

Yes, that's exactly what happened.

I thought you were mentioning the way it was laid out.

I'll fixup.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From mturquette at linaro.org  Wed May 29 15:02:04 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 12:02:04 -0700
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130529190204.6058.85682@quantum>

Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
> 
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
> 
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
> 
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> 
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> 
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
> 
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
> 

Sebastian,

Sorry for the tardy response.  This cleanup looks really good.  If it's
not too late:

Acked-by: Mike Turquette <mturquette at linaro.org>

If the branch is already pulled into arm-soc don't worry about the Ack.

Regards,
Mike

> Sebastian Hesselbarth (10):
>   clk: mvebu: introduce per-clock-gate flags
>   clk: mvebu: add common clock functions for core clk and clk gating
>   clk: mvebu: add Dove SoC-centric clock init
>   clk: mvebu: add Kirkwood SoC-centric clock init
>   clk: mvebu: add Armada 370 SoC-centric clock init
>   clk: mvebu: add Armada XP SoC-centric clock init
>   ARM: dove: move DT boards to SoC-centric clock init
>   ARM: kirkwood: move DT boards to SoC-centric clock init
>   ARM: mvebu: move DT boards to SoC-centric clock init
>   clk: mvebu: desintegrate obsolete file
> 
>  arch/arm/mach-dove/Kconfig          |    3 +-
>  arch/arm/mach-dove/board-dt.c       |    3 +-
>  arch/arm/mach-dove/common.c         |    1 -
>  arch/arm/mach-kirkwood/Kconfig      |    3 +-
>  arch/arm/mach-kirkwood/board-dt.c   |    3 +-
>  arch/arm/mach-mvebu/Kconfig         |    5 +-
>  arch/arm/mach-mvebu/armada-370-xp.c |    4 +-
>  drivers/clk/mvebu/Kconfig           |   25 +-
>  drivers/clk/mvebu/Makefile          |    8 +-
>  drivers/clk/mvebu/armada-370.c      |  176 +++++++++
>  drivers/clk/mvebu/armada-xp.c       |  204 +++++++++++
>  drivers/clk/mvebu/clk-core.c        |  675 -----------------------------------
>  drivers/clk/mvebu/clk-core.h        |   18 -
>  drivers/clk/mvebu/clk-gating-ctrl.c |  250 -------------
>  drivers/clk/mvebu/clk-gating-ctrl.h |   22 --
>  drivers/clk/mvebu/clk.c             |   23 --
>  drivers/clk/mvebu/common.c          |  163 +++++++++
>  drivers/clk/mvebu/common.h          |   48 +++
>  drivers/clk/mvebu/dove.c            |  194 ++++++++++
>  drivers/clk/mvebu/kirkwood.c        |  247 +++++++++++++
>  include/linux/clk/mvebu.h           |   22 --
>  21 files changed, 1066 insertions(+), 1031 deletions(-)
>  create mode 100644 drivers/clk/mvebu/armada-370.c
>  create mode 100644 drivers/clk/mvebu/armada-xp.c
>  delete mode 100644 drivers/clk/mvebu/clk-core.c
>  delete mode 100644 drivers/clk/mvebu/clk-core.h
>  delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
>  delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
>  delete mode 100644 drivers/clk/mvebu/clk.c
>  create mode 100644 drivers/clk/mvebu/common.c
>  create mode 100644 drivers/clk/mvebu/common.h
>  create mode 100644 drivers/clk/mvebu/dove.c
>  create mode 100644 drivers/clk/mvebu/kirkwood.c
>  delete mode 100644 include/linux/clk/mvebu.h
> ---
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> -- 
> 1.7.10.4


From sebastian.hesselbarth at gmail.com  Wed May 29 15:05:41 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:05:41 +0200
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <20130529190204.6058.85682@quantum>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130529190204.6058.85682@quantum>
Message-ID: <51A65185.1020307@gmail.com>

On 05/29/2013 09:02 PM, Mike Turquette wrote:
> Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
>> Marvell EBU SoCs share some common clock functions that register core
>> clocks or clock gates from SoC specific data. These clock drivers are
>> organized by function and over time the drivers filled up with #ifdefs
>> to separate different SoC specific code.
>>
...
>> @Mike: As this only touches MVEBU related code, I suggest to take it
>> all through the corresponding ARM branch.
>>
> Sorry for the tardy response.  This cleanup looks really good.  If it's
> not too late:
>
> Acked-by: Mike Turquette<mturquette at linaro.org>
>
> If the branch is already pulled into arm-soc don't worry about the Ack.

Mike,

thanks for the Ack, the corresponding pull request has been sent some
hours ago by Jason Cooper. It has not been pulled into arm-soc, so it
is just in time ;)

Sebastian


From paul at pwsan.com  Wed May 29 15:06:12 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 29 May 2013 19:06:12 +0000 (UTC)
Subject: [PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output
 on SoC pad
In-Reply-To: <51A35123.6040600@ti.com>
References: <1367919574-21353-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83EC8C081@DBDE04.ent.ti.com>
 <alpine.DEB.2.00.1305200246080.2656@utopia.booyaka.com>
 <51A35123.6040600@ti.com>
Message-ID: <alpine.DEB.2.02.1305291902450.9052@utopia.booyaka.com>

Salut Beno?t,

On Mon, 27 May 2013, Benoit Cousson wrote:

> On 05/20/2013 04:47 AM, Paul Walmsley wrote:
> > On Fri, 17 May 2013, Hiremath, Vaibhav wrote:
> > 
> >> Tony, Paul and Benoit,
> >>
> >> Any update on this series?
> > 
> > Most of the changes are DT-related, so it should probably go in via 
> > Beno?t.  I'll ack the clock side, but have a comment on patch 2, to be 
> > sent shortly.
> 
> I've tried to apply that patch, but unfortunately, it does depend on
> that one:
> 
> https://patchwork.kernel.org/patch/2212081/
>
> If you did not already pulled the first one I can take both with your
> acked-by.
> Otherwise, I can take only the DTS ones.
> 
> Is that OK?

Will ack that first patch now.  

Vaibhav, looks like that first series is still in RFC form; you might want 
to repost it as a non-RFC series.


- Paul

From paul at pwsan.com  Wed May 29 15:07:12 2013
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 29 May 2013 19:07:12 +0000 (UTC)
Subject: [RFC PATCH 1/3] ARM: AM33XX: clock: Add debugSS clock nodes to
 clock tree
In-Reply-To: <1362396957-30113-2-git-send-email-hvaibhav@ti.com>
References: <hvaibhav@ti.com>
 <1362396957-30113-2-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.02.1305291906160.9052@utopia.booyaka.com>

On Mon, 4 Mar 2013, hvaibhav at ti.com wrote:

> From: Vaibhav Hiremath <hvaibhav at ti.com>
> 
> Represent debugSS clock interface as provided in
> CM_WKUP_DEBUGSS_CLKCTRL register, which includes,
> 	- Clock gate for optional DEBUG_CLKA and DBGSYSCLK
> 	- Clock Mux for TRC_PMD and STM_PMD
> 	- Clock divider for STM and TPIU
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Kevin Hilman <khilman at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Rajendra Nayak <rnayak at ti.com>

Acked-by: Paul Walmsley <paul at pwsan.com>

based on a quick glance.


- Paul


From lee.jones at linaro.org  Wed May 29 15:08:02 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 29 May 2013 20:08:02 +0100
Subject: [PATCH] ARM: ux500: cut chip-select GPIOs from SSP device
In-Reply-To: <1369848742-10451-1-git-send-email-linus.walleij@stericsson.com>
References: <1369848742-10451-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130529190802.GK3012@gmail.com>

On Wed, 29 May 2013, Linus Walleij wrote:

> From: Linus Walleij <linus.walleij at linaro.org>
> 
> What GPIO pin is used with which device on the SSP/SPI bus
> is as board-specific as it gets, so it does not belong here
> in the core SoC file, and it is disabled so it doesn't hurt
> to delete this.

Sounds fine.

Acked-by: Lee Jones <lee.jones at linaro.org>

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed May 29 15:10:28 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 29 May 2013 20:10:28 +0100
Subject: [PATCH] ARM: ux500: use symbolic names for interrupt flags
In-Reply-To: <1369847989-10017-1-git-send-email-linus.walleij@stericsson.com>
References: <1369847989-10017-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130529191028.GL3012@gmail.com>

On Wed, 29 May 2013, Linus Walleij wrote:

> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This switches to including <dt-bindings/interrupt-controller/irq.h>
> and referencing the apropriate flags from there instead of
> open-coding the flag numerals everywhere in the ux500 device
> trees.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/dbx5x0.dtsi  | 104 +++++++++++++++++++++--------------------
>  arch/arm/boot/dts/href.dtsi    |   5 +-
>  arch/arm/boot/dts/snowball.dts |   2 +-
>  arch/arm/boot/dts/stuib.dtsi   |   4 +-
>  4 files changed, 60 insertions(+), 55 deletions(-)

/me likes this.

Acked-by: Lee Jones <lee.jones at linaro.org>

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From gmbnomis at gmail.com  Wed May 29 15:16:57 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Wed, 29 May 2013 21:16:57 +0200
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130529110508.GH17767@MacBook-Pro.local>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130529110508.GH17767@MacBook-Pro.local>
Message-ID: <20130529191657.GA13047@schnuecks.de>

Hi Catalin,

On Wed, May 29, 2013 at 12:05:09PM +0100, Catalin Marinas wrote:
> On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > it needs to handle are kernel mapped only.  However, for example when doing
> > direct I/O, pages with user space mappings may occur.
> 
> After Nico's clarification, I think the original commit introducing this
> function was also incomplete (commit 73be1591 - [ARM] 5545/2: add
> flush_kernel_dcache_page() for ARM) since it ignores highmem pages and
> their flushing could be deferred for a long time.

Yes, I agree.
 
> For my understanding (if I re-read this tread) - basically code like
> this should not leave the user mapping inconsistent:
> 
> kmap()
> ...
> flush_kernel_dcache_page()
> kunmap()

s/user mapping/kernel mapping/ 
The user mapping(s) can be assumed to be consistent when entering
such code. Either there is none or the page was obtained by a
mechanism like __get_user_pages(). Otherwise, we have a problem
anyway when accessing the page via the kernel mapping.

The visibility of a page to user space is just needed for
optimization.  If the page is not visible to user space, we can use
our lazy flushing mechanism (PG_dcache_clean bit) and defer flushing
until the page is mapped into user space (if ever).  Otherwise, we
need to flush the kernel mapping since only that can be dirty.

And, we don't need to do anything in flush_kernel_dcache_page() for
non-aliasing caches, of course.
 
> If we use the atomic variants, we get the cache flushing automatically
> but the kunmap_high() does not flush the cache immediately, so we need
> to handle it in flush_kernel_dcache_page().

Exactly. But only if it is really needed. If we have no user space
mapping and don't lose the kernel mapping, we just may do nothing.
 
> > Thus, continue to do lazy flushing if there are no user space mappings.
> > Otherwise, flush the kernel cache lines directly.
> ...
> >  /*
> > + * Ensure cache coherency for kernel mapping of this page.
> > + *
> > + * If the page only exists in the page cache and there are no user
> > + * space mappings, this is a no-op since the page was already marked
> > + * dirty at creation.  Otherwise, we need to flush the dirty kernel
> > + * cache lines directly.
> > + */
> > +void flush_kernel_dcache_page(struct page *page)
> > +{
> > +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> > +		struct address_space *mapping;
> > +
> > +		mapping = page_mapping(page);
> > +
> > +		if (!mapping || mapping_mapped(mapping))
> > +			__flush_kernel_dcache_page(page);
> > +	}
> > +}
> 
> BTW, does the mapping check optimise anything for the
> flush_kernel_dcache_page() uses? Would we have a mapping anyway (or
> anonymous page) in most cases?


Looking at the relevant uses in the kernel, we have:

    drivers/scsi/libsas/sas_host_smp.c
    drivers/mmc/host/mmc_spi.c
    drivers/block/ps3disk.c
    fs/exec.c
    lib/scatterlist.c
 
That is not much (I omit my usual rant here that many uses of
flush_dcache_page() in drivers are incorrect and should be uses of
flush_kernel_dcache_page() ...).

Without looking at the actual code, we seem to have two basic use
cases:

1. Block drivers (the ones listed above + those using the memory
scatterlist iterator in scatterlist.c)

These will probably almost exclusively use page cache pages for which
we can be lazy.  Other pages only occur in special I/O situations
like direct I/O.

2. fs/exec.c

I think these are anonymous pages only


Thus depending on the actual drivers used, usage can be dominated by
page cache pages on one setup and anon pages on the other.

I prefer the currently proposed way since it prevents massive
overflushing if flush_kernel_dcache_page() is used in an I/O path.


(Btw. I am still puzzled as to why making flush_kernel_dcache_page()
the current nop apparently did not cause problems in fs/exec.c.)

> Otherwise the patch looks good.

Thanks. Especially, thanks for pointing out the highmem case.


- Simon



From jason at lakedaemon.net  Wed May 29 15:17:48 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 15:17:48 -0400
Subject: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
In-Reply-To: <51A65185.1020307@gmail.com>
References: <1368234490-31416-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130529190204.6058.85682@quantum> <51A65185.1020307@gmail.com>
Message-ID: <20130529191748.GW31290@titan.lakedaemon.net>

On Wed, May 29, 2013 at 09:05:41PM +0200, Sebastian Hesselbarth wrote:
> On 05/29/2013 09:02 PM, Mike Turquette wrote:
> >Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
> >>Marvell EBU SoCs share some common clock functions that register core
> >>clocks or clock gates from SoC specific data. These clock drivers are
> >>organized by function and over time the drivers filled up with #ifdefs
> >>to separate different SoC specific code.
> >>
> ...
> >>@Mike: As this only touches MVEBU related code, I suggest to take it
> >>all through the corresponding ARM branch.
> >>
> >Sorry for the tardy response.  This cleanup looks really good.  If it's
> >not too late:
> >
> >Acked-by: Mike Turquette<mturquette at linaro.org>
> >
> >If the branch is already pulled into arm-soc don't worry about the Ack.
> 
> thanks for the Ack, the corresponding pull request has been sent some
> hours ago by Jason Cooper. It has not been pulled into arm-soc, so it
> is just in time ;)

Just talked to Olof, looks like I can squeeze it in ;-)

thx,

Jason.


From jason at lakedaemon.net  Wed May 29 15:30:41 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 15:30:41 -0400
Subject: [GIT PULL 5/5 V2] ARM: mvebu: clock SoC reorg for v3.11
In-Reply-To: <20130528203021.GK31290@titan.lakedaemon.net>
References: <20130528202140.GG31290@titan.lakedaemon.net>
 <20130528202433.GH31290@titan.lakedaemon.net>
 <20130528203021.GK31290@titan.lakedaemon.net>
Message-ID: <20130529193041.GX31290@titan.lakedaemon.net>

Olof,

MikeT's Ack came in, so I cut a v2, no other changes (well, one spelling
correction in the subject line of the last commit).


The following changes since commit 3d9939c92efdd4ced672b94994959ca71b141cb8:

  pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/seb_clk-3.11

for you to fetch changes up to ea7e0bd7e78868bbe6df6834595ef96166dd296a:

  clk: mvebu: disintegrate obsolete file (2013-05-29 19:28:29 +0000)

----------------------------------------------------------------
mvebu clock restructuring for v3.11

 - clk: mvebu
    - reorganize by SoC to remove built up #ifdefs
    - add clk flags per clock gate

Note: this branch only depends on mvebu/pcie in order to prevent managing a
tricky modify/remove file merge conflict.  By rebasing on mvebu/pcie, we are
able to build the resolution into the patch series.  The change is small, and
has been tested by the respective authors.

depends:
 - mvebu/pcie
    - mvebu/of_pci

----------------------------------------------------------------
Sebastian Hesselbarth (10):
      clk: mvebu: introduce per-clock-gate flags
      clk: mvebu: add common clock functions for core clk and clk gating
      clk: mvebu: add Dove SoC-centric clock init
      clk: mvebu: add Kirkwood SoC-centric clock init
      clk: mvebu: add Armada 370 SoC-centric clock init
      clk: mvebu: add Armada XP SoC-centric clock init
      ARM: dove: move DT boards to SoC-centric clock init
      ARM: kirkwood: move DT boards to SoC-centric clock init
      ARM: mvebu: move DT boards to SoC-centric clock init
      clk: mvebu: disintegrate obsolete file

 arch/arm/mach-dove/Kconfig          |   3 +-
 arch/arm/mach-dove/board-dt.c       |   3 +-
 arch/arm/mach-dove/common.c         |   1 -
 arch/arm/mach-kirkwood/Kconfig      |   3 +-
 arch/arm/mach-kirkwood/board-dt.c   |   3 +-
 arch/arm/mach-mvebu/Kconfig         |   5 +-
 arch/arm/mach-mvebu/armada-370-xp.c |   4 +-
 drivers/clk/mvebu/Kconfig           |  25 +-
 drivers/clk/mvebu/Makefile          |   8 +-
 drivers/clk/mvebu/armada-370.c      | 176 ++++++++++
 drivers/clk/mvebu/armada-xp.c       | 210 +++++++++++
 drivers/clk/mvebu/clk-core.c        | 675 ------------------------------------
 drivers/clk/mvebu/clk-core.h        |  18 -
 drivers/clk/mvebu/clk-gating-ctrl.c | 256 --------------
 drivers/clk/mvebu/clk-gating-ctrl.h |  22 --
 drivers/clk/mvebu/clk.c             |  23 --
 drivers/clk/mvebu/common.c          | 163 +++++++++
 drivers/clk/mvebu/common.h          |  48 +++
 drivers/clk/mvebu/dove.c            | 194 +++++++++++
 drivers/clk/mvebu/kirkwood.c        | 247 +++++++++++++
 include/linux/clk/mvebu.h           |  22 --
 21 files changed, 1072 insertions(+), 1037 deletions(-)
 create mode 100644 drivers/clk/mvebu/armada-370.c
 create mode 100644 drivers/clk/mvebu/armada-xp.c
 delete mode 100644 drivers/clk/mvebu/clk-core.c
 delete mode 100644 drivers/clk/mvebu/clk-core.h
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
 delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
 delete mode 100644 drivers/clk/mvebu/clk.c
 create mode 100644 drivers/clk/mvebu/common.c
 create mode 100644 drivers/clk/mvebu/common.h
 create mode 100644 drivers/clk/mvebu/dove.c
 create mode 100644 drivers/clk/mvebu/kirkwood.c
 delete mode 100644 include/linux/clk/mvebu.h


From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:43 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:43 +0200
Subject: [PATCH v5 01/13] net: mv643xx_eth: use phy_disconnect instead of
 phy_detach
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-2-git-send-email-sebastian.hesselbarth@gmail.com>

Using a separated mdio bus driver with mvmdio, phy_detach on network device
removal will not stop the phy and finally lead to NULL pointer dereference
in mvmdio due to non-existent network device. Use phy_disconnect instead
to properly stop phy device from accessing network device prior removal of
the network device.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: I observed this behavior when removing a modular mv643xx_eth driver
after attaching it to a phy handled by (also modular) mvmdio. The mvmdio
conversion has been done in

commit c3a07134e6aa5b93a37f72ffa3d11fadf72bf757
 ("mv643xx_eth: convert to use the Marvell Orion MDIO driver")

and should go back any -stable version with that commit (propably only 3.9)

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 2ad1494..2480a2f 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2805,7 +2805,7 @@ static int mv643xx_eth_remove(struct platform_device *pdev)
 
 	unregister_netdev(mp->dev);
 	if (mp->phy != NULL)
-		phy_detach(mp->phy);
+		phy_disconnect(mp->phy);
 	cancel_work_sync(&mp->tx_timeout_task);
 
 	if (!IS_ERR(mp->clk))
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:42 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:42 +0200
Subject: [PATCH v5 00/13] net: mv643xx_eth DT support and fixes
In-Reply-To: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set picks up work by Florian Fainelli bringing full DT
support to mv643xx_eth and Marvell SoCs using it.

The current v5 patch set drops 1:1 compatibiliy with PPC binding
for two reasons:
(a) PPC parses DT nodes in arch/ppc/sysdev and creates non-DT
    platform_devices itself,
(b) property and node naming for new ethernet devices is slightly
    different ("phy" vs "phy-handle", "marvell," prefix)

Anyway, the two bindings are functionally compatible and PPC bindings
can be converted if desireable. The patch set if fully bisectable and
care has been taken to (a) not reparse on PPC platforms, (b) allow to
use platform_device based registration even if on CONFIG_OF. Not tested
is double registration issues, i.e. if DT nodes are provided but legacy
registration it not yet removed. This double registration should lead
to either non-DT or DT registered device fail on already claimed
ressources.

Also this patch set picks up the opportunity to fix some repeatedly
reported issues with modular mvmdio/mv643xx_eth loading, unloading,
and reloading. It has been tested on SolidRun CuBox (Dove) and
Seagate Dockstar, QNAP, and USI Topkick (Kirkwood) by me or Andrew
Lunn.

Patch 1 fixes an issue introduced with switch to separate mvmdio
driver, where detaching mv643xx_eth from a phy will not stop the
phy state machine and finally dereference the already removed network
device. Using phy_disconnect properly stops the phy state machine
before detaching from it. Perhaps, this patch should go back in
stable (most likely 3.9 only) if mvmdio separation patch went in
there.

Patch 2 makes use of managed devm_ioremap for the last remaining
non-managed resource.

Patches 3-4 prepare DT support for mv643xx_eth by adding a phy_node
pointer to platform_data and exploiting that phy_node when attaching
to a phy.

Patch 5 adds a Kirkwood specific workaround for PORT_SERIAL_CTRL1
register which is reset to loopback mode when clocks are gated.

Patch 6 introduces DT parsing support for mv643xx_eth by adding a
match table for marvell,orion-eth and marvell,kirkwood-eth to the
shared driver and adding a platform_device for each of its child
nodes.

Patches 7-9 add corresponding device tree nodes to Marvell Dove,
Kirkwood, and Orion5x including all boards. Where known, also
the PHY compatible string has been set to what is reported in the
boards boot loader.

Patches 10, 11-12, and 14 finally remove all legacy platform_device
based registration from Dove, Kirkwood, and Orion5x DT setup. For
Kirkwood also now obsolete board specific setup is removed from
common DT board setup, Kconfig, Makefile, and kirkwood_defconfig.

For the patches above I suggest to take Patches 1-6 through David
Miller's branch, and Patches 7-12 through Jason Cooper's when the
former have appeared on mainline linux. The patch set has been based
on v3.10-rc3.

Overall Changelog:
v4->v5: v5 drops Kirkwood MAC address workaround by using DT
  property because OF API does not allow to modify properties
  easily. Instead the current workaround by not gating ge clocks
  is kept. The OF property workaround is postponed until some
  easy to use of_set_property is available.

Sebastian Hesselbarth (13):
  net: mv643xx_eth: use phy_disconnect instead of phy_detach
  net: mv643xx_eth: use managed devm_ioremap for port registers
  net: mv643xx_eth: add phy_node to platform_data struct
  net: mv643xx_eth: use of_phy_connect if phy_node present
  net: mv643xx_eth: proper initialization for Kirkwood SoCs
  net: mv643xx_eth: add DT parsing support
  ARM: dove: add gigabit ethernet and mvmdio device tree nodes
  ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
  ARM: orion5x: add gigabit ethernet and mvmdio device tree nodes
  ARM: dove: remove legacy mv643xx_eth setup
  ARM: kirkwood: remove legacy clk alias for mv643xx_eth
  ARM: kirkwood: remove redundant DT board files
  ARM: orion5x: remove legacy mv643xx_eth board setup

 .../devicetree/bindings/net/marvell-orion-net.txt  |   85 +++++++++
 arch/arm/boot/dts/dove-cubox.dts                   |    7 +
 arch/arm/boot/dts/dove.dtsi                        |   35 ++++
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   16 ++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   16 ++
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   17 ++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   28 +++
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   16 ++
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |   30 +++
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   16 ++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   16 ++
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   24 +++
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   16 ++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   28 +++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   27 +++
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   16 ++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   16 ++
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |   16 ++
 arch/arm/boot/dts/kirkwood-topkick.dts             |   16 ++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   16 ++
 arch/arm/boot/dts/kirkwood.dtsi                    |   52 ++++++
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |   17 ++
 arch/arm/boot/dts/orion5x.dtsi                     |   29 +++
 arch/arm/configs/kirkwood_defconfig                |   16 --
 arch/arm/mach-dove/board-dt.c                      |    9 -
 arch/arm/mach-kirkwood/Kconfig                     |  117 ------------
 arch/arm/mach-kirkwood/Makefile                    |   16 --
 arch/arm/mach-kirkwood/board-dnskw.c               |    7 -
 arch/arm/mach-kirkwood/board-dockstar.c            |   32 ----
 arch/arm/mach-kirkwood/board-dreamplug.c           |   35 ----
 arch/arm/mach-kirkwood/board-dt.c                  |   64 +------
 arch/arm/mach-kirkwood/board-goflexnet.c           |   34 ----
 arch/arm/mach-kirkwood/board-guruplug.c            |   33 ----
 arch/arm/mach-kirkwood/board-ib62x0.c              |   29 ---
 arch/arm/mach-kirkwood/board-iconnect.c            |   10 -
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c      |   34 ----
 arch/arm/mach-kirkwood/board-km_kirkwood.c         |   44 -----
 arch/arm/mach-kirkwood/board-lsxl.c                |   16 --
 arch/arm/mach-kirkwood/board-mplcec4.c             |   14 --
 arch/arm/mach-kirkwood/board-ns2.c                 |   35 ----
 arch/arm/mach-kirkwood/board-openblocks_a6.c       |   26 ---
 arch/arm/mach-kirkwood/board-readynas.c            |    6 -
 arch/arm/mach-kirkwood/board-ts219.c               |   13 --
 arch/arm/mach-kirkwood/board-usi_topkick.c         |   29 ---
 arch/arm/mach-orion5x/edmini_v2-setup.c            |   10 -
 drivers/net/ethernet/marvell/mv643xx_eth.c         |  194 ++++++++++++++++++--
 include/linux/mv643xx_eth.h                        |    2 +
 54 files changed, 754 insertions(+), 644 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-orion-net.txt
 delete mode 100644 arch/arm/mach-kirkwood/board-dockstar.c
 delete mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-goflexnet.c
 delete mode 100644 arch/arm/mach-kirkwood/board-guruplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ib62x0.c
 delete mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
 delete mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ns2.c
 delete mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
 delete mode 100644 arch/arm/mach-kirkwood/board-usi_topkick.c
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:44 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:44 +0200
Subject: [PATCH v5 02/13] net: mv643xx_eth: use managed devm_ioremap for port
 registers
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-3-git-send-email-sebastian.hesselbarth@gmail.com>

Make use of managed devm_ioremap and remove corresponding iounmap.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org       
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 2480a2f..19964e9 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2470,7 +2470,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	if (msp == NULL)
 		return -ENOMEM;
 
-	msp->base = ioremap(res->start, resource_size(res));
+	msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 	if (msp->base == NULL)
 		return -ENOMEM;
 
@@ -2498,7 +2498,6 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
 {
 	struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
 
-	iounmap(msp->base);
 	if (!IS_ERR(msp->clk))
 		clk_disable_unprepare(msp->clk);
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:45 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:45 +0200
Subject: [PATCH v5 03/13] net: mv643xx_eth: add phy_node to platform_data
 struct
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-4-git-send-email-sebastian.hesselbarth@gmail.com>

This adds a struct device_node pointer for a phy passed by phandle
to mv643xx_eth node.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 include/linux/mv643xx_eth.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 141d395..6e8215b 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -30,6 +30,7 @@ struct mv643xx_eth_shared_platform_data {
 #define MV643XX_ETH_PHY_ADDR(x)		(0x80 | (x))
 #define MV643XX_ETH_PHY_NONE		0xff
 
+struct device_node;
 struct mv643xx_eth_platform_data {
 	/*
 	 * Pointer back to our parent instance, and our port number.
@@ -41,6 +42,7 @@ struct mv643xx_eth_platform_data {
 	 * Whether a PHY is present, and if yes, at which address.
 	 */
 	int			phy_addr;
+	struct device_node	*phy_node;
 
 	/*
 	 * Use this MAC address if it is valid, overriding the
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:46 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:46 +0200
Subject: [PATCH v5 04/13] net: mv643xx_eth: use of_phy_connect if phy_node
 present
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-5-git-send-email-sebastian.hesselbarth@gmail.com>

This connects to a phy node passed to the port device instead of probing
the phy by phy_addr.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |   25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 19964e9..fa8c84a 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -60,6 +60,7 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/of_mdio.h>
 
 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
 static char mv643xx_eth_driver_version[] = "1.4";
@@ -2715,17 +2716,27 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	netif_set_real_num_tx_queues(dev, mp->txq_count);
 	netif_set_real_num_rx_queues(dev, mp->rxq_count);
 
-	if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
+	err = 0;
+	if (pd->phy_node) {
+		mp->phy = of_phy_connect(mp->dev, pd->phy_node,
+					 mv643xx_eth_adjust_link, 0,
+					 PHY_INTERFACE_MODE_GMII);
+		if (!mp->phy)
+			err = -ENODEV;
+	} else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
 		mp->phy = phy_scan(mp, pd->phy_addr);
 
-		if (IS_ERR(mp->phy)) {
+		if (IS_ERR(mp->phy))
 			err = PTR_ERR(mp->phy);
-			if (err == -ENODEV)
-				err = -EPROBE_DEFER;
-			goto out;
-		}
-		phy_init(mp, pd->speed, pd->duplex);
+		else
+			phy_init(mp, pd->speed, pd->duplex);
 	}
+	if (err == -ENODEV) {
+		err = -EPROBE_DEFER;
+		goto out;
+	}
+	if (err)
+		goto out;
 
 	SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:47 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:47 +0200
Subject: [PATCH v5 05/13] net: mv643xx_eth: proper initialization for Kirkwood
 SoCs
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-6-git-send-email-sebastian.hesselbarth@gmail.com>

Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
MAC address register contents on clock gating but also some important
registers are reset to values that would break ethernet. This patch
clears the CLK125_BYPASS_EN bit for DT enabled Kirkwood only by using
of_device_is_compatible() instead of #ifdefs. Non-DT Kirkwood is not
affected as it installs a clock gating workaround because of the MAC
address issue above. Other Orion SoCs do not suffer from register reset,
do not have the bit in question, or do not have the register at all.
Moreover, system controllers on PPC using this driver should also be
protected from clearing that bit.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: In contrast to the reset value of 0 for CLK125_BYPASS_EN bit as
stated in Kirkwood datasheet, we confirmed that reset value is 1 instead.
Either datasheet is wrong about it, there is some post-boot self-check or
BootROM flips that bit.

Changelog
v4->v5:
- check for device compatible instead of machine compatible
  (Suggested by Jason Gunthorpe)

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index fa8c84a..5b375ee 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -116,6 +116,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define  LINK_UP			0x00000002
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
+#define PORT_SERIAL_CONTROL1		0x004c
+#define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
 #define TX_BW_BURST			0x005c
@@ -2701,6 +2703,15 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
 	mp->dev = dev;
 
+	/* Kirkwood resets some registers on gated clocks. Especially
+	 * CLK125_BYPASS_EN must be cleared but is not available on
+	 * all other SoCs/System Controllers using this driver.
+	 */
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "marvell,kirkwood-eth-port"))
+		wrlp(mp, PORT_SERIAL_CONTROL1,
+		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
+
 	/*
 	 * Start with a default rate, and if there is a clock, allow
 	 * it to override the default.
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:52 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:52 +0200
Subject: [PATCH v5 10/13] ARM: dove: remove legacy mv643xx_eth setup
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-11-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards anymore.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-dove/board-dt.c |    9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b14280..048e942 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -34,10 +34,6 @@ static void __init dove_legacy_clk_init(void)
 	clkspec.np = np;
 	clkspec.args_count = 1;
 
-	clkspec.args[0] = CLOCK_GATING_BIT_GBE;
-	orion_clkdev_add(NULL, "mv643xx_eth_port.0",
-			 of_clk_get_from_provider(&clkspec));
-
 	clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
 	orion_clkdev_add("0", "pcie",
 			 of_clk_get_from_provider(&clkspec));
@@ -53,10 +49,6 @@ static void __init dove_of_clk_init(void)
 	dove_legacy_clk_init();
 }
 
-static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
-	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
-};
-
 static void __init dove_dt_init(void)
 {
 	pr_info("Dove 88AP510 SoC\n");
@@ -70,7 +62,6 @@ static void __init dove_dt_init(void)
 	dove_of_clk_init();
 
 	/* Internal devices not ported to DT yet */
-	dove_ge00_init(&dove_dt_ge00_data);
 	dove_pcie_init(1, 1);
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:51 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:51 +0200
Subject: [PATCH v5 09/13] ARM: orion5x: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-10-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Orion5x boards. Phy nodes are also added with reg property set on a
per-board basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v3->v4:
- convert to new device tree binding

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |   17 ++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   29 ++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 0077fc8..c7e2efd 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -53,3 +53,20 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	&ethphy: ethernet-phy {
+		device-type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		phy-handle = <&ethphy>;
+	};
+};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 892c64e..6fe45d5 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -132,5 +132,34 @@
 			interrupts = <28>;
 			status = "okay";
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72004 0x84>;
+			interrupts = <22>;
+			status = "disabled";
+
+			/* add phy nodes in board file */
+		};
+
+		eth: ethernet-controller at 72000 {
+			compatible = "marvell,orion-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72000 0x4000>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet-port at 0 {
+				device_type = "network";
+				compatible = "marvell,orion-eth-port";
+				reg = <0>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				/* set phy-handle property in board file */
+			};
+		};
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:53 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:53 +0200
Subject: [PATCH v5 11/13] ARM: kirkwood: remove legacy clk alias for
 mv643xx_eth
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-12-git-send-email-sebastian.hesselbarth@gmail.com>

With all boards converted to DT enabled mv643xx_eth we can now
remove the clock alias for gbe clocks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/board-dt.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..8db388a 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -66,12 +66,10 @@ static void __init kirkwood_legacy_clk_init(void)
 	 */
 	clkspec.args[0] = CGC_BIT_GE0;
 	clk = of_clk_get_from_provider(&clkspec);
-	orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
 	clk_prepare_enable(clk);
 
 	clkspec.args[0] = CGC_BIT_GE1;
 	clk = of_clk_get_from_provider(&clkspec);
-	orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
 	clk_prepare_enable(clk);
 }
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:49 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:49 +0200
Subject: [PATCH v5 07/13] ARM: dove: add gigabit ethernet and mvmdio device
 tree nodes
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-8-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds orion-eth and mvmdio device tree nodes for DT enabled
Dove boards. As there is only one ethernet controller on Dove, a default
phy node is also added with a note to set its reg property on a per-board
basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v3->v4:
- convert to new device tree binding

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/dove-cubox.dts |    7 +++++++
 arch/arm/boot/dts/dove.dtsi      |   35 +++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7e3065a..02618fa 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -49,6 +49,13 @@
 &uart0 { status = "okay"; };
 &sata0 { status = "okay"; };
 &i2c0 { status = "okay"; };
+&mdio { status = "okay"; };
+&eth { status = "okay"; };
+
+&ethphy {
+	compatible = "marvell,88e1310";
+	reg = <1>;
+};
 
 &sdio0 {
 	status = "okay";
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 6cab468..8612658 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -258,5 +258,40 @@
 				dmacap,xor;
 			};
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72004 0x84>;
+			interrupts = <30>;
+			clocks = <&gate_clk 2>;
+			status = "disabled";
+
+			ethphy: ethernet-phy {
+				device-type = "ethernet-phy";
+				/* set phy address in board file */
+			};
+		};
+
+		eth: ethernet-controller at 72000 {
+			compatible = "marvell,orion-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72000 0x4000>;
+			clocks = <&gate_clk 2>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet-port at 0 {
+				device_type = "network";
+				compatible = "marvell,orion-eth-port";
+				reg = <0>;
+				interrupts = <29>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				phy-handle = <&ethphy>;
+			};
+		};
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:55 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:55 +0200
Subject: [PATCH v5 13/13] ARM: orion5x: remove legacy mv643xx_eth board setup
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-14-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards. This patch removes eth setup
for all orion5x DT board files.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-orion5x/edmini_v2-setup.c |   10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 1476155..d9de926 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -24,7 +24,6 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
@@ -96,14 +95,6 @@ static struct platform_device edmini_v2_nor_flash = {
 };
 
 /*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data edmini_v2_eth_data = {
-	.phy_addr	= 8,
-};
-
-/*****************************************************************************
  * RTC 5C372a on I2C bus
  ****************************************************************************/
 
@@ -152,7 +143,6 @@ void __init edmini_v2_init(void)
 	 * Configure peripherals.
 	 */
 	orion5x_ehci0_init();
-	orion5x_eth_init(&edmini_v2_eth_data);
 
 	mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
 			      EDMINI_V2_NOR_BOOT_SIZE);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:48 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:48 +0200
Subject: [PATCH v5 06/13] net: mv643xx_eth: add DT parsing support
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-7-git-send-email-sebastian.hesselbarth@gmail.com>

This adds device tree parsing support for the shared driver of mv643xx_eth.
As the bindings are slightly different from current PPC bindings new binding
documentation is also added. Following PPC-style device setup, the shared
driver now also adds port platform_devices and sets up port platform_data.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: Although different, device tree bindings are compatible with PPC
bindings. As I do not have access to any PPC platform using mv643xx_eth,
I leave conversion ("phy" vs "phy-handle") and compatible string name
up to PPC guys.

Due to hang reports for modular built mvmdio and mv643xx_eth, I have
tested module loading/unloading/reloading on CuBox (Dove) and Dockstar
(Kirkwood) without any issues for the whole patch set.

Changelog:
v5->v4:
- add Kirkwood specific compatible string

v3->v4:
- separation of independent patches (phy, of_mdio, devm)
- stand-alone device tree binding compatible to existing mv64x60 binding
- device node match for shared driver only
- device node registration for port drivers
- properly return -EPROBE_DEFER on missing of phy (Reported by Simon Baatz)

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 .../devicetree/bindings/net/marvell-orion-net.txt  |   85 +++++++++++
 drivers/net/ethernet/marvell/mv643xx_eth.c         |  153 +++++++++++++++++++-
 2 files changed, 234 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-orion-net.txt

diff --git a/Documentation/devicetree/bindings/net/marvell-orion-net.txt b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
new file mode 100644
index 0000000..a73b79f
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
@@ -0,0 +1,85 @@
+Marvell Orion/Discovery ethernet controller
+=============================================
+
+The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
+(Kirkwood, Dove, Orion5x, and Discovery Innovation) and as part of Marvell
+Discovery system controller chips (mv64[345]60).
+
+The Discovery ethernet controller is described with two levels of nodes. The
+first level describes the ethernet controller itself and the second level
+describes up to 3 ethernet port nodes within that controller. The reason for
+the multiple levels is that the port registers are interleaved within a single
+set of controller registers. Each port node describes port-specific properties.
+
+Note: The above separation is only true for Discovery system controllers.
+For Orion SoCs we stick to the separation, although there each controller has
+only one port associated. Multiple ports are implemented as multiple single-port
+controllers. As Kirkwood has some issues with proper initialization after reset,
+an extra compatible string is added for it.
+
+* Ethernet controller node
+
+Required controller properties:
+ - #address-cells: shall be 1.
+ - #size-cells: shall be 0.
+ - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
+ - reg: address and length of the controller registers.
+
+Optional controller properties:
+ - clocks: phandle reference to the controller clock.
+ - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
+
+* Ethernet port node
+
+Required port properties:
+ - device_type: shall be "network".
+ - compatible: shall be one of "marvell,orion-eth-port",
+      "marvell,kirkwood-eth-port".
+ - reg: port number relative to ethernet controller, shall be 0, 1, or 2.
+ - interrupts: port interrupt.
+ - local-mac-address: 6 bytes MAC address.
+
+Optional port properties:
+ - marvell,tx-queue-size: size of the transmit ring buffer.
+ - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
+ - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
+ - marvell,rx-queue-size: size of the receive ring buffer.
+ - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
+ - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
+
+and
+
+ - phy-handle: phandle reference to ethernet PHY.
+
+or
+
+ - speed: port speed if no PHY connected.
+ - duplex: port mode if no PHY connected.
+
+* Node example:
+
+mdio-bus {
+	...
+	ethphy: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		...
+	};
+};
+
+eth: ethernet-controller at 72000 {
+	compatible = "marvell,orion-eth";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x72000 0x2000>;
+	clocks = <&gate_clk 2>;
+	marvell,tx-checksum-limit = <1600>;
+
+	ethernet at 0 {
+		device_type = "network";
+		compatible = "marvell,orion-eth-port";
+		reg = <0>;
+		interrupts = <29>;
+		phy-handle = <&ethphy>;
+		local-mac-address = [00 00 00 00 00 00];
+	};
+};
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 5b375ee..5acaaad 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -60,6 +60,9 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_net.h>
 #include <linux/of_mdio.h>
 
 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
@@ -2453,13 +2456,148 @@ static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
 	}
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id mv643xx_eth_shared_ids[] = {
+	{ .compatible = "marvell,orion-eth", },
+	{ .compatible = "marvell,kirkwood-eth", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
+#endif
+
+#if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
+#define mv643xx_eth_property(_np, _name, _v)				\
+	do {								\
+		u32 tmp;						\
+		if (!of_property_read_u32(_np, "marvell," _name, &tmp))	\
+			_v = tmp;					\
+	} while (0)
+
+static struct platform_device *port_platdev[3];
+
+static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
+					  struct device_node *pnp)
+{
+	struct platform_device *ppdev;
+	struct mv643xx_eth_platform_data ppd;
+	struct resource res;
+	const char *mac_addr;
+	int ret;
+
+	memset(&ppd, 0, sizeof(ppd));
+	ppd.shared = pdev;
+
+	memset(&res, 0, sizeof(res));
+	if (!of_irq_to_resource(pnp, 0, &res)) {
+		dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
+		dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
+		return -EINVAL;
+	}
+
+	if (ppd.port_number >= 3) {
+		dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
+		return -EINVAL;
+	}
+
+	mac_addr = of_get_mac_address(pnp);
+	if (mac_addr)
+		memcpy(ppd.mac_addr, mac_addr, 6);
+
+	mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
+	mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
+	mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
+	mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
+	mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
+	mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
+
+	ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
+	if (!ppd.phy_node) {
+		ppd.phy_addr = MV643XX_ETH_PHY_NONE;
+		of_property_read_u32(pnp, "speed", &ppd.speed);
+		of_property_read_u32(pnp, "duplex", &ppd.duplex);
+	}
+
+	ppdev = platform_device_alloc(MV643XX_ETH_NAME, ppd.port_number);
+	if (!ppdev)
+		return -ENOMEM;
+	ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+	ret = platform_device_add_resources(ppdev, &res, 1);
+	if (ret)
+		goto port_err;
+
+	ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
+	if (ret)
+		goto port_err;
+
+	ret = platform_device_add(ppdev);
+	if (ret)
+		goto port_err;
+
+	port_platdev[ppd.port_number] = ppdev;
+
+	return 0;
+
+port_err:
+	platform_device_put(ppdev);
+	return ret;
+}
+
+static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
+{
+	struct mv643xx_eth_shared_platform_data *pd;
+	struct device_node *pnp, *np = pdev->dev.of_node;
+	int ret;
+
+	/* bail out if not registered from DT */
+	if (!np)
+		return 0;
+
+	pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return -ENOMEM;
+	pdev->dev.platform_data = pd;
+
+	mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
+
+	for_each_available_child_of_node(np, pnp) {
+		ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
+static void mv643xx_eth_shared_of_remove(void)
+{
+	int n;
+
+	for (n = 0; n < 3; n++) {
+		platform_device_del(port_platdev[n]);
+		port_platdev[n] = NULL;
+	}
+}
+#else
+static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
+{
+	return 0
+}
+
+#define mv643xx_eth_shared_of_remove()
+#endif
+
 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 {
 	static int mv643xx_eth_version_printed;
-	struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
+	struct mv643xx_eth_shared_platform_data *pd;
 	struct mv643xx_eth_shared_private *msp;
 	const struct mbus_dram_target_info *dram;
 	struct resource *res;
+	int ret;
 
 	if (!mv643xx_eth_version_printed++)
 		pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
@@ -2472,6 +2610,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
 	if (msp == NULL)
 		return -ENOMEM;
+	platform_set_drvdata(pdev, msp);
 
 	msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 	if (msp->base == NULL)
@@ -2488,12 +2627,15 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	if (dram)
 		mv643xx_eth_conf_mbus_windows(msp, dram);
 
+	ret = mv643xx_eth_shared_of_probe(pdev);
+	if (ret)
+		return ret;
+	pd = pdev->dev.platform_data;
+
 	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
 					pd->tx_csum_limit : 9 * 1024;
 	infer_hw_params(msp);
 
-	platform_set_drvdata(pdev, msp);
-
 	return 0;
 }
 
@@ -2501,9 +2643,9 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
 {
 	struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
 
+	mv643xx_eth_shared_of_remove();
 	if (!IS_ERR(msp->clk))
 		clk_disable_unprepare(msp->clk);
-
 	return 0;
 }
 
@@ -2513,6 +2655,7 @@ static struct platform_driver mv643xx_eth_shared_driver = {
 	.driver = {
 		.name	= MV643XX_ETH_SHARED_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
 	},
 };
 
@@ -2721,6 +2864,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	if (!IS_ERR(mp->clk)) {
 		clk_prepare_enable(mp->clk);
 		mp->t_clk = clk_get_rate(mp->clk);
+	} else if (!IS_ERR(mp->shared->clk)) {
+		mp->t_clk = clk_get_rate(mp->shared->clk);
 	}
 
 	set_params(mp, pd);
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:50 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:50 +0200
Subject: [PATCH v5 08/13] ARM: kirkwood: add gigabit ethernet and mvmdio
 device tree nodes
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-9-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Kirkwood boards. Phy nodes are also added with reg property set on a
per-board basis.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Changelog:
v4->v5:
- use Kirkwood specific compatible string

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/kirkwood-cloudbox.dts            |   16 ++++++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi              |   16 ++++++
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   17 +++++++
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   28 +++++++++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts           |   16 ++++++
 .../arm/boot/dts/kirkwood-guruplug-server-plus.dts |   30 +++++++++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts              |   16 ++++++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   16 ++++++
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |   24 +++++++++
 arch/arm/boot/dts/kirkwood-is2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts         |   16 ++++++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi               |   28 +++++++++++
 arch/arm/boot/dts/kirkwood-mplcec4.dts             |   27 ++++++++++
 .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts  |   16 ++++++
 arch/arm/boot/dts/kirkwood-ns2-common.dtsi         |   16 ++++++
 arch/arm/boot/dts/kirkwood-ns2.dts                 |    2 +
 arch/arm/boot/dts/kirkwood-ns2lite.dts             |    2 +
 arch/arm/boot/dts/kirkwood-ns2max.dts              |    2 +
 arch/arm/boot/dts/kirkwood-ns2mini.dts             |    2 +
 arch/arm/boot/dts/kirkwood-openblocks_a6.dts       |   16 ++++++
 arch/arm/boot/dts/kirkwood-topkick.dts             |   16 ++++++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts          |    4 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi              |   16 ++++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   52 ++++++++++++++++++++
 25 files changed, 398 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e..03e1b68 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -87,3 +87,19 @@
 		gpios = <&gpio0 17 0>;
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac0..7c8bc17 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -217,3 +217,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6..b5aebbc 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -91,3 +91,20 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		compatible = "marvell,88e1116";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d..e0c93d4 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -99,3 +99,31 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be..aba5849 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -170,3 +170,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97d..210dfb9 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -96,3 +96,33 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		compatible = "marvell,88e1121";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		compatible = "marvell,88e1121";
+		reg = <1>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1a..fff3e65 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -119,3 +119,19 @@
 
 
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74..cfaf6bc 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -168,3 +168,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 11 {
+		device_type = "ethernet-phy";
+		reg = <11>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94..315f095 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -191,3 +191,27 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy1: ethernet-phy at 11 {
+		device_type = "ethernet-phy";
+		reg = <11>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0a..2e5fe72 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd054..f9194b1 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -43,3 +43,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4..dcc6470 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -201,3 +201,31 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy at 8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 7588241..ceac0de 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -182,3 +182,30 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 1 {
+		device_type = "ethernet-phy";
+		reg = <1>;
+	};
+
+	ethphy1: ethernet-phy at 2 {
+		device_type = "ethernet-phy";
+		reg = <2>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port at 0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab..b66b2cd 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -178,3 +178,19 @@
                 };
         };
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd92..6a48bfd 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -82,3 +82,19 @@
 	};
 
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy {
+		device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf..8ffd552 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4e..16332f8 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -28,3 +28,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6..68d767d 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -47,3 +47,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab..5b1b17b 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -48,3 +48,5 @@
 		};
 	};
 };
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f724..f8be3e3 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -210,3 +210,19 @@
 		};
         };
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b..34eacf2 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -201,3 +201,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy at 0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c83..0bd67bf 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -49,4 +49,6 @@
 			gpios = <&gpio0 16 1>;
 		};
 	};
-};
\ No newline at end of file
+};
+
+&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95d..a675278 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -49,4 +49,6 @@
 			gpios = <&gpio1 5 1>;
 		};
 	};
-};
\ No newline at end of file
+};
+
+&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..68fe091 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -76,3 +76,19 @@
 		};
 	};
 };
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy {
+		device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port at 0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6..2cd1f23 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -202,5 +202,57 @@
 			clocks = <&gate_clk 4>;
 			status = "disabled";
 		};
+
+		mdio: mdio-bus at 72004 {
+			compatible = "marvell,orion-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72004 0x84>;
+			interrupts = <46>;
+			clocks = <&gate_clk 0>;
+			status = "disabled";
+
+			/* add phy nodes in board file */
+		};
+
+		eth0: ethernet-controller at 72000 {
+			compatible = "marvell,kirkwood-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x72000 0x4000>;
+			clocks = <&gate_clk 0>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet0-port at 0 {
+				device_type = "network";
+				compatible = "marvell,kirkwood-eth-port";
+				reg = <0>;
+				interrupts = <11>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				/* set phy-handle property in board file */
+			};
+		};
+
+		eth1: ethernet-controller at 76000 {
+			compatible = "marvell,kirkwood-eth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x76000 0x4000>;
+			clocks = <&gate_clk 19>;
+			marvell,tx-checksum-limit = <1600>;
+			status = "disabled";
+
+			ethernet1-port at 1 {
+				device_type = "network";
+				compatible = "marvell,kirkwood-eth-port";
+				reg = <1>;
+				interrupts = <15>;
+				/* overwrite MAC address in bootloader */
+				local-mac-address = [00 00 00 00 00 00];
+				/* set phy-handle property in board file */
+			};
+		};
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed May 29 15:32:54 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 29 May 2013 21:32:54 +0200
Subject: [PATCH v5 12/13] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1369855975-21489-13-git-send-email-sebastian.hesselbarth@gmail.com>

With DT support for mv643xx_eth board specific init for some boards now
is unneccessary. Remove those board files, Kconfig entries, and
corresponding entries in kirkwood_defconfig.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
the lock-up is not caused by accessing clock gating registers but rather
non-existent device registers. This will be addressed by dtsi separation
for kirkwood and bobcat SoC variants.

Changelog:
v3->v4:
- remove more boards that don't require board specific setup

Cc: David Miller <davem at davemloft.net>
Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/configs/kirkwood_defconfig           |   16 ----
 arch/arm/mach-kirkwood/Kconfig                |  117 -------------------------
 arch/arm/mach-kirkwood/Makefile               |   16 ----
 arch/arm/mach-kirkwood/board-dnskw.c          |    7 --
 arch/arm/mach-kirkwood/board-dockstar.c       |   32 -------
 arch/arm/mach-kirkwood/board-dreamplug.c      |   35 --------
 arch/arm/mach-kirkwood/board-dt.c             |   62 +------------
 arch/arm/mach-kirkwood/board-goflexnet.c      |   34 -------
 arch/arm/mach-kirkwood/board-guruplug.c       |   33 -------
 arch/arm/mach-kirkwood/board-ib62x0.c         |   29 ------
 arch/arm/mach-kirkwood/board-iconnect.c       |   10 ---
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   34 -------
 arch/arm/mach-kirkwood/board-km_kirkwood.c    |   44 ----------
 arch/arm/mach-kirkwood/board-lsxl.c           |   16 ----
 arch/arm/mach-kirkwood/board-mplcec4.c        |   14 ---
 arch/arm/mach-kirkwood/board-ns2.c            |   35 --------
 arch/arm/mach-kirkwood/board-openblocks_a6.c  |   26 ------
 arch/arm/mach-kirkwood/board-readynas.c       |    6 --
 arch/arm/mach-kirkwood/board-ts219.c          |   13 ---
 arch/arm/mach-kirkwood/board-usi_topkick.c    |   29 ------
 20 files changed, 1 insertion(+), 607 deletions(-)
 delete mode 100644 arch/arm/mach-kirkwood/board-dockstar.c
 delete mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-goflexnet.c
 delete mode 100644 arch/arm/mach-kirkwood/board-guruplug.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ib62x0.c
 delete mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
 delete mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
 delete mode 100644 arch/arm/mach-kirkwood/board-ns2.c
 delete mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
 delete mode 100644 arch/arm/mach-kirkwood/board-usi_topkick.c

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252..540ca51 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -30,27 +30,11 @@ CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_T5325=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
-CONFIG_MACH_CLOUDBOX_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
-CONFIG_MACH_DOCKSTAR_DT=y
-CONFIG_MACH_DREAMPLUG_DT=y
-CONFIG_MACH_GOFLEXNET_DT=y
-CONFIG_MACH_GURUPLUG_DT=y
-CONFIG_MACH_IB62X0_DT=y
-CONFIG_MACH_ICONNECT_DT=y
-CONFIG_MACH_INETSPACE_V2_DT=y
-CONFIG_MACH_IOMEGA_IX2_200_DT=y
-CONFIG_MACH_KM_KIRKWOOD_DT=y
 CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_MPLCEC4_DT=y
-CONFIG_MACH_NETSPACE_LITE_V2_DT=y
-CONFIG_MACH_NETSPACE_MAX_V2_DT=y
-CONFIG_MACH_NETSPACE_MINI_V2_DT=y
-CONFIG_MACH_NETSPACE_V2_DT=y
 CONFIG_MACH_NSA310_DT=y
-CONFIG_MACH_OPENBLOCKS_A6_DT=y
 CONFIG_MACH_READYNAS_DT=y
-CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PREEMPT=y
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..c2fd30b 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -146,13 +146,6 @@ config ARCH_KIRKWOOD_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Kirkwood using flattened device tree.
 
-config MACH_CLOUDBOX_DT
-	bool "LaCie CloudBox NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  CloudBox NAS, using Flattened Device Tree.
-
 config MACH_DLINK_KIRKWOOD_DT
 	bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -161,69 +154,6 @@ config MACH_DLINK_KIRKWOOD_DT
 	  Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
 	  using Flattened Device Tree.
 
-config MACH_DOCKSTAR_DT
-	bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Seagate FreeAgent Dockstar (Flattened Device Tree).
-
-config MACH_DREAMPLUG_DT
-	bool "Marvell DreamPlug (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Marvell DreamPlug (Flattened Device Tree).
-
-config MACH_GOFLEXNET_DT
-	bool "Seagate GoFlex Net (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Seagate GoFlex Net (Flattened Device Tree).
-
-config MACH_GURUPLUG_DT
-	bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Marvell GuruPlug Reference Board (Flattened Device Tree).
-
-config MACH_IB62X0_DT
-	bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
-	  Flattened Device Tree.
-
-config MACH_ICONNECT_DT
-	bool "Iomega Iconnect (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here to enable Iomega Iconnect support.
-
-config MACH_INETSPACE_V2_DT
-	bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Internet Space v2 NAS, using Flattened Device Tree.
-
-config MACH_IOMEGA_IX2_200_DT
-	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Iomega StorCenter ix2-200 (Flattened Device Tree).
-
-config MACH_KM_KIRKWOOD_DT
-	bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
-
 config MACH_LSXL_DT
 	bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -239,39 +169,6 @@ config MACH_MPLCEC4_DT
 	  Say 'Y' here if you want your kernel to support the
 	  MPL CEC4 (Flattened Device Tree).
 
-config MACH_NETSPACE_LITE_V2_DT
-	bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space Lite v2 NAS, using Flattened Device Tree.
-
-config MACH_NETSPACE_MAX_V2_DT
-	bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space Max v2 NAS, using Flattened Device Tree.
-
-config MACH_NETSPACE_MINI_V2_DT
-	bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space Mini v2 NAS using Flattened Device Tree.
-
-	  This board is embedded in a product named CloudBox, which
-	  provides automatic backup on a 100GB cloud storage. This
-	  should not confused with a more recent LaCie NAS also named
-	  CloudBox. For this last, the disk capacity is 1TB or above.
-
-config MACH_NETSPACE_V2_DT
-	bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the LaCie
-	  Network Space v2 NAS, using Flattened Device Tree.
-
 config MACH_NSA310_DT
 	bool "ZyXEL NSA-310 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -280,13 +177,6 @@ config MACH_NSA310_DT
 	  Say 'Y' here if you want your kernel to support the
 	  ZyXEL NSA-310 board (Flattened Device Tree).
 
-config MACH_OPENBLOCKS_A6_DT
-	bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Plat'Home OpenBlocks A6 (Flattened Device Tree).
-
 config MACH_READYNAS_DT
 	bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -296,13 +186,6 @@ config MACH_READYNAS_DT
 	  Say 'Y' here if you want your kernel to support the
 	  NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
-config MACH_TOPKICK_DT
-	bool "USI Topkick (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  USI Topkick, using Flattened Device Tree
-
 config MACH_TS219_DT
 	bool "Device Tree for QNAP TS-11X, TS-21X NAS"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735..8e7fa4f 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -20,25 +20,9 @@ obj-$(CONFIG_MACH_TS219)		+= ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
-obj-$(CONFIG_MACH_CLOUDBOX_DT)		+= board-ns2.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)	+= board-dnskw.o
-obj-$(CONFIG_MACH_DOCKSTAR_DT)		+= board-dockstar.o
-obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
-obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
-obj-$(CONFIG_MACH_GURUPLUG_DT)		+= board-guruplug.o
-obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
-obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
-obj-$(CONFIG_MACH_INETSPACE_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
-obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)	+= board-km_kirkwood.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
 obj-$(CONFIG_MACH_MPLCEC4_DT)		+= board-mplcec4.o
-obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)	+= board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)		+= board-nsa310.o
-obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)	+= board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
-obj-$(CONFIG_MACH_TOPKICK_DT)		+= board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index a1aa87f..2af7a95 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,14 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data dnskw_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 /* Register any GPIO for output and set the value */
 static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 {
@@ -36,8 +31,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 
 void __init dnskw_init(void)
 {
-	kirkwood_ge00_init(&dnskw_ge00_data);
-
 	/* Set NAS to turn back on after a power failure */
 	dnskw_gpio_register(37, "dnskw:power:recover", 1);
 }
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
deleted file mode 100644
index d7196db..0000000
--- a/arch/arm/mach-kirkwood/board-dockstar.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-dockstar.c
- *
- * Seagate FreeAgent Dockstar Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * Copied and modified for Seagate GoFlex Net support by
- * Joshua Coombs <josh.coombs at gmail.com> based on ArchLinux ARM's
- * GoFlex kernel patches.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data dockstar_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init dockstar_dt_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&dockstar_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
deleted file mode 100644
index 0903242..0000000
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-dreamplug.c
- *
- * Marvell DreamPlug Reference Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-void __init dreamplug_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&dreamplug_ge00_data);
-	kirkwood_ge01_init(&dreamplug_ge01_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 8db388a..e9c444c 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -104,86 +104,26 @@ static void __init kirkwood_dt_init(void)
 	kexec_reinit = kirkwood_enable_pcie;
 #endif
 
-	if (of_machine_is_compatible("globalscale,dreamplug"))
-		dreamplug_init();
-
-	if (of_machine_is_compatible("globalscale,guruplug"))
-		guruplug_dt_init();
-
 	if (of_machine_is_compatible("dlink,dns-kirkwood"))
 		dnskw_init();
 
-	if (of_machine_is_compatible("iom,iconnect"))
-		iconnect_init();
-
-	if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
-		ib62x0_init();
-
 	if (of_machine_is_compatible("qnap,ts219"))
 		qnap_dt_ts219_init();
 
-	if (of_machine_is_compatible("seagate,dockstar"))
-		dockstar_dt_init();
-
-	if (of_machine_is_compatible("seagate,goflexnet"))
-		goflexnet_init();
-
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
-	if (of_machine_is_compatible("iom,ix2-200"))
-		iomega_ix2_200_init();
-
-	if (of_machine_is_compatible("keymile,km_kirkwood"))
-		km_kirkwood_init();
-
-	if (of_machine_is_compatible("lacie,cloudbox") ||
-	    of_machine_is_compatible("lacie,inetspace_v2") ||
-	    of_machine_is_compatible("lacie,netspace_lite_v2") ||
-	    of_machine_is_compatible("lacie,netspace_max_v2") ||
-	    of_machine_is_compatible("lacie,netspace_mini_v2") ||
-	    of_machine_is_compatible("lacie,netspace_v2"))
-		ns2_init();
-
 	if (of_machine_is_compatible("mpl,cec4"))
 		mplcec4_init();
 
 	if (of_machine_is_compatible("netgear,readynas-duo-v2"))
 		netgear_readynas_init();
 
-	if (of_machine_is_compatible("plathome,openblocks-a6"))
-		openblocks_a6_init();
-
-	if (of_machine_is_compatible("usi,topkick"))
-		usi_topkick_init();
-
 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 
 static const char * const kirkwood_dt_board_compat[] = {
-	"globalscale,dreamplug",
-	"globalscale,guruplug",
-	"dlink,dns-320",
-	"dlink,dns-325",
-	"iom,iconnect",
-	"raidsonic,ib-nas62x0",
-	"qnap,ts219",
-	"seagate,dockstar",
-	"seagate,goflexnet",
-	"buffalo,lsxl",
-	"iom,ix2-200",
-	"keymile,km_kirkwood",
-	"lacie,cloudbox",
-	"lacie,inetspace_v2",
-	"lacie,netspace_lite_v2",
-	"lacie,netspace_max_v2",
-	"lacie,netspace_mini_v2",
-	"lacie,netspace_v2",
-	"mpl,cec4",
-	"netgear,readynas-duo-v2",
-	"plathome,openblocks-a6",
-	"usi,topkick",
-	"zyxel,nsa310",
+	"marvell,kirkwood",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
deleted file mode 100644
index 9db979a..0000000
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-goflexnet.c
- *
- * Seagate GoFlext Net Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * Copied and modified for Seagate GoFlex Net support by
- * Joshua Coombs <josh.coombs at gmail.com> based on ArchLinux ARM's
- * GoFlex kernel patches.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init goflexnet_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&goflexnet_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
deleted file mode 100644
index a857163..0000000
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-guruplug.c
- *
- * Marvell Guruplug Reference Board Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data guruplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data guruplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-void __init guruplug_dt_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&guruplug_ge00_data);
-	kirkwood_ge01_init(&guruplug_ge01_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
deleted file mode 100644
index 9a857ae..0000000
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2012 (C), Simon Baatz <gmbnomis at gmail.com>
- *
- * arch/arm/mach-kirkwood/board-ib62x0.c
- *
- * RaidSonic ICY BOX IB-NAS6210 & IB-NAS6220 init for drivers not
- * converted to flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-void __init ib62x0_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&ib62x0_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4..fcaf136 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -11,18 +11,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data iconnect_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
-};
-
-void __init iconnect_init(void)
-{
-	kirkwood_ge00_init(&iconnect_ge00_data);
-}
-
 static int __init iconnect_pci_init(void)
 {
 	if (of_machine_is_compatible("iom,iconnect"))
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
deleted file mode 100644
index e5f7041..0000000
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
- *
- * Iomega StorCenter ix2-200
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
-	.phy_addr       = MV643XX_ETH_PHY_NONE,
-	.speed          = SPEED_1000,
-	.duplex         = DUPLEX_FULL,
-};
-
-static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
-};
-
-void __init iomega_ix2_200_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
-	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
deleted file mode 100644
index 44e4605..0000000
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
- * Valentin Longchamp <valentin.longchamp at keymile.com>
- *
- * arch/arm/mach-kirkwood/board-km_kirkwood.c
- *
- * Keymile km_kirkwood Reference Desing Init for drivers not converted to
- * flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/clk.h>
-#include <linux/clk-private.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init km_kirkwood_init(void)
-{
-	struct clk *sata_clk;
-	/*
-	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
-	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
-	 * devices are also not present in this variant, their clocks get
-	 * disabled because unused when clk_disable_unused() gets called.
-	 * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
-	 */
-	sata_clk = clk_get_sys("sata_mv.0", "0");
-	if (!IS_ERR(sata_clk))
-		sata_clk->flags |= CLK_IGNORE_UNUSED;
-	sata_clk = clk_get_sys("sata_mv.0", "1");
-	if (!IS_ERR(sata_clk))
-		sata_clk->flags |= CLK_IGNORE_UNUSED;
-
-	kirkwood_ge00_init(&km_kirkwood_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7a..3dc0929 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -14,17 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data lsxl_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data lsxl_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 /*
  * On the LS-XHL/LS-CHLv2, the shutdown process is following:
  * - Userland monitors key events until the power switch goes to off position
@@ -40,13 +31,6 @@ static void lsxl_power_off(void)
 
 void __init lsxl_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-
-	kirkwood_ge00_init(&lsxl_ge00_data);
-	kirkwood_ge01_init(&lsxl_ge01_data);
-
 	/* register power-off method */
 	pm_power_off = lsxl_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc66..dd1f655 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -11,24 +11,10 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mv643xx_eth.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(2),
-};
-
 void __init mplcec4_init(void)
 {
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&mplcec4_ge00_data);
-	kirkwood_ge01_init(&mplcec4_ge01_data);
 	kirkwood_pcie_init(KW_PCIE0);
 }
 
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
deleted file mode 100644
index f8f6605..0000000
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2012 (C), Simon Guinot <simon.guinot at sequanux.org>
- *
- * arch/arm/mach-kirkwood/board-ns2.c
- *
- * LaCie Network Space v2 board (and parents) initialization for drivers
- * not converted to flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/of.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data ns2_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-void __init ns2_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	if (of_machine_is_compatible("lacie,cloudbox") ||
-	    of_machine_is_compatible("lacie,netspace_lite_v2") ||
-	    of_machine_is_compatible("lacie,netspace_mini_v2"))
-		ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-	kirkwood_ge00_init(&ns2_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
deleted file mode 100644
index b11d8fd..0000000
--- a/arch/arm/mach-kirkwood/board-openblocks_a6.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
- *
- * arch/arm/mach-kirkwood/board-openblocks_a6.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data openblocks_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init openblocks_a6_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&openblocks_ge00_data);
-}
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20..3ab3e0e 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -13,16 +13,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 
-static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 void __init netgear_readynas_init(void)
 {
-	kirkwood_ge00_init(&netgear_readynas_ge00_data);
 	kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index acb0187..854d448 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -18,27 +18,14 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 #include "tsx1x-common.h"
 
-static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 void __init qnap_dt_ts219_init(void)
 {
-	u32 dev, rev;
-
-	kirkwood_pcie_id(&dev, &rev);
-	if (dev == MV88F6282_DEV_ID)
-		qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-
-	kirkwood_ge00_init(&qnap_ts219_ge00_data);
-
 	pm_power_off = qnap_tsx1x_power_off;
 }
 
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
deleted file mode 100644
index 1cc04ec..0000000
--- a/arch/arm/mach-kirkwood/board-usi_topkick.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-usi_topkick.c
- *
- * USI Topkick Init for drivers not converted to flattened device tree yet.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data topkick_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-void __init usi_topkick_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_ge00_init(&topkick_ge00_data);
-}
-- 
1.7.10.4



From jason at lakedaemon.net  Wed May 29 15:34:32 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 15:34:32 -0400
Subject: Kirkwood CPU Freq driver
In-Reply-To: <20130529005825.GM31290@titan.lakedaemon.net>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
 <20130526180513.GF31290@titan.lakedaemon.net>
 <51A5234D.9030100@baker-net.org.uk>
 <20130529005825.GM31290@titan.lakedaemon.net>
Message-ID: <20130529193432.GY31290@titan.lakedaemon.net>

On Tue, May 28, 2013 at 08:58:25PM -0400, Jason Cooper wrote:
> On Tue, May 28, 2013 at 10:36:13PM +0100, Adam Baker wrote:
> > On 26/05/13 19:05, Jason Cooper wrote:
> > >On Sun, May 26, 2013 at 10:36:14AM +0200, Andrew Lunn wrote:
> > >>On Sat, May 25, 2013 at 10:32:04PM +0100, Adam Baker wrote:
> > >>>I've been trying to test Andrew Lunn's work creating a CPU Idle
> > >>>driver for Kirkwood.
> > >>
> > >>Thanks for testing this. I must admit, i never tested it once the
> > >>first rc came out. I clearly should of, because its broken. It was a
> > >>three part patch series, and only part 1/3 made it in. Hence the
> > >>issues you are seeing.
> > >>
> > >>Jason, please can you pick up:
> > >>
> > >>https://patchwork.kernel.org/patch/2051401/
> > >>https://patchwork.kernel.org/patch/2080931/
> > >
> > >Yep, got them in now.  Sorry for the mix up.
> > >
> > 
> > I've now tested with the first of these patches applied and the
> > changes from the second added to my .config
> > 
> > To get it to work I had to follow the instructions in the
> > Documentation to add the cpus entry to kirkwood.dtsi so I'll post
> > that as a patch in a day or two but after doing that I have a
> > working cpufreq driver.
> > 
> > Measuring the power consumption of my NAS server I observed a slight
> > reduction in power consumption when the clock rate was reduced. I
> > haven't yet measured for long enough to get an accurate measurement
> > but it looks like maybe 1/4 W power saving.
> > 
> > Feel free to add
> > 
> > Tested-by: Adam Baker <linux at baker-net.org.uk>
> 
> I apologize, but I won't be able to add this.  I'm using a new work
> flow, and took the patches in too quickly (well, they had been on the
> list a while... :-P)  I should've let them sit in my tree for a few more
> days before sending the pull request to arm-soc.  If I had done that, I
> could've gone in and added the Tested-by:.  I'll be more careful in the
> future.

I take this back.  Olof didn't pull last night like I thought he would,
and he said I have a few hours until he pulls tonight.  So I've added it
now.  Sorry for the confusion.

thx,

Jason.


From plagnioj at jcrosoft.com  Wed May 29 15:32:20 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 29 May 2013 21:32:20 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
 <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
Message-ID: <20130529193220.GB19468@game.jcrosoft.org>

On 19:44 Wed 29 May     , Richard Genoud wrote:
> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> > On 16:36 Wed 29 May     , Richard Genoud wrote:
> >> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >> > Today we mix pdata and drivers data in the struct atmel_lcdfb_info
> >> > Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
> >> >
> >> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >> > Cc: linux-fbdev at vger.kernel.org
> >> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> >> > Cc: Andrew Morton <akpm at linux-foundation.org>
> >> > Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> >> > ---
> >> >  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
> >> >  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
> >> >  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
> >> >  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
> >> >  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
> >> >  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
> >> >  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
> >> >  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
> >> >  arch/arm/mach-at91/board.h                  |    4 +-
> >> >  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
> >> >  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
> >> >  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
> >> >  arch/avr32/boards/atstk1000/setup.c         |    2 +-
> >> >  arch/avr32/boards/favr-32/setup.c           |    2 +-
> >> >  arch/avr32/boards/hammerhead/setup.c        |    2 +-
> >> >  arch/avr32/boards/merisc/display.c          |    2 +-
> >> >  arch/avr32/boards/mimc200/setup.c           |    4 +-
> >> >  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
> >> >  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
> >> >  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
> >> >  include/video/atmel_lcdc.h                  |   24 +------
> >> >  21 files changed, 109 insertions(+), 101 deletions(-)
> >> >
> >> [snip]
> >> > diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> >> > index c1a2914..98733cd4 100644
> >> > --- a/drivers/video/atmel_lcdfb.c
> >> > +++ b/drivers/video/atmel_lcdfb.c
> >> > @@ -20,12 +20,45 @@
> >> >  #include <linux/gfp.h>
> >> >  #include <linux/module.h>
> >> >  #include <linux/platform_data/atmel.h>
> >> > +#include <video/of_display_timing.h>
> >> >
> >> >  #include <mach/cpu.h>
> >> >  #include <asm/gpio.h>
> >> >
> >> >  #include <video/atmel_lcdc.h>
> >> >
> >> > +struct atmel_lcdfb_config {
> >> > +       bool have_alt_pixclock;
> >> > +       bool have_hozval;
> >> > +       bool have_intensity_bit;
> >> > +};
> >> > +
> >> > + /* LCD Controller info data structure, stored in device platform_data */
> >> > +struct atmel_lcdfb_info {
> >> > +       spinlock_t              lock;
> >> > +       struct fb_info          *info;
> >> > +       void __iomem            *mmio;
> >> > +       int                     irq_base;
> >> > +       struct work_struct      task;
> >> > +
> >> > +       unsigned int            smem_len;
> >> > +       struct platform_device  *pdev;
> >> > +       struct clk              *bus_clk;
> >> > +       struct clk              *lcdc_clk;
> >> > +
> >> > +       struct backlight_device *backlight;
> >> > +       u8                      bl_power;
> >> > +       bool                    lcdcon_pol_negative;
> >> I think lcdcon_pol_negative should be part of pdata, because it really
> >> depends on how the PWM is wired on the board.
> >>
> >
> > maybe but no one mainline use it on any pdata for non-dt boars
> > so I did not want to expose it
> Well, at least, I'm using it :)
> (and I guess that Andreas is using it also, otherwise he wouldn't have
> introduce it !)

yes but pdata is for non-dt boards, for dt you can keep it in struct
atmel_lcdfb_info and add a property

if non-dt boards want it my answer is I do not care switch to DT

Best Regards,
J.
> 
> 
> Best regards,
> Richard.


From jason at lakedaemon.net  Wed May 29 15:36:54 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 15:36:54 -0400
Subject: [GIT PULL v2] ARM: mvebu: soc changes for v3.11 (round 2 cumulative)
In-Reply-To: <20130528183617.GB31290@titan.lakedaemon.net>
References: <20130528183617.GB31290@titan.lakedaemon.net>
Message-ID: <20130529193654.GZ31290@titan.lakedaemon.net>

Olof,

Since I have a few hours, I added a Tested-by that I thought I
missed.  No other changes.


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://git.infradead.org/users/jcooper/linux.git tags/soc-3.11-2

for you to fetch changes up to 0e2ee0c0610ec211a9f0ebf3088cbf4da422ebf8:

  arm: kirkwood: Instantiate cpufreq driver (2013-05-29 19:32:04 +0000)

----------------------------------------------------------------
mvebu soc changes for v3.11 (round 2)

 - kirkwood
    - use the cpufreq driver

----------------------------------------------------------------
Andrew Lunn (1):
      arm: kirkwood: Instantiate cpufreq driver

Thomas Petazzoni (1):
      arm: kirkwood: use the default of match table

 arch/arm/Kconfig                                  |  1 +
 arch/arm/mach-kirkwood/board-dt.c                 |  9 +++------
 arch/arm/mach-kirkwood/common.c                   | 23 +++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h                   |  2 ++
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |  2 ++
 5 files changed, 31 insertions(+), 6 deletions(-)


From fabio.estevam at freescale.com  Wed May 29 15:44:22 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Wed, 29 May 2013 16:44:22 -0300
Subject: [PATCH 1/2] ARM: mxs: Print silicon version on boot
Message-ID: <1369856663-29314-1-git-send-email-fabio.estevam@freescale.com>

Introduce functions that identify the SoC type (i.MX23 or iMX28)
and also report the silicon revision.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 85 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 66fe810..b632323 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -38,6 +38,21 @@
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0		0x2
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1		0x3
 
+
+#define MXS_DIGCTL_BASE_ADDR	0x8001c000
+#define HW_DIGCTL_CHIPID	0x310
+#define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
+#define HW_DIGCTL_REV_MASK	0xff
+#define HW_DIGCTL_CHIPID_MX23	(0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
+
+#define IMX_CHIP_REVISION_1_0	0x10
+#define IMX_CHIP_REVISION_1_1	0x11
+#define IMX_CHIP_REVISION_1_2	0x12
+#define IMX_CHIP_REVISION_1_3	0x13
+#define IMX_CHIP_REVISION_1_4	0x14
+#define IMX_CHIP_REV_UNKNOWN	0xff
+
 #define MXS_GPIO_NR(bank, nr)	((bank) * 32 + (nr))
 
 #define MXS_SET_ADDR		0x4
@@ -361,8 +376,78 @@ static void __init cfa10037_init(void)
 	update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
 
+static const char *mxs_get_cpu_type(void)
+{
+	int reg;
+	void __iomem *digctl_base = ioremap(MXS_DIGCTL_BASE_ADDR, SZ_8K);
+
+	if (!digctl_base)
+		return "unknown";
+
+	reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK;
+	switch (reg) {
+	case HW_DIGCTL_CHIPID_MX23:
+		return "23";
+	case HW_DIGCTL_CHIPID_MX28:
+		return "28";
+	default:
+		return "unknown";
+	}
+}
+
+static int mxs_get_cpu_rev(void)
+{
+	int reg, rev;
+	void __iomem *digctl_base = ioremap(MXS_DIGCTL_BASE_ADDR, SZ_8K);
+
+	if (!digctl_base)
+		return -ENOMEM;
+
+	reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK;
+	rev = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_REV_MASK;
+
+	switch (reg) {
+	case HW_DIGCTL_CHIPID_MX23:
+		switch (rev) {
+		case 0x0:
+			return IMX_CHIP_REVISION_1_0;
+		case 0x1:
+			return IMX_CHIP_REVISION_1_1;
+		case 0x2:
+			return IMX_CHIP_REVISION_1_2;
+		case 0x3:
+			return IMX_CHIP_REVISION_1_3;
+		case 0x4:
+			return IMX_CHIP_REVISION_1_4;
+		default:
+			return IMX_CHIP_REV_UNKNOWN;
+		}
+	case HW_DIGCTL_CHIPID_MX28:
+		switch (rev) {
+		case 0x1:
+			return IMX_CHIP_REVISION_1_2;
+		default:
+			return IMX_CHIP_REV_UNKNOWN;
+		}
+	default:
+		return IMX_CHIP_REV_UNKNOWN;
+	}
+}
+
+static void mxs_print_silicon_rev(const char *cpu, int srev)
+{
+	if (srev == IMX_CHIP_REV_UNKNOWN)
+		pr_info("CPU identified as i.MX%s, unknown revision\n", cpu);
+	else
+		pr_info("CPU identified as i.MX%s, silicon rev %d.%d\n",
+				cpu, (srev >> 4) & 0xf, srev & 0xf);
+}
+
 static void __init mxs_machine_init(void)
 {
+
+	mxs_print_silicon_rev(mxs_get_cpu_type(), mxs_get_cpu_rev());
+
 	if (of_machine_is_compatible("fsl,imx28-evk"))
 		imx28_evk_init();
 	else if (of_machine_is_compatible("bluegiga,apx4devkit"))
-- 
1.8.1.2




From fabio.estevam at freescale.com  Wed May 29 15:44:23 2013
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Wed, 29 May 2013 16:44:23 -0300
Subject: [PATCH 2/2] ARM: mxs: Pass the system revision
In-Reply-To: <1369856663-29314-1-git-send-email-fabio.estevam@freescale.com>
References: <1369856663-29314-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <1369856663-29314-2-git-send-email-fabio.estevam@freescale.com>

Some mxs userspace tools, such as multimedia plugins and kobs-ng (tool used to 
burn boot images to NAND) rely on the 'Revision' field reported by 
'/proc/cpuinfo'.

Provide a mechanism to pass such information, so that now we can get:

$ cat /proc/cpuinfo                                             
processor       : 0                                                             
model name      : ARM926EJ-S rev 5 (v5l)                                        
BogoMIPS        : 226.09                                                        
Features        : swp half fastmult edsp java                                   
CPU implementer : 0x41                                                          
CPU architecture: 5TEJ                                                          
CPU variant     : 0x0                                                           
CPU part        : 0x926                                                         
CPU revision    : 5                                                             
                                                                                
Hardware        : Freescale i.MX28 Evaluation Kit                               
Revision        : 28012                                                         
Serial          : 0000000000000000                                              

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-mxs/mach-mxs.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index b632323..032812d 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -29,6 +29,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
+#include <asm/system_info.h>
 
 #include "pm.h"
 
@@ -443,10 +444,24 @@ static void mxs_print_silicon_rev(const char *cpu, int srev)
 				cpu, (srev >> 4) & 0xf, srev & 0xf);
 }
 
+static void mxs_pass_sysrev(void)
+{
+	int cputype = 0;
+
+	if (strcmp(mxs_get_cpu_type(), "MX23"))
+		cputype = 0x23000;
+
+	if (strcmp(mxs_get_cpu_type(), "MX28"))
+		cputype = 0x28000;
+
+	system_rev = (cputype | mxs_get_cpu_rev());
+}
+
 static void __init mxs_machine_init(void)
 {
 
 	mxs_print_silicon_rev(mxs_get_cpu_type(), mxs_get_cpu_rev());
+	mxs_pass_sysrev();
 
 	if (of_machine_is_compatible("fsl,imx28-evk"))
 		imx28_evk_init();
-- 
1.8.1.2




From jason at lakedaemon.net  Wed May 29 16:00:53 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 16:00:53 -0400
Subject: [PATCH v5 01/13] net: mv643xx_eth: use phy_disconnect instead
 of phy_detach
In-Reply-To: <1369855975-21489-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130529200053.GA31290@titan.lakedaemon.net>

Sebastian,

On Wed, May 29, 2013 at 09:32:43PM +0200, Sebastian Hesselbarth wrote:
> Using a separated mdio bus driver with mvmdio, phy_detach on network device
> removal will not stop the phy and finally lead to NULL pointer dereference
> in mvmdio due to non-existent network device. Use phy_disconnect instead
> to properly stop phy device from accessing network device prior removal of
> the network device.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Note: I observed this behavior when removing a modular mv643xx_eth driver
> after attaching it to a phy handled by (also modular) mvmdio. The mvmdio
> conversion has been done in
> 
> commit c3a07134e6aa5b93a37f72ffa3d11fadf72bf757
>  ("mv643xx_eth: convert to use the Marvell Orion MDIO driver")
> 
> and should go back any -stable version with that commit (propably only 3.9)

It looks like just v3.10-rcX, here.

thx,

Jason.


From jgchunter at gmail.com  Wed May 29 16:17:38 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Wed, 29 May 2013 21:17:38 +0100
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <51A52A16.1040204@wwwdotorg.org>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
Message-ID: <51A66262.7000305@gmail.com>


On 28/05/13 23:05, Stephen Warren wrote:
> On 05/28/2013 03:25 PM, Jon Hunter wrote:
>>
>> On 27/05/13 15:37, Afzal Mohammed wrote:
>>> AM43x timer bindings.
>>>
>>> Signed-off-by: Afzal Mohammed <afzal at ti.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/omap/timer.txt | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
>>> index d02e27c..70cb398 100644
>>> --- a/Documentation/devicetree/bindings/arm/omap/timer.txt
>>> +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
>>> @@ -14,6 +14,8 @@ Required properties:
>>>  			ti,omap5430-timer (applicable to OMAP543x devices)
>>>  			ti,am335x-timer	(applicable to AM335x devices)
>>>  			ti,am335x-timer-1ms (applicable to AM335x devices)
>>> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
>>> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
>>>  
>>>  - reg:			Contains timer register address range (base address and
>>>  			length).
>>
>> If you are adding more compatibility strings, then this implies that the
>> AM43x timers are not 100% compatible with any other device listed (such
>> as am335x or any omap device). That's fine but you should state that in
>> the changelog. If the AM43x timer registers are 100% compatible with
>> existing devices you should not add these.
> 
> I'm not sure that's true; .dts files should always include a compatible
> value that describes the most specific model of the HW, plus any
> baseline compatible value that the HW is compatible with. This allows
> any required quirks/fixes/... to be applied for the specific HW model
> later even if nobody knows right now they'll be needed. Hence, defining
> new compatible values doesn't necessarily mean incompatible HW.

Yes that does seem to agree with what Grant had told me in the past [1].
So this is ok then. However, I still think that the changelog needs to
be vastly improved and more explicit about the changes.

Cheers
Jon

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/90551/focus=26447



From nicolas.pitre at linaro.org  Wed May 29 16:21:49 2013
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 29 May 2013 16:21:49 -0400 (EDT)
Subject: [GIT PULL] MCPM support for VExpress RTSM
Message-ID: <alpine.LFD.2.03.1305291604300.30828@syhkavp.arg>

ARnd, Olof, please pull the following:

	git://git.linaro.org/people/nico/linux VExpress_DCSCB

This is the first MCPM backend submission for VExpress running on RTSM 
aka Fast Models implementing the big.LITTLE system architecture.  This 
enables SMP secondary boot as well as CPU hotplug on this platform.

A big prerequisite for this support is the CCI driver from Lorenzo 
included in this pull request.

Also included is Rob Herring's set_auxcr/get_auxcr allowing nicer code.

This is based on RMK's current devel-stable branch as this code also 
relies on commit b382b940f821 to work properly.

The diffstat follows:

 Documentation/devicetree/bindings/arm/cci.txt   | 172 ++++++
 .../devicetree/bindings/arm/rtsm-dcscb.txt      |  19 +
 arch/arm/include/asm/cp15.h                     |  14 +
 arch/arm/mach-vexpress/Kconfig                  |   9 +
 arch/arm/mach-vexpress/Makefile                 |   1 +
 arch/arm/mach-vexpress/core.h                   |   2 +
 arch/arm/mach-vexpress/dcscb.c                  | 253 +++++++++
 arch/arm/mach-vexpress/dcscb_setup.S            |  38 ++
 arch/arm/mach-vexpress/platsmp.c                |  20 +
 arch/arm/mach-vexpress/v2m.c                    |   1 +
 drivers/bus/Kconfig                             |   7 +
 drivers/bus/Makefile                            |   2 +
 drivers/bus/arm-cci.c                           | 533 ++++++++++++++++++
 drivers/cpuidle/cpuidle-calxeda.c               |  14 -
 include/linux/arm-cci.h                         |  61 ++
 15 files changed, 1132 insertions(+), 14 deletions(-)


Nicolas


From akpm at linux-foundation.org  Wed May 29 16:33:54 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Wed, 29 May 2013 13:33:54 -0700
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>

On Thu, 23 May 2013 10:38:50 +0200 Johan Hovold <jhovold at gmail.com> wrote:

> This is an update of the shadow-interrupt-mask series against v3.10-rc2.
> 
> I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
> affected. If not, then some probing mechanism as the one Doug suggested
> could be implemented on top of (a subset of) these patches. What do you
> say, Nicolas?
> 
> Note that the first patch (adding a missing OF compile guard) could be
> applied straight away.

At this stage it is unclear to me how to proceed with patches 2-5.


From robertcnelson at gmail.com  Wed May 29 16:41:02 2013
From: robertcnelson at gmail.com (Robert Nelson)
Date: Wed, 29 May 2013 15:41:02 -0500
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
Message-ID: <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>

On Wed, May 29, 2013 at 3:33 PM, Andrew Morton
<akpm at linux-foundation.org> wrote:
> On Thu, 23 May 2013 10:38:50 +0200 Johan Hovold <jhovold at gmail.com> wrote:
>
>> This is an update of the shadow-interrupt-mask series against v3.10-rc2.
>>
>> I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
>> affected. If not, then some probing mechanism as the one Doug suggested
>> could be implemented on top of (a subset of) these patches. What do you
>> say, Nicolas?
>>
>> Note that the first patch (adding a missing OF compile guard) could be
>> applied straight away.
>
> At this stage it is unclear to me how to proceed with patches 2-5.

fyi:

A version of these patches had been applied once before:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0ef1594c017521ea89278e80fe3f80dafb17abde

But due to a few issues it was later reverted:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=e24b0bfa2f0446ffaad2661040be23668133aef8

Regards,

-- 
Robert Nelson
http://www.rcn-ee.com/


From csd at broadcom.com  Wed May 29 16:50:05 2013
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 29 May 2013 13:50:05 -0700
Subject: [PATCH V4 1/3] mmc: sdhci: Add size for caller in init+register
Message-ID: <1369860607-25572-1-git-send-email-csd@broadcom.com>

Add a param to allow users of sdhci_pltfm to allocate private space
in calls to sdhci_pltfm_init+sdhci_pltfm_register. This is implemented
in the same way as sdhci does for its users.
 None of the users have been migrated yet and are passing in zero to
retain their private allocation.

- todo: migrate clients to using allocation this way
- todo: remove priv variable once migration is complete

Also removed unused variable in sdhci_pltfm_init fn

Signed-off-by: Christian Daudt <csd at broadcom.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Ulf Hansson <ulf.hansson at linaro.org>

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index d49bc95..0584a1c 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -148,7 +148,7 @@ static int bcm2835_sdhci_probe(struct platform_device *pdev)
 	struct sdhci_pltfm_host *pltfm_host;
 	int ret;
 
-	host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata);
+	host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata, 0);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 
diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c
index 8ebb6b6..f2cc266 100644
--- a/drivers/mmc/host/sdhci-cns3xxx.c
+++ b/drivers/mmc/host/sdhci-cns3xxx.c
@@ -96,7 +96,7 @@ static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
 
 static int sdhci_cns3xxx_probe(struct platform_device *pdev)
 {
-	return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata);
+	return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
 }
 
 static int sdhci_cns3xxx_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c
index 15e7803..8424839 100644
--- a/drivers/mmc/host/sdhci-dove.c
+++ b/drivers/mmc/host/sdhci-dove.c
@@ -130,7 +130,7 @@ static int sdhci_dove_probe(struct platform_device *pdev)
 		gpio_direction_input(priv->gpio_cd);
 	}
 
-	host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata);
+	host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata, 0);
 	if (IS_ERR(host)) {
 		ret = PTR_ERR(host);
 		goto err_sdhci_pltfm_init;
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 67d6dde..9a1e6fa 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -470,7 +470,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 	int err;
 	struct pltfm_imx_data *imx_data;
 
-	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
+	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 5e68adc..37e668f 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -262,7 +262,7 @@ static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
 
 static int sdhci_esdhc_probe(struct platform_device *pdev)
 {
-	return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
+	return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata, 0);
 }
 
 static int sdhci_esdhc_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/sdhci-of-hlwd.c b/drivers/mmc/host/sdhci-of-hlwd.c
index 200a6a9..57c514a 100644
--- a/drivers/mmc/host/sdhci-of-hlwd.c
+++ b/drivers/mmc/host/sdhci-of-hlwd.c
@@ -68,7 +68,7 @@ static const struct sdhci_pltfm_data sdhci_hlwd_pdata = {
 
 static int sdhci_hlwd_probe(struct platform_device *pdev)
 {
-	return sdhci_pltfm_register(pdev, &sdhci_hlwd_pdata);
+	return sdhci_pltfm_register(pdev, &sdhci_hlwd_pdata, 0);
 }
 
 static int sdhci_hlwd_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index cd0f1f6..38e38a5 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -115,10 +115,10 @@ void sdhci_get_of_property(struct platform_device *pdev) {}
 EXPORT_SYMBOL_GPL(sdhci_get_of_property);
 
 struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
-				    const struct sdhci_pltfm_data *pdata)
+				    const struct sdhci_pltfm_data *pdata,
+				    size_t priv_size)
 {
 	struct sdhci_host *host;
-	struct sdhci_pltfm_host *pltfm_host;
 	struct device_node *np = pdev->dev.of_node;
 	struct resource *iomem;
 	int ret;
@@ -134,17 +134,17 @@ struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
 
 	/* Some PCI-based MFD need the parent here */
 	if (pdev->dev.parent != &platform_bus && !np)
-		host = sdhci_alloc_host(pdev->dev.parent, sizeof(*pltfm_host));
+		host = sdhci_alloc_host(pdev->dev.parent,
+			sizeof(struct sdhci_pltfm_host) + priv_size);
 	else
-		host = sdhci_alloc_host(&pdev->dev, sizeof(*pltfm_host));
+		host = sdhci_alloc_host(&pdev->dev,
+			sizeof(struct sdhci_pltfm_host) + priv_size);
 
 	if (IS_ERR(host)) {
 		ret = PTR_ERR(host);
 		goto err;
 	}
 
-	pltfm_host = sdhci_priv(host);
-
 	host->hw_name = dev_name(&pdev->dev);
 	if (pdata && pdata->ops)
 		host->ops = pdata->ops;
@@ -202,12 +202,13 @@ void sdhci_pltfm_free(struct platform_device *pdev)
 EXPORT_SYMBOL_GPL(sdhci_pltfm_free);
 
 int sdhci_pltfm_register(struct platform_device *pdev,
-			 const struct sdhci_pltfm_data *pdata)
+			const struct sdhci_pltfm_data *pdata,
+			size_t priv_size)
 {
 	struct sdhci_host *host;
 	int ret = 0;
 
-	host = sdhci_pltfm_init(pdev, pdata);
+	host = sdhci_pltfm_init(pdev, pdata, priv_size);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index 1210ed1..ed4a85d 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -27,6 +27,8 @@ struct sdhci_pltfm_host {
 	/* migrate from sdhci_of_host */
 	unsigned int clock;
 	u16 xfer_mode_shadow;
+
+	unsigned long private[0] ____cacheline_aligned;
 };
 
 #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
@@ -91,15 +93,22 @@ static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
 extern void sdhci_get_of_property(struct platform_device *pdev);
 
 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
-					  const struct sdhci_pltfm_data *pdata);
+					  const struct sdhci_pltfm_data *pdata,
+					  size_t priv_size);
 extern void sdhci_pltfm_free(struct platform_device *pdev);
 
 extern int sdhci_pltfm_register(struct platform_device *pdev,
-				const struct sdhci_pltfm_data *pdata);
+				const struct sdhci_pltfm_data *pdata,
+				size_t priv_size);
 extern int sdhci_pltfm_unregister(struct platform_device *pdev);
 
 extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
 
+static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
+{
+	return (void *)host->private;
+}
+
 #ifdef CONFIG_PM
 extern const struct dev_pm_ops sdhci_pltfm_pmops;
 #define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops)
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
index 6a3f702..1cf093f 100644
--- a/drivers/mmc/host/sdhci-pxav2.c
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -175,7 +175,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
 	if (!pxa)
 		return -ENOMEM;
 
-	host = sdhci_pltfm_init(pdev, NULL);
+	host = sdhci_pltfm_init(pdev, NULL, 0);
 	if (IS_ERR(host)) {
 		kfree(pxa);
 		return PTR_ERR(host);
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 1ae358e..9124104 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -230,7 +230,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 	if (!pxa)
 		return -ENOMEM;
 
-	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata);
+	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
 	if (IS_ERR(host)) {
 		kfree(pxa);
 		return PTR_ERR(host);
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index e0dba74..c8b0582 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -231,7 +231,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 		return -EINVAL;
 	soc_data = match->data;
 
-	host = sdhci_pltfm_init(pdev, soc_data->pdata);
+	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
 	if (IS_ERR(host))
 		return PTR_ERR(host);
 	pltfm_host = sdhci_priv(host);
-- 
1.7.10.4




From csd at broadcom.com  Wed May 29 16:50:06 2013
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 29 May 2013 13:50:06 -0700
Subject: [PATCH V4 2/3] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1369860607-25572-1-git-send-email-csd@broadcom.com>
References: <1369860607-25572-1-git-send-email-csd@broadcom.com>
Message-ID: <1369860607-25572-2-git-send-email-csd@broadcom.com>

Add SDHCI driver for the Broadcom 281xx SoCs. Also
add bindings for it into bcm281xx dts files.
Still missing:
 - power managemement

Changes from V3:
 - switch mdelay to usleep_range

Changes from V2:
 - Structure cleanups
 - init space from sdhci_pltfm_init
 - replace spinlock_irqsave with mutex on sd_card_emulate
 - Reduce init_74_clocks delay and document it

Changes from V1:
 - split DT into separate patch
 - use gpio_is_valid instead of direct test
 - switch pr_debug calls to dev_dbg
 - use of_property_read_bool

Signed-off-by: Christian Daudt <csd at broadcom.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index e3bf2d6..65edf6d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9ab8f8d..2455a35 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -249,6 +249,17 @@ config MMC_SDHCI_S3C_DMA
 
 	  YMMV.
 
+config MMC_SDHCI_BCM_KONA
+	tristate "SDHCI support on Broadcom KONA platform"
+	depends on ARCH_BCM
+	select MMC_SDHCI_PLTFM
+	help
+	  This selects the Broadcom Kona Secure Digital Host Controller
+	  Interface(SDHCI) support.
+	  This is used in Broadcom mobile SoCs.
+
+	  If you have a controller with this interface, say Y or M here.
+
 config MMC_SDHCI_BCM2835
 	tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
 	depends on ARCH_BCM2835
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cd32280..cd4c845 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)		+= sdhci-dove.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
+obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
new file mode 100644
index 0000000..78517d1
--- /dev/null
+++ b/drivers/mmc/host/sdhci-bcm-kona.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/highmem.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/version.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci.h"
+
+#define SDHCI_SOFT_RESET			0x01000000
+#define KONA_SDHOST_CORECTRL			0x8000
+#define KONA_SDHOST_CD_PINCTRL			0x00000008
+#define KONA_SDHOST_STOP_HCLK			0x00000004
+#define KONA_SDHOST_RESET			0x00000002
+#define KONA_SDHOST_EN				0x00000001
+
+#define KONA_SDHOST_CORESTAT			0x8004
+#define KONA_SDHOST_WP				0x00000002
+#define KONA_SDHOST_CD_SW			0x00000001
+
+#define KONA_SDHOST_COREIMR			0x8008
+#define KONA_SDHOST_IP				0x00000001
+
+#define KONA_SDHOST_COREISR			0x800C
+#define KONA_SDHOST_COREIMSR			0x8010
+#define KONA_SDHOST_COREDBG1			0x8014
+#define KONA_SDHOST_COREGPO_MASK		0x8018
+
+#define SD_DETECT_GPIO_DEBOUNCE_128MS		128
+
+#define KONA_MMC_AUTOSUSPEND_DELAY		(50)
+
+struct sdhci_bcm_kona_dev {
+	struct clk	*peri_clk;
+	struct clk	*sleep_clk;
+
+	struct mutex	write_lock; /* protect back to back writes */
+	unsigned int	max_freq;
+	int		is_8bit;
+	int		irq;
+	int		cd_gpio;
+	int		wp_gpio;
+	int		non_removable;
+};
+
+
+static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
+{
+	unsigned int val;
+	unsigned long timeout;
+
+	/* This timeout should be sufficent for core to reset */
+	timeout = jiffies + msecs_to_jiffies(100);
+
+	/* reset the host using the top level reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_RESET;
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
+		if (time_is_before_jiffies(timeout)) {
+			pr_err("Error: sd host is stuck in reset!!!\n");
+			return -EFAULT;
+		}
+	}
+
+	/* bring the host out of reset */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val &= ~KONA_SDHOST_RESET;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	usleep_range(1000, 5000);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+
+	return 0;
+}
+
+static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
+{
+	unsigned int val;
+
+	/* enable the interrupt from the IP core */
+	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
+	val |= KONA_SDHOST_IP;
+	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
+
+	/* Enable the AHB clock gating module to the host */
+	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
+	val |= KONA_SDHOST_EN;
+
+	/*
+	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 */
+	usleep_range(1000, 5000);
+	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
+}
+
+/*
+ * Software emulation of the SD card insertion/removal. Set insert=1 for insert
+ * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
+ * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
+ * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
+ */
+static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
+{
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
+	u32 val;
+	unsigned long flags;
+
+	/*
+	 * Back-to-Back register write needs a delay of min 10uS.
+	 * Back-to-Back writes to same register needs delay when SD bus clock
+	 * is very low w.r.t AHB clock, mainly during boot-time and during card
+	 * insert-removal.
+	 * We keep 20uS
+	 */
+	mutex_lock(&kona_dev->write_lock);
+	udelay(20);
+	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
+
+	if (insert) {
+		if (gpio_is_valid(kona_dev->wp_gpio)) {
+			int wp_status = gpio_get_value(kona_dev->wp_gpio);
+
+			if (wp_status)
+				val |= KONA_SDHOST_WP;
+			else
+				val &= ~KONA_SDHOST_WP;
+		}
+
+		val |= KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	} else {
+		val &= ~KONA_SDHOST_CD_SW;
+		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
+	}
+	mutex_unlock(&kona_dev->write_lock);
+
+	return 0;
+}
+
+/*
+ * SD card detection interrupt handler
+ */
+static irqreturn_t sdhci_bcm_kona_pltfm_cd_interrupt(int irq, void *h)
+{
+	struct sdhci_host *host = h;
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
+
+	if (gpio_get_value_cansleep(kona_dev->cd_gpio) == 0) {
+		dev_dbg(mmc_dev(host->mmc),
+			"card inserted\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 1);
+	} else {
+		dev_dbg(mmc_dev(host->mmc),
+			"card removed\n");
+		sdhci_bcm_kona_sd_card_emulate(host, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Get the base clock. Use central clock source for now. Not sure if different
+ * clock speed to each dev is allowed
+ */
+static unsigned int sdhci_bcm_kona_get_max_clk(struct sdhci_host *host)
+{
+	struct sdhci_bcm_kona_dev *kona_dev;
+	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
+	kona_dev = sdhci_pltfm_priv(pltfm_priv);
+
+	return kona_dev->max_freq;
+}
+
+static unsigned int sdhci_bcm_kona_get_timeout_clock(struct sdhci_host *host)
+{
+	return sdhci_bcm_kona_get_max_clk(host);
+}
+
+static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
+				u8 power_mode)
+{
+	/*
+	 *  JEDEC and SD spec specify supplying 74 continuous clocks to
+	 * device after power up. With minimum bus (100KHz) that
+	 * that translates to 740us
+	 */
+	if (power_mode != MMC_POWER_OFF)
+		udelay(740);
+}
+
+static struct sdhci_ops sdhci_bcm_kona_ops = {
+	.get_max_clock = sdhci_bcm_kona_get_max_clk,
+	.get_timeout_clock = sdhci_bcm_kona_get_timeout_clock,
+	.platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
+};
+
+static struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
+	.ops    = &sdhci_bcm_kona_ops,
+	.quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
+		SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
+		SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
+		SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+static const struct of_device_id sdhci_bcm_kona_of_match[] __initdata = {
+	{ .compatible = "bcm,kona-sdhci"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
+
+static int __init sdhci_bcm_kona_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sdhci_bcm_kona_dev *kona_dev = NULL;
+	struct sdhci_pltfm_host *pltfm_priv;
+	struct device *dev = &pdev->dev;
+	struct sdhci_host *host;
+	int ret;
+	unsigned int irq;
+	u32 temp;
+
+	ret = 0;
+
+	host = sdhci_pltfm_init(pdev, &sdhci_pltfm_data_kona,
+			sizeof(*kona_dev));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
+
+	pltfm_priv = sdhci_priv(host);
+
+	kona_dev = sdhci_pltfm_priv(pltfm_priv);
+	mutex_init(&kona_dev->write_lock);
+
+	kona_dev->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
+	kona_dev->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
+	if (of_property_read_bool(np, "non-removable"))
+		kona_dev->non_removable = 1;
+
+	if (of_property_read_u32(np, "bus-width", &temp) == 0 && temp == 8)
+		kona_dev->is_8bit = 1;
+
+	if (of_property_read_u32(np, "max-frequency", &kona_dev->max_freq)) {
+		dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
+		ret = -ENXIO;
+		goto err_pltfm_free;
+	}
+
+	dev_dbg(dev, "non-removable=%c\n",
+		(kona_dev->non_removable) ? 'Y' : 'N');
+	dev_dbg(dev, "cd_gpio %d, wp_gpio %d\n", kona_dev->cd_gpio,
+		kona_dev->wp_gpio);
+
+	if (kona_dev->non_removable) {
+		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+	}
+
+	dev_dbg(dev, "is_8bit=%c\n", (kona_dev->is_8bit) ? 'Y' : 'N');
+	if (kona_dev->is_8bit)
+		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+	ret = sdhci_bcm_kona_sd_reset(host);
+	if (ret)
+		goto err_pltfm_free;
+
+	sdhci_bcm_kona_sd_init(host);
+
+	ret = sdhci_add_host(host);
+	if (ret) {
+		dev_err(dev, "Failed sdhci_add_host\n");
+		goto err_reset;
+	}
+
+	/* if device is eMMC, emulate card insert right here */
+	if (kona_dev->non_removable) {
+		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
+		if (ret) {
+			dev_err(dev,
+				"unable to emulate card insertion\n");
+			goto err_remove_host;
+		}
+	} else if (gpio_is_valid(kona_dev->cd_gpio)) {
+		ret = devm_gpio_request(dev, kona_dev->cd_gpio, "sdio cd");
+		if (ret < 0) {
+			dev_err(mmc_dev(host->mmc),
+				"Unable to request GPIO pin %d\n",
+				kona_dev->cd_gpio);
+			goto err_remove_host;
+		}
+
+		gpio_direction_input(kona_dev->cd_gpio);
+
+		/* Set debounce for SD Card detect to maximum value (128ms)
+		 *
+		 * NOTE-1: If gpio_set_debounce() returns error we still
+		 * continue with the default debounce value set. Another reason
+		 * for doing this is that on rhea-ray boards the SD Detect GPIO
+		 * is on GPIO Expander and gpio_set_debounce() will return error
+		 * and if we return error from here, then probe() would fail and
+		 * SD detection would always fail.
+		 *
+		 * NOTE-2: We also give a msleep() of the "debounce" time here
+		 * so that we give enough time for the debounce to stabilize
+		 * before we read the gpio value in gpio_get_value_cansleep().
+		 */
+		ret = gpio_set_debounce(kona_dev->cd_gpio,
+				(SD_DETECT_GPIO_DEBOUNCE_128MS * 1000));
+		if (ret < 0) {
+			dev_err(mmc_dev(host->mmc),
+				"%s: gpio set debounce failed."
+				"default debounce value assumed\n", __func__);
+		}
+
+		/* Sleep for 128ms to allow debounce to stabilize */
+		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
+		/* request irq for cd_gpio after the gpio debounce is
+		 * stabilized, otherwise, some bogus gpio interrupts might be
+		 * triggered.
+		 */
+		irq = gpio_to_irq(kona_dev->cd_gpio);
+		ret = devm_request_threaded_irq(dev,
+				irq,
+				NULL,
+				sdhci_bcm_kona_pltfm_cd_interrupt,
+				IRQF_TRIGGER_FALLING|
+				IRQF_TRIGGER_RISING |
+				IRQF_ONESHOT |
+				IRQF_NO_SUSPEND, "sdio cd", host);
+		if (ret) {
+			dev_err(mmc_dev(host->mmc),
+				"Failed irq %d request for gpio=%d ret=%d\n",
+				gpio_to_irq(kona_dev->cd_gpio),
+				kona_dev->cd_gpio, ret);
+			goto err_remove_host;
+		}
+		if (gpio_is_valid(kona_dev->wp_gpio)) {
+			ret = devm_gpio_request(dev,
+				kona_dev->wp_gpio, "sdio wp");
+			if (ret < 0) {
+				dev_err(&pdev->dev,
+					"Unable to request WP pin %d\n",
+					kona_dev->wp_gpio);
+				kona_dev->wp_gpio = -1;
+			} else {
+				gpio_direction_input(kona_dev->wp_gpio);
+			}
+		}
+
+		/*
+		 * Since the card detection GPIO interrupt is configured to be
+		 * edge sensitive, check the initial GPIO value here, emulate
+		 * only if the card is present
+		 */
+		if (gpio_get_value_cansleep(kona_dev->cd_gpio) == 0)
+			sdhci_bcm_kona_sd_card_emulate(host, 1);
+	}
+
+	dev_dbg(dev, "initialized properly\n");
+	return 0;
+
+err_remove_host:
+	sdhci_remove_host(host, 0);
+
+err_reset:
+	sdhci_bcm_kona_sd_reset(host);
+
+err_pltfm_free:
+	sdhci_pltfm_free(pdev);
+
+	dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
+	return ret;
+}
+
+static int __exit sdhci_bcm_kona_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	int dead;
+	u32 scratch;
+
+	dead = 0;
+	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
+	if (scratch == (u32)-1)
+		dead = 1;
+	sdhci_remove_host(host, dead);
+
+	sdhci_free_host(host);
+
+	return 0;
+}
+
+static struct platform_driver sdhci_bcm_kona_driver = {
+	.driver		= {
+		.name	= "sdhci-kona",
+		.owner	= THIS_MODULE,
+		.pm	= SDHCI_PLTFM_PMOPS,
+		.of_match_table = of_match_ptr(sdhci_bcm_kona_of_match),
+	},
+	.probe		= sdhci_bcm_kona_probe,
+	.remove		= __exit_p(sdhci_bcm_kona_remove),
+};
+module_platform_driver(sdhci_bcm_kona_driver);
+
+MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
+MODULE_AUTHOR("Broadcom");
+MODULE_LICENSE("GPL v2");
+
-- 
1.7.10.4




From csd at broadcom.com  Wed May 29 16:50:07 2013
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 29 May 2013 13:50:07 -0700
Subject: [PATCH V4 3/3] ARM: mmc: bcm281xx SDHCI driver (dt mods)
In-Reply-To: <1369860607-25572-1-git-send-email-csd@broadcom.com>
References: <1369860607-25572-1-git-send-email-csd@broadcom.com>
Message-ID: <1369860607-25572-3-git-send-email-csd@broadcom.com>

Add SDHCI bindings for the Broadcom 281xx SoCs.

Changes from V2:
 - Documentation cleanups

Changes from V1:
 - split original patch into 2, one for driver and this one for dt

Signed-off-by: Christian Daudt <csd at broadcom.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
new file mode 100644
index 0000000..094ae01
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
@@ -0,0 +1,16 @@
+Broadcom BCM281xx SDHCI
+
+This file documents differences between the core properties in mmc.txt
+and the properties present in the bcm281xx SDHCI
+
+Required properties:
+- compatible : Should be "bcm,kona-sdhci"
+
+Example:
+
+sdio2: sdio at 0x3f1a0000 {
+	compatible = "bcm,kona-sdhci";
+	reg = <0x3f1a0000 0x10000>;
+	interrupts = <0x0 74 0x4>;
+};
+
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067c..9ae3404 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -27,4 +27,21 @@
 		status = "okay";
 	};
 
+	sdio0: sdio at 0x3f180000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		non-removable;
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		max-frequency = <48000000>;
+		status = "okay";
+	};
+
+
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c..39de6e2 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -60,4 +60,32 @@
 		clock-frequency = <32768>;
 	};
 
+	sdio0: sdio at 0x3f180000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f180000 0x10000>;
+		interrupts = <0x0 77 0x4>;
+		status = "disabled";
+	};
+
+	sdio1: sdio at 0x3f190000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f190000 0x10000>;
+		interrupts = <0x0 76 0x4>;
+		status = "disabled";
+	};
+
+	sdio2: sdio at 0x3f1a0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1a0000 0x10000>;
+		interrupts = <0x0 74 0x4>;
+		status = "disabled";
+	};
+
+	sdio3: sdio at 0x3f1b0000 {
+		compatible = "bcm,kona-sdhci";
+		reg = <0x3f1b0000 0x10000>;
+		interrupts = <0x0 73 0x4>;
+		status = "disabled";
+	};
+
 };
-- 
1.7.10.4




From c.hemp at phytec.de  Wed May 29 17:06:47 2013
From: c.hemp at phytec.de (Christian Hemp)
Date: Wed, 29 May 2013 23:06:47 +0200
Subject: [PATCH 0/2] Add Phytec phyFLEX-i.MX6 board
Message-ID: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>

This patchset adds basic support for Phytec's phyFLEX-i.MX6.

It's based on git repo from Shwan Guo branche imx/dt

Christian Hemp (2):
  ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
  ARM: dts: Phytec phyFLEX-i.MX6 support

 arch/arm/boot/dts/Makefile                 |    1 +
 arch/arm/boot/dts/imx6q-phytec-phyflex.dts |   76 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6q.dtsi               |   33 ++++++++++++
 3 files changed, 110 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6q-phytec-phyflex.dts

-- 
1.7.9.5



From c.hemp at phytec.de  Wed May 29 17:06:48 2013
From: c.hemp at phytec.de (Christian Hemp)
Date: Wed, 29 May 2013 23:06:48 +0200
Subject: [PATCH 1/2] ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
In-Reply-To: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
References: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
Message-ID: <1369861609-30408-2-git-send-email-c.hemp@phytec.de>

Add a group to the usdhc2 and enet pinctrl.

Signed-off-by: Christian Hemp <c.hemp at phytec.de>
---
 arch/arm/boot/dts/imx6q.dtsi |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..c0c8b7b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -157,6 +157,28 @@
 							MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 						>;
 					};
+
+					pinctrl_enet_3: enetgrp-3 {
+						fsl,pins = <
+							MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+							MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+							MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+							MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+							MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+							MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+							MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+							MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+							MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+							MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+							MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+							MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+							MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+							MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+							MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+							MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1b0b0
+							MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+						>;
+					};
 				};
 
 				gpmi-nand {
@@ -266,6 +288,17 @@
 							MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
 						>;
 					};
+
+					pinctrl_usdhc2_2: usdhc2grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+							MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+							MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+							MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+							MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+							MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+						>;
+					};
 				};
 
 				usdhc3 {
-- 
1.7.9.5



From c.hemp at phytec.de  Wed May 29 17:06:49 2013
From: c.hemp at phytec.de (Christian Hemp)
Date: Wed, 29 May 2013 23:06:49 +0200
Subject: [PATCH 2/2] ARM: dts: Phytec phyFLEX-i.MX6 support
In-Reply-To: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
References: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
Message-ID: <1369861609-30408-3-git-send-email-c.hemp@phytec.de>

Add support for Phytec phyFLEX-i.MX6 board

Signed-off-by: Christian Hemp <c.hemp at phytec.de>
---
 arch/arm/boot/dts/Makefile                 |    1 +
 arch/arm/boot/dts/imx6q-phytec-phyflex.dts |   76 ++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6q-phytec-phyflex.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4c58951..6ffdaa1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard.dtb \
 	imx6q-arm2.dtb \
+	imx6q-phytec-phyflex.dtb \
 	imx6q-sabreauto.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
diff --git a/arch/arm/boot/dts/imx6q-phytec-phyflex.dts b/arch/arm/boot/dts/imx6q-phytec-phyflex.dts
new file mode 100644
index 0000000..9690691
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-phyflex.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6";
+	compatible = "phytec,phyflex-imx6", "fsl,imx6q";
+
+	memory {
+		reg = <0x10000000 0x80000000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+				MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+			>;
+		};
+	};
+
+	phyflex {
+		pinctrl_usdhc3_phyflex: usdhc3grp-phyflex {
+			fsl,pins = <
+				MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
+				MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+			>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_3>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 23 0>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_1>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_2>;
+	cd-gpios = <&gpio1 4 0>;
+	wp-gpios = <&gpio1 2 0>;
+	status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2
+		     &pinctrl_usdhc3_phyflex>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "okay";
+};
+
-- 
1.7.9.5



From jgchunter at gmail.com  Wed May 29 17:29:07 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Wed, 29 May 2013 22:29:07 +0100
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <20130529185518.GB3345@blackmetal.musicnaut.iki.fi>
References: <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com> <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
 <20130526190710.GA3345@blackmetal.musicnaut.iki.fi>
 <51A4FAA1.5060504@gmail.com>
 <20130529185518.GB3345@blackmetal.musicnaut.iki.fi>
Message-ID: <51A67323.7030906@gmail.com>


On 29/05/13 19:55, Aaro Koskinen wrote:
> Hi,
> 
> On Tue, May 28, 2013 at 07:42:41PM +0100, Jon Hunter wrote:
>> Care to share the log?
> 
> Below are three logs from 3.10-rc3 / Nokia 770. I did not even compile
> Retu this time, as it has nothing to do with GPIO IRQs being broken
> on OMAP1.

That's not entirely true. v3.10-rc3 is booting fine on an osk5912 and
ethernet is working which is using a gpio for interrupts and it is
getting interrupts.

> 1) broken vanilla 3.10-rc3: serial wakeup GPIO irq gets IRQ 0 and no
> other GPIO IRQs seen in /proc/interrupts. genirq error logs seen in boot.

Getting 0 for the irq number definitely looks like the problem.

> 2) working 3.10-rc3 with Tony's fix <== this fix should be applied
> (http://marc.info/?l=linux-arm-kernel&m=136907202628855&w=2). GPIO IRQs
> are normal, e.g. touchscreen can be used.
> 
> 3) .config used.

I am using the omap1_defconfig. Can you try that one for comparison?

Jon


From mturquette at linaro.org  Wed May 29 17:48:13 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 14:48:13 -0700
Subject: [PATCH 0/2] clk: vt8500: updates for 3.11
In-Reply-To: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>
References: <1368433260-16073-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <20130529214813.6058.81599@quantum>

Quoting Tony Prisk (2013-05-13 01:20:58)
> Hi Mike,
> 
> Two updates for the arch-vt8500 clock code:
> 
> #1: Add support for the WM8850 PLL.
> #2: Remove a second divisor check in vt8500_dclk_set_rate() which causes the
> divisor to be round-down too low.
> 

Taken both into clk-next.

Thanks,
Mike

> Regards
> Tony Prisk
> 
> Tony Prisk (2):
>   clk: vt8500: Add support for clocks on the WM8850 SoCs
>   clk: vt8500: Remove unnecessary divisor adjustment in
>     vtwm_dclk_set_rate()
> 
>  Documentation/devicetree/bindings/clock/vt8500.txt |    2 +
>  drivers/clk/clk-vt8500.c                           |   75 ++++++++++++++++++--
>  2 files changed, 73 insertions(+), 4 deletions(-)
> 
> -- 
> 1.7.9.5


From arnd at arndb.de  Wed May 29 17:51:40 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 29 May 2013 23:51:40 +0200
Subject: Single zImage and A15/LPAE
In-Reply-To: <20130529151555.GP17767@MacBook-Pro.local>
References: <50735B75.8070109@wwwdotorg.org> <2274563.opVbLLPT1p@wuerfel>
 <20130529151555.GP17767@MacBook-Pro.local>
Message-ID: <201305292351.41096.arnd@arndb.de>

On Wednesday 29 May 2013, Catalin Marinas wrote:
> > I think to do this right, we need to treat ARMv7+LPAE as a separate
> > architecture level, just like we treat ARMv6, ARMv7 as separate
> > compatible architectures. BTW, is there an official name for that
> > architecture?
> 
> The official is Large Physical Address Extension which is an extension
> to ARMv7, so not a new architecture.

Ah, too bad. I had hoped there were still postfixes like v6K or v4T.
I guess there is no complete list of ARMv7 extensions anywhere, right?

	Arnd


From arno at natisbad.org  Wed May 29 18:00:36 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Thu, 30 May 2013 00:00:36 +0200
Subject: [PATCH] arm: kirkwood: convert NETGEAR ReadyNAS Duo v2 to use DT
 for the PCIe interface
In-Reply-To: <20130529114846.GQ31290@titan.lakedaemon.net> (Jason Cooper's
 message of "Wed, 29 May 2013 07:48:46 -0400")
References: <8738t6ycnm.fsf@natisbad.org>
 <20130529114846.GQ31290@titan.lakedaemon.net>
Message-ID: <87li6xla4b.fsf@natisbad.org>

Hi Jason,

Jason Cooper <jason at lakedaemon.net> writes:

>>  arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts |    8 ++++++++
>>  arch/arm/mach-kirkwood/board-readynas.c                |    1 -
>>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> Hey, I had a little time to kill, so I went ahead and fixed this up.
> Let me know if this looks ok.  I've applied it to mvebu/pcie_kirkwood,
> so you should just be able to pull that and test it.  I'll push it up to
> arm-soc in a week or so.

Pulled the branch, compiled and tested it: USB 3.0 host controller
connected to PCIe bus works as expected.

Thanks for your work,

Cheers,

a+


From arnd at arndb.de  Wed May 29 18:02:45 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 30 May 2013 00:02:45 +0200
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <Pine.LNX.4.44L0.1305291415150.885-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305291415150.885-100000@iolanthe.rowland.org>
Message-ID: <201305300002.45754.arnd@arndb.de>

On Wednesday 29 May 2013, Alan Stern wrote:
> 
> On Wed, 29 May 2013, Arnd Bergmann wrote:
> 
> > On Wednesday 29 May 2013 12:21:02 Alan Stern wrote:
> > > 
> > > Those error messages are annoying; they don't use dev_err(), so they
> > > don't include the device and driver names.  There's no way to know what
> > > they refer to.  I rather suspect they come from the usbaudio driver.
> > 
> > That makes sense. I have a usb audio device, and I don't actually recall
> > getting any sound from my speakers while testing it. I only checked
> > that the mouse was working and assumed that the usb-audio was driven
> > by ehci, but upon closer inspection, they are both on the same OHCI.
> > 
> > > When you ran this test, did you have commit 815fa7b91761 applied?
> > 
> > Yes.
> > 
> > > Does the same problem occur without Manjunath's changes?
> > 
> > No, it was introduced by the first patch, as I found later.
> 
> I'll try to replicate your result.  I don't have my USB audio device 
> here today, so it will have to wait until tomorrow.

Strange enough, it seems to be working now, on a different base.

The kernel I tried last (based on yesterday's linux-next) also
had other issues and was very slow, so it may have been something
different.

	Arnd


From mturquette at linaro.org  Wed May 29 18:11:50 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 15:11:50 -0700
Subject: [PATCH v2 1/2] clk: si5351: Fix clkout rate computation.
In-Reply-To: <51949076.9040008@streamunlimited.com>
References: <1367560403-21685-1-git-send-email-marek.belisko@streamunlimited.com>
 <20130514191650.10068.92925@quantum> <51949076.9040008@streamunlimited.com>
Message-ID: <20130529221150.6058.5735@quantum>

Quoting Marek Belisko (2013-05-16 00:53:26)
> On 05/14/2013 09:16 PM, Mike Turquette wrote:
> > Quoting Marek Belisko (2013-05-02 22:53:22)
> >> Rate was incorrectly computed because we read from wrong divider register.
> >>
> >> Signed-off-by: Marek Belisko <marek.belisko at streamunlimited.com>
> >> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> >
> > Do either of these patches need to go into clk-fixes?  If so please be
> > explicit about it in the changelog, the section under the three dashes.
> Yes I believe they should go to clk-fixes (probably also to linux-stable).

Pulled both into clk-fixes.  I added the missing changelog to patch #2
because I am such a nice guy.

Regards,
Mike

> >
> > Regards,
> > Mike
> >
> >> ---
> >>   drivers/clk/clk-si5351.c |    2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> >> index 8927284..cf39e53 100644
> >> --- a/drivers/clk/clk-si5351.c
> >> +++ b/drivers/clk/clk-si5351.c
> >> @@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
> >>          unsigned char reg;
> >>          unsigned char rdiv;
> >>
> >> -       if (hwdata->num > 5)
> >> +       if (hwdata->num <= 5)
> >>                  reg = si5351_msynth_params_address(hwdata->num) + 2;
> >>          else
> >>                  reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
> >> --
> >> 1.7.9.5
> >
> 
> Regards,
> 
> Marek
> -- 
> Marek Belisko
> 
> Software Developer
> StreamUnlimited Engineering GmbH
> Gutheil Schodergasse 8-12
> A-1100 Vienna, Austria
> 
> Office: +421 267200087
> 
> e-mail: marek.belisko at streamunlimited.com
> http://www.streamunlimited.com
> 
> Meet us at:
> 
> IFA - Berlin, 6-11 September
> CEDIA - Denver, 25-28 September


From eduardo.valentin at ti.com  Wed May 29 18:11:51 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Wed, 29 May 2013 18:11:51 -0400
Subject: [PATCH] thermal: step_wise: cdev only needs update on a new target
 state
In-Reply-To: <1369724148-15087-1-git-send-email-shawn.guo@linaro.org>
References: <1369724148-15087-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <51A67D27.9050502@ti.com>

Rui,

On 28-05-2013 02:55, Shawn Guo wrote:
> The cooling device only needs update on a new target state.  Since we
> already check old target in thermal_zone_trip_update(), we can do one
> more check to see if it's a new target state.  If not, we can reasonably
> save some uncecesary code execution.
> 

typo above:
s/uncecesary/unnecessary

> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---

A part from the above typo, I believe we must have this change in:

Acked-by: Eduardo Valentin <eduardo.valentin at ti.com>

>  drivers/thermal/step_wise.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/thermal/step_wise.c b/drivers/thermal/step_wise.c
> index 4d4ddae..0afbd86 100644
> --- a/drivers/thermal/step_wise.c
> +++ b/drivers/thermal/step_wise.c
> @@ -133,6 +133,9 @@ static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip)
>  		old_target = instance->target;
>  		instance->target = get_target_state(instance, trend, throttle);
>  
> +		if (old_target == instance->target)
> +			continue;
> +
>  		/* Activate a passive thermal instance */
>  		if (old_target == THERMAL_NO_TARGET &&
>  			instance->target != THERMAL_NO_TARGET)
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin

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From horms+renesas at verge.net.au  Wed May 29 18:28:47 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Thu, 30 May 2013 07:28:47 +0900
Subject: [GIT PULL] Renesas ARM based SoC fixes for v3.10
Message-ID: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 

for you to fetch changes up to c7f413548dce3d25609c12efe963b3e6c8e678f3:

  ARM: shmobile: sh73a0: Update CMT clockevent rating to 80 (2013-05-28 14:46:38 +0900)

----------------------------------------------------------------
Renesas ARM based SoC fixes for v3.10

* Correction to USB OVC and PENC pin groupings on r8a7779 SoC.
  This avoids conflicts when the USB_OVCn pins are used by another function.
  This has been observed to be a problem in v3.10-rc1.

* Update CMT clock rating for sh73a0 SoC to resolve boot failure
  on kzm9g-reference. This resolves a regression between v3.9 and v3.10-rc1.

----------------------------------------------------------------
Laurent Pinchart (1):
      sh-pfc: r8a7779: Don't group USB OVC and PENC pins

Simon Horman (1):
      ARM: shmobile: sh73a0: Update CMT clockevent rating to 80

 arch/arm/mach-shmobile/setup-sh73a0.c |    2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c  |   45 ++++++++++++++++++++++++++-------
 2 files changed, 37 insertions(+), 10 deletions(-)


From horms+renesas at verge.net.au  Wed May 29 18:28:49 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Thu, 30 May 2013 07:28:49 +0900
Subject: [PATCH 2/2] ARM: shmobile: sh73a0: Update CMT clockevent rating to 80
In-Reply-To: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369866529-6372-3-git-send-email-horms+renesas@verge.net.au>

Update the CMT clockevent rating from 125 to 80.

This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp:
Avoid dummy clockevent being preferred over real").

The patch noted above reduces the rating of dummy clockevent from 400 to 100.
This patch reduces the rating of CMT so that it is once again less than that
of the dummy clockevent.

Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/setup-sh73a0.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894..9696f36 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
 	.name = "CMT10",
 	.channel_offset = 0x10,
 	.timer_bit = 0,
-	.clockevent_rating = 125,
+	.clockevent_rating = 80,
 	.clocksource_rating = 125,
 };
 
-- 
1.7.10.4



From horms+renesas at verge.net.au  Wed May 29 18:28:48 2013
From: horms+renesas at verge.net.au (Simon Horman)
Date: Thu, 30 May 2013 07:28:48 +0900
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
Message-ID: <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>

From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

The USB_OVCn pins are alternate options for USB over-current detection
when using a 3.3V USB interface. As they're not mandatory they can be
used independently of the USB PENC pins. Don't group the USB_OVCn and
PENC pins to avoid conflicts when the USB_OVCn pins are used by another
function.

Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   45 +++++++++++++++++++++++++++-------
 1 file changed, 36 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 791a671..8cd90e7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2357,27 +2357,48 @@ static const unsigned int sdhi3_wp_mux[] = {
 };
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
-	/* OVC */
-	150, 154,
+	/* PENC */
+	154,
 };
 static const unsigned int usb0_mux[] = {
-	USB_OVC0_MARK, USB_PENC0_MARK,
+	USB_PENC0_MARK,
+};
+static const unsigned int usb0_ovc_pins[] = {
+	/* USB_OVC */
+	150
+};
+static const unsigned int usb0_ovc_mux[] = {
+	USB_OVC0_MARK,
 };
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
-	/* OVC */
-	152, 155,
+	/* PENC */
+	155,
 };
 static const unsigned int usb1_mux[] = {
-	USB_OVC1_MARK, USB_PENC1_MARK,
+	USB_PENC1_MARK,
+};
+static const unsigned int usb1_ovc_pins[] = {
+	/* USB_OVC */
+	152,
+};
+static const unsigned int usb1_ovc_mux[] = {
+	USB_OVC1_MARK,
 };
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
-	/* OVC, PENC */
-	125, 156,
+	/* PENC */
+	156,
 };
 static const unsigned int usb2_mux[] = {
-	USB_OVC2_MARK, USB_PENC2_MARK,
+	USB_PENC2_MARK,
+};
+static const unsigned int usb2_ovc_pins[] = {
+	/* USB_OVC */
+	125,
+};
+static const unsigned int usb2_ovc_mux[] = {
+	USB_OVC2_MARK,
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
@@ -2501,8 +2522,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi3_cd),
 	SH_PFC_PIN_GROUP(sdhi3_wp),
 	SH_PFC_PIN_GROUP(usb0),
+	SH_PFC_PIN_GROUP(usb0_ovc),
 	SH_PFC_PIN_GROUP(usb1),
+	SH_PFC_PIN_GROUP(usb1_ovc),
 	SH_PFC_PIN_GROUP(usb2),
+	SH_PFC_PIN_GROUP(usb2_ovc),
 };
 
 static const char * const du0_groups[] = {
@@ -2683,14 +2707,17 @@ static const char * const sdhi3_groups[] = {
 
 static const char * const usb0_groups[] = {
 	"usb0",
+	"usb0_ovc",
 };
 
 static const char * const usb1_groups[] = {
 	"usb1",
+	"usb1_ovc",
 };
 
 static const char * const usb2_groups[] = {
 	"usb2",
+	"usb2_ovc",
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
-- 
1.7.10.4



From sergei.shtylyov at cogentembedded.com  Wed May 29 18:35:51 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 30 May 2013 02:35:51 +0400
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <51A682C7.9060605@cogentembedded.com>

Hello.

On 05/30/2013 02:28 AM, Simon Horman wrote:

> From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>
> The USB_OVCn pins are alternate options for USB over-current detection
> when using a 3.3V USB interface. As they're not mandatory they can be
> used independently of the USB PENC pins. Don't group the USB_OVCn and
> PENC pins to avoid conflicts when the USB_OVCn pins are used by another
> function.
>
> Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

    I suspect this is needed in -stable. The bug is older than 3.10-rc1.

WBR, Sergei



From jgchunter at gmail.com  Wed May 29 18:41:52 2013
From: jgchunter at gmail.com (Jon Hunter)
Date: Wed, 29 May 2013 23:41:52 +0100
Subject: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
In-Reply-To: <51A67323.7030906@gmail.com>
References: <20130516180933.GG5600@atomide.com>
 <20130516210006.GA31836@blackmetal.musicnaut.iki.fi>
 <20130516214430.GN5600@atomide.com> <20130520174621.GI10378@atomide.com>
 <20130521173936.GE31836@blackmetal.musicnaut.iki.fi>
 <519BCCEC.8010303@gmail.com>
 <20130522212054.GG31836@blackmetal.musicnaut.iki.fi>
 <519E67AD.6070702@gmail.com>
 <20130526190710.GA3345@blackmetal.musicnaut.iki.fi>
 <51A4FAA1.5060504@gmail.com>
 <20130529185518.GB3345@blackmetal.musicnaut.iki.fi>
 <51A67323.7030906@gmail.com>
Message-ID: <51A68430.1050102@gmail.com>


On 29/05/13 22:29, Jon Hunter wrote:
> 
> On 29/05/13 19:55, Aaro Koskinen wrote:
>> Hi,
>>
>> On Tue, May 28, 2013 at 07:42:41PM +0100, Jon Hunter wrote:
>>> Care to share the log?
>>
>> Below are three logs from 3.10-rc3 / Nokia 770. I did not even compile
>> Retu this time, as it has nothing to do with GPIO IRQs being broken
>> on OMAP1.
> 
> That's not entirely true. v3.10-rc3 is booting fine on an osk5912 and
> ethernet is working which is using a gpio for interrupts and it is
> getting interrupts.

Scratch that. It appears that the osk is using gpio-0 as the interrupt
and so it is only by chance this is working. I agree it is broken and so
Tony's fix is needed.

Jon




From mturquette at linaro.org  Wed May 29 18:48:49 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 15:48:49 -0700
Subject: [PATCH] clk: sunxi: "cpu_data" is defined in header files of some
 architectures
In-Reply-To: <1368798200-7063-1-git-send-email-emilio@elopez.com.ar>
References: <5195D615.70608@cateee.net>
 <1368798200-7063-1-git-send-email-emilio@elopez.com.ar>
Message-ID: <20130529224849.6058.25112@quantum>

Quoting Emilio L?pez (2013-05-17 06:43:20)
> From: "Giacomo A. Catenazzi" <cate at cateee.net>
> 
> In some architectures, the #define cpu_data is not a "macro-function",
> so the compiler will substitute the identifier with probably something
> wrong.
> 
> Signed-off-by: Giacomo A. Catenazzi <cate at cateee.net>
> Signed-off-by: Emilio L?pez <emilio at elopez.com.ar>
> [emilio at elopez.com.ar: use cpu_mux_data instead of this_cpu_data]

Taken into clk-next.

Regards,
Mike

> ---
> 
> Hi Giacomo,
> 
> I have taken your patch and resent it to linux-arm-kernel and Mike 
> Turquette this time, but please try to use git send-email on your next 
> patch.
> 
> Here is a video from Greg that explains how to use it as well as other 
> things (checkpatch.pl, get_maintainer.pl, etc)
> 
> http://www.youtube.com/watch?v=LLBrBBImJt4
> 
> Thanks! :)
> 
> Emilio
> 
>  drivers/clk/sunxi/clk-sunxi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 930d36f..412912b 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -239,7 +239,7 @@ struct mux_data {
>         u8 shift;
>  };
>  
> -static const __initconst struct mux_data cpu_data = {
> +static const __initconst struct mux_data cpu_mux_data = {
>         .shift = 16,
>  };
>  
> @@ -433,7 +433,7 @@ static const __initconst struct of_device_id clk_div_match[] = {
>  
>  /* Matches for mux clocks */
>  static const __initconst struct of_device_id clk_mux_match[] = {
> -       {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_data,},
> +       {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,},
>         {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
>         {}
>  };
> -- 
> 1.8.2.3


From mturquette at linaro.org  Wed May 29 19:05:16 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 16:05:16 -0700
Subject: [PATCH] ARM : omap3 : fix wrong container_of in clock36xx.c
In-Reply-To: <1368805886-26085-1-git-send-email-jp.francois@cynove.com>
References: <CAGGh5h3BNV7fE3jC0KSmA+2K6zKwVyHdeo8AW0gvmhgQsy8ZEg@mail.gmail.com>
 <1368805886-26085-1-git-send-email-jp.francois@cynove.com>
Message-ID: <20130529230516.6058.74417@quantum>

Quoting Jean-Philippe Francois (2013-05-17 08:51:26)
> omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
> to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
> have parent defined as clk_divider.
> Fix the function to use clk_divider. 
> Tested with  3.9 on dm3730.
> 
> Signed-off-by: Jean-Philippe Fran??ois <jp.francois at cynove.com>
> 
> Index: b/arch/arm/mach-omap2/clock36xx.c
> ===================================================================
> --- a/arch/arm/mach-omap2/clock36xx.c
> +++ b/arch/arm/mach-omap2/clock36xx.c
> @@ -20,11 +20,12 @@
>  
>  #include <linux/kernel.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/io.h>
>  
>  #include "clock.h"
>  #include "clock36xx.h"
> -
> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
>  
>  /**
>   * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
> @@ -39,29 +40,28 @@
>   */
>  int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
>  {
> -       struct clk_hw_omap *parent;
> +       struct clk_divider *parent;
>         struct clk_hw *parent_hw;
> -       u32 dummy_v, orig_v, clksel_shift;
> +       u32 dummy_v, orig_v;
>         int ret;
>  
>         /* Clear PWRDN bit of HSDIVIDER */
>         ret = omap2_dflt_clk_enable(clk);
>  
>         parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
> -       parent = to_clk_hw_omap(parent_hw);
> +       parent = to_clk_divider(parent_hw);

Peaking inside of clock structures was OK back in the legacy clock days,
and even if the clocks are the same type (clk_hw_omap), but having omap
code dig into clk-divider structures is pretty gross.

How about reentrantly calling clk_set_rate here to achieve the same
effect?

	/* kick parent's clksel register after toggling PWRDN bit */
	struct clk *parent = clk_get_parent(clk->clk);
	unsigned long parent_rate = clk_get_rate(parent);
	clk_set_rate(parent, parent_rate/2);
	clk_set_rate(parent, parent_rate);

Regards,
Mike

>  
>         /* Restore the dividers */
>         if (!ret) {
> -               clksel_shift = __ffs(parent->clksel_mask);
> -               orig_v = __raw_readl(parent->clksel_reg);
> +               orig_v = __raw_readl(parent->reg);
>                 dummy_v = orig_v;
>  
>                 /* Write any other value different from the Read value */
> -               dummy_v ^= (1 << clksel_shift);
> -               __raw_writel(dummy_v, parent->clksel_reg);
> +               dummy_v ^= (1 << parent->shift);
> +               __raw_writel(dummy_v, parent->reg);
>  
>                 /* Write the original divider */
> -               __raw_writel(orig_v, parent->clksel_reg);
> +               __raw_writel(orig_v, parent->reg);
>         }
>  
>         return ret;


From mturquette at linaro.org  Wed May 29 19:16:49 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 16:16:49 -0700
Subject: [PATCH 4/4] MAINTAINERS: vt8500: Add clk-vt8500.c to MAINTAINERS
 file
In-Reply-To: <51973C1D.2080404@prisktech.co.nz>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
 <1368825532-30917-5-git-send-email-linux@prisktech.co.nz>
 <CABjd4Yw2LbnaUbQFW_bd_6WRGTA34-Vp_tUC2b4Jczj-MM8x1w@mail.gmail.com>
 <51973C1D.2080404@prisktech.co.nz>
Message-ID: <20130529231649.6058.4589@quantum>

Quoting Tony Prisk (2013-05-18 01:30:21)
> On 18/05/13 18:40, Alexey Charkov wrote:
> > On 18 May 2013 01:18, "Tony Prisk" <linux at prisktech.co.nz> wrote:
> >> This file has missed being added under ARM/VT8500 ARM ARCHITECTURE,
> >> and is maintained along with the rest of the vt8500 arch code.
> >>
> >> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
> >> ---
> >>   MAINTAINERS |    1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 3d7782b..5ab8ccb 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -1283,6 +1283,7 @@ M:        Tony Prisk <linux at prisktech.co.nz>
> >>   L:     linux-arm-kernel at lists.infradead.org (moderated for
> > non-subscribers)
> >>   S:     Maintained
> >>   F:     arch/arm/mach-vt8500/
> >> +F:     drivers/clk/vt8500-vt8500.c
> > This looks like a typo (clk vs. vt8500).
> >
> > Best,
> > Alexey
> >
> eeek - oops.
> 
> Mike,
> 
> Disregard this patch - I will send a more complete one through arm-soc 
> as there are other files missing as well.
> 

Hi Tony,

I've taken patch #1 into clk-fixes.  I took patches #2 & #3 into
clk-next from your previous series posted on May 13, which appear
identical to the ones in this series.  In the future could you put a
"v2" in the patch subject since those patches were re-posted?  It would
have helped me catch it.

I have not taken patch #4.

Does this all sound correct to you?

Thanks,
Mike

> Regards
> Tony P


From swarren at wwwdotorg.org  Wed May 29 19:19:20 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 17:19:20 -0600
Subject: [PATCH v7] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <1369753575-9818-1-git-send-email-p.zabel@pengutronix.de>
References: <1369753575-9818-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <51A68CF8.7000303@wwwdotorg.org>

On 05/28/2013 09:06 AM, Philipp Zabel wrote:
> This driver implements a reset controller device that toggle a gpio
> connected to a reset pin of a peripheral IC. The delay between assertion
> and de-assertion of the reset signal can be configured via device tree.

> diff --git a/drivers/reset/gpio-reset.c b/drivers/reset/gpio-reset.c

> +static void __gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)

Nit: Technically I think __ is a reserved name-space, so you shouldn't
prefix "user-level" (rather than libc/similar) symbols with it, but it's
not a big deal.

> +static int gpio_reset_probe(struct platform_device *pdev)

> +	if (of_gpio_named_count(np, "reset-gpios") != 1)
> +		return -EINVAL;

Should that error-path (and the path for of_property_read_u32() failure)
include a dev_err() like some already do, so it's obvious what the
failure is?

> +	reset_controller_register(&drvdata->rcdev);
> +
> +	platform_set_drvdata(pdev, drvdata);

It might be better to set the drvdata right after it's been allocated.
It perhaps doesn't matter much here, but if the reset controller core
ever starts calling into the registered device inside the call to
reset_controller_register(), then there might be a problem.

Aside from those minor issues,
Reviewed-by: Stephen Warren <swarren at nvidia.com>


From mturquette at linaro.org  Wed May 29 19:22:20 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 May 2013 16:22:20 -0700
Subject: [GIT PULL 2/5] ARM: mvebu: pcie driver for v3.11 (round 2
 cumulative)
In-Reply-To: <20130528202433.GH31290@titan.lakedaemon.net>
References: <20130528202140.GG31290@titan.lakedaemon.net>
 <20130528202433.GH31290@titan.lakedaemon.net>
Message-ID: <20130529232220.6058.14477@quantum>

Quoting Jason Cooper (2013-05-28 13:24:33)
> The following changes since commit 4e23d3f505e8acfeac7cc33d4113fbb5a25c3090:
> 
>   of/pci: Add of_pci_parse_bus_range() function (2013-05-19 20:30:10 +0000)
> 
> are available in the git repository at:
> 
>   git://git.infradead.org/users/jcooper/linux.git tags/pcie-3.11-2
> 
> for you to fetch changes up to 3d9939c92efdd4ced672b94994959ca71b141cb8:
> 
>   pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)
> 
> ----------------------------------------------------------------
> mvebu pcie driver for v3.11 (round 2, bugfix)
> 
>  - mvebu pcie
>     - fix return value check in mvebu_pcie_probe()
> 
> depends
>  - mvebu/of_pci
> 
> ----------------------------------------------------------------
> Thomas Petazzoni (4):
>       clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
>       clk: mvebu: add more PCIe clocks for Armada XP

Same story here for pull request #2 as for pull request #5.  The clock
changes are trivial: Ack.  However if it is a pain to add the ack don't
worry about it.

Regards,
Mike

>       pci: PCIe driver for Marvell Armada 370/XP systems
>       arm: mvebu: PCIe support is now available on mvebu
> 
> Wei Yongjun (1):
>       pci: mvebu: fix return value check in mvebu_pcie_probe()
> 
>  .../devicetree/bindings/pci/mvebu-pci.txt          | 220 ++++++
>  arch/arm/mach-mvebu/Kconfig                        |   2 +
>  drivers/clk/mvebu/clk-gating-ctrl.c                |  18 +-
>  drivers/pci/Kconfig                                |   2 +
>  drivers/pci/Makefile                               |   3 +
>  drivers/pci/host/Kconfig                           |   8 +
>  drivers/pci/host/Makefile                          |   1 +
>  drivers/pci/host/pci-mvebu.c                       | 880 +++++++++++++++++++++
>  8 files changed, 1128 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
>  create mode 100644 drivers/pci/host/Kconfig
>  create mode 100644 drivers/pci/host/Makefile
>  create mode 100644 drivers/pci/host/pci-mvebu.c
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From dgilbert at interlog.com  Wed May 29 19:22:48 2013
From: dgilbert at interlog.com (Douglas Gilbert)
Date: Wed, 29 May 2013 19:22:48 -0400
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
 <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
Message-ID: <51A68DC8.3090703@interlog.com>

On 13-05-29 04:41 PM, Robert Nelson wrote:
> On Wed, May 29, 2013 at 3:33 PM, Andrew Morton
> <akpm at linux-foundation.org> wrote:
>> On Thu, 23 May 2013 10:38:50 +0200 Johan Hovold <jhovold at gmail.com> wrote:
>>
>>> This is an update of the shadow-interrupt-mask series against v3.10-rc2.
>>>
>>> I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
>>> affected. If not, then some probing mechanism as the one Doug suggested
>>> could be implemented on top of (a subset of) these patches. What do you
>>> say, Nicolas?
>>>
>>> Note that the first patch (adding a missing OF compile guard) could be
>>> applied straight away.
>>
>> At this stage it is unclear to me how to proceed with patches 2-5.
>
> fyi:
>
> A version of these patches had been applied once before:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0ef1594c017521ea89278e80fe3f80dafb17abde
>
> But due to a few issues it was later reverted:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=e24b0bfa2f0446ffaad2661040be23668133aef8

Strange life of a patch. Mine was the original, Johan Hovold
objected and had it reverted. Johan then presented his first
patch then v2. They got lost in the weeds.

My hardware was still broken and this bug caused collateral
damage. My original patch no longer applied to lk 3.10.0-rc1
so I rewrote it, borrowing some of Johan's ideas and doing a
probe time check for the broken RTC_IMR. That patch was
presented about a week ago:
   http://marc.info/?l=linux-arm-kernel&m=136917492531478&w=2
The top of that post gives some more background.

That prompted Johan to produce v3 of his patch which is the
subject of this thread. I was hoping that Nicolas Ferre would
comment or ack one of these patches. Still waiting.


I have a copy of the original, publicly released manual for
the at91sam9g25 (a member of the at91sam9x5 family) marked
"11032A?ATARM?27-Jul-11". It contains the following:
   Errata
   49.3.1
     RTC: Interrupt Mask Register cannot be used
          Interrupt Mask Register reading always returns 0.

Both Rev B and Rev C of that manual drop that particular
erratum. My g25 SoC-based subsystems come from an Atmel
partner and still have the RTC IMR bug.

Doug Gilbert




From dianders at chromium.org  Wed May 29 19:44:18 2013
From: dianders at chromium.org (Doug Anderson)
Date: Wed, 29 May 2013 16:44:18 -0700
Subject: [PATCH v2 2/5] clk: samsung: Add support to register rate_table
 for PLL3xxx
In-Reply-To: <1369834677-20312-3-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
 <1369834677-20312-3-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=VDi+SfebiFnPNp8qR__9L=o9TJ+WSPRfRQLX+p+TMmJw@mail.gmail.com>

Vikas / Yadwinder,

On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>
> This patch defines a common rate_table which will contain recommended p, m, s,
> k values for supported rates that needs to be changed for changing
> corresponding PLL's rate.
>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
>  drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
>  drivers/clk/samsung/clk-pll.c        |   14 ++++++++++++--
>  drivers/clk/samsung/clk-pll.h        |   33 +++++++++++++++++++++++++++++++--
>  4 files changed, 54 insertions(+), 15 deletions(-)

I also reviewed this in our gerrit
<https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize
here for the list...

>  struct clk * __init samsung_clk_register_pll35xx(const char *name,
> -                       const char *pname, const void __iomem *base)
> +                       const char *pname, const void __iomem *base,
> +                       const struct samsung_pll_rate_table *rate_table,
> +                       const unsigned int rate_count)

Feels like you should document here that rate_table needs to be sorted
and the sort order.

> +struct samsung_pll_rate_table {
> +       unsigned  int rate;

nit: extra space before "int" should be removed.

Also: you can include rate here if you need a convenient place to
store it (which sadly means that this structure can't be const).
...but I do like Tomasz's idea of actually calculating it.  You can't
know it at compile time since the parent rate comes from the device
tree.

compatible = "samsung,clock-xxti";
clock-frequency = <24000000>;

> +       unsigned int pdiv;
> +       unsigned int mdiv;
> +       unsigned int sdiv;
> +       unsigned int kdiv;

I think kdiv is signed.

-Doug


From laurent.pinchart at ideasonboard.com  Wed May 29 19:51:58 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 30 May 2013 01:51:58 +0200
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <51A682C7.9060605@cogentembedded.com>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <51A682C7.9060605@cogentembedded.com>
Message-ID: <23620997.ZR1QCYhSc2@avalon>

Hi Sergei,

On Thursday 30 May 2013 02:35:51 Sergei Shtylyov wrote:
> On 05/30/2013 02:28 AM, Simon Horman wrote:
> > From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> > 
> > The USB_OVCn pins are alternate options for USB over-current detection
> > when using a 3.3V USB interface. As they're not mandatory they can be
> > used independently of the USB PENC pins. Don't group the USB_OVCn and
> > PENC pins to avoid conflicts when the USB_OVCn pins are used by another
> > function.
> > 
> > Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> I suspect this is needed in -stable. The bug is older than 3.10-rc1.

Is it ? The offending commit is

commit 97d40c4224172451f666febdd865c24b1c3c3fe5
Author: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Date:   Thu Mar 7 13:38:51 2013 +0100

    sh-pfc: r8a7779: Add USB pin groups and functions
    
    Signed-off-by: Laurent Pinchart 
<laurent.pinchart+renesas at ideasonboard.com>
    Acked-by: Linus Walleij <linus.walleij at linaro.org>

and got applied to mainline in v3.10-rc1.

-- 
Regards,

Laurent Pinchart



From tony at atomide.com  Wed May 29 20:13:22 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 29 May 2013 17:13:22 -0700
Subject: [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates
 for 3.11
In-Reply-To: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <20130530001321.GR13507@atomide.com>

* Santosh Shilimkar <santosh.shilimkar at ti.com> [130529 09:44]:
> Tony, Paul,
> 
> Here is another attempt to send the SOC data files for OMAP5 based devices.
> As aligned on list, I have dropped clock data from the series.
> That means for the boot, one clock data patch needs to be applied.
> It is available on my git tree in 'out_of_tree/omap5_clk_data' branch.
> 
> With OMAP5 and AM33XX support is DT only, respective hwmod files are cleaned
> up to remove iospace information and un-used hwmod. For 3.11 since OMAP4
> is also targeted as DT only, its hwmod data files is also cleaned up.
> Diffstat looks something like below.
> 
> 27 files changed, 9013 insertions(+), 2764 deletions(-)
> 
> One can easily notice that the OMAP5 SOC data has significantly come down
> becasue of iospace and rest of the hwmod clean-up.

Yes that's great. I'd like to take the last three patches into my yet to
be posted omap-for-v3.11/cleanup branch with the omap4 legacy boot files
now that -rc3 is out and the GPIO fix dependency has cleared.

Paul, care to ack those three? Then you probably want to review queue
the rest I presume.

Regards,

Tony


From tony at atomide.com  Wed May 29 20:24:48 2013
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 29 May 2013 17:24:48 -0700
Subject: [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates
 for 3.11
In-Reply-To: <20130530001321.GR13507@atomide.com>
References: <1369845494-30231-1-git-send-email-santosh.shilimkar@ti.com>
 <20130530001321.GR13507@atomide.com>
Message-ID: <20130530002447.GS13507@atomide.com>

* Tony Lindgren <tony at atomide.com> [130529 17:19]:
> * Santosh Shilimkar <santosh.shilimkar at ti.com> [130529 09:44]:
> > Tony, Paul,
> > 
> > Here is another attempt to send the SOC data files for OMAP5 based devices.
> > As aligned on list, I have dropped clock data from the series.
> > That means for the boot, one clock data patch needs to be applied.
> > It is available on my git tree in 'out_of_tree/omap5_clk_data' branch.
> > 
> > With OMAP5 and AM33XX support is DT only, respective hwmod files are cleaned
> > up to remove iospace information and un-used hwmod. For 3.11 since OMAP4
> > is also targeted as DT only, its hwmod data files is also cleaned up.
> > Diffstat looks something like below.
> > 
> > 27 files changed, 9013 insertions(+), 2764 deletions(-)
> > 
> > One can easily notice that the OMAP5 SOC data has significantly come down
> > becasue of iospace and rest of the hwmod clean-up.
> 
> Yes that's great. I'd like to take the last three patches into my yet to
> be posted omap-for-v3.11/cleanup branch with the omap4 legacy boot files
> now that -rc3 is out and the GPIO fix dependency has cleared.
> 
> Paul, care to ack those three? Then you probably want to review queue
> the rest I presume.

Correction: The last two patches I mean.

Regards,

Tony


From jason at lakedaemon.net  Wed May 29 20:26:22 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 May 2013 20:26:22 -0400
Subject: [GIT PULL 2/5] ARM: mvebu: pcie driver for v3.11 (round 2
 cumulative)
In-Reply-To: <20130529232220.6058.14477@quantum>
References: <20130528202140.GG31290@titan.lakedaemon.net>
 <20130528202433.GH31290@titan.lakedaemon.net>
 <20130529232220.6058.14477@quantum>
Message-ID: <20130530002622.GB31290@titan.lakedaemon.net>

On Wed, May 29, 2013 at 04:22:20PM -0700, Mike Turquette wrote:
> Quoting Jason Cooper (2013-05-28 13:24:33)
> > The following changes since commit 4e23d3f505e8acfeac7cc33d4113fbb5a25c3090:
> > 
> >   of/pci: Add of_pci_parse_bus_range() function (2013-05-19 20:30:10 +0000)
> > 
> > are available in the git repository at:
> > 
> >   git://git.infradead.org/users/jcooper/linux.git tags/pcie-3.11-2
> > 
> > for you to fetch changes up to 3d9939c92efdd4ced672b94994959ca71b141cb8:
> > 
> >   pci: mvebu: fix return value check in mvebu_pcie_probe() (2013-05-27 15:51:56 +0000)
> > 
> > ----------------------------------------------------------------
> > mvebu pcie driver for v3.11 (round 2, bugfix)
> > 
> >  - mvebu pcie
> >     - fix return value check in mvebu_pcie_probe()
> > 
> > depends
> >  - mvebu/of_pci
> > 
> > ----------------------------------------------------------------
> > Thomas Petazzoni (4):
> >       clk: mvebu: create parent-child relation for PCIe clocks on Armada 370
> >       clk: mvebu: add more PCIe clocks for Armada XP
> 
> Same story here for pull request #2 as for pull request #5.  The clock
> changes are trivial: Ack.  However if it is a pain to add the ack don't
> worry about it.

Ok, thanks for the Ack.  In this case, I'm going to wave off.  I would
have to rebase 4 branches (3 depend on this one) and send 4 new PRs.

thx,

Jason.


From christoffer.dall at linaro.org  Wed May 29 21:14:30 2013
From: christoffer.dall at linaro.org (Christoffer Dall)
Date: Wed, 29 May 2013 18:14:30 -0700
Subject: [PATCH v3] ARM: KVM: mm: Get rid of L_PTE_USER ref from PAGE_S2_DEVICE
Message-ID: <1369876470-49540-1-git-send-email-christoffer.dall@linaro.org>

THe L_PTE_USER actually has nothing to do with stage 2 mappings and the
L_PTE_S2_RDWR value sets the readable bit, which was what L_PTE_USER
was used for before proper handling of stage 2 memory defines.

Changelog:
 [v3]: Drop call to kvm_set_s2pte_writable in mmu.c
 [v2]: Change default mappings to be r/w instead of r/o, as per Marc
       Zyngier's suggestion.

Cc: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall at linaro.org>
---
 arch/arm/include/asm/pgtable.h |    2 +-
 arch/arm/kvm/mmu.c             |    1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262..8afc60c 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -97,7 +97,7 @@ extern pgprot_t		pgprot_s2_device;
 #define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_HYP)
 #define PAGE_HYP_DEVICE		_MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
 #define PAGE_S2			_MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
-#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE		_MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)
 
 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 2f12e40..d80264c 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -485,7 +485,6 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
 
 	for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
 		pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
-		kvm_set_s2pte_writable(&pte);
 
 		ret = mmu_topup_memory_cache(&cache, 2, 2);
 		if (ret)
-- 
1.7.9.5



From magnus.damm at gmail.com  Wed May 29 21:32:55 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 10:32:55 +0900
Subject: [PATCH 2/9] ARM: shmobile: add GPIO IRQ macro
In-Reply-To: <20130528061828.GA20031@quad.lixom.net>
References: <1369648773-7941-1-git-send-email-horms+renesas@verge.net.au>
 <1369648773-7941-3-git-send-email-horms+renesas@verge.net.au>
 <20130528040729.GN13532@quad.lixom.net>
 <CANqRtoTUyaqfK3Droq3EuMZy-p2gzzTtcSTp=wiSM-3j0f4+Dg@mail.gmail.com>
 <20130528061828.GA20031@quad.lixom.net>
Message-ID: <CANqRtoQEY0pEAdtTcUCzOTADBcV8aebKEUD8wQHoLwibo1++8A@mail.gmail.com>

Hey Olof,

On Tue, May 28, 2013 at 3:18 PM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, May 28, 2013 at 02:53:04PM +0900, Magnus Damm wrote:
>> Hi Olof,
>>
>> On Tue, May 28, 2013 at 1:07 PM, Olof Johansson <olof at lixom.net> wrote:
>> > On Mon, May 27, 2013 at 06:59:26PM +0900, Simon Horman wrote:
>> >> From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
>> >>
>> >> R-Car series gpio_rcar driver can control GPIO IRQ today.
>> >> It needs base IRQ number for gpio_rcar_config :: .irq_base
>> >> This patch adds macro for GPIO IRQ.
>> >> This patch was tested on Bock-W board
>> >>
>> >> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
>> >> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>> >> ---
>> >>  arch/arm/mach-shmobile/include/mach/irqs.h |    5 +++++
>> >>  1 file changed, 5 insertions(+)
>> >>
>> >> diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
>> >> index b2074e2..d241bfd 100644
>> >> --- a/arch/arm/mach-shmobile/include/mach/irqs.h
>> >> +++ b/arch/arm/mach-shmobile/include/mach/irqs.h
>> >> @@ -16,4 +16,9 @@
>> >>  #define IRQPIN_BASE          2000
>> >>  #define irq_pin(nr)          ((nr) + IRQPIN_BASE)
>> >>
>> >> +/* GPIO IRQ */
>> >> +#define _GPIO_IRQ_BASE               2500
>> >> +#define GPIO_IRQ_BASE(x)     (_GPIO_IRQ_BASE + (32 * x))
>> >> +#define GPIO_IRQ(x, y)               (_GPIO_IRQ_BASE + (32 * x) + y)
>> >> +
>> >>  #endif /* __ASM_MACH_IRQS_H */
>> >
>> > Hmm. It'd be real nice to see some effort on moving this over to sparse
>> > irq instead. That'll be needed for full device tree conversion anyway. And
>> > with that, the static irq bases will be gone, so drivers and some of
>> > the platform code will need to be adjusted accordingly.
>>
>> I believe we've been doing sparse IRQ for ages, this is just to make
>> non-DT stuff more readable.
>>
>> Or was there some particular other interface you wanted us to use for
>> non-DT board code?
>
> Sorry, terminology confusion on my side. Most other platforms sorted
> this out when they moved to sparse irq, removing most hardcoded interrupt
> numbers at the same time and handling it through DT. But since shmobile
> still has a ways to go on DT conversion things are a bit different.
>
> Either way, once things have been converted fully to DT, most of these
> static numberings can/should be possible to remove.

Yes, exactly! Please note that the current drivers are written to be
DT aware and the IRQ code makes use of IRQ domains, so like you say
the DT -reference board code does not need to make use of these kind
of macros.

However, we are still not able to swith to DT fully due to lack of DT
support for PINMUX/GPIO. One even larger road block is the common
clock framework. And then we have the I/O power domains used with
Runtime PM on sh7372.

Thanks for your help,

/ magnus


From christoffer.dall at linaro.org  Wed May 29 21:39:26 2013
From: christoffer.dall at linaro.org (Christoffer Dall)
Date: Wed, 29 May 2013 18:39:26 -0700
Subject: [GIT PULL] KVM/ARM Fixes for 3.10
Message-ID: <CAMJs5B8qTMpaaq0y=xGUrTzUd_-LvmARdGABV8PdpqmWUkPoqw@mail.gmail.com>

The following changes since commit e47a5f5fb715b90b40747e9e235de557c6abd56c:

  KVM: x86 emulator: convert XADD to fastop (2013-05-21 15:43:24 +0300)

are available in the git repository at:

  git://github.com/columbia/linux-kvm-arm.git kvm-arm-fixes-3.10

for you to fetch changes up to f3afcd8bf501e98e7707865930338e5a82d8ed88:

  ARM: KVM: be more thorough when invalidating TLBs (2013-05-27 19:34:20 -0700)

----------------------------------------------------------------
Andre Przywara (1):
      ARM: KVM: prevent NULL pointer dereferences with KVM VCPU ioctl

Marc Zyngier (1):
      ARM: KVM: be more thorough when invalidating TLBs

 arch/arm/kvm/arm.c |   15 +++++++++++++--
 arch/arm/kvm/mmu.c |   41 ++++++++++++++++++++++++++---------------
 2 files changed, 39 insertions(+), 17 deletions(-)


From Yalin.Wang at sonymobile.com  Wed May 29 21:41:42 2013
From: Yalin.Wang at sonymobile.com (Wang, Yalin)
Date: Thu, 30 May 2013 09:41:42 +0800
Subject: A bug about system call on ARM
In-Reply-To: <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
Message-ID: <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>

Hi  Will,

Have you received the log files?

And is there someone looking at this issue now ?
This issue happened on Qcom Scorpoin CPUs,
And  it just happened in our stability test occasionally .

If you have some patch for this issue,
I can do the test for it .

Thanks for your help very much !

-----Original Message-----
From: Wang, Yalin 
Sent: Wednesday, May 29, 2013 5:51 PM
To: 'Will Deacon'; richard -rw- weinberger
Cc: linux-arch at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: RE: A bug about system call on ARM

Hi 

This is kernel.log  and  the stack which is recovered by Trace32 tools.
Please have a look at it .

Thanks 

-----Original Message-----
From: Will Deacon [mailto:will.deacon at arm.com]
Sent: Wednesday, May 29, 2013 5:48 PM
To: richard -rw- weinberger
Cc: Wang, Yalin; linux-arch at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: Re: A bug about system call on ARM

Hello,

On Wed, May 29, 2013 at 09:46:42AM +0100, richard -rw- weinberger wrote:
> On Wed, May 29, 2013 at 10:24 AM, Wang, Yalin <Yalin.Wang at sonymobile.com> wrote:
> > I have download the latest linux kernel code  3.9.4 And Compare with
> > 3.4.0 kernel .
> >
> > It seems there is no change for this part , So it will still happen 
> > .
> > Does anyone know who is responsible for  arm arch part kernel code ?
> 
> See MAINTAINERS file.
> CC'ing linux-arm-kernel at lists.infradead.org

Cheers for adding us to CC.

> >> #ifdef CONFIG_ARM_THUMB
> >>         tst     r8, #PSR_T_BIT
> >>         movne   r10, #0                         @ no thumb OABI emulation
> >>         ldreq   r10, [lr, #-4]                  @ get SWI instruction          // crash at this instruction, when get SWI instruction

Do you have the panic log please? Also, which SoC are you using and how are you reproducing this?

> >>         ldr     r10, [lr, #-4]                  @ get SWI instruction
> >>   A710( and     ip, r10, #0x0f000000            @ check for SWI         )
> >>   A710( teq     ip, #0x0f000000                                         )
> >>   A710( bne     .Larm710bug                                             )
> >> #endif
> >> #ifdef CONFIG_CPU_ENDIAN_BE8
> >>         rev     r10, r10                        @ little endian instruction
> >> #endif
> >>
> >> /******************************************************************
> >> ***
> >> ******************************/
> >>
> >> Then reason why it will crash when get SWI instruction is maybe 
> >> This page is clear to aged by kernel, But this MMU fault happpened 
> >> in kernel, So the kernel do_page_fault function will not clear this 
> >> page to young, So that  will crash .

Sounds like we might need some USER annotations around the instruction loads, but we should also rework the code so that we re-enable interrupts first.

Will


From skannan at codeaurora.org  Wed May 29 21:46:37 2013
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 29 May 2013 18:46:37 -0700
Subject: [PATCH v2 1/2] clk: Disable unused clocks after deferred probing
 is done
In-Reply-To: <20130529075126.6058.58923@quantum>
References: <1368124502-18830-1-git-send-email-skannan@codeaurora.org>
 <519461BB.3010209@codeaurora.org> <20130529075126.6058.58923@quantum>
Message-ID: <51A6AF7D.8080706@codeaurora.org>

On 05/29/2013 12:51 AM, Mike Turquette wrote:
> Quoting Saravana Kannan (2013-05-15 21:34:03)
>> On 05/09/2013 11:35 AM, Saravana Kannan wrote:
>>> With deferred probing, late_initcall() is too soon to declare a clock as
>>> unused. Wait for deferred probing to finish before declaring a clock as
>>> unused. Since deferred probing is done in late_initcall(), do the unused
>>> check to late_initcall_sync.
>>>
>>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>>> ---
>>>    drivers/clk/clk.c |    2 +-
>>>    1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>>> index fe4055f..5ecb64c 100644
>>> --- a/drivers/clk/clk.c
>>> +++ b/drivers/clk/clk.c
>>> @@ -534,7 +534,7 @@ static int clk_disable_unused(void)
>>>
>>>        return 0;
>>>    }
>>> -late_initcall(clk_disable_unused);
>>> +late_initcall_sync(clk_disable_unused);
>>>
>>>    /***    helper functions   ***/
>>
>> Mike,
>>
>> Thoughts? Picking it up? Removing the existing auto-disable code (I
>> think they are still useful)?
>>
>
> Hi Saravana,
>
> I've taken this into clk-next for testing.
>
> Regards,
> Mike
>

Thanks.

-Saravana
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From shawn.guo at linaro.org  Wed May 29 21:50:08 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 09:50:08 +0800
Subject: [PATCH] SPI: Unify simple platform data for some controllers
In-Reply-To: <1962597.10ArYKg8M9@wuerfel>
References: <1369809742-4220-1-git-send-email-shc_work@mail.ru>
 <20130529144909.GT3660@sirena.org.uk>
 <1369847158.250798748@f433.i.mail.ru> <1962597.10ArYKg8M9@wuerfel>
Message-ID: <20130530015006.GA1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 08:10:05PM +0200, Arnd Bergmann wrote:
> The plan for i.MX is to move to DT-only in the long run, but
> AFAIK a lot of people still rely on board files and they are
> not trivial to convert without access to test hardware.
> 
> Any new i.MX hardware should certainly be DT-only.
> 
> Shawn can probably comment better on the time line.
> 
It's progressing slowly, and I can not really commit a time line because
there are too many board files to be converted, and more importantly
I haven't seen too much effort from board owners on this work.

Shawn



From B35083 at freescale.com  Wed May 29 21:50:09 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Thu, 30 May 2013 01:50:09 +0000
Subject: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts support
In-Reply-To: <20130529111605.GA25053@S2101-09.ap.freescale.net>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
 <1369732343-2982-5-git-send-email-b35083@freescale.com>
 <20130529111605.GA25053@S2101-09.ap.freescale.net>
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CE0C8@039-SN1MPN1-003.039d.mgd.msft.net>



>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo at linaro.org]
>Sent: Wednesday, May 29, 2013 7:16 PM
>To: Lu Jingchang-B35083
>Cc: linux-arm-kernel at lists.infradead.org; s.hauer at pengutronix.de
>Subject: Re: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts
>support
>
>On Tue, May 28, 2013 at 05:12:23PM +0800, Jingchang Lu wrote:
>> +&fec0 {
>> +	phy-mode = "rmii";
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_fec0_1>;
>> +	status = "okay";
>> +};
>
>I'm wondering if fec works fine on your side.  The kernel seems to halt on
>the repeated phy messages below here when I boot the kernel with NFS.
>
>Shawn
>
>fec 400d0000.ethernet eth0: Freescale FEC PHY driver [Generic PHY]
>(mii_bus:phy_addr=400d0000.etherne:00, irq=-1)
>IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready fec 400d1000.ethernet
>eth1: Freescale FEC PHY driver [Generic PHY]
>(mii_bus:phy_addr=400d0000.etherne:01, irq=-1)
>IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>libphy: 400d0000.etherne:01 - Link is Up - 100/Full
>IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready Sending DHCP
>requests ., OK
>IP-Config: Got DHCP answer from 192.168.1.1, my address is 192.168.1.102
>IP-Config: Complete:
>     device=eth0, hwaddr=00:04:9f:02:19:38, ipaddr=192.168.1.102,
>mask=255.255.255.0, gw=192.168.1.1
>     host=192.168.1.102, domain=domain, nis-domain=(none)
>     bootserver=0.0.0.0, rootserver=192.168.1.100, rootpath=, mtu=576
>     nameserver0=61.177.7.1, nameserver1=221.228.255.1 ALSA device list:
>  No soundcards found.
>libphy: 400d0000.etherne:00 - Link is Up - 100/Half
>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>libphy: 400d0000.etherne:00 - Link is Up - 100/Half
>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>libphy: 400d0000.etherne:00 - Link is Up - 100/Half
>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>libphy: 400d0000.etherne:00 - Link is Up - 100/Half ...
[Lu Jingchang-B35083] 
  Are you using kernel version of next-20130529? With the same .config, it seems boot crash with IPv6 enabled after I update to the git tree, but not on next-20130528 and before. Disable IPv6 option makes NFS boot successfully on my board. By the way, the failed message on my side is not the same as above. Thanks!




From shawn.guo at linaro.org  Wed May 29 22:05:25 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 10:05:25 +0800
Subject: [RFC 1/3] SPI: imx: Convert to devm_* API
In-Reply-To: <1369847430-10799-1-git-send-email-shc_work@mail.ru>
References: <20130529144909.GT3660@sirena.org.uk>
 <1369847430-10799-1-git-send-email-shc_work@mail.ru>
Message-ID: <20130530020524.GB1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 09:10:28PM +0400, Alexander Shiyan wrote:
> Use devm_* functions for the driver.
> This ensures more consistent error values and simplifies error paths.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  drivers/spi/spi-imx.c | 79 ++++++++++++++-------------------------------------
>  1 file changed, 21 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index 0befeeb..1cd4473 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -85,7 +85,6 @@ struct spi_imx_data {
>  
>  	struct completion xfer_done;
>  	void __iomem *base;
> -	int irq;
>  	struct clk *clk_per;
>  	struct clk *clk_ipg;
>  	unsigned long spi_clk;
> @@ -761,7 +760,7 @@ static int spi_imx_probe(struct platform_device *pdev)
>  	struct spi_imx_data *spi_imx;
>  	struct resource *res;
>  	struct pinctrl *pinctrl;
> -	int i, ret, num_cs;
> +	int i, irq, ret, num_cs;
>  
>  	if (!np && !mxc_platform_info) {
>  		dev_err(&pdev->dev, "can't get the platform data\n");
> @@ -798,7 +797,8 @@ static int spi_imx_probe(struct platform_device *pdev)
>  		if (!gpio_is_valid(cs_gpio))
>  			continue;
>  
> -		ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
> +		ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
> +					DRIVER_NAME);
>  		if (ret) {
>  			dev_err(&pdev->dev, "can't get cs gpios\n");
>  			goto out_gpio_free;
> @@ -818,52 +818,41 @@ static int spi_imx_probe(struct platform_device *pdev)
>  		(struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	if (!res) {
> -		dev_err(&pdev->dev, "can't get platform resource\n");
> -		ret = -ENOMEM;
> +	spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spi_imx->base)) {
> +		ret = PTR_ERR(spi_imx->base);
>  		goto out_gpio_free;
>  	}
>  
> -	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
> -		dev_err(&pdev->dev, "request_mem_region failed\n");
> -		ret = -EBUSY;
> -		goto out_gpio_free;
> -	}
> -
> -	spi_imx->base = ioremap(res->start, resource_size(res));
> -	if (!spi_imx->base) {
> -		ret = -EINVAL;
> -		goto out_release_mem;
> -	}
> -
> -	spi_imx->irq = platform_get_irq(pdev, 0);
> -	if (spi_imx->irq < 0) {
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
>  		ret = -EINVAL;
> -		goto out_iounmap;
> +		goto out_gpio_free;
>  	}
>  
> -	ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
> +	ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, DRIVER_NAME,
> +			       spi_imx);
>  	if (ret) {
> -		dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
> -		goto out_iounmap;
> +		dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
> +		goto out_gpio_free;
>  	}
>  
>  	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
>  	if (IS_ERR(pinctrl)) {
>  		ret = PTR_ERR(pinctrl);
> -		goto out_free_irq;
> +		goto out_gpio_free;
>  	}
>  
>  	spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
>  	if (IS_ERR(spi_imx->clk_ipg)) {
>  		ret = PTR_ERR(spi_imx->clk_ipg);
> -		goto out_free_irq;
> +		goto out_gpio_free;
>  	}
>  
>  	spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
>  	if (IS_ERR(spi_imx->clk_per)) {
>  		ret = PTR_ERR(spi_imx->clk_per);
> -		goto out_free_irq;
> +		goto out_gpio_free;
>  	}
>  
>  	clk_prepare_enable(spi_imx->clk_per);
> @@ -877,60 +866,34 @@ static int spi_imx_probe(struct platform_device *pdev)
>  
>  	master->dev.of_node = pdev->dev.of_node;
>  	ret = spi_bitbang_start(&spi_imx->bitbang);

---8<-----
> -	if (ret) {
> -		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
> -		goto out_clk_put;
> -	}
> -
> -	dev_info(&pdev->dev, "probed\n");
> +	if (!ret)
> +		return 0;
>  
> -	return ret;
> +	dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
>  
> -out_clk_put:
--->8------

I do not understand why above changes are necessary.

>  	clk_disable_unprepare(spi_imx->clk_per);
>  	clk_disable_unprepare(spi_imx->clk_ipg);
> -out_free_irq:
> -	free_irq(spi_imx->irq, spi_imx);
> -out_iounmap:
> -	iounmap(spi_imx->base);
> -out_release_mem:
> -	release_mem_region(res->start, resource_size(res));
> +
>  out_gpio_free:
> -	while (--i >= 0) {
> -		if (gpio_is_valid(spi_imx->chipselect[i]))
> -			gpio_free(spi_imx->chipselect[i]);
> -	}

With the change, label out_gpio_free becomes improper, and we should
probably rename it.

Shawn

>  	spi_master_put(master);
>  	kfree(master);
> -	platform_set_drvdata(pdev, NULL);
> +
>  	return ret;
>  }
>  
>  static int spi_imx_remove(struct platform_device *pdev)
>  {
>  	struct spi_master *master = platform_get_drvdata(pdev);
> -	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
> -	int i;
>  
>  	spi_bitbang_stop(&spi_imx->bitbang);
>  
>  	writel(0, spi_imx->base + MXC_CSPICTRL);
>  	clk_disable_unprepare(spi_imx->clk_per);
>  	clk_disable_unprepare(spi_imx->clk_ipg);
> -	free_irq(spi_imx->irq, spi_imx);
> -	iounmap(spi_imx->base);
> -
> -	for (i = 0; i < master->num_chipselect; i++)
> -		if (gpio_is_valid(spi_imx->chipselect[i]))
> -			gpio_free(spi_imx->chipselect[i]);
>  
>  	spi_master_put(master);
>  
> -	release_mem_region(res->start, resource_size(res));
> -
> -	platform_set_drvdata(pdev, NULL);
> -
>  	return 0;
>  }
>  
> -- 
> 1.8.1.5
> 



From shawn.guo at linaro.org  Wed May 29 22:42:41 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 10:42:41 +0800
Subject: [RFC 2/3] SPI: imx: Using SPI-master "cs_gpios" field for array
 of chipselects instead of private
In-Reply-To: <1369847430-10799-2-git-send-email-shc_work@mail.ru>
References: <20130529144909.GT3660@sirena.org.uk>
 <1369847430-10799-1-git-send-email-shc_work@mail.ru>
 <1369847430-10799-2-git-send-email-shc_work@mail.ru>
Message-ID: <20130530024240.GC1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 09:10:29PM +0400, Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> ---
>  drivers/spi/spi-imx.c | 49 +++++++++++++++++++++++++++----------------------
>  1 file changed, 27 insertions(+), 22 deletions(-)



From shawn.guo at linaro.org  Wed May 29 23:22:48 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 11:22:48 +0800
Subject: [RFC 2/3] SPI: imx: Using SPI-master "cs_gpios" field for array
 of chipselects instead of private
In-Reply-To: <1369847430-10799-2-git-send-email-shc_work@mail.ru>
References: <20130529144909.GT3660@sirena.org.uk>
 <1369847430-10799-1-git-send-email-shc_work@mail.ru>
 <1369847430-10799-2-git-send-email-shc_work@mail.ru>
Message-ID: <20130530032246.GD1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 09:10:29PM +0400, Alexander Shiyan wrote:
> @@ -356,11 +356,12 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
>  	writel(reg, spi_imx->base + MXC_CSPICTRL);
>  }
>  
> -static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
> +static int __maybe_unused mx31_config(struct spi_device *spi,
>  		struct spi_imx_config *config)
>  {
> +	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
>  	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
> -	int cs = spi_imx->chipselect[config->cs];
> +	int cs = spi->master->cs_gpios[config->cs];

Hmm, just took another look and found it (and all the following) can be
even simpler like:

	int cs = spi->cs_gpio;

Shawn

>  
>  	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
>  		MX31_CSPICTRL_DR_SHIFT;
> @@ -434,11 +435,12 @@ static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
>  	writel(reg, spi_imx->base + MXC_CSPICTRL);
>  }
>  
> -static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
> +static int __maybe_unused mx21_config(struct spi_device *spi,
>  		struct spi_imx_config *config)
>  {
> +	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
>  	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
> -	int cs = spi_imx->chipselect[config->cs];
> +	int cs = spi->master->cs_gpios[config->cs];
>  	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
>  
>  	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
> @@ -501,9 +503,10 @@ static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
>  	writel(reg, spi_imx->base + MXC_CSPICTRL);
>  }
>  
> -static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
> +static int __maybe_unused mx1_config(struct spi_device *spi,
>  		struct spi_imx_config *config)
>  {
> +	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
>  	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
>  
>  	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
> @@ -622,8 +625,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
>  
>  static void spi_imx_chipselect(struct spi_device *spi, int is_active)
>  {
> -	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
> -	int gpio = spi_imx->chipselect[spi->chip_select];
> +	int gpio = spi->master->cs_gpios[spi->chip_select];
>  	int active = is_active != BITBANG_CS_INACTIVE;
>  	int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
>  
> @@ -703,7 +705,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
>  	} else
>  		BUG();
>  
> -	spi_imx->devtype_data->config(spi_imx, &config);
> +	spi_imx->devtype_data->config(spi, &config);
>  
>  	return 0;
>  }
> @@ -731,8 +733,7 @@ static int spi_imx_transfer(struct spi_device *spi,
>  
>  static int spi_imx_setup(struct spi_device *spi)
>  {
> -	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
> -	int gpio = spi_imx->chipselect[spi->chip_select];
> +	int gpio = spi->master->cs_gpios[spi->chip_select];
>  
>  	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
>  		 spi->mode, spi->bits_per_word, spi->max_speed_hz);



From shawn.guo at linaro.org  Wed May 29 23:36:14 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 11:36:14 +0800
Subject: [RFC 3/3] SPI: imx: Using dynamic count of chipselects provided
 by of_spi_register_master
In-Reply-To: <1369847430-10799-3-git-send-email-shc_work@mail.ru>
References: <20130529144909.GT3660@sirena.org.uk>
 <1369847430-10799-1-git-send-email-shc_work@mail.ru>
 <1369847430-10799-3-git-send-email-shc_work@mail.ru>
Message-ID: <20130530033612.GE1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 09:10:30PM +0400, Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  .../devicetree/bindings/spi/fsl-imx-cspi.txt       |  2 -
>  arch/arm/boot/dts/imx27-apf27dev.dts               |  2 -
>  arch/arm/boot/dts/imx51-apf51dev.dts               |  2 -
>  arch/arm/boot/dts/imx51-babbage.dts                |  1 -
>  arch/arm/boot/dts/imx53-evk.dts                    |  1 -
>  arch/arm/boot/dts/imx53-smd.dts                    |  1 -
>  arch/arm/boot/dts/imx53-tqma53.dtsi                |  2 -
>  arch/arm/boot/dts/imx6q-sabrelite.dts              |  1 -
>  drivers/spi/spi-imx.c                              | 51 ++++++++++------------
>  9 files changed, 22 insertions(+), 41 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
> index 4256a6d..069592d 100644
> --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
> +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
> @@ -5,7 +5,6 @@ Required properties:
>  - compatible : Should be "fsl,<soc>-cspi" or "fsl,<soc>-ecspi"
>  - reg : Offset and length of the register set for the device
>  - interrupts : Should contain CSPI/eCSPI interrupt
> -- fsl,spi-num-chipselects : Contains the number of the chipselect
>  - cs-gpios : Specifies the gpio pins to be used for chipselects.
>  
>  Example:
> @@ -16,7 +15,6 @@ ecspi at 70010000 {
>  	compatible = "fsl,imx51-ecspi";
>  	reg = <0x70010000 0x4000>;
>  	interrupts = <36>;
> -	fsl,spi-num-chipselects = <2>;
>  	cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
>  		   <&gpio3 25 0>; /* GPIO3_25 */
>  };
> diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
> index 66b8e1c..6e71949 100644
> --- a/arch/arm/boot/dts/imx27-apf27dev.dts
> +++ b/arch/arm/boot/dts/imx27-apf27dev.dts
> @@ -38,13 +38,11 @@
>  };
>  
>  &cspi1 {
> -	fsl,spi-num-chipselects = <1>;
>  	cs-gpios = <&gpio4 28 1>;
>  	status = "okay";
>  };
>  
>  &cspi2 {
> -	fsl,spi-num-chipselects = <3>;
>  	cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>,
>  			<&gpio2 17 1>;
>  	status = "okay";
> diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
> index 123fe84..557b616 100644
> --- a/arch/arm/boot/dts/imx51-apf51dev.dts
> +++ b/arch/arm/boot/dts/imx51-apf51dev.dts
> @@ -40,7 +40,6 @@
>  &ecspi1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1_1>;
> -	fsl,spi-num-chipselects = <2>;
>  	cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
>  	status = "okay";
>  };
> @@ -48,7 +47,6 @@
>  &ecspi2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi2_1>;
> -	fsl,spi-num-chipselects = <2>;
>  	cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
> index 6dd9486..0a6c443 100644
> --- a/arch/arm/boot/dts/imx51-babbage.dts
> +++ b/arch/arm/boot/dts/imx51-babbage.dts
> @@ -89,7 +89,6 @@
>  &ecspi1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1_1>;
> -	fsl,spi-num-chipselects = <2>;
>  	cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
> index 801fda7..6a9b1e7 100644
> --- a/arch/arm/boot/dts/imx53-evk.dts
> +++ b/arch/arm/boot/dts/imx53-evk.dts
> @@ -43,7 +43,6 @@
>  &ecspi1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1_1>;
> -	fsl,spi-num-chipselects = <2>;
>  	cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
> index a9b6e10..6d86ae8 100644
> --- a/arch/arm/boot/dts/imx53-smd.dts
> +++ b/arch/arm/boot/dts/imx53-smd.dts
> @@ -63,7 +63,6 @@
>  &ecspi1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1_1>;
> -	fsl,spi-num-chipselects = <2>;
>  	cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
> index 38bed3e..bd5a024 100644
> --- a/arch/arm/boot/dts/imx53-tqma53.dtsi
> +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
> @@ -50,7 +50,6 @@
>  &ecspi1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1_1>;
> -	fsl,spi-num-chipselects = <4>;
>  	cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
>  		   <&gpio3 24 0>, <&gpio3 25 0>;
>  	status = "disabled";
> @@ -133,7 +132,6 @@
>  &cspi {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_cspi_1>;
> -	fsl,spi-num-chipselects = <3>;
>  	cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
>  		   <&gpio1 21 0>;
>  	status = "disabled";
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index 6a00066..a47647d 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -66,7 +66,6 @@
>  };
>  
>  &ecspi1 {
> -	fsl,spi-num-chipselects = <1>;
>  	cs-gpios = <&gpio3 19 0>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1_1>;
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index 3a11b20..5384a42 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -761,53 +761,46 @@ static int spi_imx_probe(struct platform_device *pdev)
>  	struct spi_imx_data *spi_imx;
>  	struct resource *res;
>  	struct pinctrl *pinctrl;
> -	int i, irq, ret, num_cs;
> +	int i, irq, ret;
>  
>  	if (!np && !mxc_platform_info) {
>  		dev_err(&pdev->dev, "can't get the platform data\n");
>  		return -EINVAL;
>  	}
>  
> -	ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
> -	if (ret < 0) {
> -		if (mxc_platform_info)
> -			num_cs = mxc_platform_info->num_chipselect;
> -		else
> -			return ret;
> -	}
> -
>  	master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
>  	if (!master)
>  		return -ENOMEM;
>  
> -	master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) * num_cs,
> -					GFP_KERNEL);
> -	if (!master->cs_gpios) {
> -		ret = -ENOMEM;
> -		goto out_master_free;
> +	if (!np && mxc_platform_info) {
> +		master->num_chipselect = mxc_platform_info->num_chipselect;
> +
> +		master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
> +						master->num_chipselect,
> +						GFP_KERNEL);
> +		if (!master->cs_gpios) {
> +			ret = -ENOMEM;
> +			goto out_master_free;
> +		}
> +
> +		for (i = 0; i < master->num_chipselect; i++) {
> +			master->cs_gpios[i] = mxc_platform_info->chipselect[i];
> +			ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
> +						DRIVER_NAME);
> +			if (ret) {
> +				dev_err(&pdev->dev, "can't get cs gpio %i\n",
> +					master->cs_gpios[i]);
> +				goto out_gpio_free;
> +			}
> +		}
>  	}
>  
>  	platform_set_drvdata(pdev, master);
>  
>  	master->bus_num = pdev->id;
> -	master->num_chipselect = num_cs;
>  
>  	spi_imx = spi_master_get_devdata(master);
>  	spi_imx->bitbang.master = spi_master_get(master);
> -
> -	for (i = 0; i < master->num_chipselect; i++) {
> -		int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
> -		if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
> -			cs_gpio = mxc_platform_info->chipselect[i];
> -
> -		master->cs_gpios[i] = cs_gpio;
> -		ret = devm_gpio_request(&pdev->dev, cs_gpio, DRIVER_NAME);

It seems that of_spi_register_master() does not request gpio, right?

Shawn

> -		if (ret) {
> -			dev_err(&pdev->dev, "can't get cs gpio %i\n", cs_gpio);
> -			goto out_gpio_free;
> -		}
> -	}
> -
>  	spi_imx->bitbang.chipselect = spi_imx_chipselect;
>  	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
>  	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
> -- 
> 1.8.1.5
> 



From tushar.behera at linaro.org  Wed May 29 23:37:30 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu, 30 May 2013 09:07:30 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <CAOesGMiYs6GfaWGWYB8cw_cJ6_RmmZTb4oPfXo1PYJT8-jdHzw@mail.gmail.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 <51A5C16D.20408@linaro.org> <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
 <CAOesGMiYs6GfaWGWYB8cw_cJ6_RmmZTb4oPfXo1PYJT8-jdHzw@mail.gmail.com>
Message-ID: <51A6C97A.6030306@linaro.org>

On 05/30/2013 12:16 AM, Olof Johansson wrote:
> On Wed, May 29, 2013 at 2:33 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> 
>> However, Olof Johansson mentioned, 'drivers/platform/arm/board_arndale.c'
>> would be a good alternative.
> 
> 
> Whoa. I didn't quite realize what I proposed, or rather, how what I
> proposed could be perceived. I take it back. :)
> 
> We must _not_ introduce something that will be abused as a new home
> for board file junk. If we do introduce a platform glue directory it
> would need to be very limited in scope. Compare to what's in
> drivers/platform/x86 today.
> 
> 
> -Olof
> 

This was my proof-of-concept for moving USB hub reset code out of USB
driver. Verified that it works.

I would wait for your patches for wifi-reset sequence and then will add
hub-reset code for Arndale.


-- 
Tushar Behera


From shawn.guo at linaro.org  Thu May 30 00:06:11 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 12:06:11 +0800
Subject: [RFC 1/3] SPI: imx: Convert to devm_* API
In-Reply-To: <1369885838.170762928@f286.mail.ru>
References: <20130529144909.GT3660@sirena.org.uk>
 <1369847430-10799-1-git-send-email-shc_work@mail.ru>
 <20130530020524.GB1875@S2101-09.ap.freescale.net>
 <1369885838.170762928@f286.mail.ru>
Message-ID: <20130530040609.GA2161@S2101-09.ap.freescale.net>

On Thu, May 30, 2013 at 07:50:38AM +0400, Alexander Shiyan wrote:
> > On Wed, May 29, 2013 at 09:10:28PM +0400, Alexander Shiyan wrote:
> > > Use devm_* functions for the driver.
> > > This ensures more consistent error values and simplifies error paths.
> > > 
> > > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> > > ---
> > >  drivers/spi/spi-imx.c | 79 ++++++++++++++-------------------------------------
> > >  1 file changed, 21 insertions(+), 58 deletions(-)
> > > 
> > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> ...
> > >  	master->dev.of_node = pdev->dev.of_node;
> > >  	ret = spi_bitbang_start(&spi_imx->bitbang);
> > 
> > ---8<-----
> > > -	if (ret) {
> > > -		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
> > > -		goto out_clk_put;
> > > -	}
> > > -
> > > -	dev_info(&pdev->dev, "probed\n");
> > > +	if (!ret)
> > > +		return 0;
> > >  
> > > -	return ret;
> > > +	dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
> > >  
> > > -out_clk_put:
> > --->8------
> > 
> > I do not understand why above changes are necessary.
> 
> This just simplifies the error path and removes one "goto".
> 
Sorry, I do not get it and take this as a diff stat churn.

Shawn



From swarren at wwwdotorg.org  Thu May 30 00:07:39 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 22:07:39 -0600
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
Message-ID: <1369886859-22114-1-git-send-email-swarren@wwwdotorg.org>

From: Jongsung Kim <neidhard.kim at lge.com>

Stephen Warren reported the recent commit 78506f2 (add support for
extended FIFO-size of PL011-r1p5) breaks the serial port on the
BCM2835 ARM SoC.

A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
this compatibility issue, this patch overrides the HW UART periphid
register values with the actually compatible UART periphid 0x00241011
(r1p3 or r1p4).

Reported-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Jongsung Kim <neidhard.kim at lge.com>
Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
This is a fix for v3.10-rc*.

 arch/arm/boot/dts/bcm2835.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index f0052dc..1e12aef 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -44,6 +44,7 @@
 			reg = <0x7e201000 0x1000>;
 			interrupts = <2 25>;
 			clock-frequency = <3000000>;
+			arm,primecell-periphid = <0x00241011>;
 		};
 
 		gpio: gpio {
-- 
1.7.10.4



From swarren at wwwdotorg.org  Thu May 30 00:10:11 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 May 2013 22:10:11 -0600
Subject: [PATCH V2 1/2] ARM: bcm2835: add simple framebuffer to device tree
In-Reply-To: <1365043257-29296-1-git-send-email-swarren@wwwdotorg.org>
References: <1365043257-29296-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <51A6D123.10001@wwwdotorg.org>

On 04/03/2013 08:40 PM, Stephen Warren wrote:
> Place a template simple-framebuffer device into the RPi device tree. The
> bootloader is expected to fill in all the parameters at boot time.
> Hence, disable the device by default, so if the bootloader doesn't do
> this, the device isn't activated with invalid parameters.

In the end, I dropped this patch, and decided to just have U-Boot create
this DT node itself from scratch, just like Olof did for the Samsung ARM
Chromebook.

I have however applied patch 2/2, to enable the simplefb driver in
bcm2835_defconfig.


From shawn.guo at linaro.org  Thu May 30 00:17:37 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 12:17:37 +0800
Subject: [PATCH 1/2] ARM: mxs: Print silicon version on boot
In-Reply-To: <1369856663-29314-1-git-send-email-fabio.estevam@freescale.com>
References: <1369856663-29314-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20130530041735.GF1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 04:44:22PM -0300, Fabio Estevam wrote:
> Introduce functions that identify the SoC type (i.MX23 or iMX28)
> and also report the silicon revision.

U-Boot already does that, right?

> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/mach-mxs/mach-mxs.c | 85 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
> 
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index 66fe810..b632323 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -38,6 +38,21 @@
>  #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0		0x2
>  #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1		0x3
>  
> +
> +#define MXS_DIGCTL_BASE_ADDR	0x8001c000

It should be coming from device tree.

> +#define HW_DIGCTL_CHIPID	0x310
> +#define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
> +#define HW_DIGCTL_REV_MASK	0xff
> +#define HW_DIGCTL_CHIPID_MX23	(0x3780 << 16)
> +#define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
> +
> +#define IMX_CHIP_REVISION_1_0	0x10
> +#define IMX_CHIP_REVISION_1_1	0x11
> +#define IMX_CHIP_REVISION_1_2	0x12
> +#define IMX_CHIP_REVISION_1_3	0x13
> +#define IMX_CHIP_REVISION_1_4	0x14
> +#define IMX_CHIP_REV_UNKNOWN	0xff

Maybe we should prefix them with MXS?

> +
>  #define MXS_GPIO_NR(bank, nr)	((bank) * 32 + (nr))
>  
>  #define MXS_SET_ADDR		0x4
> @@ -361,8 +376,78 @@ static void __init cfa10037_init(void)
>  	update_fec_mac_prop(OUI_CRYSTALFONTZ);
>  }
>  
> +static const char *mxs_get_cpu_type(void)
> +{
> +	int reg;

u32

> +	void __iomem *digctl_base = ioremap(MXS_DIGCTL_BASE_ADDR, SZ_8K);
> +
> +	if (!digctl_base)
> +		return "unknown";
> +
> +	reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK;
> +	switch (reg) {
> +	case HW_DIGCTL_CHIPID_MX23:
> +		return "23";
> +	case HW_DIGCTL_CHIPID_MX28:
> +		return "28";
> +	default:
> +		return "unknown";
> +	}
> +}
> +
> +static int mxs_get_cpu_rev(void)
> +{
> +	int reg, rev;
> +	void __iomem *digctl_base = ioremap(MXS_DIGCTL_BASE_ADDR, SZ_8K);
> +
> +	if (!digctl_base)
> +		return -ENOMEM;
> +
> +	reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK;
> +	rev = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_REV_MASK;
> +
> +	switch (reg) {
> +	case HW_DIGCTL_CHIPID_MX23:
> +		switch (rev) {
> +		case 0x0:
> +			return IMX_CHIP_REVISION_1_0;
> +		case 0x1:
> +			return IMX_CHIP_REVISION_1_1;
> +		case 0x2:
> +			return IMX_CHIP_REVISION_1_2;
> +		case 0x3:
> +			return IMX_CHIP_REVISION_1_3;
> +		case 0x4:
> +			return IMX_CHIP_REVISION_1_4;
> +		default:
> +			return IMX_CHIP_REV_UNKNOWN;
> +		}
> +	case HW_DIGCTL_CHIPID_MX28:
> +		switch (rev) {
> +		case 0x1:
> +			return IMX_CHIP_REVISION_1_2;
> +		default:
> +			return IMX_CHIP_REV_UNKNOWN;

So 0x0 will be an unknown revision?

> +		}
> +	default:
> +		return IMX_CHIP_REV_UNKNOWN;
> +	}
> +}
> +
> +static void mxs_print_silicon_rev(const char *cpu, int srev)
> +{
> +	if (srev == IMX_CHIP_REV_UNKNOWN)
> +		pr_info("CPU identified as i.MX%s, unknown revision\n", cpu);
> +	else
> +		pr_info("CPU identified as i.MX%s, silicon rev %d.%d\n",
> +				cpu, (srev >> 4) & 0xf, srev & 0xf);
> +}
> +
>  static void __init mxs_machine_init(void)
>  {
> +

Unnecessary blank line.

Shawn

> +	mxs_print_silicon_rev(mxs_get_cpu_type(), mxs_get_cpu_rev());
> +
>  	if (of_machine_is_compatible("fsl,imx28-evk"))
>  		imx28_evk_init();
>  	else if (of_machine_is_compatible("bluegiga,apx4devkit"))
> -- 
> 1.8.1.2
> 
> 



From shawn.guo at linaro.org  Thu May 30 00:32:51 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 12:32:51 +0800
Subject: [PATCH 2/2] ARM: mxs: Pass the system revision
In-Reply-To: <1369856663-29314-2-git-send-email-fabio.estevam@freescale.com>
References: <1369856663-29314-1-git-send-email-fabio.estevam@freescale.com>
 <1369856663-29314-2-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20130530043249.GG1875@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 04:44:23PM -0300, Fabio Estevam wrote:
> Some mxs userspace tools, such as multimedia plugins and kobs-ng (tool used to 
> burn boot images to NAND) rely on the 'Revision' field reported by 
> '/proc/cpuinfo'.
> 
> Provide a mechanism to pass such information, so that now we can get:
> 
> $ cat /proc/cpuinfo                                             
> processor       : 0                                                             
> model name      : ARM926EJ-S rev 5 (v5l)                                        
> BogoMIPS        : 226.09                                                        
> Features        : swp half fastmult edsp java                                   
> CPU implementer : 0x41                                                          
> CPU architecture: 5TEJ                                                          
> CPU variant     : 0x0                                                           
> CPU part        : 0x926                                                         
> CPU revision    : 5                                                             
>                                                                                 
> Hardware        : Freescale i.MX28 Evaluation Kit                               
> Revision        : 28012                                                         
> Serial          : 0000000000000000                                              

We now have a standard way to report SoC revision to user space.  Check
drivers/base/soc.c and arch/arm/mach-tegra/tegra.c for example.

But I will be fine with populating system_rev for coping with those
user space which are already spread widely if people think it's
useful/helpful.

Shawn

> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/mach-mxs/mach-mxs.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index b632323..032812d 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -29,6 +29,7 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/time.h>
>  #include <asm/system_misc.h>
> +#include <asm/system_info.h>
>  
>  #include "pm.h"
>  
> @@ -443,10 +444,24 @@ static void mxs_print_silicon_rev(const char *cpu, int srev)
>  				cpu, (srev >> 4) & 0xf, srev & 0xf);
>  }
>  
> +static void mxs_pass_sysrev(void)
> +{
> +	int cputype = 0;
> +
> +	if (strcmp(mxs_get_cpu_type(), "MX23"))
> +		cputype = 0x23000;
> +
> +	if (strcmp(mxs_get_cpu_type(), "MX28"))
> +		cputype = 0x28000;
> +
> +	system_rev = (cputype | mxs_get_cpu_rev());
> +}
> +
>  static void __init mxs_machine_init(void)
>  {
>  
>  	mxs_print_silicon_rev(mxs_get_cpu_type(), mxs_get_cpu_rev());
> +	mxs_pass_sysrev();
>  
>  	if (of_machine_is_compatible("fsl,imx28-evk"))
>  		imx28_evk_init();
> -- 
> 1.8.1.2
> 
> 



From weiyj.lk at gmail.com  Thu May 30 00:32:45 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Thu, 30 May 2013 12:32:45 +0800
Subject: [PATCH -next v2] dmaengine: ste_dma40: fix error return code in
 d40_probe()
Message-ID: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

In many of the error handling case, the return value 'ret' not set
and 0 will be return from d40_probe() even if error, but we should
return a negative error code instead in those error handling case.
This patch fixed them, and also removed useless variable 'err'.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
v1 -> v2: rebased on linux-next.git
---
 drivers/dma/ste_dma40.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 7f23d45..a241e25 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3506,7 +3506,6 @@ static int __init d40_probe(struct platform_device *pdev)
 {
 	struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
 	struct device_node *np = pdev->dev.of_node;
-	int err;
 	int ret = -ENOENT;
 	struct d40_base *base = NULL;
 	struct resource *res = NULL;
@@ -3619,6 +3618,7 @@ static int __init d40_probe(struct platform_device *pdev)
 		if (IS_ERR(base->lcpa_regulator)) {
 			d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
 			base->lcpa_regulator = NULL;
+			ret = PTR_ERR(base->lcpa_regulator);
 			goto failure;
 		}
 
@@ -3633,13 +3633,13 @@ static int __init d40_probe(struct platform_device *pdev)
 	}
 
 	base->initialized = true;
-	err = d40_dmaengine_init(base, num_reserved_chans);
-	if (err)
+	ret = d40_dmaengine_init(base, num_reserved_chans);
+	if (ret)
 		goto failure;
 
 	base->dev->dma_parms = &base->dma_parms;
-	err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
-	if (err) {
+	ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
+	if (ret) {
 		d40_err(&pdev->dev, "Failed to set dma max seg size\n");
 		goto failure;
 	}
@@ -3647,8 +3647,8 @@ static int __init d40_probe(struct platform_device *pdev)
 	d40_hw_init(base);
 
 	if (np) {
-		err = of_dma_controller_register(np, d40_xlate, NULL);
-		if (err && err != -ENODEV)
+		ret = of_dma_controller_register(np, d40_xlate, NULL);
+		if (ret && ret != -ENODEV)
 			dev_err(&pdev->dev,
 				"could not register of_dma_controller\n");
 	}



From olof at lixom.net  Thu May 30 00:39:04 2013
From: olof at lixom.net (Olof Johansson)
Date: Wed, 29 May 2013 21:39:04 -0700
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <Pine.LNX.4.64.1305290819190.14157@axis700.grange>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
 <20130522143204.GE32012@verge.net.au>
 <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
 <20130528024540.GC13532@quad.lixom.net>
 <Pine.LNX.4.64.1305290819190.14157@axis700.grange>
Message-ID: <CAOesGMjLiNTR7cqjSmyy2Ux1srgkC5cPO+D8UsRcgHbW8GQ26Q@mail.gmail.com>

On Tue, May 28, 2013 at 11:26 PM, Guennadi Liakhovetski
<g.liakhovetski at gmx.de> wrote:
> Hi Olof
>
> On Mon, 27 May 2013, Olof Johansson wrote:
>
>> Hi,
>>
>> Sorry, a bit behind on email and just discovered this.
>>
>> On Wed, May 22, 2013 at 07:22:59PM +0200, Guennadi Liakhovetski wrote:
>>
>> > > > The above didn't work in my tests without this:
>> > > >
>> > > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
>> > > > b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
>> > > > index f603c69..4fb0102 100644
>> > > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
>> > > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
>> > > > @@ -33,8 +33,10 @@
>> > > >         };
>> > > >
>> > > >         lbsc {
>> > > > +               compatible = "simple-bus";
>> > > >                 #address-cells = <1>;
>> > > >                 #size-cells = <1>;
>> > > > +               ranges = <0 0 0 0x80000000>;
>> > > >
>> > > >                 ethernet at 8000000 {
>> > > >                         compatible = "smsc,lan9118", "smsc,lan9115";
>> > > >
>> > >
>> > > Could you please post this as a formal patch and indicate
>> > > if you would like it included as a fix in v3.10 or not?
>> >
>> > Can do that, sure, just thought maybe it would be better to fix the
>> > original patch. Besides, I wasn't sure what the correct values for
>> > "ranges" are, I just picked up something, that would be sufficient for
>> > ethernet. But if more devices are added to it in the future, maybe
>> > different ranges values would be needed. I think actually, lbsc should map
>> > the 3 BSC areas, so, the correct property would be
>> >
>> > +           ranges = <0 0 0 0x14000000>;
>> >
>> > > Also, I am curious to know what your tests are.
>> >
>> > Just booting with NFS root. I think, anything involving ethernet. Without
>> > the "simple-bus" property the lbsc node doesn't get scanned, so, no device
>> > is added. Without "ranges" addresses cannot be mapped correctly.
>>
>> Since it's a flat mapping you can just specify an empty "ranges" property, no
>> need to actually define contents.
>
> Yes, I knew about that, but does this also hold for busses with different
> #address-cells properties, i.e. between 64- and 32-bit busses?

Oh, good question -- I don't think it does. But why go down, you might
as well use 2 cells in that part of the tree too?


-Olof


From tushar.behera at linaro.org  Thu May 30 00:40:27 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu, 30 May 2013 10:10:27 +0530
Subject: [PATCH] ARM: EXYNOS: Consolidate multiple low-level UART port
 definitions
Message-ID: <1369888827-9427-1-git-send-email-tushar.behera@linaro.org>

There are two definitions for low-level UART ports for Exynos platform.
CONFIG_S3C_LOWLEVEL_UART_PORT is used for printing "Uncompressing
Linux... done, booting the kernel." and CONFIG_S3C_UART for other
low-level messages.

The assumption for both the uart ports is that they are pre-configured
in the bootloader. Since they are essentially the same always, it
would be good to consolidate them to use only one macro, in this case
'DEBUG_S3C_UART' would be a better option.

'DEBUG_S3C_UART' is defined only if DEBUG_LL is enabled. We can safely
disable this option when DEBUG_LL is not defined and we can boot various
boards with different UART port settings. Only drawback of this
approach is that when DEBUG_LL is not defined, we would be missing the
print "Uncompressing Linux... done, booting the kernel."

Since CONFIG_S3C_LOWLEVEL_UART_PORT is still used by other Samsung
boards, the consolidation applies only for ARCH_EXYNOS.

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-exynos/include/mach/uncompress.h  |   11 ++++++++---
 arch/arm/plat-samsung/include/plat/uncompress.h |   16 ++++++++++++++--
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 2979995..45b5c2a 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -37,11 +37,16 @@ static void arch_detect_cpu(void)
 	chip_id >>= 20;
 	chip_id &= 0xf;
 
+#ifdef CONFIG_DEBUG_LL
 	if (chip_id == 0x5)
-		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+		uart_base = (volatile u8 *)EXYNOS5_PA_UART +
+			(S3C_UART_OFFSET * CONFIG_DEBUG_S3C_UART);
 	else
-		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-
+		uart_base = (volatile u8 *)EXYNOS4_PA_UART +
+			(S3C_UART_OFFSET * CONFIG_DEBUG_S3C_UART);
+#else
+	uart_base = 0;
+#endif
 	/*
 	 * For preventing FIFO overrun or infinite loop of UART console,
 	 * fifo_max should be the minimum fifo size of all of the UART channels
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 438b248..028c2a8 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -38,7 +38,11 @@ static void arch_detect_cpu(void);
 #define FIFO_MAX	 (14)
 
 #ifdef S3C_PA_UART
-#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
+#ifdef CONFIG_DEBUG_LL
+#define uart_base (S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_DEBUG_S3C_UART))
+#else
+#define uart_base 0
+#endif
 #endif
 
 static __inline__ void
@@ -66,6 +70,9 @@ uart_rd(unsigned int reg)
 
 static void putc(int ch)
 {
+	if (!uart_base)
+		return;
+
 	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
 		int level;
 
@@ -118,7 +125,12 @@ static void arch_decomp_error(const char *x)
 #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
 static inline void arch_enable_uart_fifo(void)
 {
-	u32 fifocon = uart_rd(S3C2410_UFCON);
+	u32 fifocon;
+
+	if (!uart_base)
+		return;
+
+	fifocon = uart_rd(S3C2410_UFCON);
 
 	if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
 		fifocon |= S3C2410_UFCON_RESETBOTH;
-- 
1.7.9.5



From girishks2000 at gmail.com  Thu May 30 01:25:04 2013
From: girishks2000 at gmail.com (Girish KS)
Date: Thu, 30 May 2013 10:55:04 +0530
Subject: [PATCH v1 0/3] Polling support for s3c64xx spi controller
In-Reply-To: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
References: <1369032694-13183-1-git-send-email-ks.giri@samsung.com>
Message-ID: <CAKrE-KcRNRJ-U_qR8UnVa1TJ6dJAF9ZDmuUX5dBOM3XxvOPZZg@mail.gmail.com>

Hello Mark,

Can you please check the performance with this patch set

On Mon, May 20, 2013 at 12:21 PM, Girish K S <girishks2000 at gmail.com> wrote:
> This patch series adds support for the polling mode only. Also 2nd patch
> in the series adds support for dedicated cs pin. After Thomas's patch for
> using default gpio is merged(commit id: 00ab539), one of the patch in this
> series is dropped and new series is generated.
>
> Girish K S (3):
>   spi: s3c64xx: added support for polling mode
>   spi: s3c64xx: Added provision for dedicated cs pin
>   spi: s3c64xx: Added support for exynos5440 spi
>
>  drivers/spi/spi-s3c64xx.c |  197 ++++++++++++++++++++++++++++++++-------------
>  1 files changed, 140 insertions(+), 57 deletions(-)
>
> --
> 1.7.5.4
>


From baruch at tkos.co.il  Thu May 30 01:32:33 2013
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 30 May 2013 08:32:33 +0300
Subject: [RFC PATCH 2/2] clocksource: dw_apb: allow build for
 architectures other than arm
In-Reply-To: <51A51271.2070506@linaro.org>
References: <1369570367-994-2-git-send-email-baruch@tkos.co.il>
 <51A51271.2070506@linaro.org>
Message-ID: <20130530053233.GL25186@sapphire.tkos.co.il>

Hi John,

On Tue, May 28, 2013 at 01:24:17PM -0700, John Stultz wrote:
> On 05/26/2013 05:12 AM, Baruch Siach wrote:
> >ARM is the only architecture providing sched_clock.h and setup_sched_clock().
> >Implement sched_clock() for use by other architectures.
> >
> >Cc: Ingo Molnar <mingo at redhat.com>
> >Cc: Peter Zijlstra <peterz at infradead.org>
> >Cc: John Stultz <john.stultz at linaro.org>
> >Cc: Thomas Gleixner <tglx at linutronix.de>
> >Cc: Jamie Iles <jamie at jamieiles.com>
> >Cc: Dinh Nguyen <dinguyen at altera.com>
> >Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> >---

[snip]

> >@@ -73,6 +77,9 @@ static void add_clocksource(struct device_node 
> >  *source_timer)
> >  }
> >  static void __iomem *sched_io_base;
> >+#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
> >+static u64 sched_clock_mult __read_mostly;
> >+#endif
> >  static u32 read_sched_clock(void)
> >  {
> >@@ -97,7 +104,11 @@ static void init_sched_clock(void)
> >  	timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
> >  	of_node_put(sched_timer);
> >+#ifdef CONFIG_HAVE_SETUP_SCHED_CLOCK
> >  	setup_sched_clock(read_sched_clock, 32, rate);
> >+#else
> >+	sched_clock_mult = NSEC_PER_SEC / rate;
> >+#endif
> >  }
> 
> Can you rework this to not use #ifdefs within the function? They
> make it annoying to read the code.
> 
> Instead maybe have a local setup_sched_clock() function that sets
> the mult value for the !CONFIG_HAVE_SETUP_SCHED_CLOCK case?
> 
> >  static const struct of_device_id osctimer_ids[] __initconst = {
> >@@ -124,3 +135,10 @@ void __init dw_apb_timer_init(void)
> >  	init_sched_clock();
> >  }
> >+
> >+#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
> >+unsigned long long notrace sched_clock()
> >+{
> >+	return read_sched_clock() * sched_clock_mult;
> >+}
> >+#endif
> 
> Also, can you try to condense the number of #ifndef
> CONFIG_HAVE_SETUP_SCHED_CLOCK checks to one, and consolidate the
> needed functions all in that one conditional?

Thanks for your comments. I'll rework the patch and resubmit.

I've just noticed that I have a bigger problem. read_sched_clock() returns 
u32, not u64. This means that in a rate of, say, 100MHz it will wrap around 
after a little more than 40 seconds. Would it make sense to put ARM's 32 bin 
sched_clock extension code (arch/arm/kernel/sched_clock.c) is a common place 
(maybe drivers/clocksource), and use that? There seems to be nothing ARM 
specific in this code, after all.

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From g.liakhovetski at gmx.de  Thu May 30 01:33:49 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 30 May 2013 07:33:49 +0200 (CEST)
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <CAOesGMjLiNTR7cqjSmyy2Ux1srgkC5cPO+D8UsRcgHbW8GQ26Q@mail.gmail.com>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <1364954906-16014-6-git-send-email-horms+renesas@verge.net.au>
 <Pine.LNX.4.64.1305171458550.31481@axis700.grange>
 <20130522143204.GE32012@verge.net.au>
 <Pine.LNX.4.64.1305221911380.12715@axis700.grange>
 <20130528024540.GC13532@quad.lixom.net>
 <Pine.LNX.4.64.1305290819190.14157@axis700.grange>
 <CAOesGMjLiNTR7cqjSmyy2Ux1srgkC5cPO+D8UsRcgHbW8GQ26Q@mail.gmail.com>
Message-ID: <Pine.LNX.4.64.1305300700150.24272@axis700.grange>

On Wed, 29 May 2013, Olof Johansson wrote:

> On Tue, May 28, 2013 at 11:26 PM, Guennadi Liakhovetski
> <g.liakhovetski at gmx.de> wrote:
> > Hi Olof
> >
> > On Mon, 27 May 2013, Olof Johansson wrote:
> >
> >> Hi,
> >>
> >> Sorry, a bit behind on email and just discovered this.
> >>
> >> On Wed, May 22, 2013 at 07:22:59PM +0200, Guennadi Liakhovetski wrote:
> >>
> >> > > > The above didn't work in my tests without this:
> >> > > >
> >> > > > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> >> > > > b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> >> > > > index f603c69..4fb0102 100644
> >> > > > --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> >> > > > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
> >> > > > @@ -33,8 +33,10 @@
> >> > > >         };
> >> > > >
> >> > > >         lbsc {
> >> > > > +               compatible = "simple-bus";
> >> > > >                 #address-cells = <1>;
> >> > > >                 #size-cells = <1>;
> >> > > > +               ranges = <0 0 0 0x80000000>;
> >> > > >
> >> > > >                 ethernet at 8000000 {
> >> > > >                         compatible = "smsc,lan9118", "smsc,lan9115";
> >> > > >
> >> > >
> >> > > Could you please post this as a formal patch and indicate
> >> > > if you would like it included as a fix in v3.10 or not?
> >> >
> >> > Can do that, sure, just thought maybe it would be better to fix the
> >> > original patch. Besides, I wasn't sure what the correct values for
> >> > "ranges" are, I just picked up something, that would be sufficient for
> >> > ethernet. But if more devices are added to it in the future, maybe
> >> > different ranges values would be needed. I think actually, lbsc should map
> >> > the 3 BSC areas, so, the correct property would be
> >> >
> >> > +           ranges = <0 0 0 0x14000000>;
> >> >
> >> > > Also, I am curious to know what your tests are.
> >> >
> >> > Just booting with NFS root. I think, anything involving ethernet. Without
> >> > the "simple-bus" property the lbsc node doesn't get scanned, so, no device
> >> > is added. Without "ranges" addresses cannot be mapped correctly.
> >>
> >> Since it's a flat mapping you can just specify an empty "ranges" property, no
> >> need to actually define contents.
> >
> > Yes, I knew about that, but does this also hold for busses with different
> > #address-cells properties, i.e. between 64- and 32-bit busses?
> 
> Oh, good question -- I don't think it does. But why go down, you might
> as well use 2 cells in that part of the tree too?

Ok, I didn't write the original implementation of that bus and, therefore, 
didn't decide how many address cells it shall use. My task was to fix it. 
And yes, I agree, that there are 2 ways to fix the memory mapping: either 
define ranges to map from 64-bits to 32-bits, or to change all devices on 
the bus (currently there's only 1) to use 64-bit "reg" property and use 
"ranges" with no arguments. Since that bus is clearly within a 32-bit 
area, I would prefer the former solution not to have to drag 64 bits 
around an make device nodes simpler. Can we keep this approach or are you 
strongly against it?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From pbonzini at redhat.com  Thu May 30 01:45:51 2013
From: pbonzini at redhat.com (Paolo Bonzini)
Date: Thu, 30 May 2013 07:45:51 +0200
Subject: [GIT PULL] KVM/ARM Fixes for 3.10
In-Reply-To: <CAMJs5B8qTMpaaq0y=xGUrTzUd_-LvmARdGABV8PdpqmWUkPoqw@mail.gmail.com>
References: <CAMJs5B8qTMpaaq0y=xGUrTzUd_-LvmARdGABV8PdpqmWUkPoqw@mail.gmail.com>
Message-ID: <51A6E78F.3070902@redhat.com>

Il 30/05/2013 03:39, Christoffer Dall ha scritto:
> The following changes since commit e47a5f5fb715b90b40747e9e235de557c6abd56c:
> 
>   KVM: x86 emulator: convert XADD to fastop (2013-05-21 15:43:24 +0300)

Chris,

this is based on the "next" branch, which will not be merged until the
3.11 merge window.  Please base your 3.10 fixes on the "master" branch
of kvm.git.

Thanks!

Paolo

> are available in the git repository at:
> 
>   git://github.com/columbia/linux-kvm-arm.git kvm-arm-fixes-3.10
> 
> for you to fetch changes up to f3afcd8bf501e98e7707865930338e5a82d8ed88:
> 
>   ARM: KVM: be more thorough when invalidating TLBs (2013-05-27 19:34:20 -0700)
> 
> ----------------------------------------------------------------
> Andre Przywara (1):
>       ARM: KVM: prevent NULL pointer dereferences with KVM VCPU ioctl
> 
> Marc Zyngier (1):
>       ARM: KVM: be more thorough when invalidating TLBs
> 
>  arch/arm/kvm/arm.c |   15 +++++++++++++--
>  arch/arm/kvm/mmu.c |   41 ++++++++++++++++++++++++++---------------
>  2 files changed, 39 insertions(+), 17 deletions(-)
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From linux at prisktech.co.nz  Thu May 30 02:09:47 2013
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 30 May 2013 18:09:47 +1200
Subject: [PATCH 4/4] MAINTAINERS: vt8500: Add clk-vt8500.c to MAINTAINERS
 file
In-Reply-To: <20130529231649.6058.4589@quantum>
References: <1368825532-30917-1-git-send-email-linux@prisktech.co.nz>
 <1368825532-30917-5-git-send-email-linux@prisktech.co.nz>
 <CABjd4Yw2LbnaUbQFW_bd_6WRGTA34-Vp_tUC2b4Jczj-MM8x1w@mail.gmail.com>
 <51973C1D.2080404@prisktech.co.nz> <20130529231649.6058.4589@quantum>
Message-ID: <51A6ED2B.1080908@prisktech.co.nz>

On 30/05/13 11:16, Mike Turquette wrote:
> Quoting Tony Prisk (2013-05-18 01:30:21)
>> On 18/05/13 18:40, Alexey Charkov wrote:
>>> On 18 May 2013 01:18, "Tony Prisk" <linux at prisktech.co.nz> wrote:
>>>> This file has missed being added under ARM/VT8500 ARM ARCHITECTURE,
>>>> and is maintained along with the rest of the vt8500 arch code.
>>>>
>>>> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
>>>> ---
>>>>    MAINTAINERS |    1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index 3d7782b..5ab8ccb 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -1283,6 +1283,7 @@ M:        Tony Prisk <linux at prisktech.co.nz>
>>>>    L:     linux-arm-kernel at lists.infradead.org (moderated for
>>> non-subscribers)
>>>>    S:     Maintained
>>>>    F:     arch/arm/mach-vt8500/
>>>> +F:     drivers/clk/vt8500-vt8500.c
>>> This looks like a typo (clk vs. vt8500).
>>>
>>> Best,
>>> Alexey
>>>
>> eeek - oops.
>>
>> Mike,
>>
>> Disregard this patch - I will send a more complete one through arm-soc
>> as there are other files missing as well.
>>
> Hi Tony,
>
> I've taken patch #1 into clk-fixes.  I took patches #2 & #3 into
> clk-next from your previous series posted on May 13, which appear
> identical to the ones in this series.  In the future could you put a
> "v2" in the patch subject since those patches were re-posted?  It would
> have helped me catch it.
>
> I have not taken patch #4.
>
> Does this all sound correct to you?
>
> Thanks,
> Mike
>
>> Regards
>> Tony P
Perfect - Thanks Mike

Regards
Tony P


From josh.wu at atmel.com  Thu May 30 02:14:30 2013
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 30 May 2013 14:14:30 +0800
Subject: [PATCH v2 2/4] mtd: atmel_nand: add Nand Flash Controller (NFC)
 support
In-Reply-To: <20130527102603.GR24476@game.jcrosoft.org>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-3-git-send-email-josh.wu@atmel.com>
 <20130524200947.GM24476@game.jcrosoft.org> <51A32DD2.9040707@atmel.com>
 <20130527102603.GR24476@game.jcrosoft.org>
Message-ID: <51A6EE46.6050701@atmel.com>

Hi, JC

On 5/27/2013 6:26 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:

[snip]

>>> yes but you need to update the compatible or check the IP support it too
>>> as has-nfc will mean I have the nfs on the hardware but not enable it
>>>
>>> the SoC dtsi will describe you have it but the board will decide to enable it or
>>> not
>> I can add some code to check whether is NFC supported by read SMC IP
>> version. But I'm afraid
>> such code may not work for AVR arch.
>>
>> Another way is just add a 'enable-nfc' compatible string. Which is
>> for board to enable the NFC feature.
>>
>> I'm prefer to the later one. What do you think?
> I do not like no 2
>
> I like this
>
> 		nand0: nand at 60000000 {
> 			compatible = "atmel,at91rm9200-nand";
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			reg = < 0x60000000 0x01000000   /* EBI CS3 */
> 				0xffffc070 0x00000490   /* SMC PMECC regs */
> 				0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
> 				0x00100000 0x00100000   /* ROM code */
> 				>;
> 			interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
> 			atmel,nand-addr-offset = <21>;
> 			atmel,nand-cmd-offset = <22>;
> 			pinctrl-names = "default";
> 			pinctrl-0 = <&pinctrl_nand0_ale_cle>;
> 			atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
> 			status = "disabled";
>
> 			nfc at 70000000 {
> 				compatible = "atmel,sama5d3-nfc";
> 				reg = < 0x70000000 0x10000000   /* NFC Command Registers */
> 					0xffffc000 0x00000070   /* NFC HSMC regs */
> 					0x00200000 0x00100000   /* NFC SRAM banks */
> 				>;
> 			}
> 		};
>
> so you can enable/disable it easly

Since I am not use such dts definition before, following is my guest 
implementation for above dts:
So I need define an additional platform driver for "atmel,sama5d3-nfc" 
with probe/remove function. right?
if yes, then there are two question are rise out:
1. which driver will be probed first? or it is depends? Since I think 
the "atmel,sama5d3-nfc" can be probe first is good for me.
2. how do these two drivers share data with others? I check at91 pinctrl 
as a example, and it use a static pointer array store gpio data, and 
pinctrl can access it. Seems that is enough for me.

>
>
>>>>   Examples:
>>>>   nand0: nand at 40000000,0 {
>>>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>>>> index f747791..48d7ee6 100644
>>>> --- a/drivers/mtd/nand/atmel_nand.c
>>>> +++ b/drivers/mtd/nand/atmel_nand.c
>>>> @@ -18,6 +18,9 @@
>>>>    *  Add Programmable Multibit ECC support for various AT91 SoC
>>>>    *     ? Copyright 2012 ATMEL, Hong Xu
>>>>    *
>>>> + *  Add Nand Flash Controller support for SAMA5 SoC
>>>> + *     ? Copyright 2013 ATMEL, Josh Wu (josh.wu at atmel.com)
>>>> + *
>>>>    * This program is free software; you can redistribute it and/or modify
>>>>    * it under the terms of the GNU General Public License version 2 as
>>>>    * published by the Free Software Foundation.
>>>> @@ -37,9 +40,11 @@
>>>>   #include <linux/mtd/nand.h>
>>>>   #include <linux/mtd/partitions.h>
>>>> +#include <linux/delay.h>
>>>>   #include <linux/dmaengine.h>
>>>>   #include <linux/gpio.h>
>>>>   #include <linux/io.h>
>>>> +#include <linux/interrupt.h>
>>>>   #include <linux/platform_data/atmel.h>
>>>>   #include <linux/pinctrl/consumer.h>
>>>> @@ -58,6 +63,7 @@ module_param(on_flash_bbt, int, 0);
>>>>   	__raw_writel((value), add + ATMEL_ECC_##reg)
>>>>   #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
>>>> +#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
>>>>   /* oob layout for large page size
>>>>    * bad block info is on bytes 0 and 1
>>>> @@ -85,6 +91,13 @@ static struct nand_ecclayout atmel_oobinfo_small = {
>>>>   	},
>>>>   };
> ....
>>>> +				dev_err(&pdev->dev,
>>>> +					"can't request input direction rdy gpio %d\n",
>>>> +					host->board.rdy_pin);
>>>> +				goto err_ecc_ioremap;
>>>> +			}
>>>> +
>>>> +			nand_chip->dev_ready = atmel_nand_device_ready;
>>>>   		}
>>>> -		res = gpio_direction_output(host->board.enable_pin, 1);
>>>> -		if (res < 0) {
>>>> -			dev_err(&pdev->dev,
>>>> -				"can't request output direction enable gpio %d\n",
>>>> -				host->board.enable_pin);
>>>> -			goto err_ecc_ioremap;
>>>> +		if (gpio_is_valid(host->board.enable_pin)) {
>>>> +			res = gpio_request(host->board.enable_pin,
>>> we need to use devm_ here too
>>> and everywhere we can in this driver
>> yes, but seems you already sent one patch to use devm_ for this driver.
>> https://patchwork.kernel.org/patch/1589071/
>> It is not merged in at91 tree yet.
>>
>> So what do you think if I put that patch rebased and put it as one
>> of this NFC series patches?
> yes do so

ok. I will rebase the patch and including it with nfc patches.

Best Regards,
Josh Wu

>
> Best Regards,
> J.



From jagarwal at nvidia.com  Thu May 30 02:17:02 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Thu, 30 May 2013 11:47:02 +0530
Subject: [PATCH] Move PCIe node to correct place
In-Reply-To: <5193B622.9020503@wwwdotorg.org>
References: <1368626150-25395-1-git-send-email-jagarwal@nvidia.com>
 <5193B622.9020503@wwwdotorg.org>
Message-ID: <C79B248886DD134989C8FF6B096A91AB91B616BE9E@BGMAIL01.nvidia.com>

> On 05/15/2013 07:55 AM, Jay Agarwal wrote:
> > Moving PCIe controller node to correct place so that it is sorted by
> > register address in .dtsi file
> 
> Reviewed-by: Stephen Warren <swarren at nvidia.com>
Hi Thierry,
If reviews are done, Can you please include this into your repository?



From shawn.guo at linaro.org  Thu May 30 02:25:29 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 14:25:29 +0800
Subject: [PATCH 1/2] ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
In-Reply-To: <1369861609-30408-2-git-send-email-c.hemp@phytec.de>
References: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
 <1369861609-30408-2-git-send-email-c.hemp@phytec.de>
Message-ID: <20130530062526.GA2602@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 11:06:48PM +0200, Christian Hemp wrote:
> Add a group to the usdhc2 and enet pinctrl.
> 
> Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..c0c8b7b 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -157,6 +157,28 @@
>  							MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>  						>;
>  					};
> +
> +					pinctrl_enet_3: enetgrp-3 {
> +						fsl,pins = <
> +							MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
> +							MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
> +							MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
> +							MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
> +							MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
> +							MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
> +							MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
> +							MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> +							MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
> +							MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
> +							MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
> +							MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
> +							MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
> +							MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
> +							MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> +							MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1b0b0

Why do you need to set up SPDIF_EXT_CLK in ENET pin group?

Shawn

> +							MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
> +						>;
> +					};
>  				};
>  
>  				gpmi-nand {
> @@ -266,6 +288,17 @@
>  							MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
>  						>;
>  					};
> +
> +					pinctrl_usdhc2_2: usdhc2grp-2 {
> +						fsl,pins = <
> +							MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
> +							MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
> +							MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
> +							MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
> +							MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
> +							MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
> +						>;
> +					};
>  				};
>  
>  				usdhc3 {
> -- 
> 1.7.9.5
> 



From b32955 at freescale.com  Thu May 30 02:07:12 2013
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 30 May 2013 14:07:12 +0800
Subject: [PATCH] serail: imx: add support for DTE mode
Message-ID: <1369894032-7811-1-git-send-email-b32955@freescale.com>

The uart works in the DCE mode by default, but sometime we need it
works at the DTE mode.

This patch adds the support for the DTE mode.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 .../bindings/tty/serial/fsl-imx-uart.txt           |    3 +++
 drivers/tty/serial/imx.c                           |    6 ++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
index b462d0c..c662eb3 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
@@ -8,6 +8,8 @@ Required properties:
 Optional properties:
 - fsl,uart-has-rtscts : Indicate the uart has rts and cts
 - fsl,irda-mode : Indicate the uart supports irda mode
+- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
+                  is DCE mode by default.
 
 Example:
 
@@ -16,4 +18,5 @@ serial at 73fbc000 {
 	reg = <0x73fbc000 0x4000>;
 	interrupts = <31>;
 	fsl,uart-has-rtscts;
+	fsl,dte-mode;
 };
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 72bc1db..381a2d7 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -201,6 +201,7 @@ struct imx_port {
 	unsigned int		old_status;
 	int			txirq, rxirq, rtsirq;
 	unsigned int		have_rtscts:1;
+	unsigned int		dte_mode:1;
 	unsigned int		use_irda:1;
 	unsigned int		irda_inv_rx:1;
 	unsigned int		irda_inv_tx:1;
@@ -1020,6 +1021,8 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	ufcr = readl(sport->port.membase + UFCR);
 	ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
+	if (sport->dte_mode)
+		ufcr |= UFCR_DCEDTE;
 	writel(ufcr, sport->port.membase + UFCR);
 
 	writel(num, sport->port.membase + UBIR);
@@ -1444,6 +1447,9 @@ static int serial_imx_probe_dt(struct imx_port *sport,
 	if (of_get_property(np, "fsl,irda-mode", NULL))
 		sport->use_irda = 1;
 
+	if (of_get_property(np, "fsl,dte-mode", NULL))
+		sport->dte_mode = 1;
+
 	sport->devdata = of_id->data;
 
 	return 0;
-- 
1.7.1




From shawn.guo at linaro.org  Thu May 30 02:31:26 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 14:31:26 +0800
Subject: [PATCH 2/2] ARM: dts: Phytec phyFLEX-i.MX6 support
In-Reply-To: <1369861609-30408-3-git-send-email-c.hemp@phytec.de>
References: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
 <1369861609-30408-3-git-send-email-c.hemp@phytec.de>
Message-ID: <20130530063124.GB2602@S2101-09.ap.freescale.net>

On Wed, May 29, 2013 at 11:06:49PM +0200, Christian Hemp wrote:
> Add support for Phytec phyFLEX-i.MX6 board

It's a board supporting all i.MX6 family?  Can we name it using SoC than
family name?

> 
> Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> ---
>  arch/arm/boot/dts/Makefile                 |    1 +
>  arch/arm/boot/dts/imx6q-phytec-phyflex.dts |   76 ++++++++++++++++++++++++++++
>  2 files changed, 77 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx6q-phytec-phyflex.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4c58951..6ffdaa1 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
>  	imx6dl-sabresd.dtb \
>  	imx6dl-wandboard.dtb \
>  	imx6q-arm2.dtb \
> +	imx6q-phytec-phyflex.dtb \
>  	imx6q-sabreauto.dtb \
>  	imx6q-sabrelite.dtb \
>  	imx6q-sabresd.dtb \
> diff --git a/arch/arm/boot/dts/imx6q-phytec-phyflex.dts b/arch/arm/boot/dts/imx6q-phytec-phyflex.dts
> new file mode 100644
> index 0000000..9690691
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-phytec-phyflex.dts
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include "imx6q.dtsi"
> +
> +/ {
> +	model = "Phytec phyFLEX-i.MX6";
> +	compatible = "phytec,phyflex-imx6", "fsl,imx6q";

ditto

Shawn

> +
> +	memory {
> +		reg = <0x10000000 0x80000000>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	hog {
> +                pinctrl_hog: hoggrp {
> +                        fsl,pins = <
> +				MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
> +			>;
> +		};
> +	};
> +
> +	phyflex {
> +		pinctrl_usdhc3_phyflex: usdhc3grp-phyflex {
> +			fsl,pins = <
> +				MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
> +				MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
> +			>;
> +		};
> +	};
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet_3>;
> +	phy-mode = "rgmii";
> +	phy-reset-gpios = <&gpio3 23 0>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart4_1>;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc2_2>;
> +	cd-gpios = <&gpio1 4 0>;
> +	wp-gpios = <&gpio1 2 0>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +        pinctrl-names = "default";
> +        pinctrl-0 = <&pinctrl_usdhc3_2
> +		     &pinctrl_usdhc3_phyflex>;
> +        cd-gpios = <&gpio1 27 0>;
> +        wp-gpios = <&gpio1 29 0>;
> +        status = "okay";
> +};
> +
> -- 
> 1.7.9.5
> 



From b35083 at freescale.com  Thu May 30 01:53:37 2013
From: b35083 at freescale.com (Jingchang Lu)
Date: Thu, 30 May 2013 13:53:37 +0800
Subject: [PATCH v5] tty: serial: add Freescale lpuart driver support
Message-ID: <1369893217-27809-1-git-send-email-b35083@freescale.com>

Add Freescale lpuart driver support. The lpuart device
can be found on Vybrid VF610 and Layerscape LS-1 SoCs.

Signed-off-by: Jingchang Lu <b35083 at freescale.com>
---
changes in v5:
 Coding style fix, remove redundant code.
 Checking clk_prepare_enable return value.
 Using devm_ioremap_resource instead of devm_request_and_ioremap.

changes in v4:
 Change Vybrid VF610 SoC compatible string to "fsl,vf610-lpuart"

changes in v3:
 Use general driver name lpuart instead of mvf for further share between SoCs.
 Add bind doc in Documentation/devicetree/bindings/tty/serial.
 Remove unused #include header lines and clean up code.

changes in v2:
 Remove unused variables and clean up the code.

 .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
 drivers/tty/serial/Kconfig                         |  14 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/fsl_lpuart.c                    | 873 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 5 files changed, 905 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
 create mode 100644 drivers/tty/serial/fsl_lpuart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
new file mode 100644
index 0000000..6fd1dd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
@@ -0,0 +1,14 @@
+* Freescale low power universal asynchronous receiver/transmitter (lpuart)
+
+Required properties:
+- compatible : Should be "fsl,<soc>-lpuart"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain uart interrupt
+
+Example:
+
+uart0: serial at 40027000 {
+	       compatible = "fsl,vf610-lpuart";
+	       reg = <0x40027000 0x1000>;
+	       interrupts = <0 61 0x00>;
+       };
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..aee7030 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1484,6 +1484,20 @@ config SERIAL_RP2_NR_UARTS
 	  If multiple cards are present, the default limit of 32 ports may
 	  need to be increased.
 
+config SERIAL_FSL_LPUART
+	bool "Freescale lpuart serial port support"
+	select SERIAL_CORE
+	help
+	  Support for the on-chip lpuart on some Freescale SOCs.
+
+config SERIAL_FSL_LPUART_CONSOLE
+	bool "Console on Freescale lpuart serial port"
+	depends on SERIAL_FSL_LPUART
+	select SERIAL_CORE_CONSOLE
+	help
+	  If you have enabled the lpuart serial port on the Freescale SoCs,
+	  you can make it the console by answering Y to this option.
+
 endmenu
 
 endif # TTY
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index eedfec4..cf650f0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
 obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
 obj-$(CONFIG_SERIAL_ARC)	+= arc_uart.o
 obj-$(CONFIG_SERIAL_RP2)	+= rp2.o
+obj-$(CONFIG_SERIAL_FSL_LPUART)	+= fsl_lpuart.o
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
new file mode 100644
index 0000000..7fb1681
--- /dev/null
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -0,0 +1,873 @@
+/*
+ *  Freescale lpuart serial port driver
+ *
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/of_device.h>
+#include <linux/console.h>
+#include <linux/serial_core.h>
+#include <linux/tty_flip.h>
+
+/* All registers are 8-bit width */
+#define UARTBDH			0x00
+#define UARTBDL			0x01
+#define UARTCR1			0x02
+#define UARTCR2			0x03
+#define UARTSR1			0x04
+#define UARTCR3			0x06
+#define UARTDR			0x07
+#define UARTCR4			0x0a
+#define UARTCR5			0x0b
+#define UARTMODEM		0x0d
+#define UARTPFIFO		0x10
+#define UARTCFIFO		0x11
+#define UARTSFIFO		0x12
+#define UARTTWFIFO		0x13
+#define UARTTCFIFO		0x14
+#define UARTRWFIFO		0x15
+
+#define UARTBDH_LBKDIE		0x80
+#define UARTBDH_RXEDGIE		0x40
+#define UARTBDH_SBR_MASK	0x1f
+
+#define UARTCR1_LOOPS		0x80
+#define UARTCR1_RSRC		0x20
+#define UARTCR1_M		0x10
+#define UARTCR1_WAKE		0x08
+#define UARTCR1_ILT		0x04
+#define UARTCR1_PE		0x02
+#define UARTCR1_PT		0x01
+
+#define UARTCR2_TIE		0x80
+#define UARTCR2_TCIE		0x40
+#define UARTCR2_RIE		0x20
+#define UARTCR2_ILIE		0x10
+#define UARTCR2_TE		0x08
+#define UARTCR2_RE		0x04
+#define UARTCR2_RWU		0x02
+#define UARTCR2_SBK		0x01
+
+#define UARTSR1_TDRE		0x80
+#define UARTSR1_TC		0x40
+#define UARTSR1_RDRF		0x20
+#define UARTSR1_IDLE		0x10
+#define UARTSR1_OR		0x08
+#define UARTSR1_NF		0x04
+#define UARTSR1_FE		0x02
+#define UARTSR1_PE		0x01
+
+#define UARTCR3_R8		0x80
+#define UARTCR3_T8		0x40
+#define UARTCR3_TXDIR		0x20
+#define UARTCR3_TXINV		0x10
+#define UARTCR3_ORIE		0x08
+#define UARTCR3_NEIE		0x04
+#define UARTCR3_FEIE		0x02
+#define UARTCR3_PEIE		0x01
+
+#define UARTCR4_MAEN1		0x80
+#define UARTCR4_MAEN2		0x40
+#define UARTCR4_M10		0x20
+#define UARTCR4_BRFA_MASK	0x1f
+#define UARTCR4_BRFA_OFF	0
+
+#define UARTCR5_TDMAS		0x80
+#define UARTCR5_RDMAS		0x20
+
+#define UARTMODEM_RXRTSE	0x08
+#define UARTMODEM_TXRTSPOL	0x04
+#define UARTMODEM_TXRTSE	0x02
+#define UARTMODEM_TXCTSE	0x01
+
+#define UARTPFIFO_TXFE		0x80
+#define UARTPFIFO_FIFOSIZE_MASK	0x7
+#define UARTPFIFO_TXSIZE_OFF	4
+#define UARTPFIFO_RXFE		0x08
+#define UARTPFIFO_RXSIZE_OFF	0
+
+#define UARTCFIFO_TXFLUSH	0x80
+#define UARTCFIFO_RXFLUSH	0x40
+#define UARTCFIFO_RXOFE		0x04
+#define UARTCFIFO_TXOFE		0x02
+#define UARTCFIFO_RXUFE		0x01
+
+#define UARTSFIFO_TXEMPT	0x80
+#define UARTSFIFO_RXEMPT	0x40
+#define UARTSFIFO_RXOF		0x04
+#define UARTSFIFO_TXOF		0x02
+#define UARTSFIFO_RXUF		0x01
+
+#define DRIVER_NAME	"fsl-lpuart"
+#define DEV_NAME	"ttyLP"
+#define UART_NR		6
+
+struct lpuart_port {
+	struct uart_port	port;
+	struct clk		*clk;
+	unsigned int		txfifo_size;
+	unsigned int		rxfifo_size;
+};
+
+static struct of_device_id lpuart_dt_ids[] = {
+	{
+		.compatible = "fsl,vf610-lpuart",
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
+
+static void lpuart_stop_tx(struct uart_port *port)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTCR2);
+	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
+	writeb(temp, port->membase + UARTCR2);
+}
+
+static void lpuart_stop_rx(struct uart_port *port)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTCR2);
+	writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
+}
+
+static void lpuart_enable_ms(struct uart_port *port)
+{
+}
+
+static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
+{
+	struct circ_buf *xmit = &sport->port.state->xmit;
+
+	while (!uart_circ_empty(xmit) &&
+		(readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
+		writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		sport->port.icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+	if (uart_circ_empty(xmit))
+		lpuart_stop_tx(&sport->port);
+}
+
+static void lpuart_start_tx(struct uart_port *port)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTCR2);
+	writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
+
+	if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
+		lpuart_transmit_buffer(sport);
+}
+
+static irqreturn_t lpuart_txint(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	struct circ_buf *xmit = &sport->port.state->xmit;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+	if (sport->port.x_char) {
+		writeb(sport->port.x_char, sport->port.membase + UARTDR);
+		goto out;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
+		lpuart_stop_tx(&sport->port);
+		goto out;
+	}
+
+	lpuart_transmit_buffer(sport);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&sport->port);
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_rxint(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	unsigned int flg, ignored = 0;
+	struct tty_port *port = &sport->port.state->port;
+	unsigned long flags;
+	unsigned char rx, sr;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
+		flg = TTY_NORMAL;
+		sport->port.icount.rx++;
+		/*
+		 * to clear the FE, OR, NF, FE, PE flags,
+		 * read SR1 then read DR
+		 */
+		sr = readb(sport->port.membase + UARTSR1);
+		rx = readb(sport->port.membase + UARTDR);
+
+		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
+			continue;
+
+		if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
+			if (sr & UARTSR1_PE)
+				sport->port.icount.parity++;
+			else if (sr & UARTSR1_FE)
+				sport->port.icount.frame++;
+
+			if (sr & UARTSR1_OR)
+				sport->port.icount.overrun++;
+
+			if (sr & sport->port.ignore_status_mask) {
+				if (++ignored > 100)
+					goto out;
+				continue;
+			}
+
+			sr &= sport->port.read_status_mask;
+
+			if (sr & UARTSR1_PE)
+				flg = TTY_PARITY;
+			else if (sr & UARTSR1_FE)
+				flg = TTY_FRAME;
+
+			if (sr & UARTSR1_OR)
+				flg = TTY_OVERRUN;
+
+#ifdef SUPPORT_SYSRQ
+			sport->port.sysrq = 0;
+#endif
+		}
+
+		tty_insert_flip_char(port, rx, flg);
+	}
+
+out:
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+
+	tty_flip_buffer_push(port);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_int(int irq, void *dev_id)
+{
+	struct lpuart_port *sport = dev_id;
+	unsigned char sts;
+
+	sts = readb(sport->port.membase + UARTSR1);
+
+	if (sts & UARTSR1_RDRF)
+		lpuart_rxint(irq, dev_id);
+
+	if (sts & UARTSR1_TDRE &&
+		!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
+		lpuart_txint(irq, dev_id);
+
+	return IRQ_HANDLED;
+}
+
+/* return TIOCSER_TEMT when transmitter is not busy */
+static unsigned int lpuart_tx_empty(struct uart_port *port)
+{
+	return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
+		TIOCSER_TEMT : 0;
+}
+
+static unsigned int lpuart_get_mctrl(struct uart_port *port)
+{
+	unsigned int temp = 0;
+	unsigned char reg;
+
+	reg = readb(port->membase + UARTMODEM);
+	if (reg & UARTMODEM_TXCTSE)
+		temp |= TIOCM_CTS;
+
+	if (reg & UARTMODEM_RXRTSE)
+		temp |= TIOCM_RTS;
+
+	return temp;
+}
+
+static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTMODEM) &
+			~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+	if (mctrl & TIOCM_RTS)
+		temp |= UARTMODEM_RXRTSE;
+
+	if (mctrl & TIOCM_CTS)
+		temp |= UARTMODEM_TXCTSE;
+
+	writeb(temp, port->membase + UARTMODEM);
+}
+
+static void lpuart_break_ctl(struct uart_port *port, int break_state)
+{
+	unsigned char temp;
+
+	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
+
+	if (break_state != 0)
+		temp |= UARTCR2_SBK;
+
+	writeb(temp, port->membase + UARTCR2);
+}
+
+static void lpuart_setup_watermark(struct lpuart_port *sport)
+{
+	unsigned char val, cr2;
+
+	cr2 = readb(sport->port.membase + UARTCR2);
+	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
+			UARTCR2_RIE | UARTCR2_RE);
+	writeb(cr2, sport->port.membase + UARTCR2);
+
+	/* determine FIFO size and enable FIFO mode */
+	val = readb(sport->port.membase + UARTPFIFO);
+
+	sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
+		UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
+		UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
+			sport->port.membase + UARTPFIFO);
+
+	/* flush Tx and Rx FIFO */
+	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
+			sport->port.membase + UARTCFIFO);
+
+	writeb(2, sport->port.membase + UARTTWFIFO);
+	writeb(1, sport->port.membase + UARTRWFIFO);
+}
+
+static int lpuart_startup(struct uart_port *port)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	int ret;
+	unsigned long flags;
+	unsigned char temp;
+
+	ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
+				DRIVER_NAME, sport);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	lpuart_setup_watermark(sport);
+
+	temp = readb(sport->port.membase + UARTCR2);
+	temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
+	writeb(temp, sport->port.membase + UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+	return 0;
+}
+
+static void lpuart_shutdown(struct uart_port *port)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned char temp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/* disable Rx/Tx and interrupts */
+	temp = readb(port->membase + UARTCR2);
+	temp &= ~(UARTCR2_TE | UARTCR2_RE |
+			UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+	writeb(temp, port->membase + UARTCR2);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	devm_free_irq(port->dev, port->irq, sport);
+}
+
+static void
+lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
+		   struct ktermios *old)
+{
+	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+	unsigned long flags;
+	unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+	unsigned int  baud;
+	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+	unsigned int sbr, brfa;
+
+	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
+	old_cr2 = readb(sport->port.membase + UARTCR2);
+	cr4 = readb(sport->port.membase + UARTCR4);
+	bdh = readb(sport->port.membase + UARTBDH);
+	modem = readb(sport->port.membase + UARTMODEM);
+	/*
+	 * only support CS8 and CS7, and for CS7 must enable PE.
+	 * supported mode:
+	 *  - (7,e/o,1)
+	 *  - (8,n,1)
+	 *  - (8,m/s,1)
+	 *  - (8,e/o,1)
+	 */
+	while ((termios->c_cflag & CSIZE) != CS8 &&
+		(termios->c_cflag & CSIZE) != CS7) {
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= old_csize;
+		old_csize = CS8;
+	}
+
+	if ((termios->c_cflag & CSIZE) == CS8 ||
+		(termios->c_cflag & CSIZE) == CS7)
+		cr1 = old_cr1 & ~UARTCR1_M;
+
+	if (termios->c_cflag & CMSPAR) {
+		if ((termios->c_cflag & CSIZE) != CS8) {
+			termios->c_cflag &= ~CSIZE;
+			termios->c_cflag |= CS8;
+		}
+		cr1 |= UARTCR1_M;
+	}
+
+	if (termios->c_cflag & CRTSCTS) {
+		modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+	} else {
+		termios->c_cflag &= ~CRTSCTS;
+		modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		termios->c_cflag &= ~CSTOPB;
+
+	/* parity must be enabled when CS7 to match 8-bits format */
+	if ((termios->c_cflag & CSIZE) == CS7)
+		termios->c_cflag |= PARENB;
+
+	if ((termios->c_cflag & PARENB)) {
+		if (termios->c_cflag & CMSPAR) {
+			cr1 &= ~UARTCR1_PE;
+			cr1 |= UARTCR1_M;
+		} else {
+			cr1 |= UARTCR1_PE;
+			if ((termios->c_cflag & CSIZE) == CS8)
+				cr1 |= UARTCR1_M;
+			if (termios->c_cflag & PARODD)
+				cr1 |= UARTCR1_PT;
+			else
+				cr1 &= ~UARTCR1_PT;
+		}
+	}
+
+	/* ask the core to calculate the divisor */
+	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+
+	spin_lock_irqsave(&sport->port.lock, flags);
+
+	sport->port.read_status_mask = 0;
+	if (termios->c_iflag & INPCK)
+		sport->port.read_status_mask |=	(UARTSR1_FE | UARTSR1_PE);
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		sport->port.read_status_mask |= UARTSR1_FE;
+
+	/* characters to ignore */
+	sport->port.ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		sport->port.ignore_status_mask |= UARTSR1_PE;
+	if (termios->c_iflag & IGNBRK) {
+		sport->port.ignore_status_mask |= UARTSR1_FE;
+		/*
+		 * if we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			sport->port.ignore_status_mask |= UARTSR1_OR;
+	}
+
+	/* update the per-port timeout */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/* wait transmit engin complete */
+	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+		barrier();
+
+	/* disable transmit and receive */
+	writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
+			sport->port.membase + UARTCR2);
+
+	sbr = sport->port.uartclk / (16 * baud);
+	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
+	bdh &= ~UARTBDH_SBR_MASK;
+	bdh |= (sbr >> 8) & 0x1F;
+	cr4 &= ~UARTCR4_BRFA_MASK;
+	brfa &= UARTCR4_BRFA_MASK;
+	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
+	writeb(bdh, sport->port.membase + UARTBDH);
+	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
+	writeb(cr1, sport->port.membase + UARTCR1);
+	writeb(modem, sport->port.membase + UARTMODEM);
+
+	/* restore control register */
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
+static const char *lpuart_type(struct uart_port *port)
+{
+	return "FSL_LPUART";
+}
+
+static void lpuart_release_port(struct uart_port *port)
+{
+	/* nothing to do */
+}
+
+static int lpuart_request_port(struct uart_port *port)
+{
+	return  0;
+}
+
+/* configure/autoconfigure the port */
+static void lpuart_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE)
+		port->type = PORT_LPUART;
+}
+
+static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
+		ret = -EINVAL;
+	if (port->irq != ser->irq)
+		ret = -EINVAL;
+	if (ser->io_type != UPIO_MEM)
+		ret = -EINVAL;
+	if (port->uartclk / 16 != ser->baud_base)
+		ret = -EINVAL;
+	if (port->iobase != ser->port)
+		ret = -EINVAL;
+	if (ser->hub6 != 0)
+		ret = -EINVAL;
+	return ret;
+}
+
+static struct uart_ops lpuart_pops = {
+	.tx_empty	= lpuart_tx_empty,
+	.set_mctrl	= lpuart_set_mctrl,
+	.get_mctrl	= lpuart_get_mctrl,
+	.stop_tx	= lpuart_stop_tx,
+	.start_tx	= lpuart_start_tx,
+	.stop_rx	= lpuart_stop_rx,
+	.enable_ms	= lpuart_enable_ms,
+	.break_ctl	= lpuart_break_ctl,
+	.startup	= lpuart_startup,
+	.shutdown	= lpuart_shutdown,
+	.set_termios	= lpuart_set_termios,
+	.type		= lpuart_type,
+	.request_port	= lpuart_request_port,
+	.release_port	= lpuart_release_port,
+	.config_port	= lpuart_config_port,
+	.verify_port	= lpuart_verify_port,
+};
+
+static struct lpuart_port *lpuart_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
+static void lpuart_console_putchar(struct uart_port *port, int ch)
+{
+	while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
+		barrier();
+
+	writeb(ch, port->membase + UARTDR);
+}
+
+static void
+lpuart_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct lpuart_port *sport = lpuart_ports[co->index];
+	unsigned char  old_cr2, cr2;
+
+	/* first save CR2 and then disable interrupts */
+	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
+	cr2 |= (UARTCR2_TE |  UARTCR2_RE);
+	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+	writeb(cr2, sport->port.membase + UARTCR2);
+
+	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
+
+	/* wait for transmitter finish complete and restore CR2 */
+	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+		barrier();
+
+	writeb(old_cr2, sport->port.membase + UARTCR2);
+}
+
+/*
+ * if the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+lpuart_console_get_options(struct lpuart_port *sport, int *baud,
+			   int *parity, int *bits)
+{
+	unsigned char cr, bdh, bdl, brfa;
+	unsigned int sbr, uartclk, baud_raw;
+
+	cr = readb(sport->port.membase + UARTCR2);
+	cr &= UARTCR2_TE | UARTCR2_RE;
+	if (!cr)
+		return;
+
+	/* ok, the port was enabled */
+
+	cr = readb(sport->port.membase + UARTCR1);
+
+	*parity = 'n';
+	if (cr & UARTCR1_PE) {
+		if (cr & UARTCR1_PT)
+			*parity = 'o';
+		else
+			*parity = 'e';
+	}
+
+	if (cr & UARTCR1_M)
+		*bits = 9;
+	else
+		*bits = 8;
+
+	bdh = readb(sport->port.membase + UARTBDH);
+	bdh &= UARTBDH_SBR_MASK;
+	bdl = readb(sport->port.membase + UARTBDL);
+	sbr = bdh;
+	sbr <<= 8;
+	sbr |= bdl;
+	brfa = readb(sport->port.membase + UARTCR4);
+	brfa &= UARTCR4_BRFA_MASK;
+
+	uartclk = clk_get_rate(sport->clk);
+	/*
+	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
+	 */
+	baud_raw = uartclk / (16 * (sbr + brfa / 32));
+
+	if (*baud != baud_raw)
+		printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+				"from %d to %d\n", baud_raw, *baud);
+}
+
+static int __init lpuart_console_setup(struct console *co, char *options)
+{
+	struct lpuart_port *sport;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	/*
+	 * check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
+		co->index = 0;
+
+	sport = lpuart_ports[co->index];
+	if (sport == NULL)
+		return -ENODEV;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		lpuart_console_get_options(sport, &baud, &parity, &bits);
+
+	lpuart_setup_watermark(sport);
+
+	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver lpuart_reg;
+static struct console lpuart_console = {
+	.name		= DEV_NAME,
+	.write		= lpuart_console_write,
+	.device		= uart_console_device,
+	.setup		= lpuart_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &lpuart_reg,
+};
+
+#define LPUART_CONSOLE	(&lpuart_console)
+#else
+#define LPUART_CONSOLE	NULL
+#endif
+
+static struct uart_driver lpuart_reg = {
+	.owner		= THIS_MODULE,
+	.driver_name	= DRIVER_NAME,
+	.dev_name	= DEV_NAME,
+	.nr		= ARRAY_SIZE(lpuart_ports),
+	.cons		= LPUART_CONSOLE,
+};
+
+static int lpuart_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct lpuart_port *sport;
+	struct resource *res;
+	int ret;
+
+	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+	if (!sport)
+		return -ENOMEM;
+
+	pdev->dev.coherent_dma_mask = 0;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	sport->port.mapbase = res->start;
+	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(sport->port.membase))
+		return PTR_ERR(sport->port.membase);
+
+	sport->port.dev = &pdev->dev;
+	sport->port.type = PORT_LPUART;
+	sport->port.iotype = UPIO_MEM;
+	sport->port.irq = platform_get_irq(pdev, 0);
+	sport->port.ops = &lpuart_pops;
+	sport->port.flags = UPF_BOOT_AUTOCONF;
+
+	sport->clk = devm_clk_get(&pdev->dev, "ipg");
+	if (IS_ERR(sport->clk)) {
+		ret = PTR_ERR(sport->clk);
+		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(sport->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
+		return ret;
+	}
+
+	sport->port.uartclk = clk_get_rate(sport->clk);
+
+	lpuart_ports[sport->port.line] = sport;
+
+	platform_set_drvdata(pdev, &sport->port);
+
+	ret = uart_add_one_port(&lpuart_reg, &sport->port);
+	if (ret) {
+		clk_disable_unprepare(sport->clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int lpuart_remove(struct platform_device *pdev)
+{
+	struct lpuart_port *sport = platform_get_drvdata(pdev);
+
+	uart_remove_one_port(&lpuart_reg, &sport->port);
+
+	clk_disable_unprepare(sport->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int lpuart_suspend(struct device *dev)
+{
+	struct lpuart_port *sport = dev_get_drvdata(dev);
+
+	uart_suspend_port(&lpuart_reg, &sport->port);
+
+	return 0;
+}
+
+static int lpuart_resume(struct device *dev)
+{
+	struct lpuart_port *sport = dev_get_drvdata(dev);
+
+	uart_resume_port(&lpuart_reg, &sport->port);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
+
+static struct platform_driver lpuart_driver = {
+	.probe		= lpuart_probe,
+	.remove		= lpuart_remove,
+	.driver		= {
+		.name	= "fsl-lpuart",
+		.owner	= THIS_MODULE,
+		.of_match_table = lpuart_dt_ids,
+		.pm	= &lpuart_pm_ops,
+	},
+};
+
+static int __init lpuart_serial_init(void)
+{
+	int ret;
+
+	pr_info("serial: Freescale lpuart driver\n");
+
+	ret = uart_register_driver(&lpuart_reg);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&lpuart_driver);
+	if (ret)
+		uart_unregister_driver(&lpuart_reg);
+
+	return 0;
+}
+
+static void __exit lpuart_serial_exit(void)
+{
+	platform_driver_unregister(&lpuart_driver);
+	uart_unregister_driver(&lpuart_reg);
+}
+
+module_init(lpuart_serial_init);
+module_exit(lpuart_serial_exit);
+
+MODULE_DESCRIPTION("Freescale lpuart serial port driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 74c2bf7..c8eaeb5 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -226,4 +226,7 @@
 /* Rocketport EXPRESS/INFINITY */
 #define PORT_RP2	102
 
+/* Freescale lpuart */
+#define PORT_LPUART	103
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
1.8.0




From richard.genoud at gmail.com  Thu May 30 02:39:58 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Thu, 30 May 2013 08:39:58 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <20130529193220.GB19468@game.jcrosoft.org>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
 <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
 <20130529193220.GB19468@game.jcrosoft.org>
Message-ID: <CACQ1gAj_m_aWaq5J41SY8EPwOH5-3zYPsf2WJCunvVnBCyq00Q@mail.gmail.com>

2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> On 19:44 Wed 29 May     , Richard Genoud wrote:
>> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> > On 16:36 Wed 29 May     , Richard Genoud wrote:
>> >> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> >> > Today we mix pdata and drivers data in the struct atmel_lcdfb_info
>> >> > Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
>> >> >
>> >> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> >> > Cc: linux-fbdev at vger.kernel.org
>> >> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>> >> > Cc: Andrew Morton <akpm at linux-foundation.org>
>> >> > Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
>> >> > ---
>> >> >  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
>> >> >  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
>> >> >  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
>> >> >  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
>> >> >  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
>> >> >  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
>> >> >  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
>> >> >  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
>> >> >  arch/arm/mach-at91/board.h                  |    4 +-
>> >> >  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
>> >> >  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
>> >> >  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
>> >> >  arch/avr32/boards/atstk1000/setup.c         |    2 +-
>> >> >  arch/avr32/boards/favr-32/setup.c           |    2 +-
>> >> >  arch/avr32/boards/hammerhead/setup.c        |    2 +-
>> >> >  arch/avr32/boards/merisc/display.c          |    2 +-
>> >> >  arch/avr32/boards/mimc200/setup.c           |    4 +-
>> >> >  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
>> >> >  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
>> >> >  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
>> >> >  include/video/atmel_lcdc.h                  |   24 +------
>> >> >  21 files changed, 109 insertions(+), 101 deletions(-)
>> >> >
>> >> [snip]
>> >> > diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
>> >> > index c1a2914..98733cd4 100644
>> >> > --- a/drivers/video/atmel_lcdfb.c
>> >> > +++ b/drivers/video/atmel_lcdfb.c
>> >> > @@ -20,12 +20,45 @@
>> >> >  #include <linux/gfp.h>
>> >> >  #include <linux/module.h>
>> >> >  #include <linux/platform_data/atmel.h>
>> >> > +#include <video/of_display_timing.h>
>> >> >
>> >> >  #include <mach/cpu.h>
>> >> >  #include <asm/gpio.h>
>> >> >
>> >> >  #include <video/atmel_lcdc.h>
>> >> >
>> >> > +struct atmel_lcdfb_config {
>> >> > +       bool have_alt_pixclock;
>> >> > +       bool have_hozval;
>> >> > +       bool have_intensity_bit;
>> >> > +};
>> >> > +
>> >> > + /* LCD Controller info data structure, stored in device platform_data */
>> >> > +struct atmel_lcdfb_info {
>> >> > +       spinlock_t              lock;
>> >> > +       struct fb_info          *info;
>> >> > +       void __iomem            *mmio;
>> >> > +       int                     irq_base;
>> >> > +       struct work_struct      task;
>> >> > +
>> >> > +       unsigned int            smem_len;
>> >> > +       struct platform_device  *pdev;
>> >> > +       struct clk              *bus_clk;
>> >> > +       struct clk              *lcdc_clk;
>> >> > +
>> >> > +       struct backlight_device *backlight;
>> >> > +       u8                      bl_power;
>> >> > +       bool                    lcdcon_pol_negative;
>> >> I think lcdcon_pol_negative should be part of pdata, because it really
>> >> depends on how the PWM is wired on the board.
>> >>
>> >
>> > maybe but no one mainline use it on any pdata for non-dt boars
>> > so I did not want to expose it
>> Well, at least, I'm using it :)
>> (and I guess that Andreas is using it also, otherwise he wouldn't have
>> introduce it !)
>
> yes but pdata is for non-dt boards, for dt you can keep it in struct
> atmel_lcdfb_info and add a property
>
> if non-dt boards want it my answer is I do not care switch to DT

ok (I use a full DT board based on sam9g35)

so I'll add something like
sinfo->lcdcon_pol_negative = of_property_read_bool(display_np,
"atmel,lcdcon-pwm-pulse-low");
in /atmel_lcdfb.c

But I thought the goal of this patch was to separate driver data from
platform specific data, and IMHO, lcdcon_pol_negative is a specificity
of the platform.

Best regards,
Richard.


From pekon at ti.com  Thu May 30 02:44:02 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 30 May 2013 06:44:02 +0000
Subject: [PATCH] dts: am33xx: Correct properties on gpmc node
In-Reply-To: <87mwrfbfgv.fsf@dell.be.48ers.dk>
References: <1369729497-11897-1-git-send-email-larsi@wh2.tu-dresden.de>
 <87mwrfbfgv.fsf@dell.be.48ers.dk>
Message-ID: <20980858CB6D3A4BAE95CA194937D5E73E9C8B98@DBDE04.ent.ti.com>

> >>>>> "Lars" == Lars Poeschel <larsi at wh2.tu-dresden.de> writes:
> 
>  Lars> From: Lars Poeschel <poeschel at lemonage.de>
>  Lars> The gpmc driver is actually looking for "gpmc,num-cs" and
>  Lars> "gpmc,num-waitpins" properties in DT. The binding doc also states
>  Lars> this.
>  Lars> Correct the properties in the dts to provide the right values for the
>  Lars> gpmc driver.
> 
>  Lars> Signed-off-by: Lars Poeschel <poeschel at lemonage.de>
> 
> Acked-by: Peter Korsgaard <jacmet at sunsite.dk>
> 
Acked-by: Pekon Gupta <pekon at ti.com>

My another patch [V3, 2/3] on same can be dropped, in lieu of this one..
http://www.spinics.net/lists/linux-omap/msg91167.html


with regards, pekon


From yadi.brar01 at gmail.com  Thu May 30 02:55:40 2013
From: yadi.brar01 at gmail.com (Yadwinder Singh Brar)
Date: Thu, 30 May 2013 12:25:40 +0530
Subject: [PATCH v2 2/5] clk: samsung: Add support to register rate_table
 for PLL3xxx
In-Reply-To: <CAD=FV=VDi+SfebiFnPNp8qR__9L=o9TJ+WSPRfRQLX+p+TMmJw@mail.gmail.com>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
 <1369834677-20312-3-git-send-email-vikas.sajjan@linaro.org>
 <CAD=FV=VDi+SfebiFnPNp8qR__9L=o9TJ+WSPRfRQLX+p+TMmJw@mail.gmail.com>
Message-ID: <CAKew6eVGnHNN7Fk=sqzE1iV+SFtJ1z4k1freeWdbGaYPXqpUvQ@mail.gmail.com>

Hi Doug,

On Thu, May 30, 2013 at 5:14 AM, Doug Anderson <dianders at chromium.org> wrote:
> Vikas / Yadwinder,
>
> On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
>> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>>
>> This patch defines a common rate_table which will contain recommended p, m, s,
>> k values for supported rates that needs to be changed for changing
>> corresponding PLL's rate.
>>
>> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
>>  drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
>>  drivers/clk/samsung/clk-pll.c        |   14 ++++++++++++--
>>  drivers/clk/samsung/clk-pll.h        |   33 +++++++++++++++++++++++++++++++--
>>  4 files changed, 54 insertions(+), 15 deletions(-)
>
> I also reviewed this in our gerrit
> <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize
> here for the list...
>
>>  struct clk * __init samsung_clk_register_pll35xx(const char *name,
>> -                       const char *pname, const void __iomem *base)
>> +                       const char *pname, const void __iomem *base,
>> +                       const struct samsung_pll_rate_table *rate_table,
>> +                       const unsigned int rate_count)
>
> Feels like you should document here that rate_table needs to be sorted
> and the sort order.
>

sure,  we will add comment  to sort the table in descending order.

>> +struct samsung_pll_rate_table {
>> +       unsigned  int rate;
>
> nit: extra space before "int" should be removed.
>

ok

> Also: you can include rate here if you need a convenient place to
> store it (which sadly means that this structure can't be const).
> ...but I do like Tomasz's idea of actually calculating it.  You can't
> know it at compile time since the parent rate comes from the device
> tree.
>
> compatible = "samsung,clock-xxti";
> clock-frequency = <24000000>;
>

Actually this table should contain the recommended values
and if we see the user manual, the input(parent) rate is also a part
of recommended
table of different output rate for a particular PLL for that SoC.

So as Tomasz said input(parent) rate may change with board,
then, do those corresponding recommended p, m, s, k will be valid?

In case, input(parent) rate changes then we may need different set of p, m ,s, k
values recommended for new input rate to get required(recommended to
use) output rate.

So, we think its better that the p, m, s and k along with the parent
is known at the compile time ( or DT ?),
as these p, m, s, k values are very much coupled with the parent rate
to achieve the
 required(recommended to use) output rate.

Also, since the sorted table is required (sorted based on "rate"),
its better to have the rate in a const rate table.

And the whole set of recommended values should come from same place(DT
or static table),
to keep the things simple and consistent.

Moreover, practically for a particular SoC , we use the recommended
input(parent) rate only for a PLL.
So we should keep the things simple here presently.

>> +       unsigned int pdiv;
>> +       unsigned int mdiv;
>> +       unsigned int sdiv;
>> +       unsigned int kdiv;
>
> I think kdiv is signed.
>

No, as these values should be the recommended values to be written in
corresponding  register bits. So it should remain unsigned.

K value should be considered as negative only while recalculating rate.

As per exynos5250 user manual's section 7.3.2 :
" K value description "Postive value (Negative value)":
Postive values is that you should write EPLLCON/VPLLCON register.
Negative value is that you can calculate PLL output frequency with it."

> -Doug

Regards,
Yadwinder & Vikas.


From jg1.han at samsung.com  Thu May 30 03:05:54 2013
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 30 May 2013 16:05:54 +0900
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <51A6C97A.6030306@linaro.org>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 <51A5C16D.20408@linaro.org> <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
 <CAOesGMiYs6GfaWGWYB8cw_cJ6_RmmZTb4oPfXo1PYJT8-jdHzw@mail.gmail.com>
 <51A6C97A.6030306@linaro.org>
Message-ID: <000101ce5d04$20abb7a0$620326e0$@samsung.com>

On Thursday, May 30, 2013 12:38 PM, Tushar Behera wrote:
>On 05/30/2013 12:16 AM, Olof Johansson wrote:
>> On Wed, May 29, 2013 at 2:33 AM, Jingoo Han <jg1.han at samsung.com> wrote:
>>
>>> However, Olof Johansson mentioned, 'drivers/platform/arm/board_arndale.c'
>>> would be a good alternative.
>>
>>
>> Whoa. I didn't quite realize what I proposed, or rather, how what I
>> proposed could be perceived. I take it back. :)

My original message is as below.

"However, as Olof Johansson mentioned, 'drivers/platform/arm/'
would be a good alternative."

Also, 'board_arndale.c' should not be mentioned.
Sorry for making confusion. :)

>>
>> We must _not_ introduce something that will be abused as a new home
>> for board file junk. If we do introduce a platform glue directory it
>> would need to be very limited in scope. Compare to what's in
>> drivers/platform/x86 today.
>>
>>
>> -Olof
>>
>
>This was my proof-of-concept for moving USB hub reset code out of USB
>driver. Verified that it works.

Thank you for your additional comment.

>
>I would wait for your patches for wifi-reset sequence and then will add
>hub-reset code for Arndale.

Yes, this way looks good.

Best regards,
Jingoo Han

>
>
>--
>Tushar Behera



From b-cousson at ti.com  Thu May 30 03:24:24 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Thu, 30 May 2013 09:24:24 +0200
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <20980858CB6D3A4BAE95CA194937D5E73E9C5629@DBDE04.ent.ti.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com> <20130508235404.GX32546@atomide.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C5629@DBDE04.ent.ti.com>
Message-ID: <51A6FEA8.5030704@ti.com>

Hi Pekon,

On 05/20/2013 06:44 AM, Gupta, Pekon wrote:
>  
>>>>>
>>>>>  	am33xx_pinmux: pinmux at 44e10800 {
>>>>>  		pinctrl-names = "default";
>>>>> -		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
>>>>> +		pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
>>>>> +			&nandflash_pins_s0>;
>>>>
>>>> Why add this to the board level fallback (called pinctrl hogs, I think)?
>>>> This can be part of nand node you added below so that the pinctrl will
>>>> take effect when nand gets probed instead of all the time.
>>>
>>> Yes we should have all the pinctrl entries under the related drivers.
>>> This makes it easy remux pins during runtime if needed, and also
>>> allows unloading pinctrl-single.ko for development.
>>>
>> Yes, accepted. This has been already fixed in v3 of this patch set.
>> If all fine, then please pull this for next merge..
>>
>> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046712.html
>>
>> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046814.html
>>
>> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046710.html
>>
>>
>> with regards, pekon
> 
> Request you to please accept | provide feedbacks on this patch series.
> These are waiting acceptance since Jan-2013, and are necessary for 
> DT based configs for board having NAND support.
> 
> with regards, pekon

Sorry, I missed that series.

I'm applying it right now.

Thanks,
Benoit




From srinidhi.kasagar at stericsson.com  Thu May 30 03:26:13 2013
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Thu, 30 May 2013 12:56:13 +0530
Subject: [PATCH 6/8] ARM: ux500: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-7-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
 <1369665166-13049-7-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <20130530072612.GB32244@bnru10>

On Mon, May 27, 2013 at 16:32:43 +0200, Sanjay Singh Rawat wrote:
> use cpu_do_idle for entering the wfi mode.
> 
> Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
> ---
>  arch/arm/mach-ux500/hotplug.c |    5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
> index 2bc00b0..f4ded92 100644
> --- a/arch/arm/mach-ux500/hotplug.c
> +++ b/arch/arm/mach-ux500/hotplug.c
> @@ -25,8 +25,9 @@ void __ref ux500_cpu_die(unsigned int cpu)
>  {
>  	/* directly enter low power state, skipping secure registers */
>  	for (;;) {
> -		__asm__ __volatile__("dsb\n\t" "wfi\n\t"
> -				: : : "memory");
> +		/* enter WFI mode */
> +		cpu_do_idle();
> +

Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>

srinidhi

>  		if (pen_release == cpu_logical_map(cpu)) {
>  			/*
>  			 * OK, proper wakeup, we're done
> -- 
> 1.7.9.5
> 


From plagnioj at jcrosoft.com  Thu May 30 03:23:28 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 May 2013 09:23:28 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <CACQ1gAj_m_aWaq5J41SY8EPwOH5-3zYPsf2WJCunvVnBCyq00Q@mail.gmail.com>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
 <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
 <20130529193220.GB19468@game.jcrosoft.org>
 <CACQ1gAj_m_aWaq5J41SY8EPwOH5-3zYPsf2WJCunvVnBCyq00Q@mail.gmail.com>
Message-ID: <20130530072328.GE19468@game.jcrosoft.org>

On 08:39 Thu 30 May     , Richard Genoud wrote:
> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> > On 19:44 Wed 29 May     , Richard Genoud wrote:
> >> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >> > On 16:36 Wed 29 May     , Richard Genoud wrote:
> >> >> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >> >> > Today we mix pdata and drivers data in the struct atmel_lcdfb_info
> >> >> > Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
> >> >> >
> >> >> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >> >> > Cc: linux-fbdev at vger.kernel.org
> >> >> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> >> >> > Cc: Andrew Morton <akpm at linux-foundation.org>
> >> >> > Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> >> >> > ---
> >> >> >  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
> >> >> >  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
> >> >> >  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
> >> >> >  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
> >> >> >  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
> >> >> >  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
> >> >> >  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
> >> >> >  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
> >> >> >  arch/arm/mach-at91/board.h                  |    4 +-
> >> >> >  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
> >> >> >  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
> >> >> >  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
> >> >> >  arch/avr32/boards/atstk1000/setup.c         |    2 +-
> >> >> >  arch/avr32/boards/favr-32/setup.c           |    2 +-
> >> >> >  arch/avr32/boards/hammerhead/setup.c        |    2 +-
> >> >> >  arch/avr32/boards/merisc/display.c          |    2 +-
> >> >> >  arch/avr32/boards/mimc200/setup.c           |    4 +-
> >> >> >  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
> >> >> >  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
> >> >> >  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
> >> >> >  include/video/atmel_lcdc.h                  |   24 +------
> >> >> >  21 files changed, 109 insertions(+), 101 deletions(-)
> >> >> >
> >> >> [snip]
> >> >> > diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> >> >> > index c1a2914..98733cd4 100644
> >> >> > --- a/drivers/video/atmel_lcdfb.c
> >> >> > +++ b/drivers/video/atmel_lcdfb.c
> >> >> > @@ -20,12 +20,45 @@
> >> >> >  #include <linux/gfp.h>
> >> >> >  #include <linux/module.h>
> >> >> >  #include <linux/platform_data/atmel.h>
> >> >> > +#include <video/of_display_timing.h>
> >> >> >
> >> >> >  #include <mach/cpu.h>
> >> >> >  #include <asm/gpio.h>
> >> >> >
> >> >> >  #include <video/atmel_lcdc.h>
> >> >> >
> >> >> > +struct atmel_lcdfb_config {
> >> >> > +       bool have_alt_pixclock;
> >> >> > +       bool have_hozval;
> >> >> > +       bool have_intensity_bit;
> >> >> > +};
> >> >> > +
> >> >> > + /* LCD Controller info data structure, stored in device platform_data */
> >> >> > +struct atmel_lcdfb_info {
> >> >> > +       spinlock_t              lock;
> >> >> > +       struct fb_info          *info;
> >> >> > +       void __iomem            *mmio;
> >> >> > +       int                     irq_base;
> >> >> > +       struct work_struct      task;
> >> >> > +
> >> >> > +       unsigned int            smem_len;
> >> >> > +       struct platform_device  *pdev;
> >> >> > +       struct clk              *bus_clk;
> >> >> > +       struct clk              *lcdc_clk;
> >> >> > +
> >> >> > +       struct backlight_device *backlight;
> >> >> > +       u8                      bl_power;
> >> >> > +       bool                    lcdcon_pol_negative;
> >> >> I think lcdcon_pol_negative should be part of pdata, because it really
> >> >> depends on how the PWM is wired on the board.
> >> >>
> >> >
> >> > maybe but no one mainline use it on any pdata for non-dt boars
> >> > so I did not want to expose it
> >> Well, at least, I'm using it :)
> >> (and I guess that Andreas is using it also, otherwise he wouldn't have
> >> introduce it !)
> >
> > yes but pdata is for non-dt boards, for dt you can keep it in struct
> > atmel_lcdfb_info and add a property
> >
> > if non-dt boards want it my answer is I do not care switch to DT
> 
> ok (I use a full DT board based on sam9g35)
> 
> so I'll add something like
> sinfo->lcdcon_pol_negative = of_property_read_bool(display_np,
> "atmel,lcdcon-pwm-pulse-low");
> in /atmel_lcdfb.c
> 
> But I thought the goal of this patch was to separate driver data from
> platform specific data, and IMHO, lcdcon_pol_negative is a specificity
> of the platform.

You are right but as non one mainline use it as pdata I choose to drop it
and only keep it on the driver as we can still use it for DT

It's a way to force peopoe to switch to DT

Best Regards,
J.
> 
> Best regards,
> Richard.


From pekon at ti.com  Thu May 30 03:31:51 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 30 May 2013 07:31:51 +0000
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <51A6FEA8.5030704@ti.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com> <20130508235404.GX32546@atomide.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C5629@DBDE04.ent.ti.com>
 <51A6FEA8.5030704@ti.com>
Message-ID: <20980858CB6D3A4BAE95CA194937D5E73E9C8BCD@DBDE04.ent.ti.com>

 
> Sorry, I missed that series.
> 
> I'm applying it right now.
> 
No issues.. Please pick newer v4 versions of this series.
Following are rebased, updated and tested on linux-3.10-rc3

[PATCH v4,0/3] http://www.spinics.net/lists/linux-omap/msg91165.html

[PATCH v4,1/3] http://www.spinics.net/lists/linux-omap/msg91166.html

[PATCH v4,2/3] (please skip this one)
instead pick http://www.spinics.net/lists/linux-omap/msg91161.html

[PATCH v4,3/3] http://www.spinics.net/lists/linux-omap/msg91167.html


Thanks..
with regards, pekon


From pekon at ti.com  Thu May 30 03:36:14 2013
From: pekon at ti.com (Gupta, Pekon)
Date: Thu, 30 May 2013 07:36:14 +0000
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <20980858CB6D3A4BAE95CA194937D5E73E9C8BCD@DBDE04.ent.ti.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com> <20130508235404.GX32546@atomide.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C5629@DBDE04.ent.ti.com>
 <51A6FEA8.5030704@ti.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C8BCD@DBDE04.ent.ti.com>
Message-ID: <20980858CB6D3A4BAE95CA194937D5E73E9C8C0D@DBDE04.ent.ti.com>

> > Sorry, I missed that series.
> >
> > I'm applying it right now.
> >
> No issues.. Please pick newer v4 versions of this series.
> Following are rebased, updated and tested on linux-3.10-rc3
> 
> [PATCH v4,0/3] http://www.spinics.net/lists/linux-omap/msg91165.html
> 
> [PATCH v4,1/3] http://www.spinics.net/lists/linux-omap/msg91166.html
> 
> [PATCH v4,2/3] (please skip this one)
> instead pick http://www.spinics.net/lists/linux-omap/msg91161.html
> 
> [PATCH v4,3/3] (typo) 
	http://www.spinics.net/lists/linux-omap/msg91164.html
> 
> 
> Thanks..
> with regards, pekon
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/


From b-cousson at ti.com  Thu May 30 03:39:17 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Thu, 30 May 2013 09:39:17 +0200
Subject: [v2, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to
 am335x-evm
In-Reply-To: <20980858CB6D3A4BAE95CA194937D5E73E9C8BCD@DBDE04.ent.ti.com>
References: <ebfab3e9123b3e50b9a9678c1480191addd86d59.1359007746.git.avinashphilip@ti.com>
 <517F5126.5000509@ti.com> <20130508235404.GX32546@atomide.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C320D@DBDE04.ent.ti.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C5629@DBDE04.ent.ti.com>
 <51A6FEA8.5030704@ti.com>
 <20980858CB6D3A4BAE95CA194937D5E73E9C8BCD@DBDE04.ent.ti.com>
Message-ID: <51A70225.50300@ti.com>

On 05/30/2013 09:31 AM, Gupta, Pekon wrote:
>> Sorry, I missed that series.
>>
>> I'm applying it right now.
>>
> No issues.. Please pick newer v4 versions of this series.
> Following are rebased, updated and tested on linux-3.10-rc3
> 
> [PATCH v4,0/3] http://www.spinics.net/lists/linux-omap/msg91165.html
> 
> [PATCH v4,1/3] http://www.spinics.net/lists/linux-omap/msg91166.html
> 
> [PATCH v4,2/3] (please skip this one)
> instead pick http://www.spinics.net/lists/linux-omap/msg91161.html
> 
> [PATCH v4,3/3] http://www.spinics.net/lists/linux-omap/msg91167.html

Could you please rebase on for_3.11/dts and repost the whole stuff. It
looks like Tony already pulled the GPMC node, and the two other ones
cannot apply anymore.

Thanks,
Benoit



From nicolas.ferre at atmel.com  Thu May 30 03:41:33 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 30 May 2013 09:41:33 +0200
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <1369298335-24597-1-git-send-email-jhovold@gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
Message-ID: <51A702AD.7000507@atmel.com>

On 23/05/2013 10:38, Johan Hovold :
> This is an update of the shadow-interrupt-mask series against v3.10-rc2.
>
> I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
> affected. If not, then some probing mechanism as the one Doug suggested
> could be implemented on top of (a subset of) these patches. What do you
> say, Nicolas?

No probing mechanism is needed: only sam9x5 are affected.

> Note that the first patch (adding a missing OF compile guard) could be
> applied straight away.
>
> Thanks,
> Johan
>
>
> v3:
>   - rebase against v3.10-rc2
>   - remove some comments

Thanks for rebasing this series.

Best regards,

> v2:
>   - rebase on top of DT-support patch by Joachim Eastwood
>   - add missing brace in DT-id table
>
>
> Johan Hovold (5):
>    rtc-at91rm9200: add match-table compile guard
>    rtc-at91rm9200: add configuration support
>    rtc-at91rm9200: refactor interrupt-register handling
>    rtc-at91rm9200: add shadow interrupt mask
>    rtc-at91rm9200: use shadow IMR on at91sam9x5
>
>   .../bindings/rtc/atmel,at91rm9200-rtc.txt          |   2 +-
>   arch/arm/boot/dts/at91sam9x5.dtsi                  |   2 +-
>   drivers/rtc/rtc-at91rm9200.c                       | 131 +++++++++++++++++----
>   3 files changed, 113 insertions(+), 22 deletions(-)
>


-- 
Nicolas Ferre


From linus.walleij at linaro.org  Thu May 30 03:41:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 09:41:38 +0200
Subject: [PATCH -next v2] dmaengine: ste_dma40: fix error return code in
 d40_probe()
In-Reply-To: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>
References: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>
Message-ID: <CACRpkdYBfvr0kA7bd-6Ns78UH7JtBCFDzFxyHLgtReB32O4D+w@mail.gmail.com>

On Thu, May 30, 2013 at 6:32 AM, Wei Yongjun <weiyj.lk at gmail.com> wrote:

> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>
> In many of the error handling case, the return value 'ret' not set
> and 0 will be return from d40_probe() even if error, but we should
> return a negative error code instead in those error handling case.
> This patch fixed them, and also removed useless variable 'err'.
>
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> ---
> v1 -> v2: rebased on linux-next.git

I've tentatively applied this to my dma40 branch, waiting for Vinod
to ACK it.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 03:44:49 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 09:44:49 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda+C7qzKSssXStkcM4eOQaHUcWEUd6txfV-pAWdTT=YEw@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my dma40 branch with Felipe's ACK.

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 03:48:33 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 09:48:33 +0200
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <20130529175741.GG21290@arwen.pp.htv.fi>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <20130529175741.GG21290@arwen.pp.htv.fi>
Message-ID: <CACRpkda3d9_XvqRmy0nbWyri2xC3Qst2U2Sv=UDxV4w-UxK_JQ@mail.gmail.com>

On Wed, May 29, 2013 at 7:57 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
>> For all ux500 based platforms the maximum number of end-points are used.
>> Move this knowledge into the driver so we can relinquish the burden from
>> platform data. This also removes quite a bit of complexity from the driver
>> and will aid us when we come to enable the driver for Device Tree.
>>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: linux-usb at vger.kernel.org
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>
> for drivers/usb/musb
>
> Acked-by: Felipe Balbi <balbi at ti.com>

Is that only for this patch 20/39 or also 21, 22 & 23?

Poke us if we should re-send them...

Yours,
Linus Walleij


From nicolas.ferre at atmel.com  Thu May 30 03:50:27 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 30 May 2013 09:50:27 +0200
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
 <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
Message-ID: <51A704C3.6010109@atmel.com>

On 29/05/2013 22:41, Robert Nelson :
> On Wed, May 29, 2013 at 3:33 PM, Andrew Morton
> <akpm at linux-foundation.org> wrote:
>> On Thu, 23 May 2013 10:38:50 +0200 Johan Hovold <jhovold at gmail.com> wrote:
>>
>>> This is an update of the shadow-interrupt-mask series against v3.10-rc2.
>>>
>>> I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
>>> affected. If not, then some probing mechanism as the one Doug suggested
>>> could be implemented on top of (a subset of) these patches. What do you
>>> say, Nicolas?
>>>
>>> Note that the first patch (adding a missing OF compile guard) could be
>>> applied straight away.
>>
>> At this stage it is unclear to me how to proceed with patches 2-5.
>
> fyi:
>
> A version of these patches had been applied once before:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0ef1594c017521ea89278e80fe3f80dafb17abde
>
> But due to a few issues it was later reverted:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=e24b0bfa2f0446ffaad2661040be23668133aef8

This new revision doesn't have the issue encountered by first version.

Andrew,

The review of this patch series was in my TODO list for some time...

Today, I magically took time to review it ;-)
The patch series is good and I (even if it is too late) here is my:

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

I do not know if the series can be stacked for inclusion in 3.10-rc but 
the resolution of this bug can help a lot (as Douglas is saying in 
subsequent email...).

Best regards,
-- 
Nicolas Ferre


From shawn.guo at linaro.org  Thu May 30 03:56:34 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 15:56:34 +0800
Subject: [PATCH] ARM: dts: imx53: add cspi pinctrl
In-Reply-To: <1369644741-17153-1-git-send-email-jonas@microbit.se>
References: <1369644741-17153-1-git-send-email-jonas@microbit.se>
Message-ID: <20130530075630.GA2670@S2101-09.ap.freescale.net>

On Mon, May 27, 2013 at 10:52:21AM +0200, Jonas Andersson wrote:
> Add a group to the cspi pinctrl.
> 
> Signed-off-by: Jonas Andersson <jonas at microbit.se>

Applied all 3, thanks.



From geert at linux-m68k.org  Thu May 30 04:07:48 2013
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 30 May 2013 10:07:48 +0200
Subject: linux-next: Tree for May 30
In-Reply-To: <20130530163334.105322d3c166b74165f1dad4@canb.auug.org.au>
References: <20130530163334.105322d3c166b74165f1dad4@canb.auug.org.au>
Message-ID: <CAMuHMdXNzmJtfxzzt3kuzROzJmfsTKkp_4_8pdg=ahLv2LdU+Q@mail.gmail.com>

On Thu, May 30, 2013 at 8:33 AM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Changes since 20130529:

The following defconfigs fail without anything useful in the log:
  - at91sam9g20_defconfig
  - at91sam9261_defconfig
  - at91sam9260_defconfig

A manual run reveals why:
Can't find default configuration "arch/arm/configs/at91sam9g20_defconfig"!

This is due to the merge of several config files:

commit b3f442b0eedbc20b5ce3f4a96530588d14901199
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Date:   Wed May 15 17:19:21 2013 +0200

    ARM: at91: udpate defconfigs

    Merge 9g20 with 9260 and 9g10 with 9261 as those SoCs can run from the same
    kernel even in non DT world.

    Fix the sam9261ek to allow 9g10 and sam9261 to compile together.

    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
    Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

 arch/arm/configs/at91_dt_defconfig                 |   55 +++---
 arch/arm/configs/at91rm9200_defconfig              |  218 +++-----------------
 ...am9g20_defconfig => at91sam9260_9g20_defconfig} |   67 +++++--
 arch/arm/configs/at91sam9260_defconfig             |   91 --------
 ...am9261_defconfig => at91sam9261_9g10_defconfig} |   19 +--
 arch/arm/configs/at91sam9263_defconfig             |   39 ++---
 arch/arm/configs/at91sam9g45_defconfig             |   94 +++------
 arch/arm/configs/sama5_defconfig                   |   35 +++-
 arch/arm/mach-at91/Kconfig.non_dt                  |  159 +++++++--------
 arch/arm/mach-at91/Makefile                        |    2 -
 arch/arm/mach-at91/board-sam9261ek.c               |   28 ++--
 11 files changed, 268 insertions(+), 539 deletions(-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From maxime.ripard at free-electrons.com  Thu May 30 04:11:29 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 10:11:29 +0200
Subject: [PATCHv3 RESEND 0/6] ARM: sunxi: Add support for A10 Ethernet
 controller
In-Reply-To: <CACQ1gAgp6o8HqQcv=4cWoAZze3wtXHMX+g+7KvV-pnC2W5=iyg@mail.gmail.com>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <CACQ1gAgp6o8HqQcv=4cWoAZze3wtXHMX+g+7KvV-pnC2W5=iyg@mail.gmail.com>
Message-ID: <20130530081129.GF9799@lukather>

Hi Richard,

On Wed, May 29, 2013 at 08:15:49PM +0200, Richard Genoud wrote:
> 2013/5/24 Maxime Ripard <maxime.ripard at free-electrons.com>:
> I tested it successfully on cubieboard 1GB, on top of kernel 3.10-rc3,
> nfsroot (debian wheezy)
> I also added in sun4i-a10-cubieboard.dts
> phy0: ethernet-phy at 0 {
>  reg = <1>;
> },
> like Emilio suggested.
> 
> running an iperf, there's some good perfs !
> iperf -s
> ------------------------------------------------------------
> Server listening on TCP port 5001
> TCP window size: 85.3 KByte (default)
> ------------------------------------------------------------
> [  4] local 192.168.1.10 port 5001 connected with 192.168.1.232 port 38169
> [ ID] Interval       Transfer     Bandwidth
> [  4]  0.0-10.0 sec   112 MBytes  94.1 Mbits/sec
> 
> That's great ! with this patchset, we can now run a server with a
> vanilla kernel ( who needs more that a serial port and ethernet,
> really ? ;) )
> 
> Tested-by: Richard Genoud <richard.genoud at gmail.com>

Thanks for testing this.

Did you look at the load while iperf was running? I guess we can expect
it to be pretty high since it runs without DMA.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From lee.jones at linaro.org  Thu May 30 04:12:11 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 30 May 2013 09:12:11 +0100
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <CACRpkda3d9_XvqRmy0nbWyri2xC3Qst2U2Sv=UDxV4w-UxK_JQ@mail.gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <20130529175741.GG21290@arwen.pp.htv.fi>
 <CACRpkda3d9_XvqRmy0nbWyri2xC3Qst2U2Sv=UDxV4w-UxK_JQ@mail.gmail.com>
Message-ID: <20130530081211.GA1915@gmail.com>

On Thu, 30 May 2013, Linus Walleij wrote:

> On Wed, May 29, 2013 at 7:57 PM, Felipe Balbi <balbi at ti.com> wrote:
> > On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
> >> For all ux500 based platforms the maximum number of end-points are used.
> >> Move this knowledge into the driver so we can relinquish the burden from
> >> platform data. This also removes quite a bit of complexity from the driver
> >> and will aid us when we come to enable the driver for Device Tree.
> >>
> >> Cc: Felipe Balbi <balbi at ti.com>
> >> Cc: linux-usb at vger.kernel.org
> >> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> >> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> >> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >
> > for drivers/usb/musb
> >
> > Acked-by: Felipe Balbi <balbi at ti.com>
> 
> Is that only for this patch 20/39 or also 21, 22 & 23?
> 
> Poke us if we should re-send them...

I read this as all patches in the series "for drivers/usb/musb".

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From shawn.guo at linaro.org  Thu May 30 04:16:36 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 16:16:36 +0800
Subject: [PATCH v5] tty: serial: add Freescale lpuart driver support
In-Reply-To: <1369893217-27809-1-git-send-email-b35083@freescale.com>
References: <1369893217-27809-1-git-send-email-b35083@freescale.com>
Message-ID: <20130530081633.GB2670@S2101-09.ap.freescale.net>

On Thu, May 30, 2013 at 01:53:37PM +0800, Jingchang Lu wrote:
> Add Freescale lpuart driver support. The lpuart device
> can be found on Vybrid VF610 and Layerscape LS-1 SoCs.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>



From ratbert.chuang at gmail.com  Thu May 30 04:15:26 2013
From: ratbert.chuang at gmail.com (Po-Yu Chuang)
Date: Thu, 30 May 2013 16:15:26 +0800
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <CANutaR_8jNDzPeyJ8PLZPS=yiZ8Ywmk08dR9vLcB2CpxuJac3A@mail.gmail.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com> <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com> <51A4FC08.3060906@ti.com>
 <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>
 <20130529085426.GA13095@mudshark.cambridge.arm.com>
 <CANutaR_8jNDzPeyJ8PLZPS=yiZ8Ywmk08dR9vLcB2CpxuJac3A@mail.gmail.com>
Message-ID: <CANutaR-e4L+wvfu6Fq7_Q_z9Ynwg8zZcEwzFhH5VxMGfkicYQw@mail.gmail.com>

On Wed, May 29, 2013 at 5:34 PM, Po-Yu Chuang <ratbert.chuang at gmail.com> wrote:
> Hi Will,
>
> On Wed, May 29, 2013 at 4:54 PM, Will Deacon <will.deacon at arm.com> wrote:
>> On Wed, May 29, 2013 at 03:14:58AM +0100, Po-Yu Chuang wrote:
>>> Will,
>>> I guess nobody noticed this because the MMU of later v7 processors
>>> fetches page table
>>> from D-cache. It even doesn't need to clean pmd to PoU.
>>
>> It does if it's UP. The walker is only guaranteed to read from L1 if you
>> have the multiprocessing extensions.
>
> Ya, I see.
>>
>> As for this function, looks like it's ok because it has precisely one
>> caller, so it might be worth prefixing it with some underscores to make it
>> clear that nobody else should be calling it!
>
> I am fine with that.
> Should I create a new patch?

Hi,

Does anyone have more comment about this?

Regards,
Po-Yu


From nicolas.ferre at atmel.com  Thu May 30 04:18:50 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 30 May 2013 10:18:50 +0200
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <51A68DC8.3090703@interlog.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
 <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
 <51A68DC8.3090703@interlog.com>
Message-ID: <51A70B6A.8060306@atmel.com>

On 30/05/2013 01:22, Douglas Gilbert :
> On 13-05-29 04:41 PM, Robert Nelson wrote:
>> On Wed, May 29, 2013 at 3:33 PM, Andrew Morton
>> <akpm at linux-foundation.org> wrote:
>>> On Thu, 23 May 2013 10:38:50 +0200 Johan Hovold <jhovold at gmail.com>
>>> wrote:
>>>
>>>> This is an update of the shadow-interrupt-mask series against
>>>> v3.10-rc2.
>>>>
>>>> I guess we need Atmel to confirm that all sam9x5 SoCs are indeed
>>>> affected. If not, then some probing mechanism as the one Doug suggested
>>>> could be implemented on top of (a subset of) these patches. What do you
>>>> say, Nicolas?
>>>>
>>>> Note that the first patch (adding a missing OF compile guard) could be
>>>> applied straight away.
>>>
>>> At this stage it is unclear to me how to proceed with patches 2-5.
>>
>> fyi:
>>
>> A version of these patches had been applied once before:
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0ef1594c017521ea89278e80fe3f80dafb17abde
>>
>>
>> But due to a few issues it was later reverted:
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=e24b0bfa2f0446ffaad2661040be23668133aef8
>>
>
> Strange life of a patch. Mine was the original, Johan Hovold
> objected and had it reverted. Johan then presented his first
> patch then v2. They got lost in the weeds.

No, they were not lost. No patch is ever lost and this thread is the proof.

> My hardware was still broken and this bug caused collateral
> damage. My original patch no longer applied to lk 3.10.0-rc1
> so I rewrote it, borrowing some of Johan's ideas and doing a
> probe time check for the broken RTC_IMR. That patch was
> presented about a week ago:
>    http://marc.info/?l=linux-arm-kernel&m=136917492531478&w=2
> The top of that post gives some more background.
>
> That prompted Johan to produce v3 of his patch which is the
> subject of this thread. I was hoping that Nicolas Ferre would
> comment or ack one of these patches. Still waiting.

Sure that all this did not progressed at the speed you expected. I 
understand that. But even if I did not answered in a timely manner, that 
does not mean that I didn't considered it and marked it as "things to be 
done before next merge window"...

So, today, too late, I gave my "Acked-by". Sorry for the delay. Let's 
still monitor the progress of this series upstream.

> I have a copy of the original, publicly released manual for
> the at91sam9g25 (a member of the at91sam9x5 family) marked
> "11032A?ATARM?27-Jul-11". It contains the following:
>    Errata
>    49.3.1
>      RTC: Interrupt Mask Register cannot be used
>           Interrupt Mask Register reading always returns 0.
>
> Both Rev B and Rev C of that manual drop that particular
> erratum. My g25 SoC-based subsystems come from an Atmel
> partner and still have the RTC IMR bug.

We already talked about this Douglas. Why are you saying this again. So, 
to summarize:

1/ each and every at91sam9x5 family SoC have and will probably always 
have this IMR bug (including 9g25 which is part of the family).

2/ you kindly reported the errata disappearing in the documentation. It 
is an error with document appearance which you probably noted. I have 
made the necessary actions to correct this. But here again, you have to 
be patient waiting for the datasheet's next revision.

Best regards,
-- 
Nicolas Ferre


From linus.walleij at linaro.org  Thu May 30 04:30:55 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:30:55 +0200
Subject: [PATCH 21/39] usb: musb: ux500: move the MUSB HDRC configuration
 into the driver
In-Reply-To: <1368611522-9984-22-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-22-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYOxOz_hGpijHhVeDJFg66j31CuDqA-cTmaJoJSJMoDqQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The MUSB HDRC configuration never changes between each of the ux500
> supported platforms, so there's little point passing it though platform
> data. If we set it in the driver instead, we can make good use of it
> when booting with either ATAGs or Device Tree.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied with Felipe's ACK.

Yours,
Linus Walleij


From lee.jones at linaro.org  Thu May 30 04:31:15 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 30 May 2013 09:31:15 +0100
Subject: [PATCH] ARM: ux500: Reduce PRCMU reg-names to shorter form for u8540
 DT
Message-ID: <1369902675-5170-1-git-send-email-lee.jones@linaro.org>

After some discussion and deliberation we have decided to only use the
short form of the PRCMU register names i.e. not mention the peripheral
in which the registers reside.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/ccu8540.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
index af4487f..12f0bc2 100644
--- a/arch/arm/boot/dts/ccu8540.dts
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -23,7 +23,7 @@
 	soc {
 		prcmu at 80157000 {
 			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
-			reg-names = "prcmu", "prcmu-tcpm-per4", "prcmu-tcdm-per4";
+			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 		};
 
 		uart at 80120000 {
-- 
1.7.10.4



From linus.walleij at linaro.org  Thu May 30 04:32:29 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:32:29 +0200
Subject: [PATCH 22/39] usb: musb: ux500: take the dma_mask from
 coherent_dma_mask
In-Reply-To: <1368611522-9984-23-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-23-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZo_ymcubrvm1k9+VKJq6ED-xOSv7V_Sry8ffhFB3RqyA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The dma_mask will always be the same as the coherent_dma_mask, so let's
> cut down on the platform_data burden and set it as such in the driver.
> This also saves us from supporting it separately when we come to enable
> this driver for Device Tree.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied with Felipe's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:34:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:34:00 +0200
Subject: [PATCH 23/39] usb: musb: ux500: harden checks for platform data
In-Reply-To: <1368611522-9984-24-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-24-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbCx4br+2VH7hoPBPUF6Xpb+WDu2kDxUQAGFJxEHk8ffg@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> In its current state, the ux500-musb driver uses platform data pointers
> blindly with no prior checking. If no platform data pointer is passed
> this will Oops the kernel. In this patch we ensure platform data and
> board data are present prior to using them.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied with Felipe's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:35:39 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:35:39 +0200
Subject: [PATCH 24/39] usb: musb: ux500: attempt to find channels by name
 before using pdata
In-Reply-To: <1368611522-9984-25-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-25-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYpY60FrbgMEpY2RftRN8iWca2SgzzUF=bRAk23doN_Lg@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> If we can ever get to a state where we can solely search for DMA channels
> by name, this will almost completely alleviate the requirement to pass
> copious amounts of information though platform data. Here we take the
> first step towards this. The next step will be to enable Device Tree
> complete with name<->event_line mapping.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: linux-usb at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied with Felipe's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:38:34 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:38:34 +0200
Subject: [PATCH 25/39] usb: musb: ux500: add device tree probing support
In-Reply-To: <1368611522-9984-26-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-26-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZE-i5v_B7CCVPVNpU+EgCx4D17mZ+OvwAHZXXDBdoi1w@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch will allow ux500-musb to be probed and configured solely from
> configuration found in Device Tree.
>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: linux-usb at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied with Felipe's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:42:46 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:42:46 +0200
Subject: [PATCH 26/39] ARM: ux500: Add an auxdata entry for MUSB for
 clock-name look-up
In-Reply-To: <1368611522-9984-27-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-27-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYzy-Nq5x=_tNweOTmTshkeswe0uk3c65bCOxFNCcYWZQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The recently DT:ed MUSB driver will require clock-name by device-name
> look-up capability, until common clk has is properly supported by the
> ux500 platform.
>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to my ux500-devicetree branch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:44:16 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:44:16 +0200
Subject: [PATCH 27/39] ARM: ux500: Remove ux500-musb platform registation
 when booting with DT
In-Reply-To: <1368611522-9984-28-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-28-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYm8PiQj++w_5=odvpZxOgBmjH4F9yPEFRhN+CGFEE48A@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Now the ux500-musb driver has been enabled for Device Tree, there is no
> requirement to register it from platform code.
>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch on top of the musb
stuff.

Yours,
Linus Walleij


From magnus.damm at gmail.com  Thu May 30 04:51:52 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 17:51:52 +0900
Subject: [PATCH 00/05] ARM: shmobile: r8a73a4 SMP and CPU Hotplug prototype v2
Message-ID: <20130530085152.24374.64208.sendpatchset@w520>

ARM: shmobile: r8a73a4 SMP and CPU Hotplug prototype v2

[PATCH 01/05] ARM: shmobile: r8a73a4 SMP prototype v1 (CA15 x 4)
[PATCH 02/05] ARM: shmobile: r8a73a4 CPU Hotplug prototype v1 (CA15 x 4)
[PATCH 03/05] ARM: shmobile: r8a73a4 CA15 setup WFE as NOP
[PATCH 04/05] ARM: shmobile: r8a73a4 SMP CA7 prototype (+ CA7 x 4)
[PATCH 05/05] ARM: shmobile: r8a73a4 CA7 setup arch timer

Here's V2 of r8a73a4 SMP prototype support. This time support for
both CA15 and CA7 is included.

It is worth noting that only prototype support for the actual SoC
is included here. It is included as SMP support, but since CA7 cores
perform differently compared to CA15 the system will not behave in a
deterministic way unless either big.LITTLE MP patches are used to
extend the scheduler or c-groups are used to separate CA15 and CA7.

All 8 cores boot up as expected but certainly needs more work.

Not-yet-Signed-off-by: Magnus Damm <damm at opensource.se>
---

 Written against linux.git 7b55eab81ecbbd44e76ac14c67479b82807c261b
 
 arch/arm/boot/dts/r8a73a4.dtsi                |   49 ++++
 arch/arm/mach-shmobile/Makefile               |    1 
 arch/arm/mach-shmobile/board-ape6evm.c        |    1 
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |    1 
 arch/arm/mach-shmobile/setup-r8a73a4.c        |    1 
 arch/arm/mach-shmobile/smp-r8a73a4.c          |  274 ++++++++++++++++++++++++-
 6 files changed, 321 insertions(+), 6 deletions(-)


From magnus.damm at gmail.com  Thu May 30 04:52:01 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 17:52:01 +0900
Subject: [PATCH 01/05] ARM: shmobile: r8a73a4 SMP prototype v1 (CA15 x 4)
In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520>
References: <20130530085152.24374.64208.sendpatchset@w520>
Message-ID: <20130530085201.24374.97084.sendpatchset@w520>

From: Magnus Damm <damm at opensource.se>

Add SMP prototype support for r8a73a4 by enabling
4 x Cortex-A15. This patch only adds support for
booting, see the incremental patch for CPU Hotplug.

Needs a rewrite to support more generic handling of
CPU core power domains. Not ready for merge.

Not-yet-Signed-off-by: Magnus Damm <damm at opensource.se>
---

 Developed and tested on top of v3.10-rc2

 arch/arm/boot/dts/r8a73a4.dtsi                |   21 +++++
 arch/arm/mach-shmobile/Makefile               |    1 
 arch/arm/mach-shmobile/board-ape6evm.c        |    1 
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |    1 
 arch/arm/mach-shmobile/setup-r8a73a4.c        |    1 
 arch/arm/mach-shmobile/smp-r8a73a4.c          |   89 +++++++++++++++++++++++++
 6 files changed, 114 insertions(+)

--- 0003/arch/arm/boot/dts/r8a73a4.dtsi
+++ work/arch/arm/boot/dts/r8a73a4.dtsi	2013-05-22 13:21:21.000000000 +0900
@@ -25,6 +25,27 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+			clock-frequency = <1500000000>;
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+			clock-frequency = <1500000000>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+			clock-frequency = <1500000000>;
+		};
 	};
 
 	gic: interrupt-controller at f1001000 {
--- 0001/arch/arm/mach-shmobile/Makefile
+++ work/arch/arm/mach-shmobile/Makefile	2013-05-22 13:21:21.000000000 +0900
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.
 # SMP objects
 smp-y				:= platsmp.o headsmp.o
 smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A73A4)	+= smp-r8a73a4.o
 smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o headsmp-scu.o
 smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o headsmp-scu.o
 
--- 0001/arch/arm/mach-shmobile/board-ape6evm.c
+++ work/arch/arm/mach-shmobile/board-ape6evm.c	2013-05-22 13:21:51.000000000 +0900
@@ -87,6 +87,7 @@ static const char *ape6evm_boards_compat
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
+	.smp		= smp_ops(r8a73a4_smp_ops),
 	.init_irq	= irqchip_init,
 	.init_time	= shmobile_timer_init,
 	.init_machine	= ape6evm_add_standard_devices,
--- 0001/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ work/arch/arm/mach-shmobile/include/mach/r8a73a4.h	2013-05-22 13:21:21.000000000 +0900
@@ -4,5 +4,6 @@
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
+extern struct smp_operations r8a73a4_smp_ops;
 
 #endif /* __ASM_R8A73A4_H__ */
--- 0001/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ work/arch/arm/mach-shmobile/setup-r8a73a4.c	2013-05-22 13:21:44.000000000 +0900
@@ -194,6 +194,7 @@ static const char *r8a73a4_boards_compat
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
+	.smp		= smp_ops(r8a73a4_smp_ops),
 	.init_irq	= irqchip_init,
 	.init_machine	= r8a73a4_add_standard_devices_dt,
 	.init_time	= shmobile_timer_init,
--- /dev/null
+++ work/arch/arm/mach-shmobile/smp-r8a73a4.c	2013-05-22 13:21:21.000000000 +0900
@@ -0,0 +1,89 @@
+/*
+ * SMP support for r8a73a4
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Takashi Yoshii <takashi.yoshii.ze at renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+
+#define SYSC	0xe6180000
+#define CA15BAR	0x6020
+#define RESCNT	0x801c
+
+#define APMU	0xe6150000
+#define CA15WUPCR 0x2010
+
+#define MERAM	0xe8080000
+#define CCI_BASE	0xf0190000
+#define CCI_SLAVE3	0x4000
+#define CCI_SNOOP	0x0000
+#define CCI_STATUS	0x000c
+
+static void __init r8a73a4_smp_prepare_cpus(unsigned int max_cpus)
+{
+	u32 bar;
+	void __iomem *p;
+
+	/* MERAM for jump stub, because BAR requires 256KB aligned address */
+	p = ioremap_nocache(MERAM, 16);
+	memcpy(p, shmobile_secondary_vector, 16);
+	iounmap(p);
+
+	flush_cache_louis();
+
+	/* setup reset vector and disable reset */
+	p = ioremap_nocache(SYSC, 0x9000);
+	bar = (MERAM >> 8) & 0xfffffc00;
+	__raw_writel(bar, p + CA15BAR);
+	__raw_writel(bar | 0x10, p + CA15BAR);
+	__raw_writel(__raw_readl(p + RESCNT) & ~(1 << 10), p + RESCNT);
+	iounmap(p);
+
+	/* enable snoop and DVM */
+	p = ioremap_nocache(CCI_BASE, 0x8000);
+	__raw_writel(3, p + CCI_SLAVE3 + CCI_SNOOP);	/* ca15 */
+	while (__raw_readl(p + CCI_STATUS))
+		/* wait for pending bit low */;
+	iounmap(p);
+}
+
+static int __cpuinit r8a73a4_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	void __iomem *p;
+
+	/* wake up CPU core */
+	p = ioremap_nocache(APMU, 0x3000);
+	__raw_writel(1 << (cpu_logical_map(cpu) & 3), p + CA15WUPCR);
+	iounmap(p);
+
+	return 0;
+}
+
+struct smp_operations r8a73a4_smp_ops __initdata = {
+	.smp_prepare_cpus	= r8a73a4_smp_prepare_cpus,
+	.smp_boot_secondary	= r8a73a4_boot_secondary,
+};


From magnus.damm at gmail.com  Thu May 30 04:52:11 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 17:52:11 +0900
Subject: [PATCH 02/05] ARM: shmobile: r8a73a4 CPU Hotplug prototype v1 (CA15 x
 4)
In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520>
References: <20130530085152.24374.64208.sendpatchset@w520>
Message-ID: <20130530085211.24374.15664.sendpatchset@w520>

From: Magnus Damm <damm at opensource.se>

Add CPU Hotplug prototype support for 4 x Cortex-A15
included in r8a73a4.

Needs a rewrite to support more generic handling of
CPU core power domains. Not ready for merge.

Not-yet-Signed-off-by: Magnus Damm <damm at opensource.se>
---

 Developed and tested on top of v3.10-rc2, depends on
 "[PATCH] ARM: shmobile: r8a73a4 SMP prototype v1 (CA15 x 4)"

 arch/arm/mach-shmobile/smp-r8a73a4.c |   88 ++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

--- 0005/arch/arm/mach-shmobile/smp-r8a73a4.c
+++ work/arch/arm/mach-shmobile/smp-r8a73a4.c	2013-05-22 13:34:18.000000000 +0900
@@ -36,6 +36,8 @@
 
 #define APMU	0xe6150000
 #define CA15WUPCR 0x2010
+#define CA15PSTR 0x2040
+#define CA15CPUNCR(n) (0x2100 + (0x10 * (n))) 
 
 #define MERAM	0xe8080000
 #define CCI_BASE	0xf0190000
@@ -83,7 +85,93 @@ static int __cpuinit r8a73a4_boot_second
 	return 0;
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static int r8a73a4_cpu_kill(unsigned int cpu)
+{
+	void __iomem *p;
+	int ret = 0;
+	int k;
+
+	/* this function is running on another CPU than the offline target,
+	 * here all we need to do is to wait for the SoC to enter sleep mode.
+	 */
+	p = ioremap_nocache(APMU, 0x3000);
+	for (k = 0; k < 1000; k++) {
+		if (((__raw_readl(p + CA15PSTR) >> (cpu * 4)) & 0x03) == 3) {
+			ret = 1;
+			break;
+		}
+
+		mdelay(1);
+	}
+	iounmap(p);
+
+	return ret;
+}
+
+/* nicked from arch/arm/mach-exynos/hotplug.c */
+static inline void cpu_enter_lowpower_a15(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C)
+	  : "cc");
+
+	flush_cache_louis();
+
+	asm volatile(
+	/*
+	* Turn off coherency
+	*/
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	: "=&r" (v)
+	: "Ir" (0x40)
+	: "cc");
+
+	isb();
+	dsb();
+}
+
+static int r8a73a4_do_idle_core_standby(unsigned long unused)
+{
+	cpu_do_idle(); /* WFI triggers Core Standby */
+	return 0;
+}
+
+static void r8a73a4_cpu_die(unsigned int cpu)
+{
+	void __iomem *p;
+
+	/* hardware shutdown code running on the CPU that is being offlined */
+
+	/* select CPU shutdown mode */
+	p = ioremap_nocache(APMU, 0x3000);
+	__raw_writel(3, p + CA15CPUNCR(cpu)); /* CA15 Core Standby */
+	iounmap(p);
+
+	cpu_enter_lowpower_a15();
+	cpu_suspend(0, r8a73a4_do_idle_core_standby); /* really needed? */
+}
+
+static int r8a73a4_cpu_disable(unsigned int cpu)
+{
+	return 0; /* hotplug of any CPU is tested OK */
+}
+#endif
+
 struct smp_operations r8a73a4_smp_ops __initdata = {
 	.smp_prepare_cpus	= r8a73a4_smp_prepare_cpus,
 	.smp_boot_secondary	= r8a73a4_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_kill		= r8a73a4_cpu_kill,
+	.cpu_die		= r8a73a4_cpu_die,
+	.cpu_disable		= r8a73a4_cpu_disable,
+#endif
 };


From magnus.damm at gmail.com  Thu May 30 04:52:20 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 17:52:20 +0900
Subject: [PATCH 03/05] ARM: shmobile: r8a73a4 CA15 setup WFE as NOP
In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520>
References: <20130530085152.24374.64208.sendpatchset@w520>
Message-ID: <20130530085220.24374.94574.sendpatchset@w520>

From: Magnus Damm <damm at opensource.se>

Configure CA15 included in r8a73a4 to treat WFE as NOP.

This works around hardware issue found in APE6, needed
for CA7 cluster to work together with CA15 cluster.

Not-yet-Signed-off-by: Magnus Damm <damm at opensource.se>
---

 arch/arm/mach-shmobile/smp-r8a73a4.c |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

--- 0006/arch/arm/mach-shmobile/smp-r8a73a4.c
+++ work/arch/arm/mach-shmobile/smp-r8a73a4.c	2013-05-22 14:16:59.000000000 +0900
@@ -45,6 +45,20 @@
 #define CCI_SNOOP	0x0000
 #define CCI_STATUS	0x000c
 
+static inline void r8a73a4_execute_wfe_as_nop(void)
+{
+	unsigned int v;
+
+	/* set bit 7 in ACTLR */
+	asm volatile(
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, #0x40\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)
+	  :
+	  : "cc");
+}
+
 static void __init r8a73a4_smp_prepare_cpus(unsigned int max_cpus)
 {
 	u32 bar;
@@ -71,6 +85,8 @@ static void __init r8a73a4_smp_prepare_c
 	while (__raw_readl(p + CCI_STATUS))
 		/* wait for pending bit low */;
 	iounmap(p);
+
+	r8a73a4_execute_wfe_as_nop();
 }
 
 static int __cpuinit r8a73a4_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -85,6 +101,13 @@ static int __cpuinit r8a73a4_boot_second
 	return 0;
 }
 
+static void __cpuinit r8a73a4_secondary_init(unsigned int cpu)
+{
+	/* CA15 need SW workaround */
+	if (cpu_logical_map(cpu) < 4)
+		r8a73a4_execute_wfe_as_nop();
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static int r8a73a4_cpu_kill(unsigned int cpu)
 {
@@ -169,6 +192,7 @@ static int r8a73a4_cpu_disable(unsigned
 struct smp_operations r8a73a4_smp_ops __initdata = {
 	.smp_prepare_cpus	= r8a73a4_smp_prepare_cpus,
 	.smp_boot_secondary	= r8a73a4_boot_secondary,
+	.smp_secondary_init	= r8a73a4_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= r8a73a4_cpu_kill,
 	.cpu_die		= r8a73a4_cpu_die,


From magnus.damm at gmail.com  Thu May 30 04:52:30 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 17:52:30 +0900
Subject: [PATCH 04/05] ARM: shmobile: r8a73a4 SMP CA7 prototype (+ CA7 x 4)
In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520>
References: <20130530085152.24374.64208.sendpatchset@w520>
Message-ID: <20130530085230.24374.41041.sendpatchset@w520>

From: Magnus Damm <damm at opensource.se>

Prototype code to enable 4 x CA7 found in r8a73a4.

To test on APE6EVM boot with maxcpus=4 and use CPU Hotplug
for boot and shut down. Not ready for merge.

Not-yet-Signed-off-by: Magnus Damm <damm at opensource.se>
---

 arch/arm/boot/dts/r8a73a4.dtsi       |   28 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/smp-r8a73a4.c |   36 +++++++++++++++++++++++++++++-----
 2 files changed, 59 insertions(+), 5 deletions(-)

--- 0002/arch/arm/boot/dts/r8a73a4.dtsi
+++ work/arch/arm/boot/dts/r8a73a4.dtsi	2013-05-30 16:13:11.000000000 +0900
@@ -46,6 +46,34 @@
 			reg = <3>;
 			clock-frequency = <1500000000>;
 		};
+
+		cpu4: cpu at 4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			clock-frequency = <1000000000>; 
+		};
+
+		cpu5: cpu at 5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			clock-frequency = <1000000000>; 
+		};
+
+		cpu6: cpu at 6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			clock-frequency = <1000000000>; 
+		};
+
+		cpu7: cpu at 7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			clock-frequency = <1000000000>; 
+		};
 	};
 
 	gic: interrupt-controller at f1001000 {
--- 0004/arch/arm/mach-shmobile/smp-r8a73a4.c
+++ work/arch/arm/mach-shmobile/smp-r8a73a4.c	2013-05-30 16:18:40.000000000 +0900
@@ -31,17 +31,22 @@
 #include <asm/smp_plat.h>
 
 #define SYSC	0xe6180000
+#define CA7BAR	0x4020
 #define CA15BAR	0x6020
 #define RESCNT	0x801c
 
 #define APMU	0xe6150000
+#define CA7WUPCR 0x1010
 #define CA15WUPCR 0x2010
+#define CA7PSTR	0x1040
 #define CA15PSTR 0x2040
+#define CA7CPUNCR(n) (0x1100 + (0x10 * (n))) 
 #define CA15CPUNCR(n) (0x2100 + (0x10 * (n))) 
 
 #define MERAM	0xe8080000
 #define CCI_BASE	0xf0190000
 #define CCI_SLAVE3	0x4000
+#define CCI_SLAVE4	0x5000
 #define CCI_SNOOP	0x0000
 #define CCI_STATUS	0x000c
 
@@ -75,13 +80,16 @@ static void __init r8a73a4_smp_prepare_c
 	p = ioremap_nocache(SYSC, 0x9000);
 	bar = (MERAM >> 8) & 0xfffffc00;
 	__raw_writel(bar, p + CA15BAR);
+	__raw_writel(bar, p + CA7BAR);
 	__raw_writel(bar | 0x10, p + CA15BAR);
+	__raw_writel(bar | 0x10, p + CA7BAR);
 	__raw_writel(__raw_readl(p + RESCNT) & ~(1 << 10), p + RESCNT);
 	iounmap(p);
 
 	/* enable snoop and DVM */
 	p = ioremap_nocache(CCI_BASE, 0x8000);
 	__raw_writel(3, p + CCI_SLAVE3 + CCI_SNOOP);	/* ca15 */
+	__raw_writel(3, p + CCI_SLAVE4 + CCI_SNOOP);	/* ca7 */
 	while (__raw_readl(p + CCI_STATUS))
 		/* wait for pending bit low */;
 	iounmap(p);
@@ -92,10 +100,14 @@ static void __init r8a73a4_smp_prepare_c
 static int __cpuinit r8a73a4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	void __iomem *p;
+	int cluster_cpu = cpu_logical_map(cpu) & 3;
 
 	/* wake up CPU core */
 	p = ioremap_nocache(APMU, 0x3000);
-	__raw_writel(1 << (cpu_logical_map(cpu) & 3), p + CA15WUPCR);
+	if (cpu_logical_map(cpu) < 4) 
+		__raw_writel(1 << cluster_cpu, p + CA15WUPCR);
+	else
+		__raw_writel(1 << cluster_cpu, p + CA7WUPCR);
 	iounmap(p);
 
 	return 0;
@@ -112,6 +124,7 @@ static void __cpuinit r8a73a4_secondary_
 static int r8a73a4_cpu_kill(unsigned int cpu)
 {
 	void __iomem *p;
+	int offs;
 	int ret = 0;
 	int k;
 
@@ -120,9 +133,18 @@ static int r8a73a4_cpu_kill(unsigned int
 	 */
 	p = ioremap_nocache(APMU, 0x3000);
 	for (k = 0; k < 1000; k++) {
-		if (((__raw_readl(p + CA15PSTR) >> (cpu * 4)) & 0x03) == 3) {
-			ret = 1;
-			break;
+		if (cpu < 4) { /* CA15 Core Standby */
+			offs = cpu * 4;
+			if (((__raw_readl(p + CA15PSTR) >> offs) & 0x03) == 3) {
+				ret = 1;
+				break;
+			}
+		} else { /* CA7 Core Standby */
+			offs = (cpu - 4) * 4;
+			if (((__raw_readl(p + CA7PSTR) >> offs) & 0x03) == 3) {
+				ret = 1;
+				break;
+			}
 		}
 
 		mdelay(1);
@@ -176,7 +198,11 @@ static void r8a73a4_cpu_die(unsigned int
 
 	/* select CPU shutdown mode */
 	p = ioremap_nocache(APMU, 0x3000);
-	__raw_writel(3, p + CA15CPUNCR(cpu)); /* CA15 Core Standby */
+	if (cpu < 4)
+		__raw_writel(3, p + CA15CPUNCR(cpu)); /* CA15 Core Standby */
+	else
+		__raw_writel(3, p + CA7CPUNCR(cpu - 4)); /* CA7 Core Standby */
+
 	iounmap(p);
 
 	cpu_enter_lowpower_a15();


From magnus.damm at gmail.com  Thu May 30 04:52:40 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 30 May 2013 17:52:40 +0900
Subject: [PATCH 05/05] ARM: shmobile: r8a73a4 CA7 setup arch timer
In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520>
References: <20130530085152.24374.64208.sendpatchset@w520>
Message-ID: <20130530085240.24374.65991.sendpatchset@w520>

From: Magnus Damm <damm at opensource.se>

Setup the CA7 arch timer in r8a73a4 at boot up. Thanks to
Kevin Bracey at Renesas Mobile for initial implementation.

We need to discuss if some of this can be moved into the
common arch timer driver or not. It may also need to be
shared with R-Car H2. So this is not ready for merge.

Without this patch the interrupt count for the per-cpu arch
timers for CA7 are stuck at zero.

Not-yet-Signed-off-by: Magnus Damm <damm at opensource.se>
---

 arch/arm/mach-shmobile/smp-r8a73a4.c |   37 +++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

--- 0005/arch/arm/mach-shmobile/smp-r8a73a4.c
+++ work/arch/arm/mach-shmobile/smp-r8a73a4.c	2013-05-30 17:13:01.000000000 +0900
@@ -50,6 +50,8 @@
 #define CCI_SNOOP	0x0000
 #define CCI_STATUS	0x000c
 
+#define CNTFID0	0xe6080020
+
 static inline void r8a73a4_execute_wfe_as_nop(void)
 {
 	unsigned int v;
@@ -64,6 +66,32 @@ static inline void r8a73a4_execute_wfe_a
 	  : "cc");
 }
 
+static u32 r8a73a4_arch_freq;
+
+static inline void r8a73a4_reset_arch_timer(void)
+{
+	/* Program CNTFRQ from the frequency table */
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (r8a73a4_arch_freq));
+
+	/* CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code
+	 */
+	asm volatile(
+	"cps	0x16				@ Monitor mode"
+	"mrc	p15, 0, r1, c1, c1, 0"
+	"orr	r0, r1, #1			@ Set SCR.NS (non-secure)"
+	"mcr	p15, 0, r0, c1, c1, 0"
+	"isb"
+	"mov	r0, #0"
+	"mcrr	p15, 4, r0, r0, c14		@ CNTVOFF"
+	"isb"
+	"mcr	p15, 0, r1, c1, c1, 0		@ Restore SCR"
+	"isb"
+	"cps	0x13				@ Back to SVC mode"
+	: : : "r0", "r1");
+}
+
 static void __init r8a73a4_smp_prepare_cpus(unsigned int max_cpus)
 {
 	u32 bar;
@@ -94,6 +122,11 @@ static void __init r8a73a4_smp_prepare_c
 		/* wait for pending bit low */;
 	iounmap(p);
 
+	/* Retrieve frequency to be able to later program CNTFRQ */
+	p = ioremap_nocache(CNTFID0, 16);
+	r8a73a4_arch_freq = __raw_readl(p);
+	iounmap(p);
+
 	r8a73a4_execute_wfe_as_nop();
 }
 
@@ -115,9 +148,11 @@ static int __cpuinit r8a73a4_boot_second
 
 static void __cpuinit r8a73a4_secondary_init(unsigned int cpu)
 {
-	/* CA15 need SW workaround */
+	/* CA15 and CA7 need SW workaround */
 	if (cpu_logical_map(cpu) < 4)
 		r8a73a4_execute_wfe_as_nop();
+	else
+		r8a73a4_reset_arch_timer();
 }
 
 #ifdef CONFIG_HOTPLUG_CPU


From linus.walleij at linaro.org  Thu May 30 04:45:51 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:45:51 +0200
Subject: [PATCH 28/39] ARM: ux500: Remove empty function
 u8500_of_init_devices()
In-Reply-To: <1368611522-9984-29-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-29-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZLjRv3RZk_+gpOJb-4UQcThxPshKeH1Cw-n96FY3250w@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> As promised, now all devices which resided in u8500_of_init_devices()
> have been enabled for Device Tree, we can completely remove it.
>
> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied on my ux500-dma40 branch.

And this is looking real good now!

Thanks!
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:47:38 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:47:38 +0200
Subject: [PATCH 29/39] dmaengine: ste_dma40: Use the BIT macro to replace
 ugly '(1 << x)'s
In-Reply-To: <1368611522-9984-30-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-30-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYgu3q8s=jMfQ1L-WEoDxRz4gQW6+jqZ8RTVvCAnLQKVA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The aim is to make the code that little more readable.
>
> Acked-by: Vinod Koul <vnod.koul at intel.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my ux500-dma40 branch.

Yours,
Linus Walleij


From jp.francois at cynove.com  Thu May 30 04:49:51 2013
From: jp.francois at cynove.com (jean-philippe francois)
Date: Thu, 30 May 2013 10:49:51 +0200
Subject: [PATCH v2 0/1] ARM: omap3: Fix regression in dpll4 child clock
 frequency setting.
Message-ID: <CAGGh5h3fjXkmsZDvQVGJ6ehdz7SUghhHcBU-rCcRq_7HQSWN6Q@mail.gmail.com>

Hi,

The following patch fixes a wrong container_of usage for omap3630.
All sub clock of dpll4 that do not use a reset value as divider are
affected.

For instance CAM_MCLK is 216 MHz instead of the asked 172,8 MHz
Any user of this clock is affected. This is the case for instance if
CAM_XCLKA is used to provide clock for an external camera.

Beyond wrong frequency setting, this is also a potential oops waiting
to bite any omap3isp user, since a wrong pointer is dereferenced, and
content of this pointer is used to do __raw_writel / __raw_readl.

v2 :
Follow Mike Turquette's comment and use clock framework instead of
directly accessing register.

Regards,
Jean-Philippe Fran?ois


From jp.francois at cynove.com  Thu May 30 04:50:27 2013
From: jp.francois at cynove.com (Jean-Philippe Francois)
Date: Thu, 30 May 2013 10:50:27 +0200
Subject: [PATCH v2 1/1] ARM : omap3 : fix wrong container_of in clock36xx.c
Message-ID: <1369903827-2025-1-git-send-email-jp.francois@cynove.com>

omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
have parent defined as clk_divider. Instead of using container_of to eventually get
to the register and directly mess with the divider, change freq via clk_set_rate, 
and let the clock framework toggle the divider value.
Tested with  3.9 on dm3730.

Signed-off-by: Jean-Philippe Fran??ois <jp.francois at cynove.com>

Index: b/arch/arm/mach-omap2/clock36xx.c
===================================================================
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -39,30 +39,25 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-	struct clk_hw_omap *parent;
-	struct clk_hw *parent_hw;
-	u32 dummy_v, orig_v, clksel_shift;
 	int ret;
 
 	/* Clear PWRDN bit of HSDIVIDER */
 	ret = omap2_dflt_clk_enable(clk);
 
-	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-	parent = to_clk_hw_omap(parent_hw);
-
-	/* Restore the dividers */
+	/* kick parent's clksel register after toggling PWRDN bit */
 	if (!ret) {
-		clksel_shift = __ffs(parent->clksel_mask);
-		orig_v = __raw_readl(parent->clksel_reg);
-		dummy_v = orig_v;
-
-		/* Write any other value different from the Read value */
-		dummy_v ^= (1 << clksel_shift);
-		__raw_writel(dummy_v, parent->clksel_reg);
-
-		/* Write the original divider */
-		__raw_writel(orig_v, parent->clksel_reg);
+		struct clk *parent = clk_get_parent(clk->clk);
+		unsigned long parent_rate = clk_get_rate(parent);
+		ret = clk_set_rate(parent, parent_rate/2);
+		if(ret)
+			goto badfreq;
+		ret = clk_set_rate(parent, parent_rate);
+		if(ret)
+			goto badfreq;
 	}
+	return ret;
 
+ badfreq :
+	omap2_dflt_clk_disable(clk);
 	return ret;
 }


From shawn.guo at linaro.org  Thu May 30 04:51:59 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 16:51:59 +0800
Subject: [PATCH v6 09/10] ASoC: fsl: Move fsl-ssi binding doc to sound/
In-Reply-To: <1369752478-30260-10-git-send-email-mpa@pengutronix.de>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-10-git-send-email-mpa@pengutronix.de>
Message-ID: <20130530085156.GC2670@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 04:47:57PM +0200, Markus Pargmann wrote:
> fsl-ssi was located in powerpc/fsl/ssi.txt. This is no powerpc specific
> device, so it should be moved to sound/ as it connects to differen audio
> codecs.
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> ---
>  .../devicetree/bindings/powerpc/fsl/ssi.txt        | 73 ----------------------
>  .../devicetree/bindings/sound/fsl,ssi.txt          | 73 ++++++++++++++++++++++

Please add -M to git format-patch command.

Shawn



From linus.walleij at linaro.org  Thu May 30 04:52:13 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:52:13 +0200
Subject: [PATCH 30/39] ARM: ux500: Replace ST-E's home-brew DMA direction
 definition with the generic one
In-Reply-To: <1368611522-9984-31-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-31-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZfw9ACS9=Nx9NuQqca_cvrdYwNOSWfpigMU1x94goZcA@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Vinod, I'm lacking your ACK on this patch, but have tentatively
queued it anyway. Maybe you missed it?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:54:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:54:12 +0200
Subject: [PATCH 31/39] dmaengine: ste_dma40: Replace ST-E's home-brew DMA
 direction defs with generic ones
In-Reply-To: <1368611522-9984-32-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-32-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZvdT6jb_dRteNnWDtaOY3jZ2DnRjb0SywOYbt7X51ksg@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied to my dma40 branch with Vinod's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:56:07 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:56:07 +0200
Subject: [PATCH 32/39] ARM: ux500: Remove recently unused
 stedma40_xfer_dir enums
In-Reply-To: <1368611522-9984-33-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-33-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY1XOGPz19ftH2yZFG6-_Ww3bVqrsDvRZGk60gzuu0Maw@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> We're now using the transfer direction definitions provided by the DMA
> sub-system, so the home-brew ones have become obsolete.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied, also missing Vinod's ACK on this, but it seems
it was implicitly ACKed in the discussion on patch 31.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 04:58:46 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 10:58:46 +0200
Subject: [PATCH 33/39] dmaengine: ste_dma40_ll: Use the BIT macro to
 replace ugly '(1 << x)'s
In-Reply-To: <1368611522-9984-34-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-34-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbzVSty9yX9sJxv6D9ADYj1qfB+z_rd3XUyq1W0sVcE3A@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The aim is to make the code that little more readable.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Vinod's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 05:01:27 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 11:01:27 +0200
Subject: [PATCH 34/39] dmaengine: ste_dma40: Convert data_width from
 register bit format to value
In-Reply-To: <1368611522-9984-35-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-35-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ6bijvD1S+YL2W+8R_DVGrmPshiMVigg7iK4zen8r57g@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> When a DMA client requests and configures a DMA channel, it requests
> data_width in Bytes. The DMA40 driver then swiftly converts it over to
> the necessary register bit value. Unfortunately, for any subsequent
> calculations we have to shift '1' by the bit pattern (1 << data_width)
> times to make any sense of it.
>
> This patch flips the semantics on its head and only converts the value
> to its respective register bit pattern when writing to registers. This
> way we can use the true data_width (in Bytes) value.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with what I interpret as Vinod's ACK
("okay..." statement on last reply.)

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 05:04:23 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 11:04:23 +0200
Subject: [PATCH 35/39] dmaengine: ste_dma40_ll: Replace meaningless
 register set with comment
In-Reply-To: <1368611522-9984-36-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-36-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbXVd7k9rzb-OKUmnW_9J+jWYhz=AjO09_Ymvd2_DOVcQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Unsure of the author's intentions, rather than just removing the nop,
> we're replacing it with a comment containing the possible intention
> of the statement OR:ing with 0.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Tentatively applied. Missing Vinod's ACK.

Yours,
Linus Walleij


From arno at natisbad.org  Thu May 30 05:06:08 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Thu, 30 May 2013 11:06:08 +0200
Subject: [PATCH v5 12/13] ARM: kirkwood: remove redundant DT board files
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-13-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <8738t4q1kv.fsf@natisbad.org>

Hi Jason and Sebastian,

Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> writes:

> With DT support for mv643xx_eth board specific init for some boards now
> is unneccessary. Remove those board files, Kconfig entries, and
> corresponding entries in kirkwood_defconfig.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
> the lock-up is not caused by accessing clock gating registers but rather
> non-existent device registers. This will be addressed by dtsi separation
> for kirkwood and bobcat SoC variants.
>
> Changelog:
> v3->v4:
> - remove more boards that don't require board specific setup
>
> Cc: David Miller <davem at davemloft.net>
> Cc: Lennert Buytenhek <buytenh at wantstofly.org>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> Cc: netdev at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linuxppc-dev at lists.ozlabs.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/configs/kirkwood_defconfig           |   16 ----
>  arch/arm/mach-kirkwood/Kconfig                |  117 -------------------------
>  arch/arm/mach-kirkwood/Makefile               |   16 ----
>  arch/arm/mach-kirkwood/board-dnskw.c          |    7 --
>  arch/arm/mach-kirkwood/board-dockstar.c       |   32 -------
>  arch/arm/mach-kirkwood/board-dreamplug.c      |   35 --------
>  arch/arm/mach-kirkwood/board-dt.c             |   62 +------------
>  arch/arm/mach-kirkwood/board-goflexnet.c      |   34 -------
>  arch/arm/mach-kirkwood/board-guruplug.c       |   33 -------
>  arch/arm/mach-kirkwood/board-ib62x0.c         |   29 ------
>  arch/arm/mach-kirkwood/board-iconnect.c       |   10 ---
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   34 -------
>  arch/arm/mach-kirkwood/board-km_kirkwood.c    |   44 ----------
>  arch/arm/mach-kirkwood/board-lsxl.c           |   16 ----
>  arch/arm/mach-kirkwood/board-mplcec4.c        |   14 ---
>  arch/arm/mach-kirkwood/board-ns2.c            |   35 --------
>  arch/arm/mach-kirkwood/board-openblocks_a6.c  |   26 ------
>  arch/arm/mach-kirkwood/board-readynas.c       |    6 --

Just a stupid note: With Thomas ongoing work to get mvebu-pcie driver in
place and enabled for kirkwood, some boards setup files will also lose
their pcie init routines, which may allow you to kill those additonal
files soon.

For instance 6bd98481ab34 (arm: kirkwood: NETGEAR ReadyNAS Duo v2 init
PCIe via DT) currently sitting in jcooper/mvebu/pcie_kirkwood removes
the PCIE init routine in board-readynas.c, and yours remove ge00
init. With both applied, the whole file can go away.

AFAICT, this may be the case soon for:

 arch/arm/mach-kirkwood/board-iconnect.c   (36e5722089)
 arch/arm/mach-kirkwood/board-mplcec4.c    (9470fbfb8d)
 arch/arm/mach-kirkwood/board-nsa310.c     (40fa8e5da2)
 arch/arm/mach-kirkwood/board-readynas.c   (6bd98481ab)
 arch/arm/mach-kirkwood/board-ts219.c      (259e234608)

Anyway, thanks for this work Sebastian.

Cheers,

a+


From linus.walleij at linaro.org  Thu May 30 05:06:07 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 11:06:07 +0200
Subject: [PATCH 36/39] dmaengine: ste_dma40: Allow memcpy channels to be
 configured from DT
In-Reply-To: <1368611522-9984-37-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-37-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda1LOfPyzQRAwChSH9WtcCFnLNfFa5kp=8JWX0x7ioj+g@mail.gmail.com>

On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:

> At this moment in time the memcpy channels which can be used by the D40
> are fixed, as each supported platform in Mainline uses the same ones.
> However, platforms do exist which don't follow this convention, so
> these will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Vinod's ACK.

Yours,
Linus Walleij


From sebastian.hesselbarth at gmail.com  Thu May 30 05:08:14 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 30 May 2013 11:08:14 +0200
Subject: [PATCH v5 12/13] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <8738t4q1kv.fsf@natisbad.org>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-13-git-send-email-sebastian.hesselbarth@gmail.com>
 <8738t4q1kv.fsf@natisbad.org>
Message-ID: <51A716FE.9040909@gmail.com>

On 05/30/13 11:06, Arnaud Ebalard wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> writes:
>> With DT support for mv643xx_eth board specific init for some boards now
>> is unneccessary. Remove those board files, Kconfig entries, and
>> corresponding entries in kirkwood_defconfig.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
...
> Just a stupid note: With Thomas ongoing work to get mvebu-pcie driver in
> place and enabled for kirkwood, some boards setup files will also lose
> their pcie init routines, which may allow you to kill those additonal
> files soon.
>
> For instance 6bd98481ab34 (arm: kirkwood: NETGEAR ReadyNAS Duo v2 init
> PCIe via DT) currently sitting in jcooper/mvebu/pcie_kirkwood removes
> the PCIE init routine in board-readynas.c, and yours remove ge00
> init. With both applied, the whole file can go away.
>
> AFAICT, this may be the case soon for:
>
>   arch/arm/mach-kirkwood/board-iconnect.c   (36e5722089)
>   arch/arm/mach-kirkwood/board-mplcec4.c    (9470fbfb8d)
>   arch/arm/mach-kirkwood/board-nsa310.c     (40fa8e5da2)
>   arch/arm/mach-kirkwood/board-readynas.c   (6bd98481ab)
>   arch/arm/mach-kirkwood/board-ts219.c      (259e234608)
>
> Anyway, thanks for this work Sebastian.

Arnaud,

I already realized this when merging Jason's recent PRs and put
mv643xx_eth patches on top. I am aware of it but as ARM part of
mv643xx_eth will be delayed until net part surfaces, we have
plenty of time to react on current updates to mach-kirkwood
boards.

Sebastian



From p.zabel at pengutronix.de  Thu May 30 05:08:48 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Thu, 30 May 2013 11:08:48 +0200
Subject: [PATCH v7] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <51A68CF8.7000303@wwwdotorg.org>
References: <1369753575-9818-1-git-send-email-p.zabel@pengutronix.de>
 <51A68CF8.7000303@wwwdotorg.org>
Message-ID: <1369904928.24693.6.camel@pizza.hi.pengutronix.de>

Hi Stephen,

Am Mittwoch, den 29.05.2013, 17:19 -0600 schrieb Stephen Warren:
> On 05/28/2013 09:06 AM, Philipp Zabel wrote:
> > This driver implements a reset controller device that toggle a gpio
> > connected to a reset pin of a peripheral IC. The delay between assertion
> > and de-assertion of the reset signal can be configured via device tree.
> 
> > diff --git a/drivers/reset/gpio-reset.c b/drivers/reset/gpio-reset.c
> 
> > +static void __gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
> 
> Nit: Technically I think __ is a reserved name-space, so you shouldn't
> prefix "user-level" (rather than libc/similar) symbols with it, but it's
> not a big deal.

I'll s/__//.

> > +static int gpio_reset_probe(struct platform_device *pdev)
> 
> > +	if (of_gpio_named_count(np, "reset-gpios") != 1)
> > +		return -EINVAL;
> 
> Should that error-path (and the path for of_property_read_u32() failure)
> include a dev_err() like some already do, so it's obvious what the
> failure is?

For reset-gpios, yes. reset-delay-us is marked as optional in the
bindings.

> > +	reset_controller_register(&drvdata->rcdev);
> > +
> > +	platform_set_drvdata(pdev, drvdata);
> 
> It might be better to set the drvdata right after it's been allocated.
> It perhaps doesn't matter much here, but if the reset controller core
> ever starts calling into the registered device inside the call to
> reset_controller_register(), then there might be a problem.

Alright. I'll move ist above the reset_controller_register() call.

> Aside from those minor issues,
> Reviewed-by: Stephen Warren <swarren at nvidia.com>

thanks
Philipp



From p.zabel at pengutronix.de  Thu May 30 05:09:00 2013
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Thu, 30 May 2013 11:09:00 +0200
Subject: [PATCH v8] reset: Add driver for gpio-controlled reset pins
Message-ID: <1369904940-716-1-git-send-email-p.zabel@pengutronix.de>

This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Reviewed-by: Stephen Warren <swarren at nvidia.com>
---
Changes since v7:
 - renamed __gpio_reset_set to gpio_reset_set
 - made delay_us signed, negative if reset-delay-us is not set
 - added error messages for reset-gpios and reset-delay-us misconfiguration
 - set drvdata before calling reset_controller_register
---
 .../devicetree/bindings/reset/gpio-reset.txt       |  35 +++++
 drivers/reset/Kconfig                              |  11 ++
 drivers/reset/Makefile                             |   1 +
 drivers/reset/gpio-reset.c                         | 174 +++++++++++++++++++++
 4 files changed, 221 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/gpio-reset.txt
 create mode 100644 drivers/reset/gpio-reset.c

diff --git a/Documentation/devicetree/bindings/reset/gpio-reset.txt b/Documentation/devicetree/bindings/reset/gpio-reset.txt
new file mode 100644
index 0000000..bca5348
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/gpio-reset.txt
@@ -0,0 +1,35 @@
+GPIO reset controller
+=====================
+
+A GPIO reset controller controls a single GPIO that is connected to the reset
+pin of a peripheral IC. Please also refer to reset.txt in this directory for
+common reset controller binding usage.
+
+Required properties:
+- compatible: Should be "gpio-reset"
+- reset-gpios: A gpio used as reset line. The gpio specifier for this property
+               depends on the gpio controller that provides the gpio.
+- #reset-cells: 0, see below
+
+Optional properties:
+- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for
+                  this duration to reset.
+- initially-in-reset: boolean. If not set, the initial state should be a
+                      deasserted reset line. If this property exists, the
+                      reset line should be kept in reset.
+
+example:
+
+sii902x_reset: gpio-reset {
+	compatible = "gpio-reset";
+	reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <10000>;
+	initially-in-reset;
+	#reset-cells = <0>;
+};
+
+/* Device with nRESET pin connected to GPIO5_0 */
+sii902x at 39 {
+	/* ... */
+	resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */
+};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..1a862df 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,14 @@ menuconfig RESET_CONTROLLER
 	  via GPIOs or SoC-internal reset controller modules.
 
 	  If unsure, say no.
+
+if RESET_CONTROLLER
+
+config RESET_GPIO
+	tristate "GPIO reset controller support"
+	depends on GPIOLIB && OF
+	help
+	  This driver provides support for reset lines that are controlled
+	  directly by GPIOs.
+
+endif
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f..b854f20 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_RESET_CONTROLLER) += core.o
+obj-$(CONFIG_RESET_GPIO) += gpio-reset.o
diff --git a/drivers/reset/gpio-reset.c b/drivers/reset/gpio-reset.c
new file mode 100644
index 0000000..5d2515a
--- /dev/null
+++ b/drivers/reset/gpio-reset.c
@@ -0,0 +1,174 @@
+/*
+ * GPIO Reset Controller driver
+ *
+ * Copyright 2013 Philipp Zabel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+
+struct gpio_reset_data {
+	struct reset_controller_dev rcdev;
+	unsigned int gpio;
+	bool active_low;
+	s32 delay_us;
+};
+
+static void gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
+{
+	struct gpio_reset_data *drvdata = container_of(rcdev,
+			struct gpio_reset_data, rcdev);
+	int value = asserted;
+
+	if (drvdata->active_low)
+		value = !value;
+
+	gpio_set_value(drvdata->gpio, value);
+}
+
+static int gpio_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct gpio_reset_data *drvdata = container_of(rcdev,
+			struct gpio_reset_data, rcdev);
+
+	if (drvdata->delay_us < 0)
+		return -ENOSYS;
+
+	gpio_reset_set(rcdev, 1);
+	udelay(drvdata->delay_us);
+	gpio_reset_set(rcdev, 0);
+
+	return 0;
+}
+
+static int gpio_reset_assert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	gpio_reset_set(rcdev, 1);
+
+	return 0;
+}
+
+static int gpio_reset_deassert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	gpio_reset_set(rcdev, 0);
+
+	return 0;
+}
+
+static struct reset_control_ops gpio_reset_ops = {
+	.reset = gpio_reset,
+	.assert = gpio_reset_assert,
+	.deassert = gpio_reset_deassert,
+};
+
+static int of_gpio_reset_xlate(struct reset_controller_dev *rcdev,
+			       const struct of_phandle_args *reset_spec)
+{
+	if (WARN_ON(reset_spec->args_count != 0))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int gpio_reset_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct gpio_reset_data *drvdata;
+	enum of_gpio_flags flags;
+	unsigned long gpio_flags;
+	bool initially_in_reset;
+	int ret;
+
+	drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
+	if (drvdata == NULL)
+		return -ENOMEM;
+
+	if (of_gpio_named_count(np, "reset-gpios") != 1) {
+		dev_err(&pdev->dev,
+			"reset-gpios property missing, or not a single gpio\n");
+		return -EINVAL;
+	}
+
+	drvdata->gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &flags);
+	if (drvdata->gpio == -EPROBE_DEFER) {
+		return drvdata->gpio;
+	} else if (!gpio_is_valid(drvdata->gpio)) {
+		dev_err(&pdev->dev, "invalid reset gpio: %d\n", drvdata->gpio);
+		return drvdata->gpio;
+	}
+
+	drvdata->active_low = flags & OF_GPIO_ACTIVE_LOW;
+
+	ret = of_property_read_u32(np, "reset-delay-us", &drvdata->delay_us);
+	if (ret < 0)
+		drvdata->delay_us = -1;
+	else if (drvdata->delay_us < 0)
+		dev_warn(&pdev->dev, "reset delay too high\n");
+
+	initially_in_reset = of_property_read_bool(np, "initially-in-reset");
+	if (drvdata->active_low ^ initially_in_reset)
+		gpio_flags = GPIOF_OUT_INIT_HIGH;
+	else
+		gpio_flags = GPIOF_OUT_INIT_LOW;
+
+	ret = devm_gpio_request_one(&pdev->dev, drvdata->gpio, gpio_flags, NULL);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to request gpio %d: %d\n",
+			drvdata->gpio, ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, drvdata);
+
+	drvdata->rcdev.of_node = np;
+	drvdata->rcdev.owner = THIS_MODULE;
+	drvdata->rcdev.nr_resets = 1;
+	drvdata->rcdev.ops = &gpio_reset_ops;
+	drvdata->rcdev.of_xlate = of_gpio_reset_xlate;
+	reset_controller_register(&drvdata->rcdev);
+
+	return 0;
+}
+
+static int gpio_reset_remove(struct platform_device *pdev)
+{
+	struct gpio_reset_data *drvdata = platform_get_drvdata(pdev);
+
+	reset_controller_unregister(&drvdata->rcdev);
+
+	return 0;
+}
+
+static struct of_device_id gpio_reset_dt_ids[] = {
+	{ .compatible = "gpio-reset" },
+	{ }
+};
+
+static struct platform_driver gpio_reset_driver = {
+	.probe = gpio_reset_probe,
+	.remove = gpio_reset_remove,
+	.driver = {
+		.name = "gpio-reset",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(gpio_reset_dt_ids),
+	},
+};
+
+module_platform_driver(gpio_reset_driver);
+
+MODULE_AUTHOR("Philipp Zabel <p.zabel at pengutronix.de>");
+MODULE_DESCRIPTION("gpio reset controller");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:gpio-reset");
+MODULE_DEVICE_TABLE(of, gpio_reset_dt_ids);
-- 
1.8.2.rc2



From will.deacon at arm.com  Thu May 30 05:09:49 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 30 May 2013 10:09:49 +0100
Subject: A bug about system call on ARM
In-Reply-To: <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
Message-ID: <20130530090949.GC7483@mudshark.cambridge.arm.com>

On Thu, May 30, 2013 at 02:41:42AM +0100, Wang, Yalin wrote:
> Hi  Will,

Hello,

> Have you received the log files?

Yep, and you seem to be completely correct: CPU0 ages the page from which
CPU1 just executed a system call, so we explode trying to load the swi
instruction in order to retrieve the immediate.

> And is there someone looking at this issue now ?

It's on my list, but I'm pretty busy right now and OABI-compat isn't high
priority. Are you actually running OABI binaries? If not, you can simply
turn that option off (in fact, a quick fix to this issue is to make that
depend on !SMP).

> This issue happened on Qcom Scorpoin CPUs,
> And  it just happened in our stability test occasionally .
> 
> If you have some patch for this issue,
> I can do the test for it .

I'll have a look at cooking something which uses an exception table entry
to rewind the PC and retry the system call. That's simpler than directly
injecting a user page fault from the system call path.

Will


From mpa at pengutronix.de  Thu May 30 05:10:54 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 11:10:54 +0200
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <20130529135342.GB29528@S2101-09.ap.freescale.net>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
 <20130529135342.GB29528@S2101-09.ap.freescale.net>
Message-ID: <20130530091054.GA31548@pengutronix.de>

On Wed, May 29, 2013 at 09:53:45PM +0800, Shawn Guo wrote:
> On Tue, May 28, 2013 at 04:47:49PM +0200, Markus Pargmann wrote:
> > Add devicetree support for this audio soc fabric driver.
> > 
> > platform_of_node and cpu_of_node are set according to the fsl,audmux
> > phandle.
> > 
> > This patch adds handling of ac97 reset functions according to fsl ac97
> > support. They are setup from here to avoid board specific code in the
> > generic fsl-ssi driver.
> > 
> > This patch changes the handling of pca100 boards from non-DT to DT only.
> > pcm043 is still handled without DT.
> > 
> > Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> > ---
> > 
> > Notes:
> >     Changes in v6:
> >      - phycore-ac97 now manages the ac97 reset functions of the boards using
> >        this combination of ssi-codec.
> >      - Removed preprocessor ifs for DT, non-DT distinction. pcm043 is now
> >        non-DT only and pca100 DT only.
> >     
> >     Changes in v4:
> >      - New property phytec,audmux to check which audmux setup should be
> >        executed. Checking for fsl,imx21-audmux and fsl,imx31-audmux.
> >     
> >     Changes in v3:
> >      - Add some more information in the commit message.
> >     
> >     Changes in v2:
> >      - Simplify the driver, by combining audmux port configurations. The
> >        audmux driver actually knows on which platform he is running and
> >        will return the appropriate error code if we use functions for
> >        another platform. So we don't need to have the knowledge about it
> >        in phycore-ac97 and can try both functions. This removes the need
> >        of different compatibilities and renames it to phycore-ac97.
> >      - Use a phandle for the cpu_dai link.
> >      - Add devicetree binding documentation.
> >      - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
> >     
> >     Changes in v2:
> >      - Simplify the driver, by combining audmux port configurations. The
> >        audmux driver actually knows on which platform he is running and
> >        will return the appropriate error code if we use functions for
> >        another platform. So we don't need to have the knowledge about it
> >        in phycore-ac97 and can try both functions. This removes the need
> >        of different compatibilities and renames it to imx27-ac97.
> >      - Use a phandle for the cpu_dai link.
> >      - Add devicetree binding documentation.
> >      - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
> > 
> >  .../bindings/sound/phytec,phycore-ac97.txt         |  14 ++
> >  sound/soc/fsl/phycore-ac97.c                       | 241 ++++++++++++++++++---
> >  2 files changed, 229 insertions(+), 26 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
> > new file mode 100644
> > index 0000000..41201ff
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
> > @@ -0,0 +1,14 @@
> > +Phytec phycore AC97
> > +
> > +Required properties:
> > +- compatible: "phytec,phycore-ac97"
> > +- phytec,ssi: A phandle to the ssi device that is connected to ac97.
> > +- phytec,audmux: A phandle to the audmux device.
> > +
> > +Example:
> > +
> > +sound {
> > +	compatible = "phytec,phycore-ac97";
> > +	phytec,ssi = <&ssi1>;
> > +	phytec,audmux = <&audmux>;
> > +};
> > diff --git a/sound/soc/fsl/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
> > index ae403c2..bf2c600 100644
> > --- a/sound/soc/fsl/phycore-ac97.c
> > +++ b/sound/soc/fsl/phycore-ac97.c
> > @@ -20,8 +20,14 @@
> >  #include <asm/mach-types.h>
> >  
> >  #include "imx-audmux.h"
> > +#include "fsl_ssi.h"
> > +
> > +#define DRV_NAME "phycore-audio-fabric"
> >  
> >  static struct snd_soc_card imx_phycore;
> > +static struct device_node *phycore_dai_cpu_node;
> > +static void (*phycore_ac97_reset) (struct snd_ac97 *ac97);
> > +static void (*phycore_ac97_warm_reset)(struct snd_ac97 *ac97);
> >  
> >  static struct snd_soc_ops imx_phycore_hifi_ops = {
> >  };
> > @@ -32,12 +38,12 @@ static struct snd_soc_dai_link imx_phycore_dai_ac97[] = {
> >  		.stream_name	= "HiFi",
> >  		.codec_dai_name		= "wm9712-hifi",
> >  		.codec_name	= "wm9712-codec",
> > -		.cpu_dai_name	= "imx-ssi.0",
> > -		.platform_name	= "imx-ssi.0",
> 
> I do not think these and phycore_ac97_plat_name changes are necessary,
> since of_node will always take precedence over name in match.

They are necessary, snd_soc_register_card returns with -EINVAL if both,
name and of_node, are set.

> 
> >  		.ops		= &imx_phycore_hifi_ops,
> >  	},
> >  };
> >  
> > +static const char phycore_ac97_plat_name[] = "imx-ssi.0";
> > +
> >  static struct snd_soc_card imx_phycore = {
> >  	.name		= "PhyCORE-ac97-audio",
> >  	.owner		= THIS_MODULE,
> > @@ -45,40 +51,52 @@ static struct snd_soc_card imx_phycore = {
> >  	.num_links	= ARRAY_SIZE(imx_phycore_dai_ac97),
> >  };
> >  
> > -static struct platform_device *imx_phycore_snd_ac97_device;
> > +static void phycore_ac97_imx21_audmux(void)
> > +{
> > +	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
> > +		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> > +		IMX_AUDMUX_V1_PCR_TFCSEL(3) |
> > +		IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
> > +		IMX_AUDMUX_V1_PCR_RXDSEL(3));
> > +	imx_audmux_v1_configure_port(3,
> > +		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> > +		IMX_AUDMUX_V1_PCR_TFCSEL(0) |
> > +		IMX_AUDMUX_V1_PCR_TFSDIR |
> > +		IMX_AUDMUX_V1_PCR_RXDSEL(0));
> > +}
> > +
> > +static void phycore_ac97_imx31_audmux(void)
> > +{
> > +	imx_audmux_v2_configure_port(3,
> > +		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> > +		IMX_AUDMUX_V2_PTCR_TFSEL(0) |
> > +		IMX_AUDMUX_V2_PTCR_TFSDIR,
> > +		IMX_AUDMUX_V2_PDCR_RXDSEL(0));
> > +	imx_audmux_v2_configure_port(0,
> > +		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> > +		IMX_AUDMUX_V2_PTCR_TCSEL(3) |
> > +		IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
> > +		IMX_AUDMUX_V2_PDCR_RXDSEL(3));
> > +}
> > +
> >  static struct platform_device *imx_phycore_snd_device;
> >  
> > +static struct platform_device *imx_phycore_snd_ac97_device;
> > +
> >  static int __init imx_phycore_init(void)
> >  {
> >  	int ret;
> >  
> > -	if (machine_is_pca100()) {
> > -		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
> > -			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> > -			IMX_AUDMUX_V1_PCR_TFCSEL(3) |
> > -			IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
> > -			IMX_AUDMUX_V1_PCR_RXDSEL(3));
> > -		imx_audmux_v1_configure_port(3,
> > -			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
> > -			IMX_AUDMUX_V1_PCR_TFCSEL(0) |
> > -			IMX_AUDMUX_V1_PCR_TFSDIR |
> > -			IMX_AUDMUX_V1_PCR_RXDSEL(0));
> > -	} else if (machine_is_pcm043()) {
> > -		imx_audmux_v2_configure_port(3,
> > -			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> > -			IMX_AUDMUX_V2_PTCR_TFSEL(0) |
> > -			IMX_AUDMUX_V2_PTCR_TFSDIR,
> > -			IMX_AUDMUX_V2_PDCR_RXDSEL(0));
> > -		imx_audmux_v2_configure_port(0,
> > -			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
> > -			IMX_AUDMUX_V2_PTCR_TCSEL(3) |
> > -			IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
> > -			IMX_AUDMUX_V2_PDCR_RXDSEL(3));
> > +	if (machine_is_pcm043()) {
> > +		phycore_ac97_imx31_audmux();
> >  	} else {
> >  		/* return happy. We might run on a totally different machine */
> >  		return 0;
> >  	}
> >  
> > +	imx_phycore_dai_ac97[0].cpu_dai_name = phycore_ac97_plat_name;
> > +	imx_phycore_dai_ac97[0].platform_name = phycore_ac97_plat_name;
> > +
> >  	imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
> >  	if (!imx_phycore_snd_ac97_device)
> >  		return -ENOMEM;
> > @@ -108,18 +126,189 @@ fail2:
> >  	platform_device_del(imx_phycore_snd_ac97_device);
> >  fail1:
> >  	platform_device_put(imx_phycore_snd_ac97_device);
> > +	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
> > +	imx_phycore_dai_ac97[0].platform_name = NULL;
> >  	return ret;
> >  }
> >  
> >  static void __exit imx_phycore_exit(void)
> >  {
> > +	if (!machine_is_pcm043())
> > +		return;
> > +
> >  	platform_device_unregister(imx_phycore_snd_device);
> >  	platform_device_unregister(imx_phycore_snd_ac97_device);
> > +
> > +	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
> > +	imx_phycore_dai_ac97[0].platform_name = NULL;
> >  }
> >  
> >  late_initcall(imx_phycore_init);
> >  module_exit(imx_phycore_exit);
> >  
> > +
> > +static const struct of_device_id imx_phycore_ac97_of_dev_id[] = {
> > +	{
> > +		.compatible = "phytec,phycore-ac97",
> > +	}, {
> > +		/* sentinel */
> > +	}
> > +};
> > +MODULE_DEVICE_TABLE(of, imx_phycore_ac97_of_dev_id);
> > +
> > +
> > +/*
> > + * Pointer to AC97 reset functions for specific boards
> > + */
> > +#if IS_ENABLED(CONFIG_MACH_PCA100)
> > +extern void pca100_ac97_cold_reset(struct snd_ac97 *ac97);
> > +extern void pca100_ac97_warm_reset(struct snd_ac97 *ac97);
> > +#else
> > +void pca100_ac97_cold_reset(struct snd_ac97 *ac97) { }
> > +void pca100_ac97_warm_reset(struct snd_ac97 *ac97) { }
> 
> static?

Thanks, added.

> 
> > +#endif
> > +
> > +#if IS_ENABLED(CONFIG_MACH_PCM043)
> > +extern void pcm043_ac97_cold_reset(struct snd_ac97 *ac97);
> > +extern void pcm043_ac97_warm_reset(struct snd_ac97 *ac97);
> > +#else
> > +void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { }
> > +void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { }
> > +#endif
> > +
> > +static void phycore_soc_ac97_reset(struct snd_ac97 *ac97)
> > +{
> > +	if (phycore_ac97_reset)
> > +		phycore_ac97_reset(ac97);
> > +	/* First read sometimes fails, do a dummy read */
> > +	fsl_ssi_ac97_read(ac97, 0);
> 
> This function is unavailable until patch #7, right?

Yes, sorry, I missed to update the order of the patches. I will fix it.

> 
> > +}
> > +
> > +static void phycore_soc_ac97_warm_reset(struct snd_ac97 *ac97)
> > +{
> > +	if (phycore_ac97_warm_reset)
> > +		phycore_ac97_warm_reset(ac97);
> > +
> > +	/* First read sometimes fails, do a dummy read */
> > +	fsl_ssi_ac97_read(ac97, 0);
> > +}
> > +
> > +static int phycore_ac97_setup_devices(struct platform_device *pdev)
> > +{
> > +	int ret;
> > +
> > +	imx_phycore_snd_device = platform_device_alloc("wm9712-codec", -1);
> > +	if (!imx_phycore_snd_device)
> > +		return -ENOMEM;
> > +
> > +	ret = platform_device_add(imx_phycore_snd_device);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "ASoC: Platform device allocation failed\n");
> > +		goto fail1;
> > +	}
> > +
> > +	ret = snd_soc_register_card(&imx_phycore);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "ASoC: soc card registration failed\n");
> > +		goto fail2;
> > +	}
> > +	return 0;
> > +
> > +fail2:
> > +	platform_device_del(imx_phycore_snd_device);
> > +fail1:
> > +	platform_device_put(imx_phycore_snd_device);
> > +	return ret;
> > +}
> > +
> > +static int imx_phycore_ac97_probe(struct platform_device *pdev)
> > +{
> > +	int ret;
> > +	struct device_node *ssi_np;
> > +	struct device_node *audmux_np;
> > +	const char *sprop;
> > +	const char *p;
> > +
> > +	imx_phycore.dev = &pdev->dev;
> > +
> > +	audmux_np = of_parse_phandle(pdev->dev.of_node, "phytec,audmux", 0);
> > +	if (!audmux_np) {
> > +		dev_err(&pdev->dev, "Failed to parse phytec,audmux phandle\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	if (of_device_is_compatible(audmux_np, "fsl,imx21-audmux")) {
> > +		phycore_ac97_imx21_audmux();
> > +	} else if (of_device_is_compatible(audmux_np, "fsl,imx31-audmux")) {
> > +		phycore_ac97_imx31_audmux();
> > +	} else {
> > +		dev_err(&pdev->dev, "Unknown audmux, failed to setup audmux\n");
> > +		of_node_put(audmux_np);
> > +		return -EINVAL;
> > +	}
> > +	of_node_put(audmux_np);
> > +
> > +	ssi_np = of_parse_phandle(pdev->dev.of_node, "phytec,ssi", 0);
> > +	if (!ssi_np) {
> > +		dev_err(&pdev->dev, "No valid ssi phandle found\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	imx_phycore_dai_ac97[0].cpu_of_node = ssi_np;
> > +	imx_phycore_dai_ac97[0].platform_of_node = ssi_np;
> > +	phycore_dai_cpu_node = ssi_np;
> > +
> > +	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
> > +	p = strrchr(sprop, ',');
> > +	if (p)
> > +		sprop = p + 1;
> > +
> > +	if (!strcmp(sprop, "imx27-pca100")) {
> 
> Since this is a phycore/phytec specific ASoC-machine driver, what's the
> problem with matching the machine compatible string by simply calling
> of_machine_is_compatible()?

Changed.

> 
> > +		phycore_ac97_reset = pca100_ac97_cold_reset;
> > +		phycore_ac97_warm_reset = pca100_ac97_warm_reset;
> > +	} else if (!strcmp(sprop, "imx35-pcm043")) {
> > +		phycore_ac97_reset = pcm043_ac97_cold_reset;
> > +		phycore_ac97_warm_reset = pcm043_ac97_warm_reset;
> > +	} else {
> > +		dev_err(&pdev->dev, "Failed to set AC97 reset functions, unknown board.\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	fsl_ssi_ac97_set_reset(phycore_soc_ac97_reset,
> > +			phycore_soc_ac97_warm_reset);
> > +
> > +	ret = phycore_ac97_setup_devices(pdev);
> > +	if (ret)
> > +		of_node_put(phycore_dai_cpu_node);
> > +
> > +	return ret;
> > +}
> > +
> > +static int imx_phycore_ac97_remove(struct platform_device *pdev)
> > +{
> > +	of_node_put(phycore_dai_cpu_node);
> > +	phycore_dai_cpu_node = NULL;
> > +
> > +	platform_device_unregister(imx_phycore_snd_device);
> 
> snd_soc_unregister_card() call is missing?

Yes.

Thanks,

Markus

> 
> Shawn
> 
> > +
> > +	phycore_ac97_reset = NULL;
> > +	phycore_ac97_warm_reset = NULL;
> > +
> > +	return 0;
> > +}
> > +
> > +static struct platform_driver imx_phycore_ac97_driver = {
> > +	.probe		= imx_phycore_ac97_probe,
> > +	.remove		= imx_phycore_ac97_remove,
> > +	.driver		= {
> > +		.name	= DRV_NAME,
> > +		.owner	= THIS_MODULE,
> > +		.of_match_table = imx_phycore_ac97_of_dev_id,
> > +	},
> > +};
> > +
> > +module_platform_driver(imx_phycore_ac97_driver);
> > +
> >  MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
> > -MODULE_DESCRIPTION("PhyCORE ALSA SoC driver");
> > +MODULE_DESCRIPTION(DRV_NAME ": PhyCORE ALSA SoC fabric driver");
> >  MODULE_LICENSE("GPL");
> > -- 
> > 1.8.2.1
> > 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linus.walleij at linaro.org  Thu May 30 05:12:07 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 11:12:07 +0200
Subject: [PATCH 37/39] ARM: ux500: Stop passing DMA platform data though
 AUXDATA
In-Reply-To: <1368611522-9984-38-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-38-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ2-fBrjU-iofjq1DAJ96X2SqbjACsjEWYRxThnSm0yxQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:

> The DMA platform data is now empty due to some recent refactoring,
> so there is no longer a requirement to pass it though.
>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to dma40 branch, hm now I may get a conflict with all
the AUXDATA changes in the devicetree branch. Oh well, I'll
figure it out...

Yours,
Linus Walleij


From will.deacon at arm.com  Thu May 30 05:12:05 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 30 May 2013 10:12:05 +0100
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <CANutaR-e4L+wvfu6Fq7_Q_z9Ynwg8zZcEwzFhH5VxMGfkicYQw@mail.gmail.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com>
 <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com>
 <51A4FC08.3060906@ti.com>
 <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>
 <20130529085426.GA13095@mudshark.cambridge.arm.com>
 <CANutaR_8jNDzPeyJ8PLZPS=yiZ8Ywmk08dR9vLcB2CpxuJac3A@mail.gmail.com>
 <CANutaR-e4L+wvfu6Fq7_Q_z9Ynwg8zZcEwzFhH5VxMGfkicYQw@mail.gmail.com>
Message-ID: <20130530091205.GD7483@mudshark.cambridge.arm.com>

On Thu, May 30, 2013 at 09:15:26AM +0100, Po-Yu Chuang wrote:
> On Wed, May 29, 2013 at 5:34 PM, Po-Yu Chuang <ratbert.chuang at gmail.com> wrote:
> > Hi Will,
> >
> > On Wed, May 29, 2013 at 4:54 PM, Will Deacon <will.deacon at arm.com> wrote:
> >> On Wed, May 29, 2013 at 03:14:58AM +0100, Po-Yu Chuang wrote:
> >>> Will,
> >>> I guess nobody noticed this because the MMU of later v7 processors
> >>> fetches page table
> >>> from D-cache. It even doesn't need to clean pmd to PoU.
> >>
> >> It does if it's UP. The walker is only guaranteed to read from L1 if you
> >> have the multiprocessing extensions.
> >
> > Ya, I see.
> >>
> >> As for this function, looks like it's ok because it has precisely one
> >> caller, so it might be worth prefixing it with some underscores to make it
> >> clear that nobody else should be calling it!
> >
> > I am fine with that.
> > Should I create a new patch?
> 
> Hi,
> 
> Does anyone have more comment about this?

Sorry, I was snowed under yesterday. If you fancy adding the underscores to
__map_init_section, that would help preserve what little remains of my
sanity.

Your existing patch looks technically correct.

Will


From rogerq at ti.com  Thu May 30 05:13:22 2013
From: rogerq at ti.com (Roger Quadros)
Date: Thu, 30 May 2013 12:13:22 +0300
Subject: [PATCH] ARM: OMAP2+: omap-usb-host: clean up pin mux setup code
In-Reply-To: <20130508235232.GW32546@atomide.com>
References: <1366624673-2684-1-git-send-email-rogerq@ti.com>
 <20130508235232.GW32546@atomide.com>
Message-ID: <51A71832.70305@ti.com>

On 05/09/2013 02:52 AM, Tony Lindgren wrote:
> * Roger Quadros <rogerq at ti.com> [130422 03:02]:
>> The USB host pins are named quite differently between OMAP3 and
>> OMAP4+ SoCs. To make this managable in code, we create a pin mapping
>> table (pin_names) that maps pin function to pin name.
>>
>> This pin mapping table is populated at runtime based on a pin
>> name template. Templates are provided for OMAP3 and 4 SoCs.
>>
>> The setup_io_mux() function uses the pin mapping table to
>> setup the pin mux.
>>
>> The resulting code is a lot more clean, manageable and scalable.
> 
> I'm planning to drop all the omap4 pdata soonish. Will post some
> patches after -rc1 to do that. Do you still need this patch
> considering that?
> 

In that case we don't need this.

cheers,
-roger


From mpa at pengutronix.de  Thu May 30 05:13:43 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 11:13:43 +0200
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <CAOZdJXVL2uP-qW=kydgS-t3C=C+6Cn9D3FWqbMuoK2c-EnckyA@mail.gmail.com>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
 <20130529135342.GB29528@S2101-09.ap.freescale.net>
 <CAOZdJXVL2uP-qW=kydgS-t3C=C+6Cn9D3FWqbMuoK2c-EnckyA@mail.gmail.com>
Message-ID: <20130530091343.GB31548@pengutronix.de>

On Wed, May 29, 2013 at 10:41:58AM -0500, Timur Tabi wrote:
> On Wed, May 29, 2013 at 8:53 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> >
> >
> > This function is unavailable until patch #7, right?
> 
> 
> May I suggest that Markus run this script:
> 
> for i in 1 2 3 4 5 6 7 8 9
> do
>   git checkout HEAD^
>   make
> done
> 
> It's important that each commit in a patchset be compilable, otherwise
> git-bisect will break.
> 

I will reorder the patches in the series so that the kernel is
compilable after each patch.

Thanks,

Markus

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linus.walleij at linaro.org  Thu May 30 05:15:20 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 11:15:20 +0200
Subject: [PATCH 38/39] dmaengine: ste_dma40: Fetch the number of physical
 channels from DT
In-Reply-To: <1368611522-9984-39-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-39-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbKwU=gwPYPYgMoj1mRVgnw9zA9RpzmZStFAXVHrkFNRQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Some platforms insist on obscure physical channel availability. This
> information is currently passed though platform data in internal BSP
> kernels. Once those platforms land, they'll need to configure them
> appropriately, so we may as well add the infrastructure.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Vinod's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 05:16:48 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 11:16:48 +0200
Subject: [PATCH 39/39] dmaengine: ste_dma40: Fetch disabled channels from
 DT
In-Reply-To: <1368611522-9984-40-git-send-email-lee.jones@linaro.org>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-40-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaSJ93+W3sRBB2hC87q0=KO5ZBTPa1TG4oy0nX0Jn_nYQ@mail.gmail.com>

On Wed, May 15, 2013 at 11:52 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Some platforms have channels which are not available for normal use.
> This information is currently passed though platform data in internal
> BSP kernels. Once those platforms land, they'll need to configure them
> appropriately, so we may as well add the infrastructure.
>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <djbw at fb.com>
> Cc: Per Forlin <per.forlin at stericsson.com>
> Cc: Rabin Vincent <rabin at rab.in>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Patch applied with Vinod's ACK.

Yours,
Linus Walleij


From florian.vaussard at epfl.ch  Thu May 30 05:19:33 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 30 May 2013 11:19:33 +0200
Subject: [PATCH 1/2] gpiolib: add gpio_export_with_name
In-Reply-To: <20121126135911.2F1D33E187C@localhost>
References: <20121121101259.GQ4398@game.jcrosoft.org>
 <1353492849-29397-1-git-send-email-plagnioj@jcrosoft.com>
 <20121126135911.2F1D33E187C@localhost>
Message-ID: <51A719A5.50906@epfl.ch>

Hello Grant,

On 11/26/2012 02:59 PM, Grant Likely wrote:
> On Wed, 21 Nov 2012 11:14:08 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
>> allow to specify a name to an exported gpio
>>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>
> The gpio sysfs ABI is already horrible, racy, and unsafe. Really, we
> need a proper chrdev interface for controlling gpios. Sysfs is fine for
> poking around and experimenting, but we cannot provide any fine grained
> access control, locking or faster IO with the one-file-per-gpio sysfs
> model. So, no, I don't think this is a good idea to extend gpiolib in
> this way.
>

Would it make sense to provide only the DT binding to export a GPIO,
without changing the sysfs ABI? Even if work is progressing towards
having gpio-controlled reset pins [1], some boards still need GPIOs to
be exported to userspace for other functionalities.

Regards,

Florian

[1] http://article.gmane.org/gmane.linux.power-management.general/31364


From mpa at pengutronix.de  Thu May 30 05:21:34 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 11:21:34 +0200
Subject: [PATCH v6 01/10] ASoC: phycore-ac97: Add DT support
In-Reply-To: <20130528145603.GR21462@opensource.wolfsonmicro.com>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-2-git-send-email-mpa@pengutronix.de>
 <20130528145603.GR21462@opensource.wolfsonmicro.com>
Message-ID: <20130530092134.GC31548@pengutronix.de>

On Tue, May 28, 2013 at 03:56:03PM +0100, Mark Brown wrote:
> On Tue, May 28, 2013 at 04:47:49PM +0200, Markus Pargmann wrote:
> > Add devicetree support for this audio soc fabric driver.
> 
> What is an "audio soc fabric driver"?
> 

I changed both, driver name and commit message.

Thanks,

Markus

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From mpa at pengutronix.de  Thu May 30 05:27:31 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 11:27:31 +0200
Subject: [PATCH v6 03/10] ASoC: imx-pcm-fiq: Introduce pcm-fiq-params
In-Reply-To: <20130529142648.GC29528@S2101-09.ap.freescale.net>
References: <1369752478-30260-1-git-send-email-mpa@pengutronix.de>
 <1369752478-30260-4-git-send-email-mpa@pengutronix.de>
 <20130529142648.GC29528@S2101-09.ap.freescale.net>
Message-ID: <20130530092731.GD31548@pengutronix.de>

On Wed, May 29, 2013 at 10:26:50PM +0800, Shawn Guo wrote:
> On Tue, May 28, 2013 at 04:47:51PM +0200, Markus Pargmann wrote:
> > @@ -47,7 +56,8 @@ static inline void imx_pcm_dma_exit(struct platform_device *pdev)
> >  #endif
> >  
> >  #ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
> > -int imx_pcm_fiq_init(struct platform_device *pdev);
> > +int imx_pcm_fiq_init(struct platform_device *pdev,
> > +		struct imx_pcm_fiq_params *params);
> >  void imx_pcm_fiq_exit(struct platform_device *pdev);
> >  #else
> >  static inline int imx_pcm_fiq_init(struct platform_device *pdev)
> 
> This one also needs update with a new parameter.

Fixed, thanks,

Markus

> 
> Shawn
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From davem at davemloft.net  Thu May 30 05:42:01 2013
From: davem at davemloft.net (David Miller)
Date: Thu, 30 May 2013 02:42:01 -0700 (PDT)
Subject: [PATCHv2 1/3] net: phy: prevent linking breakage
In-Reply-To: <51A5BA86.3070609@free-electrons.com>
References: <1369741403-25315-2-git-send-email-alexandre.belloni@free-electrons.com>
 <20130528.130920.1604291112518863799.davem@davemloft.net>
 <51A5BA86.3070609@free-electrons.com>
Message-ID: <20130530.024201.1913984663902628192.davem@davemloft.net>

From: Alexandre Belloni <alexandre.belloni at free-electrons.com>
Date: Wed, 29 May 2013 10:21:26 +0200

> On 28/05/2013 22:09, David Miller wrote:
>>
>> This is the wrong way to go about this.
>>
>> If the arch code absolutely requires CONFIG_PHYLIB=y then express that
>> dependency in the arch Kconfig.  The arch code in question should not
>> be compiled at all if CONFIG_PHYLIB has an incompatible setting.
> But that is making it impossible to compile a kernel without any network
> stack for those platforms or we are going back to either enclosing the
> calls to phy_register_fixup{,_for_uid,_for_id} with #ifdef CONFIG_PHYLIB
> or if(IS_BUILTIN(CONFIG_PHYLIB)). And as you can see, it is quite error
> prone and is done only done for 2 platforms on a total of 6. I believe
> fixing that in phy.h is more foolproof.

Or you properly segregate the networking bits of the platform code so
that it can be built only when the necessary networking portions are
enabled.

Sometimes having dummy stubs makes sense, but not in this situation.


From manjunath.goudar at linaro.org  Thu May 30 05:50:52 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 30 May 2013 15:20:52 +0530
Subject: [PATCH 0/2] USB: OHCI: Splitting ohci-platform into independent driver
In-Reply-To: <y>
References: <y>
Message-ID: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>

This series patch begins the process of splitting ohci-platform up 
into independent driver modules and add a name for the platform-private field.

Patch 1/2 separate ohci-platform into independent driver modules.  
 
Patch 2/2 adds an ohci->priv field for private use by OHCI platform drivers.


Manjunath Goudar (2):
  USB: OHCI: make ohci-platform a separate driver
  USB: OHCI: add a name for the platform-private field

 drivers/usb/host/Kconfig         |    2 +-
 drivers/usb/host/Makefile        |    1 +
 drivers/usb/host/ohci-hcd.c      |    6 +--
 drivers/usb/host/ohci-platform.c |   88 ++++++++++++++++++--------------------
 drivers/usb/host/ohci.h          |    3 ++
 5 files changed, 47 insertions(+), 53 deletions(-)

-- 
1.7.9.5



From manjunath.goudar at linaro.org  Thu May 30 05:50:53 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 30 May 2013 15:20:53 +0530
Subject: [RFC PATCH 1/2] USB: OHCI: make ohci-platform a separate driver
In-Reply-To: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
References: <y> <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369907454-11003-2-git-send-email-manjunath.goudar@linaro.org>

This patch splits the ohci-platform code from ohci-hcd out
into its own separate driver module.This work is part of enabling
multi-platform kernels on ARM.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig         |    2 +-
 drivers/usb/host/Makefile        |    1 +
 drivers/usb/host/ohci-hcd.c      |    6 +--
 drivers/usb/host/ohci-platform.c |   88 ++++++++++++++++++--------------------
 4 files changed, 44 insertions(+), 53 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a0a2f3a..5391a38 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -501,7 +501,7 @@ config USB_CNS3XXX_OHCI
 	  It is needed for low-speed USB 1.0 device support.
 
 config USB_OHCI_HCD_PLATFORM
-	bool "Generic OHCI driver for a platform device"
+	tristate "Generic OHCI driver for a platform device"
 	default n
 	---help---
 	  Adds an OHCI host driver for a generic platform device, which
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 2214ded..8a89c3d 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
 
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
 obj-$(CONFIG_USB_OHCI_HCD_PCI)	+= ohci-pci.o
+obj-$(CONFIG_USB_OHCI_HCD_PLATFORM)	+= ohci-platform.o
 
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 237be7c..39c7624 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1258,12 +1258,8 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_tilegx_driver
 #endif
 
-#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
-#include "ohci-platform.c"
-#define PLATFORM_DRIVER		ohci_platform_driver
-#endif
-
 #if	!IS_ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\
+	!IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM) && \
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
index 76a3531..8295375 100644
--- a/drivers/usb/host/ohci-platform.c
+++ b/drivers/usb/host/ohci-platform.c
@@ -13,16 +13,28 @@
  *
  * Licensed under the GNU/GPL. See COPYING for details.
  */
+
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/usb/ohci_pdriver.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+
+#define DRIVER_DESC "OHCI generic platform driver"
+
+static const char hcd_name[] = "ohci-platform";
 
 static int ohci_platform_reset(struct usb_hcd *hcd)
 {
 	struct platform_device *pdev = to_platform_device(hcd->self.controller);
 	struct usb_ohci_pdata *pdata = pdev->dev.platform_data;
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int err;
 
 	if (pdata->big_endian_desc)
 		ohci->flags |= OHCI_QUIRK_BE_DESC;
@@ -30,58 +42,17 @@ static int ohci_platform_reset(struct usb_hcd *hcd)
 		ohci->flags |= OHCI_QUIRK_BE_MMIO;
 	if (pdata->no_big_frame_no)
 		ohci->flags |= OHCI_QUIRK_FRAME_NO;
-
-	ohci_hcd_init(ohci);
-
 	if (pdata->num_ports)
 		ohci->num_ports = pdata->num_ports;
 
-	err = ohci_init(ohci);
-
-	return err;
-}
-
-static int ohci_platform_start(struct usb_hcd *hcd)
-{
-	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int err;
-
-	err = ohci_run(ohci);
-	if (err < 0) {
-		ohci_err(ohci, "can't start\n");
-		ohci_stop(hcd);
-	}
-
-	return err;
+	return ohci_setup(ohci);
 }
 
-static const struct hc_driver ohci_platform_hc_driver = {
-	.description		= hcd_name,
-	.product_desc		= "Generic Platform OHCI Controller",
-	.hcd_priv_size		= sizeof(struct ohci_hcd),
+static struct hc_driver __read_mostly ohci_platform_hc_driver;
 
-	.irq			= ohci_irq,
-	.flags			= HCD_MEMORY | HCD_USB11,
-
-	.reset			= ohci_platform_reset,
-	.start			= ohci_platform_start,
-	.stop			= ohci_stop,
-	.shutdown		= ohci_shutdown,
-
-	.urb_enqueue		= ohci_urb_enqueue,
-	.urb_dequeue		= ohci_urb_dequeue,
-	.endpoint_disable	= ohci_endpoint_disable,
-
-	.get_frame_number	= ohci_get_frame,
-
-	.hub_status_data	= ohci_hub_status_data,
-	.hub_control		= ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend		= ohci_bus_suspend,
-	.bus_resume		= ohci_bus_resume,
-#endif
-
-	.start_port_reset	= ohci_start_port_reset,
+static const struct ohci_driver_overrides platform_overrides = {
+	.product_desc =	"Generic Platform EHCI controller",
+	.reset =	ohci_platform_reset,
 };
 
 static int ohci_platform_probe(struct platform_device *dev)
@@ -222,3 +193,26 @@ static struct platform_driver ohci_platform_driver = {
 		.pm	= &ohci_platform_pm_ops,
 	}
 };
+
+static int __init ohci_platform_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_platform_hc_driver, &platform_overrides);
+	return platform_driver_register(&ohci_platform_driver);
+}
+module_init(ohci_platform_init);
+
+static void __exit ohci_platform_cleanup(void)
+{
+	platform_driver_unregister(&ohci_platform_driver);
+}
+module_exit(ohci_platform_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Hauke Mehrtens");
+MODULE_AUTHOR("Alan Stern");
+MODULE_LICENSE("GPL");
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Thu May 30 05:50:54 2013
From: manjunath.goudar at linaro.org (Manjunath Goudar)
Date: Thu, 30 May 2013 15:20:54 +0530
Subject: [RFC PATCH 2/2] USB: OHCI: add a name for the platform-private field
In-Reply-To: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
References: <y> <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <1369907454-11003-3-git-send-email-manjunath.goudar@linaro.org>

This patch adds an ohci->priv field for private use by OHCI
platform drivers.

Until now none of the platform drivers has used this private space,
but that's about to change in the next patch of this series.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index 3b58482..e2e5faa 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -421,6 +421,9 @@ struct ohci_hcd {
 	struct dentry		*debug_periodic;
 	struct dentry		*debug_registers;
 #endif
+	/* platform-specific data -- must come last */
+	unsigned long           priv[0] __aligned(sizeof(s64));
+
 };
 
 #ifdef CONFIG_PCI
-- 
1.7.9.5



From aida.mynzhasova at skitlab.ru  Thu May 30 06:21:01 2013
From: aida.mynzhasova at skitlab.ru (Aida Mynzhasova)
Date: Thu, 30 May 2013 14:21:01 +0400
Subject: [PATCH] ARM: OMAP2: TI81XX: id: Add cpu id for TI816x ES2.0 and ES2.1
Message-ID: <1369909261-23750-1-git-send-email-aida.mynzhasova@skitlab.ru>

Currently omap3xxx_check_revision() detects ES1.0 and ES1.1 only,
this patch extends it by adding ES2.0 and ES2.1 versions support.

Signed-off-by: Aida Mynzhasova <aida.mynzhasova at skitlab.ru>
---
 arch/arm/mach-omap2/id.c  |   11 +++++++++--
 arch/arm/mach-omap2/soc.h |    2 ++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41..8b762a3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -405,11 +405,18 @@ void __init omap3xxx_check_revision(void)
 			cpu_rev = "1.0";
 			break;
 		case 1:
-		/* FALLTHROUGH */
-		default:
 			omap_revision = TI8168_REV_ES1_1;
 			cpu_rev = "1.1";
 			break;
+		case 2:
+			omap_revision = TI8168_REV_ES2_0;
+			cpu_rev = "2.0";
+			break;
+		case 3:
+			/* FALLTHROUGH */
+		default:
+			omap_revision = TI8168_REV_ES2_1;
+			cpu_rev = "2.1";
 		}
 		break;
 	case 0xb944:
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16..8e00226 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -383,6 +383,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define TI816X_CLASS		0x81600034
 #define TI8168_REV_ES1_0	TI816X_CLASS
 #define TI8168_REV_ES1_1	(TI816X_CLASS | (0x1 << 8))
+#define TI8168_REV_ES2_0	(TI816X_CLASS | (0x2 << 8))
+#define TI8168_REV_ES2_1	(TI816X_CLASS | (0x3 << 8))
 
 #define TI814X_CLASS		0x81400034
 #define TI8148_REV_ES1_0	TI814X_CLASS
-- 
1.7.10.4



From pavel at denx.de  Thu May 30 06:37:00 2013
From: pavel at denx.de (Pavel Machek)
Date: Thu, 30 May 2013 12:37:00 +0200
Subject: [PATCH v8] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <1369904940-716-1-git-send-email-p.zabel@pengutronix.de>
References: <1369904940-716-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <20130530103659.GA24712@amd.pavel.ucw.cz>

Hi!

> This driver implements a reset controller device that toggle a gpio
> connected to a reset pin of a peripheral IC. The delay between assertion
> and de-assertion of the reset signal can be configured via device tree.
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> Reviewed-by: Stephen Warren <swarren at nvidia.com>

Reviewed-by: Pavel Machek <pavel at ucw.cz>

Seems ok to me. Having value = asserted is interesting, but you are
basically using it as a documentation, so it looks ok.

Thanks,

								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From pavel at denx.de  Thu May 30 06:38:44 2013
From: pavel at denx.de (Pavel Machek)
Date: Thu, 30 May 2013 12:38:44 +0200
Subject: [PATCH v7] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <51A68CF8.7000303@wwwdotorg.org>
References: <1369753575-9818-1-git-send-email-p.zabel@pengutronix.de>
 <51A68CF8.7000303@wwwdotorg.org>
Message-ID: <20130530103843.GB24712@amd.pavel.ucw.cz>

On Wed 2013-05-29 17:19:20, Stephen Warren wrote:
> On 05/28/2013 09:06 AM, Philipp Zabel wrote:
> > This driver implements a reset controller device that toggle a gpio
> > connected to a reset pin of a peripheral IC. The delay between assertion
> > and de-assertion of the reset signal can be configured via device tree.
> 
> > diff --git a/drivers/reset/gpio-reset.c b/drivers/reset/gpio-reset.c
> 
> > +static void __gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
> 
> Nit: Technically I think __ is a reserved name-space, so you shouldn't
> prefix "user-level" (rather than libc/similar) symbols with it, but it's
> not a big deal.

Well.. this is kernel :-). We don't have libc around... and this
standard is normally ignored here. __ is normally used as a prefix for
"simpler" function.

								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From josephl at nvidia.com  Thu May 30 07:19:39 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 30 May 2013 19:19:39 +0800
Subject: [PATCH 0/3] ARM: tegra114: cpuidle: add power down state
Message-ID: <1369912782-30663-1-git-send-email-josephl@nvidia.com>

This series introduce CPU core power down state for CPU idle. When CPU go
into this state, it saves it's context and needs a proper configuration
in flow controller to power gate the CPU when CPU runs into WFI
instruction. And the CPU also needs to set the IRQ as CPU power down idle
wake up event in flow controller.

To prevent race conditions and ensure proper interrupt routing on
Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier
call-back to reprogram the GIC CPU interface on PM entry. The
GIC CPU interface will be reset back to its normal state by
the common GIC CPU PM exit callback when the CPU wakes up.

Joseph Lo (3):
  ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM
    entry
  ARM: tegra114: add low level support for CPU idle powered-down mode
  ARM: tegra114: cpuidle: add powered-down state

 arch/arm/mach-tegra/cpuidle-tegra114.c | 62 +++++++++++++++++++++++++++++++++-
 arch/arm/mach-tegra/flowctrl.h         |  2 ++
 arch/arm/mach-tegra/irq.c              | 40 ++++++++++++++++++++++
 arch/arm/mach-tegra/sleep-tegra30.S    |  2 ++
 4 files changed, 105 insertions(+), 1 deletion(-)

-- 
1.8.3



From josephl at nvidia.com  Thu May 30 07:19:40 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 30 May 2013 19:19:40 +0800
Subject: [PATCH 1/3] ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ
 on CPU PM entry
In-Reply-To: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369912782-30663-2-git-send-email-josephl@nvidia.com>

There is a difference between GICv1 and v2 when CPU in power management
mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines
going to CPU are same lines which are also used for wake-interrupt.
Therefore, we cannot disable the GIC CPU interface if we need to use same
interrupts for CPU wake purpose. This creates a race condition for CPU
power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1
into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which
means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU.

GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not
disabled by GIC CPU interface. This is done by adding a bypass override
capability when the interrupts are disabled at the CPU interface. To
support this, there are four bits about IRQ/FIQ BypassDisable in CPU
interface Control Register. When the IRQ/FIQ not being driver by the
CPU interface, each interrupt output signal can be deasserted rather
than being driven by the legacy interrupt input.

So the wake-event can be used as wakeup signals to SoC (system power
controller).

To prevent race conditions and ensure proper interrupt routing on
Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier
call-back to reprogram the GIC CPU interface on PM entry. The
GIC CPU interface will be reset back to its normal state by
the common GIC CPU PM exit callback when the CPU wakes up.

Based on the work by: Scott Williams <scwilliams at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/irq.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 0de4eed..1a74d56 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,10 +18,12 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/cpu_pm.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/syscore_ops.h>
 
@@ -65,6 +67,7 @@ static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
 static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
 
 static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+static void __iomem *tegra_gic_cpu_base;
 #endif
 
 bool tegra_pending_sgi(void)
@@ -213,8 +216,43 @@ int tegra_legacy_irq_syscore_init(void)
 
 	return 0;
 }
+
+static int tegra_gic_notifier(struct notifier_block *self,
+			      unsigned long cmd, void *v)
+{
+	switch (cmd) {
+	case CPU_PM_ENTER:
+		writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block tegra_gic_notifier_block = {
+	.notifier_call = tegra_gic_notifier,
+};
+
+static const struct of_device_id tegra114_dt_gic_match[] __initconst = {
+	{ .compatible = "arm,cortex-a15-gic" },
+	{ }
+};
+
+static void tegra114_gic_cpu_pm_registration(void)
+{
+	struct device_node *dn;
+
+	dn = of_find_matching_node(NULL, tegra114_dt_gic_match);
+	if (!dn)
+		return;
+
+	tegra_gic_cpu_base = of_iomap(dn, 1);
+
+	cpu_pm_register_notifier(&tegra_gic_notifier_block);
+}
 #else
 #define tegra_set_wake NULL
+static void tegra114_gic_cpu_pm_registration(void) { }
 #endif
 
 void __init tegra_init_irq(void)
@@ -252,4 +290,6 @@ void __init tegra_init_irq(void)
 	if (!of_have_populated_dt())
 		gic_init(0, 29, distbase,
 			IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+
+	tegra114_gic_cpu_pm_registration();
 }
-- 
1.8.3



From josephl at nvidia.com  Thu May 30 07:19:41 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 30 May 2013 19:19:41 +0800
Subject: [PATCH 2/3] ARM: tegra114: add low level support for CPU idle
 powered-down mode
In-Reply-To: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369912782-30663-3-git-send-email-josephl@nvidia.com>

The flow controller would take care the power sequence when CPU idle in
powered-down mode. It powered gate the CPU when CPU runs into WFI
instruction. And wake up the CPU when event be triggered.

The sequence is below.
* setting wfi bitmap for the CPU as the halt event in the
  FLOW_CTRL_CPU_HALT_REG to monitor the CPU running into WFI,then power
  gate it
* setting IRQ and FIQ as wake up event to wake up CPU when event triggered

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/flowctrl.h      | 2 ++
 arch/arm/mach-tegra/sleep-tegra30.S | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 7a29bae..e56a950 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -28,6 +28,8 @@
 #define FLOW_CTRL_SCLK_RESUME		(1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
 #define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
+#define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
+#define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
 #define FLOW_CTRL_CPU0_CSR		0x8
 #define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
 #define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index ada8821..5877f26 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -99,6 +99,8 @@ flow_ctrl_setting_for_lp2:
 	cmp	r10, #TEGRA30
 	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
 	movne	r3, #FLOW_CTRL_WAITEVENT
+	orrne	r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
+	orrne	r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
 flow_ctrl_done:
 	cmp	r10, #TEGRA30
 	str	r3, [r2]
-- 
1.8.3



From josephl at nvidia.com  Thu May 30 07:19:42 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 30 May 2013 19:19:42 +0800
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
Message-ID: <1369912782-30663-4-git-send-email-josephl@nvidia.com>

This supports CPU core power down on each CPU when CPU idle. When CPU go
into this state, it saves it's context and needs a proper configuration
in flow controller to power gate the CPU when CPU runs into WFI
instruction. And the CPU also needs to set the IRQ as CPU power down idle
wake up event in flow controller.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/cpuidle-tegra114.c | 62 +++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index 1d1c602..e7d21f5 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -17,19 +17,79 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
 
 #include <asm/cpuidle.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+
+#include "pm.h"
+#include "sleep.h"
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra114_idle_power_down(struct cpuidle_device *dev,
+				    struct cpuidle_driver *drv,
+				    int index);
+#define TEGRA114_MAX_STATES 2
+#else
+#define TEGRA114_MAX_STATES 1
+#endif
 
 static struct cpuidle_driver tegra_idle_driver = {
 	.name = "tegra_idle",
 	.owner = THIS_MODULE,
-	.state_count = 1,
+	.state_count = TEGRA114_MAX_STATES,
 	.states = {
 		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+		[1] = {
+			.enter			= tegra114_idle_power_down,
+			.exit_latency		= 500,
+			.target_residency	= 1000,
+			.power_usage		= 0,
+			.flags			= CPUIDLE_FLAG_TIME_VALID,
+			.name			= "powered-down",
+			.desc			= "CPU power gated",
+		},
+#endif
 	},
 };
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra114_idle_power_down(struct cpuidle_device *dev,
+				    struct cpuidle_driver *drv,
+				    int index)
+{
+	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
+
+	local_fiq_disable();
+
+	tegra_set_cpu_in_lp2(cpu);
+	cpu_pm_enter();
+
+	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+	smp_wmb();
+
+	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+
+	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+	cpu_pm_exit();
+	tegra_clear_cpu_in_lp2(cpu);
+
+	local_fiq_enable();
+
+	smp_rmb();
+
+	return index;
+}
+#endif
+
 int __init tegra114_cpuidle_init(void)
 {
+#ifdef CONFIG_PM_SLEEP
+	tegra_tear_down_cpu = tegra30_tear_down_cpu;
+#endif
 	return cpuidle_register(&tegra_idle_driver, NULL);
 }
-- 
1.8.3



From pebolle at tiscali.nl  Thu May 30 07:20:23 2013
From: pebolle at tiscali.nl (Paul Bolle)
Date: Thu, 30 May 2013 13:20:23 +0200
Subject: [PATCH] ARM: OMAP2+: Remove obsolete Makefile line
Message-ID: <1369912823.23034.46.camel@x61.thuisdomein>

The OMAP runtime PM implementation was removed in v3.0. But one Makefile
line, which was used to tweak CFLAGS, was overlooked. Remove it too.

Signed-off-by: Paul Bolle <pebolle at tiscali.nl>
---
Untested. This cleans up after commit 638080c37a ("OMAP2+ / PM: move
runtime PM implementation to use device power domains").

 arch/arm/mach-omap2/Makefile | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..7279fa8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -93,10 +93,6 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a$(plus_sec)
 
-ifeq ($(CONFIG_PM_VERBOSE),y)
-CFLAGS_pm_bus.o				+= -DDEBUG
-endif
-
 endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
-- 
1.7.11.7



From monstr at monstr.eu  Thu May 30 07:28:37 2013
From: monstr at monstr.eu (Michal Simek)
Date: Thu, 30 May 2013 13:28:37 +0200
Subject: [GIT PULL] arm-soc: Xilinx zynq clock changes for v3.11
In-Reply-To: <51A31045.1060406@monstr.eu>
References: <51A31045.1060406@monstr.eu>
Message-ID: <51A737E5.5010206@monstr.eu>

Hi guys,

can you please look at this?
The reason is that based on this we can start to send
zynq driver for review because they depend on this.

Thanks,
Michal


On 05/27/2013 09:50 AM, Michal Simek wrote:
> Hi Arnd and Olof,
> 
> please pull the following changes to your arm-soc tree.
> We haven't got any response from audience or clk maintainer
> but we discussed these changes with him in several threads.
> The major change is to have easy to going DT clock description
> in one node and do not describe the whole clock tree in details
> which none uses.
> 
> Thanks,
> Michal
> 
> 
> The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
> 
>   Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
> 
> are available in the git repository at:
> 
>   git://git.xilinx.com/linux-xlnx.git tags/zynq-clk-for-3.11
> 
> for you to fetch changes up to 83d6e5996a34267e4402e6365c528bddd042ddf3:
> 
>   clk: zynq: Remove deprecated clock code (2013-05-27 09:21:49 +0200)
> 
> ----------------------------------------------------------------
> arm: Xilinx Zynq clock changes for v3.11
> 
> Change Xilinx Zynq DT clock description which
> reflects logical abstraction of Zynq's clock tree.
> 
> - Refactor PLL driver
> - Use new clock controller driver
> - Change timer and uart drivers
> 
> ----------------------------------------------------------------
> Soren Brinkmann (4):
>       clk: zynq: Factor out PLL driver
>       clk: zynq: Add clock controller driver
>       arm: zynq: Migrate platform to clock controller
>       clk: zynq: Remove deprecated clock code
> 
>  Documentation/devicetree/bindings/clock/zynq-7000.txt | 123 ++++++++++++++-------
>  arch/arm/boot/dts/zynq-7000.dtsi                      |  71 ++++--------
>  arch/arm/boot/dts/zynq-zc702.dts                      |   4 -
>  arch/arm/mach-zynq/slcr.c                             |   2 +-
>  drivers/clk/Makefile                                  |   2 +-
>  drivers/clk/clk-zynq.c                                | 378 --------------------------------------------------------------
>  drivers/clk/zynq/Makefile                             |   3 +
>  drivers/clk/zynq/clkc.c                               | 533 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/zynq/pll.c                                | 235 +++++++++++++++++++++++++++++++++++++++
>  drivers/clocksource/cadence_ttc_timer.c               |  23 +++-
>  drivers/tty/serial/xilinx_uartps.c                    |  85 +++++++++++---
>  include/linux/clk/zynq.h                              |   8 +-
>  12 files changed, 972 insertions(+), 495 deletions(-)
>  delete mode 100644 drivers/clk/clk-zynq.c
>  create mode 100644 drivers/clk/zynq/Makefile
>  create mode 100644 drivers/clk/zynq/clkc.c
>  create mode 100644 drivers/clk/zynq/pll.c
> 


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From ratbert.chuang at gmail.com  Thu May 30 07:33:57 2013
From: ratbert.chuang at gmail.com (Po-Yu Chuang)
Date: Thu, 30 May 2013 19:33:57 +0800
Subject: [PATCH] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <20130530091205.GD7483@mudshark.cambridge.arm.com>
References: <1369738100-11152-1-git-send-email-ratbert.chuang@gmail.com>
 <20130528130502.GA28971@mudshark.cambridge.arm.com> <51A4B938.7080708@ti.com>
 <20130528140705.GE28971@mudshark.cambridge.arm.com> <51A4FC08.3060906@ti.com>
 <CANutaR-2gTP7ubiEdgjFyzVMc6=4t5GPjLkH8pkup=O882Hb-Q@mail.gmail.com>
 <20130529085426.GA13095@mudshark.cambridge.arm.com>
 <CANutaR_8jNDzPeyJ8PLZPS=yiZ8Ywmk08dR9vLcB2CpxuJac3A@mail.gmail.com>
 <CANutaR-e4L+wvfu6Fq7_Q_z9Ynwg8zZcEwzFhH5VxMGfkicYQw@mail.gmail.com>
 <20130530091205.GD7483@mudshark.cambridge.arm.com>
Message-ID: <CANutaR_ZHWdXQrZNBN91K==n3taMKBptmyU0+8DT1RzBStNCyA@mail.gmail.com>

On Thu, May 30, 2013 at 5:12 PM, Will Deacon <will.deacon at arm.com> wrote:
> On Thu, May 30, 2013 at 09:15:26AM +0100, Po-Yu Chuang wrote:
>> On Wed, May 29, 2013 at 5:34 PM, Po-Yu Chuang <ratbert.chuang at gmail.com> wrote:
>> > Hi Will,
>> >
>> > On Wed, May 29, 2013 at 4:54 PM, Will Deacon <will.deacon at arm.com> wrote:
>> >> On Wed, May 29, 2013 at 03:14:58AM +0100, Po-Yu Chuang wrote:
>> >>> Will,
>> >>> I guess nobody noticed this because the MMU of later v7 processors
>> >>> fetches page table
>> >>> from D-cache. It even doesn't need to clean pmd to PoU.
>> >>
>> >> It does if it's UP. The walker is only guaranteed to read from L1 if you
>> >> have the multiprocessing extensions.
>> >
>> > Ya, I see.
>> >>
>> >> As for this function, looks like it's ok because it has precisely one
>> >> caller, so it might be worth prefixing it with some underscores to make it
>> >> clear that nobody else should be calling it!
>> >
>> > I am fine with that.
>> > Should I create a new patch?
>>
>> Hi,
>>
>> Does anyone have more comment about this?
Hi Will,

> Sorry, I was snowed under yesterday. If you fancy adding the underscores to
> __map_init_section, that would help preserve what little remains of my
> sanity.

Although I recognize each word above, I am not quite sure what do you mean. :-p
I assume that the sentences mean you prefer adding underscores, so I
will submit a new patch.

>
> Your existing patch looks technically correct.

Regards,
Po-Yu


From j-keerthy at ti.com  Thu May 30 07:33:28 2013
From: j-keerthy at ti.com (keerthy)
Date: Thu, 30 May 2013 17:03:28 +0530
Subject: [PATCH v10 01/12] mfd: DT bindings for the palmas family MFD
In-Reply-To: <5150906F.9040202@wwwdotorg.org>
References: <1363964122-19201-1-git-send-email-ian@slimlogic.co.uk>
 <1363964122-19201-2-git-send-email-ian@slimlogic.co.uk>
 <5150906F.9040202@wwwdotorg.org>
Message-ID: <51A73908.7020206@ti.com>


On 03/25/2013 11:29 PM, Stephen Warren wrote:

> On 03/22/2013 08:55 AM, Ian Lartey wrote:
>> From: Graeme Gregory <gg at slimlogic.co.uk>
>>
>> Add the various binding files for the palmas family of chips. There is a
>> top level MFD binding then a seperate binding for IP blocks on chips.
> 
>> diff --git a/Documentation/devicetree/bindings/clock/palmas-clk.txt b/Documentation/devicetree/bindings/clock/palmas-clk.txt
> 
> Where is the reg property; if you're instantiating the clk device as a
> standalone DT node and driver, it should be possible to retrieve the
> address of this IP block instance from DT, not using driver-internal APIs.
> 
> This same comment likely applies everywhere, so I won't repeat it.
> 
>> +Example:
>> +
>> +clk {
>> +    compatible = "ti,twl6035-clk", "ti,palmas-clk";
>> +    ti,clk32kg-mode-sleep = <0>;
>> +    ti,clk32kgaudio-mode-sleep = <0>;
> 
>> +    #clock-cells = <1>;
>> +    clock-frequency = <32000000>;
>> +    clock-names = "clk32kg", "clk32kgaudio";
> 
> The binding description itself should describe what clocks this node
> provides and consumes.
> 
> What is clock-frequency; which clock does it affect?
> 
> The presence of #clock-cells implies this is a clock provider. This
> binding should define the format of the clock cells that this property
> implies. I assume it's just the ID of the output clocks, but what values
> correspond to which output clocks? That mapping table needs to be listed
> here.
> 
> The presence of clock-names implies this is a clock consumer. However,
> there is no clocks property in the example. Is clks missing from the
> example, or should this property be clock-output-names instead? If this
> node is a clock consumer, the list of which clocks it requires should be
> documented.
> 
>> diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
> 
>> +- gpio-controller: mark the device as a GPIO controller
>> +- gpio-cells = <1>:  GPIO lines are provided.
> 
> That's #gpio-cells not gpio-cells.
> 
> I assume that cell simply contains the GPIO ID/number. That should be
> documented for clarity.
> 
> Surely gpio-cells should be 2 not 1, so there is space for flags. At
> least an "inverted" or "active-low" flag should be included; GPIO
> consumers would typically implement that flag in SW, so there' no
> requirement that the flag only be supported if the HW supports the feature.
> 
>> +- interrupt-controller : palmas has its own internal IRQs
>> +- #interrupt-cells : should be set to 2 for IRQ number and flags
>> +  The first cell is the IRQ number.
>> +  The second cell is the flags, encoded as the trigger masks from
>> +  Documentation/devicetree/bindings/interrupts.txt
> 
> You need "/interrupt-controller" before the filename there.
> 
>> +- interrupt-parent : The parent interrupt controller.
> 
> If this IP block has interrupt outputs, it should require an
> "interrupts" property too. This is the same concept that drives the need
> for a reg property. This same comment likely applies everywhere, so I
> won't repeat it.
> 
>> diff --git a/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt
> 
>> +- interrupts: the interrupt outputs of the controller.
> 
> How many entries are there, what do they mean, and in what order must
> they appear? (Note that the binding of a node must define the order of
> the interrupts property, since historically it's been accessed by index,
> not by name, and all bindings must allow that access method to be used).
> 
>> +- interrupt-names : Should be the name of irq resource. Each interrupt
>> +  binds its interrupt-name.
> 
> The binding needs to define standard names for the entries in this
> property, or define that interrupts are only retrieved by index, in
> which case interrupt-names shouldn't be present. This same comment
> likely applies everywhere, so I won't repeat it.
> 
>> diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
> 
>> +Required properties:
> ...
> 
> I believe the Palmas devices have many separate I2C addresses, even
> buses, which are I think are at least partially independently SW
> configurable. In that case, the reg property for this node should
> probably enumerate all the I2C addresses that this chip responds to, so
> that they can each be passed down to the child nodes.


Stephen,

The palmas devices do have multiple I2C slave IDs. From OMAP5 as the master
all the palmas slave devices are connected via I2C1 bus.

I did not understand the SW configurable part. It is more board
dependent. Correct me if i understood it wrongly.

Graeme,

Can i send a separate Documentation patch for palmas-core and palmas-regulators
outside this series since the drivers are already part of mainline kernel.
This will ensure at least the bare minimal DT support for palmas family
will be available in the mainline kernel?

> 

>> diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
> 
>> +Optional nodes:
>> +- regulators : should contain the constrains and init information for the
>> +	       regulators. It should contain a subnode per regulator from the
>> +	       list.
>> +	       For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
>> +	       smps45, smps457, smps7 depending on varient, smps6, smps[8-10],
>> +	       ldo[1-9], ldoln, ldousb
>> +	       For ti,palmas-charger-pmic - smps12, smps123, smps3 depending on OTP,
>> +	       smps[6-9], boost, ldo[1-14], ldoln, ldousb
> 
> The list of legal compatible values for this node above doesn't include
> both ti,palmas-pmic and ti,palmas-charger-pmic. Should it? This node
> should describe this PMIC block in a completely standalone fashion,
> without the need to go look at the top-level node to see if it's a
> "charger" variant or not.
> 
>> +	       optional chip specific regulator fields :-
>> +	       ti,warm-reset - maintain voltage during warm reset
>> +	       ti,roof-floor - control voltage selection by pin
> 
> I assume those are Boolean not integer. It's worth mentioning the type
> of each property.




Reagrds,
Keerthy


From will.deacon at arm.com  Thu May 30 07:41:12 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 30 May 2013 12:41:12 +0100
Subject: A bug about system call on ARM
In-Reply-To: <20130530090949.GC7483@mudshark.cambridge.arm.com>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
Message-ID: <20130530114112.GH7483@mudshark.cambridge.arm.com>

On Thu, May 30, 2013 at 10:09:49AM +0100, Will Deacon wrote:
> On Thu, May 30, 2013 at 02:41:42AM +0100, Wang, Yalin wrote:
> > If you have some patch for this issue,
> > I can do the test for it .
> 
> I'll have a look at cooking something which uses an exception table entry
> to rewind the PC and retry the system call. That's simpler than directly
> injecting a user page fault from the system call path.

Ok, please can you try the following?

Will

--->8

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a..855926e 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -361,6 +361,15 @@ ENTRY(vector_swi)
 	str	r8, [sp, #S_PSR]		@ Save CPSR
 	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
 	zero_fp
+	enable_irq
+	ct_user_exit
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+	ldr	ip, __cr_alignment
+	ldr	ip, [ip]
+	mcr	p15, 0, ip, c1, c0		@ update control register
+#endif
+	get_thread_info tsk
 
 	/*
 	 * Get the system call number.
@@ -375,9 +384,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
 	tst	r8, #PSR_T_BIT
 	movne	r10, #0				@ no thumb OABI emulation
-	ldreq	r10, [lr, #-4]			@ get SWI instruction
+ USER(	ldreq	r10, [lr, #-4]		)	@ get SWI instruction
 #else
-	ldr	r10, [lr, #-4]			@ get SWI instruction
+ USER(	ldr	r10, [lr, #-4]		)	@ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
 	rev	r10, r10			@ little endian instruction
@@ -392,22 +401,13 @@ ENTRY(vector_swi)
 	/* Legacy ABI only, possibly thumb mode. */
 	tst	r8, #PSR_T_BIT			@ this is SPSR from save_user_regs
 	addne	scno, r7, #__NR_SYSCALL_BASE	@ put OS number in
-	ldreq	scno, [lr, #-4]
+ USER(	ldreq	scno, [lr, #-4]		)
 
 #else
 	/* Legacy ABI only. */
-	ldr	scno, [lr, #-4]			@ get SWI instruction
-#endif
-
-#ifdef CONFIG_ALIGNMENT_TRAP
-	ldr	ip, __cr_alignment
-	ldr	ip, [ip]
-	mcr	p15, 0, ip, c1, c0		@ update control register
+ USER(	ldr	scno, [lr, #-4]		)	@ get SWI instruction
 #endif
-	enable_irq
-	ct_user_exit
 
-	get_thread_info tsk
 	adr	tbl, sys_call_table		@ load syscall table pointer
 
 #if defined(CONFIG_OABI_COMPAT)
@@ -442,6 +442,18 @@ local_restart:
 	eor	r0, scno, #__NR_SYSCALL_BASE	@ put OS number back
 	bcs	arm_syscall	
 	b	sys_ni_syscall			@ not private func
+
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+	/*
+	 * We may have faulted trying to load the SWI instruction due to
+	 * concurrent page aging on another CPU. In this case, return
+	 * back to the swi instruction and fault the page back.
+	 */
+9001:
+	sub	lr, lr, #4
+	str	lr, [sp, #S_PC]
+	b	ret_fast_syscall
+#endif
 ENDPROC(vector_swi)
 
 	/*


From b-cousson at ti.com  Thu May 30 07:44:23 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Thu, 30 May 2013 13:44:23 +0200
Subject: [PATCH v2 11/14] Documentation: dt: binding: omap: am43x timer
In-Reply-To: <51A61E60.4070708@wwwdotorg.org>
References: <cover.1369658705.git.afzal@ti.com>
 <223d90dc9eeab13d8496690d336cdf0f7d27cd22.1369658705.git.afzal@ti.com>
 <51A520B5.8040803@gmail.com> <51A52A16.1040204@wwwdotorg.org>
 <C8443D0743D26F4388EA172BF4E2A7A93EAFB044@DBDE04.ent.ti.com>
 <51A5BEB6.6070809@ti.com> <51A61E60.4070708@wwwdotorg.org>
Message-ID: <51A73B97.2020701@ti.com>

Hi Stephen,

On 05/29/2013 05:27 PM, Stephen Warren wrote:
> On 05/29/2013 02:39 AM, Benoit Cousson wrote:
>> Hi Afzal,
>>
>> On 05/29/2013 10:06 AM, Mohammed, Afzal wrote:
>>> Hi Jon,
>>>
>>> On Wed, May 29, 2013 at 03:35:10, Stephen Warren wrote:
>>>> On 05/28/2013 03:25 PM, Jon Hunter wrote:
>>>
>>>>>>  			ti,am335x-timer	(applicable to AM335x devices)
>>>>>>  			ti,am335x-timer-1ms (applicable to AM335x devices)
>>>>>> +			"ti,am4372-timer-1ms", "ti,am335x-timer-1ms" for AM43x 1ms timer
>>>>>> +			"ti,am4372-timer", "ti,am335x-timer" for AM43x timers other than 1ms one
>>>
>>>>> If you are adding more compatibility strings, then this implies that the
>>>>> AM43x timers are not 100% compatible with any other device listed (such
>>>>> as am335x or any omap device). That's fine but you should state that in
>>>>> the changelog. If the AM43x timer registers are 100% compatible with
>>>>> existing devices you should not add these.
>>>>
>>>> I'm not sure that's true; .dts files should always include a compatible
>>>> value that describes the most specific model of the HW, plus any
>>>> baseline compatible value that the HW is compatible with. This allows
>>>> any required quirks/fixes/... to be applied for the specific HW model
>>>> later even if nobody knows right now they'll be needed. Hence, defining
>>>> new compatible values doesn't necessarily mean incompatible HW.
>>>
>>> Stephen took words out of my finger ;)
>>>  
>>> Some explanations,I don;t 
>>>
>>> 1. first compatible should be exact device [A], followed by compatible
>>> model (if one)
>>> 2. Minor effort in getting DT right the first time may help prevent
>>> difficult effort later modifying it (if a necessity comes), considering
>>> the fact that DT sources has  to move out of Kernel at some point of
>>> time. And DT is not supposed to be modified, which may cause difficulty
>>> for the users (I had been a minor victim of this during rebase).
>>>
>>> As we both were in GPMC land earlier, an example,
>>>
>>> If my memory is right, GPMC IP in am335x is rev 6, and IP has 8 chip
>>> select, but one is not pinned out. Now assume that same IP is integrated
>>> in another SoC (probably OMAP4 has rev 6). Here if we use same compatible
>>> for both, driver cannot handle it properly (w/o knowledge about platform).
>>> But if exact compatible is mentioned, without modifying DT (which should
>>> be considered as a firmware) just by modifying Kernel, deciding based on
>>> compatible would help achieve what is required.
>>
>> That's true for the DTS itself, but here your are changing the binding
>> documentation which is supposed to reflect the driver "interface" in the
>> Device Tree model description.
>>
>> Since the driver does not support any new compatible string, you should
>> not update the binding.
> 
> I don't agree here; the DT binding should define all the required and/or
> allowed values that must/should/can be present in the DT - the entire
> legal schema. The set of all compatible values is included in that,
> irrespective of whether a particular value actually (currently) defines
> a different HW interface or not.

Well, I tend to agree on the principle, but so far it was never really
done like that. That's not necessarily a good excuse, but if we start
adding new bindings for the huge number of OMAP|AM variants TI has been
introduced for 10 years, I'd rather use a wildcard than a exhaustive
list of all the devices.
Something like ti,[omap|am]*-timer for example .

Regards,
Benoit



From rogerq at ti.com  Thu May 30 07:45:28 2013
From: rogerq at ti.com (Roger Quadros)
Date: Thu, 30 May 2013 14:45:28 +0300
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <20130529173715.GB21290@arwen.pp.htv.fi>
References: <1368424303-10629-5-git-send-email-chao.xie@marvell.com>
 <Pine.LNX.4.44L0.1305131012090.1389-100000@iolanthe.rowland.org>
 <20130528162415.GA28253@arwen.pp.htv.fi>
 <CADApbegejeoxc4TmjvsPse=54durFym2cfDRdg9RviDZJ2HAFg@mail.gmail.com>
 <20130529173715.GB21290@arwen.pp.htv.fi>
Message-ID: <51A73BD8.8000007@ti.com>

On 05/29/2013 08:37 PM, Felipe Balbi wrote:
> Hi,
> 
> On Wed, May 29, 2013 at 11:58:01AM +0800, Chao Xie wrote:
>> On Wed, May 29, 2013 at 12:24 AM, Felipe Balbi <balbi at ti.com> wrote:
>>> Hi,
>>>
>>> On Mon, May 13, 2013 at 10:13:44AM -0400, Alan Stern wrote:
>>>> On Mon, 13 May 2013, Chao Xie wrote:
>>>>
>>>>> Originaly, ehci driver will call the callbacks in platform data
>>>>> for PHY initialization and shut down.
>>>>> With PHY driver, it will call the APIs provided by PHY driver
>>>>> for PHY initialization and shutdown. It removes the callbacks
>>>>> in platform data, and at same time it removes one block in the
>>>>> way of enabling device tree for ehci driver.
>>>>
>>>> I wonder if this is the sort of thing that should be handled in
>>>> ehci-hcd.c rather than in all the different platform glue drivers.
>>>>
>>>> Felipe, what do you think?  Are the required actions now sufficiently
>>>> generic that a single source file can take care of them?
>>>
>>> Sorry for the delay, was on business trip and now on vacations. Anyway,
>>> I agree with you. Our PHY layer should be generic enough that it should
>>> be usable by ehci-hcd itself. If we have any missing method, let's add
>>> it generically.
>>>
>> So what are your idea about making the PHY layer more generic? How
>> ehci-hcd will make use of PHY layer?
> 
> 
> on probe grab the phy and initialize it. On suspend/resume,
> suspend/resume the PHY and so on. Whatever you were going to do on your
> ehci glue, do it on generic ehci-hcd.
> 

These operations sound generic enough to be done at HCD layer, no? So no need to
replicate the same stuff in ohci, ehci, xhci, etc.

cheers,
-roger


From ratbert.chuang at gmail.com  Thu May 30 07:46:00 2013
From: ratbert.chuang at gmail.com (Po-Yu Chuang)
Date: Thu, 30 May 2013 19:46:00 +0800
Subject: [PATCH v2] ARM: map_init_section flushes incorrect pmd
In-Reply-To: <CANutaR_ZHWdXQrZNBN91K==n3taMKBptmyU0+8DT1RzBStNCyA@mail.gmail.com>
References: <CANutaR_ZHWdXQrZNBN91K==n3taMKBptmyU0+8DT1RzBStNCyA@mail.gmail.com>
Message-ID: <1369914361-4237-1-git-send-email-ratbert.chuang@gmail.com>

This bug was introduced in commit e651eab0.
Some v4/v5 platforms failed to boot due to this.

Signed-off-by: Po-Yu Chuang <ratbert.chuang at gmail.com>
---
v2:
prefix underscores to map_init_section to emphasize that it should never be
called by some random function.

 arch/arm/mm/mmu.c |    8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e0d8565..4d409e6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -616,10 +616,12 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 	} while (pte++, addr += PAGE_SIZE, addr != end);
 }
 
-static void __init map_init_section(pmd_t *pmd, unsigned long addr,
+static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
 			unsigned long end, phys_addr_t phys,
 			const struct mem_type *type)
 {
+	pmd_t *p = pmd;
+
 #ifndef CONFIG_ARM_LPAE
 	/*
 	 * In classic MMU format, puds and pmds are folded in to
@@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
 		phys += SECTION_SIZE;
 	} while (pmd++, addr += SECTION_SIZE, addr != end);
 
-	flush_pmd_entry(pmd);
+	flush_pmd_entry(p);
 }
 
 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
@@ -661,7 +663,7 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 		 */
 		if (type->prot_sect &&
 				((addr | next | phys) & ~SECTION_MASK) == 0) {
-			map_init_section(pmd, addr, next, phys, type);
+			__map_init_section(pmd, addr, next, phys, type);
 		} else {
 			alloc_init_pte(pmd, addr, next,
 						__phys_to_pfn(phys), type);
-- 
1.7.9.5



From sergei.shtylyov at cogentembedded.com  Thu May 30 07:50:32 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 30 May 2013 15:50:32 +0400
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <23620997.ZR1QCYhSc2@avalon>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <51A682C7.9060605@cogentembedded.com> <23620997.ZR1QCYhSc2@avalon>
Message-ID: <51A73D08.40003@cogentembedded.com>

Hello.

On 30-05-2013 3:51, Laurent Pinchart wrote:

>>> From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

>>> The USB_OVCn pins are alternate options for USB over-current detection
>>> when using a 3.3V USB interface. As they're not mandatory they can be
>>> used independently of the USB PENC pins. Don't group the USB_OVCn and
>>> PENC pins to avoid conflicts when the USB_OVCn pins are used by another
>>> function.

>>> Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>>> Signed-off-by: Laurent Pinchart
>>> <laurent.pinchart+renesas at ideasonboard.com>
>>> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

>> I suspect this is needed in -stable. The bug is older than 3.10-rc1.

> Is it ? The offending commit is

> commit 97d40c4224172451f666febdd865c24b1c3c3fe5
> Author: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> Date:   Thu Mar 7 13:38:51 2013 +0100

>      sh-pfc: r8a7779: Add USB pin groups and functions

>      Signed-off-by: Laurent Pinchart
> <laurent.pinchart+renesas at ideasonboard.com>
>      Acked-by: Linus Walleij <linus.walleij at linaro.org>

> and got applied to mainline in v3.10-rc1.

    Ah, then sorry for the false alarm. Consequency of working in the 
'next' branch all the time...

WBR, Sergei



From thierry.reding at gmail.com  Thu May 30 08:15:19 2013
From: thierry.reding at gmail.com (Thierry Reding)
Date: Thu, 30 May 2013 14:15:19 +0200
Subject: [RFCv1 09/11] pci: mvebu: add MSI support
In-Reply-To: <CAErSpo7yC_97Vg-zuype-jyfqiY+77OE97cxYoEO9ZZnXjQ95A@mail.gmail.com>
References: <1364316746-8702-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1364316746-8702-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <CAErSpo7yC_97Vg-zuype-jyfqiY+77OE97cxYoEO9ZZnXjQ95A@mail.gmail.com>
Message-ID: <20130530121518.GA20267@mithrandir>

On Mon, Apr 08, 2013 at 04:29:07PM -0600, Bjorn Helgaas wrote:
> On Tue, Mar 26, 2013 at 10:52 AM, Thomas Petazzoni <thomas.petazzoni at free-electrons.com> wrote:
[...]
> > +static int mvebu_pcie_setup_msi_irq(struct msi_chip *chip,
> > +                                   struct pci_dev *pdev,
> > +                                   struct msi_desc *desc)
> > +{
> > +       struct mvebu_pcie_msi *msi = to_mvebu_msi(chip);
> 
> If this took only the pci_dev (not the msi_chip), I think you could do this:
> 
>   struct mvebu_pcie_msi *msi = &pdev->bus->sysdata->msi;

That would mean that the arch_setup_msi_irq() and friends could still be
architecture-agnostic because they only pass around pci_dev, and the
driver specific implementations would know how to lookup sysdata and
from there the MSI chip.

So I was almost convinced that putting the struct msi_chip pointer into
sysdata is a good idea. However that also means that each PCI host
bridge driver becomes architecture-specific. If we ever get a driver
that can be used on multiple architectures (however unlikely), the only
way to make it work would be to #ifdef those parts. We could make that
easier to deal with by providing an accessor (pci_sysdata_set_msi_chip()
or similar), though.

But maybe it's something we don't need to be concerned about because no
PCI host bridge driver will ever support two different architecture?

One related point is compile coverage. If the drivers are completely
architecture-agnostic it makes it a lot easier to compile-test all
drivers, which might come in useful when doing core changes and such.

Thierry
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From sergei.shtylyov at cogentembedded.com  Thu May 30 08:23:00 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 30 May 2013 16:23:00 +0400
Subject: [PATCH 2/2] ARM: shmobile: r8A7779: fix Ether device name
In-Reply-To: <20130528040043.GL13532@quad.lixom.net>
References: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
 <1369645206-3682-3-git-send-email-horms+renesas@verge.net.au>
 <20130528040043.GL13532@quad.lixom.net>
Message-ID: <51A744A4.5020909@cogentembedded.com>

Hello.

On 28-05-2013 8:00, Olof Johansson wrote:

>> From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>

>> While recasting the commit "ARM: shmobile: R8A7779: add Ether support", I made a
>> typo in the platform device's name: used underscore instead of hyphen.

> Minor nit: if this has been merged, then including the SHA is useful too.

    Yes, it has been merged in 3.10. Simon, can you do this without me 
reposting the patch? The defective commit's SHA1 ID is 
dace48d04dee46a3409d5e13cd98031522e46377.
    Note that there is analogous R8A7778 Ether fix, the SHA1 for its 
defective commit is 524219146a89aee5366326c225ccd71231419d89.

> -Olof

WBR, Sergei



From Yalin.Wang at sonymobile.com  Thu May 30 08:22:56 2013
From: Yalin.Wang at sonymobile.com (Wang, Yalin)
Date: Thu, 30 May 2013 20:22:56 +0800
Subject: =?gb2312?B?tPC4tDogQSBidWcgYWJvdXQgc3lzdGVtIGNhbGwgb24gQVJN?=
Message-ID: <ih0015wu30o5nq4ajf437rl7.1369916575726@email.android.com>

Hi Will,

i see your solution,
i Will test it tomorrow,
and report the result to you ASAP!

Thank for your help very much.

Sent from Moxier Mail
(http://www.moxier.com)


----- ???? -----
???: Will Deacon <will.deacon at arm.com>
???: "Wang, Yalin" <Yalin.Wang at sonymobile.com>
??: 'richard -rw- weinberger' <richard.weinberger at gmail.com>, "'linux-arch at vger.kernel.org'" <linux-arch at vger.kernel.org>, "'linux-kernel at vger.kernel.org'" <linux-kernel at vger.kernel.org>, "'linux-arm-kernel at lists.infradead.org'" <linux-arm-kernel at lists.infradead.org>
????: 2013-5-30 19:41
??: Re: A bug about system call on ARM



On Thu, May 30, 2013 at 10:09:49AM +0100, Will Deacon wrote:
> On Thu, May 30, 2013 at 02:41:42AM +0100, Wang, Yalin wrote:
> > If you have some patch for this issue,
> > I can do the test for it .
>
> I'll have a look at cooking something which uses an exception table entry
> to rewind the PC and retry the system call. That's simpler than directly
> injecting a user page fault from the system call path.

Ok, please can you try the following?

Will

--->8

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a..855926e 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -361,6 +361,15 @@ ENTRY(vector_swi)
        str     r8, [sp, #S_PSR]                @ Save CPSR
        str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
        zero_fp
+       enable_irq
+       ct_user_exit
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+       ldr     ip, __cr_alignment
+       ldr     ip, [ip]
+       mcr     p15, 0, ip, c1, c0              @ update control register
+#endif
+       get_thread_info tsk

        /*
         * Get the system call number.
@@ -375,9 +384,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
        tst     r8, #PSR_T_BIT
        movne   r10, #0                         @ no thumb OABI emulation
-       ldreq   r10, [lr, #-4]                  @ get SWI instruction
+ USER( ldreq   r10, [lr, #-4]          )       @ get SWI instruction
 #else
-       ldr     r10, [lr, #-4]                  @ get SWI instruction
+ USER( ldr     r10, [lr, #-4]          )       @ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
        rev     r10, r10                        @ little endian instruction
@@ -392,22 +401,13 @@ ENTRY(vector_swi)
        /* Legacy ABI only, possibly thumb mode. */
        tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
        addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
-       ldreq   scno, [lr, #-4]
+ USER( ldreq   scno, [lr, #-4]         )

 #else
        /* Legacy ABI only. */
-       ldr     scno, [lr, #-4]                 @ get SWI instruction
-#endif
-
-#ifdef CONFIG_ALIGNMENT_TRAP
-       ldr     ip, __cr_alignment
-       ldr     ip, [ip]
-       mcr     p15, 0, ip, c1, c0              @ update control register
+ USER( ldr     scno, [lr, #-4]         )       @ get SWI instruction
 #endif
-       enable_irq
-       ct_user_exit

-       get_thread_info tsk
        adr     tbl, sys_call_table             @ load syscall table pointer

 #if defined(CONFIG_OABI_COMPAT)
@@ -442,6 +442,18 @@ local_restart:
        eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
        bcs     arm_syscall
        b       sys_ni_syscall                  @ not private func
+
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+       /*
+        * We may have faulted trying to load the SWI instruction due to
+        * concurrent page aging on another CPU. In this case, return
+        * back to the swi instruction and fault the page back.
+        */
+9001:
+       sub     lr, lr, #4
+       str     lr, [sp, #S_PC]
+       b       ret_fast_syscall
+#endif
 ENDPROC(vector_swi)

        /*

From mpa at pengutronix.de  Thu May 30 08:44:55 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 14:44:55 +0200
Subject: [PATCH] ARM: imx: Remove mxc specific ulpi access ops
Message-ID: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>

There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c.
mxc access ops implement the same access operations within mach-imx. This
patch removes the mxc ulpi file and uses phy-ulpi instead for
imx_otg_ulpi_create.

phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100).

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig       |   1 +
 arch/arm/mach-imx/Makefile      |   1 -
 arch/arm/mach-imx/mach-pca100.c |   4 +-
 arch/arm/mach-imx/ulpi.c        | 118 ----------------------------------------
 arch/arm/mach-imx/ulpi.h        |   9 ++-
 5 files changed, 9 insertions(+), 124 deletions(-)
 delete mode 100644 arch/arm/mach-imx/ulpi.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328..ca59799 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -58,6 +58,7 @@ config MXC_USE_EPIT
 
 config MXC_ULPI
 	bool
+	select USB_ULPI_VIEWPORT
 
 config ARCH_HAS_RNGA
 	bool
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 70ae7c4..dcb8291 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 
-obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb..19bb644 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -398,8 +398,8 @@ static void __init pca100_init(void)
 		imx27_add_fsl_usb2_udc(&otg_device_pdata);
 	}
 
-	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+	usbh2_pdata.otg = imx_otg_ulpi_create(
+			ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
 	if (usbh2_pdata.otg)
 		imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f05195..0000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
- * Copyright 2009 Daniel Mack <daniel at caiaq.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include "ulpi.h"
-
-/* ULPIVIEW register bits */
-#define ULPIVW_WU		(1 << 31)	/* Wakeup */
-#define ULPIVW_RUN		(1 << 30)	/* read/write run */
-#define ULPIVW_WRITE		(1 << 29)	/* 0 = read  1 = write */
-#define ULPIVW_SS		(1 << 27)	/* SyncState */
-#define ULPIVW_PORT_MASK	0x07	/* Port field */
-#define ULPIVW_PORT_SHIFT	24
-#define ULPIVW_ADDR_MASK	0xff	/* data address field */
-#define ULPIVW_ADDR_SHIFT	16
-#define ULPIVW_RDATA_MASK	0xff	/* read data field */
-#define ULPIVW_RDATA_SHIFT	8
-#define ULPIVW_WDATA_MASK	0xff	/* write data field */
-#define ULPIVW_WDATA_SHIFT	0
-
-static int ulpi_poll(void __iomem *view, u32 bit)
-{
-	int timeout = 10000;
-
-	while (timeout--) {
-		u32 data = __raw_readl(view);
-
-		if (!(data & bit))
-			return 0;
-
-		cpu_relax();
-	};
-
-	printk(KERN_WARNING "timeout polling for ULPI device\n");
-
-	return -ETIMEDOUT;
-}
-
-static int ulpi_read(struct usb_phy *otg, u32 reg)
-{
-	int ret;
-	void __iomem *view = otg->io_priv;
-
-	/* make sure interface is running */
-	if (!(__raw_readl(view) & ULPIVW_SS)) {
-		__raw_writel(ULPIVW_WU, view);
-
-		/* wait for wakeup */
-		ret = ulpi_poll(view, ULPIVW_WU);
-		if (ret)
-			return ret;
-	}
-
-	/* read the register */
-	__raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
-
-	/* wait for completion */
-	ret = ulpi_poll(view, ULPIVW_RUN);
-	if (ret)
-		return ret;
-
-	return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
-}
-
-static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
-{
-	int ret;
-	void __iomem *view = otg->io_priv;
-
-	/* make sure the interface is running */
-	if (!(__raw_readl(view) & ULPIVW_SS)) {
-		__raw_writel(ULPIVW_WU, view);
-		/* wait for wakeup */
-		ret = ulpi_poll(view, ULPIVW_WU);
-		if (ret)
-			return ret;
-	}
-
-	__raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
-		      (reg << ULPIVW_ADDR_SHIFT) |
-		      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
-
-	/* wait for completion */
-	return ulpi_poll(view, ULPIVW_RUN);
-}
-
-struct usb_phy_io_ops mxc_ulpi_access_ops = {
-	.read	= ulpi_read,
-	.write	= ulpi_write,
-};
-EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
-
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
-	return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
-}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca..8bb0230 100644
--- a/arch/arm/mach-imx/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
@@ -1,8 +1,13 @@
 #ifndef __MACH_ULPI_H
 #define __MACH_ULPI_H
 
+#include <linux/usb/ulpi.h>
+
 #ifdef CONFIG_USB_ULPI
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
+static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
+{
+	return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
+}
 #else
 static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 {
@@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 }
 #endif
 
-extern struct usb_phy_io_ops mxc_ulpi_access_ops;
-
 #endif /* __MACH_ULPI_H */
 
-- 
1.8.2.1



From mkl at pengutronix.de  Thu May 30 08:51:13 2013
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Thu, 30 May 2013 14:51:13 +0200
Subject: [PATCH] ARM: imx: Remove mxc specific ulpi access ops
In-Reply-To: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>
References: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>
Message-ID: <51A74B41.5010909@pengutronix.de>

On 05/30/2013 02:44 PM, Markus Pargmann wrote:
> There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c.
> mxc access ops implement the same access operations within mach-imx. This
> patch removes the mxc ulpi file and uses phy-ulpi instead for
> imx_otg_ulpi_create.
> 
> phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100).
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/mach-imx/Kconfig       |   1 +
>  arch/arm/mach-imx/Makefile      |   1 -
>  arch/arm/mach-imx/mach-pca100.c |   4 +-
>  arch/arm/mach-imx/ulpi.c        | 118 ----------------------------------------
>  arch/arm/mach-imx/ulpi.h        |   9 ++-
>  5 files changed, 9 insertions(+), 124 deletions(-)
>  delete mode 100644 arch/arm/mach-imx/ulpi.c
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index ba44328..ca59799 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -58,6 +58,7 @@ config MXC_USE_EPIT
>  
>  config MXC_ULPI
>  	bool
> +	select USB_ULPI_VIEWPORT
>  
>  config ARCH_HAS_RNGA
>  	bool
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 70ae7c4..dcb8291 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
>  obj-$(CONFIG_MXC_TZIC) += tzic.o
>  obj-$(CONFIG_MXC_AVIC) += avic.o
>  
> -obj-$(CONFIG_MXC_ULPI) += ulpi.o
>  obj-$(CONFIG_MXC_USE_EPIT) += epit.o
>  obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
>  
> diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
> index b8b15bb..19bb644 100644
> --- a/arch/arm/mach-imx/mach-pca100.c
> +++ b/arch/arm/mach-imx/mach-pca100.c
> @@ -398,8 +398,8 @@ static void __init pca100_init(void)
>  		imx27_add_fsl_usb2_udc(&otg_device_pdata);
>  	}
>  
> -	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
> -				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
> +	usbh2_pdata.otg = imx_otg_ulpi_create(
> +			ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);

Why don't you keep otg_ulpi_create()?

http://lxr.free-electrons.com/source/include/linux/usb/ulpi.h#L185

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From mpa at pengutronix.de  Thu May 30 08:59:54 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 14:59:54 +0200
Subject: [PATCH] ARM: imx: Remove mxc specific ulpi access ops
In-Reply-To: <51A74B41.5010909@pengutronix.de>
References: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>
 <51A74B41.5010909@pengutronix.de>
Message-ID: <20130530125954.GE31548@pengutronix.de>

On Thu, May 30, 2013 at 02:51:13PM +0200, Marc Kleine-Budde wrote:
> On 05/30/2013 02:44 PM, Markus Pargmann wrote:
> > There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c.
> > mxc access ops implement the same access operations within mach-imx. This
> > patch removes the mxc ulpi file and uses phy-ulpi instead for
> > imx_otg_ulpi_create.
> > 
> > phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100).
> > 
> > Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> > Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  arch/arm/mach-imx/Kconfig       |   1 +
> >  arch/arm/mach-imx/Makefile      |   1 -
> >  arch/arm/mach-imx/mach-pca100.c |   4 +-
> >  arch/arm/mach-imx/ulpi.c        | 118 ----------------------------------------
> >  arch/arm/mach-imx/ulpi.h        |   9 ++-
> >  5 files changed, 9 insertions(+), 124 deletions(-)
> >  delete mode 100644 arch/arm/mach-imx/ulpi.c
> > 
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index ba44328..ca59799 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -58,6 +58,7 @@ config MXC_USE_EPIT
> >  
> >  config MXC_ULPI
> >  	bool
> > +	select USB_ULPI_VIEWPORT
> >  
> >  config ARCH_HAS_RNGA
> >  	bool
> > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> > index 70ae7c4..dcb8291 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
> > @@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
> >  obj-$(CONFIG_MXC_TZIC) += tzic.o
> >  obj-$(CONFIG_MXC_AVIC) += avic.o
> >  
> > -obj-$(CONFIG_MXC_ULPI) += ulpi.o
> >  obj-$(CONFIG_MXC_USE_EPIT) += epit.o
> >  obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
> >  
> > diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
> > index b8b15bb..19bb644 100644
> > --- a/arch/arm/mach-imx/mach-pca100.c
> > +++ b/arch/arm/mach-imx/mach-pca100.c
> > @@ -398,8 +398,8 @@ static void __init pca100_init(void)
> >  		imx27_add_fsl_usb2_udc(&otg_device_pdata);
> >  	}
> >  
> > -	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
> > -				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
> > +	usbh2_pdata.otg = imx_otg_ulpi_create(
> > +			ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
> 
> Why don't you keep otg_ulpi_create()?

I could still use otg_ulpi_create with updated access ops
(ulpi_viewport_access_ops). But I decided to use imx_otg_ulpi_create
because it is used 10 lines above and it is more consistent this way.

Regards,

Markus


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From gautam.vivek at samsung.com  Thu May 30 09:10:55 2013
From: gautam.vivek at samsung.com (Vivek Gautam)
Date: Thu, 30 May 2013 18:40:55 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net> <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 <51A5C16D.20408@linaro.org> <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
Message-ID: <3D99F44C56954EC59167436E26BE91F6@sisodomain.com>

Hi,

> On Wednesday, May 29, 2013 5:51 PM, Tushar Behera:
>> On 05/29/2013 11:01 AM, Olof Johansson wrote:
>> > On Tue, May 28, 2013 at 8:59 PM, Tushar Behera 
>> > <tushar.behera at linaro.org> wrote:
>> >
>> >> The patches are at [1].
>> >
>> > FWIW, a cgit/gitweb link is easier to follow when you're reading an
>> > email. Anyway, found the patches.
>> >
>> >> There are a total of 6 patches on top of
>> >> v3.10-rc3. 3 of them (a, b, d) are queued for 3.10-rc4 and another 
>> >> patch
>> >> (c) is just a defconfig hack to get Arndale booting. Remaining 2 
>> >> patches
>> >> (e, f) are required to reset the hub during EHCI initialization.
>> >
>> > Huh, I thought you said that (c) wasn't needed when I posted the
>> > defconfig update. It'd be nice to see the code fixed to handle this
>> > case instead of Linaro carrying a patch like this though. I.e. make it
>> > able to deselect the uart, or make it tied to DEBUG_LL like on other
>> > platforms instead of having a separate config for this.
>> >
>>
>> It would be good to free up the dependency on the correct UART port for
>> the board to boot. Without that, there would always be boards that don't
>> boot with default mainline defconfig file even though all other
>> components are in place.
>>
>> >> a. ARM: exynos: defconfig update
>> >> b. ARM: EXYNOS: Update defconfig for Arndale and Origen board
>> >> c. [TEMP] ARM: EXYNOS: Set low-level UART port to 2
>> >> d. ARM: dts: Enabling samsung-usb2phy driver for exynos5250
>> >> e. usb: ehci-s5p: add the HSIC port initialization
>> >> f. ARM: dts: Add USB gpio entries for Arndale board
>> >>
>> >> I am not sure whether such kind of board-specific patches (e, f) are
>> >> appreciated in the drivers. But that is all we need to get USB and
>> >> Ethernet to work on v3.10-rc3 kernel.
>> >
>> > I've come across a similar situation with wifi reset sequence on the
>> > chromebook. On the product kernel we added some code to the board file
>> > to deal with it, but if we keep doing that things will grow out of
>> > hand.
>> >
>> > I don't know if it'll be unpopular, but I think it's time to start a
>> > drivers/platform/arm for these kind of things, and have those drivers
>> > probe on the system compatible value, similar to how x86 does it (with
>> > DMI tables). At least that's my plan for approaching the wifi
>> > reset/power-on sequence on the Chromebook. I hope to have patches in
>> > not all that long...
>> >
>> > Likewise, the hub reset/enable code doesn't have to go with the USB
>> > driver, right? I.e. if you cycle reset/enable on the hub after the
>> > host and phy is configured, you'll still have a working setup?
>> >
>>
>> Right, hub reset/enable code need not be tied up with USB driver. As per
>> your suggestion regarding drivers/platform/arm, I implemented an Arndale
>> specific driver [2] in drivers/platform/arm and verified USB and
>> ethernet to be working.
>
> CC'ed Thomas Abraham, Vivek Gautam
>
> I think so.
>
> I looked at Arndale board Schematics.
> 'Hub chip' on Arndale board needs hub reset/enable code.
> 'HUB_RESET' and 'HUB_CONNECT' pins are used to reset 'Hub chip'
> on Arndale board, not Exynos EHCI controller. So, Exynos EHCI driver
> does not need to consider this hub reset/enable code.
>
> If there is a driver for this 'Hub chip', 'Hub chip' driver maybe
> consider this.
>
> However, Olof Johansson mentioned, 'drivers/platform/arm/board_arndale.c'
> would be a good alternative.

We do have a driver for USB3503 in upstream now, which has enough 
infrastructure for us to use.
We just want to handle states of HUB_CONNECT line or RESET_N line, which 
should just be fine with this driver.

Am I missing something ?

>
>>
>> [2]
>> https://git.linaro.org/gitweb?p=landing-
>> teams/working/samsung/kernel.git;a=shortlog;h=refs/heads/upstream/arndale-usb-2
>
> It looks good.


Regards
Vivek 



From mpa at pengutronix.de  Thu May 30 09:09:59 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 15:09:59 +0200
Subject: [PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as cacheable,
 increase IPU priority
In-Reply-To: <1369919399-24370-1-git-send-email-mpa@pengutronix.de>
References: <1369919399-24370-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369919399-24370-2-git-send-email-mpa@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

This is needed so that the IPU framebuffer scanout cannot be starved
by VPU or GPU activity.
The Freescale SabreLite and SabreSD boards seem to set this in the boot
rom already, but the documented register reset values do not contain
the necessary settings.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 arch/arm/mach-imx/mach-imx6q.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd8..7bef242 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -29,6 +29,7 @@
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -161,6 +162,36 @@ static void __init imx6q_usb_init(void)
 	imx_anatop_usb_chrg_detect_disable();
 }
 
+static void __init imx6q_gpr_init(void)
+{
+	struct regmap *gpr;
+
+	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+	if (IS_ERR(gpr)) {
+		pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
+		return;
+	}
+
+	/* Enable the cacheable attribute of VPU and IPU AXI transactions */
+	regmap_update_bits(gpr, IOMUXC_GPR4, 0,
+			IMX6Q_GPR4_VPU_WR_CACHE_SEL |
+			IMX6Q_GPR4_VPU_RD_CACHE_SEL |
+			IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
+			IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
+			IMX6Q_GPR4_IPU_WR_CACHE_CTL |
+			IMX6Q_GPR4_IPU_RD_CACHE_CTL);
+
+	/* Increase IPU read QoS priority */
+	regmap_update_bits(gpr, IOMUXC_GPR6,
+			IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
+			IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
+			(0xf << 16) | (0x7 << 20));
+	regmap_update_bits(gpr, IOMUXC_GPR7,
+			IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
+			IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
+			(0xf << 16) | (0x7 << 20));
+}
+
 static void __init imx6q_init_machine(void)
 {
 	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
@@ -172,6 +203,7 @@ static void __init imx6q_init_machine(void)
 	imx6q_pm_init();
 	imx6q_usb_init();
 	imx6q_1588_init();
+	imx6q_gpr_init();
 }
 
 #define OCOTP_CFG3			0x440
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 09:09:58 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 15:09:58 +0200
Subject: [PATCH 1/2] ARM: imx6q: Add GPR6 and GPR7 register definitions for
 iomuxc gpr
Message-ID: <1369919399-24370-1-git-send-email-mpa@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

Masks for IPU AXI transaction QoS settings

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index dab34a1..2e1709b 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -241,6 +241,24 @@
 
 #define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
 
+#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK	(0xf << 0)
+#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK	(0xf << 4)
+#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK	(0xf << 8)
+#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK	(0xf << 12)
+#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK	(0xf << 16)
+#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK	(0xf << 20)
+#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK	(0xf << 24)
+#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK	(0xf << 28)
+
+#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK	(0xf << 0)
+#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK	(0xf << 4)
+#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK	(0xf << 8)
+#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK	(0xf << 12)
+#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK	(0xf << 16)
+#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK	(0xf << 20)
+#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK	(0xf << 24)
+#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK	(0xf << 28)
+
 #define IMX6Q_GPR9_TZASC2_BYP			BIT(1)
 #define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
 
-- 
1.8.2.1



From arnd at arndb.de  Thu May 30 09:16:21 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 30 May 2013 15:16:21 +0200
Subject: [PATCH v7] reset: Add driver for gpio-controlled reset pins
In-Reply-To: <20130530103843.GB24712@amd.pavel.ucw.cz>
References: <1369753575-9818-1-git-send-email-p.zabel@pengutronix.de>
 <51A68CF8.7000303@wwwdotorg.org> <20130530103843.GB24712@amd.pavel.ucw.cz>
Message-ID: <201305301516.22111.arnd@arndb.de>

On Thursday 30 May 2013, Pavel Machek wrote:
> On Wed 2013-05-29 17:19:20, Stephen Warren wrote:
> > On 05/28/2013 09:06 AM, Philipp Zabel wrote:
> > > This driver implements a reset controller device that toggle a gpio
> > > connected to a reset pin of a peripheral IC. The delay between assertion
> > > and de-assertion of the reset signal can be configured via device tree.
> > 
> > > diff --git a/drivers/reset/gpio-reset.c b/drivers/reset/gpio-reset.c
> > 
> > > +static void __gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
> > 
> > Nit: Technically I think __ is a reserved name-space, so you shouldn't
> > prefix "user-level" (rather than libc/similar) symbols with it, but it's
> > not a big deal.
> 
> Well.. this is kernel :-). We don't have libc around... and this
> standard is normally ignored here. __ is normally used as a prefix for
> "simpler" function.

We're not really consistent in the kernel, but I agree the most common
use is where you have a wrapper calling the __foo function and normal
drivers are supposed to call foo instead. My reading is usually that
by calling __foo, the caller says "I know exactly what I'm doing so
I can optimize this".

	Arnd


From dt.tangr at gmail.com  Thu May 30 09:21:18 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Thu, 30 May 2013 23:21:18 +1000
Subject: [PATCH] Add Initial TI-Nspire support
Message-ID: <E775DD08-5516-468E-9924-0D839218D7F9@gmail.com>

Hi,

Here is the final patch for adding the platform code needed for Linux support on the TI-Nspire calculator series.

Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 Documentation/devicetree/bindings/arm/nspire.txt |  14 +++
 arch/arm/Kconfig                                 |   2 +
 arch/arm/Kconfig.debug                           |  16 +++
 arch/arm/Makefile                                |   1 +
 arch/arm/include/debug/nspire.S                  |  28 ++++++
 arch/arm/mach-nspire/Kconfig                     |  15 +++
 arch/arm/mach-nspire/Makefile                    |   2 +
 arch/arm/mach-nspire/Makefile.boot               |   0
 arch/arm/mach-nspire/clcd.c                      | 119 +++++++++++++++++++++++
 arch/arm/mach-nspire/clcd.h                      |  14 +++
 arch/arm/mach-nspire/mmio.h                      |  20 ++++
 arch/arm/mach-nspire/nspire.c                    |  89 +++++++++++++++++
 12 files changed, 320 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/nspire.txt
 create mode 100644 arch/arm/include/debug/nspire.S
 create mode 100644 arch/arm/mach-nspire/Kconfig
 create mode 100644 arch/arm/mach-nspire/Makefile
 create mode 100644 arch/arm/mach-nspire/Makefile.boot
 create mode 100644 arch/arm/mach-nspire/clcd.c
 create mode 100644 arch/arm/mach-nspire/clcd.h
 create mode 100644 arch/arm/mach-nspire/mmio.h
 create mode 100644 arch/arm/mach-nspire/nspire.c

diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt
new file mode 100644
index 0000000..4d08518
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/nspire.txt
@@ -0,0 +1,14 @@
+TI-NSPIRE calculators
+
+Required properties:
+- compatible: Compatible property value should contain "ti,nspire".
+	CX models should have "ti,nspire-cx"
+	Touchpad models should have "ti,nspire-tp"
+	Clickpad models should have "ti,nspire-clp"
+
+Example:
+
+/ {
+	model = "TI-NSPIRE CX";
+	compatible = "ti,nspire-cx";
+	...
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..86a3ed9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -964,6 +964,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-nspire/Kconfig"
+
 source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908..fe07941 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -309,6 +309,20 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on MVEBU based platforms.
 
+	config DEBUG_NSPIRE_CLASSIC_UART
+		bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
+		depends on ARCH_NSPIRE
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on TI-NSPIRE classic models.
+
+	config DEBUG_NSPIRE_CX_UART
+		bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
+		depends on ARCH_NSPIRE
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on TI-NSPIRE CX models.
+
 	config DEBUG_NOMADIK_UART
 		bool "Kernel low-level debugging messages via NOMADIK UART"
 		depends on ARCH_NOMADIK
@@ -633,6 +647,8 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_IMX53_UART ||\
 				 DEBUG_IMX6Q_UART
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
+	default "debug/nspire.S" if 	DEBUG_NSPIRE_CX_UART || \
+					DEBUG_NSPIRE_CLASSIC_UART
 	default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
 	default "debug/nomadik.S" if DEBUG_NOMADIK_UART
 	default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1ba358b..b4615aa 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -164,6 +164,7 @@ machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_NETX)		+= netx
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
 machine-$(CONFIG_ARCH_OMAP1)		+= omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 0000000..886fd27
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
+/*
+ *	linux/arch/arm/include/debug/nspire.S
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE	   0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE	   0xfee20000
+
+.macro	addruart, rp, rv, tmp
+	ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE)		@ physical base address
+	ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE)		@ virtual base address
+.endm
+
+
+#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
+#include <asm/hardware/debug-pl01x.S>
+#endif
+
+#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
+#endif
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 0000000..a295b18
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_NSPIRE
+	bool "TI-NSPIRE based"
+	depends on ARCH_MULTI_V4_V5
+	depends on MMU
+	select CPU_ARM926T
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select SPARSE_IRQ
+	select ARM_AMBA
+	select ARM_VIC
+	select ARM_TIMER_SP804
+	select USE_OF
+	select CLKSRC_OF
+	help
+	  This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 0000000..1bec256
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
+obj-y				+= nspire.o
+obj-y				+= clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 0000000..abea126
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,119 @@
+/*
+ *	linux/arch/arm/mach-nspire/clcd.c
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/dma-mapping.h>
+
+static struct clcd_panel nspire_cx_lcd_panel = {
+	.mode		= {
+		.name		= "Color LCD",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.sync		= 0,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.pixclock	= 1,
+		.hsync_len	= 6,
+		.vsync_len	= 1,
+		.right_margin	= 50,
+		.left_margin	= 38,
+		.lower_margin	= 3,
+		.upper_margin	= 17,
+	},
+	.width		= 65, /* ~6.50 cm */
+	.height		= 49, /* ~4.87 cm */
+	.tim2		= TIM2_IPC,
+	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
+	.bpp		= 16,
+	.caps		= CLCD_CAP_565,
+};
+
+static struct clcd_panel nspire_classic_lcd_panel = {
+	.mode		= {
+		.name		= "Grayscale LCD",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.pixclock	= 1,
+		.hsync_len	= 6,
+		.vsync_len	= 1,
+		.right_margin	= 6,
+		.left_margin	= 6,
+	},
+	.width		= 71, /* 7.11cm */
+	.height		= 53, /* 5.33cm */
+	.tim2		= 0x80007d0,
+	.cntl		= CNTL_LCDMONO8,
+	.bpp		= 8,
+	.grayscale	= 1,
+	.caps		= CLCD_CAP_5551,
+};
+
+int nspire_clcd_setup(struct clcd_fb *fb)
+{
+	struct clcd_panel *panel;
+	size_t panel_size;
+	const char *type;
+	dma_addr_t dma;
+	int err;
+
+	BUG_ON(!fb->dev->dev.of_node);
+
+	err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
+	if (err) {
+		pr_err("CLCD: Could not find lcd-type property\n");
+		return err;
+	}
+
+	if (!strcmp(type, "cx")) {
+		panel = &nspire_cx_lcd_panel;
+	} else if (!strcmp(type, "classic")) {
+		panel = &nspire_classic_lcd_panel;
+	} else {
+		pr_err("CLCD: Unknown lcd-type %s\n", type);
+		return -EINVAL;
+	}
+
+	panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
+	panel_size = ALIGN(panel_size, PAGE_SIZE);
+
+	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+		panel_size, &dma, GFP_KERNEL);
+
+	if (!fb->fb.screen_base) {
+		pr_err("CLCD: unable to map framebuffer\n");
+		return -ENOMEM;
+	}
+
+	fb->fb.fix.smem_start = dma;
+	fb->fb.fix.smem_len = panel_size;
+	fb->panel = panel;
+
+	return 0;
+}
+
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+	return dma_mmap_writecombine(&fb->dev->dev, vma,
+		fb->fb.screen_base, fb->fb.fix.smem_start,
+		fb->fb.fix.smem_len);
+}
+
+void nspire_clcd_remove(struct clcd_fb *fb)
+{
+	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+		fb->fb.screen_base, fb->fb.fix.smem_start);
+}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 0000000..8c33d2c
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
+/*
+ *	linux/arch/arm/mach-nspire/clcd.h
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+int nspire_clcd_setup(struct clcd_fb *fb);
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
+void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 0000000..8813471
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,20 @@
+/*
+ *	linux/arch/arm/mach-nspire/mmio.h
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_MISC_PHYS_BASE		0x900A0000
+#define NSPIRE_MISC_HWRESET		0x08
+
+#define NSPIRE_PWR_PHYS_BASE		0x900B0000
+#define NSPIRE_PWR_VIRT_BASE		0xFEEB0000
+#define NSPIRE_PWR_BUS_DISABLE1		0x18
+#define NSPIRE_PWR_BUS_DISABLE2		0x20
+
+#define NSPIRE_LCD_PHYS_BASE		0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 0000000..99e2609
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,89 @@
+/*
+ *	linux/arch/arm/mach-nspire/nspire.c
+ *
+ *	Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-vic.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/hardware/timer-sp.h>
+
+#include "mmio.h"
+#include "clcd.h"
+
+static const char *nspire_dt_match[] __initconst = {
+	"ti,nspire",
+	"ti,nspire-cx",
+	"ti,nspire-tp",
+	"ti,nspire-clp",
+	NULL,
+};
+
+static void __init nspire_map_io(void)
+{
+	debug_ll_io_init();
+}
+
+static struct clcd_board nspire_clcd_data = {
+	.name		= "LCD",
+	.caps		= CLCD_CAP_5551 | CLCD_CAP_565,
+	.check		= clcdfb_check,
+	.decode		= clcdfb_decode,
+	.setup		= nspire_clcd_setup,
+	.mmap		= nspire_clcd_mmap,
+	.remove		= nspire_clcd_remove,
+};
+
+
+static struct of_dev_auxdata nspire_auxdata[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
+			NULL, &nspire_clcd_data),
+	{ }
+};
+
+static void __init nspire_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			nspire_auxdata, NULL);
+}
+
+static void __init nspire_init_time(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+static void nspire_restart(char mode, const char *cmd)
+{
+	void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
+	if (!base)
+		return;
+
+	writel(2, base + NSPIRE_MISC_HWRESET);
+}
+
+DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
+	.dt_compat	= nspire_dt_match,
+	.map_io		= nspire_map_io,
+	.init_time	= nspire_init_time,
+	.init_machine	= nspire_init,
+	.restart	= nspire_restart,
+MACHINE_END
-- 
1.8.1.3




From dt.tangr at gmail.com  Thu May 30 09:24:19 2013
From: dt.tangr at gmail.com (Daniel Tang)
Date: Thu, 30 May 2013 23:24:19 +1000
Subject: [PATCH] Device trees for TI-Nspire hardware
Message-ID: <827B6FFA-81CC-4866-8F8B-2762AB8B7A2F@gmail.com>

This patch adds the device trees for describing the TI-Nspire hardware.


Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
---
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 arch/arm/boot/dts/Makefile                         |   3 +
 arch/arm/boot/dts/nspire-classic.dtsi              |  74 +++++++++
 arch/arm/boot/dts/nspire-clp.dts                   |  45 ++++++
 arch/arm/boot/dts/nspire-cx.dts                    | 112 +++++++++++++
 arch/arm/boot/dts/nspire-tp.dts                    |  44 ++++++
 arch/arm/boot/dts/nspire.dtsi                      | 175 +++++++++++++++++++++
 7 files changed, 454 insertions(+)
 create mode 100644 arch/arm/boot/dts/nspire-classic.dtsi
 create mode 100644 arch/arm/boot/dts/nspire-clp.dts
 create mode 100644 arch/arm/boot/dts/nspire-cx.dts
 create mode 100644 arch/arm/boot/dts/nspire-tp.dts
 create mode 100644 arch/arm/boot/dts/nspire.dtsi

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c43..b27b057 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -31,6 +31,7 @@ idt	Integrated Device Technologies, Inc.
 img	Imagination Technologies Ltd.
 intercontrol	Inter Control Group
 linux	Linux-specific binding
+lsi	LSI Corp. (LSI Logic)
 marvell	Marvell Technology Group Ltd.
 maxim	Maxim Integrated Products
 mosaixtech	Mosaix Technologies, Inc.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c5..6191b1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
 	imx28-sps1.dtb \
 	imx28-tx28.dtb
 dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
+	nspire-tp.dtb \
+	nspire-clp.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	omap3430-sdp.dtb \
 	omap3-beagle.dtb \
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 0000000..9565199
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/boot/nspire-classic.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "nspire.dtsi"
+
+&lcd {
+	lcd-type = "classic";
+};
+
+&fast_timer {
+	/* compatible = "lsi,zevio-timer"; */
+	reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+};
+
+&uart {
+	compatible = "ns16550";
+	reg-shift = <2>;
+	reg-io-width = <4>;
+	clocks = <&apb_pclk>;
+	no-loopback-test;
+};
+
+&timer0 {
+	/* compatible = "lsi,zevio-timer"; */
+	reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+};
+
+&timer1 {
+	compatible = "lsi,zevio-timer";
+	reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+};
+
+&keypad {
+	active-low;
+
+};
+
+&base_clk {
+	compatible = "lsi,nspire-classic-clock";
+};
+
+&ahb_clk {
+	compatible = "lsi,nspire-classic-ahb-divider";
+};
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x10000000 0x2000000>; /* 32 MB */
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		intc: interrupt-controller at DC000000 {
+			compatible = "lsi,zevio-intc";
+			interrupt-controller;
+			reg = <0xDC000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+	};
+	chosen {
+		bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
+	};
+};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 0000000..3f9c8af
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/boot/nspire-clp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00020039
+	0x0004002c 	0x00050034 	0x00060015
+	0x0007000b 	0x0008002d 	0x01000033
+	0x0101004e 	0x01020011 	0x01030004
+	0x0104002f 	0x01050003 	0x01060016
+	0x01070002 	0x01080014 	0x02000062
+	0x0201000c 	0x0202001f 	0x02030007
+	0x02040013 	0x02050006 	0x02060010
+	0x02070005 	0x02080019 	0x03000027
+	0x03010037 	0x03020018 	0x0303000a
+	0x03040031 	0x03050009 	0x03060032
+	0x03070008 	0x03080026 	0x04000028
+	0x04010035 	0x04020025 	0x04040024
+	0x04060017 	0x04080023 	0x05000028
+	0x05020022 	0x0503001b 	0x05040021
+	0x0505001a 	0x05060012 	0x0507006f
+	0x05080020 	0x0509002a 	0x0601001c
+	0x0602002e 	0x06030068 	0x06040030
+	0x0605006d 	0x0606001e 	0x06070001
+	0x0608002b 	0x0609000f 	0x07000067
+	0x0702006a 	0x0704006c 	0x07060069
+	0x0707000e 	0x0708001d 	0x070a000d
+	>;
+};
+
+/ {
+	model = "TI-NSPIRE Clickpad";
+	compatible = "ti,nspire-clp";
+};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 0000000..64632ca
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/boot/nspire-cx.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire.dtsi"
+
+&lcd {
+	lcd-type = "cx";
+};
+
+&fast_timer {
+	/* compatible = "arm,sp804", "arm,primecell"; */
+};
+
+&uart {
+	compatible = "arm,pl011", "arm,primecell";
+
+	clocks = <&uart_clk>, <&apb_pclk>;
+	clock-names = "uart_clk", "apb_pclk";
+};
+
+&timer0 {
+	compatible = "arm,sp804", "arm,primecell";
+};
+
+&timer1 {
+	compatible = "arm,sp804", "arm,primecell";
+};
+
+&base_clk {
+	compatible = "lsi,nspire-cx-clock";
+};
+
+&ahb_clk {
+	compatible = "lsi,nspire-cx-ahb-divider";
+};
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
+
+/ {
+	model = "TI-NSPIRE CX";
+	compatible = "ti,nspire-cx";
+
+	memory {
+		device_type = "memory";
+		reg = <0x10000000 0x4000000>; /* 64 MB */
+	};
+
+	uart_clk: uart_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		intc: interrupt-controller at DC000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xDC000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		apb at 90000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			i2c at 90050000 {
+				compatible = "snps,designware-i2c";
+				reg = <0x90050000 0x1000>;
+				interrupts = <20>;
+			};
+		};
+	};
+	chosen {
+		bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
+	};
+};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 0000000..ab209a3
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
+/*
+ *  linux/arch/arm/boot/nspire-tp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+	keymap = <
+	0x0000001c 	0x0001001c 	0x00040039
+	0x0005002c 	0x00060015 	0x0007000b
+	0x0008000f 	0x0100002d 	0x01010011
+	0x0102002f 	0x01030004 	0x01040016
+	0x01050014 	0x0106001f 	0x01070002
+	0x010a006a 	0x02000013 	0x02010010
+	0x02020019 	0x02030007 	0x02040018
+	0x02050031 	0x02060032 	0x02070005
+	0x02080028 	0x0209006c 	0x03000026
+	0x03010025 	0x03020024 	0x0303000a
+	0x03040017 	0x03050023 	0x03060022
+	0x03070008 	0x03080035 	0x03090069
+	0x04000021 	0x04010012 	0x04020020
+	0x0404002e 	0x04050030 	0x0406001e
+	0x0407000d 	0x04080037 	0x04090067
+	0x05010038 	0x0502000c 	0x0503001b
+	0x05040034 	0x0505001a 	0x05060006
+	0x05080027 	0x0509000e 	0x050a006f
+	0x0600002b 	0x0602004e 	0x06030068
+	0x06040003 	0x0605006d 	0x06060009
+	0x06070001 	0x0609000f 	0x0708002a
+	0x0709001d 	0x070a0033 	>;
+};
+
+/ {
+	model = "TI-NSPIRE Touchpad";
+	compatible = "ti,nspire-tp";
+};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 0000000..a22ffe6
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
+/*
+ *  linux/arch/arm/boot/nspire.dtsi
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	bootrom: bootrom at 00000000 {
+		reg = <0x00000000 0x80000>;
+	};
+
+	sram: sram at A4000000 {
+		device = "memory";
+		reg = <0xA4000000 0x20000>;
+	};
+
+	timer_clk: timer_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	base_clk: base_clk {
+		#clock-cells = <0>;
+		reg = <0x900B0024 0x4>;
+	};
+
+	ahb_clk: ahb_clk {
+		#clock-cells = <0>;
+		reg = <0x900B0024 0x4>;
+		clocks = <&base_clk>;
+	};
+
+	apb_pclk: apb_pclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <2>;
+		clock-mult = <1>;
+		clocks = <&ahb_clk>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		spi: spi at A9000000 {
+			reg = <0xA9000000 0x1000>;
+		};
+
+		usb0: usb at B0000000 {
+			reg = <0xB0000000 0x1000>;
+			interrupts = <8>;
+		};
+
+		usb1: usb at B4000000 {
+			reg = <0xB4000000 0x1000>;
+			interrupts = <9>;
+			status = "disabled";
+		};
+
+		lcd: lcd at C0000000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0xC0000000 0x1000>;
+			interrupts = <21>;
+
+			clocks = <&apb_pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		adc: adc at C4000000 {
+			reg = <0xC4000000 0x1000>;
+			interrupts = <11>;
+		};
+
+		tdes: crypto at C8010000 {
+			reg = <0xC8010000 0x1000>;
+		};
+
+		sha256: crypto at CC000000 {
+			reg = <0xCC000000 0x1000>;
+		};
+
+		apb at 90000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clock-ranges;
+			ranges;
+
+			gpio: gpio at 90000000 {
+				reg = <0x90000000 0x1000>;
+				interrupts = <7>;
+			};
+
+			fast_timer: timer at 90010000 {
+				reg = <0x90010000 0x1000>;
+				interrupts = <17>;
+			};
+
+			uart: serial at 90020000 {
+				reg = <0x90020000 0x1000>;
+				interrupts = <1>;
+			};
+
+			timer0: timer at 900C0000 {
+				reg = <0x900C0000 0x1000>;
+
+				clocks = <&timer_clk>;
+			};
+
+			timer1: timer at 900D0000 {
+				reg = <0x900D0000 0x1000>;
+				interrupts = <19>;
+
+				clocks = <&timer_clk>;
+			};
+
+			watchdog: watchdog at 90060000 {
+				compatible = "arm,amba-primecell";
+				reg = <0x90060000 0x1000>;
+				interrupts = <3>;
+			};
+
+			rtc: rtc at 90090000 {
+				reg = <0x90090000 0x1000>;
+				interrupts = <4>;
+			};
+
+			misc: misc at 900A0000 {
+				reg = <0x900A0000 0x1000>;
+			};
+
+			pwr: pwr at 900B0000 {
+				reg = <0x900B0000 0x1000>;
+				interrupts = <15>;
+			};
+
+			keypad: input at 900E0000 {
+				compatible = "ti,nspire-keypad";
+				reg = <0x900E0000 0x1000>;
+				interrupts = <16>;
+
+				scan-interval = <1000>;
+				row-delay = <200>;
+
+				clocks = <&apb_pclk>;
+			};
+
+			contrast: contrast at 900F0000 {
+				reg = <0x900F0000 0x1000>;
+			};
+
+			led: led at 90110000 {
+				reg = <0x90110000 0x1000>;
+			};
+		};
+	};
+};
-- 
1.8.1.3




From arnd at arndb.de  Thu May 30 09:26:26 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 30 May 2013 15:26:26 +0200
Subject: [PATCH 05/11] ARM: shmobile: APE6EVM LAN9220 support
In-Reply-To: <Pine.LNX.4.64.1305300700150.24272@axis700.grange>
References: <1364954906-16014-1-git-send-email-horms+renesas@verge.net.au>
 <CAOesGMjLiNTR7cqjSmyy2Ux1srgkC5cPO+D8UsRcgHbW8GQ26Q@mail.gmail.com>
 <Pine.LNX.4.64.1305300700150.24272@axis700.grange>
Message-ID: <201305301526.26225.arnd@arndb.de>

On Thursday 30 May 2013, Guennadi Liakhovetski wrote:
> Ok, I didn't write the original implementation of that bus and, therefore, 
> didn't decide how many address cells it shall use. My task was to fix it. 
> And yes, I agree, that there are 2 ways to fix the memory mapping: either 
> define ranges to map from 64-bits to 32-bits, or to change all devices on 
> the bus (currently there's only 1) to use 64-bit "reg" property and use 
> "ranges" with no arguments. Since that bus is clearly within a 32-bit 
> area, I would prefer the former solution not to have to drag 64 bits 
> around an make device nodes simpler. Can we keep this approach or are you 
> strongly against it?

I believe we should attempt to have the DT representation as close as
possible to what the hardware actually does. If this is a AHB bus
or something else that is known to be always 32 bit, I would use
a ranges property and #address-cells=<1>, but if this is a 64-bit
wide AXIv4 instance I would use #address-cells=<2> and probably
omit the ranges.

There is also the case where a device is attached to an external bus
that has 0-based addressing. In that case I would put the actual
translation into the ranges property, with all addresses that
are translated by the bus controller, such as

      lbsc {
               compatible = "simple-bus";
               #address-cells = <1>;
               #size-cells = <1>;
               ranges = <0 0x08000000 0 0x1000000>; /* 16 MB @ 128 MB */

               ethernet at 0 {
			compatible = "smsc,lan9118", "smsc,lan9115";
			reg = <0 0x1000>;
			...

	Arnd


From fabio.baltieri at linaro.org  Thu May 30 09:27:40 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu, 30 May 2013 15:27:40 +0200
Subject: [PATCH 0/5] Various DT fixes related to ux500 ASoC driver
Message-ID: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>

Hi Linus, Lee,

these are various fixes I found while testing the ux500 ASoC driver on HREF
with device-tree.

First two patches are typos in DT files, while the others are
specifically to support ux500 ASoC driver with DT enabled.

The last patch can go in the mfd tree, while the others may safely go
through arm-soc, as there are no build dependencies or regression issues
in general.

Thanks,
Fabio


Fabio Baltieri (5):
  ARM: ux500: Fix trivial typo in v-anamic1 comment
  ARM: ux500: Correct anamic2 typo in DT files
  ARM: ux500: Add DT regulators for ab8500-codec
  ARM: ux500: Provide auxdata to ux500 ASoC driver
  mfd: ab8500-core: Add of_compatible property for ab8500-codec

 arch/arm/boot/dts/dbx5x0.dtsi     | 11 ++++++++---
 arch/arm/boot/dts/href.dtsi       |  2 +-
 arch/arm/boot/dts/hrefv60plus.dts |  2 +-
 arch/arm/boot/dts/snowball.dts    |  2 +-
 arch/arm/mach-ux500/cpu-db8500.c  |  2 ++
 drivers/mfd/ab8500-core.c         |  1 +
 drivers/regulator/ab8500.c        |  8 ++++----
 7 files changed, 18 insertions(+), 10 deletions(-)

-- 
1.8.2



From fabio.baltieri at linaro.org  Thu May 30 09:27:41 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu, 30 May 2013 15:27:41 +0200
Subject: [PATCH 1/5] ARM: ux500: Fix trivial typo in v-anamic1 comment
In-Reply-To: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <1369920465-13905-2-git-send-email-fabio.baltieri@linaro.org>

Fix VAMIC1 LDO comment in DT files to be make it coherent with the
others.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index b6bc4ff..e6ea7ba 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -460,7 +460,7 @@
 						regulator-compatible = "ab8500_ldo_audio";
 					};
 
-					// supply for v-anamic1 VAMic1-LDO
+					// supply for v-anamic1 VAMIC1 LDO
 					ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 						regulator-compatible = "ab8500_ldo_anamic1";
 					};
-- 
1.8.2



From fabio.baltieri at linaro.org  Thu May 30 09:27:42 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu, 30 May 2013 15:27:42 +0200
Subject: [PATCH 2/5] ARM: ux500: Correct anamic2 typo in DT files
In-Reply-To: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <1369920465-13905-3-git-send-email-fabio.baltieri@linaro.org>

Fix typo of VAMIC2 LDO regulator name in some DT-related files.  This
patch replaces all occurrences with the right name.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi     | 4 ++--
 arch/arm/boot/dts/href.dtsi       | 2 +-
 arch/arm/boot/dts/hrefv60plus.dts | 2 +-
 arch/arm/boot/dts/snowball.dts    | 2 +-
 drivers/regulator/ab8500.c        | 8 ++++----
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index e6ea7ba..d0b6e32 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -466,8 +466,8 @@
 					};
 
 					// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
-					ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
-						regulator-compatible = "ab8500_ldo_amamic2";
+					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+						regulator-compatible = "ab8500_ldo_anamic2";
 					};
 
 					// supply for v-dmic; VDMIC LDO
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index c0bc426..4a53c48 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -256,7 +256,7 @@
 						regulator-name = "V-AMIC1";
 					};
 
-					ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 						regulator-name = "V-AMIC2";
 					};
 
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2b587a7..4f04af8 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -192,7 +192,7 @@
 						regulator-name = "V-AMIC1";
 					};
 
-					ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 						regulator-name = "V-AMIC2";
 					};
 
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index db5db24..557d75e 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -336,7 +336,7 @@
 						regulator-name = "V-AMIC1";
 					};
 
-					ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 						regulator-name = "V-AMIC2";
 					};
 
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
index f6656b8..a19045e 100644
--- a/drivers/regulator/ab8500.c
+++ b/drivers/regulator/ab8500.c
@@ -2901,7 +2901,7 @@ static struct of_regulator_match ab8500_regulator_match[] = {
 	{ .name	= "ab8500_ldo_tvout",   .driver_data = (void *) AB8500_LDO_TVOUT, },
 	{ .name = "ab8500_ldo_audio",   .driver_data = (void *) AB8500_LDO_AUDIO, },
 	{ .name	= "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
-	{ .name	= "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
+	{ .name	= "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
 	{ .name	= "ab8500_ldo_dmic",    .driver_data = (void *) AB8500_LDO_DMIC, },
 	{ .name	= "ab8500_ldo_ana",     .driver_data = (void *) AB8500_LDO_ANA, },
 };
@@ -2917,7 +2917,7 @@ static struct of_regulator_match ab8505_regulator_match[] = {
 	{ .name	= "ab8500_ldo_adc",	.driver_data = (void *) AB8505_LDO_ADC, },
 	{ .name = "ab8500_ldo_audio",   .driver_data = (void *) AB8505_LDO_AUDIO, },
 	{ .name	= "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
-	{ .name	= "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
+	{ .name	= "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
 	{ .name	= "ab8500_ldo_aux8",    .driver_data = (void *) AB8505_LDO_AUX8, },
 	{ .name	= "ab8500_ldo_ana",     .driver_data = (void *) AB8505_LDO_ANA, },
 };
@@ -2933,7 +2933,7 @@ static struct of_regulator_match ab8540_regulator_match[] = {
 	{ .name	= "ab8500_ldo_tvout",   .driver_data = (void *) AB8540_LDO_TVOUT, },
 	{ .name = "ab8500_ldo_audio",   .driver_data = (void *) AB8540_LDO_AUDIO, },
 	{ .name	= "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
-	{ .name	= "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
+	{ .name	= "ab8500_ldo_anamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
 	{ .name	= "ab8500_ldo_dmic",    .driver_data = (void *) AB8540_LDO_DMIC, },
 	{ .name	= "ab8500_ldo_ana",     .driver_data = (void *) AB8540_LDO_ANA, },
 	{ .name = "ab8500_ldo_sdio",    .driver_data = (void *) AB8540_LDO_SDIO, },
@@ -2948,7 +2948,7 @@ static struct of_regulator_match ab9540_regulator_match[] = {
 	{ .name	= "ab8500_ldo_tvout",   .driver_data = (void *) AB9540_LDO_TVOUT, },
 	{ .name = "ab8500_ldo_audio",   .driver_data = (void *) AB9540_LDO_AUDIO, },
 	{ .name	= "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
-	{ .name	= "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
+	{ .name	= "ab8500_ldo_anamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
 	{ .name	= "ab8500_ldo_dmic",    .driver_data = (void *) AB9540_LDO_DMIC, },
 	{ .name	= "ab8500_ldo_ana",     .driver_data = (void *) AB9540_LDO_ANA, },
 };
-- 
1.8.2



From fabio.baltieri at linaro.org  Thu May 30 09:27:43 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu, 30 May 2013 15:27:43 +0200
Subject: [PATCH 3/5] ARM: ux500: Add DT regulators for ab8500-codec
In-Reply-To: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <1369920465-13905-4-git-send-email-fabio.baltieri@linaro.org>

Add regulator DT bindings for the ab8500-codec driver.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index d0b6e32..8e14042 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -410,6 +410,11 @@
 				codec: ab8500-codec {
 					compatible = "stericsson,ab8500-codec";
 
+					V-AUD-supply = <&ab8500_ldo_audio_reg>;
+					V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
+					V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
+					V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
+
 					stericsson,earpeice-cmv = <950>; /* Units in mV. */
 				};
 
-- 
1.8.2



From fabio.baltieri at linaro.org  Thu May 30 09:27:44 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu, 30 May 2013 15:27:44 +0200
Subject: [PATCH 4/5] ARM: ux500: Provide auxdata to ux500 ASoC driver
In-Reply-To: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <1369920465-13905-5-git-send-email-fabio.baltieri@linaro.org>

Ux500 ASoC driver is expected to have a specific device name to get
clock resources correctly.  This patch provides the necessary
OF_DEV_AUXDATA to match the name in DT and non-DT cases.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 46cca52..fb3d5a2 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -277,6 +277,8 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
 	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
+	OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
+			NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-- 
1.8.2



From fabio.baltieri at linaro.org  Thu May 30 09:27:45 2013
From: fabio.baltieri at linaro.org (Fabio Baltieri)
Date: Thu, 30 May 2013 15:27:45 +0200
Subject: [PATCH 5/5] mfd: ab8500-core: Add of_compatible property for
 ab8500-codec
In-Reply-To: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <1369920465-13905-6-git-send-email-fabio.baltieri@linaro.org>

Add of_compatible string to the ab8500-codec cell to allow the driver to
grab handlers such as regulators from device-tree when available.

Signed-off-by: Fabio Baltieri <fabio.baltieri at linaro.org>
---
 drivers/mfd/ab8500-core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 1863985..3efb356 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -1120,6 +1120,7 @@ static struct mfd_cell ab8500_devs[] = {
 	},
 	{
 		.name = "ab8500-codec",
+		.of_compatible = "stericsson,ab8500-codec",
 	},
 };
 
-- 
1.8.2



From subashrp at gmail.com  Thu May 30 09:31:09 2013
From: subashrp at gmail.com (Subash Patel)
Date: Thu, 30 May 2013 19:01:09 +0530
Subject: [PATCH 00/14] Random LPAE-related patches
In-Reply-To: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
Message-ID: <51A7549D.9000103@gmail.com>

Hi Will,

Sorry for late response, as I was on vacation.

Thanks for these patches. I have tested these patches on exynos5440 
platform. It hasnt affected LPAE functionality for us from previous 
versions(posted by Cyril). You can use "Tested-By: Subash Patel 
<subash.rp at samsung.com>" as you deem necessary.

Regards,
Subash

On 05/17/2013 10:37 PM, Will Deacon wrote:
> Hello,
>
> This is a collection of LPAE-related patches (mostly fixes) that have
> been kicking around for a while and I've been collecting in one place.
> There were some extra patches for bootmem, but they produced lots of
> warnings and need more thought, so they've not been included here.
>
> All comments welcome,
>
> Will
>
> Cyril Chemparathy (9):
>    ARM: LPAE: use signed arithmetic for mask definitions
>    ARM: LPAE: use phys_addr_t in switch_mm()
>    ARM: LPAE: use 64-bit accessors for TTBR registers
>    ARM: LPAE: factor out T1SZ and TTBR1 computations
>    ARM: LPAE: accomodate >32-bit addresses for page table base
>    ARM: mm: use physical addresses in highmem sanity checks
>    ARM: fix type of PHYS_PFN_OFFSET to unsigned long
>    ARM: mm: cleanup checks for membank overlap with vmalloc area
>    ARM: mm: clean up membank size limit checks
>
> Vitaly Andrianov (3):
>    ARM: LPAE: use phys_addr_t in alloc_init_pud()
>    ARM: LPAE: use phys_addr_t in free_memmap()
>    ARM: LPAE: use phys_addr_t for initrd location
>
> Will Deacon (2):
>    ARM: lpae: fix definition of PTE_HWTABLE_PTRS
>    ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions
>
>   arch/arm/include/asm/memory.h               | 18 +++++++++-
>   arch/arm/include/asm/page.h                 |  2 +-
>   arch/arm/include/asm/pgtable-3level-hwdef.h | 20 +++++++++++
>   arch/arm/include/asm/pgtable-3level.h       |  8 ++---
>   arch/arm/include/asm/proc-fns.h             | 26 ++++++++++----
>   arch/arm/include/uapi/asm/hwcap.h           |  2 +-
>   arch/arm/kernel/head.S                      | 10 +++---
>   arch/arm/kernel/setup.c                     |  8 ++++-
>   arch/arm/kernel/smp.c                       | 11 ++++--
>   arch/arm/mm/context.c                       |  9 ++---
>   arch/arm/mm/init.c                          | 19 ++++++-----
>   arch/arm/mm/mmu.c                           | 49 +++++++++-----------------
>   arch/arm/mm/proc-v7-3level.S                | 53 +++++++++++++++--------------
>   13 files changed, 139 insertions(+), 96 deletions(-)
>


From stefano.stabellini at eu.citrix.com  Thu May 30 09:33:42 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 14:33:42 +0100
Subject: [PATCH v5 0/4] xen/arm: CONFIG_PARAVIRT and stolen ticks
 accounting
Message-ID: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>

Hi all,
this patch series introduces stolen ticks accounting for Xen on ARM.
Stolen ticks are clocksource ticks that have been "stolen" from the cpu,
typically because Linux is running in a virtual machine and the vcpu has
been descheduled.
To account for these ticks we introduce CONFIG_PARAVIRT and pv_time_ops
so that we can make use of:

kernel/sched/cputime.c:steal_account_process_tick


I am starting to be pretty confident about this patch series.

Please advice on what tree I should use to get this stuff upstream: most
of the changes are Xen specific, but it also contains few generic ARM
changes (the introduction of CONFIG_PARAVIRT and paravirt.c on ARM) and
a couple of lines in kernel/sched/cputime.c (a missing include).



Stefano Stabellini (4):
      xen: move xen_setup_runstate_info and get_runstate_snapshot to drivers/xen/time.c
      kernel: missing include in cputime.c
      arm: introduce CONFIG_PARAVIRT, PARAVIRT_TIME_ACCOUNTING and pv_time_ops
      xen/arm: account for stolen ticks

 arch/arm/Kconfig                |   20 +++++++++
 arch/arm/include/asm/paravirt.h |   19 ++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   25 +++++++++++
 arch/arm/xen/enlighten.c        |   21 +++++++++
 arch/ia64/xen/time.c            |   48 +++------------------
 arch/x86/xen/time.c             |   76 +--------------------------------
 drivers/xen/Makefile            |    2 +-
 drivers/xen/time.c              |   91 +++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h           |    5 ++
 kernel/sched/cputime.c          |    4 +-
 11 files changed, 193 insertions(+), 119 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c
 create mode 100644 drivers/xen/time.c


git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen.git lost_ticks_5

Cheers,

Stefano


From stefano.stabellini at eu.citrix.com  Thu May 30 09:35:00 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 14:35:00 +0100
Subject: [PATCH v5 2/4] kernel: missing include in cputime.c
In-Reply-To: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
Message-ID: <1369920902-3546-2-git-send-email-stefano.stabellini@eu.citrix.com>

steal_account_process_tick calls paravirt_steal_clock, but paravirt.h is
currently missing amoung the included header files.
Add include asm/paravirt.h ifdef CONFIG_PARAVIRT.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: mingo at redhat.com
CC: peterz at infradead.org

Changes in v5:
- add ifdef CONFIG_PARAVIRT.
---
 kernel/sched/cputime.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
index cc2dc3ee..317a578 100644
--- a/kernel/sched/cputime.c
+++ b/kernel/sched/cputime.c
@@ -5,7 +5,9 @@
 #include <linux/static_key.h>
 #include <linux/context_tracking.h>
 #include "sched.h"
-
+#ifdef CONFIG_PARAVIRT
+#include <asm/paravirt.h>
+#endif
 
 #ifdef CONFIG_IRQ_TIME_ACCOUNTING
 
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 09:35:01 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 14:35:01 +0100
Subject: [PATCH v5 3/4] arm: introduce CONFIG_PARAVIRT,
 PARAVIRT_TIME_ACCOUNTING and pv_time_ops
In-Reply-To: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
Message-ID: <1369920902-3546-3-git-send-email-stefano.stabellini@eu.citrix.com>

Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.

The only paravirt interface supported is pv_time_ops.steal_clock, so no
runtime pvops patching needed.

This allows us to make use of steal_account_process_tick for stolen
ticks accounting.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Christopher Covington <cov at codeaurora.org>
CC: linux at arm.linux.org.uk
CC: will.deacon at arm.com
CC: nico at linaro.org
CC: marc.zyngier at arm.com
CC: cov at codeaurora.org
CC: arnd at arndb.de
CC: olof at lixom.net

Changes in v3:
- improve commit description and Kconfig help text;
- no need to initialize pv_time_ops;
- add PARAVIRT_TIME_ACCOUNTING.
---
 arch/arm/Kconfig                |   20 ++++++++++++++++++++
 arch/arm/include/asm/paravirt.h |   19 +++++++++++++++++++
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/paravirt.c      |   25 +++++++++++++++++++++++++
 4 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/paravirt.h
 create mode 100644 arch/arm/kernel/paravirt.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..5621a02 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1786,12 +1786,32 @@ config XEN_DOM0
 	def_bool y
 	depends on XEN
 
+config PARAVIRT
+	bool "Enable paravirtualization code"
+	---help---
+	  This changes the kernel so it can modify itself when it is run
+	  under a hypervisor, potentially improving performance significantly
+	  over full virtualization.
+
+config PARAVIRT_TIME_ACCOUNTING
+	bool "Paravirtual steal time accounting"
+	select PARAVIRT
+	default n
+	---help---
+	  Select this option to enable fine granularity task steal time
+	  accounting. Time spent executing other tasks in parallel with
+	  the current vCPU is discounted from the vCPU power. To account for
+	  that, there can be a small performance impact.
+
+	  If in doubt, say N here.
+
 config XEN
 	bool "Xen guest support on ARM (EXPERIMENTAL)"
 	depends on ARM && AEABI && OF
 	depends on CPU_V7 && !CPU_V6
 	depends on !GENERIC_ATOMIC64
 	select ARM_PSCI
+	select PARAVIRT
 	help
 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
diff --git a/arch/arm/include/asm/paravirt.h b/arch/arm/include/asm/paravirt.h
new file mode 100644
index 0000000..3b95bc6
--- /dev/null
+++ b/arch/arm/include/asm/paravirt.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_PARAVIRT_H
+#define _ASM_ARM_PARAVIRT_H
+
+struct static_key;
+extern struct static_key paravirt_steal_enabled;
+extern struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops {
+	unsigned long long (*steal_clock)(int cpu);
+};
+extern struct pv_time_ops pv_time_ops;
+
+static inline u64 paravirt_steal_clock(int cpu)
+{
+	return pv_time_ops.steal_clock(cpu);
+}
+
+
+#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338e..d911db6 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 ifneq ($(CONFIG_ARCH_EBSA110),y)
   obj-y		+= io.o
 endif
+obj-$(CONFIG_PARAVIRT)	+= paravirt.o
 
 head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
diff --git a/arch/arm/kernel/paravirt.c b/arch/arm/kernel/paravirt.c
new file mode 100644
index 0000000..53f371e
--- /dev/null
+++ b/arch/arm/kernel/paravirt.c
@@ -0,0 +1,25 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 Citrix Systems
+ *
+ * Author: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
+ */
+
+#include <linux/export.h>
+#include <linux/jump_label.h>
+#include <linux/types.h>
+#include <asm/paravirt.h>
+
+struct static_key paravirt_steal_enabled;
+struct static_key paravirt_steal_rq_enabled;
+
+struct pv_time_ops pv_time_ops;
+EXPORT_SYMBOL_GPL(pv_time_ops);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 09:35:02 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 14:35:02 +0100
Subject: [PATCH v5 4/4] xen/arm: account for stolen ticks
In-Reply-To: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
Message-ID: <1369920902-3546-4-git-send-email-stefano.stabellini@eu.citrix.com>

Register the runstate_memory_area with the hypervisor.
Use pv_time_ops.steal_clock to account for stolen ticks.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>


Changes in v4:
- don't use paravirt_steal_rq_enabled: we do not support retrieving
stolen ticks for vcpus other than one we are running on.

Changes in v3:
- use BUG_ON and smp_processor_id.
---
 arch/arm/xen/enlighten.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 13609e0..49839d8 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -14,7 +14,10 @@
 #include <xen/xen-ops.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <asm/arch_timer.h>
 #include <asm/system_misc.h>
+#include <asm/paravirt.h>
+#include <linux/jump_label.h>
 #include <linux/interrupt.h>
 #include <linux/irqreturn.h>
 #include <linux/module.h>
@@ -152,6 +155,19 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
 }
 EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 
+unsigned long long xen_stolen_accounting(int cpu)
+{
+	struct vcpu_runstate_info state;
+
+	BUG_ON(cpu != smp_processor_id());
+
+	xen_get_runstate_snapshot(&state);
+
+	WARN_ON(state.state != RUNSTATE_running);
+
+	return state.time[RUNSTATE_runnable] + state.time[RUNSTATE_offline];
+}
+
 static void __init xen_percpu_init(void *unused)
 {
 	struct vcpu_register_vcpu_info info;
@@ -169,6 +185,8 @@ static void __init xen_percpu_init(void *unused)
 	BUG_ON(err);
 	per_cpu(xen_vcpu, cpu) = vcpup;
 
+	xen_setup_runstate_info(cpu);
+
 	enable_percpu_irq(xen_events_irq, 0);
 }
 
@@ -300,6 +318,9 @@ static int __init xen_init_events(void)
 
 	on_each_cpu(xen_percpu_init, NULL, 0);
 
+	pv_time_ops.steal_clock = xen_stolen_accounting;
+	static_key_slow_inc(&paravirt_steal_enabled);
+
 	return 0;
 }
 postcore_initcall(xen_init_events);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 09:34:59 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 14:34:59 +0100
Subject: [PATCH v5 1/4] xen: move xen_setup_runstate_info and
 get_runstate_snapshot to drivers/xen/time.c
In-Reply-To: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301426520.4799@kaball.uk.xensource.com>
Message-ID: <1369920902-3546-1-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell at citrix.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
CC: konrad.wilk at oracle.com

Changes in v2:
- leave do_stolen_accounting in arch/x86/xen/time.c;
- use the new common functions in arch/ia64/xen/time.c.
---
 arch/ia64/xen/time.c  |   48 +++----------------------
 arch/x86/xen/time.c   |   76 +----------------------------------------
 drivers/xen/Makefile  |    2 +-
 drivers/xen/time.c    |   91 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/xen/xen-ops.h |    5 +++
 5 files changed, 104 insertions(+), 118 deletions(-)
 create mode 100644 drivers/xen/time.c

diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
index 1f8244a..79a0b8c 100644
--- a/arch/ia64/xen/time.c
+++ b/arch/ia64/xen/time.c
@@ -34,53 +34,17 @@
 
 #include "../kernel/fsyscall_gtod_data.h"
 
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
 static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
 static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
 
 /* taken from i386/kernel/time-xen.c */
 static void xen_init_missing_ticks_accounting(int cpu)
 {
-	struct vcpu_register_runstate_memory_area area;
-	struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
-	int rc;
+	xen_setup_runstate_info(&runstate);
 
-	memset(runstate, 0, sizeof(*runstate));
-
-	area.addr.v = runstate;
-	rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu,
-				&area);
-	WARN_ON(rc && rc != -ENOSYS);
-
-	per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
-	per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
-					    + runstate->time[RUNSTATE_offline];
-}
-
-/*
- * Runstate accounting
- */
-/* stolen from arch/x86/xen/time.c */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = state->state_entry_time;
-		rmb();
-		*res = *state;
-		rmb();
-	} while (state->state_entry_time != state_time);
+	per_cpu(xen_blocked_time, cpu) = runstate.time[RUNSTATE_blocked];
+	per_cpu(xen_stolen_time, cpu) = runstate.time[RUNSTATE_runnable]
+					    + runstate.time[RUNSTATE_offline];
 }
 
 #define NS_PER_TICK (1000000000LL/HZ)
@@ -94,7 +58,7 @@ consider_steal_time(unsigned long new_itm)
 	struct vcpu_runstate_info runstate;
 	struct task_struct *p = current;
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	/*
 	 * Check for vcpu migration effect
@@ -202,7 +166,7 @@ static unsigned long long xen_sched_clock(void)
 	 */
 	now = ia64_native_sched_clock();
 
-	get_runstate_snapshot(&runstate);
+	xen_get_runstate_snapshot(&runstate);
 
 	WARN_ON(runstate.state != RUNSTATE_running);
 
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 3d88bfd..c0ca15e 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -30,9 +30,6 @@
 #define TIMER_SLOP	100000
 #define NS_PER_TICK	(1000000000LL / HZ)
 
-/* runstate info updated by Xen */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
-
 /* snapshots of runstate info */
 static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 
@@ -40,77 +37,6 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 static DEFINE_PER_CPU(u64, xen_residual_stolen);
 static DEFINE_PER_CPU(u64, xen_residual_blocked);
 
-/* return an consistent snapshot of 64-bit time/counter value */
-static u64 get64(const u64 *p)
-{
-	u64 ret;
-
-	if (BITS_PER_LONG < 64) {
-		u32 *p32 = (u32 *)p;
-		u32 h, l;
-
-		/*
-		 * Read high then low, and then make sure high is
-		 * still the same; this will only loop if low wraps
-		 * and carries into high.
-		 * XXX some clean way to make this endian-proof?
-		 */
-		do {
-			h = p32[1];
-			barrier();
-			l = p32[0];
-			barrier();
-		} while (p32[1] != h);
-
-		ret = (((u64)h) << 32) | l;
-	} else
-		ret = *p;
-
-	return ret;
-}
-
-/*
- * Runstate accounting
- */
-static void get_runstate_snapshot(struct vcpu_runstate_info *res)
-{
-	u64 state_time;
-	struct vcpu_runstate_info *state;
-
-	BUG_ON(preemptible());
-
-	state = &__get_cpu_var(xen_runstate);
-
-	/*
-	 * The runstate info is always updated by the hypervisor on
-	 * the current CPU, so there's no need to use anything
-	 * stronger than a compiler barrier when fetching it.
-	 */
-	do {
-		state_time = get64(&state->state_entry_time);
-		barrier();
-		*res = *state;
-		barrier();
-	} while (get64(&state->state_entry_time) != state_time);
-}
-
-/* return true when a vcpu could run but has no real cpu to run on */
-bool xen_vcpu_stolen(int vcpu)
-{
-	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
-}
-
-void xen_setup_runstate_info(int cpu)
-{
-	struct vcpu_register_runstate_memory_area area;
-
-	area.addr.v = &per_cpu(xen_runstate, cpu);
-
-	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
-			       cpu, &area))
-		BUG();
-}
-
 static void do_stolen_accounting(void)
 {
 	struct vcpu_runstate_info state;
@@ -118,7 +44,7 @@ static void do_stolen_accounting(void)
 	s64 blocked, runnable, offline, stolen;
 	cputime_t ticks;
 
-	get_runstate_snapshot(&state);
+	xen_get_runstate_snapshot(&state);
 
 	WARN_ON(state.state != RUNSTATE_running);
 
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index eabd0ee..2bf461a 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -3,7 +3,7 @@ obj-y	+= manage.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 endif
 obj-$(CONFIG_X86)			+= fallback.o
-obj-y	+= grant-table.o features.o events.o balloon.o
+obj-y	+= grant-table.o features.o events.o balloon.o time.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
diff --git a/drivers/xen/time.c b/drivers/xen/time.c
new file mode 100644
index 0000000..c2e39d3
--- /dev/null
+++ b/drivers/xen/time.c
@@ -0,0 +1,91 @@
+/*
+ * Xen stolen ticks accounting.
+ */
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/math64.h>
+#include <linux/gfp.h>
+
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+
+#include <xen/events.h>
+#include <xen/features.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/vcpu.h>
+#include <xen/xen-ops.h>
+
+/* runstate info updated by Xen */
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
+
+/* return an consistent snapshot of 64-bit time/counter value */
+static u64 get64(const u64 *p)
+{
+	u64 ret;
+
+	if (BITS_PER_LONG < 64) {
+		u32 *p32 = (u32 *)p;
+		u32 h, l;
+
+		/*
+		 * Read high then low, and then make sure high is
+		 * still the same; this will only loop if low wraps
+		 * and carries into high.
+		 * XXX some clean way to make this endian-proof?
+		 */
+		do {
+			h = p32[1];
+			barrier();
+			l = p32[0];
+			barrier();
+		} while (p32[1] != h);
+
+		ret = (((u64)h) << 32) | l;
+	} else
+		ret = *p;
+
+	return ret;
+}
+
+/*
+ * Runstate accounting
+ */
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res)
+{
+	u64 state_time;
+	struct vcpu_runstate_info *state;
+
+	BUG_ON(preemptible());
+
+	state = &__get_cpu_var(xen_runstate);
+
+	/*
+	 * The runstate info is always updated by the hypervisor on
+	 * the current CPU, so there's no need to use anything
+	 * stronger than a compiler barrier when fetching it.
+	 */
+	do {
+		state_time = get64(&state->state_entry_time);
+		barrier();
+		*res = *state;
+		barrier();
+	} while (get64(&state->state_entry_time) != state_time);
+}
+
+/* return true when a vcpu could run but has no real cpu to run on */
+bool xen_vcpu_stolen(int vcpu)
+{
+	return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
+}
+
+void xen_setup_runstate_info(int cpu)
+{
+	struct vcpu_register_runstate_memory_area area;
+
+	area.addr.v = &per_cpu(xen_runstate, cpu);
+
+	if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
+			       cpu, &area))
+		BUG();
+}
+
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index d6fe062..4fd4e47 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -3,6 +3,7 @@
 
 #include <linux/percpu.h>
 #include <asm/xen/interface.h>
+#include <xen/interface/vcpu.h>
 
 DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
 
@@ -16,6 +17,10 @@ void xen_mm_unpin_all(void);
 void xen_timer_resume(void);
 void xen_arch_resume(void);
 
+bool xen_vcpu_stolen(int vcpu);
+void xen_setup_runstate_info(int cpu);
+void xen_get_runstate_snapshot(struct vcpu_runstate_info *res);
+
 int xen_setup_shutdown_event(void);
 
 extern unsigned long *xen_contiguous_bitmap;
-- 
1.7.2.5



From mpa at pengutronix.de  Thu May 30 09:47:04 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 15:47:04 +0200
Subject: [PATCH] serial/imx: disable hardware flow control at startup
Message-ID: <1369921624-5595-1-git-send-email-mpa@pengutronix.de>

From: Lucas Stach <l.stach at pengutronix.de>

We only want to enable hardware flow control if RTS/CTS pins
are connected.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

 drivers/tty/serial/imx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 147c9e1..8cdfbd3 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -761,6 +761,8 @@ static int imx_startup(struct uart_port *port)
 
 	temp = readl(sport->port.membase + UCR2);
 	temp |= (UCR2_RXEN | UCR2_TXEN);
+	if (!sport->have_rtscts)
+		temp |= UCR2_IRTS;
 	writel(temp, sport->port.membase + UCR2);
 
 	if (USE_IRDA(sport)) {
-- 
1.8.2.1



From maxime.ripard at free-electrons.com  Thu May 30 09:49:19 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:19 +0200
Subject: [PATCHv4 0/6] ARM: sunxi: Add support for A10 Ethernet controller
Message-ID: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>

Hi,

The Allwinner A10 SoC has an ethernet controller that seem to be specific to
Allwinner. This IP has no public documentation, so exact
details are quite sparse, and this code come from refactored Allwinner
code.

The rework to use NAPI is taking more time than expected, I'm still working
on it, but it could probably be sent as a follow-up patch.

Thanks,
Maxime

Changes from v3:
  - Moved the MDIO driver to drivers/net/phy
  - Add error checking in the mdio driver for regulator_enable, that also
    silences a warning
  - Fixed the phy address in the cubieboard device tree (From Emilio Lopez)
  - Fix broken builds by selecting CONFIG_REGULATOR (From Emilio Lopez)

Changes from v2:
  - Split the MDIO controller to a separate driver and make use of standards
    device tree bindings
  - Fixed various minor things as suggested by Florian Fainelli
  - Added clock support now that we have a clock driver

Changes from v1:
  - Use phylib for the phy-related functions
  - Use an optional regulator to power up the phy
  - Rename the driver from Davicom Wemac to Allwinner EMAC, since it's the name
    mentionned in the datasheet, and we have no strong evidence of a
    relationship with Davicom
  - Fix various small things around the driver: add defines for undocumented
    values, fix documentation name and compatible example, etc.

Maxime Ripard (4):
  net: Add MDIO bus driver for the Allwinner EMAC
  ARM: sun4i: Add muxing options for the ethernet controller
  ARM: sunxi: Add EMAC controller node to sun4i DTSI
  ARM: sunxi: Add EMAC Controller to Hackberry dt

Stefan Roese (2):
  net: Add EMAC ethernet driver found on Allwinner A10 SoC's
  ARM: cubieboard: Enable ethernet (EMAC) support in dts

 .../bindings/net/allwinner,sun4i-emac.txt          |  22 +
 .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  15 +
 arch/arm/boot/dts/sun4i-a10-hackberry.dts          |  41 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  27 +
 drivers/net/ethernet/Kconfig                       |   1 +
 drivers/net/ethernet/Makefile                      |   1 +
 drivers/net/ethernet/allwinner/Kconfig             |  36 +
 drivers/net/ethernet/allwinner/Makefile            |   5 +
 drivers/net/ethernet/allwinner/sun4i-emac.c        | 960 +++++++++++++++++++++
 drivers/net/ethernet/allwinner/sun4i-emac.h        | 108 +++
 drivers/net/phy/Kconfig                            |  10 +
 drivers/net/phy/Makefile                           |   1 +
 drivers/net/phy/mdio-sun4i.c                       | 194 +++++
 14 files changed, 1447 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
 create mode 100644 drivers/net/ethernet/allwinner/Kconfig
 create mode 100644 drivers/net/ethernet/allwinner/Makefile
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h
 create mode 100644 drivers/net/phy/mdio-sun4i.c

-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Thu May 30 09:49:20 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:20 +0200
Subject: [PATCHv4 1/6] net: Add EMAC ethernet driver found on Allwinner A10
 SoC's
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369921765-3367-2-git-send-email-maxime.ripard@free-electrons.com>

From: Stefan Roese <sr at denx.de>

The Allwinner A10 has an ethernet controller that seem to be developped
internally by them.

The exact feature set of this controller is unknown, since there is no
public documentation for this IP, and this driver is mostly the one
published by Allwinner that has been heavily cleaned up.

Signed-off-by: Stefan Roese <sr at denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Tested-by: Richard Genoud <richard.genoud at gmail.com>
---
 .../bindings/net/allwinner,sun4i-emac.txt          |  22 +
 drivers/net/ethernet/Kconfig                       |   1 +
 drivers/net/ethernet/Makefile                      |   1 +
 drivers/net/ethernet/allwinner/Kconfig             |  36 +
 drivers/net/ethernet/allwinner/Makefile            |   5 +
 drivers/net/ethernet/allwinner/sun4i-emac.c        | 960 +++++++++++++++++++++
 drivers/net/ethernet/allwinner/sun4i-emac.h        | 108 +++
 7 files changed, 1133 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
 create mode 100644 drivers/net/ethernet/allwinner/Kconfig
 create mode 100644 drivers/net/ethernet/allwinner/Makefile
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
 create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
new file mode 100644
index 0000000..b90bfcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
@@ -0,0 +1,22 @@
+* Allwinner EMAC ethernet controller
+
+Required properties:
+- compatible: should be "allwinner,sun4i-emac".
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+- phy: A phandle to a phy node defining the PHY address (as the reg
+  property, a single integer).
+- clocks: A phandle to the reference clock for this device
+
+Optional properties:
+- (local-)mac-address: mac address to be used by this driver
+
+Example:
+
+emac: ethernet at 01c0b000 {
+       compatible = "allwinner,sun4i-emac";
+       reg = <0x01c0b000 0x1000>;
+       interrupts = <55>;
+       clocks = <&ahb_gates 17>;
+       phy = <&phy0>;
+};
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index ed956e0..18fd6fb 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -20,6 +20,7 @@ config SUNGEM_PHY
 source "drivers/net/ethernet/3com/Kconfig"
 source "drivers/net/ethernet/adaptec/Kconfig"
 source "drivers/net/ethernet/aeroflex/Kconfig"
+source "drivers/net/ethernet/allwinner/Kconfig"
 source "drivers/net/ethernet/alteon/Kconfig"
 source "drivers/net/ethernet/amd/Kconfig"
 source "drivers/net/ethernet/apple/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 8268d85..009da27 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_VENDOR_3COM) += 3com/
 obj-$(CONFIG_NET_VENDOR_8390) += 8390/
 obj-$(CONFIG_NET_VENDOR_ADAPTEC) += adaptec/
 obj-$(CONFIG_GRETH) += aeroflex/
+obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig
new file mode 100644
index 0000000..66d3532
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -0,0 +1,36 @@
+#
+# Allwinner device configuration
+#
+
+config NET_VENDOR_ALLWINNER
+       bool "Allwinner devices"
+       default y
+       depends on ARCH_SUNXI
+       ---help---
+         If you have a network (Ethernet) card belonging to this
+	 class, say Y and read the Ethernet-HOWTO, available from
+	 <http://www.tldp.org/docs.html#howto>.
+
+	 Note that the answer to this question doesn't directly
+	 affect the kernel: saying N will just cause the configurator
+	 to skip all the questions about Allwinner cards. If you say Y,
+	 you will be asked for your specific card in the following
+	 questions.
+
+if NET_VENDOR_ALLWINNER
+
+config SUN4I_EMAC
+        tristate "Allwinner A10 EMAC support"
+	depends on ARCH_SUNXI
+	depends on OF
+	select CRC32
+	select NET_CORE
+	select MII
+	select PHYLIB
+        ---help---
+          Support for Allwinner A10 EMAC ethernet driver.
+
+          To compile this driver as a module, choose M here.  The module
+          will be called sun4i-emac.
+
+endif # NET_VENDOR_ALLWINNER
diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile
new file mode 100644
index 0000000..03129f7
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Allwinner device drivers.
+#
+
+obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
new file mode 100644
index 0000000..b411344
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
@@ -0,0 +1,960 @@
+/*
+ * Allwinner EMAC Fast Ethernet driver for Linux.
+ *
+ * Copyright 2012-2013 Stefan Roese <sr at denx.de>
+ * Copyright 2013 Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997  Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_mdio.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+
+#include "sun4i-emac.h"
+
+#define DRV_NAME		"sun4i-emac"
+#define DRV_VERSION		"1.02"
+
+#define EMAC_MAX_FRAME_LEN	0x0600
+
+/* Transmit timeout, default 5 seconds. */
+static int watchdog = 5000;
+module_param(watchdog, int, 0400);
+MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
+
+/* EMAC register address locking.
+ *
+ * The EMAC uses an address register to control where data written
+ * to the data register goes. This means that the address register
+ * must be preserved over interrupts or similar calls.
+ *
+ * During interrupt and other critical calls, a spinlock is used to
+ * protect the system, but the calls themselves save the address
+ * in the address register in case they are interrupting another
+ * access to the device.
+ *
+ * For general accesses a lock is provided so that calls which are
+ * allowed to sleep are serialised so that the address register does
+ * not need to be saved. This lock also serves to serialise access
+ * to the EEPROM and PHY access registers which are shared between
+ * these two devices.
+ */
+
+/* The driver supports the original EMACE, and now the two newer
+ * devices, EMACA and EMACB.
+ */
+
+struct emac_board_info {
+	struct clk		*clk;
+	struct device		*dev;
+	struct platform_device	*pdev;
+	spinlock_t		lock;
+	void __iomem		*membase;
+	u32			msg_enable;
+	struct net_device	*ndev;
+	struct sk_buff		*skb_last;
+	u16			tx_fifo_stat;
+
+	int			emacrx_completed_flag;
+
+	struct phy_device	*phy_dev;
+	struct device_node	*phy_node;
+	unsigned int		link;
+	unsigned int		speed;
+	unsigned int		duplex;
+
+	phy_interface_t		phy_interface;
+};
+
+static void emac_update_speed(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned int reg_val;
+
+	/* set EMAC SPEED, depend on PHY  */
+	reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
+	reg_val &= ~(0x1 << 8);
+	if (db->speed == SPEED_100)
+		reg_val |= 1 << 8;
+	writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
+}
+
+static void emac_update_duplex(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned int reg_val;
+
+	/* set duplex depend on phy */
+	reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
+	reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
+	if (db->duplex)
+		reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
+	writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
+}
+
+static void emac_handle_link_change(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	struct phy_device *phydev = db->phy_dev;
+	unsigned long flags;
+	int status_change = 0;
+
+	if (phydev->link) {
+		if (db->speed != phydev->speed) {
+			spin_lock_irqsave(&db->lock, flags);
+			db->speed = phydev->speed;
+			emac_update_speed(dev);
+			spin_unlock_irqrestore(&db->lock, flags);
+			status_change = 1;
+		}
+
+		if (db->duplex != phydev->duplex) {
+			spin_lock_irqsave(&db->lock, flags);
+			db->duplex = phydev->duplex;
+			emac_update_duplex(dev);
+			spin_unlock_irqrestore(&db->lock, flags);
+			status_change = 1;
+		}
+	}
+
+	if (phydev->link != db->link) {
+		if (!phydev->link) {
+			db->speed = 0;
+			db->duplex = -1;
+		}
+		db->link = phydev->link;
+
+		status_change = 1;
+	}
+
+	if (status_change)
+		phy_print_status(phydev);
+}
+
+static int emac_mdio_probe(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+
+	/* to-do: PHY interrupts are currently not supported */
+
+	/* attach the mac to the phy */
+	db->phy_dev = of_phy_connect(db->ndev, db->phy_node,
+				     &emac_handle_link_change, 0,
+				     db->phy_interface);
+	if (!db->phy_dev) {
+		netdev_err(db->ndev, "could not find the PHY\n");
+		return -ENODEV;
+	}
+
+	/* mask with MAC supported features */
+	db->phy_dev->supported &= PHY_BASIC_FEATURES;
+	db->phy_dev->advertising = db->phy_dev->supported;
+
+	db->link = 0;
+	db->speed = 0;
+	db->duplex = -1;
+
+	return 0;
+}
+
+static void emac_mdio_remove(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+
+	phy_disconnect(db->phy_dev);
+	db->phy_dev = NULL;
+}
+
+static void emac_reset(struct emac_board_info *db)
+{
+	dev_dbg(db->dev, "resetting device\n");
+
+	/* RESET device */
+	writel(0, db->membase + EMAC_CTL_REG);
+	udelay(200);
+	writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
+	udelay(200);
+}
+
+static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
+{
+	writesl(reg, data, round_up(count, 4) / 4);
+}
+
+static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
+{
+	readsl(reg, data, round_up(count, 4) / 4);
+}
+
+static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	struct emac_board_info *dm = netdev_priv(dev);
+	struct phy_device *phydev = dm->phy_dev;
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_mii_ioctl(phydev, rq, cmd);
+}
+
+/* ethtool ops */
+static void emac_get_drvinfo(struct net_device *dev,
+			      struct ethtool_drvinfo *info)
+{
+	strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME));
+	strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION));
+	strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
+}
+
+static int emac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+	struct emac_board_info *dm = netdev_priv(dev);
+	struct phy_device *phydev = dm->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int emac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+	struct emac_board_info *dm = netdev_priv(dev);
+	struct phy_device *phydev = dm->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static const struct ethtool_ops emac_ethtool_ops = {
+	.get_drvinfo	= emac_get_drvinfo,
+	.get_settings	= emac_get_settings,
+	.set_settings	= emac_set_settings,
+	.get_link	= ethtool_op_get_link,
+};
+
+unsigned int emac_setup(struct net_device *ndev)
+{
+	struct emac_board_info *db = netdev_priv(ndev);
+	unsigned int reg_val;
+
+	/* set up TX */
+	reg_val = readl(db->membase + EMAC_TX_MODE_REG);
+
+	writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
+		db->membase + EMAC_TX_MODE_REG);
+
+	/* set up RX */
+	reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+
+	writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
+		EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
+		EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
+		EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
+		db->membase + EMAC_RX_CTL_REG);
+
+	/* set MAC */
+	/* set MAC CTL0 */
+	reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
+	writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
+		EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
+		db->membase + EMAC_MAC_CTL0_REG);
+
+	/* set MAC CTL1 */
+	reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
+	reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
+	reg_val |= EMAC_MAC_CTL1_CRC_EN;
+	reg_val |= EMAC_MAC_CTL1_PAD_EN;
+	writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
+
+	/* set up IPGT */
+	writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
+
+	/* set up IPGR */
+	writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
+		db->membase + EMAC_MAC_IPGR_REG);
+
+	/* set up Collison window */
+	writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
+		db->membase + EMAC_MAC_CLRT_REG);
+
+	/* set up Max Frame Length */
+	writel(EMAC_MAX_FRAME_LEN,
+		db->membase + EMAC_MAC_MAXF_REG);
+
+	return 0;
+}
+
+unsigned int emac_powerup(struct net_device *ndev)
+{
+	struct emac_board_info *db = netdev_priv(ndev);
+	unsigned int reg_val;
+
+	/* initial EMAC */
+	/* flush RX FIFO */
+	reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+	reg_val |= 0x8;
+	writel(reg_val, db->membase + EMAC_RX_CTL_REG);
+	udelay(1);
+
+	/* initial MAC */
+	/* soft reset MAC */
+	reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
+	reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
+	writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
+
+	/* set MII clock */
+	reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
+	reg_val &= (~(0xf << 2));
+	reg_val |= (0xD << 2);
+	writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
+
+	/* clear RX counter */
+	writel(0x0, db->membase + EMAC_RX_FBC_REG);
+
+	/* disable all interrupt and clear interrupt status */
+	writel(0, db->membase + EMAC_INT_CTL_REG);
+	reg_val = readl(db->membase + EMAC_INT_STA_REG);
+	writel(reg_val, db->membase + EMAC_INT_STA_REG);
+
+	udelay(1);
+
+	/* set up EMAC */
+	emac_setup(ndev);
+
+	/* set mac_address to chip */
+	writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
+	       dev_addr[2], db->membase + EMAC_MAC_A1_REG);
+	writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
+	       dev_addr[5], db->membase + EMAC_MAC_A0_REG);
+
+	mdelay(1);
+
+	return 0;
+}
+
+static int emac_set_mac_address(struct net_device *dev, void *p)
+{
+	struct sockaddr *addr = p;
+	struct emac_board_info *db = netdev_priv(dev);
+
+	if (netif_running(dev))
+		return -EBUSY;
+
+	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
+
+	writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
+	       dev_addr[2], db->membase + EMAC_MAC_A1_REG);
+	writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
+	       dev_addr[5], db->membase + EMAC_MAC_A0_REG);
+
+	return 0;
+}
+
+/* Initialize emac board */
+static void emac_init_device(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned long flags;
+	unsigned int reg_val;
+
+	spin_lock_irqsave(&db->lock, flags);
+
+	emac_update_speed(dev);
+	emac_update_duplex(dev);
+
+	/* enable RX/TX */
+	reg_val = readl(db->membase + EMAC_CTL_REG);
+	writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
+		db->membase + EMAC_CTL_REG);
+
+	/* enable RX/TX0/RX Hlevel interrup */
+	reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+	reg_val |= (0xf << 0) | (0x01 << 8);
+	writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+
+	spin_unlock_irqrestore(&db->lock, flags);
+}
+
+/* Our watchdog timed out. Called by the networking layer */
+static void emac_timeout(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned long flags;
+
+	if (netif_msg_timer(db))
+		dev_err(db->dev, "tx time out.\n");
+
+	/* Save previous register address */
+	spin_lock_irqsave(&db->lock, flags);
+
+	netif_stop_queue(dev);
+	emac_reset(db);
+	emac_init_device(dev);
+	/* We can accept TX packets again */
+	dev->trans_start = jiffies;
+	netif_wake_queue(dev);
+
+	/* Restore previous register address */
+	spin_unlock_irqrestore(&db->lock, flags);
+}
+
+/* Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	unsigned long channel;
+	unsigned long flags;
+
+	channel = db->tx_fifo_stat & 3;
+	if (channel == 3)
+		return 1;
+
+	channel = (channel == 1 ? 1 : 0);
+
+	spin_lock_irqsave(&db->lock, flags);
+
+	writel(channel, db->membase + EMAC_TX_INS_REG);
+
+	emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
+			skb->data, skb->len);
+	dev->stats.tx_bytes += skb->len;
+
+	db->tx_fifo_stat |= 1 << channel;
+	/* TX control: First packet immediately send, second packet queue */
+	if (channel == 0) {
+		/* set TX len */
+		writel(skb->len, db->membase + EMAC_TX_PL0_REG);
+		/* start translate from fifo to phy */
+		writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
+		       db->membase + EMAC_TX_CTL0_REG);
+
+		/* save the time stamp */
+		dev->trans_start = jiffies;
+	} else if (channel == 1) {
+		/* set TX len */
+		writel(skb->len, db->membase + EMAC_TX_PL1_REG);
+		/* start translate from fifo to phy */
+		writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
+		       db->membase + EMAC_TX_CTL1_REG);
+
+		/* save the time stamp */
+		dev->trans_start = jiffies;
+	}
+
+	if ((db->tx_fifo_stat & 3) == 3) {
+		/* Second packet */
+		netif_stop_queue(dev);
+	}
+
+	spin_unlock_irqrestore(&db->lock, flags);
+
+	/* free this SKB */
+	dev_kfree_skb(skb);
+
+	return NETDEV_TX_OK;
+}
+
+/* EMAC interrupt handler
+ * receive the packet to upper layer, free the transmitted packet
+ */
+static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
+			  unsigned int tx_status)
+{
+	/* One packet sent complete */
+	db->tx_fifo_stat &= ~(tx_status & 3);
+	if (3 == (tx_status & 3))
+		dev->stats.tx_packets += 2;
+	else
+		dev->stats.tx_packets++;
+
+	if (netif_msg_tx_done(db))
+		dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
+
+	netif_wake_queue(dev);
+}
+
+/* Received a packet and pass to upper layer
+ */
+static void emac_rx(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	struct sk_buff *skb;
+	u8 *rdptr;
+	bool good_packet;
+	static int rxlen_last;
+	unsigned int reg_val;
+	u32 rxhdr, rxstatus, rxcount, rxlen;
+
+	/* Check packet ready or not */
+	while (1) {
+		/* race warning: the first packet might arrive with
+		 * the interrupts disabled, but the second will fix
+		 * it
+		 */
+		rxcount = readl(db->membase + EMAC_RX_FBC_REG);
+
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "RXCount: %x\n", rxcount);
+
+		if ((db->skb_last != NULL) && (rxlen_last > 0)) {
+			dev->stats.rx_bytes += rxlen_last;
+
+			/* Pass to upper layer */
+			db->skb_last->protocol = eth_type_trans(db->skb_last,
+								dev);
+			netif_rx(db->skb_last);
+			dev->stats.rx_packets++;
+			db->skb_last = NULL;
+			rxlen_last = 0;
+
+			reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+			reg_val &= ~EMAC_RX_CTL_DMA_EN;
+			writel(reg_val, db->membase + EMAC_RX_CTL_REG);
+		}
+
+		if (!rxcount) {
+			db->emacrx_completed_flag = 1;
+			reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+			reg_val |= (0xf << 0) | (0x01 << 8);
+			writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+
+			/* had one stuck? */
+			rxcount = readl(db->membase + EMAC_RX_FBC_REG);
+			if (!rxcount)
+				return;
+		}
+
+		reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "receive header: %x\n", reg_val);
+		if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
+			/* disable RX */
+			reg_val = readl(db->membase + EMAC_CTL_REG);
+			writel(reg_val & ~EMAC_CTL_RX_EN,
+			       db->membase + EMAC_CTL_REG);
+
+			/* Flush RX FIFO */
+			reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+			writel(reg_val | (1 << 3),
+			       db->membase + EMAC_RX_CTL_REG);
+
+			do {
+				reg_val = readl(db->membase + EMAC_RX_CTL_REG);
+			} while (reg_val & (1 << 3));
+
+			/* enable RX */
+			reg_val = readl(db->membase + EMAC_CTL_REG);
+			writel(reg_val | EMAC_CTL_RX_EN,
+			       db->membase + EMAC_CTL_REG);
+			reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+			reg_val |= (0xf << 0) | (0x01 << 8);
+			writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+
+			db->emacrx_completed_flag = 1;
+
+			return;
+		}
+
+		/* A packet ready now  & Get status/length */
+		good_packet = true;
+
+		emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
+				&rxhdr, sizeof(rxhdr));
+
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
+
+		rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
+		rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
+
+		if (netif_msg_rx_status(db))
+			dev_dbg(db->dev, "RX: status %02x, length %04x\n",
+				rxstatus, rxlen);
+
+		/* Packet Status check */
+		if (rxlen < 0x40) {
+			good_packet = false;
+			if (netif_msg_rx_err(db))
+				dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
+		}
+
+		if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
+			good_packet = false;
+
+			if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
+				if (netif_msg_rx_err(db))
+					dev_dbg(db->dev, "crc error\n");
+				dev->stats.rx_crc_errors++;
+			}
+
+			if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
+				if (netif_msg_rx_err(db))
+					dev_dbg(db->dev, "length error\n");
+				dev->stats.rx_length_errors++;
+			}
+		}
+
+		/* Move data from EMAC */
+		skb = dev_alloc_skb(rxlen + 4);
+		if (good_packet && skb) {
+			skb_reserve(skb, 2);
+			rdptr = (u8 *) skb_put(skb, rxlen - 4);
+
+			/* Read received packet from RX SRAM */
+			if (netif_msg_rx_status(db))
+				dev_dbg(db->dev, "RxLen %x\n", rxlen);
+
+			emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
+					rdptr, rxlen);
+			dev->stats.rx_bytes += rxlen;
+
+			/* Pass to upper layer */
+			skb->protocol = eth_type_trans(skb, dev);
+			netif_rx(skb);
+			dev->stats.rx_packets++;
+		}
+	}
+}
+
+static irqreturn_t emac_interrupt(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct emac_board_info *db = netdev_priv(dev);
+	int int_status;
+	unsigned long flags;
+	unsigned int reg_val;
+
+	/* A real interrupt coming */
+
+	/* holders of db->lock must always block IRQs */
+	spin_lock_irqsave(&db->lock, flags);
+
+	/* Disable all interrupts */
+	writel(0, db->membase + EMAC_INT_CTL_REG);
+
+	/* Got EMAC interrupt status */
+	/* Got ISR */
+	int_status = readl(db->membase + EMAC_INT_STA_REG);
+	/* Clear ISR status */
+	writel(int_status, db->membase + EMAC_INT_STA_REG);
+
+	if (netif_msg_intr(db))
+		dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
+
+	/* Received the coming packet */
+	if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
+		/* carrier lost */
+		db->emacrx_completed_flag = 0;
+		emac_rx(dev);
+	}
+
+	/* Transmit Interrupt check */
+	if (int_status & (0x01 | 0x02))
+		emac_tx_done(dev, db, int_status);
+
+	if (int_status & (0x04 | 0x08))
+		netdev_info(dev, " ab : %x\n", int_status);
+
+	/* Re-enable interrupt mask */
+	if (db->emacrx_completed_flag == 1) {
+		reg_val = readl(db->membase + EMAC_INT_CTL_REG);
+		reg_val |= (0xf << 0) | (0x01 << 8);
+		writel(reg_val, db->membase + EMAC_INT_CTL_REG);
+	}
+	spin_unlock_irqrestore(&db->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Used by netconsole
+ */
+static void emac_poll_controller(struct net_device *dev)
+{
+	disable_irq(dev->irq);
+	emac_interrupt(dev->irq, dev);
+	enable_irq(dev->irq);
+}
+#endif
+
+/*  Open the interface.
+ *  The interface is opened whenever "ifconfig" actives it.
+ */
+static int emac_open(struct net_device *dev)
+{
+	struct emac_board_info *db = netdev_priv(dev);
+	int ret;
+
+	if (netif_msg_ifup(db))
+		dev_dbg(db->dev, "enabling %s\n", dev->name);
+
+	if (devm_request_irq(db->dev, dev->irq, &emac_interrupt,
+			     0, dev->name, dev))
+		return -EAGAIN;
+
+	/* Initialize EMAC board */
+	emac_reset(db);
+	emac_init_device(dev);
+
+	ret = emac_mdio_probe(dev);
+	if (ret < 0) {
+		netdev_err(dev, "cannot probe MDIO bus\n");
+		return ret;
+	}
+
+	phy_start(db->phy_dev);
+	netif_start_queue(dev);
+
+	return 0;
+}
+
+static void emac_shutdown(struct net_device *dev)
+{
+	unsigned int reg_val;
+	struct emac_board_info *db = netdev_priv(dev);
+
+	/* Disable all interrupt */
+	writel(0, db->membase + EMAC_INT_CTL_REG);
+
+	/* clear interupt status */
+	reg_val = readl(db->membase + EMAC_INT_STA_REG);
+	writel(reg_val, db->membase + EMAC_INT_STA_REG);
+
+	/* Disable RX/TX */
+	reg_val = readl(db->membase + EMAC_CTL_REG);
+	reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
+	writel(reg_val, db->membase + EMAC_CTL_REG);
+}
+
+/* Stop the interface.
+ * The interface is stopped when it is brought.
+ */
+static int emac_stop(struct net_device *ndev)
+{
+	struct emac_board_info *db = netdev_priv(ndev);
+
+	if (netif_msg_ifdown(db))
+		dev_dbg(db->dev, "shutting down %s\n", ndev->name);
+
+	netif_stop_queue(ndev);
+	netif_carrier_off(ndev);
+
+	phy_stop(db->phy_dev);
+
+	emac_mdio_remove(ndev);
+
+	emac_shutdown(ndev);
+
+	return 0;
+}
+
+static const struct net_device_ops emac_netdev_ops = {
+	.ndo_open		= emac_open,
+	.ndo_stop		= emac_stop,
+	.ndo_start_xmit		= emac_start_xmit,
+	.ndo_tx_timeout		= emac_timeout,
+	.ndo_do_ioctl		= emac_ioctl,
+	.ndo_change_mtu		= eth_change_mtu,
+	.ndo_validate_addr	= eth_validate_addr,
+	.ndo_set_mac_address	= emac_set_mac_address,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller	= emac_poll_controller,
+#endif
+};
+
+/* Search EMAC board, allocate space and register it
+ */
+static int emac_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct emac_board_info *db;
+	struct net_device *ndev;
+	int ret = 0;
+	const char *mac_addr;
+
+	ndev = alloc_etherdev(sizeof(struct emac_board_info));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		return -ENOMEM;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	db = netdev_priv(ndev);
+	memset(db, 0, sizeof(*db));
+
+	db->dev = &pdev->dev;
+	db->ndev = ndev;
+	db->pdev = pdev;
+
+	spin_lock_init(&db->lock);
+
+	db->membase = of_iomap(np, 0);
+	if (!db->membase) {
+		dev_err(&pdev->dev, "failed to remap registers\n");
+		return -ENOMEM;
+		goto out;
+	}
+
+	/* fill in parameters for net-dev structure */
+	ndev->base_addr = (unsigned long)db->membase;
+	ndev->irq = irq_of_parse_and_map(np, 0);
+	if (ndev->irq == -ENXIO) {
+		netdev_err(ndev, "No irq resource\n");
+		ret = ndev->irq;
+		goto out;
+	}
+
+	db->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(db->clk))
+		goto out;
+
+	clk_prepare_enable(db->clk);
+
+	db->phy_node = of_parse_phandle(np, "phy", 0);
+	if (!db->phy_node) {
+		dev_err(&pdev->dev, "no associated PHY\n");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Read MAC-address from DT */
+	mac_addr = of_get_mac_address(np);
+	if (mac_addr)
+		memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
+
+	/* Check if the MAC address is valid, if not get a random one */
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		eth_hw_addr_random(ndev);
+		dev_warn(&pdev->dev, "using random MAC address %pM\n",
+			 ndev->dev_addr);
+	}
+
+	db->emacrx_completed_flag = 1;
+	emac_powerup(ndev);
+	emac_reset(db);
+
+	ether_setup(ndev);
+
+	ndev->netdev_ops = &emac_netdev_ops;
+	ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
+	ndev->ethtool_ops = &emac_ethtool_ops;
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	ndev->poll_controller = &emac_poll_controller;
+#endif
+
+	platform_set_drvdata(pdev, ndev);
+
+	/* Carrier starts down, phylib will bring it up */
+	netif_carrier_off(ndev);
+
+	ret = register_netdev(ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "Registering netdev failed!\n");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
+		 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
+
+	return 0;
+
+out:
+	dev_err(db->dev, "not found (%d).\n", ret);
+
+	free_netdev(ndev);
+
+	return ret;
+}
+
+static int emac_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	unregister_netdev(ndev);
+	free_netdev(ndev);
+
+	dev_dbg(&pdev->dev, "released and freed device\n");
+	return 0;
+}
+
+static int emac_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(dev);
+
+	netif_carrier_off(ndev);
+	netif_device_detach(ndev);
+	emac_shutdown(ndev);
+
+	return 0;
+}
+
+static int emac_resume(struct platform_device *dev)
+{
+	struct net_device *ndev = platform_get_drvdata(dev);
+	struct emac_board_info *db = netdev_priv(ndev);
+
+	emac_reset(db);
+	emac_init_device(ndev);
+	netif_device_attach(ndev);
+
+	return 0;
+}
+
+static const struct of_device_id emac_of_match[] = {
+	{.compatible = "allwinner,sun4i-emac",},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, emac_of_match);
+
+static struct platform_driver emac_driver = {
+	.driver = {
+		.name = "sun4i-emac",
+		.of_match_table = emac_of_match,
+	},
+	.probe = emac_probe,
+	.remove = emac_remove,
+	.suspend = emac_suspend,
+	.resume = emac_resume,
+};
+
+module_platform_driver(emac_driver);
+
+MODULE_AUTHOR("Stefan Roese <sr at denx.de>");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com>");
+MODULE_DESCRIPTION("Allwinner A10 emac network driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.h b/drivers/net/ethernet/allwinner/sun4i-emac.h
new file mode 100644
index 0000000..38c72d9
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.h
@@ -0,0 +1,108 @@
+/*
+ * Allwinner EMAC Fast Ethernet driver for Linux.
+ *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ * Copyright 2013 Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997  Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _SUN4I_EMAC_H_
+#define _SUN4I_EMAC_H_
+
+#define EMAC_CTL_REG		(0x00)
+#define EMAC_CTL_RESET			(1 << 0)
+#define EMAC_CTL_TX_EN			(1 << 1)
+#define EMAC_CTL_RX_EN			(1 << 2)
+#define EMAC_TX_MODE_REG	(0x04)
+#define EMAC_TX_MODE_ABORTED_FRAME_EN	(1 << 0)
+#define EMAC_TX_MODE_DMA_EN		(1 << 1)
+#define EMAC_TX_FLOW_REG	(0x08)
+#define EMAC_TX_CTL0_REG	(0x0c)
+#define EMAC_TX_CTL1_REG	(0x10)
+#define EMAC_TX_INS_REG		(0x14)
+#define EMAC_TX_PL0_REG		(0x18)
+#define EMAC_TX_PL1_REG		(0x1c)
+#define EMAC_TX_STA_REG		(0x20)
+#define EMAC_TX_IO_DATA_REG	(0x24)
+#define EMAC_TX_IO_DATA1_REG	(0x28)
+#define EMAC_TX_TSVL0_REG	(0x2c)
+#define EMAC_TX_TSVH0_REG	(0x30)
+#define EMAC_TX_TSVL1_REG	(0x34)
+#define EMAC_TX_TSVH1_REG	(0x38)
+#define EMAC_RX_CTL_REG		(0x3c)
+#define EMAC_RX_CTL_AUTO_DRQ_EN		(1 << 1)
+#define EMAC_RX_CTL_DMA_EN		(1 << 2)
+#define EMAC_RX_CTL_PASS_ALL_EN		(1 << 4)
+#define EMAC_RX_CTL_PASS_CTL_EN		(1 << 5)
+#define EMAC_RX_CTL_PASS_CRC_ERR_EN	(1 << 6)
+#define EMAC_RX_CTL_PASS_LEN_ERR_EN	(1 << 7)
+#define EMAC_RX_CTL_PASS_LEN_OOR_EN	(1 << 8)
+#define EMAC_RX_CTL_ACCEPT_UNICAST_EN	(1 << 16)
+#define EMAC_RX_CTL_DA_FILTER_EN	(1 << 17)
+#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN	(1 << 20)
+#define EMAC_RX_CTL_HASH_FILTER_EN	(1 << 21)
+#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN	(1 << 22)
+#define EMAC_RX_CTL_SA_FILTER_EN	(1 << 24)
+#define EMAC_RX_CTL_SA_FILTER_INVERT_EN	(1 << 25)
+#define EMAC_RX_HASH0_REG	(0x40)
+#define EMAC_RX_HASH1_REG	(0x44)
+#define EMAC_RX_STA_REG		(0x48)
+#define EMAC_RX_IO_DATA_REG	(0x4c)
+#define EMAC_RX_IO_DATA_LEN(x)		(x & 0xffff)
+#define EMAC_RX_IO_DATA_STATUS(x)	((x >> 16) & 0xffff)
+#define EMAC_RX_IO_DATA_STATUS_CRC_ERR	(1 << 4)
+#define EMAC_RX_IO_DATA_STATUS_LEN_ERR	(3 << 5)
+#define EMAC_RX_IO_DATA_STATUS_OK	(1 << 7)
+#define EMAC_RX_FBC_REG		(0x50)
+#define EMAC_INT_CTL_REG	(0x54)
+#define EMAC_INT_STA_REG	(0x58)
+#define EMAC_MAC_CTL0_REG	(0x5c)
+#define EMAC_MAC_CTL0_RX_FLOW_CTL_EN	(1 << 2)
+#define EMAC_MAC_CTL0_TX_FLOW_CTL_EN	(1 << 3)
+#define EMAC_MAC_CTL0_SOFT_RESET	(1 << 15)
+#define EMAC_MAC_CTL1_REG	(0x60)
+#define EMAC_MAC_CTL1_DUPLEX_EN		(1 << 0)
+#define EMAC_MAC_CTL1_LEN_CHECK_EN	(1 << 1)
+#define EMAC_MAC_CTL1_HUGE_FRAME_EN	(1 << 2)
+#define EMAC_MAC_CTL1_DELAYED_CRC_EN	(1 << 3)
+#define EMAC_MAC_CTL1_CRC_EN		(1 << 4)
+#define EMAC_MAC_CTL1_PAD_EN		(1 << 5)
+#define EMAC_MAC_CTL1_PAD_CRC_EN	(1 << 6)
+#define EMAC_MAC_CTL1_AD_SHORT_FRAME_EN	(1 << 7)
+#define EMAC_MAC_CTL1_BACKOFF_DIS	(1 << 12)
+#define EMAC_MAC_IPGT_REG	(0x64)
+#define EMAC_MAC_IPGT_HALF_DUPLEX	(0x12)
+#define EMAC_MAC_IPGT_FULL_DUPLEX	(0x15)
+#define EMAC_MAC_IPGR_REG	(0x68)
+#define EMAC_MAC_IPGR_IPG1		(0x0c)
+#define EMAC_MAC_IPGR_IPG2		(0x12)
+#define EMAC_MAC_CLRT_REG	(0x6c)
+#define EMAC_MAC_CLRT_COLLISION_WINDOW	(0x37)
+#define EMAC_MAC_CLRT_RM		(0x0f)
+#define EMAC_MAC_MAXF_REG	(0x70)
+#define EMAC_MAC_SUPP_REG	(0x74)
+#define EMAC_MAC_TEST_REG	(0x78)
+#define EMAC_MAC_MCFG_REG	(0x7c)
+#define EMAC_MAC_A0_REG		(0x98)
+#define EMAC_MAC_A1_REG		(0x9c)
+#define EMAC_MAC_A2_REG		(0xa0)
+#define EMAC_SAFX_L_REG0	(0xa4)
+#define EMAC_SAFX_H_REG0	(0xa8)
+#define EMAC_SAFX_L_REG1	(0xac)
+#define EMAC_SAFX_H_REG1	(0xb0)
+#define EMAC_SAFX_L_REG2	(0xb4)
+#define EMAC_SAFX_H_REG2	(0xb8)
+#define EMAC_SAFX_L_REG3	(0xbc)
+#define EMAC_SAFX_H_REG3	(0xc0)
+
+#define EMAC_PHY_DUPLEX		(1 << 8)
+
+#define EMAC_EEPROM_MAGIC	(0x444d394b)
+#define EMAC_UNDOCUMENTED_MAGIC	(0x0143414d)
+#endif /* _SUN4I_EMAC_H_ */
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Thu May 30 09:49:22 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:22 +0200
Subject: [PATCHv4 3/6] ARM: sun4i: Add muxing options for the ethernet
 controller
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369921765-3367-4-git-send-email-maxime.ripard@free-electrons.com>

The EMAC only has one pinset available for muxing, so hopefully, we
cover all cases.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Tested-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..ff1f41f 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,17 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			emac_pins_a: emac0 at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA9", "PA10",
+						"PA11", "PA12", "PA13", "PA14",
+						"PA15", "PA16";
+				allwinner,function = "emac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Thu May 30 09:49:21 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:21 +0200
Subject: [PATCHv4 2/6] net: Add MDIO bus driver for the Allwinner EMAC
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369921765-3367-3-git-send-email-maxime.ripard@free-electrons.com>

This patch adds a separate driver for the MDIO interface of the
Allwinner ethernet controllers.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Tested-by: Richard Genoud <richard.genoud at gmail.com>
---
 .../bindings/net/allwinner,sun4i-mdio.txt          |  26 +++
 drivers/net/phy/Kconfig                            |  10 ++
 drivers/net/phy/Makefile                           |   1 +
 drivers/net/phy/mdio-sun4i.c                       | 194 +++++++++++++++++++++
 4 files changed, 231 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
 create mode 100644 drivers/net/phy/mdio-sun4i.c

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
new file mode 100644
index 0000000..00b9f9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
@@ -0,0 +1,26 @@
+* Allwinner A10 MDIO Ethernet Controller interface
+
+Required properties:
+- compatible: should be "allwinner,sun4i-mdio".
+- reg: address and length of the register set for the device.
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Example at the SoC level:
+mdio at 01c0b080 {
+	compatible = "allwinner,sun4i-mdio";
+	reg = <0x01c0b080 0x14>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+};
+
+And at the board level:
+
+mdio at 01c0b080 {
+	phy-supply = <&reg_emac_3v3>;
+
+	phy0: ethernet-phy at 0 {
+		reg = <0>;
+	};
+};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1e11f2b..3a316b3 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -144,6 +144,16 @@ config MDIO_OCTEON
 
 	  If in doubt, say Y.
 
+config MDIO_SUN4I
+	tristate "Allwinner sun4i MDIO interface support"
+	depends on ARCH_SUNXI
+	select REGULATOR
+	select REGULATOR_FIXED_VOLTAGE
+	help
+	  This driver supports the MDIO interface found in the network
+	  interface units of the Allwinner SoC that have an EMAC (A10,
+	  A12, A10s, etc.)
+
 config MDIO_BUS_MUX
 	tristate
 	depends on OF_MDIO
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9645e38..23a2ab2 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_AMD_PHY)		+= amd.o
 obj-$(CONFIG_MDIO_BUS_MUX)	+= mdio-mux.o
 obj-$(CONFIG_MDIO_BUS_MUX_GPIO)	+= mdio-mux-gpio.o
 obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
+obj-$(CONFIG_MDIO_SUN4I)	+= mdio-sun4i.o
diff --git a/drivers/net/phy/mdio-sun4i.c b/drivers/net/phy/mdio-sun4i.c
new file mode 100644
index 0000000..61d3f4e
--- /dev/null
+++ b/drivers/net/phy/mdio-sun4i.c
@@ -0,0 +1,194 @@
+/*
+ * Allwinner EMAC MDIO interface driver
+ *
+ * Copyright 2012-2013 Stefan Roese <sr at denx.de>
+ * Copyright 2013 Maxime Ripard <maxime.ripard at free-electrons.com>
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997  Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#define EMAC_MAC_MCMD_REG	(0x00)
+#define EMAC_MAC_MADR_REG	(0x04)
+#define EMAC_MAC_MWTD_REG	(0x08)
+#define EMAC_MAC_MRDD_REG	(0x0c)
+#define EMAC_MAC_MIND_REG	(0x10)
+#define EMAC_MAC_SSRR_REG	(0x14)
+
+#define MDIO_TIMEOUT		(msecs_to_jiffies(100))
+
+struct sun4i_mdio_data {
+	void __iomem		*membase;
+	struct regulator	*regulator;
+};
+
+static int sun4i_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct sun4i_mdio_data *data = bus->priv;
+	unsigned long start_jiffies;
+	int value;
+
+	/* issue the phy address and reg */
+	writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
+	/* pull up the phy io line */
+	writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
+
+	/* Wait read complete */
+	start_jiffies = jiffies;
+	while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
+		if (time_after(start_jiffies,
+			       start_jiffies + MDIO_TIMEOUT))
+			return -ETIMEDOUT;
+		msleep(1);
+	}
+
+	/* push down the phy io line */
+	writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
+	/* and read data */
+	value = readl(data->membase + EMAC_MAC_MRDD_REG);
+
+	return value;
+}
+
+static int sun4i_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+			    u16 value)
+{
+	struct sun4i_mdio_data *data = bus->priv;
+	unsigned long start_jiffies;
+
+	/* issue the phy address and reg */
+	writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
+	/* pull up the phy io line */
+	writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
+
+	/* Wait read complete */
+	start_jiffies = jiffies;
+	while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
+		if (time_after(start_jiffies,
+			       start_jiffies + MDIO_TIMEOUT))
+			return -ETIMEDOUT;
+		msleep(1);
+	}
+
+	/* push down the phy io line */
+	writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
+	/* and write data */
+	writel(value, data->membase + EMAC_MAC_MWTD_REG);
+
+	return 0;
+}
+
+static int sun4i_mdio_reset(struct mii_bus *bus)
+{
+	return 0;
+}
+
+static int sun4i_mdio_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct mii_bus *bus;
+	struct sun4i_mdio_data *data;
+	int ret, i;
+
+	bus = mdiobus_alloc_size(sizeof(*data));
+	if (!bus)
+		return -ENOMEM;
+
+	bus->name = "sun4i_mii_bus";
+	bus->read = &sun4i_mdio_read;
+	bus->write = &sun4i_mdio_write;
+	bus->reset = &sun4i_mdio_reset;
+	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
+	bus->parent = &pdev->dev;
+
+	bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!bus->irq) {
+		ret = -ENOMEM;
+		goto err_out_free_mdiobus;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		bus->irq[i] = PHY_POLL;
+
+	data = bus->priv;
+	data->membase = of_iomap(np, 0);
+	if (!data->membase) {
+		ret = -ENOMEM;
+		goto err_out_free_mdio_irq;
+	}
+
+	data->regulator = devm_regulator_get(&pdev->dev, "phy");
+	if (IS_ERR(data->regulator)) {
+		if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+
+		dev_info(&pdev->dev, "no regulator found\n");
+	} else {
+		ret = regulator_enable(data->regulator);
+		if (ret)
+			goto err_out_free_mdio_irq;
+	}
+
+	ret = of_mdiobus_register(bus, np);
+	if (ret < 0)
+		goto err_out_disable_regulator;
+
+	platform_set_drvdata(pdev, bus);
+
+	return 0;
+
+err_out_disable_regulator:
+	regulator_disable(data->regulator);
+err_out_free_mdio_irq:
+	kfree(bus->irq);
+err_out_free_mdiobus:
+	mdiobus_free(bus);
+	return ret;
+}
+
+static int sun4i_mdio_remove(struct platform_device *pdev)
+{
+	struct mii_bus *bus = platform_get_drvdata(pdev);
+
+	mdiobus_unregister(bus);
+	kfree(bus->irq);
+	mdiobus_free(bus);
+
+	return 0;
+}
+
+static const struct of_device_id sun4i_mdio_dt_ids[] = {
+	{ .compatible = "allwinner,sun4i-mdio" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sun4i_mdio_dt_ids);
+
+static struct platform_driver sun4i_mdio_driver = {
+	.probe = sun4i_mdio_probe,
+	.remove = sun4i_mdio_remove,
+	.driver = {
+		.name = "sun4i-mdio",
+		.of_match_table = sun4i_mdio_dt_ids,
+	},
+};
+
+module_platform_driver(sun4i_mdio_driver);
+
+MODULE_DESCRIPTION("Allwinner EMAC MDIO interface driver");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com>");
+MODULE_LICENSE("GPL");
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Thu May 30 09:49:23 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:23 +0200
Subject: [PATCHv4 4/6] ARM: sunxi: Add EMAC controller node to sun4i DTSI
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369921765-3367-5-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Tested-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ff1f41f..983da33 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -163,6 +163,22 @@
 		reg = <0x01c20000 0x300000>;
 		ranges;
 
+		emac: ethernet at 01c0b000 {
+			compatible = "allwinner,sun4i-emac";
+			reg = <0x01c0b000 0x1000>;
+			interrupts = <55>;
+			clocks = <&ahb_gates 17>;
+			status = "disabled";
+		};
+
+		mdio at 01c0b080 {
+			compatible = "allwinner,sun4i-mdio";
+			reg = <0x01c0b080 0x14>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		intc: interrupt-controller at 01c20400 {
 			compatible = "allwinner,sun4i-ic";
 			reg = <0x01c20400 0x400>;
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Thu May 30 09:49:24 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:24 +0200
Subject: [PATCHv4 5/6] ARM: cubieboard: Enable ethernet (EMAC) support in dts
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369921765-3367-6-git-send-email-maxime.ripard@free-electrons.com>

From: Stefan Roese <sr at denx.de>

Signed-off-by: Stefan Roese <sr at denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Tested-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..e752b57 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -27,6 +27,21 @@
 	};
 
 	soc at 01c20000 {
+		emac: ethernet at 01c0b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&emac_pins_a>;
+			phy = <&phy1>;
+			status = "okay";
+		};
+
+		mdio at 01c0b080 {
+			status = "okay";
+
+			phy1: ethernet-phy at 1 {
+				reg = <1>;
+			};
+		};
+
 		pinctrl at 01c20800 {
 			led_pins_cubieboard: led_pins at 0 {
 				allwinner,pins = "PH20", "PH21";
-- 
1.8.2.3



From maxime.ripard at free-electrons.com  Thu May 30 09:49:25 2013
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 30 May 2013 15:49:25 +0200
Subject: [PATCHv4 6/6] ARM: sunxi: Add EMAC Controller to Hackberry dt
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1369921765-3367-7-git-send-email-maxime.ripard@free-electrons.com>

The Hackberry has a PHY that needs to be powered up through a GPIO, so
we need to use a fixed regulator here.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Tested-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/sun4i-a10-hackberry.dts | 41 +++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b9efac1..3514b37 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -23,10 +23,51 @@
 	};
 
 	soc at 01c20000 {
+		emac: ethernet at 01c0b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&emac_pins_a>;
+			phy = <&phy0>;
+			status = "okay";
+		};
+
+		mdio at 01c0b080 {
+			phy-supply = <&reg_emac_3v3>;
+			status = "okay";
+
+			phy0: ethernet-phy at 0 {
+				reg = <0>;
+			};
+		};
+
+		pio: pinctrl at 01c20800 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&hackberry_hogs>;
+
+			hackberry_hogs: hogs at 0 {
+				allwinner,pins = "PH19";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+
 		uart0: serial at 01c28000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
 	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_emac_3v3: emac-3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "emac-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			enable-active-high;
+			gpio = <&pio 7 19 0>;
+		};
+	};
 };
-- 
1.8.2.3



From florian.vaussard at epfl.ch  Thu May 30 09:51:53 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 30 May 2013 15:51:53 +0200
Subject: [PATCH 0/3] mfd: twl4030-power: Start DT conversion
Message-ID: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

This series enables a partial DT support for twl4030-power. The
missing part is the power management scripts, as the required
binding should be defined first. It however enables the complete
shutdown of the processor at poweroff when booting with DT,
dropping the power consumption from around 350 mA on Overo+Tobi
to about 40 mA.

The poweroff callback was tested with both DT and non-DT boots.

Best regards,

Florian

Florian Vaussard (3):
  mfd: twl4030-power: Split from twl-core into a dedicated module
  mfd: twl4030-power: Start transition to DT
  mfd: twl4030-power: Simplify error path

 .../devicetree/bindings/mfd/twl4030-power.txt      |   28 ++++
 drivers/mfd/twl-core.c                             |   12 +-
 drivers/mfd/twl4030-power.c                        |  149 +++++++++++++++-----
 include/linux/i2c/twl.h                            |    1 -
 4 files changed, 148 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-power.txt

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 30 09:51:54 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 30 May 2013 15:51:54 +0200
Subject: [PATCH 1/3] mfd: twl4030-power: Split from twl-core into a dedicated
 module
In-Reply-To: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369921916-7435-2-git-send-email-florian.vaussard@epfl.ch>

For now, the call to twl4030-power is hard-wired inside twl-core.
To ease the future transition to DT, make twl4030-power as a
separate module, like what is already done for twl4030-audio
and others.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 drivers/mfd/twl-core.c      |   12 ++++++---
 drivers/mfd/twl4030-power.c |   54 +++++++++++++++++++++++++++++++++++--------
 include/linux/i2c/twl.h     |    1 -
 3 files changed, 52 insertions(+), 15 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 89ab4d9..d1b9d14 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1023,6 +1023,14 @@ add_children(struct twl4030_platform_data *pdata, unsigned irq_base,
 			return PTR_ERR(child);
 	}
 
+	if (IS_ENABLED(CONFIG_TWL4030_POWER) && pdata->power) {
+		child = add_child(TWL_MODULE_PM_MASTER, "twl4030_power",
+				  pdata->power, sizeof(*pdata->power), false,
+				  0, 0);
+		if (IS_ERR(child))
+			return PTR_ERR(child);
+	}
+
 	return 0;
 }
 
@@ -1234,10 +1242,6 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		WARN(status < 0, "Error: reading twl_idcode register value\n");
 	}
 
-	/* load power event scripts */
-	if (IS_ENABLED(CONFIG_TWL4030_POWER) && pdata && pdata->power)
-		twl4030_power_init(pdata->power);
-
 	/* Maybe init the T2 Interrupt subsystem */
 	if (client->irq) {
 		if (twl_class_is_4030()) {
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index dd362c1..c9a2a5c 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -507,8 +507,9 @@ void twl4030_power_off(void)
 		pr_err("TWL4030 Unable to power off\n");
 }
 
-void twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
+int twl4030_power_probe(struct platform_device *pdev)
 {
+	struct twl4030_power_data *pdata = pdev->dev.platform_data;
 	int err = 0;
 	int i;
 	struct twl4030_resconfig *resconfig;
@@ -524,14 +525,14 @@ void twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
 	if (err)
 		goto unlock;
 
-	for (i = 0; i < twl4030_scripts->num; i++) {
-		err = load_twl4030_script(twl4030_scripts->scripts[i], address);
+	for (i = 0; i < pdata->num; i++) {
+		err = load_twl4030_script(pdata->scripts[i], address);
 		if (err)
 			goto load;
-		address += twl4030_scripts->scripts[i]->size;
+		address += pdata->scripts[i]->size;
 	}
 
-	resconfig = twl4030_scripts->resource_config;
+	resconfig = pdata->resource_config;
 	if (resconfig) {
 		while (resconfig->resource) {
 			err = twl4030_configure_resource(resconfig);
@@ -543,7 +544,7 @@ void twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
 	}
 
 	/* Board has to be wired properly to use this feature */
-	if (twl4030_scripts->use_poweroff && !pm_power_off) {
+	if (pdata->use_poweroff && !pm_power_off) {
 		/* Default for SEQ_OFFSYNC is set, lets ensure this */
 		err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
 				      TWL4030_PM_MASTER_CFG_P123_TRANSITION);
@@ -568,18 +569,51 @@ relock:
 			       TWL4030_PM_MASTER_PROTECT_KEY);
 	if (err)
 		pr_err("TWL4030 Unable to relock registers\n");
-	return;
+	return err;
 
 unlock:
 	if (err)
 		pr_err("TWL4030 Unable to unlock registers\n");
-	return;
+	return err;
 load:
 	if (err)
 		pr_err("TWL4030 failed to load scripts\n");
-	return;
+	return err;
 resource:
 	if (err)
 		pr_err("TWL4030 failed to configure resource\n");
-	return;
+	return err;
+}
+
+static int twl4030_power_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver twl4030_power_driver = {
+	.driver = {
+		.name	= "twl4030_power",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= twl4030_power_probe,
+	.remove		= twl4030_power_remove,
+};
+
+static int __init twl4030_power_init(void)
+{
+	return platform_driver_register(&twl4030_power_driver);
 }
+subsys_initcall(twl4030_power_init);
+
+static void __exit twl4030_power_exit(void)
+{
+	platform_driver_unregister(&twl4030_power_driver);
+}
+module_exit(twl4030_power_exit);
+
+MODULE_AUTHOR("Nokia Corporation");
+MODULE_AUTHOR("Texas Instruments, Inc.");
+MODULE_DESCRIPTION("Power management for TWL4030");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:twl4030_power");
+
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 488debb..2167c0d0 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -658,7 +658,6 @@ struct twl4030_power_data {
 	bool use_poweroff;	/* Board is wired for TWL poweroff */
 };
 
-extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
 extern int twl4030_remove_script(u8 flags);
 extern void twl4030_power_off(void);
 
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 30 09:51:56 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 30 May 2013 15:51:56 +0200
Subject: [PATCH 3/3] mfd: twl4030-power: Simplify error path
In-Reply-To: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369921916-7435-4-git-send-email-florian.vaussard@epfl.ch>

Remove unnecessary goto statements, causing duplicated if
conditions.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 drivers/mfd/twl4030-power.c |   37 ++++++++++++++-----------------------
 1 files changed, 14 insertions(+), 23 deletions(-)

diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index d12d748..7eed526 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -567,21 +567,25 @@ int twl4030_power_probe(struct platform_device *pdev)
 
 	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
 			       TWL4030_PM_MASTER_PROTECT_KEY);
-	if (err)
-		goto unlock;
-
-	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
+	err |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
 			       TWL4030_PM_MASTER_PROTECT_KEY);
-	if (err)
-		goto unlock;
+
+	if (err) {
+		pr_err("TWL4030 Unable to unlock registers\n");
+		return err;
+	}
 
 	if (pdata) {
 		err = twl4030_power_configure_scripts(pdata);
-		if (err)
-			goto load;
+		if (err) {
+			pr_err("TWL4030 failed to load scripts\n");
+			return err;
+		}
 		err = twl4030_power_configure_resources(pdata);
-		if (err)
-			goto resource;
+		if (err) {
+			pr_err("TWL4030 failed to configure resource\n");
+			return err;
+		}
 	}
 
 	/* Board has to be wired properly to use this feature */
@@ -611,19 +615,6 @@ relock:
 	if (err)
 		pr_err("TWL4030 Unable to relock registers\n");
 	return err;
-
-unlock:
-	if (err)
-		pr_err("TWL4030 Unable to unlock registers\n");
-	return err;
-load:
-	if (err)
-		pr_err("TWL4030 failed to load scripts\n");
-	return err;
-resource:
-	if (err)
-		pr_err("TWL4030 failed to configure resource\n");
-	return err;
 }
 
 static int twl4030_power_remove(struct platform_device *pdev)
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Thu May 30 09:51:55 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 30 May 2013 15:51:55 +0200
Subject: [PATCH 2/3] mfd: twl4030-power: Start transition to DT
In-Reply-To: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>
References: <1369921916-7435-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1369921916-7435-3-git-send-email-florian.vaussard@epfl.ch>

Support for loading twl4030-power module via devicetree.
For now, when booting with a DT, only the poweroff callback
feature is supported through the ti,use_poweroff property.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 .../devicetree/bindings/mfd/twl4030-power.txt      |   28 +++++++
 drivers/mfd/twl4030-power.c                        |   86 +++++++++++++++----
 2 files changed, 96 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-power.txt

diff --git a/Documentation/devicetree/bindings/mfd/twl4030-power.txt b/Documentation/devicetree/bindings/mfd/twl4030-power.txt
new file mode 100644
index 0000000..8e15ec3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/twl4030-power.txt
@@ -0,0 +1,28 @@
+Texas Instruments TWL family (twl4030) reset and power management module
+
+The power management module inside the TWL family provides several facilities
+to control the power resources, including power scripts. For now, the
+binding only supports the complete shutdown of the system after poweroff.
+
+Required properties:
+- compatible : must be "ti,twl4030-power"
+
+Optional properties:
+- ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or
+		   SLEEP-to-OFF transition when the system poweroffs.
+
+Example:
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl at 48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+
+		twl_power: power {
+			compatible = "ti,twl4030-power";
+			ti,use_poweroff;
+		};
+	};
+};
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index c9a2a5c..d12d748 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -28,6 +28,7 @@
 #include <linux/pm.h>
 #include <linux/i2c/twl.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 #include <asm/mach-types.h>
 
@@ -492,6 +493,39 @@ int twl4030_remove_script(u8 flags)
 	return err;
 }
 
+int twl4030_power_configure_scripts(struct twl4030_power_data *pdata)
+{
+	int err;
+	int i;
+	u8 address = twl4030_start_script_address;
+
+	for (i = 0; i < pdata->num; i++) {
+		err = load_twl4030_script(pdata->scripts[i], address);
+		if (err)
+			return err;
+		address += pdata->scripts[i]->size;
+	}
+
+	return 0;
+}
+
+int twl4030_power_configure_resources(struct twl4030_power_data *pdata)
+{
+	struct twl4030_resconfig *resconfig = pdata->resource_config;
+	int err;
+
+	if (resconfig) {
+		while (resconfig->resource) {
+			err = twl4030_configure_resource(resconfig);
+			if (err)
+				return err;
+			resconfig++;
+		}
+	}
+
+	return 0;
+}
+
 /*
  * In master mode, start the power off sequence.
  * After a successful execution, TWL shuts down the power to the SoC
@@ -507,13 +541,29 @@ void twl4030_power_off(void)
 		pr_err("TWL4030 Unable to power off\n");
 }
 
+static bool twl4030_power_use_poweroff(struct twl4030_power_data *pdata,
+					struct device_node *node)
+{
+	if (pdata && pdata->use_poweroff)
+		return true;
+
+	if (of_property_read_bool(node, "ti,use_poweroff"))
+		return true;
+
+	return false;
+}
+
 int twl4030_power_probe(struct platform_device *pdev)
 {
 	struct twl4030_power_data *pdata = pdev->dev.platform_data;
+	struct device_node *node = pdev->dev.of_node;
 	int err = 0;
-	int i;
-	struct twl4030_resconfig *resconfig;
-	u8 val, address = twl4030_start_script_address;
+	u8 val;
+
+	if (!pdata && !node) {
+		dev_err(&pdev->dev, "Platform data is missing\n");
+		return -EINVAL;
+	}
 
 	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
 			       TWL4030_PM_MASTER_PROTECT_KEY);
@@ -525,26 +575,17 @@ int twl4030_power_probe(struct platform_device *pdev)
 	if (err)
 		goto unlock;
 
-	for (i = 0; i < pdata->num; i++) {
-		err = load_twl4030_script(pdata->scripts[i], address);
+	if (pdata) {
+		err = twl4030_power_configure_scripts(pdata);
 		if (err)
 			goto load;
-		address += pdata->scripts[i]->size;
-	}
-
-	resconfig = pdata->resource_config;
-	if (resconfig) {
-		while (resconfig->resource) {
-			err = twl4030_configure_resource(resconfig);
-			if (err)
-				goto resource;
-			resconfig++;
-
-		}
+		err = twl4030_power_configure_resources(pdata);
+		if (err)
+			goto resource;
 	}
 
 	/* Board has to be wired properly to use this feature */
-	if (pdata->use_poweroff && !pm_power_off) {
+	if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) {
 		/* Default for SEQ_OFFSYNC is set, lets ensure this */
 		err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
 				      TWL4030_PM_MASTER_CFG_P123_TRANSITION);
@@ -590,10 +631,19 @@ static int twl4030_power_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id twl4030_power_of_match[] = {
+	{.compatible = "ti,twl4030-power", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, twl4030_power_of_match);
+#endif
+
 static struct platform_driver twl4030_power_driver = {
 	.driver = {
 		.name	= "twl4030_power",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(twl4030_power_of_match),
 	},
 	.probe		= twl4030_power_probe,
 	.remove		= twl4030_power_remove,
-- 
1.7.5.4



From maxime.ripard at free-electrons.com  Thu May 30 09:53:51 2013
From: maxime.ripard at free-electrons.com (maxime.ripard at free-electrons.com)
Date: Thu, 30 May 2013 15:53:51 +0200
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <20130529124108.GA415@pengutronix.de>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529075044.GC3293@lukather>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A4D0@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529101332.GC7356@pengutronix.de>
 <20130529121916.GF3293@lukather>
 <20130529124108.GA415@pengutronix.de>
Message-ID: <20130530135351.GH9799@lukather>

Hi Michael,

On Wed, May 29, 2013 at 02:41:08PM +0200, Michael Grzeschik wrote:
> Peters patches need some more care, as they are not cleanly sperated.
> One patch e.g. adds an delayed worker to handle the otg events. Another
> one above that patch is removing the worker afterwards.

I see, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


From egtvedt at samfundet.no  Thu May 30 10:05:55 2013
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Thu, 30 May 2013 16:05:55 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <20130530072328.GE19468@game.jcrosoft.org>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
 <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
 <20130529193220.GB19468@game.jcrosoft.org>
 <CACQ1gAj_m_aWaq5J41SY8EPwOH5-3zYPsf2WJCunvVnBCyq00Q@mail.gmail.com>
 <20130530072328.GE19468@game.jcrosoft.org>
Message-ID: <20130530140555.GA10370@samfundet.no>

Around Thu 30 May 2013 09:23:28 +0200 or thereabout, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:39 Thu 30 May     , Richard Genoud wrote:
>> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> > On 19:44 Wed 29 May     , Richard Genoud wrote:
>> >> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> >> > On 16:36 Wed 29 May     , Richard Genoud wrote:
>> >> >> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:

<snipp diff>

>> >> >> > +       bool                    lcdcon_pol_negative;
>> >> >> I think lcdcon_pol_negative should be part of pdata, because it really
>> >> >> depends on how the PWM is wired on the board.
>> >> >>
>> >> >
>> >> > maybe but no one mainline use it on any pdata for non-dt boars
>> >> > so I did not want to expose it
>> >> Well, at least, I'm using it :)
>> >> (and I guess that Andreas is using it also, otherwise he wouldn't have
>> >> introduce it !)
>> >
>> > yes but pdata is for non-dt boards, for dt you can keep it in struct
>> > atmel_lcdfb_info and add a property
>> >
>> > if non-dt boards want it my answer is I do not care switch to DT
>> 
>> ok (I use a full DT board based on sam9g35)
>> 
>> so I'll add something like
>> sinfo->lcdcon_pol_negative = of_property_read_bool(display_np,
>> "atmel,lcdcon-pwm-pulse-low");
>> in /atmel_lcdfb.c
>> 
>> But I thought the goal of this patch was to separate driver data from
>> platform specific data, and IMHO, lcdcon_pol_negative is a specificity
>> of the platform.
> 
> You are right but as non one mainline use it as pdata I choose to drop it
> and only keep it on the driver as we can still use it for DT
>
> It's a way to force peopoe to switch to DT

FYI AVR32 architecture doesn't support device tree, nor is it likely to do
so. However there are no users of the PWM output from the LCDC block for the
boards in the current kernel, and I doubt new boards will pop.

-- 
Hans-Christian Egtvedt


From shawn.guo at linaro.org  Thu May 30 10:23:32 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 22:23:32 +0800
Subject: [PATCH v3] dma: imx-sdma: move to generic device tree bindings
Message-ID: <1369923812-21767-1-git-send-email-shawn.guo@linaro.org>

Update imx-sdma driver to adopt generic DMA device tree bindings.  It
calls of_dma_controller_register() with imx-sdma specific of_dma_xlate
to get the generic DMA device tree helper support.  The #dma-cells for
imx-sdma must be 3, which includes request ID, peripheral type and
priority.

The existing way of requesting channel, clients directly call
dma_request_channel(), still work there, and will be removed after
all imx-sdma clients get converted to generic DMA device tree helper.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
Changes since v2:
 * Do not use macro for transfer type and priority, and hence the
   patch 1/2 in previous version is dropped.

 .../devicetree/bindings/dma/fsl-imx-sdma.txt       |   56 ++++++++++++++++++++
 drivers/dma/imx-sdma.c                             |   40 ++++++++++++++
 2 files changed, 96 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index d1e3f44..68cee4f5 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -4,14 +4,70 @@ Required properties:
 - compatible : Should be "fsl,<chip>-sdma"
 - reg : Should contain SDMA registers location and length
 - interrupts : Should contain SDMA interrupt
+- #dma-cells : Must be <3>.
+  The first cell specifies the DMA request/event ID.  See details below
+  about the second and third cell.
 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
   scripts firmware
 
+The second cell of dma phandle specifies the peripheral type of DMA transfer.
+The full ID of peripheral types can be found below.
+
+	ID	transfer type
+	---------------------
+	0	MCU domain SSI
+	1	Shared SSI
+	2	MMC
+	3	SDHC
+	4	MCU domain UART
+	5	Shared UART
+	6	FIRI
+	7	MCU domain CSPI
+	8	Shared CSPI
+	9	SIM
+	10	ATA
+	11	CCM
+	12	External peripheral
+	13	Memory Stick Host Controller
+	14	Shared Memory Stick Host Controller
+	15	DSP
+	16	Memory
+	17	FIFO type Memory
+	18	SPDIF
+	19	IPU Memory
+	20	ASRC
+	21	ESAI
+
+The third cell specifies the transfer priority as below.
+
+	ID	transfer priority
+	-------------------------
+	0	High
+	1	Medium
+	2	Low
+
 Examples:
 
 sdma at 83fb0000 {
 	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 	reg = <0x83fb0000 0x4000>;
 	interrupts = <6>;
+	#dma-cells = <3>;
 	fsl,sdma-ram-script-name = "sdma-imx51.bin";
 };
+
+DMA clients connected to the i.MX SDMA controller must use the format
+described in the dma.txt file.
+
+Examples:
+
+ssi2: ssi at 70014000 {
+	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+	reg = <0x70014000 0x4000>;
+	interrupts = <30>;
+	clocks = <&clks 49>;
+	dmas = <&sdma 24 1 0>,
+	       <&sdma 25 1 0>;
+	dma-names = "rx", "tx";
+	fsl,fifo-depth = <15>;
+};
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 092867b..1e44b8c 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -36,6 +36,7 @@
 #include <linux/dmaengine.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/of_dma.h>
 
 #include <asm/irq.h>
 #include <linux/platform_data/dma-imx-sdma.h>
@@ -1296,6 +1297,35 @@ err_dma_alloc:
 	return ret;
 }
 
+static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
+{
+	struct imx_dma_data *data = fn_param;
+
+	if (!imx_dma_is_general_purpose(chan))
+		return false;
+
+	chan->private = data;
+
+	return true;
+}
+
+static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
+				   struct of_dma *ofdma)
+{
+	struct sdma_engine *sdma = ofdma->of_dma_data;
+	dma_cap_mask_t mask = sdma->dma_device.cap_mask;
+	struct imx_dma_data data;
+
+	if (dma_spec->args_count != 3)
+		return NULL;
+
+	data.dma_request = dma_spec->args[0];
+	data.peripheral_type = dma_spec->args[1];
+	data.priority = dma_spec->args[2];
+
+	return dma_request_channel(mask, sdma_filter_fn, &data);
+}
+
 static int __init sdma_probe(struct platform_device *pdev)
 {
 	const struct of_device_id *of_id =
@@ -1443,10 +1473,20 @@ static int __init sdma_probe(struct platform_device *pdev)
 		goto err_init;
 	}
 
+	if (np) {
+		ret = of_dma_controller_register(np, sdma_xlate, sdma);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to register controller\n");
+			goto err_register;
+		}
+	}
+
 	dev_info(sdma->dev, "initialized\n");
 
 	return 0;
 
+err_register:
+	dma_async_device_unregister(&sdma->dma_device);
 err_init:
 	kfree(sdma->script_addrs);
 err_alloc:
-- 
1.7.9.5




From stern at rowland.harvard.edu  Thu May 30 10:23:27 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 30 May 2013 10:23:27 -0400 (EDT)
Subject: [PATCh V10 04/12] usb: ehci: ehci-mv: use PHY driver for ehci
In-Reply-To: <51A73BD8.8000007@ti.com>
Message-ID: <Pine.LNX.4.44L0.1305301020230.1321-100000@iolanthe.rowland.org>

On Thu, 30 May 2013, Roger Quadros wrote:

> >> So what are your idea about making the PHY layer more generic? How
> >> ehci-hcd will make use of PHY layer?
> > 
> > 
> > on probe grab the phy and initialize it. On suspend/resume,
> > suspend/resume the PHY and so on. Whatever you were going to do on your
> > ehci glue, do it on generic ehci-hcd.
> > 
> 
> These operations sound generic enough to be done at HCD layer, no? So no need to
> replicate the same stuff in ohci, ehci, xhci, etc.

The HCD layer handles suspend and resume only for PCI host controllers.  
Not for other types.

I don't know if the acquire/start and stop/release parts can be moved 
into the USB core.  Maybe they can.

Alan Stern



From andreas.biessmann at corscience.de  Thu May 30 10:27:38 2013
From: andreas.biessmann at corscience.de (=?ISO-8859-1?Q?Andreas_Bie=DFmann?=)
Date: Thu, 30 May 2013 16:27:38 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <20130530072328.GE19468@game.jcrosoft.org>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
 <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
 <20130529193220.GB19468@game.jcrosoft.org>
 <CACQ1gAj_m_aWaq5J41SY8EPwOH5-3zYPsf2WJCunvVnBCyq00Q@mail.gmail.com>
 <20130530072328.GE19468@game.jcrosoft.org>
Message-ID: <51A761DA.6020109@corscience.de>

On 30.05.13 09:23, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:39 Thu 30 May     , Richard Genoud wrote:
>> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>>> On 19:44 Wed 29 May     , Richard Genoud wrote:
>>>> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>>>>> On 16:36 Wed 29 May     , Richard Genoud wrote:
>>>>>> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>>>>>>> Today we mix pdata and drivers data in the struct atmel_lcdfb_info
>>>>>>> Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
>>>>>>>
>>>>>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>>>>>> Cc: linux-fbdev at vger.kernel.org
>>>>>>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>>>>>>> Cc: Andrew Morton <akpm at linux-foundation.org>
>>>>>>> Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
>>>>>>> ---
>>>>>>>  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
>>>>>>>  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
>>>>>>>  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
>>>>>>>  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
>>>>>>>  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
>>>>>>>  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
>>>>>>>  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
>>>>>>>  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
>>>>>>>  arch/arm/mach-at91/board.h                  |    4 +-
>>>>>>>  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
>>>>>>>  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
>>>>>>>  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
>>>>>>>  arch/avr32/boards/atstk1000/setup.c         |    2 +-
>>>>>>>  arch/avr32/boards/favr-32/setup.c           |    2 +-
>>>>>>>  arch/avr32/boards/hammerhead/setup.c        |    2 +-
>>>>>>>  arch/avr32/boards/merisc/display.c          |    2 +-
>>>>>>>  arch/avr32/boards/mimc200/setup.c           |    4 +-
>>>>>>>  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
>>>>>>>  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
>>>>>>>  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
>>>>>>>  include/video/atmel_lcdc.h                  |   24 +------
>>>>>>>  21 files changed, 109 insertions(+), 101 deletions(-)
>>>>>>>
>>>>>> [snip]
>>>>>>> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
>>>>>>> index c1a2914..98733cd4 100644
>>>>>>> --- a/drivers/video/atmel_lcdfb.c
>>>>>>> +++ b/drivers/video/atmel_lcdfb.c
>>>>>>> @@ -20,12 +20,45 @@
>>>>>>>  #include <linux/gfp.h>
>>>>>>>  #include <linux/module.h>
>>>>>>>  #include <linux/platform_data/atmel.h>
>>>>>>> +#include <video/of_display_timing.h>
>>>>>>>
>>>>>>>  #include <mach/cpu.h>
>>>>>>>  #include <asm/gpio.h>
>>>>>>>
>>>>>>>  #include <video/atmel_lcdc.h>
>>>>>>>
>>>>>>> +struct atmel_lcdfb_config {
>>>>>>> +       bool have_alt_pixclock;
>>>>>>> +       bool have_hozval;
>>>>>>> +       bool have_intensity_bit;
>>>>>>> +};
>>>>>>> +
>>>>>>> + /* LCD Controller info data structure, stored in device platform_data */
>>>>>>> +struct atmel_lcdfb_info {
>>>>>>> +       spinlock_t              lock;
>>>>>>> +       struct fb_info          *info;
>>>>>>> +       void __iomem            *mmio;
>>>>>>> +       int                     irq_base;
>>>>>>> +       struct work_struct      task;
>>>>>>> +
>>>>>>> +       unsigned int            smem_len;
>>>>>>> +       struct platform_device  *pdev;
>>>>>>> +       struct clk              *bus_clk;
>>>>>>> +       struct clk              *lcdc_clk;
>>>>>>> +
>>>>>>> +       struct backlight_device *backlight;
>>>>>>> +       u8                      bl_power;
>>>>>>> +       bool                    lcdcon_pol_negative;
>>>>>> I think lcdcon_pol_negative should be part of pdata, because it really
>>>>>> depends on how the PWM is wired on the board.
>>>>>>
>>>>>
>>>>> maybe but no one mainline use it on any pdata for non-dt boars
>>>>> so I did not want to expose it
>>>> Well, at least, I'm using it :)
>>>> (and I guess that Andreas is using it also, otherwise he wouldn't have
>>>> introduce it !)
>>>
>>> yes but pdata is for non-dt boards, for dt you can keep it in struct
>>> atmel_lcdfb_info and add a property
>>>
>>> if non-dt boards want it my answer is I do not care switch to DT
>>
>> ok (I use a full DT board based on sam9g35)
>>
>> so I'll add something like
>> sinfo->lcdcon_pol_negative = of_property_read_bool(display_np,
>> "atmel,lcdcon-pwm-pulse-low");
>> in /atmel_lcdfb.c
>>
>> But I thought the goal of this patch was to separate driver data from
>> platform specific data, and IMHO, lcdcon_pol_negative is a specificity
>> of the platform.
> 
> You are right but as non one mainline use it as pdata I choose to drop it
> and only keep it on the driver as we can still use it for DT
> 
> It's a way to force peopoe to switch to DT

well, we use it on an avr32 board (not mainlined; though no kernel
update planned currently) ... but no way to use DT currently.

Best regards

Andreas Bie?mann


From daniel.lezcano at linaro.org  Thu May 30 10:35:41 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Thu, 30 May 2013 16:35:41 +0200
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <1369912782-30663-4-git-send-email-josephl@nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
Message-ID: <51A763BD.6070001@linaro.org>

On 05/30/2013 01:19 PM, Joseph Lo wrote:
> This supports CPU core power down on each CPU when CPU idle. When CPU go
> into this state, it saves it's context and needs a proper configuration
> in flow controller to power gate the CPU when CPU runs into WFI
> instruction. And the CPU also needs to set the IRQ as CPU power down idle
> wake up event in flow controller.
> 
> Signed-off-by: Joseph Lo <josephl at nvidia.com>
> ---

Hi Joseph,

a new flag has been added in the cpuidle framework to let this one to
handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP

It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c

You can get rid of the clockevent notify stuff by adding this flag to
the state.

Also, can you clarify why tegra3 code is used in tegra114 ?


>  arch/arm/mach-tegra/cpuidle-tegra114.c | 62 +++++++++++++++++++++++++++++++++-
>  1 file changed, 61 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
> index 1d1c602..e7d21f5 100644
> --- a/arch/arm/mach-tegra/cpuidle-tegra114.c
> +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
> @@ -17,19 +17,79 @@
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/cpuidle.h>
> +#include <linux/cpu_pm.h>
> +#include <linux/clockchips.h>
>  
>  #include <asm/cpuidle.h>
> +#include <asm/suspend.h>
> +#include <asm/smp_plat.h>
> +
> +#include "pm.h"
> +#include "sleep.h"
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int tegra114_idle_power_down(struct cpuidle_device *dev,
> +				    struct cpuidle_driver *drv,
> +				    int index);

Isn't possible to move the driver declaration after the
tegra114_idle_power_down function, before the init function, so we
prevent a forward declaration ?

> +#define TEGRA114_MAX_STATES 2
> +#else
> +#define TEGRA114_MAX_STATES 1
> +#endif
>  
>  static struct cpuidle_driver tegra_idle_driver = {
>  	.name = "tegra_idle",
>  	.owner = THIS_MODULE,
> -	.state_count = 1,
> +	.state_count = TEGRA114_MAX_STATES,
>  	.states = {
>  		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
> +#ifdef CONFIG_PM_SLEEP
> +		[1] = {
> +			.enter			= tegra114_idle_power_down,
> +			.exit_latency		= 500,
> +			.target_residency	= 1000,
> +			.power_usage		= 0,
> +			.flags			= CPUIDLE_FLAG_TIME_VALID,
> +			.name			= "powered-down",
> +			.desc			= "CPU power gated",
> +		},
> +#endif
>  	},
>  };
>  
> +#ifdef CONFIG_PM_SLEEP
> +static int tegra114_idle_power_down(struct cpuidle_device *dev,
> +				    struct cpuidle_driver *drv,
> +				    int index)
> +{
> +	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;

IMO, it is up to the tegra_set_cpu_in_lp2 / tegra_clear_cpu_in_lp2
functions to do the cpu map conversion instead of adding this into a
routine working with logical cpu.

> +	local_fiq_disable();
> +
> +	tegra_set_cpu_in_lp2(cpu);
> +	cpu_pm_enter();
> +
> +	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
> +	smp_wmb();

Why do you need a memory barrier here ?

> +	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
> +
> +	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
> +
> +	cpu_pm_exit();
> +	tegra_clear_cpu_in_lp2(cpu);
> +
> +	local_fiq_enable();
> +
> +	smp_rmb();

Why do you need a memory barrier here ?

> +	return index;
> +}
> +#endif
> +
>  int __init tegra114_cpuidle_init(void)
>  {
> +#ifdef CONFIG_PM_SLEEP
> +	tegra_tear_down_cpu = tegra30_tear_down_cpu;
> +#endif

Doesn't this code should go in the pm.c file ?

>  	return cpuidle_register(&tegra_idle_driver, NULL);
>  }
> 


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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From christoffer.dall at linaro.org  Thu May 30 10:44:14 2013
From: christoffer.dall at linaro.org (Christoffer Dall)
Date: Thu, 30 May 2013 07:44:14 -0700
Subject: [GIT PULL] KVM/ARM Fixes for 3.10
In-Reply-To: <CAEDV+gJrWqoMdqibetTo++FzW6NXE5QkF0TCTHoFJmadmpeKiQ@mail.gmail.com>
References: <CAMJs5B8qTMpaaq0y=xGUrTzUd_-LvmARdGABV8PdpqmWUkPoqw@mail.gmail.com>
 <51A6E78F.3070902@redhat.com>
 <CAEDV+gJrWqoMdqibetTo++FzW6NXE5QkF0TCTHoFJmadmpeKiQ@mail.gmail.com>
Message-ID: <20130530144414.GA56688@ubuntu>

On Thu, May 30, 2013 at 07:20:23AM -0700, Christoffer Dall wrote:
> On Wed, May 29, 2013 at 10:45 PM, Paolo Bonzini <pbonzini at redhat.com> wrote:
> 
> > Il 30/05/2013 03:39, Christoffer Dall ha scritto:
> > > The following changes since commit
> > e47a5f5fb715b90b40747e9e235de557c6abd56c:
> > >
> > >   KVM: x86 emulator: convert XADD to fastop (2013-05-21 15:43:24 +0300)
> >
> > Chris,
> >
> > this is based on the "next" branch, which will not be merged until the
> > 3.11 merge window.  Please base your 3.10 fixes on the "master" branch
> > of kvm.git.
> >
> > Thanks!
> >
> > Paolo
> >
> >
Duh, sorry about that. Here's the new pull request (I just rebased the same
branch):


The following changes since commit 514e250f67d2b2a8ab08dc9c3650af19a411c926:

  Merge tag 'gpio-fixes-v3.10-1' of git://
git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio (2013-05-23
18:24:10 -0700)

are available in the git repository at:


  git://github.com/columbia/linux-kvm-arm.git kvm-arm-fixes-3.10

for you to fetch changes up to edd89c08e6570bb88a3f275bf0d7cffcea2f1e87:

  ARM: KVM: be more thorough when invalidating TLBs (2013-05-30 07:17:07
-0700)

----------------------------------------------------------------
Andre Przywara (1):
      ARM: KVM: prevent NULL pointer dereferences with KVM VCPU ioctl

Marc Zyngier (1):
      ARM: KVM: be more thorough when invalidating TLBs

 arch/arm/kvm/arm.c |   15 +++++++++++++--
 arch/arm/kvm/mmu.c |   41 ++++++++++++++++++++++++++---------------
 2 files changed, 39 insertions(+), 17 deletions(-)


From arnd at arndb.de  Thu May 30 10:45:09 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 30 May 2013 16:45:09 +0200
Subject: [PATCH v3] dma: imx-sdma: move to generic device tree bindings
In-Reply-To: <1369923812-21767-1-git-send-email-shawn.guo@linaro.org>
References: <1369923812-21767-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <201305301645.09964.arnd@arndb.de>

On Thursday 30 May 2013, Shawn Guo wrote:
> Update imx-sdma driver to adopt generic DMA device tree bindings.  It
> calls of_dma_controller_register() with imx-sdma specific of_dma_xlate
> to get the generic DMA device tree helper support.  The #dma-cells for
> imx-sdma must be 3, which includes request ID, peripheral type and
> priority.
> 
> The existing way of requesting channel, clients directly call
> dma_request_channel(), still work there, and will be removed after
> all imx-sdma clients get converted to generic DMA device tree helper.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From shawn.guo at linaro.org  Thu May 30 10:46:04 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 22:46:04 +0800
Subject: [PATCH] ARM: imx: Remove mxc specific ulpi access ops
In-Reply-To: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>
References: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>
Message-ID: <20130530144601.GA22013@S2101-09.ap.freescale.net>

On Thu, May 30, 2013 at 02:44:55PM +0200, Markus Pargmann wrote:
> There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c.
> mxc access ops implement the same access operations within mach-imx. This
> patch removes the mxc ulpi file and uses phy-ulpi instead for
> imx_otg_ulpi_create.
> 
> phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100).
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/mach-imx/Kconfig       |   1 +
>  arch/arm/mach-imx/Makefile      |   1 -
>  arch/arm/mach-imx/mach-pca100.c |   4 +-
>  arch/arm/mach-imx/ulpi.c        | 118 ----------------------------------------
>  arch/arm/mach-imx/ulpi.h        |   9 ++-
>  5 files changed, 9 insertions(+), 124 deletions(-)
>  delete mode 100644 arch/arm/mach-imx/ulpi.c
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index ba44328..ca59799 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -58,6 +58,7 @@ config MXC_USE_EPIT
>  
>  config MXC_ULPI
>  	bool
> +	select USB_ULPI_VIEWPORT

Is MXC_ULPI still used anywhere after you remove ulpi.c in the patch?
You are even patching it, so I'm a little confused.

Shawn



From mpa at pengutronix.de  Thu May 30 10:51:52 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:52 +0200
Subject: [PATCH v7 10/11] ASoC: fsl: Move fsl-ssi binding doc to sound/
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-11-git-send-email-mpa@pengutronix.de>

fsl-ssi was located in powerpc/fsl/ssi.txt. This is no powerpc specific
device, so it should be moved to sound/ as it connects to differen audio
codecs.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 .../devicetree/bindings/{powerpc/fsl/ssi.txt => sound/fsl,ssi.txt}        | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc/fsl/ssi.txt => sound/fsl,ssi.txt} (100%)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/ssi.txt
rename to Documentation/devicetree/bindings/sound/fsl,ssi.txt
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:50 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:50 +0200
Subject: [PATCH v7 08/11] ASoC: phycore-ac97: Add DT support
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-9-git-send-email-mpa@pengutronix.de>

Add devicetree support for phycore-ac97 driver.

platform_of_node and cpu_of_node are set according to the fsl,audmux
phandle.

This patch adds handling of ac97 reset functions according to fsl ac97
support. They are setup from here to avoid board specific code in the
generic fsl-ssi driver.

This patch changes the handling of pca100 boards from non-DT to DT only.
pcm043 is still handled without DT.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v7:
     - Declare empty ac97 reset functions static.
     - Replace complicated machine compatible comparison with
       of_machine_is_compatible
     - Missing snd_soc_unregister_card in imx_phycore_ac97_remove
     - Rename driver
    
    Changes in v6:
     - phycore-ac97 now manages the ac97 reset functions of the boards using
       this combination of ssi-codec.
     - Removed preprocessor ifs for DT, non-DT distinction. pcm043 is now
       non-DT only and pca100 DT only.
    
    Changes in v4:
     - New property phytec,audmux to check which audmux setup should be
       executed. Checking for fsl,imx21-audmux and fsl,imx31-audmux.
    
    Changes in v3:
     - Add some more information in the commit message.
    
    Changes in v2:
     - Simplify the driver, by combining audmux port configurations. The
       audmux driver actually knows on which platform he is running and
       will return the appropriate error code if we use functions for
       another platform. So we don't need to have the knowledge about it
       in phycore-ac97 and can try both functions. This removes the need
       of different compatibilities and renames it to phycore-ac97.
     - Use a phandle for the cpu_dai link.
     - Add devicetree binding documentation.
     - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
    
    Changes in v2:
     - Simplify the driver, by combining audmux port configurations. The
       audmux driver actually knows on which platform he is running and
       will return the appropriate error code if we use functions for
       another platform. So we don't need to have the knowledge about it
       in phycore-ac97 and can try both functions. This removes the need
       of different compatibilities and renames it to imx27-ac97.
     - Use a phandle for the cpu_dai link.
     - Add devicetree binding documentation.
     - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
    
    Changes in v7:
     - Declare empty ac97 reset functions static.
     - Replace complicated machine compatible comparison with
       of_machine_is_compatible
     - Missing snd_soc_unregister_card in imx_phycore_ac97_remove
    
    Changes in v6:
     - phycore-ac97 now manages the ac97 reset functions of the boards using
       this combination of ssi-codec.
     - Removed preprocessor ifs for DT, non-DT distinction. pcm043 is now
       non-DT only and pca100 DT only.
    
    Changes in v4:
     - New property phytec,audmux to check which audmux setup should be
       executed. Checking for fsl,imx21-audmux and fsl,imx31-audmux.
    
    Changes in v3:
     - Add some more information in the commit message.
    
    Changes in v2:
     - Simplify the driver, by combining audmux port configurations. The
       audmux driver actually knows on which platform he is running and
       will return the appropriate error code if we use functions for
       another platform. So we don't need to have the knowledge about it
       in phycore-ac97 and can try both functions. This removes the need
       of different compatibilities and renames it to phycore-ac97.
     - Use a phandle for the cpu_dai link.
     - Add devicetree binding documentation.
     - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi
    
    Changes in v2:
     - Simplify the driver, by combining audmux port configurations. The
       audmux driver actually knows on which platform he is running and
       will return the appropriate error code if we use functions for
       another platform. So we don't need to have the knowledge about it
       in phycore-ac97 and can try both functions. This removes the need
       of different compatibilities and renames it to imx27-ac97.
     - Use a phandle for the cpu_dai link.
     - Add devicetree binding documentation.
     - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi

 .../bindings/sound/phytec,phycore-ac97.txt         |  14 ++
 sound/soc/fsl/phycore-ac97.c                       | 236 ++++++++++++++++++---
 2 files changed, 224 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt

diff --git a/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
new file mode 100644
index 0000000..41201ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt
@@ -0,0 +1,14 @@
+Phytec phycore AC97
+
+Required properties:
+- compatible: "phytec,phycore-ac97"
+- phytec,ssi: A phandle to the ssi device that is connected to ac97.
+- phytec,audmux: A phandle to the audmux device.
+
+Example:
+
+sound {
+	compatible = "phytec,phycore-ac97";
+	phytec,ssi = <&ssi1>;
+	phytec,audmux = <&audmux>;
+};
diff --git a/sound/soc/fsl/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
index ae403c2..5eb756c9 100644
--- a/sound/soc/fsl/phycore-ac97.c
+++ b/sound/soc/fsl/phycore-ac97.c
@@ -20,8 +20,14 @@
 #include <asm/mach-types.h>
 
 #include "imx-audmux.h"
+#include "fsl_ssi.h"
+
+#define DRV_NAME "phycore-audio-fabric"
 
 static struct snd_soc_card imx_phycore;
+static struct device_node *phycore_dai_cpu_node;
+static void (*phycore_ac97_reset) (struct snd_ac97 *ac97);
+static void (*phycore_ac97_warm_reset)(struct snd_ac97 *ac97);
 
 static struct snd_soc_ops imx_phycore_hifi_ops = {
 };
@@ -32,12 +38,12 @@ static struct snd_soc_dai_link imx_phycore_dai_ac97[] = {
 		.stream_name	= "HiFi",
 		.codec_dai_name		= "wm9712-hifi",
 		.codec_name	= "wm9712-codec",
-		.cpu_dai_name	= "imx-ssi.0",
-		.platform_name	= "imx-ssi.0",
 		.ops		= &imx_phycore_hifi_ops,
 	},
 };
 
+static const char phycore_ac97_plat_name[] = "imx-ssi.0";
+
 static struct snd_soc_card imx_phycore = {
 	.name		= "PhyCORE-ac97-audio",
 	.owner		= THIS_MODULE,
@@ -45,40 +51,52 @@ static struct snd_soc_card imx_phycore = {
 	.num_links	= ARRAY_SIZE(imx_phycore_dai_ac97),
 };
 
-static struct platform_device *imx_phycore_snd_ac97_device;
+static void phycore_ac97_imx21_audmux(void)
+{
+	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V1_PCR_TFCSEL(3) |
+		IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+		IMX_AUDMUX_V1_PCR_RXDSEL(3));
+	imx_audmux_v1_configure_port(3,
+		IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V1_PCR_TFCSEL(0) |
+		IMX_AUDMUX_V1_PCR_TFSDIR |
+		IMX_AUDMUX_V1_PCR_RXDSEL(0));
+}
+
+static void phycore_ac97_imx31_audmux(void)
+{
+	imx_audmux_v2_configure_port(3,
+		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V2_PTCR_TFSEL(0) |
+		IMX_AUDMUX_V2_PTCR_TFSDIR,
+		IMX_AUDMUX_V2_PDCR_RXDSEL(0));
+	imx_audmux_v2_configure_port(0,
+		IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+		IMX_AUDMUX_V2_PTCR_TCSEL(3) |
+		IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+		IMX_AUDMUX_V2_PDCR_RXDSEL(3));
+}
+
 static struct platform_device *imx_phycore_snd_device;
 
+static struct platform_device *imx_phycore_snd_ac97_device;
+
 static int __init imx_phycore_init(void)
 {
 	int ret;
 
-	if (machine_is_pca100()) {
-		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V1_PCR_TFCSEL(3) |
-			IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-			IMX_AUDMUX_V1_PCR_RXDSEL(3));
-		imx_audmux_v1_configure_port(3,
-			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V1_PCR_TFCSEL(0) |
-			IMX_AUDMUX_V1_PCR_TFSDIR |
-			IMX_AUDMUX_V1_PCR_RXDSEL(0));
-	} else if (machine_is_pcm043()) {
-		imx_audmux_v2_configure_port(3,
-			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V2_PTCR_TFSEL(0) |
-			IMX_AUDMUX_V2_PTCR_TFSDIR,
-			IMX_AUDMUX_V2_PDCR_RXDSEL(0));
-		imx_audmux_v2_configure_port(0,
-			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			IMX_AUDMUX_V2_PTCR_TCSEL(3) |
-			IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-			IMX_AUDMUX_V2_PDCR_RXDSEL(3));
+	if (machine_is_pcm043()) {
+		phycore_ac97_imx31_audmux();
 	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
 	}
 
+	imx_phycore_dai_ac97[0].cpu_dai_name = phycore_ac97_plat_name;
+	imx_phycore_dai_ac97[0].platform_name = phycore_ac97_plat_name;
+
 	imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
 	if (!imx_phycore_snd_ac97_device)
 		return -ENOMEM;
@@ -108,18 +126,184 @@ fail2:
 	platform_device_del(imx_phycore_snd_ac97_device);
 fail1:
 	platform_device_put(imx_phycore_snd_ac97_device);
+	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
+	imx_phycore_dai_ac97[0].platform_name = NULL;
 	return ret;
 }
 
 static void __exit imx_phycore_exit(void)
 {
+	if (!machine_is_pcm043())
+		return;
+
 	platform_device_unregister(imx_phycore_snd_device);
 	platform_device_unregister(imx_phycore_snd_ac97_device);
+
+	imx_phycore_dai_ac97[0].cpu_dai_name = NULL;
+	imx_phycore_dai_ac97[0].platform_name = NULL;
 }
 
 late_initcall(imx_phycore_init);
 module_exit(imx_phycore_exit);
 
+
+static const struct of_device_id imx_phycore_ac97_of_dev_id[] = {
+	{
+		.compatible = "phytec,phycore-ac97",
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx_phycore_ac97_of_dev_id);
+
+
+/*
+ * Pointer to AC97 reset functions for specific boards
+ */
+#if IS_ENABLED(CONFIG_MACH_PCA100)
+extern void pca100_ac97_cold_reset(struct snd_ac97 *ac97);
+extern void pca100_ac97_warm_reset(struct snd_ac97 *ac97);
+#else
+static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) { }
+static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) { }
+#endif
+
+#if IS_ENABLED(CONFIG_MACH_PCM043)
+extern void pcm043_ac97_cold_reset(struct snd_ac97 *ac97);
+extern void pcm043_ac97_warm_reset(struct snd_ac97 *ac97);
+#else
+static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { }
+static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { }
+#endif
+
+static void phycore_soc_ac97_reset(struct snd_ac97 *ac97)
+{
+	if (phycore_ac97_reset)
+		phycore_ac97_reset(ac97);
+	/* First read sometimes fails, do a dummy read */
+	fsl_ssi_ac97_read(ac97, 0);
+}
+
+static void phycore_soc_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+	if (phycore_ac97_warm_reset)
+		phycore_ac97_warm_reset(ac97);
+
+	/* First read sometimes fails, do a dummy read */
+	fsl_ssi_ac97_read(ac97, 0);
+}
+
+static int phycore_ac97_setup_devices(struct platform_device *pdev)
+{
+	int ret;
+
+	imx_phycore_snd_device = platform_device_alloc("wm9712-codec", -1);
+	if (!imx_phycore_snd_device)
+		return -ENOMEM;
+
+	ret = platform_device_add(imx_phycore_snd_device);
+	if (ret) {
+		dev_err(&pdev->dev, "ASoC: Platform device allocation failed\n");
+		goto fail1;
+	}
+
+	ret = snd_soc_register_card(&imx_phycore);
+	if (ret) {
+		dev_err(&pdev->dev, "ASoC: soc card registration failed\n");
+		goto fail2;
+	}
+	return 0;
+
+fail2:
+	platform_device_del(imx_phycore_snd_device);
+fail1:
+	platform_device_put(imx_phycore_snd_device);
+	return ret;
+}
+
+static int imx_phycore_ac97_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct device_node *ssi_np;
+	struct device_node *audmux_np;
+
+	imx_phycore.dev = &pdev->dev;
+
+	audmux_np = of_parse_phandle(pdev->dev.of_node, "phytec,audmux", 0);
+	if (!audmux_np) {
+		dev_err(&pdev->dev, "Failed to parse phytec,audmux phandle\n");
+		return -EINVAL;
+	}
+
+	if (of_device_is_compatible(audmux_np, "fsl,imx21-audmux")) {
+		phycore_ac97_imx21_audmux();
+	} else if (of_device_is_compatible(audmux_np, "fsl,imx31-audmux")) {
+		phycore_ac97_imx31_audmux();
+	} else {
+		dev_err(&pdev->dev, "Unknown audmux, failed to setup audmux\n");
+		of_node_put(audmux_np);
+		return -EINVAL;
+	}
+	of_node_put(audmux_np);
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "phytec,ssi", 0);
+	if (!ssi_np) {
+		dev_err(&pdev->dev, "No valid ssi phandle found\n");
+		return -EINVAL;
+	}
+
+	imx_phycore_dai_ac97[0].cpu_of_node = ssi_np;
+	imx_phycore_dai_ac97[0].platform_of_node = ssi_np;
+	phycore_dai_cpu_node = ssi_np;
+
+	if (of_machine_is_compatible("phytec,imx27-pca100")) {
+		phycore_ac97_reset = pca100_ac97_cold_reset;
+		phycore_ac97_warm_reset = pca100_ac97_warm_reset;
+	} else if (of_machine_is_compatible("phytec,imx35-pcm043")) {
+		phycore_ac97_reset = pcm043_ac97_cold_reset;
+		phycore_ac97_warm_reset = pcm043_ac97_warm_reset;
+	} else {
+		dev_err(&pdev->dev, "Failed to set AC97 reset functions, unknown board.\n");
+		return -EINVAL;
+	}
+
+	fsl_ssi_ac97_set_reset(phycore_soc_ac97_reset,
+			phycore_soc_ac97_warm_reset);
+
+	ret = phycore_ac97_setup_devices(pdev);
+	if (ret)
+		of_node_put(phycore_dai_cpu_node);
+
+	return ret;
+}
+
+static int imx_phycore_ac97_remove(struct platform_device *pdev)
+{
+	of_node_put(phycore_dai_cpu_node);
+	phycore_dai_cpu_node = NULL;
+
+	snd_soc_unregister_card(&imx_phycore);
+
+	platform_device_unregister(imx_phycore_snd_device);
+
+	phycore_ac97_reset = NULL;
+	phycore_ac97_warm_reset = NULL;
+
+	return 0;
+}
+
+static struct platform_driver imx_phycore_ac97_driver = {
+	.probe		= imx_phycore_ac97_probe,
+	.remove		= imx_phycore_ac97_remove,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table = imx_phycore_ac97_of_dev_id,
+	},
+};
+
+module_platform_driver(imx_phycore_ac97_driver);
+
 MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
-MODULE_DESCRIPTION("PhyCORE ALSA SoC driver");
+MODULE_DESCRIPTION(DRV_NAME ": PhyCORE ALSA SoC AC97 audio driver");
 MODULE_LICENSE("GPL");
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:48 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:48 +0200
Subject: [PATCH v7 06/11] ASoC: fsl-ssi: imx ac97 support
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-7-git-send-email-mpa@pengutronix.de>

This patch copies some parts from imx-ssi to support AC97 on
imx27-pca100 and imx35-pcm043. This is a implementation of the
ac97-slave mode.

For ac97, the registers have to be setup earlier than for other ssi
modes because there is some communication with the external device
before actual streaming. So this patch introduces a fsl_ssi_setup
function to setup the registers at different times.

To seperate board specific ac97 reset functions, ac97 read/write
functions are exported. The reset functions are set by other drivers.

This patch was tested with imx27-pca100.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v7:
     - ac97 ops are now assigned to soc_ac97_ops to allow enabled imx-ssi and
       fsl-ssi at the same time.
    
    Changes in v6:
     - ac97 reset functions are not provided by fsl-ssi code anymore. They were
       moved to board specific code like phycore-ac97. Therefore ac97 read/write
       functions are exported and a helper function to set the soc_ac97_ops reset
       functions was created.
    
    Changes in v3:
     - Cleanup ac97 code by adding a fsl_ssi_setup function for initial register
       setup. For ac97 the registers have to be setup earlier than in normal
       mode.

 sound/soc/fsl/fsl_ssi.c | 363 ++++++++++++++++++++++++++++++++++++++----------
 sound/soc/fsl/fsl_ssi.h |   7 +
 2 files changed, 298 insertions(+), 72 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index ed1fbbb..7c20bd7 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -141,6 +141,7 @@ struct fsl_ssi_private {
 
 	bool new_binding;
 	bool ssi_on_imx;
+	bool imx_ac97;
 	bool use_dma;
 	struct clk *clk;
 	struct snd_dmaengine_dai_dma_data dma_params_tx;
@@ -320,6 +321,124 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	return ret;
 }
 
+static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
+{
+	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+	u8 i2s_mode;
+	u8 wm;
+	int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
+
+	if (ssi_private->imx_ac97)
+		i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
+	else
+		i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
+
+	/*
+	 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
+	 * to be disabled before updating the registers we set here.
+	 */
+	write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
+
+	/*
+	 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
+	 * enable the transmit and receive FIFO.
+	 *
+	 * FIXME: Little-endian samples require a different shift dir
+	 */
+	write_ssi_mask(&ssi->scr,
+		CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
+		CCSR_SSI_SCR_TFR_CLK_DIS |
+		i2s_mode |
+		(synchronous ? CCSR_SSI_SCR_SYN : 0));
+
+	write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
+		 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
+
+	write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
+		 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
+	/*
+	 * The DC and PM bits are only used if the SSI is the clock master.
+	 */
+
+	/*
+	 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
+	 * use FIFO 1. We program the transmit water to signal a DMA transfer
+	 * if there are only two (or fewer) elements left in the FIFO. Two
+	 * elements equals one frame (left channel, right channel). This value,
+	 * however, depends on the depth of the transmit buffer.
+	 *
+	 * We set the watermark on the same level as the DMA burstsize.  For
+	 * fiq it is probably better to use the biggest possible watermark
+	 * size.
+	 */
+	if (ssi_private->use_dma)
+		wm = ssi_private->fifo_depth - 2;
+	else
+		wm = ssi_private->fifo_depth;
+
+	write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
+		CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
+		&ssi->sfcsr);
+
+	/*
+	 * For non-ac97 setups, we keep the SSI disabled because if we enable
+	 * it, then the DMA controller will start. It's not supposed to start
+	 * until the SCR.TE (or SCR.RE) bit is set, but it does anyway. The DMA
+	 * controller will transfer one "BWC" of data (i.e. the amount of data
+	 * that the MR.BWC bits are set to). The reason this is bad is because
+	 * at this point, the PCM driver has not finished initializing the DMA
+	 * controller.
+	 */
+
+
+	/*
+	 * For ac97 interrupts are enabled with the startup of the substream
+	 * because it is also running without an active substream. Normally SSI
+	 * is only enabled when there is a substream.
+	 */
+	if (!ssi_private->imx_ac97) {
+		/* Enable the interrupts and DMA requests */
+		if (ssi_private->use_dma)
+			write_ssi(SIER_FLAGS, &ssi->sier);
+		else
+			write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
+					CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
+	} else {
+		/*
+		 * Setup the clock control register
+		 */
+		write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
+				&ssi->stccr);
+		write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
+				&ssi->srccr);
+
+		/*
+		 * Enable AC97 mode and startup the SSI
+		 */
+		write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
+				&ssi->sacnt);
+		write_ssi(0xff, &ssi->saccdis);
+		write_ssi(0x300, &ssi->saccen);
+
+		/*
+		 * Enable SSI
+		 */
+		write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
+		write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
+
+		/*
+		 * Enable Transmit and Receive
+		 */
+		write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
+	}
+
+	return 0;
+}
+
+
 /**
  * fsl_ssi_startup: create a new substream
  *
@@ -341,75 +460,14 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 	 * and initialize the SSI registers.
 	 */
 	if (!ssi_private->first_stream) {
-		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
-
 		ssi_private->first_stream = substream;
 
 		/*
-		 * Section 16.5 of the MPC8610 reference manual says that the
-		 * SSI needs to be disabled before updating the registers we set
-		 * here.
-		 */
-		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
-
-		/*
-		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
-		 * Also enable the transmit and receive FIFO.
-		 *
-		 * FIXME: Little-endian samples require a different shift dir
-		 */
-		write_ssi_mask(&ssi->scr,
-			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
-			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
-			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
-
-		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
-			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
-
-		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
-			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
-
-		/*
-		 * The DC and PM bits are only used if the SSI is the clock
-		 * master.
-		 */
-
-		/* Enable the interrupts and DMA requests */
-		if (ssi_private->use_dma)
-			write_ssi(SIER_FLAGS, &ssi->sier);
-		else
-			write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
-					CCSR_SSI_SIER_RIE |
-					CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
-
-		/*
-		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
-		 * don't use FIFO 1.  We program the transmit water to signal a
-		 * DMA transfer if there are only two (or fewer) elements left
-		 * in the FIFO.  Two elements equals one frame (left channel,
-		 * right channel).  This value, however, depends on the depth of
-		 * the transmit buffer.
-		 *
-		 * We program the receive FIFO to notify us if at least two
-		 * elements (one frame) have been written to the FIFO.  We could
-		 * make this value larger (and maybe we should), but this way
-		 * data will be written to memory as soon as it's available.
-		 */
-		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
-			&ssi->sfcsr);
-
-		/*
-		 * We keep the SSI disabled because if we enable it, then the
-		 * DMA controller will start.  It's not supposed to start until
-		 * the SCR.TE (or SCR.RE) bit is set, but it does anyway.  The
-		 * DMA controller will transfer one "BWC" of data (i.e. the
-		 * amount of data that the MR.BWC bits are set to).  The reason
-		 * this is bad is because at this point, the PCM driver has not
-		 * finished initializing the DMA controller.
+		 * fsl_ssi_setup was already called by ac97_init earlier if
+		 * the driver is in ac97 mode.
 		 */
+		if (!ssi_private->imx_ac97)
+			fsl_ssi_setup(ssi_private);
 	} else {
 		if (synchronous) {
 			struct snd_pcm_runtime *first_runtime =
@@ -564,8 +622,9 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 
 	/*
 	 * If this is the last active substream, disable the SSI.
+	 * If AC97 is active, we don't want to disable SSI.
 	 */
-	if (!ssi_private->first_stream) {
+	if (!ssi_private->first_stream && !ssi_private->imx_ac97) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
 		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
@@ -614,6 +673,129 @@ static const struct snd_soc_component_driver fsl_ssi_component = {
 	.name		= "fsl-ssi",
 };
 
+/**
+ * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
+ *
+ * This function is called by ALSA to start, stop, pause, and resume the
+ * transfer of data.
+ */
+static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
+			   struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
+					CCSR_SSI_SIER_TFE0_EN);
+		else
+			write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
+					CCSR_SSI_SIER_TFE0_EN, 0);
+		else
+			write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN, 0);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
+	else
+		write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
+	.startup	= fsl_ssi_startup,
+	.shutdown	= fsl_ssi_shutdown,
+	.trigger	= fsl_ssi_ac97_trigger,
+};
+
+static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
+	.ac97_control = 1,
+	.playback = {
+		.stream_name = "AC97 Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_8000_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	},
+	.capture = {
+		.stream_name = "AC97 Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	},
+	.ops = &fsl_ssi_ac97_dai_ops,
+};
+
+
+static struct fsl_ssi_private *fsl_ac97_data;
+
+static void fsl_ssi_ac97_init(void)
+{
+	fsl_ssi_setup(fsl_ac97_data);
+}
+
+void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+		unsigned short val)
+{
+	struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
+	unsigned int lreg;
+	unsigned int lval;
+
+	if (reg > 0x7f)
+		return;
+
+
+	lreg = reg <<  12;
+	write_ssi(lreg, &ssi->sacadd);
+
+	lval = val << 4;
+	write_ssi(lval , &ssi->sacdat);
+
+	write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
+			CCSR_SSI_SACNT_WR);
+	udelay(100);
+}
+EXPORT_SYMBOL(fsl_ssi_ac97_write);
+
+unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
+		unsigned short reg)
+{
+	struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
+
+	unsigned short val = -1;
+	unsigned int lreg;
+
+	lreg = (reg & 0x7f) <<  12 ;
+	write_ssi(lreg, &ssi->sacadd);
+	write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
+			CCSR_SSI_SACNT_RD);
+
+	udelay(100);
+
+	val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
+
+	return val;
+}
+EXPORT_SYMBOL(fsl_ssi_ac97_read);
+
 /*
  * FIXME: As soon as all boards using imx-ssi AC97 mode are able to use
  * fsl-ssi, soc_ac97_ops can be used exclusively in this driver without copying
@@ -622,6 +804,23 @@ static const struct snd_soc_component_driver fsl_ssi_component = {
 struct snd_ac97_bus_ops soc_ac97_ops;
 EXPORT_SYMBOL_GPL(soc_ac97_ops);
 
+static struct snd_ac97_bus_ops fsl_ssi_soc_ac97_ops = {
+	.read		= fsl_ssi_ac97_read,
+	.write		= fsl_ssi_ac97_write,
+};
+
+/*
+ * ac97 reset and warm_reset functions are setup by board specific drivers.
+ * ssi does not have any knowledge about the used board.
+ */
+void fsl_ssi_ac97_set_reset(void (*ac97_reset)(struct snd_ac97 *ac97),
+		void (*ac97_warm_reset)(struct snd_ac97 *ac97))
+{
+	soc_ac97_ops.reset = ac97_reset;
+	soc_ac97_ops.warm_reset = ac97_warm_reset;
+}
+EXPORT_SYMBOL(fsl_ssi_ac97_set_reset);
+
 /* Show the statistics of a flag only if its interrupt is enabled.  The
  * compiler will optimze this code to a no-op if the interrupt is not
  * enabled.
@@ -698,6 +897,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	struct resource res;
 	char name[64];
 	bool shared;
+	bool ac97 = false;
 
 	/* SSIs that are not connected on the board should have a
 	 *      status = "disabled"
@@ -708,7 +908,13 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
-	if (!sprop || strcmp(sprop, "i2s-slave")) {
+	if (!sprop) {
+		dev_err(&pdev->dev, "fsl,mode property is necessary\n");
+		return -EINVAL;
+	}
+	if (!strcmp(sprop, "ac97-slave")) {
+		ac97 = true;
+	} else if (strcmp(sprop, "i2s-slave")) {
 		dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
 		return -ENODEV;
 	}
@@ -724,13 +930,23 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 
 	strcpy(ssi_private->name, p);
 
-	/* Initialize this copy of the CPU DAI driver structure */
-	memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
-	       sizeof(fsl_ssi_dai_template));
-	ssi_private->cpu_dai_drv.name = ssi_private->name;
-
 	ssi_private->use_dma = !of_property_read_bool(np, "fsl,imx-fiq");
 
+	if (ac97) {
+		memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
+				sizeof(fsl_ssi_ac97_dai));
+		memcpy(&soc_ac97_ops, &fsl_ssi_soc_ac97_ops,
+				sizeof(soc_ac97_ops));
+
+		fsl_ac97_data = ssi_private;
+		ssi_private->imx_ac97 = true;
+	} else {
+		/* Initialize this copy of the CPU DAI driver structure */
+		memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
+		       sizeof(fsl_ssi_dai_template));
+	}
+	ssi_private->cpu_dai_drv.name = ssi_private->name;
+
 	/* Get the addresses and IRQ */
 	ret = of_address_to_resource(np, 0, &res);
 	if (ret) {
@@ -910,6 +1126,9 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 done:
+	if (ssi_private->imx_ac97)
+		fsl_ssi_ac97_init();
+
 	return 0;
 
 error_dai:
diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h
index e6b9a69..87004ae 100644
--- a/sound/soc/fsl/fsl_ssi.h
+++ b/sound/soc/fsl/fsl_ssi.h
@@ -206,3 +206,10 @@ struct ccsr_ssi {
 
 #endif
 
+
+void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+		unsigned short val);
+unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
+		unsigned short reg);
+void fsl_ssi_ac97_set_reset(void (*ac97_reset)(struct snd_ac97 *ac97),
+		void (*ac97_warm_reset)(struct snd_ac97 *ac97));
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:47 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:47 +0200
Subject: [PATCH v7 05/11] ASoC: fsl-ssi: Use generic DMA bindings if possible
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-6-git-send-email-mpa@pengutronix.de>

There may be some platforms using fsl-ssi that do not have a DMA driver
with generic DMA bindings. So this patch adds support for the generic
DMA bindings, while still accepting the old "fsl,dma-events" property if
"dmas" is not found.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v5:
     - Not passing of_node now, instead setting the parent device
    
    Changes in v4:
     - Change TODO comment to a FIXME, to remove the old dma-events property as soon
       as all dma drivers support the generic DMA bindings.

 sound/soc/fsl/fsl_ssi.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2fe4dbd..ed1fbbb 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -803,15 +803,19 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 			&ssi_private->filter_data_tx;
 		ssi_private->dma_params_rx.filter_data =
 			&ssi_private->filter_data_rx;
-		/*
-		 * TODO: This is a temporary solution and should be changed
-		 * to use generic DMA binding later when the helplers get in.
-		 */
-		ret = of_property_read_u32_array(pdev->dev.of_node,
+		if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
+				ssi_private->use_dma) {
+			/*
+			 * FIXME: This is a temporary solution until all
+			 * necessary dma drivers support the generic dma
+			 * bindings.
+			 */
+			ret = of_property_read_u32_array(pdev->dev.of_node,
 					"fsl,ssi-dma-events", dma_events, 2);
-		if (ret && !ssi_private->use_dma) {
-			dev_err(&pdev->dev, "could not get dma events\n");
-			goto error_clk;
+			if (ret && ssi_private->use_dma) {
+				dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
+				goto error_clk;
+			}
 		}
 
 		shared = of_device_is_compatible(of_get_parent(np),
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:53 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:53 +0200
Subject: [PATCH v7 11/11] ASoC: fsl: Update fsl-ssi binding doc
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-12-git-send-email-mpa@pengutronix.de>

Update the fsl-ssi bindings. DMA is no required property anymore and
uses the generic DMA bindings. imx-fiq is a new alternative to DMA

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v4:
     - Add a comment about hardware bugs for imx-pcm-fiq
    
    Changes in v3:
     - In previous versions, I removed fsl,playback-dma and capture-dma. But they
       are still in use by fsl_dma.c, so I added them again.

 Documentation/devicetree/bindings/sound/fsl,ssi.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
index 5ff76c9..0375ee0 100644
--- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
@@ -43,10 +43,20 @@ Required properties:
                     together.  This would still allow different sample sizes,
                     but not different sample rates.
 
+Note that either dmas, dma-names or fsl,imx-fiq are required.
+
 Optional properties:
 - codec-handle:     Phandle to a 'codec' node that defines an audio
                     codec connected to this SSI.  This node is typically
                     a child of an I2C or other control node.
+- dmas:		    Generic dma devicetree binding as described in
+		    Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names:	    Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
+		    is not defined.
+- fsl,imx-fiq:	    Bool property. Use imx-pcm-fiq instead of imx-pcm-dma.
+  		    Only necessary for some boards with incompatible
+		    codec. imx-pcm-fiq will manually filter some data from
+		    the codec. It is a workaround for a hardware bug.
 
 Child 'codec' node required properties:
 - compatible:       Compatible list, contains the name of the codec
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:45 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:45 +0200
Subject: [PATCH v7 03/11] ASoC: fsl: Move soc_ac97_ops from imx-ssi to fsl_ssi
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-4-git-send-email-mpa@pengutronix.de>

fsl_ssi and imx-ssi can be both enabled at the same time. To be able to
add AC97 support to fsl_ssi, soc_ac97_ops have to be available to both
drivers.

fsl_ssi has DT support and should be the only driver at some point in
the future. This patch moves the definition of soc_ac97_ops to fsl_ssi.
imx-ssi copies its own ac97 ops struct into soc_ac97_ops when used in
AC97 mode.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 sound/soc/fsl/Kconfig   | 1 +
 sound/soc/fsl/fsl_ssi.c | 8 ++++++++
 sound/soc/fsl/imx-ssi.c | 7 +++++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 7860cc2..74ef96e 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -107,6 +107,7 @@ if SND_IMX_SOC
 
 config SND_SOC_IMX_SSI
 	tristate
+	select SND_SOC_FSL_SSI
 
 config SND_SOC_IMX_PCM_FIQ
 	bool
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2f2d837..db55499 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -587,6 +587,14 @@ static const struct snd_soc_component_driver fsl_ssi_component = {
 	.name		= "fsl-ssi",
 };
 
+/*
+ * FIXME: As soon as all boards using imx-ssi AC97 mode are able to use
+ * fsl-ssi, soc_ac97_ops can be used exclusively in this driver without copying
+ * the struct. AC97 support can then be removed from imx-ssi.
+ */
+struct snd_ac97_bus_ops soc_ac97_ops;
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
 /* Show the statistics of a flag only if its interrupt is enabled.  The
  * compiler will optimze this code to a no-op if the interrupt is not
  * enabled.
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index 16ae16d..3760220 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -501,13 +501,14 @@ static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
 	imx_ssi_ac97_read(ac97, 0);
 }
 
-struct snd_ac97_bus_ops soc_ac97_ops = {
+static struct snd_ac97_bus_ops imx_ssi_soc_ac97_ops = {
 	.read		= imx_ssi_ac97_read,
 	.write		= imx_ssi_ac97_write,
 	.reset		= imx_ssi_ac97_reset,
 	.warm_reset	= imx_ssi_ac97_warm_reset
 };
-EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+extern struct snd_ac97_bus_ops soc_ac97_ops;
 
 static int imx_ssi_probe(struct platform_device *pdev)
 {
@@ -547,6 +548,8 @@ static int imx_ssi_probe(struct platform_device *pdev)
 	}
 
 	if (ssi->flags & IMX_SSI_USE_AC97) {
+		memcpy(&soc_ac97_ops, &imx_ssi_soc_ac97_ops,
+				sizeof(soc_ac97_ops));
 		if (ac97_ssi) {
 			dev_err(&pdev->dev, "AC'97 SSI already registered\n");
 			ret = -EBUSY;
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:46 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:46 +0200
Subject: [PATCH v7 04/11] ASoC: fsl-ssi: Add support for imx-pcm-fiq
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-5-git-send-email-mpa@pengutronix.de>

Add support for non-dma pcm for imx platforms with imx-pcm-fiq support.
Instead of imx-pcm-audio, in this case imx-pcm-fiq-audio device is added
and the SIER flags are set differently.

We need imx-pcm-fiq for some boards that use an incompatible codec.
imx-pcm-fiq handles those codecs differently and allows to operate with
them. DMA is not possible because some data sent by the codecs, e.g.
wm9712, is not in the datastream. Also some data is mixed up in the
fifos, so that we need to sort them out manually.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v4:
     - Add a comment about the reason why we add a imx-pcm-fiq device.
     - Change commit message to include information about the usage of imx-pcm-fiq
    
    Changes in v3:
     - Rename bool "dma" to "use_dma"

 sound/soc/fsl/fsl_ssi.c | 77 +++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 65 insertions(+), 12 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index db55499..2fe4dbd 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -8,6 +8,26 @@
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
+ *
+ *
+ * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
+ *
+ * The i.MX SSI core has some nasty limitations in AC97 mode. While most
+ * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
+ * one FIFO which combines all valid receive slots. We cannot even select
+ * which slots we want to receive. The WM9712 with which this driver
+ * was developed with always sends GPIO status data in slot 12 which
+ * we receive in our (PCM-) data stream. The only chance we have is to
+ * manually skip this data in the FIQ handler. With sampling rates different
+ * from 48000Hz not every frame has valid receive data, so the ratio
+ * between pcm data and GPIO status data changes. Our FIQ handler is not
+ * able to handle this, hence this driver only works with 48000Hz sampling
+ * rate.
+ * Reading and writing AC97 registers is another challenge. The core
+ * provides us status bits when the read register is updated with *another*
+ * value. When we read the same register two times (and the register still
+ * contains the same value) these status bits are not set. We work
+ * around this by not polling these bits but only wait a fixed delay.
  */
 
 #include <linux/init.h>
@@ -121,11 +141,13 @@ struct fsl_ssi_private {
 
 	bool new_binding;
 	bool ssi_on_imx;
+	bool use_dma;
 	struct clk *clk;
 	struct snd_dmaengine_dai_dma_data dma_params_tx;
 	struct snd_dmaengine_dai_dma_data dma_params_rx;
 	struct imx_dma_data filter_data_tx;
 	struct imx_dma_data filter_data_rx;
+	struct imx_pcm_fiq_params fiq_params;
 
 	struct {
 		unsigned int rfrc;
@@ -355,7 +377,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		write_ssi(SIER_FLAGS, &ssi->sier);
+		if (ssi_private->use_dma)
+			write_ssi(SIER_FLAGS, &ssi->sier);
+		else
+			write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
+					CCSR_SSI_SIER_RIE |
+					CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -549,7 +576,7 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
 {
 	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
 
-	if (ssi_private->ssi_on_imx) {
+	if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
 		dai->playback_dma_data = &ssi_private->dma_params_tx;
 		dai->capture_dma_data = &ssi_private->dma_params_rx;
 	}
@@ -702,6 +729,8 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	       sizeof(fsl_ssi_dai_template));
 	ssi_private->cpu_dai_drv.name = ssi_private->name;
 
+	ssi_private->use_dma = !of_property_read_bool(np, "fsl,imx-fiq");
+
 	/* Get the addresses and IRQ */
 	ret = of_address_to_resource(np, 0, &res);
 	if (ret) {
@@ -723,12 +752,15 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 		goto error_iomap;
 	}
 
-	/* The 'name' should not have any slashes in it. */
-	ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
-			  ssi_private);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
-		goto error_irqmap;
+	if (ssi_private->use_dma) {
+		/* The 'name' should not have any slashes in it. */
+		ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0,
+				ssi_private->name, ssi_private);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "could not claim irq %u\n",
+					ssi_private->irq);
+			goto error_irqmap;
+		}
 	}
 
 	/* Are the RX and the TX clocks locked? */
@@ -777,7 +809,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 		 */
 		ret = of_property_read_u32_array(pdev->dev.of_node,
 					"fsl,ssi-dma-events", dma_events, 2);
-		if (ret) {
+		if (ret && !ssi_private->use_dma) {
 			dev_err(&pdev->dev, "could not get dma events\n");
 			goto error_clk;
 		}
@@ -816,9 +848,30 @@ static int fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 	if (ssi_private->ssi_on_imx) {
-		ret = imx_pcm_dma_init(pdev);
-		if (ret)
-			goto error_dev;
+		if (!ssi_private->use_dma) {
+
+			/*
+			 * Some boards use an incompatible codec. To get it
+			 * working, we are using imx-fiq-pcm-audio, that
+			 * can handle those codecs. DMA is not possible in this
+			 * situation.
+			 */
+
+			ssi_private->fiq_params.irq = ssi_private->irq;
+			ssi_private->fiq_params.base = ssi_private->ssi;
+			ssi_private->fiq_params.dma_params_rx =
+				&ssi_private->dma_params_rx;
+			ssi_private->fiq_params.dma_params_tx =
+				&ssi_private->dma_params_tx;
+
+			ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
+			if (ret)
+				goto error_dev;
+		} else {
+			ret = imx_pcm_dma_init(pdev);
+			if (ret)
+				goto error_dev;
+		}
 	}
 
 	/*
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:43 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:43 +0200
Subject: [PATCH v7 01/11] ASoC: imx-pcm-dma: DT support
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-2-git-send-email-mpa@pengutronix.de>

This patch removes the NO_DT flag. The pdev pointer may have a proper
of_node with the dmas property, so we can use it to request DMA
channels.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v6:
     - After rebasing onto Shawn's imx-pcm cleanups, this patch just consists of
       removing the NO_DT flag.
    
    Changes in v5:
     - Use dev.parent pointer to get the of_node.

 sound/soc/fsl/imx-pcm-dma.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sound/soc/fsl/imx-pcm-dma.c b/sound/soc/fsl/imx-pcm-dma.c
index fde4d2e..f323ce0 100644
--- a/sound/soc/fsl/imx-pcm-dma.c
+++ b/sound/soc/fsl/imx-pcm-dma.c
@@ -64,7 +64,6 @@ int imx_pcm_dma_init(struct platform_device *pdev)
 {
 	return snd_dmaengine_pcm_register(&pdev->dev, &imx_dmaengine_pcm_config,
 		SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
-		SND_DMAENGINE_PCM_FLAG_NO_DT |
 		SND_DMAENGINE_PCM_FLAG_COMPAT);
 }
 EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:49 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:49 +0200
Subject: [PATCH v7 07/11] ARM: imx: Export ac97 reset functions
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-8-git-send-email-mpa@pengutronix.de>

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 arch/arm/mach-imx/mach-pca100.c | 7 +++++--
 arch/arm/mach-imx/mach-pcm043.c | 7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb..68badf8 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -22,6 +22,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/dma-mapping.h>
+#include <linux/export.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
 #include <linux/irq.h>
@@ -208,7 +209,7 @@ static const struct spi_imx_master pca100_spi0_data __initconst = {
 	.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
 
-static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
+void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
 {
 	mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
 	gpio_set_value(GPIO_PORTC + 20, 1);
@@ -217,8 +218,9 @@ static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
 	mxc_gpio_mode(PC20_PF_SSI1_FS);
 	msleep(2);
 }
+EXPORT_SYMBOL(pca100_ac97_warm_reset);
 
-static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
+void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
 {
 	mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);  /* FS */
 	gpio_set_value(GPIO_PORTC + 20, 0);
@@ -232,6 +234,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
 	mxc_gpio_mode(PC22_PF_SSI1_TXD);
 	msleep(2);
 }
+EXPORT_SYMBOL(pca100_ac97_cold_reset);
 
 static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
 	.ac97_reset		= pca100_ac97_cold_reset,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 8ed533f..4f318ca 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -27,6 +27,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
+#include <linux/export.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -217,7 +218,7 @@ static iomux_v3_cfg_t pcm043_pads[] = {
 #define SD1_GPIO_WP	IMX_GPIO_NR(2, 23)
 #define SD1_GPIO_CD	IMX_GPIO_NR(2, 24)
 
-static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
+void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 {
 	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
@@ -239,8 +240,9 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 	gpio_free(AC97_GPIO_TXFS);
 	mxc_iomux_v3_setup_pad(txfs);
 }
+EXPORT_SYMBOL(pcm043_ac97_warm_reset);
 
-static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
+void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
 {
 	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
@@ -286,6 +288,7 @@ err1:
 		printk("%s failed with %d\n", __func__, ret);
 	mdelay(1);
 }
+EXPORT_SYMBOL(pcm043_ac97_cold_reset);
 
 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
 	.ac97_reset = pcm043_ac97_cold_reset,
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:42 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:42 +0200
Subject: [PATCH v7 00/11] ASoC: fsl-ssi: ac97-slave support
Message-ID: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>

Hi,

This series adds DT support for phycore-ac97. Beside ac97 support, the series
adds imx-pcm-fiq and generic DMA bindings to fsl-ssi.

Regards,

Markus

Changes in v7:
 - Only one soc_ac97_ops struct for both ssi drivers (fsl-ssi and imx-ssi) to
   make it possible to compile a kernel with both drivers.
 - Other small bug/style fixes described in the changelogs of the patches.

Changes in v6:
 - Rebased onto 3.10-rc3 with Shawn's pcm cleanup patches
 - Setup of reset functions moved to phycore-ac97.c

Changes in v5:
 - Pass of_node via parent device to imx-pcm-dma.

Changes in v4:
 - phycore-ac97 uses the iomux functions based on audmux phandle now.
 - fsl-ssi imx-pcm-fiq got some new comments about problems with imx-ssi and
   incompatible codecs

Changes in v3:
 - Rebased onto pcm dma cleanup patches
 - A lot of cleanups for the fsl-ssi ac97 integration
 - Some small changes which are listed in the notes of the patches.

Markus Pargmann (11):
      ASoC: imx-pcm-dma: DT support
      ASoC: imx-pcm-fiq: Introduce pcm-fiq-params
      ASoC: fsl: Move soc_ac97_ops from imx-ssi to fsl_ssi
      ASoC: fsl-ssi: Add support for imx-pcm-fiq
      ASoC: fsl-ssi: Use generic DMA bindings if possible
      ASoC: fsl-ssi: imx ac97 support
      ARM: imx: Export ac97 reset functions
      ASoC: phycore-ac97: Add DT support
      ASoC: fsl: Kconfig: Use fsl-ssi for phycore-ac97
      ASoC: fsl: Move fsl-ssi binding doc to sound/
      ASoC: fsl: Update fsl-ssi binding doc

 .../{powerpc/fsl/ssi.txt => sound/fsl,ssi.txt}     |  10 +
 .../bindings/sound/phytec,phycore-ac97.txt         |  14 +
 arch/arm/mach-imx/mach-pca100.c                    |   7 +-
 arch/arm/mach-imx/mach-pcm043.c                    |   7 +-
 sound/soc/fsl/Kconfig                              |   4 +-
 sound/soc/fsl/fsl_ssi.c                            | 450 +++++++++++++++++----
 sound/soc/fsl/fsl_ssi.h                            |   7 +
 sound/soc/fsl/imx-pcm-dma.c                        |   1 -
 sound/soc/fsl/imx-pcm-fiq.c                        |  18 +-
 sound/soc/fsl/imx-pcm.h                            |  15 +-
 sound/soc/fsl/imx-ssi.c                            |  14 +-
 sound/soc/fsl/imx-ssi.h                            |   1 +
 sound/soc/fsl/phycore-ac97.c                       | 236 +++++++++--
 13 files changed, 656 insertions(+), 128 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc/fsl/ssi.txt => sound/fsl,ssi.txt} (88%)
 create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt



From mpa at pengutronix.de  Thu May 30 10:51:51 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:51 +0200
Subject: [PATCH v7 09/11] ASoC: fsl: Kconfig: Use fsl-ssi for phycore-ac97
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-10-git-send-email-mpa@pengutronix.de>

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---
 sound/soc/fsl/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 74ef96e..71284c0 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -149,7 +149,8 @@ config SND_SOC_PHYCORE_AC97
 	select SND_SOC_WM9712
 	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
+	select SND_SOC_FSL_SSI if MACH_PCA100
+	select SND_SOC_IMX_SSI if MACH_PCM043
 	help
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
-- 
1.8.2.1



From mpa at pengutronix.de  Thu May 30 10:51:44 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 16:51:44 +0200
Subject: [PATCH v7 02/11] ASoC: imx-pcm-fiq: Introduce pcm-fiq-params
In-Reply-To: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
Message-ID: <1369925513-19329-3-git-send-email-mpa@pengutronix.de>

Cleaner parameter passing for imx-pcm-fiq. Create a seperated fiq-params
struct to pass all arguments.

Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
---

Notes:
    Changes in v7:
     - Fix init function signature for !CONFIG_SND_SOC_IMX_PCM_FIQ
    
    Changes in v6:
     - After rebasing onto Shawn's imx-pcm cleanups, the imx_pcm_fiq_params are now
       passed as function arguments instead of platform driver data.
    
    Changes in v3:
     - Using snd_dmaengine_dai_dma_data for dma_params after rebasing onto
       dmaengine cleanups.

 sound/soc/fsl/imx-pcm-fiq.c | 18 ++++++++++--------
 sound/soc/fsl/imx-pcm.h     | 15 +++++++++++++--
 sound/soc/fsl/imx-ssi.c     |  7 ++++++-
 sound/soc/fsl/imx-ssi.h     |  1 +
 4 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
index 310d902..3b2ba99 100644
--- a/sound/soc/fsl/imx-pcm-fiq.c
+++ b/sound/soc/fsl/imx-pcm-fiq.c
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 
 #include <sound/core.h>
+#include <sound/dmaengine_pcm.h>
 #include <sound/initval.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -32,6 +33,7 @@
 #include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "imx-ssi.h"
+#include "imx-pcm.h"
 
 struct imx_pcm_runtime_data {
 	unsigned int period;
@@ -366,9 +368,9 @@ static struct snd_soc_platform_driver imx_soc_platform_fiq = {
 	.pcm_free	= imx_pcm_fiq_free,
 };
 
-int imx_pcm_fiq_init(struct platform_device *pdev)
+int imx_pcm_fiq_init(struct platform_device *pdev,
+		struct imx_pcm_fiq_params *params)
 {
-	struct imx_ssi *ssi = platform_get_drvdata(pdev);
 	int ret;
 
 	ret = claim_fiq(&fh);
@@ -377,15 +379,15 @@ int imx_pcm_fiq_init(struct platform_device *pdev)
 		return ret;
 	}
 
-	mxc_set_irq_fiq(ssi->irq, 1);
-	ssi_irq = ssi->irq;
+	mxc_set_irq_fiq(params->irq, 1);
+	ssi_irq = params->irq;
 
-	imx_pcm_fiq = ssi->irq;
+	imx_pcm_fiq = params->irq;
 
-	imx_ssi_fiq_base = (unsigned long)ssi->base;
+	imx_ssi_fiq_base = (unsigned long)params->base;
 
-	ssi->dma_params_tx.maxburst = 4;
-	ssi->dma_params_rx.maxburst = 6;
+	params->dma_params_tx->maxburst = 4;
+	params->dma_params_rx->maxburst = 6;
 
 	ret = snd_soc_register_platform(&pdev->dev, &imx_soc_platform_fiq);
 	if (ret)
diff --git a/sound/soc/fsl/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
index 67f656c..cd8a796 100644
--- a/sound/soc/fsl/imx-pcm.h
+++ b/sound/soc/fsl/imx-pcm.h
@@ -32,6 +32,15 @@ imx_pcm_dma_params_init_data(struct imx_dma_data *dma_data,
 		dma_data->peripheral_type = IMX_DMATYPE_SSI;
 }
 
+struct imx_pcm_fiq_params {
+	int irq;
+	void __iomem *base;
+
+	/* Pointer to original ssi driver to setup tx rx sizes */
+	struct snd_dmaengine_dai_dma_data *dma_params_rx;
+	struct snd_dmaengine_dai_dma_data *dma_params_tx;
+};
+
 #ifdef CONFIG_SND_SOC_IMX_PCM_DMA
 int imx_pcm_dma_init(struct platform_device *pdev);
 void imx_pcm_dma_exit(struct platform_device *pdev);
@@ -47,10 +56,12 @@ static inline void imx_pcm_dma_exit(struct platform_device *pdev)
 #endif
 
 #ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
-int imx_pcm_fiq_init(struct platform_device *pdev);
+int imx_pcm_fiq_init(struct platform_device *pdev,
+		struct imx_pcm_fiq_params *params);
 void imx_pcm_fiq_exit(struct platform_device *pdev);
 #else
-static inline int imx_pcm_fiq_init(struct platform_device *pdev)
+static inline int imx_pcm_fiq_init(struct platform_device *pdev,
+		struct imx_pcm_fiq_params *params);
 {
 	return -ENODEV;
 }
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index a8362be..16ae16d 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -590,7 +590,12 @@ static int imx_ssi_probe(struct platform_device *pdev)
 		goto failed_register;
 	}
 
-	ret = imx_pcm_fiq_init(pdev);
+	ssi->fiq_params.irq = ssi->irq;
+	ssi->fiq_params.base = ssi->base;
+	ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
+	ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
+
+	ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
 	if (ret)
 		goto failed_pcm_fiq;
 
diff --git a/sound/soc/fsl/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
index d5003ce..fb1616b 100644
--- a/sound/soc/fsl/imx-ssi.h
+++ b/sound/soc/fsl/imx-ssi.h
@@ -209,6 +209,7 @@ struct imx_ssi {
 	struct snd_dmaengine_dai_dma_data dma_params_tx;
 	struct imx_dma_data filter_data_tx;
 	struct imx_dma_data filter_data_rx;
+	struct imx_pcm_fiq_params fiq_params;
 
 	int enabled;
 };
-- 
1.8.2.1



From lee.jones at linaro.org  Thu May 30 10:53:23 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 30 May 2013 15:53:23 +0100
Subject: [PATCH 0/5] Various DT fixes related to ux500 ASoC driver
In-Reply-To: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
References: <1369920465-13905-1-git-send-email-fabio.baltieri@linaro.org>
Message-ID: <20130530145323.GB1915@gmail.com>

On Thu, 30 May 2013, Fabio Baltieri wrote:

> Hi Linus, Lee,
> 
> these are various fixes I found while testing the ux500 ASoC driver on HREF
> with device-tree.
> 
> First two patches are typos in DT files, while the others are
> specifically to support ux500 ASoC driver with DT enabled.
> 
> The last patch can go in the mfd tree, while the others may safely go
> through arm-soc, as there are no build dependencies or regression issues
> in general.
> 
> Thanks,
> Fabio
> 
> 
> Fabio Baltieri (5):
>   ARM: ux500: Fix trivial typo in v-anamic1 comment
>   ARM: ux500: Correct anamic2 typo in DT files
>   ARM: ux500: Add DT regulators for ab8500-codec
>   ARM: ux500: Provide auxdata to ux500 ASoC driver
>   mfd: ab8500-core: Add of_compatible property for ab8500-codec
> 
>  arch/arm/boot/dts/dbx5x0.dtsi     | 11 ++++++++---
>  arch/arm/boot/dts/href.dtsi       |  2 +-
>  arch/arm/boot/dts/hrefv60plus.dts |  2 +-
>  arch/arm/boot/dts/snowball.dts    |  2 +-
>  arch/arm/mach-ux500/cpu-db8500.c  |  2 ++
>  drivers/mfd/ab8500-core.c         |  1 +
>  drivers/regulator/ab8500.c        |  8 ++++----
>  7 files changed, 18 insertions(+), 10 deletions(-)

All look good to me.

For patches 1-4:

Acked-by: Lee Jones <lee.jones at linaro.org>

For patch 5:

Applied thanks.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From shawn.guo at linaro.org  Thu May 30 10:57:25 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 30 May 2013 22:57:25 +0800
Subject: [PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as
 cacheable, increase IPU priority
In-Reply-To: <1369919399-24370-2-git-send-email-mpa@pengutronix.de>
References: <1369919399-24370-1-git-send-email-mpa@pengutronix.de>
 <1369919399-24370-2-git-send-email-mpa@pengutronix.de>
Message-ID: <20130530145703.GB22013@S2101-09.ap.freescale.net>

On Thu, May 30, 2013 at 03:09:59PM +0200, Markus Pargmann wrote:
> From: Philipp Zabel <p.zabel at pengutronix.de>
> 
> This is needed so that the IPU framebuffer scanout cannot be starved
> by VPU or GPU activity.
> The Freescale SabreLite and SabreSD boards seem to set this in the boot
> rom already,

The boot rom is not board specific but SoC, so you meant boot loader?

> but the documented register reset values do not contain
> the necessary settings.
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> ---
>  arch/arm/mach-imx/mach-imx6q.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 5536fd8..7bef242 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -29,6 +29,7 @@
>  #include <linux/regmap.h>
>  #include <linux/micrel_phy.h>
>  #include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
>  #include <asm/hardware/cache-l2x0.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> @@ -161,6 +162,36 @@ static void __init imx6q_usb_init(void)
>  	imx_anatop_usb_chrg_detect_disable();
>  }
>  
> +static void __init imx6q_gpr_init(void)
> +{
> +	struct regmap *gpr;
> +
> +	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (IS_ERR(gpr)) {
> +		pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
> +		return;
> +	}
> +
> +	/* Enable the cacheable attribute of VPU and IPU AXI transactions */
> +	regmap_update_bits(gpr, IOMUXC_GPR4, 0,
> +			IMX6Q_GPR4_VPU_WR_CACHE_SEL |
> +			IMX6Q_GPR4_VPU_RD_CACHE_SEL |
> +			IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
> +			IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
> +			IMX6Q_GPR4_IPU_WR_CACHE_CTL |
> +			IMX6Q_GPR4_IPU_RD_CACHE_CTL);
> +
> +	/* Increase IPU read QoS priority */
> +	regmap_update_bits(gpr, IOMUXC_GPR6,
> +			IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
> +			IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
> +			(0xf << 16) | (0x7 << 20));
> +	regmap_update_bits(gpr, IOMUXC_GPR7,
> +			IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
> +			IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
> +			(0xf << 16) | (0x7 << 20));
> +}
> +
>  static void __init imx6q_init_machine(void)
>  {
>  	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
> @@ -172,6 +203,7 @@ static void __init imx6q_init_machine(void)
>  	imx6q_pm_init();
>  	imx6q_usb_init();
>  	imx6q_1588_init();
> +	imx6q_gpr_init();

The function imx6q_1588_init() is all about setting up some IOMUXC GPR
bits, so can you consolidate it into imx6q_gpr_init()?

Shawn

>  }
>  
>  #define OCOTP_CFG3			0x440
> -- 
> 1.8.2.1
> 



From will.deacon at arm.com  Thu May 30 11:03:07 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 30 May 2013 16:03:07 +0100
Subject: [PATCH 00/14] Random LPAE-related patches
In-Reply-To: <51A7549D.9000103@gmail.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <51A7549D.9000103@gmail.com>
Message-ID: <20130530150307.GU7483@mudshark.cambridge.arm.com>

On Thu, May 30, 2013 at 02:31:09PM +0100, Subash Patel wrote:
> Thanks for these patches. I have tested these patches on exynos5440 
> platform. It hasnt affected LPAE functionality for us from previous 
> versions(posted by Cyril). You can use "Tested-By: Subash Patel 
> <subash.rp at samsung.com>" as you deem necessary.

Thanks Subash. I'll add your tag and send a pull to Russell when he's back
from holiday.

Will


From mpa at pengutronix.de  Thu May 30 11:03:36 2013
From: mpa at pengutronix.de (Markus Pargmann)
Date: Thu, 30 May 2013 17:03:36 +0200
Subject: [PATCH] ARM: imx: Remove mxc specific ulpi access ops
In-Reply-To: <20130530144601.GA22013@S2101-09.ap.freescale.net>
References: <1369917895-9562-1-git-send-email-mpa@pengutronix.de>
 <20130530144601.GA22013@S2101-09.ap.freescale.net>
Message-ID: <20130530150336.GF31548@pengutronix.de>

On Thu, May 30, 2013 at 10:46:04PM +0800, Shawn Guo wrote:
> On Thu, May 30, 2013 at 02:44:55PM +0200, Markus Pargmann wrote:
> > There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c.
> > mxc access ops implement the same access operations within mach-imx. This
> > patch removes the mxc ulpi file and uses phy-ulpi instead for
> > imx_otg_ulpi_create.
> > 
> > phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100).
> > 
> > Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> > Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  arch/arm/mach-imx/Kconfig       |   1 +
> >  arch/arm/mach-imx/Makefile      |   1 -
> >  arch/arm/mach-imx/mach-pca100.c |   4 +-
> >  arch/arm/mach-imx/ulpi.c        | 118 ----------------------------------------
> >  arch/arm/mach-imx/ulpi.h        |   9 ++-
> >  5 files changed, 9 insertions(+), 124 deletions(-)
> >  delete mode 100644 arch/arm/mach-imx/ulpi.c
> > 
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index ba44328..ca59799 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -58,6 +58,7 @@ config MXC_USE_EPIT
> >  
> >  config MXC_ULPI
> >  	bool
> > +	select USB_ULPI_VIEWPORT
> 
> Is MXC_ULPI still used anywhere after you remove ulpi.c in the patch?
> You are even patching it, so I'm a little confused.

No it is not used anywhere else. I removed it and replaced all
occurences with USB_ULPI_VIEWPORT.

Thanks,

Markus

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From plagnioj at jcrosoft.com  Thu May 30 10:59:38 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 May 2013 16:59:38 +0200
Subject: [PATCH 1/8] video: atmel_lcdfb: fix platform data struct
In-Reply-To: <51A761DA.6020109@corscience.de>
References: <20130411145741.GB25242@game.jcrosoft.org>
 <1365692422-9565-1-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjF5kuu-czkj56-pQdTBUhvY5VodvfnF3RA_DN-O0b9NQ@mail.gmail.com>
 <20130529173538.GC23899@game.jcrosoft.org>
 <CACQ1gAhhsMw1-Znd8BC=A0rJBrB4pphCtH9v9qOQR+j2dY3vCw@mail.gmail.com>
 <20130529193220.GB19468@game.jcrosoft.org>
 <CACQ1gAj_m_aWaq5J41SY8EPwOH5-3zYPsf2WJCunvVnBCyq00Q@mail.gmail.com>
 <20130530072328.GE19468@game.jcrosoft.org>
 <51A761DA.6020109@corscience.de>
Message-ID: <20130530145938.GK19468@game.jcrosoft.org>

On 16:27 Thu 30 May     , Andreas Bie?mann wrote:
> On 30.05.13 09:23, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 08:39 Thu 30 May     , Richard Genoud wrote:
> >> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >>> On 19:44 Wed 29 May     , Richard Genoud wrote:
> >>>> 2013/5/29 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >>>>> On 16:36 Wed 29 May     , Richard Genoud wrote:
> >>>>>> 2013/4/11 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >>>>>>> Today we mix pdata and drivers data in the struct atmel_lcdfb_info
> >>>>>>> Fix it and introduce a new struct atmel_lcdfb_pdata for platform data only
> >>>>>>>
> >>>>>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >>>>>>> Cc: linux-fbdev at vger.kernel.org
> >>>>>>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> >>>>>>> Cc: Andrew Morton <akpm at linux-foundation.org>
> >>>>>>> Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> >>>>>>> ---
> >>>>>>>  arch/arm/mach-at91/at91sam9261_devices.c    |    6 +-
> >>>>>>>  arch/arm/mach-at91/at91sam9263_devices.c    |    6 +-
> >>>>>>>  arch/arm/mach-at91/at91sam9g45_devices.c    |    6 +-
> >>>>>>>  arch/arm/mach-at91/at91sam9rl_devices.c     |    6 +-
> >>>>>>>  arch/arm/mach-at91/board-sam9261ek.c        |    6 +-
> >>>>>>>  arch/arm/mach-at91/board-sam9263ek.c        |    4 +-
> >>>>>>>  arch/arm/mach-at91/board-sam9m10g45ek.c     |    4 +-
> >>>>>>>  arch/arm/mach-at91/board-sam9rlek.c         |    4 +-
> >>>>>>>  arch/arm/mach-at91/board.h                  |    4 +-
> >>>>>>>  arch/avr32/boards/atngw100/evklcd10x.c      |    6 +-
> >>>>>>>  arch/avr32/boards/atngw100/mrmt.c           |    4 +-
> >>>>>>>  arch/avr32/boards/atstk1000/atstk1000.h     |    2 +-
> >>>>>>>  arch/avr32/boards/atstk1000/setup.c         |    2 +-
> >>>>>>>  arch/avr32/boards/favr-32/setup.c           |    2 +-
> >>>>>>>  arch/avr32/boards/hammerhead/setup.c        |    2 +-
> >>>>>>>  arch/avr32/boards/merisc/display.c          |    2 +-
> >>>>>>>  arch/avr32/boards/mimc200/setup.c           |    4 +-
> >>>>>>>  arch/avr32/mach-at32ap/at32ap700x.c         |    8 +--
> >>>>>>>  arch/avr32/mach-at32ap/include/mach/board.h |    4 +-
> >>>>>>>  drivers/video/atmel_lcdfb.c                 |  104 +++++++++++++++++----------
> >>>>>>>  include/video/atmel_lcdc.h                  |   24 +------
> >>>>>>>  21 files changed, 109 insertions(+), 101 deletions(-)
> >>>>>>>
> >>>>>> [snip]
> >>>>>>> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> >>>>>>> index c1a2914..98733cd4 100644
> >>>>>>> --- a/drivers/video/atmel_lcdfb.c
> >>>>>>> +++ b/drivers/video/atmel_lcdfb.c
> >>>>>>> @@ -20,12 +20,45 @@
> >>>>>>>  #include <linux/gfp.h>
> >>>>>>>  #include <linux/module.h>
> >>>>>>>  #include <linux/platform_data/atmel.h>
> >>>>>>> +#include <video/of_display_timing.h>
> >>>>>>>
> >>>>>>>  #include <mach/cpu.h>
> >>>>>>>  #include <asm/gpio.h>
> >>>>>>>
> >>>>>>>  #include <video/atmel_lcdc.h>
> >>>>>>>
> >>>>>>> +struct atmel_lcdfb_config {
> >>>>>>> +       bool have_alt_pixclock;
> >>>>>>> +       bool have_hozval;
> >>>>>>> +       bool have_intensity_bit;
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> + /* LCD Controller info data structure, stored in device platform_data */
> >>>>>>> +struct atmel_lcdfb_info {
> >>>>>>> +       spinlock_t              lock;
> >>>>>>> +       struct fb_info          *info;
> >>>>>>> +       void __iomem            *mmio;
> >>>>>>> +       int                     irq_base;
> >>>>>>> +       struct work_struct      task;
> >>>>>>> +
> >>>>>>> +       unsigned int            smem_len;
> >>>>>>> +       struct platform_device  *pdev;
> >>>>>>> +       struct clk              *bus_clk;
> >>>>>>> +       struct clk              *lcdc_clk;
> >>>>>>> +
> >>>>>>> +       struct backlight_device *backlight;
> >>>>>>> +       u8                      bl_power;
> >>>>>>> +       bool                    lcdcon_pol_negative;
> >>>>>> I think lcdcon_pol_negative should be part of pdata, because it really
> >>>>>> depends on how the PWM is wired on the board.
> >>>>>>
> >>>>>
> >>>>> maybe but no one mainline use it on any pdata for non-dt boars
> >>>>> so I did not want to expose it
> >>>> Well, at least, I'm using it :)
> >>>> (and I guess that Andreas is using it also, otherwise he wouldn't have
> >>>> introduce it !)
> >>>
> >>> yes but pdata is for non-dt boards, for dt you can keep it in struct
> >>> atmel_lcdfb_info and add a property
> >>>
> >>> if non-dt boards want it my answer is I do not care switch to DT
> >>
> >> ok (I use a full DT board based on sam9g35)
> >>
> >> so I'll add something like
> >> sinfo->lcdcon_pol_negative = of_property_read_bool(display_np,
> >> "atmel,lcdcon-pwm-pulse-low");
> >> in /atmel_lcdfb.c
> >>
> >> But I thought the goal of this patch was to separate driver data from
> >> platform specific data, and IMHO, lcdcon_pol_negative is a specificity
> >> of the platform.
> > 
> > You are right but as non one mainline use it as pdata I choose to drop it
> > and only keep it on the driver as we can still use it for DT
> > 
> > It's a way to force peopoe to switch to DT
> 
> well, we use it on an avr32 board (not mainlined; though no kernel
> update planned currently) ... but no way to use DT currently.

If there is 1 ARV32 user it's an other story

Best Regards,
J.
> 
> Best regards
> 
> Andreas Bie?mann


From aida.mynzhasova at skitlab.ru  Thu May 30 11:04:50 2013
From: aida.mynzhasova at skitlab.ru (Aida Mynzhasova)
Date: Thu, 30 May 2013 19:04:50 +0400
Subject: [PATCH] ARM: OMAP: TI816X: add powerdomains for TI816x
Message-ID: <1369926290-30404-1-git-send-email-aida.mynzhasova@skitlab.ru>

This patch adds required structures for powerdomain initialization on
the ti816x. It is impossible to use omap3430 structures in order to
initialize powerdomains on ti816x, because there are big differences
between PRCM module base address offsets on these CPUs.

Signed-off-by: Aida Mynzhasova <aida.mynzhasova at skitlab.ru>
---
 arch/arm/mach-omap2/powerdomains3xxx_data.c |   62 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/prcm-common.h           |   11 +++++
 2 files changed, 73 insertions(+)

diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9..e2d4bd8 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = {
 	.voltdm		  = { .name = "core" },
 };
 
+static struct powerdomain device_81xx_pwrdm = {
+	.name		  = "device_pwrdm",
+	.prcm_offs	  = TI81XX_PRM_DEVICE_MOD,
+	.voltdm		  = { .name = "core" },
+};
+
+static struct powerdomain active_816x_pwrdm = {
+	.name		  = "active_pwrdm",
+	.prcm_offs	  = TI816X_PRM_ACTIVE_MOD,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.voltdm		  = { .name = "core" },
+};
+
+static struct powerdomain default_816x_pwrdm = {
+	.name		  = "default_pwrdm",
+	.prcm_offs	  = TI81XX_PRM_DEFAULT_MOD,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.voltdm		  = { .name = "core" },
+};
+
+static struct powerdomain ivahd0_816x_pwrdm = {
+	.name		  = "ivahd0_pwrdm",
+	.prcm_offs	  = TI816X_PRM_IVAHD0_MOD,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.voltdm		  = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd1_816x_pwrdm = {
+	.name		  = "ivahd1_pwrdm",
+	.prcm_offs	  = TI816X_PRM_IVAHD1_MOD,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.voltdm		  = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd2_816x_pwrdm = {
+	.name		  = "ivahd2_pwrdm",
+	.prcm_offs	  = TI816X_PRM_IVAHD2_MOD,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.voltdm		  = { .name = "mpu_iva" },
+};
+
+static struct powerdomain sgx_816x_pwrdm = {
+	.name		  = "sgx_pwrdm",
+	.prcm_offs	  = TI816X_PRM_SGX_MOD,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.voltdm		  = { .name = "core" },
+};
+
 /* As powerdomains are added or removed above, this list must also be changed */
 static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
 	&wkup_omap2_pwrdm,
@@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
 	NULL
 };
 
+static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+	&device_81xx_pwrdm,
+	&active_816x_pwrdm,
+	&default_816x_pwrdm,
+	&ivahd0_816x_pwrdm,
+	&ivahd1_816x_pwrdm,
+	&ivahd2_816x_pwrdm,
+	&sgx_816x_pwrdm,
+	NULL
+};
+
 void __init omap3xxx_powerdomains_init(void)
 {
 	unsigned int rev;
@@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void)
 
 	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
 		pwrdm_register_pwrdms(powerdomains_am35x);
+	} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
+			|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
+		pwrdm_register_pwrdms(powerdomains_ti81xx);
 	} else {
 		pwrdm_register_pwrdms(powerdomains_omap3430_common);
 
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c7d355f..ff1ac4a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -48,6 +48,17 @@
 #define OMAP3430_NEON_MOD				0xb00
 #define OMAP3430ES2_USBHOST_MOD				0xc00
 
+/*
+ * TI81XX PRM module offsets
+ */
+#define TI81XX_PRM_DEVICE_MOD			0x0000
+#define TI816X_PRM_ACTIVE_MOD			0x0a00
+#define TI81XX_PRM_DEFAULT_MOD			0x0b00
+#define TI816X_PRM_IVAHD0_MOD			0x0c00
+#define TI816X_PRM_IVAHD1_MOD			0x0d00
+#define TI816X_PRM_IVAHD2_MOD			0x0e00
+#define TI816X_PRM_SGX_MOD				0x0f00
+
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-- 
1.7.10.4



From will.deacon at arm.com  Thu May 30 11:27:47 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 30 May 2013 16:27:47 +0100
Subject: [PATCH v2] arm64: extable: sort the exception table at build time
In-Reply-To: <1369245812-27231-1-git-send-email-will.deacon@arm.com>
References: <1369245812-27231-1-git-send-email-will.deacon@arm.com>
Message-ID: <20130530152746.GV7483@mudshark.cambridge.arm.com>

On Wed, May 22, 2013 at 07:03:32PM +0100, Will Deacon wrote:
> As is done for other architectures, sort the exception table at
> build-time rather than during boot.
> 
> Since sortextable appears to be a standalone C program relying on the
> host elf.h to provide EM_AARCH64, I've had to add a conditional check in
> order to allow cross-compilation on machines that aren't running a
> bleeding-edge libc-dev.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm64/Kconfig              |  1 +
>  arch/arm64/kernel/vmlinux.lds.S | 10 +---------
>  scripts/sortextable.c           |  5 +++++
>  3 files changed, 7 insertions(+), 9 deletions(-)

[...]

> diff --git a/scripts/sortextable.c b/scripts/sortextable.c
> index 1f10e89..f9ce116 100644
> --- a/scripts/sortextable.c
> +++ b/scripts/sortextable.c
> @@ -31,6 +31,10 @@
>  #include <tools/be_byteshift.h>
>  #include <tools/le_byteshift.h>
>  
> +#ifndef EM_AARCH64
> +#define EM_AARCH64	183
> +#endif
> +
>  static int fd_map;	/* File descriptor for file being modified. */
>  static int mmap_failed; /* Boolean flag. */
>  static void *ehdr_curr; /* current ElfXX_Ehdr *  for resource cleanup */
> @@ -249,6 +253,7 @@ do_file(char const *const fname)
>  		custom_sort = sort_relative_table;
>  		break;
>  	case EM_ARM:
> +	case EM_AARCH64:
>  	case EM_MIPS:
>  		break;
>  	}  /* end switch */

Any chance I can have an ack for this part of the patch please? Then we can
take it through the arm64 tree.

Cheers,

Will


From tushar.behera at linaro.org  Thu May 30 11:28:39 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu, 30 May 2013 20:58:39 +0530
Subject: [PATCH] ARM: EXYNOS: Update defconfig for Arndale and Origen board
In-Reply-To: <CAHbNUh0kWxqDMvLwE-_PKQVassDJvbgiCiDDNSHn9AW3md=A5A@mail.gmail.com>
References: <1368168599-28507-1-git-send-email-tushar.behera@linaro.org>
 <87sj1qzaov.fsf@linaro.org> <5191AA89.6010901@linaro.org>
 <20130528231740.GA28879@quad.lixom.net>
 <51A57D39.8030506@linaro.org>
 <CAOesGMh50Dzr_jczHZC5_txfW=6a+7EgFKvgZgj9MhUcVUTJ1Q@mail.gmail.com>
 <51A5C16D.20408@linaro.org>
 <000001ce5c4f$839f4cb0$8adde610$@samsung.com>
 <3D99F44C56954EC59167436E26BE91F6@sisodomain.com>
 <CAHbNUh0kWxqDMvLwE-_PKQVassDJvbgiCiDDNSHn9AW3md=A5A@mail.gmail.com>
Message-ID: <CAHbNUh35vdhX4F7=QeXD9RMNKq42Vu-1yjx3LSKnbd_TH_+vrw@mail.gmail.com>

Resending in plain-text mode.

On 30 May 2013 20:56, Tushar Behera <tushar.behera at linaro.org> wrote:
>>>
>> We do have a driver for USB3503 in upstream now, which has enough
>> infrastructure for us to use.
>> We just want to handle states of HUB_CONNECT line or RESET_N line, which
>> should just be fine with this driver.
>>
>> Am I missing something ?
>>

The USB3503 driver is an I2C client driver. In case of Arndale, the SDA and
SCL lines for SMSC3503 chip are sorted, hence there are no I2C channels that
the driver can register to. So effectively we can't use that driver for
Arndale.

-- 
Tushar Behera


From will.deacon at arm.com  Thu May 30 11:40:47 2013
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 30 May 2013 16:40:47 +0100
Subject: [PATCH V1] ARM: mm: lazy cache flushing on non-mapped pages
In-Reply-To: <1369839416-27817-1-git-send-email-ming.lei@canonical.com>
References: <1369839416-27817-1-git-send-email-ming.lei@canonical.com>
Message-ID: <20130530154047.GW7483@mudshark.cambridge.arm.com>

On Wed, May 29, 2013 at 03:56:56PM +0100, Ming Lei wrote:
> Currently flush_dcache_page() thinks pages as non-mapped if
> mapping_mapped(mapping) return false. This approach is very
> coase:
> 	- mmap on part of file may cause all pages backed on
> 	the file being thought as mmaped
> 
> 	- file-backed pages aren't mapped into user space actually
> 	if the memory mmaped on the file isn't accessed
> 
> This patch uses page_mapped() to decide if the page has been
> mapped.

[...]

> diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> index 0d473cc..008af99 100644
> --- a/arch/arm/mm/flush.c
> +++ b/arch/arm/mm/flush.c
> @@ -286,8 +286,8 @@ void flush_dcache_page(struct page *page)
>  
>  	mapping = page_mapping(page);
>  
> -	if (!cache_ops_need_broadcast() &&
> -	    mapping && !mapping_mapped(mapping))
> +	if (!cache_ops_need_broadcast() && mapping &&
> +		(!mapping_mapped(mapping) || !page_mapped(page)))
>  		clear_bit(PG_dcache_clean, &page->flags);
>  	else {
>  		__flush_dcache_page(mapping, page);

Does the page_mapped test make the mapping_mapped test redundant? It sounds
strange if it's possible to get a non-zero mapcount for a page when its
address space isn't mapped.

Will


From dianders at chromium.org  Thu May 30 11:55:10 2013
From: dianders at chromium.org (Doug Anderson)
Date: Thu, 30 May 2013 08:55:10 -0700
Subject: [PATCH v2 2/5] clk: samsung: Add support to register rate_table
 for PLL3xxx
In-Reply-To: <CAKew6eVGnHNN7Fk=sqzE1iV+SFtJ1z4k1freeWdbGaYPXqpUvQ@mail.gmail.com>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
 <1369834677-20312-3-git-send-email-vikas.sajjan@linaro.org>
 <CAD=FV=VDi+SfebiFnPNp8qR__9L=o9TJ+WSPRfRQLX+p+TMmJw@mail.gmail.com>
 <CAKew6eVGnHNN7Fk=sqzE1iV+SFtJ1z4k1freeWdbGaYPXqpUvQ@mail.gmail.com>
Message-ID: <CAD=FV=VEUTimNVqQvVZAkU7Qa9yy4R99E+WHA-aOzn61JBH_fw@mail.gmail.com>

Yadwinder and Vikas,

On Wed, May 29, 2013 at 11:55 PM, Yadwinder Singh Brar
<yadi.brar01 at gmail.com> wrote:
>> Also: you can include rate here if you need a convenient place to
>> store it (which sadly means that this structure can't be const).
>> ...but I do like Tomasz's idea of actually calculating it.  You can't
>> know it at compile time since the parent rate comes from the device
>> tree.
>>
>> compatible = "samsung,clock-xxti";
>> clock-frequency = <24000000>;
>>
>
> Actually this table should contain the recommended values
> and if we see the user manual, the input(parent) rate is also a part
> of recommended
> table of different output rate for a particular PLL for that SoC.

That's a reasonable point.  It's not clear to me whether the
recommended PMSK values would be the same or different if the input
wasn't 24MHz.  You're assuming that they would be different and that
seems fair given my (limited) understanding of the electrical
characteristics of PLLs.

...so if a given SoC needed to support multiple different parent clock
frequencies the presumably it would have multiple tables and pick the
right one to pass in.


> So as Tomasz said input(parent) rate may change with board,
> then, do those corresponding recommended p, m, s, k will be valid?
>
> In case, input(parent) rate changes then we may need different set of p, m ,s, k
> values recommended for new input rate to get required(recommended to
> use) output rate.
>
> So, we think its better that the p, m, s and k along with the parent
> is known at the compile time ( or DT ?),
> as these p, m, s, k values are very much coupled with the parent rate
> to achieve the
>  required(recommended to use) output rate.

Having the rate in the table definitely makes it easier to understand,
too.  We just have to hope someone doesn't mess up in their
calculation.  Worst case we could put some error checking somewhere.


> Also, since the sorted table is required (sorted based on "rate"),
> its better to have the rate in a const rate table.

You _could_ still sort the table based on eventually rate even if the
actual rate wasn't in the table.  ...but I agree that it's harder to
look at and figure out.


> And the whole set of recommended values should come from same place(DT
> or static table),
> to keep the things simple and consistent.

Agree that it's a little weird now that some bits of the clock code is
in the device tree and some bits are just static tables in code.
...but I think that's OK for now.

Perhaps a reasonable compromise is to include "24mhz" in the name of
the tables (in later patches) and then give a WARN_ON if the xxti
clock isn't 24MHz.  Then you've effectively documented the plan of
action should someone eventually need a different xxti clock.


> Moreover, practically for a particular SoC , we use the recommended
> input(parent) rate only for a PLL.
> So we should keep the things simple here presently.

>From what I've seen so far I could totally believe Samsung releasing a
new user manual in the future that provides instructions for using a
non-24MHz xxti clock.  ...but with all of the above I think we've got
a reasonable story so I think we're good.


>>> +       unsigned int pdiv;
>>> +       unsigned int mdiv;
>>> +       unsigned int sdiv;
>>> +       unsigned int kdiv;
>>
>> I think kdiv is signed.
>>
>
> No, as these values should be the recommended values to be written in
> corresponding  register bits. So it should remain unsigned.
>
> K value should be considered as negative only while recalculating rate.
>
> As per exynos5250 user manual's section 7.3.2 :
> " K value description "Postive value (Negative value)":
> Postive values is that you should write EPLLCON/VPLLCON register.
> Negative value is that you can calculate PLL output frequency with it."

OK, fair point.  We can keep it unsigned in this table.


To summarize where I think we are in this series, I'm hoping for one
more version that:
* Adds a comment about the rate table being sorted (and which direction)
* Adds "24mhz" to the variable name for the PLL tables in future patch series
* Adds a WARN_ON if the xxti clock isn't 24MHz


Does that sound like a plan?  Tomasz: any thoughts on the above?


-Doug


From g.liakhovetski at gmx.de  Thu May 30 12:02:12 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 30 May 2013 18:02:12 +0200 (CEST)
Subject: [PATCH] dmaengine: shdma: fix a build failure on platforms with no
 DMA support
Message-ID: <Pine.LNX.4.64.1305301650290.29171@axis700.grange>

On platforms with no support for the shdma dmaengine driver build is
currently failing with

drivers/built-in.o: In function `sh_mobile_sdhi_probe':
drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'

Fix the breakage by defining shdma_chan_filter to NULL in such
configurations.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---

This is for "next." Compile-tested only. I'll test it on hardware next 
week, but I don't think it shall break anything.

 include/linux/sh_dma.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index b64d6be..1fd8a20 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -99,6 +99,10 @@ struct sh_dmae_pdata {
 #define CHCR_TE	0x00000002
 #define CHCR_IE	0x00000004
 
+#if IS_ENABLED(CONFIG_SH_DMAE)
 bool shdma_chan_filter(struct dma_chan *chan, void *arg);
+#else
+#define shdma_chan_filter NULL
+#endif
 
 #endif
-- 
1.7.2.5



From ludovic.desroches at atmel.com  Thu May 30 12:08:20 2013
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Thu, 30 May 2013 18:08:20 +0200
Subject: [PATCH 0/3] at_hdmac: dt dma bindings update
Message-ID: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Hi,

This set of patches update the dt dma binding for at_hdmac since we need one
more parameter. In order to keep backward compatibility, an existing cell will
be used to add this parameter. Since the content of that cell will become a
magic value due to the concatenation of the two parameters, it is time to
use macros.

Regards

Ludovic Desroches (3):
  ARM: at91: dt: add header to define at_hdmac configuration
  ARM: at91: dt: switch DMA DT bindings to pre-processor
  at_hdmac: add FIFO configuration parameter to DMA DT binding

 .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
 arch/arm/boot/dts/at91sam9g45.dtsi                 |  5 ++--
 arch/arm/boot/dts/at91sam9n12.dtsi                 | 11 +++++----
 arch/arm/boot/dts/at91sam9x5.dtsi                  | 17 +++++++-------
 arch/arm/boot/dts/sama5d3.dtsi                     | 19 +++++++--------
 drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++----
 include/dt-bindings/dma/at91.h                     | 27 ++++++++++++++++++++++
 7 files changed, 81 insertions(+), 30 deletions(-)
 create mode 100644 include/dt-bindings/dma/at91.h

-- 
1.7.11.3



From ludovic.desroches at atmel.com  Thu May 30 12:08:21 2013
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Thu, 30 May 2013 18:08:21 +0200
Subject: [PATCH 1/3] ARM: at91: dt: add header to define at_hdmac configuration
In-Reply-To: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1369930103-11963-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

DMA-cell content is a concatenation of several values. In order to keep this
stuff human readable, macros are introduced.

The values for the FIFO configuration are not the same as the ones used in the
configuration register in order to keep backward compatibility. Most devices
use the half FIFO configuration but USART ones have to use the ASAP
configuration. This parameter was not initially planed to be into the at91 dma
dt binding. The third cell will be used to store this parameter, it will
become a concatenation of the FIFO configuration and of the peripheral ID. In
order to keep backward compatibility i.e. FIFO configuration is equal to 0, we
have to perform a translation since the value to put in the register to set
half FIFO is 1.

Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 include/dt-bindings/dma/at91.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 include/dt-bindings/dma/at91.h

diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
new file mode 100644
index 0000000..e835037
--- /dev/null
+++ b/include/dt-bindings/dma/at91.h
@@ -0,0 +1,27 @@
+/*
+ * This header provides macros for at91 dma bindings.
+ *
+ * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches at atmel.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_DMA_H__
+#define __DT_BINDINGS_AT91_DMA_H__
+
+/*
+ * Source and/or destination peripheral ID
+ */
+#define AT91_DMA_CFG_PER_ID_MASK	(0xff)
+#define AT91_DMA_CFG_PER_ID(id)		(id & AT91_DMA_CFG_PER_ID_MASK)
+
+/*
+ * FIFO configuration: it defines when a request is serviced.
+ */
+#define AT91_DMA_CFG_FIFOCFG_OFFSET	(8)
+#define AT91_DMA_CFG_FIFOCFG_MASK	(0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
+#define AT91_DMA_CFG_FIFOCFG_HALF	(0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* half FIFO (default behavior) */
+#define AT91_DMA_CFG_FIFOCFG_ALAP	(0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* largest defined AHB burst */
+#define AT91_DMA_CFG_FIFOCFG_ASAP	(0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* single AHB access */
+
+#endif /* __DT_BINDINGS_AT91_DMA_H__ */
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Thu May 30 12:08:22 2013
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Thu, 30 May 2013 18:08:22 +0200
Subject: [PATCH 2/3] ARM: at91: dt: switch DMA DT bindings to pre-processor
In-Reply-To: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1369930103-11963-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9g45.dtsi |  5 +++--
 arch/arm/boot/dts/at91sam9n12.dtsi | 11 ++++++-----
 arch/arm/boot/dts/at91sam9x5.dtsi  | 17 +++++++++--------
 arch/arm/boot/dts/sama5d3.dtsi     | 19 ++++++++++---------
 4 files changed, 28 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index f0091af..fe84404 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -537,7 +538,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xfff80000 0x600>;
 				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma 1 0>;
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -548,7 +549,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xfffd0000 0x600>;
 				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma 1 13>;
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 566af32..3076693 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -8,6 +8,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -92,7 +93,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xf0008000 0x600>;
 				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma 1 0>;
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -384,8 +385,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;
 				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma 1 13>,
-				       <&dma 1 14>;
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
+				       <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
 				dma-names = "tx", "rx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -396,8 +397,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8014000 0x100>;
 				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma 1 15>,
-				       <&dma 1 16>;
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
+				       <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
 				dma-names = "tx", "rx";
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599..a08bf77 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -470,7 +471,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xf0008000 0x600>;
 				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma0 1 0>;
+				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -481,7 +482,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xf000c000 0x600>;
 				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma1 1 0>;
+				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -544,8 +545,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;
 				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma0 1 7>,
-				       <&dma0 1 8>;
+				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
+				       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
 				dma-names = "tx", "rx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -558,8 +559,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8014000 0x100>;
 				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma1 1 5>,
-				       <&dma1 1 6>;
+				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
+				       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
 				dma-names = "tx", "rx";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -572,8 +573,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8018000 0x100>;
 				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma0 1 9>,
-				       <&dma0 1 10>;
+				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
+				       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
 				dma-names = "tx", "rx";
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index c00e158..03b8c02 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -63,7 +64,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xf0000000 0x600>;
 				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma0 2 0>;
+				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
@@ -116,8 +117,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf0014000 0x4000>;
 				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma0 2 7>,
-				       <&dma0 2 8>;
+				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
+				       <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
 				dma-names = "tx", "rx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_i2c0>;
@@ -130,8 +131,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf0018000 0x4000>;
 				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma0 2 9>,
-				       <&dma0 2 10>;
+				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
+				       <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
 				dma-names = "tx", "rx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_i2c1>;
@@ -178,7 +179,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xf8000000 0x600>;
 				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma1 2 0>;
+				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
@@ -191,7 +192,7 @@
 				compatible = "atmel,hsmci";
 				reg = <0xf8004000 0x600>;
 				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
-				dmas = <&dma1 2 1>;
+				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
 				dma-names = "rxtx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
@@ -309,8 +310,8 @@
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf801c000 0x4000>;
 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
-				dmas = <&dma1 2 11>,
-				       <&dma1 2 12>;
+				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
+				       <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
 				dma-names = "tx", "rx";
 				#address-cells = <1>;
 				#size-cells = <0>;
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Thu May 30 12:08:23 2013
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Thu, 30 May 2013 18:08:23 +0200
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA DT
 binding
In-Reply-To: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

For most devices the FIFO configuration is the same i.e. when half FIFO size is
available/filled, a source/destination request is serviced. But USART devices
have to do it when there is enough space/data available to perform a single
AHB access so the ASAP configuration.

Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
 drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++++----
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
index c80e8a3..c280a0e 100644
--- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
@@ -24,8 +24,11 @@ The three cells in order are:
 1. A phandle pointing to the DMA controller.
 2. The memory interface (16 most significant bits), the peripheral interface
 (16 less significant bits).
-3. The peripheral identifier for the hardware handshaking interface. The
-identifier can be different for tx and rx.
+3. Parameters for the at91 DMA configuration register which are device
+dependant:
+  - bit 7-0: peripheral identifier for the hardware handshaking interface. The
+  identifier can be different for tx and rx.
+  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.
 
 Example:
 
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index e923cda..bfd73e1 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -14,6 +14,7 @@
  * found on AT91SAM9263.
  */
 
+#include <dt-bindings/dma/at91.h>
 #include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
@@ -1223,14 +1224,30 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
 	atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL);
 	if (!atslave)
 		return NULL;
+
+	atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
 	/*
 	 * We can fill both SRC_PER and DST_PER, one of these fields will be
 	 * ignored depending on DMA transfer direction.
 	 */
-	per_id = dma_spec->args[1];
-	atslave->cfg = ATC_FIFOCFG_HALFFIFO | ATC_DST_H2SEL_HW
-		      | ATC_SRC_H2SEL_HW | ATC_DST_PER(per_id)
-		      | ATC_SRC_PER(per_id);
+	per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
+	atslave->cfg |= ATC_DST_PER(per_id) | ATC_SRC_PER(per_id);
+	/*
+	 * We have to translate the value we get from the device tree since
+	 * the half FIFO configuration value had to be 0 to keep backward
+	 * compatibility.
+	 */
+	switch(dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
+		case AT91_DMA_CFG_FIFOCFG_ALAP:
+			atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
+			break;
+		case AT91_DMA_CFG_FIFOCFG_ASAP:
+			atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
+			break;
+		case AT91_DMA_CFG_FIFOCFG_HALF:
+		default:
+			atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
+	}
 	atslave->dma_dev = &dmac_pdev->dev;
 
 	chan = dma_request_channel(mask, at_dma_filter, atslave);
-- 
1.7.11.3



From john.stultz at linaro.org  Thu May 30 12:11:17 2013
From: john.stultz at linaro.org (John Stultz)
Date: Thu, 30 May 2013 09:11:17 -0700
Subject: [RFC PATCH 2/2] clocksource: dw_apb: allow build for architectures
 other than arm
In-Reply-To: <20130530053233.GL25186@sapphire.tkos.co.il>
References: <1369570367-994-2-git-send-email-baruch@tkos.co.il>
 <51A51271.2070506@linaro.org> <20130530053233.GL25186@sapphire.tkos.co.il>
Message-ID: <51A77A25.8080306@linaro.org>

On 05/29/2013 10:32 PM, Baruch Siach wrote:
> Hi John,
>
> On Tue, May 28, 2013 at 01:24:17PM -0700, John Stultz wrote:
>> On 05/26/2013 05:12 AM, Baruch Siach wrote:
>>>   static const struct of_device_id osctimer_ids[] __initconst = {
>>> @@ -124,3 +135,10 @@ void __init dw_apb_timer_init(void)
>>>   	init_sched_clock();
>>>   }
>>> +
>>> +#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
>>> +unsigned long long notrace sched_clock()
>>> +{
>>> +	return read_sched_clock() * sched_clock_mult;
>>> +}
>>> +#endif
>> Also, can you try to condense the number of #ifndef
>> CONFIG_HAVE_SETUP_SCHED_CLOCK checks to one, and consolidate the
>> needed functions all in that one conditional?
> Thanks for your comments. I'll rework the patch and resubmit.
>
> I've just noticed that I have a bigger problem. read_sched_clock() returns
> u32, not u64. This means that in a rate of, say, 100MHz it will wrap around
> after a little more than 40 seconds. Would it make sense to put ARM's 32 bin
> sched_clock extension code (arch/arm/kernel/sched_clock.c) is a common place
> (maybe drivers/clocksource), and use that? There seems to be nothing ARM
> specific in this code, after all.

Yea, working out an actual generic sched_clock implementation is 
something I'd like to see done.

Though I'd really rather we not toss yet another chunk of infrastructure 
in the drivers/clocksource directory. Instead we should probably have a 
kernel/time/sched_clock.c.

Then its just the issue of tying that and the clocksource code together 
so you just register existing capable clocksources with a SCHED_CLOCK 
flag or via a different registration hook.

I don't think it will be an easy job, but if you want to give it a shot, 
I'd be quite interested in reviewing the patches!

thanks
-john








From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:23 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:23 +0100
Subject: [PATCH RFC 0/6] Introduce Xen support to ARM64
Message-ID: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>

Hi all,
this patch series introduces Xen support to arch/arm64.

As you can see from the following patches, there is very little arm64
specific code here, basically only one assembly file
(arch/arm64/xen/hypercall.S).

Everything else is common with Xen for ARMv7, in particular the code
under arch/arm/xen (enlighten.c and the stubs in grant-table.c) and all
the header files under arch/arm/include/asm/xen (events.h, hypercall.h,
hypervisor.h, interface.h, page.h) can be reused (almost) as-is.

Not knowning what is the best way forward I have just created symlinks
to the original files under arch/arm, see the first patch.

Please advice on what you think is the best way forward.



Stefano Stabellini (6):
      [HACK!] arm64/xen: create links to arch/arm include files and Xen code
      arm64/xen: arm header changes to compile on arm64
      arm64/xen: use XEN_IO_PROTO_ABI_ARM on ARM64
      arm64/xen: introduce asm/hypervisor.h and sys_bitops.h
      arm64/xen: implement xen_remap on arm64
      arm64/xen: introduce CONFIG_XEN and hypercall.S on ARM64

 arch/arm/include/asm/xen/events.h    |    4 +
 arch/arm/include/asm/xen/page.h      |    6 ++
 arch/arm64/Kconfig                   |   11 ++++
 arch/arm64/Makefile                  |    1 +
 arch/arm64/include/asm/hypervisor.h  |    6 ++
 arch/arm64/include/asm/io.h          |    1 +
 arch/arm64/include/asm/sync_bitops.h |   26 ++++++++
 arch/arm64/include/asm/xen           |    1 +
 arch/arm64/xen/Makefile              |    1 +
 arch/arm64/xen/enlighten.c           |    1 +
 arch/arm64/xen/grant-table.c         |    1 +
 arch/arm64/xen/hypercall.S           |  105 ++++++++++++++++++++++++++++++++++
 include/xen/interface/io/protocols.h |    2 +-
 13 files changed, 165 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm64/include/asm/hypervisor.h
 create mode 100644 arch/arm64/include/asm/sync_bitops.h
 create mode 120000 arch/arm64/include/asm/xen
 create mode 100644 arch/arm64/xen/Makefile
 create mode 120000 arch/arm64/xen/enlighten.c
 create mode 120000 arch/arm64/xen/grant-table.c
 create mode 100644 arch/arm64/xen/hypercall.S

- Stefano


From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:30 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:30 +0100
Subject: [PATCH RFC 3/6] arm64/xen: use XEN_IO_PROTO_ABI_ARM on ARM64
In-Reply-To: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
Message-ID: <1369930713-6063-3-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 include/xen/interface/io/protocols.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h
index 0eafaf2..056744b 100644
--- a/include/xen/interface/io/protocols.h
+++ b/include/xen/interface/io/protocols.h
@@ -15,7 +15,7 @@
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64
 #elif defined(__powerpc64__)
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64
-#elif defined(__arm__)
+#elif defined(__arm__) || defined(__aarch64__)
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
 #else
 # error arch fixup needed here
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:32 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:32 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
Message-ID: <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/page.h |    4 ++++
 arch/arm64/include/asm/io.h     |    1 +
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index cb2fa15..d995ece 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
 	return __set_phys_to_machine(pfn, mfn);
 }
 
+#ifdef CONFIG_ARM64
+#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
+#else
 #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
+#endif
 
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 2e12258..0e9c9ac 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -228,6 +228,7 @@ extern void __iounmap(volatile void __iomem *addr);
 #define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
 #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
+#define PROT_NORMAL		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
 
 #define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:33 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:33 +0100
Subject: [PATCH RFC 6/6] arm64/xen: introduce CONFIG_XEN and hypercall.S on
 ARM64
In-Reply-To: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
Message-ID: <1369930713-6063-6-git-send-email-stefano.stabellini@eu.citrix.com>

Introduce CONFIG_XEN and the implementation of hypercall.S (that is
the only ARMv8 specific code in Xen support for ARM).

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm64/Kconfig         |   11 +++++
 arch/arm64/Makefile        |    1 +
 arch/arm64/xen/Makefile    |    1 +
 arch/arm64/xen/hypercall.S |  105 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 118 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/xen/Makefile
 create mode 100644 arch/arm64/xen/hypercall.S

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 56b3f6d..f35751f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -182,6 +182,17 @@ config HW_PERF_EVENTS
 
 source "mm/Kconfig"
 
+config XEN_DOM0
+	def_bool y
+	depends on XEN
+
+config XEN
+	bool "Xen guest support on ARM64 (EXPERIMENTAL)"
+	depends on ARM64 && OF
+	depends on !GENERIC_ATOMIC64
+	help
+	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index c95c5cb..79dd13d 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -37,6 +37,7 @@ TEXT_OFFSET := 0x00080000
 export	TEXT_OFFSET GZFLAGS
 
 core-y		+= arch/arm64/kernel/ arch/arm64/mm/
+core-$(CONFIG_XEN)		+= arch/arm64/xen/
 libs-y		:= arch/arm64/lib/ $(libs-y)
 libs-y		+= $(LIBGCC)
 
diff --git a/arch/arm64/xen/Makefile b/arch/arm64/xen/Makefile
new file mode 100644
index 0000000..4384103
--- /dev/null
+++ b/arch/arm64/xen/Makefile
@@ -0,0 +1 @@
+obj-y		:= enlighten.o hypercall.o grant-table.o
diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S
new file mode 100644
index 0000000..131e4a6
--- /dev/null
+++ b/arch/arm64/xen/hypercall.S
@@ -0,0 +1,105 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/*
+ * The Xen hypercall calling convention is very similar to the ARM AEBI
+ * procedure calling convention: the first paramter is passed in x0, the
+ * second in x1, the third in x2 and the fourth in x3. Considering that
+ * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * in rx, differently from the procedure calling convention of using the
+ * stack for that case.
+ *
+ * The hypercall number is passed in x16.
+ *
+ * The return value is in x0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ *
+ * Parameter structs passed to hypercalls are laid out according to
+ * the ARM EABI standard.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+
+
+#define XEN_IMM 0xEA1
+
+#define HYPERCALL_SIMPLE(hypercall)		\
+ENTRY(HYPERVISOR_##hypercall)			\
+	mov x16, #__HYPERVISOR_##hypercall;	\
+	hvc XEN_IMM;						\
+	ret;								\
+ENDPROC(HYPERVISOR_##hypercall)
+
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+
+#define HYPERCALL5(hypercall)			\
+ENTRY(HYPERVISOR_##hypercall)			\
+	stmdb sp!, {x4}						\
+	ldr x4, [sp, #4]					\
+	mov x16, #__HYPERVISOR_##hypercall;	\
+	hvc XEN_IMM;						\
+	ldm sp!, {r4}						\
+	ret									\
+ENDPROC(HYPERVISOR_##hypercall)
+
+                .text
+
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+HYPERCALL3(vcpu_op);
+
+ENTRY(privcmd_call)
+	push x4, xzr
+	mov x16, x0
+	mov x0, x1
+	mov x1, x2
+	mov x2, x3
+	ldr x3, [sp, #8]
+	ldr x4, [sp, #4]
+	hvc XEN_IMM
+	pop x5, xzr
+	ret
+ENDPROC(privcmd_call);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:29 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:29 +0100
Subject: [PATCH RFC 2/6] arm64/xen: arm/xen header changes to compile on arm64
In-Reply-To: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
Message-ID: <1369930713-6063-2-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/events.h |    4 ++++
 arch/arm/include/asm/xen/page.h   |    2 ++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
index 8b1f37b..12e4e0b 100644
--- a/arch/arm/include/asm/xen/events.h
+++ b/arch/arm/include/asm/xen/events.h
@@ -13,7 +13,11 @@ enum ipi_vector {
 
 static inline int xen_irqs_disabled(struct pt_regs *regs)
 {
+#ifdef CONFIG_ARM
 	return raw_irqs_disabled_flags(regs->ARM_cpsr);
+#else
+	return raw_irqs_disabled_flags((unsigned long) regs->pstate);
+#endif
 }
 
 #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr),	\
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 30cdacb..cb2fa15 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,7 +1,9 @@
 #ifndef _ASM_ARM_XEN_PAGE_H
 #define _ASM_ARM_XEN_PAGE_H
 
+#ifdef ARM
 #include <asm/mach/map.h>
+#endif
 #include <asm/page.h>
 #include <asm/pgtable.h>
 
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:31 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:31 +0100
Subject: [PATCH RFC 4/6] arm64/xen: introduce asm/hypervisor.h and sys_bitops.h
In-Reply-To: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
Message-ID: <1369930713-6063-4-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm64/include/asm/hypervisor.h  |    6 ++++++
 arch/arm64/include/asm/sync_bitops.h |   26 ++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/hypervisor.h
 create mode 100644 arch/arm64/include/asm/sync_bitops.h

diff --git a/arch/arm64/include/asm/hypervisor.h b/arch/arm64/include/asm/hypervisor.h
new file mode 100644
index 0000000..b90d9e5
--- /dev/null
+++ b/arch/arm64/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_HYPERVISOR_H
+#define _ASM_ARM_HYPERVISOR_H
+
+#include <asm/xen/hypervisor.h>
+
+#endif
diff --git a/arch/arm64/include/asm/sync_bitops.h b/arch/arm64/include/asm/sync_bitops.h
new file mode 100644
index 0000000..8da0bf4
--- /dev/null
+++ b/arch/arm64/include/asm/sync_bitops.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+
+#include <asm/bitops.h>
+#include <asm/cmpxchg.h>
+
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+
+#define sync_set_bit(nr, p)            set_bit(nr, p)
+#define sync_clear_bit(nr, p)          clear_bit(nr, p)
+#define sync_change_bit(nr, p)         change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)   test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p) test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p)        test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)                test_bit(nr, addr)
+#define sync_cmpxchg                   cmpxchg
+
+#endif
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu May 30 12:18:28 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 30 May 2013 17:18:28 +0100
Subject: [PATCH RFC 1/6] [HACK!] arm64/xen: create links to arch/arm include
 files and Xen code
In-Reply-To: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
Message-ID: <1369930713-6063-1-git-send-email-stefano.stabellini@eu.citrix.com>

Most of Xen support for ARM is common between ARMv7 and ARMv8.
Create links to the code under arch/arm (bleah).

Other, probably better alternatives:

- move the code to a different location, maybe the header files to
include/xen/arm and the code to drivers/xen/arm (still pretty ugly)?

- create a copy of the code to arch/arm64 (even worse);

Please advice on how you would like me to move forward on this.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm64/include/asm/xen   |    1 +
 arch/arm64/xen/enlighten.c   |    1 +
 arch/arm64/xen/grant-table.c |    1 +
 3 files changed, 3 insertions(+), 0 deletions(-)
 create mode 120000 arch/arm64/include/asm/xen
 create mode 120000 arch/arm64/xen/enlighten.c
 create mode 120000 arch/arm64/xen/grant-table.c

diff --git a/arch/arm64/include/asm/xen b/arch/arm64/include/asm/xen
new file mode 120000
index 0000000..c27d6980
--- /dev/null
+++ b/arch/arm64/include/asm/xen
@@ -0,0 +1 @@
+../../../arm/include/asm/xen
\ No newline at end of file
diff --git a/arch/arm64/xen/enlighten.c b/arch/arm64/xen/enlighten.c
new file mode 120000
index 0000000..cb31b7c
--- /dev/null
+++ b/arch/arm64/xen/enlighten.c
@@ -0,0 +1 @@
+../../arm/xen/enlighten.c
\ No newline at end of file
diff --git a/arch/arm64/xen/grant-table.c b/arch/arm64/xen/grant-table.c
new file mode 120000
index 0000000..5494f6c
--- /dev/null
+++ b/arch/arm64/xen/grant-table.c
@@ -0,0 +1 @@
+../../arm/xen/grant-table.c
\ No newline at end of file
-- 
1.7.2.5



From dmurphy at ti.com  Thu May 30 12:23:13 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Thu, 30 May 2013 11:23:13 -0500
Subject: [PATCH] dmaengine: shdma: fix a build failure on platforms with
 no DMA support
In-Reply-To: <Pine.LNX.4.64.1305301650290.29171@axis700.grange>
References: <Pine.LNX.4.64.1305301650290.29171@axis700.grange>
Message-ID: <51A77CF1.7040105@ti.com>

On 05/30/2013 11:02 AM, Guennadi Liakhovetski wrote:
> On platforms with no support for the shdma dmaengine driver build is
> currently failing with
>
> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'
>
> Fix the breakage by defining shdma_chan_filter to NULL in such
> configurations.
>
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> ---
>
> This is for "next." Compile-tested only. I'll test it on hardware next 
> week, but I don't think it shall break anything.
>
>  include/linux/sh_dma.h |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
> index b64d6be..1fd8a20 100644
> --- a/include/linux/sh_dma.h
> +++ b/include/linux/sh_dma.h
> @@ -99,6 +99,10 @@ struct sh_dmae_pdata {
>  #define CHCR_TE	0x00000002
>  #define CHCR_IE	0x00000004
>  
> +#if IS_ENABLED(CONFIG_SH_DMAE)
>  bool shdma_chan_filter(struct dma_chan *chan, void *arg);
> +#else
> +#define shdma_chan_filter NULL
Would this not be better as a
#else
static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg)
{
    return false;
}
#endif

Otherwise runtime will call a NULL pointer

> +#endif
>  
>  #endif


-- 
------------------
Dan Murphy



From hector.palacios at digi.com  Thu May 30 12:17:47 2013
From: hector.palacios at digi.com (Hector Palacios)
Date: Thu, 30 May 2013 18:17:47 +0200
Subject: Chipidea usb otg support for IMX/MXS (device functionality)
In-Reply-To: <20130529075044.GC3293@lukather>
References: <51A5A808.2070803@digi.com>
 <F281D0F91ED19E4D8E63A7504E8A649803E8A3F3@039-SN2MPN1-021.039d.mgd.msft.net>
 <20130529075044.GC3293@lukather>
Message-ID: <51A77BAB.4060101@digi.com>

Dear Maxime,

On 05/29/2013 09:50 AM, maxime.ripard at free-electrons.com wrote:
> Hi,
>
> On Wed, May 29, 2013 at 07:11:30AM +0000, Chen Peter-B29397 wrote:
>>
>>> Hello,
>>>
>>> Am I right in assuming that the MXS USB on-the-go port does not currently
>>> support the
>>> device (gadget) functionality?
>>> Anybody out there working on that?
>>>
>>
>> As far as I know, Maxime Ripard may already let the chipidea durl-role function
>> work ok at mx28. It may need my chipidea otg patch
>>
>> https://github.com/hzpeterchen/linux-usb.git
>
> Indeed, I've been using the patchset "Add tested id switch and vbus
> connect detect support for Chipidea" from Peter for quite some time on
> top of 3.9 and it works like a charm for the gadget mode on an MX28
> platform.
>
> BTW, Peter, I've seen that these patches are still not merged in 3.10,
> is there a reason for that? do you plan on sending a version rebased on
> top of 3.10 some time in the future? I tried to do the rebasing myself,
> but the chipidea driver seems to have changed quite heavily, which makes
> the process quite difficult when you don't know what you're doing :)

I guess you didn't get rid of the 'possible circular locking dependency' you talked 
about at [1], right? I experimented the same and also a BUG [2] after cable reconnection.
Despite those, I ran a simple test of serial, ethernet, and mass_storage gadgets and 
they worked fine.

I didn't use the new properties (phy_type, dr_mode...) in the DT of my mx28 platform, 
did you?

[1] https://lkml.org/lkml/2013/3/6/200

[2]
[ 1949.074726] BUG: spinlock lockup suspected on CPU#0, swapper/0
[ 1949.080623]  lock: 0xcf41f014, .magic: dead4ead, .owner: swapper/0, .owner_cpu: 0
[ 1949.088184] [<c001510c>] (unwind_backtrace+0x0/0xf4) from [<c0273754>] 
(do_raw_spin_lock+0x104/0x14c)
[ 1949.097463] [<c0273754>] (do_raw_spin_lock+0x104/0x14c) from [<c045893c>] 
(_raw_spin_lock_irqsave+0x50/0x5c)
[ 1949.107340] [<c045893c>] (_raw_spin_lock_irqsave+0x50/0x5c) from [<c03467f8>] 
(ep_disable+0x30/0xfc)
[ 1949.116541] [<c03467f8>] (ep_disable+0x30/0xfc) from [<bf00a19c>] 
(gserial_disconnect+0x9c/0x174 [g_serial])
[ 1949.126447] [<bf00a19c>] (gserial_disconnect+0x9c/0x174 [g_serial]) from 
[<bf00a288>] (acm_disable+0xc/0x2c [g_serial])
[ 1949.137325] [<bf00a288>] (acm_disable+0xc/0x2c [g_serial]) from [<bf000930>] 
(reset_config+0x34/0x5c [libcomposite])
[ 1949.147931] [<bf000930>] (reset_config+0x34/0x5c [libcomposite]) from [<bf000fd0>] 
(composite_disconnect+0x34/0x5c [libcomposite])
[ 1949.159737] [<bf000fd0>] (composite_disconnect+0x34/0x5c [libcomposite]) from 
[<c0347b14>] (udc_irq+0x1d8/0xbe4)
[ 1949.169951] [<c0347b14>] (udc_irq+0x1d8/0xbe4) from [<c0345830>] (ci_irq+0x9c/0x104)
[ 1949.177751] [<c0345830>] (ci_irq+0x9c/0x104) from [<c006cb50>] 
(handle_irq_event_percpu+0x5c/0x26c)
[ 1949.186847] [<c006cb50>] (handle_irq_event_percpu+0x5c/0x26c) from [<c006cd9c>] 
(handle_irq_event+0x3c/0x5c)
[ 1949.196716] [<c006cd9c>] (handle_irq_event+0x3c/0x5c) from [<c006f3c8>] 
(handle_level_irq+0x8c/0x118)
[ 1949.205976] [<c006f3c8>] (handle_level_irq+0x8c/0x118) from [<c006cae4>] 
(generic_handle_irq+0x28/0x30)
[ 1949.215421] [<c006cae4>] (generic_handle_irq+0x28/0x30) from [<c001009c>] 
(handle_IRQ+0x30/0x84)
[ 1949.224246] [<c001009c>] (handle_IRQ+0x30/0x84) from [<c00086ec>] 
(icoll_handle_irq+0x30/0x44)
[ 1949.232897] [<c00086ec>] (icoll_handle_irq+0x30/0x44) from [<c000ee24>] 
(__irq_svc+0x44/0x54)
[ 1949.241438] Exception stack(0xc0627f68 to 0xc0627fb0)
[ 1949.246520] 7f60:                   c0010278 0005317f 0005217f 60000013 c0626000 
c0667c88
[ 1949.254729] 7f80: c0631980 7fffffff 40004000 41069265 4061c574 00000000 600000d3 
c0627fb0
[ 1949.262926] 7fa0: c0010278 c0010284 60000013 ffffffff
[ 1949.268023] [<c000ee24>] (__irq_svc+0x44/0x54) from [<c0010284>] 
(default_idle+0x40/0x48)
[ 1949.276244] [<c0010284>] (default_idle+0x40/0x48) from [<c00105b8>] 
(cpu_idle+0x68/0xd0)
[ 1949.284380] [<c00105b8>] (cpu_idle+0x68/0xd0) from [<c0600810>] 
(start_kernel+0x258/0x298)
[ 1953.034550]  gadget: high-speed config #2: CDC ACM config

Regards,
--
H?ctor Palacios


From dianders at chromium.org  Thu May 30 12:25:29 2013
From: dianders at chromium.org (Doug Anderson)
Date: Thu, 30 May 2013 09:25:29 -0700
Subject: [PATCH v2 3/5] clk: samsung: Add set_rate() clk_ops for PLL35xx
In-Reply-To: <1369834677-20312-4-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
 <1369834677-20312-4-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=VnrVAR6Uiy9VXAhbPLQxzeuQXZ3m0WQ6YhJzehaUdBog@mail.gmail.com>

Vikas / Yadwinder,

On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>
> This patch add set_rate() and round_rate() for PLL35xx
>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-pll.c |  103 ++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 102 insertions(+), 1 deletion(-)
[ cut ]
> +#define PLL35XX_LOCK_STAT_MASK  (0x1)

optional: Mask is _slightly_ overkill here. Could just assume that
it's a 1-bit thing and do (1 << PLL35XX_LOCK_STAT_SHIFT).


All comments are optional, so feel free to add my Reviewed-by:

Reviewed-by: Doug Anderson <dianders at chromium.org>


From nicolas.ferre at atmel.com  Thu May 30 12:32:16 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 30 May 2013 18:32:16 +0200
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA
 DT binding
In-Reply-To: <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <51A77F10.8020808@atmel.com>

On 30/05/2013 18:08, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> For most devices the FIFO configuration is the same i.e. when half FIFO size is
> available/filled, a source/destination request is serviced. But USART devices
> have to do it when there is enough space/data available to perform a single
> AHB access so the ASAP configuration.
>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Clear and neat: thanks Ludo.

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>   .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
>   drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++++----
>   2 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
> index c80e8a3..c280a0e 100644
> --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
> @@ -24,8 +24,11 @@ The three cells in order are:
>   1. A phandle pointing to the DMA controller.
>   2. The memory interface (16 most significant bits), the peripheral interface
>   (16 less significant bits).
> -3. The peripheral identifier for the hardware handshaking interface. The
> -identifier can be different for tx and rx.
> +3. Parameters for the at91 DMA configuration register which are device
> +dependant:
> +  - bit 7-0: peripheral identifier for the hardware handshaking interface. The
> +  identifier can be different for tx and rx.
> +  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.
>
>   Example:
>
> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
> index e923cda..bfd73e1 100644
> --- a/drivers/dma/at_hdmac.c
> +++ b/drivers/dma/at_hdmac.c
> @@ -14,6 +14,7 @@
>    * found on AT91SAM9263.
>    */
>
> +#include <dt-bindings/dma/at91.h>
>   #include <linux/clk.h>
>   #include <linux/dmaengine.h>
>   #include <linux/dma-mapping.h>
> @@ -1223,14 +1224,30 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
>   	atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL);
>   	if (!atslave)
>   		return NULL;
> +
> +	atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
>   	/*
>   	 * We can fill both SRC_PER and DST_PER, one of these fields will be
>   	 * ignored depending on DMA transfer direction.
>   	 */
> -	per_id = dma_spec->args[1];
> -	atslave->cfg = ATC_FIFOCFG_HALFFIFO | ATC_DST_H2SEL_HW
> -		      | ATC_SRC_H2SEL_HW | ATC_DST_PER(per_id)
> -		      | ATC_SRC_PER(per_id);
> +	per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
> +	atslave->cfg |= ATC_DST_PER(per_id) | ATC_SRC_PER(per_id);
> +	/*
> +	 * We have to translate the value we get from the device tree since
> +	 * the half FIFO configuration value had to be 0 to keep backward
> +	 * compatibility.
> +	 */
> +	switch(dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
> +		case AT91_DMA_CFG_FIFOCFG_ALAP:
> +			atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
> +			break;
> +		case AT91_DMA_CFG_FIFOCFG_ASAP:
> +			atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
> +			break;
> +		case AT91_DMA_CFG_FIFOCFG_HALF:
> +		default:
> +			atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
> +	}
>   	atslave->dma_dev = &dmac_pdev->dev;
>
>   	chan = dma_request_channel(mask, at_dma_filter, atslave);
>


-- 
Nicolas Ferre


From plagnioj at jcrosoft.com  Thu May 30 12:37:54 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 May 2013 18:37:54 +0200
Subject: [PATCH 0/3] at_hdmac: dt dma bindings update
In-Reply-To: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20130530163754.GB23653@game.jcrosoft.org>

On 18:08 Thu 30 May     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Hi,
> 
> This set of patches update the dt dma binding for at_hdmac since we need one
> more parameter. In order to keep backward compatibility, an existing cell will
> be used to add this parameter. Since the content of that cell will become a
> magic value due to the concatenation of the two parameters, it is time to
> use macros.

For the record this is based on the cleanup branch for 3.11

Best Regards,
J.
> 
> Regards
> 
> Ludovic Desroches (3):
>   ARM: at91: dt: add header to define at_hdmac configuration
>   ARM: at91: dt: switch DMA DT bindings to pre-processor
>   at_hdmac: add FIFO configuration parameter to DMA DT binding
> 
>  .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |  5 ++--
>  arch/arm/boot/dts/at91sam9n12.dtsi                 | 11 +++++----
>  arch/arm/boot/dts/at91sam9x5.dtsi                  | 17 +++++++-------
>  arch/arm/boot/dts/sama5d3.dtsi                     | 19 +++++++--------
>  drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++----
>  include/dt-bindings/dma/at91.h                     | 27 ++++++++++++++++++++++
>  7 files changed, 81 insertions(+), 30 deletions(-)
>  create mode 100644 include/dt-bindings/dma/at91.h
> 
> -- 
> 1.7.11.3
> 


From davidb at codeaurora.org  Thu May 30 12:42:48 2013
From: davidb at codeaurora.org (David Brown)
Date: Thu, 30 May 2013 09:42:48 -0700
Subject: [PATCH 7/8] ARM: msm: use generic cpu idle function for wfi
In-Reply-To: <1369665166-13049-8-git-send-email-sanjay.rawat@linaro.org>
References: <1369665166-13049-1-git-send-email-sanjay.rawat@linaro.org>
 <1369665166-13049-8-git-send-email-sanjay.rawat@linaro.org>
Message-ID: <20130530164248.GA10404@codeaurora.org>

On Mon, May 27, 2013 at 08:02:44PM +0530, Sanjay Singh Rawat wrote:
>use cpu_do_idle for entering the wfi mode.
>
>Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
>---
> arch/arm/mach-msm/hotplug.c |    9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)

Acked-by: David Brown <davidb at codeaurora.org>

-- 
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From plagnioj at jcrosoft.com  Thu May 30 12:39:36 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 May 2013 18:39:36 +0200
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA
 DT binding
In-Reply-To: <51A77F10.8020808@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
 <51A77F10.8020808@atmel.com>
Message-ID: <20130530163936.GC23653@game.jcrosoft.org>

On 18:32 Thu 30 May     , Nicolas Ferre wrote:
> On 30/05/2013 18:08, ludovic.desroches at atmel.com :
> >From: Ludovic Desroches <ludovic.desroches at atmel.com>
> >
> >For most devices the FIFO configuration is the same i.e. when half FIFO size is
> >available/filled, a source/destination request is serviced. But USART devices
> >have to do it when there is enough space/data available to perform a single
> >AHB access so the ASAP configuration.
> >
> >Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Clear and neat: thanks Ludo.

agreed

can we apply this via AT91 as this depends on some cleanup I did on DT and
could result on some nigthmware conflict

Best Regards,
J.


From catalin.marinas at arm.com  Thu May 30 12:43:35 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 30 May 2013 17:43:35 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130529191657.GA13047@schnuecks.de>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130529110508.GH17767@MacBook-Pro.local>
 <20130529191657.GA13047@schnuecks.de>
Message-ID: <20130530164335.GK23631@arm.com>

On Wed, May 29, 2013 at 08:16:57PM +0100, Simon Baatz wrote:
> On Wed, May 29, 2013 at 12:05:09PM +0100, Catalin Marinas wrote:
> > On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > > it needs to handle are kernel mapped only.  However, for example when doing
> > > direct I/O, pages with user space mappings may occur.
> > 
> > After Nico's clarification, I think the original commit introducing this
> > function was also incomplete (commit 73be1591 - [ARM] 5545/2: add
> > flush_kernel_dcache_page() for ARM) since it ignores highmem pages and
> > their flushing could be deferred for a long time.
> 
> Yes, I agree.
>  
> > For my understanding (if I re-read this tread) - basically code like
> > this should not leave the user mapping inconsistent:
> > 
> > kmap()
> > ...
> > flush_kernel_dcache_page()
> > kunmap()
> 
> s/user mapping/kernel mapping/ 
> The user mapping(s) can be assumed to be consistent when entering
> such code. Either there is none or the page was obtained by a
> mechanism like __get_user_pages(). Otherwise, we have a problem
> anyway when accessing the page via the kernel mapping.

Indeed. What I meant was user mapping inconsistent with the kernel
mapping. It's the latter that needs flushing.

> > > Thus, continue to do lazy flushing if there are no user space mappings.
> > > Otherwise, flush the kernel cache lines directly.
> > ...
> > >  /*
> > > + * Ensure cache coherency for kernel mapping of this page.
> > > + *
> > > + * If the page only exists in the page cache and there are no user
> > > + * space mappings, this is a no-op since the page was already marked
> > > + * dirty at creation.  Otherwise, we need to flush the dirty kernel
> > > + * cache lines directly.
> > > + */
> > > +void flush_kernel_dcache_page(struct page *page)
> > > +{
> > > +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> > > +		struct address_space *mapping;
> > > +
> > > +		mapping = page_mapping(page);
> > > +
> > > +		if (!mapping || mapping_mapped(mapping))
> > > +			__flush_kernel_dcache_page(page);
> > > +	}
> > > +}
> > 
> > BTW, does the mapping check optimise anything for the
> > flush_kernel_dcache_page() uses? Would we have a mapping anyway (or
> > anonymous page) in most cases?
> 
> Looking at the relevant uses in the kernel, we have:
> 
>     drivers/scsi/libsas/sas_host_smp.c
>     drivers/mmc/host/mmc_spi.c
>     drivers/block/ps3disk.c
>     fs/exec.c
>     lib/scatterlist.c
>  
> That is not much (I omit my usual rant here that many uses of
> flush_dcache_page() in drivers are incorrect and should be uses of
> flush_kernel_dcache_page() ...).
> 
> Without looking at the actual code, we seem to have two basic use
> cases:
> 
> 1. Block drivers (the ones listed above + those using the memory
> scatterlist iterator in scatterlist.c)
> 
> These will probably almost exclusively use page cache pages for which
> we can be lazy.  Other pages only occur in special I/O situations
> like direct I/O.
> 
> 2. fs/exec.c
> 
> I think these are anonymous pages only
> 
> Thus depending on the actual drivers used, usage can be dominated by
> page cache pages on one setup and anon pages on the other.
> 
> I prefer the currently proposed way since it prevents massive
> overflushing if flush_kernel_dcache_page() is used in an I/O path.
> 
> (Btw. I am still puzzled as to why making flush_kernel_dcache_page()
> the current nop apparently did not cause problems in fs/exec.c.)

We get extra flushing via flush_old_exec() -> exec_mmap() -> mmput() ->
exit_mmap() -> flush_cache_mm() before we actually start the new exec so
this would flush the arg page as well.

> > Otherwise the patch looks good.
> 
> Thanks. Especially, thanks for pointing out the highmem case.

You can add my ack (before I forget the whole discussion ;))

Acked-by: Catalin Marinas <catalin.marinas at arm.com>


From dianders at chromium.org  Thu May 30 12:50:53 2013
From: dianders at chromium.org (Doug Anderson)
Date: Thu, 30 May 2013 09:50:53 -0700
Subject: [PATCH v2 4/5] clk: samsung: Add set_rate() clk_ops for PLL36xx
In-Reply-To: <1369834677-20312-5-git-send-email-vikas.sajjan@linaro.org>
References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org>
 <1369834677-20312-5-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=X3FEyzzOhKoLo882iTiAjwDO5tYxfLLEHDmHc5v-1fJA@mail.gmail.com>

Vikas / Yadwinder,

On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> This patch adds set_rate and round_rate clk_ops for PLL36xx
>
> Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
> ---
>  drivers/clk/samsung/clk-pll.c |   59 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)

Looks good to me.  I one nit on space/vs tab after
PLL36XX_LOCK_STAT_SHIFT that would be nice to fix, but not major.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From catalin.marinas at arm.com  Thu May 30 12:56:21 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 30 May 2013 17:56:21 +0100
Subject: Single zImage and A15/LPAE
In-Reply-To: <201305292351.41096.arnd@arndb.de>
References: <50735B75.8070109@wwwdotorg.org> <2274563.opVbLLPT1p@wuerfel>
 <20130529151555.GP17767@MacBook-Pro.local>
 <201305292351.41096.arnd@arndb.de>
Message-ID: <20130530165621.GL23631@arm.com>

On Wed, May 29, 2013 at 10:51:40PM +0100, Arnd Bergmann wrote:
> On Wednesday 29 May 2013, Catalin Marinas wrote:
> > > I think to do this right, we need to treat ARMv7+LPAE as a separate
> > > architecture level, just like we treat ARMv6, ARMv7 as separate
> > > compatible architectures. BTW, is there an official name for that
> > > architecture?
> > 
> > The official is Large Physical Address Extension which is an extension
> > to ARMv7, so not a new architecture.
> 
> Ah, too bad. I had hoped there were still postfixes like v6K or v4T.
> I guess there is no complete list of ARMv7 extensions anywhere, right?

It's the ARM ARM, though not a list. With ARMv7 we moved away from
adding suffixes to the architecture number and introduced the CPUID
scheme to check for what's available on a CPU.

-- 
Catalin


From plagnioj at jcrosoft.com  Thu May 30 12:54:53 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 May 2013 18:54:53 +0200
Subject: [PATCH v2 2/4] mtd: atmel_nand: add Nand Flash Controller
 (NFC) support
In-Reply-To: <51A6EE46.6050701@atmel.com>
References: <1368784308-7600-1-git-send-email-josh.wu@atmel.com>
 <1368784308-7600-3-git-send-email-josh.wu@atmel.com>
 <20130524200947.GM24476@game.jcrosoft.org>
 <51A32DD2.9040707@atmel.com>
 <20130527102603.GR24476@game.jcrosoft.org>
 <51A6EE46.6050701@atmel.com>
Message-ID: <20130530165453.GD23653@game.jcrosoft.org>

On 14:14 Thu 30 May     , Josh Wu wrote:
> Hi, JC
> 
> On 5/27/2013 6:26 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> [snip]
> 
> >>>yes but you need to update the compatible or check the IP support it too
> >>>as has-nfc will mean I have the nfs on the hardware but not enable it
> >>>
> >>>the SoC dtsi will describe you have it but the board will decide to enable it or
> >>>not
> >>I can add some code to check whether is NFC supported by read SMC IP
> >>version. But I'm afraid
> >>such code may not work for AVR arch.
> >>
> >>Another way is just add a 'enable-nfc' compatible string. Which is
> >>for board to enable the NFC feature.
> >>
> >>I'm prefer to the later one. What do you think?
> >I do not like no 2
> >
> >I like this
> >
> >		nand0: nand at 60000000 {
> >			compatible = "atmel,at91rm9200-nand";
> >			#address-cells = <1>;
> >			#size-cells = <1>;
> >			reg = < 0x60000000 0x01000000   /* EBI CS3 */
> >				0xffffc070 0x00000490   /* SMC PMECC regs */
> >				0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
> >				0x00100000 0x00100000   /* ROM code */
> >				>;
> >			interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
> >			atmel,nand-addr-offset = <21>;
> >			atmel,nand-cmd-offset = <22>;
> >			pinctrl-names = "default";
> >			pinctrl-0 = <&pinctrl_nand0_ale_cle>;
> >			atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
> >			status = "disabled";
> >
> >			nfc at 70000000 {
> >				compatible = "atmel,sama5d3-nfc";
> >				reg = < 0x70000000 0x10000000   /* NFC Command Registers */
> >					0xffffc000 0x00000070   /* NFC HSMC regs */
> >					0x00200000 0x00100000   /* NFC SRAM banks */
> >				>;
> >			}
> >		};
> >
> >so you can enable/disable it easly
> 
> Since I am not use such dts definition before, following is my guest
> implementation for above dts:
> So I need define an additional platform driver for
> "atmel,sama5d3-nfc" with probe/remove function. right?

give one day for thisI need to check something on the hardware features
> if yes, then there are two question are rise out:
> 1. which driver will be probed first? or it is depends? Since I
> think the "atmel,sama5d3-nfc" can be probe first is good for me.
> 2. how do these two drivers share data with others? I check at91
> pinctrl as a example, and it use a static pointer array store gpio
> data, and pinctrl can access it. Seems that is enough for me.

no the pinctrl is a special case as both drivers use the same registers
to handle the pinctrl and gpio

Best Regards,
J.
> 
> >
> >
> >>>>  Examples:
> >>>>  nand0: nand at 40000000,0 {
> >>>>diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> >>>>index f747791..48d7ee6 100644
> >>>>--- a/drivers/mtd/nand/atmel_nand.c
> >>>>+++ b/drivers/mtd/nand/atmel_nand.c
> >>>>@@ -18,6 +18,9 @@
> >>>>   *  Add Programmable Multibit ECC support for various AT91 SoC
> >>>>   *     ? Copyright 2012 ATMEL, Hong Xu
> >>>>   *
> >>>>+ *  Add Nand Flash Controller support for SAMA5 SoC
> >>>>+ *     ? Copyright 2013 ATMEL, Josh Wu (josh.wu at atmel.com)
> >>>>+ *
> >>>>   * This program is free software; you can redistribute it and/or modify
> >>>>   * it under the terms of the GNU General Public License version 2 as
> >>>>   * published by the Free Software Foundation.
> >>>>@@ -37,9 +40,11 @@
> >>>>  #include <linux/mtd/nand.h>
> >>>>  #include <linux/mtd/partitions.h>
> >>>>+#include <linux/delay.h>
> >>>>  #include <linux/dmaengine.h>
> >>>>  #include <linux/gpio.h>
> >>>>  #include <linux/io.h>
> >>>>+#include <linux/interrupt.h>
> >>>>  #include <linux/platform_data/atmel.h>
> >>>>  #include <linux/pinctrl/consumer.h>
> >>>>@@ -58,6 +63,7 @@ module_param(on_flash_bbt, int, 0);
> >>>>  	__raw_writel((value), add + ATMEL_ECC_##reg)
> >>>>  #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
> >>>>+#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
> >>>>  /* oob layout for large page size
> >>>>   * bad block info is on bytes 0 and 1
> >>>>@@ -85,6 +91,13 @@ static struct nand_ecclayout atmel_oobinfo_small = {
> >>>>  	},
> >>>>  };
> >....
> >>>>+				dev_err(&pdev->dev,
> >>>>+					"can't request input direction rdy gpio %d\n",
> >>>>+					host->board.rdy_pin);
> >>>>+				goto err_ecc_ioremap;
> >>>>+			}
> >>>>+
> >>>>+			nand_chip->dev_ready = atmel_nand_device_ready;
> >>>>  		}
> >>>>-		res = gpio_direction_output(host->board.enable_pin, 1);
> >>>>-		if (res < 0) {
> >>>>-			dev_err(&pdev->dev,
> >>>>-				"can't request output direction enable gpio %d\n",
> >>>>-				host->board.enable_pin);
> >>>>-			goto err_ecc_ioremap;
> >>>>+		if (gpio_is_valid(host->board.enable_pin)) {
> >>>>+			res = gpio_request(host->board.enable_pin,
> >>>we need to use devm_ here too
> >>>and everywhere we can in this driver
> >>yes, but seems you already sent one patch to use devm_ for this driver.
> >>https://patchwork.kernel.org/patch/1589071/
> >>It is not merged in at91 tree yet.
> >>
> >>So what do you think if I put that patch rebased and put it as one
> >>of this NFC series patches?
> >yes do so
> 
> ok. I will rebase the patch and including it with nfc patches.
> 
> Best Regards,
> Josh Wu
> 
> >
> >Best Regards,
> >J.
> 


From stern at rowland.harvard.edu  Thu May 30 13:23:26 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 30 May 2013 13:23:26 -0400 (EDT)
Subject: [RFC PATCH 1/2] USB: OHCI: make ohci-platform a separate driver
In-Reply-To: <1369907454-11003-2-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305301321340.1137-100000@iolanthe.rowland.org>

On Thu, 30 May 2013, Manjunath Goudar wrote:

> This patch splits the ohci-platform code from ohci-hcd out
> into its own separate driver module.This work is part of enabling
> multi-platform kernels on ARM.

Okay, except...

> +static const struct ohci_driver_overrides platform_overrides = {
> +	.product_desc =	"Generic Platform EHCI controller",
> +	.reset =	ohci_platform_reset,
>  };

Don't forget the __initconst annotation.  After that is fixed, you can 
add my Acked-by.

Alan Stern



From stern at rowland.harvard.edu  Thu May 30 13:26:26 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 30 May 2013 13:26:26 -0400 (EDT)
Subject: [RFC PATCH 2/2] USB: OHCI: add a name for the platform-private
 field
In-Reply-To: <1369907454-11003-3-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <Pine.LNX.4.44L0.1305301323300.1137-100000@iolanthe.rowland.org>

On Thu, 30 May 2013, Manjunath Goudar wrote:

> This patch adds an ohci->priv field for private use by OHCI
> platform drivers.
> 
> Until now none of the platform drivers has used this private space,
> but that's about to change in the next patch of this series.

As far as I'm concerned, this doesn't need to be in a patch of its own.  
It can be merged into the 1/3 patch of the previous series.  After all,
that patch adds the extra_priv_size field in ohci_driver_overrides,
which doesn't make much sense unless there's a way to refer to the
private part of the ohci_hcd structure.

Alan Stern




From sergei.shtylyov at cogentembedded.com  Thu May 30 13:28:05 2013
From: sergei.shtylyov at cogentembedded.com (Sergei Shtylyov)
Date: Thu, 30 May 2013 21:28:05 +0400
Subject: [RFC PATCH 1/2] USB: OHCI: make ohci-platform a separate driver
In-Reply-To: <Pine.LNX.4.44L0.1305301321340.1137-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305301321340.1137-100000@iolanthe.rowland.org>
Message-ID: <51A78C25.1050500@cogentembedded.com>

Hello.

On 05/30/2013 09:23 PM, Alan Stern wrote:

>
>> This patch splits the ohci-platform code from ohci-hcd out
>> into its own separate driver module.This work is part of enabling
>> multi-platform kernels on ARM.
> Okay, except...
>
>> +static const struct ohci_driver_overrides platform_overrides = {
>> +	.product_desc =	"Generic Platform EHCI controller",

     Maybe "OHCI"? :-)

> Alan Stern

WBR, Sergei



From linus.walleij at linaro.org  Thu May 30 13:38:12 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 19:38:12 +0200
Subject: [RFC/PATCH v2 2/2] gpio-rcar: Add DT support
In-Reply-To: <1369136406-23800-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369136406-23800-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Message-ID: <CACRpkdb8GYpx3ASzXB7HX5oEpAUBe-yBo0N5Ep9S+DqoE6oCLw@mail.gmail.com>

On Tue, May 21, 2013 at 1:40 PM, Laurent Pinchart
<laurent.pinchart+renesas at ideasonboard.com> wrote:

> Add DT bindings for the gpio-rcar driver and read the device
> configuration from the DT node at probe time if available.
>
> Cc: devicetree-discuss at lists.ozlabs.org
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

I am assuming this will go through Simon's tree?

Note:

> +  - gpio-ranges: Range of pins managed by the GPIO controller as a 4-cells
> +    tuple using the following syntax.
> +
> +    <[phandle of the pin controller node]
> +     0
> +     [index of the first pin]
> +     [number of pins]>
> +
> +Please refer to gpio.txt in this directory for details of the common GPIO
> +bindings used by client devices.

The above ranges are part of that document.

Yours,
Linus Walleij


From jagarwal at nvidia.com  Thu May 30 13:37:57 2013
From: jagarwal at nvidia.com (Jay Agarwal)
Date: Thu, 30 May 2013 23:07:57 +0530
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <51A62042.7070304@wwwdotorg.org>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B616BE9B@BGMAIL01.nvidia.com>
 <51A62042.7070304@wwwdotorg.org>
Message-ID: <C79B248886DD134989C8FF6B096A91AB91B616BEA6@BGMAIL01.nvidia.com>

> On 05/29/2013 04:10 AM, Jay Agarwal wrote:
> >>>> So, if I apply this series, I do see the PCIe bridge and Ethernet
> >>>> device get enumerated, but I don't see the USB3 controller get
> >>>> enumerated. I believe that is a PCIe device behind the same bridge
> >>>> on the
> >>> same Tegra PCIe port.
> >>>> Shouldn't this device show up?
> >>> I have also reproduced this problem. I see somehow no non-
> >>> prefetchable memory is assigned to any of pcie devices.
> >>> Probably that is the reason for USB3 (pci 0000:04:00.0) not getting
> >>> enumerated since it uses only non-prefetchable memory.
> >>
> >> 1. Bus4(on which usb3 device resides) always return 0xffffffff from
> >> it's config space. which means device is not present?
> >> 2. That's why it is not assigned any resources and hence no usb3
> >> probe happens.
> >> 3. But same bus does return valid info like vendor/device id etc from
> >> it's config space in downstream kernel and hence usb3 probe does
> happen.
> >>
> >> Thierry, Stephen,
> >> 4. Any idea why bus4 should return 0xffffffff values in upstream kernel?
> >> Anything missing?
> >> 5. Also, how config space of all pcie devices are mapped? I mean if I
> >> change the config space offset in dts file, then also I find correct
> >> vendor/device id etc for bus0/device0/fun0.
> >>     So how this mapping happens that even after changing the config
> >> space offset in PCIe address space, it always finds correct vendor/device
> id.
> >
> >  Any idea on this?
> 
> I did already reply the same day you sent the original email. My response
> was:
> 
> Is there some reset/enable GPIO or regulator that needs to be programmed
> to enable the PCIe USB3 controller? Take a look at the schematic. If you can
> make it work by tweaking those GPIOs/... manually, then we can ignore this
> issue and fix it up later, since it's not directly related to the PCIe controller
> driver patches. It's more important to get the Ethernet working than USB, I
> think.
> 
> To be honest though, I would expect you to be asking around inside NVIDIA
> to determine the answer here. As the PCIe SW expert, I'd expect you to
> drive this process. Try asking the Cardhu board and PCIe HW experts within
> NVIDIA.
> 
> Did you make any progress on the issues with the Ethernet device?

Stephen, 
I have taken care of all your comments, but Ethernet device is not working for me neither on cardhu nor harmony. 
Could be related to my process or board, Currently debugging this.
Parallely, should I push my patches for review so that it is clear from other aspects?
 


From richard.genoud at gmail.com  Thu May 30 13:50:24 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Thu, 30 May 2013 19:50:24 +0200
Subject: [PATCHv3 RESEND 0/6] ARM: sunxi: Add support for A10 Ethernet
 controller
In-Reply-To: <20130530081129.GF9799@lukather>
References: <1369387394-9453-1-git-send-email-maxime.ripard@free-electrons.com>
 <CACQ1gAgp6o8HqQcv=4cWoAZze3wtXHMX+g+7KvV-pnC2W5=iyg@mail.gmail.com>
 <20130530081129.GF9799@lukather>
Message-ID: <CACQ1gAhu0P0BvfNkhsSgdzeU7Pf+CxesVJ87ok2FMpfBmaRMXA@mail.gmail.com>

2013/5/30 Maxime Ripard <maxime.ripard at free-electrons.com>:
>
> Did you look at the load while iperf was running? I guess we can expect
> it to be pretty high since it runs without DMA.

I just did the test.
cpu is at 55%-60%

root at debian:~# date ; iperf -c 192.168.1.10 -t 300 ; cat /proc/loadavg
Thu May 30 17:43:13 UTC 2013
------------------------------------------------------------
Client connecting to 192.168.1.10, TCP port 5001
TCP window size: 20.0 KByte (default)
------------------------------------------------------------
[  3] local 192.168.1.235 port 45459 connected with 192.168.1.10 port 5001
[ ID] Interval       Transfer     Bandwidth
[  3]  0.0-300.0 sec  3.28 GBytes  94.0 Mbits/sec
0.83 0.71 0.43 1/46 1770

loadavg over a 5min at 0.71, yeah, that's pretty high...

Richard.


From swarren at wwwdotorg.org  Thu May 30 14:04:20 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 30 May 2013 12:04:20 -0600
Subject: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu
In-Reply-To: <C79B248886DD134989C8FF6B096A91AB91B616BEA6@BGMAIL01.nvidia.com>
References: <1368010660-31465-1-git-send-email-jagarwal@nvidia.com>
 <1368010660-31465-4-git-send-email-jagarwal@nvidia.com>
 <518A8596.7070702@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B4886B5D@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B4886B6C@BGMAIL01.nvidia.com>
 <C79B248886DD134989C8FF6B096A91AB91B616BE9B@BGMAIL01.nvidia.com>
 <51A62042.7070304@wwwdotorg.org>
 <C79B248886DD134989C8FF6B096A91AB91B616BEA6@BGMAIL01.nvidia.com>
Message-ID: <51A794A4.1010502@wwwdotorg.org>

On 05/30/2013 11:37 AM, Jay Agarwal wrote:
...
> I have taken care of all your comments, but Ethernet device is not working for me neither on cardhu nor harmony. 
> Could be related to my process or board, Currently debugging this.

Are you talking about a PCIe-based Ethernet device on Harmony, or the
one that's built into the board?

The on-board Ethernet device is USB, and should work fine already, and
irrespective of any PCIe patches.

I have only tried an XHCI USB controller in the PCIe slot on Harmony, so
I can't say if Ethernet not working is a regression or not. Does the
Ethernet device work with just Thierry's patches and not yours?

> Parallely, should I push my patches for review so that it is clear from other aspects?

Well, if the patches don't work, I suppose there's not much use posting
them since they'll just need changes before they can be usefully applied
anyway. IIRC, most of my comments last time were fairly minor, so there
isn't much need for a separate review of them, right?


From linus.walleij at linaro.org  Thu May 30 14:04:40 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:04:40 +0200
Subject: [PATCH 00/11] Convert GPIO Davinci to platform driver
In-Reply-To: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdbJY1mZWzFUqWmUR_C8wjis0xtXLOGYNZB9ewqBuxcd5A@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> GPIO Davinci driver converted to platform driver to support DT booting.
> In this patch series
> - Cleaned gpio Davinci driver code with proper commenting style and appropriate
>   variable names.
> - Create platform driver for GPIO Davinci in da8xx and dm* platforms and removed
>   gpio related member updation in davinci_soc_info structure.
> - DT support added for da850 board and tested on da850 EVM.
> - Remove soc_info reference in the gpio davinci driver and start uses
>   gpiolib interface.

I'll go over and review this. I assume this will then go through
some DaVinci tree and up into ARM SoC when/if I ACK it.

Yours,
Linus Walleij


From vinod.koul at intel.com  Thu May 30 13:26:49 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 30 May 2013 22:56:49 +0530
Subject: [PATCH 0/3] at_hdmac: dt dma bindings update
In-Reply-To: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20130530172649.GC3767@intel.com>

On Thu, May 30, 2013 at 06:08:20PM +0200, ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Hi,
> 
> This set of patches update the dt dma binding for at_hdmac since we need one
> more parameter. In order to keep backward compatibility, an existing cell will
> be used to add this parameter. Since the content of that cell will become a
> magic value due to the concatenation of the two parameters, it is time to
> use macros.
which tree is this targetted to be applied? 

Arnd, can you review this series and ack if this needs to be applied thru
dmaengine?

--
~Vinod
> 
> Regards
> 
> Ludovic Desroches (3):
>   ARM: at91: dt: add header to define at_hdmac configuration
>   ARM: at91: dt: switch DMA DT bindings to pre-processor
>   at_hdmac: add FIFO configuration parameter to DMA DT binding
> 
>  .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |  5 ++--
>  arch/arm/boot/dts/at91sam9n12.dtsi                 | 11 +++++----
>  arch/arm/boot/dts/at91sam9x5.dtsi                  | 17 +++++++-------
>  arch/arm/boot/dts/sama5d3.dtsi                     | 19 +++++++--------
>  drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++----
>  include/dt-bindings/dma/at91.h                     | 27 ++++++++++++++++++++++
>  7 files changed, 81 insertions(+), 30 deletions(-)
>  create mode 100644 include/dt-bindings/dma/at91.h
> 
> -- 
> 1.7.11.3
> 

-- 


From linus.walleij at linaro.org  Thu May 30 14:06:00 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:06:00 +0200
Subject: [PATCH 01/11] ARM: davinci: GPIO: Add platform data structure
In-Reply-To: <1369206634-6778-2-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-2-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdbVY+ogiLK-WtwmPJORcwheSTHwq86uPwUB0PYxQ+=oCA@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> From: KV Sujith <sujithkv at ti.com>
>
> Add struct davinci_gpio_platform_data davinci gpio module.
>
> Signed-off-by: KV Sujith <sujithkv at ti.com>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Usually I squash such patches into the first patch making use of it,
but the spirit is good so:

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From vinod.koul at intel.com  Thu May 30 13:33:26 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 30 May 2013 23:03:26 +0530
Subject: [PATCH -next v2] dmaengine: ste_dma40: fix error return code
 in d40_probe()
In-Reply-To: <CACRpkdYBfvr0kA7bd-6Ns78UH7JtBCFDzFxyHLgtReB32O4D+w@mail.gmail.com>
References: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>
 <CACRpkdYBfvr0kA7bd-6Ns78UH7JtBCFDzFxyHLgtReB32O4D+w@mail.gmail.com>
Message-ID: <20130530173326.GD3767@intel.com>

On Thu, May 30, 2013 at 09:41:38AM +0200, Linus Walleij wrote:
> On Thu, May 30, 2013 at 6:32 AM, Wei Yongjun <weiyj.lk at gmail.com> wrote:
> 
> > From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> >
> > In many of the error handling case, the return value 'ret' not set
> > and 0 will be return from d40_probe() even if error, but we should
> > return a negative error code instead in those error handling case.
> > This patch fixed them, and also removed useless variable 'err'.
> >
> > Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> > ---
> > v1 -> v2: rebased on linux-next.git
> 
> I've tentatively applied this to my dma40 branch, waiting for Vinod
> to ACK it.
I though you wanted me to apply this :)

Nevertheless, Acked-by: Vinod Koul <vinod.koul at intel.com>

Can you CC stable too, pls.

--
~Vinod

-- 


From linus.walleij at linaro.org  Thu May 30 14:12:26 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:12:26 +0200
Subject: [PATCH 03/11] gpio: davinci: Modify to platform driver
In-Reply-To: <1369206634-6778-4-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-4-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdb9vW6Jo0T+boW0hkF6AuRNb72MgFSgwzctO=U_4XB3Yg@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

Why not squash patch 1 into this patch?

Anyway, this bring us closer to the model of other drivers so:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 14:14:06 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:14:06 +0200
Subject: [PATCH 04/11] ARM: davinci: da8xx: creation of gpio platform
 device
In-Reply-To: <1369206634-6778-5-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-5-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdaKjfyJWbr3HjHWCeFPeg0mrwDZ+G7Fn_y8Z_PGg2JM2A@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> From: KV Sujith <sujithkv at ti.com>
>
> gpio controller resource information being associated with
> davinci_soc_info structure and not created any device. Hence davinci
> gpio didn't fall under proper device model. This patch creates gpio
> davinci as a platform device for da8xx platforms.
>
> - Add Memory and IRQ resources for DA8xx.
> - Register GPIO platform driver for DA8xx.
> - Add da8xx_register_gpio API to create platform device for da8xx
>   platforms.
>
> Signed-off-by: KV Sujith <sujithkv at ti.com>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From bhelgaas at google.com  Thu May 30 14:13:53 2013
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Thu, 30 May 2013 12:13:53 -0600
Subject: [RFCv1 09/11] pci: mvebu: add MSI support
In-Reply-To: <20130530121518.GA20267@mithrandir>
References: <1364316746-8702-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1364316746-8702-10-git-send-email-thomas.petazzoni@free-electrons.com>
 <CAErSpo7yC_97Vg-zuype-jyfqiY+77OE97cxYoEO9ZZnXjQ95A@mail.gmail.com>
 <20130530121518.GA20267@mithrandir>
Message-ID: <CAErSpo7P-fs_C+Eoc1ppyWz=rGrw4idcziRf9s=h0OsxVqJhLg@mail.gmail.com>

On Thu, May 30, 2013 at 6:15 AM, Thierry Reding
<thierry.reding at gmail.com> wrote:
> On Mon, Apr 08, 2013 at 04:29:07PM -0600, Bjorn Helgaas wrote:
>> On Tue, Mar 26, 2013 at 10:52 AM, Thomas Petazzoni <thomas.petazzoni at free-electrons.com> wrote:
> [...]
>> > +static int mvebu_pcie_setup_msi_irq(struct msi_chip *chip,
>> > +                                   struct pci_dev *pdev,
>> > +                                   struct msi_desc *desc)
>> > +{
>> > +       struct mvebu_pcie_msi *msi = to_mvebu_msi(chip);
>>
>> If this took only the pci_dev (not the msi_chip), I think you could do this:
>>
>>   struct mvebu_pcie_msi *msi = &pdev->bus->sysdata->msi;
>
> That would mean that the arch_setup_msi_irq() and friends could still be
> architecture-agnostic because they only pass around pci_dev, and the
> driver specific implementations would know how to lookup sysdata and
> from there the MSI chip.
>
> So I was almost convinced that putting the struct msi_chip pointer into
> sysdata is a good idea. However that also means that each PCI host
> bridge driver becomes architecture-specific. If we ever get a driver
> that can be used on multiple architectures (however unlikely), the only
> way to make it work would be to #ifdef those parts. We could make that
> easier to deal with by providing an accessor (pci_sysdata_set_msi_chip()
> or similar), though.
>
> But maybe it's something we don't need to be concerned about because no
> PCI host bridge driver will ever support two different architecture?
>
> One related point is compile coverage. If the drivers are completely
> architecture-agnostic it makes it a lot easier to compile-test all
> drivers, which might come in useful when doing core changes and such.

Hmm, I've forgotten what I was thinking here.  (And I'm the *worst*
about reviving ancient threads myself).  So I drop whatever objection
I had :)

Bjorn


From linus.walleij at linaro.org  Thu May 30 14:15:28 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:15:28 +0200
Subject: [PATCH 05/11] ARM: davinci: creation of gpio platform device for
 dm platforms
In-Reply-To: <1369206634-6778-6-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-6-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdavLhkJ2Osa-SHp_ekxGu-gtJ7AKTXuOHHZr1Z4BUEawQ@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> gpio controller resource information being associated with
> davinci_soc_info structure and not created any device. Hence davinci
> gpio didn't fall under proper device model. This patch creates gpio
> davinci as a platform device for dm platforms.
> Also add daivinci_register_gpio API to create platform device for dm*
> platforms.
>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 14:16:24 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:16:24 +0200
Subject: [PATCH 06/11] ARM: davinci: da8xx: gpio device creation
In-Reply-To: <1369206634-6778-7-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-7-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdYq3RshsEvW2tuzD=NHuF8FcTb9Ss7XK7N=NnmTMi+WLw@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> Create davinci gpio device and remove references in davinci_soc_info
> structure. Also rearrange header file inclusion in group basis.
>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 14:16:55 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:16:55 +0200
Subject: [PATCH 07/11] ARM: davinci: create davinci gpio device for dm
 platforms
In-Reply-To: <1369206634-6778-8-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-8-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdbvQ1j0ooC5Qmt3TPZf7VVxHQuQ1Wp8SEQjsxoYUo2BYQ@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 14:19:01 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:19:01 +0200
Subject: [PATCH 08/11] ARM: davinci: start using gpiolib support
In-Reply-To: <1369206634-6778-9-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-9-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdauO5Tgkec-g5N85+M2AejUmvF+rO-5V7Yc5vKUMNpm4A@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> - Remove NEED_MACH_GPIO_H config option for Davinci platforms to start
>   using common gpio library interface.
> - Added struct davinci_gpio_controller definitions in platform_data
>   directory for Davinci gpio devices.
> - Removed GPIO_TYPE_DAVINCI enum definition as GPIO Davinci is converted
>   to Linux device driver model.
>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

> +/* Convert GPIO signal to GPIO pin number */
> +#define GPIO_TO_PIN(bank, gpio)        (16 * (bank) + (gpio))

Hm not synonymous with pinctrl pins, well I guess I have to live
with this...

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 14:25:22 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:25:22 +0200
Subject: [PATCH 09/11] gpio: davinci: DT changes for driver
In-Reply-To: <1369206634-6778-10-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-10-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdZH4w_-K617QNCo0Z9jH7LKQyjzoG9K-dj4UbN3h5Bcxw@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

(...)
> +- interrupts: The Starting IRQ number for GPIO
> +- intc_irq_num: The number of IRQs supported by the Interrupt Controller
(...)

No this is not how you pass a number of IRQs in the device tree.

"interrupts" is an array. Pass every interrupt here for a full
resolution of the IRQs.

Further this looks fishy:

+ interrupts = <42>;

Usually you pass flags with the IRQs, I would rather have expected
an array like this:

interrupts = < 90 0x4 96 0x4 14 0x4 15 0x4 79 0x4>;

0x4 is IRQ_TYPE_LEVEL_HIGH, you can use the dts
#include <dt-bindings/interrupt-controller/irq.h> and
define that symbolically.

Doesn't the DaVinci IRQ controller support *any* IRQ flags?

Since the driver code is not reading out the interrupts but
(I guess?) falling back to platform data IRQ assignment,
this seems wrong.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 14:26:44 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 20:26:44 +0200
Subject: [PATCH 11/11] ARM: davinci: da850 evm: add GPIO DT data
In-Reply-To: <1369206634-6778-12-git-send-email-avinashphilip@ti.com>
References: <1369206634-6778-1-git-send-email-avinashphilip@ti.com>
 <1369206634-6778-12-git-send-email-avinashphilip@ti.com>
Message-ID: <CACRpkdYOGj9SQepDyv3hCSXkQugNb_cwb3+KY0vixEZ7PT-nOg@mail.gmail.com>

On Wed, May 22, 2013 at 9:10 AM, Philip Avinash <avinashphilip at ti.com> wrote:

> From: KV Sujith <sujithkv at ti.com>
>
> - Add GPIO DT Data and pinmux for DA850 EVM. GPIO is configurable differently
>   on different boards. So add GPIO pinmuxing in dts file.
> - Dependency: This patch is dependent on Grab-pin-control patch;
>   https://patchwork.kernel.org/patch/2013751/
>
> Signed-off-by: KV Sujith <sujithkv at ti.com>
> Signed-off-by: Philip Avinash <avinashphilip at ti.com>

Looks fine to me, but Tony should review this.

Yours,
Linus Walleij


From andy.shevchenko at gmail.com  Thu May 30 14:29:16 2013
From: andy.shevchenko at gmail.com (Andy Shevchenko)
Date: Thu, 30 May 2013 21:29:16 +0300
Subject: [PATCH -next v2] dmaengine: ste_dma40: fix error return code in
 d40_probe()
In-Reply-To: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>
References: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>
Message-ID: <CAHp75Vf+ifmn62vRNZbqpVX1hnqeUkenzvY81gZLenFkEJ9pFA@mail.gmail.com>

On Thu, May 30, 2013 at 7:32 AM, Wei Yongjun <weiyj.lk at gmail.com> wrote:
> In many of the error handling case, the return value 'ret' not set
> and 0 will be return from d40_probe() even if error, but we should
> return a negative error code instead in those error handling case.
> This patch fixed them, and also removed useless variable 'err'.

Hold on, please.

> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c

> @@ -3619,6 +3618,7 @@ static int __init d40_probe(struct platform_device *pdev)
>                 if (IS_ERR(base->lcpa_regulator)) {
>                         d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
>                         base->lcpa_regulator = NULL;
> +                       ret = PTR_ERR(base->lcpa_regulator);

Is it really what we want?

I thixh you may remove that NULL assignment.


>                         goto failure;
>                 }
>

> @@ -3647,8 +3647,8 @@ static int __init d40_probe(struct platform_device *pdev)
>         d40_hw_init(base);
>
>         if (np) {
> -               err = of_dma_controller_register(np, d40_xlate, NULL);
> -               if (err && err != -ENODEV)
> +               ret = of_dma_controller_register(np, d40_xlate, NULL);
> +               if (ret && ret != -ENODEV)

>From the discussion of dw_dmac I remember we decide that ENODEV check
is redundant.

--
With Best Regards,
Andy Shevchenko


From vinod.koul at intel.com  Thu May 30 13:56:09 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 30 May 2013 23:26:09 +0530
Subject: [PATCH 35/39] dmaengine: ste_dma40_ll: Replace meaningless
 register set with comment
In-Reply-To: <CACRpkdbXVd7k9rzb-OKUmnW_9J+jWYhz=AjO09_Ymvd2_DOVcQ@mail.gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-36-git-send-email-lee.jones@linaro.org>
 <CACRpkdbXVd7k9rzb-OKUmnW_9J+jWYhz=AjO09_Ymvd2_DOVcQ@mail.gmail.com>
Message-ID: <20130530175609.GF3767@intel.com>

On Thu, May 30, 2013 at 11:04:23AM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > Unsure of the author's intentions, rather than just removing the nop,
> > we're replacing it with a comment containing the possible intention
> > of the statement OR:ing with 0.
> >
> > Cc: Vinod Koul <vinod.koul at intel.com>
> > Cc: Dan Williams <djbw at fb.com>
> > Cc: Per Forlin <per.forlin at stericsson.com>
> > Cc: Rabin Vincent <rabin at rab.in>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Tentatively applied. Missing Vinod's ACK.
Acked-by: Vinod Koul <vinod.koul at intel.com>

--
~Vinod


From mturquette at linaro.org  Thu May 30 14:44:43 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 11:44:43 -0700
Subject: [PATCH v2 0/5] Zynq: revised CCF code
In-Reply-To: <51961F37.3030202@monstr.eu>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
 <51961F37.3030202@monstr.eu>
Message-ID: <20130530184443.4470.73215@quantum>

Quoting Michal Simek (2013-05-17 05:14:47)
> Hi Mike,
> 
> I have sent email to Greg to take this patch from this series
> though his serial tree because it is unrelated to this clock stuff.
> 
> Can you please give me your ACK for these patches or add them
> to your CLK tree?
> 

For the four clock-related patches:

Acked-by: Mike Turquette <mturquette at linaro.org>

Regards,
Mike

> I just need to move this to be able to start to push other drivers
> which are related to this.
> 
> Thanks,
> Michal
> 
> 
> On 05/13/2013 07:46 PM, Soren Brinkmann wrote:
> > I rebased this series on v3.10-rc1 eliminating all dependencies and incorporated
> > Greg's feedback.
> > I'll push this also to my github repository.
> > https://github.com/sorenb-xlnx/linux-xlnx/tree/zynq/clkc
> > 
> > v2:
> >  - dropped the 'sort #includes' patches
> > 
> >       S?ren
> > 
> > 
> > Soren Brinkmann (5):
> >   tty: xuartps: Remove suspend/resume functions
> >   clk: zynq: Factor out PLL driver
> >   clk: zynq: Add clock controller driver
> >   arm: zynq: Migrate platform to clock controller
> >   clk: zynq: Remove deprecated clock code
> > 
> >  .../devicetree/bindings/clock/zynq-7000.txt        | 127 +++--
> >  arch/arm/boot/dts/zynq-7000.dtsi                   |  71 +--
> >  arch/arm/boot/dts/zynq-zc702.dts                   |   4 -
> >  arch/arm/mach-zynq/slcr.c                          |   2 +-
> >  drivers/clk/Makefile                               |   2 +-
> >  drivers/clk/clk-zynq.c                             | 378 ---------------
> >  drivers/clk/zynq/Makefile                          |   3 +
> >  drivers/clk/zynq/clkc.c                            | 533 +++++++++++++++++++++
> >  drivers/clk/zynq/pll.c                             | 235 +++++++++
> >  drivers/clocksource/cadence_ttc_timer.c            |  23 +-
> >  drivers/tty/serial/xilinx_uartps.c                 | 115 +++--
> >  include/linux/clk/zynq.h                           |   8 +-
> >  12 files changed, 974 insertions(+), 527 deletions(-)
> >  delete mode 100644 drivers/clk/clk-zynq.c
> >  create mode 100644 drivers/clk/zynq/Makefile
> >  create mode 100644 drivers/clk/zynq/clkc.c
> >  create mode 100644 drivers/clk/zynq/pll.c
> > 
> 
> 
> -- 
> Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
> w: www.monstr.eu p: +42-0-721842854
> Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
> Maintainer of Linux kernel - Xilinx Zynq ARM architecture
> Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


From vinod.koul at intel.com  Thu May 30 14:15:57 2013
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 30 May 2013 23:45:57 +0530
Subject: [PATCH] dmaengine: sirf: set dma residue based on the current
 dma transfer position
In-Reply-To: <1368543800-20430-1-git-send-email-Baohua.Song@csr.com>
References: <1368543800-20430-1-git-send-email-Baohua.Song@csr.com>
Message-ID: <20130530181557.GJ3767@intel.com>

On Tue, May 14, 2013 at 11:03:20PM +0800, Barry Song wrote:
> From: Rongjun Ying <Rongjun.Ying at csr.com>
> 
> read SIRFSOC_DMA_CH_ADDR register to get current dma transfer position, then
> update dma residue so that things like ALSA drivers work as ALSA drivers need
> the right residue value.
> 
> Signed-off-by: Rongjun Ying <Rongjun.Ying at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
Applied, thanks

--
~Vinod
> ---
>  drivers/dma/sirf-dma.c |   17 +++++++++++++++++
>  1 files changed, 17 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
> index 1765a0a..716b23e 100644
> --- a/drivers/dma/sirf-dma.c
> +++ b/drivers/dma/sirf-dma.c
> @@ -466,12 +466,29 @@ static enum dma_status
>  sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
>  	struct dma_tx_state *txstate)
>  {
> +	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
>  	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
>  	unsigned long flags;
>  	enum dma_status ret;
> +	struct sirfsoc_dma_desc *sdesc;
> +	int cid = schan->chan.chan_id;
> +	unsigned long dma_pos;
> +	unsigned long dma_request_bytes;
> +	unsigned long residue;
>  
>  	spin_lock_irqsave(&schan->lock, flags);
> +
> +	sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
> +			node);
> +	dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) *
> +		(sdesc->width * SIRFSOC_DMA_WORD_LEN);
> +
>  	ret = dma_cookie_status(chan, cookie, txstate);
> +	dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR)
> +		<< 2;
> +	residue = dma_request_bytes - (dma_pos - sdesc->addr);
> +	dma_set_residue(txstate, residue);
> +
>  	spin_unlock_irqrestore(&schan->lock, flags);
>  
>  	return ret;
> -- 
> 1.7.4.1
> 

-- 


From mturquette at linaro.org  Thu May 30 15:00:12 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 12:00:12 -0700
Subject: [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT
In-Reply-To: <1369330288-14856-4-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
 <1369330288-14856-4-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130530190012.4470.50181@quantum>

Quoting Linus Walleij (2013-05-23 10:31:25)
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This converts the fixed and fixed-factor clocks in the U300
> platform to register themselves from the device tree.
> 
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> Hi Mike, seeking an ACK on this to take the series through
> ARM SoC.

I'm happy to see another conversion to of_clk_init.

Acked-by: Mike Turquette <mturquette at linaro.org>

> ---
>  arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/clk-u300.c         | 33 +++++++++++++------------------
>  2 files changed, 57 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index 0530095..c51a8c7 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -33,6 +33,49 @@
>         syscon: syscon at c0011000 {
>                 compatible = "stericsson,u300-syscon";
>                 reg = <0xc0011000 0x1000>;
> +               clk32: app_32_clk at 32k {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <32768>;
> +               };
> +               pll13: pll13 at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <13000000>;
> +               };
> +               pll208: pll208 at 208M {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <208000000>;
> +               };
> +               app208: app_208_clk at 208M {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-factor-clock";
> +                       clock-div = <1>;
> +                       clock-mult = <1>;
> +                       clocks = <&pll208>;
> +               };
> +               app104: app_104_clk at 104M {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-factor-clock";
> +                       clock-div = <2>;
> +                       clock-mult = <1>;
> +                       clocks = <&pll208>;
> +               };
> +               app52: app_52_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-factor-clock";
> +                       clock-div = <4>;
> +                       clock-mult = <1>;
> +                       clocks = <&pll208>;
> +               };
> +               app26: app_26_clk at 26M {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-factor-clock";
> +                       clock-div = <2>;
> +                       clock-mult = <1>;
> +                       clocks = <&app52>;
> +               };
>         };
>  
>         timer: timer at c0014000 {
> @@ -65,6 +108,7 @@
>                 reg = <0xc0012000 0x1000>;
>                 interrupt-parent = <&vicb>;
>                 interrupts = <3>;
> +               clocks = <&clk32>;
>         };
>  
>         rtc: rtc at c0017000 {
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index a41e42e..bebd6c9 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -11,6 +11,7 @@
>  #include <linux/io.h>
>  #include <linux/clk-provider.h>
>  #include <linux/spinlock.h>
> +#include <linux/of.h>
>  
>  /* APP side SYSCON registers */
>  /* CLK Control Register 16bit (R/W) */
> @@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
>         return clk;
>  }
>  
> +static const __initconst struct of_device_id u300_clk_match[] = {
> +       {
> +               .compatible = "fixed-clock",
> +               .data = of_fixed_clk_setup,
> +       },
> +       {
> +               .compatible = "fixed-factor-clock",
> +               .data = of_fixed_factor_clk_setup,
> +       },
> +};
> +
>  void __init u300_clk_init(void __iomem *base)
>  {
>         u16 val;
> @@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
>         val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
>         writew(val, syscon_vbase + U300_SYSCON_PMCR);
>  
> -       /* These are always available (RTC and PLL13) */
> -       clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
> -                                     CLK_IS_ROOT, 32768);
> -       /* The watchdog sits directly on the 32 kHz clock */
> -       clk_register_clkdev(clk, NULL, "coh901327_wdog");
> -       clk = clk_register_fixed_rate(NULL, "pll13", NULL,
> -                                     CLK_IS_ROOT, 13000000);
> -
> -       /* These derive from PLL208 */
> -       clk = clk_register_fixed_rate(NULL, "pll208", NULL,
> -                                     CLK_IS_ROOT, 208000000);
> -       clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
> -                                       0, 1, 1);
> -       clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
> -                                       0, 1, 2);
> -       clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
> -                                       0, 1, 4);
> -       /* The 52 MHz is divided down to 26 MHz */
> -       clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
> -                                       0, 1, 2);
> +       of_clk_init(u300_clk_match);
>  
>         /* Directly on the AMBA interconnect */
>         clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
> -- 
> 1.7.11.3


From daniel.lezcano at linaro.org  Thu May 30 15:00:59 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Thu, 30 May 2013 21:00:59 +0200
Subject: [PATCH v5] clocksource: add Freescale Vybrid pit timer support
In-Reply-To: <1369732899-17142-1-git-send-email-b35083@freescale.com>
References: <1369732899-17142-1-git-send-email-b35083@freescale.com>
Message-ID: <51A7A1EB.1010109@linaro.org>

On 05/28/2013 11:21 AM, Jingchang Lu wrote:
> Add Freescale Vybrid Family period interrupt timer support.
> 
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>

I queued this patch for 3.11 in my tree [1]

Thanks
  -- Daniel

[1]
https://git.linaro.org/gitweb?p=people/dlezcano/clockevents.git;a=shortlog;h=refs/heads/timers/clockevents

> ---
> v5:
>  Follow internal suggestions to name the SoC family as VF.
>  Add comment for min and max clockevent delta.
>  Add clockevent device irq initialization.
>  Remove IRQF_DISABLED flag.
> v4:
>   Use family name names driver and symbol instead of SoC name.
>   Remove redundant code.
>   Use BUG_ON instead of WARN_ON.
>   Add necessory comment information.
> v3:
>   Move the pit driver adding from arch to drivers/clocksource.
> v2:
>   Use CLOCKSOURCE_OF_DECLARE init pit timer.
>   Add ONESHOT mode support.
> 
>  drivers/clocksource/Kconfig        |   5 +
>  drivers/clocksource/Makefile       |   1 +
>  drivers/clocksource/vf_pit_timer.c | 194 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 200 insertions(+)
>  create mode 100644 drivers/clocksource/vf_pit_timer.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index f151c6c..0a04257 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
>  	  Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
>  	  for all devicetree enabled platforms. This driver will be
>  	  needed only on systems that do not have the Exynos MCT available.
> +
> +config VF_PIT_TIMER
> +	bool
> +	help
> +	  Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 8d979c7..36a9ac1 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_BCM)		+= bcm_kona_timer.o
>  obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence_ttc_timer.o
>  obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
>  obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
> +obj-$(CONFIG_VF_PIT_TIMER)	+= vf_pit_timer.o
>  
>  obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
>  obj-$(CONFIG_CLKSRC_METAG_GENERIC)	+= metag_generic.o
> diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
> new file mode 100644
> index 0000000..598399d
> --- /dev/null
> +++ b/drivers/clocksource/vf_pit_timer.c
> @@ -0,0 +1,194 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/clockchips.h>
> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <asm/sched_clock.h>
> +
> +/*
> + * Each pit takes 0x10 Bytes register space
> + */
> +#define PITMCR		0x00
> +#define PIT0_OFFSET	0x100
> +#define PITn_OFFSET(n)	(PIT0_OFFSET + 0x10 * (n))
> +#define PITLDVAL	0x00
> +#define PITCVAL		0x04
> +#define PITTCTRL	0x08
> +#define PITTFLG		0x0c
> +
> +#define PITMCR_MDIS	(0x1 << 1)
> +
> +#define PITTCTRL_TEN	(0x1 << 0)
> +#define PITTCTRL_TIE	(0x1 << 1)
> +#define PITCTRL_CHN	(0x1 << 2)
> +
> +#define PITTFLG_TIF	0x1
> +
> +static void __iomem *clksrc_base;
> +static void __iomem *clkevt_base;
> +static unsigned long cycle_per_jiffy;
> +
> +static inline void pit_timer_enable(void)
> +{
> +	__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_timer_disable(void)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +}
> +
> +static inline void pit_irq_acknowledge(void)
> +{
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +}
> +
> +static unsigned int pit_read_sched_clock(void)
> +{
> +	return __raw_readl(clksrc_base + PITCVAL);
> +}
> +
> +static int __init pit_clocksource_init(unsigned long rate)
> +{
> +	/* set the max load value and start the clock source counter */
> +	__raw_writel(0, clksrc_base + PITTCTRL);
> +	__raw_writel(~0UL, clksrc_base + PITLDVAL);
> +	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
> +
> +	setup_sched_clock(pit_read_sched_clock, 32, rate);
> +	return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
> +			300, 32, clocksource_mmio_readl_down);
> +}
> +
> +static int pit_set_next_event(unsigned long delta,
> +				struct clock_event_device *unused)
> +{
> +	/*
> +	 * set a new value to PITLDVAL register will not restart the timer,
> +	 * to abort the current cycle and start a timer period with the new
> +	 * value, the timer must be disabled and enabled again.
> +	 * and the PITLAVAL should be set to delta minus one according to pit
> +	 * hardware requirement.
> +	 */
> +	pit_timer_disable();
> +	__raw_writel(delta - 1, clkevt_base + PITLDVAL);
> +	pit_timer_enable();
> +
> +	return 0;
> +}
> +
> +static void pit_set_mode(enum clock_event_mode mode,
> +				struct clock_event_device *evt)
> +{
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		pit_set_next_event(cycle_per_jiffy, evt);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = dev_id;
> +
> +	pit_irq_acknowledge();
> +
> +	/*
> +	 * pit hardware doesn't support oneshot, it will generate an interrupt
> +	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,
> +	 * and start the counter again. So software need to disable the timer
> +	 * to stop the counter loop in ONESHOT mode.
> +	 */
> +	if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
> +		pit_timer_disable();
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct clock_event_device clockevent_pit = {
> +	.name		= "VF pit timer",
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= pit_set_mode,
> +	.set_next_event	= pit_set_next_event,
> +	.rating		= 300,
> +};
> +
> +static struct irqaction pit_timer_irq = {
> +	.name		= "VF pit timer",
> +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= pit_timer_interrupt,
> +	.dev_id		= &clockevent_pit,
> +};
> +
> +static int __init pit_clockevent_init(unsigned long rate, int irq)
> +{
> +	__raw_writel(0, clkevt_base + PITTCTRL);
> +	__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
> +
> +	BUG_ON(setup_irq(irq, &pit_timer_irq));
> +
> +	clockevent_pit.cpumask = cpumask_of(0);
> +	clockevent_pit.irq = irq;
> +	/*
> +	 * The value for the LDVAL register trigger is calculated as:
> +	 * LDVAL trigger = (period / clock period) - 1
> +	 * The pit is a 32-bit down count timer, when the conter value
> +	 * reaches 0, it will generate an interrupt, thus the minimal
> +	 * LDVAL trigger value is 1. And then the min_delta is
> +	 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
> +	 */
> +	clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
> +
> +	return 0;
> +}
> +
> +static void __init pit_timer_init(struct device_node *np)
> +{
> +	struct clk *pit_clk;
> +	void __iomem *timer_base;
> +	unsigned long clk_rate;
> +	int irq;
> +
> +	timer_base = of_iomap(np, 0);
> +	BUG_ON(!timer_base);
> +
> +	/*
> +	 * PIT0 and PIT1 can be chained to build a 64-bit timer,
> +	 * so choose PIT2 as clocksource, PIT3 as clockevent device,
> +	 * and leave PIT0 and PIT1 unused for anyone else who needs them.
> +	 */
> +	clksrc_base = timer_base + PITn_OFFSET(2);
> +	clkevt_base = timer_base + PITn_OFFSET(3);
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +	BUG_ON(irq <= 0);
> +
> +	pit_clk = of_clk_get(np, 0);
> +	BUG_ON(IS_ERR(pit_clk));
> +
> +	BUG_ON(clk_prepare_enable(pit_clk));
> +
> +	clk_rate = clk_get_rate(pit_clk);
> +	cycle_per_jiffy = clk_rate / (HZ);
> +
> +	/* enable the pit module */
> +	__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
> +
> +	BUG_ON(pit_clocksource_init(clk_rate));
> +
> +	pit_clockevent_init(clk_rate, irq);
> +}
> +CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
> 


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From mturquette at linaro.org  Thu May 30 15:06:38 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 12:06:38 -0700
Subject: [PATCH 5/6] ARM: u300: move the gated system controller clocks to
 DT
In-Reply-To: <1369330288-14856-6-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
 <1369330288-14856-6-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130530190638.4470.74710@quantum>

Quoting Linus Walleij (2013-05-23 10:31:27)
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This moves the slow, fast, AHB bridge and "rest" clocks on
> the U300 system controller over to registration from the
> device tree.
> 
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> Hi Mike, I'm seeking an ACK to take this patch through the
> ARM SoC tree.

Acked-by: Mike Turquette <mturquette at linaro.org>

> ---
>  .../bindings/clock/ste-u300-syscon-clock.txt       |  57 ++++
>  arch/arm/boot/dts/ste-u300.dts                     | 149 ++++++++++
>  arch/arm/mach-u300/timer.c                         |   2 +-
>  drivers/clk/clk-u300.c                             | 320 ++++++++++++++-------
>  4 files changed, 418 insertions(+), 110 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> new file mode 100644
> index 0000000..b6a30f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> @@ -0,0 +1,57 @@
> +Clock bindings for ST-Ericsson U300 System Controller Clocks
> +
> +Bindings for the gated system controller clocks:
> +
> +Required properties:
> +- compatible: must be "stericsson,u300-syscon-clk"
> +- #clock-cells: must be <0>
> +- clock-type: specifies the type of clock:
> +  0 = slow clock
> +  1 = fast clock
> +  2 = rest/remaining clock
> +- clock-id: specifies the clock in the type range
> +
> +Optional properties:
> +- clocks: parent clock(s)
> +
> +The available clocks per type are as follows:
> +
> +Type:  ID:   Clock:
> +-------------------
> +0      0     Slow peripheral bridge clock
> +0      1     UART0 clock
> +0      4     GPIO clock
> +0      6     RTC clock
> +0      7     Application timer clock
> +0      8     Access timer clock
> +
> +1      0     Fast peripheral bridge clock
> +1      1     I2C bus 0 clock
> +1      2     I2C bus 1 clock
> +1      5     MMC interface peripheral (silicon) clock
> +1      6     SPI clock
> +
> +2      3     CPU clock
> +2      4     DMA controller clock
> +2      5     External Memory Interface (EMIF) clock
> +2      6     NAND flask interface clock
> +2      8     XGAM graphics engine clock
> +2      9     Shared External Memory Interface (SEMI) clock
> +2      10    AHB Subsystem Bridge clock
> +2      12    Interrupt controller clock
> +
> +Example:
> +
> +gpio_clk: gpio_clk at 13M {
> +       #clock-cells = <0>;
> +       compatible = "stericsson,u300-syscon-clk";
> +       clock-type = <0>; /* Slow */
> +       clock-id = <4>;
> +       clocks = <&slow_clk>;
> +};
> +
> +gpio: gpio at c0016000 {
> +       compatible = "stericsson,gpio-coh901";
> +       (...)
> +       clocks = <&gpio_clk>;
> +};
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index c51a8c7..e83aafc 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -43,6 +43,49 @@
>                         compatible = "fixed-clock";
>                         clock-frequency = <13000000>;
>                 };
> +               /* Slow bridge clocks under PLL13 */
> +               slow_clk: slow_clk at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <0>; /* Slow */
> +                       clock-id = <0>;
> +                       clocks = <&pll13>;
> +               };
> +               uart0_clk: uart0_clk at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <0>; /* Slow */
> +                       clock-id = <1>;
> +                       clocks = <&slow_clk>;
> +               };
> +               gpio_clk: gpio_clk at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <0>; /* Slow */
> +                       clock-id = <4>;
> +                       clocks = <&slow_clk>;
> +               };
> +               rtc_clk: rtc_clk at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <0>; /* Slow */
> +                       clock-id = <6>;
> +                       clocks = <&slow_clk>;
> +               };
> +               apptimer_clk: app_tmr_clk at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <0>; /* Slow */
> +                       clock-id = <7>;
> +                       clocks = <&slow_clk>;
> +               };
> +               acc_tmr_clk at 13M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <0>; /* Slow */
> +                       clock-id = <8>;
> +                       clocks = <&slow_clk>;
> +               };
>                 pll208: pll208 at 208M {
>                         #clock-cells = <0>;
>                         compatible = "fixed-clock";
> @@ -55,6 +98,13 @@
>                         clock-mult = <1>;
>                         clocks = <&pll208>;
>                 };
> +               cpu_clk at 208M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <3>;
> +                       clocks = <&app208>;
> +               };
>                 app104: app_104_clk at 104M {
>                         #clock-cells = <0>;
>                         compatible = "fixed-factor-clock";
> @@ -62,6 +112,13 @@
>                         clock-mult = <1>;
>                         clocks = <&pll208>;
>                 };
> +               semi_clk at 104M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <9>;
> +                       clocks = <&app104>;
> +               };
>                 app52: app_52_clk at 52M {
>                         #clock-cells = <0>;
>                         compatible = "fixed-factor-clock";
> @@ -69,6 +126,49 @@
>                         clock-mult = <1>;
>                         clocks = <&pll208>;
>                 };
> +               /* AHB subsystem clocks */
> +               ahb_clk: ahb_subsys_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <10>;
> +                       clocks = <&app52>;
> +               };
> +               intcon_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <12>;
> +                       clocks = <&ahb_clk>;
> +               };
> +               emif_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <5>;
> +                       clocks = <&ahb_clk>;
> +               };
> +               dmac_clk: dmac_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <4>;
> +                       clocks = <&app52>;
> +               };
> +               fsmc_clk: fsmc_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <6>;
> +                       clocks = <&app52>;
> +               };
> +               xgam_clk: xgam_clk at 52M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <2>; /* Rest */
> +                       clock-id = <8>;
> +                       clocks = <&app52>;
> +               };
>                 app26: app_26_clk at 26M {
>                         #clock-cells = <0>;
>                         compatible = "fixed-factor-clock";
> @@ -76,6 +176,42 @@
>                         clock-mult = <1>;
>                         clocks = <&app52>;
>                 };
> +               /* Fast bridge  clocks */
> +               fast_clk: fast_clk at 26M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <1>; /* Fast */
> +                       clock-id = <0>;
> +                       clocks = <&app26>;
> +               };
> +               i2c0_clk: i2c0_clk at 26M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <1>; /* Fast */
> +                       clock-id = <1>;
> +                       clocks = <&fast_clk>;
> +               };
> +               i2c1_clk: i2c1_clk at 26M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <1>; /* Fast */
> +                       clock-id = <2>;
> +                       clocks = <&fast_clk>;
> +               };
> +               mmc_pclk: mmc_p_clk at 26M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <1>; /* Fast */
> +                       clock-id = <5>;
> +                       clocks = <&fast_clk>;
> +               };
> +               spi_clk: spi_p_clk at 26M {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-clk";
> +                       clock-type = <1>; /* Fast */
> +                       clock-id = <6>;
> +                       clocks = <&fast_clk>;
> +               };
>         };
>  
>         timer: timer at c0014000 {
> @@ -83,6 +219,7 @@
>                 reg = <0xc0014000 0x1000>;
>                 interrupt-parent = <&vica>;
>                 interrupts = <24 25 26 27>;
> +               clocks = <&apptimer_clk>;
>         };
>  
>         gpio: gpio at c0016000 {
> @@ -90,6 +227,7 @@
>                 reg = <0xc0016000 0x1000>;
>                 interrupt-parent = <&vicb>;
>                 interrupts = <0 1 2 18 21 22 23>;
> +               clocks = <&gpio_clk>;
>                 interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
>                                 "gpio4", "gpio5", "gpio6";
>                 interrupt-controller;
> @@ -116,6 +254,7 @@
>                 reg = <0xc0017000 0x1000>;
>                 interrupt-parent = <&vicb>;
>                 interrupts = <10>;
> +               clocks = <&rtc_clk>;
>         };
>  
>         dmac: dma-controller at c00020000 {
> @@ -125,6 +264,7 @@
>                 interrupts = <2>;
>                 #dma-cells = <1>;
>                 dma-channels = <40>;
> +               clocks = <&dmac_clk>;
>         };
>  
>         /* A NAND flash of 128 MiB */
> @@ -138,6 +278,7 @@
>                         <0x80010000 0x4000>;    /* NAND Base CMD */
>                 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
>                 nand-skip-bbtscan;
> +               clocks = <&fsmc_clk>;
>  
>                 partition at 0 {
>                 label = "boot records";
> @@ -158,6 +299,7 @@
>                 reg = <0xc0004000 0x1000>;
>                 interrupt-parent = <&vicb>;
>                 interrupts = <8>;
> +               clocks = <&i2c0_clk>;
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>                 ab3100: ab3100 at 0x48 {
> @@ -235,6 +377,7 @@
>                 reg = <0xc0005000 0x1000>;
>                 interrupt-parent = <&vicb>;
>                 interrupts = <9>;
> +               clocks = <&i2c1_clk>;
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>                 fwcam0: fwcam at 0x10 {
> @@ -270,6 +413,8 @@
>                         reg = <0xc0013000 0x1000>;
>                         interrupt-parent = <&vica>;
>                         interrupts = <22>;
> +                       clocks = <&uart0_clk>, <&uart0_clk>;
> +                       clock-names = "apb_pclk", "uart0_clk";
>                         dmas = <&dmac 17 &dmac 18>;
>                         dma-names = "tx", "rx";
>                 };
> @@ -288,6 +433,8 @@
>                         reg = <0xc0001000 0x1000>;
>                         interrupt-parent = <&vicb>;
>                         interrupts = <6 7>;
> +                       clocks = <&mmc_pclk>;
> +                       clock-names = "apb_pclk";
>                         max-frequency = <24000000>;
>                         bus-width = <4>; // SD-card slot
>                         mmc-cap-mmc-highspeed;
> @@ -304,6 +451,8 @@
>                         reg = <0xc0006000 0x1000>;
>                         interrupt-parent = <&vica>;
>                         interrupts = <23>;
> +                       clocks = <&spi_clk>, <&spi_clk>;
> +                       clock-names = "apb_pclk", "spi_clk";
>                         dmas = <&dmac 27 &dmac 28>;
>                         dma-names = "tx", "rx";
>                         #address-cells = <1>;
> diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
> index 2e1c81d..390ae5f 100644
> --- a/arch/arm/mach-u300/timer.c
> +++ b/arch/arm/mach-u300/timer.c
> @@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
>         pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
>  
>         /* Clock the interrupt controller */
> -       clk = clk_get_sys("apptimer", NULL);
> +       clk = of_clk_get(np, 0);
>         BUG_ON(IS_ERR(clk));
>         clk_prepare_enable(clk);
>         rate = clk_get_rate(clk);
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index bebd6c9..5f234d3 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
>         return clk;
>  }
>  
> +#define U300_CLK_TYPE_SLOW 0
> +#define U300_CLK_TYPE_FAST 1
> +#define U300_CLK_TYPE_REST 2
> +
> +/**
> + * struct u300_clock - defines the bits and pieces for a certain clock
> + * @type: the clock type, slow fast or rest
> + * @id: the bit in the slow/fast/rest register for this clock
> + * @hw_ctrld: whether the clock is hardware controlled
> + * @clk_val: a value to poke in the one-write enable/disable registers
> + */
> +struct u300_clock {
> +       u8 type;
> +       u8 id;
> +       bool hw_ctrld;
> +       u16 clk_val;
> +};
> +
> +struct u300_clock const __initconst u300_clk_lookup[] = {
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 3,
> +               .hw_ctrld = true,
> +               .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 4,
> +               .hw_ctrld = true,
> +               .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 5,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 6,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 8,
> +               .hw_ctrld = true,
> +               .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 9,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 10,
> +               .hw_ctrld = true,
> +               .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_REST,
> +               .id = 12,
> +               .hw_ctrld = false,
> +               /* INTCON: cannot be enabled, just taken out of reset */
> +               .clk_val = 0xFFFFU,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_FAST,
> +               .id = 0,
> +               .hw_ctrld = true,
> +               .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_FAST,
> +               .id = 1,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_FAST,
> +               .id = 2,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_FAST,
> +               .id = 5,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_FAST,
> +               .id = 6,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_SLOW,
> +               .id = 0,
> +               .hw_ctrld = true,
> +               .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_SLOW,
> +               .id = 1,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_SLOW,
> +               .id = 4,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_SLOW,
> +               .id = 6,
> +               .hw_ctrld = true,
> +               /* No clock enable register bit */
> +               .clk_val = 0xFFFFU,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_SLOW,
> +               .id = 7,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
> +       },
> +       {
> +               .type = U300_CLK_TYPE_SLOW,
> +               .id = 8,
> +               .hw_ctrld = false,
> +               .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
> +       },
> +};
> +
> +static void __init of_u300_syscon_clk_init(struct device_node *np)
> +{
> +       struct clk *clk = ERR_PTR(-EINVAL);
> +       const char *clk_name = np->name;
> +       const char *parent_name;
> +       void __iomem *res_reg;
> +       void __iomem *en_reg;
> +       u32 clk_type;
> +       u32 clk_id;
> +       int i;
> +
> +       if (of_property_read_u32(np, "clock-type", &clk_type)) {
> +               pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
> +                      __func__, clk_name);
> +               return;
> +       }
> +       if (of_property_read_u32(np, "clock-id", &clk_id)) {
> +               pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
> +                      __func__, clk_name);
> +               return;
> +       }
> +       parent_name = of_clk_get_parent_name(np, 0);
> +
> +       switch (clk_type) {
> +       case U300_CLK_TYPE_SLOW:
> +               res_reg = syscon_vbase + U300_SYSCON_RSR;
> +               en_reg = syscon_vbase + U300_SYSCON_CESR;
> +               break;
> +       case U300_CLK_TYPE_FAST:
> +               res_reg = syscon_vbase + U300_SYSCON_RFR;
> +               en_reg = syscon_vbase + U300_SYSCON_CEFR;
> +               break;
> +       case U300_CLK_TYPE_REST:
> +               res_reg = syscon_vbase + U300_SYSCON_RRR;
> +               en_reg = syscon_vbase + U300_SYSCON_CERR;
> +               break;
> +       default:
> +               pr_err("unknown clock type %x specified\n", clk_type);
> +               return;
> +       }
> +
> +       for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
> +               const struct u300_clock *u3clk = &u300_clk_lookup[i];
> +
> +               if (u3clk->type == clk_type && u3clk->id == clk_id)
> +                       clk = syscon_clk_register(NULL,
> +                                                 clk_name, parent_name,
> +                                                 0, u3clk->hw_ctrld,
> +                                                 res_reg, u3clk->id,
> +                                                 en_reg, u3clk->id,
> +                                                 u3clk->clk_val);
> +       }
> +
> +       if (!IS_ERR(clk)) {
> +               of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +
> +               /*
> +                * Some few system clocks - device tree does not
> +                * represent clocks without a corresponding device node.
> +                * for now we add these three clocks here.
> +                */
> +               if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
> +                       clk_register_clkdev(clk, NULL, "pl172");
> +               if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
> +                       clk_register_clkdev(clk, NULL, "semi");
> +               if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
> +                       clk_register_clkdev(clk, NULL, "intcon");
> +       }
> +}
> +
>  /**
>   * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
>   * @hw: corresponding clock hardware entry
> @@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
>                 .compatible = "fixed-factor-clock",
>                 .data = of_fixed_factor_clk_setup,
>         },
> +       {
> +               .compatible = "stericsson,u300-syscon-clk",
> +               .data = of_u300_syscon_clk_init,
> +       },
>  };
>  
>  void __init u300_clk_init(void __iomem *base)
> @@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
>  
>         of_clk_init(u300_clk_match);
>  
> -       /* Directly on the AMBA interconnect */
> -       clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RRR, 3,
> -                                 syscon_vbase + U300_SYSCON_CERR, 3,
> -                                 U300_SYSCON_SBCER_CPU_CLK_EN);
> -       clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RRR, 4,
> -                                 syscon_vbase + U300_SYSCON_CERR, 4,
> -                                 U300_SYSCON_SBCER_DMAC_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "dma");
> -       clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RRR, 6,
> -                                 syscon_vbase + U300_SYSCON_CERR, 6,
> -                                 U300_SYSCON_SBCER_NANDIF_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "fsmc-nand");
> -       clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RRR, 8,
> -                                 syscon_vbase + U300_SYSCON_CERR, 8,
> -                                 U300_SYSCON_SBCER_XGAM_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "xgam");
> -       clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RRR, 9,
> -                                 syscon_vbase + U300_SYSCON_CERR, 9,
> -                                 U300_SYSCON_SBCER_SEMI_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "semi");
> -
> -       /* AHB bridge clocks */
> -       clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RRR, 10,
> -                                 syscon_vbase + U300_SYSCON_CERR, 10,
> -                                 U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
> -       clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RRR, 12,
> -                                 syscon_vbase + U300_SYSCON_CERR, 12,
> -                                 /* Cannot be enabled, just taken out of reset */
> -                                 0xFFFFU);
> -       clk_register_clkdev(clk, NULL, "intcon");
> -       clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RRR, 5,
> -                                 syscon_vbase + U300_SYSCON_CERR, 5,
> -                                 U300_SYSCON_SBCER_EMIF_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "pl172");
> -
> -       /* FAST bridge clocks */
> -       clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RFR, 0,
> -                                 syscon_vbase + U300_SYSCON_CEFR, 0,
> -                                 U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
> -       clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RFR, 1,
> -                                 syscon_vbase + U300_SYSCON_CEFR, 1,
> -                                 U300_SYSCON_SBCER_I2C0_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "stu300.0");
> -       clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RFR, 2,
> -                                 syscon_vbase + U300_SYSCON_CEFR, 2,
> -                                 U300_SYSCON_SBCER_I2C1_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "stu300.1");
> -       clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RFR, 5,
> -                                 syscon_vbase + U300_SYSCON_CEFR, 5,
> -                                 U300_SYSCON_SBCER_MMC_CLK_EN);
> -       clk_register_clkdev(clk, "apb_pclk", "mmci");
> -       clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RFR, 6,
> -                                 syscon_vbase + U300_SYSCON_CEFR, 6,
> -                                 U300_SYSCON_SBCER_SPI_CLK_EN);
> -       /* The SPI has no external clock for the outward bus, uses the pclk */
> -       clk_register_clkdev(clk, NULL, "pl022");
> -       clk_register_clkdev(clk, "apb_pclk", "pl022");
> -
> -       /* SLOW bridge clocks */
> -       clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RSR, 0,
> -                                 syscon_vbase + U300_SYSCON_CESR, 0,
> -                                 U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
> -       clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RSR, 1,
> -                                 syscon_vbase + U300_SYSCON_CESR, 1,
> -                                 U300_SYSCON_SBCER_UART_CLK_EN);
> -       /* Same clock is used for APB and outward bus */
> -       clk_register_clkdev(clk, NULL, "uart0");
> -       clk_register_clkdev(clk, "apb_pclk", "uart0");
> -       clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RSR, 4,
> -                                 syscon_vbase + U300_SYSCON_CESR, 4,
> -                                 U300_SYSCON_SBCER_GPIO_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "u300-gpio");
> -       clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RSR, 5,
> -                                 syscon_vbase + U300_SYSCON_CESR, 6,
> -                                 U300_SYSCON_SBCER_KEYPAD_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "coh901461-keypad");
> -       clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
> -                                 syscon_vbase + U300_SYSCON_RSR, 6,
> -                                 /* No clock enable register bit */
> -                                 NULL, 0, 0xFFFFU);
> -       clk_register_clkdev(clk, NULL, "rtc-coh901331");
> -       clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RSR, 7,
> -                                 syscon_vbase + U300_SYSCON_CESR, 7,
> -                                 U300_SYSCON_SBCER_APP_TMR_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "apptimer");
> -       clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
> -                                 syscon_vbase + U300_SYSCON_RSR, 8,
> -                                 syscon_vbase + U300_SYSCON_CESR, 8,
> -                                 U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
> -       clk_register_clkdev(clk, NULL, "timer");
> -
>         /* Then this special MMC/SD clock */
>         clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
>         clk_register_clkdev(clk, NULL, "mmci");
> -- 
> 1.7.11.3


From balbi at ti.com  Thu May 30 15:06:21 2013
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 30 May 2013 22:06:21 +0300
Subject: [PATCH 20/39] usb: musb: ux500: move channel number knowledge
 into the driver
In-Reply-To: <20130530081211.GA1915@gmail.com>
References: <1368611522-9984-1-git-send-email-lee.jones@linaro.org>
 <1368611522-9984-21-git-send-email-lee.jones@linaro.org>
 <20130529175741.GG21290@arwen.pp.htv.fi>
 <CACRpkda3d9_XvqRmy0nbWyri2xC3Qst2U2Sv=UDxV4w-UxK_JQ@mail.gmail.com>
 <20130530081211.GA1915@gmail.com>
Message-ID: <20130530190621.GB6277@arwen.pp.htv.fi>

HI

On Thu, May 30, 2013 at 09:12:11AM +0100, Lee Jones wrote:
> On Thu, 30 May 2013, Linus Walleij wrote:
> 
> > On Wed, May 29, 2013 at 7:57 PM, Felipe Balbi <balbi at ti.com> wrote:
> > > On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
> > >> For all ux500 based platforms the maximum number of end-points are used.
> > >> Move this knowledge into the driver so we can relinquish the burden from
> > >> platform data. This also removes quite a bit of complexity from the driver
> > >> and will aid us when we come to enable the driver for Device Tree.
> > >>
> > >> Cc: Felipe Balbi <balbi at ti.com>
> > >> Cc: linux-usb at vger.kernel.org
> > >> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > >> Acked-by: Fabio Baltieri <fabio.baltieri at linaro.org>
> > >> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > >
> > > for drivers/usb/musb
> > >
> > > Acked-by: Felipe Balbi <balbi at ti.com>
> > 
> > Is that only for this patch 20/39 or also 21, 22 & 23?
> > 
> > Poke us if we should re-send them...
> 
> I read this as all patches in the series "for drivers/usb/musb".

right :-) Should've sent on patch 0/39, my bad.

cheers

-- 
balbi
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From mturquette at linaro.org  Thu May 30 15:07:50 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 12:07:50 -0700
Subject: [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree
In-Reply-To: <1369330288-14856-7-git-send-email-linus.walleij@stericsson.com>
References: <1369330288-14856-1-git-send-email-linus.walleij@stericsson.com>
 <1369330288-14856-7-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20130530190750.4470.31756@quantum>

Quoting Linus Walleij (2013-05-23 10:31:28)
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This converts the last of the U300 clocks to being probed from
> the device tree.
> 
> Cc: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> Hi Mike, I'm seeking an ACK on this to take it through the
> ARM SoC tree.

Acked-by: Mike Turquette <mturquette at linaro.org>

> ---
>  .../bindings/clock/ste-u300-syscon-clock.txt       | 23 ++++++++++++++++++++++
>  arch/arm/boot/dts/ste-u300.dts                     |  9 +++++++--
>  drivers/clk/clk-u300.c                             | 22 ++++++++++++++++-----
>  3 files changed, 47 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> index b6a30f5..7cafcb9 100644
> --- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> @@ -55,3 +55,26 @@ gpio: gpio at c0016000 {
>         (...)
>         clocks = <&gpio_clk>;
>  };
> +
> +
> +Bindings for the MMC/SD card clock:
> +
> +Required properties:
> +- compatible: must be "stericsson,u300-syscon-mclk"
> +- #clock-cells: must be <0>
> +
> +Optional properties:
> +- clocks: parent clock(s)
> +
> +mmc_mclk: mmc_mclk {
> +       #clock-cells = <0>;
> +       compatible = "stericsson,u300-syscon-mclk";
> +       clocks = <&mmc_pclk>;
> +};
> +
> +mmcsd: mmcsd at c0001000 {
> +       compatible = "arm,pl18x", "arm,primecell";
> +       clocks = <&mmc_pclk>, <&mmc_mclk>;
> +       clock-names = "apb_pclk", "mclk";
> +       (...)
> +};
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index e83aafc..d5dd243 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -205,6 +205,11 @@
>                         clock-id = <5>;
>                         clocks = <&fast_clk>;
>                 };
> +               mmc_mclk: mmc_mclk {
> +                       #clock-cells = <0>;
> +                       compatible = "stericsson,u300-syscon-mclk";
> +                       clocks = <&mmc_pclk>;
> +               };
>                 spi_clk: spi_p_clk at 26M {
>                         #clock-cells = <0>;
>                         compatible = "stericsson,u300-syscon-clk";
> @@ -433,8 +438,8 @@
>                         reg = <0xc0001000 0x1000>;
>                         interrupt-parent = <&vicb>;
>                         interrupts = <6 7>;
> -                       clocks = <&mmc_pclk>;
> -                       clock-names = "apb_pclk";
> +                       clocks = <&mmc_pclk>, <&mmc_mclk>;
> +                       clock-names = "apb_pclk", "mclk";
>                         max-frequency = <24000000>;
>                         bus-width = <4>; // SD-card slot
>                         mmc-cap-mmc-highspeed;
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index 5f234d3..8774e05 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
>         return clk;
>  }
>  
> +static void __init of_u300_syscon_mclk_init(struct device_node *np)
> +{
> +       struct clk *clk = ERR_PTR(-EINVAL);
> +       const char *clk_name = np->name;
> +       const char *parent_name;
> +
> +       parent_name = of_clk_get_parent_name(np, 0);
> +       clk = mclk_clk_register(NULL, clk_name, parent_name, false);
> +       if (!IS_ERR(clk))
> +               of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
>  static const __initconst struct of_device_id u300_clk_match[] = {
>         {
>                 .compatible = "fixed-clock",
> @@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
>                 .compatible = "stericsson,u300-syscon-clk",
>                 .data = of_u300_syscon_clk_init,
>         },
> +       {
> +               .compatible = "stericsson,u300-syscon-mclk",
> +               .data = of_u300_syscon_mclk_init,
> +       },
>  };
>  
> +
>  void __init u300_clk_init(void __iomem *base)
>  {
>         u16 val;
> -       struct clk *clk;
>  
>         syscon_vbase = base;
>  
> @@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
>         writew(val, syscon_vbase + U300_SYSCON_PMCR);
>  
>         of_clk_init(u300_clk_match);
> -
> -       /* Then this special MMC/SD clock */
> -       clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
> -       clk_register_clkdev(clk, NULL, "mmci");
>  }
> -- 
> 1.7.11.3


From akpm at linux-foundation.org  Thu May 30 15:36:09 2013
From: akpm at linux-foundation.org (Andrew Morton)
Date: Thu, 30 May 2013 12:36:09 -0700
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <51A704C3.6010109@atmel.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
 <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
 <51A704C3.6010109@atmel.com>
Message-ID: <20130530123609.6e2966a66dd7b131961ed052@linux-foundation.org>

On Thu, 30 May 2013 09:50:27 +0200 Nicolas Ferre <nicolas.ferre at atmel.com> wrote:

> The review of this patch series was in my TODO list for some time...
> 
> Today, I magically took time to review it ;-)
> The patch series is good and I (even if it is too late) here is my:
> 
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> 
> I do not know if the series can be stacked for inclusion in 3.10-rc but 
> the resolution of this bug can help a lot (as Douglas is saying in 
> subsequent email...).

We can do that, but looking through the discussion and changelogs I
can't seem to find a usable description of what impact the bug (and its
fix) have upon end-users.

A nicely packaged description of that impact would help grease the
wheels, please.



From jason at lakedaemon.net  Thu May 30 15:37:08 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 May 2013 15:37:08 -0400
Subject: [PATCH v5 12/13] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <8738t4q1kv.fsf@natisbad.org>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-13-git-send-email-sebastian.hesselbarth@gmail.com>
 <8738t4q1kv.fsf@natisbad.org>
Message-ID: <20130530193708.GC31290@titan.lakedaemon.net>

On Thu, May 30, 2013 at 11:06:08AM +0200, Arnaud Ebalard wrote:
> Hi Jason and Sebastian,
> 
> Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> writes:
> 
> > With DT support for mv643xx_eth board specific init for some boards now
> > is unneccessary. Remove those board files, Kconfig entries, and
> > corresponding entries in kirkwood_defconfig.
> >
> > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> > ---
> > Note: board-km_kirkwood.c is also removed, as Valentin Longchamp confirmed
> > the lock-up is not caused by accessing clock gating registers but rather
> > non-existent device registers. This will be addressed by dtsi separation
> > for kirkwood and bobcat SoC variants.
> >
> > Changelog:
> > v3->v4:
> > - remove more boards that don't require board specific setup
> >
> > Cc: David Miller <davem at davemloft.net>
> > Cc: Lennert Buytenhek <buytenh at wantstofly.org>
> > Cc: Jason Cooper <jason at lakedaemon.net>
> > Cc: Andrew Lunn <andrew at lunn.ch>
> > Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> > Cc: netdev at vger.kernel.org
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: linuxppc-dev at lists.ozlabs.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> >  arch/arm/configs/kirkwood_defconfig           |   16 ----
> >  arch/arm/mach-kirkwood/Kconfig                |  117 -------------------------
> >  arch/arm/mach-kirkwood/Makefile               |   16 ----
> >  arch/arm/mach-kirkwood/board-dnskw.c          |    7 --
> >  arch/arm/mach-kirkwood/board-dockstar.c       |   32 -------
> >  arch/arm/mach-kirkwood/board-dreamplug.c      |   35 --------
> >  arch/arm/mach-kirkwood/board-dt.c             |   62 +------------
> >  arch/arm/mach-kirkwood/board-goflexnet.c      |   34 -------
> >  arch/arm/mach-kirkwood/board-guruplug.c       |   33 -------
> >  arch/arm/mach-kirkwood/board-ib62x0.c         |   29 ------
> >  arch/arm/mach-kirkwood/board-iconnect.c       |   10 ---
> >  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   34 -------
> >  arch/arm/mach-kirkwood/board-km_kirkwood.c    |   44 ----------
> >  arch/arm/mach-kirkwood/board-lsxl.c           |   16 ----
> >  arch/arm/mach-kirkwood/board-mplcec4.c        |   14 ---
> >  arch/arm/mach-kirkwood/board-ns2.c            |   35 --------
> >  arch/arm/mach-kirkwood/board-openblocks_a6.c  |   26 ------
> >  arch/arm/mach-kirkwood/board-readynas.c       |    6 --
> 
> Just a stupid note: With Thomas ongoing work to get mvebu-pcie driver in
> place and enabled for kirkwood, some boards setup files will also lose
> their pcie init routines, which may allow you to kill those additonal
> files soon.

Yes, we're very excited about this ;-)

> For instance 6bd98481ab34 (arm: kirkwood: NETGEAR ReadyNAS Duo v2 init
> PCIe via DT) currently sitting in jcooper/mvebu/pcie_kirkwood removes
> the PCIE init routine in board-readynas.c, and yours remove ge00
> init. With both applied, the whole file can go away.
> 
> AFAICT, this may be the case soon for:
> 
>  arch/arm/mach-kirkwood/board-iconnect.c   (36e5722089)
>  arch/arm/mach-kirkwood/board-mplcec4.c    (9470fbfb8d)
>  arch/arm/mach-kirkwood/board-nsa310.c     (40fa8e5da2)
>  arch/arm/mach-kirkwood/board-readynas.c   (6bd98481ab)
>  arch/arm/mach-kirkwood/board-ts219.c      (259e234608)

Would you mind putting a patch together (for after v3.10 drops) to do
this?  If you applied Sebastian's series on top of mvebu/pcie_kirkwood,
that should get you almost there.  The last half of his series is going
in after v3.10...

You may want to try merging in mvebu/boards and mvebu/soc.  Those have
the changes to use dt for the restart and power-off drivers.  That'll
allow us to empty out a few more board files.  mvebu/dt also has a patch
from Valentin allowing us to remove the keymile board as well.

thx,

Jason.


From mturquette at linaro.org  Thu May 30 15:42:27 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 12:42:27 -0700
Subject: [PATCHv4 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <1369410080-436-3-git-send-email-dinguyen@altera.com>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <1369410080-436-3-git-send-email-dinguyen@altera.com>
Message-ID: <20130530194227.4470.3741@quantum>

Quoting dinguyen at altera.com (2013-05-24 08:41:17)
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Add support to gate the clocks that directly feed peripherals. For clocks
> with multiple parents, add the ability to determine the correct parent,
> and also set parents. Also add support to calculate and set the clocks'
> rate.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> Reviewed-by: Pavel Machek <pavel at denx.de>
> CC: Mike Turquette <mturquette at linaro.org>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Olof Johansson <olof at lixom.net>
> Cc: Pavel Machek <pavel at denx.de>
> CC: <linux at arm.linux.org.uk>
> 

Looks OK to me.  Lots of conditionals in socfpga_gate_clk_init, which
some day might be better to break out into separate clk types.  Not a
big deal for now:

Acked-by: Mike Turquette <mturquette at linaro.org>

> v3:
> - Addressed comments from Pavel
> 
> v2:
> - Fix space/indent errors
> - Add streq for strcmp == 0
> ---
>  drivers/clk/socfpga/clk.c |  194 ++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 185 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
> index bd11315..5bb848c 100644
> --- a/drivers/clk/socfpga/clk.c
> +++ b/drivers/clk/socfpga/clk.c
> @@ -24,15 +24,17 @@
>  #include <linux/of.h>
>  
>  /* Clock Manager offsets */
> -#define CLKMGR_CTRL    0x0
> -#define CLKMGR_BYPASS 0x4
> +#define CLKMGR_CTRL    0x0
> +#define CLKMGR_BYPASS  0x4
> +#define CLKMGR_L4SRC   0x70
> +#define CLKMGR_PERPLL_SRC      0xAC
>  
>  /* Clock bypass bits */
> -#define MAINPLL_BYPASS (1<<0)
> -#define SDRAMPLL_BYPASS (1<<1)
> -#define SDRAMPLL_SRC_BYPASS (1<<2)
> -#define PERPLL_BYPASS (1<<3)
> -#define PERPLL_SRC_BYPASS (1<<4)
> +#define MAINPLL_BYPASS         (1<<0)
> +#define SDRAMPLL_BYPASS                (1<<1)
> +#define SDRAMPLL_SRC_BYPASS    (1<<2)
> +#define PERPLL_BYPASS          (1<<3)
> +#define PERPLL_SRC_BYPASS      (1<<4)
>  
>  #define SOCFPGA_PLL_BG_PWRDWN          0
>  #define SOCFPGA_PLL_EXT_ENA            1
> @@ -41,6 +43,17 @@
>  #define SOCFPGA_PLL_DIVF_SHIFT 3
>  #define SOCFPGA_PLL_DIVQ_MASK          0x003F0000
>  #define SOCFPGA_PLL_DIVQ_SHIFT 16
> +#define SOCFGPA_MAX_PARENTS    3
> +
> +#define SOCFPGA_L4_MP_CLK              "l4_mp_clk"
> +#define SOCFPGA_L4_SP_CLK              "l4_sp_clk"
> +#define SOCFPGA_NAND_CLK               "nand_clk"
> +#define SOCFPGA_NAND_X_CLK             "nand_x_clk"
> +#define SOCFPGA_MMC_CLK                        "mmc_clk"
> +#define SOCFPGA_DB_CLK                 "gpio_db_clk"
> +
> +#define div_mask(width)        ((1 << (width)) - 1)
> +#define streq(a, b) (strcmp((a), (b)) == 0)
>  
>  extern void __iomem *clk_mgr_base_addr;
>  
> @@ -49,6 +62,9 @@ struct socfpga_clk {
>         char *parent_name;
>         char *clk_name;
>         u32 fixed_div;
> +       void __iomem *div_reg;
> +       u32 width;      /* only valid if div_reg != 0 */
> +       u32 shift;      /* only valid if div_reg != 0 */
>  };
>  #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
>  
> @@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
>  
>         socfpga_clk->hw.hw.init = &init;
>  
> -       if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
> -                       strcmp(clk_name, "sdram_pll")) {
> +       if (streq(clk_name, "main_pll") ||
> +               streq(clk_name, "periph_pll") ||
> +               streq(clk_name, "sdram_pll")) {
>                 socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
>                 clk_pll_ops.enable = clk_gate_ops.enable;
>                 clk_pll_ops.disable = clk_gate_ops.disable;
> @@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
>         return clk;
>  }
>  
> +static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
> +{
> +       u32 l4_src;
> +       u32 perpll_src;
> +
> +       if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
> +               l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> +               return l4_src &= 0x1;
> +       }
> +       if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
> +               l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> +               return !!(l4_src & 2);
> +       }
> +
> +       perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> +       if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
> +               return perpll_src &= 0x3;
> +       if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
> +                       streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
> +                       return (perpll_src >> 2) & 3;
> +
> +       /* QSPI clock */
> +       return (perpll_src >> 4) & 3;
> +
> +}
> +
> +static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
> +{
> +       u32 src_reg;
> +
> +       if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
> +               src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> +               src_reg &= ~0x1;
> +               src_reg |= parent;
> +               writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
> +       } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
> +               src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> +               src_reg &= ~0x2;
> +               src_reg |= (parent << 1);
> +               writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
> +       } else {
> +               src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> +               if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
> +                       src_reg &= ~0x3;
> +                       src_reg |= parent;
> +               } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
> +                       streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
> +                       src_reg &= ~0xC;
> +                       src_reg |= (parent << 2);
> +               } else {/* QSPI clock */
> +                       src_reg &= ~0x30;
> +                       src_reg |= (parent << 4);
> +               }
> +               writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> +       }
> +
> +       return 0;
> +}
> +
> +static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
> +       unsigned long parent_rate)
> +{
> +       struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
> +       u32 div = 1, val;
> +
> +       if (socfpgaclk->fixed_div)
> +               div = socfpgaclk->fixed_div;
> +       else if (socfpgaclk->div_reg) {
> +               val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
> +               val &= div_mask(socfpgaclk->width);
> +               if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
> +                       div = val + 1;
> +               else
> +                       div = (1 << val);
> +       }
> +
> +       return parent_rate / div;
> +}
> +
> +static struct clk_ops gateclk_ops = {
> +       .recalc_rate = socfpga_clk_recalc_rate,
> +       .get_parent = socfpga_clk_get_parent,
> +       .set_parent = socfpga_clk_set_parent,
> +};
> +
> +static void __init socfpga_gate_clk_init(struct device_node *node,
> +       const struct clk_ops *ops)
> +{
> +       u32 clk_gate[2];
> +       u32 div_reg[3];
> +       u32 fixed_div;
> +       struct clk *clk;
> +       struct socfpga_clk *socfpga_clk;
> +       const char *clk_name = node->name;
> +       const char *parent_name[SOCFGPA_MAX_PARENTS];
> +       struct clk_init_data init;
> +       int rc;
> +       int i = 0;
> +
> +       socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
> +       if (WARN_ON(!socfpga_clk))
> +               return;
> +
> +       rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
> +       if (rc)
> +               clk_gate[0] = 0;
> +
> +       if (clk_gate[0]) {
> +               socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
> +               socfpga_clk->hw.bit_idx = clk_gate[1];
> +
> +               gateclk_ops.enable = clk_gate_ops.enable;
> +               gateclk_ops.disable = clk_gate_ops.disable;
> +       }
> +
> +       rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
> +       if (rc)
> +               socfpga_clk->fixed_div = 0;
> +       else
> +               socfpga_clk->fixed_div = fixed_div;
> +
> +       rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
> +       if (!rc) {
> +               socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
> +               socfpga_clk->shift = div_reg[1];
> +               socfpga_clk->width = div_reg[2];
> +       } else {
> +               socfpga_clk->div_reg = 0;
> +       }
> +
> +       of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +       init.name = clk_name;
> +       init.ops = ops;
> +       init.flags = 0;
> +       while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
> +                       of_clk_get_parent_name(node, i)) != NULL)
> +               i++;
> +
> +       init.parent_names = parent_name;
> +       init.num_parents = i;
> +       socfpga_clk->hw.hw.init = &init;
> +
> +       clk = clk_register(NULL, &socfpga_clk->hw.hw);
> +       if (WARN_ON(IS_ERR(clk))) {
> +               kfree(socfpga_clk);
> +               return;
> +       }
> +       rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
> +       if (WARN_ON(rc))
> +               return;
> +}
> +
>  static void __init socfpga_pll_init(struct device_node *node)
>  {
>         socfpga_clk_init(node, &clk_pll_ops);
> @@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
>  }
>  CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
>  
> +static void __init socfpga_gate_init(struct device_node *node)
> +{
> +       socfpga_gate_clk_init(node, &gateclk_ops);
> +}
> +CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
> +
>  void __init socfpga_init_clocks(void)
>  {
>         struct clk *clk;
> -- 
> 1.7.9.5


From linus.walleij at linaro.org  Thu May 30 16:03:58 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 22:03:58 +0200
Subject: [PATCH 1/2] gpiolib: add gpio_export_with_name
In-Reply-To: <51A719A5.50906@epfl.ch>
References: <20121121101259.GQ4398@game.jcrosoft.org>
 <1353492849-29397-1-git-send-email-plagnioj@jcrosoft.com>
 <20121126135911.2F1D33E187C@localhost> <51A719A5.50906@epfl.ch>
Message-ID: <CACRpkdb9F+wJ0hkNqPTP34r3JAEp2s07Q8U24fD6oCdj7MqCFA@mail.gmail.com>

On Thu, May 30, 2013 at 11:19 AM, Florian Vaussard
<florian.vaussard at epfl.ch> wrote:

> Even if work is progressing towards
> having gpio-controlled reset pins [1], some boards still need GPIOs to
> be exported to userspace for other functionalities.

Which are these?

When I have inquired I have heard all kind of horrible things:

- Userspace replicating drivers/leds/leds-gpio.c to
  turn on/off and even PWM (!) LEDs from userspace, when we have
  a standard sysfs interface for LEDs.

- Userspace replicating drivers/input/keyboard/gpio_keys[_polled].c
  to "just read this one button" instead of going through the
  Linux input subsystem like everyone else.

- Userspace replicating drivers/regulator/gpio-regulator.c
  to "turn on just this one voltage source".

All invalid reasons for using the sysfs ABI and trying to do the
kernels work. All creating horrs for users and developers who now
have to stash everything were trying to stach into the device tree
(the above is all perfectly expressed with DT nodes) into their
userspace app and then requiring their users to match a certain
app to a certain board.

The only examples I've really come to accept considers using
things like relays and switches on factory lines where the meaning
(semantics) of the GPIOs can only be properly understood from the
GUI in the userspace APP running that factory line. Or robotics.
In both cases presumably RT processes.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu May 30 16:08:56 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 22:08:56 +0200
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
Message-ID: <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>

On Thu, May 30, 2013 at 12:28 AM, Simon Horman
<horms+renesas at verge.net.au> wrote:

> From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>
> The USB_OVCn pins are alternate options for USB over-current detection
> when using a 3.3V USB interface. As they're not mandatory they can be
> used independently of the USB PENC pins. Don't group the USB_OVCn and
> PENC pins to avoid conflicts when the USB_OVCn pins are used by another
> function.
>
> Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas at verge.net.au>

OK, Acked-by, do you want me to take this as a fix in the pinctrl
tree for v3.10?

Just asking because Simon usually takes everything else relating to
the SH. ...

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Thu May 30 16:13:21 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 May 2013 22:13:21 +0200
Subject: [PATCH 0/3] at_hdmac: dt dma bindings update
In-Reply-To: <20130530172649.GC3767@intel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <20130530172649.GC3767@intel.com>
Message-ID: <20130530201321.GE23653@game.jcrosoft.org>

On 22:56 Thu 30 May     , Vinod Koul wrote:
> On Thu, May 30, 2013 at 06:08:20PM +0200, ludovic.desroches at atmel.com wrote:
> > From: Ludovic Desroches <ludovic.desroches at atmel.com>
> > 
> > Hi,
> > 
> > This set of patches update the dt dma binding for at_hdmac since we need one
> > more parameter. In order to keep backward compatibility, an existing cell will
> > be used to add this parameter. Since the content of that cell will become a
> > magic value due to the concatenation of the two parameters, it is time to
> > use macros.
> which tree is this targetted to be applied? 

arm-soc as this depends on alreadied applied cleanup I've 
> 
> Arnd, can you review this series and ack if this needs to be applied thru
> dmaengine?

I prefer the invert

Best Regards,
J.
> 
> --
> ~Vinod
> > 
> > Regards
> > 
> > Ludovic Desroches (3):
> >   ARM: at91: dt: add header to define at_hdmac configuration
> >   ARM: at91: dt: switch DMA DT bindings to pre-processor
> >   at_hdmac: add FIFO configuration parameter to DMA DT binding
> > 
> >  .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
> >  arch/arm/boot/dts/at91sam9g45.dtsi                 |  5 ++--
> >  arch/arm/boot/dts/at91sam9n12.dtsi                 | 11 +++++----
> >  arch/arm/boot/dts/at91sam9x5.dtsi                  | 17 +++++++-------
> >  arch/arm/boot/dts/sama5d3.dtsi                     | 19 +++++++--------
> >  drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++----
> >  include/dt-bindings/dma/at91.h                     | 27 ++++++++++++++++++++++
> >  7 files changed, 81 insertions(+), 30 deletions(-)
> >  create mode 100644 include/dt-bindings/dma/at91.h
> > 
> > -- 
> > 1.7.11.3
> > 
> 
> -- 


From tony at atomide.com  Thu May 30 16:18:54 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 May 2013 13:18:54 -0700
Subject: MUSB multiplatform work?
In-Reply-To: <20130528163548.GC28253@arwen.pp.htv.fi>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
Message-ID: <20130530201854.GB6467@atomide.com>

* Felipe Balbi <balbi at ti.com> [130528 09:42]:
> Hi,
> 
> On Mon, May 27, 2013 at 05:02:09PM +0200, Arnd Bergmann wrote:
> > Hi Felipe,
> > 
> > We've gone through remaining work items for getting the ARM kernel
> > to full multiplatform support again, and MUSB came up. I'm sure you
> > have your own thoughts on this, but I'd like to know if there is
> > already a plan in place.
> > 
> > From what I can see, the driver in PIO mode should almost work
> > on multiple platforms, but there are a couple of compile-time
> > dependencies in it that need to be turned into run-time conditionals.
> > In particular the TUSB version seem sufficiently different that
> > it needs some extra work to be a true run-time option.
> 
> yeah, TUSB layer is quite messy, all the others should be doable though.

TUSB we can make depend on ARMv7, the only implementation we have
is for omap2420, which is ARMv6. This should solve the issue for
ARMv7 multiplatform builds for now.
 
> > The DMA support as far as I can tell has never been intended to
> > be usable in a multiplatform setup, but that also seems doable.
> 
> we're looking into dmaengine for that but will take a lot of work to
> have something usable.

TUSB would work with dmaengine, but AFAIK we're still missing the
dmaengine configuration options to support increasing device end
FIFO address.
 
> > Looking just at the #ifdef statements in the driver, I found
> > that the following things need to be addressed:
> > 
> > * abstract musb_write_fifo and musb_read_fifo into callbacks
> > * move fifo_mode setting into glue driver for runtime selection
> 
> for the fifo mode, I'd rather detect the size of the internal fifo and
> configure it dynamically based on that plus number of endpoints
> configured in the IP.
> 
> > * turn TUSB compile-time switches into run-time conditionals
> > * turn musb_ep_select into run-time switch
> > * make is_dma_capable/is_cppi_enabled/tusb_dma_omap run-time conditionals
> 
> those can be remove, actually. Back at Nokia we did a huge cleanup on
> the DMA programming part, it can be very simple with no ifdefs at all,
> just needs someone to put the work and test on all platforms.
> 
> > * abtract dma_controller_create/destroy interface
> > 
> > Aside from this, a recent discussion with Maxime has brought up
> > that the Allwinner A1x platform (mach-sunxi) contains an MUSB variant
> > that is currently used with an independently implemented device driver,
> > see https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/drivers/usb/sun5i_usb
> > I wonder if you have any insight on how that can be integrated into
> > musb, or whether it is likely to be a compatible version to start with.
> 
> just write a glue layer, should be as easy as that :-)

Yes the MUSB code should be able to support it considering the number
of implementations we already have there.

Regards,

Tony



From linus.walleij at linaro.org  Thu May 30 16:21:50 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 22:21:50 +0200
Subject: MUSB multiplatform work?
In-Reply-To: <20130530201854.GB6467@atomide.com>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
 <20130530201854.GB6467@atomide.com>
Message-ID: <CACRpkdZHupVFS+pNADpaJjunPa3fEtyCqLwbL-etHs3gt8EW0Q@mail.gmail.com>

On Thu, May 30, 2013 at 10:18 PM, Tony Lindgren <tony at atomide.com> wrote:

> TUSB would work with dmaengine, but AFAIK we're still missing the
> dmaengine configuration options to support increasing device end
> FIFO address.

Can you elaborate on this? What is the usecase here?

Yours,
Linus Walleij


From tony at atomide.com  Thu May 30 16:31:33 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 May 2013 13:31:33 -0700
Subject: MUSB multiplatform work?
In-Reply-To: <CACRpkdZHupVFS+pNADpaJjunPa3fEtyCqLwbL-etHs3gt8EW0Q@mail.gmail.com>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
 <20130530201854.GB6467@atomide.com>
 <CACRpkdZHupVFS+pNADpaJjunPa3fEtyCqLwbL-etHs3gt8EW0Q@mail.gmail.com>
Message-ID: <20130530203132.GC6467@atomide.com>

* Linus Walleij <linus.walleij at linaro.org> [130530 13:27]:
> On Thu, May 30, 2013 at 10:18 PM, Tony Lindgren <tony at atomide.com> wrote:
> 
> > TUSB would work with dmaengine, but AFAIK we're still missing the
> > dmaengine configuration options to support increasing device end
> > FIFO address.
> 
> Can you elaborate on this? What is the usecase here?

There are many devices where the device FIFO is memory mapped to the
GPMC bus on omaps, like TUSB, OneNAND, smc911x etc. I believe the
only reason why these have not been converted to the dmaengine is
the fact that dmaengine cannot configure the DMA hardware to do
autoincrement and loop over the device FIFO.

You can see an example of this in tusb_omap_dma_program() if you
look at the various dma_params entries and omap_set_dma_* functions.

Regards,

Tony


From florian.vaussard at epfl.ch  Thu May 30 16:38:37 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Thu, 30 May 2013 22:38:37 +0200
Subject: [PATCH 1/2] gpiolib: add gpio_export_with_name
In-Reply-To: <CACRpkdb9F+wJ0hkNqPTP34r3JAEp2s07Q8U24fD6oCdj7MqCFA@mail.gmail.com>
References: <20121121101259.GQ4398@game.jcrosoft.org>
 <1353492849-29397-1-git-send-email-plagnioj@jcrosoft.com>
 <20121126135911.2F1D33E187C@localhost> <51A719A5.50906@epfl.ch>
 <CACRpkdb9F+wJ0hkNqPTP34r3JAEp2s07Q8U24fD6oCdj7MqCFA@mail.gmail.com>
Message-ID: <51A7B8CD.4080702@epfl.ch>

Hello Linus,

On 05/30/2013 10:03 PM, Linus Walleij wrote:
> On Thu, May 30, 2013 at 11:19 AM, Florian Vaussard
> <florian.vaussard at epfl.ch> wrote:
>
>> Even if work is progressing towards
>> having gpio-controlled reset pins [1], some boards still need GPIOs to
>> be exported to userspace for other functionalities.
>
> Which are these?
>

Sorry, I should have been more precise.

> When I have inquired I have heard all kind of horrible things:
>
> - Userspace replicating drivers/leds/leds-gpio.c to
>    turn on/off and even PWM (!) LEDs from userspace, when we have
>    a standard sysfs interface for LEDs.
>
> - Userspace replicating drivers/input/keyboard/gpio_keys[_polled].c
>    to "just read this one button" instead of going through the
>    Linux input subsystem like everyone else.
>
> - Userspace replicating drivers/regulator/gpio-regulator.c
>    to "turn on just this one voltage source".
>
> All invalid reasons for using the sysfs ABI and trying to do the
> kernels work. All creating horrs for users and developers who now
> have to stash everything were trying to stach into the device tree
> (the above is all perfectly expressed with DT nodes) into their
> userspace app and then requiring their users to match a certain
> app to a certain board.
>

100% agree with you.

> The only examples I've really come to accept considers using
> things like relays and switches on factory lines where the meaning
> (semantics) of the GPIOs can only be properly understood from the
> GUI in the userspace APP running that factory line. Or robotics.
> In both cases presumably RT processes.
>

Indeed, I work in a robotics lab :-) One of our board (mach-imx/
mx31moboard*.c) controls for example the multiplexing of two cameras
sharing the same acquisition bus (I know, a bit hackish).
I developed a similar board with an OMAP3. Such control do not
fit well in the above-mentioned cases, but we do not need RT processes.

Best regards,

Florian


From tony at atomide.com  Thu May 30 16:54:49 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 May 2013 13:54:49 -0700
Subject: MUSB multiplatform work?
In-Reply-To: <20130530201854.GB6467@atomide.com>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
 <20130530201854.GB6467@atomide.com>
Message-ID: <20130530205448.GD6467@atomide.com>

* Tony Lindgren <tony at atomide.com> [130530 13:25]:
> 
> TUSB we can make depend on ARMv7, the only implementation we have
> is for omap2420, which is ARMv6. This should solve the issue for
> ARMv7 multiplatform builds for now.

Sorry mean depend on !ARMv7. But thinking about it more, that does
not make much sense as it would break things for omap2plus_defconfig
at least which is multiplatform v6 and v7. For now TUSB can be made
to depend on MACH_NOKIA_N8X0. I doubt that anybody is using the add
on cards for H4 boards any longer..

Regards,

Tony


From tony at atomide.com  Thu May 30 17:00:26 2013
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 May 2013 14:00:26 -0700
Subject: [PATCH] ARM: OMAP2+: omap-usb-host: Fix memory leaks
In-Reply-To: <1369400818-31625-1-git-send-email-rogerq@ti.com>
References: <1369400818-31625-1-git-send-email-rogerq@ti.com>
Message-ID: <20130530210025.GE6467@atomide.com>

Hi Roger,

* Roger Quadros <rogerq at ti.com> [130524 06:12]:
> Fix memory leaks in the error path.
> Also, use platform_device_register_full() to allocate
> the platform devices and set platform data.

If you need this for the v3.10-rc, you should describe why this patch
is needed and ideally have some oops or regression causing commit
listed. Care to update the description for that?

Regards,

Tony
 
> Signed-off-by: Roger Quadros <rogerq at ti.com>
> ---
>  arch/arm/mach-omap2/usb-host.c |  106 +++++++++++++++++++++-------------------
>  1 files changed, 56 insertions(+), 50 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> index aa27d7f..609b330 100644
> --- a/arch/arm/mach-omap2/usb-host.c
> +++ b/arch/arm/mach-omap2/usb-host.c
> @@ -28,6 +28,7 @@
>  #include <linux/io.h>
>  #include <linux/gpio.h>
>  #include <linux/usb/phy.h>
> +#include <linux/usb/nop-usb-xceiv.h>
>  
>  #include "soc.h"
>  #include "omap_device.h"
> @@ -560,7 +561,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>  	struct regulator_init_data *reg_data;
>  	struct fixed_voltage_config *config;
>  	struct platform_device *pdev;
> -	int ret;
> +	struct platform_device_info pdevinfo;
> +	int ret = -ENOMEM;
>  
>  	supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
>  	if (!supplies)
> @@ -571,7 +573,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>  
>  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
>  	if (!reg_data)
> -		return -ENOMEM;
> +		goto err_data;
>  
>  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
>  	reg_data->consumer_supplies = supplies;
> @@ -580,39 +582,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
>  			GFP_KERNEL);
>  	if (!config)
> -		return -ENOMEM;
> +		goto err_config;
> +
> +	config->supply_name = kstrdup(name, GFP_KERNEL);
> +	if (!config->supply_name)
> +		goto err_supplyname;
>  
> -	config->supply_name = name;
>  	config->gpio = gpio;
>  	config->enable_high = polarity;
>  	config->init_data = reg_data;
>  
>  	/* create a regulator device */
> -	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> -	if (!pdev)
> -		return -ENOMEM;
> +	memset(&pdevinfo, 0, sizeof(pdevinfo));
> +	pdevinfo.name = reg_name;
> +	pdevinfo.id = PLATFORM_DEVID_AUTO;
> +	pdevinfo.data = config;
> +	pdevinfo.size_data = sizeof(*config);
>  
> -	pdev->id = PLATFORM_DEVID_AUTO;
> -	pdev->name = reg_name;
> -	pdev->dev.platform_data = config;
> +	pdev = platform_device_register_full(&pdevinfo);
> +	if (IS_ERR(pdev)) {
> +		ret = PTR_ERR(pdev);
> +		pr_err("%s: Failed registering regulator %s for %s : %d\n",
> +				__func__, name, dev_id, ret);
> +		goto err_register;
> +	}
>  
> -	ret = platform_device_register(pdev);
> -	if (ret)
> -		pr_err("%s: Failed registering regulator %s for %s\n",
> -				__func__, name, dev_id);
> +	return 0;
>  
> +err_register:
> +	kfree(config->supply_name);
> +err_supplyname:
> +	kfree(config);
> +err_config:
> +	kfree(reg_data);
> +err_data:
> +	kfree(supplies);
>  	return ret;
>  }
>  
> +#define MAX_STR 20
> +
>  int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
>  {
> -	char *rail_name;
> -	int i, len;
> +	char rail_name[MAX_STR];
> +	int i;
>  	struct platform_device *pdev;
>  	char *phy_id;
> -
> -	/* the phy_id will be something like "nop_usb_xceiv.1" */
> -	len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
> +	struct platform_device_info pdevinfo;
>  
>  	for (i = 0; i < num_phys; i++) {
>  
> @@ -627,25 +643,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
>  			!gpio_is_valid(phy->vcc_gpio))
>  			continue;
>  
> -		/* create a NOP PHY device */
> -		pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
> -		if (!pdev)
> -			return -ENOMEM;
> -
> -		pdev->id = phy->port;
> -		pdev->name = nop_name;
> -		pdev->dev.platform_data = phy->platform_data;
> -
> -		phy_id = kmalloc(len, GFP_KERNEL);
> -		if (!phy_id)
> +		phy_id = kmalloc(MAX_STR, GFP_KERNEL);
> +		if (!phy_id) {
> +			pr_err("%s: kmalloc() failed\n", __func__);
>  			return -ENOMEM;
> +		}
>  
> -		scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
> -					pdev->id);
> -
> -		if (platform_device_register(pdev)) {
> -			pr_err("%s: Failed to register device %s\n",
> -				__func__,  phy_id);
> +		/* create a NOP PHY device */
> +		memset(&pdevinfo, 0, sizeof(pdevinfo));
> +		pdevinfo.name = nop_name;
> +		pdevinfo.id = phy->port;
> +		pdevinfo.data = phy->platform_data;
> +		pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data);
> +
> +		scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d",
> +					phy->port);
> +		pdev = platform_device_register_full(&pdevinfo);
> +		if (IS_ERR(pdev)) {
> +			pr_err("%s: Failed to register device %s : %ld\n",
> +				__func__,  phy_id, PTR_ERR(pdev));
> +			kfree(phy_id);
>  			continue;
>  		}
>  
> @@ -653,26 +670,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
>  
>  		/* Do we need RESET regulator ? */
>  		if (gpio_is_valid(phy->reset_gpio)) {
> -
> -			rail_name = kmalloc(13, GFP_KERNEL);
> -			if (!rail_name)
> -				return -ENOMEM;
> -
> -			scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
> -
> +			scnprintf(rail_name, MAX_STR,
> +					"hsusb%d_reset", phy->port);
>  			usbhs_add_regulator(rail_name, phy_id, "reset",
>  						phy->reset_gpio, 1);
>  		}
>  
>  		/* Do we need VCC regulator ? */
>  		if (gpio_is_valid(phy->vcc_gpio)) {
> -
> -			rail_name = kmalloc(13, GFP_KERNEL);
> -			if (!rail_name)
> -				return -ENOMEM;
> -
> -			scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
> -
> +			scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
>  			usbhs_add_regulator(rail_name, phy_id, "vcc",
>  					phy->vcc_gpio, phy->vcc_polarity);
>  		}
> -- 
> 1.7.4.1
> 


From davidb at codeaurora.org  Thu May 30 17:06:58 2013
From: davidb at codeaurora.org (David Brown)
Date: Thu, 30 May 2013 14:06:58 -0700
Subject: Changes pulled into MSM tree
Message-ID: <20130530210658.GA13171@codeaurora.org>

The following changes have been pulled into the msm tree for my next
pull request.  I expect to send the pull request after these sit in
next for a few days.  The changes can be seen at:

  git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git for-next

Chen Gang (1):
      arch: arm: mach-msm: using strlcpy instead of strncpy

Maxime Ripard (1):
      ARM: msm: Remove init_irq declaration in machine description

Rohit Vaswani (3):
      ARM: msm: Remove gpiomux-v2 and re-organize MSM_GPIOMUX configs
      ARM: msm: Remove unused and unmapped MSM_TLMM_BASE for 8x60
      gpio: msm: Add device tree and irqdomain support for gpio-msm-v2

Stephen Boyd (1):
      ARM: dts: msm: Fix bad register addresses

-- 
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


From linus.walleij at linaro.org  Thu May 30 17:11:02 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 23:11:02 +0200
Subject: [PATCH 1/2] gpiolib: add gpio_export_with_name
In-Reply-To: <51A7B8CD.4080702@epfl.ch>
References: <20121121101259.GQ4398@game.jcrosoft.org>
 <1353492849-29397-1-git-send-email-plagnioj@jcrosoft.com>
 <20121126135911.2F1D33E187C@localhost> <51A719A5.50906@epfl.ch>
 <CACRpkdb9F+wJ0hkNqPTP34r3JAEp2s07Q8U24fD6oCdj7MqCFA@mail.gmail.com>
 <51A7B8CD.4080702@epfl.ch>
Message-ID: <CACRpkdZMj-Xin5PMDWavaWOTCSZF3NBWXk4fG4QXsJzhwBcs_Q@mail.gmail.com>

On Thu, May 30, 2013 at 10:38 PM, Florian Vaussard
<florian.vaussard at epfl.ch> wrote:

> Indeed, I work in a robotics lab :-) One of our board (mach-imx/
> mx31moboard*.c) controls for example the multiplexing of two cameras
> sharing the same acquisition bus (I know, a bit hackish).
> I developed a similar board with an OMAP3. Such control do not
> fit well in the above-mentioned cases, but we do not need RT processes.

It does seem to fit well with V4L and/or the media controller
framework though, or is this one of those "oh, we don't really
like to use V4L so we have this special hack instead" things?

Yours,
Linus Walleij


From olof at lixom.net  Thu May 30 17:11:31 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 30 May 2013 14:11:31 -0700
Subject: [PATCH] ARM: EXYNOS: Consolidate multiple low-level UART port
 definitions
In-Reply-To: <1369888827-9427-1-git-send-email-tushar.behera@linaro.org>
References: <1369888827-9427-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <CAOesGMgt=zvPM7WoHn4VcUkw28j7+HDUvU2n3hNojx7Nr5PqJQ@mail.gmail.com>

Hi,

On Wed, May 29, 2013 at 9:40 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
> There are two definitions for low-level UART ports for Exynos platform.
> CONFIG_S3C_LOWLEVEL_UART_PORT is used for printing "Uncompressing
> Linux... done, booting the kernel." and CONFIG_S3C_UART for other
> low-level messages.
>
> The assumption for both the uart ports is that they are pre-configured
> in the bootloader. Since they are essentially the same always, it
> would be good to consolidate them to use only one macro, in this case
> 'DEBUG_S3C_UART' would be a better option.
>
> 'DEBUG_S3C_UART' is defined only if DEBUG_LL is enabled. We can safely
> disable this option when DEBUG_LL is not defined and we can boot various
> boards with different UART port settings. Only drawback of this
> approach is that when DEBUG_LL is not defined, we would be missing the
> print "Uncompressing Linux... done, booting the kernel."
>
> Since CONFIG_S3C_LOWLEVEL_UART_PORT is still used by other Samsung
> boards, the consolidation applies only for ARCH_EXYNOS.
>
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>

This looks reasonable, but you have to convert the other samsung
platforms too -- it's not ok to ignore them.


-Olof


From linus.walleij at linaro.org  Thu May 30 17:19:33 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 May 2013 23:19:33 +0200
Subject: MUSB multiplatform work?
In-Reply-To: <20130530203132.GC6467@atomide.com>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
 <20130530201854.GB6467@atomide.com>
 <CACRpkdZHupVFS+pNADpaJjunPa3fEtyCqLwbL-etHs3gt8EW0Q@mail.gmail.com>
 <20130530203132.GC6467@atomide.com>
Message-ID: <CACRpkdaUegc7B8awUiQTvFRJHPMWv6hEEsE-2AHtZCDXVEMN9g@mail.gmail.com>

On Thu, May 30, 2013 at 10:31 PM, Tony Lindgren <tony at atomide.com> wrote:

> There are many devices where the device FIFO is memory mapped to the
> GPMC bus on omaps, like TUSB, OneNAND, smc911x etc. I believe the
> only reason why these have not been converted to the dmaengine is
> the fact that dmaengine cannot configure the DMA hardware to do
> autoincrement and loop over the device FIFO.

OK that seems like something pretty generic that we could just add
to the struct dma_slave_config actually, something like:

u32 src_fifoloop;
u32 dst_fifoloop;

Given in # of words on the src/dst address simply, left as zero
for hitting a constant address over and over again.

We'd need both to make space for device->device transfers.

If this is all that is needed to convert them do DMAengine
I'd surely ACK it (FWIW).

Yours,
Linus Walleij


From grant.likely at secretlab.ca  Thu May 30 17:29:45 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 30 May 2013 22:29:45 +0100
Subject: [RFC PATCHv4 6/6] irqchip: TI-Nspire irqchip support
In-Reply-To: <1369480087-24786-7-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-7-git-send-email-dt.tangr@gmail.com>
Message-ID: <20130530212945.C026C3E0A90@localhost>

On Sat, 25 May 2013 21:08:07 +1000, Daniel Tang <dt.tangr at gmail.com> wrote:
> Add support for the interrupt controller on TI-Nspires.
> 
> Signed-off-by: Daniel Tang <dt.tangr at gmail.com>
[...]
> +static void nspire_irq_ack(struct irq_data *irqd)
> +{
> +	void __iomem *base = irq_io_base;
> +
> +	if (irqd->hwirq < FIQ_START)
> +		base += IO_IRQ_BASE;
> +	else
> +		base += IO_FIQ_BASE;
> +
> +	readl(base + IO_RESET);
> +}
> +
> +static void nspire_irq_unmask(struct irq_data *irqd)
> +{
> +	void __iomem *base = irq_io_base;
> +	int irqnr = irqd->hwirq;
> +
> +	if (irqnr < FIQ_START) {
> +		base += IO_IRQ_BASE;
> +	} else {
> +		irqnr -= MAX_INTRS;
> +		base += IO_FIQ_BASE;
> +	}
> +
> +	writel((1<<irqnr), base + IO_ENABLE);
> +}
> +
> +static void nspire_irq_mask(struct irq_data *irqd)
> +{
> +	void __iomem *base = irq_io_base;
> +	int irqnr = irqd->hwirq;
> +
> +	if (irqnr < FIQ_START) {
> +		base += IO_IRQ_BASE;
> +	} else {
> +		irqnr -= FIQ_START;
> +		base += IO_FIQ_BASE;
> +	}
> +
> +	writel((1<<irqnr), base + IO_DISABLE);
> +}
> +
> +static struct irq_chip nspire_irq_chip = {
> +	.name		= "nspire_irq",
> +	.irq_ack	= nspire_irq_ack,
> +	.irq_mask	= nspire_irq_mask,
> +	.irq_unmask	= nspire_irq_unmask,
> +};

Should be using irq_generic_chip here. There is no need to reimplement
the above ack, mask and unmask functions. You should find the
irq_alloc_domain_generic_chips() patch in the tip tree irq/for-arm
branch. That branch is staged for merging in v3.11

Otherwise the patch looks good.

g.



From dinguyen at altera.com  Thu May 30 17:33:50 2013
From: dinguyen at altera.com (Dinh Nguyen)
Date: Thu, 30 May 2013 16:33:50 -0500
Subject: [PATCHv4 3/6] ARM: socfpga: Add support to gate peripheral clocks
In-Reply-To: <20130530194227.4470.3741@quantum>
References: <1369410080-436-1-git-send-email-dinguyen@altera.com>
 <1369410080-436-3-git-send-email-dinguyen@altera.com>
 <20130530194227.4470.3741@quantum>
Message-ID: <1369949630.32076.1.camel@linux-builds1>

On Thu, 2013-05-30 at 12:42 -0700, Mike Turquette wrote:
> Quoting dinguyen at altera.com (2013-05-24 08:41:17)
> > From: Dinh Nguyen <dinguyen at altera.com>
> > 
> > Add support to gate the clocks that directly feed peripherals. For clocks
> > with multiple parents, add the ability to determine the correct parent,
> > and also set parents. Also add support to calculate and set the clocks'
> > rate.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> > Reviewed-by: Pavel Machek <pavel at denx.de>
> > CC: Mike Turquette <mturquette at linaro.org>
> > CC: Arnd Bergmann <arnd at arndb.de>
> > CC: Olof Johansson <olof at lixom.net>
> > Cc: Pavel Machek <pavel at denx.de>
> > CC: <linux at arm.linux.org.uk>
> > 
> 
> Looks OK to me.  Lots of conditionals in socfpga_gate_clk_init, which
> some day might be better to break out into separate clk types.  Not a
> big deal for now:
> 
> Acked-by: Mike Turquette <mturquette at linaro.org>

Thanks Mike.

Arnd, if you don't have any other comments, can you or Olof please apply
this series? Or I can send a new set with Mike's Ack?

Dinh
> 
> > v3:
> > - Addressed comments from Pavel
> > 
> > v2:
> > - Fix space/indent errors
> > - Add streq for strcmp == 0
> > ---
> >  drivers/clk/socfpga/clk.c |  194 ++++++++++++++++++++++++++++++++++++++++++---
> >  1 file changed, 185 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
> > index bd11315..5bb848c 100644
> > --- a/drivers/clk/socfpga/clk.c
> > +++ b/drivers/clk/socfpga/clk.c
> > @@ -24,15 +24,17 @@
> >  #include <linux/of.h>
> >  
> >  /* Clock Manager offsets */
> > -#define CLKMGR_CTRL    0x0
> > -#define CLKMGR_BYPASS 0x4
> > +#define CLKMGR_CTRL    0x0
> > +#define CLKMGR_BYPASS  0x4
> > +#define CLKMGR_L4SRC   0x70
> > +#define CLKMGR_PERPLL_SRC      0xAC
> >  
> >  /* Clock bypass bits */
> > -#define MAINPLL_BYPASS (1<<0)
> > -#define SDRAMPLL_BYPASS (1<<1)
> > -#define SDRAMPLL_SRC_BYPASS (1<<2)
> > -#define PERPLL_BYPASS (1<<3)
> > -#define PERPLL_SRC_BYPASS (1<<4)
> > +#define MAINPLL_BYPASS         (1<<0)
> > +#define SDRAMPLL_BYPASS                (1<<1)
> > +#define SDRAMPLL_SRC_BYPASS    (1<<2)
> > +#define PERPLL_BYPASS          (1<<3)
> > +#define PERPLL_SRC_BYPASS      (1<<4)
> >  
> >  #define SOCFPGA_PLL_BG_PWRDWN          0
> >  #define SOCFPGA_PLL_EXT_ENA            1
> > @@ -41,6 +43,17 @@
> >  #define SOCFPGA_PLL_DIVF_SHIFT 3
> >  #define SOCFPGA_PLL_DIVQ_MASK          0x003F0000
> >  #define SOCFPGA_PLL_DIVQ_SHIFT 16
> > +#define SOCFGPA_MAX_PARENTS    3
> > +
> > +#define SOCFPGA_L4_MP_CLK              "l4_mp_clk"
> > +#define SOCFPGA_L4_SP_CLK              "l4_sp_clk"
> > +#define SOCFPGA_NAND_CLK               "nand_clk"
> > +#define SOCFPGA_NAND_X_CLK             "nand_x_clk"
> > +#define SOCFPGA_MMC_CLK                        "mmc_clk"
> > +#define SOCFPGA_DB_CLK                 "gpio_db_clk"
> > +
> > +#define div_mask(width)        ((1 << (width)) - 1)
> > +#define streq(a, b) (strcmp((a), (b)) == 0)
> >  
> >  extern void __iomem *clk_mgr_base_addr;
> >  
> > @@ -49,6 +62,9 @@ struct socfpga_clk {
> >         char *parent_name;
> >         char *clk_name;
> >         u32 fixed_div;
> > +       void __iomem *div_reg;
> > +       u32 width;      /* only valid if div_reg != 0 */
> > +       u32 shift;      /* only valid if div_reg != 0 */
> >  };
> >  #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
> >  
> > @@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
> >  
> >         socfpga_clk->hw.hw.init = &init;
> >  
> > -       if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
> > -                       strcmp(clk_name, "sdram_pll")) {
> > +       if (streq(clk_name, "main_pll") ||
> > +               streq(clk_name, "periph_pll") ||
> > +               streq(clk_name, "sdram_pll")) {
> >                 socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
> >                 clk_pll_ops.enable = clk_gate_ops.enable;
> >                 clk_pll_ops.disable = clk_gate_ops.disable;
> > @@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
> >         return clk;
> >  }
> >  
> > +static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
> > +{
> > +       u32 l4_src;
> > +       u32 perpll_src;
> > +
> > +       if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
> > +               l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> > +               return l4_src &= 0x1;
> > +       }
> > +       if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
> > +               l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> > +               return !!(l4_src & 2);
> > +       }
> > +
> > +       perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> > +       if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
> > +               return perpll_src &= 0x3;
> > +       if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
> > +                       streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
> > +                       return (perpll_src >> 2) & 3;
> > +
> > +       /* QSPI clock */
> > +       return (perpll_src >> 4) & 3;
> > +
> > +}
> > +
> > +static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
> > +{
> > +       u32 src_reg;
> > +
> > +       if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
> > +               src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> > +               src_reg &= ~0x1;
> > +               src_reg |= parent;
> > +               writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
> > +       } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
> > +               src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
> > +               src_reg &= ~0x2;
> > +               src_reg |= (parent << 1);
> > +               writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
> > +       } else {
> > +               src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> > +               if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
> > +                       src_reg &= ~0x3;
> > +                       src_reg |= parent;
> > +               } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
> > +                       streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
> > +                       src_reg &= ~0xC;
> > +                       src_reg |= (parent << 2);
> > +               } else {/* QSPI clock */
> > +                       src_reg &= ~0x30;
> > +                       src_reg |= (parent << 4);
> > +               }
> > +               writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
> > +       }
> > +
> > +       return 0;
> > +}
> > +
> > +static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
> > +       unsigned long parent_rate)
> > +{
> > +       struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
> > +       u32 div = 1, val;
> > +
> > +       if (socfpgaclk->fixed_div)
> > +               div = socfpgaclk->fixed_div;
> > +       else if (socfpgaclk->div_reg) {
> > +               val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
> > +               val &= div_mask(socfpgaclk->width);
> > +               if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
> > +                       div = val + 1;
> > +               else
> > +                       div = (1 << val);
> > +       }
> > +
> > +       return parent_rate / div;
> > +}
> > +
> > +static struct clk_ops gateclk_ops = {
> > +       .recalc_rate = socfpga_clk_recalc_rate,
> > +       .get_parent = socfpga_clk_get_parent,
> > +       .set_parent = socfpga_clk_set_parent,
> > +};
> > +
> > +static void __init socfpga_gate_clk_init(struct device_node *node,
> > +       const struct clk_ops *ops)
> > +{
> > +       u32 clk_gate[2];
> > +       u32 div_reg[3];
> > +       u32 fixed_div;
> > +       struct clk *clk;
> > +       struct socfpga_clk *socfpga_clk;
> > +       const char *clk_name = node->name;
> > +       const char *parent_name[SOCFGPA_MAX_PARENTS];
> > +       struct clk_init_data init;
> > +       int rc;
> > +       int i = 0;
> > +
> > +       socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
> > +       if (WARN_ON(!socfpga_clk))
> > +               return;
> > +
> > +       rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
> > +       if (rc)
> > +               clk_gate[0] = 0;
> > +
> > +       if (clk_gate[0]) {
> > +               socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
> > +               socfpga_clk->hw.bit_idx = clk_gate[1];
> > +
> > +               gateclk_ops.enable = clk_gate_ops.enable;
> > +               gateclk_ops.disable = clk_gate_ops.disable;
> > +       }
> > +
> > +       rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
> > +       if (rc)
> > +               socfpga_clk->fixed_div = 0;
> > +       else
> > +               socfpga_clk->fixed_div = fixed_div;
> > +
> > +       rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
> > +       if (!rc) {
> > +               socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
> > +               socfpga_clk->shift = div_reg[1];
> > +               socfpga_clk->width = div_reg[2];
> > +       } else {
> > +               socfpga_clk->div_reg = 0;
> > +       }
> > +
> > +       of_property_read_string(node, "clock-output-names", &clk_name);
> > +
> > +       init.name = clk_name;
> > +       init.ops = ops;
> > +       init.flags = 0;
> > +       while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
> > +                       of_clk_get_parent_name(node, i)) != NULL)
> > +               i++;
> > +
> > +       init.parent_names = parent_name;
> > +       init.num_parents = i;
> > +       socfpga_clk->hw.hw.init = &init;
> > +
> > +       clk = clk_register(NULL, &socfpga_clk->hw.hw);
> > +       if (WARN_ON(IS_ERR(clk))) {
> > +               kfree(socfpga_clk);
> > +               return;
> > +       }
> > +       rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
> > +       if (WARN_ON(rc))
> > +               return;
> > +}
> > +
> >  static void __init socfpga_pll_init(struct device_node *node)
> >  {
> >         socfpga_clk_init(node, &clk_pll_ops);
> > @@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
> >  }
> >  CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
> >  
> > +static void __init socfpga_gate_init(struct device_node *node)
> > +{
> > +       socfpga_gate_clk_init(node, &gateclk_ops);
> > +}
> > +CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
> > +
> >  void __init socfpga_init_clocks(void)
> >  {
> >         struct clk *clk;
> > -- 
> > 1.7.9.5
> 





From stepanm at codeaurora.org  Thu May 30 17:45:20 2013
From: stepanm at codeaurora.org (Stepan Moskovchenko)
Date: Thu, 30 May 2013 14:45:20 -0700
Subject: [PATCH] arm: Prevent memory aliasing on non-LPAE kernels
Message-ID: <1369950320-22784-1-git-send-email-stepanm@codeaurora.org>

Some LPAE-capable systems may use a Device Tree containing
memory nodes that describe memory extending beyond the 4GB
physical address boundary. Ignore or truncate these memory
nodes on kernels that have not been built with LPAE
support, to prevent the extended physical addresses from
being truncated and aliasing with physical addresses below
the 4GB boundary.

Signed-off-by: Stepan Moskovchenko <stepanm at codeaurora.org>
---
 arch/arm/kernel/devtree.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index bee7f9d..24bc80b 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -26,6 +26,18 @@

 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 {
+#ifndef CONFIG_ARM_LPAE
+	if (base > ((phys_addr_t)~0)) {
+		pr_crit("Ignoring memory at 0x%08llx due to lack of LPAE support\n",
+			base);
+		return;
+	}
+
+	if (size > ((phys_addr_t)~0))
+		size = ((phys_addr_t)~0);
+
+	/* arm_add_memory() already checks for the case of base + size > 4GB */
+#endif
 	arm_add_memory(base, size);
 }

--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation



From jgunthorpe at obsidianresearch.com  Thu May 30 18:10:54 2013
From: jgunthorpe at obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 30 May 2013 16:10:54 -0600
Subject: [PATCH] arm: Prevent memory aliasing on non-LPAE kernels
In-Reply-To: <1369950320-22784-1-git-send-email-stepanm@codeaurora.org>
References: <1369950320-22784-1-git-send-email-stepanm@codeaurora.org>
Message-ID: <20130530221054.GA31643@obsidianresearch.com>

On Thu, May 30, 2013 at 02:45:20PM -0700, Stepan Moskovchenko wrote:
>  void __init early_init_dt_add_memory_arch(u64 base, u64 size)
>  {
> +#ifndef CONFIG_ARM_LPAE
> +	if (base > ((phys_addr_t)~0)) {

The #ifdef is probably not necessary here, simply checking that
base/size can be represented in a phys_addr_t is enough.

> +		pr_crit("Ignoring memory at 0x%08llx due to lack of LPAE support\n",
> +			base);
> +		return;
> +	}
> +
> +	if (size > ((phys_addr_t)~0))
> +		size = ((phys_addr_t)~0);

A similar printk as arm_add_memory for this one too?

                printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
                        "32-bit physical address space\n", (long long)start);

Regards,
Jason


From arnd at arndb.de  Thu May 30 18:24:13 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 00:24:13 +0200
Subject: [PATCH] arm: Prevent memory aliasing on non-LPAE kernels
In-Reply-To: <1369950320-22784-1-git-send-email-stepanm@codeaurora.org>
References: <1369950320-22784-1-git-send-email-stepanm@codeaurora.org>
Message-ID: <3054064.aJsgTxiNUL@wuerfel>

On Thursday 30 May 2013 14:45:20 Stepan Moskovchenko wrote:
> 
>  void __init early_init_dt_add_memory_arch(u64 base, u64 size)
>  {
> +#ifndef CONFIG_ARM_LPAE
> +       if (base > ((phys_addr_t)~0)) {
> +               pr_crit("Ignoring memory at 0x%08llx due to lack of LPAE support\n",
> +                       base);
> +               return;
> +       }
> +
> +       if (size > ((phys_addr_t)~0))
> +               size = ((phys_addr_t)~0);
> +
> +       /* arm_add_memory() already checks for the case of base + size > 4GB */
> +#endif
>         arm_add_memory(base, size);
>  }

This looks wrong for the case where 'base' is between >0 and 4GB and 'size'
makes it spill over the 4GB boundary. You need to set
'size = (phys_addr_t)~0 - base' then.

	Arnd


From arno at natisbad.org  Thu May 30 18:28:56 2013
From: arno at natisbad.org (Arnaud Ebalard)
Date: Fri, 31 May 2013 00:28:56 +0200
Subject: [PATCH v5 12/13] ARM: kirkwood: remove redundant DT board files
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-13-git-send-email-sebastian.hesselbarth@gmail.com>
 <8738t4q1kv.fsf@natisbad.org>
 <20130530193708.GC31290@titan.lakedaemon.net>
Message-ID: <87txlknluf.fsf@natisbad.org>

Hi,

Jason Cooper <jason at lakedaemon.net> writes:

>> For instance 6bd98481ab34 (arm: kirkwood: NETGEAR ReadyNAS Duo v2 init
>> PCIe via DT) currently sitting in jcooper/mvebu/pcie_kirkwood removes
>> the PCIE init routine in board-readynas.c, and yours remove ge00
>> init. With both applied, the whole file can go away.
>> 
>> AFAICT, this may be the case soon for:
>> 
>>  arch/arm/mach-kirkwood/board-iconnect.c   (36e5722089)
>>  arch/arm/mach-kirkwood/board-mplcec4.c    (9470fbfb8d)
>>  arch/arm/mach-kirkwood/board-nsa310.c     (40fa8e5da2)
>>  arch/arm/mach-kirkwood/board-readynas.c   (6bd98481ab)
>>  arch/arm/mach-kirkwood/board-ts219.c      (259e234608)
>
> Would you mind putting a patch together (for after v3.10 drops) to do
> this?  If you applied Sebastian's series on top of mvebu/pcie_kirkwood,
> that should get you almost there.  The last half of his series is going
> in after v3.10...

Something like the quick quilt-generated patch at the end of this email
(done after a dummy merge of Sebastian's set in mvebu/pcie_kirkwood)? I
will take a look at what remains after Sebastian's set hit one of your
branch but I guess he will have included most of what is in the patch to
help you with the merge.

Anyway, at the end here is what DT board files would remain:

$ ls -1 arch/arm/mach-kirkwood/board-*.c
arch/arm/mach-kirkwood/board-dnskw.c
arch/arm/mach-kirkwood/board-dt.c
arch/arm/mach-kirkwood/board-lsxl.c
arch/arm/mach-kirkwood/board-ts219.c

Just one question though: the removal of MACH_*_DT in Kconfig removes
the automatic selection of useful board specific options like
ARM_APPENDED_DTB, ARM_ATAG_DTB_COMPAT, POWER_RESET_RESTART,
POWER_RESET_QNAP. Is that expected?

> You may want to try merging in mvebu/boards and mvebu/soc.  Those have
> the changes to use dt for the restart and power-off drivers.  That'll
> allow us to empty out a few more board files.  mvebu/dt also has a patch
> from Valentin allowing us to remove the keymile board as well.

yes. After a merge w/ mvebu/boards to get restart and poweroff would
allow to get rid of board-ts219.c and board-lsxl.c, leaving mainly
board-dnskw.c.

Cheers,

a+

Index: linux/arch/arm/mach-kirkwood/board-iconnect.c
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/board-iconnect.c	2013-05-30 23:38:53.652311676 +0200
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-iconnect.c
- *
- * Iomega i-connect Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include "common.h"
-
Index: linux/arch/arm/mach-kirkwood/Makefile
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/Makefile	2013-05-30 23:38:53.652311676 +0200
+++ linux/arch/arm/mach-kirkwood/Makefile	2013-05-30 23:38:53.644311636 +0200
@@ -19,9 +19,6 @@
 obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
-obj-$(CONFIG_MACH_DB88F628X_BP_DT)	+= board-db88f628x-bp.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)	+= board-dnskw.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
-obj-$(CONFIG_MACH_MPLCEC4_DT)		+= board-mplcec4.o
-obj-$(CONFIG_MACH_READYNAS_DT)		+= board-readynas.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
Index: linux/arch/arm/mach-kirkwood/board-db88f628x-bp.c
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/board-db88f628x-bp.c	2013-05-30 23:38:53.652311676 +0200
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,24 +0,0 @@
-/*
- * Saeed Bishara <saeed at marvell.com>
- *
- * Marvell DB-88F628{1,2}-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/mv643xx_eth.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-void __init db88f628x_init(void)
-{
-	kirkwood_ge00_init(&db88f628x_ge00_data);
-}
Index: linux/arch/arm/mach-kirkwood/board-mplcec4.c
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/board-mplcec4.c	2013-05-30 23:38:53.652311676 +0200
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2012 MPL AG, Switzerland
- * Stefan Peter <s.peter at mpl.ch>
- *
- * arch/arm/mach-kirkwood/board-mplcec4.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include "common.h"
-
-void __init mplcec4_init(void)
-{
-}
-
-
-
Index: linux/arch/arm/mach-kirkwood/board-readynas.c
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/board-readynas.c	2013-05-30 23:38:53.652311676 +0200
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,21 +0,0 @@
-/*
- * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already
- * converted to DT.
- *
- * Copyright (C) 2013, Arnaud EBALARD <arno at natisbad.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-
-void __init netgear_readynas_init(void)
-{
-}
Index: linux/arch/arm/mach-kirkwood/common.h
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/common.h	2013-05-30 23:38:53.652311676 +0200
+++ linux/arch/arm/mach-kirkwood/common.h	2013-05-30 23:38:53.648311656 +0200
@@ -55,16 +55,6 @@
 void kirkwood_clk_init(void);
 
 /* board init functions for boards not fully converted to fdt */
-#ifdef CONFIG_MACH_DREAMPLUG_DT
-void dreamplug_init(void);
-#else
-static inline void dreamplug_init(void) {};
-#endif
-#ifdef CONFIG_MACH_GURUPLUG_DT
-void guruplug_dt_init(void);
-#else
-static inline void guruplug_dt_init(void) {};
-#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
@@ -77,94 +67,12 @@
 static inline void dnskw_init(void) {};
 #endif
 
-#ifdef CONFIG_MACH_ICONNECT_DT
-void iconnect_init(void);
-#else
-static inline void iconnect_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_IB62X0_DT
-void ib62x0_init(void);
-#else
-static inline void ib62x0_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_DOCKSTAR_DT
-void dockstar_dt_init(void);
-#else
-static inline void dockstar_dt_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_GOFLEXNET_DT
-void goflexnet_init(void);
-#else
-static inline void goflexnet_init(void) {};
-#endif
-
 #ifdef CONFIG_MACH_LSXL_DT
 void lsxl_init(void);
 #else
 static inline void lsxl_init(void) {};
 #endif
 
-#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
-void iomega_ix2_200_init(void);
-#else
-static inline void iomega_ix2_200_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
-void km_kirkwood_init(void);
-#else
-static inline void km_kirkwood_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_DB88F628X_BP_DT
-void db88f628x_init(void);
-#else
-static inline void db88f628x_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_MPLCEC4_DT
-void mplcec4_init(void);
-#else
-static inline void mplcec4_init(void) {};
-#endif
-
-#if defined(CONFIG_MACH_INETSPACE_V2_DT) || \
-	defined(CONFIG_MACH_NETSPACE_V2_DT) || \
-	defined(CONFIG_MACH_NETSPACE_MAX_V2_DT) || \
-	defined(CONFIG_MACH_NETSPACE_LITE_V2_DT) || \
-	defined(CONFIG_MACH_NETSPACE_MINI_V2_DT)
-void ns2_init(void);
-#else
-static inline void ns2_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_OPENBLOCKS_A6_DT
-void openblocks_a6_init(void);
-#else
-static inline void openblocks_a6_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_READYNAS_DT
-void netgear_readynas_init(void);
-#else
-static inline void netgear_readynas_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_TOPKICK_DT
-void usi_topkick_init(void);
-#else
-static inline void usi_topkick_init(void) {};
-#endif
-
-#ifdef CONFIG_MACH_CLOUDBOX_DT
-void cloudbox_init(void);
-#else
-static inline void cloudbox_init(void) {};
-#endif
-
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
Index: linux/arch/arm/mach-kirkwood/Kconfig
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/Kconfig	2013-05-30 23:38:53.652311676 +0200
+++ linux/arch/arm/mach-kirkwood/Kconfig	2013-05-30 23:38:53.648311656 +0200
@@ -140,13 +140,6 @@
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Kirkwood using flattened device tree.
 
-config MACH_DB88F628X_BP_DT
-	bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
-	help
-	  Say 'Y' here if you want your kernel to support the Marvell
-	  DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
-	  Device Tree).
-
 config MACH_DLINK_KIRKWOOD_DT
 	bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
@@ -163,22 +156,6 @@
 	  Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
 	  Flattened Device Tree.
 
-config MACH_MPLCEC4_DT
-	bool "MPL CEC4 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  MPL CEC4 (Flattened Device Tree).
-
-config MACH_READYNAS_DT
-	bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
-	select ARCH_KIRKWOOD_DT
-	select ARM_APPENDED_DTB
-	select ARM_ATAG_DTB_COMPAT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
-
 config MACH_TS219_DT
 	bool "Device Tree for QNAP TS-11X, TS-21X NAS"
 	select ARCH_KIRKWOOD_DT
Index: linux/arch/arm/configs/kirkwood_defconfig
===================================================================
--- linux.orig/arch/arm/configs/kirkwood_defconfig	2013-05-30 23:38:53.596311398 +0200
+++ linux/arch/arm/configs/kirkwood_defconfig	2013-05-30 23:41:42.293147920 +0200
@@ -32,9 +32,6 @@
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
 CONFIG_MACH_LSXL_DT=y
-CONFIG_MACH_MPLCEC4_DT=y
-CONFIG_MACH_NSA310_DT=y
-CONFIG_MACH_READYNAS_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PREEMPT=y
Index: linux/arch/arm/mach-kirkwood/board-dt.c
===================================================================
--- linux.orig/arch/arm/mach-kirkwood/board-dt.c	2013-05-30 23:38:53.616311497 +0200
+++ linux/arch/arm/mach-kirkwood/board-dt.c	2013-05-30 23:45:41.782335483 +0200
@@ -113,16 +113,6 @@
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
-	if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
-	    of_machine_is_compatible("marvell,db-88f6282-bp"))
-		db88f628x_init();
-
-	if (of_machine_is_compatible("mpl,cec4"))
-		mplcec4_init();
-
-	if (of_machine_is_compatible("netgear,readynas-duo-v2"))
-		netgear_readynas_init();
-
 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 


From khilman at linaro.org  Thu May 30 18:33:02 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Thu, 30 May 2013 15:33:02 -0700
Subject: build failure: linux-next: ARM defconfigs: imx_v4_v5, imx_v6_v7
Message-ID: <87fvx43xpd.fsf@linaro.org>

Hello,

The SPI driver for IMX started failing in linux-next (next-20130530)
where the previous tag build fine.  Below is the build error[1],
followed by the the commit[2] that I think introduced the problem.  It
appears to be some missing (or extra) curly braces.

Full console build logs are here:
https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=imx_v4_v5_defconfig,label=kernel_cloud/64/console
https://ci.linaro.org/jenkins/job/khilman-kernel-arm-next/arch=arm,defconfig=imx_v6_v7_defconfig,label=kernel_cloud/64/console

Kevin

[1]
/work/kernel/next/drivers/spi/spi-imx.c: In function ?spi_imx_setupxfer?:
/work/kernel/next/drivers/spi/spi-imx.c:703:2: warning: no return statement in function returning non-void [-Wreturn-type]
/work/kernel/next/drivers/spi/spi-imx.c: At top level:
/work/kernel/next/drivers/spi/spi-imx.c:705:9: error: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?->? token
/work/kernel/next/drivers/spi/spi-imx.c:707:2: error: expected identifier or ?(? before ?return?
/work/kernel/next/drivers/spi/spi-imx.c:708:1: error: expected identifier or ?(? before ?}? token
/work/kernel/next/drivers/spi/spi-imx.c: In function ?spi_imx_probe?:
/work/kernel/next/drivers/spi/spi-imx.c:783:2: warning: left shift count >= width of type [enabled by default]

[2]
commit 24778be20f87d5aadb19624fc768b3159fa43efc
Author: Stephen Warren <swarren at wwwdotorg.org>
Date:   Tue May 21 20:36:35 2013 -0600

    spi: convert drivers to use bits_per_word_mask
    
    Fill in the recently added spi_master.bits_per_word_mask field in as
    many drivers as possible. Make related cleanups, such as removing any
    redundant error-checking, or empty setup callbacks.
    
    Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
    Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
    Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>



From swarren at wwwdotorg.org  Thu May 30 18:41:12 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 30 May 2013 16:41:12 -0600
Subject: build failure: linux-next: ARM defconfigs: imx_v4_v5, imx_v6_v7
In-Reply-To: <87fvx43xpd.fsf@linaro.org>
References: <87fvx43xpd.fsf@linaro.org>
Message-ID: <51A7D588.1070605@wwwdotorg.org>

On 05/30/2013 04:33 PM, Kevin Hilman wrote:
> Hello,
> 
> The SPI driver for IMX started failing in linux-next (next-20130530)
> where the previous tag build fine.  Below is the build error[1],
> followed by the the commit[2] that I think introduced the problem.  It
> appears to be some missing (or extra) curly braces.

Sorry about that. Sachin Kamat <sachin.kamat at linaro.org> has already
sent a patch, which Mark has applied, so this should be fixed in the
next linux-next. Unfortunately, linux-spi at vger.kernel.org doesn't seem
to be archived anywhere, so I can't link to it. Oh, I guess gitweb has it:

https://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=topic/bpw&id=6051426fd0538eac4e28c55a08e4f4fb1c709b65


From swarren at wwwdotorg.org  Thu May 30 19:03:30 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 30 May 2013 17:03:30 -0600
Subject: [PATCH v10 01/12] mfd: DT bindings for the palmas family MFD
In-Reply-To: <51A73908.7020206@ti.com>
References: <1363964122-19201-1-git-send-email-ian@slimlogic.co.uk>
 <1363964122-19201-2-git-send-email-ian@slimlogic.co.uk>
 <5150906F.9040202@wwwdotorg.org> <51A73908.7020206@ti.com>
Message-ID: <51A7DAC2.80602@wwwdotorg.org>

On 05/30/2013 05:33 AM, keerthy wrote:
> 
> On 03/25/2013 11:29 PM, Stephen Warren wrote:
> 
>> On 03/22/2013 08:55 AM, Ian Lartey wrote:
>>> From: Graeme Gregory <gg at slimlogic.co.uk>
>>>
>>> Add the various binding files for the palmas family of chips. There is a
>>> top level MFD binding then a seperate binding for IP blocks on chips.
>>
>>> diff --git a/Documentation/devicetree/bindings/clock/palmas-clk.txt b/Documentation/devicetree/bindings/clock/palmas-clk.txt
>>
>> Where is the reg property; if you're instantiating the clk device as a
>> standalone DT node and driver, it should be possible to retrieve the
>> address of this IP block instance from DT, not using driver-internal APIs.
>>
>> This same comment likely applies everywhere, so I won't repeat it.
>>
>>> +Example:
>>> +
>>> +clk {
>>> +    compatible = "ti,twl6035-clk", "ti,palmas-clk";
>>> +    ti,clk32kg-mode-sleep = <0>;
>>> +    ti,clk32kgaudio-mode-sleep = <0>;
>>
>>> +    #clock-cells = <1>;
>>> +    clock-frequency = <32000000>;
>>> +    clock-names = "clk32kg", "clk32kgaudio";
>>
>> The binding description itself should describe what clocks this node
>> provides and consumes.
>>
>> What is clock-frequency; which clock does it affect?
>>
>> The presence of #clock-cells implies this is a clock provider. This
>> binding should define the format of the clock cells that this property
>> implies. I assume it's just the ID of the output clocks, but what values
>> correspond to which output clocks? That mapping table needs to be listed
>> here.
>>
>> The presence of clock-names implies this is a clock consumer. However,
>> there is no clocks property in the example. Is clks missing from the
>> example, or should this property be clock-output-names instead? If this
>> node is a clock consumer, the list of which clocks it requires should be
>> documented.
>>
>>> diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
>>
>>> +- gpio-controller: mark the device as a GPIO controller
>>> +- gpio-cells = <1>:  GPIO lines are provided.
>>
>> That's #gpio-cells not gpio-cells.
>>
>> I assume that cell simply contains the GPIO ID/number. That should be
>> documented for clarity.
>>
>> Surely gpio-cells should be 2 not 1, so there is space for flags. At
>> least an "inverted" or "active-low" flag should be included; GPIO
>> consumers would typically implement that flag in SW, so there' no
>> requirement that the flag only be supported if the HW supports the feature.
>>
>>> +- interrupt-controller : palmas has its own internal IRQs
>>> +- #interrupt-cells : should be set to 2 for IRQ number and flags
>>> +  The first cell is the IRQ number.
>>> +  The second cell is the flags, encoded as the trigger masks from
>>> +  Documentation/devicetree/bindings/interrupts.txt
>>
>> You need "/interrupt-controller" before the filename there.
>>
>>> +- interrupt-parent : The parent interrupt controller.
>>
>> If this IP block has interrupt outputs, it should require an
>> "interrupts" property too. This is the same concept that drives the need
>> for a reg property. This same comment likely applies everywhere, so I
>> won't repeat it.
>>
>>> diff --git a/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt
>>
>>> +- interrupts: the interrupt outputs of the controller.
>>
>> How many entries are there, what do they mean, and in what order must
>> they appear? (Note that the binding of a node must define the order of
>> the interrupts property, since historically it's been accessed by index,
>> not by name, and all bindings must allow that access method to be used).
>>
>>> +- interrupt-names : Should be the name of irq resource. Each interrupt
>>> +  binds its interrupt-name.
>>
>> The binding needs to define standard names for the entries in this
>> property, or define that interrupts are only retrieved by index, in
>> which case interrupt-names shouldn't be present. This same comment
>> likely applies everywhere, so I won't repeat it.
>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
>>
>>> +Required properties:
>> ...
>>
>> I believe the Palmas devices have many separate I2C addresses, even
>> buses, which are I think are at least partially independently SW
>> configurable. In that case, the reg property for this node should
>> probably enumerate all the I2C addresses that this chip responds to, so
>> that they can each be passed down to the child nodes.
> 
> 
> Stephen,
> 
> The palmas devices do have multiple I2C slave IDs. From OMAP5 as the master
> all the palmas slave devices are connected via I2C1 bus.
> 
> I did not understand the SW configurable part. It is more board
> dependent. Correct me if i understood it wrongly.

IIRC (and I may not sine it's been a while since I looked at this),
there are SW registers that can modify the I2C address that the chip
will respond to, so you could access the main I2C address, then program
which other I2C addresses get used.

Or, perhaps I was just thinking of the fact that there are strapping
pins on the chip that affect both the main I2C address, and some/all of
the other I2C addresses, so the driver needs to be told each and every
I2C address, not just one single overall I2C address.


From dgilbert at interlog.com  Thu May 30 19:17:52 2013
From: dgilbert at interlog.com (Douglas Gilbert)
Date: Thu, 30 May 2013 19:17:52 -0400
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <20130530123609.6e2966a66dd7b131961ed052@linux-foundation.org>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
 <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
 <51A704C3.6010109@atmel.com>
 <20130530123609.6e2966a66dd7b131961ed052@linux-foundation.org>
Message-ID: <51A7DE20.5080603@interlog.com>

On 13-05-30 03:36 PM, Andrew Morton wrote:
> On Thu, 30 May 2013 09:50:27 +0200 Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>
>> The review of this patch series was in my TODO list for some time...
>>
>> Today, I magically took time to review it ;-)
>> The patch series is good and I (even if it is too late) here is my:
>>
>> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>
>> I do not know if the series can be stacked for inclusion in 3.10-rc but
>> the resolution of this bug can help a lot (as Douglas is saying in
>> subsequent email...).
>
> We can do that, but looking through the discussion and changelogs I
> can't seem to find a usable description of what impact the bug (and its
> fix) have upon end-users.
>
> A nicely packaged description of that impact would help grease the
> wheels, please.

How about this:

The members of Atmel's at91sam9x5 family (9x5) have
a broken RTC interrupt mask register (AT91_RTC_IMR).
It does not reflect enabled interrupts but instead
always returns zero.

The kernel's rtc-at91rm9200 driver handles the RTC
for the 9x5 family. Currently when the date/time is
set, an interrupt is generated and this driver neglects
to handle the interrupt. The kernel complains about the
un-handled interrupt and disables it henceforth. This
not only breaks the RTC function, but since that
interrupt is shared (Atmel's SYS interrupt) then other
things break as well (e.g. the debug port no longer
accepts characters).

Tested on the at91sam9g25. Bug confirmed by Atmel.

Edit as you please.

Doug Gilbert



From linux at baker-net.org.uk  Thu May 30 19:19:01 2013
From: linux at baker-net.org.uk (Adam Baker)
Date: Fri, 31 May 2013 00:19:01 +0100
Subject: Kirkwood CPU Freq driver
In-Reply-To: <20130528215126.GF7678@lunn.ch>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
 <20130526180513.GF31290@titan.lakedaemon.net>
 <51A5234D.9030100@baker-net.org.uk> <20130528215126.GF7678@lunn.ch>
Message-ID: <51A7DE65.4090108@baker-net.org.uk>

On 28/05/13 22:51, Andrew Lunn wrote:
>> I've now tested with the first of these patches applied and the
>> >changes from the second added to my .config
>> >
>> >To get it to work I had to follow the instructions in the
>> >Documentation to add the cpus entry to kirkwood.dtsi so I'll post
>> >that as a patch in a day or two but after doing that I have a
>> >working cpufreq driver.
> Great that you got it working. Something must of changed in the
> generic code, since originally a cpu node was not required.
>
> The clocks are not needed in node, so please don't list them.
>
Andrew, I just tried testing without the clocks line in the .dtsi and I 
get the messages below in dmesg

[   18.554990] ERROR: could not get clock /cpus/cpu at 0:cpu_clk(0)
[   18.560840] kirkwood-cpufreq kirkwood-cpufreq: Unable to get cpuclk
[   18.567154] kirkwood-cpufreq: probe of kirkwood-cpufreq failed with 
error -2

looking at the code in kirkwood_cpufreq_probe() this is what I would 
expect. Unless I've missed something the driver is simply advertising 
that it needs those clocks and as they presumably are not gateable it 
may be safe to not bother reserving them but I don't know the code well 
enough to make that decision.

Having now looked at the range of kirkwood SoCs I see oretthat there is 
a 88F632X family that include 2 processor cores. The cpus definitions 
therefore theoretically ought to live in kirkwood-6281.dtsi and 
kirkwood-6282.dtsi. The only 2 boards I can see that don't include one 
of those two at present are kirkwood-km for which the SoC data isn't 
published and kirkwood-nsa310 which seems to simply be missing pinmux 
information for things like the sata ports.

Would everyone prefer to see the cpus node in the 628x.dtsi files or 
should it go in kirkwood.dtsi until support for the 88F632X family is added?

Regards

Adam


From horms at verge.net.au  Thu May 30 20:17:35 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 May 2013 09:17:35 +0900
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
Message-ID: <20130531001735.GA26684@verge.net.au>

On Thu, May 30, 2013 at 10:08:56PM +0200, Linus Walleij wrote:
> On Thu, May 30, 2013 at 12:28 AM, Simon Horman
> <horms+renesas at verge.net.au> wrote:
> 
> > From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> >
> > The USB_OVCn pins are alternate options for USB over-current detection
> > when using a 3.3V USB interface. As they're not mandatory they can be
> > used independently of the USB PENC pins. Don't group the USB_OVCn and
> > PENC pins to avoid conflicts when the USB_OVCn pins are used by another
> > function.
> >
> > Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> 
> OK, Acked-by, do you want me to take this as a fix in the pinctrl
> tree for v3.10?
> 
> Just asking because Simon usually takes everything else relating to
> the SH. ...

This was a pull request from my tree to arm-soc, so thats they way
I was planning to handle things.

Olof, Arnd,

should I re-spin the pull request to include Linus's ack?


From kgene.kim at samsung.com  Thu May 30 20:38:16 2013
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 31 May 2013 09:38:16 +0900
Subject: [PATCH 00/14] Random LPAE-related patches
In-Reply-To: <20130530150307.GU7483@mudshark.cambridge.arm.com>
References: <1368810473-26070-1-git-send-email-will.deacon@arm.com>
 <51A7549D.9000103@gmail.com>
 <20130530150307.GU7483@mudshark.cambridge.arm.com>
Message-ID: <019601ce5d97$23f75660$6be60320$%kim@samsung.com>

Will Deacon wrote:
> 
> On Thu, May 30, 2013 at 02:31:09PM +0100, Subash Patel wrote:
> > Thanks for these patches. I have tested these patches on exynos5440
> > platform. It hasnt affected LPAE functionality for us from previous
> > versions(posted by Cyril). You can use "Tested-By: Subash Patel
> > <subash.rp at samsung.com>" as you deem necessary.
> 
> Thanks Subash. I'll add your tag and send a pull to Russell when he's back
> from holiday.
> 
Sounds good, so we can support LPAE on exynos5440 with mainline soon.

Thanks.

- Kukjin



From davem at davemloft.net  Thu May 30 20:55:49 2013
From: davem at davemloft.net (David Miller)
Date: Thu, 30 May 2013 17:55:49 -0700 (PDT)
Subject: [PATCH v5 00/13] net: mv643xx_eth DT support and fixes
In-Reply-To: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20130530.175549.407800685811475192.davem@davemloft.net>

From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date: Wed, 29 May 2013 21:32:42 +0200

> For the patches above I suggest to take Patches 1-6 through David
> Miller's branch, and Patches 7-12 through Jason Cooper's when the
> former have appeared on mainline linux. The patch set has been based
> on v3.10-rc3.

Patches 1-6 applied to net-next, and patch #1 queued up for -stable.

Thanks!


From weiyj.lk at gmail.com  Thu May 30 21:07:36 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Fri, 31 May 2013 09:07:36 +0800
Subject: [PATCH -next v2] dmaengine: ste_dma40: fix error return code in
 d40_probe()
In-Reply-To: <CAHp75Vf+ifmn62vRNZbqpVX1hnqeUkenzvY81gZLenFkEJ9pFA@mail.gmail.com>
References: <CAPgLHd-gjJ6ju3HyhiQi98YFGojvU3aYSTn7SOe4NhQPY1r++w@mail.gmail.com>
 <CAHp75Vf+ifmn62vRNZbqpVX1hnqeUkenzvY81gZLenFkEJ9pFA@mail.gmail.com>
Message-ID: <CAPgLHd-Gj0UXLdMYdQyGtyHY8T_c=XENc-=SZ=nejCKMiAFXkQ@mail.gmail.com>

On 05/31/2013 02:29 AM, Andy Shevchenko wrote:
> On Thu, May 30, 2013 at 7:32 AM, Wei Yongjun <weiyj.lk at gmail.com> wrote:
>> In many of the error handling case, the return value 'ret' not set
>> and 0 will be return from d40_probe() even if error, but we should
>> return a negative error code instead in those error handling case.
>> This patch fixed them, and also removed useless variable 'err'.
> Hold on, please.
>
>> --- a/drivers/dma/ste_dma40.c
>> +++ b/drivers/dma/ste_dma40.c
>> @@ -3619,6 +3618,7 @@ static int __init d40_probe(struct platform_device *pdev)
>>                 if (IS_ERR(base->lcpa_regulator)) {
>>                         d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
>>                         base->lcpa_regulator = NULL;
>> +                       ret = PTR_ERR(base->lcpa_regulator);
> Is it really what we want?
>
> I thixh you may remove that NULL assignment.

Ohh, I will move the ret = PTR_ERR(base->lcpa_regulator) above the NULL
assignment, the failure path test for base->lcpa_regulator to release regulator.

        if (base->lcpa_regulator) {
            regulator_disable(base->lcpa_regulator);
            regulator_put(base->lcpa_regulator);
        }

>
>
>>                         goto failure;
>>                 }
>>
>> @@ -3647,8 +3647,8 @@ static int __init d40_probe(struct platform_device *pdev)
>>         d40_hw_init(base);
>>
>>         if (np) {
>> -               err = of_dma_controller_register(np, d40_xlate, NULL);
>> -               if (err && err != -ENODEV)
>> +               ret = of_dma_controller_register(np, d40_xlate, NULL);
>> +               if (ret && ret != -ENODEV)
> >From the discussion of dw_dmac I remember we decide that ENODEV check
> is redundant.

Get it, I will remove the ENODEV check.

Thanks,
Yongjun Wei



From mturquette at linaro.org  Thu May 30 21:16:06 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 18:16:06 -0700
Subject: [RFC PATCHv4 3/6] clk: TI-Nspire clock drivers
In-Reply-To: <1369480087-24786-4-git-send-email-dt.tangr@gmail.com>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <1369480087-24786-4-git-send-email-dt.tangr@gmail.com>
Message-ID: <20130531011606.21525.92648@quantum>

Quoting Daniel Tang (2013-05-25 04:08:04)
> diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c
> new file mode 100644
> index 0000000..2546f7d
> --- /dev/null
> +++ b/drivers/clk/clk-nspire.c
> @@ -0,0 +1,155 @@
> +/*
> + *  linux/drivers/clk/clk-nspire.c

Hi Daniel,

It's best not to put any file path here, since it could change in the
future.  Please remove it.

> + *
> + *  Copyright (C) 2013 Daniel Tang <tangrs at tangrs.id.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2, as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#define MHZ (1000 * 1000)
> +
> +#define BASE_CPU_SHIFT         1
> +#define BASE_CPU_MASK          0x7F
> +
> +#define CPU_AHB_SHIFT          12
> +#define CPU_AHB_MASK           0x07
> +
> +#define FIXED_BASE_SHIFT       8
> +#define FIXED_BASE_MASK                0x01
> +
> +#define CLASSIC_BASE_SHIFT     16
> +#define CLASSIC_BASE_MASK      0x1F
> +
> +#define CX_BASE_SHIFT          15
> +#define CX_BASE_MASK           0x3F
> +
> +#define CX_UNKNOWN_SHIFT       21
> +#define CX_UNKNOWN_MASK                0x03
> +
> +struct nspire_clk_info {
> +       u32 base_clock;
> +       u16 base_cpu_ratio;
> +       u16 base_ahb_ratio;
> +};
> +
> +
> +#define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)
> +static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk)
> +{
> +       if (EXTRACT(val, FIXED_BASE))
> +               clk->base_clock = 48 * MHZ;
> +       else
> +               clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
> +
> +       clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN);
> +       clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
> +}
> +
> +static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk)
> +{
> +       if (EXTRACT(val, FIXED_BASE))
> +               clk->base_clock = 27 * MHZ;
> +       else
> +               clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
> +
> +       clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2;
> +       clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
> +}
> +#undef EXTRACT

Any particular reason for the undef?

Rest looks good to me.  If you can respin this patch I'll take it into
clk-next.

Thanks,
Mike


From laurent.pinchart at ideasonboard.com  Thu May 30 21:20:08 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Fri, 31 May 2013 03:20:08 +0200
Subject: [RFC/PATCH v2 2/2] gpio-rcar: Add DT support
In-Reply-To: <CACRpkdb8GYpx3ASzXB7HX5oEpAUBe-yBo0N5Ep9S+DqoE6oCLw@mail.gmail.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369136406-23800-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <CACRpkdb8GYpx3ASzXB7HX5oEpAUBe-yBo0N5Ep9S+DqoE6oCLw@mail.gmail.com>
Message-ID: <4678059.RuWR6CiQ8n@avalon>

Hi Linus,

On Thursday 30 May 2013 19:38:12 Linus Walleij wrote:
> On Tue, May 21, 2013 at 1:40 PM, Laurent Pinchart
> <laurent.pinchart+renesas at ideasonboard.com> wrote:
> > Add DT bindings for the gpio-rcar driver and read the device
> > configuration from the DT node at probe time if available.
> > 
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas at ideasonboard.com>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> I am assuming this will go through Simon's tree?

I've so far pushed GPIO and pinctrl patches for SH through Simon's tree due to 
the many cross-dependencies between SH arch code and the GPIO and pinctrl 
drivers. As the situation now stabilizes, we could now push the patches 
through their respective subsystem trees.

Simon, Linus, any opinion/preference on that ?

> Note:
> > +  - gpio-ranges: Range of pins managed by the GPIO controller as a
> > 4-cells
> > +    tuple using the following syntax.
> > +
> > +    <[phandle of the pin controller node]
> > +     0
> > +     [index of the first pin]
> > +     [number of pins]>
> > +
> > +Please refer to gpio.txt in this directory for details of the common GPIO
> > +bindings used by client devices.
> 
> The above ranges are part of that document.

What about replacing that with

  - gpio-ranges: Range of pins managed by the GPIO controller.

Please refer to gpio.txt in this directory for details of gpio-ranges property 
and the common GPIO bindings used by client devices.

-- 
Regards,

Laurent Pinchart



From mturquette at linaro.org  Thu May 30 21:20:14 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 18:20:14 -0700
Subject: [PATCH] clk: use platform_{get,set}_drvdata()
In-Reply-To: <000401ce581b$a9224600$fb66d200$@samsung.com>
References: <000401ce581b$a9224600$fb66d200$@samsung.com>
Message-ID: <20130531012014.21525.39312@quantum>

Quoting Jingoo Han (2013-05-23 18:11:46)
> Use the wrapper functions for getting and setting the driver data using
> platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev,
> so we can directly pass a struct platform_device.
> 
> Signed-off-by: Jingoo Han <jg1.han at samsung.com>

Taken into clk-next.

Thanks for the patch,
Mike

> ---
>  drivers/clk/clk-twl6040.c |    4 ++--
>  drivers/clk/clk-wm831x.c  |    2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c
> index 3af729b..1ada79a 100644
> --- a/drivers/clk/clk-twl6040.c
> +++ b/drivers/clk/clk-twl6040.c
> @@ -95,14 +95,14 @@ static int twl6040_clk_probe(struct platform_device *pdev)
>         if (IS_ERR(clkdata->clk))
>                 return PTR_ERR(clkdata->clk);
>  
> -       dev_set_drvdata(&pdev->dev, clkdata);
> +       platform_set_drvdata(pdev, clkdata);
>  
>         return 0;
>  }
>  
>  static int twl6040_clk_remove(struct platform_device *pdev)
>  {
> -       struct twl6040_clk *clkdata = dev_get_drvdata(&pdev->dev);
> +       struct twl6040_clk *clkdata = platform_get_drvdata(pdev);
>  
>         clk_unregister(clkdata->clk);
>  
> diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
> index 16ed068..0d3c04e 100644
> --- a/drivers/clk/clk-wm831x.c
> +++ b/drivers/clk/clk-wm831x.c
> @@ -384,7 +384,7 @@ static int wm831x_clk_probe(struct platform_device *pdev)
>         if (IS_ERR(clkdata->clkout))
>                 return PTR_ERR(clkdata->clkout);
>  
> -       dev_set_drvdata(&pdev->dev, clkdata);
> +       platform_set_drvdata(pdev, clkdata);
>  
>         return 0;
>  }
> -- 
> 1.7.10.4


From mturquette at linaro.org  Thu May 30 21:25:09 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 18:25:09 -0700
Subject: [PATCH 0/4] clk, mfd: u8540 clock tree definition
In-Reply-To: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
Message-ID: <20130531012509.21525.90187@quantum>

Quoting Philippe Begnic (2013-05-27 05:41:28)
> From: Philippe Begnic <philippe.begnic at st.com>
> 
> Create U8540 clock tree definitions for common clock framework
> 

The clock changes look good to me.  How did you want to merge the
patches?

Regards,
Mike

> Philippe Begnic (4):
>   clk: ux500: Pass clock base adresses in initcall for u8540 and u9540
>   mfd: db8500: Update register definition for u8540 clock
>   mfd: db8500: Update BML clock register for db8580
>   clk: ux500: Clocks definition for u8540
> 
>  arch/arm/mach-ux500/cpu.c                 |    6 +-
>  drivers/clk/ux500/u8540_clk.c             |  564 ++++++++++++++++++++++++++++-
>  drivers/clk/ux500/u9540_clk.c             |    4 +-
>  drivers/mfd/db8500-prcmu.c                |    1 +
>  drivers/mfd/dbx500-prcmu-regs.h           |    1 +
>  include/linux/mfd/abx500/ab8500-sysctrl.h |    4 +-
>  include/linux/mfd/dbx500-prcmu.h          |   12 +
>  include/linux/platform_data/clk-ux500.h   |    6 +-
>  8 files changed, 587 insertions(+), 11 deletions(-)
> 
> -- 
> 1.7.9.5


From weiyj.lk at gmail.com  Thu May 30 21:50:07 2013
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Fri, 31 May 2013 09:50:07 +0800
Subject: [PATCH -next v3] dmaengine: ste_dma40: fix error return code in
 d40_probe()
Message-ID: <CAPgLHd_uppj5twah650PqQnYw1JZp-GKrnBF+ZrXRarJQSNkug@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

In many of the error handling case, the return value 'ret' not set
and 0 will be return from d40_probe() even if error, but we should
return a negative error code instead in those error handling case.
This patch fixed them, and also removed useless variable 'err'.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
v2 -> v3: move NULL assign below set ret, and remove redundant ENODEV check.
---
 drivers/dma/ste_dma40.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 7f23d45..88e3cd4 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3506,7 +3506,6 @@ static int __init d40_probe(struct platform_device *pdev)
 {
 	struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
 	struct device_node *np = pdev->dev.of_node;
-	int err;
 	int ret = -ENOENT;
 	struct d40_base *base = NULL;
 	struct resource *res = NULL;
@@ -3618,6 +3617,7 @@ static int __init d40_probe(struct platform_device *pdev)
 		base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
 		if (IS_ERR(base->lcpa_regulator)) {
 			d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
+			ret = PTR_ERR(base->lcpa_regulator);
 			base->lcpa_regulator = NULL;
 			goto failure;
 		}
@@ -3633,13 +3633,13 @@ static int __init d40_probe(struct platform_device *pdev)
 	}
 
 	base->initialized = true;
-	err = d40_dmaengine_init(base, num_reserved_chans);
-	if (err)
+	ret = d40_dmaengine_init(base, num_reserved_chans);
+	if (ret)
 		goto failure;
 
 	base->dev->dma_parms = &base->dma_parms;
-	err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
-	if (err) {
+	ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
+	if (ret) {
 		d40_err(&pdev->dev, "Failed to set dma max seg size\n");
 		goto failure;
 	}
@@ -3647,8 +3647,8 @@ static int __init d40_probe(struct platform_device *pdev)
 	d40_hw_init(base);
 
 	if (np) {
-		err = of_dma_controller_register(np, d40_xlate, NULL);
-		if (err && err != -ENODEV)
+		ret = of_dma_controller_register(np, d40_xlate, NULL);
+		if (ret)
 			dev_err(&pdev->dev,
 				"could not register of_dma_controller\n");
 	}



From shawn.guo at linaro.org  Thu May 30 21:51:03 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 May 2013 09:51:03 +0800
Subject: [PATCH v7 08/11] ASoC: phycore-ac97: Add DT support
In-Reply-To: <1369925513-19329-9-git-send-email-mpa@pengutronix.de>
References: <1369925513-19329-1-git-send-email-mpa@pengutronix.de>
 <1369925513-19329-9-git-send-email-mpa@pengutronix.de>
Message-ID: <20130531015101.GA22536@S2101-09.ap.freescale.net>

On Thu, May 30, 2013 at 04:51:50PM +0200, Markus Pargmann wrote:
> Add devicetree support for phycore-ac97 driver.
> 
> platform_of_node and cpu_of_node are set according to the fsl,audmux
> phandle.
> 
> This patch adds handling of ac97 reset functions according to fsl ac97
> support. They are setup from here to avoid board specific code in the
> generic fsl-ssi driver.
> 
> This patch changes the handling of pca100 boards from non-DT to DT only.
> pcm043 is still handled without DT.
> 
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>

Compiling phycore-ac97 as module,  I got the following errors.

  CC [M]  sound/soc/fsl/phycore-ac97.o
sound/soc/fsl/phycore-ac97.c:305:1: error: redefinition of ?__inittest?
sound/soc/fsl/phycore-ac97.c:146:1: note: previous definition of ?__inittest? was here
sound/soc/fsl/phycore-ac97.c:305:1: error: redefinition of ?init_module?
sound/soc/fsl/phycore-ac97.c:146:1: note: previous definition of ?init_module? was here
sound/soc/fsl/phycore-ac97.c:305:1: error: redefinition of ?__exittest?
sound/soc/fsl/phycore-ac97.c:147:1: note: previous definition of ?__exittest? was here
sound/soc/fsl/phycore-ac97.c:305:1: error: redefinition of ?cleanup_module?
sound/soc/fsl/phycore-ac97.c:147:1: note: previous definition of ?cleanup_module? was here
make[4]: *** [sound/soc/fsl/phycore-ac97.o] Error 1

Shawn



From horms at verge.net.au  Thu May 30 22:07:48 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 May 2013 11:07:48 +0900
Subject: [PATCH 2/2] ARM: shmobile: r8A7779: fix Ether device name
In-Reply-To: <51A744A4.5020909@cogentembedded.com>
References: <1369645206-3682-1-git-send-email-horms+renesas@verge.net.au>
 <1369645206-3682-3-git-send-email-horms+renesas@verge.net.au>
 <20130528040043.GL13532@quad.lixom.net>
 <51A744A4.5020909@cogentembedded.com>
Message-ID: <20130531020748.GA29074@verge.net.au>

On Thu, May 30, 2013 at 04:23:00PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 28-05-2013 8:00, Olof Johansson wrote:
> 
> >>From: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> 
> >>While recasting the commit "ARM: shmobile: R8A7779: add Ether support", I made a
> >>typo in the platform device's name: used underscore instead of hyphen.
> 
> >Minor nit: if this has been merged, then including the SHA is useful too.
> 
>    Yes, it has been merged in 3.10. Simon, can you do this without
> me reposting the patch? The defective commit's SHA1 ID is
> dace48d04dee46a3409d5e13cd98031522e46377.
>    Note that there is analogous R8A7778 Ether fix, the SHA1 for its
> defective commit is 524219146a89aee5366326c225ccd71231419d89.

Thanks, I will fix up the commit messages.


From horms at verge.net.au  Thu May 30 22:44:38 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 May 2013 11:44:38 +0900
Subject: [PATCH] dmaengine: shdma: fix a build failure on platforms with
 no DMA support
In-Reply-To: <51A77CF1.7040105@ti.com>
References: <Pine.LNX.4.64.1305301650290.29171@axis700.grange>
 <51A77CF1.7040105@ti.com>
Message-ID: <20130531024438.GB32564@verge.net.au>

On Thu, May 30, 2013 at 11:23:13AM -0500, Dan Murphy wrote:
> On 05/30/2013 11:02 AM, Guennadi Liakhovetski wrote:
> > On platforms with no support for the shdma dmaengine driver build is
> > currently failing with
> >
> > drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> > drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'
> >
> > Fix the breakage by defining shdma_chan_filter to NULL in such
> > configurations.
> >
> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> > ---
> >
> > This is for "next." Compile-tested only. I'll test it on hardware next 
> > week, but I don't think it shall break anything.
> >
> >  include/linux/sh_dma.h |    4 ++++
> >  1 files changed, 4 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
> > index b64d6be..1fd8a20 100644
> > --- a/include/linux/sh_dma.h
> > +++ b/include/linux/sh_dma.h
> > @@ -99,6 +99,10 @@ struct sh_dmae_pdata {
> >  #define CHCR_TE	0x00000002
> >  #define CHCR_IE	0x00000004
> >  
> > +#if IS_ENABLED(CONFIG_SH_DMAE)
> >  bool shdma_chan_filter(struct dma_chan *chan, void *arg);
> > +#else
> > +#define shdma_chan_filter NULL
> Would this not be better as a
> #else
> static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg)
> {
>     return false;
> }
> #endif
> 
> Otherwise runtime will call a NULL pointer
> 
> > +#endif
> >  
> >  #endif

Hi Guennadi,

thanks for this. I will wait for a refresh (as we discussed earlier today).
Can I confirm that this is a fix for v3.10? If so, could ou note
that when you post your revised patch?

Thanks


From Yalin.Wang at sonymobile.com  Thu May 30 22:56:31 2013
From: Yalin.Wang at sonymobile.com (Wang, Yalin)
Date: Fri, 31 May 2013 10:56:31 +0800
Subject: A bug about system call on ARM
In-Reply-To: <20130530114112.GH7483@mudshark.cambridge.arm.com>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
Message-ID: <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>

Hi Will,

Thanks for your patch ,

But I found  I don't have ct_user_exit  macro 
In my arch/arm/kernel/entry-common.S 

My kernel version is 3.4.0 

I have add the file as attachment,

Could you make a patch for this file ?

Thank you !

-----Original Message-----
From: Will Deacon [mailto:will.deacon at arm.com] 
Sent: Thursday, May 30, 2013 7:41 PM
To: Wang, Yalin
Cc: 'richard -rw- weinberger'; 'linux-arch at vger.kernel.org'; 'linux-kernel at vger.kernel.org'; 'linux-arm-kernel at lists.infradead.org'
Subject: Re: A bug about system call on ARM

On Thu, May 30, 2013 at 10:09:49AM +0100, Will Deacon wrote:
> On Thu, May 30, 2013 at 02:41:42AM +0100, Wang, Yalin wrote:
> > If you have some patch for this issue, I can do the test for it .
> 
> I'll have a look at cooking something which uses an exception table 
> entry to rewind the PC and retry the system call. That's simpler than 
> directly injecting a user page fault from the system call path.

Ok, please can you try the following?

Will

--->8

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index bc5bc0a..855926e 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -361,6 +361,15 @@ ENTRY(vector_swi)
 	str	r8, [sp, #S_PSR]		@ Save CPSR
 	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
 	zero_fp
+	enable_irq
+	ct_user_exit
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+	ldr	ip, __cr_alignment
+	ldr	ip, [ip]
+	mcr	p15, 0, ip, c1, c0		@ update control register
+#endif
+	get_thread_info tsk
 
 	/*
 	 * Get the system call number.
@@ -375,9 +384,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
 	tst	r8, #PSR_T_BIT
 	movne	r10, #0				@ no thumb OABI emulation
-	ldreq	r10, [lr, #-4]			@ get SWI instruction
+ USER(	ldreq	r10, [lr, #-4]		)	@ get SWI instruction
 #else
-	ldr	r10, [lr, #-4]			@ get SWI instruction
+ USER(	ldr	r10, [lr, #-4]		)	@ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
 	rev	r10, r10			@ little endian instruction
@@ -392,22 +401,13 @@ ENTRY(vector_swi)
 	/* Legacy ABI only, possibly thumb mode. */
 	tst	r8, #PSR_T_BIT			@ this is SPSR from save_user_regs
 	addne	scno, r7, #__NR_SYSCALL_BASE	@ put OS number in
-	ldreq	scno, [lr, #-4]
+ USER(	ldreq	scno, [lr, #-4]		)
 
 #else
 	/* Legacy ABI only. */
-	ldr	scno, [lr, #-4]			@ get SWI instruction
-#endif
-
-#ifdef CONFIG_ALIGNMENT_TRAP
-	ldr	ip, __cr_alignment
-	ldr	ip, [ip]
-	mcr	p15, 0, ip, c1, c0		@ update control register
+ USER(	ldr	scno, [lr, #-4]		)	@ get SWI instruction
 #endif
-	enable_irq
-	ct_user_exit
 
-	get_thread_info tsk
 	adr	tbl, sys_call_table		@ load syscall table pointer
 
 #if defined(CONFIG_OABI_COMPAT)
@@ -442,6 +442,18 @@ local_restart:
 	eor	r0, scno, #__NR_SYSCALL_BASE	@ put OS number back
 	bcs	arm_syscall	
 	b	sys_ni_syscall			@ not private func
+
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+	/*
+	 * We may have faulted trying to load the SWI instruction due to
+	 * concurrent page aging on another CPU. In this case, return
+	 * back to the swi instruction and fault the page back.
+	 */
+9001:
+	sub	lr, lr, #4
+	str	lr, [sp, #S_PC]
+	b	ret_fast_syscall
+#endif
 ENDPROC(vector_swi)
 
 	/*
-------------- next part --------------
A non-text attachment was scrubbed...
Name: entry-common.S
Type: application/octet-stream
Size: 15071 bytes
Desc: entry-common.S
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130531/acc75b68/attachment-0001.obj>

From tushar.behera at linaro.org  Thu May 30 22:58:16 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 31 May 2013 08:28:16 +0530
Subject: [PATCH] ARM: EXYNOS: Consolidate multiple low-level UART port
 definitions
In-Reply-To: <CAOesGMgt=zvPM7WoHn4VcUkw28j7+HDUvU2n3hNojx7Nr5PqJQ@mail.gmail.com>
References: <1369888827-9427-1-git-send-email-tushar.behera@linaro.org>
 <CAOesGMgt=zvPM7WoHn4VcUkw28j7+HDUvU2n3hNojx7Nr5PqJQ@mail.gmail.com>
Message-ID: <51A811C8.9090509@linaro.org>

On 05/31/2013 02:41 AM, Olof Johansson wrote:
> Hi,
> 
> On Wed, May 29, 2013 at 9:40 PM, Tushar Behera <tushar.behera at linaro.org> wrote:
>> There are two definitions for low-level UART ports for Exynos platform.
>> CONFIG_S3C_LOWLEVEL_UART_PORT is used for printing "Uncompressing
>> Linux... done, booting the kernel." and CONFIG_S3C_UART for other
>> low-level messages.
>>
>> The assumption for both the uart ports is that they are pre-configured
>> in the bootloader. Since they are essentially the same always, it
>> would be good to consolidate them to use only one macro, in this case
>> 'DEBUG_S3C_UART' would be a better option.
>>
>> 'DEBUG_S3C_UART' is defined only if DEBUG_LL is enabled. We can safely
>> disable this option when DEBUG_LL is not defined and we can boot various
>> boards with different UART port settings. Only drawback of this
>> approach is that when DEBUG_LL is not defined, we would be missing the
>> print "Uncompressing Linux... done, booting the kernel."
>>
>> Since CONFIG_S3C_LOWLEVEL_UART_PORT is still used by other Samsung
>> boards, the consolidation applies only for ARCH_EXYNOS.
>>
>> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
> 
> This looks reasonable, but you have to convert the other samsung
> platforms too -- it's not ok to ignore them.
> 

Sure thing. I will update those platforms in a subsequent patchset.

> 
> -Olof
> 


-- 
Tushar Behera


From zhangwm at marvell.com  Thu May 30 22:58:34 2013
From: zhangwm at marvell.com (Neil Zhang)
Date: Fri, 31 May 2013 10:58:34 +0800
Subject: [PATCH v2] bring up pxa988 with DT
Message-ID: <1369969115-4279-1-git-send-email-zhangwm@marvell.com>

This patch is supposed to bring up pxa988 SMP.
will change to use CLOCKSOURCE later.

ChangeLog
V2:
1. use early_init call for handler init.
2. Add sanity check for maximum core count.

Neil Zhang (1):
  ARM: mmp: bring up pxa988 with device tree support

 arch/arm/boot/dts/pxa988-dkb.dts          |   36 ++++++
 arch/arm/boot/dts/pxa988.dtsi             |  189 +++++++++++++++++++++++++++++
 arch/arm/mach-mmp/Kconfig                 |   27 ++++
 arch/arm/mach-mmp/Makefile                |    2 +
 arch/arm/mach-mmp/common.c                |   11 ++-
 arch/arm/mach-mmp/common.h                |    2 +
 arch/arm/mach-mmp/headsmp.S               |  104 ++++++++++++++++
 arch/arm/mach-mmp/include/mach/addr-map.h |    6 +
 arch/arm/mach-mmp/mmpx-dt.c               |   74 +++++++++++
 arch/arm/mach-mmp/platsmp.c               |  167 +++++++++++++++++++++++++
 arch/arm/mach-mmp/reset.c                 |   68 ++++++++++
 arch/arm/mach-mmp/reset.h                 |   28 +++++
 drivers/clk/mmp/Makefile                  |    1 +
 13 files changed, 714 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/pxa988-dkb.dts
 create mode 100644 arch/arm/boot/dts/pxa988.dtsi
 create mode 100644 arch/arm/mach-mmp/headsmp.S
 create mode 100644 arch/arm/mach-mmp/mmpx-dt.c
 create mode 100644 arch/arm/mach-mmp/platsmp.c
 create mode 100644 arch/arm/mach-mmp/reset.c
 create mode 100644 arch/arm/mach-mmp/reset.h

-- 
1.7.4.1



From g.liakhovetski at gmx.de  Thu May 30 23:01:31 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 31 May 2013 05:01:31 +0200 (CEST)
Subject: [PATCH v2] dmaengine: shdma: fix a build failure on platforms with
 no DMA support
Message-ID: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>

On platforms with no support for the shdma dmaengine driver build is
currently failing with

drivers/built-in.o: In function `sh_mobile_sdhi_probe':
drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'

Fix the breakage by defining shdma_chan_filter to NULL in such
configurations.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
---

v2: in "next" shdma_chan_filter() is defined in shdma-base.c, which is 
built if CONFIG_SH_DMAE_BASE is defined. This version uses the correct 
symbol.

This is for "next." Compile-tested only. I'll test it on hardware next 
week, but I don't think it shall break anything.

 include/linux/sh_dma.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index b64d6be..1fd8a20 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -99,6 +99,10 @@ struct sh_dmae_pdata {
 #define CHCR_TE	0x00000002
 #define CHCR_IE	0x00000004
 
+#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
 bool shdma_chan_filter(struct dma_chan *chan, void *arg);
+#else
+#define shdma_chan_filter NULL
+#endif
 
 #endif
-- 
1.7.2.5


From wenyou.yang at atmel.com  Thu May 30 23:09:04 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Fri, 31 May 2013 11:09:04 +0800
Subject: [PATCH 0/2] ARM: dts: add watchdog device tree node in at91 dts files
Message-ID: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>

Hello,

The patches is to add watchdog device tree node for at91 SoC and board dts files.

Since the watchdog is disabled in the at91bootstrap with default configuration,
if you want to use the watchdog in the kernel, you must make sure the watchdog
doesn't be disabled in the at91bootstrap.

It is tested on at91sam9g20ek, at91sam9263ek, at91sam9g25ek
using Documentation/watchdog/src/watchdog-simple.c.

It is based on v3.10-rc3, tested on linux-watchdog git tree as well.

Best Regards,
Wenyou Yang

Wenyou Yang (2):
  ARM: dts: add the watchdog nodes for at91 SoC
  ARM: dts: add the watchdog nodes for at91 boards

 arch/arm/boot/dts/at91sam9263ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    4 ++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |    4 ++++
 arch/arm/boot/dts/at91sam9n12.dtsi          |    6 ++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi           |    6 ++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |    4 ++++
 7 files changed, 32 insertions(+)

-- 
1.7.9.5



From wenyou.yang at atmel.com  Thu May 30 23:10:01 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Fri, 31 May 2013 11:10:01 +0800
Subject: [PATCH 0/2] ARM: dts: add watchdog device tree node in at91 dts files
In-Reply-To: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
References: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <1369969802-7840-1-git-send-email-wenyou.yang@atmel.com>

Hello,

The patches is to add watchdog device tree node for at91 SoC and board dts files.

Since the watchdog is disabled in the at91bootstrap with default configuration,
if you want to use the watchdog in the kernel, you must make sure the watchdog
doesn't be disabled in the at91bootstrap.

It is tested on at91sam9g20ek, at91sam9263ek, at91sam9g25ek
using Documentation/watchdog/src/watchdog-simple.c.

It is based on v3.10-rc3, tested on linux-watchdog git tree as well.

Best Regards,
Wenyou Yang

Wenyou Yang (2):
  ARM: dts: add the watchdog nodes for at91 SoC
  ARM: dts: add the watchdog nodes for at91 boards

 arch/arm/boot/dts/at91sam9263ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    4 ++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |    4 ++++
 arch/arm/boot/dts/at91sam9n12.dtsi          |    6 ++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi           |    6 ++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |    4 ++++
 7 files changed, 32 insertions(+)

-- 
1.7.9.5



From wenyou.yang at atmel.com  Thu May 30 23:11:33 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Fri, 31 May 2013 11:11:33 +0800
Subject: [PATCH 2/2] ARM: dts: add the watchdog nodes for at91 boards
In-Reply-To: <1369969893-7992-1-git-send-email-wenyou.yang@atmel.com>
References: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
 <1369969893-7992-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <1369969893-7992-2-git-send-email-wenyou.yang@atmel.com>

boards include:
at91sam9263ek, at91sam9g20ek, at91sam9m10g45ek, at91sam9n12ek, at91sam9x5ek

Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
---
 arch/arm/boot/dts/at91sam9263ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    4 ++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |    4 ++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |    4 ++++
 5 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 3b82d91..9143842 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -89,6 +89,10 @@
 					reg = <0>;
 				};
 			};
+
+			watchdog at fffffd40 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 6a92c5b..6d6b888 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -106,6 +106,10 @@
 					reg = <1>;
 				};
 			};
+
+			watchdog at fffffd40 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 51d9251b5..03f391a 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -59,6 +59,10 @@
 				status = "okay";
 			};
 
+			watchdog at fffffd40 {
+				status = "okay";
+			};
+
 			mmc0: mmc at fff80000 {
 				pinctrl-0 = <
 					&pinctrl_board_mmc0
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d30e48b..32e073f 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -77,6 +77,10 @@
 					reg = <0>;
 				};
 			};
+
+			watchdog at fffffe40 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 1fa48d2..e60b05a 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -56,6 +56,10 @@
 				status = "okay";
 			};
 
+			watchdog at fffffe40 {
+				status = "okay";
+			};
+
 			pinctrl at fffff400 {
 				mmc0 {
 					pinctrl_board_mmc0: mmc0-board {
-- 
1.7.9.5



From zhangwm at marvell.com  Thu May 30 23:13:37 2013
From: zhangwm at marvell.com (Neil Zhang)
Date: Fri, 31 May 2013 11:13:37 +0800
Subject: [PATCH] ARM: scu: empty scu_enable for !CONFIG_HAVE_ARM_SCU
Message-ID: <1369970017-4588-1-git-send-email-zhangwm@marvell.com>

Use the right config to empty scu_enable.

Signed-off-by: Neil Zhang <zhangwm at marvell.com>
---
 arch/arm/include/asm/smp_scu.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 18d1693..ac93189 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -26,7 +26,7 @@ static inline unsigned long scu_a9_get_base(void)
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_HAVE_ARM_SCU
 void scu_enable(void __iomem *scu_base);
 #else
 static inline void scu_enable(void __iomem *scu_base) {}
-- 
1.7.4.1



From wenyou.yang at atmel.com  Thu May 30 23:11:32 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Fri, 31 May 2013 11:11:32 +0800
Subject: [PATCH 0/2] ARM: dts: add watchdog device tree node in at91 dts files
In-Reply-To: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
References: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <1369969893-7992-1-git-send-email-wenyou.yang@atmel.com>

Hello,

The patches is to add watchdog device tree node for at91 SoC and board dts files.

Since the watchdog is disabled in the at91bootstrap with default configuration,
if you want to use the watchdog in the kernel, you must make sure the watchdog
doesn't be disabled in the at91bootstrap.

It is tested on at91sam9g20ek, at91sam9263ek, at91sam9g25ek
using Documentation/watchdog/src/watchdog-simple.c.

It is based on v3.10-rc3, tested on linux-watchdog git tree as well.

Best Regards,
Wenyou Yang

Wenyou Yang (2):
  ARM: dts: add the watchdog nodes for at91 SoC
  ARM: dts: add the watchdog nodes for at91 boards

 arch/arm/boot/dts/at91sam9263ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    4 ++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |    4 ++++
 arch/arm/boot/dts/at91sam9n12.dtsi          |    6 ++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |    4 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi           |    6 ++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |    4 ++++
 7 files changed, 32 insertions(+)

-- 
1.7.9.5



From wenyou.yang at atmel.com  Thu May 30 23:10:02 2013
From: wenyou.yang at atmel.com (Wenyou Yang)
Date: Fri, 31 May 2013 11:10:02 +0800
Subject: [PATCH 1/2] ARM: dts: add the watchdog nodes for at91 SoC
In-Reply-To: <1369969802-7840-1-git-send-email-wenyou.yang@atmel.com>
References: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
 <1369969802-7840-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <1369969802-7840-2-git-send-email-wenyou.yang@atmel.com>

at91sam9x5, at91sam9n12

Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
---
 arch/arm/boot/dts/at91sam9n12.dtsi |    6 ++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |    6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 8d25f88..7f92f07 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -423,6 +423,12 @@
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
+
+			watchdog at fffffe40 {
+				compatible = "atmel,at91sam9260-wdt";
+				reg = <0xfffffe40 0x10>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..1d32064 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -648,6 +648,12 @@
 				interrupts = <1 4 7>;
 				status = "disabled";
 			};
+
+			watchdog at fffffe40 {
+				compatible = "atmel,at91sam9260-wdt";
+				reg = <0xfffffe40 0x10>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.9.5



From zhangwm at marvell.com  Thu May 30 22:58:35 2013
From: zhangwm at marvell.com (Neil Zhang)
Date: Fri, 31 May 2013 10:58:35 +0800
Subject: [PATCH v2] ARM: mmp: bring up pxa988 with device tree support
In-Reply-To: <1369969115-4279-1-git-send-email-zhangwm@marvell.com>
References: <1369969115-4279-1-git-send-email-zhangwm@marvell.com>
Message-ID: <1369969115-4279-2-git-send-email-zhangwm@marvell.com>

bring up pxa988 with device tree support.

Change-Id: I6fc869b7d5ff8dc6e4eb0042a89429200f7a9fb1
Signed-off-by: Neil Zhang <zhangwm at marvell.com>
---
 arch/arm/boot/dts/pxa988-dkb.dts          |   36 ++++++
 arch/arm/boot/dts/pxa988.dtsi             |  189 +++++++++++++++++++++++++++++
 arch/arm/mach-mmp/Kconfig                 |   27 ++++
 arch/arm/mach-mmp/Makefile                |    2 +
 arch/arm/mach-mmp/common.c                |   11 ++-
 arch/arm/mach-mmp/common.h                |    2 +
 arch/arm/mach-mmp/headsmp.S               |  104 ++++++++++++++++
 arch/arm/mach-mmp/include/mach/addr-map.h |    6 +
 arch/arm/mach-mmp/mmpx-dt.c               |   74 +++++++++++
 arch/arm/mach-mmp/platsmp.c               |  167 +++++++++++++++++++++++++
 arch/arm/mach-mmp/reset.c                 |   68 ++++++++++
 arch/arm/mach-mmp/reset.h                 |   28 +++++
 drivers/clk/mmp/Makefile                  |    1 +
 13 files changed, 714 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/pxa988-dkb.dts
 create mode 100644 arch/arm/boot/dts/pxa988.dtsi
 create mode 100644 arch/arm/mach-mmp/headsmp.S
 create mode 100644 arch/arm/mach-mmp/mmpx-dt.c
 create mode 100644 arch/arm/mach-mmp/platsmp.c
 create mode 100644 arch/arm/mach-mmp/reset.c
 create mode 100644 arch/arm/mach-mmp/reset.h

diff --git a/arch/arm/boot/dts/pxa988-dkb.dts b/arch/arm/boot/dts/pxa988-dkb.dts
new file mode 100644
index 0000000..2cee3ed
--- /dev/null
+++ b/arch/arm/boot/dts/pxa988-dkb.dts
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa988.dtsi"
+
+/ {
+	model = "Marvell PXA988 DKB Development Board";
+	compatible = "mrvl,pxa988-dkb", "mrvl,pxa988";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc {
+		apb at d4000000 {
+			uart1: uart at d4017000 {
+				status = "okay";
+			};
+
+			rtc: rtc at d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa988.dtsi b/arch/arm/boot/dts/pxa988.dtsi
new file mode 100644
index 0000000..567d33d
--- /dev/null
+++ b/arch/arm/boot/dts/pxa988.dtsi
@@ -0,0 +1,189 @@
+/*
+ *  Copyright (C) 2013 Marvell Technology Group Ltd.
+ *  Author: Chao Xie <chao.xie at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+		};
+	};
+
+	gic: interrupt-controller at d1dfe100 {
+		compatible = "arm,cortex-a9-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0xd1dff000 0x1000>,
+		      <0xd1dfe100 0x0100>;
+	};
+
+	L2: l2-cache-controller at d1dfb000 {
+		compatible = "arm,pl310-cache";
+		reg = <0xd1dfb000 0x1000>;
+		arm,data-latency = <2 1 1>;
+		arm,tag-latency = <2 1 1>;
+		arm,pwr-dynamic-clk-gating;
+		arm,pwr-standby-mode;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	local-timer at d1dfe600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0xd1dfe600 0x20>;
+		interrupts = <1 13 0x304>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		axi at d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: wakeupgen at d4282000 {
+				compatible = "mrvl,mmp-intc";
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-wakeup = <0x114 0x3
+						    0x144 0x3>;
+			};
+
+		};
+
+		apb at d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer0: timer at d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <0 13 0x4>;
+			};
+
+			uart1: uart at d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <0 27 0x4>;
+				status = "disabled";
+			};
+
+			uart2: uart at d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <0 28 0x4>;
+				status = "disabled";
+			};
+
+			uart3: uart at d4036000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4036000 0x1000>;
+				interrupts = <0 59 0x4>;
+				status = "disabled";
+			};
+
+			gpio at d4019000 {
+				compatible = "marvell,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio at d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio at d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio at d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio at d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+			};
+
+			twsi1: i2c at d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xd4011000 0x1000>;
+				interrupts = <0 7 0x4>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c at d4037000 {
+				compatible = "mrvl,mmp-twsi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xd4037000 0x1000>;
+				interrupts = <0 54 0x4>;
+				status = "disabled";
+			};
+
+			rtc: rtc at d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <0 5 0x4>,<0 6 0x4>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				status = "disabled";
+			};
+			pmx: pinmux at d401e000 {
+				compatible = "pinconf-single";
+				reg = <0xd401e000 0x330>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				#gpio-range-cells = <3>;
+				ranges;
+
+				pinctrl-single,register-width = <32>;
+				pinctrl-single,function-mask = <7>;
+
+				range: gpio-range {
+					#pinctrl-single,gpio-range-cells = <3>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index ebdda83..0955191 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -107,6 +107,16 @@ config MACH_MMP2_DT
 	  Include support for Marvell MMP2 based platforms using
 	  the device tree.
 
+config MACH_MMPX_DT
+	bool "Support no-PJ/PJ4(ARMv7) platforms from device tree"
+	depends on !CPU_MOHAWK && !CPU_PJ4
+	select CPU_PXA988
+	select USE_OF
+	select PINCTRL
+	select PINCTRL_SINGLE
+	help
+	  Include support for Marvell MMP2 based platforms using
+	  the device tree.
 endmenu
 
 config CPU_PXA168
@@ -123,6 +133,23 @@ config CPU_PXA910
 	help
 	  Select code specific to PXA910
 
+config CPU_PXA988
+	bool
+	select CPU_V7
+	select ARM_GIC
+	select HAVE_SMP
+	select HAVE_ARM_SCU
+	select LOCAL_TIMERS
+	select HAVE_ARM_TWD
+	select COMMON_CLK
+	select CLKSRC_OF
+	select MIGHT_HAVE_CACHE_L2X0
+	help
+	  Say 'Y' here if you want to support the Marvell pxa988-base
+	  platforms.
+	  PXA988 is an SoC with dual-core Cotex-A9 and comunication
+	  processor, code name "Emei".
+
 config CPU_MMP2
 	bool
 	select COMMON_CLK
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 095c155..e572786 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -8,6 +8,7 @@ obj-y				+= common.o devices.o time.o irq.o
 obj-$(CONFIG_CPU_PXA168)	+= pxa168.o
 obj-$(CONFIG_CPU_PXA910)	+= pxa910.o
 obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o
+obj-$(CONFIG_CPU_PXA988)        += platsmp.o headsmp.o reset.o
 
 ifeq ($(CONFIG_COMMON_CLK), )
 obj-y				+= clock.o
@@ -31,5 +32,6 @@ obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
 obj-$(CONFIG_MACH_MMP2_DT)	+= mmp2-dt.o
+obj-$(CONFIG_MACH_MMPX_DT)	+= mmpx-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b79..0c621bc 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -11,6 +11,10 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -36,7 +40,12 @@ static struct map_desc standard_io_desc[] __initdata = {
 		.virtual	= (unsigned long)AXI_VIRT_BASE,
 		.length		= AXI_PHYS_SIZE,
 		.type		= MT_DEVICE,
-	},
+	}, {
+		.pfn		= __phys_to_pfn(MMP_CORE_PERIPH_PHYS_BASE),
+		.virtual	= (unsigned long)MMP_CORE_PERIPH_VIRT_BASE,
+		.length		= MMP_CORE_PERIPH_PHYS_SIZE,
+		.type		= MT_DEVICE,
+	}
 };
 
 void __init mmp_map_io(void)
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b..ea0225f 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,5 +1,7 @@
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
 
+extern struct smp_operations mmp_smp_ops;
+
 extern void timer_init(int irq);
 
 extern void __init icu_init_irq(void);
diff --git a/arch/arm/mach-mmp/headsmp.S b/arch/arm/mach-mmp/headsmp.S
new file mode 100644
index 0000000..2b6177e
--- /dev/null
+++ b/arch/arm/mach-mmp/headsmp.S
@@ -0,0 +1,104 @@
+/*
+ * linux/arch/arm/mach-mmp/headsmp.S
+ *
+ * Copyright (C) 2012 Marvell, Inc.
+ *
+ * Author: Neil Zhang <zhangwm at marvell.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+#include <asm/cache.h>
+#include <asm/assembler.h>
+#include <mach/addr-map.h>
+
+	__CPUINIT
+
+/*
+ * Marvell specific entry point for secondary CPUs.
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate for secondary core, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.
+ */
+	.align L1_CACHE_SHIFT
+
+
+/*
+ * PXA specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(mmp_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	bl	v7_invalidate_l1
+	b	secondary_startup
+ENDPROC(mmp_secondary_startup)
+
+	.align	2
+1:	.long	.
+	.long	pen_release
+
+
+/*
+ * Note: The following code is located into the .data section. This is to
+ *       allow sw_reset_flag and cpu_plugin_handler to be accessed with a
+ *       relative load while we can't rely on any MMU translation.
+ *       Reference from: arch/arm/kernel/sleep.S
+ */
+
+	.data
+	.align
+
+/*
+ * ROM code jumps to this function while waking up from CPU
+ * OFF or software reset state. Physical address of the function is
+ * stored at CA9_WARM_RESET_VECTOR while system is bring up.
+ */
+ENTRY(mmp_cpu_reset_entry)
+	adr	r1, mmp_entry_vectors
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15		@ fetch CPUID
+1:
+	ldr	r2, [r1, r0, lsl #2]    @ get the handler addr for this core
+	cmp	r2, #0
+	movne	pc, r2			@ jump to the handler
+	beq	1b
+ENDPROC(mmp_cpu_reset_entry)
+
+	/* Point to the address that save handlers for each core */
+	.global mmp_entry_vectors
+mmp_entry_vectors:
+	.rept   CONFIG_NR_CPUS
+        .long   0                               @ preserve stack phys ptr here
+	.endr
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
index f88a44c..092005b 100644
--- a/arch/arm/mach-mmp/include/mach/addr-map.h
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -25,6 +25,10 @@
 #define AXI_VIRT_BASE		IOMEM(0xfe200000)
 #define AXI_PHYS_SIZE		0x00200000
 
+#define MMP_CORE_PERIPH_PHYS_BASE	0xd1dfe000
+#define MMP_CORE_PERIPH_VIRT_BASE	IOMEM(0xfe400000)
+#define MMP_CORE_PERIPH_PHYS_SIZE	0x00002000
+
 /* Static Memory Controller - Chip Select 0 and 1 */
 #define SMC_CS0_PHYS_BASE	0x80000000
 #define SMC_CS0_PHYS_SIZE	0x10000000
@@ -43,4 +47,6 @@
 #define CIU_VIRT_BASE		(AXI_VIRT_BASE + 0x82c00)
 #define CIU_REG(x)		(CIU_VIRT_BASE + (x))
 
+#define SCU_VIRT_BASE		(MMP_CORE_PERIPH_VIRT_BASE)
+
 #endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/mmpx-dt.c b/arch/arm/mach-mmp/mmpx-dt.c
new file mode 100644
index 0000000..2ebd057
--- /dev/null
+++ b/arch/arm/mach-mmp/mmpx-dt.c
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmpx-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/regs-apbc.h>
+
+#include "common.h"
+
+/* PXA988 */
+static const struct of_dev_auxdata pxa988_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+void __init pxa988_dt_init_timer(void)
+{
+	extern void __init mmp_dt_init_timer(void);
+	/*
+	 * Is is a SOC timer, and will be used for broadcasting
+	 * when local timers are disabled.
+	 */
+	mmp_dt_init_timer();
+
+	clocksource_of_init();
+}
+
+static void __init pxa988_dt_init_machine(void)
+{
+	l2x0_of_init(0x30800000, 0xFE7FFFFF);
+
+	pxa910_clk_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     pxa988_auxdata_lookup, NULL);
+}
+
+static const char *pxa988_dt_board_compat[] __initdata = {
+	"mrvl,pxa988-dkb",
+	NULL,
+};
+
+DT_MACHINE_START(PXA988_DT, "Marvell PXA988 (Device Tree Support)")
+	.smp		= smp_ops(mmp_smp_ops),
+	.map_io		= mmp_map_io,
+	.init_irq	= irqchip_init,
+	.init_time	= pxa988_dt_init_timer,
+	.init_machine	= pxa988_dt_init_machine,
+	.dt_compat	= pxa988_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/platsmp.c b/arch/arm/mach-mmp/platsmp.c
new file mode 100644
index 0000000..f341a67
--- /dev/null
+++ b/arch/arm/mach-mmp/platsmp.c
@@ -0,0 +1,167 @@
+/*
+ *  linux/arch/arm/mach-mmp/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/mach-types.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+
+#include <mach/irqs.h>
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "reset.h"
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void __cpuinit write_pen_release(int val)
+{
+	pen_release = val;
+	smp_wmb();
+	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+#ifdef CONFIG_HAVE_ARM_SCU
+static void __iomem *scu_get_base_addr(void)
+{
+	return SCU_VIRT_BASE;
+}
+#endif
+
+static inline unsigned int get_core_count(void)
+{
+	u32 ret = 1;
+#ifdef CONFIG_HAVE_ARM_SCU
+	ret = scu_get_core_count(scu_get_base_addr());
+#endif
+
+	return ret;
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __cpuinit mmp_secondary_init(unsigned int cpu)
+{
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+static int __cpuinit mmp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Avoid timer calibration on slave cpus. Use the value calibrated
+	 * on master cpu. Referenced from tegra3
+	 */
+	preset_lpj = loops_per_jiffy;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	write_pen_release(cpu);
+
+	/* reset the cpu, let it branch to the kernel entry */
+	mmp_cpu_power_up(cpu);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init mmp_smp_init_cpus(void)
+{
+	unsigned int i, ncores = get_core_count();
+
+	if (ncores > nr_cpu_ids) {
+		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+			ncores, nr_cpu_ids);
+		ncores = nr_cpu_ids;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+static void __init mmp_smp_prepare_cpus(unsigned int max_cpus)
+{
+	int i;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+#ifdef CONFIG_HAVE_ARM_SCU
+	scu_enable(scu_get_base_addr());
+#endif
+}
+
+struct smp_operations mmp_smp_ops __initdata = {
+	.smp_init_cpus		= mmp_smp_init_cpus,
+	.smp_prepare_cpus	= mmp_smp_prepare_cpus,
+	.smp_secondary_init	= mmp_secondary_init,
+	.smp_boot_secondary	= mmp_boot_secondary,
+};
diff --git a/arch/arm/mach-mmp/reset.c b/arch/arm/mach-mmp/reset.c
new file mode 100644
index 0000000..5eab6cf
--- /dev/null
+++ b/arch/arm/mach-mmp/reset.c
@@ -0,0 +1,68 @@
+/*
+ * linux/arch/arm/mach-mmp/reset.c
+ *
+ * Author:	Neil Zhang <zhangwm at marvell.com>
+ * Copyright:	(C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/smp.h>
+
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+
+#include <mach/addr-map.h>
+
+#include "reset.h"
+
+#define PMU_CC2_AP			APMU_REG(0x0100)
+#define CIU_CA9_WARM_RESET_VECTOR	CIU_REG(0x00d8)
+
+/*
+ * This function is called from boot_secondary to bootup the secondary cpu.
+ */
+void mmp_cpu_power_up(u32 cpu)
+{
+	u32 tmp;
+
+	BUG_ON(cpu == 0);
+
+	tmp = readl(PMU_CC2_AP);
+	if (tmp & CPU_CORE_RST(cpu)) {
+		/* Release secondary core from reset */
+		tmp &= ~(CPU_CORE_RST(cpu)
+			| CPU_DBG_RST(cpu) | CPU_WDOG_RST(cpu));
+		writel(tmp, PMU_CC2_AP);
+	}
+}
+
+void mmp_set_entry_vector(u32 cpu, u32 addr)
+{
+	BUG_ON(cpu >= CONFIG_NR_CPUS);
+
+	mmp_entry_vectors[cpu] = addr;
+	smp_wmb();
+	__cpuc_flush_dcache_area((void *)&mmp_entry_vectors[cpu],
+				sizeof(mmp_entry_vectors[cpu]));
+	outer_clean_range(__pa(&mmp_entry_vectors[cpu]),
+				__pa(&mmp_entry_vectors[cpu + 1]));
+}
+
+static int __init mmp_entry_vector_init(void)
+{
+	int cpu;
+
+	/* We will reset from DDR directly by default */
+	writel(__pa(mmp_cpu_reset_entry), CIU_CA9_WARM_RESET_VECTOR);
+
+	for (cpu = 1; cpu < CONFIG_NR_CPUS; cpu++)
+		mmp_set_entry_vector(cpu, __pa(mmp_secondary_startup));
+}
+
+early_initcall(mmp_entry_vector_init);
diff --git a/arch/arm/mach-mmp/reset.h b/arch/arm/mach-mmp/reset.h
new file mode 100644
index 0000000..5c88c1a
--- /dev/null
+++ b/arch/arm/mach-mmp/reset.h
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/reset.h
+ *
+ * Author:	Neil Zhang <zhangwm at marvell.com>
+ * Copyright:	(C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __RESET_PXA988_H__
+#define __RESET_PXA988_H__
+
+#define CPU_CORE_RST(n)	(1 << ((n) * 4 + 16))
+#define CPU_DBG_RST(n)	(1 << ((n) * 4 + 18))
+#define CPU_WDOG_RST(n)	(1 << ((n) * 4 + 19))
+
+extern u32 mmp_entry_vectors[CONFIG_NR_CPUS];
+
+void mmp_secondary_startup(void);
+void mmp_cpu_reset_entry(void);
+
+void mmp_cpu_power_up(u32 cpu);
+void mmp_set_entry_vector(u32 cpu, u32 addr);
+
+#endif /* __RESET_PXA988_H__ */
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 392d780..59a3f9f7 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -7,3 +7,4 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
 obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
+obj-$(CONFIG_CPU_PXA988) += clk-pxa910.o
-- 
1.7.4.1



From nico at fluxnic.net  Thu May 30 23:54:56 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 30 May 2013 23:54:56 -0400 (EDT)
Subject: A bug about system call on ARM
In-Reply-To: <20130530114112.GH7483@mudshark.cambridge.arm.com>
References: <35FD53F367049845BC99AC72306C23D1610991B85B@CNBJMBX05.corpusers.net>
 <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305302319430.30828@syhkavp.arg>

On Thu, 30 May 2013, Will Deacon wrote:

> On Thu, May 30, 2013 at 10:09:49AM +0100, Will Deacon wrote:
> > On Thu, May 30, 2013 at 02:41:42AM +0100, Wang, Yalin wrote:
> > > If you have some patch for this issue,
> > > I can do the test for it .
> > 
> > I'll have a look at cooking something which uses an exception table entry
> > to rewind the PC and retry the system call. That's simpler than directly
> > injecting a user page fault from the system call path.
> 
> Ok, please can you try the following?
> 
> Will
> 
> --->8
> 
> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> index bc5bc0a..855926e 100644
> --- a/arch/arm/kernel/entry-common.S
> +++ b/arch/arm/kernel/entry-common.S
> @@ -361,6 +361,15 @@ ENTRY(vector_swi)
>  	str	r8, [sp, #S_PSR]		@ Save CPSR
>  	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
>  	zero_fp
> +	enable_irq
> +	ct_user_exit
> +
> +#ifdef CONFIG_ALIGNMENT_TRAP
> +	ldr	ip, __cr_alignment
> +	ldr	ip, [ip]
> +	mcr	p15, 0, ip, c1, c0		@ update control register
> +#endif

This is wrong.  you must set up the align bit in the control register 
_before_ enabling IRQs or an IRQ handler might run without alignment 
fixup.

Otherwise the patch looks good to me.


Nicolas


From balbi at ti.com  Fri May 31 00:00:04 2013
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 31 May 2013 07:00:04 +0300
Subject: MUSB multiplatform work?
In-Reply-To: <20130530205448.GD6467@atomide.com>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
 <20130530201854.GB6467@atomide.com>
 <20130530205448.GD6467@atomide.com>
Message-ID: <20130531040004.GA7879@arwen.pp.htv.fi>

On Thu, May 30, 2013 at 01:54:49PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony at atomide.com> [130530 13:25]:
> > 
> > TUSB we can make depend on ARMv7, the only implementation we have
> > is for omap2420, which is ARMv6. This should solve the issue for
> > ARMv7 multiplatform builds for now.
> 
> Sorry mean depend on !ARMv7. But thinking about it more, that does
> not make much sense as it would break things for omap2plus_defconfig
> at least which is multiplatform v6 and v7. For now TUSB can be made
> to depend on MACH_NOKIA_N8X0. I doubt that anybody is using the add
> on cards for H4 boards any longer..

could also be made to depend on BROKEN. I don't think anyone *really*
cares about that glue layer other than the very few in the world who
still like the nostalgic feeling of booting current linux releases on
n8x0 devices.

-- 
balbi
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From nico at fluxnic.net  Fri May 31 00:03:35 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 31 May 2013 00:03:35 -0400 (EDT)
Subject: =?GB2312?Q?Re=3A_=B4=F0=B8=B4=3A_A_bug_about_system_call_on_ARM?=
In-Reply-To: <ih0015wu30o5nq4ajf437rl7.1369916575726@email.android.com>
References: <ih0015wu30o5nq4ajf437rl7.1369916575726@email.android.com>
Message-ID: <alpine.LFD.2.03.1305302356140.30828@syhkavp.arg>

On Thu, 30 May 2013, Wang, Yalin wrote:

> Hi Will,
> 
> i see your solution,
> i Will test it tomorrow,
> and report the result to you ASAP!

This is good if you can report success without changing any of your 
current configuration.  This issue is worth fixing.

However, as others have mentioned already, you most likely can set 
CONFIG_OABI_COMPAT to n afterwards.  Not only will this make you immune 
to the bug you reported, but that will also make the syscall path more 
efficient as well.


Nicolas


From ming.lei at canonical.com  Fri May 31 00:31:59 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 31 May 2013 12:31:59 +0800
Subject: [PATCH V1] ARM: mm: lazy cache flushing on non-mapped pages
In-Reply-To: <20130530154047.GW7483@mudshark.cambridge.arm.com>
References: <1369839416-27817-1-git-send-email-ming.lei@canonical.com>
 <20130530154047.GW7483@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVNL032TY7b=YHEg9aaT_WNW3R8JOzaVqSbq09t2kcVOQg@mail.gmail.com>

On Thu, May 30, 2013 at 11:40 PM, Will Deacon <will.deacon at arm.com> wrote:
> Does the page_mapped test make the mapping_mapped test redundant? It sounds
> strange if it's possible to get a non-zero mapcount for a page when its
> address space isn't mapped.

Yes, page_mapped() should always return correct value for a page in page
cache.

I keep the previous check just for safe reason, and I can remove it if
you care.

Thanks
--
Ming Lei


From olof at lixom.net  Fri May 31 00:43:08 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 30 May 2013 21:43:08 -0700
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <20130531001735.GA26684@verge.net.au>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
 <20130531001735.GA26684@verge.net.au>
Message-ID: <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>

Hi,

On Thu, May 30, 2013 at 5:17 PM, Simon Horman <horms at verge.net.au> wrote:
> On Thu, May 30, 2013 at 10:08:56PM +0200, Linus Walleij wrote:
>> On Thu, May 30, 2013 at 12:28 AM, Simon Horman
>> <horms+renesas at verge.net.au> wrote:
>>
>> > From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>> >
>> > The USB_OVCn pins are alternate options for USB over-current detection
>> > when using a 3.3V USB interface. As they're not mandatory they can be
>> > used independently of the USB PENC pins. Don't group the USB_OVCn and
>> > PENC pins to avoid conflicts when the USB_OVCn pins are used by another
>> > function.
>> >
>> > Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>>
>> OK, Acked-by, do you want me to take this as a fix in the pinctrl
>> tree for v3.10?
>>
>> Just asking because Simon usually takes everything else relating to
>> the SH. ...
>
> This was a pull request from my tree to arm-soc, so thats they way
> I was planning to handle things.
>
> Olof, Arnd,
>
> should I re-spin the pull request to include Linus's ack?

You can if you want, but for an odd and specific fix like this we'll
all know he's ok with the code going in.


-Olof


From monstr at monstr.eu  Fri May 31 01:17:59 2013
From: monstr at monstr.eu (Michal Simek)
Date: Fri, 31 May 2013 07:17:59 +0200
Subject: [PATCH v2 0/5] Zynq: revised CCF code
In-Reply-To: <20130530184443.4470.73215@quantum>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
 <51961F37.3030202@monstr.eu> <20130530184443.4470.73215@quantum>
Message-ID: <51A83287.3010604@monstr.eu>

On 05/30/2013 08:44 PM, Mike Turquette wrote:
> Quoting Michal Simek (2013-05-17 05:14:47)
>> Hi Mike,
>>
>> I have sent email to Greg to take this patch from this series
>> though his serial tree because it is unrelated to this clock stuff.
>>
>> Can you please give me your ACK for these patches or add them
>> to your CLK tree?
>>
> 
> For the four clock-related patches:
> 
> Acked-by: Mike Turquette <mturquette at linaro.org>

I have already sent pull request to Arnd and Olof.
Or is it you who should take these patches through your tree?

Thanks.
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From baruch at tkos.co.il  Fri May 31 01:32:47 2013
From: baruch at tkos.co.il (Baruch Siach)
Date: Fri, 31 May 2013 08:32:47 +0300
Subject: [RFC PATCH 2/2] clocksource: dw_apb: allow build for
 architectures other than arm
In-Reply-To: <51A77A25.8080306@linaro.org>
References: <1369570367-994-2-git-send-email-baruch@tkos.co.il>
 <51A51271.2070506@linaro.org>
 <20130530053233.GL25186@sapphire.tkos.co.il>
 <51A77A25.8080306@linaro.org>
Message-ID: <20130531053247.GX5037@tarshish>

Hi John,

On Thu, May 30, 2013 at 09:11:17AM -0700, John Stultz wrote:
> On 05/29/2013 10:32 PM, Baruch Siach wrote:
> >On Tue, May 28, 2013 at 01:24:17PM -0700, John Stultz wrote:
> >>On 05/26/2013 05:12 AM, Baruch Siach wrote:
> >>>  static const struct of_device_id osctimer_ids[] __initconst = {
> >>>@@ -124,3 +135,10 @@ void __init dw_apb_timer_init(void)
> >>>  	init_sched_clock();
> >>>  }
> >>>+
> >>>+#ifndef CONFIG_HAVE_SETUP_SCHED_CLOCK
> >>>+unsigned long long notrace sched_clock()
> >>>+{
> >>>+	return read_sched_clock() * sched_clock_mult;
> >>>+}
> >>>+#endif
> >>Also, can you try to condense the number of #ifndef
> >>CONFIG_HAVE_SETUP_SCHED_CLOCK checks to one, and consolidate the
> >>needed functions all in that one conditional?
> >Thanks for your comments. I'll rework the patch and resubmit.
> >
> >I've just noticed that I have a bigger problem. read_sched_clock() returns
> >u32, not u64. This means that in a rate of, say, 100MHz it will wrap around
> >after a little more than 40 seconds. Would it make sense to put ARM's 32 bin
> >sched_clock extension code (arch/arm/kernel/sched_clock.c) is a common place
> >(maybe drivers/clocksource), and use that? There seems to be nothing ARM
> >specific in this code, after all.
> 
> Yea, working out an actual generic sched_clock implementation is
> something I'd like to see done.
> 
> Though I'd really rather we not toss yet another chunk of
> infrastructure in the drivers/clocksource directory. Instead we
> should probably have a kernel/time/sched_clock.c.
> 
> Then its just the issue of tying that and the clocksource code
> together so you just register existing capable clocksources with a
> SCHED_CLOCK flag or via a different registration hook.
> 
> I don't think it will be an easy job, but if you want to give it a
> shot, I'd be quite interested in reviewing the patches!

Although I'd very much like to contribute in this area, I'm afraid I don't 
have time for this now. My problem is much narrower in scope, though, and I 
think it can be solved without a generic sched_clock implementation at first 
step. All I want is to use a 32 bit counter for sched_clock. The code enabling 
this is currently only available for ARM (arch/arm/kernel/sched_clock.c). 
Should this part of the code move to kernel/time/sched_clock.c?

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From andrew at lunn.ch  Fri May 31 01:33:10 2013
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 31 May 2013 07:33:10 +0200
Subject: Kirkwood CPU Freq driver
In-Reply-To: <51A7DE65.4090108@baker-net.org.uk>
References: <51A12DD4.9010907@baker-net.org.uk>
 <20130526083614.GB26249@lunn.ch>
 <20130526180513.GF31290@titan.lakedaemon.net>
 <51A5234D.9030100@baker-net.org.uk> <20130528215126.GF7678@lunn.ch>
 <51A7DE65.4090108@baker-net.org.uk>
Message-ID: <20130531053310.GJ7678@lunn.ch>

On Fri, May 31, 2013 at 12:19:01AM +0100, Adam Baker wrote:
> On 28/05/13 22:51, Andrew Lunn wrote:
> >>I've now tested with the first of these patches applied and the
> >>>changes from the second added to my .config
> >>>
> >>>To get it to work I had to follow the instructions in the
> >>>Documentation to add the cpus entry to kirkwood.dtsi so I'll post
> >>>that as a patch in a day or two but after doing that I have a
> >>>working cpufreq driver.
> >Great that you got it working. Something must of changed in the
> >generic code, since originally a cpu node was not required.
> >
> >The clocks are not needed in node, so please don't list them.
> >
> Andrew, I just tried testing without the clocks line in the .dtsi
> and I get the messages below in dmesg
> 
> [   18.554990] ERROR: could not get clock /cpus/cpu at 0:cpu_clk(0)
> [   18.560840] kirkwood-cpufreq kirkwood-cpufreq: Unable to get cpuclk
> [   18.567154] kirkwood-cpufreq: probe of kirkwood-cpufreq failed
> with error -2

Duh! I have forgotten how my driver works! Yes, it needs the node,
with clocks. I even documented it!

Strange thing is, i cannot find a patch adding such a node.

I suggest you add the node to the kirkwood.dtsi. I've never seen any
products using the 88F632X, we have no support for it, and very likely
its much more work needed than just moving a few DT nodes around.

Please submit your patch to Jason.

       Thanks
	Andrew


From horms at verge.net.au  Fri May 31 01:45:17 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 May 2013 14:45:17 +0900
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
 <20130531001735.GA26684@verge.net.au>
 <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>
Message-ID: <20130531054517.GC5009@verge.net.au>

On Thu, May 30, 2013 at 09:43:08PM -0700, Olof Johansson wrote:
> Hi,
> 
> On Thu, May 30, 2013 at 5:17 PM, Simon Horman <horms at verge.net.au> wrote:
> > On Thu, May 30, 2013 at 10:08:56PM +0200, Linus Walleij wrote:
> >> On Thu, May 30, 2013 at 12:28 AM, Simon Horman
> >> <horms+renesas at verge.net.au> wrote:
> >>
> >> > From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> >> >
> >> > The USB_OVCn pins are alternate options for USB over-current detection
> >> > when using a 3.3V USB interface. As they're not mandatory they can be
> >> > used independently of the USB PENC pins. Don't group the USB_OVCn and
> >> > PENC pins to avoid conflicts when the USB_OVCn pins are used by another
> >> > function.
> >> >
> >> > Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> >> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >>
> >> OK, Acked-by, do you want me to take this as a fix in the pinctrl
> >> tree for v3.10?
> >>
> >> Just asking because Simon usually takes everything else relating to
> >> the SH. ...
> >
> > This was a pull request from my tree to arm-soc, so thats they way
> > I was planning to handle things.
> >
> > Olof, Arnd,
> >
> > should I re-spin the pull request to include Linus's ack?
> 
> You can if you want, but for an odd and specific fix like this we'll
> all know he's ok with the code going in.

In that case my preference is to leave the pull request as is.
Could you consider merging it?

As an aside, I do expect to send some more v3.10 fixes for shmobile.
There seem to be more than usual.


From olof at lixom.net  Fri May 31 02:11:36 2013
From: olof at lixom.net (Olof Johansson)
Date: Thu, 30 May 2013 23:11:36 -0700
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <20130531054517.GC5009@verge.net.au>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
 <20130531001735.GA26684@verge.net.au>
 <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>
 <20130531054517.GC5009@verge.net.au>
Message-ID: <CAOesGMgrdyFi3GMz52CVnhzmOYHbR5=29Ua0iS8cNbSjg6r-2A@mail.gmail.com>

On Thu, May 30, 2013 at 10:45 PM, Simon Horman <horms at verge.net.au> wrote:
> On Thu, May 30, 2013 at 09:43:08PM -0700, Olof Johansson wrote:
>> Hi,
>>
>> On Thu, May 30, 2013 at 5:17 PM, Simon Horman <horms at verge.net.au> wrote:
>> > On Thu, May 30, 2013 at 10:08:56PM +0200, Linus Walleij wrote:
>> >> On Thu, May 30, 2013 at 12:28 AM, Simon Horman
>> >> <horms+renesas at verge.net.au> wrote:
>> >>
>> >> > From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>> >> >
>> >> > The USB_OVCn pins are alternate options for USB over-current detection
>> >> > when using a 3.3V USB interface. As they're not mandatory they can be
>> >> > used independently of the USB PENC pins. Don't group the USB_OVCn and
>> >> > PENC pins to avoid conflicts when the USB_OVCn pins are used by another
>> >> > function.
>> >> >
>> >> > Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
>> >> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
>> >> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>> >>
>> >> OK, Acked-by, do you want me to take this as a fix in the pinctrl
>> >> tree for v3.10?
>> >>
>> >> Just asking because Simon usually takes everything else relating to
>> >> the SH. ...
>> >
>> > This was a pull request from my tree to arm-soc, so thats they way
>> > I was planning to handle things.
>> >
>> > Olof, Arnd,
>> >
>> > should I re-spin the pull request to include Linus's ack?
>>
>> You can if you want, but for an odd and specific fix like this we'll
>> all know he's ok with the code going in.
>
> In that case my preference is to leave the pull request as is.
> Could you consider merging it?

Yes, I will do a pass tomorrow and handle the outstanding merges.

> As an aside, I do expect to send some more v3.10 fixes for shmobile.
> There seem to be more than usual.

A little unfortunate but it's hard to do much about.

Please be conservative with what you pick up for 3.10 vs 3.11 -- Linus
has said he really wants to see things slow down.

And please make our case as easy as possible by making sure it's
pretty clear from the patch descriptions what kind of bugs they fix
(and if they are regressions).



-Olof


From sebastian.hesselbarth at gmail.com  Fri May 31 02:28:58 2013
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 31 May 2013 08:28:58 +0200
Subject: [PATCH v5 00/13] net: mv643xx_eth DT support and fixes
In-Reply-To: <20130530.175549.407800685811475192.davem@davemloft.net>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130530.175549.407800685811475192.davem@davemloft.net>
Message-ID: <51A8432A.4000602@gmail.com>

On 05/31/2013 02:55 AM, David Miller wrote:
> From: Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> Date: Wed, 29 May 2013 21:32:42 +0200
>
>> For the patches above I suggest to take Patches 1-6 through David
>> Miller's branch, and Patches 7-12 through Jason Cooper's when the
>> former have appeared on mainline linux. The patch set has been based
>> on v3.10-rc3.
>
> Patches 1-6 applied to net-next, and patch #1 queued up for -stable.

David,

thanks for pulling these in. I finally found how to check if a patch
already went into -stable. As Jason already said, the mdio patch that
#1 fixes did not yet went into -stable. Can you unqueue it? Sorry for
the confusion.

Sebastian



From gururaja.hebbar at ti.com  Fri May 31 02:33:23 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 12:03:23 +0530
Subject: [PATCH 0/2] rtc: rtc-omap: add support for DT wakeup & alarm events
Message-ID: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>

Current rtc-omap driver expects the rtc module wake-up capabilities to
be set up by board specific code. However, in case of DT, this is not
possible.

So, add a DT property "ti,wakeup_capable" to indicate that the module
is wake-up capable.

Also, on some platforms (like AM33xx), a special register
(RTC_IRQWAKEEN) is available to enable Wakeup feature for Alarm Events.

Since new platforms/Boards are now added through DT only, this feature
is supported via DT property only. Platforms using such IP should add
the property "ti,has_irq_wake_enb" in rtc DT node.

Kernel Base for the series is
	> git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/
linux-omap-dt.git
	> linux-omap-git/for_3.11/dts

Hebbar Gururaja (2):
  rtc: omap: add option to indicate wakeup support through DT
  rtc: omap: add rtc wakeup support to alarm events

 Documentation/devicetree/bindings/rtc/rtc-omap.txt |    6 +++
 drivers/rtc/rtc-omap.c                             |   50 +++++++++++++++++---
 2 files changed, 49 insertions(+), 7 deletions(-)

-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 02:33:24 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 12:03:24 +0530
Subject: [PATCH 1/2] rtc: omap: add option to indicate wakeup support through
 DT
In-Reply-To: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369982005-8572-2-git-send-email-gururaja.hebbar@ti.com>

Even though RTC-IP is wakeup capable, Not all Boards support it.

For example
The rtc alarm wakeup is available in rtc-ip since omap1 days but alarm
was not wired properly in previous ompa1 boards.

	commit fa5b07820fe3a0fc06ac368516e71f10a59b9539
	Author: Sekhar Nori <nsekhar at ti.com>
	Date:   Wed Oct 27 15:33:05 2010 -0700

	rtc: omap: let device wakeup capability be configured from chip
	init logic

	The rtc-omap driver currently hardcodes the RTC wakeup
	capability to be "not capable".  While this seems to be true for
	existing OMAP1 boards which are not wired for this, the
	DA850/OMAP-L138 SoC, the RTC can always be wake up source from
	its "deep sleep" mode.

Current rtc-omap driver expects the rtc module wake-up capabilities to
be set up by board specific code. However, in case of DT, this is not
possible.

So, add a DT property "ti,wakeup_capable" to indicate that the module is
wake-up capable.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
---
:100644 100644 b47aa41... 108a629... M	Documentation/devicetree/bindings/rtc/rtc-omap.txt
:100644 100644 b0ba3fc... 000a02f... M	drivers/rtc/rtc-omap.c
 Documentation/devicetree/bindings/rtc/rtc-omap.txt |    4 ++++
 drivers/rtc/rtc-omap.c                             |    5 +++++
 2 files changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
index b47aa41..108a629 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts: rtc timer, alarm interrupts in order
 - interrupt-parent: phandle for the interrupt controller
 
+Optional properties:
+- ti,wakeup_capable: Inform the rtc driver that this module is wake-up
+  capable so that rtcwake and suspend tests can work.
+
 Example:
 
 rtc at 1c23000 {
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index b0ba3fc..000a02f 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -423,6 +423,11 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
 	 *    is write-only, and always reads as zero...)
 	 */
 
+	/* Fixup wakeup-enable feature based on the device tree */
+	if (of_id && of_find_property(pdev->dev.of_node,
+				      "ti,wakeup_capable", NULL))
+		device_init_wakeup(&pdev->dev, 1);
+
 	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
 		pr_info("%s: split power mode\n", pdev->name);
 
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 02:33:25 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 12:03:25 +0530
Subject: [PATCH 2/2] rtc: omap: add rtc wakeup support to alarm events
In-Reply-To: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369982005-8572-3-git-send-email-gururaja.hebbar@ti.com>

On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
is available to enable Wakeup feature for Alarm Events.

Since new platforms/Boards are now added through DT only, this feature
is supported via DT property only.

Platforms using such IP should add the property "ti,has_irq_wake_enb"
in rtc DT node.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
---
:100644 100644 108a629... b870d87... M	Documentation/devicetree/bindings/rtc/rtc-omap.txt
:100644 100644 000a02f... 5e9c0dd... M	drivers/rtc/rtc-omap.c
 Documentation/devicetree/bindings/rtc/rtc-omap.txt |    2 +
 drivers/rtc/rtc-omap.c                             |   47 ++++++++++++++++----
 2 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
index 108a629..b870d87 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
@@ -9,6 +9,8 @@ Required properties:
 Optional properties:
 - ti,wakeup_capable: Inform the rtc driver that this module is wake-up
   capable so that rtcwake and suspend tests can work.
+- ti,has_irq_wake_enb: Inform rtc driver that this module has a a
+  special register to enable Wakeup feature for Alarm events.
 
 Example:
 
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 000a02f..5e9c0dd 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -72,6 +72,8 @@
 #define OMAP_RTC_KICK0_REG		0x6c
 #define OMAP_RTC_KICK1_REG		0x70
 
+#define OMAP_RTC_IRQWAKEEN		0x7C
+
 /* OMAP_RTC_CTRL_REG bit fields: */
 #define OMAP_RTC_CTRL_SPLIT		(1<<7)
 #define OMAP_RTC_CTRL_DISABLE		(1<<6)
@@ -96,6 +98,9 @@
 #define OMAP_RTC_INTERRUPTS_IT_ALARM    (1<<3)
 #define OMAP_RTC_INTERRUPTS_IT_TIMER    (1<<2)
 
+/* OMAP_RTC_IRQWAKEEN bit fields: */
+#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN    (1<<1)
+
 /* OMAP_RTC_KICKER values */
 #define	KICK0_VALUE			0x83e70b13
 #define	KICK1_VALUE			0x95a4f1e0
@@ -103,6 +108,7 @@
 #define	OMAP_RTC_HAS_KICKER		0x1
 
 static void __iomem	*rtc_base;
+static unsigned int	has_irq_wake_enb_bit;
 
 #define rtc_read(addr)		readb(rtc_base + (addr))
 #define rtc_write(val, addr)	writeb(val, rtc_base + (addr))
@@ -425,9 +431,14 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
 
 	/* Fixup wakeup-enable feature based on the device tree */
 	if (of_id && of_find_property(pdev->dev.of_node,
-				      "ti,wakeup_capable", NULL))
+				      "ti,wakeup_capable", NULL)) {
 		device_init_wakeup(&pdev->dev, 1);
 
+		if (of_find_property(pdev->dev.of_node,
+				     "ti,has_irq_wake_enb", NULL))
+			has_irq_wake_enb_bit = true;
+	}
+
 	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
 		pr_info("%s: split power mode\n", pdev->name);
 
@@ -469,16 +480,26 @@ static u8 irqstat;
 
 static int omap_rtc_suspend(struct device *dev)
 {
+	u8 irqwake_stat;
+
 	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
 
-	/* FIXME the RTC alarm is not currently acting as a wakeup event
-	 * source, and in fact this enable() call is just saving a flag
-	 * that's never used...
+	/*
+	 * FIXME. On some platforms the RTC alarm is not currently acting as a
+	 * wakeup event source, and in fact this enable() call is just saving a
+	 * flag that's never used...
 	 */
-	if (device_may_wakeup(dev))
+	if (device_may_wakeup(dev)) {
 		enable_irq_wake(omap_rtc_alarm);
-	else
+
+		if (has_irq_wake_enb_bit == true) {
+			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
+			irqwake_stat |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
+			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
+		}
+	} else {
 		rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
+	}
 
 	/* Disable the clock/module */
 	pm_runtime_put_sync(dev);
@@ -488,13 +509,23 @@ static int omap_rtc_suspend(struct device *dev)
 
 static int omap_rtc_resume(struct device *dev)
 {
+	u8 irqwake_stat;
+
 	/* Enable the clock/module so that we can access the registers */
 	pm_runtime_get_sync(dev);
 
-	if (device_may_wakeup(dev))
+	if (device_may_wakeup(dev)) {
 		disable_irq_wake(omap_rtc_alarm);
-	else
+
+		if (has_irq_wake_enb_bit == true) {
+			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
+			irqwake_stat &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
+			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
+		}
+	} else {
 		rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
+	}
+
 	return 0;
 }
 #endif
-- 
1.7.9.5



From mturquette at linaro.org  Fri May 31 02:32:25 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 30 May 2013 23:32:25 -0700
Subject: [PATCH v2 0/5] Zynq: revised CCF code
In-Reply-To: <51A83287.3010604@monstr.eu>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
 <51961F37.3030202@monstr.eu> <20130530184443.4470.73215@quantum>
 <51A83287.3010604@monstr.eu>
Message-ID: <20130531063225.21525.49143@quantum>

Quoting Michal Simek (2013-05-30 22:17:59)
> On 05/30/2013 08:44 PM, Mike Turquette wrote:
> > Quoting Michal Simek (2013-05-17 05:14:47)
> >> Hi Mike,
> >>
> >> I have sent email to Greg to take this patch from this series
> >> though his serial tree because it is unrelated to this clock stuff.
> >>
> >> Can you please give me your ACK for these patches or add them
> >> to your CLK tree?
> >>
> > 
> > For the four clock-related patches:
> > 
> > Acked-by: Mike Turquette <mturquette at linaro.org>
> 
> I have already sent pull request to Arnd and Olof.
> Or is it you who should take these patches through your tree?
> 

Either way is fine.  Since you have already sent the pull request to the
arm-soc tree then that is probably the best path.

Regards,
Mike

> Thanks.
> Michal
> 
> 
> -- 
> Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
> w: www.monstr.eu p: +42-0-721842854
> Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
> Maintainer of Linux kernel - Xilinx Zynq ARM architecture
> Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


From prabhakar.csengg at gmail.com  Fri May 31 02:44:44 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 31 May 2013 12:14:44 +0530
Subject: [PATCH 1/2] rtc: omap: add option to indicate wakeup support
 through DT
In-Reply-To: <1369982005-8572-2-git-send-email-gururaja.hebbar@ti.com>
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
 <1369982005-8572-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <CA+V-a8vAM_4qC20Fpipu3tROs65dERoFgV-ypyJh336rir-0EQ@mail.gmail.com>

Hi Gururaja,

Thanks for the patch.

On Fri, May 31, 2013 at 12:03 PM, Hebbar Gururaja
<gururaja.hebbar at ti.com> wrote:
> Even though RTC-IP is wakeup capable, Not all Boards support it.
>
> For example
> The rtc alarm wakeup is available in rtc-ip since omap1 days but alarm
> was not wired properly in previous ompa1 boards.
>
[snip]
>
> +Optional properties:
> +- ti,wakeup_capable: Inform the rtc driver that this module is wake-up
For devicetree properties '-' is preferred over '_'.

Regards,
--Prabhakar Lad


From gururaja.hebbar at ti.com  Fri May 31 02:46:42 2013
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 31 May 2013 06:46:42 +0000
Subject: [PATCH 1/2] rtc: omap: add option to indicate wakeup support
 through DT
In-Reply-To: <CA+V-a8vAM_4qC20Fpipu3tROs65dERoFgV-ypyJh336rir-0EQ@mail.gmail.com>
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
 <1369982005-8572-2-git-send-email-gururaja.hebbar@ti.com>
 <CA+V-a8vAM_4qC20Fpipu3tROs65dERoFgV-ypyJh336rir-0EQ@mail.gmail.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EC1E168@DBDE04.ent.ti.com>

On Fri, May 31, 2013 at 12:14:44, Prabhakar Lad wrote:
> Hi Gururaja,
> 
> Thanks for the patch.
> 
> On Fri, May 31, 2013 at 12:03 PM, Hebbar Gururaja
> <gururaja.hebbar at ti.com> wrote:
> > Even though RTC-IP is wakeup capable, Not all Boards support it.
> >
> > For example
> > The rtc alarm wakeup is available in rtc-ip since omap1 days but alarm
> > was not wired properly in previous ompa1 boards.
> >
> [snip]
> >
> > +Optional properties:
> > +- ti,wakeup_capable: Inform the rtc driver that this module is wake-up
> For devicetree properties '-' is preferred over '_'.

Thanks for the review. I will make the correction. But will wait for some 
more time (so others can review) and then send V2

> 
> Regards,
> --Prabhakar Lad
> 


Regards, 
Gururaja


From B35083 at freescale.com  Fri May 31 02:48:27 2013
From: B35083 at freescale.com (Lu Jingchang-B35083)
Date: Fri, 31 May 2013 06:48:27 +0000
Subject: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts support
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
 <1369732343-2982-5-git-send-email-b35083@freescale.com>
 <20130529111605.GA25053@S2101-09.ap.freescale.net> 
Message-ID: <B56CDBE15CE27145A4B77D2D24263E851CE3E6@039-SN1MPN1-003.039d.mgd.msft.net>

>>-----Original Message-----
>>From: Shawn Guo [mailto:shawn.guo at linaro.org]
>>Sent: Wednesday, May 29, 2013 7:16 PM
>>To: Lu Jingchang-B35083
>>Cc: linux-arm-kernel at lists.infradead.org; s.hauer at pengutronix.de
>>Subject: Re: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts
>>support
>>
>>On Tue, May 28, 2013 at 05:12:23PM +0800, Jingchang Lu wrote:
>>> +&fec0 {
>>> +	phy-mode = "rmii";
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&pinctrl_fec0_1>;
>>> +	status = "okay";
>>> +};
>>
>>I'm wondering if fec works fine on your side.  The kernel seems to halt
>>on the repeated phy messages below here when I boot the kernel with NFS.
>>
>>Shawn
>>
>>fec 400d0000.ethernet eth0: Freescale FEC PHY driver [Generic PHY]
>>(mii_bus:phy_addr=400d0000.etherne:00, irq=-1)
>>IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready fec
>>400d1000.ethernet
>>eth1: Freescale FEC PHY driver [Generic PHY]
>>(mii_bus:phy_addr=400d0000.etherne:01, irq=-1)
>>IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>>IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>>libphy: 400d0000.etherne:01 - Link is Up - 100/Full
>>IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready Sending DHCP
>>requests ., OK
>>IP-Config: Got DHCP answer from 192.168.1.1, my address is
>>192.168.1.102
>>IP-Config: Complete:
>>     device=eth0, hwaddr=00:04:9f:02:19:38, ipaddr=192.168.1.102,
>>mask=255.255.255.0, gw=192.168.1.1
>>     host=192.168.1.102, domain=domain, nis-domain=(none)
>>     bootserver=0.0.0.0, rootserver=192.168.1.100, rootpath=, mtu=576
>>     nameserver0=61.177.7.1, nameserver1=221.228.255.1 ALSA device list:
>>  No soundcards found.
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Half
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Half
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Half
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Full
>>libphy: 400d0000.etherne:00 - Link is Up - 100/Half ...
[Lu Jingchang-B35083] 
  I have test on linux-next-20130530 and linux-next-20130531 kernel tree, all things work well on my side, NFS rootfs is mounted successfully. The VF610 supporting patches seem has no problem. Does it work now on your side? Thanks!

===========================================================
Booting Linux on physical CPU 0x0
Linux version 3.10.0-rc3-next-20130531+
[ ... ]

fec 400d0000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=400d0000.etherne:00, irq=-1)
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
IP-Config: Complete:
     device=eth0, hwaddr=00:e0:0c:bc:e5:64, ipaddr=10.193.20.229, mask=255.255.255.0, gw=10.193.20.254
     host=10.193.20.229, domain=, nis-domain=(none)
     bootserver=10.193.20.106, rootserver=10.193.20.106, rootpath=
VFS: Mounted root (nfs filesystem) on device 0:11.
devtmpfs: mounted
Freeing unused kernel memory: 184K (805bf000 - 805ed000)
starting pid 95, tty '': '/etc/rc.d/rcS'
Mounting /proc and /sys
Starting the hotplug events dispatcher udevd
Synthesizing initial hotplug evudevd (104): /proc/104/oom_adj is deprecated, please use /proc/104/oom_score_adj instead.
ents
Setting the hostname to freescale
Loading module telnetd
modprobe: chdir(3.10.0-rc3-next-20130531+): No such file or directory
Mounting filesystems
mount: mounting usbfs on /proc/bus/usb failed: No such file or directory
starting pid 421, tty '': '-/sbin/getty -L ttyLP1 115200 vt100'

arm-none-linux-gnueabi-gcc (Freescale MAD -- Linaro 2011.07 -- Built at 2011/08/10 09:20) 4.6.2 20110630 (prerelease)
root filesystem built on Thu, 09 Aug 2012 16:38:52 +0800
Freescale Semiconductor, Inc.

freescale login: root
login[421]: root login on 'ttyLP1'


BusyBox v1.18.5 () built-in shell (ash)
Enter 'help' for a list of built-in commands.

root at freescale ~$



From prabhakar.csengg at gmail.com  Fri May 31 02:50:39 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 31 May 2013 12:20:39 +0530
Subject: [PATCH 2/2] rtc: omap: add rtc wakeup support to alarm events
In-Reply-To: <1369982005-8572-3-git-send-email-gururaja.hebbar@ti.com>
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
 <1369982005-8572-3-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <CA+V-a8tpPV35Z22YCNKOvCP36+v1sF8+9Fiy_Wrk4T-iCVv4nw@mail.gmail.com>

Hi Gururaja,

Thanks for the patch.

On Fri, May 31, 2013 at 12:03 PM, Hebbar Gururaja
<gururaja.hebbar at ti.com> wrote:
> On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
[snip]
>  - ti,wakeup_capable: Inform the rtc driver that this module is wake-up
>    capable so that rtcwake and suspend tests can work.
> +- ti,has_irq_wake_enb: Inform rtc driver that this module has a a
same comment applies here as well.
s/has a a/ has a

> +  special register to enable Wakeup feature for Alarm events.
>
>  Example:
>
> diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
> index 000a02f..5e9c0dd 100644
> --- a/drivers/rtc/rtc-omap.c
> +++ b/drivers/rtc/rtc-omap.c
> @@ -72,6 +72,8 @@
>  #define OMAP_RTC_KICK0_REG             0x6c
>  #define OMAP_RTC_KICK1_REG             0x70
>
> +#define OMAP_RTC_IRQWAKEEN             0x7C
> +
why not have the hex values in smaller case as done in the rest of the file ?

Regards,
--Prabhakar Lad


From lee.jones at linaro.org  Fri May 31 02:55:32 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 07:55:32 +0100
Subject: [PATCH 0/4] clk, mfd: u8540 clock tree definition
In-Reply-To: <20130531012509.21525.90187@quantum>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
 <20130531012509.21525.90187@quantum>
Message-ID: <20130531065532.GA10355@gmail.com>

On Thu, 30 May 2013, Mike Turquette wrote:

> Quoting Philippe Begnic (2013-05-27 05:41:28)
> > From: Philippe Begnic <philippe.begnic at st.com>
> > 
> > Create U8540 clock tree definitions for common clock framework
> > 
> 
> The clock changes look good to me.  How did you want to merge the
> patches?

You may as well take them through your tree Mike.

> > Philippe Begnic (4):
> >   clk: ux500: Pass clock base adresses in initcall for u8540 and u9540
> >   mfd: db8500: Update register definition for u8540 clock
> >   mfd: db8500: Update BML clock register for db8580
> >   clk: ux500: Clocks definition for u8540
> > 
> >  arch/arm/mach-ux500/cpu.c                 |    6 +-
> >  drivers/clk/ux500/u8540_clk.c             |  564 ++++++++++++++++++++++++++++-
> >  drivers/clk/ux500/u9540_clk.c             |    4 +-
> >  drivers/mfd/db8500-prcmu.c                |    1 +
> >  drivers/mfd/dbx500-prcmu-regs.h           |    1 +
> >  include/linux/mfd/abx500/ab8500-sysctrl.h |    4 +-
> >  include/linux/mfd/dbx500-prcmu.h          |   12 +
> >  include/linux/platform_data/clk-ux500.h   |    6 +-
> >  8 files changed, 587 insertions(+), 11 deletions(-)
> > 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Fri May 31 03:01:44 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 09:01:44 +0200
Subject: [RFC/PATCH v2 2/2] gpio-rcar: Add DT support
In-Reply-To: <4678059.RuWR6CiQ8n@avalon>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <1369136406-23800-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <CACRpkdb8GYpx3ASzXB7HX5oEpAUBe-yBo0N5Ep9S+DqoE6oCLw@mail.gmail.com>
 <4678059.RuWR6CiQ8n@avalon>
Message-ID: <CACRpkda4rRWcVkdGPcSvJeQq_KaJE5uxD+0P62Ot8=Xuf2-B+A@mail.gmail.com>

On Fri, May 31, 2013 at 3:20 AM, Laurent Pinchart
<laurent.pinchart at ideasonboard.com> wrote:

> I've so far pushed GPIO and pinctrl patches for SH through Simon's tree due to
> the many cross-dependencies between SH arch code and the GPIO and pinctrl
> drivers. As the situation now stabilizes, we could now push the patches
> through their respective subsystem trees.
>
> Simon, Linus, any opinion/preference on that ?

Depends, if they are still large patch sets I'd prefer Simon to
take it, but once the drivers are in place and going to maintenance
mode I'll handle them in pinctrl.

>> The above ranges are part of that document.
>
> What about replacing that with
>
>   - gpio-ranges: Range of pins managed by the GPIO controller.
>
> Please refer to gpio.txt in this directory for details of gpio-ranges property
> and the common GPIO bindings used by client devices.

Go for it!

Yours,
Linus Walleij


From monstr at monstr.eu  Fri May 31 03:03:33 2013
From: monstr at monstr.eu (Michal Simek)
Date: Fri, 31 May 2013 09:03:33 +0200
Subject: [PATCH v2 0/5] Zynq: revised CCF code
In-Reply-To: <20130531063225.21525.49143@quantum>
References: <1368467199-8702-1-git-send-email-soren.brinkmann@xilinx.com>
 <51961F37.3030202@monstr.eu> <20130530184443.4470.73215@quantum>
 <51A83287.3010604@monstr.eu> <20130531063225.21525.49143@quantum>
Message-ID: <51A84B45.3070804@monstr.eu>

On 05/31/2013 08:32 AM, Mike Turquette wrote:
> Quoting Michal Simek (2013-05-30 22:17:59)
>> On 05/30/2013 08:44 PM, Mike Turquette wrote:
>>> Quoting Michal Simek (2013-05-17 05:14:47)
>>>> Hi Mike,
>>>>
>>>> I have sent email to Greg to take this patch from this series
>>>> though his serial tree because it is unrelated to this clock stuff.
>>>>
>>>> Can you please give me your ACK for these patches or add them
>>>> to your CLK tree?
>>>>
>>>
>>> For the four clock-related patches:
>>>
>>> Acked-by: Mike Turquette <mturquette at linaro.org>
>>
>> I have already sent pull request to Arnd and Olof.
>> Or is it you who should take these patches through your tree?
>>
> 
> Either way is fine.  Since you have already sent the pull request to the
> arm-soc tree then that is probably the best path.

ok. I will keep my eyes on it.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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From rogerq at ti.com  Fri May 31 03:17:14 2013
From: rogerq at ti.com (Roger Quadros)
Date: Fri, 31 May 2013 10:17:14 +0300
Subject: [PATCH] ARM: OMAP2+: omap-usb-host: Fix memory leaks
In-Reply-To: <20130530210025.GE6467@atomide.com>
References: <1369400818-31625-1-git-send-email-rogerq@ti.com>
 <20130530210025.GE6467@atomide.com>
Message-ID: <51A84E7A.106@ti.com>

Hi Tony,

On 05/31/2013 12:00 AM, Tony Lindgren wrote:
> Hi Roger,
> 
> * Roger Quadros <rogerq at ti.com> [130524 06:12]:
>> Fix memory leaks in the error path.
>> Also, use platform_device_register_full() to allocate
>> the platform devices and set platform data.
> 
> If you need this for the v3.10-rc, you should describe why this patch
> is needed and ideally have some oops or regression causing commit
> listed. Care to update the description for that?

There is no oops or regression happening. Just that there will be a
small memory leak if any of the memory allocations fail or if the
platform device is destroyed.

If it doesn't look that serious to you then it can wait.
But if we move to device tree only boot then this patch and the file
"usb-host.c" might not be required at all.

cheers,
-roger

>  
>> Signed-off-by: Roger Quadros <rogerq at ti.com>
>> ---
>>  arch/arm/mach-omap2/usb-host.c |  106 +++++++++++++++++++++-------------------
>>  1 files changed, 56 insertions(+), 50 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
>> index aa27d7f..609b330 100644
>> --- a/arch/arm/mach-omap2/usb-host.c
>> +++ b/arch/arm/mach-omap2/usb-host.c
>> @@ -28,6 +28,7 @@
>>  #include <linux/io.h>
>>  #include <linux/gpio.h>
>>  #include <linux/usb/phy.h>
>> +#include <linux/usb/nop-usb-xceiv.h>
>>  
>>  #include "soc.h"
>>  #include "omap_device.h"
>> @@ -560,7 +561,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>>  	struct regulator_init_data *reg_data;
>>  	struct fixed_voltage_config *config;
>>  	struct platform_device *pdev;
>> -	int ret;
>> +	struct platform_device_info pdevinfo;
>> +	int ret = -ENOMEM;
>>  
>>  	supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
>>  	if (!supplies)
>> @@ -571,7 +573,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>>  
>>  	reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
>>  	if (!reg_data)
>> -		return -ENOMEM;
>> +		goto err_data;
>>  
>>  	reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
>>  	reg_data->consumer_supplies = supplies;
>> @@ -580,39 +582,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
>>  	config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
>>  			GFP_KERNEL);
>>  	if (!config)
>> -		return -ENOMEM;
>> +		goto err_config;
>> +
>> +	config->supply_name = kstrdup(name, GFP_KERNEL);
>> +	if (!config->supply_name)
>> +		goto err_supplyname;
>>  
>> -	config->supply_name = name;
>>  	config->gpio = gpio;
>>  	config->enable_high = polarity;
>>  	config->init_data = reg_data;
>>  
>>  	/* create a regulator device */
>> -	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
>> -	if (!pdev)
>> -		return -ENOMEM;
>> +	memset(&pdevinfo, 0, sizeof(pdevinfo));
>> +	pdevinfo.name = reg_name;
>> +	pdevinfo.id = PLATFORM_DEVID_AUTO;
>> +	pdevinfo.data = config;
>> +	pdevinfo.size_data = sizeof(*config);
>>  
>> -	pdev->id = PLATFORM_DEVID_AUTO;
>> -	pdev->name = reg_name;
>> -	pdev->dev.platform_data = config;
>> +	pdev = platform_device_register_full(&pdevinfo);
>> +	if (IS_ERR(pdev)) {
>> +		ret = PTR_ERR(pdev);
>> +		pr_err("%s: Failed registering regulator %s for %s : %d\n",
>> +				__func__, name, dev_id, ret);
>> +		goto err_register;
>> +	}
>>  
>> -	ret = platform_device_register(pdev);
>> -	if (ret)
>> -		pr_err("%s: Failed registering regulator %s for %s\n",
>> -				__func__, name, dev_id);
>> +	return 0;
>>  
>> +err_register:
>> +	kfree(config->supply_name);
>> +err_supplyname:
>> +	kfree(config);
>> +err_config:
>> +	kfree(reg_data);
>> +err_data:
>> +	kfree(supplies);
>>  	return ret;
>>  }
>>  
>> +#define MAX_STR 20
>> +
>>  int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
>>  {
>> -	char *rail_name;
>> -	int i, len;
>> +	char rail_name[MAX_STR];
>> +	int i;
>>  	struct platform_device *pdev;
>>  	char *phy_id;
>> -
>> -	/* the phy_id will be something like "nop_usb_xceiv.1" */
>> -	len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
>> +	struct platform_device_info pdevinfo;
>>  
>>  	for (i = 0; i < num_phys; i++) {
>>  
>> @@ -627,25 +643,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
>>  			!gpio_is_valid(phy->vcc_gpio))
>>  			continue;
>>  
>> -		/* create a NOP PHY device */
>> -		pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
>> -		if (!pdev)
>> -			return -ENOMEM;
>> -
>> -		pdev->id = phy->port;
>> -		pdev->name = nop_name;
>> -		pdev->dev.platform_data = phy->platform_data;
>> -
>> -		phy_id = kmalloc(len, GFP_KERNEL);
>> -		if (!phy_id)
>> +		phy_id = kmalloc(MAX_STR, GFP_KERNEL);
>> +		if (!phy_id) {
>> +			pr_err("%s: kmalloc() failed\n", __func__);
>>  			return -ENOMEM;
>> +		}
>>  
>> -		scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
>> -					pdev->id);
>> -
>> -		if (platform_device_register(pdev)) {
>> -			pr_err("%s: Failed to register device %s\n",
>> -				__func__,  phy_id);
>> +		/* create a NOP PHY device */
>> +		memset(&pdevinfo, 0, sizeof(pdevinfo));
>> +		pdevinfo.name = nop_name;
>> +		pdevinfo.id = phy->port;
>> +		pdevinfo.data = phy->platform_data;
>> +		pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data);
>> +
>> +		scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d",
>> +					phy->port);
>> +		pdev = platform_device_register_full(&pdevinfo);
>> +		if (IS_ERR(pdev)) {
>> +			pr_err("%s: Failed to register device %s : %ld\n",
>> +				__func__,  phy_id, PTR_ERR(pdev));
>> +			kfree(phy_id);
>>  			continue;
>>  		}
>>  
>> @@ -653,26 +670,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
>>  
>>  		/* Do we need RESET regulator ? */
>>  		if (gpio_is_valid(phy->reset_gpio)) {
>> -
>> -			rail_name = kmalloc(13, GFP_KERNEL);
>> -			if (!rail_name)
>> -				return -ENOMEM;
>> -
>> -			scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
>> -
>> +			scnprintf(rail_name, MAX_STR,
>> +					"hsusb%d_reset", phy->port);
>>  			usbhs_add_regulator(rail_name, phy_id, "reset",
>>  						phy->reset_gpio, 1);
>>  		}
>>  
>>  		/* Do we need VCC regulator ? */
>>  		if (gpio_is_valid(phy->vcc_gpio)) {
>> -
>> -			rail_name = kmalloc(13, GFP_KERNEL);
>> -			if (!rail_name)
>> -				return -ENOMEM;
>> -
>> -			scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
>> -
>> +			scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
>>  			usbhs_add_regulator(rail_name, phy_id, "vcc",
>>  					phy->vcc_gpio, phy->vcc_polarity);
>>  		}
>> -- 
>> 1.7.4.1
>>



From linus.walleij at linaro.org  Fri May 31 03:21:46 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 09:21:46 +0200
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <CAOesGMgrdyFi3GMz52CVnhzmOYHbR5=29Ua0iS8cNbSjg6r-2A@mail.gmail.com>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
 <20130531001735.GA26684@verge.net.au>
 <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>
 <20130531054517.GC5009@verge.net.au>
 <CAOesGMgrdyFi3GMz52CVnhzmOYHbR5=29Ua0iS8cNbSjg6r-2A@mail.gmail.com>
Message-ID: <CACRpkda9tjydo038exS2a=Gsvum41LyvXd=GwKh3b0Zi4rOA9g@mail.gmail.com>

On Fri, May 31, 2013 at 8:11 AM, Olof Johansson <olof at lixom.net> wrote:
> [Simon]
>> As an aside, I do expect to send some more v3.10 fixes for shmobile.
>> There seem to be more than usual.
>
> A little unfortunate but it's hard to do much about.
>
> Please be conservative with what you pick up for 3.10 vs 3.11 -- Linus
> has said he really wants to see things slow down.

What we might need to think about is the evolutional pace of the ARM
kernel - compared to a few years back we have increased the change
rate by orders of a magnitude (at least that is my feeling...)

There may be some point where we actually need to tell people to
hold changes back because they are just pushing too large volumes
through one merge window, resulting in a corresponding amount of
fixes.

This merge window both Samsung Exynos and SH mobile seem to
have been a little bit trigger-happy :-/

Yours,
Linus Walleij


From laurent.pinchart at ideasonboard.com  Fri May 31 03:32:32 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Fri, 31 May 2013 09:32:32 +0200
Subject: [RFC/PATCH v2 2/2] gpio-rcar: Add DT support
In-Reply-To: <CACRpkda4rRWcVkdGPcSvJeQq_KaJE5uxD+0P62Ot8=Xuf2-B+A@mail.gmail.com>
References: <1369136406-23800-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
 <4678059.RuWR6CiQ8n@avalon>
 <CACRpkda4rRWcVkdGPcSvJeQq_KaJE5uxD+0P62Ot8=Xuf2-B+A@mail.gmail.com>
Message-ID: <4646425.XBU4xZJKKv@avalon>

Hi Linus,

On Friday 31 May 2013 09:01:44 Linus Walleij wrote:
> On Fri, May 31, 2013 at 3:20 AM, Laurent Pinchart wrote:
> > I've so far pushed GPIO and pinctrl patches for SH through Simon's tree
> > due to the many cross-dependencies between SH arch code and the GPIO and
> > pinctrl drivers. As the situation now stabilizes, we could now push the
> > patches through their respective subsystem trees.
> > 
> > Simon, Linus, any opinion/preference on that ?
> 
> Depends, if they are still large patch sets I'd prefer Simon to
> take it, but once the drivers are in place and going to maintenance
> mode I'll handle them in pinctrl.

Let's make the switch for v3.12 then if that's fine with you.

> >> The above ranges are part of that document.
> > 
> > What about replacing that with
> > 
> >   - gpio-ranges: Range of pins managed by the GPIO controller.
> > 
> > Please refer to gpio.txt in this directory for details of gpio-ranges
> > property and the common GPIO bindings used by client devices.
> 
> Go for it!

Thanks.

-- 
Regards,

Laurent Pinchart



From shawn.guo at linaro.org  Fri May 31 03:38:08 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 May 2013 15:38:08 +0800
Subject: [PATCH v4 4/4] ARM: dts: add initial VF610 Tower board dts support
In-Reply-To: <B56CDBE15CE27145A4B77D2D24263E851CE3E6@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
 <1369732343-2982-5-git-send-email-b35083@freescale.com>
 <20130529111605.GA25053@S2101-09.ap.freescale.net>
 <B56CDBE15CE27145A4B77D2D24263E851CE3E6@039-SN1MPN1-003.039d.mgd.msft.net>
Message-ID: <20130531073806.GA6520@S2101-09.ap.freescale.net>

On Fri, May 31, 2013 at 06:48:27AM +0000, Lu Jingchang-B35083 wrote:
> [Lu Jingchang-B35083] 
>   I have test on linux-next-20130530 and linux-next-20130531 kernel tree, all things work well on my side, NFS rootfs is mounted successfully. The VF610 supporting patches seem has no problem. Does it work now on your side? Thanks!
> 

Yeah, I can boot into console using next-20130531 now.  Will applied the
patches.  Thanks.

Shawn



From tomi.valkeinen at ti.com  Fri May 31 03:37:51 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 May 2013 10:37:51 +0300
Subject: [PATCH 0/3] ARM: OMAP: add corrected DSS regulator supplies
Message-ID: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>

Hi Tony,

Here are a few patches adding corrected DSS regulator supplies. The current
ones in the board files are not really correct, although the dss driver works
ok with them.

So these patches add new regulator supply entries. When these are merged, I'll
change omapdss driver to use the new ones, instead of the old ones. After that,
we can remove the old ones from the board files.

Note that these patches were also present in the big DSS series I sent
yesterday. There's no reason for these patches to be there, so I'm sending them
separately, and will drop these from my DSS series.

 Tomi

Tomi Valkeinen (3):
  ARM: OMAP: fix dsi regulator names
  ARM: OMAP: add vdds_dsi supply for omapdss_dpi.0
  ARM: OMAP: add vdds_sdi supply for omapdss_sdi.0

 arch/arm/mach-omap2/board-cm-t35.c           | 3 ++-
 arch/arm/mach-omap2/board-devkit8000.c       | 1 +
 arch/arm/mach-omap2/board-ldp.c              | 3 ++-
 arch/arm/mach-omap2/board-omap3pandora.c     | 1 +
 arch/arm/mach-omap2/board-rx51-peripherals.c | 1 +
 arch/arm/mach-omap2/twl-common.c             | 1 +
 6 files changed, 8 insertions(+), 2 deletions(-)

-- 
1.8.1.2



From tomi.valkeinen at ti.com  Fri May 31 03:37:54 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 May 2013 10:37:54 +0300
Subject: [PATCH 3/3] ARM: OMAP: add vdds_sdi supply for omapdss_sdi.0
In-Reply-To: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>
References: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>
Message-ID: <1369985874-8571-4-git-send-email-tomi.valkeinen@ti.com>

SDI driver gets currently the vdds_sdi regulator via omapdss device.
This is not correct, and we'll change the SDI driver to get the
regulator directly via omapdss_sdi.0 device.

This patch changes the rx51 board file to add vdds_dsi supply for
omapdss_sdi.0 device.

Note that the vdds_sdi supply for omapdss device is still left there, as
the current display driver uses it. When both the board files and the
display driver has been changed, we can remove the unused supply.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
---
 arch/arm/mach-omap2/board-rx51-peripherals.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 18ca61e..9c2dd10 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -553,6 +553,7 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
 
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
 	REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+	REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"),
 	/* Si4713 supply */
 	REGULATOR_SUPPLY("vdd", "2-0063"),
 	/* lis3lv02d */
-- 
1.8.1.2



From tomi.valkeinen at ti.com  Fri May 31 03:37:52 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 May 2013 10:37:52 +0300
Subject: [PATCH 1/3] ARM: OMAP: fix dsi regulator names
In-Reply-To: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>
References: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>
Message-ID: <1369985874-8571-2-git-send-email-tomi.valkeinen@ti.com>

board-cm-t35.c and board-ldp.c contain regulator supply entries for
vdds_dsi. However, the given device name is wrong.

This patch fixes the device name from omapdss_dsi1 to omapdss_dsi.0.

Note that as far as I know, DSI driver is not used on these boards, so
this should not have caused any problems. The DSI block can be used to
generate clock for DPI, though, but that's not enabled for omap3 boards
currently.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
---
 arch/arm/mach-omap2/board-cm-t35.c | 2 +-
 arch/arm/mach-omap2/board-ldp.c    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ee6218c..ce00968 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,7 +293,7 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
 static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
 	REGULATOR_SUPPLY("vcc", "spi1.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d0d17bc..3dbc881 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,7 +272,7 @@ static struct regulator_init_data ldp_vaux1 = {
 
 static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
 static struct regulator_init_data ldp_vpll2 = {
-- 
1.8.1.2



From tomi.valkeinen at ti.com  Fri May 31 03:37:53 2013
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 May 2013 10:37:53 +0300
Subject: [PATCH 2/3] ARM: OMAP: add vdds_dsi supply for omapdss_dpi.0
In-Reply-To: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>
References: <1369985874-8571-1-git-send-email-tomi.valkeinen@ti.com>
Message-ID: <1369985874-8571-3-git-send-email-tomi.valkeinen@ti.com>

DPI driver gets currently the vdds_dsi regulator via omapdss device.
This is not correct, and we'll change the DPI driver to get the
regulator directly via omapdss_dpi.0 device.

This patch changes the relevant board files to add vdds_dsi supply for
omapdss_dpi.0 device.

Note that the vdds_dsi supply for omapdss device is still left there, as
the current display driver uses it. When both the board files and the
display driver has been changed, we can remove the unused supply.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
---
 arch/arm/mach-omap2/board-cm-t35.c       | 1 +
 arch/arm/mach-omap2/board-devkit8000.c   | 1 +
 arch/arm/mach-omap2/board-ldp.c          | 1 +
 arch/arm/mach-omap2/board-omap3pandora.c | 1 +
 arch/arm/mach-omap2/twl-common.c         | 1 +
 5 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ce00968..d4622ed 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,6 +293,7 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
 static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
 	REGULATOR_SUPPLY("vcc", "spi1.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 5764205..f1d91ba 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -222,6 +222,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
 
 static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 3dbc881..62e4f70 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,6 +272,7 @@ static struct regulator_init_data ldp_vaux1 = {
 
 static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 28133d5..b1547a0 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -343,6 +343,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
 static struct regulator_consumer_supply pandora_vdds_supplies[] = {
 	REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 51e138c..c05898f 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -140,6 +140,7 @@ static struct regulator_init_data omap3_vdac_idata = {
 
 static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
 	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
-- 
1.8.1.2



From laurent.pinchart at ideasonboard.com  Fri May 31 03:43:30 2013
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Fri, 31 May 2013 09:43:30 +0200
Subject: [RFC PATCHv4 0/6] arm: Initial TI-Nspire support
In-Reply-To: <1369738372.3148.7.camel@hornet>
References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com>
 <201305271231.40693.arnd@arndb.de> <1369738372.3148.7.camel@hornet>
Message-ID: <2266847.DGUdOCUR2h@avalon>

Hi Pawel,

Sorry for the late reply, I'm currently attending LinuxCon Japan, my mail 
backlog is growing.

On Tuesday 28 May 2013 11:52:52 Pawel Moll wrote:
> On Mon, 2013-05-27 at 11:31 +0100, Arnd Bergmann wrote:
> > On Monday 27 May 2013, Daniel Tang wrote:
> > > > The one remaining bit that sticks out is the clcd platform data. As I
> > > > said before, I won't require you to convert that to DT in order to
> > > > get your code merged, but I'd also really like to see that happen,
> > > > as we will also need that to get rid of auxdata on the ARM reference
> > > > platforms (integrator, versatile, realview, vexpress).
> > > 
> > > How would you like me to convert the platform data to DT? AFAIK, the
> > > clcd driver isn't aware of DT so the only way is to use the AUXDATA
> > > right now.
> > 
> > Linus Walleij mentioned on IRC that Pawel Moll already posted a series
> > that adds DT support for clcd:
> > 
> > http://lists.freedesktop.org/archives/dri-devel/2013-April/037519.html
> > 
> > The series does a few more things, but you can probbly split out the
> > parts you need and base on that.
> 
> The main "issue" with the series is its dependency on Laurent Pinchart's
> Common Display Framework (or rather on the progress of its upstreaming).
> I'm planning to discuss this in details in during the Linaro Connect in
> Dublin, but generally, if it's not getting merged in the next window,
> I'll spin the series to use the standard video modes bindings instead of
> CDF. This will make me hurt on Versatile Express, but should work for
> others.

I've met with Tomi Valkeinen (TI), Alexandre Courbot (NVidia) and Tomasz Figa 
(Samsung) recently, For the first time the meetings helped narrowing the 
options *down*. It seems a path is slowly unfolding, and I would like to 
target v3.13 for a first (possibly limited) version.

Regarding the DT bindings, Alexandre and Tomasz will look into the V4L2 DT 
bindings to see whether/how they can be reused/leveraged for the CDF bindings. 
In both case we need to describe a graph of connected entities, and there's 
not much in the V4L2 DT bindings that is V4L2-specific in that regard.

-- 
Regards,

Laurent Pinchart



From horms at verge.net.au  Fri May 31 03:43:26 2013
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 May 2013 16:43:26 +0900
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <CAOesGMgrdyFi3GMz52CVnhzmOYHbR5=29Ua0iS8cNbSjg6r-2A@mail.gmail.com>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
 <20130531001735.GA26684@verge.net.au>
 <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>
 <20130531054517.GC5009@verge.net.au>
 <CAOesGMgrdyFi3GMz52CVnhzmOYHbR5=29Ua0iS8cNbSjg6r-2A@mail.gmail.com>
Message-ID: <20130531074323.GA22356@verge.net.au>

On Thu, May 30, 2013 at 11:11:36PM -0700, Olof Johansson wrote:
> On Thu, May 30, 2013 at 10:45 PM, Simon Horman <horms at verge.net.au> wrote:
> > On Thu, May 30, 2013 at 09:43:08PM -0700, Olof Johansson wrote:
> >> Hi,
> >>
> >> On Thu, May 30, 2013 at 5:17 PM, Simon Horman <horms at verge.net.au> wrote:
> >> > On Thu, May 30, 2013 at 10:08:56PM +0200, Linus Walleij wrote:
> >> >> On Thu, May 30, 2013 at 12:28 AM, Simon Horman
> >> >> <horms+renesas at verge.net.au> wrote:
> >> >>
> >> >> > From: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> >> >> >
> >> >> > The USB_OVCn pins are alternate options for USB over-current detection
> >> >> > when using a 3.3V USB interface. As they're not mandatory they can be
> >> >> > used independently of the USB PENC pins. Don't group the USB_OVCn and
> >> >> > PENC pins to avoid conflicts when the USB_OVCn pins are used by another
> >> >> > function.
> >> >> >
> >> >> > Reported-by: Sergei Shtylyov <sergei.shtylyov at cogentembedded.com>
> >> >> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> >> >> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> >> >>
> >> >> OK, Acked-by, do you want me to take this as a fix in the pinctrl
> >> >> tree for v3.10?
> >> >>
> >> >> Just asking because Simon usually takes everything else relating to
> >> >> the SH. ...
> >> >
> >> > This was a pull request from my tree to arm-soc, so thats they way
> >> > I was planning to handle things.
> >> >
> >> > Olof, Arnd,
> >> >
> >> > should I re-spin the pull request to include Linus's ack?
> >>
> >> You can if you want, but for an odd and specific fix like this we'll
> >> all know he's ok with the code going in.
> >
> > In that case my preference is to leave the pull request as is.
> > Could you consider merging it?
> 
> Yes, I will do a pass tomorrow and handle the outstanding merges.
> 
> > As an aside, I do expect to send some more v3.10 fixes for shmobile.
> > There seem to be more than usual.
> 
> A little unfortunate but it's hard to do much about.
> 
> Please be conservative with what you pick up for 3.10 vs 3.11 -- Linus
> has said he really wants to see things slow down.
> 
> And please make our case as easy as possible by making sure it's
> pretty clear from the patch descriptions what kind of bugs they fix
> (and if they are regressions).

Understood. I will be careful to only send the bare essentials for v3.10.


From nicolas.ferre at atmel.com  Fri May 31 03:54:49 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 09:54:49 +0200
Subject: [PATCH v3 0/5] rtc-at91rm9200: add shadow interrupt mask
In-Reply-To: <51A7DE20.5080603@interlog.com>
References: <1364983415-20298-1-git-send-email-jhovold@gmail.com>
 <1369298335-24597-1-git-send-email-jhovold@gmail.com>
 <20130529133354.dd181c845ee4e96527483345@linux-foundation.org>
 <CAOCHtYiK8Y6iTnb4dWAE+cKHqEta-64gj+PorSFVGBF5wmg1+Q@mail.gmail.com>
 <51A704C3.6010109@atmel.com>
 <20130530123609.6e2966a66dd7b131961ed052@linux-foundation.org>
 <51A7DE20.5080603@interlog.com>
Message-ID: <51A85749.6060005@atmel.com>

On 31/05/2013 01:17, Douglas Gilbert :
> On 13-05-30 03:36 PM, Andrew Morton wrote:
>> On Thu, 30 May 2013 09:50:27 +0200 Nicolas Ferre
>> <nicolas.ferre at atmel.com> wrote:
>>
>>> The review of this patch series was in my TODO list for some time...
>>>
>>> Today, I magically took time to review it ;-)
>>> The patch series is good and I (even if it is too late) here is my:
>>>
>>> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>>
>>> I do not know if the series can be stacked for inclusion in 3.10-rc but
>>> the resolution of this bug can help a lot (as Douglas is saying in
>>> subsequent email...).
>>
>> We can do that, but looking through the discussion and changelogs I
>> can't seem to find a usable description of what impact the bug (and its
>> fix) have upon end-users.
>>
>> A nicely packaged description of that impact would help grease the
>> wheels, please.
>
> How about this:
>
> The members of Atmel's at91sam9x5 family (9x5) have
> a broken RTC interrupt mask register (AT91_RTC_IMR).
> It does not reflect enabled interrupts but instead
> always returns zero.
>
> The kernel's rtc-at91rm9200 driver handles the RTC
> for the 9x5 family. Currently when the date/time is
> set, an interrupt is generated and this driver neglects
> to handle the interrupt. The kernel complains about the
> un-handled interrupt and disables it henceforth. This
> not only breaks the RTC function, but since that
> interrupt is shared (Atmel's SYS interrupt) then other
> things break as well (e.g. the debug port no longer
> accepts characters).
>
> Tested on the at91sam9g25. Bug confirmed by Atmel.

Absolutely. Thank you Douglas for the detailed description.

>
> Edit as you please.
>
> Doug Gilbert
>
>


-- 
Nicolas Ferre


From shawn.guo at linaro.org  Fri May 31 03:59:14 2013
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 May 2013 15:59:14 +0800
Subject: [PATCH v4 0/4] Add initial Freescale Vybrid VF610 support
In-Reply-To: <1369732343-2982-1-git-send-email-b35083@freescale.com>
References: <1369732343-2982-1-git-send-email-b35083@freescale.com>
Message-ID: <20130531075912.GA4101@S2101-09.ap.freescale.net>

On Tue, May 28, 2013 at 05:12:19PM +0800, Jingchang Lu wrote:
> Jingchang Lu (4):
>   ARM: imx: add VF610 clock support
>   ARM: imx: add initial support for VF610
>   ARM: dts: add SoC level device tree source for VF610
>   ARM: dts: add initial VF610 Tower board dts support

All applied, thanks.



From nicolas.ferre at atmel.com  Fri May 31 04:04:37 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 10:04:37 +0200
Subject: [PATCH 0/3] at_hdmac: dt dma bindings update
In-Reply-To: <20130530201321.GE23653@game.jcrosoft.org>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <20130530172649.GC3767@intel.com> <20130530201321.GE23653@game.jcrosoft.org>
Message-ID: <51A85995.1050909@atmel.com>

On 30/05/2013 22:13, Jean-Christophe PLAGNIOL-VILLARD :
> On 22:56 Thu 30 May     , Vinod Koul wrote:
>> On Thu, May 30, 2013 at 06:08:20PM +0200, ludovic.desroches at atmel.com wrote:
>>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>>
>>> Hi,
>>>
>>> This set of patches update the dt dma binding for at_hdmac since we need one
>>> more parameter. In order to keep backward compatibility, an existing cell will
>>> be used to add this parameter. Since the content of that cell will become a
>>> magic value due to the concatenation of the two parameters, it is time to
>>> use macros.
>> which tree is this targetted to be applied?
>
> arm-soc as this depends on alreadied applied cleanup I've

... already pushed (it must be the end of your sentence, Jean-Christophe...)

Vinod, Arnd,

- patch 1 shall be applied before any of the two others of the series
- patch 2 is pure DT modification, but relies on Jean-Christophe's
   already pushed cleanup branch in arm-soc
- patch 3 is the pure dmaengine one, but relies on the 1st patch

So, maybe the preferred way to include this material upstream is to go 
through arm-soc as suggested by Jean-Christophe.

Bye,

>> Arnd, can you review this series and ack if this needs to be applied thru
>> dmaengine?
>
> I prefer the invert
>
> Best Regards,
> J.
>>
>> --
>> ~Vinod
>>>
>>> Regards
>>>
>>> Ludovic Desroches (3):
>>>    ARM: at91: dt: add header to define at_hdmac configuration
>>>    ARM: at91: dt: switch DMA DT bindings to pre-processor
>>>    at_hdmac: add FIFO configuration parameter to DMA DT binding
>>>
>>>   .../devicetree/bindings/dma/atmel-dma.txt          |  7 ++++--
>>>   arch/arm/boot/dts/at91sam9g45.dtsi                 |  5 ++--
>>>   arch/arm/boot/dts/at91sam9n12.dtsi                 | 11 +++++----
>>>   arch/arm/boot/dts/at91sam9x5.dtsi                  | 17 +++++++-------
>>>   arch/arm/boot/dts/sama5d3.dtsi                     | 19 +++++++--------
>>>   drivers/dma/at_hdmac.c                             | 25 ++++++++++++++++----
>>>   include/dt-bindings/dma/at91.h                     | 27 ++++++++++++++++++++++
>>>   7 files changed, 81 insertions(+), 30 deletions(-)
>>>   create mode 100644 include/dt-bindings/dma/at91.h
>>>
>>> --
>>> 1.7.11.3
>>>
>>
>> --
>


-- 
Nicolas Ferre


From magnus.damm at gmail.com  Fri May 31 03:57:08 2013
From: magnus.damm at gmail.com (Magnus Damm)
Date: Fri, 31 May 2013 16:57:08 +0900
Subject: [PATCH 04/12] ARM: shmobile: r8a7740: Add DT name to clock list
 for CMT10
In-Reply-To: <20130528062246.GB20031@quad.lixom.net>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <1369645193-3595-5-git-send-email-horms+renesas@verge.net.au>
 <20130528032948.GF13532@quad.lixom.net>
 <20130528052944.GC25005@verge.net.au>
 <20130528062246.GB20031@quad.lixom.net>
Message-ID: <CANqRtoRwBHY1+Tgekg1CocZa4zWCAUWuZnW=5MXTA9SPcWYD0A@mail.gmail.com>

Hi Olof,

On Tue, May 28, 2013 at 3:22 PM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, May 28, 2013 at 02:29:44PM +0900, Simon Horman wrote:
>> On Mon, May 27, 2013 at 08:29:48PM -0700, Olof Johansson wrote:
>> > Hi,
>> >
>> > On Mon, May 27, 2013 at 05:59:45PM +0900, Simon Horman wrote:
>> > > From: Bastian Hecht <hechtb at gmail.com>
>> > >
>> > > This adds temporarily the alternative device name to the clock list
>> > > that is used when booting via Device Tree setup.
>> >
>> > >
>> > > Signed-off-by: Bastian Hecht <hechtb+renesas at gmail.com>
>> > > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
>> > > ---
>> > >  arch/arm/mach-shmobile/clock-r8a7740.c |    1 +
>> > >  1 file changed, 1 insertion(+)
>> > >
>> > > diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
>> > > index 5bd8da0..8fc396a 100644
>> > > --- a/arch/arm/mach-shmobile/clock-r8a7740.c
>> > > +++ b/arch/arm/mach-shmobile/clock-r8a7740.c
>> > > @@ -582,6 +582,7 @@ static struct clk_lookup lookups[] = {
>> > >   CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
>> > >
>> > >   CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
>> > > + CLKDEV_DEV_ID("e6138010.timer",         &mstp_clks[MSTP329]),
>> > >   CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
>> > >   CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
>> > >   CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
>> > > --
>> > > 1.7.10.4
>> > >
>> >
>> > Usually this is instead handled by adding entries to OF_DEV_AUXDATA() to
>> > rename the device in the board file. Would you mind doing that instead?
>>
>> Magnus has indicated in the past that he prefers this method over
>> using OF_DEV_AUXDATA() and the above is consistent with other
>> shmobile code.
>
> Ho hum. That's 180 degrees opposite to how we've been doing it on all
> other ARM platforms. :)

Correct! =) But that is not the only thing! The mach-shmobile
implementation style for DT is also different. I guess you've seen
other mach-shmobile-specific oddities like the DT -reference boards in
parallel with the C version, right?

With mach-shmobile we have deliberately chosen to avoid AUXDATA. The
reason for that is that we keep the DT version of a device clean from
the beginning so it is kept totally free of platform data while in
parallel we also have a regular platform device with platform data for
the old legacy C version of board support. Other ARM subarchitectures
seem to use DT together with platform data which is a step that we
prefer to skip by using a C version and a DT version of board support
in parallel. The idea is that we should be able to existing level of
support in the C version while incrementally doing development on the
DT -reference code. Then drop the C version when the DT version has
become good enough. Current blockers are GPIO/PFC DT and common clock
framework.

Regarding AUXDATA, I don't really mind using it that much, except that
I prefer to not use DT together with platform data. So that's what
we've been doing. As for device name conversion with AUXDATA, yes, we
could use that, but it turns out that if you're not using platform
data then it becomes more verbose line wise compared to just popping
in an additional line in the clock lookup like the patch above does.
It is already abstracted per-SoC but with AUXDATA i suspect we will
have to mix board specific bits with new SoC specific tables.

You can probably find other instances of similar mixed DT names with
regular platform device names in various clock lookup tables in
mach-shmobile. Of course we will convert them over if that makes your
life easier. Personally, due to limited time I'd rather work on other
non-cosmetic stuff like getting rid off CONFIG_MEMORY_START and others
and also fixing up 64-bit memory that seems broken in the generic ARM
kernel.

> Once you guys have clock bindings for device tree, the aliases should be
> possible to remove. That's where having them as auxdata is useful, since it's
> just one place and it's also obvious just what clocks and what drivers need
> aliases on device tree.

I agree that common clocks and DT bindings will make it possible for
us to remove these special cases, but from my point of view it is even
easier to kill off DT special case names like we already have in
clock-r8axxx.c when moving to common clocks (and getting rid of that
file) instead of introducing AUXDATA just to remove it soon again.

> Where are you guys at on your plans for getting DT_based clock going? That will
> sort of indicate just how temporary these clock alaises will be. I'm guessing
> we'll be living with them for a while though?

I have to deal with LPAE soon according to my todo list. After that I
will make sure common clock conversion starts moving. There are many
SoCs to convert, so it will have to happen gradually. I doubt we will
get any code ready for merge in v3.11, getting some bits into v3.12 is
probably possible.

Apart from moving to common clocks and after that adding support for a
single multi-subarch kernel binary, is there anything you want us to
implement? Anything for v3.11? I'd like to get the memory bits sorted
out if possible.

Thanks for your help.

Cheers,

/ magnus


From florian.vaussard at epfl.ch  Fri May 31 04:17:22 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 10:17:22 +0200
Subject: [PATCH 1/2] gpiolib: add gpio_export_with_name
In-Reply-To: <CACRpkdZMj-Xin5PMDWavaWOTCSZF3NBWXk4fG4QXsJzhwBcs_Q@mail.gmail.com>
References: <20121121101259.GQ4398@game.jcrosoft.org>
 <1353492849-29397-1-git-send-email-plagnioj@jcrosoft.com>
 <20121126135911.2F1D33E187C@localhost> <51A719A5.50906@epfl.ch>
 <CACRpkdb9F+wJ0hkNqPTP34r3JAEp2s07Q8U24fD6oCdj7MqCFA@mail.gmail.com>
 <51A7B8CD.4080702@epfl.ch>
 <CACRpkdZMj-Xin5PMDWavaWOTCSZF3NBWXk4fG4QXsJzhwBcs_Q@mail.gmail.com>
Message-ID: <51A85C92.4090701@epfl.ch>

Hello Linus,

On 05/30/2013 11:11 PM, Linus Walleij wrote:
> On Thu, May 30, 2013 at 10:38 PM, Florian Vaussard
> <florian.vaussard at epfl.ch> wrote:
>
>> Indeed, I work in a robotics lab :-) One of our board (mach-imx/
>> mx31moboard*.c) controls for example the multiplexing of two cameras
>> sharing the same acquisition bus (I know, a bit hackish).
>> I developed a similar board with an OMAP3. Such control do not
>> fit well in the above-mentioned cases, but we do not need RT processes.
>
> It does seem to fit well with V4L and/or the media controller
> framework though, or is this one of those "oh, we don't really
> like to use V4L so we have this special hack instead" things?
>

Sorry, I was not aware of this mux capability inside V4L. Thank
you. So we can live without gpio-export for most of our hardware.

Regards,

Florian


From prabhakar.csengg at gmail.com  Fri May 31 04:43:00 2013
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 31 May 2013 14:13:00 +0530
Subject: [PATCH v2 1/4] ARM: davinci: dm365 evm: remove init_enable from
 ths7303 pdata
In-Reply-To: <CA+V-a8sAXXq=gBO_uDsOS1MonXJan+mpBwo15tvp+wR40kAMKA@mail.gmail.com>
References: <1369503576-22271-1-git-send-email-prabhakar.csengg@gmail.com>
 <1369503576-22271-2-git-send-email-prabhakar.csengg@gmail.com>
 <CA+V-a8sAXXq=gBO_uDsOS1MonXJan+mpBwo15tvp+wR40kAMKA@mail.gmail.com>
Message-ID: <CA+V-a8t8vx2S0rAZrZysF9PT2zVwx+EM0B5D=t50qoSiW8U_GA@mail.gmail.com>

Hi Sekhar,

On Sat, May 25, 2013 at 11:13 PM, Prabhakar Lad
<prabhakar.csengg at gmail.com> wrote:
> Hi Sekhar,
>
> On Sat, May 25, 2013 at 11:09 PM, Prabhakar Lad
> <prabhakar.csengg at gmail.com> wrote:
>> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
>>
>> remove init_enable from ths7303 pdata as it is being dropped
>> from ths7303_platform_data.
>>
> Can you please ack this patch as I intend to take this patch via media
> tree.
gentle ping.

Regards,
--Prabhakar


From will.deacon at arm.com  Fri May 31 04:45:08 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 31 May 2013 09:45:08 +0100
Subject: A bug about system call on ARM
In-Reply-To: <alpine.LFD.2.03.1305302319430.30828@syhkavp.arg>
References: <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <alpine.LFD.2.03.1305302319430.30828@syhkavp.arg>
Message-ID: <20130531084508.GA4928@mudshark.cambridge.arm.com>

On Fri, May 31, 2013 at 04:54:56AM +0100, Nicolas Pitre wrote:
> On Thu, 30 May 2013, Will Deacon wrote:
> 
> > On Thu, May 30, 2013 at 10:09:49AM +0100, Will Deacon wrote:
> > > On Thu, May 30, 2013 at 02:41:42AM +0100, Wang, Yalin wrote:
> > > > If you have some patch for this issue,
> > > > I can do the test for it .
> > > 
> > > I'll have a look at cooking something which uses an exception table entry
> > > to rewind the PC and retry the system call. That's simpler than directly
> > > injecting a user page fault from the system call path.
> > 
> > Ok, please can you try the following?
> > 
> > Will
> > 
> > --->8
> > 
> > diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> > index bc5bc0a..855926e 100644
> > --- a/arch/arm/kernel/entry-common.S
> > +++ b/arch/arm/kernel/entry-common.S
> > @@ -361,6 +361,15 @@ ENTRY(vector_swi)
> >  	str	r8, [sp, #S_PSR]		@ Save CPSR
> >  	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
> >  	zero_fp
> > +	enable_irq
> > +	ct_user_exit
> > +
> > +#ifdef CONFIG_ALIGNMENT_TRAP
> > +	ldr	ip, __cr_alignment
> > +	ldr	ip, [ip]
> > +	mcr	p15, 0, ip, c1, c0		@ update control register
> > +#endif
> 
> This is wrong.  you must set up the align bit in the control register 
> _before_ enabling IRQs or an IRQ handler might run without alignment 
> fixup.

Okey doke, I can fix that up. I thought it was only needed for the network
layer, but I suppose they have interrupts over there too :)

> Otherwise the patch looks good to me.

Thanks Nicolas.

Will


From will.deacon at arm.com  Fri May 31 04:46:38 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 31 May 2013 09:46:38 +0100
Subject: A bug about system call on ARM
In-Reply-To: <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
References: <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
Message-ID: <20130531084638.GB4928@mudshark.cambridge.arm.com>

On Fri, May 31, 2013 at 03:56:31AM +0100, Wang, Yalin wrote:
> Hi Will,
> 
> Thanks for your patch ,
> 
> But I found  I don't have ct_user_exit  macro 
> In my arch/arm/kernel/entry-common.S 
> 
> My kernel version is 3.4.0 

Well things have moved on this since then (we're approaching 3.10, so you
might consider an upgrade!).

For the purposes of this patch, you can just delete the ct_user_exit line.

Will


From will.deacon at arm.com  Fri May 31 04:47:03 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 31 May 2013 09:47:03 +0100
Subject: [PATCH V1] ARM: mm: lazy cache flushing on non-mapped pages
In-Reply-To: <CACVXFVNL032TY7b=YHEg9aaT_WNW3R8JOzaVqSbq09t2kcVOQg@mail.gmail.com>
References: <1369839416-27817-1-git-send-email-ming.lei@canonical.com>
 <20130530154047.GW7483@mudshark.cambridge.arm.com>
 <CACVXFVNL032TY7b=YHEg9aaT_WNW3R8JOzaVqSbq09t2kcVOQg@mail.gmail.com>
Message-ID: <20130531084703.GC4928@mudshark.cambridge.arm.com>

On Fri, May 31, 2013 at 05:31:59AM +0100, Ming Lei wrote:
> On Thu, May 30, 2013 at 11:40 PM, Will Deacon <will.deacon at arm.com> wrote:
> > Does the page_mapped test make the mapping_mapped test redundant? It sounds
> > strange if it's possible to get a non-zero mapcount for a page when its
> > address space isn't mapped.
> 
> Yes, page_mapped() should always return correct value for a page in page
> cache.
> 
> I keep the previous check just for safe reason, and I can remove it if
> you care.

I think it makes the code clearer and removes a check, so yes please.

Will


From b20788 at freescale.com  Fri May 31 17:01:52 2013
From: b20788 at freescale.com (Anson Huang)
Date: Fri, 31 May 2013 17:01:52 -0400
Subject: [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes.
Message-ID: <1370034115-24006-1-git-send-email-b20788@freescale.com>

Some clock gates are useful when we try to disable them
to save power, so we need to add these useful clock gate
into clock tree.

Signed-off-by: Anson Huang <b20788 at freescale.com>
---
 .../devicetree/bindings/clock/imx6q-clock.txt      |   13 +++++++++++++
 arch/arm/mach-imx/clk-imx6q.c                      |   17 ++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 6deb6fd..df68f99 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -208,6 +208,19 @@ clocks and IDs.
 	pll4_post_div		193
 	pll5_post_div		194
 	pll5_video_div		195
+	aips_tz1		196
+	aips_tz2		197
+	caam_mem		198
+	caam_aclk		199
+	caam_ipg		200
+	tzasc1			201
+	tzasc2			202
+	vdoa			203
+	mmdc_ch0_ipg		204
+	mmdc_ch1_ipg		205
+	mx6fast1		206
+	per2_main		207
+	emi_slow		208
 
 Examples:
 
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index dda9a2b..dfb77c1 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -238,7 +238,9 @@ enum mx6q_clks {
 	pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
 	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
 	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
+	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1,
+	aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg,
+	mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void)
 	clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
 
 	/*                                name             parent_name          reg         shift */
+	clk[aips_tz1]     = imx_clk_gate2("aips_tz1",      "ahb",               base + 0x68, 0);
+	clk[aips_tz2]     = imx_clk_gate2("aips_tz2",      "ahb",               base + 0x68, 2);
 	clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
 	clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
+	clk[caam_mem]     = imx_clk_gate2("caam_mem",      "ahb",               base + 0x68, 8);
+	clk[caam_aclk]    = imx_clk_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
+	clk[caam_ipg]     = imx_clk_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
 	clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
 	clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
 	clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
@@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void)
 	clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
 	clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
 	clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
+	clk[tzasc1]       = imx_clk_gate2("tzasc1",        "mmdc_ch0_axi_podf", base + 0x70, 22);
+	clk[tzasc2]       = imx_clk_gate2("tzasc2",        "mmdc_ch0_axi_podf", base + 0x70, 24);
+	clk[vdoa]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
 	clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
 	clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
 	clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
@@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void)
 	clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
 	clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
 	clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
+	clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg",  "ipg",               base + 0x74, 24);
+	clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg",  "ipg",               base + 0x74, 26);
 	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
 	clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
 	clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+	clk[mx6fast1]     = imx_clk_gate2("mx6fast1",      "ahb",               base + 0x78, 8);
 	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
+	clk[per2_main]    = imx_clk_gate2("per2_main",     "ahb",               base + 0x78, 14);
 	clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
 	clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
 	clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
@@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void)
 	clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
 	clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
 	clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+	clk[emi_slow]     = imx_clk_gate2("emi_slow",      "emi_slow_podf",     base + 0x80, 10);
 	clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
 	clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
 	clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
-- 
1.7.9.5




From b20788 at freescale.com  Fri May 31 17:01:55 2013
From: b20788 at freescale.com (Anson Huang)
Date: Fri, 31 May 2013 17:01:55 -0400
Subject: [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial
 enable_count
In-Reply-To: <1370034115-24006-1-git-send-email-b20788@freescale.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
Message-ID: <1370034115-24006-4-git-send-email-b20788@freescale.com>

Those always-on clocks need to be added into init_on array, this
is to avoid confusion when we dump the clock tree, the result
shows that some clocks are on but their enabled_count is 0.

Signed-off-by: Anson Huang <b20788 at freescale.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 390950e..66831a6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -247,7 +247,7 @@ static struct clk *clk[clk_max];
 static struct clk_onecell_data clk_data;
 
 static enum mx6q_clks const clks_init_on[] __initconst = {
-	mmdc_ch0_axi, rom, pll1_sys,
+	mmdc_ch0_axi, rom, pll1_sys, ckil, ocram, axi, ipg_per, mx6fast1, per2_main, aips_tz1, aips_tz2, mmdc_ch0_ipg, mmdc_ch1_ipg,
 };
 
 static struct clk_div_table clk_enet_ref_table[] = {
-- 
1.7.9.5




From b20788 at freescale.com  Fri May 31 17:01:53 2013
From: b20788 at freescale.com (Anson Huang)
Date: Fri, 31 May 2013 17:01:53 -0400
Subject: [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong
In-Reply-To: <1370034115-24006-1-git-send-email-b20788@freescale.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
Message-ID: <1370034115-24006-2-git-send-email-b20788@freescale.com>

per1_bch is sourced from ahb, previous parent
info is incorrect.

Signed-off-by: Anson Huang <b20788 at freescale.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index dfb77c1..c501947 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void)
 	clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
 	clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
 	clk[mx6fast1]     = imx_clk_gate2("mx6fast1",      "ahb",               base + 0x78, 8);
-	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
+	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "ahb",               base + 0x78, 12);
 	clk[per2_main]    = imx_clk_gate2("per2_main",     "ahb",               base + 0x78, 14);
 	clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
 	clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
-- 
1.7.9.5




From b20788 at freescale.com  Fri May 31 17:01:54 2013
From: b20788 at freescale.com (Anson Huang)
Date: Fri, 31 May 2013 17:01:54 -0400
Subject: [PATCH 3/4] ARM: imx: clk-imx6q: AXI clock select index is incorrect
In-Reply-To: <1370034115-24006-1-git-send-email-b20788@freescale.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
Message-ID: <1370034115-24006-3-git-send-email-b20788@freescale.com>

The AXI clock mux should be as below:

00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;

So, we need to insert a dummy clock for index 2b'10, otherwise,
if we want to select pll3_pfd1_540m as AXI's parent, it will
still source from periph.

Signed-off-by: Anson Huang <b20788 at freescale.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index c501947..390950e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -181,7 +181,7 @@ static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy",
 static const char *periph2_clk2_sels[]	= { "pll3_usb_otg", "pll2_bus", };
 static const char *periph_sels[]	= { "periph_pre", "periph_clk2", };
 static const char *periph2_sels[]	= { "periph2_pre", "periph2_clk2", };
-static const char *axi_sels[]		= { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *axi_sels[]		= { "periph", "pll2_pfd2_396m", "dummy", "pll3_pfd1_540m", };
 static const char *audio_sels[]	= { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
 static const char *gpu_axi_sels[]	= { "axi", "ahb", };
 static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
-- 
1.7.9.5




From tom.leiming at gmail.com  Fri May 31 05:07:22 2013
From: tom.leiming at gmail.com (Ming Lei)
Date: Fri, 31 May 2013 17:07:22 +0800
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
Message-ID: <CACVXFVOo6HNXeZ95QqAXU64aAmXXrTVsHJ9TvgirWKOWmwnSfA@mail.gmail.com>

On Sun, May 12, 2013 at 1:35 PM, Simon Baatz <gmbnomis at gmail.com> wrote:
> +void flush_kernel_dcache_page(struct page *page)
> +{
> +       if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> +               struct address_space *mapping;
> +
> +               mapping = page_mapping(page);
> +
> +               if (!mapping || mapping_mapped(mapping))

It is better to replace mapping_mapped(mapping) with page_mapped(page).

> +                       __flush_kernel_dcache_page(page);

I am wondering if I-cache should be flushed here since the user mapping
on the page may be executable and I/D coherency should be maintained.


Thanks,
-- 
Ming Lei


From ming.lei at canonical.com  Fri May 31 05:10:45 2013
From: ming.lei at canonical.com (Ming Lei)
Date: Fri, 31 May 2013 17:10:45 +0800
Subject: [PATCH V1] ARM: mm: lazy cache flushing on non-mapped pages
In-Reply-To: <20130531084703.GC4928@mudshark.cambridge.arm.com>
References: <1369839416-27817-1-git-send-email-ming.lei@canonical.com>
 <20130530154047.GW7483@mudshark.cambridge.arm.com>
 <CACVXFVNL032TY7b=YHEg9aaT_WNW3R8JOzaVqSbq09t2kcVOQg@mail.gmail.com>
 <20130531084703.GC4928@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVNivgi8RdjX8iabcrh2ed7ddfdsUK_vmm1_MYNFONzQUA@mail.gmail.com>

On Fri, May 31, 2013 at 4:47 PM, Will Deacon <will.deacon at arm.com> wrote:
>
> I think it makes the code clearer and removes a check, so yes please.

No problem, will do it in v2.


Thanks,
--
Ming Lei


From josephl at nvidia.com  Fri May 31 05:12:29 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 31 May 2013 17:12:29 +0800
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <51A763BD.6070001@linaro.org>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
 <51A763BD.6070001@linaro.org>
Message-ID: <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>

Hi Daniel,

Thanks for your review.

On Thu, 2013-05-30 at 22:35 +0800, Daniel Lezcano wrote:
> On 05/30/2013 01:19 PM, Joseph Lo wrote:
> > This supports CPU core power down on each CPU when CPU idle. When CPU go
> > into this state, it saves it's context and needs a proper configuration
> > in flow controller to power gate the CPU when CPU runs into WFI
> > instruction. And the CPU also needs to set the IRQ as CPU power down idle
> > wake up event in flow controller.
> > 
> > Signed-off-by: Joseph Lo <josephl at nvidia.com>
> > ---
> 
> Hi Joseph,
> 
> a new flag has been added in the cpuidle framework to let this one to
> handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP
> 
> It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c
> 
> You can get rid of the clockevent notify stuff by adding this flag to
> the state.
> 

I just tested this flag on Tegra20, 30 and 114. It is only OK on
Tegra20. It caused a warning message below on Tegra30/114 at boot time.

I gave it a quick check I found it can't clean
tick_broadcast_pending_mask sometimes if apply the flag. But I keep the
code right now it's always OK. Not sure why? 

[   25.629539] ------------[ cut here ]------------
[   25.629559] WARNING: CPU: 2 PID: 0 at
kernel/time/tick-broadcast.c:578 tick_broadcast_oneshot_control
+0x1a4/0x1d0()
[   25.629565] Modules linked in:
[   25.629574] CPU: 2 PID: 0 Comm: swapper/2 Not tainted
3.10.0-rc3-next-20130529+ #15
[   25.629601] [<c00148f4>] (unwind_backtrace+0x0/0xf8) from
[<c0011040>] (show_stack+0x10/0x14)
[   25.629616] [<c0011040>] (show_stack+0x10/0x14) from [<c0504248>]
(dump_stack+0x80/0xc4)
[   25.629633] [<c0504248>] (dump_stack+0x80/0xc4) from [<c00231ac>]
(warn_slowpath_common+0x64/0x88)
[   25.629646] [<c00231ac>] (warn_slowpath_common+0x64/0x88) from
[<c00231ec>] (warn_slowpath_null+0x1c/0x24)
[   25.629657] [<c00231ec>] (warn_slowpath_null+0x1c/0x24) from
[<c00667f8>] (tick_broadcast_oneshot_control+0x1a4/0x1d0)
[   25.629670] [<c00667f8>] (tick_broadcast_oneshot_control+0x1a4/0x1d0)
from [<c0065cd0>] (tick_notify+0x240/0x40c)
[   25.629685] [<c0065cd0>] (tick_notify+0x240/0x40c) from [<c0044724>]
(notifier_call_chain+0x44/0x84)
[   25.629699] [<c0044724>] (notifier_call_chain+0x44/0x84) from
[<c0044828>] (raw_notifier_call_chain+0x18/0x20)
[   25.629712] [<c0044828>] (raw_notifier_call_chain+0x18/0x20) from
[<c00650cc>] (clockevents_notify+0x28/0x170)
[   25.629726] [<c00650cc>] (clockevents_notify+0x28/0x170) from
[<c033f1f0>] (cpuidle_idle_call+0x11c/0x168)
[   25.629739] [<c033f1f0>] (cpuidle_idle_call+0x11c/0x168) from
[<c000ea94>] (arch_cpu_idle+0x8/0x38)
[   25.629755] [<c000ea94>] (arch_cpu_idle+0x8/0x38) from [<c005ea80>]
(cpu_startup_entry+0x60/0x134)
[   25.629767] [<c005ea80>] (cpu_startup_entry+0x60/0x134) from
[<804fe9a4>] (0x804fe9a4)
[   25.629772] ---[ end trace 5484e77e2531bccc ]---


> Also, can you clarify why tegra3 code is used in tegra114 ?
> 
Yes, because the flow controller that was used to control CPU power is
similar for both SoCs. The function is shared for Tegra30/114.

> 
> >  arch/arm/mach-tegra/cpuidle-tegra114.c | 62 +++++++++++++++++++++++++++++++++-
> >  1 file changed, 61 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
> > index 1d1c602..e7d21f5 100644
> > --- a/arch/arm/mach-tegra/cpuidle-tegra114.c
> > +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
> > @@ -17,19 +17,79 @@
> >  #include <linux/kernel.h>
> >  #include <linux/module.h>
> >  #include <linux/cpuidle.h>
> > +#include <linux/cpu_pm.h>
> > +#include <linux/clockchips.h>
> >  
> >  #include <asm/cpuidle.h>
> > +#include <asm/suspend.h>
> > +#include <asm/smp_plat.h>
> > +
> > +#include "pm.h"
> > +#include "sleep.h"
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int tegra114_idle_power_down(struct cpuidle_device *dev,
> > +				    struct cpuidle_driver *drv,
> > +				    int index);
> 
> Isn't possible to move the driver declaration after the
> tegra114_idle_power_down function, before the init function, so we
> prevent a forward declaration ?
> 
> > +#define TEGRA114_MAX_STATES 2
> > +#else
> > +#define TEGRA114_MAX_STATES 1
> > +#endif
> >  
> >  static struct cpuidle_driver tegra_idle_driver = {
> >  	.name = "tegra_idle",
> >  	.owner = THIS_MODULE,
> > -	.state_count = 1,
> > +	.state_count = TEGRA114_MAX_STATES,
> >  	.states = {
> >  		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
> > +#ifdef CONFIG_PM_SLEEP
> > +		[1] = {
> > +			.enter			= tegra114_idle_power_down,
> > +			.exit_latency		= 500,
> > +			.target_residency	= 1000,
> > +			.power_usage		= 0,
> > +			.flags			= CPUIDLE_FLAG_TIME_VALID,
> > +			.name			= "powered-down",
> > +			.desc			= "CPU power gated",
> > +		},
> > +#endif
> >  	},
> >  };
> >  
> > +#ifdef CONFIG_PM_SLEEP
> > +static int tegra114_idle_power_down(struct cpuidle_device *dev,
> > +				    struct cpuidle_driver *drv,
> > +				    int index)
> > +{
> > +	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
> 
> IMO, it is up to the tegra_set_cpu_in_lp2 / tegra_clear_cpu_in_lp2
> functions to do the cpu map conversion instead of adding this into a
> routine working with logical cpu.
> 
Good idea, I can create another patch to do that.

> > +	local_fiq_disable();
> > +
> > +	tegra_set_cpu_in_lp2(cpu);
> > +	cpu_pm_enter();
> > +
> > +	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
> > +	smp_wmb();
> 
> Why do you need a memory barrier here ?
> 
Yeah, Looks I don't have any static data that needs a barrier to sync
data for SMP here. Will remove them.

> > +	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
> > +
> > +	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
> > +
> > +	cpu_pm_exit();
> > +	tegra_clear_cpu_in_lp2(cpu);
> > +
> > +	local_fiq_enable();
> > +
> > +	smp_rmb();
> 
> Why do you need a memory barrier here ?
> 
> > +	return index;
> > +}
> > +#endif
> > +
> >  int __init tegra114_cpuidle_init(void)
> >  {
> > +#ifdef CONFIG_PM_SLEEP
> > +	tegra_tear_down_cpu = tegra30_tear_down_cpu;
> > +#endif
> 
> Doesn't this code should go in the pm.c file ?
> 
Yes, I had a plan to do that too. Currently It had a timing issue about
this. Because the CPU idle driver was registered by device_initcall, but
the PM init function was registered at late init. I need to sync the
init time first.
OK, will do that too.

Thanks,
Joseph




From ludovic.desroches at atmel.com  Fri May 31 05:16:27 2013
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Fri, 31 May 2013 11:16:27 +0200
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA DT
 binding
In-Reply-To: <20130530163936.GC23653@game.jcrosoft.org>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
 <51A77F10.8020808@atmel.com>
 <20130530163936.GC23653@game.jcrosoft.org>
Message-ID: <20130531091627.GD11384@ludovic.desroches@atmel.com>

On Thu, May 30, 2013 at 06:39:36PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 18:32 Thu 30 May     , Nicolas Ferre wrote:
> > On 30/05/2013 18:08, ludovic.desroches at atmel.com :
> > >From: Ludovic Desroches <ludovic.desroches at atmel.com>
> > >
> > >For most devices the FIFO configuration is the same i.e. when half FIFO size is
> > >available/filled, a source/destination request is serviced. But USART devices
> > >have to do it when there is enough space/data available to perform a single
> > >AHB access so the ASAP configuration.
> > >
> > >Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > >Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> > 
> > Clear and neat: thanks Ludo.
> 
> agreed
> 
> can we apply this via AT91 as this depends on some cleanup I did on DT and
> could result on some nigthmware conflict
> 

In fact, I am not sure it's the best solution. I have noticed that there is a
conflict with a patch sent by Nicolas (dmaengine: at_hdmac: extend hardware
handshaking interface identification) which is already in Vinod's tree but
which is not present on Jean-Christophe's cleanup tree on which I based these
patches.

Moreover this patch doesn't use macros introduced by Nicolas' patch. I may
update it and it should go through Vinod's tree with a dependence on patch 1/3.

What's your point of view?


From linus.walleij at stericsson.com  Fri May 31 05:18:37 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:37 +0200
Subject: [PATCH 02/39] ARM: u300: device tree support for the timer
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-3-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds device tree support for the U300 timer, by making
the memory base offset and IRQ dynamically assigned, then
optionally looking them up from the device tree.

Since the timer needs to be registered before any platform
devices are created, we will go into the device tree and look
up the "/timer at c0014000" node and read our base address and
IRQ from there.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Use CLOCKSOURCE_OF_DECLARE as suggested by Rob Herring, select
  this for the machine so we do not get compile warnings.
---
 .../bindings/timer/stericsson-u300-apptimer.txt    |  18 ++++
 arch/arm/Kconfig                                   |   1 +
 arch/arm/mach-u300/timer.c                         | 109 ++++++++++++++-------
 arch/arm/mach-u300/timer.h                         |   1 +
 4 files changed, 91 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt

diff --git a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
new file mode 100644
index 0000000..9499bc8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
@@ -0,0 +1,18 @@
+ST-Ericsson U300 apptimer
+
+Required properties:
+
+- compatible : should be "stericsson,u300-apptimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupts; one for each subtimer. These
+  are, in order: OS (operating system), DD (device driver) both
+  adopted for EPOC/Symbian with two specific IRQs for these tasks,
+  then GP1 and GP2, which are general-purpose timers.
+
+Example:
+
+timer {
+	compatible = "stericsson,u300-apptimer";
+	reg = <0xc0014000 0x1000>;
+	interrupts = <24 25 26 27>;
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d423d58..fbad333 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -821,6 +821,7 @@ config ARCH_U300
 	select ARM_VIC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
+	select CLKSRC_OF
 	select COMMON_CLK
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index c3d3802..df1e3b5 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -19,6 +19,8 @@
 #include <linux/err.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -190,6 +192,8 @@
 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 
+static void __iomem *u300_timer_base;
+
 /*
  * The u300_set_mode() function is always called first, if we
  * have oneshot timer active, the oneshot scheduling function
@@ -202,28 +206,28 @@ static void u300_set_mode(enum clock_event_mode mode,
 	case CLOCK_EVT_MODE_PERIODIC:
 		/* Disable interrupts on GPT1 */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Disable GP1 while we're reprogramming it. */
 		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+		       u300_timer_base + U300_TIMER_APP_DGPT1);
 		/*
 		 * Set the periodic mode to a certain number of ticks per
 		 * jiffy.
 		 */
 		writel(TICKS_PER_JIFFY,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+		       u300_timer_base + U300_TIMER_APP_GPT1TC);
 		/*
 		 * Set continuous mode, so the timer keeps triggering
 		 * interrupts.
 		 */
 		writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+		       u300_timer_base + U300_TIMER_APP_SGPT1M);
 		/* Enable timer interrupts */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Then enable the OS timer again */
 		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+		       u300_timer_base + U300_TIMER_APP_EGPT1);
 		break;
 	case CLOCK_EVT_MODE_ONESHOT:
 		/* Just break; here? */
@@ -234,33 +238,33 @@ static void u300_set_mode(enum clock_event_mode mode,
 		 */
 		/* Disable interrupts on GPT1 */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Disable GP1 while we're reprogramming it. */
 		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+		       u300_timer_base + U300_TIMER_APP_DGPT1);
 		/*
 		 * Expire far in the future, u300_set_next_event() will be
 		 * called soon...
 		 */
-		writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+		writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
 		/* We run one shot per tick here! */
 		writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+		       u300_timer_base + U300_TIMER_APP_SGPT1M);
 		/* Enable interrupts for this timer */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Enable timer */
 		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+		       u300_timer_base + U300_TIMER_APP_EGPT1);
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 		/* Disable interrupts on GP1 */
 		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+		       u300_timer_base + U300_TIMER_APP_GPT1IE);
 		/* Disable GP1 */
 		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-		       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+		       u300_timer_base + U300_TIMER_APP_DGPT1);
 		break;
 	case CLOCK_EVT_MODE_RESUME:
 		/* Ignore this call */
@@ -282,27 +286,27 @@ static int u300_set_next_event(unsigned long cycles,
 {
 	/* Disable interrupts on GPT1 */
 	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+	       u300_timer_base + U300_TIMER_APP_GPT1IE);
 	/* Disable GP1 while we're reprogramming it. */
 	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+	       u300_timer_base + U300_TIMER_APP_DGPT1);
 	/* Reset the General Purpose timer 1. */
 	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+	       u300_timer_base + U300_TIMER_APP_RGPT1);
 	/* IRQ in n * cycles */
-	writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
 	/*
 	 * We run one shot per tick here! (This is necessary to reconfigure,
 	 * the timer will tilt if you don't!)
 	 */
 	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+	       u300_timer_base + U300_TIMER_APP_SGPT1M);
 	/* Enable timer interrupts */
 	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+	       u300_timer_base + U300_TIMER_APP_GPT1IE);
 	/* Then enable the OS timer again */
 	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+	       u300_timer_base + U300_TIMER_APP_EGPT1);
 	return 0;
 }
 
@@ -321,8 +325,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = &clockevent_u300_1mhz;
 	/* ACK/Clear timer IRQ for the APP GPT1 Timer */
+
 	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+		u300_timer_base + U300_TIMER_APP_GPT1IA);
 	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
@@ -343,12 +348,12 @@ static struct irqaction u300_timer_irq = {
 
 static u32 notrace u300_read_sched_clock(void)
 {
-	return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
 
 static unsigned long u300_read_current_timer(void)
 {
-	return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
 
 static struct delay_timer u300_delay_timer;
@@ -356,11 +361,14 @@ static struct delay_timer u300_delay_timer;
 /*
  * This sets up the system timers, clock source and clock event.
  */
-void __init u300_timer_init(void)
+static void __init u300_timer_setup(void __iomem *base, int irq)
 {
 	struct clk *clk;
 	unsigned long rate;
 
+	u300_timer_base = base;
+	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
+
 	/* Clock the interrupt controller */
 	clk = clk_get_sys("apptimer", NULL);
 	BUG_ON(IS_ERR(clk));
@@ -378,40 +386,40 @@ void __init u300_timer_init(void)
 	 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 	 */
 	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+		u300_timer_base + U300_TIMER_APP_CRC);
 	writel(U300_TIMER_APP_ROST_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+		u300_timer_base + U300_TIMER_APP_ROST);
 	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+		u300_timer_base + U300_TIMER_APP_DOST);
 	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+		u300_timer_base + U300_TIMER_APP_RDDT);
 	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+		u300_timer_base + U300_TIMER_APP_DDDT);
 
 	/* Reset the General Purpose timer 1. */
 	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+		u300_timer_base + U300_TIMER_APP_RGPT1);
 
 	/* Set up the IRQ handler */
-	setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+	setup_irq(irq, &u300_timer_irq);
 
 	/* Reset the General Purpose timer 2 */
 	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+		u300_timer_base + U300_TIMER_APP_RGPT2);
 	/* Set this timer to run around forever */
-	writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
 	/* Set continuous mode so it wraps around */
 	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
-	       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+	       u300_timer_base + U300_TIMER_APP_SGPT2M);
 	/* Disable timer interrupts */
 	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+		u300_timer_base + U300_TIMER_APP_GPT2IE);
 	/* Then enable the GP2 timer to use as a free running us counter */
 	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
-		U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+		u300_timer_base + U300_TIMER_APP_EGPT2);
 
 	/* Use general purpose timer 2 as clock source */
-	if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+	if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
 			"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 		pr_err("timer: failed to initialize U300 clock source\n");
 
@@ -424,3 +432,28 @@ void __init u300_timer_init(void)
 	 * used by hrtimers!
 	 */
 }
+
+
+void __init u300_timer_init()
+{
+	u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
+}
+
+#ifdef CONFIG_OF
+
+static void __init u300_timer_init_of(struct device_node *np)
+{
+	void __iomem *base;
+	struct resource irq_res;
+	int irq;
+
+	base = of_iomap(np, 0);
+	/* Get the IRQ for the GP1 timer */
+	irq = of_irq_to_resource(np, 2, &irq_res);
+	u300_timer_setup(base, irq);
+}
+
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+		       u300_timer_init_of);
+
+#endif
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
index d34287b..7766dfa 100644
--- a/arch/arm/mach-u300/timer.h
+++ b/arch/arm/mach-u300/timer.h
@@ -1 +1,2 @@
 extern void u300_timer_init(void);
+
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:36 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:36 +0200
Subject: [PATCH 01/39] ARM: u300: enable delaytimer on the U300
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-2-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The U300 can support timer-based delays, so implement this.
Skips past jiffy calibration.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/timer.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index d9e7320..c3d3802 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -18,6 +18,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/irq.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -345,6 +346,12 @@ static u32 notrace u300_read_sched_clock(void)
 	return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 }
 
+static unsigned long u300_read_current_timer(void)
+{
+	return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+}
+
+static struct delay_timer u300_delay_timer;
 
 /*
  * This sets up the system timers, clock source and clock event.
@@ -362,6 +369,10 @@ void __init u300_timer_init(void)
 
 	setup_sched_clock(u300_read_sched_clock, 32, rate);
 
+	u300_delay_timer.read_current_timer = &u300_read_current_timer;
+	u300_delay_timer.freq = rate;
+	register_current_timer_delay(&u300_delay_timer);
+
 	/*
 	 * Disable the "OS" and "DD" timers - these are designed for Symbian!
 	 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:38 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:38 +0200
Subject: [PATCH 03/39] pinctrl: u300 device tree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-4-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds a simple device tree compat string for the U300 pin
controller. The base address is already passed properly as
a resource and everything works fine.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinctrl-u300.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 6a3a750..06bfa09 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -1105,10 +1105,17 @@ static int u300_pmx_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id u300_pinctrl_match[] = {
+	{ .compatible = "stericsson,pinctrl-u300" },
+	{},
+};
+
+
 static struct platform_driver u300_pmx_driver = {
 	.driver = {
 		.name = DRIVER_NAME,
 		.owner = THIS_MODULE,
+		.of_match_table = u300_pinctrl_match,
 	},
 	.probe = u300_pmx_probe,
 	.remove = u300_pmx_remove,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:35 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:35 +0200
Subject: [PATCH 00/39] U300 device tree and multiplatform
Message-ID: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This series of "only" 37 patches, partially sent earlier but
here in its final form, will convert the U300 platform to
using device tree exclusively, delete board files, and converts
the machine to multiplatform.

In order not to artificially split things up, two fixes from
Ulf Hansson and Peter Huewe are included.

A pull request will follow unless there are unfixable remarks.

Linus Walleij (37):
  ARM: u300: enable delaytimer on the U300
  ARM: u300: device tree support for the timer
  pinctrl: u300 device tree support
  pinctrl: coh901: add device tree support
  ARM: u300: basic device tree support
  i2c: stu300: device tree support
  ARM: u300: register I2C bus drivers from device tree
  watchdog: coh901327: devicetree support
  ARM: u300: add the COH 901 327 watchdog to device tree
  rtc: coh901331: add devicetree support
  ARM: u300: add RTC to device tree
  ARM: u300: set up board power from device tree
  ARM: u300: support regulators in the device tree
  ARM: u300: enable MMC/SD card from device tree
  dma: coh901318: add devicetree support
  ARM: u300: augment device tree with DMA channels
  ARM: u300: add the COH 901 318 DMAC to device tree
  ARM: u300: add SPI PL022 to the device tree
  ARM: u300: probe the U300 dummy-spichip from device tree
  ARM: u300: add FSMC flash into the device tree
  ARM: u300: delete all static board data
  ARM: u300: move debugmacro to debug includes
  ARM: u300: remove deps from debug macro
  ARM: u300: push down syscon registers
  ARM: u300: delete <mach/hardware.h>
  ARM: u300: delete <mach/irqs.h>
  ARM: u300: localize <mach/u300-regs.h>
  ARM: u300: convert to multiplatform
  ARM: u300: delete remnant machine headers
  ARM: u300: add syscon node
  ARM: u300: remove register definition file
  clk: move the U300 fixed and fixed-factor to DT
  i2c: stu300: do not request a specific clock name
  ARM: u300: move the gated system controller clocks to DT
  ARM: u300: convert MMC/SD clock to device tree
  pinctrl: get rid of all platform data for coh901
  spi: pl022: use DMA by default when probing from DT

Peter Huewe (1):
  ARM: u300 use module_spi_driver to register driver

Ulf Hansson (1):
  ARM: u300: Update MMC configs for u300 defconfig

 Documentation/devicetree/bindings/arm/ste-u300.txt |  46 ++
 .../bindings/clock/ste-u300-syscon-clock.txt       |  80 +++
 .../devicetree/bindings/dma/ste-coh901318.txt      |  32 +
 .../bindings/gpio/gpio-stericsson-coh901.txt       |   7 +
 .../devicetree/bindings/i2c/i2c-st-ddci2c.txt      |  15 +
 .../bindings/timer/stericsson-u300-apptimer.txt    |  18 +
 .../bindings/watchdog/stericsson-coh901327.txt     |  19 +
 arch/arm/Kconfig                                   |  19 +-
 arch/arm/Kconfig.debug                             |   8 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/ste-u300.dts                     | 473 +++++++++++++
 arch/arm/configs/u300_defconfig                    |  14 +-
 .../mach/debug-macro.S => include/debug/u300.S}    |   9 +-
 arch/arm/mach-u300/Kconfig                         |  31 +-
 arch/arm/mach-u300/Makefile                        |   2 -
 arch/arm/mach-u300/core.c                          | 759 +++++++--------------
 arch/arm/mach-u300/dummyspichip.c                  |  20 +-
 arch/arm/mach-u300/i2c.c                           | 285 --------
 arch/arm/mach-u300/i2c.h                           |  23 -
 arch/arm/mach-u300/include/mach/hardware.h         |   5 -
 arch/arm/mach-u300/include/mach/irqs.h             |  80 ---
 arch/arm/mach-u300/include/mach/syscon.h           | 592 ----------------
 arch/arm/mach-u300/include/mach/timex.h            |  17 -
 arch/arm/mach-u300/include/mach/u300-regs.h        | 165 -----
 arch/arm/mach-u300/include/mach/uncompress.h       |  45 --
 arch/arm/mach-u300/regulator.c                     |  62 +-
 arch/arm/mach-u300/spi.c                           | 102 ---
 arch/arm/mach-u300/spi.h                           |  26 -
 arch/arm/mach-u300/timer.c                         | 113 +--
 arch/arm/mach-u300/timer.h                         |   1 -
 arch/arm/mach-u300/u300-gpio.h                     |  70 --
 drivers/clk/clk-u300.c                             | 718 +++++++++++++++----
 drivers/dma/coh901318.c                            |  43 ++
 drivers/i2c/busses/i2c-stu300.c                    |  16 +-
 drivers/pinctrl/pinctrl-coh901.c                   |  35 +-
 drivers/pinctrl/pinctrl-u300.c                     |   7 +
 drivers/rtc/rtc-coh901331.c                        |   6 +
 drivers/spi/spi-pl022.c                            |   1 +
 drivers/watchdog/coh901327_wdt.c                   |  12 +-
 include/linux/platform_data/pinctrl-coh901.h       |  22 -
 40 files changed, 1784 insertions(+), 2215 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/ste-u300.txt
 create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
 create mode 100644 Documentation/devicetree/bindings/dma/ste-coh901318.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
 create mode 100644 Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
 create mode 100644 Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
 create mode 100644 arch/arm/boot/dts/ste-u300.dts
 rename arch/arm/{mach-u300/include/mach/debug-macro.S => include/debug/u300.S} (78%)
 delete mode 100644 arch/arm/mach-u300/i2c.c
 delete mode 100644 arch/arm/mach-u300/i2c.h
 delete mode 100644 arch/arm/mach-u300/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-u300/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-u300/include/mach/syscon.h
 delete mode 100644 arch/arm/mach-u300/include/mach/timex.h
 delete mode 100644 arch/arm/mach-u300/include/mach/u300-regs.h
 delete mode 100644 arch/arm/mach-u300/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-u300/spi.c
 delete mode 100644 arch/arm/mach-u300/spi.h
 delete mode 100644 arch/arm/mach-u300/timer.h
 delete mode 100644 arch/arm/mach-u300/u300-gpio.h
 delete mode 100644 include/linux/platform_data/pinctrl-coh901.h

-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:41 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:41 +0200
Subject: [PATCH 06/39] i2c: stu300: device tree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-7-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds device tree support for the ST DDC I2C driver known
as "stu300" in the kernel tree.

Reviewed-by: Wolfram Sang <wsa at the-dreams.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt | 15 +++++++++++++++
 drivers/i2c/busses/i2c-stu300.c                         | 12 ++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt

diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
new file mode 100644
index 0000000..bd81a48
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
@@ -0,0 +1,15 @@
+ST Microelectronics DDC I2C
+
+Required properties :
+- compatible : Must be "st,ddci2c"
+- reg: physical base address of the controller and length of memory mapped
+     region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- Child nodes conforming to i2c bus binding
+
+Examples :
+
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 0a6f941..1beaa05a 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -17,6 +17,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/of_i2c.h>
 
 /* the name of this kernel module */
 #define NAME "stu300"
@@ -923,6 +924,7 @@ stu300_probe(struct platform_device *pdev)
 	adap->nr = bus_nr;
 	adap->algo = &stu300_algo;
 	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
 	i2c_set_adapdata(adap, dev);
 
 	/* i2c device drivers may be active on return from add_adapter() */
@@ -934,6 +936,10 @@ stu300_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, dev);
+	dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
+		 dev->virtbase, dev->irq);
+	of_i2c_register_devices(adap);
+
 	return 0;
 }
 
@@ -978,11 +984,17 @@ stu300_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id stu300_dt_match[] = {
+	{ .compatible = "st,ddci2c" },
+	{},
+};
+
 static struct platform_driver stu300_i2c_driver = {
 	.driver = {
 		.name	= NAME,
 		.owner	= THIS_MODULE,
 		.pm	= STU300_I2C_PM,
+		.of_match_table = stu300_dt_match,
 	},
 	.remove		= __exit_p(stu300_remove),
 
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:43 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:43 +0200
Subject: [PATCH 08/39] watchdog: coh901327: devicetree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-9-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds support for probing the COH 901 327 watchdog from
the device tree and also adds associated bindings.

Acked-by: Wim Van Sebroeck <wim at iguana.be>
Reviewed-by: Guenter Roeck <linux at roeck-us.net>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 .../bindings/watchdog/stericsson-coh901327.txt        | 19 +++++++++++++++++++
 drivers/watchdog/coh901327_wdt.c                      | 12 +++++++++---
 2 files changed, 28 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt

diff --git a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
new file mode 100644
index 0000000..8ffb88e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
@@ -0,0 +1,19 @@
+ST-Ericsson COH 901 327 Watchdog timer
+
+Required properties:
+- compatible: must be "stericsson,coh901327".
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: the interrupt used for the watchdog timeout warning.
+
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+
+Example:
+
+watchdog: watchdog at c0012000 {
+	compatible = "stericsson,coh901327";
+	reg = <0xc0012000 0x1000>;
+	interrupts = <3>;
+	timeout-sec = <60>;
+};
diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c
index b9b8a8b..4bd070f 100644
--- a/drivers/watchdog/coh901327_wdt.c
+++ b/drivers/watchdog/coh901327_wdt.c
@@ -354,9 +354,9 @@ static int __init coh901327_probe(struct platform_device *pdev)
 
 	clk_disable(clk);
 
-	if (margin < 1 || margin > 327)
-		margin = 60;
-	coh901327_wdt.timeout = margin;
+	ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev);
+	if (ret < 0)
+		coh901327_wdt.timeout = 60;
 
 	ret = watchdog_register_device(&coh901327_wdt);
 	if (ret == 0)
@@ -441,10 +441,16 @@ void coh901327_watchdog_reset(void)
 	/* Return and await doom */
 }
 
+static const struct of_device_id coh901327_dt_match[] = {
+	{ .compatible = "stericsson,coh901327" },
+	{},
+};
+
 static struct platform_driver coh901327_driver = {
 	.driver = {
 		.owner	= THIS_MODULE,
 		.name	= "coh901327_wdog",
+		.of_match_table = coh901327_dt_match,
 	},
 	.remove		= __exit_p(coh901327_remove),
 	.suspend	= coh901327_suspend,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:40 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:40 +0200
Subject: [PATCH 05/39] ARM: u300: basic device tree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-6-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This register the most basic peripherals and makes the
U300 boot to prompt from a device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Rename nodes in accordance with review comments from Arnd:
  - timer0 at x -> timer at x
  - gpioN at x -> gpio at x
  - pinctrl0 at x -> pinctrl at x
  - intc at 0xx -> interrupt-controller at x
  - uart at x -> serial at x
---
 Documentation/devicetree/bindings/arm/ste-u300.txt |  9 +++
 arch/arm/boot/dts/Makefile                         |  1 +
 arch/arm/boot/dts/ste-u300.dts                     | 86 ++++++++++++++++++++++
 arch/arm/mach-u300/core.c                          | 81 ++++++++++++++++++++
 4 files changed, 177 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/ste-u300.txt
 create mode 100644 arch/arm/boot/dts/ste-u300.dts

diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
new file mode 100644
index 0000000..222dca5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -0,0 +1,9 @@
+ST-Ericsson U300 Device Tree Bindings
+
+For various board the "board" node may contain specific properties
+that pertain to this particular board, such as board-specific GPIOs
+or board power regulator supplies.
+
+Required root node property:
+
+compatible="stericsson,u300";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..3dd1316 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
 	versatile-pb.dtb
+dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
 	vexpress-v2p-ca9.dtb \
 	vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
new file mode 100644
index 0000000..9e423eb
--- /dev/null
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -0,0 +1,86 @@
+/*
+ * Device Tree for the ST-Ericsson U300 Machine and SoC
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "ST-Ericsson U300";
+	compatible = "stericsson,u300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
+	};
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+        };
+
+	memory {
+		reg = <0x48000000 0x03c00000>;
+	};
+
+	timer: timer at c0014000 {
+		compatible = "stericsson,u300-apptimer";
+		reg = <0xc0014000 0x1000>;
+		interrupt-parent = <&vica>;
+		interrupts = <24 25 26 27>;
+	};
+
+	gpio: gpio at c0016000 {
+		compatible = "stericsson,gpio-coh901";
+		reg = <0xc0016000 0x1000>;
+		interrupt-parent = <&vicb>;
+		interrupts = <0 1 2 18 21 22 23>;
+		interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
+				"gpio4", "gpio5", "gpio6";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pinctrl: pinctrl at c0011000 {
+		compatible = "stericsson,pinctrl-u300";
+		reg = <0xc0011000 0x1000>;
+	};
+
+	amba {
+		compatible = "arm,amba-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		vica: interrupt-controller at a0001000 {
+			compatible = "arm,versatile-vic";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xa0001000 0x20>;
+		};
+
+		vicb: interrupt-controller at a0002000 {
+			compatible = "arm,versatile-vic";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xa0002000 0x20>;
+		};
+
+		uart0: serial at c0013000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xc0013000 0x1000>;
+			interrupt-parent = <&vica>;
+			interrupts = <22>;
+		};
+
+		uart1: serial at c0007000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xc0007000 0x1000>;
+			interrupt-parent = <&vicb>;
+			interrupts = <20>;
+		};
+	};
+};
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17..a210b1c 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -33,6 +33,9 @@
 #include <linux/platform_data/pinctrl-coh901.h>
 #include <linux/platform_data/dma-coh901318.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -698,3 +701,81 @@ MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
 	.init_machine	= u300_init_machine,
 	.restart	= u300_restart,
 MACHINE_END
+
+#ifdef CONFIG_OF
+
+/* These are mostly to get the right device names for the clock lookups */
+static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
+		"pinctrl-u300", NULL),
+	OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
+		"u300-gpio", &u300_gpio_plat),
+	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
+		"uart0", &uart0_plat_data),
+	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
+		"uart1", &uart1_plat_data),
+	OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
+		"mmci", &mmcsd_platform_data),
+	{ /* sentinel */ },
+};
+
+static void __init u300_init_irq_dt(void)
+{
+	struct clk *clk;
+
+	/* initialize clocking early, we want to clock the INTCON */
+	u300_clk_init(U300_SYSCON_VBASE);
+
+	/* Bootstrap EMIF and SEMI clocks */
+	clk = clk_get_sys("pl172", NULL);
+	BUG_ON(IS_ERR(clk));
+	clk_prepare_enable(clk);
+	clk = clk_get_sys("semi", NULL);
+	BUG_ON(IS_ERR(clk));
+	clk_prepare_enable(clk);
+
+	/* Clock the interrupt controller */
+	clk = clk_get_sys("intcon", NULL);
+	BUG_ON(IS_ERR(clk));
+	clk_prepare_enable(clk);
+
+	irqchip_init();
+}
+
+static void __init u300_init_machine_dt(void)
+{
+	u16 val;
+
+	/* Check what platform we run and print some status information */
+	u300_init_check_chip();
+
+	u300_assign_physmem();
+
+	/* Initialize pinmuxing */
+	pinctrl_register_mappings(u300_pinmux_map,
+				  ARRAY_SIZE(u300_pinmux_map));
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			u300_auxdata_lookup, NULL);
+
+	/* Enable SEMI self refresh */
+	val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+		U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
+	writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+}
+
+static const char * u300_board_compat[] = {
+	"stericsson,u300",
+	NULL,
+};
+
+DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
+	.map_io		= u300_map_io,
+	.init_irq	= u300_init_irq_dt,
+	.init_time	= clocksource_of_init,
+	.init_machine	= u300_init_machine_dt,
+	.restart	= u300_restart,
+	.dt_compat      = u300_board_compat,
+MACHINE_END
+
+#endif /* CONFIG_OF */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:42 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:42 +0200
Subject: [PATCH 07/39] ARM: u300: register I2C bus drivers from device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-8-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds the two I2C busses to the device tree so these
probe properly.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 18 ++++++++++++++++++
 arch/arm/mach-u300/core.c      |  4 ++++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 9e423eb..67a1b52 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -49,6 +49,24 @@
 		reg = <0xc0011000 0x1000>;
 	};
 
+	i2c0: i2c at c0004000 {
+		compatible = "st,ddci2c";
+		reg = <0xc0004000 0x1000>;
+		interrupt-parent = <&vicb>;
+		interrupts = <8>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	i2c1: i2c at c0005000 {
+		compatible = "st,ddci2c";
+		reg = <0xc0005000 0x1000>;
+		interrupt-parent = <&vicb>;
+		interrupts = <9>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
 	amba {
 		compatible = "arm,amba-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a210b1c..abe9704 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -714,6 +714,10 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
 		"uart1", &uart1_plat_data),
+	OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
+		"stu300.0", NULL),
+	OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
+		"stu300.1", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
 		"mmci", &mmcsd_platform_data),
 	{ /* sentinel */ },
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:44 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:44 +0200
Subject: [PATCH 09/39] ARM: u300: add the COH 901 327 watchdog to device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-10-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds the COH 901 327 watchdog to the U300 device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 7 +++++++
 arch/arm/mach-u300/core.c      | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 67a1b52..f0eb5f4 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -49,6 +49,13 @@
 		reg = <0xc0011000 0x1000>;
 	};
 
+	watchdog: watchdog at c0012000 {
+		compatible = "stericsson,coh901327";
+		reg = <0xc0012000 0x1000>;
+		interrupt-parent = <&vicb>;
+		interrupts = <3>;
+	};
+
 	i2c0: i2c at c0004000 {
 		compatible = "st,ddci2c";
 		reg = <0xc0004000 0x1000>;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index abe9704..190e788 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -710,6 +710,8 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"pinctrl-u300", NULL),
 	OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
 		"u300-gpio", &u300_gpio_plat),
+	OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
+		"coh901327_wdog", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:46 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:46 +0200
Subject: [PATCH 11/39] ARM: u300: add RTC to device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-12-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds the COH 901 331 RTC to the U300 device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 7 +++++++
 arch/arm/mach-u300/core.c      | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index f0eb5f4..711a2d9 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -56,6 +56,13 @@
 		interrupts = <3>;
 	};
 
+	rtc: rtc at c0017000 {
+		compatible = "stericsson,coh901331";
+		reg = <0xc0017000 0x1000>;
+		interrupt-parent = <&vicb>;
+		interrupts = <10>;
+	};
+
 	i2c0: i2c at c0004000 {
 		compatible = "st,ddci2c";
 		reg = <0xc0004000 0x1000>;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 190e788..637034b 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -712,6 +712,8 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"u300-gpio", &u300_gpio_plat),
 	OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
 		"coh901327_wdog", NULL),
+	OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
+		"rtc-coh901331", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:47 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:47 +0200
Subject: [PATCH 12/39] ARM: u300: set up board power from device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-13-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds support for setting up the board power from the
device tree on the U300. We use a board-specific node in the
device tree for the S365 board and bind a regulator for the
board power to this node.

Cc: Mark Brown <broonie at kernel.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 Documentation/devicetree/bindings/arm/ste-u300.txt | 13 +++++++
 arch/arm/mach-u300/regulator.c                     | 42 ++++++++++++++++++++--
 2 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
index 222dca5..cd9001a 100644
--- a/Documentation/devicetree/bindings/arm/ste-u300.txt
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -7,3 +7,16 @@ or board power regulator supplies.
 Required root node property:
 
 compatible="stericsson,u300";
+
+Boards with the U300 SoC include:
+
+S365 "Small Board U365":
+
+Required node: s365
+
+Example:
+
+s365 {
+	compatible = "stericsson,s365";
+	vana15-supply = <&ab3100_ldo_d_reg>;
+};
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 9c53f01..8a67dc6 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -10,9 +10,14 @@
 #include <linux/device.h>
 #include <linux/signal.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
 #include <linux/io.h>
+#include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 
@@ -47,13 +52,17 @@ void u300_pm_poweroff(void)
 /*
  * Hog the regulators needed to power up the board.
  */
-static int __init u300_init_boardpower(void)
+static int __init __u300_init_boardpower(struct platform_device *pdev)
 {
 	int err;
 	u32 val;
 
 	pr_info("U300: setting up board power\n");
-	main_power_15 = regulator_get(NULL, "vana15");
+	if (pdev)
+		main_power_15 = regulator_get(&pdev->dev, "vana15");
+	else
+		main_power_15 = regulator_get(NULL, "vana15");
+
 	if (IS_ERR(main_power_15)) {
 		pr_err("could not get vana15");
 		return PTR_ERR(main_power_15);
@@ -82,7 +91,34 @@ static int __init u300_init_boardpower(void)
 	return 0;
 }
 
+static int __init s365_board_probe(struct platform_device *pdev)
+{
+	return __u300_init_boardpower(pdev);
+}
+
+static const struct of_device_id s365_board_match[] = {
+	{ .compatible = "stericsson,s365" },
+	{},
+};
+
+static struct platform_driver s365_board_driver = {
+	.driver		= {
+		.name   = "s365-board",
+		.owner  = THIS_MODULE,
+		.of_match_table = s365_board_match,
+	},
+};
+
 /*
  * So at module init time we hog the regulator!
  */
-module_init(u300_init_boardpower);
+static int __init u300_init_boardpower(void)
+{
+	if (of_have_populated_dt())
+		return platform_driver_probe(&s365_board_driver,
+					     s365_board_probe);
+	/* Only call this on non-DT boots */
+	return __u300_init_boardpower(NULL);
+}
+
+device_initcall(u300_init_boardpower);
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:48 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:48 +0200
Subject: [PATCH 13/39] ARM: u300: support regulators in the device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-14-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Now that we have enabled board power and the AB3100 regulators,
put the regulator data into the device tree and enable it so
we can start to tie regulators to devices. To begin with we're
only supplying the power to the board itself.

Cc: Mark Brown <broonie at kernel.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 79 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 711a2d9..d1ab4e9 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -24,6 +24,11 @@
 		reg = <0x48000000 0x03c00000>;
 	};
 
+	s365 {
+		compatible = "stericsson,s365";
+		vana15-supply = <&ab3100_ldo_d_reg>;
+	};
+
 	timer: timer at c0014000 {
 		compatible = "stericsson,u300-apptimer";
 		reg = <0xc0014000 0x1000>;
@@ -70,6 +75,74 @@
 		interrupts = <8>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		ab3100: ab3100 at 0x48 {
+			compatible = "stericsson,ab3100";
+			reg = <0x48>;
+			interrupt-parent = <&vica>;
+			interrupts = <0>; /* EXT0 IRQ */
+			ab3100-regulators {
+				compatible = "stericsson,ab3100-regulators";
+				ab3100_ldo_a_reg: ab3100_ldo_a {
+					regulator-compatible = "ab3100_ldo_a";
+					startup-delay-us = <200>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+				ab3100_ldo_c_reg: ab3100_ldo_c {
+					regulator-compatible = "ab3100_ldo_c";
+					startup-delay-us = <200>;
+				};
+				ab3100_ldo_d_reg: ab3100_ldo_d {
+					regulator-compatible = "ab3100_ldo_d";
+					startup-delay-us = <200>;
+				};
+				ab3100_ldo_e_reg: ab3100_ldo_e {
+					regulator-compatible = "ab3100_ldo_e";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					startup-delay-us = <200>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+				ab3100_ldo_f_reg: ab3100_ldo_f {
+					regulator-compatible = "ab3100_ldo_f";
+					regulator-min-microvolt = <2500000>;
+					regulator-max-microvolt = <2500000>;
+					startup-delay-us = <600>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+				ab3100_ldo_g_reg: ab3100_ldo_g {
+					regulator-compatible = "ab3100_ldo_g";
+					regulator-min-microvolt = <1500000>;
+					regulator-max-microvolt = <2850000>;
+					startup-delay-us = <400>;
+				};
+				ab3100_ldo_h_reg: ab3100_ldo_h {
+					regulator-compatible = "ab3100_ldo_h";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <2750000>;
+					startup-delay-us = <200>;
+				};
+				ab3100_ldo_k_reg: ab3100_ldo_k {
+					regulator-compatible = "ab3100_ldo_k";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <2750000>;
+					startup-delay-us = <200>;
+				};
+				ab3100_ext_reg: ab3100_ext {
+					regulator-compatible = "ab3100_ext";
+				};
+				ab3100_buck_reg: ab3100_buck {
+					regulator-compatible = "ab3100_buck";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1800000>;
+					startup-delay-us = <1000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+			};
+		};
 	};
 
 	i2c1: i2c at c0005000 {
@@ -79,6 +152,12 @@
 		interrupts = <9>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		fwcam0: fwcam at 0x10 {
+			reg = <0x10>;
+		};
+		fwcam1: fwcam at 0x5d {
+			reg = <0x5d>;
+		};
 	};
 
 	amba {
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:45 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:45 +0200
Subject: [PATCH 10/39] rtc: coh901331: add devicetree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-11-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This add devicetree probe support to the COH 901 331 RTC
driver.

Cc: Alessandro Zummo <a.zummo at towertech.it>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Hi Alessandro, I'm seeking an ACK to take this patch through
the ARM SoC tree along with the code making use of it.
---
 drivers/rtc/rtc-coh901331.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c
index 93c0658..ad6863a 100644
--- a/drivers/rtc/rtc-coh901331.c
+++ b/drivers/rtc/rtc-coh901331.c
@@ -274,11 +274,17 @@ static void coh901331_shutdown(struct platform_device *pdev)
 	clk_disable_unprepare(rtap->clk);
 }
 
+static const struct of_device_id coh901331_dt_match[] = {
+	{ .compatible = "stericsson,coh901331" },
+	{},
+};
+
 static struct platform_driver coh901331_driver = {
 	.driver = {
 		.name = "rtc-coh901331",
 		.owner = THIS_MODULE,
 		.pm = &coh901331_pm_ops,
+		.of_match_table = coh901331_dt_match,
 	},
 	.remove = __exit_p(coh901331_remove),
 	.shutdown = coh901331_shutdown,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:49 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:49 +0200
Subject: [PATCH 14/39] ARM: u300: enable MMC/SD card from device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-15-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds support for the U300 MMC/SD card slot from the device
tree boot. No other changes needed.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index d1ab4e9..ae51dd1 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -193,5 +193,19 @@
 			interrupt-parent = <&vicb>;
 			interrupts = <20>;
 		};
+
+		mmcsd: mmcsd at c0001000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0xc0001000 0x1000>;
+			interrupt-parent = <&vicb>;
+			interrupts = <6 7>;
+			max-frequency = <24000000>;
+			bus-width = <4>; // SD-card slot
+			mmc-cap-mmc-highspeed;
+			mmc-cap-sd-highspeed;
+			cd-gpios = <&gpio 12 0x4>;
+			cd-inverted;
+			vmmc-supply = <&ab3100_ldo_g_reg>;
+		};
 	};
 };
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:50 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:50 +0200
Subject: [PATCH 15/39] dma: coh901318: add devicetree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-16-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds support for probing the COH 901 318 DMA controller
and channels from the device tree.

Contains portions of a sketch patch from Arnd Bergmann.

Cc: Arnd Bergmann <arnd at arndb.de>
Acked-by: Vinod Koul <vinod.koul at intel.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Folded in channel translation, request and filtering from
  the device tree based on a patch by Arnd Bergmann.
- Added device tree binding documentation.
---
 .../devicetree/bindings/dma/ste-coh901318.txt      | 32 ++++++++++++++++
 drivers/dma/coh901318.c                            | 43 ++++++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/ste-coh901318.txt

diff --git a/Documentation/devicetree/bindings/dma/ste-coh901318.txt b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
new file mode 100644
index 0000000..091ad05
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
@@ -0,0 +1,32 @@
+ST-Ericsson COH 901 318 DMA Controller
+
+This is a DMA controller which has begun as a fork of the
+ARM PL08x PrimeCell VHDL code.
+
+Required properties:
+- compatible: should be "stericsson,coh901318"
+- reg: register locations and length
+- interrupts: the single DMA IRQ
+- #dma-cells: must be set to <1>, as the channels on the
+  COH 901 318 are simple and identified by a single number
+- dma-channels: the number of DMA channels handled
+
+Example:
+
+dmac: dma-controller at c00020000 {
+	compatible = "stericsson,coh901318";
+	reg = <0xc0020000 0x1000>;
+	interrupt-parent = <&vica>;
+	interrupts = <2>;
+	#dma-cells = <1>;
+	dma-channels = <40>;
+};
+
+Consumers example:
+
+uart0: serial at c0013000 {
+	compatible = "...";
+	(...)
+	dmas = <&dmac 17 &dmac 18>;
+	dma-names = "tx", "rx";
+};
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 3b23061..9bfaddd 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -22,6 +22,7 @@
 #include <linux/uaccess.h>
 #include <linux/debugfs.h>
 #include <linux/platform_data/dma-coh901318.h>
+#include <linux/of_dma.h>
 
 #include "coh901318.h"
 #include "dmaengine.h"
@@ -1788,6 +1789,35 @@ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 }
 EXPORT_SYMBOL(coh901318_filter_id);
 
+struct coh901318_filter_args {
+	struct coh901318_base *base;
+	unsigned int ch_nr;
+};
+
+static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
+{
+	struct coh901318_filter_args *args = data;
+
+	if (&args->base->dma_slave == chan->device &&
+	    args->ch_nr == to_coh901318_chan(chan)->id)
+		return true;
+
+	return false;
+}
+
+static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
+					struct of_dma *ofdma)
+{
+	struct coh901318_filter_args args = {
+		.base = ofdma->of_dma_data,
+		.ch_nr = dma_spec->args[0],
+	};
+	dma_cap_mask_t cap;
+	dma_cap_zero(cap);
+	dma_cap_set(DMA_SLAVE, cap);
+
+	return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
+}
 /*
  * DMA channel allocation
  */
@@ -2735,12 +2765,19 @@ static int __init coh901318_probe(struct platform_device *pdev)
 	if (err)
 		goto err_register_memcpy;
 
+	err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
+					 base);
+	if (err)
+		goto err_register_of_dma;
+
 	platform_set_drvdata(pdev, base);
 	dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
 		(u32) base->virtbase);
 
 	return err;
 
+ err_register_of_dma:
+	dma_async_device_unregister(&base->dma_memcpy);
  err_register_memcpy:
 	dma_async_device_unregister(&base->dma_slave);
  err_register_slave:
@@ -2752,17 +2789,23 @@ static int coh901318_remove(struct platform_device *pdev)
 {
 	struct coh901318_base *base = platform_get_drvdata(pdev);
 
+	of_dma_controller_free(pdev->dev.of_node);
 	dma_async_device_unregister(&base->dma_memcpy);
 	dma_async_device_unregister(&base->dma_slave);
 	coh901318_pool_destroy(&base->pool);
 	return 0;
 }
 
+static const struct of_device_id coh901318_dt_match[] = {
+	{ .compatible = "stericsson,coh901318" },
+	{},
+};
 
 static struct platform_driver coh901318_driver = {
 	.remove = coh901318_remove,
 	.driver = {
 		.name	= "coh901318",
+		.of_match_table = coh901318_dt_match,
 	},
 };
 
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:54 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:54 +0200
Subject: [PATCH 19/39] ARM: u300: probe the U300 dummy-spichip from device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-20-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This probes the U300 dummy-spichip from the device tree
and adds the apropriate node to the tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts    | 5 +++++
 arch/arm/mach-u300/dummyspichip.c | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 355ac60..1b20769 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -233,6 +233,11 @@
 			num-cs = <3>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			spi-dummy at 1 {
+				compatible = "arm,pl022-dummy";
+				reg = <1>;
+				spi-max-frequency = <20000000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb6..52962bf 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -263,10 +263,16 @@ static int pl022_dummy_remove(struct spi_device *spi)
 	return 0;
 }
 
+static const struct of_device_id pl022_dummy_dt_match[] = {
+	{ .compatible = "arm,pl022-dummy" },
+	{},
+};
+
 static struct spi_driver pl022_dummy_driver = {
 	.driver = {
 		.name	= "spi-dummy",
 		.owner	= THIS_MODULE,
+		.of_match_table = pl022_dummy_dt_match,
 	},
 	.probe	= pl022_dummy_probe,
 	.remove	= pl022_dummy_remove,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:53 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:53 +0200
Subject: [PATCH 18/39] ARM: u300: add SPI PL022 to the device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-19-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This registers the PL022 PrimeCell from the U300 device
tree. We make a new copy of the platform data for the
device tree boot path, as the old platform data is in an
older file which will be going away.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Add DMA channels.
---
 arch/arm/boot/dts/ste-u300.dts | 12 ++++++++++++
 arch/arm/mach-u300/core.c      | 19 +++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 4dc9f26..355ac60 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -222,5 +222,17 @@
 			dmas = <&dmac 14>;
 			dma-names = "rx";
 		};
+
+		spi: ssp at c0006000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xc0006000 0x1000>;
+			interrupt-parent = <&vica>;
+			interrupts = <23>;
+			dmas = <&dmac 27 &dmac 28>;
+			dma-names = "tx", "rx";
+			num-cs = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 7866f54..d102cb5 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -19,6 +19,7 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
@@ -704,6 +705,22 @@ MACHINE_END
 
 #ifdef CONFIG_OF
 
+static struct pl022_ssp_controller spi_plat_data = {
+	/* If you have several SPI buses this varies, we have only bus 0 */
+	.bus_id = 0,
+	/*
+	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
+	 * chip selects for SPI. (Same on U330, U335 and U365.)
+	 * TODO: make sure the GPIO driver can select these properly
+	 * and do padmuxing accordingly too.
+	 */
+	.num_chipselect = 3,
+	.enable_dma = 1,
+	.dma_filter = coh901318_filter_id,
+	.dma_rx_param = (void *) U300_DMA_SPI_RX,
+	.dma_tx_param = (void *) U300_DMA_SPI_TX,
+};
+
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
@@ -720,6 +737,8 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
 		"uart1", &uart1_plat_data),
+	OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
+		"pl022", &spi_plat_data),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
 		"stu300.0", NULL),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:58 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:58 +0200
Subject: [PATCH 23/39] ARM: u300: remove deps from debug macro
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-24-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This rids the dependency to <mach/hardware.h> (which is an
implicit dependency to <mach/u300-regs.h>) from the U300
debug macro. Take this opportunity to update the file
header.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/include/debug/u300.S | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S
index 8ae8e4a..6f04f08 100644
--- a/arch/arm/include/debug/u300.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
 /*
- *
- * arch-arm/mach-u300/include/mach/debug-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2013 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Debugging macro include header.
  * Author: Linus Walleij <linus.walleij at stericsson.com>
  */
-#include <mach/hardware.h>
+#define U300_SLOW_PER_PHYS_BASE		0xc0010000
+#define U300_SLOW_PER_VIRT_BASE		0xff000000
 
 	.macro	addruart, rp, rv, tmp
 	/* If we move the address using MMU, use this. */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:00 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:00 +0200
Subject: [PATCH 25/39] ARM: u300: delete <mach/hardware.h>
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-26-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This file is now unused and can be deleted.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/hardware.h | 5 -----
 arch/arm/mach-u300/timer.c                 | 1 -
 2 files changed, 6 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/hardware.h

diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce..0000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/hardware.h
- */
-#include <asm/sizes.h>
-#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index f3efef0..00499d9 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -22,7 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/hardware.h>
 #include <mach/irqs.h>
 
 /* Generic stuff */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:52 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:52 +0200
Subject: [PATCH 17/39] ARM: u300: add the COH 901 318 DMAC to device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-18-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds the COH 901 318 DMA controller to the U300
device tree. All devices now converted to device tree
so far will start to find their DMA channels.

Note that the U300 is not yet using the device tree
to obtain DMA channels, but this is a first step.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 9 +++++++++
 arch/arm/mach-u300/core.c      | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 6be932b..4dc9f26 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -68,6 +68,15 @@
 		interrupts = <10>;
 	};
 
+	dmac: dma-controller at c00020000 {
+		compatible = "stericsson,coh901318";
+		reg = <0xc0020000 0x1000>;
+		interrupt-parent = <&vica>;
+		interrupts = <2>;
+		#dma-cells = <1>;
+		dma-channels = <40>;
+	};
+
 	i2c0: i2c at c0004000 {
 		compatible = "st,ddci2c";
 		reg = <0xc0004000 0x1000>;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 637034b..7866f54 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -714,6 +714,8 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"coh901327_wdog", NULL),
 	OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
 		"rtc-coh901331", NULL),
+	OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
+		"coh901318", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:55 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:55 +0200
Subject: [PATCH 20/39] ARM: u300: add FSMC flash into the device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-21-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This registers the U300 FSMC flash controller from the
device tree, and defines the three partitions. Skip the
BBT scan as in the current platform data.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 26 ++++++++++++++++++++++++++
 arch/arm/mach-u300/core.c      |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 1b20769..b8a8ddb 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -77,6 +77,32 @@
 		dma-channels = <40>;
 	};
 
+	/* A NAND flash of 128 MiB */
+	fsmc: flash at 40000000 {
+		compatible = "stericsson,fsmc-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x9f800000 0x1000>,	/* FSMC Register*/
+			<0x80000000 0x4000>,	/* NAND Base DATA */
+			<0x80020000 0x4000>,	/* NAND Base ADDR */
+			<0x80010000 0x4000>;	/* NAND Base CMD */
+		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+		nand-skip-bbtscan;
+
+		partition at 0 {
+		label = "boot records";
+			reg = <0x0 0x20000>;
+		};
+		partition at 20000 {
+			label = "free";
+			reg = <0x20000 0x7e0000>;
+		};
+		partition at 800000 {
+			label = "platform";
+			reg = <0x800000 0xf800000>;
+		};
+	};
+
 	i2c0: i2c at c0004000 {
 		compatible = "st,ddci2c";
 		reg = <0xc0004000 0x1000>;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index d102cb5..8f9e77a 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -733,6 +733,8 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 		"rtc-coh901331", NULL),
 	OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
 		"coh901318", NULL),
+	OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
+		"fsmc-nand", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
 		"uart0", &uart0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:51 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:51 +0200
Subject: [PATCH 16/39] ARM: u300: augment device tree with DMA channels
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-17-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds DMA channel assignments to the MMC/SD-controller
and the two UARTs already in the U300 device tree, as we
have now defined a way to obtain DMA channels from the
device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index ae51dd1..6be932b 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -185,6 +185,8 @@
 			reg = <0xc0013000 0x1000>;
 			interrupt-parent = <&vica>;
 			interrupts = <22>;
+			dmas = <&dmac 17 &dmac 18>;
+			dma-names = "tx", "rx";
 		};
 
 		uart1: serial at c0007000 {
@@ -192,6 +194,8 @@
 			reg = <0xc0007000 0x1000>;
 			interrupt-parent = <&vicb>;
 			interrupts = <20>;
+			dmas = <&dmac 38 &dmac 39>;
+			dma-names = "tx", "rx";
 		};
 
 		mmcsd: mmcsd at c0001000 {
@@ -206,6 +210,8 @@
 			cd-gpios = <&gpio 12 0x4>;
 			cd-inverted;
 			vmmc-supply = <&ab3100_ldo_g_reg>;
+			dmas = <&dmac 14>;
+			dma-names = "rx";
 		};
 	};
 };
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:39 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:39 +0200
Subject: [PATCH 04/39] pinctrl: coh901: add device tree support
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-5-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This makes it possible to probe the COH901 pinctrl driver from
the device tree, and assigned the device tree node in the
gpio_chip so we can look up cross-references from the device
tree. Start grabbing the per-port (bank) IRQs by index instead
of by name so we don't have to look up the IRQs by name going
forward.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Alter the driver to look up IRQ by index.
- Alter the bindings accordingly.
---
 .../devicetree/bindings/gpio/gpio-stericsson-coh901.txt      |  7 +++++++
 drivers/pinctrl/pinctrl-coh901.c                             | 12 ++++++++++--
 2 files changed, 17 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
new file mode 100644
index 0000000..fd665b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
@@ -0,0 +1,7 @@
+ST-Ericsson COH 901 571/3 GPIO controller
+
+Required properties:
+- compatible: Compatible property value should be "stericsson,gpio-coh901"
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index edde3ac..d4f8afd 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -773,8 +773,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
 		port->number = portno;
 		port->gpio = gpio;
 
-		port->irq = platform_get_irq_byname(pdev,
-						    port->name);
+		port->irq = platform_get_irq(pdev, portno);
 
 		dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
 			port->name);
@@ -811,6 +810,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
 	}
 	dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 
+#ifdef CONFIG_OF_GPIO
+	gpio->chip.of_node = pdev->dev.of_node;
+#endif
 	err = gpiochip_add(&gpio->chip);
 	if (err) {
 		dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
@@ -864,9 +866,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id u300_gpio_match[] = {
+	{ .compatible = "stericsson,gpio-coh901" },
+	{},
+};
+
 static struct platform_driver u300_gpio_driver = {
 	.driver		= {
 		.name	= "u300-gpio",
+		.of_match_table = u300_gpio_match,
 	},
 	.remove		= __exit_p(u300_gpio_remove),
 };
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:57 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:57 +0200
Subject: [PATCH 22/39] ARM: u300: move debugmacro to debug includes
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-23-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This moves the U300 debug macro to the debug headers to
make way for multiplatform support.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig.debug                                            | 8 ++++++++
 .../include/mach/debug-macro.S => include/debug/u300.S}           | 0
 2 files changed, 8 insertions(+)
 rename arch/arm/{mach-u300/include/mach/debug-macro.S => include/debug/u300.S} (100%)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908..2708ed9 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -443,6 +443,13 @@ choice
 		  Say Y here if you want the debug print routines to direct
 		  their output to the uart1 port on SiRFmarco devices.
 
+	config DEBUG_U300_UART
+		bool "Kernel low-level debugging messages via U300 UART0"
+		depends on ARCH_U300
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the uart port on U300 devices.
+
 	config DEBUG_UX500_UART
 		depends on ARCH_U8500
 		bool "Use Ux500 UART for low-level debug"
@@ -643,6 +650,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
 	default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
 	default "debug/tegra.S" if DEBUG_TEGRA_UART
+	default "debug/u300.S" if DEBUG_U300_UART
 	default "debug/ux500.S" if DEBUG_UX500_UART
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
 		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S
similarity index 100%
rename from arch/arm/mach-u300/include/mach/debug-macro.S
rename to arch/arm/include/debug/u300.S
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:56 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:56 +0200
Subject: [PATCH 21/39] ARM: u300: delete all static board data
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-22-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

We have now transferred all the U300 peripherals to the device
tree, so we just select USE_OF, and delete all static board data,
then require that this platform shall be booted using the device
tree and nothing else.

This gets rid of the MMCI (PL180), PL022, and serial PL011
platform data entries and more.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Delete MORE static data! (Platform data and static DMA channel
  assignments for PL011, PL022, PL180...
---
 arch/arm/Kconfig               |   1 +
 arch/arm/mach-u300/Makefile    |   2 -
 arch/arm/mach-u300/core.c      | 548 +----------------------------------------
 arch/arm/mach-u300/i2c.c       | 285 ---------------------
 arch/arm/mach-u300/i2c.h       |  23 --
 arch/arm/mach-u300/regulator.c |  12 +-
 arch/arm/mach-u300/spi.c       | 102 --------
 arch/arm/mach-u300/spi.h       |  26 --
 arch/arm/mach-u300/timer.c     |  38 +--
 arch/arm/mach-u300/timer.h     |   2 -
 arch/arm/mach-u300/u300-gpio.h |  70 ------
 11 files changed, 22 insertions(+), 1087 deletions(-)
 delete mode 100644 arch/arm/mach-u300/i2c.c
 delete mode 100644 arch/arm/mach-u300/i2c.h
 delete mode 100644 arch/arm/mach-u300/spi.c
 delete mode 100644 arch/arm/mach-u300/spi.h
 delete mode 100644 arch/arm/mach-u300/timer.h
 delete mode 100644 arch/arm/mach-u300/u300-gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fbad333..2689643 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -827,6 +827,7 @@ config ARCH_U300
 	select GENERIC_CLOCKEVENTS
 	select HAVE_TCM
 	select SPARSE_IRQ
+	select USE_OF
 	help
 	  Support for ST-Ericsson U300 series mobile platforms.
 
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58..0f362b6 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,5 @@ obj-m		:=
 obj-n		:=
 obj-		:=
 
-obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
-obj-$(CONFIG_I2C_STU300)          += i2c.o
 obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 8f9e77a..13d4812 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -9,50 +9,20 @@
  * Author: Linus Walleij <linus.walleij at stericsson.com>
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/termios.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/amba/serial.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
 #include <linux/platform_data/pinctrl-coh901.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/irqchip/arm-vic.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/clocksource.h>
+#include <linux/clk.h>
 
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
+#include <mach/u300-regs.h>
 #include <mach/syscon.h>
-#include <mach/irqs.h>
-
-#include "timer.h"
-#include "spi.h"
-#include "i2c.h"
-#include "u300-gpio.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -87,287 +57,6 @@ static void __init u300_map_io(void)
 }
 
 /*
- * Declaration of devices found on the U300 board and
- * their respective memory locations.
- */
-
-static struct amba_pl011_data uart0_plat_data = {
-#ifdef CONFIG_COH901318
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_UART0_RX,
-	.dma_tx_param = (void *) U300_DMA_UART0_TX,
-#endif
-};
-
-/* Slow device at 0x3000 offset */
-static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
-	{ IRQ_U300_UART0 }, &uart0_plat_data);
-
-/* The U335 have an additional UART1 on the APP CPU */
-static struct amba_pl011_data uart1_plat_data = {
-#ifdef CONFIG_COH901318
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_UART1_RX,
-	.dma_tx_param = (void *) U300_DMA_UART1_TX,
-#endif
-};
-
-/* Fast device at 0x7000 offset */
-static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
-	{ IRQ_U300_UART1 }, &uart1_plat_data);
-
-/* AHB device at 0x4000 offset */
-static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
-
-/* Fast device at 0x6000 offset */
-static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
-	{ IRQ_U300_SPI }, NULL);
-
-/* Fast device at 0x1000 offset */
-#define U300_MMCSD_IRQS	{ IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
-
-static struct mmci_platform_data mmcsd_platform_data = {
-	/*
-	 * Do not set ocr_mask or voltage translation function,
-	 * we have a regulator we can control instead.
-	 */
-	.f_max = 24000000,
-	.gpio_wp = -1,
-	.gpio_cd = U300_GPIO_PIN_MMC_CD,
-	.cd_invert = true,
-	.capabilities = MMC_CAP_MMC_HIGHSPEED |
-	MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-	/* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-
-static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
-	U300_MMCSD_IRQS, &mmcsd_platform_data);
-
-/*
- * The order of device declaration may be important, since some devices
- * have dependencies on other devices being initialized first.
- */
-static struct amba_device *amba_devs[] __initdata = {
-	&uart0_device,
-	&uart1_device,
-	&pl022_device,
-	&pl172_device,
-	&mmcsd_device,
-};
-
-/* Here follows a list of all hw resources that the platform devices
- * allocate. Note, clock dependencies are not included
- */
-
-static struct resource gpio_resources[] = {
-	{
-		.start = U300_GPIO_BASE,
-		.end   = (U300_GPIO_BASE + SZ_4K - 1),
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "gpio0",
-		.start = IRQ_U300_GPIO_PORT0,
-		.end   = IRQ_U300_GPIO_PORT0,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio1",
-		.start = IRQ_U300_GPIO_PORT1,
-		.end   = IRQ_U300_GPIO_PORT1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio2",
-		.start = IRQ_U300_GPIO_PORT2,
-		.end   = IRQ_U300_GPIO_PORT2,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio3",
-		.start = IRQ_U300_GPIO_PORT3,
-		.end   = IRQ_U300_GPIO_PORT3,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio4",
-		.start = IRQ_U300_GPIO_PORT4,
-		.end   = IRQ_U300_GPIO_PORT4,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio5",
-		.start = IRQ_U300_GPIO_PORT5,
-		.end   = IRQ_U300_GPIO_PORT5,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "gpio6",
-		.start = IRQ_U300_GPIO_PORT6,
-		.end   = IRQ_U300_GPIO_PORT6,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource keypad_resources[] = {
-	{
-		.start = U300_KEYPAD_BASE,
-		.end   = U300_KEYPAD_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "coh901461-press",
-		.start = IRQ_U300_KEYPAD_KEYBF,
-		.end   = IRQ_U300_KEYPAD_KEYBF,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.name  = "coh901461-release",
-		.start = IRQ_U300_KEYPAD_KEYBR,
-		.end   = IRQ_U300_KEYPAD_KEYBR,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource rtc_resources[] = {
-	{
-		.start = U300_RTC_BASE,
-		.end   = U300_RTC_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_RTC,
-		.end   = IRQ_U300_RTC,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-/*
- * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
- * but these are not yet used by the driver.
- */
-static struct resource fsmc_resources[] = {
-	{
-		.name  = "nand_addr",
-		.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
-		.end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "nand_cmd",
-		.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
-		.end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "nand_data",
-		.start = U300_NAND_CS0_PHYS_BASE,
-		.end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.name  = "fsmc_regs",
-		.start = U300_NAND_IF_PHYS_BASE,
-		.end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct resource i2c0_resources[] = {
-	{
-		.start = U300_I2C0_BASE,
-		.end   = U300_I2C0_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_I2C0,
-		.end   = IRQ_U300_I2C0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c1_resources[] = {
-	{
-		.start = U300_I2C1_BASE,
-		.end   = U300_I2C1_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_I2C1,
-		.end   = IRQ_U300_I2C1,
-		.flags = IORESOURCE_IRQ,
-	},
-
-};
-
-static struct resource wdog_resources[] = {
-	{
-		.start = U300_WDOG_BASE,
-		.end   = U300_WDOG_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_WDOG,
-		.end   = IRQ_U300_WDOG,
-		.flags = IORESOURCE_IRQ,
-	}
-};
-
-static struct resource dma_resource[] = {
-	{
-		.start = U300_DMAC_BASE,
-		.end = U300_DMAC_BASE + PAGE_SIZE - 1,
-		.flags =  IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_U300_DMA,
-		.end = IRQ_U300_DMA,
-		.flags =  IORESOURCE_IRQ,
-	}
-};
-
-
-static struct resource pinctrl_resources[] = {
-	{
-		.start = U300_SYSCON_BASE,
-		.end   = U300_SYSCON_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device wdog_device = {
-	.name = "coh901327_wdog",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(wdog_resources),
-	.resource = wdog_resources,
-};
-
-static struct platform_device i2c0_device = {
-	.name = "stu300",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(i2c0_resources),
-	.resource = i2c0_resources,
-};
-
-static struct platform_device i2c1_device = {
-	.name = "stu300",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(i2c1_resources),
-	.resource = i2c1_resources,
-};
-
-static struct platform_device pinctrl_device = {
-	.name = "pinctrl-u300",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(pinctrl_resources),
-	.resource = pinctrl_resources,
-};
-
-/*
  * The different variants have a few different versions of the
  * GPIO block, with different number of ports.
  */
@@ -376,75 +65,6 @@ static struct u300_gpio_platform u300_gpio_plat = {
 	.gpio_base = 0,
 };
 
-static struct platform_device gpio_device = {
-	.name = "u300-gpio",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(gpio_resources),
-	.resource = gpio_resources,
-	.dev = {
-		.platform_data = &u300_gpio_plat,
-	},
-};
-
-static struct platform_device keypad_device = {
-	.name = "keypad",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(keypad_resources),
-	.resource = keypad_resources,
-};
-
-static struct platform_device rtc_device = {
-	.name = "rtc-coh901331",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(rtc_resources),
-	.resource = rtc_resources,
-};
-
-static struct mtd_partition u300_partitions[] = {
-	{
-		.name = "bootrecords",
-		.offset = 0,
-		.size = SZ_128K,
-	},
-	{
-		.name = "free",
-		.offset = SZ_128K,
-		.size = 8064 * SZ_1K,
-	},
-	{
-		.name = "platform",
-		.offset = 8192 * SZ_1K,
-		.size = 253952 * SZ_1K,
-	},
-};
-
-static struct fsmc_nand_platform_data nand_platform_data = {
-	.partitions = u300_partitions,
-	.nr_partitions = ARRAY_SIZE(u300_partitions),
-	.options = NAND_SKIP_BBTSCAN,
-	.width = FSMC_NAND_BW8,
-};
-
-static struct platform_device nand_device = {
-	.name = "fsmc-nand",
-	.id = -1,
-	.resource = fsmc_resources,
-	.num_resources = ARRAY_SIZE(fsmc_resources),
-	.dev = {
-		.platform_data = &nand_platform_data,
-	},
-};
-
-static struct platform_device dma_device = {
-	.name		= "coh901318",
-	.id		= -1,
-	.resource	= dma_resource,
-	.num_resources  = ARRAY_SIZE(dma_resource),
-	.dev = {
-		.coherent_dma_mask = ~0,
-	},
-};
-
 static unsigned long pin_pullup_conf[] = {
 	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 };
@@ -471,61 +91,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
 				    pin_highz_conf),
 };
 
-/*
- * Notice that AMBA devices are initialized before platform devices.
- *
- */
-static struct platform_device *platform_devs[] __initdata = {
-	&dma_device,
-	&i2c0_device,
-	&i2c1_device,
-	&keypad_device,
-	&rtc_device,
-	&pinctrl_device,
-	&gpio_device,
-	&nand_device,
-	&wdog_device,
-};
-
-/*
- * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
- * together so some interrupts are connected to the first one and some
- * to the second one.
- */
-static void __init u300_init_irq(void)
-{
-	u32 mask[2] = {0, 0};
-	struct clk *clk;
-	int i;
-
-	/* initialize clocking early, we want to clock the INTCON */
-	u300_clk_init(U300_SYSCON_VBASE);
-
-	/* Bootstrap EMIF and SEMI clocks */
-	clk = clk_get_sys("pl172", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_prepare_enable(clk);
-	clk = clk_get_sys("semi", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_prepare_enable(clk);
-
-	/* Clock the interrupt controller */
-	clk = clk_get_sys("intcon", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_prepare_enable(clk);
-
-	for (i = 0; i < U300_VIC_IRQS_END; i++)
-		set_bit(i, (unsigned long *) &mask[0]);
-	vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-		 mask[0], mask[0]);
-	vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
-		 mask[1], mask[1]);
-}
-
-
-/*
- * U300 platforms peripheral handling
- */
 struct db_chip {
 	u16 chipid;
 	const char *name;
@@ -604,74 +169,6 @@ static void __init u300_init_check_chip(void)
 	}
 }
 
-/*
- * Some devices and their resources require reserved physical memory from
- * the end of the available RAM. This function traverses the list of devices
- * and assigns actual addresses to these.
- */
-static void __init u300_assign_physmem(void)
-{
-	unsigned long curr_start = __pa(high_memory);
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
-		for (j = 0; j < platform_devs[i]->num_resources; j++) {
-			struct resource *const res =
-			  &platform_devs[i]->resource[j];
-
-			if (IORESOURCE_MEM == res->flags &&
-				     0 == res->start) {
-				res->start  = curr_start;
-				res->end   += curr_start;
-				curr_start += resource_size(res);
-
-				printk(KERN_INFO "core.c: Mapping RAM " \
-				       "%#x-%#x to device %s:%s\n",
-					res->start, res->end,
-				       platform_devs[i]->name, res->name);
-			}
-		}
-	}
-}
-
-static void __init u300_init_machine(void)
-{
-	int i;
-	u16 val;
-
-	/* Check what platform we run and print some status information */
-	u300_init_check_chip();
-
-	/* Initialize SPI device with some board specifics */
-	u300_spi_init(&pl022_device);
-
-	/* Register the AMBA devices in the AMBA bus abstraction layer */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-
-	u300_assign_physmem();
-
-	/* Initialize pinmuxing */
-	pinctrl_register_mappings(u300_pinmux_map,
-				  ARRAY_SIZE(u300_pinmux_map));
-
-	/* Register subdevices on the I2C buses */
-	u300_i2c_register_board_devices();
-
-	/* Register the platform devices */
-	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-
-	/* Register subdevices on the SPI bus */
-	u300_spi_register_board_devices();
-
-	/* Enable SEMI self refresh */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
-		U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
-}
-
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
@@ -692,35 +189,6 @@ static void u300_restart(char mode, const char *cmd)
 	while (1);
 }
 
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
-	/* Maintainer: Linus Walleij <linus.walleij at stericsson.com> */
-	.atag_offset	= 0x100,
-	.map_io		= u300_map_io,
-	.nr_irqs	= 0,
-	.init_irq	= u300_init_irq,
-	.init_time	= u300_timer_init,
-	.init_machine	= u300_init_machine,
-	.restart	= u300_restart,
-MACHINE_END
-
-#ifdef CONFIG_OF
-
-static struct pl022_ssp_controller spi_plat_data = {
-	/* If you have several SPI buses this varies, we have only bus 0 */
-	.bus_id = 0,
-	/*
-	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-	 * chip selects for SPI. (Same on U330, U335 and U365.)
-	 * TODO: make sure the GPIO driver can select these properly
-	 * and do padmuxing accordingly too.
-	 */
-	.num_chipselect = 3,
-	.enable_dma = 1,
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_SPI_RX,
-	.dma_tx_param = (void *) U300_DMA_SPI_TX,
-};
-
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
@@ -736,17 +204,17 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
 		"fsmc-nand", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
-		"uart0", &uart0_plat_data),
+		"uart0", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
-		"uart1", &uart1_plat_data),
+		"uart1", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
-		"pl022", &spi_plat_data),
+		"pl022", NULL),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
 		"stu300.0", NULL),
 	OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
 		"stu300.1", NULL),
 	OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
-		"mmci", &mmcsd_platform_data),
+		"mmci", NULL),
 	{ /* sentinel */ },
 };
 
@@ -780,8 +248,6 @@ static void __init u300_init_machine_dt(void)
 	/* Check what platform we run and print some status information */
 	u300_init_check_chip();
 
-	u300_assign_physmem();
-
 	/* Initialize pinmuxing */
 	pinctrl_register_mappings(u300_pinmux_map,
 				  ARRAY_SIZE(u300_pinmux_map));
@@ -808,5 +274,3 @@ DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
 	.restart	= u300_restart,
 	.dt_compat      = u300_board_compat,
 MACHINE_END
-
-#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
deleted file mode 100644
index 96800aa..0000000
--- a/arch/arm/mach-u300/i2c.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.c
- *
- * Copyright (C) 2009-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/mfd/ab3100.h>
-#include <linux/regulator/machine.h>
-#include <linux/amba/bus.h>
-#include <mach/irqs.h>
-
-/*
- * Initial settings of ab3100 registers.
- * Common for below LDO regulator settings are that
- * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
- * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
- */
-
-/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
-#define LDO_A_SETTING		0x16
-/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_C_SETTING		0x10
-/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
-#define LDO_D_SETTING		0x10
-/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_E_SETTING		0x10
-/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
-#define LDO_E_SLEEP_SETTING	0x00
-/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_F_SETTING		0xD0
-/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_G_SETTING		0x00
-/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
-#define LDO_H_SETTING		0x18
-/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_K_SETTING		0x00
-/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
-#define LDO_EXT_SETTING		0x00
-/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
-#define BUCK_SETTING	0x7D
-/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
-#define BUCK_SLEEP_SETTING	0xAC
-
-#ifdef CONFIG_AB3100_CORE
-static struct regulator_consumer_supply supply_ldo_c[] = {
-	{
-		.dev_name = "ab3100-codec",
-		.supply = "vaudio", /* Powers the codec */
-	},
-};
-
-/*
- * This one needs to be a supply so we can turn it off
- * in order to shut down the system.
- */
-static struct regulator_consumer_supply supply_ldo_d[] = {
-	{
-		.supply = "vana15", /* Powers the SoC (CPU etc) */
-	},
-};
-
-static struct regulator_consumer_supply supply_ldo_g[] = {
-	{
-		.dev_name = "mmci",
-		.supply = "vmmc", /* Powers MMC/SD card */
-	},
-};
-
-static struct regulator_consumer_supply supply_ldo_h[] = {
-	{
-		.dev_name = "xgam_pdi",
-		.supply = "vdisp", /* Powers camera, display etc */
-	},
-};
-
-static struct regulator_consumer_supply supply_ldo_k[] = {
-	{
-		.dev_name = "irda",
-		.supply = "vir", /* Power IrDA */
-	},
-};
-
-/*
- * This is a placeholder for whoever wish to use the
- * external power.
- */
-static struct regulator_consumer_supply supply_ldo_ext[] = {
-	{
-		.supply = "vext", /* External power */
-	},
-};
-
-/* Preset (hardware defined) voltages for these regulators */
-#define LDO_A_VOLTAGE 2750000
-#define LDO_C_VOLTAGE 2650000
-#define LDO_D_VOLTAGE 2650000
-
-static struct ab3100_platform_data ab3100_plf_data = {
-	.reg_constraints = {
-		/* LDO A routing and constraints */
-		{
-			.constraints = {
-				.name = "vrad",
-				.min_uV = LDO_A_VOLTAGE,
-				.max_uV = LDO_A_VOLTAGE,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-		/* LDO C routing and constraints */
-		{
-			.constraints = {
-				.min_uV = LDO_C_VOLTAGE,
-				.max_uV = LDO_C_VOLTAGE,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
-			.consumer_supplies = supply_ldo_c,
-		},
-		/* LDO D routing and constraints */
-		{
-			.constraints = {
-				.min_uV = LDO_D_VOLTAGE,
-				.max_uV = LDO_D_VOLTAGE,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-				/*
-				 * Actually this is boot_on but we need
-				 * to reference count it externally to
-				 * be able to shut down the system.
-				 */
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
-			.consumer_supplies = supply_ldo_d,
-		},
-		/* LDO E routing and constraints */
-		{
-			.constraints = {
-				.name = "vio",
-				.min_uV = 1800000,
-				.max_uV = 1800000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-		/* LDO F routing and constraints */
-		{
-			.constraints = {
-				.name = "vana25",
-				.min_uV = 2500000,
-				.max_uV = 2500000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-		/* LDO G routing and constraints */
-		{
-			.constraints = {
-				.min_uV = 1500000,
-				.max_uV = 2850000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
-			.consumer_supplies = supply_ldo_g,
-		},
-		/* LDO H routing and constraints */
-		{
-			.constraints = {
-				.min_uV = 1200000,
-				.max_uV = 2750000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
-			.consumer_supplies = supply_ldo_h,
-		},
-		/* LDO K routing and constraints */
-		{
-			.constraints = {
-				.min_uV = 1800000,
-				.max_uV = 2750000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
-			.consumer_supplies = supply_ldo_k,
-		},
-		/* External regulator interface. No fixed voltage specified.
-		 * If we knew the voltage of the external regulator and it
-		 * was connected on the board, we could add the (fixed)
-		 * voltage for it here.
-		 */
-		{
-			.constraints = {
-				.min_uV = 0,
-				.max_uV = 0,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_STATUS,
-			},
-			.num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
-			.consumer_supplies = supply_ldo_ext,
-		},
-		/* Buck converter routing and constraints */
-		{
-			.constraints = {
-				.name = "vcore",
-				.min_uV = 1200000,
-				.max_uV = 1800000,
-				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE,
-				.always_on = 1,
-				.boot_on = 1,
-			},
-		},
-	},
-	.reg_initvals = {
-		LDO_A_SETTING,
-		LDO_C_SETTING,
-		LDO_E_SETTING,
-		LDO_E_SLEEP_SETTING,
-		LDO_F_SETTING,
-		LDO_G_SETTING,
-		LDO_H_SETTING,
-		LDO_K_SETTING,
-		LDO_EXT_SETTING,
-		BUCK_SETTING,
-		BUCK_SLEEP_SETTING,
-		LDO_D_SETTING,
-	},
-};
-#endif
-
-static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
-#ifdef CONFIG_AB3100_CORE
-	{
-		.type = "ab3100",
-		.addr = 0x48,
-		.irq = IRQ_U300_IRQ0_EXT,
-		.platform_data = &ab3100_plf_data,
-	},
-#else
-	{ },
-#endif
-};
-
-static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-	{
-		.type = "fwcam",
-		.addr = 0x10,
-	},
-	{
-		.type = "fwcam",
-		.addr = 0x5d,
-	},
-};
-
-void __init u300_i2c_register_board_devices(void)
-{
-	i2c_register_board_info(0, bus0_i2c_board_info,
-				ARRAY_SIZE(bus0_i2c_board_info));
-	/*
-	 * This makes the core shut down all unused regulators
-	 * after all the initcalls have completed.
-	 */
-	regulator_has_full_constraints();
-	i2c_register_board_info(1, bus1_i2c_board_info,
-				ARRAY_SIZE(bus1_i2c_board_info));
-}
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
deleted file mode 100644
index 485c02e..0000000
--- a/arch/arm/mach-u300/i2c.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef MACH_U300_I2C_H
-#define MACH_U300_I2C_H
-
-#ifdef CONFIG_I2C_STU300
-void __init u300_i2c_register_board_devices(void);
-#else
-/* Compile out this stuff if no I2C adapter is available */
-static inline void __init u300_i2c_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 8a67dc6..bbda954 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -58,10 +58,7 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
 	u32 val;
 
 	pr_info("U300: setting up board power\n");
-	if (pdev)
-		main_power_15 = regulator_get(&pdev->dev, "vana15");
-	else
-		main_power_15 = regulator_get(NULL, "vana15");
+	main_power_15 = regulator_get(&pdev->dev, "vana15");
 
 	if (IS_ERR(main_power_15)) {
 		pr_err("could not get vana15");
@@ -114,11 +111,8 @@ static struct platform_driver s365_board_driver = {
  */
 static int __init u300_init_boardpower(void)
 {
-	if (of_have_populated_dt())
-		return platform_driver_probe(&s365_board_driver,
-					     s365_board_probe);
-	/* Only call this on non-DT boots */
-	return __u300_init_boardpower(NULL);
+	return platform_driver_probe(&s365_board_driver,
+				     s365_board_probe);
 }
 
 device_initcall(u300_init_boardpower);
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
deleted file mode 100644
index 9106982..0000000
--- a/arch/arm/mach-u300/spi.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.c
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/spi/spi.h>
-#include <linux/amba/pl022.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/err.h>
-
-/*
- * The following is for the actual devices on the SSP/SPI bus
- */
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-static void select_dummy_chip(u32 chipselect)
-{
-	pr_debug("CORE: %s called with CS=0x%x (%s)\n",
-		 __func__,
-		 chipselect,
-		 chipselect ? "unselect chip" : "select chip");
-	/*
-	 * Here you would write the chip select value to the GPIO pins if
-	 * this was a real chip (but this is a loopback dummy).
-	 */
-}
-
-struct pl022_config_chip dummy_chip_info = {
-	/* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
-	.com_mode = DMA_TRANSFER,
-	.iface = SSP_INTERFACE_MOTOROLA_SPI,
-	/* We can only act as master but SSP_SLAVE is possible in theory */
-	.hierarchy = SSP_MASTER,
-	/* 0 = drive TX even as slave, 1 = do not drive TX as slave */
-	.slave_tx_disable = 0,
-	.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
-	.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
-	.ctrl_len = SSP_BITS_12,
-	.wait_state = SSP_MWIRE_WAIT_ZERO,
-	.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-	/*
-	 * This is where you insert a call to a function to enable CS
-	 * (usually GPIO) for a certain chip.
-	 */
-	.cs_control = select_dummy_chip,
-};
-#endif
-
-static struct spi_board_info u300_spi_devices[] = {
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-	{
-		/* A dummy chip used for loopback tests */
-		.modalias       = "spi-dummy",
-		/* Really dummy, pass in additional chip config here */
-		.platform_data  = NULL,
-		/* This defines how the controller shall handle the device */
-		.controller_data = &dummy_chip_info,
-		/* .irq - no external IRQ routed from this device */
-		.max_speed_hz   = 1000000,
-		.bus_num        = 0, /* Only one bus on this chip */
-		.chip_select    = 0,
-		/* Means SPI_CS_HIGH, change if e.g low CS */
-		.mode           = SPI_MODE_1 | SPI_LOOP,
-	},
-#endif
-};
-
-static struct pl022_ssp_controller ssp_platform_data = {
-	/* If you have several SPI buses this varies, we have only bus 0 */
-	.bus_id = 0,
-	/*
-	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-	 * chip selects for SPI. (Same on U330, U335 and U365.)
-	 * TODO: make sure the GPIO driver can select these properly
-	 * and do padmuxing accordingly too.
-	 */
-	.num_chipselect = 3,
-#ifdef CONFIG_COH901318
-	.enable_dma = 1,
-	.dma_filter = coh901318_filter_id,
-	.dma_rx_param = (void *) U300_DMA_SPI_RX,
-	.dma_tx_param = (void *) U300_DMA_SPI_TX,
-#else
-	.enable_dma = 0,
-#endif
-};
-
-
-void __init u300_spi_init(struct amba_device *adev)
-{
-	adev->dev.platform_data = &ssp_platform_data;
-}
-
-void __init u300_spi_register_board_devices(void)
-{
-	/* Register any SPI devices */
-	spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
-}
diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h
deleted file mode 100644
index bd3d867..0000000
--- a/arch/arm/mach-u300/spi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#ifndef SPI_H
-#define SPI_H
-#include <linux/amba/bus.h>
-
-#ifdef CONFIG_SPI_PL022
-void __init u300_spi_init(struct amba_device *adev);
-void __init u300_spi_register_board_devices(void);
-#else
-/* Compile out SPI support if PL022 is not selected */
-static inline void __init u300_spi_init(struct amba_device *adev)
-{
-}
-static inline void __init u300_spi_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index df1e3b5..f3efef0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -30,8 +30,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include "timer.h"
-
 /*
  * APP side special timer registers
  * This timer contains four timers which can fire an interrupt each.
@@ -361,12 +359,22 @@ static struct delay_timer u300_delay_timer;
 /*
  * This sets up the system timers, clock source and clock event.
  */
-static void __init u300_timer_setup(void __iomem *base, int irq)
+static void __init u300_timer_init_of(struct device_node *np)
 {
+	struct resource irq_res;
+	int irq;
 	struct clk *clk;
 	unsigned long rate;
 
-	u300_timer_base = base;
+	u300_timer_base = of_iomap(np, 0);
+	if (!u300_timer_base)
+		panic("could not ioremap system timer\n");
+
+	/* Get the IRQ for the GP1 timer */
+	irq = of_irq_to_resource(np, 2, &irq_res);
+	if (irq <= 0)
+		panic("no IRQ for system timer\n");
+
 	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
 
 	/* Clock the interrupt controller */
@@ -433,27 +441,5 @@ static void __init u300_timer_setup(void __iomem *base, int irq)
 	 */
 }
 
-
-void __init u300_timer_init()
-{
-	u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
-}
-
-#ifdef CONFIG_OF
-
-static void __init u300_timer_init_of(struct device_node *np)
-{
-	void __iomem *base;
-	struct resource irq_res;
-	int irq;
-
-	base = of_iomap(np, 0);
-	/* Get the IRQ for the GP1 timer */
-	irq = of_irq_to_resource(np, 2, &irq_res);
-	u300_timer_setup(base, irq);
-}
-
 CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
 		       u300_timer_init_of);
-
-#endif
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index 7766dfa..0000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1,2 +0,0 @@
-extern void u300_timer_init(void);
-
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f5077..0000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Individual pin assignments for the B335/S335.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#define U300_GPIO_PIN_UART_RX		0
-#define U300_GPIO_PIN_UART_TX		1
-#define U300_GPIO_PIN_UART_CTS		2
-#define U300_GPIO_PIN_UART_RTS		3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY	4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05		5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD		6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07		7 /* Test point TP2430 */
-
-#define U300_GPIO_PIN_GPIO08		8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09		9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10		10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET	11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD		12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY	13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14		14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15		15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16		16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE		17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18		18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19		19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20		20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21		21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22		22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23		23 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO24		24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25		25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26		26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27		27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28		28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29		29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30		30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31		31 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO32		32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33		33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34		34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35		35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36		36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37		37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38		38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39		39 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO40		40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41		41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42		42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43		43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44		44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45		45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46		46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47		47 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO48		48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49		49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50		50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51		51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52		52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53		53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54		54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55		55 /* Unrouted */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:06 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:06 +0200
Subject: [PATCH 31/39] ARM: u300: add syscon node
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-32-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds a device tree node for the U300 system controller
and remaps this dynamically instead of using hard-coded
virtual addresses. The board power set-up code is altered
to fetch a reference to the syscon using ampersand <&syscon>
notation. This way of passing a pointer to the syscon will
also be used by the clocks.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +++++++++++++++++++---
 arch/arm/boot/dts/ste-u300.dts                     |  6 +++++
 arch/arm/mach-u300/core.c                          | 22 +++++++++++++---
 arch/arm/mach-u300/regulator.c                     | 21 ++++++++++++---
 4 files changed, 69 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
index cd9001a..69b5ab0 100644
--- a/Documentation/devicetree/bindings/arm/ste-u300.txt
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -8,15 +8,39 @@ Required root node property:
 
 compatible="stericsson,u300";
 
+Required node: syscon
+This contains the system controller.
+- compatible: must be "stericsson,u300-syscon".
+- reg: the base address and size of the system controller.
+
 Boards with the U300 SoC include:
 
 S365 "Small Board U365":
 
 Required node: s365
+This contains the board-specific information.
+- compatible: must be "stericsson,s365".
+- vana15-supply: the regulator supplying the 1.5V to drive the
+  board.
+- syscon: a pointer to the syscon node so we can acccess the
+  syscon registers to set the board as self-powered.
 
 Example:
 
-s365 {
-	compatible = "stericsson,s365";
-	vana15-supply = <&ab3100_ldo_d_reg>;
+/ {
+	model = "ST-Ericsson U300";
+	compatible = "stericsson,u300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	s365 {
+		compatible = "stericsson,s365";
+		vana15-supply = <&ab3100_ldo_d_reg>;
+		syscon = <&syscon>;
+	};
+
+	syscon: syscon at c0011000 {
+		compatible = "stericsson,u300-syscon";
+		reg = <0xc0011000 0x1000>;
+	};
 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index b8a8ddb..644befd 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -27,6 +27,12 @@
 	s365 {
 		compatible = "stericsson,s365";
 		vana15-supply = <&ab3100_ldo_d_reg>;
+		syscon = <&syscon>;
+	};
+
+	syscon: syscon at c0011000 {
+		compatible = "stericsson,u300-syscon";
+		reg = <0xc0011000 0x1000>;
 	};
 
 	timer: timer at c0014000 {
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 1fdaf81..8cfca45 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -14,6 +14,7 @@
 #include <linux/platform_data/clk-u300.h>
 #include <linux/platform_data/pinctrl-coh901.h>
 #include <linux/irqchip.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/clocksource.h>
 #include <linux/clk.h>
@@ -48,6 +49,8 @@
 #define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
 #define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
 
+static void __iomem *syscon_base;
+
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
  * only things we need are the areas where we find the timer, syscon and
@@ -171,7 +174,7 @@ static void __init u300_init_check_chip(void)
 	const char unknown[] = "UNKNOWN";
 
 	/* Read out and print chip ID */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+	val = readw(syscon_base + U300_SYSCON_CIDR);
 	/* This is in funky bigendian order... */
 	val = (val & 0xFFU) << 8 | (val >> 8);
 	chip = db_chips;
@@ -244,10 +247,21 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 
 static void __init u300_init_irq_dt(void)
 {
+	struct device_node *syscon;
 	struct clk *clk;
 
+	syscon = of_find_node_by_path("/syscon at c0011000");
+	if (!syscon) {
+		pr_crit("could not find syscon node\n");
+		return;
+	}
+	syscon_base = of_iomap(syscon, 0);
+	if (!syscon_base) {
+		pr_crit("could not remap syscon\n");
+		return;
+	}
 	/* initialize clocking early, we want to clock the INTCON */
-	u300_clk_init(U300_SYSCON_VBASE);
+	u300_clk_init(syscon_base);
 
 	/* Bootstrap EMIF and SEMI clocks */
 	clk = clk_get_sys("pl172", NULL);
@@ -280,9 +294,9 @@ static void __init u300_init_machine_dt(void)
 			u300_auxdata_lookup, NULL);
 
 	/* Enable SEMI self refresh */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+	val = readw(syscon_base + U300_SYSCON_SMCR) |
 		U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+	writew(val, syscon_base + U300_SYSCON_SMCR);
 }
 
 static const char * u300_board_compat[] = {
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 1cbe88c..273fceb 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -16,8 +16,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
+#include <linux/of_address.h>
 #include <linux/io.h>
-#include "u300-regs.h"
 
 /* Power Management Control 16bit (R/W) */
 #define U300_SYSCON_PMCR					(0x50)
@@ -57,10 +57,25 @@ void u300_pm_poweroff(void)
  */
 static int __init __u300_init_boardpower(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *syscon_np;
+	static void __iomem *syscon_base;
 	int err;
 	u32 val;
 
 	pr_info("U300: setting up board power\n");
+
+	syscon_np = of_parse_phandle(np, "syscon", 0);
+	if (!syscon_np) {
+		pr_crit("U300: no syscon node\n");
+		return -ENODEV;
+	}
+	syscon_base = of_iomap(syscon_np, 0);
+	if (!syscon_base) {
+		pr_crit("U300: could not remap syscon\n");
+		return -ENODEV;
+	}
+
 	main_power_15 = regulator_get(&pdev->dev, "vana15");
 
 	if (IS_ERR(main_power_15)) {
@@ -81,9 +96,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
 	 * the rest of the U300 power management is implemented.
 	 */
 	pr_info("U300: disable system controller pull-up\n");
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+	val = readw(syscon_base + U300_SYSCON_PMCR);
 	val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+	writew(val, syscon_base + U300_SYSCON_PMCR);
 
 	/* Register globally exported PM poweroff hook */
 	pm_power_off = u300_pm_poweroff;
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:18:59 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:18:59 +0200
Subject: [PATCH 24/39] ARM: u300: push down syscon registers
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-25-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Get rid of the <mach/syscon.h> header as a prerequisite for
multiplatform support. Do this by pushing the registers down
to their respective drivers and deleting the unused remainder.

Acked-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                |  26 +-
 arch/arm/mach-u300/include/mach/syscon.h | 592 -------------------------------
 arch/arm/mach-u300/regulator.c           |   9 +-
 drivers/clk/clk-u300.c                   | 343 +++++++++++++++++-
 4 files changed, 373 insertions(+), 597 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/syscon.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 13d4812..254fe92 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -22,7 +22,31 @@
 #include <asm/mach/arch.h>
 
 #include <mach/u300-regs.h>
-#include <mach/syscon.h>
+
+/*
+ * SYSCON addresses applicable to the core machine.
+ */
+
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR					(0x400)
+/* SMCR */
+#define U300_SYSCON_SMCR					(0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK				(0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND			(0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE			(0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE		(0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR					(0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE			(0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR						(0x4f8)
+#define U300_SYSCON_PCR_SERV_IND				(0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR						(0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND		(0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND		(0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0b..0000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/syscon.h
- *
- *
- * Copyright (C) 2008-2012 ST-Ericsson AB
- *
- * Author: Rickard Andersson <rickard.andersson at stericsson.com>
- */
-
-#ifndef __MACH_SYSCON_H
-#define __MACH_SYSCON_H
-
-/*
- * All register defines for SYSCON registers that concerns individual
- * block clocks and reset lines are registered here. This is because
- * we don't want any other file to try to fool around with this stuff.
- */
-
-/* APP side SYSCON registers */
-/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
-/* CLK Control Register 16bit (R/W) */
-#define U300_SYSCON_CCR						(0x0000)
-#define U300_SYSCON_CCR_I2S1_USE_VCXO				(0x0040)
-#define U300_SYSCON_CCR_I2S0_USE_VCXO				(0x0020)
-#define U300_SYSCON_CCR_TURN_VCXO_ON				(0x0008)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK			(0x0007)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER		(0x04)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW			(0x03)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE		(0x02)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH			(0x01)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST			(0x00)
-/* CLK Status Register 16bit (R/W) */
-#define U300_SYSCON_CSR						(0x0004)
-#define U300_SYSCON_CSR_PLL208_LOCK_IND				(0x0002)
-#define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
-/* Reset lines for SLOW devices 16bit (R/W) */
-#define U300_SYSCON_RSR						(0x0014)
-#define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
-#define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
-#define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
-#define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
-#define U300_SYSCON_RSR_KEYPAD_RESET_EN				(0x0020)
-#define U300_SYSCON_RSR_GPIO_RESET_EN				(0x0010)
-#define U300_SYSCON_RSR_EH_RESET_EN				(0x0008)
-#define U300_SYSCON_RSR_BTR_RESET_EN				(0x0004)
-#define U300_SYSCON_RSR_UART_RESET_EN				(0x0002)
-#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
-/* Reset lines for FAST devices 16bit (R/W) */
-#define U300_SYSCON_RFR						(0x0018)
-#define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
-#define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
-#define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
-#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
-#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE			(0x0008)
-#define U300_SYSCON_RFR_I2C1_RESET_ENABLE			(0x0004)
-#define U300_SYSCON_RFR_I2C0_RESET_ENABLE			(0x0002)
-#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
-/* Reset lines for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_RRR						(0x001c)
-#define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
-#define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
-#define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
-#define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
-#define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
-#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN			(0x0080)
-#define U300_SYSCON_RRR_NANDIF_RESET_EN				(0x0040)
-#define U300_SYSCON_RRR_EMIF_RESET_EN				(0x0020)
-#define U300_SYSCON_RRR_DMAC_RESET_EN				(0x0010)
-#define U300_SYSCON_RRR_CPU_RESET_EN				(0x0008)
-#define U300_SYSCON_RRR_APEX_RESET_EN				(0x0004)
-#define U300_SYSCON_RRR_AHB_RESET_EN				(0x0002)
-#define U300_SYSCON_RRR_AAIF_RESET_EN				(0x0001)
-/* Clock enable for SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CESR					(0x0020)
-#define U300_SYSCON_CESR_PPM_CLK_EN				(0x0200)
-#define U300_SYSCON_CESR_ACC_TMR_CLK_EN				(0x0100)
-#define U300_SYSCON_CESR_APP_TMR_CLK_EN				(0x0080)
-#define U300_SYSCON_CESR_KEYPAD_CLK_EN				(0x0040)
-#define U300_SYSCON_CESR_GPIO_CLK_EN				(0x0010)
-#define U300_SYSCON_CESR_EH_CLK_EN				(0x0008)
-#define U300_SYSCON_CESR_BTR_CLK_EN				(0x0004)
-#define U300_SYSCON_CESR_UART_CLK_EN				(0x0002)
-#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN			(0x0001)
-/* Clock enable for FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CEFR					(0x0024)
-#define U300_SYSCON_CEFR_UART1_CLK_EN				(0x0200)
-#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN			(0x0100)
-#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN			(0x0080)
-#define U300_SYSCON_CEFR_SPI_CLK_EN				(0x0040)
-#define U300_SYSCON_CEFR_MMC_CLK_EN				(0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN				(0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN				(0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN				(0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN				(0x0002)
-#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN			(0x0001)
-/* Clock enable for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CERR					(0x0028)
-#define U300_SYSCON_CERR_CDS_CLK_EN				(0x2000)
-#define U300_SYSCON_CERR_ISP_CLK_EN				(0x1000)
-#define U300_SYSCON_CERR_MSPRO_CLK_EN				(0x0800)
-#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN		(0x0400)
-#define U300_SYSCON_CERR_SEMI_CLK_EN				(0x0200)
-#define U300_SYSCON_CERR_XGAM_CLK_EN				(0x0100)
-#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN			(0x0080)
-#define U300_SYSCON_CERR_NANDIF_CLK_EN				(0x0040)
-#define U300_SYSCON_CERR_EMIF_CLK_EN				(0x0020)
-#define U300_SYSCON_CERR_DMAC_CLK_EN				(0x0010)
-#define U300_SYSCON_CERR_CPU_CLK_EN				(0x0008)
-#define U300_SYSCON_CERR_APEX_CLK_EN				(0x0004)
-#define U300_SYSCON_CERR_AHB_CLK_EN				(0x0002)
-#define U300_SYSCON_CERR_AAIF_CLK_EN				(0x0001)
-/* Single block clock enable 16bit (-/W) */
-#define U300_SYSCON_SBCER					(0x002c)
-#define U300_SYSCON_SBCER_PPM_CLK_EN				(0x0009)
-#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN			(0x0008)
-#define U300_SYSCON_SBCER_APP_TMR_CLK_EN			(0x0007)
-#define U300_SYSCON_SBCER_KEYPAD_CLK_EN				(0x0006)
-#define U300_SYSCON_SBCER_GPIO_CLK_EN				(0x0004)
-#define U300_SYSCON_SBCER_EH_CLK_EN				(0x0003)
-#define U300_SYSCON_SBCER_BTR_CLK_EN				(0x0002)
-#define U300_SYSCON_SBCER_UART_CLK_EN				(0x0001)
-#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN			(0x0000)
-#define U300_SYSCON_SBCER_UART1_CLK_EN				(0x0019)
-#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN			(0x0018)
-#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN			(0x0017)
-#define U300_SYSCON_SBCER_SPI_CLK_EN				(0x0016)
-#define U300_SYSCON_SBCER_MMC_CLK_EN				(0x0015)
-#define U300_SYSCON_SBCER_I2S1_CLK_EN				(0x0014)
-#define U300_SYSCON_SBCER_I2S0_CLK_EN				(0x0013)
-#define U300_SYSCON_SBCER_I2C1_CLK_EN				(0x0012)
-#define U300_SYSCON_SBCER_I2C0_CLK_EN				(0x0011)
-#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN			(0x0010)
-#define U300_SYSCON_SBCER_CDS_CLK_EN				(0x002D)
-#define U300_SYSCON_SBCER_ISP_CLK_EN				(0x002C)
-#define U300_SYSCON_SBCER_MSPRO_CLK_EN				(0x002B)
-#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN		(0x002A)
-#define U300_SYSCON_SBCER_SEMI_CLK_EN				(0x0029)
-#define U300_SYSCON_SBCER_XGAM_CLK_EN				(0x0028)
-#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN			(0x0027)
-#define U300_SYSCON_SBCER_NANDIF_CLK_EN				(0x0026)
-#define U300_SYSCON_SBCER_EMIF_CLK_EN				(0x0025)
-#define U300_SYSCON_SBCER_DMAC_CLK_EN				(0x0024)
-#define U300_SYSCON_SBCER_CPU_CLK_EN				(0x0023)
-#define U300_SYSCON_SBCER_APEX_CLK_EN				(0x0022)
-#define U300_SYSCON_SBCER_AHB_CLK_EN				(0x0021)
-#define U300_SYSCON_SBCER_AAIF_CLK_EN				(0x0020)
-/* Single block clock disable 16bit (-/W) */
-#define U300_SYSCON_SBCDR					(0x0030)
-/* Same values as above for SBCER */
-/* Clock force SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CFSR					(0x003c)
-#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN			(0x0200)
-#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN			(0x0100)
-#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN			(0x0080)
-#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN			(0x0020)
-#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN			(0x0010)
-#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN			(0x0008)
-#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN			(0x0004)
-#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN			(0x0002)
-#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN		(0x0001)
-/* Clock force FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CFFR					(0x40)
-/* Values not defined. Define if you want to use them. */
-/* Clock force the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CFRR					(0x44)
-#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN			(0x2000)
-#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN			(0x1000)
-#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN			(0x0800)
-#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN		(0x0400)
-#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN			(0x0200)
-#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN			(0x0100)
-#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN			(0x0080)
-#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN			(0x0040)
-#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN			(0x0020)
-#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN			(0x0010)
-#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN			(0x0008)
-#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN			(0x0004)
-#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN			(0x0002)
-#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN			(0x0001)
-/* PLL208 Frequency Control 16bit (R/W) */
-#define U300_SYSCON_PFCR					(0x48)
-#define U300_SYSCON_PFCR_DPLL_MULT_NUM				(0x000F)
-/* Power Management Control 16bit (R/W) */
-#define U300_SYSCON_PMCR					(0x50)
-#define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
-#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
-/*
- * All other clocking registers moved to clock.c!
- */
-/* Reset Out 16bit (R/W) */
-#define U300_SYSCON_RCR						(0x6c)
-#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE			(0x0001)
-/* EMIF Slew Rate Control 16bit (R/W) */
-#define U300_SYSCON_SRCLR					(0x70)
-#define U300_SYSCON_SRCLR_MASK					(0x03FF)
-#define U300_SYSCON_SRCLR_VALUE					(0x03FF)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B			(0x0200)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A			(0x0100)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B			(0x0080)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A			(0x0040)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B			(0x0020)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A			(0x0010)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B			(0x0008)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A			(0x0004)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B			(0x0002)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A			(0x0001)
-/* EMIF Clock Control Register 16bit (R/W) */
-#define U300_SYSCON_ECCR					(0x0078)
-#define U300_SYSCON_ECCR_MASK					(0x000F)
-#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE		(0x0008)
-#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE	(0x0004)
-#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE		(0x0002)
-#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE		(0x0001)
-/* Step one for killing the applications system 16bit (-/W) */
-#define U300_SYSCON_KA1R					(0x0080)
-#define U300_SYSCON_KA1R_MASK					(0xFFFF)
-#define U300_SYSCON_KA1R_VALUE					(0xFFFF)
-/* Step two for killing the application system 16bit (-/W) */
-#define U300_SYSCON_KA2R					(0x0084)
-#define U300_SYSCON_KA2R_MASK					(0xFFFF)
-#define U300_SYSCON_KA2R_VALUE					(0xFFFF)
-/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
-#define U300_SYSCON_MMF0R					(0x90)
-#define U300_SYSCON_MMF0R_MASK					(0x00FF)
-#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK			(0x00F0)
-#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK			(0x000F)
-/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
-#define U300_SYSCON_MMF1R					(0x94)
-#define U300_SYSCON_MMF1R_MASK					(0x00FF)
-#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK			(0x00F0)
-#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK			(0x000F)
-/* AAIF control register 16 bit (R/W) */
-#define U300_SYSCON_AAIFCR					(0x98)
-#define U300_SYSCON_AAIFCR_MASK					(0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK			(0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL			(0x0000)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING			(0x0001)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT			(0x0002)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT			(0x0003)
-/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
-#define U300_SYSCON_MMCR					(0x9C)
-#define U300_SYSCON_MMCR_MASK					(0x0003)
-#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE			(0x0002)
-#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE			(0x0001)
-/* Pull up/down control (R/W) */
-#define U300_SYSCON_PUCR					(0x104)
-#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE		(0x0200)
-#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE		(0x0100)
-#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE			(0x0080)
-#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE			(0x0040)
-#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK			(0x003F)
-/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
-#define U300_SYSCON_S0CCR					(0x120)
-#define U300_SYSCON_S0CCR_FIELD_MASK				(0x43FF)
-#define U300_SYSCON_S0CCR_CLOCK_REQ				(0x4000)
-#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR			(0x2000)
-#define U300_SYSCON_S0CCR_CLOCK_INV				(0x0200)
-#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK			(0x01E0)
-#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK			(0x001E)
-#define U300_SYSCON_S0CCR_CLOCK_ENABLE				(0x0001)
-#define U300_SYSCON_S0CCR_SEL_MCLK				(0x8<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK			(0xA<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK			(0xC<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK			(0xD<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK			(0x0<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK			(0x2<<1)
-#define U300_SYSCON_S0CCR_SEL_RTC_CLK				(0x4<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK			(0x6<<1)
-/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
-#define U300_SYSCON_S1CCR					(0x124)
-#define U300_SYSCON_S1CCR_FIELD_MASK				(0x43FF)
-#define U300_SYSCON_S1CCR_CLOCK_REQ				(0x4000)
-#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR			(0x2000)
-#define U300_SYSCON_S1CCR_CLOCK_INV				(0x0200)
-#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK			(0x01E0)
-#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK			(0x001E)
-#define U300_SYSCON_S1CCR_CLOCK_ENABLE				(0x0001)
-#define U300_SYSCON_S1CCR_SEL_MCLK				(0x8<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK			(0xA<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK			(0xC<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK			(0xD<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK			(0x2<<1)
-#define U300_SYSCON_S1CCR_SEL_RTC_CLK				(0x4<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK			(0x6<<1)
-/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
-#define U300_SYSCON_S2CCR					(0x128)
-#define U300_SYSCON_S2CCR_FIELD_MASK				(0xC3FF)
-#define U300_SYSCON_S2CCR_CLK_STEAL				(0x8000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ				(0x4000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR			(0x2000)
-#define U300_SYSCON_S2CCR_CLOCK_INV				(0x0200)
-#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK			(0x01E0)
-#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK			(0x001E)
-#define U300_SYSCON_S2CCR_CLOCK_ENABLE				(0x0001)
-#define U300_SYSCON_S2CCR_SEL_MCLK				(0x8<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK			(0xA<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK			(0xC<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK			(0xD<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK			(0x2<<1)
-#define U300_SYSCON_S2CCR_SEL_RTC_CLK				(0x4<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK			(0x6<<1)
-/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
-#define U300_SYSCON_MCR						(0x12c)
-#define U300_SYSCON_MCR_FIELD_MASK				(0x00FF)
-#define U300_SYSCON_MCR_PMGEN_CR_4_MASK				(0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO				(0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_4_SPI				(0x0040)
-#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF				(0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_2_MASK				(0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO				(0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC		(0x0010)
-#define U300_SYSCON_MCR_PMGEN_CR_2_DSP				(0x0020)
-#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF				(0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_0_MASK				(0x000C)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1		(0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2		(0x0004)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3		(0x0008)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM			(0x000C)
-#define U300_SYSCON_MCR_PM1G_MODE_ENABLE			(0x0002)
-#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE			(0x0001)
-/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
-#define U300_SYSCON_PICR					(0x0130)
-#define U300_SYSCON_PICR_MASK					(0x00FF)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE		(0x0080)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE		(0x0040)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE		(0x0020)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE		(0x0010)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE		(0x0008)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE		(0x0004)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE		(0x0002)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE		(0x0001)
-/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
-#define U300_SYSCON_PISR					(0x0134)
-#define U300_SYSCON_PISR_MASK					(0x000F)
-#define U300_SYSCON_PISR_PLL13_UNLOCK_IND			(0x0008)
-#define U300_SYSCON_PISR_PLL13_LOCK_IND				(0x0004)
-#define U300_SYSCON_PISR_PLL208_UNLOCK_IND			(0x0002)
-#define U300_SYSCON_PISR_PLL208_LOCK_IND			(0x0001)
-/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
-#define U300_SYSCON_PICLR					(0x0138)
-#define U300_SYSCON_PICLR_MASK					(0x000F)
-#define U300_SYSCON_PICLR_RWMASK				(0x0000)
-#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC			(0x0008)
-#define U300_SYSCON_PICLR_PLL13_LOCK_SC				(0x0004)
-#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC			(0x0002)
-#define U300_SYSCON_PICLR_PLL208_LOCK_SC			(0x0001)
-/* CAMIF_CONTROL 16 bit (-/W) */
-#define U300_SYSCON_CICR					(0x013C)
-#define U300_SYSCON_CICR_MASK					(0x0FFF)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK		(0x0F00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1		(0x0C00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0		(0x0300)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK		(0x00F0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1		(0x00C0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0		(0x0030)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK		(0x000F)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1		(0x000C)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0		(0x0003)
-/* Clock activity observability register 0 */
-#define U300_SYSCON_C0OAR					(0x140)
-#define U300_SYSCON_C0OAR_MASK					(0xFFFF)
-#define U300_SYSCON_C0OAR_VALUE					(0xFFFF)
-#define U300_SYSCON_C0OAR_BT_H_CLK				(0x8000)
-#define U300_SYSCON_C0OAR_ASPB_P_CLK				(0x4000)
-#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK			(0x2000)
-#define U300_SYSCON_C0OAR_APP_SEMI_CLK				(0x1000)
-#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK			(0x0800)
-#define U300_SYSCON_C0OAR_APP_I2S1_CLK				(0x0400)
-#define U300_SYSCON_C0OAR_APP_I2S0_CLK				(0x0200)
-#define U300_SYSCON_C0OAR_APP_CPU_CLK				(0x0100)
-#define U300_SYSCON_C0OAR_APP_52_CLK				(0x0080)
-#define U300_SYSCON_C0OAR_APP_208_CLK				(0x0040)
-#define U300_SYSCON_C0OAR_APP_104_CLK				(0x0020)
-#define U300_SYSCON_C0OAR_APEX_CLK				(0x0010)
-#define U300_SYSCON_C0OAR_AHPB_M_H_CLK				(0x0008)
-#define U300_SYSCON_C0OAR_AHB_CLK				(0x0004)
-#define U300_SYSCON_C0OAR_AFPB_P_CLK				(0x0002)
-#define U300_SYSCON_C0OAR_AAIF_CLK				(0x0001)
-/* Clock activity observability register 1 */
-#define U300_SYSCON_C1OAR					(0x144)
-#define U300_SYSCON_C1OAR_MASK					(0x3FFE)
-#define U300_SYSCON_C1OAR_VALUE					(0x3FFE)
-#define U300_SYSCON_C1OAR_NFIF_F_CLK				(0x2000)
-#define U300_SYSCON_C1OAR_MSPRO_CLK				(0x1000)
-#define U300_SYSCON_C1OAR_MMC_P_CLK				(0x0800)
-#define U300_SYSCON_C1OAR_MMC_CLK				(0x0400)
-#define U300_SYSCON_C1OAR_KP_P_CLK				(0x0200)
-#define U300_SYSCON_C1OAR_I2C1_P_CLK				(0x0100)
-#define U300_SYSCON_C1OAR_I2C0_P_CLK				(0x0080)
-#define U300_SYSCON_C1OAR_GPIO_CLK				(0x0040)
-#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK				(0x0020)
-#define U300_SYSCON_C1OAR_EMIF_H_CLK				(0x0010)
-#define U300_SYSCON_C1OAR_EVHIST_CLK				(0x0008)
-#define U300_SYSCON_C1OAR_PPM_CLK				(0x0004)
-#define U300_SYSCON_C1OAR_DMA_CLK				(0x0002)
-/* Clock activity observability register 2 */
-#define U300_SYSCON_C2OAR					(0x148)
-#define U300_SYSCON_C2OAR_MASK					(0x0FFF)
-#define U300_SYSCON_C2OAR_VALUE					(0x0FFF)
-#define U300_SYSCON_C2OAR_XGAM_CDI_CLK				(0x0800)
-#define U300_SYSCON_C2OAR_XGAM_CLK				(0x0400)
-#define U300_SYSCON_C2OAR_VC_H_CLK				(0x0200)
-#define U300_SYSCON_C2OAR_VC_CLK				(0x0100)
-#define U300_SYSCON_C2OAR_UA_P_CLK				(0x0080)
-#define U300_SYSCON_C2OAR_TMR1_CLK				(0x0040)
-#define U300_SYSCON_C2OAR_TMR0_CLK				(0x0020)
-#define U300_SYSCON_C2OAR_SPI_P_CLK				(0x0010)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK			(0x0008)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CLK				(0x0004)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK			(0x0002)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CLK				(0x0001)
-
-/* Chip ID register 16bit (R/-) */
-#define U300_SYSCON_CIDR					(0x400)
-/* Video IRQ clear 16bit (R/W) */
-#define U300_SYSCON_VICR					(0x404)
-#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE		(0x0002)
-#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE		(0x0001)
-/* SMCR */
-#define U300_SYSCON_SMCR					(0x4d0)
-#define U300_SYSCON_SMCR_FIELD_MASK				(0x000e)
-#define U300_SYSCON_SMCR_SEMI_SREFACK_IND			(0x0008)
-#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE			(0x0004)
-#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE		(0x0002)
-/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
-#define U300_SYSCON_CSDR					(0x4f0)
-#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE			(0x0001)
-/* PRINT_CONTROL Print Control 16bit (R/-) */
-#define U300_SYSCON_PCR						(0x4f8)
-#define U300_SYSCON_PCR_SERV_IND				(0x0001)
-/* BOOT_CONTROL 16bit (R/-) */
-#define U300_SYSCON_BCR						(0x4fc)
-#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND		(0x0400)
-#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND		(0x0200)
-#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
-#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
-
-
-/* CPU clock defines */
-/**
- * CPU high frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_HIGH    208
-/**
- * CPU medium frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_MEDIUM   52
-/**
- * CPU low frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_LOW      13
-
-/* EMIF clock defines */
-/**
- * EMIF high frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_HIGH   104
-/**
- * EMIF medium frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_MEDIUM  52
-/**
- * EMIF low frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_LOW     13
-
-/* AHB clock defines */
-/**
- * AHB high frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_HIGH     52
-/**
- * AHB medium frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_MEDIUM   26
-/**
- * AHB low frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_LOW       7  /* i.e 13/2=6.5MHz */
-
-enum syscon_busmaster {
-  SYSCON_BM_DMAC,
-  SYSCON_BM_XGAM,
-  SYSCON_BM_VIDEO_ENC
-};
-
-/* Selectr a resistor or a set of resistors */
-enum syscon_pull_up_down {
-  SYSCON_PU_KEY_IN_EN,
-  SYSCON_PU_EMIF_1_8_BIT_EN,
-  SYSCON_PU_EMIF_1_16_BIT_EN,
-  SYSCON_PU_EMIF_1_NFIF_READY_EN,
-  SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
-};
-
-/*
- * Note that this array must match the order of the array "clk_reg"
- * in syscon.c
- */
-enum syscon_clk {
-  SYSCON_CLKCONTROL_SLOW_BRIDGE,
-  SYSCON_CLKCONTROL_UART,
-  SYSCON_CLKCONTROL_BTR,
-  SYSCON_CLKCONTROL_EH,
-  SYSCON_CLKCONTROL_GPIO,
-  SYSCON_CLKCONTROL_KEYPAD,
-  SYSCON_CLKCONTROL_APP_TIMER,
-  SYSCON_CLKCONTROL_ACC_TIMER,
-  SYSCON_CLKCONTROL_FAST_BRIDGE,
-  SYSCON_CLKCONTROL_I2C0,
-  SYSCON_CLKCONTROL_I2C1,
-  SYSCON_CLKCONTROL_I2S0,
-  SYSCON_CLKCONTROL_I2S1,
-  SYSCON_CLKCONTROL_MMC,
-  SYSCON_CLKCONTROL_SPI,
-  SYSCON_CLKCONTROL_I2S0_CORE,
-  SYSCON_CLKCONTROL_I2S1_CORE,
-  SYSCON_CLKCONTROL_UART1,
-  SYSCON_CLKCONTROL_AAIF,
-  SYSCON_CLKCONTROL_AHB,
-  SYSCON_CLKCONTROL_APEX,
-  SYSCON_CLKCONTROL_CPU,
-  SYSCON_CLKCONTROL_DMA,
-  SYSCON_CLKCONTROL_EMIF,
-  SYSCON_CLKCONTROL_NAND_IF,
-  SYSCON_CLKCONTROL_VIDEO_ENC,
-  SYSCON_CLKCONTROL_XGAM,
-  SYSCON_CLKCONTROL_SEMI,
-  SYSCON_CLKCONTROL_AHB_SUBSYS,
-  SYSCON_CLKCONTROL_MSPRO
-};
-
-enum syscon_sysclk_mode {
-  SYSCON_SYSCLK_DISABLED,
-  SYSCON_SYSCLK_M_CLK,
-  SYSCON_SYSCLK_ACC_FSM,
-  SYSCON_SYSCLK_PLL60_48,
-  SYSCON_SYSCLK_PLL60_60,
-  SYSCON_SYSCLK_ACC_PLL208,
-  SYSCON_SYSCLK_APP_PLL13,
-  SYSCON_SYSCLK_APP_FSM,
-  SYSCON_SYSCLK_RTC,
-  SYSCON_SYSCLK_APP_PLL208
-};
-
-enum syscon_sysclk_req {
-  SYSCON_SYSCLKREQ_DISABLED,
-  SYSCON_SYSCLKREQ_ACTIVE_LOW,
-  SYSCON_SYSCLKREQ_MONITOR
-};
-
-enum syscon_clk_mode {
-  SYSCON_CLKMODE_OFF,
-  SYSCON_CLKMODE_DEFAULT,
-  SYSCON_CLKMODE_LOW,
-  SYSCON_CLKMODE_MEDIUM,
-  SYSCON_CLKMODE_HIGH,
-  SYSCON_CLKMODE_PERMANENT,
-  SYSCON_CLKMODE_ON,
-};
-
-enum syscon_call_mode {
-  SYSCON_CLKCALL_NOWAIT,
-  SYSCON_CLKCALL_WAIT,
-};
-
-int syscon_dc_on(bool keep_power_on);
-int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
-				      bool active);
-bool syscon_get_busmaster_active_state(void);
-int syscon_set_sleep_mask(enum syscon_clk,
-			  bool sleep_ctrl);
-int syscon_config_sysclk(u32 sysclk,
-			 enum syscon_sysclk_mode sysclkmode,
-			 bool inverse,
-			 u32 divisor,
-			 enum syscon_sysclk_req sysclkreq);
-bool syscon_can_turn_off_semi_clock(void);
-
-/* This function is restricted to core.c */
-int syscon_request_normal_power(bool req);
-
-/* This function is restricted to be used by platform_speed.c */
-int syscon_speed_request(enum syscon_call_mode wait_mode,
-			 enum syscon_clk_mode req_clk_mode);
-#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index bbda954..ab7d7a5 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,9 +17,12 @@
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
 #include <linux/io.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/syscon.h>
+#include <mach/u300-regs.h>
+
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR					(0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
 
 /*
  * Regulators that power the board and chip and which are
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f792..a41e42e 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,348 @@
 #include <linux/io.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
-#include <mach/syscon.h>
+
+/* APP side SYSCON registers */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR						(0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO				(0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO				(0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON				(0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK			(0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER		(0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW			(0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE		(0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH			(0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST			(0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR						(0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND				(0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR						(0x0014)
+#define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN				(0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN				(0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN				(0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN				(0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN				(0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR						(0x0018)
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE			(0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE			(0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE			(0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR						(0x001c)
+#define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
+#define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN			(0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN				(0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN				(0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN				(0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN				(0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN				(0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN				(0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN				(0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR					(0x0020)
+#define U300_SYSCON_CESR_PPM_CLK_EN				(0x0200)
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN				(0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN				(0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN				(0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN				(0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN				(0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN				(0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN				(0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN			(0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR					(0x0024)
+#define U300_SYSCON_CEFR_UART1_CLK_EN				(0x0200)
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN			(0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN			(0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN				(0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN				(0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN				(0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN				(0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN				(0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN				(0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN			(0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR					(0x0028)
+#define U300_SYSCON_CERR_CDS_CLK_EN				(0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN				(0x1000)
+#define U300_SYSCON_CERR_MSPRO_CLK_EN				(0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN		(0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN				(0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN				(0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN			(0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN				(0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN				(0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN				(0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN				(0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN				(0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN				(0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN				(0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER					(0x002c)
+#define U300_SYSCON_SBCER_PPM_CLK_EN				(0x0009)
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN			(0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN			(0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN				(0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN				(0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN				(0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN				(0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN				(0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN			(0x0000)
+#define U300_SYSCON_SBCER_UART1_CLK_EN				(0x0019)
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN			(0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN			(0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN				(0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN				(0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN				(0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN				(0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN				(0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN				(0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN			(0x0010)
+#define U300_SYSCON_SBCER_CDS_CLK_EN				(0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN				(0x002C)
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN				(0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN		(0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN				(0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN				(0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN			(0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN				(0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN				(0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN				(0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN				(0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN				(0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN				(0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN				(0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR					(0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR					(0x003c)
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN			(0x0200)
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN			(0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN			(0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN			(0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN			(0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN			(0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN			(0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN			(0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN		(0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR					(0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR					(0x44)
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN			(0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN			(0x1000)
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN			(0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN		(0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN			(0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN			(0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN			(0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN			(0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN			(0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN			(0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN			(0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN			(0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN			(0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN			(0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR					(0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM				(0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR					(0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR						(0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE			(0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR					(0x70)
+#define U300_SYSCON_SRCLR_MASK					(0x03FF)
+#define U300_SYSCON_SRCLR_VALUE					(0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B			(0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A			(0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B			(0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A			(0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B			(0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A			(0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B			(0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A			(0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B			(0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A			(0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR					(0x0078)
+#define U300_SYSCON_ECCR_MASK					(0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE		(0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE	(0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE		(0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE		(0x0001)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R					(0x90)
+#define U300_SYSCON_MMF0R_MASK					(0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK			(0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK			(0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R					(0x94)
+#define U300_SYSCON_MMF1R_MASK					(0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK			(0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK			(0x000F)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR					(0x9C)
+#define U300_SYSCON_MMCR_MASK					(0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE			(0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE			(0x0001)
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR					(0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK				(0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ				(0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR			(0x2000)
+#define U300_SYSCON_S0CCR_CLOCK_INV				(0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK			(0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK			(0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE				(0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK				(0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK			(0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK			(0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK			(0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK			(0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK			(0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK				(0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK			(0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR					(0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK				(0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ				(0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR			(0x2000)
+#define U300_SYSCON_S1CCR_CLOCK_INV				(0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK			(0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK			(0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE				(0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK				(0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK			(0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK			(0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK			(0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK			(0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK				(0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK			(0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR					(0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK				(0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL				(0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ				(0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR			(0x2000)
+#define U300_SYSCON_S2CCR_CLOCK_INV				(0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK			(0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK			(0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE				(0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK				(0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK			(0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK			(0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK			(0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK			(0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK			(0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK			(0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK				(0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK			(0x6<<1)
+/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
+#define U300_SYSCON_PICR					(0x0130)
+#define U300_SYSCON_PICR_MASK					(0x00FF)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE		(0x0080)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE		(0x0040)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE		(0x0020)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE		(0x0010)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE		(0x0008)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE		(0x0004)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE		(0x0002)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE		(0x0001)
+/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
+#define U300_SYSCON_PISR					(0x0134)
+#define U300_SYSCON_PISR_MASK					(0x000F)
+#define U300_SYSCON_PISR_PLL13_UNLOCK_IND			(0x0008)
+#define U300_SYSCON_PISR_PLL13_LOCK_IND				(0x0004)
+#define U300_SYSCON_PISR_PLL208_UNLOCK_IND			(0x0002)
+#define U300_SYSCON_PISR_PLL208_LOCK_IND			(0x0001)
+/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
+#define U300_SYSCON_PICLR					(0x0138)
+#define U300_SYSCON_PICLR_MASK					(0x000F)
+#define U300_SYSCON_PICLR_RWMASK				(0x0000)
+#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC			(0x0008)
+#define U300_SYSCON_PICLR_PLL13_LOCK_SC				(0x0004)
+#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC			(0x0002)
+#define U300_SYSCON_PICLR_PLL208_LOCK_SC			(0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR					(0x140)
+#define U300_SYSCON_C0OAR_MASK					(0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE					(0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK				(0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK				(0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK			(0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK				(0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK			(0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK				(0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK				(0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK				(0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK				(0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK				(0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK				(0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK				(0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK				(0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK				(0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK				(0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK				(0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR					(0x144)
+#define U300_SYSCON_C1OAR_MASK					(0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE					(0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK				(0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK				(0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK				(0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK				(0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK				(0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK				(0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK				(0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK				(0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK				(0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK				(0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK				(0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK				(0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK				(0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR					(0x148)
+#define U300_SYSCON_C2OAR_MASK					(0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE					(0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK				(0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK				(0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK				(0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK				(0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK				(0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK				(0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK				(0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK				(0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK			(0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK				(0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK			(0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK				(0x0001)
+
 
 /*
  * The clocking hierarchy currently looks like this.
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:03 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:03 +0200
Subject: [PATCH 28/39] ARM: u300: convert to multiplatform
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-29-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Now that we removed our dependency on <mach/*> the U300
can be converted to mutliplatform. Remove the invalid restriction
that U300 would not support AUTO_ZRELADDR (it does) and update
the defconfig in the process.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig                | 21 +--------------------
 arch/arm/configs/u300_defconfig | 11 ++++-------
 arch/arm/mach-u300/Kconfig      | 31 +++++++++++++++++++++++++------
 3 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2689643..b6f9ce6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -812,25 +812,6 @@ config ARCH_SHARK
 	  Support for the StrongARM based Digital DNARD machine, also known
 	  as "Shark" (<http://www.shark-linux.de/shark.html>).
 
-config ARCH_U300
-	bool "ST-Ericsson U300 Series"
-	depends on MMU
-	select ARCH_REQUIRE_GPIOLIB
-	select ARM_AMBA
-	select ARM_PATCH_PHYS_VIRT
-	select ARM_VIC
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select CLKSRC_OF
-	select COMMON_CLK
-	select CPU_ARM926T
-	select GENERIC_CLOCKEVENTS
-	select HAVE_TCM
-	select SPARSE_IRQ
-	select USE_OF
-	help
-	  Support for ST-Ericsson U300 series mobile platforms.
-
 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select ARCH_HAS_HOLES_MEMORYMODEL
@@ -2041,7 +2022,7 @@ config CRASH_DUMP
 
 config AUTO_ZRELADDR
 	bool "Auto calculation of the decompressed kernel image address"
-	depends on !ZBOOT_ROM && !ARCH_U300
+	depends on !ZBOOT_ROM
 	help
 	  ZRELADDR is the physical address where the decompressed kernel
 	  image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000e..a5fa0d9 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 # CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_U300=y
-CONFIG_MACH_U300=y
-CONFIG_MACH_U300_BS335=y
 CONFIG_MACH_U300_SPIDUMMY=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,11 +42,11 @@ CONFIG_I2C=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_CLKGATE=y
@@ -70,4 +68,3 @@ CONFIG_DEBUG_FS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f59764..e2f350f 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,45 @@
-if ARCH_U300
-
 menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
-config MACH_U300
-	bool "U300"
+config ARCH_U300
+	bool "ST-Ericsson U300 Series"
+	depends on MMU
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_VIC
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select CLKSRC_OF
+	select COMMON_CLK
+	select CPU_ARM926T
+	select GENERIC_CLOCKEVENTS
+	select HAVE_TCM
 	select PINCTRL
 	select PINCTRL_COH901
 	select PINCTRL_U300
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  Support for ST-Ericsson U300 series mobile platforms.
 
 comment "ST-Ericsson U300/U335 Feature Selections"
 
+config MACH_U300
+	depends on ARCH_U300
+	bool "U300"
+	default y
+
 config U300_DEBUG
+	depends on ARCH_U300
 	bool "Debug support for U300"
 	depends on PM
 	help
 		Debug support for U300 in sysfs, procfs etc.
 
 config MACH_U300_SPIDUMMY
+	depends on ARCH_U300
 	bool "SSP/SPI dummy chip"
 	select SPI
 	select SPI_MASTER
@@ -31,5 +52,3 @@ config MACH_U300_SPIDUMMY
 		SPI framework and ARM PL022 support.
 
 endmenu
-
-endif
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:01 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:01 +0200
Subject: [PATCH 26/39] ARM: u300: delete <mach/irqs.h>
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-27-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

All IRQs are now obtained from the device tree, and this file
is unused, so delete it.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/irqs.h | 80 ----------------------------------
 arch/arm/mach-u300/timer.c             |  2 -
 2 files changed, 82 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/irqs.h

diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76..0000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/irqs.h
- *
- *
- * Copyright (C) 2006-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * IRQ channel definitions for the U300 platforms.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_U300_INTCON0_START		32
-#define IRQ_U300_INTCON1_START		64
-/* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT		32
-#define IRQ_U300_IRQ1_EXT		33
-#define IRQ_U300_DMA			34
-#define IRQ_U300_VIDEO_ENC_0		35
-#define IRQ_U300_VIDEO_ENC_1		36
-#define IRQ_U300_AAIF_RX		37
-#define IRQ_U300_AAIF_TX		38
-#define IRQ_U300_AAIF_VGPIO		39
-#define IRQ_U300_AAIF_WAKEUP		40
-#define IRQ_U300_PCM_I2S0_FRAME		41
-#define IRQ_U300_PCM_I2S0_FIFO		42
-#define IRQ_U300_PCM_I2S1_FRAME		43
-#define IRQ_U300_PCM_I2S1_FIFO		44
-#define IRQ_U300_XGAM_GAMCON		45
-#define IRQ_U300_XGAM_CDI		46
-#define IRQ_U300_XGAM_CDICON		47
-#define IRQ_U300_XGAM_PDI		49
-#define IRQ_U300_XGAM_PDICON		50
-#define IRQ_U300_XGAM_GAMEACC		51
-#define IRQ_U300_XGAM_MCIDCT		52
-#define IRQ_U300_APEX			53
-#define IRQ_U300_UART0			54
-#define IRQ_U300_SPI			55
-#define IRQ_U300_TIMER_APP_OS		56
-#define IRQ_U300_TIMER_APP_DD		57
-#define IRQ_U300_TIMER_APP_GP1		58
-#define IRQ_U300_TIMER_APP_GP2		59
-#define IRQ_U300_TIMER_OS		60
-#define IRQ_U300_TIMER_MS		61
-#define IRQ_U300_KEYPAD_KEYBF		62
-#define IRQ_U300_KEYPAD_KEYBR		63
-/* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0		64
-#define IRQ_U300_GPIO_PORT1		65
-#define IRQ_U300_GPIO_PORT2		66
-
-/* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG			67
-#define IRQ_U300_EVHIST			68
-#define IRQ_U300_MSPRO			69
-#define IRQ_U300_MMCSD_MCIINTR0		70
-#define IRQ_U300_MMCSD_MCIINTR1		71
-#define IRQ_U300_I2C0			72
-#define IRQ_U300_I2C1			73
-#define IRQ_U300_RTC			74
-#define IRQ_U300_NFIF			75
-#define IRQ_U300_NFIF2			76
-
-/* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0			77
-#define IRQ_U300_ISP_F1			78
-#define IRQ_U300_ISP_F2			79
-#define IRQ_U300_ISP_F3			80
-#define IRQ_U300_ISP_F4			81
-#define IRQ_U300_GPIO_PORT3		82
-#define IRQ_U300_SYSCON_PLL_LOCK	83
-#define IRQ_U300_UART1			84
-#define IRQ_U300_GPIO_PORT4		85
-#define IRQ_U300_GPIO_PORT5		86
-#define IRQ_U300_GPIO_PORT6		87
-#define U300_VIC_IRQS_END		88
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 00499d9..2e1c81d 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -22,8 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/irqs.h>
-
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:05 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:05 +0200
Subject: [PATCH 30/39] ARM: u300 use module_spi_driver to register driver
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-31-git-send-email-linus.walleij@stericsson.com>

From: Peter Huewe <peterhuewe at gmx.de>

Removing some boilerplate by using module_spi_driver instead of calling
register and unregister in the otherwise empty init/exit functions.

Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/dummyspichip.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 52962bf..ec0283c 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -278,19 +278,7 @@ static struct spi_driver pl022_dummy_driver = {
 	.remove	= pl022_dummy_remove,
 };
 
-static int __init pl022_init_dummy(void)
-{
-	return spi_register_driver(&pl022_dummy_driver);
-}
-
-static void __exit pl022_exit_dummy(void)
-{
-	spi_unregister_driver(&pl022_dummy_driver);
-}
-
-module_init(pl022_init_dummy);
-module_exit(pl022_exit_dummy);
-
+module_spi_driver(pl022_dummy_driver);
 MODULE_AUTHOR("Linus Walleij <linus.walleij at stericsson.com>");
 MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
 MODULE_LICENSE("GPL");
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:04 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:04 +0200
Subject: [PATCH 29/39] ARM: u300: delete remnant machine headers
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-30-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Two files remain in <mach/*> for U300: timex.h and
uncompress.h. The former is done away with by using
defaults, the latter is unused in multiplatform.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/timex.h      | 17 -----------
 arch/arm/mach-u300/include/mach/uncompress.h | 45 ----------------------------
 2 files changed, 62 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/timex.h
 delete mode 100644 arch/arm/mach-u300/include/mach/uncompress.h

diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72..0000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/timex.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform tick rate definition.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-/* This is for the APP OS GP1 (General Purpose 1) timer */
-#define CLOCK_TICK_RATE		1000000
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e6..0000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/uncompress.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR	(*(volatile unsigned char *)0xc0013000)
-#define AMBA_UART_LCRH	(*(volatile unsigned char *)0xc001302C)
-#define AMBA_UART_CR	(*(volatile unsigned char *)0xc0013030)
-#define AMBA_UART_FR	(*(volatile unsigned char *)0xc0013018)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-	while (AMBA_UART_FR & (1 << 5))
-		barrier();
-
-	AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
-	while (AMBA_UART_FR & (1 << 3))
-		barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:14 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:14 +0200
Subject: [PATCH 39/39] ARM: u300: Update MMC configs for u300 defconfig
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-40-git-send-email-linus.walleij@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Enable MMC_UNSAFE_RESUME to be accomplish a proper suspend/resume cycle
for SD/SDIO/(e)MMC.

ARMMMCI host driver supports clock gating through runtime PM, thus
MMC_CLKGATE is not needed. Moreover ARMMMCI can do scatter-gather which
means we can explicity disable MMC_BLOCK_BOUNCE, since it's default
enabled, to skip unnecessary bounce buffer copying.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/configs/u300_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index a5fa0d9..fd81a1b 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -49,7 +49,8 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:12 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:12 +0200
Subject: [PATCH 37/39] pinctrl: get rid of all platform data for coh901
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-38-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This deletes the dependency on any platform data for
the COH901 pin controller. There is only one user in the
kernel, and if we at some point want to support more
variants, they shall provide their variant info through
the device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                    | 12 +-----------
 drivers/pinctrl/pinctrl-coh901.c             | 23 +++++++++--------------
 include/linux/platform_data/pinctrl-coh901.h | 22 ----------------------
 3 files changed, 10 insertions(+), 47 deletions(-)
 delete mode 100644 include/linux/platform_data/pinctrl-coh901.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 6e5744a..4f7ac2a 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -12,7 +12,6 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_data/clk-u300.h>
-#include <linux/platform_data/pinctrl-coh901.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
@@ -194,15 +193,6 @@ static void __init u300_map_io(void)
 	iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 }
 
-/*
- * The different variants have a few different versions of the
- * GPIO block, with different number of ports.
- */
-static struct u300_gpio_platform u300_gpio_plat = {
-	.ports = 7,
-	.gpio_base = 0,
-};
-
 static unsigned long pin_pullup_conf[] = {
 	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 };
@@ -332,7 +322,7 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
 		"pinctrl-u300", NULL),
 	OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
-		"u300-gpio", &u300_gpio_plat),
+		"u300-gpio", NULL),
 	OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
 		"coh901327_wdog", NULL),
 	OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index d4f8afd..46ff140 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -22,7 +22,6 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
 
 #define U300_GPIO_PORT_STRIDE				(0x30)
@@ -58,8 +57,9 @@
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE		(0x00000001UL)
 
 /* 8 bits per port, no version has more than 7 ports */
+#define U300_GPIO_NUM_PORTS 7
 #define U300_GPIO_PINS_PER_PORT 8
-#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
+#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
 
 struct u300_gpio {
 	struct gpio_chip chip;
@@ -111,9 +111,6 @@ struct u300_gpio_confdata {
 	int outval;
 };
 
-/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
-#define BS335_GPIO_NUM_PORTS 7
-
 #define U300_FLOATING_INPUT { \
 	.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
 	.output = false, \
@@ -136,7 +133,7 @@ struct u300_gpio_confdata {
 
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
-bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
+bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 	/* Port 0, pins 0-7 */
 	{
 		U300_FLOATING_INPUT,
@@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 	}
 }
 
-static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
-				     struct u300_gpio_platform *plat)
+static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
 {
 	int i, j;
 
 	/* Write default config and values to all pins */
-	for (i = 0; i < plat->ports; i++) {
+	for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
 		for (j = 0; j < 8; j++) {
 			const struct u300_gpio_confdata *conf;
 			int offset = (i*8) + j;
@@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = {
 
 static int __init u300_gpio_probe(struct platform_device *pdev)
 {
-	struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 	struct u300_gpio *gpio;
 	struct resource *memres;
 	int err = 0;
@@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	gpio->chip = u300_gpio_chip;
-	gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
+	gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
 	gpio->chip.dev = &pdev->dev;
-	gpio->chip.base = plat->gpio_base;
+	gpio->chip.base = 0;
 	gpio->dev = &pdev->dev;
 
 	memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -755,11 +750,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
 		 ((val & 0x0000FE00) >> 9) * 8);
 	writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
 	       gpio->base + U300_GPIO_CR);
-	u300_gpio_init_coh901571(gpio, plat);
+	u300_gpio_init_coh901571(gpio);
 
 	/* Add each port with its IRQ separately */
 	INIT_LIST_HEAD(&gpio->port_list);
-	for (portno = 0 ; portno < plat->ports; portno++) {
+	for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
 		struct u300_gpio_port *port =
 			kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 
diff --git a/include/linux/platform_data/pinctrl-coh901.h b/include/linux/platform_data/pinctrl-coh901.h
deleted file mode 100644
index dfbc65d..0000000
--- a/include/linux/platform_data/pinctrl-coh901.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2007-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * GPIO block resgister definitions and inline macros for
- * U300 GPIO COH 901 335 or COH 901 571/3
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __MACH_U300_GPIO_U300_H
-#define __MACH_U300_GPIO_U300_H
-
-/**
- * struct u300_gpio_platform - U300 GPIO platform data
- * @ports: number of GPIO block ports
- * @gpio_base: first GPIO number for this block (use a free range)
- */
-struct u300_gpio_platform {
-	u8 ports;
-	int gpio_base;
-};
-
-#endif /* __MACH_U300_GPIO_U300_H */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:02 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:02 +0200
Subject: [PATCH 27/39] ARM: u300: localize <mach/u300-regs.h>
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-28-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This register base file is now only used in the machine
itself so move it down into mach-u300.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                         | 2 +-
 arch/arm/mach-u300/regulator.c                    | 2 +-
 arch/arm/mach-u300/{include/mach => }/u300-regs.h | 0
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/arm/mach-u300/{include/mach => }/u300-regs.h (100%)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 254fe92..1fdaf81 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -21,7 +21,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
-#include <mach/u300-regs.h>
+#include "u300-regs.h"
 
 /*
  * SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index ab7d7a5..1cbe88c 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,7 +17,7 @@
 #include <linux/regulator/consumer.h>
 /* Those are just for writing in syscon */
 #include <linux/io.h>
-#include <mach/u300-regs.h>
+#include "u300-regs.h"
 
 /* Power Management Control 16bit (R/W) */
 #define U300_SYSCON_PMCR					(0x50)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
similarity index 100%
rename from arch/arm/mach-u300/include/mach/u300-regs.h
rename to arch/arm/mach-u300/u300-regs.h
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:08 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:08 +0200
Subject: [PATCH 33/39] clk: move the U300 fixed and fixed-factor to DT
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-34-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the fixed and fixed-factor clocks in the U300
platform to register themselves from the device tree.

Acked-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/clk-u300.c         | 33 +++++++++++++------------------
 2 files changed, 57 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 644befd..203ec1fc 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -33,6 +33,49 @@
 	syscon: syscon at c0011000 {
 		compatible = "stericsson,u300-syscon";
 		reg = <0xc0011000 0x1000>;
+		clk32: app_32_clk at 32k {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+		pll13: pll13 at 13M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <13000000>;
+		};
+		pll208: pll208 at 208M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <208000000>;
+		};
+		app208: app_208_clk at 208M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&pll208>;
+		};
+		app104: app_104_clk at 104M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll208>;
+		};
+		app52: app_52_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <4>;
+			clock-mult = <1>;
+			clocks = <&pll208>;
+		};
+		app26: app_26_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&app52>;
+		};
 	};
 
 	timer: timer at c0014000 {
@@ -65,6 +108,7 @@
 		reg = <0xc0012000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <3>;
+		clocks = <&clk32>;
 	};
 
 	rtc: rtc at c0017000 {
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a41e42e..bebd6c9 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
+#include <linux/of.h>
 
 /* APP side SYSCON registers */
 /* CLK Control Register 16bit (R/W) */
@@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
 	return clk;
 }
 
+static const __initconst struct of_device_id u300_clk_match[] = {
+	{
+		.compatible = "fixed-clock",
+		.data = of_fixed_clk_setup,
+	},
+	{
+		.compatible = "fixed-factor-clock",
+		.data = of_fixed_factor_clk_setup,
+	},
+};
+
 void __init u300_clk_init(void __iomem *base)
 {
 	u16 val;
@@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
 	val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
 	writew(val, syscon_vbase + U300_SYSCON_PMCR);
 
-	/* These are always available (RTC and PLL13) */
-	clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
-				      CLK_IS_ROOT, 32768);
-	/* The watchdog sits directly on the 32 kHz clock */
-	clk_register_clkdev(clk, NULL, "coh901327_wdog");
-	clk = clk_register_fixed_rate(NULL, "pll13", NULL,
-				      CLK_IS_ROOT, 13000000);
-
-	/* These derive from PLL208 */
-	clk = clk_register_fixed_rate(NULL, "pll208", NULL,
-				      CLK_IS_ROOT, 208000000);
-	clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
-					0, 1, 1);
-	clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
-					0, 1, 2);
-	clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
-					0, 1, 4);
-	/* The 52 MHz is divided down to 26 MHz */
-	clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
-					0, 1, 2);
+	of_clk_init(u300_clk_match);
 
 	/* Directly on the AMBA interconnect */
 	clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:09 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:09 +0200
Subject: [PATCH 34/39] i2c: stu300: do not request a specific clock name
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-35-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

We have used the default clock associated with the block
for a long time, only heuristics in the clock system has
made this work anyway. This needs to be done away with as
we start probing this driver and its clocks exclusively
from the device tree.

Acked-by: Wolfram Sang <wsa at the-dreams.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/i2c/busses/i2c-stu300.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 1beaa05a..d1a6b20 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -868,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
 	struct resource *res;
 	int bus_nr;
 	int ret = 0;
-	char clk_name[] = "I2C0";
 
 	dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
 	if (!dev) {
@@ -877,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
 	}
 
 	bus_nr = pdev->id;
-	clk_name[3] += (char)bus_nr;
-	dev->clk = devm_clk_get(&pdev->dev, clk_name);
+	dev->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(dev->clk)) {
 		dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
 		return PTR_ERR(dev->clk);
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:07 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:07 +0200
Subject: [PATCH 32/39] ARM: u300: remove register definition file
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-33-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Now that the core file is the only one actually using any
of the base addresses, we can delete that header and move
the base address definitions into the one and only core
file.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c      | 113 +++++++++++++++++++++++++++-
 arch/arm/mach-u300/u300-regs.h | 165 -----------------------------------------
 2 files changed, 112 insertions(+), 166 deletions(-)
 delete mode 100644 arch/arm/mach-u300/u300-regs.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 8cfca45..6e5744a 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -22,7 +22,118 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
-#include "u300-regs.h"
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE		0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE		0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE			(1 << 16)
+#define PLAT_NAND_ALE			(1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE		0xa0000000
+#define U300_AHB_PER_VIRT_BASE		0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE		0xc0000000
+#define U300_FAST_PER_VIRT_BASE		0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE		0xc0010000
+#define U300_SLOW_PER_VIRT_BASE		0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE		0xffff0000
+#define U300_BOOTROM_VIRT_BASE		0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE		0x2FFE0000
+
+/*
+ * AHB peripherals
+ */
+
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)
+
+/*
+ * FAST peripherals
+ */
+
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE			(U300_FAST_PER_PHYS_BASE+0x7000)
+
+/*
+ * SLOW peripherals
+ */
+
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE		(U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)
+
+/*
+ * REST peripherals
+ */
+
+/* ISP (image signal processor) */
+#define U300_ISP_BASE			(0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE			(0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE			(0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE			(0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE		(0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE			(0xd0000000)
 
 /*
  * SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
deleted file mode 100644
index 0320495..0000000
--- a/arch/arm/mach-u300/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE		0x80000000
-
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE		0x9f800000
-
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE			(1 << 16)
-#define PLAT_NAND_ALE			(1 << 17)
-
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE		0xa0000000
-#define U300_AHB_PER_VIRT_BASE		0xff010000
-
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE		0xc0000000
-#define U300_FAST_PER_VIRT_BASE		0xff020000
-
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE		0xc0010000
-#define U300_SLOW_PER_VIRT_BASE		0xff000000
-
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE		0xffff0000
-#define U300_BOOTROM_VIRT_BASE		0xffff0000
-
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE		0x2FFE0000
-
-/*
- * AHB peripherals
- */
-
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)
-
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)
-
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)
-
-
-/*
- * FAST peripherals
- */
-
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)
-
-/* MMC/SD controller */
-#define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)
-
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)
-
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)
-
-/* I2C0 controller */
-#define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)
-
-/* I2C1 controller */
-#define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)
-
-/* SPI controller */
-#define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)
-
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE			(U300_FAST_PER_PHYS_BASE+0x7000)
-
-/*
- * SLOW peripherals
- */
-
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE		(U300_SLOW_PER_PHYS_BASE)
-
-/* SYSCON */
-#define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-
-/* Watchdog */
-#define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)
-
-/* UART0 */
-#define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)
-
-/* APP side special timer */
-#define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-
-/* Keypad */
-#define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)
-
-/* GPIO */
-#define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)
-
-/* RTC */
-#define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
-
-/* Bus tracer */
-#define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)
-
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)
-
-/* Genric Timer */
-#define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)
-
-/* PPM */
-#define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)
-
-
-/*
- * REST peripherals
- */
-
-/* ISP (image signal processor) */
-#define U300_ISP_BASE			(0xA0008000)
-
-/* DMA Controller base */
-#define U300_DMAC_BASE			(0xC0020000)
-
-/* MSL Base */
-#define U300_MSL_BASE			(0xc0022000)
-
-/* APEX Base */
-#define U300_APEX_BASE			(0xc0030000)
-
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE		(0xc0080000)
-
-/* XGAM Base */
-#define U300_XGAM_BASE			(0xd0000000)
-
-#endif
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:13 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:13 +0200
Subject: [PATCH 38/39] spi: pl022: use DMA by default when probing from DT
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-39-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

In the past we controlled the selection of DMA for a certain
host by a boolean switch in the platform data. Currently
there is no way to enable DMA on a PL022 probed from the
device tree. Let's default to trying to obtain DMA channels
in the DT case, and then we can always fail (and thus fall
back to PIO mode).

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/spi/spi-pl022.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 371cc66f..3b24654 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2083,6 +2083,7 @@ pl022_platform_data_dt_get(struct device *dev)
 	}
 
 	pd->bus_id = -1;
+	pd->enable_dma = 1;
 	of_property_read_u32(np, "num-cs", &tmp);
 	pd->num_chipselect = tmp;
 	of_property_read_u32(np, "pl022,autosuspend-delay",
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:11 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:11 +0200
Subject: [PATCH 36/39] ARM: u300: convert MMC/SD clock to device tree
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-37-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the last of the U300 clocks to being probed from
the device tree.

Acked-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 .../bindings/clock/ste-u300-syscon-clock.txt       | 23 ++++++++++++++++++++++
 arch/arm/boot/dts/ste-u300.dts                     |  9 +++++++--
 drivers/clk/clk-u300.c                             | 22 ++++++++++++++++-----
 3 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
index b6a30f5..7cafcb9 100644
--- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -55,3 +55,26 @@ gpio: gpio at c0016000 {
 	(...)
 	clocks = <&gpio_clk>;
 };
+
+
+Bindings for the MMC/SD card clock:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-mclk"
+- #clock-cells: must be <0>
+
+Optional properties:
+- clocks: parent clock(s)
+
+mmc_mclk: mmc_mclk {
+	#clock-cells = <0>;
+	compatible = "stericsson,u300-syscon-mclk";
+	clocks = <&mmc_pclk>;
+};
+
+mmcsd: mmcsd at c0001000 {
+	compatible = "arm,pl18x", "arm,primecell";
+	clocks = <&mmc_pclk>, <&mmc_mclk>;
+	clock-names = "apb_pclk", "mclk";
+	(...)
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 7edc5e5..05a0821 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -205,6 +205,11 @@
 			clock-id = <5>;
 			clocks = <&fast_clk>;
 		};
+		mmc_mclk: mmc_mclk {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-mclk";
+			clocks = <&mmc_pclk>;
+		};
 		spi_clk: spi_p_clk at 26M {
 			#clock-cells = <0>;
 			compatible = "stericsson,u300-syscon-clk";
@@ -433,8 +438,8 @@
 			reg = <0xc0001000 0x1000>;
 			interrupt-parent = <&vicb>;
 			interrupts = <6 7>;
-			clocks = <&mmc_pclk>;
-			clock-names = "apb_pclk";
+			clocks = <&mmc_pclk>, <&mmc_mclk>;
+			clock-names = "apb_pclk", "mclk";
 			max-frequency = <24000000>;
 			bus-width = <4>; // SD-card slot
 			mmc-cap-mmc-highspeed;
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 5f234d3..8774e05 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
 	return clk;
 }
 
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+	struct clk *clk = ERR_PTR(-EINVAL);
+	const char *clk_name = np->name;
+	const char *parent_name;
+
+	parent_name = of_clk_get_parent_name(np, 0);
+	clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
 static const __initconst struct of_device_id u300_clk_match[] = {
 	{
 		.compatible = "fixed-clock",
@@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
 		.compatible = "stericsson,u300-syscon-clk",
 		.data = of_u300_syscon_clk_init,
 	},
+	{
+		.compatible = "stericsson,u300-syscon-mclk",
+		.data = of_u300_syscon_mclk_init,
+	},
 };
 
+
 void __init u300_clk_init(void __iomem *base)
 {
 	u16 val;
-	struct clk *clk;
 
 	syscon_vbase = base;
 
@@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
 	writew(val, syscon_vbase + U300_SYSCON_PMCR);
 
 	of_clk_init(u300_clk_match);
-
-	/* Then this special MMC/SD clock */
-	clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
-	clk_register_clkdev(clk, NULL, "mmci");
 }
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri May 31 05:19:10 2013
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 31 May 2013 11:19:10 +0200
Subject: [PATCH 35/39] ARM: u300: move the gated system controller clocks to DT
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1369991954-17406-36-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This moves the slow, fast, AHB bridge and "rest" clocks on
the U300 system controller over to registration from the
device tree.

Acked-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 .../bindings/clock/ste-u300-syscon-clock.txt       |  57 ++++
 arch/arm/boot/dts/ste-u300.dts                     | 149 ++++++++++
 arch/arm/mach-u300/timer.c                         |   2 +-
 drivers/clk/clk-u300.c                             | 320 ++++++++++++++-------
 4 files changed, 418 insertions(+), 110 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 0000000..b6a30f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,57 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+
+Bindings for the gated system controller clocks:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+  0 = slow clock
+  1 = fast clock
+  2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+
+Optional properties:
+- clocks: parent clock(s)
+
+The available clocks per type are as follows:
+
+Type:  ID:   Clock:
+-------------------
+0      0     Slow peripheral bridge clock
+0      1     UART0 clock
+0      4     GPIO clock
+0      6     RTC clock
+0      7     Application timer clock
+0      8     Access timer clock
+
+1      0     Fast peripheral bridge clock
+1      1     I2C bus 0 clock
+1      2     I2C bus 1 clock
+1      5     MMC interface peripheral (silicon) clock
+1      6     SPI clock
+
+2      3     CPU clock
+2      4     DMA controller clock
+2      5     External Memory Interface (EMIF) clock
+2      6     NAND flask interface clock
+2      8     XGAM graphics engine clock
+2      9     Shared External Memory Interface (SEMI) clock
+2      10    AHB Subsystem Bridge clock
+2      12    Interrupt controller clock
+
+Example:
+
+gpio_clk: gpio_clk at 13M {
+	#clock-cells = <0>;
+	compatible = "stericsson,u300-syscon-clk";
+	clock-type = <0>; /* Slow */
+	clock-id = <4>;
+	clocks = <&slow_clk>;
+};
+
+gpio: gpio at c0016000 {
+	compatible = "stericsson,gpio-coh901";
+	(...)
+	clocks = <&gpio_clk>;
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 203ec1fc..7edc5e5 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
 			compatible = "fixed-clock";
 			clock-frequency = <13000000>;
 		};
+		/* Slow bridge clocks under PLL13 */
+		slow_clk: slow_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <0>;
+			clocks = <&pll13>;
+		};
+		uart0_clk: uart0_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <1>;
+			clocks = <&slow_clk>;
+		};
+		gpio_clk: gpio_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <4>;
+			clocks = <&slow_clk>;
+		};
+		rtc_clk: rtc_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <6>;
+			clocks = <&slow_clk>;
+		};
+		apptimer_clk: app_tmr_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <7>;
+			clocks = <&slow_clk>;
+		};
+		acc_tmr_clk at 13M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <0>; /* Slow */
+			clock-id = <8>;
+			clocks = <&slow_clk>;
+		};
 		pll208: pll208 at 208M {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -55,6 +98,13 @@
 			clock-mult = <1>;
 			clocks = <&pll208>;
 		};
+		cpu_clk at 208M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <3>;
+			clocks = <&app208>;
+		};
 		app104: app_104_clk at 104M {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
 			clock-mult = <1>;
 			clocks = <&pll208>;
 		};
+		semi_clk at 104M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <9>;
+			clocks = <&app104>;
+		};
 		app52: app_52_clk at 52M {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
 			clock-mult = <1>;
 			clocks = <&pll208>;
 		};
+		/* AHB subsystem clocks */
+		ahb_clk: ahb_subsys_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <10>;
+			clocks = <&app52>;
+		};
+		intcon_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <12>;
+			clocks = <&ahb_clk>;
+		};
+		emif_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <5>;
+			clocks = <&ahb_clk>;
+		};
+		dmac_clk: dmac_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <4>;
+			clocks = <&app52>;
+		};
+		fsmc_clk: fsmc_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <6>;
+			clocks = <&app52>;
+		};
+		xgam_clk: xgam_clk at 52M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <2>; /* Rest */
+			clock-id = <8>;
+			clocks = <&app52>;
+		};
 		app26: app_26_clk at 26M {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
 			clock-mult = <1>;
 			clocks = <&app52>;
 		};
+		/* Fast bridge  clocks */
+		fast_clk: fast_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <0>;
+			clocks = <&app26>;
+		};
+		i2c0_clk: i2c0_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <1>;
+			clocks = <&fast_clk>;
+		};
+		i2c1_clk: i2c1_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <2>;
+			clocks = <&fast_clk>;
+		};
+		mmc_pclk: mmc_p_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <5>;
+			clocks = <&fast_clk>;
+		};
+		spi_clk: spi_p_clk at 26M {
+			#clock-cells = <0>;
+			compatible = "stericsson,u300-syscon-clk";
+			clock-type = <1>; /* Fast */
+			clock-id = <6>;
+			clocks = <&fast_clk>;
+		};
 	};
 
 	timer: timer at c0014000 {
@@ -83,6 +219,7 @@
 		reg = <0xc0014000 0x1000>;
 		interrupt-parent = <&vica>;
 		interrupts = <24 25 26 27>;
+		clocks = <&apptimer_clk>;
 	};
 
 	gpio: gpio at c0016000 {
@@ -90,6 +227,7 @@
 		reg = <0xc0016000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <0 1 2 18 21 22 23>;
+		clocks = <&gpio_clk>;
 		interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
 				"gpio4", "gpio5", "gpio6";
 		interrupt-controller;
@@ -116,6 +254,7 @@
 		reg = <0xc0017000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <10>;
+		clocks = <&rtc_clk>;
 	};
 
 	dmac: dma-controller at c00020000 {
@@ -125,6 +264,7 @@
 		interrupts = <2>;
 		#dma-cells = <1>;
 		dma-channels = <40>;
+		clocks = <&dmac_clk>;
 	};
 
 	/* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
 			<0x80010000 0x4000>;	/* NAND Base CMD */
 		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
 		nand-skip-bbtscan;
+		clocks = <&fsmc_clk>;
 
 		partition at 0 {
 		label = "boot records";
@@ -158,6 +299,7 @@
 		reg = <0xc0004000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <8>;
+		clocks = <&i2c0_clk>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		ab3100: ab3100 at 0x48 {
@@ -235,6 +377,7 @@
 		reg = <0xc0005000 0x1000>;
 		interrupt-parent = <&vicb>;
 		interrupts = <9>;
+		clocks = <&i2c1_clk>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		fwcam0: fwcam at 0x10 {
@@ -270,6 +413,8 @@
 			reg = <0xc0013000 0x1000>;
 			interrupt-parent = <&vica>;
 			interrupts = <22>;
+			clocks = <&uart0_clk>, <&uart0_clk>;
+			clock-names = "apb_pclk", "uart0_clk";
 			dmas = <&dmac 17 &dmac 18>;
 			dma-names = "tx", "rx";
 		};
@@ -288,6 +433,8 @@
 			reg = <0xc0001000 0x1000>;
 			interrupt-parent = <&vicb>;
 			interrupts = <6 7>;
+			clocks = <&mmc_pclk>;
+			clock-names = "apb_pclk";
 			max-frequency = <24000000>;
 			bus-width = <4>; // SD-card slot
 			mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
 			reg = <0xc0006000 0x1000>;
 			interrupt-parent = <&vica>;
 			interrupts = <23>;
+			clocks = <&spi_clk>, <&spi_clk>;
+			clock-names = "apb_pclk", "spi_clk";
 			dmas = <&dmac 27 &dmac 28>;
 			dma-names = "tx", "rx";
 			num-cs = <3>;
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e1c81d..390ae5f 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
 	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
 
 	/* Clock the interrupt controller */
-	clk = clk_get_sys("apptimer", NULL);
+	clk = of_clk_get(np, 0);
 	BUG_ON(IS_ERR(clk));
 	clk_prepare_enable(clk);
 	rate = clk_get_rate(clk);
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index bebd6c9..5f234d3 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
 	return clk;
 }
 
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+	u8 type;
+	u8 id;
+	bool hw_ctrld;
+	u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 3,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 4,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 5,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 6,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 8,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 9,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 10,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_REST,
+		.id = 12,
+		.hw_ctrld = false,
+		/* INTCON: cannot be enabled, just taken out of reset */
+		.clk_val = 0xFFFFU,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 0,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 1,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 2,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 5,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_FAST,
+		.id = 6,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 0,
+		.hw_ctrld = true,
+		.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 1,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 4,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 6,
+		.hw_ctrld = true,
+		/* No clock enable register bit */
+		.clk_val = 0xFFFFU,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 7,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+	},
+	{
+		.type = U300_CLK_TYPE_SLOW,
+		.id = 8,
+		.hw_ctrld = false,
+		.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+	},
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+	struct clk *clk = ERR_PTR(-EINVAL);
+	const char *clk_name = np->name;
+	const char *parent_name;
+	void __iomem *res_reg;
+	void __iomem *en_reg;
+	u32 clk_type;
+	u32 clk_id;
+	int i;
+
+	if (of_property_read_u32(np, "clock-type", &clk_type)) {
+		pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+		       __func__, clk_name);
+		return;
+	}
+	if (of_property_read_u32(np, "clock-id", &clk_id)) {
+		pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+		       __func__, clk_name);
+		return;
+	}
+	parent_name = of_clk_get_parent_name(np, 0);
+
+	switch (clk_type) {
+	case U300_CLK_TYPE_SLOW:
+		res_reg = syscon_vbase + U300_SYSCON_RSR;
+		en_reg = syscon_vbase + U300_SYSCON_CESR;
+		break;
+	case U300_CLK_TYPE_FAST:
+		res_reg = syscon_vbase + U300_SYSCON_RFR;
+		en_reg = syscon_vbase + U300_SYSCON_CEFR;
+		break;
+	case U300_CLK_TYPE_REST:
+		res_reg = syscon_vbase + U300_SYSCON_RRR;
+		en_reg = syscon_vbase + U300_SYSCON_CERR;
+		break;
+	default:
+		pr_err("unknown clock type %x specified\n", clk_type);
+		return;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+		const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+		if (u3clk->type == clk_type && u3clk->id == clk_id)
+			clk = syscon_clk_register(NULL,
+						  clk_name, parent_name,
+						  0, u3clk->hw_ctrld,
+						  res_reg, u3clk->id,
+						  en_reg, u3clk->id,
+						  u3clk->clk_val);
+	}
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+		/*
+		 * Some few system clocks - device tree does not
+		 * represent clocks without a corresponding device node.
+		 * for now we add these three clocks here.
+		 */
+		if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+			clk_register_clkdev(clk, NULL, "pl172");
+		if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+			clk_register_clkdev(clk, NULL, "semi");
+		if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+			clk_register_clkdev(clk, NULL, "intcon");
+	}
+}
+
 /**
  * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
  * @hw: corresponding clock hardware entry
@@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
 		.compatible = "fixed-factor-clock",
 		.data = of_fixed_factor_clk_setup,
 	},
+	{
+		.compatible = "stericsson,u300-syscon-clk",
+		.data = of_u300_syscon_clk_init,
+	},
 };
 
 void __init u300_clk_init(void __iomem *base)
@@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
 
 	of_clk_init(u300_clk_match);
 
-	/* Directly on the AMBA interconnect */
-	clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 3,
-				  syscon_vbase + U300_SYSCON_CERR, 3,
-				  U300_SYSCON_SBCER_CPU_CLK_EN);
-	clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 4,
-				  syscon_vbase + U300_SYSCON_CERR, 4,
-				  U300_SYSCON_SBCER_DMAC_CLK_EN);
-	clk_register_clkdev(clk, NULL, "dma");
-	clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 6,
-				  syscon_vbase + U300_SYSCON_CERR, 6,
-				  U300_SYSCON_SBCER_NANDIF_CLK_EN);
-	clk_register_clkdev(clk, NULL, "fsmc-nand");
-	clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 8,
-				  syscon_vbase + U300_SYSCON_CERR, 8,
-				  U300_SYSCON_SBCER_XGAM_CLK_EN);
-	clk_register_clkdev(clk, NULL, "xgam");
-	clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 9,
-				  syscon_vbase + U300_SYSCON_CERR, 9,
-				  U300_SYSCON_SBCER_SEMI_CLK_EN);
-	clk_register_clkdev(clk, NULL, "semi");
-
-	/* AHB bridge clocks */
-	clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RRR, 10,
-				  syscon_vbase + U300_SYSCON_CERR, 10,
-				  U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
-	clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 12,
-				  syscon_vbase + U300_SYSCON_CERR, 12,
-				  /* Cannot be enabled, just taken out of reset */
-				  0xFFFFU);
-	clk_register_clkdev(clk, NULL, "intcon");
-	clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RRR, 5,
-				  syscon_vbase + U300_SYSCON_CERR, 5,
-				  U300_SYSCON_SBCER_EMIF_CLK_EN);
-	clk_register_clkdev(clk, NULL, "pl172");
-
-	/* FAST bridge clocks */
-	clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RFR, 0,
-				  syscon_vbase + U300_SYSCON_CEFR, 0,
-				  U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
-	clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 1,
-				  syscon_vbase + U300_SYSCON_CEFR, 1,
-				  U300_SYSCON_SBCER_I2C0_CLK_EN);
-	clk_register_clkdev(clk, NULL, "stu300.0");
-	clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 2,
-				  syscon_vbase + U300_SYSCON_CEFR, 2,
-				  U300_SYSCON_SBCER_I2C1_CLK_EN);
-	clk_register_clkdev(clk, NULL, "stu300.1");
-	clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 5,
-				  syscon_vbase + U300_SYSCON_CEFR, 5,
-				  U300_SYSCON_SBCER_MMC_CLK_EN);
-	clk_register_clkdev(clk, "apb_pclk", "mmci");
-	clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RFR, 6,
-				  syscon_vbase + U300_SYSCON_CEFR, 6,
-				  U300_SYSCON_SBCER_SPI_CLK_EN);
-	/* The SPI has no external clock for the outward bus, uses the pclk */
-	clk_register_clkdev(clk, NULL, "pl022");
-	clk_register_clkdev(clk, "apb_pclk", "pl022");
-
-	/* SLOW bridge clocks */
-	clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
-				  syscon_vbase + U300_SYSCON_RSR, 0,
-				  syscon_vbase + U300_SYSCON_CESR, 0,
-				  U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
-	clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 1,
-				  syscon_vbase + U300_SYSCON_CESR, 1,
-				  U300_SYSCON_SBCER_UART_CLK_EN);
-	/* Same clock is used for APB and outward bus */
-	clk_register_clkdev(clk, NULL, "uart0");
-	clk_register_clkdev(clk, "apb_pclk", "uart0");
-	clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 4,
-				  syscon_vbase + U300_SYSCON_CESR, 4,
-				  U300_SYSCON_SBCER_GPIO_CLK_EN);
-	clk_register_clkdev(clk, NULL, "u300-gpio");
-	clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 5,
-				  syscon_vbase + U300_SYSCON_CESR, 6,
-				  U300_SYSCON_SBCER_KEYPAD_CLK_EN);
-	clk_register_clkdev(clk, NULL, "coh901461-keypad");
-	clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
-				  syscon_vbase + U300_SYSCON_RSR, 6,
-				  /* No clock enable register bit */
-				  NULL, 0, 0xFFFFU);
-	clk_register_clkdev(clk, NULL, "rtc-coh901331");
-	clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 7,
-				  syscon_vbase + U300_SYSCON_CESR, 7,
-				  U300_SYSCON_SBCER_APP_TMR_CLK_EN);
-	clk_register_clkdev(clk, NULL, "apptimer");
-	clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
-				  syscon_vbase + U300_SYSCON_RSR, 8,
-				  syscon_vbase + U300_SYSCON_CESR, 8,
-				  U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
-	clk_register_clkdev(clk, NULL, "timer");
-
 	/* Then this special MMC/SD clock */
 	clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
 	clk_register_clkdev(clk, NULL, "mmci");
-- 
1.7.11.3



From daniel.lezcano at linaro.org  Fri May 31 05:27:45 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 31 May 2013 11:27:45 +0200
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
 <51A763BD.6070001@linaro.org>
 <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <51A86D11.8060305@linaro.org>

On 05/31/2013 11:12 AM, Joseph Lo wrote:
> Hi Daniel,
> 
> Thanks for your review.
> 
> On Thu, 2013-05-30 at 22:35 +0800, Daniel Lezcano wrote:
>> On 05/30/2013 01:19 PM, Joseph Lo wrote:
>>> This supports CPU core power down on each CPU when CPU idle. When CPU go
>>> into this state, it saves it's context and needs a proper configuration
>>> in flow controller to power gate the CPU when CPU runs into WFI
>>> instruction. And the CPU also needs to set the IRQ as CPU power down idle
>>> wake up event in flow controller.
>>>
>>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
>>> ---
>>
>> Hi Joseph,
>>
>> a new flag has been added in the cpuidle framework to let this one to
>> handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP
>>
>> It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c
>>
>> You can get rid of the clockevent notify stuff by adding this flag to
>> the state.
>>
> 
> I just tested this flag on Tegra20, 30 and 114. It is only OK on
> Tegra20. It caused a warning message below on Tegra30/114 at boot time.
> 
> I gave it a quick check I found it can't clean
> tick_broadcast_pending_mask sometimes if apply the flag. But I keep the
> code right now it's always OK. Not sure why? 

Is it possible you didn't intialized the timer broadcast with
CLOCK_EVT_NOTIFY_BROADCAST_ON in the driver and then this one is
actually disabled for you driver ?

> [   25.629539] ------------[ cut here ]------------
> [   25.629559] WARNING: CPU: 2 PID: 0 at
> kernel/time/tick-broadcast.c:578 tick_broadcast_oneshot_control
> +0x1a4/0x1d0()
> [   25.629565] Modules linked in:
> [   25.629574] CPU: 2 PID: 0 Comm: swapper/2 Not tainted
> 3.10.0-rc3-next-20130529+ #15
> [   25.629601] [<c00148f4>] (unwind_backtrace+0x0/0xf8) from
> [<c0011040>] (show_stack+0x10/0x14)
> [   25.629616] [<c0011040>] (show_stack+0x10/0x14) from [<c0504248>]
> (dump_stack+0x80/0xc4)
> [   25.629633] [<c0504248>] (dump_stack+0x80/0xc4) from [<c00231ac>]
> (warn_slowpath_common+0x64/0x88)
> [   25.629646] [<c00231ac>] (warn_slowpath_common+0x64/0x88) from
> [<c00231ec>] (warn_slowpath_null+0x1c/0x24)
> [   25.629657] [<c00231ec>] (warn_slowpath_null+0x1c/0x24) from
> [<c00667f8>] (tick_broadcast_oneshot_control+0x1a4/0x1d0)
> [   25.629670] [<c00667f8>] (tick_broadcast_oneshot_control+0x1a4/0x1d0)
> from [<c0065cd0>] (tick_notify+0x240/0x40c)
> [   25.629685] [<c0065cd0>] (tick_notify+0x240/0x40c) from [<c0044724>]
> (notifier_call_chain+0x44/0x84)
> [   25.629699] [<c0044724>] (notifier_call_chain+0x44/0x84) from
> [<c0044828>] (raw_notifier_call_chain+0x18/0x20)
> [   25.629712] [<c0044828>] (raw_notifier_call_chain+0x18/0x20) from
> [<c00650cc>] (clockevents_notify+0x28/0x170)
> [   25.629726] [<c00650cc>] (clockevents_notify+0x28/0x170) from
> [<c033f1f0>] (cpuidle_idle_call+0x11c/0x168)
> [   25.629739] [<c033f1f0>] (cpuidle_idle_call+0x11c/0x168) from
> [<c000ea94>] (arch_cpu_idle+0x8/0x38)
> [   25.629755] [<c000ea94>] (arch_cpu_idle+0x8/0x38) from [<c005ea80>]
> (cpu_startup_entry+0x60/0x134)
> [   25.629767] [<c005ea80>] (cpu_startup_entry+0x60/0x134) from
> [<804fe9a4>] (0x804fe9a4)
> [   25.629772] ---[ end trace 5484e77e2531bccc ]---
> 
> 
>> Also, can you clarify why tegra3 code is used in tegra114 ?
>>
> Yes, because the flow controller that was used to control CPU power is
> similar for both SoCs. The function is shared for Tegra30/114.
> 
>>
>>>  arch/arm/mach-tegra/cpuidle-tegra114.c | 62 +++++++++++++++++++++++++++++++++-
>>>  1 file changed, 61 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
>>> index 1d1c602..e7d21f5 100644
>>> --- a/arch/arm/mach-tegra/cpuidle-tegra114.c
>>> +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
>>> @@ -17,19 +17,79 @@
>>>  #include <linux/kernel.h>
>>>  #include <linux/module.h>
>>>  #include <linux/cpuidle.h>
>>> +#include <linux/cpu_pm.h>
>>> +#include <linux/clockchips.h>
>>>  
>>>  #include <asm/cpuidle.h>
>>> +#include <asm/suspend.h>
>>> +#include <asm/smp_plat.h>
>>> +
>>> +#include "pm.h"
>>> +#include "sleep.h"
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int tegra114_idle_power_down(struct cpuidle_device *dev,
>>> +				    struct cpuidle_driver *drv,
>>> +				    int index);
>>
>> Isn't possible to move the driver declaration after the
>> tegra114_idle_power_down function, before the init function, so we
>> prevent a forward declaration ?
>>
>>> +#define TEGRA114_MAX_STATES 2
>>> +#else
>>> +#define TEGRA114_MAX_STATES 1
>>> +#endif
>>>  
>>>  static struct cpuidle_driver tegra_idle_driver = {
>>>  	.name = "tegra_idle",
>>>  	.owner = THIS_MODULE,
>>> -	.state_count = 1,
>>> +	.state_count = TEGRA114_MAX_STATES,
>>>  	.states = {
>>>  		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
>>> +#ifdef CONFIG_PM_SLEEP
>>> +		[1] = {
>>> +			.enter			= tegra114_idle_power_down,
>>> +			.exit_latency		= 500,
>>> +			.target_residency	= 1000,
>>> +			.power_usage		= 0,
>>> +			.flags			= CPUIDLE_FLAG_TIME_VALID,
>>> +			.name			= "powered-down",
>>> +			.desc			= "CPU power gated",
>>> +		},
>>> +#endif
>>>  	},
>>>  };
>>>  
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int tegra114_idle_power_down(struct cpuidle_device *dev,
>>> +				    struct cpuidle_driver *drv,
>>> +				    int index)
>>> +{
>>> +	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
>>
>> IMO, it is up to the tegra_set_cpu_in_lp2 / tegra_clear_cpu_in_lp2
>> functions to do the cpu map conversion instead of adding this into a
>> routine working with logical cpu.
>>
> Good idea, I can create another patch to do that.
> 
>>> +	local_fiq_disable();
>>> +
>>> +	tegra_set_cpu_in_lp2(cpu);
>>> +	cpu_pm_enter();
>>> +
>>> +	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
>>> +	smp_wmb();
>>
>> Why do you need a memory barrier here ?
>>
> Yeah, Looks I don't have any static data that needs a barrier to sync
> data for SMP here. Will remove them.
> 
>>> +	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
>>> +
>>> +	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
>>> +
>>> +	cpu_pm_exit();
>>> +	tegra_clear_cpu_in_lp2(cpu);
>>> +
>>> +	local_fiq_enable();
>>> +
>>> +	smp_rmb();
>>
>> Why do you need a memory barrier here ?
>>
>>> +	return index;
>>> +}
>>> +#endif
>>> +
>>>  int __init tegra114_cpuidle_init(void)
>>>  {
>>> +#ifdef CONFIG_PM_SLEEP
>>> +	tegra_tear_down_cpu = tegra30_tear_down_cpu;
>>> +#endif
>>
>> Doesn't this code should go in the pm.c file ?
>>
> Yes, I had a plan to do that too. Currently It had a timing issue about
> this. Because the CPU idle driver was registered by device_initcall, but
> the PM init function was registered at late init. I need to sync the
> init time first.
> OK, will do that too.
> 
> Thanks,
> Joseph
> 
> 


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog



From nicolas.ferre at atmel.com  Fri May 31 05:31:33 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 11:31:33 +0200
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA
 DT binding
In-Reply-To: <20130531091627.GD11384@ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
 <51A77F10.8020808@atmel.com> <20130530163936.GC23653@game.jcrosoft.org>
 <20130531091627.GD11384@ludovic.desroches@atmel.com>
Message-ID: <51A86DF5.4010808@atmel.com>

On 31/05/2013 11:16, Ludovic Desroches :
> On Thu, May 30, 2013 at 06:39:36PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 18:32 Thu 30 May     , Nicolas Ferre wrote:
>>> On 30/05/2013 18:08, ludovic.desroches at atmel.com :
>>>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>>>
>>>> For most devices the FIFO configuration is the same i.e. when half FIFO size is
>>>> available/filled, a source/destination request is serviced. But USART devices
>>>> have to do it when there is enough space/data available to perform a single
>>>> AHB access so the ASAP configuration.
>>>>
>>>> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>>>
>>> Clear and neat: thanks Ludo.
>>
>> agreed
>>
>> can we apply this via AT91 as this depends on some cleanup I did on DT and
>> could result on some nigthmware conflict
>>
>
> In fact, I am not sure it's the best solution. I have noticed that there is a
> conflict with a patch sent by Nicolas (dmaengine: at_hdmac: extend hardware
> handshaking interface identification) which is already in Vinod's tree but
> which is not present on Jean-Christophe's cleanup tree on which I based these
> patches.
>
> Moreover this patch doesn't use macros introduced by Nicolas' patch. I may
> update it and it should go through Vinod's tree with a dependence on patch 1/3.
>
> What's your point of view?

Indeed. Another option could be to push patches 1 and 3 in dmaengine's 
tree and make the 2nd patch go through arm-soc with a dependency on 
slave-dma GIT tree (it seems it is an usual patern).

Arnd, Jean-Christophe, what do you think?

Bye,
-- 
Nicolas Ferre


From davem at davemloft.net  Fri May 31 05:32:50 2013
From: davem at davemloft.net (David Miller)
Date: Fri, 31 May 2013 02:32:50 -0700 (PDT)
Subject: [PATCH v5 00/13] net: mv643xx_eth DT support and fixes
In-Reply-To: <51A8432A.4000602@gmail.com>
References: <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20130530.175549.407800685811475192.davem@davemloft.net>
 <51A8432A.4000602@gmail.com>
Message-ID: <20130531.023250.1043552574744640563.davem@davemloft.net>

From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Date: Fri, 31 May 2013 08:28:58 +0200

> thanks for pulling these in. I finally found how to check if a patch
> already went into -stable. As Jason already said, the mdio patch that
> #1 fixes did not yet went into -stable. Can you unqueue it? Sorry for
> the confusion.

I'll unqueue it, thanks.


From richard.genoud at gmail.com  Fri May 31 05:39:01 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 31 May 2013 11:39:01 +0200
Subject: [PATCH 0/2] ARM: dts: add watchdog device tree node in at91 dts
 files
In-Reply-To: <1369969893-7992-1-git-send-email-wenyou.yang@atmel.com>
References: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
 <1369969893-7992-1-git-send-email-wenyou.yang@atmel.com>
Message-ID: <CACQ1gAjF=L+tVcJc3QMv7HEYcny2y-HcDLGJ5N7XbM=_vL+dFQ@mail.gmail.com>

2013/5/31 Wenyou Yang <wenyou.yang at atmel.com>:
> Hello,
>
> The patches is to add watchdog device tree node for at91 SoC and board dts files.
>
> Since the watchdog is disabled in the at91bootstrap with default configuration,
> if you want to use the watchdog in the kernel, you must make sure the watchdog
> doesn't be disabled in the at91bootstrap.
>
> It is tested on at91sam9g20ek, at91sam9263ek, at91sam9g25ek
> using Documentation/watchdog/src/watchdog-simple.c.
>
> It is based on v3.10-rc3, tested on linux-watchdog git tree as well.
>
> Best Regards,
> Wenyou Yang
>
> Wenyou Yang (2):
>   ARM: dts: add the watchdog nodes for at91 SoC
>   ARM: dts: add the watchdog nodes for at91 boards
>
>  arch/arm/boot/dts/at91sam9263ek.dts         |    4 ++++
>  arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    4 ++++
>  arch/arm/boot/dts/at91sam9m10g45ek.dts      |    4 ++++
>  arch/arm/boot/dts/at91sam9n12.dtsi          |    6 ++++++
>  arch/arm/boot/dts/at91sam9n12ek.dts         |    4 ++++
>  arch/arm/boot/dts/at91sam9x5.dtsi           |    6 ++++++
>  arch/arm/boot/dts/at91sam9x5ek.dtsi         |    4 ++++
>  7 files changed, 32 insertions(+)
>
> --
> 1.7.9.5
>

Those patches haven been floating around from quite some time.
Let's merge them !

Tested on sam9g35, v3.10-rc2

Tested-by: Richard Genoud <richard.genoud at gmail.com>


From srinivas.kandagatla at st.com  Fri May 31 05:43:59 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 31 May 2013 10:43:59 +0100
Subject: [PATCH v1 0/2] ARM:prima2: multi_v7 kernel fixes.
Message-ID: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>

From: Srinivas Kandagatla <srinivas.kandagatla at st.com>

If we try to boot a multi_v7_defconfig kernel on any ARM parts other than 
prima2, you will hit kernel panics. This is because some of the code is still
using explicit early_initcall and postcore_initcalls.

Moving these calls to machine descriptor level is the right way to fix this
issue. Also the calls will not be attempted to run on any non-prima2 parts.

As I do not have any prima2 boards, I could not test these patches.
However I feel that these are safe patches.

Barry, can you give it a quick test please.

Thankyou,
srini

Srinivas Kandagatla (2):
  ARM:prima2: move sirfsoc_of_rstc_init to .init_early
  ARM:prima2:move postcore_initcalls to init_machine.

 arch/arm/mach-prima2/common.c |    6 ++++++
 arch/arm/mach-prima2/common.h |    1 +
 arch/arm/mach-prima2/pm.c     |    6 ++----
 arch/arm/mach-prima2/pm.h     |    2 ++
 arch/arm/mach-prima2/rstc.c   |    5 +----
 5 files changed, 12 insertions(+), 8 deletions(-)

-- 
1.7.6.5



From srinivas.kandagatla at st.com  Fri May 31 05:45:01 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 31 May 2013 10:45:01 +0100
Subject: [PATCH v1 1/2] ARM:prima2: move sirfsoc_of_rstc_init to .init_early
In-Reply-To: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
References: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <1369993501-24309-1-git-send-email-srinivas.kandagatla@st.com>

From: Srinivas Kandagatla <srinivas.kandagatla at st.com>

This patch moves sirfsoc_of_rstc_init from early_initcall to .init_early
in machine descriptor, doing this way a multi_v7 kernel will not crash
on non-prima2 SOCs.

Without this patch the multi_v7 kernel panics if we boot it on any non
prima2 parts with below log:

Kernel panic - not syncing: unable to find compatible rstc node in dtb

CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc3-00535-gc3cc4ac #62
[<c001387c>] (unwind_backtrace+0x0/0xf8) from [<c00111cc>]
(show_stack+0x10/0x14)
[<c00111cc>] (show_stack+0x10/0x14) from [<c03417f4>] (panic+0x90/0x1e4)
[<c03417f4>] (panic+0x90/0x1e4) from [<c04256d0>]
(sirfsoc_of_rstc_init+0x24/0x5c)
[<c04256d0>] (sirfsoc_of_rstc_init+0x24/0x5c) from [<c041f854>]
(do_one_initcall+0x90/0x150)
[<c041f854>] (do_one_initcall+0x90/0x150) from [<c041f978>]
(kernel_init_freeable+0x64/0x1c4)
[<c041f978>] (kernel_init_freeable+0x64/0x1c4) from [<c033d344>]
(kernel_init+0x8/0xe4)
[<c033d344>] (kernel_init+0x8/0xe4) from [<c000ded8>]
(ret_from_fork+0x14/0x3c)

Initially detected when booting Stih415 SOC with multi_v7_defconfig.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
---
 arch/arm/mach-prima2/common.c |    3 +++
 arch/arm/mach-prima2/common.h |    1 +
 arch/arm/mach-prima2/rstc.c   |    5 +----
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd8..9aefcd6 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -61,6 +61,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = atlas6_dt_match,
 	.restart	= sirfsoc_restart,
+	.init_early	= sirfsoc_of_rstc_init,
 MACHINE_END
 #endif
 
@@ -81,6 +82,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = prima2_dt_match,
 	.restart	= sirfsoc_restart,
+	.init_early	= sirfsoc_of_rstc_init,
 MACHINE_END
 #endif
 
@@ -100,5 +102,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = marco_dt_match,
 	.restart	= sirfsoc_restart,
+	.init_early	= sirfsoc_of_rstc_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd..65703a4 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -20,6 +20,7 @@ extern struct smp_operations   sirfsoc_smp_ops;
 extern void sirfsoc_secondary_startup(void);
 extern void sirfsoc_cpu_die(unsigned int cpu);
 
+extern void sirfsoc_of_rstc_init(void);
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
 extern void sirfsoc_restart(char, const char *);
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019c..5506425 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -23,7 +23,7 @@ static struct of_device_id rstc_ids[]  = {
 	{},
 };
 
-static int __init sirfsoc_of_rstc_init(void)
+void sirfsoc_of_rstc_init(void)
 {
 	struct device_node *np;
 
@@ -36,10 +36,7 @@ static int __init sirfsoc_of_rstc_init(void)
 		panic("unable to map rstc cpu registers\n");
 
 	of_node_put(np);
-
-	return 0;
 }
-early_initcall(sirfsoc_of_rstc_init);
 
 int sirfsoc_reset_device(struct device *dev)
 {
-- 
1.7.6.5



From srinivas.kandagatla at st.com  Fri May 31 05:45:17 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 31 May 2013 10:45:17 +0100
Subject: [PATCH v1 2/2] ARM:prima2:move postcore_initcalls to init_machine.
In-Reply-To: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
References: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <1369993517-24735-1-git-send-email-srinivas.kandagatla@st.com>

From: Srinivas Kandagatla <srinivas.kandagatla at st.com>

This patch moves all  postcore_initcalls to very first calls in
init_machine. This should achieve the same sequencing as done via
postcore_initcalls.
Without this patch a multi_v7 kernel panics if we boot it on any
non prima2 parts with below log:

Kernel panic - not syncing: unable to find compatible pwrc node in dtb

CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc3-00536-ge2f1bc1 #63
[<c001387c>] (unwind_backtrace+0x0/0xf8) from [<c00111cc>]
(show_stack+0x10/0x14)
[<c00111cc>] (show_stack+0x10/0x14) from [<c0341834>] (panic+0x90/0x1e4)
[<c0341834>] (panic+0x90/0x1e4) from [<c0425784>]
(sirfsoc_of_pwrc_init+0x24/0x58)
[<c0425784>] (sirfsoc_of_pwrc_init+0x24/0x58) from [<c041f854>]
(do_one_initcall+0x90/0x150)
[<c041f854>] (do_one_initcall+0x90/0x150) from [<c041fa10>]
(kernel_init_freeable+0xfc/0x1c4)
[<c041fa10>] (kernel_init_freeable+0xfc/0x1c4) from [<c033d384>]
(kernel_init+0x8/0xe4)
[<c033d384>] (kernel_init+0x8/0xe4) from [<c000ded8>]
(ret_from_fork+0x14/0x3c)
CPU1: stopping
CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.10.0-rc3-00536-ge2f1bc1 #63
[<c001387c>] (unwind_backtrace+0x0/0xf8) from [<c00111cc>]
(show_stack+0x10/0x14)
[<c00111cc>] (show_stack+0x10/0x14) from [<c0012030>]
(handle_IPI+0xf8/0x12c)
[<c0012030>] (handle_IPI+0xf8/0x12c) from [<c0008600>]
(gic_handle_irq+0x54/0x5c)
[<c0008600>] (gic_handle_irq+0x54/0x5c) from [<c000da80>]
(__irq_svc+0x40/0x50)
Exception stack(0xef079fa0 to 0xef079fe8)
9fa0: c0ddd6d8 00000000 000002d2 00000000 ef078000 c04888f5 00000001
c04888f5
9fc0: c045c490 c045c42c c0348f38 00000000 01000000 ef079fe8 c000f018
c000f01c
9fe0: 60000113 ffffffff
[<c000da80>] (__irq_svc+0x40/0x50) from [<c000f01c>]
(arch_cpu_idle+0x28/0x30)
[<c000f01c>] (arch_cpu_idle+0x28/0x30) from [<c0051080>]
(cpu_startup_entry+0x60/0x130)
[<c0051080>] (cpu_startup_entry+0x60/0x130) from [<6033dfc4>]
(0x6033dfc4)

Initially detected when booting Stih415 SOC with multi_v7_defconfig.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
---
 arch/arm/mach-prima2/common.c |    3 +++
 arch/arm/mach-prima2/pm.c     |    6 ++----
 arch/arm/mach-prima2/pm.h     |    2 ++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 9aefcd6..8e27cb7 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -16,6 +16,7 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include "common.h"
+#include "pm.h"
 
 static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
 	{ .compatible = "simple-bus", },
@@ -24,6 +25,8 @@ static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
 
 void __init sirfsoc_mach_init(void)
 {
+	sirfsoc_of_pwrc_init();
+	sirfsoc_memc_init();
 	of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
 }
 
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 9936c18..8850e3b 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -96,7 +96,7 @@ static const struct of_device_id pwrc_ids[] = {
 	{}
 };
 
-static int __init sirfsoc_of_pwrc_init(void)
+int __init sirfsoc_of_pwrc_init(void)
 {
 	struct device_node *np;
 
@@ -116,7 +116,6 @@ static int __init sirfsoc_of_pwrc_init(void)
 
 	return 0;
 }
-postcore_initcall(sirfsoc_of_pwrc_init);
 
 static const struct of_device_id memc_ids[] = {
 	{ .compatible = "sirf,prima2-memc" },
@@ -143,8 +142,7 @@ static struct platform_driver sirfsoc_memc_driver = {
 	},
 };
 
-static int __init sirfsoc_memc_init(void)
+int __init sirfsoc_memc_init(void)
 {
 	return platform_driver_register(&sirfsoc_memc_driver);
 }
-postcore_initcall(sirfsoc_memc_init);
diff --git a/arch/arm/mach-prima2/pm.h b/arch/arm/mach-prima2/pm.h
index bae6d77..b658d66 100644
--- a/arch/arm/mach-prima2/pm.h
+++ b/arch/arm/mach-prima2/pm.h
@@ -23,6 +23,8 @@
 
 #ifndef __ASSEMBLY__
 extern int sirfsoc_finish_suspend(unsigned long);
+extern int __init sirfsoc_of_pwrc_init(void);
+extern int __init sirfsoc_memc_init(void);
 #endif
 
 #endif
-- 
1.7.6.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:01 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:01 +0530
Subject: [PATCH 01/11] pinctrl: single: adopt pinctrl sleep mode management
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-2-git-send-email-gururaja.hebbar@ti.com>

Make pinctrl-single able to handle suspend/resume events and change
hogged pins states accordingly.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Linus Walleij <linus.walleij at linaro.org>
---
:100644 100644 b9fa046... bfd4f6a... M	drivers/pinctrl/pinctrl-single.c
 drivers/pinctrl/pinctrl-single.c |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index b9fa046..bfd4f6a 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1346,6 +1346,29 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
 	return ret;
 }
 
+static int pinctrl_single_suspend(struct platform_device *pdev,
+					pm_message_t state)
+{
+	struct pcs_device *pcs;
+
+	pcs = platform_get_drvdata(pdev);
+	if (!pcs)
+		return -EINVAL;
+
+	return pinctrl_force_sleep(pcs->pctl);
+}
+
+static int pinctrl_single_resume(struct platform_device *pdev)
+{
+	struct pcs_device *pcs;
+
+	pcs = platform_get_drvdata(pdev);
+	if (!pcs)
+		return -EINVAL;
+
+	return pinctrl_force_default(pcs->pctl);
+}
+
 static int pcs_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -1494,6 +1517,10 @@ static struct platform_driver pcs_driver = {
 		.name		= DRIVER_NAME,
 		.of_match_table	= pcs_of_match,
 	},
+#ifdef CONFIG_PM
+	.suspend = pinctrl_single_suspend,
+	.resume = pinctrl_single_resume,
+#endif
 };
 
 module_platform_driver(pcs_driver);
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:03 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:03 +0530
Subject: [PATCH 03/11] Input: gpio_keys: Adopt pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-4-git-send-email-gururaja.hebbar@ti.com>

Amend gpio-keys driver to optionally take a pin control handle and set
the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By Optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
Cc: linux-input at vger.kernel.org
---
:100644 100644 b29ca65... ca615a4... M	drivers/input/keyboard/gpio_keys.c
 drivers/input/keyboard/gpio_keys.c |   47 ++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
index b29ca65..ca615a4 100644
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -28,6 +28,7 @@
 #include <linux/gpio.h>
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/spinlock.h>
 
 struct gpio_button_data {
@@ -47,6 +48,10 @@ struct gpio_keys_drvdata {
 	struct input_dev *input;
 	struct mutex disable_lock;
 	struct gpio_button_data data[0];
+	/* Two optional pin states - default & sleep */
+	struct pinctrl		*pinctrl;
+	struct pinctrl_state	*pins_default;
+	struct pinctrl_state	*pins_sleep;
 };
 
 /*
@@ -709,6 +714,35 @@ static int gpio_keys_probe(struct platform_device *pdev)
 		goto fail1;
 	}
 
+	ddata->pinctrl = devm_pinctrl_get(dev);
+	if (!IS_ERR(ddata->pinctrl)) {
+		ddata->pins_default = pinctrl_lookup_state(ddata->pinctrl,
+						PINCTRL_STATE_DEFAULT);
+		/* enable pins to be muxed in and configured */
+		if (IS_ERR(ddata->pins_default))
+			dev_dbg(dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(ddata->pinctrl,
+						 ddata->pins_default))
+				dev_err(dev,
+					"could not set default pinstate\n");
+
+		ddata->pins_sleep = pinctrl_lookup_state(ddata->pinctrl,
+						PINCTRL_STATE_SLEEP);
+		if (IS_ERR(ddata->pins_sleep))
+			dev_dbg(dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		ddata->pins_default = ERR_PTR(-ENODATA);
+		ddata->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(dev, "pins are not configured from the driver\n");
+	}
+
 	ddata->pdata = pdata;
 	ddata->input = input;
 	mutex_init(&ddata->disable_lock);
@@ -816,6 +850,13 @@ static int gpio_keys_suspend(struct device *dev)
 				enable_irq_wake(bdata->irq);
 		}
 	} else {
+		/* Optionally let pins go into sleep states */
+		if (!IS_ERR(ddata->pins_sleep))
+			if (pinctrl_select_state(ddata->pinctrl,
+						 ddata->pins_sleep))
+				dev_err(dev,
+					"could not set pins to sleep state\n");
+
 		mutex_lock(&input->mutex);
 		if (input->users)
 			gpio_keys_close(input);
@@ -839,6 +880,12 @@ static int gpio_keys_resume(struct device *dev)
 				disable_irq_wake(bdata->irq);
 		}
 	} else {
+		/* Optionaly enable pins to be muxed in and configured */
+		if (!IS_ERR(ddata->pins_default))
+			if (pinctrl_select_state(ddata->pinctrl,
+						 ddata->pins_default))
+				dev_err(dev, "could not set default pins\n");
+
 		mutex_lock(&input->mutex);
 		if (input->users)
 			error = gpio_keys_open(input);
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:00 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:00 +0530
Subject: [PATCH 00/11] drivers: Add Pinctrl PM support
Message-ID: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>

By optionally putting the pins into sleep state in the suspend [or in
runtime_suspend] callback we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

These states can be specified in the DT blob and corresponding driver
can pick these states during probe & set the related values during
idle/suspend.

Not all drivers support/has idle state. Drivers like i2c, spi, mmc has
idle states and hence these drivers are updated to support all the
three states
- default  : during regular operation
- idle : when the module is in idle state
- sleep : when the module is in suspend state

For those drivers which doesn't support/have idle state (at least at
the moment), only default & sleep state is added.

The modification expects DT blob to provide the phandler & the pinctrl
states otherwise it gives a warning message. To remove this warning
message pass default state with null phandler to pinctrl in device node

Kernel Base for the series is
	> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/
	linux-2.6.git
	> tag: v3.10-rc3

Hebbar Gururaja (11):
  pinctrl: single: adopt pinctrl sleep mode management
  leds: leds-gpio: Enhance pinctrl support
  Input: gpio_keys: Adopt pinctrl support
  Input: matrix-keypad: Adopt pinctrl support
  spi: omap2-mcspi: enhance pinctrl support
  usb: musb: dsps: Adopt pinctrl support
  pwm: pwm-tiehrpwm: enhance pinctrl support
  pwm: pwm-tiecap: enhance pinctrl support
  mmc: omap_hsmmc: enhance pinctrl support
  video: da8xx-fb: adopt pinctrl support
  i2c: omap: enhance pinctrl support

 drivers/i2c/busses/i2c-omap.c          |  112 ++++++++++++++++++++++++++++++--
 drivers/input/keyboard/gpio_keys.c     |   47 ++++++++++++++
 drivers/input/keyboard/matrix_keypad.c |   48 ++++++++++++++
 drivers/leds/leds-gpio.c               |   81 +++++++++++++++++++++--
 drivers/mmc/host/omap_hsmmc.c          |   79 ++++++++++++++++++++--
 drivers/pinctrl/pinctrl-single.c       |   27 ++++++++
 drivers/pwm/pwm-tiecap.c               |   48 ++++++++++++--
 drivers/pwm/pwm-tiehrpwm.c             |   49 ++++++++++++--
 drivers/spi/spi-omap2-mcspi.c          |   89 +++++++++++++++++++++++--
 drivers/usb/musb/musb_dsps.c           |   46 +++++++++++++
 drivers/video/da8xx-fb.c               |   48 ++++++++++++++
 11 files changed, 641 insertions(+), 33 deletions(-)

-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:05 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:05 +0530
Subject: [PATCH 05/11] spi: omap2-mcspi: enhance pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-6-git-send-email-gururaja.hebbar@ti.com>

Amend the spi omap controller to optionally take a pin control
handle and set the state of the pins to:

- "default" on boot, resume and before performing an spi transfer
- "idle" after initial default, after resume default, and after each
spi xfer
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

(Changes based on i2c-nomadik.c & spi-pl022.c)

Note:
A .suspend callback is added which simply puts the pins to sleep state.
They are moved to default & idle state by the .resume callback.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Mark Brown <broonie at kernel.org>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: spi-devel-general at lists.sourceforge.net
---
:100644 100644 86d2158... 146dd16... M	drivers/spi/spi-omap2-mcspi.c
 drivers/spi/spi-omap2-mcspi.c |   89 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 84 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 86d2158..146dd16 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -130,6 +130,12 @@ struct omap2_mcspi {
 	struct device		*dev;
 	struct omap2_mcspi_regs ctx;
 	unsigned int		pin_dir:1;
+
+	/* Three pin states - default, idle & sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_idle;
+	struct pinctrl_state		*pins_sleep;
 };
 
 struct omap2_mcspi_cs {
@@ -267,6 +273,12 @@ static int omap2_prepare_transfer(struct spi_master *master)
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 
 	pm_runtime_get_sync(mcspi->dev);
+
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(mcspi->pins_default))
+		if (pinctrl_select_state(mcspi->pinctrl, mcspi->pins_default))
+			dev_err(mcspi->dev, "could not set default pins\n");
+
 	return 0;
 }
 
@@ -274,6 +286,12 @@ static int omap2_unprepare_transfer(struct spi_master *master)
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 
+	/* Optionally let pins go into idle state */
+	if (!IS_ERR(mcspi->pins_idle))
+		if (pinctrl_select_state(mcspi->pinctrl, mcspi->pins_idle))
+			dev_err(mcspi->dev,
+				"could not set pins to idle state\n");
+
 	pm_runtime_mark_last_busy(mcspi->dev);
 	pm_runtime_put_autosuspend(mcspi->dev);
 	return 0;
@@ -1186,7 +1204,6 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
 	static int		bus_num = 1;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
-	struct pinctrl *pinctrl;
 
 	master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 	if (master == NULL) {
@@ -1284,10 +1301,46 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
 	if (status < 0)
 		goto dma_chnl_free;
 
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl))
-		dev_warn(&pdev->dev,
-				"pins are not configured from the driver\n");
+	mcspi->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(mcspi->pinctrl)) {
+		mcspi->pins_default = pinctrl_lookup_state(mcspi->pinctrl,
+							 PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(mcspi->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(mcspi->pinctrl,
+						 mcspi->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pinstate\n");
+
+		mcspi->pins_idle = pinctrl_lookup_state(mcspi->pinctrl,
+						      PINCTRL_STATE_IDLE);
+		if (IS_ERR(mcspi->pins_idle))
+			dev_dbg(&pdev->dev, "could not get idle pinstate\n");
+		else
+			/* If possible, let's idle until the first transfer */
+			if (pinctrl_select_state(mcspi->pinctrl,
+						 mcspi->pins_idle))
+				dev_err(&pdev->dev,
+					"could not set idle pinstate\n");
+
+		mcspi->pins_sleep = pinctrl_lookup_state(mcspi->pinctrl,
+						       PINCTRL_STATE_SLEEP);
+		if (IS_ERR(mcspi->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		mcspi->pins_default = ERR_PTR(-ENODATA);
+		mcspi->pins_idle = ERR_PTR(-ENODATA);
+		mcspi->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev, "did not get pins for i2c error: %li\n",
+			PTR_ERR(mcspi->pinctrl));
+	}
 
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
@@ -1335,6 +1388,18 @@ static int omap2_mcspi_remove(struct platform_device *pdev)
 MODULE_ALIAS("platform:omap2_mcspi");
 
 #ifdef	CONFIG_SUSPEND
+static int omap2_mcspi_suspend(struct device *dev)
+{
+	struct spi_master	*master = dev_get_drvdata(dev);
+	struct omap2_mcspi	*mcspi = spi_master_get_devdata(master);
+
+	if (!IS_ERR(mcspi->pins_sleep))
+		if (pinctrl_select_state(mcspi->pinctrl, mcspi->pins_sleep))
+			dev_err(dev, "could not set pins to sleep state\n");
+
+	return 0;
+}
+
 /*
  * When SPI wake up from off-mode, CS is in activate state. If it was in
  * unactive state when driver was suspend, then force it to unactive state at
@@ -1348,6 +1413,17 @@ static int omap2_mcspi_resume(struct device *dev)
 	struct omap2_mcspi_cs	*cs;
 
 	pm_runtime_get_sync(mcspi->dev);
+
+	/* First go to the default state */
+	if (!IS_ERR(mcspi->pins_default))
+		if (pinctrl_select_state(mcspi->pinctrl, mcspi->pins_default))
+			dev_err(dev, "could not set pins to default state\n");
+
+	/* Then let's idle the pins until the next transfer happens */
+	if (!IS_ERR(mcspi->pins_idle))
+		if (pinctrl_select_state(mcspi->pinctrl, mcspi->pins_idle))
+			dev_err(dev, "could not set pins to idle state\n");
+
 	list_for_each_entry(cs, &ctx->cs, node) {
 		if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
 			/*
@@ -1364,12 +1440,15 @@ static int omap2_mcspi_resume(struct device *dev)
 	pm_runtime_put_autosuspend(mcspi->dev);
 	return 0;
 }
+
 #else
+#define	omap2_mcspi_suspend	NULL
 #define	omap2_mcspi_resume	NULL
 #endif
 
 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
 	.resume = omap2_mcspi_resume,
+	.suspend = omap2_mcspi_suspend,
 	.runtime_resume	= omap_mcspi_runtime_resume,
 };
 
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:04 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:04 +0530
Subject: [PATCH 04/11] Input: matrix-keypad: Adopt pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-5-git-send-email-gururaja.hebbar@ti.com>

Amend matrix-keypad driver to optionally take a pin control handle and
set the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
Cc: linux-input at vger.kernel.org
---
:100644 100644 71d7719... aed43fb... M	drivers/input/keyboard/matrix_keypad.c
 drivers/input/keyboard/matrix_keypad.c |   48 ++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/input/keyboard/matrix_keypad.c b/drivers/input/keyboard/matrix_keypad.c
index 71d7719..aed43fb 100644
--- a/drivers/input/keyboard/matrix_keypad.c
+++ b/drivers/input/keyboard/matrix_keypad.c
@@ -26,6 +26,7 @@
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
 
 struct matrix_keypad {
 	const struct matrix_keypad_platform_data *pdata;
@@ -40,6 +41,10 @@ struct matrix_keypad {
 	bool scan_pending;
 	bool stopped;
 	bool gpio_all_disabled;
+	/* Two optional pin states - default & sleep */
+	struct pinctrl		*pinctrl;
+	struct pinctrl_state	*pins_default;
+	struct pinctrl_state	*pins_sleep;
 };
 
 /*
@@ -280,6 +285,13 @@ static int matrix_keypad_suspend(struct device *dev)
 
 	if (device_may_wakeup(&pdev->dev))
 		matrix_keypad_enable_wakeup(keypad);
+	else
+		/* Optionally let pins go into sleep states */
+		if (!IS_ERR(keypad->pins_sleep))
+			if (pinctrl_select_state(keypad->pinctrl,
+						 keypad->pins_sleep))
+				dev_err(dev,
+					"could not set pins to sleep state\n");
 
 	return 0;
 }
@@ -291,6 +303,12 @@ static int matrix_keypad_resume(struct device *dev)
 
 	if (device_may_wakeup(&pdev->dev))
 		matrix_keypad_disable_wakeup(keypad);
+	else
+		/* Optionaly enable pins to be muxed in and configured */
+		if (!IS_ERR(keypad->pins_default))
+			if (pinctrl_select_state(keypad->pinctrl,
+						 keypad->pins_default))
+				dev_err(dev, "could not set default pins\n");
 
 	matrix_keypad_start(keypad->input_dev);
 
@@ -491,6 +509,36 @@ static int matrix_keypad_probe(struct platform_device *pdev)
 		goto err_free_mem;
 	}
 
+	keypad->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(keypad->pinctrl)) {
+		keypad->pins_default = pinctrl_lookup_state(keypad->pinctrl,
+						PINCTRL_STATE_DEFAULT);
+		/* enable pins to be muxed in and configured */
+		if (IS_ERR(keypad->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(keypad->pinctrl,
+						 keypad->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pins\n");
+
+		keypad->pins_sleep = pinctrl_lookup_state(keypad->pinctrl,
+						PINCTRL_STATE_SLEEP);
+		if (IS_ERR(keypad->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		keypad->pins_default = ERR_PTR(-ENODATA);
+		keypad->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev,
+			"pins are not configured from the driver\n");
+	}
+
 	keypad->input_dev = input_dev;
 	keypad->pdata = pdata;
 	keypad->row_shift = get_count_order(pdata->num_col_gpios);
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:02 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:02 +0530
Subject: [PATCH 02/11] leds: leds-gpio: Enhance pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-3-git-send-email-gururaja.hebbar@ti.com>

Amend leds-gpio driver to optionally take a pin control handle and set
the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Bryan Wu <cooloney at gmail.com>
Cc: Richard Purdie <rpurdie at rpsys.net>
Cc: linux-leds at vger.kernel.org
---
:100644 100644 b02b679... b094e52... M	drivers/leds/leds-gpio.c
 drivers/leds/leds-gpio.c |   81 ++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 75 insertions(+), 6 deletions(-)

diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
index b02b679..b094e52 100644
--- a/drivers/leds/leds-gpio.c
+++ b/drivers/leds/leds-gpio.c
@@ -153,6 +153,10 @@ static void delete_gpio_led(struct gpio_led_data *led)
 
 struct gpio_leds_priv {
 	int num_leds;
+	/* Two optional pin states - default & sleep */
+	struct pinctrl		*pinctrl;
+	struct pinctrl_state	*pins_default;
+	struct pinctrl_state	*pins_sleep;
 	struct gpio_led_data leds[];
 };
 
@@ -162,6 +166,43 @@ static inline int sizeof_gpio_leds_priv(int num_leds)
 		(sizeof(struct gpio_led_data) * num_leds);
 }
 
+/* Use pinctrl API for gpio configuration */
+static void gpio_led_get_pinctrl(struct gpio_leds_priv *priv,
+				struct platform_device *pdev)
+{
+	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(priv->pinctrl)) {
+		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
+						PINCTRL_STATE_DEFAULT);
+		/* enable pins to be muxed in and configured */
+		if (IS_ERR(priv->pins_default))
+			dev_dbg(&pdev->dev,
+				"could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(priv->pinctrl,
+						 priv->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pins\n");
+
+		priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl,
+						PINCTRL_STATE_SLEEP);
+		if (IS_ERR(priv->pins_sleep))
+			dev_dbg(&pdev->dev,
+				"could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		priv->pins_default = ERR_PTR(-ENODATA);
+		priv->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev,
+			"pins are not configured from the driver\n");
+	}
+}
+
 /* Code to create from OpenFirmware platform devices */
 #ifdef CONFIG_OF_GPIO
 static struct gpio_leds_priv *gpio_leds_create_of(struct platform_device *pdev)
@@ -184,6 +225,8 @@ static struct gpio_leds_priv *gpio_leds_create_of(struct platform_device *pdev)
 	if (!priv)
 		return ERR_PTR(-ENOMEM);
 
+	gpio_led_get_pinctrl(priv, pdev);
+
 	for_each_child_of_node(np, child) {
 		struct gpio_led led = {};
 		enum of_gpio_flags flags;
@@ -236,14 +279,8 @@ static int gpio_led_probe(struct platform_device *pdev)
 {
 	struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
 	struct gpio_leds_priv *priv;
-	struct pinctrl *pinctrl;
 	int i, ret = 0;
 
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl))
-		dev_warn(&pdev->dev,
-			"pins are not configured from the driver\n");
-
 	if (pdata && pdata->num_leds) {
 		priv = devm_kzalloc(&pdev->dev,
 				sizeof_gpio_leds_priv(pdata->num_leds),
@@ -251,6 +288,8 @@ static int gpio_led_probe(struct platform_device *pdev)
 		if (!priv)
 			return -ENOMEM;
 
+		gpio_led_get_pinctrl(priv, pdev);
+
 		priv->num_leds = pdata->num_leds;
 		for (i = 0; i < priv->num_leds; i++) {
 			ret = create_gpio_led(&pdata->leds[i],
@@ -287,6 +326,32 @@ static int gpio_led_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static int gpio_led_suspend(struct platform_device *pdev,
+					pm_message_t state)
+{
+	struct gpio_leds_priv *priv = platform_get_drvdata(pdev);
+
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(priv->pins_sleep))
+		if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep))
+			dev_err(&pdev->dev,
+				"could not set pins to sleep state\n");
+
+	return 0;
+}
+
+static int gpio_led_resume(struct platform_device *pdev)
+{
+	struct gpio_leds_priv *priv = platform_get_drvdata(pdev);
+
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(priv->pins_default))
+		if (pinctrl_select_state(priv->pinctrl, priv->pins_default))
+			dev_err(&pdev->dev, "could not set default pins\n");
+
+	return 0;
+}
+
 static struct platform_driver gpio_led_driver = {
 	.probe		= gpio_led_probe,
 	.remove		= gpio_led_remove,
@@ -295,6 +360,10 @@ static struct platform_driver gpio_led_driver = {
 		.owner	= THIS_MODULE,
 		.of_match_table = of_match_ptr(of_gpio_leds_match),
 	},
+#ifdef CONFIG_PM
+	.suspend = gpio_led_suspend,
+	.resume = gpio_led_resume,
+#endif
 };
 
 module_platform_driver(gpio_led_driver);
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:07 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:07 +0530
Subject: [PATCH 07/11] pwm: pwm-tiehrpwm: enhance pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-8-git-send-email-gururaja.hebbar@ti.com>

Amend the ti ehrpwm controller to optionally take a pin control handle
and set the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Todo:
        - if an idle state is available for pins, add support for it.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Philip, Avinash <avinashphilip at ti.com>
---
:100644 100644 48a485c... ed55460ae. M	drivers/pwm/pwm-tiehrpwm.c
 drivers/pwm/pwm-tiehrpwm.c |   49 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 44 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 48a485c..ed55460ae 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -132,6 +132,11 @@ struct ehrpwm_pwm_chip {
 	enum pwm_polarity polarity[NUM_PWM_CHANNEL];
 	struct	clk	*tbclk;
 	struct ehrpwm_context ctx;
+
+	/* two pin states - default, sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_sleep;
 };
 
 static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
@@ -439,11 +444,6 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct ehrpwm_pwm_chip *pc;
 	u16 status;
-	struct pinctrl *pinctrl;
-
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl))
-		dev_warn(&pdev->dev, "unable to select pin group\n");
 
 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 	if (!pc) {
@@ -451,6 +451,34 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
+	pc->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(pc->pinctrl)) {
+		pc->pins_default = pinctrl_lookup_state(pc->pinctrl,
+							 PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(pc->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(pc->pinctrl, pc->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pinstate\n");
+
+		pc->pins_sleep = pinctrl_lookup_state(pc->pinctrl,
+						       PINCTRL_STATE_SLEEP);
+		if (IS_ERR(pc->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		pc->pins_default = ERR_PTR(-ENODATA);
+		pc->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev, "did not get pins for i2c error: %li\n",
+			PTR_ERR(pc->pinctrl));
+	}
+
 	clk = devm_clk_get(&pdev->dev, "fck");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -570,6 +598,12 @@ static int ehrpwm_pwm_suspend(struct device *dev)
 		/* Disable explicitly if PWM is running */
 		pm_runtime_put_sync(dev);
 	}
+
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(pc->pins_sleep))
+		if (pinctrl_select_state(pc->pinctrl, pc->pins_sleep))
+			dev_err(dev, "could not set pins to sleep state\n");
+
 	return 0;
 }
 
@@ -578,6 +612,11 @@ static int ehrpwm_pwm_resume(struct device *dev)
 	struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
 	int i;
 
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(pc->pins_default))
+		if (pinctrl_select_state(pc->pinctrl, pc->pins_default))
+			dev_err(dev, "could not set default pins\n");
+
 	for (i = 0; i < pc->chip.npwm; i++) {
 		struct pwm_device *pwm = &pc->chip.pwms[i];
 
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:06 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:06 +0530
Subject: [PATCH 06/11] usb: musb: dsps: Adopt pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-7-git-send-email-gururaja.hebbar@ti.com>

Amend the musb controller to optionally take a pin control handle and
set the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Todo:
        - if an idle state is available for pins, add support for it.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: linux-usb at vger.kernel.org
---
:100644 100644 e1b661d... a9580fe... M	drivers/usb/musb/musb_dsps.c
 drivers/usb/musb/musb_dsps.c |   46 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
index e1b661d..a9580fe 100644
--- a/drivers/usb/musb/musb_dsps.c
+++ b/drivers/usb/musb/musb_dsps.c
@@ -39,6 +39,7 @@
 #include <linux/usb/nop-usb-xceiv.h>
 #include <linux/platform_data/usb-omap.h>
 #include <linux/sizes.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -124,6 +125,11 @@ struct dsps_glue {
 	struct timer_list timer[2];	/* otg_workaround timer */
 	unsigned long last_timer[2];    /* last timer data for each instance */
 	u32 __iomem *usb_ctrl[2];
+
+	/* two pin states - default, sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_sleep;
 };
 
 #define	DSPS_AM33XX_CONTROL_MODULE_PHYS_0	0x44e10620
@@ -636,6 +642,36 @@ static int dsps_probe(struct platform_device *pdev)
 		ret = -ENOMEM;
 		goto err1;
 	}
+
+	glue->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(glue->pinctrl)) {
+		glue->pins_default = pinctrl_lookup_state(glue->pinctrl,
+							 PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(glue->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(glue->pinctrl,
+						 glue->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pinstate\n");
+
+		glue->pins_sleep = pinctrl_lookup_state(glue->pinctrl,
+						       PINCTRL_STATE_SLEEP);
+		if (IS_ERR(glue->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		glue->pins_default = ERR_PTR(-ENODATA);
+		glue->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev, "did not get pins for i2c error: %li\n",
+			PTR_ERR(glue->pinctrl));
+	}
+
 	platform_set_drvdata(pdev, glue);
 
 	/* enable the usbss clocks */
@@ -700,6 +736,11 @@ static int dsps_suspend(struct device *dev)
 	for (i = 0; i < wrp->instances; i++)
 		musb_dsps_phy_control(glue, i, 0);
 
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(glue->pins_sleep))
+		if (pinctrl_select_state(glue->pinctrl, glue->pins_sleep))
+			dev_err(dev, "could not set pins to sleep state\n");
+
 	return 0;
 }
 
@@ -710,6 +751,11 @@ static int dsps_resume(struct device *dev)
 	const struct dsps_musb_wrapper *wrp = glue->wrp;
 	int i;
 
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(glue->pins_default))
+		if (pinctrl_select_state(glue->pinctrl, glue->pins_default))
+			dev_err(dev, "could not set default pins\n");
+
 	for (i = 0; i < wrp->instances; i++)
 		musb_dsps_phy_control(glue, i, 1);
 
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:08 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:08 +0530
Subject: [PATCH 08/11] pwm: pwm-tiecap: enhance pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-9-git-send-email-gururaja.hebbar@ti.com>

Amend TI ecap controller to optionally take a pin control handle and
set the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Todo:
        - if an idle state is available for pins, add support for it.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: Philip, Avinash <avinashphilip at ti.com>
---
:100644 100644 72ca42d... d02769d... M	drivers/pwm/pwm-tiecap.c
 drivers/pwm/pwm-tiecap.c |   48 +++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 43 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
index 72ca42d..d02769d 100644
--- a/drivers/pwm/pwm-tiecap.c
+++ b/drivers/pwm/pwm-tiecap.c
@@ -52,6 +52,11 @@ struct ecap_pwm_chip {
 	unsigned int	clk_rate;
 	void __iomem	*mmio_base;
 	struct ecap_context ctx;
+
+	/* two pin states - default, sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_sleep;
 };
 
 static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
@@ -208,11 +213,6 @@ static int ecap_pwm_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct ecap_pwm_chip *pc;
 	u16 status;
-	struct pinctrl *pinctrl;
-
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl))
-		dev_warn(&pdev->dev, "unable to select pin group\n");
 
 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 	if (!pc) {
@@ -220,6 +220,34 @@ static int ecap_pwm_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
+	pc->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(pc->pinctrl)) {
+		pc->pins_default = pinctrl_lookup_state(pc->pinctrl,
+							 PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(pc->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(pc->pinctrl, pc->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pinstate\n");
+
+		pc->pins_sleep = pinctrl_lookup_state(pc->pinctrl,
+						       PINCTRL_STATE_SLEEP);
+		if (IS_ERR(pc->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		pc->pins_default = ERR_PTR(-ENODATA);
+		pc->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev, "did not get pins for i2c error: %li\n",
+			PTR_ERR(pc->pinctrl));
+	}
+
 	clk = devm_clk_get(&pdev->dev, "fck");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -318,6 +346,11 @@ static int ecap_pwm_suspend(struct device *dev)
 	if (test_bit(PWMF_ENABLED, &pwm->flags))
 		pm_runtime_put_sync(dev);
 
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(pc->pins_sleep))
+		if (pinctrl_select_state(pc->pinctrl, pc->pins_sleep))
+			dev_err(dev, "could not set pins to sleep state\n");
+
 	return 0;
 }
 
@@ -326,6 +359,11 @@ static int ecap_pwm_resume(struct device *dev)
 	struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
 	struct pwm_device *pwm = pc->chip.pwms;
 
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(pc->pins_default))
+		if (pinctrl_select_state(pc->pinctrl, pc->pins_default))
+			dev_err(dev, "could not set default pins\n");
+
 	/* Enable explicitly if PWM was running */
 	if (test_bit(PWMF_ENABLED, &pwm->flags))
 		pm_runtime_get_sync(dev);
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:09 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:09 +0530
Subject: [PATCH 09/11] mmc: omap_hsmmc: enhance pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-10-git-send-email-gururaja.hebbar@ti.com>

Amend the hsmmc controller to optionally take a pin control handle and
set the state of the pins to:

- "default" on boot, resume and before performing a mmc transfer
- "idle" after initial default, after resume default, and after each
mmc/sd card access
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Balaji T K <balajitk at ti.com>
Cc: Chris Ball <cjb at laptop.org>
Cc: linux-mmc at vger.kernel.org
Cc: linux-omap at vger.kernel.org
---
:100644 100644 6e44025... a2d69aa... M	drivers/mmc/host/omap_hsmmc.c
 drivers/mmc/host/omap_hsmmc.c |   79 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 74 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 6e44025..a2d69aa 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -183,6 +183,12 @@ struct omap_hsmmc_host {
 	struct omap_hsmmc_next	next_data;
 
 	struct	omap_mmc_platform_data	*pdata;
+
+	/* Three pin states - default, idle & sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_idle;
+	struct pinctrl_state		*pins_sleep;
 };
 
 static int omap_hsmmc_card_detect(struct device *dev, int slot)
@@ -1775,7 +1781,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 	const struct of_device_id *match;
 	dma_cap_mask_t mask;
 	unsigned tx_req, rx_req;
-	struct pinctrl *pinctrl;
 
 	match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
 	if (match) {
@@ -1982,10 +1987,46 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
 	omap_hsmmc_disable_irq(host);
 
-	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(pinctrl))
-		dev_warn(&pdev->dev,
-			"pins are not configured from the driver\n");
+	host->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(host->pinctrl)) {
+		host->pins_default = pinctrl_lookup_state(host->pinctrl,
+							PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(host->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(host->pinctrl,
+						 host->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pinstate\n");
+
+		host->pins_idle = pinctrl_lookup_state(host->pinctrl,
+							PINCTRL_STATE_IDLE);
+		if (IS_ERR(host->pins_idle))
+			dev_dbg(&pdev->dev, "could not get idle pinstate\n");
+		else
+			/* If possible, let's idle until the first transfer */
+			if (pinctrl_select_state(host->pinctrl,
+						 host->pins_idle))
+				dev_err(&pdev->dev,
+					"could not set idle pinstate\n");
+
+		host->pins_sleep = pinctrl_lookup_state(host->pinctrl,
+							PINCTRL_STATE_SLEEP);
+		if (IS_ERR(host->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		host->pins_default = ERR_PTR(-ENODATA);
+		host->pins_idle = ERR_PTR(-ENODATA);
+		host->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev, "did not get pins for mmc error: %li\n",
+			PTR_ERR(host->pinctrl));
+	}
 
 	omap_hsmmc_protect_card(host);
 
@@ -2135,6 +2176,12 @@ static int omap_hsmmc_suspend(struct device *dev)
 		clk_disable_unprepare(host->dbclk);
 err:
 	pm_runtime_put_sync(host->dev);
+
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(host->pins_sleep))
+		if (pinctrl_select_state(host->pinctrl, host->pins_sleep))
+			dev_err(dev, "could not set pins to sleep state\n");
+
 	return ret;
 }
 
@@ -2152,6 +2199,16 @@ static int omap_hsmmc_resume(struct device *dev)
 
 	pm_runtime_get_sync(host->dev);
 
+	/* First go to the default state */
+	if (!IS_ERR(host->pins_default))
+		if (pinctrl_select_state(host->pinctrl, host->pins_default))
+			dev_err(host->dev, "could not set pins to default state\n");
+
+	/* Then let's idle the pins until the next transfer happens */
+	if (!IS_ERR(host->pins_idle))
+		if (pinctrl_select_state(host->pinctrl, host->pins_idle))
+			dev_err(host->dev, "couldn't set pins to idle state\n");
+
 	if (host->dbclk)
 		clk_prepare_enable(host->dbclk);
 
@@ -2185,6 +2242,12 @@ static int omap_hsmmc_runtime_suspend(struct device *dev)
 
 	host = platform_get_drvdata(to_platform_device(dev));
 	omap_hsmmc_context_save(host);
+
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(host->pins_idle))
+		if (pinctrl_select_state(host->pinctrl, host->pins_idle))
+			dev_err(dev, "could not set pins to idle state\n");
+
 	dev_dbg(dev, "disabled\n");
 
 	return 0;
@@ -2195,6 +2258,12 @@ static int omap_hsmmc_runtime_resume(struct device *dev)
 	struct omap_hsmmc_host *host;
 
 	host = platform_get_drvdata(to_platform_device(dev));
+
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(host->pins_default))
+		if (pinctrl_select_state(host->pinctrl, host->pins_default))
+			dev_err(host->dev, "could not set default pins\n");
+
 	omap_hsmmc_context_restore(host);
 	dev_dbg(dev, "enabled\n");
 
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:10 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:10 +0530
Subject: [PATCH 10/11] video: da8xx-fb: adopt pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-11-git-send-email-gururaja.hebbar@ti.com>

Amend the da8xx-fb controller to optionally take a pin control handle
and set the state of the pins to:

- "default" on boot, resume
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Todo:
        - if an idle state is available for pins, add support for it.

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
Cc: linux-fbdev at vger.kernel.org
---
:100644 100644 0810939... 10c8036... M	drivers/video/da8xx-fb.c
 drivers/video/da8xx-fb.c |   48 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 0810939..10c8036 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -36,6 +36,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/lcm.h>
+#include <linux/pinctrl/consumer.h>
 #include <video/da8xx-fb.h>
 #include <asm/div64.h>
 
@@ -182,6 +183,11 @@ struct da8xx_fb_par {
 #endif
 	void (*panel_power_ctrl)(int);
 	u32 pseudo_palette[16];
+
+	/* two pin states - default, sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_sleep;
 };
 
 /* Variable Screen Information */
@@ -1306,6 +1312,36 @@ static int fb_probe(struct platform_device *device)
 	par->lcd_fck_rate = clk_get_rate(fb_clk);
 #endif
 	par->pxl_clk = lcdc_info->pixclock;
+
+	par->pinctrl = devm_pinctrl_get(&device->dev);
+	if (!IS_ERR(par->pinctrl)) {
+		par->pins_default = pinctrl_lookup_state(par->pinctrl,
+							 PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(par->pins_default))
+			dev_dbg(&device->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(par->pinctrl,
+						 par->pins_default))
+				dev_err(&device->dev,
+					"could not set default pinstate\n");
+
+		par->pins_sleep = pinctrl_lookup_state(par->pinctrl,
+						       PINCTRL_STATE_SLEEP);
+		if (IS_ERR(par->pins_sleep))
+			dev_dbg(&device->dev, "could not get sleep pinstate\n");
+	} else {
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		par->pins_default = ERR_PTR(-ENODATA);
+		par->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&device->dev, "did not get pins for lcd error: %li\n",
+			PTR_ERR(par->pinctrl));
+	}
+
 	if (fb_pdata->panel_power_ctrl) {
 		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
 		par->panel_power_ctrl(1);
@@ -1551,6 +1587,12 @@ static int fb_suspend(struct platform_device *dev, pm_message_t state)
 	pm_runtime_put_sync(&dev->dev);
 	console_unlock();
 
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(par->pins_sleep))
+		if (pinctrl_select_state(par->pinctrl, par->pins_sleep))
+			dev_err(&dev->dev,
+				"could not set pins to sleep state\n");
+
 	return 0;
 }
 static int fb_resume(struct platform_device *dev)
@@ -1560,6 +1602,12 @@ static int fb_resume(struct platform_device *dev)
 
 	console_lock();
 	pm_runtime_get_sync(&dev->dev);
+
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(par->pins_default))
+		if (pinctrl_select_state(par->pinctrl, par->pins_default))
+			dev_err(&dev->dev, "could not set default pins\n");
+
 	lcd_context_restore();
 	if (par->blank == FB_BLANK_UNBLANK) {
 		lcd_enable_raster();
-- 
1.7.9.5



From gururaja.hebbar at ti.com  Fri May 31 06:13:11 2013
From: gururaja.hebbar at ti.com (Hebbar Gururaja)
Date: Fri, 31 May 2013 15:43:11 +0530
Subject: [PATCH 11/11] i2c: omap: enhance pinctrl support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>

Amend the I2C omap pin controller to optionally take a pin control
handle and set the state of the pins to:

- "default" on boot, resume and before performing an i2c transfer
- "idle" after initial default, after resume default, and after each
i2c xfer
- "sleep" on suspend()

By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.

Note:
A .suspend & .resume callback is added which simply puts the pins to sleep
state upon suspend & are moved to default & idle state upon resume.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

(Changes based on i2c-nomadik.c)

Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Wolfram Sang <wsa at the-dreams.de>
Cc: linux-omap at vger.kernel.org
Cc: linux-i2c at vger.kernel.org
---
:100644 100644 e02f9e3... 588ba28... M	drivers/i2c/busses/i2c-omap.c
 drivers/i2c/busses/i2c-omap.c |  112 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 105 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..588ba28 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -214,7 +214,11 @@ struct omap_i2c_dev {
 	u16			westate;
 	u16			errata;
 
-	struct pinctrl		*pins;
+	/* Three pin states - default, idle & sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_idle;
+	struct pinctrl_state		*pins_sleep;
 };
 
 static const u8 reg_map_ip_v1[] = {
@@ -641,6 +645,11 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 	if (IS_ERR_VALUE(r))
 		goto out;
 
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(dev->pins_default))
+		if (pinctrl_select_state(dev->pinctrl, dev->pins_default))
+			dev_err(dev->dev, "could not set default pins\n");
+
 	r = omap_i2c_wait_for_bb(dev);
 	if (r < 0)
 		goto out;
@@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 out:
 	pm_runtime_mark_last_busy(dev->dev);
+
 	pm_runtime_put_autosuspend(dev->dev);
+	/* Optionally let pins go into idle state */
+	if (!IS_ERR(dev->pins_idle))
+		if (pinctrl_select_state(dev->pinctrl, dev->pins_idle))
+			dev_err(dev->dev, "could not set pins to idle state\n");
+
 	return r;
 }
 
@@ -1123,14 +1138,47 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
 	}
 
-	dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
-	if (IS_ERR(dev->pins)) {
-		if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
+	dev->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (!IS_ERR(dev->pinctrl)) {
+		dev->pins_default = pinctrl_lookup_state(dev->pinctrl,
+							 PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(dev->pins_default))
+			dev_dbg(&pdev->dev, "could not get default pinstate\n");
+		else
+			if (pinctrl_select_state(dev->pinctrl,
+						 dev->pins_default))
+				dev_err(&pdev->dev,
+					"could not set default pinstate\n");
+
+		dev->pins_idle = pinctrl_lookup_state(dev->pinctrl,
+						      PINCTRL_STATE_IDLE);
+		if (IS_ERR(dev->pins_idle))
+			dev_dbg(&pdev->dev, "could not get idle pinstate\n");
+		else
+			/* If possible, let's idle until the first transfer */
+			if (pinctrl_select_state(dev->pinctrl, dev->pins_idle))
+				dev_err(&pdev->dev,
+					"could not set idle pinstate\n");
+
+		dev->pins_sleep = pinctrl_lookup_state(dev->pinctrl,
+						       PINCTRL_STATE_SLEEP);
+		if (IS_ERR(dev->pins_sleep))
+			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
+	} else {
+		if (PTR_ERR(dev->pinctrl) == -EPROBE_DEFER)
 			return -EPROBE_DEFER;
 
-		dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
-			 PTR_ERR(dev->pins));
-		dev->pins = NULL;
+		/*
+		* Since we continue even when pinctrl node is not found,
+		* Invalidate pins as not available. This is to make sure that
+		* IS_ERR(pins_xxx) results in failure when used.
+		*/
+		dev->pins_default = ERR_PTR(-ENODATA);
+		dev->pins_idle = ERR_PTR(-ENODATA);
+		dev->pins_sleep = ERR_PTR(-ENODATA);
+
+		dev_dbg(&pdev->dev, "did not get pins for i2c error: %li\n",
+			PTR_ERR(dev->pinctrl));
 	}
 
 	dev->dev = &pdev->dev;
@@ -1300,6 +1348,10 @@ static int omap_i2c_runtime_suspend(struct device *dev)
 		omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
 	}
 
+	if (!IS_ERR(_dev->pins_idle))
+		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_idle))
+			dev_err(dev, "could not set pins to idle state\n");
+
 	return 0;
 }
 
@@ -1311,13 +1363,59 @@ static int omap_i2c_runtime_resume(struct device *dev)
 	if (!_dev->regs)
 		return 0;
 
+	/* Optionally place the pins to the default state */
+	if (!IS_ERR(_dev->pins_default))
+		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_default))
+			dev_err(dev, "could not set pins to default state\n");
+
 	__omap_i2c_init(_dev);
 
 	return 0;
 }
 #endif /* CONFIG_PM_RUNTIME */
 
+#ifdef CONFIG_PM_SLEEP
+static int omap_i2c_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
+
+	pm_runtime_get_sync(dev);
+	if (omap_i2c_wait_for_bb(_dev) < 0) {
+		pm_runtime_put_sync(dev);
+		return -EBUSY;
+	}
+	pm_runtime_put_sync(dev);
+
+	if (!IS_ERR(_dev->pins_sleep))
+		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_sleep))
+			dev_err(dev, "could not set pins to sleep state\n");
+
+	return 0;
+}
+
+static int omap_i2c_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
+
+	/* First go to the default state */
+	if (!IS_ERR(_dev->pins_default))
+		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_default))
+			dev_err(dev, "could not set pins to default state\n");
+
+	/* Then let's idle the pins until the next transfer happens */
+	if (!IS_ERR(_dev->pins_idle))
+		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_idle))
+			dev_err(dev, "could not set pins to idle state\n");
+
+	return 0;
+}
+#endif
+
+
 static struct dev_pm_ops omap_i2c_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(omap_i2c_suspend, omap_i2c_resume)
 	SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
 			   omap_i2c_runtime_resume, NULL)
 };
-- 
1.7.9.5



From c.hemp at phytec.de  Fri May 31 05:56:54 2013
From: c.hemp at phytec.de (Christian Hemp)
Date: Fri, 31 May 2013 11:56:54 +0200
Subject: [PATCH 2/2] ARM: dts: Phytec phyFLEX-i.MX6 support
In-Reply-To: <20130530063124.GB2602@S2101-09.ap.freescale.net>
References: <1369861609-30408-1-git-send-email-c.hemp@phytec.de>
 <1369861609-30408-3-git-send-email-c.hemp@phytec.de>
 <20130530063124.GB2602@S2101-09.ap.freescale.net>
Message-ID: <1369994214.2535.33.camel@lws-hemp>

Hello Shawn,

Am Donnerstag, den 30.05.2013, 14:31 +0800 schrieb Shawn Guo:
> On Wed, May 29, 2013 at 11:06:49PM +0200, Christian Hemp wrote:
> > Add support for Phytec phyFLEX-i.MX6 board
> 
> It's a board supporting all i.MX6 family?

At the moment only i.MX6q but this will change.

>   Can we name it using SoC than
> family name?

Okay. 


Christian

> > 
> > Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> > ---
> >  arch/arm/boot/dts/Makefile                 |    1 +
> >  arch/arm/boot/dts/imx6q-phytec-phyflex.dts |   76 ++++++++++++++++++++++++++++
> >  2 files changed, 77 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx6q-phytec-phyflex.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 4c58951..6ffdaa1 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
> >  	imx6dl-sabresd.dtb \
> >  	imx6dl-wandboard.dtb \
> >  	imx6q-arm2.dtb \
> > +	imx6q-phytec-phyflex.dtb \
> >  	imx6q-sabreauto.dtb \
> >  	imx6q-sabrelite.dtb \
> >  	imx6q-sabresd.dtb \
> > diff --git a/arch/arm/boot/dts/imx6q-phytec-phyflex.dts b/arch/arm/boot/dts/imx6q-phytec-phyflex.dts
> > new file mode 100644
> > index 0000000..9690691
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6q-phytec-phyflex.dts
> > @@ -0,0 +1,76 @@
> > +/*
> > + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +#include "imx6q.dtsi"
> > +
> > +/ {
> > +	model = "Phytec phyFLEX-i.MX6";
> > +	compatible = "phytec,phyflex-imx6", "fsl,imx6q";
> 
> ditto
> 
> Shawn
> 
> > +
> > +	memory {
> > +		reg = <0x10000000 0x80000000>;
> > +	};
> > +};
> > +
> > +&iomuxc {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_hog>;
> > +
> > +	hog {
> > +                pinctrl_hog: hoggrp {
> > +                        fsl,pins = <
> > +				MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
> > +			>;
> > +		};
> > +	};
> > +
> > +	phyflex {
> > +		pinctrl_usdhc3_phyflex: usdhc3grp-phyflex {
> > +			fsl,pins = <
> > +				MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
> > +				MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
> > +			>;
> > +		};
> > +	};
> > +};
> > +
> > +&fec {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_enet_3>;
> > +	phy-mode = "rgmii";
> > +	phy-reset-gpios = <&gpio3 23 0>;
> > +	status = "okay";
> > +};
> > +
> > +&uart4 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart4_1>;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_usdhc2_2>;
> > +	cd-gpios = <&gpio1 4 0>;
> > +	wp-gpios = <&gpio1 2 0>;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc3 {
> > +        pinctrl-names = "default";
> > +        pinctrl-0 = <&pinctrl_usdhc3_2
> > +		     &pinctrl_usdhc3_phyflex>;
> > +        cd-gpios = <&gpio1 27 0>;
> > +        wp-gpios = <&gpio1 29 0>;
> > +        status = "okay";
> > +};
> > +
> > -- 
> > 1.7.9.5
> > 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From arnd at arndb.de  Fri May 31 06:31:41 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 12:31:41 +0200
Subject: [PATCH 02/39] ARM: u300: device tree support for the timer
In-Reply-To: <1369991954-17406-3-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-3-git-send-email-linus.walleij@stericsson.com>
Message-ID: <7742928.6bJiIVUE0X@wuerfel>

On Friday 31 May 2013 11:18:37 Linus Walleij wrote:
> +
> +
> +void __init u300_timer_init()
> +{
> +       u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
> +}
> +
> +#ifdef CONFIG_OF
> +
> +static void __init u300_timer_init_of(struct device_node *np)
> +{
> +       void __iomem *base;
> +       struct resource irq_res;
> +       int irq;
> +
> +       base = of_iomap(np, 0);
> +       /* Get the IRQ for the GP1 timer */
> +       irq = of_irq_to_resource(np, 2, &irq_res);
> +       u300_timer_setup(base, irq);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
> +                      u300_timer_init_of);
> +
> +#endif

You should not need the CONFIG_OF #ifdef, since the CLOCKSOURCE_OF_DECLARE
macro is designed to let the function get dropped by the compiler when
that is not set.

You might want a CONFIG_ATAGS check for the other function though.

> diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
> index d34287b..7766dfa 100644
> --- a/arch/arm/mach-u300/timer.h
> +++ b/arch/arm/mach-u300/timer.h
> @@ -1 +1,2 @@
>  extern void u300_timer_init(void);
> +
> 

You probably didn't mean to include this newline.

	Arnd


From catalin.marinas at arm.com  Fri May 31 06:36:17 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 11:36:17 +0100
Subject: [PATCH RFC 1/6] [HACK!] arm64/xen: create links to arch/arm
 include files and Xen code
In-Reply-To: <1369930713-6063-1-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-1-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20130531103617.GA18045@localhost.cambridge.arm.com>

On Thu, May 30, 2013 at 05:18:28PM +0100, Stefano Stabellini wrote:
> Most of Xen support for ARM is common between ARMv7 and ARMv8.
> Create links to the code under arch/arm (bleah).
> 
> Other, probably better alternatives:
> 
> - move the code to a different location, maybe the header files to
> include/xen/arm and the code to drivers/xen/arm (still pretty ugly)?
> 
> - create a copy of the code to arch/arm64 (even worse);

KVM handles this in the Makefile by referencing back to arch/arm or even
the generic kvm directory. I think that's the 'cleanest' ;)

-- 
Catalin


From arnd at arndb.de  Fri May 31 06:37:12 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 12:37:12 +0200
Subject: [PATCH 12/39] ARM: u300: set up board power from device tree
In-Reply-To: <1369991954-17406-13-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-13-git-send-email-linus.walleij@stericsson.com>
Message-ID: <6621177.ZgrPQ48FXE@wuerfel>

On Friday 31 May 2013 11:18:47 Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This adds support for setting up the board power from the
> device tree on the U300. We use a board-specific node in the
> device tree for the S365 board and bind a regulator for the
> board power to this node.
> 
> Cc: Mark Brown <broonie at kernel.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

This is fairly unusual, I think I've never seen a platform driver
registered for a board.  Is that the intended method for hogging
a regulator?

	Arnd


From dirk.behme at de.bosch.com  Fri May 31 06:37:57 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 31 May 2013 12:37:57 +0200
Subject: [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes.
In-Reply-To: <1370034115-24006-1-git-send-email-b20788@freescale.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
Message-ID: <51A87D85.9000802@de.bosch.com>

On 31.05.2013 23:01, Anson Huang wrote:
> Some clock gates are useful when we try to disable them
> to save power, so we need to add these useful clock gate
> into clock tree.
>
> Signed-off-by: Anson Huang <b20788 at freescale.com>
> ---
>   .../devicetree/bindings/clock/imx6q-clock.txt      |   13 +++++++++++++
>   arch/arm/mach-imx/clk-imx6q.c                      |   17 ++++++++++++++++-
>   2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> index 6deb6fd..df68f99 100644
> --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> @@ -208,6 +208,19 @@ clocks and IDs.
>   	pll4_post_div		193
>   	pll5_post_div		194
>   	pll5_video_div		195
> +	aips_tz1		196
> +	aips_tz2		197
> +	caam_mem		198
> +	caam_aclk		199
> +	caam_ipg		200
> +	tzasc1			201
> +	tzasc2			202
> +	vdoa			203
> +	mmdc_ch0_ipg		204
> +	mmdc_ch1_ipg		205
> +	mx6fast1		206
> +	per2_main		207
> +	emi_slow		208
>
>   Examples:
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index dda9a2b..dfb77c1 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -238,7 +238,9 @@ enum mx6q_clks {
>   	pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
>   	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
>   	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
> -	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
> +	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1,
> +	aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg,
> +	mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max
>   };
>
>   static struct clk *clk[clk_max];
> @@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void)
>   	clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
>
>   	/*                                name             parent_name          reg         shift */
> +	clk[aips_tz1]     = imx_clk_gate2("aips_tz1",      "ahb",               base + 0x68, 0);
> +	clk[aips_tz2]     = imx_clk_gate2("aips_tz2",      "ahb",               base + 0x68, 2);
>   	clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
>   	clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
> +	clk[caam_mem]     = imx_clk_gate2("caam_mem",      "ahb",               base + 0x68, 8);
> +	clk[caam_aclk]    = imx_clk_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
> +	clk[caam_ipg]     = imx_clk_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
>   	clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
>   	clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
>   	clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
> @@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void)
>   	clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
>   	clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
>   	clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
> +	clk[tzasc1]       = imx_clk_gate2("tzasc1",        "mmdc_ch0_axi_podf", base + 0x70, 22);
> +	clk[tzasc2]       = imx_clk_gate2("tzasc2",        "mmdc_ch0_axi_podf", base + 0x70, 24);
> +	clk[vdoa]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
>   	clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
>   	clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
>   	clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
> @@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void)
>   	clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
>   	clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
>   	clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
> +	clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg",  "ipg",               base + 0x74, 24);
> +	clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg",  "ipg",               base + 0x74, 26);
>   	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
>   	clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
>   	clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
> +	clk[mx6fast1]     = imx_clk_gate2("mx6fast1",      "ahb",               base + 0x78, 8);
>   	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
> +	clk[per2_main]    = imx_clk_gate2("per2_main",     "ahb",               base + 0x78, 14);
>   	clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
>   	clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
>   	clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
> @@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void)
>   	clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
>   	clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
>   	clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
> +	clk[emi_slow]     = imx_clk_gate2("emi_slow",      "emi_slow_podf",     base + 0x80, 10);
>   	clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
>   	clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
>   	clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);

I think we have the emi_slow already:

https://git.linaro.org/gitweb?p=people/shawnguo/linux-2.6.git;a=commitdiff;h=5e569c675297733dec9f5b65aed3fe694c6e6975

Best regards

Dirk












From catalin.marinas at arm.com  Fri May 31 06:43:03 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 11:43:03 +0100
Subject: [PATCH RFC 2/6] arm64/xen: arm/xen header changes to compile on
 arm64
In-Reply-To: <1369930713-6063-2-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-2-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20130531104303.GB18045@localhost.cambridge.arm.com>

On Thu, May 30, 2013 at 05:18:29PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/xen/events.h |    4 ++++
>  arch/arm/include/asm/xen/page.h   |    2 ++
>  2 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
> index 8b1f37b..12e4e0b 100644
> --- a/arch/arm/include/asm/xen/events.h
> +++ b/arch/arm/include/asm/xen/events.h
> @@ -13,7 +13,11 @@ enum ipi_vector {
>  
>  static inline int xen_irqs_disabled(struct pt_regs *regs)
>  {
> +#ifdef CONFIG_ARM
>  	return raw_irqs_disabled_flags(regs->ARM_cpsr);
> +#else
> +	return raw_irqs_disabled_flags((unsigned long) regs->pstate);
> +#endif
>  }

At least for this part, it makes sense to live in the arch/arm64
directory.

>  #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr),	\
> diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
> index 30cdacb..cb2fa15 100644
> --- a/arch/arm/include/asm/xen/page.h
> +++ b/arch/arm/include/asm/xen/page.h
> @@ -1,7 +1,9 @@
>  #ifndef _ASM_ARM_XEN_PAGE_H
>  #define _ASM_ARM_XEN_PAGE_H
>  
> +#ifdef ARM
>  #include <asm/mach/map.h>
> +#endif
>  #include <asm/page.h>
>  #include <asm/pgtable.h>

Is there anything ARM-specific in this file?

-- 
Catalin


From sanjay.rawat at linaro.org  Fri May 31 06:44:26 2013
From: sanjay.rawat at linaro.org (Sanjay Singh Rawat)
Date: Fri, 31 May 2013 16:14:26 +0530
Subject: [PATCH] ARM: zynq: wfi exit on same cpu is valid
Message-ID: <1369997066-10585-1-git-send-email-sanjay.rawat@linaro.org>

The current code considers every wakeup as spurious, which is not
correct. Handle the same way as other arm platforms are doing.

Signed-off-by: Sanjay Singh Rawat <sanjay.rawat at linaro.org>
---
 arch/arm/mach-zynq/hotplug.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
index c89672b..a1ab22c 100644
--- a/arch/arm/mach-zynq/hotplug.c
+++ b/arch/arm/mach-zynq/hotplug.c
@@ -67,6 +67,13 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
 		dsb();
 		wfi();
 
+		if (pen_release == cpu_logical_map(cpu)) {
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		}
+
 		/*
 		 * Getting here, means that we have come out of WFI without
 		 * having been woken up - this shouldn't happen
-- 
1.7.9.5



From dirk.behme at de.bosch.com  Fri May 31 06:44:23 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 31 May 2013 12:44:23 +0200
Subject: [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial
 enable_count
In-Reply-To: <1370034115-24006-4-git-send-email-b20788@freescale.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
 <1370034115-24006-4-git-send-email-b20788@freescale.com>
Message-ID: <51A87F07.3080402@de.bosch.com>

On 31.05.2013 23:01, Anson Huang wrote:
> Those always-on clocks need to be added into init_on array, this
> is to avoid confusion when we dump the clock tree, the result
> shows that some clocks are on but their enabled_count is 0.
>
> Signed-off-by: Anson Huang <b20788 at freescale.com>
> ---
>   arch/arm/mach-imx/clk-imx6q.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index 390950e..66831a6 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -247,7 +247,7 @@ static struct clk *clk[clk_max];
>   static struct clk_onecell_data clk_data;
>
>   static enum mx6q_clks const clks_init_on[] __initconst = {
> -	mmdc_ch0_axi, rom, pll1_sys,
> +	mmdc_ch0_axi, rom, pll1_sys, ckil, ocram, axi, ipg_per, mx6fast1, per2_main, aips_tz1, aips_tz2, mmdc_ch0_ipg, mmdc_ch1_ipg,


All clocks added with patch 1/4 but not listed here will be disabled by 
the kernel, then? Is this intended? I just ask because it might change 
the boards behavior in case the boot loader touches one of the clocks 
from 1/4 and now they are disabled by the kernel.

Best regards

Dirk



From arnd at arndb.de  Fri May 31 06:47:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 12:47:44 +0200
Subject: [PATCH 31/39] ARM: u300: add syscon node
In-Reply-To: <1369991954-17406-32-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-32-git-send-email-linus.walleij@stericsson.com>
Message-ID: <14733989.vf3LkZC316@wuerfel>

On Friday 31 May 2013 11:19:06 Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This adds a device tree node for the U300 system controller
> and remaps this dynamically instead of using hard-coded
> virtual addresses. The board power set-up code is altered
> to fetch a reference to the syscon using ampersand <&syscon>
> notation. This way of passing a pointer to the syscon will
> also be used by the clocks.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +++++++++++++++++++---
>  arch/arm/boot/dts/ste-u300.dts                     |  6 +++++
>  arch/arm/mach-u300/core.c                          | 22 +++++++++++++---
>  arch/arm/mach-u300/regulator.c                     | 21 ++++++++++++---
>  4 files changed, 69 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
> index cd9001a..69b5ab0 100644
> --- a/Documentation/devicetree/bindings/arm/ste-u300.txt
> +++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
> @@ -8,15 +8,39 @@ Required root node property:
>  
>  compatible="stericsson,u300";
>  
> +Required node: syscon
> +This contains the system controller.
> +- compatible: must be "stericsson,u300-syscon".
> +- reg: the base address and size of the system controller.
> +

Any reason why you are not making it compatible with "syscon", to use
the drivers/mfd/syscon.c driver?

	Arnd 


From josephl at nvidia.com  Fri May 31 06:47:58 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 31 May 2013 18:47:58 +0800
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <51A86D11.8060305@linaro.org>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
 <51A763BD.6070001@linaro.org>
 <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>
 <51A86D11.8060305@linaro.org>
Message-ID: <1369997278.7804.73.camel@jlo-ubuntu-64.nvidia.com>

On Fri, 2013-05-31 at 17:27 +0800, Daniel Lezcano wrote:
> On 05/31/2013 11:12 AM, Joseph Lo wrote:
> > Hi Daniel,
> > 
> > Thanks for your review.
> > 
> > On Thu, 2013-05-30 at 22:35 +0800, Daniel Lezcano wrote:
> >> On 05/30/2013 01:19 PM, Joseph Lo wrote:
> >>> This supports CPU core power down on each CPU when CPU idle. When CPU go
> >>> into this state, it saves it's context and needs a proper configuration
> >>> in flow controller to power gate the CPU when CPU runs into WFI
> >>> instruction. And the CPU also needs to set the IRQ as CPU power down idle
> >>> wake up event in flow controller.
> >>>
> >>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
> >>> ---
> >>
> >> Hi Joseph,
> >>
> >> a new flag has been added in the cpuidle framework to let this one to
> >> handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP
> >>
> >> It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c
> >>
> >> You can get rid of the clockevent notify stuff by adding this flag to
> >> the state.
> >>
> > 
> > I just tested this flag on Tegra20, 30 and 114. It is only OK on
> > Tegra20. It caused a warning message below on Tegra30/114 at boot time.
> > 
> > I gave it a quick check I found it can't clean
> > tick_broadcast_pending_mask sometimes if apply the flag. But I keep the
> > code right now it's always OK. Not sure why? 
> 
> Is it possible you didn't intialized the timer broadcast with
> CLOCK_EVT_NOTIFY_BROADCAST_ON in the driver and then this one is
> actually disabled for you driver ?
> 
I found if I don't apply the CPUIDLE_FLAG_TIMER_STOP flag, the function
"cpuidle_setup_broadcast_timer" (drivers/cpuidle/driver.c) would not be
called. Then it's OK.

If I apply this flag (with no CONFIG_CPU_IDLE_MULTIPLE_DRIVERS), the
cpuidle_register_driver only register for CPU0. Then the
"cpuidle_setup_broadcast_timer" only turn on for CPU0. I think this
might be the root cause. Not sure this also can reproduce on the other
SoCs?




From arnd at arndb.de  Fri May 31 06:49:17 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 12:49:17 +0200
Subject: [PATCH 21/39] ARM: u300: delete all static board data
In-Reply-To: <1369991954-17406-22-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-22-git-send-email-linus.walleij@stericsson.com>
Message-ID: <6751591.S13Ph9lFnY@wuerfel>

On Friday 31 May 2013 11:18:56 Linus Walleij wrote:
>  /* These are mostly to get the right device names for the clock lookups */
>  static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
>         OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
> @@ -736,17 +204,17 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
>         OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
>                 "fsmc-nand", NULL),
>         OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
> -               "uart0", &uart0_plat_data),
> +               "uart0", NULL),
>         OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
> -               "uart1", &uart1_plat_data),
> +               "uart1", NULL),
>         OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
> -               "pl022", &spi_plat_data),
> +               "pl022", NULL),
>         OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
>                 "stu300.0", NULL),
>         OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
>                 "stu300.1", NULL),
>         OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
> -               "mmci", &mmcsd_platform_data),
> +               "mmci", NULL),
>         { /* sentinel */ },
>  };

I did not see any patch removing the auxdata list in the end.
Do you still need it after the clocks are moved over to DT
probing?

	Arnd


From arnd at arndb.de  Fri May 31 06:50:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 12:50:46 +0200
Subject: [PATCH 00/39] U300 device tree and multiplatform
In-Reply-To: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1702584.N7yIx70bQg@wuerfel>

On Friday 31 May 2013 11:18:35 Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This series of "only" 37 patches, partially sent earlier but
> here in its final form, will convert the U300 platform to
> using device tree exclusively, delete board files, and converts
> the machine to multiplatform.
> 
> In order not to artificially split things up, two fixes from
> Ulf Hansson and Peter Huewe are included.
> 
> A pull request will follow unless there are unfixable remarks.

Looks great. I have a few final questions, but no show stopper.

Please reply to my comments so we know how to deal with them
before you send the pull request.

	Arnd


From catalin.marinas at arm.com  Fri May 31 06:59:15 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 11:59:15 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20130531105915.GC18045@localhost.cambridge.arm.com>

On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> --- a/arch/arm/include/asm/xen/page.h
> +++ b/arch/arm/include/asm/xen/page.h
> @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
>  	return __set_phys_to_machine(pfn, mfn);
>  }
>  
> +#ifdef CONFIG_ARM64
> +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> +#else
>  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> +#endif

Now I saw the ARM-specific part. Can you not use something like
ioremap_cached() which would give normal cacheable memory (at least on
ARMv7).

>  #endif /* _ASM_ARM_XEN_PAGE_H */
> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> index 2e12258..0e9c9ac 100644
> --- a/arch/arm64/include/asm/io.h
> +++ b/arch/arm64/include/asm/io.h
> @@ -228,6 +228,7 @@ extern void __iounmap(volatile void __iomem *addr);
>  #define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
>  #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
>  #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
> +#define PROT_NORMAL		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
>  
>  #define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
>  #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))

Of course we need to add ioremap_cached() for arm64 but until now we
didn't need it.

-- 
Catalin


From catalin.marinas at arm.com  Fri May 31 07:02:26 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 12:02:26 +0100
Subject: [PATCH RFC 6/6] arm64/xen: introduce CONFIG_XEN and hypercall.S
 on ARM64
In-Reply-To: <1369930713-6063-6-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-6-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20130531110225.GD18045@localhost.cambridge.arm.com>

On Thu, May 30, 2013 at 05:18:33PM +0100, Stefano Stabellini wrote:
> Introduce CONFIG_XEN and the implementation of hypercall.S (that is
> the only ARMv8 specific code in Xen support for ARM).
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm64/Kconfig         |   11 +++++
>  arch/arm64/Makefile        |    1 +
>  arch/arm64/xen/Makefile    |    1 +
>  arch/arm64/xen/hypercall.S |  105 ++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 118 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm64/xen/Makefile
>  create mode 100644 arch/arm64/xen/hypercall.S
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 56b3f6d..f35751f 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -182,6 +182,17 @@ config HW_PERF_EVENTS
>  
>  source "mm/Kconfig"
>  
> +config XEN_DOM0
> +	def_bool y
> +	depends on XEN
> +
> +config XEN
> +	bool "Xen guest support on ARM64 (EXPERIMENTAL)"
> +	depends on ARM64 && OF
> +	depends on !GENERIC_ATOMIC64

I don't think we need this depends on !GENERIC_ATOMIC64, we don't enable
it on arm64.

-- 
Catalin


From Yalin.Wang at sonymobile.com  Fri May 31 07:02:49 2013
From: Yalin.Wang at sonymobile.com (Wang, Yalin)
Date: Fri, 31 May 2013 19:02:49 +0800
Subject: A bug about system call on ARM
In-Reply-To: <20130531084638.GB4928@mudshark.cambridge.arm.com>
References: <CAFLxGvy39xWdZmtiVHP+y=zH1coCVmMuREcmD25wSb=w-VK7Xg@mail.gmail.com>
 <35FD53F367049845BC99AC72306C23D1610991B85D@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
 <20130531084638.GB4928@mudshark.cambridge.arm.com>
Message-ID: <35FD53F367049845BC99AC72306C23D1610991B874@CNBJMBX05.corpusers.net>

Hi  Will,

I have merge your code ,
But there is a different ,

+	
+	ct_user_exit
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+	ldr	ip, __cr_alignment
+	ldr	ip, [ip]
+	mcr	p15, 0, ip, c1, c0		@ update control register
+#endif 

+	enable_irq
+	get_thread_info tsk

Is this change ok ?


Thanks 

-----Original Message-----
From: linux-arch-owner at vger.kernel.org [mailto:linux-arch-owner at vger.kernel.org] On Behalf Of Will Deacon
Sent: Friday, May 31, 2013 4:47 PM
To: Wang, Yalin
Cc: 'richard -rw- weinberger'; 'linux-arch at vger.kernel.org'; 'linux-kernel at vger.kernel.org'; 'linux-arm-kernel at lists.infradead.org'
Subject: Re: A bug about system call on ARM

On Fri, May 31, 2013 at 03:56:31AM +0100, Wang, Yalin wrote:
> Hi Will,
> 
> Thanks for your patch ,
> 
> But I found  I don't have ct_user_exit  macro In my 
> arch/arm/kernel/entry-common.S
> 
> My kernel version is 3.4.0

Well things have moved on this since then (we're approaching 3.10, so you might consider an upgrade!).

For the purposes of this patch, you can just delete the ct_user_exit line.

Will
--
To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo at vger.kernel.org More majordomo info at  http://vger.kernel.org/majordomo-info.html


From b20788 at freescale.com  Fri May 31 19:08:00 2013
From: b20788 at freescale.com (Anson Huang)
Date: Fri, 31 May 2013 19:08:00 -0400
Subject: [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes.
In-Reply-To: <51A87D85.9000802@de.bosch.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
 <51A87D85.9000802@de.bosch.com>
Message-ID: <20130531230800.GA15742@ubuntu>

On Fri, May 31, 2013 at 12:37:57PM +0200, Dirk Behme wrote:
> On 31.05.2013 23:01, Anson Huang wrote:
> >Some clock gates are useful when we try to disable them
> >to save power, so we need to add these useful clock gate
> >into clock tree.
> >
> >Signed-off-by: Anson Huang <b20788 at freescale.com>
> >---
> >  .../devicetree/bindings/clock/imx6q-clock.txt      |   13 +++++++++++++
> >  arch/arm/mach-imx/clk-imx6q.c                      |   17 ++++++++++++++++-
> >  2 files changed, 29 insertions(+), 1 deletion(-)
> >
> >diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> >index 6deb6fd..df68f99 100644
> >--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> >+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> >@@ -208,6 +208,19 @@ clocks and IDs.
> >  	pll4_post_div		193
> >  	pll5_post_div		194
> >  	pll5_video_div		195
> >+	aips_tz1		196
> >+	aips_tz2		197
> >+	caam_mem		198
> >+	caam_aclk		199
> >+	caam_ipg		200
> >+	tzasc1			201
> >+	tzasc2			202
> >+	vdoa			203
> >+	mmdc_ch0_ipg		204
> >+	mmdc_ch1_ipg		205
> >+	mx6fast1		206
> >+	per2_main		207
> >+	emi_slow		208
> >
> >  Examples:
> >
> >diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> >index dda9a2b..dfb77c1 100644
> >--- a/arch/arm/mach-imx/clk-imx6q.c
> >+++ b/arch/arm/mach-imx/clk-imx6q.c
> >@@ -238,7 +238,9 @@ enum mx6q_clks {
> >  	pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
> >  	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
> >  	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
> >-	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
> >+	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1,
> >+	aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg,
> >+	mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max
> >  };
> >
> >  static struct clk *clk[clk_max];
> >@@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void)
> >  	clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
> >
> >  	/*                                name             parent_name          reg         shift */
> >+	clk[aips_tz1]     = imx_clk_gate2("aips_tz1",      "ahb",               base + 0x68, 0);
> >+	clk[aips_tz2]     = imx_clk_gate2("aips_tz2",      "ahb",               base + 0x68, 2);
> >  	clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
> >  	clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
> >+	clk[caam_mem]     = imx_clk_gate2("caam_mem",      "ahb",               base + 0x68, 8);
> >+	clk[caam_aclk]    = imx_clk_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
> >+	clk[caam_ipg]     = imx_clk_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
> >  	clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
> >  	clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
> >  	clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
> >@@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void)
> >  	clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
> >  	clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
> >  	clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
> >+	clk[tzasc1]       = imx_clk_gate2("tzasc1",        "mmdc_ch0_axi_podf", base + 0x70, 22);
> >+	clk[tzasc2]       = imx_clk_gate2("tzasc2",        "mmdc_ch0_axi_podf", base + 0x70, 24);
> >+	clk[vdoa]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
> >  	clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
> >  	clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
> >  	clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
> >@@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void)
> >  	clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
> >  	clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
> >  	clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
> >+	clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg",  "ipg",               base + 0x74, 24);
> >+	clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg",  "ipg",               base + 0x74, 26);
> >  	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
> >  	clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
> >  	clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
> >+	clk[mx6fast1]     = imx_clk_gate2("mx6fast1",      "ahb",               base + 0x78, 8);
> >  	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
> >+	clk[per2_main]    = imx_clk_gate2("per2_main",     "ahb",               base + 0x78, 14);
> >  	clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
> >  	clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
> >  	clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
> >@@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void)
> >  	clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
> >  	clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
> >  	clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
> >+	clk[emi_slow]     = imx_clk_gate2("emi_slow",      "emi_slow_podf",     base + 0x80, 10);
> >  	clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
> >  	clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
> >  	clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
> 
> I think we have the emi_slow already:
> 
> https://git.linaro.org/gitweb?p=people/shawnguo/linux-2.6.git;a=commitdiff;h=5e569c675297733dec9f5b65aed3fe694c6e6975
> 
Oh, will remove this emi_slow clock, thanks for reminding.
> Best regards
> 
> Dirk
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 



From b20788 at freescale.com  Fri May 31 19:11:00 2013
From: b20788 at freescale.com (Anson Huang)
Date: Fri, 31 May 2013 19:11:00 -0400
Subject: [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial
 enable_count
In-Reply-To: <51A87F07.3080402@de.bosch.com>
References: <1370034115-24006-1-git-send-email-b20788@freescale.com>
 <1370034115-24006-4-git-send-email-b20788@freescale.com>
 <51A87F07.3080402@de.bosch.com>
Message-ID: <20130531231100.GB15742@ubuntu>

On Fri, May 31, 2013 at 12:44:23PM +0200, Dirk Behme wrote:
> On 31.05.2013 23:01, Anson Huang wrote:
> >Those always-on clocks need to be added into init_on array, this
> >is to avoid confusion when we dump the clock tree, the result
> >shows that some clocks are on but their enabled_count is 0.
> >
> >Signed-off-by: Anson Huang <b20788 at freescale.com>
> >---
> >  arch/arm/mach-imx/clk-imx6q.c |    2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> >index 390950e..66831a6 100644
> >--- a/arch/arm/mach-imx/clk-imx6q.c
> >+++ b/arch/arm/mach-imx/clk-imx6q.c
> >@@ -247,7 +247,7 @@ static struct clk *clk[clk_max];
> >  static struct clk_onecell_data clk_data;
> >
> >  static enum mx6q_clks const clks_init_on[] __initconst = {
> >-	mmdc_ch0_axi, rom, pll1_sys,
> >+	mmdc_ch0_axi, rom, pll1_sys, ckil, ocram, axi, ipg_per, mx6fast1, per2_main, aips_tz1, aips_tz2, mmdc_ch0_ipg, mmdc_ch1_ipg,
> 
> 
> All clocks added with patch 1/4 but not listed here will be disabled
> by the kernel, then? Is this intended? I just ask because it might
> change the boards behavior in case the boot loader touches one of
> the clocks from 1/4 and now they are disabled by the kernel.
> 
Yes, I think we should only add those necessary clocks during kernel
boot up, other clocks will be disabled by clk framework automatically,
and modules need to enable those clocks they need before active.
> Best regards
> 
> Dirk
> 
> 



From will.deacon at arm.com  Fri May 31 07:13:05 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 31 May 2013 12:13:05 +0100
Subject: A bug about system call on ARM
In-Reply-To: <35FD53F367049845BC99AC72306C23D1610991B874@CNBJMBX05.corpusers.net>
References: <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
 <20130531084638.GB4928@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B874@CNBJMBX05.corpusers.net>
Message-ID: <20130531111305.GI4928@mudshark.cambridge.arm.com>

On Fri, May 31, 2013 at 12:02:49PM +0100, Wang, Yalin wrote:
> Hi  Will,
> 
> I have merge your code ,
> But there is a different ,
> 
> +	
> +	ct_user_exit

I thought you didn't have ct_user_exit? In which case, just delete this
line.

> +#ifdef CONFIG_ALIGNMENT_TRAP
> +	ldr	ip, __cr_alignment
> +	ldr	ip, [ip]
> +	mcr	p15, 0, ip, c1, c0		@ update control register
> +#endif 
> 
> +	enable_irq
> +	get_thread_info tsk

Hard to tell without context. You can take a look at my git tree if you
like (I fixed it up based on Nico's comment):

  https://git.kernel.org/cgit/linux/kernel/git/will/linux.git/commit/?h=misc-patches

Will


From dmurphy at ti.com  Fri May 31 07:18:31 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 06:18:31 -0500
Subject: [PATCH v2] dmaengine: shdma: fix a build failure on platforms
 with no DMA support
In-Reply-To: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
References: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
Message-ID: <51A88707.4040601@ti.com>

On 05/30/2013 10:01 PM, Guennadi Liakhovetski wrote:
> On platforms with no support for the shdma dmaengine driver build is
> currently failing with
>
> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'
>
> Fix the breakage by defining shdma_chan_filter to NULL in such
> configurations.
>
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> ---
>
> v2: in "next" shdma_chan_filter() is defined in shdma-base.c, which is 
> built if CONFIG_SH_DMAE_BASE is defined. This version uses the correct 
> symbol.
>
> This is for "next." Compile-tested only. I'll test it on hardware next 
> week, but I don't think it shall break anything.
>
>  include/linux/sh_dma.h |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
> index b64d6be..1fd8a20 100644
> --- a/include/linux/sh_dma.h
> +++ b/include/linux/sh_dma.h
> @@ -99,6 +99,10 @@ struct sh_dmae_pdata {
>  #define CHCR_TE	0x00000002
>  #define CHCR_IE	0x00000004
>  
> +#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
>  bool shdma_chan_filter(struct dma_chan *chan, void *arg);
> +#else
> +#define shdma_chan_filter NULL
OK I did not see a reply to my previous comment
Would this not be better as a
#else
static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg) { return false; }
#endif

Otherwise runtime will call a NULL pointer
> +#endif
>  
>  #endif


-- 
------------------
Dan Murphy



From dirk.behme at de.bosch.com  Fri May 31 07:22:54 2013
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 31 May 2013 13:22:54 +0200
Subject: [PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as
 cacheable, increase IPU priority
In-Reply-To: <1369919399-24370-2-git-send-email-mpa@pengutronix.de>
References: <1369919399-24370-1-git-send-email-mpa@pengutronix.de>
 <1369919399-24370-2-git-send-email-mpa@pengutronix.de>
Message-ID: <51A8880E.4010600@de.bosch.com>

On 30.05.2013 15:09, Markus Pargmann wrote:
> From: Philipp Zabel <p.zabel at pengutronix.de>
>
> This is needed so that the IPU framebuffer scanout cannot be starved
> by VPU or GPU activity.
> The Freescale SabreLite and SabreSD boards seem to set this in the boot
> rom already, but the documented register reset values do not contain
> the necessary settings.
>
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> Signed-off-by: Markus Pargmann <mpa at pengutronix.de>
> ---
>   arch/arm/mach-imx/mach-imx6q.c | 32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 5536fd8..7bef242 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -29,6 +29,7 @@
>   #include <linux/regmap.h>
>   #include <linux/micrel_phy.h>
>   #include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
>   #include <asm/hardware/cache-l2x0.h>
>   #include <asm/mach/arch.h>
>   #include <asm/mach/map.h>
> @@ -161,6 +162,36 @@ static void __init imx6q_usb_init(void)
>   	imx_anatop_usb_chrg_detect_disable();
>   }
>
> +static void __init imx6q_gpr_init(void)
> +{
> +	struct regmap *gpr;
> +
> +	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (IS_ERR(gpr)) {
> +		pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
> +		return;
> +	}
> +
> +	/* Enable the cacheable attribute of VPU and IPU AXI transactions */
> +	regmap_update_bits(gpr, IOMUXC_GPR4, 0,
> +			IMX6Q_GPR4_VPU_WR_CACHE_SEL |
> +			IMX6Q_GPR4_VPU_RD_CACHE_SEL |
> +			IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
> +			IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
> +			IMX6Q_GPR4_IPU_WR_CACHE_CTL |
> +			IMX6Q_GPR4_IPU_RD_CACHE_CTL);

I have to admit that I don't understand much of this ;) But comparing 
this with the U-Boot settings

http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg;h=d0f581582113647b06e5f7ab7f72207746613bc6;hb=refs/heads/master#l170

U-Boot additionally sets GPR4[31-28]:

/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF

> +	/* Increase IPU read QoS priority */
> +	regmap_update_bits(gpr, IOMUXC_GPR6,
> +			IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
> +			IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
> +			(0xf << 16) | (0x7 << 20));
> +	regmap_update_bits(gpr, IOMUXC_GPR7,
> +			IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
> +			IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
> +			(0xf << 16) | (0x7 << 20));

and here U-Boot additionally touches GPR6/7[6-0]:

/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F

As mentioned above, I have no idea if/why this is necessary ;)

Best regards

Dirk









From arnd at arndb.de  Fri May 31 07:24:59 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 13:24:59 +0200
Subject: [PATCH v2] ARM: mmp: bring up pxa988 with device tree support
In-Reply-To: <1369969115-4279-2-git-send-email-zhangwm@marvell.com>
References: <1369969115-4279-1-git-send-email-zhangwm@marvell.com>
 <1369969115-4279-2-git-send-email-zhangwm@marvell.com>
Message-ID: <1726105.oKcjXShr89@wuerfel>

On Friday 31 May 2013 10:58:35 Neil Zhang wrote:
> bring up pxa988 with device tree support.
> 
> Change-Id: I6fc869b7d5ff8dc6e4eb0042a89429200f7a9fb1

Please don't post silly extra headers like that.

> Signed-off-by: Neil Zhang <zhangwm at marvell.com>

A couple of comments on the DT structure:

> +	gic: interrupt-controller at d1dfe100 {
> +		compatible = "arm,cortex-a9-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0xd1dff000 0x1000>,
> +		      <0xd1dfe100 0x0100>;
> +	};
> +
> +	L2: l2-cache-controller at d1dfb000 {
> +		compatible = "arm,pl310-cache";
> +		reg = <0xd1dfb000 0x1000>;
> +		arm,data-latency = <2 1 1>;
> +		arm,tag-latency = <2 1 1>;
> +		arm,pwr-dynamic-clk-gating;
> +		arm,pwr-standby-mode;
> +		cache-unified;
> +		cache-level = <2>;
> +	};
> +
> +	local-timer at d1dfe600 {
> +		compatible = "arm,cortex-a9-twd-timer";
> +		reg = <0xd1dfe600 0x20>;
> +		interrupts = <1 13 0x304>;
> +	};

Why are these all top-level devices, rather than part of the
'soc' node?

> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		axi at d4200000 {	/* AXI */
> +			compatible = "mrvl,axi-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xd4200000 0x00200000>;
> +			ranges;
> +
> +			intc: wakeupgen at d4282000 {
> +				compatible = "mrvl,mmp-intc";
> +				reg = <0xd4282000 0x1000>;
> +				mrvl,intc-wakeup = <0x114 0x3
> +						    0x144 0x3>;
> +			};
> +
> +		};

What is a 'mrvl,axi-bus'? Is that different from ARM's AXI bus?

The documented vendor prefix for Marvell is 'marvell', not 'mrvl',
please be consistent with that.

What is the purpose of the 'reg' property in the axi bus? I notice
that it overlaps with its own children, wich seens very strange.
Maybe you meant this:

	axi {
		ranges = <0xd4200000 0xd4200000 0x00200000>;
		...
	};

> +		apb at d4000000 {	/* APB */
> +			compatible = "mrvl,apb-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xd4000000 0x00200000>;
> +			ranges;

Same comments apply here.

> diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
> index ebdda83..0955191 100644
> --- a/arch/arm/mach-mmp/Kconfig
> +++ b/arch/arm/mach-mmp/Kconfig
> @@ -107,6 +107,16 @@ config MACH_MMP2_DT
>  	  Include support for Marvell MMP2 based platforms using
>  	  the device tree.
>  
> +config MACH_MMPX_DT
> +	bool "Support no-PJ/PJ4(ARMv7) platforms from device tree"
> +	depends on !CPU_MOHAWK && !CPU_PJ4
> +	select CPU_PXA988
> +	select USE_OF
> +	select PINCTRL
> +	select PINCTRL_SINGLE

Why would this be mutually exclusive with PJ4? Cortex-A9 and PJ4
are both ARMv7 based, so we should be able to have them in the
same kernel.

> +	help
> +	  Include support for Marvell MMP2 based platforms using
> +	  the device tree.
>  endmenu

You should probably change the help texts to say different things
here, e.g. list the models supported under these.

> diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
> index 9292b79..0c621bc 100644
> --- a/arch/arm/mach-mmp/common.c
> +++ b/arch/arm/mach-mmp/common.c
> @@ -11,6 +11,10 @@
>  #include <linux/init.h>
>  #include <linux/kernel.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/of_address.h>
>  
>  #include <asm/page.h>
>  #include <asm/mach/map.h>
> @@ -36,7 +40,12 @@ static struct map_desc standard_io_desc[] __initdata = {
>  		.virtual	= (unsigned long)AXI_VIRT_BASE,
>  		.length		= AXI_PHYS_SIZE,
>  		.type		= MT_DEVICE,
> -	},
> +	}, {
> +		.pfn		= __phys_to_pfn(MMP_CORE_PERIPH_PHYS_BASE),
> +		.virtual	= (unsigned long)MMP_CORE_PERIPH_VIRT_BASE,
> +		.length		= MMP_CORE_PERIPH_PHYS_SIZE,
> +		.type		= MT_DEVICE,
> +	}
>  };
>  
>  void __init mmp_map_io(void)

What is this needed for?

> +/* PXA988 */
> +static const struct of_dev_auxdata pxa988_auxdata_lookup[] __initconst = {
> +	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
> +	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
> +	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
> +	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
> +	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
> +	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
> +	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
> +	{}
> +};

Why do you need auxdata?

> +void __init pxa988_dt_init_timer(void)
> +{
> +	extern void __init mmp_dt_init_timer(void);

You should never put 'extern' declarations into a .c file.

> +	/*
> +	 * Is is a SOC timer, and will be used for broadcasting
> +	 * when local timers are disabled.
> +	 */
> +	mmp_dt_init_timer();
> +
> +	clocksource_of_init();
> +}

Please just change the mmp_dt_init_timer function to use
CLOCKSOURCE_OF_DECLARE(), and if possible move the file to
drivers/clocksource.

> +static const char *pxa988_dt_board_compat[] __initdata = {
> +	"mrvl,pxa988-dkb",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(PXA988_DT, "Marvell PXA988 (Device Tree Support)")
> +	.smp		= smp_ops(mmp_smp_ops),
> +	.map_io		= mmp_map_io,
> +	.init_irq	= irqchip_init,

You can leave out the init_irq, it's implicit.

> +	.init_time	= pxa988_dt_init_timer,
> +	.init_machine	= pxa988_dt_init_machine,
> +	.dt_compat	= pxa988_dt_board_compat,
> +MACHINE_END


> +
> +static int __init mmp_entry_vector_init(void)
> +{
> +	int cpu;
> +
> +	/* We will reset from DDR directly by default */
> +	writel(__pa(mmp_cpu_reset_entry), CIU_CA9_WARM_RESET_VECTOR);
> +
> +	for (cpu = 1; cpu < CONFIG_NR_CPUS; cpu++)
> +		mmp_set_entry_vector(cpu, __pa(mmp_secondary_startup));
> +}
> +
> +early_initcall(mmp_entry_vector_init);

You need to check which machine you are running on here. Best just move
the call into one of the init functions of the machine descriptor,
e.g. init_machine or init_late.

CONFIG_NR_CPUS is probably the wrong constant to use here, it does
not have to match the physically present CPU cores.

	Arnd


From linus.walleij at linaro.org  Fri May 31 07:26:31 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 13:26:31 +0200
Subject: [PATCH 02/39] ARM: u300: device tree support for the timer
In-Reply-To: <7742928.6bJiIVUE0X@wuerfel>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-3-git-send-email-linus.walleij@stericsson.com>
 <7742928.6bJiIVUE0X@wuerfel>
Message-ID: <CACRpkdZYsnUhjYO_U4L56TMY+fs+ZU9zk3zLWnjPtf8Bmmn0YQ@mail.gmail.com>

On Fri, May 31, 2013 at 12:31 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 31 May 2013 11:18:37 Linus Walleij wrote:

>> +void __init u300_timer_init()
>> +{
>> +       u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +
>> +static void __init u300_timer_init_of(struct device_node *np)
>> +{
>> +       void __iomem *base;
>> +       struct resource irq_res;
>> +       int irq;
>> +
>> +       base = of_iomap(np, 0);
>> +       /* Get the IRQ for the GP1 timer */
>> +       irq = of_irq_to_resource(np, 2, &irq_res);
>> +       u300_timer_setup(base, irq);
>> +}
>> +
>> +CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
>> +                      u300_timer_init_of);
>> +
>> +#endif
>
> You should not need the CONFIG_OF #ifdef, since the CLOCKSOURCE_OF_DECLARE
> macro is designed to let the function get dropped by the compiler when
> that is not set.
>
> You might want a CONFIG_ATAGS check for the other function though.

Both the other function and the #ifdef CONFIG_OF are deleted in
patch 21. Is this OK?

>> diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
>> index d34287b..7766dfa 100644
>> --- a/arch/arm/mach-u300/timer.h
>> +++ b/arch/arm/mach-u300/timer.h
>> @@ -1 +1,2 @@
>>  extern void u300_timer_init(void);
>> +
>
> You probably didn't mean to include this newline.

This entire file is also deleted in patch 21.

I can fix it up if you absolutely want to but it feels like
something of an academic exercise.

Yours,
Linus Walleij


From Yalin.Wang at sonymobile.com  Fri May 31 07:30:38 2013
From: Yalin.Wang at sonymobile.com (Wang, Yalin)
Date: Fri, 31 May 2013 19:30:38 +0800
Subject: A bug about system call on ARM
In-Reply-To: <20130531111305.GI4928@mudshark.cambridge.arm.com>
References: <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
 <20130531084638.GB4928@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B874@CNBJMBX05.corpusers.net>
 <20130531111305.GI4928@mudshark.cambridge.arm.com>
Message-ID: <35FD53F367049845BC99AC72306C23D1610991B876@CNBJMBX05.corpusers.net>

Hi Will,

I see,
I will make one more test .

Thanks for your clarification .

-----Original Message-----
From: Will Deacon [mailto:will.deacon at arm.com] 
Sent: Friday, May 31, 2013 7:13 PM
To: Wang, Yalin
Cc: 'richard -rw- weinberger'; 'linux-arch at vger.kernel.org'; 'linux-kernel at vger.kernel.org'; 'linux-arm-kernel at lists.infradead.org'
Subject: Re: A bug about system call on ARM

On Fri, May 31, 2013 at 12:02:49PM +0100, Wang, Yalin wrote:
> Hi  Will,
> 
> I have merge your code ,
> But there is a different ,
> 
> +	
> +	ct_user_exit

I thought you didn't have ct_user_exit? In which case, just delete this line.

> +#ifdef CONFIG_ALIGNMENT_TRAP
> +	ldr	ip, __cr_alignment
> +	ldr	ip, [ip]
> +	mcr	p15, 0, ip, c1, c0		@ update control register
> +#endif
> 
> +	enable_irq
> +	get_thread_info tsk

Hard to tell without context. You can take a look at my git tree if you like (I fixed it up based on Nico's comment):

  https://git.kernel.org/cgit/linux/kernel/git/will/linux.git/commit/?h=misc-patches

Will


From josephl at nvidia.com  Fri May 31 07:31:10 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 31 May 2013 19:31:10 +0800
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <1369997278.7804.73.camel@jlo-ubuntu-64.nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
 <51A763BD.6070001@linaro.org>
 <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>
 <51A86D11.8060305@linaro.org>
 <1369997278.7804.73.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <1369999870.7804.78.camel@jlo-ubuntu-64.nvidia.com>

On Fri, 2013-05-31 at 18:47 +0800, Joseph Lo wrote:
> On Fri, 2013-05-31 at 17:27 +0800, Daniel Lezcano wrote:
> > On 05/31/2013 11:12 AM, Joseph Lo wrote:
> > > Hi Daniel,
> > > 
> > > Thanks for your review.
> > > 
> > > On Thu, 2013-05-30 at 22:35 +0800, Daniel Lezcano wrote:
> > >> On 05/30/2013 01:19 PM, Joseph Lo wrote:
> > >>> This supports CPU core power down on each CPU when CPU idle. When CPU go
> > >>> into this state, it saves it's context and needs a proper configuration
> > >>> in flow controller to power gate the CPU when CPU runs into WFI
> > >>> instruction. And the CPU also needs to set the IRQ as CPU power down idle
> > >>> wake up event in flow controller.
> > >>>
> > >>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
> > >>> ---
> > >>
> > >> Hi Joseph,
> > >>
> > >> a new flag has been added in the cpuidle framework to let this one to
> > >> handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP
> > >>
> > >> It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c
> > >>
> > >> You can get rid of the clockevent notify stuff by adding this flag to
> > >> the state.
> > >>
> > > 
> > > I just tested this flag on Tegra20, 30 and 114. It is only OK on
> > > Tegra20. It caused a warning message below on Tegra30/114 at boot time.
> > > 
> > > I gave it a quick check I found it can't clean
> > > tick_broadcast_pending_mask sometimes if apply the flag. But I keep the
> > > code right now it's always OK. Not sure why? 
> > 
> > Is it possible you didn't intialized the timer broadcast with
> > CLOCK_EVT_NOTIFY_BROADCAST_ON in the driver and then this one is
> > actually disabled for you driver ?
> > 
> I found if I don't apply the CPUIDLE_FLAG_TIMER_STOP flag, the function
> "cpuidle_setup_broadcast_timer" (drivers/cpuidle/driver.c) would not be
> called. Then it's OK.
> 
> If I apply this flag (with no CONFIG_CPU_IDLE_MULTIPLE_DRIVERS), the
> cpuidle_register_driver only register for CPU0. Then the
> "cpuidle_setup_broadcast_timer" only turn on for CPU0. I think this
> might be the root cause. Not sure this also can reproduce on the other
> SoCs?
> 
Looks it's not related to CLOCK_EVT_NOTIFY_BROADCAST_ON. I still saw the
warning message even enable CONFIG_CPU_IDLE_MULTIPLE_DRIVERS. But if I
move the clockevent_notify of CLOCK_EVT_NOTIFY_BROADCAST_EXIT from idle
framework back to driver, then everything is OK.




From linus.walleij at linaro.org  Fri May 31 07:33:45 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 13:33:45 +0200
Subject: [PATCH 12/39] ARM: u300: set up board power from device tree
In-Reply-To: <6621177.ZgrPQ48FXE@wuerfel>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-13-git-send-email-linus.walleij@stericsson.com>
 <6621177.ZgrPQ48FXE@wuerfel>
Message-ID: <CACRpkdYXfm4xzqn2Kb0fw2_+BSSXBoNXye2zu3fpv1sPQcHO9w@mail.gmail.com>

On Fri, May 31, 2013 at 12:37 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 31 May 2013 11:18:47 Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij at linaro.org>
>>
>> This adds support for setting up the board power from the
>> device tree on the U300. We use a board-specific node in the
>> device tree for the S365 board and bind a regulator for the
>> board power to this node.
>>
>> Cc: Mark Brown <broonie at kernel.org>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>
> This is fairly unusual, I think I've never seen a platform driver
> registered for a board.  Is that the intended method for hogging
> a regulator?

There are no precedents AFAICT.

As you can see the previous code uses:
regulator_get(NULL, "vana15");

But that does not match with device tree: it needs some node
to tie the regulator to, i.e. a platform device. Else we leave the
system in some half-transition to DT.

The siutation is similar to our inability to use clk_get_sys()
in pure DT platforms - no node/device there either.

Mark remarked on the first iteration that:

> I would expect this to be bound based on the board name that appears in
> the device tree which (given the way this stuff mostly works) I'd expect
> to have a device node available.

This is what I'm trying to do here.

The root node which actually contains the compatible-string
for the board itself can *not* be used, as the OF platform core
code does not create a platform device for this node, and it
cannot reference anything either.

So a single board node directly in the root was the best
I could come up with, other suggestions welcome...

Yours,
Linus Walleij


From josephl at nvidia.com  Fri May 31 07:44:40 2013
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 31 May 2013 19:44:40 +0800
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <1369999870.7804.78.camel@jlo-ubuntu-64.nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
 <51A763BD.6070001@linaro.org>
 <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>
 <51A86D11.8060305@linaro.org>
 <1369997278.7804.73.camel@jlo-ubuntu-64.nvidia.com>
 <1369999870.7804.78.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <1370000680.7804.83.camel@jlo-ubuntu-64.nvidia.com>

On Fri, 2013-05-31 at 19:31 +0800, Joseph Lo wrote:
> On Fri, 2013-05-31 at 18:47 +0800, Joseph Lo wrote:
> > On Fri, 2013-05-31 at 17:27 +0800, Daniel Lezcano wrote:
> > > On 05/31/2013 11:12 AM, Joseph Lo wrote:
> > > > Hi Daniel,
> > > > 
> > > > Thanks for your review.
> > > > 
> > > > On Thu, 2013-05-30 at 22:35 +0800, Daniel Lezcano wrote:
> > > >> On 05/30/2013 01:19 PM, Joseph Lo wrote:
> > > >>> This supports CPU core power down on each CPU when CPU idle. When CPU go
> > > >>> into this state, it saves it's context and needs a proper configuration
> > > >>> in flow controller to power gate the CPU when CPU runs into WFI
> > > >>> instruction. And the CPU also needs to set the IRQ as CPU power down idle
> > > >>> wake up event in flow controller.
> > > >>>
> > > >>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
> > > >>> ---
> > > >>
> > > >> Hi Joseph,
> > > >>
> > > >> a new flag has been added in the cpuidle framework to let this one to
> > > >> handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP
> > > >>
> > > >> It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c
> > > >>
> > > >> You can get rid of the clockevent notify stuff by adding this flag to
> > > >> the state.
> > > >>
> > > > 
> > > > I just tested this flag on Tegra20, 30 and 114. It is only OK on
> > > > Tegra20. It caused a warning message below on Tegra30/114 at boot time.
> > > > 
> > > > I gave it a quick check I found it can't clean
> > > > tick_broadcast_pending_mask sometimes if apply the flag. But I keep the
> > > > code right now it's always OK. Not sure why? 
> > > 
> > > Is it possible you didn't intialized the timer broadcast with
> > > CLOCK_EVT_NOTIFY_BROADCAST_ON in the driver and then this one is
> > > actually disabled for you driver ?
> > > 
> > I found if I don't apply the CPUIDLE_FLAG_TIMER_STOP flag, the function
> > "cpuidle_setup_broadcast_timer" (drivers/cpuidle/driver.c) would not be
> > called. Then it's OK.
> > 
> > If I apply this flag (with no CONFIG_CPU_IDLE_MULTIPLE_DRIVERS), the
> > cpuidle_register_driver only register for CPU0. Then the
> > "cpuidle_setup_broadcast_timer" only turn on for CPU0. I think this
> > might be the root cause. Not sure this also can reproduce on the other
> > SoCs?
> > 
> Looks it's not related to CLOCK_EVT_NOTIFY_BROADCAST_ON. I still saw the
> warning message even enable CONFIG_CPU_IDLE_MULTIPLE_DRIVERS. But if I
> move the clockevent_notify of CLOCK_EVT_NOTIFY_BROADCAST_EXIT from idle
> framework back to driver, then everything is OK.
> 
Once I move the clockevent_notify of CLOCK_EVT_NOTIFY_BROADCAST_EXIT
right after "local_irq_enable" in the
"cpuidle_enter_state" (drivers/cpuidle/cpuidle.c). Then the warning
message shows up.




From jason at lakedaemon.net  Fri May 31 07:54:50 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 31 May 2013 07:54:50 -0400
Subject: [PATCH v5 12/13] ARM: kirkwood: remove redundant DT board files
In-Reply-To: <87txlknluf.fsf@natisbad.org>
References: <1369154510-4927-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1369855975-21489-13-git-send-email-sebastian.hesselbarth@gmail.com>
 <8738t4q1kv.fsf@natisbad.org>
 <20130530193708.GC31290@titan.lakedaemon.net>
 <87txlknluf.fsf@natisbad.org>
Message-ID: <20130531115450.GA3803@titan.lakedaemon.net>

Arnaud,

On Fri, May 31, 2013 at 12:28:56AM +0200, Arnaud Ebalard wrote:
> Hi,
> 
> Jason Cooper <jason at lakedaemon.net> writes:
> 
> >> For instance 6bd98481ab34 (arm: kirkwood: NETGEAR ReadyNAS Duo v2 init
> >> PCIe via DT) currently sitting in jcooper/mvebu/pcie_kirkwood removes
> >> the PCIE init routine in board-readynas.c, and yours remove ge00
> >> init. With both applied, the whole file can go away.
> >> 
> >> AFAICT, this may be the case soon for:
> >> 
> >>  arch/arm/mach-kirkwood/board-iconnect.c   (36e5722089)
> >>  arch/arm/mach-kirkwood/board-mplcec4.c    (9470fbfb8d)
> >>  arch/arm/mach-kirkwood/board-nsa310.c     (40fa8e5da2)
> >>  arch/arm/mach-kirkwood/board-readynas.c   (6bd98481ab)
> >>  arch/arm/mach-kirkwood/board-ts219.c      (259e234608)
> >
> > Would you mind putting a patch together (for after v3.10 drops) to do
> > this?  If you applied Sebastian's series on top of mvebu/pcie_kirkwood,
> > that should get you almost there.  The last half of his series is going
> > in after v3.10...
> 
> Something like the quick quilt-generated patch at the end of this email
> (done after a dummy merge of Sebastian's set in mvebu/pcie_kirkwood)? 

yep.

> I will take a look at what remains after Sebastian's set hit one of
> your branch but I guess he will have included most of what is in the
> patch to help you with the merge.
> 
> Anyway, at the end here is what DT board files would remain:
> 
> $ ls -1 arch/arm/mach-kirkwood/board-*.c
> arch/arm/mach-kirkwood/board-dnskw.c

This one seems to just be setting a gpio to enable reboot after power
failure.  Should be simple to move to DT.

> arch/arm/mach-kirkwood/board-dt.c

We obviously need this one. ;-)

> arch/arm/mach-kirkwood/board-lsxl.c

This is taken care of in mvebu/boards

  391a16c ARM: Kirkwood: Convert LSXL to restart-poweroff driver.

> arch/arm/mach-kirkwood/board-ts219.c

Also in mvebu/boards

  4350a47 ARM: Kirkwood: Make use of the QNAP Power off driver.

> Just one question though: the removal of MACH_*_DT in Kconfig removes
> the automatic selection of useful board specific options like
> ARM_APPENDED_DTB, ARM_ATAG_DTB_COMPAT, POWER_RESET_RESTART,
> POWER_RESET_QNAP. Is that expected?

I would select POWER_RESET_QNAP and POWER_RESET_RESTART in Kconfig for
ARCH_KIRKWOOD_DT, and put ARM_APPENDED_DTB and ARM_ATAG_DTB_COMPAT into
the defconfig.

thx,

Jason.


From linus.walleij at linaro.org  Fri May 31 07:55:56 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 13:55:56 +0200
Subject: [PATCH 31/39] ARM: u300: add syscon node
In-Reply-To: <14733989.vf3LkZC316@wuerfel>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-32-git-send-email-linus.walleij@stericsson.com>
 <14733989.vf3LkZC316@wuerfel>
Message-ID: <CACRpkdaPXLuyXWSrMipZs6L973-8C=iaeOWYZ_zCKCSZNn2cQQ@mail.gmail.com>

On Fri, May 31, 2013 at 12:47 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 31 May 2013 11:19:06 Linus Walleij wrote:

>>  compatible="stericsson,u300";
>>
>> +Required node: syscon
>> +This contains the system controller.
>> +- compatible: must be "stericsson,u300-syscon".
>> +- reg: the base address and size of the system controller.
>> +
>
> Any reason why you are not making it compatible with "syscon", to use
> the drivers/mfd/syscon.c driver?

For the first lookup at irq_init() we cannot use it.

This is because that needs to be initialized at irq_init() time
to set up the clocks, which are needed by the interrupt controller,
it cannot use device matching, as the platform devices are not
probed yet.

However I can make it compatible for the board power snippet
to make use of it for sure.

But I find no good examples in the kernel on how to grab a
referenced syscon node and use the regmap API to read/write
registers :-(

Dong: do you have some example to point at for this?

Yours,
Linus Walleij


From stefano.stabellini at eu.citrix.com  Fri May 31 08:02:04 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 31 May 2013 13:02:04 +0100
Subject: [PATCH RFC 1/6] [HACK!] arm64/xen: create links to arch/arm
 include files and Xen code
In-Reply-To: <20130531103617.GA18045@localhost.cambridge.arm.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531103617.GA18045@localhost.cambridge.arm.com>
Message-ID: <alpine.DEB.2.02.1305311259090.4799@kaball.uk.xensource.com>

On Fri, 31 May 2013, Catalin Marinas wrote:
> On Thu, May 30, 2013 at 05:18:28PM +0100, Stefano Stabellini wrote:
> > Most of Xen support for ARM is common between ARMv7 and ARMv8.
> > Create links to the code under arch/arm (bleah).
> > 
> > Other, probably better alternatives:
> > 
> > - move the code to a different location, maybe the header files to
> > include/xen/arm and the code to drivers/xen/arm (still pretty ugly)?
> > 
> > - create a copy of the code to arch/arm64 (even worse);
> 
> KVM handles this in the Makefile by referencing back to arch/arm or even
> the generic kvm directory. I think that's the 'cleanest' ;)

Do you mean creating links in the Makefile or generating header file
copies from the Makefile?
Or do you mean using something like "-I arch/arm/include/asm/xen" in the
arch/arm64 Makefile?

I tried to find exactly what KVM is doing but I couldn't find the code
you are talking about..


From tushar.behera at linaro.org  Fri May 31 07:49:01 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 31 May 2013 17:19:01 +0530
Subject: [PATCH 0/3] Consolidate uncompress code for Samsung platform
Message-ID: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>

The patches are based on v3.10-rc3.

They are build tested for s3c2410_defconfig, s3c6400_defconfig,
s5p64x0_defconfig, s5pc100_defconfig, s5pv210_defconfig,
exynos4_defconfig and exynos_defconfig.

Since they affect all the Samsung boards, testing them on different
machines would be essential. Unfortunately I can only test on Exynos here.

Tested on Exynos5250 based Arndale board.

Tushar Behera (3):
  ARM: EXYNOS: uncompress - print debug messages if DEBUG_LL is defined
  ARM: SAMSUNG: Consolidate uncompress subroutine
  ARM: S5P64X0: Remove duplicate uncompress code

 arch/arm/mach-exynos/include/mach/uncompress.h  |   14 +-
 arch/arm/mach-s3c24xx/include/mach/uncompress.h |    7 +
 arch/arm/mach-s3c64xx/include/mach/uncompress.h |    7 +
 arch/arm/mach-s5p64x0/include/mach/uncompress.h |  163 ++---------------------
 arch/arm/mach-s5pc100/include/mach/uncompress.h |    6 +
 arch/arm/mach-s5pv210/include/mach/uncompress.h |    6 +
 arch/arm/plat-samsung/include/plat/uncompress.h |   16 ++-
 7 files changed, 53 insertions(+), 166 deletions(-)

-- 
1.7.9.5



From tushar.behera at linaro.org  Fri May 31 07:49:03 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 31 May 2013 17:19:03 +0530
Subject: [PATCH 2/3] ARM: SAMSUNG: Consolidate uncompress subroutine
In-Reply-To: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
References: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1370000944-19786-3-git-send-email-tushar.behera@linaro.org>

For mach-exynos, uart_base is a pointer and the value is calculated
in the machine folder. For other machines, uart_base is defined as
a macro in platform directory. For symmetry, the uart_base macro
definition is removed and the uart_base calculation is moved to
specific machine folders.

This would help us consolidating uncompress subroutine for s5p64x0.

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-exynos/include/mach/uncompress.h  |    3 ---
 arch/arm/mach-s3c24xx/include/mach/uncompress.h |    7 +++++++
 arch/arm/mach-s3c64xx/include/mach/uncompress.h |    7 +++++++
 arch/arm/mach-s5pc100/include/mach/uncompress.h |    6 ++++++
 arch/arm/mach-s5pv210/include/mach/uncompress.h |    6 ++++++
 arch/arm/plat-samsung/include/plat/uncompress.h |    6 ++----
 6 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 730f69f..30592fd 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -15,9 +15,6 @@
 #include <asm/mach-types.h>
 
 #include <mach/map.h>
-
-volatile u8 *uart_base;
-
 #include <plat/uncompress.h>
 
 static unsigned int __raw_readl(unsigned int ptr)
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f8..638893e 100644
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
@@ -49,6 +49,13 @@ static void arch_detect_cpu(void)
 		fifo_mask = S3C2410_UFSTAT_TXMASK;
 		fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
 	}
+
+#ifdef CONFIG_DEBUG_LL
+	uart_base = (volatile u8 *) S3C_PA_UART +
+		(S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+	uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
index c6a82a2..d6f9188 100644
--- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -23,6 +23,13 @@ static void arch_detect_cpu(void)
 	/* we do not need to do any cpu detection here at the moment. */
 	fifo_mask = S3C2440_UFSTAT_TXMASK;
 	fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+
+#ifdef CONFIG_DEBUG_LL
+	uart_base = (volatile u8 *)S3C_PA_UART +
+		(S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+	uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
index 01ccf53..c1242df 100644
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h
@@ -23,6 +23,12 @@ static void arch_detect_cpu(void)
 	/* we do not need to do any cpu detection here at the moment. */
 	fifo_mask = S3C2440_UFSTAT_TXMASK;
 	fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+
+#ifdef CONFIG_DEBUG_LL
+	uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+	uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
index ef977ea..2193812 100644
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h
@@ -21,6 +21,12 @@ static void arch_detect_cpu(void)
 	/* we do not need to do any cpu detection here at the moment. */
 	fifo_mask = S5PV210_UFSTAT_TXMASK;
 	fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
+
+#ifdef CONFIG_DEBUG_LL
+	uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+	uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 350032b..78274eb 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -21,6 +21,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 unsigned int fifo_mask;
 unsigned int fifo_max;
 
+volatile u8 *uart_base;
+
 /* forward declerations */
 
 static void arch_detect_cpu(void);
@@ -37,10 +39,6 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
 
-#ifdef S3C_PA_UART
-#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
-#endif
-
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
 {
-- 
1.7.9.5



From tushar.behera at linaro.org  Fri May 31 07:49:04 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 31 May 2013 17:19:04 +0530
Subject: [PATCH 3/3] ARM: S5P64X0: Remove duplicate uncompress code
In-Reply-To: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
References: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1370000944-19786-4-git-send-email-tushar.behera@linaro.org>

The uncompress code in S5P64X0 is almost same as the uncompress code
defined in plat-samsung. Better to reuse that code.

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-s5p64x0/include/mach/uncompress.h |  163 ++---------------------
 1 file changed, 8 insertions(+), 155 deletions(-)

diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 19e0d64..b28a551 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -14,171 +14,24 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include <mach/map.h>
+#include <plat/uncompress.h>
 
-/*
- * cannot use commonly <plat/uncompress.h>
- * because uart base of S5P6440 and S5P6450 is different
- */
-
-typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-unsigned int fifo_mask;
-unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX	 (14)
-
-unsigned long uart_base;
-
-static __inline__ void get_uart_base(void)
+static void arch_detect_cpu(void)
 {
 	unsigned int chipid;
 
 	chipid = *(const volatile unsigned int __force *) 0xE0100118;
 
-	uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
-
+#ifdef DEBUG_LL
 	if ((chipid & 0xff000) == 0x50000)
-		uart_base += 0xEC800000;
+		uart_base = S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 	else
-		uart_base += 0xEC000000;
-}
-
-static __inline__ void uart_wr(unsigned int reg, unsigned int val)
-{
-	volatile unsigned int *ptr;
-
-	get_uart_base();
-	ptr = (volatile unsigned int *)(reg + uart_base);
-	*ptr = val;
-}
-
-static __inline__ unsigned int uart_rd(unsigned int reg)
-{
-	volatile unsigned int *ptr;
-
-	get_uart_base();
-	ptr = (volatile unsigned int *)(reg + uart_base);
-	return *ptr;
-}
-
-/*
- * we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
- */
-
-static void putc(int ch)
-{
-	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-		int level;
-
-		while (1) {
-			level = uart_rd(S3C2410_UFSTAT);
-			level &= fifo_mask;
-
-			if (level < fifo_max)
-				break;
-		}
-
-	} else {
-		/* not using fifos */
-
-		while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-			barrier();
-	}
-
-	/* write byte to transmission register */
-	uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d, ad)			\
-	do {							\
-		*((volatile unsigned int __force *)(ad)) = (d); \
-	} while (0)
-
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-	putstr("\n\n");
-	putstr(x);
-	putstr("\n\n -- System resetting\n");
-
-	__raw_writel(0x4000, S3C2410_WTDAT);
-	__raw_writel(0x4000, S3C2410_WTCNT);
-	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-	while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-	u32 fifocon = uart_rd(S3C2410_UFCON);
-
-	if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
-		fifocon |= S3C2410_UFCON_RESETBOTH;
-		uart_wr(S3C2410_UFCON, fifocon);
-
-		/* wait for fifo reset to complete */
-		while (1) {
-			fifocon = uart_rd(S3C2410_UFCON);
-			if (!(fifocon & S3C2410_UFCON_RESETBOTH))
-				break;
-		}
-	}
-}
+		uart_base = S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 #else
-#define arch_enable_uart_fifo() do { } while(0)
+	uart_base = NULL;
 #endif
 
-static void arch_decomp_setup(void)
-{
-	/*
-	 * we may need to setup the uart(s) here if we are not running
-	 * on an BAST... the BAST will have left the uarts configured
-	 * after calling linux.
-	 */
-
-	arch_detect_cpu();
-
-	/*
-	 * Enable the UART FIFOs if they where not enabled and our
-	 * configuration says we should turn them on.
-	 */
-
-	arch_enable_uart_fifo();
+	fifo_mask = S3C2440_UFSTAT_TXMASK;
+	fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
 }
-
-
-
-static void arch_detect_cpu(void)
-{
-	/* we do not need to do any cpu detection here at the moment. */
-}
-
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
-- 
1.7.9.5



From jason at lakedaemon.net  Fri May 31 08:05:19 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 31 May 2013 08:05:19 -0400
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130530164335.GK23631@arm.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130529110508.GH17767@MacBook-Pro.local>
 <20130529191657.GA13047@schnuecks.de>
 <20130530164335.GK23631@arm.com>
Message-ID: <20130531120519.GB3803@titan.lakedaemon.net>

On Thu, May 30, 2013 at 05:43:35PM +0100, Catalin Marinas wrote:
> On Wed, May 29, 2013 at 08:16:57PM +0100, Simon Baatz wrote:
> > On Wed, May 29, 2013 at 12:05:09PM +0100, Catalin Marinas wrote:
> > > On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > > > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > > > it needs to handle are kernel mapped only.  However, for example when doing
> > > > direct I/O, pages with user space mappings may occur.
> > > 
> > > After Nico's clarification, I think the original commit introducing this
> > > function was also incomplete (commit 73be1591 - [ARM] 5545/2: add
> > > flush_kernel_dcache_page() for ARM) since it ignores highmem pages and
> > > their flushing could be deferred for a long time.
> > 
> > Yes, I agree.
> >  
> > > For my understanding (if I re-read this tread) - basically code like
> > > this should not leave the user mapping inconsistent:
> > > 
> > > kmap()
> > > ...
> > > flush_kernel_dcache_page()
> > > kunmap()
> > 
> > s/user mapping/kernel mapping/ 
> > The user mapping(s) can be assumed to be consistent when entering
> > such code. Either there is none or the page was obtained by a
> > mechanism like __get_user_pages(). Otherwise, we have a problem
> > anyway when accessing the page via the kernel mapping.
> 
> Indeed. What I meant was user mapping inconsistent with the kernel
> mapping. It's the latter that needs flushing.
> 
> > > > Thus, continue to do lazy flushing if there are no user space mappings.
> > > > Otherwise, flush the kernel cache lines directly.
> > > ...
> > > >  /*
> > > > + * Ensure cache coherency for kernel mapping of this page.
> > > > + *
> > > > + * If the page only exists in the page cache and there are no user
> > > > + * space mappings, this is a no-op since the page was already marked
> > > > + * dirty at creation.  Otherwise, we need to flush the dirty kernel
> > > > + * cache lines directly.
> > > > + */
> > > > +void flush_kernel_dcache_page(struct page *page)
> > > > +{
> > > > +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> > > > +		struct address_space *mapping;
> > > > +
> > > > +		mapping = page_mapping(page);
> > > > +
> > > > +		if (!mapping || mapping_mapped(mapping))
> > > > +			__flush_kernel_dcache_page(page);
> > > > +	}
> > > > +}
> > > 
> > > BTW, does the mapping check optimise anything for the
> > > flush_kernel_dcache_page() uses? Would we have a mapping anyway (or
> > > anonymous page) in most cases?
> > 
> > Looking at the relevant uses in the kernel, we have:
> > 
> >     drivers/scsi/libsas/sas_host_smp.c
> >     drivers/mmc/host/mmc_spi.c
> >     drivers/block/ps3disk.c
> >     fs/exec.c
> >     lib/scatterlist.c
> >  
> > That is not much (I omit my usual rant here that many uses of
> > flush_dcache_page() in drivers are incorrect and should be uses of
> > flush_kernel_dcache_page() ...).
> > 
> > Without looking at the actual code, we seem to have two basic use
> > cases:
> > 
> > 1. Block drivers (the ones listed above + those using the memory
> > scatterlist iterator in scatterlist.c)
> > 
> > These will probably almost exclusively use page cache pages for which
> > we can be lazy.  Other pages only occur in special I/O situations
> > like direct I/O.
> > 
> > 2. fs/exec.c
> > 
> > I think these are anonymous pages only
> > 
> > Thus depending on the actual drivers used, usage can be dominated by
> > page cache pages on one setup and anon pages on the other.
> > 
> > I prefer the currently proposed way since it prevents massive
> > overflushing if flush_kernel_dcache_page() is used in an I/O path.
> > 
> > (Btw. I am still puzzled as to why making flush_kernel_dcache_page()
> > the current nop apparently did not cause problems in fs/exec.c.)
> 
> We get extra flushing via flush_old_exec() -> exec_mmap() -> mmput() ->
> exit_mmap() -> flush_cache_mm() before we actually start the new exec so
> this would flush the arg page as well.
> 
> > > Otherwise the patch looks good.
> > 
> > Thanks. Especially, thanks for pointing out the highmem case.
> 
> You can add my ack (before I forget the whole discussion ;))
> 
> Acked-by: Catalin Marinas <catalin.marinas at arm.com>

wrt to 73be1591, this appears to go all the way back to v2.6.31.x... Can
Simon go ahead and put this in rmk's patch tracker and mention that it
should go to all -stable trees?

thx,

Jason.


From manjunath.goudar at linaro.org  Fri May 31 08:08:38 2013
From: manjunath.goudar at linaro.org (manjunath.goudar at linaro.org)
Date: Fri, 31 May 2013 17:38:38 +0530
Subject: [PATCH V2 0/2] USB: OHCI: Splitting ohci-platform into independent
 driver
In-Reply-To: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
References: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
Message-ID: <51a892d6.3077420a.5699.0f80@mx.google.com>

From: Manjunath Goudar <manjunath.goudar at linaro.org>

This series patch begins the process of splitting ohci-platform up
into independent driver modules and add a name for the platform-private field.

Patch 1/2 separate ohci-platform into independent driver modules.

V1 to V2:
Passed "hcd" argment instead of "ohci" in ohci_setup().

Patch 2/2 adds an ohci->priv field for private use by OHCI platform drivers.
V1 to V2:
No changes. 


Manjunath Goudar (2):
  USB: OHCI: make ohci-platform a separate driver
  USB: OHCI: add a name for the platform-private field

 drivers/usb/host/Kconfig         |    2 +-
 drivers/usb/host/Makefile        |    1 +
 drivers/usb/host/ohci-hcd.c      |    6 +--
 drivers/usb/host/ohci-platform.c |   88 ++++++++++++++++++--------------------
 drivers/usb/host/ohci.h          |    3 ++
 5 files changed, 47 insertions(+), 53 deletions(-)

-- 
1.7.9.5



From manjunath.goudar at linaro.org  Fri May 31 08:08:39 2013
From: manjunath.goudar at linaro.org (manjunath.goudar at linaro.org)
Date: Fri, 31 May 2013 17:38:39 +0530
Subject: [PATCH V2 1/2] USB: OHCI: make ohci-platform a separate driver
In-Reply-To: <1370002120-19495-1-git-send-email-y>
References: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
 <1370002120-19495-1-git-send-email-y>
Message-ID: <51a892db.3077420a.5699.0f88@mx.google.com>

From: Manjunath Goudar <manjunath.goudar at linaro.org>

This patch splits the ohci-platform code from ohci-hcd out
into its own separate driver module.This work is part of enabling
multi-platform kernels on ARM.

In V2:
  -Passed "hcd" argment instead of "ohci" in ohci_setup() because it is
   using "struct usb_hcd" argment.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Acked-by: Alan Stern <stern at rowland.harvard.edu>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/Kconfig         |    2 +-
 drivers/usb/host/Makefile        |    1 +
 drivers/usb/host/ohci-hcd.c      |    6 +--
 drivers/usb/host/ohci-platform.c |   88 ++++++++++++++++++--------------------
 4 files changed, 44 insertions(+), 53 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a0a2f3a..5391a38 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -501,7 +501,7 @@ config USB_CNS3XXX_OHCI
 	  It is needed for low-speed USB 1.0 device support.
 
 config USB_OHCI_HCD_PLATFORM
-	bool "Generic OHCI driver for a platform device"
+	tristate "Generic OHCI driver for a platform device"
 	default n
 	---help---
 	  Adds an OHCI host driver for a generic platform device, which
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 2214ded..8a89c3d 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_USB_ISP1362_HCD)	+= isp1362-hcd.o
 
 obj-$(CONFIG_USB_OHCI_HCD)	+= ohci-hcd.o
 obj-$(CONFIG_USB_OHCI_HCD_PCI)	+= ohci-pci.o
+obj-$(CONFIG_USB_OHCI_HCD_PLATFORM)	+= ohci-platform.o
 
 obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 237be7c..39c7624 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1258,12 +1258,8 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_tilegx_driver
 #endif
 
-#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
-#include "ohci-platform.c"
-#define PLATFORM_DRIVER		ohci_platform_driver
-#endif
-
 #if	!IS_ENABLED(CONFIG_USB_OHCI_HCD_PCI) &&	\
+	!IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM) && \
 	!defined(PLATFORM_DRIVER) &&	\
 	!defined(OMAP1_PLATFORM_DRIVER) &&	\
 	!defined(OMAP3_PLATFORM_DRIVER) &&	\
diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
index 76a3531..288feed 100644
--- a/drivers/usb/host/ohci-platform.c
+++ b/drivers/usb/host/ohci-platform.c
@@ -13,16 +13,28 @@
  *
  * Licensed under the GNU/GPL. See COPYING for details.
  */
+
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/usb/ohci_pdriver.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "ohci.h"
+
+#define DRIVER_DESC "OHCI generic platform driver"
+
+static const char hcd_name[] = "ohci-platform";
 
 static int ohci_platform_reset(struct usb_hcd *hcd)
 {
 	struct platform_device *pdev = to_platform_device(hcd->self.controller);
 	struct usb_ohci_pdata *pdata = pdev->dev.platform_data;
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int err;
 
 	if (pdata->big_endian_desc)
 		ohci->flags |= OHCI_QUIRK_BE_DESC;
@@ -30,58 +42,17 @@ static int ohci_platform_reset(struct usb_hcd *hcd)
 		ohci->flags |= OHCI_QUIRK_BE_MMIO;
 	if (pdata->no_big_frame_no)
 		ohci->flags |= OHCI_QUIRK_FRAME_NO;
-
-	ohci_hcd_init(ohci);
-
 	if (pdata->num_ports)
 		ohci->num_ports = pdata->num_ports;
 
-	err = ohci_init(ohci);
-
-	return err;
-}
-
-static int ohci_platform_start(struct usb_hcd *hcd)
-{
-	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int err;
-
-	err = ohci_run(ohci);
-	if (err < 0) {
-		ohci_err(ohci, "can't start\n");
-		ohci_stop(hcd);
-	}
-
-	return err;
+	return ohci_setup(ohci_to_hcd(ohci));
 }
 
-static const struct hc_driver ohci_platform_hc_driver = {
-	.description		= hcd_name,
-	.product_desc		= "Generic Platform OHCI Controller",
-	.hcd_priv_size		= sizeof(struct ohci_hcd),
+static struct hc_driver __read_mostly ohci_platform_hc_driver;
 
-	.irq			= ohci_irq,
-	.flags			= HCD_MEMORY | HCD_USB11,
-
-	.reset			= ohci_platform_reset,
-	.start			= ohci_platform_start,
-	.stop			= ohci_stop,
-	.shutdown		= ohci_shutdown,
-
-	.urb_enqueue		= ohci_urb_enqueue,
-	.urb_dequeue		= ohci_urb_dequeue,
-	.endpoint_disable	= ohci_endpoint_disable,
-
-	.get_frame_number	= ohci_get_frame,
-
-	.hub_status_data	= ohci_hub_status_data,
-	.hub_control		= ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend		= ohci_bus_suspend,
-	.bus_resume		= ohci_bus_resume,
-#endif
-
-	.start_port_reset	= ohci_start_port_reset,
+static const struct ohci_driver_overrides platform_overrides __initconst = {
+	.product_desc =	"Generic Platform OHCI controller",
+	.reset =	ohci_platform_reset,
 };
 
 static int ohci_platform_probe(struct platform_device *dev)
@@ -222,3 +193,26 @@ static struct platform_driver ohci_platform_driver = {
 		.pm	= &ohci_platform_pm_ops,
 	}
 };
+
+static int __init ohci_platform_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_platform_hc_driver, &platform_overrides);
+	return platform_driver_register(&ohci_platform_driver);
+}
+module_init(ohci_platform_init);
+
+static void __exit ohci_platform_cleanup(void)
+{
+	platform_driver_unregister(&ohci_platform_driver);
+}
+module_exit(ohci_platform_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Hauke Mehrtens");
+MODULE_AUTHOR("Alan Stern");
+MODULE_LICENSE("GPL");
-- 
1.7.9.5



From manjunath.goudar at linaro.org  Fri May 31 08:08:40 2013
From: manjunath.goudar at linaro.org (manjunath.goudar at linaro.org)
Date: Fri, 31 May 2013 17:38:40 +0530
Subject: [PATCH V2 2/2] USB: OHCI: add a name for the platform-private field
In-Reply-To: <1370002120-19495-1-git-send-email-y>
References: <1369907454-11003-1-git-send-email-manjunath.goudar@linaro.org>
 <1370002120-19495-1-git-send-email-y>
Message-ID: <51a892e0.3077420a.5699.0f8c@mx.google.com>

From: Manjunath Goudar <manjunath.goudar at linaro.org>

This patch adds an ohci->priv field for private use by OHCI
platform drivers.

Until now none of the platform drivers has used this private space,
but that's about to change in the next patch of this series.

In V2:
No changes.

Signed-off-by: Manjunath Goudar <manjunath.goudar at linaro.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Greg KH <greg at kroah.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
---
 drivers/usb/host/ohci.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index 3b58482..e2e5faa 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -421,6 +421,9 @@ struct ohci_hcd {
 	struct dentry		*debug_periodic;
 	struct dentry		*debug_registers;
 #endif
+	/* platform-specific data -- must come last */
+	unsigned long           priv[0] __aligned(sizeof(s64));
+
 };
 
 #ifdef CONFIG_PCI
-- 
1.7.9.5



From tushar.behera at linaro.org  Fri May 31 07:49:02 2013
From: tushar.behera at linaro.org (Tushar Behera)
Date: Fri, 31 May 2013 17:19:02 +0530
Subject: [PATCH 1/3] ARM: EXYNOS: uncompress - print debug messages if
 DEBUG_LL is defined
In-Reply-To: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
References: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1370000944-19786-2-git-send-email-tushar.behera@linaro.org>

Printing low-level debug messages make an assumption that the specified
UART port has been preconfigured by the bootloader. Incorrectly
specified UART port results in system getting stalled while printing the
message "Uncompressing Linux... done, booting the kernel"

This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since
the UART port might different for different board, it is not possible to
specify it correctly for every board that use a common defconfig file.

Calling this print subroutine only when DEBUG_LL fixes the problem. By
disabling DEBUG_LL in default config file, we would be able to boot
multiple boards with different default UART ports.

With this current approach, we miss the print "Uncompressing Linux...
done, booting the kernel." when DEBUG_LL is not defined.

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-exynos/include/mach/uncompress.h  |   11 ++++++++---
 arch/arm/plat-samsung/include/plat/uncompress.h |   10 +++++++++-
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 2979995..730f69f 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -37,11 +37,16 @@ static void arch_detect_cpu(void)
 	chip_id >>= 20;
 	chip_id &= 0xf;
 
+#ifdef CONFIG_DEBUG_LL
 	if (chip_id == 0x5)
-		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+		uart_base = (volatile u8 *)EXYNOS5_PA_UART +
+			(S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 	else
-		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-
+		uart_base = (volatile u8 *)EXYNOS4_PA_UART +
+			(S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+	uart_base = NULL;
+#endif
 	/*
 	 * For preventing FIFO overrun or infinite loop of UART console,
 	 * fifo_max should be the minimum fifo size of all of the UART channels
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 438b248..350032b 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -66,6 +66,9 @@ uart_rd(unsigned int reg)
 
 static void putc(int ch)
 {
+	if (!uart_base)
+		return;
+
 	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
 		int level;
 
@@ -118,7 +121,12 @@ static void arch_decomp_error(const char *x)
 #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
 static inline void arch_enable_uart_fifo(void)
 {
-	u32 fifocon = uart_rd(S3C2410_UFCON);
+	u32 fifocon;
+
+	if (!uart_base)
+		return;
+
+	fifocon = uart_rd(S3C2410_UFCON);
 
 	if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
 		fifocon |= S3C2410_UFCON_RESETBOTH;
-- 
1.7.9.5



From grant.likely at secretlab.ca  Fri May 31 08:21:00 2013
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 31 May 2013 13:21:00 +0100
Subject: [PATCH 2/2] ARM: shmobile: irqpin: map spurious interrupts in DT
 case
In-Reply-To: <Pine.LNX.4.64.1305241112210.1090@axis700.grange>
References: <Pine.LNX.4.64.1305241109530.1090@axis700.grange>
 <Pine.LNX.4.64.1305241112210.1090@axis700.grange>
Message-ID: <20130531122100.BEC173E0901@localhost>

On Fri, 24 May 2013 11:13:07 +0200 (CEST), Guennadi Liakhovetski <g.liakhovetski at gmx.de> wrote:
> In the non-DT case all interrupts get mapped statically during probing,
> therefore, if a spurious interrupt arrives, it can easily be mapped back
> to hardware registers and bits and handled. In the DT case interrupts are
> mapped only when a device, using that interrupt is instantiated from DT.
> So, spurious interrupts occur unmapped and thus cannot be handled properly.
> This patch fixes this by mapping such interrupts as they occur.

That sounds like a bad approach. If the driver really requires the irqs
to be mapped, then it should do all of them when the controller is set
up. Mapping at interrupt handling time is absolutely the wrong time to
do it.

Also, why is mapping the irq necessary to handle it? You don't want to
call generic_handle_irq() on a bad interrupt because there won't be
anything listening for it. First of all, that particular irq should be
entirely disabled if at all possible. Second, if it isn't possible to
disable it, then the handler function should clear the state and get out
of the handler as quickly as possible.

g.

> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> ---
>  drivers/irqchip/irq-renesas-intc-irqpin.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
> index 82cec63..e62d76d 100644
> --- a/drivers/irqchip/irq-renesas-intc-irqpin.c
> +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
> @@ -71,6 +71,7 @@ struct intc_irqpin_priv {
>  	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
>  	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
>  	struct renesas_intc_irqpin_config config;
> +	unsigned int min_irq;
>  	unsigned int number_of_irqs;
>  	struct platform_device *pdev;
>  	struct irq_chip irq_chip;
> @@ -274,6 +275,10 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
>  	struct intc_irqpin_priv *p = i->p;
>  	unsigned long bit;
>  
> +	if (!i->domain_irq)
> +		/* unmapped: spurious IRQ, map it now */
> +		irq_create_mapping(p->irq_domain, irq - p->min_irq);
> +
>  	intc_irqpin_dbg(i, "demux1");
>  	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
>  
> @@ -372,6 +377,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	p->min_irq = INT_MAX;
>  	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
>  	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
>  		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
> @@ -380,6 +386,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
>  
>  		p->irq[k].p = p;
>  		p->irq[k].requested_irq = irq->start;
> +		if (p->min_irq > irq->start)
> +			p->min_irq = irq->start;
>  	}
>  
>  	p->number_of_irqs = k;
> -- 
> 1.7.2.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.


From 21cnbao at gmail.com  Fri May 31 08:24:43 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 31 May 2013 20:24:43 +0800
Subject: [PATCH v1 1/2] ARM:prima2: move sirfsoc_of_rstc_init to
 .init_early
In-Reply-To: <1369993501-24309-1-git-send-email-srinivas.kandagatla@st.com>
References: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
 <1369993501-24309-1-git-send-email-srinivas.kandagatla@st.com>
Message-ID: <CAGsJ_4z65+SOCQM2XKmrda+5Hu9wRuZviSvW3As1ROa0SmdXqw@mail.gmail.com>

2013/5/31 Srinivas KANDAGATLA <srinivas.kandagatla at st.com>:
> From: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>
> This patch moves sirfsoc_of_rstc_init from early_initcall to .init_early
> in machine descriptor, doing this way a multi_v7 kernel will not crash
> on non-prima2 SOCs.
>
> Without this patch the multi_v7 kernel panics if we boot it on any non
> prima2 parts with below log:
>
> Kernel panic - not syncing: unable to find compatible rstc node in dtb
>
> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc3-00535-gc3cc4ac #62
> [<c001387c>] (unwind_backtrace+0x0/0xf8) from [<c00111cc>]
> (show_stack+0x10/0x14)
> [<c00111cc>] (show_stack+0x10/0x14) from [<c03417f4>] (panic+0x90/0x1e4)
> [<c03417f4>] (panic+0x90/0x1e4) from [<c04256d0>]
> (sirfsoc_of_rstc_init+0x24/0x5c)
> [<c04256d0>] (sirfsoc_of_rstc_init+0x24/0x5c) from [<c041f854>]
> (do_one_initcall+0x90/0x150)
> [<c041f854>] (do_one_initcall+0x90/0x150) from [<c041f978>]
> (kernel_init_freeable+0x64/0x1c4)
> [<c041f978>] (kernel_init_freeable+0x64/0x1c4) from [<c033d344>]
> (kernel_init+0x8/0xe4)
> [<c033d344>] (kernel_init+0x8/0xe4) from [<c000ded8>]
> (ret_from_fork+0x14/0x3c)
>
> Initially detected when booting Stih415 SOC with multi_v7_defconfig.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>

hi Sriniva,
i think my "arm: prima2: move to generic reset controller driver
framework" fixs this too:
http://www.spinics.net/lists/arm-kernel/msg246206.html

Arnd, will you ack that one so that i will send a pull request with that.

-barry


From vikas.sajjan at linaro.org  Fri May 31 08:31:30 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:30 +0530
Subject: [PATCH v3 0/6] Add generic set_rate clk_ops for PLL35xx and PLL36xx
 for samsung SoCs
Message-ID: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>

This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
    for PLL35xx & PLL36xx and usues clk->base instead of clk->con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
    values for supported rates that needs to be changed for changing
    corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35xx and PLL36xx

changes since v2:
	- Added new patch to reorder the MUX registration for mout_vpllsrc MUX
	before the PLL registrations. And to add the alias for the mout_vpllsrc MUX.
        - Added a check to confirm parent rate while registrating the PLL
	rate tables.

changes since v1:
	- removed sorting and bsearch
	- modified the definition of struct "samsung_pll_rate_table"
	- added generic round_rate()
	- rectified the ops assignment for "rate table passed as NULL"
	  during PLL registration

Is rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome tree.


Vikas Sajjan (3):
  clk: samsung: Add set_rate() clk_ops for PLL36xx
  clk: samsung: Add alias for mout_vpllsrc and reorder MUX registration
    for it
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk->base instead of directly using clk->con0 for
    PLL3xxx
  clk: samsung: Add support to register rate_table for PLL3xxx
  clk: samsung: Add set_rate() clk_ops for PLL35xx

 drivers/clk/samsung/clk-exynos4.c    |   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   69 +++++++++--
 drivers/clk/samsung/clk-pll.c        |  226 ++++++++++++++++++++++++++++++----
 drivers/clk/samsung/clk-pll.h        |   35 +++++-
 drivers/clk/samsung/clk.h            |    2 +
 5 files changed, 300 insertions(+), 42 deletions(-)

-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 31 08:31:31 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:31 +0530
Subject: [PATCH v3 1/6] clk: samsung: Use clk->base instead of directly using
 clk->con0 for PLL3xxx
In-Reply-To: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1370003496-19288-2-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.

Reviewed-by: Tomasz Figa <t.figa at samsung.com>
Reviewed-by: Doug Anderson <dianders at chromium.org>
Tested-by: Doug Anderson <dianders at chromium.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |   10 ++++---
 drivers/clk/samsung/clk-exynos5250.c |   14 ++++-----
 drivers/clk/samsung/clk-pll.c        |   54 ++++++++++++++++++----------------
 drivers/clk/samsung/clk-pll.h        |    4 +--
 4 files changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e6..cf7d4e7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -97,12 +97,14 @@
 #define GATE_IP_PERIL		0xc950
 #define E4210_GATE_IP_PERIR	0xc960
 #define GATE_BLOCK		0xc970
+#define E4X12_MPLL_LOCK		0x10008
 #define E4X12_MPLL_CON0		0x10108
 #define SRC_DMC			0x10200
 #define SRC_MASK_DMC		0x10300
 #define DIV_DMC0		0x10500
 #define DIV_DMC1		0x10504
 #define GATE_IP_DMC		0x10900
+#define APLL_LOCK		0x14000
 #define APLL_CON0		0x14100
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
@@ -1019,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
 					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-					reg_base + APLL_CON0);
+					reg_base + APLL_LOCK);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-					reg_base + E4X12_MPLL_CON0);
+					reg_base + E4X12_MPLL_LOCK);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + EPLL_CON0);
+					reg_base + EPLL_LOCK);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + VPLL_CON0);
+					reg_base + VPLL_LOCK);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..687b580 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ext_clk_match);
 
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-			reg_base + 0x100);
+			reg_base);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-			reg_base + 0x4100);
+			reg_base + 0x4000);
 	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
-			reg_base + 0x20110);
+			reg_base + 0x20010);
 	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
-			reg_base + 0x10150);
+			reg_base + 0x10050);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
-			reg_base + 0x10120);
+			reg_base + 0x10020);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10130);
+			reg_base + 0x10030);
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10140);
+			reg_base + 0x10040);
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..a7d8ad9 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -13,9 +13,24 @@
 #include "clk.h"
 #include "clk-pll.h"
 
+struct samsung_clk_pll {
+	struct clk_hw		hw;
+	const void __iomem	*base;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+#define pll_readl(pll, offset)						\
+		__raw_readl((void __iomem *)(pll->base + (offset)));
+#define pll_writel(pll, val, offset)					\
+		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
+
 /*
  * PLL35xx Clock Type
  */
+#define PLL35XX_LOCK_OFFSET	(0x0)
+#define PLL35XX_CON0_OFFSET	(0x100)
+#define PLL35XX_CON1_OFFSET	(0x104)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -24,21 +39,14 @@
 #define PLL35XX_PDIV_SHIFT      (8)
 #define PLL35XX_SDIV_SHIFT      (0)
 
-struct samsung_clk_pll35xx {
-	struct clk_hw		hw;
-	const void __iomem	*con_reg;
-};
-
-#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
-
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
-	struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = pll_readl(pll, PLL35XX_CON0_OFFSET);
 	mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
 	pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
 	sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -54,9 +62,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *con_reg)
+			const char *pname, const void __iomem *base)
 {
-	struct samsung_clk_pll35xx *pll;
+	struct samsung_clk_pll *pll;
 	struct clk *clk;
 	struct clk_init_data init;
 
@@ -73,7 +81,7 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 	init.num_parents = 1;
 
 	pll->hw.init = &init;
-	pll->con_reg = con_reg;
+	pll->base = base;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
@@ -91,6 +99,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 /*
  * PLL36xx Clock Type
  */
+#define PLL36XX_LOCK_OFFSET	(0x0)
+#define PLL36XX_CON0_OFFSET	(0x100)
+#define PLL36XX_CON1_OFFSET	(0x104)
 
 #define PLL36XX_KDIV_MASK	(0xFFFF)
 #define PLL36XX_MDIV_MASK	(0x1FF)
@@ -100,22 +111,15 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_PDIV_SHIFT	(8)
 #define PLL36XX_SDIV_SHIFT	(0)
 
-struct samsung_clk_pll36xx {
-	struct clk_hw		hw;
-	const void __iomem	*con_reg;
-};
-
-#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
-
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
-	struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 4);
+	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -133,9 +137,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *con_reg)
+			const char *pname, const void __iomem *base)
 {
-	struct samsung_clk_pll36xx *pll;
+	struct samsung_clk_pll *pll;
 	struct clk *clk;
 	struct clk_init_data init;
 
@@ -152,7 +156,7 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 	init.num_parents = 1;
 
 	pll->hw.init = &init;
-	pll->con_reg = con_reg;
+	pll->base = base;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index f33786e..1329522 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,9 +25,9 @@ enum pll46xx_type {
 };
 
 extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *con_reg);
+			const char *pname, const void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *con_reg);
+			const char *pname, const void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll45xx_type type);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 31 08:31:32 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:32 +0530
Subject: [PATCH v3 2/6] clk: samsung: Add support to register rate_table for
 PLL3xxx
In-Reply-To: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1370003496-19288-3-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.

Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
 drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
 drivers/clk/samsung/clk-pll.c        |   14 ++++++++++++--
 drivers/clk/samsung/clk-pll.h        |   35 ++++++++++++++++++++++++++++++++--
 4 files changed, 56 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index cf7d4e7..beff8a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
 					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-					reg_base + APLL_LOCK);
+					reg_base + APLL_LOCK, NULL, 0);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-					reg_base + E4X12_MPLL_LOCK);
+					reg_base + E4X12_MPLL_LOCK, NULL, 0);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + EPLL_LOCK);
+					reg_base + EPLL_LOCK, NULL, 0);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + VPLL_LOCK);
+					reg_base + VPLL_LOCK, NULL, 0);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ext_clk_match);
 
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
-			reg_base);
+			reg_base, NULL, 0);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-			reg_base + 0x4000);
+			reg_base + 0x4000, NULL, 0);
 	bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
-			reg_base + 0x20010);
+			reg_base + 0x20010, NULL, 0);
 	gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
-			reg_base + 0x10050);
+			reg_base + 0x10050, NULL, 0);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
-			reg_base + 0x10020);
+			reg_base + 0x10020, NULL, 0);
 	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10030);
+			reg_base + 0x10030, NULL, 0);
 	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
-			reg_base + 0x10040);
+			reg_base + 0x10040, NULL, 0);
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index a7d8ad9..8226528 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -16,6 +16,8 @@
 struct samsung_clk_pll {
 	struct clk_hw		hw;
 	const void __iomem	*base;
+	const struct samsung_pll_rate_table *rate_table;
+	unsigned int rate_count;
 };
 
 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *base)
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -82,6 +86,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 
 	pll->hw.init = &init;
 	pll->base = base;
+	pll->rate_table = rate_table;
+	pll->rate_count = rate_count;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
@@ -137,7 +143,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *base)
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -157,6 +165,8 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 
 	pll->hw.init = &init;
 	pll->base = base;
+	pll->rate_table = rate_table;
+	pll->rate_count = rate_count;
 
 	clk = clk_register(NULL, &pll->hw);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 1329522..4780e6c 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -12,6 +12,33 @@
 #ifndef __SAMSUNG_CLK_PLL_H
 #define __SAMSUNG_CLK_PLL_H
 
+#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
+	{							\
+		.rate	=	(_rate),				\
+		.mdiv	=	(_m),				\
+		.pdiv	=	(_p),				\
+		.sdiv	=	(_s),				\
+	}
+
+#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
+	{							\
+		.rate	=	(_rate),				\
+		.mdiv	=	(_m),				\
+		.pdiv	=	(_p),				\
+		.sdiv	=	(_s),				\
+		.kdiv	=	(_k),				\
+	}
+
+/* NOTE: Rate table should be kept sorted in descending order. */
+
+struct samsung_pll_rate_table {
+	unsigned int rate;
+	unsigned int pdiv;
+	unsigned int mdiv;
+	unsigned int sdiv;
+	unsigned int kdiv;
+};
+
 enum pll45xx_type {
 	pll_4500,
 	pll_4502,
@@ -25,9 +52,13 @@ enum pll46xx_type {
 };
 
 extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
-			const char *pname, const void __iomem *base);
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count);
 extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
-			const char *pname, const void __iomem *base);
+			const char *pname, const void __iomem *base,
+			const struct samsung_pll_rate_table *rate_table,
+			const unsigned int rate_count);
 extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll45xx_type type);
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 31 08:31:33 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:33 +0530
Subject: [PATCH v3 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx
In-Reply-To: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1370003496-19288-4-git-send-email-vikas.sajjan@linaro.org>

From: Yadwinder Singh Brar <yadi.brar at samsung.com>

This patch add set_rate() and round_rate() for PLL35xx

Reviewed-by: Doug Anderson <dianders at chromium.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-pll.c |  103 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 8226528..9591560 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -27,6 +27,36 @@ struct samsung_clk_pll {
 #define pll_writel(pll, val, offset)					\
 		__raw_writel(val, (void __iomem *)(pll->base + (offset)));
 
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+				struct samsung_clk_pll *pll, unsigned long rate)
+{
+	const struct samsung_pll_rate_table  *rate_table = pll->rate_table;
+	int i;
+
+	for (i = 0; i < pll->rate_count; i++) {
+		if (rate == rate_table[i].rate)
+			return &rate_table[i];
+	}
+
+	return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+			unsigned long drate, unsigned long *prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+	int i;
+
+	/* Assumming rate_table is in descending order */
+	for (i = 0; i < pll->rate_count; i++) {
+		if (drate >= rate_table[i].rate)
+			return rate_table[i].rate;
+	}
+
+	/* return minimum supported value */
+	return rate_table[i - 1].rate;
+}
 /*
  * PLL35xx Clock Type
  */
@@ -34,12 +64,17 @@ struct samsung_clk_pll {
 #define PLL35XX_CON0_OFFSET	(0x100)
 #define PLL35XX_CON1_OFFSET	(0x104)
 
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR	(270)
+
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
 #define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_LOCK_STAT_MASK  (0x1)
 #define PLL35XX_MDIV_SHIFT      (16)
 #define PLL35XX_PDIV_SHIFT      (8)
 #define PLL35XX_SDIV_SHIFT      (0)
+#define PLL35XX_LOCK_STAT_SHIFT	(29)
 
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
@@ -59,8 +94,70 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+	if ((mdiv != ((pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK)) ||
+		(pdiv != ((pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK)))
+		return 1;
+	else
+		return 0;
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate;
+	u32 tmp;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+	if (!(samsung_pll35xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+		/* If only s change, change just s value only*/
+		tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
+		tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
+		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+	} else {
+		/* Set PLL lock time. */
+		pll_writel(pll, rate->pdiv * PLL35XX_LOCK_FACTOR,
+				PLL35XX_LOCK_OFFSET);
+
+		/* Change PLL PMS values */
+		tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
+				(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
+				(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
+		tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
+				(rate->pdiv << PLL35XX_PDIV_SHIFT) |
+				(rate->sdiv << PLL35XX_SDIV_SHIFT);
+		pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+		/* wait_lock_time */
+		do {
+			cpu_relax();
+			tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+		} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
+				<< PLL35XX_LOCK_STAT_SHIFT)));
+	}
+
+	return 0;
+}
+
 static const struct clk_ops samsung_pll35xx_clk_ops = {
 	.recalc_rate = samsung_pll35xx_recalc_rate,
+	.round_rate = samsung_pll_round_rate,
+	.set_rate = samsung_pll35xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll35xx_clk_min_ops = {
+	.recalc_rate = samsung_pll35xx_recalc_rate,
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
@@ -79,11 +176,15 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 	}
 
 	init.name = name;
-	init.ops = &samsung_pll35xx_clk_ops;
 	init.flags = CLK_GET_RATE_NOCACHE;
 	init.parent_names = &pname;
 	init.num_parents = 1;
 
+	if (rate_table && rate_count)
+		init.ops = &samsung_pll35xx_clk_ops;
+	else
+		init.ops = &samsung_pll35xx_clk_min_ops;
+
 	pll->hw.init = &init;
 	pll->base = base;
 	pll->rate_table = rate_table;
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 31 08:31:34 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:34 +0530
Subject: [PATCH v3 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx
In-Reply-To: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1370003496-19288-5-git-send-email-vikas.sajjan@linaro.org>

This patch adds set_rate and round_rate clk_ops for PLL36xx

Reviewed-by: Doug Anderson <dianders at chromium.org>
Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
---
 drivers/clk/samsung/clk-pll.c |   59 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 9591560..7143ed89 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -210,6 +210,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_CON0_OFFSET	(0x100)
 #define PLL36XX_CON1_OFFSET	(0x104)
 
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR	(3000)
+
 #define PLL36XX_KDIV_MASK	(0xFFFF)
 #define PLL36XX_MDIV_MASK	(0x1FF)
 #define PLL36XX_PDIV_MASK	(0x3F)
@@ -217,6 +220,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
 #define PLL36XX_MDIV_SHIFT	(16)
 #define PLL36XX_PDIV_SHIFT	(8)
 #define PLL36XX_SDIV_SHIFT	(0)
+#define PLL36XX_KDIV_SHIFT	(0)
+#define PLL36XX_LOCK_STAT_SHIFT	(29)
 
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
@@ -239,8 +244,57 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 tmp, pll_con0, pll_con1;
+	const struct samsung_pll_rate_table *rate;
+
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
+
+	/* Set PLL lock time. */
+	pll_writel(pll, (rate->pdiv * PLL36XX_LOCK_FACTOR),
+			PLL36XX_LOCK_OFFSET);
+
+	 /* Change PLL PMS values */
+	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
+			(PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
+			(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
+	pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
+			(rate->pdiv << PLL36XX_PDIV_SHIFT) |
+			(rate->sdiv << PLL36XX_SDIV_SHIFT);
+	pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+	pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
+	pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
+	pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+	/* wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+	} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
+
+	return 0;
+}
+
 static const struct clk_ops samsung_pll36xx_clk_ops = {
 	.recalc_rate = samsung_pll36xx_recalc_rate,
+	.set_rate = samsung_pll36xx_set_rate,
+	.round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+	.recalc_rate = samsung_pll36xx_recalc_rate,
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -264,6 +318,11 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
 	init.parent_names = &pname;
 	init.num_parents = 1;
 
+	if (rate_table && rate_count)
+		init.ops = &samsung_pll36xx_clk_ops;
+	else
+		init.ops = &samsung_pll36xx_clk_min_ops;
+
 	pll->hw.init = &init;
 	pll->base = base;
 	pll->rate_table = rate_table;
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 31 08:31:35 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:35 +0530
Subject: [PATCH v3 5/6] clk: samsung: Add alias for mout_vpllsrc and reorder
 MUX registration for it
In-Reply-To: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1370003496-19288-6-git-send-email-vikas.sajjan@linaro.org>

While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the
"fout_vpll" (child), we found get rate was failing.

So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.
Its also adds the alias for the mout_vpllsrc MUX.

Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
---
 drivers/clk/samsung/clk-exynos5250.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ddf10ca..b0e6680 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -207,6 +207,11 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
 	FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
 };
 
+struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
+	MUX_A(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1,
+			"mout_vpllsrc"),
+};
+
 struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
 	MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
@@ -214,7 +219,6 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
 	MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
 	MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
-	MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
 	MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
 	MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
 	MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
@@ -490,6 +494,9 @@ void __init exynos5250_clk_init(struct device_node *np)
 			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
 			ext_clk_match);
 
+	samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+			ARRAY_SIZE(exynos5250_pll_pmux_clks));
+
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
 			reg_base, NULL, 0);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
-- 
1.7.9.5



From vikas.sajjan at linaro.org  Fri May 31 08:31:36 2013
From: vikas.sajjan at linaro.org (Vikas Sajjan)
Date: Fri, 31 May 2013 18:01:36 +0530
Subject: [PATCH v3 6/6] clk: samsung: Add EPLL and VPLL freq table for
 exynos5250 SoC
In-Reply-To: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <1370003496-19288-7-git-send-email-vikas.sajjan@linaro.org>

Adds the EPLL and VPLL freq table for exynos5250 SoC.

Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |   48 +++++++++++++++++++++++++++++++---
 drivers/clk/samsung/clk.h            |    2 ++
 2 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index b0e6680..0566421 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -473,11 +473,32 @@ static __initdata struct of_device_id ext_clk_match[] = {
 	{ },
 };
 
+static const struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
+	/* sorted in descending order */
+	/* PLL_36XX_RATE(rate, m, p, s, k) */
+	PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+	PLL_36XX_RATE(70500000, 94, 2, 4, 0),
+};
+
+static const struct samsung_pll_rate_table epll_24mhz_tbl[] = {
+	/* sorted in descending order */
+	/* PLL_36XX_RATE(rate, m, p, s, k) */
+	PLL_36XX_RATE(192000000, 48, 3, 1, 0),
+	PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+	PLL_36XX_RATE(180000000, 45, 3, 1, 0),
+	PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+	PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+	PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+	PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+	PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
 /* register exynox5250 clocks */
 void __init exynos5250_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
 	struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+	unsigned long fin_pll_rate, mout_vpllsrc_rate;
 
 	if (np) {
 		reg_base = of_iomap(np, 0);
@@ -497,6 +518,9 @@ void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_register_mux(exynos5250_pll_pmux_clks,
 			ARRAY_SIZE(exynos5250_pll_pmux_clks));
 
+	fin_pll_rate = _get_rate("fin_pll");
+	mout_vpllsrc_rate = _get_rate("mout_vpllsrc");
+
 	apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
 			reg_base, NULL, 0);
 	mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
@@ -507,10 +531,28 @@ void __init exynos5250_clk_init(struct device_node *np)
 			reg_base + 0x10050, NULL, 0);
 	cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
 			reg_base + 0x10020, NULL, 0);
-	epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-			reg_base + 0x10030, NULL, 0);
-	vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
+
+	if (fin_pll_rate == (24 * MHZ)) {
+		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+				reg_base + 0x10030, epll_24mhz_tbl,
+				ARRAY_SIZE(epll_24mhz_tbl));
+	} else {
+		pr_warn("Exynos5250: valid epll rate_table missing for\n"
+			"parent fin_pll:%lu hz\n", fin_pll_rate);
+		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+				reg_base + 0x10030, NULL, 0);
+	}
+
+	if (mout_vpllsrc_rate == (24 * MHZ)) {
+		vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc"
+			, reg_base + 0x10040, vpll_24mhz_tbl,
+			ARRAY_SIZE(vpll_24mhz_tbl));
+	} else {
+		pr_warn("Exynos5250: valid vpll rate_table missing for\n"
+			"parent mout_vpllsrc_rate:%lu hz\n", mout_vpllsrc_rate);
+		samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
 			reg_base + 0x10040, NULL, 0);
+	}
 
 	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index e4ad6ea..c997649 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -20,6 +20,8 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#define MHZ (1000*1000)
+
 /**
  * struct samsung_clock_alias: information about mux clock
  * @id: platform specific id of the clock.
-- 
1.7.9.5



From florian.vaussard at epfl.ch  Fri May 31 08:32:58 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:32:58 +0200
Subject: [PATCH v4 4/5] ARM: dts: OMAP2+: Header file for pinctrl constants
In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370003579-30219-5-git-send-email-florian.vaussard@epfl.ch>

Most of the constants are taken from arch/arm/mach-omap2/mux.h.
Define some others for the PIN_OUTPUT_* flavours.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Reviewed-by: Stephen Warren <swarren at nvidia.com>
---
 include/dt-bindings/pinctrl/omap.h |   50 ++++++++++++++++++++++++++++++++++++
 1 files changed, 50 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/omap.h

diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
new file mode 100644
index 0000000..370df3f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -0,0 +1,50 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA		(1 << 3)
+#define PULL_UP			(1 << 4)
+#define ALTELECTRICALSEL	(1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN		(1 << 8)
+#define OFF_EN			(1 << 9)
+#define OFFOUT_EN		(1 << 10)
+#define OFFOUT_VAL		(1 << 11)
+#define OFF_PULL_EN		(1 << 12)
+#define OFF_PULL_UP		(1 << 13)
+#define WAKEUP_EN		(1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT		0
+#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE		0
+#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
+
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:32:56 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:32:56 +0200
Subject: [PATCH v4 2/5] ARM: dts: OMAP2+: Use existing constants for GPIOs
In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370003579-30219-3-git-send-email-florian.vaussard@epfl.ch>

Use standard GPIO constants to enhance the readability of DT GPIOs.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Reviewed-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 ++
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    6 +++---
 arch/arm/boot/dts/omap3-devkit8000.dts    |    6 +++---
 arch/arm/boot/dts/omap3-evm.dts           |    2 +-
 arch/arm/boot/dts/omap3-igep0020.dts      |    8 ++++----
 arch/arm/boot/dts/omap3-igep0030.dts      |    8 ++++----
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 ++
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-sdp.dts           |   16 ++++++++--------
 arch/arm/boot/dts/omap4.dtsi              |    2 ++
 arch/arm/boot/dts/omap5.dtsi              |    2 ++
 13 files changed, 36 insertions(+), 28 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index e6e4587..f39b237 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index e0ce823..1e580d9 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -29,13 +29,13 @@
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index fcac96a..434288f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -28,18 +28,18 @@
 		compatible = "gpio-leds";
 		pmu_stat {
 			label = "beagleboard::pmu_stat";
-			gpios = <&twl_gpio 19 0>; /* LEDB */
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 		};
 
 		heartbeat {
 			label = "beagleboard::usr0";
-			gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "beagleboard::usr1";
-			gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8d0f5e4..5be71b1 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -22,21 +22,21 @@
 
 		heartbeat {
 			label = "devkit8000::led1";
-			gpios = <&gpio6 26 0>;	/* 186 -> LED1 */
+			gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;	/* 186 -> LED1 */
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "devkit8000::led2";
-			gpios = <&gpio6 3 0>;	/* 163 -> LED2 */
+			gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;	/* 163 -> LED2 */
 			default-state = "on";
 			linux,default-trigger = "none";
 		};
 
 		usr {
 			label = "devkit8000::led3";
-			gpios = <&gpio6 4 0>;	/* 164 -> LED3 */
+			gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;	/* 164 -> LED3 */
 			default-state = "on";
 			linux,default-trigger = "usr";
                 };
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index d75759b..baa24bb 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -28,7 +28,7 @@
 		compatible = "gpio-leds";
 		ledb {
 			label = "omap3evm::ledb";
-			gpios = <&twl_gpio 19 0>; /* LEDB */
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 			linux,default-trigger = "default-on";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index c50ce59..e8c4828 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -19,25 +19,25 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&gpio1 26 0>;
+			 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&gpio1 27 0>;
+			 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 28 0>;
+			 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 			 default-state = "off";
 		};
 
 		user2 {
 			label = "omap3:green:user1";
-			gpios = <&twl_gpio 19 1>;
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 5061a27..644d053 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -19,25 +19,25 @@
 		compatible = "gpio-leds";
 		boot {
 			 label = "omap3:green:boot";
-			 gpios = <&twl_gpio 13 1>;
+			 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
 			 default-state = "on";
 		};
 
 		user0 {
 			 label = "omap3:red:user0";
-			 gpios = <&twl_gpio 18 1>; /* LEDA */
+			 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
 			 default-state = "off";
 		};
 
 		user1 {
 			 label = "omap3:green:user1";
-			 gpios = <&twl_gpio 19 1>; /* LEDB */
+			 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
 			 default-state = "off";
 		};
 
 		user2 {
 			 label = "omap3:red:user1";
-			 gpios = <&gpio1 16 1>;
+			 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 			 default-state = "off";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 5df894f..c7eebbf 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -20,7 +20,7 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "overo:red:gpio21";
-			gpios = <&gpio1 21 0>;
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a0a7b44..fac923b 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 171a185..f5bec4d 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -20,13 +20,13 @@
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "pandaboard::status1";
-			gpios = <&gpio1 7 0>;
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		mmc {
 			label = "pandaboard::status2";
-			gpios = <&gpio1 8 0>;
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 	};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index fc7c7f4..7a26194 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -41,42 +41,42 @@
 		compatible = "gpio-leds";
 		debug0 {
 			label = "omap4:green:debug0";
-			gpios = <&gpio2 29 0>; /* 61 */
+			gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
 		};
 
 		debug1 {
 			label = "omap4:green:debug1";
-			gpios = <&gpio1 30 0>; /* 30 */
+			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
 		};
 
 		debug2 {
 			label = "omap4:green:debug2";
-			gpios = <&gpio1 7 0>; /* 7 */
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
 		};
 
 		debug3 {
 			label = "omap4:green:debug3";
-			gpios = <&gpio1 8 0>; /* 8 */
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
 		};
 
 		debug4 {
 			label = "omap4:green:debug4";
-			gpios = <&gpio2 18 0>; /* 50 */
+			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
 		};
 
 		user1 {
 			label = "omap4:blue:user";
-			gpios = <&gpio6 9 0>; /* 169 */
+			gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
 		};
 
 		user2 {
 			label = "omap4:red:user";
-			gpios = <&gpio6 10 0>; /* 170 */
+			gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
 		};
 
 		user3 {
 			label = "omap4:green:user";
-			gpios = <&gpio5 11 0>; /* 139 */
+			gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 7fe2c18..4160d7d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 4337afe..f4f86d6 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -7,6 +7,8 @@
  * Based on "omap4.dtsi"
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:32:54 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:32:54 +0200
Subject: [PATCH v4 0/5] ARM: dts: OMAP2+: Use preprocessor for device trees
Message-ID: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

Following a similar proposal by Stephen Warren for tegra [1], this series
makes use of the C preprocessor when compiling OMAP DT files, and
accomplishes some improvements to improve overall readability.

Patch 1 is a preparation for the rest of the series.
Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
it to simplify pinctrl DT.

As for previous versions, the .dtb files were diff-tested before and after
applying the series to guarantee identity for all targets.

The same series for AM3XXX will follow shortly.

Best regards,

Florian

>From v3:
- Rebased on Benoit's for_3.11/dts branch

>From v2: 
- Address Tony's comments (standardize comments, remove OMAP_ prefix)

>From v1: 
- Remove duplicated fix
- Remove OMAP_GPIO macro
- Add pinctrl constants

Florian Vaussard (5):
  ARM: dts: OMAP2+: Use #include for all device trees
  ARM: dts: OMAP2+: Use existing constants for GPIOs
  ARM: dts: OMAP4/5: Use existing constants for IRQs
  ARM: dts: OMAP2+: Header file for pinctrl constants
  ARM: dts: OMAP2+: Use pinctrl constants

 arch/arm/boot/dts/omap2.dtsi              |    5 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    8 +-
 arch/arm/boot/dts/omap3-beagle.dts        |   34 ++++----
 arch/arm/boot/dts/omap3-devkit8000.dts    |   10 +-
 arch/arm/boot/dts/omap3-evm.dts           |    6 +-
 arch/arm/boot/dts/omap3-igep.dtsi         |   38 ++++----
 arch/arm/boot/dts/omap3-igep0020.dts      |   10 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |   10 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 +-
 arch/arm/boot/dts/omap3-tobi.dts          |    4 +-
 arch/arm/boot/dts/omap3.dtsi              |    5 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 +-
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |   10 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   70 ++++++++--------
 arch/arm/boot/dts/omap4-panda-es.dts      |   10 +-
 arch/arm/boot/dts/omap4-panda.dts         |    4 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |  126 ++++++++++++++--------------
 arch/arm/boot/dts/omap4-var-som.dts       |    8 +-
 arch/arm/boot/dts/omap4.dtsi              |  118 ++++++++++++++-------------
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    6 +-
 arch/arm/boot/dts/omap5-evm.dts           |   92 ++++++++++----------
 arch/arm/boot/dts/omap5.dtsi              |  128 +++++++++++++++--------------
 include/dt-bindings/pinctrl/omap.h        |   50 +++++++++++
 30 files changed, 422 insertions(+), 358 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/omap.h

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:32:55 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:32:55 +0200
Subject: [PATCH v4 1/5] ARM: dts: OMAP2+: Use #include for all device trees
In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370003579-30219-2-git-send-email-florian.vaussard@epfl.ch>

Replace /include/ by #include for OMAP2+ DT, in order to use the
C pre-processor, making use of #define features possible.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Reviewed-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/omap2.dtsi              |    2 +-
 arch/arm/boot/dts/omap2420-h4.dts         |    2 +-
 arch/arm/boot/dts/omap2420.dtsi           |    2 +-
 arch/arm/boot/dts/omap2430.dtsi           |    2 +-
 arch/arm/boot/dts/omap3-beagle-xm.dts     |    4 ++--
 arch/arm/boot/dts/omap3-beagle.dts        |    4 ++--
 arch/arm/boot/dts/omap3-devkit8000.dts    |    4 ++--
 arch/arm/boot/dts/omap3-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap3-igep.dtsi         |    4 ++--
 arch/arm/boot/dts/omap3-igep0020.dts      |    2 +-
 arch/arm/boot/dts/omap3-igep0030.dts      |    2 +-
 arch/arm/boot/dts/omap3-overo.dtsi        |    4 ++--
 arch/arm/boot/dts/omap3-tobi.dts          |    2 +-
 arch/arm/boot/dts/omap3.dtsi              |    2 +-
 arch/arm/boot/dts/omap3430-sdp.dts        |    4 ++--
 arch/arm/boot/dts/omap34xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap36xx.dtsi           |    2 +-
 arch/arm/boot/dts/omap4-panda-a4.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda-common.dtsi |    4 ++--
 arch/arm/boot/dts/omap4-panda-es.dts      |    4 ++--
 arch/arm/boot/dts/omap4-panda.dts         |    4 ++--
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    2 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +++---
 arch/arm/boot/dts/omap4-var-som.dts       |    4 ++--
 arch/arm/boot/dts/omap4.dtsi              |    2 +-
 arch/arm/boot/dts/omap443x.dtsi           |    2 +-
 arch/arm/boot/dts/omap4460.dtsi           |    2 +-
 arch/arm/boot/dts/omap5-evm.dts           |    4 ++--
 arch/arm/boot/dts/omap5.dtsi              |    2 +-
 29 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..e6e4587 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee..224c08f 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 
 / {
 	model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285..c8f9c55 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc44..c535a5a 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
 	compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..e0ce823 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard xM";
@@ -75,7 +75,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..fcac96a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 BeagleBoard";
@@ -107,7 +107,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc..8d0f5e4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
 	model = "TimLL OMAP3 Devkit8000";
 	compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -80,7 +80,7 @@
 	status = "disabled";
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c20..d75759b 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -44,7 +44,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index d5cd504..d1d2ba7 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	memory {
@@ -86,7 +86,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 0ba4313..c50ce59 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEPv2";
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index f65bc3a..5061a27 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
 	model = "IGEP COM Module";
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50..e112a42 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	pwmleds {
@@ -49,7 +49,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 /* i2c2 pins are used for gpio */
 &i2c2 {
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12d..5df894f 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 
 / {
 	model = "TI OMAP3 Gumstix Overo on Tobi";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99ba6e1..a0a7b44 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap3430", "ti,omap3";
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43..2a725a0 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI OMAP3430 SDP";
@@ -28,7 +28,7 @@
 	};
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
 
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae..5355d61 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc..f8b3765 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0..f18fb5c 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index eeb734e..171a185 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 PandaBoard";
@@ -184,7 +184,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c6f012e 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f..6189a8b 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ff..4f26355 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 98505a2..fc7c7f4 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 SDP board";
@@ -336,7 +336,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103..6593607 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 
 / {
 	model = "Variscite OMAP4 SOM";
@@ -39,7 +39,7 @@
 	};
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
 	clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 006563e..7fe2c18 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -6,7 +6,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39a..a81f8df 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..41762c2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
 	cpus {
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 982acd1..f5f55d1 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
+#include "omap5.dtsi"
+#include "samsung_k3pe0e000b.dtsi"
 
 / {
 	model = "TI OMAP5 EVM board";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 888d114..4337afe 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -7,7 +7,7 @@
  * Based on "omap4.dtsi"
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	#address-cells = <1>;
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:32:59 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:32:59 +0200
Subject: [PATCH v4 5/5] ARM: dts: OMAP2+: Use pinctrl constants
In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370003579-30219-6-git-send-email-florian.vaussard@epfl.ch>

Using constants for pinctrl allows a better readability, and removes
redundancy with comments.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Reviewed-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/omap2.dtsi              |    1 +
 arch/arm/boot/dts/omap3-beagle.dts        |   24 ++++----
 arch/arm/boot/dts/omap3-igep.dtsi         |   34 +++++-----
 arch/arm/boot/dts/omap3.dtsi              |    1 +
 arch/arm/boot/dts/omap4-panda-a4.dts      |    6 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi |   54 ++++++++--------
 arch/arm/boot/dts/omap4-panda-es.dts      |    6 +-
 arch/arm/boot/dts/omap4-sdp-es23plus.dts  |    6 +-
 arch/arm/boot/dts/omap4-sdp.dts           |   98 ++++++++++++++--------------
 arch/arm/boot/dts/omap4.dtsi              |    1 +
 arch/arm/boot/dts/omap5-evm.dts           |   88 +++++++++++++-------------
 arch/arm/boot/dts/omap5.dtsi              |    1 +
 12 files changed, 162 insertions(+), 158 deletions(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index f39b237..b3cc896 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 434288f..6d47c4b 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -81,18 +81,18 @@
 
 	hsusbb2_pins: pinmux_hsusbb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
-			0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
-			0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
-			0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
-			0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
-			0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
-			0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
-			0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
-			0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
-			0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
-			0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
-			0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
+			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
+			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
+			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
+			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
+			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
+			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
+			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
+			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
+			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
+			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
+			0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index d1d2ba7..5224c29 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -29,43 +29,43 @@
 &omap3_pmx_core {
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			0x152 0x100	/* uart1_rx.uart1_rx INPUT | MODE0 */
-			0x14c 0		/* uart1_tx.uart1_tx OUTPUT | MODE0 */
+			0x152 (PIN_INPUT | MUX_MODE0)		/* uart1_rx.uart1_rx */
+			0x14c (PIN_OUTPUT |MUX_MODE0)		/* uart1_tx.uart1_tx */
 		>;
 	};
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			0x14a 0x100	/* uart2_rx.uart2_rx INPUT | MODE0 */
-			0x148 0		/* uart2_tx.uart2_tx OUTPUT | MODE0 */
+			0x14a (PIN_INPUT | MUX_MODE0)		/* uart2_rx.uart2_rx */
+			0x148 (PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			0x16e 0x100	/* uart3_rx.uart3_rx INPUT | MODE0 */
-			0x170 0		/* uart3_tx.uart3_tx OUTPUT | MODE0 */
+			0x16e (PIN_INPUT | MUX_MODE0)		/* uart3_rx.uart3_rx */
+			0x170 (PIN_OUTPUT | MUX_MODE0)		/* uart3_tx.uart3_tx */
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			0x114 0x0118    /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
-			0x116 0x0118    /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
-			0x118 0x0118 	/* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
-			0x11a 0x0118	/* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
-			0x11c 0x0118	/* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
-			0x11e 0x0118	/* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
-			0x120 0x0100	/* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
-			0x122 0x0100	/* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
-			0x124 0x0100	/* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
-			0x126 0x0100	/* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
+			0x114 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			0x116 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
+			0x118 (PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat0.sdmmc1_dat0 */
+			0x11a (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
+			0x11c (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
+			0x11e (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
+			0x120 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat4.sdmmc1_dat4 */
+			0x122 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat5.sdmmc1_dat5 */
+			0x124 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat6.sdmmc1_dat6 */
+			0x126 (PIN_INPUT | MUX_MODE0)		/* sdmmc1_dat7.sdmmc1_dat7 */
 		>;
 	};
 
 	smsc911x_pins: pinmux_smsc911x_pins {
 		pinctrl-single,pins = <
-                        0x1a2 0x0104    /* mcspi1_cs2.gpio_176 INPUT | MODE4 */
+			0x1a2 (PIN_INPUT | MUX_MODE4)		/* mcspi1_cs2.gpio_176 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index fac923b..6d05ee0 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index f18fb5c..133f1b7 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -13,8 +13,8 @@
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 8d09cf5..d5d144a 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -64,7 +64,7 @@
 
 	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
 		pinctrl-single,pins = <
-			0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+			0x14 (PIN_OUTPUT | MUX_MODE2)		/* fref_clk0_out.sys_drm_msecure */
 		>;
 	};
 };
@@ -82,77 +82,77 @@
 
 	twl6030_pins: pinmux_twl6030_pins {
 		pinctrl-single,pins = <
-			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+			0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)	/* sys_nirq1.sys_nirq1 */
 		>;
 	};
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-			0x160 0x100	/* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+			0xe0 (PIN_OUTPUT | MUX_MODE3)	/* hdq_sio.gpio_127 */
+			0x160 (PIN_INPUT | MUX_MODE0)	/* sys_nirq2.sys_nirq2 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0xc6 0x108	/* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-			0xc8 0x108	/* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-			0xca 0x118	/* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-			0xcc 0x108	/* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-			0xce 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+			0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_ul_data.abe_pdm_ul_data */
+			0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_dl_data.abe_pdm_dl_data */
+			0xca (PIN_INPUT_PULLUP   | MUX_MODE0)	/* abe_pdm_frame.abe_pdm_frame */
+			0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_lb_clk.abe_pdm_lb_clk */
+			0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0xbe 0x100	/* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-			0xc0 0x108	/* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-			0xc2 0x8		/* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-			0xc4 0x100	/* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+			0xbe (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+			0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dr.abe_mcbsp1_dr */
+			0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
+			0xc4 (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
 		>;
 	};
 
 	dss_hdmi_pins: pinmux_dss_hdmi_pins {
 		pinctrl-single,pins = <
-			0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-			0x5c 0x118	/* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-			0x5e 0x118	/* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+			0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+			0x5c (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_scl.hdmi_scl */
+			0x5e (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_sda.hdmi_sda */
 		>;
 	};
 
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
-			0x22 0x3	/* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-			0x48 0x3	/* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-			0x58 0x10b	/* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+			0x22 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_a17.gpio_41 */
+			0x48 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_nbe1.gpio_60 */
+			0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* hdmi_hpd.gpio_63 */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
+			0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-			0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+			0xea (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
+			0xec (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+			0xee (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
+			0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index c6f012e..5cfdf19 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -29,8 +29,8 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index 4f26355..aad5dda 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -10,8 +10,8 @@
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-		0x5c 0x100	/* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+		0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		0x5c (PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
+		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index e9df3ea..7951b4e 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -150,7 +150,7 @@
 
 	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
 		pinctrl-single,pins = <
-			0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+			0x14 (PIN_OUTPUT | MUX_MODE2)		/* fref_clk0_out.sys_drm_msecure */
 		>;
 	};
 };
@@ -170,129 +170,129 @@
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			0xd8 0x118	/* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
-			0xda 0		/* uart2_rts.uart2_rts OUTPUT | MODE0 */
-			0xdc 0x118	/* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
-			0xde 0		/* uart2_tx.uart2_tx OUTPUT | MODE0 */
+			0xd8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_cts.uart2_cts */
+			0xda (PIN_OUTPUT | MUX_MODE0)		/* uart2_rts.uart2_rts */
+			0xdc (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_rx.uart2_rx */
+			0xde (PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			0x100 0x118	/* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
-			0x102 0		/* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
-			0x104 0x100	/* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
-			0x106 0		/* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart3_cts_rctx.uart3_cts_rctx */
+			0x102 (PIN_OUTPUT | MUX_MODE0)		/* uart3_rts_sd.uart3_rts_sd */
+			0x104 (PIN_INPUT | MUX_MODE0)		/* uart3_rx_irrx.uart3_rx_irrx */
+			0x106 (PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
 		>;
 	};
 
 	uart4_pins: pinmux_uart4_pins {
 		pinctrl-single,pins = <
-			0x11c 0x100	/* uart4_rx.uart4_rx INPUT | MODE0 */
-			0x11e 0		/* uart4_tx.uart4_tx OUTPUT | MODE0 */
+			0x11c (PIN_INPUT | MUX_MODE0)		/* uart4_rx.uart4_rx */
+			0x11e (PIN_OUTPUT | MUX_MODE0)		/* uart4_tx.uart4_tx */
 		>;
 	};
 
 	twl6030_pins: pinmux_twl6030_pins {
 		pinctrl-single,pins = <
-			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+			0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)	/* sys_nirq1.sys_nirq1 */
 		>;
 	};
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */
-			0x160 0x100	/* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+			0xe0 (PIN_OUTPUT | MUX_MODE3)		/* hdq_sio.gpio_127 */
+			0x160 (PIN_INPUT | MUX_MODE0)		/* sys_nirq2.sys_nirq2 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0xc6 0x108	/* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-			0xc8 0x108	/* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-			0xca 0x118	/* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-			0xcc 0x108	/* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-			0xce 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+			0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_ul_data.abe_pdm_ul_data */
+			0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_dl_data.abe_pdm_dl_data */
+			0xca (PIN_INPUT_PULLUP | MUX_MODE0)	/* abe_pdm_frame.abe_pdm_frame */
+			0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_pdm_lb_clk.abe_pdm_lb_clk */
+			0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
 		>;
 	};
 
 	dmic_pins: pinmux_dmic_pins {
 		pinctrl-single,pins = <
-			0xd0 0		/* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
-			0xd2 0x100	/* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
-			0xd4 0x100	/* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
-			0xd6 0x100	/* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* abe_dmic_clk1.abe_dmic_clk1 */
+			0xd2 (PIN_INPUT | MUX_MODE0)		/* abe_dmic_din1.abe_dmic_din1 */
+			0xd4 (PIN_INPUT | MUX_MODE0)		/* abe_dmic_din2.abe_dmic_din2 */
+			0xd6 (PIN_INPUT | MUX_MODE0)		/* abe_dmic_din3.abe_dmic_din3 */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0xbe 0x100	/* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-			0xc0 0x108	/* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-			0xc2 0x8	/* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-			0xc4 0x100	/* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+			0xbe (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+			0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dr.abe_mcbsp1_dr */
+			0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
+			0xc4 (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
 		>;
 	};
 
 	mcbsp2_pins: pinmux_mcbsp2_pins {
 		pinctrl-single,pins = <
-			0xb6 0x100	/* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
-			0xb8 0x108	/* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
-			0xba 0x8	/* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-			0xbc 0x100	/* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+			0xb6 (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+			0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp2_dr.abe_mcbsp2_dr */
+			0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp2_dx.abe_mcbsp2_dx */
+			0xbc (PIN_INPUT | MUX_MODE0)		/* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
 		>;
 	};
 
 	mcspi1_pins: pinmux_mcspi1_pins {
 		pinctrl-single,pins = <
-			0xf2 0x100	/*  mcspi1_clk.mcspi1_clk INPUT | MODE0 */
-			0xf4 0x100	/*  mcspi1_somi.mcspi1_somi INPUT | MODE0 */
-			0xf6 0x100	/*  mcspi1_simo.mcspi1_simo INPUT | MODE0 */
-			0xf8 0x100	/*  mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/
+			0xf2 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_clk.mcspi1_clk */
+			0xf4 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_somi.mcspi1_somi */
+			0xf6 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_simo.mcspi1_simo */
+			0xf8 (PIN_INPUT | MUX_MODE0)		/*  mcspi1_cs0.mcspi1_cs0 */
 		>;
 	};
 
 	dss_hdmi_pins: pinmux_dss_hdmi_pins {
 		pinctrl-single,pins = <
-			0x5a 0x118	/* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-			0x5c 0x118	/* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-			0x5e 0x118	/* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+			0x5a (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+			0x5c (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_scl.hdmi_scl */
+			0x5e (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_sda.hdmi_sda */
 		>;
 	};
 
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
-			0x22 0x3	/* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-			0x48 0x3	/* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-			0x58 0x10b	/* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+			0x22 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_a17.gpio_41 */
+			0x48 (PIN_OUTPUT | MUX_MODE3)		/* gpmc_nbe1.gpio_60 */
+			0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* hdmi_hpd.gpio_63 */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-			0xe4 0x118       /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+			0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
+			0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-			0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+			0xea (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
+			0xec (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-			0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+			0xee (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
+			0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 6137aff..463b97d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index f5f55d1..22e9ee8 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -40,106 +40,106 @@
 
 	twl6040_pins: pinmux_twl6040_pins {
 		pinctrl-single,pins = <
-			0x18a 0x6	/* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
+			0x18a (PIN_OUTPUT | MUX_MODE6)	/* perslimbus2_clock.gpio5_145 */
 		>;
 	};
 
 	mcpdm_pins: pinmux_mcpdm_pins {
 		pinctrl-single,pins = <
-			0x142 0x108	/* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
-			0x15c 0x108	/* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
-			0x15e 0x108	/* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
-			0x160 0x118	/* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
-			0x162 0x108	/* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
+			0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
+			0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_ul_data.abemcpdm_ul_data */
+			0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_dl_data.abemcpdm_dl_data */
+			0x160 (PIN_INPUT_PULLUP | MUX_MODE0)	/* abemcpdm_frame.abemcpdm_frame */
+			0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_lb_clk.abemcpdm_lb_clk */
 		>;
 	};
 
 	dmic_pins: pinmux_dmic_pins {
 		pinctrl-single,pins = <
-			0x144 0x100	/* abedmic_din1.abedmic_din1 INPUT | MODE0 */
-			0x146 0x100	/* abedmic_din2.abedmic_din2 INPUT | MODE0 */
-			0x148 0x100	/* abedmic_din3.abedmic_din3 INPUT | MODE0 */
-			0x14a 0		/* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
+			0x144 (PIN_INPUT | MUX_MODE0)		/* abedmic_din1.abedmic_din1 */
+			0x146 (PIN_INPUT | MUX_MODE0)		/* abedmic_din2.abedmic_din2 */
+			0x148 (PIN_INPUT | MUX_MODE0)		/* abedmic_din3.abedmic_din3 */
+			0x14a (PIN_OUTPUT | MUX_MODE0)		/* abedmic_clk1.abedmic_clk1 */
 		>;
 	};
 
 	mcbsp1_pins: pinmux_mcbsp1_pins {
 		pinctrl-single,pins = <
-			0x14c 0x101	/* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
-			0x14e 0x9	/* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
-			0x150 0x101	/* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
-			0x152 0x109	/* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
+			0x14c (PIN_INPUT | MUX_MODE1)		/* abedmic_clk2.abemcbsp1_fsx */
+			0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* abedmic_clk3.abemcbsp1_dx */
+			0x150 (PIN_INPUT | MUX_MODE1)		/* abeslimbus1_clock.abemcbsp1_clkx */
+			0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* abeslimbus1_data.abemcbsp1_dr */
 		>;
 	};
 
 	mcbsp2_pins: pinmux_mcbsp2_pins {
 		pinctrl-single,pins = <
-			0x154 0x108	/* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
-			0x156 0x8	/* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-			0x158 0x100	/* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
-			0x15a 0x100	/* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
+			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dr.abemcbsp2_dr */
+			0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dx.abemcbsp2_dx */
+			0x158 (PIN_INPUT | MUX_MODE0)		/* abemcbsp2_fsx.abemcbsp2_fsx */
+			0x15a (PIN_INPUT | MUX_MODE0)		/* abemcbsp2_clkx.abemcbsp2_clkx */
 		>;
 	};
 
-        i2c1_pins: pinmux_i2c1_pins {
-                pinctrl-single,pins = <
-                        0x1b2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0x1b4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
-                >;
-        };
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
+		>;
+	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			0x178 0x100        /* i2c2_scl INPUTENABLE | MODE0 */
-			0x17a 0x100        /* i2c2_sda INPUTENABLE | MODE0 */
+			0x178 (PIN_INPUT | MUX_MODE0)		/* i2c2_scl */
+			0x17a (PIN_INPUT | MUX_MODE0)		/* i2c2_sda */
 		>;
 	};
 
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
-			0x13a 0x100        /* i2c3_scl INPUTENABLE | MODE0 */
-			0x13c 0x100     /* i2c3_sda INPUTENABLE | MODE0 */
+			0x13a (PIN_INPUT | MUX_MODE0)		/* i2c3_scl */
+			0x13c (PIN_INPUT | MUX_MODE0)		/* i2c3_sda */
 		>;
 	};
 
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
-			0xb8 0x100        /* i2c4_scl INPUTENABLE | MODE0 */
-			0xba 0x100     /* i2c4_sda INPUTENABLE | MODE0 */
+			0xb8 (PIN_INPUT | MUX_MODE0)		/* i2c4_scl */
+			0xba (PIN_INPUT | MUX_MODE0)		/* i2c4_sda */
 		>;
 	};
 
 	i2c5_pins: pinmux_i2c5_pins {
 		pinctrl-single,pins = <
-			0x184 0x100        /* i2c5_scl INPUTENABLE | MODE0 */
-			0x186 0x100     /* i2c5_sda INPUTENABLE | MODE0 */
+			0x184 (PIN_INPUT | MUX_MODE0)		/* i2c5_scl */
+			0x186 (PIN_INPUT | MUX_MODE0)		/* i2c5_sda */
 		>;
 	};
 
 	mcspi2_pins: pinmux_mcspi2_pins {
 		pinctrl-single,pins = <
-			0xbc 0x100	/*  MCSPI2_CLK INPUTENABLE | MODE0 */
-			0xbe 0x100	/*  MCSPI2_SIMO INPUTENABLE | MODE0 */
-			0xc0 0x118	/*  MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
-			0xc2 0x0	/*  MCSPI2_CS MODE0*/
+			0xbc (PIN_INPUT | MUX_MODE0)		/*  mcspi2_clk */
+			0xbe (PIN_INPUT | MUX_MODE0)		/*  mcspi2_simo */
+			0xc0 (PIN_INPUT_PULLUP | MUX_MODE0)	/*  mcspi2_somi */
+			0xc2 (PIN_OUTPUT | MUX_MODE0)		/*  mcspi2_cs */
 		>;
 	};
 
 	mcspi3_pins: pinmux_mcspi3_pins {
 		pinctrl-single,pins = <
-			0x78 0x101	/*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-			0x7a 0x101	/*  MCSPI2_CS INPUTENABLE | MODE1 */
-			0x7c 0x101	/*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-			0x7e 0x101	/*  MCSPI2_CLK INPUTENABLE | MODE1 */
+			0x78 (PIN_INPUT | MUX_MODE1)		/*  mcspi2_somi */
+			0x7a (PIN_INPUT | MUX_MODE1)		/*  mcspi2_cs */
+			0x7c (PIN_INPUT | MUX_MODE1)		/*  mcspi2_simo */
+			0x7e (PIN_INPUT | MUX_MODE1)		/*  mcspi2_clk */
 		>;
 	};
 
 	mcspi4_pins: pinmux_mcspi4_pins {
 		pinctrl-single,pins = <
-			0x164 0x101	/*  MCSPI2_CLK INPUTENABLE | MODE1 */
-			0x168 0x101	/*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-			0x16a 0x101	/*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-			0x16c 0x101	/*  MCSPI2_CS INPUTENABLE | MODE1 */
+			0x164 (PIN_INPUT | MUX_MODE1)		/*  mcspi2_clk */
+			0x168 (PIN_INPUT | MUX_MODE1)		/*  mcspi2_simo */
+			0x16a (PIN_INPUT | MUX_MODE1)		/*  mcspi2_somi */
+			0x16c (PIN_INPUT | MUX_MODE1)		/*  mcspi2_cs */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 2b80653..08558c9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
 #include "skeleton.dtsi"
 
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:32:57 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:32:57 +0200
Subject: [PATCH v4 3/5] ARM: dts: OMAP4/5: Use existing constants for IRQs
In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370003579-30219-4-git-send-email-florian.vaussard@epfl.ch>

Use the constants defined in include/dt-bindings/interrupt-controller/
to enhance readability.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Reviewed-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |    8 +-
 arch/arm/boot/dts/omap4-sdp.dts           |    6 +-
 arch/arm/boot/dts/omap4-var-som.dts       |    4 +-
 arch/arm/boot/dts/omap4.dtsi              |  113 +++++++++++++-------------
 arch/arm/boot/dts/omap4460.dtsi           |    4 +-
 arch/arm/boot/dts/omap5.dtsi              |  123 +++++++++++++++--------------
 6 files changed, 130 insertions(+), 128 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index f5bec4d..8d09cf5 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -165,16 +165,16 @@
 
 	twl: twl at 48 {
 		reg = <0x48>;
-		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		/* IRQ# = 7 */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
 	twl6040: twl at 4b {
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
-		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		/* IRQ# = 119 */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 7a26194..e9df3ea 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -306,7 +306,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 
@@ -314,7 +314,7 @@
 		compatible = "ti,twl6040";
 		reg = <0x4b>;
 		/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-		interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
 		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
@@ -395,7 +395,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <2 8>; /* gpio line 34, low triggered */
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6593607..b41269e 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -34,7 +34,7 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-		interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
 		interrupt-parent = <&gic>;
 	};
 };
@@ -68,7 +68,7 @@
 		spi-max-frequency = <24000000>;
 		reg = <0>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <11 8>; /* gpio line 171, low triggered */
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */
 		vdd-supply = <&vdd_eth>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4160d7d..6137aff 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -50,7 +51,7 @@
 	local-timer at 0x48240600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x48240600 0x20>;
-		interrupts = <1 13 0x304>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	/*
@@ -91,8 +92,8 @@
 		reg = <0x44000000 0x1000>,
 		      <0x44800000 0x2000>,
 		      <0x45000000 0x1000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4a304000 {
 			compatible = "ti,omap-counter32k";
@@ -120,10 +121,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -132,7 +133,7 @@
 		gpio1: gpio at 4a310000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4a310000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -144,7 +145,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -155,7 +156,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -166,7 +167,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -177,7 +178,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -188,7 +189,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -201,7 +202,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -210,7 +211,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -218,7 +219,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -226,7 +227,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -234,7 +235,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -242,7 +243,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -251,7 +252,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -260,7 +261,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -269,7 +270,7 @@
 		i2c4: i2c at 48350000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48350000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -278,7 +279,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -298,7 +299,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -313,7 +314,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -325,7 +326,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -337,7 +338,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -348,7 +349,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -358,7 +359,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -368,7 +369,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -378,7 +379,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -388,7 +389,7 @@
 		wdt2: wdt at 4a314000 {
 			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 			reg = <0x4a314000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -397,7 +398,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -409,7 +410,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -420,7 +421,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -434,7 +435,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -448,7 +449,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -461,7 +462,7 @@
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */
 			reg-names = "mpu";
-			interrupts = <0 16 0x4>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp4";
@@ -473,7 +474,7 @@
 		keypad: keypad at 4a31c000 {
 			compatible = "ti,omap4-keypad";
 			reg = <0x4a31c000 0x80>;
-			interrupts = <0 120 0x4>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
 		};
@@ -481,7 +482,7 @@
 		emif1: emif at 4c000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4c000000 0x100>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif1";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -492,7 +493,7 @@
 		emif2: emif at 4d000000 {
 			compatible = "ti,emif-4d";
 			reg = <0x4d000000 0x100>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "emif2";
 			phy-type = <1>;
 			hw-caps-read-idle-ctrl;
@@ -517,7 +518,7 @@
 		timer1: timer at 4a318000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x4a318000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -525,21 +526,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -547,7 +548,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -556,7 +557,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 		};
@@ -565,7 +566,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -574,7 +575,7 @@
 			compatible = "ti,omap4430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
@@ -583,7 +584,7 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
 		};
@@ -591,7 +592,7 @@
 		timer10: timer at 48086000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
 		};
@@ -599,7 +600,7 @@
 		timer11: timer at 48088000 {
 			compatible = "ti,omap4430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -607,7 +608,7 @@
 		usbhstll: usbhstll at 4a062000 {
 			compatible = "ti,usbhs-tll";
 			reg = <0x4a062000 0x1000>;
-			interrupts = <0 78 0x4>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
 		};
 
@@ -623,14 +624,14 @@
 				compatible = "ti,ohci-omap3", "usb-ohci";
 				reg = <0x4a064800 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 76 0x4>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			usbhsehci: ehci at 4a064c00 {
 				compatible = "ti,ehci-omap", "usb-ehci";
 				reg = <0x4a064c00 0x400>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 77 0x4>;
+				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
 
@@ -645,7 +646,7 @@
 		usb_otg_hs: usb_otg_hs at 4a0ab000 {
 			compatible = "ti,omap4-musb";
 			reg = <0x4a0ab000 0x7ff>;
-			interrupts = <0 92 0x4>, <0 93 0x4>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc", "dma";
 			ti,hwmods = "usb_otg_hs";
 			usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 41762c2..19628b1 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -25,8 +25,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 54 0x4>,
-			     <0 55 0x4>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		ti,hwmods = "debugss";
 	};
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index f4f86d6..2b80653 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -8,6 +8,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
@@ -38,11 +39,11 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		/* PPI secure/nonsecure IRQ, active low level-sensitive */
-		interrupts = <1 13 0x308>,
-			     <1 14 0x308>,
-			     <1 11 0x308>,
-			     <1 10 0x308>;
+		/* PPI secure/nonsecure IRQ */
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <6144000>;
 	};
 
@@ -84,8 +85,8 @@
 		reg = <0x44000000 0x2000>,
 		      <0x44800000 0x3000>,
 		      <0x45000000 0x4000>;
-		interrupts = <0 9 0x4>,
-			     <0 10 0x4>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
@@ -113,10 +114,10 @@
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <0 12 0x4>,
-				     <0 13 0x4>,
-				     <0 14 0x4>,
-				     <0 15 0x4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -125,7 +126,7 @@
 		gpio1: gpio at 4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-			interrupts = <0 29 0x4>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			ti,gpio-always-on;
 			gpio-controller;
@@ -137,7 +138,7 @@
 		gpio2: gpio at 48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <0 30 0x4>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -148,7 +149,7 @@
 		gpio3: gpio at 48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <0 31 0x4>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -159,7 +160,7 @@
 		gpio4: gpio at 48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <0 32 0x4>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -170,7 +171,7 @@
 		gpio5: gpio at 4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <0 33 0x4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -181,7 +182,7 @@
 		gpio6: gpio at 4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <0 34 0x4>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -192,7 +193,7 @@
 		gpio7: gpio at 48051000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48051000 0x200>;
-			interrupts = <0 35 0x4>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio7";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -203,7 +204,7 @@
 		gpio8: gpio at 48053000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48053000 0x200>;
-			interrupts = <0 121 0x4>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio8";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -216,7 +217,7 @@
 			reg = <0x50000000 0x1000>;
 			#address-cells = <2>;
 			#size-cells = <1>;
-			interrupts = <0 20 0x4>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
@@ -225,7 +226,7 @@
 		i2c1: i2c at 48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <0 56 0x4>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -234,7 +235,7 @@
 		i2c2: i2c at 48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <0 57 0x4>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -243,7 +244,7 @@
 		i2c3: i2c at 48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <0 61 0x4>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -252,7 +253,7 @@
 		i2c4: i2c at 4807a000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807a000 0x100>;
-			interrupts = <0 62 0x4>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -261,7 +262,7 @@
 		i2c5: i2c at 4807c000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807c000 0x100>;
-			interrupts = <0 60 0x4>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c5";
@@ -270,7 +271,7 @@
 		mcspi1: spi at 48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <0 65 0x4>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -290,7 +291,7 @@
 		mcspi2: spi at 4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <0 66 0x4>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -305,7 +306,7 @@
 		mcspi3: spi at 480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <0 91 0x4>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -317,7 +318,7 @@
 		mcspi4: spi at 480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <0 48 0x4>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
@@ -329,7 +330,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <0 72 0x4>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 		};
@@ -337,7 +338,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <0 73 0x4>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 		};
@@ -345,7 +346,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <0 74 0x4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
@@ -353,7 +354,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <0 70 0x4>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
@@ -361,7 +362,7 @@
 		uart5: serial at 48066000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48066000 0x100>;
-			interrupts = <0 105 0x4>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 		};
@@ -369,7 +370,7 @@
 		uart6: serial at 48068000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48068000 0x100>;
-			interrupts = <0 106 0x4>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 		};
@@ -377,7 +378,7 @@
 		mmc1: mmc at 4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <0 83 0x4>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -388,7 +389,7 @@
 		mmc2: mmc at 480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <0 86 0x4>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -398,7 +399,7 @@
 		mmc3: mmc at 480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <0 94 0x4>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -408,7 +409,7 @@
 		mmc4: mmc at 480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <0 96 0x4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -418,7 +419,7 @@
 		mmc5: mmc at 480d5000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d5000 0x400>;
-			interrupts = <0 59 0x4>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
@@ -436,7 +437,7 @@
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 112 0x4>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mcpdm";
 			dmas = <&sdma 65>,
 			       <&sdma 66>;
@@ -448,7 +449,7 @@
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 114 0x4>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmic";
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
@@ -459,7 +460,7 @@
 			reg = <0x40122000 0xff>, /* MPU private access */
 			      <0x49022000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 17 0x4>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp1";
@@ -473,7 +474,7 @@
 			reg = <0x40124000 0xff>, /* MPU private access */
 			      <0x49024000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 22 0x4>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp2";
@@ -487,7 +488,7 @@
 			reg = <0x40126000 0xff>, /* MPU private access */
 			      <0x49026000 0xff>; /* L3 Interconnect */
 			reg-names = "mpu", "dma";
-			interrupts = <0 23 0x4>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "common";
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp3";
@@ -499,7 +500,7 @@
 		timer1: timer at 4ae18000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4ae18000 0x80>;
-			interrupts = <0 37 0x4>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -507,21 +508,21 @@
 		timer2: timer at 48032000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <0 38 0x4>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer at 48034000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <0 39 0x4>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer at 48036000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <0 40 0x4>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
@@ -529,7 +530,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x40138000 0x80>,
 			      <0x49038000 0x80>;
-			interrupts = <0 41 0x4>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -538,7 +539,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013a000 0x80>,
 			      <0x4903a000 0x80>;
-			interrupts = <0 42 0x4>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -548,7 +549,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013c000 0x80>,
 			      <0x4903c000 0x80>;
-			interrupts = <0 43 0x4>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -557,7 +558,7 @@
 			compatible = "ti,omap5430-timer";
 			reg = <0x4013e000 0x80>,
 			      <0x4903e000 0x80>;
-			interrupts = <0 44 0x4>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -566,21 +567,21 @@
 		timer9: timer at 4803e000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <0 45 0x4>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 		};
 
 		timer10: timer at 48086000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <0 46 0x4>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 		};
 
 		timer11: timer at 48088000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <0 47 0x4>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -588,7 +589,7 @@
 		wdt2: wdt at 4ae14000 {
 			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 			reg = <0x4ae14000 0x80>;
-			interrupts = <0 80 0x4>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -597,7 +598,7 @@
 			ti,hwmods	= "emif1";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4c000000 0x400>;
-			interrupts = <0 110 0x4>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -608,7 +609,7 @@
 			ti,hwmods	= "emif2";
 			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
 			reg = <0x4d000000 0x400>;
-			interrupts = <0 111 0x4>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
@@ -626,7 +627,7 @@
 			compatible = "ti,dwc3";
 			ti,hwmods = "usb_otg_ss";
 			reg = <0x4a020000 0x1000>;
-			interrupts = <0 93 4>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			utmi-mode = <2>;
@@ -634,7 +635,7 @@
 			dwc3 at 4a030000 {
 				compatible = "synopsys,dwc3";
 				reg = <0x4a030000 0x1000>;
-				interrupts = <0 92 4>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 				usb-phy = <&usb2_phy>, <&usb3_phy>;
 				tx-fifo-resize;
 			};
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:42:21 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:42:21 +0200
Subject: [PATCH 3/4] ARM: dts: AM33XX: Specific pinctrl header
In-Reply-To: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370004142-30506-4-git-send-email-florian.vaussard@epfl.ch>

The pinctrl IP inside the AM33XX family differs slightly from
what is found on OMAP2+. Define a specific header to take account
of the differences.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 include/dt-bindings/pinctrl/am33xx.h |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/am33xx.h

diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
new file mode 100644
index 0000000..9ffb6c2
--- /dev/null
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#include <include/dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef  INPUT_EN
+#define INPUT_EN		(1 << 5)
+#define SLEWCTRL_FAST		(1 << 6)
+
+/* update macro depending on INPUT_EN */
+#undef  PIN_INPUT
+#undef  PIN_INPUT_PULLUP
+#undef  PIN_INPUT_PULLDOWN
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:42:20 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:42:20 +0200
Subject: [PATCH 2/4] ARM: dts: AM33XX: Use existing constants for GPIOs
In-Reply-To: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370004142-30506-3-git-send-email-florian.vaussard@epfl.ch>

Use standard GPIO constants to enhance the readability of DT GPIOs.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/am335x-bone.dts  |    8 ++++----
 arch/arm/boot/dts/am335x-evm.dts   |   14 +++++++-------
 arch/arm/boot/dts/am335x-evmsk.dts |   16 ++++++++--------
 arch/arm/boot/dts/am33xx.dtsi      |    2 ++
 4 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 0365e56..5bfb7dd 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -88,27 +88,27 @@
 
 		led at 2 {
 			label = "beaglebone:green:heartbeat";
-			gpios = <&gpio1 21 0>;
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 			default-state = "off";
 		};
 
 		led at 3 {
 			label = "beaglebone:green:mmc0";
-			gpios = <&gpio1 22 0>;
+			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 			default-state = "off";
 		};
 
 		led at 4 {
 			label = "beaglebone:green:usr2";
-			gpios = <&gpio1 23 0>;
+			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
 		led at 5 {
 			label = "beaglebone:green:usr3";
-			gpios = <&gpio1 24 0>;
+			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 	};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 629476e..0fbecfd 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -159,12 +159,12 @@
 		debounce-delay-ms = <5>;
 		col-scan-delay-us = <2>;
 
-		row-gpios = <&gpio1 25 0	/* Bank1, pin25 */
-			     &gpio1 26 0	/* Bank1, pin26 */
-			     &gpio1 27 0>;	/* Bank1, pin27 */
+		row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH		/* Bank1, pin25 */
+			     &gpio1 26 GPIO_ACTIVE_HIGH		/* Bank1, pin26 */
+			     &gpio1 27 GPIO_ACTIVE_HIGH>;	/* Bank1, pin27 */
 
-		col-gpios = <&gpio1 21 0	/* Bank1, pin21 */
-			     &gpio1 22 0>;	/* Bank1, pin22 */
+		col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH		/* Bank1, pin21 */
+			     &gpio1 22 GPIO_ACTIVE_HIGH>;	/* Bank1, pin22 */
 
 		linux,keymap = <0x0000008b	/* MENU */
 				0x0100009e	/* BACK */
@@ -183,14 +183,14 @@
 		switch at 9 {
 			label = "volume-up";
 			linux,code = <115>;
-			gpios = <&gpio0 2 1>;
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
 			gpio-key,wakeup;
 		};
 
 		switch at 10 {
 			label = "volume-down";
 			linux,code = <114>;
-			gpios = <&gpio0 3 1>;
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
 			gpio-key,wakeup;
 		};
 	};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index a339a76..289ba2c 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -144,26 +144,26 @@
 
 		led at 1 {
 			label = "evmsk:green:usr0";
-			gpios = <&gpio1 4 0>;
+			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
 		led at 2 {
 			label = "evmsk:green:usr1";
-			gpios = <&gpio1 5 0>;
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
 		led at 3 {
 			label = "evmsk:green:mmc0";
-			gpios = <&gpio1 6 0>;
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 			default-state = "off";
 		};
 
 		led at 4 {
 			label = "evmsk:green:heartbeat";
-			gpios = <&gpio1 7 0>;
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 			default-state = "off";
 		};
@@ -177,26 +177,26 @@
 		switch at 1 {
 			label = "button0";
 			linux,code = <0x100>;
-			gpios = <&gpio2 3 0>;
+			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		switch at 2 {
 			label = "button1";
 			linux,code = <0x101>;
-			gpios = <&gpio2 2 0>;
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		switch at 3 {
 			label = "button2";
 			linux,code = <0x102>;
-			gpios = <&gpio0 30 0>;
+			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
 			gpio-key,wakeup;
 		};
 
 		switch at 4 {
 			label = "button3";
 			linux,code = <0x103>;
-			gpios = <&gpio2 5 0>;
+			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 016c460..f116c79 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "skeleton.dtsi"
 
 / {
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:42:18 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:42:18 +0200
Subject: [PATCH 0/4] ARM: dts: AM3XXX: Use preprocessor for device trees
Message-ID: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

Following my series for OMAP2+, this series makes use of the C preprocessor
when compiling AM3XXX DT files, and accomplishes some improvements to improve
overall readability.

The .dtb files were diff-tested before and after applying the series to
guarantee identity for all targets.

For the am335x boards, I spotted a few output pins with pullup selected, but
not enabled. Although it seems a bit strange to me, I left the state
untouched. Has someone a rational for this? Is the pullup later activated?
Or is it unintentional?

This series depends on my previous series "ARM: dts: OMAP2+: Use preprocessor
for device trees", itself based on Benoit's for_3.11/dts branch.

Regards,

Florian

Florian Vaussard (4):
  ARM: dts: AM3XXX: Use #include for all device trees
  ARM: dts: AM33XX: Use existing constants for GPIOs
  ARM: dts: AM33XX: Specific pinctrl header
  ARM: dts: AM33XX: Use pinctrl constants

 arch/arm/boot/dts/am335x-bone.dts       |   28 ++++++++++----------
 arch/arm/boot/dts/am335x-evm.dts        |   44 +++++++++++++++---------------
 arch/arm/boot/dts/am335x-evmsk.dts      |   44 +++++++++++++++---------------
 arch/arm/boot/dts/am33xx.dtsi           |    5 +++-
 arch/arm/boot/dts/am3517-evm.dts        |    2 +-
 arch/arm/boot/dts/am3517_mt_ventoux.dts |    2 +-
 include/dt-bindings/pinctrl/am33xx.h    |   19 +++++++++++++
 7 files changed, 83 insertions(+), 61 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/am33xx.h

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:42:19 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:42:19 +0200
Subject: [PATCH 1/4] ARM: dts: AM3XXX: Use #include for all device trees
In-Reply-To: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370004142-30506-2-git-send-email-florian.vaussard@epfl.ch>

Replace /include/ by #include for AM33XX and AM35XX device tree
files, in order to use the C pre-processor, making use of #define
features possible.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/am335x-bone.dts       |    2 +-
 arch/arm/boot/dts/am335x-evm.dts        |    2 +-
 arch/arm/boot/dts/am335x-evmsk.dts      |    2 +-
 arch/arm/boot/dts/am33xx.dtsi           |    2 +-
 arch/arm/boot/dts/am3517-evm.dts        |    2 +-
 arch/arm/boot/dts/am3517_mt_ventoux.dts |    2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 74bfcc6..0365e56 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
 	model = "TI AM335x BeagleBone";
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 896d392..629476e 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
 	model = "TI AM335x EVM";
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 4d81dbc..a339a76 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
 	model = "TI AM335x EVM-SK";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index a3daebb..016c460 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "ti,am33xx";
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e9b5bda..e99dfaf 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index 5568683..fdf5ce6 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
 	model = "TeeJet Mt.Ventoux";
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri May 31 08:42:22 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 14:42:22 +0200
Subject: [PATCH 4/4] ARM: dts: AM33XX: Use pinctrl constants
In-Reply-To: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370004142-30506-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1370004142-30506-5-git-send-email-florian.vaussard@epfl.ch>

Using constants for pinctrl allows a better readability, and removes
redundancy with comments.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/am335x-bone.dts  |   18 +++++++++---------
 arch/arm/boot/dts/am335x-evm.dts   |   28 ++++++++++++++--------------
 arch/arm/boot/dts/am335x-evmsk.dts |   26 +++++++++++++-------------
 arch/arm/boot/dts/am33xx.dtsi      |    1 +
 4 files changed, 37 insertions(+), 36 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 5bfb7dd..61d0793 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -30,30 +30,30 @@
 
 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
-				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
-				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
-				0x5c 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
-				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+				0x54 (PIN_OUTPUT | MUX_MODE7)		/* gpmc_a5.gpio1_21 */
+				0x58 (PIN_OUTPUT | PULL_UP | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
+				0x5c (PIN_OUTPUT | MUX_MODE7)		/* gpmc_a7.gpio1_23 */
+				0x60 (PIN_OUTPUT | PULL_UP | MUX_MODE7)	/* gpmc_a8.gpio1_24 */
 			>;
 		};
 
 		i2c0_pins: pinmux_i2c0_pins {
 			pinctrl-single,pins = <
-				0x188 0x30	/* i2c0_sda.i2c0_sda PULLUP | INPUTENABLE | MODE0 */
-				0x18c 0x30	/* i2c0_scl.i2c0_scl PULLUP | INPUTENABLE | MODE0 */
+				0x188 (PIN_INPUT | PULL_UP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				0x18c (PIN_INPUT | PULL_UP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
 
 		uart0_pins: pinmux_uart0_pins {
 			pinctrl-single,pins = <
-				0x170 0x30	/* uart0_rxd.uart0_rxd PULLUP | INPUTENABLE | MODE0 */
-				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
+				0x170 (PIN_INPUT | PULL_UP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+				0x174 (PIN_OUTPUT | MUX_MODE0)		/* uart0_txd.uart0_txd */
 			>;
 		};
 
 		clkout2_pin: pinmux_clkout2_pin {
 			pinctrl-single,pins = <
-				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+				0x1b4 (PIN_OUTPUT | MUX_MODE3)		/* xdma_event_intr1.clkout2 */
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0fbecfd..0ee69ec 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -30,45 +30,45 @@
 
 		matrix_keypad_s0: matrix_keypad_s0 {
 			pinctrl-single,pins = <
-				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
-				0x58 0x7	/* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
-				0x64 0x27	/* gpmc_a9.gpio1_25, INPUT | MODE7 */
-				0x68 0x27	/* gpmc_a10.gpio1_26, INPUT | MODE7 */
-				0x6c 0x27	/* gpmc_a11.gpio1_27, INPUT | MODE7 */
+				0x54 (PIN_OUTPUT | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
+				0x58 (PIN_OUTPUT | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
+				0x64 (PIN_INPUT | MUX_MODE7)	/* gpmc_a9.gpio1_25 */
+				0x68 (PIN_INPUT | MUX_MODE7)	/* gpmc_a10.gpio1_26 */
+				0x6c (PIN_INPUT | MUX_MODE7)	/* gpmc_a11.gpio1_27 */
 			>;
 		};
 
 		volume_keys_s0: volume_keys_s0 {
 			pinctrl-single,pins = <
-				0x150 0x27	/* spi0_sclk.gpio0_2, INPUT | MODE7 */
-				0x154 0x27	/* spi0_d0.gpio0_3, INPUT | MODE7 */
+				0x150 (PIN_INPUT | MUX_MODE7)	/* spi0_sclk.gpio0_2 */
+				0x154 (PIN_INPUT | MUX_MODE7)	/* spi0_d0.gpio0_3 */
 			>;
 		};
 
 		i2c0_pins: pinmux_i2c0_pins {
 			pinctrl-single,pins = <
-				0x188 0x30	/* i2c0_sda.i2c0_sda PULLUP | INPUTENABLE | MODE0 */
-				0x18c 0x30	/* i2c0_scl.i2c0_scl PULLUP | INPUTENABLE | MODE0 */
+				0x188 (PIN_INPUT | PULL_UP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				0x18c (PIN_INPUT | PULL_UP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
 
 		i2c1_pins: pinmux_i2c1_pins {
 			pinctrl-single,pins = <
-				0x158 0x32	/* spi0_d1.i2c1_sda PULLUP | INPUTENABLE | MODE2 */
-				0x15c 0x32	/* spi0_cs0.i2c1_scl PULLUP | INPUTENABLE | MODE2 */
+				0x158 (PIN_INPUT | PULL_UP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
+				0x15c (PIN_INPUT | PULL_UP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
 			>;
 		};
 
 		uart0_pins: pinmux_uart0_pins {
 			pinctrl-single,pins = <
-				0x170 0x30	/* uart0_rxd.uart0_rxd PULLUP | INPUTENABLE | MODE0 */
-				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
+				0x170 (PIN_INPUT | PULL_UP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+				0x174 (PIN_OUTPUT | MUX_MODE0)		/* uart0_txd.uart0_txd */
 			>;
 		};
 
 		clkout2_pin: pinmux_clkout2_pin {
 			pinctrl-single,pins = <
-				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+				0x1b4 (PIN_OUTPUT | MUX_MODE3)		/* xdma_event_intr1.clkout2 */
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 289ba2c..5e0e709 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -36,39 +36,39 @@
 
 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
-				0x10 0x7	/* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
-				0x14 0x7	/* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
-				0x18 0x7	/* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
-				0x1c 0x7	/* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
+				0x10 (PIN_OUTPUT | MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
+				0x14 (PIN_OUTPUT | MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
+				0x18 (PIN_OUTPUT | MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
+				0x1c (PIN_OUTPUT | MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
 			>;
 		};
 
 		gpio_keys_s0: gpio_keys_s0 {
 			pinctrl-single,pins = <
-				0x94 0x27	/* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
-				0x90 0x27	/* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
-				0x70 0x27	/* gpmc_wait0.gpio0_30, INPUT | MODE7 */
-				0x9c 0x27	/* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
+				0x94 (PIN_INPUT | MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
+				0x90 (PIN_INPUT | MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
+				0x70 (PIN_INPUT | MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
+				0x9c (PIN_INPUT | MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
 			>;
 		};
 
 		i2c0_pins: pinmux_i2c0_pins {
 			pinctrl-single,pins = <
-				0x188 0x30	/* i2c0_sda.i2c0_sda PULLUP | INPUTENABLE | MODE0 */
-				0x18c 0x30	/* i2c0_scl.i2c0_scl PULLUP | INPUTENABLE | MODE0 */
+				0x188 (PIN_INPUT | PULL_UP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				0x18c (PIN_INPUT | PULL_UP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
 
 		uart0_pins: pinmux_uart0_pins {
 			pinctrl-single,pins = <
-				0x170 0x30	/* uart0_rxd.uart0_rxd PULLUP | INPUTENABLE | MODE0 */
-				0x174 0x00	/* uart0_txd.uart0_txd PULLDOWN | MODE0 */
+				0x170 (PIN_INPUT | PULL_UP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+				0x174 (PIN_OUTPUT | MUX_MODE0)		/* uart0_txd.uart0_txd */
 			>;
 		};
 
 		clkout2_pin: pinmux_clkout2_pin {
 			pinctrl-single,pins = <
-				0x1b4 0x03	/* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+				0x1b4 (PIN_OUTPUT | MUX_MODE3)		/* xdma_event_intr1.clkout2 */
 			>;
 		};
 	};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f116c79..bdcc55f 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
 
 #include "skeleton.dtsi"
 
-- 
1.7.5.4



From linus.walleij at linaro.org  Fri May 31 08:45:13 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 14:45:13 +0200
Subject: [PATCH 21/39] ARM: u300: delete all static board data
In-Reply-To: <6751591.S13Ph9lFnY@wuerfel>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <1369991954-17406-22-git-send-email-linus.walleij@stericsson.com>
 <6751591.S13Ph9lFnY@wuerfel>
Message-ID: <CACRpkdbi-xPFiy=N4=5V7cOkRPYJcoj4beTkaDLoODxxko17tw@mail.gmail.com>

On Fri, May 31, 2013 at 12:49 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> I did not see any patch removing the auxdata list in the end.
> Do you still need it after the clocks are moved over to DT
> probing?

Unfortunately yes.

I am still using the device names to resolve pin control
handles.

It's on the TODO. Once that is done this can be deleted.

Yours,
Linus Walleij


From srinivas.kandagatla at st.com  Fri May 31 08:42:54 2013
From: srinivas.kandagatla at st.com (Srinivas KANDAGATLA)
Date: Fri, 31 May 2013 13:42:54 +0100
Subject: [PATCH v1 1/2] ARM:prima2: move sirfsoc_of_rstc_init to
 .init_early
In-Reply-To: <CAGsJ_4z65+SOCQM2XKmrda+5Hu9wRuZviSvW3As1ROa0SmdXqw@mail.gmail.com>
References: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
 <1369993501-24309-1-git-send-email-srinivas.kandagatla@st.com>
 <CAGsJ_4z65+SOCQM2XKmrda+5Hu9wRuZviSvW3As1ROa0SmdXqw@mail.gmail.com>
Message-ID: <51A89ACE.8030604@st.com>

On 31/05/13 13:24, Barry Song wrote:
>> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
> hi Sriniva,
> i think my "arm: prima2: move to generic reset controller driver
> framework" fixs this too:
> http://www.spinics.net/lists/arm-kernel/msg246206.html
I did look at the patch, I think it will fix it.

But the patch is still using arch_initcall directly, which means this
call will be attempted by every SOC in multi_v7 kernel.
This call can be easily hooked into machine descriptor.
In that way only prima compatible machines will attempt to call this
function in first place.

Do you know if the second issue of postcore init is fixed in any other
patches.

thanks,
srini


From b-cousson at ti.com  Fri May 31 08:53:56 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 May 2013 14:53:56 +0200
Subject: [PATCH v4 0/5] ARM: dts: OMAP2+: Use preprocessor for device trees
In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <51A89D64.9000803@ti.com>

Hi Florian,

On 05/31/2013 02:32 PM, Florian Vaussard wrote:
> Hello,
> 
> Following a similar proposal by Stephen Warren for tegra [1], this series
> makes use of the C preprocessor when compiling OMAP DT files, and
> accomplishes some improvements to improve overall readability.
> 
> Patch 1 is a preparation for the rest of the series.
> Patch 2 uses existing constants for GPIOs. Patch 3 does the same for
> IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses
> it to simplify pinctrl DT.
> 
> As for previous versions, the .dtb files were diff-tested before and after
> applying the series to guarantee identity for all targets.
> 
> The same series for AM3XXX will follow shortly.
> 
> Best regards,
> 
> Florian

Thanks for the series. I've just applied it and will push the update
for_3.11/dts branch ASAP.

Regards,
Benoit



From 21cnbao at gmail.com  Fri May 31 08:56:58 2013
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 31 May 2013 20:56:58 +0800
Subject: [PATCH v1 1/2] ARM:prima2: move sirfsoc_of_rstc_init to
 .init_early
In-Reply-To: <51A89ACE.8030604@st.com>
References: <1369993439-24216-1-git-send-email-srinivas.kandagatla@st.com>
 <1369993501-24309-1-git-send-email-srinivas.kandagatla@st.com>
 <CAGsJ_4z65+SOCQM2XKmrda+5Hu9wRuZviSvW3As1ROa0SmdXqw@mail.gmail.com>
 <51A89ACE.8030604@st.com>
Message-ID: <CAGsJ_4zaW_y0VCxZzwoK5s-Mv+M9yFXWfWuiMJ_fG9qKqDG3uQ@mail.gmail.com>

2013/5/31 Srinivas KANDAGATLA <srinivas.kandagatla at st.com>:
> On 31/05/13 13:24, Barry Song wrote:
>>> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla at st.com>
>> hi Sriniva,
>> i think my "arm: prima2: move to generic reset controller driver
>> framework" fixs this too:
>> http://www.spinics.net/lists/arm-kernel/msg246206.html
> I did look at the patch, I think it will fix it.
>
> But the patch is still using arch_initcall directly, which means this
> call will be attempted by every SOC in multi_v7 kernel.
> This call can be easily hooked into machine descriptor.
> In that way only prima compatible machines will attempt to call this
> function in first place.

mine should fix panic as it returns 0 instead of using BUG(). but i do
think we should merge yours too to avoid redundant execution path.

>
> Do you know if the second issue of postcore init is fixed in any other
> patches.

no. i will test your v2.

>
> thanks,
> srini

-barry


From g.liakhovetski at gmx.de  Fri May 31 09:08:29 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 31 May 2013 15:08:29 +0200 (CEST)
Subject: [PATCH v2] dmaengine: shdma: fix a build failure on platforms
 with no DMA support
In-Reply-To: <51A88707.4040601@ti.com>
References: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
 <51A88707.4040601@ti.com>
Message-ID: <alpine.DEB.2.00.1305311504460.6919@axis700.grange>

On Fri, 31 May 2013, Dan Murphy wrote:

> On 05/30/2013 10:01 PM, Guennadi Liakhovetski wrote:
> > On platforms with no support for the shdma dmaengine driver build is
> > currently failing with
> >
> > drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> > drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'
> >
> > Fix the breakage by defining shdma_chan_filter to NULL in such
> > configurations.
> >
> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> > ---
> >
> > v2: in "next" shdma_chan_filter() is defined in shdma-base.c, which is 
> > built if CONFIG_SH_DMAE_BASE is defined. This version uses the correct 
> > symbol.
> >
> > This is for "next." Compile-tested only. I'll test it on hardware next 
> > week, but I don't think it shall break anything.
> >
> >  include/linux/sh_dma.h |    4 ++++
> >  1 files changed, 4 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
> > index b64d6be..1fd8a20 100644
> > --- a/include/linux/sh_dma.h
> > +++ b/include/linux/sh_dma.h
> > @@ -99,6 +99,10 @@ struct sh_dmae_pdata {
> >  #define CHCR_TE	0x00000002
> >  #define CHCR_IE	0x00000004
> >  
> > +#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
> >  bool shdma_chan_filter(struct dma_chan *chan, void *arg);
> > +#else
> > +#define shdma_chan_filter NULL
> OK I did not see a reply to my previous comment
> Would this not be better as a
> #else
> static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg) { return false; }
> #endif
> 
> Otherwise runtime will call a NULL pointer

Have you looked at the code?:

		if (fn && !fn(chan, fn_param)) {

Have you considered, when this channel allocation at all has a chance to 
get as far as to checking the filter? Have you thought about the meaning 
of "inline" when uing a function to assign it to a pointer? Are you sure 
"will" is the right word here?

Thanks
Guennadi

> > +#endif
> >  
> >  #endif
> 
> 
> -- 
> ------------------
> Dan Murphy
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From daniel.lezcano at linaro.org  Fri May 31 09:18:35 2013
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 31 May 2013 15:18:35 +0200
Subject: [PATCH 3/3] ARM: tegra114: cpuidle: add powered-down state
In-Reply-To: <1370000680.7804.83.camel@jlo-ubuntu-64.nvidia.com>
References: <1369912782-30663-1-git-send-email-josephl@nvidia.com>
 <1369912782-30663-4-git-send-email-josephl@nvidia.com>
 <51A763BD.6070001@linaro.org>
 <1369991550.7804.37.camel@jlo-ubuntu-64.nvidia.com>
 <51A86D11.8060305@linaro.org>
 <1369997278.7804.73.camel@jlo-ubuntu-64.nvidia.com>
 <1369999870.7804.78.camel@jlo-ubuntu-64.nvidia.com>
 <1370000680.7804.83.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <51A8A32B.6080303@linaro.org>

On 05/31/2013 01:44 PM, Joseph Lo wrote:
> On Fri, 2013-05-31 at 19:31 +0800, Joseph Lo wrote:
>> On Fri, 2013-05-31 at 18:47 +0800, Joseph Lo wrote:
>>> On Fri, 2013-05-31 at 17:27 +0800, Daniel Lezcano wrote:
>>>> On 05/31/2013 11:12 AM, Joseph Lo wrote:
>>>>> Hi Daniel,
>>>>>
>>>>> Thanks for your review.
>>>>>
>>>>> On Thu, 2013-05-30 at 22:35 +0800, Daniel Lezcano wrote:
>>>>>> On 05/30/2013 01:19 PM, Joseph Lo wrote:
>>>>>>> This supports CPU core power down on each CPU when CPU idle. When CPU go
>>>>>>> into this state, it saves it's context and needs a proper configuration
>>>>>>> in flow controller to power gate the CPU when CPU runs into WFI
>>>>>>> instruction. And the CPU also needs to set the IRQ as CPU power down idle
>>>>>>> wake up event in flow controller.
>>>>>>>
>>>>>>> Signed-off-by: Joseph Lo <josephl at nvidia.com>
>>>>>>> ---
>>>>>>
>>>>>> Hi Joseph,
>>>>>>
>>>>>> a new flag has been added in the cpuidle framework to let this one to
>>>>>> handle the timer broadcast : CPUIDLE_FLAG_TIMER_STOP
>>>>>>
>>>>>> It is the commit b60e6a0eb0273132cbb60a9806abf5f47a4aee1c
>>>>>>
>>>>>> You can get rid of the clockevent notify stuff by adding this flag to
>>>>>> the state.
>>>>>>
>>>>>
>>>>> I just tested this flag on Tegra20, 30 and 114. It is only OK on
>>>>> Tegra20. It caused a warning message below on Tegra30/114 at boot time.
>>>>>
>>>>> I gave it a quick check I found it can't clean
>>>>> tick_broadcast_pending_mask sometimes if apply the flag. But I keep the
>>>>> code right now it's always OK. Not sure why? 
>>>>
>>>> Is it possible you didn't intialized the timer broadcast with
>>>> CLOCK_EVT_NOTIFY_BROADCAST_ON in the driver and then this one is
>>>> actually disabled for you driver ?
>>>>
>>> I found if I don't apply the CPUIDLE_FLAG_TIMER_STOP flag, the function
>>> "cpuidle_setup_broadcast_timer" (drivers/cpuidle/driver.c) would not be
>>> called. Then it's OK.
>>>
>>> If I apply this flag (with no CONFIG_CPU_IDLE_MULTIPLE_DRIVERS), the
>>> cpuidle_register_driver only register for CPU0. Then the
>>> "cpuidle_setup_broadcast_timer" only turn on for CPU0. I think this
>>> might be the root cause. Not sure this also can reproduce on the other
>>> SoCs?
>>>
>> Looks it's not related to CLOCK_EVT_NOTIFY_BROADCAST_ON. I still saw the
>> warning message even enable CONFIG_CPU_IDLE_MULTIPLE_DRIVERS. But if I
>> move the clockevent_notify of CLOCK_EVT_NOTIFY_BROADCAST_EXIT from idle
>> framework back to driver, then everything is OK.
>>
> Once I move the clockevent_notify of CLOCK_EVT_NOTIFY_BROADCAST_EXIT
> right after "local_irq_enable" in the
> "cpuidle_enter_state" (drivers/cpuidle/cpuidle.c). Then the warning
> message shows up.

Is it possible you pastebin you kernel config file ? I would like to
check a couple of things before investigating the code.

Thanks


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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From stefano.stabellini at eu.citrix.com  Fri May 31 09:21:16 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 31 May 2013 14:21:16 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <20130531105915.GC18045@localhost.cambridge.arm.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531105915.GC18045@localhost.cambridge.arm.com>
Message-ID: <alpine.DEB.2.02.1305311419280.4799@kaball.uk.xensource.com>

On Fri, 31 May 2013, Catalin Marinas wrote:
> On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > --- a/arch/arm/include/asm/xen/page.h
> > +++ b/arch/arm/include/asm/xen/page.h
> > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> >  	return __set_phys_to_machine(pfn, mfn);
> >  }
> >  
> > +#ifdef CONFIG_ARM64
> > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > +#else
> >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > +#endif
> 
> Now I saw the ARM-specific part. Can you not use something like
> ioremap_cached() which would give normal cacheable memory (at least on
> ARMv7).

No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
needs to be MT_MEMORY. It is used for normal memory pages, not device
memory.


From b-cousson at ti.com  Fri May 31 09:23:37 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 May 2013 15:23:37 +0200
Subject: [GIT PULL] ARM: OMAP: dts fixes for 3.10-rc4
Message-ID: <51A8A459.1000706@ti.com>

Hi Tony,

Please pull two DTS fixes for the next -rc.

Thanks,
Benoit


The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:
  Linus Torvalds (1):
        Linux 3.10-rc3

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git dts-fixes-for-3.10

Kevin Hilman (1):
      ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line

Lars Poeschel (1):
      ARM: dts: AM33xx: Fix properties on gpmc node

 arch/arm/boot/dts/am33xx.dtsi             |    4 ++--
 arch/arm/boot/dts/omap4-panda-common.dtsi |   20 ++++++++++++++++++++
 arch/arm/boot/dts/omap4-sdp.dts           |   20 ++++++++++++++++++++
 3 files changed, 42 insertions(+), 2 deletions(-)


From stefano.stabellini at eu.citrix.com  Fri May 31 09:25:20 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 31 May 2013 14:25:20 +0100
Subject: [PATCH RFC 2/6] arm64/xen: arm/xen header changes to compile on
 arm64
In-Reply-To: <20130531104303.GB18045@localhost.cambridge.arm.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531104303.GB18045@localhost.cambridge.arm.com>
Message-ID: <alpine.DEB.2.02.1305311422250.4799@kaball.uk.xensource.com>

On Fri, 31 May 2013, Catalin Marinas wrote:
> On Thu, May 30, 2013 at 05:18:29PM +0100, Stefano Stabellini wrote:
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/include/asm/xen/events.h |    4 ++++
> >  arch/arm/include/asm/xen/page.h   |    2 ++
> >  2 files changed, 6 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
> > index 8b1f37b..12e4e0b 100644
> > --- a/arch/arm/include/asm/xen/events.h
> > +++ b/arch/arm/include/asm/xen/events.h
> > @@ -13,7 +13,11 @@ enum ipi_vector {
> >  
> >  static inline int xen_irqs_disabled(struct pt_regs *regs)
> >  {
> > +#ifdef CONFIG_ARM
> >  	return raw_irqs_disabled_flags(regs->ARM_cpsr);
> > +#else
> > +	return raw_irqs_disabled_flags((unsigned long) regs->pstate);
> > +#endif
> >  }
> 
> At least for this part, it makes sense to live in the arch/arm64
> directory.

Yes, good idea, there isn't much else in that header file anyway.


> >  #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr),	\
> > diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
> > index 30cdacb..cb2fa15 100644
> > --- a/arch/arm/include/asm/xen/page.h
> > +++ b/arch/arm/include/asm/xen/page.h
> > @@ -1,7 +1,9 @@
> >  #ifndef _ASM_ARM_XEN_PAGE_H
> >  #define _ASM_ARM_XEN_PAGE_H
> >  
> > +#ifdef ARM
> >  #include <asm/mach/map.h>
> > +#endif
> >  #include <asm/page.h>
> >  #include <asm/pgtable.h>
> 
> Is there anything ARM-specific in this file?

The only ARM-specific stuff here is the definition of xen_remap, like
you have spotted in the other email. The inclusion of asm/mach/map.h is
needed because it containes the definition of MT_MEMORY.


From catalin.marinas at arm.com  Fri May 31 09:10:38 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 14:10:38 +0100
Subject: [PATCH RFC 1/6] [HACK!] arm64/xen: create links to arch/arm
 include files and Xen code
In-Reply-To: <alpine.DEB.2.02.1305311259090.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531103617.GA18045@localhost.cambridge.arm.com>
 <alpine.DEB.2.02.1305311259090.4799@kaball.uk.xensource.com>
Message-ID: <20130531131038.GA15551@arm.com>

On Fri, May 31, 2013 at 01:02:04PM +0100, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Catalin Marinas wrote:
> > On Thu, May 30, 2013 at 05:18:28PM +0100, Stefano Stabellini wrote:
> > > Most of Xen support for ARM is common between ARMv7 and ARMv8.
> > > Create links to the code under arch/arm (bleah).
> > > 
> > > Other, probably better alternatives:
> > > 
> > > - move the code to a different location, maybe the header files to
> > > include/xen/arm and the code to drivers/xen/arm (still pretty ugly)?
> > > 
> > > - create a copy of the code to arch/arm64 (even worse);
> > 
> > KVM handles this in the Makefile by referencing back to arch/arm or even
> > the generic kvm directory. I think that's the 'cleanest' ;)
> 
> Do you mean creating links in the Makefile or generating header file
> copies from the Makefile?
> Or do you mean using something like "-I arch/arm/include/asm/xen" in the
> arch/arm64 Makefile?

I meant C files being compiled directly from arch/arm (no links).

For headers, if they are specific to arm or arm64, just copy the header
in each place (e.g. not using regs->pstate in the arch/arm code with
#ifdef's). For the rest, if they cannot be made generic, one way is to
have a dummy file including the arm equivalent:

#include <../../arm/include/asm/xen/events.h>

Passing -I is dangerous as you actually need "-I arch/arm/include" which
could bring other files.

-- 
Catalin


From arnd at arndb.de  Fri May 31 09:51:58 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 15:51:58 +0200
Subject: [PATCH 12/39] ARM: u300: set up board power from device tree
In-Reply-To: <CACRpkdYXfm4xzqn2Kb0fw2_+BSSXBoNXye2zu3fpv1sPQcHO9w@mail.gmail.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <6621177.ZgrPQ48FXE@wuerfel>
 <CACRpkdYXfm4xzqn2Kb0fw2_+BSSXBoNXye2zu3fpv1sPQcHO9w@mail.gmail.com>
Message-ID: <4270774.6CqcMSP3z0@wuerfel>

On Friday 31 May 2013 13:33:45 Linus Walleij wrote:
> Mark remarked on the first iteration that:
> 
> > I would expect this to be bound based on the board name that appears in
> > the device tree which (given the way this stuff mostly works) I'd expect
> > to have a device node available.
> 
> This is what I'm trying to do here.
> 
> The root node which actually contains the compatible-string
> for the board itself can *not* be used, as the OF platform core
> code does not create a platform device for this node, and it
> cannot reference anything either.
> 
> So a single board node directly in the root was the best
> I could come up with, other suggestions welcome...

I think I would actually put this into a machine_desc callback for a
machine that matches just this one board: If this is truly board
specific, this is where it belongs.

Of course we try to have a single machine_desc work with any board
normally, but the machine_desc is also the abstraction we already
have for boards. There is a device_node for '/', but as you say
there is no 'struct device' attached to it.

If it is not really a property of a particular board, but something
that you would need for other boards as well, it could perhaps
be tied to the syscon functionality, or to ab3100:

ab3100_regulators_probe() could itself set up the the supply
and then set the syscon bit. Basically you just move all of 
arch/arm/mach-u300/regulator.c into drivers/regulator/ab3100.c

	Arnd


From arnd at arndb.de  Fri May 31 09:53:10 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 15:53:10 +0200
Subject: [PATCH 02/39] ARM: u300: device tree support for the timer
In-Reply-To: <CACRpkdZYsnUhjYO_U4L56TMY+fs+ZU9zk3zLWnjPtf8Bmmn0YQ@mail.gmail.com>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <7742928.6bJiIVUE0X@wuerfel>
 <CACRpkdZYsnUhjYO_U4L56TMY+fs+ZU9zk3zLWnjPtf8Bmmn0YQ@mail.gmail.com>
Message-ID: <2014595.XlPVsySsVh@wuerfel>

On Friday 31 May 2013 13:26:31 Linus Walleij wrote:
> 
> > You should not need the CONFIG_OF #ifdef, since the CLOCKSOURCE_OF_DECLARE
> > macro is designed to let the function get dropped by the compiler when
> > that is not set.
> >
> > You might want a CONFIG_ATAGS check for the other function though.
> 
> Both the other function and the #ifdef CONFIG_OF are deleted in
> patch 21. Is this OK?

Ok, that's fine then.

> >> diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
> >> index d34287b..7766dfa 100644
> >> --- a/arch/arm/mach-u300/timer.h
> >> +++ b/arch/arm/mach-u300/timer.h
> >> @@ -1 +1,2 @@
> >>  extern void u300_timer_init(void);
> >> +
> >
> > You probably didn't mean to include this newline.
> 
> This entire file is also deleted in patch 21.
> 
> I can fix it up if you absolutely want to but it feels like
> something of an academic exercise.

No, not if that is the only change you'd do to this patch.

	Arnd


From arnd at arndb.de  Fri May 31 09:56:45 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 15:56:45 +0200
Subject: [PATCH 2/2] ARM: shmobile: sdhi: remove DMA hardware dependencies
In-Reply-To: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
References: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
Message-ID: <1370008605-3745603-2-git-send-email-arnd@arndb.de>

The MMC driver should not need to care what the dma engine
is that it is using, so it must not rely on the argument
to the filter function to be a 'slave_id' value.

Passing the slave id in dmaengine_slave_config is not
portable, and does not work with DT-enabled systems,
so this turns the filter argument into a void pointer
that gets set by the platform code and gets passed
to the dmaengine code as an opaque value.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
Cc: Chris Ball <cjb at laptop.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/board-ag5evm.c          |  4 ++--
 arch/arm/mach-shmobile/board-ap4evb.c          |  8 ++++----
 arch/arm/mach-shmobile/board-armadillo800eva.c |  8 ++++----
 arch/arm/mach-shmobile/board-kzm9g.c           |  8 ++++----
 arch/arm/mach-shmobile/board-mackerel.c        | 12 ++++++------
 drivers/mmc/host/sh_mobile_sdhi.c              | 20 +++-----------------
 drivers/mmc/host/tmio_mmc_dma.c                |  6 ++----
 include/linux/mfd/tmio.h                       |  2 --
 include/linux/mmc/sh_mobile_sdhi.h             |  5 +++--
 9 files changed, 28 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index ad01651..cb467fb 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -405,8 +405,8 @@ static struct regulator_consumer_supply fixed2v8_power_consumers[] =
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index c900e24..d7ccb2e 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -357,8 +357,8 @@ static struct platform_device sh_mmcif_device = {
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_caps	= MMC_CAP_SDIO_IRQ,
@@ -398,8 +398,8 @@ static struct platform_device sdhi0_device = {
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI1_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI1_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_ocr_mask	= MMC_VDD_165_195,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index e95e5dc..fcea414 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -690,8 +690,8 @@ static struct platform_device vcc_sdhi1 = {
 #define IRQ31	irq_pin(31)
 static struct sh_mobile_sdhi_info sdhi0_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
@@ -735,8 +735,8 @@ static struct platform_device sdhi0_device = {
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI1_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI1_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 0434b36..3f3092f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -444,8 +444,8 @@ static struct platform_device vcc_sdhi2 = {
 /* SDHI */
 static struct sh_mobile_sdhi_info sdhi0_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT,
@@ -489,8 +489,8 @@ static struct platform_device sdhi0_device = {
 /* Micro SD */
 static struct sh_mobile_sdhi_info sdhi2_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI2_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI2_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI2_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI2_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 49755ff..4522b76 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -973,8 +973,8 @@ static struct platform_device nand_flash_device = {
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_flags	= TMIO_MMC_USE_GPIO_CD,
@@ -1015,8 +1015,8 @@ static struct platform_device sdhi0_device = {
 /* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
 static struct sh_mobile_sdhi_info sdhi1_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI1_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI1_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
@@ -1061,8 +1061,8 @@ static struct platform_device sdhi1_device = {
  */
 static struct sh_mobile_sdhi_info sdhi2_info = {
 #ifdef CONFIG_SH_DMAE_BASE
-	.dma_slave_tx	= SHDMA_SLAVE_SDHI2_TX,
-	.dma_slave_rx	= SHDMA_SLAVE_SDHI2_RX,
+	.dma_slave_tx	= (void *)SHDMA_SLAVE_SDHI2_TX,
+	.dma_slave_rx	= (void *)SHDMA_SLAVE_SDHI2_RX,
 	.dma_filter	= shdma_chan_filter,
 #endif
 	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index efe3386..c4a0aab 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -185,23 +185,9 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
 		if (p->get_cd)
 			mmc_data->get_cd = sh_mobile_sdhi_get_cd;
 
-		if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) {
-			/*
-			 * Yes, we have to provide slave IDs twice to TMIO:
-			 * once as a filter parameter and once for channel
-			 * configuration as an explicit slave ID
-			 */
-			dma_priv->chan_priv_tx = (void *)p->dma_slave_tx;
-			dma_priv->chan_priv_rx = (void *)p->dma_slave_rx;
-			/*
-			 * This is a layering violation: the slave driver
-			 * should not be aware that the chan_priv_* is the
-			 * slave id.
-			 * We should not really need to set the slave id
-			 * here anyway. -arnd
-			 */
-			dma_priv->slave_id_tx = p->dma_slave_tx;
-			dma_priv->slave_id_rx = p->dma_slave_rx;
+		if (p->dma_slave_tx && p->dma_slave_rx) {
+			dma_priv->chan_priv_tx = p->dma_slave_tx;
+			dma_priv->chan_priv_rx = p->dma_slave_rx;
 			dma_priv->filter = p->dma_filter;
 		}
 	}
diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c
index 47bdb8f..caad28e 100644
--- a/drivers/mmc/host/tmio_mmc_dma.c
+++ b/drivers/mmc/host/tmio_mmc_dma.c
@@ -290,8 +290,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat
 		if (!host->chan_tx)
 			return;
 
-		if (pdata->dma->chan_priv_tx)
-			cfg.slave_id = pdata->dma->slave_id_tx;
+		cfg.slave_id = 0; /* already set */
 		cfg.direction = DMA_MEM_TO_DEV;
 		cfg.dst_addr = res->start + (CTL_SD_DATA_PORT << host->bus_shift);
 		cfg.src_addr = 0;
@@ -308,8 +307,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat
 		if (!host->chan_rx)
 			goto ereqrx;
 
-		if (pdata->dma->chan_priv_rx)
-			cfg.slave_id = pdata->dma->slave_id_rx;
+		cfg.slave_id = 0;
 		cfg.direction = DMA_DEV_TO_MEM;
 		cfg.src_addr = cfg.dst_addr;
 		cfg.dst_addr = 0;
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index ce35113..0990d8a 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -86,8 +86,6 @@ struct dma_chan;
 struct tmio_mmc_dma {
 	void *chan_priv_tx;
 	void *chan_priv_rx;
-	int slave_id_tx;
-	int slave_id_rx;
 	int alignment_shift;
 	bool (*filter)(struct dma_chan *chan, void *arg);
 };
diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h
index 342f07b..66a7d1c 100644
--- a/include/linux/mmc/sh_mobile_sdhi.h
+++ b/include/linux/mmc/sh_mobile_sdhi.h
@@ -2,6 +2,7 @@
 #define LINUX_MMC_SH_MOBILE_SDHI_H
 
 #include <linux/types.h>
+#include <linux/dmaengine.h>
 
 struct platform_device;
 
@@ -18,8 +19,8 @@ struct sh_mobile_sdhi_ops {
 };
 
 struct sh_mobile_sdhi_info {
-	int dma_slave_tx;
-	int dma_slave_rx;
+	void *dma_slave_tx;
+	void *dma_slave_rx;
 	dma_filter_fn dma_filter;
 	unsigned long tmio_flags;
 	unsigned long tmio_caps;
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 09:56:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 15:56:44 +0200
Subject: [PATCH 1/2] ARM: shmobile: sdhi: pass DMA filter from platform code
Message-ID: <1370008605-3745603-1-git-send-email-arnd@arndb.de>

Since eec95ee2261 "mmc: sdhi/tmio: switch to using
dmaengine_slave_config()", we are getting a link error with
a number of shmobile configurations that turn on the sdhi
driver but the not the SH_DMAE_BASE driver.

The reason is that the driver now incorrectly refers to
a global filter function that should be referenced only
by platform code:

drivers/built-in.o: In function `sh_mobile_sdhi_probe':
drivers/mmc/host/sh_mobile_sdhi.c:202: undefined reference to `shdma_chan_filter'
drivers/mmc/host/sh_mobile_sdhi.c:202: undefined reference to `shdma_chan_filter'

The fix is to move the pointer to the filter function out
of the driver, similar to how we do it for most other
platforms. This makes the driver almost independent
of the underlying dma engine, besides the fact that
it tries to pass the same number both into the filter
function and into slave config, which only works on
some DMA engine drivers.

Since the bug is only present on the mmc tree, I think
the fix should be applied there as well.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
Cc: Chris Ball <cjb at laptop.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Simon Horman <horms+renesas at verge.net.au>
---
 arch/arm/mach-shmobile/board-ag5evm.c          |  4 ++++
 arch/arm/mach-shmobile/board-ap4evb.c          |  7 +++++++
 arch/arm/mach-shmobile/board-armadillo800eva.c |  7 +++++++
 arch/arm/mach-shmobile/board-kzm9g.c           |  7 +++++++
 arch/arm/mach-shmobile/board-mackerel.c        | 10 ++++++++++
 drivers/mmc/host/sh_mobile_sdhi.c              |  9 ++++++++-
 include/linux/mmc/sh_mobile_sdhi.h             |  1 +
 7 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index c754071..ad01651 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
+#include <linux/sh_dma.h>
 #include <linux/irqchip/arm-gic.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
@@ -403,8 +404,11 @@ static struct regulator_consumer_supply fixed2v8_power_consumers[] =
 
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED,
 	.tmio_ocr_mask	= MMC_VDD_27_28 | MMC_VDD_28_29,
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 297bf5e..c900e24 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -38,6 +38,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_clk.h>
 #include <linux/gpio.h>
@@ -355,8 +356,11 @@ static struct platform_device sh_mmcif_device = {
 
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_caps	= MMC_CAP_SDIO_IRQ,
 };
 
@@ -393,8 +397,11 @@ static struct platform_device sdhi0_device = {
 
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_ocr_mask	= MMC_VDD_165_195,
 	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE,
 	.tmio_caps	= MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 44a6215..e95e5dc 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -34,6 +34,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_eth.h>
 #include <linux/videodev2.h>
 #include <linux/usb/renesas_usbhs.h>
@@ -688,8 +689,11 @@ static struct platform_device vcc_sdhi1 = {
  */
 #define IRQ31	irq_pin(31)
 static struct sh_mobile_sdhi_info sdhi0_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_POWER_OFF_CARD,
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
@@ -730,8 +734,11 @@ static struct platform_device sdhi0_device = {
 
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_POWER_OFF_CARD,
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 165483c..0434b36 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -37,6 +37,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/sh_dma.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/renesas_usbhs.h>
 #include <linux/videodev2.h>
@@ -442,8 +443,11 @@ static struct platform_device vcc_sdhi2 = {
 
 /* SDHI */
 static struct sh_mobile_sdhi_info sdhi0_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT,
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_POWER_OFF_CARD,
@@ -484,8 +488,11 @@ static struct platform_device sdhi0_device = {
 
 /* Micro SD */
 static struct sh_mobile_sdhi_info sdhi2_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI2_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI2_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT |
 			  TMIO_MMC_USE_GPIO_CD |
 			  TMIO_MMC_WRPROTECT_DISABLE,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 85f51a8..49755ff 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -45,6 +45,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/tca6416_keypad.h>
 #include <linux/usb/renesas_usbhs.h>
@@ -971,8 +972,11 @@ static struct platform_device nand_flash_device = {
 
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_flags	= TMIO_MMC_USE_GPIO_CD,
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 	.cd_gpio	= 172,
@@ -1010,8 +1014,11 @@ static struct platform_device sdhi0_device = {
 
 /* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
 static struct sh_mobile_sdhi_info sdhi1_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_NEEDS_POLL,
@@ -1053,8 +1060,11 @@ static struct platform_device sdhi1_device = {
  * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
  */
 static struct sh_mobile_sdhi_info sdhi2_info = {
+#ifdef CONFIG_SH_DMAE_BASE
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI2_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI2_RX,
+	.dma_filter	= shdma_chan_filter,
+#endif
 	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_NEEDS_POLL,
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index cc4c872..efe3386 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -193,13 +193,20 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
 			 */
 			dma_priv->chan_priv_tx = (void *)p->dma_slave_tx;
 			dma_priv->chan_priv_rx = (void *)p->dma_slave_rx;
+			/*
+			 * This is a layering violation: the slave driver
+			 * should not be aware that the chan_priv_* is the
+			 * slave id.
+			 * We should not really need to set the slave id
+			 * here anyway. -arnd
+			 */
 			dma_priv->slave_id_tx = p->dma_slave_tx;
 			dma_priv->slave_id_rx = p->dma_slave_rx;
+			dma_priv->filter = p->dma_filter;
 		}
 	}
 
 	dma_priv->alignment_shift = 1; /* 2-byte alignment */
-	dma_priv->filter = shdma_chan_filter;
 
 	mmc_data->dma = dma_priv;
 
diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h
index b76bcf0..342f07b 100644
--- a/include/linux/mmc/sh_mobile_sdhi.h
+++ b/include/linux/mmc/sh_mobile_sdhi.h
@@ -20,6 +20,7 @@ struct sh_mobile_sdhi_ops {
 struct sh_mobile_sdhi_info {
 	int dma_slave_tx;
 	int dma_slave_rx;
+	dma_filter_fn dma_filter;
 	unsigned long tmio_flags;
 	unsigned long tmio_caps;
 	unsigned long tmio_caps2;
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 09:58:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 15:58:37 +0200
Subject: [PATCH 2/2] ARM: shmobile: sdhi: remove DMA hardware dependencies
In-Reply-To: <1370008605-3745603-2-git-send-email-arnd@arndb.de>
References: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
 <1370008605-3745603-2-git-send-email-arnd@arndb.de>
Message-ID: <2364919.FdR1Nu0Y37@wuerfel>

On Friday 31 May 2013 15:56:45 Arnd Bergmann wrote:
> --- a/include/linux/mmc/sh_mobile_sdhi.h
> +++ b/include/linux/mmc/sh_mobile_sdhi.h
> @@ -2,6 +2,7 @@
>  #define LINUX_MMC_SH_MOBILE_SDHI_H
>  
>  #include <linux/types.h>
> +#include <linux/dmaengine.h>
>  
>  struct platform_device;
>  

This hunk should have been in the first patch. I'll
wait for comments before re-sending. Don't apply as-is.

	Arnd


From linus.walleij at linaro.org  Fri May 31 10:02:34 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 16:02:34 +0200
Subject: [PATCH 12/39] ARM: u300: set up board power from device tree
In-Reply-To: <4270774.6CqcMSP3z0@wuerfel>
References: <1369991954-17406-1-git-send-email-linus.walleij@stericsson.com>
 <6621177.ZgrPQ48FXE@wuerfel>
 <CACRpkdYXfm4xzqn2Kb0fw2_+BSSXBoNXye2zu3fpv1sPQcHO9w@mail.gmail.com>
 <4270774.6CqcMSP3z0@wuerfel>
Message-ID: <CACRpkdb=Z8oFpvxni6jyaWHoQOjhFkWQ_71ku=h5UFk9pzJZ2A@mail.gmail.com>

On Fri, May 31, 2013 at 3:51 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> If it is not really a property of a particular board, but something
> that you would need for other boards as well, it could perhaps
> be tied to the syscon functionality, or to ab3100:
>
> ab3100_regulators_probe() could itself set up the the supply
> and then set the syscon bit. Basically you just move all of
> arch/arm/mach-u300/regulator.c into drivers/regulator/ab3100.c

I think this is more likely the case.

Mark: would you be OK with the ab3100 driver hogging one of its
own regulators?

Yours,
Linus Walleij


From stern at rowland.harvard.edu  Fri May 31 10:05:41 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Fri, 31 May 2013 10:05:41 -0400 (EDT)
Subject: [RFC PATCH 2/2] USB: OHCI: add a name for the platform-private
 field
In-Reply-To: <CAJFYCKECv-a8TkngRZzKfPi4apRTRtjDj2tQfRMJS94n7sSsFQ@mail.gmail.com>
Message-ID: <Pine.LNX.4.44L0.1305311005050.1276-100000@iolanthe.rowland.org>

On Fri, 31 May 2013, Manjunath Goudar wrote:

> On 30 May 2013 22:56, Alan Stern <stern at rowland.harvard.edu> wrote:
> 
> > On Thu, 30 May 2013, Manjunath Goudar wrote:
> >
> > > This patch adds an ohci->priv field for private use by OHCI
> > > platform drivers.
> > >
> > > Until now none of the platform drivers has used this private space,
> > > but that's about to change in the next patch of this series.
> >
> > As far as I'm concerned, this doesn't need to be in a patch of its own.
> > It can be merged into the 1/3 patch of the previous series.  After all,
> > that patch adds the extra_priv_size field in ohci_driver_overrides,
> > which doesn't make much sense unless there's a way to refer to the
> > private part of the ohci_hcd structure
> 
> 
> 
>  Already 1/3 patch is merged into main line kernel.

Yeah, too late now.

> Two days back only I started making ohci-spera a separate driver ,that time
> I felt extra_priv_size field is required in ohci_driver_overrides that what
> I created separate patch.
> 
> extra_priv_size patch is related to Spear patch,If you are agree,I can add
> this patch with Spear patch,making Spear patch series.

No, we may as well keep it separate like this.

Alan Stern



From b-cousson at ti.com  Fri May 31 10:06:42 2013
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 May 2013 16:06:42 +0200
Subject: [PATCH v7] ARM: dts: omap4-panda: Update the LED support for
 the panda DTS
In-Reply-To: <1369826427-31963-1-git-send-email-dmurphy@ti.com>
References: <1369826427-31963-1-git-send-email-dmurphy@ti.com>
Message-ID: <51A8AE72.5010601@ti.com>

Hi Dan,

On 05/29/2013 01:20 PM, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
> 
> A1-A3 = gpio_wk7clean
> ES = gpio_110
> 
> There is no change to LED D2
> 
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
> 
> Signed-off-by: Dan Murphy <dmurphy at ti.com>

That patch was good... until Florian introduces some new constant to
improve the readability of the DTS [1].

Could you rebase on the lastest for_3.11/dts and use the macros for the
GPIO and pinctrl nodes?

Thanks,
Benoit

[1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg89684.html

> ---
> v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
> v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
> v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/
> 
>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>  arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>  2 files changed, 43 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 03bd60d..5fd59b3 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -16,8 +16,13 @@
>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>  	};
>  
> -	leds {
> +	leds: leds {
>  		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <
> +			&led_wkgpio_pins
> +		>;
> +
>  		heartbeat {
>  			label = "pandaboard::status1";
>  			gpios = <&gpio1 7 0>;
> @@ -137,6 +142,15 @@
>  	};
>  };
>  
> +&omap4_pmx_wkup {
> +	led_wkgpio_pins: pinmux_leds_wkpins {
> +		pinctrl-single,pins = <
> +			0x1a 0x3	/* gpio_wk7 OUTPUT | MODE 3 */
> +			0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
>  &i2c1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&i2c1_pins>;
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..c968a3b 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,31 @@
>  		0x5e 0x100	/* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>  		>;
>  };
> +
> +&omap4_pmx_core {
> +	led_gpio_pins: gpio_led_pmx {
> +		pinctrl-single,pins = <
> +			0xb6 0x3	/* gpio_110 OUTPUT | MODE 3 */
> +		>;
> +	};
> +};
> +
> +&led_wkgpio_pins {
> +	pinctrl-single,pins = <
> +		0x1c 0x3	/* gpio_wk8 OUTPUT | MODE 3 */
> +	>;
> +};
> +
> +&leds {
> +	pinctrl-0 = <
> +		&led_gpio_pins
> +		&led_wkgpio_pins
> +	>;
> +
> +	heartbeat {
> +		gpios = <&gpio4 14 0>;
> +	};
> +	mmc {
> +		gpios = <&gpio1 8 0>;
> +	};
> +};
> 



From stern at rowland.harvard.edu  Fri May 31 10:07:35 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Fri, 31 May 2013 10:07:35 -0400 (EDT)
Subject: [PATCH V2 1/2] USB: OHCI: make ohci-platform a separate driver
In-Reply-To: <51a892db.3077420a.5699.0f88@mx.google.com>
Message-ID: <Pine.LNX.4.44L0.1305311005520.1276-100000@iolanthe.rowland.org>

On Fri, 31 May 2013 manjunath.goudar at linaro.org wrote:

> From: Manjunath Goudar <manjunath.goudar at linaro.org>
> 
> This patch splits the ohci-platform code from ohci-hcd out
> into its own separate driver module.This work is part of enabling
> multi-platform kernels on ARM.
> 
> In V2:
>   -Passed "hcd" argment instead of "ohci" in ohci_setup() because it is
>    using "struct usb_hcd" argment.

> @@ -30,58 +42,17 @@ static int ohci_platform_reset(struct usb_hcd *hcd)

...

> +	return ohci_setup(ohci_to_hcd(ohci));

You don't need to use ohci_to_hcd(), because the hcd value is already a 
parameter in this function.

Alan Stern



From stern at rowland.harvard.edu  Fri May 31 10:12:38 2013
From: stern at rowland.harvard.edu (Alan Stern)
Date: Fri, 31 May 2013 10:12:38 -0400 (EDT)
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <201305300002.45754.arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1305311011570.1276-100000@iolanthe.rowland.org>

On Thu, 30 May 2013, Arnd Bergmann wrote:

> > I'll try to replicate your result.  I don't have my USB audio device 
> > here today, so it will have to wait until tomorrow.
> 
> Strange enough, it seems to be working now, on a different base.
> 
> The kernel I tried last (based on yesterday's linux-next) also
> had other issues and was very slow, so it may have been something
> different.

My test ran successfully, no problems.  I guess we can ignore this.

Alan Stern



From catalin.marinas at arm.com  Fri May 31 10:15:08 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 15:15:08 +0100
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130531120519.GB3803@titan.lakedaemon.net>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130529110508.GH17767@MacBook-Pro.local>
 <20130529191657.GA13047@schnuecks.de>
 <20130530164335.GK23631@arm.com>
 <20130531120519.GB3803@titan.lakedaemon.net>
Message-ID: <20130531141508.GB15551@arm.com>

On Fri, May 31, 2013 at 01:05:19PM +0100, Jason Cooper wrote:
> On Thu, May 30, 2013 at 05:43:35PM +0100, Catalin Marinas wrote:
> > On Wed, May 29, 2013 at 08:16:57PM +0100, Simon Baatz wrote:
> > > On Wed, May 29, 2013 at 12:05:09PM +0100, Catalin Marinas wrote:
> > > > On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > > > > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > > > > it needs to handle are kernel mapped only.  However, for example when doing
> > > > > direct I/O, pages with user space mappings may occur.
> > > > 
> > > > After Nico's clarification, I think the original commit introducing this
> > > > function was also incomplete (commit 73be1591 - [ARM] 5545/2: add
> > > > flush_kernel_dcache_page() for ARM) since it ignores highmem pages and
> > > > their flushing could be deferred for a long time.
> > > 
> > > Yes, I agree.
> > >  
> > > > For my understanding (if I re-read this tread) - basically code like
> > > > this should not leave the user mapping inconsistent:
> > > > 
> > > > kmap()
> > > > ...
> > > > flush_kernel_dcache_page()
> > > > kunmap()
> > > 
> > > s/user mapping/kernel mapping/ 
> > > The user mapping(s) can be assumed to be consistent when entering
> > > such code. Either there is none or the page was obtained by a
> > > mechanism like __get_user_pages(). Otherwise, we have a problem
> > > anyway when accessing the page via the kernel mapping.
> > 
> > Indeed. What I meant was user mapping inconsistent with the kernel
> > mapping. It's the latter that needs flushing.
> > 
> > > > > Thus, continue to do lazy flushing if there are no user space mappings.
> > > > > Otherwise, flush the kernel cache lines directly.
> > > > ...
> > > > >  /*
> > > > > + * Ensure cache coherency for kernel mapping of this page.
> > > > > + *
> > > > > + * If the page only exists in the page cache and there are no user
> > > > > + * space mappings, this is a no-op since the page was already marked
> > > > > + * dirty at creation.  Otherwise, we need to flush the dirty kernel
> > > > > + * cache lines directly.
> > > > > + */
> > > > > +void flush_kernel_dcache_page(struct page *page)
> > > > > +{
> > > > > +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> > > > > +		struct address_space *mapping;
> > > > > +
> > > > > +		mapping = page_mapping(page);
> > > > > +
> > > > > +		if (!mapping || mapping_mapped(mapping))
> > > > > +			__flush_kernel_dcache_page(page);
> > > > > +	}
> > > > > +}
> > > > 
> > > > BTW, does the mapping check optimise anything for the
> > > > flush_kernel_dcache_page() uses? Would we have a mapping anyway (or
> > > > anonymous page) in most cases?
> > > 
> > > Looking at the relevant uses in the kernel, we have:
> > > 
> > >     drivers/scsi/libsas/sas_host_smp.c
> > >     drivers/mmc/host/mmc_spi.c
> > >     drivers/block/ps3disk.c
> > >     fs/exec.c
> > >     lib/scatterlist.c
> > >  
> > > That is not much (I omit my usual rant here that many uses of
> > > flush_dcache_page() in drivers are incorrect and should be uses of
> > > flush_kernel_dcache_page() ...).
> > > 
> > > Without looking at the actual code, we seem to have two basic use
> > > cases:
> > > 
> > > 1. Block drivers (the ones listed above + those using the memory
> > > scatterlist iterator in scatterlist.c)
> > > 
> > > These will probably almost exclusively use page cache pages for which
> > > we can be lazy.  Other pages only occur in special I/O situations
> > > like direct I/O.
> > > 
> > > 2. fs/exec.c
> > > 
> > > I think these are anonymous pages only
> > > 
> > > Thus depending on the actual drivers used, usage can be dominated by
> > > page cache pages on one setup and anon pages on the other.
> > > 
> > > I prefer the currently proposed way since it prevents massive
> > > overflushing if flush_kernel_dcache_page() is used in an I/O path.
> > > 
> > > (Btw. I am still puzzled as to why making flush_kernel_dcache_page()
> > > the current nop apparently did not cause problems in fs/exec.c.)
> > 
> > We get extra flushing via flush_old_exec() -> exec_mmap() -> mmput() ->
> > exit_mmap() -> flush_cache_mm() before we actually start the new exec so
> > this would flush the arg page as well.
> > 
> > > > Otherwise the patch looks good.
> > > 
> > > Thanks. Especially, thanks for pointing out the highmem case.
> > 
> > You can add my ack (before I forget the whole discussion ;))
> > 
> > Acked-by: Catalin Marinas <catalin.marinas at arm.com>
> 
> wrt to 73be1591, this appears to go all the way back to v2.6.31.x... Can
> Simon go ahead and put this in rmk's patch tracker and mention that it
> should go to all -stable trees?

I'm not sure how easy it is to apply this patch on past stable versions.
Maybe something simpler for stable like always flushing the cache in
flush_kernel_dcache_page() with optimisation only in recent stable
versions.

-- 
Catalin


From catalin.marinas at arm.com  Fri May 31 10:16:01 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 15:16:01 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <alpine.DEB.2.02.1305311419280.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531105915.GC18045@localhost.cambridge.arm.com>
 <alpine.DEB.2.02.1305311419280.4799@kaball.uk.xensource.com>
Message-ID: <20130531141601.GC15551@arm.com>

On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Catalin Marinas wrote:
> > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > --- a/arch/arm/include/asm/xen/page.h
> > > +++ b/arch/arm/include/asm/xen/page.h
> > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > >  	return __set_phys_to_machine(pfn, mfn);
> > >  }
> > >  
> > > +#ifdef CONFIG_ARM64
> > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > +#else
> > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > +#endif
> > 
> > Now I saw the ARM-specific part. Can you not use something like
> > ioremap_cached() which would give normal cacheable memory (at least on
> > ARMv7).
> 
> No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> needs to be MT_MEMORY. It is used for normal memory pages, not device
> memory.

MT_DEVICE_CACHED is Normal memory for ARMv7.

-- 
Catalin


From jason at lakedaemon.net  Fri May 31 10:20:10 2013
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 31 May 2013 10:20:10 -0400
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20130531141508.GB15551@arm.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <20130529110508.GH17767@MacBook-Pro.local>
 <20130529191657.GA13047@schnuecks.de>
 <20130530164335.GK23631@arm.com>
 <20130531120519.GB3803@titan.lakedaemon.net>
 <20130531141508.GB15551@arm.com>
Message-ID: <20130531142010.GC3803@titan.lakedaemon.net>

On Fri, May 31, 2013 at 03:15:08PM +0100, Catalin Marinas wrote:
> On Fri, May 31, 2013 at 01:05:19PM +0100, Jason Cooper wrote:
> > On Thu, May 30, 2013 at 05:43:35PM +0100, Catalin Marinas wrote:
> > > On Wed, May 29, 2013 at 08:16:57PM +0100, Simon Baatz wrote:
> > > > On Wed, May 29, 2013 at 12:05:09PM +0100, Catalin Marinas wrote:
> > > > > On Sun, May 12, 2013 at 06:35:56AM +0100, Simon Baatz wrote:
> > > > > > Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages
> > > > > > it needs to handle are kernel mapped only.  However, for example when doing
> > > > > > direct I/O, pages with user space mappings may occur.
> > > > > 
> > > > > After Nico's clarification, I think the original commit introducing this
> > > > > function was also incomplete (commit 73be1591 - [ARM] 5545/2: add
> > > > > flush_kernel_dcache_page() for ARM) since it ignores highmem pages and
> > > > > their flushing could be deferred for a long time.
> > > > 
> > > > Yes, I agree.
> > > >  
> > > > > For my understanding (if I re-read this tread) - basically code like
> > > > > this should not leave the user mapping inconsistent:
> > > > > 
> > > > > kmap()
> > > > > ...
> > > > > flush_kernel_dcache_page()
> > > > > kunmap()
> > > > 
> > > > s/user mapping/kernel mapping/ 
> > > > The user mapping(s) can be assumed to be consistent when entering
> > > > such code. Either there is none or the page was obtained by a
> > > > mechanism like __get_user_pages(). Otherwise, we have a problem
> > > > anyway when accessing the page via the kernel mapping.
> > > 
> > > Indeed. What I meant was user mapping inconsistent with the kernel
> > > mapping. It's the latter that needs flushing.
> > > 
> > > > > > Thus, continue to do lazy flushing if there are no user space mappings.
> > > > > > Otherwise, flush the kernel cache lines directly.
> > > > > ...
> > > > > >  /*
> > > > > > + * Ensure cache coherency for kernel mapping of this page.
> > > > > > + *
> > > > > > + * If the page only exists in the page cache and there are no user
> > > > > > + * space mappings, this is a no-op since the page was already marked
> > > > > > + * dirty at creation.  Otherwise, we need to flush the dirty kernel
> > > > > > + * cache lines directly.
> > > > > > + */
> > > > > > +void flush_kernel_dcache_page(struct page *page)
> > > > > > +{
> > > > > > +	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> > > > > > +		struct address_space *mapping;
> > > > > > +
> > > > > > +		mapping = page_mapping(page);
> > > > > > +
> > > > > > +		if (!mapping || mapping_mapped(mapping))
> > > > > > +			__flush_kernel_dcache_page(page);
> > > > > > +	}
> > > > > > +}
> > > > > 
> > > > > BTW, does the mapping check optimise anything for the
> > > > > flush_kernel_dcache_page() uses? Would we have a mapping anyway (or
> > > > > anonymous page) in most cases?
> > > > 
> > > > Looking at the relevant uses in the kernel, we have:
> > > > 
> > > >     drivers/scsi/libsas/sas_host_smp.c
> > > >     drivers/mmc/host/mmc_spi.c
> > > >     drivers/block/ps3disk.c
> > > >     fs/exec.c
> > > >     lib/scatterlist.c
> > > >  
> > > > That is not much (I omit my usual rant here that many uses of
> > > > flush_dcache_page() in drivers are incorrect and should be uses of
> > > > flush_kernel_dcache_page() ...).
> > > > 
> > > > Without looking at the actual code, we seem to have two basic use
> > > > cases:
> > > > 
> > > > 1. Block drivers (the ones listed above + those using the memory
> > > > scatterlist iterator in scatterlist.c)
> > > > 
> > > > These will probably almost exclusively use page cache pages for which
> > > > we can be lazy.  Other pages only occur in special I/O situations
> > > > like direct I/O.
> > > > 
> > > > 2. fs/exec.c
> > > > 
> > > > I think these are anonymous pages only
> > > > 
> > > > Thus depending on the actual drivers used, usage can be dominated by
> > > > page cache pages on one setup and anon pages on the other.
> > > > 
> > > > I prefer the currently proposed way since it prevents massive
> > > > overflushing if flush_kernel_dcache_page() is used in an I/O path.
> > > > 
> > > > (Btw. I am still puzzled as to why making flush_kernel_dcache_page()
> > > > the current nop apparently did not cause problems in fs/exec.c.)
> > > 
> > > We get extra flushing via flush_old_exec() -> exec_mmap() -> mmput() ->
> > > exit_mmap() -> flush_cache_mm() before we actually start the new exec so
> > > this would flush the arg page as well.
> > > 
> > > > > Otherwise the patch looks good.
> > > > 
> > > > Thanks. Especially, thanks for pointing out the highmem case.
> > > 
> > > You can add my ack (before I forget the whole discussion ;))
> > > 
> > > Acked-by: Catalin Marinas <catalin.marinas at arm.com>
> > 
> > wrt to 73be1591, this appears to go all the way back to v2.6.31.x... Can
> > Simon go ahead and put this in rmk's patch tracker and mention that it
> > should go to all -stable trees?
> 
> I'm not sure how easy it is to apply this patch on past stable versions.
> Maybe something simpler for stable like always flushing the cache in
> flush_kernel_dcache_page() with optimisation only in recent stable
> versions.

Ok, then please don't let that hold this up.  We can do something separate
for stable later if it's desired.

thx,

Jason.


From lee.jones at linaro.org  Fri May 31 10:24:31 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 15:24:31 +0100
Subject: [PATCH 1/2] ARM: ux500: Allocate correct amount of memory for the
 u8540 in DT
Message-ID: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>

As it stands, the memory node in the u8540 Device Tree is ignored and
memory is actually stipulated by the bootloader via ATAGS. ARM core
architecture code then extracts the memory ATAG and inserts it into the
Device Tree. In the u8540 the LittleKernel bootloader only stipulates
512MB of memory; however, the u8540 actually has 4GB. We're taking the
responsibility to register the remainder from Device Tree here.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/ccu8540.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
index 12f0bc2..199866b 100644
--- a/arch/arm/boot/dts/ccu8540.dts
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -16,8 +16,8 @@
 	model = "ST-Ericsson U8540 platform with Device Tree";
 	compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
 
-	memory {
-		reg = <0x00000000 0x20000000>;
+	memory at 0 {
+		reg = <0x20000000 0x3f000000>, <0xc0000000 0x3f000000>;
 	};
 
 	soc {
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May 31 10:24:32 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 15:24:32 +0100
Subject: [PATCH 2/2] ARM: ux500: Enable HIGHMEM in the u8540 defconfig
In-Reply-To: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>
References: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1370010272-25520-2-git-send-email-lee.jones@linaro.org>

In order to utilise all of the memory located on ux500 based devices
we have to enable HIGHMEM. Without it the kernel truncates memory down
to what's left after the PAGE_OFFSET has been applied, which doesn't
leave an awful lot, especially if we're running large rootfs' such
as full Linux desktop distributions or Android.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/configs/u8500_defconfig |    1 +
 drivers/of/fdt.c                 |   52 +++++++-------------------------------
 2 files changed, 10 insertions(+), 43 deletions(-)

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d322d2..38d633a 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -1,3 +1,4 @@
+CONFIG_HIGHMEM=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 5439925..808be06 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -43,7 +43,7 @@ void *of_fdt_get_property(struct boot_param_header *blob,
 
 	do {
 		u32 tag = be32_to_cpup((__be32 *)p);
-		u32 sz, noff, i;
+		u32 sz, noff;
 		const char *nstr;
 
 		p += 4;
@@ -66,10 +66,6 @@ void *of_fdt_get_property(struct boot_param_header *blob,
 		if (strcmp(name, nstr) == 0) {
 			if (size)
 				*size = sz;
-
-	print_hex_dump(KERN_ERR, "node: ", DUMP_PREFIX_ADDRESS,
-		       16, 1, (__be32 *)node, p - node, true);
-
 			return (void *)p;
 		}
 		p += sz;
@@ -624,68 +620,38 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname,
 	__be32 *reg, *endp;
 	unsigned long l;
 
-	printk("LEE: ******************************************* \n");
-	printk("LEE: ******************************************* \n");
-	printk("LEE: ******************************************* \n");
-	printk("LEE: ******************************************* \n");
-	printk("LEE: ******************************************* \n");
-	printk("LEE: ******************************************* \n");
-	printk("LEE: ******************************************* \n");
-
 	/* We are scanning "memory" nodes only */
 	if (type == NULL) {
-		printk("LEE: 1\n");
 		/*
 		 * The longtrail doesn't have a device_type on the
 		 * /memory node, so look for the node called /memory at 0.
 		 */
-		if (depth != 1 || strcmp(uname, "memory at 0") != 0) {
-			printk("LEE: 2\n");
+		if (depth != 1 || strcmp(uname, "memory at 0") != 0)
 			return 0;
-		}
-	} else if (strcmp(type, "memory") != 0) {
-		printk("LEE: 3\n");
+	} else if (strcmp(type, "memory") != 0)
 		return 0;
-	}
 
 	reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
-	if (reg == NULL) {
+	if (reg == NULL)
 		reg = of_get_flat_dt_prop(node, "reg", &l);
-		printk("LEE: This is correct \n");
-	}
-	if (reg == NULL) {
-		printk("LEE: 4\n");
-       		return 0;
-	}
-
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
-	printk("LEE: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n");
+	if (reg == NULL)
+		return 0;
 
 	endp = reg + (l / sizeof(__be32));
 
-	printk("LEE: reg: 0x%p\n", reg);
-
-	printk("memory scan node %s, reg size %ld, data: %x %x %x %x,\n",
+	pr_debug("memory scan node %s, reg size %ld, data: %x %x %x %x,\n",
 	    uname, l, reg[0], reg[1], reg[2], reg[3]);
 
-	printk("extras: %x %x %x %x,\n", reg[4], reg[5], reg[6], reg[7]);
-
 	while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
 		u64 base, size;
 
 		base = dt_mem_next_cell(dt_root_addr_cells, &reg);
 		size = dt_mem_next_cell(dt_root_size_cells, &reg);
 
-		printk(" - %llx ,  %llx\n", (unsigned long long)base,
-		    (unsigned long long)size);
-
 		if (size == 0)
 			continue;
+		pr_debug(" - %llx ,  %llx\n", (unsigned long long)base,
+		    (unsigned long long)size);
 
 		early_init_dt_add_memory_arch(base, size);
 	}
-- 
1.7.10.4



From dmurphy at ti.com  Fri May 31 10:29:42 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 09:29:42 -0500
Subject: [PATCH v7] ARM: dts: omap4-panda: Update the LED support for
 the panda DTS
In-Reply-To: <51A8AE72.5010601@ti.com>
References: <1369826427-31963-1-git-send-email-dmurphy@ti.com>
 <51A8AE72.5010601@ti.com>
Message-ID: <51A8B3D6.1020608@ti.com>

Hi
On 05/31/2013 09:06 AM, Benoit Cousson wrote:
> Hi Dan,
>
> On 05/29/2013 01:20 PM, Dan Murphy wrote:
>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>> are different.
>>
>> A1-A3 = gpio_wk7clean
>> ES = gpio_110
>>
>> There is no change to LED D2
>>
>> Abstract away the pinmux and the LED definitions for the two boards into
>> the respective DTS files.
>>
>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> That patch was good... until Florian introduces some new constant to
> improve the readability of the DTS [1].
>
> Could you rebase on the lastest for_3.11/dts and use the macros for the
> GPIO and pinctrl nodes?
N/P working on it now

Thanks
> Thanks,
> Benoit
>
> [1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg89684.html
>

-- 
------------------
Dan Murphy



From linus.walleij at linaro.org  Fri May 31 10:30:13 2013
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 31 May 2013 16:30:13 +0200
Subject: [GIT PULL] ux500 fixes for the v3.10 series
Message-ID: <CACRpkdY11CLBVTtWcXFDfWjrgfizhK45WnkR8b7CL8JwqQy8pg@mail.gmail.com>

Hi ARM SoC folks,

here are two fixes from Lee Jones which hopefully fixes up the
last pieces of fallout from the v3.10 merge window. Description
in the signed tag.

Please pull them in for fixes to Torvalds.

Yours,
Linus Walleij


The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:

  Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-arm-soc-v3.10-fixes-2

for you to fetch changes up to 67b7c75e1a42f8288450203cd80a26b11dab8582:

  ARM: ux500: Provide supplies for AUX1, AUX2 and AUX3 (2013-05-27
14:08:20 +0200)

----------------------------------------------------------------
Ux500 fixes for v3.10:
- A multiplatform fix making sure ux500_idle_init() is only
  executed on ux500.
- A regulator fix making sure the MMC/SD card regulator is
  not disabled on boot.

----------------------------------------------------------------
Lee Jones (2):
      ARM: ux500: Only configure wake-up reasons on ux500 based platforms
      ARM: ux500: Provide supplies for AUX1, AUX2 and AUX3

 arch/arm/mach-ux500/board-mop500-regulators.c | 3 +++
 arch/arm/mach-ux500/cpuidle.c                 | 4 ++++
 2 files changed, 7 insertions(+)


From dmurphy at ti.com  Fri May 31 10:48:02 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 09:48:02 -0500
Subject: [PATCH v8] ARM: dts: omap4-panda: Update the LED support for the
 panda DTS
Message-ID: <1370011682-20675-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
v8 - Rebase to latest and use pinctrl macros - https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/

 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..523a800 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <
+			&led_wkgpio_pins
+		>;
+
 		heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
@@ -157,6 +162,15 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk7 OUTPUT | MODE 3 */
+			0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..5551ec6 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
 		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
+
+&omap4_pmx_core {
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 (PIN_OUTPUT | MUX_MODE3)	/* gpio_110 OUTPUT | MODE 3 */
+		>;
+	};
+};
+
+&led_wkgpio_pins {
+	pinctrl-single,pins = <
+		0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 OUTPUT | MODE 3 */
+	>;
+};
+
+&leds {
+	pinctrl-0 = <
+		&led_gpio_pins
+		&led_wkgpio_pins
+	>;
+
+	heartbeat {
+		gpios = <&gpio4 14 0>;
+	};
+	mmc {
+		gpios = <&gpio1 8 0>;
+	};
+};
-- 
1.7.5.4



From stefano.stabellini at eu.citrix.com  Fri May 31 10:50:16 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 31 May 2013 15:50:16 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <20130531141601.GC15551@arm.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531105915.GC18045@localhost.cambridge.arm.com>
 <alpine.DEB.2.02.1305311419280.4799@kaball.uk.xensource.com>
 <20130531141601.GC15551@arm.com>
Message-ID: <alpine.DEB.2.02.1305311530440.4799@kaball.uk.xensource.com>

On Fri, 31 May 2013, Catalin Marinas wrote:
> On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > > --- a/arch/arm/include/asm/xen/page.h
> > > > +++ b/arch/arm/include/asm/xen/page.h
> > > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > > >  	return __set_phys_to_machine(pfn, mfn);
> > > >  }
> > > >  
> > > > +#ifdef CONFIG_ARM64
> > > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > > +#else
> > > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > > +#endif
> > > 
> > > Now I saw the ARM-specific part. Can you not use something like
> > > ioremap_cached() which would give normal cacheable memory (at least on
> > > ARMv7).
> > 
> > No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> > needs to be MT_MEMORY. It is used for normal memory pages, not device
> > memory.
> 
> MT_DEVICE_CACHED is Normal memory for ARMv7.

I didn't realize that MT_DEVICE_CACHED and MT_MEMORY end up having the
same AttrIndx encoding!
In that case yes, I should be able to use it.
I take that I should just implement ioremap_cached on arm64 as well?


From arnd at arndb.de  Fri May 31 10:51:52 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 16:51:52 +0200
Subject: [PATCH v2] dmaengine: shdma: fix a build failure on platforms
 with no DMA support
In-Reply-To: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
References: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
Message-ID: <3410825.gK3KBC8v80@wuerfel>

On Friday 31 May 2013 05:01:31 Guennadi Liakhovetski wrote:
> On platforms with no support for the shdma dmaengine driver build is
> currently failing with
> 
> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'
> 
> Fix the breakage by defining shdma_chan_filter to NULL in such
> configurations.
> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>

Sorry, I saw your patch too late and already spent some time doing a different one.

> diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
> index b64d6be..1fd8a20 100644
> --- a/include/linux/sh_dma.h
> +++ b/include/linux/sh_dma.h
> @@ -99,6 +99,10 @@ struct sh_dmae_pdata {
>  #define CHCR_TE        0x00000002
>  #define CHCR_IE        0x00000004
>  
> +#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
>  bool shdma_chan_filter(struct dma_chan *chan, void *arg);
> +#else
> +#define shdma_chan_filter NULL
> +#endif

I still think that this is not the right solution, or at least not
complete: No slave driver should care about which dma-engine it is
connected to. You have already done most of the necessary conversion,
so it would be straightforward to also pass the filter function
pointer to the sdhi driver along with the data that gets passed into
it.

	Arnd


From g.liakhovetski at gmx.de  Fri May 31 10:52:13 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 31 May 2013 16:52:13 +0200 (CEST)
Subject: [PATCH 1/2] ARM: shmobile: sdhi: pass DMA filter from platform
 code
In-Reply-To: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
References: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
Message-ID: <alpine.DEB.2.00.1305311611460.7395@axis700.grange>

Hi Arnd

Thanks for the patches. How about this fix:

http://thread.gmane.org/gmane.linux.kernel.mmc/20619

I think it's a better fix. SHDMA users cannot use other DMA drivers, so, I 
don't think we need to pass the filter via the platform data.

Thanks
Guennadi

On Fri, 31 May 2013, Arnd Bergmann wrote:

> Since eec95ee2261 "mmc: sdhi/tmio: switch to using
> dmaengine_slave_config()", we are getting a link error with
> a number of shmobile configurations that turn on the sdhi
> driver but the not the SH_DMAE_BASE driver.
> 
> The reason is that the driver now incorrectly refers to
> a global filter function that should be referenced only
> by platform code:
> 
> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
> drivers/mmc/host/sh_mobile_sdhi.c:202: undefined reference to `shdma_chan_filter'
> drivers/mmc/host/sh_mobile_sdhi.c:202: undefined reference to `shdma_chan_filter'
> 
> The fix is to move the pointer to the filter function out
> of the driver, similar to how we do it for most other
> platforms. This makes the driver almost independent
> of the underlying dma engine, besides the fact that
> it tries to pass the same number both into the filter
> function and into slave config, which only works on
> some DMA engine drivers.
> 
> Since the bug is only present on the mmc tree, I think
> the fix should be applied there as well.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Simon Horman <horms+renesas at verge.net.au>
> ---
>  arch/arm/mach-shmobile/board-ag5evm.c          |  4 ++++
>  arch/arm/mach-shmobile/board-ap4evb.c          |  7 +++++++
>  arch/arm/mach-shmobile/board-armadillo800eva.c |  7 +++++++
>  arch/arm/mach-shmobile/board-kzm9g.c           |  7 +++++++
>  arch/arm/mach-shmobile/board-mackerel.c        | 10 ++++++++++
>  drivers/mmc/host/sh_mobile_sdhi.c              |  9 ++++++++-
>  include/linux/mmc/sh_mobile_sdhi.h             |  1 +
>  7 files changed, 44 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
> index c754071..ad01651 100644
> --- a/arch/arm/mach-shmobile/board-ag5evm.c
> +++ b/arch/arm/mach-shmobile/board-ag5evm.c
> @@ -42,6 +42,7 @@
>  #include <linux/mmc/sh_mobile_sdhi.h>
>  #include <linux/mfd/tmio.h>
>  #include <linux/sh_clk.h>
> +#include <linux/sh_dma.h>
>  #include <linux/irqchip/arm-gic.h>
>  #include <video/sh_mobile_lcdc.h>
>  #include <video/sh_mipi_dsi.h>
> @@ -403,8 +404,11 @@ static struct regulator_consumer_supply fixed2v8_power_consumers[] =
>  
>  /* SDHI0 */
>  static struct sh_mobile_sdhi_info sdhi0_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED,
>  	.tmio_ocr_mask	= MMC_VDD_27_28 | MMC_VDD_28_29,
> diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
> index 297bf5e..c900e24 100644
> --- a/arch/arm/mach-shmobile/board-ap4evb.c
> +++ b/arch/arm/mach-shmobile/board-ap4evb.c
> @@ -38,6 +38,7 @@
>  #include <linux/regulator/fixed.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/smsc911x.h>
> +#include <linux/sh_dma.h>
>  #include <linux/sh_intc.h>
>  #include <linux/sh_clk.h>
>  #include <linux/gpio.h>
> @@ -355,8 +356,11 @@ static struct platform_device sh_mmcif_device = {
>  
>  /* SDHI0 */
>  static struct sh_mobile_sdhi_info sdhi0_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_caps	= MMC_CAP_SDIO_IRQ,
>  };
>  
> @@ -393,8 +397,11 @@ static struct platform_device sdhi0_device = {
>  
>  /* SDHI1 */
>  static struct sh_mobile_sdhi_info sdhi1_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_ocr_mask	= MMC_VDD_165_195,
>  	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE,
>  	.tmio_caps	= MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
> diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
> index 44a6215..e95e5dc 100644
> --- a/arch/arm/mach-shmobile/board-armadillo800eva.c
> +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
> @@ -34,6 +34,7 @@
>  #include <linux/regulator/fixed.h>
>  #include <linux/regulator/gpio-regulator.h>
>  #include <linux/regulator/machine.h>
> +#include <linux/sh_dma.h>
>  #include <linux/sh_eth.h>
>  #include <linux/videodev2.h>
>  #include <linux/usb/renesas_usbhs.h>
> @@ -688,8 +689,11 @@ static struct platform_device vcc_sdhi1 = {
>   */
>  #define IRQ31	irq_pin(31)
>  static struct sh_mobile_sdhi_info sdhi0_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
>  			  MMC_CAP_POWER_OFF_CARD,
>  	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
> @@ -730,8 +734,11 @@ static struct platform_device sdhi0_device = {
>  
>  /* SDHI1 */
>  static struct sh_mobile_sdhi_info sdhi1_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
>  			  MMC_CAP_POWER_OFF_CARD,
>  	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
> diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
> index 165483c..0434b36 100644
> --- a/arch/arm/mach-shmobile/board-kzm9g.c
> +++ b/arch/arm/mach-shmobile/board-kzm9g.c
> @@ -37,6 +37,7 @@
>  #include <linux/regulator/fixed.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/smsc911x.h>
> +#include <linux/sh_dma.h>
>  #include <linux/usb/r8a66597.h>
>  #include <linux/usb/renesas_usbhs.h>
>  #include <linux/videodev2.h>
> @@ -442,8 +443,11 @@ static struct platform_device vcc_sdhi2 = {
>  
>  /* SDHI */
>  static struct sh_mobile_sdhi_info sdhi0_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT,
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
>  			  MMC_CAP_POWER_OFF_CARD,
> @@ -484,8 +488,11 @@ static struct platform_device sdhi0_device = {
>  
>  /* Micro SD */
>  static struct sh_mobile_sdhi_info sdhi2_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI2_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI2_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT |
>  			  TMIO_MMC_USE_GPIO_CD |
>  			  TMIO_MMC_WRPROTECT_DISABLE,
> diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
> index 85f51a8..49755ff 100644
> --- a/arch/arm/mach-shmobile/board-mackerel.c
> +++ b/arch/arm/mach-shmobile/board-mackerel.c
> @@ -45,6 +45,7 @@
>  #include <linux/regulator/fixed.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/smsc911x.h>
> +#include <linux/sh_dma.h>
>  #include <linux/sh_intc.h>
>  #include <linux/tca6416_keypad.h>
>  #include <linux/usb/renesas_usbhs.h>
> @@ -971,8 +972,11 @@ static struct platform_device nand_flash_device = {
>  
>  /* SDHI0 */
>  static struct sh_mobile_sdhi_info sdhi0_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_flags	= TMIO_MMC_USE_GPIO_CD,
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
>  	.cd_gpio	= 172,
> @@ -1010,8 +1014,11 @@ static struct platform_device sdhi0_device = {
>  
>  /* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
>  static struct sh_mobile_sdhi_info sdhi1_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI1_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
>  			  MMC_CAP_NEEDS_POLL,
> @@ -1053,8 +1060,11 @@ static struct platform_device sdhi1_device = {
>   * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
>   */
>  static struct sh_mobile_sdhi_info sdhi2_info = {
> +#ifdef CONFIG_SH_DMAE_BASE
>  	.dma_slave_tx	= SHDMA_SLAVE_SDHI2_TX,
>  	.dma_slave_rx	= SHDMA_SLAVE_SDHI2_RX,
> +	.dma_filter	= shdma_chan_filter,
> +#endif
>  	.tmio_flags	= TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
>  	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
>  			  MMC_CAP_NEEDS_POLL,
> diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
> index cc4c872..efe3386 100644
> --- a/drivers/mmc/host/sh_mobile_sdhi.c
> +++ b/drivers/mmc/host/sh_mobile_sdhi.c
> @@ -193,13 +193,20 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
>  			 */
>  			dma_priv->chan_priv_tx = (void *)p->dma_slave_tx;
>  			dma_priv->chan_priv_rx = (void *)p->dma_slave_rx;
> +			/*
> +			 * This is a layering violation: the slave driver
> +			 * should not be aware that the chan_priv_* is the
> +			 * slave id.
> +			 * We should not really need to set the slave id
> +			 * here anyway. -arnd
> +			 */
>  			dma_priv->slave_id_tx = p->dma_slave_tx;
>  			dma_priv->slave_id_rx = p->dma_slave_rx;
> +			dma_priv->filter = p->dma_filter;
>  		}
>  	}
>  
>  	dma_priv->alignment_shift = 1; /* 2-byte alignment */
> -	dma_priv->filter = shdma_chan_filter;
>  
>  	mmc_data->dma = dma_priv;
>  
> diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h
> index b76bcf0..342f07b 100644
> --- a/include/linux/mmc/sh_mobile_sdhi.h
> +++ b/include/linux/mmc/sh_mobile_sdhi.h
> @@ -20,6 +20,7 @@ struct sh_mobile_sdhi_ops {
>  struct sh_mobile_sdhi_info {
>  	int dma_slave_tx;
>  	int dma_slave_rx;
> +	dma_filter_fn dma_filter;
>  	unsigned long tmio_flags;
>  	unsigned long tmio_caps;
>  	unsigned long tmio_caps2;
> -- 
> 1.8.1.2
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From arnd at arndb.de  Fri May 31 10:57:58 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 16:57:58 +0200
Subject: [PATCH V8 0/3] USB: OHCI: Start splitting up the driver
In-Reply-To: <Pine.LNX.4.44L0.1305311011570.1276-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1305311011570.1276-100000@iolanthe.rowland.org>
Message-ID: <5039645.ToQR1GYgdC@wuerfel>

On Friday 31 May 2013 10:12:38 Alan Stern wrote:
> On Thu, 30 May 2013, Arnd Bergmann wrote:
> 
> > > I'll try to replicate your result.  I don't have my USB audio device 
> > > here today, so it will have to wait until tomorrow.
> > 
> > Strange enough, it seems to be working now, on a different base.
> > 
> > The kernel I tried last (based on yesterday's linux-next) also
> > had other issues and was very slow, so it may have been something
> > different.
> 
> My test ran successfully, no problems.  I guess we can ignore this.

Ok, good.

	Arnd


From lee.jones at linaro.org  Fri May 31 10:58:16 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 15:58:16 +0100
Subject: [PATCH 2/2] ARM: ux500: Enable HIGHMEM in the u8540 defconfig
In-Reply-To: <1370010272-25520-2-git-send-email-lee.jones@linaro.org>
References: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>
 <1370010272-25520-2-git-send-email-lee.jones@linaro.org>
Message-ID: <20130531145816.GB12488@gmail.com>

Ah, cack!

One of the pitfalls of autonomously using the '-a' flag.

I'll re-spin.


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From grygorii.strashko at ti.com  Fri May 31 10:55:38 2013
From: grygorii.strashko at ti.com (Grygorii Strashko)
Date: Fri, 31 May 2013 17:55:38 +0300
Subject: [PATCH 11/11] i2c: omap: enhance pinctrl support
In-Reply-To: <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
 <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <51A8B9EA.6030604@ti.com>

On 05/31/2013 01:13 PM, Hebbar Gururaja wrote:
> Amend the I2C omap pin controller to optionally take a pin control
> handle and set the state of the pins to:
>
> - "default" on boot, resume and before performing an i2c transfer
> - "idle" after initial default, after resume default, and after each
> i2c xfer
> - "sleep" on suspend()
>
> By optionally putting the pins into sleep state in the suspend callback
> we can accomplish two things.
> - One is to minimize current leakage from pins and thus save power,
> - second, we can prevent the IP from driving pins output in an
> uncontrolled manner, which may happen if the power domain drops the
> domain regulator.
>
> Note:
> A .suspend & .resume callback is added which simply puts the pins to sleep
> state upon suspend & are moved to default & idle state upon resume.
>
> If any of the above pin states are missing in dt, a warning message
> about the missing state is displayed.
> If certain pin-states are not available, to remove this warning message
> pass respective state name with null phandler.
>
> (Changes based on i2c-nomadik.c)
>
> Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Wolfram Sang <wsa at the-dreams.de>
> Cc: linux-omap at vger.kernel.org
> Cc: linux-i2c at vger.kernel.org
> ---
> :100644 100644 e02f9e3... 588ba28... M	drivers/i2c/busses/i2c-omap.c
>   drivers/i2c/busses/i2c-omap.c |  112 ++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 105 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index e02f9e3..588ba28 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -214,7 +214,11 @@ struct omap_i2c_dev {
>   	u16			westate;
>   	u16			errata;
>   
> -	struct pinctrl		*pins;
> +	/* Three pin states - default, idle & sleep */
> +	struct pinctrl			*pinctrl;
> +	struct pinctrl_state		*pins_default;
> +	struct pinctrl_state		*pins_idle;
> +	struct pinctrl_state		*pins_sleep;
>   };
>   
>   static const u8 reg_map_ip_v1[] = {
> @@ -641,6 +645,11 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>   	if (IS_ERR_VALUE(r))
>   		goto out;
>   
The current HWMOD framework configures PINs to enable state before 
enabling the device and
switch PINs to idle state after disabling the device. Why here its done 
in different order?
> +	/* Optionaly enable pins to be muxed in and configured */
> +	if (!IS_ERR(dev->pins_default))
> +		if (pinctrl_select_state(dev->pinctrl, dev->pins_default))
> +			dev_err(dev->dev, "could not set default pins\n");
> +
>   	r = omap_i2c_wait_for_bb(dev);
>   	if (r < 0)
>   		goto out;
> @@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>   
>   out:
>   	pm_runtime_mark_last_busy(dev->dev);
> +
>   	pm_runtime_put_autosuspend(dev->dev);
> +	/* Optionally let pins go into idle state */
> +	if (!IS_ERR(dev->pins_idle))
> +		if (pinctrl_select_state(dev->pinctrl, dev->pins_idle))
> +			dev_err(dev->dev, "could not set pins to idle state\n");
> +
>   	return r;
>   }
>   
> @@ -1123,14 +1138,47 @@ omap_i2c_probe(struct platform_device *pdev)
>   		dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
>   	}
>   
> -	dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
> -	if (IS_ERR(dev->pins)) {
> -		if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
> +	dev->pinctrl = devm_pinctrl_get(&pdev->dev);
May be struct device ->pins->p can be used instead of dev->pinctrl?
> +	if (!IS_ERR(dev->pinctrl)) {
> +		dev->pins_default = pinctrl_lookup_state(dev->pinctrl,
> +							 PINCTRL_STATE_DEFAULT);
> +		if (IS_ERR(dev->pins_default))
> +			dev_dbg(&pdev->dev, "could not get default pinstate\n");
> +		else
> +			if (pinctrl_select_state(dev->pinctrl,
> +						 dev->pins_default))
> +				dev_err(&pdev->dev,
> +					"could not set default pinstate\n");
Don't need to set Default pin state
Default pins state is applied by DD framework automatically before 
device probing
and stored in struct device ->pins->default_state
> +
> +		dev->pins_idle = pinctrl_lookup_state(dev->pinctrl,
> +						      PINCTRL_STATE_IDLE);
> +		if (IS_ERR(dev->pins_idle))
> +			dev_dbg(&pdev->dev, "could not get idle pinstate\n");
> +		else
> +			/* If possible, let's idle until the first transfer */
> +			if (pinctrl_select_state(dev->pinctrl, dev->pins_idle))
> +				dev_err(&pdev->dev,
> +					"could not set idle pinstate\n");
> +
> +		dev->pins_sleep = pinctrl_lookup_state(dev->pinctrl,
> +						       PINCTRL_STATE_SLEEP);
> +		if (IS_ERR(dev->pins_sleep))
> +			dev_dbg(&pdev->dev, "could not get sleep pinstate\n");
> +	} else {
> +		if (PTR_ERR(dev->pinctrl) == -EPROBE_DEFER)
>   			return -EPROBE_DEFER;
>   
> -		dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
> -			 PTR_ERR(dev->pins));
> -		dev->pins = NULL;
> +		/*
> +		* Since we continue even when pinctrl node is not found,
> +		* Invalidate pins as not available. This is to make sure that
> +		* IS_ERR(pins_xxx) results in failure when used.
> +		*/
> +		dev->pins_default = ERR_PTR(-ENODATA);
> +		dev->pins_idle = ERR_PTR(-ENODATA);
> +		dev->pins_sleep = ERR_PTR(-ENODATA);
> +
> +		dev_dbg(&pdev->dev, "did not get pins for i2c error: %li\n",
> +			PTR_ERR(dev->pinctrl));
>   	}
>   
>   	dev->dev = &pdev->dev;
> @@ -1300,6 +1348,10 @@ static int omap_i2c_runtime_suspend(struct device *dev)
>   		omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
>   	}
>   
> +	if (!IS_ERR(_dev->pins_idle))
> +		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_idle))
> +			dev_err(dev, "could not set pins to idle state\n");
> +
It's done in omap_i2c_xfer
>   	return 0;
>   }
>   
> @@ -1311,13 +1363,59 @@ static int omap_i2c_runtime_resume(struct device *dev)
>   	if (!_dev->regs)
>   		return 0;
>   
> +	/* Optionally place the pins to the default state */
> +	if (!IS_ERR(_dev->pins_default))
> +		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_default))
> +			dev_err(dev, "could not set pins to default state\n");
> +
It's done in omap_i2c_xfer
>   	__omap_i2c_init(_dev);
>   
>   	return 0;
>   }
>   #endif /* CONFIG_PM_RUNTIME */
>   
> +#ifdef CONFIG_PM_SLEEP
> +static int omap_i2c_suspend(struct device *dev)
Please, use .suspend_noirq() - it's possible that I2C will be used
even after "device suspend" stage especially on SMP platforms((( ),
but its prohibited to use it after "suspend_noirq" stage (
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
> +
> +	pm_runtime_get_sync(dev);
Here is the better way to detect late I2C activities during suspending:
     i2c_lock_adapter(&_dev->adapter);

     /* Check for active I2C transaction */
     if (atomic_read(&dev->power.usage_count) > 1) {
         dev_info(dev,
              "active I2C transaction detected - suspend aborted\n");
         return -EBUSY;
     }

     i2c_unlock_adapter(&_dev->adapter);
> +	if (omap_i2c_wait_for_bb(_dev) < 0) {
> +		pm_runtime_put_sync(dev);
> +		return -EBUSY;
> +	}
> +	pm_runtime_put_sync(dev);
> +
> +	if (!IS_ERR(_dev->pins_sleep))
> +		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_sleep))
> +			dev_err(dev, "could not set pins to sleep state\n");
> +
> +	return 0;
> +}
Not sure it's right - Lest assume suspend_noirq() is used here.
Then, at this point, OMAP device framework will disable device 
(_od_suspend_noirq()).
But PINs will be switched to IDLE state before that. Is it ok?
Possibly Kevin could clarify this point?
> +
> +static int omap_i2c_resume(struct device *dev)
Please, use .resume_noirq()
> +{
The same is here - OMAP device framework will enable device 
(_od_suspend_noirq()) here.
But PINs are still in IDLE state???
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
> +
> +	/* First go to the default state */
> +	if (!IS_ERR(_dev->pins_default))
> +		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_default))
> +			dev_err(dev, "could not set pins to default state\n");
> +
> +	/* Then let's idle the pins until the next transfer happens */
> +	if (!IS_ERR(_dev->pins_idle))
> +		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_idle))
> +			dev_err(dev, "could not set pins to idle state\n");
> +
This is wrong - at this moment I2C device can be as in Enabled state
as in Disabled
> +	return 0;
> +}
> +#endif
> +
> +
>   static struct dev_pm_ops omap_i2c_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(omap_i2c_suspend, omap_i2c_resume)
>   	SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
>   			   omap_i2c_runtime_resume, NULL)
>   };



From dmurphy at ti.com  Fri May 31 11:00:29 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 10:00:29 -0500
Subject: [PATCH v2] dmaengine: shdma: fix a build failure on platforms
 with no DMA support
In-Reply-To: <alpine.DEB.2.00.1305311504460.6919@axis700.grange>
References: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
 <51A88707.4040601@ti.com> <alpine.DEB.2.00.1305311504460.6919@axis700.grange>
Message-ID: <51A8BB0D.9060907@ti.com>

On 05/31/2013 08:08 AM, Guennadi Liakhovetski wrote:
> On Fri, 31 May 2013, Dan Murphy wrote:
>
>> On 05/30/2013 10:01 PM, Guennadi Liakhovetski wrote:
>>> On platforms with no support for the shdma dmaengine driver build is
>>> currently failing with
>>>
>>> drivers/built-in.o: In function `sh_mobile_sdhi_probe':
>>> drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter'
>>>
>>> Fix the breakage by defining shdma_chan_filter to NULL in such
>>> configurations.
>>>
>>> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas at gmail.com>
>>> ---
>>>
>>> v2: in "next" shdma_chan_filter() is defined in shdma-base.c, which is 
>>> built if CONFIG_SH_DMAE_BASE is defined. This version uses the correct 
>>> symbol.
>>>
>>> This is for "next." Compile-tested only. I'll test it on hardware next 
>>> week, but I don't think it shall break anything.
>>>
>>>  include/linux/sh_dma.h |    4 ++++
>>>  1 files changed, 4 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
>>> index b64d6be..1fd8a20 100644
>>> --- a/include/linux/sh_dma.h
>>> +++ b/include/linux/sh_dma.h
>>> @@ -99,6 +99,10 @@ struct sh_dmae_pdata {
>>>  #define CHCR_TE	0x00000002
>>>  #define CHCR_IE	0x00000004
>>>  
>>> +#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
>>>  bool shdma_chan_filter(struct dma_chan *chan, void *arg);
>>> +#else
>>> +#define shdma_chan_filter NULL
>> OK I did not see a reply to my previous comment
>> Would this not be better as a
>> #else
>> static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg) { return false; }
>> #endif
>>
>> Otherwise runtime will call a NULL pointer
> Have you looked at the code?:
>
> 		if (fn && !fn(chan, fn_param)) {
>
> Have you considered, when this channel allocation at all has a chance to 
> get as far as to checking the filter? Have you thought about the meaning 
> of "inline" when uing a function to assign it to a pointer? Are you sure 
> "will" is the right word here?
My consideration was that since this is an exported symbol that a driver could call this API explicitly without checking for
the function pointer first, there is a potential of calling a NULL pointer.

Dan
> Thanks
> Guennadi
>
>>> +#endif
>>>  
>>>  #endif
>>
>> -- 
>> ------------------
>> Dan Murphy
>>
> ---
> Guennadi Liakhovetski, Ph.D.
> Freelance Open-Source Software Developer
> http://www.open-technology.de/


-- 
------------------
Dan Murphy



From richard.genoud at gmail.com  Fri May 31 11:01:59 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 31 May 2013 17:01:59 +0200
Subject: [PATCH 1/2] spi: atmel: convert to dma_request_slave_channel_compat()
Message-ID: <1370012520-30539-1-git-send-email-richard.genoud@gmail.com>

Use generic DMA DT helper.
Platforms booting with or without DT populated are both supported.

Based on Ludovic Desroches <ludovic.desroches at atmel.com> patchset
"ARM: at91: move to generic DMA device tree binding"

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/spi/spi-atmel.c |   42 +++++++++++++++++++++++++++---------------
 1 file changed, 27 insertions(+), 15 deletions(-)

rebased on linux-next next-20130531

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 31cfc87..ea1ec00 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -424,10 +424,15 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 	return err;
 }
 
-static bool filter(struct dma_chan *chan, void *slave)
+static bool filter(struct dma_chan *chan, void *pdata)
 {
-	struct	at_dma_slave *sl = slave;
+	struct atmel_spi_dma *sl_pdata = pdata;
+	struct at_dma_slave *sl;
 
+	if (!sl_pdata)
+		return false;
+
+	sl = &sl_pdata->dma_slave;
 	if (sl->dma_dev == chan->device->dev) {
 		chan->private = sl;
 		return true;
@@ -438,24 +443,31 @@ static bool filter(struct dma_chan *chan, void *slave)
 
 static int atmel_spi_configure_dma(struct atmel_spi *as)
 {
-	struct at_dma_slave *sdata = &as->dma.dma_slave;
 	struct dma_slave_config	slave_config;
+	struct device *dev = &as->pdev->dev;
 	int err;
 
-	if (sdata && sdata->dma_dev) {
-		dma_cap_mask_t mask;
+	dma_cap_mask_t mask;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
 
-		/* Try to grab two DMA channels */
-		dma_cap_zero(mask);
-		dma_cap_set(DMA_SLAVE, mask);
-		as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
-		if (as->dma.chan_tx)
-			as->dma.chan_rx =
-				dma_request_channel(mask, filter, sdata);
+	as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
+							   &as->dma,
+							   dev, "tx");
+	if (!as->dma.chan_tx) {
+		dev_err(dev,
+			"DMA TX channel not available, SPI unable to use DMA\n");
+		err = -EBUSY;
+		goto error;
 	}
-	if (!as->dma.chan_rx || !as->dma.chan_tx) {
-		dev_err(&as->pdev->dev,
-			"DMA channel not available, SPI unable to use DMA\n");
+
+	as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
+							   &as->dma,
+							   dev, "rx");
+
+	if (!as->dma.chan_rx) {
+		dev_err(dev,
+			"DMA RX channel not available, SPI unable to use DMA\n");
 		err = -EBUSY;
 		goto error;
 	}
-- 
1.7.10.4



From richard.genoud at gmail.com  Fri May 31 11:02:00 2013
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 31 May 2013 17:02:00 +0200
Subject: [PATCH 2/2] ARM: at91: dt: at91sam9x5: add SPI DMA client infos
In-Reply-To: <1370012520-30539-1-git-send-email-richard.genoud@gmail.com>
References: <1370012520-30539-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1370012520-30539-2-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

rebased on linux-next next-20130531
plus Ludovic Desroches' patch "ARM: at91: dt: add header to define at_hdmac configuration"
to get the AT91_DMA_CFG_PER_ID() macro

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599..a5942d0 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -629,6 +629,9 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
 				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
+				       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
+				dma-names = "tx", "rx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
@@ -640,6 +643,9 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
+				       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
+				dma-names = "tx", "rx";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
-- 
1.7.10.4



From arnd at arndb.de  Fri May 31 11:02:53 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:02:53 +0200
Subject: [PATCH 2/2] ARM: ux500: Enable HIGHMEM in the u8540 defconfig
In-Reply-To: <1370010272-25520-2-git-send-email-lee.jones@linaro.org>
References: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>
 <1370010272-25520-2-git-send-email-lee.jones@linaro.org>
Message-ID: <38058740.G1EqTG95pA@wuerfel>

On Friday 31 May 2013 15:24:32 Lee Jones wrote:
> In order to utilise all of the memory located on ux500 based devices
> we have to enable HIGHMEM. Without it the kernel truncates memory down
> to what's left after the PAGE_OFFSET has been applied, which doesn't
> leave an awful lot, especially if we're running large rootfs' such
> as full Linux desktop distributions or Android.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

How much memory do those devices have? Enabling HIGHMEM is quite expensive.

> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 5439925..808be06 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c

You should probably resend the patch without the second half that got
in it by accident.

	ARnd


From eduardo.valentin at ti.com  Fri May 31 11:03:24 2013
From: eduardo.valentin at ti.com (Eduardo Valentin)
Date: Fri, 31 May 2013 11:03:24 -0400
Subject: [PATCHv2 1/3] arm: introduce config HAS_BANDGAP
In-Reply-To: <1368629928-6723-2-git-send-email-eduardo.valentin@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-2-git-send-email-eduardo.valentin@ti.com>
Message-ID: <51A8BBBC.9000505@ti.com>

Tony, Russell,



On 15-05-2013 10:58, Eduardo Valentin wrote:
> Introduce HAS_BANDGAP config entry. This config is a
> boolean value so that arch code can flag is they
> feature a bandgap device.
> 
> This config entry follows the same idea behind
> ARCH_HAS_CPUFREQ.
> 
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-omap at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>

Gentle reminder on this one.

> ---
>  arch/arm/Kconfig            | 3 +++
>  arch/arm/mach-omap2/Kconfig | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d423d58..bcbdec9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -174,6 +174,9 @@ config ARCH_HAS_CPUFREQ
>  	  and that the relevant menu configurations are displayed for
>  	  it.
>  
> +config ARCH_HAS_BANDGAP
> +	bool
> +
>  config GENERIC_HWEIGHT
>  	bool
>  	default y
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f49cd51..8620ab5 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -4,6 +4,7 @@ config ARCH_OMAP
>  config ARCH_OMAP2PLUS
>  	bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
>  	select ARCH_HAS_CPUFREQ
> +	select ARCH_HAS_BANDGAP
>  	select ARCH_HAS_HOLES_MEMORYMODEL
>  	select ARCH_OMAP
>  	select ARCH_REQUIRE_GPIOLIB
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin

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From arnd at arndb.de  Fri May 31 11:04:17 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:04:17 +0200
Subject: [PATCH v2] dmaengine: shdma: fix a build failure on platforms
 with no DMA support
In-Reply-To: <51A8BB0D.9060907@ti.com>
References: <Pine.LNX.4.64.1305310423360.1470@axis700.grange>
 <alpine.DEB.2.00.1305311504460.6919@axis700.grange> <51A8BB0D.9060907@ti.com>
Message-ID: <4422231.HoYmB8LUsn@wuerfel>

On Friday 31 May 2013 10:00:29 Dan Murphy wrote:
> My consideration was that since this is an exported symbol that a driver
> could call this API explicitly without checking for
> the function pointer first, there is a potential of calling a NULL pointer.

Drivers never call a filter function directly, so that is not an issue.
Even if a driver would try it, that would not actually compile.
	
	Arnd


From javier at dowhile0.org  Fri May 31 11:05:58 2013
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Fri, 31 May 2013 17:05:58 +0200
Subject: [PATCH v8] ARM: dts: omap4-panda: Update the LED support for the
 panda DTS
In-Reply-To: <1370011682-20675-1-git-send-email-dmurphy@ti.com>
References: <1370011682-20675-1-git-send-email-dmurphy@ti.com>
Message-ID: <CABxcv=mCh38XgFoRSrZ8BK5U5EFDb-1Fb70FoLyNqb0V3WQm-g@mail.gmail.com>

On Fri, May 31, 2013 at 4:48 PM, Dan Murphy <dmurphy at ti.com> wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
>
> A1-A3 = gpio_wk7
> ES = gpio_110
>
> There is no change to LED D2
>
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
>
> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> ---
> v8 - Rebase to latest and use pinctrl macros - https://patchwork.kernel.org/patch/2629351/
> v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
> v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
> v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/
>
>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>  arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>  2 files changed, 43 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index d5d144a..523a800 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -16,8 +16,13 @@
>                 reg = <0x80000000 0x40000000>; /* 1 GB */
>         };
>
> -       leds {
> +       leds: leds {
>                 compatible = "gpio-leds";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <
> +                       &led_wkgpio_pins
> +               >;
> +
>                 heartbeat {
>                         label = "pandaboard::status1";
>                         gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> @@ -157,6 +162,15 @@
>         };
>  };
>
> +&omap4_pmx_wkup {
> +       led_wkgpio_pins: pinmux_leds_wkpins {
> +               pinctrl-single,pins = <
> +                       0x1a (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk7 OUTPUT | MODE 3 */
> +                       0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 OUTPUT | MODE 3 */

Hello Dan,

The OUTPUT | MODE 3 in the comments were added so people shouldn't
have to look at the TRM to find what each constant number meant. But
now using the macros this is not needed anymore, so I don't think is
necessary to keep that on the comments.

Best regards,
Javier


From lee.jones at linaro.org  Fri May 31 11:09:06 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 16:09:06 +0100
Subject: [PATCH] ARM: ux500: Enable HIGHMEM in the u8540 defconfig
Message-ID: <1370012946-7374-1-git-send-email-lee.jones@linaro.org>

In order to utilise all of the memory located on ux500 based devices
we have to enable HIGHMEM. Without it the kernel truncates memory down
to what's left after the PAGE_OFFSET has been applied, which doesn't
leave an awful lot, especially if we're running large rootfs' such
as full Linux desktop distributions or Android.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/configs/u8500_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d322d2..38d633a 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -1,3 +1,4 @@
+CONFIG_HIGHMEM=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
-- 
1.7.10.4



From arnd at arndb.de  Fri May 31 11:11:59 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:11:59 +0200
Subject: [PATCH 1/2] ARM: shmobile: sdhi: pass DMA filter from platform
 code
In-Reply-To: <alpine.DEB.2.00.1305311611460.7395@axis700.grange>
References: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
 <alpine.DEB.2.00.1305311611460.7395@axis700.grange>
Message-ID: <2862988.jnTv0iSQcj@wuerfel>

On Friday 31 May 2013 16:52:13 Guennadi Liakhovetski wrote:
> 
> Thanks for the patches. How about this fix:
> 
> http://thread.gmane.org/gmane.linux.kernel.mmc/20619
> 
> I think it's a better fix. SHDMA users cannot use other DMA drivers, so, I 
> don't think we need to pass the filter via the platform data.

I think it's more a matter of using the API correctly. The dmaengine
API is an abstraction to separate the slave driver from the master
through well-defined calls. If you make additional assumptions
in the slave driver about the master, that is a layering violation.

	Arnd


From festevam at gmail.com  Fri May 31 11:12:26 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 31 May 2013 12:12:26 -0300
Subject: [PATCHv2 1/3] arm: introduce config HAS_BANDGAP
In-Reply-To: <1368629928-6723-2-git-send-email-eduardo.valentin@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-2-git-send-email-eduardo.valentin@ti.com>
Message-ID: <CAOMZO5CL=apxbkCHA6Xsw+m5d-rhe_VcOaA9KpkSmiJ=ZRL7gA@mail.gmail.com>

On Wed, May 15, 2013 at 11:58 AM, Eduardo Valentin
<eduardo.valentin at ti.com> wrote:
> Introduce HAS_BANDGAP config entry. This config is a
> boolean value so that arch code can flag is they
> feature a bandgap device.
>
> This config entry follows the same idea behind
> ARCH_HAS_CPUFREQ.

It would be nice if you explain what BANDGAP means here, since you
introduce this option in this patch.


From plagnioj at jcrosoft.com  Fri May 31 11:08:33 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 May 2013 17:08:33 +0200
Subject: [PATCH 1/2] spi: atmel: convert to
 dma_request_slave_channel_compat()
In-Reply-To: <1370012520-30539-1-git-send-email-richard.genoud@gmail.com>
References: <1370012520-30539-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <20130531150833.GF23653@game.jcrosoft.org>

On 17:01 Fri 31 May     , Richard Genoud wrote:
> Use generic DMA DT helper.
> Platforms booting with or without DT populated are both supported.
> 
> Based on Ludovic Desroches <ludovic.desroches at atmel.com> patchset
> "ARM: at91: move to generic DMA device tree binding"
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Ludo please take a look but this looks ok to me

Best Regards,
J.
> ---
>  drivers/spi/spi-atmel.c |   42 +++++++++++++++++++++++++++---------------
>  1 file changed, 27 insertions(+), 15 deletions(-)
> 
> rebased on linux-next next-20130531
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 31cfc87..ea1ec00 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -424,10 +424,15 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as,
>  	return err;
>  }
>  
> -static bool filter(struct dma_chan *chan, void *slave)
> +static bool filter(struct dma_chan *chan, void *pdata)
>  {
> -	struct	at_dma_slave *sl = slave;
> +	struct atmel_spi_dma *sl_pdata = pdata;
> +	struct at_dma_slave *sl;
>  
> +	if (!sl_pdata)
> +		return false;
> +
> +	sl = &sl_pdata->dma_slave;
>  	if (sl->dma_dev == chan->device->dev) {
>  		chan->private = sl;
>  		return true;
> @@ -438,24 +443,31 @@ static bool filter(struct dma_chan *chan, void *slave)
>  
>  static int atmel_spi_configure_dma(struct atmel_spi *as)
>  {
> -	struct at_dma_slave *sdata = &as->dma.dma_slave;
>  	struct dma_slave_config	slave_config;
> +	struct device *dev = &as->pdev->dev;
>  	int err;
>  
> -	if (sdata && sdata->dma_dev) {
> -		dma_cap_mask_t mask;
> +	dma_cap_mask_t mask;
> +	dma_cap_zero(mask);
> +	dma_cap_set(DMA_SLAVE, mask);
>  
> -		/* Try to grab two DMA channels */
> -		dma_cap_zero(mask);
> -		dma_cap_set(DMA_SLAVE, mask);
> -		as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
> -		if (as->dma.chan_tx)
> -			as->dma.chan_rx =
> -				dma_request_channel(mask, filter, sdata);
> +	as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
> +							   &as->dma,
> +							   dev, "tx");
> +	if (!as->dma.chan_tx) {
> +		dev_err(dev,
> +			"DMA TX channel not available, SPI unable to use DMA\n");
> +		err = -EBUSY;
> +		goto error;
>  	}
> -	if (!as->dma.chan_rx || !as->dma.chan_tx) {
> -		dev_err(&as->pdev->dev,
> -			"DMA channel not available, SPI unable to use DMA\n");
> +
> +	as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
> +							   &as->dma,
> +							   dev, "rx");
> +
> +	if (!as->dma.chan_rx) {
> +		dev_err(dev,
> +			"DMA RX channel not available, SPI unable to use DMA\n");
>  		err = -EBUSY;
>  		goto error;
>  	}
> -- 
> 1.7.10.4
> 


From plagnioj at jcrosoft.com  Fri May 31 11:11:25 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 May 2013 17:11:25 +0200
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA
 DT binding
In-Reply-To: <51A86DF5.4010808@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
 <51A77F10.8020808@atmel.com>
 <20130530163936.GC23653@game.jcrosoft.org>
 <20130531091627.GD11384@ludovic.desroches@atmel.com>
 <51A86DF5.4010808@atmel.com>
Message-ID: <20130531151125.GG23653@game.jcrosoft.org>

On 11:31 Fri 31 May     , Nicolas Ferre wrote:
> On 31/05/2013 11:16, Ludovic Desroches :
> >On Thu, May 30, 2013 at 06:39:36PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>On 18:32 Thu 30 May     , Nicolas Ferre wrote:
> >>>On 30/05/2013 18:08, ludovic.desroches at atmel.com :
> >>>>From: Ludovic Desroches <ludovic.desroches at atmel.com>
> >>>>
> >>>>For most devices the FIFO configuration is the same i.e. when half FIFO size is
> >>>>available/filled, a source/destination request is serviced. But USART devices
> >>>>have to do it when there is enough space/data available to perform a single
> >>>>AHB access so the ASAP configuration.
> >>>>
> >>>>Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >>>>Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> >>>
> >>>Clear and neat: thanks Ludo.
> >>
> >>agreed
> >>
> >>can we apply this via AT91 as this depends on some cleanup I did on DT and
> >>could result on some nigthmware conflict
> >>
> >
> >In fact, I am not sure it's the best solution. I have noticed that there is a
> >conflict with a patch sent by Nicolas (dmaengine: at_hdmac: extend hardware
> >handshaking interface identification) which is already in Vinod's tree but
> >which is not present on Jean-Christophe's cleanup tree on which I based these
> >patches.
> >
> >Moreover this patch doesn't use macros introduced by Nicolas' patch. I may
> >update it and it should go through Vinod's tree with a dependence on patch 1/3.
> >
> >What's your point of view?
> 
> Indeed. Another option could be to push patches 1 and 3 in
> dmaengine's tree and make the 2nd patch go through arm-soc with a
> dependency on slave-dma GIT tree (it seems it is an usual patern).
> 
> Arnd, Jean-Christophe, what do you think?

Nico I let you handle this one my only concern is that the cleanup work can
cause nightware conflict

Best Regards,
J.
> 
> Bye,
> -- 
> Nicolas Ferre


From lee.jones at linaro.org  Fri May 31 11:15:51 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 16:15:51 +0100
Subject: [PATCH v2] ARM: ux500: Allocate correct amount of memory for the
 u8540 in DT
Message-ID: <1370013351-7960-1-git-send-email-lee.jones@linaro.org>

As it stands, the memory node in the u8540 Device Tree is ignored and
memory is actually stipulated by the bootloader via ATAGS. ARM core
architecture code then extracts the memory ATAG and inserts it into the
Device Tree. In the u8540 the LittleKernel bootloader only stipulates
512MB of memory; however, the u8540 actually has 2GB. We're taking the
responsibility to register the remainder from Device Tree here.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/ccu8540.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
index 12f0bc2..5603764 100644
--- a/arch/arm/boot/dts/ccu8540.dts
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -16,8 +16,8 @@
 	model = "ST-Ericsson U8540 platform with Device Tree";
 	compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
 
-	memory {
-		reg = <0x00000000 0x20000000>;
+	memory at 0 {
+		reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
 	};
 
 	soc {
-- 
1.7.10.4



From lee.jones at linaro.org  Fri May 31 11:18:50 2013
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 May 2013 16:18:50 +0100
Subject: [PATCH 2/2] ARM: ux500: Enable HIGHMEM in the u8540 defconfig
In-Reply-To: <38058740.G1EqTG95pA@wuerfel>
References: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>
 <1370010272-25520-2-git-send-email-lee.jones@linaro.org>
 <38058740.G1EqTG95pA@wuerfel>
Message-ID: <20130531151850.GC12488@gmail.com>

On Fri, 31 May 2013, Arnd Bergmann wrote:

> On Friday 31 May 2013 15:24:32 Lee Jones wrote:
> > In order to utilise all of the memory located on ux500 based devices
> > we have to enable HIGHMEM. Without it the kernel truncates memory down
> > to what's left after the PAGE_OFFSET has been applied, which doesn't
> > leave an awful lot, especially if we're running large rootfs' such
> > as full Linux desktop distributions or Android.
> > 
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> How much memory do those devices have? Enabling HIGHMEM is quite expensive.

Another 1GB.

> > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > index 5439925..808be06 100644
> > --- a/drivers/of/fdt.c
> > +++ b/drivers/of/fdt.c
> 
> You should probably resend the patch without the second half that got
> in it by accident.

I did already, thanks.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From dmurphy at ti.com  Fri May 31 11:19:44 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 10:19:44 -0500
Subject: [PATCH v8] ARM: dts: omap4-panda: Update the LED support for
 the panda DTS
In-Reply-To: <CABxcv=mCh38XgFoRSrZ8BK5U5EFDb-1Fb70FoLyNqb0V3WQm-g@mail.gmail.com>
References: <1370011682-20675-1-git-send-email-dmurphy@ti.com>
 <CABxcv=mCh38XgFoRSrZ8BK5U5EFDb-1Fb70FoLyNqb0V3WQm-g@mail.gmail.com>
Message-ID: <51A8BF90.4060509@ti.com>

On 05/31/2013 10:05 AM, Javier Martinez Canillas wrote:
> On Fri, May 31, 2013 at 4:48 PM, Dan Murphy <dmurphy at ti.com> wrote:
>> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
>> are different.
>>
>> A1-A3 = gpio_wk7
>> ES = gpio_110
>>
>> There is no change to LED D2
>>
>> Abstract away the pinmux and the LED definitions for the two boards into
>> the respective DTS files.
>>
>> Signed-off-by: Dan Murphy <dmurphy at ti.com>
>> ---
>> v8 - Rebase to latest and use pinctrl macros - https://patchwork.kernel.org/patch/2629351/
>> v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
>> v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
>> v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/
>>
>>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>>  arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>>  2 files changed, 43 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> index d5d144a..523a800 100644
>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> @@ -16,8 +16,13 @@
>>                 reg = <0x80000000 0x40000000>; /* 1 GB */
>>         };
>>
>> -       leds {
>> +       leds: leds {
>>                 compatible = "gpio-leds";
>> +               pinctrl-names = "default";
>> +               pinctrl-0 = <
>> +                       &led_wkgpio_pins
>> +               >;
>> +
>>                 heartbeat {
>>                         label = "pandaboard::status1";
>>                         gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
>> @@ -157,6 +162,15 @@
>>         };
>>  };
>>
>> +&omap4_pmx_wkup {
>> +       led_wkgpio_pins: pinmux_leds_wkpins {
>> +               pinctrl-single,pins = <
>> +                       0x1a (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk7 OUTPUT | MODE 3 */
>> +                       0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 OUTPUT | MODE 3 */
> Hello Dan,
>
> The OUTPUT | MODE 3 in the comments were added so people shouldn't
> have to look at the TRM to find what each constant number meant. But
> now using the macros this is not needed anymore, so I don't think is
> necessary to keep that on the comments.
>
> Best regards,
> Javier
Yes you are correct sending update to remove the comments

-- 
------------------
Dan Murphy



From dmurphy at ti.com  Fri May 31 11:19:51 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 10:19:51 -0500
Subject: [PATCH v9] ARM: dts: omap4-panda: Update the LED support for the
 panda DTS
Message-ID: <1370013591-25957-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
v9 - Removed comments for mux config - https://patchwork.kernel.org/patch/2644391/
v8 - Rebase to latest and use pinctrl macros - https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/
 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..800fa4e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <
+			&led_wkgpio_pins
+		>;
+
 		heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
@@ -157,6 +162,15 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk7 */
+			0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..0a7812f 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
 		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
+
+&omap4_pmx_core {
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 (PIN_OUTPUT | MUX_MODE3)	/* gpio_110 */
+		>;
+	};
+};
+
+&led_wkgpio_pins {
+	pinctrl-single,pins = <
+		0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 */
+	>;
+};
+
+&leds {
+	pinctrl-0 = <
+		&led_gpio_pins
+		&led_wkgpio_pins
+	>;
+
+	heartbeat {
+		gpios = <&gpio4 14 0>;
+	};
+	mmc {
+		gpios = <&gpio1 8 0>;
+	};
+};
-- 
1.7.5.4



From stefano.stabellini at eu.citrix.com  Fri May 31 11:20:02 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 31 May 2013 16:20:02 +0100
Subject: [PATCH RFC 1/6] [HACK!] arm64/xen: create links to arch/arm
 include files and Xen code
In-Reply-To: <20130531131038.GA15551@arm.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531103617.GA18045@localhost.cambridge.arm.com>
 <alpine.DEB.2.02.1305311259090.4799@kaball.uk.xensource.com>
 <20130531131038.GA15551@arm.com>
Message-ID: <alpine.DEB.2.02.1305311446360.4799@kaball.uk.xensource.com>

On Fri, 31 May 2013, Catalin Marinas wrote:
> On Fri, May 31, 2013 at 01:02:04PM +0100, Stefano Stabellini wrote:
> > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > On Thu, May 30, 2013 at 05:18:28PM +0100, Stefano Stabellini wrote:
> > > > Most of Xen support for ARM is common between ARMv7 and ARMv8.
> > > > Create links to the code under arch/arm (bleah).
> > > > 
> > > > Other, probably better alternatives:
> > > > 
> > > > - move the code to a different location, maybe the header files to
> > > > include/xen/arm and the code to drivers/xen/arm (still pretty ugly)?
> > > > 
> > > > - create a copy of the code to arch/arm64 (even worse);
> > > 
> > > KVM handles this in the Makefile by referencing back to arch/arm or even
> > > the generic kvm directory. I think that's the 'cleanest' ;)
> > 
> > Do you mean creating links in the Makefile or generating header file
> > copies from the Makefile?
> > Or do you mean using something like "-I arch/arm/include/asm/xen" in the
> > arch/arm64 Makefile?
> 
> I meant C files being compiled directly from arch/arm (no links).

OK.


> For headers, if they are specific to arm or arm64, just copy the header
> in each place (e.g. not using regs->pstate in the arch/arm code with
> #ifdef's). For the rest, if they cannot be made generic, one way is to
> have a dummy file including the arm equivalent:
> 
> #include <../../arm/include/asm/xen/events.h>
> 
> Passing -I is dangerous as you actually need "-I arch/arm/include" which
> could bring other files.

Thanks, that is a good idea, I'll do that.


From stefano.stabellini at eu.citrix.com  Fri May 31 11:23:20 2013
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Fri, 31 May 2013 16:23:20 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <alpine.DEB.2.02.1305311530440.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531105915.GC18045@localhost.cambridge.arm.com>
 <alpine.DEB.2.02.1305311419280.4799@kaball.uk.xensource.com>
 <20130531141601.GC15551@arm.com>
 <alpine.DEB.2.02.1305311530440.4799@kaball.uk.xensource.com>
Message-ID: <alpine.DEB.2.02.1305311622150.4799@kaball.uk.xensource.com>

On Fri, 31 May 2013, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Catalin Marinas wrote:
> > On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> > > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > > > --- a/arch/arm/include/asm/xen/page.h
> > > > > +++ b/arch/arm/include/asm/xen/page.h
> > > > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > > > >  	return __set_phys_to_machine(pfn, mfn);
> > > > >  }
> > > > >  
> > > > > +#ifdef CONFIG_ARM64
> > > > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > > > +#else
> > > > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > > > +#endif
> > > > 
> > > > Now I saw the ARM-specific part. Can you not use something like
> > > > ioremap_cached() which would give normal cacheable memory (at least on
> > > > ARMv7).
> > > 
> > > No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> > > needs to be MT_MEMORY. It is used for normal memory pages, not device
> > > memory.
> > 
> > MT_DEVICE_CACHED is Normal memory for ARMv7.
> 
> I didn't realize that MT_DEVICE_CACHED and MT_MEMORY end up having the
> same AttrIndx encoding!
> In that case yes, I should be able to use it.
> I take that I should just implement ioremap_cached on arm64 as well?
> 

Should just use MT_MEMORY and call it PROT_NORMAL?

#define PROT_NORMAL     (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
#define ioremap_cached(addr, size)     __ioremap((addr), (size), __pgprot(PROT_NORMAL))


From Catalin.Marinas at arm.com  Fri May 31 11:25:39 2013
From: Catalin.Marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 16:25:39 +0100
Subject: [GIT PULL] arm64 fixes for 3.10
Message-ID: <20130531152539.GE15551@arm.com>

Hi Linus,

Please pull the arm64 patches below. Thanks.

The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:

  Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git tags/arm64-stable

for you to fetch changes up to 9955ac47f4ba1c95ecb6092aeaefb40a22e99268:

  arm64: don't kill the kernel on a bad esr from el0 (2013-05-31 16:04:51 +0100)

----------------------------------------------------------------
- Module compilation issues (symbol not exported).
- Plug a hole where user space can bring the kernel down.

----------------------------------------------------------------
Catalin Marinas (1):
      arm64: Do not report user faults for handled signals

Chen Gang (1):
      arm64: kernel: compiling issue, need 'EXPORT_SYMBOL(clear_page)'

Mark Rutland (2):
      arm64: treat unhandled compat el0 traps as undef
      arm64: don't kill the kernel on a bad esr from el0

 arch/arm64/kernel/arm64ksyms.c |  1 +
 arch/arm64/kernel/entry.S      | 10 ++++++++++
 arch/arm64/kernel/traps.c      | 17 ++++++++++++-----
 arch/arm64/mm/fault.c          |  3 ++-
 4 files changed, 25 insertions(+), 6 deletions(-)


From plagnioj at jcrosoft.com  Fri May 31 11:24:05 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 May 2013 17:24:05 +0200
Subject: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
In-Reply-To: <5194D123.4060403@ti.com>
References: <1368629928-6723-1-git-send-email-eduardo.valentin@ti.com>
 <1368629928-6723-4-git-send-email-eduardo.valentin@ti.com>
 <5193A875.1020000@ti.com> <5193B9AA.7020507@ti.com>
 <20130515165726.GK22508@game.jcrosoft.org>
 <5194D123.4060403@ti.com>
Message-ID: <20130531152405.GH23653@game.jcrosoft.org>

On 08:29 Thu 16 May     , Eduardo Valentin wrote:
> On 15-05-2013 12:57, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 12:36 Wed 15 May     , Eduardo Valentin wrote:
> >> On 15-05-2013 11:23, Benoit Cousson wrote:
> >>> Hi Eduardo,
> >>>
> >>> On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
> >>>> Include bandgap devices for OMAP4460 devices.
> >>>>
> >>>> Cc: "Beno?t Cousson" <b-cousson at ti.com>
> >>>> Cc: Tony Lindgren <tony at atomide.com>
> >>>> Cc: Russell King <linux at arm.linux.org.uk>
> >>>> Cc: linux-omap at vger.kernel.org
> >>>> Cc: devicetree-discuss at lists.ozlabs.org
> >>>> Cc: linux-arm-kernel at lists.infradead.org
> >>>> Cc: linux-kernel at vger.kernel.org
> >>>> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
> >>>> ---
> >>>>  arch/arm/boot/dts/omap4460.dtsi | 9 +++++++++
> >>>>  1 file changed, 9 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
> >>>> index 2cf227c..e5bfbfe 100644
> >>>> --- a/arch/arm/boot/dts/omap4460.dtsi
> >>>> +++ b/arch/arm/boot/dts/omap4460.dtsi
> >>>> @@ -29,4 +29,13 @@
> >>>>  			     <0 55 0x4>;
> >>>>  		ti,hwmods = "debugss";
> >>>>  	};
> >>>> +
> >>>> +	bandgap {
> >>>> +		reg = <0x4a002260 0x4
> >>>> +			0x4a00232C 0x4
> >>>> +			0x4a002378 0x18>;
> >>>> +		compatible = "ti,omap4460-bandgap";
> >>>> +		interrupts = <0 126 4>; /* talert */
> >>>> +		ti,tshut-gpio = <86>;
> >>
> >>
> >>
> >>>
> >>> Why do you need a custom attribute for GPIO? Cannot you use the standard
> >>> one?
> >>
> >> I believe it was by your suggestion :-), during the first attempts to
> >> send this driver. But could not find the thread link :-( sorry.
> >>
> >>
> >> I guess the reasoning to mark it as a ti specific is because it will be
> >> used as IRQ line to treat thermal shutdown (in SW).
> > so use interrup-parent
> 
> 
> Jean-Christophe,
> 
> That will change the controller and break the configuration for the
> other IRQ line, coming from GIC.

put this on hold I'm preparing a fix for this
I've discuss with Grant already.

This way for me is buggy

Best Regards,
J.
> 
> >>
> >>>
> >>> Where is the gpio controller phandle?
> >>>
> >>> Usually it looks like this:
> >>>
> >>> 	gpios = <&gpio1 8 0>;
> >>>
> >>>
> >>> Regards,
> >>> Benoit
> >>>
> >>>
> >>>
> >>
> >>
> > 
> > 
> > 
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel at lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> > 
> > 
> 
> 




From florian.vaussard at epfl.ch  Fri May 31 11:28:14 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 17:28:14 +0200
Subject: [PATCH v9] ARM: dts: omap4-panda: Update the LED support for
 the panda DTS
In-Reply-To: <1370013591-25957-1-git-send-email-dmurphy@ti.com>
References: <1370013591-25957-1-git-send-email-dmurphy@ti.com>
Message-ID: <51A8C18E.7020800@epfl.ch>

Hello Dan,

On 05/31/2013 05:19 PM, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
>
> A1-A3 = gpio_wk7
> ES = gpio_110
>
> There is no change to LED D2
>
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
>
> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> ---
> v9 - Removed comments for mux config - https://patchwork.kernel.org/patch/2644391/
> v8 - Rebase to latest and use pinctrl macros - https://patchwork.kernel.org/patch/2629351/
> v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
> v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
> v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/
>   arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
>   arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
>   2 files changed, 43 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index d5d144a..800fa4e 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -16,8 +16,13 @@
>   		reg = <0x80000000 0x40000000>; /* 1 GB */
>   	};
>
> -	leds {
> +	leds: leds {
>   		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <
> +			&led_wkgpio_pins
> +		>;
> +
>   		heartbeat {
>   			label = "pandaboard::status1";
>   			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> @@ -157,6 +162,15 @@
>   	};
>   };
>
> +&omap4_pmx_wkup {
> +	led_wkgpio_pins: pinmux_leds_wkpins {
> +		pinctrl-single,pins = <
> +			0x1a (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk7 */
> +			0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 */
> +		>;
> +	};
> +};
> +
>   &i2c1 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&i2c1_pins>;
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index 5cfdf19..0a7812f 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,31 @@
>   		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
>   		>;
>   };
> +
> +&omap4_pmx_core {
> +	led_gpio_pins: gpio_led_pmx {
> +		pinctrl-single,pins = <
> +			0xb6 (PIN_OUTPUT | MUX_MODE3)	/* gpio_110 */
> +		>;
> +	};
> +};
> +
> +&led_wkgpio_pins {
> +	pinctrl-single,pins = <
> +		0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 */
> +	>;
> +};
> +
> +&leds {
> +	pinctrl-0 = <
> +		&led_gpio_pins
> +		&led_wkgpio_pins
> +	>;
> +
> +	heartbeat {
> +		gpios = <&gpio4 14 0>;

And here you could use the GPIO defines:

		gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;

> +	};
> +	mmc {
> +		gpios = <&gpio1 8 0>;

Same here.

> +	};
> +};
>

Regards,

Florian


From g.liakhovetski at gmx.de  Fri May 31 11:30:01 2013
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 31 May 2013 17:30:01 +0200 (CEST)
Subject: [PATCH 1/2] ARM: shmobile: sdhi: pass DMA filter from platform
 code
In-Reply-To: <2862988.jnTv0iSQcj@wuerfel>
References: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
 <alpine.DEB.2.00.1305311611460.7395@axis700.grange>
 <2862988.jnTv0iSQcj@wuerfel>
Message-ID: <alpine.DEB.2.00.1305311721160.7395@axis700.grange>

On Fri, 31 May 2013, Arnd Bergmann wrote:

> On Friday 31 May 2013 16:52:13 Guennadi Liakhovetski wrote:
> > 
> > Thanks for the patches. How about this fix:
> > 
> > http://thread.gmane.org/gmane.linux.kernel.mmc/20619
> > 
> > I think it's a better fix. SHDMA users cannot use other DMA drivers, so, I 
> > don't think we need to pass the filter via the platform data.
> 
> I think it's more a matter of using the API correctly. The dmaengine
> API is an abstraction to separate the slave driver from the master
> through well-defined calls. If you make additional assumptions
> in the slave driver about the master, that is a layering violation.

I think it is a common practice, see e.g.

drivers/mmc/host/omap_hsmmc.c
drivers/mmc/host/davinci_mmc.c

And what do you do for DT-based platforms?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From arnd at arndb.de  Fri May 31 11:36:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:36:44 +0200
Subject: [PATCH 2/2] ARM: ux500: Enable HIGHMEM in the u8540 defconfig
In-Reply-To: <20130531151850.GC12488@gmail.com>
References: <1370010272-25520-1-git-send-email-lee.jones@linaro.org>
 <38058740.G1EqTG95pA@wuerfel> <20130531151850.GC12488@gmail.com>
Message-ID: <1902994.0Kq6C7Rx1R@wuerfel>

On Friday 31 May 2013 16:18:50 Lee Jones wrote:
> On Fri, 31 May 2013, Arnd Bergmann wrote:
> 
> > On Friday 31 May 2013 15:24:32 Lee Jones wrote:
> > > In order to utilise all of the memory located on ux500 based devices
> > > we have to enable HIGHMEM. Without it the kernel truncates memory down
> > > to what's left after the PAGE_OFFSET has been applied, which doesn't
> > > leave an awful lot, especially if we're running large rootfs' such
> > > as full Linux desktop distributions or Android.
> > > 
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > 
> > How much memory do those devices have? Enabling HIGHMEM is quite expensive.
> 
> Another 1GB.

You mean you have 2GB total or 1.75GB?  You could just use
CONFIG_VMSPLIT_2G to an extra GB compared to the default, which
is what vexpress, imx and s5p already do, but you still have to
put the vmalloc area in the low 2GB then.

	Arnd


From csd at broadcom.com  Fri May 31 11:41:40 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 31 May 2013 08:41:40 -0700
Subject: [PATCH V4 1/3] mmc: sdhci: Add size for caller in
 init+register
In-Reply-To: <1369860607-25572-1-git-send-email-csd@broadcom.com>
References: <1369860607-25572-1-git-send-email-csd@broadcom.com>
Message-ID: <51A8C4B4.6020104@broadcom.com>

Hi Chris,
  Can you pls take this patch and the one named "[PATCH V4 2/3] ARM: 
mmc: bcm281xx SDHCI driver" into your tree ?

  Thanks,
     csd.

On 13-05-29 01:50 PM, Christian Daudt wrote:
> Add a param to allow users of sdhci_pltfm to allocate private space
> in calls to sdhci_pltfm_init+sdhci_pltfm_register. This is implemented
> in the same way as sdhci does for its users.
>   None of the users have been migrated yet and are passing in zero to
> retain their private allocation.
>
> - todo: migrate clients to using allocation this way
> - todo: remove priv variable once migration is complete
>
> Also removed unused variable in sdhci_pltfm_init fn
>
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Reviewed-by: Ulf Hansson <ulf.hansson at linaro.org>




From dmurphy at ti.com  Fri May 31 11:44:55 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 10:44:55 -0500
Subject: [PATCH v10 1/2] ARM: dts: omap4-panda: Update the LED support for the
 panda DTS
Message-ID: <1370015095-26746-1-git-send-email-dmurphy@ti.com>

The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.

A1-A3 = gpio_wk7
ES = gpio_110

There is no change to LED D2

Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
v10 - Update gpio entries to use gpio macros - https://patchwork.kernel.org/patch/2644561/ 
v9 - Removed comments for mux config - https://patchwork.kernel.org/patch/2644391/
v8 - Rebase to latest and use pinctrl macros - https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver - https://patchwork.kernel.org/patch/2573981/
 arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++++++++++++++-
 arch/arm/boot/dts/omap4-panda-es.dts      |   28 ++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..800fa4e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <
+			&led_wkgpio_pins
+		>;
+
 		heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
@@ -157,6 +162,15 @@
 	};
 };
 
+&omap4_pmx_wkup {
+	led_wkgpio_pins: pinmux_leds_wkpins {
+		pinctrl-single,pins = <
+			0x1a (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk7 */
+			0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 */
+		>;
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..56c4354 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
 		0x5e (PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
 };
+
+&omap4_pmx_core {
+	led_gpio_pins: gpio_led_pmx {
+		pinctrl-single,pins = <
+			0xb6 (PIN_OUTPUT | MUX_MODE3)	/* gpio_110 */
+		>;
+	};
+};
+
+&led_wkgpio_pins {
+	pinctrl-single,pins = <
+		0x1c (PIN_OUTPUT | MUX_MODE3)	/* gpio_wk8 */
+	>;
+};
+
+&leds {
+	pinctrl-0 = <
+		&led_gpio_pins
+		&led_wkgpio_pins
+	>;
+
+	heartbeat {
+		gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+	};
+	mmc {
+		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+	};
+};
-- 
1.7.5.4



From dmurphy at ti.com  Fri May 31 11:45:22 2013
From: dmurphy at ti.com (Dan Murphy)
Date: Fri, 31 May 2013 10:45:22 -0500
Subject: [PATCH v1] ARM: dts: omap4-panda: Update the twl6040 gpio to macro
 definition
Message-ID: <1370015122-26792-1-git-send-email-dmurphy@ti.com>

Update the dt property ti,audpwron-gpio to use the
gpio macro definition for GPIO_ACTIVE_HIGH.

Signed-off-by: Dan Murphy <dmurphy at ti.com>
---
 arch/arm/boot/dts/omap4-panda-common.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 800fa4e..00cbaa5 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -190,7 +190,7 @@
 		/* IRQ# = 119 */
 		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
 		interrupt-parent = <&gic>;
-		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+		ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
 
 		vio-supply = <&v1v8>;
 		v2v1-supply = <&v2v1>;
-- 
1.7.5.4



From arnd at arndb.de  Fri May 31 11:49:28 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:49:28 +0200
Subject: [PATCH] ARM: nomadik: fix clocksource warning
Message-ID: <41518453.ApMFpK6n11@wuerfel>

The clocksource API has changed slightly, which causes a harmless
warning:

/git/arm-soc/drivers/clocksource/nomadik-mtu.c:259:28: warning: 'nmdk_timer_match' defined but not used [-Wunused-variable]
 static struct of_device_id nmdk_timer_match[] __initconst = {
                            ^

Fortunately, the same API change also lets us simplify the code
while removing the warning.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>

---

I've applied this patch on top of next/dt to remove the warning introduced
by Linus' patch.

diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index 7982cb0..b9415b6 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -256,23 +256,13 @@ void __init nmdk_timer_init(void __iomem *base, int irq)
 	__nmdk_timer_init(base, irq, pclk0, clk0);
 }
 
-static struct of_device_id nmdk_timer_match[] __initconst = {
-	{ .compatible = "st,nomadik-mtu" },
-	{}
-};
-
-static void __init nmdk_timer_of_init(void)
+static void __init nmdk_timer_of_init(struct device_node *node)
 {
-	struct device_node *node;
 	struct clk *pclk;
 	struct clk *clk;
 	void __iomem *base;
 	int irq;
 
-	node = of_find_matching_node(NULL, nmdk_timer_match);
-	if (!node)
-		panic("No timer node");
-
 	base = of_iomap(node, 0);
 	if (!base)
 		panic("Can't remap registers");



From arnd at arndb.de  Fri May 31 11:54:39 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:54:39 +0200
Subject: warning introduced in "DMA: AT91: Get residual bytes in dma buffer"
Message-ID: <5527092.NRqFJAfgoB@wuerfel>

Patch 7c407d3e "DMA: AT91: Get residual bytes in dma buffer" 
causes a build warning 

/git/arm-soc/drivers/dma/at_hdmac.c:424:13: warning: 'atc_cleanup_descriptors' defined but not used [-Wunused-function]
 static void atc_cleanup_descriptors(struct at_dma_chan *atchan)
             ^

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---

This may not be the right solution, but it should get fixed
in linux-next in some way.

Elen, please address this appropriately.

	Arnd

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 6db5228..09929c8 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -421,7 +421,7 @@ static void atc_complete_all(struct at_dma_chan *atchan)
  *
  * Called with atchan->lock held and bh disabled
  */
-static void atc_cleanup_descriptors(struct at_dma_chan *atchan)
+static void __maybe_unused atc_cleanup_descriptors(struct at_dma_chan *atchan)
 {
 	struct at_desc	*desc, *_desc;
 	struct at_desc	*child;



From catalin.marinas at arm.com  Fri May 31 11:56:13 2013
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 31 May 2013 16:56:13 +0100
Subject: [PATCH RFC 5/6] arm64/xen: implement xen_remap on arm64
In-Reply-To: <alpine.DEB.2.02.1305311622150.4799@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1305301705500.4799@kaball.uk.xensource.com>
 <1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com>
 <20130531105915.GC18045@localhost.cambridge.arm.com>
 <alpine.DEB.2.02.1305311419280.4799@kaball.uk.xensource.com>
 <20130531141601.GC15551@arm.com>
 <alpine.DEB.2.02.1305311530440.4799@kaball.uk.xensource.com>
 <alpine.DEB.2.02.1305311622150.4799@kaball.uk.xensource.com>
Message-ID: <20130531155613.GF15551@arm.com>

On Fri, May 31, 2013 at 04:23:20PM +0100, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Stefano Stabellini wrote:
> > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> > > > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > > > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > > > > --- a/arch/arm/include/asm/xen/page.h
> > > > > > +++ b/arch/arm/include/asm/xen/page.h
> > > > > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > > > > >  	return __set_phys_to_machine(pfn, mfn);
> > > > > >  }
> > > > > >  
> > > > > > +#ifdef CONFIG_ARM64
> > > > > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > > > > +#else
> > > > > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > > > > +#endif
> > > > > 
> > > > > Now I saw the ARM-specific part. Can you not use something like
> > > > > ioremap_cached() which would give normal cacheable memory (at least on
> > > > > ARMv7).
> > > > 
> > > > No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> > > > needs to be MT_MEMORY. It is used for normal memory pages, not device
> > > > memory.
> > > 
> > > MT_DEVICE_CACHED is Normal memory for ARMv7.
> > 
> > I didn't realize that MT_DEVICE_CACHED and MT_MEMORY end up having the
> > same AttrIndx encoding!
> > In that case yes, I should be able to use it.
> > I take that I should just implement ioremap_cached on arm64 as well?
> > 
> 
> Should just use MT_MEMORY and call it PROT_NORMAL?
> 
> #define PROT_NORMAL     (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
> #define ioremap_cached(addr, size)     __ioremap((addr), (size), __pgprot(PROT_NORMAL))

Looks fine.

-- 
Catalin


From arnd at arndb.de  Fri May 31 11:59:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 17:59:46 +0200
Subject: [PATCH] gpio/omap: omap_gpio_init_context stub must be inline
Message-ID: <2942784.trumtc2GjZ@wuerfel>

The bug fix 352a2d5bf "gpio/omap: ensure gpio context is initialised"
has caused a new warning for omap1_defconfig:

drivers/gpio/gpio-omap.c:1465:13: warning: 'omap_gpio_init_context' defined but not used [-Wunused-function]
 static void omap_gpio_init_context(struct gpio_bank *p) {}
             ^

The solution is to mark the stub function as 'static inline' so
it gets left out of the build when unused.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index d3f7d2d..e5fba65 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1462,7 +1462,7 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
 #else
 #define omap_gpio_runtime_suspend NULL
 #define omap_gpio_runtime_resume NULL
-static void omap_gpio_init_context(struct gpio_bank *p) {}
+static inline void omap_gpio_init_context(struct gpio_bank *p) {}
 #endif
 
 static const struct dev_pm_ops gpio_pm_ops = {



From arnd at arndb.de  Fri May 31 12:02:31 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 18:02:31 +0200
Subject: [PATCH 1/2] ARM: shmobile: sdhi: pass DMA filter from platform
 code
In-Reply-To: <alpine.DEB.2.00.1305311721160.7395@axis700.grange>
References: <1370008605-3745603-1-git-send-email-arnd@arndb.de>
 <2862988.jnTv0iSQcj@wuerfel>
 <alpine.DEB.2.00.1305311721160.7395@axis700.grange>
Message-ID: <3675801.kLfsmmiSOq@wuerfel>

On Friday 31 May 2013 17:30:01 Guennadi Liakhovetski wrote:
> On Fri, 31 May 2013, Arnd Bergmann wrote:
> > On Friday 31 May 2013 16:52:13 Guennadi Liakhovetski wrote:

> > I think it's more a matter of using the API correctly. The dmaengine
> > API is an abstraction to separate the slave driver from the master
> > through well-defined calls. If you make additional assumptions
> > in the slave driver about the master, that is a layering violation.
> 
> I think it is a common practice, see e.g.
> 
> drivers/mmc/host/omap_hsmmc.c
> drivers/mmc/host/davinci_mmc.c

Yes, those should be fixed as well.

> And what do you do for DT-based platforms?

Once the driver is DT-enabled, we no longer have to pass
a filter function at all because the slave id and all settings
will get pulled out of the DT using the dma engine's xlate()
callback.

	Arnd


From florian.vaussard at epfl.ch  Fri May 31 12:12:56 2013
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 May 2013 18:12:56 +0200
Subject: [PATCH v1] ARM: dts: omap4-panda: Update the twl6040 gpio to
 macro definition
In-Reply-To: <1370015122-26792-1-git-send-email-dmurphy@ti.com>
References: <1370015122-26792-1-git-send-email-dmurphy@ti.com>
Message-ID: <51A8CC08.6090305@epfl.ch>

Hello Dan,

On 05/31/2013 05:45 PM, Dan Murphy wrote:
> Update the dt property ti,audpwron-gpio to use the
> gpio macro definition for GPIO_ACTIVE_HIGH.
>
> Signed-off-by: Dan Murphy <dmurphy at ti.com>
> ---
>   arch/arm/boot/dts/omap4-panda-common.dtsi |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 800fa4e..00cbaa5 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -190,7 +190,7 @@
>   		/* IRQ# = 119 */
>   		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
>   		interrupt-parent = <&gic>;
> -		ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
> +		ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
>
>   		vio-supply = <&v1v8>;
>   		v2v1-supply = <&v2v1>;
>

I missed it during the conversion, thank you.

Reviewed-by: Florian Vaussard <florian.vaussard at epfl.ch>


From cjb at laptop.org  Fri May 31 12:15:55 2013
From: cjb at laptop.org (Chris Ball)
Date: Fri, 31 May 2013 12:15:55 -0400
Subject: [PATCH V4 2/3] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <1369860607-25572-2-git-send-email-csd@broadcom.com> (Christian
 Daudt's message of "Wed, 29 May 2013 13:50:06 -0700")
References: <1369860607-25572-1-git-send-email-csd@broadcom.com>
 <1369860607-25572-2-git-send-email-csd@broadcom.com>
Message-ID: <87d2s7ceh0.fsf@octavius.laptop.org>

Hi Christian,

On Wed, May 29 2013, Christian Daudt wrote:
> +	/* if device is eMMC, emulate card insert right here */
> +	if (kona_dev->non_removable) {
> +		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
> +		if (ret) {
> +			dev_err(dev,
> +				"unable to emulate card insertion\n");
> +			goto err_remove_host;
> +		}
> +	} else if (gpio_is_valid(kona_dev->cd_gpio)) {
> +		ret = devm_gpio_request(dev, kona_dev->cd_gpio, "sdio cd");
> +		if (ret < 0) {
> +			dev_err(mmc_dev(host->mmc),
> +				"Unable to request GPIO pin %d\n",
> +				kona_dev->cd_gpio);
> +			goto err_remove_host;
> +		}
> +
> +		gpio_direction_input(kona_dev->cd_gpio);
> +
> +		/* Set debounce for SD Card detect to maximum value (128ms)
> +		 *
> +		 * NOTE-1: If gpio_set_debounce() returns error we still
> +		 * continue with the default debounce value set. Another reason
> +		 * for doing this is that on rhea-ray boards the SD Detect GPIO
> +		 * is on GPIO Expander and gpio_set_debounce() will return error
> +		 * and if we return error from here, then probe() would fail and
> +		 * SD detection would always fail.
> +		 *
> +		 * NOTE-2: We also give a msleep() of the "debounce" time here
> +		 * so that we give enough time for the debounce to stabilize
> +		 * before we read the gpio value in gpio_get_value_cansleep().
> +		 */
> +		ret = gpio_set_debounce(kona_dev->cd_gpio,
> +				(SD_DETECT_GPIO_DEBOUNCE_128MS * 1000));
> +		if (ret < 0) {
> +			dev_err(mmc_dev(host->mmc),
> +				"%s: gpio set debounce failed."
> +				"default debounce value assumed\n", __func__);
> +		}
> +
> +		/* Sleep for 128ms to allow debounce to stabilize */
> +		msleep(SD_DETECT_GPIO_DEBOUNCE_128MS);
> +		/* request irq for cd_gpio after the gpio debounce is
> +		 * stabilized, otherwise, some bogus gpio interrupts might be
> +		 * triggered.
> +		 */
> +		irq = gpio_to_irq(kona_dev->cd_gpio);
> +		ret = devm_request_threaded_irq(dev,
> +				irq,
> +				NULL,
> +				sdhci_bcm_kona_pltfm_cd_interrupt,
> +				IRQF_TRIGGER_FALLING|
> +				IRQF_TRIGGER_RISING |
> +				IRQF_ONESHOT |
> +				IRQF_NO_SUSPEND, "sdio cd", host);
> +		if (ret) {
> +			dev_err(mmc_dev(host->mmc),
> +				"Failed irq %d request for gpio=%d ret=%d\n",
> +				gpio_to_irq(kona_dev->cd_gpio),
> +				kona_dev->cd_gpio, ret);
> +			goto err_remove_host;
> +		}
> +		if (gpio_is_valid(kona_dev->wp_gpio)) {
> +			ret = devm_gpio_request(dev,
> +				kona_dev->wp_gpio, "sdio wp");
> +			if (ret < 0) {
> +				dev_err(&pdev->dev,
> +					"Unable to request WP pin %d\n",
> +					kona_dev->wp_gpio);
> +				kona_dev->wp_gpio = -1;
> +			} else {
> +				gpio_direction_input(kona_dev->wp_gpio);
> +			}
> +		}

Could you investigate replacing this section of code with a call to
mmc_of_parse(), please?  It should be able to replace your parsing
and handling of bus-width, cd-gpios, wp-gpios, and non-removable
(other than the initialization quirks specific to your hardware).

I'd like to avoid every driver having its own DT parsing.
Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From nico at fluxnic.net  Fri May 31 12:48:56 2013
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 31 May 2013 12:48:56 -0400 (EDT)
Subject: A bug about system call on ARM
In-Reply-To: <20130531111305.GI4928@mudshark.cambridge.arm.com>
References: <35FD53F367049845BC99AC72306C23D1610991B85E@CNBJMBX05.corpusers.net>
 <CAFLxGvyy=73dGQqG8W6SXZah7WQZ4gJAeeHXN8opKaOuG-5yUQ@mail.gmail.com>
 <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
 <20130531084638.GB4928@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B874@CNBJMBX05.corpusers.net>
 <20130531111305.GI4928@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.03.1305311247280.30828@syhkavp.arg>

On Fri, 31 May 2013, Will Deacon wrote:

> Hard to tell without context. You can take a look at my git tree if you
> like (I fixed it up based on Nico's comment):
> 
>   https://git.kernel.org/cgit/linux/kernel/git/will/linux.git/commit/?h=misc-patches

If you like, you may add "Reviewed-by: Nicolas Pitre <nico at linaro.org>" 
to it.


Nicolas


From will.deacon at arm.com  Fri May 31 12:52:50 2013
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 31 May 2013 17:52:50 +0100
Subject: A bug about system call on ARM
In-Reply-To: <alpine.LFD.2.03.1305311247280.30828@syhkavp.arg>
References: <20130529094826.GD13095@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B865@CNBJMBX05.corpusers.net>
 <35FD53F367049845BC99AC72306C23D1610991B866@CNBJMBX05.corpusers.net>
 <20130530090949.GC7483@mudshark.cambridge.arm.com>
 <20130530114112.GH7483@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B86D@CNBJMBX05.corpusers.net>
 <20130531084638.GB4928@mudshark.cambridge.arm.com>
 <35FD53F367049845BC99AC72306C23D1610991B874@CNBJMBX05.corpusers.net>
 <20130531111305.GI4928@mudshark.cambridge.arm.com>
 <alpine.LFD.2.03.1305311247280.30828@syhkavp.arg>
Message-ID: <20130531165250.GU4928@mudshark.cambridge.arm.com>

On Fri, May 31, 2013 at 05:48:56PM +0100, Nicolas Pitre wrote:
> On Fri, 31 May 2013, Will Deacon wrote:
> 
> > Hard to tell without context. You can take a look at my git tree if you
> > like (I fixed it up based on Nico's comment):
> > 
> >   https://git.kernel.org/cgit/linux/kernel/git/will/linux.git/commit/?h=misc-patches
> 
> If you like, you may add "Reviewed-by: Nicolas Pitre <nico at linaro.org>" 
> to it.

Cheers Nicolas, will do.

Will


From l.stach at pengutronix.de  Fri May 31 13:02:24 2013
From: l.stach at pengutronix.de (Lucas Stach)
Date: Fri, 31 May 2013 19:02:24 +0200
Subject: [PATCH] arm: allow all architectures to change max zone order
Message-ID: <1370019744-7588-1-git-send-email-l.stach@pengutronix.de>

Many multimedia applications on architectures without an
IOMMU need large physically contiguous buffers and so need
to adjust the max zone order of the page allocator.

There is zero reason to not allow this adjustment on arches
other than SHMOBILE.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..6ceace8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1710,7 +1710,7 @@ config HW_PERF_EVENTS
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
-	int "Maximum zone order" if ARCH_SHMOBILE
+	int "Maximum zone order"
 	range 11 64 if ARCH_SHMOBILE
 	default "12" if SOC_AM33XX
 	default "9" if SA1111
-- 
1.7.10.4



From dmitry.torokhov at gmail.com  Fri May 31 13:04:37 2013
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Fri, 31 May 2013 10:04:37 -0700
Subject: [PATCH 00/11] drivers: Add Pinctrl PM support
In-Reply-To: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20130531170437.GA17591@core.coreip.homeip.net>

Hi Hebbar,

On Fri, May 31, 2013 at 03:43:00PM +0530, Hebbar Gururaja wrote:
> By optionally putting the pins into sleep state in the suspend [or in
> runtime_suspend] callback we can accomplish two things.
> - One is to minimize current leakage from pins and thus save power,
> - second, we can prevent the IP from driving pins output in an
> uncontrolled manner, which may happen if the power domain drops the
> domain regulator.
> 
> These states can be specified in the DT blob and corresponding driver
> can pick these states during probe & set the related values during
> idle/suspend.
> 
> Not all drivers support/has idle state. Drivers like i2c, spi, mmc has
> idle states and hence these drivers are updated to support all the
> three states
> - default  : during regular operation
> - idle : when the module is in idle state
> - sleep : when the module is in suspend state
> 
> For those drivers which doesn't support/have idle state (at least at
> the moment), only default & sleep state is added.

As with the original introduction of pinctrl states my question is: "Can
all of this be handled in the driver/bus core instead of adding a lot
of boilerplate code to the individual drivers".

Thanks.

-- 
Dmitry


From dianders at chromium.org  Fri May 31 13:08:39 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 31 May 2013 10:08:39 -0700
Subject: [PATCH v3 2/6] clk: samsung: Add support to register rate_table
 for PLL3xxx
In-Reply-To: <1370003496-19288-3-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
 <1370003496-19288-3-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=XnzS8TuvtGRrZ+jN=8AUYr-imL1bRsdWY3BDQVwm615g@mail.gmail.com>

Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>
> This patch defines a common rate_table which will contain recommended p, m, s,
> k values for supported rates that needs to be changed for changing
> corresponding PLL's rate.
>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
>  drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
>  drivers/clk/samsung/clk-pll.c        |   14 ++++++++++++--
>  drivers/clk/samsung/clk-pll.h        |   35 ++++++++++++++++++++++++++++++++--
>  4 files changed, 56 insertions(+), 15 deletions(-)

This looks good to me.  Hopefully Tomasz agrees.  Tomasz: if you
haven't been following this thread, see
<https://patchwork.kernel.org/patch/2643351/> for how we resolved the
constant vs. calculated input clock.

Reviewed-by: Doug Anderson <dianders at chromium.org>


From dianders at chromium.org  Fri May 31 13:10:58 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 31 May 2013 10:10:58 -0700
Subject: [PATCH v3 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx
In-Reply-To: <1370003496-19288-4-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
 <1370003496-19288-4-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=UuEYCjaiTHn0B2iBUyKqA+KcbGWMu4iTNhSDFPz3311w@mail.gmail.com>

Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> +static long samsung_pll_round_rate(struct clk_hw *hw,
> +                       unsigned long drate, unsigned long *prate)
> +{
> +       struct samsung_clk_pll *pll = to_clk_pll(hw);
> +       const struct samsung_pll_rate_table *rate_table = pll->rate_table;
> +       int i;
> +
> +       /* Assumming rate_table is in descending order */
> +       for (i = 0; i < pll->rate_count; i++) {
> +               if (drate >= rate_table[i].rate)
> +                       return rate_table[i].rate;
> +       }
> +
> +       /* return minimum supported value */
> +       return rate_table[i - 1].rate;
> +}
>  /*
>   * PLL35xx Clock Type
>   */

You seem to have lost a carriage return between v2 and v3.  I will add
it locally before applying.  This still looks good though and already
has my Reviewed-by.

-Doug


From dianders at chromium.org  Fri May 31 13:15:11 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 31 May 2013 10:15:11 -0700
Subject: [PATCH v3 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx
In-Reply-To: <1370003496-19288-5-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
 <1370003496-19288-5-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=XP3s+uJL+31XFz6r=BW5mGXDiK8EMT04rRwNf-XFa8qw@mail.gmail.com>

Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
>  struct clk * __init samsung_clk_register_pll36xx(const char *name,
> @@ -264,6 +318,11 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name,
>         init.parent_names = &pname;
>         init.num_parents = 1;
>
> +       if (rate_table && rate_count)
> +               init.ops = &samsung_pll36xx_clk_ops;
> +       else
> +               init.ops = &samsung_pll36xx_clk_min_ops;
> +
>         pll->hw.init = &init;
>         pll->base = base;
>         pll->rate_table = rate_table;

Interesting.  In the gerrit review you sent for v2 you properly
removed the line:

  init.ops = &samsung_pll36xx_clk_ops;

...but the v2 you posted upstream didn't have that removal.  You've
also lost it in v3.  Perhaps you can add that back in?  I'll do it
locally before applying.


-Doug


From dianders at chromium.org  Fri May 31 13:20:12 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 31 May 2013 10:20:12 -0700
Subject: [PATCH v3 5/6] clk: samsung: Add alias for mout_vpllsrc and
 reorder MUX registration for it
In-Reply-To: <1370003496-19288-6-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
 <1370003496-19288-6-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=Wcw7OArXr6mEoSWzvbhqQWGGTP88fc=kTq6iUzqj0YTQ@mail.gmail.com>

Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the
> "fout_vpll" (child), we found get rate was failing.
>
> So this patch moves the mout_vpllsrc MUX out of the existing common list
> and registers the mout_vpllsrc MUX before the PLL registrations.
> Its also adds the alias for the mout_vpllsrc MUX.

I think the moving makes sense, but not the alias.  IMHO global
aliases should be avoided unless they can be strongly justified.

In part 6 of this series I see where you're using the alias but I
don't think you need it.  In your case you are a clock provider, so I
think you can use __clk_lookup("mout_vpllsrc") to find your clock.

I will post an update on our gerrit and you can see what you think.
If someone on the list thinks that using __clk_lookup() is a bad idea
and they'd rather see the global alias, please shout.


-Doug


From khilman at linaro.org  Fri May 31 13:34:59 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 10:34:59 -0700
Subject: [PATCH 11/11] i2c: omap: enhance pinctrl support
In-Reply-To: <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>
 (Hebbar Gururaja's message of "Fri, 31 May 2013 15:43:11 +0530")
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
 <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <87k3mf2gu4.fsf@linaro.org>

Hebbar Gururaja <gururaja.hebbar at ti.com> writes:

> Amend the I2C omap pin controller to optionally take a pin control
> handle and set the state of the pins to:
>
> - "default" on boot, resume and before performing an i2c transfer
> - "idle" after initial default, after resume default, and after each
> i2c xfer
> - "sleep" on suspend()
>
> By optionally putting the pins into sleep state in the suspend callback
> we can accomplish two things.
> - One is to minimize current leakage from pins and thus save power,
> - second, we can prevent the IP from driving pins output in an
> uncontrolled manner, which may happen if the power domain drops the
> domain regulator.
>
> Note:
> A .suspend & .resume callback is added which simply puts the pins to sleep
> state upon suspend & are moved to default & idle state upon resume.
>
> If any of the above pin states are missing in dt, a warning message
> about the missing state is displayed.
> If certain pin-states are not available, to remove this warning message
> pass respective state name with null phandler.
>
> (Changes based on i2c-nomadik.c)
>
> Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Wolfram Sang <wsa at the-dreams.de>
> Cc: linux-omap at vger.kernel.org
> Cc: linux-i2c at vger.kernel.org

[...]

> @@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  
>  out:
>  	pm_runtime_mark_last_busy(dev->dev);
> +
>  	pm_runtime_put_autosuspend(dev->dev);
> +	/* Optionally let pins go into idle state */
> +	if (!IS_ERR(dev->pins_idle))
> +		if (pinctrl_select_state(dev->pinctrl, dev->pins_idle))
> +			dev_err(dev->dev, "could not set pins to idle state\n");

This is wrong.  You're changing the muxing before the device actually
goes idle.  Anything you want to happen when the device actually idles
for real has to be in runtime PM callbacks.

Looking below, I see it's already in the callbacks, so why is it here also?

[...]

> @@ -1300,6 +1348,10 @@ static int omap_i2c_runtime_suspend(struct device *dev)
>  		omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
>  	}
>  
> +	if (!IS_ERR(_dev->pins_idle))
> +		if (pinctrl_select_state(_dev->pinctrl, _dev->pins_idle))
> +			dev_err(dev, "could not set pins to idle state\n");
> +
>  	return 0;
>  }
>  

Kevin


From cooloney at gmail.com  Fri May 31 13:37:08 2013
From: cooloney at gmail.com (Bryan Wu)
Date: Fri, 31 May 2013 10:37:08 -0700
Subject: [PATCH] ARM: ux500: register LP5521 LEDs in the device tree
In-Reply-To: <1369210331-18545-1-git-send-email-linus.walleij@stericsson.com>
References: <1369210331-18545-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAK5ve-+oJL0fbtM=5xRSBjCztX1fP-fcwUvZurnj42hiXR5X+Q@mail.gmail.com>

On Wed, May 22, 2013 at 1:12 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
>
> Based on pending device tree support in the LP55xx drivers
> we can add the correct LED and channel configuration from the
> ux500 device tree for all HREF variants.
>
> Cc: Milo Kim <Milo.Kim at ti.com>
> Cc: Bryan Wu <cooloney at gmail.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/href.dtsi | 38 ++++++++++++++++++++++++++++++++------
>  1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
> index 62523f6..e315429 100644
> --- a/arch/arm/boot/dts/href.dtsi
> +++ b/arch/arm/boot/dts/href.dtsi
> @@ -63,16 +63,42 @@
>                 };
>
>                 i2c at 80128000 {
> -                       lp5521 at 0x33 {
> -                               compatible = "lp5521";
> +                       lp5521 at 33 {

Is this right, I guess it should be still "lp5521 at 0x33", although it's
just a name.

-Bryan

> +                               compatible = "national,lp5521";
>                                 reg = <0x33>;
> +                               label = "lp5521_pri";
> +                               clock-mode = /bits/ 8 <2>;
> +                               chan0 {
> +                                       led-cur = /bits/ 8 <0x2f>;
> +                                       max-cur = /bits/ 8 <0x5f>;
> +                               };
> +                               chan1 {
> +                                       led-cur = /bits/ 8 <0x2f>;
> +                                       max-cur = /bits/ 8 <0x5f>;
> +                               };
> +                               chan2 {
> +                                       led-cur = /bits/ 8 <0x2f>;
> +                                       max-cur = /bits/ 8 <0x5f>;
> +                               };
>                         };
> -
> -                       lp5521 at 0x34 {
> -                               compatible = "lp5521";
> +                       lp5521 at 34 {
> +                               compatible = "national,lp5521";
>                                 reg = <0x34>;
> +                               label = "lp5521_sec";
> +                               clock-mode = /bits/ 8 <2>;
> +                               chan0 {
> +                                       led-cur = /bits/ 8 <0x2f>;
> +                                       max-cur = /bits/ 8 <0x5f>;
> +                               };
> +                               chan1 {
> +                                       led-cur = /bits/ 8 <0x2f>;
> +                                       max-cur = /bits/ 8 <0x5f>;
> +                               };
> +                               chan2 {
> +                                       led-cur = /bits/ 8 <0x2f>;
> +                                       max-cur = /bits/ 8 <0x5f>;
> +                               };
>                         };
> -
>                         bh1780 at 0x29 {
>                                 compatible = "rohm,bh1780gli";
>                                 reg = <0x33>;
> --
> 1.7.11.3
>


From khilman at linaro.org  Fri May 31 13:41:22 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 10:41:22 -0700
Subject: [PATCH 2/2] rtc: omap: add rtc wakeup support to alarm events
In-Reply-To: <1369982005-8572-3-git-send-email-gururaja.hebbar@ti.com> (Hebbar
 Gururaja's message of "Fri, 31 May 2013 12:03:25 +0530")
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
 <1369982005-8572-3-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <87a9nb2gjh.fsf@linaro.org>

Hebbar Gururaja <gururaja.hebbar at ti.com> writes:

> On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
> is available to enable Wakeup feature for Alarm Events.
>
> Since new platforms/Boards are now added through DT only, this feature
> is supported via DT property only.

> Platforms using such IP should add the property "ti,has_irq_wake_enb"
> in rtc DT node.

This is a property of the IP, not the board.  Can't you detect this
based on the revision of the IP?

Kevin


From sboyd at codeaurora.org  Fri May 31 13:45:26 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri, 31 May 2013 10:45:26 -0700
Subject: [PATCHv6 00/11] Remove ARM local timer API
In-Reply-To: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <20130531174526.GD599@codeaurora.org>

Comments have been light for this round so I think we're about
ready to merge. John/Thomas, can you pick up these patches or
shall I route them through arm-soc or something else?

On 05/13, Stephen Boyd wrote:
> In light of Mark Rutland's recent work on divorcing the ARM architected
> timers from the ARM local timer API and introducing a generic arch hook for
> broadcast it seems that we should remove the local timer API entirely.
> Doing so will reduce the architecture dependencies of our timer drivers,
> reduce code in ARM core, and simplify timer drivers because they no longer
> go through an architecture layer that is essentially a hotplug notifier.
> 
> Previous attempts have been made[1] unsuccessfully. I'm hoping this can
> be accepted now so that we can clean up the timer drivers that are
> used in both UP and SMP situations. Right now these drivers have to ignore
> the timer setup callback on the boot CPU to avoid registering clockevents
> twice. This is not very symmetric and causes convuluted code that does
> the same thing in two places.
> 
> Patches based on next-20130418
> 
> I'm still looking for Acks/Tested-by on EXYNOS and PRIMA2.
> 
> [1] http://article.gmane.org/gmane.linux.ports.arm.kernel/145705
> 
> Note: A hotplug notifier is used by both x86 for the apb_timer (see 
> apbt_cpuhp_notify) and by metag (see arch_timer_cpu_notify in
> metag_generic.c) so this is not new.
> 
> Changes since v5:
>  * Rebased onto v3.10-rc1
>  * Rebase caused minor updates to mct patch
> 
> Changes since v4:
>  * Rebased onto next-20130418
>  * Rebase caused minor updates to mct patch and twd Kconfig
> 
> Changes since v3:
>  * New patch to fix SMP with dummy timers registered after a global timer
>  * Push this_cpu_ptr lower to avoid preemptible false positive warnings
>  * Collected acks/tested-bys
> 
> Changes since v2:
>  * Bug fixes in smp_twd from Tony Lindgren's testing
>  * Move smp_twd to use late_time_init hook
>  * Collected Acks
> 
> Changes since v1:
>  * Picked up Mark's generic dummy timer driver
>  * Split out omap changes into new patch
> 
> Mark Rutland (1):
>   clocksource: add generic dummy timer driver
> 
> Stephen Boyd (10):
>   clockevents: Prefer CPU local devices over global devices
>   ARM: smp: Remove duplicate dummy timer implementation
>   ARM: smp_twd: Divorce smp_twd from local timer API
>   ARM: OMAP2+: Divorce from local timer API
>   ARM: EXYNOS4: Divorce mct from local timer API
>   ARM: PRIMA2: Divorce timer-marco from local timer API
>   ARM: msm: Divorce msm_timer from local timer API
>   clocksource: time-armada-370-xp: Fix sparse warning
>   clocksource: time-armada-370-xp: Divorce from local timer API
>   ARM: smp: Remove local timer API
> 
>  arch/arm/Kconfig                         |  12 +--
>  arch/arm/include/asm/localtimer.h        |  34 ---------
>  arch/arm/kernel/smp.c                    |  87 ---------------------
>  arch/arm/kernel/smp_twd.c                |  64 ++++++++++------
>  arch/arm/mach-highbank/Kconfig           |   2 +-
>  arch/arm/mach-imx/Kconfig                |   2 +-
>  arch/arm/mach-msm/timer.c                | 126 +++++++++++++++++--------------
>  arch/arm/mach-omap2/Kconfig              |   3 +-
>  arch/arm/mach-omap2/timer.c              |   7 --
>  arch/arm/mach-realview/Kconfig           |   8 +-
>  arch/arm/mach-spear/Kconfig              |   2 +-
>  arch/arm/mach-tegra/Kconfig              |   2 +-
>  arch/arm/mach-ux500/Kconfig              |   2 +-
>  arch/arm/mach-vexpress/Kconfig           |   2 +-
>  arch/arm/mach-zynq/Kconfig               |   2 +-
>  drivers/clocksource/Makefile             |   1 +
>  drivers/clocksource/dummy_timer.c        |  69 +++++++++++++++++
>  drivers/clocksource/exynos_mct.c         |  60 ++++++++++-----
>  drivers/clocksource/time-armada-370-xp.c |  92 +++++++++++-----------
>  drivers/clocksource/timer-marco.c        | 100 +++++++++++++-----------
>  include/linux/time-armada-370-xp.h       |   4 +-
>  kernel/time/tick-common.c                |   5 +-
>  22 files changed, 340 insertions(+), 346 deletions(-)
>  delete mode 100644 arch/arm/include/asm/localtimer.h
>  create mode 100644 drivers/clocksource/dummy_timer.c
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From khilman at linaro.org  Fri May 31 13:48:03 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 10:48:03 -0700
Subject: [PATCH 1/2] rtc: omap: add option to indicate wakeup support
 through DT
In-Reply-To: <1369982005-8572-2-git-send-email-gururaja.hebbar@ti.com> (Hebbar
 Gururaja's message of "Fri, 31 May 2013 12:03:24 +0530")
References: <1369982005-8572-1-git-send-email-gururaja.hebbar@ti.com>
 <1369982005-8572-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <87wqqf11nw.fsf@linaro.org>

Hebbar Gururaja <gururaja.hebbar at ti.com> writes:

> Even though RTC-IP is wakeup capable, Not all Boards support it.
>
> For example
> The rtc alarm wakeup is available in rtc-ip since omap1 days but alarm
> was not wired properly in previous ompa1 boards.
>
> 	commit fa5b07820fe3a0fc06ac368516e71f10a59b9539
> 	Author: Sekhar Nori <nsekhar at ti.com>
> 	Date:   Wed Oct 27 15:33:05 2010 -0700
>
> 	rtc: omap: let device wakeup capability be configured from chip
> 	init logic
>
> 	The rtc-omap driver currently hardcodes the RTC wakeup
> 	capability to be "not capable".  While this seems to be true for
> 	existing OMAP1 boards which are not wired for this, the
> 	DA850/OMAP-L138 SoC, the RTC can always be wake up source from
> 	its "deep sleep" mode.
>
> Current rtc-omap driver expects the rtc module wake-up capabilities to
> be set up by board specific code. However, in case of DT, this is not
> possible.
>
> So, add a DT property "ti,wakeup_capable" to indicate that the module is
> wake-up capable.

Why is this a TI-specific property?  

Also, I think we can do this without a new DT property.Did you see this
patch from Tony which is already queued for v3.11:

    http://marc.info/?l=linux-omap&m=136917244530612&w=2

I think this is the right way to go.  Platforms that don't want/need
wakeup support can disable it from userspace via:

    echo disabled > /sys/devices/.../power/wakeup

Kevin



From tony at atomide.com  Fri May 31 13:52:30 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 May 2013 10:52:30 -0700
Subject: MUSB multiplatform work?
In-Reply-To: <20130531040004.GA7879@arwen.pp.htv.fi>
References: <201305271702.09203.arnd@arndb.de>
 <20130528163548.GC28253@arwen.pp.htv.fi>
 <20130530201854.GB6467@atomide.com>
 <20130530205448.GD6467@atomide.com>
 <20130531040004.GA7879@arwen.pp.htv.fi>
Message-ID: <20130531175228.GP6467@atomide.com>

* Felipe Balbi <balbi at ti.com> [130530 21:06]:
> On Thu, May 30, 2013 at 01:54:49PM -0700, Tony Lindgren wrote:
> > * Tony Lindgren <tony at atomide.com> [130530 13:25]:
> > > 
> > > TUSB we can make depend on ARMv7, the only implementation we have
> > > is for omap2420, which is ARMv6. This should solve the issue for
> > > ARMv7 multiplatform builds for now.
> > 
> > Sorry mean depend on !ARMv7. But thinking about it more, that does
> > not make much sense as it would break things for omap2plus_defconfig
> > at least which is multiplatform v6 and v7. For now TUSB can be made
> > to depend on MACH_NOKIA_N8X0. I doubt that anybody is using the add
> > on cards for H4 boards any longer..
> 
> could also be made to depend on BROKEN. I don't think anyone *really*
> cares about that glue layer other than the very few in the world who
> still like the nostalgic feeling of booting current linux releases on
> n8x0 devices.

Unfortunately that's the best test case we have for GPMC and DMA stress
testing so it's good to keep around.

And n8x0 is still quite usable general purpose pocket computer with
keyboard and WLAN and tons of storage :)

Regards,

Tony


From dianders at chromium.org  Fri May 31 13:58:07 2013
From: dianders at chromium.org (Doug Anderson)
Date: Fri, 31 May 2013 10:58:07 -0700
Subject: [PATCH v3 6/6] clk: samsung: Add EPLL and VPLL freq table for
 exynos5250 SoC
In-Reply-To: <1370003496-19288-7-git-send-email-vikas.sajjan@linaro.org>
References: <1370003496-19288-1-git-send-email-vikas.sajjan@linaro.org>
 <1370003496-19288-7-git-send-email-vikas.sajjan@linaro.org>
Message-ID: <CAD=FV=UXV59zcrhLxjnU0LgX1LR855mQUd-xMM4bbXhRmB7UyQ@mail.gmail.com>

Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> Adds the EPLL and VPLL freq table for exynos5250 SoC.
>
> Signed-off-by: Vikas Sajjan <vikas.sajjan at linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |   48 +++++++++++++++++++++++++++++++---
>  drivers/clk/samsung/clk.h            |    2 ++
>  2 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index b0e6680..0566421 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -473,11 +473,32 @@ static __initdata struct of_device_id ext_clk_match[] = {
>         { },
>  };
>
> +static const struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
> +       /* sorted in descending order */
> +       /* PLL_36XX_RATE(rate, m, p, s, k) */
> +       PLL_36XX_RATE(266000000, 266, 3, 3, 0),
> +       PLL_36XX_RATE(70500000, 94, 2, 4, 0),

Would be nice to include the comment that you included in our gerrit:
that the 70.5 is not in the manual but is used by exynos5250-snow.


> +       fin_pll_rate = _get_rate("fin_pll");
> +       mout_vpllsrc_rate = _get_rate("mout_vpllsrc");

This line is why you added an alias for mout_vpllsrc.  I'd rather not
see that since it also exports the clock to other places.

I've changed this to use __clk_lookup().  That function _is_ exported
by <linux/clk-provider.h> and we are a clock provider, so it seems
legit to use that.  ...and it's nice not to have an extra clock alias.

See my changes to <https://gerrit.chromium.org/gerrit/#/c/56797/> for
an example.


> @@ -507,10 +531,28 @@ void __init exynos5250_clk_init(struct device_node *np)
>                         reg_base + 0x10050, NULL, 0);
>         cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
>                         reg_base + 0x10020, NULL, 0);
> -       epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
> -                       reg_base + 0x10030, NULL, 0);
> -       vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
> +
> +       if (fin_pll_rate == (24 * MHZ)) {
> +               epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
> +                               reg_base + 0x10030, epll_24mhz_tbl,
> +                               ARRAY_SIZE(epll_24mhz_tbl));
> +       } else {
> +               pr_warn("Exynos5250: valid epll rate_table missing for\n"
> +                       "parent fin_pll:%lu hz\n", fin_pll_rate);

nit: use %s and __func__ rather than adding Exynos5250 hardcoded in here?


-Doug


From khilman at linaro.org  Fri May 31 14:07:02 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 11:07:02 -0700
Subject: [PATCH 11/11] i2c: omap: enhance pinctrl support
In-Reply-To: <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>
 (Hebbar Gururaja's message of "Fri, 31 May 2013 15:43:11 +0530")
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
 <1369995191-20855-12-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <87bo7r10s9.fsf@linaro.org>

+Linus Walleij (pinctrl maintainer)

Hebbar Gururaja <gururaja.hebbar at ti.com> writes:

> Amend the I2C omap pin controller to optionally take a pin control
> handle and set the state of the pins to:
>
> - "default" on boot, resume and before performing an i2c transfer
> - "idle" after initial default, after resume default, and after each
> i2c xfer
> - "sleep" on suspend()
>
> By optionally putting the pins into sleep state in the suspend callback
> we can accomplish two things.
> - One is to minimize current leakage from pins and thus save power,
> - second, we can prevent the IP from driving pins output in an
> uncontrolled manner, which may happen if the power domain drops the
> domain regulator.
>
> Note:
> A .suspend & .resume callback is added which simply puts the pins to sleep
> state upon suspend & are moved to default & idle state upon resume.
>
> If any of the above pin states are missing in dt, a warning message
> about the missing state is displayed.
> If certain pin-states are not available, to remove this warning message
> pass respective state name with null phandler.
>
> (Changes based on i2c-nomadik.c)
>
> Signed-off-by: Hebbar Gururaja <gururaja.hebbar at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Wolfram Sang <wsa at the-dreams.de>
> Cc: linux-omap at vger.kernel.org
> Cc: linux-i2c at vger.kernel.org

[...]

> @@ -1123,14 +1138,47 @@ omap_i2c_probe(struct platform_device *pdev)
>  		dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
>  	}
>  
> -	dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
> -	if (IS_ERR(dev->pins)) {
> -		if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
> +	dev->pinctrl = devm_pinctrl_get(&pdev->dev);
> +	if (!IS_ERR(dev->pinctrl)) {
> +		dev->pins_default = pinctrl_lookup_state(dev->pinctrl,
> +							 PINCTRL_STATE_DEFAULT);

This part is already done by probe in driver core, why does it need to
be done again.  dev->pins->default_state should already have this.
(c.f. pinctrl_bind_pins() in drivers/base/pinctrl.c)

But that brings up a bigger question about whether or not we should be
doing the rest of this (idle/sleep) pin management in the drivers or in
the driver core as well.  I would much prefer it be handled by the
driver core.

In fact, since these are all PM related events, it should probably be
handled by the PM core and seems pretty straight forward to do so.

Kevin


From khilman at linaro.org  Fri May 31 14:08:06 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 11:08:06 -0700
Subject: [PATCH 00/11] drivers: Add Pinctrl PM support
In-Reply-To: <20130531170437.GA17591@core.coreip.homeip.net> (Dmitry
 Torokhov's message of "Fri, 31 May 2013 10:04:37 -0700")
References: <1369995191-20855-1-git-send-email-gururaja.hebbar@ti.com>
 <20130531170437.GA17591@core.coreip.homeip.net>
Message-ID: <8761xz10qh.fsf@linaro.org>

+ Linus W. (pinctrl maintainer)

Dmitry Torokhov <dmitry.torokhov at gmail.com> writes:

> Hi Hebbar,
>
> On Fri, May 31, 2013 at 03:43:00PM +0530, Hebbar Gururaja wrote:
>> By optionally putting the pins into sleep state in the suspend [or in
>> runtime_suspend] callback we can accomplish two things.
>> - One is to minimize current leakage from pins and thus save power,
>> - second, we can prevent the IP from driving pins output in an
>> uncontrolled manner, which may happen if the power domain drops the
>> domain regulator.
>> 
>> These states can be specified in the DT blob and corresponding driver
>> can pick these states during probe & set the related values during
>> idle/suspend.
>> 
>> Not all drivers support/has idle state. Drivers like i2c, spi, mmc has
>> idle states and hence these drivers are updated to support all the
>> three states
>> - default  : during regular operation
>> - idle : when the module is in idle state
>> - sleep : when the module is in suspend state
>> 
>> For those drivers which doesn't support/have idle state (at least at
>> the moment), only default & sleep state is added.
>
> As with the original introduction of pinctrl states my question is: "Can
> all of this be handled in the driver/bus core instead of adding a lot
> of boilerplate code to the individual drivers".

Yes, I had the same thought.

What's being handled here are either events related to runtime PM
(runtime suspend, runtime resume) or system PM (suspend/resume) so seems
appropriat to handle them in the PM core.

Kevin


From john.stultz at linaro.org  Fri May 31 14:08:29 2013
From: john.stultz at linaro.org (John Stultz)
Date: Fri, 31 May 2013 11:08:29 -0700
Subject: [PATCHv6 00/11] Remove ARM local timer API
In-Reply-To: <20130531174526.GD599@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
 <20130531174526.GD599@codeaurora.org>
Message-ID: <51A8E71D.1000407@linaro.org>

On 05/31/2013 10:45 AM, Stephen Boyd wrote:
> Comments have been light for this round so I think we're about
> ready to merge. John/Thomas, can you pick up these patches or
> shall I route them through arm-soc or something else?


So there looks to be a fair amount of additions in the ARM tree, do 
those already have acks from Arnd/Olof/other folks? (I think I was only 
cc'ed on the first two patches).

Daniel (cc'ed) has just started helping out here, and should be able to 
review and hopefully ack or pick up the timer related 
drivers/clocksource changes to feed to Thomas' tree. Not sure if he's 
got them in his mailbox so you might want to resend them and make sure 
he's CC'ed.

If Arnd/Olof/whomever else from the arm side has acked things, Daniel 
probably could queue the arm changes too, but it might be better just to 
get Daniel's ack on the drivers/clocksource changes and then queue 
things via arm-soc?

thanks
-john



> On 05/13, Stephen Boyd wrote:
>> In light of Mark Rutland's recent work on divorcing the ARM architected
>> timers from the ARM local timer API and introducing a generic arch hook for
>> broadcast it seems that we should remove the local timer API entirely.
>> Doing so will reduce the architecture dependencies of our timer drivers,
>> reduce code in ARM core, and simplify timer drivers because they no longer
>> go through an architecture layer that is essentially a hotplug notifier.
>>
>> Previous attempts have been made[1] unsuccessfully. I'm hoping this can
>> be accepted now so that we can clean up the timer drivers that are
>> used in both UP and SMP situations. Right now these drivers have to ignore
>> the timer setup callback on the boot CPU to avoid registering clockevents
>> twice. This is not very symmetric and causes convuluted code that does
>> the same thing in two places.
>>
>> Patches based on next-20130418
>>
>> I'm still looking for Acks/Tested-by on EXYNOS and PRIMA2.
>>
>> [1] http://article.gmane.org/gmane.linux.ports.arm.kernel/145705
>>
>> Note: A hotplug notifier is used by both x86 for the apb_timer (see
>> apbt_cpuhp_notify) and by metag (see arch_timer_cpu_notify in
>> metag_generic.c) so this is not new.
>>
>> Changes since v5:
>>   * Rebased onto v3.10-rc1
>>   * Rebase caused minor updates to mct patch
>>
>> Changes since v4:
>>   * Rebased onto next-20130418
>>   * Rebase caused minor updates to mct patch and twd Kconfig
>>
>> Changes since v3:
>>   * New patch to fix SMP with dummy timers registered after a global timer
>>   * Push this_cpu_ptr lower to avoid preemptible false positive warnings
>>   * Collected acks/tested-bys
>>
>> Changes since v2:
>>   * Bug fixes in smp_twd from Tony Lindgren's testing
>>   * Move smp_twd to use late_time_init hook
>>   * Collected Acks
>>
>> Changes since v1:
>>   * Picked up Mark's generic dummy timer driver
>>   * Split out omap changes into new patch
>>
>> Mark Rutland (1):
>>    clocksource: add generic dummy timer driver
>>
>> Stephen Boyd (10):
>>    clockevents: Prefer CPU local devices over global devices
>>    ARM: smp: Remove duplicate dummy timer implementation
>>    ARM: smp_twd: Divorce smp_twd from local timer API
>>    ARM: OMAP2+: Divorce from local timer API
>>    ARM: EXYNOS4: Divorce mct from local timer API
>>    ARM: PRIMA2: Divorce timer-marco from local timer API
>>    ARM: msm: Divorce msm_timer from local timer API
>>    clocksource: time-armada-370-xp: Fix sparse warning
>>    clocksource: time-armada-370-xp: Divorce from local timer API
>>    ARM: smp: Remove local timer API
>>
>>   arch/arm/Kconfig                         |  12 +--
>>   arch/arm/include/asm/localtimer.h        |  34 ---------
>>   arch/arm/kernel/smp.c                    |  87 ---------------------
>>   arch/arm/kernel/smp_twd.c                |  64 ++++++++++------
>>   arch/arm/mach-highbank/Kconfig           |   2 +-
>>   arch/arm/mach-imx/Kconfig                |   2 +-
>>   arch/arm/mach-msm/timer.c                | 126 +++++++++++++++++--------------
>>   arch/arm/mach-omap2/Kconfig              |   3 +-
>>   arch/arm/mach-omap2/timer.c              |   7 --
>>   arch/arm/mach-realview/Kconfig           |   8 +-
>>   arch/arm/mach-spear/Kconfig              |   2 +-
>>   arch/arm/mach-tegra/Kconfig              |   2 +-
>>   arch/arm/mach-ux500/Kconfig              |   2 +-
>>   arch/arm/mach-vexpress/Kconfig           |   2 +-
>>   arch/arm/mach-zynq/Kconfig               |   2 +-
>>   drivers/clocksource/Makefile             |   1 +
>>   drivers/clocksource/dummy_timer.c        |  69 +++++++++++++++++
>>   drivers/clocksource/exynos_mct.c         |  60 ++++++++++-----
>>   drivers/clocksource/time-armada-370-xp.c |  92 +++++++++++-----------
>>   drivers/clocksource/timer-marco.c        | 100 +++++++++++++-----------
>>   include/linux/time-armada-370-xp.h       |   4 +-
>>   kernel/time/tick-common.c                |   5 +-
>>   22 files changed, 340 insertions(+), 346 deletions(-)
>>   delete mode 100644 arch/arm/include/asm/localtimer.h
>>   create mode 100644 drivers/clocksource/dummy_timer.c
>>
>> -- 
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> hosted by The Linux Foundation
>>
>> --
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From khilman at linaro.org  Fri May 31 14:20:45 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 11:20:45 -0700
Subject: [PATCH] ARM: EXYNOS: Consolidate multiple low-level UART port
 definitions
In-Reply-To: <1369888827-9427-1-git-send-email-tushar.behera@linaro.org>
 (Tushar Behera's message of "Thu, 30 May 2013 10:10:27 +0530")
References: <1369888827-9427-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <871u8n105e.fsf@linaro.org>

Tushar Behera <tushar.behera at linaro.org> writes:

> There are two definitions for low-level UART ports for Exynos platform.
> CONFIG_S3C_LOWLEVEL_UART_PORT is used for printing "Uncompressing
> Linux... done, booting the kernel." and CONFIG_S3C_UART for other
> low-level messages.
>
> The assumption for both the uart ports is that they are pre-configured
> in the bootloader. Since they are essentially the same always, it
> would be good to consolidate them to use only one macro, in this case
> 'DEBUG_S3C_UART' would be a better option.
>
> 'DEBUG_S3C_UART' is defined only if DEBUG_LL is enabled. We can safely
> disable this option when DEBUG_LL is not defined and we can boot various
> boards with different UART port settings. Only drawback of this
> approach is that when DEBUG_LL is not defined, we would be missing the
> print "Uncompressing Linux... done, booting the kernel."

Perfectly acceptable to me (and already the case on OMAP.)

> Since CONFIG_S3C_LOWLEVEL_UART_PORT is still used by other Samsung
> boards, the consolidation applies only for ARCH_EXYNOS.
>
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>

Acked-by: Kevin Hilman <khilman at linaro.org>



From sboyd at codeaurora.org  Fri May 31 14:38:28 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri, 31 May 2013 11:38:28 -0700
Subject: [PATCHv6 07/11] ARM: PRIMA2: Divorce timer-marco from local
 timer API
In-Reply-To: <1368473175-4841-8-git-send-email-sboyd@codeaurora.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
 <1368473175-4841-8-git-send-email-sboyd@codeaurora.org>
Message-ID: <20130531183828.GE599@codeaurora.org>

On 05/13, Stephen Boyd wrote:
> Separate the marco local timers from the local timer API. This
> will allow us to remove ARM local timer support in the near future
> and gets us closer to moving this driver to drivers/clocksource.
> 
> Cc: Barry Song <baohua.song at csr.com>
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---

Barry, have you been able to test this patch?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From gmbnomis at gmail.com  Fri May 31 14:54:14 2013
From: gmbnomis at gmail.com (Simon Baatz)
Date: Fri, 31 May 2013 20:54:14 +0200
Subject: [PATCH V4] ARM: handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <CACVXFVOo6HNXeZ95QqAXU64aAmXXrTVsHJ9TvgirWKOWmwnSfA@mail.gmail.com>
References: <1368336956-6693-1-git-send-email-gmbnomis@gmail.com>
 <CACVXFVOo6HNXeZ95QqAXU64aAmXXrTVsHJ9TvgirWKOWmwnSfA@mail.gmail.com>
Message-ID: <20130531185414.GA19061@schnuecks.de>

On Fri, May 31, 2013 at 05:07:22PM +0800, Ming Lei wrote:
> On Sun, May 12, 2013 at 1:35 PM, Simon Baatz <gmbnomis at gmail.com> wrote:
> > +void flush_kernel_dcache_page(struct page *page)
> > +{
> > +       if (cache_is_vivt() || cache_is_vipt_aliasing()) {
> > +               struct address_space *mapping;
> > +
> > +               mapping = page_mapping(page);
> > +
> > +               if (!mapping || mapping_mapped(mapping))
> 
> It is better to replace mapping_mapped(mapping) with page_mapped(page).

Good point. I did not have the time to look into your proposed change
for flush_dcache_page() yet.

However, this patch here is a fix for a long standing bug, which
should also be applied to stable in one form or another.  I would not
like to mix it with a separate performance improvement.

But, of course, if we decide to change the respective condition in
flush_dcache_page(), we should also change it in
flush_kernel_dcache_page() at the same time (provided this patch gets
accepted).
 
> > +                       __flush_kernel_dcache_page(page);
> 
> I am wondering if I-cache should be flushed here since the user mapping
> on the page may be executable and I/D coherency should be maintained.

Me too. In fact, I wondered so much that I proposed it myself in a
previous version of the patch (see [1]) :-) However, this has never
been part of flush_kernel_dcache_page() and it is not clear whether
the flush for I/D-cache coherency is really needed here (or in
flush_dcache_page() for that matter) or whether it is sufficient to
do it when mapping the page into user space.

On top of that neither Russell nor Catalin liked this idea very much.

- Simon


[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/124292.html


From soren.brinkmann at xilinx.com  Fri May 31 15:12:07 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 31 May 2013 12:12:07 -0700
Subject: [BUG] zynq | CCF | SRCU
Message-ID: <42b8bfd5-3012-4c49-b9ef-7a9beb5956f1@VA3EHSMHS041.ehs.local>

Hi,

we recently encountered some kernel panics when we compiled one of our
drivers as module and tested inserting/removing the module.
Trying to debug this issue, I could reproduce it on the mainline kernel
with a dummy module.

What happens is, that when on driver remove clk_notifier_unregister() is
called and no other notifier for that clock is registered, the kernel
panics.
I'm not sure what is going wrong here. If there is a bug (and if where)
or I'm just using the infrastructure the wrong way,... So, any hint is
appreciated.

I attach the output from the crashing system. The stacktrace indicates a
crash in 'srcu_readers_seq_idx()'.
I also attach the module I used to trigger the issue and a patch on top
of mainline commit a93cb29acaa8f75618c3f202d1cf43c231984644 which has
the DT modifications I need to make the module find its clock and boot
with my initramfs.


	Thanks,
	S??ren

-------------- next part --------------


U-Boot 2013.01-00001-g7926df4 (Apr 09 2013 - 09:45:48)

I2C:   ready
DRAM:  1 GiB
WARNING: Caches not enabled
MMC:   zynq_sdhci: 0
SF: Detected N25Q128A with page size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   Gem.e000b000
Hit any key to stop autoboot:  3  2  1  0 
TFTPing Linux to RAM...
Gem.e000b000 Waiting for PHY auto negotiation to complete..... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'uImage'.
Load address: 0x3000000
Loading: *T #################################################################
	 #################################################################
	 ##################################
	 410.2 KiB/s
done
Bytes transferred = 2397912 (2496d8 hex)
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete..... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'devicetree.dtb'.
Load address: 0x2a00000
Loading: *#
	 200.2 KiB/s
done
Bytes transferred = 3078 (c06 hex)
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete..... done
Using Gem.e000b000 device
TFTP from server 10.10.70.101; our IP address is 10.10.70.102
Filename 'uramdisk.image.gz'.
Load address: 0x2000000
Loading: *#################################################################
	 #################################################################
	 #################################################################
	 ################################################################
	 3.4 MiB/s
done
Bytes transferred = 3792138 (39dd0a hex)
## Booting kernel from Legacy Image at 03000000 ...
   Image Name:   Linux-3.10.0-rc3-00119-ga93cb29-
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2397848 Bytes = 2.3 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 02000000 ...
   Image Name:   
   Image Type:   ARM Linux RAMDisk Image (gzip compressed)
   Data Size:    3792074 Bytes = 3.6 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
   Booting using the fdt blob at 0x02a00000
   Loading Kernel Image ... OK
OK
   Loading Ramdisk to 1fc62000, end 1ffffcca ... OK
   Loading Device Tree to 1fc5e000, end 1fc61c05 ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0

[    0.000000] Linux version 3.10.0-rc3-00119-ga93cb29-dirty (sorenb at xsjandreislx) (gcc version 4.7.2 (Sourcery CodeBench Lite 2012.09-104) ) #85 SMP PREEMPT Fri May 31 11:43:25 PDT 2013

[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d

[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

[    0.000000] Machine: Xilinx Zynq Platform, model: Zynq ZC702 Development Board

[    0.000000] bootconsole [earlycon0] enabled

[    0.000000] cma: CMA: reserved 16 MiB at 2e800000

[    0.000000] Memory policy: ECC disabled, Data cache writealloc

[    0.000000] PERCPU: Embedded 9 pages/cpu @c1475000 s14144 r8192 d14528 u36864

[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260624

[    0.000000] Kernel command line: console=ttyPS0,115200 earlyprintk

[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)

[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)

[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)

[    0.000000] Memory: 1024MB = 1024MB total

[    0.000000] Memory: 1006620k/1006620k available, 41956k reserved, 270336K highmem

[    0.000000] Virtual kernel memory layout:

[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)

[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)

[    0.000000]     vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)

[    0.000000]     lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)

[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)

[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)

[    0.000000]       .text : 0xc0008000 - 0xc06338a4   (6319 kB)

[    0.000000]       .init : 0xc0634000 - 0xc0685740   ( 326 kB)

[    0.000000]       .data : 0xc0686000 - 0xc06d0ee0   ( 300 kB)

[    0.000000]        .bss : 0xc06d0ee0 - 0xc0c615d0   (5698 kB)

[    0.000000] Preemptible hierarchical RCU implementation.

[    0.000000] 	RCU lockdep checking is enabled.

[    0.000000] 	Additional per-CPU info printed with stalls.

[    0.000000] 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.

[    0.000000] NR_IRQS:16 nr_irqs:16 16

[    0.000000] slcr mapped to f0002000

[    0.000000] ttc0 #0 at f0004000, irq=43

[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms

[    0.000000] Console: colour dummy device 80x30

[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar

[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8

[    0.000000] ... MAX_LOCK_DEPTH:          48

[    0.000000] ... MAX_LOCKDEP_KEYS:        8191

[    0.000000] ... CLASSHASH_SIZE:          4096

[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384

[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768

[    0.000000] ... CHAINHASH_SIZE:          16384

[    0.000000]  memory used by lock dependency info: 3695 kB

[    0.000000]  per task-struct memory footprint: 1152 bytes

[    0.060000] Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)

[    0.150000] pid_max: default: 32768 minimum: 301

[    0.150000] Mount-cache hash table entries: 512

[    0.160000] CPU: Testing write buffer coherency: ok

[    0.160000] ftrace: allocating 15863 entries in 47 pages

[    0.200000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000

[    0.200000] Setting up static identity map for 0xc04552d8 - 0xc0455330

[    0.210000] CPU1: Booted secondary processor

[    0.300000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001

[    0.300000] Brought up 2 CPUs

[    0.300000] SMP: Total of 2 processors activated (2664.03 BogoMIPS).

[    0.310000] CPU: All CPU(s) started in SVC mode.

[    0.320000] devtmpfs: initialized

[    0.340000] NET: Registered protocol family 16

[    0.340000] DMA: preallocated 256 KiB pool for atomic coherent allocations

[    0.360000] L310 cache controller enabled

[    0.360000] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 524288 B

[    0.370000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.

[    0.370000] hw-breakpoint: maximum watchpoint size is 4 bytes.

[    0.450000] bio: create slab <bio-0> at 0

[    0.460000] SCSI subsystem initialized

[    0.460000] usbcore: registered new interface driver usbfs

[    0.460000] usbcore: registered new interface driver hub

[    0.470000] usbcore: registered new device driver usb

[    0.480000] Switching to clocksource ttc_clocksource

[    0.650000] NET: Registered protocol family 2

[    0.650000] TCP established hash table entries: 8192 (order: 4, 65536 bytes)

[    0.650000] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)

[    0.670000] TCP: Hash tables configured (established 8192 bind 8192)

[    0.670000] TCP: reno registered

[    0.670000] UDP hash table entries: 512 (order: 3, 40960 bytes)

[    0.680000] UDP-Lite hash table entries: 512 (order: 3, 40960 bytes)

[    0.690000] NET: Registered protocol family 1

[    0.690000] RPC: Registered named UNIX socket transport module.

[    0.690000] RPC: Registered udp transport module.

[    0.700000] RPC: Registered tcp transport module.

[    0.700000] RPC: Registered tcp NFSv4.1 backchannel transport module.

[    0.710000] Trying to unpack rootfs image as initramfs...

[    1.250000] Freeing initrd memory: 3700K (dfc62000 - dffff000)

[    1.260000] bounce pool size: 64 pages

[    1.260000] jffs2: version 2.2. (NAND) (SUMMARY)  ?? 2001-2006 Red Hat, Inc.

[    1.260000] msgmni has been set to 1477

[    1.290000] io scheduler noop registered

[    1.290000] io scheduler deadline registered

[    1.290000] io scheduler cfq registered (default)

[    1.310000] e000?[    1.310000] console [ttyPS0] enabled, bootconsole disabled
[    1.310000] console [ttyPS0] enabled, bootconsole disabled

[    1.360000] brd: module loaded
[    1.380000] loop: module loaded
[    1.400000] usbcore: registered new interface driver usb-storage
[    1.410000] mousedev: PS/2 mouse device common for all mice
[    1.420000] i2c /dev entries driver
[    1.430000] mpcore_wdt: MPcore Watchdog Timer: 0.1. mpcore_noboot=0 mpcore_margin=60 sec (nowayout= 0)
[    1.440000] cpuidle: using governor ladder
[    1.440000] cpuidle: using governor menu
[    1.440000] sdhci: Secure Digital Host Controller Interface driver
[    1.450000] sdhci: Copyright(c) Pierre Ossman
[    1.460000] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.460000] usbcore: registered new interface driver usbhid
[    1.470000] usbhid: USB HID core driver
[    1.470000] TCP: cubic registered
[    1.480000] NET: Registered protocol family 17
[    1.480000] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    1.490000] Registering SWP/SWPB emulation handler
[    1.500000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[    1.510000] Freeing unused kernel memory: 324K (c0634000 - c0685000)
Starting logging: OK
Starting mdev...
mdev: bad line 25
mdev: bad line 26
mdev: bad line 27
mdev: bad line 28
mdev: bad line 29
mdev: bad line 32
mdev: bad line 33
mdev: bad line 34
mdev: bad line 35
Initializing random number generator... done.
Starting network...
Starting dropbear sshd: generating rsa key... generating dsa key... OK


Zynq Busybox System

zynq login: root
Password: 
# lsmod
# modprobe clk_notif_dbg
[  508.310000] clk_notif_dbg clk_notif_dbg.1: clk_get()
[  508.320000] clk_notif_dbg clk_notif_dbg.1: clk_prepare()
[  508.320000] clk_notif_dbg clk_notif_dbg.1: clk_enable()
[  508.330000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_register()
[  508.330000] clk_notif_dbg clk_notif_dbg.1: probe done
# 
# modprobe clk_notif_dbg[J -r
[  512.230000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_unregister()
[  512.240000] clk_notif_dbg clk_notif_dbg.1: clk_disable()
[  512.240000] clk_notif_dbg clk_notif_dbg.1: clk_unprepare()
[  512.250000] clk_notif_dbg clk_notif_dbg.1: clk_put()
[  512.250000] clk_notif_dbg clk_notif_dbg.1: remove done
# 
# modprobe clk_notif_dbg -r[J
# modprobe clk_notif_dbg[J
[  515.290000] clk_notif_dbg clk_notif_dbg.1: clk_get()
[  515.290000] clk_notif_dbg clk_notif_dbg.1: clk_prepare()
[  515.300000] clk_notif_dbg clk_notif_dbg.1: clk_enable()
[  515.300000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_register()
[  515.310000] clk_notif_dbg clk_notif_dbg.1: probe done
# 
# modprobe clk_notif_dbg[J
# modprobe clk_notif_dbg -r[J
[  517.040000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_unregister()
[  517.040000] Unable to handle kernel paging request at virtual address 00df3008
[  517.050000] pgd = ed858000
[  517.050000] [00df3008] *pgd=00000000
[  517.060000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
[  517.060000] Modules linked in: clk_notif_dbg(O-) [last unloaded: clk_notif_dbg]
[  517.060000] CPU: 1 PID: 499 Comm: modprobe Tainted: G           O 3.10.0-rc3-00119-ga93cb29-dirty #85
[  517.060000] task: ee1e0180 ti: ee3e6000 task.ti: ee3e6000
[  517.060000] PC is at srcu_readers_seq_idx+0x48/0x84
[  517.060000] LR is at srcu_readers_seq_idx+0x60/0x84
[  517.060000] pc : [<c0052720>]    lr : [<c0052738>]    psr: 80070013
[  517.060000] sp : ee3e7d48  ip : 00000000  fp : ee3e7d6c
[  517.060000] r10: 00000000  r9 : ee3e6000  r8 : 00000000
[  517.060000] r7 : ed84fe4c  r6 : c068ec90  r5 : c068e430  r4 : 00000000
[  517.060000] r3 : 00df3000  r2 : 00000000  r1 : 00000002  r0 : 00000000
[  517.060000] Flags: Nzcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[  517.060000] Control: 18c5387d  Table: 2d85804a  DAC: 00000015
[  517.060000] Process modprobe (pid: 499, stack limit = 0xee3e6238)
[  517.060000] Stack: (0xee3e7d48 to 0xee3e8000)
[  517.060000] 7d40:                   ee3e7dd4 ed84fe4c 00000000 00000002 c045719c 00000002
[  517.060000] 7d60: ee3e7da4 ee3e7d70 c0052790 c00526e4 ee3e6000 00000002 ee3e7da4 ed84fe4c
[  517.060000] 7d80: ed84fe80 00000001 00000000 00000002 ee3e6000 00000000 ee3e7dcc ee3e7da8
[  517.060000] 7da0: c00528b0 c0052768 ed84fe4c ee3e7dd4 00000001 00000000 ed84fe54 00000002
[  517.060000] 7dc0: ee3e7e2c ee3e7dd0 c0052c30 c0052864 ee3e7dfc 00000000 c0052d38 00000000
[  517.060000] 7de0: 00000000 dead4ead ffffffff ffffffff c06d8880 00000000 00000000 c0557b5a
[  517.060000] 7e00: ee3e7e00 ee3e7e00 ed84fe04 00000000 bf008704 00000081 c000f044 00000000
[  517.060000] 7e20: ee3e7e3c ee3e7e30 c0052d14 c0052b28 ee3e7e5c ee3e7e40 c0053a08 c0052cf4
[  517.060000] 7e40: ee002dc0 ed84fe00 ee002dc0 bf008704 ee3e7e7c ee3e7e60 c0375a78 c00539ac
[  517.060000] 7e60: 60070013 ee150410 bf008700 ee150444 ee3e7e94 ee3e7e80 bf008034 c0375a08
[  517.060000] 7e80: ee150410 bf008548 ee3e7ea4 ee3e7e98 c02bb974 bf00800c ee3e7ebc ee3e7ea8
[  517.060000] 7ea0: c02b9bf8 c02bb95c ee150410 bf008548 ee3e7edc ee3e7ec0 c02ba680 c02b9b78
[  517.060000] 7ec0: 00000000 bf008548 00000000 c06af670 ee3e7efc ee3e7ee0 c02b99c4 c02ba5f0
[  517.060000] 7ee0: ee3f9840 bf008548 00000000 bee66e83 ee3e7f14 ee3e7f00 c02bace4 c02b9904
[  517.060000] 7f00: bf008588 00000000 ee3e7f24 ee3e7f18 c02bbb44 c02bac9c ee3e7f34 ee3e7f28
[  517.060000] 7f20: bf0081f8 c02bbb34 ee3e7fa4 ee3e7f38 c00835e4 bf0081f0 c005815c 00000000
[  517.060000] 7f40: bf008588 00000880 ee3e7f3c 5f6b6c63 69746f6e 62645f66 ee3e0067 ee3e7f68
[  517.060000] 7f60: c0079424 c00791a8 00000000 00000000 bee66e83 00108250 ee3e7f94 ee3e7f88
[  517.060000] 7f80: c00794c4 000792dc 00000000 00000000 bee66e83 00108250 00000000 ee3e7fa8
[  517.060000] 7fa0: c000edc0 c00833f0 00000000 bee66e83 bee66e83 00000880 00108250 00000000
[  517.060000] 7fc0: 00000000 bee66e83 00108250 00000081 00000001 bee66d74 000ffcc0 00000000
[  517.060000] 7fe0: b6e7afd0 bee669e4 000370bc b6e7afdc 60070010 bee66e83 f8ce7acf b7b173d5
[  517.060000] [<c0052720>] (srcu_readers_seq_idx+0x48/0x84) from [<c0052790>] (try_check_zero+0x34/0xfc)
[  517.060000] [<c0052790>] (try_check_zero+0x34/0xfc) from [<c00528b0>] (srcu_advance_batches+0x58/0x114)
[  517.060000] [<c00528b0>] (srcu_advance_batches+0x58/0x114) from [<c0052c30>] (__synchronize_srcu+0x114/0x1ac)
[  517.060000] [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) from [<c0052d14>] (synchronize_srcu+0x2c/0x34)
[  517.060000] [<c0052d14>] (synchronize_srcu+0x2c/0x34) from [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74)
[  517.060000] [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) from [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0)
[  517.060000] [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) from [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg])
[  517.060000] [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) from [<c02bb974>] (platform_drv_remove+0x24/0x28)
[  517.060000] [<c02bb974>] (platform_drv_remove+0x24/0x28) from [<c02b9bf8>] (__device_release_driver+0x8c/0xd4)
[  517.060000] [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) from [<c02ba680>] (driver_detach+0x9c/0xc4)
[  517.060000] [<c02ba680>] (driver_detach+0x9c/0xc4) from [<c02b99c4>] (bus_remove_driver+0xcc/0xfc)
[  517.060000] [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) from [<c02bace4>] (driver_unregister+0x54/0x78)
[  517.060000] [<c02bace4>] (driver_unregister+0x54/0x78) from [<c02bbb44>] (platform_driver_unregister+0x1c/0x20)
[  517.060000] [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) from [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg])
[  517.060000] [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) from [<c00835e4>] (SyS_delete_module+0x200/0x28c)
[  517.060000] [<c00835e4>] (SyS_delete_module+0x200/0x28c) from [<c000edc0>] (ret_fast_syscall+0x0/0x48)
[  517.060000] Code: e5973004 e7911102 e0833001 e2881002 (e7933101) 
[  517.490000] ---[ end trace 389463afcdb5d46a ]---
Segmentation fault
# 

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From mturquette at linaro.org  Fri May 31 15:14:37 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 31 May 2013 12:14:37 -0700
Subject: [PATCH 0/4] clk, mfd: u8540 clock tree definition
In-Reply-To: <20130531065532.GA10355@gmail.com>
References: <1369658492-31358-1-git-send-email-philippe.begnic.st@gmail.com>
 <20130531012509.21525.90187@quantum> <20130531065532.GA10355@gmail.com>
Message-ID: <20130531191437.21525.40759@quantum>

Quoting Lee Jones (2013-05-30 23:55:32)
> On Thu, 30 May 2013, Mike Turquette wrote:
> 
> > Quoting Philippe Begnic (2013-05-27 05:41:28)
> > > From: Philippe Begnic <philippe.begnic at st.com>
> > > 
> > > Create U8540 clock tree definitions for common clock framework
> > > 
> > 
> > The clock changes look good to me.  How did you want to merge the
> > patches?
> 
> You may as well take them through your tree Mike.
> 

Sure I can take them but it would be best to wait for an Ack from Samuel
for the MFD parts, if only so that we are coordinated.

Regards,
Mike

> > > Philippe Begnic (4):
> > >   clk: ux500: Pass clock base adresses in initcall for u8540 and u9540
> > >   mfd: db8500: Update register definition for u8540 clock
> > >   mfd: db8500: Update BML clock register for db8580
> > >   clk: ux500: Clocks definition for u8540
> > > 
> > >  arch/arm/mach-ux500/cpu.c                 |    6 +-
> > >  drivers/clk/ux500/u8540_clk.c             |  564 ++++++++++++++++++++++++++++-
> > >  drivers/clk/ux500/u9540_clk.c             |    4 +-
> > >  drivers/mfd/db8500-prcmu.c                |    1 +
> > >  drivers/mfd/dbx500-prcmu-regs.h           |    1 +
> > >  include/linux/mfd/abx500/ab8500-sysctrl.h |    4 +-
> > >  include/linux/mfd/dbx500-prcmu.h          |   12 +
> > >  include/linux/platform_data/clk-ux500.h   |    6 +-
> > >  8 files changed, 587 insertions(+), 11 deletions(-)
> > > 
> 
> -- 
> Lee Jones
> Linaro ST-Ericsson Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog


From mturquette at linaro.org  Fri May 31 15:23:06 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 31 May 2013 12:23:06 -0700
Subject: [PATCH] clk: tegra: fix clk_out parents list
In-Reply-To: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>
References: <1369641279-6894-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <20130531192306.21525.67464@quantum>

Quoting Prashant Gaikwad (2013-05-27 00:54:39)
> Number of parents for clk_out_2 and clk_out_3 was incorrectly set
> to clk_out1_parents. Even though it did not break anything since the
> size was same better to fix.
> 
> Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>

Taken into clk-next since this fix doesn't appear to fix anything.

Thanks,
Mike

> ---
>  drivers/clk/tegra/clk-tegra114.c |    4 ++--
>  drivers/clk/tegra/clk-tegra30.c  |    4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index e0ee077..6d438bb 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1602,7 +1602,7 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
>  
>         /* clk_out_2 */
>         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
> -                              ARRAY_SIZE(clk_out1_parents), 0,
> +                              ARRAY_SIZE(clk_out2_parents), 0,
>                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
>                                &clk_out_lock);
>         clks[clk_out_2_mux] = clk;
> @@ -1614,7 +1614,7 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
>  
>         /* clk_out_3 */
>         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
> -                              ARRAY_SIZE(clk_out1_parents), 0,
> +                              ARRAY_SIZE(clk_out3_parents), 0,
>                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
>                                &clk_out_lock);
>         clks[clk_out_3_mux] = clk;
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 985ad69..b62e140 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1223,7 +1223,7 @@ static void __init tegra30_pmc_clk_init(void)
>  
>         /* clk_out_2 */
>         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
> -                              ARRAY_SIZE(clk_out1_parents), 0,
> +                              ARRAY_SIZE(clk_out2_parents), 0,
>                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
>                                &clk_out_lock);
>         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
> @@ -1234,7 +1234,7 @@ static void __init tegra30_pmc_clk_init(void)
>  
>         /* clk_out_3 */
>         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
> -                              ARRAY_SIZE(clk_out1_parents), 0,
> +                              ARRAY_SIZE(clk_out3_parents), 0,
>                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
>                                &clk_out_lock);
>         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
> -- 
> 1.7.4.1


From mturquette at linaro.org  Fri May 31 15:32:11 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 31 May 2013 12:32:11 -0700
Subject: [PATCH v2 1/1] ARM : omap3 : fix wrong container_of in clock36xx.c
In-Reply-To: <1369903827-2025-1-git-send-email-jp.francois@cynove.com>
References: <1369903827-2025-1-git-send-email-jp.francois@cynove.com>
Message-ID: <20130531193211.21525.68958@quantum>

Quoting Jean-Philippe Francois (2013-05-30 01:50:27)
> omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
> to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
> have parent defined as clk_divider. Instead of using container_of to eventually get
> to the register and directly mess with the divider, change freq via clk_set_rate, 
> and let the clock framework toggle the divider value.
> Tested with  3.9 on dm3730.
> 
> Signed-off-by: Jean-Philippe Fran??ois <jp.francois at cynove.com>

Did you use git-format-patch to create this patch?  Its a bit nicer to
use that or if you just use diff then use "diff -up" or "diff -uprN"
(taken from Documentation/SubmittingPatches.txt).

Also did you test this to make sure it works?  I don't mean a boot test,
but actually disabling/re-enabling an HSDIVIDER on 3630?  The previous
code just programmed the clksel field to 1, and this code divides the
rate by 2, then restores it.  I just used that as an example in my
previous email and it needs to be verified that it works (though it
should if I remember this errata correctly).

If that testing is done and everything looks good then please add:

Acked-by: Mike Turquette <mturquette at linaro.org>

> 
> Index: b/arch/arm/mach-omap2/clock36xx.c
> ===================================================================
> --- a/arch/arm/mach-omap2/clock36xx.c
> +++ b/arch/arm/mach-omap2/clock36xx.c
> @@ -39,30 +39,25 @@
>   */
>  int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
>  {
> -       struct clk_hw_omap *parent;
> -       struct clk_hw *parent_hw;
> -       u32 dummy_v, orig_v, clksel_shift;
>         int ret;
>  
>         /* Clear PWRDN bit of HSDIVIDER */
>         ret = omap2_dflt_clk_enable(clk);
>  
> -       parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
> -       parent = to_clk_hw_omap(parent_hw);
> -
> -       /* Restore the dividers */
> +       /* kick parent's clksel register after toggling PWRDN bit */
>         if (!ret) {
> -               clksel_shift = __ffs(parent->clksel_mask);
> -               orig_v = __raw_readl(parent->clksel_reg);
> -               dummy_v = orig_v;
> -
> -               /* Write any other value different from the Read value */
> -               dummy_v ^= (1 << clksel_shift);
> -               __raw_writel(dummy_v, parent->clksel_reg);
> -
> -               /* Write the original divider */
> -               __raw_writel(orig_v, parent->clksel_reg);
> +               struct clk *parent = clk_get_parent(clk->clk);
> +               unsigned long parent_rate = clk_get_rate(parent);
> +               ret = clk_set_rate(parent, parent_rate/2);
> +               if(ret)
> +                       goto badfreq;
> +               ret = clk_set_rate(parent, parent_rate);
> +               if(ret)
> +                       goto badfreq;
>         }
> +       return ret;
>  
> + badfreq :
> +       omap2_dflt_clk_disable(clk);
>         return ret;
>  }


From mturquette at linaro.org  Fri May 31 15:52:35 2013
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 31 May 2013 12:52:35 -0700
Subject: [BUG] zynq | CCF | SRCU
In-Reply-To: <42b8bfd5-3012-4c49-b9ef-7a9beb5956f1@VA3EHSMHS041.ehs.local>
References: <42b8bfd5-3012-4c49-b9ef-7a9beb5956f1@VA3EHSMHS041.ehs.local>
Message-ID: <20130531195235.21525.64931@quantum>

Quoting S?ren Brinkmann (2013-05-31 12:12:07)
> Hi,
> 
> we recently encountered some kernel panics when we compiled one of our
> drivers as module and tested inserting/removing the module.
> Trying to debug this issue, I could reproduce it on the mainline kernel
> with a dummy module.
> 
> What happens is, that when on driver remove clk_notifier_unregister() is
> called and no other notifier for that clock is registered, the kernel
> panics.
> I'm not sure what is going wrong here. If there is a bug (and if where)
> or I'm just using the infrastructure the wrong way,... So, any hint is
> appreciated.
> 
> I attach the output from the crashing system. The stacktrace indicates a
> crash in 'srcu_readers_seq_idx()'.
> I also attach the module I used to trigger the issue and a patch on top
> of mainline commit a93cb29acaa8f75618c3f202d1cf43c231984644 which has
> the DT modifications I need to make the module find its clock and boot
> with my initramfs.
> 

Soren,

I only took a quick look at this so the following is a shot in the dark.
notifier_block->next should be protected by an RCU lock, and the way you
open-code the initialization struck me as a bit weird.  Can you change
your code to the following and let me know if it makes any difference?

static struct notifier_block nb = {
        .notifier_call = clk_notif_dbg_cb;
};

static int clk_notif_dbg_cb(struct notifier_block *nb,
                unsigned long event, void *data)
{
        pr_info("clk_notif_dbg_cb\n");

        return NOTIFY_OK;
}

static int clk_notif_dbg_probe(struct platform_device *pdev)
{
        ...
        if (clk_notifier_register(clk, &nb))
                dev_warn(&pdev->dev, "clk_notifier_register failed\n");
        ...


That is a small difference, but that style of initializing the
notifier_block has always worked for me when using clk rate-change
notifiers.  However I'm sure the bug you mention is far more evil and
nefarious than that ;-)

Regards,
Mike

> 
>         Thanks,
>         S?ren


From plagnioj at jcrosoft.com  Fri May 31 15:48:38 2013
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 May 2013 21:48:38 +0200
Subject: Jean-Christophe PLAGNIOL-VILLARD off until 10th of June
Message-ID: <20130531194838.GI23653@game.jcrosoft.org>

Hi,

	I'm Traveling back to France next week to go to my sister weeding
	so I'll be off tonight and will start to be back end of next week
	And fully back the 10th of June.

	If any urgent matter for FBDEV please ping Tomi and for AT91 ping
	Nicolas

Best Regards,
J.


From john.stultz at linaro.org  Fri May 31 16:40:46 2013
From: john.stultz at linaro.org (John Stultz)
Date: Fri, 31 May 2013 13:40:46 -0700
Subject: [PATCH 5/4] sched: Make ARM's sched_clock generic for all
 architectures
In-Reply-To: <1367369675-13535-1-git-send-email-sboyd@codeaurora.org>
References: <1366417746-24990-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <51A90ACE.7070906@linaro.org>

On 04/30/2013 05:54 PM, Stephen Boyd wrote:
> Here's the patch to make sched_clock generic. I didn't know
> where to put it so I just made a new file in kernel/sched
> for now.
>
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>

Hey Stephen,
     Baruch just asked a question about moving arm's sched_clock.c to be 
generic, and it sounded familiar, so I dug around and found this mail 
from a few months ago.

Just wanted to follow up and see what the status is with this? Is this 
queued somewhere already?

thanks
-john



From arnd at arndb.de  Fri May 31 16:41:16 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 22:41:16 +0200
Subject: [PATCH] ARM: pxa: propagate errors from regulator_enable() to pxamci
Message-ID: <2578085.T8WORaQtxA@wuerfel>

The em_x270_mci_setpower() and em_x270_usb_hub_init() functions
call regulator_enable(), which may return an error that must
be checked.

This changes the em_x270_usb_hub_init() function to bail out
if it fails, and changes the pxamci_platform_data->setpower
callback so that the a failed em_x270_mci_setpower call
can be propagated by the pxamci driver into the mmc core.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Mike Rapoport <mike at compulab.co.il>
Cc: Paul Gortmaker <paul.gortmaker at windriver.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Chris Ball <cjb at laptop.org>

diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 446563a..1df06c2 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -477,16 +477,24 @@ static int em_x270_usb_hub_init(void)
 	/* USB Hub power-on and reset */
 	gpio_direction_output(usb_hub_reset, 1);
 	gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
-	regulator_enable(em_x270_usb_ldo);
+	err = regulator_enable(em_x270_usb_ldo);
+	if (err)
+		goto err_free_rst_gpio;
+
 	gpio_set_value(usb_hub_reset, 0);
 	gpio_set_value(usb_hub_reset, 1);
 	regulator_disable(em_x270_usb_ldo);
-	regulator_enable(em_x270_usb_ldo);
+	if (err)
+		goto err_free_rst_gpio;
+
+	err = regulator_enable(em_x270_usb_ldo);
 	gpio_set_value(usb_hub_reset, 0);
 	gpio_set_value(GPIO9_USB_VBUS_EN, 1);
 
 	return 0;
 
+err_free_rst_gpio:
+	gpio_free(usb_hub_reset);
 err_free_vbus_gpio:
 	gpio_free(GPIO9_USB_VBUS_EN);
 err_free_usb_ldo:
@@ -592,7 +600,7 @@ err_irq:
 	return err;
 }
 
-static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
+static int em_x270_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
@@ -600,10 +608,11 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
 		int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
 
 		regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
-		regulator_enable(em_x270_sdio_ldo);
+		return regulator_enable(em_x270_sdio_ldo);
 	} else {
 		regulator_disable(em_x270_sdio_ldo);
 	}
+	return 0;
 }
 
 static void em_x270_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 7a12c1b..4c72fa6 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -408,7 +408,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
 	return err;
 }
 
-static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
+static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
@@ -420,6 +420,7 @@ static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
 		printk(KERN_DEBUG "%s: off\n", __func__);
 		MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
 	}
+	return 0;
 }
 
 static void mainstone_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index fb7f1d1..13e5b00 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -335,7 +335,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
 	return err;
 }
 
-static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
+static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data *p_d = dev->platform_data;
 	u8 val;
@@ -348,6 +348,7 @@ static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
 		val &= ~PCM990_CTRL_MMC2PWR;
 
 	pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
+	return 0;
 }
 
 static void pcm990_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f..cb374c2 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -258,7 +258,7 @@ err_free_2:
 	return err;
 }
 
-static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
+static int poodle_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
@@ -270,6 +270,8 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
 		gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
 		gpio_set_value(POODLE_GPIO_SD_PWR, 0);
 	}
+
+	return 0;
 }
 
 static void poodle_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c..49bfcd7 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -597,7 +597,7 @@ static inline void spitz_spi_init(void) {}
  * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
  * give the card a chance to fully insert/eject.
  */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
@@ -605,6 +605,8 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
 		spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
 	else
 		spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
+
+	return 0;
 }
 
 static struct pxamci_platform_data spitz_mci_platform_data = {
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 88fde43..62aea3e 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -734,9 +734,10 @@ static int stargate2_mci_init(struct device *dev,
  *
  * Very simple control. Either it is on or off and is controlled by
  * a gpio pin */
-static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
+static int stargate2_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
+	return 0;
 }
 
 static void stargate2_mci_exit(struct device *dev, void *data)
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 847b199..2c5a91b 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -128,7 +128,7 @@ static inline int pxamci_set_power(struct pxamci_host *host,
 			       !!on ^ host->pdata->gpio_power_invert);
 	}
 	if (!host->vcc && host->pdata && host->pdata->setpower)
-		host->pdata->setpower(mmc_dev(host->mmc), vdd);
+		return host->pdata->setpower(mmc_dev(host->mmc), vdd);
 
 	return 0;
 }
diff --git a/include/linux/platform_data/mmc-pxamci.h b/include/linux/platform_data/mmc-pxamci.h
index 9eb515b..1706b35 100644
--- a/include/linux/platform_data/mmc-pxamci.h
+++ b/include/linux/platform_data/mmc-pxamci.h
@@ -12,7 +12,7 @@ struct pxamci_platform_data {
 	unsigned long detect_delay_ms;		/* delay in millisecond before detecting cards after interrupt */
 	int (*init)(struct device *, irq_handler_t , void *);
 	int (*get_ro)(struct device *);
-	void (*setpower)(struct device *, unsigned int);
+	int (*setpower)(struct device *, unsigned int);
 	void (*exit)(struct device *, void *);
 	int gpio_card_detect;			/* gpio detecting card insertion */
 	int gpio_card_ro;			/* gpio detecting read only toggle */



From arnd at arndb.de  Fri May 31 16:47:04 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 22:47:04 +0200
Subject: [PATCH] ARM: ux500: avoid warning in ux500_read_asicid
Message-ID: <2475820.dXNmmAuTaP@wuerfel>

phys_addr_t may be 64 bit, which causes this harmless warning
in ux500_read_asicid:

arch/arm/mach-ux500/id.c: In function 'ux500_read_asicid':
arch/arm/include/asm/io.h:159:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
 #define IOMEM(x) ((void __force __iomem *)(x))
                   ^
arch/arm/mach-ux500/id.c:40:9: note: in expansion of macro 'readl'
  return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));

We can solve this in a nicer way by making UX500_VIRT_ROM have a proper
type to start with and calculating the address using pointer arithmetic.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Linus Walleij <linus.walleij at linaro.org>

diff --git a/arch/arm/mach-ux500/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h
index b2d7a0b..bb4cc41 100644
--- a/arch/arm/mach-ux500/db8500-regs.h
+++ b/arch/arm/mach-ux500/db8500-regs.h
@@ -184,7 +184,7 @@
 #define U8500_IO_VIRTUAL	0xf0000000
 #define U8500_IO_PHYSICAL	0xa0000000
 /* This is where we map in the ROM to check ASIC IDs */
-#define UX500_VIRT_ROM		0xf0000000
+#define UX500_VIRT_ROM		IOMEM(0xf0000000)
 
 /* This macro is used in assembly, so no cast */
 #define IO_ADDRESS(x)           \
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 0d33d1a..392f2fd 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -21,11 +21,11 @@
 
 struct dbx500_asic_id dbx500_id;
 
-static unsigned int ux500_read_asicid(phys_addr_t addr)
+static unsigned int __init ux500_read_asicid(phys_addr_t addr)
 {
 	phys_addr_t base = addr & ~0xfff;
 	struct map_desc desc = {
-		.virtual	= UX500_VIRT_ROM,
+		.virtual	= (unsigned long)UX500_VIRT_ROM,
 		.pfn		= __phys_to_pfn(base),
 		.length		= SZ_16K,
 		.type		= MT_DEVICE,
@@ -37,7 +37,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr)
 	local_flush_tlb_all();
 	flush_cache_all();
 
-	return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
+	return readl(UX500_VIRT_ROM + (addr & 0xfff));
 }
 
 static void ux500_print_soc_info(unsigned int asicid)



From arnd at arndb.de  Fri May 31 16:48:34 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 22:48:34 +0200
Subject: [PATCH] ARM: pxa: propagate errors from regulator_enable() to
 pxamci
In-Reply-To: <2578085.T8WORaQtxA@wuerfel>
References: <2578085.T8WORaQtxA@wuerfel>
Message-ID: <2230532.ij37rWB9OD@wuerfel>

[using Mark's proper address. I did the patch a while ago before it was changed]

On Friday 31 May 2013 22:41:16 Arnd Bergmann wrote:
> The em_x270_mci_setpower() and em_x270_usb_hub_init() functions
> call regulator_enable(), which may return an error that must
> be checked.
> 
> This changes the em_x270_usb_hub_init() function to bail out
> if it fails, and changes the pxamci_platform_data->setpower
> callback so that the a failed em_x270_mci_setpower call
> can be propagated by the pxamci driver into the mmc core.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Mike Rapoport <mike at compulab.co.il>
> Cc: Paul Gortmaker <paul.gortmaker at windriver.com>
> Cc: Mark Brown <broonie at kernel.org>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Chris Ball <cjb at laptop.org>
> 
> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
> index 446563a..1df06c2 100644
> --- a/arch/arm/mach-pxa/em-x270.c
> +++ b/arch/arm/mach-pxa/em-x270.c
> @@ -477,16 +477,24 @@ static int em_x270_usb_hub_init(void)
>  	/* USB Hub power-on and reset */
>  	gpio_direction_output(usb_hub_reset, 1);
>  	gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
> -	regulator_enable(em_x270_usb_ldo);
> +	err = regulator_enable(em_x270_usb_ldo);
> +	if (err)
> +		goto err_free_rst_gpio;
> +
>  	gpio_set_value(usb_hub_reset, 0);
>  	gpio_set_value(usb_hub_reset, 1);
>  	regulator_disable(em_x270_usb_ldo);
> -	regulator_enable(em_x270_usb_ldo);
> +	if (err)
> +		goto err_free_rst_gpio;
> +
> +	err = regulator_enable(em_x270_usb_ldo);
>  	gpio_set_value(usb_hub_reset, 0);
>  	gpio_set_value(GPIO9_USB_VBUS_EN, 1);
>  
>  	return 0;
>  
> +err_free_rst_gpio:
> +	gpio_free(usb_hub_reset);
>  err_free_vbus_gpio:
>  	gpio_free(GPIO9_USB_VBUS_EN);
>  err_free_usb_ldo:
> @@ -592,7 +600,7 @@ err_irq:
>  	return err;
>  }
>  
> -static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
> +static int em_x270_mci_setpower(struct device *dev, unsigned int vdd)
>  {
>  	struct pxamci_platform_data* p_d = dev->platform_data;
>  
> @@ -600,10 +608,11 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
>  		int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
>  
>  		regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
> -		regulator_enable(em_x270_sdio_ldo);
> +		return regulator_enable(em_x270_sdio_ldo);
>  	} else {
>  		regulator_disable(em_x270_sdio_ldo);
>  	}
> +	return 0;
>  }
>  
>  static void em_x270_mci_exit(struct device *dev, void *data)
> diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
> index 7a12c1b..4c72fa6 100644
> --- a/arch/arm/mach-pxa/mainstone.c
> +++ b/arch/arm/mach-pxa/mainstone.c
> @@ -408,7 +408,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
>  	return err;
>  }
>  
> -static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
> +static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
>  {
>  	struct pxamci_platform_data* p_d = dev->platform_data;
>  
> @@ -420,6 +420,7 @@ static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
>  		printk(KERN_DEBUG "%s: off\n", __func__);
>  		MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
>  	}
> +	return 0;
>  }
>  
>  static void mainstone_mci_exit(struct device *dev, void *data)
> diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
> index fb7f1d1..13e5b00 100644
> --- a/arch/arm/mach-pxa/pcm990-baseboard.c
> +++ b/arch/arm/mach-pxa/pcm990-baseboard.c
> @@ -335,7 +335,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
>  	return err;
>  }
>  
> -static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
> +static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
>  {
>  	struct pxamci_platform_data *p_d = dev->platform_data;
>  	u8 val;
> @@ -348,6 +348,7 @@ static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
>  		val &= ~PCM990_CTRL_MMC2PWR;
>  
>  	pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
> +	return 0;
>  }
>  
>  static void pcm990_mci_exit(struct device *dev, void *data)
> diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
> index 50ccd5f..cb374c2 100644
> --- a/arch/arm/mach-pxa/poodle.c
> +++ b/arch/arm/mach-pxa/poodle.c
> @@ -258,7 +258,7 @@ err_free_2:
>  	return err;
>  }
>  
> -static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
> +static int poodle_mci_setpower(struct device *dev, unsigned int vdd)
>  {
>  	struct pxamci_platform_data* p_d = dev->platform_data;
>  
> @@ -270,6 +270,8 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
>  		gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
>  		gpio_set_value(POODLE_GPIO_SD_PWR, 0);
>  	}
> +
> +	return 0;
>  }
>  
>  static void poodle_mci_exit(struct device *dev, void *data)
> diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
> index 362726c..49bfcd7 100644
> --- a/arch/arm/mach-pxa/spitz.c
> +++ b/arch/arm/mach-pxa/spitz.c
> @@ -597,7 +597,7 @@ static inline void spitz_spi_init(void) {}
>   * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
>   * give the card a chance to fully insert/eject.
>   */
> -static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
> +static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
>  {
>  	struct pxamci_platform_data* p_d = dev->platform_data;
>  
> @@ -605,6 +605,8 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
>  		spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
>  	else
>  		spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
> +
> +	return 0;
>  }
>  
>  static struct pxamci_platform_data spitz_mci_platform_data = {
> diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
> index 88fde43..62aea3e 100644
> --- a/arch/arm/mach-pxa/stargate2.c
> +++ b/arch/arm/mach-pxa/stargate2.c
> @@ -734,9 +734,10 @@ static int stargate2_mci_init(struct device *dev,
>   *
>   * Very simple control. Either it is on or off and is controlled by
>   * a gpio pin */
> -static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
> +static int stargate2_mci_setpower(struct device *dev, unsigned int vdd)
>  {
>  	gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
> +	return 0;
>  }
>  
>  static void stargate2_mci_exit(struct device *dev, void *data)
> diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
> index 847b199..2c5a91b 100644
> --- a/drivers/mmc/host/pxamci.c
> +++ b/drivers/mmc/host/pxamci.c
> @@ -128,7 +128,7 @@ static inline int pxamci_set_power(struct pxamci_host *host,
>  			       !!on ^ host->pdata->gpio_power_invert);
>  	}
>  	if (!host->vcc && host->pdata && host->pdata->setpower)
> -		host->pdata->setpower(mmc_dev(host->mmc), vdd);
> +		return host->pdata->setpower(mmc_dev(host->mmc), vdd);
>  
>  	return 0;
>  }
> diff --git a/include/linux/platform_data/mmc-pxamci.h b/include/linux/platform_data/mmc-pxamci.h
> index 9eb515b..1706b35 100644
> --- a/include/linux/platform_data/mmc-pxamci.h
> +++ b/include/linux/platform_data/mmc-pxamci.h
> @@ -12,7 +12,7 @@ struct pxamci_platform_data {
>  	unsigned long detect_delay_ms;		/* delay in millisecond before detecting cards after interrupt */
>  	int (*init)(struct device *, irq_handler_t , void *);
>  	int (*get_ro)(struct device *);
> -	void (*setpower)(struct device *, unsigned int);
> +	int (*setpower)(struct device *, unsigned int);
>  	void (*exit)(struct device *, void *);
>  	int gpio_card_detect;			/* gpio detecting card insertion */
>  	int gpio_card_ro;			/* gpio detecting read only toggle */


From nicolas.ferre at atmel.com  Fri May 31 16:52:37 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 22:52:37 +0200
Subject: [PATCH v2] ARM: at91/dt: add pinctrl definition for at91 tc blocks
In-Reply-To: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>
References: <1369389956-30466-1-git-send-email-b.brezillon@overkiz.com>
Message-ID: <1370033557-17114-1-git-send-email-nicolas.ferre@atmel.com>

From: Boris BREZILLON <b.brezillon at overkiz.com>

This patch adds pinctrl configurations for at91 Timer Counter blocks.
These pin definitions can be referenced by "atmel,tcb-pwm" devices to
setup pins as PWM output for instance.

Signed-off-by: Boris BREZILLON <b.brezillon at overkiz.com>
[nicolas.ferre at atmel.com: switch to pinctrl pre-processor macros]
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Hi Boris,

Here is your patch modified with pinctrl macros used.
I plan to stack it on top of our at91-3.11-dt branch now.

Thanks and best regards,

Nicolas Ferre

 arch/arm/boot/dts/at91rm9200.dtsi  | 76 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9260.dtsi | 76 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi | 38 +++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi | 76 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi | 76 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  | 76 ++++++++++++++++++++++++++++++++++++++
 6 files changed, 418 insertions(+)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4aad0d9..b91cf78 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -398,6 +398,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index de571d9..899a7cf 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -355,6 +355,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d9cf51a..ff63811 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -324,6 +324,44 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index f0091af..faec17d 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -344,6 +344,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index d12da33..3166e1d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -285,6 +285,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 5635064..e77106e 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -414,6 +414,82 @@
 					};
 				};
 
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
-- 
1.8.0



From nicolas.ferre at atmel.com  Fri May 31 16:54:00 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 22:54:00 +0200
Subject: [PATCH 0/2] ARM: dts: add watchdog device tree node in at91 dts
 files
In-Reply-To: <CACQ1gAjF=L+tVcJc3QMv7HEYcny2y-HcDLGJ5N7XbM=_vL+dFQ@mail.gmail.com>
References: <1369969744-3428-1-git-send-email-wenyou.yang@atmel.com>
 <1369969893-7992-1-git-send-email-wenyou.yang@atmel.com>
 <CACQ1gAjF=L+tVcJc3QMv7HEYcny2y-HcDLGJ5N7XbM=_vL+dFQ@mail.gmail.com>
Message-ID: <51A90DE8.1010009@atmel.com>

On 31/05/2013 11:39, Richard Genoud :
> 2013/5/31 Wenyou Yang <wenyou.yang at atmel.com>:
>> Hello,
>>
>> The patches is to add watchdog device tree node for at91 SoC and board dts files.
>>
>> Since the watchdog is disabled in the at91bootstrap with default configuration,
>> if you want to use the watchdog in the kernel, you must make sure the watchdog
>> doesn't be disabled in the at91bootstrap.
>>
>> It is tested on at91sam9g20ek, at91sam9263ek, at91sam9g25ek
>> using Documentation/watchdog/src/watchdog-simple.c.
>>
>> It is based on v3.10-rc3, tested on linux-watchdog git tree as well.
>>
>> Best Regards,
>> Wenyou Yang
>>
>> Wenyou Yang (2):
>>    ARM: dts: add the watchdog nodes for at91 SoC
>>    ARM: dts: add the watchdog nodes for at91 boards
>>
>>   arch/arm/boot/dts/at91sam9263ek.dts         |    4 ++++
>>   arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    4 ++++
>>   arch/arm/boot/dts/at91sam9m10g45ek.dts      |    4 ++++
>>   arch/arm/boot/dts/at91sam9n12.dtsi          |    6 ++++++
>>   arch/arm/boot/dts/at91sam9n12ek.dts         |    4 ++++
>>   arch/arm/boot/dts/at91sam9x5.dtsi           |    6 ++++++
>>   arch/arm/boot/dts/at91sam9x5ek.dtsi         |    4 ++++
>>   7 files changed, 32 insertions(+)
>>
>> --
>> 1.7.9.5
>>
>
> Those patches haven been floating around from quite some time.
> Let's merge them !
>
> Tested on sam9g35, v3.10-rc2
>
> Tested-by: Richard Genoud <richard.genoud at gmail.com>

Both patches added to the at91-3.11-dt branch. Thanks!

Bye,
-- 
Nicolas Ferre


From khilman at linaro.org  Fri May 31 16:56:34 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 13:56:34 -0700
Subject: [PATCH] mfd: twl-core: convert to module_init()
Message-ID: <1370033794-5357-1-git-send-email-khilman@linaro.org>

There's no reason for twl-core to be subsys_inicall anymore.  Anything
using twl that early needs a rethink, or deferred probe changes.

Boot tested and RTC wake tested (via TWL RTC) on OMAP platforms:
3530/Beagle, 3730/Beagle-xM, 3530/Overo, 3730/Overo-STORM, 4430/Panda,
4460/Panda-ES.

Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
 drivers/mfd/twl-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 89ab4d9..7749b9e 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1309,7 +1309,7 @@ static int __init twl_init(void)
 {
 	return i2c_add_driver(&twl_driver);
 }
-subsys_initcall(twl_init);
+module_init(twl_init);
 
 static void __exit twl_exit(void)
 {
-- 
1.8.2



From nicolas.ferre at atmel.com  Fri May 31 16:56:52 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 22:56:52 +0200
Subject: [PATCH 0/5] ARM: at91: Calao USB-A926x switch completyl to dt
 and drop board file
In-Reply-To: <20130526153037.GQ24476@game.jcrosoft.org>
References: <20130526153037.GQ24476@game.jcrosoft.org>
Message-ID: <51A90E94.6010404@atmel.com>

On 26/05/2013 17:30, Jean-Christophe PLAGNIOL-VILLARD :
> Hi,
>
> 	The Follwing patch serie finish to swtich the Calao USB-A926x to DT
> 	and drop the board file.
>
> 	This is the first boards to be drop on at91
>
> The following changes since commit 24577c1b3ebf3eab6465bb112a6265e87400163e:
>
>    ARM: at91: dt: sam9260: add i2c gpio pinctrl (2013-05-26 16:56:39 +0800)
>
> are available in the git repository at:
>
>    git://github.com/at91linux/linux-at91.git j/for-3.11-calao-dt

Whole series added to the at91-3.11-dt branch.

Thanks for this move forward!

Bye,

> for you to fetch changes up to c3ea1d2cc2f543ee0646a75890e1a7be5dd82c0b:
>
>    ARM: at91: drop non DT: Calao USB-A96x (2013-05-26 23:32:23 +0800)
>
> ----------------------------------------------------------------
> Jean-Christophe PLAGNIOL-VILLARD (5):
>        ARM: at91: dt: usb-a9260: update shutdown controller
>        ARM: at91: dt: usb-a9263: update shutdown controller
>        ARM: at91: dt: usb-a9263: add dataflash support
>        ARM: at91: dt: add Calao USB-A9G20 low power version
>        ARM: at91: drop non DT: Calao USB-A96x
>
>   arch/arm/boot/dts/Makefile                  |    1 +
>   arch/arm/boot/dts/usb_a9260.dts             |    9 ++++++
>   arch/arm/boot/dts/usb_a9263.dts             |   14 +++++++++
>   arch/arm/boot/dts/usb_a9g20.dts             |   18 +----------
>   arch/arm/boot/dts/usb_a9g20_common.dtsi     |   27 ++++++++++++++++
>   arch/arm/boot/dts/usb_a9g20_lpw.dts         |   31 ++++++++++++++++++
>   arch/arm/configs/at91_dt_defconfig          |    2 ++
>   arch/arm/configs/at91sam9260_9g20_defconfig |    1 -
>   arch/arm/configs/at91sam9263_defconfig      |    1 -
>   arch/arm/mach-at91/Kconfig.non_dt           |   19 -----------
>   arch/arm/mach-at91/Makefile                 |    3 --
>   arch/arm/mach-at91/board-usb-a926x.c        |  384 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
>   12 files changed, 85 insertions(+), 425 deletions(-)
>   create mode 100644 arch/arm/boot/dts/usb_a9g20_common.dtsi
>   create mode 100644 arch/arm/boot/dts/usb_a9g20_lpw.dts
>   delete mode 100644 arch/arm/mach-at91/board-usb-a926x.c
>
> Best Regards,
> J.
>


-- 
Nicolas Ferre


From arnd at arndb.de  Fri May 31 16:59:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 22:59:44 +0200
Subject: [PATCH] clocksource: kona: adapt to CLOCKSOURCE_OF_DECLARE change
Message-ID: <3174210.ZivUajNGev@wuerfel>

The CLOCKSOURCE_OF_DECLARE functions now take a device_node pointer
as their argument, as of the clksrc/cleanup branch in arm-soc.
This patch adapts the bcm_kona_timer driver to the new interface.

This causes an annoying but harmless build-time warning, it would
be nice to have this fixed in 3.10.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Christian Daudt <csd at broadcom.com>
Cc: John Stultz <john.stultz at linaro.org>
---
diff --git a/drivers/clocksource/bcm_kona_timer.c b/drivers/clocksource/bcm_kona_timer.c
index 350f493..ba3d859 100644
--- a/drivers/clocksource/bcm_kona_timer.c
+++ b/drivers/clocksource/bcm_kona_timer.c
@@ -103,16 +103,10 @@ static const struct of_device_id bcm_timer_ids[] __initconst = {
 	{},
 };
 
-static void __init kona_timers_init(void)
+static void __init kona_timers_init(struct device_node *node)
 {
-	struct device_node *node;
 	u32 freq;
 
-	node = of_find_matching_node(NULL, bcm_timer_ids);
-
-	if (!node)
-		panic("No timer");
-
 	if (!of_property_read_u32(node, "clock-frequency", &freq))
 		arch_timer_rate = freq;
 	else
@@ -199,13 +193,12 @@ static struct irqaction kona_timer_irq = {
 	.handler = kona_timer_interrupt,
 };
 
-static void __init kona_timer_init(void)
+static void __init kona_timer_init(struct device_node *node)
 {
-	kona_timers_init();
+	kona_timers_init(node);
 	kona_timer_clockevents_init();
 	setup_irq(timers.tmr_irq, &kona_timer_irq);
 	kona_timer_set_next_event((arch_timer_rate / HZ), NULL);
 }
 
-CLOCKSOURCE_OF_DECLARE(bcm_kona, "bcm,kona-timer",
-	kona_timer_init);
+CLOCKSOURCE_OF_DECLARE(bcm_kona, "bcm,kona-timer", kona_timer_init);



From soren.brinkmann at xilinx.com  Fri May 31 17:10:05 2013
From: soren.brinkmann at xilinx.com (=?utf-8?B?U8O2cmVu?= Brinkmann)
Date: Fri, 31 May 2013 14:10:05 -0700
Subject: [BUG] zynq | CCF | SRCU
In-Reply-To: <20130531195235.21525.64931@quantum>
References: <42b8bfd5-3012-4c49-b9ef-7a9beb5956f1@VA3EHSMHS041.ehs.local>
 <20130531195235.21525.64931@quantum>
Message-ID: <09ee3179-5100-4c7c-bf3d-0a659a3e7633@DB8EHSMHS026.ehs.local>

Hi Mike,

On Fri, May 31, 2013 at 12:52:35PM -0700, Mike Turquette wrote:
> Quoting S?ren Brinkmann (2013-05-31 12:12:07)
> > Hi,
> > 
> > we recently encountered some kernel panics when we compiled one of our
> > drivers as module and tested inserting/removing the module.
> > Trying to debug this issue, I could reproduce it on the mainline kernel
> > with a dummy module.
> > 
> > What happens is, that when on driver remove clk_notifier_unregister() is
> > called and no other notifier for that clock is registered, the kernel
> > panics.
> > I'm not sure what is going wrong here. If there is a bug (and if where)
> > or I'm just using the infrastructure the wrong way,... So, any hint is
> > appreciated.
> > 
> > I attach the output from the crashing system. The stacktrace indicates a
> > crash in 'srcu_readers_seq_idx()'.
> > I also attach the module I used to trigger the issue and a patch on top
> > of mainline commit a93cb29acaa8f75618c3f202d1cf43c231984644 which has
> > the DT modifications I need to make the module find its clock and boot
> > with my initramfs.
> > 
> 
> Soren,
> 
> I only took a quick look at this so the following is a shot in the dark.
> notifier_block->next should be protected by an RCU lock, and the way you
> open-code the initialization struck me as a bit weird.  Can you change
> your code to the following and let me know if it makes any difference?
> 
> static struct notifier_block nb = {
>         .notifier_call = clk_notif_dbg_cb;
> };
> 
> static int clk_notif_dbg_cb(struct notifier_block *nb,
>                 unsigned long event, void *data)
> {
>         pr_info("clk_notif_dbg_cb\n");
> 
>         return NOTIFY_OK;
> }
> 
> static int clk_notif_dbg_probe(struct platform_device *pdev)
> {
>         ...
>         if (clk_notifier_register(clk, &nb))
>                 dev_warn(&pdev->dev, "clk_notifier_register failed\n");
>         ...
> 
> 
> That is a small difference, but that style of initializing the
> notifier_block has always worked for me when using clk rate-change
> notifiers.  However I'm sure the bug you mention is far more evil and
> nefarious than that ;-)
I changed the module like this (I hope this is what you suggested):
	8,9d7
	< static struct notifier_block nb;
	< 
	17a16,19
	> static struct notifier_block nb = {
	>       .notifier_call = clk_notif_dbg_cb
	> };
	> 
	20,22d21
	<       nb.next = NULL;
	<       nb.notifier_call = clk_notif_dbg_cb;
	<

The result is the same. It crashes in srcu_readers_seq_idx().

	Thanks,
	S?ren




From nicolas.ferre at atmel.com  Fri May 31 17:17:19 2013
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 May 2013 23:17:19 +0200
Subject: [GIT PULL] at91: Device Tree update for 3.11 #1
Message-ID: <1370035039-17757-1-git-send-email-nicolas.ferre@atmel.com>

Arnd, Olof,

This is the pull-request for DT update on AT91. As said earlier, and like any
other patches that will be produced for 3.11, it is based on material already
included in arm-soc/at91/cleanup branch.

A little conflict may appear while merging with already-sent pull-request for
the USBA driver ([GIT PULL] at91: USBA DT support for 3.11). I have resolved
the conflict and pushed the result branch as: at91-at91-3.11-driver-usba-dt+resolved

Thanks, best regards,

The following changes since commit b3f442b0eedbc20b5ce3f4a96530588d14901199:

  ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-dt

for you to fetch changes up to 028633c238f91dc113520a7ad25d37b2ba9068af:

  ARM: at91/dt: add pinctrl definition for at91 tc blocks (2013-05-31 22:40:37 +0200)

----------------------------------------------------------------
Big DT-centric update for AT91:
- Calao boards update, removal of one board C file and
  associated defconfig, Kconfig Makefile lines
- several Acme boards updates
- addition of watchdog, uart and pinctrl descriptions for
  several products
- modification of RTC compatible string for 9x5 family

----------------------------------------------------------------
Boris BREZILLON (1):
      ARM: at91/dt: add pinctrl definition for at91 tc blocks

Douglas Gilbert (1):
      ARM: at91: add Acme Systems Fox G20 board

Jean-Christophe PLAGNIOL-VILLARD (6):
      ARM: at91: dt: sam9260: add i2c gpio pinctrl
      ARM: at91: dt: usb-a9260: update shutdown controller
      ARM: at91: dt: usb-a9263: update shutdown controller
      ARM: at91: dt: usb-a9263: add dataflash support
      ARM: at91: dt: add Calao USB-A9G20 low power version
      ARM: at91: drop non DT: Calao USB-A96x

Nicolas Ferre (5):
      ARM: at91: at91sam9x5 RTC is not compatible with at91rm9200 one
      ARM: at91/at91-ariag25.dts: add RTC node
      ARM: at91/at91sam9x5.dtsi: add UART0/1 nodes
      ARM: at91/at91-ariag25.dts: UART0/1 nodes are disabled
      ARM: at91: switch Fox G20 board .dts to pre-processor defines

Wenyou Yang (2):
      ARM: at91/dtsi: add the watchdog nodes for at91 SoC
      ARM: at91/dts: add the watchdog nodes for at91 boards

 arch/arm/boot/dts/Makefile                  |   2 +
 arch/arm/boot/dts/at91-ariag25.dts          |  21 +-
 arch/arm/boot/dts/at91-foxg20.dts           | 157 ++++++++++++
 arch/arm/boot/dts/at91rm9200.dtsi           |  76 ++++++
 arch/arm/boot/dts/at91sam9260.dtsi          |  86 +++++++
 arch/arm/boot/dts/at91sam9263.dtsi          |  38 +++
 arch/arm/boot/dts/at91sam9263ek.dts         |   4 +
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   4 +
 arch/arm/boot/dts/at91sam9g45.dtsi          |  76 ++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |   4 +
 arch/arm/boot/dts/at91sam9n12.dtsi          |  82 ++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |   4 +
 arch/arm/boot/dts/at91sam9x5.dtsi           | 102 +++++++-
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |   4 +
 arch/arm/boot/dts/usb_a9260.dts             |   9 +
 arch/arm/boot/dts/usb_a9263.dts             |  14 +
 arch/arm/boot/dts/usb_a9g20.dts             |  18 +-
 arch/arm/boot/dts/usb_a9g20_common.dtsi     |  27 ++
 arch/arm/boot/dts/usb_a9g20_lpw.dts         |  31 +++
 arch/arm/configs/at91_dt_defconfig          |   2 +
 arch/arm/configs/at91sam9260_9g20_defconfig |   1 -
 arch/arm/configs/at91sam9263_defconfig      |   1 -
 arch/arm/mach-at91/Kconfig.non_dt           |  19 --
 arch/arm/mach-at91/Makefile                 |   3 -
 arch/arm/mach-at91/board-usb-a926x.c        | 384 ----------------------------
 25 files changed, 737 insertions(+), 432 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91-foxg20.dts
 create mode 100644 arch/arm/boot/dts/usb_a9g20_common.dtsi
 create mode 100644 arch/arm/boot/dts/usb_a9g20_lpw.dts
 delete mode 100644 arch/arm/mach-at91/board-usb-a926x.c

-- 
Nicolas Ferre


From tony at atomide.com  Fri May 31 17:20:04 2013
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 May 2013 14:20:04 -0700
Subject: [PATCH] mfd: twl-core: convert to module_init()
In-Reply-To: <1370033794-5357-1-git-send-email-khilman@linaro.org>
References: <1370033794-5357-1-git-send-email-khilman@linaro.org>
Message-ID: <20130531212003.GR6467@atomide.com>

* Kevin Hilman <khilman at linaro.org> [130531 14:02]:
> There's no reason for twl-core to be subsys_inicall anymore.  Anything
> using twl that early needs a rethink, or deferred probe changes.
> 
> Boot tested and RTC wake tested (via TWL RTC) on OMAP platforms:
> 3530/Beagle, 3730/Beagle-xM, 3530/Overo, 3730/Overo-STORM, 4430/Panda,
> 4460/Panda-ES.
> 
> Cc: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Kevin Hilman <khilman at linaro.org>

Totally agree:

Acked-by: Tony Lindgren <tony at atomide.com>

> ---
>  drivers/mfd/twl-core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
> index 89ab4d9..7749b9e 100644
> --- a/drivers/mfd/twl-core.c
> +++ b/drivers/mfd/twl-core.c
> @@ -1309,7 +1309,7 @@ static int __init twl_init(void)
>  {
>  	return i2c_add_driver(&twl_driver);
>  }
> -subsys_initcall(twl_init);
> +module_init(twl_init);
>  
>  static void __exit twl_exit(void)
>  {
> -- 
> 1.8.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


From arnd at arndb.de  Fri May 31 17:30:29 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 23:30:29 +0200
Subject: [PATCH 1/3] ARM: at91: dt: add header to define at_hdmac
 configuration
In-Reply-To: <1369930103-11963-2-git-send-email-ludovic.desroches@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <201305312330.29364.arnd@arndb.de>

On Thursday 30 May 2013, ludovic.desroches at atmel.com wrote:
> +/*
> + * Source and/or destination peripheral ID
> + */
> +#define AT91_DMA_CFG_PER_ID_MASK       (0xff)
> +#define AT91_DMA_CFG_PER_ID(id)                (id & AT91_DMA_CFG_PER_ID_MASK)
> +

I'm a little worried about macros like this one spreading in the name
of readability, and I don't see this as actual value-add here:

The output of the macro is always the same as the input, and passing
an invalid number still results in an invalid output and no error message,
it actually prevents us from warning about the mistake at run-time.

The other macros are fine.

	Arnd


From arnd at arndb.de  Fri May 31 17:39:05 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 31 May 2013 23:39:05 +0200
Subject: [PATCH 04/12] ARM: shmobile: r8a7740: Add DT name to clock list
 for CMT10
In-Reply-To: <CANqRtoRwBHY1+Tgekg1CocZa4zWCAUWuZnW=5MXTA9SPcWYD0A@mail.gmail.com>
References: <1369645193-3595-1-git-send-email-horms+renesas@verge.net.au>
 <20130528062246.GB20031@quad.lixom.net>
 <CANqRtoRwBHY1+Tgekg1CocZa4zWCAUWuZnW=5MXTA9SPcWYD0A@mail.gmail.com>
Message-ID: <201305312339.05762.arnd@arndb.de>

On Friday 31 May 2013, Magnus Damm wrote:
> With mach-shmobile we have deliberately chosen to avoid AUXDATA. The
> reason for that is that we keep the DT version of a device clean from
> the beginning so it is kept totally free of platform data while in
> parallel we also have a regular platform device with platform data for
> the old legacy C version of board support. Other ARM subarchitectures
> seem to use DT together with platform data which is a step that we
> prefer to skip by using a C version and a DT version of board support
> in parallel. The idea is that we should be able to existing level of
> support in the C version while incrementally doing development on the
> DT -reference code. Then drop the C version when the DT version has
> become good enough. Current blockers are GPIO/PFC DT and common clock
> framework.

I think this makes sense and you we shouldn't force you as the platform
maintainer to do it the other way. Incrementally removing the auxdata
and platform_data structures as most platforms do is nice in the sense
that it allows you to have a fully working system booting with DT
from the start and to reduce the amount of code as early as possible,
and for instance this has worked rather well on kirkwood/orion/dove/mvebu.

The price for that method is that you end up having to coordinate patches
carefully between subsystems so you first add DT support to a driver,
and then atomically change the dts file and the board file to the
method. With your way, you can avoid a lot of the trouble we've seen
on other platforms with complex dependency graphs or broken
bisection.

> > Where are you guys at on your plans for getting DT_based clock going? That will
> > sort of indicate just how temporary these clock alaises will be. I'm guessing
> > we'll be living with them for a while though?
> 
> I have to deal with LPAE soon according to my todo list. After that I
> will make sure common clock conversion starts moving. There are many
> SoCs to convert, so it will have to happen gradually. I doubt we will
> get any code ready for merge in v3.11, getting some bits into v3.12 is
> probably possible.
> 
> Apart from moving to common clocks and after that adding support for a
> single multi-subarch kernel binary, is there anything you want us to
> implement? Anything for v3.11? I'd like to get the memory bits sorted
> out if possible.

My preference would be if you can get CONFIG_MULTIPLATFORM to work on
as many of your SoCs as possible, but that depends on having at least
some support for COMMON_CLK.

	Arnd


From khilman at linaro.org  Fri May 31 17:44:54 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 14:44:54 -0700
Subject: [PATCH] mfd: twl4030: allow IRQ wake enable to succeed on subchip IRQs
Message-ID: <1370036694-26210-1-git-send-email-khilman@linaro.org>

The genirq IRQ wake method will default to failure if the irq_chip
does not provide a set_wake method.  However, for TWL4030 sub-chip
IRQs, we want the wake enable to succeed even though we don't provide
a set_wake method.  This allows sub-chip IRQs to still be flagged as
wakeup capable, and allow them to wakeup from suspend (or abort
suspend if they fire during suspend.)

To fix, use the IRQCHIP_SKIP_SET_WAKE flag in the irq_chip.

Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
 drivers/mfd/twl4030-irq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index a5f9888..3fa7df2 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -573,6 +573,7 @@ static struct irq_chip twl4030_sih_irq_chip = {
 	.irq_set_type	= twl4030_sih_set_type,
 	.irq_bus_lock	= twl4030_sih_bus_lock,
 	.irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
+	.flags		= IRQCHIP_SKIP_SET_WAKE,
 };
 
 /*----------------------------------------------------------------------*/
-- 
1.8.2



From sboyd at codeaurora.org  Fri May 31 18:13:58 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri, 31 May 2013 15:13:58 -0700
Subject: [PATCH 5/4] sched: Make ARM's sched_clock generic for all
 architectures
In-Reply-To: <51A90ACE.7070906@linaro.org>
References: <1366417746-24990-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-1-git-send-email-sboyd@codeaurora.org>
 <51A90ACE.7070906@linaro.org>
Message-ID: <20130531221358.GF599@codeaurora.org>

On 05/31, John Stultz wrote:
> On 04/30/2013 05:54 PM, Stephen Boyd wrote:
> >Here's the patch to make sched_clock generic. I didn't know
> >where to put it so I just made a new file in kernel/sched
> >for now.
> >
> >Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> 
> Hey Stephen,
>     Baruch just asked a question about moving arm's sched_clock.c to
> be generic, and it sounded familiar, so I dug around and found this
> mail from a few months ago.
> 
> Just wanted to follow up and see what the status is with this? Is
> this queued somewhere already?
> 

As far as I know nothing has been queued. I refreshed the
patchset against 3.10-rc2 but haven't sent it out since it wasn't
clear if anyone wanted it. Shall I send it again?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From sboyd at codeaurora.org  Fri May 31 18:16:33 2013
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri, 31 May 2013 15:16:33 -0700
Subject: [PATCHv6 00/11] Remove ARM local timer API
In-Reply-To: <51A8E71D.1000407@linaro.org>
References: <1368473175-4841-1-git-send-email-sboyd@codeaurora.org>
 <20130531174526.GD599@codeaurora.org> <51A8E71D.1000407@linaro.org>
Message-ID: <20130531221633.GG599@codeaurora.org>

On 05/31, John Stultz wrote:
> On 05/31/2013 10:45 AM, Stephen Boyd wrote:
> >Comments have been light for this round so I think we're about
> >ready to merge. John/Thomas, can you pick up these patches or
> >shall I route them through arm-soc or something else?
> 
> 
> So there looks to be a fair amount of additions in the ARM tree, do
> those already have acks from Arnd/Olof/other folks? (I think I was
> only cc'ed on the first two patches).

I'm still missing acks from Kukjin and Barry.

> 
> Daniel (cc'ed) has just started helping out here, and should be able
> to review and hopefully ack or pick up the timer related
> drivers/clocksource changes to feed to Thomas' tree. Not sure if
> he's got them in his mailbox so you might want to resend them and
> make sure he's CC'ed.
> 
> If Arnd/Olof/whomever else from the arm side has acked things,
> Daniel probably could queue the arm changes too, but it might be
> better just to get Daniel's ack on the drivers/clocksource changes
> and then queue things via arm-soc?

Either way works for me. I would just like to see this merged
into 3.11. I guess I will resend one more time.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From s-anna at ti.com  Fri May 31 18:17:13 2013
From: s-anna at ti.com (Anna, Suman)
Date: Fri, 31 May 2013 22:17:13 +0000
Subject: [PATCH 1/2] ARM: dts: OMAP5: add PWM capability to timer nodes
 missing it
In-Reply-To: <516F3696.9080008@ti.com>
References: <1366240995-53538-1-git-send-email-s-anna@ti.com>
 <516F3696.9080008@ti.com>
Message-ID: <37C860A02101E749A747FA2D3C1E3C504BE487@DLEE11.ent.ti.com>

Benoit, Tony,
 
> On 04/17/2013 06:23 PM, Suman Anna wrote:
> > OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM.
> > The PWM capability property is missing from the node definitions of
> > couple of timers, and this has been fixed.
> >
> > Signed-off-by: Suman Anna <s-anna at ti.com>
> > ---
> >  arch/arm/boot/dts/omap5.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> > index 790bb2a..0d155f5 100644
> > --- a/arch/arm/boot/dts/omap5.dtsi
> > +++ b/arch/arm/boot/dts/omap5.dtsi
> > @@ -422,6 +422,7 @@
> >  			interrupts = <0 41 0x4>;
> >  			ti,hwmods = "timer5";
> >  			ti,timer-dsp;
> > +			ti,timer-pwm;
> >  		};
> >
> >  		timer6: timer at 4013a000 {
> > @@ -458,6 +459,7 @@
> >  			reg = <0x4803e000 0x80>;
> >  			interrupts = <0 45 0x4>;
> >  			ti,hwmods = "timer9";
> > +			ti,timer-pwm;
> >  		};
> >
> >  		timer10: timer at 48086000 {
> > @@ -465,6 +467,7 @@
> >  			reg = <0x48086000 0x80>;
> >  			interrupts = <0 46 0x4>;
> >  			ti,hwmods = "timer10";
> > +			ti,timer-pwm;
> >  		};
> >
> >  		timer11: timer at 48088000 {
> 
> Make sure you copy the linux-arm and device-tree mailing lists.
> 
> Acked-by: Jon Hunter <jon-hunter at ti.com>
> 

Can you include this patch in your next fixes pull request (if you haven't
already done so)? The other patch in the series is a feature change, but
this is a fix, and can go into 3.10 itself.

Regards
Suman

From arnd at arndb.de  Fri May 31 18:22:51 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:51 +0200
Subject: [PATCH 14/15] clk: tegra: provide tegra_periph_reset_assert
 alternative
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-15-git-send-email-arnd@arndb.de>

We have some tegra device drivers that are written to be platform
independent but still use the tegra specific tegra_periph_reset_assert
function. In order to build and link them without errors,
this provides a static inline version of these functions that
does nothing when Tegra support is disabled.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 include/linux/clk/tegra.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 642789b..1397190 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,8 +120,13 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
+#ifdef ARCH_TEGRA
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
+#else
+static inline void tegra_periph_reset_deassert(struct clk *c) {}
+static inline void tegra_periph_reset_assert(struct clk *c) {}
+#endif
 void tegra_clocks_init(void);
 void tegra_clocks_apply_init_table(void);
 
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:43 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:43 +0200
Subject: [PATCH 06/15] cpuidle: calxeda: select ARM_CPU_SUSPEND
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-7-git-send-email-arnd@arndb.de>

Like other ARM specific drivers, this one requires ARM_CPU_SUSPEND,
as shown by this linker error:

drivers/built-in.o: In function `calxeda_pwrdown_idle':
drivers/cpuidle/cpuidle-calxeda.c:84: undefined reference to `cpu_suspend'
drivers/cpuidle/cpuidle-calxeda.c:86: undefined reference to `cpu_resume'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Rafael J. Wysocki <rjw at sisk.pl>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: linux-pm at vger.kernel.org
---
 drivers/cpuidle/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index c4cc27e..e21cdfa 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -36,6 +36,7 @@ if CPU_IDLE
 config CPU_IDLE_CALXEDA
 	bool "CPU Idle Driver for Calxeda processors"
 	depends on ARCH_HIGHBANK
+	select ARM_CPU_SUSPEND
 	help
 	  Select this to enable cpuidle on Calxeda processors.
 
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:41 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:41 +0200
Subject: [PATCH 04/15] [SCSI] nsp32: use mdelay instead of large udelay
 constants
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-5-git-send-email-arnd@arndb.de>

ARM cannot handle udelay for more than 2 miliseconds, so we
should use mdelay instead for those.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: GOTO Masanori <gotom at debian.or.jp>
Cc: YOKOTA Hiroshi <yokota at netlab.is.tsukuba.ac.jp>
Cc: "James E.J. Bottomley" <JBottomley at parallels.com>
Cc: linux-scsi at vger.kernel.org
---
 drivers/scsi/nsp32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/nsp32.c b/drivers/scsi/nsp32.c
index 1e3879d..0665f9c 100644
--- a/drivers/scsi/nsp32.c
+++ b/drivers/scsi/nsp32.c
@@ -2899,7 +2899,7 @@ static void nsp32_do_bus_reset(nsp32_hw_data *data)
 	 * reset SCSI bus
 	 */
 	nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
-	udelay(RESET_HOLD_TIME);
+	mdelay(RESET_HOLD_TIME / 1000);
 	nsp32_write1(base, SCSI_BUS_CONTROL, 0);
 	for(i = 0; i < 5; i++) {
 		intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:44 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:44 +0200
Subject: [PATCH 07/15] cpufreq: spear needs cpufreq table
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-8-git-send-email-arnd@arndb.de>

Like a lot of the other cpufreq drivers, this one needs to
select CONFIG_CPU_FREQ_TABLE to avoid a build error like

drivers/built-in.o: In function `spear_cpufreq_exit':
spear-cpufreq.c:198: undefined reference to `cpufreq_frequency_table_put_attr'
drivers/built-in.o: In function `spear_cpufreq_verify':
spear-cpufreq.c:35: undefined reference to `cpufreq_frequency_table_verify'
drivers/built-in.o: In function `spear_cpufreq_init':
spear-cpufreq.c:181: undefined reference to `cpufreq_frequency_table_cpuinfo'
spear-cpufreq.c:187: undefined reference to `cpufreq_frequency_table_get_attr'
drivers/built-in.o: In function `spear_cpufreq_target':
spear-cpufreq.c:120: undefined reference to `cpufreq_frequency_table_target'
drivers/built-in.o:(.data+0x5e63c): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Viresh Kumar <viresh.kumar at linaro.org>
Cc: cpufreq at vger.kernel.org
Cc: linux-pm at vger.kernel.org
---
 drivers/cpufreq/Kconfig.arm | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index a924408..d3f2c6b 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -205,6 +205,7 @@ config ARM_SA1110_CPUFREQ
 config ARM_SPEAR_CPUFREQ
 	bool "SPEAr CPUFreq support"
 	depends on PLAT_SPEAR
+	select CPU_FREQ_TABLE
 	default y
 	help
 	  This adds the CPUFreq driver support for SPEAr SOCs.
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:49 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:49 +0200
Subject: [PATCH 12/15] [media] davinci: vpfe_capture needs i2c
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-13-git-send-email-arnd@arndb.de>

The vpfe_capture driver is implicitly built for three of the davinci
capture drivers but depends on i2c, so we need to add the dependency
in Kconfig for each driver using this.

 drivers/media/platform/davinci/vpfe_capture.c: In function 'vpfe_probe':
 drivers/media/platform/davinci/vpfe_capture.c:1934:2: error: implicit declaration of function 'i2c_get_adapter' [-Werror=implicit-function-declaration]
 drivers/media/platform/davinci/vpfe_capture.c:1934:11: warning: assignment makes pointer from integer without a cast [enabled by default]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Lad, Prabhakar <prabhakar.csengg at gmail.com>
Cc: Hans Verkuil <hans.verkuil at cisco.com>
Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
---
 drivers/media/platform/davinci/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/media/platform/davinci/Kconfig b/drivers/media/platform/davinci/Kconfig
index afb3aec..02da88b 100644
--- a/drivers/media/platform/davinci/Kconfig
+++ b/drivers/media/platform/davinci/Kconfig
@@ -27,6 +27,7 @@ config VIDEO_DAVINCI_VPIF_CAPTURE
 config VIDEO_DM6446_CCDC
 	tristate "TI DM6446 CCDC video capture driver"
 	depends on VIDEO_V4L2 && (ARCH_DAVINCI || ARCH_OMAP3)
+	depends on I2C
 	select VIDEOBUF_DMA_CONTIG
 	help
 	   Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces
@@ -41,6 +42,7 @@ config VIDEO_DM6446_CCDC
 config VIDEO_DM355_CCDC
 	tristate "TI DM355 CCDC video capture driver"
 	depends on VIDEO_V4L2 && ARCH_DAVINCI
+	depends on I2C
 	select VIDEOBUF_DMA_CONTIG
 	help
 	   Enables DM355 CCD hw module. DM355 CCDC hw interfaces
@@ -55,6 +57,7 @@ config VIDEO_DM355_CCDC
 config VIDEO_DM365_ISIF
 	tristate "TI DM365 ISIF video capture driver"
 	depends on VIDEO_V4L2 && ARCH_DAVINCI
+	depends on I2C
 	select VIDEOBUF_DMA_CONTIG
 	help
 	   Enables ISIF hw module. This is the hardware module for
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:38 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:38 +0200
Subject: [PATCH 01/15] irqdomain: export irq_domain_add_simple
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-2-git-send-email-arnd@arndb.de>

All other irq_domain_add_* functions are exported already, and apparently
this one got left out by mistake, which causes build errors for ARM
allmodconfig kernels:

ERROR: "irq_domain_add_simple" [drivers/gpio/gpio-rcar.ko] undefined!
ERROR: "irq_domain_add_simple" [drivers/gpio/gpio-em.ko] undefined!

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Simon Horman <horms+renesas at verge.net.au>
Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Cc: Magnus Damm <damm at opensource.se>
---
 kernel/irq/irqdomain.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index af804b5..47d0564 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -194,6 +194,7 @@ struct irq_domain *irq_domain_add_simple(struct device_node *of_node,
 	/* A linear domain is the default */
 	return irq_domain_add_linear(of_node, size, ops, host_data);
 }
+EXPORT_SYMBOL_GPL(irq_domain_add_simple);
 
 /**
  * irq_domain_add_legacy() - Allocate and register a legacy revmap irq_domain.
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:45 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:45 +0200
Subject: [PATCH 08/15] thermal: cpu_cooling: fix stub function
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-9-git-send-email-arnd@arndb.de>

The function stub for cpufreq_cooling_get_level introduced
in 57df81069 "Thermal: exynos: fix cooling state translation"
is not syntactically correct C and needs to be fixed to avoid
this error:

In file included from drivers/thermal/db8500_thermal.c:20:0:
 include/linux/cpu_cooling.h: In function 'cpufreq_cooling_get_level':
include/linux/cpu_cooling.h:57:1:
 error: parameter name omitted  unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)  ^
 include/linux/cpu_cooling.h:57:1: error: parameter name omitted

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Eduardo Valentin <eduardo.valentin at ti.com>
Cc: Eduardo Valentin <eduardo.valentin at ti.com>
Cc: Zhang Rui <rui.zhang at intel.com>
Cc: Amit Daniel kachhap <amit.daniel at samsung.com>
---
 include/linux/cpu_cooling.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h
index 282e270..a5d52ee 100644
--- a/include/linux/cpu_cooling.h
+++ b/include/linux/cpu_cooling.h
@@ -41,7 +41,7 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus);
  */
 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev);
 
-unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int);
+unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq);
 #else /* !CONFIG_CPU_THERMAL */
 static inline struct thermal_cooling_device *
 cpufreq_cooling_register(const struct cpumask *clip_cpus)
@@ -54,7 +54,7 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
 	return;
 }
 static inline
-unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int)
+unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq)
 {
 	return THERMAL_CSTATE_INVALID;
 }
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:52 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:52 +0200
Subject: [PATCH 15/15] OF: remove #ifdef from linux/of_platform.h
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-16-git-send-email-arnd@arndb.de>

A lot of code uses the functions from of_platform.h when built for
devicetree-enabled platforms but can also be built without them.
In order to avoid using #ifdef everywhere in drivers, this
makes all the function declarations visible, which means we
can use "if (IS_ENABLED(CONFIG_OF))" in driver code and get build
coverage over the code but let the compiler drop the reference
in the object code.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at linaro.org>
Cc: Rob Herring <rob.herring at calxeda.com>
---
 include/linux/of_platform.h | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/include/linux/of_platform.h b/include/linux/of_platform.h
index 2a93b64..7747ad0 100644
--- a/include/linux/of_platform.h
+++ b/include/linux/of_platform.h
@@ -13,8 +13,6 @@
 
 #include <linux/device.h>
 #include <linux/mod_devicetable.h>
-
-#ifdef CONFIG_OF_DEVICE
 #include <linux/pm.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
@@ -82,7 +80,6 @@ extern struct platform_device *of_device_alloc(struct device_node *np,
 					 struct device *parent);
 extern struct platform_device *of_find_device_by_node(struct device_node *np);
 
-#ifdef CONFIG_OF_ADDRESS /* device reg helpers depend on OF_ADDRESS */
 /* Platform devices and busses creation */
 extern struct platform_device *of_platform_device_create(struct device_node *np,
 						   const char *bus_id,
@@ -91,17 +88,12 @@ extern struct platform_device *of_platform_device_create(struct device_node *np,
 extern int of_platform_bus_probe(struct device_node *root,
 				 const struct of_device_id *matches,
 				 struct device *parent);
+#ifdef CONFIG_OF_ADDRESS
 extern int of_platform_populate(struct device_node *root,
 				const struct of_device_id *matches,
 				const struct of_dev_auxdata *lookup,
 				struct device *parent);
-#endif /* CONFIG_OF_ADDRESS */
-
-#endif /* CONFIG_OF_DEVICE */
-
-#if !defined(CONFIG_OF_ADDRESS)
-struct of_dev_auxdata;
-struct device_node;
+#else
 static inline int of_platform_populate(struct device_node *root,
 					const struct of_device_id *matches,
 					const struct of_dev_auxdata *lookup,
@@ -109,6 +101,6 @@ static inline int of_platform_populate(struct device_node *root,
 {
 	return -ENODEV;
 }
-#endif /* !CONFIG_OF_ADDRESS */
+#endif
 
 #endif	/* _LINUX_OF_PLATFORM_H */
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:40 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:40 +0200
Subject: [PATCH 03/15] drm/nouveau: use mdelay instead of large udelay
 constants
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-4-git-send-email-arnd@arndb.de>

ARM cannot handle udelay for more than 2 miliseconds, so we
should use mdelay instead for those.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: David Airlie <airlied at linux.ie>
Cc: Ben Skeggs <bskeggs at redhat.com>
Cc: dri-devel at lists.freedesktop.org
---
 drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index d0817d9..ed7415e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -51,7 +51,8 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
 	const u32 doff = (or * 0x800);
 	int load = -EINVAL;
 	nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
-	udelay(9500);
+	mdelay(9);
+	udelay(500);
 	nv_wr32(priv, 0x61a00c + doff, 0x80000000);
 	load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
 	nv_wr32(priv, 0x61a00c + doff, 0x00000000);
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:47 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:47 +0200
Subject: [PATCH 10/15] drm/tilcd: select BACKLIGHT_LCD_SUPPORT
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-11-git-send-email-arnd@arndb.de>

The dependecies for BACKLIGHT_CLASS_DEVICE are defined a bit
strange, but it seems one has to always select both BACKLIGHT_CLASS_DEVICE
and BACKLIGHT_LCD_SUPPORT to avoid this error:

drivers/gpu/drm/tilcdc/tilcdc_panel.c:396:
 undefined reference to `of_find_backlight_by_node'

Cc: Rob Clark <robdclark at gmail.com>
Cc: dri-devel at lists.freedesktop.org
Cc: Dave Airlie <airlied at redhat.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/gpu/drm/tilcdc/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index e461e99..7a4d101 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -6,6 +6,7 @@ config DRM_TILCDC
 	select DRM_GEM_CMA_HELPER
 	select VIDEOMODE_HELPERS
 	select BACKLIGHT_CLASS_DEVICE
+	select BACKLIGHT_LCD_SUPPORT
 	help
 	  Choose this option if you have an TI SoC with LCDC display
 	  controller, for example AM33xx in beagle-bone, DA8xx, or
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:42 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:42 +0200
Subject: [PATCH 05/15] hwrng: bcm2835: fix MODULE_LICENSE tag
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-6-git-send-email-arnd@arndb.de>

The MODULE_LICENSE macro invocation must use either "GPL" or "GPL v2",
but not "GPLv2" in order to be detected by the module loader.

This fixes the allmodconfig build error:

FATAL: modpost: GPL-incompatible module bcm2835-rng.ko uses GPL-only symbol 'platform_driver_unregister'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Dom Cobley <popcornmix at gmail.com>
Cc: Lubomir Rintel <lkundrak at v3.sk>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: Matt Mackall <mpm at selenic.com>
Cc: linux-rpi-kernel at lists.infradead.org
Cc: Herbert Xu <herbert at gondor.apana.org.au>
---
 drivers/char/hw_random/bcm2835-rng.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/char/hw_random/bcm2835-rng.c b/drivers/char/hw_random/bcm2835-rng.c
index eb7f147..43577ca 100644
--- a/drivers/char/hw_random/bcm2835-rng.c
+++ b/drivers/char/hw_random/bcm2835-rng.c
@@ -110,4 +110,4 @@ module_platform_driver(bcm2835_rng_driver);
 
 MODULE_AUTHOR("Lubomir Rintel <lkundrak at v3.sk>");
 MODULE_DESCRIPTION("BCM2835 Random Number Generator (RNG) driver");
-MODULE_LICENSE("GPLv2");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:46 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:46 +0200
Subject: [PATCH 09/15] drm: always provide debugfs function prototypes
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-10-git-send-email-arnd@arndb.de>

It is generally considered bad style to enclose function prototypes
in header files in #ifdef. This case illustrates why that is:
The tegra host1x driver calls into the debugfs functions if
CONFIG_DEBUG_FS is enabled, but that code is otherwise already
discarded by the compiler, so leaving the prototype in place
actually makes everything work.

drivers/gpu/host1x/drm/dc.c: In function 'tegra_dc_debugfs_init':
drivers/gpu/host1x/drm/dc.c:1004:2: error: implicit declaration of function 'drm_debugfs_create_files' [-Werror=implicit-function-declaration]
drivers/gpu/host1x/drm/dc.c: In function 'tegra_dc_debugfs_exit': drivers/gpu/host1x/drm/dc.c:1026:2: error: implicit declaration of function 'drm_debugfs_remove_files' [-Werror=implicit-function-declaration]

Cc: Ben Gamari <bgamari at gmail.com>
Cc: Dave Airlie <airlied at redhat.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 include/drm/drmP.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 63d17ee..8bc105e 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1551,7 +1551,7 @@ extern int drm_proc_init(struct drm_minor *minor, struct proc_dir_entry *root);
 extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root);
 
 				/* Debugfs support */
-#if defined(CONFIG_DEBUG_FS)
+
 extern int drm_debugfs_init(struct drm_minor *minor, int minor_id,
 			    struct dentry *root);
 extern int drm_debugfs_create_files(struct drm_info_list *files, int count,
@@ -1559,7 +1559,6 @@ extern int drm_debugfs_create_files(struct drm_info_list *files, int count,
 extern int drm_debugfs_remove_files(struct drm_info_list *files, int count,
                                     struct drm_minor *minor);
 extern int drm_debugfs_cleanup(struct drm_minor *minor);
-#endif
 
 				/* Info file support */
 extern int drm_name_info(struct seq_file *m, void *data);
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:50 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:50 +0200
Subject: [PATCH 13/15] [media] omap3isp: include linux/mm_types.h
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-14-git-send-email-arnd@arndb.de>

The ispqueue.h file uses vm_flags_t, which is defined in
linux/mm_types.h, so we must include that header in order
to build in all configurations.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
Cc: linux-media at vger.kernel.org
Cc: Konstantin Khlebnikov <khlebnikov at openvz.org>
Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
---
 drivers/media/platform/omap3isp/ispqueue.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/omap3isp/ispqueue.h b/drivers/media/platform/omap3isp/ispqueue.h
index 908dfd7..e6e720c 100644
--- a/drivers/media/platform/omap3isp/ispqueue.h
+++ b/drivers/media/platform/omap3isp/ispqueue.h
@@ -31,6 +31,7 @@
 #include <linux/mutex.h>
 #include <linux/videodev2.h>
 #include <linux/wait.h>
+#include <linux/mm_types.h>
 
 struct isp_video_queue;
 struct page;
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:39 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:39 +0200
Subject: [PATCH 02/15] mtd: omap2: allow bulding as a module
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-3-git-send-email-arnd@arndb.de>

The omap2 nand device driver calls into the the elm code, which can
be a loadable module, and in that case it cannot be built-in itself.
I can see no reason why the omap2 driver cannot also be a module,
so let's make the option "tristate" in Kconfig to fix this allmodconfig
build error:

ERROR: "elm_config" [drivers/mtd/nand/omap2.ko] undefined!
ERROR: "elm_decode_bch_error_page" [drivers/mtd/nand/omap2.ko] undefined!

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Tony Lindgren <tony at atomide.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: Afzal Mohammed <afzal at ti.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: linux-mtd at lists.infradead.org
---
 drivers/mtd/nand/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3ae9105..5ef8f5e 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -95,7 +95,7 @@ config MTD_NAND_OMAP2
 
 config MTD_NAND_OMAP_BCH
 	depends on MTD_NAND && MTD_NAND_OMAP2 && ARCH_OMAP3
-	bool "Enable support for hardware BCH error correction"
+	tristate "Enable support for hardware BCH error correction"
 	default n
 	select BCH
 	select BCH_CONST_PARAMS
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:48 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:48 +0200
Subject: [PATCH 11/15] iwlegacy: il_pm_ops is only provided for PM_SLEEP
In-Reply-To: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
Message-ID: <1370038972-2318779-12-git-send-email-arnd@arndb.de>

This makes sure the conditionals for the declaration match the
definition, so we provide the alternative

 #else
 #define IL_LEGACY_PM_OPS NULL
 #endif

in the correct cases. As suggested by Borislav Petkov, this removes
the comments for the #else and #endif lines.

drivers/built-in.o:(.data+0x57974): undefined reference to `il_pm_ops'

Cc: Johannes Berg <johannes.berg at intel.com>
Cc: John W. Linville <linville at tuxdriver.com>
Cc: Borislav Petkov <bp at alien8.de>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/net/wireless/iwlegacy/common.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2..30dda98 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,14 +1832,14 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
 			  u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS	(&il_pm_ops)
 
-#else /* !CONFIG_PM */
+#else
 
-#define IL_LEGACY_PM_OPS	NULL
+#define
 
 #endif /* !CONFIG_PM */
 
-- 
1.8.1.2



From arnd at arndb.de  Fri May 31 18:22:37 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat,  1 Jun 2013 00:22:37 +0200
Subject: [PATCH 00/15] Linux-3.10 ARM randconfig fixes
Message-ID: <1370038972-2318779-1-git-send-email-arnd@arndb.de>

Hi subsystem maintainers,

These are a few patches left over from doing randconfig tests
a couple of weeks ago. Please apply them directly into your
trees unless you see problems. All patches can theoretically
be seen as bug fixes for 3.10, but they are not critical,
so applying them for 3.11 is fine as well.

	Arnd

Arnd Bergmann (15):
  irqdomain: export irq_domain_add_simple
  mtd: omap2: allow bulding as a module
  drm/nouveau: use mdelay instead of large udelay constants
  [SCSI] nsp32: use mdelay instead of large udelay constants
  hwrng: bcm2835: fix MODULE_LICENSE tag
  cpuidle: calxeda: select ARM_CPU_SUSPEND
  cpufreq: spear needs cpufreq table
  thermal: cpu_cooling: fix stub function
  drm: always provide debugfs function prototypes
  drm/tilcd: select BACKLIGHT_LCD_SUPPORT
  iwlegacy: il_pm_ops is only provided for PM_SLEEP
  [media] davinci: vpfe_capture needs i2c
  [media] omap3isp: include linux/mm_types.h
  clk: tegra: provide tegra_periph_reset_assert alternative
  OF: remove #ifdef from linux/of_platform.h

 drivers/char/hw_random/bcm2835-rng.c               |  2 +-
 drivers/cpufreq/Kconfig.arm                        |  1 +
 drivers/cpuidle/Kconfig                            |  1 +
 drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c |  3 ++-
 drivers/gpu/drm/tilcdc/Kconfig                     |  1 +
 drivers/media/platform/davinci/Kconfig             |  3 +++
 drivers/media/platform/omap3isp/ispqueue.h         |  1 +
 drivers/mtd/nand/Kconfig                           |  2 +-
 drivers/net/wireless/iwlegacy/common.h             |  6 +++---
 drivers/scsi/nsp32.c                               |  2 +-
 include/drm/drmP.h                                 |  3 +--
 include/linux/clk/tegra.h                          |  5 +++++
 include/linux/cpu_cooling.h                        |  4 ++--
 include/linux/of_platform.h                        | 14 +++-----------
 kernel/irq/irqdomain.c                             |  1 +
 15 files changed, 27 insertions(+), 22 deletions(-)

Cc: "James E.J. Bottomley" <JBottomley at parallels.com>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: Dave Airlie <airlied at redhat.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: John W. Linville <linville at tuxdriver.com>
Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Cc: Mauro Carvalho Chehab <mchehab at redhat.com>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Rob Clark <robdclark at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Viresh Kumar <viresh.kumar at linaro.org>
Cc: cpufreq at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: linux-media at vger.kernel.org
Cc: linux-mtd at lists.infradead.org
Cc: linux-pm at vger.kernel.org
Cc: linux-rpi-kernel at lists.infradead.org
Cc: linux-scsi at vger.kernel.org


-- 
1.8.1.2



From simon.guinot at sequanux.org  Fri May 31 18:16:16 2013
From: simon.guinot at sequanux.org (Simon Guinot)
Date: Sat, 1 Jun 2013 00:16:16 +0200
Subject: [PATCHv2 1/3] Add support for GMT G762/G763 PWM fan controller
In-Reply-To: <b44f55c4194f6cd8c94f8a3d63ad5c8bd1d1cfe0.1369687670.git.arno@natisbad.org>
References: <cover.1369687670.git.arno@natisbad.org>
 <b44f55c4194f6cd8c94f8a3d63ad5c8bd1d1cfe0.1369687670.git.arno@natisbad.org>
Message-ID: <20130531221616.GG7626@kw.sim.vm.gnt>

On Tue, May 28, 2013 at 12:03:14AM +0200, Arnaud Ebalard wrote:
> 
> Signed-off-by: Arnaud Ebalard <arno at natisbad.org>
> ---
>  drivers/hwmon/Kconfig              |   10 +
>  drivers/hwmon/Makefile             |    1 +
>  drivers/hwmon/g762.c               | 1012 ++++++++++++++++++++++++++++++++++++
>  include/linux/platform_data/g762.h |   54 ++
>  4 files changed, 1077 insertions(+)
>  create mode 100644 drivers/hwmon/g762.c
>  create mode 100644 include/linux/platform_data/g762.h

Hi Arnaud,

After more tests on my 2Big Network v2 board, it appears that the fan
doesn't rotate when PWM mode (the preferred operating mode for this
board) is selected. Nevertheless, DC mode is usable (even if not ideal
given the hardware). After some investigations I noticed that an extra
initialization is needed to enable PWM mode on my board: the set_cnt
register must be set to 0 while the default value is 0xff. Is that
specific to my hardware ? Is PWM mode working on your ReadyNAS with
the default set_cnt value ?

I haven't noticed this issue while testing your v1 patch series because
at the time I was using a board with an U-Boot modified by LaCie. This
last sets the set_cnt register to 0 while U-Boot mainline don't.
Actually, the 2Big fan is not configured nor even started by U-Boot
mainline. I have to fix this but maybe that something can be done in
the g762 Linux driver too ?

> 
> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> index 0428e8a..142bdf8 100644
> --- a/drivers/hwmon/Kconfig
> +++ b/drivers/hwmon/Kconfig

Snip

> diff --git a/include/linux/platform_data/g762.h b/include/linux/platform_data/g762.h
> new file mode 100644
> index 0000000..29e3934
> --- /dev/null
> +++ b/include/linux/platform_data/g762.h
> @@ -0,0 +1,54 @@
> +/*
> + * Platform data structure for g762 fan controller driver
> + *
> + * Copyright (C) 2013, Arnaud EBALARD <arno at natisbad.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +#ifndef __LINUX_PLATFORM_DATA_G762_H__
> +#define __LINUX_PLATFORM_DATA_G762_H__
> +
> +#define G762_DEFAULT_NO_OVERLOAD 0xffffffff
> +
> +struct g762_platform_data {
> +	u32 fan_startv;
> +	u32 fan_gear_mode;
> +	u32 fan_div;
> +	u32 fan_pulses;
> +	u32 fan_target;
> +	u32 pwm_polarity;
> +	u32 pwm_enable;
> +	u32 pwm_freq;
> +	u32 pwm_mode;
> +};
> +
> +/* When filling a g762_platform_data structure to be passed during platform
> + * init to the driver, it needs to be initialized to the following default
> + * value before changing specific fields. This is needed to avoid a sparse
> + * initialization to have current values replaced by 0 */

In other places, you use this multi-line comment format:

/*
 * ...
 * ...
 */

> +
> +static const struct g762_platform_data G762_DEFAULT_PDATA = {
> +	.fan_startv = G762_DEFAULT_NO_OVERLOAD,
> +	.fan_gear_mode = G762_DEFAULT_NO_OVERLOAD,
> +	.fan_div = G762_DEFAULT_NO_OVERLOAD,
> +	.fan_pulses = G762_DEFAULT_NO_OVERLOAD,
> +	.fan_target = G762_DEFAULT_NO_OVERLOAD,
> +	.pwm_polarity = G762_DEFAULT_NO_OVERLOAD,
> +	.pwm_enable = G762_DEFAULT_NO_OVERLOAD,
> +	.pwm_freq = G762_DEFAULT_NO_OVERLOAD,
> +	.pwm_mode = G762_DEFAULT_NO_OVERLOAD,
> +};

Are you sure that all this settings are needed ? IMHO the g762 platform
data should only holds the platform specific configuration: fan_startv,
fan_gear_mode, fan_div and fan_pulses. The other settings are not really
related with the platform but more with the operating fan configuration.
For my part, I am happy enough with the sysfs hwmon interface.

The same comment applies to the g762 DT binding properties.

Regards,

Simon
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From grant.likely at linaro.org  Fri May 31 18:37:03 2013
From: grant.likely at linaro.org (Grant Likely)
Date: Fri, 31 May 2013 23:37:03 +0100
Subject: [PATCH 11/21] irqdomain: export irq_domain_add_simple
In-Reply-To: <20130426005012.GB20070@verge.net.au>
References: <1366910944-3033663-1-git-send-email-arnd@arndb.de>
 <1366910944-3033663-12-git-send-email-arnd@arndb.de>
 <20130426005012.GB20070@verge.net.au>
Message-ID: <20130531223703.CFB573E08FE@localhost>

On Fri, 26 Apr 2013 09:50:12 +0900, Simon Horman <horms at verge.net.au> wrote:
> On Thu, Apr 25, 2013 at 07:28:54PM +0200, Arnd Bergmann wrote:
> > All other irq_domain_add_* functions are exported already, and apparently
> > this one got left out by mistake, which causes build errors for ARM
> > allmodconfig kernels:
> > 
> > ERROR: "irq_domain_add_simple" [drivers/gpio/gpio-rcar.ko] undefined!
> > ERROR: "irq_domain_add_simple" [drivers/gpio/gpio-em.ko] undefined!
> > 
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > Cc: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> > Cc: Grant Likely <grant.likely at linaro.org>
> > Cc: Thomas Gleixner <tglx at linutronix.de>
> > Cc: Simon Horman <horms+renesas at verge.net.au>
> > Cc: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> > Cc: Magnus Damm <damm at opensource.se>
> 
> Acked-by: Simon Horman <horms+renesas at verge.net.au>
> 
> Grant, could consider taking this one?
> 

Applied, thanks. I'll push out to Linus shortly.

g.


From khilman at linaro.org  Fri May 31 18:37:07 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 15:37:07 -0700
Subject: [PATCH] rtc: rtc-twl: ensure IRQ is wakeup enabled
Message-ID: <1370039827-25033-1-git-send-email-khilman@linaro.org>

Currently, the RTC IRQ is never wakeup-enabled so is not capable of
bringing the system out of suspend.

On OMAP platforms, we have gotten by without this because the TWL RTC
is on an I2C-connected chip which is capable of waking up the OMAP via
the IO ring when the OMAP is in low-power states.

However, if the OMAP suspends without hitting the low-power states
(and the IO ring is not enabled), RTC wakeups will not work because
the IRQ is not wakeup enabled.

To fix, ensure the RTC IRQ is wakeup enabled whenever the RTC alarm is
set.

Cc: Alessandro Zummo <a.zummo at towertech.it>
Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
 drivers/rtc/rtc-twl.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a52..bbda0fd 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -213,12 +213,24 @@ static int mask_rtc_irq_bit(unsigned char bit)
 
 static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
 {
+	struct platform_device *pdev = to_platform_device(dev);
+	int irq = platform_get_irq(pdev, 0);
+	static bool twl_rtc_wake_enabled;
 	int ret;
 
-	if (enabled)
+	if (enabled) {
 		ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
-	else
+		if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
+			enable_irq_wake(irq);
+			twl_rtc_wake_enabled = true;
+		}
+	} else {
 		ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
+		if (twl_rtc_wake_enabled) {
+			disable_irq_wake(irq);
+			twl_rtc_wake_enabled = false;
+		}
+	}
 
 	return ret;
 }
-- 
1.8.2



From andre.przywara at linaro.org  Fri May 31 18:39:12 2013
From: andre.przywara at linaro.org (Andre Przywara)
Date: Sat,  1 Jun 2013 00:39:12 +0200
Subject: [PATCH] ARM/KVM: save and restore generic timer registers
Message-ID: <1370039952-20888-1-git-send-email-andre.przywara@linaro.org>

For migration to work we need to save (and later restore) the state of
each cores virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and just
need to add the three registers (control, counter, compare value) to
the list of saved registers. However we provide special accessor
functions to get the value of each register, since the content can
change anytime.

Signed-off-by: Andre Przywara <andre.przywara at linaro.org>
---
 arch/arm/include/asm/kvm_asm.h  |  7 ++++++-
 arch/arm/include/asm/kvm_host.h |  3 +++
 arch/arm/include/uapi/asm/kvm.h | 16 ++++++++++++++++
 arch/arm/kvm/arch_timer.c       | 32 ++++++++++++++++++++++++++++++++
 arch/arm/kvm/coproc.c           | 30 ++++++++++++++++++++++++++++++
 5 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d5032..a732b17 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -46,7 +46,12 @@
 #define c13_TID_URO	24	/* Thread ID, User R/O */
 #define c13_TID_PRIV	25	/* Thread ID, Privileged */
 #define c14_CNTKCTL	26	/* Timer Control Register (PL1) */
-#define NR_CP15_REGS	27	/* Number of regs (incl. invalid) */
+#define c14_CNTV_CTL	27	/* Virtual Timer Control Register */
+#define c14_CNTVCT	28	/* Virtual Timer Counter Register */
+#define c14_CNTVCT_high	29	/* Virtual Timer Counter Register */
+#define c14_CNTV_CVAL	30	/* Virtual Timer Counter Register */
+#define c14_CNTV_CVAL_high	31	/* Virtual Timer Counter Register */
+#define NR_CP15_REGS	32	/* Number of regs (incl. invalid) */
 
 #define ARM_EXCEPTION_RESET	  0
 #define ARM_EXCEPTION_UNDEFINED   1
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786..80714ab 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -224,4 +224,7 @@ static inline int kvm_arch_dev_ioctl_check_extension(long ext)
 int kvm_perf_init(void);
 int kvm_perf_teardown(void);
 
+u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, const struct kvm_one_reg *);
+void kvm_arm_timer_set_reg(struct kvm_vcpu *, const struct kvm_one_reg *, u64);
+
 #endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index c1ee007..e3b0115 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -118,6 +118,22 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_32_CRN_MASK		0x0000000000007800
 #define KVM_REG_ARM_32_CRN_SHIFT	11
 
+#define KVM_REG_ARM_32_CP15		(KVM_REG_ARM | KVM_REG_SIZE_U32      | \
+					(15ULL << KVM_REG_ARM_COPROC_SHIFT))
+#define KVM_REG_ARM_64_CP15		(KVM_REG_ARM | KVM_REG_SIZE_U64      | \
+					(15ULL << KVM_REG_ARM_COPROC_SHIFT))
+#define KVM_REG_ARM_TIMER_CTL		(KVM_REG_ARM_32_CP15                 | \
+					( 3ULL << KVM_REG_ARM_CRM_SHIFT)     | \
+					(14ULL << KVM_REG_ARM_32_CRN_SHIFT)  | \
+					( 0ULL << KVM_REG_ARM_OPC1_SHIFT)    | \
+					( 1ULL << KVM_REG_ARM_32_OPC2_SHIFT))
+#define KVM_REG_ARM_TIMER_CNT		(KVM_REG_ARM_64_CP15 | \
+					(14ULL << KVM_REG_ARM_CRM_SHIFT)     | \
+					( 1ULL << KVM_REG_ARM_OPC1_SHIFT))
+#define KVM_REG_ARM_TIMER_CVAL		(KVM_REG_ARM_64_CP15 | \
+					(14ULL << KVM_REG_ARM_CRM_SHIFT)     | \
+					( 3ULL << KVM_REG_ARM_OPC1_SHIFT))
+
 /* Normal registers are mapped as coprocessor 16. */
 #define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
 #define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / 4)
diff --git a/arch/arm/kvm/arch_timer.c b/arch/arm/kvm/arch_timer.c
index c55b608..64a8920b 100644
--- a/arch/arm/kvm/arch_timer.c
+++ b/arch/arm/kvm/arch_timer.c
@@ -171,6 +171,38 @@ static void kvm_timer_init_interrupt(void *info)
 	enable_percpu_irq(timer_irq.irq, 0);
 }
 
+void kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu,
+			   const struct kvm_one_reg *reg, u64 val)
+{
+	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+
+	switch (reg->id) {
+	case KVM_REG_ARM_TIMER_CTL:
+		timer->cntv_ctl = val;
+		break;
+	case KVM_REG_ARM_TIMER_CNT:
+		vcpu->kvm->arch.timer.cntvoff = kvm_phys_timer_read() - val;
+		break;
+	case KVM_REG_ARM_TIMER_CVAL:
+		timer->cntv_cval = val;
+		break;
+	}
+}
+
+u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+
+	switch (reg->id) {
+	case KVM_REG_ARM_TIMER_CTL:
+		return timer->cntv_ctl;
+	case KVM_REG_ARM_TIMER_CNT:
+		return kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
+	case KVM_REG_ARM_TIMER_CVAL:
+		return timer->cntv_cval;
+	}
+	return 0;
+}
 
 static int kvm_timer_cpu_notify(struct notifier_block *self,
 				unsigned long action, void *cpu)
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 8eea97b..63b2e89 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -156,6 +156,8 @@ static const struct coproc_reg cp15_regs[] = {
 	/* TTBR0/TTBR1: swapped by interrupt.S. */
 	{ CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
 	{ CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
+	{ CRm(14), Op1( 1), is64, NULL, reset_unknown64, c14_CNTVCT},
+	{ CRm(14), Op1( 3), is64, NULL, reset_unknown64, c14_CNTV_CVAL},
 
 	/* TTBCR: swapped by interrupt.S. */
 	{ CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
@@ -226,6 +228,8 @@ static const struct coproc_reg cp15_regs[] = {
 	/* CNTKCTL: swapped by interrupt.S. */
 	{ CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
 			NULL, reset_val, c14_CNTKCTL, 0x00000000 },
+	{ CRn(14), CRm( 3), Op1( 0), Op2( 1), is32,
+			NULL, reset_val, c14_CNTV_CTL, 0x00000000 },
 };
 
 /* Target specific emulation tables */
@@ -823,10 +827,22 @@ static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
 }
 #endif /* !CONFIG_VFPv3 */
 
+static bool is_timer_reg(u64 index)
+{
+	switch (index) {
+	case KVM_REG_ARM_TIMER_CTL:
+	case KVM_REG_ARM_TIMER_CNT:
+	case KVM_REG_ARM_TIMER_CVAL:
+		return true;
+	}
+	return false;
+}
+
 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 {
 	const struct coproc_reg *r;
 	void __user *uaddr = (void __user *)(long)reg->addr;
+	u64 val;
 
 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 		return demux_c15_get(reg->id, uaddr);
@@ -834,6 +850,11 @@ int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
 		return vfp_get_reg(vcpu, reg->id, uaddr);
 
+	if (is_timer_reg(reg->id)) {
+		val = kvm_arm_timer_get_reg(vcpu, reg);
+		return reg_to_user(uaddr, &val, reg->id);
+	}
+
 	r = index_to_coproc_reg(vcpu, reg->id);
 	if (!r)
 		return get_invariant_cp15(reg->id, uaddr);
@@ -846,6 +867,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 {
 	const struct coproc_reg *r;
 	void __user *uaddr = (void __user *)(long)reg->addr;
+	u64 val;
+	int ret;
 
 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 		return demux_c15_set(reg->id, uaddr);
@@ -853,6 +876,13 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
 		return vfp_set_reg(vcpu, reg->id, uaddr);
 
+	if (is_timer_reg(reg->id)) {
+		ret = reg_from_user(&val, uaddr, reg->id);
+		if (ret == 0)
+			kvm_arm_timer_set_reg(vcpu, reg, val);
+		return ret;
+	}
+
 	r = index_to_coproc_reg(vcpu, reg->id);
 	if (!r)
 		return set_invariant_cp15(reg->id, uaddr);
-- 
1.7.12.1



From arnd at arndb.de  Fri May 31 18:41:07 2013
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 1 Jun 2013 00:41:07 +0200
Subject: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <1369046369-12489-4-git-send-email-josephl@nvidia.com>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
 <1369046369-12489-4-git-send-email-josephl@nvidia.com>
Message-ID: <201306010041.07230.arnd@arndb.de>

On Monday 20 May 2013, Joseph Lo wrote:
> +       cpu_to_csr_req r1, r0
> +       mov32   r2, TEGRA_FLOW_CTRL_BASE
> +       ldr     r1, [r2, r1]

This causes build errors now, since cpu_to_csr_req is not defined anywhere.

	Arnd


From festevam at gmail.com  Fri May 31 18:42:07 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 31 May 2013 19:42:07 -0300
Subject: [PATCH v2 2/2] ARM: mxs: Pass the system revision
In-Reply-To: <1370040127-15072-1-git-send-email-festevam@gmail.com>
References: <1370040127-15072-1-git-send-email-festevam@gmail.com>
Message-ID: <1370040127-15072-2-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Some mxs userspace tools, such as multimedia plugins and kobs-ng (tool used to 
burn boot images to NAND) rely on the 'Revision' field reported by 
'/proc/cpuinfo'.

Provide a mechanism to pass such information, so that now we can get:

$ cat /proc/cpuinfo                                             
processor       : 0                                                             
model name      : ARM926EJ-S rev 5 (v5l)                                        
BogoMIPS        : 226.09                                                        
Features        : swp half fastmult edsp java                                   
CPU implementer : 0x41                                                          
CPU architecture: 5TEJ                                                          
CPU variant     : 0x0                                                           
CPU part        : 0x926                                                         
CPU revision    : 5                                                             
                                                                                
Hardware        : Freescale i.MX28 Evaluation Kit                               
Revision        : 28012                                                         
Serial          : 0000000000000000 

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com> 
---
Changes since v1:
- No changes

 arch/arm/mach-mxs/mach-mxs.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 462fa14..0d7e1eb 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -29,6 +29,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
+#include <asm/system_info.h>
 
 #include "pm.h"
 
@@ -442,12 +443,26 @@ static void mxs_print_silicon_rev(const char *cpu, int srev)
 				cpu, (srev >> 4) & 0xf, srev & 0xf);
 }
 
+static void mxs_pass_sysrev(void)
+{
+	int cputype = 0;
+
+	if (strcmp(mxs_get_cpu_type(), "MX23"))
+		cputype = 0x23000;
+
+	if (strcmp(mxs_get_cpu_type(), "MX28"))
+		cputype = 0x28000;
+
+	system_rev = (cputype | mxs_get_cpu_rev());
+}
+
 static void __init mxs_machine_init(void)
 {
 	const char *cpu_char = mxs_get_cpu_type();
 	int cpu_rev = mxs_get_cpu_rev();
 
 	mxs_print_silicon_rev(cpu_char, cpu_rev);
+	mxs_pass_sysrev();
 
 	if (of_machine_is_compatible("fsl,imx28-evk"))
 		imx28_evk_init();
-- 
1.8.1.2



From festevam at gmail.com  Fri May 31 18:42:06 2013
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 31 May 2013 19:42:06 -0300
Subject: [PATCH v2 1/2] ARM: mxs: Print silicon version on boot
Message-ID: <1370040127-15072-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Introduce functions that identify the SoC type (i.MX23 or iMX28)
and also report the silicon revision.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Changes since v1:
- Use MXS as prefix in the revision definitions
- Retrieve the base address from dt
- Remove unneeded blank line
- Treat 0x0 as TO1.1
- Use u32

 arch/arm/mach-mxs/mach-mxs.c | 86 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 66fe810..462fa14 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -38,12 +38,27 @@
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0		0x2
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1		0x3
 
+#define HW_DIGCTL_CHIPID	0x310
+#define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
+#define HW_DIGCTL_REV_MASK	0xff
+#define HW_DIGCTL_CHIPID_MX23	(0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
+
+#define MXS_CHIP_REVISION_1_0	0x10
+#define MXS_CHIP_REVISION_1_1	0x11
+#define MXS_CHIP_REVISION_1_2	0x12
+#define MXS_CHIP_REVISION_1_3	0x13
+#define MXS_CHIP_REVISION_1_4	0x14
+#define MXS_CHIP_REV_UNKNOWN	0xff
+
 #define MXS_GPIO_NR(bank, nr)	((bank) * 32 + (nr))
 
 #define MXS_SET_ADDR		0x4
 #define MXS_CLR_ADDR		0x8
 #define MXS_TOG_ADDR		0xc
 
+static void __iomem *digctl_base;
+
 static inline void __mxs_setl(u32 mask, void __iomem *reg)
 {
 	__raw_writel(mask, reg + MXS_SET_ADDR);
@@ -361,8 +376,79 @@ static void __init cfa10037_init(void)
 	update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
 
+static const char *mxs_get_cpu_type(void)
+{
+	u32 reg;
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
+	digctl_base = of_iomap(np, 0);
+	WARN_ON(!digctl_base);
+
+	reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK;
+	switch (reg) {
+	case HW_DIGCTL_CHIPID_MX23:
+		return "23";
+	case HW_DIGCTL_CHIPID_MX28:
+		return "28";
+	default:
+		return "unknown";
+	}
+}
+
+static int mxs_get_cpu_rev(void)
+{
+	u32 reg, rev;
+
+	reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK;
+	rev = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_REV_MASK;
+
+	switch (reg) {
+	case HW_DIGCTL_CHIPID_MX23:
+		switch (rev) {
+		case 0x0:
+			return MXS_CHIP_REVISION_1_0;
+		case 0x1:
+			return MXS_CHIP_REVISION_1_1;
+		case 0x2:
+			return MXS_CHIP_REVISION_1_2;
+		case 0x3:
+			return MXS_CHIP_REVISION_1_3;
+		case 0x4:
+			return MXS_CHIP_REVISION_1_4;
+		default:
+			return MXS_CHIP_REV_UNKNOWN;
+		}
+	case HW_DIGCTL_CHIPID_MX28:
+		switch (rev) {
+		case 0x0:
+			return MXS_CHIP_REVISION_1_1;
+		case 0x1:
+			return MXS_CHIP_REVISION_1_2;
+		default:
+			return MXS_CHIP_REV_UNKNOWN;
+		}
+	default:
+		return MXS_CHIP_REV_UNKNOWN;
+	}
+}
+
+static void mxs_print_silicon_rev(const char *cpu, int srev)
+{
+	if (srev == MXS_CHIP_REV_UNKNOWN)
+		pr_info("CPU identified as i.MX%s, unknown revision\n", cpu);
+	else
+		pr_info("CPU identified as i.MX%s, silicon rev %d.%d\n",
+				cpu, (srev >> 4) & 0xf, srev & 0xf);
+}
+
 static void __init mxs_machine_init(void)
 {
+	const char *cpu_char = mxs_get_cpu_type();
+	int cpu_rev = mxs_get_cpu_rev();
+
+	mxs_print_silicon_rev(cpu_char, cpu_rev);
+
 	if (of_machine_is_compatible("fsl,imx28-evk"))
 		imx28_evk_init();
 	else if (of_machine_is_compatible("bluegiga,apx4devkit"))
-- 
1.8.1.2



From khilman at linaro.org  Fri May 31 18:45:54 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 15:45:54 -0700
Subject: [PATCH 0/3] ARM: DTS: misc. OMAP3 fixes for proper wakeup
Message-ID: <1370040357-25794-1-git-send-email-khilman@linaro.org>

Benoit,

Here are handful of DT updates while working on getting PM functionality
working for DT boot on OMAP3.

Kevin


Kevin Hilman (3):
  ARM: DTS: OMAP3: beagle/overo: mux console UART, enable wakeup
  ARM: DTS: OMAP3: beagle: enable user button via gpio_keys, enable
    wakeup
  ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line

 arch/arm/boot/dts/omap3-beagle-xm.dts | 39 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-beagle.dts    | 37 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi    | 14 +++++++++++++
 arch/arm/boot/dts/twl4030.dtsi        | 17 +++++++++++++++
 4 files changed, 107 insertions(+)

-- 
1.8.2



From khilman at linaro.org  Fri May 31 18:45:55 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 15:45:55 -0700
Subject: [PATCH 1/3] ARM: DTS: OMAP3: beagle/overo: mux console UART,
 enable wakeup
In-Reply-To: <1370040357-25794-1-git-send-email-khilman@linaro.org>
References: <1370040357-25794-1-git-send-email-khilman@linaro.org>
Message-ID: <1370040357-25794-2-git-send-email-khilman@linaro.org>

Ensure the console uart (UART3) on these boards is mux'd correctly, and
IO ring wakeup is enabled.

This is needed for serial console wakeups when using DT boot.

Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
 arch/arm/boot/dts/omap3-beagle-xm.dts | 14 ++++++++++++++
 arch/arm/boot/dts/omap3-beagle.dts    | 12 ++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi    | 14 ++++++++++++++
 3 files changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..ca067b0 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -126,3 +126,17 @@
 	mode = <3>;
 	power = <50>;
 };
+
+&omap3_pmx_core {
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			0x16e 0x4100	/* uart3_rx_irrx.uart3_rx_irrx WAKEUP | INPUT | MODE0 */
+			0x170 0x0	/* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+		>;
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..b004372 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -95,6 +95,13 @@
 			0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
 		>;
 	};
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			0x16e 0x4100	/* uart3_rx_irrx.uart3_rx_irrx WAKEUP | INPUT | MODE0 */
+			0x170 0x0	/* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -142,3 +149,8 @@
 	 */
 	ti,pulldowns = <0x03a1c4>;
 };
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50..d63ed39 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -77,3 +77,17 @@
 	mode = <3>;
 	power = <50>;
 };
+
+&omap3_pmx_core {
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			0x16e 0x4100	/* uart3_rx_irrx.uart3_rx_irrx WAKEUP | INPUT | MODE0 */
+			0x170 0x0	/* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+		>;
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
-- 
1.8.2



From khilman at linaro.org  Fri May 31 18:45:56 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 15:45:56 -0700
Subject: [PATCH 2/3] ARM: DTS: OMAP3: beagle: enable user button via gpio_keys,
 enable wakeup
In-Reply-To: <1370040357-25794-1-git-send-email-khilman@linaro.org>
References: <1370040357-25794-1-git-send-email-khilman@linaro.org>
Message-ID: <1370040357-25794-3-git-send-email-khilman@linaro.org>

Using the gpio-keys bindings, configure the user button on Beagle
boards.  Since the user button is enabled as a wakeup source, also
ensure the GPIO pin is mux'd correctly and has IO ring wakeups enabled,
so it can also wakeup from off mode.

Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
 arch/arm/boot/dts/omap3-beagle-xm.dts | 25 +++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-beagle.dts    | 25 +++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index ca067b0..c93c36f 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -57,6 +57,26 @@
 		ti,mcbsp = <&mcbsp2>;
 		ti,codec = <&twl_audio>;
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user {
+			label = "user";
+			gpios = <&gpio1 4 0>;
+			linux,code = <0x114>;
+			gpio-key,wakeup;
+		};
+
+	};
+};
+
+&omap3_pmx_wkup {
+	gpio1_pins: pinmux_gpio1_pins {
+		pinctrl-single,pins = <
+			0x0e 0x4104	/* sys_boot2.gpio_4 WAKEUP | INPUT | MODE4 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -140,3 +160,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
 };
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index b004372..c9794cb 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -71,6 +71,26 @@
 		reset-supply = <&hsusb2_reset>;
 		vcc-supply = <&hsusb2_power>;
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user {
+			label = "user";
+			gpios = <&gpio1 7 0>;
+			linux,code = <0x114>;
+			gpio-key,wakeup;
+		};
+
+	};
+};
+
+&omap3_pmx_wkup {
+	gpio1_pins: pinmux_gpio1_pins {
+		pinctrl-single,pins = <
+			0x14 0x4104	/* sys_boot5.gpio_7 WAKEUP | INPUT | MODE4 */
+		>;
+	};
 };
 
 &omap3_pmx_core {
@@ -154,3 +174,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
 };
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio1_pins>;
+};
-- 
1.8.2



From khilman at linaro.org  Fri May 31 18:45:57 2013
From: khilman at linaro.org (Kevin Hilman)
Date: Fri, 31 May 2013 15:45:57 -0700
Subject: [PATCH 3/3] ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line
In-Reply-To: <1370040357-25794-1-git-send-email-khilman@linaro.org>
References: <1370040357-25794-1-git-send-email-khilman@linaro.org>
Message-ID: <1370040357-25794-4-git-send-email-khilman@linaro.org>

On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP.  Therefore, configure the defaults for the
SYS_NIRQ pin in the twl4030 DTS file.

Boards that hook up the twl4030 differently can easily override this
in their board-specific DTS file.

This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030.  Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.

Signed-off-by: Kevin Hilman <khilman at linaro.org>
---
 arch/arm/boot/dts/twl4030.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index b3034da..c7fe9f6 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -13,6 +13,8 @@
 	compatible = "ti,twl4030";
 	interrupt-controller;
 	#interrupt-cells = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&twl4030_pins>;
 
 	rtc {
 		compatible = "ti,twl4030-rtc";
@@ -92,3 +94,18 @@
 		#pwm-cells = <2>;
 	};
 };
+
+&omap3_pmx_core {
+	/*
+	 * On most OMAP3 platforms, the twl4030 IRQ line is connected
+         * to the SYS_NIRQ line on OMAP.  Therefore, configure the
+         * defaults for the SYS_NIRQ pin here.  Boards that hook up
+         * the twl4030 differently can easily override this in their
+         * board-specific DTS file.
+	 */
+	twl4030_pins: pinmux_twl4030_pins {
+		pinctrl-single,pins = <
+			0x1b0 0x4118 /*	sys_nirq.sys_nirq WAKEUP | INPUT_PULLUP | MODE 0 */
+		>;
+	};
+};
-- 
1.8.2



From olof at lixom.net  Fri May 31 19:11:40 2013
From: olof at lixom.net (Olof Johansson)
Date: Fri, 31 May 2013 16:11:40 -0700
Subject: [PATCH 3/3] at_hdmac: add FIFO configuration parameter to DMA DT
 binding
In-Reply-To: <51A86DF5.4010808@atmel.com>
References: <1369930103-11963-1-git-send-email-ludovic.desroches@atmel.com>
 <1369930103-11963-4-git-send-email-ludovic.desroches@atmel.com>
 <51A77F10.8020808@atmel.com>
 <20130530163936.GC23653@game.jcrosoft.org>
 <51A86DF5.4010808@atmel.com>
Message-ID: <CAOesGMhQetZfyzMpCax63xoRqtRW2ZRXt04MCbgCT-CcvUq43A@mail.gmail.com>

On Fri, May 31, 2013 at 2:31 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> On 31/05/2013 11:16, Ludovic Desroches :
>>
>> On Thu, May 30, 2013 at 06:39:36PM +0200, Jean-Christophe PLAGNIOL-VILLARD
>> wrote:
>>>
>>> On 18:32 Thu 30 May     , Nicolas Ferre wrote:
>>>>
>>>> On 30/05/2013 18:08, ludovic.desroches at atmel.com :
>>>>>
>>>>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>>>>
>>>>> For most devices the FIFO configuration is the same i.e. when half FIFO
>>>>> size is
>>>>> available/filled, a source/destination request is serviced. But USART
>>>>> devices
>>>>> have to do it when there is enough space/data available to perform a
>>>>> single
>>>>> AHB access so the ASAP configuration.
>>>>>
>>>>> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>>>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>>>>
>>>>
>>>> Clear and neat: thanks Ludo.
>>>
>>>
>>> agreed
>>>
>>> can we apply this via AT91 as this depends on some cleanup I did on DT
>>> and
>>> could result on some nigthmware conflict
>>>
>>
>> In fact, I am not sure it's the best solution. I have noticed that there
>> is a
>> conflict with a patch sent by Nicolas (dmaengine: at_hdmac: extend
>> hardware
>> handshaking interface identification) which is already in Vinod's tree but
>> which is not present on Jean-Christophe's cleanup tree on which I based
>> these
>> patches.
>>
>> Moreover this patch doesn't use macros introduced by Nicolas' patch. I may
>> update it and it should go through Vinod's tree with a dependence on patch
>> 1/3.
>>
>> What's your point of view?
>
>
> Indeed. Another option could be to push patches 1 and 3 in dmaengine's tree
> and make the 2nd patch go through arm-soc with a dependency on slave-dma GIT
> tree (it seems it is an usual patern).
>
> Arnd, Jean-Christophe, what do you think?

I'm not sure patch 1 needs to go through the dma-engine tree? Sure,
it's a dma-related header file but it's only used to craft the device
tree in patch 2, it doesn't affect the driver.

(Arnd has comments on the patch that should be resolved though).


-Olof


From aaro.koskinen at iki.fi  Fri May 31 19:34:58 2013
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Sat, 1 Jun 2013 02:34:58 +0300
Subject: [PATCH 03/15] drm/nouveau: use mdelay instead of large udelay
 constants
In-Reply-To: <1370038972-2318779-4-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
 <1370038972-2318779-4-git-send-email-arnd@arndb.de>
Message-ID: <20130531233458.GD3345@blackmetal.musicnaut.iki.fi>

Hi,

On Sat, Jun 01, 2013 at 12:22:40AM +0200, Arnd Bergmann wrote:
> ARM cannot handle udelay for more than 2 miliseconds, so we
                                           ^^^^

                                 There's l missing here.

> should use mdelay instead for those.

Could this be handled inside ARM udelay() instead? Probably most of the
delay values are compile-time constants.

A.


From benh at kernel.crashing.org  Fri May 31 19:40:30 2013
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sat, 01 Jun 2013 09:40:30 +1000
Subject: [PATCH v2] can: flexcan: remove HAVE_CAN_FLEXCAN Kconfig symbol
In-Reply-To: <519A4A00.8000109@pengutronix.de>
References: <1368781157-4646-1-git-send-email-mkl@pengutronix.de>
 <20130517090949.GI8607@S2101-09.ap.freescale.net>
 <519A4A00.8000109@pengutronix.de>
Message-ID: <1370043630.3928.166.camel@pasglop>

On Mon, 2013-05-20 at 18:06 +0200, Marc Kleine-Budde wrote:
> On 05/17/2013 11:09 AM, Shawn Guo wrote:
> > On Fri, May 17, 2013 at 10:59:17AM +0200, Marc Kleine-Budde wrote:
> >> This patch removes the Kconfig symbol HAVE_CAN_FLEXCAN from arch/{arm,powerpc}
> >> and allowing compilation unconditionally on all arm and powerpc platforms.
> >>
> >> This brings a bigger compile time coverage and removes the following dependency
> >> warning found by Arnd Bergmann:
> >>
> >>     warning: (SOC_IMX28 && SOC_IMX25 && SOC_IMX35 && IMX_HAVE_PLATFORM_FLEXCAN &&
> >>         SOC_IMX53 && SOC_IMX6Q) selects HAVE_CAN_FLEXCAN
> >>     which has unmet direct dependencies (NET && CAN && CAN_DEV)
> >>
> >> Cc: Arnd Bergmann <arnd at arndb.de>
> >> Cc: Shawn Guo <shawn.guo at linaro.org>
> > 
> > Acked-by: Shawn Guo <shawn.guo at linaro.org>
> 
> Thanks.
> 
> An Acked-by by the powerpc people would be fine. However, if nobody
> doesn't object, I'm sending this patch via linux-can and net-next upstream.

Sorry, missed it, if it's still out there, add my

Acked-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>

Cheers,
Ben.



From swarren at wwwdotorg.org  Fri May 31 19:46:19 2013
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 31 May 2013 17:46:19 -0600
Subject: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
In-Reply-To: <201306010041.07230.arnd@arndb.de>
References: <1369046369-12489-1-git-send-email-josephl@nvidia.com>
 <1369046369-12489-4-git-send-email-josephl@nvidia.com>
 <201306010041.07230.arnd@arndb.de>
Message-ID: <51A9364B.4090002@wwwdotorg.org>

On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> On Monday 20 May 2013, Joseph Lo wrote:
>> +       cpu_to_csr_req r1, r0
>> +       mov32   r2, TEGRA_FLOW_CTRL_BASE
>> +       ldr     r1, [r2, r1]
> 
> This causes build errors now, since cpu_to_csr_req is not defined anywhere.

What build error are you seeing? I built next-20130531 earlier today
without any issue.

I do remember making a similar comment during review of this patch that
cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
another patch in the series which had added it, or something like that.


From john.stultz at linaro.org  Fri May 31 19:50:04 2013
From: john.stultz at linaro.org (John Stultz)
Date: Fri, 31 May 2013 16:50:04 -0700
Subject: [PATCH 5/4] sched: Make ARM's sched_clock generic for all
 architectures
In-Reply-To: <20130531221358.GF599@codeaurora.org>
References: <1366417746-24990-1-git-send-email-sboyd@codeaurora.org>
 <1367369675-13535-1-git-send-email-sboyd@codeaurora.org>
 <51A90ACE.7070906@linaro.org> <20130531221358.GF599@codeaurora.org>
Message-ID: <51A9372C.8060107@linaro.org>

On 05/31/2013 03:13 PM, Stephen Boyd wrote:
> On 05/31, John Stultz wrote:
>> On 04/30/2013 05:54 PM, Stephen Boyd wrote:
>>> Here's the patch to make sched_clock generic. I didn't know
>>> where to put it so I just made a new file in kernel/sched
>>> for now.
>>>
>>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
>> Hey Stephen,
>>      Baruch just asked a question about moving arm's sched_clock.c to
>> be generic, and it sounded familiar, so I dug around and found this
>> mail from a few months ago.
>>
>> Just wanted to follow up and see what the status is with this? Is
>> this queued somewhere already?
>>
> As far as I know nothing has been queued. I refreshed the
> patchset against 3.10-rc2 but haven't sent it out since it wasn't
> clear if anyone wanted it. Shall I send it again?

Please. Even if it need an eventual deeper rework to be totally generic, 
I think we need to start moving things in that generic direction. 
Baruch's case is a clear example where non-arm code could share it, so I 
think that's at least a good proof point that sharing is actually needed 
(rather then just for theoretical reasons).

thanks
-john



From horms at verge.net.au  Fri May 31 20:00:18 2013
From: horms at verge.net.au (Simon Horman)
Date: Sat, 1 Jun 2013 09:00:18 +0900
Subject: [PATCH 1/2] sh-pfc: r8a7779: Don't group USB OVC and PENC pins
In-Reply-To: <CACRpkda9tjydo038exS2a=Gsvum41LyvXd=GwKh3b0Zi4rOA9g@mail.gmail.com>
References: <1369866529-6372-1-git-send-email-horms+renesas@verge.net.au>
 <1369866529-6372-2-git-send-email-horms+renesas@verge.net.au>
 <CACRpkdZxWsJuvrtH-=VVqAGUCpdgS3W52R4tw5-_QGpggB+1uw@mail.gmail.com>
 <20130531001735.GA26684@verge.net.au>
 <CAOesGMiTXW0mVmbBbha5S4O64yu_vM=eLxM4JyctsfONCAo4qg@mail.gmail.com>
 <20130531054517.GC5009@verge.net.au>
 <CAOesGMgrdyFi3GMz52CVnhzmOYHbR5=29Ua0iS8cNbSjg6r-2A@mail.gmail.com>
 <CACRpkda9tjydo038exS2a=Gsvum41LyvXd=GwKh3b0Zi4rOA9g@mail.gmail.com>
Message-ID: <20130601000018.GB3673@verge.net.au>

On Fri, May 31, 2013 at 09:21:46AM +0200, Linus Walleij wrote:
> On Fri, May 31, 2013 at 8:11 AM, Olof Johansson <olof at lixom.net> wrote:
> > [Simon]
> >> As an aside, I do expect to send some more v3.10 fixes for shmobile.
> >> There seem to be more than usual.
> >
> > A little unfortunate but it's hard to do much about.
> >
> > Please be conservative with what you pick up for 3.10 vs 3.11 -- Linus
> > has said he really wants to see things slow down.
> 
> What we might need to think about is the evolutional pace of the ARM
> kernel - compared to a few years back we have increased the change
> rate by orders of a magnitude (at least that is my feeling...)
> 
> There may be some point where we actually need to tell people to
> hold changes back because they are just pushing too large volumes
> through one merge window, resulting in a corresponding amount of
> fixes.
> 
> This merge window both Samsung Exynos and SH mobile seem to
> have been a little bit trigger-happy :-/

To quantify things, for shmobile I am currently aware of 4 problems that
seem to be worthy of fixing for v3.10. A patche for one has been
accepted into arm-soc, Patches for two are this pull request. And one more
has a patch in the pipeline.

These known problems seem to fall into two categories:

1. Problems that have been in linux-next for a while but only recently
   appeared in the renesas tree. These were observed when boot testing kernels
   during the course of rebasing the renesas tree on v3.10-rcX.

   I believe that these problems could and should have been
   spotted earlier by boot testing linux-next more often,
   allowing them to be resolved in the merge-window rather than
   at -rc time.

   I intend to make this happen.

2. Problems that have been present in the renesas tree and
   thus linux-next for a while but were not observed as
   early as they might have been.

   Statistically the rate of these problems could have
   been reduced by accepting changes more slowly.
   But at this point we are talking about one or two bugs out
   of many many changes. Bugs that only affect a small
   subset of shmobile hardware support.





From csd at broadcom.com  Fri May 31 20:17:36 2013
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 31 May 2013 17:17:36 -0700
Subject: [PATCH V4 2/3] ARM: mmc: bcm281xx SDHCI driver
In-Reply-To: <87d2s7ceh0.fsf@octavius.laptop.org>
References: <1369860607-25572-1-git-send-email-csd@broadcom.com>
 <1369860607-25572-2-git-send-email-csd@broadcom.com>
 <87d2s7ceh0.fsf@octavius.laptop.org>
Message-ID: <51A93DA0.3070909@broadcom.com>

Hi Chris,
On 13-05-31 09:15 AM, Chris Ball wrote:
>
> Could you investigate replacing this section of code with a call to
> mmc_of_parse(), please?  It should be able to replace your parsing
> and handling of bus-width, cd-gpios, wp-gpios, and non-removable
> (other than the initialization quirks specific to your hardware).
>
> I'd like to avoid every driver having its own DT parsing.
> Thanks,
>
> - Chris.
I looked into it and it can replace just about everything that our own 
dt parsing code is doing. The only problem is with cd_gpio. If I call 
mmc_of_parse, then it will install its own irq handler for cd gpio, and 
our driver needs a different handler. the mmc irq handler can call a 
card_event callback, but that is already pointing to sdhci_card_event. 
So the only way I can use mmc_of_parse that I can see is by adding a 
flag to it to skip cd_gpio parsing which only this driver will then set 
to true. Any other ideas ?

  Thanks,
    csd




From davem at davemloft.net  Fri May 31 20:23:36 2013
From: davem at davemloft.net (David Miller)
Date: Fri, 31 May 2013 17:23:36 -0700 (PDT)
Subject: [PATCHv4 0/6] ARM: sunxi: Add support for A10 Ethernet controller
In-Reply-To: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1369921765-3367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20130531.172336.1848458955586893446.davem@davemloft.net>

From: Maxime Ripard <maxime.ripard at free-electrons.com>
Date: Thu, 30 May 2013 15:49:19 +0200

> The Allwinner A10 SoC has an ethernet controller that seem to be specific to
> Allwinner. This IP has no public documentation, so exact
> details are quite sparse, and this code come from refactored Allwinner
> code.
> 
> The rework to use NAPI is taking more time than expected, I'm still working
> on it, but it could probably be sent as a follow-up patch.

Looks good.

All applied to net-next, thanks.


From stepanm at codeaurora.org  Fri May 31 21:30:52 2013
From: stepanm at codeaurora.org (Stepan Moskovchenko)
Date: Fri, 31 May 2013 18:30:52 -0700
Subject: [PATCH] arm: Prevent memory aliasing on non-LPAE kernels
In-Reply-To: <3054064.aJsgTxiNUL@wuerfel>
References: <1369950320-22784-1-git-send-email-stepanm@codeaurora.org>
 <3054064.aJsgTxiNUL@wuerfel>
Message-ID: <51A94ECC.5090303@codeaurora.org>

On 5/30/2013 3:24 PM, Arnd Bergmann wrote:
>> +       if (size > ((phys_addr_t)~0))
>> +               size = ((phys_addr_t)~0);
>> +
>> +       /* arm_add_memory() already checks for the case of base + size > 4GB */
>> +#endif
>>          arm_add_memory(base, size);
>>   }
>
> This looks wrong for the case where 'base' is between >0 and 4GB and 'size'
> makes it spill over the 4GB boundary. You need to set
> 'size = (phys_addr_t)~0 - base' then.
>

Ah. I believe arm_add_memory() already has the logic to handle this 
case. Here, we are just trying to shrink 'size' to fit into phys_addr_t, 
since it is currently u64 but arm_add_memory() uses phys_addr_t for its 
arguments. I did not want to have this logic in two places, but I can do 
what you said if you like.


-- 
  The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
  hosted by The Linux Foundation


From viresh.kumar at linaro.org  Fri May 31 21:58:01 2013
From: viresh.kumar at linaro.org (Viresh Kumar)
Date: Sat, 1 Jun 2013 07:28:01 +0530
Subject: [PATCH 07/15] cpufreq: spear needs cpufreq table
In-Reply-To: <1370038972-2318779-8-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
 <1370038972-2318779-8-git-send-email-arnd@arndb.de>
Message-ID: <CAKohpomzoGsOoQ__fd0V651bjWt2=JTC10wGSQzX2yyTcWZmvA@mail.gmail.com>

On 1 June 2013 03:52, Arnd Bergmann <arnd at arndb.de> wrote:
> Like a lot of the other cpufreq drivers, this one needs to
> select CONFIG_CPU_FREQ_TABLE to avoid a build error like
>
> drivers/built-in.o: In function `spear_cpufreq_exit':
> spear-cpufreq.c:198: undefined reference to `cpufreq_frequency_table_put_attr'
> drivers/built-in.o: In function `spear_cpufreq_verify':
> spear-cpufreq.c:35: undefined reference to `cpufreq_frequency_table_verify'
> drivers/built-in.o: In function `spear_cpufreq_init':
> spear-cpufreq.c:181: undefined reference to `cpufreq_frequency_table_cpuinfo'
> spear-cpufreq.c:187: undefined reference to `cpufreq_frequency_table_get_attr'
> drivers/built-in.o: In function `spear_cpufreq_target':
> spear-cpufreq.c:120: undefined reference to `cpufreq_frequency_table_target'
> drivers/built-in.o:(.data+0x5e63c): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Viresh Kumar <viresh.kumar at linaro.org>
> Cc: cpufreq at vger.kernel.org
> Cc: linux-pm at vger.kernel.org
> ---
>  drivers/cpufreq/Kconfig.arm | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Viresh Kumar <viresh.kumar at linaro.org>

BTW, you want me to apply this one or take it through arm-soc tree?


From elezegarcia at gmail.com  Fri May 31 22:17:48 2013
From: elezegarcia at gmail.com (Ezequiel Garcia)
Date: Fri, 31 May 2013 23:17:48 -0300
Subject: [PATCH 07/15] cpufreq: spear needs cpufreq table
In-Reply-To: <1370038972-2318779-8-git-send-email-arnd@arndb.de>
References: <1370038972-2318779-1-git-send-email-arnd@arndb.de>
 <1370038972-2318779-8-git-send-email-arnd@arndb.de>
Message-ID: <CALF0-+XYhpLaJLSZqamuV0aQFwxtu4WS7RNpbU6Li78gmMSOWw@mail.gmail.com>

On Fri, May 31, 2013 at 7:22 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> Like a lot of the other cpufreq drivers, this one needs to
> select CONFIG_CPU_FREQ_TABLE to avoid a build error like
>

Indeed. I found the same thing while playing with Kirkwood's.

@Andrew, I have a patch sitting here, but feel free to send it if you want.
-- 
    Ezequiel


From olof at lixom.net  Fri May 31 23:59:29 2013
From: olof at lixom.net (Olof Johansson)
Date: Fri, 31 May 2013 20:59:29 -0700
Subject: [PATCH 1/3] ARM: EXYNOS: uncompress - print debug messages if
 DEBUG_LL is defined
In-Reply-To: <1370000944-19786-2-git-send-email-tushar.behera@linaro.org>
References: <1370000944-19786-1-git-send-email-tushar.behera@linaro.org>
 <1370000944-19786-2-git-send-email-tushar.behera@linaro.org>
Message-ID: <20130601035929.GA3868@quad.lixom.net>

On Fri, May 31, 2013 at 05:19:02PM +0530, Tushar Behera wrote:
> Printing low-level debug messages make an assumption that the specified
> UART port has been preconfigured by the bootloader. Incorrectly
> specified UART port results in system getting stalled while printing the
> message "Uncompressing Linux... done, booting the kernel"
> 
> This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since
> the UART port might different for different board, it is not possible to
> specify it correctly for every board that use a common defconfig file.
> 
> Calling this print subroutine only when DEBUG_LL fixes the problem. By
> disabling DEBUG_LL in default config file, we would be able to boot
> multiple boards with different default UART ports.
> 
> With this current approach, we miss the print "Uncompressing Linux...
> done, booting the kernel." when DEBUG_LL is not defined.
> 
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
> ---
>  arch/arm/mach-exynos/include/mach/uncompress.h  |   11 ++++++++---
>  arch/arm/plat-samsung/include/plat/uncompress.h |   10 +++++++++-
>  2 files changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
> index 2979995..730f69f 100644
> --- a/arch/arm/mach-exynos/include/mach/uncompress.h
> +++ b/arch/arm/mach-exynos/include/mach/uncompress.h
> @@ -37,11 +37,16 @@ static void arch_detect_cpu(void)
>  	chip_id >>= 20;
>  	chip_id &= 0xf;
>  
> +#ifdef CONFIG_DEBUG_LL
>  	if (chip_id == 0x5)
> -		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
> +		uart_base = (volatile u8 *)EXYNOS5_PA_UART +
> +			(S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
>  	else
> -		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
> -
> +		uart_base = (volatile u8 *)EXYNOS4_PA_UART +
> +			(S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
> +#else
> +	uart_base = NULL;
> +#endif

You can do:

	if (!config_enabled(CONFIG_DEBUG_LL))
		return;

Since uart_base will be set to 0 by being in BSS anyway.


-Olof


